data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv
1: b'%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:18: Cannot find include file: axi/assign.svh\n`include "axi/assign.svh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test,data/full_repos/permissive/489147019/axi/assign.svh\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test,data/full_repos/permissive/489147019/axi/assign.svh.v\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test,data/full_repos/permissive/489147019/axi/assign.svh.sv\n             axi/assign.svh\n             axi/assign.svh.v\n             axi/assign.svh.sv\n             obj_dir/axi/assign.svh\n             obj_dir/axi/assign.svh.v\n             obj_dir/axi/assign.svh.sv\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:41: Unsupported: classes\n  class ax_transfer;\n  ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:43: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n    rand axi_pkg::len_t   len   = \'0;\n         ^~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:52: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n  localparam time CyclTime = 10ns;\n                             ^~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:53: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n  localparam time ApplTime =  2ns;\n                              ^~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:54: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n  localparam time TestTime =  8ns;\n                              ^~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:56: syntax error, unexpected ::, expecting \'.\' or \';\'\n  typedef axi_test::axi_rand_master #(\n                  ^~\n                                                                                                  : ... Perhaps \'axi_test\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:70: syntax error, unexpected ::, expecting \'.\' or \';\'\n  typedef axi_test::axi_rand_slave #(\n                  ^~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:100: Define or directive not defined: \'`AXI_ASSIGN\'\n  `AXI_ASSIGN(slave_dv, master_dv)\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:100: syntax error, unexpected \'(\'\n  `AXI_ASSIGN(slave_dv, master_dv)\n              ^~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:114: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n    automatic axi_rand_master_t axi_rand_master = new(master_dv);\n              ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:116: syntax error, unexpected ::, expecting \')\'\n    axi_rand_master.add_memory_region(16\'h0000, 16\'hFFFF, axi_pkg::DEVICE_NONBUFFERABLE);\n                                                                 ^~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:117: syntax error, unexpected ::, expecting \')\'\n    axi_rand_master.add_memory_region(16\'h0000, 16\'hFFFF, axi_pkg::WTHRU_NOALLOCATE);\n                                                                 ^~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:118: syntax error, unexpected ::, expecting \')\'\n    axi_rand_master.add_memory_region(16\'h0000, 16\'hFFFF, axi_pkg::WBACK_RWALLOCATE);\n                                                                 ^~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:120: syntax error, unexpected \'@\'\n    @(posedge rst_n);\n    ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:123: syntax error, unexpected \'@\'\n    repeat (10000) @(posedge clk);\n                   ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:128: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n    automatic axi_rand_slave_t  axi_rand_slave  = new(slave_dv);\n              ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:130: syntax error, unexpected \'@\'\n    @(posedge rst_n);\n    ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:140: syntax error, unexpected \'@\'\n    @(posedge rst_n);\n    ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:143: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:144: Unsupported: Ignoring delay on this delayed statement.\n      #TestTime;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:184: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:185: Unsupported: Ignoring delay on this delayed statement.\n      #TestTime;\n      ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:202: Unsupported: wait statements\n      wait (ax_queue.size());\n      ^~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:212: syntax error, unexpected ::, expecting \';\'\n        test_addr = axi_pkg::beat_addr(ax_beat.addr, ax_beat.size, ax_beat.len, ax_beat.burst, i);\n                           ^~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:229: syntax error, unexpected ::, expecting \')\'\n      int unsigned burst_length, axi_pkg::burst_t mode);\n                                        ^~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:240: syntax error, unexpected \'(\', expecting \'#\' or final\n    assume (mode inside {axi_pkg::BURST_FIXED, axi_pkg::BURST_INCR, axi_pkg::BURST_WRAP});\n            ^~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:246: syntax error, unexpected ::\n    if (mode == axi_pkg::BURST_WRAP) begin\n                       ^~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:254: syntax error, unexpected ::\n      if (mode != axi_pkg::BURST_FIXED) begin\n                         ^~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_addr_test.sv:272: syntax error, unexpected ::, expecting \',\' or \':\'\n      axi_pkg::BURST_FIXED: $display("TYPE: BURST_FIXED");\n             ^~\n%Error: Cannot continue\n'
function automatic void data_transfer(addr_t start_addr, int unsigned num_bytes,
      int unsigned burst_length, axi_pkg::burst_t mode);

    localparam int unsigned large_addr = $bits(addr_t);
    typedef logic [large_addr:0] laddr_t;

    laddr_t      addr;
    laddr_t      aligned_addr;
    bit          aligned;
    int unsigned dtsize;
    laddr_t      lower_wrap_boundary;
    laddr_t      upper_wrap_boundary;
    assume (mode inside {axi_pkg::BURST_FIXED, axi_pkg::BURST_INCR, axi_pkg::BURST_WRAP});
    addr         = laddr_t'(start_addr);
    aligned_addr = laddr_t'((addr / num_bytes) * num_bytes);
    aligned      = (aligned_addr == addr);
    dtsize       = num_bytes * burst_length;

    if (mode == axi_pkg::BURST_WRAP) begin
      lower_wrap_boundary = laddr_t'((addr / dtsize) * dtsize);
      upper_wrap_boundary = lower_wrap_boundary + dtsize;
    end

    for (int unsigned n = 1; n <= burst_length; n++) begin
      gold_addr.push_back(addr_t'(addr));

      if (mode != axi_pkg::BURST_FIXED) begin
        if (aligned) begin
          addr += num_bytes;
        end else begin
          addr    = aligned_addr + num_bytes;
          aligned = 1'b1;
        end
        if (mode == axi_pkg::BURST_WRAP && (addr >= upper_wrap_boundary)) begin
          addr = lower_wrap_boundary;
        end
      end
    end
  endfunction
function automatic void data_transfer(addr_t start_addr, int unsigned num_bytes,
      int unsigned burst_length, axi_pkg::burst_t mode);


    localparam int unsigned large_addr = $bits(addr_t);
    typedef logic [large_addr:0] laddr_t;

    laddr_t      addr;
    laddr_t      aligned_addr;
    bit          aligned;
    int unsigned dtsize;
    laddr_t      lower_wrap_boundary;
    laddr_t      upper_wrap_boundary;
    assume (mode inside {axi_pkg::BURST_FIXED, axi_pkg::BURST_INCR, axi_pkg::BURST_WRAP});
    addr         = laddr_t'(start_addr);
    aligned_addr = laddr_t'((addr / num_bytes) * num_bytes);
    aligned      = (aligned_addr == addr);
    dtsize       = num_bytes * burst_length;

    if (mode == axi_pkg::BURST_WRAP) begin
      lower_wrap_boundary = laddr_t'((addr / dtsize) * dtsize);
      upper_wrap_boundary = lower_wrap_boundary + dtsize;
    end

    for (int unsigned n = 1; n <= burst_length; n++) begin
      gold_addr.push_back(addr_t'(addr));

      if (mode != axi_pkg::BURST_FIXED) begin
        if (aligned) begin
          addr += num_bytes;
        end else begin
          addr    = aligned_addr + num_bytes;
          aligned = 1'b1;
        end
        if (mode == axi_pkg::BURST_WRAP && (addr >= upper_wrap_boundary)) begin
          addr = lower_wrap_boundary;
        end
      end
    end
  endfunction