data/full_repos/permissive/424292861/guia8/ALU.v
1: b"%Error: data/full_repos/permissive/424292861/guia8/ALU.v:60: syntax error, unexpected '=', expecting IDENTIFIER\n s1 = and1;\n    ^\n%Error: data/full_repos/permissive/424292861/guia8/ALU.v:106: syntax error, unexpected '=', expecting IDENTIFIER\n soma = 5'b0001;\n      ^\n%Error: Exiting due to 2 error(s)\n"
module halfsum(a,b,s0,s1);
	input a;
	input b;
	output s0;
	output s1;
	reg s0;
	reg s1;
	wire nota;
	wire notb;
	wire andb1;
	wire andb2;
	not NOT1(nota,a);
	not NOT2(notb,b);
	and AND1(s1,a,b);
	and AND2(andb1,nota,b);
	and AND3(andb2,a,notb);
	or  OR(s1,andb1,andb2);
endmodule
module halfsum(a,b,s0,s1);

	input a;
	input b;
	output s0;
	output s1;
	reg s0;
	reg s1;
	wire nota;
	wire notb;
	wire andb1;
	wire andb2;
	not NOT1(nota,a);
	not NOT2(notb,b);
	and AND1(s1,a,b);
	and AND2(andb1,nota,b);
	and AND3(andb2,a,notb);
	or  OR(s1,andb1,andb2);
endmodule