data/full_repos/permissive/506562943/HDLBits/Verilog Language/Modules/module.v
1: b'%Error: Cannot find file containing module: Language/Modules,data/full_repos/permissive/506562943\n        ... Looked in:\n             data/full_repos/permissive/506562943/HDLBits/Verilog/Language/Modules,data/full_repos/permissive/506562943\n             data/full_repos/permissive/506562943/HDLBits/Verilog/Language/Modules,data/full_repos/permissive/506562943.v\n             data/full_repos/permissive/506562943/HDLBits/Verilog/Language/Modules,data/full_repos/permissive/506562943.sv\n             Language/Modules,data/full_repos/permissive/506562943\n             Language/Modules,data/full_repos/permissive/506562943.v\n             Language/Modules,data/full_repos/permissive/506562943.sv\n             obj_dir/Language/Modules,data/full_repos/permissive/506562943\n             obj_dir/Language/Modules,data/full_repos/permissive/506562943.v\n             obj_dir/Language/Modules,data/full_repos/permissive/506562943.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/506562943/HDLBits/Verilog\n%Error: Cannot find file containing module: Language/Modules/module.v\n%Error: Exiting due to 3 error(s)\n'
module top_module ( input a, input b, output out );


    mod_a u_mod_a(a, b, out);
    

    mod_a u_mod_a(
        .in2(b),
        .in1(a),
        .out(out)
    );
    
endmodule
module top_module ( input a, input b, output out );



    mod_a u_mod_a(a, b, out);
    

    mod_a u_mod_a(
        .in2(b),
        .in1(a),
        .out(out)
    );
    
endmodule