data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv
1: b'%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:51: Cannot find include file: common_cells/registers.svh\n  `include "common_cells/registers.svh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl,data/full_repos/permissive/489147019/common_cells/registers.svh\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl,data/full_repos/permissive/489147019/common_cells/registers.svh.v\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl,data/full_repos/permissive/489147019/common_cells/registers.svh.sv\n             common_cells/registers.svh\n             common_cells/registers.svh.v\n             common_cells/registers.svh.sv\n             obj_dir/common_cells/registers.svh\n             obj_dir/common_cells/registers.svh.v\n             obj_dir/common_cells/registers.svh.sv\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:860: Cannot find include file: mempool/mempool.svh\n`include "mempool/mempool.svh" \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:7: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER\n  import mempool_pkg::*;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:15: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter int unsigned NumCaches    = NumCoresPerTile / NumCoresPerCache\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:16: syntax error, unexpected \')\', expecting \';\'\n) (\n^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:19: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input  logic                                        rst_ni,\n  ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:21: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input  logic                                        scan_enable_i,\n  ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:22: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input  logic                                        scan_data_i,\n  ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:23: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output logic                                        scan_data_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:25: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input  logic              [idx_width(NumTiles)-1:0] tile_id_i,\n  ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:27: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output tcdm_master_req_t  [NumGroups-1:0]           tcdm_master_req_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:29: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input  logic              [NumGroups-1:0]           tcdm_master_req_ready_i,\n  ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:30: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input  tcdm_master_resp_t [NumGroups-1:0]           tcdm_master_resp_i,\n  ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:32: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output logic              [NumGroups-1:0]           tcdm_master_resp_ready_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:34: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input  tcdm_slave_req_t   [NumGroups-1:0]           tcdm_slave_req_i,\n  ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:36: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output logic              [NumGroups-1:0]           tcdm_slave_req_ready_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:37: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output tcdm_slave_resp_t  [NumGroups-1:0]           tcdm_slave_resp_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:39: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input  logic              [NumGroups-1:0]           tcdm_slave_resp_ready_i,\n  ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:41: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output axi_tile_req_t                               axi_mst_req_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:45: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:63: syntax error, unexpected IDENTIFIER, expecting \';\'\n  localparam addr_t TCDMSize = NumBanks * TCDMSizePerBank;\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:64: syntax error, unexpected IDENTIFIER, expecting \';\'\n  localparam addr_t TCDMMask = ~(TCDMSize - 1);\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:71: syntax error, unexpected if\n  if (NumGroups != 1) begin: gen_group_id\n  ^~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:88: syntax error, unexpected IDENTIFIER\n  addr_t    [NumCoresPerTile-1:0] snitch_data_qaddr;\n  ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:90: syntax error, unexpected IDENTIFIER\n  amo_t     [NumCoresPerTile-1:0] snitch_data_qamo;\n  ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:96: syntax error, unexpected IDENTIFIER\n  data_t    [NumCoresPerTile-1:0] snitch_data_pdata;\n  ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:98: syntax error, unexpected IDENTIFIER\n  meta_id_t [NumCoresPerTile-1:0] snitch_data_pid;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:102: syntax error, unexpected for\n  for (genvar c = 0; unsigned\'(c) < NumCoresPerTile; c++) begin: gen_cores\n  ^~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:104: syntax error, unexpected assign\n    assign hart_id = {unsigned\'(tile_id_i), c[idx_width(NumCoresPerTile)-1:0]};\n    ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:164: syntax error, unexpected for\n  for (genvar c = 0; unsigned\'(c) < NumCaches; c++) begin: gen_caches\n  ^~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:216: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n    meta_id_t meta_id;\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:225: syntax error, unexpected IDENTIFIER\n  tcdm_slave_req_t         [NumBanksPerTile-1:0] bank_req_payload;\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:228: syntax error, unexpected IDENTIFIER\n  tcdm_slave_resp_t        [NumBanksPerTile-1:0] bank_resp_payload;\n  ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:231: syntax error, unexpected for\n  for (genvar b = 0; unsigned\'(b) < NumBanksPerTile; b++) begin: gen_banks\n  ^~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:236: syntax error, unexpected IDENTIFIER\n    bank_addr_t req_addr;\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:309: syntax error, unexpected IDENTIFIER\n  tcdm_slave_req_t   [NumGroups-1:0] postreg_tcdm_slave_req;\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:312: syntax error, unexpected IDENTIFIER\n  tcdm_slave_resp_t  [NumGroups-1:0] prereg_tcdm_slave_resp;\n  ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:315: syntax error, unexpected IDENTIFIER\n  tcdm_master_resp_t [NumGroups-1:0] postreg_tcdm_master_resp;\n  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:321: syntax error, unexpected for\n  for (genvar h = 0; unsigned\'(h) < NumGroups; h++) begin: gen_tcdm_registers\n  ^~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:390: syntax error, unexpected IDENTIFIER\n  tcdm_master_resp_t [NumCoresPerTile-1:0] remote_resp_interco;\n  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:394: syntax error, unexpected IDENTIFIER\n  stream_xbar #(\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:444: syntax error, unexpected IDENTIFIER\n  tcdm_slave_req_t  [NumCoresPerTile-1:0] local_req_interco_payload;\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:447: syntax error, unexpected IDENTIFIER\n  tcdm_slave_resp_t [NumCoresPerTile-1:0] local_resp_interco_payload;\n  ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:450: syntax error, unexpected for\n  for (genvar j = 0; unsigned\'(j) < NumCoresPerTile; j++) begin: gen_local_req_interco_tgt_sel_local\n  ^~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:509: syntax error, unexpected IDENTIFIER\n  dresp_t [NumCoresPerTile-1:0] soc_data_p;\n  ^~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:518: syntax error, unexpected IDENTIFIER\n  address_map_t [2:0] mask_map;\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:697: syntax error, unexpected assign\n  assign soc_resp_i.id = \'x;\n  ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:863: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER\n  import mempool_pkg::*;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:871: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter int unsigned NumCaches       = NumCoresPerTile / NumCoresPerCache\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/mempool_tile.sv:872: syntax error, unexpected \')\', expecting \';\'\n) (\n^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module mempool_tile_wrap
  import mempool_pkg::*;
  import cf_math_pkg::idx_width;
#(

  parameter addr_t       TCDMBaseAddr    = 32'b0,

  parameter logic [31:0] BootAddr        = 32'h0000_1000,

  parameter int unsigned NumCaches       = NumCoresPerTile / NumCoresPerCache
) (

  input  logic                             clk_i,
  input  logic                             rst_ni,

  input  logic                             scan_enable_i,
  input  logic                             scan_data_i,
  output logic                             scan_data_o,

  input  logic [idx_width(NumTiles)-1:0]   tile_id_i,

  output `STRUCT_PORT(tcdm_master_req_t)   tcdm_master_north_req_o,
  output logic                             tcdm_master_north_req_valid_o,
  input  logic                             tcdm_master_north_req_ready_i,
  input  `STRUCT_PORT(tcdm_master_resp_t)  tcdm_master_north_resp_i,
  input  logic                             tcdm_master_north_resp_valid_i,
  output logic                             tcdm_master_north_resp_ready_o,
  output `STRUCT_PORT(tcdm_master_req_t)   tcdm_master_northeast_req_o,
  output logic                             tcdm_master_northeast_req_valid_o,
  input  logic                             tcdm_master_northeast_req_ready_i,
  input  `STRUCT_PORT(tcdm_master_resp_t)  tcdm_master_northeast_resp_i,
  input  logic                             tcdm_master_northeast_resp_valid_i,
  output logic                             tcdm_master_northeast_resp_ready_o,
  output `STRUCT_PORT(tcdm_master_req_t)   tcdm_master_east_req_o,
  output logic                             tcdm_master_east_req_valid_o,
  input  logic                             tcdm_master_east_req_ready_i,
  input  `STRUCT_PORT(tcdm_master_resp_t)  tcdm_master_east_resp_i,
  input  logic                             tcdm_master_east_resp_valid_i,
  output logic                             tcdm_master_east_resp_ready_o,
  output `STRUCT_PORT(tcdm_master_req_t)   tcdm_master_local_req_o,
  output logic                             tcdm_master_local_req_valid_o,
  input  logic                             tcdm_master_local_req_ready_i,
  input  `STRUCT_PORT(tcdm_master_resp_t)  tcdm_master_local_resp_i,
  input  logic                             tcdm_master_local_resp_valid_i,
  output logic                             tcdm_master_local_resp_ready_o,

  input  `STRUCT_PORT(tcdm_slave_req_t)    tcdm_slave_north_req_i,
  input  logic                             tcdm_slave_north_req_valid_i,
  output logic                             tcdm_slave_north_req_ready_o,
  output `STRUCT_PORT(tcdm_slave_resp_t)   tcdm_slave_north_resp_o,
  output logic                             tcdm_slave_north_resp_valid_o,
  input  logic                             tcdm_slave_north_resp_ready_i,
  input  `STRUCT_PORT(tcdm_slave_req_t)    tcdm_slave_northeast_req_i,
  input  logic                             tcdm_slave_northeast_req_valid_i,
  output logic                             tcdm_slave_northeast_req_ready_o,
  output `STRUCT_PORT(tcdm_slave_resp_t)   tcdm_slave_northeast_resp_o,
  output logic                             tcdm_slave_northeast_resp_valid_o,
  input  logic                             tcdm_slave_northeast_resp_ready_i,
  input  `STRUCT_PORT(tcdm_slave_req_t)    tcdm_slave_east_req_i,
  input  logic                             tcdm_slave_east_req_valid_i,
  output logic                             tcdm_slave_east_req_ready_o,
  output `STRUCT_PORT(tcdm_slave_resp_t)   tcdm_slave_east_resp_o,
  output logic                             tcdm_slave_east_resp_valid_o,
  input  logic                             tcdm_slave_east_resp_ready_i,
  input  `STRUCT_PORT(tcdm_slave_req_t)    tcdm_slave_local_req_i,
  input  logic                             tcdm_slave_local_req_valid_i,
  output logic                             tcdm_slave_local_req_ready_o,
  output `STRUCT_PORT(tcdm_slave_resp_t)   tcdm_slave_local_resp_o,
  output logic                             tcdm_slave_local_resp_valid_o,
  input  logic                             tcdm_slave_local_resp_ready_i,

  output `STRUCT_PORT(axi_tile_req_t)      axi_mst_req_o,
  input  `STRUCT_PORT(axi_tile_resp_t)     axi_mst_resp_i,

  input  logic [NumCoresPerTile-1:0]       wake_up_i
);

  mempool_tile #(
    .TCDMBaseAddr(TCDMBaseAddr),
    .BootAddr    (BootAddr    )
  ) i_tile (
    .clk_i                   (clk_i                                                                                                                              ),
    .rst_ni                  (rst_ni                                                                                                                             ),
    .tile_id_i               (tile_id_i                                                                                                                          ),

    .scan_enable_i           (scan_enable_i                                                                                                                      ),
    .scan_data_i             (scan_data_i                                                                                                                        ),
    .scan_data_o             (scan_data_o                                                                                                                        ),

    .tcdm_master_req_o       ({tcdm_master_northeast_req_o, tcdm_master_north_req_o, tcdm_master_east_req_o, tcdm_master_local_req_o}                            ),
    .tcdm_master_req_ready_i ({tcdm_master_northeast_req_ready_i, tcdm_master_north_req_ready_i, tcdm_master_east_req_ready_i, tcdm_master_local_req_ready_i}    ),
    .tcdm_master_req_valid_o ({tcdm_master_northeast_req_valid_o, tcdm_master_north_req_valid_o, tcdm_master_east_req_valid_o, tcdm_master_local_req_valid_o}    ),
    .tcdm_master_resp_i      ({tcdm_master_northeast_resp_i, tcdm_master_north_resp_i, tcdm_master_east_resp_i, tcdm_master_local_resp_i}                        ),
    .tcdm_master_resp_ready_o({tcdm_master_northeast_resp_ready_o, tcdm_master_north_resp_ready_o, tcdm_master_east_resp_ready_o, tcdm_master_local_resp_ready_o}),
    .tcdm_master_resp_valid_i({tcdm_master_northeast_resp_valid_i, tcdm_master_north_resp_valid_i, tcdm_master_east_resp_valid_i, tcdm_master_local_resp_valid_i}),

    .tcdm_slave_req_i        ({tcdm_slave_northeast_req_i, tcdm_slave_north_req_i, tcdm_slave_east_req_i, tcdm_slave_local_req_i}                                ),
    .tcdm_slave_req_ready_o  ({tcdm_slave_northeast_req_ready_o, tcdm_slave_north_req_ready_o, tcdm_slave_east_req_ready_o, tcdm_slave_local_req_ready_o}        ),
    .tcdm_slave_req_valid_i  ({tcdm_slave_northeast_req_valid_i, tcdm_slave_north_req_valid_i, tcdm_slave_east_req_valid_i, tcdm_slave_local_req_valid_i}        ),
    .tcdm_slave_resp_o       ({tcdm_slave_northeast_resp_o, tcdm_slave_north_resp_o, tcdm_slave_east_resp_o, tcdm_slave_local_resp_o}                            ),
    .tcdm_slave_resp_ready_i ({tcdm_slave_northeast_resp_ready_i, tcdm_slave_north_resp_ready_i, tcdm_slave_east_resp_ready_i, tcdm_slave_local_resp_ready_i}    ),
    .tcdm_slave_resp_valid_o ({tcdm_slave_northeast_resp_valid_o, tcdm_slave_north_resp_valid_o, tcdm_slave_east_resp_valid_o, tcdm_slave_local_resp_valid_o}    ),

    .axi_mst_req_o           (axi_mst_req_o                                                                                                                      ),
    .axi_mst_resp_i          (axi_mst_resp_i                                                                                                                     ),

    .wake_up_i               (wake_up_i                                                                                                                          )
  );

endmodule
module mempool_tile_wrap
  import mempool_pkg::*;

  import cf_math_pkg::idx_width;
#(

  parameter addr_t       TCDMBaseAddr    = 32'b0,

  parameter logic [31:0] BootAddr        = 32'h0000_1000,

  parameter int unsigned NumCaches       = NumCoresPerTile / NumCoresPerCache
) (

  input  logic                             clk_i,
  input  logic                             rst_ni,

  input  logic                             scan_enable_i,
  input  logic                             scan_data_i,
  output logic                             scan_data_o,

  input  logic [idx_width(NumTiles)-1:0]   tile_id_i,

  output `STRUCT_PORT(tcdm_master_req_t)   tcdm_master_north_req_o,
  output logic                             tcdm_master_north_req_valid_o,
  input  logic                             tcdm_master_north_req_ready_i,
  input  `STRUCT_PORT(tcdm_master_resp_t)  tcdm_master_north_resp_i,
  input  logic                             tcdm_master_north_resp_valid_i,
  output logic                             tcdm_master_north_resp_ready_o,
  output `STRUCT_PORT(tcdm_master_req_t)   tcdm_master_northeast_req_o,
  output logic                             tcdm_master_northeast_req_valid_o,
  input  logic                             tcdm_master_northeast_req_ready_i,
  input  `STRUCT_PORT(tcdm_master_resp_t)  tcdm_master_northeast_resp_i,
  input  logic                             tcdm_master_northeast_resp_valid_i,
  output logic                             tcdm_master_northeast_resp_ready_o,
  output `STRUCT_PORT(tcdm_master_req_t)   tcdm_master_east_req_o,
  output logic                             tcdm_master_east_req_valid_o,
  input  logic                             tcdm_master_east_req_ready_i,
  input  `STRUCT_PORT(tcdm_master_resp_t)  tcdm_master_east_resp_i,
  input  logic                             tcdm_master_east_resp_valid_i,
  output logic                             tcdm_master_east_resp_ready_o,
  output `STRUCT_PORT(tcdm_master_req_t)   tcdm_master_local_req_o,
  output logic                             tcdm_master_local_req_valid_o,
  input  logic                             tcdm_master_local_req_ready_i,
  input  `STRUCT_PORT(tcdm_master_resp_t)  tcdm_master_local_resp_i,
  input  logic                             tcdm_master_local_resp_valid_i,
  output logic                             tcdm_master_local_resp_ready_o,

  input  `STRUCT_PORT(tcdm_slave_req_t)    tcdm_slave_north_req_i,
  input  logic                             tcdm_slave_north_req_valid_i,
  output logic                             tcdm_slave_north_req_ready_o,
  output `STRUCT_PORT(tcdm_slave_resp_t)   tcdm_slave_north_resp_o,
  output logic                             tcdm_slave_north_resp_valid_o,
  input  logic                             tcdm_slave_north_resp_ready_i,
  input  `STRUCT_PORT(tcdm_slave_req_t)    tcdm_slave_northeast_req_i,
  input  logic                             tcdm_slave_northeast_req_valid_i,
  output logic                             tcdm_slave_northeast_req_ready_o,
  output `STRUCT_PORT(tcdm_slave_resp_t)   tcdm_slave_northeast_resp_o,
  output logic                             tcdm_slave_northeast_resp_valid_o,
  input  logic                             tcdm_slave_northeast_resp_ready_i,
  input  `STRUCT_PORT(tcdm_slave_req_t)    tcdm_slave_east_req_i,
  input  logic                             tcdm_slave_east_req_valid_i,
  output logic                             tcdm_slave_east_req_ready_o,
  output `STRUCT_PORT(tcdm_slave_resp_t)   tcdm_slave_east_resp_o,
  output logic                             tcdm_slave_east_resp_valid_o,
  input  logic                             tcdm_slave_east_resp_ready_i,
  input  `STRUCT_PORT(tcdm_slave_req_t)    tcdm_slave_local_req_i,
  input  logic                             tcdm_slave_local_req_valid_i,
  output logic                             tcdm_slave_local_req_ready_o,
  output `STRUCT_PORT(tcdm_slave_resp_t)   tcdm_slave_local_resp_o,
  output logic                             tcdm_slave_local_resp_valid_o,
  input  logic                             tcdm_slave_local_resp_ready_i,

  output `STRUCT_PORT(axi_tile_req_t)      axi_mst_req_o,
  input  `STRUCT_PORT(axi_tile_resp_t)     axi_mst_resp_i,

  input  logic [NumCoresPerTile-1:0]       wake_up_i
);

  mempool_tile #(
    .TCDMBaseAddr(TCDMBaseAddr),
    .BootAddr    (BootAddr    )
  ) i_tile (
    .clk_i                   (clk_i                                                                                                                              ),
    .rst_ni                  (rst_ni                                                                                                                             ),
    .tile_id_i               (tile_id_i                                                                                                                          ),

    .scan_enable_i           (scan_enable_i                                                                                                                      ),
    .scan_data_i             (scan_data_i                                                                                                                        ),
    .scan_data_o             (scan_data_o                                                                                                                        ),

    .tcdm_master_req_o       ({tcdm_master_northeast_req_o, tcdm_master_north_req_o, tcdm_master_east_req_o, tcdm_master_local_req_o}                            ),
    .tcdm_master_req_ready_i ({tcdm_master_northeast_req_ready_i, tcdm_master_north_req_ready_i, tcdm_master_east_req_ready_i, tcdm_master_local_req_ready_i}    ),
    .tcdm_master_req_valid_o ({tcdm_master_northeast_req_valid_o, tcdm_master_north_req_valid_o, tcdm_master_east_req_valid_o, tcdm_master_local_req_valid_o}    ),
    .tcdm_master_resp_i      ({tcdm_master_northeast_resp_i, tcdm_master_north_resp_i, tcdm_master_east_resp_i, tcdm_master_local_resp_i}                        ),
    .tcdm_master_resp_ready_o({tcdm_master_northeast_resp_ready_o, tcdm_master_north_resp_ready_o, tcdm_master_east_resp_ready_o, tcdm_master_local_resp_ready_o}),
    .tcdm_master_resp_valid_i({tcdm_master_northeast_resp_valid_i, tcdm_master_north_resp_valid_i, tcdm_master_east_resp_valid_i, tcdm_master_local_resp_valid_i}),

    .tcdm_slave_req_i        ({tcdm_slave_northeast_req_i, tcdm_slave_north_req_i, tcdm_slave_east_req_i, tcdm_slave_local_req_i}                                ),
    .tcdm_slave_req_ready_o  ({tcdm_slave_northeast_req_ready_o, tcdm_slave_north_req_ready_o, tcdm_slave_east_req_ready_o, tcdm_slave_local_req_ready_o}        ),
    .tcdm_slave_req_valid_i  ({tcdm_slave_northeast_req_valid_i, tcdm_slave_north_req_valid_i, tcdm_slave_east_req_valid_i, tcdm_slave_local_req_valid_i}        ),
    .tcdm_slave_resp_o       ({tcdm_slave_northeast_resp_o, tcdm_slave_north_resp_o, tcdm_slave_east_resp_o, tcdm_slave_local_resp_o}                            ),
    .tcdm_slave_resp_ready_i ({tcdm_slave_northeast_resp_ready_i, tcdm_slave_north_resp_ready_i, tcdm_slave_east_resp_ready_i, tcdm_slave_local_resp_ready_i}    ),
    .tcdm_slave_resp_valid_o ({tcdm_slave_northeast_resp_valid_o, tcdm_slave_north_resp_valid_o, tcdm_slave_east_resp_valid_o, tcdm_slave_local_resp_valid_o}    ),

    .axi_mst_req_o           (axi_mst_req_o                                                                                                                      ),
    .axi_mst_resp_i          (axi_mst_resp_i                                                                                                                     ),

    .wake_up_i               (wake_up_i                                                                                                                          )
  );

endmodule