data/full_repos/permissive/426029503/lcd/lcd.v
data/verilator_xmls/f94c490b-5c82-4e2f-9c87-8f2f24fedae0.xml
module lcd_control(
   input clock,
	input rst,
	input [255:0]data,
	output reg LCD_RS,
	output LCD_RW,
	output LCD_EN,
	output reg [7:0] LCD_DATA,
	output reg check
);
	parameter	INIT_STATE	=	0;
	parameter	LOAD_STATE	=	1;
	parameter	PUSH_STATE	=	2;
	parameter	IDLE_STATE	=	3;
	






	

	
	
	

	

	reg [5:0] index;
	reg [2:0] state;
	
	reg dispClock;
   reg [25:0]counter;

	always @(posedge dispClock or posedge rst) begin
		if (rst == 1'b1) begin
			index <= 0;
			state <= INIT_STATE;
		end
		else begin
			case (state)
				INIT_STATE: begin
					index <= 0;
					state <= LOAD_STATE;
					
				end
				LOAD_STATE: begin
					state <= (index > 36 ? IDLE_STATE : PUSH_STATE);
				
				end
				PUSH_STATE: begin
					index <= index + 1;
					state <= LOAD_STATE;
				end
				IDLE_STATE : begin
					state <= IDLE_STATE;
				end
				default: begin
					index <= 0;
					state <= INIT_STATE;
				end
			endcase
		end
	end

	assign LCD_EN = (state == PUSH_STATE);
	assign LCD_RW = 0;
	
	always @(*) begin
		case (index)
				  0: {LCD_RS, LCD_DATA} = {1'b0, 8'b0011_1000};
				  1: {LCD_RS, LCD_DATA} = {1'b0, 8'b0000_0110};
				  2: {LCD_RS, LCD_DATA} = {1'b0, 8'b0000_0001};

				  3: {LCD_RS, LCD_DATA} = {1'b1,  data[255:248]};
				  4: {LCD_RS, LCD_DATA} = {1'b1,  data[247:240]};
				  5: {LCD_RS, LCD_DATA} = {1'b1,  data[239:232]};
				  6: {LCD_RS, LCD_DATA} = {1'b1,  data[231:224]};
				  7: {LCD_RS, LCD_DATA} = {1'b1,  data[223:216]};
				  8: {LCD_RS, LCD_DATA} = {1'b1,  data[215:208]};
				  9: {LCD_RS, LCD_DATA} = {1'b1,  data[207:200]};
				 10: {LCD_RS, LCD_DATA} = {1'b1,  data[199:192]};
				 11: {LCD_RS, LCD_DATA} = {1'b1,  data[191:184]};
				 12: {LCD_RS, LCD_DATA} = {1'b1,  data[183:176]};
				 13: {LCD_RS, LCD_DATA} = {1'b1,  data[175:168]};
				 14: {LCD_RS, LCD_DATA} = {1'b1,  data[167:160]};
				 15: {LCD_RS, LCD_DATA} = {1'b1,  data[159:152]};
				 16: {LCD_RS, LCD_DATA} = {1'b1,  data[151:144]};
				 17: {LCD_RS, LCD_DATA} = {1'b1,  data[143:136]};
				 18: {LCD_RS, LCD_DATA} = {1'b1,  data[135:128]};
			 
				 19: {LCD_RS, LCD_DATA} = {1'b0, 8'b1100_0000};
			 	
				 20: {LCD_RS, LCD_DATA} = {1'b1,  data[127:120]};
				 21: {LCD_RS, LCD_DATA} = {1'b1,  data[119:112]};
				 22: {LCD_RS, LCD_DATA} = {1'b1,  data[111:104]};
				 23: {LCD_RS, LCD_DATA} = {1'b1,  data[103:96]};
				 24: {LCD_RS, LCD_DATA} = {1'b1,  data[95:88]};
				 25: {LCD_RS, LCD_DATA} = {1'b1,  data[87:80]};
				 26: {LCD_RS, LCD_DATA} = {1'b1,  data[79:72]};
				 27: {LCD_RS, LCD_DATA} = {1'b1,  data[71:64]};
				 28: {LCD_RS, LCD_DATA} = {1'b1,  data[63:56]};
				 29: {LCD_RS, LCD_DATA} = {1'b1,  data[55:48]};
				 30: {LCD_RS, LCD_DATA} = {1'b1,  data[47:40]};
				 31: {LCD_RS, LCD_DATA} = {1'b1,  data[39:32]};
				 32: {LCD_RS, LCD_DATA} = {1'b1,  data[31:24]};
				 33: {LCD_RS, LCD_DATA} = {1'b1,  data[23:16]};
				 34: {LCD_RS, LCD_DATA} = {1'b1,  data[15:8]};
				 35: {LCD_RS, LCD_DATA} = {1'b1,  data[7:0]};

			default: {LCD_RS, LCD_DATA} = {1'b0, 8'b1000_0000};
		endcase 
	end
	
	always @(posedge clock or posedge rst) begin
	if (rst == 1'b1)
		begin
			counter = 26'd0;
			dispClock = 1'b0;
		end
	else
		begin
		    counter = counter + 1'b1;
		
		if (counter == 26'd100_000)
			begin
				counter = 26'd0;
				dispClock = ~dispClock;
			end
			
	end
end
	
	

endmodule
module lcd_control(
   input clock,
	input rst,
	input [255:0]data,
	output reg LCD_RS,
	output LCD_RW,
	output LCD_EN,
	output reg [7:0] LCD_DATA,
	output reg check
);

	parameter	INIT_STATE	=	0;
	parameter	LOAD_STATE	=	1;
	parameter	PUSH_STATE	=	2;
	parameter	IDLE_STATE	=	3;
	






	

	
	
	

	

	reg [5:0] index;
	reg [2:0] state;
	
	reg dispClock;
   reg [25:0]counter;

	always @(posedge dispClock or posedge rst) begin
		if (rst == 1'b1) begin
			index <= 0;
			state <= INIT_STATE;
		end
		else begin
			case (state)
				INIT_STATE: begin
					index <= 0;
					state <= LOAD_STATE;
					
				end
				LOAD_STATE: begin
					state <= (index > 36 ? IDLE_STATE : PUSH_STATE);
				
				end
				PUSH_STATE: begin
					index <= index + 1;
					state <= LOAD_STATE;
				end
				IDLE_STATE : begin
					state <= IDLE_STATE;
				end
				default: begin
					index <= 0;
					state <= INIT_STATE;
				end
			endcase
		end
	end

	assign LCD_EN = (state == PUSH_STATE);
	assign LCD_RW = 0;
	
	always @(*) begin
		case (index)
				  0: {LCD_RS, LCD_DATA} = {1'b0, 8'b0011_1000};
				  1: {LCD_RS, LCD_DATA} = {1'b0, 8'b0000_0110};
				  2: {LCD_RS, LCD_DATA} = {1'b0, 8'b0000_0001};

				  3: {LCD_RS, LCD_DATA} = {1'b1,  data[255:248]};
				  4: {LCD_RS, LCD_DATA} = {1'b1,  data[247:240]};
				  5: {LCD_RS, LCD_DATA} = {1'b1,  data[239:232]};
				  6: {LCD_RS, LCD_DATA} = {1'b1,  data[231:224]};
				  7: {LCD_RS, LCD_DATA} = {1'b1,  data[223:216]};
				  8: {LCD_RS, LCD_DATA} = {1'b1,  data[215:208]};
				  9: {LCD_RS, LCD_DATA} = {1'b1,  data[207:200]};
				 10: {LCD_RS, LCD_DATA} = {1'b1,  data[199:192]};
				 11: {LCD_RS, LCD_DATA} = {1'b1,  data[191:184]};
				 12: {LCD_RS, LCD_DATA} = {1'b1,  data[183:176]};
				 13: {LCD_RS, LCD_DATA} = {1'b1,  data[175:168]};
				 14: {LCD_RS, LCD_DATA} = {1'b1,  data[167:160]};
				 15: {LCD_RS, LCD_DATA} = {1'b1,  data[159:152]};
				 16: {LCD_RS, LCD_DATA} = {1'b1,  data[151:144]};
				 17: {LCD_RS, LCD_DATA} = {1'b1,  data[143:136]};
				 18: {LCD_RS, LCD_DATA} = {1'b1,  data[135:128]};
			 
				 19: {LCD_RS, LCD_DATA} = {1'b0, 8'b1100_0000};
			 	
				 20: {LCD_RS, LCD_DATA} = {1'b1,  data[127:120]};
				 21: {LCD_RS, LCD_DATA} = {1'b1,  data[119:112]};
				 22: {LCD_RS, LCD_DATA} = {1'b1,  data[111:104]};
				 23: {LCD_RS, LCD_DATA} = {1'b1,  data[103:96]};
				 24: {LCD_RS, LCD_DATA} = {1'b1,  data[95:88]};
				 25: {LCD_RS, LCD_DATA} = {1'b1,  data[87:80]};
				 26: {LCD_RS, LCD_DATA} = {1'b1,  data[79:72]};
				 27: {LCD_RS, LCD_DATA} = {1'b1,  data[71:64]};
				 28: {LCD_RS, LCD_DATA} = {1'b1,  data[63:56]};
				 29: {LCD_RS, LCD_DATA} = {1'b1,  data[55:48]};
				 30: {LCD_RS, LCD_DATA} = {1'b1,  data[47:40]};
				 31: {LCD_RS, LCD_DATA} = {1'b1,  data[39:32]};
				 32: {LCD_RS, LCD_DATA} = {1'b1,  data[31:24]};
				 33: {LCD_RS, LCD_DATA} = {1'b1,  data[23:16]};
				 34: {LCD_RS, LCD_DATA} = {1'b1,  data[15:8]};
				 35: {LCD_RS, LCD_DATA} = {1'b1,  data[7:0]};

			default: {LCD_RS, LCD_DATA} = {1'b0, 8'b1000_0000};
		endcase 
	end
	
	always @(posedge clock or posedge rst) begin
	if (rst == 1'b1)
		begin
			counter = 26'd0;
			dispClock = 1'b0;
		end
	else
		begin
		    counter = counter + 1'b1;
		
		if (counter == 26'd100_000)
			begin
				counter = 26'd0;
				dispClock = ~dispClock;
			end
			
	end
end
	
	

endmodule