data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/InstructionDecode/RegisterFile.v
data/verilator_xmls/ef77fbfa-5390-49ef-a869-d0091926420f.xml
module RegisterFile (
    input [4:0] rs1, rs2, wrd,
    input [63:0] wbd,
    input wwreg, clk,

    output reg [63:0] rqa, rqb
);

    reg [63:0] regfile [0:31];
    integer i;

    initial begin
        for (i = 0; i < 32; i = i + 1)
            regfile [i] = 64'h0;
    end

    always @(negedge clk) begin
        if (wwreg & (wrd != 0))
            regfile[wrd] <= wbd;
    end

    always @(*) begin
        rqa = regfile[rs1];
        rqb = regfile[rs2];
    end

endmodule
module RegisterFile (
    input [4:0] rs1, rs2, wrd,
    input [63:0] wbd,
    input wwreg, clk,

    output reg [63:0] rqa, rqb
);


    reg [63:0] regfile [0:31];
    integer i;

    initial begin
        for (i = 0; i < 32; i = i + 1)
            regfile [i] = 64'h0;
    end

    always @(negedge clk) begin
        if (wwreg & (wrd != 0))
            regfile[wrd] <= wbd;
    end

    always @(*) begin
        rqa = regfile[rs1];
        rqb = regfile[rs2];
    end

endmodule