data/full_repos/permissive/504248338/verilog/rtl/lib/ctech_cells.sv
1: b'%Warning-MULTITOP: data/full_repos/permissive/504248338/verilog/rtl/lib/ctech_cells.sv:26: Multiple top level modules\n                                                                                         : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                         : ... Top module \'ctech_mux2x1\'\nmodule ctech_mux2x1 #(parameter WB = 1) (\n       ^~~~~~~~~~~~\n                                                                                         : ... Top module \'ctech_mux2x1_2\'\nmodule ctech_mux2x1_2 #(parameter WB = 1) (\n       ^~~~~~~~~~~~~~\n                                                                                         : ... Top module \'ctech_mux2x1_4\'\nmodule ctech_mux2x1_4 #(parameter WB = 1) (\n       ^~~~~~~~~~~~~~\n                                                                                         : ... Top module \'ctech_buf\'\nmodule ctech_buf (\n       ^~~~~~~~~\n                                                                                         : ... Top module \'ctech_clk_buf\'\nmodule ctech_clk_buf (\n       ^~~~~~~~~~~~~\n                                                                                         : ... Top module \'ctech_delay_buf\'\nmodule ctech_delay_buf (\n       ^~~~~~~~~~~~~~~\n                                                                                         : ... Top module \'ctech_delay_clkbuf\'\nmodule ctech_delay_clkbuf (\n       ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module ctech_buf (
	input  logic A,
	output logic X);

`ifndef SYNTHESIS
assign X = A;
`else
    sky130_fd_sc_hd__bufbuf_8 u_buf  (.A(A),.X(X));
`endif

endmodule
module ctech_buf (
	input  logic A,
	output logic X);


`ifndef SYNTHESIS
assign X = A;
`else
    sky130_fd_sc_hd__bufbuf_8 u_buf  (.A(A),.X(X));
`endif

endmodule