data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/ALUcontrol.v
data/verilator_xmls/15c0f3a3-0284-4101-955a-2a019038a683.xml
module ALUcontrol(
    input [1:0]ALUop,
    input[6:0]funct7,
    input[2:0]funct3,
    output reg [3:0] ALUinput
);   
    always@(*) begin
        if(ALUop == 2'b00)
            ALUinput = 4'b0010;
        else if(ALUop == 2'b10) begin
            if(funct3 == 3'b000) begin
                if(funct7 == 7'b0000000)
                    ALUinput = 4'b0010;
                else if(funct7 == 7'b0100000)
                    ALUinput = 4'b0110;                  
            end
            else if(funct3 == 3'b111 && funct7 == 7'b00000000)
                ALUinput = 4'b0000;
            else if(funct3 == 3'b110 && funct7 == 7'b00000000 )
                ALUinput = 4'b0001;
            else if(funct3 == 3'b100 && funct7 == 7'b00000000)
                ALUinput = 4'b0011;
                        else if(funct7 == 7'b0000000 && funct3 == 3'b101)
                ALUinput = 4'b0101;
            else if(funct7 == 7'b0000000 && funct3 == 3'b001)
                ALUinput = 4'b0100;
            else if(funct7 == 7'b0100000 && funct3 == 3'b101)
                ALUinput = 4'b1001;
            else if(funct7 == 7'b0000000 && funct3 == 3'b011)
                ALUinput = 4'b0111;
            else if(funct7 == 7'b0000000 && funct3 == 3'b010)
                ALUinput = 4'b1000;
        end
        else if(ALUop == 2'b01) begin
            if(funct3 == 3'b000 || funct3 == 3'b001)
                ALUinput = 4'b0110;
            else if(funct3 == 3'b100 || funct3 ==3'b101)
                ALUinput = 4'b1000;
            else if(funct3 == 3'b110 || funct3 ==3'b111)
                ALUinput = 4'b0111;
        end
    end
endmodule
module ALUcontrol(
    input [1:0]ALUop,
    input[6:0]funct7,
    input[2:0]funct3,
    output reg [3:0] ALUinput
);
   
    always@(*) begin
        if(ALUop == 2'b00)
            ALUinput = 4'b0010;
        else if(ALUop == 2'b10) begin
            if(funct3 == 3'b000) begin
                if(funct7 == 7'b0000000)
                    ALUinput = 4'b0010;
                else if(funct7 == 7'b0100000)
                    ALUinput = 4'b0110;                  
            end
            else if(funct3 == 3'b111 && funct7 == 7'b00000000)
                ALUinput = 4'b0000;
            else if(funct3 == 3'b110 && funct7 == 7'b00000000 )
                ALUinput = 4'b0001;
            else if(funct3 == 3'b100 && funct7 == 7'b00000000)
                ALUinput = 4'b0011;
                        else if(funct7 == 7'b0000000 && funct3 == 3'b101)
                ALUinput = 4'b0101;
            else if(funct7 == 7'b0000000 && funct3 == 3'b001)
                ALUinput = 4'b0100;
            else if(funct7 == 7'b0100000 && funct3 == 3'b101)
                ALUinput = 4'b1001;
            else if(funct7 == 7'b0000000 && funct3 == 3'b011)
                ALUinput = 4'b0111;
            else if(funct7 == 7'b0000000 && funct3 == 3'b010)
                ALUinput = 4'b1000;
        end
        else if(ALUop == 2'b01) begin
            if(funct3 == 3'b000 || funct3 == 3'b001)
                ALUinput = 4'b0110;
            else if(funct3 == 3'b100 || funct3 ==3'b101)
                ALUinput = 4'b1000;
            else if(funct3 == 3'b110 || funct3 ==3'b111)
                ALUinput = 4'b0111;
        end
    end
endmodule