data/full_repos/permissive/449370139/verilog_code/car_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/449370139/verilog_code/car_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n                 #10\n                 ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/449370139/verilog_code/car_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Error: data/full_repos/permissive/449370139/verilog_code/car_tb.v:37: Cannot find file containing module: \'car_top\'\ncar_top car(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/449370139/verilog_code,data/full_repos/permissive/449370139/car_top\n             data/full_repos/permissive/449370139/verilog_code,data/full_repos/permissive/449370139/car_top.v\n             data/full_repos/permissive/449370139/verilog_code,data/full_repos/permissive/449370139/car_top.sv\n             car_top\n             car_top.v\n             car_top.sv\n             obj_dir/car_top\n             obj_dir/car_top.v\n             obj_dir/car_top.sv\n%Warning-WIDTH: data/full_repos/permissive/449370139/verilog_code/car_tb.v:62: Operator LT expects 32 or 24 bits on the LHS, but LHS\'s VARREF \'invect\' generates 8 bits.\n                                                                             : ... In instance car_tb\n        for (invect = 0; invect < 9999999; invect = invect + 1)\n                                ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module car_tb();
reg clk;
reg I_rst_n;
reg rxd;
reg go;
reg excute;
reg [4:0]setdir;
wire txd;
wire [3:0] O_red;
wire [3:0] O_green;
wire [3:0] O_blue;
wire O_hs;
wire O_vs;
wire [4:0]showstate;

car_top car(
    .clk(clk)      ,
    .I_rst_n(I_rst_n)  ,
    .rxd(rxd)      ,
    .go(go)       ,
    .excute(excute)   ,
    .setdir(setdir)   ,
    .txd(txd)      ,
    .O_red(O_red)    ,
    .O_green(O_green)  ,
    .O_blue(O_blue)   ,
    .O_hs(O_hs)     ,
    .O_vs(O_vs)     ,
    .showstate(showstate)
    );
reg [7:0] invect;
initial
    begin
        I_rst_n<=1'b0;
        clk<=1'b0;
        rxd<=1'b1;
        go<=1'b1;
        excute<=1'b1;
        setdir<=5'b00000;
        #10
        for (invect = 0; invect < 9999999; invect = invect + 1)
                 begin  
                 I_rst_n<=1'b1;
                 #10
                 clk=~clk;
                 end
    end  
endmodule
module car_tb();

reg clk;
reg I_rst_n;
reg rxd;
reg go;
reg excute;
reg [4:0]setdir;
wire txd;
wire [3:0] O_red;
wire [3:0] O_green;
wire [3:0] O_blue;
wire O_hs;
wire O_vs;
wire [4:0]showstate;

car_top car(
    .clk(clk)      ,
    .I_rst_n(I_rst_n)  ,
    .rxd(rxd)      ,
    .go(go)       ,
    .excute(excute)   ,
    .setdir(setdir)   ,
    .txd(txd)      ,
    .O_red(O_red)    ,
    .O_green(O_green)  ,
    .O_blue(O_blue)   ,
    .O_hs(O_hs)     ,
    .O_vs(O_vs)     ,
    .showstate(showstate)
    );
reg [7:0] invect;
initial
    begin
        I_rst_n<=1'b0;
        clk<=1'b0;
        rxd<=1'b1;
        go<=1'b1;
        excute<=1'b1;
        setdir<=5'b00000;
        #10
        for (invect = 0; invect < 9999999; invect = invect + 1)
                 begin  
                 I_rst_n<=1'b1;
                 #10
                 clk=~clk;
                 end
    end  
endmodule