data/full_repos/permissive/419538859/lab4/lab4_2/lab4_2.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/419538859/lab4/lab4_2/lab4_2.v:12: Signal definition not found, creating implicitly: \'clk_idx\'\nfreq_div#(22) M1 (clk,reset,clk_idx);\n                            ^~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/419538859/lab4/lab4_2/lab4_2.v:13: Signal definition not found, creating implicitly: \'clk_row\'\nfreq_div#(12) M2 (clk,reset,clk_row);\n                            ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab4/lab4_2/lab4_2.v:163: Operator ADD expects 7 bits on the RHS, but RHS\'s VARREF \'cnt\' generates 3 bits.\n                                                                             : ... In instance lab4_2.M4\n  idx_cnt =idx+cnt;    \n              ^\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab4/lab4_2/lab4_2.v:14: Output port connection \'idx\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'idx\' generates 8 bits.\n                                                                            : ... In instance lab4_2\nidx_gen M3 (clk_idx,reset,idx); \n                          ^~~\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab4/lab4_2/lab4_2.v:15: Input port connection \'idx\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'idx\' generates 8 bits.\n                                                                            : ... In instance lab4_2\nrow_gen M4 (clk_row,reset, idx, row, idx_cnt);\n                           ^~~\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab4/lab4_2/lab4_2.v:15: Output port connection \'idx_cnt\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'idx_cnt\' generates 8 bits.\n                                                                            : ... In instance lab4_2\nrow_gen M4 (clk_row,reset, idx, row, idx_cnt);\n                                     ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab4/lab4_2/lab4_2.v:16: Input port connection \'addr\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'idx_cnt\' generates 8 bits.\n                                                                            : ... In instance lab4_2\nrom_char M5 (idx_cnt, column_out);\n             ^~~~~~~\n%Error: Exiting due to 7 warning(s)\n'
module 	row_gen(clk, reset, idx, row, idx_cnt);
input 	clk, reset;
input	[6:0]idx;
output	[7:0]row;
output	[6:0]idx_cnt;
reg		[7:0]row;
reg		[6:0]idx_cnt;
reg		[2:0]cnt;

always@(posedge clk or posedge reset) 
begin
	if(reset) begin
		row		=8'b1000_0000;
		cnt		=3'd0;
		idx_cnt	=7'd0;
		end
	else begin
		row		={row[0],row[7:1]} ;
		cnt		=cnt+3'd1;
		idx_cnt	=idx+cnt;
		end
end
endmodule
module 	row_gen(clk, reset, idx, row, idx_cnt);

input 	clk, reset;
input	[6:0]idx;
output	[7:0]row;
output	[6:0]idx_cnt;
reg		[7:0]row;
reg		[6:0]idx_cnt;
reg		[2:0]cnt;

always@(posedge clk or posedge reset) 
begin
	if(reset) begin
		row		=8'b1000_0000;
		cnt		=3'd0;
		idx_cnt	=7'd0;
		end
	else begin
		row		={row[0],row[7:1]} ;
		cnt		=cnt+3'd1;
		idx_cnt	=idx+cnt;
		end
end
endmodule