data/full_repos/permissive/423852699/verilog/ALU.v
1: b'%Warning-WIDTH: data/full_repos/permissive/423852699/verilog/ALU.v:75: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'addResult\' generates 33 bits.\n                                                                     : ... In instance ALU\n                alu_result_reg = addResult;\n                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/423852699/verilog/ALU.v:85: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'subResult\' generates 33 bits.\n                                                                     : ... In instance ALU\n                alu_result_reg = subResult;\n                               ^\n%Error: Exiting due to 2 warning(s)\n'
module ALU (
    input wire[31:0] opr1,
    input wire[31:0] opr2,
    input wire[3:0] ALUControl,

    output wire[31:0] ALUResult,
    output wire not_change
);



    wire[32:0] extOpr1 = {opr1[31], opr1};
    wire[32:0] extOpr2 = {opr2[31], opr2};

    wire[32:0] addResult = extOpr1 + extOpr2;
    wire[31:0] adduResult = opr1 + opr2;

    wire[32:0] subResult = extOpr1 - extOpr2;
    wire[31:0] subuResult = opr1 - opr2;

    wire[31:0] andResult = opr1 & opr2;
    wire[31:0] orResult = opr1 | opr2;
    wire[31:0] xorResult = opr1 ^ opr2;
    wire[31:0] norResult = ~(opr1 | opr2);

    wire[31:0] sltResult = $signed(opr1) < $signed(opr2) ? 32'h1 : 32'h0;
    wire[31:0] sltuResult = opr1 < opr2 ? 32'h1 : 32'h0;

    wire[31:0] sllResult = opr2 << opr1;
    wire[31:0] srlResult = opr2 >> opr1;
    wire[31:0] sraResult = opr2[31] ? (~(32'hffffffff >> opr1) | (opr2 >> opr1)) : opr2 >> opr1;

    wire[31:0] luiResult = {opr2[15:0], 16'h0};

    wire[31:0] movnResult = opr1;

    reg[31:0] alu_result_reg;
    assign ALUResult = alu_result_reg;
    
    always @(*) begin
        case (ALUControl)
            4'b0000,
            4'b0001:
            begin
                alu_result_reg = movnResult;
            end

            4'b0010:
            begin
                alu_result_reg = addResult;
            end

            4'b0011:
            begin
                alu_result_reg = adduResult;
            end

            4'b0100:
            begin
                alu_result_reg = subResult;
            end

            4'b0101:
            begin
                alu_result_reg = subuResult;
            end

            4'b0110:
            begin
                alu_result_reg = andResult;
            end

            4'b0111:
            begin
                alu_result_reg = orResult;
            end

            4'b1000:
            begin
                alu_result_reg = xorResult;
            end

            4'b1001:
            begin
                alu_result_reg = norResult;
            end

            4'b1010:
            begin
                alu_result_reg = sltResult;
            end

            4'b1011:
            begin
                alu_result_reg = sltuResult;
            end

            4'b1100:
            begin
                alu_result_reg = srlResult;
            end

            4'b1101:
            begin
                alu_result_reg = sraResult;
            end

            4'b1110:
            begin
                alu_result_reg = sllResult;
            end

            4'b1111:
            begin
                alu_result_reg = luiResult;
            end

            default:
            begin
                alu_result_reg = 32'hcfcfcfcf;
            end
        endcase
    end

    wire not_change_movn = (ALUControl == 4'b0001 & opr2 == 0);
    wire not_change_movz = (ALUControl == 4'b0000 & opr2 != 0);
    wire not_change_add_overflow = ALUControl == 4'b0010 & (addResult[32] ^ addResult[31]);
    wire not_change_sub_overflow = ALUControl == 4'b0100 & (subResult[32] ^ subResult[31]);

    assign not_change = not_change_movn | not_change_movz | not_change_add_overflow | not_change_sub_overflow;
endmodule
module ALU (
    input wire[31:0] opr1,
    input wire[31:0] opr2,
    input wire[3:0] ALUControl,

    output wire[31:0] ALUResult,
    output wire not_change
);




    wire[32:0] extOpr1 = {opr1[31], opr1};
    wire[32:0] extOpr2 = {opr2[31], opr2};

    wire[32:0] addResult = extOpr1 + extOpr2;
    wire[31:0] adduResult = opr1 + opr2;

    wire[32:0] subResult = extOpr1 - extOpr2;
    wire[31:0] subuResult = opr1 - opr2;

    wire[31:0] andResult = opr1 & opr2;
    wire[31:0] orResult = opr1 | opr2;
    wire[31:0] xorResult = opr1 ^ opr2;
    wire[31:0] norResult = ~(opr1 | opr2);

    wire[31:0] sltResult = $signed(opr1) < $signed(opr2) ? 32'h1 : 32'h0;
    wire[31:0] sltuResult = opr1 < opr2 ? 32'h1 : 32'h0;

    wire[31:0] sllResult = opr2 << opr1;
    wire[31:0] srlResult = opr2 >> opr1;
    wire[31:0] sraResult = opr2[31] ? (~(32'hffffffff >> opr1) | (opr2 >> opr1)) : opr2 >> opr1;

    wire[31:0] luiResult = {opr2[15:0], 16'h0};

    wire[31:0] movnResult = opr1;

    reg[31:0] alu_result_reg;
    assign ALUResult = alu_result_reg;
    
    always @(*) begin
        case (ALUControl)
            4'b0000,
            4'b0001:
            begin
                alu_result_reg = movnResult;
            end

            4'b0010:
            begin
                alu_result_reg = addResult;
            end

            4'b0011:
            begin
                alu_result_reg = adduResult;
            end

            4'b0100:
            begin
                alu_result_reg = subResult;
            end

            4'b0101:
            begin
                alu_result_reg = subuResult;
            end

            4'b0110:
            begin
                alu_result_reg = andResult;
            end

            4'b0111:
            begin
                alu_result_reg = orResult;
            end

            4'b1000:
            begin
                alu_result_reg = xorResult;
            end

            4'b1001:
            begin
                alu_result_reg = norResult;
            end

            4'b1010:
            begin
                alu_result_reg = sltResult;
            end

            4'b1011:
            begin
                alu_result_reg = sltuResult;
            end

            4'b1100:
            begin
                alu_result_reg = srlResult;
            end

            4'b1101:
            begin
                alu_result_reg = sraResult;
            end

            4'b1110:
            begin
                alu_result_reg = sllResult;
            end

            4'b1111:
            begin
                alu_result_reg = luiResult;
            end

            default:
            begin
                alu_result_reg = 32'hcfcfcfcf;
            end
        endcase
    end

    wire not_change_movn = (ALUControl == 4'b0001 & opr2 == 0);
    wire not_change_movz = (ALUControl == 4'b0000 & opr2 != 0);
    wire not_change_add_overflow = ALUControl == 4'b0010 & (addResult[32] ^ addResult[31]);
    wire not_change_sub_overflow = ALUControl == 4'b0100 & (subResult[32] ^ subResult[31]);

    assign not_change = not_change_movn | not_change_movz | not_change_add_overflow | not_change_sub_overflow;
endmodule