data/full_repos/permissive/441216763/testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/441216763/testbench.v:9: Unsupported: Ignoring delay on this delayed statement.\n    always #(40/2) clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/441216763/testbench.v:15: Unsupported: Ignoring delay on this delayed statement.\n            OP=4\'b0000;A=32\'h0000_0000; B=32\'h0000_0001;#50;\n                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/441216763/testbench.v:16: Unsupported: Ignoring delay on this delayed statement.\n            OP=4\'b0000;A=32\'h0000_0001; B=32\'h0000_0001;#50;\n                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/441216763/testbench.v:18: Unsupported: Ignoring delay on this delayed statement.\n            OP=4\'b0001;A=32\'h0000_0000; B=32\'h0000_0001;#50;\n                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/441216763/testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n            OP=4\'b0001;A=32\'h0000_0000; B=32\'h0000_0000;#50;\n                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/441216763/testbench.v:21: Unsupported: Ignoring delay on this delayed statement.\n            OP=4\'b0010;A=32\'h0000_0000; B=32\'h0000_0001;#50;\n                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/441216763/testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n            OP=4\'b0010;A=32\'h0000_0000; B=32\'h0000_0000;#50;\n                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/441216763/testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\n            OP=4\'b0011;A=32\'h0000_0000; B=32\'h0000_0001;#50;\n                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/441216763/testbench.v:25: Unsupported: Ignoring delay on this delayed statement.\n            OP=4\'b0011;A=32\'h0000_0000; B=32\'h0000_0000;#50;\n                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/441216763/testbench.v:27: Unsupported: Ignoring delay on this delayed statement.\n            OP=4\'b0110;A=32\'h7FFF_FFFF; B=32\'h8FFF_FFFF;#50;\n                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/441216763/testbench.v:28: Unsupported: Ignoring delay on this delayed statement.\n            OP=4\'b0110;A=32\'hFFFF_FFFF; B=32\'h7FFF_FFFF;#50;\n                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/441216763/testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n            OP=4\'b0111;A=32\'h0000_0001; B=32\'h0000_0001;#50;\n                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/441216763/testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n            OP=4\'b0111;A=32\'h0000_0001; B=32\'h0000_0008;#50;\n                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/441216763/testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n            OP=4\'b0100;A=32\'h7FFF_FFFF; B=32\'h7FFF_FFFF;#50;\n                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/441216763/testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n            OP=4\'b0100;A=32\'hFFFF_FFFF; B=32\'hFFFF_FFFF;#50;\n                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/441216763/testbench.v:39: Unsupported: Ignoring delay on this delayed statement.\n            OP=4\'b0101;A=32\'h7FFF_FFFF; B=32\'h7FFF_FFFF;#50;\n                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/441216763/testbench.v:40: Unsupported: Ignoring delay on this delayed statement.\n            OP=4\'b0101;A=32\'hFFFF_FFFF; B=32\'hFFFF_FFFF;#50;\n                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/441216763/testbench.v:45: Unsupported: Ignoring delay on this delayed statement.\n            #(40)\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/441216763/testbench.v:47: Unsupported: Ignoring delay on this delayed statement.\n            #(40)\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/441216763/testbench.v:49: Unsupported: Ignoring delay on this delayed statement.\n            #(40*40)\n            ^\n%Error: data/full_repos/permissive/441216763/testbench.v:56: Cannot find file containing module: \'ALU\'\n    ALU ALU_test(\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/441216763,data/full_repos/permissive/441216763/ALU\n             data/full_repos/permissive/441216763,data/full_repos/permissive/441216763/ALU.v\n             data/full_repos/permissive/441216763,data/full_repos/permissive/441216763/ALU.sv\n             ALU\n             ALU.v\n             ALU.sv\n             obj_dir/ALU\n             obj_dir/ALU.v\n             obj_dir/ALU.sv\n%Error: Exiting due to 1 error(s), 20 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();
    reg [31:0] A,B;
    reg [3:0] OP;
    reg clk;
    reg Rst;
    real time_now;
    always #(`clock_period/2) clk = ~clk;
    initial
    begin
            clk=1;
            Rst = 0;

            OP=4'b0000;A=32'h0000_0000; B=32'h0000_0001;#50;
            OP=4'b0000;A=32'h0000_0001; B=32'h0000_0001;#50;

            OP=4'b0001;A=32'h0000_0000; B=32'h0000_0001;#50;
            OP=4'b0001;A=32'h0000_0000; B=32'h0000_0000;#50;

            OP=4'b0010;A=32'h0000_0000; B=32'h0000_0001;#50;
            OP=4'b0010;A=32'h0000_0000; B=32'h0000_0000;#50;

            OP=4'b0011;A=32'h0000_0000; B=32'h0000_0001;#50;
            OP=4'b0011;A=32'h0000_0000; B=32'h0000_0000;#50;

            OP=4'b0110;A=32'h7FFF_FFFF; B=32'h8FFF_FFFF;#50;
            OP=4'b0110;A=32'hFFFF_FFFF; B=32'h7FFF_FFFF;#50;

            OP=4'b0111;A=32'h0000_0001; B=32'h0000_0001;#50;
            OP=4'b0111;A=32'h0000_0001; B=32'h0000_0008;#50;

            time_now = $time;

            OP=4'b0100;A=32'h7FFF_FFFF; B=32'h7FFF_FFFF;#50;

            OP=4'b0100;A=32'hFFFF_FFFF; B=32'hFFFF_FFFF;#50;

            OP=4'b0101;A=32'h7FFF_FFFF; B=32'h7FFF_FFFF;#50;
            OP=4'b0101;A=32'hFFFF_FFFF; B=32'hFFFF_FFFF;#50;

            OP=4'b1000;
            A=32'h7FFF_FFFF; B=32'h7FFF_FFFF;
            Rst = 0;
            #(`clock_period)
            Rst = 1;
            #(`clock_period)
            Rst = 0;
            #(`clock_period*40)
       $stop;

    end
    
    wire [31:0] F;
    wire ZF, CF, OF, SF, PF;
    ALU ALU_test(
        .OP(OP),
        .A(A),
        .B(B),
        .Rst(Rst),
        .clk(clk),
        .F(F),
        .ZF(ZF),
        .CF(CF),
        .OF(OF),
        .SF(SF),
        .PF(PF)
    );
    
endmodule
module test();

    reg [31:0] A,B;
    reg [3:0] OP;
    reg clk;
    reg Rst;
    real time_now;
    always #(`clock_period/2) clk = ~clk;
    initial
    begin
            clk=1;
            Rst = 0;

            OP=4'b0000;A=32'h0000_0000; B=32'h0000_0001;#50;
            OP=4'b0000;A=32'h0000_0001; B=32'h0000_0001;#50;

            OP=4'b0001;A=32'h0000_0000; B=32'h0000_0001;#50;
            OP=4'b0001;A=32'h0000_0000; B=32'h0000_0000;#50;

            OP=4'b0010;A=32'h0000_0000; B=32'h0000_0001;#50;
            OP=4'b0010;A=32'h0000_0000; B=32'h0000_0000;#50;

            OP=4'b0011;A=32'h0000_0000; B=32'h0000_0001;#50;
            OP=4'b0011;A=32'h0000_0000; B=32'h0000_0000;#50;

            OP=4'b0110;A=32'h7FFF_FFFF; B=32'h8FFF_FFFF;#50;
            OP=4'b0110;A=32'hFFFF_FFFF; B=32'h7FFF_FFFF;#50;

            OP=4'b0111;A=32'h0000_0001; B=32'h0000_0001;#50;
            OP=4'b0111;A=32'h0000_0001; B=32'h0000_0008;#50;

            time_now = $time;

            OP=4'b0100;A=32'h7FFF_FFFF; B=32'h7FFF_FFFF;#50;

            OP=4'b0100;A=32'hFFFF_FFFF; B=32'hFFFF_FFFF;#50;

            OP=4'b0101;A=32'h7FFF_FFFF; B=32'h7FFF_FFFF;#50;
            OP=4'b0101;A=32'hFFFF_FFFF; B=32'hFFFF_FFFF;#50;

            OP=4'b1000;
            A=32'h7FFF_FFFF; B=32'h7FFF_FFFF;
            Rst = 0;
            #(`clock_period)
            Rst = 1;
            #(`clock_period)
            Rst = 0;
            #(`clock_period*40)
       $stop;

    end
    
    wire [31:0] F;
    wire ZF, CF, OF, SF, PF;
    ALU ALU_test(
        .OP(OP),
        .A(A),
        .B(B),
        .Rst(Rst),
        .clk(clk),
        .F(F),
        .ZF(ZF),
        .CF(CF),
        .OF(OF),
        .SF(SF),
        .PF(PF)
    );
    
endmodule