data/full_repos/permissive/515100461/sequential/execute.v
1: b'%Error: data/full_repos/permissive/515100461/sequential/execute.v:1: Cannot find include file: ALU.v\n`include "ALU.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/515100461/sequential,data/full_repos/permissive/515100461/ALU.v\n             data/full_repos/permissive/515100461/sequential,data/full_repos/permissive/515100461/ALU.v.v\n             data/full_repos/permissive/515100461/sequential,data/full_repos/permissive/515100461/ALU.v.sv\n             ALU.v\n             ALU.v.v\n             ALU.v.sv\n             obj_dir/ALU.v\n             obj_dir/ALU.v.v\n             obj_dir/ALU.v.sv\n%Error: Exiting due to 1 error(s)\n'
module execute(icode,ifun,clk,valA,valB,valC,valE,cnd);
input [3:0] icode,ifun;
input [63:0] valA, valB, valC;
input clk;
output reg [63:0] valE;
output reg cnd;

reg zf,sf,of;
reg[1:0] control;
reg signed[63:0] t,a,b;
wire signed [63:0] ans;
wire overflow;
initial 
begin
    zf = 0;
    of = 0;
    sf = 0;
    a = 63'b0;
    b = 63'b0;
    control = 2'b00;
end

always@(*)
begin
    if(icode == 4'b0110)
    begin
        zf = (ans == 63'b0);
        sf = (ans < 1'b0);
        of = (a<1'b0 == b<1'b0)&&(ans<1'b0!=a<1'b0);
    end
    
end

alu alu1(.control(control),.a(a),.b(b),.end_result(ans),.carry_overflow(overflow));

wire o1;

xor(o1,sf,of);

always@(*)
begin
case(icode)

  4'b0010 :
  begin
    case(ifun)

      4'b0000:
      cnd = 1;

      4'b0001:
      begin
         if(o1) cnd = 1;
         else if(zf) cnd = 1;   
      end

      4'b0010:
          if(o1) cnd =1;
    
      4'b0011:
          if(zf) cnd =1;

      4'b0100:
        if(!zf) cnd =1;

      4'b0101:
        if(!o1) cnd =1;
    
      4'b0110:
      begin
          if(!o1)
          if(!zf) cnd =1;
      end
    endcase

      valE = valA + valB;
  end

  4'b0011 :
  begin
      valE = 63'b0 + valC;
  end
  
  4'b0100 :
  begin
      valE = valB + valC;
  end

  4'b0101 :
  begin
      valE = valB + valC;
  end

  4'b0110 :
  begin
      case(ifun)
          4'b0000:
          begin
              control <= 2'b00;
              a <= valA;
              b <= valB;
          end

           4'b0001:
          begin
              control = 2'b01;
              a = valB;
              b = valA;
          end

           4'b0010:
          begin
              control = 2'b11;
              a = valA;
              b = valB;
          end

           4'b0011:
          begin
              control = 2'b10;
              a = valA;
              b = valB;
          end
      endcase
      valE = ans;
   end

   4'b0111:
   begin 
    case(ifun)

      4'b0000:
      cnd = 1;

      4'b0001:
      begin
         if(o1) cnd = 1;
         else if(zf) cnd = 1;   
      end

      4'b0010:
          if(o1) cnd =1;
    
      4'b0011:
          if(zf) cnd =1;

      4'b0100:
        if(!zf) cnd =1;

      4'b0101:
        if(!o1) cnd =1;
    
      4'b0110:
      begin
          if(!o1)
          if(!zf) cnd =1;
      end
    endcase           
   end
   4'b1000 :
   valE = -64'd8 + valB;

   4'b1001 :
   valE = 64'd8 + valA; 

   4'b1010:
   valE = -64'd8 + valB;

   4'b1011:
   valE = 64'd8 + valA; 

  endcase
end
endmodule
module execute(icode,ifun,clk,valA,valB,valC,valE,cnd);

input [3:0] icode,ifun;
input [63:0] valA, valB, valC;
input clk;
output reg [63:0] valE;
output reg cnd;

reg zf,sf,of;
reg[1:0] control;
reg signed[63:0] t,a,b;
wire signed [63:0] ans;
wire overflow;
initial 
begin
    zf = 0;
    of = 0;
    sf = 0;
    a = 63'b0;
    b = 63'b0;
    control = 2'b00;
end

always@(*)
begin
    if(icode == 4'b0110)
    begin
        zf = (ans == 63'b0);
        sf = (ans < 1'b0);
        of = (a<1'b0 == b<1'b0)&&(ans<1'b0!=a<1'b0);
    end
    
end

alu alu1(.control(control),.a(a),.b(b),.end_result(ans),.carry_overflow(overflow));

wire o1;

xor(o1,sf,of);

always@(*)
begin
case(icode)

  4'b0010 :
  begin
    case(ifun)

      4'b0000:
      cnd = 1;

      4'b0001:
      begin
         if(o1) cnd = 1;
         else if(zf) cnd = 1;   
      end

      4'b0010:
          if(o1) cnd =1;
    
      4'b0011:
          if(zf) cnd =1;

      4'b0100:
        if(!zf) cnd =1;

      4'b0101:
        if(!o1) cnd =1;
    
      4'b0110:
      begin
          if(!o1)
          if(!zf) cnd =1;
      end
    endcase

      valE = valA + valB;
  end

  4'b0011 :
  begin
      valE = 63'b0 + valC;
  end
  
  4'b0100 :
  begin
      valE = valB + valC;
  end

  4'b0101 :
  begin
      valE = valB + valC;
  end

  4'b0110 :
  begin
      case(ifun)
          4'b0000:
          begin
              control <= 2'b00;
              a <= valA;
              b <= valB;
          end

           4'b0001:
          begin
              control = 2'b01;
              a = valB;
              b = valA;
          end

           4'b0010:
          begin
              control = 2'b11;
              a = valA;
              b = valB;
          end

           4'b0011:
          begin
              control = 2'b10;
              a = valA;
              b = valB;
          end
      endcase
      valE = ans;
   end

   4'b0111:
   begin 
    case(ifun)

      4'b0000:
      cnd = 1;

      4'b0001:
      begin
         if(o1) cnd = 1;
         else if(zf) cnd = 1;   
      end

      4'b0010:
          if(o1) cnd =1;
    
      4'b0011:
          if(zf) cnd =1;

      4'b0100:
        if(!zf) cnd =1;

      4'b0101:
        if(!o1) cnd =1;
    
      4'b0110:
      begin
          if(!o1)
          if(!zf) cnd =1;
      end
    endcase           
   end
   4'b1000 :
   valE = -64'd8 + valB;

   4'b1001 :
   valE = 64'd8 + valA; 

   4'b1010:
   valE = -64'd8 + valB;

   4'b1011:
   valE = 64'd8 + valA; 

  endcase
end
endmodule