data/full_repos/permissive/521704862/iiitb_SDM_tb.v
1: b'%Error: data/full_repos/permissive/521704862/iiitb_SDM_tb.v:7: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("sqnsdet_tb.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/521704862/iiitb_SDM_tb.v:8: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0);\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/521704862/iiitb_SDM_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n#10 reset=1;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/521704862/iiitb_SDM_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n#10 reset =0;\n^\n%Error: data/full_repos/permissive/521704862/iiitb_SDM_tb.v:13: Unsupported or unknown PLI call: $monitor\n$monitor($time, , ,"c=%b",clock,,"y=%b",detector_out,,"r=%b",reset,,"d=%b",sequence_in);\n^~~~~~~~\n%Error: data/full_repos/permissive/521704862/iiitb_SDM_tb.v:13: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n$monitor($time, , ,"c=%b",clock,,"y=%b",detector_out,,"r=%b",reset,,"d=%b",sequence_in);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/521704862/iiitb_SDM_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n#10 sequence_in=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/521704862/iiitb_SDM_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n#10 sequence_in=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/521704862/iiitb_SDM_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n#10 sequence_in=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/521704862/iiitb_SDM_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n#10 sequence_in=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/521704862/iiitb_SDM_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n#10 sequence_in=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/521704862/iiitb_SDM_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n#10 sequence_in=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/521704862/iiitb_SDM_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n#10 sequence_in=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/521704862/iiitb_SDM_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n#10 sequence_in=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/521704862/iiitb_SDM_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n#10 sequence_in=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/521704862/iiitb_SDM_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n#10 sequence_in=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/521704862/iiitb_SDM_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n#10 sequence_in=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/521704862/iiitb_SDM_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n#5 clock=~clock;\n^\n%Warning-STMTDLY: data/full_repos/permissive/521704862/iiitb_SDM_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n#200 $finish ;\n^\n%Error: Exiting due to 4 error(s), 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module iiitb_SDM_tb;
reg sequence_in,clock,reset;
wire detector_out;
iiitb_SDM m1(sequence_in,clock,reset,detector_out);
initial
begin
$dumpfile("sqnsdet_tb.vcd");
$dumpvars(0);
clock=0;sequence_in=0;
reset=1;
#10 reset=1;
#10 reset =0;
$monitor($time, , ,"c=%b",clock,,"y=%b",detector_out,,"r=%b",reset,,"d=%b",sequence_in);
#10 sequence_in=0;
#10 sequence_in=1;
#10 sequence_in=0;
#10 sequence_in=1;
#10 sequence_in=0;
#10 sequence_in=1;
#10 sequence_in=1;
#10 sequence_in=0;
#10 sequence_in=1;
#10 sequence_in=0;
#10 sequence_in=0;

end
always
#5 clock=~clock;
initial
#200 $finish ;
endmodule
module iiitb_SDM_tb;

reg sequence_in,clock,reset;
wire detector_out;
iiitb_SDM m1(sequence_in,clock,reset,detector_out);
initial
begin
$dumpfile("sqnsdet_tb.vcd");
$dumpvars(0);
clock=0;sequence_in=0;
reset=1;
#10 reset=1;
#10 reset =0;
$monitor($time, , ,"c=%b",clock,,"y=%b",detector_out,,"r=%b",reset,,"d=%b",sequence_in);
#10 sequence_in=0;
#10 sequence_in=1;
#10 sequence_in=0;
#10 sequence_in=1;
#10 sequence_in=0;
#10 sequence_in=1;
#10 sequence_in=1;
#10 sequence_in=0;
#10 sequence_in=1;
#10 sequence_in=0;
#10 sequence_in=0;

end
always
#5 clock=~clock;
initial
#200 $finish ;
endmodule