data/full_repos/permissive/426864978/lab2/task2/tb_rtl_task2.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task2/tb_rtl_task2.sv:18: Unsupported: Ignoring delay on this delayed statement.\n        forever #5 CLOCK_50 = ~CLOCK_50;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task2/tb_rtl_task2.sv:56: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task2/tb_rtl_task2.sv:65: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task2/tb_rtl_task2.sv:74: Unsupported: Ignoring delay on this delayed statement.\n        #10; cycle_count = cycle_count + 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task2/tb_rtl_task2.sv:84: Unsupported: Ignoring delay on this delayed statement.\n                #10; cycle_count = cycle_count + 1;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task2/tb_rtl_task2.sv:88: Unsupported: Ignoring delay on this delayed statement.\n        #10; cycle_count = cycle_count + 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task2/tb_rtl_task2.sv:95: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/426864978/lab2/task2/tb_rtl_task2.sv:27: Can\'t find definition of \'VGA_X\' in dotted variable: \'tb_rtl_task2.dut.VGA_X\'\n            if (tb_rtl_task2.dut.VGA_X !== exp_x) begin\n                                 ^~~~~\n%Error: data/full_repos/permissive/426864978/lab2/task2/tb_rtl_task2.sv:28: Can\'t find definition of \'VGA_X\' in dotted variable: \'tb_rtl_task2.dut.VGA_X\'\n                $display("ERROR A: Expected VGA_X is %d, actual VGA_X is %d", exp_x, tb_rtl_task2.dut.VGA_X);\n                                                                                                      ^~~~~\n%Error: data/full_repos/permissive/426864978/lab2/task2/tb_rtl_task2.sv:31: Can\'t find definition of \'VGA_Y\' in dotted variable: \'tb_rtl_task2.dut.VGA_Y\'\n            if (tb_rtl_task2.dut.VGA_Y !== exp_y) begin\n                                 ^~~~~\n%Error: data/full_repos/permissive/426864978/lab2/task2/tb_rtl_task2.sv:32: Can\'t find definition of \'VGA_Y\' in dotted variable: \'tb_rtl_task2.dut.VGA_Y\'\n                $display("ERROR B: Expected VGA_Y is %d, actual VGA_Y is %d", exp_y, tb_rtl_task2.dut.VGA_Y);\n                                                                                                      ^~~~~\n%Error: data/full_repos/permissive/426864978/lab2/task2/tb_rtl_task2.sv:35: Can\'t find definition of \'VGA_COLOUR\' in dotted variable: \'tb_rtl_task2.dut.VGA_COLOUR\'\n            if (tb_rtl_task2.dut.VGA_COLOUR !== exp_colour) begin\n                                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/426864978/lab2/task2/tb_rtl_task2.sv:36: Can\'t find definition of \'VGA_COLOUR\' in dotted variable: \'tb_rtl_task2.dut.VGA_COLOUR\'\n                $display("ERROR C: Expected VGA_COLOUR is %d, actual VGA_COLOUR is %d", exp_colour, tb_rtl_task2.dut.VGA_COLOUR);\n                                                                                                                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/426864978/lab2/task2/tb_rtl_task2.sv:39: Can\'t find definition of \'done\' in dotted variable: \'tb_rtl_task2.dut.done\'\n            if (tb_rtl_task2.dut.done !== exp_done) begin\n                                 ^~~~\n%Error: data/full_repos/permissive/426864978/lab2/task2/tb_rtl_task2.sv:40: Can\'t find definition of \'done\' in dotted variable: \'tb_rtl_task2.dut.done\'\n                $display("ERROR D: Expected done is %b, actual done is %b", exp_done, tb_rtl_task2.dut.done);\n                                                                                                       ^~~~\n%Error: data/full_repos/permissive/426864978/lab2/task2/tb_rtl_task2.sv:43: Can\'t find definition of \'VGA_PLOT\' in dotted variable: \'tb_rtl_task2.dut.VGA_PLOT\'\n            if (tb_rtl_task2.dut.VGA_PLOT !== exp_plot) begin\n                                 ^~~~~~~~\n%Error: data/full_repos/permissive/426864978/lab2/task2/tb_rtl_task2.sv:44: Can\'t find definition of \'VGA_PLOT\' in dotted variable: \'tb_rtl_task2.dut.VGA_PLOT\'\n                $display("ERROR E: Expected VGA_PLOT is %b, actual VGA_PLOT is %b", exp_plot, tb_rtl_task2.dut.VGA_PLOT);\n                                                                                                               ^~~~~~~~\n%Error: data/full_repos/permissive/426864978/lab2/task2/tb_rtl_task2.sv:58: Can\'t find definition of \'start\' in dotted variable: \'tb_rtl_task2.dut.start\'\n        if (tb_rtl_task2.dut.start !== 1\'b1) begin\n                             ^~~~~\n%Error: data/full_repos/permissive/426864978/lab2/task2/tb_rtl_task2.sv:59: Can\'t find definition of \'start\' in dotted variable: \'tb_rtl_task2.dut.start\'\n            $display("ERROR 1: Expected start is %b, actual start is %b", 1\'b1, tb_rtl_task2.dut.start);\n                                                                                                 ^~~~~\n%Error: data/full_repos/permissive/426864978/lab2/task2/tb_rtl_task2.sv:67: Can\'t find definition of \'start\' in dotted variable: \'tb_rtl_task2.dut.start\'\n        if (tb_rtl_task2.dut.start !== 1\'b1) begin\n                             ^~~~~\n%Error: data/full_repos/permissive/426864978/lab2/task2/tb_rtl_task2.sv:68: Can\'t find definition of \'start\' in dotted variable: \'tb_rtl_task2.dut.start\'\n            $display("ERROR 2: Expected start is %b, actual start is %b", 1\'b1, tb_rtl_task2.dut.start);\n                                                                                                 ^~~~~\n%Error: data/full_repos/permissive/426864978/lab2/task2/tb_rtl_task2.sv:76: Can\'t find definition of \'start\' in dotted variable: \'tb_rtl_task2.dut.start\'\n        if (tb_rtl_task2.dut.start !== 1\'b1) begin\n                             ^~~~~\n%Error: data/full_repos/permissive/426864978/lab2/task2/tb_rtl_task2.sv:77: Can\'t find definition of \'start\' in dotted variable: \'tb_rtl_task2.dut.start\'\n            $display("ERROR 3: Expected start is %b, actual start is %b", 1\'b1, tb_rtl_task2.dut.start);\n                                                                                                 ^~~~~\n%Error: data/full_repos/permissive/426864978/lab2/task2/tb_rtl_task2.sv:90: Can\'t find definition of \'start\' in dotted variable: \'tb_rtl_task2.dut.start\'\n        if (tb_rtl_task2.dut.start !== 1\'b0) begin\n                             ^~~~~\n%Error: data/full_repos/permissive/426864978/lab2/task2/tb_rtl_task2.sv:91: Can\'t find definition of \'start\' in dotted variable: \'tb_rtl_task2.dut.start\'\n            $display("ERROR 4: Expected start is %b, actual start is %b", 1\'b0, tb_rtl_task2.dut.start);\n                                                                                                 ^~~~~\n%Error: data/full_repos/permissive/426864978/lab2/task2/tb_rtl_task2.sv:97: Can\'t find definition of \'start\' in dotted variable: \'tb_rtl_task2.dut.start\'\n        if (tb_rtl_task2.dut.start !== 1\'b1) begin\n                             ^~~~~\n%Error: data/full_repos/permissive/426864978/lab2/task2/tb_rtl_task2.sv:98: Can\'t find definition of \'start\' in dotted variable: \'tb_rtl_task2.dut.start\'\n            $display("ERROR 5: Expected start is %b, actual start is %b", 1\'b1, tb_rtl_task2.dut.start);\n                                                                                                 ^~~~~\n%Error: Exiting due to 20 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_rtl_task2();


    logic CLOCK_50, VGA_HS, VGA_VS, VGA_CLK, VGA_PLOT, err;
    logic [3:0] KEY;
    logic [9:0] SW, LEDR;
    logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, VGA_Y;
    logic [7:0] VGA_R, VGA_G, VGA_B, VGA_X;
    logic [2:0] VGA_COLOUR;
    integer i, j, cycle_count;

    task2 dut(.*);

    initial begin
        CLOCK_50 = 0;
        forever #5 CLOCK_50 = ~CLOCK_50;
    end

    task validator;
        input [7:0] exp_x;
        input [6:0] exp_y;
        input [2:0] exp_colour;
        input exp_done, exp_plot;
        begin
            if (tb_rtl_task2.dut.VGA_X !== exp_x) begin
                $display("ERROR A: Expected VGA_X is %d, actual VGA_X is %d", exp_x, tb_rtl_task2.dut.VGA_X);
                err = 1'b1;
            end
            if (tb_rtl_task2.dut.VGA_Y !== exp_y) begin
                $display("ERROR B: Expected VGA_Y is %d, actual VGA_Y is %d", exp_y, tb_rtl_task2.dut.VGA_Y);
                err = 1'b1;
            end
            if (tb_rtl_task2.dut.VGA_COLOUR !== exp_colour) begin
                $display("ERROR C: Expected VGA_COLOUR is %d, actual VGA_COLOUR is %d", exp_colour, tb_rtl_task2.dut.VGA_COLOUR);
                err = 1'b1;
            end
            if (tb_rtl_task2.dut.done !== exp_done) begin
                $display("ERROR D: Expected done is %b, actual done is %b", exp_done, tb_rtl_task2.dut.done);
                err = 1'b1;
            end
            if (tb_rtl_task2.dut.VGA_PLOT !== exp_plot) begin
                $display("ERROR E: Expected VGA_PLOT is %b, actual VGA_PLOT is %b", exp_plot, tb_rtl_task2.dut.VGA_PLOT);
                err = 1'b1;
            end
        end
    endtask

    initial begin
        err = 1'b0;
        cycle_count = 0;


        KEY[3] = 1'bx;
        #10;
        validator(8'b0, 7'b0, 3'b0, 1'b0, 1'b0);
        if (tb_rtl_task2.dut.start !== 1'b1) begin
            $display("ERROR 1: Expected start is %b, actual start is %b", 1'b1, tb_rtl_task2.dut.start);
            err = 1'b1;
        end


        KEY[3] = 1'b0;
        #10;
        validator(8'b0, 7'b0, 3'b0, 1'b0, 1'b0);
        if (tb_rtl_task2.dut.start !== 1'b1) begin
            $display("ERROR 2: Expected start is %b, actual start is %b", 1'b1, tb_rtl_task2.dut.start);
            err = 1'b1;
        end


        KEY[3] = 1'b1;
        #10; cycle_count = cycle_count + 1;
        validator(8'b0, 7'b0, 3'b0, 1'b0, 1'b1);
        if (tb_rtl_task2.dut.start !== 1'b1) begin
            $display("ERROR 3: Expected start is %b, actual start is %b", 1'b1, tb_rtl_task2.dut.start);
            err = 1'b1;
        end

        for (i = 0; i < 160; i = i + 1) begin
            for (j = 0; j < 120; j = j + 1) begin
                validator(i, j, i % 8, 1'b0, 1'b1);
                #10; cycle_count = cycle_count + 1;
            end
        end

        #10; cycle_count = cycle_count + 1;
        validator(8'd0, 7'd0, 3'd0, 1'b1, 1'b0);
        if (tb_rtl_task2.dut.start !== 1'b0) begin
            $display("ERROR 4: Expected start is %b, actual start is %b", 1'b0, tb_rtl_task2.dut.start);
            err = 1'b1;
        end

        #10;
        validator(8'd0, 7'd0, 3'd0, 1'b0, 1'b0);
        if (tb_rtl_task2.dut.start !== 1'b1) begin
            $display("ERROR 5: Expected start is %b, actual start is %b", 1'b1, tb_rtl_task2.dut.start);
            err = 1'b1;
        end

        $display("TOTAL NO OF CYCLES: %d", cycle_count);

        if (~err) begin
            $display("SUCCESS: All tests passed.");
        end
        $stop;
    end

endmodule
module tb_rtl_task2();



    logic CLOCK_50, VGA_HS, VGA_VS, VGA_CLK, VGA_PLOT, err;
    logic [3:0] KEY;
    logic [9:0] SW, LEDR;
    logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, VGA_Y;
    logic [7:0] VGA_R, VGA_G, VGA_B, VGA_X;
    logic [2:0] VGA_COLOUR;
    integer i, j, cycle_count;

    task2 dut(.*);

    initial begin
        CLOCK_50 = 0;
        forever #5 CLOCK_50 = ~CLOCK_50;
    end

    task validator;
        input [7:0] exp_x;
        input [6:0] exp_y;
        input [2:0] exp_colour;
        input exp_done, exp_plot;
        begin
            if (tb_rtl_task2.dut.VGA_X !== exp_x) begin
                $display("ERROR A: Expected VGA_X is %d, actual VGA_X is %d", exp_x, tb_rtl_task2.dut.VGA_X);
                err = 1'b1;
            end
            if (tb_rtl_task2.dut.VGA_Y !== exp_y) begin
                $display("ERROR B: Expected VGA_Y is %d, actual VGA_Y is %d", exp_y, tb_rtl_task2.dut.VGA_Y);
                err = 1'b1;
            end
            if (tb_rtl_task2.dut.VGA_COLOUR !== exp_colour) begin
                $display("ERROR C: Expected VGA_COLOUR is %d, actual VGA_COLOUR is %d", exp_colour, tb_rtl_task2.dut.VGA_COLOUR);
                err = 1'b1;
            end
            if (tb_rtl_task2.dut.done !== exp_done) begin
                $display("ERROR D: Expected done is %b, actual done is %b", exp_done, tb_rtl_task2.dut.done);
                err = 1'b1;
            end
            if (tb_rtl_task2.dut.VGA_PLOT !== exp_plot) begin
                $display("ERROR E: Expected VGA_PLOT is %b, actual VGA_PLOT is %b", exp_plot, tb_rtl_task2.dut.VGA_PLOT);
                err = 1'b1;
            end
        end
    endtask

    initial begin
        err = 1'b0;
        cycle_count = 0;


        KEY[3] = 1'bx;
        #10;
        validator(8'b0, 7'b0, 3'b0, 1'b0, 1'b0);
        if (tb_rtl_task2.dut.start !== 1'b1) begin
            $display("ERROR 1: Expected start is %b, actual start is %b", 1'b1, tb_rtl_task2.dut.start);
            err = 1'b1;
        end


        KEY[3] = 1'b0;
        #10;
        validator(8'b0, 7'b0, 3'b0, 1'b0, 1'b0);
        if (tb_rtl_task2.dut.start !== 1'b1) begin
            $display("ERROR 2: Expected start is %b, actual start is %b", 1'b1, tb_rtl_task2.dut.start);
            err = 1'b1;
        end


        KEY[3] = 1'b1;
        #10; cycle_count = cycle_count + 1;
        validator(8'b0, 7'b0, 3'b0, 1'b0, 1'b1);
        if (tb_rtl_task2.dut.start !== 1'b1) begin
            $display("ERROR 3: Expected start is %b, actual start is %b", 1'b1, tb_rtl_task2.dut.start);
            err = 1'b1;
        end

        for (i = 0; i < 160; i = i + 1) begin
            for (j = 0; j < 120; j = j + 1) begin
                validator(i, j, i % 8, 1'b0, 1'b1);
                #10; cycle_count = cycle_count + 1;
            end
        end

        #10; cycle_count = cycle_count + 1;
        validator(8'd0, 7'd0, 3'd0, 1'b1, 1'b0);
        if (tb_rtl_task2.dut.start !== 1'b0) begin
            $display("ERROR 4: Expected start is %b, actual start is %b", 1'b0, tb_rtl_task2.dut.start);
            err = 1'b1;
        end

        #10;
        validator(8'd0, 7'd0, 3'd0, 1'b0, 1'b0);
        if (tb_rtl_task2.dut.start !== 1'b1) begin
            $display("ERROR 5: Expected start is %b, actual start is %b", 1'b1, tb_rtl_task2.dut.start);
            err = 1'b1;
        end

        $display("TOTAL NO OF CYCLES: %d", cycle_count);

        if (~err) begin
            $display("SUCCESS: All tests passed.");
        end
        $stop;
    end

endmodule