data/full_repos/permissive/417261953/src/debouncer.v
data/verilator_xmls/ac82b993-5f03-428f-b220-ad106744ae84.xml
module debouncer (
	input 		noisy,
	input 		clk,
	output reg 	debounced
);

	reg [7:0] shiftreg;
	
	always @ (posedge clk) 
	begin
		shiftreg[7:0] <= {shiftreg[6:0],noisy};
		if (shiftreg[7:0] == 8'b00000000) 
		  begin
			debounced <= 1'b1;
		  end 
		else if (shiftreg[7:0] == 8'b11111111) 
		  begin
			debounced <= 1'b0;
		  end 
		else 
		  begin
			debounced <= debounced;
		  end
	end

endmodule
module debouncer (
	input 		noisy,
	input 		clk,
	output reg 	debounced
);


	reg [7:0] shiftreg;
	
	always @ (posedge clk) 
	begin
		shiftreg[7:0] <= {shiftreg[6:0],noisy};
		if (shiftreg[7:0] == 8'b00000000) 
		  begin
			debounced <= 1'b1;
		  end 
		else if (shiftreg[7:0] == 8'b11111111) 
		  begin
			debounced <= 1'b0;
		  end 
		else 
		  begin
			debounced <= debounced;
		  end
	end

endmodule