data/full_repos/permissive/450205124/Assignment2/Q2-Johnson-Counter/A2Q2_d_flip_flop.v
data/verilator_xmls/c084ac94-84db-4cba-a686-9b689fdddbf6.xml
module d_flip_flop(q,d,clk);
    output reg q=1'b0;
    input d,clk;
        always @(posedge clk) begin
            q=d;
        end
endmodule
module d_flip_flop(q,d,clk);

    output reg q=1'b0;
    input d,clk;
        always @(posedge clk) begin
            q=d;
        end
endmodule