data/full_repos/permissive/437677776/rtl/verilog/wishbone_if.v
1: b'%Error: data/full_repos/permissive/437677776/rtl/verilog/wishbone_if.v:39: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/437677776/rtl/verilog,data/full_repos/permissive/437677776/defines.v\n             data/full_repos/permissive/437677776/rtl/verilog,data/full_repos/permissive/437677776/defines.v.v\n             data/full_repos/permissive/437677776/rtl/verilog,data/full_repos/permissive/437677776/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/437677776/rtl/verilog/wishbone_if.v:171: Define or directive not defined: \'`CPUREG_CONFIG0\'\n              `CPUREG_CONFIG0: begin\n              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437677776/rtl/verilog/wishbone_if.v:171: syntax error, unexpected \':\', expecting endcase\n              `CPUREG_CONFIG0: begin\n                             ^\n%Error: data/full_repos/permissive/437677776/rtl/verilog/wishbone_if.v:175: Define or directive not defined: \'`CPUREG_INT_PENDING\'\n              `CPUREG_INT_PENDING: begin\n              ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437677776/rtl/verilog/wishbone_if.v:175: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n              `CPUREG_INT_PENDING: begin\n                                   ^~~~~\n%Error: data/full_repos/permissive/437677776/rtl/verilog/wishbone_if.v:181: Define or directive not defined: \'`CPUREG_INT_STATUS\'\n              `CPUREG_INT_STATUS: begin\n              ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437677776/rtl/verilog/wishbone_if.v:181: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n              `CPUREG_INT_STATUS: begin\n                                  ^~~~~\n%Error: data/full_repos/permissive/437677776/rtl/verilog/wishbone_if.v:185: Define or directive not defined: \'`CPUREG_INT_MASK\'\n              `CPUREG_INT_MASK: begin\n              ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437677776/rtl/verilog/wishbone_if.v:185: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n              `CPUREG_INT_MASK: begin\n                                ^~~~~\n%Error: data/full_repos/permissive/437677776/rtl/verilog/wishbone_if.v:203: Define or directive not defined: \'`CPUREG_CONFIG0\'\n              `CPUREG_CONFIG0: begin\n              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437677776/rtl/verilog/wishbone_if.v:207: Define or directive not defined: \'`CPUREG_INT_PENDING\'\n              `CPUREG_INT_PENDING: begin\n              ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437677776/rtl/verilog/wishbone_if.v:207: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n              `CPUREG_INT_PENDING: begin\n                                   ^~~~~\n%Error: data/full_repos/permissive/437677776/rtl/verilog/wishbone_if.v:211: Define or directive not defined: \'`CPUREG_INT_MASK\'\n              `CPUREG_INT_MASK: begin\n              ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437677776/rtl/verilog/wishbone_if.v:211: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n              `CPUREG_INT_MASK: begin\n                                ^~~~~\n%Error: Cannot continue\n'
module wishbone_if(

  wb_dat_o, wb_ack_o, wb_int_o, ctrl_tx_enable,

  wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_we_i, wb_stb_i, wb_cyc_i,
  status_crc_error, status_fragment_error, status_txdfifo_ovflow,
  status_txdfifo_udflow, status_rxdfifo_ovflow, status_rxdfifo_udflow,
  status_pause_frame_rx, status_local_fault, status_remote_fault
  );


input         wb_clk_i;
input         wb_rst_i;

input  [7:0]  wb_adr_i;
input  [31:0] wb_dat_i;
input         wb_we_i;
input         wb_stb_i;
input         wb_cyc_i;

output [31:0] wb_dat_o;
output        wb_ack_o;
output        wb_int_o;

input         status_crc_error;
input         status_fragment_error;
   
input         status_txdfifo_ovflow;

input         status_txdfifo_udflow;

input         status_rxdfifo_ovflow;

input         status_rxdfifo_udflow;

input         status_pause_frame_rx;

input         status_local_fault;
input         status_remote_fault;

output        ctrl_tx_enable;




reg [31:0]              wb_dat_o;
reg                     wb_int_o;


reg  [0:0]              cpureg_config0;
reg  [8:0]              cpureg_int_pending;
reg  [8:0]              cpureg_int_mask;

reg                     cpuack;

reg                     status_remote_fault_d1;
reg                     status_local_fault_d1;




wire [8:0]             int_sources;






assign int_sources = {
                      status_fragment_error,
                      status_crc_error,

                      status_pause_frame_rx,

                      status_remote_fault ^ status_remote_fault_d1,
                      status_local_fault ^ status_local_fault_d1,

                      status_rxdfifo_udflow,
                      status_rxdfifo_ovflow,
                      status_txdfifo_udflow,
                      status_txdfifo_ovflow
                      };




assign ctrl_tx_enable = cpureg_config0[0];






assign wb_ack_o = cpuack && wb_stb_i;

always @(posedge wb_clk_i or posedge wb_rst_i) begin

    if (wb_rst_i == 1'b1) begin

        cpureg_config0 <= 1'h1;
        cpureg_int_pending <= 9'b0;
        cpureg_int_mask <= 9'b0;

        wb_dat_o <= 32'b0;
        wb_int_o <= 1'b0;

        cpuack <= 1'b0;

        status_remote_fault_d1 <= status_remote_fault;
        status_local_fault_d1 <= status_local_fault;

    end
    else begin

        wb_int_o <= |(cpureg_int_pending & cpureg_int_mask);

        cpureg_int_pending <= cpureg_int_pending | int_sources;

        cpuack <= wb_cyc_i && wb_stb_i;

        status_remote_fault_d1 <= status_remote_fault;
        status_local_fault_d1 <= status_local_fault;




        if (wb_cyc_i && wb_stb_i && !wb_we_i) begin

            case ({wb_adr_i[7:2], 2'b0})

              `CPUREG_CONFIG0: begin
                  wb_dat_o <= {31'b0, cpureg_config0};
              end
                           
              `CPUREG_INT_PENDING: begin
                  wb_dat_o <= {23'b0, cpureg_int_pending};
                  cpureg_int_pending <= int_sources;
                  wb_int_o <= 1'b0;
              end

              `CPUREG_INT_STATUS: begin
                  wb_dat_o <= {23'b0, int_sources};
              end

              `CPUREG_INT_MASK: begin
                  wb_dat_o <= {23'b0, cpureg_int_mask};
              end

              default: begin
              end

            endcase

        end




        if (wb_cyc_i && wb_stb_i && wb_we_i) begin

            case ({wb_adr_i[7:2], 2'b0})

              `CPUREG_CONFIG0: begin
                  cpureg_config0 <= wb_dat_i[0:0];
              end
                           
              `CPUREG_INT_PENDING: begin
                  cpureg_int_pending <= wb_dat_i[8:0] | cpureg_int_pending | int_sources;
              end

              `CPUREG_INT_MASK: begin
                  cpureg_int_mask <= wb_dat_i[8:0];
              end

              default: begin
              end

            endcase

        end

    end

end

endmodule
module wishbone_if(

  wb_dat_o, wb_ack_o, wb_int_o, ctrl_tx_enable,

  wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_we_i, wb_stb_i, wb_cyc_i,
  status_crc_error, status_fragment_error, status_txdfifo_ovflow,
  status_txdfifo_udflow, status_rxdfifo_ovflow, status_rxdfifo_udflow,
  status_pause_frame_rx, status_local_fault, status_remote_fault
  );



input         wb_clk_i;
input         wb_rst_i;

input  [7:0]  wb_adr_i;
input  [31:0] wb_dat_i;
input         wb_we_i;
input         wb_stb_i;
input         wb_cyc_i;

output [31:0] wb_dat_o;
output        wb_ack_o;
output        wb_int_o;

input         status_crc_error;
input         status_fragment_error;
   
input         status_txdfifo_ovflow;

input         status_txdfifo_udflow;

input         status_rxdfifo_ovflow;

input         status_rxdfifo_udflow;

input         status_pause_frame_rx;

input         status_local_fault;
input         status_remote_fault;

output        ctrl_tx_enable;




reg [31:0]              wb_dat_o;
reg                     wb_int_o;


reg  [0:0]              cpureg_config0;
reg  [8:0]              cpureg_int_pending;
reg  [8:0]              cpureg_int_mask;

reg                     cpuack;

reg                     status_remote_fault_d1;
reg                     status_local_fault_d1;




wire [8:0]             int_sources;






assign int_sources = {
                      status_fragment_error,
                      status_crc_error,

                      status_pause_frame_rx,

                      status_remote_fault ^ status_remote_fault_d1,
                      status_local_fault ^ status_local_fault_d1,

                      status_rxdfifo_udflow,
                      status_rxdfifo_ovflow,
                      status_txdfifo_udflow,
                      status_txdfifo_ovflow
                      };




assign ctrl_tx_enable = cpureg_config0[0];






assign wb_ack_o = cpuack && wb_stb_i;

always @(posedge wb_clk_i or posedge wb_rst_i) begin

    if (wb_rst_i == 1'b1) begin

        cpureg_config0 <= 1'h1;
        cpureg_int_pending <= 9'b0;
        cpureg_int_mask <= 9'b0;

        wb_dat_o <= 32'b0;
        wb_int_o <= 1'b0;

        cpuack <= 1'b0;

        status_remote_fault_d1 <= status_remote_fault;
        status_local_fault_d1 <= status_local_fault;

    end
    else begin

        wb_int_o <= |(cpureg_int_pending & cpureg_int_mask);

        cpureg_int_pending <= cpureg_int_pending | int_sources;

        cpuack <= wb_cyc_i && wb_stb_i;

        status_remote_fault_d1 <= status_remote_fault;
        status_local_fault_d1 <= status_local_fault;




        if (wb_cyc_i && wb_stb_i && !wb_we_i) begin

            case ({wb_adr_i[7:2], 2'b0})

              `CPUREG_CONFIG0: begin
                  wb_dat_o <= {31'b0, cpureg_config0};
              end
                           
              `CPUREG_INT_PENDING: begin
                  wb_dat_o <= {23'b0, cpureg_int_pending};
                  cpureg_int_pending <= int_sources;
                  wb_int_o <= 1'b0;
              end

              `CPUREG_INT_STATUS: begin
                  wb_dat_o <= {23'b0, int_sources};
              end

              `CPUREG_INT_MASK: begin
                  wb_dat_o <= {23'b0, cpureg_int_mask};
              end

              default: begin
              end

            endcase

        end




        if (wb_cyc_i && wb_stb_i && wb_we_i) begin

            case ({wb_adr_i[7:2], 2'b0})

              `CPUREG_CONFIG0: begin
                  cpureg_config0 <= wb_dat_i[0:0];
              end
                           
              `CPUREG_INT_PENDING: begin
                  cpureg_int_pending <= wb_dat_i[8:0] | cpureg_int_pending | int_sources;
              end

              `CPUREG_INT_MASK: begin
                  cpureg_int_mask <= wb_dat_i[8:0];
              end

              default: begin
              end

            endcase

        end

    end

end

endmodule