data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/aluwrap/tb_aluwrap.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/aluwrap/tb_aluwrap.v:9: Unsupported: Ignoring delay on this delayed statement.\n#1 clk=1;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/aluwrap/tb_aluwrap.v:10: Unsupported: Ignoring delay on this delayed statement.\n#1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/aluwrap/tb_aluwrap.v:62: Unsupported: Ignoring delay on this delayed statement.\n#3 t_rst = 1\'b1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/aluwrap/tb_aluwrap.v:63: Unsupported: Ignoring delay on this delayed statement.\n#2 t_rst = 1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/aluwrap/tb_aluwrap.v:65: Unsupported: Ignoring delay on this delayed statement.\n#2;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/aluwrap/tb_aluwrap.v:67: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/aluwrap/tb_aluwrap.v:73: Unsupported: Ignoring delay on this delayed statement.\n#2 en = 1\'b0;\n^\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/aluwrap/tb_aluwrap.v:74: Unsupported: wait statements\nwait(vld);\n^~~~\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/aluwrap/tb_aluwrap.v:75: Unsupported: Ignoring delay on this delayed statement.\n#200;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/aluwrap/tb_aluwrap.v:79: Unsupported: Ignoring delay on this delayed statement.\n#10 en = 1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/aluwrap/tb_aluwrap.v:80: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/aluwrap/tb_aluwrap.v:87: Unsupported: Ignoring delay on this delayed statement.\n#2;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/aluwrap/tb_aluwrap.v:90: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/aluwrap/tb_aluwrap.v:95: Unsupported: Ignoring delay on this delayed statement.\n#2 en = 1\'b0;\n^\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/aluwrap/tb_aluwrap.v:96: Unsupported: wait statements\nwait(vld);\n^~~~\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/aluwrap/tb_aluwrap.v:97: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/aluwrap/tb_aluwrap.v:105: Unsupported: Ignoring delay on this delayed statement.\n#2;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/aluwrap/tb_aluwrap.v:107: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/aluwrap/tb_aluwrap.v:114: Unsupported: Ignoring delay on this delayed statement.\n#2 en = 1\'b0;\n^\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/aluwrap/tb_aluwrap.v:115: Unsupported: wait statements\nwait(vld);\n^~~~\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/aluwrap/tb_aluwrap.v:116: Unsupported: Ignoring delay on this delayed statement.\n#200;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/aluwrap/tb_aluwrap.v:117: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/aluwrap/tb_aluwrap.v:126: Unsupported or unknown PLI call: $monitor\n$monitor ("exp cnt = %d",ialuwrap.imontexp.cnt);\n^~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/aluwrap/tb_aluwrap.v:139: Unsupported or unknown PLI call: $shm_open\n$shm_open ("my_waves");\n^~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/aluwrap/tb_aluwrap.v:140: Unsupported or unknown PLI call: $shm_probe\n$shm_probe (tb_aluwrap,"AC");\n^~~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/aluwrap/tb_aluwrap.v:141: Unsupported or unknown PLI call: $recordfile\n$recordfile("testsample.trn");\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/aluwrap/tb_aluwrap.v:142: Unsupported or unknown PLI call: $recordvars\n$recordvars();\n^~~~~~~~~~~\n%Error: Exiting due to 8 error(s), 19 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_aluwrap;

reg clk;
reg t_rst;

always begin
clk = 0;
#1 clk=1;
#1;
end


wire [1:0] t_status;

reg [255:0] a;
reg [255:0] b;
reg         c;

reg         en;
reg [3:0]   opcode;

wire [255:0] r;
wire [255:0] rswap;
wire         vld;

reg          swapop;



aluwrap ialuwrap
    (
     .clk(clk),
     .rst(t_rst),

     .status(t_status),

     .a(a),
     .b(b),
     .c(c),
     .en(en),
     .swapop(swapop),
     .swapvl(1'b1),
     .opcode(opcode),

     .r(r),
     .rswap(rswap),
     .vld(vld)
     );



initial begin
opcode[3] = 0;
opcode[2] = 0;
t_rst = 1'b0;
a = 256'd11;
b = 256'd1;
c = 1'b1;
en = 1'b0;
opcode[1:0] = 2'b00;
#3 t_rst = 1'b1;
#2 t_rst = 1'b0;
en = 1'b1;
#2;
en = 1'b0;
#100;
a = 256'd11;
b = 256'd12;
c = 1'b0;
opcode[1:0] = 2'b01;
en = 1'b1;
#2 en = 1'b0;
wait(vld);
#200;
opcode[1:0] = 2'b10;
a = 256'd4568979;
en = 1'b1;
#10 en = 1'b0;
#1000;
opcode[2] = 1;
a = 256'd103;
b = 256'd141;
c = 1'b0;
opcode[1:0] = 2'b11;

#2;
en = 1'b0;

#1000;
a = 256'd1045645;
b = 256'd1412;
swapop = 1;
en = 1'b1;
#2 en = 1'b0;
wait(vld);
#1000;
a = 256'd11;
b = 256'd1;
c = 1'b1;
en = 1'b0;
opcode[1:0] = 2'b00;
swapop = 1'b0;
en = 1'b1;
#2;
en = 1'b0;
#100;
c = 1'b0;
a = 256'h55df5d5850f47bad82149139979369fe498a9022a412b5e0bedd2cfc21c3ed91;
b = 256'h6B17D1F2E12C4247F8BCE6E563A440F277037D812DEB33A0F4A13945D898C296;
c = 1'b0;
opcode[1:0] = 2'b01;
en = 1'b1;
#2 en = 1'b0;
wait(vld);
#200;
#100;
$finish;
end

initial begin
$display ("==========OUTPUT==========");
end

initial begin
$monitor ("exp cnt = %d",ialuwrap.imontexp.cnt);
end

always@(posedge clk) begin
if(vld)
    begin
    $display ("Output : %d ", r);
    $display ("Output : %d ", rswap);
    end
end


initial begin
$shm_open ("my_waves");
$shm_probe (tb_aluwrap,"AC");
$recordfile("testsample.trn");
$recordvars();
end

endmodule
module tb_aluwrap;


reg clk;
reg t_rst;

always begin
clk = 0;
#1 clk=1;
#1;
end


wire [1:0] t_status;

reg [255:0] a;
reg [255:0] b;
reg         c;

reg         en;
reg [3:0]   opcode;

wire [255:0] r;
wire [255:0] rswap;
wire         vld;

reg          swapop;



aluwrap ialuwrap
    (
     .clk(clk),
     .rst(t_rst),

     .status(t_status),

     .a(a),
     .b(b),
     .c(c),
     .en(en),
     .swapop(swapop),
     .swapvl(1'b1),
     .opcode(opcode),

     .r(r),
     .rswap(rswap),
     .vld(vld)
     );



initial begin
opcode[3] = 0;
opcode[2] = 0;
t_rst = 1'b0;
a = 256'd11;
b = 256'd1;
c = 1'b1;
en = 1'b0;
opcode[1:0] = 2'b00;
#3 t_rst = 1'b1;
#2 t_rst = 1'b0;
en = 1'b1;
#2;
en = 1'b0;
#100;
a = 256'd11;
b = 256'd12;
c = 1'b0;
opcode[1:0] = 2'b01;
en = 1'b1;
#2 en = 1'b0;
wait(vld);
#200;
opcode[1:0] = 2'b10;
a = 256'd4568979;
en = 1'b1;
#10 en = 1'b0;
#1000;
opcode[2] = 1;
a = 256'd103;
b = 256'd141;
c = 1'b0;
opcode[1:0] = 2'b11;

#2;
en = 1'b0;

#1000;
a = 256'd1045645;
b = 256'd1412;
swapop = 1;
en = 1'b1;
#2 en = 1'b0;
wait(vld);
#1000;
a = 256'd11;
b = 256'd1;
c = 1'b1;
en = 1'b0;
opcode[1:0] = 2'b00;
swapop = 1'b0;
en = 1'b1;
#2;
en = 1'b0;
#100;
c = 1'b0;
a = 256'h55df5d5850f47bad82149139979369fe498a9022a412b5e0bedd2cfc21c3ed91;
b = 256'h6B17D1F2E12C4247F8BCE6E563A440F277037D812DEB33A0F4A13945D898C296;
c = 1'b0;
opcode[1:0] = 2'b01;
en = 1'b1;
#2 en = 1'b0;
wait(vld);
#200;
#100;
$finish;
end

initial begin
$display ("==========OUTPUT==========");
end

initial begin
$monitor ("exp cnt = %d",ialuwrap.imontexp.cnt);
end

always@(posedge clk) begin
if(vld)
    begin
    $display ("Output : %d ", r);
    $display ("Output : %d ", rswap);
    end
end


initial begin
$shm_open ("my_waves");
$shm_probe (tb_aluwrap,"AC");
$recordfile("testsample.trn");
$recordvars();
end

endmodule