data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/id_stage.sv
1: b"%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/id_stage.sv:23: syntax error, unexpected ::, expecting ')' or ','\n    input  ariane_pkg::fetch_entry_t      fetch_entry_i,\n                     ^~\n                                                                                                            : ... Perhaps 'ariane_pkg' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/id_stage.sv:25: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic                          fetch_entry_ready_o,  \n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/id_stage.sv:27: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output ariane_pkg::scoreboard_entry_t issue_entry_o,        \n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/id_stage.sv:29: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic                          is_ctrl_flow_o,       \n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/id_stage.sv:30: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic                          issue_instr_ack_i,    \n    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/id_stage.sv:32: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  riscv::priv_lvl_t              priv_lvl_i,           \n    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/id_stage.sv:35: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic [1:0]                    irq_i,\n    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/id_stage.sv:36: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  ariane_pkg::irq_ctrl_t         irq_ctrl_i,\n    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/id_stage.sv:38: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic                          tvm_i,\n    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/id_stage.sv:39: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic                          tw_i,\n    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/id_stage.sv:40: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic                          tsr_i\n    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/id_stage.sv:45: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n        ariane_pkg::scoreboard_entry_t sbe;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/id_stage.sv:47: syntax error, unexpected '}'\n    } issue_n, issue_q;\n    ^\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/id_stage.sv:50: syntax error, unexpected IDENTIFIER\n    ariane_pkg::scoreboard_entry_t   decoded_instruction;\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/id_stage.sv:59: syntax error, unexpected IDENTIFIER\n    compressed_decoder compressed_decoder_i (\n    ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 15 error(s)\n"
module id_stage (
    input  logic                          clk_i,
    input  logic                          rst_ni,

    input  logic                          flush_i,
    input  logic                          debug_req_i,

    input  ariane_pkg::fetch_entry_t      fetch_entry_i,
    input  logic                          fetch_entry_valid_i,
    output logic                          fetch_entry_ready_o,

    output ariane_pkg::scoreboard_entry_t issue_entry_o,
    output logic                          issue_entry_valid_o,
    output logic                          is_ctrl_flow_o,
    input  logic                          issue_instr_ack_i,

    input  riscv::priv_lvl_t              priv_lvl_i,
    input  riscv::xs_t                    fs_i,
    input  logic [2:0]                    frm_i,
    input  logic [1:0]                    irq_i,
    input  ariane_pkg::irq_ctrl_t         irq_ctrl_i,
    input  logic                          debug_mode_i,
    input  logic                          tvm_i,
    input  logic                          tw_i,
    input  logic                          tsr_i
);

    struct packed {
        logic                          valid;
        ariane_pkg::scoreboard_entry_t sbe;
        logic                          is_ctrl_flow;
    } issue_n, issue_q;

    logic                            is_control_flow_instr;
    ariane_pkg::scoreboard_entry_t   decoded_instruction;

    logic                is_illegal;
    logic                [31:0] instruction;
    logic                is_compressed;




    compressed_decoder compressed_decoder_i (
        .instr_i                 ( fetch_entry_i.instruction   ),
        .instr_o                 ( instruction                 ),
        .illegal_instr_o         ( is_illegal                  ),
        .is_compressed_o         ( is_compressed               )
    );



    decoder decoder_i (
        .debug_req_i,
        .irq_ctrl_i,
        .irq_i,
        .pc_i                    ( fetch_entry_i.address           ),
        .is_compressed_i         ( is_compressed                   ),
        .is_illegal_i            ( is_illegal                      ),
        .instruction_i           ( instruction                     ),
        .compressed_instr_i      ( fetch_entry_i.instruction[15:0] ),
        .branch_predict_i        ( fetch_entry_i.branch_predict    ),
        .ex_i                    ( fetch_entry_i.ex                ),
        .priv_lvl_i              ( priv_lvl_i                      ),
        .debug_mode_i            ( debug_mode_i                    ),
        .fs_i,
        .frm_i,
        .tvm_i,
        .tw_i,
        .tsr_i,
        .instruction_o           ( decoded_instruction          ),
        .is_control_flow_instr_o ( is_control_flow_instr        )
    );




    assign issue_entry_o = issue_q.sbe;
    assign issue_entry_valid_o = issue_q.valid;
    assign is_ctrl_flow_o = issue_q.is_ctrl_flow;

    always_comb begin
        issue_n     = issue_q;
        fetch_entry_ready_o = 1'b0;


        if (issue_instr_ack_i)
            issue_n.valid = 1'b0;




        if ((!issue_q.valid || issue_instr_ack_i) && fetch_entry_valid_i) begin
            fetch_entry_ready_o = 1'b1;
            issue_n = '{1'b1, decoded_instruction, is_control_flow_instr};
        end


        if (flush_i)
            issue_n.valid = 1'b0;
    end



    always_ff @(posedge clk_i or negedge rst_ni) begin
        if(~rst_ni) begin
            issue_q <= '0;
        end else begin
            issue_q <= issue_n;
        end
    end
endmodule
module id_stage (
    input  logic                          clk_i,
    input  logic                          rst_ni,

    input  logic                          flush_i,
    input  logic                          debug_req_i,

    input  ariane_pkg::fetch_entry_t      fetch_entry_i,
    input  logic                          fetch_entry_valid_i,
    output logic                          fetch_entry_ready_o,

    output ariane_pkg::scoreboard_entry_t issue_entry_o,
    output logic                          issue_entry_valid_o,
    output logic                          is_ctrl_flow_o,
    input  logic                          issue_instr_ack_i,

    input  riscv::priv_lvl_t              priv_lvl_i,
    input  riscv::xs_t                    fs_i,
    input  logic [2:0]                    frm_i,
    input  logic [1:0]                    irq_i,
    input  ariane_pkg::irq_ctrl_t         irq_ctrl_i,
    input  logic                          debug_mode_i,
    input  logic                          tvm_i,
    input  logic                          tw_i,
    input  logic                          tsr_i
);


    struct packed {
        logic                          valid;
        ariane_pkg::scoreboard_entry_t sbe;
        logic                          is_ctrl_flow;
    } issue_n, issue_q;

    logic                            is_control_flow_instr;
    ariane_pkg::scoreboard_entry_t   decoded_instruction;

    logic                is_illegal;
    logic                [31:0] instruction;
    logic                is_compressed;




    compressed_decoder compressed_decoder_i (
        .instr_i                 ( fetch_entry_i.instruction   ),
        .instr_o                 ( instruction                 ),
        .illegal_instr_o         ( is_illegal                  ),
        .is_compressed_o         ( is_compressed               )
    );



    decoder decoder_i (
        .debug_req_i,
        .irq_ctrl_i,
        .irq_i,
        .pc_i                    ( fetch_entry_i.address           ),
        .is_compressed_i         ( is_compressed                   ),
        .is_illegal_i            ( is_illegal                      ),
        .instruction_i           ( instruction                     ),
        .compressed_instr_i      ( fetch_entry_i.instruction[15:0] ),
        .branch_predict_i        ( fetch_entry_i.branch_predict    ),
        .ex_i                    ( fetch_entry_i.ex                ),
        .priv_lvl_i              ( priv_lvl_i                      ),
        .debug_mode_i            ( debug_mode_i                    ),
        .fs_i,
        .frm_i,
        .tvm_i,
        .tw_i,
        .tsr_i,
        .instruction_o           ( decoded_instruction          ),
        .is_control_flow_instr_o ( is_control_flow_instr        )
    );




    assign issue_entry_o = issue_q.sbe;
    assign issue_entry_valid_o = issue_q.valid;
    assign is_ctrl_flow_o = issue_q.is_ctrl_flow;

    always_comb begin
        issue_n     = issue_q;
        fetch_entry_ready_o = 1'b0;


        if (issue_instr_ack_i)
            issue_n.valid = 1'b0;




        if ((!issue_q.valid || issue_instr_ack_i) && fetch_entry_valid_i) begin
            fetch_entry_ready_o = 1'b1;
            issue_n = '{1'b1, decoded_instruction, is_control_flow_instr};
        end


        if (flush_i)
            issue_n.valid = 1'b0;
    end



    always_ff @(posedge clk_i or negedge rst_ni) begin
        if(~rst_ni) begin
            issue_q <= '0;
        end else begin
            issue_q <= issue_n;
        end
    end
endmodule