data/full_repos/permissive/522187840/Openlane/src/iiitb_sysarray.v
data/verilator_xmls/fb9a557c-bb5e-422f-a11f-2e468898cbfa.xml
module delay(a,b,a1,b1,clock);

parameter n = 31;

input [n:0] a,b;
input clock;
output [n:0] a1,b1;
reg [n:0] a1,b1;




function [n:0] allocate(input [n:0] a);
    begin
        allocate = 2*a-a;
    end
endfunction

always @(posedge clock)
begin
	a1 <= allocate(a);
	b1 <= allocate(b);
end

endmodule
module delay(a,b,a1,b1,clock);


parameter n = 31;

input [n:0] a,b;
input clock;
output [n:0] a1,b1;
reg [n:0] a1,b1;




function [n:0] allocate(input [n:0] a);
    begin
        allocate = 2*a-a;
    end
endfunction

always @(posedge clock)
begin
	a1 <= allocate(a);
	b1 <= allocate(b);
end

endmodule