data/full_repos/permissive/46454310/dsp/filterfir.v
1: b'%Error: data/full_repos/permissive/46454310/dsp/filterfir.v:15: Cannot find file containing module: \'dff\'\ndff u2(clk,rst,x,d11);\n^~~\n        ... Looked in:\n             data/full_repos/permissive/46454310/dsp,data/full_repos/permissive/46454310/dff\n             data/full_repos/permissive/46454310/dsp,data/full_repos/permissive/46454310/dff.v\n             data/full_repos/permissive/46454310/dsp,data/full_repos/permissive/46454310/dff.sv\n             dff\n             dff.v\n             dff.sv\n             obj_dir/dff\n             obj_dir/dff.v\n             obj_dir/dff.sv\n%Error: data/full_repos/permissive/46454310/dsp/filterfir.v:18: Cannot find file containing module: \'dff\'\ndff u4(clk,rst,d11,d12);\n^~~\n%Error: data/full_repos/permissive/46454310/dsp/filterfir.v:21: Cannot find file containing module: \'dff\'\ndff u6(clk,rst,d12,d13);\n^~~\n%Error: data/full_repos/permissive/46454310/dsp/filterfir.v:24: Cannot find file containing module: \'dff\'\ndff u8(clk,rst,d13,d14);\n^~~\n%Warning-WIDTH: data/full_repos/permissive/46454310/dsp/filterfir.v:26: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'d3\' generates 8 bits.\n                                                                      : ... In instance filterfir\nassign dataout=d3+m5;\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/46454310/dsp/filterfir.v:26: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'m5\' generates 8 bits.\n                                                                      : ... In instance filterfir\nassign dataout=d3+m5;\n                 ^\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module filterfir(clk,rst,x,dataout);
input [7:0]x;
input clk,rst;
output [9:0]dataout;
wire [7:0]d1,d2,d3;
wire [7:0]m1,m2,m3,m4,m5;
wire [7:0]d11,d12,d13,d14;
parameter h0=3'b101;
parameter h1=3'b100;
parameter h2=3'b011;
parameter h3=3'b010;
parameter h4=3'b001;
assign m1=x>>h0;
dff u2(clk,rst,x,d11);
assign m2=d11>>h1;
assign d1=m1+m2;
dff u4(clk,rst,d11,d12);
assign m3=d12>>h2;
assign d2=d1+m3;
dff u6(clk,rst,d12,d13);
assign m4=d13>>h3;
assign d3=d2+m4;
dff u8(clk,rst,d13,d14);
assign m5=d14>>h4;
assign dataout=d3+m5;
endmodule
module filterfir(clk,rst,x,dataout);

input [7:0]x;
input clk,rst;
output [9:0]dataout;
wire [7:0]d1,d2,d3;
wire [7:0]m1,m2,m3,m4,m5;
wire [7:0]d11,d12,d13,d14;
parameter h0=3'b101;
parameter h1=3'b100;
parameter h2=3'b011;
parameter h3=3'b010;
parameter h4=3'b001;
assign m1=x>>h0;
dff u2(clk,rst,x,d11);
assign m2=d11>>h1;
assign d1=m1+m2;
dff u4(clk,rst,d11,d12);
assign m3=d12>>h2;
assign d2=d1+m3;
dff u6(clk,rst,d12,d13);
assign m4=d13>>h3;
assign d3=d2+m4;
dff u8(clk,rst,d13,d14);
assign m5=d14>>h4;
assign dataout=d3+m5;
endmodule