data/full_repos/permissive/522668124/verilog/rtl/IMemory.sv
1: b'%Warning-IMPLICIT: data/full_repos/permissive/522668124/verilog/rtl/IMemory.sv:129: Signal definition not found, creating implicitly: \'i_type_immediate\'\n  assign i_type_immediate = {{20{instruction[31]}}, instruction[31:20]};\n         ^~~~~~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/522668124/verilog/rtl/IMemory.sv:131: Signal definition not found, creating implicitly: \'s_type_immediate\'\n                                                                                  : ... Suggested alternative: \'i_type_immediate\'\n  assign s_type_immediate = {{20{instruction[31]}}, instruction[31:25], instruction[11:7]};\n         ^~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/522668124/verilog/rtl/IMemory.sv:133: Signal definition not found, creating implicitly: \'b_type_immediate\'\n                                                                                  : ... Suggested alternative: \'i_type_immediate\'\n  assign b_type_immediate = {{19{instruction[31]}}, instruction[31], instruction[7], \n         ^~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/522668124/verilog/rtl/IMemory.sv:136: Signal definition not found, creating implicitly: \'u_type_immediate\'\n                                                                                  : ... Suggested alternative: \'b_type_immediate\'\n  assign u_type_immediate = {instruction[31:12], {12{1\'b0}}};\n         ^~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/522668124/verilog/rtl/IMemory.sv:138: Signal definition not found, creating implicitly: \'j_type_immediate\'\n                                                                                  : ... Suggested alternative: \'b_type_immediate\'\n  assign j_type_immediate = {{11{instruction[31]}}, instruction[31], instruction[19:12], \n         ^~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/IMemory.sv:83: Bit extraction of array[16:0] requires 5 bit index, not 4 bits.\n                                                                              : ... In instance IMemory\n      iram[la_instruction_select] <= la_instruction_input;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/IMemory.sv:88: Bit extraction of array[16:0] requires 5 bit index, not 4 bits.\n                                                                              : ... In instance IMemory\n    la_instruction_read <= iram[la_instruction_select];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/IMemory.sv:129: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                               : ... In instance IMemory\n  assign i_type_immediate = {{20{instruction[31]}}, instruction[31:20]};\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/IMemory.sv:131: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                               : ... In instance IMemory\n  assign s_type_immediate = {{20{instruction[31]}}, instruction[31:25], instruction[11:7]};\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/IMemory.sv:133: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                               : ... In instance IMemory\n  assign b_type_immediate = {{19{instruction[31]}}, instruction[31], instruction[7], \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/IMemory.sv:136: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                               : ... In instance IMemory\n  assign u_type_immediate = {instruction[31:12], {12{1\'b0}}};\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/IMemory.sv:138: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                               : ... In instance IMemory\n  assign j_type_immediate = {{11{instruction[31]}}, instruction[31], instruction[19:12], \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/IMemory.sv:142: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'immediate_reg\' generates 1 bits.\n                                                                               : ... In instance IMemory\n  assign immediate = immediate_reg;\n                   ^\n%Error: Exiting due to 13 warning(s)\n'
module IMemory

(
  `ifdef USE_POWER_PINS
      inout vccd1,
      inout vssd1,
  `endif
  
  input  logic        clk,
  input  logic        rst_n,
  input  logic [31:0] pc,
  
  input  logic [31:0] la_instruction_input,
  input  logic [3:0]  la_instruction_select,
  input  logic        la_instruction_write,

  output logic [5:0]  instruction_type_output,
  output logic [6:0]  opcode,
  output logic [4:0]  rd,
  output logic [4:0]  rs1,
  output logic [4:0]  rs2,
  output logic [2:0]  funct3,
  output logic [6:0]  funct7,
  output logic [31:0] immediate,
  
  output logic [31:0] la_instruction_read

);

  logic [31:0] iram[0:16];
  logic [31:0] instruction;
  
  always_ff  @(negedge clk) begin
    if (!rst_n && !la_instruction_write) begin
    

    
      iram[0] <= 32'b 000000111100_00000_000_00001_0010011;
      iram[1] <= 32'b 0000000_00000_00000_010_00000_0100011;
      iram[2] <= 32'b 000000000000_00000_010_00010_0000011;
      iram[3] <= 32'b 0_000000_00010_00001_000_1000_0_1100011;
      iram[4] <= 32'b 000000000001_00010_000_00010_0010011;
      iram[5] <= 32'b 0000000_00010_00000_010_00000_0100011;
      iram[6] <= 32'b 111111110000_00000_000_00000_1100111;
      iram[7] <= 32'h 00000000;
      iram[8] <= 32'h 00000000;
      iram[9] <= 32'h 00000000;
      iram[10] <= 32'h 00000000;
      iram[11] <= 32'h 00000000;
      iram[12] <= 32'h 00000000;
      iram[13] <= 32'h 00000000;
      iram[14] <= 32'h 00000000;
      iram[15] <= 32'b 1_1111100010_1_11111111_00000_1101111;
      
    end else if (la_instruction_write) begin
      iram[la_instruction_select] <= la_instruction_input;
    end
  end
 
  always_ff  @(posedge clk) begin 
    la_instruction_read <= iram[la_instruction_select];
    instruction <= iram[(pc>>2)];
  end

  
  logic r_type;
  logic i_type;
  logic s_type;
  logic b_type;
  logic u_type;
  logic j_type;
  logic [5:0] instruction_type;
  
  always_comb begin
   
    r_type = (opcode == 7'b0110011) ? 1 : 0;
    i_type = ((opcode == 7'b0010011) || (opcode == 7'b0000011) || (opcode == 7'b1100111)
        || (opcode == 7'b1110011)) ? 1 : 0;
    s_type = (opcode == 7'b0100011) ? 1 : 0;
    b_type = (opcode == 7'b1100011) ? 1 : 0;
    u_type = ((opcode == 7'b0110111) || (opcode == 7'b0010111)) ? 1 : 0;
    j_type = (opcode == 7'b1101111) ? 1 : 0;
    instruction_type = {j_type, u_type, b_type, s_type, i_type, r_type};
  
  end
  
  assign instruction_type_output = instruction_type;
  

  assign opcode = instruction[6:0];
  
  assign rd = instruction[11:7];
  
  assign rs1 = instruction[19:15];
  assign rs2 = instruction[24:20];
  
  assign funct3 = instruction[14:12];
  assign funct7 = instruction[31:25];
  

  
  assign i_type_immediate = {{20{instruction[31]}}, instruction[31:20]};
  
  assign s_type_immediate = {{20{instruction[31]}}, instruction[31:25], instruction[11:7]};
  
  assign b_type_immediate = {{19{instruction[31]}}, instruction[31], instruction[7], 
      instruction[30:25], instruction[11:8], {1{1'b0}}};
  
  assign u_type_immediate = {instruction[31:12], {12{1'b0}}};
  
  assign j_type_immediate = {{11{instruction[31]}}, instruction[31], instruction[19:12], 
      instruction[20], instruction[30:21], {1{1'b0}}};

  logic immediate_reg;
  assign immediate = immediate_reg;

  always_comb begin

    case (instruction_type)

      6'b000001: begin
        immediate_reg = 0;
        end

      6'b000010: begin
        immediate_reg = i_type_immediate;
        end

      6'b000100: begin
        immediate_reg = s_type_immediate;
        end

      6'b001000: begin
        immediate_reg = b_type_immediate;
        end

      6'b010000: begin
        immediate_reg = u_type_immediate;
        end

      6'b100000: begin
        immediate_reg = j_type_immediate;
        end
      default: begin
        immediate_reg = 0;
        end
    endcase
  end

endmodule
module IMemory

(
  `ifdef USE_POWER_PINS
      inout vccd1,
      inout vssd1,
  `endif
  
  input  logic        clk,
  input  logic        rst_n,
  input  logic [31:0] pc,
  
  input  logic [31:0] la_instruction_input,
  input  logic [3:0]  la_instruction_select,
  input  logic        la_instruction_write,

  output logic [5:0]  instruction_type_output,
  output logic [6:0]  opcode,
  output logic [4:0]  rd,
  output logic [4:0]  rs1,
  output logic [4:0]  rs2,
  output logic [2:0]  funct3,
  output logic [6:0]  funct7,
  output logic [31:0] immediate,
  
  output logic [31:0] la_instruction_read

);


  logic [31:0] iram[0:16];
  logic [31:0] instruction;
  
  always_ff  @(negedge clk) begin
    if (!rst_n && !la_instruction_write) begin
    

    
      iram[0] <= 32'b 000000111100_00000_000_00001_0010011;
      iram[1] <= 32'b 0000000_00000_00000_010_00000_0100011;
      iram[2] <= 32'b 000000000000_00000_010_00010_0000011;
      iram[3] <= 32'b 0_000000_00010_00001_000_1000_0_1100011;
      iram[4] <= 32'b 000000000001_00010_000_00010_0010011;
      iram[5] <= 32'b 0000000_00010_00000_010_00000_0100011;
      iram[6] <= 32'b 111111110000_00000_000_00000_1100111;
      iram[7] <= 32'h 00000000;
      iram[8] <= 32'h 00000000;
      iram[9] <= 32'h 00000000;
      iram[10] <= 32'h 00000000;
      iram[11] <= 32'h 00000000;
      iram[12] <= 32'h 00000000;
      iram[13] <= 32'h 00000000;
      iram[14] <= 32'h 00000000;
      iram[15] <= 32'b 1_1111100010_1_11111111_00000_1101111;
      
    end else if (la_instruction_write) begin
      iram[la_instruction_select] <= la_instruction_input;
    end
  end
 
  always_ff  @(posedge clk) begin 
    la_instruction_read <= iram[la_instruction_select];
    instruction <= iram[(pc>>2)];
  end

  
  logic r_type;
  logic i_type;
  logic s_type;
  logic b_type;
  logic u_type;
  logic j_type;
  logic [5:0] instruction_type;
  
  always_comb begin
   
    r_type = (opcode == 7'b0110011) ? 1 : 0;
    i_type = ((opcode == 7'b0010011) || (opcode == 7'b0000011) || (opcode == 7'b1100111)
        || (opcode == 7'b1110011)) ? 1 : 0;
    s_type = (opcode == 7'b0100011) ? 1 : 0;
    b_type = (opcode == 7'b1100011) ? 1 : 0;
    u_type = ((opcode == 7'b0110111) || (opcode == 7'b0010111)) ? 1 : 0;
    j_type = (opcode == 7'b1101111) ? 1 : 0;
    instruction_type = {j_type, u_type, b_type, s_type, i_type, r_type};
  
  end
  
  assign instruction_type_output = instruction_type;
  

  assign opcode = instruction[6:0];
  
  assign rd = instruction[11:7];
  
  assign rs1 = instruction[19:15];
  assign rs2 = instruction[24:20];
  
  assign funct3 = instruction[14:12];
  assign funct7 = instruction[31:25];
  

  
  assign i_type_immediate = {{20{instruction[31]}}, instruction[31:20]};
  
  assign s_type_immediate = {{20{instruction[31]}}, instruction[31:25], instruction[11:7]};
  
  assign b_type_immediate = {{19{instruction[31]}}, instruction[31], instruction[7], 
      instruction[30:25], instruction[11:8], {1{1'b0}}};
  
  assign u_type_immediate = {instruction[31:12], {12{1'b0}}};
  
  assign j_type_immediate = {{11{instruction[31]}}, instruction[31], instruction[19:12], 
      instruction[20], instruction[30:21], {1{1'b0}}};

  logic immediate_reg;
  assign immediate = immediate_reg;

  always_comb begin

    case (instruction_type)

      6'b000001: begin
        immediate_reg = 0;
        end

      6'b000010: begin
        immediate_reg = i_type_immediate;
        end

      6'b000100: begin
        immediate_reg = s_type_immediate;
        end

      6'b001000: begin
        immediate_reg = b_type_immediate;
        end

      6'b010000: begin
        immediate_reg = u_type_immediate;
        end

      6'b100000: begin
        immediate_reg = j_type_immediate;
        end
      default: begin
        immediate_reg = 0;
        end
    endcase
  end

endmodule