data/full_repos/permissive/447862055/Project2-SingleCycle-MIPS/reg_file.v
data/verilator_xmls/f1106a42-1a55-4a7d-9833-4094d7cc0f22.xml
module reg_file(
	input clk,
	input rst,
	input [`ADDR_WIDTH - 1:0] waddr,
	input [`ADDR_WIDTH - 1:0] raddr1,
	input [`ADDR_WIDTH - 1:0] raddr2,
	input wen,
	input [`DATA_WIDTH - 1:0] wdata,
	output [`DATA_WIDTH - 1:0] rdata1,
	output [`DATA_WIDTH - 1:0] rdata2
);

	reg [`DATA_WIDTH - 1:0] r [`DATA_WIDTH - 1:0];

	always @(posedge clk) begin
		if(wen & (|waddr)) begin
			r[waddr] <= wdata;
		end
	end
	
	assign rdata1 = {`DATA_WIDTH{|raddr1}} & r[raddr1];
	assign rdata2 = {`DATA_WIDTH{|raddr2}} & r[raddr2];

endmodule
module reg_file(
	input clk,
	input rst,
	input [`ADDR_WIDTH - 1:0] waddr,
	input [`ADDR_WIDTH - 1:0] raddr1,
	input [`ADDR_WIDTH - 1:0] raddr2,
	input wen,
	input [`DATA_WIDTH - 1:0] wdata,
	output [`DATA_WIDTH - 1:0] rdata1,
	output [`DATA_WIDTH - 1:0] rdata2
);


	reg [`DATA_WIDTH - 1:0] r [`DATA_WIDTH - 1:0];

	always @(posedge clk) begin
		if(wen & (|waddr)) begin
			r[waddr] <= wdata;
		end
	end
	
	assign rdata1 = {`DATA_WIDTH{|raddr1}} & r[raddr1];
	assign rdata2 = {`DATA_WIDTH{|raddr2}} & r[raddr2];

endmodule