data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/throttle_new.v
1: b'%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/throttle_new.v:2: Cannot find include file: syn_tb_defines.vh\n`include "syn_tb_defines.vh" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb,data/full_repos/permissive/509468557/syn_tb_defines.vh\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb,data/full_repos/permissive/509468557/syn_tb_defines.vh.v\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb,data/full_repos/permissive/509468557/syn_tb_defines.vh.sv\n             syn_tb_defines.vh\n             syn_tb_defines.vh.v\n             syn_tb_defines.vh.sv\n             obj_dir/syn_tb_defines.vh\n             obj_dir/syn_tb_defines.vh.v\n             obj_dir/syn_tb_defines.vh.sv\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/throttle_new.v:13: Define or directive not defined: \'`LOG2_Q\'\ninput [`LOG2_Q-1:0] id;\n       ^~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/throttle_new.v:18: Define or directive not defined: \'`LOG2_Q\'\nreg [`LOG2_Q-1:0] prev_id;\n     ^~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module throttle_new (clk, reset, perc, len, valid, id, ready);

input clk;
input reset;

input [31:0] perc;
input [3:0] len;
input valid;
input [`LOG2_Q-1:0] id;
output ready;

reg ready;
reg [15:0] d;
reg [`LOG2_Q-1:0] prev_id;

wire [15:0] dx;
wire [15:0] dy;
wire [15:0] dx2;
wire [15:0] dy2;

assign dy = perc;
assign dy2 = 2 * dy;
assign dx = 100;
assign dx2 = 2 * dx;


always @ (posedge clk or negedge reset) begin

	if (!reset) begin
		d <= dy2 - dx + `THROTTLE_CENTER;
		ready <= 0;
	end
	else begin
		if (valid == 1'b1 && !ready) begin
			if (d > `THROTTLE_CENTER) begin
				ready <= 1;
                d <= d + ((dy2 - dx2) * len);
			end
			else begin
				ready <= 0;
				d <= d + (dy2);
			end
		end
		else begin
			ready <= 0;
		end
	end

end


endmodule
module throttle_new (clk, reset, perc, len, valid, id, ready);


input clk;
input reset;

input [31:0] perc;
input [3:0] len;
input valid;
input [`LOG2_Q-1:0] id;
output ready;

reg ready;
reg [15:0] d;
reg [`LOG2_Q-1:0] prev_id;

wire [15:0] dx;
wire [15:0] dy;
wire [15:0] dx2;
wire [15:0] dy2;

assign dy = perc;
assign dy2 = 2 * dy;
assign dx = 100;
assign dx2 = 2 * dx;


always @ (posedge clk or negedge reset) begin

	if (!reset) begin
		d <= dy2 - dx + `THROTTLE_CENTER;
		ready <= 0;
	end
	else begin
		if (valid == 1'b1 && !ready) begin
			if (d > `THROTTLE_CENTER) begin
				ready <= 1;
                d <= d + ((dy2 - dx2) * len);
			end
			else begin
				ready <= 0;
				d <= d + (dy2);
			end
		end
		else begin
			ready <= 0;
		end
	end

end


endmodule