data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/nanolada/memory.v
1: b'%Error: data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/nanolada/memory.v:32: Cannot find file containing module: \'SevensegDisplay\'\nSevensegDisplay display(seg,an,digit0,digit1,digit2,digit3,clock);\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/nanolada,data/full_repos/permissive/423958267/SevensegDisplay\n             data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/nanolada,data/full_repos/permissive/423958267/SevensegDisplay.v\n             data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/nanolada,data/full_repos/permissive/423958267/SevensegDisplay.sv\n             SevensegDisplay\n             SevensegDisplay.v\n             SevensegDisplay.sv\n             obj_dir/SevensegDisplay\n             obj_dir/SevensegDisplay.v\n             obj_dir/SevensegDisplay.sv\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/nanolada/memory.v:42: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'digit0\' generates 4 bits.\n                                                                                                            : ... In instance memory\n  16\'hFFF0: data_out = digit0;\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/nanolada/memory.v:43: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'digit1\' generates 4 bits.\n                                                                                                            : ... In instance memory\n  16\'hFFF4: data_out = digit1;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/nanolada/memory.v:44: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'digit2\' generates 4 bits.\n                                                                                                            : ... In instance memory\n  16\'hFFF8: data_out = digit2;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/nanolada/memory.v:45: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'digit3\' generates 4 bits.\n                                                                                                            : ... In instance memory\n  16\'hFFFC: data_out = digit3;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/nanolada/memory.v:46: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                                            : ... In instance memory\n  16\'hFFE0: data_out = sw[3:0];\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/nanolada/memory.v:47: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                                            : ... In instance memory\n  16\'hFFE4: data_out = sw[7:4];\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/nanolada/memory.v:48: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                                            : ... In instance memory\n  16\'hFFE8: data_out = sw[11:8];\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/nanolada/memory.v:49: Bit extraction of array[65536:0] requires 17 bit index, not 16 bits.\n                                                                                                            : ... In instance memory\n  default: data_out = mem[address];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/nanolada/memory.v:49: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 4 bits.\n                                                                                                            : ... In instance memory\n  default: data_out = mem[address];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/nanolada/memory.v:57: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'data\' generates 32 bits.\n                                                                                                            : ... In instance memory\n   16\'hFFF0: digit0 = data;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/nanolada/memory.v:58: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'data\' generates 32 bits.\n                                                                                                            : ... In instance memory\n   16\'hFFF4: digit1 = data;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/nanolada/memory.v:59: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'data\' generates 32 bits.\n                                                                                                            : ... In instance memory\n   16\'hFFF8: digit2 = data;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/nanolada/memory.v:61: Bit extraction of array[65536:0] requires 17 bit index, not 16 bits.\n                                                                                                            : ... In instance memory\n   default: mem[address]=data;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab05/lab05.srcs/sources_1/imports/nanolada/memory.v:61: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'data\' generates 32 bits.\n                                                                                                            : ... In instance memory\n   default: mem[address]=data;\n                        ^\n%Error: Exiting due to 1 error(s), 14 warning(s)\n'
module memory(data,address,wr,clock,sw,seg,an);
parameter DATA_WIDTH=32;
parameter ADDR_WIDTH=16;

inout	[DATA_WIDTH-1:0]	data;
input	[ADDR_WIDTH-1:0]	address;
input wr;
input clock;
input [11:0] sw;
output [6:0] seg;
output [3:0] an;


reg	[3:0]	mem[0:1 << ADDR_WIDTH];

reg	[DATA_WIDTH-1:0]	data_out;

assign data=(wr==0) ? data_out:32'bz;

reg [3:0] digit0;
reg [3:0] digit1;
reg [3:0] digit2;
reg [3:0] digit3;
SevensegDisplay display(seg,an,digit0,digit1,digit2,digit3,clock);

initial
begin
	$readmemb("data.list",mem);
end

always @(address)
begin
	case (address)
		16'hFFF0: data_out = digit0;
		16'hFFF4: data_out = digit1;
		16'hFFF8: data_out = digit2;
		16'hFFFC: data_out = digit3;
		16'hFFE0: data_out = sw[3:0];
		16'hFFE4: data_out = sw[7:4];
		16'hFFE8: data_out = sw[11:8];
		default: data_out = mem[address];
	endcase
end

always @(posedge clock)
begin : MEM_WRITE
	if (wr) begin
		case (address)
			16'hFFF0: digit0 = data;
			16'hFFF4: digit1 = data;
			16'hFFF8: digit2 = data;
			16'hFFFC: digit3 = data[7:4];
			default: mem[address]=data;
		endcase
	end
end


endmodule
module memory(data,address,wr,clock,sw,seg,an);

parameter DATA_WIDTH=32;
parameter ADDR_WIDTH=16;

inout	[DATA_WIDTH-1:0]	data;
input	[ADDR_WIDTH-1:0]	address;
input wr;
input clock;
input [11:0] sw;
output [6:0] seg;
output [3:0] an;


reg	[3:0]	mem[0:1 << ADDR_WIDTH];

reg	[DATA_WIDTH-1:0]	data_out;

assign data=(wr==0) ? data_out:32'bz;

reg [3:0] digit0;
reg [3:0] digit1;
reg [3:0] digit2;
reg [3:0] digit3;
SevensegDisplay display(seg,an,digit0,digit1,digit2,digit3,clock);

initial
begin
	$readmemb("data.list",mem);
end

always @(address)
begin
	case (address)
		16'hFFF0: data_out = digit0;
		16'hFFF4: data_out = digit1;
		16'hFFF8: data_out = digit2;
		16'hFFFC: data_out = digit3;
		16'hFFE0: data_out = sw[3:0];
		16'hFFE4: data_out = sw[7:4];
		16'hFFE8: data_out = sw[11:8];
		default: data_out = mem[address];
	endcase
end

always @(posedge clock)
begin : MEM_WRITE
	if (wr) begin
		case (address)
			16'hFFF0: digit0 = data;
			16'hFFF4: digit1 = data;
			16'hFFF8: digit2 = data;
			16'hFFFC: digit3 = data[7:4];
			default: mem[address]=data;
		endcase
	end
end


endmodule