data/full_repos/permissive/48250786/mixColumns.v
1: b'%Warning-WIDTH: data/full_repos/permissive/48250786/mixColumns.v:78: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s AND generates 8 bits.\n                                                                   : ... In instance mixColumns\n  s0_2 = (s[0] & 8\'h80) ? ((s[0] << 1) ^ 8\'h1B) : (s[0] << 1);\n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/48250786/mixColumns.v:79: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s AND generates 8 bits.\n                                                                   : ... In instance mixColumns\n  s1_2 = (s[1] & 8\'h80) ? ((s[1] << 1) ^ 8\'h1B) : (s[1] << 1);\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/48250786/mixColumns.v:80: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s AND generates 8 bits.\n                                                                   : ... In instance mixColumns\n  s2_2 = (s[2] & 8\'h80) ? ((s[2] << 1) ^ 8\'h1B) : (s[2] << 1);\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/48250786/mixColumns.v:81: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s AND generates 8 bits.\n                                                                   : ... In instance mixColumns\n  s3_2 = (s[3] & 8\'h80) ? ((s[3] << 1) ^ 8\'h1B) : (s[3] << 1);\n                        ^\n%Error: data/full_repos/permissive/48250786/mixColumns.v:107: Cannot find file containing module: \'mixcolumns9b\'\n mixcolumns9b mix1(.dout({s0_9,s0_B}), .add(s[0]), .clock(clk), .en(1\'b1) );\n ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/48250786,data/full_repos/permissive/48250786/mixcolumns9b\n             data/full_repos/permissive/48250786,data/full_repos/permissive/48250786/mixcolumns9b.v\n             data/full_repos/permissive/48250786,data/full_repos/permissive/48250786/mixcolumns9b.sv\n             mixcolumns9b\n             mixcolumns9b.v\n             mixcolumns9b.sv\n             obj_dir/mixcolumns9b\n             obj_dir/mixcolumns9b.v\n             obj_dir/mixcolumns9b.sv\n%Error: data/full_repos/permissive/48250786/mixColumns.v:108: Cannot find file containing module: \'mixcolumnsde\'\n mixcolumnsde mix2(.dout({s0_D,s0_E}), .add(s[0]), .clock(clk), .en(1\'b1) );\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/48250786/mixColumns.v:111: Cannot find file containing module: \'mixcolumns9b\'\n mixcolumns9b mix3(.dout({s1_9,s1_B}), .add(s[1]), .clock(clk), .en(1\'b1) );\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/48250786/mixColumns.v:112: Cannot find file containing module: \'mixcolumnsde\'\n mixcolumnsde mix4(.dout({s1_D,s1_E}), .add(s[1]), .clock(clk), .en(1\'b1) );\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/48250786/mixColumns.v:115: Cannot find file containing module: \'mixcolumns9b\'\n mixcolumns9b mix5(.dout({s2_9,s2_B}), .add(s[2]), .clock(clk), .en(1\'b1) );\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/48250786/mixColumns.v:116: Cannot find file containing module: \'mixcolumnsde\'\n mixcolumnsde mix6(.dout({s2_D,s2_E}), .add(s[2]), .clock(clk), .en(1\'b1) );\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/48250786/mixColumns.v:119: Cannot find file containing module: \'mixcolumns9b\'\n mixcolumns9b mix7(.dout({s3_9,s3_B}), .add(s[3]), .clock(clk), .en(1\'b1) );\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/48250786/mixColumns.v:120: Cannot find file containing module: \'mixcolumnsde\'\n mixcolumnsde mix8(.dout({s3_D,s3_E}), .add(s[3]), .clock(clk), .en(1\'b1) );\n ^~~~~~~~~~~~\n%Error: Exiting due to 8 error(s), 4 warning(s)\n'
module mixColumns(
	 output [31:0] mixOut,
	 input [31:0] mixIn,
	 input clk,
	 input inv
    );
	 
	 wire [31:0] mixOutInv;
	 wire [31:0] mixOutNorm;
	 
	wire [7:0] s [0:3];
	wire [7:0] c [0:3];
	wire [7:0] cinv [0:3];


	reg [7:0] s0_2;
	reg [7:0] s0_3;
	reg [7:0] s1_2;
	reg [7:0] s1_3;
	reg [7:0] s2_2;
	reg [7:0] s2_3;
	reg [7:0] s3_2;
	reg [7:0] s3_3;
	reg [7:0] s0_1;
	reg [7:0] s1_1;
	reg [7:0] s2_1;
	reg [7:0] s3_1;
	
	wire [7:0] s0_9;
	wire [7:0] s0_B;
	wire [7:0] s0_D;
	wire [7:0] s0_E;
	wire [7:0] s1_9;
	wire [7:0] s1_B;
	wire [7:0] s1_D;
	wire [7:0] s1_E;
	wire [7:0] s2_9;
	wire [7:0] s2_B;
	wire [7:0] s2_D;
	wire [7:0] s2_E;
	wire [7:0] s3_9;
	wire [7:0] s3_B;
	wire [7:0] s3_D;
	wire [7:0] s3_E;


	assign {s[0], s[1], s[2], s[3]} = mixIn;
	





	


	always @(posedge clk) begin
		s0_2 = (s[0] & 8'h80) ? ((s[0] << 1) ^ 8'h1B) : (s[0] << 1);
		s1_2 = (s[1] & 8'h80) ? ((s[1] << 1) ^ 8'h1B) : (s[1] << 1);
		s2_2 = (s[2] & 8'h80) ? ((s[2] << 1) ^ 8'h1B) : (s[2] << 1);
		s3_2 = (s[3] & 8'h80) ? ((s[3] << 1) ^ 8'h1B) : (s[3] << 1);
		
		s0_3 = s0_2 ^ s[0];
		s1_3 = s1_2 ^ s[1];
		s2_3 = s2_2 ^ s[2];
		s3_3 = s3_2 ^ s[3];
		
		s0_1 = s[0];
		s1_1 = s[1];
		s2_1 = s[2];
		s3_1 = s[3];
	end
	

	assign c[0] = s0_2 ^ s1_3 ^ s2_1 ^ s3_1;
	assign c[1] = s0_1 ^ s1_2 ^ s2_3 ^ s3_1;
	assign c[2] = s0_1 ^ s1_1 ^ s2_2 ^ s3_3;
	assign c[3] = s0_3 ^ s1_1 ^ s2_1 ^ s3_2;
	





	

	mixcolumns9b mix1(.dout({s0_9,s0_B}), .add(s[0]), .clock(clk), .en(1'b1) );
	mixcolumnsde mix2(.dout({s0_D,s0_E}), .add(s[0]), .clock(clk), .en(1'b1) );
	

	mixcolumns9b mix3(.dout({s1_9,s1_B}), .add(s[1]), .clock(clk), .en(1'b1) );
	mixcolumnsde mix4(.dout({s1_D,s1_E}), .add(s[1]), .clock(clk), .en(1'b1) );
	

	mixcolumns9b mix5(.dout({s2_9,s2_B}), .add(s[2]), .clock(clk), .en(1'b1) );
	mixcolumnsde mix6(.dout({s2_D,s2_E}), .add(s[2]), .clock(clk), .en(1'b1) );
	

	mixcolumns9b mix7(.dout({s3_9,s3_B}), .add(s[3]), .clock(clk), .en(1'b1) );
	mixcolumnsde mix8(.dout({s3_D,s3_E}), .add(s[3]), .clock(clk), .en(1'b1) );
	
	
	assign cinv[0] = s0_E ^ s1_B ^ s2_D ^ s3_9;
	assign cinv[1] = s0_9 ^ s1_E ^ s2_B ^ s3_D;
	assign cinv[2] = s0_D ^ s1_9 ^ s2_E ^ s3_B;
	assign cinv[3] = s0_B ^ s1_D ^ s2_9 ^ s3_E;
	

	assign mixOutNorm = {c[0], c[1], c[2], c[3]};
	assign mixOutInv = {cinv[0], cinv[1], cinv[2], cinv[3]};

	assign mixOut = (inv)?(mixOutInv):(mixOutNorm);

endmodule
module mixColumns(
	 output [31:0] mixOut,
	 input [31:0] mixIn,
	 input clk,
	 input inv
    );

	 
	 wire [31:0] mixOutInv;
	 wire [31:0] mixOutNorm;
	 
	wire [7:0] s [0:3];
	wire [7:0] c [0:3];
	wire [7:0] cinv [0:3];


	reg [7:0] s0_2;
	reg [7:0] s0_3;
	reg [7:0] s1_2;
	reg [7:0] s1_3;
	reg [7:0] s2_2;
	reg [7:0] s2_3;
	reg [7:0] s3_2;
	reg [7:0] s3_3;
	reg [7:0] s0_1;
	reg [7:0] s1_1;
	reg [7:0] s2_1;
	reg [7:0] s3_1;
	
	wire [7:0] s0_9;
	wire [7:0] s0_B;
	wire [7:0] s0_D;
	wire [7:0] s0_E;
	wire [7:0] s1_9;
	wire [7:0] s1_B;
	wire [7:0] s1_D;
	wire [7:0] s1_E;
	wire [7:0] s2_9;
	wire [7:0] s2_B;
	wire [7:0] s2_D;
	wire [7:0] s2_E;
	wire [7:0] s3_9;
	wire [7:0] s3_B;
	wire [7:0] s3_D;
	wire [7:0] s3_E;


	assign {s[0], s[1], s[2], s[3]} = mixIn;
	





	


	always @(posedge clk) begin
		s0_2 = (s[0] & 8'h80) ? ((s[0] << 1) ^ 8'h1B) : (s[0] << 1);
		s1_2 = (s[1] & 8'h80) ? ((s[1] << 1) ^ 8'h1B) : (s[1] << 1);
		s2_2 = (s[2] & 8'h80) ? ((s[2] << 1) ^ 8'h1B) : (s[2] << 1);
		s3_2 = (s[3] & 8'h80) ? ((s[3] << 1) ^ 8'h1B) : (s[3] << 1);
		
		s0_3 = s0_2 ^ s[0];
		s1_3 = s1_2 ^ s[1];
		s2_3 = s2_2 ^ s[2];
		s3_3 = s3_2 ^ s[3];
		
		s0_1 = s[0];
		s1_1 = s[1];
		s2_1 = s[2];
		s3_1 = s[3];
	end
	

	assign c[0] = s0_2 ^ s1_3 ^ s2_1 ^ s3_1;
	assign c[1] = s0_1 ^ s1_2 ^ s2_3 ^ s3_1;
	assign c[2] = s0_1 ^ s1_1 ^ s2_2 ^ s3_3;
	assign c[3] = s0_3 ^ s1_1 ^ s2_1 ^ s3_2;
	





	

	mixcolumns9b mix1(.dout({s0_9,s0_B}), .add(s[0]), .clock(clk), .en(1'b1) );
	mixcolumnsde mix2(.dout({s0_D,s0_E}), .add(s[0]), .clock(clk), .en(1'b1) );
	

	mixcolumns9b mix3(.dout({s1_9,s1_B}), .add(s[1]), .clock(clk), .en(1'b1) );
	mixcolumnsde mix4(.dout({s1_D,s1_E}), .add(s[1]), .clock(clk), .en(1'b1) );
	

	mixcolumns9b mix5(.dout({s2_9,s2_B}), .add(s[2]), .clock(clk), .en(1'b1) );
	mixcolumnsde mix6(.dout({s2_D,s2_E}), .add(s[2]), .clock(clk), .en(1'b1) );
	

	mixcolumns9b mix7(.dout({s3_9,s3_B}), .add(s[3]), .clock(clk), .en(1'b1) );
	mixcolumnsde mix8(.dout({s3_D,s3_E}), .add(s[3]), .clock(clk), .en(1'b1) );
	
	
	assign cinv[0] = s0_E ^ s1_B ^ s2_D ^ s3_9;
	assign cinv[1] = s0_9 ^ s1_E ^ s2_B ^ s3_D;
	assign cinv[2] = s0_D ^ s1_9 ^ s2_E ^ s3_B;
	assign cinv[3] = s0_B ^ s1_D ^ s2_9 ^ s3_E;
	

	assign mixOutNorm = {c[0], c[1], c[2], c[3]};
	assign mixOutInv = {cinv[0], cinv[1], cinv[2], cinv[3]};

	assign mixOut = (inv)?(mixOutInv):(mixOutNorm);

endmodule