data/full_repos/permissive/441359809/src/yosys/tests/hana/test_simulation_always.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_simulation_always.v:10: Multiple top level modules\n                                                                                                        : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                        : ... Top module \'f1_test\'\nmodule f1_test(input [1:0] in, output reg [1:0] out);\n       ^~~~~~~\n                                                                                                        : ... Top module \'f2_test\'\nmodule f2_test(a, b, c, d, z);\n       ^~~~~~~\n                                                                                                        : ... Top module \'f3_test\'\nmodule f3_test (in1, in2, out);\n       ^~~~~~~\n                                                                                                        : ... Top module \'f4_test\'\nmodule f4_test(ctrl, in1,  in2, out);\n       ^~~~~~~\n                                                                                                        : ... Top module \'f5_test\'\nmodule f5_test(input in, output reg out);\n       ^~~~~~~\n                                                                                                        : ... Top module \'f6_NonBlockingEx\'\nmodule f6_NonBlockingEx(clk, merge, er, xmit, fddi, claim);\n       ^~~~~~~~~~~~~~~~\n                                                                                                        : ... Top module \'f7_FlipFlop\'\nmodule f7_FlipFlop(clk, cs, ns);\n       ^~~~~~~~~~~\n                                                                                                        : ... Top module \'f8_inc\'\nmodule f8_inc(clock, counter);\n       ^~~~~~\n                                                                                                        : ... Top module \'f9_MyCounter\'\nmodule f9_MyCounter (clock, preset, updown, presetdata, counter);\n       ^~~~~~~~~~~~\n                                                                                                        : ... Top module \'f10_FlipFlop\'\nmodule f10_FlipFlop(clock, cs, ns);\n       ^~~~~~~~~~~~\n                                                                                                        : ... Top module \'f11_test\'\nmodule f11_test(input in, output reg [1:0] out);\n       ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_simulation_always.v:131: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'in\' generates 1 bits.\n                                                                                                      : ... In instance f11_test\n        out = in;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_simulation_always.v:81: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'cs\' generates 8 bits.\n                                                                                                     : ... In instance f7_FlipFlop\n    is <= cs;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_simulation_always.v:83: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'is\' generates 32 bits.\n                                                                                                     : ... In instance f7_FlipFlop\nassign ns = is;\n          ^\n%Error: Exiting due to 4 warning(s)\n'
module f3_test (in1, in2, out);
input  in1, in2;
output  reg out;

always @ ( in1 or in2)
	if(in1 > in2)
		out = in1;
	else
		out = in2;
endmodule
module f3_test (in1, in2, out);

input  in1, in2;
output  reg out;

always @ ( in1 or in2)
	if(in1 > in2)
		out = in1;
	else
		out = in2;
endmodule