data/full_repos/permissive/418692101/EnhancedSuperTestbench.sv
1: b'%Error: data/full_repos/permissive/418692101/EnhancedSuperTestbench.sv:2: Cannot find include file: TOP.v\n`include "TOP.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418692101,data/full_repos/permissive/418692101/TOP.v\n             data/full_repos/permissive/418692101,data/full_repos/permissive/418692101/TOP.v.v\n             data/full_repos/permissive/418692101,data/full_repos/permissive/418692101/TOP.v.sv\n             TOP.v\n             TOP.v.v\n             TOP.v.sv\n             obj_dir/TOP.v\n             obj_dir/TOP.v.v\n             obj_dir/TOP.v.sv\n%Error: Exiting due to 1 error(s)\n'
module EnhancedSuperTestbench;
    wire [31:0] MemInput [0:199];
    wire [31:0] SeqInput [0:199];
    IntelligentFileReader IFT(MemInput, SeqInput);
    reg ini;
    reg clk;
    reg nrst;
    wire WR;
    wire CS;
    wire [9:0] ADDR;
    reg PassClock;
    reg [3:0] PassNumber;
    wire [31:0] DATA;

    reg [31:0] dtw_in;
    reg dtw_valid;
    wire dtw_ready;
    TOP uut(clk, nrst, dtw_valid, dtw_in, DATA, ADDR, WR, CS, dtw_ready);
    EnhancedSRAM ES(clk, WR, CS, ADDR, PassClock, PassNumber, DATA);
    initial begin
        PassClock = 1'b1;
        PassNumber = 4'b0;
        ini = 1'b0;
        clk = 1'b0;
        nrst = 1'b0;
        dtw_in = 32'd0;
        dtw_valid = 1'b0;
        #(10 * `cycle);
        nrst = 1'b1;
    end
    always #(100 * `cycle) PassClock = ~PassClock;
    always #(`cycle / 2) clk = ~clk;
    always @(negedge PassClock) begin
        if (ini == 1'b0) begin
            ini = 1'b1;
        end else begin
            PassNumber = PassNumber + 4'b1;
        end
    end
    integer counter = 0;
    always @(posedge PassClock) begin
        #(`cycle * 10) dtw_valid = 1'b1;
        repeat(20) begin
            dtw_in = SeqInput[PassNumber * 20 + counter];
            #(`cycle);
            counter = counter + 1;
        end
        counter = 0;
        dtw_valid = 1'b0;
        dtw_in = 32'h0;
    end
endmodule
module EnhancedSuperTestbench;

    wire [31:0] MemInput [0:199];
    wire [31:0] SeqInput [0:199];
    IntelligentFileReader IFT(MemInput, SeqInput);
    reg ini;
    reg clk;
    reg nrst;
    wire WR;
    wire CS;
    wire [9:0] ADDR;
    reg PassClock;
    reg [3:0] PassNumber;
    wire [31:0] DATA;

    reg [31:0] dtw_in;
    reg dtw_valid;
    wire dtw_ready;
    TOP uut(clk, nrst, dtw_valid, dtw_in, DATA, ADDR, WR, CS, dtw_ready);
    EnhancedSRAM ES(clk, WR, CS, ADDR, PassClock, PassNumber, DATA);
    initial begin
        PassClock = 1'b1;
        PassNumber = 4'b0;
        ini = 1'b0;
        clk = 1'b0;
        nrst = 1'b0;
        dtw_in = 32'd0;
        dtw_valid = 1'b0;
        #(10 * `cycle);
        nrst = 1'b1;
    end
    always #(100 * `cycle) PassClock = ~PassClock;
    always #(`cycle / 2) clk = ~clk;
    always @(negedge PassClock) begin
        if (ini == 1'b0) begin
            ini = 1'b1;
        end else begin
            PassNumber = PassNumber + 4'b1;
        end
    end
    integer counter = 0;
    always @(posedge PassClock) begin
        #(`cycle * 10) dtw_valid = 1'b1;
        repeat(20) begin
            dtw_in = SeqInput[PassNumber * 20 + counter];
            #(`cycle);
            counter = counter + 1;
        end
        counter = 0;
        dtw_valid = 1'b0;
        dtw_in = 32'h0;
    end
endmodule