data/full_repos/permissive/485467282/buffer.v
data/verilator_xmls/5190ef51-b961-4ca8-86b1-a0f4fc1e5bcc.xml
module buffer(input [15:0] in, 
              input en, clk,
              output reg [15:0] out);
    
    always @(*) begin
        if(en)
            out <= in;
        else
            out <= 16'bx;
    end

endmodule
module buffer(input [15:0] in, 
              input en, clk,
              output reg [15:0] out);

    
    always @(*) begin
        if(en)
            out <= in;
        else
            out <= 16'bx;
    end

endmodule