data/full_repos/permissive/47037127/intpipe_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/47037127/intpipe_testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n #0 clk=!clk;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/47037127/intpipe_testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #1 aDat=aDat+1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/47037127/intpipe_testbench.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #1 aDat=aDat;\n  ^\n%Error: data/full_repos/permissive/47037127/intpipe_testbench.v:65: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("intpipe_testbench.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/47037127/intpipe_testbench.v:66: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/47037127/intpipe_testbench.v:71: Unsupported or unknown PLI call: $monitor\n $monitor("%d, \\t%b, \\t%b, \\t%b, \\t%b, \\t%b, \\t%b", $time, clk, opCode, aDat, bDat, cOut, cWrite);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/47037127/intpipe_testbench.v:75: Unsupported: Ignoring delay on this delayed statement.\n #128 $finish;\n ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module intpipe_testbench();

reg clk, pause, empty;
reg [4:0] opCode;
reg [3:0] a;
reg [3:0] b;
reg [3:0] c;
reg [15:0] aDat;
reg [15:0] bDat;
wire [3:0] aSel;
wire [3:0] bSel;
wire [3:0] cSel;
wire [15:0] cOut;
wire cWrite;

reg [15:0] ctr;

intpipe p(clk, pause, empty, opCode, a, b, c, aDat, bDat, aSel, bSel, cSel, cOut, cWrite);

initial begin
 ctr=0;
 clk=0;
 pause=0;
 empty=0;
 opCode=1;
 a=0;
 b=1;
 c=2;
 aDat=1;
 bDat=1;
end

always begin
 #0 clk=!clk;
 if(clk==1) begin
  #1 aDat=aDat+1;
 end
 else begin
  #1 aDat=aDat;
 end
 
 ctr=ctr+1;
 

 if(ctr==10) begin
  opCode=0;
 end
 
 if(ctr==15) begin
  opCode=3;
 end
 

 if(ctr==20) begin
  pause=1;
 end
 
 if(ctr==30) begin
  pause=0;
 end
end

initial begin
 $dumpfile("intpipe_testbench.vcd");
 $dumpvars;
end

initial begin
 $display("\t\tTime, \tClock, \tA, \tB, \tOp, \tOut, \tcWrite");
 $monitor("%d, \t%b, \t%b, \t%b, \t%b, \t%b, \t%b", $time, clk, opCode, aDat, bDat, cOut, cWrite);
end

initial 
 #128 $finish;
 
endmodule
module intpipe_testbench();


reg clk, pause, empty;
reg [4:0] opCode;
reg [3:0] a;
reg [3:0] b;
reg [3:0] c;
reg [15:0] aDat;
reg [15:0] bDat;
wire [3:0] aSel;
wire [3:0] bSel;
wire [3:0] cSel;
wire [15:0] cOut;
wire cWrite;

reg [15:0] ctr;

intpipe p(clk, pause, empty, opCode, a, b, c, aDat, bDat, aSel, bSel, cSel, cOut, cWrite);

initial begin
 ctr=0;
 clk=0;
 pause=0;
 empty=0;
 opCode=1;
 a=0;
 b=1;
 c=2;
 aDat=1;
 bDat=1;
end

always begin
 #0 clk=!clk;
 if(clk==1) begin
  #1 aDat=aDat+1;
 end
 else begin
  #1 aDat=aDat;
 end
 
 ctr=ctr+1;
 

 if(ctr==10) begin
  opCode=0;
 end
 
 if(ctr==15) begin
  opCode=3;
 end
 

 if(ctr==20) begin
  pause=1;
 end
 
 if(ctr==30) begin
  pause=0;
 end
end

initial begin
 $dumpfile("intpipe_testbench.vcd");
 $dumpvars;
end

initial begin
 $display("\t\tTime, \tClock, \tA, \tB, \tOp, \tOut, \tcWrite");
 $monitor("%d, \t%b, \t%b, \t%b, \t%b, \t%b, \t%b", $time, clk, opCode, aDat, bDat, cOut, cWrite);
end

initial 
 #128 $finish;
 
endmodule