data/full_repos/permissive/433640910/ArithmeticLogicUnit/alu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/433640910/ArithmeticLogicUnit/alu.v:50: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 4 bits.\n                                                                                 : ... In instance part2\n   3\'b011: ALUtemp = (Data|Data_b) ? 8\'b00000001 : 8\'b0;\n                                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module part2(Clock, Reset_b, Data, Function, ALUout);

	input [3:0] Data;
	input Reset_b, Clock;
	input [2:0] Function;
	
	output reg[7:0]ALUout;
	reg [7:0]ALUtemp;
	
	wire [3:0]Data_b;
	assign Data_b = ALUout[3:0];

	wire [3:0]sum, c_out;
	rippleadder u0(Data,Data_b,0, sum, c_out);
	
	wire[4:0]sum2;
	assign sum2 = Data + Data_b; 
		
	
	always @(*)
	begin
		case(Function[2:0])
			3'b000: ALUtemp = {3'b0, c_out[3], sum};
			3'b001: ALUtemp = {3'b0, sum2};
			3'b010: ALUtemp = {{4{Data_b[3]}}, Data_b};
			3'b011: ALUtemp = (Data|Data_b) ? 8'b00000001 : 8'b0;
			3'b100: ALUtemp = ((&Data) & (&Data_b)) ? 8'b00000001 : 8'b0;
			3'b101: ALUtemp = {4'b0000,Data_b} << Data;	
			3'b110: ALUtemp = Data * Data_b;
			3'b111: ALUtemp = ALUout;
			default: ALUtemp = 8'b0;
		endcase
	end	


	always @(posedge Clock)
	begin
		if(Reset_b == 1'b0)
		
			ALUout <= 8'b00000000;
		else
			ALUout <= ALUtemp;
	end


endmodule
module part2(Clock, Reset_b, Data, Function, ALUout);


	input [3:0] Data;
	input Reset_b, Clock;
	input [2:0] Function;
	
	output reg[7:0]ALUout;
	reg [7:0]ALUtemp;
	
	wire [3:0]Data_b;
	assign Data_b = ALUout[3:0];

	wire [3:0]sum, c_out;
	rippleadder u0(Data,Data_b,0, sum, c_out);
	
	wire[4:0]sum2;
	assign sum2 = Data + Data_b; 
		
	
	always @(*)
	begin
		case(Function[2:0])
			3'b000: ALUtemp = {3'b0, c_out[3], sum};
			3'b001: ALUtemp = {3'b0, sum2};
			3'b010: ALUtemp = {{4{Data_b[3]}}, Data_b};
			3'b011: ALUtemp = (Data|Data_b) ? 8'b00000001 : 8'b0;
			3'b100: ALUtemp = ((&Data) & (&Data_b)) ? 8'b00000001 : 8'b0;
			3'b101: ALUtemp = {4'b0000,Data_b} << Data;	
			3'b110: ALUtemp = Data * Data_b;
			3'b111: ALUtemp = ALUout;
			default: ALUtemp = 8'b0;
		endcase
	end	


	always @(posedge Clock)
	begin
		if(Reset_b == 1'b0)
		
			ALUout <= 8'b00000000;
		else
			ALUout <= ALUtemp;
	end


endmodule