data/full_repos/permissive/504677412/src/fifo_top/fifo_fwft_18x1024.v
1: b'%Error: data/full_repos/permissive/504677412/src/fifo_top/fifo_fwft_18x1024.v:23: syntax error, unexpected IDENTIFIER\ndYs+cPrvRlu1ZRdQ5InKmrlihFG6n/khaMDd278U/tj5NR5NxDkyOmBejbTmEDXtjuu/byV3xDJ8\n^~~\n%Error: Exiting due to 1 error(s)\n'
module fifo_fwft_18x1024 (
  Data,
  Clk,
  WrEn,
  RdEn,
  Reset,
  Wnum,
  Almost_Empty,
  Almost_Full,
  Q,
  Empty,
  Full
)
;
input [17:0] Data;
input Clk;
input WrEn;
input RdEn;
input Reset;
output [10:0] Wnum;
output Almost_Empty;
output Almost_Full;
output [17:0] Q;
output Empty;
output Full;
wire VCC;
wire GND;
  \~fifo_sc.fifo_fwft_18x1024  fifo_sc_inst (
    .Clk(Clk),
    .Reset(Reset),
    .WrEn(WrEn),
    .RdEn(RdEn),
    .Data(Data[17:0]),
    .Full(Full),
    .Almost_Empty(Almost_Empty),
    .Almost_Full(Almost_Full),
    .Empty(Empty),
    .Wnum(Wnum[10:0]),
    .Q(Q[17:0])
);
  VCC VCC_cZ (
    .V(VCC)
);
  GND GND_cZ (
    .G(GND)
);
  GSR GSR (
    .GSRI(VCC) 
);
endmodule
module fifo_fwft_18x1024 (
  Data,
  Clk,
  WrEn,
  RdEn,
  Reset,
  Wnum,
  Almost_Empty,
  Almost_Full,
  Q,
  Empty,
  Full
)
;

input [17:0] Data;
input Clk;
input WrEn;
input RdEn;
input Reset;
output [10:0] Wnum;
output Almost_Empty;
output Almost_Full;
output [17:0] Q;
output Empty;
output Full;
wire VCC;
wire GND;
  \~fifo_sc.fifo_fwft_18x1024  fifo_sc_inst (
    .Clk(Clk),
    .Reset(Reset),
    .WrEn(WrEn),
    .RdEn(RdEn),
    .Data(Data[17:0]),
    .Full(Full),
    .Almost_Empty(Almost_Empty),
    .Almost_Full(Almost_Full),
    .Empty(Empty),
    .Wnum(Wnum[10:0]),
    .Q(Q[17:0])
);
  VCC VCC_cZ (
    .V(VCC)
);
  GND GND_cZ (
    .G(GND)
);
  GSR GSR (
    .GSRI(VCC) 
);
endmodule