data/full_repos/permissive/488482526/test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:26: Unsupported: Ignoring delay on this delayed statement.\n   #(PERIOD_CLK-(PERIOD_CLK*DUTY_CYCLE_CLK)) clk = 1\'b1;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:27: Unsupported: Ignoring delay on this delayed statement.\n   #(PERIOD_CLK*DUTY_CYCLE_CLK);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:53: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/488482526/test.v:56: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:58: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:60: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:62: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:64: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:66: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:68: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:70: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:72: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:74: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:76: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:78: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:80: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:82: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:84: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:86: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:88: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:90: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:92: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:94: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:96: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:98: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:100: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:102: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:104: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:106: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:108: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:110: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:112: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:114: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:116: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:118: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:120: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:122: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:124: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:126: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:128: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:130: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:132: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:134: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:136: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:138: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:140: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:142: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:144: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:146: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:148: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:150: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:154: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:156: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:158: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:160: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:162: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:164: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:166: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:168: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:170: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:172: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:174: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:176: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:178: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:180: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:182: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:184: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:186: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:188: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:190: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:192: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:194: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:196: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:198: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:200: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:202: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:204: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:206: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:208: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:210: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:212: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:214: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:216: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:218: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:220: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:222: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:224: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:226: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:228: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:230: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:232: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:234: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:236: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:238: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:240: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:242: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:244: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:246: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:248: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:250: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:252: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:254: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Error: data/full_repos/permissive/488482526/test.v:256: syntax error, unexpected \'@\'\n @(posedge column[7]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:258: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK*0.2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:260: Unsupported: Ignoring delay on this delayed statement.\n #(PERIOD_CLK);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488482526/test.v:263: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: Exiting due to 34 error(s), 73 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

reg clk = 0;
reg btn;
reg switch;
reg UP;
reg STEP;
reg SYS_NRST;

wire [7:0]row;
wire [7:0]column;

wire rst;
wire CE_1MHZ;
wire [3:0]SEQ;

parameter PERIOD_CLK = 20.8;
parameter DUTY_CYCLE_CLK = 0.4;

initial
	forever
		begin
			clk = 1'b0;
			#(PERIOD_CLK-(PERIOD_CLK*DUTY_CYCLE_CLK)) clk = 1'b1;
			#(PERIOD_CLK*DUTY_CYCLE_CLK);
		end


initial
	begin
		SYS_NRST = 0;
		#100;
		SYS_NRST = 1;
	end

reg [1:0] RST_S;

always @ (posedge clk, negedge SYS_NRST)
	if(!SYS_NRST) 
		RST_S <= 2'b11;
	else 
		RST_S <= {RST_S[0], 1'b0};

assign rst = RST_S[1];

initial begin

	STEP = 0;
	UP = 1;

	#100;


	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;

	UP = 0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	
	#100;
	
	$stop; 
end


M_CLOCK_DIVIDER #(
.div_value(48))

DIV_1KHZ (
.clk(clk),
.rst(rst),
.divided_clk(CE_1MHZ)
);

 
LR2_SEQ_GEN_FSM FSM_wrapper(
.clk(clk),
.UP(UP),
.CE(STEP),
.rst(rst),
.SEQ(SEQ)
 );
LR4_MATRIX_DISP_V10 matrix_wrapper(
.clk(clk),
.rst(rst),
.CE(CE_1MHZ),
.SEQ(SEQ),
.column(column),
.row(row)
 );



endmodule
module test;


reg clk = 0;
reg btn;
reg switch;
reg UP;
reg STEP;
reg SYS_NRST;

wire [7:0]row;
wire [7:0]column;

wire rst;
wire CE_1MHZ;
wire [3:0]SEQ;

parameter PERIOD_CLK = 20.8;
parameter DUTY_CYCLE_CLK = 0.4;

initial
	forever
		begin
			clk = 1'b0;
			#(PERIOD_CLK-(PERIOD_CLK*DUTY_CYCLE_CLK)) clk = 1'b1;
			#(PERIOD_CLK*DUTY_CYCLE_CLK);
		end


initial
	begin
		SYS_NRST = 0;
		#100;
		SYS_NRST = 1;
	end

reg [1:0] RST_S;

always @ (posedge clk, negedge SYS_NRST)
	if(!SYS_NRST) 
		RST_S <= 2'b11;
	else 
		RST_S <= {RST_S[0], 1'b0};

assign rst = RST_S[1];

initial begin

	STEP = 0;
	UP = 1;

	#100;


	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;

	UP = 0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	@(posedge column[7]);
	@(posedge clk);
	#(PERIOD_CLK*0.2);
	STEP = 1'b1;
	#(PERIOD_CLK);
	STEP = 1'b0;
	
	#100;
	
	$stop; 
end


M_CLOCK_DIVIDER #(
.div_value(48))

DIV_1KHZ (
.clk(clk),
.rst(rst),
.divided_clk(CE_1MHZ)
);

 
LR2_SEQ_GEN_FSM FSM_wrapper(
.clk(clk),
.UP(UP),
.CE(STEP),
.rst(rst),
.SEQ(SEQ)
 );
LR4_MATRIX_DISP_V10 matrix_wrapper(
.clk(clk),
.rst(rst),
.CE(CE_1MHZ),
.SEQ(SEQ),
.column(column),
.row(row)
 );



endmodule