data/full_repos/permissive/423547971/FPGA Projects/Nexys A7 3-Axis Accelerometer SPI/top.v
1: b'%Error: Cannot find file containing module: Projects/Nexys\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/Nexys\n             data/full_repos/permissive/423547971/FPGA/Projects/Nexys.v\n             data/full_repos/permissive/423547971/FPGA/Projects/Nexys.sv\n             Projects/Nexys\n             Projects/Nexys.v\n             Projects/Nexys.sv\n             obj_dir/Projects/Nexys\n             obj_dir/Projects/Nexys.v\n             obj_dir/Projects/Nexys.sv\n%Error: Cannot find file containing module: A7\n%Error: Cannot find file containing module: 3-Axis\n%Error: Cannot find file containing module: Accelerometer\n%Error: Cannot find file containing module: SPI,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: SPI/top.v\n%Error: Exiting due to 7 error(s)\n'
module top(
    input CLK100MHZ,
    input ACL_MISO,
    output ACL_MOSI,
    output ACL_SCLK,
    output ACL_CSN,
    output [14:0] LED,
    output [6:0] SEG,
    output DP,
    output [7:0] AN
    );
    
    wire w_4MHz;
    wire [14:0] acl_data;
        
    iclk_gen clock_generation(
        .CLK100MHZ(CLK100MHZ),
        .clk_4MHz(w_4MHz)
    );
    
    spi_master master(
        .iclk(w_4MHz),
        .miso(ACL_MISO),
        .sclk(ACL_SCLK),
        .mosi(ACL_MOSI),
        .cs(ACL_CSN),
        .acl_data(acl_data)
    );
    
    seg7_control display_control(
        .CLK100MHZ(CLK100MHZ),
        .acl_data(acl_data),
        .seg(SEG),
        .dp(DP),
        .an(AN)
    );

    assign LED[14:10] = acl_data[14:10];
    assign LED[9:5]   = acl_data[9:5];
    assign LED[4:0]   = acl_data[4:0];
    
endmodule
module top(
    input CLK100MHZ,
    input ACL_MISO,
    output ACL_MOSI,
    output ACL_SCLK,
    output ACL_CSN,
    output [14:0] LED,
    output [6:0] SEG,
    output DP,
    output [7:0] AN
    );

    
    wire w_4MHz;
    wire [14:0] acl_data;
        
    iclk_gen clock_generation(
        .CLK100MHZ(CLK100MHZ),
        .clk_4MHz(w_4MHz)
    );
    
    spi_master master(
        .iclk(w_4MHz),
        .miso(ACL_MISO),
        .sclk(ACL_SCLK),
        .mosi(ACL_MOSI),
        .cs(ACL_CSN),
        .acl_data(acl_data)
    );
    
    seg7_control display_control(
        .CLK100MHZ(CLK100MHZ),
        .acl_data(acl_data),
        .seg(SEG),
        .dp(DP),
        .an(AN)
    );

    assign LED[14:10] = acl_data[14:10];
    assign LED[9:5]   = acl_data[9:5];
    assign LED[4:0]   = acl_data[4:0];
    
endmodule