data/full_repos/permissive/427221126/src/ShiftRegister.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/427221126/src/ShiftRegister.v:165: Multiple top level modules\n                                                                               : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                               : ... Top module \'ShiftRegSIPOnB\'\nmodule ShiftRegSIPOnB\n       ^~~~~~~~~~~~~~\n                                                                               : ... Top module \'ShiftRegPISO\'\nmodule ShiftRegPISO\n       ^~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module ShiftRegPISO
  #(
    parameter INWIDTH = 16,
              DEPTH = 4
  )
  (
    input clk,
    input reset, 
    input en,
    input  [INWIDTH*DEPTH-1:0] pin,
    input                      pin_valid,
    input  [INWIDTH-1:0]       casin,
    input                      shift,
    output [INWIDTH-1:0]       dout
  );
  reg [INWIDTH-1:0] shreg [0:DEPTH-1];
  genvar ii;

  always @(posedge clk) begin
    if (reset == 1'b1)
      shreg[DEPTH-1] <= 0;
    else if (en) 
      if (pin_valid) 
        shreg[DEPTH-1] <= pin[DEPTH*INWIDTH-1:(DEPTH-1)*INWIDTH];
      else if (shift)
        shreg[DEPTH-1] <= casin;
  end
  
  generate
    for (ii = 0; ii < DEPTH-1; ii = ii + 1) begin : elem
      always @(posedge clk) begin
        if (reset == 1'b1)
          shreg[ii] <= 0;
        else if (en) begin
          if (pin_valid)
            shreg[ii] <= pin[(ii+1)*INWIDTH-1:ii*INWIDTH];
          else if (shift) begin
            shreg[ii] <= shreg[ii+1];
          end
        end
      end
    end
  endgenerate

  assign dout = shreg[0];
endmodule
module ShiftRegPISO
  #(
    parameter INWIDTH = 16,
              DEPTH = 4
  )
  (
    input clk,
    input reset, 
    input en,
    input  [INWIDTH*DEPTH-1:0] pin,
    input                      pin_valid,
    input  [INWIDTH-1:0]       casin,
    input                      shift,
    output [INWIDTH-1:0]       dout
  );

  reg [INWIDTH-1:0] shreg [0:DEPTH-1];
  genvar ii;

  always @(posedge clk) begin
    if (reset == 1'b1)
      shreg[DEPTH-1] <= 0;
    else if (en) 
      if (pin_valid) 
        shreg[DEPTH-1] <= pin[DEPTH*INWIDTH-1:(DEPTH-1)*INWIDTH];
      else if (shift)
        shreg[DEPTH-1] <= casin;
  end
  
  generate
    for (ii = 0; ii < DEPTH-1; ii = ii + 1) begin : elem
      always @(posedge clk) begin
        if (reset == 1'b1)
          shreg[ii] <= 0;
        else if (en) begin
          if (pin_valid)
            shreg[ii] <= pin[(ii+1)*INWIDTH-1:ii*INWIDTH];
          else if (shift) begin
            shreg[ii] <= shreg[ii+1];
          end
        end
      end
    end
  endgenerate

  assign dout = shreg[0];
endmodule