data/full_repos/permissive/484799296/verilog/ram/ram.v
data/verilator_xmls/f01d718b-cff7-4cad-9314-c87ee906f851.xml
module ram
(
    input enable,
    input write_enable,
    input [11:0] address,
    inout [7:0] data
);

    reg [7:0] mem [0:4095];
    reg [7:0] out_data;




    assign data = (enable & ~write_enable)?out_data:8'bzzzz_zzzz;

    always @ (enable, write_enable, address, data)
    begin


        if (enable & write_enable) 
        begin
            mem[address] = data;
        end


        if (enable & ~write_enable)
        begin
            out_data = mem[address];
        end

    end


    initial begin

        mem[12'b000000000000] = 8'b1010_1010;
    end

endmodule
module ram
(
    input enable,
    input write_enable,
    input [11:0] address,
    inout [7:0] data
);


    reg [7:0] mem [0:4095];
    reg [7:0] out_data;




    assign data = (enable & ~write_enable)?out_data:8'bzzzz_zzzz;

    always @ (enable, write_enable, address, data)
    begin


        if (enable & write_enable) 
        begin
            mem[address] = data;
        end


        if (enable & ~write_enable)
        begin
            out_data = mem[address];
        end

    end


    initial begin

        mem[12'b000000000000] = 8'b1010_1010;
    end

endmodule