data/full_repos/permissive/469804105/RTL/Project_files/Shift_left_reg_r.v
data/verilator_xmls/06660fb0-191a-4aa6-bea6-cf66ea3b3f87.xml
module Shift_left_reg_r(i_clk , clr_R , in_r , en_r , ld_r  , sl_r , out_r  );
input i_clk ;
input clr_R ;
input [`WIDTH_R-1:0] in_r ;
input ld_r ;
input en_r  ;
input sl_r ;
output reg [`WIDTH_R-1:0] out_r  ;  



always @ (posedge i_clk)
 begin 
   if(clr_R==1'b1)
    out_r <= 4'b0000;
      else if(en_r==1'b1)
      begin
            out_r <= in_r ;
           end
                  else if (ld_r==1'b1)
        begin
                   out_r <= {out_r[2:0] , sl_r} ;
                end
                    else
          begin
                  out_r <= out_r ;
                  end      
               end         
endmodule
module Shift_left_reg_r(i_clk , clr_R , in_r , en_r , ld_r  , sl_r , out_r  );

input i_clk ;
input clr_R ;
input [`WIDTH_R-1:0] in_r ;
input ld_r ;
input en_r  ;
input sl_r ;
output reg [`WIDTH_R-1:0] out_r  ;  



always @ (posedge i_clk)
 begin 
   if(clr_R==1'b1)
    out_r <= 4'b0000;
      else if(en_r==1'b1)
      begin
            out_r <= in_r ;
           end
                  else if (ld_r==1'b1)
        begin
                   out_r <= {out_r[2:0] , sl_r} ;
                end
                    else
          begin
                  out_r <= out_r ;
                  end      
               end         
endmodule