data/full_repos/permissive/493441306/Verilog Language/vectors/07_vector4.v
1: b'%Error: Cannot find file containing module: Language/vectors,data/full_repos/permissive/493441306\n        ... Looked in:\n             data/full_repos/permissive/493441306/Verilog/Language/vectors,data/full_repos/permissive/493441306\n             data/full_repos/permissive/493441306/Verilog/Language/vectors,data/full_repos/permissive/493441306.v\n             data/full_repos/permissive/493441306/Verilog/Language/vectors,data/full_repos/permissive/493441306.sv\n             Language/vectors,data/full_repos/permissive/493441306\n             Language/vectors,data/full_repos/permissive/493441306.v\n             Language/vectors,data/full_repos/permissive/493441306.sv\n             obj_dir/Language/vectors,data/full_repos/permissive/493441306\n             obj_dir/Language/vectors,data/full_repos/permissive/493441306.v\n             obj_dir/Language/vectors,data/full_repos/permissive/493441306.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/493441306/Verilog\n%Error: Cannot find file containing module: Language/vectors/07_vector4.v\n%Error: Exiting due to 3 error(s)\n'
module top_module (
    input [7:0] in,
    output [31:0] out );

    assign out = { {24{in[7]}}, in };

endmodule
module top_module (
    input [7:0] in,
    output [31:0] out );


    assign out = { {24{in[7]}}, in };

endmodule