data/full_repos/permissive/42434302/ivltests/pr820.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr820.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #3001;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/42434302/ivltests/pr820.v:29: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    $display($time,,"waddr wdata %d %d    raddr rdata %d %d",waddr,wdata,raddr,rdata);\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr820.v:67: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr820.v:69: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr820.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr820.v:74: Unsupported: Ignoring delay on this delayed statement.\n    forever #5 clk = ~clk;\n            ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module clk_reset_gen(clk, reset);
  output clk;
  output reset;
  reg clk;
  reg reset;
  initial begin
    reset = 1;
    #5;
    clk = 0;
    #5;
    clk = 1;
    #5;
    reset = 0;
    clk = 0;
    forever #5 clk = ~clk;
  end
endmodule
module clk_reset_gen(clk, reset);

  output clk;
  output reset;
  reg clk;
  reg reset;
  initial begin
    reset = 1;
    #5;
    clk = 0;
    #5;
    clk = 1;
    #5;
    reset = 0;
    clk = 0;
    forever #5 clk = ~clk;
  end
endmodule