data/full_repos/permissive/499054870/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/499054870/verilog/rtl/user_proj_example.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499054870/verilog/rtl/user_proj_example.v:67: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499054870/verilog/rtl/user_proj_example.v:68: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499054870/verilog/rtl/user_proj_example.v:115: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_oeb = {(`MPRJ_IO_PADS-1){1'b1}};\n                      ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module mydff(
    input clk,
    input D,
    output Q
    );

reg Q_q;
assign Q = Q_q;
always @(posedge clk)                                                    
begin                                                                                               
    Q_q <= D;                                                                      
end
endmodule
module mydff(
    input clk,
    input D,
    output Q
    );


reg Q_q;
assign Q = Q_q;
always @(posedge clk)                                                    
begin                                                                                               
    Q_q <= D;                                                                      
end
endmodule