data/full_repos/permissive/493019833/test/testcase/firrtl/OpShift/reference/OpShift.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/OpShift/reference/OpShift.v:155: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                         : ... In instance OpShift.u_pad_10\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/OpShift/reference/OpShift.v:148: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                         : ... In instance OpShift.s_pad_9\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/OpShift/reference/OpShift.v:105: [7:8] Range extract has backward bit ordering, perhaps you wanted [8:7]\n                                                                                                 : ... In instance OpShift.s_shr_4\n    assign y = n < width ? in[width-1:n] : in[width-1:width-1];\n                             ^\n%Warning-SELRANGE: data/full_repos/permissive/493019833/test/testcase/firrtl/OpShift/reference/OpShift.v:105: Selection index out of range: 9:8 outside 7:0\n                                                                                                            : ... In instance OpShift.s_shr_4\n    assign y = n < width ? in[width-1:n] : in[width-1:width-1];\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/OpShift/reference/OpShift.v:105: Operator COND expects 2 bits on the Conditional False, but Conditional False\'s SEL generates 1 bits.\n                                                                                                         : ... In instance OpShift.s_shr_4\n    assign y = n < width ? in[width-1:n] : in[width-1:width-1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/OpShift/reference/OpShift.v:105: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 2 bits.\n                                                                                                         : ... In instance OpShift.s_shr_4\n    assign y = n < width ? in[width-1:n] : in[width-1:width-1];\n             ^\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/OpShift/reference/OpShift.v:89: [7:8] Range extract has backward bit ordering, perhaps you wanted [8:7]\n                                                                                                : ... In instance OpShift.u_shr_2\n    assign y = n < width ? in[width-1:n] : 1\'b0;\n                             ^\n%Warning-SELRANGE: data/full_repos/permissive/493019833/test/testcase/firrtl/OpShift/reference/OpShift.v:89: Selection index out of range: 9:8 outside 7:0\n                                                                                                           : ... In instance OpShift.u_shr_2\n    assign y = n < width ? in[width-1:n] : 1\'b0;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/OpShift/reference/OpShift.v:89: Operator COND expects 2 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                        : ... In instance OpShift.u_shr_2\n    assign y = n < width ? in[width-1:n] : 1\'b0;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/OpShift/reference/OpShift.v:89: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 2 bits.\n                                                                                                        : ... In instance OpShift.u_shr_2\n    assign y = n < width ? in[width-1:n] : 1\'b0;\n             ^\n%Error: Exiting due to 2 error(s), 8 warning(s)\n'
module OpShift(
    input clock,
    input reset,
    input [7:0] io_u0,
    input [2:0] io_u1,
    input [7:0] io_s0,
    output [9:0] io_uout_shl,
    output [5:0] io_uout_shr,
    output [9:0] io_sout_shl,
    output [5:0] io_sout_shr,
    output [14:0] io_uout_dshl,
    output [7:0] io_uout_dshr,
    output [14:0] io_sout_dshl,
    output [7:0] io_sout_dshr
);
    wire [9:0] _T_27;
    SHL_UNSIGNED #(.width(8), .n(2)) u_shl_1 (
        .y(_T_27),
        .in(io_u0)
    );
    wire _T_28;
    SHR_UNSIGNED #(.width(8), .n(8)) u_shr_2 (
        .y(_T_28),
        .in(io_u0)
    );
    wire [9:0] _T_29;
    SHL_SIGNED #(.width(8), .n(2)) s_shl_3 (
        .y(_T_29),
        .in(io_s0)
    );
    wire _T_30;
    SHR_SIGNED #(.width(8), .n(8)) s_shr_4 (
        .y(_T_30),
        .in(io_s0)
    );
    wire [14:0] _T_31;
    DSHL_UNSIGNED #(.width_in(8), .width_n(3)) u_dshl_5 (
        .y(_T_31),
        .in(io_u0),
        .n(io_u1)
    );
    wire [7:0] _T_32;
    DSHR_UNSIGNED #(.width_in(8), .width_n(3)) u_dshr_6 (
        .y(_T_32),
        .in(io_u0),
        .n(io_u1)
    );
    wire [14:0] _T_33;
    DSHL_SIGNED #(.width_in(8), .width_n(3)) s_dshl_7 (
        .y(_T_33),
        .in(io_s0),
        .n(io_u1)
    );
    wire [7:0] _T_34;
    DSHR_SIGNED #(.width_in(8), .width_n(3)) s_dshr_8 (
        .y(_T_34),
        .in(io_s0),
        .n(io_u1)
    );
    assign io_sout_dshl = _T_33;
    assign io_sout_dshr = _T_34;
    assign io_sout_shl = _T_29;
    PAD_SIGNED #(.width(1), .n(6)) s_pad_9 (
        .y(io_sout_shr),
        .in(_T_30)
    );
    assign io_uout_dshl = _T_31;
    assign io_uout_dshr = _T_32;
    assign io_uout_shl = _T_27;
    PAD_UNSIGNED #(.width(1), .n(6)) u_pad_10 (
        .y(io_uout_shr),
        .in(_T_28)
    );
endmodule
module OpShift(
    input clock,
    input reset,
    input [7:0] io_u0,
    input [2:0] io_u1,
    input [7:0] io_s0,
    output [9:0] io_uout_shl,
    output [5:0] io_uout_shr,
    output [9:0] io_sout_shl,
    output [5:0] io_sout_shr,
    output [14:0] io_uout_dshl,
    output [7:0] io_uout_dshr,
    output [14:0] io_sout_dshl,
    output [7:0] io_sout_dshr
);

    wire [9:0] _T_27;
    SHL_UNSIGNED #(.width(8), .n(2)) u_shl_1 (
        .y(_T_27),
        .in(io_u0)
    );
    wire _T_28;
    SHR_UNSIGNED #(.width(8), .n(8)) u_shr_2 (
        .y(_T_28),
        .in(io_u0)
    );
    wire [9:0] _T_29;
    SHL_SIGNED #(.width(8), .n(2)) s_shl_3 (
        .y(_T_29),
        .in(io_s0)
    );
    wire _T_30;
    SHR_SIGNED #(.width(8), .n(8)) s_shr_4 (
        .y(_T_30),
        .in(io_s0)
    );
    wire [14:0] _T_31;
    DSHL_UNSIGNED #(.width_in(8), .width_n(3)) u_dshl_5 (
        .y(_T_31),
        .in(io_u0),
        .n(io_u1)
    );
    wire [7:0] _T_32;
    DSHR_UNSIGNED #(.width_in(8), .width_n(3)) u_dshr_6 (
        .y(_T_32),
        .in(io_u0),
        .n(io_u1)
    );
    wire [14:0] _T_33;
    DSHL_SIGNED #(.width_in(8), .width_n(3)) s_dshl_7 (
        .y(_T_33),
        .in(io_s0),
        .n(io_u1)
    );
    wire [7:0] _T_34;
    DSHR_SIGNED #(.width_in(8), .width_n(3)) s_dshr_8 (
        .y(_T_34),
        .in(io_s0),
        .n(io_u1)
    );
    assign io_sout_dshl = _T_33;
    assign io_sout_dshr = _T_34;
    assign io_sout_shl = _T_29;
    PAD_SIGNED #(.width(1), .n(6)) s_pad_9 (
        .y(io_sout_shr),
        .in(_T_30)
    );
    assign io_uout_dshl = _T_31;
    assign io_uout_dshr = _T_32;
    assign io_uout_shl = _T_27;
    PAD_UNSIGNED #(.width(1), .n(6)) u_pad_10 (
        .y(io_uout_shr),
        .in(_T_28)
    );
endmodule