data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:616: Multiple top level modules\n                                                                                      : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                      : ... Top module \'loadBalancer\'\nmodule loadBalancer#(\n       ^~~~~~~~~~~~\n                                                                                      : ... Top module \'wrArbiter\'\nmodule wrArbiter#(\n       ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:659: Bit extraction of var[0:0] requires 1 bit index, not 8 bits.\n                                                                                   : ... In instance wrArbiter\n                    frag_fifo_rd_en[t_pipe_select] <= 1\'b1;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:657: Bit extraction of var[0:0] requires 1 bit index, not 8 bits.\n                                                                                   : ... In instance wrArbiter\n                if(frag_fifo_threshold[t_pipe_select]) begin\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:656: Bit extraction of var[0:0] requires 1 bit index, not 8 bits.\n                                                                                   : ... In instance wrArbiter\n            if(frag_fifo_rd_en[t_pipe_select] == \'b0) begin \n                              ^\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:670: Bit extraction of var[0:0] requires 1 bit index, not 8 bits.\n                                                                                   : ... In instance wrArbiter\n            frag_fifo_rd_en[t_pipe_select] <= \'b0;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:675: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'fragOffs\' generates 4 bits.\n                                                                                   : ... In instance wrArbiter\n                frag_wr_addr <= fragOffs + (frag_base_addr * (vertexSize + \'b1)) + f_array_ptr;\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:675: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'vertexSize\' generates 4 bits.\n                                                                                   : ... In instance wrArbiter\n                frag_wr_addr <= fragOffs + (frag_base_addr * (vertexSize + \'b1)) + f_array_ptr;\n                                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:684: Bit extraction of var[0:0] requires 1 bit index, not 8 bits.\n                                                                                   : ... In instance wrArbiter\n                    frag_fifo_rd_en[t_pipe_select] <= 1\'b0;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:673: Bit extraction of var[0:0] requires 1 bit index, not 8 bits.\n                                                                                   : ... In instance wrArbiter\n            if(frag_fifo_rd_en[t_pipe_select] == 1\'b1) begin \n                              ^\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:703: Bit extraction of var[0:0] requires 1 bit index, not 8 bits.\n                                                                                   : ... In instance wrArbiter\n            if((fragOffs == vertexSize) || (~frag_fifo_rd_en[t_pipe_select] && ~frag_fifo_threshold[t_pipe_select]) || ((t_pipe_select == (NUM_T_PIPES-1)) && (frag_fifo_empty[t_pipe_select]))) begin  \n                                                            ^\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:703: Bit extraction of var[0:0] requires 1 bit index, not 8 bits.\n                                                                                   : ... In instance wrArbiter\n            if((fragOffs == vertexSize) || (~frag_fifo_rd_en[t_pipe_select] && ~frag_fifo_threshold[t_pipe_select]) || ((t_pipe_select == (NUM_T_PIPES-1)) && (frag_fifo_empty[t_pipe_select]))) begin  \n                                                                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:703: Bit extraction of var[0:0] requires 1 bit index, not 8 bits.\n                                                                                   : ... In instance wrArbiter\n            if((fragOffs == vertexSize) || (~frag_fifo_rd_en[t_pipe_select] && ~frag_fifo_threshold[t_pipe_select]) || ((t_pipe_select == (NUM_T_PIPES-1)) && (frag_fifo_empty[t_pipe_select]))) begin  \n                                                                                                                                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:123: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance loadBalancer\n                        v_mem_wr_en <= 1\'b0;\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:124: Bit extraction of var[0:0] requires 1 bit index, not 8 bits.\n                                                                                   : ... In instance loadBalancer\n                        if(tri_fifo_upper_threshold[t_pipe_select]) begin\n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:151: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'vertexSize\' generates 4 bits.\n                                                                                   : ... In instance loadBalancer\n                            main_mem_rd_addr <= v_array_ptr + ((vertexSize + 1) * main_mem_rd_data) + vertex_attr_offset;\n                                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:151: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'vertex_attr_offset\' generates 4 bits.\n                                                                                   : ... In instance loadBalancer\n                            main_mem_rd_addr <= v_array_ptr + ((vertexSize + 1) * main_mem_rd_data) + vertex_attr_offset;\n                                                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:154: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'vertexSize\' generates 4 bits.\n                                                                                   : ... In instance loadBalancer\n                            main_mem_rd_addr <= v_array_ptr + ((vertexSize + 1) * vertex_base_addr) + vertex_attr_offset;\n                                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:154: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'vertex_attr_offset\' generates 4 bits.\n                                                                                   : ... In instance loadBalancer\n                            main_mem_rd_addr <= v_array_ptr + ((vertexSize + 1) * vertex_base_addr) + vertex_attr_offset;\n                                                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:196: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance loadBalancer\n                                v_mem_wr_en <= 1\'b0;\n                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:213: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance loadBalancer\n                        v_mem_wr_en <= 1\'b0;\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:214: Bit extraction of var[0:0] requires 1 bit index, not 8 bits.\n                                                                                   : ... In instance loadBalancer\n                        if(tri_fifo_upper_threshold[t_pipe_select]) begin\n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:241: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'vertexSize\' generates 4 bits.\n                                                                                   : ... In instance loadBalancer\n                            main_mem_rd_addr <= v_array_ptr + ((vertexSize + 1) * main_mem_rd_data) + vertex_attr_offset;\n                                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:241: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'vertex_attr_offset\' generates 4 bits.\n                                                                                   : ... In instance loadBalancer\n                            main_mem_rd_addr <= v_array_ptr + ((vertexSize + 1) * main_mem_rd_data) + vertex_attr_offset;\n                                                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:246: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'vertexSize\' generates 4 bits.\n                                                                                   : ... In instance loadBalancer\n                            main_mem_rd_addr <= v_array_ptr + ((vertexSize + 1) * vertex_base_addr) + vertex_attr_offset;\n                                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:246: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'vertex_attr_offset\' generates 4 bits.\n                                                                                   : ... In instance loadBalancer\n                            main_mem_rd_addr <= v_array_ptr + ((vertexSize + 1) * vertex_base_addr) + vertex_attr_offset;\n                                                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:287: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance loadBalancer\n                                v_mem_wr_en <= 1\'b0;\n                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:308: Bit extraction of var[0:0] requires 1 bit index, not 8 bits.\n                                                                                   : ... In instance loadBalancer\n                        tri_fifo_wr_en[t_pipe_select] <= 1\'b1;\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:368: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance loadBalancer\n                        v_mem_wr_en <= 1\'b0;\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:370: Bit extraction of var[0:0] requires 1 bit index, not 8 bits.\n                                                                                   : ... In instance loadBalancer\n                        if(tri_fifo_upper_threshold[t_pipe_select]) begin\n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:398: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'vertexSize\' generates 4 bits.\n                                                                                   : ... In instance loadBalancer\n                            main_mem_rd_addr <= v_array_ptr + ((vertexSize + 1) * main_mem_rd_data) + vertex_attr_offset;\n                                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:398: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'vertex_attr_offset\' generates 4 bits.\n                                                                                   : ... In instance loadBalancer\n                            main_mem_rd_addr <= v_array_ptr + ((vertexSize + 1) * main_mem_rd_data) + vertex_attr_offset;\n                                                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:401: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'vertexSize\' generates 4 bits.\n                                                                                   : ... In instance loadBalancer\n                            main_mem_rd_addr <= v_array_ptr + ((vertexSize + 1) * vertex_base_addr) + vertex_attr_offset;\n                                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:401: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'vertex_attr_offset\' generates 4 bits.\n                                                                                   : ... In instance loadBalancer\n                            main_mem_rd_addr <= v_array_ptr + ((vertexSize + 1) * vertex_base_addr) + vertex_attr_offset;\n                                                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:443: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                   : ... In instance loadBalancer\n                                v_mem_wr_en <= 1\'b0;\n                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:466: Bit extraction of var[0:0] requires 1 bit index, not 8 bits.\n                                                                                   : ... In instance loadBalancer\n                        tri_fifo_wr_en[t_pipe_select] <= 1\'b1;\n                                      ^\n%Warning-UNSIGNED: data/full_repos/permissive/499944578/rtl/src/top/loadBalancer.v:704: Comparison is constant due to unsigned arithmetic\n                                                                                      : ... In instance wrArbiter\n                if(t_pipe_select < (NUM_T_PIPES-1)) begin\n                                 ^\n%Error: Exiting due to 36 warning(s)\n'
module wrArbiter#(
    parameter NUM_T_PIPES = 1,
    parameter FIFO_MAX_FRAGMENTS = 4,
    parameter DATA_WIDTH = 32,
    parameter MAIN_MEM_ADDR_WIDTH = 32,
    parameter LOCAL_VERTEX_MEM_ADDR_WIDTH = 4   
)(
    input wire clk,
    input wire resetn,
    input wire en,

    input wire [NUM_T_PIPES-1:0] t_pipe_done,

    input wire [NUM_T_PIPES-1:0][DATA_WIDTH-1:0] frag_fifo_rd_data,
    output reg [NUM_T_PIPES-1:0]                 frag_fifo_rd_en, 

    input wire [NUM_T_PIPES-1:0] frag_fifo_full, 
    input wire [NUM_T_PIPES-1:0] frag_fifo_empty, 
    input wire [NUM_T_PIPES-1:0] frag_fifo_threshold, 
    input wire [NUM_T_PIPES-1:0] frag_fifo_overflow, 
    input wire [NUM_T_PIPES-1:0] frag_fifo_underflow,

    output reg [DATA_WIDTH-1:0] frag_wr_data,
    output reg [MAIN_MEM_ADDR_WIDTH-1:0] frag_wr_addr,
    output reg frag_wr_en,

    input wire [MAIN_MEM_ADDR_WIDTH-1:0] f_array_ptr,
    input wire [LOCAL_VERTEX_MEM_ADDR_WIDTH-1:0] vertexSize
);
    reg we;

    reg [NUM_T_PIPES-1:0][7:0] done_count;
    reg [LOCAL_VERTEX_MEM_ADDR_WIDTH-1:0] fragOffs;
    reg [MAIN_MEM_ADDR_WIDTH-1:0] frag_base_addr;
   
    always @(posedge clk or negedge resetn) begin
        if(~resetn) begin
            done_count <= 'b0;
            frag_fifo_rd_en <= 'b0;
        end else if(en) begin
            if(frag_fifo_rd_en[t_pipe_select] == 'b0) begin 
                if(frag_fifo_threshold[t_pipe_select]) begin
                    
                    frag_fifo_rd_en[t_pipe_select] <= 1'b1;
                    we <= 1'b1;
                end
            end
            frag_wr_en <= we;
        end
    end 
    
    always @(posedge clk or negedge resetn) begin
        if(~resetn) begin
            fragOffs <= 'b0;
            frag_fifo_rd_en[t_pipe_select] <= 'b0;
            frag_base_addr <= 'b0;
        end else if(en) begin
            if(frag_fifo_rd_en[t_pipe_select] == 1'b1) begin 
                frag_wr_data <= frag_fifo_rd_data[t_pipe_select];
                frag_wr_addr <= fragOffs + (frag_base_addr * (vertexSize + 'b1)) + f_array_ptr;

                if(fragOffs < vertexSize) begin
                    fragOffs <= fragOffs + 'b1;
                    
                end
                if(fragOffs == vertexSize) begin
                    fragOffs <= 'b0;
                    frag_base_addr <= frag_base_addr + 'b1;
                    frag_fifo_rd_en[t_pipe_select] <= 1'b0;
                    we <= 1'b0;
                    
                end
            end
        end
    end 
 




    

    reg [7:0] t_pipe_select;
    always @(posedge clk or negedge resetn) begin
        if(~resetn) begin
            t_pipe_select <= 'b0;
        end else begin
            if((fragOffs == vertexSize) || (~frag_fifo_rd_en[t_pipe_select] && ~frag_fifo_threshold[t_pipe_select]) || ((t_pipe_select == (NUM_T_PIPES-1)) && (frag_fifo_empty[t_pipe_select]))) begin
                if(t_pipe_select < (NUM_T_PIPES-1)) begin
                    t_pipe_select <= t_pipe_select + 'b1; 
                end
                if(t_pipe_select == (NUM_T_PIPES-1)) begin
                    t_pipe_select <= 'b0;
                end
            end 
        end
    end
    











endmodule
module wrArbiter#(
    parameter NUM_T_PIPES = 1,
    parameter FIFO_MAX_FRAGMENTS = 4,
    parameter DATA_WIDTH = 32,
    parameter MAIN_MEM_ADDR_WIDTH = 32,
    parameter LOCAL_VERTEX_MEM_ADDR_WIDTH = 4   
)(
    input wire clk,
    input wire resetn,
    input wire en,

    input wire [NUM_T_PIPES-1:0] t_pipe_done,

    input wire [NUM_T_PIPES-1:0][DATA_WIDTH-1:0] frag_fifo_rd_data,
    output reg [NUM_T_PIPES-1:0]                 frag_fifo_rd_en, 

    input wire [NUM_T_PIPES-1:0] frag_fifo_full, 
    input wire [NUM_T_PIPES-1:0] frag_fifo_empty, 
    input wire [NUM_T_PIPES-1:0] frag_fifo_threshold, 
    input wire [NUM_T_PIPES-1:0] frag_fifo_overflow, 
    input wire [NUM_T_PIPES-1:0] frag_fifo_underflow,

    output reg [DATA_WIDTH-1:0] frag_wr_data,
    output reg [MAIN_MEM_ADDR_WIDTH-1:0] frag_wr_addr,
    output reg frag_wr_en,

    input wire [MAIN_MEM_ADDR_WIDTH-1:0] f_array_ptr,
    input wire [LOCAL_VERTEX_MEM_ADDR_WIDTH-1:0] vertexSize
);

    reg we;

    reg [NUM_T_PIPES-1:0][7:0] done_count;
    reg [LOCAL_VERTEX_MEM_ADDR_WIDTH-1:0] fragOffs;
    reg [MAIN_MEM_ADDR_WIDTH-1:0] frag_base_addr;
   
    always @(posedge clk or negedge resetn) begin
        if(~resetn) begin
            done_count <= 'b0;
            frag_fifo_rd_en <= 'b0;
        end else if(en) begin
            if(frag_fifo_rd_en[t_pipe_select] == 'b0) begin 
                if(frag_fifo_threshold[t_pipe_select]) begin
                    
                    frag_fifo_rd_en[t_pipe_select] <= 1'b1;
                    we <= 1'b1;
                end
            end
            frag_wr_en <= we;
        end
    end 
    
    always @(posedge clk or negedge resetn) begin
        if(~resetn) begin
            fragOffs <= 'b0;
            frag_fifo_rd_en[t_pipe_select] <= 'b0;
            frag_base_addr <= 'b0;
        end else if(en) begin
            if(frag_fifo_rd_en[t_pipe_select] == 1'b1) begin 
                frag_wr_data <= frag_fifo_rd_data[t_pipe_select];
                frag_wr_addr <= fragOffs + (frag_base_addr * (vertexSize + 'b1)) + f_array_ptr;

                if(fragOffs < vertexSize) begin
                    fragOffs <= fragOffs + 'b1;
                    
                end
                if(fragOffs == vertexSize) begin
                    fragOffs <= 'b0;
                    frag_base_addr <= frag_base_addr + 'b1;
                    frag_fifo_rd_en[t_pipe_select] <= 1'b0;
                    we <= 1'b0;
                    
                end
            end
        end
    end 
 




    

    reg [7:0] t_pipe_select;
    always @(posedge clk or negedge resetn) begin
        if(~resetn) begin
            t_pipe_select <= 'b0;
        end else begin
            if((fragOffs == vertexSize) || (~frag_fifo_rd_en[t_pipe_select] && ~frag_fifo_threshold[t_pipe_select]) || ((t_pipe_select == (NUM_T_PIPES-1)) && (frag_fifo_empty[t_pipe_select]))) begin
                if(t_pipe_select < (NUM_T_PIPES-1)) begin
                    t_pipe_select <= t_pipe_select + 'b1; 
                end
                if(t_pipe_select == (NUM_T_PIPES-1)) begin
                    t_pipe_select <= 'b0;
                end
            end 
        end
    end
    











endmodule