data/full_repos/permissive/460664642/bcd_tb.v
1: b'%Error: data/full_repos/permissive/460664642/bcd_tb.v:1: Cannot find include file: bcd.v\n`include "bcd.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/460664642,data/full_repos/permissive/460664642/bcd.v\n             data/full_repos/permissive/460664642,data/full_repos/permissive/460664642/bcd.v.v\n             data/full_repos/permissive/460664642,data/full_repos/permissive/460664642/bcd.v.sv\n             bcd.v\n             bcd.v.v\n             bcd.v.sv\n             obj_dir/bcd.v\n             obj_dir/bcd.v.v\n             obj_dir/bcd.v.sv\n%Error: data/full_repos/permissive/460664642/bcd_tb.v:10: Unsupported or unknown PLI call: $monitor\n   $monitor("Binary=%b,BCD=%b",Input,bcd);\n   ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/460664642/bcd_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n     #1 Input = i; \n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module bcd_tb();

reg [7:0] Input;
wire [11:0] bcd;

reg [7:0] i;

initial begin
   $monitor("Binary=%b,BCD=%b",Input,bcd);
   Input = 0;
   for(i = 0; i < 256; i = i + 1)
   begin
     #1 Input = i; 
   end
end

binary_to_BCD BIN2BCD (
Input,
bcd[3:0],
bcd[7:4],
bcd[11:8]
 );
endmodule
module bcd_tb();


reg [7:0] Input;
wire [11:0] bcd;

reg [7:0] i;

initial begin
   $monitor("Binary=%b,BCD=%b",Input,bcd);
   Input = 0;
   for(i = 0; i < 256; i = i + 1)
   begin
     #1 Input = i; 
   end
end

binary_to_BCD BIN2BCD (
Input,
bcd[3:0],
bcd[7:4],
bcd[11:8]
 );
endmodule