data/full_repos/permissive/521337848/Hardware/GRAPHICS/VGAGen.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/521337848/Hardware/GRAPHICS/VGAGen.v:166: Cell has missing pin: \'cclk\'\noutputVideo oV(.clk(clk),\n            ^~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-MULTITOP: data/full_repos/permissive/521337848/Hardware/GRAPHICS/VGAGen.v:40: Multiple top level modules\n                                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                     : ... Top module \'collector\'\nmodule collector(\n       ^~~~~~~~~\n                                                                                     : ... Top module \'lastBlock\'\nmodule lastBlock(\n       ^~~~~~~~~\n                                                                                     : ... Top module \'buffer9\'\nmodule buffer9(\n       ^~~~~~~\n                                                                                     : ... Top module \'next\'\nmodule next(\n       ^~~~\n                                                                                     : ... Top module \'clkdiv\'\nmodule clkdiv(\n       ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/521337848/Hardware/GRAPHICS/VGAGen.v:113: Signal definition not found, creating implicitly: \'ins4\'\n                                                                                      : ... Suggested alternative: \'ins\'\nbuffer b13(.clk(dclk),.in(ins3),.out(ins4));\n                                     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/GRAPHICS/VGAGen.v:155: Input port connection \'CounterX\' expects 10 bits on the pin connection, but pin connection\'s VARREF \'xc2\' generates 1 bits.\n                                                                                   : ... In instance lastBlock\n    .CounterX(xc2),\n     ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/GRAPHICS/VGAGen.v:156: Input port connection \'CounterY\' expects 9 bits on the pin connection, but pin connection\'s VARREF \'yc2\' generates 1 bits.\n                                                                                   : ... In instance lastBlock\n    .CounterY(yc2),\n     ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/GRAPHICS/VGAGen.v:354: Operator ASSIGNW expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance next\nassign out = {CounterX[6:2],3\'b0};\n           ^\n%Error: Exiting due to 6 warning(s)\n'
module outputVideo(
	input clk,
	input cclk,
	
	input xR,
	input xG,
	input xB,
	
	input ins,
	
	input xhsync,
	input xvsync,
	
	output reg hsync,
	output reg vsync,
	
	output reg R,
	output reg G,
	output reg B
);

reg f_R;
reg f_G;
reg f_B;

always@(posedge clk)begin
	R <= f_R;
	G <= f_G;
	B <= f_B;
end

always@(posedge clk)begin
	hsync <= xhsync;
	vsync <= xvsync;
end

always@(*)begin
	f_R = 0;
	f_G = 0;
	f_B = 0;
	
	if(ins) begin
		f_R = xR;
		f_G = xG;
		f_B = xB;
	end
	
end

endmodule
module outputVideo(
	input clk,
	input cclk,
	
	input xR,
	input xG,
	input xB,
	
	input ins,
	
	input xhsync,
	input xvsync,
	
	output reg hsync,
	output reg vsync,
	
	output reg R,
	output reg G,
	output reg B
);


reg f_R;
reg f_G;
reg f_B;

always@(posedge clk)begin
	R <= f_R;
	G <= f_G;
	B <= f_B;
end

always@(posedge clk)begin
	hsync <= xhsync;
	vsync <= xvsync;
end

always@(*)begin
	f_R = 0;
	f_G = 0;
	f_B = 0;
	
	if(ins) begin
		f_R = xR;
		f_G = xG;
		f_B = xB;
	end
	
end

endmodule