data/full_repos/permissive/493019833/test/testcase/firrtl/DoesAbs/sbt/DoesAbs.v
data/verilator_xmls/355169dd-379c-4cd9-adbc-d603ca790d9d.xml
module DoesAbs(
  input        clock,
  input        reset,
  input  [3:0] io_uIn,
  input  [3:0] io_sIn,
  input  [4:0] io_fIn,
  output [3:0] io_uAbsGrow,
  output [3:0] io_uAbsWrap,
  output [4:0] io_sAbsGrow,
  output [3:0] io_sAbsWrap,
  output [5:0] io_fAbsGrow,
  output [4:0] io_fAbsWrap
);
  wire  _T_8 = $signed(io_sIn) >= 4'sh0;
  wire [4:0] _T_11 = 4'sh0 - $signed(io_sIn);
  wire [3:0] _T_21 = 4'sh0 - $signed(io_sIn);
  wire [5:0] _T_27 = 5'sh0 - $signed(io_fIn);
  wire [4:0] _T_37 = 5'sh0 - $signed(io_fIn);
  assign io_uAbsGrow = io_uIn;
  assign io_uAbsWrap = io_uIn;
  assign io_sAbsGrow = _T_8 ? $signed({{1{io_sIn[3]}},io_sIn}) : $signed(_T_11);
  assign io_sAbsWrap = _T_8 ? $signed(io_sIn) : $signed(_T_21);
  assign io_fAbsGrow = io_fIn[4] ? $signed(_T_27) : $signed({{1{io_fIn[4]}},io_fIn});
  assign io_fAbsWrap = io_fIn[4] ? $signed(_T_37) : $signed(io_fIn);
endmodule
module DoesAbs(
  input        clock,
  input        reset,
  input  [3:0] io_uIn,
  input  [3:0] io_sIn,
  input  [4:0] io_fIn,
  output [3:0] io_uAbsGrow,
  output [3:0] io_uAbsWrap,
  output [4:0] io_sAbsGrow,
  output [3:0] io_sAbsWrap,
  output [5:0] io_fAbsGrow,
  output [4:0] io_fAbsWrap
);

  wire  _T_8 = $signed(io_sIn) >= 4'sh0;
  wire [4:0] _T_11 = 4'sh0 - $signed(io_sIn);
  wire [3:0] _T_21 = 4'sh0 - $signed(io_sIn);
  wire [5:0] _T_27 = 5'sh0 - $signed(io_fIn);
  wire [4:0] _T_37 = 5'sh0 - $signed(io_fIn);
  assign io_uAbsGrow = io_uIn;
  assign io_uAbsWrap = io_uIn;
  assign io_sAbsGrow = _T_8 ? $signed({{1{io_sIn[3]}},io_sIn}) : $signed(_T_11);
  assign io_sAbsWrap = _T_8 ? $signed(io_sIn) : $signed(_T_21);
  assign io_fAbsGrow = io_fIn[4] ? $signed(_T_27) : $signed({{1{io_fIn[4]}},io_fIn});
  assign io_fAbsWrap = io_fIn[4] ? $signed(_T_37) : $signed(io_fIn);
endmodule