data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v
1: b'%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:24: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters_cla.v\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters_cla.v.v\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters_cla.v.sv\n             ./const/parameters_cla.v\n             ./const/parameters_cla.v.v\n             ./const/parameters_cla.v.sv\n             obj_dir/./const/parameters_cla.v\n             obj_dir/./const/parameters_cla.v.v\n             obj_dir/./const/parameters_cla.v.sv\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:55: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:76: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:106: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:125: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:146: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:172: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/CLA_16.v:200: Cannot find include file: ./const/parameters_cla.v\n`include "./const/parameters_cla.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n'
module PRESTAGE_16 ( A, B, CIN, PHI, POUT, GOUT );
`include "./const/parameters_cla.v"

input  [N_16-1:0] A;
input  [N_16-1:0] B;
input  CIN;
input  PHI;
output [N_16-1:0] POUT;
output [N_16:0] GOUT;


INVBLOCK U2 (CIN , PHI , GOUT[0] );
genvar i;
  generate
  for(i=0;i<=N_16-1;i=i+1) begin: gen_prop
  BLOCK0 U(A[i] , B[i] , PHI , POUT[i] , GOUT[i+1] );
  end
  endgenerate
 
endmodule
module PRESTAGE_16 ( A, B, CIN, PHI, POUT, GOUT );

`include "./const/parameters_cla.v"

input  [N_16-1:0] A;
input  [N_16-1:0] B;
input  CIN;
input  PHI;
output [N_16-1:0] POUT;
output [N_16:0] GOUT;


INVBLOCK U2 (CIN , PHI , GOUT[0] );
genvar i;
  generate
  for(i=0;i<=N_16-1;i=i+1) begin: gen_prop
  BLOCK0 U(A[i] , B[i] , PHI , POUT[i] , GOUT[i+1] );
  end
  endgenerate
 
endmodule