data/full_repos/permissive/441359809/src/yosys/backends/smt2/example.v
1: b'%Error: data/full_repos/permissive/441359809/src/yosys/backends/smt2/example.v:9: Unsupported: Unclocked assertion\n                                                                                : ... In instance main\n assert property (counter != 15);\n ^~~~~~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main(input clk);
	reg [3:0] counter = 0;
	always @(posedge clk) begin
		if (counter == 10)
			counter <= 0;
		else
			counter <= counter + 1;
	end
	assert property (counter != 15);

endmodule
module main(input clk);

	reg [3:0] counter = 0;
	always @(posedge clk) begin
		if (counter == 10)
			counter <= 0;
		else
			counter <= counter + 1;
	end
	assert property (counter != 15);

endmodule