data/full_repos/permissive/441359809/src/yosys/tests/arch/ice40/macc.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/tests/arch/ice40/macc.v:27: Multiple top level modules\n                                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                            : ... Top module \'top\'\nmodule top(clk,a,b,c,set);\n       ^~~\n                                                                                            : ... Top module \'top2\'\nmodule top2(clk,a,b,c,hold);\n       ^~~~\n%Error: Exiting due to 1 warning(s)\n'
module top(clk,a,b,c,set);
parameter A_WIDTH = 6;
parameter B_WIDTH = 6;
input set;
input clk;
input signed [(A_WIDTH - 1):0] a;
input signed [(B_WIDTH - 1):0] b;
output signed [(A_WIDTH + B_WIDTH - 1):0] c;
reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c;
assign c = reg_tmp_c;
always @(posedge clk)
begin
    if(set)
    begin
        reg_tmp_c <= 0;
    end
    else
    begin
        reg_tmp_c <= a * b + c;
    end
end
endmodule
module top(clk,a,b,c,set);

parameter A_WIDTH = 6;
parameter B_WIDTH = 6;
input set;
input clk;
input signed [(A_WIDTH - 1):0] a;
input signed [(B_WIDTH - 1):0] b;
output signed [(A_WIDTH + B_WIDTH - 1):0] c;
reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c;
assign c = reg_tmp_c;
always @(posedge clk)
begin
    if(set)
    begin
        reg_tmp_c <= 0;
    end
    else
    begin
        reg_tmp_c <= a * b + c;
    end
end
endmodule