data/full_repos/permissive/496508301/Lesson1/inverter/inv.v
data/verilator_xmls/6ab180bf-7fb1-453b-9bb5-d6df38013085.xml
module inv( 
    A,
    Y
);
input  A;
output Y;

assign Y=~A;
endmodule
module inv( 
    A,
    Y
);

input  A;
output Y;

assign Y=~A;
endmodule