data/full_repos/permissive/423410371/src/synth/reset_gen.v
data/verilator_xmls/6e6efd0c-36f7-497d-b30b-bd2f8bf732ff.xml
module reset_gen #(parameter RESET_CYCLES = 200)
                (
                 input clk,
                 output wire reset_n
                 );





  reg [7 : 0] reset_ctr_reg = 8'h0;
  reg [7 : 0] reset_ctr_new;
  reg         reset_ctr_we;

  reg         reset_n_reg = 1'h0;
  reg         reset_n_new;





  assign reset_n = reset_n_reg;





    always @(posedge clk)
      begin : reg_update
        reset_n_reg <= reset_n_new;

        if (reset_ctr_we)
          reset_ctr_reg <= reset_ctr_new;
      end





  always @*
    begin : reset_logic
      reset_n_new   = 1'h1;
      reset_ctr_new = 8'h0;
      reset_ctr_we  = 1'h0;

      if (reset_ctr_reg < RESET_CYCLES) begin
        reset_n_new   = 1'h0;
        reset_ctr_new = reset_ctr_reg + 1'h1;
        reset_ctr_we  = 1'h1;
      end
    end

endmodule
module reset_gen #(parameter RESET_CYCLES = 200)
                (
                 input clk,
                 output wire reset_n
                 );






  reg [7 : 0] reset_ctr_reg = 8'h0;
  reg [7 : 0] reset_ctr_new;
  reg         reset_ctr_we;

  reg         reset_n_reg = 1'h0;
  reg         reset_n_new;





  assign reset_n = reset_n_reg;





    always @(posedge clk)
      begin : reg_update
        reset_n_reg <= reset_n_new;

        if (reset_ctr_we)
          reset_ctr_reg <= reset_ctr_new;
      end





  always @*
    begin : reset_logic
      reset_n_new   = 1'h1;
      reset_ctr_new = 8'h0;
      reset_ctr_we  = 1'h0;

      if (reset_ctr_reg < RESET_CYCLES) begin
        reset_n_new   = 1'h0;
        reset_ctr_new = reset_ctr_reg + 1'h1;
        reset_ctr_we  = 1'h1;
      end
    end

endmodule