data/full_repos/permissive/42434302/ivltests/pr2138979d.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:133: Operator COND expects 16 bits on the Conditional True, but Conditional True\'s VARREF \'a\' generates 8 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign mux_uu = sel ?         a  :         b ;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:133: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'b\' generates 8 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign mux_uu = sel ?         a  :         b ;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:134: Operator COND expects 16 bits on the Conditional True, but Conditional True\'s VARREF \'a\' generates 8 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign mux_us = sel ?         a  : $signed(b);\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:134: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s SIGNED generates 8 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign mux_us = sel ?         a  : $signed(b);\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:135: Operator COND expects 16 bits on the Conditional True, but Conditional True\'s SIGNED generates 8 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign mux_su = sel ? $signed(a) :         b ;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:135: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'b\' generates 8 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign mux_su = sel ? $signed(a) :         b ;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:136: Operator COND expects 16 bits on the Conditional True, but Conditional True\'s SIGNED generates 8 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign mux_ss = sel ? $signed(a) : $signed(b);\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:136: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s SIGNED generates 8 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign mux_ss = sel ? $signed(a) : $signed(b);\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:138: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'c\' generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign eql_uu =         a  ==         c ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:139: Operator EQ expects 8 bits on the RHS, but RHS\'s SIGNED generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign eql_us =         a  == $signed(c);\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:140: Operator EQ expects 8 bits on the RHS, but RHS\'s VARREF \'c\' generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign eql_su = $signed(a) ==         c ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:141: Operator EQ expects 8 bits on the RHS, but RHS\'s SIGNED generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign eql_ss = $signed(a) == $signed(c);\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:143: Operator NEQ expects 8 bits on the RHS, but RHS\'s VARREF \'c\' generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign neq_uu =         a  !=         c ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:144: Operator NEQ expects 8 bits on the RHS, but RHS\'s SIGNED generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign neq_us =         a  != $signed(c);\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:145: Operator NEQ expects 8 bits on the RHS, but RHS\'s VARREF \'c\' generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign neq_su = $signed(a) !=         c ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:146: Operator NEQ expects 8 bits on the RHS, but RHS\'s SIGNED generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign neq_ss = $signed(a) != $signed(c);\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:148: Operator NOT expects 16 bits on the LHS, but LHS\'s UNSIGNED generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign sgn_u = ~$unsigned(c) ;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:149: Operator NOT expects 16 bits on the LHS, but LHS\'s SIGNED generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign sgn_s = ~$signed(c) ;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:151: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'a\' generates 8 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign add_uu =         a  +         c ;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:151: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'c\' generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign add_uu =         a  +         c ;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:152: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'a\' generates 8 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign add_us =         a  + $signed(c);\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:152: Operator ADD expects 16 bits on the RHS, but RHS\'s SIGNED generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign add_us =         a  + $signed(c);\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:153: Operator ADD expects 16 bits on the LHS, but LHS\'s SIGNED generates 8 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign add_su = $signed(a) +         c ;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:153: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'c\' generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign add_su = $signed(a) +         c ;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:154: Operator ADD expects 16 bits on the LHS, but LHS\'s SIGNED generates 8 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign add_ss = $signed(a) + $signed(c);\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:154: Operator ADD expects 16 bits on the RHS, but RHS\'s SIGNED generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign add_ss = $signed(a) + $signed(c);\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:156: Operator SUB expects 16 bits on the LHS, but LHS\'s VARREF \'a\' generates 8 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign sub_uu =         a  -         c ;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:156: Operator SUB expects 16 bits on the RHS, but RHS\'s VARREF \'c\' generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign sub_uu =         a  -         c ;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:157: Operator SUB expects 16 bits on the LHS, but LHS\'s VARREF \'a\' generates 8 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign sub_us =         a  - $signed(c);\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:157: Operator SUB expects 16 bits on the RHS, but RHS\'s SIGNED generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign sub_us =         a  - $signed(c);\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:158: Operator SUB expects 16 bits on the LHS, but LHS\'s SIGNED generates 8 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign sub_su = $signed(a) -         c ;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:158: Operator SUB expects 16 bits on the RHS, but RHS\'s VARREF \'c\' generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign sub_su = $signed(a) -         c ;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:159: Operator SUB expects 16 bits on the LHS, but LHS\'s SIGNED generates 8 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign sub_ss = $signed(a) - $signed(c);\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:159: Operator SUB expects 16 bits on the RHS, but RHS\'s SIGNED generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign sub_ss = $signed(a) - $signed(c);\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:166: Operator LT expects 8 bits on the RHS, but RHS\'s VARREF \'c\' generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign ltn_uu =         a  <         c ;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:167: Operator LT expects 8 bits on the RHS, but RHS\'s SIGNED generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign ltn_us =         a  < $signed(c);\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:168: Operator LT expects 8 bits on the RHS, but RHS\'s VARREF \'c\' generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign ltn_su = $signed(a) <         c ;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:169: Operator LTS expects 8 bits on the RHS, but RHS\'s SIGNED generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign ltn_ss = $signed(a) < $signed(c);\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:171: Operator LTE expects 8 bits on the RHS, but RHS\'s VARREF \'c\' generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign leq_uu =         a  <=         c ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:172: Operator LTE expects 8 bits on the RHS, but RHS\'s SIGNED generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign leq_us =         a  <= $signed(c);\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:173: Operator LTE expects 8 bits on the RHS, but RHS\'s VARREF \'c\' generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign leq_su = $signed(a) <=         c ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:174: Operator LTES expects 8 bits on the RHS, but RHS\'s SIGNED generates 6 bits.\n                                                                             : ... In instance signed_logic_operators_bug.INST2\nassign leq_ss = $signed(a) <= $signed(c);\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:30: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                            : ... In instance signed_logic_operators_bug\n        sel = $random;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:31: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                            : ... In instance signed_logic_operators_bug\n        a   = $random;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                            : ... In instance signed_logic_operators_bug\n        b   = $random;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr2138979d.v:33: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                            : ... In instance signed_logic_operators_bug\n        c   = $random;\n            ^\n%Error: Exiting due to 47 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module signed_operators(
    sel,
    a, b,
    c,
    mux_uu, mux_us, mux_su, mux_ss,
    eql_uu, eql_us, eql_su, eql_ss,
    neq_uu, neq_us, neq_su, neq_ss,
    sgn_u,  sgn_s,
    add_uu, add_us, add_su, add_ss,
    sub_uu, sub_us, sub_su, sub_ss,
    mul_uu, mul_us, mul_su, mul_ss,
    ltn_uu, ltn_us, ltn_su, ltn_ss,
    leq_uu, leq_us, leq_su, leq_ss
    );

input         sel;
input   [7:0] a, b;
input   [5:0] c;
output [15:0] mux_uu, mux_us, mux_su, mux_ss;
output        eql_uu, eql_us, eql_su, eql_ss;
output        neq_uu, neq_us, neq_su, neq_ss;
output [15:0] sgn_u,  sgn_s;
output [15:0] add_uu, add_us, add_su, add_ss;
output [15:0] sub_uu, sub_us, sub_su, sub_ss;
output [15:0] mul_uu, mul_us, mul_su, mul_ss;
output        ltn_uu, ltn_us, ltn_su, ltn_ss;
output        leq_uu, leq_us, leq_su, leq_ss;





assign mux_uu = sel ?         a  :         b ;
assign mux_us = sel ?         a  : $signed(b);
assign mux_su = sel ? $signed(a) :         b ;
assign mux_ss = sel ? $signed(a) : $signed(b);

assign eql_uu =         a  ==         c ;
assign eql_us =         a  == $signed(c);
assign eql_su = $signed(a) ==         c ;
assign eql_ss = $signed(a) == $signed(c);

assign neq_uu =         a  !=         c ;
assign neq_us =         a  != $signed(c);
assign neq_su = $signed(a) !=         c ;
assign neq_ss = $signed(a) != $signed(c);

assign sgn_u = ~$unsigned(c) ;
assign sgn_s = ~$signed(c) ;

assign add_uu =         a  +         c ;
assign add_us =         a  + $signed(c);
assign add_su = $signed(a) +         c ;
assign add_ss = $signed(a) + $signed(c);

assign sub_uu =         a  -         c ;
assign sub_us =         a  - $signed(c);
assign sub_su = $signed(a) -         c ;
assign sub_ss = $signed(a) - $signed(c);

assign mul_uu =         a  *         c ;
assign mul_us =         a  * $signed(c);
assign mul_su = $signed(a) *         c ;
assign mul_ss = $signed(a) * $signed(c);

assign ltn_uu =         a  <         c ;
assign ltn_us =         a  < $signed(c);
assign ltn_su = $signed(a) <         c ;
assign ltn_ss = $signed(a) < $signed(c);

assign leq_uu =         a  <=         c ;
assign leq_us =         a  <= $signed(c);
assign leq_su = $signed(a) <=         c ;
assign leq_ss = $signed(a) <= $signed(c);

endmodule
module signed_operators(
    sel,
    a, b,
    c,
    mux_uu, mux_us, mux_su, mux_ss,
    eql_uu, eql_us, eql_su, eql_ss,
    neq_uu, neq_us, neq_su, neq_ss,
    sgn_u,  sgn_s,
    add_uu, add_us, add_su, add_ss,
    sub_uu, sub_us, sub_su, sub_ss,
    mul_uu, mul_us, mul_su, mul_ss,
    ltn_uu, ltn_us, ltn_su, ltn_ss,
    leq_uu, leq_us, leq_su, leq_ss
    );


input         sel;
input   [7:0] a, b;
input   [5:0] c;
output [15:0] mux_uu, mux_us, mux_su, mux_ss;
output        eql_uu, eql_us, eql_su, eql_ss;
output        neq_uu, neq_us, neq_su, neq_ss;
output [15:0] sgn_u,  sgn_s;
output [15:0] add_uu, add_us, add_su, add_ss;
output [15:0] sub_uu, sub_us, sub_su, sub_ss;
output [15:0] mul_uu, mul_us, mul_su, mul_ss;
output        ltn_uu, ltn_us, ltn_su, ltn_ss;
output        leq_uu, leq_us, leq_su, leq_ss;





assign mux_uu = sel ?         a  :         b ;
assign mux_us = sel ?         a  : $signed(b);
assign mux_su = sel ? $signed(a) :         b ;
assign mux_ss = sel ? $signed(a) : $signed(b);

assign eql_uu =         a  ==         c ;
assign eql_us =         a  == $signed(c);
assign eql_su = $signed(a) ==         c ;
assign eql_ss = $signed(a) == $signed(c);

assign neq_uu =         a  !=         c ;
assign neq_us =         a  != $signed(c);
assign neq_su = $signed(a) !=         c ;
assign neq_ss = $signed(a) != $signed(c);

assign sgn_u = ~$unsigned(c) ;
assign sgn_s = ~$signed(c) ;

assign add_uu =         a  +         c ;
assign add_us =         a  + $signed(c);
assign add_su = $signed(a) +         c ;
assign add_ss = $signed(a) + $signed(c);

assign sub_uu =         a  -         c ;
assign sub_us =         a  - $signed(c);
assign sub_su = $signed(a) -         c ;
assign sub_ss = $signed(a) - $signed(c);

assign mul_uu =         a  *         c ;
assign mul_us =         a  * $signed(c);
assign mul_su = $signed(a) *         c ;
assign mul_ss = $signed(a) * $signed(c);

assign ltn_uu =         a  <         c ;
assign ltn_us =         a  < $signed(c);
assign ltn_su = $signed(a) <         c ;
assign ltn_ss = $signed(a) < $signed(c);

assign leq_uu =         a  <=         c ;
assign leq_us =         a  <= $signed(c);
assign leq_su = $signed(a) <=         c ;
assign leq_ss = $signed(a) <= $signed(c);

endmodule