data/full_repos/permissive/524509242/FSM GCD/debouncer.v
1: b'%Error: Cannot find file containing module: GCD,data/full_repos/permissive/524509242\n        ... Looked in:\n             data/full_repos/permissive/524509242/FSM/GCD,data/full_repos/permissive/524509242\n             data/full_repos/permissive/524509242/FSM/GCD,data/full_repos/permissive/524509242.v\n             data/full_repos/permissive/524509242/FSM/GCD,data/full_repos/permissive/524509242.sv\n             GCD,data/full_repos/permissive/524509242\n             GCD,data/full_repos/permissive/524509242.v\n             GCD,data/full_repos/permissive/524509242.sv\n             obj_dir/GCD,data/full_repos/permissive/524509242\n             obj_dir/GCD,data/full_repos/permissive/524509242.v\n             obj_dir/GCD,data/full_repos/permissive/524509242.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/524509242/FSM\n%Error: Cannot find file containing module: GCD/debouncer.v\n%Error: Exiting due to 3 error(s)\n'
module debouncer(clk, clock_div, in, out);
	input clk;
	input clock_div;
	input in;
	output reg out = 1'b0;
	
	reg sync = 1'b0;
	reg sync2 = 1'b0;
	reg sync3 = 1'b0;
	reg clock_div_prev = 1'b0;
	reg out_prev = 1'b0;
	
	always @(posedge clk) begin
		
		sync <= in;
		sync2 <= sync;
		sync3 <= sync2;
		

		clock_div_prev <= clock_div;
		out_prev <= out;	
		



		out <= (!sync3 && sync2) || (out && (!(clock_div && !clock_div_prev) || !out_prev));
	end
endmodule
module debouncer(clk, clock_div, in, out);

	input clk;
	input clock_div;
	input in;
	output reg out = 1'b0;
	
	reg sync = 1'b0;
	reg sync2 = 1'b0;
	reg sync3 = 1'b0;
	reg clock_div_prev = 1'b0;
	reg out_prev = 1'b0;
	
	always @(posedge clk) begin
		
		sync <= in;
		sync2 <= sync;
		sync3 <= sync2;
		

		clock_div_prev <= clock_div;
		out_prev <= out;	
		



		out <= (!sync3 && sync2) || (out && (!(clock_div && !clock_div_prev) || !out_prev));
	end
endmodule