data/full_repos/permissive/452183855/lab1/Lab1_dataflow.v
data/verilator_xmls/eec5d751-5488-4efa-985b-a130b203fe34.xml
module Lab1_dataflow(F, A, B, C, D);
    output F;
    input  A, B, C, D;
    wire   w1, w2, w3, w4, w5, w6, w7, w8;

    assign F= ((!(A && C)) || (B && (!D))) && (A ||((!B) && D));

endmodule
module Lab1_dataflow(F, A, B, C, D);

    output F;
    input  A, B, C, D;
    wire   w1, w2, w3, w4, w5, w6, w7, w8;

    assign F= ((!(A && C)) || (B && (!D))) && (A ||((!B) && D));

endmodule