data/full_repos/permissive/515636003/divby3.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/515636003/divby3.v:11: Little bit endian vector: MSB < LSB of bit range: 0:7\ninput [0:N-1] num;\n      ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module div_by_3_detector (clk, rst, num, state, isdiv_by_3);


parameter N = 8;

parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10;


input clk, rst;

input [0:N-1] num;



output wire isdiv_by_3;

output reg [1:0] state; 



reg [3:0] count;



wire done;



assign isdiv_by_3 = (state == S0);


assign done = (count == N); 




always @(posedge clk or posedge rst) begin
    if (rst) count <= 4'b0;	
    else if (~done) count <= count + 1;
end


always @(posedge clk or posedge rst) begin
    if (rst) state <= S0;
    else if (~done) begin
        case (state)
            S0: if (num[count]==1'b0) state <= S0; 
                else if (num[count]==1'b1) state <= S1;
            S1: if (num[count]==1'b0) state <= S2; 
                else if (num[count]==1'b1) state <= S0;
            S2: if (num[count]==1'b0) state <= S1; 
                else if (num[count]==1'b1) state <= S2;
            default: state <= S0; 
        endcase
    end
end

endmodule
module div_by_3_detector (clk, rst, num, state, isdiv_by_3);



parameter N = 8;

parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10;


input clk, rst;

input [0:N-1] num;



output wire isdiv_by_3;

output reg [1:0] state; 



reg [3:0] count;



wire done;



assign isdiv_by_3 = (state == S0);


assign done = (count == N); 




always @(posedge clk or posedge rst) begin
    if (rst) count <= 4'b0;	
    else if (~done) count <= count + 1;
end


always @(posedge clk or posedge rst) begin
    if (rst) state <= S0;
    else if (~done) begin
        case (state)
            S0: if (num[count]==1'b0) state <= S0; 
                else if (num[count]==1'b1) state <= S1;
            S1: if (num[count]==1'b0) state <= S2; 
                else if (num[count]==1'b1) state <= S0;
            S2: if (num[count]==1'b0) state <= S1; 
                else if (num[count]==1'b1) state <= S2;
            default: state <= S0; 
        endcase
    end
end

endmodule