data/full_repos/permissive/414822257/ip/third_party/picorv32_wb/mem_ff_wb.v
1: b"%Error: data/full_repos/permissive/414822257/ip/third_party/picorv32_wb/mem_ff_wb.v:41: Duplicate declaration of signal: 'wb_ack_o'\n                                                                                      : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n  reg wb_ack_o;\n      ^~~~~~~~\n        data/full_repos/permissive/414822257/ip/third_party/picorv32_wb/mem_ff_wb.v:19: ... Location of original declaration\n  output wb_ack_o,\n         ^~~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module ff32_ram #(
  parameter ADDR_WIDTH = 8
)(
  input clk,

  input [ADDR_WIDTH-1:0] addr,
  input [31:0] din,
  output reg [31:0] dout,

  input en,
  input [3:0] wmask
);
  reg [7:0] ram0 [(1<<ADDR_WIDTH)-1:0];
  reg [7:0] ram1 [(1<<ADDR_WIDTH)-1:0];
  reg [7:0] ram2 [(1<<ADDR_WIDTH)-1:0];
  reg [7:0] ram3 [(1<<ADDR_WIDTH)-1:0];

`ifdef SIM
  integer i;
  initial begin
    for (i = 0; i < (1<<ADDR_WIDTH); i = i + 1) begin
      ram0[i] = 8'b0;
      ram1[i] = 8'b0;
      ram2[i] = 8'b0;
      ram3[i] = 8'b0;
    end
  end
`endif


  always @(posedge clk) begin
    if (en) begin
      if (wmask[0])
        ram0[addr] <= din[7:0];
      if (wmask[1])
        ram1[addr] <= din[15:8];
      if (wmask[2])
        ram2[addr] <= din[23:16];
      if (wmask[3])
        ram3[addr] <= din[31:24];
    end
  end


  always @(posedge clk) begin
    if (en) begin
      dout[7:0] <= ram0[addr];
      dout[15:8] <= ram1[addr];
      dout[23:16] <= ram2[addr];
      dout[31:24] <= ram3[addr];
    end
  end
endmodule
module ff32_ram #(
  parameter ADDR_WIDTH = 8
)(
  input clk,

  input [ADDR_WIDTH-1:0] addr,
  input [31:0] din,
  output reg [31:0] dout,

  input en,
  input [3:0] wmask
);

  reg [7:0] ram0 [(1<<ADDR_WIDTH)-1:0];
  reg [7:0] ram1 [(1<<ADDR_WIDTH)-1:0];
  reg [7:0] ram2 [(1<<ADDR_WIDTH)-1:0];
  reg [7:0] ram3 [(1<<ADDR_WIDTH)-1:0];

`ifdef SIM
  integer i;
  initial begin
    for (i = 0; i < (1<<ADDR_WIDTH); i = i + 1) begin
      ram0[i] = 8'b0;
      ram1[i] = 8'b0;
      ram2[i] = 8'b0;
      ram3[i] = 8'b0;
    end
  end
`endif


  always @(posedge clk) begin
    if (en) begin
      if (wmask[0])
        ram0[addr] <= din[7:0];
      if (wmask[1])
        ram1[addr] <= din[15:8];
      if (wmask[2])
        ram2[addr] <= din[23:16];
      if (wmask[3])
        ram3[addr] <= din[31:24];
    end
  end


  always @(posedge clk) begin
    if (en) begin
      dout[7:0] <= ram0[addr];
      dout[15:8] <= ram1[addr];
      dout[23:16] <= ram2[addr];
      dout[31:24] <= ram3[addr];
    end
  end
endmodule