data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram/xil_sdp_ram_be.v
1: b'%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram/xil_sdp_ram_be.v:29: Cannot find include file: xil_xpm_param.vh\n`include "xil_xpm_param.vh" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram,data/full_repos/permissive/530013823/xil_xpm_param.vh\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram,data/full_repos/permissive/530013823/xil_xpm_param.vh.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram,data/full_repos/permissive/530013823/xil_xpm_param.vh.sv\n             xil_xpm_param.vh\n             xil_xpm_param.vh.v\n             xil_xpm_param.vh.sv\n             obj_dir/xil_xpm_param.vh\n             obj_dir/xil_xpm_param.vh.v\n             obj_dir/xil_xpm_param.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module  xil_sdp_ram_be
    (
     clka   ,
     adra   ,
     wena   ,
     wdaa   ,
     bwea   ,
     clkb   ,
     adrb   ,
     renb   ,
     rdab
     );

parameter   ADRA= 11;
parameter   WIDA=  9;
parameter   DEPA= 18432;
parameter   ADRB= 11;
parameter   WIDB=  9;
parameter   DEPB= 18432;
parameter   TYPE= "ultra";
parameter   INIT= "none";
parameter   MCLK= "common_clock";
parameter   MRWA= "read_first";
parameter   MRWB= "read_first";
parameter   NCLK= 2;

`include "xil_xpm_param.vh"

input               clka;
input [ADRA-1:0]    adra;
input               wena;
input [WIDA-1:0]    wdaa;
input [WIDA/8-1:0]  bwea;

input               clkb;
input [ADRB-1:0]    adrb;
input               renb;
output [WIDB-1:0]   rdab;




URAM288_BASE #(
               .AUTO_SLEEP_LATENCY(8),
               .AVG_CONS_INACTIVE_CYCLES(10),

               .BWE_MODE_A("PARITY_INDEPENDENT"),
               .BWE_MODE_B("PARITY_INDEPENDENT"),
               .EN_AUTO_SLEEP_MODE("FALSE"),
               .EN_ECC_RD_A("FALSE"),
               .EN_ECC_RD_B("FALSE"),
               .EN_ECC_WR_A("FALSE"),
               .EN_ECC_WR_B("FALSE"),
               .IREG_PRE_A("FALSE"),
               .IREG_PRE_B("FALSE"),
               .IS_CLK_INVERTED(1'b0),
               .IS_EN_A_INVERTED(1'b0),
               .IS_EN_B_INVERTED(1'b0),
               .IS_RDB_WR_A_INVERTED(1'b0),
               .IS_RDB_WR_B_INVERTED(1'b0),
               .IS_RST_A_INVERTED(1'b0),
               .IS_RST_B_INVERTED(1'b0),




               .OREG_A("TRUE"),
               .OREG_B("TRUE"),
               .OREG_ECC_A("FALSE"),
               .OREG_ECC_B("FALSE"),
               .RST_MODE_A("SYNC"),
               .RST_MODE_B("SYNC"),
               .USE_EXT_CE_A("FALSE"),
               .USE_EXT_CE_B("FALSE")
               )
URAM288_BASE_inst (
                   .DBITERR_A(),
                   .DBITERR_B(),
                   .DOUT_A(),
                   .DOUT_B(rdab),
                   .SBITERR_A(SBITERR_A),
                   .SBITERR_B(SBITERR_B),
                   .ADDR_A(adra),
                   .ADDR_B(adrb),
                   .BWE_A(bwea),
                   .BWE_B(0),
                   .CLK(clka),
                   .DIN_A(wdaa),
                   .DIN_B(0),
                   .EN_A(wena),
                   .EN_B(1),
                   .INJECT_DBITERR_A(0),
                   .INJECT_DBITERR_B(0),
                   .INJECT_SBITERR_A(0),
                   .INJECT_SBITERR_B(0),
                   .OREG_CE_A(1),
                   .OREG_CE_B(1),
                   .OREG_ECC_CE_A(1),
                   .OREG_ECC_CE_B(1),
                   .RDB_WR_A(1),
                   .RDB_WR_B(0),
                   .RST_A(0),

                   .RST_B(0),

                   .SLEEP(0)
                   );

                
endmodule
module  xil_sdp_ram_be
    (
     clka   ,
     adra   ,
     wena   ,
     wdaa   ,
     bwea   ,
     clkb   ,
     adrb   ,
     renb   ,
     rdab
     );


parameter   ADRA= 11;
parameter   WIDA=  9;
parameter   DEPA= 18432;
parameter   ADRB= 11;
parameter   WIDB=  9;
parameter   DEPB= 18432;
parameter   TYPE= "ultra";
parameter   INIT= "none";
parameter   MCLK= "common_clock";
parameter   MRWA= "read_first";
parameter   MRWB= "read_first";
parameter   NCLK= 2;

`include "xil_xpm_param.vh"

input               clka;
input [ADRA-1:0]    adra;
input               wena;
input [WIDA-1:0]    wdaa;
input [WIDA/8-1:0]  bwea;

input               clkb;
input [ADRB-1:0]    adrb;
input               renb;
output [WIDB-1:0]   rdab;




URAM288_BASE #(
               .AUTO_SLEEP_LATENCY(8),
               .AVG_CONS_INACTIVE_CYCLES(10),

               .BWE_MODE_A("PARITY_INDEPENDENT"),
               .BWE_MODE_B("PARITY_INDEPENDENT"),
               .EN_AUTO_SLEEP_MODE("FALSE"),
               .EN_ECC_RD_A("FALSE"),
               .EN_ECC_RD_B("FALSE"),
               .EN_ECC_WR_A("FALSE"),
               .EN_ECC_WR_B("FALSE"),
               .IREG_PRE_A("FALSE"),
               .IREG_PRE_B("FALSE"),
               .IS_CLK_INVERTED(1'b0),
               .IS_EN_A_INVERTED(1'b0),
               .IS_EN_B_INVERTED(1'b0),
               .IS_RDB_WR_A_INVERTED(1'b0),
               .IS_RDB_WR_B_INVERTED(1'b0),
               .IS_RST_A_INVERTED(1'b0),
               .IS_RST_B_INVERTED(1'b0),




               .OREG_A("TRUE"),
               .OREG_B("TRUE"),
               .OREG_ECC_A("FALSE"),
               .OREG_ECC_B("FALSE"),
               .RST_MODE_A("SYNC"),
               .RST_MODE_B("SYNC"),
               .USE_EXT_CE_A("FALSE"),
               .USE_EXT_CE_B("FALSE")
               )
URAM288_BASE_inst (
                   .DBITERR_A(),
                   .DBITERR_B(),
                   .DOUT_A(),
                   .DOUT_B(rdab),
                   .SBITERR_A(SBITERR_A),
                   .SBITERR_B(SBITERR_B),
                   .ADDR_A(adra),
                   .ADDR_B(adrb),
                   .BWE_A(bwea),
                   .BWE_B(0),
                   .CLK(clka),
                   .DIN_A(wdaa),
                   .DIN_B(0),
                   .EN_A(wena),
                   .EN_B(1),
                   .INJECT_DBITERR_A(0),
                   .INJECT_DBITERR_B(0),
                   .INJECT_SBITERR_A(0),
                   .INJECT_SBITERR_B(0),
                   .OREG_CE_A(1),
                   .OREG_CE_B(1),
                   .OREG_ECC_CE_A(1),
                   .OREG_ECC_CE_B(1),
                   .RDB_WR_A(1),
                   .RDB_WR_B(0),
                   .RST_A(0),

                   .RST_B(0),

                   .SLEEP(0)
                   );

                
endmodule