data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v
1: b"%Error: data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v:85: syntax error, unexpected type, expecting IDENTIFIER or '[' or do or final\n input  wire [1:0]           type,     \n                             ^~~~\n%Error: data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v:87: syntax error, unexpected ')', expecting ',' or ';'\n);\n^\n%Error: data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v:90: syntax error, unexpected IDENTIFIER\n    mirror m1(.in(a), .out(ma));\n    ^~~~~~\n%Error: data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v:379: syntax error, unexpected type\n        .type(alufn[1:0]),\n         ^~~~\n%Error: Exiting due to 4 error(s)\n"
module shift  #(parameter WIDTH=32, LOGWIDTH=$clog2(WIDTH) ) (
	input  wire [WIDTH-1:0]     a,
	input  wire [LOGWIDTH-1:0]  shamt,
	input  wire [1:0]           type,	    
	output wire [WIDTH-1:0]     r
);
    wire [WIDTH-1 : 0] ma, my, y, x, sy;

    mirror m1(.in(a), .out(ma));
    mirror m2(.in(y), .out(my));

    assign x = type[0] ? ma : a;
    
    shift_right shr (.a(x), .r(y), .shamt(shamt), .ar(type[1]));

    assign r = type[0] ? my : y;

endmodule
module shift  #(parameter WIDTH=32, LOGWIDTH=$clog2(WIDTH) ) (
	input  wire [WIDTH-1:0]     a,
	input  wire [LOGWIDTH-1:0]  shamt,
	input  wire [1:0]           type,	    
	output wire [WIDTH-1:0]     r
);

    wire [WIDTH-1 : 0] ma, my, y, x, sy;

    mirror m1(.in(a), .out(ma));
    mirror m2(.in(y), .out(my));

    assign x = type[0] ? ma : a;
    
    shift_right shr (.a(x), .r(y), .shamt(shamt), .ar(type[1]));

    assign r = type[0] ? my : y;

endmodule