data/full_repos/permissive/43856783/Integrador/inter_tst.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/43856783/Integrador/inter_tst.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/43856783/Integrador/inter_tst.v:66: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk <= !clk;\n        ^\n%Error: data/full_repos/permissive/43856783/Integrador/inter_tst.v:39: Cannot find file containing module: \'Integradorv2\'\n Integradorv2 uut (\n ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43856783/Integrador,data/full_repos/permissive/43856783/Integradorv2\n             data/full_repos/permissive/43856783/Integrador,data/full_repos/permissive/43856783/Integradorv2.v\n             data/full_repos/permissive/43856783/Integrador,data/full_repos/permissive/43856783/Integradorv2.sv\n             Integradorv2\n             Integradorv2.v\n             Integradorv2.sv\n             obj_dir/Integradorv2\n             obj_dir/Integradorv2.v\n             obj_dir/Integradorv2.sv\n%Warning-WIDTH: data/full_repos/permissive/43856783/Integrador/inter_tst.v:52: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'ha\' generates 5 bits.\n                                                                             : ... In instance inter_tst\n  dt = 5\'d10;\n     ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module inter_tst;


	reg [15:0] a;
	reg [15:0] dt;
	reg enable;
	reg rst;
	reg clk;


	wire [15:0] v;
	wire busy;


	Integradorv2 uut (
		.a(a), 
		.dt(dt), 
		.enable(enable), 
		.rst(rst), 
		.clk(clk), 
		.v(v), 
		.busy(busy)
	);

	initial begin

		a = 16'hAA;
		dt = 5'd10;
		enable = 0;
		rst = 1;
		clk = 0;


		#100;
     	  

		
		   enable = 1;
			rst = 0;
	end
	
	always #5 clk <= !clk;
      
endmodule
module inter_tst;



	reg [15:0] a;
	reg [15:0] dt;
	reg enable;
	reg rst;
	reg clk;


	wire [15:0] v;
	wire busy;


	Integradorv2 uut (
		.a(a), 
		.dt(dt), 
		.enable(enable), 
		.rst(rst), 
		.clk(clk), 
		.v(v), 
		.busy(busy)
	);

	initial begin

		a = 16'hAA;
		dt = 5'd10;
		enable = 0;
		rst = 1;
		clk = 0;


		#100;
     	  

		
		   enable = 1;
			rst = 0;
	end
	
	always #5 clk <= !clk;
      
endmodule