data/full_repos/permissive/488739248/rtl/ym3526/jtopl_eg_cnt.v
data/verilator_xmls/f70dfc27-9c10-4301-93f9-248ab52b18ca.xml
module jtopl_eg_cnt(
	input wire            rst,
	input wire            clk,
	input wire            cen,
	input wire            zero,
	output reg [14:0] eg_cnt
);

always @(posedge clk, posedge rst) begin : envelope_counter
	if( rst ) begin
		eg_cnt		<=15'd0;
	end
	else begin
		if( zero && cen ) begin



			eg_cnt <= eg_cnt + 1'b1;
		end
	end
end

endmodule
module jtopl_eg_cnt(
	input wire            rst,
	input wire            clk,
	input wire            cen,
	input wire            zero,
	output reg [14:0] eg_cnt
);


always @(posedge clk, posedge rst) begin : envelope_counter
	if( rst ) begin
		eg_cnt		<=15'd0;
	end
	else begin
		if( zero && cen ) begin



			eg_cnt <= eg_cnt + 1'b1;
		end
	end
end

endmodule