data/full_repos/permissive/445148650/tasks/Task202-DataFlowLevel/uop_nxor.sv
data/verilator_xmls/5faa28b9-5aed-4890-a4c7-d7fa9c105a2a.xml
module uop_nxor (output wire Y, input wire A, input wire B);






assign Y = ~A & ~B|A & B;






endmodule
module uop_nxor (output wire Y, input wire A, input wire B);







assign Y = ~A & ~B|A & B;






endmodule