data/full_repos/permissive/411838135/rv/synth/vsram.v
1: b'%Error: No top level module found\n%Error: Exiting due to 1 error(s)\n'
module HARD_SYNC(
    input   CLK,
    input   DIN,
    output  DOUT);

    parameter LATENCY=2;

    reg [LATENCY-1:0]r_sync;
    assign DOUT = r_sync[LATENCY-1];

    always @(posedge CLK)
        r_sync <= {r_sync[LATENCY-2:0],DIN};

endmodule
module HARD_SYNC(
    input   CLK,
    input   DIN,
    output  DOUT);


    parameter LATENCY=2;

    reg [LATENCY-1:0]r_sync;
    assign DOUT = r_sync[LATENCY-1];

    always @(posedge CLK)
        r_sync <= {r_sync[LATENCY-2:0],DIN};

endmodule