data/full_repos/permissive/472586361/humanmachine/control.v
data/verilator_xmls/33d228a9-730d-4009-af48-f30d3edf4202.xml
module control(	input [3:0] command,
				input CLK,
				output reg [15:0] ctrl_wrd
				);
	
	reg [2:0] count ;
	reg reset_in;

	
	parameter HLT=	16'b1000000000000000;
	parameter AI=	16'b0100000000000000;
	parameter AO=	16'b0010000000000000;
	parameter BI=	16'b0001000000000000;
	parameter MI= 	16'b0000100000000000;
	parameter RR=	16'b0000010000000000;
	parameter RW=	16'b0000001000000000;
	parameter II=	16'b0000000100000000;
	parameter IO=   16'b0000000010000000;
	parameter CI=   16'b0000000001000000;
	parameter CO=   16'b0000000000100000;
	parameter CE=   16'b0000000000010000;
	parameter ALUOPTION=	16'b0000000000001000;
	parameter ALUO=	16'b0000000000000100;
	parameter DI=	16'b0000000000000010;
	parameter FL=	16'b0000000000000001;
	

	
initial begin
    count <= 3'b111;
    reset_in <= 1'b0;
end
always @ (posedge CLK)
    begin
        count = reset_in ? 3'b000 : count+1;
        reset_in = 1'b0;
        case(count)
            3'b000: ctrl_wrd = CO|MI;
            3'b001: ctrl_wrd = RR|II|CE;
            3'b010: begin
                    case(command)
                    4'b0001: ctrl_wrd = IO|MI;
                    4'b0010: ctrl_wrd = IO|MI;
                    4'b0011: ctrl_wrd = ALUO|AI;
                    4'b0100: ctrl_wrd = ALUO|BI;
                    4'b0101: ctrl_wrd = ALUOPTION|ALUO|AI;
                    4'b0110: ctrl_wrd = ALUOPTION|ALUO|BI;
                    4'b0111: ctrl_wrd = IO|MI;
                    4'b1000: ctrl_wrd = IO|CI;
                    4'b1001: ctrl_wrd = AO|DI;
                    4'b1010: ctrl_wrd = HLT;
                    default: ctrl_wrd = 16'b0000000000000000;
                    endcase 
                    end      
            3'b011: begin
                    case(command)
                    4'b0001: ctrl_wrd = RR|AI;
                    4'b0010: ctrl_wrd = RR|BI;
                    4'b0011: ctrl_wrd = 16'b0000000000000000;
                    4'b0100: ctrl_wrd = 16'b0000000000000000;
                    4'b0101: ctrl_wrd = 16'b0000000000000000;
                    4'b0110: ctrl_wrd = 16'b0000000000000000;
                    4'b0111: ctrl_wrd = AO|RW;
                    4'b1000: ctrl_wrd = 16'b0000000000000000;
                    4'b1001: ctrl_wrd = 16'b0000000000000000;
                    4'b1010: ctrl_wrd = 16'b0000000000000000;
                    default: ctrl_wrd = 16'b0000000000000000;
                    endcase
                    reset_in = 1'b1;
                    end

            default: ctrl_wrd = 16'b0000000000000000;
        endcase                          
    end



endmodule
module control(	input [3:0] command,
				input CLK,
				output reg [15:0] ctrl_wrd
				);

	
	reg [2:0] count ;
	reg reset_in;

	
	parameter HLT=	16'b1000000000000000;
	parameter AI=	16'b0100000000000000;
	parameter AO=	16'b0010000000000000;
	parameter BI=	16'b0001000000000000;
	parameter MI= 	16'b0000100000000000;
	parameter RR=	16'b0000010000000000;
	parameter RW=	16'b0000001000000000;
	parameter II=	16'b0000000100000000;
	parameter IO=   16'b0000000010000000;
	parameter CI=   16'b0000000001000000;
	parameter CO=   16'b0000000000100000;
	parameter CE=   16'b0000000000010000;
	parameter ALUOPTION=	16'b0000000000001000;
	parameter ALUO=	16'b0000000000000100;
	parameter DI=	16'b0000000000000010;
	parameter FL=	16'b0000000000000001;
	

	
initial begin
    count <= 3'b111;
    reset_in <= 1'b0;
end
always @ (posedge CLK)
    begin
        count = reset_in ? 3'b000 : count+1;
        reset_in = 1'b0;
        case(count)
            3'b000: ctrl_wrd = CO|MI;
            3'b001: ctrl_wrd = RR|II|CE;
            3'b010: begin
                    case(command)
                    4'b0001: ctrl_wrd = IO|MI;
                    4'b0010: ctrl_wrd = IO|MI;
                    4'b0011: ctrl_wrd = ALUO|AI;
                    4'b0100: ctrl_wrd = ALUO|BI;
                    4'b0101: ctrl_wrd = ALUOPTION|ALUO|AI;
                    4'b0110: ctrl_wrd = ALUOPTION|ALUO|BI;
                    4'b0111: ctrl_wrd = IO|MI;
                    4'b1000: ctrl_wrd = IO|CI;
                    4'b1001: ctrl_wrd = AO|DI;
                    4'b1010: ctrl_wrd = HLT;
                    default: ctrl_wrd = 16'b0000000000000000;
                    endcase 
                    end      
            3'b011: begin
                    case(command)
                    4'b0001: ctrl_wrd = RR|AI;
                    4'b0010: ctrl_wrd = RR|BI;
                    4'b0011: ctrl_wrd = 16'b0000000000000000;
                    4'b0100: ctrl_wrd = 16'b0000000000000000;
                    4'b0101: ctrl_wrd = 16'b0000000000000000;
                    4'b0110: ctrl_wrd = 16'b0000000000000000;
                    4'b0111: ctrl_wrd = AO|RW;
                    4'b1000: ctrl_wrd = 16'b0000000000000000;
                    4'b1001: ctrl_wrd = 16'b0000000000000000;
                    4'b1010: ctrl_wrd = 16'b0000000000000000;
                    default: ctrl_wrd = 16'b0000000000000000;
                    endcase
                    reset_in = 1'b1;
                    end

            default: ctrl_wrd = 16'b0000000000000000;
        endcase                          
    end



endmodule