data/full_repos/permissive/515599642/Simple CPU module using Verilog/testbench.v
1: b'%Error: Cannot find file containing module: CPU\n        ... Looked in:\n             data/full_repos/permissive/515599642/Simple/CPU\n             data/full_repos/permissive/515599642/Simple/CPU.v\n             data/full_repos/permissive/515599642/Simple/CPU.sv\n             CPU\n             CPU.v\n             CPU.sv\n             obj_dir/CPU\n             obj_dir/CPU.v\n             obj_dir/CPU.sv\n%Error: Cannot find file containing module: module\n%Error: Cannot find file containing module: using\n%Error: Cannot find file containing module: Verilog,data/full_repos/permissive/515599642\n%Error: Cannot find file containing module: data/full_repos/permissive/515599642/Simple\n%Error: Cannot find file containing module: Verilog/testbench.v\n%Error: Exiting due to 6 error(s)\n'
module testbench;
reg [3:0]in_A, in_B;
reg[7:0] in_ctrl_bus;
reg in_clk;
wire [3:0]out_Q;

top dut(in_A, in_B, in_ctrl_bus, in_clk, out_Q);

initial begin
in_clk=0;
#5 in_A=4'b0000; in_B=4'b0000; in_ctrl_bus=8'b00000000;
#5 in_A=4'b1101; in_B=4'b0010; in_ctrl_bus=8'b10000000;	
#5 in_A=4'b1110; in_B=4'b0111; in_ctrl_bus=8'b01011000;
#5 in_A=4'b1001; in_B=4'b1010; in_ctrl_bus=8'b10110000;	
#5 in_A=4'b1010; in_B=4'b0100; in_ctrl_bus=8'b11010000;
#5 in_A=4'b1101; in_B=4'b0010; in_ctrl_bus=8'b10111000;	
#5 in_A=4'b1110; in_B=4'b1100; in_ctrl_bus=8'b11000110;
#5 in_A=4'b0001; in_B=4'b0010; in_ctrl_bus=8'b11100000;	
#5 in_A=4'b0110; in_B=4'b0101; in_ctrl_bus=8'b01011000;
#5 in_A=4'b1001; in_B=4'b1110; in_ctrl_bus=8'b10110000;	
#5 in_A=4'b1111; in_B=4'b1111; in_ctrl_bus=8'b11111111;
#5 $finish;
end
always begin
#5 in_clk=~in_clk;
end
endmodule
module testbench;

reg [3:0]in_A, in_B;
reg[7:0] in_ctrl_bus;
reg in_clk;
wire [3:0]out_Q;

top dut(in_A, in_B, in_ctrl_bus, in_clk, out_Q);

initial begin
in_clk=0;
#5 in_A=4'b0000; in_B=4'b0000; in_ctrl_bus=8'b00000000;
#5 in_A=4'b1101; in_B=4'b0010; in_ctrl_bus=8'b10000000;	
#5 in_A=4'b1110; in_B=4'b0111; in_ctrl_bus=8'b01011000;
#5 in_A=4'b1001; in_B=4'b1010; in_ctrl_bus=8'b10110000;	
#5 in_A=4'b1010; in_B=4'b0100; in_ctrl_bus=8'b11010000;
#5 in_A=4'b1101; in_B=4'b0010; in_ctrl_bus=8'b10111000;	
#5 in_A=4'b1110; in_B=4'b1100; in_ctrl_bus=8'b11000110;
#5 in_A=4'b0001; in_B=4'b0010; in_ctrl_bus=8'b11100000;	
#5 in_A=4'b0110; in_B=4'b0101; in_ctrl_bus=8'b01011000;
#5 in_A=4'b1001; in_B=4'b1110; in_ctrl_bus=8'b10110000;	
#5 in_A=4'b1111; in_B=4'b1111; in_ctrl_bus=8'b11111111;
#5 $finish;
end
always begin
#5 in_clk=~in_clk;
end
endmodule