data/full_repos/permissive/424312442/lab_8_vga_interface/sources_1/vga_single_source.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/424312442/lab_8_vga_interface/sources_1/vga_single_source.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/424312442/lab_8_vga_interface/sources_1/vga_single_source.v:140: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Error: data/full_repos/permissive/424312442/lab_8_vga_interface/sources_1/vga_single_source.v:157: syntax error, unexpected \'(\', expecting IDENTIFIER\npixel_clock(clk, clk25);\n            ^~~\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pixel_clock(clk, pixel_clock);

input clk;
output pixel_clock = 1;
reg pixel_clock;
reg counter = 0;
always @(posedge clk) begin
    counter <= counter + 1;
    if (counter == 0) pixel_clock = !pixel_clock;
end
endmodule
module pixel_clock(clk, pixel_clock);


input clk;
output pixel_clock = 1;
reg pixel_clock;
reg counter = 0;
always @(posedge clk) begin
    counter <= counter + 1;
    if (counter == 0) pixel_clock = !pixel_clock;
end
endmodule