data/full_repos/permissive/439514885/testbench/apb_driver.v
1: b'%Error: data/full_repos/permissive/439514885/testbench/apb_driver.v:34: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Error: data/full_repos/permissive/439514885/testbench/apb_driver.v:42: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Error: data/full_repos/permissive/439514885/testbench/apb_driver.v:57: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Error: data/full_repos/permissive/439514885/testbench/apb_driver.v:64: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Error: data/full_repos/permissive/439514885/testbench/apb_driver.v:68: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439514885/testbench/apb_driver.v:69: Unsupported: Ignoring delay on this delayed statement.\n    #1 data = prdata;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/439514885/testbench/apb_driver.v:78: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Error: Exiting due to 6 error(s), 1 warning(s)\n'
module apb_driver(

   paddr,
   pwrite,
   psel,
   penable,
   pwdata,


   clk,
   prdata
);

output [7:0]  paddr;
output        pwrite;
output        psel;
output        penable;
output [31:0] pwdata;

input         clk;
input[31:0]   prdata;

reg [7:0]   paddr;
reg         pwrite;
reg         psel;
reg         penable;
reg [31:0]  pwdata;


task write;
  input [7:0] addr;
  input [31:0] data;
  begin
    @(negedge clk);
    psel = 1'b1;
    pwrite = 1'b1;
    paddr = addr;
    pwdata = data;
    penable = 0;


    @(negedge clk);
    penable = 1;
  end
endtask







task read;
  input[7:0] addr;
  output[31:0] data;
  begin
    @(negedge clk);
    psel = 1;
    paddr = addr;
    penable = 0;
    pwrite = 0;


    @(negedge clk);
    penable = 1;


    @(posedge clk);
    #1 data = prdata;
  end
endtask




task idle();
  begin
    @(negedge clk);
    psel = 0;
    penable = 0;
    pwrite = 0;
    paddr = 0;
    pwdata = 0;
  end
endtask

endmodule
module apb_driver(

   paddr,
   pwrite,
   psel,
   penable,
   pwdata,


   clk,
   prdata
);


output [7:0]  paddr;
output        pwrite;
output        psel;
output        penable;
output [31:0] pwdata;

input         clk;
input[31:0]   prdata;

reg [7:0]   paddr;
reg         pwrite;
reg         psel;
reg         penable;
reg [31:0]  pwdata;


task write;
  input [7:0] addr;
  input [31:0] data;
  begin
    @(negedge clk);
    psel = 1'b1;
    pwrite = 1'b1;
    paddr = addr;
    pwdata = data;
    penable = 0;


    @(negedge clk);
    penable = 1;
  end
endtask







task read;
  input[7:0] addr;
  output[31:0] data;
  begin
    @(negedge clk);
    psel = 1;
    paddr = addr;
    penable = 0;
    pwrite = 0;


    @(negedge clk);
    penable = 1;


    @(posedge clk);
    #1 data = prdata;
  end
endtask




task idle();
  begin
    @(negedge clk);
    psel = 0;
    penable = 0;
    pwrite = 0;
    paddr = 0;
    pwdata = 0;
  end
endtask

endmodule