data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Finite State Machines/Fsm3s/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines/Fsm3s,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/Fsm3s/top_module.v\n%Error: Exiting due to 5 error(s)\n'
module top_module (
    input  wire clk,
    input  wire in,
    input  wire reset,
    output reg  out
);

  parameter A = 2'h0, B = 2'h1, C = 2'h2, D = 2'h3;
  reg [1:0] state, next_state;


  always @(*) begin
    case ({
      in, state
    })
      {1'b0, A} : next_state = A;
      {1'b0, B} : next_state = C;
      {1'b0, C} : next_state = A;
      {1'b1, C} : next_state = D;
      {1'b0, D} : next_state = C;
      default: next_state = B;
    endcase
  end


  always @(posedge clk) begin
    if (reset) state <= A;
    else if (clk) begin
      state <= next_state;
    end
  end


  always @(*) begin
    case (state)
      D: out = 1'b1;
      default: out = 1'b0;
    endcase
  end
endmodule
module top_module (
    input  wire clk,
    input  wire in,
    input  wire reset,
    output reg  out
);


  parameter A = 2'h0, B = 2'h1, C = 2'h2, D = 2'h3;
  reg [1:0] state, next_state;


  always @(*) begin
    case ({
      in, state
    })
      {1'b0, A} : next_state = A;
      {1'b0, B} : next_state = C;
      {1'b0, C} : next_state = A;
      {1'b1, C} : next_state = D;
      {1'b0, D} : next_state = C;
      default: next_state = B;
    endcase
  end


  always @(posedge clk) begin
    if (reset) state <= A;
    else if (clk) begin
      state <= next_state;
    end
  end


  always @(*) begin
    case (state)
      D: out = 1'b1;
      default: out = 1'b0;
    endcase
  end
endmodule