data/full_repos/permissive/521867481/uart/Uart8Transmitter.v
1: b'%Error: data/full_repos/permissive/521867481/uart/Uart8Transmitter.v:1: Cannot find include file: UartStates.vh\n`include "UartStates.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/521867481/uart,data/full_repos/permissive/521867481/UartStates.vh\n             data/full_repos/permissive/521867481/uart,data/full_repos/permissive/521867481/UartStates.vh.v\n             data/full_repos/permissive/521867481/uart,data/full_repos/permissive/521867481/UartStates.vh.sv\n             UartStates.vh\n             UartStates.vh.v\n             UartStates.vh.sv\n             obj_dir/UartStates.vh\n             obj_dir/UartStates.vh.v\n             obj_dir/UartStates.vh.sv\n%Error: data/full_repos/permissive/521867481/uart/Uart8Transmitter.v:19: Define or directive not defined: \'`RESET\'\n    reg [2:0] state  = `RESET;\n                       ^~~~~~\n%Error: data/full_repos/permissive/521867481/uart/Uart8Transmitter.v:19: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    reg [2:0] state  = `RESET;\n                             ^\n%Error: data/full_repos/permissive/521867481/uart/Uart8Transmitter.v:26: Define or directive not defined: \'`IDLE\'\n                state   <= `IDLE;\n                           ^~~~~\n%Error: data/full_repos/permissive/521867481/uart/Uart8Transmitter.v:26: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                state   <= `IDLE;\n                                ^\n%Error: data/full_repos/permissive/521867481/uart/Uart8Transmitter.v:28: Define or directive not defined: \'`IDLE\'\n            `IDLE       : begin\n            ^~~~~\n%Error: data/full_repos/permissive/521867481/uart/Uart8Transmitter.v:28: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `IDLE       : begin\n                          ^~~~~\n%Error: data/full_repos/permissive/521867481/uart/Uart8Transmitter.v:36: Define or directive not defined: \'`START_BIT\'\n                    state   <= `START_BIT;\n                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/uart/Uart8Transmitter.v:36: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                    state   <= `START_BIT;\n                                         ^\n%Error: data/full_repos/permissive/521867481/uart/Uart8Transmitter.v:39: Define or directive not defined: \'`START_BIT\'\n            `START_BIT  : begin\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/uart/Uart8Transmitter.v:39: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `START_BIT  : begin\n                          ^~~~~\n%Error: data/full_repos/permissive/521867481/uart/Uart8Transmitter.v:42: Define or directive not defined: \'`DATA_BITS\'\n                state   <= `DATA_BITS;\n                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/uart/Uart8Transmitter.v:42: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                state   <= `DATA_BITS;\n                                     ^\n%Error: data/full_repos/permissive/521867481/uart/Uart8Transmitter.v:44: Define or directive not defined: \'`DATA_BITS\'\n            `DATA_BITS  : begin  \n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/uart/Uart8Transmitter.v:44: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `DATA_BITS  : begin  \n                          ^~~~~\n%Error: data/full_repos/permissive/521867481/uart/Uart8Transmitter.v:48: Define or directive not defined: \'`STOP_BIT\'\n                    state   <= `STOP_BIT;\n                               ^~~~~~~~~\n%Error: data/full_repos/permissive/521867481/uart/Uart8Transmitter.v:48: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                    state   <= `STOP_BIT;\n                                        ^\n%Error: data/full_repos/permissive/521867481/uart/Uart8Transmitter.v:53: Define or directive not defined: \'`STOP_BIT\'\n            `STOP_BIT   : begin  \n            ^~~~~~~~~\n%Error: data/full_repos/permissive/521867481/uart/Uart8Transmitter.v:53: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `STOP_BIT   : begin  \n                          ^~~~~\n%Error: data/full_repos/permissive/521867481/uart/Uart8Transmitter.v:57: Define or directive not defined: \'`IDLE\'\n                state   <= `IDLE;\n                           ^~~~~\n%Error: data/full_repos/permissive/521867481/uart/Uart8Transmitter.v:57: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                state   <= `IDLE;\n                                ^\n%Error: Exiting due to 21 error(s)\n'
module Uart8Transmitter (
    input  wire       clk,
    input  wire       en,
    input  wire       start,
    input  wire [7:0] in,
    output reg        out,
    output reg        done,
    output reg        busy
);
    reg [2:0] state  = `RESET;
    reg [7:0] data   = 8'b0;
    reg [2:0] bitIdx = 3'b0;

    always @(posedge clk) begin
        case (state)
            default     : begin
                state   <= `IDLE;
            end
            `IDLE       : begin
                out     <= 1'b1;
                done    <= 1'b0;
                busy    <= 1'b0;
                bitIdx  <= 3'b0;
                data    <= 8'b0;
                if (start & en) begin
                    data    <= in;
                    state   <= `START_BIT;
                end
            end
            `START_BIT  : begin
                out     <= 1'b0;
                busy    <= 1'b1;
                state   <= `DATA_BITS;
            end
            `DATA_BITS  : begin
                out     <= data[bitIdx];
                if (&bitIdx) begin
                    bitIdx  <= 3'b0;
                    state   <= `STOP_BIT;
                end else begin
                    bitIdx  <= bitIdx + 1'b1;
                end
            end
            `STOP_BIT   : begin
                out     <= 1'b1;
                done    <= 1'b1;
                data    <= 8'b0;
                state   <= `IDLE;
            end
        endcase
    end

endmodule
module Uart8Transmitter (
    input  wire       clk,
    input  wire       en,
    input  wire       start,
    input  wire [7:0] in,
    output reg        out,
    output reg        done,
    output reg        busy
);

    reg [2:0] state  = `RESET;
    reg [7:0] data   = 8'b0;
    reg [2:0] bitIdx = 3'b0;

    always @(posedge clk) begin
        case (state)
            default     : begin
                state   <= `IDLE;
            end
            `IDLE       : begin
                out     <= 1'b1;
                done    <= 1'b0;
                busy    <= 1'b0;
                bitIdx  <= 3'b0;
                data    <= 8'b0;
                if (start & en) begin
                    data    <= in;
                    state   <= `START_BIT;
                end
            end
            `START_BIT  : begin
                out     <= 1'b0;
                busy    <= 1'b1;
                state   <= `DATA_BITS;
            end
            `DATA_BITS  : begin
                out     <= data[bitIdx];
                if (&bitIdx) begin
                    bitIdx  <= 3'b0;
                    state   <= `STOP_BIT;
                end else begin
                    bitIdx  <= bitIdx + 1'b1;
                end
            end
            `STOP_BIT   : begin
                out     <= 1'b1;
                done    <= 1'b1;
                data    <= 8'b0;
                state   <= `IDLE;
            end
        endcase
    end

endmodule