data/full_repos/permissive/497604366/cpu/cpu.srcs/sources_1/new/instruction_memory.v
1: b"%Error: data/full_repos/permissive/497604366/cpu/cpu.srcs/sources_1/new/instruction_memory.v:25: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n    output reg [31:0] do\n                      ^~\n%Error: data/full_repos/permissive/497604366/cpu/cpu.srcs/sources_1/new/instruction_memory.v:38: syntax error, unexpected <=\n        do <= memory[pc[7:2]];\n           ^~\n%Error: Cannot continue\n"
module instruction_memory(
    input [31:0] pc,
    output reg [31:0] do
    );
    reg [31:0] memory[0:63];
    
    initial begin
        memory[25] <= {6'b100011,5'b00001,5'b00010,5'b00011,5'b00000,6'b100000};
        memory[26] <= {6'b100011,5'b01001,5'b00011,5'b00100,5'b00000,6'b100010};
        memory[27] <= {6'b100011,5'b00011,5'b01001,5'b00101,5'b00000,6'b100101};
        memory[28] <= {6'b100011,5'b00011,5'b01001,5'b00110,5'b00000,6'b100110};
        memory[29] <= {6'b000000,5'b00011,5'b01001,5'b00111,5'b00000,6'b100100};
    end
    
    always @(*) begin
        do <= memory[pc[7:2]];
    end
endmodule
module instruction_memory(
    input [31:0] pc,
    output reg [31:0] do
    );

    reg [31:0] memory[0:63];
    
    initial begin
        memory[25] <= {6'b100011,5'b00001,5'b00010,5'b00011,5'b00000,6'b100000};
        memory[26] <= {6'b100011,5'b01001,5'b00011,5'b00100,5'b00000,6'b100010};
        memory[27] <= {6'b100011,5'b00011,5'b01001,5'b00101,5'b00000,6'b100101};
        memory[28] <= {6'b100011,5'b00011,5'b01001,5'b00110,5'b00000,6'b100110};
        memory[29] <= {6'b000000,5'b00011,5'b01001,5'b00111,5'b00000,6'b100100};
    end
    
    always @(*) begin
        do <= memory[pc[7:2]];
    end
endmodule