data/full_repos/permissive/450205124/Assignment3/Q1-sequence-detector/A3Q1_sequence_detector_full.v
1: b'%Error: data/full_repos/permissive/450205124/Assignment3/Q1-sequence-detector/A3Q1_sequence_detector_full.v:1: Cannot find include file: A3Q1_sequence_detector_unit.v\n`include "A3Q1_sequence_detector_unit.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/450205124/Assignment3/Q1-sequence-detector,data/full_repos/permissive/450205124/A3Q1_sequence_detector_unit.v\n             data/full_repos/permissive/450205124/Assignment3/Q1-sequence-detector,data/full_repos/permissive/450205124/A3Q1_sequence_detector_unit.v.v\n             data/full_repos/permissive/450205124/Assignment3/Q1-sequence-detector,data/full_repos/permissive/450205124/A3Q1_sequence_detector_unit.v.sv\n             A3Q1_sequence_detector_unit.v\n             A3Q1_sequence_detector_unit.v.v\n             A3Q1_sequence_detector_unit.v.sv\n             obj_dir/A3Q1_sequence_detector_unit.v\n             obj_dir/A3Q1_sequence_detector_unit.v.v\n             obj_dir/A3Q1_sequence_detector_unit.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment3/Q1-sequence-detector/A3Q1_sequence_detector_full.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #1\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module sequence_detector_full(out,seq,reset,clk);
	output reg [7:0] out=8'd0;
	input [7:0] seq;
	input reset;
	input clk;
	
	reg i=0;
	wire o;
	integer count=7;

	sequence_detector_unit sd (o,i, clk,reset);
	always @(negedge clk) begin
		i=seq[count];
		#1
		out[count]=o;
		count=count-1;
		if(count==-1) begin
		  count=7;
		end
	end
endmodule
module sequence_detector_full(out,seq,reset,clk);

	output reg [7:0] out=8'd0;
	input [7:0] seq;
	input reset;
	input clk;
	
	reg i=0;
	wire o;
	integer count=7;

	sequence_detector_unit sd (o,i, clk,reset);
	always @(negedge clk) begin
		i=seq[count];
		#1
		out[count]=o;
		count=count-1;
		if(count==-1) begin
		  count=7;
		end
	end
endmodule