data/full_repos/permissive/471089853/src/teras.v
1: b"%Error: data/full_repos/permissive/471089853/src/teras.v:83: Cannot find file containing module: 'SystolicArray'\nSystolicArray sa_inst (\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/471089853/src,data/full_repos/permissive/471089853/SystolicArray\n             data/full_repos/permissive/471089853/src,data/full_repos/permissive/471089853/SystolicArray.v\n             data/full_repos/permissive/471089853/src,data/full_repos/permissive/471089853/SystolicArray.sv\n             SystolicArray\n             SystolicArray.v\n             SystolicArray.sv\n             obj_dir/SystolicArray\n             obj_dir/SystolicArray.v\n             obj_dir/SystolicArray.sv\n%Error: data/full_repos/permissive/471089853/src/teras.v:122: Cannot find file containing module: 'fifo'\nfifo #\n^~~~\n%Error: Exiting due to 2 error(s)\n"
module teras #
(
    parameter integer DATA_WIDTH = 32
)
(

    input  wire clk,
    input  wire rst_n,




    output wire rtr_o,
    input  wire rts_i,

    input wire [DATA_WIDTH-1:0] data_i,




    input  wire rtr_i,
    output wire rts_o,

    output wire [DATA_WIDTH-1:0] data_o
);


localparam integer ARITH_IN_WIDTH = 8;
localparam integer ARITH_OUT_WIDTH = 8;
localparam integer N = 3;
localparam integer M = 3;

localparam integer S3FDP_PP_DEPTH = 2;
localparam integer L2A_PP_DEPTH = 7;
localparam integer FIFO_DEPTH = 16;
localparam integer OUT_WIDTH = M*ARITH_OUT_WIDTH;
localparam integer FIFO_WIDTH = OUT_WIDTH;




wire [DATA_WIDTH-1:0] sa_data_i;
wire [OUT_WIDTH-1:0] sa_data_o;
wire sa_eob;
wire sa_eob_q;
wire sa_valid_o;
wire sa_sob;


wire [OUT_WIDTH-1:0] fifo_data_o;
wire fifo_valid_o;






assign rtr_o = rtr_i;
assign sa_data_i = (rts_i & rtr_o) ? data_i : {DATA_WIDTH{1'b0}};
assign sa_eob = sa_data_i[DATA_WIDTH-1];
assign sa_sob = sa_data_i[DATA_WIDTH-2];






SystolicArray sa_inst (


    .clk     ( clk                               ),
    .rst     ( ~rst_n                            ),


    .rowsA   ( sa_data_i[(N*ARITH_IN_WIDTH)-1:0] ), 
    .colsB   ( sa_data_i[(N*ARITH_IN_WIDTH)-1:0] ),
    .SOB     ( sa_sob                            ),
    .EOB     ( sa_eob                            ),
    .colsC   ( sa_data_o                         ),
    .EOB_Q_o ( sa_eob_q                          )

);





localparam integer size = N+2+S3FDP_PP_DEPTH+L2A_PP_DEPTH-1;
reg [size-1:0] shift_register;
always @(posedge clk or negedge rst_n) begin
	if ( ~rst_n ) begin
		shift_register <= 0;
	end
	else begin
		shift_register <= {shift_register[size-2:0],sa_eob_q};
	end
end
assign sa_valid_o = |shift_register[(size-2) -: N];








fifo #
(
    .C_WIDTH ( FIFO_WIDTH ),
    .C_DEPTH ( FIFO_DEPTH ),
    .C_DELAY ( 2 )
) fifo_inst (
     .CLK      ( clk                  ),
     .RST      ( ~rst_n               ),

     .WR_DATA  ( sa_data_o            ),
     .WR_VALID ( sa_valid_o           ),
     .WR_READY ( ),

     .RD_DATA  ( fifo_data_o          ),
     .RD_READY ( rtr_i & fifo_valid_o ),
     .RD_VALID ( fifo_valid_o         )
);






assign rts_o  = fifo_valid_o;
assign data_o = {{DATA_WIDTH-OUT_WIDTH{1'b0}},fifo_data_o};

endmodule
module teras #
(
    parameter integer DATA_WIDTH = 32
)
(

    input  wire clk,
    input  wire rst_n,




    output wire rtr_o,
    input  wire rts_i,

    input wire [DATA_WIDTH-1:0] data_i,




    input  wire rtr_i,
    output wire rts_o,

    output wire [DATA_WIDTH-1:0] data_o
);



localparam integer ARITH_IN_WIDTH = 8;
localparam integer ARITH_OUT_WIDTH = 8;
localparam integer N = 3;
localparam integer M = 3;

localparam integer S3FDP_PP_DEPTH = 2;
localparam integer L2A_PP_DEPTH = 7;
localparam integer FIFO_DEPTH = 16;
localparam integer OUT_WIDTH = M*ARITH_OUT_WIDTH;
localparam integer FIFO_WIDTH = OUT_WIDTH;




wire [DATA_WIDTH-1:0] sa_data_i;
wire [OUT_WIDTH-1:0] sa_data_o;
wire sa_eob;
wire sa_eob_q;
wire sa_valid_o;
wire sa_sob;


wire [OUT_WIDTH-1:0] fifo_data_o;
wire fifo_valid_o;






assign rtr_o = rtr_i;
assign sa_data_i = (rts_i & rtr_o) ? data_i : {DATA_WIDTH{1'b0}};
assign sa_eob = sa_data_i[DATA_WIDTH-1];
assign sa_sob = sa_data_i[DATA_WIDTH-2];






SystolicArray sa_inst (


    .clk     ( clk                               ),
    .rst     ( ~rst_n                            ),


    .rowsA   ( sa_data_i[(N*ARITH_IN_WIDTH)-1:0] ), 
    .colsB   ( sa_data_i[(N*ARITH_IN_WIDTH)-1:0] ),
    .SOB     ( sa_sob                            ),
    .EOB     ( sa_eob                            ),
    .colsC   ( sa_data_o                         ),
    .EOB_Q_o ( sa_eob_q                          )

);





localparam integer size = N+2+S3FDP_PP_DEPTH+L2A_PP_DEPTH-1;
reg [size-1:0] shift_register;
always @(posedge clk or negedge rst_n) begin
	if ( ~rst_n ) begin
		shift_register <= 0;
	end
	else begin
		shift_register <= {shift_register[size-2:0],sa_eob_q};
	end
end
assign sa_valid_o = |shift_register[(size-2) -: N];








fifo #
(
    .C_WIDTH ( FIFO_WIDTH ),
    .C_DEPTH ( FIFO_DEPTH ),
    .C_DELAY ( 2 )
) fifo_inst (
     .CLK      ( clk                  ),
     .RST      ( ~rst_n               ),

     .WR_DATA  ( sa_data_o            ),
     .WR_VALID ( sa_valid_o           ),
     .WR_READY ( ),

     .RD_DATA  ( fifo_data_o          ),
     .RD_READY ( rtr_i & fifo_valid_o ),
     .RD_VALID ( fifo_valid_o         )
);






assign rts_o  = fifo_valid_o;
assign data_o = {{DATA_WIDTH-OUT_WIDTH{1'b0}},fifo_data_o};

endmodule