data/full_repos/permissive/423547971/10 Verilog Projects Book/Section_10/traffic_controller_TB.v
1: b'%Error: Cannot find file containing module: Verilog\n        ... Looked in:\n             data/full_repos/permissive/423547971/10/Verilog\n             data/full_repos/permissive/423547971/10/Verilog.v\n             data/full_repos/permissive/423547971/10/Verilog.sv\n             Verilog\n             Verilog.v\n             Verilog.sv\n             obj_dir/Verilog\n             obj_dir/Verilog.v\n             obj_dir/Verilog.sv\n%Error: Cannot find file containing module: Projects\n%Error: Cannot find file containing module: Book/Section_10,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/10\n%Error: Cannot find file containing module: Book/Section_10/traffic_controller_TB.v\n%Error: Exiting due to 5 error(s)\n'
module traffic_controller_TB;
	reg clock;
	reg reset;
	reg sensor;
	wire [2:0] major;
	wire [2:0] minor;
	
	traffic_controller DUT(.clock(clock), .reset(reset), 
						   .sensor(sensor), 
						   .major(major), .minor(minor));
						   
	always #2 clock = ~clock;
	
	initial begin
		$dumpfile("traffic_controller_TB.vcd");
		$dumpvars(0, traffic_controller_TB);
	end
	
	initial begin
		clock = 0;
		reset = 0;
		sensor = 0;
		
		#5 reset = 1;
		
		#4 sensor = 1;
		#20 sensor = 0;
		
		#50 $finish;
	end
	
endmodule
module traffic_controller_TB;

	reg clock;
	reg reset;
	reg sensor;
	wire [2:0] major;
	wire [2:0] minor;
	
	traffic_controller DUT(.clock(clock), .reset(reset), 
						   .sensor(sensor), 
						   .major(major), .minor(minor));
						   
	always #2 clock = ~clock;
	
	initial begin
		$dumpfile("traffic_controller_TB.vcd");
		$dumpvars(0, traffic_controller_TB);
	end
	
	initial begin
		clock = 0;
		reset = 0;
		sensor = 0;
		
		#5 reset = 1;
		
		#4 sensor = 1;
		#20 sensor = 0;
		
		#50 $finish;
	end
	
endmodule