data/full_repos/permissive/448192472/V11_Mux4to1_Verilog_script/test_mux4to1.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/448192472/V11_Mux4to1_Verilog_script/test_mux4to1.v:28: Unsupported: Ignoring delay on this delayed statement.\n#100 A = 4\'b0001; s0 = 0; s1 = 0;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/448192472/V11_Mux4to1_Verilog_script/test_mux4to1.v:29: Unsupported: Ignoring delay on this delayed statement.\n#100 A = 4\'b0010; s0 = 1; s1 = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/448192472/V11_Mux4to1_Verilog_script/test_mux4to1.v:30: Unsupported: Ignoring delay on this delayed statement.\n#100 A = 4\'b0100; s0 = 0; s1 = 1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/448192472/V11_Mux4to1_Verilog_script/test_mux4to1.v:31: Unsupported: Ignoring delay on this delayed statement.\n#100 A = 4\'b1000; s0 = 1; s1 = 1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/448192472/V11_Mux4to1_Verilog_script/test_mux4to1.v:32: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Error: data/full_repos/permissive/448192472/V11_Mux4to1_Verilog_script/test_mux4to1.v:17: Cannot find file containing module: \'mux4to1\'\n mux4to1 uut (\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/448192472/V11_Mux4to1_Verilog_script,data/full_repos/permissive/448192472/mux4to1\n             data/full_repos/permissive/448192472/V11_Mux4to1_Verilog_script,data/full_repos/permissive/448192472/mux4to1.v\n             data/full_repos/permissive/448192472/V11_Mux4to1_Verilog_script,data/full_repos/permissive/448192472/mux4to1.sv\n             mux4to1\n             mux4to1.v\n             mux4to1.sv\n             obj_dir/mux4to1\n             obj_dir/mux4to1.v\n             obj_dir/mux4to1.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_mux4to1;


	reg [3:0] A;
	reg s0;
	reg s1;


	wire Q;


	mux4to1 uut (
		.A(A), 
		.s0(s0), 
		.s1(s1), 
		.Q(Q)
	);

	initial 
	begin

	A = 4'b0000; s0 = 0; s1 = 0;
#100	A = 4'b0001; s0 = 0; s1 = 0;
#100	A = 4'b0010; s0 = 1; s1 = 0;
#100	A = 4'b0100; s0 = 0; s1 = 1;
#100	A = 4'b1000; s0 = 1; s1 = 1;
#100;
	$finish;

	end
      
endmodule
module test_mux4to1;



	reg [3:0] A;
	reg s0;
	reg s1;


	wire Q;


	mux4to1 uut (
		.A(A), 
		.s0(s0), 
		.s1(s1), 
		.Q(Q)
	);

	initial 
	begin

	A = 4'b0000; s0 = 0; s1 = 0;
#100	A = 4'b0001; s0 = 0; s1 = 0;
#100	A = 4'b0010; s0 = 1; s1 = 0;
#100	A = 4'b0100; s0 = 0; s1 = 1;
#100	A = 4'b1000; s0 = 1; s1 = 1;
#100;
	$finish;

	end
      
endmodule