data/full_repos/permissive/462122681/ALU.v
1: b'%Warning-WIDTH: data/full_repos/permissive/462122681/ALU.v:17: Operator ADD expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                             : ... In instance ALU\n           ALU_Result = A + B ; \n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/462122681/ALU.v:17: Operator ADD expects 64 bits on the RHS, but RHS\'s VARREF \'B\' generates 32 bits.\n                                                             : ... In instance ALU\n           ALU_Result = A + B ; \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/462122681/ALU.v:19: Operator SUB expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                             : ... In instance ALU\n           ALU_Result = A - B ;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/462122681/ALU.v:19: Operator SUB expects 64 bits on the RHS, but RHS\'s VARREF \'B\' generates 32 bits.\n                                                             : ... In instance ALU\n           ALU_Result = A - B ;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/462122681/ALU.v:26: Operator SHIFTL expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                             : ... In instance ALU\n           ALU_Result = A << B;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/462122681/ALU.v:28: Operator SHIFTR expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                             : ... In instance ALU\n           ALU_Result = A >> B;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/462122681/ALU.v:31: Operator SHIFTL expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                             : ... In instance ALU\n     ALU_Result = (A << B)|(A >> (32 - B));\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/462122681/ALU.v:31: Operator SHIFTR expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                             : ... In instance ALU\n     ALU_Result = (A << B)|(A >> (32 - B));\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/462122681/ALU.v:33: Operator SHIFTL expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                             : ... In instance ALU\n     ALU_Result = (A << B%32)|(A >> (32 - B%32));\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/462122681/ALU.v:33: Operator SHIFTR expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                             : ... In instance ALU\n     ALU_Result = (A << B%32)|(A >> (32 - B%32));\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/462122681/ALU.v:37: Operator SHIFTR expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                             : ... In instance ALU\n     ALU_Result = (A >> B)|(A << (32 - B));\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/462122681/ALU.v:37: Operator SHIFTL expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                             : ... In instance ALU\n     ALU_Result = (A >> B)|(A << (32 - B));\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/462122681/ALU.v:39: Operator SHIFTR expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                             : ... In instance ALU\n     ALU_Result = (A >> B%32)|(A << (32 - B%32));\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/462122681/ALU.v:39: Operator SHIFTL expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                             : ... In instance ALU\n     ALU_Result = (A >> B%32)|(A << (32 - B%32));\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/462122681/ALU.v:42: Operator AND expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                             : ... In instance ALU\n           ALU_Result = A & B;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/462122681/ALU.v:42: Operator AND expects 64 bits on the RHS, but RHS\'s VARREF \'B\' generates 32 bits.\n                                                             : ... In instance ALU\n           ALU_Result = A & B;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/462122681/ALU.v:44: Operator OR expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                             : ... In instance ALU\n           ALU_Result = A | B;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/462122681/ALU.v:44: Operator OR expects 64 bits on the RHS, but RHS\'s VARREF \'B\' generates 32 bits.\n                                                             : ... In instance ALU\n           ALU_Result = A | B;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/462122681/ALU.v:46: Operator NOT expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                             : ... In instance ALU\n           ALU_Result = ~A;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/462122681/ALU.v:48: Operator NOT expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                             : ... In instance ALU\n           ALU_Result = ~A + 1;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/462122681/ALU.v:50: Operator ADD expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                             : ... In instance ALU\n           ALU_Result = A + B;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/462122681/ALU.v:50: Operator ADD expects 64 bits on the RHS, but RHS\'s VARREF \'B\' generates 32 bits.\n                                                             : ... In instance ALU\n           ALU_Result = A + B;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/462122681/ALU.v:52: Operator AND expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                             : ... In instance ALU\n           ALU_Result = A & B;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/462122681/ALU.v:52: Operator AND expects 64 bits on the RHS, but RHS\'s VARREF \'B\' generates 32 bits.\n                                                             : ... In instance ALU\n           ALU_Result = A & B;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/462122681/ALU.v:54: Operator OR expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                             : ... In instance ALU\n           ALU_Result = A | B;  \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/462122681/ALU.v:54: Operator OR expects 64 bits on the RHS, but RHS\'s VARREF \'B\' generates 32 bits.\n                                                             : ... In instance ALU\n           ALU_Result = A | B;  \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/462122681/ALU.v:55: Operator ADD expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                             : ... In instance ALU\n          default: ALU_Result = A + B ; \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/462122681/ALU.v:55: Operator ADD expects 64 bits on the RHS, but RHS\'s VARREF \'B\' generates 32 bits.\n                                                             : ... In instance ALU\n          default: ALU_Result = A + B ; \n                                  ^\n%Error: data/full_repos/permissive/462122681/ALU.v:60: Cannot find file containing module: \'div\'\ndiv DIV(. A(A), .B(B), .out(div_out));\n^~~\n        ... Looked in:\n             data/full_repos/permissive/462122681,data/full_repos/permissive/462122681/div\n             data/full_repos/permissive/462122681,data/full_repos/permissive/462122681/div.v\n             data/full_repos/permissive/462122681,data/full_repos/permissive/462122681/div.sv\n             div\n             div.v\n             div.sv\n             obj_dir/div\n             obj_dir/div.v\n             obj_dir/div.sv\n%Error: data/full_repos/permissive/462122681/ALU.v:61: Cannot find file containing module: \'mul\'\nmul MUL(. A(A), .B(B), .mul_out(mul_out));\n^~~\n%Error: Exiting due to 2 error(s), 28 warning(s)\n'
module ALU(
	input wire clk,
	input wire clr,
	input wire[31:0] A,B,
	input wire[4:0] ALU_Sel,
	output reg[63:0] ALU_Result
	
);
	wire [63:0] div_out;
	wire [63:0] mul_out;
	
    always @(*)
    begin
        case(ALU_Sel)
        5'b00011:
           ALU_Result = A + B ; 
        5'b00100:
           ALU_Result = A - B ;
        5'b01110:
           ALU_Result = mul_out[63:0];
        5'b01111: begin
			  ALU_Result = div_out[63:0];
			  end
        5'b00110:
           ALU_Result = A << B;
        5'b00101:
           ALU_Result = A >> B;
        5'b01000: begin
			  if (B < 32) begin
					ALU_Result = (A << B)|(A >> (32 - B));
			  end else 
					ALU_Result = (A << B%32)|(A >> (32 - B%32));
			  end
        5'b00111: begin
			  if (B < 32) begin
					ALU_Result = (A >> B)|(A << (32 - B));
			  end else
					ALU_Result = (A >> B%32)|(A << (32 - B%32));
				end
        5'b01001:
           ALU_Result = A & B;
        5'b01010:
           ALU_Result = A | B;
        5'b10001:
           ALU_Result = ~A;
        5'b10000:
           ALU_Result = ~A + 1;
		  5'b01011:
           ALU_Result = A + B;
		  5'b01100:
           ALU_Result = A & B;
		  5'b01101:
           ALU_Result = A | B;  
          default: ALU_Result = A + B ; 
        endcase
    end
	 
	 
div DIV(. A(A), .B(B), .out(div_out));
mul MUL(. A(A), .B(B), .mul_out(mul_out));
endmodule
module ALU(
	input wire clk,
	input wire clr,
	input wire[31:0] A,B,
	input wire[4:0] ALU_Sel,
	output reg[63:0] ALU_Result
	
);

	wire [63:0] div_out;
	wire [63:0] mul_out;
	
    always @(*)
    begin
        case(ALU_Sel)
        5'b00011:
           ALU_Result = A + B ; 
        5'b00100:
           ALU_Result = A - B ;
        5'b01110:
           ALU_Result = mul_out[63:0];
        5'b01111: begin
			  ALU_Result = div_out[63:0];
			  end
        5'b00110:
           ALU_Result = A << B;
        5'b00101:
           ALU_Result = A >> B;
        5'b01000: begin
			  if (B < 32) begin
					ALU_Result = (A << B)|(A >> (32 - B));
			  end else 
					ALU_Result = (A << B%32)|(A >> (32 - B%32));
			  end
        5'b00111: begin
			  if (B < 32) begin
					ALU_Result = (A >> B)|(A << (32 - B));
			  end else
					ALU_Result = (A >> B%32)|(A << (32 - B%32));
				end
        5'b01001:
           ALU_Result = A & B;
        5'b01010:
           ALU_Result = A | B;
        5'b10001:
           ALU_Result = ~A;
        5'b10000:
           ALU_Result = ~A + 1;
		  5'b01011:
           ALU_Result = A + B;
		  5'b01100:
           ALU_Result = A & B;
		  5'b01101:
           ALU_Result = A | B;  
          default: ALU_Result = A + B ; 
        endcase
    end
	 
	 
div DIV(. A(A), .B(B), .out(div_out));
mul MUL(. A(A), .B(B), .mul_out(mul_out));
endmodule