data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_ddr_rptr_vddcom.v
data/verilator_xmls/53933f1a-44cf-4c93-bb8f-6959f398fa45.xml
module bw_io_ddr_rptr_vddcom(vdd18,vdd_com);
input vdd18;
output vdd_com;

endmodule
module bw_io_ddr_rptr_vddcom(vdd18,vdd_com);

input vdd18;
output vdd_com;

endmodule