data/full_repos/permissive/500128826/HDLBits/CS450/counter_2bc/top_module_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/500128826/HDLBits/CS450/counter_2bc/top_module_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #5 clk = clk + 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/500128826/HDLBits/CS450/counter_2bc/top_module_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #61 areset = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/500128826/HDLBits/CS450/counter_2bc/top_module_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #63 areset = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/500128826/HDLBits/CS450/counter_2bc/top_module_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #50 train_valid = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/500128826/HDLBits/CS450/counter_2bc/top_module_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #5 train_taken = $random;\n    ^\n%Error: data/full_repos/permissive/500128826/HDLBits/CS450/counter_2bc/top_module_tb.v:45: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("top_module_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/500128826/HDLBits/CS450/counter_2bc/top_module_tb.v:46: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, top_module_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/500128826/HDLBits/CS450/counter_2bc/top_module_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #(ITERATIONS) $display("Done simulating.");\n    ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_module_tb ();
  reg clk = 1'd1;
  reg areset = 1'd0;
  reg train_valid = 1'd0;
  reg train_taken = 1'd0;
  wire [1:0] state;

  localparam ITERATIONS = 10000;

  always begin
    #5 clk = clk + 1;
  end

  initial begin
    #61 areset = 1'b1;
    #63 areset = 1'b0;
  end

  initial begin
    #50 train_valid = 1'b1;
  end

  always begin
    #5 train_taken = $random;
  end

  top_module uut (
      .clk(clk),
      .areset(areset),
      .train_valid(train_valid),
      .train_taken(train_taken),
      .state(state)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule
module top_module_tb ();

  reg clk = 1'd1;
  reg areset = 1'd0;
  reg train_valid = 1'd0;
  reg train_taken = 1'd0;
  wire [1:0] state;

  localparam ITERATIONS = 10000;

  always begin
    #5 clk = clk + 1;
  end

  initial begin
    #61 areset = 1'b1;
    #63 areset = 1'b0;
  end

  initial begin
    #50 train_valid = 1'b1;
  end

  always begin
    #5 train_taken = $random;
  end

  top_module uut (
      .clk(clk),
      .areset(areset),
      .train_valid(train_valid),
      .train_taken(train_taken),
      .state(state)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule