data/full_repos/permissive/481307378/source_files/FullAdder/fa_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/FullAdder/fa_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/FullAdder/fa_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/FullAdder/fa_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/FullAdder/fa_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/FullAdder/fa_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/FullAdder/fa_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/FullAdder/fa_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/FullAdder/fa_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Error: data/full_repos/permissive/481307378/source_files/FullAdder/fa_tb.v:27: Cannot find file containing module: \'fa\'\nfa dut(.a(t_a), .b(t_b), .c_in(t_cin), .s(t_sum), .c_out(t_cout));\n^~\n        ... Looked in:\n             data/full_repos/permissive/481307378/source_files/FullAdder,data/full_repos/permissive/481307378/fa\n             data/full_repos/permissive/481307378/source_files/FullAdder,data/full_repos/permissive/481307378/fa.v\n             data/full_repos/permissive/481307378/source_files/FullAdder,data/full_repos/permissive/481307378/fa.sv\n             fa\n             fa.v\n             fa.sv\n             obj_dir/fa\n             obj_dir/fa.v\n             obj_dir/fa.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fa_tb();
reg t_a, t_b, t_cin;
wire t_sum, t_cout;

fa dut(.a(t_a), .b(t_b), .c_in(t_cin), .s(t_sum), .c_out(t_cout));
initial
begin
    t_a = 0; t_b = 0; t_cin = 0;
    #10
    t_a = 0; t_b = 0; t_cin = 1;
    #10
    t_a = 0; t_b = 1; t_cin = 0;
    #10
    t_a = 0; t_b = 1; t_cin = 1;
    #10

    t_a = 1; t_b = 0; t_cin = 0;
    #10
    t_a = 1; t_b = 0; t_cin = 1;
    #10
    t_a = 1; t_b = 1; t_cin = 0;
    #10
    t_a = 1; t_b = 1; t_cin = 1;
    #10
    $stop;
end
endmodule
module fa_tb();

reg t_a, t_b, t_cin;
wire t_sum, t_cout;

fa dut(.a(t_a), .b(t_b), .c_in(t_cin), .s(t_sum), .c_out(t_cout));
initial
begin
    t_a = 0; t_b = 0; t_cin = 0;
    #10
    t_a = 0; t_b = 0; t_cin = 1;
    #10
    t_a = 0; t_b = 1; t_cin = 0;
    #10
    t_a = 0; t_b = 1; t_cin = 1;
    #10

    t_a = 1; t_b = 0; t_cin = 0;
    #10
    t_a = 1; t_b = 0; t_cin = 1;
    #10
    t_a = 1; t_b = 1; t_cin = 0;
    #10
    t_a = 1; t_b = 1; t_cin = 1;
    #10
    $stop;
end
endmodule