data/full_repos/permissive/493019833/test/testcase/firrtl/IntervalChainedAddTester/reference/IntervalChainedAddTester.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/IntervalChainedAddTester/reference/IntervalChainedAddTester.v:252: Operator COND expects 7 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 3 bits.\n                                                                                                                                           : ... In instance IntervalChainedAddTester.u_pad_25\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/IntervalChainedAddTester/reference/IntervalChainedAddTester.v:216: Operator COND expects 3 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 2 bits.\n                                                                                                                                           : ... In instance IntervalChainedAddTester.s_pad_5\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/IntervalChainedAddTester/reference/IntervalChainedAddTester.v:216: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 2 bits.\n                                                                                                                                           : ... In instance IntervalChainedAddTester.s_pad_8\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/IntervalChainedAddTester/reference/IntervalChainedAddTester.v:216: Operator COND expects 5 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 2 bits.\n                                                                                                                                           : ... In instance IntervalChainedAddTester.s_pad_11\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/IntervalChainedAddTester/reference/IntervalChainedAddTester.v:216: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 2 bits.\n                                                                                                                                           : ... In instance IntervalChainedAddTester.s_pad_14\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/IntervalChainedAddTester/reference/IntervalChainedAddTester.v:216: Operator COND expects 7 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 2 bits.\n                                                                                                                                           : ... In instance IntervalChainedAddTester.s_pad_17\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/IntervalChainedAddTester/reference/IntervalChainedAddTester.v:216: Operator COND expects 5 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 4 bits.\n                                                                                                                                           : ... In instance IntervalChainedAddTester.s_pad_20\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Error: Exiting due to 7 warning(s)\n'
module ASSINT(y, in);
    parameter width = 4;
    output [width-1:0] y;
    input [width-1:0] in;
    assign y = $signed(in);
endmodule
module ASSINT(y, in);

    parameter width = 4;
    output [width-1:0] y;
    input [width-1:0] in;
    assign y = $signed(in);
endmodule