data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ImmExt_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ImmExt_TB.v:15: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ImmExt_TB.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ImmExt_TB.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ImmExt_TB.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ImmExt_TB.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ImmExt_TB.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ImmExt_TB.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ImmExt_TB.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ImmExt_TB.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ImmExt_TB.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ImmExt_TB.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ImmExt_TB.v:12: Cannot find file containing module: \'ImmExt\'\n    ImmExt DUT(.opcode(opcode), .instr(instr), .ext_imm(ext_imm));\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new,data/full_repos/permissive/433174928/ImmExt\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new,data/full_repos/permissive/433174928/ImmExt.v\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new,data/full_repos/permissive/433174928/ImmExt.sv\n             ImmExt\n             ImmExt.v\n             ImmExt.sv\n             obj_dir/ImmExt\n             obj_dir/ImmExt.v\n             obj_dir/ImmExt.sv\n%Error: Exiting due to 1 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ImmExt_TB(

    );

    reg [2:0] opcode;
    reg [31:0] instr;
    wire [31:0] ext_imm;
    
    ImmExt DUT(.opcode(opcode), .instr(instr), .ext_imm(ext_imm));

    initial begin
        #5;
        
        instr <= 32'hffdff0ef;
        opcode <=3'd0;
        #10;
        
        if(ext_imm!=32'hfffffffc) $fatal("Expected output not received");
        #10;

        instr <= 32'h02830283;
        opcode <=3'd1;
        #10;

        if(ext_imm!=32'h00000028) $fatal("Expected output not received");
        #10;

        instr <= 32'hfe9246e3;
        opcode <=3'd2;
        #10;
        
        if(ext_imm!=32'hffffffec) $fatal("Expected output not received");
        #10;

        instr <= 32'h00129023;
        opcode <=3'd3;
        #10;
        
        if(ext_imm!=32'h00000000) $fatal("Expected output not received");
        #10;

        instr <= 32'h00001117;
        opcode <= 3'd4;
        #10;
        
        if(ext_imm!=32'h00001000) $fatal("Expected output not received");
        #10;

        $display("All test cases passed");
        $finish;
    end
endmodule
module ImmExt_TB(

    );


    reg [2:0] opcode;
    reg [31:0] instr;
    wire [31:0] ext_imm;
    
    ImmExt DUT(.opcode(opcode), .instr(instr), .ext_imm(ext_imm));

    initial begin
        #5;
        
        instr <= 32'hffdff0ef;
        opcode <=3'd0;
        #10;
        
        if(ext_imm!=32'hfffffffc) $fatal("Expected output not received");
        #10;

        instr <= 32'h02830283;
        opcode <=3'd1;
        #10;

        if(ext_imm!=32'h00000028) $fatal("Expected output not received");
        #10;

        instr <= 32'hfe9246e3;
        opcode <=3'd2;
        #10;
        
        if(ext_imm!=32'hffffffec) $fatal("Expected output not received");
        #10;

        instr <= 32'h00129023;
        opcode <=3'd3;
        #10;
        
        if(ext_imm!=32'h00000000) $fatal("Expected output not received");
        #10;

        instr <= 32'h00001117;
        opcode <= 3'd4;
        #10;
        
        if(ext_imm!=32'h00001000) $fatal("Expected output not received");
        #10;

        $display("All test cases passed");
        $finish;
    end
endmodule