data/full_repos/permissive/513806017/generated/Leros.v
data/verilator_xmls/89e8d668-0412-4ac1-97d0-bdf2db6b5e63.xml
module InstrMem(
  input         clock,
  input         reset,
  input  [9:0]  io_addr,
  output [15:0] io_instr
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif
  reg [9:0] memReg;
  wire [15:0] _GEN_1 = 3'h1 == memReg[2:0] ? 16'h903 : 16'h0;
  wire [15:0] _GEN_2 = 3'h2 == memReg[2:0] ? 16'hd02 : _GEN_1;
  wire [15:0] _GEN_3 = 3'h3 == memReg[2:0] ? 16'h21ab : _GEN_2;
  assign io_instr = 3'h4 == memReg[2:0] ? 16'h2400 : _GEN_3;
  always @(posedge clock) begin
    if (reset) begin
      memReg <= 10'h0;
    end else begin
      memReg <= io_addr;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  memReg = _RAND_0[9:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module InstrMem(
  input         clock,
  input         reset,
  input  [9:0]  io_addr,
  output [15:0] io_instr
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif
  reg [9:0] memReg;
  wire [15:0] _GEN_1 = 3'h1 == memReg[2:0] ? 16'h903 : 16'h0;
  wire [15:0] _GEN_2 = 3'h2 == memReg[2:0] ? 16'hd02 : _GEN_1;
  wire [15:0] _GEN_3 = 3'h3 == memReg[2:0] ? 16'h21ab : _GEN_2;
  assign io_instr = 3'h4 == memReg[2:0] ? 16'h2400 : _GEN_3;
  always @(posedge clock) begin
    if (reset) begin
      memReg <= 10'h0;
    end else begin
      memReg <= io_addr;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  memReg = _RAND_0[9:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule