data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu.v:27: Cannot find include file: sys.h\n`include "sys.h" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu.v:28: Cannot find include file: iop.h\n`include "iop.h" \n         ^~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu.v:168: Define or directive not defined: \'`CLK_IOB_WIDTH\'\n   output [`CLK_IOB_WIDTH-1:0]clsp_iob_data;  \n           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu.v:391: Define or directive not defined: \'`IOB_CLK_WIDTH\'\n   input [`IOB_CLK_WIDTH-1:0]iob_clsp_data;  \n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu.v:394: Define or directive not defined: \'`IOB_CPU_WIDTH\'\n   input [`IOB_CPU_WIDTH-1:0]iob_ctu_coreavail;  \n          ^~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu.v:525: Unsupported: Ignoring delay on this delayed statement.\n           #1 ;  \n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu.v:625: Define or directive not defined: \'`CLK_IOB_WIDTH\'\n    .clsp_iob_data   (clsp_iob_data[`CLK_IOB_WIDTH-1:0]),\n                                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu.v:740: Define or directive not defined: \'`IOB_CLK_WIDTH\'\n    .iob_clsp_data   (iob_clsp_data[`IOB_CLK_WIDTH-1:0]),\n                                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu.v:954: Define or directive not defined: \'`IOB_CPU_WIDTH\'\n    .iob_ctu_coreavail   (iob_ctu_coreavail[`IOB_CPU_WIDTH-1:0]),\n                                            ^~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s), 1 warning(s)\n'
module ctu_sync_pulse_check(

data, lclk, rclk, enable_chk
);

   input data;
   input lclk;
   input rclk;
   input enable_chk;

   parameter setup_clocks = 1 , 
             hold_clocks  = 0; 

   time  last_clk;
   time  last_data;
   time  first_edge;
   time  period;

   reg     enable_chk_int;

   always @( posedge rclk)
   begin
   if(enable_chk === 1'b1)
       first_edge = $time;
   end

   always @( negedge rclk)
   begin
     if(enable_chk === 1'b1)
        period = ($time - first_edge) * 2;
   end

  always @ (posedge rclk)
  if( ~enable_chk)
      enable_chk_int <= 1'b0;
  else
      enable_chk_int <= enable_chk; 

 always @ (posedge data) 
 begin 
         if((($time  - last_clk ) < ( setup_clocks * period)) & enable_chk_int 
           )
		`ifdef MODELSIM
           $display ( "CTU_mpath_error",
                    "Expect setup time : %t. Actual setup time %t",
                     (setup_clocks * period), ($time  - last_clk ));
		`else
           $error ( "CTU_mpath_error",
                    "Expect setup time : %t. Actual setup time %t",
                     (setup_clocks * period), ($time  - last_clk ));
		`endif
         last_data = $time;
  end

  always @ ( posedge lclk)
  begin
         if( (($time  - last_data) < ( hold_clocks * period)) & enable_chk_int 
           )
		`ifdef MODELSIM
           $display ( "CTU_mpath_error",
                    "Expect hold time : %t. Actual hold time %t",
                     (hold_clocks * period), ($time  - last_data ));
		`else
           $error ( "CTU_mpath_error",
                    "Expect hold time : %t. Actual hold time %t",
                     (hold_clocks * period), ($time  - last_data ));
		`endif
         last_clk = $time;
  end

   endmodule
module ctu_sync_pulse_check(

data, lclk, rclk, enable_chk
);


   input data;
   input lclk;
   input rclk;
   input enable_chk;

   parameter setup_clocks = 1 , 
             hold_clocks  = 0; 

   time  last_clk;
   time  last_data;
   time  first_edge;
   time  period;

   reg     enable_chk_int;

   always @( posedge rclk)
   begin
   if(enable_chk === 1'b1)
       first_edge = $time;
   end

   always @( negedge rclk)
   begin
     if(enable_chk === 1'b1)
        period = ($time - first_edge) * 2;
   end

  always @ (posedge rclk)
  if( ~enable_chk)
      enable_chk_int <= 1'b0;
  else
      enable_chk_int <= enable_chk; 

 always @ (posedge data) 
 begin 
         if((($time  - last_clk ) < ( setup_clocks * period)) & enable_chk_int 
           )
		`ifdef MODELSIM
           $display ( "CTU_mpath_error",
                    "Expect setup time : %t. Actual setup time %t",
                     (setup_clocks * period), ($time  - last_clk ));
		`else
           $error ( "CTU_mpath_error",
                    "Expect setup time : %t. Actual setup time %t",
                     (setup_clocks * period), ($time  - last_clk ));
		`endif
         last_data = $time;
  end

  always @ ( posedge lclk)
  begin
         if( (($time  - last_data) < ( hold_clocks * period)) & enable_chk_int 
           )
		`ifdef MODELSIM
           $display ( "CTU_mpath_error",
                    "Expect hold time : %t. Actual hold time %t",
                     (hold_clocks * period), ($time  - last_data ));
		`else
           $error ( "CTU_mpath_error",
                    "Expect hold time : %t. Actual hold time %t",
                     (hold_clocks * period), ($time  - last_data ));
		`endif
         last_clk = $time;
  end

   endmodule