data/full_repos/permissive/491135068/adder32.v
data/verilator_xmls/ac7d160e-7893-4fa0-8680-7bc8bea41b31.xml
module adder32(
    input [31:0] a, b,
    output reg [31:0] out
    );
    
    always@(a, b) begin
        out = a + b;
    end
endmodule
module adder32(
    input [31:0] a, b,
    output reg [31:0] out
    );

    
    always@(a, b) begin
        out = a + b;
    end
endmodule