data/full_repos/permissive/489994352/Image-Part/expand1x1.v
1: b"%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:2: Input/output/inout does not appear in port list: 'clk'\ninput clk, rst, i_data_valid;\n      ^~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:2: Input/output/inout does not appear in port list: 'rst'\ninput clk, rst, i_data_valid;\n           ^~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:2: Input/output/inout does not appear in port list: 'i_data_valid'\ninput clk, rst, i_data_valid;\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:3: Input/output/inout does not appear in port list: 'firesel'\ninput [2:0] firesel;\n            ^~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:5: Input/output/inout does not appear in port list: 'addressf1'\noutput [31:0] addressf1, addressfiltf1, addressf2, addressfiltf2,\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:5: Input/output/inout does not appear in port list: 'addressfiltf1'\noutput [31:0] addressf1, addressfiltf1, addressf2, addressfiltf2,\n                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:5: Input/output/inout does not appear in port list: 'addressf2'\noutput [31:0] addressf1, addressfiltf1, addressf2, addressfiltf2,\n                                        ^~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:5: Input/output/inout does not appear in port list: 'addressfiltf2'\noutput [31:0] addressf1, addressfiltf1, addressf2, addressfiltf2,\n                                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:6: Input/output/inout does not appear in port list: 'addressf3'\n              addressf3, addressfiltf3, addressf4, addressfiltf4,\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:6: Input/output/inout does not appear in port list: 'addressfiltf3'\n              addressf3, addressfiltf3, addressf4, addressfiltf4,\n                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:6: Input/output/inout does not appear in port list: 'addressf4'\n              addressf3, addressfiltf3, addressf4, addressfiltf4,\n                                        ^~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:6: Input/output/inout does not appear in port list: 'addressfiltf4'\n              addressf3, addressfiltf3, addressf4, addressfiltf4,\n                                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:7: Input/output/inout does not appear in port list: 'addressf5'\n              addressf5, addressfiltf5, addressf6, addressfiltf6,\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:7: Input/output/inout does not appear in port list: 'addressfiltf5'\n              addressf5, addressfiltf5, addressf6, addressfiltf6,\n                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:7: Input/output/inout does not appear in port list: 'addressf6'\n              addressf5, addressfiltf5, addressf6, addressfiltf6,\n                                        ^~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:7: Input/output/inout does not appear in port list: 'addressfiltf6'\n              addressf5, addressfiltf5, addressf6, addressfiltf6,\n                                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:8: Input/output/inout does not appear in port list: 'addressf7'\n              addressf7, addressfiltf7, addressf8, addressfiltf8,\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:8: Input/output/inout does not appear in port list: 'addressfiltf7'\n              addressf7, addressfiltf7, addressf8, addressfiltf8,\n                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:8: Input/output/inout does not appear in port list: 'addressf8'\n              addressf7, addressfiltf7, addressf8, addressfiltf8,\n                                        ^~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:8: Input/output/inout does not appear in port list: 'addressfiltf8'\n              addressf7, addressfiltf7, addressf8, addressfiltf8,\n                                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:9: Input/output/inout does not appear in port list: 'addressf9'\n              addressf9, addressfiltf9, addressf10, addressfiltf10,\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:9: Input/output/inout does not appear in port list: 'addressfiltf9'\n              addressf9, addressfiltf9, addressf10, addressfiltf10,\n                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:9: Input/output/inout does not appear in port list: 'addressf10'\n              addressf9, addressfiltf9, addressf10, addressfiltf10,\n                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:9: Input/output/inout does not appear in port list: 'addressfiltf10'\n              addressf9, addressfiltf9, addressf10, addressfiltf10,\n                                                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:10: Input/output/inout does not appear in port list: 'addressf11'\n              addressf11, addressfiltf11, addressf12, addressfiltf12,\n              ^~~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:10: Input/output/inout does not appear in port list: 'addressfiltf11'\n              addressf11, addressfiltf11, addressf12, addressfiltf12,\n                          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:10: Input/output/inout does not appear in port list: 'addressf12'\n              addressf11, addressfiltf11, addressf12, addressfiltf12,\n                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:10: Input/output/inout does not appear in port list: 'addressfiltf12'\n              addressf11, addressfiltf11, addressf12, addressfiltf12,\n                                                      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:11: Input/output/inout does not appear in port list: 'addressf13'\n              addressf13, addressfiltf13, addressf14, addressfiltf14,\n              ^~~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:11: Input/output/inout does not appear in port list: 'addressfiltf13'\n              addressf13, addressfiltf13, addressf14, addressfiltf14,\n                          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:11: Input/output/inout does not appear in port list: 'addressf14'\n              addressf13, addressfiltf13, addressf14, addressfiltf14,\n                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:11: Input/output/inout does not appear in port list: 'addressfiltf14'\n              addressf13, addressfiltf13, addressf14, addressfiltf14,\n                                                      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:12: Input/output/inout does not appear in port list: 'addressf15'\n              addressf15, addressfiltf15, addressf16, addressfiltf16;\n              ^~~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:12: Input/output/inout does not appear in port list: 'addressfiltf15'\n              addressf15, addressfiltf15, addressf16, addressfiltf16;\n                          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:12: Input/output/inout does not appear in port list: 'addressf16'\n              addressf15, addressfiltf15, addressf16, addressfiltf16;\n                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:12: Input/output/inout does not appear in port list: 'addressfiltf16'\n              addressf15, addressfiltf15, addressf16, addressfiltf16;\n                                                      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:13: Input/output/inout does not appear in port list: 'biasf1'\ninput [15:0] biasf1, biasf2, biasf3, biasf4,\n             ^~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:13: Input/output/inout does not appear in port list: 'biasf2'\ninput [15:0] biasf1, biasf2, biasf3, biasf4,\n                     ^~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:13: Input/output/inout does not appear in port list: 'biasf3'\ninput [15:0] biasf1, biasf2, biasf3, biasf4,\n                             ^~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:13: Input/output/inout does not appear in port list: 'biasf4'\ninput [15:0] biasf1, biasf2, biasf3, biasf4,\n                                     ^~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:14: Input/output/inout does not appear in port list: 'biasf5'\n             biasf5, biasf6, biasf7, biasf8,\n             ^~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:14: Input/output/inout does not appear in port list: 'biasf6'\n             biasf5, biasf6, biasf7, biasf8,\n                     ^~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:14: Input/output/inout does not appear in port list: 'biasf7'\n             biasf5, biasf6, biasf7, biasf8,\n                             ^~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:14: Input/output/inout does not appear in port list: 'biasf8'\n             biasf5, biasf6, biasf7, biasf8,\n                                     ^~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:15: Input/output/inout does not appear in port list: 'biasf9'\n             biasf9, biasf10, biasf11, biasf12,\n             ^~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:15: Input/output/inout does not appear in port list: 'biasf10'\n             biasf9, biasf10, biasf11, biasf12,\n                     ^~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:15: Input/output/inout does not appear in port list: 'biasf11'\n             biasf9, biasf10, biasf11, biasf12,\n                              ^~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:15: Input/output/inout does not appear in port list: 'biasf12'\n             biasf9, biasf10, biasf11, biasf12,\n                                       ^~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:16: Input/output/inout does not appear in port list: 'biasf13'\n             biasf13, biasf14, biasf15, biasf16;\n             ^~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/expand1x1.v:16: Input/output/inout does not appear in port list: 'biasf14'\n             biasf13, biasf14, biasf15, biasf16;\n                      ^~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n"
module expand1x1();
input clk, rst, i_data_valid;
input [2:0] firesel;

output [31:0] addressf1, addressfiltf1, addressf2, addressfiltf2,
              addressf3, addressfiltf3, addressf4, addressfiltf4,
              addressf5, addressfiltf5, addressf6, addressfiltf6,
              addressf7, addressfiltf7, addressf8, addressfiltf8,
              addressf9, addressfiltf9, addressf10, addressfiltf10,
              addressf11, addressfiltf11, addressf12, addressfiltf12,
              addressf13, addressfiltf13, addressf14, addressfiltf14,
              addressf15, addressfiltf15, addressf16, addressfiltf16;
input [15:0] biasf1, biasf2, biasf3, biasf4,
             biasf5, biasf6, biasf7, biasf8,
             biasf9, biasf10, biasf11, biasf12,
             biasf13, biasf14, biasf15, biasf16;
input [16*16-1:0] dataf1, dataf2, dataf3, dataf4,
                  dataf5, dataf6, dataf7, dataf8,
                  dataf9, dataf10, dataf11, dataf12,
                  dataf13, dataf14, dataf15, dataf16;

output [31:0] imgaddr;
input [16*8-1:0] imgdata;


output outvalid;
output [16*16-1:0] outim;
wire [15:0] outimw [0:15];


reg [31:0] inputchannel, chcyc, inputsize, filtersize, filtcyc;
always @(*)
begin
    case (firesel)
        3'd0:begin
            inputchannel = 32'd16;

            inputsize = 32'd55;
            filtersize = 32'd64;

        end
        3'd1:begin
            inputchannel = 32'd128;

            inputsize = 32'd55;
            filtersize = 32'd16;

        end
        3'd2:begin
            inputchannel = 32'd128;

            inputsize = 32'd27;
            filtersize = 32'd32;

        end
        3'd3:begin
            inputchannel = 32'd256;

            inputsize = 32'd27;
            filtersize = 32'd32;

        end
        3'd4:begin
            inputchannel = 32'd256;

            inputsize = 32'd13;
            filtersize = 32'd48;

        end
        3'd5:begin
            inputchannel = 32'd384;

            inputsize = 32'd13;
            filtersize = 32'd48;

        end
        3'd6:begin
            inputchannel = 32'd384;

            inputsize = 32'd13;
            filtersize = 32'd64;

        end
        3'd7:begin
            inputchannel = 32'd512;

            inputsize = 32'd13;
            filtersize = 32'd64;

        end
    endcase
end

endmodule
module expand1x1();

input clk, rst, i_data_valid;
input [2:0] firesel;

output [31:0] addressf1, addressfiltf1, addressf2, addressfiltf2,
              addressf3, addressfiltf3, addressf4, addressfiltf4,
              addressf5, addressfiltf5, addressf6, addressfiltf6,
              addressf7, addressfiltf7, addressf8, addressfiltf8,
              addressf9, addressfiltf9, addressf10, addressfiltf10,
              addressf11, addressfiltf11, addressf12, addressfiltf12,
              addressf13, addressfiltf13, addressf14, addressfiltf14,
              addressf15, addressfiltf15, addressf16, addressfiltf16;
input [15:0] biasf1, biasf2, biasf3, biasf4,
             biasf5, biasf6, biasf7, biasf8,
             biasf9, biasf10, biasf11, biasf12,
             biasf13, biasf14, biasf15, biasf16;
input [16*16-1:0] dataf1, dataf2, dataf3, dataf4,
                  dataf5, dataf6, dataf7, dataf8,
                  dataf9, dataf10, dataf11, dataf12,
                  dataf13, dataf14, dataf15, dataf16;

output [31:0] imgaddr;
input [16*8-1:0] imgdata;


output outvalid;
output [16*16-1:0] outim;
wire [15:0] outimw [0:15];


reg [31:0] inputchannel, chcyc, inputsize, filtersize, filtcyc;
always @(*)
begin
    case (firesel)
        3'd0:begin
            inputchannel = 32'd16;

            inputsize = 32'd55;
            filtersize = 32'd64;

        end
        3'd1:begin
            inputchannel = 32'd128;

            inputsize = 32'd55;
            filtersize = 32'd16;

        end
        3'd2:begin
            inputchannel = 32'd128;

            inputsize = 32'd27;
            filtersize = 32'd32;

        end
        3'd3:begin
            inputchannel = 32'd256;

            inputsize = 32'd27;
            filtersize = 32'd32;

        end
        3'd4:begin
            inputchannel = 32'd256;

            inputsize = 32'd13;
            filtersize = 32'd48;

        end
        3'd5:begin
            inputchannel = 32'd384;

            inputsize = 32'd13;
            filtersize = 32'd48;

        end
        3'd6:begin
            inputchannel = 32'd384;

            inputsize = 32'd13;
            filtersize = 32'd64;

        end
        3'd7:begin
            inputchannel = 32'd512;

            inputsize = 32'd13;
            filtersize = 32'd64;

        end
    endcase
end

endmodule