data/full_repos/permissive/452016975/src/data_memory_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/452016975/src/data_memory_testbench.v:18: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/data_memory_testbench.v:25: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/data_memory_testbench.v:33: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Error: data/full_repos/permissive/452016975/src/data_memory_testbench.v:35: Unsupported or unknown PLI call: $writememb\n $writememb("C:/Users/okant/Desktop/GTU/CSE331/hw4/simulation/modelsim/mem_memory.txt", obj_memory._memory);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/452016975/src/data_memory_testbench.v:38: Unsupported or unknown PLI call: $monitor\n $monitor("time=%2d, write_data=%32b,  adress=%2d,  mem_read=%1b,  mem_write=%1b,   read_data=%32b "\n ^~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module data_memory_testbench();
		
		wire [31:0] read_data;
		reg [31:0] adress; 
		reg [31:0] write_data;
		reg mem_read,mem_write;
	
	data_memory obj_memory(read_data,adress[31:0],write_data,mem_write,mem_read);
			
	initial begin
	$readmemb("C:/Users/okant/Desktop/GTU/CSE331/hw4/simulation/modelsim/mem_memory.txt", obj_memory._memory);


	write_data = 32'b0000_1111_0000_0000_0000_0000_0000_0011; 
	adress = 32'b00000000000000000000000000000001;
	mem_read = 1'b1;
	mem_write = 1'b0;
	#20;
	

	write_data = 32'b1111_0000_0000_0000_0000_0000_0000_0001; 
	adress = 32'b00000000000000000000000000000000;
	mem_read = 1'b0;
	mem_write = 1'b1;
	#20;
	
	

	write_data = 32'b1111_0000_0000_1111_0000_0000_0000_0001; 
	adress = 32'b00000000000000000000000000000010;
	mem_read = 1'b1;
	mem_write = 1'b0;
	#20;
	
	$writememb("C:/Users/okant/Desktop/GTU/CSE331/hw4/simulation/modelsim/mem_memory.txt", obj_memory._memory);
	end
	initial begin
	$monitor("time=%2d, write_data=%32b,  adress=%2d,  mem_read=%1b,  mem_write=%1b,   read_data=%32b "
																											,$time,write_data,adress,mem_read,mem_write,read_data);
	end
endmodule
module data_memory_testbench();

		
		wire [31:0] read_data;
		reg [31:0] adress; 
		reg [31:0] write_data;
		reg mem_read,mem_write;
	
	data_memory obj_memory(read_data,adress[31:0],write_data,mem_write,mem_read);
			
	initial begin
	$readmemb("C:/Users/okant/Desktop/GTU/CSE331/hw4/simulation/modelsim/mem_memory.txt", obj_memory._memory);


	write_data = 32'b0000_1111_0000_0000_0000_0000_0000_0011; 
	adress = 32'b00000000000000000000000000000001;
	mem_read = 1'b1;
	mem_write = 1'b0;
	#20;
	

	write_data = 32'b1111_0000_0000_0000_0000_0000_0000_0001; 
	adress = 32'b00000000000000000000000000000000;
	mem_read = 1'b0;
	mem_write = 1'b1;
	#20;
	
	

	write_data = 32'b1111_0000_0000_1111_0000_0000_0000_0001; 
	adress = 32'b00000000000000000000000000000010;
	mem_read = 1'b1;
	mem_write = 1'b0;
	#20;
	
	$writememb("C:/Users/okant/Desktop/GTU/CSE331/hw4/simulation/modelsim/mem_memory.txt", obj_memory._memory);
	end
	initial begin
	$monitor("time=%2d, write_data=%32b,  adress=%2d,  mem_read=%1b,  mem_write=%1b,   read_data=%32b "
																											,$time,write_data,adress,mem_read,mem_write,read_data);
	end
endmodule