data/full_repos/permissive/41807012/rtl/generic/crc16.v
1: b"%Error: data/full_repos/permissive/41807012/rtl/generic/crc16.v:55: syntax error, unexpected ',', expecting IDENTIFIER or do or final\n  input                 bit,\n                           ^\n%Error: data/full_repos/permissive/41807012/rtl/generic/crc16.v:57: syntax error, unexpected ')', expecting ',' or ';'\n);\n^\n%Error: data/full_repos/permissive/41807012/rtl/generic/crc16.v:64: syntax error, unexpected assign\nassign inv = bit ^ crc[15];   \n^~~~~~\n%Error: Exiting due to 3 error(s)\n"
module crc16 #(
  parameter             POLYNOMIAL  =   16'h1021,
  parameter             SEED        =   16'h0000
)(
  input                 clk,
  input                 rst,
  input                 en,
  input                 bit,
  output  reg   [15:0]  crc
);



wire         inv;


assign inv = bit ^ crc[15];



always @ (posedge clk) begin
  if (rst) begin

    crc  <=  0;
  end
  else begin

    if (en) begin

      crc[15] <= crc[14];
      crc[14] <= crc[13];
      crc[13] <= crc[12];
      crc[12] <= crc[11] ^ inv;
      crc[11] <= crc[10];
      crc[10] <= crc[9];
      crc[9]  <= crc[8];
      crc[8]  <= crc[7];
      crc[7]  <= crc[6];
      crc[6]  <= crc[5];
      crc[5]  <= crc[4] ^ inv;
      crc[4]  <= crc[3];
      crc[3]  <= crc[2];
      crc[2]  <= crc[1];
      crc[1]  <= crc[0];
      crc[0]  <= inv;
    end
  end
end

endmodule
module crc16 #(
  parameter             POLYNOMIAL  =   16'h1021,
  parameter             SEED        =   16'h0000
)(
  input                 clk,
  input                 rst,
  input                 en,
  input                 bit,
  output  reg   [15:0]  crc
);




wire         inv;


assign inv = bit ^ crc[15];



always @ (posedge clk) begin
  if (rst) begin

    crc  <=  0;
  end
  else begin

    if (en) begin

      crc[15] <= crc[14];
      crc[14] <= crc[13];
      crc[13] <= crc[12];
      crc[12] <= crc[11] ^ inv;
      crc[11] <= crc[10];
      crc[10] <= crc[9];
      crc[9]  <= crc[8];
      crc[8]  <= crc[7];
      crc[7]  <= crc[6];
      crc[6]  <= crc[5];
      crc[5]  <= crc[4] ^ inv;
      crc[4]  <= crc[3];
      crc[3]  <= crc[2];
      crc[2]  <= crc[1];
      crc[1]  <= crc[0];
      crc[0]  <= inv;
    end
  end
end

endmodule