data/full_repos/permissive/445357518/cpu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/445357518/cpu.v:43: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 17 bits.\n                                                             : ... In instance cpu\n assign pc = {8\'b0, PC};\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/445357518/cpu.v:45: Cannot find file containing module: \'vDFF1\'\n vDFF1 #(16) instructionRegister(clk, in, load_ir, regOut);\n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/vDFF1\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/vDFF1.v\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/vDFF1.sv\n             vDFF1\n             vDFF1.v\n             vDFF1.sv\n             obj_dir/vDFF1\n             obj_dir/vDFF1.v\n             obj_dir/vDFF1.sv\n%Error: data/full_repos/permissive/445357518/cpu.v:54: Cannot find file containing module: \'datapath\'\n datapath DP(.clk(clk), .write(write),.loada(loada),.loadb(loadb),.loadc(loadc),.loads(loads)\n ^~~~~~~~\n%Error: data/full_repos/permissive/445357518/cpu.v:64: Cannot find file containing module: \'vDFF1\'\n vDFF1 #(9) Program_Counter(clk, next_PC, load_PC, PC);\n ^~~~~\n%Error: data/full_repos/permissive/445357518/cpu.v:73: Cannot find file containing module: \'vDFF1\'\n vDFF1 #(9) Data_Address(clk, out[8:0], load_addr, DA);\n ^~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n'
module cpu(clk,reset,in,out,N,V,Z, mem_cmd, mem_addr);
	input clk, reset;
	input [15:0] in;
	output [15:0] out;
	output N, V, Z;
	wire [15:0] regOut, sximm5, sximm8,mdata, out, pc;
        wire[2:0] opcode,nsel, readnum, writenum; 
        wire[1:0] op, ALUop, shift,vsel;
        wire loada, loadb, loadc, loads, asel, bsel,write, address_select, load_PC, reset_PC, load_ir, load_addr;
	wire[8:0] next_PC, PC, next_PC_out_plusOne, DA; 
	output[1:0] mem_cmd;
	output[8:0] mem_addr; 

	assign pc = {8'b0, PC};

	vDFF1 #(16) instructionRegister(clk, in, load_ir, regOut);
	

	instruction_decoder ID(regOut, nsel, ALUop, sximm5, sximm8, shift, readnum, writenum, opcode, op);


	FSM fSM(clk,reset,opcode,op,nsel,loada,loadb,loadc,loads,asel,bsel,vsel,write, mem_cmd, address_select, load_PC, reset_PC, load_ir, load_addr);


	datapath DP(.clk(clk), .write(write),.loada(loada),.loadb(loadb),.loadc(loadc),.loads(loads)
                       , .asel(asel),.bsel(bsel),.vsel(vsel), .writenum(writenum), 
                      .readnum(readnum),  .sximm5(sximm5), .sximm8(sximm8), .mdata(in), 
                     .PC(pc),  .datapath_out(out), .shift(shift), .ALUop(ALUop)  
                      , .N_out(N), .V_out(V), .Z_out(Z));


	assign next_PC = reset_PC ? 9'b000000000: next_PC_out_plusOne;


	vDFF1 #(9) Program_Counter(clk, next_PC, load_PC, PC);


	assign next_PC_out_plusOne = PC + 9'd1;
	

	assign mem_addr = address_select ? PC: DA; 
	

	vDFF1 #(9) Data_Address(clk, out[8:0], load_addr, DA);

endmodule
module cpu(clk,reset,in,out,N,V,Z, mem_cmd, mem_addr);

	input clk, reset;
	input [15:0] in;
	output [15:0] out;
	output N, V, Z;
	wire [15:0] regOut, sximm5, sximm8,mdata, out, pc;
        wire[2:0] opcode,nsel, readnum, writenum; 
        wire[1:0] op, ALUop, shift,vsel;
        wire loada, loadb, loadc, loads, asel, bsel,write, address_select, load_PC, reset_PC, load_ir, load_addr;
	wire[8:0] next_PC, PC, next_PC_out_plusOne, DA; 
	output[1:0] mem_cmd;
	output[8:0] mem_addr; 

	assign pc = {8'b0, PC};

	vDFF1 #(16) instructionRegister(clk, in, load_ir, regOut);
	

	instruction_decoder ID(regOut, nsel, ALUop, sximm5, sximm8, shift, readnum, writenum, opcode, op);


	FSM fSM(clk,reset,opcode,op,nsel,loada,loadb,loadc,loads,asel,bsel,vsel,write, mem_cmd, address_select, load_PC, reset_PC, load_ir, load_addr);


	datapath DP(.clk(clk), .write(write),.loada(loada),.loadb(loadb),.loadc(loadc),.loads(loads)
                       , .asel(asel),.bsel(bsel),.vsel(vsel), .writenum(writenum), 
                      .readnum(readnum),  .sximm5(sximm5), .sximm8(sximm8), .mdata(in), 
                     .PC(pc),  .datapath_out(out), .shift(shift), .ALUop(ALUop)  
                      , .N_out(N), .V_out(V), .Z_out(Z));


	assign next_PC = reset_PC ? 9'b000000000: next_PC_out_plusOne;


	vDFF1 #(9) Program_Counter(clk, next_PC, load_PC, PC);


	assign next_PC_out_plusOne = PC + 9'd1;
	

	assign mem_addr = address_select ? PC: DA; 
	

	vDFF1 #(9) Data_Address(clk, out[8:0], load_addr, DA);

endmodule