data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/lsu/rtl/aq_lsu_lm.v
1: b"%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/lsu/rtl/aq_lsu_lm.v:95: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_aq_lsu_lm_gated_clk (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/lsu/rtl,data/full_repos/permissive/418750043/gated_clk_cell\n             data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/lsu/rtl,data/full_repos/permissive/418750043/gated_clk_cell.v\n             data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/lsu/rtl,data/full_repos/permissive/418750043/gated_clk_cell.sv\n             gated_clk_cell\n             gated_clk_cell.v\n             gated_clk_cell.sv\n             obj_dir/gated_clk_cell\n             obj_dir/gated_clk_cell.v\n             obj_dir/gated_clk_cell.sv\n%Error: Exiting due to 1 error(s)\n"
module aq_lsu_lm(
  cp0_lsu_icg_en,
  cpurst_b,
  forever_cpuclk,
  ifu_lsu_warm_up,
  lm_clr,
  lm_pass,
  lm_req_addr,
  lm_req_size,
  lm_set,
  lm_set_gate,
  pad_yy_icg_scan_en,
  rtu_lsu_expt_ack,
  rtu_lsu_expt_exit
);


input           cp0_lsu_icg_en;    
input           cpurst_b;          
input           forever_cpuclk;    
input           ifu_lsu_warm_up;   
input           lm_clr;            
input   [39:0]  lm_req_addr;       
input   [1 :0]  lm_req_size;       
input           lm_set;            
input           lm_set_gate;       
input           pad_yy_icg_scan_en; 
input           rtu_lsu_expt_ack;  
input           rtu_lsu_expt_exit; 
output          lm_pass;           


reg     [39:0]  lm_addr;           
reg             lm_cur_state;      
reg             lm_next_state;     
reg     [1 :0]  lm_size;           


wire            cp0_lsu_icg_en;    
wire            cpurst_b;          
wire            expt_ack;          
wire            expt_exit;         
wire            forever_cpuclk;    
wire            ifu_lsu_warm_up;   
wire            lm_clk;            
wire            lm_clk_en;         
wire            lm_clr;            
wire            lm_pass;           
wire    [39:0]  lm_req_addr;       
wire    [1 :0]  lm_req_size;       
wire            lm_set;            
wire            lm_set_gate;       
wire            pad_yy_icg_scan_en; 
wire            rtu_lsu_expt_ack;  
wire            rtu_lsu_expt_exit; 
wire            warm_up;           


parameter PADDR = 40;



assign warm_up = ifu_lsu_warm_up;


assign expt_exit = rtu_lsu_expt_exit;
assign expt_ack  = rtu_lsu_expt_ack;



parameter LM_OPEN = 1'b0;
parameter LM_EXCL = 1'b1;

assign lm_clk_en = lm_set_gate | (lm_cur_state == LM_EXCL) | ifu_lsu_warm_up; 


gated_clk_cell  x_aq_lsu_lm_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (lm_clk            ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (lm_clk_en         ),
  .module_en          (cp0_lsu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);








always@(posedge lm_clk or negedge cpurst_b)
begin
  if (!cpurst_b) 
    lm_cur_state <= LM_OPEN;
  else
    lm_cur_state <= lm_next_state;
end
      

always @( expt_ack
       or lm_clr
       or lm_cur_state
       or expt_exit
       or lm_set)
begin
  case (lm_cur_state)
    LM_OPEN:begin
      if (lm_set & !expt_ack & !expt_exit)
        lm_next_state = LM_EXCL;
      else
        lm_next_state = LM_OPEN;
    end
    LM_EXCL:begin
      if (expt_ack | expt_exit | lm_clr)
        lm_next_state = LM_OPEN;
      else
        lm_next_state = LM_EXCL;
    end
    default: lm_next_state = LM_OPEN;
  endcase

end

always@(posedge lm_clk)
begin
  if (warm_up)
  begin
    lm_addr[PADDR-1:0] <= {PADDR{1'b0}};
    lm_size[1:0]       <= 2'b0; 
  end
  else if (lm_set)
  begin
    lm_addr[PADDR-1:0] <= lm_req_addr[PADDR-1:0];
    lm_size[1:0]       <= lm_req_size[1:0]; 
  end
end

assign lm_pass = lm_cur_state
                 & (lm_addr[PADDR-1:0] == lm_req_addr[PADDR-1:0])
                 & (lm_size[1:0] == lm_req_size[1:0]);



endmodule
module aq_lsu_lm(
  cp0_lsu_icg_en,
  cpurst_b,
  forever_cpuclk,
  ifu_lsu_warm_up,
  lm_clr,
  lm_pass,
  lm_req_addr,
  lm_req_size,
  lm_set,
  lm_set_gate,
  pad_yy_icg_scan_en,
  rtu_lsu_expt_ack,
  rtu_lsu_expt_exit
);



input           cp0_lsu_icg_en;    
input           cpurst_b;          
input           forever_cpuclk;    
input           ifu_lsu_warm_up;   
input           lm_clr;            
input   [39:0]  lm_req_addr;       
input   [1 :0]  lm_req_size;       
input           lm_set;            
input           lm_set_gate;       
input           pad_yy_icg_scan_en; 
input           rtu_lsu_expt_ack;  
input           rtu_lsu_expt_exit; 
output          lm_pass;           


reg     [39:0]  lm_addr;           
reg             lm_cur_state;      
reg             lm_next_state;     
reg     [1 :0]  lm_size;           


wire            cp0_lsu_icg_en;    
wire            cpurst_b;          
wire            expt_ack;          
wire            expt_exit;         
wire            forever_cpuclk;    
wire            ifu_lsu_warm_up;   
wire            lm_clk;            
wire            lm_clk_en;         
wire            lm_clr;            
wire            lm_pass;           
wire    [39:0]  lm_req_addr;       
wire    [1 :0]  lm_req_size;       
wire            lm_set;            
wire            lm_set_gate;       
wire            pad_yy_icg_scan_en; 
wire            rtu_lsu_expt_ack;  
wire            rtu_lsu_expt_exit; 
wire            warm_up;           


parameter PADDR = 40;



assign warm_up = ifu_lsu_warm_up;


assign expt_exit = rtu_lsu_expt_exit;
assign expt_ack  = rtu_lsu_expt_ack;



parameter LM_OPEN = 1'b0;
parameter LM_EXCL = 1'b1;

assign lm_clk_en = lm_set_gate | (lm_cur_state == LM_EXCL) | ifu_lsu_warm_up; 


gated_clk_cell  x_aq_lsu_lm_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (lm_clk            ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (lm_clk_en         ),
  .module_en          (cp0_lsu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);








always@(posedge lm_clk or negedge cpurst_b)
begin
  if (!cpurst_b) 
    lm_cur_state <= LM_OPEN;
  else
    lm_cur_state <= lm_next_state;
end
      

always @( expt_ack
       or lm_clr
       or lm_cur_state
       or expt_exit
       or lm_set)
begin
  case (lm_cur_state)
    LM_OPEN:begin
      if (lm_set & !expt_ack & !expt_exit)
        lm_next_state = LM_EXCL;
      else
        lm_next_state = LM_OPEN;
    end
    LM_EXCL:begin
      if (expt_ack | expt_exit | lm_clr)
        lm_next_state = LM_OPEN;
      else
        lm_next_state = LM_EXCL;
    end
    default: lm_next_state = LM_OPEN;
  endcase

end

always@(posedge lm_clk)
begin
  if (warm_up)
  begin
    lm_addr[PADDR-1:0] <= {PADDR{1'b0}};
    lm_size[1:0]       <= 2'b0; 
  end
  else if (lm_set)
  begin
    lm_addr[PADDR-1:0] <= lm_req_addr[PADDR-1:0];
    lm_size[1:0]       <= lm_req_size[1:0]; 
  end
end

assign lm_pass = lm_cur_state
                 & (lm_addr[PADDR-1:0] == lm_req_addr[PADDR-1:0])
                 & (lm_size[1:0] == lm_req_size[1:0]);



endmodule