data/full_repos/permissive/515245706/milestone1/numberDrawer/number1.v
1: b'%Error: data/full_repos/permissive/515245706/milestone1/numberDrawer/number1.v:10: Cannot find file containing module: \'verticalLine\'\n verticalLine v0(\n ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/515245706/milestone1/numberDrawer,data/full_repos/permissive/515245706/verticalLine\n             data/full_repos/permissive/515245706/milestone1/numberDrawer,data/full_repos/permissive/515245706/verticalLine.v\n             data/full_repos/permissive/515245706/milestone1/numberDrawer,data/full_repos/permissive/515245706/verticalLine.sv\n             verticalLine\n             verticalLine.v\n             verticalLine.sv\n             obj_dir/verticalLine\n             obj_dir/verticalLine.v\n             obj_dir/verticalLine.sv\n%Warning-WIDTH: data/full_repos/permissive/515245706/milestone1/numberDrawer/number1.v:21: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'x\' generates 5 bits.\n                                                                                         : ... In instance number1\n assign xOut = xIn + x;\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/515245706/milestone1/numberDrawer/number1.v:22: Operator ADD expects 7 bits on the RHS, but RHS\'s VARREF \'y\' generates 5 bits.\n                                                                                         : ... In instance number1\n assign yOut = yIn + y;\n                   ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module number1(xIn, yIn, clk, enable, resetn, xOut, yOut);
	input [7: 0] xIn;
	input [6: 0] yIn;
	input clk, enable, resetn;
	output [7: 0] xOut;
	output [6: 0] yOut;
	
	wire [4:0]x, y;
	
	verticalLine v0(
		.x(5'd14),
		.y(5'd7),
		.distance(5'd15),
		.clk(clk),
		.enable(enable),
		.resetn(resetn),
		.xOut(x),
		.yOut(y)
	);
	
	assign xOut = xIn + x;
	assign yOut = yIn + y;
endmodule
module number1(xIn, yIn, clk, enable, resetn, xOut, yOut);

	input [7: 0] xIn;
	input [6: 0] yIn;
	input clk, enable, resetn;
	output [7: 0] xOut;
	output [6: 0] yOut;
	
	wire [4:0]x, y;
	
	verticalLine v0(
		.x(5'd14),
		.y(5'd7),
		.distance(5'd15),
		.clk(clk),
		.enable(enable),
		.resetn(resetn),
		.xOut(x),
		.yOut(y)
	);
	
	assign xOut = xIn + x;
	assign yOut = yIn + y;
endmodule