data/full_repos/permissive/429737743/sources_1/new/RF.v
1: b'%Error: data/full_repos/permissive/429737743/sources_1/new/RF.v:21: Cannot find include file: cpu_constant.v\n`include "cpu_constant.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/429737743/sources_1/new,data/full_repos/permissive/429737743/cpu_constant.v\n             data/full_repos/permissive/429737743/sources_1/new,data/full_repos/permissive/429737743/cpu_constant.v.v\n             data/full_repos/permissive/429737743/sources_1/new,data/full_repos/permissive/429737743/cpu_constant.v.sv\n             cpu_constant.v\n             cpu_constant.v.v\n             cpu_constant.v.sv\n             obj_dir/cpu_constant.v\n             obj_dir/cpu_constant.v.v\n             obj_dir/cpu_constant.v.sv\n%Error: data/full_repos/permissive/429737743/sources_1/new/RF.v:49: Define or directive not defined: \'`RRD\'\n            `RRD : begin\n            ^~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/RF.v:49: syntax error, unexpected \':\', expecting endcase\n            `RRD : begin\n                 ^\n%Error: data/full_repos/permissive/429737743/sources_1/new/RF.v:53: Define or directive not defined: \'`RWT\'\n            `RWT : begin\n            ^~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/RF.v:53: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `RWT : begin\n                   ^~~~~\n%Error: Cannot continue\n'
module RF(rs1, rs2, zero, a, b, neg, uneg,
    ctl, rd, Ans
);
output [31 : 0] a, b;reg [31 : 0] a, b;
output zero, neg, uneg;
input [4 : 0] rd, rs1, rs2;
input [31 : 0] Ans;
input [1 : 0] ctl;

reg [31 : 0] x[0 : 31];

assign zero = ((Ans == 0) ? 1'b1 : 1'b0);
assign neg = Ans[31 : 31];
assign uneg = a[31 : 31];

initial begin
    x[0] = 0;
    x[1] = 0;
    x[2] = 0;
    x[3] = 0;
end


always @(*) begin
    if (ctl[1 : 1]) begin
        case(ctl[0 : 0])
            `RRD : begin
                a = x[rs1];
                b = x[rs2];
            end
            `RWT : begin
                x[rd] = Ans;
            end
        endcase
    end
end
endmodule
module RF(rs1, rs2, zero, a, b, neg, uneg,
    ctl, rd, Ans
);

output [31 : 0] a, b;reg [31 : 0] a, b;
output zero, neg, uneg;
input [4 : 0] rd, rs1, rs2;
input [31 : 0] Ans;
input [1 : 0] ctl;

reg [31 : 0] x[0 : 31];

assign zero = ((Ans == 0) ? 1'b1 : 1'b0);
assign neg = Ans[31 : 31];
assign uneg = a[31 : 31];

initial begin
    x[0] = 0;
    x[1] = 0;
    x[2] = 0;
    x[3] = 0;
end


always @(*) begin
    if (ctl[1 : 1]) begin
        case(ctl[0 : 0])
            `RRD : begin
                a = x[rs1];
                b = x[rs2];
            end
            `RWT : begin
                x[rd] = Ans;
            end
        endcase
    end
end
endmodule