data/full_repos/permissive/482168662/lab02_counter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/482168662/lab02_counter.v:56: Operator ASSIGNDLY expects 26 bits on the Assign RHS, but Assign RHS\'s CONST \'25\'h0\' generates 25 bits.\n                                                                       : ... In instance top_module.fenpiqi\n            cnt <= 25\'b0;\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/482168662/lab02_counter.v:58: Operator ASSIGNDLY expects 26 bits on the Assign RHS, but Assign RHS\'s CONST \'25\'h0\' generates 25 bits.\n                                                                       : ... In instance top_module.fenpiqi\n                cnt <= 25\'b0;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/482168662/lab02_counter.v:57: Operator EQ expects 26 bits on the RHS, but RHS\'s VARREF \'MAX\' generates 25 bits.\n                                                                       : ... In instance top_module.fenpiqi\n        else if(cnt == MAX)\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/482168662/lab02_counter.v:66: Operator EQ expects 26 bits on the RHS, but RHS\'s VARREF \'MAX\' generates 25 bits.\n                                                                       : ... In instance top_module.fenpiqi\n        else if(cnt == MAX)\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/482168662/lab02_counter.v:73: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                       : ... In instance top_module.fenpiqi\n            cnt_10Hz <= 22\'b0;\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/482168662/lab02_counter.v:75: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                       : ... In instance top_module.fenpiqi\n                cnt_10Hz <= 22\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/482168662/lab02_counter.v:74: Operator EQ expects 23 bits on the RHS, but RHS\'s VARREF \'MAX_10Hz\' generates 22 bits.\n                                                                       : ... In instance top_module.fenpiqi\n        else if(cnt_10Hz == MAX_10Hz)\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/482168662/lab02_counter.v:83: Operator EQ expects 23 bits on the RHS, but RHS\'s VARREF \'MAX_10Hz\' generates 22 bits.\n                                                                       : ... In instance top_module.fenpiqi\n        else if(cnt_10Hz == MAX_10Hz)\n                         ^~\n%Error: Exiting due to 8 warning(s)\n'
module top_module(
    input clk,
    input rst_n,
    input control,
    output [7:0] led_out
);
    wire clk_1Hz,clk_10Hz;

    divide fenpiqi(
        .clk(clk),
        .rst_n(rst_n),
        .clk_1Hz(clk_1Hz),
        .clk_10Hz(clk_10Hz)
    );
    counter cnt(
        .clk(clk),
        .clk_1Hz(clk_1Hz),
        .clk_10Hz(clk_10Hz),
        .key_sw0(control),
        .key_sw3_n(rst_n),
        .led(led_out)
    );
    
endmodule
module top_module(
    input clk,
    input rst_n,
    input control,
    output [7:0] led_out
);

    wire clk_1Hz,clk_10Hz;

    divide fenpiqi(
        .clk(clk),
        .rst_n(rst_n),
        .clk_1Hz(clk_1Hz),
        .clk_10Hz(clk_10Hz)
    );
    counter cnt(
        .clk(clk),
        .clk_1Hz(clk_1Hz),
        .clk_10Hz(clk_10Hz),
        .key_sw0(control),
        .key_sw3_n(rst_n),
        .led(led_out)
    );
    
endmodule