data/full_repos/permissive/40581558/fpga_sim/model_rec/src_trans/EmitOneCH.v
1: b'%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/model_rec/src_trans/EmitOneCH.v:24: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                               : ... In instance EmitOneCH\n    Delay_Counter <= 8\'d0;\n                  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/model_rec/src_trans/EmitOneCH.v:61: Operator LT expects 9 bits on the LHS, but LHS\'s VARREF \'Emit_Counter\' generates 7 bits.\n                                                                                               : ... In instance EmitOneCH\n    else if(Emit_Counter <({Emit_Width,2\'b0}+Emit_Width))begin              \n                         ^\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/model_rec/src_trans/EmitOneCH.v:61: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'Emit_Width\' generates 7 bits.\n                                                                                               : ... In instance EmitOneCH\n    else if(Emit_Counter <({Emit_Width,2\'b0}+Emit_Width))begin              \n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/model_rec/src_trans/EmitOneCH.v:42: Operator LT expects 8 bits on the LHS, but LHS\'s VARREF \'Emit_Counter\' generates 7 bits.\n                                                                                               : ... In instance EmitOneCH\n    else if(Emit_Counter <{Emit_Width,1\'b0})begin            \n                         ^\n%Error: Exiting due to 4 warning(s)\n'
module  EmitOneCH
(
  input         Transmit_CLK,
  input         RX_Gate,
  input   [7:0] EmitDelay,
  input   [6:0] Emit_Width,
  output  reg   TXP,
  output  reg   TXN
  );  
    
	 
	 
  reg  [6:0]  Emit_Counter;
  
  reg  [6:0]  Delay_Counter;
    
	 
  always @(posedge Transmit_CLK or negedge RX_Gate)
  begin
  	if(~RX_Gate) 
	 begin
  		Emit_Counter  <= 7'd0;
  		Delay_Counter <= 8'd0;
  		TXP           <= 1'b1;
  		TXN           <= 1'b1;
  	end
  	else
  		begin
  		  if(Delay_Counter < EmitDelay[6:0] ) begin
  				Delay_Counter <= Delay_Counter + 1'b1;
  				TXP           <= 1'b1;
				TXN           <= 1'b1;
		  end
  		  else begin
			if(~EmitDelay[7]) begin
				if(Emit_Counter <Emit_Width)begin
					TXP <= 1'b1;
					TXN <= 1'b0;
					Emit_Counter <= Emit_Counter + 1'b1;
				end
				else if(Emit_Counter <{Emit_Width,1'b0})begin
					TXP <= 1'b0;
					TXN <= 1'b1;
					Emit_Counter <= Emit_Counter + 1'b1;
				end		

				else if(Emit_Counter <({Emit_Width,2'b0}+Emit_Width))begin
					TXP <= 1'b0;
					TXN <= 1'b0;
					Emit_Counter <= Emit_Counter + 1'b1;
				end
				
				else begin                                               
					TXP <= 1'b1;
					TXN <= 1'b1;
				end
				
				
			end
			else begin
				TXP <= 1'b1;
				TXN <= 1'b1;
			end


		  end
	   end
  end

    
endmodule
module  EmitOneCH
(
  input         Transmit_CLK,
  input         RX_Gate,
  input   [7:0] EmitDelay,
  input   [6:0] Emit_Width,
  output  reg   TXP,
  output  reg   TXN
  );
  
    
	 
	 
  reg  [6:0]  Emit_Counter;
  
  reg  [6:0]  Delay_Counter;
    
	 
  always @(posedge Transmit_CLK or negedge RX_Gate)
  begin
  	if(~RX_Gate) 
	 begin
  		Emit_Counter  <= 7'd0;
  		Delay_Counter <= 8'd0;
  		TXP           <= 1'b1;
  		TXN           <= 1'b1;
  	end
  	else
  		begin
  		  if(Delay_Counter < EmitDelay[6:0] ) begin
  				Delay_Counter <= Delay_Counter + 1'b1;
  				TXP           <= 1'b1;
				TXN           <= 1'b1;
		  end
  		  else begin
			if(~EmitDelay[7]) begin
				if(Emit_Counter <Emit_Width)begin
					TXP <= 1'b1;
					TXN <= 1'b0;
					Emit_Counter <= Emit_Counter + 1'b1;
				end
				else if(Emit_Counter <{Emit_Width,1'b0})begin
					TXP <= 1'b0;
					TXN <= 1'b1;
					Emit_Counter <= Emit_Counter + 1'b1;
				end		

				else if(Emit_Counter <({Emit_Width,2'b0}+Emit_Width))begin
					TXP <= 1'b0;
					TXN <= 1'b0;
					Emit_Counter <= Emit_Counter + 1'b1;
				end
				
				else begin                                               
					TXP <= 1'b1;
					TXN <= 1'b1;
				end
				
				
			end
			else begin
				TXP <= 1'b1;
				TXN <= 1'b1;
			end


		  end
	   end
  end

    
endmodule