data/full_repos/permissive/499083592/wrapper.v
1: b"%Error: data/full_repos/permissive/499083592/wrapper.v:63: Define or directive not defined: '`MPRJ_IO_PADS'\n    input wire [`MPRJ_IO_PADS-1:0] io_in,            \n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499083592/wrapper.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n    inout wire [`MPRJ_IO_PADS-1:0] io_out,           \n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499083592/wrapper.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n    inout wire [`MPRJ_IO_PADS-1:0] io_oeb,           \n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499083592/wrapper.v:88: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0]    buf_io_out;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499083592/wrapper.v:89: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0]    buf_io_oeb;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499083592/wrapper.v:150: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_out       = active ? buf_io_out       : {`MPRJ_IO_PADS{1'bz}};\n                                                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499083592/wrapper.v:151: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_oeb       = active ? buf_io_oeb       : {`MPRJ_IO_PADS{1'bz}};\n                                                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499083592/wrapper.v:168: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign buf_io_oeb = {`MPRJ_IO_PADS{1'b0}};\n                         ^~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module wrapped_instrumented_adder_behav(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif
    input wire wb_clk_i,

`ifdef USE_WB
    input wire          wb_rst_i,
    input wire          wbs_stb_i,
    input wire          wbs_cyc_i,
    input wire          wbs_we_i,
    input wire [3:0]    wbs_sel_i,
    input wire [31:0]   wbs_dat_i,
    input wire [31:0]   wbs_adr_i,
    inout wire          wbs_ack_o,
    inout wire [31:0]   wbs_dat_o,
`endif


`ifdef USE_SHARED_OPENRAM
    inout wire          rambus_wb_clk_o,
    inout wire          rambus_wb_rst_o,
    inout wire          rambus_wb_stb_o,
    inout wire          rambus_wb_cyc_o,
    inout wire          rambus_wb_we_o,
    inout wire [3:0]    rambus_wb_sel_o,
    inout wire [31:0]   rambus_wb_dat_o,
    inout wire [9:0]    rambus_wb_adr_o,
    input wire          rambus_wb_ack_i,
    input wire [31:0]   rambus_wb_dat_i,
`endif



`ifdef USE_LA
    input wire [31:0]   la1_data_in,
    inout wire [31:0]   la1_data_out,
    input wire [31:0]   la1_oenb,
    input wire [31:0]   la2_data_in,
    inout wire [31:0]   la2_data_out,
    input wire [31:0]   la2_oenb,
    input wire [31:0]   la3_data_in,
    inout wire [31:0]   la3_data_out,
    input wire [31:0]   la3_oenb,
`endif


`ifdef USE_IO
    input wire [`MPRJ_IO_PADS-1:0] io_in,
    inout wire [`MPRJ_IO_PADS-1:0] io_out,
    inout wire [`MPRJ_IO_PADS-1:0] io_oeb,
`endif


`ifdef USE_IRQ
    inout wire [2:0] user_irq,
`endif

`ifdef USE_CLK2

    input wire user_clock2,
`endif
    

    input wire active
);


    wire                        buf_wbs_ack_o;
    wire [31:0]                 buf_wbs_dat_o;
    wire [31:0]                 buf_la1_data_out;
    wire [31:0]                 buf_la2_data_out;
    wire [31:0]                 buf_la3_data_out;
    wire [`MPRJ_IO_PADS-1:0]    buf_io_out;
    wire [`MPRJ_IO_PADS-1:0]    buf_io_oeb;
    wire [2:0]                  buf_user_irq;
    wire                        buf_rambus_wb_clk_o;
    wire                        buf_rambus_wb_rst_o;
    wire                        buf_rambus_wb_stb_o;
    wire                        buf_rambus_wb_cyc_o;
    wire                        buf_rambus_wb_we_o;
    wire [3:0]                  buf_rambus_wb_sel_o;
    wire [31:0]                 buf_rambus_wb_dat_o;
    wire [9:0]                  buf_rambus_wb_adr_o;

    `ifdef FORMAL

    `ifdef USE_WB
    assign wbs_ack_o    = active ? buf_wbs_ack_o    : 1'b0;
    assign wbs_dat_o    = active ? buf_wbs_dat_o    : 32'b0;
    `endif
    `ifdef USE_SHARED_OPENRAM
    assign rambus_wb_clk_o = active ? buf_rambus_wb_clk_o : 1'b0;
    assign rambus_wb_rst_o = active ? buf_rambus_wb_rst_o : 1'b0;
    assign rambus_wb_stb_o = active ? buf_rambus_wb_stb_o : 1'b0;
    assign rambus_wb_cyc_o = active ? buf_rambus_wb_cyc_o : 1'b0;
    assign rambus_wb_we_o  = active ? buf_rambus_wb_we_o  : 1'b0;
    assign rambus_wb_sel_o = active ? buf_rambus_wb_sel_o : 4'b0;
    assign rambus_wb_dat_o = active ? buf_rambus_wb_dat_o : 32'b0;
    assign rambus_wb_adr_o = active ? buf_rambus_wb_adr_o : 10'b0;
    `endif
    `ifdef USE_LA
    assign la1_data_out = active ? buf_la1_data_out  : 32'b0;
    `endif
    `ifdef USE_IO
    assign io_out       = active ? buf_io_out       : {`MPRJ_IO_PADS{1'b0}};
    assign io_oeb       = active ? buf_io_oeb       : {`MPRJ_IO_PADS{1'b0}};
    `endif
    `ifdef USE_IRQ
    assign user_irq     = active ? buf_user_irq          : 3'b0;
    `endif
    `include "properties.v"
    `else

    
    `ifdef USE_WB
    assign wbs_ack_o    = active ? buf_wbs_ack_o    : 1'bz;
    assign wbs_dat_o    = active ? buf_wbs_dat_o    : 32'bz;
    `endif
    `ifdef USE_SHARED_OPENRAM
    assign rambus_wb_clk_o = active ? buf_rambus_wb_clk_o : 1'bz;
    assign rambus_wb_rst_o = active ? buf_rambus_wb_rst_o : 1'bz;
    assign rambus_wb_stb_o = active ? buf_rambus_wb_stb_o : 1'bz;
    assign rambus_wb_cyc_o = active ? buf_rambus_wb_cyc_o : 1'bz;
    assign rambus_wb_we_o  = active ? buf_rambus_wb_we_o  : 1'bz;
    assign rambus_wb_sel_o = active ? buf_rambus_wb_sel_o : 4'bz;
    assign rambus_wb_dat_o = active ? buf_rambus_wb_dat_o : 32'bz;
    assign rambus_wb_adr_o = active ? buf_rambus_wb_adr_o : 10'bz;
    `endif
    `ifdef USE_LA
    assign la1_data_out  = active ? buf_la1_data_out  : 32'bz;
    assign la2_data_out  = active ? buf_la2_data_out  : 32'bz;
    assign la3_data_out  = active ? buf_la3_data_out  : 32'bz;
    `endif
    `ifdef USE_IO
    assign io_out       = active ? buf_io_out       : {`MPRJ_IO_PADS{1'bz}};
    assign io_oeb       = active ? buf_io_oeb       : {`MPRJ_IO_PADS{1'bz}};
    `endif
    `ifdef USE_IRQ
    assign user_irq     = active ? buf_user_irq          : 3'bz;
    `endif
    `endif


    `ifdef COCOTB_SIM
    initial begin
        $dumpfile ("wrapped_instrumented_adder_behav.vcd");
        $dumpvars (0, wrapped_instrumented_adder_behav);
        #1;
    end
    `endif


    assign buf_io_oeb = {`MPRJ_IO_PADS{1'b0}};

    parameter WIDTH = 32;
    reg [WIDTH-1:0] a_input;
    reg [WIDTH-1:0] b_input;
    reg [WIDTH-1:0] s_output_bit_b;
    reg [WIDTH-1:0] a_input_ext_bit_b;
    reg [WIDTH-1:0] a_input_ring_bit_b;
    wire [WIDTH-1:0] sum_out;
    wire write          = la1_data_in[8];
    wire [3:0] reg_sel  = la1_data_in[12:9];


    always @(posedge wb_clk_i) begin
        if(write)
            case(reg_sel)
            0: a_input            <= la3_data_in;    
            1: b_input            <= la3_data_in;
            2: s_output_bit_b     <= la3_data_in;
            3: a_input_ext_bit_b  <= la3_data_in;
            4: a_input_ring_bit_b <= la3_data_in;
            endcase
    end 

    assign buf_la3_data_out = reg_sel == 0 ? a_input :
                              reg_sel == 1 ? b_input :
                              reg_sel == 2 ? s_output_bit_b :
                              reg_sel == 3 ? a_input_ext_bit_b :
                              reg_sel == 4 ? a_input_ring_bit_b :
                                             sum_out;

    instrumented_adder instrumented_adder(

    .clk                    (wb_clk_i),
    .reset                  (la1_data_in[0]),


    .stop_b                 (la1_data_in[1]),
    .extra_inverter         (la1_data_in[2]),
    .bypass_b               (la1_data_in[3]),
    .control_b              (la1_data_in[4]),
    .a_input_ext_bit_b      (a_input_ext_bit_b),
    .a_input_ring_bit_b     (a_input_ring_bit_b),
    .s_output_bit_b         (s_output_bit_b),


    .counter_enable         (la1_data_in[5]),
    .counter_load           (la1_data_in[6]),
    .force_count            (la1_data_in[7]),
    .integration_time       (la2_data_in),
    

    .a_input                (a_input),
    .b_input                (b_input),



    .sum_out                (sum_out),
    .done                   (buf_la1_data_out[0]),
    .ring_osc_counter_out   (buf_la2_data_out)
    );

    assign buf_io_out[8] = la1_data_in[1];
    assign buf_io_out[9] = buf_la2_data_out[3];
    assign buf_io_out[10]= buf_la1_data_out[0];

endmodule
module wrapped_instrumented_adder_behav(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif
    input wire wb_clk_i,

`ifdef USE_WB
    input wire          wb_rst_i,
    input wire          wbs_stb_i,
    input wire          wbs_cyc_i,
    input wire          wbs_we_i,
    input wire [3:0]    wbs_sel_i,
    input wire [31:0]   wbs_dat_i,
    input wire [31:0]   wbs_adr_i,
    inout wire          wbs_ack_o,
    inout wire [31:0]   wbs_dat_o,
`endif


`ifdef USE_SHARED_OPENRAM
    inout wire          rambus_wb_clk_o,
    inout wire          rambus_wb_rst_o,
    inout wire          rambus_wb_stb_o,
    inout wire          rambus_wb_cyc_o,
    inout wire          rambus_wb_we_o,
    inout wire [3:0]    rambus_wb_sel_o,
    inout wire [31:0]   rambus_wb_dat_o,
    inout wire [9:0]    rambus_wb_adr_o,
    input wire          rambus_wb_ack_i,
    input wire [31:0]   rambus_wb_dat_i,
`endif



`ifdef USE_LA
    input wire [31:0]   la1_data_in,
    inout wire [31:0]   la1_data_out,
    input wire [31:0]   la1_oenb,
    input wire [31:0]   la2_data_in,
    inout wire [31:0]   la2_data_out,
    input wire [31:0]   la2_oenb,
    input wire [31:0]   la3_data_in,
    inout wire [31:0]   la3_data_out,
    input wire [31:0]   la3_oenb,
`endif


`ifdef USE_IO
    input wire [`MPRJ_IO_PADS-1:0] io_in,
    inout wire [`MPRJ_IO_PADS-1:0] io_out,
    inout wire [`MPRJ_IO_PADS-1:0] io_oeb,
`endif


`ifdef USE_IRQ
    inout wire [2:0] user_irq,
`endif

`ifdef USE_CLK2

    input wire user_clock2,
`endif
    

    input wire active
);



    wire                        buf_wbs_ack_o;
    wire [31:0]                 buf_wbs_dat_o;
    wire [31:0]                 buf_la1_data_out;
    wire [31:0]                 buf_la2_data_out;
    wire [31:0]                 buf_la3_data_out;
    wire [`MPRJ_IO_PADS-1:0]    buf_io_out;
    wire [`MPRJ_IO_PADS-1:0]    buf_io_oeb;
    wire [2:0]                  buf_user_irq;
    wire                        buf_rambus_wb_clk_o;
    wire                        buf_rambus_wb_rst_o;
    wire                        buf_rambus_wb_stb_o;
    wire                        buf_rambus_wb_cyc_o;
    wire                        buf_rambus_wb_we_o;
    wire [3:0]                  buf_rambus_wb_sel_o;
    wire [31:0]                 buf_rambus_wb_dat_o;
    wire [9:0]                  buf_rambus_wb_adr_o;

    `ifdef FORMAL

    `ifdef USE_WB
    assign wbs_ack_o    = active ? buf_wbs_ack_o    : 1'b0;
    assign wbs_dat_o    = active ? buf_wbs_dat_o    : 32'b0;
    `endif
    `ifdef USE_SHARED_OPENRAM
    assign rambus_wb_clk_o = active ? buf_rambus_wb_clk_o : 1'b0;
    assign rambus_wb_rst_o = active ? buf_rambus_wb_rst_o : 1'b0;
    assign rambus_wb_stb_o = active ? buf_rambus_wb_stb_o : 1'b0;
    assign rambus_wb_cyc_o = active ? buf_rambus_wb_cyc_o : 1'b0;
    assign rambus_wb_we_o  = active ? buf_rambus_wb_we_o  : 1'b0;
    assign rambus_wb_sel_o = active ? buf_rambus_wb_sel_o : 4'b0;
    assign rambus_wb_dat_o = active ? buf_rambus_wb_dat_o : 32'b0;
    assign rambus_wb_adr_o = active ? buf_rambus_wb_adr_o : 10'b0;
    `endif
    `ifdef USE_LA
    assign la1_data_out = active ? buf_la1_data_out  : 32'b0;
    `endif
    `ifdef USE_IO
    assign io_out       = active ? buf_io_out       : {`MPRJ_IO_PADS{1'b0}};
    assign io_oeb       = active ? buf_io_oeb       : {`MPRJ_IO_PADS{1'b0}};
    `endif
    `ifdef USE_IRQ
    assign user_irq     = active ? buf_user_irq          : 3'b0;
    `endif
    `include "properties.v"
    `else

    
    `ifdef USE_WB
    assign wbs_ack_o    = active ? buf_wbs_ack_o    : 1'bz;
    assign wbs_dat_o    = active ? buf_wbs_dat_o    : 32'bz;
    `endif
    `ifdef USE_SHARED_OPENRAM
    assign rambus_wb_clk_o = active ? buf_rambus_wb_clk_o : 1'bz;
    assign rambus_wb_rst_o = active ? buf_rambus_wb_rst_o : 1'bz;
    assign rambus_wb_stb_o = active ? buf_rambus_wb_stb_o : 1'bz;
    assign rambus_wb_cyc_o = active ? buf_rambus_wb_cyc_o : 1'bz;
    assign rambus_wb_we_o  = active ? buf_rambus_wb_we_o  : 1'bz;
    assign rambus_wb_sel_o = active ? buf_rambus_wb_sel_o : 4'bz;
    assign rambus_wb_dat_o = active ? buf_rambus_wb_dat_o : 32'bz;
    assign rambus_wb_adr_o = active ? buf_rambus_wb_adr_o : 10'bz;
    `endif
    `ifdef USE_LA
    assign la1_data_out  = active ? buf_la1_data_out  : 32'bz;
    assign la2_data_out  = active ? buf_la2_data_out  : 32'bz;
    assign la3_data_out  = active ? buf_la3_data_out  : 32'bz;
    `endif
    `ifdef USE_IO
    assign io_out       = active ? buf_io_out       : {`MPRJ_IO_PADS{1'bz}};
    assign io_oeb       = active ? buf_io_oeb       : {`MPRJ_IO_PADS{1'bz}};
    `endif
    `ifdef USE_IRQ
    assign user_irq     = active ? buf_user_irq          : 3'bz;
    `endif
    `endif


    `ifdef COCOTB_SIM
    initial begin
        $dumpfile ("wrapped_instrumented_adder_behav.vcd");
        $dumpvars (0, wrapped_instrumented_adder_behav);
        #1;
    end
    `endif


    assign buf_io_oeb = {`MPRJ_IO_PADS{1'b0}};

    parameter WIDTH = 32;
    reg [WIDTH-1:0] a_input;
    reg [WIDTH-1:0] b_input;
    reg [WIDTH-1:0] s_output_bit_b;
    reg [WIDTH-1:0] a_input_ext_bit_b;
    reg [WIDTH-1:0] a_input_ring_bit_b;
    wire [WIDTH-1:0] sum_out;
    wire write          = la1_data_in[8];
    wire [3:0] reg_sel  = la1_data_in[12:9];


    always @(posedge wb_clk_i) begin
        if(write)
            case(reg_sel)
            0: a_input            <= la3_data_in;    
            1: b_input            <= la3_data_in;
            2: s_output_bit_b     <= la3_data_in;
            3: a_input_ext_bit_b  <= la3_data_in;
            4: a_input_ring_bit_b <= la3_data_in;
            endcase
    end 

    assign buf_la3_data_out = reg_sel == 0 ? a_input :
                              reg_sel == 1 ? b_input :
                              reg_sel == 2 ? s_output_bit_b :
                              reg_sel == 3 ? a_input_ext_bit_b :
                              reg_sel == 4 ? a_input_ring_bit_b :
                                             sum_out;

    instrumented_adder instrumented_adder(

    .clk                    (wb_clk_i),
    .reset                  (la1_data_in[0]),


    .stop_b                 (la1_data_in[1]),
    .extra_inverter         (la1_data_in[2]),
    .bypass_b               (la1_data_in[3]),
    .control_b              (la1_data_in[4]),
    .a_input_ext_bit_b      (a_input_ext_bit_b),
    .a_input_ring_bit_b     (a_input_ring_bit_b),
    .s_output_bit_b         (s_output_bit_b),


    .counter_enable         (la1_data_in[5]),
    .counter_load           (la1_data_in[6]),
    .force_count            (la1_data_in[7]),
    .integration_time       (la2_data_in),
    

    .a_input                (a_input),
    .b_input                (b_input),



    .sum_out                (sum_out),
    .done                   (buf_la1_data_out[0]),
    .ring_osc_counter_out   (buf_la2_data_out)
    );

    assign buf_io_out[8] = la1_data_in[1];
    assign buf_io_out[9] = buf_la2_data_out[3];
    assign buf_io_out[10]= buf_la1_data_out[0];

endmodule