data/full_repos/permissive/47537295/src/debouncer.v
1: b'%Warning-WIDTH: data/full_repos/permissive/47537295/src/debouncer.v:37: Operator ADD expects 18 bits on the RHS, but RHS\'s CONST \'2\'h1\' generates 2 bits.\n                                                                      : ... In instance debouncer\n  if (btn != ol) cnt <= cnt + 2\'b1;\n                            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module debouncer(
    input btn,
    input clk,
    output ol,
    output op
    );
	 reg [17:0] cnt;
	 reg temp_ol=0;
	 reg temp_op=0;
	 parameter cycles=262143;
	 assign ol = temp_ol;
	 assign op = temp_op;
	 
	always @(posedge clk)
	begin
		temp_op <= 0;
		if (btn != ol) cnt <= cnt + 2'b1;
		else cnt <= 0;
		if (cnt == cycles) begin
			temp_ol <= btn;
			if (ol == 0) temp_op <= 1;
		end
	end

endmodule
module debouncer(
    input btn,
    input clk,
    output ol,
    output op
    );

	 reg [17:0] cnt;
	 reg temp_ol=0;
	 reg temp_op=0;
	 parameter cycles=262143;
	 assign ol = temp_ol;
	 assign op = temp_op;
	 
	always @(posedge clk)
	begin
		temp_op <= 0;
		if (btn != ol) cnt <= cnt + 2'b1;
		else cnt <= 0;
		if (cnt == cycles) begin
			temp_ol <= btn;
			if (ol == 0) temp_op <= 1;
		end
	end

endmodule