data/full_repos/permissive/446997925/hw3/alu_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/446997925/hw3/alu_testbench.v:16: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/446997925/hw3/alu_testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/446997925/hw3/alu_testbench.v:29: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/446997925/hw3/alu_testbench.v:36: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/446997925/hw3/alu_testbench.v:43: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/446997925/hw3/alu_testbench.v:48: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/446997925/hw3/alu_testbench.v:51: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/446997925/hw3/alu_testbench.v:56: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/446997925/hw3/alu_testbench.v:60: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/446997925/hw3/alu_testbench.v:65: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Error: data/full_repos/permissive/446997925/hw3/alu_testbench.v:70: Unsupported or unknown PLI call: $monitor\n$monitor("time = %d, a =%32b, b=%32b, sel=%3b, out=%32b", $time, a, b, opt, out);\n^~~~~~~~\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu_testbench();

reg [31:0] a, b;
reg [2:0] opt;
wire [31:0] out;

alu alu_test(a [31:0],b [31:0],opt,out[31:0]);

initial begin

a = 32'd2;
b = 32'd6;
opt = 3'b000;

#`DELAY;

a = 32'd15;
b = 32'd3;
opt = 3'b010;

#`DELAY;

a = 32'b00000000_00000000_00000000_10101010;
b = 32'b00000000_00000000_11111111_11111111;
opt = 3'b110;


#`DELAY;

a = 32'b00000000_00000000_00000000_10101010;
b = 32'b00000000_00000000_11111111_11111111;
opt = 3'b111;


#`DELAY;

a = 32'b00000000_00000000_00000000_10101010;
b = 32'b00000000_00000000_11111111_11111111;
opt = 3'b001;


#`DELAY;

a = 32'd5;
b = 32'd8;
opt = 3'b011;
#`DELAY;


#`DELAY;

a = 32'd5;
b = 32'd8;
opt = 3'b100;
#`DELAY;



#`DELAY;

a = 32'd5;
b = 32'd8;
opt = 3'b101;
#`DELAY;

end
initial
begin
$monitor("time = %d, a =%32b, b=%32b, sel=%3b, out=%32b", $time, a, b, opt, out);
end


endmodule
module alu_testbench();


reg [31:0] a, b;
reg [2:0] opt;
wire [31:0] out;

alu alu_test(a [31:0],b [31:0],opt,out[31:0]);

initial begin

a = 32'd2;
b = 32'd6;
opt = 3'b000;

#`DELAY;

a = 32'd15;
b = 32'd3;
opt = 3'b010;

#`DELAY;

a = 32'b00000000_00000000_00000000_10101010;
b = 32'b00000000_00000000_11111111_11111111;
opt = 3'b110;


#`DELAY;

a = 32'b00000000_00000000_00000000_10101010;
b = 32'b00000000_00000000_11111111_11111111;
opt = 3'b111;


#`DELAY;

a = 32'b00000000_00000000_00000000_10101010;
b = 32'b00000000_00000000_11111111_11111111;
opt = 3'b001;


#`DELAY;

a = 32'd5;
b = 32'd8;
opt = 3'b011;
#`DELAY;


#`DELAY;

a = 32'd5;
b = 32'd8;
opt = 3'b100;
#`DELAY;



#`DELAY;

a = 32'd5;
b = 32'd8;
opt = 3'b101;
#`DELAY;

end
initial
begin
$monitor("time = %d, a =%32b, b=%32b, sel=%3b, out=%32b", $time, a, b, opt, out);
end


endmodule