data/full_repos/permissive/427281804/FPU/verilog/bsl_tb.v
1: b'%Error: data/full_repos/permissive/427281804/FPU/verilog/bsl_tb.v:8: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("bsl_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/427281804/FPU/verilog/bsl_tb.v:9: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/427281804/FPU/verilog/bsl_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n    #1 a=a+1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/427281804/FPU/verilog/bsl_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #1 a=a+1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/427281804/FPU/verilog/bsl_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #1 a=a+1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/427281804/FPU/verilog/bsl_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #1 a=a+1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/427281804/FPU/verilog/bsl_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #1 a=a+1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/427281804/FPU/verilog/bsl_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #1 a=a+1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/427281804/FPU/verilog/bsl_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #1 a=a+1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/427281804/FPU/verilog/bsl_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #1 a=a+1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/427281804/FPU/verilog/bsl_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #1 a=a+1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/427281804/FPU/verilog/bsl_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #1 a=a+1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/427281804/FPU/verilog/bsl_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #1 a=a+1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/427281804/FPU/verilog/bsl_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #1 a=a+1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/427281804/FPU/verilog/bsl_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #1 a=a+1;\n    ^\n%Error: Exiting due to 2 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bsl_tb;

reg [4:0] a;
reg [31:0] b;
initial begin
    $dumpfile("bsl_tb.vcd");
    $dumpvars;
    a = 0;
    b = 32'hDEADBEEF;
    #1 a=a+1;
    #1 a=a+1;
    #1 a=a+1;
    #1 a=a+1;
    #1 a=a+1;
    #1 a=a+1;
    #1 a=a+1;
    #1 a=a+1;
    #1 a=a+1;
    #1 a=a+1;
    #1 a=a+1;
    #1 a=a+1;
    #1 a=a+1;
    $finish;
end

wire [31:0] dout_sr;
wire [31:0] dout_sr_ref = b>>a;
wire [31:0] dout_sl;
wire [31:0] dout_sl_ref = b<<a;

bsr #(.SWIDTH(5)) dur(
    .din(b),
    .s(a),
    .filler(1'b0),
    .dout(dout_sr)
);

bsl #(.SWIDTH(5)) dul(
    .din(b),
    .s(a),
    .filler(1'b0),
    .dout(dout_sl)
);

endmodule
module bsl_tb;


reg [4:0] a;
reg [31:0] b;
initial begin
    $dumpfile("bsl_tb.vcd");
    $dumpvars;
    a = 0;
    b = 32'hDEADBEEF;
    #1 a=a+1;
    #1 a=a+1;
    #1 a=a+1;
    #1 a=a+1;
    #1 a=a+1;
    #1 a=a+1;
    #1 a=a+1;
    #1 a=a+1;
    #1 a=a+1;
    #1 a=a+1;
    #1 a=a+1;
    #1 a=a+1;
    #1 a=a+1;
    $finish;
end

wire [31:0] dout_sr;
wire [31:0] dout_sr_ref = b>>a;
wire [31:0] dout_sl;
wire [31:0] dout_sl_ref = b<<a;

bsr #(.SWIDTH(5)) dur(
    .din(b),
    .s(a),
    .filler(1'b0),
    .dout(dout_sr)
);

bsl #(.SWIDTH(5)) dul(
    .din(b),
    .s(a),
    .filler(1'b0),
    .dout(dout_sl)
);

endmodule