data/full_repos/permissive/493019833/test/testcase/firrtl/Mux4/reference/Mux4.v
data/verilator_xmls/a85de39e-363e-4cff-9f06-ff1e5ce00174.xml
module BITWISENOT(y, in);
    parameter width = 4;
    output [width-1:0] y;
    input [width-1:0] in;
    assign y = ~in;
endmodule
module BITWISENOT(y, in);

    parameter width = 4;
    output [width-1:0] y;
    input [width-1:0] in;
    assign y = ~in;
endmodule