data/full_repos/permissive/49387115/rtl/verilog/GPIA_BYTE.v
1: b"%Error: data/full_repos/permissive/49387115/rtl/verilog/GPIA_BYTE.v:24: Cannot find file containing module: 'GPIA_BIT'\nGPIA_BIT bit0(\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/49387115/rtl/verilog,data/full_repos/permissive/49387115/GPIA_BIT\n             data/full_repos/permissive/49387115/rtl/verilog,data/full_repos/permissive/49387115/GPIA_BIT.v\n             data/full_repos/permissive/49387115/rtl/verilog,data/full_repos/permissive/49387115/GPIA_BIT.sv\n             GPIA_BIT\n             GPIA_BIT.v\n             GPIA_BIT.sv\n             obj_dir/GPIA_BIT\n             obj_dir/GPIA_BIT.v\n             obj_dir/GPIA_BIT.sv\n%Error: data/full_repos/permissive/49387115/rtl/verilog/GPIA_BYTE.v:33: Cannot find file containing module: 'GPIA_BIT'\nGPIA_BIT bit1(\n^~~~~~~~\n%Error: data/full_repos/permissive/49387115/rtl/verilog/GPIA_BYTE.v:42: Cannot find file containing module: 'GPIA_BIT'\nGPIA_BIT bit2(\n^~~~~~~~\n%Error: data/full_repos/permissive/49387115/rtl/verilog/GPIA_BYTE.v:51: Cannot find file containing module: 'GPIA_BIT'\nGPIA_BIT bit3(\n^~~~~~~~\n%Error: data/full_repos/permissive/49387115/rtl/verilog/GPIA_BYTE.v:60: Cannot find file containing module: 'GPIA_BIT'\nGPIA_BIT bit4(\n^~~~~~~~\n%Error: data/full_repos/permissive/49387115/rtl/verilog/GPIA_BYTE.v:69: Cannot find file containing module: 'GPIA_BIT'\nGPIA_BIT bit5(\n^~~~~~~~\n%Error: data/full_repos/permissive/49387115/rtl/verilog/GPIA_BYTE.v:78: Cannot find file containing module: 'GPIA_BIT'\nGPIA_BIT bit6(\n^~~~~~~~\n%Error: data/full_repos/permissive/49387115/rtl/verilog/GPIA_BYTE.v:87: Cannot find file containing module: 'GPIA_BIT'\nGPIA_BIT bit7(\n^~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module GPIA_BYTE(
	input	clk_i,
	input	res_i,
	input	[1:0] mode_i,
	input	[7:0] d_i,
	input	stb_i,

	output	[7:0] q_o
);

GPIA_BIT bit0(
	.clk_i(clk_i),
	.res_i(res_i),
	.mode_i(mode_i),
	.d_i(d_i[0]),
	.stb_i(stb_i),
	.q_o(q_o[0])
);

GPIA_BIT bit1(
	.clk_i(clk_i),
	.res_i(res_i),
	.mode_i(mode_i),
	.d_i(d_i[1]),
	.stb_i(stb_i),
	.q_o(q_o[1])
);

GPIA_BIT bit2(
	.clk_i(clk_i),
	.res_i(res_i),
	.mode_i(mode_i),
	.d_i(d_i[2]),
	.stb_i(stb_i),
	.q_o(q_o[2])
);

GPIA_BIT bit3(
	.clk_i(clk_i),
	.res_i(res_i),
	.mode_i(mode_i),
	.d_i(d_i[3]),
	.stb_i(stb_i),
	.q_o(q_o[3])
);

GPIA_BIT bit4(
	.clk_i(clk_i),
	.res_i(res_i),
	.mode_i(mode_i),
	.d_i(d_i[4]),
	.stb_i(stb_i),
	.q_o(q_o[4])
);

GPIA_BIT bit5(
	.clk_i(clk_i),
	.res_i(res_i),
	.mode_i(mode_i),
	.d_i(d_i[5]),
	.stb_i(stb_i),
	.q_o(q_o[5])
);

GPIA_BIT bit6(
	.clk_i(clk_i),
	.res_i(res_i),
	.mode_i(mode_i),
	.d_i(d_i[6]),
	.stb_i(stb_i),
	.q_o(q_o[6])
);

GPIA_BIT bit7(
	.clk_i(clk_i),
	.res_i(res_i),
	.mode_i(mode_i),
	.d_i(d_i[7]),
	.stb_i(stb_i),
	.q_o(q_o[7])
);

endmodule
module GPIA_BYTE(
	input	clk_i,
	input	res_i,
	input	[1:0] mode_i,
	input	[7:0] d_i,
	input	stb_i,

	output	[7:0] q_o
);


GPIA_BIT bit0(
	.clk_i(clk_i),
	.res_i(res_i),
	.mode_i(mode_i),
	.d_i(d_i[0]),
	.stb_i(stb_i),
	.q_o(q_o[0])
);

GPIA_BIT bit1(
	.clk_i(clk_i),
	.res_i(res_i),
	.mode_i(mode_i),
	.d_i(d_i[1]),
	.stb_i(stb_i),
	.q_o(q_o[1])
);

GPIA_BIT bit2(
	.clk_i(clk_i),
	.res_i(res_i),
	.mode_i(mode_i),
	.d_i(d_i[2]),
	.stb_i(stb_i),
	.q_o(q_o[2])
);

GPIA_BIT bit3(
	.clk_i(clk_i),
	.res_i(res_i),
	.mode_i(mode_i),
	.d_i(d_i[3]),
	.stb_i(stb_i),
	.q_o(q_o[3])
);

GPIA_BIT bit4(
	.clk_i(clk_i),
	.res_i(res_i),
	.mode_i(mode_i),
	.d_i(d_i[4]),
	.stb_i(stb_i),
	.q_o(q_o[4])
);

GPIA_BIT bit5(
	.clk_i(clk_i),
	.res_i(res_i),
	.mode_i(mode_i),
	.d_i(d_i[5]),
	.stb_i(stb_i),
	.q_o(q_o[5])
);

GPIA_BIT bit6(
	.clk_i(clk_i),
	.res_i(res_i),
	.mode_i(mode_i),
	.d_i(d_i[6]),
	.stb_i(stb_i),
	.q_o(q_o[6])
);

GPIA_BIT bit7(
	.clk_i(clk_i),
	.res_i(res_i),
	.mode_i(mode_i),
	.d_i(d_i[7]),
	.stb_i(stb_i),
	.q_o(q_o[7])
);

endmodule