data/full_repos/permissive/472097485/Chu04/StopWatch_06/ModMCounterWithUD.v
1: b'%Error: data/full_repos/permissive/472097485/Chu04/StopWatch_06/ModMCounterWithUD.v:8: Cannot find file containing module: \'DFFArray\'\n DFFArray #( N ) state( clk, reset, next, count );\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/472097485/Chu04/StopWatch_06,data/full_repos/permissive/472097485/DFFArray\n             data/full_repos/permissive/472097485/Chu04/StopWatch_06,data/full_repos/permissive/472097485/DFFArray.v\n             data/full_repos/permissive/472097485/Chu04/StopWatch_06,data/full_repos/permissive/472097485/DFFArray.sv\n             DFFArray\n             DFFArray.v\n             DFFArray.sv\n             obj_dir/DFFArray\n             obj_dir/DFFArray.v\n             obj_dir/DFFArray.sv\n%Warning-WIDTH: data/full_repos/permissive/472097485/Chu04/StopWatch_06/ModMCounterWithUD.v:11: Operator EQ expects 32 or 2 bits on the LHS, but LHS\'s VARREF \'count\' generates 1 bits.\n                                                                                              : ... In instance ModMCounterWithUD\n assign next = en ? ( up ? ( count == M - 1 ? 0 : count + 1 ) : ( count == 0 ? M - 1 : count - 1 ) ) : count;\n                                   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/472097485/Chu04/StopWatch_06/ModMCounterWithUD.v:11: Operator COND expects 32 or 2 bits on the Conditional False, but Conditional False\'s VARREF \'count\' generates 1 bits.\n                                                                                              : ... In instance ModMCounterWithUD\n assign next = en ? ( up ? ( count == M - 1 ? 0 : count + 1 ) : ( count == 0 ? M - 1 : count - 1 ) ) : count;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/472097485/Chu04/StopWatch_06/ModMCounterWithUD.v:11: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 32 or 2 bits.\n                                                                                              : ... In instance ModMCounterWithUD\n assign next = en ? ( up ? ( count == M - 1 ? 0 : count + 1 ) : ( count == 0 ? M - 1 : count - 1 ) ) : count;\n             ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module ModMCounterWithUD #( parameter M = 2, parameter N = 1 )( input clk, input reset, input en, input up, output [N-1:0] count );

	wire [N-1:0] next;

	DFFArray #( N ) state( clk, reset, next, count );


	assign next = en ? ( up ? ( count == M - 1 ? 0 : count + 1 ) : ( count == 0 ? M - 1 : count - 1 ) ) : count;

endmodule
module ModMCounterWithUD #( parameter M = 2, parameter N = 1 )( input clk, input reset, input en, input up, output [N-1:0] count );


	wire [N-1:0] next;

	DFFArray #( N ) state( clk, reset, next, count );


	assign next = en ? ( up ? ( count == M - 1 ? 0 : count + 1 ) : ( count == 0 ? M - 1 : count - 1 ) ) : count;

endmodule