data/full_repos/permissive/474294847/rtl-tests/IO/btn-debounce-tb.v
1: b'%Error: data/full_repos/permissive/474294847/rtl-tests/IO/btn-debounce-tb.v:1: Cannot find include file: btn-debounce.v\n`include "btn-debounce.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/474294847/rtl-tests/IO,data/full_repos/permissive/474294847/btn-debounce.v\n             data/full_repos/permissive/474294847/rtl-tests/IO,data/full_repos/permissive/474294847/btn-debounce.v.v\n             data/full_repos/permissive/474294847/rtl-tests/IO,data/full_repos/permissive/474294847/btn-debounce.v.sv\n             btn-debounce.v\n             btn-debounce.v.v\n             btn-debounce.v.sv\n             obj_dir/btn-debounce.v\n             obj_dir/btn-debounce.v.v\n             obj_dir/btn-debounce.v.sv\n%Error: data/full_repos/permissive/474294847/rtl-tests/IO/btn-debounce-tb.v:17: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("./build/rtl-sim/vcd/btn-debounce.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/474294847/rtl-tests/IO/btn-debounce-tb.v:18: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/474294847/rtl-tests/IO/btn-debounce-tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/474294847/rtl-tests/IO/btn-debounce-tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module btn_debounce_tb;

reg raw_input, clk;
wire btn_pulse;
integer i;

btn_debounce dut
(
    raw_input, clk, btn_pulse
);


initial
begin
    $dumpfile("./build/rtl-sim/vcd/btn-debounce.vcd");
    $dumpvars;
end

initial
begin
    for (i = 0; i < 64; i = i + 1)
    begin
        if (i == 16)
            raw_input = 1;
        else
            raw_input = 0;
        
        clk = 0;
        #100;
        clk = 1;
        #100;
    end
end


endmodule
module btn_debounce_tb;


reg raw_input, clk;
wire btn_pulse;
integer i;

btn_debounce dut
(
    raw_input, clk, btn_pulse
);


initial
begin
    $dumpfile("./build/rtl-sim/vcd/btn-debounce.vcd");
    $dumpvars;
end

initial
begin
    for (i = 0; i < 64; i = i + 1)
    begin
        if (i == 16)
            raw_input = 1;
        else
            raw_input = 0;
        
        clk = 0;
        #100;
        clk = 1;
        #100;
    end
end


endmodule