data/full_repos/permissive/51625123/src/scores2.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/51625123/src/scores2.v:166: Multiple top level modules\n                                                                        : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                        : ... Top module \'scores\'\nmodule scores(clk, neglineclk, realx, realy, score_addA, score_addB, score_reset, scoreA, scoreB, score_scan);\n       ^~~~~~\n                                                                        : ... Top module \'mux2x4\'\nmodule mux2x4(sel, d0, d1, d2, d3, q);\n       ^~~~~~\n                                                                        : ... Top module \'counter_mod8\'\nmodule counter_mod8(c, r, q, cout);\n       ^~~~~~~~~~~~\n                                                                        : ... Top module \'counter_mod4\'\nmodule counter_mod4(c, r, q, cout);\n       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/51625123/src/scores2.v:113: Cannot find file containing module: \'scorecopymux\'\nscorecopymux scorecopymux(score0, score1, score2, score3, textadr, textd);\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/51625123/src,data/full_repos/permissive/51625123/scorecopymux\n             data/full_repos/permissive/51625123/src,data/full_repos/permissive/51625123/scorecopymux.v\n             data/full_repos/permissive/51625123/src,data/full_repos/permissive/51625123/scorecopymux.sv\n             scorecopymux\n             scorecopymux.v\n             scorecopymux.sv\n             obj_dir/scorecopymux\n             obj_dir/scorecopymux.v\n             obj_dir/scorecopymux.sv\n%Warning-WIDTH: data/full_repos/permissive/51625123/src/scores2.v:172: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s CONST \'2\'h1\' generates 2 bits.\n                                                                     : ... In instance mux2x4\n       2\'b01 ? d1 :\n             ^\n%Warning-WIDTH: data/full_repos/permissive/51625123/src/scores2.v:173: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s CONST \'2\'h2\' generates 2 bits.\n                                                                     : ... In instance mux2x4\n       2\'b10 ? d2 : d3;\n             ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module scores(clk, neglineclk, realx, realy, score_addA, score_addB, score_reset, scoreA, scoreB, score_scan);
input clk;
input neglineclk;
input [9:0] realx, realy;
input score_addA, score_addB, score_reset;
output [7:0]scoreA, scoreB;
output score_scan;


wire scout1, scout2, scout3, scout4;
wire [3:0] score0;
wire [3:0] score1;
wire [3:0] score2;
wire [3:0] score3;
bcdcounterx bcdcounter1(score_reset,	score_addA, scout1, score1);
bcdcounterx bcdcounter2(score_reset,	scout1, scout2, score0);

bcdcounterx bcdcounter3(score_reset,	score_addB, scout3, score3);
bcdcounterx bcdcounter4(score_reset,	scout3, scout4, score2);

reg [7:0] scoreA, scoreB;
always @(score0 or score1 or score2 or score3) begin
	scoreA <= {score0,score1};
	scoreB <= {score2,score3};
end

parameter XSTART = 640/2-3*8*4;
parameter YSTART = 6*8;

reg rscxr;
wire scxr = rscxr;
always @(negedge clk) begin
	if (realx == XSTART) rscxr <= 1;
	else rscxr <= 0;
end

wire newline = !neglineclk;
wire scyr = realy == YSTART;

reg [7:0] xwide;
always @(posedge clk) begin
	if (scxr) 
		xwide <= 6*8*4;
	else
		if (xwide > 0) xwide <= xwide - 1;
end

wire display_ax = xwide != 0;
wire display_ay = realy >= YSTART && realy < YSTART+5*8;

wire displayactive = display_ax & display_ay & skippy;



reg skippy;
always @(posedge clk) begin
	if (realx == XSTART + 2*8*4) begin
		skippy <= 0;
	end else if (realx == XSTART + 4*8*4) begin
		skippy <= 1;
	end
end

wire [3:0] dummy;
wire [1:0] bitnumber;
wire [1:0] textadr;
unicounter unicounter(clk, scxr, skippy & display_ax, dummy[2:0], bitnumber, textadr);

wire [2:0] y;
unicounter ycounter(newline, scyr, display_ay, dummy[2:0], y[1:0], {dummy[0],y[2]});


wire [3:0] textd;

scorecopymux scorecopymux(score0, score1, score2, score3, textadr, textd);


wire [3:0] pixels;
charrom charrom(clk, charcode, y, pixels);


wire [3:0] charcode;
textramx displaymem(clk, textd, textadr, charcode);

reg sscan;
always @(posedge clk) begin
	sscan <= displayactive & pixels[bitnumber];
end
assign score_scan = sscan;


endmodule
module scores(clk, neglineclk, realx, realy, score_addA, score_addB, score_reset, scoreA, scoreB, score_scan);

input clk;
input neglineclk;
input [9:0] realx, realy;
input score_addA, score_addB, score_reset;
output [7:0]scoreA, scoreB;
output score_scan;


wire scout1, scout2, scout3, scout4;
wire [3:0] score0;
wire [3:0] score1;
wire [3:0] score2;
wire [3:0] score3;
bcdcounterx bcdcounter1(score_reset,	score_addA, scout1, score1);
bcdcounterx bcdcounter2(score_reset,	scout1, scout2, score0);

bcdcounterx bcdcounter3(score_reset,	score_addB, scout3, score3);
bcdcounterx bcdcounter4(score_reset,	scout3, scout4, score2);

reg [7:0] scoreA, scoreB;
always @(score0 or score1 or score2 or score3) begin
	scoreA <= {score0,score1};
	scoreB <= {score2,score3};
end

parameter XSTART = 640/2-3*8*4;
parameter YSTART = 6*8;

reg rscxr;
wire scxr = rscxr;
always @(negedge clk) begin
	if (realx == XSTART) rscxr <= 1;
	else rscxr <= 0;
end

wire newline = !neglineclk;
wire scyr = realy == YSTART;

reg [7:0] xwide;
always @(posedge clk) begin
	if (scxr) 
		xwide <= 6*8*4;
	else
		if (xwide > 0) xwide <= xwide - 1;
end

wire display_ax = xwide != 0;
wire display_ay = realy >= YSTART && realy < YSTART+5*8;

wire displayactive = display_ax & display_ay & skippy;



reg skippy;
always @(posedge clk) begin
	if (realx == XSTART + 2*8*4) begin
		skippy <= 0;
	end else if (realx == XSTART + 4*8*4) begin
		skippy <= 1;
	end
end

wire [3:0] dummy;
wire [1:0] bitnumber;
wire [1:0] textadr;
unicounter unicounter(clk, scxr, skippy & display_ax, dummy[2:0], bitnumber, textadr);

wire [2:0] y;
unicounter ycounter(newline, scyr, display_ay, dummy[2:0], y[1:0], {dummy[0],y[2]});


wire [3:0] textd;

scorecopymux scorecopymux(score0, score1, score2, score3, textadr, textd);


wire [3:0] pixels;
charrom charrom(clk, charcode, y, pixels);


wire [3:0] charcode;
textramx displaymem(clk, textd, textadr, charcode);

reg sscan;
always @(posedge clk) begin
	sscan <= displayactive & pixels[bitnumber];
end
assign score_scan = sscan;


endmodule