data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v
1: b'%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:7: Cannot find include file: define.vh\n`include "define.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src,data/full_repos/permissive/413020148/define.vh\n             data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src,data/full_repos/permissive/413020148/define.vh.v\n             data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src,data/full_repos/permissive/413020148/define.vh.sv\n             define.vh\n             define.vh.v\n             define.vh.sv\n             obj_dir/define.vh\n             obj_dir/define.vh.v\n             obj_dir/define.vh.sv\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:76: Define or directive not defined: \'`D_START_PC\'\n    reg  [31:0] pc             = `D_START_PC;   \n                                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:76: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    reg  [31:0] pc             = `D_START_PC;   \n                                            ^\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:101: Define or directive not defined: \'`PRIV_M\'\n    reg   [1:0] priv           = `PRIV_M;       \n                                 ^~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:101: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    reg   [1:0] priv           = `PRIV_M;       \n                                        ^\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:169: Define or directive not defined: \'`S_INI\'\n    always@(posedge CLK) r_init_stage <= (w_state==`S_INI);\n                                                   ^~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:169: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    always@(posedge CLK) r_init_stage <= (w_state==`S_INI);\n                                                         ^\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:180: Define or directive not defined: \'`S_IF\'\n        if(state==`S_IF && r_if_state==1 && !w_busy) r_if_irl <= w_insn_data[31:16];\n                  ^~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:180: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n        if(state==`S_IF && r_if_state==1 && !w_busy) r_if_irl <= w_insn_data[31:16];\n                        ^~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:181: Define or directive not defined: \'`S_IF\'\n        if(state==`S_IF && w_pagefault==~0) begin r_cpc <= pc; end\n                  ^~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:181: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n        if(state==`S_IF && w_pagefault==~0) begin r_cpc <= pc; end\n                        ^~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:184: Define or directive not defined: \'`S_IF\'\n    wire [1:0] w_if_state = ((!(state==`S_IF || state==`S_CVT)) || w_pagefault!=~0) ? 0 :\n                                       ^~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:184: Define or directive not defined: \'`S_CVT\'\n    wire [1:0] w_if_state = ((!(state==`S_IF || state==`S_CVT)) || w_pagefault!=~0) ? 0 :\n                                                       ^~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:209: Define or directive not defined: \'`OPCODE_OP_FP___\'\n    wire w_nop = (w_ir_t[6:0]==`OPCODE_OP_FP___ ||  \n                               ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:209: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n    wire w_nop = (w_ir_t[6:0]==`OPCODE_OP_FP___ ||  \n                                                ^~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:210: Define or directive not defined: \'`OPCODE_LOAD_FP_\'\n                  w_ir_t[6:0]==`OPCODE_LOAD_FP_ ||  w_ir_t[6:0]==`OPCODE_STORE_FP);\n                               ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:210: Define or directive not defined: \'`OPCODE_STORE_FP\'\n                  w_ir_t[6:0]==`OPCODE_LOAD_FP_ ||  w_ir_t[6:0]==`OPCODE_STORE_FP);\n                                                                 ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:212: Define or directive not defined: \'`RV32_NOP\'\n    wire [31:0] w_ir = (w_nop) ? `RV32_NOP : (w_cinsn) ? w_ir_t : w_ir_org;  \n                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:212: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n    wire [31:0] w_ir = (w_nop) ? `RV32_NOP : (w_cinsn) ? w_ir_t : w_ir_org;  \n                                           ^\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:213: Define or directive not defined: \'`S_CVT\'\n    always@(posedge CLK) if(state == `S_CVT) begin \n                                     ^~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:213: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    always@(posedge CLK) if(state == `S_CVT) begin \n                                           ^\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:216: syntax error, unexpected <=, expecting IDENTIFIER\n        if(!w_busy) r_ir16  <= w_ir_org[31:16];\n                            ^~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:227: Define or directive not defined: \'`S_WB\'\n    wire w_regfile_we = (w_wb_r_enable && state==`S_WB);\n                                                 ^~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:227: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    wire w_regfile_we = (w_wb_r_enable && state==`S_WB);\n                                                      ^\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:230: Define or directive not defined: \'`S_ID\'\n    always @(posedge CLK) if(state == `S_ID) begin\n                                      ^~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:230: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    always @(posedge CLK) if(state == `S_ID) begin\n                                           ^\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:244: Define or directive not defined: \'`OPCODE_SYSTEM__\'\n    wire w_op_priv = (r_ir[ 6: 0]==`OPCODE_SYSTEM__ && r_ir[14:12]==`FUNCT3_PRIV__);\n                                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:244: Define or directive not defined: \'`FUNCT3_PRIV__\'\n    wire w_op_priv = (r_ir[ 6: 0]==`OPCODE_SYSTEM__ && r_ir[14:12]==`FUNCT3_PRIV__);\n                                                                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:245: Define or directive not defined: \'`OPCODE_SYSTEM__\'\n    wire w_op_csr  = (r_ir[ 6: 0]==`OPCODE_SYSTEM__ && r_ir[14:12]!=`FUNCT3_PRIV__);\n                                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:245: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n    wire w_op_csr  = (r_ir[ 6: 0]==`OPCODE_SYSTEM__ && r_ir[14:12]!=`FUNCT3_PRIV__);\n                                                    ^~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:245: Define or directive not defined: \'`FUNCT3_PRIV__\'\n    wire w_op_csr  = (r_ir[ 6: 0]==`OPCODE_SYSTEM__ && r_ir[14:12]!=`FUNCT3_PRIV__);\n                                                                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:246: Define or directive not defined: \'`S_ID\'\n    always @(posedge CLK) if(state == `S_ID) begin       \n                                      ^~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:246: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    always @(posedge CLK) if(state == `S_ID) begin       \n                                           ^\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:247: Define or directive not defined: \'`FUNCT5_AMO_SC__\'\n        r_op_AMO_SC   <= (r_ir[31:27]==`FUNCT5_AMO_SC__);  \n                                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:248: Define or directive not defined: \'`FUNCT5_AMO_LR__\'\n        r_op_AMO_LR   <= (r_ir[31:27]==`FUNCT5_AMO_LR__);  \n                                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:249: Define or directive not defined: \'`OPCODE_LOAD____\'\n        r_op_LOAD     <= (r_ir[ 6: 0]==`OPCODE_LOAD____);  \n                                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:250: Define or directive not defined: \'`OPCODE_STORE___\'\n        r_op_STORE    <= (r_ir[ 6: 0]==`OPCODE_STORE___);  \n                                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:251: Define or directive not defined: \'`OPCODE_AMO_____\'\n        r_op_AMO      <= (r_ir[ 6: 0]==`OPCODE_AMO_____);  \n                                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:252: Define or directive not defined: \'`OPCODE_SYSTEM__\'\n        r_op_SYS      <= (r_ir[ 6: 0]==`OPCODE_SYSTEM__);  \n                                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:253: Define or directive not defined: \'`FUNCT12_ECALL_\'\n        r_op_ECALL    <= (w_op_priv && r_ir[31:20]==`FUNCT12_ECALL_);\n                                                    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:254: Define or directive not defined: \'`FUNCT12_SRET__\'\n        r_op_SRET     <= (w_op_priv && r_ir[31:20]==`FUNCT12_SRET__);\n                                                    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:255: Define or directive not defined: \'`FUNCT12_MRET__\'\n        r_op_MRET     <= (w_op_priv && r_ir[31:20]==`FUNCT12_MRET__);\n                                                    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:256: Define or directive not defined: \'`CSR_MSTATUS\'\n        r_op_CSR_MSTA <= (w_op_csr  && r_ir[31:20]==`CSR_MSTATUS);\n                                                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:257: Define or directive not defined: \'`CSR_SSTATUS\'\n        r_op_CSR_SSTA <= (w_op_csr  && r_ir[31:20]==`CSR_SSTATUS);\n                                                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:273: Define or directive not defined: \'`S_OF\'\n    always @(posedge CLK) if(state == `S_OF) begin\n                                      ^~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:273: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    always @(posedge CLK) if(state == `S_OF) begin\n                                           ^\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:279: Define or directive not defined: \'`OPCODE_OP_IMM__\'\n        r_alu_in2  <= (r_opcode==`OPCODE_OP_IMM__) ? r_imm : w_rrs2;\n                                 ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:280: Define or directive not defined: \'`OPCODE_OP_IMM__\'\n        r_alu_f7   <= (r_opcode==`OPCODE_OP_IMM__) ?\n                                 ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:281: Define or directive not defined: \'`FUNCT3_ADD___\'\n                      ((r_funct3==`FUNCT3_ADD___) ? 0 : r_funct7 & 7\'h20) : r_funct7;;\n                                  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/rvcorem.v:288: Define or directive not defined: \'`S_EX1\'\n    wire        w_ex1 = (state == `S_EX1);\n                                  ^~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module m_alu_a(w_in1, w_in2, w_funct5, r_rslt);
    input wire [31:0]  w_in1, w_in2;
    input wire  [4:0]  w_funct5;
    output reg [31:0]  r_rslt;

    wire signed [31:0] w_sin1 = w_in1;
    wire signed [31:0] w_sin2 = w_in2;

    always@(*) begin
        case(w_funct5)
            `FUNCT5_AMO_LR__ : r_rslt = 0;
            `FUNCT5_AMO_SC__ : r_rslt = w_in1;
            `FUNCT5_AMO_SWAP : r_rslt = w_in1;
            `FUNCT5_AMO_ADD_ : r_rslt = w_in1 + w_in2;
            `FUNCT5_AMO_AND_ : r_rslt = w_in1 & w_in2;
            `FUNCT5_AMO_OR__ : r_rslt = w_in1 | w_in2;
            `FUNCT5_AMO_XOR_ : r_rslt = w_in1 ^ w_in2;
            `FUNCT5_AMO_MIN_ : r_rslt = (w_sin1 < w_sin2) ? w_in1 : w_in2;
            `FUNCT5_AMO_MINU : r_rslt = (w_in1 < w_in2) ? w_in1 : w_in2;
            `FUNCT5_AMO_MAX_ : r_rslt = (w_sin1 > w_sin2) ? w_in1 : w_in2;
            `FUNCT5_AMO_MAXU : r_rslt = (w_in1 > w_in2) ? w_in1 : w_in2;
            default          : r_rslt = 0;
        endcase
    end
endmodule
module m_alu_a(w_in1, w_in2, w_funct5, r_rslt);

    input wire [31:0]  w_in1, w_in2;
    input wire  [4:0]  w_funct5;
    output reg [31:0]  r_rslt;

    wire signed [31:0] w_sin1 = w_in1;
    wire signed [31:0] w_sin2 = w_in2;

    always@(*) begin
        case(w_funct5)
            `FUNCT5_AMO_LR__ : r_rslt = 0;
            `FUNCT5_AMO_SC__ : r_rslt = w_in1;
            `FUNCT5_AMO_SWAP : r_rslt = w_in1;
            `FUNCT5_AMO_ADD_ : r_rslt = w_in1 + w_in2;
            `FUNCT5_AMO_AND_ : r_rslt = w_in1 & w_in2;
            `FUNCT5_AMO_OR__ : r_rslt = w_in1 | w_in2;
            `FUNCT5_AMO_XOR_ : r_rslt = w_in1 ^ w_in2;
            `FUNCT5_AMO_MIN_ : r_rslt = (w_sin1 < w_sin2) ? w_in1 : w_in2;
            `FUNCT5_AMO_MINU : r_rslt = (w_in1 < w_in2) ? w_in1 : w_in2;
            `FUNCT5_AMO_MAX_ : r_rslt = (w_sin1 > w_sin2) ? w_in1 : w_in2;
            `FUNCT5_AMO_MAXU : r_rslt = (w_in1 > w_in2) ? w_in1 : w_in2;
            default          : r_rslt = 0;
        endcase
    end
endmodule