data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/macro/rdygen.v
data/verilator_xmls/6a93ec00-d34a-482b-bcbd-256f7687f481.xml
module rdygen
    (
     rst,
     clk,
     pce_,
     scanmode,
     rdyin,
     rdyout
     );




input   rst;
input   clk;
input   pce_;
input   scanmode;
input   rdyin;
output  rdyout;







wire        cerst;
assign      cerst = rst | pce_;





reg     rdystatic;

always @(posedge clk or posedge cerst)
    if (cerst)    rdystatic <= 1'b0;
    else
        begin

        if(rdyin)   rdystatic <= rdyin;
        else        rdystatic <= rdystatic;
        end

assign rdyout   = rdystatic;

endmodule
module rdygen
    (
     rst,
     clk,
     pce_,
     scanmode,
     rdyin,
     rdyout
     );





input   rst;
input   clk;
input   pce_;
input   scanmode;
input   rdyin;
output  rdyout;







wire        cerst;
assign      cerst = rst | pce_;





reg     rdystatic;

always @(posedge clk or posedge cerst)
    if (cerst)    rdystatic <= 1'b0;
    else
        begin

        if(rdyin)   rdystatic <= rdyin;
        else        rdystatic <= rdystatic;
        end

assign rdyout   = rdystatic;

endmodule