data/full_repos/permissive/461569093/CodesForFSM/A2_RawatA.srcs/sources_1/new/clock.v
data/verilator_xmls/a8ba27a6-be89-4541-b7c9-8b9eb5081efb.xml
module clock
    (
    input wire cclk,
    input wire [31:0] clkscale,
    output reg clk_out
    );
    reg [31:0] clkq = 0;
    
    always@(posedge cclk)
        begin
            clkq = clkq + 1;
                if(clkq>=clkscale)
                    begin
                        clk_out=~clk_out;
                        clkq=0;
                    end
        end
endmodule
module clock
    (
    input wire cclk,
    input wire [31:0] clkscale,
    output reg clk_out
    );

    reg [31:0] clkq = 0;
    
    always@(posedge cclk)
        begin
            clkq = clkq + 1;
                if(clkq>=clkscale)
                    begin
                        clk_out=~clk_out;
                        clkq=0;
                    end
        end
endmodule