data/full_repos/permissive/413230008/Binary-to-BCD/Code/Sources/rca_nbit.v
1: b"%Error: data/full_repos/permissive/413230008/Binary-to-BCD/Code/Sources/rca_nbit.v:41: Cannot find file containing module: 'full_adder'\n            full_adder FA (\n            ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/413230008/Binary-to-BCD/Code/Sources,data/full_repos/permissive/413230008/full_adder\n             data/full_repos/permissive/413230008/Binary-to-BCD/Code/Sources,data/full_repos/permissive/413230008/full_adder.v\n             data/full_repos/permissive/413230008/Binary-to-BCD/Code/Sources,data/full_repos/permissive/413230008/full_adder.sv\n             full_adder\n             full_adder.v\n             full_adder.sv\n             obj_dir/full_adder\n             obj_dir/full_adder.v\n             obj_dir/full_adder.sv\n%Error: Exiting due to 1 error(s)\n"
module rca_nbit
#(parameter n = 4)
(
    input [n-1: 0] x,
    input [n-1: 0] y,
    input c_in,
    output [n - 1: 0] s,
    output c_out
    );
    
    wire [n: 0] c;
    assign c[0] = c_in;
    assign c_out = c[n];
    
    generate 
        genvar k;
        for (k = 0; k < n; k = k+1)
        begin: stage
            full_adder FA (
            .x(x[k]),
            .y(y[k]),
            .c_in(c[k]),
            .s(s[k]),
            .c_out(c[k+1])
            );
        end
    endgenerate
    
    
endmodule
module rca_nbit
#(parameter n = 4)
(
    input [n-1: 0] x,
    input [n-1: 0] y,
    input c_in,
    output [n - 1: 0] s,
    output c_out
    );

    
    wire [n: 0] c;
    assign c[0] = c_in;
    assign c_out = c[n];
    
    generate 
        genvar k;
        for (k = 0; k < n; k = k+1)
        begin: stage
            full_adder FA (
            .x(x[k]),
            .y(y[k]),
            .c_in(c[k]),
            .s(s[k]),
            .c_out(c[k+1])
            );
        end
    endgenerate
    
    
endmodule