data/full_repos/permissive/491934675/ECE251/Mux2in1out/mux221.v
data/verilator_xmls/a3beca5b-e77a-4914-9432-c0f523c6b71f.xml
module mux2in1(
    input sel,
    input [7:0] inA, inB,
    output reg [7:0] out
);

always@(*) begin
    out = sel? inA : inB;
end

endmodule
module mux2in1(
    input sel,
    input [7:0] inA, inB,
    output reg [7:0] out
);


always@(*) begin
    out = sel? inA : inB;
end

endmodule