data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/recv_credit_flow_ctrl.v
1: b'%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/recv_credit_flow_ctrl.v:81: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 13 bits.\n                                                                                                                                                                  : ... In instance recv_credit_flow_ctrl\n        rCplHAmt <= #1 (rMaxRecv>>({2\'b11, CONFIG_CPL_BOUNDARY_SEL}));\n                 ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/recv_credit_flow_ctrl.v:82: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 13 bits.\n                                                                                                                                                                  : ... In instance recv_credit_flow_ctrl\n        rCplDAmt <= #1 (rMaxRecv>>4);\n                 ^~\n%Error: Exiting due to 2 warning(s)\n'
module recv_credit_flow_ctrl
    (
     input        CLK,
     input        RST,
     input [2:0]  CONFIG_MAX_READ_REQUEST_SIZE,
     input [11:0] CONFIG_MAX_CPL_DATA,
     input [7:0]  CONFIG_MAX_CPL_HDR,
     input        CONFIG_CPL_BOUNDARY_SEL,
     input        RX_ENG_RD_DONE,
     input        TX_ENG_RD_REQ_SENT,
     output       RXBUF_SPACE_AVAIL
     );

    reg           rCreditAvail=0;
    reg           rCplDAvail=0;
    reg           rCplHAvail=0;
    reg [12:0]    rMaxRecv=0;
    reg [11:0]    rCplDAmt=0;
    reg [7:0]     rCplHAmt=0;
    reg [11:0]    rCplD=0;
    reg [7:0]     rCplH=0;

    reg           rInfHCred;
    reg           rInfDCred;
    

    assign RXBUF_SPACE_AVAIL = rCreditAvail;


    always @(posedge CLK) begin
        rInfHCred <= (CONFIG_MAX_CPL_HDR == 0);
        rInfDCred <= (CONFIG_MAX_CPL_DATA == 0);
        rMaxRecv <= #1 (13'd128<<CONFIG_MAX_READ_REQUEST_SIZE);
        rCplHAmt <= #1 (rMaxRecv>>({2'b11, CONFIG_CPL_BOUNDARY_SEL}));
        rCplDAmt <= #1 (rMaxRecv>>4);
        rCplHAvail <= #1 (rCplH <= CONFIG_MAX_CPL_HDR);
        rCplDAvail <= #1 (rCplD <= CONFIG_MAX_CPL_DATA);
        rCreditAvail <= #1 ((rCplHAvail|rInfHCred) & (rCplDAvail | rInfDCred));
    end


    always @ (posedge CLK) begin
        if (RST) begin
            rCplH <= #1 0;
            rCplD <= #1 0;
        end
        else if (RX_ENG_RD_DONE & TX_ENG_RD_REQ_SENT) begin
            rCplH <= #1 rCplH;
            rCplD <= #1 rCplD;
        end
        else if (TX_ENG_RD_REQ_SENT) begin
            rCplH <= #1 rCplH + rCplHAmt;
            rCplD <= #1 rCplD + rCplDAmt;
        end
        else if (RX_ENG_RD_DONE) begin
            rCplH <= #1 rCplH - rCplHAmt;
            rCplD <= #1 rCplD - rCplDAmt;
        end
    end

endmodule
module recv_credit_flow_ctrl
    (
     input        CLK,
     input        RST,
     input [2:0]  CONFIG_MAX_READ_REQUEST_SIZE,
     input [11:0] CONFIG_MAX_CPL_DATA,
     input [7:0]  CONFIG_MAX_CPL_HDR,
     input        CONFIG_CPL_BOUNDARY_SEL,
     input        RX_ENG_RD_DONE,
     input        TX_ENG_RD_REQ_SENT,
     output       RXBUF_SPACE_AVAIL
     );


    reg           rCreditAvail=0;
    reg           rCplDAvail=0;
    reg           rCplHAvail=0;
    reg [12:0]    rMaxRecv=0;
    reg [11:0]    rCplDAmt=0;
    reg [7:0]     rCplHAmt=0;
    reg [11:0]    rCplD=0;
    reg [7:0]     rCplH=0;

    reg           rInfHCred;
    reg           rInfDCred;
    

    assign RXBUF_SPACE_AVAIL = rCreditAvail;


    always @(posedge CLK) begin
        rInfHCred <= (CONFIG_MAX_CPL_HDR == 0);
        rInfDCred <= (CONFIG_MAX_CPL_DATA == 0);
        rMaxRecv <= #1 (13'd128<<CONFIG_MAX_READ_REQUEST_SIZE);
        rCplHAmt <= #1 (rMaxRecv>>({2'b11, CONFIG_CPL_BOUNDARY_SEL}));
        rCplDAmt <= #1 (rMaxRecv>>4);
        rCplHAvail <= #1 (rCplH <= CONFIG_MAX_CPL_HDR);
        rCplDAvail <= #1 (rCplD <= CONFIG_MAX_CPL_DATA);
        rCreditAvail <= #1 ((rCplHAvail|rInfHCred) & (rCplDAvail | rInfDCred));
    end


    always @ (posedge CLK) begin
        if (RST) begin
            rCplH <= #1 0;
            rCplD <= #1 0;
        end
        else if (RX_ENG_RD_DONE & TX_ENG_RD_REQ_SENT) begin
            rCplH <= #1 rCplH;
            rCplD <= #1 rCplD;
        end
        else if (TX_ENG_RD_REQ_SENT) begin
            rCplH <= #1 rCplH + rCplHAmt;
            rCplD <= #1 rCplD + rCplDAmt;
        end
        else if (RX_ENG_RD_DONE) begin
            rCplH <= #1 rCplH - rCplHAmt;
            rCplD <= #1 rCplD - rCplDAmt;
        end
    end

endmodule