data/full_repos/permissive/463555432/Codes/amsg_laplacian_3.v
1: b'%Warning-WIDTH: data/full_repos/permissive/463555432/Codes/amsg_laplacian_3.v:15: Operator SUB expects 16 bits on the RHS, but RHS\'s VARREF \'n3\' generates 9 bits.\n                                                                                : ... In instance AMSG_laplacian_3\n    assign ys1 = m1 - n3;\n                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/463555432/Codes/amsg_laplacian_3.v:21: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'ys1\' generates 16 bits.\n                                                                                : ... In instance AMSG_laplacian_3\n      y1 <= ys1;\n         ^~\n%Error: Exiting due to 2 warning(s)\n'
module AMSG_laplacian_3(
  input [7:0] p2, p4, p5, p6, p8,
  output reg [7:0] y1
    );
    wire [15:0] ys1;
    wire [8:0] n1, n2, n3;
    wire [15:0] m1;
    
    assign n1 = p2 + p4;
    assign n2 = p6 + p8;
    assign n3 = n1 + n2;
	assign m1 = 4 * p5;
    assign ys1 = m1 - n3;
    always@(ys1)
    begin
    if(ys1 > 255)
      y1 <= 255;
    else
      y1 <= ys1;
    end
endmodule
module AMSG_laplacian_3(
  input [7:0] p2, p4, p5, p6, p8,
  output reg [7:0] y1
    );

    wire [15:0] ys1;
    wire [8:0] n1, n2, n3;
    wire [15:0] m1;
    
    assign n1 = p2 + p4;
    assign n2 = p6 + p8;
    assign n3 = n1 + n2;
	assign m1 = 4 * p5;
    assign ys1 = m1 - n3;
    always@(ys1)
    begin
    if(ys1 > 255)
      y1 <= 255;
    else
      y1 <= ys1;
    end
endmodule