data/full_repos/permissive/441359809/src/yosys/tests/arch/common/shifter.v
data/verilator_xmls/19c7fcc1-1825-4979-9396-a3d49916c26e.xml
module top(out, clk, in);
    output [7:0] out;
    input signed clk, in;
    reg signed [7:0] out = 0;

    always @(posedge clk)
	begin
		out    <= out >> 1;
		out[7] <= in;
	end    
endmodule
module top(out, clk, in);

    output [7:0] out;
    input signed clk, in;
    reg signed [7:0] out = 0;

    always @(posedge clk)
	begin
		out    <= out >> 1;
		out[7] <= in;
	end    
endmodule