data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/SYNTAX_BENCHMARKS/inferred_ram.v
1: b'%Warning-WIDTH: data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/SYNTAX_BENCHMARKS/inferred_ram.v:16: Bit extraction of array[8:0] requires 4 bit index, not 9 bits.\n                                                                                                                               : ... In instance inferred_ram\n mregs [adr] <= a;\n       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/SYNTAX_BENCHMARKS/inferred_ram.v:21: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                                                               : ... In instance inferred_ram\n adr <= 8\'b00000000;\n     ^~\n%Error: Exiting due to 2 warning(s)\n'
module inferred_ram (clk,a,b,reset);
	input reset;
	input clk;
	input [31:0] a;
	output [31:0] b;

	reg  [31:0] mregs [8:0];  
	reg [8:0] adr;

	reg [31:0] b;

always @ (posedge clk )
	if (!reset)
	begin
	mregs [adr] <= a;
	b <= mregs [adr-1];
	adr <= adr+1;
	end
	else
	adr <= 8'b00000000;

endmodule
module inferred_ram (clk,a,b,reset);

	input reset;
	input clk;
	input [31:0] a;
	output [31:0] b;

	reg  [31:0] mregs [8:0];  
	reg [8:0] adr;

	reg [31:0] b;

always @ (posedge clk )
	if (!reset)
	begin
	mregs [adr] <= a;
	b <= mregs [adr-1];
	adr <= adr+1;
	end
	else
	adr <= 8'b00000000;

endmodule