data/full_repos/permissive/501791642/ISE_devel/utils.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/501791642/ISE_devel/utils.v:25: Multiple top level modules\n                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                            : ... Top module \'prescaler\'\nmodule prescaler #(\n       ^~~~~~~~~\n                                                                            : ... Top module \'up_cnt_mod\'\nmodule up_cnt_mod #(  \n       ^~~~~~~~~~\n                                                                            : ... Top module \'shift_reg\'\nmodule shift_reg #(\n       ^~~~~~~~~\n                                                                            : ... Top module \'register\'\nmodule register #(\n       ^~~~~~~~\n                                                                            : ... Top module \'register_clr\'\nmodule register_clr #(\n       ^~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module up_cnt_mod #(  
    parameter MODULO = 10,
    parameter W = 4 
)
(
    input               CLK,
    input               CE,
    input               CLR,
    output reg [W-1:0]  Q = 0,
    output              CO
);

always @(posedge CLK)
    if (CLR)
        Q <= {W{1'd0}};
    else if (CE)
        if (Q == MODULO-1)
            Q <= {W{1'd0}};
        else
            Q <= Q+1;
            
    assign CO = CE & (Q == MODULO-1);

endmodule
module up_cnt_mod #(  
    parameter MODULO = 10,
    parameter W = 4 
)
(
    input               CLK,
    input               CE,
    input               CLR,
    output reg [W-1:0]  Q = 0,
    output              CO
);


always @(posedge CLK)
    if (CLR)
        Q <= {W{1'd0}};
    else if (CE)
        if (Q == MODULO-1)
            Q <= {W{1'd0}};
        else
            Q <= Q+1;
            
    assign CO = CE & (Q == MODULO-1);

endmodule