data/full_repos/permissive/451270484/simple_registers/counters/counter128_async_resetb/counter128_async_resetb_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/451270484/simple_registers/counters/counter128_async_resetb/counter128_async_resetb_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #0 reset = 1\'b0; clk = 1\'b0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/451270484/simple_registers/counters/counter128_async_resetb/counter128_async_resetb_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #100 reset = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/451270484/simple_registers/counters/counter128_async_resetb/counter128_async_resetb_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = ~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/451270484/simple_registers/counters/counter128_async_resetb/counter128_async_resetb_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #5000 $stop;\n    ^\n%Error: data/full_repos/permissive/451270484/simple_registers/counters/counter128_async_resetb/counter128_async_resetb_tb.v:13: Can\'t find definition of variable: \'reset\'\n                                                                                                                              : ... Suggested alternative: \'resetb\'\n    #0 reset = 1\'b0; clk = 1\'b0;\n       ^~~~~\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module counter128_async_resetb_tb;

  reg clk, resetb;
  wire [127:0] result;

  counter128_async_resetb DUT(
    .clk(clk), 
    .resetb(resetb), 
    .result(result)
  );
  
  initial begin
    #0 reset = 1'b0; clk = 1'b0;
    #100 reset = 1'b1;
  end

  always begin
    #10 clk = ~clk;
  end
  
  initial begin
    #5000 $stop;
  end

endmodule
module counter128_async_resetb_tb;


  reg clk, resetb;
  wire [127:0] result;

  counter128_async_resetb DUT(
    .clk(clk), 
    .resetb(resetb), 
    .result(result)
  );
  
  initial begin
    #0 reset = 1'b0; clk = 1'b0;
    #100 reset = 1'b1;
  end

  always begin
    #10 clk = ~clk;
  end
  
  initial begin
    #5000 $stop;
  end

endmodule