data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/data_memory.v
data/verilator_xmls/9aa7964c-ab73-4e9a-b763-a5e2d4305b90.xml
module data_memory(
    input clk,
    input mem_read,
    input mem_write,
    input [9:0] address,
    input [31:0] write_data,
    output reg [31:0] read_data
    );
    reg [31:0] memory[0:1023];
    integer i;
    initial begin
        for(i = 0; i <= 1023; i = i + 1)
            memory[i] = 0;
    end
    always@(posedge clk) begin
        if(mem_write == 1)
            memory[address] = write_data;
    end
        
    always@(*) begin
        if(mem_read == 1)
            read_data = memory[address];
    end
endmodule
module data_memory(
    input clk,
    input mem_read,
    input mem_write,
    input [9:0] address,
    input [31:0] write_data,
    output reg [31:0] read_data
    );

    reg [31:0] memory[0:1023];
    integer i;
    initial begin
        for(i = 0; i <= 1023; i = i + 1)
            memory[i] = 0;
    end
    always@(posedge clk) begin
        if(mem_write == 1)
            memory[address] = write_data;
    end
        
    always@(*) begin
        if(mem_read == 1)
            read_data = memory[address];
    end
endmodule