data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/ADC/ADC_to_fp.v
1: b"%Error: data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/ADC/ADC_to_fp.v:29: Duplicate declaration of signal: 'ADC_16Q48_OUT'\n                                                                                          : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n    wire [FLOAT_WIDTH   - 1 : 0] ADC_16Q48_OUT;\n                                 ^~~~~~~~~~~~~\n        data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/ADC/ADC_to_fp.v:11: ... Location of original declaration\n    output  [ADC_WIDTH  - 1 : 0] ADC_16Q48_OUT,\n                                 ^~~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module ADC_to_fp
#(
    parameter FLOAT_WIDTH = 64,
    parameter ADC_WIDTH = 12
)
(
    input   ADC_CLK,
    input   [ADC_WIDTH  - 1 : 0] ADC_DATA_IN,
    input   enable,
    output  DONE,
    output  [ADC_WIDTH  - 1 : 0] ADC_16Q48_OUT,
    output REG_WRITE,
    output REG_RST
);


    reg [FLOAT_WIDTH    - 1 : 0] GAIN_MUL_IN    = 64'h0014_0000_0000_0000;



    wire RST;
    wire VALID;
    wire in_REG_RST;
    wire [ADC_WIDTH   - 1 : 0] ADC_AVERAGE_OUT;

    wire [FLOAT_WIDTH   - 1 : 0] ADC_MUL_INPUT;
    wire [FLOAT_WIDTH*2 - 1 : 0] ADC_MUL_DATA_OUT;

    wire [FLOAT_WIDTH   - 1 : 0] ADC_16Q48_OUT;
    
    assign ADC_16Q48_OUT = ADC_MUL_DATA_OUT[112+11:48+11];
    assign REG_RST = in_REG_RST;
    assign REG_WRITE = VALID;



    ADC_AVERAGE  #(.ADC_WIDTH(ADC_WIDTH), .NUM_SAMPS(1024)) ADC_AVERAGE0 (.DATA_IN(ADC_DATA_IN), .DATA_OUT(ADC_AVERAGE_OUT), .CLK(ADC_CLK), .DONE(DONE), .RST(RST));

    ADC_FSM FSM0 (.done(DONE), .enable(enable), .adc_clk(ADC_CLK), .ADC_RST(RST), .REG_RST(in_REG_RST), .REG_WRITE(VALID));
    
    gen_padder #(.IN_WIDTH(ADC_WIDTH), .OUT_WIDTH(FLOAT_WIDTH), .L_PAD_WIDTH(4), .R_PAD_WIDTH(FLOAT_WIDTH-16)) PAD0 (.in(ADC_AVERAGE_OUT), .out(ADC_MUL_INPUT));

    gen_mult #(.DATA_WIDTH(FLOAT_WIDTH)) MULT1 (.a(ADC_MUL_INPUT), .b(GAIN_MUL_IN), .p(ADC_MUL_DATA_OUT));


endmodule
module ADC_to_fp
#(
    parameter FLOAT_WIDTH = 64,
    parameter ADC_WIDTH = 12
)
(
    input   ADC_CLK,
    input   [ADC_WIDTH  - 1 : 0] ADC_DATA_IN,
    input   enable,
    output  DONE,
    output  [ADC_WIDTH  - 1 : 0] ADC_16Q48_OUT,
    output REG_WRITE,
    output REG_RST
);



    reg [FLOAT_WIDTH    - 1 : 0] GAIN_MUL_IN    = 64'h0014_0000_0000_0000;



    wire RST;
    wire VALID;
    wire in_REG_RST;
    wire [ADC_WIDTH   - 1 : 0] ADC_AVERAGE_OUT;

    wire [FLOAT_WIDTH   - 1 : 0] ADC_MUL_INPUT;
    wire [FLOAT_WIDTH*2 - 1 : 0] ADC_MUL_DATA_OUT;

    wire [FLOAT_WIDTH   - 1 : 0] ADC_16Q48_OUT;
    
    assign ADC_16Q48_OUT = ADC_MUL_DATA_OUT[112+11:48+11];
    assign REG_RST = in_REG_RST;
    assign REG_WRITE = VALID;



    ADC_AVERAGE  #(.ADC_WIDTH(ADC_WIDTH), .NUM_SAMPS(1024)) ADC_AVERAGE0 (.DATA_IN(ADC_DATA_IN), .DATA_OUT(ADC_AVERAGE_OUT), .CLK(ADC_CLK), .DONE(DONE), .RST(RST));

    ADC_FSM FSM0 (.done(DONE), .enable(enable), .adc_clk(ADC_CLK), .ADC_RST(RST), .REG_RST(in_REG_RST), .REG_WRITE(VALID));
    
    gen_padder #(.IN_WIDTH(ADC_WIDTH), .OUT_WIDTH(FLOAT_WIDTH), .L_PAD_WIDTH(4), .R_PAD_WIDTH(FLOAT_WIDTH-16)) PAD0 (.in(ADC_AVERAGE_OUT), .out(ADC_MUL_INPUT));

    gen_mult #(.DATA_WIDTH(FLOAT_WIDTH)) MULT1 (.a(ADC_MUL_INPUT), .b(GAIN_MUL_IN), .p(ADC_MUL_DATA_OUT));


endmodule