data/full_repos/permissive/510755552/proj/accel/cfu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:65: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 9 bits.\n                                                                        : ... In instance Cfu.m15\n                im0 <= im[7:0]  + 9\'d128; \n                    ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:66: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 9 bits.\n                                                                        : ... In instance Cfu.m15\n                im1 <= im[15:8] + 9\'d128;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:67: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 9 bits.\n                                                                        : ... In instance Cfu.m15\n                im2 <= im[23:16] + 9\'d128; \n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:68: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 9 bits.\n                                                                        : ... In instance Cfu.m15\n                im3 <= im[31:24] + 9\'d128; \n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:188: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n            tile_mem[mem_ctr]         <= cfu0[31:0];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:212: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'ctr\' generates 4 bits.\n                                                                         : ... In instance Cfu\n                id = ctr; \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:216: Operator ADD expects 32 or 8 bits on the LHS, but LHS\'s VARREF \'ctr\' generates 4 bits.\n                                                                         : ... In instance Cfu\n                id = ctr + 3; \n                         ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:220: Operator ADD expects 32 or 8 bits on the LHS, but LHS\'s VARREF \'ctr\' generates 4 bits.\n                                                                         : ... In instance Cfu\n                id = ctr + 6;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:305: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n    mac  m00(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a00]),  .p(out[0])); \n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:306: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n    mac  m01(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a01]),  .p(out[1])); \n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:307: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n    mac  m02(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a02]),  .p(out[2])); \n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:308: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n    mac  m03(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a03]),  .p(out[3])); \n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:309: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n    mac  m04(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a04]),  .p(out[4])); \n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:310: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n    mac  m05(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a05]),  .p(out[5])); \n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:311: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n    mac  m06(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a06]),  .p(out[6])); \n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:312: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n    mac  m07(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a07]),  .p(out[7])); \n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:313: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n    mac  m08(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a08]),  .p(out[8])); \n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:314: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n    mac  m09(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a09]),  .p(out[9])); \n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:315: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n    mac  m10(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a10]),  .p(out[10])); \n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:316: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n    mac  m11(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a11]),  .p(out[11])); \n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:317: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n    mac  m12(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a12]),  .p(out[12])); \n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:318: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n    mac  m13(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a13]),  .p(out[13])); \n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:319: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n    mac  m14(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a14]),  .p(out[14]));     \n                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/510755552/proj/accel/cfu.v:320: Bit extraction of array[63:0] requires 6 bit index, not 8 bits.\n                                                                         : ... In instance Cfu\n    mac  m15(.clk(clk), .reset(cfu_reset), .start(mode), .sel(sel), .w(tile_mem_w), .im(tile_mem[a15]),  .p(out[15]));\n                                                                                                ^\n%Error: Exiting due to 24 warning(s)\n'
module mac (
    input clk, reset, start, 
    input [2:0] sel,
    input [31:0] w,    
    input [31:0] im,  
    output signed [31:0] p   
);
    
    reg signed [31:0] d;
    

    reg [7:0] im0;
    reg [7:0] im1; 
    reg [7:0] im2; 
    reg [7:0] im3; 
    reg [7:0] w0; 
    reg [7:0] w1; 
    reg [7:0] w2; 
    reg [7:0] w3;
    

    reg [31:0] acc1;
    reg [31:0] acc2; 
    reg [31:0] acc3; 
    reg [31:0] acc4; 
    reg [31:0] acc5;
    reg [31:0] acc6; 
    reg [31:0] acc7; 
    reg [31:0] acc8;
    

    reg [31:0] prod;
    
     
    always @(posedge clk) 
    begin
    	case({reset, start})
            2'b10, 2'b11:    begin
                im0 <= 0;
                im1 <= 0; 
                im2 <= 0; 
                im3 <= 0;
                
                w0 <= 0; 
                w1 <= 0; 
                w2 <= 0; 
                w3 <= 0;
                
                acc1 <= 0; 
                acc2 <= 0; 
                acc3 <= 0; 
                acc4 <= 0; 
                acc5 <= 0; 
                acc6 <= 0; 
                acc7 <= 0; 
                acc8 <= 0; 
            end         
            2'b01:    begin
                im0 <= im[7:0]  + 9'd128; 
                im1 <= im[15:8] + 9'd128;
                im2 <= im[23:16] + 9'd128; 
                im3 <= im[31:24] + 9'd128; 
                	    	
                w0 <= w[7:0]; 
                w1 <= w[15:8]; 
                w2 <= w[23:16]; 
                w3 <= w[31:24];	
                prod <= $signed({1'b0, im0}) * $signed(w0) + $signed({1'b0, im1}) * $signed(w1) + $signed({1'b0, im2}) * $signed(w2) + $signed({1'b0,im3}) * $signed(w3);
                
                case(sel)
                    3'b000: acc1 <= $signed(acc1) + prod; 
                    3'b001: acc2 <= $signed(acc2) + prod; 
                    3'b010: acc3 <= $signed(acc3) + prod; 
                    3'b011: acc4 <= $signed(acc4) + prod;  
                    3'b100: acc5 <= $signed(acc5) + prod; 
                    3'b101: acc6 <= $signed(acc6) + prod; 
                    3'b110: acc7 <= $signed(acc7) + prod; 
                    3'b111: acc8 <= $signed(acc8) + prod;  
                endcase
            end 
            default:    begin
                im0 <= im0; 
                im1 <= im1;
                im2 <= im2;
                im3 <= im3; 
                 
                w0 <= w0; 
                w1 <= w1; 
                w2 <= w2; 
                w3 <= w3;
                
                acc1 <= $signed(acc1);
                acc2 <= $signed(acc2);
                acc3 <= $signed(acc3); 
                acc4 <= $signed(acc4);  
                acc5 <= $signed(acc5);
                acc6 <= $signed(acc6);
                acc7 <= $signed(acc7); 
                acc8 <= $signed(acc8); 	    
            end 
        endcase
    end 
    
    always @(*) begin
        case(sel)
            3'b000: d = $signed(acc1);
            3'b001: d = $signed(acc2);
            3'b010: d = $signed(acc3); 
            3'b011: d = $signed(acc4);
            3'b100: d = $signed(acc5);
            3'b101: d = $signed(acc6);
            3'b110: d = $signed(acc7); 
            3'b111: d = $signed(acc8);    
        endcase
    end	
    	
    assign p = d;
        
endmodule
module mac (
    input clk, reset, start, 
    input [2:0] sel,
    input [31:0] w,    
    input [31:0] im,  
    output signed [31:0] p   
);

    
    reg signed [31:0] d;
    

    reg [7:0] im0;
    reg [7:0] im1; 
    reg [7:0] im2; 
    reg [7:0] im3; 
    reg [7:0] w0; 
    reg [7:0] w1; 
    reg [7:0] w2; 
    reg [7:0] w3;
    

    reg [31:0] acc1;
    reg [31:0] acc2; 
    reg [31:0] acc3; 
    reg [31:0] acc4; 
    reg [31:0] acc5;
    reg [31:0] acc6; 
    reg [31:0] acc7; 
    reg [31:0] acc8;
    

    reg [31:0] prod;
    
     
    always @(posedge clk) 
    begin
    	case({reset, start})
            2'b10, 2'b11:    begin
                im0 <= 0;
                im1 <= 0; 
                im2 <= 0; 
                im3 <= 0;
                
                w0 <= 0; 
                w1 <= 0; 
                w2 <= 0; 
                w3 <= 0;
                
                acc1 <= 0; 
                acc2 <= 0; 
                acc3 <= 0; 
                acc4 <= 0; 
                acc5 <= 0; 
                acc6 <= 0; 
                acc7 <= 0; 
                acc8 <= 0; 
            end         
            2'b01:    begin
                im0 <= im[7:0]  + 9'd128; 
                im1 <= im[15:8] + 9'd128;
                im2 <= im[23:16] + 9'd128; 
                im3 <= im[31:24] + 9'd128; 
                	    	
                w0 <= w[7:0]; 
                w1 <= w[15:8]; 
                w2 <= w[23:16]; 
                w3 <= w[31:24];	
                prod <= $signed({1'b0, im0}) * $signed(w0) + $signed({1'b0, im1}) * $signed(w1) + $signed({1'b0, im2}) * $signed(w2) + $signed({1'b0,im3}) * $signed(w3);
                
                case(sel)
                    3'b000: acc1 <= $signed(acc1) + prod; 
                    3'b001: acc2 <= $signed(acc2) + prod; 
                    3'b010: acc3 <= $signed(acc3) + prod; 
                    3'b011: acc4 <= $signed(acc4) + prod;  
                    3'b100: acc5 <= $signed(acc5) + prod; 
                    3'b101: acc6 <= $signed(acc6) + prod; 
                    3'b110: acc7 <= $signed(acc7) + prod; 
                    3'b111: acc8 <= $signed(acc8) + prod;  
                endcase
            end 
            default:    begin
                im0 <= im0; 
                im1 <= im1;
                im2 <= im2;
                im3 <= im3; 
                 
                w0 <= w0; 
                w1 <= w1; 
                w2 <= w2; 
                w3 <= w3;
                
                acc1 <= $signed(acc1);
                acc2 <= $signed(acc2);
                acc3 <= $signed(acc3); 
                acc4 <= $signed(acc4);  
                acc5 <= $signed(acc5);
                acc6 <= $signed(acc6);
                acc7 <= $signed(acc7); 
                acc8 <= $signed(acc8); 	    
            end 
        endcase
    end 
    
    always @(*) begin
        case(sel)
            3'b000: d = $signed(acc1);
            3'b001: d = $signed(acc2);
            3'b010: d = $signed(acc3); 
            3'b011: d = $signed(acc4);
            3'b100: d = $signed(acc5);
            3'b101: d = $signed(acc6);
            3'b110: d = $signed(acc7); 
            3'b111: d = $signed(acc8);    
        endcase
    end	
    	
    assign p = d;
        
endmodule