data/full_repos/permissive/490031785/Assignments/ass2.v
data/verilator_xmls/fa4b9fe4-8783-4583-83bf-cd4ffce12ce6.xml
module Circuit_2 (Out_1, Out_2, Out_3, A, B, C, D);
     	    output Out_1, Out_2, Out_3;
     	    input A, B, C, D;
     	
     	    assign Out_1 = (A | !B) & !C & (C | D);
        assign Out_2 = (!C & D | B & C & D | C & !D) & (!A | B);
     	    assign Out_3 = (A & B | C) & D | (!B & C);
     	endmodule
module Circuit_2 (Out_1, Out_2, Out_3, A, B, C, D);

     	    output Out_1, Out_2, Out_3;
     	    input A, B, C, D;
     	
     	    assign Out_1 = (A | !B) & !C & (C | D);
        assign Out_2 = (!C & D | B & C & D | C & !D) & (!A | B);
     	    assign Out_3 = (A & B | C) & D | (!B & C);
     	endmodule