data/full_repos/permissive/497870922/rtl/spi module/spi_gray_counter.v
1: b'%Error: Cannot find file containing module: module,data/full_repos/permissive/497870922\n        ... Looked in:\n             data/full_repos/permissive/497870922/rtl/spi/module,data/full_repos/permissive/497870922\n             data/full_repos/permissive/497870922/rtl/spi/module,data/full_repos/permissive/497870922.v\n             data/full_repos/permissive/497870922/rtl/spi/module,data/full_repos/permissive/497870922.sv\n             module,data/full_repos/permissive/497870922\n             module,data/full_repos/permissive/497870922.v\n             module,data/full_repos/permissive/497870922.sv\n             obj_dir/module,data/full_repos/permissive/497870922\n             obj_dir/module,data/full_repos/permissive/497870922.v\n             obj_dir/module,data/full_repos/permissive/497870922.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/497870922/rtl/spi\n%Error: Cannot find file containing module: module/spi_gray_counter.v\n%Error: Exiting due to 3 error(s)\n'
module gray_counter (clk_i, rst_n_i, en_i, period_i, clock_o);

parameter SIZE = 8;
 
input            clk_i;
input            rst_n_i;
input            en_i;
input [SIZE-1:0] period_i;

output           clock_o;

reg   [SIZE-1:0] gray_code;
reg   [SIZE-1:0] tog;
reg              clock;
wire  [SIZE-1:0] gray_code_comp;
 
integer i,j,k;
 
bin2gray #SIZE B2G(period_i, gray_code_comp);

assign clock_o = clock;
 
always @(posedge clk_i or negedge rst_n_i) 
  if (rst_n_i==1'b0) begin
   gray_code <= 0;
   clock <= 1'b0;
  end
  else begin
    if (en_i==1'b1) 
      if (gray_code_comp==gray_code) begin
        gray_code <= 0;
        clock  <= 1'b1;
      end
      else begin
        clock  <= 1'b0;
        tog = 0;
        for (i=0; i<=SIZE-1; i=i+1) begin




          for (j=i; j<=SIZE-1; j=j+1) tog[i] = tog[i] ^ gray_code[j];  
          tog[i] = !tog[i];                 



          for (k=0; k<=i-1; k=k+1) tog[i] = tog[i] && !tog[k];
        end



        if (tog[SIZE-2:0]==0) tog[SIZE-1] = 1; 



        gray_code <= gray_code ^ tog;          
      end
   end
endmodule
module gray_counter (clk_i, rst_n_i, en_i, period_i, clock_o);


parameter SIZE = 8;
 
input            clk_i;
input            rst_n_i;
input            en_i;
input [SIZE-1:0] period_i;

output           clock_o;

reg   [SIZE-1:0] gray_code;
reg   [SIZE-1:0] tog;
reg              clock;
wire  [SIZE-1:0] gray_code_comp;
 
integer i,j,k;
 
bin2gray #SIZE B2G(period_i, gray_code_comp);

assign clock_o = clock;
 
always @(posedge clk_i or negedge rst_n_i) 
  if (rst_n_i==1'b0) begin
   gray_code <= 0;
   clock <= 1'b0;
  end
  else begin
    if (en_i==1'b1) 
      if (gray_code_comp==gray_code) begin
        gray_code <= 0;
        clock  <= 1'b1;
      end
      else begin
        clock  <= 1'b0;
        tog = 0;
        for (i=0; i<=SIZE-1; i=i+1) begin




          for (j=i; j<=SIZE-1; j=j+1) tog[i] = tog[i] ^ gray_code[j];  
          tog[i] = !tog[i];                 



          for (k=0; k<=i-1; k=k+1) tog[i] = tog[i] && !tog[k];
        end



        if (tog[SIZE-2:0]==0) tog[SIZE-1] = 1; 



        gray_code <= gray_code ^ tog;          
      end
   end
endmodule