data/full_repos/permissive/482720319/MIPS_proc.v
1: b'%Error: data/full_repos/permissive/482720319/MIPS_proc.v:1: Cannot find include file: data_mem.v\n`include "data_mem.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/482720319,data/full_repos/permissive/482720319/data_mem.v\n             data/full_repos/permissive/482720319,data/full_repos/permissive/482720319/data_mem.v.v\n             data/full_repos/permissive/482720319,data/full_repos/permissive/482720319/data_mem.v.sv\n             data_mem.v\n             data_mem.v.v\n             data_mem.v.sv\n             obj_dir/data_mem.v\n             obj_dir/data_mem.v.v\n             obj_dir/data_mem.v.sv\n%Error: data/full_repos/permissive/482720319/MIPS_proc.v:2: Cannot find include file: reg_dec.v\n`include "reg_dec.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/482720319/MIPS_proc.v:3: Cannot find include file: reg_file.v\n`include "reg_file.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/482720319/MIPS_proc.v:4: Cannot find include file: alu.v\n`include "alu.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/482720319/MIPS_proc.v:5: Cannot find include file: mips_control_fsm.v\n`include "mips_control_fsm.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/482720319/MIPS_proc.v:6: Cannot find include file: alu_control.v\n`include "alu_control.v" \n         ^~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/482720319/MIPS_proc.v:85: Unsupported: Ignoring delay on this delayed statement.\n            forever #1 clk <= ~clk;\n                    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/482720319/MIPS_proc.v:90: Unsupported: Ignoring delay on this delayed statement.\n            #1.5 rst = 0;\n            ^\n%Error: data/full_repos/permissive/482720319/MIPS_proc.v:175: syntax error, unexpected \'@\'\n            @(MemData);\n            ^\n%Error: data/full_repos/permissive/482720319/MIPS_proc.v:193: syntax error, unexpected \'@\'\n            @(posedge done_sig);\n            ^\n%Error: data/full_repos/permissive/482720319/MIPS_proc.v:261: Unsupported or unknown PLI call: $dumpfile\n            $dumpfile("mem_test.vcd");\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/482720319/MIPS_proc.v:262: Unsupported or unknown PLI call: $dumpvars\n            $dumpvars(2, MIPS_16);\n            ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/482720319/MIPS_proc.v:263: Unsupported: Ignoring delay on this delayed statement.\n            #30 $finish;\n            ^\n%Error: Exiting due to 10 error(s), 3 warning(s)\n'
module MIPS_16();

      reg [15:0] PC;
      reg [15:0] ALUout;
      wire [15:0] addr;
      reg [15:0] A, B, C;
      wire [15:0] MemData;
      wire [3:0] qw4, qw3, qw2, qw1;
      wire [11:0] se1;
      wire [7:0] se2;
      reg [15:0] instr;
      reg [15:0] MDR;
      wire [15:0] rd1, rd2, rd3;
      wire [3:0] q4, q3, q2, q1;
      wire [11:0] q321;
      wire [7:0] q21;
      wire [3:0] w_reg, read_reg_1, read_reg_2;
      wire [15:0] w_data;
      wire [15:0] srcA, srcB;
      wire zero;
      wire [15:0] alures;
      wire PCen;
      
      wire RegDst;
      wire [1:0] ALUdir;
      wire MemTowire;

      wire PCWrite;
      wire [2:0] ALUop;
      wire ALUsrcA;
      wire [2:0] ALUsrcB;
      wire [1:0] PCsrc;
      wire RegWrite;
      reg [1:0] RegSrcA;
      wire IorD;
      wire MemRead, MemWrite;
      wire IRwrite;
      wire be;
      wire branch;      
      
      
      reg clk;
      reg rst;

      assign addr = (IorD ? ALUout : PC);
      wire done_sig;
      ControlFSM fsm1 (
            q4,
            rst,
            q1,
            clk,
            PCsrc,
            IorD,
            MemWrite,
            MemRead,
            IRwrite,
            RegDst,
            RegWrite,
            ALUsrcA,
            ALUsrcB,
            ALUdir,
            MemToReg,
            PCWrite,
            branch,
            be,
            cur_state,
            done_sig
      );

        
      

      
      initial begin
            PC = 16'h0000;

            clk <= 0;
            forever #1 clk <= ~clk;
      end
      
      initial begin
            rst = 1;
            #1.5 rst = 0;
      end

      assign se1 = { {4{q321[11]}} , q321};
      assign se2 = { {8{q21[7]}} , q21};
      
      assign q4 = instr[15:12];
      assign q3 = instr[11:8];
      assign q2 = instr[7:4];
      assign q1 = instr[3:0];
      assign q321 = instr[11:0];
      assign q21 = instr[7:0];
      
      wire [3:0] op_fsm;
      assign op_fsm = MemData[15:12];

      wire [3:0] ex_ins_1, ex_ins_2;
      
      RegDecoder rad (
            q3,
            ex_ins_1,
            ex_ins_2
      );
                  
                  
      assign w_reg = (RegDst ? ex_ins_1 : q3);
      assign read_reg_1 = (RegSrcA[1] ? ex_ins_2 : (RegSrcA[0] ? q3 : q2));
      assign read_reg_2 = q1;
      assign w_data = (MemToReg ? MDR : ALUout);
      assign PCen = (PCWrite | (branch & (be ~^ zero)));


      ALU alu1(
            ALUop,
            srcA,
            srcB,
            alures,
            zero
      );

      wire [15:0] d_rdata;
      RegFile regf (
            w_reg,
            read_reg_1,
            read_reg_2,
            w_data,
            RegWrite,
            rd1,
            rd2,
            rd3,
            d_rdata
      );


      assign srcA = (ALUsrcA ? A : PC);
      assign srcB = (ALUsrcB[2] ? se2 : (ALUsrcB[1] ? (ALUsrcB[0] ? q2 : se1) : (ALUsrcB[0] ? 16'd1 : B)));

      wire [15:0] d_mem;

      Datamemory mem1(
            addr,
            rd3,
            MemRead,
            MemWrite,
            MemData,
            d_mem
      );

      
      alucontrol alu_c1 ( 
            q4,
            q1,
            ALUdir,
            ALUop
      );
      

      

      always @(posedge clk) begin

            ALUout <= alures;
      end

      always @(posedge clk) begin
            @(MemData);
            MDR <= MemData;
      end

      always @(posedge clk) begin
            




            
            C <= rd3;
            A = rd1;
            B = rd2;
            
            


            @(posedge done_sig);

            if(PCen) begin

                  case (PCsrc)
                        2'b00 : begin

                              PC = PC + se1;
                        end
                        2'b01 : PC = C;
                        2'b10 : PC = PC + 1;  
                        default : PC <= PC;
                  endcase   
            end

            if(IRwrite)
                  instr = MemData;
            
      end















      

      always @(*) begin
            case (q4)
                  4'b1000 : RegSrcA <= 2'b00;
                  4'b1100 : RegSrcA <= 2'b00;
                  4'b1011 : RegSrcA <= 2'b00;
                  4'b1111 : RegSrcA <= 2'b00;
                  4'b0100 : RegSrcA <= 2'b00;
                  4'b0101 : RegSrcA <= 2'b00;
                  4'b1001 : RegSrcA <= 2'b01;
                  4'b1010 : RegSrcA <= 2'b01;
                  4'b1101 : RegSrcA <= 2'b01;
                  4'b1110 : RegSrcA <= 2'b01;
                  4'b0000 : RegSrcA <= 2'b01;
                  4'b0111 : RegSrcA <= 2'b01;
                  4'b0110 : RegSrcA <= 2'b01;
                  4'b0001 : RegSrcA <= 2'b10;
                  4'b0010 : RegSrcA <= 2'b10;
                  default : RegSrcA <= 2'b00;
            endcase
      end









      wire [3:0] cur_state;

      initial begin
            $dumpfile("mem_test.vcd");
            $dumpvars(2, MIPS_16);
            #30 $finish;
      end

endmodule
module MIPS_16();


      reg [15:0] PC;
      reg [15:0] ALUout;
      wire [15:0] addr;
      reg [15:0] A, B, C;
      wire [15:0] MemData;
      wire [3:0] qw4, qw3, qw2, qw1;
      wire [11:0] se1;
      wire [7:0] se2;
      reg [15:0] instr;
      reg [15:0] MDR;
      wire [15:0] rd1, rd2, rd3;
      wire [3:0] q4, q3, q2, q1;
      wire [11:0] q321;
      wire [7:0] q21;
      wire [3:0] w_reg, read_reg_1, read_reg_2;
      wire [15:0] w_data;
      wire [15:0] srcA, srcB;
      wire zero;
      wire [15:0] alures;
      wire PCen;
      
      wire RegDst;
      wire [1:0] ALUdir;
      wire MemTowire;

      wire PCWrite;
      wire [2:0] ALUop;
      wire ALUsrcA;
      wire [2:0] ALUsrcB;
      wire [1:0] PCsrc;
      wire RegWrite;
      reg [1:0] RegSrcA;
      wire IorD;
      wire MemRead, MemWrite;
      wire IRwrite;
      wire be;
      wire branch;      
      
      
      reg clk;
      reg rst;

      assign addr = (IorD ? ALUout : PC);
      wire done_sig;
      ControlFSM fsm1 (
            q4,
            rst,
            q1,
            clk,
            PCsrc,
            IorD,
            MemWrite,
            MemRead,
            IRwrite,
            RegDst,
            RegWrite,
            ALUsrcA,
            ALUsrcB,
            ALUdir,
            MemToReg,
            PCWrite,
            branch,
            be,
            cur_state,
            done_sig
      );

        
      

      
      initial begin
            PC = 16'h0000;

            clk <= 0;
            forever #1 clk <= ~clk;
      end
      
      initial begin
            rst = 1;
            #1.5 rst = 0;
      end

      assign se1 = { {4{q321[11]}} , q321};
      assign se2 = { {8{q21[7]}} , q21};
      
      assign q4 = instr[15:12];
      assign q3 = instr[11:8];
      assign q2 = instr[7:4];
      assign q1 = instr[3:0];
      assign q321 = instr[11:0];
      assign q21 = instr[7:0];
      
      wire [3:0] op_fsm;
      assign op_fsm = MemData[15:12];

      wire [3:0] ex_ins_1, ex_ins_2;
      
      RegDecoder rad (
            q3,
            ex_ins_1,
            ex_ins_2
      );
                  
                  
      assign w_reg = (RegDst ? ex_ins_1 : q3);
      assign read_reg_1 = (RegSrcA[1] ? ex_ins_2 : (RegSrcA[0] ? q3 : q2));
      assign read_reg_2 = q1;
      assign w_data = (MemToReg ? MDR : ALUout);
      assign PCen = (PCWrite | (branch & (be ~^ zero)));


      ALU alu1(
            ALUop,
            srcA,
            srcB,
            alures,
            zero
      );

      wire [15:0] d_rdata;
      RegFile regf (
            w_reg,
            read_reg_1,
            read_reg_2,
            w_data,
            RegWrite,
            rd1,
            rd2,
            rd3,
            d_rdata
      );


      assign srcA = (ALUsrcA ? A : PC);
      assign srcB = (ALUsrcB[2] ? se2 : (ALUsrcB[1] ? (ALUsrcB[0] ? q2 : se1) : (ALUsrcB[0] ? 16'd1 : B)));

      wire [15:0] d_mem;

      Datamemory mem1(
            addr,
            rd3,
            MemRead,
            MemWrite,
            MemData,
            d_mem
      );

      
      alucontrol alu_c1 ( 
            q4,
            q1,
            ALUdir,
            ALUop
      );
      

      

      always @(posedge clk) begin

            ALUout <= alures;
      end

      always @(posedge clk) begin
            @(MemData);
            MDR <= MemData;
      end

      always @(posedge clk) begin
            




            
            C <= rd3;
            A = rd1;
            B = rd2;
            
            


            @(posedge done_sig);

            if(PCen) begin

                  case (PCsrc)
                        2'b00 : begin

                              PC = PC + se1;
                        end
                        2'b01 : PC = C;
                        2'b10 : PC = PC + 1;  
                        default : PC <= PC;
                  endcase   
            end

            if(IRwrite)
                  instr = MemData;
            
      end















      

      always @(*) begin
            case (q4)
                  4'b1000 : RegSrcA <= 2'b00;
                  4'b1100 : RegSrcA <= 2'b00;
                  4'b1011 : RegSrcA <= 2'b00;
                  4'b1111 : RegSrcA <= 2'b00;
                  4'b0100 : RegSrcA <= 2'b00;
                  4'b0101 : RegSrcA <= 2'b00;
                  4'b1001 : RegSrcA <= 2'b01;
                  4'b1010 : RegSrcA <= 2'b01;
                  4'b1101 : RegSrcA <= 2'b01;
                  4'b1110 : RegSrcA <= 2'b01;
                  4'b0000 : RegSrcA <= 2'b01;
                  4'b0111 : RegSrcA <= 2'b01;
                  4'b0110 : RegSrcA <= 2'b01;
                  4'b0001 : RegSrcA <= 2'b10;
                  4'b0010 : RegSrcA <= 2'b10;
                  default : RegSrcA <= 2'b00;
            endcase
      end









      wire [3:0] cur_state;

      initial begin
            $dumpfile("mem_test.vcd");
            $dumpvars(2, MIPS_16);
            #30 $finish;
      end

endmodule