data/full_repos/permissive/417765606/ubuntu18p04/verilog/not_gate/rtl/not_gate.v
data/verilator_xmls/b86ff046-beef-4dc1-9d6b-5d400aa48d5c.xml
module not_gate (
    input a,
    output o
);

    assign o = ~a;

endmodule
module not_gate (
    input a,
    output o
);


    assign o = ~a;

endmodule