data/full_repos/permissive/496030466/Verilog/sim/Sim_Bus_Pkg.sv
1: b"%Error: data/full_repos/permissive/496030466/Verilog/sim/Sim_Bus_Pkg.sv:41: syntax error, unexpected '@'\n    repeat (N) @(posedge i_Bus_Clk);\n               ^\n%Error: data/full_repos/permissive/496030466/Verilog/sim/Sim_Bus_Pkg.sv:64: Unsupported: classes\n  class Bus_Trans;\n  ^~~~~\n%Error: data/full_repos/permissive/496030466/Verilog/sim/Sim_Bus_Pkg.sv:65: Unsupported: 'static' class item\n    static int n_Next_ID;\n    ^~~~~~\n%Error: data/full_repos/permissive/496030466/Verilog/sim/Sim_Bus_Pkg.sv:66: Unsupported: const class member qualifier\n    const int  n_ID;\n    ^~~~~\n%Error: data/full_repos/permissive/496030466/Verilog/sim/Sim_Bus_Pkg.sv:73: Unsupported: new constructor\n    function new();\n             ^~~\n%Error: data/full_repos/permissive/496030466/Verilog/sim/Sim_Bus_Pkg.sv:74: syntax error, unexpected ++, expecting ';'\n      n_ID = n_Next_ID++;\n                      ^~\n%Error: data/full_repos/permissive/496030466/Verilog/sim/Sim_Bus_Pkg.sv:161: Unsupported: classes\n  class Bus_Driver;\n  ^~~~~\n%Error: data/full_repos/permissive/496030466/Verilog/sim/Sim_Bus_Pkg.sv:164: Unsupported: virtual data type\n    virtual Bus_Interface.MP_Master hook;\n    ^~~~~~~\n%Error: data/full_repos/permissive/496030466/Verilog/sim/Sim_Bus_Pkg.sv:164: syntax error, unexpected '.', expecting IDENTIFIER or '=' or do or final\n    virtual Bus_Interface.MP_Master hook;\n                         ^\n%Error: data/full_repos/permissive/496030466/Verilog/sim/Sim_Bus_Pkg.sv:170: Unsupported: new constructor\n    function new(virtual Bus_Interface.MP_Master hook);\n             ^~~\n%Error: data/full_repos/permissive/496030466/Verilog/sim/Sim_Bus_Pkg.sv:170: Unsupported: virtual data type\n    function new(virtual Bus_Interface.MP_Master hook);\n                 ^~~~~~~\n%Error: data/full_repos/permissive/496030466/Verilog/sim/Sim_Bus_Pkg.sv:170: syntax error, unexpected '.', expecting IDENTIFIER\n    function new(virtual Bus_Interface.MP_Master hook);\n                                      ^\n%Error: data/full_repos/permissive/496030466/Verilog/sim/Sim_Bus_Pkg.sv:213: syntax error, unexpected IDENTIFIER\n      trans = trans.f_Bus_Wr_Trans(i_Addr8, i_Data);\n      ^~~~~\n%Error: data/full_repos/permissive/496030466/Verilog/sim/Sim_Bus_Pkg.sv:222: syntax error, unexpected IDENTIFIER\n      trans = trans.f_Bus_Rd_Trans(i_Addr8, o_Data);\n      ^~~~~\n%Error: Cannot continue\n"
function Bus_Trans f_Bus_Wr_Trans(logic [15:0] i_Addr8,
                                    logic [15:0] i_Data);
      Bus_Trans trans;
      trans = new;
      
      trans.r_Wr_Rd_n = 1'b1;
      trans.r_Addr8   = i_Addr8;
      trans.r_Data    = i_Data;

      return trans;
    endfunction
function Bus_Trans f_Bus_Wr_Trans(logic [15:0] i_Addr8,
                                    logic [15:0] i_Data);

      Bus_Trans trans;
      trans = new;
      
      trans.r_Wr_Rd_n = 1'b1;
      trans.r_Addr8   = i_Addr8;
      trans.r_Data    = i_Data;

      return trans;
    endfunction