data/full_repos/permissive/437632408/NVDLA/nvdla/nocif/NV_NVDLA_MCIF_write.v
1: b"%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/nocif/NV_NVDLA_MCIF_write.v:127: Cannot find file containing module: 'NV_NVDLA_MCIF_WRITE_ig'\nNV_NVDLA_MCIF_WRITE_ig u_ig (\n^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/437632408/NVDLA/nvdla/nocif,data/full_repos/permissive/437632408/NV_NVDLA_MCIF_WRITE_ig\n             data/full_repos/permissive/437632408/NVDLA/nvdla/nocif,data/full_repos/permissive/437632408/NV_NVDLA_MCIF_WRITE_ig.v\n             data/full_repos/permissive/437632408/NVDLA/nvdla/nocif,data/full_repos/permissive/437632408/NV_NVDLA_MCIF_WRITE_ig.sv\n             NV_NVDLA_MCIF_WRITE_ig\n             NV_NVDLA_MCIF_WRITE_ig.v\n             NV_NVDLA_MCIF_WRITE_ig.sv\n             obj_dir/NV_NVDLA_MCIF_WRITE_ig\n             obj_dir/NV_NVDLA_MCIF_WRITE_ig.v\n             obj_dir/NV_NVDLA_MCIF_WRITE_ig.sv\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/nocif/NV_NVDLA_MCIF_write.v:169: Cannot find file containing module: 'NV_NVDLA_MCIF_WRITE_eg'\nNV_NVDLA_MCIF_WRITE_eg u_eg (\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/nocif/NV_NVDLA_MCIF_write.v:198: Cannot find file containing module: 'NV_NVDLA_MCIF_WRITE_cq'\nNV_NVDLA_MCIF_WRITE_cq u_cq (\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module NV_NVDLA_MCIF_write (
   bdma2mcif_wr_req_pd
  ,bdma2mcif_wr_req_valid
  ,cdp2mcif_wr_req_pd
  ,cdp2mcif_wr_req_valid
  ,mcif2noc_axi_aw_awready
  ,mcif2noc_axi_w_wready
  ,noc2mcif_axi_b_bid
  ,noc2mcif_axi_b_bvalid
  ,nvdla_core_clk
  ,nvdla_core_rstn
  ,pdp2mcif_wr_req_pd
  ,pdp2mcif_wr_req_valid
  ,pwrbus_ram_pd
  ,rbk2mcif_wr_req_pd
  ,rbk2mcif_wr_req_valid
  ,reg2dp_wr_os_cnt
  ,reg2dp_wr_weight_bdma
  ,reg2dp_wr_weight_cdp
  ,reg2dp_wr_weight_pdp
  ,reg2dp_wr_weight_rbk
  ,reg2dp_wr_weight_sdp
  ,sdp2mcif_wr_req_pd
  ,sdp2mcif_wr_req_valid
  ,bdma2mcif_wr_req_ready
  ,cdp2mcif_wr_req_ready
  ,mcif2bdma_wr_rsp_complete
  ,mcif2cdp_wr_rsp_complete
  ,mcif2noc_axi_aw_awaddr
  ,mcif2noc_axi_aw_awid
  ,mcif2noc_axi_aw_awlen
  ,mcif2noc_axi_aw_awvalid
  ,mcif2noc_axi_w_wdata
  ,mcif2noc_axi_w_wlast
  ,mcif2noc_axi_w_wstrb
  ,mcif2noc_axi_w_wvalid
  ,mcif2pdp_wr_rsp_complete
  ,mcif2rbk_wr_rsp_complete
  ,mcif2sdp_wr_rsp_complete
  ,noc2mcif_axi_b_bready
  ,pdp2mcif_wr_req_ready
  ,rbk2mcif_wr_req_ready
  ,sdp2mcif_wr_req_ready
  );



input nvdla_core_clk;
input nvdla_core_rstn;
input bdma2mcif_wr_req_valid;
output bdma2mcif_wr_req_ready;
input [514:0] bdma2mcif_wr_req_pd;
input cdp2mcif_wr_req_valid;
output cdp2mcif_wr_req_ready;
input [514:0] cdp2mcif_wr_req_pd;
output mcif2bdma_wr_rsp_complete;
output mcif2cdp_wr_rsp_complete;
output mcif2noc_axi_aw_awvalid;
input mcif2noc_axi_aw_awready;
output [7:0] mcif2noc_axi_aw_awid;
output [3:0] mcif2noc_axi_aw_awlen;
output [63:0] mcif2noc_axi_aw_awaddr;
output mcif2noc_axi_w_wvalid;
input mcif2noc_axi_w_wready;
output [511:0] mcif2noc_axi_w_wdata;
output [63:0] mcif2noc_axi_w_wstrb;
output mcif2noc_axi_w_wlast;
output mcif2pdp_wr_rsp_complete;
output mcif2rbk_wr_rsp_complete;
output mcif2sdp_wr_rsp_complete;
input noc2mcif_axi_b_bvalid;
output noc2mcif_axi_b_bready;
input [7:0] noc2mcif_axi_b_bid;
input pdp2mcif_wr_req_valid;
output pdp2mcif_wr_req_ready;
input [514:0] pdp2mcif_wr_req_pd;
input [31:0] pwrbus_ram_pd;
input rbk2mcif_wr_req_valid;
output rbk2mcif_wr_req_ready;
input [514:0] rbk2mcif_wr_req_pd;
input sdp2mcif_wr_req_valid;
output sdp2mcif_wr_req_ready;
input [514:0] sdp2mcif_wr_req_pd;
input [7:0] reg2dp_wr_os_cnt;
input [7:0] reg2dp_wr_weight_bdma;
input [7:0] reg2dp_wr_weight_cdp;
input [7:0] reg2dp_wr_weight_pdp;
input [7:0] reg2dp_wr_weight_rbk;
input [7:0] reg2dp_wr_weight_sdp;
wire [2:0] cq_rd0_pd;
wire cq_rd0_prdy;
wire cq_rd0_pvld;
wire [2:0] cq_rd1_pd;
wire cq_rd1_prdy;
wire cq_rd1_pvld;
wire [2:0] cq_rd2_pd;
wire cq_rd2_prdy;
wire cq_rd2_pvld;
wire [2:0] cq_rd3_pd;
wire cq_rd3_prdy;
wire cq_rd3_pvld;
wire [2:0] cq_rd4_pd;
wire cq_rd4_prdy;
wire cq_rd4_pvld;
wire [2:0] cq_wr_pd;
wire cq_wr_prdy;
wire cq_wr_pvld;
wire [2:0] cq_wr_thread_id;
wire [1:0] eg2ig_axi_len;
wire eg2ig_axi_vld;








NV_NVDLA_MCIF_WRITE_ig u_ig (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.bdma2mcif_wr_req_valid (bdma2mcif_wr_req_valid)
  ,.bdma2mcif_wr_req_ready (bdma2mcif_wr_req_ready)
  ,.bdma2mcif_wr_req_pd (bdma2mcif_wr_req_pd[514:0])
  ,.cdp2mcif_wr_req_valid (cdp2mcif_wr_req_valid)
  ,.cdp2mcif_wr_req_ready (cdp2mcif_wr_req_ready)
  ,.cdp2mcif_wr_req_pd (cdp2mcif_wr_req_pd[514:0])
  ,.cq_wr_pvld (cq_wr_pvld)
  ,.cq_wr_prdy (cq_wr_prdy)
  ,.cq_wr_thread_id (cq_wr_thread_id[2:0])
  ,.cq_wr_pd (cq_wr_pd[2:0])
  ,.mcif2noc_axi_aw_awvalid (mcif2noc_axi_aw_awvalid)
  ,.mcif2noc_axi_aw_awready (mcif2noc_axi_aw_awready)
  ,.mcif2noc_axi_aw_awid (mcif2noc_axi_aw_awid[7:0])
  ,.mcif2noc_axi_aw_awlen (mcif2noc_axi_aw_awlen[3:0])
  ,.mcif2noc_axi_aw_awaddr (mcif2noc_axi_aw_awaddr[63:0])
  ,.mcif2noc_axi_w_wvalid (mcif2noc_axi_w_wvalid)
  ,.mcif2noc_axi_w_wready (mcif2noc_axi_w_wready)
  ,.mcif2noc_axi_w_wdata (mcif2noc_axi_w_wdata[511:0])
  ,.mcif2noc_axi_w_wstrb (mcif2noc_axi_w_wstrb[63:0])
  ,.mcif2noc_axi_w_wlast (mcif2noc_axi_w_wlast)
  ,.pdp2mcif_wr_req_valid (pdp2mcif_wr_req_valid)
  ,.pdp2mcif_wr_req_ready (pdp2mcif_wr_req_ready)
  ,.pdp2mcif_wr_req_pd (pdp2mcif_wr_req_pd[514:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  ,.rbk2mcif_wr_req_valid (rbk2mcif_wr_req_valid)
  ,.rbk2mcif_wr_req_ready (rbk2mcif_wr_req_ready)
  ,.rbk2mcif_wr_req_pd (rbk2mcif_wr_req_pd[514:0])
  ,.sdp2mcif_wr_req_valid (sdp2mcif_wr_req_valid)
  ,.sdp2mcif_wr_req_ready (sdp2mcif_wr_req_ready)
  ,.sdp2mcif_wr_req_pd (sdp2mcif_wr_req_pd[514:0])
  ,.reg2dp_wr_os_cnt (reg2dp_wr_os_cnt[7:0])
  ,.reg2dp_wr_weight_bdma (reg2dp_wr_weight_bdma[7:0])
  ,.reg2dp_wr_weight_cdp (reg2dp_wr_weight_cdp[7:0])
  ,.reg2dp_wr_weight_pdp (reg2dp_wr_weight_pdp[7:0])
  ,.reg2dp_wr_weight_rbk (reg2dp_wr_weight_rbk[7:0])
  ,.reg2dp_wr_weight_sdp (reg2dp_wr_weight_sdp[7:0])
  ,.eg2ig_axi_len (eg2ig_axi_len[1:0])
  ,.eg2ig_axi_vld (eg2ig_axi_vld)
  );
NV_NVDLA_MCIF_WRITE_eg u_eg (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.mcif2sdp_wr_rsp_complete (mcif2sdp_wr_rsp_complete)
  ,.mcif2cdp_wr_rsp_complete (mcif2cdp_wr_rsp_complete)
  ,.mcif2pdp_wr_rsp_complete (mcif2pdp_wr_rsp_complete)
  ,.mcif2bdma_wr_rsp_complete (mcif2bdma_wr_rsp_complete)
  ,.mcif2rbk_wr_rsp_complete (mcif2rbk_wr_rsp_complete)
  ,.cq_rd0_pvld (cq_rd0_pvld)
  ,.cq_rd0_prdy (cq_rd0_prdy)
  ,.cq_rd0_pd (cq_rd0_pd[2:0])
  ,.cq_rd1_pvld (cq_rd1_pvld)
  ,.cq_rd1_prdy (cq_rd1_prdy)
  ,.cq_rd1_pd (cq_rd1_pd[2:0])
  ,.cq_rd2_pvld (cq_rd2_pvld)
  ,.cq_rd2_prdy (cq_rd2_prdy)
  ,.cq_rd2_pd (cq_rd2_pd[2:0])
  ,.cq_rd3_pvld (cq_rd3_pvld)
  ,.cq_rd3_prdy (cq_rd3_prdy)
  ,.cq_rd3_pd (cq_rd3_pd[2:0])
  ,.cq_rd4_pvld (cq_rd4_pvld)
  ,.cq_rd4_prdy (cq_rd4_prdy)
  ,.cq_rd4_pd (cq_rd4_pd[2:0])
  ,.noc2mcif_axi_b_bvalid (noc2mcif_axi_b_bvalid)
  ,.noc2mcif_axi_b_bready (noc2mcif_axi_b_bready)
  ,.noc2mcif_axi_b_bid (noc2mcif_axi_b_bid[7:0])
  ,.eg2ig_axi_len (eg2ig_axi_len[1:0])
  ,.eg2ig_axi_vld (eg2ig_axi_vld)
  );
NV_NVDLA_MCIF_WRITE_cq u_cq (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.cq_wr_prdy (cq_wr_prdy)
  ,.cq_wr_pvld (cq_wr_pvld)
  ,.cq_wr_thread_id (cq_wr_thread_id[2:0])
  ,.cq_wr_pd (cq_wr_pd[2:0])
  ,.cq_rd0_prdy (cq_rd0_prdy)
  ,.cq_rd0_pvld (cq_rd0_pvld)
  ,.cq_rd0_pd (cq_rd0_pd[2:0])
  ,.cq_rd1_prdy (cq_rd1_prdy)
  ,.cq_rd1_pvld (cq_rd1_pvld)
  ,.cq_rd1_pd (cq_rd1_pd[2:0])
  ,.cq_rd2_prdy (cq_rd2_prdy)
  ,.cq_rd2_pvld (cq_rd2_pvld)
  ,.cq_rd2_pd (cq_rd2_pd[2:0])
  ,.cq_rd3_prdy (cq_rd3_prdy)
  ,.cq_rd3_pvld (cq_rd3_pvld)
  ,.cq_rd3_pd (cq_rd3_pd[2:0])
  ,.cq_rd4_prdy (cq_rd4_prdy)
  ,.cq_rd4_pvld (cq_rd4_pvld)
  ,.cq_rd4_pd (cq_rd4_pd[2:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  );
endmodule
module NV_NVDLA_MCIF_write (
   bdma2mcif_wr_req_pd
  ,bdma2mcif_wr_req_valid
  ,cdp2mcif_wr_req_pd
  ,cdp2mcif_wr_req_valid
  ,mcif2noc_axi_aw_awready
  ,mcif2noc_axi_w_wready
  ,noc2mcif_axi_b_bid
  ,noc2mcif_axi_b_bvalid
  ,nvdla_core_clk
  ,nvdla_core_rstn
  ,pdp2mcif_wr_req_pd
  ,pdp2mcif_wr_req_valid
  ,pwrbus_ram_pd
  ,rbk2mcif_wr_req_pd
  ,rbk2mcif_wr_req_valid
  ,reg2dp_wr_os_cnt
  ,reg2dp_wr_weight_bdma
  ,reg2dp_wr_weight_cdp
  ,reg2dp_wr_weight_pdp
  ,reg2dp_wr_weight_rbk
  ,reg2dp_wr_weight_sdp
  ,sdp2mcif_wr_req_pd
  ,sdp2mcif_wr_req_valid
  ,bdma2mcif_wr_req_ready
  ,cdp2mcif_wr_req_ready
  ,mcif2bdma_wr_rsp_complete
  ,mcif2cdp_wr_rsp_complete
  ,mcif2noc_axi_aw_awaddr
  ,mcif2noc_axi_aw_awid
  ,mcif2noc_axi_aw_awlen
  ,mcif2noc_axi_aw_awvalid
  ,mcif2noc_axi_w_wdata
  ,mcif2noc_axi_w_wlast
  ,mcif2noc_axi_w_wstrb
  ,mcif2noc_axi_w_wvalid
  ,mcif2pdp_wr_rsp_complete
  ,mcif2rbk_wr_rsp_complete
  ,mcif2sdp_wr_rsp_complete
  ,noc2mcif_axi_b_bready
  ,pdp2mcif_wr_req_ready
  ,rbk2mcif_wr_req_ready
  ,sdp2mcif_wr_req_ready
  );




input nvdla_core_clk;
input nvdla_core_rstn;
input bdma2mcif_wr_req_valid;
output bdma2mcif_wr_req_ready;
input [514:0] bdma2mcif_wr_req_pd;
input cdp2mcif_wr_req_valid;
output cdp2mcif_wr_req_ready;
input [514:0] cdp2mcif_wr_req_pd;
output mcif2bdma_wr_rsp_complete;
output mcif2cdp_wr_rsp_complete;
output mcif2noc_axi_aw_awvalid;
input mcif2noc_axi_aw_awready;
output [7:0] mcif2noc_axi_aw_awid;
output [3:0] mcif2noc_axi_aw_awlen;
output [63:0] mcif2noc_axi_aw_awaddr;
output mcif2noc_axi_w_wvalid;
input mcif2noc_axi_w_wready;
output [511:0] mcif2noc_axi_w_wdata;
output [63:0] mcif2noc_axi_w_wstrb;
output mcif2noc_axi_w_wlast;
output mcif2pdp_wr_rsp_complete;
output mcif2rbk_wr_rsp_complete;
output mcif2sdp_wr_rsp_complete;
input noc2mcif_axi_b_bvalid;
output noc2mcif_axi_b_bready;
input [7:0] noc2mcif_axi_b_bid;
input pdp2mcif_wr_req_valid;
output pdp2mcif_wr_req_ready;
input [514:0] pdp2mcif_wr_req_pd;
input [31:0] pwrbus_ram_pd;
input rbk2mcif_wr_req_valid;
output rbk2mcif_wr_req_ready;
input [514:0] rbk2mcif_wr_req_pd;
input sdp2mcif_wr_req_valid;
output sdp2mcif_wr_req_ready;
input [514:0] sdp2mcif_wr_req_pd;
input [7:0] reg2dp_wr_os_cnt;
input [7:0] reg2dp_wr_weight_bdma;
input [7:0] reg2dp_wr_weight_cdp;
input [7:0] reg2dp_wr_weight_pdp;
input [7:0] reg2dp_wr_weight_rbk;
input [7:0] reg2dp_wr_weight_sdp;
wire [2:0] cq_rd0_pd;
wire cq_rd0_prdy;
wire cq_rd0_pvld;
wire [2:0] cq_rd1_pd;
wire cq_rd1_prdy;
wire cq_rd1_pvld;
wire [2:0] cq_rd2_pd;
wire cq_rd2_prdy;
wire cq_rd2_pvld;
wire [2:0] cq_rd3_pd;
wire cq_rd3_prdy;
wire cq_rd3_pvld;
wire [2:0] cq_rd4_pd;
wire cq_rd4_prdy;
wire cq_rd4_pvld;
wire [2:0] cq_wr_pd;
wire cq_wr_prdy;
wire cq_wr_pvld;
wire [2:0] cq_wr_thread_id;
wire [1:0] eg2ig_axi_len;
wire eg2ig_axi_vld;








NV_NVDLA_MCIF_WRITE_ig u_ig (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.bdma2mcif_wr_req_valid (bdma2mcif_wr_req_valid)
  ,.bdma2mcif_wr_req_ready (bdma2mcif_wr_req_ready)
  ,.bdma2mcif_wr_req_pd (bdma2mcif_wr_req_pd[514:0])
  ,.cdp2mcif_wr_req_valid (cdp2mcif_wr_req_valid)
  ,.cdp2mcif_wr_req_ready (cdp2mcif_wr_req_ready)
  ,.cdp2mcif_wr_req_pd (cdp2mcif_wr_req_pd[514:0])
  ,.cq_wr_pvld (cq_wr_pvld)
  ,.cq_wr_prdy (cq_wr_prdy)
  ,.cq_wr_thread_id (cq_wr_thread_id[2:0])
  ,.cq_wr_pd (cq_wr_pd[2:0])
  ,.mcif2noc_axi_aw_awvalid (mcif2noc_axi_aw_awvalid)
  ,.mcif2noc_axi_aw_awready (mcif2noc_axi_aw_awready)
  ,.mcif2noc_axi_aw_awid (mcif2noc_axi_aw_awid[7:0])
  ,.mcif2noc_axi_aw_awlen (mcif2noc_axi_aw_awlen[3:0])
  ,.mcif2noc_axi_aw_awaddr (mcif2noc_axi_aw_awaddr[63:0])
  ,.mcif2noc_axi_w_wvalid (mcif2noc_axi_w_wvalid)
  ,.mcif2noc_axi_w_wready (mcif2noc_axi_w_wready)
  ,.mcif2noc_axi_w_wdata (mcif2noc_axi_w_wdata[511:0])
  ,.mcif2noc_axi_w_wstrb (mcif2noc_axi_w_wstrb[63:0])
  ,.mcif2noc_axi_w_wlast (mcif2noc_axi_w_wlast)
  ,.pdp2mcif_wr_req_valid (pdp2mcif_wr_req_valid)
  ,.pdp2mcif_wr_req_ready (pdp2mcif_wr_req_ready)
  ,.pdp2mcif_wr_req_pd (pdp2mcif_wr_req_pd[514:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  ,.rbk2mcif_wr_req_valid (rbk2mcif_wr_req_valid)
  ,.rbk2mcif_wr_req_ready (rbk2mcif_wr_req_ready)
  ,.rbk2mcif_wr_req_pd (rbk2mcif_wr_req_pd[514:0])
  ,.sdp2mcif_wr_req_valid (sdp2mcif_wr_req_valid)
  ,.sdp2mcif_wr_req_ready (sdp2mcif_wr_req_ready)
  ,.sdp2mcif_wr_req_pd (sdp2mcif_wr_req_pd[514:0])
  ,.reg2dp_wr_os_cnt (reg2dp_wr_os_cnt[7:0])
  ,.reg2dp_wr_weight_bdma (reg2dp_wr_weight_bdma[7:0])
  ,.reg2dp_wr_weight_cdp (reg2dp_wr_weight_cdp[7:0])
  ,.reg2dp_wr_weight_pdp (reg2dp_wr_weight_pdp[7:0])
  ,.reg2dp_wr_weight_rbk (reg2dp_wr_weight_rbk[7:0])
  ,.reg2dp_wr_weight_sdp (reg2dp_wr_weight_sdp[7:0])
  ,.eg2ig_axi_len (eg2ig_axi_len[1:0])
  ,.eg2ig_axi_vld (eg2ig_axi_vld)
  );
NV_NVDLA_MCIF_WRITE_eg u_eg (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.mcif2sdp_wr_rsp_complete (mcif2sdp_wr_rsp_complete)
  ,.mcif2cdp_wr_rsp_complete (mcif2cdp_wr_rsp_complete)
  ,.mcif2pdp_wr_rsp_complete (mcif2pdp_wr_rsp_complete)
  ,.mcif2bdma_wr_rsp_complete (mcif2bdma_wr_rsp_complete)
  ,.mcif2rbk_wr_rsp_complete (mcif2rbk_wr_rsp_complete)
  ,.cq_rd0_pvld (cq_rd0_pvld)
  ,.cq_rd0_prdy (cq_rd0_prdy)
  ,.cq_rd0_pd (cq_rd0_pd[2:0])
  ,.cq_rd1_pvld (cq_rd1_pvld)
  ,.cq_rd1_prdy (cq_rd1_prdy)
  ,.cq_rd1_pd (cq_rd1_pd[2:0])
  ,.cq_rd2_pvld (cq_rd2_pvld)
  ,.cq_rd2_prdy (cq_rd2_prdy)
  ,.cq_rd2_pd (cq_rd2_pd[2:0])
  ,.cq_rd3_pvld (cq_rd3_pvld)
  ,.cq_rd3_prdy (cq_rd3_prdy)
  ,.cq_rd3_pd (cq_rd3_pd[2:0])
  ,.cq_rd4_pvld (cq_rd4_pvld)
  ,.cq_rd4_prdy (cq_rd4_prdy)
  ,.cq_rd4_pd (cq_rd4_pd[2:0])
  ,.noc2mcif_axi_b_bvalid (noc2mcif_axi_b_bvalid)
  ,.noc2mcif_axi_b_bready (noc2mcif_axi_b_bready)
  ,.noc2mcif_axi_b_bid (noc2mcif_axi_b_bid[7:0])
  ,.eg2ig_axi_len (eg2ig_axi_len[1:0])
  ,.eg2ig_axi_vld (eg2ig_axi_vld)
  );
NV_NVDLA_MCIF_WRITE_cq u_cq (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.cq_wr_prdy (cq_wr_prdy)
  ,.cq_wr_pvld (cq_wr_pvld)
  ,.cq_wr_thread_id (cq_wr_thread_id[2:0])
  ,.cq_wr_pd (cq_wr_pd[2:0])
  ,.cq_rd0_prdy (cq_rd0_prdy)
  ,.cq_rd0_pvld (cq_rd0_pvld)
  ,.cq_rd0_pd (cq_rd0_pd[2:0])
  ,.cq_rd1_prdy (cq_rd1_prdy)
  ,.cq_rd1_pvld (cq_rd1_pvld)
  ,.cq_rd1_pd (cq_rd1_pd[2:0])
  ,.cq_rd2_prdy (cq_rd2_prdy)
  ,.cq_rd2_pvld (cq_rd2_pvld)
  ,.cq_rd2_pd (cq_rd2_pd[2:0])
  ,.cq_rd3_prdy (cq_rd3_prdy)
  ,.cq_rd3_pvld (cq_rd3_pvld)
  ,.cq_rd3_pd (cq_rd3_pd[2:0])
  ,.cq_rd4_prdy (cq_rd4_prdy)
  ,.cq_rd4_pvld (cq_rd4_pvld)
  ,.cq_rd4_pd (cq_rd4_pd[2:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  );
endmodule