data/full_repos/permissive/507203156/03-源代码/sift_tb/tf_top.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb/tf_top.v:41: Unsupported: Ignoring delay on this delayed statement.\n #10000\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb/tf_top.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #10000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb/tf_top.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #10000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb/tf_top.v:61: Unsupported: Ignoring delay on this delayed statement.\n    #10000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb/tf_top.v:66: Unsupported: Ignoring delay on this delayed statement.\n    #10000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb/tf_top.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #10000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb/tf_top.v:76: Unsupported: Ignoring delay on this delayed statement.\n    #10000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb/tf_top.v:81: Unsupported: Ignoring delay on this delayed statement.\n    #10000\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb/tf_top.v:88: Unsupported: Ignoring delay on this delayed statement.\nalways #CLOCK_FRAME clk_sys=~clk_sys;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb/tf_top.v:96: Unsupported: Ignoring delay on this delayed statement.\n                # CLOCK_FRAME;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb/tf_top.v:97: Unsupported: Ignoring delay on this delayed statement.\n                # CLOCK_FRAME;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb/tf_top.v:102: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s CONST \'7\'bzzzzzzz\' generates 7 bits.\n                                                                                      : ... In instance tf_top\nassign EPP_Data = (EPP_DataStrobe0==0 && EPP_Write0==0) ? input_data : 7\'bzzzzzzz;\n                                                        ^\n%Error: data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb/tf_top.v:105: Cannot find file containing module: \'sift_top\'\n sift_top uut (\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb,data/full_repos/permissive/507203156/sift_top\n             data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb,data/full_repos/permissive/507203156/sift_top.v\n             data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb,data/full_repos/permissive/507203156/sift_top.sv\n             sift_top\n             sift_top.v\n             sift_top.sv\n             obj_dir/sift_top\n             obj_dir/sift_top.v\n             obj_dir/sift_top.sv\n%Error: Exiting due to 1 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tf_top;


reg clk_sys;
reg rst_sys;
reg EPP_Write0;
reg EPP_DataStrobe0;
reg EPP_Reset0;
reg EPP_AddressStrobe0;


wire EPP_Interrupt;
wire EPP_Wait;
wire led1;
wire led2;


wire [7:0] EPP_Data;
   

reg [7:0] input_data; 
integer file;
reg     [7:0]   data_img[262144:0];

parameter   CLOCK_FRAME = 10;

initial begin

	clk_sys = 0;
	rst_sys = 0;
	EPP_Write0 = 0;
	EPP_DataStrobe0 = 0;
	EPP_Reset0 = 0;
	EPP_AddressStrobe0 = 0;
       

	#10000
	rst_sys=1;
    EPP_Reset0 = 1;
    EPP_DataStrobe0 = 0;
    EPP_AddressStrobe0 = 1;
    EPP_Write0 = 1;
       


    
    #10000
    EPP_DataStrobe0 = 0;
    EPP_AddressStrobe0 = 1;
    EPP_Write0 = 0;
    
    #10000
    EPP_DataStrobe0 = 1;
    EPP_AddressStrobe0 = 0;
    EPP_Write0 = 1;
    
    #10000
    EPP_DataStrobe0 = 1;
    EPP_AddressStrobe0 = 0;
    EPP_Write0 = 0;
    
    #10000
    EPP_DataStrobe0 = 0;
    EPP_AddressStrobe0 = 0;
    EPP_Write0 = 0;
    
    #10000
    EPP_DataStrobe0 = 0;
    EPP_AddressStrobe0 = 0;
    EPP_Write0 = 1;
    
    #10000
    EPP_DataStrobe0 = 1;
    EPP_AddressStrobe0 = 1;
    EPP_Write0 = 0;
    
    #10000
    EPP_DataStrobe0 = 1;
    EPP_AddressStrobe0 = 1;
    EPP_Write0 = 1;
    
end

always #CLOCK_FRAME clk_sys=~clk_sys;

task    import_img_data();
    integer k;
    begin    
        for(k=0; k<262144; k=k+1)
            begin
                input_data = data_img[k];    
                # CLOCK_FRAME;
                # CLOCK_FRAME;
            end
    end    
endtask 

assign EPP_Data = (EPP_DataStrobe0==0 && EPP_Write0==0) ? input_data : 7'bzzzzzzz;


	sift_top uut (
		.clk_sys(clk_sys), 
		.rst_sys(rst_sys), 
		.EPP_Write0(EPP_Write0), 
		.EPP_DataStrobe0(EPP_DataStrobe0), 
		.EPP_Reset0(EPP_Reset0), 
		.EPP_AddressStrobe0(EPP_AddressStrobe0), 
		.EPP_Data(EPP_Data), 
		.EPP_Interrupt(EPP_Interrupt), 
		.EPP_Wait(EPP_Wait), 
		.led1(led1), 
		.led2(led2)
	);
 
endmodule
module tf_top;



reg clk_sys;
reg rst_sys;
reg EPP_Write0;
reg EPP_DataStrobe0;
reg EPP_Reset0;
reg EPP_AddressStrobe0;


wire EPP_Interrupt;
wire EPP_Wait;
wire led1;
wire led2;


wire [7:0] EPP_Data;
   

reg [7:0] input_data; 
integer file;
reg     [7:0]   data_img[262144:0];

parameter   CLOCK_FRAME = 10;

initial begin

	clk_sys = 0;
	rst_sys = 0;
	EPP_Write0 = 0;
	EPP_DataStrobe0 = 0;
	EPP_Reset0 = 0;
	EPP_AddressStrobe0 = 0;
       

	#10000
	rst_sys=1;
    EPP_Reset0 = 1;
    EPP_DataStrobe0 = 0;
    EPP_AddressStrobe0 = 1;
    EPP_Write0 = 1;
       


    
    #10000
    EPP_DataStrobe0 = 0;
    EPP_AddressStrobe0 = 1;
    EPP_Write0 = 0;
    
    #10000
    EPP_DataStrobe0 = 1;
    EPP_AddressStrobe0 = 0;
    EPP_Write0 = 1;
    
    #10000
    EPP_DataStrobe0 = 1;
    EPP_AddressStrobe0 = 0;
    EPP_Write0 = 0;
    
    #10000
    EPP_DataStrobe0 = 0;
    EPP_AddressStrobe0 = 0;
    EPP_Write0 = 0;
    
    #10000
    EPP_DataStrobe0 = 0;
    EPP_AddressStrobe0 = 0;
    EPP_Write0 = 1;
    
    #10000
    EPP_DataStrobe0 = 1;
    EPP_AddressStrobe0 = 1;
    EPP_Write0 = 0;
    
    #10000
    EPP_DataStrobe0 = 1;
    EPP_AddressStrobe0 = 1;
    EPP_Write0 = 1;
    
end

always #CLOCK_FRAME clk_sys=~clk_sys;

task    import_img_data();
    integer k;
    begin    
        for(k=0; k<262144; k=k+1)
            begin
                input_data = data_img[k];    
                # CLOCK_FRAME;
                # CLOCK_FRAME;
            end
    end    
endtask 

assign EPP_Data = (EPP_DataStrobe0==0 && EPP_Write0==0) ? input_data : 7'bzzzzzzz;


	sift_top uut (
		.clk_sys(clk_sys), 
		.rst_sys(rst_sys), 
		.EPP_Write0(EPP_Write0), 
		.EPP_DataStrobe0(EPP_DataStrobe0), 
		.EPP_Reset0(EPP_Reset0), 
		.EPP_AddressStrobe0(EPP_AddressStrobe0), 
		.EPP_Data(EPP_Data), 
		.EPP_Interrupt(EPP_Interrupt), 
		.EPP_Wait(EPP_Wait), 
		.led1(led1), 
		.led2(led2)
	);
 
endmodule