data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/router_output_port_lookup_v1_0_0/hdl/preprocess_control.v
data/verilator_xmls/360ab213-6004-4a8a-b338-6f9571423942.xml
module preprocess_control
    #(parameter C_S_AXIS_DATA_WIDTH=256
      )
   (
    
    input [C_S_AXIS_DATA_WIDTH-1:0]    tdata,
    input			       valid,
    input			       tlast,


    output reg                         word_IP_DST_HI,
    output reg                         word_IP_DST_LO,



    input                              reset,
    input                              clk
   );

   function integer log2;
      input integer number;
      begin
         log2=0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
   endfunction



   localparam WORD_1           = 1;
   localparam WORD_2           = 2;
   localparam WAIT_EOP         = 4;


   reg [2:0]                            state, state_next;



   always @(*) begin
      state_next = state;
      word_IP_DST_HI = 0;
      word_IP_DST_LO = 0;

      case(state)
        WORD_1: begin
           if(valid) begin
              word_IP_DST_HI = 1;
              state_next     = WORD_2;
           end
        end

        WORD_2: begin
           if(valid) begin
              word_IP_DST_LO = 1;
	      if(tlast)
		state_next = WORD_1;
	      else
              	state_next = WAIT_EOP;
           end
        end

        WAIT_EOP: begin
           if(valid && tlast) begin
              state_next = WORD_1;
           end
        end
      endcase
   end

   always@(posedge clk) begin
      if(reset) begin
         state <= WORD_1;
      end
      else begin
         state <= state_next;
      end
   end

endmodule
module preprocess_control
    #(parameter C_S_AXIS_DATA_WIDTH=256
      )
   (
    
    input [C_S_AXIS_DATA_WIDTH-1:0]    tdata,
    input			       valid,
    input			       tlast,


    output reg                         word_IP_DST_HI,
    output reg                         word_IP_DST_LO,



    input                              reset,
    input                              clk
   );


   function integer log2;
      input integer number;
      begin
         log2=0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
   endfunction



   localparam WORD_1           = 1;
   localparam WORD_2           = 2;
   localparam WAIT_EOP         = 4;


   reg [2:0]                            state, state_next;



   always @(*) begin
      state_next = state;
      word_IP_DST_HI = 0;
      word_IP_DST_LO = 0;

      case(state)
        WORD_1: begin
           if(valid) begin
              word_IP_DST_HI = 1;
              state_next     = WORD_2;
           end
        end

        WORD_2: begin
           if(valid) begin
              word_IP_DST_LO = 1;
	      if(tlast)
		state_next = WORD_1;
	      else
              	state_next = WAIT_EOP;
           end
        end

        WAIT_EOP: begin
           if(valid && tlast) begin
              state_next = WORD_1;
           end
        end
      endcase
   end

   always@(posedge clk) begin
      if(reset) begin
         state <= WORD_1;
      end
      else begin
         state <= state_next;
      end
   end

endmodule