data/full_repos/permissive/42434302/ivltests/pr1476440.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1476440.v:15: Unsupported: Ignoring delay on this delayed statement.\nalways #2 ck <= !ck;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();
reg ck;
integer cnt;
real tval;

initial begin
ck <= 0;
cnt <= 0;
tval <= 0.0;
end


always #2 ck <= !ck;


always @(posedge ck) begin
cnt <= cnt + 1;
tval <= $realtime;
$display ("tval = %g", tval);

if (cnt >= 5) begin
$finish;
end
end

endmodule
module test();

reg ck;
integer cnt;
real tval;

initial begin
ck <= 0;
cnt <= 0;
tval <= 0.0;
end


always #2 ck <= !ck;


always @(posedge ck) begin
cnt <= cnt + 1;
tval <= $realtime;
$display ("tval = %g", tval);

if (cnt >= 5) begin
$finish;
end
end

endmodule