data/full_repos/permissive/433640910/RateDivider/500hertzdivider.v
data/verilator_xmls/b39f86ae-6406-42e9-ab5c-066d899b9777.xml
module counter(Clock, Clear_b, Enable, q);
	input Clock, Clear_b, Enable;
	output reg[3:0] q;
	
	always@(posedge Clock)
		begin
			if(Clear_b  == 0)
				q <= 0;
			else if(Enable)
				q <= q + 1;
		end

endmodule
module counter(Clock, Clear_b, Enable, q);

	input Clock, Clear_b, Enable;
	output reg[3:0] q;
	
	always@(posedge Clock)
		begin
			if(Clear_b  == 0)
				q <= 0;
			else if(Enable)
				q <= q + 1;
		end

endmodule