data/full_repos/permissive/421048855/Circuits/Sequential Logic/Counters/Count clock.v
1: b'%Error: Cannot find file containing module: Logic/Counters,data/full_repos/permissive/421048855\n        ... Looked in:\n             data/full_repos/permissive/421048855/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/421048855\n             data/full_repos/permissive/421048855/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/421048855.v\n             data/full_repos/permissive/421048855/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/421048855.sv\n             Logic/Counters,data/full_repos/permissive/421048855\n             Logic/Counters,data/full_repos/permissive/421048855.v\n             Logic/Counters,data/full_repos/permissive/421048855.sv\n             obj_dir/Logic/Counters,data/full_repos/permissive/421048855\n             obj_dir/Logic/Counters,data/full_repos/permissive/421048855.v\n             obj_dir/Logic/Counters,data/full_repos/permissive/421048855.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/421048855/Circuits/Sequential\n%Error: Cannot find file containing module: Logic/Counters/Count\n%Error: Cannot find file containing module: clock.v\n%Error: Exiting due to 4 error(s)\n'
module cnt_hh_one(
input clk,
input reset,
input ena,
input hh_ten,
output reg [3:0] hh_one,
output reg over
);
always @(posedge clk) begin
	if(reset) begin
		hh_one <= 'd2;
	end
	else if(ena) begin
		if(hh_ten == 'd1 && hh_one == 'd2) begin
			hh_one <= 'd1;
			over <= 'b1;
		end
		else if(hh_one >= 'd9) begin
			hh_one <= 'd0;
			over <= 'b1;
		end
		else begin
			hh_one <= hh_one + 'd1;
			over <= 'b0;
		end
	end
end
endmodule
module cnt_hh_one(
input clk,
input reset,
input ena,
input hh_ten,
output reg [3:0] hh_one,
output reg over
);

always @(posedge clk) begin
	if(reset) begin
		hh_one <= 'd2;
	end
	else if(ena) begin
		if(hh_ten == 'd1 && hh_one == 'd2) begin
			hh_one <= 'd1;
			over <= 'b1;
		end
		else if(hh_one >= 'd9) begin
			hh_one <= 'd0;
			over <= 'b1;
		end
		else begin
			hh_one <= hh_one + 'd1;
			over <= 'b0;
		end
	end
end
endmodule