data/full_repos/permissive/414664427/my_keypad/uarttx.v
1: b'%Warning-WIDTH: data/full_repos/permissive/414664427/my_keypad/uarttx.v:85: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'tx_bit_cycle_cnt\' generates 11 bits.\n                                                                          : ... In instance uarttx\n        if (tx_bit_cycle_cnt == (CYCLES4BIT - 1)) begin\n                             ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/414664427/my_keypad/uarttx.v:97: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'tx_bit_cycle_cnt\' generates 11 bits.\n                                                                          : ... In instance uarttx\n      if (tx_bit_cycle_cnt == (CYCLES4BIT -1)) begin\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/414664427/my_keypad/uarttx.v:113: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'tx_bit_cycle_cnt\' generates 11 bits.\n                                                                           : ... In instance uarttx\n      if (tx_bit_cycle_cnt == (CYCLES4BIT -1)) begin\n                           ^~\n%Error: Exiting due to 3 warning(s)\n'
module uarttx(clk, uart_tx, tx_ready, tx_trigger, tx_data, resetn);
input clk;
input tx_trigger;
output uart_tx;
output tx_ready;
input  resetn;
input [7:0] tx_data;



parameter CLK_FREQ = 12_000_000;
parameter BAUDRATE = 9600;
parameter CYCLES4BIT = $rtoi(CLK_FREQ/BAUDRATE);
parameter BIT_COUNTER_WIDTH = $clog2(CYCLES4BIT);
localparam HALF_CYCLES4BIT = $rtoi(CYCLES4BIT / 2);
initial begin
  $display("CYCLES4BIT per bit:\n", CYCLES4BIT);
  $display("Half CYCLES4BIT per bit:\n", HALF_CYCLES4BIT);
  $display("RX state bits:\n", TX_STATE_BITS);
  $display("Width bits cycle counter per bit:\n", BIT_COUNTER_WIDTH);
end

reg [$clog2(TX_STOP) -1:0]tx_state;
localparam TX_IDLE  = 0;
localparam TX_START = 1;
localparam TX_DATA =  2;
localparam TX_STOP  = 3;
localparam TX_STATE_BITS = $clog2(TX_STOP);

reg tx_ready;
reg tx = 1'b1;
reg [BIT_COUNTER_WIDTH - 1: 0] tx_bit_cycle_cnt = 0;
reg [2:0] tx_bit_cnt = 0;

assign uart_tx = tx;

always @(posedge clk) begin

  if (!resetn) begin
    tx_state <= TX_IDLE;
    tx_ready <= 1'b0;
    tx_bit_cycle_cnt <= 0;
    tx_bit_cnt <= 0;
    tx <= 1'b1;
  end else begin

    case (tx_state)

      TX_IDLE: begin
        tx_ready <= 0;
        if (tx_trigger == 1'b1) begin 
          tx_state <= TX_START;
          tx <= 1'b1;
          tx_bit_cycle_cnt <= 0;
        end
      end

      TX_START: begin
        tx_bit_cycle_cnt <= tx_bit_cycle_cnt + 1;
        tx <= 1'b0;

        if (tx_bit_cycle_cnt == (CYCLES4BIT - 1)) begin
          tx_bit_cnt <= 0;
          tx_bit_cycle_cnt <= 0;
          tx_state <= TX_DATA;
        end else 
          tx_state <= TX_START;
      end

    TX_DATA: begin
      tx_bit_cycle_cnt <= tx_bit_cycle_cnt + 1;
      tx <= tx_data[tx_bit_cnt];

      if (tx_bit_cycle_cnt == (CYCLES4BIT -1)) begin
        tx_bit_cycle_cnt <= 0;
        tx_bit_cnt <= tx_bit_cnt + 1;

        if (tx_bit_cnt == 7) begin
          tx_state <= TX_STOP;
        end else 
          tx_state <= TX_DATA;

      end else 
        tx_state <= TX_DATA;
    end

    TX_STOP: begin
      tx <= 1'b1;
      tx_bit_cycle_cnt <= tx_bit_cycle_cnt + 1;
      if (tx_bit_cycle_cnt == (CYCLES4BIT -1)) begin
        tx_ready <= 1;
        tx_state <= TX_IDLE;
      end else
        tx_state <= TX_STOP;
    end

    default:
      tx_state <= TX_IDLE;

  endcase

  end

end

endmodule
module uarttx(clk, uart_tx, tx_ready, tx_trigger, tx_data, resetn);

input clk;
input tx_trigger;
output uart_tx;
output tx_ready;
input  resetn;
input [7:0] tx_data;



parameter CLK_FREQ = 12_000_000;
parameter BAUDRATE = 9600;
parameter CYCLES4BIT = $rtoi(CLK_FREQ/BAUDRATE);
parameter BIT_COUNTER_WIDTH = $clog2(CYCLES4BIT);
localparam HALF_CYCLES4BIT = $rtoi(CYCLES4BIT / 2);
initial begin
  $display("CYCLES4BIT per bit:\n", CYCLES4BIT);
  $display("Half CYCLES4BIT per bit:\n", HALF_CYCLES4BIT);
  $display("RX state bits:\n", TX_STATE_BITS);
  $display("Width bits cycle counter per bit:\n", BIT_COUNTER_WIDTH);
end

reg [$clog2(TX_STOP) -1:0]tx_state;
localparam TX_IDLE  = 0;
localparam TX_START = 1;
localparam TX_DATA =  2;
localparam TX_STOP  = 3;
localparam TX_STATE_BITS = $clog2(TX_STOP);

reg tx_ready;
reg tx = 1'b1;
reg [BIT_COUNTER_WIDTH - 1: 0] tx_bit_cycle_cnt = 0;
reg [2:0] tx_bit_cnt = 0;

assign uart_tx = tx;

always @(posedge clk) begin

  if (!resetn) begin
    tx_state <= TX_IDLE;
    tx_ready <= 1'b0;
    tx_bit_cycle_cnt <= 0;
    tx_bit_cnt <= 0;
    tx <= 1'b1;
  end else begin

    case (tx_state)

      TX_IDLE: begin
        tx_ready <= 0;
        if (tx_trigger == 1'b1) begin 
          tx_state <= TX_START;
          tx <= 1'b1;
          tx_bit_cycle_cnt <= 0;
        end
      end

      TX_START: begin
        tx_bit_cycle_cnt <= tx_bit_cycle_cnt + 1;
        tx <= 1'b0;

        if (tx_bit_cycle_cnt == (CYCLES4BIT - 1)) begin
          tx_bit_cnt <= 0;
          tx_bit_cycle_cnt <= 0;
          tx_state <= TX_DATA;
        end else 
          tx_state <= TX_START;
      end

    TX_DATA: begin
      tx_bit_cycle_cnt <= tx_bit_cycle_cnt + 1;
      tx <= tx_data[tx_bit_cnt];

      if (tx_bit_cycle_cnt == (CYCLES4BIT -1)) begin
        tx_bit_cycle_cnt <= 0;
        tx_bit_cnt <= tx_bit_cnt + 1;

        if (tx_bit_cnt == 7) begin
          tx_state <= TX_STOP;
        end else 
          tx_state <= TX_DATA;

      end else 
        tx_state <= TX_DATA;
    end

    TX_STOP: begin
      tx <= 1'b1;
      tx_bit_cycle_cnt <= tx_bit_cycle_cnt + 1;
      if (tx_bit_cycle_cnt == (CYCLES4BIT -1)) begin
        tx_ready <= 1;
        tx_state <= TX_IDLE;
      end else
        tx_state <= TX_STOP;
    end

    default:
      tx_state <= TX_IDLE;

  endcase

  end

end

endmodule