data/full_repos/permissive/446623173/tb3.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/446623173/tb3.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/446623173/tb3.v:65: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk = ~ clk;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/446623173/tb3.v:66: Unsupported: Ignoring delay on this delayed statement.\nalways #200 button = ~ button;   \n       ^\n%Error: data/full_repos/permissive/446623173/tb3.v:38: Cannot find file containing module: \'Test\'\n Test uut (\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/446623173,data/full_repos/permissive/446623173/Test\n             data/full_repos/permissive/446623173,data/full_repos/permissive/446623173/Test.v\n             data/full_repos/permissive/446623173,data/full_repos/permissive/446623173/Test.sv\n             Test\n             Test.v\n             Test.sv\n             obj_dir/Test\n             obj_dir/Test.v\n             obj_dir/Test.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb3;


	reg clk;
	reg reset;
	reg button;
	reg [31:0] message1;
	reg [31:0] message2;


	wire aek;


	Test uut (
		.clk(clk), 
		.reset(reset),
		.button(button),
		.message1(message1), 
		.message2(message2), 
		.m_tick(aek)
	);

	initial begin

		clk = 0;
		reset = 1;
		button=1;
		message1=32'b00000001001000110100010101100111;
		message2=32'b10001001101010111100110111101111;


		#100;
        

		reset=0;
		



	end
always #1 clk = ~ clk;
always #200 button = ~ button;   
endmodule
module tb3;



	reg clk;
	reg reset;
	reg button;
	reg [31:0] message1;
	reg [31:0] message2;


	wire aek;


	Test uut (
		.clk(clk), 
		.reset(reset),
		.button(button),
		.message1(message1), 
		.message2(message2), 
		.m_tick(aek)
	);

	initial begin

		clk = 0;
		reset = 1;
		button=1;
		message1=32'b00000001001000110100010101100111;
		message2=32'b10001001101010111100110111101111;


		#100;
        

		reset=0;
		



	end
always #1 clk = ~ clk;
always #200 button = ~ button;   
endmodule