data/full_repos/permissive/458737381/src/verilog-parser/tests/multi_array.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/multi_array.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #1 array[1][200] = 16\'h1234;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/multi_array.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #1 read_bit  = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/multi_array.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #1 array[1][200] = 16\'hAAAA;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/multi_array.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #1 byte_no = 2;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/multi_array.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #1 byte_no = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/multi_array.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #1 $finish;\n  ^\n%Warning-WIDTH: data/full_repos/permissive/458737381/src/verilog-parser/tests/multi_array.v:16: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s COND generates 32 or 16 bits.\n                                                                                              : ... In instance multi_array\nwire [7:0] data_array = (read_multi) ? array[address1][address2] : 0;\n                      ^\n%Error: Exiting due to 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module multi_array();

reg read_v95, read_multi, read_bit;



reg [7:0] address;
reg [7:0] memory [0:255];
wire [7:0] data_out;

assign data_out = (read_v95) ? memory[address] : 0;


reg [7:0] address1, address2;
reg [15:0] array [0:255][0:255];
wire [7:0] data_array = (read_multi) ? array[address1][address2] : 0;


wire [7:0] data_bit = (read_bit) ? array[1][200][12:5] : 8'b0;


reg  [31:0] double_word;
reg  [2:0] byte_no;
wire [7:0] pos_offset = double_word[byte_no*8 +:8];
wire [7:0] neg_offset = double_word[byte_no*8 -:8];

initial begin

  #1 array[1][200] = 16'h1234;
  #1 read_bit  = 1;
  #1 array[1][200] = 16'hAAAA;

  double_word = 32'hDEAD_BEEF;
  #1 byte_no = 2;
  #1 byte_no = 1;
  #1 $finish;
end

always @ (*)
  $display (
   "double_word : %h byte_no : %d pos_offset : %h neg_offset : %h", 
   double_word, byte_no, pos_offset, neg_offset);

always @ (*)
  $display ("array[1][200] : %h read_bit : %b data_bit : %h", 
   array[1][200],read_bit, data_bit);

endmodule
module multi_array();


reg read_v95, read_multi, read_bit;



reg [7:0] address;
reg [7:0] memory [0:255];
wire [7:0] data_out;

assign data_out = (read_v95) ? memory[address] : 0;


reg [7:0] address1, address2;
reg [15:0] array [0:255][0:255];
wire [7:0] data_array = (read_multi) ? array[address1][address2] : 0;


wire [7:0] data_bit = (read_bit) ? array[1][200][12:5] : 8'b0;


reg  [31:0] double_word;
reg  [2:0] byte_no;
wire [7:0] pos_offset = double_word[byte_no*8 +:8];
wire [7:0] neg_offset = double_word[byte_no*8 -:8];

initial begin

  #1 array[1][200] = 16'h1234;
  #1 read_bit  = 1;
  #1 array[1][200] = 16'hAAAA;

  double_word = 32'hDEAD_BEEF;
  #1 byte_no = 2;
  #1 byte_no = 1;
  #1 $finish;
end

always @ (*)
  $display (
   "double_word : %h byte_no : %d pos_offset : %h neg_offset : %h", 
   double_word, byte_no, pos_offset, neg_offset);

always @ (*)
  $display ("array[1][200] : %h read_bit : %b data_bit : %h", 
   array[1][200],read_bit, data_bit);

endmodule