data/full_repos/permissive/414867793/Logic_Circuits/Half_Adder/ADD.v
data/verilator_xmls/2b89d8a3-a5ed-499f-adfc-89e3c4c25471.xml
module ADD(A,B,S,C);
input A,B;
output S,C;
assign S=(A^B);
assign C=(A&B);
endmodule
module ADD(A,B,S,C);

input A,B;
output S,C;
assign S=(A^B);
assign C=(A&B);
endmodule