data/full_repos/permissive/499494419/je.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/499494419/je.v:78: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/499494419/je.v:82: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/je.v:84: Unsupported: Ignoring delay on this delayed statement.\n  #180;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/je.v:89: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/je.v:91: Unsupported: Ignoring delay on this delayed statement.\n  #180;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/je.v:93: Unsupported: Ignoring delay on this delayed statement.\n  #190;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/je.v:95: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/je.v:99: Unsupported: Ignoring delay on this delayed statement.\n  #180;data=1;data2=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/je.v:100: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/je.v:102: Unsupported: Ignoring delay on this delayed statement.\n  #180;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/je.v:106: Unsupported: Ignoring delay on this delayed statement.\n  #190;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/je.v:108: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/je.v:110: Unsupported: Ignoring delay on this delayed statement.\n  #180;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/je.v:117: Unsupported: Ignoring delay on this delayed statement.\n   always #5 clk=~clk;\n          ^\n%Error: data/full_repos/permissive/499494419/je.v:50: Cannot find file containing module: \'main\'\n main uut (\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/499494419,data/full_repos/permissive/499494419/main\n             data/full_repos/permissive/499494419,data/full_repos/permissive/499494419/main.v\n             data/full_repos/permissive/499494419,data/full_repos/permissive/499494419/main.sv\n             main\n             main.v\n             main.sv\n             obj_dir/main\n             obj_dir/main.v\n             obj_dir/main.sv\n%Error: Exiting due to 1 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module je;


	reg clk;
	reg rst;
	reg data;
	reg data2;


	wire datadelay0;
	wire datadelay2;
	wire datadelay8;
	wire datadelay19;
	wire datadelay18;
	wire datadelay14;
	wire delay0;
	wire delay1;
	wire hebo;
	wire delay5;
	wire gie;
	wire gie2;
	wire b3;
	wire [4:0] cnt;


	main uut (
		.clk(clk), 
		.rst(rst), 
		.data(data), 
		.datadelay0(datadelay0), 
		.datadelay2(datadelay2), 
		.datadelay8(datadelay8), 
		.datadelay19(datadelay19), 
		.datadelay18(datadelay18), 
		.datadelay14(datadelay14), 
		.data2(data2), 
		.delay0(delay0), 
		.delay1(delay1), 
		.hebo(hebo), 
		.delay5(delay5), 
		.gie(gie), 
		.gie2(gie2),
		.b3(b3),
		.cnt(cnt)
	);

initial begin

		clk = 1;
		rst = 0;
		data = 0;
		data2=0;

		#100;
		rst=1;
		
		data=1;data2=1;
		#10;
		data=0;data2=0;
		#180;
		
      
		data=1;data2=1;
		
		#10;
		data=0;data2=0;
		#180;
		data=0;data2=0;
		#190;
		data=1;data2=1;
		#10;
		
      
		data=0;data2=0;
		#180;data=1;data2=1;
		#10;
		data=0;data2=0;
		#180;
		
      
		data=0;data2=0;
		#190;
		data=1;data2=1;
		#10;
		data=0;data2=0;
		#180;
	
      
		 


	end
   always #5 clk=~clk;
      
endmodule
module je;



	reg clk;
	reg rst;
	reg data;
	reg data2;


	wire datadelay0;
	wire datadelay2;
	wire datadelay8;
	wire datadelay19;
	wire datadelay18;
	wire datadelay14;
	wire delay0;
	wire delay1;
	wire hebo;
	wire delay5;
	wire gie;
	wire gie2;
	wire b3;
	wire [4:0] cnt;


	main uut (
		.clk(clk), 
		.rst(rst), 
		.data(data), 
		.datadelay0(datadelay0), 
		.datadelay2(datadelay2), 
		.datadelay8(datadelay8), 
		.datadelay19(datadelay19), 
		.datadelay18(datadelay18), 
		.datadelay14(datadelay14), 
		.data2(data2), 
		.delay0(delay0), 
		.delay1(delay1), 
		.hebo(hebo), 
		.delay5(delay5), 
		.gie(gie), 
		.gie2(gie2),
		.b3(b3),
		.cnt(cnt)
	);

initial begin

		clk = 1;
		rst = 0;
		data = 0;
		data2=0;

		#100;
		rst=1;
		
		data=1;data2=1;
		#10;
		data=0;data2=0;
		#180;
		
      
		data=1;data2=1;
		
		#10;
		data=0;data2=0;
		#180;
		data=0;data2=0;
		#190;
		data=1;data2=1;
		#10;
		
      
		data=0;data2=0;
		#180;data=1;data2=1;
		#10;
		data=0;data2=0;
		#180;
		
      
		data=0;data2=0;
		#190;
		data=1;data2=1;
		#10;
		data=0;data2=0;
		#180;
	
      
		 


	end
   always #5 clk=~clk;
      
endmodule