data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/tc141_fflops.v
data/verilator_xmls/9ba128f8-fb7e-4069-a297-c6176d89a7ff.xml
module tc141_fflops
    (
     clk    ,
     rst_   ,
     din    ,
     dout   
     
     );



parameter           DAT = 8;



input               clk ;
input               rst_;
input [DAT-1:0]     din ;
output [DAT-1:0]    dout;






(* ASYNC_REG = "TRUE" *)reg [DAT-1:0]       din_p1 = {DAT{1'b0}};
(* ASYNC_REG = "TRUE" *)reg [DAT-1:0]       din_p2 = {DAT{1'b0}};
wire [DAT-1:0]      dout;
assign              dout = din_p2;

always @(posedge clk)
    begin
    din_p1 <= din ;
    din_p2 <= din_p1;
    end

endmodule
module tc141_fflops
    (
     clk    ,
     rst_   ,
     din    ,
     dout   
     
     );




parameter           DAT = 8;



input               clk ;
input               rst_;
input [DAT-1:0]     din ;
output [DAT-1:0]    dout;






(* ASYNC_REG = "TRUE" *)reg [DAT-1:0]       din_p1 = {DAT{1'b0}};
(* ASYNC_REG = "TRUE" *)reg [DAT-1:0]       din_p2 = {DAT{1'b0}};
wire [DAT-1:0]      dout;
assign              dout = din_p2;

always @(posedge clk)
    begin
    din_p1 <= din ;
    din_p2 <= din_p1;
    end

endmodule