data/full_repos/permissive/433624543/full_adder.v
data/verilator_xmls/0d4faf9d-9cf3-42a0-83ea-e3e8f1513433.xml
module full_adder 
  (
   a,
   b,
   carry_in,
   sum,
   carry_out
   );
 
  input  a;
  input  b;
  input  carry_in;
  output sum;
  output carry_out;
 
  wire   w_WIRE_1;
  wire   w_WIRE_2;
  wire   w_WIRE_3;
       
  assign w_WIRE_1 = a ^ b;
  assign w_WIRE_2 = w_WIRE_1 & carry_in;
  assign w_WIRE_3 = a & b;
 
  assign sum   = w_WIRE_1 ^ carry_in;
  assign carry_out = w_WIRE_2 | w_WIRE_3;

   
endmodule
module full_adder 
  (
   a,
   b,
   carry_in,
   sum,
   carry_out
   );

 
  input  a;
  input  b;
  input  carry_in;
  output sum;
  output carry_out;
 
  wire   w_WIRE_1;
  wire   w_WIRE_2;
  wire   w_WIRE_3;
       
  assign w_WIRE_1 = a ^ b;
  assign w_WIRE_2 = w_WIRE_1 & carry_in;
  assign w_WIRE_3 = a & b;
 
  assign sum   = w_WIRE_1 ^ carry_in;
  assign carry_out = w_WIRE_2 | w_WIRE_3;

   
endmodule