data/full_repos/permissive/42149584/Lab4-Part1-40x7bit-RAM/OverallController.v
1: b'%Warning-WIDTH: data/full_repos/permissive/42149584/Lab4-Part1-40x7bit-RAM/OverallController.v:16: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'InitialState\' generates 2 bits.\n                                                                                                 : ... In instance OverallController\n initial State = InitialState;\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/42149584/Lab4-Part1-40x7bit-RAM/OverallController.v:17: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'InitialState\' generates 2 bits.\n                                                                                                 : ... In instance OverallController\n initial NextState = InitialState;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/42149584/Lab4-Part1-40x7bit-RAM/OverallController.v:20: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'InitialState\' generates 2 bits.\n                                                                                                 : ... In instance OverallController\n  case (State)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/42149584/Lab4-Part1-40x7bit-RAM/OverallController.v:20: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'LoadState\' generates 2 bits.\n                                                                                                 : ... In instance OverallController\n  case (State)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/42149584/Lab4-Part1-40x7bit-RAM/OverallController.v:20: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'ReadState\' generates 2 bits.\n                                                                                                 : ... In instance OverallController\n  case (State)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/42149584/Lab4-Part1-40x7bit-RAM/OverallController.v:20: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'IncrementState\' generates 2 bits.\n                                                                                                 : ... In instance OverallController\n  case (State)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/42149584/Lab4-Part1-40x7bit-RAM/OverallController.v:28: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'InitialState\' generates 2 bits.\n                                                                                                 : ... In instance OverallController\n  if (Reset == 1) State <= InitialState;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/42149584/Lab4-Part1-40x7bit-RAM/OverallController.v:32: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'IncrementState\' generates 2 bits.\n                                                                                                 : ... In instance OverallController\n  if (IncrementData == 1) NextState <= IncrementState;\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/42149584/Lab4-Part1-40x7bit-RAM/OverallController.v:33: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'LoadState\' generates 2 bits.\n                                                                                                 : ... In instance OverallController\n  else if (LoadData == 1) NextState <= LoadState;\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/42149584/Lab4-Part1-40x7bit-RAM/OverallController.v:34: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'ReadState\' generates 2 bits.\n                                                                                                 : ... In instance OverallController\n  else NextState <= ReadState;\n                 ^~\n%Error: Exiting due to 10 warning(s)\n'
module OverallController(Clock, IncrementData, LoadData, Reset, AddOne, WriteOrRead);
	input Clock, IncrementData, LoadData, Reset;
	output reg AddOne, WriteOrRead;
	parameter InitialState = 2'b00;
	parameter LoadState = 2'b01;
	parameter ReadState = 2'b10;
	parameter IncrementState = 2'b11;
	reg [2:0] State;
	reg [2:0] NextState;
	initial State = InitialState;
	initial NextState = InitialState;
	
	always @ (State)
		case (State)
		InitialState: 		begin AddOne <= 0; WriteOrRead <= 0; end
		LoadState: 			begin AddOne <= 0; WriteOrRead <= 1; end
		ReadState: 			begin AddOne <= 0; WriteOrRead <= 0; end
		IncrementState:	begin AddOne <= 1; WriteOrRead <= 1; end
		endcase
		
	always @ (posedge Clock or posedge Reset)
		if (Reset == 1) State <= InitialState;
		else State <= NextState;
	
	always @ (State or IncrementData or LoadData)
		if (IncrementData == 1) NextState <= IncrementState;
		else if (LoadData == 1) NextState <= LoadState;
		else NextState <= ReadState;
endmodule
module OverallController(Clock, IncrementData, LoadData, Reset, AddOne, WriteOrRead);

	input Clock, IncrementData, LoadData, Reset;
	output reg AddOne, WriteOrRead;
	parameter InitialState = 2'b00;
	parameter LoadState = 2'b01;
	parameter ReadState = 2'b10;
	parameter IncrementState = 2'b11;
	reg [2:0] State;
	reg [2:0] NextState;
	initial State = InitialState;
	initial NextState = InitialState;
	
	always @ (State)
		case (State)
		InitialState: 		begin AddOne <= 0; WriteOrRead <= 0; end
		LoadState: 			begin AddOne <= 0; WriteOrRead <= 1; end
		ReadState: 			begin AddOne <= 0; WriteOrRead <= 0; end
		IncrementState:	begin AddOne <= 1; WriteOrRead <= 1; end
		endcase
		
	always @ (posedge Clock or posedge Reset)
		if (Reset == 1) State <= InitialState;
		else State <= NextState;
	
	always @ (State or IncrementData or LoadData)
		if (IncrementData == 1) NextState <= IncrementState;
		else if (LoadData == 1) NextState <= LoadState;
		else NextState <= ReadState;
endmodule