data/full_repos/permissive/447976230/fpga/usrp1/models/bustri.v
data/verilator_xmls/1d4656b1-867f-46f6-84d7-4b1d77a57ac3.xml
module bustri (data,
	       enabledt,
	       tridata);
   
   input [15:0]  data;
   input 	 enabledt;
   inout [15:0]  tridata;
   
   assign 	 tridata = enabledt ? data :16'bz;
   
endmodule
module bustri (data,
	       enabledt,
	       tridata);

   
   input [15:0]  data;
   input 	 enabledt;
   inout [15:0]  tridata;
   
   assign 	 tridata = enabledt ? data :16'bz;
   
endmodule