data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/idu/rtl/ct_idu_rf_prf_gated_preg.v
1: b"%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/idu/rtl/ct_idu_rf_prf_gated_preg.v:65: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_preg_gated_clk (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/idu/rtl,data/full_repos/permissive/418752214/gated_clk_cell\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/idu/rtl,data/full_repos/permissive/418752214/gated_clk_cell.v\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/idu/rtl,data/full_repos/permissive/418752214/gated_clk_cell.sv\n             gated_clk_cell\n             gated_clk_cell.v\n             gated_clk_cell.sv\n             obj_dir/gated_clk_cell\n             obj_dir/gated_clk_cell.v\n             obj_dir/gated_clk_cell.sv\n%Error: Exiting due to 1 error(s)\n"
module ct_idu_rf_prf_gated_preg(
  cp0_idu_icg_en,
  cp0_yy_clk_en,
  forever_cpuclk,
  iu_idu_ex2_pipe0_wb_preg_data,
  iu_idu_ex2_pipe1_wb_preg_data,
  lsu_idu_wb_pipe3_wb_preg_data,
  pad_yy_icg_scan_en,
  x_reg_dout,
  x_wb_vld
);


input           cp0_idu_icg_en;               
input           cp0_yy_clk_en;                
input           forever_cpuclk;               
input   [63:0]  iu_idu_ex2_pipe0_wb_preg_data; 
input   [63:0]  iu_idu_ex2_pipe1_wb_preg_data; 
input   [63:0]  lsu_idu_wb_pipe3_wb_preg_data; 
input           pad_yy_icg_scan_en;           
input   [2 :0]  x_wb_vld;                     
output  [63:0]  x_reg_dout;                   


reg     [63:0]  reg_dout;                     
reg     [63:0]  write_data;                   


wire            cp0_idu_icg_en;               
wire            cp0_yy_clk_en;                
wire            forever_cpuclk;               
wire    [63:0]  iu_idu_ex2_pipe0_wb_preg_data; 
wire    [63:0]  iu_idu_ex2_pipe1_wb_preg_data; 
wire    [63:0]  lsu_idu_wb_pipe3_wb_preg_data; 
wire            pad_yy_icg_scan_en;           
wire            preg_clk;                     
wire            preg_clk_en;                  
wire            write_en;                     
wire    [63:0]  x_reg_dout;                   
wire    [2 :0]  x_wb_vld;                     






assign preg_clk_en = write_en;

gated_clk_cell  x_preg_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (preg_clk          ),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (preg_clk_en       ),
  .module_en          (cp0_idu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);











assign write_en = |x_wb_vld[2:0];

always @( iu_idu_ex2_pipe0_wb_preg_data[63:0]
       or x_wb_vld[2:0]
       or lsu_idu_wb_pipe3_wb_preg_data[63:0]
       or iu_idu_ex2_pipe1_wb_preg_data[63:0])
begin
  case (x_wb_vld[2:0])
    3'b001 : write_data[63:0] = iu_idu_ex2_pipe0_wb_preg_data[63:0];
    3'b010 : write_data[63:0] = iu_idu_ex2_pipe1_wb_preg_data[63:0];
    3'b100 : write_data[63:0] = lsu_idu_wb_pipe3_wb_preg_data[63:0];
    default: write_data[63:0] = {64{1'bx}};
  endcase

end




always @(posedge preg_clk)
begin
  if(write_en)
    reg_dout[63:0] <= write_data[63:0];
  else
    reg_dout[63:0] <= reg_dout[63:0];
end
assign x_reg_dout[63:0] = reg_dout[63:0];


endmodule
module ct_idu_rf_prf_gated_preg(
  cp0_idu_icg_en,
  cp0_yy_clk_en,
  forever_cpuclk,
  iu_idu_ex2_pipe0_wb_preg_data,
  iu_idu_ex2_pipe1_wb_preg_data,
  lsu_idu_wb_pipe3_wb_preg_data,
  pad_yy_icg_scan_en,
  x_reg_dout,
  x_wb_vld
);



input           cp0_idu_icg_en;               
input           cp0_yy_clk_en;                
input           forever_cpuclk;               
input   [63:0]  iu_idu_ex2_pipe0_wb_preg_data; 
input   [63:0]  iu_idu_ex2_pipe1_wb_preg_data; 
input   [63:0]  lsu_idu_wb_pipe3_wb_preg_data; 
input           pad_yy_icg_scan_en;           
input   [2 :0]  x_wb_vld;                     
output  [63:0]  x_reg_dout;                   


reg     [63:0]  reg_dout;                     
reg     [63:0]  write_data;                   


wire            cp0_idu_icg_en;               
wire            cp0_yy_clk_en;                
wire            forever_cpuclk;               
wire    [63:0]  iu_idu_ex2_pipe0_wb_preg_data; 
wire    [63:0]  iu_idu_ex2_pipe1_wb_preg_data; 
wire    [63:0]  lsu_idu_wb_pipe3_wb_preg_data; 
wire            pad_yy_icg_scan_en;           
wire            preg_clk;                     
wire            preg_clk_en;                  
wire            write_en;                     
wire    [63:0]  x_reg_dout;                   
wire    [2 :0]  x_wb_vld;                     






assign preg_clk_en = write_en;

gated_clk_cell  x_preg_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (preg_clk          ),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (preg_clk_en       ),
  .module_en          (cp0_idu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);











assign write_en = |x_wb_vld[2:0];

always @( iu_idu_ex2_pipe0_wb_preg_data[63:0]
       or x_wb_vld[2:0]
       or lsu_idu_wb_pipe3_wb_preg_data[63:0]
       or iu_idu_ex2_pipe1_wb_preg_data[63:0])
begin
  case (x_wb_vld[2:0])
    3'b001 : write_data[63:0] = iu_idu_ex2_pipe0_wb_preg_data[63:0];
    3'b010 : write_data[63:0] = iu_idu_ex2_pipe1_wb_preg_data[63:0];
    3'b100 : write_data[63:0] = lsu_idu_wb_pipe3_wb_preg_data[63:0];
    default: write_data[63:0] = {64{1'bx}};
  endcase

end




always @(posedge preg_clk)
begin
  if(write_en)
    reg_dout[63:0] <= write_data[63:0];
  else
    reg_dout[63:0] <= reg_dout[63:0];
end
assign x_reg_dout[63:0] = reg_dout[63:0];


endmodule