data/full_repos/permissive/415843050/cpu-src/datamem.v
1: b"%Error: data/full_repos/permissive/415843050/cpu-src/datamem.v:33: Cannot find file containing module: 'ram'\n    ram ram(\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/415843050/cpu-src,data/full_repos/permissive/415843050/ram\n             data/full_repos/permissive/415843050/cpu-src,data/full_repos/permissive/415843050/ram.v\n             data/full_repos/permissive/415843050/cpu-src,data/full_repos/permissive/415843050/ram.sv\n             ram\n             ram.v\n             ram.sv\n             obj_dir/ram\n             obj_dir/ram.v\n             obj_dir/ram.sv\n%Error: Exiting due to 1 error(s)\n"
module DataMEM(
    clock,
    Memory_write,Address,Read_data,Write_data,
    Upg_rst_i,Upg_clk_i,Upg_wen_i,Upg_adr_i,Upg_dat_i,Upg_done_i
    );
    
    input       clock;
    input       Memory_write;
    input[31:0] Address;
    input[31:0] Write_data;
    output[31:0]    Read_data;
    

    input       Upg_rst_i;
    input       Upg_clk_i;
    input       Upg_wen_i;
    input[13:0] Upg_adr_i;
    input[31:0] Upg_dat_i;
    input       Upg_done_i;
    
    wire clk;
    assign clk = clock;
    
    wire kickoff = Upg_rst_i | ((~Upg_rst_i) & Upg_done_i);
    

    ram ram(
        .clka(kickoff ? clk : Upg_clk_i),
        .wea(kickoff ? Memory_write : Upg_wen_i),
        .addra(kickoff ? Address[15:2] : Upg_adr_i),
        .dina(kickoff ? Write_data : Upg_dat_i),
        .douta(Read_data)
    );
    
endmodule
module DataMEM(
    clock,
    Memory_write,Address,Read_data,Write_data,
    Upg_rst_i,Upg_clk_i,Upg_wen_i,Upg_adr_i,Upg_dat_i,Upg_done_i
    );

    
    input       clock;
    input       Memory_write;
    input[31:0] Address;
    input[31:0] Write_data;
    output[31:0]    Read_data;
    

    input       Upg_rst_i;
    input       Upg_clk_i;
    input       Upg_wen_i;
    input[13:0] Upg_adr_i;
    input[31:0] Upg_dat_i;
    input       Upg_done_i;
    
    wire clk;
    assign clk = clock;
    
    wire kickoff = Upg_rst_i | ((~Upg_rst_i) & Upg_done_i);
    

    ram ram(
        .clka(kickoff ? clk : Upg_clk_i),
        .wea(kickoff ? Memory_write : Upg_wen_i),
        .addra(kickoff ? Address[15:2] : Upg_adr_i),
        .dina(kickoff ? Write_data : Upg_dat_i),
        .douta(Read_data)
    );
    
endmodule