data/full_repos/permissive/458737381/src/verilog-parser/tests/iob_jbi_rptr_1.v
data/verilator_xmls/5efd22c5-4a20-4a6f-9e6d-7edde2ef2a23.xml
module iob_jbi_rptr_1 (

   sig_buf, 

   sig
   );


output	[135:0]	 sig_buf;
input	[135:0]	 sig;


assign	sig_buf = sig;



endmodule
module iob_jbi_rptr_1 (

   sig_buf, 

   sig
   );



output	[135:0]	 sig_buf;
input	[135:0]	 sig;


assign	sig_buf = sig;



endmodule