data/full_repos/permissive/48250786/mixcolumnsde.v
data/verilator_xmls/42610220-9ab3-4ec1-be50-a0e6a13c26f4.xml
module mixcolumnsde(
	 output reg [15:0] dout,
	 input [7:0] add,
	 input clock,
	 input en
    );
	 
	 reg [15:0] rom [0:255];
	 
	 initial begin
		$readmemh("mixcols_d_e.table", rom, 0, 255);
	 end
	 
	 always @(posedge clock) begin
		if(en) begin
			dout <= rom[add];
		end
	 end

endmodule
module mixcolumnsde(
	 output reg [15:0] dout,
	 input [7:0] add,
	 input clock,
	 input en
    );

	 
	 reg [15:0] rom [0:255];
	 
	 initial begin
		$readmemh("mixcols_d_e.table", rom, 0, 255);
	 end
	 
	 always @(posedge clock) begin
		if(en) begin
			dout <= rom[add];
		end
	 end

endmodule