data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_loop_unrolling/cachelib/v_rtl/dut_Add_12Sx9S_12S_1.v
data/verilator_xmls/7afc5a6d-39f0-48ac-b19a-bf130bbe26f1.xml
module dut_Add_12Sx9S_12S_1 (
	in2,
	in1,
	out1
	);
input [11:0] in2;
input [8:0] in1;
output [11:0] out1;
wire [11:0] asc001;

assign asc001 = 
	+(in2)
	+({{3{in1[8]}}, in1});

assign out1 = asc001;
endmodule
module dut_Add_12Sx9S_12S_1 (
	in2,
	in1,
	out1
	);

input [11:0] in2;
input [8:0] in1;
output [11:0] out1;
wire [11:0] asc001;

assign asc001 = 
	+(in2)
	+({{3{in1[8]}}, in1});

assign out1 = asc001;
endmodule