data/full_repos/permissive/440264724/hdl/peri/platform_timer/timer_regs.v
data/verilator_xmls/0ca51d20-f34f-492c-b3b9-b47092d90107.xml
module timer_regs (
	input wire clk,
	input wire rst_n,
	

	input wire apbs_psel,
	input wire apbs_penable,
	input wire apbs_pwrite,
	input wire [15:0] apbs_paddr,
	input wire [31:0] apbs_pwdata,
	output wire [31:0] apbs_prdata,
	output wire apbs_pready,
	output wire apbs_pslverr,
	

	input wire [31:0] time_i,
	output reg [31:0] time_o,
	output reg time_wen,
	output reg time_ren,
	input wire [31:0] timeh_i,
	output reg [31:0] timeh_o,
	output reg timeh_wen,
	output reg timeh_ren,
	output reg [31:0] timecmp0_o,
	output reg [31:0] timecmp0h_o,
	output reg [31:0] timecmp1_o,
	output reg [31:0] timecmp1h_o,
	input wire [1:0] softirq_set_i,
	output reg [1:0] softirq_set_o,
	output reg softirq_set_wen,
	output reg softirq_set_ren,
	input wire [1:0] softirq_clr_i,
	output reg [1:0] softirq_clr_o,
	output reg softirq_clr_wen,
	output reg softirq_clr_ren
);


wire [31:0] wdata = apbs_pwdata;
reg [31:0] rdata;
wire wen = apbs_psel && apbs_penable && apbs_pwrite;
wire ren = apbs_psel && apbs_penable && !apbs_pwrite;
wire [15:0] addr = apbs_paddr & 16'h1c;
assign apbs_prdata = rdata;
assign apbs_pready = 1'b1;
assign apbs_pslverr = 1'b0;

localparam ADDR_TIME = 0;
localparam ADDR_TIMEH = 4;
localparam ADDR_TIMECMP0 = 8;
localparam ADDR_TIMECMP0H = 12;
localparam ADDR_TIMECMP1 = 16;
localparam ADDR_TIMECMP1H = 20;
localparam ADDR_SOFTIRQ_SET = 24;
localparam ADDR_SOFTIRQ_CLR = 28;

wire __time_wen = wen && addr == ADDR_TIME;
wire __time_ren = ren && addr == ADDR_TIME;
wire __timeh_wen = wen && addr == ADDR_TIMEH;
wire __timeh_ren = ren && addr == ADDR_TIMEH;
wire __timecmp0_wen = wen && addr == ADDR_TIMECMP0;
wire __timecmp0_ren = ren && addr == ADDR_TIMECMP0;
wire __timecmp0h_wen = wen && addr == ADDR_TIMECMP0H;
wire __timecmp0h_ren = ren && addr == ADDR_TIMECMP0H;
wire __timecmp1_wen = wen && addr == ADDR_TIMECMP1;
wire __timecmp1_ren = ren && addr == ADDR_TIMECMP1;
wire __timecmp1h_wen = wen && addr == ADDR_TIMECMP1H;
wire __timecmp1h_ren = ren && addr == ADDR_TIMECMP1H;
wire __softirq_set_wen = wen && addr == ADDR_SOFTIRQ_SET;
wire __softirq_set_ren = ren && addr == ADDR_SOFTIRQ_SET;
wire __softirq_clr_wen = wen && addr == ADDR_SOFTIRQ_CLR;
wire __softirq_clr_ren = ren && addr == ADDR_SOFTIRQ_CLR;

wire [31:0] time_wdata = wdata[31:0];
wire [31:0] time_rdata;
wire [31:0] __time_rdata = {time_rdata};
assign time_rdata = time_i;

wire [31:0] timeh_wdata = wdata[31:0];
wire [31:0] timeh_rdata;
wire [31:0] __timeh_rdata = {timeh_rdata};
assign timeh_rdata = timeh_i;

wire [31:0] timecmp0_wdata = wdata[31:0];
wire [31:0] timecmp0_rdata;
wire [31:0] __timecmp0_rdata = {timecmp0_rdata};
assign timecmp0_rdata = timecmp0_o;

wire [31:0] timecmp0h_wdata = wdata[31:0];
wire [31:0] timecmp0h_rdata;
wire [31:0] __timecmp0h_rdata = {timecmp0h_rdata};
assign timecmp0h_rdata = timecmp0h_o;

wire [31:0] timecmp1_wdata = wdata[31:0];
wire [31:0] timecmp1_rdata;
wire [31:0] __timecmp1_rdata = {timecmp1_rdata};
assign timecmp1_rdata = timecmp1_o;

wire [31:0] timecmp1h_wdata = wdata[31:0];
wire [31:0] timecmp1h_rdata;
wire [31:0] __timecmp1h_rdata = {timecmp1h_rdata};
assign timecmp1h_rdata = timecmp1h_o;

wire [1:0] softirq_set_wdata = wdata[1:0];
wire [1:0] softirq_set_rdata;
wire [31:0] __softirq_set_rdata = {30'h0, softirq_set_rdata};
assign softirq_set_rdata = softirq_set_i;

wire [1:0] softirq_clr_wdata = wdata[1:0];
wire [1:0] softirq_clr_rdata;
wire [31:0] __softirq_clr_rdata = {30'h0, softirq_clr_rdata};
assign softirq_clr_rdata = softirq_clr_i;

always @ (*) begin
	case (addr)
		ADDR_TIME: rdata = __time_rdata;
		ADDR_TIMEH: rdata = __timeh_rdata;
		ADDR_TIMECMP0: rdata = __timecmp0_rdata;
		ADDR_TIMECMP0H: rdata = __timecmp0h_rdata;
		ADDR_TIMECMP1: rdata = __timecmp1_rdata;
		ADDR_TIMECMP1H: rdata = __timecmp1h_rdata;
		ADDR_SOFTIRQ_SET: rdata = __softirq_set_rdata;
		ADDR_SOFTIRQ_CLR: rdata = __softirq_clr_rdata;
		default: rdata = 32'h0;
	endcase
	time_wen = __time_wen;
	time_o = time_wdata;
	time_ren = __time_ren;
	timeh_wen = __timeh_wen;
	timeh_o = timeh_wdata;
	timeh_ren = __timeh_ren;
	softirq_set_wen = __softirq_set_wen;
	softirq_set_o = softirq_set_wdata;
	softirq_set_ren = __softirq_set_ren;
	softirq_clr_wen = __softirq_clr_wen;
	softirq_clr_o = softirq_clr_wdata;
	softirq_clr_ren = __softirq_clr_ren;
end

always @ (posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		timecmp0_o <= 32'h0;
		timecmp0h_o <= 32'h0;
		timecmp1_o <= 32'h0;
		timecmp1h_o <= 32'h0;
	end else begin
		if (__timecmp0_wen)
			timecmp0_o <= timecmp0_wdata;
		if (__timecmp0h_wen)
			timecmp0h_o <= timecmp0h_wdata;
		if (__timecmp1_wen)
			timecmp1_o <= timecmp1_wdata;
		if (__timecmp1h_wen)
			timecmp1h_o <= timecmp1h_wdata;
	end
end

endmodule
module timer_regs (
	input wire clk,
	input wire rst_n,
	

	input wire apbs_psel,
	input wire apbs_penable,
	input wire apbs_pwrite,
	input wire [15:0] apbs_paddr,
	input wire [31:0] apbs_pwdata,
	output wire [31:0] apbs_prdata,
	output wire apbs_pready,
	output wire apbs_pslverr,
	

	input wire [31:0] time_i,
	output reg [31:0] time_o,
	output reg time_wen,
	output reg time_ren,
	input wire [31:0] timeh_i,
	output reg [31:0] timeh_o,
	output reg timeh_wen,
	output reg timeh_ren,
	output reg [31:0] timecmp0_o,
	output reg [31:0] timecmp0h_o,
	output reg [31:0] timecmp1_o,
	output reg [31:0] timecmp1h_o,
	input wire [1:0] softirq_set_i,
	output reg [1:0] softirq_set_o,
	output reg softirq_set_wen,
	output reg softirq_set_ren,
	input wire [1:0] softirq_clr_i,
	output reg [1:0] softirq_clr_o,
	output reg softirq_clr_wen,
	output reg softirq_clr_ren
);



wire [31:0] wdata = apbs_pwdata;
reg [31:0] rdata;
wire wen = apbs_psel && apbs_penable && apbs_pwrite;
wire ren = apbs_psel && apbs_penable && !apbs_pwrite;
wire [15:0] addr = apbs_paddr & 16'h1c;
assign apbs_prdata = rdata;
assign apbs_pready = 1'b1;
assign apbs_pslverr = 1'b0;

localparam ADDR_TIME = 0;
localparam ADDR_TIMEH = 4;
localparam ADDR_TIMECMP0 = 8;
localparam ADDR_TIMECMP0H = 12;
localparam ADDR_TIMECMP1 = 16;
localparam ADDR_TIMECMP1H = 20;
localparam ADDR_SOFTIRQ_SET = 24;
localparam ADDR_SOFTIRQ_CLR = 28;

wire __time_wen = wen && addr == ADDR_TIME;
wire __time_ren = ren && addr == ADDR_TIME;
wire __timeh_wen = wen && addr == ADDR_TIMEH;
wire __timeh_ren = ren && addr == ADDR_TIMEH;
wire __timecmp0_wen = wen && addr == ADDR_TIMECMP0;
wire __timecmp0_ren = ren && addr == ADDR_TIMECMP0;
wire __timecmp0h_wen = wen && addr == ADDR_TIMECMP0H;
wire __timecmp0h_ren = ren && addr == ADDR_TIMECMP0H;
wire __timecmp1_wen = wen && addr == ADDR_TIMECMP1;
wire __timecmp1_ren = ren && addr == ADDR_TIMECMP1;
wire __timecmp1h_wen = wen && addr == ADDR_TIMECMP1H;
wire __timecmp1h_ren = ren && addr == ADDR_TIMECMP1H;
wire __softirq_set_wen = wen && addr == ADDR_SOFTIRQ_SET;
wire __softirq_set_ren = ren && addr == ADDR_SOFTIRQ_SET;
wire __softirq_clr_wen = wen && addr == ADDR_SOFTIRQ_CLR;
wire __softirq_clr_ren = ren && addr == ADDR_SOFTIRQ_CLR;

wire [31:0] time_wdata = wdata[31:0];
wire [31:0] time_rdata;
wire [31:0] __time_rdata = {time_rdata};
assign time_rdata = time_i;

wire [31:0] timeh_wdata = wdata[31:0];
wire [31:0] timeh_rdata;
wire [31:0] __timeh_rdata = {timeh_rdata};
assign timeh_rdata = timeh_i;

wire [31:0] timecmp0_wdata = wdata[31:0];
wire [31:0] timecmp0_rdata;
wire [31:0] __timecmp0_rdata = {timecmp0_rdata};
assign timecmp0_rdata = timecmp0_o;

wire [31:0] timecmp0h_wdata = wdata[31:0];
wire [31:0] timecmp0h_rdata;
wire [31:0] __timecmp0h_rdata = {timecmp0h_rdata};
assign timecmp0h_rdata = timecmp0h_o;

wire [31:0] timecmp1_wdata = wdata[31:0];
wire [31:0] timecmp1_rdata;
wire [31:0] __timecmp1_rdata = {timecmp1_rdata};
assign timecmp1_rdata = timecmp1_o;

wire [31:0] timecmp1h_wdata = wdata[31:0];
wire [31:0] timecmp1h_rdata;
wire [31:0] __timecmp1h_rdata = {timecmp1h_rdata};
assign timecmp1h_rdata = timecmp1h_o;

wire [1:0] softirq_set_wdata = wdata[1:0];
wire [1:0] softirq_set_rdata;
wire [31:0] __softirq_set_rdata = {30'h0, softirq_set_rdata};
assign softirq_set_rdata = softirq_set_i;

wire [1:0] softirq_clr_wdata = wdata[1:0];
wire [1:0] softirq_clr_rdata;
wire [31:0] __softirq_clr_rdata = {30'h0, softirq_clr_rdata};
assign softirq_clr_rdata = softirq_clr_i;

always @ (*) begin
	case (addr)
		ADDR_TIME: rdata = __time_rdata;
		ADDR_TIMEH: rdata = __timeh_rdata;
		ADDR_TIMECMP0: rdata = __timecmp0_rdata;
		ADDR_TIMECMP0H: rdata = __timecmp0h_rdata;
		ADDR_TIMECMP1: rdata = __timecmp1_rdata;
		ADDR_TIMECMP1H: rdata = __timecmp1h_rdata;
		ADDR_SOFTIRQ_SET: rdata = __softirq_set_rdata;
		ADDR_SOFTIRQ_CLR: rdata = __softirq_clr_rdata;
		default: rdata = 32'h0;
	endcase
	time_wen = __time_wen;
	time_o = time_wdata;
	time_ren = __time_ren;
	timeh_wen = __timeh_wen;
	timeh_o = timeh_wdata;
	timeh_ren = __timeh_ren;
	softirq_set_wen = __softirq_set_wen;
	softirq_set_o = softirq_set_wdata;
	softirq_set_ren = __softirq_set_ren;
	softirq_clr_wen = __softirq_clr_wen;
	softirq_clr_o = softirq_clr_wdata;
	softirq_clr_ren = __softirq_clr_ren;
end

always @ (posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		timecmp0_o <= 32'h0;
		timecmp0h_o <= 32'h0;
		timecmp1_o <= 32'h0;
		timecmp1h_o <= 32'h0;
	end else begin
		if (__timecmp0_wen)
			timecmp0_o <= timecmp0_wdata;
		if (__timecmp0h_wen)
			timecmp0h_o <= timecmp0h_wdata;
		if (__timecmp1_wen)
			timecmp1_o <= timecmp1_wdata;
		if (__timecmp1h_wen)
			timecmp1h_o <= timecmp1h_wdata;
	end
end

endmodule