data/full_repos/permissive/43858668/final_verilog/src/clib/c_one_hot_therm_conv.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_one_hot_therm_conv.v:35: Cannot find include file: c_functions.v\n`include "c_functions.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v.sv\n             c_functions.v\n             c_functions.v.v\n             c_functions.v.sv\n             obj_dir/c_functions.v\n             obj_dir/c_functions.v.v\n             obj_dir/c_functions.v.sv\n%Error: Exiting due to 1 error(s)\n'
module c_one_hot_therm_conv
  (data_in, data_out);
   
`include "c_functions.v"
   

   parameter width = 8;
   

   localparam depth = clogb(width);
   

   input [0:width-1] data_in;
   

   output [0:width-1] data_out;
   wire [0:width-1]   data_out;
   
   genvar 	      level;
   
   wire [0:(depth+1)*width-1] data_int;
   assign data_int[0:width-1] = data_in;
   
   generate
      
      for(level = 0; level < depth; level = level + 1)
	begin:levels
	   
	   wire [0:width-1] data_in;
	   assign data_in = data_int[level*width:(level+1)*width-1];
	   
	   wire [0:width-1] data_shifted;
	   assign data_shifted
	     = {{(1<<level){1'b0}}, data_in[0:width-(1<<level)-1]};
	   
	   wire [0:width-1] data_out;
	   assign data_out = data_in | data_shifted;
	   
	   assign data_int[(level+1)*width:(level+2)*width-1] = data_out;
	   
	end
      
   endgenerate
   
   assign data_out = data_int[depth*width:(depth+1)*width-1];
   
endmodule
module c_one_hot_therm_conv
  (data_in, data_out);

   
`include "c_functions.v"
   

   parameter width = 8;
   

   localparam depth = clogb(width);
   

   input [0:width-1] data_in;
   

   output [0:width-1] data_out;
   wire [0:width-1]   data_out;
   
   genvar 	      level;
   
   wire [0:(depth+1)*width-1] data_int;
   assign data_int[0:width-1] = data_in;
   
   generate
      
      for(level = 0; level < depth; level = level + 1)
	begin:levels
	   
	   wire [0:width-1] data_in;
	   assign data_in = data_int[level*width:(level+1)*width-1];
	   
	   wire [0:width-1] data_shifted;
	   assign data_shifted
	     = {{(1<<level){1'b0}}, data_in[0:width-(1<<level)-1]};
	   
	   wire [0:width-1] data_out;
	   assign data_out = data_in | data_shifted;
	   
	   assign data_int[(level+1)*width:(level+2)*width-1] = data_out;
	   
	end
      
   endgenerate
   
   assign data_out = data_int[depth*width:(depth+1)*width-1];
   
endmodule