data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:294: Multiple top level modules\n                                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                           : ... Top module \'counter\'\nmodule counter(\n       ^~~~~~~\n                                                                                           : ... Top module \'buf1clear\'\nmodule buf1clear(\n       ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:468: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'s_addr\' generates 15 bits.\n                                                                                        : ... In instance counter.sA\n      toSave = s_addr;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:476: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h2\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n      1: i_addr = 16\'d2;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:477: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h3\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n      2: i_addr = 16\'d3;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:478: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h4\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n      3: i_addr = 16\'d4;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:479: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h5\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n      4: i_addr = 16\'d5;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:480: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h6\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n      5: i_addr = 16\'d6;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:481: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h7\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n      6: i_addr = 16\'d7;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:482: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h8\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n      7: i_addr = 16\'d8;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:486: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h8\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n     if(exp) i_addr = 16\'d8;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:499: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s VARREF \'num\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n    JMP: if(dataAddr == 0) i_addr = num;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:518: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s VARREF \'num\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n        if(dataAddr == 0) i_addr = num;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:546: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh2\' generates 32 or 2 bits.\n                                                                                        : ... In instance counter.sA\n         n_int = 2;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:531: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s VARREF \'toCont\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n          i_addr = toCont;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/counterAddr.v:536: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s VARREF \'num\' generates 16 bits.\n                                                                                        : ... In instance counter.sA\n          i_addr = num;\n                 ^\n%Error: Exiting due to 15 warning(s)\n'
module przebuffer(
	input rst,
	
	input feirq,
	output reg eirq,
	
	input clk,
	input irq1,
	input irq2,
	input irq3,
	input rem,
	
	output reg oirq1,
	output reg oirq2,
	output reg oirq3
);

reg f_oirq1;
reg f_oirq2;
reg f_oirq3;

reg n_rem;

always@(posedge clk)begin
	if(rst) n_rem <= 0;
	else n_rem <= rem;
end

always@(posedge clk)begin
	if(rst) eirq <= 0;
	else eirq <= feirq;
end


always@(posedge clk)begin
	if(rst) begin
		f_oirq1 <= 0;
		f_oirq2 <= 0;
		f_oirq3 <= 0;

	end else begin
		f_oirq1 <= oirq1;
		f_oirq2 <= oirq2;
		f_oirq3 <= oirq3;
	end
end

always@(*)begin
		
	oirq1 = f_oirq1;
	oirq2 = f_oirq2;
	oirq3 = f_oirq3;
		
	if(irq1 | irq2 | irq3)begin
		if((~f_oirq1) & (~f_oirq2) & (~f_oirq3))begin
			oirq1 = irq1;
			oirq2 = irq2;
			oirq3 = irq3;
		end
		
	end else
		if(n_rem)begin
			oirq1 = 0;
			oirq2 = 0;
			oirq3 = 0;
		end
end

endmodule
module przebuffer(
	input rst,
	
	input feirq,
	output reg eirq,
	
	input clk,
	input irq1,
	input irq2,
	input irq3,
	input rem,
	
	output reg oirq1,
	output reg oirq2,
	output reg oirq3
);


reg f_oirq1;
reg f_oirq2;
reg f_oirq3;

reg n_rem;

always@(posedge clk)begin
	if(rst) n_rem <= 0;
	else n_rem <= rem;
end

always@(posedge clk)begin
	if(rst) eirq <= 0;
	else eirq <= feirq;
end


always@(posedge clk)begin
	if(rst) begin
		f_oirq1 <= 0;
		f_oirq2 <= 0;
		f_oirq3 <= 0;

	end else begin
		f_oirq1 <= oirq1;
		f_oirq2 <= oirq2;
		f_oirq3 <= oirq3;
	end
end

always@(*)begin
		
	oirq1 = f_oirq1;
	oirq2 = f_oirq2;
	oirq3 = f_oirq3;
		
	if(irq1 | irq2 | irq3)begin
		if((~f_oirq1) & (~f_oirq2) & (~f_oirq3))begin
			oirq1 = irq1;
			oirq2 = irq2;
			oirq3 = irq3;
		end
		
	end else
		if(n_rem)begin
			oirq1 = 0;
			oirq2 = 0;
			oirq3 = 0;
		end
end

endmodule