data/full_repos/permissive/486812922/src/alu.v
1: b'%Error: data/full_repos/permissive/486812922/src/alu.v:2: Cannot find include file: ctrl_encode_def.v\n`include "ctrl_encode_def.v"  \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/486812922/src,data/full_repos/permissive/486812922/ctrl_encode_def.v\n             data/full_repos/permissive/486812922/src,data/full_repos/permissive/486812922/ctrl_encode_def.v.v\n             data/full_repos/permissive/486812922/src,data/full_repos/permissive/486812922/ctrl_encode_def.v.sv\n             ctrl_encode_def.v\n             ctrl_encode_def.v.v\n             ctrl_encode_def.v.sv\n             obj_dir/ctrl_encode_def.v\n             obj_dir/ctrl_encode_def.v.v\n             obj_dir/ctrl_encode_def.v.sv\n%Error: data/full_repos/permissive/486812922/src/alu.v:26: Define or directive not defined: \'`ALUOp_ADD\'\n        `ALUOp_ADD:\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/alu.v:26: syntax error, unexpected \':\', expecting endcase\n        `ALUOp_ADD:\n                  ^\n%Error: data/full_repos/permissive/486812922/src/alu.v:28: Define or directive not defined: \'`ALUOp_ADDU\'\n        `ALUOp_ADDU:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/alu.v:30: Define or directive not defined: \'`ALUOp_SUB\'\n        `ALUOp_SUB:\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/alu.v:32: Define or directive not defined: \'`ALUOp_SUBU\'\n        `ALUOp_SUBU:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/alu.v:34: Define or directive not defined: \'`ALUOp_AND\'\n        `ALUOp_AND:\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/alu.v:36: Define or directive not defined: \'`ALUOp_OR\'\n        `ALUOp_OR:\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/alu.v:38: Define or directive not defined: \'`ALUOp_XOR\'\n        `ALUOp_XOR:\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/alu.v:40: Define or directive not defined: \'`ALUOp_NOR\'\n        `ALUOp_NOR:\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/alu.v:42: Define or directive not defined: \'`ALUOp_SLT\'\n        `ALUOp_SLT:\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/alu.v:44: Define or directive not defined: \'`ALUOp_SLTU\'\n        `ALUOp_SLTU:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/alu.v:46: Define or directive not defined: \'`ALUOp_SLL\'\n        `ALUOp_SLL:\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/alu.v:48: Define or directive not defined: \'`ALUOp_SRL\'\n        `ALUOp_SRL:\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/alu.v:50: Define or directive not defined: \'`ALUOp_SRA\'\n        `ALUOp_SRA:\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/alu.v:52: Define or directive not defined: \'`ALUOp_SLLV\'\n        `ALUOp_SLLV:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/alu.v:54: Define or directive not defined: \'`ALUOp_SRLV\'\n        `ALUOp_SRLV:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/alu.v:56: Define or directive not defined: \'`ALUOp_SRAV\'\n        `ALUOp_SRAV:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/alu.v:59: Define or directive not defined: \'`ALUOp_ADDI\'\n        `ALUOp_ADDI:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/alu.v:61: Define or directive not defined: \'`ALUOp_ADDIU\'\n        `ALUOp_ADDIU:\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/alu.v:63: Define or directive not defined: \'`ALUOp_ANDI\'\n        `ALUOp_ANDI:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/alu.v:65: Define or directive not defined: \'`ALUOp_ORI\'\n        `ALUOp_ORI:\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/alu.v:67: Define or directive not defined: \'`ALUOp_XORI\'\n        `ALUOp_XORI:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/alu.v:69: Define or directive not defined: \'`ALUOp_LUI\'\n        `ALUOp_LUI:\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/alu.v:71: Define or directive not defined: \'`ALUOp_BEQ\'\n        `ALUOp_BEQ:\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/alu.v:73: Define or directive not defined: \'`ALUOp_BNE\'\n        `ALUOp_BNE:\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/alu.v:75: Define or directive not defined: \'`ALUOp_SLTI\'\n        `ALUOp_SLTI:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/alu.v:77: Define or directive not defined: \'`ALUOp_SLTIU\'\n        `ALUOp_SLTIU:\n        ^~~~~~~~~~~~\n%Error: Cannot continue\n'
module alu_32(A, B, ALUOp, C, Zero);

input [31: 0] A;
input [31: 0] B;

input [4: 0] ALUOp;

output reg [31: 0] C;

output Zero;
assign Zero = C[0];


wire [32: 0] AS = {A[31], A[31: 0]};
wire [32: 0] AZ = {1'd0, A[31: 0]};
wire [32: 0] BZ = {1'd0, B[31: 0]};
wire [32: 0] BS = {B[31], B[31: 0]};
reg extend_f = 0;
always @( ALUOp or A or B ) begin
    C = 0;

    case ( ALUOp )
        `ALUOp_ADD:
            {extend_f, C} <= AS + BS;
        `ALUOp_ADDU:
            {extend_f, C} <= AS + BS;
        `ALUOp_SUB:
            C <= A - B;
        `ALUOp_SUBU:
            C <= A - B;
        `ALUOp_AND:
            C <= A & B;
        `ALUOp_OR:
            C <= A | B;
        `ALUOp_XOR:
            C <= A ^ B;
        `ALUOp_NOR:
            C <= ~(A | B);
        `ALUOp_SLT:
            C <= (A[31] && B[31] || !A[31] && !B[31]) ? (A < B) ? 1 : 0 : (A[31] && !B[31]) ? 1 : 0;
        `ALUOp_SLTU:
            C <= (A[31] && B[31] || !A[31] && !B[31]) ? (A < B) ? 1 : 0 : (A[31] && !B[31]) ? 1 : 0;
        `ALUOp_SLL:
            C <= B << A[4: 0];
        `ALUOp_SRL:
            C <= B >> A[4: 0];
        `ALUOp_SRA:
            C <= $signed(B) >>> A[4: 0];
        `ALUOp_SLLV:
            C <= B << A[4: 0];
        `ALUOp_SRLV:
            C <= B >> A[4: 0];
        `ALUOp_SRAV:
            C <= $signed(B) >>> A[4: 0];

        `ALUOp_ADDI:
            {extend_f, C} <= AS + BS;
        `ALUOp_ADDIU:
            {extend_f, C} <= AS + BS;
        `ALUOp_ANDI:
            C <= A & B;
        `ALUOp_ORI:
            C <= A | B;
        `ALUOp_XORI:
            C <= A ^ B;
        `ALUOp_LUI:
            C <= (B << 16) & 32'hffff0000;
        `ALUOp_BEQ:
            C <= (A == B) ? 32'd1 : 32'd0;
        `ALUOp_BNE:
            C <= (A != B) ? 32'd1 : 32'd0;
        `ALUOp_SLTI:
            C <= (A[31] && B[31] || !A[31] && !B[31]) ? (A < B) ? 1 : 0 : (A[31] && !B[31]) ? 1 : 0;
        `ALUOp_SLTIU:
            C <= (A[31] && B[31] || !A[31] && !B[31]) ? (A < B) ? 1 : 0 : (A[31] && !B[31]) ? 1 : 0;

        default:
            C <= 0;
    endcase
end
endmodule
module alu_32(A, B, ALUOp, C, Zero);


input [31: 0] A;
input [31: 0] B;

input [4: 0] ALUOp;

output reg [31: 0] C;

output Zero;
assign Zero = C[0];


wire [32: 0] AS = {A[31], A[31: 0]};
wire [32: 0] AZ = {1'd0, A[31: 0]};
wire [32: 0] BZ = {1'd0, B[31: 0]};
wire [32: 0] BS = {B[31], B[31: 0]};
reg extend_f = 0;
always @( ALUOp or A or B ) begin
    C = 0;

    case ( ALUOp )
        `ALUOp_ADD:
            {extend_f, C} <= AS + BS;
        `ALUOp_ADDU:
            {extend_f, C} <= AS + BS;
        `ALUOp_SUB:
            C <= A - B;
        `ALUOp_SUBU:
            C <= A - B;
        `ALUOp_AND:
            C <= A & B;
        `ALUOp_OR:
            C <= A | B;
        `ALUOp_XOR:
            C <= A ^ B;
        `ALUOp_NOR:
            C <= ~(A | B);
        `ALUOp_SLT:
            C <= (A[31] && B[31] || !A[31] && !B[31]) ? (A < B) ? 1 : 0 : (A[31] && !B[31]) ? 1 : 0;
        `ALUOp_SLTU:
            C <= (A[31] && B[31] || !A[31] && !B[31]) ? (A < B) ? 1 : 0 : (A[31] && !B[31]) ? 1 : 0;
        `ALUOp_SLL:
            C <= B << A[4: 0];
        `ALUOp_SRL:
            C <= B >> A[4: 0];
        `ALUOp_SRA:
            C <= $signed(B) >>> A[4: 0];
        `ALUOp_SLLV:
            C <= B << A[4: 0];
        `ALUOp_SRLV:
            C <= B >> A[4: 0];
        `ALUOp_SRAV:
            C <= $signed(B) >>> A[4: 0];

        `ALUOp_ADDI:
            {extend_f, C} <= AS + BS;
        `ALUOp_ADDIU:
            {extend_f, C} <= AS + BS;
        `ALUOp_ANDI:
            C <= A & B;
        `ALUOp_ORI:
            C <= A | B;
        `ALUOp_XORI:
            C <= A ^ B;
        `ALUOp_LUI:
            C <= (B << 16) & 32'hffff0000;
        `ALUOp_BEQ:
            C <= (A == B) ? 32'd1 : 32'd0;
        `ALUOp_BNE:
            C <= (A != B) ? 32'd1 : 32'd0;
        `ALUOp_SLTI:
            C <= (A[31] && B[31] || !A[31] && !B[31]) ? (A < B) ? 1 : 0 : (A[31] && !B[31]) ? 1 : 0;
        `ALUOp_SLTIU:
            C <= (A[31] && B[31] || !A[31] && !B[31]) ? (A < B) ? 1 : 0 : (A[31] && !B[31]) ? 1 : 0;

        default:
            C <= 0;
    endcase
end
endmodule