data/full_repos/permissive/515613617/lift.v
1: b'%Warning-WIDTH: data/full_repos/permissive/515613617/lift.v:20: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h1\' generates 6 bits.\n                                                              : ... In instance lift\nstop=6\'d1;\n    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/515613617/lift.v:21: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                              : ... In instance lift\ndoor = 1\'d1;\n     ^\n%Warning-WIDTH: data/full_repos/permissive/515613617/lift.v:22: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                              : ... In instance lift\nUp=1\'d0;\n  ^\n%Warning-WIDTH: data/full_repos/permissive/515613617/lift.v:23: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                              : ... In instance lift\nDown=1\'d0;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/515613617/lift.v:33: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                              : ... In instance lift\ndoor=1\'d0;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/515613617/lift.v:34: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                              : ... In instance lift\nstop=1\'d0;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/515613617/lift.v:35: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                              : ... In instance lift\nUp=1\'d0;\n  ^\n%Warning-WIDTH: data/full_repos/permissive/515613617/lift.v:36: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                              : ... In instance lift\nDown=1\'d1;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/515613617/lift.v:43: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                              : ... In instance lift\ndoor=1\'d0;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/515613617/lift.v:44: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                              : ... In instance lift\nstop=1\'d0;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/515613617/lift.v:45: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                              : ... In instance lift\nUp=1\'d1;\n  ^\n%Warning-WIDTH: data/full_repos/permissive/515613617/lift.v:46: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                              : ... In instance lift\nDown=1\'d0;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/515613617/lift.v:52: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                              : ... In instance lift\ndoor=1\'d1;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/515613617/lift.v:53: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                              : ... In instance lift\nstop=1\'d1;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/515613617/lift.v:54: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                              : ... In instance lift\nUp=1\'d0;\n  ^\n%Warning-WIDTH: data/full_repos/permissive/515613617/lift.v:55: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                              : ... In instance lift\nDown=1\'d0;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/515613617/lift.v:27: Operator LT expects 6 bits on the RHS, but RHS\'s CONST \'5\'h1f\' generates 5 bits.\n                                                              : ... In instance lift\nif(req_floor < 5\'d31)\n             ^\n%Error: Exiting due to 17 warning(s)\n'
module lift(clk,reset,req_floor,stop,door,Up,Down,y);
input clk,reset;
input [5:0] req_floor;
output reg[1:0] door;
output reg[1:0] Up;
output reg[1:0] Down;
output reg[1:0] stop;

output [5:0] y;
reg [5:0] cf ;

always @ (posedge clk)
begin

if(reset)
begin
cf=6'd0;
stop=6'd1;
door = 1'd1;
Up=1'd0;
Down=1'd0;
end
else
begin
if(req_floor < 5'd31)
begin

if(req_floor < cf )
begin
cf=cf-1;
door=1'd0;
stop=1'd0;
Up=1'd0;
Down=1'd1;
end


else if (req_floor > cf)
begin
cf = cf+1;
door=1'd0;
stop=1'd0;
Up=1'd1;
Down=1'd0;
end

else if(req_floor == cf )
begin
cf = req_floor;
door=1'd1;
stop=1'd1;
Up=1'd0;
Down=1'd0;
end
end


end


end


assign y = cf;

endmodule
module lift(clk,reset,req_floor,stop,door,Up,Down,y);

input clk,reset;
input [5:0] req_floor;
output reg[1:0] door;
output reg[1:0] Up;
output reg[1:0] Down;
output reg[1:0] stop;

output [5:0] y;
reg [5:0] cf ;

always @ (posedge clk)
begin

if(reset)
begin
cf=6'd0;
stop=6'd1;
door = 1'd1;
Up=1'd0;
Down=1'd0;
end
else
begin
if(req_floor < 5'd31)
begin

if(req_floor < cf )
begin
cf=cf-1;
door=1'd0;
stop=1'd0;
Up=1'd0;
Down=1'd1;
end


else if (req_floor > cf)
begin
cf = cf+1;
door=1'd0;
stop=1'd0;
Up=1'd1;
Down=1'd0;
end

else if(req_floor == cf )
begin
cf = req_floor;
door=1'd1;
stop=1'd1;
Up=1'd0;
Down=1'd0;
end
end


end


end


assign y = cf;

endmodule