data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/register_interface/src/reg_uniform.sv
1: b'%Warning-MULTITOP: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/register_interface/src/reg_uniform.sv:32: Multiple top level modules\n                                                                                                                                                 : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                                                                 : ... Top module \'reg_uniform\'\nmodule reg_uniform #(\n       ^~~~~~~~~~~\n                                                                                                                                                 : ... Top module \'REG_BUS\'\n  REG_BUS.in   reg_i\n  ^~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/register_interface/src/reg_uniform.sv:32: Unsupported: Interfaced port on top level module\n  REG_BUS.in   reg_i\n               ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/register_interface/src/reg_uniform.sv:32: Cannot find file containing interface: \'REG_BUS\'\n  REG_BUS.in   reg_i\n  ^~~~~~~\n%Error: Internal Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/register_interface/src/reg_uniform.sv:32: ../V3LinkDot.cpp:2055: Unlinked interface\n  REG_BUS.in   reg_i\n  ^~~~~~~\n'
module reg_uniform #(

  parameter int ADDR_WIDTH = -1,

  parameter int DATA_WIDTH = -1,

  parameter int NUM_REG = -1,

  parameter int REG_WIDTH = -1,

  parameter logic [NUM_REG-1:0] REG_WRITABLE = '1
)(
  input  logic                              clk_i      ,
  input  logic                              rst_ni     ,
  input  logic [NUM_REG-1:0][REG_WIDTH-1:0] init_val_i ,
  input  logic [NUM_REG-1:0][REG_WIDTH-1:0] rd_val_i   ,
  output logic [NUM_REG-1:0][REG_WIDTH-1:0] wr_val_o   ,
  output logic [NUM_REG-1:0]                wr_evt_o   ,
  REG_BUS.in   reg_i
);


  logic [NUM_REG-1:0][REG_WIDTH-1:0] reg_q;
  logic [NUM_REG-1:0][REG_WIDTH/8-1:0] reg_wr;

  for (genvar i = 0; i < NUM_REG; i++) begin


    if (REG_WRITABLE[i]) begin

      for (genvar j = 0; j < REG_WIDTH/8; j++) begin
        always_ff @(posedge clk_i, negedge rst_ni) begin
          if (!rst_ni)
            reg_q[i][j*8+7 -: 8] <= init_val_i[i][j*8+7 -: 8];
          else if (reg_wr[i][j])
            reg_q[i][j*8+7 -: 8] <= reg_i.wdata[(i*REG_WIDTH+j*8+7)%DATA_WIDTH -: 8];
        end
      end
    end else begin
      assign reg_q[i] = init_val_i[i];
    end
  end


  always_comb begin
    wr_val_o = reg_q;
    for (int i = 0; i < NUM_REG; i++)
      wr_evt_o[i] = |reg_wr[i];
  end


  localparam int ADDR_SHIFT = $clog2(DATA_WIDTH/8);
  logic [ADDR_WIDTH-ADDR_SHIFT-1:0] bus_word_addr;
  assign bus_word_addr = reg_i.addr >> ADDR_SHIFT;


  localparam int NUM_BUS_WORDS = (NUM_REG * REG_WIDTH + DATA_WIDTH - 1) / DATA_WIDTH;
  logic [NUM_BUS_WORDS-1:0][DATA_WIDTH-1:0] reg_busmapped;
  logic [NUM_BUS_WORDS-1:0][DATA_WIDTH/8-1:0] reg_wr_busmapped;
  assign reg_busmapped = rd_val_i;
  assign reg_wr = reg_wr_busmapped;


  always_comb begin
    reg_wr_busmapped = '0;
    reg_i.ready = 1;
    reg_i.rdata = '0;
    reg_i.error = 0;
    if (reg_i.valid) begin
      if (bus_word_addr < NUM_BUS_WORDS) begin
        reg_i.rdata = reg_busmapped[bus_word_addr];
        if (reg_i.write) begin
          reg_wr_busmapped[bus_word_addr] = reg_i.wstrb;
        end
      end else begin
        reg_i.error = 1;
      end
    end
  end

endmodule
module reg_uniform #(

  parameter int ADDR_WIDTH = -1,

  parameter int DATA_WIDTH = -1,

  parameter int NUM_REG = -1,

  parameter int REG_WIDTH = -1,

  parameter logic [NUM_REG-1:0] REG_WRITABLE = '1
)(
  input  logic                              clk_i      ,
  input  logic                              rst_ni     ,
  input  logic [NUM_REG-1:0][REG_WIDTH-1:0] init_val_i ,
  input  logic [NUM_REG-1:0][REG_WIDTH-1:0] rd_val_i   ,
  output logic [NUM_REG-1:0][REG_WIDTH-1:0] wr_val_o   ,
  output logic [NUM_REG-1:0]                wr_evt_o   ,
  REG_BUS.in   reg_i
);



  logic [NUM_REG-1:0][REG_WIDTH-1:0] reg_q;
  logic [NUM_REG-1:0][REG_WIDTH/8-1:0] reg_wr;

  for (genvar i = 0; i < NUM_REG; i++) begin


    if (REG_WRITABLE[i]) begin

      for (genvar j = 0; j < REG_WIDTH/8; j++) begin
        always_ff @(posedge clk_i, negedge rst_ni) begin
          if (!rst_ni)
            reg_q[i][j*8+7 -: 8] <= init_val_i[i][j*8+7 -: 8];
          else if (reg_wr[i][j])
            reg_q[i][j*8+7 -: 8] <= reg_i.wdata[(i*REG_WIDTH+j*8+7)%DATA_WIDTH -: 8];
        end
      end
    end else begin
      assign reg_q[i] = init_val_i[i];
    end
  end


  always_comb begin
    wr_val_o = reg_q;
    for (int i = 0; i < NUM_REG; i++)
      wr_evt_o[i] = |reg_wr[i];
  end


  localparam int ADDR_SHIFT = $clog2(DATA_WIDTH/8);
  logic [ADDR_WIDTH-ADDR_SHIFT-1:0] bus_word_addr;
  assign bus_word_addr = reg_i.addr >> ADDR_SHIFT;


  localparam int NUM_BUS_WORDS = (NUM_REG * REG_WIDTH + DATA_WIDTH - 1) / DATA_WIDTH;
  logic [NUM_BUS_WORDS-1:0][DATA_WIDTH-1:0] reg_busmapped;
  logic [NUM_BUS_WORDS-1:0][DATA_WIDTH/8-1:0] reg_wr_busmapped;
  assign reg_busmapped = rd_val_i;
  assign reg_wr = reg_wr_busmapped;


  always_comb begin
    reg_wr_busmapped = '0;
    reg_i.ready = 1;
    reg_i.rdata = '0;
    reg_i.error = 0;
    if (reg_i.valid) begin
      if (bus_word_addr < NUM_BUS_WORDS) begin
        reg_i.rdata = reg_busmapped[bus_word_addr];
        if (reg_i.write) begin
          reg_wr_busmapped[bus_word_addr] = reg_i.wstrb;
        end
      end else begin
        reg_i.error = 1;
      end
    end
  end

endmodule