data/full_repos/permissive/515625485/usr_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/515625485/usr_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n    rst = 1; #10; rst = 0; #10;\n             ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/515625485/usr_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n    rst = 1; #10; rst = 0; #10;\n                           ^\n%Warning-STMTDLY: data/full_repos/permissive/515625485/usr_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n    mode = 2\'b00; rst = 1; #10; rst = 0; #10;\n                           ^\n%Warning-STMTDLY: data/full_repos/permissive/515625485/usr_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n    mode = 2\'b00; rst = 1; #10; rst = 0; #10;\n                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/515625485/usr_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n    mode = 2\'b01; inp = 4\'b0011; #10;\n                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/515625485/usr_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n    MODE = 2\'b01; DATAIN = 4\'b0011; #10;\n                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/515625485/usr_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n    MODE = 2\'b00; reset = 1; #10; reset = 0; #10;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/515625485/usr_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n    MODE = 2\'b00; reset = 1; #10; reset = 0; #10;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/515625485/usr_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n    MODE = 2\'b10; DATAIN = 4\'b0111; #10;\n                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/515625485/usr_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n    MODE = 2\'b10; DATAIN = 4\'b0111; #10;\n                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/515625485/usr_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n    MODE = 2\'b00; reset = 1; #10; reset = 0; #10;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/515625485/usr_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n    MODE = 2\'b00; reset = 1; #10; reset = 0; #10;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/515625485/usr_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n    MODE = 2\'b11; DATAIN = 4\'b1010; #10;\n                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/515625485/usr_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515625485/usr_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n  always #5 clock = ~clock;\n         ^\n%Error: data/full_repos/permissive/515625485/usr_tb.v:22: Can\'t find definition of variable: \'MODE\'\n    MODE = 2\'b01; DATAIN = 4\'b0011; #10;\n    ^~~~\n%Error: data/full_repos/permissive/515625485/usr_tb.v:22: Can\'t find definition of variable: \'DATAIN\'\n    MODE = 2\'b01; DATAIN = 4\'b0011; #10;\n                  ^~~~~~\n%Error: data/full_repos/permissive/515625485/usr_tb.v:23: Can\'t find definition of variable: \'DATAOUT\'\n    if ( DATAOUT === 4\'b1100 ) \n         ^~~~~~~\n%Error: data/full_repos/permissive/515625485/usr_tb.v:30: Can\'t find definition of variable: \'reset\'\n                                                        : ... Suggested alternative: \'rst\'\n    MODE = 2\'b00; reset = 1; #10; reset = 0; #10;\n                  ^~~~~\n%Error: data/full_repos/permissive/515625485/usr_tb.v:59: Can\'t find definition of variable: \'clock\'\n                                                        : ... Suggested alternative: \'clk\'\n  always #5 clock = ~clock;\n                     ^~~~~\n%Error: Exiting due to 5 error(s), 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module universalShiftRegisterTb;
  wire [3:0] outp;
  reg clk, rst;
  reg [1:0] mode;
  reg [3:0] inp;
  
  universalShiftRegister jusr(outp, clk, rst, mode, inp);
  
  initial
  begin
    clk =0; mode = 2'b00; inp = 4'b0000;
    rst = 1; #10; rst = 0; #10;
    
    $display("RSLT\tD == DOUT");

    mode = 2'b00; rst = 1; #10; rst = 0; #10;
    mode = 2'b01; inp = 4'b0011; #10;
    if ( outp === 4'b1000 ) 
      $display("PASS\t%p is %p with %p", inp, mode, outp);
    else
      $display("FAIL\t%p is %p with %p", inp, mode, outp);
    MODE = 2'b01; DATAIN = 4'b0011; #10;
    if ( DATAOUT === 4'b1100 ) 
      $display("PASS\t%p is %p with %p",inp, mode, outp);
    else
      $display("FAIL\t%p is %p with %p", inp, mode, outp);
    
    

    MODE = 2'b00; reset = 1; #10; reset = 0; #10;
    MODE = 2'b10; DATAIN = 4'b0111; #10;
    if ( DATAOUT === 4'b0001 ) 
      $display("PASS\t%p is %p with %p",inp, mode, outp);
    else
      $display("FAIL\t%p is %p with %p", inp, mode, outp);
    MODE = 2'b10; DATAIN = 4'b0111; #10;
    if ( DATAOUT === 4'b0011 ) 
      $display("PASS\t%p is %p with %p", inp, mode, outp);
    else
      $display("FAIL\t%p is %p with %p", inp, mode, outp);



    MODE = 2'b00; reset = 1; #10; reset = 0; #10;
    MODE = 2'b11; DATAIN = 4'b1010; #10;
    if ( DATAOUT === 4'b1010 )
      $display("PASS\t%p is %p with %p", inp, mode, outp);
    else
      $display("FAIL\t%p is %p with %p", inp, mode, outp);

    #20;
    $finish;
  end
  
    
  

  
  always #5 clock = ~clock;
  
endmodule
module universalShiftRegisterTb;

  wire [3:0] outp;
  reg clk, rst;
  reg [1:0] mode;
  reg [3:0] inp;
  
  universalShiftRegister jusr(outp, clk, rst, mode, inp);
  
  initial
  begin
    clk =0; mode = 2'b00; inp = 4'b0000;
    rst = 1; #10; rst = 0; #10;
    
    $display("RSLT\tD == DOUT");

    mode = 2'b00; rst = 1; #10; rst = 0; #10;
    mode = 2'b01; inp = 4'b0011; #10;
    if ( outp === 4'b1000 ) 
      $display("PASS\t%p is %p with %p", inp, mode, outp);
    else
      $display("FAIL\t%p is %p with %p", inp, mode, outp);
    MODE = 2'b01; DATAIN = 4'b0011; #10;
    if ( DATAOUT === 4'b1100 ) 
      $display("PASS\t%p is %p with %p",inp, mode, outp);
    else
      $display("FAIL\t%p is %p with %p", inp, mode, outp);
    
    

    MODE = 2'b00; reset = 1; #10; reset = 0; #10;
    MODE = 2'b10; DATAIN = 4'b0111; #10;
    if ( DATAOUT === 4'b0001 ) 
      $display("PASS\t%p is %p with %p",inp, mode, outp);
    else
      $display("FAIL\t%p is %p with %p", inp, mode, outp);
    MODE = 2'b10; DATAIN = 4'b0111; #10;
    if ( DATAOUT === 4'b0011 ) 
      $display("PASS\t%p is %p with %p", inp, mode, outp);
    else
      $display("FAIL\t%p is %p with %p", inp, mode, outp);



    MODE = 2'b00; reset = 1; #10; reset = 0; #10;
    MODE = 2'b11; DATAIN = 4'b1010; #10;
    if ( DATAOUT === 4'b1010 )
      $display("PASS\t%p is %p with %p", inp, mode, outp);
    else
      $display("FAIL\t%p is %p with %p", inp, mode, outp);

    #20;
    $finish;
  end
  
    
  

  
  always #5 clock = ~clock;
  
endmodule