data/full_repos/permissive/419677538/Exercise_1/verilog_code/FourBitRippleCarryAdder.v
1: b"%Error: data/full_repos/permissive/419677538/Exercise_1/verilog_code/FourBitRippleCarryAdder.v:6: Cannot find file containing module: 'FABehav'\n   FABehav fa1(a[0], b[0], cstart, s[0], fa1_Cout);\n   ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/419677538/Exercise_1/verilog_code,data/full_repos/permissive/419677538/FABehav\n             data/full_repos/permissive/419677538/Exercise_1/verilog_code,data/full_repos/permissive/419677538/FABehav.v\n             data/full_repos/permissive/419677538/Exercise_1/verilog_code,data/full_repos/permissive/419677538/FABehav.sv\n             FABehav\n             FABehav.v\n             FABehav.sv\n             obj_dir/FABehav\n             obj_dir/FABehav.v\n             obj_dir/FABehav.sv\n%Error: data/full_repos/permissive/419677538/Exercise_1/verilog_code/FourBitRippleCarryAdder.v:7: Cannot find file containing module: 'FABehav'\n   FABehav fa2(a[1], b[1], fa1_Cout, s[1], fa2_Cout);\n   ^~~~~~~\n%Error: data/full_repos/permissive/419677538/Exercise_1/verilog_code/FourBitRippleCarryAdder.v:8: Cannot find file containing module: 'FABehav'\n   FABehav fa3(a[2], b[2], fa2_Cout, s[2], fa3_Cout);\n   ^~~~~~~\n%Error: data/full_repos/permissive/419677538/Exercise_1/verilog_code/FourBitRippleCarryAdder.v:9: Cannot find file containing module: 'FABehav'\n   FABehav fa4(a[3], b[3], fa3_Cout, s[3], s[4]);\n   ^~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module FourBitRippleCarryAdder(a,b,cstart,s);
   output [4:0] s ;
   input [3:0] a,b;
   input cstart;
   wire fa1_Cout,fa2_Cout,fa3_Cout;
   FABehav fa1(a[0], b[0], cstart, s[0], fa1_Cout);
   FABehav fa2(a[1], b[1], fa1_Cout, s[1], fa2_Cout);
   FABehav fa3(a[2], b[2], fa2_Cout, s[2], fa3_Cout);
   FABehav fa4(a[3], b[3], fa3_Cout, s[3], s[4]);
endmodule
module FourBitRippleCarryAdder(a,b,cstart,s);

   output [4:0] s ;
   input [3:0] a,b;
   input cstart;
   wire fa1_Cout,fa2_Cout,fa3_Cout;
   FABehav fa1(a[0], b[0], cstart, s[0], fa1_Cout);
   FABehav fa2(a[1], b[1], fa1_Cout, s[1], fa2_Cout);
   FABehav fa3(a[2], b[2], fa2_Cout, s[2], fa3_Cout);
   FABehav fa4(a[3], b[3], fa3_Cout, s[3], s[4]);
endmodule