data/full_repos/permissive/492772061/ADPPulse/slow/ADP_Sim_Slow.srcs/sources_1/new/ledIndicator.v
data/verilator_xmls/e63ee03c-ec2c-43f2-85db-8cbd9d23efed.xml
module ledIndicator(
    input clk,
    output ledline
    );
    
    reg [31:0]clkdiv = 32'd0;

    reg led;
    
    assign ledline = led;
    
    always @ (posedge clk) begin
        clkdiv <= clkdiv +1'd1;
        if (clkdiv >= 50000000) begin
            clkdiv <= 0;
            led <= ~led;
        end
    end
endmodule
module ledIndicator(
    input clk,
    output ledline
    );

    
    reg [31:0]clkdiv = 32'd0;

    reg led;
    
    assign ledline = led;
    
    always @ (posedge clk) begin
        clkdiv <= clkdiv +1'd1;
        if (clkdiv >= 50000000) begin
            clkdiv <= 0;
            led <= ~led;
        end
    end
endmodule