data/full_repos/permissive/424312442/HW3/Question 4/HW3_4.v
1: b'%Error: Cannot find file containing module: 4,data/full_repos/permissive/424312442\n        ... Looked in:\n             data/full_repos/permissive/424312442/HW3/Question/4,data/full_repos/permissive/424312442\n             data/full_repos/permissive/424312442/HW3/Question/4,data/full_repos/permissive/424312442.v\n             data/full_repos/permissive/424312442/HW3/Question/4,data/full_repos/permissive/424312442.sv\n             4,data/full_repos/permissive/424312442\n             4,data/full_repos/permissive/424312442.v\n             4,data/full_repos/permissive/424312442.sv\n             obj_dir/4,data/full_repos/permissive/424312442\n             obj_dir/4,data/full_repos/permissive/424312442.v\n             obj_dir/4,data/full_repos/permissive/424312442.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/424312442/HW3/Question\n%Error: Cannot find file containing module: 4/HW3_4.v\n%Error: Exiting due to 3 error(s)\n'
module comparitor_4bit(A, B, GTin, EQin, LTin, GTout, EQout, LTout);
input [3:0] A, B;
input GTin, EQin, LTin;
output reg GTout, EQout, LTout;

always @(A, B, GTin, EQin, LTin) begin
    if (A > B) begin
        GTout <= 1;
        EQout <= 0;
        LTout <= 0;
    end else if (A < B) begin
        GTout <= 0;
        EQout <= 0;
        LTout <= 1;
    end else if (A == B) begin
        if (GTin || LTin) begin
            GTout <= GTin;
            EQout <= 0;
            LTout <= LTin;
        end else begin
            GTout <= 0;
            EQout <= 1;
            LTout <= 0;
        end
    end
end
endmodule
module comparitor_4bit(A, B, GTin, EQin, LTin, GTout, EQout, LTout);

input [3:0] A, B;
input GTin, EQin, LTin;
output reg GTout, EQout, LTout;

always @(A, B, GTin, EQin, LTin) begin
    if (A > B) begin
        GTout <= 1;
        EQout <= 0;
        LTout <= 0;
    end else if (A < B) begin
        GTout <= 0;
        EQout <= 0;
        LTout <= 1;
    end else if (A == B) begin
        if (GTin || LTin) begin
            GTout <= GTin;
            EQout <= 0;
            LTout <= LTin;
        end else begin
            GTout <= 0;
            EQout <= 1;
            LTout <= 0;
        end
    end
end
endmodule