data/full_repos/permissive/431474762/MEM.v
1: b'%Error: data/full_repos/permissive/431474762/MEM.v:1: Cannot find include file: lib/defines.vh\n`include "lib/defines.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/431474762,data/full_repos/permissive/431474762/lib/defines.vh\n             data/full_repos/permissive/431474762,data/full_repos/permissive/431474762/lib/defines.vh.v\n             data/full_repos/permissive/431474762,data/full_repos/permissive/431474762/lib/defines.vh.sv\n             lib/defines.vh\n             lib/defines.vh.v\n             lib/defines.vh.sv\n             obj_dir/lib/defines.vh\n             obj_dir/lib/defines.vh.v\n             obj_dir/lib/defines.vh.sv\n%Error: data/full_repos/permissive/431474762/MEM.v:6: Define or directive not defined: \'`StallBus\'\n    input wire [`StallBus-1:0] stall,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/431474762/MEM.v:7: Define or directive not defined: \'`EX_TO_MEM_WD\'\n    input wire [`EX_TO_MEM_WD-1:0] ex_to_mem_bus,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/431474762/MEM.v:9: Define or directive not defined: \'`MEM_TO_WB_WD\'\n    output wire [`MEM_TO_WB_WD-1:0] mem_to_wb_bus,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/431474762/MEM.v:10: Define or directive not defined: \'`MEM_TO_ID_WD\'\n    output wire [`MEM_TO_ID_WD-1:0] mem_to_id_bus\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/431474762/MEM.v:13: Define or directive not defined: \'`EX_TO_MEM_WD\'\n    reg [`EX_TO_MEM_WD-1:0] ex_to_mem_bus_r;\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/431474762/MEM.v:22: Define or directive not defined: \'`EX_TO_MEM_WD\'\n            ex_to_mem_bus_r <= `EX_TO_MEM_WD\'b0;\n                               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/431474762/MEM.v:27: Define or directive not defined: \'`Stop\'\n        else if (stall[3]==`Stop && stall[4]==`NoStop) begin\n                           ^~~~~\n%Error: data/full_repos/permissive/431474762/MEM.v:27: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n        else if (stall[3]==`Stop && stall[4]==`NoStop) begin\n                                 ^~\n%Error: data/full_repos/permissive/431474762/MEM.v:27: Define or directive not defined: \'`NoStop\'\n        else if (stall[3]==`Stop && stall[4]==`NoStop) begin\n                                              ^~~~~~~\n%Error: data/full_repos/permissive/431474762/MEM.v:28: Define or directive not defined: \'`EX_TO_MEM_WD\'\n            ex_to_mem_bus_r <= `EX_TO_MEM_WD\'b0;\n                               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/431474762/MEM.v:30: Define or directive not defined: \'`NoStop\'\n        else if (stall[3]==`NoStop) begin\n                           ^~~~~~~\n%Error: Exiting due to 12 error(s)\n'
module MEM(
    input wire clk,
    input wire rst,

    input wire [`StallBus-1:0] stall,
    input wire [`EX_TO_MEM_WD-1:0] ex_to_mem_bus,
    input wire [31:0] data_sram_rdata,
    output wire [`MEM_TO_WB_WD-1:0] mem_to_wb_bus,
    output wire [`MEM_TO_ID_WD-1:0] mem_to_id_bus
);

    reg [`EX_TO_MEM_WD-1:0] ex_to_mem_bus_r;
    wire mem_to_iden;
    wire [4:0] mem_to_idregaddr;
    wire [31:0] mem_to_idata;
    wire mem_id_hlwe;
    wire [1:0]mem_id_hlwaddr;
    wire [63:0] mem_id_hlwdata;
    always @ (posedge clk) begin
        if (rst) begin
            ex_to_mem_bus_r <= `EX_TO_MEM_WD'b0;
        end



        else if (stall[3]==`Stop && stall[4]==`NoStop) begin
            ex_to_mem_bus_r <= `EX_TO_MEM_WD'b0;
        end
        else if (stall[3]==`NoStop) begin
            ex_to_mem_bus_r <= ex_to_mem_bus;
        end
    end

    wire [31:0] mem_pc;
    wire data_ram_en;
    wire [3:0] data_ram_wen;
    wire sel_rf_res;
    wire rf_we;
    wire [4:0] rf_waddr;
    wire [31:0] rf_wdata;
    wire hl_we;
    wire [1:0]hl_waddr;
    wire [63:0] hl_rdata;
    wire [31:0] ex_result;
    wire [31:0] mem_result;
    wire [5:0] ld_type_i;
    wire [1:0] addr_ram_i;
    assign {
        addr_ram_i,
        hl_rdata,
        hl_waddr,
        hl_we,
        ld_type_i,
        mem_pc,
        data_ram_en,
        data_ram_wen,
        sel_rf_res,
        rf_we,
        rf_waddr,
        ex_result
    } =  ex_to_mem_bus_r;
    

    assign mem_result=(ld_type_i==6'b10_0000)&&(addr_ram_i==2'b00)?{{24{data_sram_rdata[7]}},data_sram_rdata[7:0]}:
                       (ld_type_i==6'b10_0000)&&(addr_ram_i==2'b01)?{{24{data_sram_rdata[15]}},data_sram_rdata[15:8]}:
                       (ld_type_i==6'b10_0000)&&(addr_ram_i==2'b10)?{{24{data_sram_rdata[23]}},data_sram_rdata[23:16]}:
                       (ld_type_i==6'b10_0000)&&(addr_ram_i==2'b11)?{{24{data_sram_rdata[31]}},data_sram_rdata[31:24]}:
                       (ld_type_i==6'b10_0100)&&(addr_ram_i==2'b00)?{24'b0,data_sram_rdata[7:0]}:
                       (ld_type_i==6'b10_0100)&&(addr_ram_i==2'b01)?{24'b0,data_sram_rdata[15:8]}:
                       (ld_type_i==6'b10_0100)&&(addr_ram_i==2'b10)?{24'b0,data_sram_rdata[23:16]}:
                       (ld_type_i==6'b10_0100)&&(addr_ram_i==2'b11)?{24'b0,data_sram_rdata[31:24]}:
                       (ld_type_i==6'b10_0001)&&(addr_ram_i==2'b00)?{{16{data_sram_rdata[15]}},data_sram_rdata[15:0]}:
                       (ld_type_i==6'b10_0001)&&(addr_ram_i==2'b10)?{{16{data_sram_rdata[31]}},data_sram_rdata[31:16]}:
                       (ld_type_i==6'b10_0101)&&(addr_ram_i==2'b00)?{16'b0,data_sram_rdata[15:0]}:
                       (ld_type_i==6'b10_0101)&&(addr_ram_i==2'b10)?{16'b0,data_sram_rdata[31:16]}:
                       (ld_type_i==6'b10_0011)?data_sram_rdata[31:0]:32'b0;
    assign rf_wdata = sel_rf_res ? mem_result : ex_result;

    assign mem_to_wb_bus = {
        hl_rdata,
        hl_waddr,
        hl_we,
        mem_pc,
        rf_we,
        rf_waddr,
        rf_wdata
    };
    assign mem_to_iden=rf_we;
    assign mem_to_idregaddr=rf_waddr;
    assign mem_to_idata=rf_wdata;
    assign mem_id_hlwe=hl_we;
    assign mem_id_hlwaddr=hl_waddr;
    assign mem_id_hlwdata=hl_rdata;
    assign mem_to_id_bus={
      mem_id_hlwdata,
      mem_id_hlwaddr,
      mem_id_hlwe,
      mem_to_iden,
      mem_to_idregaddr,
      mem_to_idata
    };

endmodule
module MEM(
    input wire clk,
    input wire rst,

    input wire [`StallBus-1:0] stall,
    input wire [`EX_TO_MEM_WD-1:0] ex_to_mem_bus,
    input wire [31:0] data_sram_rdata,
    output wire [`MEM_TO_WB_WD-1:0] mem_to_wb_bus,
    output wire [`MEM_TO_ID_WD-1:0] mem_to_id_bus
);


    reg [`EX_TO_MEM_WD-1:0] ex_to_mem_bus_r;
    wire mem_to_iden;
    wire [4:0] mem_to_idregaddr;
    wire [31:0] mem_to_idata;
    wire mem_id_hlwe;
    wire [1:0]mem_id_hlwaddr;
    wire [63:0] mem_id_hlwdata;
    always @ (posedge clk) begin
        if (rst) begin
            ex_to_mem_bus_r <= `EX_TO_MEM_WD'b0;
        end



        else if (stall[3]==`Stop && stall[4]==`NoStop) begin
            ex_to_mem_bus_r <= `EX_TO_MEM_WD'b0;
        end
        else if (stall[3]==`NoStop) begin
            ex_to_mem_bus_r <= ex_to_mem_bus;
        end
    end

    wire [31:0] mem_pc;
    wire data_ram_en;
    wire [3:0] data_ram_wen;
    wire sel_rf_res;
    wire rf_we;
    wire [4:0] rf_waddr;
    wire [31:0] rf_wdata;
    wire hl_we;
    wire [1:0]hl_waddr;
    wire [63:0] hl_rdata;
    wire [31:0] ex_result;
    wire [31:0] mem_result;
    wire [5:0] ld_type_i;
    wire [1:0] addr_ram_i;
    assign {
        addr_ram_i,
        hl_rdata,
        hl_waddr,
        hl_we,
        ld_type_i,
        mem_pc,
        data_ram_en,
        data_ram_wen,
        sel_rf_res,
        rf_we,
        rf_waddr,
        ex_result
    } =  ex_to_mem_bus_r;
    

    assign mem_result=(ld_type_i==6'b10_0000)&&(addr_ram_i==2'b00)?{{24{data_sram_rdata[7]}},data_sram_rdata[7:0]}:
                       (ld_type_i==6'b10_0000)&&(addr_ram_i==2'b01)?{{24{data_sram_rdata[15]}},data_sram_rdata[15:8]}:
                       (ld_type_i==6'b10_0000)&&(addr_ram_i==2'b10)?{{24{data_sram_rdata[23]}},data_sram_rdata[23:16]}:
                       (ld_type_i==6'b10_0000)&&(addr_ram_i==2'b11)?{{24{data_sram_rdata[31]}},data_sram_rdata[31:24]}:
                       (ld_type_i==6'b10_0100)&&(addr_ram_i==2'b00)?{24'b0,data_sram_rdata[7:0]}:
                       (ld_type_i==6'b10_0100)&&(addr_ram_i==2'b01)?{24'b0,data_sram_rdata[15:8]}:
                       (ld_type_i==6'b10_0100)&&(addr_ram_i==2'b10)?{24'b0,data_sram_rdata[23:16]}:
                       (ld_type_i==6'b10_0100)&&(addr_ram_i==2'b11)?{24'b0,data_sram_rdata[31:24]}:
                       (ld_type_i==6'b10_0001)&&(addr_ram_i==2'b00)?{{16{data_sram_rdata[15]}},data_sram_rdata[15:0]}:
                       (ld_type_i==6'b10_0001)&&(addr_ram_i==2'b10)?{{16{data_sram_rdata[31]}},data_sram_rdata[31:16]}:
                       (ld_type_i==6'b10_0101)&&(addr_ram_i==2'b00)?{16'b0,data_sram_rdata[15:0]}:
                       (ld_type_i==6'b10_0101)&&(addr_ram_i==2'b10)?{16'b0,data_sram_rdata[31:16]}:
                       (ld_type_i==6'b10_0011)?data_sram_rdata[31:0]:32'b0;
    assign rf_wdata = sel_rf_res ? mem_result : ex_result;

    assign mem_to_wb_bus = {
        hl_rdata,
        hl_waddr,
        hl_we,
        mem_pc,
        rf_we,
        rf_waddr,
        rf_wdata
    };
    assign mem_to_iden=rf_we;
    assign mem_to_idregaddr=rf_waddr;
    assign mem_to_idata=rf_wdata;
    assign mem_id_hlwe=hl_we;
    assign mem_id_hlwaddr=hl_waddr;
    assign mem_id_hlwdata=hl_rdata;
    assign mem_to_id_bus={
      mem_id_hlwdata,
      mem_id_hlwaddr,
      mem_id_hlwe,
      mem_to_iden,
      mem_to_idregaddr,
      mem_to_idata
    };

endmodule