data/full_repos/permissive/513306128/ECEN248/clock_divider.v
data/verilator_xmls/9e9dff82-c08c-4116-b44b-46239213b343.xml
module clock_divider(ClkOut,ClkIn);

output wire [3:0] ClkOut;
input wire ClkIn;

parameter n = 25;
reg [n:0] Count;

always@(posedge ClkIn)
    Count <= Count +1;
assign ClkOut[3:0] = Count[n:n-3];

endmodule
module clock_divider(ClkOut,ClkIn);


output wire [3:0] ClkOut;
input wire ClkIn;

parameter n = 25;
reg [n:0] Count;

always@(posedge ClkIn)
    Count <= Count +1;
assign ClkOut[3:0] = Count[n:n-3];

endmodule