data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/rx_dcoffset_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/rx_dcoffset_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n   initial #1000 rst = 0;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/rx_dcoffset_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n   always #5 clk = ~clk;\n          ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/rx_dcoffset_tb.v:29: Unsupported or unknown PLI call: $dumpfile\n   initial $dumpfile("rx_dcoffset_tb.vcd");\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/rx_dcoffset_tb.v:30: Unsupported or unknown PLI call: $dumpvars\n   initial $dumpvars(0,rx_dcoffset_tb);\n           ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module rx_dcoffset_tb();
   
   reg clk, rst;

   initial rst = 1;
   initial #1000 rst = 0;
   initial clk = 0;
   always #5 clk = ~clk;
   
   initial $dumpfile("rx_dcoffset_tb.vcd");
   initial $dumpvars(0,rx_dcoffset_tb);

   reg [13:0] adc_in;
   wire [13:0] adc_out;

   always @(posedge clk)
     begin
	if(adc_in[13])
	  $write("-%d,",-adc_in);
	else
	  $write("%d,",adc_in);
	if(adc_out[13])
	  $write("-%d\n",-adc_out);
	else
	  $write("%d\n",adc_out);
     end	
   
   rx_dcoffset #(.WIDTH(14),.ADDR(0), .alpha_shift(8))
     rx_dcoffset(.clk(clk),.rst(rst),.set_stb(0),.set_addr(0),.set_data(0),
		 .in(adc_in),.out(adc_out));

   always @(posedge clk)
     adc_in <= (($random % 473) + 23)/4;
   
endmodule
module rx_dcoffset_tb();

   
   reg clk, rst;

   initial rst = 1;
   initial #1000 rst = 0;
   initial clk = 0;
   always #5 clk = ~clk;
   
   initial $dumpfile("rx_dcoffset_tb.vcd");
   initial $dumpvars(0,rx_dcoffset_tb);

   reg [13:0] adc_in;
   wire [13:0] adc_out;

   always @(posedge clk)
     begin
	if(adc_in[13])
	  $write("-%d,",-adc_in);
	else
	  $write("%d,",adc_in);
	if(adc_out[13])
	  $write("-%d\n",-adc_out);
	else
	  $write("%d\n",adc_out);
     end	
   
   rx_dcoffset #(.WIDTH(14),.ADDR(0), .alpha_shift(8))
     rx_dcoffset(.clk(clk),.rst(rst),.set_stb(0),.set_addr(0),.set_data(0),
		 .in(adc_in),.out(adc_out));

   always @(posedge clk)
     adc_in <= (($random % 473) + 23)/4;
   
endmodule