data/full_repos/permissive/406635962/src/tb/tb_cpu_top.v
1: b'%Error: data/full_repos/permissive/406635962/src/tb/tb_cpu_top.v:3: Cannot find include file: ../rtl/defines.v\n`include "../rtl/defines.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/406635962/src/tb,data/full_repos/permissive/406635962/../rtl/defines.v\n             data/full_repos/permissive/406635962/src/tb,data/full_repos/permissive/406635962/../rtl/defines.v.v\n             data/full_repos/permissive/406635962/src/tb,data/full_repos/permissive/406635962/../rtl/defines.v.sv\n             ../rtl/defines.v\n             ../rtl/defines.v.v\n             ../rtl/defines.v.sv\n             obj_dir/../rtl/defines.v\n             obj_dir/../rtl/defines.v.v\n             obj_dir/../rtl/defines.v.sv\n%Error: data/full_repos/permissive/406635962/src/tb/tb_cpu_top.v:10: Define or directive not defined: \'`PC_SIZE\'\n    reg[`PC_SIZE-1:0] pc_rtvec; \n        ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/tb/tb_cpu_top.v:20: Define or directive not defined: \'`PC_SIZE\'\n        pc_rtvec = `PC_SIZE\'h0000_0070;\n                   ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/406635962/src/tb/tb_cpu_top.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #30 rst_n = 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/406635962/src/tb/tb_cpu_top.v:45: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk = ~clk; \n           ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module tb_cpu_top;
    reg clk;
    reg rst_n;
    reg[`PC_SIZE-1:0] pc_rtvec; 
    
    cpu_top u_cpu_top(
    .pc_rtvec(pc_rtvec),
    .clk(clk),
    .rst_n(rst_n)
    );
    
    initial begin
        rst_n = 0;
        pc_rtvec = `PC_SIZE'h0000_0070;
        #30 rst_n = 1;


    end 
    reg[31:0] instr_in;
    integer i;
    integer test_file;
    initial begin
        test_file = $fopen("C:\\Users\\hurui\\Desktop\\test_insr\\a_debug","rb");
        for(i=0; i<16000; i=i+1) begin
            if($fread(instr_in, test_file)) begin
                $display(instr_in);
                u_cpu_top.u_srams.u_itcm_ram.u_itcm_gnrl_ram.mem_r[i] =  {instr_in[7:0],instr_in[15:8],instr_in[23:16],instr_in[31:24]};
                u_cpu_top.u_srams.u_dtcm_ram.u_dtcm_gnrl_ram.mem_r[i] =  {instr_in[7:0],instr_in[15:8],instr_in[23:16],instr_in[31:24]};
            end
            else begin
                u_cpu_top.u_srams.u_itcm_ram.u_itcm_gnrl_ram.mem_r[i] <= 32'd0;
                u_cpu_top.u_srams.u_dtcm_ram.u_dtcm_gnrl_ram.mem_r[i] <= 32'd0;
            end
        end
        $fclose(test_file);
    end
    
    initial clk = 0;
    always #5 clk = ~clk; 
endmodule
module tb_cpu_top;

    reg clk;
    reg rst_n;
    reg[`PC_SIZE-1:0] pc_rtvec; 
    
    cpu_top u_cpu_top(
    .pc_rtvec(pc_rtvec),
    .clk(clk),
    .rst_n(rst_n)
    );
    
    initial begin
        rst_n = 0;
        pc_rtvec = `PC_SIZE'h0000_0070;
        #30 rst_n = 1;


    end 
    reg[31:0] instr_in;
    integer i;
    integer test_file;
    initial begin
        test_file = $fopen("C:\\Users\\hurui\\Desktop\\test_insr\\a_debug","rb");
        for(i=0; i<16000; i=i+1) begin
            if($fread(instr_in, test_file)) begin
                $display(instr_in);
                u_cpu_top.u_srams.u_itcm_ram.u_itcm_gnrl_ram.mem_r[i] =  {instr_in[7:0],instr_in[15:8],instr_in[23:16],instr_in[31:24]};
                u_cpu_top.u_srams.u_dtcm_ram.u_dtcm_gnrl_ram.mem_r[i] =  {instr_in[7:0],instr_in[15:8],instr_in[23:16],instr_in[31:24]};
            end
            else begin
                u_cpu_top.u_srams.u_itcm_ram.u_itcm_gnrl_ram.mem_r[i] <= 32'd0;
                u_cpu_top.u_srams.u_dtcm_ram.u_dtcm_gnrl_ram.mem_r[i] <= 32'd0;
            end
        end
        $fclose(test_file);
    end
    
    initial clk = 0;
    always #5 clk = ~clk; 
endmodule