data/full_repos/permissive/524522105/async_mem/src/pulse_gen.v
data/verilator_xmls/60c05dab-b64d-4ea1-939b-dba8d03fddb7.xml
module pulse_gen ( input  clock,
                   output pulse );
  parameter CTR_WIDTH = 12;
  parameter PLS_WIDTH =  2;

  reg [CTR_WIDTH-1:0] ctr   = 0;
  reg                 spent = 0;

  assign pulse = ctr[CTR_WIDTH-1] & ~ctr[PLS_WIDTH-1] & ~spent;

  always @ (posedge clock)
  begin
    ctr <= ctr + 1'b1;

    if (ctr[PLS_WIDTH-1]) begin
      spent <= 1'b1;
    end

    if (~ctr[CTR_WIDTH-1]) begin
      spent <= 0;
    end

  end
endmodule
module pulse_gen ( input  clock,
                   output pulse );

  parameter CTR_WIDTH = 12;
  parameter PLS_WIDTH =  2;

  reg [CTR_WIDTH-1:0] ctr   = 0;
  reg                 spent = 0;

  assign pulse = ctr[CTR_WIDTH-1] & ~ctr[PLS_WIDTH-1] & ~spent;

  always @ (posedge clock)
  begin
    ctr <= ctr + 1'b1;

    if (ctr[PLS_WIDTH-1]) begin
      spent <= 1'b1;
    end

    if (~ctr[CTR_WIDTH-1]) begin
      spent <= 0;
    end

  end
endmodule