data/full_repos/permissive/441359809/test/main_test/simple_cases/decode_32_2/decode_32_2.v
data/verilator_xmls/1b070e07-c8d8-49ac-9b7a-3fd783e1c3e7.xml
module decode_32_2 (input [5-1:0] sel, input [32-1:0] din, output dout);
  wire [32-1:0] p = din << sel; assign dout = p[32-1];
endmodule
module decode_32_2 (input [5-1:0] sel, input [32-1:0] din, output dout);

  wire [32-1:0] p = din << sel; assign dout = p[32-1];
endmodule