data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/OUT_REG.v
data/verilator_xmls/801c1e68-3af7-4d47-8311-419eb1269e2c.xml
module OUT_REG #(parameter REG_DATA_WIDTH=16)(

OUT_REG_Clk,
OUT_REG_Reset,
OUT_REG_Set,
OUT_REG_Input_Data,

OUT_REG_Output_Data
);




input OUT_REG_Clk;
input OUT_REG_Reset;
input OUT_REG_Set;
input signed [REG_DATA_WIDTH-1:0] OUT_REG_Input_Data;
output signed [REG_DATA_WIDTH-1:0] OUT_REG_Output_Data;





reg signed [REG_DATA_WIDTH-1:0] Internal_Signal_Reg;
reg signed[REG_DATA_WIDTH-1:0] Internal_Data_Reg;




always@(*)
begin
	if(OUT_REG_Set)
		Internal_Signal_Reg=OUT_REG_Input_Data;
	else
		Internal_Signal_Reg=Internal_Data_Reg;
end





always@(posedge OUT_REG_Clk or negedge OUT_REG_Reset)
begin
	if(!OUT_REG_Reset)
		Internal_Data_Reg<=0;
	else
		Internal_Data_Reg<=Internal_Signal_Reg;
end




assign OUT_REG_Output_Data=Internal_Data_Reg;


endmodule
module OUT_REG #(parameter REG_DATA_WIDTH=16)(

OUT_REG_Clk,
OUT_REG_Reset,
OUT_REG_Set,
OUT_REG_Input_Data,

OUT_REG_Output_Data
);





input OUT_REG_Clk;
input OUT_REG_Reset;
input OUT_REG_Set;
input signed [REG_DATA_WIDTH-1:0] OUT_REG_Input_Data;
output signed [REG_DATA_WIDTH-1:0] OUT_REG_Output_Data;





reg signed [REG_DATA_WIDTH-1:0] Internal_Signal_Reg;
reg signed[REG_DATA_WIDTH-1:0] Internal_Data_Reg;




always@(*)
begin
	if(OUT_REG_Set)
		Internal_Signal_Reg=OUT_REG_Input_Data;
	else
		Internal_Signal_Reg=Internal_Data_Reg;
end





always@(posedge OUT_REG_Clk or negedge OUT_REG_Reset)
begin
	if(!OUT_REG_Reset)
		Internal_Data_Reg<=0;
	else
		Internal_Data_Reg<=Internal_Signal_Reg;
end




assign OUT_REG_Output_Data=Internal_Data_Reg;


endmodule