data/full_repos/permissive/524532083/verilog/vcs/decap.v
1: b"%Error: data/full_repos/permissive/524532083/verilog/vcs/decap.v:58: Can't resolve module reference: 'sky130_fd_sc_hd__decap'\n    sky130_fd_sc_hd__decap base ();\n                           ^~~~\n%Error: Exiting due to 1 error(s)\n"
module sky130_ef_sc_hd__decap_12 (
    VPWR,
    VGND,
    VPB ,
    VNB
);

    input VPWR;
    input VGND;
    input VPB ;
    input VNB ;
    sky130_fd_sc_hd__decap base (
        .VPWR(VPWR),
        .VGND(VGND),
        .VPB(VPB),
        .VNB(VNB)
    );

endmodule
module sky130_ef_sc_hd__decap_12 (
    VPWR,
    VGND,
    VPB ,
    VNB
);


    input VPWR;
    input VGND;
    input VPB ;
    input VNB ;
    sky130_fd_sc_hd__decap base (
        .VPWR(VPWR),
        .VGND(VGND),
        .VPB(VPB),
        .VNB(VNB)
    );

endmodule