data/full_repos/permissive/441359809/src/yosys/passes/sat/example.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/passes/sat/example.v:15: Multiple top level modules\n                                                                                         : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                         : ... Top module \'example001\'\nmodule example001(a, y);\n       ^~~~~~~~~~\n                                                                                         : ... Top module \'example002\'\nmodule example002(a, y);\n       ^~~~~~~~~~\n                                                                                         : ... Top module \'example003\'\nmodule example003(a_shl, a_shr, a_sshl, a_sshr, sh, y_shl, y_shr, y_sshl, y_sshr);\n       ^~~~~~~~~~\n                                                                                         : ... Top module \'example004\'\nmodule example004(clk, rst, y);\n       ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/passes/sat/example.v:30: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh4\' generates 32 or 3 bits.\n                                                                                      : ... In instance example002\n   t1 <= 4;\n      ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/passes/sat/example.v:22: Operator CASE expects 16 bits on the Case expression, but Case expression\'s VARREF \'a\' generates 4 bits.\n                                                                                      : ... In instance example002\n casex (a)\n ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/passes/sat/example.v:42: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh4\' generates 32 or 3 bits.\n                                                                                      : ... In instance example002\n   t2 <= 4;\n      ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/passes/sat/example.v:34: Operator CASE expects 16 bits on the Case expression, but Case expression\'s VARREF \'a\' generates 4 bits.\n                                                                                      : ... In instance example002\n casex (a)\n ^~~~~\n%Error: Exiting due to 5 warning(s)\n'
module example003(a_shl, a_shr, a_sshl, a_sshr, sh, y_shl, y_shr, y_sshl, y_sshr);

input [7:0] a_shl, a_shr;
input signed [7:0] a_sshl, a_sshr;
input [3:0] sh;

output [7:0] y_shl = a_shl << sh, y_shr = a_shr >> sh;
output signed [7:0] y_sshl = a_sshl <<< sh, y_sshr = a_sshr >>> sh;

endmodule
module example003(a_shl, a_shr, a_sshl, a_sshr, sh, y_shl, y_shr, y_sshl, y_sshr);


input [7:0] a_shl, a_shr;
input signed [7:0] a_sshl, a_sshr;
input [3:0] sh;

output [7:0] y_shl = a_shl << sh, y_shr = a_shr >> sh;
output signed [7:0] y_sshl = a_sshl <<< sh, y_sshr = a_sshr >>> sh;

endmodule