data/full_repos/permissive/445929378/decrypting_entity.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/445929378/decrypting_entity.v:65: Signal definition not found, creating implicitly: \'output_tvalid\'\n                                                                              : ... Suggested alternative: \'output_a_tvalid\'\n   assign output_tvalid = out_a_valid & out_b_valid & out_c_valid;\n          ^~~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/445929378/decrypting_entity.v:70: Signal definition not found, creating implicitly: \'rst_rng\'\n   assign rst_rng = reset;\n          ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/445929378/decrypting_entity.v:71: Signal definition not found, creating implicitly: \'rst_mod_exp\'\n   assign rst_mod_exp = reset;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/445929378/decrypting_entity.v:73: Cannot find file containing module: \'LFSR\'\n   LFSR private_key_generator (\n   ^~~~\n        ... Looked in:\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/LFSR\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/LFSR.v\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/LFSR.sv\n             LFSR\n             LFSR.v\n             LFSR.sv\n             obj_dir/LFSR\n             obj_dir/LFSR.v\n             obj_dir/LFSR.sv\n%Error: data/full_repos/permissive/445929378/decrypting_entity.v:82: Cannot find file containing module: \'mod_exp\'\n   mod_exp public_key_generator(\n   ^~~~~~~\n%Error: data/full_repos/permissive/445929378/decrypting_entity.v:99: Cannot find file containing module: \'mult_inverse\'\n   mult_inverse decrypt(\n   ^~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 3 warning(s)\n'
module decrypting_entity #(parameter SIZE = 64)
   (
    input wire 		     clk, rst, switch,

    wire [SIZE-1 : 0] 	     input_first_tdata,
    input wire 		     input_first_tvalid,
    output wire 	     input_first_tready,
   
    input wire [SIZE-1 : 0]  input_second_tdata,
    input wire 		     input_second_tvalid, 
    output wire 	     input_second_tready,

    output wire [SIZE-1 : 0] output_a_tdata,
    output wire 	     output_a_tvalid, 
    input wire 		     output_a_tready,
   
    output wire [SIZE-1 : 0] output_b_tdata,
    output wire 	     output_b_tvalid, 
    input wire 		     output_b_tready,

    output wire [SIZE-1 : 0] output_c_tdata,
    output wire 	     output_c_tvalid, 
    input wire 		     output_c_tready
    );
   
   reg [SIZE-1 : 0] 	     first;
   reg [SIZE-1 : 0] 	     second;

   reg [SIZE-1 : 0] 	     p;
   reg [SIZE-1 : 0] 	     private_key;
   wire [SIZE-1 : 0] 	     private_key_wire;
   wire 		     private_key_ready;
   
   reg [SIZE-1 : 0] 	     public_key;
   wire [SIZE-1 : 0] 	     public_key_wire;
   wire 		     public_key_ready;

   reg [SIZE-1 : 0] 	     output_a_reg;
   reg [SIZE-1 : 0] 	     output_b_reg;
   reg [SIZE-1 : 0] 	     output_c_reg;

   reg [SIZE-1 : 0] 	     inverse;
   wire [SIZE-1 : 0] 	     inverse_wire;
   wire 		     inverse_tvalid;
   
   reg 			     out_a_valid, out_b_valid, out_c_valid;
   reg 			     state = 0;


   reg 			     generate_private_key = 0;
   wire 		     seed_ready = generate_private_key;

   reg 			     generate_public_key = 0;
   wire 		     run_public_key = generate_public_key;
   
   reg 			     data_read = 0;
   wire 		     input_read;
   wire 		     input_rdy = input_first_tvalid & input_second_tvalid;

   reg 			     reset;
   
   assign input_read = data_read;
   assign output_tvalid = out_a_valid & out_b_valid & out_c_valid;
   assign output_a_tdata = output_a_reg;
   assign output_b_tdata = output_b_reg;
   assign output_c_tdata = output_c_reg;

   assign rst_rng = reset;
   assign rst_mod_exp = reset;

   LFSR private_key_generator (
			       .clk(clk), 
			       .rst(rst_rng),
			       .input_tvalid(seed_ready),
			       .seed(first),
			       .output_tvalid(private_key_ready),
			       .rnd(private_key_wire)
			       );
   
   mod_exp public_key_generator(
				.clk(clk), 
				.rst(rst_mod_exp), 
				.input_base_tdata(second),
				.input_base_tvalid(input_read), 

				.input_power_tdata(private_key), 
				.input_power_tvalid(run_public_key), 

				.input_modulus_tdata(first), 
				.input_modulus_tvalid(input_read), 

				.output_tdata(public_key_wire), 
				.output_tvalid(public_key_ready), 
				.output_tready(input_read)
				);

   mult_inverse decrypt(
			.clk(clk), 
			.rst(rst), 
			.input_base_tdata(first), 
			.input_base_tvalid(input_read), 
			.input_modulus_tdata(p), 
			.input_modulus_tvalid(input_read), 
			.output_tdata(inverse), 
			.output_tvalid(inverse_tvalid), 
			.output_tready(input_ready)
			);
   
   always @(posedge clk)
     begin
	if(rst) begin
	   first <= 0;
	   second <= 0;

	   data_read <= 0;
	   out_a_valid <= 0;
	   out_b_valid <= 0;
	   out_c_valid <= 0;
	end else begin
	   if(!state) begin

	      if(!input_read) begin
		 first <= input_first_tdata;
		 second <= input_second_tdata;
		 if(input_rdy) begin 
		    data_read <= 1;
		    generate_private_key <= 1;
		 end
	      end else begin
		 if(private_key_ready) begin
		    private_key <= private_key_wire;
		    generate_private_key <= 0;
		    p <= first;
		    if(private_key < (first + 1)) begin
		       generate_public_key <= 1;

		    end
		 end
		 if(public_key_ready) begin
		    generate_public_key <= 0;
		    output_a_reg <= first;
		    output_b_reg <= second;
		    output_c_reg <= public_key_wire;
		    public_key <= public_key_wire;
		    state <= 1;
		    reset <= 1;
		 end
	      end
	   end else begin
	      if(switch) begin
		 $display("xd");
		 
	      end

	   end
	end
	if(reset) reset <= 0;
	
     end
endmodule
module decrypting_entity #(parameter SIZE = 64)
   (
    input wire 		     clk, rst, switch,

    wire [SIZE-1 : 0] 	     input_first_tdata,
    input wire 		     input_first_tvalid,
    output wire 	     input_first_tready,
   
    input wire [SIZE-1 : 0]  input_second_tdata,
    input wire 		     input_second_tvalid, 
    output wire 	     input_second_tready,

    output wire [SIZE-1 : 0] output_a_tdata,
    output wire 	     output_a_tvalid, 
    input wire 		     output_a_tready,
   
    output wire [SIZE-1 : 0] output_b_tdata,
    output wire 	     output_b_tvalid, 
    input wire 		     output_b_tready,

    output wire [SIZE-1 : 0] output_c_tdata,
    output wire 	     output_c_tvalid, 
    input wire 		     output_c_tready
    );

   
   reg [SIZE-1 : 0] 	     first;
   reg [SIZE-1 : 0] 	     second;

   reg [SIZE-1 : 0] 	     p;
   reg [SIZE-1 : 0] 	     private_key;
   wire [SIZE-1 : 0] 	     private_key_wire;
   wire 		     private_key_ready;
   
   reg [SIZE-1 : 0] 	     public_key;
   wire [SIZE-1 : 0] 	     public_key_wire;
   wire 		     public_key_ready;

   reg [SIZE-1 : 0] 	     output_a_reg;
   reg [SIZE-1 : 0] 	     output_b_reg;
   reg [SIZE-1 : 0] 	     output_c_reg;

   reg [SIZE-1 : 0] 	     inverse;
   wire [SIZE-1 : 0] 	     inverse_wire;
   wire 		     inverse_tvalid;
   
   reg 			     out_a_valid, out_b_valid, out_c_valid;
   reg 			     state = 0;


   reg 			     generate_private_key = 0;
   wire 		     seed_ready = generate_private_key;

   reg 			     generate_public_key = 0;
   wire 		     run_public_key = generate_public_key;
   
   reg 			     data_read = 0;
   wire 		     input_read;
   wire 		     input_rdy = input_first_tvalid & input_second_tvalid;

   reg 			     reset;
   
   assign input_read = data_read;
   assign output_tvalid = out_a_valid & out_b_valid & out_c_valid;
   assign output_a_tdata = output_a_reg;
   assign output_b_tdata = output_b_reg;
   assign output_c_tdata = output_c_reg;

   assign rst_rng = reset;
   assign rst_mod_exp = reset;

   LFSR private_key_generator (
			       .clk(clk), 
			       .rst(rst_rng),
			       .input_tvalid(seed_ready),
			       .seed(first),
			       .output_tvalid(private_key_ready),
			       .rnd(private_key_wire)
			       );
   
   mod_exp public_key_generator(
				.clk(clk), 
				.rst(rst_mod_exp), 
				.input_base_tdata(second),
				.input_base_tvalid(input_read), 

				.input_power_tdata(private_key), 
				.input_power_tvalid(run_public_key), 

				.input_modulus_tdata(first), 
				.input_modulus_tvalid(input_read), 

				.output_tdata(public_key_wire), 
				.output_tvalid(public_key_ready), 
				.output_tready(input_read)
				);

   mult_inverse decrypt(
			.clk(clk), 
			.rst(rst), 
			.input_base_tdata(first), 
			.input_base_tvalid(input_read), 
			.input_modulus_tdata(p), 
			.input_modulus_tvalid(input_read), 
			.output_tdata(inverse), 
			.output_tvalid(inverse_tvalid), 
			.output_tready(input_ready)
			);
   
   always @(posedge clk)
     begin
	if(rst) begin
	   first <= 0;
	   second <= 0;

	   data_read <= 0;
	   out_a_valid <= 0;
	   out_b_valid <= 0;
	   out_c_valid <= 0;
	end else begin
	   if(!state) begin

	      if(!input_read) begin
		 first <= input_first_tdata;
		 second <= input_second_tdata;
		 if(input_rdy) begin 
		    data_read <= 1;
		    generate_private_key <= 1;
		 end
	      end else begin
		 if(private_key_ready) begin
		    private_key <= private_key_wire;
		    generate_private_key <= 0;
		    p <= first;
		    if(private_key < (first + 1)) begin
		       generate_public_key <= 1;

		    end
		 end
		 if(public_key_ready) begin
		    generate_public_key <= 0;
		    output_a_reg <= first;
		    output_b_reg <= second;
		    output_c_reg <= public_key_wire;
		    public_key <= public_key_wire;
		    state <= 1;
		    reset <= 1;
		 end
	      end
	   end else begin
	      if(switch) begin
		 $display("xd");
		 
	      end

	   end
	end
	if(reset) reset <= 0;
	
     end
endmodule