data/full_repos/permissive/417268106/src/hrd/led_driver.v
1: b'%Warning-WIDTH: data/full_repos/permissive/417268106/src/hrd/led_driver.v:36: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                            : ... In instance led_driver\nassign oLED = int2_count[23] ? ((abs_select_high[3:0] == 3\'h0) ? 10\'h030 :\n                                                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/417268106/src/hrd/led_driver.v:37: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                            : ... In instance led_driver\n                            (abs_select_high[3:0] == 3\'h1) ? (signed_bit?10\'h010:10\'h020) :\n                                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/417268106/src/hrd/led_driver.v:38: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'3\'h2\' generates 3 bits.\n                                                                            : ... In instance led_driver\n                            (abs_select_high[3:0] == 3\'h2) ? (signed_bit?10\'h018:10\'h060) :\n                                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/417268106/src/hrd/led_driver.v:39: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'3\'h3\' generates 3 bits.\n                                                                            : ... In instance led_driver\n                            (abs_select_high[3:0] == 3\'h3) ? (signed_bit?10\'h8:10\'h040) :\n                                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/417268106/src/hrd/led_driver.v:40: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                                            : ... In instance led_driver\n                            (abs_select_high[3:0] == 3\'h4) ? (signed_bit?10\'hc:10\'h0c0) :\n                                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/417268106/src/hrd/led_driver.v:41: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'3\'h5\' generates 3 bits.\n                                                                            : ... In instance led_driver\n                            (abs_select_high[3:0] == 3\'h5) ? (signed_bit?10\'h4:10\'h080) :\n                                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/417268106/src/hrd/led_driver.v:42: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'3\'h6\' generates 3 bits.\n                                                                            : ... In instance led_driver\n                            (abs_select_high[3:0] == 3\'h6) ? (signed_bit?10\'h6:10\'h180) :\n                                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/417268106/src/hrd/led_driver.v:43: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'3\'h7\' generates 3 bits.\n                                                                            : ... In instance led_driver\n                            (abs_select_high[3:0] == 3\'h7) ? (signed_bit?10\'h2:10\'h100) :\n                                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/417268106/src/hrd/led_driver.v:44: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                            : ... In instance led_driver\n                            (abs_select_high[3:0] == 3\'h8) ? (signed_bit?10\'h3:10\'h300) :\n                                                  ^~\n%Error: Exiting due to 9 warning(s)\n'
module led_driver (iRSTN, iCLK, iDIG, iG_INT2, oLED);
input				       iRSTN;
input				       iCLK;
input		    [9:0]  iDIG;
input		           iG_INT2;
output	    [9:0]  oLED;




wire				[4:0]  select_data;
wire               signed_bit;
wire				[3:0]  abs_select_high;
reg				  [1:0]  int2_d;
reg	        [23:0] int2_count;
reg	               int2_count_en;




assign select_data = iG_INT2 ? iDIG[9:5] :
                               (iDIG[9]?(iDIG[8]?iDIG[8:4]:5'h10):(iDIG[8]?5'hf:iDIG[8:4]));
assign signed_bit = select_data[4];
assign abs_select_high = signed_bit ? ~select_data[3:0] : select_data[3:0];


												
assign oLED = int2_count[23] ? ((abs_select_high[3:0] == 3'h0) ? 10'h030 :
				                        (abs_select_high[3:0] == 3'h1) ? (signed_bit?10'h010:10'h020) :
				                        (abs_select_high[3:0] == 3'h2) ? (signed_bit?10'h018:10'h060) :
				                        (abs_select_high[3:0] == 3'h3) ? (signed_bit?10'h8:10'h040) :
				                        (abs_select_high[3:0] == 3'h4) ? (signed_bit?10'hc:10'h0c0) :
				                        (abs_select_high[3:0] == 3'h5) ? (signed_bit?10'h4:10'h080) :
				                        (abs_select_high[3:0] == 3'h6) ? (signed_bit?10'h6:10'h180) :
				                        (abs_select_high[3:0] == 3'h7) ? (signed_bit?10'h2:10'h100) :
				                        (abs_select_high[3:0] == 3'h8) ? (signed_bit?10'h3:10'h300) :
				                                                         (signed_bit?10'h1:10'h200)):
				                        (int2_count[20] ? 10'h0 : 10'h3ff);
												
												
												

always@(posedge iCLK or negedge iRSTN)
	if (!iRSTN)
  begin
    int2_count_en	<= 1'b0;	
    int2_count <= 24'h800000;
  end
	else
	begin
		int2_d <= {int2_d[0], iG_INT2};

		if (!int2_d[1] && int2_d[0])
    begin
      int2_count_en	<= 1'b1;		
	    int2_count <= 24'h0;
	  end
	  else if (int2_count[23])
	  	int2_count_en	<= 1'b0; 	
    else
	  	int2_count <= int2_count + 1;
	end

endmodule
module led_driver (iRSTN, iCLK, iDIG, iG_INT2, oLED);

input				       iRSTN;
input				       iCLK;
input		    [9:0]  iDIG;
input		           iG_INT2;
output	    [9:0]  oLED;




wire				[4:0]  select_data;
wire               signed_bit;
wire				[3:0]  abs_select_high;
reg				  [1:0]  int2_d;
reg	        [23:0] int2_count;
reg	               int2_count_en;




assign select_data = iG_INT2 ? iDIG[9:5] :
                               (iDIG[9]?(iDIG[8]?iDIG[8:4]:5'h10):(iDIG[8]?5'hf:iDIG[8:4]));
assign signed_bit = select_data[4];
assign abs_select_high = signed_bit ? ~select_data[3:0] : select_data[3:0];


												
assign oLED = int2_count[23] ? ((abs_select_high[3:0] == 3'h0) ? 10'h030 :
				                        (abs_select_high[3:0] == 3'h1) ? (signed_bit?10'h010:10'h020) :
				                        (abs_select_high[3:0] == 3'h2) ? (signed_bit?10'h018:10'h060) :
				                        (abs_select_high[3:0] == 3'h3) ? (signed_bit?10'h8:10'h040) :
				                        (abs_select_high[3:0] == 3'h4) ? (signed_bit?10'hc:10'h0c0) :
				                        (abs_select_high[3:0] == 3'h5) ? (signed_bit?10'h4:10'h080) :
				                        (abs_select_high[3:0] == 3'h6) ? (signed_bit?10'h6:10'h180) :
				                        (abs_select_high[3:0] == 3'h7) ? (signed_bit?10'h2:10'h100) :
				                        (abs_select_high[3:0] == 3'h8) ? (signed_bit?10'h3:10'h300) :
				                                                         (signed_bit?10'h1:10'h200)):
				                        (int2_count[20] ? 10'h0 : 10'h3ff);
												
												
												

always@(posedge iCLK or negedge iRSTN)
	if (!iRSTN)
  begin
    int2_count_en	<= 1'b0;	
    int2_count <= 24'h800000;
  end
	else
	begin
		int2_d <= {int2_d[0], iG_INT2};

		if (!int2_d[1] && int2_d[0])
    begin
      int2_count_en	<= 1'b1;		
	    int2_count <= 24'h0;
	  end
	  else if (int2_count[23])
	  	int2_count_en	<= 1'b0; 	
    else
	  	int2_count <= int2_count + 1;
	end

endmodule