data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Saber_blocks/pol_mul256_parallel_in.v
1: b'%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Saber_blocks/pol_mul256_parallel_in.v:49: Cannot find file containing module: \'poly_load_control_BRAM\'\npoly_load_control_BRAM PLC(clk, rst_poly_load, pol_load_coeff4x, bram_address_relative, poly_load, poly_load_done);\n^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Saber_blocks,data/full_repos/permissive/428190211/poly_load_control_BRAM\n             data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Saber_blocks,data/full_repos/permissive/428190211/poly_load_control_BRAM.v\n             data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Saber_blocks,data/full_repos/permissive/428190211/poly_load_control_BRAM.sv\n             poly_load_control_BRAM\n             poly_load_control_BRAM.v\n             poly_load_control_BRAM.sv\n             obj_dir/poly_load_control_BRAM\n             obj_dir/poly_load_control_BRAM.v\n             obj_dir/poly_load_control_BRAM.sv\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Saber_blocks/pol_mul256_parallel_in.v:56: Cannot find file containing module: \'parallel_Mults\'\nparallel_Mults PMULTs(acc, pol, s, s_sign, result);\n^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Saber_blocks/pol_mul256_parallel_in.v:118: Operator EQ expects 9 bits on the LHS, but LHS\'s VARREF \'state\' generates 3 bits.\n                                                                                                                          : ... In instance poly_mul256_parallel_in\n else if(state==9\'d1)\n              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module poly_mul256_parallel_in(clk, rst, acc_clear, pol_load_coeff4x,
								bram_address_relative, pol_64bit_in,  
								s_address, s, s_sign, 
								read, coeff4x_out, 
								read64, polmul_result64_out, pol_mul_done);
								
input clk, rst;
input pol_load_coeff4x;
input acc_clear;
output [5:0] bram_address_relative;
input [63:0] pol_64bit_in;								
output reg [7:0] s_address;
input [2:0] s;
input s_sign;
input read, read64;

output [63:0] coeff4x_out;
output [63:0] polmul_result64_out;
output pol_mul_done;

reg rst_poly_load;
wire poly_load, poly_load_done;

reg shift_pol, acc_en, s_address_inc;
reg [2:0] state, nextstate;
reg [8:0] counter;
wire counter_finish;

poly_load_control_BRAM PLC(clk, rst_poly_load, pol_load_coeff4x, bram_address_relative, poly_load, poly_load_done);


reg [3327:0]pol;
reg [3327:0] acc;
wire [3327:0] result;

parallel_Mults PMULTs(acc, pol, s, s_sign, result);

always @(posedge clk)
begin
	if(pol_load_coeff4x==1'b1 && poly_load==1'b1)
		pol <= {3'd0,pol_64bit_in[57:48],3'd0,pol_64bit_in[41:32],3'd0,pol_64bit_in[25:16],3'd0,pol_64bit_in[9:0],pol[3327:52]};
	else if(poly_load)
		pol <= {pol_64bit_in, pol[3327:64]};
	else if(shift_pol)
	begin
		pol <= {pol[3314:0],-pol[3327:3315]};
	end
end


always @(posedge clk)
begin
	if(acc_clear)
	begin
		acc <= 3328'd0;
	end
	else if(acc_en)	
	begin
		acc <= result;
	end
	else if(read)
	begin
		acc <= {acc[51:0],acc[3327:52]};
	end
	else if(read64)
	begin
		acc <= {acc[63:0],acc[3327:64]};
	end
end	

assign coeff4x_out = {3'd0,acc[51:39],3'd0,acc[38:26],3'd0,acc[25:13],3'd0,acc[12:0]};
assign polmul_result64_out = acc[63:0];

always @(posedge clk)
begin
	if(rst)
		s_address <= 8'd0;
	else if(s_address_inc)
		s_address <= s_address + 1'b1;
	else
		s_address <= s_address;
end
		
		

always @(posedge clk)
begin
	if(rst)
		state <= 3'd0;
	else 
		state <= nextstate;
end

always @(posedge clk)
begin
	if(rst)
		counter <= 9'd0;
	else if(state==9'd1)
		counter <= counter + 1'b1;
	else
		counter <= counter;
end

assign counter_finish = (counter == 9'd255) ? 1'b1 : 1'b0;		

always @(state)
begin
	case(state)
	3'd0: begin
				shift_pol<=1'b0; acc_en<=1'b0; s_address_inc<=1'b0; rst_poly_load<=1'b1;
			end
	3'd4: begin
				shift_pol<=1'b0; acc_en<=1'b0; s_address_inc<=1'b0; rst_poly_load<=1'b0;
			end
	3'd3: begin
				shift_pol<=1'b0; acc_en<=1'b0; s_address_inc<=1'b1; rst_poly_load<=1'b1; 
			end			
	3'd1: begin
				shift_pol<=1'b1; acc_en<=1'b1; s_address_inc<=1'b1; rst_poly_load<=1'b1;
			end
	3'd2: begin
				shift_pol<=1'b0; acc_en<=1'b0; s_address_inc<=1'b0; rst_poly_load<=1'b1;
			end			
	default: begin
				shift_pol<=1'b0; acc_en<=1'b0; s_address_inc<=1'b0; rst_poly_load<=1'b1;
			end			
	endcase
end	

always @(state or counter_finish or poly_load_done)
begin
	case(state)
	3'd0: nextstate <= 3'd4;
	3'd4: begin
				if(poly_load_done)
					nextstate <= 3'd3;
				else
					nextstate <= 3'd4;
			end
	3'd3: nextstate <= 3'd1;
	3'd1: begin
				if(counter_finish)
					nextstate <= 3'd2;
				else
					nextstate <= 3'd1;
			end
	3'd2: nextstate <= 3'd2;
	default: nextstate <= 3'd0;
	endcase
end

wire pol_mul_done = (state==3'd2) ? 1'b1 : 1'b0;
	
endmodule
module poly_mul256_parallel_in(clk, rst, acc_clear, pol_load_coeff4x,
								bram_address_relative, pol_64bit_in,  
								s_address, s, s_sign, 
								read, coeff4x_out, 
								read64, polmul_result64_out, pol_mul_done);

								
input clk, rst;
input pol_load_coeff4x;
input acc_clear;
output [5:0] bram_address_relative;
input [63:0] pol_64bit_in;								
output reg [7:0] s_address;
input [2:0] s;
input s_sign;
input read, read64;

output [63:0] coeff4x_out;
output [63:0] polmul_result64_out;
output pol_mul_done;

reg rst_poly_load;
wire poly_load, poly_load_done;

reg shift_pol, acc_en, s_address_inc;
reg [2:0] state, nextstate;
reg [8:0] counter;
wire counter_finish;

poly_load_control_BRAM PLC(clk, rst_poly_load, pol_load_coeff4x, bram_address_relative, poly_load, poly_load_done);


reg [3327:0]pol;
reg [3327:0] acc;
wire [3327:0] result;

parallel_Mults PMULTs(acc, pol, s, s_sign, result);

always @(posedge clk)
begin
	if(pol_load_coeff4x==1'b1 && poly_load==1'b1)
		pol <= {3'd0,pol_64bit_in[57:48],3'd0,pol_64bit_in[41:32],3'd0,pol_64bit_in[25:16],3'd0,pol_64bit_in[9:0],pol[3327:52]};
	else if(poly_load)
		pol <= {pol_64bit_in, pol[3327:64]};
	else if(shift_pol)
	begin
		pol <= {pol[3314:0],-pol[3327:3315]};
	end
end


always @(posedge clk)
begin
	if(acc_clear)
	begin
		acc <= 3328'd0;
	end
	else if(acc_en)	
	begin
		acc <= result;
	end
	else if(read)
	begin
		acc <= {acc[51:0],acc[3327:52]};
	end
	else if(read64)
	begin
		acc <= {acc[63:0],acc[3327:64]};
	end
end	

assign coeff4x_out = {3'd0,acc[51:39],3'd0,acc[38:26],3'd0,acc[25:13],3'd0,acc[12:0]};
assign polmul_result64_out = acc[63:0];

always @(posedge clk)
begin
	if(rst)
		s_address <= 8'd0;
	else if(s_address_inc)
		s_address <= s_address + 1'b1;
	else
		s_address <= s_address;
end
		
		

always @(posedge clk)
begin
	if(rst)
		state <= 3'd0;
	else 
		state <= nextstate;
end

always @(posedge clk)
begin
	if(rst)
		counter <= 9'd0;
	else if(state==9'd1)
		counter <= counter + 1'b1;
	else
		counter <= counter;
end

assign counter_finish = (counter == 9'd255) ? 1'b1 : 1'b0;		

always @(state)
begin
	case(state)
	3'd0: begin
				shift_pol<=1'b0; acc_en<=1'b0; s_address_inc<=1'b0; rst_poly_load<=1'b1;
			end
	3'd4: begin
				shift_pol<=1'b0; acc_en<=1'b0; s_address_inc<=1'b0; rst_poly_load<=1'b0;
			end
	3'd3: begin
				shift_pol<=1'b0; acc_en<=1'b0; s_address_inc<=1'b1; rst_poly_load<=1'b1; 
			end			
	3'd1: begin
				shift_pol<=1'b1; acc_en<=1'b1; s_address_inc<=1'b1; rst_poly_load<=1'b1;
			end
	3'd2: begin
				shift_pol<=1'b0; acc_en<=1'b0; s_address_inc<=1'b0; rst_poly_load<=1'b1;
			end			
	default: begin
				shift_pol<=1'b0; acc_en<=1'b0; s_address_inc<=1'b0; rst_poly_load<=1'b1;
			end			
	endcase
end	

always @(state or counter_finish or poly_load_done)
begin
	case(state)
	3'd0: nextstate <= 3'd4;
	3'd4: begin
				if(poly_load_done)
					nextstate <= 3'd3;
				else
					nextstate <= 3'd4;
			end
	3'd3: nextstate <= 3'd1;
	3'd1: begin
				if(counter_finish)
					nextstate <= 3'd2;
				else
					nextstate <= 3'd1;
			end
	3'd2: nextstate <= 3'd2;
	default: nextstate <= 3'd0;
	endcase
end

wire pol_mul_done = (state==3'd2) ? 1'b1 : 1'b0;
	
endmodule