data/full_repos/permissive/440170309/src/frame_gen.v
1: b"%Error: data/full_repos/permissive/440170309/src/frame_gen.v:43: Cannot find file containing module: 'decoder6x64'\n    decoder6x64 decoder6x64(scan_row, mask);\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/440170309/src,data/full_repos/permissive/440170309/decoder6x64\n             data/full_repos/permissive/440170309/src,data/full_repos/permissive/440170309/decoder6x64.v\n             data/full_repos/permissive/440170309/src,data/full_repos/permissive/440170309/decoder6x64.sv\n             decoder6x64\n             decoder6x64.v\n             decoder6x64.sv\n             obj_dir/decoder6x64\n             obj_dir/decoder6x64.v\n             obj_dir/decoder6x64.sv\n%Error: Exiting due to 1 error(s)\n"
module frame_gen #(parameter FRAME_GEN_CLK_DIV=23)(
    input wire clk,
    input wire rst,
    input wire en,
    input wire [3: 0] display_speed,

    output wire [8*64-1: 0] frame_cube_flat,

    output wire frame_valid
);


    reg [3: 0] speed_cnt;
    wire speed_ctrl;
    assign speed_ctrl = (speed_cnt == display_speed);
    always @(posedge clk) begin
        speed_cnt <= rst | ~en | speed_ctrl? 0 : speed_cnt + 1;
    end



    reg [FRAME_GEN_CLK_DIV-1:0] cnt;
    always @(posedge clk) begin
        cnt <= rst | ~en? 0 :
               speed_ctrl ? cnt + 1 : cnt;
    end

    assign frame_valid = en & (cnt == 0) & (speed_cnt==0);


    reg [5: 0] scan_row;
    always @(posedge clk) begin
        if(rst) begin
            scan_row <= 0;
        end else begin
            if(frame_valid) begin
                scan_row <= scan_row + 1;
            end
        end
    end

    wire [63: 0] mask;
    decoder6x64 decoder6x64(scan_row, mask);

    wire [7:0] frame_cube [63:0];
    genvar i;
    generate
        for (i = 0; i < 64; i = i + 1)
        begin
            assign frame_cube[i] = 8'hff & {8{mask[i]}};
        end
    endgenerate

    generate
        for(i = 0; i < 64; i = i + 1)
        begin : gen_frame
            assign frame_cube_flat[(i<<3) + 7 -: 8] = frame_cube[i];
        end
    endgenerate
endmodule
module frame_gen #(parameter FRAME_GEN_CLK_DIV=23)(
    input wire clk,
    input wire rst,
    input wire en,
    input wire [3: 0] display_speed,

    output wire [8*64-1: 0] frame_cube_flat,

    output wire frame_valid
);



    reg [3: 0] speed_cnt;
    wire speed_ctrl;
    assign speed_ctrl = (speed_cnt == display_speed);
    always @(posedge clk) begin
        speed_cnt <= rst | ~en | speed_ctrl? 0 : speed_cnt + 1;
    end



    reg [FRAME_GEN_CLK_DIV-1:0] cnt;
    always @(posedge clk) begin
        cnt <= rst | ~en? 0 :
               speed_ctrl ? cnt + 1 : cnt;
    end

    assign frame_valid = en & (cnt == 0) & (speed_cnt==0);


    reg [5: 0] scan_row;
    always @(posedge clk) begin
        if(rst) begin
            scan_row <= 0;
        end else begin
            if(frame_valid) begin
                scan_row <= scan_row + 1;
            end
        end
    end

    wire [63: 0] mask;
    decoder6x64 decoder6x64(scan_row, mask);

    wire [7:0] frame_cube [63:0];
    genvar i;
    generate
        for (i = 0; i < 64; i = i + 1)
        begin
            assign frame_cube[i] = 8'hff & {8{mask[i]}};
        end
    endgenerate

    generate
        for(i = 0; i < 64; i = i + 1)
        begin : gen_frame
            assign frame_cube_flat[(i<<3) + 7 -: 8] = frame_cube[i];
        end
    endgenerate
endmodule