data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_alu.v
1: b'%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_alu.v:36: Cannot find include file: pacoblaze_inc.v\n`include "pacoblaze_inc.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze,data/full_repos/permissive/487568919/pacoblaze_inc.v\n             data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze,data/full_repos/permissive/487568919/pacoblaze_inc.v.v\n             data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze,data/full_repos/permissive/487568919/pacoblaze_inc.v.sv\n             pacoblaze_inc.v\n             pacoblaze_inc.v.v\n             pacoblaze_inc.v.sv\n             obj_dir/pacoblaze_inc.v\n             obj_dir/pacoblaze_inc.v.v\n             obj_dir/pacoblaze_inc.v.sv\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_alu.v:46: Define or directive not defined: \'`PACOBLAZE_ALU\'\n                                                                                                     : ... Suggested alternative: \'`PACOBLAZE_ALU_V_\'\nmodule `PACOBLAZE_ALU(\n       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_alu.v:47: syntax error, unexpected \'(\', expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\n operation,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_alu.v:58: Define or directive not defined: \'`operation_width\'\n                                                                                                     : ... Suggested alternative: \'`operation_is\'\ninput [`operation_width-1:0] operation;  \n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_alu.v:62: Define or directive not defined: \'`operand_width\'\noutput reg [`operand_width-1:0] result;  \n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_alu.v:63: syntax error, unexpected input\ninput [`operand_width-1:0] operand_a, operand_b;  \n^~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_alu.v:63: Define or directive not defined: \'`operand_width\'\ninput [`operand_width-1:0] operand_a, operand_b;  \n       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_alu.v:79: Define or directive not defined: \'`operand_width\'\nwire [`operand_width-1:0] addsub_b =\n      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_alu.v:80: Define or directive not defined: \'`op_sub\'\n ((operation == (`op_sub))\n                 ^~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_alu.v:80: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n ((operation == (`op_sub))\n                        ^\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_alu.v:81: Define or directive not defined: \'`op_subcy\'\n || (operation == (`op_subcy))\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_alu.v:96: Define or directive not defined: \'`op_addcy\'\n ((operation == (`op_addcy))\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_alu.v:96: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n ((operation == (`op_addcy))\n                          ^\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_alu.v:101: Define or directive not defined: \'`op_sub\'\n ((operation == (`op_sub))\n                 ^~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_alu.v:109: Define or directive not defined: \'`op_subcy\'\n ((operation == (`op_subcy))\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_alu.v:117: Define or directive not defined: \'`operand_width\'\nwire [1+`operand_width-1:0] addsub_result = operand_a + addsub_b + addsub_carry;\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_alu.v:126: Define or directive not defined: \'`opcode_rr\'\n (shift_operation == `opcode_rr) ? operand_a[0] :  \n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_alu.v:126: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n (shift_operation == `opcode_rr) ? operand_a[0] :  \n                               ^\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_alu.v:127: Define or directive not defined: \'`opcode_rl\'\n (shift_operation == `opcode_rl) ? operand_a[7] :  \n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_alu.v:128: Define or directive not defined: \'`opcode_rsa\'\n (shift_operation == `opcode_rsa) ? carry_in :\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_alu.v:183: Define or directive not defined: \'`op_add\'\n  (`op_add),\n   ^~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_alu.v:184: Define or directive not defined: \'`op_addcy\'\n  (`op_addcy):\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_alu.v:190: Define or directive not defined: \'`op_sub\'\n  (`op_sub),\n   ^~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_alu.v:191: Define or directive not defined: \'`op_subcy\'\n  (`op_subcy): begin\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_alu.v:195: Define or directive not defined: \'`op_and\'\n  (`op_and):\n   ^~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_alu.v:198: Define or directive not defined: \'`op_or\'\n  (`op_or):\n   ^~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_alu.v:206: Define or directive not defined: \'`op_xor\'\n  (`op_xor):\n   ^~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_alu.v:209: Define or directive not defined: \'`op_rs\'\n  (`op_rs):\n   ^~~~~~\n%Error: Exiting due to 28 error(s)\n'
module `PACOBLAZE_ALU(
	operation,
	shift_operation, shift_direction, shift_constant,
	result, operand_a, operand_b,
`ifdef HAS_WIDE_ALU
	resultw, operand_u, operand_v,
`endif
	carry_in, zero_out, carry_out
`ifdef HAS_DEBUG
	, debug
`endif
);
input [`operation_width-1:0] operation;
input [2:0] shift_operation;
input shift_direction;
input shift_constant;
output reg [`operand_width-1:0] result;
input [`operand_width-1:0] operand_a, operand_b;
`ifdef HAS_WIDE_ALU
output reg [`operand_width-1:0] resultw;
input [`operand_width-1:0] operand_u, operand_v;
`endif
input carry_in;
output zero_out;
output reg carry_out;

`ifdef HAS_DEBUG
output reg [8*`alu_debug_width:1] debug;
reg [18*8:1] debug_rabc;
reg [7*8:1] debug_cz;
`endif


wire [`operand_width-1:0] addsub_b =
	(`operation_is(`op_sub)
	|| `operation_is(`op_subcy)
`ifdef HAS_COMPARE_OPERATION
	|| `operation_is(`op_compare)
`endif
	) ? ~operand_b :
	operand_b;

`ifdef HAS_WIDE_ALU
wire [2*`operand_width-1:0] addsubw_b =
	(`operation_is(`op_subw) || `operation_is(`op_subwcy)) ? ~{operand_v, operand_b} :
	{operand_v, operand_b};
`endif


wire addsub_carry =
	(`operation_is(`op_addcy)
`ifdef HAS_WIDE_ALU
	|| `operation_is(`op_addwcy)
`endif
	) ? carry_in :
	(`operation_is(`op_sub)
`ifdef HAS_COMPARE_OPERATION
	|| `operation_is(`op_compare)
`endif
`ifdef HAS_WIDE_ALU
	|| `operation_is(`op_subw)
`endif
	) ? 1 :
	(`operation_is(`op_subcy)
`ifdef HAS_WIDE_ALU
	|| `operation_is(`op_subwcy)
`endif
	) ? ~carry_in :
	0;


wire [1+`operand_width-1:0] addsub_result = operand_a + addsub_b + addsub_carry;
`ifdef HAS_WIDE_ALU
wire [1+2*`operand_width-1:0] addsubw_result =
	{operand_u, operand_a} + addsubw_b + addsub_carry;
`endif



wire shift_bit =
	(shift_operation == `opcode_rr) ? operand_a[0] :
	(shift_operation == `opcode_rl) ? operand_a[7] :
	(shift_operation == `opcode_rsa) ? carry_in :
	shift_constant;

`ifdef HAS_WIDE_ALU
wire [2*`operand_width-1:0] resultx = {resultw, result};
`endif

assign zero_out =
`ifdef HAS_MUL_OPERATION
	(`operation_is(`op_mul)) ? ~|resultx :
`endif
`ifdef HAS_WIDE_ALU
	(`operation_is(`op_addw) || `operation_is(`op_addwcy)
	|| `operation_is(`op_subw) || `operation_is(`op_subwcy)
	) ? ~|resultx :
`endif
	~|result;





always @(operation,
	shift_operation, shift_direction, shift_constant, shift_bit,
	result, operand_a, operand_b, carry_in, carry_out,
	addsub_result, addsub_carry
`ifdef HAS_WIDE_ALU
	, resultw, operand_v, addsubw_result
`endif
	) begin: on_alu

	carry_out = 0;
`ifdef HAS_WIDE_ALU
	resultw = operand_v;
`endif


`ifdef USE_ONEHOT_ENCODING
	case (1'b1)
`else
	case (operation)
`endif

		`operation(`op_add),
		`operation(`op_addcy):
			{carry_out, result} = addsub_result;

`ifdef HAS_COMPARE_OPERATION
		`operation(`op_compare),
`endif
		`operation(`op_sub),
		`operation(`op_subcy): begin
			{carry_out, result} = {~addsub_result[8], addsub_result[7:0]};
		end

		`operation(`op_and):
			result = operand_a & operand_b;

		`operation(`op_or):
			result = operand_a | operand_b;

`ifdef HAS_TEST_OPERATION
		`operation(`op_test):
			begin result = operand_a & operand_b; carry_out = ^result; end
`endif

		`operation(`op_xor):
			result = operand_a ^ operand_b;

		`operation(`op_rs):
			if (shift_direction)
				{result, carry_out} = {shift_bit, operand_a};
			else
				{carry_out, result} = {operand_a, shift_bit};

`ifdef HAS_MUL_OPERATION
		`operation(`op_mul):
			{resultw, result} = operand_a * operand_b;
`endif

`ifdef HAS_WIDE_ALU
		`operation(`op_addw),
		`operation(`op_addwcy):
			{carry_out, resultw, result} = addsubw_result;

		`operation(`op_subw),
		`operation(`op_subwcy):
			{carry_out, resultw, result} = {~addsubw_result[16], addsubw_result[15:0]};
`endif

		default:
			result = operand_b;

	endcase

end


`ifdef HAS_DEBUG

`include "pacoblaze_util.v"

always @(operand_a, operand_b, result)
	debug_rabc = {"r=", numtohex(result[7:4]), numtohex(operand_a[3:0]), " a=", numtohex(operand_a[7:4]), numtohex(operand_a[3:0]), " b=", numtohex(operand_b[7:4]), numtohex(operand_b[3:0]), " c=", numtohex(carry_in)};

always @(carry_in, carry_out, zero_out)
	debug_cz = {"C=", numtohex(carry_out), " Z=", numtohex(zero_out)};

always @(debug_rabc, debug_cz)
	debug = {debug_rabc, ", ", debug_cz};

`endif


endmodule
module `PACOBLAZE_ALU(
	operation,
	shift_operation, shift_direction, shift_constant,
	result, operand_a, operand_b,
`ifdef HAS_WIDE_ALU
	resultw, operand_u, operand_v,
`endif
	carry_in, zero_out, carry_out
`ifdef HAS_DEBUG
	, debug
`endif
);

input [`operation_width-1:0] operation;
input [2:0] shift_operation;
input shift_direction;
input shift_constant;
output reg [`operand_width-1:0] result;
input [`operand_width-1:0] operand_a, operand_b;
`ifdef HAS_WIDE_ALU
output reg [`operand_width-1:0] resultw;
input [`operand_width-1:0] operand_u, operand_v;
`endif
input carry_in;
output zero_out;
output reg carry_out;

`ifdef HAS_DEBUG
output reg [8*`alu_debug_width:1] debug;
reg [18*8:1] debug_rabc;
reg [7*8:1] debug_cz;
`endif


wire [`operand_width-1:0] addsub_b =
	(`operation_is(`op_sub)
	|| `operation_is(`op_subcy)
`ifdef HAS_COMPARE_OPERATION
	|| `operation_is(`op_compare)
`endif
	) ? ~operand_b :
	operand_b;

`ifdef HAS_WIDE_ALU
wire [2*`operand_width-1:0] addsubw_b =
	(`operation_is(`op_subw) || `operation_is(`op_subwcy)) ? ~{operand_v, operand_b} :
	{operand_v, operand_b};
`endif


wire addsub_carry =
	(`operation_is(`op_addcy)
`ifdef HAS_WIDE_ALU
	|| `operation_is(`op_addwcy)
`endif
	) ? carry_in :
	(`operation_is(`op_sub)
`ifdef HAS_COMPARE_OPERATION
	|| `operation_is(`op_compare)
`endif
`ifdef HAS_WIDE_ALU
	|| `operation_is(`op_subw)
`endif
	) ? 1 :
	(`operation_is(`op_subcy)
`ifdef HAS_WIDE_ALU
	|| `operation_is(`op_subwcy)
`endif
	) ? ~carry_in :
	0;


wire [1+`operand_width-1:0] addsub_result = operand_a + addsub_b + addsub_carry;
`ifdef HAS_WIDE_ALU
wire [1+2*`operand_width-1:0] addsubw_result =
	{operand_u, operand_a} + addsubw_b + addsub_carry;
`endif



wire shift_bit =
	(shift_operation == `opcode_rr) ? operand_a[0] :
	(shift_operation == `opcode_rl) ? operand_a[7] :
	(shift_operation == `opcode_rsa) ? carry_in :
	shift_constant;

`ifdef HAS_WIDE_ALU
wire [2*`operand_width-1:0] resultx = {resultw, result};
`endif

assign zero_out =
`ifdef HAS_MUL_OPERATION
	(`operation_is(`op_mul)) ? ~|resultx :
`endif
`ifdef HAS_WIDE_ALU
	(`operation_is(`op_addw) || `operation_is(`op_addwcy)
	|| `operation_is(`op_subw) || `operation_is(`op_subwcy)
	) ? ~|resultx :
`endif
	~|result;





always @(operation,
	shift_operation, shift_direction, shift_constant, shift_bit,
	result, operand_a, operand_b, carry_in, carry_out,
	addsub_result, addsub_carry
`ifdef HAS_WIDE_ALU
	, resultw, operand_v, addsubw_result
`endif
	) begin: on_alu

	carry_out = 0;
`ifdef HAS_WIDE_ALU
	resultw = operand_v;
`endif


`ifdef USE_ONEHOT_ENCODING
	case (1'b1)
`else
	case (operation)
`endif

		`operation(`op_add),
		`operation(`op_addcy):
			{carry_out, result} = addsub_result;

`ifdef HAS_COMPARE_OPERATION
		`operation(`op_compare),
`endif
		`operation(`op_sub),
		`operation(`op_subcy): begin
			{carry_out, result} = {~addsub_result[8], addsub_result[7:0]};
		end

		`operation(`op_and):
			result = operand_a & operand_b;

		`operation(`op_or):
			result = operand_a | operand_b;

`ifdef HAS_TEST_OPERATION
		`operation(`op_test):
			begin result = operand_a & operand_b; carry_out = ^result; end
`endif

		`operation(`op_xor):
			result = operand_a ^ operand_b;

		`operation(`op_rs):
			if (shift_direction)
				{result, carry_out} = {shift_bit, operand_a};
			else
				{carry_out, result} = {operand_a, shift_bit};

`ifdef HAS_MUL_OPERATION
		`operation(`op_mul):
			{resultw, result} = operand_a * operand_b;
`endif

`ifdef HAS_WIDE_ALU
		`operation(`op_addw),
		`operation(`op_addwcy):
			{carry_out, resultw, result} = addsubw_result;

		`operation(`op_subw),
		`operation(`op_subwcy):
			{carry_out, resultw, result} = {~addsubw_result[16], addsubw_result[15:0]};
`endif

		default:
			result = operand_b;

	endcase

end


`ifdef HAS_DEBUG

`include "pacoblaze_util.v"

always @(operand_a, operand_b, result)
	debug_rabc = {"r=", numtohex(result[7:4]), numtohex(operand_a[3:0]), " a=", numtohex(operand_a[7:4]), numtohex(operand_a[3:0]), " b=", numtohex(operand_b[7:4]), numtohex(operand_b[3:0]), " c=", numtohex(carry_in)};

always @(carry_in, carry_out, zero_out)
	debug_cz = {"C=", numtohex(carry_out), " Z=", numtohex(zero_out)};

always @(debug_rabc, debug_cz)
	debug = {debug_rabc, ", ", debug_cz};

`endif


endmodule