data/full_repos/permissive/449652714/src/sources_1/rtl/loader.v
1: b'%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/loader.v:7: Cannot find include file: define.vh\n`include "define.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/449652714/src/sources_1/rtl,data/full_repos/permissive/449652714/define.vh\n             data/full_repos/permissive/449652714/src/sources_1/rtl,data/full_repos/permissive/449652714/define.vh.v\n             data/full_repos/permissive/449652714/src/sources_1/rtl,data/full_repos/permissive/449652714/define.vh.sv\n             define.vh\n             define.vh.v\n             define.vh.sv\n             obj_dir/define.vh\n             obj_dir/define.vh.v\n             obj_dir/define.vh.sv\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/loader.v:52: Define or directive not defined: \'`BIN_SIZE\'\n                if(waddr>=`BIN_SIZE) DONE <= 1;\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/loader.v:52: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n                if(waddr>=`BIN_SIZE) DONE <= 1;\n                                   ^\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/loader.v:82: Define or directive not defined: \'`SERIAL_WCNT\'\n        end else if( waitnum >= `SERIAL_WCNT ) begin\n                                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/loader.v:82: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        end else if( waitnum >= `SERIAL_WCNT ) begin\n                                             ^\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/loader.v:88: syntax error, unexpected else\n        end else begin\n            ^~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/loader.v:123: Define or directive not defined: \'`SERIAL_WCNT\'\n    assign waitcnt = `SERIAL_WCNT;\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/loader.v:123: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    assign waitcnt = `SERIAL_WCNT;\n                                 ^\n%Error: Exiting due to 8 error(s)\n'
module PLOADER (CLK, RST_X, RXD, ADDR, DATA, WE, DONE, KEY_WE, KEY_DATA);
    input  wire         CLK, RST_X, RXD;
    output reg  [31:0]  ADDR;
    output reg  [31:0]  DATA;
    output reg          WE;
    output reg          DONE;
    output wire         KEY_WE;
    output wire [7:0]   KEY_DATA;

    reg [31:0] waddr;

    wire SER_EN;
    wire [7:0] SER_DATA;
    serialc serc (CLK, RST_X, RXD, SER_DATA, SER_EN);

    assign KEY_WE = SER_EN && DONE;
    assign KEY_DATA = SER_DATA;

    always @(posedge CLK) begin
        if(!RST_X) begin
            {ADDR, DATA, WE, waddr, DONE} <= 0;
        end else begin
            if(DONE==0 && SER_EN) begin
                ADDR  <= waddr;

                DATA  <= {SER_DATA, DATA[31:8]};
                WE    <= (waddr[1:0]==3);
                waddr <= waddr + 1;
            end else begin
                WE <= 0;
                if(waddr>=`BIN_SIZE) DONE <= 1;
            end
        end
    end
endmodule
module PLOADER (CLK, RST_X, RXD, ADDR, DATA, WE, DONE, KEY_WE, KEY_DATA);

    input  wire         CLK, RST_X, RXD;
    output reg  [31:0]  ADDR;
    output reg  [31:0]  DATA;
    output reg          WE;
    output reg          DONE;
    output wire         KEY_WE;
    output wire [7:0]   KEY_DATA;

    reg [31:0] waddr;

    wire SER_EN;
    wire [7:0] SER_DATA;
    serialc serc (CLK, RST_X, RXD, SER_DATA, SER_EN);

    assign KEY_WE = SER_EN && DONE;
    assign KEY_DATA = SER_DATA;

    always @(posedge CLK) begin
        if(!RST_X) begin
            {ADDR, DATA, WE, waddr, DONE} <= 0;
        end else begin
            if(DONE==0 && SER_EN) begin
                ADDR  <= waddr;

                DATA  <= {SER_DATA, DATA[31:8]};
                WE    <= (waddr[1:0]==3);
                waddr <= waddr + 1;
            end else begin
                WE <= 0;
                if(waddr>=`BIN_SIZE) DONE <= 1;
            end
        end
    end
endmodule