data/full_repos/permissive/501115231/DMA/testDMAC.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/501115231/DMA/testDMAC.v:64: Unsupported: Ignoring delay on this delayed statement.\n   forever #5 clk=~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/501115231/DMA/testDMAC.v:70: Unsupported: Ignoring delay on this delayed statement.\n   #2 rst = 1\'b1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/501115231/DMA/testDMAC.v:71: Unsupported: Ignoring delay on this delayed statement.\n   #1 rst = 1\'b0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/501115231/DMA/testDMAC.v:78: Unsupported: Ignoring delay on this delayed statement.\n      #46 stall_ext = 1\'b0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/501115231/DMA/testDMAC.v:79: Unsupported: Ignoring delay on this delayed statement.\n      #30 stall_ext = 1\'b0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/501115231/DMA/testDMAC.v:80: Unsupported: Ignoring delay on this delayed statement.\n      #40 stall_ext = 1\'b0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/501115231/DMA/testDMAC.v:81: Unsupported: Ignoring delay on this delayed statement.\n      #30 stall_ext = 1\'b0;\n      ^\n%Error: data/full_repos/permissive/501115231/DMA/testDMAC.v:14: Cannot find file containing module: \'DMAC\'\n DMAC #(.ADR_SIZE(16), .DATA_SIZE(16))\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/501115231/DMA,data/full_repos/permissive/501115231/DMAC\n             data/full_repos/permissive/501115231/DMA,data/full_repos/permissive/501115231/DMAC.v\n             data/full_repos/permissive/501115231/DMA,data/full_repos/permissive/501115231/DMAC.sv\n             DMAC\n             DMAC.v\n             DMAC.sv\n             obj_dir/DMAC\n             obj_dir/DMAC.v\n             obj_dir/DMAC.sv\n%Error: data/full_repos/permissive/501115231/DMA/testDMAC.v:33: Cannot find file containing module: \'memory_int\'\n memory_int #(.DMA_SIZE(16), .DMD_SIZE(16))\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/501115231/DMA/testDMAC.v:51: Cannot find file containing module: \'memory_ext_2\'\nmemory_ext_2 #(.DMA_SIZE(16), .DMD_SIZE(16))\n^~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testDMA();


 reg clk,rst,stall_ext,stall_int,reg_access=0;


 wire[15:0] NPA,SPA;
 wire[15:0] NPD_OUT,SPD_OUT;
 wire[15:0] NPD_IN,SPD_IN;
 wire wr_rd_np,wr_rd_sp,np_en,sp_en;



 DMAC #(.ADR_SIZE(16), .DATA_SIZE(16))
      tstDMA(
           clk,
           rst,
           stall_int,
           stall_ext,
           reg_access,
           NPD_IN,
           SPD_IN,
           wr_rd_np,
           wr_rd_sp,
           np_en,
           sp_en,
           NPA,
           SPA,
           NPD_OUT,
           SPD_OUT
        );

 memory_int #(.DMA_SIZE(16), .DMD_SIZE(16))
		testMemint(
					clk,
					np_en,
				  wr_rd_np,
					NPA,
					NPD_OUT,
					NPD_IN
				);

memory_ext_2 #(.DMA_SIZE(16), .DMD_SIZE(16))
    testMemext2	(
          clk,
          sp_en,
          wr_rd_sp,
          SPA,
          SPD_OUT,
          SPD_IN
        );

  initial 
  begin
   clk = 1'b0;
   forever #5 clk=~clk;
  end
  
 initial 
  begin
      rst = 1'b0;
   #2 rst = 1'b1;
   #1 rst = 1'b0;
  end

  initial 
  begin
       stall_int = 1'b0;
       stall_ext=0;
      #46 stall_ext = 1'b0;
      #30 stall_ext = 1'b0;
      #40 stall_ext = 1'b0;
      #30 stall_ext = 1'b0;
  end
endmodule
module testDMA();



 reg clk,rst,stall_ext,stall_int,reg_access=0;


 wire[15:0] NPA,SPA;
 wire[15:0] NPD_OUT,SPD_OUT;
 wire[15:0] NPD_IN,SPD_IN;
 wire wr_rd_np,wr_rd_sp,np_en,sp_en;



 DMAC #(.ADR_SIZE(16), .DATA_SIZE(16))
      tstDMA(
           clk,
           rst,
           stall_int,
           stall_ext,
           reg_access,
           NPD_IN,
           SPD_IN,
           wr_rd_np,
           wr_rd_sp,
           np_en,
           sp_en,
           NPA,
           SPA,
           NPD_OUT,
           SPD_OUT
        );

 memory_int #(.DMA_SIZE(16), .DMD_SIZE(16))
		testMemint(
					clk,
					np_en,
				  wr_rd_np,
					NPA,
					NPD_OUT,
					NPD_IN
				);

memory_ext_2 #(.DMA_SIZE(16), .DMD_SIZE(16))
    testMemext2	(
          clk,
          sp_en,
          wr_rd_sp,
          SPA,
          SPD_OUT,
          SPD_IN
        );

  initial 
  begin
   clk = 1'b0;
   forever #5 clk=~clk;
  end
  
 initial 
  begin
      rst = 1'b0;
   #2 rst = 1'b1;
   #1 rst = 1'b0;
  end

  initial 
  begin
       stall_int = 1'b0;
       stall_ext=0;
      #46 stall_ext = 1'b0;
      #30 stall_ext = 1'b0;
      #40 stall_ext = 1'b0;
      #30 stall_ext = 1'b0;
  end
endmodule