data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ram/alram113x.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ram/alram113x.v:61: Cannot find file containing module: 'alram112x'\nalram112x\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ram,data/full_repos/permissive/530013823/alram112x\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ram,data/full_repos/permissive/530013823/alram112x.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ram,data/full_repos/permissive/530013823/alram112x.sv\n             alram112x\n             alram112x.v\n             alram112x.sv\n             obj_dir/alram112x\n             obj_dir/alram112x.v\n             obj_dir/alram112x.sv\n%Error: Exiting due to 1 error(s)\n"
module alram113x
    (
     clkw,
     clkr,
     rst,
     
     rdo,
     ra,
     
     wdi,
     wa,
     we
     );



parameter WID = 256;
parameter AWID = 5;
parameter DEP = 1<<AWID;




input clkw;
input clkr;
input rst;

output [WID-1:0] rdo;
input [AWID-1:0] ra;

input [WID-1:0]  wdi;
input [AWID-1:0] wa;
input            we;




reg [AWID-1:0]   ira;
reg [WID-1:0]   rdo;
wire [WID-1:0]    irdo;

always@(posedge clkr)
    begin
    ira <= ra;
    rdo <= irdo;
    end

alram112x
    #(WID,AWID)
ialram112x
    (
     .clkw(clkw),
     .clkr(clkr),
     .rst(rst),
     
     .rdo(irdo),
     .ra(ira),
     
     .wdi(wdi),
     .wa(wa),
     .we(we)
     );

endmodule
module alram113x
    (
     clkw,
     clkr,
     rst,
     
     rdo,
     ra,
     
     wdi,
     wa,
     we
     );




parameter WID = 256;
parameter AWID = 5;
parameter DEP = 1<<AWID;




input clkw;
input clkr;
input rst;

output [WID-1:0] rdo;
input [AWID-1:0] ra;

input [WID-1:0]  wdi;
input [AWID-1:0] wa;
input            we;




reg [AWID-1:0]   ira;
reg [WID-1:0]   rdo;
wire [WID-1:0]    irdo;

always@(posedge clkr)
    begin
    ira <= ra;
    rdo <= irdo;
    end

alram112x
    #(WID,AWID)
ialram112x
    (
     .clkw(clkw),
     .clkr(clkr),
     .rst(rst),
     
     .rdo(irdo),
     .ra(ira),
     
     .wdi(wdi),
     .wa(wa),
     .we(we)
     );

endmodule