data/full_repos/permissive/487568919/basic_verilog/dynamic_delay.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/dynamic_delay.sv:82: Operator ADD expects 32 bits on the LHS, but LHS\'s SEL generates 8 bits.\n                                                                                      : ... In instance dynamic_delay\n    out[j] <= pack_data[sel[SEL_W-1:0]+j];\n                                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module dynamic_delay #( parameter
  LENGTH = 63,
  WIDTH = 4,

  SEL_W = $clog2( (LENGTH+1)*WIDTH )

)(
  input clk,
  input nrst,
  input ena,
  input [WIDTH-1:0] in,


  input [SEL_W-1:0] sel,
  output logic [WIDTH-1:0] out
);



logic [(LENGTH+1)-1:0][WIDTH-1:0] data = '0;


logic [(LENGTH+1)*WIDTH-1:0] pack_data;
assign pack_data[(LENGTH+1)*WIDTH-1:0] = data;

integer i;
always_ff @(posedge clk) begin
  if( ~nrst ) begin

    for( i=1; i<(LENGTH+1); i=i+1 ) begin
      data[i][WIDTH-1:0] <= '0;
    end
  end else if (ena) begin
    for( i=1; i<(LENGTH+1); i=i+1 ) begin
      data[i][WIDTH-1:0] <= data[i-1][WIDTH-1:0];
    end
  end
end

integer j;
always_comb begin

  data[0][WIDTH-1:0] <= in[WIDTH-1:0];


  for( j=0; j<WIDTH; j=j+1 ) begin
    out[j] <= pack_data[sel[SEL_W-1:0]+j];
  end
end

endmodule
module dynamic_delay #( parameter
  LENGTH = 63,
  WIDTH = 4,

  SEL_W = $clog2( (LENGTH+1)*WIDTH )

)(
  input clk,
  input nrst,
  input ena,
  input [WIDTH-1:0] in,


  input [SEL_W-1:0] sel,
  output logic [WIDTH-1:0] out
);




logic [(LENGTH+1)-1:0][WIDTH-1:0] data = '0;


logic [(LENGTH+1)*WIDTH-1:0] pack_data;
assign pack_data[(LENGTH+1)*WIDTH-1:0] = data;

integer i;
always_ff @(posedge clk) begin
  if( ~nrst ) begin

    for( i=1; i<(LENGTH+1); i=i+1 ) begin
      data[i][WIDTH-1:0] <= '0;
    end
  end else if (ena) begin
    for( i=1; i<(LENGTH+1); i=i+1 ) begin
      data[i][WIDTH-1:0] <= data[i-1][WIDTH-1:0];
    end
  end
end

integer j;
always_comb begin

  data[0][WIDTH-1:0] <= in[WIDTH-1:0];


  for( j=0; j<WIDTH; j=j+1 ) begin
    out[j] <= pack_data[sel[SEL_W-1:0]+j];
  end
end

endmodule