data/full_repos/permissive/518306084/iiitb_bidicntr.v
data/verilator_xmls/3ea15b06-d51c-4681-a431-7a6cdd6a7de8.xml
module iiitb_bidicntr(count,clk,ctrl,reset);
	input clk,reset,ctrl;
	output reg [3:0] count;
	always@(posedge clk)
		begin
		if(reset) count<=0;
		else if(ctrl) count<=count+1;
		else count<=count-1;
	end
endmodule
module iiitb_bidicntr(count,clk,ctrl,reset);

	input clk,reset,ctrl;
	output reg [3:0] count;
	always@(posedge clk)
		begin
		if(reset) count<=0;
		else if(ctrl) count<=count+1;
		else count<=count-1;
	end
endmodule