data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/clip_reg.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/clip_reg.v:29: Little bit endian vector: MSB < LSB of bit range: -1:0\n     input [bits_in-1:0] in,\n           ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/clip_reg.v:30: Little bit endian vector: MSB < LSB of bit range: -1:0\n     output reg [bits_out-1:0] out,\n                ^\n%Warning-LITENDIAN: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/clip_reg.v:34: Little bit endian vector: MSB < LSB of bit range: -1:0\n   wire [bits_out-1:0] temp;\n        ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/clip_reg.v:36: Cannot find file containing module: \'clip\'\n   clip #(.bits_in(bits_in),.bits_out(bits_out)) clip (.in(in),.out(temp));\n   ^~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib,data/full_repos/permissive/447976230/clip\n             data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib,data/full_repos/permissive/447976230/clip.v\n             data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib,data/full_repos/permissive/447976230/clip.sv\n             clip\n             clip.v\n             clip.sv\n             obj_dir/clip\n             obj_dir/clip.v\n             obj_dir/clip.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module clip_reg
  #(parameter bits_in=0,
    parameter bits_out=0,
    parameter STROBED=1'b0)
    (input clk,
     input [bits_in-1:0] in,
     output reg [bits_out-1:0] out,
     input strobe_in,
     output reg strobe_out);
   
   wire [bits_out-1:0] temp;

   clip #(.bits_in(bits_in),.bits_out(bits_out)) clip (.in(in),.out(temp));

   always @(posedge clk)
     strobe_out <= strobe_in;
   
   always @(posedge clk)
     if(strobe_in | ~STROBED)
       out <= temp;
   
endmodule
module clip_reg
  #(parameter bits_in=0,
    parameter bits_out=0,
    parameter STROBED=1'b0)
    (input clk,
     input [bits_in-1:0] in,
     output reg [bits_out-1:0] out,
     input strobe_in,
     output reg strobe_out);

   
   wire [bits_out-1:0] temp;

   clip #(.bits_in(bits_in),.bits_out(bits_out)) clip (.in(in),.out(temp));

   always @(posedge clk)
     strobe_out <= strobe_in;
   
   always @(posedge clk)
     if(strobe_in | ~STROBED)
       out <= temp;
   
endmodule