data/full_repos/permissive/48602886/src/device/vga_sdram/vga_display_sdram.sv
1: b"%Error: data/full_repos/permissive/48602886/src/device/vga_sdram/vga_display_sdram.sv:80: Cannot find file containing module: 'vga_640x480_60hz_adv7123'\n vga_640x480_60hz_adv7123 DISPLAY_MODULE(\n ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/48602886/src/device/vga_sdram,data/full_repos/permissive/48602886/vga_640x480_60hz_adv7123\n             data/full_repos/permissive/48602886/src/device/vga_sdram,data/full_repos/permissive/48602886/vga_640x480_60hz_adv7123.v\n             data/full_repos/permissive/48602886/src/device/vga_sdram,data/full_repos/permissive/48602886/vga_640x480_60hz_adv7123.sv\n             vga_640x480_60hz_adv7123\n             vga_640x480_60hz_adv7123.v\n             vga_640x480_60hz_adv7123.sv\n             obj_dir/vga_640x480_60hz_adv7123\n             obj_dir/vga_640x480_60hz_adv7123.v\n             obj_dir/vga_640x480_60hz_adv7123.sv\n%Error: Exiting due to 1 error(s)\n"
module vga_display_sdram(

		input wire iCLOCK,
		input wire inRESET,
		input wire iRESET_SYNC,

		input wire iDEV_REQ,		
		output wire oDEV_BUSY,
		input wire iDEV_RW,
		input wire [31:0] iDEV_ADDR,
		input wire [31:0] iDEV_DATA,

		output wire oDEV_REQ,		
		input wire iDEV_BUSY,
		output wire [31:0] oDEV_DATA,

		output wire oDEV_IRQ_REQ,		
		input wire iDEV_IRQ_BUSY, 
		input wire iDEV_IRQ_ACK,

		input wire iVGA_CLOCK,

		output wire oMEM_VALID,
		output wire [1:0] oMEM_BYTEENA,
		output wire oMEM_RW,
		output wire [31:0] oMEM_ADDR,
		output wire [15:0] oMEM_DATA,
		input wire iMEM_BUSY,
		input wire iMEM_VALID,
		input wire [15:0] iMEM_DATA,
		output wire oMEM_BUSY,

		output wire oDISP_HSYNC,
		output wire oDISP_VSYNC,

		output wire oADV_CLOCK,
		output wire onADV_BLANK,
		output wire onADV_SYNC,
		output wire [7:0] oADV_R,
		output wire [7:0] oADV_G,
		output wire [7:0] oADV_B
	);					
	
	
	


	wire displaycontroller_wait;

	wire display_addr_wr_condition;

	reg b_req;
	reg [31:0] b_data;
	

	assign display_addr_wr_condition = iDEV_REQ && !displaycontroller_wait;


	vga_640x480_60hz_adv7123 DISPLAY_MODULE(

		.iCLOCK(iCLOCK),
		.inRESET(inRESET),
		.iRESET_SYNC(iRESET_SYNC),		

		.iDISP_WR_REQ(display_addr_wr_condition),
		.oDISP_WR_BUSY(displaycontroller_wait),
		.iDISP_WR_ADDR({2'h0, iDEV_ADDR[31:2]}),
		.iDISP_WR_DATA(iDEV_DATA),

		.iVGA_CLOCK(iVGA_CLOCK),

		.*,

		.oDISP_HSYNC(oDISP_HSYNC),
		.oDISP_VSYNC(oDISP_VSYNC),

		.oADV_CLOCK(oADV_CLOCK),
		.onADV_BLANK(onADV_BLANK),
		.onADV_SYNC(onADV_SYNC),
		.oADV_R(oADV_R),
		.oADV_G(oADV_G),
		.oADV_B(oADV_B)
	);	
	

	always@(posedge iCLOCK or negedge inRESET)begin
		if(!inRESET)begin
			b_req <= 1'b0;
			b_data <= {32{1'b0}};
		end
		else if(iRESET_SYNC)begin
			b_req <= 1'b0;
			b_data <= {32{1'b0}};
		end
		else begin
			b_req <= 1'b0;
			b_data <= {32{1'b0}};
		end
	end
	
	

	assign oDEV_BUSY = displaycontroller_wait;
	assign oDEV_REQ = b_req;
	assign oDEV_DATA = b_data;
	assign oDEV_IRQ_REQ = 1'b0;
	

endmodule
module vga_display_sdram(

		input wire iCLOCK,
		input wire inRESET,
		input wire iRESET_SYNC,

		input wire iDEV_REQ,		
		output wire oDEV_BUSY,
		input wire iDEV_RW,
		input wire [31:0] iDEV_ADDR,
		input wire [31:0] iDEV_DATA,

		output wire oDEV_REQ,		
		input wire iDEV_BUSY,
		output wire [31:0] oDEV_DATA,

		output wire oDEV_IRQ_REQ,		
		input wire iDEV_IRQ_BUSY, 
		input wire iDEV_IRQ_ACK,

		input wire iVGA_CLOCK,

		output wire oMEM_VALID,
		output wire [1:0] oMEM_BYTEENA,
		output wire oMEM_RW,
		output wire [31:0] oMEM_ADDR,
		output wire [15:0] oMEM_DATA,
		input wire iMEM_BUSY,
		input wire iMEM_VALID,
		input wire [15:0] iMEM_DATA,
		output wire oMEM_BUSY,

		output wire oDISP_HSYNC,
		output wire oDISP_VSYNC,

		output wire oADV_CLOCK,
		output wire onADV_BLANK,
		output wire onADV_SYNC,
		output wire [7:0] oADV_R,
		output wire [7:0] oADV_G,
		output wire [7:0] oADV_B
	);
					
	
	
	


	wire displaycontroller_wait;

	wire display_addr_wr_condition;

	reg b_req;
	reg [31:0] b_data;
	

	assign display_addr_wr_condition = iDEV_REQ && !displaycontroller_wait;


	vga_640x480_60hz_adv7123 DISPLAY_MODULE(

		.iCLOCK(iCLOCK),
		.inRESET(inRESET),
		.iRESET_SYNC(iRESET_SYNC),		

		.iDISP_WR_REQ(display_addr_wr_condition),
		.oDISP_WR_BUSY(displaycontroller_wait),
		.iDISP_WR_ADDR({2'h0, iDEV_ADDR[31:2]}),
		.iDISP_WR_DATA(iDEV_DATA),

		.iVGA_CLOCK(iVGA_CLOCK),

		.*,

		.oDISP_HSYNC(oDISP_HSYNC),
		.oDISP_VSYNC(oDISP_VSYNC),

		.oADV_CLOCK(oADV_CLOCK),
		.onADV_BLANK(onADV_BLANK),
		.onADV_SYNC(onADV_SYNC),
		.oADV_R(oADV_R),
		.oADV_G(oADV_G),
		.oADV_B(oADV_B)
	);	
	

	always@(posedge iCLOCK or negedge inRESET)begin
		if(!inRESET)begin
			b_req <= 1'b0;
			b_data <= {32{1'b0}};
		end
		else if(iRESET_SYNC)begin
			b_req <= 1'b0;
			b_data <= {32{1'b0}};
		end
		else begin
			b_req <= 1'b0;
			b_data <= {32{1'b0}};
		end
	end
	
	

	assign oDEV_BUSY = displaycontroller_wait;
	assign oDEV_REQ = b_req;
	assign oDEV_DATA = b_data;
	assign oDEV_IRQ_REQ = 1'b0;
	

endmodule