data/full_repos/permissive/427221126/src/FIFO.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/427221126/src/FIFO.v:349: Cell has missing pin: \'LAST\'\n  FIFOsync_ram #(.INWIDTH(INWIDTH), .DEPTH(DEPTH)) U_fifo (\n                                                   ^~~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-MULTITOP: data/full_repos/permissive/427221126/src/FIFO.v:277: Multiple top level modules\n                                                                      : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                      : ... Top module \'FIFOsync\'\nmodule FIFOsync \n       ^~~~~~~~\n                                                                      : ... Top module \'FIFOpi\'\nmodule FIFOpi \n       ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/FIFO.v:62: Operator NEQ expects 32 bits on the LHS, but LHS\'s VARREF \'tail\' generates 5 bits.\n                                                                  : ... In instance FIFOpi.U_fifo\n      if (tail != MAX_COUNT)\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/FIFO.v:78: Operator NEQ expects 32 bits on the LHS, but LHS\'s VARREF \'head\' generates 5 bits.\n                                                                  : ... In instance FIFOpi.U_fifo\n      if (head != MAX_COUNT)\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/FIFO.v:98: Operator NEQ expects 32 bits on the LHS, but LHS\'s VARREF \'count\' generates 5 bits.\n                                                                  : ... In instance FIFOpi.U_fifo\n        if (count != DEPTH)\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/FIFO.v:104: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'count\' generates 5 bits.\n                                                                   : ... In instance FIFOpi.U_fifo\n        if (count == DEPTH)  \n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/FIFO.v:129: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'count\' generates 5 bits.\n                                                                   : ... In instance FIFOpi.U_fifo\n  assign FULL = (count == DEPTH);\n                       ^~\n%Error: data/full_repos/permissive/427221126/src/FIFO.v:133: Cannot find file containing module: \'RAM2P_WF_RO\'\n  RAM2P_WF_RO #(.DATA_WIDTH(INWIDTH), .ADDR_WIDTH(PTR_WIDTH)) U_fiforam (\n  ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/RAM2P_WF_RO\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/RAM2P_WF_RO.v\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/RAM2P_WF_RO.sv\n             RAM2P_WF_RO\n             RAM2P_WF_RO.v\n             RAM2P_WF_RO.sv\n             obj_dir/RAM2P_WF_RO\n             obj_dir/RAM2P_WF_RO.v\n             obj_dir/RAM2P_WF_RO.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n'
module FIFOsync_ram
  #(
    parameter INWIDTH = 17, 
              DEPTH = 325
  )
  (
    input                CLK  ,
    input                RESET,
    input                EN   ,
    input  [INWIDTH-1:0] DI   ,
    input                WRITE,
    output [INWIDTH-1:0] DO   ,
    input                READ ,
    output               FULL ,
    output               EMPTY,
    output               LAST  
  );
  localparam CNT_WIDTH = $clog2(DEPTH+1);
  localparam MAX_COUNT = DEPTH-1;
  localparam PTR_WIDTH = $clog2(DEPTH);

  wire [INWIDTH-1:0]   do_head, do_tail;
  wire                 fiforam_we;
  reg                  fifo_empty_n;
  reg                  fifo_last;
  reg                  get_read_through_dout;
  reg  [CNT_WIDTH-1:0] count, next_count;
  reg  [PTR_WIDTH-1:0] head, tail, next_head;
  integer i;
  

  assign fiforam_we = (!RESET && WRITE && !FULL && EN);

  always @(posedge CLK) begin : update_tail
    if (RESET)
      tail <= 0;
    else if (EN && WRITE && !FULL)
      if (tail != MAX_COUNT)
        tail <= tail + 1;
      else
        tail <= 0;
  end

  always @(posedge CLK) begin : read_from_head
    if (RESET)
      head <= 0;
    else if (EN)
      head <= next_head;
  end

  always @* begin
    next_head = head;
    if (READ && (fifo_empty_n == 1'b1)) begin
      if (head != MAX_COUNT)
        next_head = head + 1;
      else
        next_head = 0;
    end
  end

  always @(posedge CLK) begin
    if (RESET)
      count <= 0;
    else if (EN) begin
      count <= next_count;
    end
  end

  always @(count or READ or WRITE) begin
    next_count = count;
    case ({READ, WRITE}) 
      2'b00 : next_count = count;
      2'b01 :
        if (count != DEPTH)
          next_count = count + 1;
      2'b10 :
        if (count != 0)
          next_count = count - 1;
      2'b11 :
        if (count == DEPTH)
          next_count = count - 1;
        else if (count == 0)
          next_count = count + 1;
        else
          next_count = count;
    endcase
  end
  
  always @(posedge CLK) begin : status_flags
    if (RESET) begin
      get_read_through_dout <= 0;
      fifo_empty_n <= 0;
    end
    else if (EN) begin
      get_read_through_dout <= (fiforam_we && (next_head == tail));
      fifo_empty_n <= !(next_count == 0);
    end
  end

  always @(*) begin
    fifo_last = (count != 0) && (next_count == 0);
  end

  assign DO = get_read_through_dout ? (do_tail) : (do_head);
  assign FULL = (count == DEPTH);
  assign EMPTY = (fifo_empty_n == 1'b0);
  assign LAST = fifo_last;
  
  RAM2P_WF_RO #(.DATA_WIDTH(INWIDTH), .ADDR_WIDTH(PTR_WIDTH)) U_fiforam (
    .CLK(CLK), .EN(EN), .RESET(RESET),
    .ADDR1(tail), .WE(fiforam_we),
    .ADDR2(next_head),
    .DI(DI),
    .DO1(do_tail),
    .DO2(do_head)
  );
endmodule
module FIFOsync_ram
  #(
    parameter INWIDTH = 17, 
              DEPTH = 325
  )
  (
    input                CLK  ,
    input                RESET,
    input                EN   ,
    input  [INWIDTH-1:0] DI   ,
    input                WRITE,
    output [INWIDTH-1:0] DO   ,
    input                READ ,
    output               FULL ,
    output               EMPTY,
    output               LAST  
  );

  localparam CNT_WIDTH = $clog2(DEPTH+1);
  localparam MAX_COUNT = DEPTH-1;
  localparam PTR_WIDTH = $clog2(DEPTH);

  wire [INWIDTH-1:0]   do_head, do_tail;
  wire                 fiforam_we;
  reg                  fifo_empty_n;
  reg                  fifo_last;
  reg                  get_read_through_dout;
  reg  [CNT_WIDTH-1:0] count, next_count;
  reg  [PTR_WIDTH-1:0] head, tail, next_head;
  integer i;
  

  assign fiforam_we = (!RESET && WRITE && !FULL && EN);

  always @(posedge CLK) begin : update_tail
    if (RESET)
      tail <= 0;
    else if (EN && WRITE && !FULL)
      if (tail != MAX_COUNT)
        tail <= tail + 1;
      else
        tail <= 0;
  end

  always @(posedge CLK) begin : read_from_head
    if (RESET)
      head <= 0;
    else if (EN)
      head <= next_head;
  end

  always @* begin
    next_head = head;
    if (READ && (fifo_empty_n == 1'b1)) begin
      if (head != MAX_COUNT)
        next_head = head + 1;
      else
        next_head = 0;
    end
  end

  always @(posedge CLK) begin
    if (RESET)
      count <= 0;
    else if (EN) begin
      count <= next_count;
    end
  end

  always @(count or READ or WRITE) begin
    next_count = count;
    case ({READ, WRITE}) 
      2'b00 : next_count = count;
      2'b01 :
        if (count != DEPTH)
          next_count = count + 1;
      2'b10 :
        if (count != 0)
          next_count = count - 1;
      2'b11 :
        if (count == DEPTH)
          next_count = count - 1;
        else if (count == 0)
          next_count = count + 1;
        else
          next_count = count;
    endcase
  end
  
  always @(posedge CLK) begin : status_flags
    if (RESET) begin
      get_read_through_dout <= 0;
      fifo_empty_n <= 0;
    end
    else if (EN) begin
      get_read_through_dout <= (fiforam_we && (next_head == tail));
      fifo_empty_n <= !(next_count == 0);
    end
  end

  always @(*) begin
    fifo_last = (count != 0) && (next_count == 0);
  end

  assign DO = get_read_through_dout ? (do_tail) : (do_head);
  assign FULL = (count == DEPTH);
  assign EMPTY = (fifo_empty_n == 1'b0);
  assign LAST = fifo_last;
  
  RAM2P_WF_RO #(.DATA_WIDTH(INWIDTH), .ADDR_WIDTH(PTR_WIDTH)) U_fiforam (
    .CLK(CLK), .EN(EN), .RESET(RESET),
    .ADDR1(tail), .WE(fiforam_we),
    .ADDR2(next_head),
    .DI(DI),
    .DO1(do_tail),
    .DO2(do_head)
  );
endmodule