data/full_repos/permissive/460328193/ipa_proj_pipe/alu.v
data/verilator_xmls/5b9d9e13-a42f-48bd-be1d-2eece74cde62.xml
module xor64(out,A,B);
input [63:0] A,B;
output [63:0] out;


genvar i;

generate for (i = 0; i <64;i=i+1)
 begin
   xor g1(out[i],A[i],B[i]);
 end
endgenerate

endmodule
module xor64(out,A,B);

input [63:0] A,B;
output [63:0] out;


genvar i;

generate for (i = 0; i <64;i=i+1)
 begin
   xor g1(out[i],A[i],B[i]);
 end
endgenerate

endmodule