data/full_repos/permissive/417288846/List_1/Task_1/mux_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/mux_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n        #1 i1 = 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/mux_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #1 s2 = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/mux_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #1 i2 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/mux_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #1 s2 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/mux_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #1 i3 = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/mux_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #1 s2 = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/mux_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #1 i4 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/mux_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #2 $finish;\n        ^\n%Error: data/full_repos/permissive/417288846/List_1/Task_1/mux_tb.v:34: Unsupported or unknown PLI call: $monitor\n    initial $monitor ($time, " s1=%d, s2=%d, i1=%d, i2=%d, i3=%d, i4=%d, out=%d", s1, s2, i1, i2, i3, i4, out);\n            ^~~~~~~~\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
    reg  i1, i2, i3, i4, s1, s2;
    wire out;

    mux_4 mux1(i1, i2, i3, i4, s1, s2, out);
    initial begin
        i1 = 0;
        i2 = 1;
        i3 = 0;
        i4 = 1;
        s1 = 0;
        s2 = 0;


        #1 i1 = 1;


        #1 s2 = 1;
        #1 i2 = 0;


        #1 s2 = 0;
        s1 = 1;
        #1 i3 = 1;
        

        #1 s2 = 1;
        #1 i4 = 0;



        #2 $finish;
    end
    initial $monitor ($time, " s1=%d, s2=%d, i1=%d, i2=%d, i3=%d, i4=%d, out=%d", s1, s2, i1, i2, i3, i4, out);
endmodule
module testbench;

    reg  i1, i2, i3, i4, s1, s2;
    wire out;

    mux_4 mux1(i1, i2, i3, i4, s1, s2, out);
    initial begin
        i1 = 0;
        i2 = 1;
        i3 = 0;
        i4 = 1;
        s1 = 0;
        s2 = 0;


        #1 i1 = 1;


        #1 s2 = 1;
        #1 i2 = 0;


        #1 s2 = 0;
        s1 = 1;
        #1 i3 = 1;
        

        #1 s2 = 1;
        #1 i4 = 0;



        #2 $finish;
    end
    initial $monitor ($time, " s1=%d, s2=%d, i1=%d, i2=%d, i3=%d, i4=%d, out=%d", s1, s2, i1, i2, i3, i4, out);
endmodule