data/full_repos/permissive/515186003/univ_shift_reg_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/515186003/univ_shift_reg_tb.v:7: Unsupported: Ignoring delay on this delayed statement.\nforever #05 clk=~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/515186003/univ_shift_reg_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n#10 s0=0;s1=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/515186003/univ_shift_reg_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n#10 s0=0;s1=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/515186003/univ_shift_reg_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n#10 s0=1;s1=0;\n^\n%Error: data/full_repos/permissive/515186003/univ_shift_reg_tb.v:4: Cannot find file containing module: \'UniversalShiftReg\'\nUniversalShiftReg b1(clk,clr,s0,s1,q0,q1,q2,q3,sinr,sinl,d0,d1,d2,d3);\n^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/515186003,data/full_repos/permissive/515186003/UniversalShiftReg\n             data/full_repos/permissive/515186003,data/full_repos/permissive/515186003/UniversalShiftReg.v\n             data/full_repos/permissive/515186003,data/full_repos/permissive/515186003/UniversalShiftReg.sv\n             UniversalShiftReg\n             UniversalShiftReg.v\n             UniversalShiftReg.sv\n             obj_dir/UniversalShiftReg\n             obj_dir/UniversalShiftReg.v\n             obj_dir/UniversalShiftReg.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module UniversalShiftReg_Tb;
reg q0,q1,q2,q3,clk,clr,sinr,sinl,s0,s1;
wire d0,d1,d2,d3;
UniversalShiftReg b1(clk,clr,s0,s1,q0,q1,q2,q3,sinr,sinl,d0,d1,d2,d3);
initial begin
clk=0;
forever #05 clk=~clk;
end
initial begin
clr=0;s0=1;s1=1;q0=1;q1=0;q2=1;q3=1;sinr=0;sinl=0;
#10 s0=0;s1=0;
#10 s0=0;s1=1;
#10 s0=1;s1=0;

end
endmodule
module UniversalShiftReg_Tb;

reg q0,q1,q2,q3,clk,clr,sinr,sinl,s0,s1;
wire d0,d1,d2,d3;
UniversalShiftReg b1(clk,clr,s0,s1,q0,q1,q2,q3,sinr,sinl,d0,d1,d2,d3);
initial begin
clk=0;
forever #05 clk=~clk;
end
initial begin
clr=0;s0=1;s1=1;q0=1;q1=0;q2=1;q3=1;sinr=0;sinl=0;
#10 s0=0;s1=0;
#10 s0=0;s1=1;
#10 s0=1;s1=0;

end
endmodule