data/full_repos/permissive/494148647/src/util/reset_synchronizer_tb.v
1: b'%Error: data/full_repos/permissive/494148647/src/util/reset_synchronizer_tb.v:47: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("reset_synchronizer_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/494148647/src/util/reset_synchronizer_tb.v:48: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, reset_synchronizer_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/494148647/src/util/reset_synchronizer_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n        repeat(4) #10 clk = ~clk;\n                  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/494148647/src/util/reset_synchronizer_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n        repeat(47) #10 clk = ~clk;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/494148647/src/util/reset_synchronizer_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n        repeat(20) #10 clk = ~clk;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/494148647/src/util/reset_synchronizer_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n        repeat(48) #10 clk = ~clk;\n                   ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module reset_synchronizer_tb ();

    localparam DELAY = 8;

    reg clk, rst;
    wire rst_out;

    integer i = 0, err_count = 0;

    reset_synchronizer #(.DELAY(DELAY)) DUT (
        .clk(clk),
        .rst_in(rst),
        .rst_out(rst_out)
    );


    always @(posedge clk) begin
        if (rst)
            i <= 0;
        else
            i <= i + 1;

        if (i < DELAY) begin
            if (rst_out != 1'b1) begin
                $display("ERROR: expected rst_out == 1 at %t", $time);
                err_count = err_count + 1;
            end
        end else begin
            if (rst_out != 1'b0) begin
                $display("ERROR: expected rst_out == 0 at %t", $time);
                err_count = err_count + 1;
            end
        end
    end


    initial begin
        $dumpfile("reset_synchronizer_tb.vcd");
        $dumpvars(0, reset_synchronizer_tb);

        clk = 1'b0;
        rst = 1'b1;
        repeat(4) #10 clk = ~clk;
        rst = 1'b0;
        repeat(47) #10 clk = ~clk;

        rst = 1'b1;
        repeat(20) #10 clk = ~clk;
        rst = 1'b0;
        repeat(48) #10 clk = ~clk;

        $display("test finished with %d errors", err_count);
        $finish;
    end

endmodule
module reset_synchronizer_tb ();


    localparam DELAY = 8;

    reg clk, rst;
    wire rst_out;

    integer i = 0, err_count = 0;

    reset_synchronizer #(.DELAY(DELAY)) DUT (
        .clk(clk),
        .rst_in(rst),
        .rst_out(rst_out)
    );


    always @(posedge clk) begin
        if (rst)
            i <= 0;
        else
            i <= i + 1;

        if (i < DELAY) begin
            if (rst_out != 1'b1) begin
                $display("ERROR: expected rst_out == 1 at %t", $time);
                err_count = err_count + 1;
            end
        end else begin
            if (rst_out != 1'b0) begin
                $display("ERROR: expected rst_out == 0 at %t", $time);
                err_count = err_count + 1;
            end
        end
    end


    initial begin
        $dumpfile("reset_synchronizer_tb.vcd");
        $dumpvars(0, reset_synchronizer_tb);

        clk = 1'b0;
        rst = 1'b1;
        repeat(4) #10 clk = ~clk;
        rst = 1'b0;
        repeat(47) #10 clk = ~clk;

        rst = 1'b1;
        repeat(20) #10 clk = ~clk;
        rst = 1'b0;
        repeat(48) #10 clk = ~clk;

        $display("test finished with %d errors", err_count);
        $finish;
    end

endmodule