data/full_repos/permissive/493265923/01_CLKMUX4_NOGLITCH/CLKMUX4_NOGLITCH.v
data/verilator_xmls/32c86285-08e2-459d-9886-581745d910e2.xml
module CLKMUX4_NOGLITCH(
    DATA3_I,
    DATA2_I,
    DATA1_I,
    DATA0_I,
    SEL_I,
    EN_I,
    DATA_O
);


    input  wire                DATA3_I;
    input  wire                DATA2_I;
    input  wire                DATA1_I;
    input  wire                DATA0_I;
    input  wire unsigned [1:0] SEL_I;
    input  wire                EN_I;

    output wire                DATA_O;


    wire unsigned [3:0] DATA_WIRE;
    wire unsigned [1:0] SELECT_ENABLE_WIRE_XOR;
    wire                SELECT_ENABLE_WIRE_OR;
    wire                TRUE_EN;
    wire                DATACTRL;

    reg unsigned [1:0] SEL_REG = 2'b00;
    reg                ENA_REG = 1'b0;



    assign DATA_WIRE[3:0] = {DATA3_I, DATA2_I, DATA1_I, DATA0_I};


    assign DATACTRL       = datasel(DATA_WIRE, SEL_REG);


    always @ (negedge DATACTRL) begin
        if (ENA_REG == 1'b0) begin
            SEL_REG[1:0] <= SEL_I[1:0];
        end
        ENA_REG <= TRUE_EN;
    end


    assign SELECT_ENABLE_WIRE_XOR[1:0] = {SEL_REG[1] ^ SEL_I[1], SEL_REG[0] ^ SEL_I[0]};
    assign SELECT_ENABLE_WIRE_OR       = SELECT_ENABLE_WIRE_XOR[1] | SELECT_ENABLE_WIRE_XOR[0];
    assign TRUE_EN                     = ~SELECT_ENABLE_WIRE_OR & EN_I;


    assign DATA_O                      = ENA_REG & DATACTRL;


    function datasel;
        input unsigned [3:0] data_wire;
        input unsigned [1:0] sel_reg; 
    begin
        case (sel_reg)
            2'b11:
                datasel = data_wire[3];

            2'b10:
                datasel = data_wire[2];

            2'b01:
                datasel = data_wire[1];

            default:
                datasel = data_wire[0];

        endcase
    end
    endfunction

endmodule
module CLKMUX4_NOGLITCH(
    DATA3_I,
    DATA2_I,
    DATA1_I,
    DATA0_I,
    SEL_I,
    EN_I,
    DATA_O
);



    input  wire                DATA3_I;
    input  wire                DATA2_I;
    input  wire                DATA1_I;
    input  wire                DATA0_I;
    input  wire unsigned [1:0] SEL_I;
    input  wire                EN_I;

    output wire                DATA_O;


    wire unsigned [3:0] DATA_WIRE;
    wire unsigned [1:0] SELECT_ENABLE_WIRE_XOR;
    wire                SELECT_ENABLE_WIRE_OR;
    wire                TRUE_EN;
    wire                DATACTRL;

    reg unsigned [1:0] SEL_REG = 2'b00;
    reg                ENA_REG = 1'b0;



    assign DATA_WIRE[3:0] = {DATA3_I, DATA2_I, DATA1_I, DATA0_I};


    assign DATACTRL       = datasel(DATA_WIRE, SEL_REG);


    always @ (negedge DATACTRL) begin
        if (ENA_REG == 1'b0) begin
            SEL_REG[1:0] <= SEL_I[1:0];
        end
        ENA_REG <= TRUE_EN;
    end


    assign SELECT_ENABLE_WIRE_XOR[1:0] = {SEL_REG[1] ^ SEL_I[1], SEL_REG[0] ^ SEL_I[0]};
    assign SELECT_ENABLE_WIRE_OR       = SELECT_ENABLE_WIRE_XOR[1] | SELECT_ENABLE_WIRE_XOR[0];
    assign TRUE_EN                     = ~SELECT_ENABLE_WIRE_OR & EN_I;


    assign DATA_O                      = ENA_REG & DATACTRL;


    function datasel;
        input unsigned [3:0] data_wire;
        input unsigned [1:0] sel_reg; 
    begin
        case (sel_reg)
            2'b11:
                datasel = data_wire[3];

            2'b10:
                datasel = data_wire[2];

            2'b01:
                datasel = data_wire[1];

            default:
                datasel = data_wire[0];

        endcase
    end
    endfunction

endmodule