data/full_repos/permissive/430026064/PC.v
1: b'%Error: data/full_repos/permissive/430026064/PC.v:1: Cannot find include file: defs.v\n`include "defs.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/430026064,data/full_repos/permissive/430026064/defs.v\n             data/full_repos/permissive/430026064,data/full_repos/permissive/430026064/defs.v.v\n             data/full_repos/permissive/430026064,data/full_repos/permissive/430026064/defs.v.sv\n             defs.v\n             defs.v.v\n             defs.v.sv\n             obj_dir/defs.v\n             obj_dir/defs.v.v\n             obj_dir/defs.v.sv\n%Error: data/full_repos/permissive/430026064/PC.v:17: Define or directive not defined: \'`CODE_START_ADDR\'\n         if(is_first_inst == 1) begin out <= `CODE_START_ADDR; is_first_inst = 0; end\n                                             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430026064/PC.v:17: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n         if(is_first_inst == 1) begin out <= `CODE_START_ADDR; is_first_inst = 0; end\n                                                             ^\n%Error: Exiting due to 3 error(s)\n'
module PC(
	input clock, 
	input is_stall,
  	input [31:0] in,
  	input enable,
    output reg [31:0] out
);
  
  integer is_first_inst = 1;
  always @(posedge clock) begin
      if(enable == 1'b1) begin
        if (is_stall == 0) begin
        	if(is_first_inst == 1) begin out <= `CODE_START_ADDR; is_first_inst = 0; end
        	else begin out <= in; end
          $display("Clock rising edge!");
        end else begin $display("PC: Pipeline is stalled"); end
      end
    end 
endmodule
module PC(
	input clock, 
	input is_stall,
  	input [31:0] in,
  	input enable,
    output reg [31:0] out
);

  
  integer is_first_inst = 1;
  always @(posedge clock) begin
      if(enable == 1'b1) begin
        if (is_stall == 0) begin
        	if(is_first_inst == 1) begin out <= `CODE_START_ADDR; is_first_inst = 0; end
        	else begin out <= in; end
          $display("Clock rising edge!");
        end else begin $display("PC: Pipeline is stalled"); end
      end
    end 
endmodule