data/full_repos/permissive/493019833/test/testcase/firrtl/FixedRing1.lo/sbt/FixedRing1.lo.v
data/verilator_xmls/abe4d5bf-85ca-4da2-aec2-17378ed37bf2.xml
module FixedRing1(
  input         clock,
  input         reset,
  input  [15:0] io_in,
  output [15:0] io_floor,
  output [15:0] io_ceil,
  output        io_isWhole,
  output [15:0] io_round,
  output [63:0] io_real_node
);
  wire [11:0] _T_9 = io_in[15:4];
  wire [15:0] _GEN_0 = {$signed(_T_9), 4'h0};
  wire  _T_12 = $signed(io_in) == $signed(_GEN_0);
  wire [12:0] _T_17 = $signed(_T_9) + 12'sh1;
  wire [12:0] _T_20 = _T_12 ? $signed({{1{_T_9[11]}},_T_9}) : $signed(_T_17);
  wire [16:0] _T_24 = $signed(io_in) + 16'sh8;
  wire [12:0] _T_26 = _T_24[16:4];
  wire [16:0] _GEN_2 = {$signed(_T_20), 4'h0};
  wire [16:0] _GEN_5 = {$signed(_T_26), 4'h0};
  assign io_floor = {$signed(_T_9), 4'h0};
  assign io_ceil = _GEN_2[15:0];
  assign io_isWhole = $signed(io_in) == $signed(_GEN_0);
  assign io_round = _GEN_5[15:0];
  assign io_real_node = 64'h0;
endmodule
module FixedRing1(
  input         clock,
  input         reset,
  input  [15:0] io_in,
  output [15:0] io_floor,
  output [15:0] io_ceil,
  output        io_isWhole,
  output [15:0] io_round,
  output [63:0] io_real_node
);

  wire [11:0] _T_9 = io_in[15:4];
  wire [15:0] _GEN_0 = {$signed(_T_9), 4'h0};
  wire  _T_12 = $signed(io_in) == $signed(_GEN_0);
  wire [12:0] _T_17 = $signed(_T_9) + 12'sh1;
  wire [12:0] _T_20 = _T_12 ? $signed({{1{_T_9[11]}},_T_9}) : $signed(_T_17);
  wire [16:0] _T_24 = $signed(io_in) + 16'sh8;
  wire [12:0] _T_26 = _T_24[16:4];
  wire [16:0] _GEN_2 = {$signed(_T_20), 4'h0};
  wire [16:0] _GEN_5 = {$signed(_T_26), 4'h0};
  assign io_floor = {$signed(_T_9), 4'h0};
  assign io_ceil = _GEN_2[15:0];
  assign io_isWhole = $signed(io_in) == $signed(_GEN_0);
  assign io_round = _GEN_5[15:0];
  assign io_real_node = 64'h0;
endmodule