data/full_repos/permissive/524307278/datapath/alu.v
1: b'%Error: data/full_repos/permissive/524307278/datapath/alu.v:1: Input/output/inout declaration not found for port: \'Addr\'\nmodule alu(busA, busB, ALUctr, zero, Alu_out, Addr);\n                                              ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/524307278/datapath/alu.v:29: Signal definition not found, creating implicitly: \'Addr\'\n    assign Addr = Alu_out;\n           ^~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module alu(busA, busB, ALUctr, zero, Alu_out, Addr);
    input [31:0] busA, busB;
    input [1:0] ALUctr;

    output [31:0] zero;
    output reg[31:0] Alu_out;


    parameter ADD = 2'b00;
    parameter SUB = 2'b01;
    parameter OR = 2'b10;


    always@(*) begin
        case(ALUctr)
            ADD: begin
                Alu_out = busA + busB;
            end
            SUB: begin
                Alu_out = busA - busB;
            end
            OR: begin
                Alu_out = busA|busB;
            end
        endcase
    end

    assign zero = Alu_out;
    assign Addr = Alu_out;


endmodule
module alu(busA, busB, ALUctr, zero, Alu_out, Addr);

    input [31:0] busA, busB;
    input [1:0] ALUctr;

    output [31:0] zero;
    output reg[31:0] Alu_out;


    parameter ADD = 2'b00;
    parameter SUB = 2'b01;
    parameter OR = 2'b10;


    always@(*) begin
        case(ALUctr)
            ADD: begin
                Alu_out = busA + busB;
            end
            SUB: begin
                Alu_out = busA - busB;
            end
            OR: begin
                Alu_out = busA|busB;
            end
        endcase
    end

    assign zero = Alu_out;
    assign Addr = Alu_out;


endmodule