data/full_repos/permissive/514437299/digital/rtl/servant_top.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:79: Little bit endian vector: MSB < LSB of bit range: -1:0\n  input  wire [MAX_RANDBITS_LEN-1:0] i_msk_randbits,\n              ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:80: Little bit endian vector: MSB < LSB of bit range: -1:0\n  input  wire [XTR_RANDBITS_LEN-1:0] i_xtr_randbits,\n              ^\n%Warning-LITENDIAN: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:243: Little bit endian vector: MSB < LSB of bit range: -1:0\n  wire [CMO_RANDBITS_LEN-1:0] msk_randbits_cmo;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:244: Little bit endian vector: MSB < LSB of bit range: -1:0\n  wire [DLO_RANDBITS_LEN-1:0] msk_randbits_dlo;\n       ^\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:328: [2:3] Range extract has backward bit ordering, perhaps you wanted [3:2]\n                                                                          : ... In instance servant_top\n  assign cmo_rf_rdata_enc      = cmo_rf_rdata_enc_nsh    ^ i_xtr_randbits[3:2];\n                                                                         ^\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:329: [2:3] Range extract has backward bit ordering, perhaps you wanted [3:2]\n                                                                          : ... In instance servant_top\n  assign cmo_rf_rdata_enc_s1   =                           i_xtr_randbits[3:2];\n                                                                         ^\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:330: [4:35] Range extract has backward bit ordering, perhaps you wanted [35:4]\n                                                                          : ... In instance servant_top\n  assign cmo_wb_mem_rdt_enc    = cmo_wb_mem_rdt_enc_nsh  ^ i_xtr_randbits[35:4];\n                                                                         ^\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:330: Extracting 32 bits from only 2 bit number\n                                                                          : ... In instance servant_top\n  assign cmo_wb_mem_rdt_enc    = cmo_wb_mem_rdt_enc_nsh  ^ i_xtr_randbits[35:4];\n                                                                         ^\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:331: [4:35] Range extract has backward bit ordering, perhaps you wanted [35:4]\n                                                                          : ... In instance servant_top\n  assign cmo_wb_mem_rdt_enc_s1 =                           i_xtr_randbits[35:4];\n                                                                         ^\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:331: Extracting 32 bits from only 2 bit number\n                                                                          : ... In instance servant_top\n  assign cmo_wb_mem_rdt_enc_s1 =                           i_xtr_randbits[35:4];\n                                                                         ^\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:335: [2:3] Range extract has backward bit ordering, perhaps you wanted [3:2]\n                                                                          : ... In instance servant_top\n  assign dlo_rf_rdata_enc      = dlo_rf_rdata_enc_nsh    ^ i_xtr_randbits[3:2];\n                                                                         ^\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:336: [2:3] Range extract has backward bit ordering, perhaps you wanted [3:2]\n                                                                          : ... In instance servant_top\n  assign dlo_rf_rdata_enc_s1   =                           i_xtr_randbits[3:2];\n                                                                         ^\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:337: [4:35] Range extract has backward bit ordering, perhaps you wanted [35:4]\n                                                                          : ... In instance servant_top\n  assign dlo_wb_mem_rdt_enc    = dlo_wb_mem_rdt_enc_nsh  ^ i_xtr_randbits[35:4];\n                                                                         ^\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:337: Extracting 32 bits from only 2 bit number\n                                                                          : ... In instance servant_top\n  assign dlo_wb_mem_rdt_enc    = dlo_wb_mem_rdt_enc_nsh  ^ i_xtr_randbits[35:4];\n                                                                         ^\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:338: [4:35] Range extract has backward bit ordering, perhaps you wanted [35:4]\n                                                                          : ... In instance servant_top\n  assign dlo_wb_mem_rdt_enc_s1 =                           i_xtr_randbits[35:4];\n                                                                         ^\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:338: Extracting 32 bits from only 2 bit number\n                                                                          : ... In instance servant_top\n  assign dlo_wb_mem_rdt_enc_s1 =                           i_xtr_randbits[35:4];\n                                                                         ^\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:341: Cannot find file containing module: \'servant\'\n  servant U_SERVANT_CMO(\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514437299/digital/rtl,data/full_repos/permissive/514437299/servant\n             data/full_repos/permissive/514437299/digital/rtl,data/full_repos/permissive/514437299/servant.v\n             data/full_repos/permissive/514437299/digital/rtl,data/full_repos/permissive/514437299/servant.sv\n             servant\n             servant.v\n             servant.sv\n             obj_dir/servant\n             obj_dir/servant.v\n             obj_dir/servant.sv\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:374: Cannot find file containing module: \'servant\'\n  servant U_SERVANT_DLO(\n  ^~~~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:437: Cannot find file containing module: \'servant\'\n  servant U_SERVANT_PLN(\n  ^~~~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:454: Cannot find file containing module: \'mux\'\n  mux U_MUX(\n  ^~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:562: Cannot find file containing module: \'ram\'\n  ram U_RAM(\n  ^~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/servant_top.v:573: Cannot find file containing module: \'rf\'\n  rf U_RF(\n  ^~\n%Error: Exiting due to 18 error(s), 4 warning(s)\n'
module sec(
  input  wire [1:0]  i_key_enc_rf,
  input  wire [31:0] i_key_enc_ram,
  input  wire [8:0]  i_key_scr_rf,
  input  wire [31:0] i_key_scr_ram,
`ifndef RTL
  input  wire [8:0]  i_rf_waddr_s1,
  input  wire [8:0]  i_rf_raddr_s1,
  input  wire [1:0]  i_rf_wdata_s1,
  input  wire [1:0]  i_rf_rdata_enc_s1,
  output wire [8:0]  o_rf_waddr_scr_s1,
  output wire [8:0]  o_rf_raddr_scr_s1,
  output wire [1:0]  o_rf_wdata_enc_s1,
  output wire [1:0]  o_rf_rdata_s1,
  input  wire [31:0] i_wb_mem_adr_s1,
  input  wire [31:0] i_wb_mem_dat_s1,
  input  wire [31:0] i_wb_mem_rdt_enc_s1,
  output wire [31:0] o_wb_mem_adr_scr_s1,
  output wire [31:0] o_wb_mem_dat_enc_s1,
  output wire [31:0] o_wb_mem_rdt_s1,
`endif
  input  wire [8:0]  i_rf_waddr,
  input  wire [8:0]  i_rf_raddr,
  input  wire [1:0]  i_rf_wdata,
  input  wire [1:0]  i_rf_rdata_enc,
  output wire [8:0]  o_rf_waddr_scr,
  output wire [8:0]  o_rf_raddr_scr,
  output wire [1:0]  o_rf_wdata_enc,
  output wire [1:0]  o_rf_rdata,
  input  wire [31:0] i_wb_mem_adr,
  input  wire [31:0] i_wb_mem_dat,
  input  wire [31:0] i_wb_mem_rdt_enc,
  output wire [31:0] o_wb_mem_adr_scr,
  output wire [31:0] o_wb_mem_dat_enc,
  output wire [31:0] o_wb_mem_rdt);



  assign o_rf_waddr_scr      = i_rf_waddr       ^ i_key_scr_rf;
  assign o_rf_raddr_scr      = i_rf_raddr       ^ i_key_scr_rf;
  assign o_rf_wdata_enc      = i_rf_wdata       ^ i_key_enc_rf;
  assign o_rf_rdata          = i_rf_rdata_enc   ^ i_key_enc_rf;

  assign o_wb_mem_adr_scr    = i_wb_mem_adr     ^ i_key_scr_ram;
  assign o_wb_mem_dat_enc    = i_wb_mem_dat     ^ i_key_enc_ram ^ o_wb_mem_adr_scr;
  assign o_wb_mem_rdt        = i_wb_mem_rdt_enc ^ i_key_enc_ram ^ o_wb_mem_adr_scr;

`ifndef RTL
  assign o_rf_waddr_scr_s1      = i_rf_waddr_s1;
  assign o_rf_raddr_scr_s1      = i_rf_raddr_s1;
  assign o_rf_wdata_enc_s1      = i_rf_wdata_s1;
  assign o_rf_rdata_s1          = i_rf_rdata_enc_s1;

  assign o_wb_mem_adr_scr_s1    = i_wb_mem_adr_s1;
  assign o_wb_mem_dat_enc_s1    = i_wb_mem_dat_s1     ^ o_wb_mem_adr_scr_s1;
  assign o_wb_mem_rdt_s1        = i_wb_mem_rdt_enc_s1 ^ o_wb_mem_adr_scr_s1;
`endif

endmodule
module sec(
  input  wire [1:0]  i_key_enc_rf,
  input  wire [31:0] i_key_enc_ram,
  input  wire [8:0]  i_key_scr_rf,
  input  wire [31:0] i_key_scr_ram,
`ifndef RTL
  input  wire [8:0]  i_rf_waddr_s1,
  input  wire [8:0]  i_rf_raddr_s1,
  input  wire [1:0]  i_rf_wdata_s1,
  input  wire [1:0]  i_rf_rdata_enc_s1,
  output wire [8:0]  o_rf_waddr_scr_s1,
  output wire [8:0]  o_rf_raddr_scr_s1,
  output wire [1:0]  o_rf_wdata_enc_s1,
  output wire [1:0]  o_rf_rdata_s1,
  input  wire [31:0] i_wb_mem_adr_s1,
  input  wire [31:0] i_wb_mem_dat_s1,
  input  wire [31:0] i_wb_mem_rdt_enc_s1,
  output wire [31:0] o_wb_mem_adr_scr_s1,
  output wire [31:0] o_wb_mem_dat_enc_s1,
  output wire [31:0] o_wb_mem_rdt_s1,
`endif
  input  wire [8:0]  i_rf_waddr,
  input  wire [8:0]  i_rf_raddr,
  input  wire [1:0]  i_rf_wdata,
  input  wire [1:0]  i_rf_rdata_enc,
  output wire [8:0]  o_rf_waddr_scr,
  output wire [8:0]  o_rf_raddr_scr,
  output wire [1:0]  o_rf_wdata_enc,
  output wire [1:0]  o_rf_rdata,
  input  wire [31:0] i_wb_mem_adr,
  input  wire [31:0] i_wb_mem_dat,
  input  wire [31:0] i_wb_mem_rdt_enc,
  output wire [31:0] o_wb_mem_adr_scr,
  output wire [31:0] o_wb_mem_dat_enc,
  output wire [31:0] o_wb_mem_rdt);




  assign o_rf_waddr_scr      = i_rf_waddr       ^ i_key_scr_rf;
  assign o_rf_raddr_scr      = i_rf_raddr       ^ i_key_scr_rf;
  assign o_rf_wdata_enc      = i_rf_wdata       ^ i_key_enc_rf;
  assign o_rf_rdata          = i_rf_rdata_enc   ^ i_key_enc_rf;

  assign o_wb_mem_adr_scr    = i_wb_mem_adr     ^ i_key_scr_ram;
  assign o_wb_mem_dat_enc    = i_wb_mem_dat     ^ i_key_enc_ram ^ o_wb_mem_adr_scr;
  assign o_wb_mem_rdt        = i_wb_mem_rdt_enc ^ i_key_enc_ram ^ o_wb_mem_adr_scr;

`ifndef RTL
  assign o_rf_waddr_scr_s1      = i_rf_waddr_s1;
  assign o_rf_raddr_scr_s1      = i_rf_raddr_s1;
  assign o_rf_wdata_enc_s1      = i_rf_wdata_s1;
  assign o_rf_rdata_s1          = i_rf_rdata_enc_s1;

  assign o_wb_mem_adr_scr_s1    = i_wb_mem_adr_s1;
  assign o_wb_mem_dat_enc_s1    = i_wb_mem_dat_s1     ^ o_wb_mem_adr_scr_s1;
  assign o_wb_mem_rdt_s1        = i_wb_mem_rdt_enc_s1 ^ o_wb_mem_adr_scr_s1;
`endif

endmodule