data/full_repos/permissive/528147991/scr/PC.v
1: b'%Warning-WIDTH: data/full_repos/permissive/528147991/scr/PC.v:17: Operator ADD expects 32 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n                                                                : ... In instance PC\n   addr <= addr + $signed(bOff);\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module PC(clk, jump, branch, jVal, bOff, addr);

	input clk;
	input jump, branch;
	
	input [15:0] bOff;
	input [31:0] jVal;
	
	output reg [31:0] addr;
	
	always @ (posedge clk )
	begin
		
		if (jump)
			addr <= jVal;
		else if (branch)
			addr <= addr + $signed(bOff);
		else
			addr <= addr + 1;
			
	end
endmodule
module PC(clk, jump, branch, jVal, bOff, addr);


	input clk;
	input jump, branch;
	
	input [15:0] bOff;
	input [31:0] jVal;
	
	output reg [31:0] addr;
	
	always @ (posedge clk )
	begin
		
		if (jump)
			addr <= jVal;
		else if (branch)
			addr <= addr + $signed(bOff);
		else
			addr <= addr + 1;
			
	end
endmodule