data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld/ps_cpld_regs.v
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld/ps_cpld_regs.v:49: Cannot find include file: regmap/constants_regmap_utils.vh\n`include "regmap/constants_regmap_utils.vh" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld,data/full_repos/permissive/447976230/regmap/constants_regmap_utils.vh\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld,data/full_repos/permissive/447976230/regmap/constants_regmap_utils.vh.v\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld,data/full_repos/permissive/447976230/regmap/constants_regmap_utils.vh.sv\n             regmap/constants_regmap_utils.vh\n             regmap/constants_regmap_utils.vh.v\n             regmap/constants_regmap_utils.vh.sv\n             obj_dir/regmap/constants_regmap_utils.vh\n             obj_dir/regmap/constants_regmap_utils.vh.v\n             obj_dir/regmap/constants_regmap_utils.vh.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld/ps_cpld_regs.v:50: Cannot find include file: regmap/ps_cpld_base_regmap_utils.vh\n`include "regmap/ps_cpld_base_regmap_utils.vh" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld/ps_cpld_regs.v:51: Cannot find include file: ../../../lib/rfnoc/core/ctrlport.vh\n`include "../../../lib/rfnoc/core/ctrlport.vh" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module ps_cpld_regs #(
  parameter BASE_ADDRESS = 0
) (
  input wire ctrlport_clk,
  input wire ctrlport_rst,


  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [31:0] s_ctrlport_req_data,

  output reg         s_ctrlport_resp_ack,
  output reg  [ 1:0] s_ctrlport_resp_status,
  output reg  [31:0] s_ctrlport_resp_data,


  output reg  [ 1:0] db_clk_enable      = 2'b00,
  output reg  [ 1:0] db_reset           = 2'b11,
  output reg         pll_ref_clk_enable = 1'b0,

  output reg  [11:0] dio_direction_a    = 12'b0,
  output reg  [11:0] dio_direction_b    = 12'b0,

  output reg  [39:0] serial_num         = 40'b0,
  output reg         cmi_ready          = 1'b0,
  input  wire        cmi_other_side_detected
);

`include "regmap/constants_regmap_utils.vh"
`include "regmap/ps_cpld_base_regmap_utils.vh"
`include "../../../lib/rfnoc/core/ctrlport.vh"





localparam NUM_ADDRESSES = 64;
wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) &&
                        (s_ctrlport_req_addr < BASE_ADDRESS + NUM_ADDRESSES);





reg [SCRATCH_REGISTER_SIZE-1:0] scratch_reg;





always @(posedge ctrlport_clk) begin

  if (ctrlport_rst) begin
    scratch_reg             <= 0;
    db_clk_enable           <= 2'b00;
    db_reset                <= 2'b11;
    pll_ref_clk_enable      <= 1'b0;
    dio_direction_a         <= {DIO_DIRECTION_A_SIZE{1'b0}};
    dio_direction_b         <= {DIO_DIRECTION_B_SIZE{1'b0}};
    s_ctrlport_resp_ack     <= 1'b0;
    s_ctrlport_resp_data    <= {CTRLPORT_ADDR_W {1'bx}};
    s_ctrlport_resp_status  <= CTRL_STS_OKAY;


  end else begin
    if (s_ctrlport_req_wr) begin

      s_ctrlport_resp_ack    <= 1'b1;
      s_ctrlport_resp_data   <= {CTRLPORT_ADDR_W {1'bx}};
      s_ctrlport_resp_status <= CTRL_STS_OKAY;

      case (s_ctrlport_req_addr)
        BASE_ADDRESS + SCRATCH_REGISTER:
          scratch_reg <= s_ctrlport_req_data;

        BASE_ADDRESS + PL_DB_REGISTER: begin
          if (s_ctrlport_req_data[DISABLE_CLOCK_DB0]) begin
            db_clk_enable[0] <= 1'b0;
          end else if (s_ctrlport_req_data[ENABLE_CLOCK_DB0]) begin
            db_clk_enable[0] <= 1'b1;
          end
          if (s_ctrlport_req_data[DISABLE_CLOCK_DB1]) begin
            db_clk_enable[1] <= 1'b0;
          end else if (s_ctrlport_req_data[ENABLE_CLOCK_DB1]) begin
            db_clk_enable[1] <= 1'b1;
          end
          if (s_ctrlport_req_data[DISABLE_PLL_REF_CLOCK]) begin
            pll_ref_clk_enable <= 1'b0;
          end else if (s_ctrlport_req_data[ENABLE_PLL_REF_CLOCK]) begin
            pll_ref_clk_enable <= 1'b1;
          end
          if (s_ctrlport_req_data[ASSERT_RESET_DB0]) begin
            db_reset[0] <= 1'b1;
          end else if (s_ctrlport_req_data[RELEASE_RESET_DB0]) begin
            db_reset[0] <= 1'b0;
          end
          if (s_ctrlport_req_data[ASSERT_RESET_DB1]) begin
            db_reset[1] <= 1'b1;
          end else if (s_ctrlport_req_data[RELEASE_RESET_DB1]) begin
            db_reset[1] <= 1'b0;
          end
        end

        BASE_ADDRESS + DIO_DIRECTION_REGISTER: begin
          dio_direction_a <= s_ctrlport_req_data[DIO_DIRECTION_A_MSB:DIO_DIRECTION_A];
          dio_direction_b <= s_ctrlport_req_data[DIO_DIRECTION_B_MSB:DIO_DIRECTION_B];
        end

        BASE_ADDRESS + SERIAL_NUM_LOW_REG: begin
          serial_num[31:0] <= s_ctrlport_req_data;
        end

        BASE_ADDRESS + SERIAL_NUM_HIGH_REG: begin
          serial_num[39:32] <= s_ctrlport_req_data[SERIAL_NUM_HIGH_REG_SIZE-1:0];
        end

        BASE_ADDRESS + CMI_CONTROL_STATUS: begin
          cmi_ready <= s_ctrlport_req_data[CMI_READY];
        end


        default: begin
          if (address_in_range) begin
            s_ctrlport_resp_status <= CTRL_STS_CMDERR;


          end else begin
            s_ctrlport_resp_ack <= 1'b0;
          end
        end
      endcase


    end else if (s_ctrlport_req_rd) begin

      s_ctrlport_resp_ack     <= 1'b1;
      s_ctrlport_resp_status  <= CTRL_STS_OKAY;
      s_ctrlport_resp_data    <= {CTRLPORT_DATA_W {1'b0}};

      case (s_ctrlport_req_addr)
        BASE_ADDRESS + SIGNATURE_REGISTER:
          s_ctrlport_resp_data <= PS_CPLD_SIGNATURE;

        BASE_ADDRESS + REVISION_REGISTER:
          s_ctrlport_resp_data <= CPLD_REVISION;

        BASE_ADDRESS + OLDEST_COMPATIBLE_REVISION_REGISTER:
          s_ctrlport_resp_data <= OLDEST_CPLD_REVISION;

        BASE_ADDRESS + SCRATCH_REGISTER:
          s_ctrlport_resp_data <= scratch_reg;

        BASE_ADDRESS + GIT_HASH_REGISTER:
          `ifdef GIT_HASH
            s_ctrlport_resp_data <= `GIT_HASH;
          `else
            s_ctrlport_resp_data <= 32'hDEADBEEF;
          `endif

        BASE_ADDRESS + PL_DB_REGISTER: begin
          s_ctrlport_resp_data[DB0_CLOCK_ENABLED]     <= db_clk_enable[0];
          s_ctrlport_resp_data[DB1_CLOCK_ENABLED]     <= db_clk_enable[1];
          s_ctrlport_resp_data[PLL_REF_CLOCK_ENABLED] <= pll_ref_clk_enable;
          s_ctrlport_resp_data[DB0_RESET_ASSERTED]    <= db_reset[0];
          s_ctrlport_resp_data[DB1_RESET_ASSERTED]    <= db_reset[1];
        end

        BASE_ADDRESS + DIO_DIRECTION_REGISTER: begin
          s_ctrlport_resp_data[DIO_DIRECTION_A_MSB:DIO_DIRECTION_A] <= dio_direction_a;
          s_ctrlport_resp_data[DIO_DIRECTION_B_MSB:DIO_DIRECTION_B] <= dio_direction_b;
        end

        BASE_ADDRESS + SERIAL_NUM_LOW_REG: begin
          s_ctrlport_resp_data <= serial_num[31:0];
        end

        BASE_ADDRESS + SERIAL_NUM_HIGH_REG: begin
          s_ctrlport_resp_data[SERIAL_NUM_HIGH_REG_SIZE-1:0] <= serial_num[39:32];
        end

        BASE_ADDRESS + CMI_CONTROL_STATUS: begin
          s_ctrlport_resp_data[CMI_READY] <= cmi_ready;
          s_ctrlport_resp_data[OTHER_SIDE_DETECTED] <= cmi_other_side_detected;
        end


        default: begin
          s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'bx}};
          if (address_in_range) begin
            s_ctrlport_resp_status <= CTRL_STS_CMDERR;


          end else begin
            s_ctrlport_resp_ack <= 1'b0;
          end
        end
      endcase


    end else begin
      s_ctrlport_resp_ack <= 1'b0;
    end
  end
end

endmodule
module ps_cpld_regs #(
  parameter BASE_ADDRESS = 0
) (
  input wire ctrlport_clk,
  input wire ctrlport_rst,


  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [31:0] s_ctrlport_req_data,

  output reg         s_ctrlport_resp_ack,
  output reg  [ 1:0] s_ctrlport_resp_status,
  output reg  [31:0] s_ctrlport_resp_data,


  output reg  [ 1:0] db_clk_enable      = 2'b00,
  output reg  [ 1:0] db_reset           = 2'b11,
  output reg         pll_ref_clk_enable = 1'b0,

  output reg  [11:0] dio_direction_a    = 12'b0,
  output reg  [11:0] dio_direction_b    = 12'b0,

  output reg  [39:0] serial_num         = 40'b0,
  output reg         cmi_ready          = 1'b0,
  input  wire        cmi_other_side_detected
);


`include "regmap/constants_regmap_utils.vh"
`include "regmap/ps_cpld_base_regmap_utils.vh"
`include "../../../lib/rfnoc/core/ctrlport.vh"





localparam NUM_ADDRESSES = 64;
wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) &&
                        (s_ctrlport_req_addr < BASE_ADDRESS + NUM_ADDRESSES);





reg [SCRATCH_REGISTER_SIZE-1:0] scratch_reg;





always @(posedge ctrlport_clk) begin

  if (ctrlport_rst) begin
    scratch_reg             <= 0;
    db_clk_enable           <= 2'b00;
    db_reset                <= 2'b11;
    pll_ref_clk_enable      <= 1'b0;
    dio_direction_a         <= {DIO_DIRECTION_A_SIZE{1'b0}};
    dio_direction_b         <= {DIO_DIRECTION_B_SIZE{1'b0}};
    s_ctrlport_resp_ack     <= 1'b0;
    s_ctrlport_resp_data    <= {CTRLPORT_ADDR_W {1'bx}};
    s_ctrlport_resp_status  <= CTRL_STS_OKAY;


  end else begin
    if (s_ctrlport_req_wr) begin

      s_ctrlport_resp_ack    <= 1'b1;
      s_ctrlport_resp_data   <= {CTRLPORT_ADDR_W {1'bx}};
      s_ctrlport_resp_status <= CTRL_STS_OKAY;

      case (s_ctrlport_req_addr)
        BASE_ADDRESS + SCRATCH_REGISTER:
          scratch_reg <= s_ctrlport_req_data;

        BASE_ADDRESS + PL_DB_REGISTER: begin
          if (s_ctrlport_req_data[DISABLE_CLOCK_DB0]) begin
            db_clk_enable[0] <= 1'b0;
          end else if (s_ctrlport_req_data[ENABLE_CLOCK_DB0]) begin
            db_clk_enable[0] <= 1'b1;
          end
          if (s_ctrlport_req_data[DISABLE_CLOCK_DB1]) begin
            db_clk_enable[1] <= 1'b0;
          end else if (s_ctrlport_req_data[ENABLE_CLOCK_DB1]) begin
            db_clk_enable[1] <= 1'b1;
          end
          if (s_ctrlport_req_data[DISABLE_PLL_REF_CLOCK]) begin
            pll_ref_clk_enable <= 1'b0;
          end else if (s_ctrlport_req_data[ENABLE_PLL_REF_CLOCK]) begin
            pll_ref_clk_enable <= 1'b1;
          end
          if (s_ctrlport_req_data[ASSERT_RESET_DB0]) begin
            db_reset[0] <= 1'b1;
          end else if (s_ctrlport_req_data[RELEASE_RESET_DB0]) begin
            db_reset[0] <= 1'b0;
          end
          if (s_ctrlport_req_data[ASSERT_RESET_DB1]) begin
            db_reset[1] <= 1'b1;
          end else if (s_ctrlport_req_data[RELEASE_RESET_DB1]) begin
            db_reset[1] <= 1'b0;
          end
        end

        BASE_ADDRESS + DIO_DIRECTION_REGISTER: begin
          dio_direction_a <= s_ctrlport_req_data[DIO_DIRECTION_A_MSB:DIO_DIRECTION_A];
          dio_direction_b <= s_ctrlport_req_data[DIO_DIRECTION_B_MSB:DIO_DIRECTION_B];
        end

        BASE_ADDRESS + SERIAL_NUM_LOW_REG: begin
          serial_num[31:0] <= s_ctrlport_req_data;
        end

        BASE_ADDRESS + SERIAL_NUM_HIGH_REG: begin
          serial_num[39:32] <= s_ctrlport_req_data[SERIAL_NUM_HIGH_REG_SIZE-1:0];
        end

        BASE_ADDRESS + CMI_CONTROL_STATUS: begin
          cmi_ready <= s_ctrlport_req_data[CMI_READY];
        end


        default: begin
          if (address_in_range) begin
            s_ctrlport_resp_status <= CTRL_STS_CMDERR;


          end else begin
            s_ctrlport_resp_ack <= 1'b0;
          end
        end
      endcase


    end else if (s_ctrlport_req_rd) begin

      s_ctrlport_resp_ack     <= 1'b1;
      s_ctrlport_resp_status  <= CTRL_STS_OKAY;
      s_ctrlport_resp_data    <= {CTRLPORT_DATA_W {1'b0}};

      case (s_ctrlport_req_addr)
        BASE_ADDRESS + SIGNATURE_REGISTER:
          s_ctrlport_resp_data <= PS_CPLD_SIGNATURE;

        BASE_ADDRESS + REVISION_REGISTER:
          s_ctrlport_resp_data <= CPLD_REVISION;

        BASE_ADDRESS + OLDEST_COMPATIBLE_REVISION_REGISTER:
          s_ctrlport_resp_data <= OLDEST_CPLD_REVISION;

        BASE_ADDRESS + SCRATCH_REGISTER:
          s_ctrlport_resp_data <= scratch_reg;

        BASE_ADDRESS + GIT_HASH_REGISTER:
          `ifdef GIT_HASH
            s_ctrlport_resp_data <= `GIT_HASH;
          `else
            s_ctrlport_resp_data <= 32'hDEADBEEF;
          `endif

        BASE_ADDRESS + PL_DB_REGISTER: begin
          s_ctrlport_resp_data[DB0_CLOCK_ENABLED]     <= db_clk_enable[0];
          s_ctrlport_resp_data[DB1_CLOCK_ENABLED]     <= db_clk_enable[1];
          s_ctrlport_resp_data[PLL_REF_CLOCK_ENABLED] <= pll_ref_clk_enable;
          s_ctrlport_resp_data[DB0_RESET_ASSERTED]    <= db_reset[0];
          s_ctrlport_resp_data[DB1_RESET_ASSERTED]    <= db_reset[1];
        end

        BASE_ADDRESS + DIO_DIRECTION_REGISTER: begin
          s_ctrlport_resp_data[DIO_DIRECTION_A_MSB:DIO_DIRECTION_A] <= dio_direction_a;
          s_ctrlport_resp_data[DIO_DIRECTION_B_MSB:DIO_DIRECTION_B] <= dio_direction_b;
        end

        BASE_ADDRESS + SERIAL_NUM_LOW_REG: begin
          s_ctrlport_resp_data <= serial_num[31:0];
        end

        BASE_ADDRESS + SERIAL_NUM_HIGH_REG: begin
          s_ctrlport_resp_data[SERIAL_NUM_HIGH_REG_SIZE-1:0] <= serial_num[39:32];
        end

        BASE_ADDRESS + CMI_CONTROL_STATUS: begin
          s_ctrlport_resp_data[CMI_READY] <= cmi_ready;
          s_ctrlport_resp_data[OTHER_SIDE_DETECTED] <= cmi_other_side_detected;
        end


        default: begin
          s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'bx}};
          if (address_in_range) begin
            s_ctrlport_resp_status <= CTRL_STS_CMDERR;


          end else begin
            s_ctrlport_resp_ack <= 1'b0;
          end
        end
      endcase


    end else begin
      s_ctrlport_resp_ack <= 1'b0;
    end
  end
end

endmodule