data/full_repos/permissive/499960660/verilog/dv/kairos/kairos_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/499960660/verilog/dv/kairos/kairos_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n always #12.5 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/499960660/verilog/dv/kairos/kairos_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n always #10 clk = ~clk;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499960660/verilog/dv/kairos/kairos_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n  #350\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499960660/verilog/dv/kairos/kairos_tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n        #150\n        ^\n%Error: data/full_repos/permissive/499960660/verilog/dv/kairos/kairos_tb.v:171: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("kairos.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/499960660/verilog/dv/kairos/kairos_tb.v:172: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, kairos_tb);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/499960660/verilog/dv/kairos/kairos_tb.v:176: syntax error, unexpected \'@\'\n   repeat (1000) @(posedge clock);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/499960660/verilog/dv/kairos/kairos_tb.v:192: Unsupported: Ignoring delay on this delayed statement.\n  #2000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499960660/verilog/dv/kairos/kairos_tb.v:194: Unsupported: Ignoring delay on this delayed statement.\n  #300000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499960660/verilog/dv/kairos/kairos_tb.v:203: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499960660/verilog/dv/kairos/kairos_tb.v:205: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499960660/verilog/dv/kairos/kairos_tb.v:207: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499960660/verilog/dv/kairos/kairos_tb.v:209: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: Exiting due to 3 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module kairos_tb;
	reg clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

	wire gpio;
	wire [37:0] mprj_io;





	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
	end

	localparam STANDBY = 2'd0;
	localparam STEP1   = 2'd1;
	localparam STEP2   = 2'd2;
	localparam STEP3   = 2'd3;

    reg                     [1:0] state;
    reg                    [11:0] input_adr_r;
    reg                           counter;
    reg                           fsm_start;
    integer                       file;

    reg  [`NUM_CONFIGS-1:0][15:0] config_r;
    reg                    [31:0] instr_memory[`NUM_INSTRUCTIONS-1:0];
    reg                    [31:0] input_memory[`TOTAL_INPUT_SIZE-1:0];

    reg                           clk;
    reg                           rst_n;

    wire                          input_rdy_w;
    reg                           input_vld_r;
    reg   [`INPUT_FIFO_WIDTH-1:0] input_data_r;

    reg                           output_rdy_r;
    wire                          output_vld_w;
    wire [`OUTPUT_FIFO_WIDTH-1:0] output_data_w;


    assign mprj_io[37]   = clk;
    assign mprj_io[36]   = rst_n;
    assign mprj_io[15:0] = input_data_r;
    assign mprj_io[16]   = input_vld_r;
    assign mprj_io[17]   = output_rdy_r;


    assign output_data_w = mprj_io[33:18];
    assign output_vld_w  = mprj_io[34];
    assign input_rdy_w   = mprj_io[35] & fsm_start;

	always #10 clk = ~clk;

	initial begin
        $readmemb("instr_data.txt", instr_memory);
        $readmemh("input_data.txt", input_memory);
        file = $fopen("output.txt", "w");

		clk          <= 0;
        rst_n        <= 0;

        state        <= STANDBY;
        counter      <= 0;
        fsm_start    <= 0;

        input_adr_r  <= 0;
        input_vld_r  <= 0;
        input_data_r <= 0;
        output_rdy_r <= 1;

        config_r[0]  <= `NUM_INSTRUCTIONS - 1;
        config_r[1]  <= `INPUT_DATA_SIZE - 1;
        config_r[2]  <= 16'h7d0;
        config_r[3]  <= `OUTPUT_DATA_SIZE - 1;
        config_r[4]  <= 16'h7e8;

		#350
        rst_n        <= 1;
        #150
        fsm_start    <= 1;
    end

    always @(posedge clk) begin
        case (state)
            STANDBY: begin
                if (input_rdy_w) begin
                    input_data_r <= config_r[input_adr_r]; 
                    input_adr_r  <= input_adr_r + 1;
                    input_vld_r  <= 1;

                    if (input_adr_r == `NUM_CONFIGS - 1) begin
                        state       <= STEP1;
                        input_adr_r <= 0;
                    end
                end
            end

            STEP1: begin
                if (input_rdy_w) begin
                    input_data_r <= instr_memory[input_adr_r][counter*16+:16]; 
                    input_adr_r  <= (counter == 1) ? input_adr_r + 1 : input_adr_r;
                    input_vld_r  <= (input_adr_r < `NUM_INSTRUCTIONS);
                    counter      <= counter + 1;

                    if (input_adr_r == `NUM_INSTRUCTIONS) begin
                        state       <= STEP2;
                        input_adr_r <= 0;
                        counter     <= 0;
                    end
                end
            end

            STEP2: begin
                if (input_rdy_w) begin
                    input_data_r <= input_memory[input_adr_r][counter*16+:16]; 
                    input_adr_r  <= (counter == 1) ? input_adr_r + 1 : input_adr_r;
                    input_vld_r  <= 1;
                    counter      <= counter + 1;

                    if (input_adr_r == `TOTAL_INPUT_SIZE) begin
                        state       <= STEP3;
                        input_vld_r <= 0;
                    end
                end
            end
        endcase

        if (output_vld_w) begin
            $fwrite(file, "%h\n", output_data_w);
        end
    end

	initial begin
		$dumpfile("kairos.vcd");
		$dumpvars(0, kairos_tb);


		repeat (25) begin
			repeat (1000) @(posedge clock);

		end
		$display("%c[1;31m",27);
		`ifdef GL
			$display ("Monitor: Timeout, Test Mega-Project IO Ports (GL) Completed");
		`else
			$display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Completed");
		`endif
		$display("%c[0m",27);
		$finish;
	end

	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#300000;
		CSB = 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3;
	wire VDD1V8;
	wire VSS;
	
	assign VDD3V3 = power1;
	assign VDD1V8 = power2;
	assign VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda1_2  (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock    (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("kairos.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule
module kairos_tb;

	reg clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

	wire gpio;
	wire [37:0] mprj_io;





	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
	end

	localparam STANDBY = 2'd0;
	localparam STEP1   = 2'd1;
	localparam STEP2   = 2'd2;
	localparam STEP3   = 2'd3;

    reg                     [1:0] state;
    reg                    [11:0] input_adr_r;
    reg                           counter;
    reg                           fsm_start;
    integer                       file;

    reg  [`NUM_CONFIGS-1:0][15:0] config_r;
    reg                    [31:0] instr_memory[`NUM_INSTRUCTIONS-1:0];
    reg                    [31:0] input_memory[`TOTAL_INPUT_SIZE-1:0];

    reg                           clk;
    reg                           rst_n;

    wire                          input_rdy_w;
    reg                           input_vld_r;
    reg   [`INPUT_FIFO_WIDTH-1:0] input_data_r;

    reg                           output_rdy_r;
    wire                          output_vld_w;
    wire [`OUTPUT_FIFO_WIDTH-1:0] output_data_w;


    assign mprj_io[37]   = clk;
    assign mprj_io[36]   = rst_n;
    assign mprj_io[15:0] = input_data_r;
    assign mprj_io[16]   = input_vld_r;
    assign mprj_io[17]   = output_rdy_r;


    assign output_data_w = mprj_io[33:18];
    assign output_vld_w  = mprj_io[34];
    assign input_rdy_w   = mprj_io[35] & fsm_start;

	always #10 clk = ~clk;

	initial begin
        $readmemb("instr_data.txt", instr_memory);
        $readmemh("input_data.txt", input_memory);
        file = $fopen("output.txt", "w");

		clk          <= 0;
        rst_n        <= 0;

        state        <= STANDBY;
        counter      <= 0;
        fsm_start    <= 0;

        input_adr_r  <= 0;
        input_vld_r  <= 0;
        input_data_r <= 0;
        output_rdy_r <= 1;

        config_r[0]  <= `NUM_INSTRUCTIONS - 1;
        config_r[1]  <= `INPUT_DATA_SIZE - 1;
        config_r[2]  <= 16'h7d0;
        config_r[3]  <= `OUTPUT_DATA_SIZE - 1;
        config_r[4]  <= 16'h7e8;

		#350
        rst_n        <= 1;
        #150
        fsm_start    <= 1;
    end

    always @(posedge clk) begin
        case (state)
            STANDBY: begin
                if (input_rdy_w) begin
                    input_data_r <= config_r[input_adr_r]; 
                    input_adr_r  <= input_adr_r + 1;
                    input_vld_r  <= 1;

                    if (input_adr_r == `NUM_CONFIGS - 1) begin
                        state       <= STEP1;
                        input_adr_r <= 0;
                    end
                end
            end

            STEP1: begin
                if (input_rdy_w) begin
                    input_data_r <= instr_memory[input_adr_r][counter*16+:16]; 
                    input_adr_r  <= (counter == 1) ? input_adr_r + 1 : input_adr_r;
                    input_vld_r  <= (input_adr_r < `NUM_INSTRUCTIONS);
                    counter      <= counter + 1;

                    if (input_adr_r == `NUM_INSTRUCTIONS) begin
                        state       <= STEP2;
                        input_adr_r <= 0;
                        counter     <= 0;
                    end
                end
            end

            STEP2: begin
                if (input_rdy_w) begin
                    input_data_r <= input_memory[input_adr_r][counter*16+:16]; 
                    input_adr_r  <= (counter == 1) ? input_adr_r + 1 : input_adr_r;
                    input_vld_r  <= 1;
                    counter      <= counter + 1;

                    if (input_adr_r == `TOTAL_INPUT_SIZE) begin
                        state       <= STEP3;
                        input_vld_r <= 0;
                    end
                end
            end
        endcase

        if (output_vld_w) begin
            $fwrite(file, "%h\n", output_data_w);
        end
    end

	initial begin
		$dumpfile("kairos.vcd");
		$dumpvars(0, kairos_tb);


		repeat (25) begin
			repeat (1000) @(posedge clock);

		end
		$display("%c[1;31m",27);
		`ifdef GL
			$display ("Monitor: Timeout, Test Mega-Project IO Ports (GL) Completed");
		`else
			$display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Completed");
		`endif
		$display("%c[0m",27);
		$finish;
	end

	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#300000;
		CSB = 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3;
	wire VDD1V8;
	wire VSS;
	
	assign VDD3V3 = power1;
	assign VDD1V8 = power2;
	assign VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda1_2  (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock    (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("kairos.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule