data/full_repos/permissive/464991782/TestBenchALU1.v
1: b'%Error: data/full_repos/permissive/464991782/TestBenchALU1.v:25: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("TestBenchALU1.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/464991782/TestBenchALU1.v:26: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0,TestBenchALU1);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/464991782/TestBenchALU1.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #10 {S1, S0, A, B, CarryIn} = i;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TestBenchALU1();
reg S1, S0, A, B, CarryIn;
wire CarryOut, F;

ALU1 ALU(F, CarryOut, S1, S0, A, B, CarryIn);

integer i;
initial
begin

  $dumpfile("TestBenchALU1.vcd");
  $dumpvars(0,TestBenchALU1);
for (i = 0; i <= 31; i = i + 1)
  begin
    #10 {S1, S0, A, B, CarryIn} = i;
  end
$finish();
end
endmodule
module TestBenchALU1();

reg S1, S0, A, B, CarryIn;
wire CarryOut, F;

ALU1 ALU(F, CarryOut, S1, S0, A, B, CarryIn);

integer i;
initial
begin

  $dumpfile("TestBenchALU1.vcd");
  $dumpvars(0,TestBenchALU1);
for (i = 0; i <= 31; i = i + 1)
  begin
    #10 {S1, S0, A, B, CarryIn} = i;
  end
$finish();
end
endmodule