data/full_repos/permissive/428125225/xianshi.v
1: b'%Warning-WIDTH: data/full_repos/permissive/428125225/xianshi.v:6: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 8 bits.\n                                                                : ... In instance xianshi\nassign d[19:16] =  s_out/100%10; \n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/428125225/xianshi.v:7: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 8 bits.\n                                                                : ... In instance xianshi\nassign d[15:12] =  s_out/10%10; \n                ^\n%Warning-WIDTH: data/full_repos/permissive/428125225/xianshi.v:8: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 8 bits.\n                                                                : ... In instance xianshi\nassign d[11:8]  =  s_out%10; \n                ^\n%Warning-WIDTH: data/full_repos/permissive/428125225/xianshi.v:9: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 8 bits.\n                                                                : ... In instance xianshi\nassign d[7:4]   =  s_out*10%10; \n                ^\n%Warning-WIDTH: data/full_repos/permissive/428125225/xianshi.v:10: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 or 8 bits.\n                                                                 : ... In instance xianshi\nassign d[3:0]   =  s_out*100%10; \n                ^\n%Error: Exiting due to 5 warning(s)\n'
module xianshi(
output [19:0] d,
input [7:0]  s_out
);

assign d[19:16] =  s_out/100%10;
assign d[15:12] =  s_out/10%10;
assign d[11:8]  =  s_out%10;
assign d[7:4]   =  s_out*10%10;
assign d[3:0]   =  s_out*100%10;
   
endmodule
module xianshi(
output [19:0] d,
input [7:0]  s_out
);


assign d[19:16] =  s_out/100%10;
assign d[15:12] =  s_out/10%10;
assign d[11:8]  =  s_out%10;
assign d[7:4]   =  s_out*10%10;
assign d[3:0]   =  s_out*100%10;
   
endmodule