data/full_repos/permissive/453650571/Project_files/data_path.v
data/verilator_xmls/2fe5e599-a4a5-46ec-8eeb-20575229a8e2.xml
module data_path(
clk , rst_n , sel_1 , op  , REG1 , REG2 , ld_1  , ld_2 , data_in , data_out, en
    );
  input clk, rst_n  , sel_1 ,op, ld_1 , ld_2 , en;
  input [3:0] data_in  ;
  output reg [3:0] data_out ;
  reg[3:0] F;
  output reg[3:0] REG1 , REG2 ; 
    

    
    always @ (posedge clk )
  begin 
    if(rst_n)
    begin
    REG1 <= 4'b0000;
    end
    else if (ld_1)
    begin
    if(sel_1)
    begin
    REG1<= data_in ;
    end
    else
    begin
    REG1<= data_out ;
     end
     end
     else
     begin
     REG1<= REG1 ;
     end
    end
    
    

    always @ (posedge clk)
    begin
    if ( rst_n)
    begin
    REG2 <= 4'b0000;
    end
    else if (ld_2)
    begin
    REG2<= data_out ;
    end
    else
    begin
    REG2 <= REG2 ;
    end
    end
    
    

    always@(op or REG1 or REG2 )
    begin
    case(op)
    0: F = REG1 ;
    1: F = REG1 + REG2 ;
    endcase
    end
    

    always @ ( en or F)
    begin
    if (en)
    begin
    data_out = F ;
    end
    else
    begin
    data_out = 4'b0000;
    end
    end
       
endmodule
module data_path(
clk , rst_n , sel_1 , op  , REG1 , REG2 , ld_1  , ld_2 , data_in , data_out, en
    );

  input clk, rst_n  , sel_1 ,op, ld_1 , ld_2 , en;
  input [3:0] data_in  ;
  output reg [3:0] data_out ;
  reg[3:0] F;
  output reg[3:0] REG1 , REG2 ; 
    

    
    always @ (posedge clk )
  begin 
    if(rst_n)
    begin
    REG1 <= 4'b0000;
    end
    else if (ld_1)
    begin
    if(sel_1)
    begin
    REG1<= data_in ;
    end
    else
    begin
    REG1<= data_out ;
     end
     end
     else
     begin
     REG1<= REG1 ;
     end
    end
    
    

    always @ (posedge clk)
    begin
    if ( rst_n)
    begin
    REG2 <= 4'b0000;
    end
    else if (ld_2)
    begin
    REG2<= data_out ;
    end
    else
    begin
    REG2 <= REG2 ;
    end
    end
    
    

    always@(op or REG1 or REG2 )
    begin
    case(op)
    0: F = REG1 ;
    1: F = REG1 + REG2 ;
    endcase
    end
    

    always @ ( en or F)
    begin
    if (en)
    begin
    data_out = F ;
    end
    else
    begin
    data_out = 4'b0000;
    end
    end
       
endmodule