data/full_repos/permissive/461620575/Galaga on FPGA/ALU/hex2seg.v
1: b'%Error: Cannot find file containing module: on\n        ... Looked in:\n             data/full_repos/permissive/461620575/Galaga/on\n             data/full_repos/permissive/461620575/Galaga/on.v\n             data/full_repos/permissive/461620575/Galaga/on.sv\n             on\n             on.v\n             on.sv\n             obj_dir/on\n             obj_dir/on.v\n             obj_dir/on.sv\n%Error: Cannot find file containing module: FPGA/ALU,data/full_repos/permissive/461620575\n%Error: Cannot find file containing module: data/full_repos/permissive/461620575/Galaga\n%Error: Cannot find file containing module: FPGA/ALU/hex2seg.v\n%Error: Exiting due to 4 error(s)\n'
module hex2seg(hex, seg);
	input [3:0] hex;
	output reg [0:6] seg;
	
	always @(hex)
	begin
		case(hex)
		4'b0000: seg = 7'b0000001;
		4'b0001: seg = 7'b1001111;
		4'b0010: seg = 7'b0010010;
		4'b0011: seg = 7'b0000110;
		4'b0100: seg = 7'b1001100;
		4'b0101: seg = 7'b0100100;
		4'b0110: seg = 7'b0100000;
		4'b0111: seg = 7'b0001111;
		4'b1000: seg = 7'b0000000;
		4'b1001: seg = 7'b0001100;
		4'b1010: seg = 7'b0001000;
		4'b1011: seg = 7'b1100000;
		4'b1100: seg = 7'b0110001;
		4'b1101: seg = 7'b1000010;
		4'b1110: seg = 7'b0110000;
		4'b1111: seg = 7'b0111000;		
		endcase
	end
endmodule
module hex2seg(hex, seg);

	input [3:0] hex;
	output reg [0:6] seg;
	
	always @(hex)
	begin
		case(hex)
		4'b0000: seg = 7'b0000001;
		4'b0001: seg = 7'b1001111;
		4'b0010: seg = 7'b0010010;
		4'b0011: seg = 7'b0000110;
		4'b0100: seg = 7'b1001100;
		4'b0101: seg = 7'b0100100;
		4'b0110: seg = 7'b0100000;
		4'b0111: seg = 7'b0001111;
		4'b1000: seg = 7'b0000000;
		4'b1001: seg = 7'b0001100;
		4'b1010: seg = 7'b0001000;
		4'b1011: seg = 7'b1100000;
		4'b1100: seg = 7'b0110001;
		4'b1101: seg = 7'b1000010;
		4'b1110: seg = 7'b0110000;
		4'b1111: seg = 7'b0111000;		
		endcase
	end
endmodule