data/full_repos/permissive/427221126/workspace/mult_booth.sv
data/verilator_xmls/8c0f0c4b-8478-4475-9fde-3cb583000ab9.xml
module rca  (
    input  [31:0] op1,
    input  [31:0] op2,
    input  cin,
    output [31:0] sum,
    output cout
);

wire [32:0] temp;
assign temp[0] = cin;
assign cout = temp[32];

genvar i;
for( i=0; i<32; i=i+1) begin
    full_adder u_full_adder(
        .a      (   op1[i]     ),
        .b      (   op2[i]     ),
        .cin    (   temp[i]    ),
        .cout   (   temp[i+1]  ),
        .s      (   sum[i]     )
    );
end

endmodule
module rca  (
    input  [31:0] op1,
    input  [31:0] op2,
    input  cin,
    output [31:0] sum,
    output cout
);


wire [32:0] temp;
assign temp[0] = cin;
assign cout = temp[32];

genvar i;
for( i=0; i<32; i=i+1) begin
    full_adder u_full_adder(
        .a      (   op1[i]     ),
        .b      (   op2[i]     ),
        .cin    (   temp[i]    ),
        .cout   (   temp[i+1]  ),
        .s      (   sum[i]     )
    );
end

endmodule