data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_dgain.v
1: b'%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_dgain.v:49: Operator GT expects 12 bits on the RHS, but RHS\'s REPLICATE generates 8 bits.\n                                                                                                     : ... In instance isp_dgain\n   data_1 <= data_0[BITS-1+8:4] > {BITS{1\'b1}} ? {BITS{1\'b1}} : data_0[BITS-1+4:4];\n                                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module isp_dgain
#(
	parameter BITS = 8,
	parameter WIDTH = 1280,
	parameter HEIGHT = 960
)
(
	input pclk,
	input rst_n,

	input [7:0] gain,

	input in_href,
	input in_vsync,
	input [BITS-1:0] in_raw,

	output out_href,
	output out_vsync,
	output [BITS-1:0] out_raw
);

	reg [BITS-1+8:0] data_0;
	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n) begin
			data_0 <= 0;
		end
		else begin
			data_0 <= in_raw * gain;
		end
	end

	reg [BITS-1:0] data_1;
	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n) begin
			data_1 <= 0;
		end
		else begin
			data_1 <= data_0[BITS-1+8:4] > {BITS{1'b1}} ? {BITS{1'b1}} : data_0[BITS-1+4:4];
		end
	end

	localparam DLY_CLK = 2;
	reg [DLY_CLK-1:0] href_dly;
	reg [DLY_CLK-1:0] vsync_dly;
	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n) begin
			href_dly <= 0;
			vsync_dly <= 0;
		end
		else begin
			href_dly <= {href_dly[DLY_CLK-2:0], in_href};
			vsync_dly <= {vsync_dly[DLY_CLK-2:0], in_vsync};
		end
	end

	assign out_href = href_dly[DLY_CLK-1];
	assign out_vsync = vsync_dly[DLY_CLK-1];
	assign out_raw = out_href ? data_1 : {BITS{1'b0}};
endmodule
module isp_dgain
#(
	parameter BITS = 8,
	parameter WIDTH = 1280,
	parameter HEIGHT = 960
)
(
	input pclk,
	input rst_n,

	input [7:0] gain,

	input in_href,
	input in_vsync,
	input [BITS-1:0] in_raw,

	output out_href,
	output out_vsync,
	output [BITS-1:0] out_raw
);


	reg [BITS-1+8:0] data_0;
	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n) begin
			data_0 <= 0;
		end
		else begin
			data_0 <= in_raw * gain;
		end
	end

	reg [BITS-1:0] data_1;
	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n) begin
			data_1 <= 0;
		end
		else begin
			data_1 <= data_0[BITS-1+8:4] > {BITS{1'b1}} ? {BITS{1'b1}} : data_0[BITS-1+4:4];
		end
	end

	localparam DLY_CLK = 2;
	reg [DLY_CLK-1:0] href_dly;
	reg [DLY_CLK-1:0] vsync_dly;
	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n) begin
			href_dly <= 0;
			vsync_dly <= 0;
		end
		else begin
			href_dly <= {href_dly[DLY_CLK-2:0], in_href};
			vsync_dly <= {vsync_dly[DLY_CLK-2:0], in_vsync};
		end
	end

	assign out_href = href_dly[DLY_CLK-1];
	assign out_vsync = vsync_dly[DLY_CLK-1];
	assign out_raw = out_href ? data_1 : {BITS{1'b0}};
endmodule