data/full_repos/permissive/485721981/sources/synthesis/sinegen.v
1: b'%Warning-WIDTH: data/full_repos/permissive/485721981/sources/synthesis/sinegen.v:104: Operator ADD expects 19 bits on the RHS, but RHS\'s VARREF \'frq\' generates 16 bits.\n                                                                                    : ... In instance sinegen\n            rAccu <= rAccu + frq;    \n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/485721981/sources/synthesis/sinegen.v:101: Operator GTE expects 32 or 27 bits on the LHS, but LHS\'s VARREF \'rAccu\' generates 19 bits.\n                                                                                    : ... In instance sinegen\n        end else if (rAccu >= C_STEP_INTERVAL) begin\n                           ^~\n%Error: Exiting due to 2 warning(s)\n'
module sinegen # (
        parameter C_CLK_FRQ = 100_000_000
    ) (
        input rstb,
        input clk,
        input [15 : 0] frq,
        output reg [7 : 0] data
    );
    
    





    localparam C_PHASE_STEPS = 256;
    localparam C_PHASE_STEPS_WIDTH = 8;
    

    localparam C_STEP_INTERVAL = C_CLK_FRQ /  (C_PHASE_STEPS);
    localparam C_STEP_INTERVAL_WIDTH = $clog2(C_STEP_INTERVAL);





    


    reg	[7:0] rSine [0 : C_PHASE_STEPS - 1];
    initial $readmemh("sine.mem", rSine, 0, C_PHASE_STEPS - 1);    
    

    reg [C_PHASE_STEPS_WIDTH - 1 : 0] rPhase;
    

    reg [C_STEP_INTERVAL_WIDTH - 1 : 0] rAccu;
    

    reg rPStep;
    
    
    





    always@(posedge clk) begin
        data <= rSine[rPhase];    
    end




    

    always@(posedge clk) begin
        if (rstb == 1'b0) begin
            rAccu <= 0;
        end else if (rAccu >= C_STEP_INTERVAL) begin
            rAccu <= 0;
        end else begin
            rAccu <= rAccu + frq;    
        end
    end 
    

    always@(posedge clk) begin
        if (rstb == 1'b0) begin
            rPhase <= 0;
        end else if (rAccu == 0) begin
            rPhase <= rPhase + 1; 
        end else begin
            rPhase <= rPhase;     
        end
    end 

endmodule
module sinegen # (
        parameter C_CLK_FRQ = 100_000_000
    ) (
        input rstb,
        input clk,
        input [15 : 0] frq,
        output reg [7 : 0] data
    );

    
    





    localparam C_PHASE_STEPS = 256;
    localparam C_PHASE_STEPS_WIDTH = 8;
    

    localparam C_STEP_INTERVAL = C_CLK_FRQ /  (C_PHASE_STEPS);
    localparam C_STEP_INTERVAL_WIDTH = $clog2(C_STEP_INTERVAL);





    


    reg	[7:0] rSine [0 : C_PHASE_STEPS - 1];
    initial $readmemh("sine.mem", rSine, 0, C_PHASE_STEPS - 1);    
    

    reg [C_PHASE_STEPS_WIDTH - 1 : 0] rPhase;
    

    reg [C_STEP_INTERVAL_WIDTH - 1 : 0] rAccu;
    

    reg rPStep;
    
    
    





    always@(posedge clk) begin
        data <= rSine[rPhase];    
    end




    

    always@(posedge clk) begin
        if (rstb == 1'b0) begin
            rAccu <= 0;
        end else if (rAccu >= C_STEP_INTERVAL) begin
            rAccu <= 0;
        end else begin
            rAccu <= rAccu + frq;    
        end
    end 
    

    always@(posedge clk) begin
        if (rstb == 1'b0) begin
            rPhase <= 0;
        end else if (rAccu == 0) begin
            rPhase <= rPhase + 1; 
        end else begin
            rPhase <= rPhase;     
        end
    end 

endmodule