data/full_repos/permissive/455874613/Projects/Module06/MemoryUnit.v
data/verilator_xmls/bcbb853c-b533-42d2-825d-3d1150dfd819.xml
module MemoryUnit (
	input         arst ,
	input         clk  ,
	input         wren ,
	input  [34:0] din  ,
	output reg [34:0] dout
);

	always @(posedge clk or posedge arst) begin
			if(arst) dout<=0;
			else begin
			if(wren) 
				 dout <= din;
			end
		end

endmodule
module MemoryUnit (
	input         arst ,
	input         clk  ,
	input         wren ,
	input  [34:0] din  ,
	output reg [34:0] dout
);


	always @(posedge clk or posedge arst) begin
			if(arst) dout<=0;
			else begin
			if(wren) 
				 dout <= din;
			end
		end

endmodule