data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/MICROBENCHMARKS/bm_base_multiply.v
1: b'%Warning-WIDTH: data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/MICROBENCHMARKS/bm_base_multiply.v:53: Operator AND expects 16 bits on the LHS, but LHS\'s VARREF \'temp_a\' generates 8 bits.\n                                                                                                                                 : ... In instance bm_base_multiply\n out2 <= temp_a & temp_b;\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/MICROBENCHMARKS/bm_base_multiply.v:53: Operator AND expects 16 bits on the RHS, but RHS\'s VARREF \'temp_b\' generates 8 bits.\n                                                                                                                                 : ... In instance bm_base_multiply\n out2 <= temp_a & temp_b;\n                ^\n%Error: Exiting due to 2 warning(s)\n'
module b(clock,
		a_in,
		b_in,
		out);

input	clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
wire [`BITS-1:0] temp;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;

a my_a(clock, a_in, b_in, temp);

always @(posedge clock)
begin
	out <= a_in & temp;
end

endmodule
module b(clock,
		a_in,
		b_in,
		out);


input	clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
wire [`BITS-1:0] temp;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;

a my_a(clock, a_in, b_in, temp);

always @(posedge clock)
begin
	out <= a_in & temp;
end

endmodule