data/full_repos/permissive/455223995/src/slzw_lib.v
1: b'%Error: data/full_repos/permissive/455223995/src/slzw_lib.v:50: syntax error, unexpected byte, expecting IDENTIFIER or \'[\' or do or final\n  input   [7:0] byte,\n                ^~~~\n%Error: data/full_repos/permissive/455223995/src/slzw_lib.v:56: syntax error, unexpected \'[\', expecting "\'{"\nwire [13:0] num1 = {1\'b0, byte[4:0], byte[7:0]};\n                              ^\n%Error: data/full_repos/permissive/455223995/src/slzw_lib.v:62: syntax error, unexpected assign\nassign haddr      = num1 + num2;\n^~~~~~\n%Error: Exiting due to 3 error(s)\n'
module slzw_mem_occupied
#(parameter
   MEMSIZE                     = 10240
)
(
  input             clk,
  input             reset_n,

  input             clr,

  input      [13:0] waddr,
  input      [13:0] raddr,
  input             set,

  output            occupied,
  output            busy
);

localparam  OCCMEMSIZE         = MEMSIZE/32;

reg  [31:0] occmem [0:OCCMEMSIZE-1];
reg         set_last;
reg  [13:0] addr_last;
reg  [31:0] rval;
reg         clr_last;
reg   [8:0] clr_count;

wire        out_of_range       = (waddr > (OCCMEMSIZE[13:0]-14'b1)) ? 1'b1 : 1'b0;

assign      occupied           = rval[waddr[4:0]] | (set_last && (addr_last == waddr)) | out_of_range;
assign      busy               = (clr_count > 9'h000);

always @ (posedge clk `RESET)
begin
  if (reset_n == 1'b0)
  begin
    set_last                   <= 1'b0;
    clr_last                   <= 1'b0;
    clr_count                  <= 9'h000;
  end
  else
  begin

    clr_last                   <= clr;
    set_last                   <= set;
    addr_last                  <= waddr;


    if (!out_of_range)
    begin
      rval                     <= occmem[raddr[13:5]];
    end


    if ((clr && !clr_last && clr_count == 9'h000) || busy)
    begin
      occmem[clr_count]        <= 32'h00000000;
      clr_count                <= clr_count + 9'h001;
      if (clr_count == (OCCMEMSIZE[8:0]-9'd1))
      begin
        clr_count              <= 9'h00;
      end
    end



    else if (set_last && !out_of_range)
    begin
      occmem[addr_last[13:5]]  <= rval | (32'h1 << addr_last[4:0]);
    end
  end
end

endmodule
module slzw_mem_occupied
#(parameter
   MEMSIZE                     = 10240
)
(
  input             clk,
  input             reset_n,

  input             clr,

  input      [13:0] waddr,
  input      [13:0] raddr,
  input             set,

  output            occupied,
  output            busy
);


localparam  OCCMEMSIZE         = MEMSIZE/32;

reg  [31:0] occmem [0:OCCMEMSIZE-1];
reg         set_last;
reg  [13:0] addr_last;
reg  [31:0] rval;
reg         clr_last;
reg   [8:0] clr_count;

wire        out_of_range       = (waddr > (OCCMEMSIZE[13:0]-14'b1)) ? 1'b1 : 1'b0;

assign      occupied           = rval[waddr[4:0]] | (set_last && (addr_last == waddr)) | out_of_range;
assign      busy               = (clr_count > 9'h000);

always @ (posedge clk `RESET)
begin
  if (reset_n == 1'b0)
  begin
    set_last                   <= 1'b0;
    clr_last                   <= 1'b0;
    clr_count                  <= 9'h000;
  end
  else
  begin

    clr_last                   <= clr;
    set_last                   <= set;
    addr_last                  <= waddr;


    if (!out_of_range)
    begin
      rval                     <= occmem[raddr[13:5]];
    end


    if ((clr && !clr_last && clr_count == 9'h000) || busy)
    begin
      occmem[clr_count]        <= 32'h00000000;
      clr_count                <= clr_count + 9'h001;
      if (clr_count == (OCCMEMSIZE[8:0]-9'd1))
      begin
        clr_count              <= 9'h00;
      end
    end



    else if (set_last && !out_of_range)
    begin
      occmem[addr_last[13:5]]  <= rval | (32'h1 << addr_last[4:0]);
    end
  end
end

endmodule