data/full_repos/permissive/493441306/Verilog Language/more_verilog_features/05_adder100i.v
1: b'%Error: Cannot find file containing module: Language/more_verilog_features,data/full_repos/permissive/493441306\n        ... Looked in:\n             data/full_repos/permissive/493441306/Verilog/Language/more_verilog_features,data/full_repos/permissive/493441306\n             data/full_repos/permissive/493441306/Verilog/Language/more_verilog_features,data/full_repos/permissive/493441306.v\n             data/full_repos/permissive/493441306/Verilog/Language/more_verilog_features,data/full_repos/permissive/493441306.sv\n             Language/more_verilog_features,data/full_repos/permissive/493441306\n             Language/more_verilog_features,data/full_repos/permissive/493441306.v\n             Language/more_verilog_features,data/full_repos/permissive/493441306.sv\n             obj_dir/Language/more_verilog_features,data/full_repos/permissive/493441306\n             obj_dir/Language/more_verilog_features,data/full_repos/permissive/493441306.v\n             obj_dir/Language/more_verilog_features,data/full_repos/permissive/493441306.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/493441306/Verilog\n%Error: Cannot find file containing module: Language/more_verilog_features/05_adder100i.v\n%Error: Exiting due to 3 error(s)\n'
module top_module( 
    input [99:0] a, b,
    input cin,
    output [99:0] cout,
    output [99:0] sum );
    
    always@(*) begin
        {cout[0],sum[0]} = a[0] + b[0] + cin;
        for(int i=1;i<100;i++) begin
            {cout[i],sum[i]} = a[i] + b[i] + cout[i-1];
        end
    end

endmodule
module top_module( 
    input [99:0] a, b,
    input cin,
    output [99:0] cout,
    output [99:0] sum );

    
    always@(*) begin
        {cout[0],sum[0]} = a[0] + b[0] + cin;
        for(int i=1;i<100;i++) begin
            {cout[i],sum[i]} = a[i] + b[i] + cout[i-1];
        end
    end

endmodule