data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/include/riscv_pkg.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/include/riscv_pkg.sv:315: Operator OR expects 64 bits on the RHS, but RHS\'s VARREF \'IRQ_S_SOFT\' generates 32 bits.\n    localparam logic [XLEN-1:0] S_SW_INTERRUPT    = (1 << (XLEN-1)) | IRQ_S_SOFT;\n                                                                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/include/riscv_pkg.sv:316: Operator OR expects 64 bits on the RHS, but RHS\'s VARREF \'IRQ_M_SOFT\' generates 32 bits.\n    localparam logic [XLEN-1:0] M_SW_INTERRUPT    = (1 << (XLEN-1)) | IRQ_M_SOFT;\n                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/include/riscv_pkg.sv:317: Operator OR expects 64 bits on the RHS, but RHS\'s VARREF \'IRQ_S_TIMER\' generates 32 bits.\n    localparam logic [XLEN-1:0] S_TIMER_INTERRUPT = (1 << (XLEN-1)) | IRQ_S_TIMER;\n                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/include/riscv_pkg.sv:318: Operator OR expects 64 bits on the RHS, but RHS\'s VARREF \'IRQ_M_TIMER\' generates 32 bits.\n    localparam logic [XLEN-1:0] M_TIMER_INTERRUPT = (1 << (XLEN-1)) | IRQ_M_TIMER;\n                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/include/riscv_pkg.sv:319: Operator OR expects 64 bits on the RHS, but RHS\'s VARREF \'IRQ_S_EXT\' generates 32 bits.\n    localparam logic [XLEN-1:0] S_EXT_INTERRUPT   = (1 << (XLEN-1)) | IRQ_S_EXT;\n                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/include/riscv_pkg.sv:320: Operator OR expects 64 bits on the RHS, but RHS\'s VARREF \'IRQ_M_EXT\' generates 32 bits.\n    localparam logic [XLEN-1:0] M_EXT_INTERRUPT   = (1 << (XLEN-1)) | IRQ_M_EXT;\n                                                                    ^\n%Warning-UNPACKED: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/include/riscv_pkg.sv:676: Unsupported: Unpacked struct/union\n    typedef struct {\n            ^~~~~~\n%Error: Exiting due to 7 warning(s)\n'
function automatic logic [31:0] andi (logic[4:0] rd, logic[4:0] rs1, logic [11:0] imm);

        return {imm[11:0], rs1, 3'h7, rd, 7'h13};
    endfunction
function automatic logic [31:0] andi (logic[4:0] rd, logic[4:0] rs1, logic [11:0] imm);


        return {imm[11:0], rs1, 3'h7, rd, 7'h13};
    endfunction