data/full_repos/permissive/488093047/Verilog Codes/TB_NOT.v
1: b'%Error: Cannot find file containing module: Codes,data/full_repos/permissive/488093047\n        ... Looked in:\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.v\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.sv\n             Codes,data/full_repos/permissive/488093047\n             Codes,data/full_repos/permissive/488093047.v\n             Codes,data/full_repos/permissive/488093047.sv\n             obj_dir/Codes,data/full_repos/permissive/488093047\n             obj_dir/Codes,data/full_repos/permissive/488093047.v\n             obj_dir/Codes,data/full_repos/permissive/488093047.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/488093047/Verilog\n%Error: Cannot find file containing module: Codes/TB_NOT.v\n%Error: Exiting due to 3 error(s)\n'
module TB_NOT();
parameter N=32;
reg [N-1:0]A;
wire [N-1:0]NOT;
NOT #(.N(N)) DUT1(.A(A),.NOT(NOT));

initial begin
A=32'd312;



end
endmodule
module TB_NOT();

parameter N=32;
reg [N-1:0]A;
wire [N-1:0]NOT;
NOT #(.N(N)) DUT1(.A(A),.NOT(NOT));

initial begin
A=32'd312;



end
endmodule