data/full_repos/permissive/493265923/02_INTEGRATOR_FWD/INTEGRATOR_FWD_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/493265923/02_INTEGRATOR_FWD/INTEGRATOR_FWD_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #2000 DATA_I <= 6\'b111111; \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/493265923/02_INTEGRATOR_FWD/INTEGRATOR_FWD_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #2000 DATA_I <= 6\'b000001;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/493265923/02_INTEGRATOR_FWD/INTEGRATOR_FWD_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #10 CLK_I <= ~CLK_I;\n        ^\n%Error: data/full_repos/permissive/493265923/02_INTEGRATOR_FWD/INTEGRATOR_FWD_tb.v:12: Cannot find file containing module: \'INTEGRATOR_FWD\'\n    INTEGRATOR_FWD u1(\n    ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/493265923/02_INTEGRATOR_FWD,data/full_repos/permissive/493265923/INTEGRATOR_FWD\n             data/full_repos/permissive/493265923/02_INTEGRATOR_FWD,data/full_repos/permissive/493265923/INTEGRATOR_FWD.v\n             data/full_repos/permissive/493265923/02_INTEGRATOR_FWD,data/full_repos/permissive/493265923/INTEGRATOR_FWD.sv\n             INTEGRATOR_FWD\n             INTEGRATOR_FWD.v\n             INTEGRATOR_FWD.sv\n             obj_dir/INTEGRATOR_FWD\n             obj_dir/INTEGRATOR_FWD.v\n             obj_dir/INTEGRATOR_FWD.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module INTEGRATOR_FWD_tb ();

    reg CLK_I = 1'b0;
    reg signed [5:0] DATA_I = 6'b000001;

    wire signed [5:0] DATA_O;
    wire OFDET_O;
    wire UFDET_O;


    INTEGRATOR_FWD u1(
        .CLK_I(CLK_I),
        .DATA_I(DATA_I),
        .DATA_O(DATA_O),
        .OFDET_O(OFDET_O),
        .UFDET_O(UFDET_O)
    );
    defparam u1.DATA_Bit_Length = 6;

    always begin

        #2000 DATA_I <= 6'b111111; 


        #2000 DATA_I <= 6'b000001;
    end

    always begin

        #10 CLK_I <= ~CLK_I;
    end

endmodule
module INTEGRATOR_FWD_tb ();


    reg CLK_I = 1'b0;
    reg signed [5:0] DATA_I = 6'b000001;

    wire signed [5:0] DATA_O;
    wire OFDET_O;
    wire UFDET_O;


    INTEGRATOR_FWD u1(
        .CLK_I(CLK_I),
        .DATA_I(DATA_I),
        .DATA_O(DATA_O),
        .OFDET_O(OFDET_O),
        .UFDET_O(UFDET_O)
    );
    defparam u1.DATA_Bit_Length = 6;

    always begin

        #2000 DATA_I <= 6'b111111; 


        #2000 DATA_I <= 6'b000001;
    end

    always begin

        #10 CLK_I <= ~CLK_I;
    end

endmodule