data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tech_cells_generic/src/pulp_clock_xor2.sv
data/verilator_xmls/67ff8eaf-4be1-42ef-822d-4c32c16e14d0.xml
module pulp_clock_xor2
  (
   input  logic clk0_i,
   input  logic clk1_i,
   output logic clk_o
   );
   
   assign clk_o = clk0_i ^ clk1_i;
   
endmodule
module pulp_clock_xor2
  (
   input  logic clk0_i,
   input  logic clk1_i,
   output logic clk_o
   );

   
   assign clk_o = clk0_i ^ clk1_i;
   
endmodule