data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v
1: b'%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:52: Cannot find include file: output_port_lookup_cpu_regs_defines.v\n`include "output_port_lookup_cpu_regs_defines.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl,data/full_repos/permissive/498471995/output_port_lookup_cpu_regs_defines.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl,data/full_repos/permissive/498471995/output_port_lookup_cpu_regs_defines.v.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl,data/full_repos/permissive/498471995/output_port_lookup_cpu_regs_defines.v.sv\n             output_port_lookup_cpu_regs_defines.v\n             output_port_lookup_cpu_regs_defines.v.v\n             output_port_lookup_cpu_regs_defines.v.sv\n             obj_dir/output_port_lookup_cpu_regs_defines.v\n             obj_dir/output_port_lookup_cpu_regs_defines.v.v\n             obj_dir/output_port_lookup_cpu_regs_defines.v.sv\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:170: Define or directive not defined: \'`REG_ID_BITS\'\n   reg      [`REG_ID_BITS]    id_reg;\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:170: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   reg      [`REG_ID_BITS]    id_reg;\n                         ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:171: Define or directive not defined: \'`REG_VERSION_BITS\'\n   reg      [`REG_VERSION_BITS]    version_reg;\n             ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:171: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   reg      [`REG_VERSION_BITS]    version_reg;\n                              ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:172: Define or directive not defined: \'`REG_RESET_BITS\'\n   wire     [`REG_RESET_BITS]    reset_reg;\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:172: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   wire     [`REG_RESET_BITS]    reset_reg;\n                            ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:173: Define or directive not defined: \'`REG_FLIP_BITS\'\n   reg      [`REG_FLIP_BITS]    ip2cpu_flip_reg;\n             ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:173: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   reg      [`REG_FLIP_BITS]    ip2cpu_flip_reg;\n                           ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:174: Define or directive not defined: \'`REG_FLIP_BITS\'\n   wire     [`REG_FLIP_BITS]    cpu2ip_flip_reg;\n             ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:174: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   wire     [`REG_FLIP_BITS]    cpu2ip_flip_reg;\n                           ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:175: Define or directive not defined: \'`REG_PKTIN_BITS\'\n   reg      [`REG_PKTIN_BITS]    pktin_reg;\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:175: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   reg      [`REG_PKTIN_BITS]    pktin_reg;\n                            ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:177: Define or directive not defined: \'`REG_PKTOUT_BITS\'\n   reg      [`REG_PKTOUT_BITS]    pktout_reg;\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:177: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   reg      [`REG_PKTOUT_BITS]    pktout_reg;\n                             ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:179: Define or directive not defined: \'`REG_LUTHIT_BITS\'\n   reg      [`REG_LUTHIT_BITS]    luthit_reg;\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:179: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   reg      [`REG_LUTHIT_BITS]    luthit_reg;\n                             ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:181: Define or directive not defined: \'`REG_LUTMISS_BITS\'\n   reg      [`REG_LUTMISS_BITS]    lutmiss_reg;\n             ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:181: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   reg      [`REG_LUTMISS_BITS]    lutmiss_reg;\n                              ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:183: Define or directive not defined: \'`REG_DEBUG_BITS\'\n   reg      [`REG_DEBUG_BITS]    ip2cpu_debug_reg;\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:183: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   reg      [`REG_DEBUG_BITS]    ip2cpu_debug_reg;\n                            ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:184: Define or directive not defined: \'`REG_DEBUG_BITS\'\n   wire     [`REG_DEBUG_BITS]    cpu2ip_debug_reg;\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:184: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   wire     [`REG_DEBUG_BITS]    cpu2ip_debug_reg;\n                            ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:368: Define or directive not defined: \'`REG_ID_DEFAULT\'\n  id_reg <= #1    `REG_ID_DEFAULT;\n                  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:368: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  id_reg <= #1    `REG_ID_DEFAULT;\n                                 ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:369: Define or directive not defined: \'`REG_VERSION_DEFAULT\'\n  version_reg <= #1    `REG_VERSION_DEFAULT;\n                       ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:369: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  version_reg <= #1    `REG_VERSION_DEFAULT;\n                                           ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:370: Define or directive not defined: \'`REG_FLIP_DEFAULT\'\n  ip2cpu_flip_reg <= #1    `REG_FLIP_DEFAULT;\n                           ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:370: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  ip2cpu_flip_reg <= #1    `REG_FLIP_DEFAULT;\n                                            ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:371: Define or directive not defined: \'`REG_PKTIN_DEFAULT\'\n  pktin_reg <= #1    `REG_PKTIN_DEFAULT;\n                     ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:371: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  pktin_reg <= #1    `REG_PKTIN_DEFAULT;\n                                       ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:372: Define or directive not defined: \'`REG_PKTOUT_DEFAULT\'\n  pktout_reg <= #1    `REG_PKTOUT_DEFAULT;\n                      ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:372: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  pktout_reg <= #1    `REG_PKTOUT_DEFAULT;\n                                         ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:373: Define or directive not defined: \'`REG_LUTHIT_DEFAULT\'\n  luthit_reg <= #1    `REG_LUTHIT_DEFAULT;\n                      ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:373: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  luthit_reg <= #1    `REG_LUTHIT_DEFAULT;\n                                         ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:374: Define or directive not defined: \'`REG_LUTMISS_DEFAULT\'\n  lutmiss_reg <= #1    `REG_LUTMISS_DEFAULT;\n                       ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:374: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  lutmiss_reg <= #1    `REG_LUTMISS_DEFAULT;\n                                           ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:375: Define or directive not defined: \'`REG_DEBUG_DEFAULT\'\n  ip2cpu_debug_reg <= #1    `REG_DEBUG_DEFAULT;\n                            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:375: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  ip2cpu_debug_reg <= #1    `REG_DEBUG_DEFAULT;\n                                              ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:378: Define or directive not defined: \'`REG_ID_DEFAULT\'\n  id_reg <= #1    `REG_ID_DEFAULT;\n                  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:378: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  id_reg <= #1    `REG_ID_DEFAULT;\n                                 ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:379: Define or directive not defined: \'`REG_VERSION_DEFAULT\'\n  version_reg <= #1    `REG_VERSION_DEFAULT;\n                       ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:379: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  version_reg <= #1    `REG_VERSION_DEFAULT;\n                                           ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:381: Define or directive not defined: \'`REG_PKTIN_WIDTH\'\n  pktin_reg[`REG_PKTIN_WIDTH -2: 0] <= #1  clear_counters | pktin_reg_clear ? \'h0  : pktin_reg[`REG_PKTIN_WIDTH-2:0] + (s_axis_tlast && s_axis_tvalid && s_axis_tready) ;\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:381: Define or directive not defined: \'`REG_PKTIN_WIDTH\'\n  pktin_reg[`REG_PKTIN_WIDTH -2: 0] <= #1  clear_counters | pktin_reg_clear ? \'h0  : pktin_reg[`REG_PKTIN_WIDTH-2:0] + (s_axis_tlast && s_axis_tvalid && s_axis_tready) ;\n                                                                                               ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:382: Define or directive not defined: \'`REG_PKTIN_WIDTH\'\n                pktin_reg[`REG_PKTIN_WIDTH-1] <= #1 clear_counters | pktin_reg_clear ? 1\'h0   : pktin_reg[`REG_PKTIN_WIDTH-2:0] + (s_axis_tlast && s_axis_tvalid && s_axis_tready) \n                          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:382: Define or directive not defined: \'`REG_PKTIN_WIDTH\'\n                pktin_reg[`REG_PKTIN_WIDTH-1] <= #1 clear_counters | pktin_reg_clear ? 1\'h0   : pktin_reg[`REG_PKTIN_WIDTH-2:0] + (s_axis_tlast && s_axis_tvalid && s_axis_tready) \n                                                                                                          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:383: Define or directive not defined: \'`REG_PKTIN_WIDTH\'\n                                                     > {(`REG_PKTIN_WIDTH-1){1\'b1}} ? 1\'b1 : pktin_reg[`REG_PKTIN_WIDTH-1];\n                                                         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:383: Define or directive not defined: \'`REG_PKTIN_WIDTH\'\n                                                     > {(`REG_PKTIN_WIDTH-1){1\'b1}} ? 1\'b1 : pktin_reg[`REG_PKTIN_WIDTH-1];\n                                                                                                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/switch_output_port_lookup_v1_0_1/hdl/switch_output_port_lookup.v:385: Define or directive not defined: \'`REG_PKTOUT_WIDTH\'\n  pktout_reg [`REG_PKTOUT_WIDTH-2:0]<= #1  clear_counters | pktout_reg_clear ? \'h0  : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tvalid && m_axis_tlast && m_axis_tready) ;\n              ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module switch_output_port_lookup
#(

    parameter C_M_AXIS_DATA_WIDTH  = 256,
    parameter C_S_AXIS_DATA_WIDTH  = 256,
    parameter C_M_AXIS_TUSER_WIDTH = 128,
    parameter C_S_AXIS_TUSER_WIDTH = 128,
    parameter SRC_PORT_POS         = 16,
    parameter DST_PORT_POS         = 24,
    parameter NUM_OUTPUT_QUEUES    = 8,



    parameter C_S_AXI_DATA_WIDTH    = 32,          
    parameter C_S_AXI_ADDR_WIDTH    = 12,          
    parameter C_USE_WSTRB           = 0,	   
    parameter C_DPHASE_TIMEOUT      = 0,               
    parameter C_NUM_ADDRESS_RANGES = 1,
    parameter  C_TOTAL_NUM_CE       = 1,
    parameter  C_S_AXI_MIN_SIZE    = 32'h0000_FFFF,
    parameter [0:8*C_NUM_ADDRESS_RANGES-1] C_ARD_NUM_CE_ARRAY  = 
                                                {
                                                 C_NUM_ADDRESS_RANGES{8'd1}
                                                 },
    parameter     C_FAMILY            = "virtex7", 
    parameter C_BASEADDR            = 32'h00000000,
    parameter C_HIGHADDR            = 32'h0000FFFF


)
(

    input                                      axis_aclk,
    input                                      axis_resetn,


    output [C_M_AXIS_DATA_WIDTH - 1:0]         m_axis_tdata,
    output [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] m_axis_tkeep,
    output reg [C_M_AXIS_TUSER_WIDTH-1:0]      m_axis_tuser,
    output                                     m_axis_tvalid,
    input                                      m_axis_tready,
    output                                     m_axis_tlast,


    input [C_S_AXIS_DATA_WIDTH - 1:0]          s_axis_tdata,
    input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0]  s_axis_tkeep,
    input [C_S_AXIS_TUSER_WIDTH-1:0]           s_axis_tuser,
    input                                      s_axis_tvalid,
    output                                     s_axis_tready,
    input                                      s_axis_tlast,



    input                                     S_AXI_ACLK,
    input                                     S_AXI_ARESETN,
    input      [C_S_AXI_ADDR_WIDTH-1 : 0]     S_AXI_AWADDR,
    input                                     S_AXI_AWVALID,
    input      [C_S_AXI_DATA_WIDTH-1 : 0]     S_AXI_WDATA,
    input      [C_S_AXI_DATA_WIDTH/8-1 : 0]   S_AXI_WSTRB,
    input                                     S_AXI_WVALID,
    input                                     S_AXI_BREADY,
    input      [C_S_AXI_ADDR_WIDTH-1 : 0]     S_AXI_ARADDR,
    input                                     S_AXI_ARVALID,
    input                                     S_AXI_RREADY,
    output                                    S_AXI_ARREADY,
    output     [C_S_AXI_DATA_WIDTH-1 : 0]     S_AXI_RDATA,
    output     [1 : 0]                        S_AXI_RRESP,
    output                                    S_AXI_RVALID,
    output                                    S_AXI_WREADY,
    output     [1 :0]                         S_AXI_BRESP,
    output                                    S_AXI_BVALID,
    output                                    S_AXI_AWREADY
);

   function integer log2;
      input integer number;
      begin
         log2=0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
   endfunction


   localparam LUT_DEPTH_BITS            = 4;
   localparam DEFAULT_MISS_OUTPUT_PORTS = 8'h55;

   localparam NUM_STATES                = 2;
   localparam WAIT_STATE                = 1;
   localparam SEND_STATE                = 2;


   wire [47:0]			           dst_mac;
   wire [47:0]                     src_mac;
   wire [NUM_OUTPUT_QUEUES-1:0]    src_port;
   wire                            eth_done;
   wire [NUM_OUTPUT_QUEUES-1:0]    dst_ports;
   
   wire                            lookup_done;
   reg				   send_packet;
   
   wire [C_S_AXIS_TUSER_WIDTH-1:0] tuser_fifo;

   wire                            in_fifo_rd_en;
   wire                            in_fifo_nearly_full;
   wire                            in_fifo_empty;

   wire [NUM_OUTPUT_QUEUES-1:0]    dst_ports_latched;
   reg                             dst_port_rd;
   wire                            dst_port_fifo_nearly_full;
   wire                            dst_port_fifo_empty;
   
   reg  [NUM_STATES-1:0]           state, state_next;


   reg      [`REG_ID_BITS]    id_reg;
   reg      [`REG_VERSION_BITS]    version_reg;
   wire     [`REG_RESET_BITS]    reset_reg;
   reg      [`REG_FLIP_BITS]    ip2cpu_flip_reg;
   wire     [`REG_FLIP_BITS]    cpu2ip_flip_reg;
   reg      [`REG_PKTIN_BITS]    pktin_reg;
   wire                             pktin_reg_clear;
   reg      [`REG_PKTOUT_BITS]    pktout_reg;
   wire                             pktout_reg_clear;
   reg      [`REG_LUTHIT_BITS]    luthit_reg;
   wire                             luthit_reg_clear;
   reg      [`REG_LUTMISS_BITS]    lutmiss_reg;
   wire                             lutmiss_reg_clear;
   reg      [`REG_DEBUG_BITS]    ip2cpu_debug_reg;
   wire     [`REG_DEBUG_BITS]    cpu2ip_debug_reg;

   wire clear_counters;
   wire reset_registers;
   wire reset_tables;
   

   

   fallthrough_small_fifo #(.WIDTH(C_M_AXIS_DATA_WIDTH+C_M_AXIS_TUSER_WIDTH+C_M_AXIS_DATA_WIDTH/8+1), .MAX_DEPTH_BITS(4))
      input_fifo
        (.din         ({s_axis_tlast, s_axis_tuser, s_axis_tkeep, s_axis_tdata}),
         .wr_en       (s_axis_tvalid & s_axis_tready),
         .rd_en       (in_fifo_rd_en),
         .dout        ({m_axis_tlast, tuser_fifo, m_axis_tkeep, m_axis_tdata}),
         .full        (),
         .prog_full   (),
         .nearly_full (in_fifo_nearly_full),
         .empty       (in_fifo_empty),
         .reset       (~axis_resetn),
         .clk         (axis_aclk)
         );

   assign s_axis_tready = ~in_fifo_nearly_full;
   
   eth_parser
     #(.C_S_AXIS_DATA_WIDTH (C_S_AXIS_DATA_WIDTH),
       .C_S_AXIS_TUSER_WIDTH (C_S_AXIS_TUSER_WIDTH))
      eth_parser
         (.tdata    (s_axis_tdata),
          .tuser    (s_axis_tuser),
          .valid    (s_axis_tvalid & s_axis_tready),
	      .tlast    (s_axis_tlast),
          
		  .dst_mac  (dst_mac),
          .src_mac  (src_mac),
          .eth_done (eth_done),
          .src_port (src_port),
          .reset    (~axis_resetn),
          .clk      (axis_aclk));

   mac_cam_lut
     #(.NUM_OUTPUT_QUEUES(NUM_OUTPUT_QUEUES),
       .LUT_DEPTH_BITS(LUT_DEPTH_BITS),
       .DEFAULT_MISS_OUTPUT_PORTS(DEFAULT_MISS_OUTPUT_PORTS))
   mac_cam_lut

     (.dst_mac      (dst_mac),
      .src_mac      (src_mac),
      .src_port     (src_port),
      .lookup_req   (eth_done),
      .dst_ports    (dst_ports),
      
      .lookup_done  (lookup_done),
      .lut_hit      (lut_hit),
      .lut_miss     (lut_miss),


      .clk          (axis_aclk),
      .reset        (~axis_resetn | reset_tables));

   fallthrough_small_fifo #(.WIDTH(NUM_OUTPUT_QUEUES), .MAX_DEPTH_BITS(2))
      dst_port_fifo
        (.din (dst_ports),
         .wr_en (lookup_done),
         .rd_en (dst_port_rd),
         .dout (dst_ports_latched),
         .full (),
         .prog_full (),
         .nearly_full (dst_port_fifo_nearly_full),
         .empty (dst_port_fifo_empty),
         .reset (~axis_resetn),
         .clk (axis_aclk)
         );


   always @(*) begin
      m_axis_tuser = tuser_fifo;
      state_next   = state;
      dst_port_rd = 0;
      send_packet  = 1;

      case(state)
        WAIT_STATE: begin
	       send_packet = 0;
        
     	   if(!dst_port_fifo_empty) begin
	          state_next = SEND_STATE;
		  send_packet = 1;
                  dst_port_rd = 1;
           	  m_axis_tuser[DST_PORT_POS+7:DST_PORT_POS] = dst_ports_latched;
	       end	
	    end

	    SEND_STATE: begin
	       if(m_axis_tlast & m_axis_tvalid & m_axis_tready)
		      state_next = WAIT_STATE;
	    end
      endcase
   end

   always @(posedge axis_aclk) begin
      if(~axis_resetn) begin
         state <= WAIT_STATE;
      end
      else begin
         state <= state_next;
      end
   end


   assign m_axis_tvalid = ~in_fifo_empty & send_packet;
   assign in_fifo_rd_en = m_axis_tready & m_axis_tvalid;




output_port_lookup_cpu_regs 
 #(
   .C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
   .C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH),
   .C_BASE_ADDRESS    (C_BASEADDR)
 ) opl_cpu_regs_inst
 (   

    .clk                    (axis_aclk),
    .resetn                 (axis_resetn),

    .S_AXI_ACLK             (S_AXI_ACLK),
    .S_AXI_ARESETN          (S_AXI_ARESETN),
    .S_AXI_AWADDR           (S_AXI_AWADDR),
    .S_AXI_AWVALID          (S_AXI_AWVALID),
    .S_AXI_WDATA            (S_AXI_WDATA),
    .S_AXI_WSTRB            (S_AXI_WSTRB),
    .S_AXI_WVALID           (S_AXI_WVALID),
    .S_AXI_BREADY           (S_AXI_BREADY),
    .S_AXI_ARADDR           (S_AXI_ARADDR),
    .S_AXI_ARVALID          (S_AXI_ARVALID),
    .S_AXI_RREADY           (S_AXI_RREADY),
    .S_AXI_ARREADY          (S_AXI_ARREADY),
    .S_AXI_RDATA            (S_AXI_RDATA),
    .S_AXI_RRESP            (S_AXI_RRESP),
    .S_AXI_RVALID           (S_AXI_RVALID),
    .S_AXI_WREADY           (S_AXI_WREADY),
    .S_AXI_BRESP            (S_AXI_BRESP),
    .S_AXI_BVALID           (S_AXI_BVALID),
    .S_AXI_AWREADY          (S_AXI_AWREADY),

   

   .id_reg          (id_reg),
   .version_reg          (version_reg),
   .reset_reg          (reset_reg),
   .ip2cpu_flip_reg          (ip2cpu_flip_reg),
   .cpu2ip_flip_reg          (cpu2ip_flip_reg),
   .pktin_reg           (pktin_reg),
   .pktin_reg_clear     (pktin_reg_clear),
   .pktout_reg          (pktout_reg),
   .pktout_reg_clear    (pktout_reg_clear),
   .luthit_reg              (luthit_reg),
   .luthit_reg_clear        (luthit_reg_clear),
   .lutmiss_reg             (lutmiss_reg),
   .lutmiss_reg_clear       (lutmiss_reg_clear),

   .ip2cpu_debug_reg          (ip2cpu_debug_reg),
   .cpu2ip_debug_reg          (cpu2ip_debug_reg),

   .cpu_resetn_soft(),
   .resetn_soft    (),
   .resetn_sync    (resetn_sync)
);

   assign clear_counters =  reset_reg[0];
   assign reset_registers = reset_reg[4];
   assign reset_tables   =  reset_reg[8];


always @(posedge axis_aclk)
	if (~resetn_sync | reset_registers) begin
		id_reg <= #1    `REG_ID_DEFAULT;
		version_reg <= #1    `REG_VERSION_DEFAULT;
		ip2cpu_flip_reg <= #1    `REG_FLIP_DEFAULT;
		pktin_reg <= #1    `REG_PKTIN_DEFAULT;
		pktout_reg <= #1    `REG_PKTOUT_DEFAULT;
		luthit_reg <= #1    `REG_LUTHIT_DEFAULT;
		lutmiss_reg <= #1    `REG_LUTMISS_DEFAULT;
		ip2cpu_debug_reg <= #1    `REG_DEBUG_DEFAULT;
	end
	else begin
		id_reg <= #1    `REG_ID_DEFAULT;
		version_reg <= #1    `REG_VERSION_DEFAULT;
		ip2cpu_flip_reg <= #1    ~cpu2ip_flip_reg;
		pktin_reg[`REG_PKTIN_WIDTH -2: 0] <= #1  clear_counters | pktin_reg_clear ? 'h0  : pktin_reg[`REG_PKTIN_WIDTH-2:0] + (s_axis_tlast && s_axis_tvalid && s_axis_tready) ;
                pktin_reg[`REG_PKTIN_WIDTH-1] <= #1 clear_counters | pktin_reg_clear ? 1'h0   : pktin_reg[`REG_PKTIN_WIDTH-2:0] + (s_axis_tlast && s_axis_tvalid && s_axis_tready) 
                                                     > {(`REG_PKTIN_WIDTH-1){1'b1}} ? 1'b1 : pktin_reg[`REG_PKTIN_WIDTH-1];
                                                               
		pktout_reg [`REG_PKTOUT_WIDTH-2:0]<= #1  clear_counters | pktout_reg_clear ? 'h0  : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tvalid && m_axis_tlast && m_axis_tready) ;
                pktout_reg [`REG_PKTOUT_WIDTH-1]<= #1  clear_counters | pktout_reg_clear ? 'h0  : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tvalid && m_axis_tlast && m_axis_tready)  > {(`REG_PKTOUT_WIDTH-1){1'b1}} ?
                                                                1'b1 : pktout_reg [`REG_PKTOUT_WIDTH-1];
		luthit_reg[`REG_LUTHIT_WIDTH -2: 0] <= #1  clear_counters | luthit_reg_clear ? 'h0  : luthit_reg[`REG_LUTHIT_WIDTH-2:0] + (lut_hit & lookup_done) ;
                luthit_reg[`REG_LUTHIT_WIDTH-1] <= #1 clear_counters | luthit_reg_clear ? 1'h0 : luthit_reg_clear ? 'h0  : luthit_reg[`REG_LUTHIT_WIDTH-2:0] + (lut_hit & lookup_done)
                                                     > {(`REG_LUTHIT_WIDTH-1){1'b1}} ? 1'b1 : pktin_reg[`REG_LUTHIT_WIDTH-1];
                                                               
		lutmiss_reg [`REG_LUTMISS_WIDTH-2:0]<= #1  clear_counters | lutmiss_reg_clear ? 'h0  : lutmiss_reg [`REG_LUTMISS_WIDTH-2:0] + (lut_miss & lookup_done) ;
                lutmiss_reg [`REG_LUTMISS_WIDTH-1]<= #1  clear_counters | lutmiss_reg_clear ? 'h0  : lutmiss_reg [`REG_LUTMISS_WIDTH-2:0] + (lut_miss & lookup_done)  > {(`REG_LUTMISS_WIDTH-1){1'b1}} ?
                                                                1'b1 : lutmiss_reg [`REG_LUTMISS_WIDTH-1];

		ip2cpu_debug_reg <= #1    `REG_DEBUG_DEFAULT+cpu2ip_debug_reg;
        end



   
endmodule
module switch_output_port_lookup
#(

    parameter C_M_AXIS_DATA_WIDTH  = 256,
    parameter C_S_AXIS_DATA_WIDTH  = 256,
    parameter C_M_AXIS_TUSER_WIDTH = 128,
    parameter C_S_AXIS_TUSER_WIDTH = 128,
    parameter SRC_PORT_POS         = 16,
    parameter DST_PORT_POS         = 24,
    parameter NUM_OUTPUT_QUEUES    = 8,



    parameter C_S_AXI_DATA_WIDTH    = 32,          
    parameter C_S_AXI_ADDR_WIDTH    = 12,          
    parameter C_USE_WSTRB           = 0,	   
    parameter C_DPHASE_TIMEOUT      = 0,               
    parameter C_NUM_ADDRESS_RANGES = 1,
    parameter  C_TOTAL_NUM_CE       = 1,
    parameter  C_S_AXI_MIN_SIZE    = 32'h0000_FFFF,
    parameter [0:8*C_NUM_ADDRESS_RANGES-1] C_ARD_NUM_CE_ARRAY  = 
                                                {
                                                 C_NUM_ADDRESS_RANGES{8'd1}
                                                 },
    parameter     C_FAMILY            = "virtex7", 
    parameter C_BASEADDR            = 32'h00000000,
    parameter C_HIGHADDR            = 32'h0000FFFF


)
(

    input                                      axis_aclk,
    input                                      axis_resetn,


    output [C_M_AXIS_DATA_WIDTH - 1:0]         m_axis_tdata,
    output [((C_M_AXIS_DATA_WIDTH / 8)) - 1:0] m_axis_tkeep,
    output reg [C_M_AXIS_TUSER_WIDTH-1:0]      m_axis_tuser,
    output                                     m_axis_tvalid,
    input                                      m_axis_tready,
    output                                     m_axis_tlast,


    input [C_S_AXIS_DATA_WIDTH - 1:0]          s_axis_tdata,
    input [((C_S_AXIS_DATA_WIDTH / 8)) - 1:0]  s_axis_tkeep,
    input [C_S_AXIS_TUSER_WIDTH-1:0]           s_axis_tuser,
    input                                      s_axis_tvalid,
    output                                     s_axis_tready,
    input                                      s_axis_tlast,



    input                                     S_AXI_ACLK,
    input                                     S_AXI_ARESETN,
    input      [C_S_AXI_ADDR_WIDTH-1 : 0]     S_AXI_AWADDR,
    input                                     S_AXI_AWVALID,
    input      [C_S_AXI_DATA_WIDTH-1 : 0]     S_AXI_WDATA,
    input      [C_S_AXI_DATA_WIDTH/8-1 : 0]   S_AXI_WSTRB,
    input                                     S_AXI_WVALID,
    input                                     S_AXI_BREADY,
    input      [C_S_AXI_ADDR_WIDTH-1 : 0]     S_AXI_ARADDR,
    input                                     S_AXI_ARVALID,
    input                                     S_AXI_RREADY,
    output                                    S_AXI_ARREADY,
    output     [C_S_AXI_DATA_WIDTH-1 : 0]     S_AXI_RDATA,
    output     [1 : 0]                        S_AXI_RRESP,
    output                                    S_AXI_RVALID,
    output                                    S_AXI_WREADY,
    output     [1 :0]                         S_AXI_BRESP,
    output                                    S_AXI_BVALID,
    output                                    S_AXI_AWREADY
);


   function integer log2;
      input integer number;
      begin
         log2=0;
         while(2**log2<number) begin
            log2=log2+1;
         end
      end
   endfunction


   localparam LUT_DEPTH_BITS            = 4;
   localparam DEFAULT_MISS_OUTPUT_PORTS = 8'h55;

   localparam NUM_STATES                = 2;
   localparam WAIT_STATE                = 1;
   localparam SEND_STATE                = 2;


   wire [47:0]			           dst_mac;
   wire [47:0]                     src_mac;
   wire [NUM_OUTPUT_QUEUES-1:0]    src_port;
   wire                            eth_done;
   wire [NUM_OUTPUT_QUEUES-1:0]    dst_ports;
   
   wire                            lookup_done;
   reg				   send_packet;
   
   wire [C_S_AXIS_TUSER_WIDTH-1:0] tuser_fifo;

   wire                            in_fifo_rd_en;
   wire                            in_fifo_nearly_full;
   wire                            in_fifo_empty;

   wire [NUM_OUTPUT_QUEUES-1:0]    dst_ports_latched;
   reg                             dst_port_rd;
   wire                            dst_port_fifo_nearly_full;
   wire                            dst_port_fifo_empty;
   
   reg  [NUM_STATES-1:0]           state, state_next;


   reg      [`REG_ID_BITS]    id_reg;
   reg      [`REG_VERSION_BITS]    version_reg;
   wire     [`REG_RESET_BITS]    reset_reg;
   reg      [`REG_FLIP_BITS]    ip2cpu_flip_reg;
   wire     [`REG_FLIP_BITS]    cpu2ip_flip_reg;
   reg      [`REG_PKTIN_BITS]    pktin_reg;
   wire                             pktin_reg_clear;
   reg      [`REG_PKTOUT_BITS]    pktout_reg;
   wire                             pktout_reg_clear;
   reg      [`REG_LUTHIT_BITS]    luthit_reg;
   wire                             luthit_reg_clear;
   reg      [`REG_LUTMISS_BITS]    lutmiss_reg;
   wire                             lutmiss_reg_clear;
   reg      [`REG_DEBUG_BITS]    ip2cpu_debug_reg;
   wire     [`REG_DEBUG_BITS]    cpu2ip_debug_reg;

   wire clear_counters;
   wire reset_registers;
   wire reset_tables;
   

   

   fallthrough_small_fifo #(.WIDTH(C_M_AXIS_DATA_WIDTH+C_M_AXIS_TUSER_WIDTH+C_M_AXIS_DATA_WIDTH/8+1), .MAX_DEPTH_BITS(4))
      input_fifo
        (.din         ({s_axis_tlast, s_axis_tuser, s_axis_tkeep, s_axis_tdata}),
         .wr_en       (s_axis_tvalid & s_axis_tready),
         .rd_en       (in_fifo_rd_en),
         .dout        ({m_axis_tlast, tuser_fifo, m_axis_tkeep, m_axis_tdata}),
         .full        (),
         .prog_full   (),
         .nearly_full (in_fifo_nearly_full),
         .empty       (in_fifo_empty),
         .reset       (~axis_resetn),
         .clk         (axis_aclk)
         );

   assign s_axis_tready = ~in_fifo_nearly_full;
   
   eth_parser
     #(.C_S_AXIS_DATA_WIDTH (C_S_AXIS_DATA_WIDTH),
       .C_S_AXIS_TUSER_WIDTH (C_S_AXIS_TUSER_WIDTH))
      eth_parser
         (.tdata    (s_axis_tdata),
          .tuser    (s_axis_tuser),
          .valid    (s_axis_tvalid & s_axis_tready),
	      .tlast    (s_axis_tlast),
          
		  .dst_mac  (dst_mac),
          .src_mac  (src_mac),
          .eth_done (eth_done),
          .src_port (src_port),
          .reset    (~axis_resetn),
          .clk      (axis_aclk));

   mac_cam_lut
     #(.NUM_OUTPUT_QUEUES(NUM_OUTPUT_QUEUES),
       .LUT_DEPTH_BITS(LUT_DEPTH_BITS),
       .DEFAULT_MISS_OUTPUT_PORTS(DEFAULT_MISS_OUTPUT_PORTS))
   mac_cam_lut

     (.dst_mac      (dst_mac),
      .src_mac      (src_mac),
      .src_port     (src_port),
      .lookup_req   (eth_done),
      .dst_ports    (dst_ports),
      
      .lookup_done  (lookup_done),
      .lut_hit      (lut_hit),
      .lut_miss     (lut_miss),


      .clk          (axis_aclk),
      .reset        (~axis_resetn | reset_tables));

   fallthrough_small_fifo #(.WIDTH(NUM_OUTPUT_QUEUES), .MAX_DEPTH_BITS(2))
      dst_port_fifo
        (.din (dst_ports),
         .wr_en (lookup_done),
         .rd_en (dst_port_rd),
         .dout (dst_ports_latched),
         .full (),
         .prog_full (),
         .nearly_full (dst_port_fifo_nearly_full),
         .empty (dst_port_fifo_empty),
         .reset (~axis_resetn),
         .clk (axis_aclk)
         );


   always @(*) begin
      m_axis_tuser = tuser_fifo;
      state_next   = state;
      dst_port_rd = 0;
      send_packet  = 1;

      case(state)
        WAIT_STATE: begin
	       send_packet = 0;
        
     	   if(!dst_port_fifo_empty) begin
	          state_next = SEND_STATE;
		  send_packet = 1;
                  dst_port_rd = 1;
           	  m_axis_tuser[DST_PORT_POS+7:DST_PORT_POS] = dst_ports_latched;
	       end	
	    end

	    SEND_STATE: begin
	       if(m_axis_tlast & m_axis_tvalid & m_axis_tready)
		      state_next = WAIT_STATE;
	    end
      endcase
   end

   always @(posedge axis_aclk) begin
      if(~axis_resetn) begin
         state <= WAIT_STATE;
      end
      else begin
         state <= state_next;
      end
   end


   assign m_axis_tvalid = ~in_fifo_empty & send_packet;
   assign in_fifo_rd_en = m_axis_tready & m_axis_tvalid;




output_port_lookup_cpu_regs 
 #(
   .C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
   .C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH),
   .C_BASE_ADDRESS    (C_BASEADDR)
 ) opl_cpu_regs_inst
 (   

    .clk                    (axis_aclk),
    .resetn                 (axis_resetn),

    .S_AXI_ACLK             (S_AXI_ACLK),
    .S_AXI_ARESETN          (S_AXI_ARESETN),
    .S_AXI_AWADDR           (S_AXI_AWADDR),
    .S_AXI_AWVALID          (S_AXI_AWVALID),
    .S_AXI_WDATA            (S_AXI_WDATA),
    .S_AXI_WSTRB            (S_AXI_WSTRB),
    .S_AXI_WVALID           (S_AXI_WVALID),
    .S_AXI_BREADY           (S_AXI_BREADY),
    .S_AXI_ARADDR           (S_AXI_ARADDR),
    .S_AXI_ARVALID          (S_AXI_ARVALID),
    .S_AXI_RREADY           (S_AXI_RREADY),
    .S_AXI_ARREADY          (S_AXI_ARREADY),
    .S_AXI_RDATA            (S_AXI_RDATA),
    .S_AXI_RRESP            (S_AXI_RRESP),
    .S_AXI_RVALID           (S_AXI_RVALID),
    .S_AXI_WREADY           (S_AXI_WREADY),
    .S_AXI_BRESP            (S_AXI_BRESP),
    .S_AXI_BVALID           (S_AXI_BVALID),
    .S_AXI_AWREADY          (S_AXI_AWREADY),

   

   .id_reg          (id_reg),
   .version_reg          (version_reg),
   .reset_reg          (reset_reg),
   .ip2cpu_flip_reg          (ip2cpu_flip_reg),
   .cpu2ip_flip_reg          (cpu2ip_flip_reg),
   .pktin_reg           (pktin_reg),
   .pktin_reg_clear     (pktin_reg_clear),
   .pktout_reg          (pktout_reg),
   .pktout_reg_clear    (pktout_reg_clear),
   .luthit_reg              (luthit_reg),
   .luthit_reg_clear        (luthit_reg_clear),
   .lutmiss_reg             (lutmiss_reg),
   .lutmiss_reg_clear       (lutmiss_reg_clear),

   .ip2cpu_debug_reg          (ip2cpu_debug_reg),
   .cpu2ip_debug_reg          (cpu2ip_debug_reg),

   .cpu_resetn_soft(),
   .resetn_soft    (),
   .resetn_sync    (resetn_sync)
);

   assign clear_counters =  reset_reg[0];
   assign reset_registers = reset_reg[4];
   assign reset_tables   =  reset_reg[8];


always @(posedge axis_aclk)
	if (~resetn_sync | reset_registers) begin
		id_reg <= #1    `REG_ID_DEFAULT;
		version_reg <= #1    `REG_VERSION_DEFAULT;
		ip2cpu_flip_reg <= #1    `REG_FLIP_DEFAULT;
		pktin_reg <= #1    `REG_PKTIN_DEFAULT;
		pktout_reg <= #1    `REG_PKTOUT_DEFAULT;
		luthit_reg <= #1    `REG_LUTHIT_DEFAULT;
		lutmiss_reg <= #1    `REG_LUTMISS_DEFAULT;
		ip2cpu_debug_reg <= #1    `REG_DEBUG_DEFAULT;
	end
	else begin
		id_reg <= #1    `REG_ID_DEFAULT;
		version_reg <= #1    `REG_VERSION_DEFAULT;
		ip2cpu_flip_reg <= #1    ~cpu2ip_flip_reg;
		pktin_reg[`REG_PKTIN_WIDTH -2: 0] <= #1  clear_counters | pktin_reg_clear ? 'h0  : pktin_reg[`REG_PKTIN_WIDTH-2:0] + (s_axis_tlast && s_axis_tvalid && s_axis_tready) ;
                pktin_reg[`REG_PKTIN_WIDTH-1] <= #1 clear_counters | pktin_reg_clear ? 1'h0   : pktin_reg[`REG_PKTIN_WIDTH-2:0] + (s_axis_tlast && s_axis_tvalid && s_axis_tready) 
                                                     > {(`REG_PKTIN_WIDTH-1){1'b1}} ? 1'b1 : pktin_reg[`REG_PKTIN_WIDTH-1];
                                                               
		pktout_reg [`REG_PKTOUT_WIDTH-2:0]<= #1  clear_counters | pktout_reg_clear ? 'h0  : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tvalid && m_axis_tlast && m_axis_tready) ;
                pktout_reg [`REG_PKTOUT_WIDTH-1]<= #1  clear_counters | pktout_reg_clear ? 'h0  : pktout_reg [`REG_PKTOUT_WIDTH-2:0] + (m_axis_tvalid && m_axis_tlast && m_axis_tready)  > {(`REG_PKTOUT_WIDTH-1){1'b1}} ?
                                                                1'b1 : pktout_reg [`REG_PKTOUT_WIDTH-1];
		luthit_reg[`REG_LUTHIT_WIDTH -2: 0] <= #1  clear_counters | luthit_reg_clear ? 'h0  : luthit_reg[`REG_LUTHIT_WIDTH-2:0] + (lut_hit & lookup_done) ;
                luthit_reg[`REG_LUTHIT_WIDTH-1] <= #1 clear_counters | luthit_reg_clear ? 1'h0 : luthit_reg_clear ? 'h0  : luthit_reg[`REG_LUTHIT_WIDTH-2:0] + (lut_hit & lookup_done)
                                                     > {(`REG_LUTHIT_WIDTH-1){1'b1}} ? 1'b1 : pktin_reg[`REG_LUTHIT_WIDTH-1];
                                                               
		lutmiss_reg [`REG_LUTMISS_WIDTH-2:0]<= #1  clear_counters | lutmiss_reg_clear ? 'h0  : lutmiss_reg [`REG_LUTMISS_WIDTH-2:0] + (lut_miss & lookup_done) ;
                lutmiss_reg [`REG_LUTMISS_WIDTH-1]<= #1  clear_counters | lutmiss_reg_clear ? 'h0  : lutmiss_reg [`REG_LUTMISS_WIDTH-2:0] + (lut_miss & lookup_done)  > {(`REG_LUTMISS_WIDTH-1){1'b1}} ?
                                                                1'b1 : lutmiss_reg [`REG_LUTMISS_WIDTH-1];

		ip2cpu_debug_reg <= #1    `REG_DEBUG_DEFAULT+cpu2ip_debug_reg;
        end



   
endmodule