data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/af4eos_agg_ffcvrt.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/af4eos_agg_ffcvrt.v:194: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n     .do        (rdat),\n      ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/af4eos_agg_ffcvrt.v:194: syntax error, unexpected '(', expecting ')'\n     .do        (rdat),\n                 ^~~~\n%Error: Exiting due to 2 error(s)\n"
module af4eos_agg_ffcvrt
    (

     wclk,
     wrst,
     wen,
     wdat,
     wfull,
     whfull,
     wlen,

     rclk,
     rrst,
     ren,
     rdat,
     rempty
     
     );



parameter           ADR = 8,
                    DEP = 256,
                    DAT = 8,
                    TYP = "AUTO",
                    MAX = 0;




input               wclk;
input               wrst;
input               wen;
input [DAT-1:0]     wdat;
output              wfull;
output              whfull;
output [ADR:0]      wlen;


input               rclk;
input               rrst;
input               ren;
output [DAT-1:0]    rdat;
output              rempty;







wire [ADR-1:0]      waddr;
wire [ADR-1:0]      raddr;
wire [ADR:0]        gwprt;
wire [ADR:0]        grprt;

wire                rst;
assign              rst = wrst | rrst;


wire                owrst;
asyn_rst           wr_asyn_rst (.clk (wclk), .irst (rst), .orst (owrst));

wire                orrst;
asyn_rst           rd_asyn_rst (.clk (rclk), .irst (rst), .orst (orrst));



af4eos_agg_wprt_ctrl    af4eos_agg_wprt_ctrl
    (
     .wrst     (owrst),
     .wclk      (wclk),
     .wen       (wen),
     .waddr     (waddr),
     .gwprt     (gwprt),
     .grprt     (grprt),
     .wfull     (wfull),
     .whfull    (whfull),
     .wlen      (wlen)
     
     );
defparam            af4eos_agg_wprt_ctrl.ADDR = ADR,
                    af4eos_agg_wprt_ctrl.DEP  = DEP;

af4eos_agg_rprt_ctrl    af4eos_agg_rprt_ctrl
    (
     .rrst     (orrst),
     .rclk      (rclk),
     .ren       (ren),
     .raddr     (raddr),
     .grprt     (grprt),
     .gwprt     (gwprt),
     .rempty    (rempty),
     .rdy       ()
     
     );
defparam            af4eos_agg_rprt_ctrl.ADDR = ADR;



iarray112x    af4eos_agg_data
    (
     .wrst     (owrst),
     .wclk      (wclk),
     .wa        (waddr),
     .we        (wen),
     .di        (wdat),

     .rrst     (orrst),
     .rclk      (rclk),
     .ra        (raddr),
     .re        (ren),
     .do        (rdat),

     .test      (1'b0),
     .mask      (1'b0)
     );
defparam af4eos_agg_data.ADDRBIT    = ADR,
         af4eos_agg_data.DEPTH      = DEP,
         af4eos_agg_data.WIDTH      = DAT,
         af4eos_agg_data.TYPE       = TYP,
         af4eos_agg_data.MAXDEPTH   = MAX,
         af4eos_agg_data.MEM_RESET  = "OFF",
         af4eos_agg_data.NUMCLK     = 2;


endmodule
module af4eos_agg_ffcvrt
    (

     wclk,
     wrst,
     wen,
     wdat,
     wfull,
     whfull,
     wlen,

     rclk,
     rrst,
     ren,
     rdat,
     rempty
     
     );




parameter           ADR = 8,
                    DEP = 256,
                    DAT = 8,
                    TYP = "AUTO",
                    MAX = 0;




input               wclk;
input               wrst;
input               wen;
input [DAT-1:0]     wdat;
output              wfull;
output              whfull;
output [ADR:0]      wlen;


input               rclk;
input               rrst;
input               ren;
output [DAT-1:0]    rdat;
output              rempty;







wire [ADR-1:0]      waddr;
wire [ADR-1:0]      raddr;
wire [ADR:0]        gwprt;
wire [ADR:0]        grprt;

wire                rst;
assign              rst = wrst | rrst;


wire                owrst;
asyn_rst           wr_asyn_rst (.clk (wclk), .irst (rst), .orst (owrst));

wire                orrst;
asyn_rst           rd_asyn_rst (.clk (rclk), .irst (rst), .orst (orrst));



af4eos_agg_wprt_ctrl    af4eos_agg_wprt_ctrl
    (
     .wrst     (owrst),
     .wclk      (wclk),
     .wen       (wen),
     .waddr     (waddr),
     .gwprt     (gwprt),
     .grprt     (grprt),
     .wfull     (wfull),
     .whfull    (whfull),
     .wlen      (wlen)
     
     );
defparam            af4eos_agg_wprt_ctrl.ADDR = ADR,
                    af4eos_agg_wprt_ctrl.DEP  = DEP;

af4eos_agg_rprt_ctrl    af4eos_agg_rprt_ctrl
    (
     .rrst     (orrst),
     .rclk      (rclk),
     .ren       (ren),
     .raddr     (raddr),
     .grprt     (grprt),
     .gwprt     (gwprt),
     .rempty    (rempty),
     .rdy       ()
     
     );
defparam            af4eos_agg_rprt_ctrl.ADDR = ADR;



iarray112x    af4eos_agg_data
    (
     .wrst     (owrst),
     .wclk      (wclk),
     .wa        (waddr),
     .we        (wen),
     .di        (wdat),

     .rrst     (orrst),
     .rclk      (rclk),
     .ra        (raddr),
     .re        (ren),
     .do        (rdat),

     .test      (1'b0),
     .mask      (1'b0)
     );
defparam af4eos_agg_data.ADDRBIT    = ADR,
         af4eos_agg_data.DEPTH      = DEP,
         af4eos_agg_data.WIDTH      = DAT,
         af4eos_agg_data.TYPE       = TYP,
         af4eos_agg_data.MAXDEPTH   = MAX,
         af4eos_agg_data.MEM_RESET  = "OFF",
         af4eos_agg_data.NUMCLK     = 2;


endmodule