data/full_repos/permissive/468612001/Week03/mux8b_2to1/mux8b_2to1_if.v
data/verilator_xmls/1f63848a-5c40-4f51-b7fc-8864e8dcf995.xml
module mux8b_2to1_if (a, b, sel, out);
	input [7:0] a, b;
	input			sel;
	output [7:0] out;
	reg [7:0] out;
	
	always @(a, b, sel) begin
		if(sel)	out = b;
		else		out = a;
	end
endmodule
module mux8b_2to1_if (a, b, sel, out);

	input [7:0] a, b;
	input			sel;
	output [7:0] out;
	reg [7:0] out;
	
	always @(a, b, sel) begin
		if(sel)	out = b;
		else		out = a;
	end
endmodule