data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Latches and Flip-Flops/ece241_2013_q7/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Latches\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Latches\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Latches.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Latches.sv\n             Logic/Latches\n             Logic/Latches.v\n             Logic/Latches.sv\n             obj_dir/Logic/Latches\n             obj_dir/Logic/Latches.v\n             obj_dir/Logic/Latches.sv\n%Error: Cannot find file containing module: and\n%Error: Cannot find file containing module: Flip-Flops/ece241_2013_q7,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Flip-Flops/ece241_2013_q7/top_module.v\n%Error: Exiting due to 5 error(s)\n'
module top_module (
    input  wire clk,
    input  wire j,
    input  wire k,
    output wire Q
);

  wire dff_d, dff_q, dff_qn;

  my_dff dff1 (
      .clk(clk),
      .d  (dff_d),
      .q  (dff_q),
      .qn (dff_qn)
  );

  assign Q = dff_q;
  assign dff_d = (dff_qn & j) | (~k & dff_q);

endmodule
module top_module (
    input  wire clk,
    input  wire j,
    input  wire k,
    output wire Q
);


  wire dff_d, dff_q, dff_qn;

  my_dff dff1 (
      .clk(clk),
      .d  (dff_d),
      .q  (dff_q),
      .qn (dff_qn)
  );

  assign Q = dff_q;
  assign dff_d = (dff_qn & j) | (~k & dff_q);

endmodule