data/full_repos/permissive/472097485/Chu01/Eq1_01/TestEq2Bit.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu01/Eq1_01/TestEq2Bit.v:18: Unsupported: Ignoring delay on this delayed statement.\n #1 bit1 = !bit1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu01/Eq1_01/TestEq2Bit.v:21: Unsupported: Ignoring delay on this delayed statement.\n #2 bit2 = !bit2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu01/Eq1_01/TestEq2Bit.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: data/full_repos/permissive/472097485/Chu01/Eq1_01/TestEq2Bit.v:15: Cannot find file containing module: \'Eq2Bit\'\n Eq2Bit uut ( bit1, bit2, out );\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/472097485/Chu01/Eq1_01,data/full_repos/permissive/472097485/Eq2Bit\n             data/full_repos/permissive/472097485/Chu01/Eq1_01,data/full_repos/permissive/472097485/Eq2Bit.v\n             data/full_repos/permissive/472097485/Chu01/Eq1_01,data/full_repos/permissive/472097485/Eq2Bit.sv\n             Eq2Bit\n             Eq2Bit.v\n             Eq2Bit.sv\n             obj_dir/Eq2Bit\n             obj_dir/Eq2Bit.v\n             obj_dir/Eq2Bit.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TestEq2Bit;


	reg bit1, bit2;


	wire out;


	Eq2Bit uut ( bit1, bit2, out );

	always begin
	#1 bit1 = !bit1;
	end
	always begin
	#2 bit2 = !bit2;
	end

	initial begin

		bit1 = 0;
		bit2 = 0;


		#10;
	

		$stop;
	end
		
endmodule
module TestEq2Bit;



	reg bit1, bit2;


	wire out;


	Eq2Bit uut ( bit1, bit2, out );

	always begin
	#1 bit1 = !bit1;
	end
	always begin
	#2 bit2 = !bit2;
	end

	initial begin

		bit1 = 0;
		bit2 = 0;


		#10;
	

		$stop;
	end
		
endmodule