data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/fifo_tb.sv
1: b"%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/fifo_tb.sv:30: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n    import rand_verif_pkg::rand_wait;\n           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/fifo_tb.sv:73: Unsupported: wait statements\n        wait (n_checks >= N_CHECKS);\n        ^~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/fifo_tb.sv:78: Unsupported: classes\n    class random_action_t;\n    ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/fifo_tb.sv:80: Unsupported: SystemVerilog 2005 reserved word not implemented: 'constraint'\n        constraint random_action {\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/fifo_tb.sv:80: syntax error, unexpected IDENTIFIER\n        constraint random_action {\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/fifo_tb.sv:81: Unsupported: SystemVerilog 2005 reserved word not implemented: 'dist'\n            action dist {\n                   ^~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/fifo_tb.sv:101: Unsupported: SystemVerilog 2005 reserved word not implemented: 'randomize'\n            rand_success = rand_act.randomize(); assert(rand_success);\n                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/fifo_tb.sv:179: syntax error, unexpected IDENTIFIER\n    clk_rst_gen #(.CLK_PERIOD(TCLK), .RST_CLK_CYCLES(10)) i_clk_rst_gen (\n    ^~~~~~~~~~~\n%Error: Cannot continue\n"
module fifo_tb #(

    parameter int unsigned  N_CHECKS        = 100000,
    parameter time          TCLK            = 10ns,
    parameter time          TA              = TCLK * 1/4,
    parameter time          TT              = TCLK * 3/4
);

    timeunit 1ns;
    timeprecision 10ps;

    logic       clk,
                rst_n;

    logic [3:0] done;

    clk_rst_gen #(.CLK_PERIOD(TCLK), .RST_CLK_CYCLES(10)) i_clk_rst_gen (
        .clk_o    (clk),
        .rst_no   (rst_n)
    );

    fifo_inst_tb #(
        .FALL_THROUGH   (1'b0),
        .DEPTH          (8),
        .N_CHECKS       (N_CHECKS),
        .TA             (TA),
        .TT             (TT)
    ) i_tb_8 (
        .clk_i  (clk),
        .rst_ni (rst_n),
        .done_o (done[0])
    );

    fifo_inst_tb #(
        .FALL_THROUGH   (1'b1),
        .DEPTH          (8),
        .N_CHECKS       (N_CHECKS),
        .TA             (TA),
        .TT             (TT)
    ) i_tb_ft_8 (
        .clk_i  (clk),
        .rst_ni (rst_n),
        .done_o (done[1])
    );

    fifo_inst_tb #(
        .FALL_THROUGH   (1'b0),
        .DEPTH          (1),
        .N_CHECKS       (N_CHECKS),
        .TA             (TA),
        .TT             (TT)
    ) i_tb_1 (
        .clk_i  (clk),
        .rst_ni (rst_n),
        .done_o (done[2])
    );

    fifo_inst_tb #(
        .FALL_THROUGH   (1'b1),
        .DEPTH          (1),
        .N_CHECKS       (N_CHECKS),
        .TA             (TA),
        .TT             (TT)
    ) i_tb_ft_1 (
        .clk_i  (clk),
        .rst_ni (rst_n),
        .done_o (done[3])
    );

    initial begin
        wait ((&done));
        $finish();
    end

endmodule
module fifo_tb #(

    parameter int unsigned  N_CHECKS        = 100000,
    parameter time          TCLK            = 10ns,
    parameter time          TA              = TCLK * 1/4,
    parameter time          TT              = TCLK * 3/4
);


    timeunit 1ns;
    timeprecision 10ps;

    logic       clk,
                rst_n;

    logic [3:0] done;

    clk_rst_gen #(.CLK_PERIOD(TCLK), .RST_CLK_CYCLES(10)) i_clk_rst_gen (
        .clk_o    (clk),
        .rst_no   (rst_n)
    );

    fifo_inst_tb #(
        .FALL_THROUGH   (1'b0),
        .DEPTH          (8),
        .N_CHECKS       (N_CHECKS),
        .TA             (TA),
        .TT             (TT)
    ) i_tb_8 (
        .clk_i  (clk),
        .rst_ni (rst_n),
        .done_o (done[0])
    );

    fifo_inst_tb #(
        .FALL_THROUGH   (1'b1),
        .DEPTH          (8),
        .N_CHECKS       (N_CHECKS),
        .TA             (TA),
        .TT             (TT)
    ) i_tb_ft_8 (
        .clk_i  (clk),
        .rst_ni (rst_n),
        .done_o (done[1])
    );

    fifo_inst_tb #(
        .FALL_THROUGH   (1'b0),
        .DEPTH          (1),
        .N_CHECKS       (N_CHECKS),
        .TA             (TA),
        .TT             (TT)
    ) i_tb_1 (
        .clk_i  (clk),
        .rst_ni (rst_n),
        .done_o (done[2])
    );

    fifo_inst_tb #(
        .FALL_THROUGH   (1'b1),
        .DEPTH          (1),
        .N_CHECKS       (N_CHECKS),
        .TA             (TA),
        .TT             (TT)
    ) i_tb_ft_1 (
        .clk_i  (clk),
        .rst_ni (rst_n),
        .done_o (done[3])
    );

    initial begin
        wait ((&done));
        $finish();
    end

endmodule