data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/top_double_ram_sy.v
1: b"%Error: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/top_double_ram_sy.v:45: Cannot find file containing module: 'div_clock'\ndiv_clock my_div_clk(clk, rst_clk, clk_div);\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM,data/full_repos/permissive/426072575/div_clock\n             data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM,data/full_repos/permissive/426072575/div_clock.v\n             data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM,data/full_repos/permissive/426072575/div_clock.sv\n             div_clock\n             div_clock.v\n             div_clock.sv\n             obj_dir/div_clock\n             obj_dir/div_clock.v\n             obj_dir/div_clock.sv\n%Error: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/top_double_ram_sy.v:47: Cannot find file containing module: 'debounce'\ndebounce mydebounce(clk, cs, rst, rst_clk, load, cs_o, rst_o, rst_clk_o, load_o);\n^~~~~~~~\n%Error: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/top_double_ram_sy.v:51: Cannot find file containing module: 'fpga_double_ram_sy'\nfpga_double_ram_sy my_double_ram_sy(\n^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module top_double_ram_sy(
clk, rst, cs, 
din_a_0, addr_a_0, dout_a, we_a, oe_a,
din_b_0, addr_b_0, dout_b, we_b, oe_b,
rst_clk,
load
    );
    
parameter DATA_WIDTH = 3;
parameter ADDR_WIDTH = 3;
parameter RAM_DEPTH = DATA_WIDTH;

input clk, rst, cs;
input [ADDR_WIDTH-1:0] addr_a_0, addr_b_0;
input [DATA_WIDTH-1:0]  din_a_0, din_b_0;
output [DATA_WIDTH-1:0]  dout_a, dout_b;
input we_a, oe_a, we_b, oe_b;
input rst_clk;
input load;
wire rst_o, cs_o, rst_clk_o, load_o;

wire clk_div;
div_clock my_div_clk(clk, rst_clk, clk_div);

debounce mydebounce(clk, cs, rst, rst_clk, load, cs_o, rst_o, rst_clk_o, load_o);



fpga_double_ram_sy my_double_ram_sy(
    clk, rst_o, cs_o,
    din_a_0, addr_a_0, dout_a, we_a, oe_a,
    din_b_0, addr_b_0, dout_b, we_b, oe_b,
    load_o
);

endmodule
module top_double_ram_sy(
clk, rst, cs, 
din_a_0, addr_a_0, dout_a, we_a, oe_a,
din_b_0, addr_b_0, dout_b, we_b, oe_b,
rst_clk,
load
    );

    
parameter DATA_WIDTH = 3;
parameter ADDR_WIDTH = 3;
parameter RAM_DEPTH = DATA_WIDTH;

input clk, rst, cs;
input [ADDR_WIDTH-1:0] addr_a_0, addr_b_0;
input [DATA_WIDTH-1:0]  din_a_0, din_b_0;
output [DATA_WIDTH-1:0]  dout_a, dout_b;
input we_a, oe_a, we_b, oe_b;
input rst_clk;
input load;
wire rst_o, cs_o, rst_clk_o, load_o;

wire clk_div;
div_clock my_div_clk(clk, rst_clk, clk_div);

debounce mydebounce(clk, cs, rst, rst_clk, load, cs_o, rst_o, rst_clk_o, load_o);



fpga_double_ram_sy my_double_ram_sy(
    clk, rst_o, cs_o,
    din_a_0, addr_a_0, dout_a, we_a, oe_a,
    din_b_0, addr_b_0, dout_b, we_b, oe_b,
    load_o
);

endmodule