data/full_repos/permissive/47956074/rtl/cmsdk_ahb_ram.v
1: b"%Error: data/full_repos/permissive/47956074/rtl/cmsdk_ahb_ram.v:80: Cannot find file containing module: 'ahb_to_ssram'\n     ahb_to_ssram  #(.AW(AW)) U_AHB_TO_SSRAM\n     ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/47956074/rtl,data/full_repos/permissive/47956074/ahb_to_ssram\n             data/full_repos/permissive/47956074/rtl,data/full_repos/permissive/47956074/ahb_to_ssram.v\n             data/full_repos/permissive/47956074/rtl,data/full_repos/permissive/47956074/ahb_to_ssram.sv\n             ahb_to_ssram\n             ahb_to_ssram.v\n             ahb_to_ssram.sv\n             obj_dir/ahb_to_ssram\n             obj_dir/ahb_to_ssram.v\n             obj_dir/ahb_to_ssram.sv\n%Error: data/full_repos/permissive/47956074/rtl/cmsdk_ahb_ram.v:141: Cannot find file containing module: 'bytewrite_ram_32bits'\n   bytewrite_ram_32bits\n   ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module cmsdk_ahb_ram(

   HREADYOUT, HRDATA, HRESP,

   HCLK, HRESETn, HSEL, HADDR, HTRANS, HSIZE, HWRITE, HWDATA, HREADY
   );

   parameter AW       = 16;
   parameter ROM      = 0;
   parameter filename = "";






   input            HCLK;
   input            HRESETn;

   input            HSEL;
   input [AW-1:0]   HADDR;
   input [1:0]      HTRANS;
   input [2:0]      HSIZE;
   input            HWRITE;
   input [31:0]     HWDATA;
   input            HREADY;

   output           HREADYOUT;
   output [31:0]    HRDATA;
   output           HRESP;







   wire [AW-1:0]        ahb_sram_addr;
   wire [31:0]          ahb_sram_din;
   wire [3:0]           ahb_sram_wb;
   wire [31:0]          sram_ahb_dout;


   wire [3:0]           ahb_sram_wb_qual;


     ahb_to_ssram  #(.AW(AW)) U_AHB_TO_SSRAM
  (
   .ahb_sram_we                         (),
   .ahb_sram_en                         (),
   .ahb_sram_enb                        (),


   .HREADYOUT                           (HREADYOUT),
   .HRDATA                              (HRDATA[31:0]),
   .HRESP                               (HRESP),
   .ahb_sram_addr                       (ahb_sram_addr[AW-1:0]),
   .ahb_sram_wb                         (ahb_sram_wb[3:0]),
   .ahb_sram_din                        (ahb_sram_din[31:0]),

   .HCLK                                (HCLK),
   .HRESETn                             (HRESETn),
   .HSEL                                (HSEL),
   .HADDR                               (HADDR[AW-1:0]),
   .HTRANS                              (HTRANS[1:0]),
   .HSIZE                               (HSIZE[2:0]),
   .HWRITE                              (HWRITE),
   .HWDATA                              (HWDATA[31:0]),
   .HREADY                              (HREADY),
   .sram_ahb_dout                       (sram_ahb_dout[31:0]));


   assign ahb_sram_wb_qual = ahb_sram_wb & {4{!ROM}};






   bytewrite_ram_32bits
   #(.SIZE(1<<(AW-2)),.ADDR_WIDTH(AW-2))
   U_RAM (


          .dout                         (sram_ahb_dout[31:0]),

          .clk                          (HCLK),
          .we                           (ahb_sram_wb[3:0]),
          .addr                         (ahb_sram_addr[AW-1:2]),
          .din                          (ahb_sram_din[31:0]));






endmodule
module cmsdk_ahb_ram(

   HREADYOUT, HRDATA, HRESP,

   HCLK, HRESETn, HSEL, HADDR, HTRANS, HSIZE, HWRITE, HWDATA, HREADY
   );


   parameter AW       = 16;
   parameter ROM      = 0;
   parameter filename = "";






   input            HCLK;
   input            HRESETn;

   input            HSEL;
   input [AW-1:0]   HADDR;
   input [1:0]      HTRANS;
   input [2:0]      HSIZE;
   input            HWRITE;
   input [31:0]     HWDATA;
   input            HREADY;

   output           HREADYOUT;
   output [31:0]    HRDATA;
   output           HRESP;







   wire [AW-1:0]        ahb_sram_addr;
   wire [31:0]          ahb_sram_din;
   wire [3:0]           ahb_sram_wb;
   wire [31:0]          sram_ahb_dout;


   wire [3:0]           ahb_sram_wb_qual;


     ahb_to_ssram  #(.AW(AW)) U_AHB_TO_SSRAM
  (
   .ahb_sram_we                         (),
   .ahb_sram_en                         (),
   .ahb_sram_enb                        (),


   .HREADYOUT                           (HREADYOUT),
   .HRDATA                              (HRDATA[31:0]),
   .HRESP                               (HRESP),
   .ahb_sram_addr                       (ahb_sram_addr[AW-1:0]),
   .ahb_sram_wb                         (ahb_sram_wb[3:0]),
   .ahb_sram_din                        (ahb_sram_din[31:0]),

   .HCLK                                (HCLK),
   .HRESETn                             (HRESETn),
   .HSEL                                (HSEL),
   .HADDR                               (HADDR[AW-1:0]),
   .HTRANS                              (HTRANS[1:0]),
   .HSIZE                               (HSIZE[2:0]),
   .HWRITE                              (HWRITE),
   .HWDATA                              (HWDATA[31:0]),
   .HREADY                              (HREADY),
   .sram_ahb_dout                       (sram_ahb_dout[31:0]));


   assign ahb_sram_wb_qual = ahb_sram_wb & {4{!ROM}};






   bytewrite_ram_32bits
   #(.SIZE(1<<(AW-2)),.ADDR_WIDTH(AW-2))
   U_RAM (


          .dout                         (sram_ahb_dout[31:0]),

          .clk                          (HCLK),
          .we                           (ahb_sram_wb[3:0]),
          .addr                         (ahb_sram_addr[AW-1:2]),
          .din                          (ahb_sram_din[31:0]));






endmodule