data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/had/rtl/ct_had_etm_if.v
data/verilator_xmls/e74b2d0d-153c-4f34-9e53-4a9191abecd4.xml
module ct_had_etm_if(
  cpurst_b,
  event_clk,
  x_enter_dbg_req,
  x_enter_dbg_req_i,
  x_enter_dbg_req_o,
  x_enter_dbg_req_o_ff,
  x_event_clk_en,
  x_exit_dbg_req,
  x_exit_dbg_req_i,
  x_exit_dbg_req_o,
  x_exit_dbg_req_o_ff
);



input        cpurst_b;            
input        event_clk;           
input        x_enter_dbg_req;     
input        x_enter_dbg_req_o;   
input        x_exit_dbg_req;      
input        x_exit_dbg_req_o;    
output       x_enter_dbg_req_i;   
output       x_enter_dbg_req_o_ff; 
output       x_event_clk_en;      
output       x_exit_dbg_req_i;    
output       x_exit_dbg_req_o_ff; 


reg          x_enter_dbg_req_i;   
reg          x_enter_dbg_req_o_ff; 
reg          x_exit_dbg_req_i;    
reg          x_exit_dbg_req_o_ff; 


wire         cpurst_b;            
wire         event_clk;           
wire         x_enter_dbg_req;     
wire         x_enter_dbg_req_o;   
wire         x_event_clk_en;      
wire         x_exit_dbg_req;      
wire         x_exit_dbg_req_o;    



















always @ (posedge event_clk or negedge cpurst_b)
begin
  if (!cpurst_b) begin
    x_enter_dbg_req_o_ff <= 1'b0;
    x_exit_dbg_req_o_ff  <= 1'b0;
  end
  else begin
    x_enter_dbg_req_o_ff <= x_enter_dbg_req_o;
    x_exit_dbg_req_o_ff  <= x_exit_dbg_req_o;
  end
end











always @ (posedge event_clk or negedge cpurst_b)
begin
  if (!cpurst_b) begin
    x_enter_dbg_req_i <= 1'b0;
    x_exit_dbg_req_i  <= 1'b0;
  end
  else begin
    x_enter_dbg_req_i <= x_enter_dbg_req;
    x_exit_dbg_req_i  <= x_exit_dbg_req;
  end
end

assign x_event_clk_en = x_exit_dbg_req_o_ff | x_exit_dbg_req_o
                      | x_enter_dbg_req_o_ff | x_enter_dbg_req_o
                      | x_exit_dbg_req_i | x_exit_dbg_req
                      | x_enter_dbg_req_i | x_enter_dbg_req;







endmodule
module ct_had_etm_if(
  cpurst_b,
  event_clk,
  x_enter_dbg_req,
  x_enter_dbg_req_i,
  x_enter_dbg_req_o,
  x_enter_dbg_req_o_ff,
  x_event_clk_en,
  x_exit_dbg_req,
  x_exit_dbg_req_i,
  x_exit_dbg_req_o,
  x_exit_dbg_req_o_ff
);




input        cpurst_b;            
input        event_clk;           
input        x_enter_dbg_req;     
input        x_enter_dbg_req_o;   
input        x_exit_dbg_req;      
input        x_exit_dbg_req_o;    
output       x_enter_dbg_req_i;   
output       x_enter_dbg_req_o_ff; 
output       x_event_clk_en;      
output       x_exit_dbg_req_i;    
output       x_exit_dbg_req_o_ff; 


reg          x_enter_dbg_req_i;   
reg          x_enter_dbg_req_o_ff; 
reg          x_exit_dbg_req_i;    
reg          x_exit_dbg_req_o_ff; 


wire         cpurst_b;            
wire         event_clk;           
wire         x_enter_dbg_req;     
wire         x_enter_dbg_req_o;   
wire         x_event_clk_en;      
wire         x_exit_dbg_req;      
wire         x_exit_dbg_req_o;    



















always @ (posedge event_clk or negedge cpurst_b)
begin
  if (!cpurst_b) begin
    x_enter_dbg_req_o_ff <= 1'b0;
    x_exit_dbg_req_o_ff  <= 1'b0;
  end
  else begin
    x_enter_dbg_req_o_ff <= x_enter_dbg_req_o;
    x_exit_dbg_req_o_ff  <= x_exit_dbg_req_o;
  end
end











always @ (posedge event_clk or negedge cpurst_b)
begin
  if (!cpurst_b) begin
    x_enter_dbg_req_i <= 1'b0;
    x_exit_dbg_req_i  <= 1'b0;
  end
  else begin
    x_enter_dbg_req_i <= x_enter_dbg_req;
    x_exit_dbg_req_i  <= x_exit_dbg_req;
  end
end

assign x_event_clk_en = x_exit_dbg_req_o_ff | x_exit_dbg_req_o
                      | x_enter_dbg_req_o_ff | x_enter_dbg_req_o
                      | x_exit_dbg_req_i | x_exit_dbg_req
                      | x_enter_dbg_req_i | x_enter_dbg_req;







endmodule