data/full_repos/permissive/458737381/src/verilog-parser/tests/delay.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/delay.v:6: Unsupported or unknown PLI call: $monitor\n  $monitor (\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/delay.v:10: Unsupported: Ignoring delay on this delayed statement.\n  #10 in = 1; \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/delay.v:11: Unsupported: Ignoring delay on this delayed statement.\n  #10 in = 0; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/delay.v:12: Unsupported: Ignoring delay on this delayed statement.\n  #20 $finish; \n  ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module delay();
 reg in; 
 wire rise_delay, fall_delay, all_delay; 
  
 initial begin 
  $monitor (
    "Time=%g in=%b rise_delay=%b fall_delay=%b all_delay=%b", 
    $time, in, rise_delay, fall_delay, all_delay);
  in = 0; 
  #10 in = 1; 
  #10 in = 0; 
  #20 $finish; 
 end 
  
 buf #(1,0)U_rise (rise_delay,in); 
 buf #(0,1)U_fall (fall_delay,in); 
 buf #1 U_all (all_delay,in); 
  
endmodule
module delay();

 reg in; 
 wire rise_delay, fall_delay, all_delay; 
  
 initial begin 
  $monitor (
    "Time=%g in=%b rise_delay=%b fall_delay=%b all_delay=%b", 
    $time, in, rise_delay, fall_delay, all_delay);
  in = 0; 
  #10 in = 1; 
  #10 in = 0; 
  #20 $finish; 
 end 
  
 buf #(1,0)U_rise (rise_delay,in); 
 buf #(0,1)U_fall (fall_delay,in); 
 buf #1 U_all (all_delay,in); 
  
endmodule