data/full_repos/permissive/487082250/sources/slowClock.v
data/verilator_xmls/ffb347c1-c569-41a9-be03-8663e5bfc9f4.xml
module slowClock(
    input clk_in,
    output reg clk_out
    );
    reg [20:0] period_count = 0;
    always @ (posedge clk_in)
        if (period_count!= 500000)
        begin
        period_count= period_count + 1;
        clk_out = 0;
        end
    else
    begin
        period_count = 0;
        clk_out = 1;
        end
endmodule
module slowClock(
    input clk_in,
    output reg clk_out
    );

    reg [20:0] period_count = 0;
    always @ (posedge clk_in)
        if (period_count!= 500000)
        begin
        period_count= period_count + 1;
        clk_out = 0;
        end
    else
    begin
        period_count = 0;
        clk_out = 1;
        end
endmodule