data/full_repos/permissive/489075769/master_ar.v
1: b'%Error: data/full_repos/permissive/489075769/master_ar.v:323: Cannot find file containing module: \'read_address_slave\'\nread_address_slave s (.ACLK(ACLK), .ARESETn(rst), .i_ARREADY(ar_ready), .o_ARREADY(o_ARREADY), .ARVALID(ARVALID), .i_ARADDR(i_ARADDR), .o_ARADDR(o_ARADDR));\n^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489075769,data/full_repos/permissive/489075769/read_address_slave\n             data/full_repos/permissive/489075769,data/full_repos/permissive/489075769/read_address_slave.v\n             data/full_repos/permissive/489075769,data/full_repos/permissive/489075769/read_address_slave.sv\n             read_address_slave\n             read_address_slave.v\n             read_address_slave.sv\n             obj_dir/read_address_slave\n             obj_dir/read_address_slave.v\n             obj_dir/read_address_slave.sv\n%Error: data/full_repos/permissive/489075769/master_ar.v:325: Cannot find file containing module: \'read_data_slave\'\nread_data_slave s1 (.ACLK(ACLK), .ARESETn(rst), .i_RVALID(r_valid), .o_RVALID(o_RVALID), .RREADY(RREADY), .i_RDATA(out_data), .o_RDATA(o_RDATA), .i_RRESP(rresp), .o_RRESP(o_RRESP));\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489075769/master_ar.v:235: Cannot find file containing module: \'read_address_master\'\nread_address_master read_addr_m (.ACLK(ACLK), .ARESETn(rst), .i_ARVALID(ar_valid), .o_ARVALID(o_ARVALID), .ARREADY(r_ready), .i_ARADDR(ar_addr), .o_ARADDR(o_ARADDR), .ARPROT(prot));\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489075769/master_ar.v:237: Cannot find file containing module: \'read_data_master\'\nread_data_master read_data_m (.ACLK(ACLK), .ARESETn(rst) ,.RVALID(RVALID), .i_RREADY(r_ready), .o_RREADY(o_RREADY), .i_RDATA(i_RDATA), .o_RDATA(o_RDATA), .i_RRESP(i_RRESP), .o_RRESP(o_RRESP));\n^~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/489075769/master_ar.v:152: Output port connection \'o_RRESP\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'i_RRESP\' generates 2 bits.\n                                                                    : ... In instance master_ar\nslave_ar s (ACLK, rst, write, read,o_ARVALID,o_RREADY, o_ARADDR, ARREADY, RVALID,i_RRESP, s_ARADDR, i_RDATA);                                         \n                                                                                 ^~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 4 error(s), 1 warning(s)\n'
module master(
		input ACLK,
		input rst,
		input write,
		input read,

		input RVALID,

		input [31:0] i_RDATA,
		input [1:0] i_RRESP,

		output o_ARVALID,
		output [31:0] o_ARADDR,
		output o_RREADY,
		output [1:0] o_RRESP,

		output [31:0] o_RDATA
		);
reg aw_valid;
reg ar_valid;
reg w_valid;
reg r_ready;
reg wresp_ready;

reg [31:0] ar_addr;
reg [31:0] aw_addr;
reg [31:0] out_data;
reg [31:0] in_data;
reg [2:0] prot;
reg [1:0] in_rresp;
reg [1:0] in_wresp;

wire ar_valid_out;

always @(ACLK) begin

if (write) begin

aw_valid <= 1'b1;
aw_addr <= 32'hffffffff;

w_valid <= 1'b1;
out_data <= 32'h11111111;

wresp_ready <= 1'b1;

end

else begin
aw_valid <= 1'b0;
aw_addr <= 32'h00000000;

w_valid <= 1'b0;
out_data <= 32'h00000000;

wresp_ready <= 1'b0;
end

if(read) begin

prot <= 3'b000;

ar_valid <= 1'b1;
ar_addr <= 32'hffffffff;

r_ready <= 1'b1;

end

else begin

ar_valid <= 1'b0;
ar_addr <= 32'h00000000;

r_ready <= 1'b0;

end
end

read_address_master read_addr_m (.ACLK(ACLK), .ARESETn(rst), .i_ARVALID(ar_valid), .o_ARVALID(o_ARVALID), .ARREADY(r_ready), .i_ARADDR(ar_addr), .o_ARADDR(o_ARADDR), .ARPROT(prot));

read_data_master read_data_m (.ACLK(ACLK), .ARESETn(rst) ,.RVALID(RVALID), .i_RREADY(r_ready), .o_RREADY(o_RREADY), .i_RDATA(i_RDATA), .o_RDATA(o_RDATA), .i_RRESP(i_RRESP), .o_RRESP(o_RRESP));



endmodule
module master(
		input ACLK,
		input rst,
		input write,
		input read,

		input RVALID,

		input [31:0] i_RDATA,
		input [1:0] i_RRESP,

		output o_ARVALID,
		output [31:0] o_ARADDR,
		output o_RREADY,
		output [1:0] o_RRESP,

		output [31:0] o_RDATA
		);

reg aw_valid;
reg ar_valid;
reg w_valid;
reg r_ready;
reg wresp_ready;

reg [31:0] ar_addr;
reg [31:0] aw_addr;
reg [31:0] out_data;
reg [31:0] in_data;
reg [2:0] prot;
reg [1:0] in_rresp;
reg [1:0] in_wresp;

wire ar_valid_out;

always @(ACLK) begin

if (write) begin

aw_valid <= 1'b1;
aw_addr <= 32'hffffffff;

w_valid <= 1'b1;
out_data <= 32'h11111111;

wresp_ready <= 1'b1;

end

else begin
aw_valid <= 1'b0;
aw_addr <= 32'h00000000;

w_valid <= 1'b0;
out_data <= 32'h00000000;

wresp_ready <= 1'b0;
end

if(read) begin

prot <= 3'b000;

ar_valid <= 1'b1;
ar_addr <= 32'hffffffff;

r_ready <= 1'b1;

end

else begin

ar_valid <= 1'b0;
ar_addr <= 32'h00000000;

r_ready <= 1'b0;

end
end

read_address_master read_addr_m (.ACLK(ACLK), .ARESETn(rst), .i_ARVALID(ar_valid), .o_ARVALID(o_ARVALID), .ARREADY(r_ready), .i_ARADDR(ar_addr), .o_ARADDR(o_ARADDR), .ARPROT(prot));

read_data_master read_data_m (.ACLK(ACLK), .ARESETn(rst) ,.RVALID(RVALID), .i_RREADY(r_ready), .o_RREADY(o_RREADY), .i_RDATA(i_RDATA), .o_RDATA(o_RDATA), .i_RRESP(i_RRESP), .o_RRESP(o_RRESP));



endmodule