data/full_repos/permissive/493019833/test/testcase/firrtl/Cvt/sbt/Cvt.v
data/verilator_xmls/69263a2f-2cee-46e0-8501-3159b9b7dab2.xml
module Cvt(
  input        clock,
  input        reset,
  input  [7:0] io_u0,
  input  [7:0] io_s0,
  output [9:0] io_uout_asUInt_u,
  output [9:0] io_uout_asUInt_s,
  output [9:0] io_sout_asSInt_u,
  output [9:0] io_sout_asSInt_s,
  output [9:0] io_sout_neg_u,
  output [9:0] io_sout_neg_s
);
  wire [7:0] _T_21 = io_s0;
  wire [7:0] _T_22 = io_u0;
  wire [7:0] _T_27 = 8'sh0 - $signed(io_u0);
  wire [7:0] _T_31 = 8'sh0 - $signed(io_s0);
  assign io_uout_asUInt_u = {{2'd0}, io_u0};
  assign io_uout_asUInt_s = {{2'd0}, _T_21};
  assign io_sout_asSInt_u = {{2{_T_22[7]}},_T_22};
  assign io_sout_asSInt_s = {{2{io_s0[7]}},io_s0};
  assign io_sout_neg_u = {{2{_T_27[7]}},_T_27};
  assign io_sout_neg_s = {{2{_T_31[7]}},_T_31};
endmodule
module Cvt(
  input        clock,
  input        reset,
  input  [7:0] io_u0,
  input  [7:0] io_s0,
  output [9:0] io_uout_asUInt_u,
  output [9:0] io_uout_asUInt_s,
  output [9:0] io_sout_asSInt_u,
  output [9:0] io_sout_asSInt_s,
  output [9:0] io_sout_neg_u,
  output [9:0] io_sout_neg_s
);

  wire [7:0] _T_21 = io_s0;
  wire [7:0] _T_22 = io_u0;
  wire [7:0] _T_27 = 8'sh0 - $signed(io_u0);
  wire [7:0] _T_31 = 8'sh0 - $signed(io_s0);
  assign io_uout_asUInt_u = {{2'd0}, io_u0};
  assign io_uout_asUInt_s = {{2'd0}, _T_21};
  assign io_sout_asSInt_u = {{2{_T_22[7]}},_T_22};
  assign io_sout_asSInt_s = {{2{io_s0[7]}},io_s0};
  assign io_sout_neg_u = {{2{_T_27[7]}},_T_27};
  assign io_sout_neg_s = {{2{_T_31[7]}},_T_31};
endmodule