data/full_repos/permissive/495910568/rtl/frequency_divider/frequency_divider.v
data/verilator_xmls/2b0ca810-5353-4d17-a844-f495065e9efe.xml
module freq_divider(
    input wire clock_in,
    output reg clock_out
    );

reg[9:0] counter=10'd0;
parameter DIVISOR = 10'd2;





always @(posedge clock_in)
begin
 counter <= counter + 10'd1;
 if(counter>=(DIVISOR-1))
  counter <= 10'd0;

 clock_out <= (counter<DIVISOR/2)?1'b1:1'b0;

end
endmodule
module freq_divider(
    input wire clock_in,
    output reg clock_out
    );


reg[9:0] counter=10'd0;
parameter DIVISOR = 10'd2;





always @(posedge clock_in)
begin
 counter <= counter + 10'd1;
 if(counter>=(DIVISOR-1))
  counter <= 10'd0;

 clock_out <= (counter<DIVISOR/2)?1'b1:1'b0;

end
endmodule