data/full_repos/permissive/458737381/src/verilog-parser/tests/d_latch_switch.v
1: b"%Error-ASSIGNIN: data/full_repos/permissive/458737381/src/verilog-parser/tests/d_latch_switch.v:21: Assigning to input/const variable: 'd'\npmos p1 (d,q,clkn);\n         ^\n%Error-ASSIGNIN: data/full_repos/permissive/458737381/src/verilog-parser/tests/d_latch_switch.v:22: Assigning to input/const variable: 'd'\nnmos n1 (d,q,clk);\n         ^\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module d_latch_switch(clk,d,q);
input clk,d;
output q;

wire clkn, net1, qn;

not_switch i1 (clkn,clk);

pmos p1 (d,q,clkn);
nmos n1 (d,q,clk);

pmos p2 (q,net1,clk);
nmos n2 (q,net1,clkn);

not_switch i2 (qn,q);
not_switch i3 (net1,qn);

endmodule
module d_latch_switch(clk,d,q);

input clk,d;
output q;

wire clkn, net1, qn;

not_switch i1 (clkn,clk);

pmos p1 (d,q,clkn);
nmos n1 (d,q,clk);

pmos p2 (q,net1,clk);
nmos n2 (q,net1,clkn);

not_switch i2 (qn,q);
not_switch i3 (net1,qn);

endmodule