data/full_repos/permissive/413379110/SMPTE_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/413379110/SMPTE_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #1\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/413379110/SMPTE_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #1 RST   <= 0; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/413379110/SMPTE_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = !clk;\n  ^\n%Error: data/full_repos/permissive/413379110/SMPTE_tb.v:23: Cannot find file containing module: \'SMPTE274\'\nSMPTE274 data(\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/413379110,data/full_repos/permissive/413379110/SMPTE274\n             data/full_repos/permissive/413379110,data/full_repos/permissive/413379110/SMPTE274.v\n             data/full_repos/permissive/413379110,data/full_repos/permissive/413379110/SMPTE274.sv\n             SMPTE274\n             SMPTE274.v\n             SMPTE274.sv\n             obj_dir/SMPTE274\n             obj_dir/SMPTE274.v\n             obj_dir/SMPTE274.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module SMPTE274_tb();

reg               clk;
reg               RST;
reg               EN;
reg  [ 9 : 0]     i_data_Y, i_data_C;
wire [11 : 0]     PIX_CNT_o;
wire [10 : 0]     LINE_CNT_o;
wire [ 9 : 0]     Y_data_o, C_data_o ;
wire              VSYNC_o;
wire              HSYNC_o;
wire              DATA_RQ_o;


integer           data_file    ;
integer           scan_file    ;
reg  [ 9 : 0 ]    captured_data;
`define NULL      0 


SMPTE274 data(
  .CLK_74M                ( clk        ),
  .RST                    ( RST        ),
  .EN                     ( EN         ),
  .i_data_Y               ( i_data_Y   ),
  .i_data_C               ( i_data_C   ),
  .PIX_CNT_o              ( PIX_CNT_o  ),
  .LINE_CNT_o             ( LINE_CNT_o ),
  .Y_data_o               ( Y_data_o   ),
  .C_data_o               ( C_data_o   ),
  .VSYNC_o                ( VSYNC_o    ),
  .HSYNC_o                ( HSYNC_o    ),
  .DATA_RQ_o              ( DATA_RQ_o  )
);

initial
begin
  data_file = $fopen("out.dat", "r");
  if (data_file == `NULL)
  begin
      $display("data_file handle was NULL");
      $finish;
  end
  
  #1
  RST      <= 1;
  clk      <= 0;
  EN       <= 0;
  i_data_Y <= 10'h011;
  i_data_C <= 10'h0CC;
  #1 RST   <= 0; 
  EN       <= 1;   
end

always
begin
  #1 clk = !clk;
end

always @(posedge clk) 
begin
  if  (DATA_RQ_o)
    scan_file = $fscanf(data_file, "%d\n", captured_data);
  else
    captured_data <= 10'h000;     
  if (!$feof(data_file)) 
  begin
    i_data_Y <= captured_data;
  end
end

    
endmodule
module SMPTE274_tb();


reg               clk;
reg               RST;
reg               EN;
reg  [ 9 : 0]     i_data_Y, i_data_C;
wire [11 : 0]     PIX_CNT_o;
wire [10 : 0]     LINE_CNT_o;
wire [ 9 : 0]     Y_data_o, C_data_o ;
wire              VSYNC_o;
wire              HSYNC_o;
wire              DATA_RQ_o;


integer           data_file    ;
integer           scan_file    ;
reg  [ 9 : 0 ]    captured_data;
`define NULL      0 


SMPTE274 data(
  .CLK_74M                ( clk        ),
  .RST                    ( RST        ),
  .EN                     ( EN         ),
  .i_data_Y               ( i_data_Y   ),
  .i_data_C               ( i_data_C   ),
  .PIX_CNT_o              ( PIX_CNT_o  ),
  .LINE_CNT_o             ( LINE_CNT_o ),
  .Y_data_o               ( Y_data_o   ),
  .C_data_o               ( C_data_o   ),
  .VSYNC_o                ( VSYNC_o    ),
  .HSYNC_o                ( HSYNC_o    ),
  .DATA_RQ_o              ( DATA_RQ_o  )
);

initial
begin
  data_file = $fopen("out.dat", "r");
  if (data_file == `NULL)
  begin
      $display("data_file handle was NULL");
      $finish;
  end
  
  #1
  RST      <= 1;
  clk      <= 0;
  EN       <= 0;
  i_data_Y <= 10'h011;
  i_data_C <= 10'h0CC;
  #1 RST   <= 0; 
  EN       <= 1;   
end

always
begin
  #1 clk = !clk;
end

always @(posedge clk) 
begin
  if  (DATA_RQ_o)
    scan_file = $fscanf(data_file, "%d\n", captured_data);
  else
    captured_data <= 10'h000;     
  if (!$feof(data_file)) 
  begin
    i_data_Y <= captured_data;
  end
end

    
endmodule