data/full_repos/permissive/431687600/Proc_SRC/top_risc_proc.v
1: b'%Error: data/full_repos/permissive/431687600/Proc_SRC/top_risc_proc.v:15: Cannot find include file: ALU.v\n`include "ALU.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/431687600/Proc_SRC,data/full_repos/permissive/431687600/ALU.v\n             data/full_repos/permissive/431687600/Proc_SRC,data/full_repos/permissive/431687600/ALU.v.v\n             data/full_repos/permissive/431687600/Proc_SRC,data/full_repos/permissive/431687600/ALU.v.sv\n             ALU.v\n             ALU.v.v\n             ALU.v.sv\n             obj_dir/ALU.v\n             obj_dir/ALU.v.v\n             obj_dir/ALU.v.sv\n%Error: data/full_repos/permissive/431687600/Proc_SRC/top_risc_proc.v:16: Cannot find include file: program_counter.v\n`include "program_counter.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/431687600/Proc_SRC/top_risc_proc.v:17: Cannot find include file: control.v\n`include "control.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/431687600/Proc_SRC/top_risc_proc.v:18: Cannot find include file: instruction_memory.v\n`include "instruction_memory.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/431687600/Proc_SRC/top_risc_proc.v:19: Cannot find include file: register_file.v\n`include "register_file.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module top_risc_proc(
	input clk,reset);
	wire w_memWrite,w_memRead,w_PCop,w_checkbranch;
	wire [12:0] w_instruction,w_ALUresult,w_dataA,w_dataB, w_PCcurr, w_PC;
	wire [8:0] w_branch;
	wire [3:0] w_opcode;
	wire [2:0] w_regDest,w_regAddress1,w_regAddress2;
	
	

	PC u0(
	.clk(clk),
	.reset(reset),
	.i_PCop(w_PCop),
	.i_PC(w_PC),
	.i_Branch(w_branch),
	.o_PCcurr(w_PCcurr) 
	);

	instruction_memory u1(
	 .reset(reset),
	 .i_PCcurr(w_PCcurr),
	 .o_instruction(w_instruction)
	);

	ALU u2(
	 .i_opcode(w_opcode),
	 .i_dataA(w_dataA),
	 .i_dataB(w_dataB),
	 .o_result(w_ALUresult),
	 .o_checkbranch(w_checkbranch)
	 );

	register_file u3(
	 .clk(clk),
	 .reset(reset),
	 .i_memWrite(w_memWrite),
	 .i_memRead(w_memRead),
	 .i_address1(w_regAddress1),
	 .i_address2(w_regAddress2),
	 .i_destReg(w_regDest),
	 .i_ALUresult(w_ALUresult),
	 .o_dataA(w_dataA), 
	 .o_dataB(w_dataB)
	 );


	control u4(
	 .clk(clk),
	 .reset(reset),
	 .i_checkbranch(w_checkbranch),
	 .i_instruction(w_instruction),
	 .o_opcode(w_opcode),                      
	 .o_destination(w_regDest),
	 .o_addr1(w_regAddress1),
	 .o_addr2(w_regAddress2),     
	 .o_branch(w_branch),
	 .o_PC(w_PC),                      
	 .o_memWrite(w_memWrite),
	 .o_memRead(w_memRead),
	 .o_PCop(w_PCop)
	 ); 


endmodule
module top_risc_proc(
	input clk,reset);

	wire w_memWrite,w_memRead,w_PCop,w_checkbranch;
	wire [12:0] w_instruction,w_ALUresult,w_dataA,w_dataB, w_PCcurr, w_PC;
	wire [8:0] w_branch;
	wire [3:0] w_opcode;
	wire [2:0] w_regDest,w_regAddress1,w_regAddress2;
	
	

	PC u0(
	.clk(clk),
	.reset(reset),
	.i_PCop(w_PCop),
	.i_PC(w_PC),
	.i_Branch(w_branch),
	.o_PCcurr(w_PCcurr) 
	);

	instruction_memory u1(
	 .reset(reset),
	 .i_PCcurr(w_PCcurr),
	 .o_instruction(w_instruction)
	);

	ALU u2(
	 .i_opcode(w_opcode),
	 .i_dataA(w_dataA),
	 .i_dataB(w_dataB),
	 .o_result(w_ALUresult),
	 .o_checkbranch(w_checkbranch)
	 );

	register_file u3(
	 .clk(clk),
	 .reset(reset),
	 .i_memWrite(w_memWrite),
	 .i_memRead(w_memRead),
	 .i_address1(w_regAddress1),
	 .i_address2(w_regAddress2),
	 .i_destReg(w_regDest),
	 .i_ALUresult(w_ALUresult),
	 .o_dataA(w_dataA), 
	 .o_dataB(w_dataB)
	 );


	control u4(
	 .clk(clk),
	 .reset(reset),
	 .i_checkbranch(w_checkbranch),
	 .i_instruction(w_instruction),
	 .o_opcode(w_opcode),                      
	 .o_destination(w_regDest),
	 .o_addr1(w_regAddress1),
	 .o_addr2(w_regAddress2),     
	 .o_branch(w_branch),
	 .o_PC(w_PC),                      
	 .o_memWrite(w_memWrite),
	 .o_memRead(w_memRead),
	 .o_PCop(w_PCop)
	 ); 


endmodule