data/full_repos/permissive/493212017/processor/sail-core/verilog/adder.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/493212017/processor/sail-core/verilog/adder.v:56: Multiple top level modules\n                                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                              : ... Top module \'adder\'\nmodule adder(input1, input2, out);\n       ^~~~~\n                                                                                              : ... Top module \'full_adder\'\nmodule full_adder(carry_in, input1, input2, out);\n       ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/493212017/processor/sail-core/verilog/adder.v:62: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'carry_in\' generates 1 bits.\n                                                                                           : ... In instance full_adder\n assign  out = input1 + input2 + carry_in;\n                               ^\n%Error: Exiting due to 2 warning(s)\n'
module full_adder(carry_in, input1, input2, out);
	input		carry_in;
	input [31:0]	input1;
	input [31:0]	input2;
	output [31:0]	out;

	assign		out = input1 + input2 + carry_in;
endmodule
module full_adder(carry_in, input1, input2, out);

	input		carry_in;
	input [31:0]	input1;
	input [31:0]	input2;
	output [31:0]	out;

	assign		out = input1 + input2 + carry_in;
endmodule