data/full_repos/permissive/46343463/src/ProgramCounter.v
data/verilator_xmls/cf60db29-340a-49ee-85cd-62899ea31d61.xml
module ProgramCounter
(
    input				clk,
    input				rst,
    input				start,
    input               we,
	input				stall,
    input		[31:0]	addr_i,
    output reg	[31:0]	addr_o
);

	always @ (posedge clk or negedge rst) begin
		if(~rst)
		addr_o <= 32'b0;
		else begin
			if(start) begin
				if(!stall && we)
					addr_o <= addr_i;
			end
			else
				addr_o <= 32'bz;
		end
	end

endmodule
module ProgramCounter
(
    input				clk,
    input				rst,
    input				start,
    input               we,
	input				stall,
    input		[31:0]	addr_i,
    output reg	[31:0]	addr_o
);


	always @ (posedge clk or negedge rst) begin
		if(~rst)
		addr_o <= 32'b0;
		else begin
			if(start) begin
				if(!stall && we)
					addr_o <= addr_i;
			end
			else
				addr_o <= 32'bz;
		end
	end

endmodule