data/full_repos/permissive/52881156/fpga_files/catapult_proj/Background Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1/cycle_mgc_ioport_v2001.v
1: b'%Error: Cannot find file containing module: Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156\n        ... Looked in:\n             data/full_repos/permissive/52881156/fpga_files/catapult_proj/Background/Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156\n             data/full_repos/permissive/52881156/fpga_files/catapult_proj/Background/Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156.v\n             data/full_repos/permissive/52881156/fpga_files/catapult_proj/Background/Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156.sv\n             Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156\n             Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156.v\n             Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156.sv\n             obj_dir/Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156\n             obj_dir/Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156.v\n             obj_dir/Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/52881156/fpga_files/catapult_proj/Background\n%Error: Cannot find file containing module: Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1/cycle_mgc_ioport_v2001.v\n%Error: Exiting due to 3 error(s)\n'
module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);

    parameter integer rscid   = 0;
    parameter integer width   = 8;
    parameter integer sz_width = 8;
    parameter integer fifo_sz = 8;
    parameter integer log2_sz = 3;
    parameter         ph_clk  = 1'b1;
    parameter         ph_en   = 1'b1;
    parameter         ph_arst = 1'b1;
    parameter         ph_srst = 1'b1;
    parameter integer pwropt  = 0;

    input              clk;
    input              en;
    input              arst;
    input              srst;
    input              ldin;
    output             vdin;
    output [width-1:0] din;
    input              ldout;
    output             vdout;
    input  [width-1:0] dout;
    output [sz_width-1:0]      size;
    input              req_size;


    mgc_out_fifo_wait_core
    #(
        .rscid    (rscid),
        .width    (width),
        .sz_width (sz_width),
        .fifo_sz  (fifo_sz),
        .ph_clk   (ph_clk),
        .ph_en    (ph_en),
        .ph_arst  (ph_arst),
        .ph_srst  (ph_srst),
        .ph_log2  (log2_sz),
        .pwropt   (pwropt)
    )
    FIFO
    (
        .clk     (clk),
        .en      (en),
        .arst    (arst),
        .srst    (srst),
        .ld      (ldout),
        .vd      (vdout),
        .d       (dout),
        .lz      (vdin),
        .vz      (ldin),
        .z       (din),
        .size    (size)
    );

endmodule
module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size);


    parameter integer rscid   = 0;
    parameter integer width   = 8;
    parameter integer sz_width = 8;
    parameter integer fifo_sz = 8;
    parameter integer log2_sz = 3;
    parameter         ph_clk  = 1'b1;
    parameter         ph_en   = 1'b1;
    parameter         ph_arst = 1'b1;
    parameter         ph_srst = 1'b1;
    parameter integer pwropt  = 0;

    input              clk;
    input              en;
    input              arst;
    input              srst;
    input              ldin;
    output             vdin;
    output [width-1:0] din;
    input              ldout;
    output             vdout;
    input  [width-1:0] dout;
    output [sz_width-1:0]      size;
    input              req_size;


    mgc_out_fifo_wait_core
    #(
        .rscid    (rscid),
        .width    (width),
        .sz_width (sz_width),
        .fifo_sz  (fifo_sz),
        .ph_clk   (ph_clk),
        .ph_en    (ph_en),
        .ph_arst  (ph_arst),
        .ph_srst  (ph_srst),
        .ph_log2  (log2_sz),
        .pwropt   (pwropt)
    )
    FIFO
    (
        .clk     (clk),
        .en      (en),
        .arst    (arst),
        .srst    (srst),
        .ld      (ldout),
        .vd      (vdout),
        .d       (dout),
        .lz      (vdin),
        .vz      (ldin),
        .z       (din),
        .size    (size)
    );

endmodule