data/full_repos/permissive/476411248/PSC_Block_Array.v
1: b"%Error: data/full_repos/permissive/476411248/PSC_Block_Array.v:46: Cannot find file containing module: 'Parallel_Serial_Converter'\n        Parallel_Serial_Converter # (TILE_DIM, MAX_WORD_LENGTH, MAX_WORD_LENGTH) ps_convert_block\n        ^~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/476411248,data/full_repos/permissive/476411248/Parallel_Serial_Converter\n             data/full_repos/permissive/476411248,data/full_repos/permissive/476411248/Parallel_Serial_Converter.v\n             data/full_repos/permissive/476411248,data/full_repos/permissive/476411248/Parallel_Serial_Converter.sv\n             Parallel_Serial_Converter\n             Parallel_Serial_Converter.v\n             Parallel_Serial_Converter.sv\n             obj_dir/Parallel_Serial_Converter\n             obj_dir/Parallel_Serial_Converter.v\n             obj_dir/Parallel_Serial_Converter.sv\n%Error: Exiting due to 1 error(s)\n"
module PSC_Block_Array
    #(parameter MAX_WORD_LENGTH = 16, parameter[7:0] TILE_DIM = 8'h02)(
        input clk, 
        input reset, 
        input [1:0] mode,
        input start,
        output finish,
        input [8*TILE_DIM-1:0] serial_data_in,
        input [4*MAX_WORD_LENGTH*TILE_DIM-1:0] parallel_data_in,
        output[8*TILE_DIM-1:0] serial_data_out,
        output[4*MAX_WORD_LENGTH*TILE_DIM-1:0] parallel_data_out
    );
    

genvar gi;

generate
    for (gi=0; gi<TILE_DIM; gi=gi+1) begin : psc_block
        Parallel_Serial_Converter # (TILE_DIM, MAX_WORD_LENGTH, MAX_WORD_LENGTH) ps_convert_block
        (
            clk,  
            reset, 
            mode,
            start,
            finish,
            serial_data_in[8*gi+:8],
            parallel_data_in[4*MAX_WORD_LENGTH*gi+:4*MAX_WORD_LENGTH],
            serial_data_out[8*gi+:8],
            parallel_data_out[4*MAX_WORD_LENGTH*gi+:4*MAX_WORD_LENGTH]
        );
    end
endgenerate
endmodule
module PSC_Block_Array
    #(parameter MAX_WORD_LENGTH = 16, parameter[7:0] TILE_DIM = 8'h02)(
        input clk, 
        input reset, 
        input [1:0] mode,
        input start,
        output finish,
        input [8*TILE_DIM-1:0] serial_data_in,
        input [4*MAX_WORD_LENGTH*TILE_DIM-1:0] parallel_data_in,
        output[8*TILE_DIM-1:0] serial_data_out,
        output[4*MAX_WORD_LENGTH*TILE_DIM-1:0] parallel_data_out
    );

    

genvar gi;

generate
    for (gi=0; gi<TILE_DIM; gi=gi+1) begin : psc_block
        Parallel_Serial_Converter # (TILE_DIM, MAX_WORD_LENGTH, MAX_WORD_LENGTH) ps_convert_block
        (
            clk,  
            reset, 
            mode,
            start,
            finish,
            serial_data_in[8*gi+:8],
            parallel_data_in[4*MAX_WORD_LENGTH*gi+:4*MAX_WORD_LENGTH],
            serial_data_out[8*gi+:8],
            parallel_data_out[4*MAX_WORD_LENGTH*gi+:4*MAX_WORD_LENGTH]
        );
    end
endgenerate
endmodule