data/full_repos/permissive/482975152/PipelinedProcessor.srcs/sources_1/new/DReg.v
data/verilator_xmls/4837a4e4-2013-47a1-9663-87699880a029.xml
module DReg(
    input clk,
    input EN,
    input CLR,
    input [31:0] IMRD,
    input [31:0] PCp1F,
    output reg [31:0] InstrD,
    output reg [31:0] PCp1D
    );
    
    always @(posedge clk) begin
        if (CLR) begin
            InstrD <= 32'b00000000000000000000000000100000;
        end
        else if (EN == 1) begin
            InstrD <= InstrD;
            PCp1D <= PCp1D;
        end     
        else begin
            InstrD <= IMRD;
            PCp1D <= PCp1F;
        end
    end
endmodule
module DReg(
    input clk,
    input EN,
    input CLR,
    input [31:0] IMRD,
    input [31:0] PCp1F,
    output reg [31:0] InstrD,
    output reg [31:0] PCp1D
    );

    
    always @(posedge clk) begin
        if (CLR) begin
            InstrD <= 32'b00000000000000000000000000100000;
        end
        else if (EN == 1) begin
            InstrD <= InstrD;
            PCp1D <= PCp1D;
        end     
        else begin
            InstrD <= IMRD;
            PCp1D <= PCp1F;
        end
    end
endmodule