data/full_repos/permissive/497604366/cpu/cpu.srcs/sources_1/new/not_gate.v
data/verilator_xmls/509e2bd0-0ffb-45c5-97b5-b1c67adf97f1.xml
module not_gate(
    input clk,
    output reg clk_output
    );
    
    always @(*) begin
        clk_output <= ~clk;
    end
endmodule
module not_gate(
    input clk,
    output reg clk_output
    );

    
    always @(*) begin
        clk_output <= ~clk;
    end
endmodule