data/full_repos/permissive/434837003/test/specify.v
1: b"%Error: data/full_repos/permissive/434837003/test/specify.v:28: Unsupported or unknown PLI call: $q\n        PATHPULSE$clr[2]$q = (0,4),\n                        ^~\n%Error: data/full_repos/permissive/434837003/test/specify.v:78: syntax error, unexpected '(', expecting IDENTIFIER\nposdff_udp (ffout, clock, data, preset, clear, notifier);\n            ^~~~~\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module dff(q, qbar, clock, data, preset, clear);

output q, qbar;
input clock, data, preset, clear;

reg notifier;

and (enable, preset, clear);
not (qbar, ffout);
buf (q, ffout);
posdff_udp (ffout, clock, data, preset, clear, notifier);

specify

    specparam tSU = 10, tHD = 1, tPW = 25, tWPC = 10, tREC = 5;

    specparam tPLHc = 4:6:9 , tPHLc = 5:8:11;
    specparam tPLHpc = 3:5:6 , tPHLpc = 4:7:9;


    (clock *> q,qbar) = (tPLHc, tPHLc);
    (preset,clear *> q,qbar) = (tPLHpc, tPHLpc);


    $setup(data, posedge clock &&& enable, tSU, notifier);

    $hold(posedge clock, data &&& enable, tHD, notifier);

    $period(posedge clock, tPW, notifier);

    $width(negedge preset, tWPC, 0, notifier);
    $width(negedge clear, tWPC, 0, notifier);

    $recovery(posedge preset, posedge clock, tREC, notifier);
    $recovery(posedge clear, posedge clock, tREC, notifier);

    $setup( data, posedge clk &&& clr, 10 ) ;

    $setup( data, posedge clk &&& (~clr), 10 ) ;
    $setup( data, posedge clk &&& (clr===0), 10 );
    $setup( data, edge[01, 0x, x1] clk &&& (clr===0), 10 );
endspecify

endmodule
module dff(q, qbar, clock, data, preset, clear);


output q, qbar;
input clock, data, preset, clear;

reg notifier;

and (enable, preset, clear);
not (qbar, ffout);
buf (q, ffout);
posdff_udp (ffout, clock, data, preset, clear, notifier);

specify

    specparam tSU = 10, tHD = 1, tPW = 25, tWPC = 10, tREC = 5;

    specparam tPLHc = 4:6:9 , tPHLc = 5:8:11;
    specparam tPLHpc = 3:5:6 , tPHLpc = 4:7:9;


    (clock *> q,qbar) = (tPLHc, tPHLc);
    (preset,clear *> q,qbar) = (tPLHpc, tPHLpc);


    $setup(data, posedge clock &&& enable, tSU, notifier);

    $hold(posedge clock, data &&& enable, tHD, notifier);

    $period(posedge clock, tPW, notifier);

    $width(negedge preset, tWPC, 0, notifier);
    $width(negedge clear, tWPC, 0, notifier);

    $recovery(posedge preset, posedge clock, tREC, notifier);
    $recovery(posedge clear, posedge clock, tREC, notifier);

    $setup( data, posedge clk &&& clr, 10 ) ;

    $setup( data, posedge clk &&& (~clr), 10 ) ;
    $setup( data, posedge clk &&& (clr===0), 10 );
    $setup( data, edge[01, 0x, x1] clk &&& (clr===0), 10 );
endspecify

endmodule