data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_dpram_en_w1st.v
data/verilator_xmls/559fcc62-75b0-496d-8b3d-36c42bd4f3aa.xml
module or1k_dpram_en_w1st
#(
  parameter ADDR_WIDTH    = 32,
  parameter DATA_WIDTH    = 32,
  parameter CLEAR_ON_INIT =  0
)
(

  input                       clk_a,
  input                       en_a,
  input                       we_a,
  input      [ADDR_WIDTH-1:0] addr_a,
  input      [DATA_WIDTH-1:0] din_a,
  output reg [DATA_WIDTH-1:0] dout_a,

  input                       clk_b,
  input                       en_b,
  input                       we_b,
  input      [ADDR_WIDTH-1:0] addr_b,
  input      [DATA_WIDTH-1:0] din_b,
  output reg [DATA_WIDTH-1:0] dout_b
);

  reg [DATA_WIDTH-1:0] mem[0:((1<<ADDR_WIDTH)-1)];


 `ifndef SYNTHESIS

  generate
  if (CLEAR_ON_INIT) begin : clear_ram
    integer idx;
    initial begin

      dout_a = {DATA_WIDTH{1'b0}};
      dout_b = {DATA_WIDTH{1'b0}};

      for (idx=0; idx < (1<<ADDR_WIDTH); idx=idx+1)
        mem[idx] = {DATA_WIDTH{1'b0}};
    end
  end
  endgenerate

 `endif


  always @(posedge clk_a) begin
    if(en_a) begin
      if (we_a) begin
        mem[addr_a] <= din_a;
        dout_a      <= din_a;
      end
      else begin
        dout_a <= mem[addr_a];
      end
    end
  end


  always @(posedge clk_b) begin
    if(en_b) begin
      if (we_b) begin
        mem[addr_b] <= din_b;
        dout_b      <= din_b;
      end
      else begin
        dout_b <= mem[addr_b];
      end
    end
  end

endmodule
module or1k_dpram_en_w1st
#(
  parameter ADDR_WIDTH    = 32,
  parameter DATA_WIDTH    = 32,
  parameter CLEAR_ON_INIT =  0
)
(

  input                       clk_a,
  input                       en_a,
  input                       we_a,
  input      [ADDR_WIDTH-1:0] addr_a,
  input      [DATA_WIDTH-1:0] din_a,
  output reg [DATA_WIDTH-1:0] dout_a,

  input                       clk_b,
  input                       en_b,
  input                       we_b,
  input      [ADDR_WIDTH-1:0] addr_b,
  input      [DATA_WIDTH-1:0] din_b,
  output reg [DATA_WIDTH-1:0] dout_b
);


  reg [DATA_WIDTH-1:0] mem[0:((1<<ADDR_WIDTH)-1)];


 `ifndef SYNTHESIS

  generate
  if (CLEAR_ON_INIT) begin : clear_ram
    integer idx;
    initial begin

      dout_a = {DATA_WIDTH{1'b0}};
      dout_b = {DATA_WIDTH{1'b0}};

      for (idx=0; idx < (1<<ADDR_WIDTH); idx=idx+1)
        mem[idx] = {DATA_WIDTH{1'b0}};
    end
  end
  endgenerate

 `endif


  always @(posedge clk_a) begin
    if(en_a) begin
      if (we_a) begin
        mem[addr_a] <= din_a;
        dout_a      <= din_a;
      end
      else begin
        dout_a <= mem[addr_a];
      end
    end
  end


  always @(posedge clk_b) begin
    if(en_b) begin
      if (we_b) begin
        mem[addr_b] <= din_b;
        dout_b      <= din_b;
      end
      else begin
        dout_b <= mem[addr_b];
      end
    end
  end

endmodule