data/full_repos/permissive/481044442/BDCDrv/clk_1hz.v
data/verilator_xmls/bbb8d82c-a352-4d8b-b381-8259fc6843ed.xml
module clk1hz(clk,reset,clk_1hz);
input clk;
input reset;
output clk_1hz;



reg [27:0] cnt_1hz;
reg clk_freq_1hz;
always@(posedge clk or posedge reset)
begin
	if(reset) begin
				cnt_1hz<=28'd0;
				clk_freq_1hz=1'b0;
				end
	else begin
			if(cnt_1hz==28'd24576000) begin
										clk_freq_1hz=~clk_freq_1hz;
										cnt_1hz<=28'd0;
										end
			else
				cnt_1hz<=cnt_1hz+1'b1;
			end
end
assign clk_1hz=clk_freq_1hz;
endmodule
module clk1hz(clk,reset,clk_1hz);

input clk;
input reset;
output clk_1hz;



reg [27:0] cnt_1hz;
reg clk_freq_1hz;
always@(posedge clk or posedge reset)
begin
	if(reset) begin
				cnt_1hz<=28'd0;
				clk_freq_1hz=1'b0;
				end
	else begin
			if(cnt_1hz==28'd24576000) begin
										clk_freq_1hz=~clk_freq_1hz;
										cnt_1hz<=28'd0;
										end
			else
				cnt_1hz<=cnt_1hz+1'b1;
			end
end
assign clk_1hz=clk_freq_1hz;
endmodule