data/full_repos/permissive/474294847/rtl-tests/uart/uart-reciever-tb.v
1: b'%Error: data/full_repos/permissive/474294847/rtl-tests/uart/uart-reciever-tb.v:1: Cannot find include file: uart-reciever.v\n`include "uart-reciever.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/474294847/rtl-tests/uart,data/full_repos/permissive/474294847/uart-reciever.v\n             data/full_repos/permissive/474294847/rtl-tests/uart,data/full_repos/permissive/474294847/uart-reciever.v.v\n             data/full_repos/permissive/474294847/rtl-tests/uart,data/full_repos/permissive/474294847/uart-reciever.v.sv\n             uart-reciever.v\n             uart-reciever.v.v\n             uart-reciever.v.sv\n             obj_dir/uart-reciever.v\n             obj_dir/uart-reciever.v.v\n             obj_dir/uart-reciever.v.sv\n%Error: data/full_repos/permissive/474294847/rtl-tests/uart/uart-reciever-tb.v:20: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("./build/rtl-sim/vcd/uart-reciever.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/474294847/rtl-tests/uart/uart-reciever-tb.v:21: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/474294847/rtl-tests/uart/uart-reciever-tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module uart_reciever_tb;

reg clk;
reg rx;
wire rx_done;
wire [7:0] rx_byte;

uart_reciever dut
(
    clk,
    rx,
    rx_done,
    rx_byte
);

initial
begin
    $dumpfile("./build/rtl-sim/vcd/uart-reciever.vcd");
    $dumpvars;
end

integer i;
initial
begin
    clk = 0;
    rx = 1;

    for (i = 'd0; i < 10000; i = i + 1)
    begin
        if (i == 4)
            rx = 0;
        else if (i >= 5690)
            rx = 1;
        
        clk = ~clk; 
        #100;
    end
end

endmodule
module uart_reciever_tb;


reg clk;
reg rx;
wire rx_done;
wire [7:0] rx_byte;

uart_reciever dut
(
    clk,
    rx,
    rx_done,
    rx_byte
);

initial
begin
    $dumpfile("./build/rtl-sim/vcd/uart-reciever.vcd");
    $dumpvars;
end

integer i;
initial
begin
    clk = 0;
    rx = 1;

    for (i = 'd0; i < 10000; i = i + 1)
    begin
        if (i == 4)
            rx = 0;
        else if (i >= 5690)
            rx = 1;
        
        clk = ~clk; 
        #100;
    end
end

endmodule