data/full_repos/permissive/499944578/rtl/src/utils/delaySignal.v
1: b'%Warning-SELRANGE: data/full_repos/permissive/499944578/rtl/src/utils/delaySignal.v:20: Selection index out of range: 1:1 outside 0:0\n                                                                                      : ... In instance delaySignal\n                delayedSignal[i] <= delayedSignal[i-1];\n                                                 ^\n                   ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module delaySignal#(
    parameter NUM_CYCLES = 1,
    parameter DATA_WIDTH = 1

)(
    input  wire clk,
    input  wire resetn, 
    input  wire [DATA_WIDTH-1:0] in, 
    output wire  [DATA_WIDTH-1:0] out
);
    reg [NUM_CYCLES-1:0][DATA_WIDTH-1:0] delayedSignal;
   
    genvar i;
    generate
    for (i=0; i < NUM_CYCLES; i=i+1) begin
        always @(posedge clk or negedge resetn) begin
            if (resetn == 1'b0) begin
                delayedSignal[i] <= 'b0;
            end else begin
                delayedSignal[i] <= delayedSignal[i-1];
            end
        end
        
    end
    endgenerate
   
    assign out = delayedSignal[NUM_CYCLES-1];
endmodule
module delaySignal#(
    parameter NUM_CYCLES = 1,
    parameter DATA_WIDTH = 1

)(
    input  wire clk,
    input  wire resetn, 
    input  wire [DATA_WIDTH-1:0] in, 
    output wire  [DATA_WIDTH-1:0] out
);

    reg [NUM_CYCLES-1:0][DATA_WIDTH-1:0] delayedSignal;
   
    genvar i;
    generate
    for (i=0; i < NUM_CYCLES; i=i+1) begin
        always @(posedge clk or negedge resetn) begin
            if (resetn == 1'b0) begin
                delayedSignal[i] <= 'b0;
            end else begin
                delayedSignal[i] <= delayedSignal[i-1];
            end
        end
        
    end
    endgenerate
   
    assign out = delayedSignal[NUM_CYCLES-1];
endmodule