data/full_repos/permissive/429850924/tb_shift_adder.v
1: b'%Error: data/full_repos/permissive/429850924/tb_shift_adder.v:11: Unsupported or unknown PLI call: $dumpfile\n    initial begin $dumpfile("test.vcd"); $dumpvars(0,tb); end\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/429850924/tb_shift_adder.v:11: Unsupported or unknown PLI call: $dumpvars\n    initial begin $dumpfile("test.vcd"); $dumpvars(0,tb); end\n                                         ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/429850924/tb_shift_adder.v:15: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/429850924/tb_shift_adder.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #5\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429850924/tb_shift_adder.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #160 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429850924/tb_shift_adder.v:24: Unsupported: Ignoring delay on this delayed statement.\n    initial clk = 1\'b1; always #5 clk =~ clk;\n                               ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;
    reg clk, reset, load;
    reg [15:0] a, b, out;

    wire [15:0] op, contents_a, contents_b;
    wire carry;

    shift_adder addr(clk, reset, load, a, b, contents_a, contents_b, op, carry);
    
    initial begin $dumpfile("test.vcd"); $dumpvars(0,tb); end
    initial begin
        reset = 1'b1;
        load = 1'b0;
        #5
        reset = 1'b0;
        load = 1'b1;
        a = 16'b0101011101001001;
        b = 16'b1000001110101001;
        #5
        load = 1'b0;
        #160 $finish;
    end
    initial clk = 1'b1; always #5 clk =~ clk;
endmodule
module tb;

    reg clk, reset, load;
    reg [15:0] a, b, out;

    wire [15:0] op, contents_a, contents_b;
    wire carry;

    shift_adder addr(clk, reset, load, a, b, contents_a, contents_b, op, carry);
    
    initial begin $dumpfile("test.vcd"); $dumpvars(0,tb); end
    initial begin
        reset = 1'b1;
        load = 1'b0;
        #5
        reset = 1'b0;
        load = 1'b1;
        a = 16'b0101011101001001;
        b = 16'b1000001110101001;
        #5
        load = 1'b0;
        #160 $finish;
    end
    initial clk = 1'b1; always #5 clk =~ clk;
endmodule