data/full_repos/permissive/444555755/mp4/hdl/given_cache/cache.sv
1: b"%Error: data/full_repos/permissive/444555755/mp4/hdl/given_cache/cache.sv:41: Cannot find file containing module: 'cache_control'\ncache_control control(.*);\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/444555755/mp4/hdl/given_cache,data/full_repos/permissive/444555755/cache_control\n             data/full_repos/permissive/444555755/mp4/hdl/given_cache,data/full_repos/permissive/444555755/cache_control.v\n             data/full_repos/permissive/444555755/mp4/hdl/given_cache,data/full_repos/permissive/444555755/cache_control.sv\n             cache_control\n             cache_control.v\n             cache_control.sv\n             obj_dir/cache_control\n             obj_dir/cache_control.v\n             obj_dir/cache_control.sv\n%Error: data/full_repos/permissive/444555755/mp4/hdl/given_cache/cache.sv:42: Cannot find file containing module: 'cache_datapath'\ncache_datapath #(s_offset, s_index) datapath(.*);\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/444555755/mp4/hdl/given_cache/cache.sv:44: Cannot find file containing module: 'line_adapter'\nline_adapter bus (\n^~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module cache #(
  parameter s_offset = 5,
  parameter s_index = 3,
  parameter s_tag = 32 - s_offset - s_index,
  parameter s_mask = 2**s_offset,
  parameter s_line = 8*s_mask,
  parameter num_sets = 2**s_index
)(
  input clk,

  input logic pmem_resp,
  input logic [255:0] pmem_rdata,
  output logic [31:0] pmem_address,
  output logic [255:0] pmem_wdata,
  output logic pmem_read,
  output logic pmem_write,


  input logic mem_read,
  input logic mem_write,
  input logic [3:0] mem_byte_enable_cpu,
  input logic [31:0] mem_address,
  input logic [31:0] mem_wdata_cpu,
  output logic mem_resp,
  output logic [31:0] mem_rdata_cpu
);

logic tag_load;
logic valid_load;
logic dirty_load;
logic dirty_in;
logic dirty_out;

logic hit;
logic [1:0] writing;

logic [s_line - 1:0] mem_wdata;
logic [s_line - 1:0] mem_rdata;
logic [31:0] mem_byte_enable;

cache_control control(.*);
cache_datapath #(s_offset, s_index) datapath(.*);

line_adapter bus (
    .mem_wdata_line(mem_wdata),
    .mem_rdata_line(mem_rdata),
    .mem_wdata(mem_wdata_cpu),
    .mem_rdata(mem_rdata_cpu),
    .mem_byte_enable(mem_byte_enable_cpu),
    .mem_byte_enable_line(mem_byte_enable),
    .address(mem_address)
);

endmodule
module cache #(
  parameter s_offset = 5,
  parameter s_index = 3,
  parameter s_tag = 32 - s_offset - s_index,
  parameter s_mask = 2**s_offset,
  parameter s_line = 8*s_mask,
  parameter num_sets = 2**s_index
)(
  input clk,

  input logic pmem_resp,
  input logic [255:0] pmem_rdata,
  output logic [31:0] pmem_address,
  output logic [255:0] pmem_wdata,
  output logic pmem_read,
  output logic pmem_write,


  input logic mem_read,
  input logic mem_write,
  input logic [3:0] mem_byte_enable_cpu,
  input logic [31:0] mem_address,
  input logic [31:0] mem_wdata_cpu,
  output logic mem_resp,
  output logic [31:0] mem_rdata_cpu
);


logic tag_load;
logic valid_load;
logic dirty_load;
logic dirty_in;
logic dirty_out;

logic hit;
logic [1:0] writing;

logic [s_line - 1:0] mem_wdata;
logic [s_line - 1:0] mem_rdata;
logic [31:0] mem_byte_enable;

cache_control control(.*);
cache_datapath #(s_offset, s_index) datapath(.*);

line_adapter bus (
    .mem_wdata_line(mem_wdata),
    .mem_rdata_line(mem_rdata),
    .mem_wdata(mem_wdata_cpu),
    .mem_rdata(mem_rdata_cpu),
    .mem_byte_enable(mem_byte_enable_cpu),
    .mem_byte_enable_line(mem_byte_enable),
    .address(mem_address)
);

endmodule