data/full_repos/permissive/451577625/system/divider_32.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/451577625/system/divider_32.v:119: Unsupported: Ignoring delay on this delayed statement.\n  forever #10 clk = ~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/451577625/system/divider_32.v:18: Cannot find file containing module: \'adder_32\'\n adder_32 invert_dividend (.in_x (~in_dividend),\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/adder_32\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/adder_32.v\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/adder_32.sv\n             adder_32\n             adder_32.v\n             adder_32.sv\n             obj_dir/adder_32\n             obj_dir/adder_32.v\n             obj_dir/adder_32.sv\n%Error: data/full_repos/permissive/451577625/system/divider_32.v:24: Cannot find file containing module: \'adder_32\'\n adder_32 invert_divisor (.in_x (~in_divisor),\n ^~~~~~~~\n%Error: data/full_repos/permissive/451577625/system/divider_32.v:30: Cannot find file containing module: \'adder_32\'\n adder_32 invert_quotient(.in_x (~w_pos_quotient),\n ^~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module divider_32_tb;
	
	reg [31:0] dividend, divisor;
	reg reset;
	wire [31:0] quotient, remainder;
	
	parameter pos_pos = 0;
	parameter pos_neg = 1;
	parameter neg_pos = 2;
	parameter neg_neg = 3;
	
	integer count = 0;
	integer state;
	
	reg clk;
	
	divider_32 DUT ( .clk (clk),
		.in_reset (reset),
		.in_dividend (dividend),
		.in_divisor (divisor),
		.out_quotient (quotient),
		.out_remainder (remainder));
	
	initial begin
		state = 0;
		clk = 0;
		reset = 1;
		forever #10 clk = ~clk;
	end
	
	always @(posedge clk) begin
		count = count + 1;
		reset = 0;
		if (count == 34) begin
			count = 0;
			state = state + 1;
			reset = 1;
		end
	end
	
	always @(state) begin
		case(state)
			pos_pos : begin
				dividend = 32'h1e; divisor = 32'h4;
			end
			pos_neg : begin
				dividend = 32'ha; divisor = 32'hFFFFFFFD;
			end
			neg_pos : begin
				dividend = 32'hFFFFFE0C; divisor = 32'h3;
			end
			neg_neg : begin
				dividend = 32'hFFFFFF9C; divisor = 32'hFFFFFFF7;
			end
		endcase
	end
	

endmodule
module divider_32_tb;

	
	reg [31:0] dividend, divisor;
	reg reset;
	wire [31:0] quotient, remainder;
	
	parameter pos_pos = 0;
	parameter pos_neg = 1;
	parameter neg_pos = 2;
	parameter neg_neg = 3;
	
	integer count = 0;
	integer state;
	
	reg clk;
	
	divider_32 DUT ( .clk (clk),
		.in_reset (reset),
		.in_dividend (dividend),
		.in_divisor (divisor),
		.out_quotient (quotient),
		.out_remainder (remainder));
	
	initial begin
		state = 0;
		clk = 0;
		reset = 1;
		forever #10 clk = ~clk;
	end
	
	always @(posedge clk) begin
		count = count + 1;
		reset = 0;
		if (count == 34) begin
			count = 0;
			state = state + 1;
			reset = 1;
		end
	end
	
	always @(state) begin
		case(state)
			pos_pos : begin
				dividend = 32'h1e; divisor = 32'h4;
			end
			pos_neg : begin
				dividend = 32'ha; divisor = 32'hFFFFFFFD;
			end
			neg_pos : begin
				dividend = 32'hFFFFFE0C; divisor = 32'h3;
			end
			neg_neg : begin
				dividend = 32'hFFFFFF9C; divisor = 32'hFFFFFFF7;
			end
		endcase
	end
	

endmodule