data/full_repos/permissive/515598112/3_Circuits/02_Sequential_Logic/03_Shift_Registers/02_Left_or_right_rotator.v
data/verilator_xmls/3d6eeef5-9419-4bef-8dd6-75f835657ab8.xml
module top_module(
    input clk,
    input load,
    input [1:0] ena,
    input [99:0] data,
    output reg [99:0] q
);
    
    always @(posedge clk) begin
        if (load == 1'b1) begin
            q <= data;
        end
        else begin
            case (ena)
                2'b01: q <= {q[0], q[99:1]};
                2'b10: q <= {q[98:0], q[99]};
                default: q <= q;
            endcase
        end
    end

endmodule
module top_module(
    input clk,
    input load,
    input [1:0] ena,
    input [99:0] data,
    output reg [99:0] q
);

    
    always @(posedge clk) begin
        if (load == 1'b1) begin
            q <= data;
        end
        else begin
            case (ena)
                2'b01: q <= {q[0], q[99:1]};
                2'b10: q <= {q[98:0], q[99]};
                default: q <= q;
            endcase
        end
    end

endmodule