data/full_repos/permissive/43856783/Ultrasonico/peripheral_ult.v
1: b'%Warning-WIDTH: data/full_repos/permissive/43856783/Ultrasonico/peripheral_ult.v:31: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s COND generates 4 bits.\n                                                                                   : ... In instance peripheral_mult\n   4\'h0:  s = (cs && wr) ? 4\'b0001 : 4\'b000 ;  \n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/43856783/Ultrasonico/peripheral_ult.v:33: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s COND generates 4 bits.\n                                                                                   : ... In instance peripheral_mult\n   4\'h2:  s = (cs && rd) ? 4\'b0010 : 4\'b000 ;  \n            ^\n%Warning-WIDTH: data/full_repos/permissive/43856783/Ultrasonico/peripheral_ult.v:34: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s COND generates 4 bits.\n                                                                                   : ... In instance peripheral_mult\n   4\'h4:  s = (cs && rd) ? 4\'b0100 : 4\'b000 ;  \n            ^\n%Warning-WIDTH: data/full_repos/permissive/43856783/Ultrasonico/peripheral_ult.v:35: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s COND generates 4 bits.\n                                                                                   : ... In instance peripheral_mult\n   4\'h6:  s = (cs && rd) ? 4\'b1000 : 4\'b000 ;  \n            ^\n%Warning-WIDTH: data/full_repos/permissive/43856783/Ultrasonico/peripheral_ult.v:36: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                   : ... In instance peripheral_mult\n   default:  s = 4\'b000 ;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/43856783/Ultrasonico/peripheral_ult.v:41: Operator CASE expects 4 bits on the Case expression, but Case expression\'s VARREF \'s\' generates 2 bits.\n                                                                                   : ... In instance peripheral_mult\n  case (s)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/43856783/Ultrasonico/peripheral_ult.v:50: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                   : ... In instance peripheral_mult\n   4\'b0100:  d_out     = value[7:0] ;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/43856783/Ultrasonico/peripheral_ult.v:51: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                   : ... In instance peripheral_mult\n   4\'b1000:  d_out     = value[15:8] ;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/43856783/Ultrasonico/peripheral_ult.v:48: Operator CASE expects 4 bits on the Case expression, but Case expression\'s VARREF \'s\' generates 2 bits.\n                                                                                   : ... In instance peripheral_mult\n  case (s)\n  ^~~~\n%Error: data/full_repos/permissive/43856783/Ultrasonico/peripheral_ult.v:56: Cannot find file containing module: \'ultrasonic\'\n ultrasonic ult ( \n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43856783/Ultrasonico,data/full_repos/permissive/43856783/ultrasonic\n             data/full_repos/permissive/43856783/Ultrasonico,data/full_repos/permissive/43856783/ultrasonic.v\n             data/full_repos/permissive/43856783/Ultrasonico,data/full_repos/permissive/43856783/ultrasonic.sv\n             ultrasonic\n             ultrasonic.v\n             ultrasonic.sv\n             obj_dir/ultrasonic\n             obj_dir/ultrasonic.v\n             obj_dir/ultrasonic.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n'
module peripheral_mult(
	input 			clk,
	input 			rst,
	input [15:0]	d_in,
	input 			cs,
	input [3:0]		addr,
	input 			rd,
	input 			wr,
	input 			signal,
	
	output reg [15:0] d_out
	);
	


	reg [1:0] 		s;
    wire [15:0] 	value ; 
    wire 			done ;
	
	reg enable ;



	always @(*) begin
		case (addr)
			4'h0:		s = (cs && wr) ? 4'b0001 : 4'b000 ;
		
			4'h2:		s = (cs && rd) ? 4'b0010 : 4'b000 ;
			4'h4:		s = (cs && rd) ? 4'b0100 : 4'b000 ;
			4'h6:		s = (cs && rd) ? 4'b1000 : 4'b000 ;
			default: 	s = 4'b000 ;
		endcase
	end

	always @(negedge clk) begin
		case (s)
			4'b0001:	 	enable 		= 1 ;
			default:	d_out   	= 0 ;
		endcase
	end
	
	always @(negedge clk) begin
		case (s)
			4'b0010:	d_out[0] 	= done ;
			4'b0100: 	d_out    	= value[7:0] ;
			4'b1000: 	d_out    	= value[15:8] ;
			default:	d_out   	= 0 ;
		endcase
	end

	ultrasonic ult ( 
		.clk(clk), 
		.enable(enable), 
		.signal(signal) , 
		.value(value) , 
		.done(done) 
		);

endmodule
module peripheral_mult(
	input 			clk,
	input 			rst,
	input [15:0]	d_in,
	input 			cs,
	input [3:0]		addr,
	input 			rd,
	input 			wr,
	input 			signal,
	
	output reg [15:0] d_out
	);

	


	reg [1:0] 		s;
    wire [15:0] 	value ; 
    wire 			done ;
	
	reg enable ;



	always @(*) begin
		case (addr)
			4'h0:		s = (cs && wr) ? 4'b0001 : 4'b000 ;
		
			4'h2:		s = (cs && rd) ? 4'b0010 : 4'b000 ;
			4'h4:		s = (cs && rd) ? 4'b0100 : 4'b000 ;
			4'h6:		s = (cs && rd) ? 4'b1000 : 4'b000 ;
			default: 	s = 4'b000 ;
		endcase
	end

	always @(negedge clk) begin
		case (s)
			4'b0001:	 	enable 		= 1 ;
			default:	d_out   	= 0 ;
		endcase
	end
	
	always @(negedge clk) begin
		case (s)
			4'b0010:	d_out[0] 	= done ;
			4'b0100: 	d_out    	= value[7:0] ;
			4'b1000: 	d_out    	= value[15:8] ;
			default:	d_out   	= 0 ;
		endcase
	end

	ultrasonic ult ( 
		.clk(clk), 
		.enable(enable), 
		.signal(signal) , 
		.value(value) , 
		.done(done) 
		);

endmodule