data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/full_add.v
data/verilator_xmls/14d12b6a-ffe4-47ef-aaec-933e0f37e7ba.xml
module full_add(
    output  reg sum = 1'b0,
    output  reg co  = 1'b0,
    input       x,
    input       y,
    input       ci
);

    always @* begin : proc_fa
        sum <= x ^ y ^ ci;
        co  <= x & y | x & ci | y & ci;
    end

endmodule
module full_add(
    output  reg sum = 1'b0,
    output  reg co  = 1'b0,
    input       x,
    input       y,
    input       ci
);


    always @* begin : proc_fa
        sum <= x ^ y ^ ci;
        co  <= x & y | x & ci | y & ci;
    end

endmodule