data/full_repos/permissive/497039278/tb/pro_tb3.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tb3.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 0; wr <= 1; wdata <= 32\'h10F00080;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tb3.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 1; wr <= 1; wdata <= 32\'h10F10081;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tb3.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 2; wr <= 1; wdata <= 32\'h10F20082;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tb3.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 3; wr <= 1; wdata <= 32\'h10F30083;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tb3.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 4; wr <= 1; wdata <= 32\'h10F40084;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tb3.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 5; wr <= 1; wdata <= 32\'h10F50085;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tb3.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 6; wr <= 1; wdata <= 32\'h10F60086;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tb3.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 7; wr <= 1; wdata <= 32\'h10F70087;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tb3.v:52: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 8; wr <= 1; wdata <= 32\'h20010000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tb3.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 9; wr <= 1; wdata <= 32\'h21230000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tb3.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 10;wr <= 1; wdata <= 32\'h22450000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tb3.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 11;wr <= 1; wdata <= 32\'h23670000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tb3.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 0; wr <= 0; wdata <= 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tb3.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #10         working <= 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tb3.v:58: Unsupported: Ignoring delay on this delayed statement.\n    #500        $stop;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tb3.v:60: Unsupported: Ignoring delay on this delayed statement.\nalways #10 clock = ~clock;\n       ^\n%Error: data/full_repos/permissive/497039278/tb/pro_tb3.v:62: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("pro_tb3.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/497039278/tb/pro_tb3.v:63: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 16 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pro_tb2;
reg             clock;
reg[31:0]        addr;
reg             wr;
reg[31:0]       wdata;
reg             working;
reg[3:0]        rID;

wire[31:0]      valE;
wire[31:0]      r0, r1, r2, r3, r4, r5, r6, r7;
wire[31:0]      rdata;
reg             flg = 0;
wire[2:0]       cc;






processor processor(
                clock,
                addr,
                wr,
                wdata,
                working,
                rID,







                valE,
                r0, r1, r2, r3, r4, r5, r6, r7,
                rdata,
                cc

);

initial begin
    clock <= 0; addr <= 0; wr <= 0; wdata <= 0; working <= 0;
    #20         addr <= 0; wr <= 1; wdata <= 32'h10F00080;
    #20         addr <= 1; wr <= 1; wdata <= 32'h10F10081;
    #20         addr <= 2; wr <= 1; wdata <= 32'h10F20082;
    #20         addr <= 3; wr <= 1; wdata <= 32'h10F30083;
    #20         addr <= 4; wr <= 1; wdata <= 32'h10F40084;
    #20         addr <= 5; wr <= 1; wdata <= 32'h10F50085;
    #20         addr <= 6; wr <= 1; wdata <= 32'h10F60086;
    #20         addr <= 7; wr <= 1; wdata <= 32'h10F70087;
    #20         addr <= 8; wr <= 1; wdata <= 32'h20010000;
    #20         addr <= 9; wr <= 1; wdata <= 32'h21230000;
    #20         addr <= 10;wr <= 1; wdata <= 32'h22450000;
    #20         addr <= 11;wr <= 1; wdata <= 32'h23670000;
    #20         addr <= 0; wr <= 0; wdata <= 0;
    #10         working <= 1;
    #500        $stop;
end
always #10 clock = ~clock;
initial begin
    $dumpfile("pro_tb3.vcd");
    $dumpvars;
end
endmodule
module pro_tb2;

reg             clock;
reg[31:0]        addr;
reg             wr;
reg[31:0]       wdata;
reg             working;
reg[3:0]        rID;

wire[31:0]      valE;
wire[31:0]      r0, r1, r2, r3, r4, r5, r6, r7;
wire[31:0]      rdata;
reg             flg = 0;
wire[2:0]       cc;






processor processor(
                clock,
                addr,
                wr,
                wdata,
                working,
                rID,







                valE,
                r0, r1, r2, r3, r4, r5, r6, r7,
                rdata,
                cc

);

initial begin
    clock <= 0; addr <= 0; wr <= 0; wdata <= 0; working <= 0;
    #20         addr <= 0; wr <= 1; wdata <= 32'h10F00080;
    #20         addr <= 1; wr <= 1; wdata <= 32'h10F10081;
    #20         addr <= 2; wr <= 1; wdata <= 32'h10F20082;
    #20         addr <= 3; wr <= 1; wdata <= 32'h10F30083;
    #20         addr <= 4; wr <= 1; wdata <= 32'h10F40084;
    #20         addr <= 5; wr <= 1; wdata <= 32'h10F50085;
    #20         addr <= 6; wr <= 1; wdata <= 32'h10F60086;
    #20         addr <= 7; wr <= 1; wdata <= 32'h10F70087;
    #20         addr <= 8; wr <= 1; wdata <= 32'h20010000;
    #20         addr <= 9; wr <= 1; wdata <= 32'h21230000;
    #20         addr <= 10;wr <= 1; wdata <= 32'h22450000;
    #20         addr <= 11;wr <= 1; wdata <= 32'h23670000;
    #20         addr <= 0; wr <= 0; wdata <= 0;
    #10         working <= 1;
    #500        $stop;
end
always #10 clock = ~clock;
initial begin
    $dumpfile("pro_tb3.vcd");
    $dumpvars;
end
endmodule