data/full_repos/permissive/412284801/adders/add-subtractor/b_addsub_mux.v
data/verilator_xmls/50ede92c-7cac-4913-9d77-13231aeab2cf.xml
module b_addsub_mux(a,b,cin,sel,sum,cout);
    input a,b,cin,sel;
    output reg sum,cout;

    reg x1,o1,x2;
    reg w1,w2;

    always@(*)begin
        if(sel == 1) begin
            w1 = b;
        end else begin
            w1 = ~b;
        end

        x1 = a ^ w1; x2 = a & w1;
        sum = cin ^ x1; o1 = cin & x1;
        cout = o1 | x2;
    end
endmodule
module b_addsub_mux(a,b,cin,sel,sum,cout);

    input a,b,cin,sel;
    output reg sum,cout;

    reg x1,o1,x2;
    reg w1,w2;

    always@(*)begin
        if(sel == 1) begin
            w1 = b;
        end else begin
            w1 = ~b;
        end

        x1 = a ^ w1; x2 = a & w1;
        sum = cin ^ x1; o1 = cin & x1;
        cout = o1 | x2;
    end
endmodule