data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/DAC_offset_to_twos_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/DAC_offset_to_twos_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #H_period;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/DAC_offset_to_twos_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #H_period;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/DAC_offset_to_twos_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #H_period;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/DAC_offset_to_twos_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #H_period;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/DAC_offset_to_twos_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #H_period;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/DAC_offset_to_twos_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #H_period;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/DAC_offset_to_twos_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #H_period;\n    ^\n%Error: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/DAC_offset_to_twos_tb.v:7: Cannot find file containing module: \'DAC_offset_to_twos\'\nDAC_offset_to_twos  #(.WIRE_WIDTH(14)) DACO0 (.data_in(DATA_IN), .data_out(DATA_OUT));\n^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb,data/full_repos/permissive/503053625/DAC_offset_to_twos\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb,data/full_repos/permissive/503053625/DAC_offset_to_twos.v\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb,data/full_repos/permissive/503053625/DAC_offset_to_twos.sv\n             DAC_offset_to_twos\n             DAC_offset_to_twos.v\n             DAC_offset_to_twos.sv\n             obj_dir/DAC_offset_to_twos\n             obj_dir/DAC_offset_to_twos.v\n             obj_dir/DAC_offset_to_twos.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module DAC_offset_to_twos_tb;
localparam H_period=2;

reg [13:0]DATA_IN=14'h0000;
wire [13:0]DATA_OUT;

DAC_offset_to_twos  #(.WIRE_WIDTH(14)) DACO0 (.data_in(DATA_IN), .data_out(DATA_OUT));

initial
begin
    #H_period;
    DATA_IN = 14'h0000;
    #H_period;
    DATA_IN = 14'h0001;
    #H_period;
    DATA_IN = 14'h1ffe;
    #H_period;
    DATA_IN = 14'h1fff;
    #H_period;
    DATA_IN = 14'h2000;
    #H_period;
    DATA_IN = 14'h3FFe;
    #H_period;
    DATA_IN = 14'h3FFe;
end
endmodule
module DAC_offset_to_twos_tb;

localparam H_period=2;

reg [13:0]DATA_IN=14'h0000;
wire [13:0]DATA_OUT;

DAC_offset_to_twos  #(.WIRE_WIDTH(14)) DACO0 (.data_in(DATA_IN), .data_out(DATA_OUT));

initial
begin
    #H_period;
    DATA_IN = 14'h0000;
    #H_period;
    DATA_IN = 14'h0001;
    #H_period;
    DATA_IN = 14'h1ffe;
    #H_period;
    DATA_IN = 14'h1fff;
    #H_period;
    DATA_IN = 14'h2000;
    #H_period;
    DATA_IN = 14'h3FFe;
    #H_period;
    DATA_IN = 14'h3FFe;
end
endmodule