data/full_repos/permissive/518460376/verilog/rtl/rtl/dp_ram_wrap.v
1: b"%Error: data/full_repos/permissive/518460376/verilog/rtl/rtl/dp_ram_wrap.v:34: Cannot find file containing module: 'dp_ram'\n dp_ram #(.ADDR_WIDTH(ADDR_WIDTH)) dp_ram_i(\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/518460376/verilog/rtl/rtl,data/full_repos/permissive/518460376/dp_ram\n             data/full_repos/permissive/518460376/verilog/rtl/rtl,data/full_repos/permissive/518460376/dp_ram.v\n             data/full_repos/permissive/518460376/verilog/rtl/rtl,data/full_repos/permissive/518460376/dp_ram.sv\n             dp_ram\n             dp_ram.v\n             dp_ram.sv\n             obj_dir/dp_ram\n             obj_dir/dp_ram.v\n             obj_dir/dp_ram.sv\n%Error: Exiting due to 1 error(s)\n"
module dp_ram_wrap 
#(
    parameter ADDR_WIDTH = 8
  )
(
	clk,
	en_a_i,
	addr_a_i,
	wdata_a_i,
	rdata_a_o,
	we_a_i,
	be_a_i,
	en_b_i,
	addr_b_i,
	wdata_b_i,
	rdata_b_o,
	we_b_i,
	be_b_i
);

	input wire clk;
	input wire en_a_i;
	input wire [ADDR_WIDTH - 1:0] addr_a_i;
	input wire [31:0] wdata_a_i;
	output wire [31:0] rdata_a_o;
	input wire we_a_i;
	input wire [3:0] be_a_i;
	input wire en_b_i;
	input wire [ADDR_WIDTH - 1:0] addr_b_i;
	input wire [31:0] wdata_b_i;
	output wire [31:0] rdata_b_o;
	input wire we_b_i;
	input wire [3:0] be_b_i;
	dp_ram #(.ADDR_WIDTH(ADDR_WIDTH)) dp_ram_i(
		.clk(clk),
		.en_a_i(en_a_i),
		.addr_a_i(addr_a_i),
		.wdata_a_i(wdata_a_i),
		.rdata_a_o(rdata_a_o),
		.we_a_i(we_a_i),
		.be_a_i(be_a_i),
		.en_b_i(en_b_i),
		.addr_b_i(addr_b_i),
		.wdata_b_i(wdata_b_i),
		.rdata_b_o(rdata_b_o),
		.we_b_i(we_b_i),
		.be_b_i(be_b_i)
	);
endmodule
module dp_ram_wrap 
#(
    parameter ADDR_WIDTH = 8
  )
(
	clk,
	en_a_i,
	addr_a_i,
	wdata_a_i,
	rdata_a_o,
	we_a_i,
	be_a_i,
	en_b_i,
	addr_b_i,
	wdata_b_i,
	rdata_b_o,
	we_b_i,
	be_b_i
);


	input wire clk;
	input wire en_a_i;
	input wire [ADDR_WIDTH - 1:0] addr_a_i;
	input wire [31:0] wdata_a_i;
	output wire [31:0] rdata_a_o;
	input wire we_a_i;
	input wire [3:0] be_a_i;
	input wire en_b_i;
	input wire [ADDR_WIDTH - 1:0] addr_b_i;
	input wire [31:0] wdata_b_i;
	output wire [31:0] rdata_b_o;
	input wire we_b_i;
	input wire [3:0] be_b_i;
	dp_ram #(.ADDR_WIDTH(ADDR_WIDTH)) dp_ram_i(
		.clk(clk),
		.en_a_i(en_a_i),
		.addr_a_i(addr_a_i),
		.wdata_a_i(wdata_a_i),
		.rdata_a_o(rdata_a_o),
		.we_a_i(we_a_i),
		.be_a_i(be_a_i),
		.en_b_i(en_b_i),
		.addr_b_i(addr_b_i),
		.wdata_b_i(wdata_b_i),
		.rdata_b_o(rdata_b_o),
		.we_b_i(we_b_i),
		.be_b_i(be_b_i)
	);
endmodule