data/full_repos/permissive/43264243/utx.v
1: b'%Error: data/full_repos/permissive/43264243/utx.v:23: Cannot find include file: config.h\n`include "config.h" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43264243,data/full_repos/permissive/43264243/config.h\n             data/full_repos/permissive/43264243,data/full_repos/permissive/43264243/config.h.v\n             data/full_repos/permissive/43264243,data/full_repos/permissive/43264243/config.h.sv\n             config.h\n             config.h.v\n             config.h.sv\n             obj_dir/config.h\n             obj_dir/config.h.v\n             obj_dir/config.h.sv\n%Error: data/full_repos/permissive/43264243/utx.v:45: Define or directive not defined: \'`BAUDRATE_DIVISOR\'\n  baudce <= (baudcntr == `BAUDRATE_DIVISOR) ? 1\'b1 : 1\'b0;\n                         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43264243/utx.v:45: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  baudce <= (baudcntr == `BAUDRATE_DIVISOR) ? 1\'b1 : 1\'b0;\n                                          ^\n%Error: data/full_repos/permissive/43264243/utx.v:52: Define or directive not defined: \'`BAUDRATE_DIVISOR\'\n    if(baudcntr == `BAUDRATE_DIVISOR)\n                   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43264243/utx.v:52: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    if(baudcntr == `BAUDRATE_DIVISOR)\n                                    ^\n%Error: Exiting due to 5 error(s)\n'
module bit_counter(clk, rstn, ce, bitnum);
	input clk;
	input rstn;
	input ce;
	output [3:0] bitnum;

	
	reg [3:0] bitnum_int;
	
	assign bitnum = bitnum_int;
	
	always @(posedge clk or negedge rstn) begin
		if(rstn == 0)
			bitnum_int <= 0;
		else begin
			if(ce) begin
				if(bitnum_int == 9)
					bitnum_int <= 0;
				else
					bitnum_int <= bitnum_int + 1'b1;
			end
		end
	end	
endmodule
module bit_counter(clk, rstn, ce, bitnum);

	input clk;
	input rstn;
	input ce;
	output [3:0] bitnum;

	
	reg [3:0] bitnum_int;
	
	assign bitnum = bitnum_int;
	
	always @(posedge clk or negedge rstn) begin
		if(rstn == 0)
			bitnum_int <= 0;
		else begin
			if(ce) begin
				if(bitnum_int == 9)
					bitnum_int <= 0;
				else
					bitnum_int <= bitnum_int + 1'b1;
			end
		end
	end	
endmodule