data/full_repos/permissive/468929885/verilog/rtl/el_latch.v
data/verilator_xmls/4883c891-5e56-4588-beb2-c70be7908109.xml
module el_latch#(
	parameter						RAIL_NUM = 2
)
(

	input							rst,

	input							lat_i,
	input	[RAIL_NUM-1 : 0]		in,

	output							ack_o,
	output	[RAIL_NUM-1 : 0]		out

);

reg [RAIL_NUM-1 : 0] out_r = 0;
wire ack;

assign ack = ^out_r;
assign ack_o = ack;
assign out = out_r;

always@(*)
begin
	if(rst)
	begin
		out_r = 0;
	end
	else
	begin
		if(!lat_i)
		begin
			out_r = in;
		end
	end
end



endmodule
module el_latch#(
	parameter						RAIL_NUM = 2
)
(

	input							rst,

	input							lat_i,
	input	[RAIL_NUM-1 : 0]		in,

	output							ack_o,
	output	[RAIL_NUM-1 : 0]		out

);


reg [RAIL_NUM-1 : 0] out_r = 0;
wire ack;

assign ack = ^out_r;
assign ack_o = ack;
assign out = out_r;

always@(*)
begin
	if(rst)
	begin
		out_r = 0;
	end
	else
	begin
		if(!lat_i)
		begin
			out_r = in;
		end
	end
end



endmodule