data/full_repos/permissive/425063349/DFF.v
data/verilator_xmls/05984a1d-a371-4809-8a49-5d2414a18fbb.xml
module DFF (output reg Q, output Qn, input D, Clear, Clock); 
	always @ (posedge Clock) begin
		if (Clear)
			Q <= 1'b0;
		else
			Q <= D;
	end
	assign Qn = ~Q;
endmodule
module DFF (output reg Q, output Qn, input D, Clear, Clock);
 
	always @ (posedge Clock) begin
		if (Clear)
			Q <= 1'b0;
		else
			Q <= D;
	end
	assign Qn = ~Q;
endmodule