data/full_repos/permissive/494664634/AxiMM2S2MMTest/src/hdl/AxiMM2S2MMTest.v
data/verilator_xmls/d3017545-f862-41ac-bdb1-40a911ceef28.xml
module DmaInfo(
  input  [31:0] addr,
  input  [31:0] blength,
  output [31:0] offset,
  output [31:0] wlength,
  output [3:0]  fkeep,
  output [3:0]  lkeep
);
  wire [29:0] waddr = addr[31:2];
  wire [31:0] addr_n = addr + blength;
  wire [31:0] _wlength_T_1 = addr_n + 32'h3;
  wire [29:0] _wlength_T_4 = _wlength_T_1[31:2] - waddr;
  wire [6:0] _fkeep_T_1 = 7'hf << addr[1:0];
  wire [2:0] _GEN_0 = {{1'd0}, addr_n[1:0]};
  wire [2:0] _lkeep_T_4 = 3'h4 - _GEN_0;
  wire [3:0] _lkeep_T_5 = 4'hf >> _lkeep_T_4;
  assign offset = {waddr, 2'h0};
  assign wlength = {{2'd0}, _wlength_T_4};
  assign fkeep = _fkeep_T_1[3:0];
  assign lkeep = addr_n[1:0] == 2'h0 ? 4'hf : _lkeep_T_5;
endmodule
module DmaInfo(
  input  [31:0] addr,
  input  [31:0] blength,
  output [31:0] offset,
  output [31:0] wlength,
  output [3:0]  fkeep,
  output [3:0]  lkeep
);

  wire [29:0] waddr = addr[31:2];
  wire [31:0] addr_n = addr + blength;
  wire [31:0] _wlength_T_1 = addr_n + 32'h3;
  wire [29:0] _wlength_T_4 = _wlength_T_1[31:2] - waddr;
  wire [6:0] _fkeep_T_1 = 7'hf << addr[1:0];
  wire [2:0] _GEN_0 = {{1'd0}, addr_n[1:0]};
  wire [2:0] _lkeep_T_4 = 3'h4 - _GEN_0;
  wire [3:0] _lkeep_T_5 = 4'hf >> _lkeep_T_4;
  assign offset = {waddr, 2'h0};
  assign wlength = {{2'd0}, _wlength_T_4};
  assign fkeep = _fkeep_T_1[3:0];
  assign lkeep = addr_n[1:0] == 2'h0 ? 4'hf : _lkeep_T_5;
endmodule