data/full_repos/permissive/411457613/Pyverilog/verilogcode/generate.v
data/verilator_xmls/a886b39c-bad5-4d3d-a303-964413e6e7ba.xml
module TOP(CLK, RST_X, subin, subout);
  parameter WD = 4;
  input CLK;
  input RST_X;
  input [WD-1:0] subin;
  output [WD-1:0] subout;
  
  genvar j;
  generate for(j=0; j<WD; j=j+1) begin: subloop
    if(j == 0) begin: _subt
      wire tmp;
      assign subout[j] = subin[j];
      assign tmp = ~subin[j];
    end else begin: _subf
      wire tmp;
      if(j == 1) begin
        assign subout[j] = subloop[j-1]._subt.tmp ^ subin[j];
      end else begin
        assign subout[j] = subloop[j-1]._subf.tmp ^ subin[j];
      end
    end
  end endgenerate
    
endmodule
module TOP(CLK, RST_X, subin, subout);

  parameter WD = 4;
  input CLK;
  input RST_X;
  input [WD-1:0] subin;
  output [WD-1:0] subout;
  
  genvar j;
  generate for(j=0; j<WD; j=j+1) begin: subloop
    if(j == 0) begin: _subt
      wire tmp;
      assign subout[j] = subin[j];
      assign tmp = ~subin[j];
    end else begin: _subf
      wire tmp;
      if(j == 1) begin
        assign subout[j] = subloop[j-1]._subt.tmp ^ subin[j];
      end else begin
        assign subout[j] = subloop[j-1]._subf.tmp ^ subin[j];
      end
    end
  end endgenerate
    
endmodule