data/full_repos/permissive/506636840/rtl/gpio/rtl/verilog/gpio_top.v
1: b'%Error: data/full_repos/permissive/506636840/rtl/gpio/rtl/verilog/gpio_top.v:115: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/506636840/rtl/gpio/rtl/verilog,data/full_repos/permissive/506636840/timescale.v\n             data/full_repos/permissive/506636840/rtl/gpio/rtl/verilog,data/full_repos/permissive/506636840/timescale.v.v\n             data/full_repos/permissive/506636840/rtl/gpio/rtl/verilog,data/full_repos/permissive/506636840/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/506636840/rtl/gpio/rtl/verilog/gpio_top.v:117: Cannot find include file: gpio_defines.v\n`include "gpio_defines.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/gpio/rtl/verilog/gpio_top.v:138: Define or directive not defined: \'`GPIO_ADDRHH\'\nparameter aw = `GPIO_ADDRHH+1;\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/gpio/rtl/verilog/gpio_top.v:139: Define or directive not defined: \'`GPIO_IOS\'\nparameter gw = `GPIO_IOS;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/gpio/rtl/verilog/gpio_top.v:139: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter gw = `GPIO_IOS;\n                        ^\n%Error: Exiting due to 5 error(s)\n'
module gpio_top(

  PCLK, PRESETN, PSEL, PADDR, PWDATA, PRDATA, PENABLE, PREADY,
  PSLVERR, PWRITE,

  IRQ,
`ifdef GPIO_AUX_IMPLEMENT

  aux_i,
`endif


  ext_pad_i, ext_pad_o, ext_padoe_o
`ifdef GPIO_CLKPAD
  , clk_pad_i 
`endif
);

parameter dw = 32;
parameter aw = `GPIO_ADDRHH+1;
parameter gw = `GPIO_IOS;



input PCLK;
input PRESETN;
input PSEL;
input [aw-1:0] PADDR;
input [dw-1:0] PWDATA;
input PENABLE;
input PWRITE;
output [dw-1:0] PRDATA;
output PREADY;
output PSLVERR;

output            IRQ;

`ifdef GPIO_AUX_IMPLEMENT

input   [gw-1:0]  aux_i;
`endif




input   [gw-1:0]  ext_pad_i;
`ifdef GPIO_CLKPAD
input             clk_pad_i;
`endif
output  [gw-1:0]  ext_pad_o;
output  [gw-1:0]  ext_padoe_o;

`ifdef GPIO_IMPLEMENTED




`ifdef GPIO_RGPIO_IN
reg [gw-1:0]  rgpio_in;
`else
wire  [gw-1:0]  rgpio_in;
`endif




`ifdef GPIO_RGPIO_OUT
reg [gw-1:0]  rgpio_out;
`else
wire  [gw-1:0]  rgpio_out;
`endif




`ifdef GPIO_RGPIO_OE
reg [gw-1:0]  rgpio_oe;
`else
wire  [gw-1:0]  rgpio_oe;
`endif




`ifdef GPIO_RGPIO_INTE
reg [gw-1:0]  rgpio_inte;
`else
wire  [gw-1:0]  rgpio_inte;
`endif




`ifdef GPIO_RGPIO_PTRIG
reg [gw-1:0]  rgpio_ptrig;
`else
wire  [gw-1:0]  rgpio_ptrig;
`endif




`ifdef GPIO_RGPIO_AUX
reg [gw-1:0]  rgpio_aux;
`else
wire  [gw-1:0]  rgpio_aux;
`endif




`ifdef GPIO_RGPIO_CTRL
reg [1:0]   rgpio_ctrl;
`else
wire  [1:0]   rgpio_ctrl;
`endif




`ifdef GPIO_RGPIO_INTS
reg [gw-1:0]  rgpio_ints;
`else
wire  [gw-1:0]  rgpio_ints;
`endif




`ifdef GPIO_RGPIO_ECLK
reg [gw-1:0]  rgpio_eclk;
`else
wire  [gw-1:0]  rgpio_eclk;
`endif




`ifdef GPIO_RGPIO_NEC
reg [gw-1:0]  rgpio_nec;
`else
wire  [gw-1:0]  rgpio_nec;
`endif





`ifdef GPIO_SYNC_IN_WB 
reg  [gw-1:0]  sync      ,
               ext_pad_s ;
`else 
wire [gw-1:0]  ext_pad_s ;
`endif






wire            rgpio_out_sel;
wire            rgpio_oe_sel;
wire            rgpio_inte_sel;
wire            rgpio_ptrig_sel;
wire            rgpio_aux_sel;
wire            rgpio_ctrl_sel;
wire            rgpio_ints_sel;
wire            rgpio_eclk_sel ;
wire            rgpio_nec_sel ;
wire            full_decoding;
wire  [gw-1:0]  in_muxed;
wire            wb_ack;
wire            wb_err;
wire            wb_inta;
reg   [dw-1:0]  wb_dat;
`ifdef GPIO_REGISTERED_WB_OUTPUTS
reg             PREADY;
reg             PSLVERR;
reg             IRQ;
reg   [dw-1:0]  PRDATA;
`endif
wire  [gw-1:0]  out_pad;
`ifdef GPIO_REGISTERED_IO_OUTPUTS
reg   [gw-1:0]  ext_pad_o;
`endif
`ifdef GPIO_CLKPAD
wire  [gw-1:0]  extc_in;
wire  [gw-1:0]  pext_clk;
reg   [gw-1:0]  pextc_sampled;
`ifdef GPIO_NO_NEGEDGE_FLOPS
`ifdef GPIO_NO_CLKPAD_LOGIC
`else
reg   [gw-1:0]  nextc_sampled;
`endif
`else
reg   [gw-1:0]  nextc_sampled;
`endif
`endif












assign wb_ack = PSEL & PENABLE & !PSLVERR;




`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0)
    PREADY <= #1 1'b0;
  else
    PREADY <= #1 wb_ack & ~PREADY & (!wb_err) ;
`else
assign PREADY = wb_ack;
`endif




`ifdef GPIO_FULL_DECODE
`ifdef GPIO_STRICT_32BIT_ACCESS
assign wb_err = PSEL & PENABLE & (!full_decoding );
`else
assign wb_err = PSEL & PENABLE & !full_decoding;
`endif
`else
`ifdef GPIO_STRICT_32BIT_ACCESS
assign wb_err = PSEL & PENABLE ;
`else
assign wb_err = 1'b0;
`endif
`endif




`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0)
    PSLVERR <= #1 1'b0;
  else
    PSLVERR <= #1 wb_err & ~PSLVERR;
`else
assign PSLVERR = wb_err;
`endif




`ifdef GPIO_FULL_DECODE
assign full_decoding = (PADDR[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) &
      (PADDR[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}});
`else
assign full_decoding = 1'b1;
`endif




`ifdef GPIO_RGPIO_OUT
assign rgpio_out_sel = PSEL & PENABLE & (PADDR[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding;
`endif
`ifdef GPIO_RGPIO_OE
assign rgpio_oe_sel = PSEL & PENABLE & (PADDR[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding;
`endif
`ifdef GPIO_RGPIO_INTE
assign rgpio_inte_sel = PSEL & PENABLE & (PADDR[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding;
`endif
`ifdef GPIO_RGPIO_PTRIG
assign rgpio_ptrig_sel = PSEL & PENABLE & (PADDR[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;
`endif
`ifdef GPIO_RGPIO_AUX
assign rgpio_aux_sel = PSEL & PENABLE & (PADDR[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;
`endif
`ifdef GPIO_RGPIO_CTRL
assign rgpio_ctrl_sel = PSEL & PENABLE & (PADDR[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;
`endif
`ifdef GPIO_RGPIO_INTS
assign rgpio_ints_sel = PSEL & PENABLE & (PADDR[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTS) & full_decoding;
`endif
`ifdef GPIO_RGPIO_ECLK
assign rgpio_eclk_sel = PSEL & PENABLE & (PADDR[`GPIO_OFS_BITS] == `GPIO_RGPIO_ECLK) & full_decoding;
`endif
`ifdef GPIO_RGPIO_NEC
assign rgpio_nec_sel = PSEL & PENABLE & (PADDR[`GPIO_OFS_BITS] == `GPIO_RGPIO_NEC) & full_decoding;
`endif





`ifdef GPIO_RGPIO_CTRL
always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0)
    rgpio_ctrl <= #1 2'b0;
  else if (rgpio_ctrl_sel && PWRITE)
    rgpio_ctrl <= #1 PWDATA[1:0];
  else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
    rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] | IRQ;
`else
assign rgpio_ctrl = 2'h01;
`endif




`ifdef GPIO_RGPIO_OUT
always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0)
    rgpio_out <= #1 {gw{1'b0}};
  else if (rgpio_out_sel && PWRITE)
    begin
`ifdef GPIO_STRICT_32BIT_ACCESS
    rgpio_out <= #1 PWDATA[gw-1:0];
`endif

`ifdef GPIO_WB_BYTES4
       rgpio_out [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES3
       rgpio_out [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES2
       rgpio_out [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES1
       rgpio_out [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
   end

`else
assign rgpio_out = `GPIO_DEF_RGPIO_OUT;
`endif




`ifdef GPIO_RGPIO_OE
always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0)
    rgpio_oe <= #1 {gw{1'b0}};
  else if (rgpio_oe_sel && PWRITE)
  begin
`ifdef GPIO_STRICT_32BIT_ACCESS
    rgpio_oe <= #1 PWDATA[gw-1:0];
`endif

`ifdef GPIO_WB_BYTES4
       rgpio_oe [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES3
       rgpio_oe [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES2
       rgpio_oe [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES1
       rgpio_oe [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
   end

`else
assign rgpio_oe = `GPIO_DEF_RGPIO_OE;
`endif




`ifdef GPIO_RGPIO_INTE
always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0)
    rgpio_inte <= #1 {gw{1'b0}};
  else if (rgpio_inte_sel && PWRITE)
  begin
`ifdef GPIO_STRICT_32BIT_ACCESS
    rgpio_inte <= #1 PWDATA[gw-1:0];
`endif

`ifdef GPIO_WB_BYTES4
       rgpio_inte [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES3
       rgpio_inte [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES2
       rgpio_inte [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES1
       rgpio_inte [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
   end


`else
assign rgpio_inte = `GPIO_DEF_RGPIO_INTE;
`endif




`ifdef GPIO_RGPIO_PTRIG
always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0)
    rgpio_ptrig <= #1 {gw{1'b0}};
  else if (rgpio_ptrig_sel && PWRITE)
  begin
`ifdef GPIO_STRICT_32BIT_ACCESS
    rgpio_ptrig <= #1 PWDATA[gw-1:0];
`endif

`ifdef GPIO_WB_BYTES4
       rgpio_ptrig [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES3
       rgpio_ptrig [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES2
       rgpio_ptrig [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES1
       rgpio_ptrig [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
   end
    
`else
assign rgpio_ptrig = `GPIO_DEF_RGPIO_PTRIG;
`endif




`ifdef GPIO_RGPIO_AUX
always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0)
    rgpio_aux <= #1 {gw{1'b0}};
  else if (rgpio_aux_sel && PWRITE)
  begin
`ifdef GPIO_STRICT_32BIT_ACCESS
    rgpio_aux <= #1 PWDATA[gw-1:0];
`endif

`ifdef GPIO_WB_BYTES4
       rgpio_aux [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES3
       rgpio_aux [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES2
       rgpio_aux [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES1
       rgpio_aux [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
   end

`else
assign rgpio_aux = `GPIO_DEF_RGPIO_AUX;
`endif





`ifdef GPIO_RGPIO_ECLK
always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0)
    rgpio_eclk <= #1 {gw{1'b0}};
  else if (rgpio_eclk_sel && PWRITE)
  begin
`ifdef GPIO_STRICT_32BIT_ACCESS
    rgpio_eclk <= #1 PWDATA[gw-1:0];
`endif

`ifdef GPIO_WB_BYTES4
       rgpio_eclk [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES3
       rgpio_eclk [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES2
       rgpio_eclk [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES1
       rgpio_eclk [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
   end


`else
assign rgpio_eclk = `GPIO_DEF_RGPIO_ECLK;
`endif






`ifdef GPIO_RGPIO_NEC
always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0)
    rgpio_nec <= #1 {gw{1'b0}};
  else if (rgpio_nec_sel && PWRITE)
  begin
`ifdef GPIO_STRICT_32BIT_ACCESS
    rgpio_nec <= #1 PWDATA[gw-1:0];
`endif

`ifdef GPIO_WB_BYTES4
       rgpio_nec [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES3
       rgpio_nec [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES2
       rgpio_nec [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES1
       rgpio_nec [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
   end


`else
assign rgpio_nec = `GPIO_DEF_RGPIO_NEC;
`endif




`ifdef  GPIO_SYNC_IN_WB
always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0) begin
    sync      <= #1 {gw{1'b0}} ; 
    ext_pad_s <= #1 {gw{1'b0}} ; 
  end else begin
    sync      <= #1 ext_pad_i  ; 
    ext_pad_s <= #1 sync       ; 
  end
`else 
assign  ext_pad_s = ext_pad_i;
`endif
  



`ifdef GPIO_RGPIO_IN
always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0)
    rgpio_in <= #1 {gw{1'b0}};
  else
    rgpio_in <= #1 in_muxed;
`else
assign rgpio_in = in_muxed;
`endif

`ifdef GPIO_CLKPAD

`ifdef GPIO_SYNC_CLK_WB






reg  sync_clk,
     clk_s   ,
     clk_r   ;
wire pedge   ,
     nedge   ;
wire [gw-1:0] pedge_vec   ,
              nedge_vec   ;
wire [gw-1:0] in_lach     ;

assign pedge =  clk_s & !clk_r ; 
assign nedge = !clk_s &  clk_r ; 
assign pedge_vec = {gw{pedge}} ;   
assign nedge_vec = {gw{nedge}} ;   

assign in_lach = (~rgpio_nec & pedge_vec) | (rgpio_nec & nedge_vec) ;
assign extc_in = (in_lach & ext_pad_s) | (~in_lach & pextc_sampled) ;

always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0) begin
    sync_clk <= #1 1'b0 ;
    clk_s    <= #1 1'b0 ;
    clk_r    <= #1 1'b0 ;
  end else begin
    sync_clk <= #1 clk_pad_i ;
    clk_s    <= #1 sync_clk  ;
    clk_r    <= #1 clk_s     ;
  end

always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0) begin
    pextc_sampled <= #1 {gw{1'b0}};
  end else begin
    pextc_sampled <= #1 extc_in ;
  end

assign in_muxed = (rgpio_eclk & pextc_sampled) | (~rgpio_eclk & ext_pad_s) ;

`else






`ifdef GPIO_SYNC_IN_CLK_WB

reg [gw-1:0] syn_extc  ,
             extc_s    ;

always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0) begin
    syn_extc  <= #1 {gw{1'b0}};
    extc_s    <= #1 {gw{1'b0}};
  end else begin
    syn_extc  <= #1 extc_in ;
    extc_s    <= #1 syn_extc;
  end

`else

wire [gw-1:0] extc_s   ;
assign extc_s = syn_extc ;

`endif

`ifdef GPIO_SYNC_IN_CLK
reg [gw-1:0] syn_pclk    ,
             ext_pad_spc ;

always @(posedge clk_pad_i or negedge PRESETN)
  if (PRESETN == 0) begin
    syn_pclk    <= #1 {gw{1'b0}} ; 
    ext_pad_spc <= #1 {gw{1'b0}} ; 
  end else begin
    syn_pclk    <= #1 ext_pad_i ; 
    ext_pad_spc <= #1 syn_pclk  ; 
  end

`else

wire [gw-1:0] ext_pad_spc      ;
assign ext_pad_spc = ext_pad_i ;

`endif

always @(posedge clk_pad_i or negedge PRESETN)
  if (PRESETN == 0) begin
    pextc_sampled <= #1 {gw{1'b0}};
  end else begin
    pextc_sampled <= #1 ext_pad_spc ;
  end


`ifdef GPIO_NO_NEGEDGE_FLOPS

`ifdef GPIO_NO_CLKPAD_LOGIC

assign extc_in = pextc_sampled;

`else

wire  clk_n;
assign clk_n = !clk_pad_i;

`ifdef GPIO_SYNC_IN_CLK
reg [gw-1:0] syn_nclk    ,
             ext_pad_snc ;

always @(posedge clk_n or negedge PRESETN)
  if (PRESETN == 0) begin
    syn_nclk    <= #1 {gw{1'b0}} ; 
    ext_pad_snc <= #1 {gw{1'b0}} ; 
  end else begin
    syn_nclk    <= #1 ext_pad_i ; 
    ext_pad_snc <= #1 syn_nclk  ; 
  end

`else

wire [gw-1:0] ext_pad_snc      ;
assign ext_pad_snc = ext_pad_i ;

`endif

always @(posedge clk_n or negedge PRESETN)
  if (PRESETN == 0) begin
    nextc_sampled <= #1 {gw{1'b0}};
  end else begin
    nextc_sampled <= #1 ext_pad_snc ;
  end  

assign extc_in = (~rgpio_nec & pextc_sampled) | (rgpio_nec & nextc_sampled) ;

`endif


`else

`ifdef GPIO_SYNC_IN_CLK
reg [gw-1:0] syn_nclk    ,
             ext_pad_snc ;

always @(negedge clk_n or negedge PRESETN)
  if (PRESETN == 0) begin
    syn_nclk    <= #1 {gw{1'b0}} ; 
    ext_pad_snc <= #1 {gw{1'b0}} ; 
  end else begin
    syn_nclk    <= #1 ext_pad_i ; 
    ext_pad_snc <= #1 syn_nclk  ; 
  end

`else

wire [gw-1:0] ext_pad_snc      ;
assign ext_pad_snc = ext_pad_i ;

`endif

always @(negedge clk_pad_i or negedge PRESETN)
  if (PRESETN == 0) begin
    nextc_sampled <= #1 {gw{1'b0}};
  end else begin
    nextc_sampled <= #1 ext_pad_snc ;
  end

assign extc_in = (~rgpio_nec & pextc_sampled) | (rgpio_nec & nextc_sampled) ;

`endif

assign in_muxed = (rgpio_eclk & extc_s)      | (~rgpio_eclk & ext_pad_s) ;


`endif


`else

assign  in_muxed  = ext_pad_s ;

`endif






always @(PADDR or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or
    rgpio_ptrig or rgpio_aux or rgpio_ctrl or rgpio_ints or rgpio_eclk or rgpio_nec)
  case (PADDR[`GPIO_OFS_BITS])
`ifdef GPIO_READREGS
  `ifdef GPIO_RGPIO_OUT
    `GPIO_RGPIO_OUT: begin
      wb_dat[dw-1:0] = rgpio_out;
    end
  `endif
  `ifdef GPIO_RGPIO_OE
    `GPIO_RGPIO_OE: begin
      wb_dat[dw-1:0] = rgpio_oe;
    end
  `endif
  `ifdef GPIO_RGPIO_INTE
    `GPIO_RGPIO_INTE: begin
      wb_dat[dw-1:0] = rgpio_inte;
    end
  `endif
  `ifdef GPIO_RGPIO_PTRIG
    `GPIO_RGPIO_PTRIG: begin
      wb_dat[dw-1:0] = rgpio_ptrig;
    end
  `endif
  `ifdef GPIO_RGPIO_NEC
    `GPIO_RGPIO_NEC: begin
      wb_dat[dw-1:0] = rgpio_nec;
    end
  `endif
  `ifdef GPIO_RGPIO_ECLK
    `GPIO_RGPIO_ECLK: begin
      wb_dat[dw-1:0] = rgpio_eclk;
    end
  `endif
  `ifdef GPIO_RGPIO_AUX
    `GPIO_RGPIO_AUX: begin
      wb_dat[dw-1:0] = rgpio_aux;
    end
  `endif
  `ifdef GPIO_RGPIO_CTRL
    `GPIO_RGPIO_CTRL: begin
      wb_dat[1:0] = rgpio_ctrl;
      wb_dat[dw-1:2] = {dw-2{1'b0}};
    end
  `endif
`endif
  `ifdef GPIO_RGPIO_INTS
    `GPIO_RGPIO_INTS: begin
      wb_dat[dw-1:0] = rgpio_ints;
    end
  `endif
    default: begin
      wb_dat[dw-1:0] = rgpio_in;
    end
  endcase




`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0)
    PRDATA <= #1 {dw{1'b0}};
  else
    PRDATA <= #1 wb_dat;
`else
assign PRDATA = wb_dat;
`endif




`ifdef GPIO_RGPIO_INTS
always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0)
    rgpio_ints <= #1 {gw{1'b0}};
  else if (rgpio_ints_sel && PWRITE)
    rgpio_ints <= #1 PWDATA[gw-1:0];
  else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
    rgpio_ints <= #1 (rgpio_ints | ((in_muxed ^ rgpio_in) & ~(in_muxed ^ rgpio_ptrig)) & rgpio_inte);
`else
assign rgpio_ints = (rgpio_ints | ((in_muxed ^ rgpio_in) & ~(in_muxed ^ rgpio_ptrig)) & rgpio_inte);
`endif




assign wb_inta = |rgpio_ints ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0;




`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0)
    IRQ <= #1 1'b0;
  else
    IRQ <= #1 wb_inta;
`else
assign IRQ = wb_inta;
`endif




assign ext_padoe_o = rgpio_oe;




`ifdef GPIO_AUX_IMPLEMENT
assign out_pad = rgpio_out & ~rgpio_aux | aux_i & rgpio_aux;
`else
assign out_pad = rgpio_out ;
`endif




`ifdef GPIO_REGISTERED_IO_OUTPUTS
always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0)
    ext_pad_o <= #1 {gw{1'b0}};
  else
    ext_pad_o <= #1 out_pad;
`else
assign ext_pad_o = out_pad;
`endif


`else





assign IRQ = 1'b0;
assign PREADY = 1'b0;
assign PSLVERR = 0;
assign ext_padoe_o = {gw{1'b1}};
assign ext_pad_o = {gw{1'b0}};




assign PRDATA = {dw{1'b0}};

`endif

endmodule
module gpio_top(

  PCLK, PRESETN, PSEL, PADDR, PWDATA, PRDATA, PENABLE, PREADY,
  PSLVERR, PWRITE,

  IRQ,
`ifdef GPIO_AUX_IMPLEMENT

  aux_i,
`endif


  ext_pad_i, ext_pad_o, ext_padoe_o
`ifdef GPIO_CLKPAD
  , clk_pad_i 
`endif
);


parameter dw = 32;
parameter aw = `GPIO_ADDRHH+1;
parameter gw = `GPIO_IOS;



input PCLK;
input PRESETN;
input PSEL;
input [aw-1:0] PADDR;
input [dw-1:0] PWDATA;
input PENABLE;
input PWRITE;
output [dw-1:0] PRDATA;
output PREADY;
output PSLVERR;

output            IRQ;

`ifdef GPIO_AUX_IMPLEMENT

input   [gw-1:0]  aux_i;
`endif




input   [gw-1:0]  ext_pad_i;
`ifdef GPIO_CLKPAD
input             clk_pad_i;
`endif
output  [gw-1:0]  ext_pad_o;
output  [gw-1:0]  ext_padoe_o;

`ifdef GPIO_IMPLEMENTED




`ifdef GPIO_RGPIO_IN
reg [gw-1:0]  rgpio_in;
`else
wire  [gw-1:0]  rgpio_in;
`endif




`ifdef GPIO_RGPIO_OUT
reg [gw-1:0]  rgpio_out;
`else
wire  [gw-1:0]  rgpio_out;
`endif




`ifdef GPIO_RGPIO_OE
reg [gw-1:0]  rgpio_oe;
`else
wire  [gw-1:0]  rgpio_oe;
`endif




`ifdef GPIO_RGPIO_INTE
reg [gw-1:0]  rgpio_inte;
`else
wire  [gw-1:0]  rgpio_inte;
`endif




`ifdef GPIO_RGPIO_PTRIG
reg [gw-1:0]  rgpio_ptrig;
`else
wire  [gw-1:0]  rgpio_ptrig;
`endif




`ifdef GPIO_RGPIO_AUX
reg [gw-1:0]  rgpio_aux;
`else
wire  [gw-1:0]  rgpio_aux;
`endif




`ifdef GPIO_RGPIO_CTRL
reg [1:0]   rgpio_ctrl;
`else
wire  [1:0]   rgpio_ctrl;
`endif




`ifdef GPIO_RGPIO_INTS
reg [gw-1:0]  rgpio_ints;
`else
wire  [gw-1:0]  rgpio_ints;
`endif




`ifdef GPIO_RGPIO_ECLK
reg [gw-1:0]  rgpio_eclk;
`else
wire  [gw-1:0]  rgpio_eclk;
`endif




`ifdef GPIO_RGPIO_NEC
reg [gw-1:0]  rgpio_nec;
`else
wire  [gw-1:0]  rgpio_nec;
`endif





`ifdef GPIO_SYNC_IN_WB 
reg  [gw-1:0]  sync      ,
               ext_pad_s ;
`else 
wire [gw-1:0]  ext_pad_s ;
`endif






wire            rgpio_out_sel;
wire            rgpio_oe_sel;
wire            rgpio_inte_sel;
wire            rgpio_ptrig_sel;
wire            rgpio_aux_sel;
wire            rgpio_ctrl_sel;
wire            rgpio_ints_sel;
wire            rgpio_eclk_sel ;
wire            rgpio_nec_sel ;
wire            full_decoding;
wire  [gw-1:0]  in_muxed;
wire            wb_ack;
wire            wb_err;
wire            wb_inta;
reg   [dw-1:0]  wb_dat;
`ifdef GPIO_REGISTERED_WB_OUTPUTS
reg             PREADY;
reg             PSLVERR;
reg             IRQ;
reg   [dw-1:0]  PRDATA;
`endif
wire  [gw-1:0]  out_pad;
`ifdef GPIO_REGISTERED_IO_OUTPUTS
reg   [gw-1:0]  ext_pad_o;
`endif
`ifdef GPIO_CLKPAD
wire  [gw-1:0]  extc_in;
wire  [gw-1:0]  pext_clk;
reg   [gw-1:0]  pextc_sampled;
`ifdef GPIO_NO_NEGEDGE_FLOPS
`ifdef GPIO_NO_CLKPAD_LOGIC
`else
reg   [gw-1:0]  nextc_sampled;
`endif
`else
reg   [gw-1:0]  nextc_sampled;
`endif
`endif












assign wb_ack = PSEL & PENABLE & !PSLVERR;




`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0)
    PREADY <= #1 1'b0;
  else
    PREADY <= #1 wb_ack & ~PREADY & (!wb_err) ;
`else
assign PREADY = wb_ack;
`endif




`ifdef GPIO_FULL_DECODE
`ifdef GPIO_STRICT_32BIT_ACCESS
assign wb_err = PSEL & PENABLE & (!full_decoding );
`else
assign wb_err = PSEL & PENABLE & !full_decoding;
`endif
`else
`ifdef GPIO_STRICT_32BIT_ACCESS
assign wb_err = PSEL & PENABLE ;
`else
assign wb_err = 1'b0;
`endif
`endif




`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0)
    PSLVERR <= #1 1'b0;
  else
    PSLVERR <= #1 wb_err & ~PSLVERR;
`else
assign PSLVERR = wb_err;
`endif




`ifdef GPIO_FULL_DECODE
assign full_decoding = (PADDR[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) &
      (PADDR[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}});
`else
assign full_decoding = 1'b1;
`endif




`ifdef GPIO_RGPIO_OUT
assign rgpio_out_sel = PSEL & PENABLE & (PADDR[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding;
`endif
`ifdef GPIO_RGPIO_OE
assign rgpio_oe_sel = PSEL & PENABLE & (PADDR[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding;
`endif
`ifdef GPIO_RGPIO_INTE
assign rgpio_inte_sel = PSEL & PENABLE & (PADDR[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding;
`endif
`ifdef GPIO_RGPIO_PTRIG
assign rgpio_ptrig_sel = PSEL & PENABLE & (PADDR[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;
`endif
`ifdef GPIO_RGPIO_AUX
assign rgpio_aux_sel = PSEL & PENABLE & (PADDR[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;
`endif
`ifdef GPIO_RGPIO_CTRL
assign rgpio_ctrl_sel = PSEL & PENABLE & (PADDR[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;
`endif
`ifdef GPIO_RGPIO_INTS
assign rgpio_ints_sel = PSEL & PENABLE & (PADDR[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTS) & full_decoding;
`endif
`ifdef GPIO_RGPIO_ECLK
assign rgpio_eclk_sel = PSEL & PENABLE & (PADDR[`GPIO_OFS_BITS] == `GPIO_RGPIO_ECLK) & full_decoding;
`endif
`ifdef GPIO_RGPIO_NEC
assign rgpio_nec_sel = PSEL & PENABLE & (PADDR[`GPIO_OFS_BITS] == `GPIO_RGPIO_NEC) & full_decoding;
`endif





`ifdef GPIO_RGPIO_CTRL
always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0)
    rgpio_ctrl <= #1 2'b0;
  else if (rgpio_ctrl_sel && PWRITE)
    rgpio_ctrl <= #1 PWDATA[1:0];
  else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
    rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] | IRQ;
`else
assign rgpio_ctrl = 2'h01;
`endif




`ifdef GPIO_RGPIO_OUT
always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0)
    rgpio_out <= #1 {gw{1'b0}};
  else if (rgpio_out_sel && PWRITE)
    begin
`ifdef GPIO_STRICT_32BIT_ACCESS
    rgpio_out <= #1 PWDATA[gw-1:0];
`endif

`ifdef GPIO_WB_BYTES4
       rgpio_out [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES3
       rgpio_out [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES2
       rgpio_out [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES1
       rgpio_out [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
   end

`else
assign rgpio_out = `GPIO_DEF_RGPIO_OUT;
`endif




`ifdef GPIO_RGPIO_OE
always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0)
    rgpio_oe <= #1 {gw{1'b0}};
  else if (rgpio_oe_sel && PWRITE)
  begin
`ifdef GPIO_STRICT_32BIT_ACCESS
    rgpio_oe <= #1 PWDATA[gw-1:0];
`endif

`ifdef GPIO_WB_BYTES4
       rgpio_oe [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES3
       rgpio_oe [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES2
       rgpio_oe [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES1
       rgpio_oe [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
   end

`else
assign rgpio_oe = `GPIO_DEF_RGPIO_OE;
`endif




`ifdef GPIO_RGPIO_INTE
always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0)
    rgpio_inte <= #1 {gw{1'b0}};
  else if (rgpio_inte_sel && PWRITE)
  begin
`ifdef GPIO_STRICT_32BIT_ACCESS
    rgpio_inte <= #1 PWDATA[gw-1:0];
`endif

`ifdef GPIO_WB_BYTES4
       rgpio_inte [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES3
       rgpio_inte [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES2
       rgpio_inte [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES1
       rgpio_inte [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
   end


`else
assign rgpio_inte = `GPIO_DEF_RGPIO_INTE;
`endif




`ifdef GPIO_RGPIO_PTRIG
always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0)
    rgpio_ptrig <= #1 {gw{1'b0}};
  else if (rgpio_ptrig_sel && PWRITE)
  begin
`ifdef GPIO_STRICT_32BIT_ACCESS
    rgpio_ptrig <= #1 PWDATA[gw-1:0];
`endif

`ifdef GPIO_WB_BYTES4
       rgpio_ptrig [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES3
       rgpio_ptrig [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES2
       rgpio_ptrig [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES1
       rgpio_ptrig [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
   end
    
`else
assign rgpio_ptrig = `GPIO_DEF_RGPIO_PTRIG;
`endif




`ifdef GPIO_RGPIO_AUX
always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0)
    rgpio_aux <= #1 {gw{1'b0}};
  else if (rgpio_aux_sel && PWRITE)
  begin
`ifdef GPIO_STRICT_32BIT_ACCESS
    rgpio_aux <= #1 PWDATA[gw-1:0];
`endif

`ifdef GPIO_WB_BYTES4
       rgpio_aux [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES3
       rgpio_aux [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES2
       rgpio_aux [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES1
       rgpio_aux [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
   end

`else
assign rgpio_aux = `GPIO_DEF_RGPIO_AUX;
`endif





`ifdef GPIO_RGPIO_ECLK
always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0)
    rgpio_eclk <= #1 {gw{1'b0}};
  else if (rgpio_eclk_sel && PWRITE)
  begin
`ifdef GPIO_STRICT_32BIT_ACCESS
    rgpio_eclk <= #1 PWDATA[gw-1:0];
`endif

`ifdef GPIO_WB_BYTES4
       rgpio_eclk [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES3
       rgpio_eclk [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES2
       rgpio_eclk [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES1
       rgpio_eclk [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
   end


`else
assign rgpio_eclk = `GPIO_DEF_RGPIO_ECLK;
`endif






`ifdef GPIO_RGPIO_NEC
always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0)
    rgpio_nec <= #1 {gw{1'b0}};
  else if (rgpio_nec_sel && PWRITE)
  begin
`ifdef GPIO_STRICT_32BIT_ACCESS
    rgpio_nec <= #1 PWDATA[gw-1:0];
`endif

`ifdef GPIO_WB_BYTES4
       rgpio_nec [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES3
       rgpio_nec [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES2
       rgpio_nec [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
`ifdef GPIO_WB_BYTES1
       rgpio_nec [gw-1:0] <= #1 PWDATA [gw-1:0] ;
`endif
   end


`else
assign rgpio_nec = `GPIO_DEF_RGPIO_NEC;
`endif




`ifdef  GPIO_SYNC_IN_WB
always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0) begin
    sync      <= #1 {gw{1'b0}} ; 
    ext_pad_s <= #1 {gw{1'b0}} ; 
  end else begin
    sync      <= #1 ext_pad_i  ; 
    ext_pad_s <= #1 sync       ; 
  end
`else 
assign  ext_pad_s = ext_pad_i;
`endif
  



`ifdef GPIO_RGPIO_IN
always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0)
    rgpio_in <= #1 {gw{1'b0}};
  else
    rgpio_in <= #1 in_muxed;
`else
assign rgpio_in = in_muxed;
`endif

`ifdef GPIO_CLKPAD

`ifdef GPIO_SYNC_CLK_WB






reg  sync_clk,
     clk_s   ,
     clk_r   ;
wire pedge   ,
     nedge   ;
wire [gw-1:0] pedge_vec   ,
              nedge_vec   ;
wire [gw-1:0] in_lach     ;

assign pedge =  clk_s & !clk_r ; 
assign nedge = !clk_s &  clk_r ; 
assign pedge_vec = {gw{pedge}} ;   
assign nedge_vec = {gw{nedge}} ;   

assign in_lach = (~rgpio_nec & pedge_vec) | (rgpio_nec & nedge_vec) ;
assign extc_in = (in_lach & ext_pad_s) | (~in_lach & pextc_sampled) ;

always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0) begin
    sync_clk <= #1 1'b0 ;
    clk_s    <= #1 1'b0 ;
    clk_r    <= #1 1'b0 ;
  end else begin
    sync_clk <= #1 clk_pad_i ;
    clk_s    <= #1 sync_clk  ;
    clk_r    <= #1 clk_s     ;
  end

always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0) begin
    pextc_sampled <= #1 {gw{1'b0}};
  end else begin
    pextc_sampled <= #1 extc_in ;
  end

assign in_muxed = (rgpio_eclk & pextc_sampled) | (~rgpio_eclk & ext_pad_s) ;

`else






`ifdef GPIO_SYNC_IN_CLK_WB

reg [gw-1:0] syn_extc  ,
             extc_s    ;

always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0) begin
    syn_extc  <= #1 {gw{1'b0}};
    extc_s    <= #1 {gw{1'b0}};
  end else begin
    syn_extc  <= #1 extc_in ;
    extc_s    <= #1 syn_extc;
  end

`else

wire [gw-1:0] extc_s   ;
assign extc_s = syn_extc ;

`endif

`ifdef GPIO_SYNC_IN_CLK
reg [gw-1:0] syn_pclk    ,
             ext_pad_spc ;

always @(posedge clk_pad_i or negedge PRESETN)
  if (PRESETN == 0) begin
    syn_pclk    <= #1 {gw{1'b0}} ; 
    ext_pad_spc <= #1 {gw{1'b0}} ; 
  end else begin
    syn_pclk    <= #1 ext_pad_i ; 
    ext_pad_spc <= #1 syn_pclk  ; 
  end

`else

wire [gw-1:0] ext_pad_spc      ;
assign ext_pad_spc = ext_pad_i ;

`endif

always @(posedge clk_pad_i or negedge PRESETN)
  if (PRESETN == 0) begin
    pextc_sampled <= #1 {gw{1'b0}};
  end else begin
    pextc_sampled <= #1 ext_pad_spc ;
  end


`ifdef GPIO_NO_NEGEDGE_FLOPS

`ifdef GPIO_NO_CLKPAD_LOGIC

assign extc_in = pextc_sampled;

`else

wire  clk_n;
assign clk_n = !clk_pad_i;

`ifdef GPIO_SYNC_IN_CLK
reg [gw-1:0] syn_nclk    ,
             ext_pad_snc ;

always @(posedge clk_n or negedge PRESETN)
  if (PRESETN == 0) begin
    syn_nclk    <= #1 {gw{1'b0}} ; 
    ext_pad_snc <= #1 {gw{1'b0}} ; 
  end else begin
    syn_nclk    <= #1 ext_pad_i ; 
    ext_pad_snc <= #1 syn_nclk  ; 
  end

`else

wire [gw-1:0] ext_pad_snc      ;
assign ext_pad_snc = ext_pad_i ;

`endif

always @(posedge clk_n or negedge PRESETN)
  if (PRESETN == 0) begin
    nextc_sampled <= #1 {gw{1'b0}};
  end else begin
    nextc_sampled <= #1 ext_pad_snc ;
  end  

assign extc_in = (~rgpio_nec & pextc_sampled) | (rgpio_nec & nextc_sampled) ;

`endif


`else

`ifdef GPIO_SYNC_IN_CLK
reg [gw-1:0] syn_nclk    ,
             ext_pad_snc ;

always @(negedge clk_n or negedge PRESETN)
  if (PRESETN == 0) begin
    syn_nclk    <= #1 {gw{1'b0}} ; 
    ext_pad_snc <= #1 {gw{1'b0}} ; 
  end else begin
    syn_nclk    <= #1 ext_pad_i ; 
    ext_pad_snc <= #1 syn_nclk  ; 
  end

`else

wire [gw-1:0] ext_pad_snc      ;
assign ext_pad_snc = ext_pad_i ;

`endif

always @(negedge clk_pad_i or negedge PRESETN)
  if (PRESETN == 0) begin
    nextc_sampled <= #1 {gw{1'b0}};
  end else begin
    nextc_sampled <= #1 ext_pad_snc ;
  end

assign extc_in = (~rgpio_nec & pextc_sampled) | (rgpio_nec & nextc_sampled) ;

`endif

assign in_muxed = (rgpio_eclk & extc_s)      | (~rgpio_eclk & ext_pad_s) ;


`endif


`else

assign  in_muxed  = ext_pad_s ;

`endif






always @(PADDR or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or
    rgpio_ptrig or rgpio_aux or rgpio_ctrl or rgpio_ints or rgpio_eclk or rgpio_nec)
  case (PADDR[`GPIO_OFS_BITS])
`ifdef GPIO_READREGS
  `ifdef GPIO_RGPIO_OUT
    `GPIO_RGPIO_OUT: begin
      wb_dat[dw-1:0] = rgpio_out;
    end
  `endif
  `ifdef GPIO_RGPIO_OE
    `GPIO_RGPIO_OE: begin
      wb_dat[dw-1:0] = rgpio_oe;
    end
  `endif
  `ifdef GPIO_RGPIO_INTE
    `GPIO_RGPIO_INTE: begin
      wb_dat[dw-1:0] = rgpio_inte;
    end
  `endif
  `ifdef GPIO_RGPIO_PTRIG
    `GPIO_RGPIO_PTRIG: begin
      wb_dat[dw-1:0] = rgpio_ptrig;
    end
  `endif
  `ifdef GPIO_RGPIO_NEC
    `GPIO_RGPIO_NEC: begin
      wb_dat[dw-1:0] = rgpio_nec;
    end
  `endif
  `ifdef GPIO_RGPIO_ECLK
    `GPIO_RGPIO_ECLK: begin
      wb_dat[dw-1:0] = rgpio_eclk;
    end
  `endif
  `ifdef GPIO_RGPIO_AUX
    `GPIO_RGPIO_AUX: begin
      wb_dat[dw-1:0] = rgpio_aux;
    end
  `endif
  `ifdef GPIO_RGPIO_CTRL
    `GPIO_RGPIO_CTRL: begin
      wb_dat[1:0] = rgpio_ctrl;
      wb_dat[dw-1:2] = {dw-2{1'b0}};
    end
  `endif
`endif
  `ifdef GPIO_RGPIO_INTS
    `GPIO_RGPIO_INTS: begin
      wb_dat[dw-1:0] = rgpio_ints;
    end
  `endif
    default: begin
      wb_dat[dw-1:0] = rgpio_in;
    end
  endcase




`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0)
    PRDATA <= #1 {dw{1'b0}};
  else
    PRDATA <= #1 wb_dat;
`else
assign PRDATA = wb_dat;
`endif




`ifdef GPIO_RGPIO_INTS
always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0)
    rgpio_ints <= #1 {gw{1'b0}};
  else if (rgpio_ints_sel && PWRITE)
    rgpio_ints <= #1 PWDATA[gw-1:0];
  else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
    rgpio_ints <= #1 (rgpio_ints | ((in_muxed ^ rgpio_in) & ~(in_muxed ^ rgpio_ptrig)) & rgpio_inte);
`else
assign rgpio_ints = (rgpio_ints | ((in_muxed ^ rgpio_in) & ~(in_muxed ^ rgpio_ptrig)) & rgpio_inte);
`endif




assign wb_inta = |rgpio_ints ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0;




`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0)
    IRQ <= #1 1'b0;
  else
    IRQ <= #1 wb_inta;
`else
assign IRQ = wb_inta;
`endif




assign ext_padoe_o = rgpio_oe;




`ifdef GPIO_AUX_IMPLEMENT
assign out_pad = rgpio_out & ~rgpio_aux | aux_i & rgpio_aux;
`else
assign out_pad = rgpio_out ;
`endif




`ifdef GPIO_REGISTERED_IO_OUTPUTS
always @(posedge PCLK or negedge PRESETN)
  if (PRESETN == 0)
    ext_pad_o <= #1 {gw{1'b0}};
  else
    ext_pad_o <= #1 out_pad;
`else
assign ext_pad_o = out_pad;
`endif


`else





assign IRQ = 1'b0;
assign PREADY = 1'b0;
assign PSLVERR = 0;
assign ext_padoe_o = {gw{1'b1}};
assign ext_pad_o = {gw{1'b0}};




assign PRDATA = {dw{1'b0}};

`endif

endmodule