data/full_repos/permissive/482720319/reg_dec.v
data/verilator_xmls/8136432b-3f89-45f0-811d-47216d5c4304.xml
module RegDecoder(
      input [3:0] R,
      output [3:0] ext_Rd, ext_Rp 
);

      assign ext_Rd = {2'b11, R[3:2]};
      assign ext_Rp = {2'b10, R[1:0]};

endmodule
module RegDecoder(
      input [3:0] R,
      output [3:0] ext_Rd, ext_Rp 
);


      assign ext_Rd = {2'b11, R[3:2]};
      assign ext_Rp = {2'b10, R[1:0]};

endmodule