data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/nonblocking_gate.v
1: b'%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/nonblocking_gate.v:13: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance nonblocking_gate\n            dout[31:0] <= din;\n                       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/nonblocking_gate.v:15: Operator ASSIGNDLY expects 31 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance nonblocking_gate\n            dout[31:1] <= din;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/nonblocking_gate.v:17: Operator ASSIGNDLY expects 30 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance nonblocking_gate\n            dout[31:2] <= din;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/nonblocking_gate.v:19: Operator ASSIGNDLY expects 29 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance nonblocking_gate\n            dout[31:3] <= din;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/nonblocking_gate.v:21: Operator ASSIGNDLY expects 28 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance nonblocking_gate\n            dout[31:4] <= din;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/nonblocking_gate.v:23: Operator ASSIGNDLY expects 27 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance nonblocking_gate\n            dout[31:5] <= din;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/nonblocking_gate.v:25: Operator ASSIGNDLY expects 26 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance nonblocking_gate\n            dout[31:6] <= din;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/nonblocking_gate.v:27: Operator ASSIGNDLY expects 25 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance nonblocking_gate\n            dout[31:7] <= din;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/nonblocking_gate.v:29: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance nonblocking_gate\n            dout[31:8] <= din;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/nonblocking_gate.v:31: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance nonblocking_gate\n            dout[31:9] <= din;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/nonblocking_gate.v:33: Operator ASSIGNDLY expects 22 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance nonblocking_gate\n            dout[31:10] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/nonblocking_gate.v:35: Operator ASSIGNDLY expects 21 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance nonblocking_gate\n            dout[31:11] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/nonblocking_gate.v:37: Operator ASSIGNDLY expects 20 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance nonblocking_gate\n            dout[31:12] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/nonblocking_gate.v:39: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance nonblocking_gate\n            dout[31:13] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/nonblocking_gate.v:41: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance nonblocking_gate\n            dout[31:14] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/nonblocking_gate.v:43: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance nonblocking_gate\n            dout[31:15] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/nonblocking_gate.v:45: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance nonblocking_gate\n            dout[31:16] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/nonblocking_gate.v:47: Operator ASSIGNDLY expects 15 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance nonblocking_gate\n            dout[31:17] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/nonblocking_gate.v:49: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance nonblocking_gate\n            dout[31:18] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/nonblocking_gate.v:51: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance nonblocking_gate\n            dout[31:19] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/nonblocking_gate.v:53: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance nonblocking_gate\n            dout[31:20] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/nonblocking_gate.v:55: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance nonblocking_gate\n            dout[31:21] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/nonblocking_gate.v:57: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance nonblocking_gate\n            dout[31:22] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/nonblocking_gate.v:59: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance nonblocking_gate\n            dout[31:23] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/nonblocking_gate.v:61: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance nonblocking_gate\n            dout[31:24] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/nonblocking_gate.v:63: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance nonblocking_gate\n            dout[31:25] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/nonblocking_gate.v:65: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance nonblocking_gate\n            dout[31:26] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/nonblocking_gate.v:67: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance nonblocking_gate\n            dout[31:27] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/nonblocking_gate.v:69: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance nonblocking_gate\n            dout[31:28] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/nonblocking_gate.v:71: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance nonblocking_gate\n            dout[31:29] <= din;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/nonblocking_gate.v:75: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                                      : ... In instance nonblocking_gate\n            dout[31:31] <= din;\n                        ^~\n%Error: Exiting due to 31 warning(s)\n'
module nonblocking_gate (clk, ctrl, din, sel, dout);
   input wire clk;
   input wire [4:0] ctrl;
   input wire [1:0] din;
   input wire [0:0] sel;
   output reg [31:0] dout;
   always @(posedge clk)
     begin
        dout <= (dout)+(1);
        case (({(ctrl)*(sel)})+(0))
          0:
            dout[31:0] <= din;
          1:
            dout[31:1] <= din;
          2:
            dout[31:2] <= din;
          3:
            dout[31:3] <= din;
          4:
            dout[31:4] <= din;
          5:
            dout[31:5] <= din;
          6:
            dout[31:6] <= din;
          7:
            dout[31:7] <= din;
          8:
            dout[31:8] <= din;
          9:
            dout[31:9] <= din;
          10:
            dout[31:10] <= din;
          11:
            dout[31:11] <= din;
          12:
            dout[31:12] <= din;
          13:
            dout[31:13] <= din;
          14:
            dout[31:14] <= din;
          15:
            dout[31:15] <= din;
          16:
            dout[31:16] <= din;
          17:
            dout[31:17] <= din;
          18:
            dout[31:18] <= din;
          19:
            dout[31:19] <= din;
          20:
            dout[31:20] <= din;
          21:
            dout[31:21] <= din;
          22:
            dout[31:22] <= din;
          23:
            dout[31:23] <= din;
          24:
            dout[31:24] <= din;
          25:
            dout[31:25] <= din;
          26:
            dout[31:26] <= din;
          27:
            dout[31:27] <= din;
          28:
            dout[31:28] <= din;
          29:
            dout[31:29] <= din;
          30:
            dout[31:30] <= din;
          31:
            dout[31:31] <= din;
        endcase
     end
endmodule
module nonblocking_gate (clk, ctrl, din, sel, dout);

   input wire clk;
   input wire [4:0] ctrl;
   input wire [1:0] din;
   input wire [0:0] sel;
   output reg [31:0] dout;
   always @(posedge clk)
     begin
        dout <= (dout)+(1);
        case (({(ctrl)*(sel)})+(0))
          0:
            dout[31:0] <= din;
          1:
            dout[31:1] <= din;
          2:
            dout[31:2] <= din;
          3:
            dout[31:3] <= din;
          4:
            dout[31:4] <= din;
          5:
            dout[31:5] <= din;
          6:
            dout[31:6] <= din;
          7:
            dout[31:7] <= din;
          8:
            dout[31:8] <= din;
          9:
            dout[31:9] <= din;
          10:
            dout[31:10] <= din;
          11:
            dout[31:11] <= din;
          12:
            dout[31:12] <= din;
          13:
            dout[31:13] <= din;
          14:
            dout[31:14] <= din;
          15:
            dout[31:15] <= din;
          16:
            dout[31:16] <= din;
          17:
            dout[31:17] <= din;
          18:
            dout[31:18] <= din;
          19:
            dout[31:19] <= din;
          20:
            dout[31:20] <= din;
          21:
            dout[31:21] <= din;
          22:
            dout[31:22] <= din;
          23:
            dout[31:23] <= din;
          24:
            dout[31:24] <= din;
          25:
            dout[31:25] <= din;
          26:
            dout[31:26] <= din;
          27:
            dout[31:27] <= din;
          28:
            dout[31:28] <= din;
          29:
            dout[31:29] <= din;
          30:
            dout[31:30] <= din;
          31:
            dout[31:31] <= din;
        endcase
     end
endmodule