data/full_repos/permissive/458134463/Modules/adder_4bit.v
1: b"%Error: data/full_repos/permissive/458134463/Modules/adder_4bit.v:16: Cannot find file containing module: 'full_adder'\nfull_adder fa_1(value1[0], value2[0], sum[0], c1       , carry_in),\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458134463/Modules,data/full_repos/permissive/458134463/full_adder\n             data/full_repos/permissive/458134463/Modules,data/full_repos/permissive/458134463/full_adder.v\n             data/full_repos/permissive/458134463/Modules,data/full_repos/permissive/458134463/full_adder.sv\n             full_adder\n             full_adder.v\n             full_adder.sv\n             obj_dir/full_adder\n             obj_dir/full_adder.v\n             obj_dir/full_adder.sv\n%Error: Exiting due to 1 error(s)\n"
module adder_4bit(value1, value2, sum, carry_out, carry_in, overflow);

input [3:0] value1;
input [3:0] value2;
input carry_in;

output [3:0] sum;
output carry_out;
output overflow;

wire c1;
wire c2;
wire c3;


full_adder fa_1(value1[0], value2[0], sum[0], c1       , carry_in),
			  fa_2(value1[1], value2[1], sum[1], c2       , c1      ),
           fa_3(value1[2], value2[2], sum[2], c3       , c2      ),
           fa_4(value1[3], value2[3], sum[3], carry_out, c3      );


xor xor1(overflow, c3, carry_out);

endmodule
module adder_4bit(value1, value2, sum, carry_out, carry_in, overflow);


input [3:0] value1;
input [3:0] value2;
input carry_in;

output [3:0] sum;
output carry_out;
output overflow;

wire c1;
wire c2;
wire c3;


full_adder fa_1(value1[0], value2[0], sum[0], c1       , carry_in),
			  fa_2(value1[1], value2[1], sum[1], c2       , c1      ),
           fa_3(value1[2], value2[2], sum[2], c3       , c2      ),
           fa_4(value1[3], value2[3], sum[3], carry_out, c3      );


xor xor1(overflow, c3, carry_out);

endmodule