data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v
1: b'%Warning-REDEFMACRO: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:198: Redefining existing define: \'M_W\', with different value: 8\n                     ... Use "/* verilator lint_off REDEFMACRO */" and lint_on around source to disable this message.\n%Warning-REDEFMACRO: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:198: Previous definition is here, with value: 4\n%Warning-PINMISSING: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:379: Cell has missing pin: \'RST\'\nmb24 b_mult(\n     ^~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:499: Cannot find file containing module: \'HALF_ADDER\'\nHALF_ADDER ha000(.a(cv[0]), .b(fpp0[0]) , .sum(has000), .cout(hac000));\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/HALF_ADDER\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/HALF_ADDER.v\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/HALF_ADDER.sv\n             HALF_ADDER\n             HALF_ADDER.v\n             HALF_ADDER.sv\n             obj_dir/HALF_ADDER\n             obj_dir/HALF_ADDER.v\n             obj_dir/HALF_ADDER.sv\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:500: Cannot find file containing module: \'HALF_ADDER\'\nHALF_ADDER ha001(.a(cv[1]), .b(fpp0[1]) , .sum(has001), .cout(hac001));\n^~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:501: Cannot find file containing module: \'HALF_ADDER\'\nHALF_ADDER ha002(.a(cv[2]), .b(fpp0[2]) , .sum(has002), .cout(hac002));\n^~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:505: Cannot find file containing module: \'HALF_ADDER\'\nHALF_ADDER aha002(.a(cv[7]), .b(fpp1[4]) , .sum(ahas002), .cout(ahac002));\n^~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:509: Cannot find file containing module: \'FULL_ADDER\'\n                FULL_ADDER fa000(.a(cv[i + 3]), .b(fpp0[i + 3]), .cin(fpp1[i]), .sum(fas0[i]), .cout(fac0[i]));\n                ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:209: Operator ADD expects 6 bits on the LHS, but LHS\'s VARREF \'my\' generates 4 bits.\n                                                                                  : ... In instance sa_2D.pre_process[1].prep00\nassign SUM=my+(my<<1);\n             ^\n%Warning-WIDTH: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:209: Operator SHIFTL expects 6 bits on the LHS, but LHS\'s VARREF \'my\' generates 4 bits.\n                                                                                  : ... In instance sa_2D.pre_process[1].prep00\nassign SUM=my+(my<<1);\n                 ^~\n%Warning-LITENDIAN: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:43: Little bit endian vector: MSB < LSB of bit range: 0:1\nreg [0:HPE-1]D_SHIFTEN;\n    ^\n%Error: Exiting due to 5 error(s), 6 warning(s)\n'
module sa_2D( AA, BB, CLK,SHIFTEN ,RST, Y);

parameter HPE=2;
parameter VPE=2;

parameter WIDTH=4;
`define P_W 8
`define M_W 4
parameter group_cnt=(WIDTH>>2)+1;

input   [WIDTH*HPE-1:0]  AA;
input   [WIDTH*HPE-1:0]  BB;
input           CLK;
input           RST;
input 	[1:0]	   SHIFTEN;
output   [(2*WIDTH*HPE*VPE)-1:0]  Y;

wire [WIDTH-1:0] Ain[0:HPE-1];
wire [WIDTH-1:0] Bin[0:HPE-1];

genvar z;
  generate for (z = 0; z < HPE; z = z+1) begin:Input_weights 
      assign Ain[z] = AA[(((z+1)*WIDTH)-1) : ((z)*WIDTH)];
      assign Bin[z] = BB[(((z+1)*WIDTH)-1) : ((z)*WIDTH)];
end
endgenerate


wire [group_cnt - 1:0] S [0:VPE-1][0:HPE-1];
wire [group_cnt - 1:0] D [0:VPE-1][0:HPE-1];
wire [group_cnt - 1:0] T [0:VPE-1][0:HPE-1];
wire [group_cnt - 1:0] Q [0:VPE-1][0:HPE-1];
wire [group_cnt - 1:0] N [0:VPE-1][0:HPE-1];



wire [WIDTH-1:0] MY_OUT[0:VPE-1][0:HPE-1];

wire [WIDTH+1:0] TMY[0:VPE-1][0:HPE-1];

wire [WIDTH*2-1:0] Y_OUT[0:VPE-1][0:HPE-1];
reg [0:HPE-1]D_SHIFTEN;
wire  SHIFTEN_OUT [0:HPE-1][0:HPE-1];



assign Y[31:24]=Y_OUT[0][0];
assign Y[23:16]=Y_OUT[0][1];
assign Y[15:8]=Y_OUT[1][0];
assign Y[7:0]=Y_OUT[1][1];

wire [group_cnt - 1:0] s [0:HPE-1];
wire [group_cnt - 1:0] d [0:HPE-1];
wire [group_cnt - 1:0] t [0:HPE-1];
wire [group_cnt - 1:0] q [0:HPE-1];
wire [group_cnt - 1:0] n [0:HPE-1];

genvar l;
generate
	for (l = 0; l < HPE; l = l + 1) begin: pre_pro1
    pre_process_be pre_pro_be(.mx(Ain[l]), .CLK(CLK), .sr(s[l]), .dr(d[l]), .tr(t[l]), .qr(q[l]), .nr(n[l]));
    end
endgenerate    


genvar k;
generate
	for (k = 0; k < HPE; k = k + 1) begin: pre_process
    sa_pre_process_TMY prep00(.my(Bin[k]), .CLK(CLK), .RST(RST), .my_out(MY_OUT[k][0]), .TMY(TMY[k][0])); 	
    end
endgenerate        





PE_OS_16_R8 PE00( .s(s[0]), .d(d[0]), .t(t[0]), .q(q[0]), .n(n[0]), .Y(MY_OUT[0][0]), .TMY(TMY[0][0]), .CLK(CLK),
 .RST(RST),.SHIFTEN(D_SHIFTEN[0]),.SHIFTV(8'b0),.S_OUT(S[0][0]), .D_OUT(D[0][0]), .T_OUT(T[0][0]), .Q_OUT(Q[0][0]),
  .N_OUT(N[0][0]), .Y_OUT(MY_OUT[0][1]), .TMY_OUT(TMY[0][1]), .MAC_OUT(Y_OUT[0][0]),.SHIFTEN_OUT(SHIFTEN_OUT[0][0]));

PE_OS_16_R8 PE1111( .s(s[1]), .d(d[1]), .t(t[1]), .q(q[1]), .n(n[1]), .Y(MY_OUT[0][1]), .TMY(TMY[0][1]), .CLK(CLK),
 .RST(RST),.SHIFTEN(D_SHIFTEN[1]),.SHIFTV(8'b0),.S_OUT(S[1][0]), .D_OUT(D[1][0]), .T_OUT(T[1][0]), .Q_OUT(Q[1][0]),
  .N_OUT(N[1][0]), .Y_OUT(), .TMY_OUT(), .MAC_OUT(Y_OUT[1][0]), .SHIFTEN_OUT(SHIFTEN_OUT[1][0]) );

PE_OS_16_R8 PEyy( .s(S[0][0]), .d(D[0][0]), .t(T[0][0]), .q(Q[0][0]), .n(N[0][0]), .Y(MY_OUT[1][0]), .TMY(TMY[1][0]),
 .CLK(CLK), .RST(RST),.SHIFTEN(SHIFTEN_OUT[0][0]),.SHIFTV(Y_OUT[0][0]),.S_OUT(S[0][1]), .D_OUT(D[0][1]), .T_OUT(T[0][1]),
  .Q_OUT(Q[0][1]), .N_OUT(N[0][1]), .Y_OUT(MY_OUT[1][1]), .TMY_OUT(TMY[1][1]), .MAC_OUT(Y_OUT[0][1]),.SHIFTEN_OUT(SHIFTEN_OUT[0][1]) );

PE_OS_16_R8 PEzz( .s(S[1][0]), .d(D[1][0]), .t(T[1][0]), .q(Q[1][0]), .n(N[1][0]), .Y(MY_OUT[1][1]), .TMY(TMY[1][1]),
.CLK(CLK), .RST(RST),.SHIFTEN(SHIFTEN_OUT[1][0]),.SHIFTV(Y_OUT[1][0]),.S_OUT(S[1][1]), .D_OUT(D[1][1]), .T_OUT(T[1][1]),
 .Q_OUT(Q[1][1]), .N_OUT(N[1][1]), .Y_OUT(), .TMY_OUT(), .MAC_OUT(Y_OUT[1][1]),.SHIFTEN_OUT(SHIFTEN_OUT[1][1]) );


  
always @(posedge CLK)
begin  
  D_SHIFTEN <= SHIFTEN;
end
  
  
  
  
endmodule
module sa_2D( AA, BB, CLK,SHIFTEN ,RST, Y);


parameter HPE=2;
parameter VPE=2;

parameter WIDTH=4;
`define P_W 8
`define M_W 4
parameter group_cnt=(WIDTH>>2)+1;

input   [WIDTH*HPE-1:0]  AA;
input   [WIDTH*HPE-1:0]  BB;
input           CLK;
input           RST;
input 	[1:0]	   SHIFTEN;
output   [(2*WIDTH*HPE*VPE)-1:0]  Y;

wire [WIDTH-1:0] Ain[0:HPE-1];
wire [WIDTH-1:0] Bin[0:HPE-1];

genvar z;
  generate for (z = 0; z < HPE; z = z+1) begin:Input_weights 
      assign Ain[z] = AA[(((z+1)*WIDTH)-1) : ((z)*WIDTH)];
      assign Bin[z] = BB[(((z+1)*WIDTH)-1) : ((z)*WIDTH)];
end
endgenerate


wire [group_cnt - 1:0] S [0:VPE-1][0:HPE-1];
wire [group_cnt - 1:0] D [0:VPE-1][0:HPE-1];
wire [group_cnt - 1:0] T [0:VPE-1][0:HPE-1];
wire [group_cnt - 1:0] Q [0:VPE-1][0:HPE-1];
wire [group_cnt - 1:0] N [0:VPE-1][0:HPE-1];



wire [WIDTH-1:0] MY_OUT[0:VPE-1][0:HPE-1];

wire [WIDTH+1:0] TMY[0:VPE-1][0:HPE-1];

wire [WIDTH*2-1:0] Y_OUT[0:VPE-1][0:HPE-1];
reg [0:HPE-1]D_SHIFTEN;
wire  SHIFTEN_OUT [0:HPE-1][0:HPE-1];



assign Y[31:24]=Y_OUT[0][0];
assign Y[23:16]=Y_OUT[0][1];
assign Y[15:8]=Y_OUT[1][0];
assign Y[7:0]=Y_OUT[1][1];

wire [group_cnt - 1:0] s [0:HPE-1];
wire [group_cnt - 1:0] d [0:HPE-1];
wire [group_cnt - 1:0] t [0:HPE-1];
wire [group_cnt - 1:0] q [0:HPE-1];
wire [group_cnt - 1:0] n [0:HPE-1];

genvar l;
generate
	for (l = 0; l < HPE; l = l + 1) begin: pre_pro1
    pre_process_be pre_pro_be(.mx(Ain[l]), .CLK(CLK), .sr(s[l]), .dr(d[l]), .tr(t[l]), .qr(q[l]), .nr(n[l]));
    end
endgenerate    


genvar k;
generate
	for (k = 0; k < HPE; k = k + 1) begin: pre_process
    sa_pre_process_TMY prep00(.my(Bin[k]), .CLK(CLK), .RST(RST), .my_out(MY_OUT[k][0]), .TMY(TMY[k][0])); 	
    end
endgenerate        





PE_OS_16_R8 PE00( .s(s[0]), .d(d[0]), .t(t[0]), .q(q[0]), .n(n[0]), .Y(MY_OUT[0][0]), .TMY(TMY[0][0]), .CLK(CLK),
 .RST(RST),.SHIFTEN(D_SHIFTEN[0]),.SHIFTV(8'b0),.S_OUT(S[0][0]), .D_OUT(D[0][0]), .T_OUT(T[0][0]), .Q_OUT(Q[0][0]),
  .N_OUT(N[0][0]), .Y_OUT(MY_OUT[0][1]), .TMY_OUT(TMY[0][1]), .MAC_OUT(Y_OUT[0][0]),.SHIFTEN_OUT(SHIFTEN_OUT[0][0]));

PE_OS_16_R8 PE1111( .s(s[1]), .d(d[1]), .t(t[1]), .q(q[1]), .n(n[1]), .Y(MY_OUT[0][1]), .TMY(TMY[0][1]), .CLK(CLK),
 .RST(RST),.SHIFTEN(D_SHIFTEN[1]),.SHIFTV(8'b0),.S_OUT(S[1][0]), .D_OUT(D[1][0]), .T_OUT(T[1][0]), .Q_OUT(Q[1][0]),
  .N_OUT(N[1][0]), .Y_OUT(), .TMY_OUT(), .MAC_OUT(Y_OUT[1][0]), .SHIFTEN_OUT(SHIFTEN_OUT[1][0]) );

PE_OS_16_R8 PEyy( .s(S[0][0]), .d(D[0][0]), .t(T[0][0]), .q(Q[0][0]), .n(N[0][0]), .Y(MY_OUT[1][0]), .TMY(TMY[1][0]),
 .CLK(CLK), .RST(RST),.SHIFTEN(SHIFTEN_OUT[0][0]),.SHIFTV(Y_OUT[0][0]),.S_OUT(S[0][1]), .D_OUT(D[0][1]), .T_OUT(T[0][1]),
  .Q_OUT(Q[0][1]), .N_OUT(N[0][1]), .Y_OUT(MY_OUT[1][1]), .TMY_OUT(TMY[1][1]), .MAC_OUT(Y_OUT[0][1]),.SHIFTEN_OUT(SHIFTEN_OUT[0][1]) );

PE_OS_16_R8 PEzz( .s(S[1][0]), .d(D[1][0]), .t(T[1][0]), .q(Q[1][0]), .n(N[1][0]), .Y(MY_OUT[1][1]), .TMY(TMY[1][1]),
.CLK(CLK), .RST(RST),.SHIFTEN(SHIFTEN_OUT[1][0]),.SHIFTV(Y_OUT[1][0]),.S_OUT(S[1][1]), .D_OUT(D[1][1]), .T_OUT(T[1][1]),
 .Q_OUT(Q[1][1]), .N_OUT(N[1][1]), .Y_OUT(), .TMY_OUT(), .MAC_OUT(Y_OUT[1][1]),.SHIFTEN_OUT(SHIFTEN_OUT[1][1]) );


  
always @(posedge CLK)
begin  
  D_SHIFTEN <= SHIFTEN;
end
  
  
  
  
endmodule