data/full_repos/permissive/419538859/lab2/lab2_3/lab2_3.v
1: b"%Error: data/full_repos/permissive/419538859/lab2/lab2_3/lab2_3.v:11: syntax error, unexpected '(', expecting IDENTIFIER\nfreq_div #(21) (clk,reset,clk_count);  \n                ^~~\n%Error: data/full_repos/permissive/419538859/lab2/lab2_3/lab2_3.v:12: syntax error, unexpected '(', expecting IDENTIFIER\nfreq_div #(17) (clk,reset,clk_sel);  \n                ^~~\n%Error: data/full_repos/permissive/419538859/lab2/lab2_3/lab2_3.v:15: syntax error, unexpected '(', expecting IDENTIFIER\nseg7_select #(2) (clk_sel,reset,seg7_sel);\n                  ^~~~~~~\n%Error: data/full_repos/permissive/419538859/lab2/lab2_3/lab2_3.v:23: syntax error, unexpected '(', expecting IDENTIFIER\ncount_0_9 (clk,reset,enable,carry0,count0_out);\n           ^~~\n%Error: Exiting due to 4 error(s)\n"
module lab2_3(clk, reset, seg7_sel, enable,seg7_out, dpt_out, carry_out, led_com);
input		clk, reset,enable;
output[2:0]	seg7_sel;
output[6:0] seg7_out;
output		dpt_out, carry_out, led_com;
wire		clk_count, clk_sel;
wire[3:0] 	count_out, count_out1, count_out0;
assign		dpt_out= 1'b0;
assign		led_com= 1'b1;
assign  	count_out= seg7_sel[0] ? count_out0 : count_out1;
freq_div #(21) (clk,reset,clk_count);
freq_div #(17) (clk,reset,clk_sel);
count_00_99	 (clk_count, reset, enable, count_out1, count_out0, carry_out);
bcd_to_seg7_1 (count_out,seg7_out);
seg7_select #(2) (clk_sel,reset,seg7_sel);
endmodule
module lab2_3(clk, reset, seg7_sel, enable,seg7_out, dpt_out, carry_out, led_com);

input		clk, reset,enable;
output[2:0]	seg7_sel;
output[6:0] seg7_out;
output		dpt_out, carry_out, led_com;
wire		clk_count, clk_sel;
wire[3:0] 	count_out, count_out1, count_out0;
assign		dpt_out= 1'b0;
assign		led_com= 1'b1;
assign  	count_out= seg7_sel[0] ? count_out0 : count_out1;
freq_div #(21) (clk,reset,clk_count);
freq_div #(17) (clk,reset,clk_sel);
count_00_99	 (clk_count, reset, enable, count_out1, count_out0, carry_out);
bcd_to_seg7_1 (count_out,seg7_out);
seg7_select #(2) (clk_sel,reset,seg7_sel);
endmodule