data/full_repos/permissive/494664634/AxiS2MMTest/src/hdl/AxiS2MMTest.v
data/verilator_xmls/8782da5f-17bb-4ce7-b810-c4989e6c3866.xml
module AxiCtrlS2MM(
  input         clock,
  input         reset,
  input  [31:0] s_axi_araddr,
  input         s_axi_arvalid,
  output        s_axi_arready,
  output [31:0] s_axi_rdata,
  output        s_axi_rvalid,
  input         s_axi_rready,
  input  [31:0] s_axi_awaddr,
  input         s_axi_awvalid,
  output        s_axi_awready,
  input  [31:0] s_axi_wdata,
  input         s_axi_wvalid,
  output        s_axi_wready,
  output        s_axi_bvalid,
  input         s_axi_bready,
  output        start,
  input         done,
  output [31:0] write_addr,
  output [31:0] write_length
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
`endif
  wire  axi_ctrl_clock;
  wire  axi_ctrl_reset;
  wire [31:0] axi_ctrl_s_axi_araddr;
  wire  axi_ctrl_s_axi_arvalid;
  wire  axi_ctrl_s_axi_arready;
  wire [31:0] axi_ctrl_s_axi_rdata;
  wire  axi_ctrl_s_axi_rvalid;
  wire  axi_ctrl_s_axi_rready;
  wire [31:0] axi_ctrl_s_axi_awaddr;
  wire  axi_ctrl_s_axi_awvalid;
  wire  axi_ctrl_s_axi_awready;
  wire [31:0] axi_ctrl_s_axi_wdata;
  wire  axi_ctrl_s_axi_wvalid;
  wire  axi_ctrl_s_axi_wready;
  wire  axi_ctrl_s_axi_bvalid;
  wire  axi_ctrl_s_axi_bready;
  wire  axi_ctrl_wr_en;
  wire  axi_ctrl_rd_en;
  wire [11:0] axi_ctrl_wr_addr;
  wire [11:0] axi_ctrl_rd_addr;
  wire [31:0] axi_ctrl_wr_data;
  wire [31:0] axi_ctrl_rd_data;
  reg [31:0] int_write_addr;
  reg [31:0] int_write_length;
  wire [31:0] _GEN_0 = axi_ctrl_wr_addr == 12'h0 ? axi_ctrl_wr_data : 32'h0;
  wire [31:0] _GEN_3 = axi_ctrl_wr_en ? _GEN_0 : 32'h0;
  wire [15:0] _GEN_6 = axi_ctrl_rd_addr == 12'h4 ? {{15'd0}, done} : 16'hdead;
  wire [15:0] _GEN_7 = axi_ctrl_rd_en ? _GEN_6 : 16'hdead;
  AxiLiteControl axi_ctrl (
    .clock(axi_ctrl_clock),
    .reset(axi_ctrl_reset),
    .s_axi_araddr(axi_ctrl_s_axi_araddr),
    .s_axi_arvalid(axi_ctrl_s_axi_arvalid),
    .s_axi_arready(axi_ctrl_s_axi_arready),
    .s_axi_rdata(axi_ctrl_s_axi_rdata),
    .s_axi_rvalid(axi_ctrl_s_axi_rvalid),
    .s_axi_rready(axi_ctrl_s_axi_rready),
    .s_axi_awaddr(axi_ctrl_s_axi_awaddr),
    .s_axi_awvalid(axi_ctrl_s_axi_awvalid),
    .s_axi_awready(axi_ctrl_s_axi_awready),
    .s_axi_wdata(axi_ctrl_s_axi_wdata),
    .s_axi_wvalid(axi_ctrl_s_axi_wvalid),
    .s_axi_wready(axi_ctrl_s_axi_wready),
    .s_axi_bvalid(axi_ctrl_s_axi_bvalid),
    .s_axi_bready(axi_ctrl_s_axi_bready),
    .wr_en(axi_ctrl_wr_en),
    .rd_en(axi_ctrl_rd_en),
    .wr_addr(axi_ctrl_wr_addr),
    .rd_addr(axi_ctrl_rd_addr),
    .wr_data(axi_ctrl_wr_data),
    .rd_data(axi_ctrl_rd_data)
  );
  assign s_axi_arready = axi_ctrl_s_axi_arready;
  assign s_axi_rdata = axi_ctrl_s_axi_rdata;
  assign s_axi_rvalid = axi_ctrl_s_axi_rvalid;
  assign s_axi_awready = axi_ctrl_s_axi_awready;
  assign s_axi_wready = axi_ctrl_s_axi_wready;
  assign s_axi_bvalid = axi_ctrl_s_axi_bvalid;
  assign start = _GEN_3[0];
  assign write_addr = int_write_addr;
  assign write_length = int_write_length;
  assign axi_ctrl_clock = clock;
  assign axi_ctrl_reset = reset;
  assign axi_ctrl_s_axi_araddr = s_axi_araddr;
  assign axi_ctrl_s_axi_arvalid = s_axi_arvalid;
  assign axi_ctrl_s_axi_rready = s_axi_rready;
  assign axi_ctrl_s_axi_awaddr = s_axi_awaddr;
  assign axi_ctrl_s_axi_awvalid = s_axi_awvalid;
  assign axi_ctrl_s_axi_wdata = s_axi_wdata;
  assign axi_ctrl_s_axi_wvalid = s_axi_wvalid;
  assign axi_ctrl_s_axi_bready = s_axi_bready;
  assign axi_ctrl_rd_data = {{16'd0}, _GEN_7};
  always @(posedge clock) begin
    if (reset) begin
      int_write_addr <= 32'h0;
    end else if (axi_ctrl_wr_en) begin
      if (axi_ctrl_wr_addr == 12'h10) begin
        int_write_addr <= axi_ctrl_wr_data;
      end
    end
    if (reset) begin
      int_write_length <= 32'h0;
    end else if (axi_ctrl_wr_en) begin
      if (axi_ctrl_wr_addr == 12'h14) begin
        int_write_length <= axi_ctrl_wr_data;
      end
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  int_write_addr = _RAND_0[31:0];
  _RAND_1 = {1{`RANDOM}};
  int_write_length = _RAND_1[31:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module AxiCtrlS2MM(
  input         clock,
  input         reset,
  input  [31:0] s_axi_araddr,
  input         s_axi_arvalid,
  output        s_axi_arready,
  output [31:0] s_axi_rdata,
  output        s_axi_rvalid,
  input         s_axi_rready,
  input  [31:0] s_axi_awaddr,
  input         s_axi_awvalid,
  output        s_axi_awready,
  input  [31:0] s_axi_wdata,
  input         s_axi_wvalid,
  output        s_axi_wready,
  output        s_axi_bvalid,
  input         s_axi_bready,
  output        start,
  input         done,
  output [31:0] write_addr,
  output [31:0] write_length
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
`endif
  wire  axi_ctrl_clock;
  wire  axi_ctrl_reset;
  wire [31:0] axi_ctrl_s_axi_araddr;
  wire  axi_ctrl_s_axi_arvalid;
  wire  axi_ctrl_s_axi_arready;
  wire [31:0] axi_ctrl_s_axi_rdata;
  wire  axi_ctrl_s_axi_rvalid;
  wire  axi_ctrl_s_axi_rready;
  wire [31:0] axi_ctrl_s_axi_awaddr;
  wire  axi_ctrl_s_axi_awvalid;
  wire  axi_ctrl_s_axi_awready;
  wire [31:0] axi_ctrl_s_axi_wdata;
  wire  axi_ctrl_s_axi_wvalid;
  wire  axi_ctrl_s_axi_wready;
  wire  axi_ctrl_s_axi_bvalid;
  wire  axi_ctrl_s_axi_bready;
  wire  axi_ctrl_wr_en;
  wire  axi_ctrl_rd_en;
  wire [11:0] axi_ctrl_wr_addr;
  wire [11:0] axi_ctrl_rd_addr;
  wire [31:0] axi_ctrl_wr_data;
  wire [31:0] axi_ctrl_rd_data;
  reg [31:0] int_write_addr;
  reg [31:0] int_write_length;
  wire [31:0] _GEN_0 = axi_ctrl_wr_addr == 12'h0 ? axi_ctrl_wr_data : 32'h0;
  wire [31:0] _GEN_3 = axi_ctrl_wr_en ? _GEN_0 : 32'h0;
  wire [15:0] _GEN_6 = axi_ctrl_rd_addr == 12'h4 ? {{15'd0}, done} : 16'hdead;
  wire [15:0] _GEN_7 = axi_ctrl_rd_en ? _GEN_6 : 16'hdead;
  AxiLiteControl axi_ctrl (
    .clock(axi_ctrl_clock),
    .reset(axi_ctrl_reset),
    .s_axi_araddr(axi_ctrl_s_axi_araddr),
    .s_axi_arvalid(axi_ctrl_s_axi_arvalid),
    .s_axi_arready(axi_ctrl_s_axi_arready),
    .s_axi_rdata(axi_ctrl_s_axi_rdata),
    .s_axi_rvalid(axi_ctrl_s_axi_rvalid),
    .s_axi_rready(axi_ctrl_s_axi_rready),
    .s_axi_awaddr(axi_ctrl_s_axi_awaddr),
    .s_axi_awvalid(axi_ctrl_s_axi_awvalid),
    .s_axi_awready(axi_ctrl_s_axi_awready),
    .s_axi_wdata(axi_ctrl_s_axi_wdata),
    .s_axi_wvalid(axi_ctrl_s_axi_wvalid),
    .s_axi_wready(axi_ctrl_s_axi_wready),
    .s_axi_bvalid(axi_ctrl_s_axi_bvalid),
    .s_axi_bready(axi_ctrl_s_axi_bready),
    .wr_en(axi_ctrl_wr_en),
    .rd_en(axi_ctrl_rd_en),
    .wr_addr(axi_ctrl_wr_addr),
    .rd_addr(axi_ctrl_rd_addr),
    .wr_data(axi_ctrl_wr_data),
    .rd_data(axi_ctrl_rd_data)
  );
  assign s_axi_arready = axi_ctrl_s_axi_arready;
  assign s_axi_rdata = axi_ctrl_s_axi_rdata;
  assign s_axi_rvalid = axi_ctrl_s_axi_rvalid;
  assign s_axi_awready = axi_ctrl_s_axi_awready;
  assign s_axi_wready = axi_ctrl_s_axi_wready;
  assign s_axi_bvalid = axi_ctrl_s_axi_bvalid;
  assign start = _GEN_3[0];
  assign write_addr = int_write_addr;
  assign write_length = int_write_length;
  assign axi_ctrl_clock = clock;
  assign axi_ctrl_reset = reset;
  assign axi_ctrl_s_axi_araddr = s_axi_araddr;
  assign axi_ctrl_s_axi_arvalid = s_axi_arvalid;
  assign axi_ctrl_s_axi_rready = s_axi_rready;
  assign axi_ctrl_s_axi_awaddr = s_axi_awaddr;
  assign axi_ctrl_s_axi_awvalid = s_axi_awvalid;
  assign axi_ctrl_s_axi_wdata = s_axi_wdata;
  assign axi_ctrl_s_axi_wvalid = s_axi_wvalid;
  assign axi_ctrl_s_axi_bready = s_axi_bready;
  assign axi_ctrl_rd_data = {{16'd0}, _GEN_7};
  always @(posedge clock) begin
    if (reset) begin
      int_write_addr <= 32'h0;
    end else if (axi_ctrl_wr_en) begin
      if (axi_ctrl_wr_addr == 12'h10) begin
        int_write_addr <= axi_ctrl_wr_data;
      end
    end
    if (reset) begin
      int_write_length <= 32'h0;
    end else if (axi_ctrl_wr_en) begin
      if (axi_ctrl_wr_addr == 12'h14) begin
        int_write_length <= axi_ctrl_wr_data;
      end
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  int_write_addr = _RAND_0[31:0];
  _RAND_1 = {1{`RANDOM}};
  int_write_length = _RAND_1[31:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule