data/full_repos/permissive/506636840/rtl/uart/rtl/uart_apb.v
1: b'%Error: data/full_repos/permissive/506636840/rtl/uart/rtl/uart_apb.v:24: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/506636840/rtl/uart/rtl,data/full_repos/permissive/506636840/timescale.v\n             data/full_repos/permissive/506636840/rtl/uart/rtl,data/full_repos/permissive/506636840/timescale.v.v\n             data/full_repos/permissive/506636840/rtl/uart/rtl,data/full_repos/permissive/506636840/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: Exiting due to 1 error(s)\n'
module uart_apb(input PCLK,
                input PRESETn,
                input PSEL,
                input PWRITE,
                input PENABLE,
                output logic PREADY,
                output logic we_o,
                output logic re_o);
                
typedef enum {IDLE, SETUP, ACCESS} APB_STATE;

APB_STATE fsm_state;

always @(posedge PCLK)
  begin
    if (PRESETn == 0)
      begin
        we_o = 0;
        re_o = 0;
        PREADY = 0;
        fsm_state = IDLE;
      end
    else
      case (fsm_state)
        IDLE: begin
                we_o <= 0;
                re_o <= 0;
                PREADY <= 0;
                if (PSEL)
                  fsm_state <= SETUP;
              end
        SETUP: if (PSEL && PENABLE)
                 begin
                   fsm_state <= ACCESS;
                   if (PWRITE)
                     we_o <= 1;
                   else
                     re_o <= 1;
                 end
               else
                 fsm_state <= IDLE;
        ACCESS: begin
                  PREADY <= 1;
                  we_o <= 0;
                  re_o <= 0;
                  fsm_state <= IDLE;
                end
        default: fsm_state <= IDLE;
      endcase
  end
  
endmodule
module uart_apb(input PCLK,
                input PRESETn,
                input PSEL,
                input PWRITE,
                input PENABLE,
                output logic PREADY,
                output logic we_o,
                output logic re_o);

                
typedef enum {IDLE, SETUP, ACCESS} APB_STATE;

APB_STATE fsm_state;

always @(posedge PCLK)
  begin
    if (PRESETn == 0)
      begin
        we_o = 0;
        re_o = 0;
        PREADY = 0;
        fsm_state = IDLE;
      end
    else
      case (fsm_state)
        IDLE: begin
                we_o <= 0;
                re_o <= 0;
                PREADY <= 0;
                if (PSEL)
                  fsm_state <= SETUP;
              end
        SETUP: if (PSEL && PENABLE)
                 begin
                   fsm_state <= ACCESS;
                   if (PWRITE)
                     we_o <= 1;
                   else
                     re_o <= 1;
                 end
               else
                 fsm_state <= IDLE;
        ACCESS: begin
                  PREADY <= 1;
                  we_o <= 0;
                  re_o <= 0;
                  fsm_state <= IDLE;
                end
        default: fsm_state <= IDLE;
      endcase
  end
  
endmodule