data/full_repos/permissive/43858668/final_verilog/src/clib/c_rr_arbiter.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_rr_arbiter.v:35: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_constants.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_constants.v.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_constants.v.sv\n             c_constants.v\n             c_constants.v.v\n             c_constants.v.sv\n             obj_dir/c_constants.v\n             obj_dir/c_constants.v.v\n             obj_dir/c_constants.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_rr_arbiter.v:36: Cannot find include file: c_functions.v\n`include "c_functions.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_rr_arbiter.v:50: Define or directive not defined: \'`RESET_TYPE_ASYNC\'\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_rr_arbiter.v:50: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                                           ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_rr_arbiter.v:171: Define or directive not defined: \'`BINARY_OP_OR\'\n        .op(`BINARY_OP_OR))\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_rr_arbiter.v:189: Define or directive not defined: \'`BINARY_OP_AND\'\n        .op(`BINARY_OP_AND))\n            ^~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n'
module c_rr_arbiter
  (clk, reset, active, req_pr, gnt_pr, gnt, update);
   
`include "c_constants.v"
`include "c_functions.v"
   

   parameter num_ports = 32;
   

   parameter num_priorities = 1;
   

   parameter encode_state = 1;
   

   localparam state_width = clogb(num_ports);
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   input clk;
   input reset;
   input active;
   

   input [0:num_priorities*num_ports-1] req_pr;
   

   output [0:num_priorities*num_ports-1] gnt_pr;
   wire [0:num_priorities*num_ports-1] 	 gnt_pr;
   

   output [0:num_ports-1] 		 gnt;
   wire [0:num_ports-1] 		 gnt;
   

   input 				 update;
   
   wire [0:num_priorities*num_ports-1] 	 gnt_intm_pr;
   
   wire [0:num_ports-1] 		 mask;
   
   genvar 				 prio;
   
   generate
      
      for(prio = 0; prio < num_priorities; prio = prio + 1)
	begin:prios
	   
	   wire [0:num_ports-1] req;
	   assign req = req_pr[prio*num_ports:(prio+1)*num_ports-1];
	   
	   wire [0:num_ports-1] gnt;
	   c_rr_arbiter_base
	     #(.num_ports(num_ports))
	   gnt_ab
	     (.mask(mask),
	      .req(req),
	      .gnt(gnt));
	   
	   assign gnt_intm_pr[prio*num_ports:(prio+1)*num_ports-1] = gnt;
	   
	end
      
      if(encode_state)
	begin
	   
	   wire [0:state_width-1] next_state;
	   c_encode
	     #(.num_ports(num_ports),
	       .offset(1))
	   next_state_enc
	     (.data_in(gnt),
	      .data_out(next_state));
	   
	   wire [0:state_width-1] state_s, state_q;
	   assign state_s = update ? next_state : state_q;
	   c_dff
	     #(.width(state_width),
	       .reset_type(reset_type))
	   stateq
	     (.clk(clk),
	      .reset(reset),
	      .active(active),
	      .d(state_s),
	      .q(state_q));
	   
	   wire [0:num_ports-1]   state_therm;
	   c_decode
	     #(.num_ports(num_ports),
	       .therm_enc(1))
	   state_therm_dec
	     (.data_in(state_q),
	      .data_out(state_therm));
	   
	   assign mask = {1'b0, state_therm[0:num_ports-2]};
	   
	end
      else
	begin
	   
	   wire [0:num_ports-2] gnt_shifted;
	   assign gnt_shifted = gnt[1:num_ports-1];
	   
	   wire [0:num_ports-2] next_mask;
	   c_one_hot_therm_conv
	     #(.width(num_ports-1))
	   next_mask_ohtc
	     (.data_in(gnt_shifted),
	      .data_out(next_mask));
	   
	   wire [0:num_ports-2] mask_s, mask_q;
	   assign mask_s = update ? next_mask : mask_q;
	   c_dff
	     #(.width(num_ports-1),
	       .reset_type(reset_type))
	   maskq
	     (.clk(clk),
	      .reset(reset),
	      .active(active),
	      .d(mask_s),
	      .q(mask_q));
	   
	   assign mask = {1'b0, mask_q};
	   
	end
      
      if(num_priorities == 1)
	begin
	   assign gnt_pr = gnt_intm_pr;
	   assign gnt = gnt_intm_pr;
	end
      else if(num_priorities > 1)
	begin
	   
	   wire [0:num_priorities-1] 	any_req_pr;
	   c_reduce_bits
	     #(.num_ports(num_priorities),
	       .width(num_ports),
	       .op(`BINARY_OP_OR))
	   any_req_pr_rb
	     (.data_in(req_pr),
	      .data_out(any_req_pr));
	   
	   wire [0:num_priorities-1] 	any_req_mod_pr;
	   assign any_req_mod_pr = {any_req_pr[0:num_priorities-2], 1'b1};
	   
	   wire [0:num_priorities-1] 	sel_pr;
	   c_lod
	     #(.width(num_priorities))
	   sel_pr_lod
	     (.data_in(any_req_mod_pr),
	      .data_out(sel_pr));
	   
	   c_gate_bits
	     #(.num_ports(num_priorities),
	       .width(num_ports),
	       .op(`BINARY_OP_AND))
	   gnt_pr_gb
	     (.select(sel_pr),
	      .data_in(gnt_intm_pr),
	      .data_out(gnt_pr));
	   
	   c_select_1ofn
	     #(.num_ports(num_priorities),
	       .width(num_ports))
	   gnt_sel
	     (.select(sel_pr),
	      .data_in(gnt_intm_pr),
	      .data_out(gnt));
	   
	end
      
      endgenerate
   
endmodule
module c_rr_arbiter
  (clk, reset, active, req_pr, gnt_pr, gnt, update);

   
`include "c_constants.v"
`include "c_functions.v"
   

   parameter num_ports = 32;
   

   parameter num_priorities = 1;
   

   parameter encode_state = 1;
   

   localparam state_width = clogb(num_ports);
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   input clk;
   input reset;
   input active;
   

   input [0:num_priorities*num_ports-1] req_pr;
   

   output [0:num_priorities*num_ports-1] gnt_pr;
   wire [0:num_priorities*num_ports-1] 	 gnt_pr;
   

   output [0:num_ports-1] 		 gnt;
   wire [0:num_ports-1] 		 gnt;
   

   input 				 update;
   
   wire [0:num_priorities*num_ports-1] 	 gnt_intm_pr;
   
   wire [0:num_ports-1] 		 mask;
   
   genvar 				 prio;
   
   generate
      
      for(prio = 0; prio < num_priorities; prio = prio + 1)
	begin:prios
	   
	   wire [0:num_ports-1] req;
	   assign req = req_pr[prio*num_ports:(prio+1)*num_ports-1];
	   
	   wire [0:num_ports-1] gnt;
	   c_rr_arbiter_base
	     #(.num_ports(num_ports))
	   gnt_ab
	     (.mask(mask),
	      .req(req),
	      .gnt(gnt));
	   
	   assign gnt_intm_pr[prio*num_ports:(prio+1)*num_ports-1] = gnt;
	   
	end
      
      if(encode_state)
	begin
	   
	   wire [0:state_width-1] next_state;
	   c_encode
	     #(.num_ports(num_ports),
	       .offset(1))
	   next_state_enc
	     (.data_in(gnt),
	      .data_out(next_state));
	   
	   wire [0:state_width-1] state_s, state_q;
	   assign state_s = update ? next_state : state_q;
	   c_dff
	     #(.width(state_width),
	       .reset_type(reset_type))
	   stateq
	     (.clk(clk),
	      .reset(reset),
	      .active(active),
	      .d(state_s),
	      .q(state_q));
	   
	   wire [0:num_ports-1]   state_therm;
	   c_decode
	     #(.num_ports(num_ports),
	       .therm_enc(1))
	   state_therm_dec
	     (.data_in(state_q),
	      .data_out(state_therm));
	   
	   assign mask = {1'b0, state_therm[0:num_ports-2]};
	   
	end
      else
	begin
	   
	   wire [0:num_ports-2] gnt_shifted;
	   assign gnt_shifted = gnt[1:num_ports-1];
	   
	   wire [0:num_ports-2] next_mask;
	   c_one_hot_therm_conv
	     #(.width(num_ports-1))
	   next_mask_ohtc
	     (.data_in(gnt_shifted),
	      .data_out(next_mask));
	   
	   wire [0:num_ports-2] mask_s, mask_q;
	   assign mask_s = update ? next_mask : mask_q;
	   c_dff
	     #(.width(num_ports-1),
	       .reset_type(reset_type))
	   maskq
	     (.clk(clk),
	      .reset(reset),
	      .active(active),
	      .d(mask_s),
	      .q(mask_q));
	   
	   assign mask = {1'b0, mask_q};
	   
	end
      
      if(num_priorities == 1)
	begin
	   assign gnt_pr = gnt_intm_pr;
	   assign gnt = gnt_intm_pr;
	end
      else if(num_priorities > 1)
	begin
	   
	   wire [0:num_priorities-1] 	any_req_pr;
	   c_reduce_bits
	     #(.num_ports(num_priorities),
	       .width(num_ports),
	       .op(`BINARY_OP_OR))
	   any_req_pr_rb
	     (.data_in(req_pr),
	      .data_out(any_req_pr));
	   
	   wire [0:num_priorities-1] 	any_req_mod_pr;
	   assign any_req_mod_pr = {any_req_pr[0:num_priorities-2], 1'b1};
	   
	   wire [0:num_priorities-1] 	sel_pr;
	   c_lod
	     #(.width(num_priorities))
	   sel_pr_lod
	     (.data_in(any_req_mod_pr),
	      .data_out(sel_pr));
	   
	   c_gate_bits
	     #(.num_ports(num_priorities),
	       .width(num_ports),
	       .op(`BINARY_OP_AND))
	   gnt_pr_gb
	     (.select(sel_pr),
	      .data_in(gnt_intm_pr),
	      .data_out(gnt_pr));
	   
	   c_select_1ofn
	     #(.num_ports(num_priorities),
	       .width(num_ports))
	   gnt_sel
	     (.select(sel_pr),
	      .data_in(gnt_intm_pr),
	      .data_out(gnt));
	   
	end
      
      endgenerate
   
endmodule