data/full_repos/permissive/419984230/tests/piso_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/419984230/tests/piso_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #90;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/419984230/tests/piso_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #10 en = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/419984230/tests/piso_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/419984230/tests/piso_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #10; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/419984230/tests/piso_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = ~clk;\n        ^\n%Error: data/full_repos/permissive/419984230/tests/piso_tb.v:27: Cannot find file containing module: \'piso\'\n piso uut (\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/419984230/tests,data/full_repos/permissive/419984230/piso\n             data/full_repos/permissive/419984230/tests,data/full_repos/permissive/419984230/piso.v\n             data/full_repos/permissive/419984230/tests,data/full_repos/permissive/419984230/piso.sv\n             piso\n             piso.v\n             piso.sv\n             obj_dir/piso\n             obj_dir/piso.v\n             obj_dir/piso.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module piso_tb;


	reg en;
	reg clk;
	reg [74:0] din;
	reg [74:0] out;
	reg rst;
	integer i;
	integer j;
	reg [74:0] data [13:0];


	wire tFlag;
	wire dout;
	wire [2:0]  row;


	piso uut (
		.en(en), 
		.clk(clk), 
		.din(din), 
		.rst(rst), 
		.tFlag(tFlag), 
		.dout(dout),
		.row(row)
	);
	
	initial begin

		en = 0;
		data [0] = 75'h4204016000000000001;
		data [1] = 75'h0004023000000000000;
		data [2] = 75'h00040234CCCC0000000;
		data [3] = 75'h0003FD06C4C5974E65C;
		data [4] = 75'h00040B41E83DD97F62B;
		data [5] = 75'h000407F48BC6A7EF9DB;
		data [6] = 75'h000407F48BC6A7EF9DB;
		data [7] = 75'h0004048684D129F5D32;
		data [8] = 75'h0003F72611593C60001;
		data [9] = 75'h000C0100FF20BD91970;
		data [10] = 75'h000C0BAD7E6A5048159;
		data [11] = 75'h00040BBC674C4140EF3;
		data [12] = 75'h00040A69E94DB886091;
		data [13] = 75'h000C07D46072866091F;
		clk = 0;
		din = 0;
		rst = 1;


		#90;
		rst = 0;
		#10 en = 1;
		for (j=0; j<=13; j=j+1) begin
            din = data [j];
			for (i=74; i>=0; i=i-1) begin
				#10;
			end
		end
		#10; 
		$finish();
	end

	always #5 clk = ~clk;
	always @(posedge clk) begin
		out = {out[73:0], dout};
		if(tFlag)
			$display("OUT: %h", out);
	end
      
endmodule
module piso_tb;



	reg en;
	reg clk;
	reg [74:0] din;
	reg [74:0] out;
	reg rst;
	integer i;
	integer j;
	reg [74:0] data [13:0];


	wire tFlag;
	wire dout;
	wire [2:0]  row;


	piso uut (
		.en(en), 
		.clk(clk), 
		.din(din), 
		.rst(rst), 
		.tFlag(tFlag), 
		.dout(dout),
		.row(row)
	);
	
	initial begin

		en = 0;
		data [0] = 75'h4204016000000000001;
		data [1] = 75'h0004023000000000000;
		data [2] = 75'h00040234CCCC0000000;
		data [3] = 75'h0003FD06C4C5974E65C;
		data [4] = 75'h00040B41E83DD97F62B;
		data [5] = 75'h000407F48BC6A7EF9DB;
		data [6] = 75'h000407F48BC6A7EF9DB;
		data [7] = 75'h0004048684D129F5D32;
		data [8] = 75'h0003F72611593C60001;
		data [9] = 75'h000C0100FF20BD91970;
		data [10] = 75'h000C0BAD7E6A5048159;
		data [11] = 75'h00040BBC674C4140EF3;
		data [12] = 75'h00040A69E94DB886091;
		data [13] = 75'h000C07D46072866091F;
		clk = 0;
		din = 0;
		rst = 1;


		#90;
		rst = 0;
		#10 en = 1;
		for (j=0; j<=13; j=j+1) begin
            din = data [j];
			for (i=74; i>=0; i=i-1) begin
				#10;
			end
		end
		#10; 
		$finish();
	end

	always #5 clk = ~clk;
	always @(posedge clk) begin
		out = {out[73:0], dout};
		if(tFlag)
			$display("OUT: %h", out);
	end
      
endmodule