data/full_repos/permissive/523038000/lab10/data_mem.v
data/verilator_xmls/42481740-7eb9-409b-ac80-d9c106cc438f.xml
module data_memory ( data_out , address,data_in ,wr,clk ) ;
output [31:0] data_out;
input [31:0] data_in;
input [3:0] address;
input wr,clk;

reg [31:0] data_mem [15:0];

assign data_out=data_mem[address];

always @ (posedge clk )
if (wr==1)
data_mem[address]=data_in;

endmodule
module data_memory ( data_out , address,data_in ,wr,clk ) ;

output [31:0] data_out;
input [31:0] data_in;
input [3:0] address;
input wr,clk;

reg [31:0] data_mem [15:0];

assign data_out=data_mem[address];

always @ (posedge clk )
if (wr==1)
data_mem[address]=data_in;

endmodule