data/full_repos/permissive/43858668/final_verilog/src/clib/c_add_nto1.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_add_nto1.v:35: Cannot find include file: c_functions.v\n`include "c_functions.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v.sv\n             c_functions.v\n             c_functions.v.v\n             c_functions.v.sv\n             obj_dir/c_functions.v\n             obj_dir/c_functions.v.v\n             obj_dir/c_functions.v.sv\n%Error: Exiting due to 1 error(s)\n'
module c_add_nto1
  (data_in, data_out);
   
`include "c_functions.v"
   

   parameter width = 1;
   

   parameter num_ports = 2;
   

   localparam out_width = clogb(num_ports * (1 << width - 1) + 1);
   

   input [0:width*num_ports-1] data_in;
   

   output [0:out_width-1] data_out;
   reg [0:out_width-1] data_out;
   
   integer 	       i;
   
   always @(data_in)
     begin
	data_out = {out_width{1'b0}};
	for(i = 0; i < num_ports; i = i + 1)
	  begin
	     data_out = data_out + data_in[i*width +: width];
	  end
     end
   
endmodule
module c_add_nto1
  (data_in, data_out);

   
`include "c_functions.v"
   

   parameter width = 1;
   

   parameter num_ports = 2;
   

   localparam out_width = clogb(num_ports * (1 << width - 1) + 1);
   

   input [0:width*num_ports-1] data_in;
   

   output [0:out_width-1] data_out;
   reg [0:out_width-1] data_out;
   
   integer 	       i;
   
   always @(data_in)
     begin
	data_out = {out_width{1'b0}};
	for(i = 0; i < num_ports; i = i + 1)
	  begin
	     data_out = data_out + data_in[i*width +: width];
	  end
     end
   
endmodule