data/full_repos/permissive/406635962/src/rtl/core.v
1: b'%Error: data/full_repos/permissive/406635962/src/rtl/core.v:6: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/406635962/src/rtl/core.v:9: Define or directive not defined: \'`PC_SIZE\'\n    input [`PC_SIZE-1:0] pc_rtvec,     \n           ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/core.v:13: Define or directive not defined: \'`ITCM_ADDR_WIDTH\'\n    output [`ITCM_ADDR_WIDTH-1:0] ifu2itcm_cmd_addr,\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/core.v:17: Define or directive not defined: \'`ITCM_RAM_DW\'\n    input [`ITCM_RAM_DW-1:0] ifu2itcm_rsp_rdata,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/core.v:23: Define or directive not defined: \'`DTCM_ADDR_WIDTH\'\n    output [`DTCM_ADDR_WIDTH-1:0] lsu2dtcm_cmd_addr,\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/core.v:24: Define or directive not defined: \'`XLEN\'\n    output [`XLEN-1:0] lsu2dtcm_cmd_wdata,\n            ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/core.v:25: Define or directive not defined: \'`XLEN\'\n    output [`XLEN/8-1:0] lsu2dtcm_cmd_wmask,\n            ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/core.v:25: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n    output [`XLEN/8-1:0] lsu2dtcm_cmd_wmask,\n                 ^\n%Error: data/full_repos/permissive/406635962/src/rtl/core.v:28: Define or directive not defined: \'`XLEN\'\n    input [`XLEN-1:0] lsu2dtcm_rsp_rdata,\n           ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/core.v:36: Define or directive not defined: \'`INSTR_SIZE\'\nwire [`INSTR_SIZE-1:0] ifu_o_ir;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/core.v:37: Define or directive not defined: \'`PC_SIZE\'\nwire [`PC_SIZE-1:0] ifu_o_pc;\n      ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/core.v:38: Define or directive not defined: \'`RFIDX_WIDTH\'\nwire [`RFIDX_WIDTH-1:0]ifu_o_rs1idx;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/core.v:39: Define or directive not defined: \'`RFIDX_WIDTH\'\nwire [`RFIDX_WIDTH-1:0]ifu_o_rs2idx;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/core.v:47: Define or directive not defined: \'`XLEN\'\nwire [`XLEN-1:0] pipe_flush_add_op1;\n      ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/core.v:48: Define or directive not defined: \'`XLEN\'\nwire [`XLEN-1:0] pipe_flush_add_op2;\n      ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/core.v:49: Define or directive not defined: \'`XLEN\'\nwire [`XLEN-1:0] rf2ifu_x1;\n      ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/core.v:50: Define or directive not defined: \'`XLEN\'\nwire [`XLEN-1:0] rf2ifu_rs1;\n      ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/core.v:53: Define or directive not defined: \'`RFIDX_WIDTH\'\nwire [`RFIDX_WIDTH-1:0] dec2ifu_rdidx;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/core.v:55: syntax error, unexpected IDENTIFIER\nifu u_ifu (\n^~~\n%Error: data/full_repos/permissive/406635962/src/rtl/core.v:96: Define or directive not defined: \'`DTCM_ADDR_WIDTH\'\nwire [`DTCM_ADDR_WIDTH-1:0] agu_cmd_addr;\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/core.v:97: Define or directive not defined: \'`ITAG_WIDTH\'\nwire [`ITAG_WIDTH-1:0] agu_cmd_itag;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/core.v:98: Define or directive not defined: \'`XLEN\'\nwire [`XLEN-1:0] agu_cmd_wdata;\n      ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/core.v:99: Define or directive not defined: \'`XLEN\'\nwire [`XLEN/8-1:0] agu_cmd_wmask;\n      ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/core.v:99: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\nwire [`XLEN/8-1:0] agu_cmd_wmask;\n           ^\n%Error: data/full_repos/permissive/406635962/src/rtl/core.v:103: Define or directive not defined: \'`XLEN\'\nwire [`XLEN-1:0] lsu_o_wbck_data;\n      ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/core.v:104: Define or directive not defined: \'`ITAG_WIDTH\'\nwire [`ITAG_WIDTH-1:0] lsu_o_wbck_itag;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/core.v:108: syntax error, unexpected IDENTIFIER\nexu u_exu (\n^~~\n%Error: Exiting due to 27 error(s)\n'
module core (
    input [`PC_SIZE-1:0] pc_rtvec,

    output ifu2itcm_cmd_valid,    
    input ifu2itcm_cmd_ready,
    output [`ITCM_ADDR_WIDTH-1:0] ifu2itcm_cmd_addr,

    input ifu2itcm_rsp_valid,
    output ifu2itcm_rsp_ready,
    input [`ITCM_RAM_DW-1:0] ifu2itcm_rsp_rdata,


    output lsu2dtcm_cmd_valid,
    input lsu2dtcm_cmd_ready,
    output lsu2dtcm_cmd_read,
    output [`DTCM_ADDR_WIDTH-1:0] lsu2dtcm_cmd_addr,
    output [`XLEN-1:0] lsu2dtcm_cmd_wdata,
    output [`XLEN/8-1:0] lsu2dtcm_cmd_wmask,
    input lsu2dtcm_rsp_valid,
    output lsu2dtcm_rsp_ready,
    input [`XLEN-1:0] lsu2dtcm_rsp_rdata,

    input clk,
    input rst_n
);


wire ifu_exu_valid;
wire [`INSTR_SIZE-1:0] ifu_o_ir;
wire [`PC_SIZE-1:0] ifu_o_pc;
wire [`RFIDX_WIDTH-1:0]ifu_o_rs1idx;
wire [`RFIDX_WIDTH-1:0]ifu_o_rs2idx;
wire ifu_o_prdt_taken;
wire ifu_exu_ready;

wire oitf_empty;

wire pipe_flush_ack;
wire pipe_flush_req;
wire [`XLEN-1:0] pipe_flush_add_op1;
wire [`XLEN-1:0] pipe_flush_add_op2;
wire [`XLEN-1:0] rf2ifu_x1;
wire [`XLEN-1:0] rf2ifu_rs1;
wire dec2ifu_rden;
wire dec2ifu_rs1en;
wire [`RFIDX_WIDTH-1:0] dec2ifu_rdidx;

ifu u_ifu (
    .pc_rtvec(pc_rtvec),
    .ifu_o_ir(ifu_o_ir),
    .ifu_o_pc(ifu_o_pc),
    .ifu_o_rs1idx(ifu_o_rs1idx),
    .ifu_o_rs2idx(ifu_o_rs2idx),
    .ifu_o_prdt_taken(ifu_o_prdt_taken),
    .ifu_o_valid(ifu_exu_valid),
    .ifu_o_ready(ifu_exu_ready),
    .pipe_flush_ack(pipe_flush_ack),
    .pipe_flush_req(pipe_flush_req),
    .pipe_flush_add_op1(pipe_flush_add_op1),
    .pipe_flush_add_op2(pipe_flush_add_op2),

    .ifu2itcm_cmd_valid(ifu2itcm_cmd_valid),
    .ifu2itcm_cmd_ready(ifu2itcm_cmd_ready),
    .ifu2itcm_cmd_addr(ifu2itcm_cmd_addr),
    .ifu2itcm_rsp_valid(ifu2itcm_rsp_valid),
    .ifu2itcm_rsp_ready(ifu2itcm_rsp_ready),
    .ifu2itcm_rsp_rdata(ifu2itcm_rsp_rdata),

    .oitf_empty(oitf_empty),
    .rf2ifu_x1(rf2ifu_x1),
    .rf2ifu_rs1(rf2ifu_rs1),
    .dec2ifu_rden(dec2ifu_rden),
    .dec2ifu_rs1en(dec2ifu_rs1en),
    .dec2ifu_rdidx(dec2ifu_rdidx),
    .clk(clk),
    .rst_n(rst_n)
);



wire agu_cmd_ready;
wire agu_cmd_usign;
wire agu_cmd_valid;
wire agu_cmd_read;
wire agu_rsp_valid;
wire agu_rsp_ready;
wire [1:0] agu_cmd_size;

wire [`DTCM_ADDR_WIDTH-1:0] agu_cmd_addr;
wire [`ITAG_WIDTH-1:0] agu_cmd_itag;
wire [`XLEN-1:0] agu_cmd_wdata;
wire [`XLEN/8-1:0] agu_cmd_wmask;

wire lsu_o_valid;
wire lsu_o_ready;
wire [`XLEN-1:0] lsu_o_wbck_data;
wire [`ITAG_WIDTH-1:0] lsu_o_wbck_itag;



exu u_exu (
    .i_valid(ifu_exu_valid),
    .i_ready(ifu_exu_ready),
    .i_ir(ifu_o_ir),
    .i_pc(ifu_o_pc),
    .i_prdt_taken(ifu_o_prdt_taken),
    .i_rs1idx(ifu_o_rs1idx),
    .i_rs2idx(ifu_o_rs2idx),
    .pipe_flush_ack(pipe_flush_ack),
    .pipe_flush_req(pipe_flush_req),
    .pipe_flush_add_op1(pipe_flush_add_op1),
    .pipe_flush_add_op2(pipe_flush_add_op2),

    .lsu_wbck_i_valid(lsu_o_valid),
    .lsu_wbck_i_ready(lsu_o_ready),
    .lsu_wbck_i_data(lsu_o_wbck_data),
    .lsu_wbck_i_itag(lsu_o_wbck_itag),

    .oitf_empty(oitf_empty),
    .rf2ifu_x1(rf2ifu_x1),
    .rf2ifu_rs1(rf2ifu_rs1),
    .dec2ifu_rden(dec2ifu_rden),
    .dec2ifu_rs1en(dec2ifu_rs1en),
    .dec2ifu_rdidx(dec2ifu_rdidx),

    .agu_cmd_valid(agu_cmd_valid),
    .agu_cmd_ready(agu_cmd_ready),
    .agu_cmd_addr(agu_cmd_addr),
    .agu_cmd_read(agu_cmd_read),
    .agu_cmd_itag(agu_cmd_itag),
     .agu_cmd_usign(agu_cmd_usign),
    .agu_cmd_size(agu_cmd_size),
    .agu_cmd_wdata(agu_cmd_wdata),
    .agu_cmd_wmask(agu_cmd_wmask),
    .agu_rsp_valid(agu_rsp_valid),
    .agu_rsp_ready(agu_rsp_ready),
    .clk(clk),
    .rst_n(rst_n)
);


lsu u_lsu (
    .lsu_o_valid(lsu_o_valid),
    .lsu_o_ready(lsu_o_ready),
    .lsu_o_wbck_data(lsu_o_wbck_data),
    .lsu_o_wbck_itag(lsu_o_wbck_itag),

    .agu_cmd_valid(agu_cmd_valid),
    .agu_cmd_ready(agu_cmd_ready),
    .agu_cmd_read(agu_cmd_read),
    .agu_cmd_addr(agu_cmd_addr),
    .agu_cmd_wdata(agu_cmd_wdata),
    .agu_cmd_wmask(agu_cmd_wmask),
    .agu_cmd_itag(agu_cmd_itag),
    .agu_cmd_usign(agu_cmd_usign),
    .agu_cmd_size(agu_cmd_size),
    .agu_rsp_valid(agu_rsp_valid),
    .agu_rsp_ready(agu_rsp_ready),

    .dtcm_cmd_valid(lsu2dtcm_cmd_valid),
    .dtcm_cmd_ready(lsu2dtcm_cmd_ready),
    .dtcm_cmd_read(lsu2dtcm_cmd_read),
    .dtcm_cmd_addr(lsu2dtcm_cmd_addr),
    .dtcm_cmd_wdata(lsu2dtcm_cmd_wdata),
    .dtcm_cmd_wmask(lsu2dtcm_cmd_wmask),
    .dtcm_rsp_valid(lsu2dtcm_rsp_valid),
    .dtcm_rsp_ready(lsu2dtcm_rsp_ready),
    .dtcm_rsp_rdata(lsu2dtcm_rsp_rdata),
    .clk(clk),
    .rst_n(rst_n)
);
endmodule
module core (
    input [`PC_SIZE-1:0] pc_rtvec,

    output ifu2itcm_cmd_valid,    
    input ifu2itcm_cmd_ready,
    output [`ITCM_ADDR_WIDTH-1:0] ifu2itcm_cmd_addr,

    input ifu2itcm_rsp_valid,
    output ifu2itcm_rsp_ready,
    input [`ITCM_RAM_DW-1:0] ifu2itcm_rsp_rdata,


    output lsu2dtcm_cmd_valid,
    input lsu2dtcm_cmd_ready,
    output lsu2dtcm_cmd_read,
    output [`DTCM_ADDR_WIDTH-1:0] lsu2dtcm_cmd_addr,
    output [`XLEN-1:0] lsu2dtcm_cmd_wdata,
    output [`XLEN/8-1:0] lsu2dtcm_cmd_wmask,
    input lsu2dtcm_rsp_valid,
    output lsu2dtcm_rsp_ready,
    input [`XLEN-1:0] lsu2dtcm_rsp_rdata,

    input clk,
    input rst_n
);



wire ifu_exu_valid;
wire [`INSTR_SIZE-1:0] ifu_o_ir;
wire [`PC_SIZE-1:0] ifu_o_pc;
wire [`RFIDX_WIDTH-1:0]ifu_o_rs1idx;
wire [`RFIDX_WIDTH-1:0]ifu_o_rs2idx;
wire ifu_o_prdt_taken;
wire ifu_exu_ready;

wire oitf_empty;

wire pipe_flush_ack;
wire pipe_flush_req;
wire [`XLEN-1:0] pipe_flush_add_op1;
wire [`XLEN-1:0] pipe_flush_add_op2;
wire [`XLEN-1:0] rf2ifu_x1;
wire [`XLEN-1:0] rf2ifu_rs1;
wire dec2ifu_rden;
wire dec2ifu_rs1en;
wire [`RFIDX_WIDTH-1:0] dec2ifu_rdidx;

ifu u_ifu (
    .pc_rtvec(pc_rtvec),
    .ifu_o_ir(ifu_o_ir),
    .ifu_o_pc(ifu_o_pc),
    .ifu_o_rs1idx(ifu_o_rs1idx),
    .ifu_o_rs2idx(ifu_o_rs2idx),
    .ifu_o_prdt_taken(ifu_o_prdt_taken),
    .ifu_o_valid(ifu_exu_valid),
    .ifu_o_ready(ifu_exu_ready),
    .pipe_flush_ack(pipe_flush_ack),
    .pipe_flush_req(pipe_flush_req),
    .pipe_flush_add_op1(pipe_flush_add_op1),
    .pipe_flush_add_op2(pipe_flush_add_op2),

    .ifu2itcm_cmd_valid(ifu2itcm_cmd_valid),
    .ifu2itcm_cmd_ready(ifu2itcm_cmd_ready),
    .ifu2itcm_cmd_addr(ifu2itcm_cmd_addr),
    .ifu2itcm_rsp_valid(ifu2itcm_rsp_valid),
    .ifu2itcm_rsp_ready(ifu2itcm_rsp_ready),
    .ifu2itcm_rsp_rdata(ifu2itcm_rsp_rdata),

    .oitf_empty(oitf_empty),
    .rf2ifu_x1(rf2ifu_x1),
    .rf2ifu_rs1(rf2ifu_rs1),
    .dec2ifu_rden(dec2ifu_rden),
    .dec2ifu_rs1en(dec2ifu_rs1en),
    .dec2ifu_rdidx(dec2ifu_rdidx),
    .clk(clk),
    .rst_n(rst_n)
);



wire agu_cmd_ready;
wire agu_cmd_usign;
wire agu_cmd_valid;
wire agu_cmd_read;
wire agu_rsp_valid;
wire agu_rsp_ready;
wire [1:0] agu_cmd_size;

wire [`DTCM_ADDR_WIDTH-1:0] agu_cmd_addr;
wire [`ITAG_WIDTH-1:0] agu_cmd_itag;
wire [`XLEN-1:0] agu_cmd_wdata;
wire [`XLEN/8-1:0] agu_cmd_wmask;

wire lsu_o_valid;
wire lsu_o_ready;
wire [`XLEN-1:0] lsu_o_wbck_data;
wire [`ITAG_WIDTH-1:0] lsu_o_wbck_itag;



exu u_exu (
    .i_valid(ifu_exu_valid),
    .i_ready(ifu_exu_ready),
    .i_ir(ifu_o_ir),
    .i_pc(ifu_o_pc),
    .i_prdt_taken(ifu_o_prdt_taken),
    .i_rs1idx(ifu_o_rs1idx),
    .i_rs2idx(ifu_o_rs2idx),
    .pipe_flush_ack(pipe_flush_ack),
    .pipe_flush_req(pipe_flush_req),
    .pipe_flush_add_op1(pipe_flush_add_op1),
    .pipe_flush_add_op2(pipe_flush_add_op2),

    .lsu_wbck_i_valid(lsu_o_valid),
    .lsu_wbck_i_ready(lsu_o_ready),
    .lsu_wbck_i_data(lsu_o_wbck_data),
    .lsu_wbck_i_itag(lsu_o_wbck_itag),

    .oitf_empty(oitf_empty),
    .rf2ifu_x1(rf2ifu_x1),
    .rf2ifu_rs1(rf2ifu_rs1),
    .dec2ifu_rden(dec2ifu_rden),
    .dec2ifu_rs1en(dec2ifu_rs1en),
    .dec2ifu_rdidx(dec2ifu_rdidx),

    .agu_cmd_valid(agu_cmd_valid),
    .agu_cmd_ready(agu_cmd_ready),
    .agu_cmd_addr(agu_cmd_addr),
    .agu_cmd_read(agu_cmd_read),
    .agu_cmd_itag(agu_cmd_itag),
     .agu_cmd_usign(agu_cmd_usign),
    .agu_cmd_size(agu_cmd_size),
    .agu_cmd_wdata(agu_cmd_wdata),
    .agu_cmd_wmask(agu_cmd_wmask),
    .agu_rsp_valid(agu_rsp_valid),
    .agu_rsp_ready(agu_rsp_ready),
    .clk(clk),
    .rst_n(rst_n)
);


lsu u_lsu (
    .lsu_o_valid(lsu_o_valid),
    .lsu_o_ready(lsu_o_ready),
    .lsu_o_wbck_data(lsu_o_wbck_data),
    .lsu_o_wbck_itag(lsu_o_wbck_itag),

    .agu_cmd_valid(agu_cmd_valid),
    .agu_cmd_ready(agu_cmd_ready),
    .agu_cmd_read(agu_cmd_read),
    .agu_cmd_addr(agu_cmd_addr),
    .agu_cmd_wdata(agu_cmd_wdata),
    .agu_cmd_wmask(agu_cmd_wmask),
    .agu_cmd_itag(agu_cmd_itag),
    .agu_cmd_usign(agu_cmd_usign),
    .agu_cmd_size(agu_cmd_size),
    .agu_rsp_valid(agu_rsp_valid),
    .agu_rsp_ready(agu_rsp_ready),

    .dtcm_cmd_valid(lsu2dtcm_cmd_valid),
    .dtcm_cmd_ready(lsu2dtcm_cmd_ready),
    .dtcm_cmd_read(lsu2dtcm_cmd_read),
    .dtcm_cmd_addr(lsu2dtcm_cmd_addr),
    .dtcm_cmd_wdata(lsu2dtcm_cmd_wdata),
    .dtcm_cmd_wmask(lsu2dtcm_cmd_wmask),
    .dtcm_rsp_valid(lsu2dtcm_rsp_valid),
    .dtcm_rsp_ready(lsu2dtcm_rsp_ready),
    .dtcm_rsp_rdata(lsu2dtcm_rsp_rdata),
    .clk(clk),
    .rst_n(rst_n)
);
endmodule