data/full_repos/permissive/493019833/test/testcase/firrtl/MultiClockSpecanonfun22anonfunapplymcVsp12anon5/reference/MultiClockSpecanonfun22anonfunapplymcVsp12anon5.v
data/verilator_xmls/9272881c-134c-485f-9a70-d6ede1ec1a41.xml
module DFF_POSCLK(q, d, clk);
    parameter width = 4;
    output reg [width-1:0] q;
    input [width-1:0] d;
    input clk;
    always @(posedge clk) begin
        q <= d;
    end
endmodule
module DFF_POSCLK(q, d, clk);

    parameter width = 4;
    output reg [width-1:0] q;
    input [width-1:0] d;
    input clk;
    always @(posedge clk) begin
        q <= d;
    end
endmodule