data/full_repos/permissive/445357518/alu.v
data/verilator_xmls/8a445699-a7bd-409a-ac79-fd4d429ecbf0.xml
module ALU(Ain,Bin,ALUop,out,N,V,Z);
input [15:0] Ain, Bin;
input [1:0] ALUop;
output [15:0] out;
output N,V,Z;
wire c1,c2;
reg [15:0] out;
reg V;

assign Z = (out==16'd0) ? 1:0;
assign N =  (out[15]==1'b1) ? 1:0;
always @* begin
    V=1'b0;
   
  case(ALUop)
    2'b00: out= Ain+Bin;
    2'b01: out= Ain-Bin;
    2'b10: out= Ain&Bin;
    2'b11: out= ~Bin;
   default:out={16{1'bx}};
   endcase


   if(ALUop==2'b01) begin
     
       if(Ain[15]== ~Bin[15] & out[7]!==Ain[7]) begin
             V=1'b1;
          end

   end
end



endmodule
module ALU(Ain,Bin,ALUop,out,N,V,Z);

input [15:0] Ain, Bin;
input [1:0] ALUop;
output [15:0] out;
output N,V,Z;
wire c1,c2;
reg [15:0] out;
reg V;

assign Z = (out==16'd0) ? 1:0;
assign N =  (out[15]==1'b1) ? 1:0;
always @* begin
    V=1'b0;
   
  case(ALUop)
    2'b00: out= Ain+Bin;
    2'b01: out= Ain-Bin;
    2'b10: out= Ain&Bin;
    2'b11: out= ~Bin;
   default:out={16{1'bx}};
   endcase


   if(ALUop==2'b01) begin
     
       if(Ain[15]== ~Bin[15] & out[7]!==Ain[7]) begin
             V=1'b1;
          end

   end
end



endmodule