data/full_repos/permissive/486588912/verilog/ifetch.v
1: b"%Error: data/full_repos/permissive/486588912/verilog/ifetch.v:39: Cannot find file containing module: 'l1icache'\n    l1icache il1(\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/486588912/verilog,data/full_repos/permissive/486588912/l1icache\n             data/full_repos/permissive/486588912/verilog,data/full_repos/permissive/486588912/l1icache.v\n             data/full_repos/permissive/486588912/verilog,data/full_repos/permissive/486588912/l1icache.sv\n             l1icache\n             l1icache.v\n             l1icache.sv\n             obj_dir/l1icache\n             obj_dir/l1icache.v\n             obj_dir/l1icache.sv\n%Error: Exiting due to 1 error(s)\n"
module ifetch(
    input sys_clk,
    input rst_n,


    input do_jump,
    input [31:0] jump_addr,


    input stall,
    output global_stall,

    input fetch_bubble,

    output [31:0] ins_out,
    output reg [31:0] pc_out,
    output reg [31:0] next_pc_out,


    output immu_read,
    output [31:0] immu_addr,

    input immu_done,
    input [255:0] immu_read_data,

    input is_sync_ins
);
    reg [31:0] pc;
    reg [31:0] next_pc;
    reg working;
    wire [31:0] il1_ins_out;
    wire il1_stall;
    wire i1l_inv_stall;

    wire [4:0] sync_type = ins_out[10:6];

    l1icache il1(
        .sys_clk(sys_clk),
        .rst_n(rst_n),

        .l1_read(working),
        .l1_addr(pc),

        .l1_data_o(il1_ins_out),
        .out_req_stall(stall),
        .miss_stall(il1_stall),
        .invalid_stall(i1l_inv_stall),
        .out_bubble(fetch_bubble),

        .l1_mmu_req_read(immu_read),
        .l1_mmu_req_addr(immu_addr),

        .mmu_l1_done(immu_done),
        .mmu_l1_read_data(immu_read_data),

        .is_sync_ins(is_sync_ins),
        .sync_type(sync_type)
    );
    reg il1_algn;
    always @(posedge sys_clk) il1_algn <= il1_stall;
    assign ins_out = il1_algn ? 32'b0 : il1_ins_out;

    wire pos_stall = stall || i1l_inv_stall;
    reg out_stall_algn;
    always @(posedge sys_clk) out_stall_algn <= pos_stall;

    assign global_stall = il1_algn || pos_stall;
    
    always @(posedge sys_clk) begin
        if (!rst_n) begin

            pc_out <= 0;
            next_pc_out <= 0;
            working <= 0;
        end else begin

            pc_out <= pc;
            next_pc_out <= next_pc;
            working <= 1;
        end
    end

    always @* begin
        if (!rst_n) begin
            next_pc = 32'b0;
        end else begin
            next_pc = pc + 4;
        end
    end

    always @(negedge sys_clk) begin
        if (!rst_n) begin
            pc <= 32'hFFFFE000;
        end else begin
            if (pc == 32'h00008000) begin
                pc <= 32'HFFFFE000;
            end else begin
                if (global_stall || il1_stall || fetch_bubble) 
                    pc <= pc;
                else if (do_jump) 
                    pc <= jump_addr;
                else
                    pc <= next_pc;
            end
        end
    end


endmodule
module ifetch(
    input sys_clk,
    input rst_n,


    input do_jump,
    input [31:0] jump_addr,


    input stall,
    output global_stall,

    input fetch_bubble,

    output [31:0] ins_out,
    output reg [31:0] pc_out,
    output reg [31:0] next_pc_out,


    output immu_read,
    output [31:0] immu_addr,

    input immu_done,
    input [255:0] immu_read_data,

    input is_sync_ins
);

    reg [31:0] pc;
    reg [31:0] next_pc;
    reg working;
    wire [31:0] il1_ins_out;
    wire il1_stall;
    wire i1l_inv_stall;

    wire [4:0] sync_type = ins_out[10:6];

    l1icache il1(
        .sys_clk(sys_clk),
        .rst_n(rst_n),

        .l1_read(working),
        .l1_addr(pc),

        .l1_data_o(il1_ins_out),
        .out_req_stall(stall),
        .miss_stall(il1_stall),
        .invalid_stall(i1l_inv_stall),
        .out_bubble(fetch_bubble),

        .l1_mmu_req_read(immu_read),
        .l1_mmu_req_addr(immu_addr),

        .mmu_l1_done(immu_done),
        .mmu_l1_read_data(immu_read_data),

        .is_sync_ins(is_sync_ins),
        .sync_type(sync_type)
    );
    reg il1_algn;
    always @(posedge sys_clk) il1_algn <= il1_stall;
    assign ins_out = il1_algn ? 32'b0 : il1_ins_out;

    wire pos_stall = stall || i1l_inv_stall;
    reg out_stall_algn;
    always @(posedge sys_clk) out_stall_algn <= pos_stall;

    assign global_stall = il1_algn || pos_stall;
    
    always @(posedge sys_clk) begin
        if (!rst_n) begin

            pc_out <= 0;
            next_pc_out <= 0;
            working <= 0;
        end else begin

            pc_out <= pc;
            next_pc_out <= next_pc;
            working <= 1;
        end
    end

    always @* begin
        if (!rst_n) begin
            next_pc = 32'b0;
        end else begin
            next_pc = pc + 4;
        end
    end

    always @(negedge sys_clk) begin
        if (!rst_n) begin
            pc <= 32'hFFFFE000;
        end else begin
            if (pc == 32'h00008000) begin
                pc <= 32'HFFFFE000;
            end else begin
                if (global_stall || il1_stall || fetch_bubble) 
                    pc <= pc;
                else if (do_jump) 
                    pc <= jump_addr;
                else
                    pc <= next_pc;
            end
        end
    end


endmodule