data/full_repos/permissive/493019833/test/testcase/firrtl/ReadwriterTester1/reference/ReadwriterTester1.v
data/verilator_xmls/3c94b868-81da-44b2-a2c5-c1d87bbc25fb.xml
module ReadwriterTester1(
    input clock,
    input [4:0] waddr,
    input [31:0] wdata,
    input rw_wen,
    output [31:0] rw_rdata
);
    wire [31:0] m_rw_rdata;
    wire m_rw_wmode;
    wire m_rw_clk;
    wire m_rw_en;
    wire m_rw_wmask;
    wire [4:0] m_rw_addr;
    wire [31:0] m_rw_wdata;
    wire _WTEMP_0;
    BITWISENOT #(.width(1)) bitwisenot_1 (
        .y(_WTEMP_0),
        .in(m_rw_wmode)
    );
    RAMMEM #(.depth(32), .addrbits(5), .width(32), .isSyncRead(0)) m (
        .read_data(m_rw_rdata),
        .read_clk(m_rw_clk),
        .read_en(_WTEMP_0),
        .read_addr(m_rw_addr),
        .write_clk(m_rw_clk),
        .write_en(m_rw_wmode),
        .write_mask(m_rw_wmask),
        .write_addr(m_rw_addr),
        .write_data(m_rw_wdata)
    );
    assign m_rw_addr = waddr;
    assign m_rw_clk = clock;
    assign m_rw_en = 1'h1;
    assign m_rw_wdata = wdata;
    assign m_rw_wmask = 1'h1;
    assign m_rw_wmode = rw_wen;
    assign rw_rdata = m_rw_rdata;
endmodule
module ReadwriterTester1(
    input clock,
    input [4:0] waddr,
    input [31:0] wdata,
    input rw_wen,
    output [31:0] rw_rdata
);

    wire [31:0] m_rw_rdata;
    wire m_rw_wmode;
    wire m_rw_clk;
    wire m_rw_en;
    wire m_rw_wmask;
    wire [4:0] m_rw_addr;
    wire [31:0] m_rw_wdata;
    wire _WTEMP_0;
    BITWISENOT #(.width(1)) bitwisenot_1 (
        .y(_WTEMP_0),
        .in(m_rw_wmode)
    );
    RAMMEM #(.depth(32), .addrbits(5), .width(32), .isSyncRead(0)) m (
        .read_data(m_rw_rdata),
        .read_clk(m_rw_clk),
        .read_en(_WTEMP_0),
        .read_addr(m_rw_addr),
        .write_clk(m_rw_clk),
        .write_en(m_rw_wmode),
        .write_mask(m_rw_wmask),
        .write_addr(m_rw_addr),
        .write_data(m_rw_wdata)
    );
    assign m_rw_addr = waddr;
    assign m_rw_clk = clock;
    assign m_rw_en = 1'h1;
    assign m_rw_wdata = wdata;
    assign m_rw_wmask = 1'h1;
    assign m_rw_wmode = rw_wen;
    assign rw_rdata = m_rw_rdata;
endmodule