data/full_repos/permissive/42434302/ivltests/pr3527694.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr3527694.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr3527694.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr3527694.v:25: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Error: data/full_repos/permissive/42434302/ivltests/pr3527694.v:26: Unsupported or unknown PLI call: $dumpflush\n $dumpflush;\n ^~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr3527694.v:84: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Error: data/full_repos/permissive/42434302/ivltests/pr3527694.v:140: Unsupported or unknown PLI call: $strobe\n $strobe("%m wide: %h, width1:%h, width2:%h", wide, width1, width2);\n ^~~~~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test1
#(
parameter WIDTH1 = 1,
parameter WIDTH2 = 2
) (
input sys_clk,
input sys_rst
);

wire [15:0] w1 = WIDTH1;
wire [15:0] w2 = WIDTH2;

generate
if(WIDTH1 != 1) begin: not1

test2 #(
	.WIDTH1(18),
	.WIDTH2(18)
) test2_0 (
	.sys_clk(sys_clk),
	.sys_rst(sys_rst)
);

test2 #(
	.WIDTH1(18),
	.WIDTH2(18)
) test2_1 (
	.sys_clk(sys_clk),
	.sys_rst(sys_rst)
);

end
endgenerate

initial begin
	#40;
	$finish;
end

endmodule
module test1
#(
parameter WIDTH1 = 1,
parameter WIDTH2 = 2
) (
input sys_clk,
input sys_rst
);


wire [15:0] w1 = WIDTH1;
wire [15:0] w2 = WIDTH2;

generate
if(WIDTH1 != 1) begin: not1

test2 #(
	.WIDTH1(18),
	.WIDTH2(18)
) test2_0 (
	.sys_clk(sys_clk),
	.sys_rst(sys_rst)
);

test2 #(
	.WIDTH1(18),
	.WIDTH2(18)
) test2_1 (
	.sys_clk(sys_clk),
	.sys_rst(sys_rst)
);

end
endgenerate

initial begin
	#40;
	$finish;
end

endmodule