data/full_repos/permissive/501470173/verilog/rtl/LIFO.v
data/verilator_xmls/a8f001c6-0743-4b45-a90c-52b30664b5e2.xml
module LIFO(
    input clk,
	 input rst,
    input wr_en,
    input rd_en,
    input [10:0] din,
    output [10:0] dout
    );



   reg [3:0] addr;
   reg [10:0] ram [15:0];

   always@(posedge clk)
		if (rst)
			addr<=0;
		else 
			 begin 
			  if (wr_en==0 && rd_en==1)
					if (addr>0)
						addr<=addr-1;
			  if (wr_en==1 && rd_en==0)
					if (addr<15)
						addr<=addr+1;
			 end
		
	always @(posedge clk)
      if (wr_en)
         ram[addr] <= din;

   assign dout = ram[addr];   

endmodule
module LIFO(
    input clk,
	 input rst,
    input wr_en,
    input rd_en,
    input [10:0] din,
    output [10:0] dout
    );




   reg [3:0] addr;
   reg [10:0] ram [15:0];

   always@(posedge clk)
		if (rst)
			addr<=0;
		else 
			 begin 
			  if (wr_en==0 && rd_en==1)
					if (addr>0)
						addr<=addr-1;
			  if (wr_en==1 && rd_en==0)
					if (addr<15)
						addr<=addr+1;
			 end
		
	always @(posedge clk)
      if (wr_en)
         ram[addr] <= din;

   assign dout = ram[addr];   

endmodule