data/full_repos/permissive/436123010/design_sources/ControlUnit.v
data/verilator_xmls/7f072ffc-29b2-4bb7-835a-8f370b7f3680.xml
module ControlUnit(
    input wire [5:0] instruction,
    input wire [5:0] funct, 
    output reg RegDst,
    output reg Branch,
    output reg BranchNE,    
    output reg MemRead,
    output reg MemToReg,
    output reg [2:0] ALUOp,
    output reg MemWrite,
    output reg ALUSrc,
    output reg RegWrite,
    output reg Jump,
    output reg storeRA,
    output reg jumpRA
    );


    always @* 
        case(instruction)
            6'b000000:
            begin
            if(funct == 6'b001000)
            begin



                RegWrite = 0;

                MemWrite = 0;
                Branch  = 0;
                BranchNE = 0;

                Jump = 0;
                storeRA = 0;
                jumpRA = 1;
            end                            
            else
            begin
                RegDst = 1;
                ALUSrc = 0;
                MemToReg = 0;
                RegWrite = 1;
                MemRead = 0;
                MemWrite = 0;
                Branch  = 0;
                BranchNE = 0;
                ALUOp = 3'b010;
                Jump = 0;
                storeRA = 0;
                jumpRA = 0;
            end   
            end               
            6'b000100:
            begin

                ALUSrc = 0;

                RegWrite = 0;
                MemRead = 0;
                MemWrite = 0;
                Branch  = 1;
                BranchNE = 0;
                ALUOp = 3'b001;
                Jump = 0;   
                storeRA = 0;
                jumpRA = 0;                             
            end
            6'b000101:
            begin

                ALUSrc = 0;

                RegWrite = 0;
                MemRead = 0;
                MemWrite = 0;
                Branch  = 0;
                BranchNE = 1;
                ALUOp = 3'b001;
                Jump = 0;     
                storeRA = 0;
                jumpRA = 0;                
            end           
            6'b000011:
            begin
                RegDst = 0;
                ALUSrc = 0;
                MemToReg = 0;
                MemRead  = 0;

                MemWrite = 0;
                RegWrite = 0;
                Branch = 0;
                BranchNE = 0;

                Jump = 1;
                storeRA = 1;     
                jumpRA = 0; 
            end     
            6'b000010:
            begin

                RegDst = 0;
                ALUSrc = 0;
                MemToReg = 0;
                MemRead  = 0;

                MemWrite = 0;
                RegWrite = 0;
                Branch = 0;
                BranchNE = 0;

                Jump = 1;
                storeRA = 0;     
                jumpRA = 0; 
            end    
            6'b001010:
            begin
                RegDst = 0;
                ALUSrc = 1;
                MemToReg = 0;
                RegWrite = 1;
                MemRead = 0;
                MemWrite = 0;
                Branch  = 0;
                BranchNE = 0;
                ALUOp = 3'b100;
                Jump = 0;
                storeRA = 0;
                jumpRA = 0;
            end
            6'b100011:
            begin
                RegDst = 0;
                ALUSrc = 1;
                MemToReg = 1;
                RegWrite = 1;
                MemRead = 1;
                MemWrite = 0;
                Branch  = 0;
                BranchNE = 0;
                ALUOp = 3'b000;
                Jump = 0;
                storeRA = 0;
                jumpRA = 0;
            end
            6'b101011:
            begin
                RegDst = 0;
                ALUSrc = 1;
                MemToReg = 0;
                RegWrite = 0;
                MemRead = 0;
                MemWrite = 1;
                Branch  = 0;
                BranchNE = 0;
                ALUOp = 3'b000;
                Jump = 0;
                storeRA = 0;
                jumpRA = 0;
            end     
            6'b001000:
            begin
                RegDst = 0;
                ALUSrc = 1;
                MemToReg = 0;
                RegWrite = 1;
                MemRead = 0;
                MemWrite = 0;
                Branch = 0;
                BranchNE = 0;
                ALUOp = 3'b000;
                Jump = 0;
                storeRA = 0;
                jumpRA = 0;
            end                                            
            6'b001001:
            begin
                RegDst = 0;
                ALUSrc = 1;
                MemToReg = 0;
                RegWrite = 1;
                MemRead = 0;
                MemWrite = 0;
                Branch = 0;
                BranchNE = 0;
                ALUOp = 3'b000;
                Jump = 0;
                storeRA = 0;
                jumpRA = 0;
            end       
            default:
            begin
                RegDst = 0; 
                ALUSrc = 0;  
                MemToReg = 0;
                RegWrite = 0; 
                MemRead = 0;  
                MemWrite = 0;
                Branch = 0;   
                BranchNE = 0;
                ALUOp = 3'b000;
                Jump = 0;
                storeRA = 0;
                jumpRA = 0;            
            end                 
        endcase
endmodule
module ControlUnit(
    input wire [5:0] instruction,
    input wire [5:0] funct, 
    output reg RegDst,
    output reg Branch,
    output reg BranchNE,    
    output reg MemRead,
    output reg MemToReg,
    output reg [2:0] ALUOp,
    output reg MemWrite,
    output reg ALUSrc,
    output reg RegWrite,
    output reg Jump,
    output reg storeRA,
    output reg jumpRA
    );



    always @* 
        case(instruction)
            6'b000000:
            begin
            if(funct == 6'b001000)
            begin



                RegWrite = 0;

                MemWrite = 0;
                Branch  = 0;
                BranchNE = 0;

                Jump = 0;
                storeRA = 0;
                jumpRA = 1;
            end                            
            else
            begin
                RegDst = 1;
                ALUSrc = 0;
                MemToReg = 0;
                RegWrite = 1;
                MemRead = 0;
                MemWrite = 0;
                Branch  = 0;
                BranchNE = 0;
                ALUOp = 3'b010;
                Jump = 0;
                storeRA = 0;
                jumpRA = 0;
            end   
            end               
            6'b000100:
            begin

                ALUSrc = 0;

                RegWrite = 0;
                MemRead = 0;
                MemWrite = 0;
                Branch  = 1;
                BranchNE = 0;
                ALUOp = 3'b001;
                Jump = 0;   
                storeRA = 0;
                jumpRA = 0;                             
            end
            6'b000101:
            begin

                ALUSrc = 0;

                RegWrite = 0;
                MemRead = 0;
                MemWrite = 0;
                Branch  = 0;
                BranchNE = 1;
                ALUOp = 3'b001;
                Jump = 0;     
                storeRA = 0;
                jumpRA = 0;                
            end           
            6'b000011:
            begin
                RegDst = 0;
                ALUSrc = 0;
                MemToReg = 0;
                MemRead  = 0;

                MemWrite = 0;
                RegWrite = 0;
                Branch = 0;
                BranchNE = 0;

                Jump = 1;
                storeRA = 1;     
                jumpRA = 0; 
            end     
            6'b000010:
            begin

                RegDst = 0;
                ALUSrc = 0;
                MemToReg = 0;
                MemRead  = 0;

                MemWrite = 0;
                RegWrite = 0;
                Branch = 0;
                BranchNE = 0;

                Jump = 1;
                storeRA = 0;     
                jumpRA = 0; 
            end    
            6'b001010:
            begin
                RegDst = 0;
                ALUSrc = 1;
                MemToReg = 0;
                RegWrite = 1;
                MemRead = 0;
                MemWrite = 0;
                Branch  = 0;
                BranchNE = 0;
                ALUOp = 3'b100;
                Jump = 0;
                storeRA = 0;
                jumpRA = 0;
            end
            6'b100011:
            begin
                RegDst = 0;
                ALUSrc = 1;
                MemToReg = 1;
                RegWrite = 1;
                MemRead = 1;
                MemWrite = 0;
                Branch  = 0;
                BranchNE = 0;
                ALUOp = 3'b000;
                Jump = 0;
                storeRA = 0;
                jumpRA = 0;
            end
            6'b101011:
            begin
                RegDst = 0;
                ALUSrc = 1;
                MemToReg = 0;
                RegWrite = 0;
                MemRead = 0;
                MemWrite = 1;
                Branch  = 0;
                BranchNE = 0;
                ALUOp = 3'b000;
                Jump = 0;
                storeRA = 0;
                jumpRA = 0;
            end     
            6'b001000:
            begin
                RegDst = 0;
                ALUSrc = 1;
                MemToReg = 0;
                RegWrite = 1;
                MemRead = 0;
                MemWrite = 0;
                Branch = 0;
                BranchNE = 0;
                ALUOp = 3'b000;
                Jump = 0;
                storeRA = 0;
                jumpRA = 0;
            end                                            
            6'b001001:
            begin
                RegDst = 0;
                ALUSrc = 1;
                MemToReg = 0;
                RegWrite = 1;
                MemRead = 0;
                MemWrite = 0;
                Branch = 0;
                BranchNE = 0;
                ALUOp = 3'b000;
                Jump = 0;
                storeRA = 0;
                jumpRA = 0;
            end       
            default:
            begin
                RegDst = 0; 
                ALUSrc = 0;  
                MemToReg = 0;
                RegWrite = 0; 
                MemRead = 0;  
                MemWrite = 0;
                Branch = 0;   
                BranchNE = 0;
                ALUOp = 3'b000;
                Jump = 0;
                storeRA = 0;
                jumpRA = 0;            
            end                 
        endcase
endmodule