data/full_repos/permissive/510956372/src/counter_bcd.v
data/verilator_xmls/dce04a69-d72a-4d06-b7ec-a41dc696f34a.xml
module counter_bcd(   input clk,
                      input enable,
                      input reset,
                      output reg [3:0] bcd,
                      output cnt_9);
  initial begin
    bcd = 0;
    cnt_9 = 0;
  end
  always @(posedge clk) begin
    if (reset) begin
      bcd = 0;
      cnt_9 = 1'b0; 
    end else if (enable) begin

      if (bcd == 9) begin
        bcd = 0;
      end else begin
        bcd++;
      end
      

      cnt_9 = (bcd == 9)? 1'b1 : 1'b0;
    end 
  end 
endmodule
module counter_bcd(   input clk,
                      input enable,
                      input reset,
                      output reg [3:0] bcd,
                      output cnt_9);

  initial begin
    bcd = 0;
    cnt_9 = 0;
  end
  always @(posedge clk) begin
    if (reset) begin
      bcd = 0;
      cnt_9 = 1'b0; 
    end else if (enable) begin

      if (bcd == 9) begin
        bcd = 0;
      end else begin
        bcd++;
      end
      

      cnt_9 = (bcd == 9)? 1'b1 : 1'b0;
    end 
  end 
endmodule