data/full_repos/permissive/479923049/top.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/479923049/top.v:37: Signal definition not found, creating implicitly: \'tri_state_enable\'\n                                                                : ... Suggested alternative: \'tristate_enable\'\n  assign tri_state_enable = (2\'d1 == mem_cmd) & (1\'b0 == mem_addr[8]);    \n         ^~~~~~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/479923049/top.v:41: Signal definition not found, creating implicitly: \'tri_state_switch_enable\'\n                                                                : ... Suggested alternative: \'tri_state_enable\'\n  assign tri_state_switch_enable = ((mem_addr == 9\'h140) && (mem_cmd == 2\'d1));\n         ^~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/479923049/top.v:48: Signal definition not found, creating implicitly: \'led_enable\'\n  assign led_enable = ((mem_addr == 9\'h100) && (mem_cmd == 2\'d2));\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/479923049/top.v:17: Cannot find file containing module: \'cpu\'\n  cpu CPU ( .clk          (~KEY[0]),\n  ^~~\n        ... Looked in:\n             data/full_repos/permissive/479923049,data/full_repos/permissive/479923049/cpu\n             data/full_repos/permissive/479923049,data/full_repos/permissive/479923049/cpu.v\n             data/full_repos/permissive/479923049,data/full_repos/permissive/479923049/cpu.sv\n             cpu\n             cpu.v\n             cpu.sv\n             obj_dir/cpu\n             obj_dir/cpu.v\n             obj_dir/cpu.sv\n%Error: data/full_repos/permissive/479923049/top.v:50: Cannot find file containing module: \'vDFFE\'\n  vDFFE #(8) ledr_register(.clk (KEY[0]), .en (led_enable), .in (write_data[7:0]), .out (LEDR[7:0]));\n  ^~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module RAM(clk,read_address,write_address,write,din,dout);
  parameter data_width = 16; 
  parameter addr_width = 8;
  parameter filename = "data.txt";

  input clk;
  input [addr_width-1:0] read_address, write_address;
  input write;
  input [data_width-1:0] din;
  output [data_width-1:0] dout;
  reg [data_width-1:0] dout;

  reg [data_width-1:0] mem [2**addr_width-1:0];

  initial $readmemb(filename, mem);

  always @ (posedge clk) begin
    if (write)
      mem[write_address] <= din;
    dout <= mem[read_address];

  end 
endmodule
module RAM(clk,read_address,write_address,write,din,dout);

  parameter data_width = 16; 
  parameter addr_width = 8;
  parameter filename = "data.txt";

  input clk;
  input [addr_width-1:0] read_address, write_address;
  input write;
  input [data_width-1:0] din;
  output [data_width-1:0] dout;
  reg [data_width-1:0] dout;

  reg [data_width-1:0] mem [2**addr_width-1:0];

  initial $readmemb(filename, mem);

  always @ (posedge clk) begin
    if (write)
      mem[write_address] <= din;
    dout <= mem[read_address];

  end 
endmodule