data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code/FAnbit.v
1: b"%Error: data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code/FAnbit.v:34: Cannot find file containing module: 'FA'\n       FA UNIT0 (\n       ^~\n        ... Looked in:\n             data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code,data/full_repos/permissive/502135797/FA\n             data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code,data/full_repos/permissive/502135797/FA.v\n             data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code,data/full_repos/permissive/502135797/FA.sv\n             FA\n             FA.v\n             FA.sv\n             obj_dir/FA\n             obj_dir/FA.v\n             obj_dir/FA.sv\n%Error: data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code/FAnbit.v:47: Cannot find file containing module: 'FA'\n        FA UNIT(\n        ^~\n%Error: Exiting due to 2 error(s)\n"
module FAnbit
        #(parameter DT = 4)
(
    input cinbit,
    input [DT-1:0] abit,
    input [DT-1:0] bbit,
    output [DT-1:0] sumbit,
    output coutbit
    );
    wire [DT-1:0] bridge;
    
       FA UNIT0 (
                 .cin(cinbit),
                 .a(abit[0]),
                 .b(bbit[0]),
                 .sum(sumbit[0]),
                 .cout(bridge[0])
                    );
       
    genvar i;
    generate
    for(i=1;i<DT;i=i+1)
        begin
        
        FA UNIT(
                 .cin(bridge[i-1]),
                 .a(abit[i]),
                 .b(bbit[i]),
                 .sum(sumbit[i]),
                 .cout(bridge[i])
        );  
     end
    endgenerate
      
    assign coutbit=bridge[DT-1];
endmodule
module FAnbit
        #(parameter DT = 4)
(
    input cinbit,
    input [DT-1:0] abit,
    input [DT-1:0] bbit,
    output [DT-1:0] sumbit,
    output coutbit
    );

    wire [DT-1:0] bridge;
    
       FA UNIT0 (
                 .cin(cinbit),
                 .a(abit[0]),
                 .b(bbit[0]),
                 .sum(sumbit[0]),
                 .cout(bridge[0])
                    );
       
    genvar i;
    generate
    for(i=1;i<DT;i=i+1)
        begin
        
        FA UNIT(
                 .cin(bridge[i-1]),
                 .a(abit[i]),
                 .b(bbit[i]),
                 .sum(sumbit[i]),
                 .cout(bridge[i])
        );  
     end
    endgenerate
      
    assign coutbit=bridge[DT-1];
endmodule