data/full_repos/permissive/434840709/lab2/mux/test_mux_2_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/434840709/lab2/mux/test_mux_2_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n        d=2\'b10;A=0;#1000;\n                    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/434840709/lab2/mux/test_mux_2_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n        d=2\'b10;A=1;#1000;\n                    ^\n%Error: data/full_repos/permissive/434840709/lab2/mux/test_mux_2_tb.v:7: Cannot find file containing module: \'mux2\'\n    mux2 u0(.d(d),.a(a),.y(y));\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/434840709/lab2/mux,data/full_repos/permissive/434840709/mux2\n             data/full_repos/permissive/434840709/lab2/mux,data/full_repos/permissive/434840709/mux2.v\n             data/full_repos/permissive/434840709/lab2/mux,data/full_repos/permissive/434840709/mux2.sv\n             mux2\n             mux2.v\n             mux2.sv\n             obj_dir/mux2\n             obj_dir/mux2.v\n             obj_dir/mux2.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_mux2();
    reg A;
    reg [1:0]d;
    wire a;
    wire y;
    mux2 u0(.d(d),.a(a),.y(y));
    assign a = A;
    initial
    begin
        d=2'b10;A=0;#1000;
        d=2'b10;A=1;#1000;
    end
endmodule
module test_mux2();

    reg A;
    reg [1:0]d;
    wire a;
    wire y;
    mux2 u0(.d(d),.a(a),.y(y));
    assign a = A;
    initial
    begin
        d=2'b10;A=0;#1000;
        d=2'b10;A=1;#1000;
    end
endmodule