data/full_repos/permissive/448192472/V14_3bit_up_down_counter_Basys2/updown_counter.v
data/verilator_xmls/e12e715a-abfc-42a5-9bf8-3162cc9c6d4d.xml
module updown_counter(clk, dir_up, clear, Q, sclk);

input clk, dir_up, clear;
output reg [2:0] Q;
output sclk;

reg [24:0] counter = 0;

assign sclk = counter[24];

always @(posedge clk)
	counter <= counter + 1;

always @(posedge sclk or posedge clear)
	begin
		if (clear)
		begin
			Q <= 3'b000; 
		end
		else
		begin
			if(dir_up)
			begin
			 Q <= Q + 1;
			end
			else 
			begin
			 Q <= Q - 1;
			end
		end
	end
endmodule
module updown_counter(clk, dir_up, clear, Q, sclk);


input clk, dir_up, clear;
output reg [2:0] Q;
output sclk;

reg [24:0] counter = 0;

assign sclk = counter[24];

always @(posedge clk)
	counter <= counter + 1;

always @(posedge sclk or posedge clear)
	begin
		if (clear)
		begin
			Q <= 3'b000; 
		end
		else
		begin
			if(dir_up)
			begin
			 Q <= Q + 1;
			end
			else 
			begin
			 Q <= Q - 1;
			end
		end
	end
endmodule