data/full_repos/permissive/425063349/Transmitter_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/425063349/Transmitter_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n  #80 Reset = 1\'b0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/425063349/Transmitter_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n  #1000 Reset = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/425063349/Transmitter_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #100 Reset = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/425063349/Transmitter_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #1000 Reset = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/425063349/Transmitter_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #100 Reset = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/425063349/Transmitter_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #50 Clock = ~Clock;\n  ^\n%Error: data/full_repos/permissive/425063349/Transmitter_tb.v:7: Cannot find file containing module: \'Transmitter\'\n Transmitter t1(Byte, Z, hashValue, Reset, Clock);\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/425063349,data/full_repos/permissive/425063349/Transmitter\n             data/full_repos/permissive/425063349,data/full_repos/permissive/425063349/Transmitter.v\n             data/full_repos/permissive/425063349,data/full_repos/permissive/425063349/Transmitter.sv\n             Transmitter\n             Transmitter.v\n             Transmitter.sv\n             obj_dir/Transmitter\n             obj_dir/Transmitter.v\n             obj_dir/Transmitter.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Transmitter_tb;
	reg [63:0] hashValue = 64'h652a55328ca;
	wire [7:0] Byte;
	reg Clock = 1;
	reg Reset = 1;
	wire Z;
	Transmitter t1(Byte, Z, hashValue, Reset, Clock);
	
	initial begin
		#80 Reset = 1'b0;
		#1000 Reset = 1'b1;
		hashValue = 64'hd0ab89039614;
		
		#100 Reset = 1'b0;
		#1000 Reset = 1'b1;
		hashValue = 64'hd0a7798b0879;
		
		#100 Reset = 1'b0;
	end

	always
		#50 Clock = ~Clock;
endmodule
module Transmitter_tb;

	reg [63:0] hashValue = 64'h652a55328ca;
	wire [7:0] Byte;
	reg Clock = 1;
	reg Reset = 1;
	wire Z;
	Transmitter t1(Byte, Z, hashValue, Reset, Clock);
	
	initial begin
		#80 Reset = 1'b0;
		#1000 Reset = 1'b1;
		hashValue = 64'hd0ab89039614;
		
		#100 Reset = 1'b0;
		#1000 Reset = 1'b1;
		hashValue = 64'hd0a7798b0879;
		
		#100 Reset = 1'b0;
	end

	always
		#50 Clock = ~Clock;
endmodule