data/full_repos/permissive/523397305/iiitb_8bit_up_down_counter_tb.v
1: b'%Error: data/full_repos/permissive/523397305/iiitb_8bit_up_down_counter_tb.v:10: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("waveform.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/523397305/iiitb_8bit_up_down_counter_tb.v:11: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0,updowncounter_testbench);\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/523397305/iiitb_8bit_up_down_counter_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\nforever #5 clk=~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/523397305/iiitb_8bit_up_down_counter_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/523397305/iiitb_8bit_up_down_counter_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n#200;\n^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module updowncounter_testbench();
reg clk, reset,up_down;
wire [7:0] counter;

up_down_counter dut(clk, reset,up_down, counter);
initial begin 

$dumpfile("waveform.vcd");
$dumpvars(0,updowncounter_testbench);

clk=0;
forever #5 clk=~clk;
end
initial begin
reset=1;
up_down=0;
#20;
reset=0;
#200;
up_down=1;
end
endmodule
module updowncounter_testbench();

reg clk, reset,up_down;
wire [7:0] counter;

up_down_counter dut(clk, reset,up_down, counter);
initial begin 

$dumpfile("waveform.vcd");
$dumpvars(0,updowncounter_testbench);

clk=0;
forever #5 clk=~clk;
end
initial begin
reset=1;
up_down=0;
#20;
reset=0;
#200;
up_down=1;
end
endmodule