data/full_repos/permissive/433640910/RateDivider/ratedivider.v
data/verilator_xmls/57a74fa6-75f9-4eaa-9a52-504b12b5b704.xml
module part2(ClockIn, Reset, Speed, CounterValue);
	input ClockIn, Reset;
	input [1:0] Speed;
	output [3:0] CounterValue;
	
	wire Enable;
	wire [26:0] RateDividerCounter;		
	
	RateDivider u0(Speed, ClockIn, Reset, RateDividerCounter);

	assign Enable = (RateDividerCounter == 0) ? 1 : 0;
	
	counter c1 (ClockIn, ~Reset, Enable, CounterValue);
	
endmodule
module part2(ClockIn, Reset, Speed, CounterValue);

	input ClockIn, Reset;
	input [1:0] Speed;
	output [3:0] CounterValue;
	
	wire Enable;
	wire [26:0] RateDividerCounter;		
	
	RateDivider u0(Speed, ClockIn, Reset, RateDividerCounter);

	assign Enable = (RateDividerCounter == 0) ? 1 : 0;
	
	counter c1 (ClockIn, ~Reset, Enable, CounterValue);
	
endmodule