data/full_repos/permissive/478970138/4-6/user/sim/tb.v
1: b'%Error: data/full_repos/permissive/478970138/4-6/user/sim/tb.v:7: Unsupported or unknown PLI call: $dumpfile\n       $dumpfile("wave.vcd");\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/478970138/4-6/user/sim/tb.v:8: Unsupported or unknown PLI call: $dumpvars\n       $dumpvars(0, tb);\n       ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/478970138/4-6/user/sim/tb.v:9: Unsupported: Ignoring delay on this delayed statement.\n       #6000 $finish;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/478970138/4-6/user/sim/tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #10 A = A + 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/478970138/4-6/user/sim/tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #160 B = B + 1\'b1;\n        ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb (

);
    initial begin
       $dumpfile("wave.vcd");
       $dumpvars(0, tb);
       #6000 $finish;
    end

    reg [3:0] A, B;

    initial begin
        A = 4'b0;
        B = 4'b0;
    end

    always begin
        #10 A = A + 1'b1;
    end

    always begin
        #160 B = B + 1'b1;
    end

    wire [7:0]	S;

    multiplier4 u_multiplier4(

        .A 		( A 		),
        .B 		( B 		),
        .S 		( S 		)
    );

endmodule
module tb (

);

    initial begin
       $dumpfile("wave.vcd");
       $dumpvars(0, tb);
       #6000 $finish;
    end

    reg [3:0] A, B;

    initial begin
        A = 4'b0;
        B = 4'b0;
    end

    always begin
        #10 A = A + 1'b1;
    end

    always begin
        #160 B = B + 1'b1;
    end

    wire [7:0]	S;

    multiplier4 u_multiplier4(

        .A 		( A 		),
        .B 		( B 		),
        .S 		( S 		)
    );

endmodule