data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/SIMPLE_COUNTER.v
data/verilator_xmls/fa202062-901f-48f2-826c-6efed94009e7.xml
module SIMPLE_COUNTER #(parameter BITWIDTH=10)(


COUNTER_Clk,
COUNTER_Clr,
COUNTER_En,
COUNTER_Number,


COUNTER_Out,
COUNTER_Eqn_Flag

);





input COUNTER_Clk;
input COUNTER_Clr;
input COUNTER_En;
input [BITWIDTH-1:0] COUNTER_Number;
output [BITWIDTH-1:0] COUNTER_Out;
output COUNTER_Eqn_Flag;




reg [BITWIDTH-1:0] counter;





always@(posedge COUNTER_Clk or negedge COUNTER_Clr)
begin
		if(!COUNTER_Clr)
		begin
			counter<=0;
		end
		else if(COUNTER_En)
			counter<=counter +1'b1;
end


assign COUNTER_Out=counter;
assign COUNTER_Eqn_Flag = counter== COUNTER_Number ? 1'b1 : 1'b0;

endmodule
module SIMPLE_COUNTER #(parameter BITWIDTH=10)(


COUNTER_Clk,
COUNTER_Clr,
COUNTER_En,
COUNTER_Number,


COUNTER_Out,
COUNTER_Eqn_Flag

);






input COUNTER_Clk;
input COUNTER_Clr;
input COUNTER_En;
input [BITWIDTH-1:0] COUNTER_Number;
output [BITWIDTH-1:0] COUNTER_Out;
output COUNTER_Eqn_Flag;




reg [BITWIDTH-1:0] counter;





always@(posedge COUNTER_Clk or negedge COUNTER_Clr)
begin
		if(!COUNTER_Clr)
		begin
			counter<=0;
		end
		else if(COUNTER_En)
			counter<=counter +1'b1;
end


assign COUNTER_Out=counter;
assign COUNTER_Eqn_Flag = counter== COUNTER_Number ? 1'b1 : 1'b0;

endmodule