data/full_repos/permissive/462323524/validation/lib/map_file.v
1: b'%Error: data/full_repos/permissive/462323524/validation/lib/map_file.v:26: Unsupported or unknown PLI call: $adff\n    $adff  #( \n    ^~~~~\n%Error: data/full_repos/permissive/462323524/validation/lib/map_file.v:26: syntax error, unexpected ${ignored-bbox-sys}\n    $adff  #( \n         ^\n%Error: data/full_repos/permissive/462323524/validation/lib/map_file.v:66: Unsupported or unknown PLI call: $dff\n    $dff  #( \n    ^~~~\n%Error: data/full_repos/permissive/462323524/validation/lib/map_file.v:66: syntax error, unexpected ${ignored-bbox-sys}\n    $dff  #( \n        ^\n%Error: data/full_repos/permissive/462323524/validation/lib/map_file.v:105: Unsupported or unknown PLI call: $dffsr\n    $dffsr  #( \n    ^~~~~~\n%Error: data/full_repos/permissive/462323524/validation/lib/map_file.v:105: syntax error, unexpected ${ignored-bbox-sys}\n    $dffsr  #( \n          ^\n%Error: data/full_repos/permissive/462323524/validation/lib/map_file.v:149: Unsupported or unknown PLI call: $aldff\n    $aldff  #( \n    ^~~~~~\n%Error: data/full_repos/permissive/462323524/validation/lib/map_file.v:149: syntax error, unexpected ${ignored-bbox-sys}\n    $aldff  #( \n          ^\n%Error: data/full_repos/permissive/462323524/validation/lib/map_file.v:238: Unsupported or unknown PLI call: $sdff\n    $sdff  #( \n    ^~~~~\n%Error: data/full_repos/permissive/462323524/validation/lib/map_file.v:238: syntax error, unexpected ${ignored-bbox-sys}\n    $sdff  #( \n         ^\n%Error: Exiting due to 10 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module \$dffe ( CLK, D, EN, Q);
    parameter CLK_POLARITY =1'b1;
    parameter EN_POLARITY =1'b1;
    parameter WIDTH =1;

    input  CLK, EN;
    input [WIDTH -1:0] D; 
    output [WIDTH -1:0] Q;

    wire GCLK;

    generate
        if (WIDTH < 5) begin
                sky130_fd_sc_hd__dlclkp_1  clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
                end
            else if (WIDTH < 17) begin
                sky130_fd_sc_hd__dlclkp_2  clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
                end
            else begin
                sky130_fd_sc_hd__dlclkp_4  clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
        end
    endgenerate

    $dff  #( 
            .WIDTH(WIDTH), 
            .CLK_POLARITY(CLK_POLARITY),
            ) 
            flipflop(  
            .CLK(GCLK), 
            .D(D), 
            .Q(Q)
            );
endmodule
module \$dffe ( CLK, D, EN, Q);

    parameter CLK_POLARITY =1'b1;
    parameter EN_POLARITY =1'b1;
    parameter WIDTH =1;

    input  CLK, EN;
    input [WIDTH -1:0] D; 
    output [WIDTH -1:0] Q;

    wire GCLK;

    generate
        if (WIDTH < 5) begin
                sky130_fd_sc_hd__dlclkp_1  clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
                end
            else if (WIDTH < 17) begin
                sky130_fd_sc_hd__dlclkp_2  clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
                end
            else begin
                sky130_fd_sc_hd__dlclkp_4  clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
        end
    endgenerate

    $dff  #( 
            .WIDTH(WIDTH), 
            .CLK_POLARITY(CLK_POLARITY),
            ) 
            flipflop(  
            .CLK(GCLK), 
            .D(D), 
            .Q(Q)
            );
endmodule