data/full_repos/permissive/528912093/Proiect/Vsm-AccumulatorA.v
1: b"%Error: data/full_repos/permissive/528912093/Proiect/Vsm-AccumulatorA.v:9: syntax error, unexpected ';', expecting IDENTIFIER or do or final\n wire w6,w7,w9,w11,w13,w15,;\n                           ^\n%Error: data/full_repos/permissive/528912093/Proiect/Vsm-AccumulatorA.v:23: syntax error, unexpected always\nalways\n^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module VsmAccumulatorA( A[0],A[1],A[2],A[3],ClearA,EnableA,LatchA,MainClock,
 AluA3,IB3,IB2,IB1,IB0,AluA0,AluA1,AluA2);
 input A[0],A[1],A[2],A[3],ClearA,EnableA,LatchA,MainClock;
 output AluA3,IB3,IB2,IB1,IB0,AluA0,AluA1,AluA2;
 wire w6,w7,w9,w11,w13,w15,;
 dreg #(4) dreg_1(AluA0,w9,A[0],w6,w7);
 dreg #(4) dreg_2(AluA1,w11,A[1],w6,w7);
 dreg #(4) dreg_3(AluA2,w13,A[2],w6,w7);
 dreg #(4) dreg_4(AluA3,w15,A[3],w6,w7);
 not #(3) inv_5(w6,ClearA);
 and #(5) and2_6(w7,MainClock,LatchA);
 notif1 #(1) notif1_7(IB0,w9,EnableA);
 notif1 #(1) notif1_8(IB1,w11,EnableA);
 notif1 #(1) notif1_9(IB2,w13,EnableA);
 notif1 #(1) notif1_10(IB3,w15,EnableA);
endmodule
module VsmAccumulatorA( A[0],A[1],A[2],A[3],ClearA,EnableA,LatchA,MainClock,
 AluA3,IB3,IB2,IB1,IB0,AluA0,AluA1,AluA2);

 input A[0],A[1],A[2],A[3],ClearA,EnableA,LatchA,MainClock;
 output AluA3,IB3,IB2,IB1,IB0,AluA0,AluA1,AluA2;
 wire w6,w7,w9,w11,w13,w15,;
 dreg #(4) dreg_1(AluA0,w9,A[0],w6,w7);
 dreg #(4) dreg_2(AluA1,w11,A[1],w6,w7);
 dreg #(4) dreg_3(AluA2,w13,A[2],w6,w7);
 dreg #(4) dreg_4(AluA3,w15,A[3],w6,w7);
 not #(3) inv_5(w6,ClearA);
 and #(5) and2_6(w7,MainClock,LatchA);
 notif1 #(1) notif1_7(IB0,w9,EnableA);
 notif1 #(1) notif1_8(IB1,w11,EnableA);
 notif1 #(1) notif1_9(IB2,w13,EnableA);
 notif1 #(1) notif1_10(IB3,w15,EnableA);
endmodule