data/full_repos/permissive/42581625/PersonalComputer/vag.v
1: b'%Warning-WIDTH: data/full_repos/permissive/42581625/PersonalComputer/vag.v:40: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 11 bits.\n                                                                             : ... In instance vga_dis\nassign xpos = x_cnt-11\'d267; \n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/42581625/PersonalComputer/vag.v:97: Cannot find file containing module: \'ZBziku\'\nZBziku ziku(\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/42581625/PersonalComputer,data/full_repos/permissive/42581625/ZBziku\n             data/full_repos/permissive/42581625/PersonalComputer,data/full_repos/permissive/42581625/ZBziku.v\n             data/full_repos/permissive/42581625/PersonalComputer,data/full_repos/permissive/42581625/ZBziku.sv\n             ZBziku\n             ZBziku.v\n             ZBziku.sv\n             obj_dir/ZBziku\n             obj_dir/ZBziku.v\n             obj_dir/ZBziku.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module vga_dis(
input clk,
input rst_n,
input[15:0] ZBcode,
output valid,
output[9:0] xpos,
output[9:0] ypos,
output hsync,
output vsync,
output vga_r,
output vga_g,
output vga_b
);


reg[10:0] x_cnt;
reg[9:0] y_cnt;
initial begin
	x_cnt <= 0;
	y_cnt <= 0;
end
always @ (posedge clk or negedge rst_n)
if(!rst_n) x_cnt <= 11'd0;
else if(x_cnt == 11'd1039) x_cnt <= 11'd0;
else x_cnt <= x_cnt+1'b1;

always @ (posedge clk or negedge rst_n)
if(!rst_n) y_cnt <= 10'd0;
else if(y_cnt == 10'd665) y_cnt <= 10'd0;
else if(x_cnt == 11'd1039) y_cnt <= y_cnt+1'b1;




assign valid = (x_cnt >= 11'd267) && (x_cnt < 11'd907) 
&& (y_cnt >= 10'd131) && (y_cnt < 10'd531); 
 

assign xpos = x_cnt-11'd267;
assign ypos = y_cnt-10'd131;


reg hsync_r,vsync_r;
initial begin
	hsync_r <= 1;
	vsync_r <= 1;
end
always @ (posedge clk or negedge rst_n)
	if(!rst_n) 
		hsync_r <= 1'b1;
	else if(x_cnt == 11'd0) 
		hsync_r <= 1'b0;
	else if(x_cnt == 11'd120) 
		hsync_r <= 1'b1;
 
always @ (posedge clk or negedge rst_n)
if(!rst_n) vsync_r <= 1'b1;
else if(y_cnt == 10'd0) vsync_r <= 1'b0;
else if(y_cnt == 10'd6) vsync_r <= 1'b1;

assign hsync = hsync_r;
assign vsync = vsync_r;



wire white;
wire[15:0] bit16;
wire[7:0] adr;
assign adr = (|ZBcode[15:7])? 8'h1 : ZBcode[7:0];
ZBziku ziku(
	.addra({adr[7:0],ypos[3:0]}),
	.douta(bit16)
);

assign white = bit16[4'd15-xpos[3:0]];
assign vga_r = valid ? white : 1'b0;
assign vga_g = valid ? white : 1'b0;
assign vga_b = valid ? white : 1'b0;
endmodule
module vga_dis(
input clk,
input rst_n,
input[15:0] ZBcode,
output valid,
output[9:0] xpos,
output[9:0] ypos,
output hsync,
output vsync,
output vga_r,
output vga_g,
output vga_b
);



reg[10:0] x_cnt;
reg[9:0] y_cnt;
initial begin
	x_cnt <= 0;
	y_cnt <= 0;
end
always @ (posedge clk or negedge rst_n)
if(!rst_n) x_cnt <= 11'd0;
else if(x_cnt == 11'd1039) x_cnt <= 11'd0;
else x_cnt <= x_cnt+1'b1;

always @ (posedge clk or negedge rst_n)
if(!rst_n) y_cnt <= 10'd0;
else if(y_cnt == 10'd665) y_cnt <= 10'd0;
else if(x_cnt == 11'd1039) y_cnt <= y_cnt+1'b1;




assign valid = (x_cnt >= 11'd267) && (x_cnt < 11'd907) 
&& (y_cnt >= 10'd131) && (y_cnt < 10'd531); 
 

assign xpos = x_cnt-11'd267;
assign ypos = y_cnt-10'd131;


reg hsync_r,vsync_r;
initial begin
	hsync_r <= 1;
	vsync_r <= 1;
end
always @ (posedge clk or negedge rst_n)
	if(!rst_n) 
		hsync_r <= 1'b1;
	else if(x_cnt == 11'd0) 
		hsync_r <= 1'b0;
	else if(x_cnt == 11'd120) 
		hsync_r <= 1'b1;
 
always @ (posedge clk or negedge rst_n)
if(!rst_n) vsync_r <= 1'b1;
else if(y_cnt == 10'd0) vsync_r <= 1'b0;
else if(y_cnt == 10'd6) vsync_r <= 1'b1;

assign hsync = hsync_r;
assign vsync = vsync_r;



wire white;
wire[15:0] bit16;
wire[7:0] adr;
assign adr = (|ZBcode[15:7])? 8'h1 : ZBcode[7:0];
ZBziku ziku(
	.addra({adr[7:0],ypos[3:0]}),
	.douta(bit16)
);

assign white = bit16[4'd15-xpos[3:0]];
assign vga_r = valid ? white : 1'b0;
assign vga_g = valid ? white : 1'b0;
assign vga_b = valid ? white : 1'b0;
endmodule