data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_loop_unrolling/bdw_work/modules/dut/UNROLL_FILL/v_rtl/dut_LessThan_4Sx4S_1U_4.v
data/verilator_xmls/6a7ee35d-5624-42aa-bb61-a4b92d912a06.xml
module dut_LessThan_4Sx4S_1U_4 (
	in2,
	in1,
	out1
	);
input [3:0] in2,
	in1;
output  out1;
wire  asc001;

assign asc001 = ((9'B100000000 ^ {{5{in1[3]}}, in1})>(9'B100000000 ^ {{5{in2[3]}}, in2}));

assign out1 = asc001;
endmodule
module dut_LessThan_4Sx4S_1U_4 (
	in2,
	in1,
	out1
	);

input [3:0] in2,
	in1;
output  out1;
wire  asc001;

assign asc001 = ((9'B100000000 ^ {{5{in1[3]}}, in1})>(9'B100000000 ^ {{5{in2[3]}}, in2}));

assign out1 = asc001;
endmodule