data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/phy-tx/probador_phy_tx.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/phy-tx/probador_phy_tx.v:22: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk_32f = ~clk_32f;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/phy-tx/probador_phy_tx.v:58: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile ("prueba_phy_tx.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/phy-tx/probador_phy_tx.v:59: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/phy-tx/probador_phy_tx.v:65: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/phy-tx/probador_phy_tx.v:70: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/phy-tx/probador_phy_tx.v:88: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/phy-tx/probador_phy_tx.v:106: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/phy-tx/probador_phy_tx.v:124: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/phy-tx/probador_phy_tx.v:143: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/phy-tx/probador_phy_tx.v:196: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/phy-tx/probador_phy_tx.v:214: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/phy-tx/probador_phy_tx.v:233: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/phy-tx/probador_phy_tx.v:269: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/phy-tx/probador_phy_tx.v:287: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/phy-tx/probador_phy_tx.v:306: syntax error, unexpected \'@\'\n        @(posedge clk_32f);\n        ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/phy-tx/probador_phy_tx.v:342: syntax error, unexpected \'@\'\n        @(posedge clk_32f);\n        ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/phy-tx/probador_phy_tx.v:360: syntax error, unexpected \'@\'\n        @(posedge clk_32f);\n        ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/phy-tx/probador_phy_tx.v:379: syntax error, unexpected \'@\'\n        @(posedge clk_32f);\n        ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/phy-tx/probador_phy_tx.v:450: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n reg [1:0] checker; \n           ^~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/phy-tx/probador_phy_tx.v:450: syntax error, unexpected \';\', expecting IDENTIFIER or \'=\' or do or final\n reg [1:0] checker; \n                  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/phy-tx/probador_phy_tx.v:452: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  if (Data_out_1bit_0_c == Data_out_1bit_0_e) checker[1] = 1;\n                                              ^~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/phy-tx/probador_phy_tx.v:452: syntax error, unexpected \'[\'\n  if (Data_out_1bit_0_c == Data_out_1bit_0_e) checker[1] = 1;\n                                                     ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/phy-tx/probador_phy_tx.v:453: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  else checker[1] = 0;\n       ^~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/phy-tx/probador_phy_tx.v:455: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  if (Data_out_1bit_1_c == Data_out_1bit_1_e) checker[0] = 1;\n                                              ^~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/phy-tx/probador_phy_tx.v:455: syntax error, unexpected \'[\'\n  if (Data_out_1bit_1_c == Data_out_1bit_1_e) checker[0] = 1;\n                                                     ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/ProyectoFinal/phy-tx/probador_phy_tx.v:456: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  else checker[0] = 0;\n       ^~~~~~~\n%Error: Exiting due to 25 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module probador_phy_tx (
	output reg clk_32f,
	output reg clk_2f,
	output reg clk_4f,
	output reg reset,
	output reg valid_in,
	output reg [31:0] Data_in,
	input  Data_out_1bit_0_c,
	input  Data_out_1bit_1_c,
    input  Data_out_1bit_0_e,
	input  Data_out_1bit_1_e
);
	reg [1:0] conteo_4;
	reg [2:0] conteo_2;
	initial begin
		clk_32f = 0;
		clk_4f = 0;
		clk_2f = 0;
		conteo_4 = 'b11;
		conteo_2 = 'b111;
	end 
	always #1 clk_32f = ~clk_32f;

	always @(posedge clk_32f) begin
		case (conteo_4)
			2'b00: conteo_4 <= 2'b01;
			2'b01: conteo_4 <= 2'b10;
			2'b10: conteo_4 <= 2'b11;
			2'b11:
			begin
				conteo_4 <= 2'b00;
				case (clk_4f)
					1'b0: clk_4f <= 1;
					1'b1: clk_4f <= 0;
				endcase
			end 
		endcase
		case (conteo_2)
			3'b000: conteo_2 <= 3'b001;
			3'b001: conteo_2 <= 3'b010;
			3'b010: conteo_2 <= 3'b011;
			3'b011: conteo_2 <= 3'b100;
			3'b100: conteo_2 <= 3'b101;
			3'b101: conteo_2 <= 3'b110;
			3'b110: conteo_2 <= 3'b111;
			3'b111:
			begin
				conteo_2 <= 3'b000;
				case (clk_2f)
					1'b0: clk_2f <= 1;
					1'b1: clk_2f <= 0;
				endcase
			end 
		endcase
	end

	initial begin
		$dumpfile ("prueba_phy_tx.vcd");
		$dumpvars;

		reset <= 0;
		valid_in <= 0;
		Data_in <= 32'b0;

		@(posedge clk_32f);
		reset <= 1;
		valid_in <= 1;
		Data_in <= 'hFFFFFFFF;

		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 'hEEEEEEEE;

		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 'hDDDDDDDD;
        
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 'hCCCCCCCC;
        
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		valid_in <= 0;
		Data_in <= 32'b0;
        
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);

		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);

		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		valid_in <= 1;
		Data_in <= 'h00000003;
        
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 'h00000004;

		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		valid_in <= 0;
		Data_in <= 32'b0;

		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);

		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		valid_in <= 1;
		Data_in <= 'hAAAAAAAA;
        
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 'h99999999;

		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		valid_in <= 0;
		Data_in <= 32'b0;
		
        @(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);

		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		valid_in <= 1;
		Data_in <= 'h00000007;
		
        @(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 'h00000008;
		
        @(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		valid_in <= 0;
		Data_in <= 32'b0;
		
        @(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		$finish;
	end




	reg [1:0] checker; 
	always @(*) begin
		if (Data_out_1bit_0_c == Data_out_1bit_0_e) checker[1] = 1;
		else checker[1] = 0;

		if (Data_out_1bit_1_c == Data_out_1bit_1_e) checker[0] = 1;
		else checker[0] = 0;
	end
endmodule
module probador_phy_tx (
	output reg clk_32f,
	output reg clk_2f,
	output reg clk_4f,
	output reg reset,
	output reg valid_in,
	output reg [31:0] Data_in,
	input  Data_out_1bit_0_c,
	input  Data_out_1bit_1_c,
    input  Data_out_1bit_0_e,
	input  Data_out_1bit_1_e
);

	reg [1:0] conteo_4;
	reg [2:0] conteo_2;
	initial begin
		clk_32f = 0;
		clk_4f = 0;
		clk_2f = 0;
		conteo_4 = 'b11;
		conteo_2 = 'b111;
	end 
	always #1 clk_32f = ~clk_32f;

	always @(posedge clk_32f) begin
		case (conteo_4)
			2'b00: conteo_4 <= 2'b01;
			2'b01: conteo_4 <= 2'b10;
			2'b10: conteo_4 <= 2'b11;
			2'b11:
			begin
				conteo_4 <= 2'b00;
				case (clk_4f)
					1'b0: clk_4f <= 1;
					1'b1: clk_4f <= 0;
				endcase
			end 
		endcase
		case (conteo_2)
			3'b000: conteo_2 <= 3'b001;
			3'b001: conteo_2 <= 3'b010;
			3'b010: conteo_2 <= 3'b011;
			3'b011: conteo_2 <= 3'b100;
			3'b100: conteo_2 <= 3'b101;
			3'b101: conteo_2 <= 3'b110;
			3'b110: conteo_2 <= 3'b111;
			3'b111:
			begin
				conteo_2 <= 3'b000;
				case (clk_2f)
					1'b0: clk_2f <= 1;
					1'b1: clk_2f <= 0;
				endcase
			end 
		endcase
	end

	initial begin
		$dumpfile ("prueba_phy_tx.vcd");
		$dumpvars;

		reset <= 0;
		valid_in <= 0;
		Data_in <= 32'b0;

		@(posedge clk_32f);
		reset <= 1;
		valid_in <= 1;
		Data_in <= 'hFFFFFFFF;

		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 'hEEEEEEEE;

		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 'hDDDDDDDD;
        
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 'hCCCCCCCC;
        
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		valid_in <= 0;
		Data_in <= 32'b0;
        
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);

		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);

		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		valid_in <= 1;
		Data_in <= 'h00000003;
        
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 'h00000004;

		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		valid_in <= 0;
		Data_in <= 32'b0;

		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);

		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		valid_in <= 1;
		Data_in <= 'hAAAAAAAA;
        
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 'h99999999;

		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		valid_in <= 0;
		Data_in <= 32'b0;
		
        @(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);

		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		valid_in <= 1;
		Data_in <= 'h00000007;
		
        @(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		Data_in <= 'h00000008;
		
        @(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		valid_in <= 0;
		Data_in <= 32'b0;
		
        @(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		@(posedge clk_32f);
		$finish;
	end




	reg [1:0] checker; 
	always @(*) begin
		if (Data_out_1bit_0_c == Data_out_1bit_0_e) checker[1] = 1;
		else checker[1] = 0;

		if (Data_out_1bit_1_c == Data_out_1bit_1_e) checker[0] = 1;
		else checker[0] = 0;
	end
endmodule