data/full_repos/permissive/439345921/ROM32K_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/439345921/ROM32K_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n always #4 begin\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/439345921/ROM32K_tb.v:26: Cannot find file containing module: \'ROM32K\'\n ROM32K ROM32K_inst (\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/439345921,data/full_repos/permissive/439345921/ROM32K\n             data/full_repos/permissive/439345921,data/full_repos/permissive/439345921/ROM32K.v\n             data/full_repos/permissive/439345921,data/full_repos/permissive/439345921/ROM32K.sv\n             ROM32K\n             ROM32K.v\n             ROM32K.sv\n             obj_dir/ROM32K\n             obj_dir/ROM32K.v\n             obj_dir/ROM32K.sv\n%Warning-WIDTH: data/full_repos/permissive/439345921/ROM32K_tb.v:65: Operator ADD expects 16 bits on the RHS, but RHS\'s CONST \'6\'h1\' generates 6 bits.\n                                                                   : ... In instance ROM32K_tb\n    srom_data <= srom_data + 6\'d1;\n                           ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ROM32K_tb();

	reg clk_srom;
	reg rst_n;
	reg [14:0] address;
	wire srom_do;
	reg [5:0] count;
	reg stage;
	reg [15:0] srom_data;


	wire ready;
	wire [15:0] data;
	wire srom_cs_n;
	wire srom_sck;
	wire srom_di;
	wire [14:0] sram_address;
	wire sram_ce_n;
	wire sram_oe_n;
	wire sram_we_n;


	wire [15:0] sram_dio;
	
	ROM32K ROM32K_inst (
		.clk_srom(clk_srom),
		.rst_n(rst_n),
		.ready(ready),
		.address(pc),
		.data(instruction),
		.srom_cs_n(srom_cs_n),
		.srom_sck(srom_sck),
		.srom_di(srom_di),
		.srom_do(srom_do),
		.sram_address(sram_address),
		.sram_dio(sram_dio),
		.sram_ce_n(sram_ce_n),
		.sram_oe_n(sram_oe_n),
		.sram_we_n(sram_we_n)
	);

	initial begin
		clk_srom = 0;
		rst_n = 1;
		address = 15'd0;
		count = 6'd0;
		stage = 0;
		srom_data = 16'd1001;
	end
	
	always #4 begin
		clk_srom = ~clk_srom;
	end

	always @(negedge clk_srom) begin
		if (stage == 0) begin
			if (count == 6'd41) begin
				count <= 6'd0;
				stage <= 1;
			end else count <= count + 1;
		end else begin
			if (count == 6'd15) begin
				count <= 0;
				srom_data <= srom_data + 6'd1;
			end else count <= count + 1;
		end
	end
	
	assign srom_do = srom_data[15 - count];

endmodule
module ROM32K_tb();


	reg clk_srom;
	reg rst_n;
	reg [14:0] address;
	wire srom_do;
	reg [5:0] count;
	reg stage;
	reg [15:0] srom_data;


	wire ready;
	wire [15:0] data;
	wire srom_cs_n;
	wire srom_sck;
	wire srom_di;
	wire [14:0] sram_address;
	wire sram_ce_n;
	wire sram_oe_n;
	wire sram_we_n;


	wire [15:0] sram_dio;
	
	ROM32K ROM32K_inst (
		.clk_srom(clk_srom),
		.rst_n(rst_n),
		.ready(ready),
		.address(pc),
		.data(instruction),
		.srom_cs_n(srom_cs_n),
		.srom_sck(srom_sck),
		.srom_di(srom_di),
		.srom_do(srom_do),
		.sram_address(sram_address),
		.sram_dio(sram_dio),
		.sram_ce_n(sram_ce_n),
		.sram_oe_n(sram_oe_n),
		.sram_we_n(sram_we_n)
	);

	initial begin
		clk_srom = 0;
		rst_n = 1;
		address = 15'd0;
		count = 6'd0;
		stage = 0;
		srom_data = 16'd1001;
	end
	
	always #4 begin
		clk_srom = ~clk_srom;
	end

	always @(negedge clk_srom) begin
		if (stage == 0) begin
			if (count == 6'd41) begin
				count <= 6'd0;
				stage <= 1;
			end else count <= count + 1;
		end else begin
			if (count == 6'd15) begin
				count <= 0;
				srom_data <= srom_data + 6'd1;
			end else count <= count + 1;
		end
	end
	
	assign srom_do = srom_data[15 - count];

endmodule