data/full_repos/permissive/427048176/verilog/dv/parallax_test/parallax_test_tb.v
1: b'%Error: data/full_repos/permissive/427048176/verilog/dv/parallax_test/parallax_test_tb.v:20: Cannot find include file: uprj_netlists.v\n`include "uprj_netlists.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/427048176/verilog/dv/parallax_test,data/full_repos/permissive/427048176/uprj_netlists.v\n             data/full_repos/permissive/427048176/verilog/dv/parallax_test,data/full_repos/permissive/427048176/uprj_netlists.v.v\n             data/full_repos/permissive/427048176/verilog/dv/parallax_test,data/full_repos/permissive/427048176/uprj_netlists.v.sv\n             uprj_netlists.v\n             uprj_netlists.v.v\n             uprj_netlists.v.sv\n             obj_dir/uprj_netlists.v\n             obj_dir/uprj_netlists.v.v\n             obj_dir/uprj_netlists.v.sv\n%Error: data/full_repos/permissive/427048176/verilog/dv/parallax_test/parallax_test_tb.v:21: Cannot find include file: caravel_netlists.v\n`include "caravel_netlists.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427048176/verilog/dv/parallax_test/parallax_test_tb.v:22: Cannot find include file: spiflash.v\n`include "spiflash.v" \n         ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/427048176/verilog/dv/parallax_test/parallax_test_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n always #12.5 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/427048176/verilog/dv/parallax_test/parallax_test_tb.v:48: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("parallax_test.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/427048176/verilog/dv/parallax_test/parallax_test_tb.v:49: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, parallax_test_tb);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/427048176/verilog/dv/parallax_test/parallax_test_tb.v:63: syntax error, unexpected \'@\'\n    repeat (832*10) @(posedge clock);\n                    ^\n%Error: data/full_repos/permissive/427048176/verilog/dv/parallax_test/parallax_test_tb.v:88: Unsupported: wait statements\n  wait(hsync == 1);\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/427048176/verilog/dv/parallax_test/parallax_test_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/427048176/verilog/dv/parallax_test/parallax_test_tb.v:98: Unsupported: wait statements\n    wait(hsync == 0);\n    ^~~~\n%Error: data/full_repos/permissive/427048176/verilog/dv/parallax_test/parallax_test_tb.v:99: Unsupported: wait statements\n    wait(hsync == 1);\n    ^~~~\n%Error: data/full_repos/permissive/427048176/verilog/dv/parallax_test/parallax_test_tb.v:106: Unsupported: wait statements\n   #1 wait(vsync == 0);\n      ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/427048176/verilog/dv/parallax_test/parallax_test_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n   #1 wait(vsync == 0);\n   ^\n%Error: data/full_repos/permissive/427048176/verilog/dv/parallax_test/parallax_test_tb.v:109: Unsupported: wait statements\n    wait(hsync == 0);\n    ^~~~\n%Error: data/full_repos/permissive/427048176/verilog/dv/parallax_test/parallax_test_tb.v:110: Unsupported: wait statements\n    wait(hsync == 1);\n    ^~~~\n%Error: data/full_repos/permissive/427048176/verilog/dv/parallax_test/parallax_test_tb.v:115: Unsupported: wait statements\n   #1 wait(vsync == 1);\n      ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/427048176/verilog/dv/parallax_test/parallax_test_tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n   #1 wait(vsync == 1);\n   ^\n%Error: data/full_repos/permissive/427048176/verilog/dv/parallax_test/parallax_test_tb.v:119: Unsupported: wait statements\n    wait(hsync == 0);\n    ^~~~\n%Error: data/full_repos/permissive/427048176/verilog/dv/parallax_test/parallax_test_tb.v:120: Unsupported: wait statements\n    wait(hsync == 1);\n    ^~~~\n%Error: data/full_repos/permissive/427048176/verilog/dv/parallax_test/parallax_test_tb.v:129: Unsupported: wait statements\n    wait(hsync == 0);\n    ^~~~\n%Error: data/full_repos/permissive/427048176/verilog/dv/parallax_test/parallax_test_tb.v:130: Unsupported: wait statements\n    wait(hsync == 1);\n    ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/427048176/verilog/dv/parallax_test/parallax_test_tb.v:148: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/427048176/verilog/dv/parallax_test/parallax_test_tb.v:156: Unsupported: Ignoring delay on this delayed statement.\n  #8;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/427048176/verilog/dv/parallax_test/parallax_test_tb.v:158: Unsupported: Ignoring delay on this delayed statement.\n  #8;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/427048176/verilog/dv/parallax_test/parallax_test_tb.v:160: Unsupported: Ignoring delay on this delayed statement.\n  #8;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/427048176/verilog/dv/parallax_test/parallax_test_tb.v:162: Unsupported: Ignoring delay on this delayed statement.\n  #8;\n  ^\n%Error: Exiting due to 17 error(s), 9 warning(s)\n'
module parallax_test_tb;
	reg clock;
	reg RSTB;

	reg power1, power2, power3, power4;

	wire gpio;
	wire [37:0] mprj_io;

	wire hsync;
	wire vsync;
	wire [2:0] rgb;

	assign hsync = mprj_io[8];
	assign vsync = mprj_io[9];
	assign rgb = mprj_io[12:10];

	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
	end

	initial begin
		$dumpfile("parallax_test.vcd");
		$dumpvars(0, parallax_test_tb);











		repeat (3) begin
			repeat (52) begin
				repeat (832*10) @(posedge clock);
				$display("8320 cycles passed (10 lines x 832 pixel clocks)");
			end
			$display("frame passed");
		end

		$display("%c[1;31m",27);
		`ifdef GL
			$display ("Monitor: Timeout, VGA signal (GL) Failed");
		`else
			$display ("Monitor: Timeout, VGA signal (RTL) Failed");
		`endif
		$display("%c[0m",27);
		$finish;
	end









	initial begin
		wait(hsync == 1);
		#1;
		repeat (2) begin
			if (hsync != 1 ||
				vsync != 1 ||
				rgb != 0) $display("000 failed! mprj_io=%b", mprj_io);
			$display("Vertical retrace started");


			repeat (9) begin
				wait(hsync == 0);
				wait(hsync == 1);
				if (vsync != 1 ||
					rgb != 0) $display("001 failed! mprj_io=%b", mprj_io);
				$display("VBLANK FRONT porch line started");
			end


			#1 wait(vsync == 0);
			$display("Vertical sync period started");
			repeat (3) begin
				wait(hsync == 0);
				wait(hsync == 1);
				if (vsync != 0 ||
					rgb != 0) $display("002 failed! mprj_io=%b", mprj_io);
				$display("VSYNC line started");
			end
			#1 wait(vsync == 1);


			repeat (28) begin
				wait(hsync == 0);
				wait(hsync == 1);
				if (vsync != 1 ||
					rgb != 0) $display("003 failed! mprj_io=%b", mprj_io);
				$display("VBLANK BACK porch line started");
			end


			$display("Visible portion of the frame started");
			repeat (480) begin
				wait(hsync == 0);
				wait(hsync == 1);
				if (vsync != 1) $display("004 failed! mprj_io=%b", mprj_io);
				$display("ACTIVE line started");
			end

			$display("Frame ended");
		end

		`ifdef GL
		$display("Monitor: VGA signal (GL) Passed");
		`else
		$display("Monitor: VGA signal (RTL) Passed");
		`endif
		$finish;
	end

	initial begin
		RSTB <= 1'b0;
		#100;
		RSTB <= 1'b1;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;

		#8;
		power1 <= 1'b1;
		#8;
		power2 <= 1'b1;
		#8;
		power3 <= 1'b1;
		#8;
		power4 <= 1'b1;
	end

    wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD1V8;
    wire VDD3V3;
	wire VSS;

	assign VDD3V3 = power1;
	assign VDD1V8 = power2;
	assign VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vssio	  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock	  (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("parallax_test.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule
module parallax_test_tb;

	reg clock;
	reg RSTB;

	reg power1, power2, power3, power4;

	wire gpio;
	wire [37:0] mprj_io;

	wire hsync;
	wire vsync;
	wire [2:0] rgb;

	assign hsync = mprj_io[8];
	assign vsync = mprj_io[9];
	assign rgb = mprj_io[12:10];

	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
	end

	initial begin
		$dumpfile("parallax_test.vcd");
		$dumpvars(0, parallax_test_tb);











		repeat (3) begin
			repeat (52) begin
				repeat (832*10) @(posedge clock);
				$display("8320 cycles passed (10 lines x 832 pixel clocks)");
			end
			$display("frame passed");
		end

		$display("%c[1;31m",27);
		`ifdef GL
			$display ("Monitor: Timeout, VGA signal (GL) Failed");
		`else
			$display ("Monitor: Timeout, VGA signal (RTL) Failed");
		`endif
		$display("%c[0m",27);
		$finish;
	end









	initial begin
		wait(hsync == 1);
		#1;
		repeat (2) begin
			if (hsync != 1 ||
				vsync != 1 ||
				rgb != 0) $display("000 failed! mprj_io=%b", mprj_io);
			$display("Vertical retrace started");


			repeat (9) begin
				wait(hsync == 0);
				wait(hsync == 1);
				if (vsync != 1 ||
					rgb != 0) $display("001 failed! mprj_io=%b", mprj_io);
				$display("VBLANK FRONT porch line started");
			end


			#1 wait(vsync == 0);
			$display("Vertical sync period started");
			repeat (3) begin
				wait(hsync == 0);
				wait(hsync == 1);
				if (vsync != 0 ||
					rgb != 0) $display("002 failed! mprj_io=%b", mprj_io);
				$display("VSYNC line started");
			end
			#1 wait(vsync == 1);


			repeat (28) begin
				wait(hsync == 0);
				wait(hsync == 1);
				if (vsync != 1 ||
					rgb != 0) $display("003 failed! mprj_io=%b", mprj_io);
				$display("VBLANK BACK porch line started");
			end


			$display("Visible portion of the frame started");
			repeat (480) begin
				wait(hsync == 0);
				wait(hsync == 1);
				if (vsync != 1) $display("004 failed! mprj_io=%b", mprj_io);
				$display("ACTIVE line started");
			end

			$display("Frame ended");
		end

		`ifdef GL
		$display("Monitor: VGA signal (GL) Passed");
		`else
		$display("Monitor: VGA signal (RTL) Passed");
		`endif
		$finish;
	end

	initial begin
		RSTB <= 1'b0;
		#100;
		RSTB <= 1'b1;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;

		#8;
		power1 <= 1'b1;
		#8;
		power2 <= 1'b1;
		#8;
		power3 <= 1'b1;
		#8;
		power4 <= 1'b1;
	end

    wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD1V8;
    wire VDD3V3;
	wire VSS;

	assign VDD3V3 = power1;
	assign VDD1V8 = power2;
	assign VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vssio	  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock	  (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("parallax_test.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule