data/full_repos/permissive/527193964/sim/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/527193964/sim/tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n  forever #10 tck = ~tck;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/527193964/sim/tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/527193964/sim/tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/527193964/sim/tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/527193964/sim/tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n      #20; \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/527193964/sim/tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n   #20;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/527193964/sim/tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/527193964/sim/tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n   #20;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/527193964/sim/tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/527193964/sim/tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/527193964/sim/tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n   #20;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/527193964/sim/tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/527193964/sim/tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/527193964/sim/tb.v:96: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/527193964/sim/tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n      #20; \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/527193964/sim/tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n   #20;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/527193964/sim/tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/527193964/sim/tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n   #20;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/527193964/sim/tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/527193964/sim/tb.v:111: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/527193964/sim/tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/527193964/sim/tb.v:41: Cannot find file containing module: \'tap_controller\'\n tap_controller uut (\n ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/527193964/sim,data/full_repos/permissive/527193964/tap_controller\n             data/full_repos/permissive/527193964/sim,data/full_repos/permissive/527193964/tap_controller.v\n             data/full_repos/permissive/527193964/sim,data/full_repos/permissive/527193964/tap_controller.sv\n             tap_controller\n             tap_controller.v\n             tap_controller.sv\n             obj_dir/tap_controller\n             obj_dir/tap_controller.v\n             obj_dir/tap_controller.sv\n%Error: Exiting due to 1 error(s), 21 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tap_controler_asm_tb;


	reg tck;
	reg tms;
	reg trst;


	wire cdr1;
	wire sdr1;
	wire udr1;
	wire cir1;
	wire sir1;
	wire uir1;


	tap_controller uut (
		.tck(tck), 
		.tms(tms), 
		.trst(trst), 
		.cdr1(cdr1), 
		.sdr1(sdr1), 
		.udr1(udr1), 
		.cir1(cir1), 
		.sir1(sir1), 
		.uir1(uir1)
	);

	


initial begin

		tck = 0;
		forever #10 tck = ~tck;
end

initial begin


		tms = 0;
		trst = 0;
		#20;

		trst = 1;
#20;
		tms = 1;
		
	   #20;
	   tms = 0;
      #20;	
     tms = 0;
	  #20;
	   tms = 0;
		#20;
		tms = 1;
	  #20;
	   tms = 1;
		
		#20;
		tms=0;
		#20;
		tms = 1;
	  #20;
	   tms = 1;
		#20
		
		tms = 0;
		#20;

		tms = 1;
	   #10;
	   tms = 0;
      #20;	
     tms = 0;
	  #20;
	   tms = 0;
		#20;
		tms = 1;
	  #20;
	   tms = 1;
		#20;
		
		

		tms=1;
		#100;
		tms=0;
		
	


		#100;
        


	end
      
endmodule
module tap_controler_asm_tb;



	reg tck;
	reg tms;
	reg trst;


	wire cdr1;
	wire sdr1;
	wire udr1;
	wire cir1;
	wire sir1;
	wire uir1;


	tap_controller uut (
		.tck(tck), 
		.tms(tms), 
		.trst(trst), 
		.cdr1(cdr1), 
		.sdr1(sdr1), 
		.udr1(udr1), 
		.cir1(cir1), 
		.sir1(sir1), 
		.uir1(uir1)
	);

	


initial begin

		tck = 0;
		forever #10 tck = ~tck;
end

initial begin


		tms = 0;
		trst = 0;
		#20;

		trst = 1;
#20;
		tms = 1;
		
	   #20;
	   tms = 0;
      #20;	
     tms = 0;
	  #20;
	   tms = 0;
		#20;
		tms = 1;
	  #20;
	   tms = 1;
		
		#20;
		tms=0;
		#20;
		tms = 1;
	  #20;
	   tms = 1;
		#20
		
		tms = 0;
		#20;

		tms = 1;
	   #10;
	   tms = 0;
      #20;	
     tms = 0;
	  #20;
	   tms = 0;
		#20;
		tms = 1;
	  #20;
	   tms = 1;
		#20;
		
		

		tms=1;
		#100;
		tms=0;
		
	


		#100;
        


	end
      
endmodule