data/full_repos/permissive/503509790/verilog/rtl/list_ch08_04_uart.v
1: b"%Error: data/full_repos/permissive/503509790/verilog/rtl/list_ch08_04_uart.v:33: Cannot find file containing module: 'mod_m_counter'\n   mod_m_counter #(.N(DVSR_BIT)) baud_gen_unit\n   ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/503509790/verilog/rtl,data/full_repos/permissive/503509790/mod_m_counter\n             data/full_repos/permissive/503509790/verilog/rtl,data/full_repos/permissive/503509790/mod_m_counter.v\n             data/full_repos/permissive/503509790/verilog/rtl,data/full_repos/permissive/503509790/mod_m_counter.sv\n             mod_m_counter\n             mod_m_counter.v\n             mod_m_counter.sv\n             obj_dir/mod_m_counter\n             obj_dir/mod_m_counter.v\n             obj_dir/mod_m_counter.sv\n%Error: data/full_repos/permissive/503509790/verilog/rtl/list_ch08_04_uart.v:36: Cannot find file containing module: 'uart_rx'\n   uart_rx #(.DBIT(DBIT), .SB_TICK(SB_TICK)) uart_rx_unit\n   ^~~~~~~\n%Error: data/full_repos/permissive/503509790/verilog/rtl/list_ch08_04_uart.v:40: Cannot find file containing module: 'fifo'\n   fifo #(.B(DBIT), .W(FIFO_W)) fifo_rx_unit\n   ^~~~\n%Error: data/full_repos/permissive/503509790/verilog/rtl/list_ch08_04_uart.v:45: Cannot find file containing module: 'fifo'\n   fifo #(.B(DBIT), .W(FIFO_W)) fifo_tx_unit\n   ^~~~\n%Error: data/full_repos/permissive/503509790/verilog/rtl/list_ch08_04_uart.v:50: Cannot find file containing module: 'uart_tx'\n   uart_tx #(.DBIT(DBIT), .SB_TICK(SB_TICK)) uart_tx_unit\n   ^~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module uart
   #(

      parameter DBIT = 8,
                SB_TICK = 16,

                DVSR_BIT = 8,
                FIFO_W = 4

   )
   (
   `ifdef USE_POWER_PINS
      inout vccd1,
      inout vssd1,
   `endif
    input wire clk, reset,
    input wire [DVSR_BIT - 1:0] dvsr,

    input rx_fifo_flush_enable,
    input wire rd_uart, wr_uart, rx,
    input wire [7:0] w_data,
    output wire tx_full, rx_empty, tx,
    output wire [7:0] r_data
   );


   wire tick, rx_done_tick, tx_done_tick;
   wire tx_empty, tx_fifo_not_empty;
   wire [7:0] tx_fifo_out, rx_data_out;


   mod_m_counter #(.N(DVSR_BIT)) baud_gen_unit
      (.clk(clk), .dvsr(dvsr), .reset(reset), .q(), .max_tick(tick));

   uart_rx #(.DBIT(DBIT), .SB_TICK(SB_TICK)) uart_rx_unit
      (.clk(clk), .reset(reset), .rx(rx), .s_tick(tick),
       .rx_done_tick(rx_done_tick), .dout(rx_data_out));

   fifo #(.B(DBIT), .W(FIFO_W)) fifo_rx_unit
      (.clk(clk), .reset(reset), .flush_enable(rx_fifo_flush_enable), .rd(rd_uart),
       .wr(rx_done_tick), .w_data(rx_data_out),
       .empty(rx_empty), .full(), .r_data(r_data));

   fifo #(.B(DBIT), .W(FIFO_W)) fifo_tx_unit
      (.clk(clk), .reset(reset), .rd(tx_done_tick), .flush_enable(0),
       .wr(wr_uart), .w_data(w_data), .empty(tx_empty),
       .full(tx_full), .r_data(tx_fifo_out));

   uart_tx #(.DBIT(DBIT), .SB_TICK(SB_TICK)) uart_tx_unit
      (.clk(clk), .reset(reset), .tx_start(tx_fifo_not_empty),
       .s_tick(tick), .din(tx_fifo_out),
       .tx_done_tick(tx_done_tick), .tx(tx));

   assign tx_fifo_not_empty = ~tx_empty;

endmodule
module uart
   #(

      parameter DBIT = 8,
                SB_TICK = 16,

                DVSR_BIT = 8,
                FIFO_W = 4

   )
   (
   `ifdef USE_POWER_PINS
      inout vccd1,
      inout vssd1,
   `endif
    input wire clk, reset,
    input wire [DVSR_BIT - 1:0] dvsr,

    input rx_fifo_flush_enable,
    input wire rd_uart, wr_uart, rx,
    input wire [7:0] w_data,
    output wire tx_full, rx_empty, tx,
    output wire [7:0] r_data
   );



   wire tick, rx_done_tick, tx_done_tick;
   wire tx_empty, tx_fifo_not_empty;
   wire [7:0] tx_fifo_out, rx_data_out;


   mod_m_counter #(.N(DVSR_BIT)) baud_gen_unit
      (.clk(clk), .dvsr(dvsr), .reset(reset), .q(), .max_tick(tick));

   uart_rx #(.DBIT(DBIT), .SB_TICK(SB_TICK)) uart_rx_unit
      (.clk(clk), .reset(reset), .rx(rx), .s_tick(tick),
       .rx_done_tick(rx_done_tick), .dout(rx_data_out));

   fifo #(.B(DBIT), .W(FIFO_W)) fifo_rx_unit
      (.clk(clk), .reset(reset), .flush_enable(rx_fifo_flush_enable), .rd(rd_uart),
       .wr(rx_done_tick), .w_data(rx_data_out),
       .empty(rx_empty), .full(), .r_data(r_data));

   fifo #(.B(DBIT), .W(FIFO_W)) fifo_tx_unit
      (.clk(clk), .reset(reset), .rd(tx_done_tick), .flush_enable(0),
       .wr(wr_uart), .w_data(w_data), .empty(tx_empty),
       .full(tx_full), .r_data(tx_fifo_out));

   uart_tx #(.DBIT(DBIT), .SB_TICK(SB_TICK)) uart_tx_unit
      (.clk(clk), .reset(reset), .tx_start(tx_fifo_not_empty),
       .s_tick(tick), .din(tx_fifo_out),
       .tx_done_tick(tx_done_tick), .tx(tx));

   assign tx_fifo_not_empty = ~tx_empty;

endmodule