data/full_repos/permissive/430434698/board_level_data_receiver_physical.v
1: b"%Error: data/full_repos/permissive/430434698/board_level_data_receiver_physical.v:63: Cannot find file containing module: 'reset_sync'\n    reset_sync #(\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/430434698,data/full_repos/permissive/430434698/reset_sync\n             data/full_repos/permissive/430434698,data/full_repos/permissive/430434698/reset_sync.v\n             data/full_repos/permissive/430434698,data/full_repos/permissive/430434698/reset_sync.sv\n             reset_sync\n             reset_sync.v\n             reset_sync.sv\n             obj_dir/reset_sync\n             obj_dir/reset_sync.v\n             obj_dir/reset_sync.sv\n%Error: data/full_repos/permissive/430434698/board_level_data_receiver_physical.v:77: Cannot find file containing module: 'bits_synchronizer'\n    bits_synchronizer #(\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430434698/board_level_data_receiver_physical.v:120: Cannot find file containing module: 'board_level_data_receiver_physical_buffer'\n    board_level_data_receiver_physical_buffer board_level_data_receiver_physical_buffer_inst(\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430434698/board_level_data_receiver_physical.v:133: Cannot find file containing module: 'board_level_data_physical_decoder'\n    board_level_data_physical_decoder board_level_data_physical_decoder_inst(\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module board_level_data_receiver_physical(
        input clk,
        input rst,
        input rev_clk,
        input serial_data,
        output frame_start,
        output frame_end,
        output [5:0] data,
        output valid
    );

    wire rev_clk_rst;

    (* IOB = "TRUE" *)reg serial_data_iob_sync;


    wire serial_data_sync;


    reg [7:0] rev_buffer;
    wire rev_frame_start;

    reg [2:0] rev_cnt;
    wire [3:0] next_rev_cnt;

    wire [7:0] raw_data;
    wire raw_valid;

    reset_sync #(
        .RESET_IN_ACTIVE_LEVEL(1'b1),
        .RESET_OUT_ACTIVE_LEVEL(1'b1),
        .RESET_SYNC_STAGE(3)
    )reset_sync_inst(
        .clk(rev_clk),
        .rst_in(rst),
        .rst_out(rev_clk_rst)
    );

    always @(posedge rev_clk) begin
        serial_data_iob_sync <= serial_data;
    end

    bits_synchronizer #(
        .STAGE(3), 
        .BITS(1), 
        .DEFAULT_LEVEL(1'b0)
    )serial_data_sync_inst(
        .clk(rev_clk), 
        .rst(rst), 
        .din(serial_data_iob_sync), 
        .dout(serial_data_sync)
    );


    always @(posedge rev_clk) begin
        if(rev_clk_rst) begin
            rev_buffer <= 8'b0;
        end
        else begin
            rev_buffer <= {rev_buffer[6:0], serial_data_sync};
        end
    end


    assign rev_frame_start = (~(|rev_buffer[7:1])) & rev_buffer[0];


    assign next_rev_cnt = rev_cnt + 3'b1;

    always @(posedge rev_clk) begin
        if(rev_clk_rst) begin
            rev_cnt <= 3'b0;
        end
        else if(rev_frame_start) begin
            rev_cnt <= 3'b0;
        end
        else if(rev_cnt == 3'd7) begin
            rev_cnt <= 3'b0;
        end
        else begin
            rev_cnt <= next_rev_cnt[2:0];
        end
    end


    board_level_data_receiver_physical_buffer board_level_data_receiver_physical_buffer_inst(
        .rst(rst),
        .wr_clk(rev_clk),
        .rd_clk(clk),
        .din(rev_buffer),
        .wr_en((rev_cnt == 3'd7) | rev_frame_start),
        .rd_en(1'b1),
        .dout(raw_data),
        .full(),
        .empty(),
        .valid(raw_valid)
    );

    board_level_data_physical_decoder board_level_data_physical_decoder_inst(
        .clk(clk),
        .rst(rst),
        .raw_data(raw_data),
        .raw_data_valid(raw_valid),
        .frame_start(frame_start),
        .frame_end(frame_end),
        .decoded_data(data),
        .decoded_data_valid(valid)
    );


endmodule
module board_level_data_receiver_physical(
        input clk,
        input rst,
        input rev_clk,
        input serial_data,
        output frame_start,
        output frame_end,
        output [5:0] data,
        output valid
    );


    wire rev_clk_rst;

    (* IOB = "TRUE" *)reg serial_data_iob_sync;


    wire serial_data_sync;


    reg [7:0] rev_buffer;
    wire rev_frame_start;

    reg [2:0] rev_cnt;
    wire [3:0] next_rev_cnt;

    wire [7:0] raw_data;
    wire raw_valid;

    reset_sync #(
        .RESET_IN_ACTIVE_LEVEL(1'b1),
        .RESET_OUT_ACTIVE_LEVEL(1'b1),
        .RESET_SYNC_STAGE(3)
    )reset_sync_inst(
        .clk(rev_clk),
        .rst_in(rst),
        .rst_out(rev_clk_rst)
    );

    always @(posedge rev_clk) begin
        serial_data_iob_sync <= serial_data;
    end

    bits_synchronizer #(
        .STAGE(3), 
        .BITS(1), 
        .DEFAULT_LEVEL(1'b0)
    )serial_data_sync_inst(
        .clk(rev_clk), 
        .rst(rst), 
        .din(serial_data_iob_sync), 
        .dout(serial_data_sync)
    );


    always @(posedge rev_clk) begin
        if(rev_clk_rst) begin
            rev_buffer <= 8'b0;
        end
        else begin
            rev_buffer <= {rev_buffer[6:0], serial_data_sync};
        end
    end


    assign rev_frame_start = (~(|rev_buffer[7:1])) & rev_buffer[0];


    assign next_rev_cnt = rev_cnt + 3'b1;

    always @(posedge rev_clk) begin
        if(rev_clk_rst) begin
            rev_cnt <= 3'b0;
        end
        else if(rev_frame_start) begin
            rev_cnt <= 3'b0;
        end
        else if(rev_cnt == 3'd7) begin
            rev_cnt <= 3'b0;
        end
        else begin
            rev_cnt <= next_rev_cnt[2:0];
        end
    end


    board_level_data_receiver_physical_buffer board_level_data_receiver_physical_buffer_inst(
        .rst(rst),
        .wr_clk(rev_clk),
        .rd_clk(clk),
        .din(rev_buffer),
        .wr_en((rev_cnt == 3'd7) | rev_frame_start),
        .rd_en(1'b1),
        .dout(raw_data),
        .full(),
        .empty(),
        .valid(raw_valid)
    );

    board_level_data_physical_decoder board_level_data_physical_decoder_inst(
        .clk(clk),
        .rst(rst),
        .raw_data(raw_data),
        .raw_data_valid(raw_valid),
        .frame_start(frame_start),
        .frame_end(frame_end),
        .decoded_data(data),
        .decoded_data_valid(valid)
    );


endmodule