data/full_repos/permissive/486367830/hdl/comp_mult_top.v
1: b'%Error: data/full_repos/permissive/486367830/hdl/comp_mult_top.v:116: Cannot find file containing module: \'comp_mult_wrapper\'\ncomp_mult_wrapper #(\n^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/486367830/hdl,data/full_repos/permissive/486367830/comp_mult_wrapper\n             data/full_repos/permissive/486367830/hdl,data/full_repos/permissive/486367830/comp_mult_wrapper.v\n             data/full_repos/permissive/486367830/hdl,data/full_repos/permissive/486367830/comp_mult_wrapper.sv\n             comp_mult_wrapper\n             comp_mult_wrapper.v\n             comp_mult_wrapper.sv\n             obj_dir/comp_mult_wrapper\n             obj_dir/comp_mult_wrapper.v\n             obj_dir/comp_mult_wrapper.sv\n%Warning-WIDTH: data/full_repos/permissive/486367830/hdl/comp_mult_top.v:307: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'byte_cnt\' generates 3 bits.\n                                                                            : ... In instance comp_mult_top\n        if(byte_cnt < 3\'d2) mem_addr = op1_addr + byte_cnt       ; else  \n                                                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/486367830/hdl/comp_mult_top.v:308: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'byte_cnt\' generates 3 bits.\n                                                                            : ... In instance comp_mult_top\n                            mem_addr = op2_addr + byte_cnt - \'d2 ;       \n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/486367830/hdl/comp_mult_top.v:310: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'byte_cnt\' generates 3 bits.\n                                                                            : ... In instance comp_mult_top\n                            mem_addr = res_addr + byte_cnt;              \n                                                ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module comp_mult_top #(
parameter NO_MULT   = 4     ,
parameter APB_BADDR = 0     ,
parameter SYS_AW    = 16    ,
parameter REG_DW    = 16
)(
input                    clk         ,
input                    rst_n       ,
       

input      [ SYS_AW-1:0] apb_paddr   ,
input                    apb_psel    ,
input                    apb_penable ,
input                    apb_pwrite  ,
input      [REG_DW -1:0] apb_pwdata  ,
output                   apb_pready  ,
output reg [REG_DW -1:0] apb_prdata  ,
output reg               apb_pslverr ,
     





                                     

output reg               mem_ce      ,
output reg               mem_we      ,
output reg [SYS_AW -1:0] mem_addr    ,
output reg [     8 -1:0] mem_wr_data ,
input      [     8 -1:0] mem_rd_data
);




localparam DWIDTH = 8 ;


localparam IDLE   = 2'b00;
localparam RD_OPS = 2'b01;
localparam WORK   = 2'b10;
localparam WR_RES = 2'b11;





reg  [       REG_DW -1:0] op1_addr      ;
reg  [       REG_DW -1:0] op2_addr      ;
reg  [       REG_DW -1:0] res_addr      ;
reg  [       REG_DW -1:0] no_op         ;
reg  [       REG_DW -1:0] cfg_start     ;
reg  [       REG_DW -1:0] sts_stop      ;
             

wire                      wr_op1_addr   ;
wire                      wr_op2_addr   ;
wire                      wr_res_addr   ;
wire                      wr_no_op      ;
wire                      wr_cfg_start  ;
wire                      wr_sts_stop   ;

wire                      rd_sts_stop   ;
wire                      rd_sts_state  ;

wire                      sel_regs      ;
                          

reg                       op_val        ;
wire                      op_rdy        ;
wire [   2*2*DWIDTH -1:0] op_data       ;
wire                      res_val       ;
reg                       res_rdy       ;
wire [2*2*(DWIDTH+1)-1:0] res_data      ;

wire                      set_res_rdy   ;

reg  [     3*DWIDTH -1:0] data_reg      ;


reg  [            2 -1:0] sts_cstate    ;

wire                      start         ;
wire                      sw_rst        ;


wire                      byte_rd_done  ;
wire                      byte_wr_done  ;
wire                      finish        ;
wire                      next_op       ;


reg                       mem_ce_d      ;
reg                       mem_we_d      ;

wire                      set_mem_ce    ;
wire                      set_mem_we    ;

reg  [            3 -1:0] byte_cnt      ;
                          
reg  [       REG_DW -1:0] op_cnt        ;
                          
                       


comp_mult_wrapper #(
.DWIDTH  (DWIDTH  ),
.NO_MULT (NO_MULT )
) i_comp_mult_wrapper (

.clk      (clk     ),
.rst_n    (rst_n   ),
.sw_rst   (sw_rst  ),
.op_val   (op_val  ),
.op_rdy   (op_rdy  ),
.op_data  (op_data ),
.res_val  (res_val ),
.res_rdy  (res_rdy ),
.res_data (res_data)
); 





assign apb_pready = 1'b1;


assign wr_op1_addr  = apb_psel & apb_penable &  apb_pwrite & (apb_paddr == APB_BADDR + 0); 
assign wr_op2_addr  = apb_psel & apb_penable &  apb_pwrite & (apb_paddr == APB_BADDR + 1); 
assign wr_res_addr  = apb_psel & apb_penable &  apb_pwrite & (apb_paddr == APB_BADDR + 2); 
assign wr_no_op     = apb_psel & apb_penable &  apb_pwrite & (apb_paddr == APB_BADDR + 3); 
assign wr_cfg_start = apb_psel & apb_penable &  apb_pwrite & (apb_paddr == APB_BADDR + 4); 
assign wr_sts_stop  = apb_psel & apb_penable &  apb_pwrite & (apb_paddr == APB_BADDR + 5);  

assign rd_sts_stop  = apb_psel & apb_penable & ~apb_pwrite & (apb_paddr == APB_BADDR + 5);  
assign rd_sts_state = apb_psel & apb_penable & ~apb_pwrite & (apb_paddr == APB_BADDR + 6);  



assign sel_regs = wr_op1_addr  |
                  wr_op2_addr  |
                  wr_res_addr  |
                  wr_no_op     |
                  wr_cfg_start |
                  wr_sts_stop  |
                  rd_sts_stop  |
                  rd_sts_state ;
     
     

always @(posedge clk or negedge rst_n)
if(~rst_n)        apb_pslverr <= 'd0         ; else
if(apb_pslverr)   apb_pslverr <= 'd0         ; else
if(apb_penable)   apb_pslverr <= ~sel_regs   ;



always @(posedge clk or negedge rst_n)
if(~rst_n)          op1_addr  <= 'd0            ; else
if(wr_op1_addr)     op1_addr  <= apb_pwdata     ; else
if(byte_rd_done)    op1_addr  <= op1_addr + 'd2 ;


always @(posedge clk or negedge rst_n)
if(~rst_n)          op2_addr  <= 'd0            ; else
if(wr_op2_addr)     op2_addr  <= apb_pwdata     ; else
if(byte_rd_done)    op2_addr  <= op2_addr + 'd2 ;


always @(posedge clk or negedge rst_n)
if(~rst_n)          res_addr  <= 'd0            ; else
if(wr_res_addr)     res_addr  <= apb_pwdata     ; else
if(byte_wr_done)    res_addr  <= res_addr + 'd6 ;


always @(posedge clk or negedge rst_n)
if(~rst_n)          no_op     <= 'd0            ; else
if(wr_no_op)        no_op     <= apb_pwdata     ;
                                                    

always @(posedge clk or negedge rst_n)              
if(~rst_n)          cfg_start <= 'd0            ; else
if(~sw_rst & start) cfg_start <= 'd0            ; else
if(wr_cfg_start)    cfg_start <= apb_pwdata     ;
                                              

always @(posedge clk or negedge rst_n)        
if(~rst_n)          sts_stop  <= 'd0            ; else
if(wr_sts_stop)     sts_stop  <= apb_pwdata     ; else
if(finish)          sts_stop  <= {{REG_DW-1{1'b0}}, 1'b1} ;



always @(posedge clk or negedge rst_n)
if(~rst_n)          apb_prdata <= 'd0                            ; else
if(rd_sts_stop)     apb_prdata <= sts_stop                       ; else
if(rd_sts_state)    apb_prdata <= {{REG_DW-2{1'b0}}, sts_cstate} ;




assign start  = cfg_start[0] & (no_op > 'd0);
assign sw_rst = cfg_start[1];

always @(posedge clk or negedge rst_n)
if(~rst_n) 
    sts_cstate <= IDLE;
else if(sw_rst) 
    sts_cstate <= IDLE; 
else begin 
    case(sts_cstate)
        IDLE    : if(start)
                    sts_cstate <= RD_OPS;   
                  else
                    sts_cstate <= IDLE;
                    
        RD_OPS  : if(byte_rd_done)  
                    sts_cstate <= WORK;
                  else 
                    sts_cstate <= RD_OPS;
                        
        WORK    : if(res_val)
                    sts_cstate <= WR_RES;
                  else 
                    sts_cstate <= WORK;

        default : if(finish) 
                    sts_cstate <= IDLE;
                  else if(next_op)
                    sts_cstate <= RD_OPS;
                  else 
                    sts_cstate <= WR_RES;
    endcase 
end   


assign byte_rd_done = (sts_cstate == RD_OPS) & (byte_cnt == 3'd3);
assign byte_wr_done = (sts_cstate == WR_RES) & (byte_cnt == 3'd5);
assign next_op      = byte_wr_done & (op_cnt != (no_op - 'd1));
assign finish       = byte_wr_done & (op_cnt == (no_op - 'd1));



always @(posedge clk or negedge rst_n)
if(~rst_n)          byte_cnt <= 3'd0            ; else
if(byte_rd_done)    byte_cnt <= 3'd0            ; else
if(byte_wr_done)    byte_cnt <= 3'd0            ; else
if(mem_ce)          byte_cnt <= byte_cnt + 3'd1 ;



always @(posedge clk or negedge rst_n)
if(~rst_n)          op_cnt <= 'd0          ; else
if(finish)          op_cnt <= 'd0          ; else
if(next_op)         op_cnt <= op_cnt + 'd1 ;




always @(posedge clk or negedge rst_n)
if(~rst_n)          op_val <= 1'b0; else
if(byte_rd_done)    op_val <= 1'b1; else
if(op_val & op_rdy) op_val <= 1'b0;



always @(posedge clk or negedge rst_n)
if(~rst_n)          data_reg <= 'd0; else
if(mem_ce_d & ~mem_we_d) begin
    case(byte_cnt)
        3'b001 :    data_reg[3*DWIDTH-1 : 2*DWIDTH] <= mem_rd_data;
        3'b010 :    data_reg[2*DWIDTH-1 : 1*DWIDTH] <= mem_rd_data;
        3'b011 :    data_reg[1*DWIDTH-1 : 0       ] <= mem_rd_data;
        default:    data_reg                        <= data_reg; 
    endcase 
end 


assign op_data = {data_reg, mem_rd_data};


assign set_res_rdy = (sts_cstate == WR_RES) & (byte_cnt == 3'd4);

always @(posedge clk or negedge rst_n)
if(~rst_n)       res_rdy <= 1'b0; else
if(set_res_rdy)  res_rdy <= 1'b1; else
if(byte_wr_done) res_rdy <= 1'b0;






always @(*) 
    if(sts_cstate == RD_OPS)
        if(byte_cnt < 3'd2) mem_addr = op1_addr + byte_cnt       ; else
                            mem_addr = op2_addr + byte_cnt - 'd2 ;
    else
                            mem_addr = res_addr + byte_cnt;





always @(*)
    case(byte_cnt)
        3'b000  : mem_wr_data <= res_data[25:18];
        3'b001  : mem_wr_data <= res_data[33:26];
        3'b010  : mem_wr_data <= {6'd0, res_data[35:34]};
        3'b011  : mem_wr_data <= res_data[ 7:0 ];
        3'b100  : mem_wr_data <= res_data[15:8 ];
        default : mem_wr_data <= {6'd0, res_data[17:16]};
    endcase 



assign set_mem_ce = ((sts_cstate == IDLE)   & start   ) |
                    ((sts_cstate == WR_RES) & next_op ) |
                    ((sts_cstate == WORK)   & res_val ) ;


always @(posedge clk or negedge rst_n)
if(~rst_n)        mem_ce <= 1'b0; else
if(set_mem_ce)    mem_ce <= 1'b1; else
if(byte_rd_done | byte_wr_done) 
                  mem_ce <= 1'b0;



assign set_mem_we = (sts_cstate == WORK) & res_val;

always @(posedge clk or negedge rst_n)
if(~rst_n)        mem_we <= 1'b0; else
if(set_mem_we)    mem_we <= 1'b1; else
if(byte_wr_done)  mem_we <= 1'b0;




always @(posedge clk or negedge rst_n)
if(~rst_n) mem_ce_d <= 1'b0   ; else
if(sw_rst) mem_ce_d <= 1'b0   ; else
           mem_ce_d <= mem_ce ;        
           
           


always @(posedge clk or negedge rst_n)    
if(~rst_n) mem_we_d <= 1'b0   ; else
if(sw_rst) mem_we_d <= 1'b0   ; else
           mem_we_d <= mem_we ;




endmodule
module comp_mult_top #(
parameter NO_MULT   = 4     ,
parameter APB_BADDR = 0     ,
parameter SYS_AW    = 16    ,
parameter REG_DW    = 16
)(
input                    clk         ,
input                    rst_n       ,
       

input      [ SYS_AW-1:0] apb_paddr   ,
input                    apb_psel    ,
input                    apb_penable ,
input                    apb_pwrite  ,
input      [REG_DW -1:0] apb_pwdata  ,
output                   apb_pready  ,
output reg [REG_DW -1:0] apb_prdata  ,
output reg               apb_pslverr ,
     





                                     

output reg               mem_ce      ,
output reg               mem_we      ,
output reg [SYS_AW -1:0] mem_addr    ,
output reg [     8 -1:0] mem_wr_data ,
input      [     8 -1:0] mem_rd_data
);





localparam DWIDTH = 8 ;


localparam IDLE   = 2'b00;
localparam RD_OPS = 2'b01;
localparam WORK   = 2'b10;
localparam WR_RES = 2'b11;





reg  [       REG_DW -1:0] op1_addr      ;
reg  [       REG_DW -1:0] op2_addr      ;
reg  [       REG_DW -1:0] res_addr      ;
reg  [       REG_DW -1:0] no_op         ;
reg  [       REG_DW -1:0] cfg_start     ;
reg  [       REG_DW -1:0] sts_stop      ;
             

wire                      wr_op1_addr   ;
wire                      wr_op2_addr   ;
wire                      wr_res_addr   ;
wire                      wr_no_op      ;
wire                      wr_cfg_start  ;
wire                      wr_sts_stop   ;

wire                      rd_sts_stop   ;
wire                      rd_sts_state  ;

wire                      sel_regs      ;
                          

reg                       op_val        ;
wire                      op_rdy        ;
wire [   2*2*DWIDTH -1:0] op_data       ;
wire                      res_val       ;
reg                       res_rdy       ;
wire [2*2*(DWIDTH+1)-1:0] res_data      ;

wire                      set_res_rdy   ;

reg  [     3*DWIDTH -1:0] data_reg      ;


reg  [            2 -1:0] sts_cstate    ;

wire                      start         ;
wire                      sw_rst        ;


wire                      byte_rd_done  ;
wire                      byte_wr_done  ;
wire                      finish        ;
wire                      next_op       ;


reg                       mem_ce_d      ;
reg                       mem_we_d      ;

wire                      set_mem_ce    ;
wire                      set_mem_we    ;

reg  [            3 -1:0] byte_cnt      ;
                          
reg  [       REG_DW -1:0] op_cnt        ;
                          
                       


comp_mult_wrapper #(
.DWIDTH  (DWIDTH  ),
.NO_MULT (NO_MULT )
) i_comp_mult_wrapper (

.clk      (clk     ),
.rst_n    (rst_n   ),
.sw_rst   (sw_rst  ),
.op_val   (op_val  ),
.op_rdy   (op_rdy  ),
.op_data  (op_data ),
.res_val  (res_val ),
.res_rdy  (res_rdy ),
.res_data (res_data)
); 





assign apb_pready = 1'b1;


assign wr_op1_addr  = apb_psel & apb_penable &  apb_pwrite & (apb_paddr == APB_BADDR + 0); 
assign wr_op2_addr  = apb_psel & apb_penable &  apb_pwrite & (apb_paddr == APB_BADDR + 1); 
assign wr_res_addr  = apb_psel & apb_penable &  apb_pwrite & (apb_paddr == APB_BADDR + 2); 
assign wr_no_op     = apb_psel & apb_penable &  apb_pwrite & (apb_paddr == APB_BADDR + 3); 
assign wr_cfg_start = apb_psel & apb_penable &  apb_pwrite & (apb_paddr == APB_BADDR + 4); 
assign wr_sts_stop  = apb_psel & apb_penable &  apb_pwrite & (apb_paddr == APB_BADDR + 5);  

assign rd_sts_stop  = apb_psel & apb_penable & ~apb_pwrite & (apb_paddr == APB_BADDR + 5);  
assign rd_sts_state = apb_psel & apb_penable & ~apb_pwrite & (apb_paddr == APB_BADDR + 6);  



assign sel_regs = wr_op1_addr  |
                  wr_op2_addr  |
                  wr_res_addr  |
                  wr_no_op     |
                  wr_cfg_start |
                  wr_sts_stop  |
                  rd_sts_stop  |
                  rd_sts_state ;
     
     

always @(posedge clk or negedge rst_n)
if(~rst_n)        apb_pslverr <= 'd0         ; else
if(apb_pslverr)   apb_pslverr <= 'd0         ; else
if(apb_penable)   apb_pslverr <= ~sel_regs   ;



always @(posedge clk or negedge rst_n)
if(~rst_n)          op1_addr  <= 'd0            ; else
if(wr_op1_addr)     op1_addr  <= apb_pwdata     ; else
if(byte_rd_done)    op1_addr  <= op1_addr + 'd2 ;


always @(posedge clk or negedge rst_n)
if(~rst_n)          op2_addr  <= 'd0            ; else
if(wr_op2_addr)     op2_addr  <= apb_pwdata     ; else
if(byte_rd_done)    op2_addr  <= op2_addr + 'd2 ;


always @(posedge clk or negedge rst_n)
if(~rst_n)          res_addr  <= 'd0            ; else
if(wr_res_addr)     res_addr  <= apb_pwdata     ; else
if(byte_wr_done)    res_addr  <= res_addr + 'd6 ;


always @(posedge clk or negedge rst_n)
if(~rst_n)          no_op     <= 'd0            ; else
if(wr_no_op)        no_op     <= apb_pwdata     ;
                                                    

always @(posedge clk or negedge rst_n)              
if(~rst_n)          cfg_start <= 'd0            ; else
if(~sw_rst & start) cfg_start <= 'd0            ; else
if(wr_cfg_start)    cfg_start <= apb_pwdata     ;
                                              

always @(posedge clk or negedge rst_n)        
if(~rst_n)          sts_stop  <= 'd0            ; else
if(wr_sts_stop)     sts_stop  <= apb_pwdata     ; else
if(finish)          sts_stop  <= {{REG_DW-1{1'b0}}, 1'b1} ;



always @(posedge clk or negedge rst_n)
if(~rst_n)          apb_prdata <= 'd0                            ; else
if(rd_sts_stop)     apb_prdata <= sts_stop                       ; else
if(rd_sts_state)    apb_prdata <= {{REG_DW-2{1'b0}}, sts_cstate} ;




assign start  = cfg_start[0] & (no_op > 'd0);
assign sw_rst = cfg_start[1];

always @(posedge clk or negedge rst_n)
if(~rst_n) 
    sts_cstate <= IDLE;
else if(sw_rst) 
    sts_cstate <= IDLE; 
else begin 
    case(sts_cstate)
        IDLE    : if(start)
                    sts_cstate <= RD_OPS;   
                  else
                    sts_cstate <= IDLE;
                    
        RD_OPS  : if(byte_rd_done)  
                    sts_cstate <= WORK;
                  else 
                    sts_cstate <= RD_OPS;
                        
        WORK    : if(res_val)
                    sts_cstate <= WR_RES;
                  else 
                    sts_cstate <= WORK;

        default : if(finish) 
                    sts_cstate <= IDLE;
                  else if(next_op)
                    sts_cstate <= RD_OPS;
                  else 
                    sts_cstate <= WR_RES;
    endcase 
end   


assign byte_rd_done = (sts_cstate == RD_OPS) & (byte_cnt == 3'd3);
assign byte_wr_done = (sts_cstate == WR_RES) & (byte_cnt == 3'd5);
assign next_op      = byte_wr_done & (op_cnt != (no_op - 'd1));
assign finish       = byte_wr_done & (op_cnt == (no_op - 'd1));



always @(posedge clk or negedge rst_n)
if(~rst_n)          byte_cnt <= 3'd0            ; else
if(byte_rd_done)    byte_cnt <= 3'd0            ; else
if(byte_wr_done)    byte_cnt <= 3'd0            ; else
if(mem_ce)          byte_cnt <= byte_cnt + 3'd1 ;



always @(posedge clk or negedge rst_n)
if(~rst_n)          op_cnt <= 'd0          ; else
if(finish)          op_cnt <= 'd0          ; else
if(next_op)         op_cnt <= op_cnt + 'd1 ;




always @(posedge clk or negedge rst_n)
if(~rst_n)          op_val <= 1'b0; else
if(byte_rd_done)    op_val <= 1'b1; else
if(op_val & op_rdy) op_val <= 1'b0;



always @(posedge clk or negedge rst_n)
if(~rst_n)          data_reg <= 'd0; else
if(mem_ce_d & ~mem_we_d) begin
    case(byte_cnt)
        3'b001 :    data_reg[3*DWIDTH-1 : 2*DWIDTH] <= mem_rd_data;
        3'b010 :    data_reg[2*DWIDTH-1 : 1*DWIDTH] <= mem_rd_data;
        3'b011 :    data_reg[1*DWIDTH-1 : 0       ] <= mem_rd_data;
        default:    data_reg                        <= data_reg; 
    endcase 
end 


assign op_data = {data_reg, mem_rd_data};


assign set_res_rdy = (sts_cstate == WR_RES) & (byte_cnt == 3'd4);

always @(posedge clk or negedge rst_n)
if(~rst_n)       res_rdy <= 1'b0; else
if(set_res_rdy)  res_rdy <= 1'b1; else
if(byte_wr_done) res_rdy <= 1'b0;






always @(*) 
    if(sts_cstate == RD_OPS)
        if(byte_cnt < 3'd2) mem_addr = op1_addr + byte_cnt       ; else
                            mem_addr = op2_addr + byte_cnt - 'd2 ;
    else
                            mem_addr = res_addr + byte_cnt;





always @(*)
    case(byte_cnt)
        3'b000  : mem_wr_data <= res_data[25:18];
        3'b001  : mem_wr_data <= res_data[33:26];
        3'b010  : mem_wr_data <= {6'd0, res_data[35:34]};
        3'b011  : mem_wr_data <= res_data[ 7:0 ];
        3'b100  : mem_wr_data <= res_data[15:8 ];
        default : mem_wr_data <= {6'd0, res_data[17:16]};
    endcase 



assign set_mem_ce = ((sts_cstate == IDLE)   & start   ) |
                    ((sts_cstate == WR_RES) & next_op ) |
                    ((sts_cstate == WORK)   & res_val ) ;


always @(posedge clk or negedge rst_n)
if(~rst_n)        mem_ce <= 1'b0; else
if(set_mem_ce)    mem_ce <= 1'b1; else
if(byte_rd_done | byte_wr_done) 
                  mem_ce <= 1'b0;



assign set_mem_we = (sts_cstate == WORK) & res_val;

always @(posedge clk or negedge rst_n)
if(~rst_n)        mem_we <= 1'b0; else
if(set_mem_we)    mem_we <= 1'b1; else
if(byte_wr_done)  mem_we <= 1'b0;




always @(posedge clk or negedge rst_n)
if(~rst_n) mem_ce_d <= 1'b0   ; else
if(sw_rst) mem_ce_d <= 1'b0   ; else
           mem_ce_d <= mem_ce ;        
           
           


always @(posedge clk or negedge rst_n)    
if(~rst_n) mem_we_d <= 1'b0   ; else
if(sw_rst) mem_we_d <= 1'b0   ; else
           mem_we_d <= mem_we ;




endmodule