data/full_repos/permissive/505451992/clock.v
1: b'%Warning-WIDTH: data/full_repos/permissive/505451992/clock.v:18: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s CONST \'23\'h0\' generates 23 bits.\n                                                               : ... In instance Clock\n        count <= 23\'b0;\n              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/505451992/clock.v:22: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s CONST \'23\'h0\' generates 23 bits.\n                                                               : ... In instance Clock\n                count <= 23\'b0;\n                      ^~\n%Error: Exiting due to 2 warning(s)\n'
module Clock(
input reset,
input clk,
input[23:0] Rate,
output CLK_PWM
    );
    
 wire[23:0] Rate_y;
 assign  Rate_y = Rate;

 reg[23:0] count; 
    reg CLK;
always@(posedge clk or posedge reset) begin                                                                                                                                                                                                                                                                                                                         
        if(reset) begin
        count <= 23'b0;
         CLK <= 1'b0;
        end
        else if(count == Rate_y) begin
                count <= 23'b0;
                CLK<=  ~ CLK;
                end
                else begin
                  count <= count + 23'd1;
                  CLK <=   CLK;
            end
            end
            
    assign CLK_PWM = CLK;
    
endmodule
module Clock(
input reset,
input clk,
input[23:0] Rate,
output CLK_PWM
    );

    
 wire[23:0] Rate_y;
 assign  Rate_y = Rate;

 reg[23:0] count; 
    reg CLK;
always@(posedge clk or posedge reset) begin                                                                                                                                                                                                                                                                                                                         
        if(reset) begin
        count <= 23'b0;
         CLK <= 1'b0;
        end
        else if(count == Rate_y) begin
                count <= 23'b0;
                CLK<=  ~ CLK;
                end
                else begin
                  count <= count + 23'd1;
                  CLK <=   CLK;
            end
            end
            
    assign CLK_PWM = CLK;
    
endmodule