data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v
1: b'%Error: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:13: Unsupported: fork statements\ninitial fork\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:15: Unsupported: Ignoring delay on this delayed statement.\n #1 Reset = 0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11100010_00000001_00000000_00000000 ; #1 MEMLOAD = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11100010_00000001_00000000_00000000 ; #1 MEMLOAD = 1; \n                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #5 MEMLOAD=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11100011_10000000_00010000_00101000 ; #1 MEMLOAD = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11100011_10000000_00010000_00101000 ; #1 MEMLOAD = 1; \n                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #5 MEMLOAD=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11100111_11010001_00100000_00000000 ; #1 MEMLOAD = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11100111_11010001_00100000_00000000 ; #1 MEMLOAD = 1; \n                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #5 MEMLOAD=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11100101_11010001_00110000_00000010 ; #1 MEMLOAD = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11100101_11010001_00110000_00000010 ; #1 MEMLOAD = 1; \n                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #5 MEMLOAD=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11100000_10000000_01010000_00000000 ; #1 MEMLOAD = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11100000_10000000_01010000_00000000 ; #1 MEMLOAD = 1; \n                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #5 MEMLOAD=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:43: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11100000_10000010_01010000_00000101; #1 MEMLOAD = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:43: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11100000_10000010_01010000_00000101; #1 MEMLOAD = 1; \n                                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #5 MEMLOAD=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11100010_01010011_00110000_00000001 ; #1 MEMLOAD = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11100010_01010011_00110000_00000001 ; #1 MEMLOAD = 1; \n                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #5 MEMLOAD=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b00011010_11111111_11111111_11111101 ; #1 MEMLOAD = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b00011010_11111111_11111111_11111101 ; #1 MEMLOAD = 1; \n                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:52: Unsupported: Ignoring delay on this delayed statement.\n    #5 MEMLOAD=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11100101_11000001_01010000_00000011 ; #1 MEMLOAD = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11100101_11000001_01010000_00000011 ; #1 MEMLOAD = 1; \n                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #5 MEMLOAD=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:59: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11101010_00000000_00000000_00000001 ; #1 MEMLOAD = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:59: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11101010_00000000_00000000_00000001 ; #1 MEMLOAD = 1; \n                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #5 MEMLOAD=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:63: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b00001011_00000101_00000111_00000100 ; #1 MEMLOAD = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:63: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b00001011_00000101_00000111_00000100 ; #1 MEMLOAD = 1; \n                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #5 MEMLOAD=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:67: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11101010_11111111_11111111_11111111 ; #1 MEMLOAD = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:67: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11101010_11111111_11111111_11111111 ; #1 MEMLOAD = 1; \n                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:68: Unsupported: Ignoring delay on this delayed statement.\n    #5 MEMLOAD=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'h00000000 ; #1 MEMLOAD = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'h00000000 ; #1 MEMLOAD = 1; \n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:72: Unsupported: Ignoring delay on this delayed statement.\n    #5 MEMLOAD=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #5 MFC = 1 ;#7 MFC = 0 ; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #5 MFC = 1 ;#7 MFC = 0 ; \n              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:79: Unsupported: Ignoring delay on this delayed statement.\n #1 Clk = ~Clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:81: Unsupported: Ignoring delay on this delayed statement.\ninitial #sim_time $finish; \n        ^\n%Error: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:84: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("ARM_CU_ALU_TestBench4.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:85: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,ARM_CU_ALU_TestBench4);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench4.v:87: Unsupported or unknown PLI call: $monitor\n $monitor("input MFC =%d, Reset =%d, Clk =%d, MEMSTORE=%d,MEMLOAD=%d,MEMDAT=%d, output MEMADD=%d, MFA=%d,READ_WRITE=%d,WORD_BYTE=%d,",MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT, MEMADD, MFA,READ_WRITE,WORD_BYTE);\n ^~~~~~~~\n%Error: Exiting due to 4 error(s), 44 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ARM_CU_ALU_TestBench4;

parameter sim_time = 750*2;

reg MFC , Reset , Clk , MEMSTORE,MEMLOAD;
reg [31:0] MEMDAT;
wire MFA,READ_WRITE,WORD_BYTE;
wire [7:0] MEMADD;


ARM_CU_ALU CPU( MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT,MEMADD, MFA,READ_WRITE,WORD_BYTE);

initial fork
	Reset =1; Clk = 0; MEMSTORE=0;MEMLOAD=0;MEMDAT=0;MFC=0;
	#1 Reset = 0;
join

always@(posedge MFA)begin
	if(READ_WRITE == 1)
		case(MEMADD) 
			8'h00:begin
				#1 MEMDAT = 32'b11100010_00000001_00000000_00000000 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
				
			end
			8'h01:begin
				#1 MEMDAT = 32'b11100011_10000000_00010000_00101000 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h02:begin
				#1 MEMDAT = 32'b11100111_11010001_00100000_00000000 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h03:begin
				#1 MEMDAT = 32'b11100101_11010001_00110000_00000010 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h04:begin
				#1 MEMDAT = 32'b11100000_10000000_01010000_00000000 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h05:begin
				#1 MEMDAT = 32'b11100000_10000010_01010000_00000101; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h06:begin
				#1 MEMDAT = 32'b11100010_01010011_00110000_00000001 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h07:begin
				#1 MEMDAT = 32'b00011010_11111111_11111111_11111101 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h08:begin
				#1 MEMDAT = 32'b11100101_11000001_01010000_00000011 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h09:begin
				#1 MEMDAT = 32'b11101010_00000000_00000000_00000001 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h0A:begin
				#1 MEMDAT = 32'b00001011_00000101_00000111_00000100 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h0B:begin
				#1 MEMDAT = 32'b11101010_11111111_11111111_11111111 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			default:begin
				#1 MEMDAT = 32'h00000000 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
		endcase
		#5 MFC = 1 ;#7 MFC = 0 ; 
end
	
always 
	#1 Clk = ~Clk;
	
initial #sim_time $finish; 

initial begin
	$dumpfile("ARM_CU_ALU_TestBench4.vcd");
	$dumpvars(0,ARM_CU_ALU_TestBench4);
	$display(" Test Results" );
	$monitor("input MFC =%d, Reset =%d, Clk =%d, MEMSTORE=%d,MEMLOAD=%d,MEMDAT=%d, output MEMADD=%d, MFA=%d,READ_WRITE=%d,WORD_BYTE=%d,",MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT, MEMADD, MFA,READ_WRITE,WORD_BYTE);
end

endmodule
module ARM_CU_ALU_TestBench4;


parameter sim_time = 750*2;

reg MFC , Reset , Clk , MEMSTORE,MEMLOAD;
reg [31:0] MEMDAT;
wire MFA,READ_WRITE,WORD_BYTE;
wire [7:0] MEMADD;


ARM_CU_ALU CPU( MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT,MEMADD, MFA,READ_WRITE,WORD_BYTE);

initial fork
	Reset =1; Clk = 0; MEMSTORE=0;MEMLOAD=0;MEMDAT=0;MFC=0;
	#1 Reset = 0;
join

always@(posedge MFA)begin
	if(READ_WRITE == 1)
		case(MEMADD) 
			8'h00:begin
				#1 MEMDAT = 32'b11100010_00000001_00000000_00000000 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
				
			end
			8'h01:begin
				#1 MEMDAT = 32'b11100011_10000000_00010000_00101000 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h02:begin
				#1 MEMDAT = 32'b11100111_11010001_00100000_00000000 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h03:begin
				#1 MEMDAT = 32'b11100101_11010001_00110000_00000010 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h04:begin
				#1 MEMDAT = 32'b11100000_10000000_01010000_00000000 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h05:begin
				#1 MEMDAT = 32'b11100000_10000010_01010000_00000101; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h06:begin
				#1 MEMDAT = 32'b11100010_01010011_00110000_00000001 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h07:begin
				#1 MEMDAT = 32'b00011010_11111111_11111111_11111101 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h08:begin
				#1 MEMDAT = 32'b11100101_11000001_01010000_00000011 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h09:begin
				#1 MEMDAT = 32'b11101010_00000000_00000000_00000001 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h0A:begin
				#1 MEMDAT = 32'b00001011_00000101_00000111_00000100 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h0B:begin
				#1 MEMDAT = 32'b11101010_11111111_11111111_11111111 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			default:begin
				#1 MEMDAT = 32'h00000000 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
		endcase
		#5 MFC = 1 ;#7 MFC = 0 ; 
end
	
always 
	#1 Clk = ~Clk;
	
initial #sim_time $finish; 

initial begin
	$dumpfile("ARM_CU_ALU_TestBench4.vcd");
	$dumpvars(0,ARM_CU_ALU_TestBench4);
	$display(" Test Results" );
	$monitor("input MFC =%d, Reset =%d, Clk =%d, MEMSTORE=%d,MEMLOAD=%d,MEMDAT=%d, output MEMADD=%d, MFA=%d,READ_WRITE=%d,WORD_BYTE=%d,",MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT, MEMADD, MFA,READ_WRITE,WORD_BYTE);
end

endmodule