data/full_repos/permissive/458737381/src/verilog-parser/tests/fsm_full_tb.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/fsm_full_tb.v:1: Cannot find include file: fsm_full.v\n`include "fsm_full.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/fsm_full.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/fsm_full.v.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/fsm_full.v.sv\n             fsm_full.v\n             fsm_full.v.v\n             fsm_full.v.sv\n             obj_dir/fsm_full.v\n             obj_dir/fsm_full.v.v\n             obj_dir/fsm_full.v.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/fsm_full_tb.v:10: Unsupported or unknown PLI call: $monitor\n  $monitor("%g\\t    %b  %b  %b  %b  %b  %b  %b  %b", \n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/fsm_full_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #10 reset = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/fsm_full_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #10 reset = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/fsm_full_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #10 req_0 = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/fsm_full_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #20 req_0 = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/fsm_full_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #10 req_1 = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/fsm_full_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #20 req_1 = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/fsm_full_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #10 req_2 = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/fsm_full_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #20 req_2 = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/fsm_full_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #10 req_3 = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/fsm_full_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #20 req_3 = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/fsm_full_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #10 $finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/fsm_full_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n #2 clock = ~clock;\n ^\n%Error: Exiting due to 2 error(s), 12 warning(s)\n'
module fsm_full_tb();
reg clock , reset ;
reg req_0 , req_1 ,  req_2 , req_3; 
wire gnt_0 , gnt_1 , gnt_2 , gnt_3 ;

initial begin
  $display("Time\t    R0 R1 R2 R3 G0 G1 G2 G3");
  $monitor("%g\t    %b  %b  %b  %b  %b  %b  %b  %b", 
    $time, req_0, req_1, req_2, req_3, gnt_0, gnt_1, gnt_2, gnt_3);
  clock = 0;
  reset = 0;
  req_0 = 0;
  req_1 = 0;
  req_2 = 0;
  req_3 = 0;
  #10 reset = 1;
  #10 reset = 0;
  #10 req_0 = 1;
  #20 req_0 = 0;
  #10 req_1 = 1;
  #20 req_1 = 0;
  #10 req_2 = 1;
  #20 req_2 = 0;
  #10 req_3 = 1;
  #20 req_3 = 0;
  #10 $finish;
end

always
 #2 clock = ~clock;


fsm_full U_fsm_full(
clock ,
reset ,
req_0 ,
req_1 ,
req_2 ,
req_3 ,
gnt_0 ,
gnt_1 ,
gnt_2 ,
gnt_3
);



endmodule
module fsm_full_tb();

reg clock , reset ;
reg req_0 , req_1 ,  req_2 , req_3; 
wire gnt_0 , gnt_1 , gnt_2 , gnt_3 ;

initial begin
  $display("Time\t    R0 R1 R2 R3 G0 G1 G2 G3");
  $monitor("%g\t    %b  %b  %b  %b  %b  %b  %b  %b", 
    $time, req_0, req_1, req_2, req_3, gnt_0, gnt_1, gnt_2, gnt_3);
  clock = 0;
  reset = 0;
  req_0 = 0;
  req_1 = 0;
  req_2 = 0;
  req_3 = 0;
  #10 reset = 1;
  #10 reset = 0;
  #10 req_0 = 1;
  #20 req_0 = 0;
  #10 req_1 = 1;
  #20 req_1 = 0;
  #10 req_2 = 1;
  #20 req_2 = 0;
  #10 req_3 = 1;
  #20 req_3 = 0;
  #10 $finish;
end

always
 #2 clock = ~clock;


fsm_full U_fsm_full(
clock ,
reset ,
req_0 ,
req_1 ,
req_2 ,
req_3 ,
gnt_0 ,
gnt_1 ,
gnt_2 ,
gnt_3
);



endmodule