data/full_repos/permissive/519458744/BLI201V32ITL/rtl/core/bli201v32itl_core_idu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/519458744/BLI201V32ITL/rtl/core/bli201v32itl_core_idu.v:65: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 7 bits.\n                                                                                                     : ... In instance idu\n  assign opcode   = idu_i_inst[6:0];\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/rtl/core/bli201v32itl_core_idu.v:171: Cannot find file containing module: \'regfile\'\n  regfile u_regfile (\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/519458744/BLI201V32ITL/rtl/core,data/full_repos/permissive/519458744/regfile\n             data/full_repos/permissive/519458744/BLI201V32ITL/rtl/core,data/full_repos/permissive/519458744/regfile.v\n             data/full_repos/permissive/519458744/BLI201V32ITL/rtl/core,data/full_repos/permissive/519458744/regfile.sv\n             regfile\n             regfile.v\n             regfile.sv\n             obj_dir/regfile\n             obj_dir/regfile.v\n             obj_dir/regfile.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module idu (
  input  clk,
  input  rst,

  input  [31:0] idu_i_inst,
  output        idu_o_is_jump,

  output [31:0] idu_o_rs1_data,
  output [31:0] idu_o_rs2_data,
  output [31:0] idu_o_imm,

  output [1:0]  idu_o_a_sel,
  output [1:0]  idu_o_b_sel,
  output [10:0] idu_o_alu_sel,
  output [3:0]  idu_o_br_sel,

  output        idu_o_is_load,
  output        idu_o_is_store,
  output [4:0]  idu_o_fmt_sel,

  output [2:0]  idu_o_wb_sel,
  input  [31:0] idu_i_rd_data
);

  wire [7:0] opcode;
  wire [4:0] rd_addr;
  wire [2:0] funct3;
  wire [4:0] rs1_addr;
  wire [4:0] rs2_addr;
  wire [6:0] funct7;

  wire opcode_is_load;
  wire opcode_is_fence;
  wire opcode_is_alu_i;
  wire opcode_is_auipc;
  wire opcode_is_alu_iw;
  wire opcode_is_store;
  wire opcode_is_alu_r;
  wire opcode_is_lui;
  wire opcode_is_alu_rw;
  wire opcode_is_branch;
  wire opcode_is_jalr;
  wire opcode_is_jal;
  wire opcode_is_sys;
  
  wire opcode_is_type_r;
  wire opcode_is_type_i;
  wire opcode_is_type_s;
  wire opcode_is_type_b;
  wire opcode_is_type_u;
  wire opcode_is_type_j;
  
  wire regfile_w_en;
  
  wire is_loadstore_doubleword;
  wire is_loadstore_word;
  wire is_loadstore_half;
  wire is_loadstore_byte;
  
  wire is_load_unsigned = funct3[2];


  assign opcode   = idu_i_inst[6:0];
  assign rd_addr  = idu_i_inst[11:7];
  assign funct3   = idu_i_inst[14:12];
  assign rs1_addr = idu_i_inst[19:15];
  assign rs2_addr = idu_i_inst[24:20];
  assign funct7   = idu_i_inst[31:25];


  assign opcode_is_load     = opcode === 'b0000011;
  assign opcode_is_fence    = opcode === 'b0001111;
  assign opcode_is_alu_i    = opcode === 'b0010011;
  assign opcode_is_auipc    = opcode === 'b0010111;
  assign opcode_is_alu_iw   = opcode === 'b0011011;
  assign opcode_is_store    = opcode === 'b0100011;
  assign opcode_is_alu_r    = opcode === 'b0110011;
  assign opcode_is_lui      = opcode === 'b0110111;
  assign opcode_is_alu_rw   = opcode === 'b0110011;
  assign opcode_is_branch   = opcode === 'b1100011;
  assign opcode_is_jalr     = opcode === 'b1100111;
  assign opcode_is_jal      = opcode === 'b1101111;
  assign opcode_is_sys      = opcode === 'b1110011;


  assign opcode_is_type_r = opcode_is_alu_rw | opcode_is_alu_r;
  assign opcode_is_type_i = opcode_is_sys | opcode_is_jalr | opcode_is_alu_iw | opcode_is_alu_i | opcode_is_fence | opcode_is_load;
  assign opcode_is_type_s = opcode_is_store;
  assign opcode_is_type_b = opcode_is_branch;
  assign opcode_is_type_u = opcode_is_lui | opcode_is_auipc;
  assign opcode_is_type_j = opcode_is_jal;


  assign idu_o_imm = (

      ({32{opcode_is_type_i}} & ({{20{idu_i_inst[31]}}, idu_i_inst[31:20]}))

    | ({32{opcode_is_type_s}} & ({{20{idu_i_inst[31]}}, idu_i_inst[31:25], idu_i_inst[11:7]}))

    | ({32{opcode_is_type_b}} & ({{19{idu_i_inst[31]}}, idu_i_inst[31], idu_i_inst[7], idu_i_inst[30:25], idu_i_inst[11:8], 1'b0}))

    | ({32{opcode_is_type_u}} & ({idu_i_inst[31:12], {12{1'b0}}}))

    | ({32{opcode_is_type_j}} & ({{11{idu_i_inst[31]}}, idu_i_inst[31], idu_i_inst[19:12], idu_i_inst[20], idu_i_inst[30:21], 1'b0}))
  );

  assign idu_o_is_jump = opcode_is_jalr | opcode_is_jal;



  assign regfile_w_en = (rd_addr !== 'h00) & (opcode_is_type_j | opcode_is_type_u | opcode_is_type_i | opcode_is_type_r);
  
  

  assign idu_o_a_sel = (opcode_is_auipc | opcode_is_type_j | opcode_is_type_b) ? 'b10 : 'b01;
  assign idu_o_b_sel = (!opcode_is_type_r) ? 'b10 : 'b01;
  assign idu_o_alu_sel = {

    (opcode_is_lui),

    (opcode_is_alu_r & (funct3 === 'b111) & (funct7 === 'b0000000)) | (opcode_is_alu_i & (funct3 === 'b111)),

    (opcode_is_alu_r & (funct3 === 'b110) & (funct7 === 'b0000000)) | (opcode_is_alu_i & (funct3 === 'b110)),

    (opcode_is_alu_r & (funct3 === 'b101) & (funct7 === 'b0100000)) | (opcode_is_alu_i & (funct3 === 'b101) & (funct7 === 'b0100000)),

    (opcode_is_alu_r & (funct3 === 'b101) & (funct7 === 'b0000000)) | (opcode_is_alu_i & (funct3 === 'b101) & (funct7 === 'b0000000)),

    (opcode_is_alu_r & (funct3 === 'b100) & (funct7 === 'b0000000)) | (opcode_is_alu_i & (funct3 === 'b100)),

    (opcode_is_alu_r & (funct3 === 'b011) & (funct7 === 'b0000000)) | (opcode_is_alu_i & (funct3 === 'b011)),

    (opcode_is_alu_r & (funct3 === 'b010) & (funct7 === 'b0000000)) | (opcode_is_alu_i & (funct3 === 'b010)),

    (opcode_is_alu_r & (funct3 === 'b001) & (funct7 === 'b0000000)) | (opcode_is_alu_i & (funct3 === 'b001) & (funct7 === 'b0000000)),

    (opcode_is_alu_r & (funct3 === 'b000) & (funct7 === 'b0100000)),

    (
       (opcode_is_alu_r & (funct3 === 'b000) & (funct7 === 'b0000000))
     | (opcode_is_alu_i & (funct3 === 'b000))
     | (opcode_is_auipc)
     | (opcode_is_jalr)
     | (opcode_is_load)
     | (opcode_is_type_j)
     | (opcode_is_type_b)
     | (opcode_is_type_s)
     )
  };
  assign idu_o_br_sel = {funct3, opcode_is_branch};



  assign is_loadstore_doubleword = funct3[1:0] === 'b11;
  assign is_loadstore_word = funct3[1:0] === 'b10;
  assign is_loadstore_half = funct3[1:0] === 'b01;
  assign is_loadstore_byte = funct3[1:0] === 'b00;

  assign idu_o_is_load = opcode_is_load;
  assign idu_o_is_store = opcode_is_store;
  assign idu_o_fmt_sel = {is_load_unsigned, is_loadstore_doubleword, is_loadstore_word, is_loadstore_half, is_loadstore_byte};



  assign idu_o_wb_sel = (idu_o_is_jump) ? 'b100 :
                        (opcode_is_load) ? 'b010 :
                        'b001;

  regfile u_regfile (
    .clk(clk),
    .regfile_i_rd_addr(rd_addr),
    .regfile_i_w_en(regfile_w_en),
    .regfile_i_rd_data(idu_i_rd_data),
    .regfile_i_rs1_addr(rs1_addr),
    .regfile_o_rs1_data(idu_o_rs1_data),
    .regfile_i_rs2_addr(rs2_addr),
    .regfile_o_rs2_data(idu_o_rs2_data)
  );

endmodule
module idu (
  input  clk,
  input  rst,

  input  [31:0] idu_i_inst,
  output        idu_o_is_jump,

  output [31:0] idu_o_rs1_data,
  output [31:0] idu_o_rs2_data,
  output [31:0] idu_o_imm,

  output [1:0]  idu_o_a_sel,
  output [1:0]  idu_o_b_sel,
  output [10:0] idu_o_alu_sel,
  output [3:0]  idu_o_br_sel,

  output        idu_o_is_load,
  output        idu_o_is_store,
  output [4:0]  idu_o_fmt_sel,

  output [2:0]  idu_o_wb_sel,
  input  [31:0] idu_i_rd_data
);


  wire [7:0] opcode;
  wire [4:0] rd_addr;
  wire [2:0] funct3;
  wire [4:0] rs1_addr;
  wire [4:0] rs2_addr;
  wire [6:0] funct7;

  wire opcode_is_load;
  wire opcode_is_fence;
  wire opcode_is_alu_i;
  wire opcode_is_auipc;
  wire opcode_is_alu_iw;
  wire opcode_is_store;
  wire opcode_is_alu_r;
  wire opcode_is_lui;
  wire opcode_is_alu_rw;
  wire opcode_is_branch;
  wire opcode_is_jalr;
  wire opcode_is_jal;
  wire opcode_is_sys;
  
  wire opcode_is_type_r;
  wire opcode_is_type_i;
  wire opcode_is_type_s;
  wire opcode_is_type_b;
  wire opcode_is_type_u;
  wire opcode_is_type_j;
  
  wire regfile_w_en;
  
  wire is_loadstore_doubleword;
  wire is_loadstore_word;
  wire is_loadstore_half;
  wire is_loadstore_byte;
  
  wire is_load_unsigned = funct3[2];


  assign opcode   = idu_i_inst[6:0];
  assign rd_addr  = idu_i_inst[11:7];
  assign funct3   = idu_i_inst[14:12];
  assign rs1_addr = idu_i_inst[19:15];
  assign rs2_addr = idu_i_inst[24:20];
  assign funct7   = idu_i_inst[31:25];


  assign opcode_is_load     = opcode === 'b0000011;
  assign opcode_is_fence    = opcode === 'b0001111;
  assign opcode_is_alu_i    = opcode === 'b0010011;
  assign opcode_is_auipc    = opcode === 'b0010111;
  assign opcode_is_alu_iw   = opcode === 'b0011011;
  assign opcode_is_store    = opcode === 'b0100011;
  assign opcode_is_alu_r    = opcode === 'b0110011;
  assign opcode_is_lui      = opcode === 'b0110111;
  assign opcode_is_alu_rw   = opcode === 'b0110011;
  assign opcode_is_branch   = opcode === 'b1100011;
  assign opcode_is_jalr     = opcode === 'b1100111;
  assign opcode_is_jal      = opcode === 'b1101111;
  assign opcode_is_sys      = opcode === 'b1110011;


  assign opcode_is_type_r = opcode_is_alu_rw | opcode_is_alu_r;
  assign opcode_is_type_i = opcode_is_sys | opcode_is_jalr | opcode_is_alu_iw | opcode_is_alu_i | opcode_is_fence | opcode_is_load;
  assign opcode_is_type_s = opcode_is_store;
  assign opcode_is_type_b = opcode_is_branch;
  assign opcode_is_type_u = opcode_is_lui | opcode_is_auipc;
  assign opcode_is_type_j = opcode_is_jal;


  assign idu_o_imm = (

      ({32{opcode_is_type_i}} & ({{20{idu_i_inst[31]}}, idu_i_inst[31:20]}))

    | ({32{opcode_is_type_s}} & ({{20{idu_i_inst[31]}}, idu_i_inst[31:25], idu_i_inst[11:7]}))

    | ({32{opcode_is_type_b}} & ({{19{idu_i_inst[31]}}, idu_i_inst[31], idu_i_inst[7], idu_i_inst[30:25], idu_i_inst[11:8], 1'b0}))

    | ({32{opcode_is_type_u}} & ({idu_i_inst[31:12], {12{1'b0}}}))

    | ({32{opcode_is_type_j}} & ({{11{idu_i_inst[31]}}, idu_i_inst[31], idu_i_inst[19:12], idu_i_inst[20], idu_i_inst[30:21], 1'b0}))
  );

  assign idu_o_is_jump = opcode_is_jalr | opcode_is_jal;



  assign regfile_w_en = (rd_addr !== 'h00) & (opcode_is_type_j | opcode_is_type_u | opcode_is_type_i | opcode_is_type_r);
  
  

  assign idu_o_a_sel = (opcode_is_auipc | opcode_is_type_j | opcode_is_type_b) ? 'b10 : 'b01;
  assign idu_o_b_sel = (!opcode_is_type_r) ? 'b10 : 'b01;
  assign idu_o_alu_sel = {

    (opcode_is_lui),

    (opcode_is_alu_r & (funct3 === 'b111) & (funct7 === 'b0000000)) | (opcode_is_alu_i & (funct3 === 'b111)),

    (opcode_is_alu_r & (funct3 === 'b110) & (funct7 === 'b0000000)) | (opcode_is_alu_i & (funct3 === 'b110)),

    (opcode_is_alu_r & (funct3 === 'b101) & (funct7 === 'b0100000)) | (opcode_is_alu_i & (funct3 === 'b101) & (funct7 === 'b0100000)),

    (opcode_is_alu_r & (funct3 === 'b101) & (funct7 === 'b0000000)) | (opcode_is_alu_i & (funct3 === 'b101) & (funct7 === 'b0000000)),

    (opcode_is_alu_r & (funct3 === 'b100) & (funct7 === 'b0000000)) | (opcode_is_alu_i & (funct3 === 'b100)),

    (opcode_is_alu_r & (funct3 === 'b011) & (funct7 === 'b0000000)) | (opcode_is_alu_i & (funct3 === 'b011)),

    (opcode_is_alu_r & (funct3 === 'b010) & (funct7 === 'b0000000)) | (opcode_is_alu_i & (funct3 === 'b010)),

    (opcode_is_alu_r & (funct3 === 'b001) & (funct7 === 'b0000000)) | (opcode_is_alu_i & (funct3 === 'b001) & (funct7 === 'b0000000)),

    (opcode_is_alu_r & (funct3 === 'b000) & (funct7 === 'b0100000)),

    (
       (opcode_is_alu_r & (funct3 === 'b000) & (funct7 === 'b0000000))
     | (opcode_is_alu_i & (funct3 === 'b000))
     | (opcode_is_auipc)
     | (opcode_is_jalr)
     | (opcode_is_load)
     | (opcode_is_type_j)
     | (opcode_is_type_b)
     | (opcode_is_type_s)
     )
  };
  assign idu_o_br_sel = {funct3, opcode_is_branch};



  assign is_loadstore_doubleword = funct3[1:0] === 'b11;
  assign is_loadstore_word = funct3[1:0] === 'b10;
  assign is_loadstore_half = funct3[1:0] === 'b01;
  assign is_loadstore_byte = funct3[1:0] === 'b00;

  assign idu_o_is_load = opcode_is_load;
  assign idu_o_is_store = opcode_is_store;
  assign idu_o_fmt_sel = {is_load_unsigned, is_loadstore_doubleword, is_loadstore_word, is_loadstore_half, is_loadstore_byte};



  assign idu_o_wb_sel = (idu_o_is_jump) ? 'b100 :
                        (opcode_is_load) ? 'b010 :
                        'b001;

  regfile u_regfile (
    .clk(clk),
    .regfile_i_rd_addr(rd_addr),
    .regfile_i_w_en(regfile_w_en),
    .regfile_i_rd_data(idu_i_rd_data),
    .regfile_i_rs1_addr(rs1_addr),
    .regfile_o_rs1_data(idu_o_rs1_data),
    .regfile_i_rs2_addr(rs2_addr),
    .regfile_o_rs2_data(idu_o_rs2_data)
  );

endmodule