data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/memrwpx.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/memrwpx.v:25: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n     do\n     ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/memrwpx.v:41: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\noutput [WIDTH-1:0]  do;      \n                    ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/memrwpx.v:49: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\nreg  [WIDTH-1:0]    do;      \n                    ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/memrwpx.v:76: syntax error, unexpected <=\n        do      <= {WIDTH{1'b0}};\n                ^~\n%Error: Cannot continue\n"
module memrwpx
    (
     rst_,
     wrclk,
     wa,
     we,
     di,
     rdclk,
     ra,
     do
     );

parameter ADDRBIT = 9;
parameter DEPTH   = 512;
parameter WIDTH   = 32;
parameter TYPE = "AUTO";
parameter MAXDEPTH = 0;

input               rst_;
input               wrclk;
input [ADDRBIT-1:0] wa;
input               we;
input [WIDTH-1:0]   di;
input               rdclk;
input [ADDRBIT-1:0] ra;
output [WIDTH-1:0]  do;

reg [ADDRBIT-1:0]   iwa;
reg                 iwe;
reg [WIDTH-1:0]     idi;
reg [ADDRBIT-1:0]   ira;

wire [WIDTH-1:0]    ido;
reg  [WIDTH-1:0]    do;



always @ (posedge wrclk or negedge rst_)
    if (~rst_)
        begin
        iwa <= {ADDRBIT{1'b0}};
        iwe <= 1'b0;
        idi <= {WIDTH{1'b0}};
        end
    else
        begin
        iwa <= wa;
        iwe <= we;
        idi <= di;
        end


always @ (posedge rdclk or negedge rst_)
    if (~rst_)
        ira <= {ADDRBIT{1'b0}};
    else
        ira <= ra;

always @ (posedge rdclk or negedge rst_)
    if (~rst_)
        do      <= {WIDTH{1'b0}};
    else
        do      <= ido;


ramrwpx #(ADDRBIT,DEPTH,WIDTH) ram (wrclk,iwa,iwe,idi,rdclk,ira,ido);

endmodule
module memrwpx
    (
     rst_,
     wrclk,
     wa,
     we,
     di,
     rdclk,
     ra,
     do
     );


parameter ADDRBIT = 9;
parameter DEPTH   = 512;
parameter WIDTH   = 32;
parameter TYPE = "AUTO";
parameter MAXDEPTH = 0;

input               rst_;
input               wrclk;
input [ADDRBIT-1:0] wa;
input               we;
input [WIDTH-1:0]   di;
input               rdclk;
input [ADDRBIT-1:0] ra;
output [WIDTH-1:0]  do;

reg [ADDRBIT-1:0]   iwa;
reg                 iwe;
reg [WIDTH-1:0]     idi;
reg [ADDRBIT-1:0]   ira;

wire [WIDTH-1:0]    ido;
reg  [WIDTH-1:0]    do;



always @ (posedge wrclk or negedge rst_)
    if (~rst_)
        begin
        iwa <= {ADDRBIT{1'b0}};
        iwe <= 1'b0;
        idi <= {WIDTH{1'b0}};
        end
    else
        begin
        iwa <= wa;
        iwe <= we;
        idi <= di;
        end


always @ (posedge rdclk or negedge rst_)
    if (~rst_)
        ira <= {ADDRBIT{1'b0}};
    else
        ira <= ra;

always @ (posedge rdclk or negedge rst_)
    if (~rst_)
        do      <= {WIDTH{1'b0}};
    else
        do      <= ido;


ramrwpx #(ADDRBIT,DEPTH,WIDTH) ram (wrclk,iwa,iwe,idi,rdclk,ira,ido);

endmodule