data/full_repos/permissive/441359809/src/yosys/tests/opt/opt_share_diff_port_widths.v
1: b'%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/opt/opt_share_diff_port_widths.v:14: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 11 bits.\n                                                                                                        : ... In instance opt_share_test\n      0: res = add0_res[10:0];\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/opt/opt_share_diff_port_widths.v:15: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 11 bits.\n                                                                                                        : ... In instance opt_share_test\n      1: res = add1_res[10:0];\n             ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/opt/opt_share_diff_port_widths.v:17: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                                        : ... In instance opt_share_test\n      default: res = 32\'bx;\n                   ^\n%Error: Exiting due to 3 warning(s)\n'
module opt_share_test(
  input [15:0]       a,
  input [15:0]       b,
  input [15:0]       c,
  input [1:0]      sel,
  output reg [15:0] res
  );

  wire [15:0]       add0_res = a+b;
  wire [15:0]       add1_res = a+c;

  always @* begin
    case(sel)
      0: res = add0_res[10:0];
      1: res = add1_res[10:0];
      2: res = a - b;
      default: res = 32'bx;
    endcase
  end

endmodule
module opt_share_test(
  input [15:0]       a,
  input [15:0]       b,
  input [15:0]       c,
  input [1:0]      sel,
  output reg [15:0] res
  );


  wire [15:0]       add0_res = a+b;
  wire [15:0]       add1_res = a+c;

  always @* begin
    case(sel)
      0: res = add0_res[10:0];
      1: res = add1_res[10:0];
      2: res = a - b;
      default: res = 32'bx;
    endcase
  end

endmodule