data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v
1: b'%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:46: Cannot find include file: spi_defines.v\n`include "spi_defines.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/506636840/rtl/spi/rtl/verilog,data/full_repos/permissive/506636840/spi_defines.v\n             data/full_repos/permissive/506636840/rtl/spi/rtl/verilog,data/full_repos/permissive/506636840/spi_defines.v.v\n             data/full_repos/permissive/506636840/rtl/spi/rtl/verilog,data/full_repos/permissive/506636840/spi_defines.v.sv\n             spi_defines.v\n             spi_defines.v.v\n             spi_defines.v.sv\n             obj_dir/spi_defines.v\n             obj_dir/spi_defines.v.v\n             obj_dir/spi_defines.v.sv\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:47: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:75: Define or directive not defined: \'`SPI_SS_NB\'\n  output          [`SPI_SS_NB-1:0] ss_pad_o;          \n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:85: Define or directive not defined: \'`SPI_DIVIDER_LEN\'\n  reg       [`SPI_DIVIDER_LEN-1:0] divider;           \n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:86: Define or directive not defined: \'`SPI_CTRL_BIT_NB\'\n  reg       [`SPI_CTRL_BIT_NB-1:0] ctrl;              \n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:87: Define or directive not defined: \'`SPI_SS_NB\'\n  reg             [`SPI_SS_NB-1:0] ss;                \n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:89: Define or directive not defined: \'`SPI_MAX_CHAR\'\n  wire         [`SPI_MAX_CHAR-1:0] rx;                \n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:92: Define or directive not defined: \'`SPI_CHAR_LEN_BITS\'\n  wire    [`SPI_CHAR_LEN_BITS-1:0] char_len;          \n           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:107: Define or directive not defined: \'`SPI_OFS_BITS\'\n  assign spi_divider_sel = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_DEVIDE);\n                                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:107: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  assign spi_divider_sel = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_DEVIDE);\n                                                                ^\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:107: Define or directive not defined: \'`SPI_DEVIDE\'\n  assign spi_divider_sel = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_DEVIDE);\n                                                                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:108: Define or directive not defined: \'`SPI_OFS_BITS\'\n  assign spi_ctrl_sel    = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_CTRL);\n                                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:108: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  assign spi_ctrl_sel    = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_CTRL);\n                                                                ^\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:108: Define or directive not defined: \'`SPI_CTRL\'\n  assign spi_ctrl_sel    = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_CTRL);\n                                                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:109: Define or directive not defined: \'`SPI_OFS_BITS\'\n  assign spi_tx_sel[0]   = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_TX_0);\n                                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:109: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  assign spi_tx_sel[0]   = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_TX_0);\n                                                                ^\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:109: Define or directive not defined: \'`SPI_TX_0\'\n  assign spi_tx_sel[0]   = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_TX_0);\n                                                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:110: Define or directive not defined: \'`SPI_OFS_BITS\'\n  assign spi_tx_sel[1]   = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_TX_1);\n                                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:110: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  assign spi_tx_sel[1]   = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_TX_1);\n                                                                ^\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:110: Define or directive not defined: \'`SPI_TX_1\'\n  assign spi_tx_sel[1]   = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_TX_1);\n                                                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:111: Define or directive not defined: \'`SPI_OFS_BITS\'\n  assign spi_tx_sel[2]   = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_TX_2);\n                                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:111: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  assign spi_tx_sel[2]   = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_TX_2);\n                                                                ^\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:111: Define or directive not defined: \'`SPI_TX_2\'\n  assign spi_tx_sel[2]   = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_TX_2);\n                                                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:112: Define or directive not defined: \'`SPI_OFS_BITS\'\n  assign spi_tx_sel[3]   = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_TX_3);\n                                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:112: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  assign spi_tx_sel[3]   = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_TX_3);\n                                                                ^\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:112: Define or directive not defined: \'`SPI_TX_3\'\n  assign spi_tx_sel[3]   = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_TX_3);\n                                                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:113: Define or directive not defined: \'`SPI_OFS_BITS\'\n  assign spi_ss_sel      = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_SS);\n                                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:113: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  assign spi_ss_sel      = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_SS);\n                                                                ^\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:113: Define or directive not defined: \'`SPI_SS\'\n  assign spi_ss_sel      = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_SS);\n                                                                     ^~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:118: Define or directive not defined: \'`SPI_OFS_BITS\'\n    case (PADDR[`SPI_OFS_BITS])\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:118: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    case (PADDR[`SPI_OFS_BITS])\n                             ^\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:131: Define or directive not defined: \'`SPI_RX_0\'\n      `SPI_RX_0:    wb_dat = {{32-`SPI_MAX_CHAR{1\'b0}}, rx[`SPI_MAX_CHAR-1:0]};\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:131: Define or directive not defined: \'`SPI_MAX_CHAR\'\n      `SPI_RX_0:    wb_dat = {{32-`SPI_MAX_CHAR{1\'b0}}, rx[`SPI_MAX_CHAR-1:0]};\n                                  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:131: Define or directive not defined: \'`SPI_MAX_CHAR\'\n      `SPI_RX_0:    wb_dat = {{32-`SPI_MAX_CHAR{1\'b0}}, rx[`SPI_MAX_CHAR-1:0]};\n                                                           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:132: Define or directive not defined: \'`SPI_RX_1\'\n      `SPI_RX_1:    wb_dat = 32\'b0;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:133: Define or directive not defined: \'`SPI_RX_2\'\n      `SPI_RX_2:    wb_dat = 32\'b0;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:134: Define or directive not defined: \'`SPI_RX_3\'\n      `SPI_RX_3:    wb_dat = 32\'b0;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:137: Define or directive not defined: \'`SPI_CTRL\'\n      `SPI_CTRL:    wb_dat = {{32-`SPI_CTRL_BIT_NB{1\'b0}}, ctrl};\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:137: Define or directive not defined: \'`SPI_CTRL_BIT_NB\'\n      `SPI_CTRL:    wb_dat = {{32-`SPI_CTRL_BIT_NB{1\'b0}}, ctrl};\n                                  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:138: Define or directive not defined: \'`SPI_DEVIDE\'\n      `SPI_DEVIDE:  wb_dat = {{32-`SPI_DIVIDER_LEN{1\'b0}}, divider};\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:138: Define or directive not defined: \'`SPI_DIVIDER_LEN\'\n      `SPI_DEVIDE:  wb_dat = {{32-`SPI_DIVIDER_LEN{1\'b0}}, divider};\n                                  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:139: Define or directive not defined: \'`SPI_SS\'\n      `SPI_SS:      wb_dat = {{32-`SPI_SS_NB{1\'b0}}, ss};\n      ^~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:139: Define or directive not defined: \'`SPI_SS_NB\'\n      `SPI_SS:      wb_dat = {{32-`SPI_SS_NB{1\'b0}}, ss};\n                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:180: Define or directive not defined: \'`SPI_DIVIDER_LEN\'\n        divider <= #Tp {`SPI_DIVIDER_LEN{1\'b0}};\n                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:203: Define or directive not defined: \'`SPI_CTRL_BIT_NB\'\n      ctrl <= #Tp {`SPI_CTRL_BIT_NB{1\'b0}};\n                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:206: Define or directive not defined: \'`SPI_CTRL_BIT_NB\'\n          ctrl[`SPI_CTRL_BIT_NB-1:0] <= #Tp PWDATA[`SPI_CTRL_BIT_NB-1:0];\n               ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:206: Define or directive not defined: \'`SPI_CTRL_BIT_NB\'\n          ctrl[`SPI_CTRL_BIT_NB-1:0] <= #Tp PWDATA[`SPI_CTRL_BIT_NB-1:0];\n                                                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:209: Define or directive not defined: \'`SPI_CTRL_GO\'\n      ctrl[`SPI_CTRL_GO] <= #Tp 1\'b0;\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:209: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n      ctrl[`SPI_CTRL_GO] <= #Tp 1\'b0;\n                       ^\n%Error: data/full_repos/permissive/506636840/rtl/spi/rtl/verilog/spi_top.v:212: Define or directive not defined: \'`SPI_CTRL_RX_NEGEDGE\'\n  assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE];\n                           ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module spi_top
(

  PCLK, PRESETN, PADDR, PWDATA, PRDATA, PSEL,
  PWRITE, PENABLE, PREADY, PSLVERR,

  IRQ,

  ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i
);

  parameter Tp = 1;
  
  input                            PCLK;
  input                            PRESETN;
  input [4:0]                      PADDR;
  input [31:0]                     PWDATA;
  output[31:0]                     PRDATA;
  input                            PWRITE;
  input                            PSEL;
  input                            PENABLE;
  output                           PREADY;
  output                           PSLVERR;
  output                           IRQ;
                                                     

  output          [`SPI_SS_NB-1:0] ss_pad_o;
  output                           sclk_pad_o;
  output                           mosi_pad_o;
  input                            miso_pad_i;
                                                     
  reg                     [32-1:0] PRDATA;
  reg                              PREADY;
  reg                              IRQ;
                                               

  reg       [`SPI_DIVIDER_LEN-1:0] divider;
  reg       [`SPI_CTRL_BIT_NB-1:0] ctrl;
  reg             [`SPI_SS_NB-1:0] ss;
  reg                     [32-1:0] wb_dat;
  wire         [`SPI_MAX_CHAR-1:0] rx;
  wire                             rx_negedge;
  wire                             tx_negedge;
  wire    [`SPI_CHAR_LEN_BITS-1:0] char_len;
  wire                             go;
  wire                             lsb;
  wire                             ie;
  wire                             ass;
  wire                             spi_divider_sel;
  wire                             spi_ctrl_sel;
  wire                       [3:0] spi_tx_sel;
  wire                             spi_ss_sel;
  wire                             tip;
  wire                             pos_edge;
  wire                             neg_edge;
  wire                             last_bit;
  

  assign spi_divider_sel = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_DEVIDE);
  assign spi_ctrl_sel    = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_CTRL);
  assign spi_tx_sel[0]   = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_TX_0);
  assign spi_tx_sel[1]   = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_TX_1);
  assign spi_tx_sel[2]   = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_TX_2);
  assign spi_tx_sel[3]   = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_TX_3);
  assign spi_ss_sel      = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_SS);
  

  always @(PADDR or rx or ctrl or divider or ss)
  begin
    case (PADDR[`SPI_OFS_BITS])
`ifdef SPI_MAX_CHAR_128
      `SPI_RX_0:    wb_dat = rx[31:0];
      `SPI_RX_1:    wb_dat = rx[63:32];
      `SPI_RX_2:    wb_dat = rx[95:64];
      `SPI_RX_3:    wb_dat = {{128-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:96]};
`else
`ifdef SPI_MAX_CHAR_64
      `SPI_RX_0:    wb_dat = rx[31:0];
      `SPI_RX_1:    wb_dat = {{64-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:32]};
      `SPI_RX_2:    wb_dat = 32'b0;
      `SPI_RX_3:    wb_dat = 32'b0;
`else
      `SPI_RX_0:    wb_dat = {{32-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:0]};
      `SPI_RX_1:    wb_dat = 32'b0;
      `SPI_RX_2:    wb_dat = 32'b0;
      `SPI_RX_3:    wb_dat = 32'b0;
`endif
`endif
      `SPI_CTRL:    wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl};
      `SPI_DEVIDE:  wb_dat = {{32-`SPI_DIVIDER_LEN{1'b0}}, divider};
      `SPI_SS:      wb_dat = {{32-`SPI_SS_NB{1'b0}}, ss};
      default:      wb_dat = 32'bx;
    endcase
  end
  

  always @(posedge PCLK or negedge PRESETN)
  begin
    if (PRESETN == 0)
      PRDATA <= #Tp 32'b0;
    else
      PRDATA <= #Tp wb_dat;
  end
  

  always @(posedge PCLK or negedge PRESETN)
  begin
    if (PRESETN == 0)
      PREADY <= #Tp 1'b0;
    else
      PREADY <= #Tp PSEL & PENABLE & ~PREADY;
  end
  

  assign PSLVERR = 1'b0;
  

  always @(posedge PCLK or negedge PRESETN)
  begin
    if (PRESETN == 0)
      IRQ <= #Tp 1'b0;
    else if (ie && tip && last_bit && pos_edge)
      IRQ <= #Tp 1'b1;
    else if (PREADY)
      IRQ <= #Tp 1'b0;
  end
  

  always @(posedge PCLK or negedge PRESETN)
  begin
    if (PRESETN == 0)
        divider <= #Tp {`SPI_DIVIDER_LEN{1'b0}};
    else if (spi_divider_sel && PWRITE && !tip)
      begin
      `ifdef SPI_DIVIDER_LEN_8
        
          divider <= #Tp PWDATA[`SPI_DIVIDER_LEN-1:0];
      `endif
      `ifdef SPI_DIVIDER_LEN_16
          divider[`SPI_DIVIDER_LEN-1:0] <= #Tp PWDATA[`SPI_DIVIDER_LEN-1:0];
      `endif
      `ifdef SPI_DIVIDER_LEN_24
          divider[`SPI_DIVIDER_LEN-1:0] <= #Tp PWDATA[`SPI_DIVIDER_LEN-1:0];
      `endif
      `ifdef SPI_DIVIDER_LEN_32
          divider[`SPI_DIVIDER_LEN-1:0] <= #Tp PWDATA[`SPI_DIVIDER_LEN-1:0];
      `endif
      end
  end
  

  always @(posedge PCLK or negedge PRESETN)
  begin
    if (PRESETN == 0)
      ctrl <= #Tp {`SPI_CTRL_BIT_NB{1'b0}};
    else if(spi_ctrl_sel && PWRITE && !tip)
      begin
          ctrl[`SPI_CTRL_BIT_NB-1:0] <= #Tp PWDATA[`SPI_CTRL_BIT_NB-1:0];
      end
    else if(tip && last_bit && pos_edge)
      ctrl[`SPI_CTRL_GO] <= #Tp 1'b0;
  end
  
  assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE];
  assign tx_negedge = ctrl[`SPI_CTRL_TX_NEGEDGE];
  assign go         = ctrl[`SPI_CTRL_GO];
  assign char_len   = ctrl[`SPI_CTRL_CHAR_LEN];
  assign lsb        = ctrl[`SPI_CTRL_LSB];
  assign ie         = ctrl[`SPI_CTRL_IE];
  assign ass        = ctrl[`SPI_CTRL_ASS];
  

  always @(posedge PCLK or negedge PRESETN)
  begin
    if (PRESETN == 0)
      ss <= #Tp {`SPI_SS_NB{1'b0}};
    else if(spi_ss_sel && PWRITE && !tip)
      begin
      `ifdef SPI_SS_NB_8
          ss <= #Tp PWDATA[`SPI_SS_NB-1:0];
      `endif
      `ifdef SPI_SS_NB_16
          ss[`SPI_SS_NB-1:0] <= #Tp PWDATA[`SPI_SS_NB-1:0];
      `endif
      `ifdef SPI_SS_NB_24
          ss[`SPI_SS_NB-1:0] <= #Tp PWDATA[`SPI_SS_NB-1:0];
      `endif
      `ifdef SPI_SS_NB_32
          ss[`SPI_SS_NB-1:0] <= #Tp PWDATA[`SPI_SS_NB-1:0];
      `endif
      end
  end
  
  assign ss_pad_o = ~((ss & {`SPI_SS_NB{tip & ass}}) | (ss & {`SPI_SS_NB{!ass}}));
  
  spi_clgen clgen (.clk_in(PCLK), .rst(!PRESETN), .go(go), .enable(tip), .last_clk(last_bit),
                   .divider(divider), .clk_out(sclk_pad_o), .pos_edge(pos_edge), 
                   .neg_edge(neg_edge));
  
  spi_shift shift (.clk(PCLK), .rst(!PRESETN), .len(char_len[`SPI_CHAR_LEN_BITS-1:0]),
                   .latch(spi_tx_sel[3:0] & {4{PWRITE}}), .byte_sel(4'hF), .lsb(lsb), 
                   .go(go), .pos_edge(pos_edge), .neg_edge(neg_edge), 
                   .rx_negedge(rx_negedge), .tx_negedge(tx_negedge),
                   .tip(tip), .last(last_bit), 
                   .p_in(PWDATA), .p_out(rx), 
                   .s_clk(sclk_pad_o), .s_in(miso_pad_i), .s_out(mosi_pad_o));
endmodule
module spi_top
(

  PCLK, PRESETN, PADDR, PWDATA, PRDATA, PSEL,
  PWRITE, PENABLE, PREADY, PSLVERR,

  IRQ,

  ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i
);


  parameter Tp = 1;
  
  input                            PCLK;
  input                            PRESETN;
  input [4:0]                      PADDR;
  input [31:0]                     PWDATA;
  output[31:0]                     PRDATA;
  input                            PWRITE;
  input                            PSEL;
  input                            PENABLE;
  output                           PREADY;
  output                           PSLVERR;
  output                           IRQ;
                                                     

  output          [`SPI_SS_NB-1:0] ss_pad_o;
  output                           sclk_pad_o;
  output                           mosi_pad_o;
  input                            miso_pad_i;
                                                     
  reg                     [32-1:0] PRDATA;
  reg                              PREADY;
  reg                              IRQ;
                                               

  reg       [`SPI_DIVIDER_LEN-1:0] divider;
  reg       [`SPI_CTRL_BIT_NB-1:0] ctrl;
  reg             [`SPI_SS_NB-1:0] ss;
  reg                     [32-1:0] wb_dat;
  wire         [`SPI_MAX_CHAR-1:0] rx;
  wire                             rx_negedge;
  wire                             tx_negedge;
  wire    [`SPI_CHAR_LEN_BITS-1:0] char_len;
  wire                             go;
  wire                             lsb;
  wire                             ie;
  wire                             ass;
  wire                             spi_divider_sel;
  wire                             spi_ctrl_sel;
  wire                       [3:0] spi_tx_sel;
  wire                             spi_ss_sel;
  wire                             tip;
  wire                             pos_edge;
  wire                             neg_edge;
  wire                             last_bit;
  

  assign spi_divider_sel = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_DEVIDE);
  assign spi_ctrl_sel    = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_CTRL);
  assign spi_tx_sel[0]   = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_TX_0);
  assign spi_tx_sel[1]   = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_TX_1);
  assign spi_tx_sel[2]   = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_TX_2);
  assign spi_tx_sel[3]   = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_TX_3);
  assign spi_ss_sel      = PSEL & PENABLE & (PADDR[`SPI_OFS_BITS] == `SPI_SS);
  

  always @(PADDR or rx or ctrl or divider or ss)
  begin
    case (PADDR[`SPI_OFS_BITS])
`ifdef SPI_MAX_CHAR_128
      `SPI_RX_0:    wb_dat = rx[31:0];
      `SPI_RX_1:    wb_dat = rx[63:32];
      `SPI_RX_2:    wb_dat = rx[95:64];
      `SPI_RX_3:    wb_dat = {{128-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:96]};
`else
`ifdef SPI_MAX_CHAR_64
      `SPI_RX_0:    wb_dat = rx[31:0];
      `SPI_RX_1:    wb_dat = {{64-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:32]};
      `SPI_RX_2:    wb_dat = 32'b0;
      `SPI_RX_3:    wb_dat = 32'b0;
`else
      `SPI_RX_0:    wb_dat = {{32-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:0]};
      `SPI_RX_1:    wb_dat = 32'b0;
      `SPI_RX_2:    wb_dat = 32'b0;
      `SPI_RX_3:    wb_dat = 32'b0;
`endif
`endif
      `SPI_CTRL:    wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl};
      `SPI_DEVIDE:  wb_dat = {{32-`SPI_DIVIDER_LEN{1'b0}}, divider};
      `SPI_SS:      wb_dat = {{32-`SPI_SS_NB{1'b0}}, ss};
      default:      wb_dat = 32'bx;
    endcase
  end
  

  always @(posedge PCLK or negedge PRESETN)
  begin
    if (PRESETN == 0)
      PRDATA <= #Tp 32'b0;
    else
      PRDATA <= #Tp wb_dat;
  end
  

  always @(posedge PCLK or negedge PRESETN)
  begin
    if (PRESETN == 0)
      PREADY <= #Tp 1'b0;
    else
      PREADY <= #Tp PSEL & PENABLE & ~PREADY;
  end
  

  assign PSLVERR = 1'b0;
  

  always @(posedge PCLK or negedge PRESETN)
  begin
    if (PRESETN == 0)
      IRQ <= #Tp 1'b0;
    else if (ie && tip && last_bit && pos_edge)
      IRQ <= #Tp 1'b1;
    else if (PREADY)
      IRQ <= #Tp 1'b0;
  end
  

  always @(posedge PCLK or negedge PRESETN)
  begin
    if (PRESETN == 0)
        divider <= #Tp {`SPI_DIVIDER_LEN{1'b0}};
    else if (spi_divider_sel && PWRITE && !tip)
      begin
      `ifdef SPI_DIVIDER_LEN_8
        
          divider <= #Tp PWDATA[`SPI_DIVIDER_LEN-1:0];
      `endif
      `ifdef SPI_DIVIDER_LEN_16
          divider[`SPI_DIVIDER_LEN-1:0] <= #Tp PWDATA[`SPI_DIVIDER_LEN-1:0];
      `endif
      `ifdef SPI_DIVIDER_LEN_24
          divider[`SPI_DIVIDER_LEN-1:0] <= #Tp PWDATA[`SPI_DIVIDER_LEN-1:0];
      `endif
      `ifdef SPI_DIVIDER_LEN_32
          divider[`SPI_DIVIDER_LEN-1:0] <= #Tp PWDATA[`SPI_DIVIDER_LEN-1:0];
      `endif
      end
  end
  

  always @(posedge PCLK or negedge PRESETN)
  begin
    if (PRESETN == 0)
      ctrl <= #Tp {`SPI_CTRL_BIT_NB{1'b0}};
    else if(spi_ctrl_sel && PWRITE && !tip)
      begin
          ctrl[`SPI_CTRL_BIT_NB-1:0] <= #Tp PWDATA[`SPI_CTRL_BIT_NB-1:0];
      end
    else if(tip && last_bit && pos_edge)
      ctrl[`SPI_CTRL_GO] <= #Tp 1'b0;
  end
  
  assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE];
  assign tx_negedge = ctrl[`SPI_CTRL_TX_NEGEDGE];
  assign go         = ctrl[`SPI_CTRL_GO];
  assign char_len   = ctrl[`SPI_CTRL_CHAR_LEN];
  assign lsb        = ctrl[`SPI_CTRL_LSB];
  assign ie         = ctrl[`SPI_CTRL_IE];
  assign ass        = ctrl[`SPI_CTRL_ASS];
  

  always @(posedge PCLK or negedge PRESETN)
  begin
    if (PRESETN == 0)
      ss <= #Tp {`SPI_SS_NB{1'b0}};
    else if(spi_ss_sel && PWRITE && !tip)
      begin
      `ifdef SPI_SS_NB_8
          ss <= #Tp PWDATA[`SPI_SS_NB-1:0];
      `endif
      `ifdef SPI_SS_NB_16
          ss[`SPI_SS_NB-1:0] <= #Tp PWDATA[`SPI_SS_NB-1:0];
      `endif
      `ifdef SPI_SS_NB_24
          ss[`SPI_SS_NB-1:0] <= #Tp PWDATA[`SPI_SS_NB-1:0];
      `endif
      `ifdef SPI_SS_NB_32
          ss[`SPI_SS_NB-1:0] <= #Tp PWDATA[`SPI_SS_NB-1:0];
      `endif
      end
  end
  
  assign ss_pad_o = ~((ss & {`SPI_SS_NB{tip & ass}}) | (ss & {`SPI_SS_NB{!ass}}));
  
  spi_clgen clgen (.clk_in(PCLK), .rst(!PRESETN), .go(go), .enable(tip), .last_clk(last_bit),
                   .divider(divider), .clk_out(sclk_pad_o), .pos_edge(pos_edge), 
                   .neg_edge(neg_edge));
  
  spi_shift shift (.clk(PCLK), .rst(!PRESETN), .len(char_len[`SPI_CHAR_LEN_BITS-1:0]),
                   .latch(spi_tx_sel[3:0] & {4{PWRITE}}), .byte_sel(4'hF), .lsb(lsb), 
                   .go(go), .pos_edge(pos_edge), .neg_edge(neg_edge), 
                   .rx_negedge(rx_negedge), .tx_negedge(tx_negedge),
                   .tip(tip), .last(last_bit), 
                   .p_in(PWDATA), .p_out(rx), 
                   .s_clk(sclk_pad_o), .s_in(miso_pad_i), .s_out(mosi_pad_o));
endmodule