data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_simple_if.v
data/verilator_xmls/491ad51a-ab53-4033-b344-4c0e42c9285a.xml
module simple_if();

reg latch;
wire enable,din;

always @ (enable or din)
if (enable) begin
  latch <= din;
end  

endmodule
module simple_if();


reg latch;
wire enable,din;

always @ (enable or din)
if (enable) begin
  latch <= din;
end  

endmodule