data/full_repos/permissive/456468799/Verilog/VideoControl.v
data/verilator_xmls/2783d2d3-2d2c-435b-84d6-f605ae8ce918.xml
module VideoControl(input CLK_n,
                    input DISPEN_BUF,
                    input S5,
                    input S6,
                    input PHI_n,
                    input[1 : 0] MODE,
                    input MODE_SYNC,
                    output LOAD,
                    output COLOUR_KEEP,
                    output INK_SEL,
                    output BORDER_SEL,
                    output SHIFT,
                    output KEEP,
                    output MODE_IS_0,
                    output MODE_IS_2);
  reg _mode_is_0;
  reg _mode_is_1;
  reg _mode_is_2;

  always
    @(posedge MODE_SYNC)
      begin
        _mode_is_2 <= ~MODE[0] & MODE[1];
        _mode_is_1 <= MODE[0] & ~MODE[1];
        _mode_is_0 <= ~MODE[0] & ~MODE[1];
      end
  assign MODE_IS_0 = _mode_is_0;
  assign MODE_IS_2 = _mode_is_2;
  reg u1005,
      u1013,
      u1007,
      _load,
      _colour_keep,
      _ink_sel,
      _border_sel,
      _shift,
      _keep;
  wire u1008 = _load ? DISPEN_BUF : u1005;
  wire u1017 = _mode_is_2 | (_mode_is_1 & u1013) | (u1013 & u1007);
  always
    @(posedge CLK_n)
      begin
        _load <= S5 ^ S6;
        u1007 <= ~PHI_n;
        u1005 <= u1008;
        u1013 <= _load | ~u1013;
        _colour_keep <= ~(u1013 | _mode_is_2);
        _ink_sel <= (u1013 | _mode_is_2) & u1008;
        _border_sel <= (u1013 | _mode_is_2) & ~u1008;
        _shift <= u1017 & ~(S5 ^ S6);
        _keep <= ~u1017;
      end
  assign LOAD = _load;
  assign COLOUR_KEEP = _colour_keep;
  assign INK_SEL = _ink_sel;
  assign BORDER_SEL = _border_sel;
  assign SHIFT = _shift;
  assign KEEP = _keep;
endmodule
module VideoControl(input CLK_n,
                    input DISPEN_BUF,
                    input S5,
                    input S6,
                    input PHI_n,
                    input[1 : 0] MODE,
                    input MODE_SYNC,
                    output LOAD,
                    output COLOUR_KEEP,
                    output INK_SEL,
                    output BORDER_SEL,
                    output SHIFT,
                    output KEEP,
                    output MODE_IS_0,
                    output MODE_IS_2);

  reg _mode_is_0;
  reg _mode_is_1;
  reg _mode_is_2;

  always
    @(posedge MODE_SYNC)
      begin
        _mode_is_2 <= ~MODE[0] & MODE[1];
        _mode_is_1 <= MODE[0] & ~MODE[1];
        _mode_is_0 <= ~MODE[0] & ~MODE[1];
      end
  assign MODE_IS_0 = _mode_is_0;
  assign MODE_IS_2 = _mode_is_2;
  reg u1005,
      u1013,
      u1007,
      _load,
      _colour_keep,
      _ink_sel,
      _border_sel,
      _shift,
      _keep;
  wire u1008 = _load ? DISPEN_BUF : u1005;
  wire u1017 = _mode_is_2 | (_mode_is_1 & u1013) | (u1013 & u1007);
  always
    @(posedge CLK_n)
      begin
        _load <= S5 ^ S6;
        u1007 <= ~PHI_n;
        u1005 <= u1008;
        u1013 <= _load | ~u1013;
        _colour_keep <= ~(u1013 | _mode_is_2);
        _ink_sel <= (u1013 | _mode_is_2) & u1008;
        _border_sel <= (u1013 | _mode_is_2) & ~u1008;
        _shift <= u1017 & ~(S5 ^ S6);
        _keep <= ~u1017;
      end
  assign LOAD = _load;
  assign COLOUR_KEEP = _colour_keep;
  assign INK_SEL = _ink_sel;
  assign BORDER_SEL = _border_sel;
  assign SHIFT = _shift;
  assign KEEP = _keep;
endmodule