data/full_repos/permissive/423547971/FPGA Projects/Nexys to Basys Test 1(ROM to RAM)/Nexys Video part/nexys_top.v
1: b'%Error: Cannot find file containing module: Projects/Nexys\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/Nexys\n             data/full_repos/permissive/423547971/FPGA/Projects/Nexys.v\n             data/full_repos/permissive/423547971/FPGA/Projects/Nexys.sv\n             Projects/Nexys\n             Projects/Nexys.v\n             Projects/Nexys.sv\n             obj_dir/Projects/Nexys\n             obj_dir/Projects/Nexys.v\n             obj_dir/Projects/Nexys.sv\n%Error: Cannot find file containing module: to\n%Error: Cannot find file containing module: Basys\n%Error: Cannot find file containing module: Test\n%Error: Cannot find file containing module: 1(ROM\n%Error: Cannot find file containing module: RAM)/Nexys\n%Error: Cannot find file containing module: Video\n%Error: Cannot find file containing module: part,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: part/nexys_top.v\n%Error: Exiting due to 10 error(s)\n'
module nexys_top(
    input clk,
    output o_1Hz,
    output [3:0] o_data,
    output wr_en,
    output [3:0] o_addr,
    output [3:0] led
    );
    
    wire w_1Hz;
    wire [3:0] w_addr;
    wire [3:0] w_data;
    
    rom r(.addr(w_addr), .data(w_data));
    rom_control rc(.clk_1Hz(w_1Hz), .addr(w_addr), .wr_en(wr_en));
    oneHz_gen uno(.clk(clk), .clk_1Hz(w_1Hz));
    
    assign o_addr = w_addr;
    assign o_data = w_data;
    assign led = w_data;
    assign o_1Hz = w_1Hz;
    
endmodule
module nexys_top(
    input clk,
    output o_1Hz,
    output [3:0] o_data,
    output wr_en,
    output [3:0] o_addr,
    output [3:0] led
    );

    
    wire w_1Hz;
    wire [3:0] w_addr;
    wire [3:0] w_data;
    
    rom r(.addr(w_addr), .data(w_data));
    rom_control rc(.clk_1Hz(w_1Hz), .addr(w_addr), .wr_en(wr_en));
    oneHz_gen uno(.clk(clk), .clk_1Hz(w_1Hz));
    
    assign o_addr = w_addr;
    assign o_data = w_data;
    assign led = w_data;
    assign o_1Hz = w_1Hz;
    
endmodule