data/full_repos/permissive/457911422/Slave.v
data/verilator_xmls/7a6c2b04-08c7-4ac7-acc4-84c23d46eca5.xml
module Slave(
input wire reset,
input wire [7:0] slaveDataToSend, 
output reg [7:0] slaveDataReceived,
input wire sclk,
input wire CS,
input wire MOSI,
output reg MISO
);

reg [7:0] Register;

reg flag = 0;

always @(negedge CS or posedge reset)
begin
if (CS == 0) begin
	Register <= slaveDataToSend;
	slaveDataReceived <= 8'bxxxxxxxx;
	flag <= 1;
end
if (reset) begin
	Register <= 0;
end

end

always @(posedge CS) begin
	flag <= 0;
	MISO <= 1'bz;
end

always @(posedge sclk)
begin
if (flag) begin
	Register <= Register >> 1;
	MISO <= Register[0];
end
end

always @ (negedge sclk)
begin
if (flag) begin
	Register[7] = MOSI;
	slaveDataReceived <= {MOSI, slaveDataReceived[7:1]};
end
end
endmodule
module Slave(
input wire reset,
input wire [7:0] slaveDataToSend, 
output reg [7:0] slaveDataReceived,
input wire sclk,
input wire CS,
input wire MOSI,
output reg MISO
);


reg [7:0] Register;

reg flag = 0;

always @(negedge CS or posedge reset)
begin
if (CS == 0) begin
	Register <= slaveDataToSend;
	slaveDataReceived <= 8'bxxxxxxxx;
	flag <= 1;
end
if (reset) begin
	Register <= 0;
end

end

always @(posedge CS) begin
	flag <= 0;
	MISO <= 1'bz;
end

always @(posedge sclk)
begin
if (flag) begin
	Register <= Register >> 1;
	MISO <= Register[0];
end
end

always @ (negedge sclk)
begin
if (flag) begin
	Register[7] = MOSI;
	slaveDataReceived <= {MOSI, slaveDataReceived[7:1]};
end
end
endmodule