data/full_repos/permissive/467394306/rtl/esp_wrapper.sv
1: b'%Error: data/full_repos/permissive/467394306/rtl/esp_wrapper.sv:198: syntax error, unexpected endcase\n                        endcase\n                        ^~~~~~~\n%Error: data/full_repos/permissive/467394306/rtl/esp_wrapper.sv:216: syntax error, unexpected end, expecting endcase\n            end\n            ^~~\n%Error: Cannot continue\n'
module SYSTOLA_ESP_WRAPPER (clk, rst, dma_read_chnl_valid, dma_read_chnl_data, dma_read_chnl_ready,

conf_info_depth, conf_done, acc_done, debug, 
dma_read_ctrl_valid, dma_read_ctrl_data_index, dma_read_ctrl_data_length, dma_read_ctrl_data_size, dma_read_ctrl_ready, 
dma_write_ctrl_valid, dma_write_ctrl_data_index, dma_write_ctrl_data_length, dma_write_ctrl_data_size, dma_write_ctrl_ready, 
dma_write_chnl_valid, dma_write_chnl_data, dma_write_chnl_ready);

    input clk;
    input rst;


    input [31:0]  conf_info_depth;
    input conf_done;

    input dma_read_ctrl_ready;
    output reg dma_read_ctrl_valid;
    output reg [31:0] dma_read_ctrl_data_index;
    output reg [31:0] dma_read_ctrl_data_length;
    output reg [2:0]  dma_read_ctrl_data_size;

    output reg dma_read_chnl_ready;
    input dma_read_chnl_valid;
    input [31:0]  dma_read_chnl_data;

    input dma_write_ctrl_ready;
    output dma_write_ctrl_valid;
    output reg [31:0] dma_write_ctrl_data_index;
    output reg [31:0] dma_write_ctrl_data_length;
    output reg [2:0]  dma_write_ctrl_data_size;

    input dma_write_chnl_ready;
    output reg dma_write_chnl_valid;
    output reg [31:0] dma_write_chnl_data;

    output reg acc_done;
    output reg [31:0] debug;













































    wire rstn;
    assign rstn = rst;


    reg [10:0] A0, A1;
    reg [7:0] D0, D1;
    wire [7:0] Q0, Q1;
    reg CE0, CE1, WE0, WE1;
    reg [7:0] WEM0, WEM1;

    BRAM_2048x8 plm (.clk(),
        .A0(A0),
        .D0(D0),
        .Q0(Q0),
        .WE0(WE0),
        .WEM0(WEM0),
        .CE0(CE0),
        .A1(A1),
        .D1(D1),
        .Q1(Q1),
        .WE1(WE1),
        .WEM1(WEM1),
        .CE1(CE1)
    );






    reg start;
    reg [1:0] state;    





    reg [1:0] cnt;
    reg [1:0] stateaux;

    reg [63:0] dmabuf;
    reg [31:0] beatit;


    reg inptarget;

    always @ (posedge clk) begin
        if (!rstn) begin

            start <= 0;
            state <= 0;

            inptarget <= 0;
            cnt <= 0;
            stateaux <= 0;
            beatit <= 0;
            

            A0 <= 0;    A1 <= 0;
            D0 <= 0;    D1 <= 0;
            CE0 <= 0;   CE1 <= 0;
            WE0 <= 0;   WE1 <= 0;
            WEM0 <= 0;  WEM1 <= 0;

        end else begin
            if (start) begin
                case (state)
                    2'b00 : begin





                        case (stateaux)
                            2'b00 : begin
                                dma_read_ctrl_valid <= 1;
                                dma_read_chnl_ready <= 0;
                                dma_read_ctrl_data_index <= 0;
                                dma_read_ctrl_data_length <= depth;
                                dma_read_ctrl_data_size <= 011;
                                dma_read_chnl_ready <= 1;

                                if(dma_read_ctrl_valid && dma_read_ctrl_ready) begin
                                    dmabuf <= dma_read_chnl_data;
                                    dma_read_chnl_ready <= 0;
                                    
                                end
                            end 
                            default: 
                        endcase
                    end

                    2'b01 : begin

                    end
                    2'b10 : begin

                    end
                    2'b11 : beginw
                        acc_done <= 1;
                    end
                endcase
            end else begin
                if (conf_done) begin
                    start <= 1;
                    cnt <= 0;
                end
            end
        end
    end



endmodule
module SYSTOLA_ESP_WRAPPER (clk, rst, dma_read_chnl_valid, dma_read_chnl_data, dma_read_chnl_ready,

conf_info_depth, conf_done, acc_done, debug, 
dma_read_ctrl_valid, dma_read_ctrl_data_index, dma_read_ctrl_data_length, dma_read_ctrl_data_size, dma_read_ctrl_ready, 
dma_write_ctrl_valid, dma_write_ctrl_data_index, dma_write_ctrl_data_length, dma_write_ctrl_data_size, dma_write_ctrl_ready, 
dma_write_chnl_valid, dma_write_chnl_data, dma_write_chnl_ready);


    input clk;
    input rst;


    input [31:0]  conf_info_depth;
    input conf_done;

    input dma_read_ctrl_ready;
    output reg dma_read_ctrl_valid;
    output reg [31:0] dma_read_ctrl_data_index;
    output reg [31:0] dma_read_ctrl_data_length;
    output reg [2:0]  dma_read_ctrl_data_size;

    output reg dma_read_chnl_ready;
    input dma_read_chnl_valid;
    input [31:0]  dma_read_chnl_data;

    input dma_write_ctrl_ready;
    output dma_write_ctrl_valid;
    output reg [31:0] dma_write_ctrl_data_index;
    output reg [31:0] dma_write_ctrl_data_length;
    output reg [2:0]  dma_write_ctrl_data_size;

    input dma_write_chnl_ready;
    output reg dma_write_chnl_valid;
    output reg [31:0] dma_write_chnl_data;

    output reg acc_done;
    output reg [31:0] debug;













































    wire rstn;
    assign rstn = rst;


    reg [10:0] A0, A1;
    reg [7:0] D0, D1;
    wire [7:0] Q0, Q1;
    reg CE0, CE1, WE0, WE1;
    reg [7:0] WEM0, WEM1;

    BRAM_2048x8 plm (.clk(),
        .A0(A0),
        .D0(D0),
        .Q0(Q0),
        .WE0(WE0),
        .WEM0(WEM0),
        .CE0(CE0),
        .A1(A1),
        .D1(D1),
        .Q1(Q1),
        .WE1(WE1),
        .WEM1(WEM1),
        .CE1(CE1)
    );






    reg start;
    reg [1:0] state;    





    reg [1:0] cnt;
    reg [1:0] stateaux;

    reg [63:0] dmabuf;
    reg [31:0] beatit;


    reg inptarget;

    always @ (posedge clk) begin
        if (!rstn) begin

            start <= 0;
            state <= 0;

            inptarget <= 0;
            cnt <= 0;
            stateaux <= 0;
            beatit <= 0;
            

            A0 <= 0;    A1 <= 0;
            D0 <= 0;    D1 <= 0;
            CE0 <= 0;   CE1 <= 0;
            WE0 <= 0;   WE1 <= 0;
            WEM0 <= 0;  WEM1 <= 0;

        end else begin
            if (start) begin
                case (state)
                    2'b00 : begin





                        case (stateaux)
                            2'b00 : begin
                                dma_read_ctrl_valid <= 1;
                                dma_read_chnl_ready <= 0;
                                dma_read_ctrl_data_index <= 0;
                                dma_read_ctrl_data_length <= depth;
                                dma_read_ctrl_data_size <= 011;
                                dma_read_chnl_ready <= 1;

                                if(dma_read_ctrl_valid && dma_read_ctrl_ready) begin
                                    dmabuf <= dma_read_chnl_data;
                                    dma_read_chnl_ready <= 0;
                                    
                                end
                            end 
                            default: 
                        endcase
                    end

                    2'b01 : begin

                    end
                    2'b10 : begin

                    end
                    2'b11 : beginw
                        acc_done <= 1;
                    end
                endcase
            end else begin
                if (conf_done) begin
                    start <= 1;
                    cnt <= 0;
                end
            end
        end
    end



endmodule