data/full_repos/permissive/52714256/GYRACC/src/clk_div.v
data/verilator_xmls/79147c5e-98da-4dc2-9f57-0dc2e15580db.xml
module CLK_DIV
    (
    input wire GCLK,
    output reg out = 1'b0,
    input wire [63:0] T
    );
    
    reg [63:0] cnt = 64'd0;
    always @(posedge GCLK) begin
        if (cnt == 64'd0) begin
            cnt <= T;
            out <= ~out;
        end
        else begin
            cnt <= cnt - 64'd1;
        end
    
    end
endmodule
module CLK_DIV
    (
    input wire GCLK,
    output reg out = 1'b0,
    input wire [63:0] T
    );

    
    reg [63:0] cnt = 64'd0;
    always @(posedge GCLK) begin
        if (cnt == 64'd0) begin
            cnt <= T;
            out <= ~out;
        end
        else begin
            cnt <= cnt - 64'd1;
        end
    
    end
endmodule