data/full_repos/permissive/475432092/bujbdmjimdisffpwqi/Divider100MHz.v
1: b'%Warning-WIDTH: data/full_repos/permissive/475432092/bujbdmjimdisffpwqi/Divider100MHz.v:35: Operator LT expects 32 or 27 bits on the LHS, but LHS\'s VARREF \'Count_DIV\' generates 26 bits.\n                                                                                          : ... In instance Divider100MHz\n   if (Count_DIV < CLK_Freq / (2 * OUT_Freq) - 1) begin\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Divider100MHz(CP_100MHz, nCLR, CP_1Hz);
	parameter N = 26;
	parameter CLK_Freq = 100000000;
	parameter OUT_Freq = 1;
	input nCLR, CP_100MHz;
	output reg CP_1Hz;
	reg [N - 1:0] Count_DIV;
	always @(posedge CP_100MHz or negedge nCLR) begin
		if (! nCLR) begin
			CP_1Hz <= 0;
			Count_DIV <= 0;
		end
		else begin
			if (Count_DIV < CLK_Freq / (2 * OUT_Freq) - 1) begin
				Count_DIV <= Count_DIV + 1'b1;
			end
			else begin
				Count_DIV <= 0;
				CP_1Hz <= ~ CP_1Hz;
			end
		end
	end
endmodule
module Divider100MHz(CP_100MHz, nCLR, CP_1Hz);

	parameter N = 26;
	parameter CLK_Freq = 100000000;
	parameter OUT_Freq = 1;
	input nCLR, CP_100MHz;
	output reg CP_1Hz;
	reg [N - 1:0] Count_DIV;
	always @(posedge CP_100MHz or negedge nCLR) begin
		if (! nCLR) begin
			CP_1Hz <= 0;
			Count_DIV <= 0;
		end
		else begin
			if (Count_DIV < CLK_Freq / (2 * OUT_Freq) - 1) begin
				Count_DIV <= Count_DIV + 1'b1;
			end
			else begin
				Count_DIV <= 0;
				CP_1Hz <= ~ CP_1Hz;
			end
		end
	end
endmodule