data/full_repos/permissive/504677412/src/fifo_top/afifo_fwft_36x512.v
1: b'%Error: data/full_repos/permissive/504677412/src/fifo_top/afifo_fwft_36x512.v:23: syntax error, unexpected IDENTIFIER\nFVbvHIKTe7IJ+9OrVDI9pFzyvQUGTGYmY7KspW80hZOIgMFXLIjI2idaZfM7xRLXshBrWbo7pyKC\n^~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n'
module afifo_fwft_36x512 (
  Data,
  WrReset,
  RdReset,
  WrClk,
  RdClk,
  WrEn,
  RdEn,
  Rnum,
  Almost_Full,
  Q,
  Empty,
  Full
)
;
input [35:0] Data;
input WrReset;
input RdReset;
input WrClk;
input RdClk;
input WrEn;
input RdEn;
output [9:0] Rnum;
output Almost_Full;
output [35:0] Q;
output Empty;
output Full;
wire VCC;
wire GND;
  \~fifo.afifo_fwft_36x512  fifo_inst (
    .RdClk(RdClk),
    .RdReset(RdReset),
    .WrClk(WrClk),
    .WrReset(WrReset),
    .WrEn(WrEn),
    .RdEn(RdEn),
    .Data(Data[35:0]),
    .Full(Full),
    .Almost_Full(Almost_Full),
    .Empty(Empty),
    .Rnum(Rnum[9:0]),
    .Q(Q[35:0])
);
  VCC VCC_cZ (
    .V(VCC)
);
  GND GND_cZ (
    .G(GND)
);
  GSR GSR (
    .GSRI(VCC) 
);
endmodule
module afifo_fwft_36x512 (
  Data,
  WrReset,
  RdReset,
  WrClk,
  RdClk,
  WrEn,
  RdEn,
  Rnum,
  Almost_Full,
  Q,
  Empty,
  Full
)
;

input [35:0] Data;
input WrReset;
input RdReset;
input WrClk;
input RdClk;
input WrEn;
input RdEn;
output [9:0] Rnum;
output Almost_Full;
output [35:0] Q;
output Empty;
output Full;
wire VCC;
wire GND;
  \~fifo.afifo_fwft_36x512  fifo_inst (
    .RdClk(RdClk),
    .RdReset(RdReset),
    .WrClk(WrClk),
    .WrReset(WrReset),
    .WrEn(WrEn),
    .RdEn(RdEn),
    .Data(Data[35:0]),
    .Full(Full),
    .Almost_Full(Almost_Full),
    .Empty(Empty),
    .Rnum(Rnum[9:0]),
    .Q(Q[35:0])
);
  VCC VCC_cZ (
    .V(VCC)
);
  GND GND_cZ (
    .G(GND)
);
  GSR GSR (
    .GSRI(VCC) 
);
endmodule