data/full_repos/permissive/423547971/10 Verilog Projects Book/Section_1/d_ff_TB.v
1: b'%Error: Cannot find file containing module: Verilog\n        ... Looked in:\n             data/full_repos/permissive/423547971/10/Verilog\n             data/full_repos/permissive/423547971/10/Verilog.v\n             data/full_repos/permissive/423547971/10/Verilog.sv\n             Verilog\n             Verilog.v\n             Verilog.sv\n             obj_dir/Verilog\n             obj_dir/Verilog.v\n             obj_dir/Verilog.sv\n%Error: Cannot find file containing module: Projects\n%Error: Cannot find file containing module: Book/Section_1,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/10\n%Error: Cannot find file containing module: Book/Section_1/d_ff_TB.v\n%Error: Exiting due to 5 error(s)\n'
module d_ff_TB;
	reg  clock;
	reg  reset;
	reg  data_in;
	wire q;

	d_ff DUT(.clock(clock), .reset(reset), 
			 .data_in(data_in), .q(q));

	always #2 clock = ~clock;
	
	initial begin
		$dumpfile("d_ff_TB.vcd");
		$dumpvars(0, d_ff_TB);
	end
	
	initial begin
		clock = 0;
		reset = 0;
		data_in = 0;		
		
		#9 reset = 1;
		   data_in = 1;
		
		#4 data_in = 0;
		#4 data_in = 1;
		#4 reset = 0;
		#4 reset = 1;
		
		#4 $finish;
	end
	
endmodule
module d_ff_TB;

	reg  clock;
	reg  reset;
	reg  data_in;
	wire q;

	d_ff DUT(.clock(clock), .reset(reset), 
			 .data_in(data_in), .q(q));

	always #2 clock = ~clock;
	
	initial begin
		$dumpfile("d_ff_TB.vcd");
		$dumpvars(0, d_ff_TB);
	end
	
	initial begin
		clock = 0;
		reset = 0;
		data_in = 0;		
		
		#9 reset = 1;
		   data_in = 1;
		
		#4 data_in = 0;
		#4 data_in = 1;
		#4 reset = 0;
		#4 reset = 1;
		
		#4 $finish;
	end
	
endmodule