data/full_repos/permissive/515133384/Verilog Code for Design part.v
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/515133384/Verilog\n        ... Looked in:\n             data/full_repos/permissive/515133384,data/full_repos/permissive/515133384/data/full_repos/permissive/515133384/Verilog\n             data/full_repos/permissive/515133384,data/full_repos/permissive/515133384/data/full_repos/permissive/515133384/Verilog.v\n             data/full_repos/permissive/515133384,data/full_repos/permissive/515133384/data/full_repos/permissive/515133384/Verilog.sv\n             data/full_repos/permissive/515133384/Verilog\n             data/full_repos/permissive/515133384/Verilog.v\n             data/full_repos/permissive/515133384/Verilog.sv\n             obj_dir/data/full_repos/permissive/515133384/Verilog\n             obj_dir/data/full_repos/permissive/515133384/Verilog.v\n             obj_dir/data/full_repos/permissive/515133384/Verilog.sv\n%Error: Cannot find file containing module: Code\n%Error: Cannot find file containing module: for\n%Error: Cannot find file containing module: Design\n%Error: Cannot find file containing module: part.v\n%Error: Exiting due to 5 error(s)\n'
module mainckt1(.A0(A0),.B0(B0),.Cin0(Cin0),.S0(S0),.C0(C0),.A1(A1),.B1(B1),.Cin1(Cin1),.S1(S1),.C1(C1),.A2(A2),.B2(B2),.Cin2(Cin2),.S2(S2),.C2(C2),.out0(out0),.c0(c0),.A3(A3),.B3(B3),.Cin3(Cin3),.S3(S3),.C3(C3),.A4(A4),.B4(B4),.Cin4(Cin4),.S4(S4),.C4(C4),.out1(out1),.cout(cout),.Sout(Sout),.Cout(Cout),.c1(c1),.Cx0(Cx0),.Cx1(Cx1),.Cx2(Cx2),.Cx3(Cx3),.Cx4(Cx4));
  input [1:0]A0,B0;
  output reg[2:0]Cx0;
  output reg[3:0]Cx1,Cx2;
  output reg[4:0]Cx3,Cx4;
  input [2:0]A1,B1,A2,B2;
  input [3:0]A3,B3,A4,B4;
  input Cin0,Cin1,Cin2,Cin3,Cin4;

  output reg[8:0]Sout;
  output reg Cout;
  inout [1:0]S0;
  inout [2:0]S1,S2;
  inout [3:0]S3,S4;
  
  inout cout;
  inout [3:0]out0;
  inout [4:0]out1;
  inout C0,C1,C2,C3,C4;

  inout c0;

  inout c1;
 
 
  defparam a0.N=2;
  defparam a1.N=3;
  defparam a2.N=3;
  defparam b0.N=3;
  defparam a3.N=4;
  defparam a4.N=4;
  defparam b1.N=4;
  CLA a0 (A0, B0, Cin0, S0, C0, Cx0);

  CLA a1 (A1,B1,Cin1,S1,C1, Cx1);

  CLA a2 (A2,B2,Cin2,S2,C2, Cx2);

  mux2x1 b0({C1,S1},{C2,S2},C0,out0);


  parameter N=4;
  assign c0=out0[N-1];
  CLA a3 (A3,B3,Cin3,S3,C3, Cx3);

  CLA a4 (A4,B4,Cin4,S4,C4, Cx4);

  mux2x1 b1({C3,S3},{C4,S4},c0,out1);


  parameter N1=5;
  assign c1=out1[N1-1];
  assign Sout={out1[N1-2:0],out0[N-2:0],S0};
  assign Cout=c1;
endmodule
module mainckt1(.A0(A0),.B0(B0),.Cin0(Cin0),.S0(S0),.C0(C0),.A1(A1),.B1(B1),.Cin1(Cin1),.S1(S1),.C1(C1),.A2(A2),.B2(B2),.Cin2(Cin2),.S2(S2),.C2(C2),.out0(out0),.c0(c0),.A3(A3),.B3(B3),.Cin3(Cin3),.S3(S3),.C3(C3),.A4(A4),.B4(B4),.Cin4(Cin4),.S4(S4),.C4(C4),.out1(out1),.cout(cout),.Sout(Sout),.Cout(Cout),.c1(c1),.Cx0(Cx0),.Cx1(Cx1),.Cx2(Cx2),.Cx3(Cx3),.Cx4(Cx4));

  input [1:0]A0,B0;
  output reg[2:0]Cx0;
  output reg[3:0]Cx1,Cx2;
  output reg[4:0]Cx3,Cx4;
  input [2:0]A1,B1,A2,B2;
  input [3:0]A3,B3,A4,B4;
  input Cin0,Cin1,Cin2,Cin3,Cin4;

  output reg[8:0]Sout;
  output reg Cout;
  inout [1:0]S0;
  inout [2:0]S1,S2;
  inout [3:0]S3,S4;
  
  inout cout;
  inout [3:0]out0;
  inout [4:0]out1;
  inout C0,C1,C2,C3,C4;

  inout c0;

  inout c1;
 
 
  defparam a0.N=2;
  defparam a1.N=3;
  defparam a2.N=3;
  defparam b0.N=3;
  defparam a3.N=4;
  defparam a4.N=4;
  defparam b1.N=4;
  CLA a0 (A0, B0, Cin0, S0, C0, Cx0);

  CLA a1 (A1,B1,Cin1,S1,C1, Cx1);

  CLA a2 (A2,B2,Cin2,S2,C2, Cx2);

  mux2x1 b0({C1,S1},{C2,S2},C0,out0);


  parameter N=4;
  assign c0=out0[N-1];
  CLA a3 (A3,B3,Cin3,S3,C3, Cx3);

  CLA a4 (A4,B4,Cin4,S4,C4, Cx4);

  mux2x1 b1({C3,S3},{C4,S4},c0,out1);


  parameter N1=5;
  assign c1=out1[N1-1];
  assign Sout={out1[N1-2:0],out0[N-2:0],S0};
  assign Cout=c1;
endmodule