data/full_repos/permissive/493019833/test/testcase/firrtl/ParameterizedNumberOperation/reference/ParameterizedNumberOperation.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/ParameterizedNumberOperation/reference/ParameterizedNumberOperation.v:61: Operator COND expects 48 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 24 bits.\n                                                                                                                                                  : ... In instance ParameterizedNumberOperation.s_pad_3\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/ParameterizedNumberOperation/reference/ParameterizedNumberOperation.v:54: Operator COND expects 24 bits on the Conditional False, but Conditional False\'s SEL generates 1 bits.\n                                                                                                                                                  : ... In instance ParameterizedNumberOperation.s_shr_2\n    assign y = n < width ? in[width-1:n] : in[width-1:width-1];\n                         ^\n%Error: Exiting due to 2 warning(s)\n'
module ParameterizedNumberOperation(
    input clock,
    input reset,
    input [15:0] io_a1,
    input [15:0] io_a2,
    output [47:0] io_c
);
    wire [47:0] _register1__q;
    wire [47:0] _register1__d;
    DFF_POSCLK #(.width(48)) register1 (
        .q(_register1__q),
        .d(_register1__d),
        .clk(clock)
    );
    wire [31:0] _T_10;
    MUL2_SIGNED #(.width_a(16), .width_b(16)) s_mul2_1 (
        .y(_T_10),
        .a(io_a1),
        .b(io_a2)
    );
    wire [23:0] _node_0;
    SHR_SIGNED #(.width(32), .n(8)) s_shr_2 (
        .y(_node_0),
        .in(_T_10)
    );
    assign io_c = _register1__q;
    PAD_SIGNED #(.width(24), .n(48)) s_pad_3 (
        .y(_register1__d),
        .in(_node_0)
    );
endmodule
module ParameterizedNumberOperation(
    input clock,
    input reset,
    input [15:0] io_a1,
    input [15:0] io_a2,
    output [47:0] io_c
);

    wire [47:0] _register1__q;
    wire [47:0] _register1__d;
    DFF_POSCLK #(.width(48)) register1 (
        .q(_register1__q),
        .d(_register1__d),
        .clk(clock)
    );
    wire [31:0] _T_10;
    MUL2_SIGNED #(.width_a(16), .width_b(16)) s_mul2_1 (
        .y(_T_10),
        .a(io_a1),
        .b(io_a2)
    );
    wire [23:0] _node_0;
    SHR_SIGNED #(.width(32), .n(8)) s_shr_2 (
        .y(_node_0),
        .in(_T_10)
    );
    assign io_c = _register1__q;
    PAD_SIGNED #(.width(24), .n(48)) s_pad_3 (
        .y(_register1__d),
        .in(_node_0)
    );
endmodule