data/full_repos/permissive/493441306/Verilog Language/more_verilog_features/03_vector100r.v
1: b'%Error: Cannot find file containing module: Language/more_verilog_features,data/full_repos/permissive/493441306\n        ... Looked in:\n             data/full_repos/permissive/493441306/Verilog/Language/more_verilog_features,data/full_repos/permissive/493441306\n             data/full_repos/permissive/493441306/Verilog/Language/more_verilog_features,data/full_repos/permissive/493441306.v\n             data/full_repos/permissive/493441306/Verilog/Language/more_verilog_features,data/full_repos/permissive/493441306.sv\n             Language/more_verilog_features,data/full_repos/permissive/493441306\n             Language/more_verilog_features,data/full_repos/permissive/493441306.v\n             Language/more_verilog_features,data/full_repos/permissive/493441306.sv\n             obj_dir/Language/more_verilog_features,data/full_repos/permissive/493441306\n             obj_dir/Language/more_verilog_features,data/full_repos/permissive/493441306.v\n             obj_dir/Language/more_verilog_features,data/full_repos/permissive/493441306.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/493441306/Verilog\n%Error: Cannot find file containing module: Language/more_verilog_features/03_vector100r.v\n%Error: Exiting due to 3 error(s)\n'
module top_module( 
    input [99:0] in,
    output [99:0] out
);
    integer i;
    always@(*) begin
        for(i=0;i<=99;i++)
            out[i] = in[99-i];
    end

endmodule
module top_module( 
    input [99:0] in,
    output [99:0] out
);

    integer i;
    always@(*) begin
        for(i=0;i<=99;i++)
            out[i] = in[99-i];
    end

endmodule