data/full_repos/permissive/420501560/fpga/electronic-geartrain.srcs/sources_1/new/controller.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/420501560/fpga/electronic-geartrain.srcs/sources_1/new/controller.v:76: Signal definition not found, creating implicitly: \'out_step\'\n  assign out_step = step_select(mode, rpm_step, axis_step, divider_step);\n         ^~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/420501560/fpga/electronic-geartrain.srcs/sources_1/new/controller.v:79: Operator CASE expects 32 or 2 bits on the Case expression, but Case expression\'s VARREF \'mode\' generates 1 bits.\n                                                                                                                 : ... In instance controller\n    case (mode)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/420501560/fpga/electronic-geartrain.srcs/sources_1/new/controller.v:76: Operator FUNCREF \'step_select\' expects 1 bits on the Function Argument, but Function Argument\'s VARREF \'mode\' generates 2 bits.\n                                                                                                                 : ... In instance controller\n  assign out_step = step_select(mode, rpm_step, axis_step, divider_step);\n                    ^~~~~~~~~~~\n%Error: Exiting due to 3 warning(s)\n'
module track_position
(
  input step,
  input direction,
  output reg[31:0] pos
);
  always @(posedge step)
  begin
    if(direction)
    begin
      pos <= pos + 1;
    end
    else
    begin
      pos <= pos - 1;
    end
  end
endmodule
module track_position
(
  input step,
  input direction,
  output reg[31:0] pos
);

  always @(posedge step)
  begin
    if(direction)
    begin
      pos <= pos + 1;
    end
    else
    begin
      pos <= pos - 1;
    end
  end
endmodule