data/full_repos/permissive/423958267/lab02/lab02.srcs/sources_1/new/Counter.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/423958267/lab02/lab02.srcs/sources_1/new/Counter.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #0 counter = 0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Counter #(parameter N=20)(
    output reg [N-1:0] counter,
    input clk
);
    initial begin
        #0 counter = 0;
    end
    always @(posedge clk)
    begin
        counter <= counter + 1;
    end
endmodule
module Counter #(parameter N=20)(
    output reg [N-1:0] counter,
    input clk
);

    initial begin
        #0 counter = 0;
    end
    always @(posedge clk)
    begin
        counter <= counter + 1;
    end
endmodule