data/full_repos/permissive/491934675/ECE251/ALU/ALU.v
1: b'%Warning-WIDTH: data/full_repos/permissive/491934675/ECE251/ALU/ALU.v:48: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s NEQ generates 1 bits.\n                                                                        : ... In instance ALU\n                cmpreg = (A!=B);\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module ALU(
    input [3:0] opcase,
    input [2:0] shiftamt,
    input [7:0] A, B,
    output reg [7:0] out1,
    output wire [1:0] flags 
);
    reg [1:0] cmpflag;
    reg [7:0] cmpreg;
    always@(*)begin
        case(opcase[2:0])
        `NOT : out1 = ~A;
        `AND : out1 = A&B;
        `OR : out1 = A | B;
        `ADD : out1 = A + B;   
        `SUB : out1 = A - B; 
        default : out1 = 8'bzzzzzzzz;
        endcase

        if(opcase[3] == 0) begin
            case(opcase[2:0])
            `MUL_CMPI : out1 = A*B;
            `SIX : out1 = A >> shiftamt;
            `SVN : out1 = A << shiftamt; 
            endcase
        end

        if(opcase[3] == 1) begin
            case(opcase[2:0])
            `MUL_CMPI : begin
                out1 = 8'bzzzzzzzz;
                cmpreg = A - B;
                cmpreg = (A!=B);
                cmpflag[1] = (A>B);
                cmpflag[0] = (A != B);
            end
            endcase
        end
    end


    assign flags = cmpflag;

endmodule
module ALU(
    input [3:0] opcase,
    input [2:0] shiftamt,
    input [7:0] A, B,
    output reg [7:0] out1,
    output wire [1:0] flags 
);

    reg [1:0] cmpflag;
    reg [7:0] cmpreg;
    always@(*)begin
        case(opcase[2:0])
        `NOT : out1 = ~A;
        `AND : out1 = A&B;
        `OR : out1 = A | B;
        `ADD : out1 = A + B;   
        `SUB : out1 = A - B; 
        default : out1 = 8'bzzzzzzzz;
        endcase

        if(opcase[3] == 0) begin
            case(opcase[2:0])
            `MUL_CMPI : out1 = A*B;
            `SIX : out1 = A >> shiftamt;
            `SVN : out1 = A << shiftamt; 
            endcase
        end

        if(opcase[3] == 1) begin
            case(opcase[2:0])
            `MUL_CMPI : begin
                out1 = 8'bzzzzzzzz;
                cmpreg = A - B;
                cmpreg = (A!=B);
                cmpflag[1] = (A>B);
                cmpflag[0] = (A != B);
            end
            endcase
        end
    end


    assign flags = cmpflag;

endmodule