data/full_repos/permissive/441359809/src/yosys/manual/PRESENTATION_ExSyn/abc_01.v
data/verilator_xmls/adaa9be3-eca8-4c17-b54b-056ad025c9c9.xml
module test(input clk, a, b, c,
            output reg y);

	reg [2:0] q1, q2;
	always @(posedge clk) begin
		q1 <= { a, b, c };
		q2 <= q1;
		y <= ^q2;
	end
endmodule
module test(input clk, a, b, c,
            output reg y);


	reg [2:0] q1, q2;
	always @(posedge clk) begin
		q1 <= { a, b, c };
		q2 <= q1;
		y <= ^q2;
	end
endmodule