data/full_repos/permissive/444465810/func/axi/CP0.v
1: b"%Error: data/full_repos/permissive/444465810/func/axi/CP0.v:53: Cannot find file containing module: 'mux2'\n    mux2 MBDPC (\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/444465810/func/axi,data/full_repos/permissive/444465810/mux2\n             data/full_repos/permissive/444465810/func/axi,data/full_repos/permissive/444465810/mux2.v\n             data/full_repos/permissive/444465810/func/axi,data/full_repos/permissive/444465810/mux2.sv\n             mux2\n             mux2.v\n             mux2.sv\n             obj_dir/mux2\n             obj_dir/mux2.v\n             obj_dir/mux2.sv\n%Error: data/full_repos/permissive/444465810/func/axi/CP0.v:60: Cannot find file containing module: 'mux2'\n    mux2 MEPCIN (\n    ^~~~\n%Error: data/full_repos/permissive/444465810/func/axi/CP0.v:67: Cannot find file containing module: 'mux2'\n    mux2 MBADADDR (\n    ^~~~\n%Error: Exiting due to 3 error(s)\n"
module CP0(
    input clk,
    input rst,

    input [31:0] CP0_DATA_IN,
    input [31:0] CP0_PC_IN,
    input [15:0] CP0_CONTROL,
    output [31: 0] Status_OUT,          
    output [31: 0] Cause_OUT,
    output [31: 0] BadAddr_OUT,
    output [31: 0] EPC_OUT,
    output [31: 0] Count_OUT,
    output [31: 0] Compare_OUT,
    output INT
);

    reg [31: 0] EPC;

    reg [31: 0] BadVAddr;

    reg         Cause_BD;
    reg         Cause_TI;
    reg [5 : 0] Cause_IP_7_2;
    reg [1 : 0] Cause_IP_1_0;
    reg [4 : 0] Cause_ExcCode;

    reg [7 : 0] Status_IM_7_0;
    reg         Status_EXL;
    reg         Status_IE;

    reg [31: 0] Count;
    reg         tick;

    reg [31: 0] Compare; 


    assign Status_OUT  = { 9'b0, 1'b1,6'b0,Status_IM_7_0, 6'b0, Status_EXL, Status_IE };
    assign Cause_OUT   = { Cause_BD,15'b0, Cause_IP_7_2, Cause_IP_1_0, 1'b0, Cause_ExcCode, 2'b0 };
    assign BadAddr_OUT =   BadVAddr;
    assign EPC_OUT     =   EPC;
    assign Count_OUT   =   Count;
    assign Compare_OUT =   Compare;
    assign INT         =   ((Cause_IP_1_0 & Status_IM_7_0[1:0]) != 2'b00) & (Status_IE == 1'b1) & (Status_EXL == 1'b0);


    wire [31: 0] CP0_IN;
    wire [31: 0] BadAddr_IN;
    wire [31: 0] BDPC;
    
    mux2 MBDPC (
        .In0        ( CP0_PC_IN          ),
        .In1        ( CP0_PC_IN - 32'd4  ),
        .Op         ( CP0_CONTROL[6]     ),
        .Out        ( BDPC               )
    );
    
    mux2 MEPCIN (
        .In0        ( CP0_DATA_IN     ),
        .In1        ( BDPC            ),
        .Op         ( CP0_CONTROL[13] ),
        .Out        ( CP0_IN          )
    );
    
    mux2 MBADADDR (
        .In0    ( CP0_IN          ),
        .In1    ( CP0_DATA_IN     ),
        .Op     ( CP0_CONTROL[11] ),
        .Out    ( BadAddr_IN      )
    );
    
    
    always @(posedge clk)
    begin
        if(rst)
        begin
            EPC           <= 32'b0;
            BadVAddr      <= 32'b0;
            Cause_BD      <= 1'b0;
            Cause_TI      <= 1'b0;
            Cause_IP_7_2  <= 6'b0;
            Cause_IP_1_0  <= 2'b0;
            Cause_ExcCode <= 5'b0;
            Status_IM_7_0 <= 8'b0;

            Status_IE     <= 1'b0;
            Count         <= 32'b0;
            tick          <= 1'b0;
        end
        if(!rst)
            tick          <= ~tick;
        if (CP0_CONTROL[0])
        begin
            if(CP0_CONTROL[13] & Status_EXL)
                EPC <= EPC;
            else
                EPC <= CP0_IN;
        end
        if (CP0_CONTROL[12])
        begin
            BadVAddr <= BadAddr_IN;
        end
        if (CP0_CONTROL[10])
        begin
            Status_IM_7_0 <= CP0_IN[15: 8];

            Status_IE     <= CP0_IN[0];
        end
        if (CP0_CONTROL[8])
        begin

        end
        if (CP0_CONTROL[5])
        begin
            Cause_IP_1_0  <= CP0_IN[9 : 8];
        end
        if (CP0_CONTROL[7] & !Status_EXL)
        begin
            Cause_BD      <= CP0_CONTROL[6];
        end
        if (CP0_CONTROL[4])
        begin
            Cause_ExcCode <=    ( (Cause_IP_1_0 != 2'b00) & (Status_IE == 1'b1) & (Status_EXL == 1'b0)) ? 5'b00000 : 
                                ( CP0_CONTROL[3:1] == 3'b001) ? 5'b00100 :
                                ( CP0_CONTROL[3:1] == 3'b010) ? 5'b00101 :
                                ( CP0_CONTROL[3:1] == 3'b011) ? 5'b01000 :
                                ( CP0_CONTROL[3:1] == 3'b100) ? 5'b01001 :
                                ( CP0_CONTROL[3:1] == 3'b101) ? 5'b01010 :
                                ( CP0_CONTROL[3:1] == 3'b110) ? 5'b01100 :
                                5'b0;
        end
        if(CP0_CONTROL[14])
        begin
            Count          <= CP0_IN;  
        end
        if(!CP0_CONTROL[14] & tick)
        begin
            Count          <= Count + 1'b1;
        end
        if(CP0_CONTROL[15])
        begin
            Compare        <= CP0_IN; 
            Cause_TI       <= 1'b0;
        end
        if(!CP0_CONTROL[15] & Count == Compare)
        begin
            Cause_TI       <= 1'b1;
        end
    end
    always @(posedge clk) begin
        if(rst)
            Status_EXL     <= 1'b0;
        else if(CP0_CONTROL[8])
            Status_EXL     <= CP0_CONTROL[9];
        else if(CP0_CONTROL[10])
            Status_EXL     <= CP0_IN[1];
    end
endmodule
module CP0(
    input clk,
    input rst,

    input [31:0] CP0_DATA_IN,
    input [31:0] CP0_PC_IN,
    input [15:0] CP0_CONTROL,
    output [31: 0] Status_OUT,          
    output [31: 0] Cause_OUT,
    output [31: 0] BadAddr_OUT,
    output [31: 0] EPC_OUT,
    output [31: 0] Count_OUT,
    output [31: 0] Compare_OUT,
    output INT
);


    reg [31: 0] EPC;

    reg [31: 0] BadVAddr;

    reg         Cause_BD;
    reg         Cause_TI;
    reg [5 : 0] Cause_IP_7_2;
    reg [1 : 0] Cause_IP_1_0;
    reg [4 : 0] Cause_ExcCode;

    reg [7 : 0] Status_IM_7_0;
    reg         Status_EXL;
    reg         Status_IE;

    reg [31: 0] Count;
    reg         tick;

    reg [31: 0] Compare; 


    assign Status_OUT  = { 9'b0, 1'b1,6'b0,Status_IM_7_0, 6'b0, Status_EXL, Status_IE };
    assign Cause_OUT   = { Cause_BD,15'b0, Cause_IP_7_2, Cause_IP_1_0, 1'b0, Cause_ExcCode, 2'b0 };
    assign BadAddr_OUT =   BadVAddr;
    assign EPC_OUT     =   EPC;
    assign Count_OUT   =   Count;
    assign Compare_OUT =   Compare;
    assign INT         =   ((Cause_IP_1_0 & Status_IM_7_0[1:0]) != 2'b00) & (Status_IE == 1'b1) & (Status_EXL == 1'b0);


    wire [31: 0] CP0_IN;
    wire [31: 0] BadAddr_IN;
    wire [31: 0] BDPC;
    
    mux2 MBDPC (
        .In0        ( CP0_PC_IN          ),
        .In1        ( CP0_PC_IN - 32'd4  ),
        .Op         ( CP0_CONTROL[6]     ),
        .Out        ( BDPC               )
    );
    
    mux2 MEPCIN (
        .In0        ( CP0_DATA_IN     ),
        .In1        ( BDPC            ),
        .Op         ( CP0_CONTROL[13] ),
        .Out        ( CP0_IN          )
    );
    
    mux2 MBADADDR (
        .In0    ( CP0_IN          ),
        .In1    ( CP0_DATA_IN     ),
        .Op     ( CP0_CONTROL[11] ),
        .Out    ( BadAddr_IN      )
    );
    
    
    always @(posedge clk)
    begin
        if(rst)
        begin
            EPC           <= 32'b0;
            BadVAddr      <= 32'b0;
            Cause_BD      <= 1'b0;
            Cause_TI      <= 1'b0;
            Cause_IP_7_2  <= 6'b0;
            Cause_IP_1_0  <= 2'b0;
            Cause_ExcCode <= 5'b0;
            Status_IM_7_0 <= 8'b0;

            Status_IE     <= 1'b0;
            Count         <= 32'b0;
            tick          <= 1'b0;
        end
        if(!rst)
            tick          <= ~tick;
        if (CP0_CONTROL[0])
        begin
            if(CP0_CONTROL[13] & Status_EXL)
                EPC <= EPC;
            else
                EPC <= CP0_IN;
        end
        if (CP0_CONTROL[12])
        begin
            BadVAddr <= BadAddr_IN;
        end
        if (CP0_CONTROL[10])
        begin
            Status_IM_7_0 <= CP0_IN[15: 8];

            Status_IE     <= CP0_IN[0];
        end
        if (CP0_CONTROL[8])
        begin

        end
        if (CP0_CONTROL[5])
        begin
            Cause_IP_1_0  <= CP0_IN[9 : 8];
        end
        if (CP0_CONTROL[7] & !Status_EXL)
        begin
            Cause_BD      <= CP0_CONTROL[6];
        end
        if (CP0_CONTROL[4])
        begin
            Cause_ExcCode <=    ( (Cause_IP_1_0 != 2'b00) & (Status_IE == 1'b1) & (Status_EXL == 1'b0)) ? 5'b00000 : 
                                ( CP0_CONTROL[3:1] == 3'b001) ? 5'b00100 :
                                ( CP0_CONTROL[3:1] == 3'b010) ? 5'b00101 :
                                ( CP0_CONTROL[3:1] == 3'b011) ? 5'b01000 :
                                ( CP0_CONTROL[3:1] == 3'b100) ? 5'b01001 :
                                ( CP0_CONTROL[3:1] == 3'b101) ? 5'b01010 :
                                ( CP0_CONTROL[3:1] == 3'b110) ? 5'b01100 :
                                5'b0;
        end
        if(CP0_CONTROL[14])
        begin
            Count          <= CP0_IN;  
        end
        if(!CP0_CONTROL[14] & tick)
        begin
            Count          <= Count + 1'b1;
        end
        if(CP0_CONTROL[15])
        begin
            Compare        <= CP0_IN; 
            Cause_TI       <= 1'b0;
        end
        if(!CP0_CONTROL[15] & Count == Compare)
        begin
            Cause_TI       <= 1'b1;
        end
    end
    always @(posedge clk) begin
        if(rst)
            Status_EXL     <= 1'b0;
        else if(CP0_CONTROL[8])
            Status_EXL     <= CP0_CONTROL[9];
        else if(CP0_CONTROL[10])
            Status_EXL     <= CP0_IN[1];
    end
endmodule