data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv:6: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv:14: syntax error, unexpected \'@\', expecting \';\'\ndefault clocking cb @(posedge clk);\n                    ^\n%Error: data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv:17: syntax error, unexpected endclocking\nendclocking\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv:24: syntax error, unexpected int, expecting IDENTIFIER or genvar\n    for (int i = 1; i < 32; i++) begin\n         ^~~\n%Error: data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv:30: syntax error, unexpected <=, expecting IDENTIFIER\n    cb.rst <= 1\'b1;\n           ^~\n%Error: data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv:31: syntax error, unexpected <=, expecting IDENTIFIER\n    cb.load <= 1\'b0;\n            ^~\n%Error: data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv:32: syntax error, unexpected <=, expecting IDENTIFIER\n    cb.in <= 32\'b0;\n          ^~\n%Error: data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv:33: syntax error, unexpected <=, expecting IDENTIFIER\n    cb.src_a <= 5\'b0;\n             ^~\n%Error: data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv:34: syntax error, unexpected <=, expecting IDENTIFIER\n    cb.src_b <= 5\'b0;\n             ^~\n%Error: data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv:35: syntax error, unexpected <=, expecting IDENTIFIER\n    cb.dest <= 5\'b0;\n            ^~\n%Error: data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv:37: syntax error, unexpected <=, expecting IDENTIFIER\n    cb.rst <= 1\'b0;\n           ^~\n%Error: data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv:42: syntax error, unexpected <=, expecting IDENTIFIER\n    cb.load <= 1\'b1;\n            ^~\n%Error: data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv:43: syntax error, unexpected <=, expecting IDENTIFIER\n    cb.in <= data;\n          ^~\n%Error: data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv:44: syntax error, unexpected <=, expecting IDENTIFIER\n    cb.dest <= dest;\n            ^~\n%Error: data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv:46: syntax error, unexpected <=, expecting IDENTIFIER\n    cb.load <= 1\'b0;\n            ^~\n%Error: data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv:50: syntax error, unexpected int, expecting IDENTIFIER or genvar\n    for (int i = 1; i < 32; i++) begin\n         ^~~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module mp1_tb;

bit clk = 1'b0;
always #5 clk = ~clk;

bit rst, load;
bit [31:0] in, reg_a, reg_b;
bit [4:0] src_a, src_b, dest;

mp1 mp1(.*);

default clocking cb @(posedge clk);
    input reg_a, reg_b;
    output rst, load, in, src_a, src_b, dest;
endclocking

function void print_reg(int i);
    $display("reg %2x: %x", i, mp1.rf.data[i]);
endfunction

function void print_regfile();
    for (int i = 1; i < 32; i++) begin
        print_reg(i);
    end
endfunction

task reset();
    cb.rst <= 1'b1;
    cb.load <= 1'b0;
    cb.in <= 32'b0;
    cb.src_a <= 5'b0;
    cb.src_b <= 5'b0;
    cb.dest <= 5'b0;
    #10;
    cb.rst <= 1'b0;
    #10;
endtask

task regfile_write(bit [4:0] dest, bit [31:0] data);
    cb.load <= 1'b1;
    cb.in <= data;
    cb.dest <= dest;
    #10;
    cb.load <= 1'b0;
endtask

task sequential_write();
    for (int i = 1; i < 32; i++) begin
        regfile_write(i, i);
    end
endtask

initial begin
    $display("Starting simulation.");
    reset();
    print_regfile();
    $display("Writing to regfile...");
    sequential_write();
    #10;
    $display("Wrote to regfile.");
    print_regfile();
    $finish;
end

final begin
    $display("Ending simulation.");
end

endmodule
module mp1_tb;


bit clk = 1'b0;
always #5 clk = ~clk;

bit rst, load;
bit [31:0] in, reg_a, reg_b;
bit [4:0] src_a, src_b, dest;

mp1 mp1(.*);

default clocking cb @(posedge clk);
    input reg_a, reg_b;
    output rst, load, in, src_a, src_b, dest;
endclocking

function void print_reg(int i);
    $display("reg %2x: %x", i, mp1.rf.data[i]);
endfunction

function void print_regfile();
    for (int i = 1; i < 32; i++) begin
        print_reg(i);
    end
endfunction

task reset();
    cb.rst <= 1'b1;
    cb.load <= 1'b0;
    cb.in <= 32'b0;
    cb.src_a <= 5'b0;
    cb.src_b <= 5'b0;
    cb.dest <= 5'b0;
    #10;
    cb.rst <= 1'b0;
    #10;
endtask

task regfile_write(bit [4:0] dest, bit [31:0] data);
    cb.load <= 1'b1;
    cb.in <= data;
    cb.dest <= dest;
    #10;
    cb.load <= 1'b0;
endtask

task sequential_write();
    for (int i = 1; i < 32; i++) begin
        regfile_write(i, i);
    end
endtask

initial begin
    $display("Starting simulation.");
    reset();
    print_regfile();
    $display("Writing to regfile...");
    sequential_write();
    #10;
    $display("Wrote to regfile.");
    print_regfile();
    $finish;
end

final begin
    $display("Ending simulation.");
end

endmodule