data/full_repos/permissive/492007370/Code/project_1/project_1.srcs/sources_1/imports/new/testBench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/492007370/Code/project_1/project_1.srcs/sources_1/imports/new/testBench.v:30: Unsupported: Ignoring delay on this delayed statement.\n    always #clockRate clk = ~clk;  \n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/492007370/Code/project_1/project_1.srcs/sources_1/imports/new/testBench.v:13: Cannot find file containing module: \'sine_gen\'\n    sine_gen baseSineGen(.clk (clk), .sineOutput (sine));\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/492007370/Code/project_1/project_1.srcs/sources_1/imports/new,data/full_repos/permissive/492007370/sine_gen\n             data/full_repos/permissive/492007370/Code/project_1/project_1.srcs/sources_1/imports/new,data/full_repos/permissive/492007370/sine_gen.v\n             data/full_repos/permissive/492007370/Code/project_1/project_1.srcs/sources_1/imports/new,data/full_repos/permissive/492007370/sine_gen.sv\n             sine_gen\n             sine_gen.v\n             sine_gen.sv\n             obj_dir/sine_gen\n             obj_dir/sine_gen.v\n             obj_dir/sine_gen.sv\n%Error: data/full_repos/permissive/492007370/Code/project_1/project_1.srcs/sources_1/imports/new/testBench.v:14: Cannot find file containing module: \'min_max\'\n    min_max samp(.clk (clk),.samples (Input_Data), .min (Min_Output), .max(Max_Output));\n    ^~~~~~~\n%Error: data/full_repos/permissive/492007370/Code/project_1/project_1.srcs/sources_1/imports/new/testBench.v:15: Cannot find file containing module: \'mean\'\n    mean mean1(.clk (clk),.mean(Mean_Output));\n    ^~~~\n%Error: data/full_repos/permissive/492007370/Code/project_1/project_1.srcs/sources_1/imports/new/testBench.v:16: Cannot find file containing module: \'std\'\n    std std1(.clk (clk),.mean(Mean_Output), .std(Std_Output));\n    ^~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testBench;
    reg clk;
    wire [15:0] sine;
    wire [15:0] Input_Data;
    wire [15:0] Min_Output;
    wire [15:0] Max_Output;
    wire [15:0] Mean_Output;
    wire [15:0] Std_Output;
    

    sine_gen baseSineGen(.clk (clk), .sineOutput (sine));
    min_max samp(.clk (clk),.samples (Input_Data), .min (Min_Output), .max(Max_Output));
    mean mean1(.clk (clk),.mean(Mean_Output));
    std std1(.clk (clk),.mean(Mean_Output), .std(Std_Output));

    

    parameter freq = 100000000;
    parameter SIZE = 1024; 
    parameter clockRate = 0.2;
    

    initial
    begin 
    clk = 1'b0;
    end
    
    always #clockRate clk = ~clk;
    
endmodule
module testBench;

    reg clk;
    wire [15:0] sine;
    wire [15:0] Input_Data;
    wire [15:0] Min_Output;
    wire [15:0] Max_Output;
    wire [15:0] Mean_Output;
    wire [15:0] Std_Output;
    

    sine_gen baseSineGen(.clk (clk), .sineOutput (sine));
    min_max samp(.clk (clk),.samples (Input_Data), .min (Min_Output), .max(Max_Output));
    mean mean1(.clk (clk),.mean(Mean_Output));
    std std1(.clk (clk),.mean(Mean_Output), .std(Std_Output));

    

    parameter freq = 100000000;
    parameter SIZE = 1024; 
    parameter clockRate = 0.2;
    

    initial
    begin 
    clk = 1'b0;
    end
    
    always #clockRate clk = ~clk;
    
endmodule