data/full_repos/permissive/493019833/test/testcase/firrtl/ReadwriterTester1/reference/ReadwriterTester1.v
data/verilator_xmls/3c94b868-81da-44b2-a2c5-c1d87bbc25fb.xml
module BITWISENOT(y, in);
    parameter width = 4;
    output [width-1:0] y;
    input [width-1:0] in;
    assign y = ~in;
endmodule
module BITWISENOT(y, in);

    parameter width = 4;
    output [width-1:0] y;
    input [width-1:0] in;
    assign y = ~in;
endmodule