data/full_repos/permissive/524208019/counter/counter.v
data/verilator_xmls/0d1b94a0-f25e-477b-92bd-0bce958230f4.xml
module counter(
  input clk,
  input reset,
  input enable,
  output [7:0] out
);

  (* keep *) reg [7:0] tmp;
  always @(*) begin
    tmp  = counter_reg + 1;
  end

  reg [7:0] counter_reg;
  always @(posedge clk) begin
    if (reset) begin
      counter_reg <= 0;
    end else if (enable) begin
      counter_reg <= tmp;
    end
  end

  assign out = counter_reg;

endmodule
module counter(
  input clk,
  input reset,
  input enable,
  output [7:0] out
);


  (* keep *) reg [7:0] tmp;
  always @(*) begin
    tmp  = counter_reg + 1;
  end

  reg [7:0] counter_reg;
  always @(posedge clk) begin
    if (reset) begin
      counter_reg <= 0;
    end else if (enable) begin
      counter_reg <= tmp;
    end
  end

  assign out = counter_reg;

endmodule