data/full_repos/permissive/499137621/CheckPoint2_32bit_ALU_project-main/bit_or_EN.v
data/verilator_xmls/c5d9a605-fce4-4f4e-b12a-900a0eb53391.xml
module bit_or_EN (EN,ctrl_ALUopcode);
	input [4:0] ctrl_ALUopcode;
	output EN;


	wire  op0, op1, op2, op3, op4;
	

	assign op0 =  ctrl_ALUopcode[0];
	assign op1 =  ctrl_ALUopcode[1];
	not not2(op2, ctrl_ALUopcode[2]);
	not not3(op3, ctrl_ALUopcode[3]);
	not not4(op4, ctrl_ALUopcode[4]);	
	

	

	and and_5(EN, op0, op1, op2, op3, op4);
	
endmodule
module bit_or_EN (EN,ctrl_ALUopcode);

	input [4:0] ctrl_ALUopcode;
	output EN;


	wire  op0, op1, op2, op3, op4;
	

	assign op0 =  ctrl_ALUopcode[0];
	assign op1 =  ctrl_ALUopcode[1];
	not not2(op2, ctrl_ALUopcode[2]);
	not not3(op3, ctrl_ALUopcode[3]);
	not not4(op4, ctrl_ALUopcode[4]);	
	

	

	and and_5(EN, op0, op1, op2, op3, op4);
	
endmodule