data/full_repos/permissive/520487363/EX2 - FPGA Realization of Radix-4 Multiplier/Verilog/DFlipFlop.v
1: b'%Error: Invalid Option: -\n'
module DFlipFlop (
    input ld, clk, rst,
    input ldData,
    output reg out
);
    always @(posedge clk or posedge rst) begin
        if (rst) out <= 1'b0;
        else if (ld) out <= ldData;
    end
endmodule
module DFlipFlop (
    input ld, clk, rst,
    input ldData,
    output reg out
);

    always @(posedge clk or posedge rst) begin
        if (rst) out <= 1'b0;
        else if (ld) out <= ldData;
    end
endmodule