data/full_repos/permissive/432564927/Lab1 (Verilog)/Lab1_Unal (Verilog)/Unal_Lab1.srcs/sources_1/new/lab1.v
1: b'%Error: Cannot find file containing module: (Verilog)/Lab1_Unal\n        ... Looked in:\n             data/full_repos/permissive/432564927/Lab1/(Verilog)/Lab1_Unal\n             data/full_repos/permissive/432564927/Lab1/(Verilog)/Lab1_Unal.v\n             data/full_repos/permissive/432564927/Lab1/(Verilog)/Lab1_Unal.sv\n             (Verilog)/Lab1_Unal\n             (Verilog)/Lab1_Unal.v\n             (Verilog)/Lab1_Unal.sv\n             obj_dir/(Verilog)/Lab1_Unal\n             obj_dir/(Verilog)/Lab1_Unal.v\n             obj_dir/(Verilog)/Lab1_Unal.sv\n%Error: Cannot find file containing module: (Verilog)/Unal_Lab1.srcs/sources_1/new,data/full_repos/permissive/432564927\n%Error: Cannot find file containing module: data/full_repos/permissive/432564927/Lab1\n%Error: Cannot find file containing module: (Verilog)/Unal_Lab1.srcs/sources_1/new/lab1.v\n%Error: Exiting due to 4 error(s)\n'
module lab1(
    input u, 
    input [2:0] currentState, 
    input clrn,
    output reg [6:0] led,
    output reg [2:0] nextState
    );
    
    reg [2:0] S0 = 3'b000;
    reg [2:0] S1 = 3'b001;
    reg [2:0] S2 = 3'b010;
    reg [2:0] S3 = 3'b011;
    reg [2:0] S4 = 3'b100;
    reg [2:0] S5 = 3'b101;

    always @(*)
    begin
           case(currentState)
              S0: begin
                 if (u == 1)
                    nextState = S1;
                 else
                    nextState = S5;
              end
              S1: begin
                 if (u == 1)
                    nextState = S2;
                 else
                    nextState = S0;
              end
              S2: begin
                 if (u == 1)
                    nextState = S3;
                 else
                    nextState = S1;
              end
              S3: begin
                 if (u == 1)
                    nextState = S4;
                 else
                    nextState = S2;
              end
              S4: begin
                 if (u == 1)
                    nextState = S5;
                 else
                    nextState = S3;
              end
              S5: begin
                 if (u == 1)
                    nextState = S0;
                 else
                    nextState = S4;
              end
           endcase
     end  
     
    always @(*)
    begin
        case(currentState)
            S0: begin
                led <= 7'b1000000;
            end
            S1: begin
                led <= 7'b1111001;
            end
            S2: begin
                led <= 7'b0100100;
            end
            S3: begin
                led <= 7'b0110000;
            end
            S4: begin
                led <= 7'b0011001;
            end
            S5: begin
                led <= 7'b0010010;
            end
        endcase
    end
endmodule
module lab1(
    input u, 
    input [2:0] currentState, 
    input clrn,
    output reg [6:0] led,
    output reg [2:0] nextState
    );

    
    reg [2:0] S0 = 3'b000;
    reg [2:0] S1 = 3'b001;
    reg [2:0] S2 = 3'b010;
    reg [2:0] S3 = 3'b011;
    reg [2:0] S4 = 3'b100;
    reg [2:0] S5 = 3'b101;

    always @(*)
    begin
           case(currentState)
              S0: begin
                 if (u == 1)
                    nextState = S1;
                 else
                    nextState = S5;
              end
              S1: begin
                 if (u == 1)
                    nextState = S2;
                 else
                    nextState = S0;
              end
              S2: begin
                 if (u == 1)
                    nextState = S3;
                 else
                    nextState = S1;
              end
              S3: begin
                 if (u == 1)
                    nextState = S4;
                 else
                    nextState = S2;
              end
              S4: begin
                 if (u == 1)
                    nextState = S5;
                 else
                    nextState = S3;
              end
              S5: begin
                 if (u == 1)
                    nextState = S0;
                 else
                    nextState = S4;
              end
           endcase
     end  
     
    always @(*)
    begin
        case(currentState)
            S0: begin
                led <= 7'b1000000;
            end
            S1: begin
                led <= 7'b1111001;
            end
            S2: begin
                led <= 7'b0100100;
            end
            S3: begin
                led <= 7'b0110000;
            end
            S4: begin
                led <= 7'b0011001;
            end
            S5: begin
                led <= 7'b0010010;
            end
        endcase
    end
endmodule