data/full_repos/permissive/515133384/Verilog Code for Design part.v
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/515133384/Verilog\n        ... Looked in:\n             data/full_repos/permissive/515133384,data/full_repos/permissive/515133384/data/full_repos/permissive/515133384/Verilog\n             data/full_repos/permissive/515133384,data/full_repos/permissive/515133384/data/full_repos/permissive/515133384/Verilog.v\n             data/full_repos/permissive/515133384,data/full_repos/permissive/515133384/data/full_repos/permissive/515133384/Verilog.sv\n             data/full_repos/permissive/515133384/Verilog\n             data/full_repos/permissive/515133384/Verilog.v\n             data/full_repos/permissive/515133384/Verilog.sv\n             obj_dir/data/full_repos/permissive/515133384/Verilog\n             obj_dir/data/full_repos/permissive/515133384/Verilog.v\n             obj_dir/data/full_repos/permissive/515133384/Verilog.sv\n%Error: Cannot find file containing module: Code\n%Error: Cannot find file containing module: for\n%Error: Cannot find file containing module: Design\n%Error: Cannot find file containing module: part.v\n%Error: Exiting due to 5 error(s)\n'
module boolean(Y0,Y1,Y2,P,Q,R,S);
  input Y0,Y1,Y2;
  output reg[8:0]P,Q,R,S;
  always@(Y0 or Y1 or Y2)
    begin
      P={9{~((Y0~^Y1)|Y2)}};
      Q={9{~((Y0~&Y1)|Y2)}};
      R={9{((Y0~|Y1)&Y2)}};
      S={9{((Y0^Y1)&Y2)}};
      
    end
endmodule
module boolean(Y0,Y1,Y2,P,Q,R,S);

  input Y0,Y1,Y2;
  output reg[8:0]P,Q,R,S;
  always@(Y0 or Y1 or Y2)
    begin
      P={9{~((Y0~^Y1)|Y2)}};
      Q={9{~((Y0~&Y1)|Y2)}};
      R={9{((Y0~|Y1)&Y2)}};
      S={9{((Y0^Y1)&Y2)}};
      
    end
endmodule