data/full_repos/permissive/492213907/codes/Led7_Decoder.v
data/verilator_xmls/5f10a9f7-3c27-4916-80ed-b555109e20d8.xml
module Led7_Decoder(clk, clk_sw_1, clk_sw_2, mode, hex0, hex1);

	output [6:0] hex0;
	output [6:0] hex1;
	input [1:0] mode;
	input clk, clk_sw_1, clk_sw_2;
	
	reg [6:0] hex0_reg;
	reg [6:0] hex1_reg;

	always @ (posedge clk) begin
	
		if (mode == 2'b01)
			hex0_reg <= 7'b0110000;
	
		if (mode == 2'b10)
			hex0_reg <= 7'b1101101;
	
		if (mode == 2'b11)
			hex0_reg <= 7'b1111001;
	
		if (mode == 2'b00)
			hex0_reg <= 7'b1111110;
	
		if (clk_sw_1 == 0 && clk_sw_2 == 1)
			hex1_reg <= 7'b0110000;

		if (clk_sw_1 == 1 && clk_sw_2 == 0)
			hex1_reg <= 7'b1101101;
	
		if (clk_sw_1 == 1 && clk_sw_2 == 1)
			hex1_reg <= 7'b0110011;
	
		if (clk_sw_1 == 0 && clk_sw_2 == 0)
			hex1_reg <= 7'b1111110;
	
	end
	
	assign hex0 = hex0_reg;
	assign hex1 = hex1_reg;
	
endmodule
module Led7_Decoder(clk, clk_sw_1, clk_sw_2, mode, hex0, hex1);


	output [6:0] hex0;
	output [6:0] hex1;
	input [1:0] mode;
	input clk, clk_sw_1, clk_sw_2;
	
	reg [6:0] hex0_reg;
	reg [6:0] hex1_reg;

	always @ (posedge clk) begin
	
		if (mode == 2'b01)
			hex0_reg <= 7'b0110000;
	
		if (mode == 2'b10)
			hex0_reg <= 7'b1101101;
	
		if (mode == 2'b11)
			hex0_reg <= 7'b1111001;
	
		if (mode == 2'b00)
			hex0_reg <= 7'b1111110;
	
		if (clk_sw_1 == 0 && clk_sw_2 == 1)
			hex1_reg <= 7'b0110000;

		if (clk_sw_1 == 1 && clk_sw_2 == 0)
			hex1_reg <= 7'b1101101;
	
		if (clk_sw_1 == 1 && clk_sw_2 == 1)
			hex1_reg <= 7'b0110011;
	
		if (clk_sw_1 == 0 && clk_sw_2 == 0)
			hex1_reg <= 7'b1111110;
	
	end
	
	assign hex0 = hex0_reg;
	assign hex1 = hex1_reg;
	
endmodule