data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_ifddioin.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_ifddioin.v:80: Cannot find file containing module: 'fflopx'\nfflopx #(DW) ffdat_l (rxclk, rxrst_, edat_l, odat_l);\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core,data/full_repos/permissive/530013823/fflopx\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core,data/full_repos/permissive/530013823/fflopx.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core,data/full_repos/permissive/530013823/fflopx.sv\n             fflopx\n             fflopx.v\n             fflopx.sv\n             obj_dir/fflopx\n             obj_dir/fflopx.v\n             obj_dir/fflopx.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_ifddioin.v:81: Cannot find file containing module: 'fflopx'\nfflopx #(DW) ffdat_h (rxclk, rxrst_, edat_h, odat_h);\n^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module ipsmacge_ifddioin
    (
     rxclk,
     rxrst_,
     idat_h,
     idat_l,
     odat_h, 
     odat_l
     );



parameter DW = 10;



input             rxrst_;

input             rxclk;

input [DW-1: 0]   idat_h;
input [DW-1: 0]   idat_l;

output [DW-1: 0]  odat_h;
output [DW-1: 0]  odat_l;



reg  [DW-1:0]     idat_h1;
wire [DW-1:0]     edat_l;
wire [DW-1:0]     edat_h;

























assign edat_h = idat_h1;
assign edat_l = idat_l;


always @(posedge rxclk or negedge rxrst_)
    begin
    if (!rxrst_)idat_h1 <= {DW{1'b0}};
    else        idat_h1 <= idat_h;
    end

fflopx #(DW) ffdat_l (rxclk, rxrst_, edat_l, odat_l);
fflopx #(DW) ffdat_h (rxclk, rxrst_, edat_h, odat_h);

endmodule
module ipsmacge_ifddioin
    (
     rxclk,
     rxrst_,
     idat_h,
     idat_l,
     odat_h, 
     odat_l
     );




parameter DW = 10;



input             rxrst_;

input             rxclk;

input [DW-1: 0]   idat_h;
input [DW-1: 0]   idat_l;

output [DW-1: 0]  odat_h;
output [DW-1: 0]  odat_l;



reg  [DW-1:0]     idat_h1;
wire [DW-1:0]     edat_l;
wire [DW-1:0]     edat_h;

























assign edat_h = idat_h1;
assign edat_l = idat_l;


always @(posedge rxclk or negedge rxrst_)
    begin
    if (!rxrst_)idat_h1 <= {DW{1'b0}};
    else        idat_h1 <= idat_h;
    end

fflopx #(DW) ffdat_l (rxclk, rxrst_, edat_l, odat_l);
fflopx #(DW) ffdat_h (rxclk, rxrst_, edat_h, odat_h);

endmodule