data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_hz.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_hz.v:31: Cannot find file containing module: 'bw_clk_gclk_inv_224x'\nbw_clk_gclk_inv_224x x2 (\n^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_clk_gclk_inv_224x\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_clk_gclk_inv_224x.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_clk_gclk_inv_224x.sv\n             bw_clk_gclk_inv_224x\n             bw_clk_gclk_inv_224x.v\n             bw_clk_gclk_inv_224x.sv\n             obj_dir/bw_clk_gclk_inv_224x\n             obj_dir/bw_clk_gclk_inv_224x.v\n             obj_dir/bw_clk_gclk_inv_224x.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_hz.v:34: Cannot find file containing module: 'bw_clk_gclk_inv_224x'\nbw_clk_gclk_inv_224x x3 (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_hz.v:37: Cannot find file containing module: 'bw_clk_gclk_inv_192x'\nbw_clk_gclk_inv_192x x4 (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_hz.v:40: Cannot find file containing module: 'bw_clk_gclk_inv_224x'\nbw_clk_gclk_inv_224x x5 (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_hz.v:43: Cannot find file containing module: 'bw_clk_gclk_inv_288x'\nbw_clk_gclk_inv_288x x6 (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_hz.v:46: Cannot find file containing module: 'bw_clk_gclk_inv_224x'\nbw_clk_gclk_inv_224x x7 (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_hz.v:49: Cannot find file containing module: 'bw_clk_gclk_inv_288x'\nbw_clk_gclk_inv_288x x8 (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_hz.v:52: Cannot find file containing module: 'bw_clk_gclk_inv_224x'\nbw_clk_gclk_inv_224x x0 (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_hz.v:55: Cannot find file containing module: 'bw_clk_gclk_inv_192x'\nbw_clk_gclk_inv_192x x1 (\n^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n"
module bw_clk_gl_hz1(col_clk ,center_clk );
output [3:0]	col_clk ;
input		center_clk ;
 
wire [1:0]	c13 ;
wire [1:0]	c14 ;
wire		c15 ;
 
 
bw_clk_gclk_inv_224x x2 (
     .clkout          (c15 ),
     .clkin           (center_clk ) );
bw_clk_gclk_inv_224x x3 (
     .clkout          (col_clk[2] ),
     .clkin           (c13[1] ) );
bw_clk_gclk_inv_192x x4 (
     .clkout          (c13[1] ),
     .clkin           (c14[1] ) );
bw_clk_gclk_inv_224x x5 (
     .clkout          (col_clk[1] ),
     .clkin           (c13[0] ) );
bw_clk_gclk_inv_288x x6 (
     .clkout          (c14[0] ),
     .clkin           (c15 ) );
bw_clk_gclk_inv_224x x7 (
     .clkout          (col_clk[0] ),
     .clkin           (c13[0] ) );
bw_clk_gclk_inv_288x x8 (
     .clkout          (c14[1] ),
     .clkin           (c15 ) );
bw_clk_gclk_inv_224x x0 (
     .clkout          (col_clk[3] ),
     .clkin           (c13[1] ) );
bw_clk_gclk_inv_192x x1 (
     .clkout          (c13[0] ),
     .clkin           (c14[0] ) );
endmodule
module bw_clk_gl_hz1(col_clk ,center_clk );

output [3:0]	col_clk ;
input		center_clk ;
 
wire [1:0]	c13 ;
wire [1:0]	c14 ;
wire		c15 ;
 
 
bw_clk_gclk_inv_224x x2 (
     .clkout          (c15 ),
     .clkin           (center_clk ) );
bw_clk_gclk_inv_224x x3 (
     .clkout          (col_clk[2] ),
     .clkin           (c13[1] ) );
bw_clk_gclk_inv_192x x4 (
     .clkout          (c13[1] ),
     .clkin           (c14[1] ) );
bw_clk_gclk_inv_224x x5 (
     .clkout          (col_clk[1] ),
     .clkin           (c13[0] ) );
bw_clk_gclk_inv_288x x6 (
     .clkout          (c14[0] ),
     .clkin           (c15 ) );
bw_clk_gclk_inv_224x x7 (
     .clkout          (col_clk[0] ),
     .clkin           (c13[0] ) );
bw_clk_gclk_inv_288x x8 (
     .clkout          (c14[1] ),
     .clkin           (c15 ) );
bw_clk_gclk_inv_224x x0 (
     .clkout          (col_clk[3] ),
     .clkin           (c13[1] ) );
bw_clk_gclk_inv_192x x1 (
     .clkout          (c13[0] ),
     .clkin           (c14[0] ) );
endmodule