data/full_repos/permissive/494148647/src/peripherals/i2cm/i2cm_iom.v
1: b"%Error: data/full_repos/permissive/494148647/src/peripherals/i2cm/i2cm_iom.v:96: Cannot find file containing module: 'i2c_master_top'\n    i2c_master_top i2c_top (\n    ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/494148647/src/peripherals/i2cm,data/full_repos/permissive/494148647/i2c_master_top\n             data/full_repos/permissive/494148647/src/peripherals/i2cm,data/full_repos/permissive/494148647/i2c_master_top.v\n             data/full_repos/permissive/494148647/src/peripherals/i2cm,data/full_repos/permissive/494148647/i2c_master_top.sv\n             i2c_master_top\n             i2c_master_top.v\n             i2c_master_top.sv\n             obj_dir/i2c_master_top\n             obj_dir/i2c_master_top.v\n             obj_dir/i2c_master_top.sv\n%Error: Exiting due to 1 error(s)\n"
module i2cm_iom(


    input clk,
    input rst,
    input io_addr_strobe,
    input io_read_strobe,
    input io_write_strobe,
    input [11:0] io_address,
    input [3:0] io_byte_enable,
    input [31:0] io_write_data,
    output [31:0] io_read_data,
    output io_ready,


    output irq,


    inout scl,
    inout sda
    );


    reg [2:0] wb_adr;
    reg [7:0] wb_dat_i;
    reg  wb_we;
    reg  wb_cyc;
    wire wb_ack;


    wire scl_pad_i;
    wire scl_pad_o;
    wire scl_padoen;

    assign scl = (scl_padoen ? 1'bz : scl_pad_o);
    assign scl_pad_i = scl;


    wire sda_pad_i;
    wire sda_pad_o;
    wire sda_padoen;

    assign sda = (sda_padoen ? 1'bz : sda_pad_o);
    assign sda_pad_i = sda;


    reg io_ready_default;
    assign io_read_data[31:8] = 24'b0;
    assign io_ready = io_ready_default | wb_ack;


    always @(posedge clk) begin
        io_ready_default <= #1 1'b0;

        if (rst) begin
            wb_adr <= #1 3'b0;
            wb_dat_i <= #1 8'b0;
            wb_we <= #1 1'b0;
            wb_cyc <= #1 1'b0;
        end else begin
            wb_adr <= #1 wb_adr;
            wb_dat_i <= #1 wb_dat_i;
            wb_we <= #1 wb_we;
            wb_cyc <= #1 wb_cyc;


            if (io_addr_strobe) begin
                if (io_address[11:5] == 7'b0) begin
                    wb_adr <= #1 io_address[4:2];
                    wb_dat_i <= #1 io_write_data[7:0];
                    wb_we <= #1 io_write_strobe;
                    wb_cyc <= #1 1'b1;
                end else begin
                    io_ready_default <= #1 1'b1;
                end
            end


            if (wb_cyc & wb_ack) begin
                wb_adr <= #1 3'b0;
                wb_dat_i <= #1 8'b0;
                wb_we <= #1 1'b0;
                wb_cyc <= #1 1'b0;
            end
        end
    end


    i2c_master_top i2c_top (


        .wb_clk_i(clk),
        .wb_rst_i(1'b0),
        .arst_i(~rst),
        .wb_adr_i(wb_adr),
        .wb_dat_i(wb_dat_i),
        .wb_dat_o(io_read_data[7:0]),
        .wb_we_i(wb_we),
        .wb_stb_i(wb_cyc),
        .wb_cyc_i(wb_cyc),
        .wb_ack_o(wb_ack),
        .wb_inta_o(irq),


        .scl_pad_i(scl_pad_i),
        .scl_pad_o(scl_pad_o),
        .scl_padoen_o(scl_padoen),
        .sda_pad_i(sda_pad_i),
        .sda_pad_o(sda_pad_o),
        .sda_padoen_o(sda_padoen)
    );

endmodule
module i2cm_iom(


    input clk,
    input rst,
    input io_addr_strobe,
    input io_read_strobe,
    input io_write_strobe,
    input [11:0] io_address,
    input [3:0] io_byte_enable,
    input [31:0] io_write_data,
    output [31:0] io_read_data,
    output io_ready,


    output irq,


    inout scl,
    inout sda
    );



    reg [2:0] wb_adr;
    reg [7:0] wb_dat_i;
    reg  wb_we;
    reg  wb_cyc;
    wire wb_ack;


    wire scl_pad_i;
    wire scl_pad_o;
    wire scl_padoen;

    assign scl = (scl_padoen ? 1'bz : scl_pad_o);
    assign scl_pad_i = scl;


    wire sda_pad_i;
    wire sda_pad_o;
    wire sda_padoen;

    assign sda = (sda_padoen ? 1'bz : sda_pad_o);
    assign sda_pad_i = sda;


    reg io_ready_default;
    assign io_read_data[31:8] = 24'b0;
    assign io_ready = io_ready_default | wb_ack;


    always @(posedge clk) begin
        io_ready_default <= #1 1'b0;

        if (rst) begin
            wb_adr <= #1 3'b0;
            wb_dat_i <= #1 8'b0;
            wb_we <= #1 1'b0;
            wb_cyc <= #1 1'b0;
        end else begin
            wb_adr <= #1 wb_adr;
            wb_dat_i <= #1 wb_dat_i;
            wb_we <= #1 wb_we;
            wb_cyc <= #1 wb_cyc;


            if (io_addr_strobe) begin
                if (io_address[11:5] == 7'b0) begin
                    wb_adr <= #1 io_address[4:2];
                    wb_dat_i <= #1 io_write_data[7:0];
                    wb_we <= #1 io_write_strobe;
                    wb_cyc <= #1 1'b1;
                end else begin
                    io_ready_default <= #1 1'b1;
                end
            end


            if (wb_cyc & wb_ack) begin
                wb_adr <= #1 3'b0;
                wb_dat_i <= #1 8'b0;
                wb_we <= #1 1'b0;
                wb_cyc <= #1 1'b0;
            end
        end
    end


    i2c_master_top i2c_top (


        .wb_clk_i(clk),
        .wb_rst_i(1'b0),
        .arst_i(~rst),
        .wb_adr_i(wb_adr),
        .wb_dat_i(wb_dat_i),
        .wb_dat_o(io_read_data[7:0]),
        .wb_we_i(wb_we),
        .wb_stb_i(wb_cyc),
        .wb_cyc_i(wb_cyc),
        .wb_ack_o(wb_ack),
        .wb_inta_o(irq),


        .scl_pad_i(scl_pad_i),
        .scl_pad_o(scl_pad_o),
        .scl_padoen_o(scl_padoen),
        .sda_pad_i(sda_pad_i),
        .sda_pad_o(sda_pad_o),
        .sda_padoen_o(sda_padoen)
    );

endmodule