data/full_repos/permissive/515513819/neuron/neuron_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/515513819/neuron/neuron_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_in = 1; sign_in = 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/515513819/neuron/neuron_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #1  data_in = 0; sign_in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/neuron/neuron_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_in = 1; sign_in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/neuron/neuron_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #1  data_in = 0; sign_in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/neuron/neuron_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_in = 1; sign_in = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/neuron/neuron_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #1  data_in = 0; sign_in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/neuron/neuron_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_in = 1; sign_in = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/neuron/neuron_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #1  data_in = 0; sign_in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/neuron/neuron_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_in = 1; sign_in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/neuron/neuron_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #1 data_in = 0; sign_in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/neuron/neuron_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_in = 1; sign_in = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/neuron/neuron_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #1  data_in = 0; sign_in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/neuron/neuron_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_in = 1; sign_in = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/neuron/neuron_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n    #1  data_in = 0; sign_in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/neuron/neuron_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #5 clk = !clk;\n    ^\n%Error: data/full_repos/permissive/515513819/neuron/neuron_tb.v:8: Cannot find file containing module: \'neuron\'\n  neuron U0(\n  ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/515513819/neuron,data/full_repos/permissive/515513819/neuron\n             data/full_repos/permissive/515513819/neuron,data/full_repos/permissive/515513819/neuron.v\n             data/full_repos/permissive/515513819/neuron,data/full_repos/permissive/515513819/neuron.sv\n             neuron\n             neuron.v\n             neuron.sv\n             obj_dir/neuron\n             obj_dir/neuron.v\n             obj_dir/neuron.sv\n%Error: Exiting due to 1 error(s), 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module neuron_tb ;
  reg clk, weight;
  reg data_in, sign_in;
  wire data_out, sign_out;

  neuron U0(
    .clk      (clk),
    .weight   (weight),
    .data_in  (data_in),
    .sign_in  (sign_in),
    .data_out (data_out),
    .sign_out (sign_out)
    );


  initial begin
    clk = 0;
    weight = 1;

    data_in = 0; sign_in = 0;

    #10 data_in = 1; sign_in = 1;
    #1  data_in = 0; sign_in = 0;

    #10 data_in = 1; sign_in = 0;
    #1  data_in = 0; sign_in = 0;

    #10 data_in = 1; sign_in = 1;
    #1  data_in = 0; sign_in = 0;

    #10 data_in = 1; sign_in = 1;
    #1  data_in = 0; sign_in = 0;

    #10 data_in = 1; sign_in = 0;
    #1 data_in = 0; sign_in = 0;

    #10 data_in = 1; sign_in = 1;
    #1  data_in = 0; sign_in = 0;

    #10 data_in = 1; sign_in = 1;
    #1  data_in = 0; sign_in = 0;

  end

  always
    #5 clk = !clk;

endmodule
module neuron_tb ;

  reg clk, weight;
  reg data_in, sign_in;
  wire data_out, sign_out;

  neuron U0(
    .clk      (clk),
    .weight   (weight),
    .data_in  (data_in),
    .sign_in  (sign_in),
    .data_out (data_out),
    .sign_out (sign_out)
    );


  initial begin
    clk = 0;
    weight = 1;

    data_in = 0; sign_in = 0;

    #10 data_in = 1; sign_in = 1;
    #1  data_in = 0; sign_in = 0;

    #10 data_in = 1; sign_in = 0;
    #1  data_in = 0; sign_in = 0;

    #10 data_in = 1; sign_in = 1;
    #1  data_in = 0; sign_in = 0;

    #10 data_in = 1; sign_in = 1;
    #1  data_in = 0; sign_in = 0;

    #10 data_in = 1; sign_in = 0;
    #1 data_in = 0; sign_in = 0;

    #10 data_in = 1; sign_in = 1;
    #1  data_in = 0; sign_in = 0;

    #10 data_in = 1; sign_in = 1;
    #1  data_in = 0; sign_in = 0;

  end

  always
    #5 clk = !clk;

endmodule