data/full_repos/permissive/527176783/Pipeline/BranchPredict.v
1: b'%Error: data/full_repos/permissive/527176783/Pipeline/BranchPredict.v:3: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/527176783/Pipeline,data/full_repos/permissive/527176783/define.v\n             data/full_repos/permissive/527176783/Pipeline,data/full_repos/permissive/527176783/define.v.v\n             data/full_repos/permissive/527176783/Pipeline,data/full_repos/permissive/527176783/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/527176783/Pipeline/BranchPredict.v:15: Define or directive not defined: \'`ALUSub\'\n            `ALUSub: out = in_a - in_b;\n            ^~~~~~~\n%Error: data/full_repos/permissive/527176783/Pipeline/BranchPredict.v:15: syntax error, unexpected \':\', expecting endcase\n            `ALUSub: out = in_a - in_b;\n                   ^\n%Error: data/full_repos/permissive/527176783/Pipeline/BranchPredict.v:16: Define or directive not defined: \'`ALUSubZero\'\n            `ALUSubZero: out = in_a - 32\'d0;\n            ^~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module BranchPredict(
    input  [3:0]  Aluc,
    input  [31:0] in_a,
    input  [31:0] in_b,
    output reg Zero,
    output reg Sign
);
    reg [31:0] out;

    always @(*) begin
        case (Aluc)
            `ALUSub: out = in_a - in_b;
            `ALUSubZero: out = in_a - 32'd0;
            default: out = 1'b1;
        endcase

        if (out == 0) Zero = 1;
        else Zero = 0;
        
        Sign = out[31];
    end

endmodule
module BranchPredict(
    input  [3:0]  Aluc,
    input  [31:0] in_a,
    input  [31:0] in_b,
    output reg Zero,
    output reg Sign
);

    reg [31:0] out;

    always @(*) begin
        case (Aluc)
            `ALUSub: out = in_a - in_b;
            `ALUSubZero: out = in_a - 32'd0;
            default: out = 1'b1;
        endcase

        if (out == 0) Zero = 1;
        else Zero = 0;
        
        Sign = out[31];
    end

endmodule