data/full_repos/permissive/519458744/BLI201V32I/rtl/bli201v32i_top.v
1: b"%Error: data/full_repos/permissive/519458744/BLI201V32I/rtl/bli201v32i_top.v:21: Cannot find file containing module: 'clk_wiz_0'\n  clk_wiz_0 u_clk_wiz_0 (\n  ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/519458744/BLI201V32I/rtl,data/full_repos/permissive/519458744/clk_wiz_0\n             data/full_repos/permissive/519458744/BLI201V32I/rtl,data/full_repos/permissive/519458744/clk_wiz_0.v\n             data/full_repos/permissive/519458744/BLI201V32I/rtl,data/full_repos/permissive/519458744/clk_wiz_0.sv\n             clk_wiz_0\n             clk_wiz_0.v\n             clk_wiz_0.sv\n             obj_dir/clk_wiz_0\n             obj_dir/clk_wiz_0.v\n             obj_dir/clk_wiz_0.sv\n%Error: data/full_repos/permissive/519458744/BLI201V32I/rtl/bli201v32i_top.v:41: Cannot find file containing module: 'core'\n  core u_core (\n  ^~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32I/rtl/bli201v32i_top.v:52: Cannot find file containing module: 'mmio'\n  mmio u_mmio (\n  ^~~~\n%Error: Exiting due to 3 error(s)\n"
module z1top #(
  parameter IMEM_HEX = "firmware.hex",
  parameter IMEM_BIN = ""
) (
  input         CLK100MHZ,
  input         ck_rst,
  
  input  [3:0]  sw,
  output [3:0]  led,
  input  [3:0]  btn
);

  wire clk;
  wire rst;
  
  assign rst = ck_rst;
  

  clk_wiz_0 u_clk_wiz_0 (

    .clk_out1(clk),

    .resetn(rst), 

    .clk_in1(CLK100MHZ)
  );

  wire [31:0] core2mmio_addr;
  wire [3:0]  core2mmio_wmask;
  wire [31:0] core2mmio_wdata;
  wire [31:0] mmio2core_rdata;
  





  
  core u_core (
    .clk(clk),
    .rst(rst),
    
    .core_o_mmio_addr(core2mmio_addr),
    .core_o_mmio_wmask(core2mmio_wmask),
    .core_o_mmio_wdata(core2mmio_wdata),
    .core_i_mmio_rdata(mmio2core_rdata)
  );

  
  mmio u_mmio (
    .clk(clk),
    .rst(rst),
    .mmio_i_addr(core2mmio_addr),
    .mmio_i_wmask(core2mmio_wmask),
    .mmio_i_wdata(core2mmio_wdata),
    .mmio_o_rdata(mmio2core_rdata),
    
    .mmio_o_gpio_led(led),
    .mmio_i_gpio_btn(btn),
    .mmio_i_gpio_sw(sw)
  );

endmodule
module z1top #(
  parameter IMEM_HEX = "firmware.hex",
  parameter IMEM_BIN = ""
) (
  input         CLK100MHZ,
  input         ck_rst,
  
  input  [3:0]  sw,
  output [3:0]  led,
  input  [3:0]  btn
);


  wire clk;
  wire rst;
  
  assign rst = ck_rst;
  

  clk_wiz_0 u_clk_wiz_0 (

    .clk_out1(clk),

    .resetn(rst), 

    .clk_in1(CLK100MHZ)
  );

  wire [31:0] core2mmio_addr;
  wire [3:0]  core2mmio_wmask;
  wire [31:0] core2mmio_wdata;
  wire [31:0] mmio2core_rdata;
  





  
  core u_core (
    .clk(clk),
    .rst(rst),
    
    .core_o_mmio_addr(core2mmio_addr),
    .core_o_mmio_wmask(core2mmio_wmask),
    .core_o_mmio_wdata(core2mmio_wdata),
    .core_i_mmio_rdata(mmio2core_rdata)
  );

  
  mmio u_mmio (
    .clk(clk),
    .rst(rst),
    .mmio_i_addr(core2mmio_addr),
    .mmio_i_wmask(core2mmio_wmask),
    .mmio_i_wdata(core2mmio_wdata),
    .mmio_o_rdata(mmio2core_rdata),
    
    .mmio_o_gpio_led(led),
    .mmio_i_gpio_btn(btn),
    .mmio_i_gpio_sw(sw)
  );

endmodule