data/full_repos/permissive/492213907/codes/t_Combo_str.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/492213907/codes/t_Combo_str.v:9: Unsupported: Ignoring delay on this delayed statement.\n initial #timeout $finish;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/492213907/codes/t_Combo_str.v:13: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk_50 = ~clk_50;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/492213907/codes/t_Combo_str.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/492213907/codes/t_Combo_str.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/492213907/codes/t_Combo_str.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Error: data/full_repos/permissive/492213907/codes/t_Combo_str.v:11: Cannot find file containing module: \'Combo_str\'\n Combo_str C(clk_50, en, rst, sw_1, sw_2, sw_3, sw_4, led, hex0, hex1);\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/492213907/codes,data/full_repos/permissive/492213907/Combo_str\n             data/full_repos/permissive/492213907/codes,data/full_repos/permissive/492213907/Combo_str.v\n             data/full_repos/permissive/492213907/codes,data/full_repos/permissive/492213907/Combo_str.sv\n             Combo_str\n             Combo_str.v\n             Combo_str.sv\n             obj_dir/Combo_str\n             obj_dir/Combo_str.v\n             obj_dir/Combo_str.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module t_Combo_str();

	reg clk_50, en, rst, sw_1, sw_2, sw_3, sw_4;
	wire [26:0] led;
	wire [6:0] hex0;
	wire [6:0] hex1;
	parameter timeout = 800;
	
	initial #timeout $finish;
	
	Combo_str C(clk_50, en, rst, sw_1, sw_2, sw_3, sw_4, led, hex0, hex1);
	
	always #5 clk_50 = ~clk_50;

	initial begin
		clk_50 = 0;
		en = 0;
		rst = 0;
		sw_1 = 0;
		sw_2 = 0;
		sw_3 = 0;
		sw_4 = 1;
		
		#20
		rst = 1;
		
		#10
		rst = 0;
		
		#5
		en = 1;
		


	end

endmodule
module t_Combo_str();


	reg clk_50, en, rst, sw_1, sw_2, sw_3, sw_4;
	wire [26:0] led;
	wire [6:0] hex0;
	wire [6:0] hex1;
	parameter timeout = 800;
	
	initial #timeout $finish;
	
	Combo_str C(clk_50, en, rst, sw_1, sw_2, sw_3, sw_4, led, hex0, hex1);
	
	always #5 clk_50 = ~clk_50;

	initial begin
		clk_50 = 0;
		en = 0;
		rst = 0;
		sw_1 = 0;
		sw_2 = 0;
		sw_3 = 0;
		sw_4 = 1;
		
		#20
		rst = 1;
		
		#10
		rst = 0;
		
		#5
		en = 1;
		


	end

endmodule