data/full_repos/permissive/434840709/USTB_digital_logic_homework/task2/GPU.v
data/verilator_xmls/7580a205-be06-4c06-9946-2a531b2b78e5.xml
module GPU(
    input clk3hz,
    input rst,
    input [31:0] myID, 
    output [15:0] dataBus
);

    reg[31:0] msgArray;
    assign dataBus = msgArray[31:16];
    always @(posedge clk3hz) begin
        if (!rst) 
            msgArray <= myID;
        else begin
            msgArray[3:0]  <= msgArray[31:28];
            msgArray[31:4] <= msgArray[27:0];
        end
    end
    
endmodule
module GPU(
    input clk3hz,
    input rst,
    input [31:0] myID, 
    output [15:0] dataBus
);


    reg[31:0] msgArray;
    assign dataBus = msgArray[31:16];
    always @(posedge clk3hz) begin
        if (!rst) 
            msgArray <= myID;
        else begin
            msgArray[3:0]  <= msgArray[31:28];
            msgArray[31:4] <= msgArray[27:0];
        end
    end
    
endmodule