data/full_repos/permissive/514313792/prj_qsys/avalon_vip/vip/vip_sobel.v
1: b'%Error: data/full_repos/permissive/514313792/prj_qsys/avalon_vip/vip/vip_sobel.v:51: Cannot find file containing module: \'shift_register\'\n shift_register #(BITS, WIDTH, 2) line2buf(pclk, in_href, in_data, shiftout, {tap1x, tap0x});\n ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514313792/prj_qsys/avalon_vip/vip,data/full_repos/permissive/514313792/shift_register\n             data/full_repos/permissive/514313792/prj_qsys/avalon_vip/vip,data/full_repos/permissive/514313792/shift_register.v\n             data/full_repos/permissive/514313792/prj_qsys/avalon_vip/vip,data/full_repos/permissive/514313792/shift_register.sv\n             shift_register\n             shift_register.v\n             shift_register.sv\n             obj_dir/shift_register\n             obj_dir/shift_register.v\n             obj_dir/shift_register.sv\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_vip/vip/vip_sobel.v:96: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'p11\' generates 8 bits.\n                                                                                           : ... In instance vip_sobel\n   gx1 <= p11 + (p21 << 1) + p31;\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_vip/vip/vip_sobel.v:96: Operator SHIFTL expects 10 bits on the LHS, but LHS\'s VARREF \'p21\' generates 8 bits.\n                                                                                           : ... In instance vip_sobel\n   gx1 <= p11 + (p21 << 1) + p31;\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_vip/vip/vip_sobel.v:96: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'p31\' generates 8 bits.\n                                                                                           : ... In instance vip_sobel\n   gx1 <= p11 + (p21 << 1) + p31;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_vip/vip/vip_sobel.v:97: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'p13\' generates 8 bits.\n                                                                                           : ... In instance vip_sobel\n   gx3 <= p13 + (p23 << 1) + p33;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_vip/vip/vip_sobel.v:97: Operator SHIFTL expects 10 bits on the LHS, but LHS\'s VARREF \'p23\' generates 8 bits.\n                                                                                           : ... In instance vip_sobel\n   gx3 <= p13 + (p23 << 1) + p33;\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_vip/vip/vip_sobel.v:97: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'p33\' generates 8 bits.\n                                                                                           : ... In instance vip_sobel\n   gx3 <= p13 + (p23 << 1) + p33;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_vip/vip/vip_sobel.v:98: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'p11\' generates 8 bits.\n                                                                                           : ... In instance vip_sobel\n   gy1 <= p11 + (p12 << 1) + p13;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_vip/vip/vip_sobel.v:98: Operator SHIFTL expects 10 bits on the LHS, but LHS\'s VARREF \'p12\' generates 8 bits.\n                                                                                           : ... In instance vip_sobel\n   gy1 <= p11 + (p12 << 1) + p13;\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_vip/vip/vip_sobel.v:98: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'p13\' generates 8 bits.\n                                                                                           : ... In instance vip_sobel\n   gy1 <= p11 + (p12 << 1) + p13;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_vip/vip/vip_sobel.v:99: Operator ADD expects 10 bits on the LHS, but LHS\'s VARREF \'p31\' generates 8 bits.\n                                                                                           : ... In instance vip_sobel\n   gy3 <= p31 + (p32 << 1) + p33;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_vip/vip/vip_sobel.v:99: Operator SHIFTL expects 10 bits on the LHS, but LHS\'s VARREF \'p32\' generates 8 bits.\n                                                                                           : ... In instance vip_sobel\n   gy3 <= p31 + (p32 << 1) + p33;\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_vip/vip/vip_sobel.v:99: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'p33\' generates 8 bits.\n                                                                                           : ... In instance vip_sobel\n   gy3 <= p31 + (p32 << 1) + p33;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_vip/vip/vip_sobel.v:103: Operator GT expects 11 bits on the RHS, but RHS\'s REPLICATE generates 8 bits.\n                                                                                            : ... In instance vip_sobel\n   out <= g > {BITS{1\'b1}} ? {BITS{1\'b1}} : g[BITS-1:0];\n            ^\n%Error: Exiting due to 1 error(s), 13 warning(s)\n'
module vip_sobel
#(
	parameter BITS = 8,
	parameter WIDTH = 640,
	parameter HEIGHT = 480
)
(
	input pclk,
	input rst_n,

	input in_href,
	input in_vsync,
	input [BITS-1:0] in_data,

	output out_href,
	output out_vsync,
	output [BITS-1:0] out_data
);

	wire [BITS-1:0] shiftout;
	wire [BITS-1:0] tap1x, tap0x;
	shift_register #(BITS, WIDTH, 2) line2buf(pclk, in_href, in_data, shiftout, {tap1x, tap0x});
	
	reg [BITS-1:0] p11,p12,p13;
	reg [BITS-1:0] p21,p22,p23;
	reg [BITS-1:0] p31,p32,p33;
	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n) begin
			p13 <= 0;
			p23 <= 0;
			p33 <= 0;
			p12 <= 0;
			p22 <= 0;
			p32 <= 0;
			p11 <= 0;
			p21 <= 0;
			p31 <= 0;
		end
		else begin
			p13 <= p12;
			p23 <= p22;
			p33 <= p32;
			p12 <= p11;
			p22 <= p21;
			p32 <= p31;
			p11 <= in_data;
			p21 <= tap0x;
			p31 <= tap1x;
		end
	end
	
	reg [BITS+1:0] gx1,gx3,gy1,gy3,gx,gy;
	reg [BITS+2:0] g;
	reg [BITS-1:0] out;
	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n) begin
			gx1 <= 0;
			gx3 <= 0;
			gy1 <= 0;
			gy3 <= 0;
			gx <= 0;
			gy <= 0;
			g <= 0;
			out <= 0;
		end
		else begin
			gx1 <= p11 + (p21 << 1) + p31;
			gx3 <= p13 + (p23 << 1) + p33;
			gy1 <= p11 + (p12 << 1) + p13;
			gy3 <= p31 + (p32 << 1) + p33;
			gx <= gx1 > gx3 ? gx1 - gx3 : gx3 - gx1;
			gy <= gy1 > gy3 ? gy1 - gy3 : gy3 - gy1;
			g <= gx + gy;
			out <= g > {BITS{1'b1}} ? {BITS{1'b1}} : g[BITS-1:0];
		end
	end
	
	localparam DLY_CLK = 7;
	reg [DLY_CLK-1:0] href_dly;
	reg [DLY_CLK-1:0] vsync_dly;
	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n) begin
			href_dly <= 0;
			vsync_dly <= 0;
		end
		else begin
			href_dly <= {href_dly[DLY_CLK-2:0], in_href};
			vsync_dly <= {vsync_dly[DLY_CLK-2:0], in_vsync};
		end
	end
	
	assign out_href = href_dly[DLY_CLK-1];
	assign out_vsync = vsync_dly[DLY_CLK-1];
	assign out_data = out_href ? out : {BITS{1'b0}};
endmodule
module vip_sobel
#(
	parameter BITS = 8,
	parameter WIDTH = 640,
	parameter HEIGHT = 480
)
(
	input pclk,
	input rst_n,

	input in_href,
	input in_vsync,
	input [BITS-1:0] in_data,

	output out_href,
	output out_vsync,
	output [BITS-1:0] out_data
);


	wire [BITS-1:0] shiftout;
	wire [BITS-1:0] tap1x, tap0x;
	shift_register #(BITS, WIDTH, 2) line2buf(pclk, in_href, in_data, shiftout, {tap1x, tap0x});
	
	reg [BITS-1:0] p11,p12,p13;
	reg [BITS-1:0] p21,p22,p23;
	reg [BITS-1:0] p31,p32,p33;
	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n) begin
			p13 <= 0;
			p23 <= 0;
			p33 <= 0;
			p12 <= 0;
			p22 <= 0;
			p32 <= 0;
			p11 <= 0;
			p21 <= 0;
			p31 <= 0;
		end
		else begin
			p13 <= p12;
			p23 <= p22;
			p33 <= p32;
			p12 <= p11;
			p22 <= p21;
			p32 <= p31;
			p11 <= in_data;
			p21 <= tap0x;
			p31 <= tap1x;
		end
	end
	
	reg [BITS+1:0] gx1,gx3,gy1,gy3,gx,gy;
	reg [BITS+2:0] g;
	reg [BITS-1:0] out;
	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n) begin
			gx1 <= 0;
			gx3 <= 0;
			gy1 <= 0;
			gy3 <= 0;
			gx <= 0;
			gy <= 0;
			g <= 0;
			out <= 0;
		end
		else begin
			gx1 <= p11 + (p21 << 1) + p31;
			gx3 <= p13 + (p23 << 1) + p33;
			gy1 <= p11 + (p12 << 1) + p13;
			gy3 <= p31 + (p32 << 1) + p33;
			gx <= gx1 > gx3 ? gx1 - gx3 : gx3 - gx1;
			gy <= gy1 > gy3 ? gy1 - gy3 : gy3 - gy1;
			g <= gx + gy;
			out <= g > {BITS{1'b1}} ? {BITS{1'b1}} : g[BITS-1:0];
		end
	end
	
	localparam DLY_CLK = 7;
	reg [DLY_CLK-1:0] href_dly;
	reg [DLY_CLK-1:0] vsync_dly;
	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n) begin
			href_dly <= 0;
			vsync_dly <= 0;
		end
		else begin
			href_dly <= {href_dly[DLY_CLK-2:0], in_href};
			vsync_dly <= {vsync_dly[DLY_CLK-2:0], in_vsync};
		end
	end
	
	assign out_href = href_dly[DLY_CLK-1];
	assign out_vsync = vsync_dly[DLY_CLK-1];
	assign out_data = out_href ? out : {BITS{1'b0}};
endmodule