data/full_repos/permissive/449071180/tb_bcd_inverse.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_bcd_inverse.v:17: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/449071180/tb_bcd_inverse.v:7: Cannot find file containing module: \'bcd_inverse\'\nbcd_inverse port_map(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/bcd_inverse\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/bcd_inverse.v\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/bcd_inverse.sv\n             bcd_inverse\n             bcd_inverse.v\n             bcd_inverse.sv\n             obj_dir/bcd_inverse\n             obj_dir/bcd_inverse.v\n             obj_dir/bcd_inverse.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_bcd_inverse();

reg [7:0] in_test;

wire [2:0] out_test;

bcd_inverse port_map(
.in(in_test),
.out(out_test)
);


initial begin
in_test = 8'b1;
end
always begin
#5;
in_test = in_test << 1;
end



endmodule
module tb_bcd_inverse();


reg [7:0] in_test;

wire [2:0] out_test;

bcd_inverse port_map(
.in(in_test),
.out(out_test)
);


initial begin
in_test = 8'b1;
end
always begin
#5;
in_test = in_test << 1;
end



endmodule