data/full_repos/permissive/492581806/cpu.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/492581806/cpu.v:50: Unsupported: Ignoring delay on this delayed statement.\n#1 pc= pc+4;                              \n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/492581806/cpu.v:59: Unsupported: Ignoring delay on this delayed statement.\n#0.9 PC =  pc;                             \n^\n%Warning-STMTDLY: data/full_repos/permissive/492581806/cpu.v:63: Unsupported: Ignoring delay on this delayed statement.\n#0.9 PC =  pc;                             \n^\n%Warning-STMTDLY: data/full_repos/permissive/492581806/cpu.v:55: Unsupported: Ignoring delay on this delayed statement.\n#0.1\n^\n%Warning-STMTDLY: data/full_repos/permissive/492581806/cpu.v:71: Unsupported: Ignoring delay on this delayed statement.\n#1;\n^\n%Error: data/full_repos/permissive/492581806/cpu.v:234: Cannot find file containing module: \'reg_file\'\nreg_file myreg (INDATA, out1,out2,INSTRUCTION [18:16], INSTRUCTION[10:8] , INSTRUCTION[2:0] , WRITEENABLE , CLK , RESET,BUSYWAIT,INSBUSYWAIT);\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/492581806,data/full_repos/permissive/492581806/reg_file\n             data/full_repos/permissive/492581806,data/full_repos/permissive/492581806/reg_file.v\n             data/full_repos/permissive/492581806,data/full_repos/permissive/492581806/reg_file.sv\n             reg_file\n             reg_file.v\n             reg_file.sv\n             obj_dir/reg_file\n             obj_dir/reg_file.v\n             obj_dir/reg_file.sv\n%Error: data/full_repos/permissive/492581806/cpu.v:288: Cannot find file containing module: \'alu\'\nalu myalu (out1,outmux2,aluresult,ALUOP,ZERO);   \n^~~\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cpu(PC, INSTRUCTION, CLK, RESET,BUSYWAIT,READ,WRITE,WRITEDATA,READDATA,ADDRESS,INSBUSYWAIT);

input [31:0] INSTRUCTION;
input CLK,RESET;
output reg [31:0] PC;
output reg READ,WRITE;
input BUSYWAIT,INSBUSYWAIT;
input [7:0] READDATA;
output reg [7:0] WRITEDATA;
output [7:0] ADDRESS;
reg DatamemSelect;
reg WRITEENABLE;
reg [7:0] INDATA;
wire [7:0] aluresult,out1,out2;
reg select1,select2,select3,select4;
wire select5,and_output;
reg  [2:0] ALUOP;
wire [7:0] complement;
reg  [7:0] outmux1,outmux2;
reg  [31:0] pc;
wire ZERO,busywait;


reg signed [9:0] leftshift;
reg signed [31:0] extended;
wire  [31:0]target;




always@(PC)
begin
if(BUSYWAIT==0 && INSBUSYWAIT==0)
#1 pc= pc+4;
end

always@(posedge CLK)
begin
#0.1
if(RESET)
begin
pc=0;
#0.9 PC =  pc;
end
else
if(BUSYWAIT==0 && INSBUSYWAIT==0)
#0.9 PC =  pc;
end




always@(INSTRUCTION)
begin
#1;
case(INSTRUCTION[31:24])

            
8'b00000010:begin
	 ALUOP= 3'b001; 
         select1=0;
         select2=0;
	 select3=0;
	 select4=0;
	 WRITEENABLE=1;
	DatamemSelect=0;
	 READ=0;
	 WRITE=0;
         end
      
8'b00000011:begin
	ALUOP= 3'b001;
      	select1=1;
    	select2=0;
	select3=0;
	select4=0;
	WRITEENABLE=1;
	DatamemSelect=0;
	READ=0;
	WRITE=0;
	end                
8'b00000100:begin
	ALUOP= 3'b010;  
	select1=0;
        select2=0;
	select3=0;
	select4=0;
	WRITEENABLE=1;
	DatamemSelect=0;
	READ=0;
	WRITE=0;
	end      
8'b00000101:begin
	ALUOP= 3'b011;  
	select1=0;
	select2=0; 
	select3=0;
	select4=0;
	WRITEENABLE=1;
	DatamemSelect=0;
	 READ=0;
	 WRITE=0;
	end            
8'b00000001:begin
	ALUOP= 3'b000;
	select1=0;
	select2=0; 
	select3=0;
	select4=0;
	WRITEENABLE=1;
	DatamemSelect=0;
	READ=0;
	 WRITE=0;
	end  
            
8'b00000000:begin
	ALUOP= 3'b000;
	select1=0;
	select2=1;
	select3=0;
	select4=0;
	WRITEENABLE=1;
	DatamemSelect=0;
	READ=0;
	 WRITE=0;
	end
8'b00000111:begin
	ALUOP= 3'b001;
	select1=1;
	select2=0;
	select3=1;
	select4=0;
	WRITEENABLE=0;
	DatamemSelect=0;
	READ=0;
	 WRITE=0;
	end       
8'b00000110:begin
	ALUOP= 3'b100;
	select1=0;
	select2=0;
	select3=0;
	select4=1;
	WRITEENABLE=0;
	DatamemSelect=0;
	READ=0;
	 WRITE=0;
	end  
8'b00001000:begin
        ALUOP= 3'b000;
	select1=0;
	select2=0;
	select3=0;
	select4=0;
	WRITEENABLE=1;
	DatamemSelect=1;
	READ=1;
	WRITE=0;
	end
     
8'b00001001:begin
        ALUOP= 3'b000;
	select1=0;
	select2=1;
	select3=0;
	select4=0;
	WRITEENABLE=1;
	DatamemSelect=1;
	READ=1;
	WRITE=0;
	end
8'b00001010:begin
        ALUOP= 3'b000;
	select1=0;
	select2=0;
	select3=0;
	select4=0;
	WRITEENABLE=0;
	DatamemSelect=0;
	READ=0;
	WRITE=1;
	end
8'b00001011:begin
        ALUOP= 3'b000;
	select1=0;
	select2=1;
	select3=0;
	select4=0;
        DatamemSelect=0;
	WRITEENABLE=0;
	READ=0;
	 WRITE=1;
	end
     
         
endcase
end


always@(negedge BUSYWAIT)
begin
READ=0;
WRITE=0;
end


always@(DatamemSelect,aluresult,READDATA)    
begin
if(DatamemSelect)
INDATA=READDATA;
else
INDATA=aluresult;
end




reg_file myreg (INDATA, out1,out2,INSTRUCTION [18:16], INSTRUCTION[10:8] , INSTRUCTION[2:0] , WRITEENABLE , CLK , RESET,BUSYWAIT,INSBUSYWAIT);



always@(out1,WRITEDATA)
begin
WRITEDATA=out1;
end


assign #1 complement=(~out2+8'b00000001);


always@(complement,out2,select1)
begin
if (select1)
     outmux1= complement;
else
     outmux1=out2;
end

always@(outmux1,INSTRUCTION,select2)
begin
if (select2)
     outmux2=INSTRUCTION[7:0];
else
    outmux2=outmux1;
end

assign and_output=select3 & ZERO;
assign select5=and_output |select4;
 

always @(INSTRUCTION)
begin
leftshift[1:0]=2'b00;
leftshift[9:2]=INSTRUCTION[23:16];
extended[9:0]=leftshift[9:0];
extended[31:10]={22{leftshift[9]}};
end

assign #2 target=extended+PC+4;


always@(target,select5)
begin
if (select5)
     pc=target;
else
    pc=PC+4;
end



alu myalu (out1,outmux2,aluresult,ALUOP,ZERO);
assign ADDRESS=aluresult;


endmodule
module cpu(PC, INSTRUCTION, CLK, RESET,BUSYWAIT,READ,WRITE,WRITEDATA,READDATA,ADDRESS,INSBUSYWAIT);


input [31:0] INSTRUCTION;
input CLK,RESET;
output reg [31:0] PC;
output reg READ,WRITE;
input BUSYWAIT,INSBUSYWAIT;
input [7:0] READDATA;
output reg [7:0] WRITEDATA;
output [7:0] ADDRESS;
reg DatamemSelect;
reg WRITEENABLE;
reg [7:0] INDATA;
wire [7:0] aluresult,out1,out2;
reg select1,select2,select3,select4;
wire select5,and_output;
reg  [2:0] ALUOP;
wire [7:0] complement;
reg  [7:0] outmux1,outmux2;
reg  [31:0] pc;
wire ZERO,busywait;


reg signed [9:0] leftshift;
reg signed [31:0] extended;
wire  [31:0]target;




always@(PC)
begin
if(BUSYWAIT==0 && INSBUSYWAIT==0)
#1 pc= pc+4;
end

always@(posedge CLK)
begin
#0.1
if(RESET)
begin
pc=0;
#0.9 PC =  pc;
end
else
if(BUSYWAIT==0 && INSBUSYWAIT==0)
#0.9 PC =  pc;
end




always@(INSTRUCTION)
begin
#1;
case(INSTRUCTION[31:24])

            
8'b00000010:begin
	 ALUOP= 3'b001; 
         select1=0;
         select2=0;
	 select3=0;
	 select4=0;
	 WRITEENABLE=1;
	DatamemSelect=0;
	 READ=0;
	 WRITE=0;
         end
      
8'b00000011:begin
	ALUOP= 3'b001;
      	select1=1;
    	select2=0;
	select3=0;
	select4=0;
	WRITEENABLE=1;
	DatamemSelect=0;
	READ=0;
	WRITE=0;
	end                
8'b00000100:begin
	ALUOP= 3'b010;  
	select1=0;
        select2=0;
	select3=0;
	select4=0;
	WRITEENABLE=1;
	DatamemSelect=0;
	READ=0;
	WRITE=0;
	end      
8'b00000101:begin
	ALUOP= 3'b011;  
	select1=0;
	select2=0; 
	select3=0;
	select4=0;
	WRITEENABLE=1;
	DatamemSelect=0;
	 READ=0;
	 WRITE=0;
	end            
8'b00000001:begin
	ALUOP= 3'b000;
	select1=0;
	select2=0; 
	select3=0;
	select4=0;
	WRITEENABLE=1;
	DatamemSelect=0;
	READ=0;
	 WRITE=0;
	end  
            
8'b00000000:begin
	ALUOP= 3'b000;
	select1=0;
	select2=1;
	select3=0;
	select4=0;
	WRITEENABLE=1;
	DatamemSelect=0;
	READ=0;
	 WRITE=0;
	end
8'b00000111:begin
	ALUOP= 3'b001;
	select1=1;
	select2=0;
	select3=1;
	select4=0;
	WRITEENABLE=0;
	DatamemSelect=0;
	READ=0;
	 WRITE=0;
	end       
8'b00000110:begin
	ALUOP= 3'b100;
	select1=0;
	select2=0;
	select3=0;
	select4=1;
	WRITEENABLE=0;
	DatamemSelect=0;
	READ=0;
	 WRITE=0;
	end  
8'b00001000:begin
        ALUOP= 3'b000;
	select1=0;
	select2=0;
	select3=0;
	select4=0;
	WRITEENABLE=1;
	DatamemSelect=1;
	READ=1;
	WRITE=0;
	end
     
8'b00001001:begin
        ALUOP= 3'b000;
	select1=0;
	select2=1;
	select3=0;
	select4=0;
	WRITEENABLE=1;
	DatamemSelect=1;
	READ=1;
	WRITE=0;
	end
8'b00001010:begin
        ALUOP= 3'b000;
	select1=0;
	select2=0;
	select3=0;
	select4=0;
	WRITEENABLE=0;
	DatamemSelect=0;
	READ=0;
	WRITE=1;
	end
8'b00001011:begin
        ALUOP= 3'b000;
	select1=0;
	select2=1;
	select3=0;
	select4=0;
        DatamemSelect=0;
	WRITEENABLE=0;
	READ=0;
	 WRITE=1;
	end
     
         
endcase
end


always@(negedge BUSYWAIT)
begin
READ=0;
WRITE=0;
end


always@(DatamemSelect,aluresult,READDATA)    
begin
if(DatamemSelect)
INDATA=READDATA;
else
INDATA=aluresult;
end




reg_file myreg (INDATA, out1,out2,INSTRUCTION [18:16], INSTRUCTION[10:8] , INSTRUCTION[2:0] , WRITEENABLE , CLK , RESET,BUSYWAIT,INSBUSYWAIT);



always@(out1,WRITEDATA)
begin
WRITEDATA=out1;
end


assign #1 complement=(~out2+8'b00000001);


always@(complement,out2,select1)
begin
if (select1)
     outmux1= complement;
else
     outmux1=out2;
end

always@(outmux1,INSTRUCTION,select2)
begin
if (select2)
     outmux2=INSTRUCTION[7:0];
else
    outmux2=outmux1;
end

assign and_output=select3 & ZERO;
assign select5=and_output |select4;
 

always @(INSTRUCTION)
begin
leftshift[1:0]=2'b00;
leftshift[9:2]=INSTRUCTION[23:16];
extended[9:0]=leftshift[9:0];
extended[31:10]={22{leftshift[9]}};
end

assign #2 target=extended+PC+4;


always@(target,select5)
begin
if (select5)
     pc=target;
else
    pc=PC+4;
end



alu myalu (out1,outmux2,aluresult,ALUOP,ZERO);
assign ADDRESS=aluresult;


endmodule