data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/tech_cells_generic/src/pulp_clock_inverter.sv
data/verilator_xmls/a151528c-08b6-4d4e-908b-35d6a75ddccd.xml
module pulp_clock_inverter
  (
   input  logic clk_i,
   output logic clk_o
   );
   
   assign clk_o = ~clk_i;
   
endmodule
module pulp_clock_inverter
  (
   input  logic clk_i,
   output logic clk_o
   );

   
   assign clk_o = ~clk_i;
   
endmodule