data/full_repos/permissive/449807379/CPU_design/bitxor.v
1: b'%Warning-WIDTH: data/full_repos/permissive/449807379/CPU_design/bitxor.v:17: Operator XOR expects 33 bits on the LHS, but LHS\'s SEL generates 32 bits.\n                                                                           : ... In instance bit_xor\nassign temp = bit_xor_en ? (in1[31:0] ^ in2[31:0]) : 32\'bz;\n                                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/449807379/CPU_design/bitxor.v:17: Operator XOR expects 33 bits on the RHS, but RHS\'s SEL generates 32 bits.\n                                                                           : ... In instance bit_xor\nassign temp = bit_xor_en ? (in1[31:0] ^ in2[31:0]) : 32\'bz;\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/449807379/CPU_design/bitxor.v:17: Operator COND expects 33 bits on the Conditional False, but Conditional False\'s CONST \'32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz\' generates 32 bits.\n                                                                           : ... In instance bit_xor\nassign temp = bit_xor_en ? (in1[31:0] ^ in2[31:0]) : 32\'bz;\n                         ^\n%Error: Exiting due to 3 warning(s)\n'
module bit_xor(in1, in2, out, bit_xor_en);

input [31:0] in1, in2;
input bit_xor_en;

output [35:0] out;

wire [32:0] temp;

wire isNegative, isZero, hasCarry, hasOverflow;

assign isNegative = (temp[31] == 1'b1) ? 1'b1 : 1'b0;
assign isZero = (temp[31:0] == 32'b0) ? 1'b1 : 1'b0;
assign hasCarry = 1'b0;
assign hasOverflow = 1'b0;

assign temp = bit_xor_en ? (in1[31:0] ^ in2[31:0]) : 32'bz;

assign out = {isNegative, isZero, hasCarry, hasOverflow, temp[31:0] };

endmodule
module bit_xor(in1, in2, out, bit_xor_en);


input [31:0] in1, in2;
input bit_xor_en;

output [35:0] out;

wire [32:0] temp;

wire isNegative, isZero, hasCarry, hasOverflow;

assign isNegative = (temp[31] == 1'b1) ? 1'b1 : 1'b0;
assign isZero = (temp[31:0] == 32'b0) ? 1'b1 : 1'b0;
assign hasCarry = 1'b0;
assign hasOverflow = 1'b0;

assign temp = bit_xor_en ? (in1[31:0] ^ in2[31:0]) : 32'bz;

assign out = {isNegative, isZero, hasCarry, hasOverflow, temp[31:0] };

endmodule