data/full_repos/permissive/461069000/pwm/src/pwm_top.v
1: b'%Error: data/full_repos/permissive/461069000/pwm/src/pwm_top.v:19: Unsupported or unknown PLI call: $from_myhdl\n $from_myhdl(clk, enable, pwm_in);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/461069000/pwm/src/pwm_top.v:20: Unsupported or unknown PLI call: $to_myhdl\n $to_myhdl(out, counter_out);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/461069000/pwm/src/pwm_top.v:24: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("pwm_top.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/461069000/pwm/src/pwm_top.v:25: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars();\n    ^~~~~~~~~\n%Error: Exiting due to 4 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pwm_top;

reg clk = 0;
reg enable = 1;

reg [7:0] pwm_in;
wire out;
wire [7:0] counter_out;

pwm dut (.clk(clk), .enable(enable), .in(pwm_in) ,.out(out));


assign counter_out = dut.counter_1.out;


initial begin
	$from_myhdl(clk, enable, pwm_in);
	$to_myhdl(out, counter_out);
end

initial begin
    $dumpfile("pwm_top.vcd");
    $dumpvars();
end

endmodule
module pwm_top;


reg clk = 0;
reg enable = 1;

reg [7:0] pwm_in;
wire out;
wire [7:0] counter_out;

pwm dut (.clk(clk), .enable(enable), .in(pwm_in) ,.out(out));


assign counter_out = dut.counter_1.out;


initial begin
	$from_myhdl(clk, enable, pwm_in);
	$to_myhdl(out, counter_out);
end

initial begin
    $dumpfile("pwm_top.vcd");
    $dumpvars();
end

endmodule