data/full_repos/permissive/458313092/UART_RX/UART_RX_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/458313092/UART_RX/UART_RX_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n   #period clk = ~clk;    \n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458313092/UART_RX/UART_RX_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n   #10 ; \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/UART_RX/UART_RX_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n   #(clock_per_bit_uart*8);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/UART_RX/UART_RX_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n   #(clock_per_bit_uart*8);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/UART_RX/UART_RX_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n   #(clock_per_bit_uart*8);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/UART_RX/UART_RX_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n   #(clock_per_bit_uart*8);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/UART_RX/UART_RX_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n   #(clock_per_bit_uart*8);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/UART_RX/UART_RX_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n   #(clock_per_bit_uart*8);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/UART_RX/UART_RX_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n   #(clock_per_bit_uart*8);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/UART_RX/UART_RX_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n   #(clock_per_bit_uart*8);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/UART_RX/UART_RX_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n   #(clock_per_bit_uart*8);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/UART_RX/UART_RX_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n   #(clock_per_bit_uart*8);  \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/UART_RX/UART_RX_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n   #(clock_per_bit_uart*8);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/UART_RX/UART_RX_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n   #(clock_per_bit_uart*8);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/UART_RX/UART_RX_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n   #(clock_per_bit_uart*8);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/UART_RX/UART_RX_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n   #(clock_per_bit_uart*8);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/UART_RX/UART_RX_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n   #(clock_per_bit_uart*8);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/UART_RX/UART_RX_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n   #(clock_per_bit_uart*8);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/UART_RX/UART_RX_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n   #(clock_per_bit_uart*8);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/UART_RX/UART_RX_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n   #(clock_per_bit_uart*8);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/UART_RX/UART_RX_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n   #(clock_per_bit_uart*8);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/UART_RX/UART_RX_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n   #(clock_per_bit_uart*8);  \n   ^\n%Error: data/full_repos/permissive/458313092/UART_RX/UART_RX_tb.v:14: Cannot find file containing module: \'UART_RX\'\n UART_RX #(.clock_per_bit(clock_per_bit_uart) ) UUT (.Data_out(Data_out_t), .serial_rx(serial_rx_t) , .clk(clk), .data_ready(data_ready_t));\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458313092/UART_RX,data/full_repos/permissive/458313092/UART_RX\n             data/full_repos/permissive/458313092/UART_RX,data/full_repos/permissive/458313092/UART_RX.v\n             data/full_repos/permissive/458313092/UART_RX,data/full_repos/permissive/458313092/UART_RX.sv\n             UART_RX\n             UART_RX.v\n             UART_RX.sv\n             obj_dir/UART_RX\n             obj_dir/UART_RX.v\n             obj_dir/UART_RX.sv\n%Error: Exiting due to 1 error(s), 22 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module UART_RX_tb;
	
	reg clk = 1'b0;
	localparam clock_per_bit_uart = 10;
	wire[7:0] Data_out_t;
	wire data_ready_t;
	reg serial_rx_t;
	
	localparam period = 4; 
	
	UART_RX #(.clock_per_bit(clock_per_bit_uart) ) UUT (.Data_out(Data_out_t), .serial_rx(serial_rx_t) , .clk(clk), .data_ready(data_ready_t));
	
	
	
	always
		begin
			#period clk = ~clk;    
		end
	
	always
		
		begin  
			
			
			serial_rx_t = 1'b1;
			#10	; 

			
			serial_rx_t = 1'b0;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b1;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b0;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b0;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b0;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b0;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b1;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b0;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b1;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b1;
			#(clock_per_bit_uart*8);  

			
			
			

			
			serial_rx_t = 1'b0;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b0;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b0;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b0;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b0;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b0;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b0;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b0;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b1;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b1;
			#(clock_per_bit_uart*8);  

			
			
			$stop ;
		end
	
	
endmodule
module UART_RX_tb;

	
	reg clk = 1'b0;
	localparam clock_per_bit_uart = 10;
	wire[7:0] Data_out_t;
	wire data_ready_t;
	reg serial_rx_t;
	
	localparam period = 4; 
	
	UART_RX #(.clock_per_bit(clock_per_bit_uart) ) UUT (.Data_out(Data_out_t), .serial_rx(serial_rx_t) , .clk(clk), .data_ready(data_ready_t));
	
	
	
	always
		begin
			#period clk = ~clk;    
		end
	
	always
		
		begin  
			
			
			serial_rx_t = 1'b1;
			#10	; 

			
			serial_rx_t = 1'b0;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b1;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b0;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b0;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b0;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b0;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b1;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b0;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b1;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b1;
			#(clock_per_bit_uart*8);  

			
			
			

			
			serial_rx_t = 1'b0;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b0;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b0;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b0;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b0;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b0;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b0;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b0;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b1;
			#(clock_per_bit_uart*8);
			
			serial_rx_t = 1'b1;
			#(clock_per_bit_uart*8);  

			
			
			$stop ;
		end
	
	
endmodule