data/full_repos/permissive/461141714/src/Pipelined CPU/halt_detector.v
1: b'%Error: Cannot find file containing module: CPU,data/full_repos/permissive/461141714\n        ... Looked in:\n             data/full_repos/permissive/461141714/src/Pipelined/CPU,data/full_repos/permissive/461141714\n             data/full_repos/permissive/461141714/src/Pipelined/CPU,data/full_repos/permissive/461141714.v\n             data/full_repos/permissive/461141714/src/Pipelined/CPU,data/full_repos/permissive/461141714.sv\n             CPU,data/full_repos/permissive/461141714\n             CPU,data/full_repos/permissive/461141714.v\n             CPU,data/full_repos/permissive/461141714.sv\n             obj_dir/CPU,data/full_repos/permissive/461141714\n             obj_dir/CPU,data/full_repos/permissive/461141714.v\n             obj_dir/CPU,data/full_repos/permissive/461141714.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/461141714/src/Pipelined\n%Error: Cannot find file containing module: CPU/halt_detector.v\n%Error: Exiting due to 3 error(s)\n'
module HALT_DETECTOR(
        input clk,
        input reset_n,
        
        input [`WORD_SIZE-1:0] instruction,
        output reg is_halted
    );
    initial is_halted = 0;
    always @(reset_n) if(reset_n == 0) is_halted = 0;
    
    always @(posedge clk) begin
        if(reset_n != 0) begin
            if(instruction[15:12] === `OPCODE_RRR && instruction[5:0] === `FUNC_HLT) begin
                is_halted = 1;
            end
        end
    end
    
endmodule
module HALT_DETECTOR(
        input clk,
        input reset_n,
        
        input [`WORD_SIZE-1:0] instruction,
        output reg is_halted
    );

    initial is_halted = 0;
    always @(reset_n) if(reset_n == 0) is_halted = 0;
    
    always @(posedge clk) begin
        if(reset_n != 0) begin
            if(instruction[15:12] === `OPCODE_RRR && instruction[5:0] === `FUNC_HLT) begin
                is_halted = 1;
            end
        end
    end
    
endmodule