data/full_repos/permissive/446312960/Verilog_Simulation/00_src/nand4_if.v
data/verilator_xmls/f98ae2b9-eddb-4a1b-bd36-3f568cc76f8e.xml
module nand4_if(a,y);
   input [3:0] a;
   output reg y;

   always @(a)
   begin
      if(a == 4'b1111)
      begin
         y=1'b0;
      end
      else
      begin
         y=1'b1;
      end
   end
endmodule
module nand4_if(a,y);

   input [3:0] a;
   output reg y;

   always @(a)
   begin
      if(a == 4'b1111)
      begin
         y=1'b0;
      end
      else
      begin
         y=1'b1;
      end
   end
endmodule