data/full_repos/permissive/518460376/verilog/rtl/ips/apb/apb_timer/timer.v
1: b'%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/apb/apb_timer/timer.v:31: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS\'s SEL generates 3 bits.\n                                                                                             : ... In instance timer\n assign register_adr = PADDR[4:2];\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/apb/apb_timer/timer.v:51: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                             : ... In instance timer\n   regs_n[64+:32] = 1\'b0;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/apb/apb_timer/timer.v:52: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'prescaler_int\' generates 3 bits.\n                                                                                             : ... In instance timer\n  else if ((regs_q[32] && (prescaler_int != \'b0)) && (prescaler_int == cycle_counter_q))\n                                                                    ^~\n%Error: Exiting due to 3 warning(s)\n'
module timer 
#(
    parameter APB_ADDR_WIDTH = 12
)
(
	HCLK,
	HRESETn,
	PADDR,
	PWDATA,
	PWRITE,
	PSEL,
	PENABLE,
	PRDATA,
	PREADY,
	PSLVERR,
	irq_o
);

	input wire HCLK;
	input wire HRESETn;
	input wire [APB_ADDR_WIDTH - 1:0] PADDR;
	input wire [31:0] PWDATA;
	input wire PWRITE;
	input wire PSEL;
	input wire PENABLE;
	output reg [31:0] PRDATA;
	output wire PREADY;
	output wire PSLVERR;
	output reg [1:0] irq_o;
	wire [1:0] register_adr;
	assign register_adr = PADDR[4:2];
	assign PREADY = 1'b1;
	assign PSLVERR = 1'b0;
	reg [95:0] regs_q;
	reg [95:0] regs_n;
	reg [31:0] cycle_counter_n;
	reg [31:0] cycle_counter_q;
	wire [2:0] prescaler_int;
	always @(*) begin
		irq_o = 2'b00;
		if (regs_q[64+:32] == 32'hffffffff)
			irq_o[0] = 1'b1;
		if ((regs_q[0+:32] != 'b0) && (regs_q[64+:32] == regs_q[0+:32]))
			irq_o[1] = 1'b1;
	end
	assign prescaler_int = regs_q[37-:3];
	always @(*) begin
		regs_n = regs_q;
		cycle_counter_n = cycle_counter_q + 1;
		if ((irq_o[0] == 1'b1) || (irq_o[1] == 1'b1))
			regs_n[64+:32] = 1'b0;
		else if ((regs_q[32] && (prescaler_int != 'b0)) && (prescaler_int == cycle_counter_q))
			regs_n[64+:32] = regs_q[64+:32] + 1;
		else if (regs_q[32] && (regs_q[37-:3] == 'b0))
			regs_n[64+:32] = regs_q[64+:32] + 1;
		if (cycle_counter_q >= regs_q[32+:32])
			cycle_counter_n = 32'b00000000000000000000000000000000;
		if ((PSEL && PENABLE) && PWRITE)
			case (register_adr)
				2'b00: regs_n[64+:32] = PWDATA;
				2'b01: regs_n[32+:32] = PWDATA;
				2'b10: begin
					regs_n[0+:32] = PWDATA;
					regs_n[64+:32] = 32'b00000000000000000000000000000000;
				end
			endcase
	end
	always @(*) begin
		PRDATA = 'b0;
		if ((PSEL && PENABLE) && !PWRITE)
			case (register_adr)
				2'b00: PRDATA = regs_q[64+:32];
				2'b01: PRDATA = regs_q[32+:32];
				2'b10: PRDATA = regs_q[0+:32];
			endcase
	end
	always @(posedge HCLK or negedge HRESETn)
		if (~HRESETn) begin
			regs_q <= {3 {32'b00000000000000000000000000000000}};
			cycle_counter_q <= 32'b00000000000000000000000000000000;
		end
		else begin
			regs_q <= regs_n;
			cycle_counter_q <= cycle_counter_n;
		end
endmodule
module timer 
#(
    parameter APB_ADDR_WIDTH = 12
)
(
	HCLK,
	HRESETn,
	PADDR,
	PWDATA,
	PWRITE,
	PSEL,
	PENABLE,
	PRDATA,
	PREADY,
	PSLVERR,
	irq_o
);


	input wire HCLK;
	input wire HRESETn;
	input wire [APB_ADDR_WIDTH - 1:0] PADDR;
	input wire [31:0] PWDATA;
	input wire PWRITE;
	input wire PSEL;
	input wire PENABLE;
	output reg [31:0] PRDATA;
	output wire PREADY;
	output wire PSLVERR;
	output reg [1:0] irq_o;
	wire [1:0] register_adr;
	assign register_adr = PADDR[4:2];
	assign PREADY = 1'b1;
	assign PSLVERR = 1'b0;
	reg [95:0] regs_q;
	reg [95:0] regs_n;
	reg [31:0] cycle_counter_n;
	reg [31:0] cycle_counter_q;
	wire [2:0] prescaler_int;
	always @(*) begin
		irq_o = 2'b00;
		if (regs_q[64+:32] == 32'hffffffff)
			irq_o[0] = 1'b1;
		if ((regs_q[0+:32] != 'b0) && (regs_q[64+:32] == regs_q[0+:32]))
			irq_o[1] = 1'b1;
	end
	assign prescaler_int = regs_q[37-:3];
	always @(*) begin
		regs_n = regs_q;
		cycle_counter_n = cycle_counter_q + 1;
		if ((irq_o[0] == 1'b1) || (irq_o[1] == 1'b1))
			regs_n[64+:32] = 1'b0;
		else if ((regs_q[32] && (prescaler_int != 'b0)) && (prescaler_int == cycle_counter_q))
			regs_n[64+:32] = regs_q[64+:32] + 1;
		else if (regs_q[32] && (regs_q[37-:3] == 'b0))
			regs_n[64+:32] = regs_q[64+:32] + 1;
		if (cycle_counter_q >= regs_q[32+:32])
			cycle_counter_n = 32'b00000000000000000000000000000000;
		if ((PSEL && PENABLE) && PWRITE)
			case (register_adr)
				2'b00: regs_n[64+:32] = PWDATA;
				2'b01: regs_n[32+:32] = PWDATA;
				2'b10: begin
					regs_n[0+:32] = PWDATA;
					regs_n[64+:32] = 32'b00000000000000000000000000000000;
				end
			endcase
	end
	always @(*) begin
		PRDATA = 'b0;
		if ((PSEL && PENABLE) && !PWRITE)
			case (register_adr)
				2'b00: PRDATA = regs_q[64+:32];
				2'b01: PRDATA = regs_q[32+:32];
				2'b10: PRDATA = regs_q[0+:32];
			endcase
	end
	always @(posedge HCLK or negedge HRESETn)
		if (~HRESETn) begin
			regs_q <= {3 {32'b00000000000000000000000000000000}};
			cycle_counter_q <= 32'b00000000000000000000000000000000;
		end
		else begin
			regs_q <= regs_n;
			cycle_counter_q <= cycle_counter_n;
		end
endmodule