data/full_repos/permissive/492140037/CPU/设计文件/dmemory32.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/492140037/CPU/\xe8\xae\xbe\xe8\xae\xa1\xe6\x96\x87\xe4\xbb\xb6/dmemory32.v:14: Signal definition not found, creating implicitly: \'clk\'\n                                                                                       : ... Suggested alternative: \'clock\'\n    assign clk = !clock;\n           ^~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/492140037/CPU/\xe8\xae\xbe\xe8\xae\xa1\xe6\x96\x87\xe4\xbb\xb6/dmemory32.v:23: Cannot find file containing module: \'RAM\'\n    RAM ram(\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/492140037/CPU/\xe8\xae\xbe\xe8\xae\xa1\xe6\x96\x87\xe4\xbb\xb6,data/full_repos/permissive/492140037/RAM\n             data/full_repos/permissive/492140037/CPU/\xe8\xae\xbe\xe8\xae\xa1\xe6\x96\x87\xe4\xbb\xb6,data/full_repos/permissive/492140037/RAM.v\n             data/full_repos/permissive/492140037/CPU/\xe8\xae\xbe\xe8\xae\xa1\xe6\x96\x87\xe4\xbb\xb6,data/full_repos/permissive/492140037/RAM.sv\n             RAM\n             RAM.v\n             RAM.sv\n             obj_dir/RAM\n             obj_dir/RAM.v\n             obj_dir/RAM.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module dmemory32(clock,memWrite,address,writeData,readData,upg_rst_i,upg_clk_i,upg_wen_i,upg_adr_i
,upg_dat_i,upg_done_i);

    input clock, memWrite;

    input [31:0] address;

    input [31:0] writeData;

    output[31:0] readData;

    assign clk = !clock;
    input upg_rst_i,upg_clk_i,upg_wen_i;
    input [13:0] upg_adr_i;
    input [31:0] upg_dat_i;
    input upg_done_i;
    wire kickOff = upg_rst_i|(~upg_rst_i&upg_done_i);



    RAM ram(
        .clka(kickOff? clk:upg_clk_i),
        .wea(kickOff? memWrite:upg_wen_i),
        .addra(kickOff? address[15:2]:upg_adr_i),
        .dina(kickOff? writeData:upg_dat_i),
        .douta(readData)
    );


endmodule
module dmemory32(clock,memWrite,address,writeData,readData,upg_rst_i,upg_clk_i,upg_wen_i,upg_adr_i
,upg_dat_i,upg_done_i);


    input clock, memWrite;

    input [31:0] address;

    input [31:0] writeData;

    output[31:0] readData;

    assign clk = !clock;
    input upg_rst_i,upg_clk_i,upg_wen_i;
    input [13:0] upg_adr_i;
    input [31:0] upg_dat_i;
    input upg_done_i;
    wire kickOff = upg_rst_i|(~upg_rst_i&upg_done_i);



    RAM ram(
        .clka(kickOff? clk:upg_clk_i),
        .wea(kickOff? memWrite:upg_wen_i),
        .addra(kickOff? address[15:2]:upg_adr_i),
        .dina(kickOff? writeData:upg_dat_i),
        .douta(readData)
    );


endmodule