data/full_repos/permissive/493019833/test/testcase/firrtl/SignedAdder.lo/sbt/SignedAdder.lo.v
data/verilator_xmls/38fa1e6a-86b2-4c8f-97c5-359cba3079c1.xml
module SignedAdder(
  input         clock,
  input         reset,
  input  [15:0] io_in0,
  input  [15:0] io_in1,
  output [15:0] io_out
);
  assign io_out = $signed(io_in0) + $signed(io_in1);
endmodule
module SignedAdder(
  input         clock,
  input         reset,
  input  [15:0] io_in0,
  input  [15:0] io_in1,
  output [15:0] io_out
);

  assign io_out = $signed(io_in0) + $signed(io_in1);
endmodule