data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:39: Cannot find include file: c_functions.v\n`include "c_functions.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v.v\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v.sv\n             c_functions.v\n             c_functions.v.v\n             c_functions.v.sv\n             obj_dir/c_functions.v\n             obj_dir/c_functions.v.v\n             obj_dir/c_functions.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:40: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:41: Cannot find include file: rtr_constants.v\n`include "rtr_constants.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:42: Cannot find include file: vcr_constants.v\n`include "vcr_constants.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:79: Define or directive not defined: \'`CONNECTIVITY_LINE\'\n   parameter connectivity = `CONNECTIVITY_LINE;\n                            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:79: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter connectivity = `CONNECTIVITY_LINE;\n                                              ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:83: Define or directive not defined: \'`CONNECTIVITY_LINE\'\n     = ((connectivity == `CONNECTIVITY_LINE) ||\n                         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:83: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n     = ((connectivity == `CONNECTIVITY_LINE) ||\n                                           ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:84: Define or directive not defined: \'`CONNECTIVITY_RING\'\n (connectivity == `CONNECTIVITY_RING)) ?\n                  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:86: Define or directive not defined: \'`CONNECTIVITY_FULL\'\n       (connectivity == `CONNECTIVITY_FULL) ?\n                        ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:98: Define or directive not defined: \'`PACKET_FORMAT_EXPLICIT_LENGTH\'\n   parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;\n                             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:98: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;\n                                                           ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:129: Define or directive not defined: \'`PACKET_FORMAT_HEAD_TAIL\'\n     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:129: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? \n                                                 ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:131: Define or directive not defined: \'`PACKET_FORMAT_TAIL_ONLY\'\n       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:133: Define or directive not defined: \'`PACKET_FORMAT_EXPLICIT_LENGTH\'\n       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:146: Define or directive not defined: \'`ROUTING_TYPE_PHASED_DOR\'\n   parameter routing_type = `ROUTING_TYPE_PHASED_DOR;\n                            ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:146: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter routing_type = `ROUTING_TYPE_PHASED_DOR;\n                                                    ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:150: Define or directive not defined: \'`ROUTING_TYPE_PHASED_DOR\'\n     = (routing_type == `ROUTING_TYPE_PHASED_DOR) ? \n                        ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:150: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n     = (routing_type == `ROUTING_TYPE_PHASED_DOR) ? \n                                                ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:159: Define or directive not defined: \'`PACKET_FORMAT_HEAD_TAIL\'\n     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:159: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? \n                                                 ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:161: Define or directive not defined: \'`PACKET_FORMAT_TAIL_ONLY\'\n       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:163: Define or directive not defined: \'`PACKET_FORMAT_EXPLICIT_LENGTH\'\n       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:168: Define or directive not defined: \'`DIM_ORDER_ASCENDING\'\n   parameter dim_order = `DIM_ORDER_ASCENDING;\n                         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:168: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter dim_order = `DIM_ORDER_ASCENDING;\n                                             ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:171: Define or directive not defined: \'`ELIG_MASK_NONE\'\n   parameter elig_mask = `ELIG_MASK_NONE;\n                         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:171: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter elig_mask = `ELIG_MASK_NONE;\n                                        ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:174: Define or directive not defined: \'`ELIG_MASK_USED\'\n   localparam atomic_vc_allocation = (elig_mask == `ELIG_MASK_USED);\n                                                   ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:174: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   localparam atomic_vc_allocation = (elig_mask == `ELIG_MASK_USED);\n                                                                  ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:180: Define or directive not defined: \'`FB_MGMT_TYPE_STATIC\'\n   parameter fb_mgmt_type = `FB_MGMT_TYPE_STATIC;\n                            ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:180: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter fb_mgmt_type = `FB_MGMT_TYPE_STATIC;\n                                                ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:199: Define or directive not defined: \'`RESET_TYPE_ASYNC\'\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:199: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                                           ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:723: Define or directive not defined: \'`FB_MGMT_TYPE_STATIC\'\n      if(fb_mgmt_type == `FB_MGMT_TYPE_STATIC)\n                         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:723: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      if(fb_mgmt_type == `FB_MGMT_TYPE_STATIC)\n                                             ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:786: syntax error, unexpected generate\n   generate\n   ^~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ivc_ctrl.v:790: Define or directive not defined: \'`ELIG_MASK_NONE\'\n    if(elig_mask == `ELIG_MASK_NONE)\n                    ^~~~~~~~~~~~~~~\n%Error: Exiting due to 38 error(s)\n'
module vcr_ivc_ctrl
  (clk, reset, router_address, flit_valid_in, flit_head_in, flit_tail_in, 
   flit_sel_in, header_info_in, fb_pop_tail, fb_pop_next_header_info, 
   almost_full_op_ovc, full_op_ovc, route_op, route_orc, vc_gnt, vc_sel_ovc, 
   sw_gnt, sw_sel, sw_gnt_op, flit_valid, flit_head, flit_tail, next_lar_info, 
   fb_almost_empty, fb_empty, allocated, free_nonspec, free_spec, errors);
   
`include "c_functions.v"
`include "c_constants.v"
`include "rtr_constants.v"
`include "vcr_constants.v"
   

   parameter num_message_classes = 2;
   

   parameter num_resource_classes = 2;
   

   localparam resource_class_idx_width = clogb(num_resource_classes);
   

   localparam num_packet_classes = num_message_classes * num_resource_classes;
   

   parameter num_vcs_per_class = 1;
   

   localparam num_vcs_per_message_class
     = num_resource_classes * num_vcs_per_class;
   

   localparam num_vcs = num_packet_classes * num_vcs_per_class;
   

   localparam vc_idx_width = clogb(num_vcs);
   

   parameter num_routers_per_dim = 4;
   

   parameter num_dimensions = 2;
   

   parameter num_nodes_per_router = 1;
   

   parameter connectivity = `CONNECTIVITY_LINE;
   

   localparam num_neighbors_per_dim
     = ((connectivity == `CONNECTIVITY_LINE) ||
	(connectivity == `CONNECTIVITY_RING)) ?
       2 :
       (connectivity == `CONNECTIVITY_FULL) ?
       (num_routers_per_dim - 1) :
       -1;
   

   localparam num_ports
     = num_dimensions * num_neighbors_per_dim + num_nodes_per_router;
   

   localparam port_idx_width = clogb(num_ports);
   

   parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;
   


   parameter max_payload_length = 4;
   


   parameter min_payload_length = 1;
   

   localparam payload_length_width
     = clogb(max_payload_length-min_payload_length+1);
   

   localparam flit_ctr_width = clogb(max_payload_length);
   

   localparam dim_addr_width = clogb(num_routers_per_dim);
   

   localparam router_addr_width = num_dimensions * dim_addr_width;
   

   localparam node_addr_width = clogb(num_nodes_per_router);
   

   localparam addr_width = router_addr_width + node_addr_width;
   

   localparam flit_ctrl_width
     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? 
       (1 + vc_idx_width + 1 + 1) : 
       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? 
       (1 + vc_idx_width + 1) : 
       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? 
       (1 + vc_idx_width + 1) : 
       -1;
   



   parameter restrict_turns = 1;
   

   localparam lar_info_width = port_idx_width + resource_class_idx_width;
   

   parameter routing_type = `ROUTING_TYPE_PHASED_DOR;
   

   localparam dest_info_width
     = (routing_type == `ROUTING_TYPE_PHASED_DOR) ? 
       (num_resource_classes * router_addr_width + node_addr_width) : 
       -1;
   

   localparam route_info_width = lar_info_width + dest_info_width + 1;
   

   localparam header_info_width
     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? 
       route_info_width : 
       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? 
       route_info_width : 
       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? 
       (route_info_width + payload_length_width) : 
       -1;
   

   parameter dim_order = `DIM_ORDER_ASCENDING;
   

   parameter elig_mask = `ELIG_MASK_NONE;
   

   localparam atomic_vc_allocation = (elig_mask == `ELIG_MASK_USED);
   

   parameter sw_alloc_spec = 1;
   

   parameter fb_mgmt_type = `FB_MGMT_TYPE_STATIC;
   

   parameter explicit_pipeline_register = 0;
   

   parameter vc_id = 0;
   

   localparam message_class
     = (vc_id / num_vcs_per_message_class) % num_message_classes;
   

   localparam resource_class
     = (vc_id / num_vcs_per_class) % num_resource_classes;
   

   parameter port_id = 0;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   input clk;
   input reset;
   

   input [0:router_addr_width-1] router_address;
   

   input 			 flit_valid_in;
   

   input 			 flit_head_in;
   

   input 			 flit_tail_in;
   

   input 			 flit_sel_in;
   


   input [0:header_info_width-1] header_info_in;
   

   input 			 fb_pop_tail;
   


   input [0:header_info_width-1] fb_pop_next_header_info;
   

   input [0:num_ports*num_vcs-1]   almost_full_op_ovc;
   

   input [0:num_ports*num_vcs-1]   full_op_ovc;
   

   output [0:num_ports-1] 	   route_op;
   wire [0:num_ports-1] 	   route_op;
   

   output [0:num_resource_classes-1] route_orc;
   wire [0:num_resource_classes-1]   route_orc;
   

   input 			     vc_gnt;
   

   input [0:num_vcs-1] 		     vc_sel_ovc;
   

   input 			     sw_gnt;
   

   input 			     sw_sel;
   

   input [0:num_ports-1] 	     sw_gnt_op;
   

   output 			     flit_valid;
   wire 			     flit_valid;
   

   output 			     flit_head;
   wire 			     flit_head;
   

   output 			     flit_tail;
   wire 			     flit_tail;
   


   output [0:lar_info_width-1] 	     next_lar_info;
   wire [0:lar_info_width-1] 	     next_lar_info;
   

   input 			     fb_almost_empty;
   

   input 			     fb_empty;
   

   output 			     allocated;
   wire 			     allocated;
   

   output 			     free_nonspec;
   wire 			     free_nonspec;
   

   output 			     free_spec;
   wire 			     free_spec;
   

   output [0:2] 		     errors;
   wire [0:2] 			     errors;
   
   



   
   wire 			     flit_valid_sel_in;
   assign flit_valid_sel_in = flit_valid_in & flit_sel_in;
   
   assign flit_valid = flit_valid_sel_in | ~fb_empty;
   
   wire 			     pop_active;
   assign pop_active = flit_valid_in | ~fb_empty;
   
   wire 			     flit_sent;
   
   wire 			     flit_sent_tail;
   assign flit_sent_tail = flit_sent & flit_tail;
   
   wire 			     flit_valid_sel_head_in;
   assign flit_valid_sel_head_in = flit_valid_sel_in & flit_head_in;
   
   wire 			     vc_allocated_s, vc_allocated_q;
   generate
      if(atomic_vc_allocation)
	begin
	   assign vc_allocated_s
	     = (vc_allocated_q & ~flit_valid_sel_head_in) | vc_gnt;
	   assign allocated = vc_allocated_q & ~flit_valid_sel_head_in;
	end
      else
	begin
	   assign vc_allocated_s = (vc_allocated_q | vc_gnt) & ~flit_sent_tail;
	   assign allocated = vc_allocated_q;
	end
   endgenerate
   c_dff
     #(.width(1),
       .reset_type(reset_type))
   vc_allocatedq
     (.clk(clk),
      .reset(reset),
      .active(pop_active),
      .d(vc_allocated_s),
      .q(vc_allocated_q));
   
   wire [0:num_vcs_per_message_class-1] vc_allocated_next_orc_ocvc;
   
   generate
      
      if(num_vcs_per_message_class == 1)
	assign vc_allocated_next_orc_ocvc = 1'b1;
      else if(num_vcs_per_message_class > 1)
	begin
	   
	   wire [0:num_vcs_per_message_class-1] vc_sel_orc_ocvc;
	   assign vc_sel_orc_ocvc
	     = vc_sel_ovc[message_class*num_vcs_per_message_class:
	                  (message_class+1)*num_vcs_per_message_class-1];
	   
	   wire [0:num_vcs_per_message_class-1] vc_allocated_orc_ocvc_q;
	   
	   assign vc_allocated_next_orc_ocvc
	     = allocated ? vc_allocated_orc_ocvc_q : vc_sel_orc_ocvc;
	   
	   wire [0:num_vcs_per_message_class-1] vc_allocated_orc_ocvc_s;
	   assign vc_allocated_orc_ocvc_s = vc_allocated_next_orc_ocvc;
	   c_dff
	     #(.width(num_vcs_per_message_class),
	       .reset_type(reset_type))
	   vc_allocated_orc_ocvcq
	     (.clk(clk),
	      .reset(1'b0),
	      .active(pop_active),
	      .d(vc_allocated_orc_ocvc_s),
	      .q(vc_allocated_orc_ocvc_q));
	   
	end
      
   endgenerate
   
   wire [0:num_vcs-1] vc_allocated_next_ovc;
   c_align
     #(.in_width(num_vcs_per_message_class),
       .out_width(num_vcs),
       .offset(message_class*num_vcs_per_message_class))
   vc_allocated_next_ovc_agn
     (.data_in(vc_allocated_next_orc_ocvc),
      .dest_in({num_vcs{1'b0}}),
      .data_out(vc_allocated_next_ovc));
   
   



   
   assign flit_tail = fb_empty ? flit_tail_in : fb_pop_tail;
   
   wire 	      htr_flit_head_s, htr_flit_head_q;
   assign htr_flit_head_s = flit_sent ? flit_tail : htr_flit_head_q;
   c_dff
     #(.width(1),
       .reset_type(reset_type),
       .reset_value(1'b1))
   htr_flit_headq
     (.clk(clk),
      .reset(reset),
      .active(pop_active),
      .d(htr_flit_head_s),
      .q(htr_flit_head_q));
   
   assign flit_head = fb_empty ? flit_head_in : htr_flit_head_q;
   
   



   
   wire [0:route_info_width-1] route_info_in;
   assign route_info_in = header_info_in[0:route_info_width-1];
   
   wire 		       hdr_active;
   wire 		       hdr_capture;
   generate
      if(atomic_vc_allocation)
	begin
	   assign hdr_active = flit_valid_in & flit_head_in;
	   assign hdr_capture = flit_valid_sel_head_in;
	end
      else
	begin
	   assign hdr_active = ~fb_empty | (flit_valid_in & flit_head_in);
	   assign hdr_capture = (fb_empty & flit_valid_sel_head_in) | 
				flit_sent_tail;
	end
   endgenerate
   
   wire two_plus_flits;
   assign two_plus_flits = ~fb_empty & ~fb_almost_empty;
   
   wire [0:route_info_width-1] fb_pop_next_route_info;
   assign fb_pop_next_route_info
     = fb_pop_next_header_info[0:route_info_width-1];
   
   wire [0:lar_info_width-1]   lar_info_in;
   assign lar_info_in = route_info_in[0:lar_info_width-1];
   
   wire [0:lar_info_width-1]   hdr_lar_info_s, hdr_lar_info_q;
   generate
      if(atomic_vc_allocation)
	assign hdr_lar_info_s = hdr_capture ? lar_info_in : hdr_lar_info_q;
      else
	begin
	   
	   wire [0:lar_info_width-1] fb_pop_next_lar_info;
	   assign fb_pop_next_lar_info
	     = fb_pop_next_route_info[0:lar_info_width-1];
	   
	   assign hdr_lar_info_s
	     = hdr_capture ?
	       (two_plus_flits ? fb_pop_next_lar_info : lar_info_in) :
	       hdr_lar_info_q;
	   
	end
   endgenerate
   c_dff
     #(.width(lar_info_width),
       .reset_type(reset_type))
   hdr_lar_infoq
     (.clk(clk),
      .reset(1'b0),
      .active(hdr_active),
      .d(hdr_lar_info_s),
      .q(hdr_lar_info_q));
   
   wire [0:dest_info_width-1] 	     dest_info_in;
   assign dest_info_in = route_info_in[lar_info_width:
				       lar_info_width+dest_info_width-1];
   
   wire [0:dest_info_width-1] 	     hdr_dest_info_s, hdr_dest_info_q;
   generate
      if(atomic_vc_allocation)
	assign hdr_dest_info_s = hdr_capture ? dest_info_in : hdr_dest_info_q;
      else
	begin
	   
	   wire [0:dest_info_width-1] fb_pop_next_dest_info;
	   assign fb_pop_next_dest_info
	     = fb_pop_next_route_info[lar_info_width:
				      lar_info_width+dest_info_width-1];
	   
	   assign hdr_dest_info_s
	     = hdr_capture ?
	       (two_plus_flits ? fb_pop_next_dest_info : dest_info_in) :
	       hdr_dest_info_q;
	   
	end
   endgenerate
   c_dff
     #(.width(dest_info_width),
       .reset_type(reset_type))
   hdr_dest_infoq
     (.clk(clk),
      .reset(1'b0),
      .active(hdr_active),
      .d(hdr_dest_info_s),
      .q(hdr_dest_info_q));
   
   



   
   wire [0:port_idx_width-1] 	      route_port_in;
   assign route_port_in = lar_info_in[0:port_idx_width-1];
   
   wire [0:num_ports-1] 	      route_in_op;
   c_decode
     #(.num_ports(num_ports))
   route_in_op_dec
     (.data_in(route_port_in),
      .data_out(route_in_op));
   
   wire [0:port_idx_width-1] 	      hdr_route_port;
   assign hdr_route_port = hdr_lar_info_q[0:port_idx_width-1];
   
   wire [0:num_ports-1] 	      hdr_route_op;
   c_decode
     #(.num_ports(num_ports))
   hdr_route_op_dec
     (.data_in(hdr_route_port),
      .data_out(hdr_route_op));
   
   wire 			      bypass_route_info;
   generate
      if(atomic_vc_allocation)
	assign bypass_route_info = flit_valid_sel_head_in;
      else
	assign bypass_route_info = fb_empty & flit_valid_sel_head_in;
   endgenerate
   
   wire [0:num_ports-1] 	      route_unmasked_op;
   assign route_unmasked_op = bypass_route_info ? route_in_op : hdr_route_op;
   
   wire [0:num_resource_classes-1]    route_unmasked_orc;
   
   generate
      
      if(num_resource_classes == 1)
	assign route_unmasked_orc = 1'b1;
      else if(num_resource_classes > 1)
	begin
	   
	   wire [0:resource_class_idx_width-1] route_rcsel_in;
	   assign route_rcsel_in
	     = lar_info_in[port_idx_width:
			   port_idx_width+resource_class_idx_width-1];
	   
	   wire [0:num_resource_classes-1]     route_in_orc;
	   c_decode
	     #(.num_ports(num_resource_classes))
	   route_in_orc_dec
	     (.data_in(route_rcsel_in),
	      .data_out(route_in_orc));
	   
	   wire [0:resource_class_idx_width-1] hdr_route_rcsel;
	   assign hdr_route_rcsel
	     = hdr_lar_info_q[port_idx_width:
				   port_idx_width+resource_class_idx_width-1];
	   
	   wire [0:num_resource_classes-1]     hdr_route_orc;
	   c_decode
	     #(.num_ports(num_resource_classes))
	   hdr_route_orc_dec
	     (.data_in(hdr_route_rcsel),
	      .data_out(hdr_route_orc));
	   
	   assign route_unmasked_orc
	     = bypass_route_info ? route_in_orc : hdr_route_orc;
	   
	end
      
   endgenerate
   
   wire [0:1] 				       rf_errors;
   rtr_route_filter
     #(.num_message_classes(num_message_classes),
       .num_resource_classes(num_resource_classes),
       .num_vcs_per_class(num_vcs_per_class),
       .num_ports(num_ports),
       .num_neighbors_per_dim(num_neighbors_per_dim),
       .num_nodes_per_router(num_nodes_per_router),
       .restrict_turns(restrict_turns),
       .connectivity(connectivity),
       .routing_type(routing_type),
       .dim_order(dim_order),
       .port_id(port_id),
       .vc_id(vc_id))
   rf
     (.clk(clk),
      .route_valid(flit_valid),
      .route_in_op(route_unmasked_op),
      .route_in_orc(route_unmasked_orc),
      .route_out_op(route_op),
      .route_out_orc(route_orc),
      .errors(rf_errors));
   
   wire 				       error_invalid_port;
   assign error_invalid_port = rf_errors[0];
   
   wire 				       error_invalid_class;
   assign error_invalid_class = rf_errors[1];
   
   



   
   wire [0:dest_info_width-1] 		       dest_info;
   assign dest_info = bypass_route_info ? dest_info_in : hdr_dest_info_q;
   
   wire [0:lar_info_width-1] 		       lar_info;
   assign lar_info = bypass_route_info ? lar_info_in : hdr_lar_info_q;
   
   wire [0:router_addr_width-1] 	       next_router_address;
   rtr_next_hop_addr
     #(.num_resource_classes(num_resource_classes),
       .num_routers_per_dim(num_routers_per_dim),
       .num_dimensions(num_dimensions),
       .num_nodes_per_router(num_nodes_per_router),
       .connectivity(connectivity),
       .routing_type(routing_type))
   nha
     (.router_address(router_address),
      .dest_info(dest_info),
      .lar_info(lar_info),
      .next_router_address(next_router_address));
   
   wire [0:num_message_classes-1] 	       sel_mc;
   c_align
     #(.in_width(1),
       .out_width(num_message_classes),
       .offset(message_class))
   sel_mc_agn
     (.data_in(1'b1),
      .dest_in({num_message_classes{1'b0}}),
      .data_out(sel_mc));
   
   wire [0:num_ports-1] 		       next_route_op;
   wire [0:num_resource_classes-1] 	       next_route_orc;
   rtr_routing_logic
     #(.num_message_classes(num_message_classes),
       .num_resource_classes(num_resource_classes),
       .num_routers_per_dim(num_routers_per_dim),
       .num_dimensions(num_dimensions),
       .num_nodes_per_router(num_nodes_per_router),
       .connectivity(connectivity),
       .routing_type(routing_type),
       .dim_order(dim_order))
   rtl
     (.router_address(next_router_address),
      .sel_mc(sel_mc),
      .sel_irc(route_orc),
      .dest_info(dest_info),
      .route_op(next_route_op),
      .route_orc(next_route_orc));
   
   wire [0:port_idx_width-1] 		       next_route_port;
   c_encode
     #(.num_ports(num_ports))
   next_route_port_enc
     (.data_in(next_route_op),
      .data_out(next_route_port));
   
   assign next_lar_info[0:port_idx_width-1] = next_route_port;
   
   generate
      
      if(num_resource_classes > 1)
	begin
	   
	   wire [0:resource_class_idx_width-1] next_route_rcsel;
	   c_encode
	     #(.num_ports(num_resource_classes))
	   next_route_rcsel_enc
	     (.data_in(next_route_orc),
	      .data_out(next_route_rcsel));
	   
	   assign next_lar_info[port_idx_width:
				port_idx_width+resource_class_idx_width-1]
	     = next_route_rcsel;
	   
	end
      
   endgenerate
   
   



   
   wire 				       cred_track_active;
   assign cred_track_active = pop_active | allocated;
   
   wire [0:num_vcs-1] 			       almost_full_ovc;
   c_select_1ofn
     #(.num_ports(num_ports),
       .width(num_vcs))
   almost_full_ovc_sel
     (.select(route_op),
      .data_in(almost_full_op_ovc),
      .data_out(almost_full_ovc));
   
   wire [0:num_vcs-1] 			       full_ovc;
   c_select_1ofn
     #(.num_ports(num_ports),
       .width(num_vcs))
   full_ovc_sel
     (.select(route_op),
      .data_in(full_op_ovc),
      .data_out(full_ovc));
   
   wire 				       reduce;
   
   generate
      
      if(fb_mgmt_type == `FB_MGMT_TYPE_STATIC)
	assign reduce = flit_sent;
      else
	begin
	   
	   c_select_1ofn
	     #(.num_ports(num_ports),
	       .width(1))
	   reduce_sel
	     (.select(route_op),
	      .data_in(sw_gnt_op),
	      .data_out(reduce));
	   
	end
      
   endgenerate
   
   wire [0:num_vcs-1] 			       next_free_ovc;
   assign next_free_ovc = ~full_ovc & ~(almost_full_ovc & {num_vcs{reduce}});
   
   wire [0:num_vcs_per_message_class-1]        next_free_orc_ocvc;
   assign next_free_orc_ocvc
     = next_free_ovc[message_class*num_vcs_per_message_class:
		     (message_class+1)*num_vcs_per_message_class-1];
   
   wire 				       free_nonspec_muxed;
   c_select_1ofn
     #(.num_ports(num_vcs_per_message_class),
       .width(1))
   free_nonspec_muxed_sel
     (.select(vc_allocated_next_orc_ocvc),
      .data_in(next_free_orc_ocvc),
      .data_out(free_nonspec_muxed));
   
   wire 				       free_nonspec_s, free_nonspec_q;
   assign free_nonspec_s = free_nonspec_muxed;
   c_dff
     #(.width(1),
       .reset_value(1'b1),
       .reset_type(reset_type))
   free_nonspecq
     (.clk(clk),
      .reset(1'b0),
      .active(cred_track_active),
      .d(free_nonspec_s),
      .q(free_nonspec_q));
   
   assign free_nonspec = free_nonspec_q;
   
   wire [0:num_vcs-1] 			       free_spec_ovc;
   assign free_spec_ovc = ~full_ovc;
   
   c_select_1ofn
     #(.num_ports(num_vcs),
       .width(1))
   free_spec_sel
     (.select(vc_sel_ovc),
      .data_in(free_spec_ovc),
      .data_out(free_spec));
   
   wire 				       sw_gnt_sel;
   assign sw_gnt_sel = sw_gnt & sw_sel;
   
   generate
      
      if(sw_alloc_spec)
	begin
	   if(elig_mask == `ELIG_MASK_NONE)
	     assign flit_sent = sw_gnt_sel & ((vc_gnt & free_spec) | allocated);
	   else
	     assign flit_sent = sw_gnt_sel & (vc_gnt | allocated);
	end
      else
	assign flit_sent = sw_gnt_sel;
      
   endgenerate
   
   



   
   wire ftc_active;
   assign ftc_active = flit_valid_in;
   
   wire error_invalid_flit_type;
   rtr_flit_type_check
     #(.reset_type(reset_type))
   ftc
     (.clk(clk),
      .reset(reset),
      .active(ftc_active),
      .flit_valid(flit_valid_sel_in),
      .flit_head(flit_head_in),
      .flit_tail(flit_tail_in),
      .error(error_invalid_flit_type));
   
   assign errors[0] = error_invalid_port;
   assign errors[1] = error_invalid_class;
   assign errors[2] = error_invalid_flit_type;
   
endmodule
module vcr_ivc_ctrl
  (clk, reset, router_address, flit_valid_in, flit_head_in, flit_tail_in, 
   flit_sel_in, header_info_in, fb_pop_tail, fb_pop_next_header_info, 
   almost_full_op_ovc, full_op_ovc, route_op, route_orc, vc_gnt, vc_sel_ovc, 
   sw_gnt, sw_sel, sw_gnt_op, flit_valid, flit_head, flit_tail, next_lar_info, 
   fb_almost_empty, fb_empty, allocated, free_nonspec, free_spec, errors);

   
`include "c_functions.v"
`include "c_constants.v"
`include "rtr_constants.v"
`include "vcr_constants.v"
   

   parameter num_message_classes = 2;
   

   parameter num_resource_classes = 2;
   

   localparam resource_class_idx_width = clogb(num_resource_classes);
   

   localparam num_packet_classes = num_message_classes * num_resource_classes;
   

   parameter num_vcs_per_class = 1;
   

   localparam num_vcs_per_message_class
     = num_resource_classes * num_vcs_per_class;
   

   localparam num_vcs = num_packet_classes * num_vcs_per_class;
   

   localparam vc_idx_width = clogb(num_vcs);
   

   parameter num_routers_per_dim = 4;
   

   parameter num_dimensions = 2;
   

   parameter num_nodes_per_router = 1;
   

   parameter connectivity = `CONNECTIVITY_LINE;
   

   localparam num_neighbors_per_dim
     = ((connectivity == `CONNECTIVITY_LINE) ||
	(connectivity == `CONNECTIVITY_RING)) ?
       2 :
       (connectivity == `CONNECTIVITY_FULL) ?
       (num_routers_per_dim - 1) :
       -1;
   

   localparam num_ports
     = num_dimensions * num_neighbors_per_dim + num_nodes_per_router;
   

   localparam port_idx_width = clogb(num_ports);
   

   parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;
   


   parameter max_payload_length = 4;
   


   parameter min_payload_length = 1;
   

   localparam payload_length_width
     = clogb(max_payload_length-min_payload_length+1);
   

   localparam flit_ctr_width = clogb(max_payload_length);
   

   localparam dim_addr_width = clogb(num_routers_per_dim);
   

   localparam router_addr_width = num_dimensions * dim_addr_width;
   

   localparam node_addr_width = clogb(num_nodes_per_router);
   

   localparam addr_width = router_addr_width + node_addr_width;
   

   localparam flit_ctrl_width
     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? 
       (1 + vc_idx_width + 1 + 1) : 
       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? 
       (1 + vc_idx_width + 1) : 
       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? 
       (1 + vc_idx_width + 1) : 
       -1;
   



   parameter restrict_turns = 1;
   

   localparam lar_info_width = port_idx_width + resource_class_idx_width;
   

   parameter routing_type = `ROUTING_TYPE_PHASED_DOR;
   

   localparam dest_info_width
     = (routing_type == `ROUTING_TYPE_PHASED_DOR) ? 
       (num_resource_classes * router_addr_width + node_addr_width) : 
       -1;
   

   localparam route_info_width = lar_info_width + dest_info_width + 1;
   

   localparam header_info_width
     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? 
       route_info_width : 
       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? 
       route_info_width : 
       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? 
       (route_info_width + payload_length_width) : 
       -1;
   

   parameter dim_order = `DIM_ORDER_ASCENDING;
   

   parameter elig_mask = `ELIG_MASK_NONE;
   

   localparam atomic_vc_allocation = (elig_mask == `ELIG_MASK_USED);
   

   parameter sw_alloc_spec = 1;
   

   parameter fb_mgmt_type = `FB_MGMT_TYPE_STATIC;
   

   parameter explicit_pipeline_register = 0;
   

   parameter vc_id = 0;
   

   localparam message_class
     = (vc_id / num_vcs_per_message_class) % num_message_classes;
   

   localparam resource_class
     = (vc_id / num_vcs_per_class) % num_resource_classes;
   

   parameter port_id = 0;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   input clk;
   input reset;
   

   input [0:router_addr_width-1] router_address;
   

   input 			 flit_valid_in;
   

   input 			 flit_head_in;
   

   input 			 flit_tail_in;
   

   input 			 flit_sel_in;
   


   input [0:header_info_width-1] header_info_in;
   

   input 			 fb_pop_tail;
   


   input [0:header_info_width-1] fb_pop_next_header_info;
   

   input [0:num_ports*num_vcs-1]   almost_full_op_ovc;
   

   input [0:num_ports*num_vcs-1]   full_op_ovc;
   

   output [0:num_ports-1] 	   route_op;
   wire [0:num_ports-1] 	   route_op;
   

   output [0:num_resource_classes-1] route_orc;
   wire [0:num_resource_classes-1]   route_orc;
   

   input 			     vc_gnt;
   

   input [0:num_vcs-1] 		     vc_sel_ovc;
   

   input 			     sw_gnt;
   

   input 			     sw_sel;
   

   input [0:num_ports-1] 	     sw_gnt_op;
   

   output 			     flit_valid;
   wire 			     flit_valid;
   

   output 			     flit_head;
   wire 			     flit_head;
   

   output 			     flit_tail;
   wire 			     flit_tail;
   


   output [0:lar_info_width-1] 	     next_lar_info;
   wire [0:lar_info_width-1] 	     next_lar_info;
   

   input 			     fb_almost_empty;
   

   input 			     fb_empty;
   

   output 			     allocated;
   wire 			     allocated;
   

   output 			     free_nonspec;
   wire 			     free_nonspec;
   

   output 			     free_spec;
   wire 			     free_spec;
   

   output [0:2] 		     errors;
   wire [0:2] 			     errors;
   
   



   
   wire 			     flit_valid_sel_in;
   assign flit_valid_sel_in = flit_valid_in & flit_sel_in;
   
   assign flit_valid = flit_valid_sel_in | ~fb_empty;
   
   wire 			     pop_active;
   assign pop_active = flit_valid_in | ~fb_empty;
   
   wire 			     flit_sent;
   
   wire 			     flit_sent_tail;
   assign flit_sent_tail = flit_sent & flit_tail;
   
   wire 			     flit_valid_sel_head_in;
   assign flit_valid_sel_head_in = flit_valid_sel_in & flit_head_in;
   
   wire 			     vc_allocated_s, vc_allocated_q;
   generate
      if(atomic_vc_allocation)
	begin
	   assign vc_allocated_s
	     = (vc_allocated_q & ~flit_valid_sel_head_in) | vc_gnt;
	   assign allocated = vc_allocated_q & ~flit_valid_sel_head_in;
	end
      else
	begin
	   assign vc_allocated_s = (vc_allocated_q | vc_gnt) & ~flit_sent_tail;
	   assign allocated = vc_allocated_q;
	end
   endgenerate
   c_dff
     #(.width(1),
       .reset_type(reset_type))
   vc_allocatedq
     (.clk(clk),
      .reset(reset),
      .active(pop_active),
      .d(vc_allocated_s),
      .q(vc_allocated_q));
   
   wire [0:num_vcs_per_message_class-1] vc_allocated_next_orc_ocvc;
   
   generate
      
      if(num_vcs_per_message_class == 1)
	assign vc_allocated_next_orc_ocvc = 1'b1;
      else if(num_vcs_per_message_class > 1)
	begin
	   
	   wire [0:num_vcs_per_message_class-1] vc_sel_orc_ocvc;
	   assign vc_sel_orc_ocvc
	     = vc_sel_ovc[message_class*num_vcs_per_message_class:
	                  (message_class+1)*num_vcs_per_message_class-1];
	   
	   wire [0:num_vcs_per_message_class-1] vc_allocated_orc_ocvc_q;
	   
	   assign vc_allocated_next_orc_ocvc
	     = allocated ? vc_allocated_orc_ocvc_q : vc_sel_orc_ocvc;
	   
	   wire [0:num_vcs_per_message_class-1] vc_allocated_orc_ocvc_s;
	   assign vc_allocated_orc_ocvc_s = vc_allocated_next_orc_ocvc;
	   c_dff
	     #(.width(num_vcs_per_message_class),
	       .reset_type(reset_type))
	   vc_allocated_orc_ocvcq
	     (.clk(clk),
	      .reset(1'b0),
	      .active(pop_active),
	      .d(vc_allocated_orc_ocvc_s),
	      .q(vc_allocated_orc_ocvc_q));
	   
	end
      
   endgenerate
   
   wire [0:num_vcs-1] vc_allocated_next_ovc;
   c_align
     #(.in_width(num_vcs_per_message_class),
       .out_width(num_vcs),
       .offset(message_class*num_vcs_per_message_class))
   vc_allocated_next_ovc_agn
     (.data_in(vc_allocated_next_orc_ocvc),
      .dest_in({num_vcs{1'b0}}),
      .data_out(vc_allocated_next_ovc));
   
   



   
   assign flit_tail = fb_empty ? flit_tail_in : fb_pop_tail;
   
   wire 	      htr_flit_head_s, htr_flit_head_q;
   assign htr_flit_head_s = flit_sent ? flit_tail : htr_flit_head_q;
   c_dff
     #(.width(1),
       .reset_type(reset_type),
       .reset_value(1'b1))
   htr_flit_headq
     (.clk(clk),
      .reset(reset),
      .active(pop_active),
      .d(htr_flit_head_s),
      .q(htr_flit_head_q));
   
   assign flit_head = fb_empty ? flit_head_in : htr_flit_head_q;
   
   



   
   wire [0:route_info_width-1] route_info_in;
   assign route_info_in = header_info_in[0:route_info_width-1];
   
   wire 		       hdr_active;
   wire 		       hdr_capture;
   generate
      if(atomic_vc_allocation)
	begin
	   assign hdr_active = flit_valid_in & flit_head_in;
	   assign hdr_capture = flit_valid_sel_head_in;
	end
      else
	begin
	   assign hdr_active = ~fb_empty | (flit_valid_in & flit_head_in);
	   assign hdr_capture = (fb_empty & flit_valid_sel_head_in) | 
				flit_sent_tail;
	end
   endgenerate
   
   wire two_plus_flits;
   assign two_plus_flits = ~fb_empty & ~fb_almost_empty;
   
   wire [0:route_info_width-1] fb_pop_next_route_info;
   assign fb_pop_next_route_info
     = fb_pop_next_header_info[0:route_info_width-1];
   
   wire [0:lar_info_width-1]   lar_info_in;
   assign lar_info_in = route_info_in[0:lar_info_width-1];
   
   wire [0:lar_info_width-1]   hdr_lar_info_s, hdr_lar_info_q;
   generate
      if(atomic_vc_allocation)
	assign hdr_lar_info_s = hdr_capture ? lar_info_in : hdr_lar_info_q;
      else
	begin
	   
	   wire [0:lar_info_width-1] fb_pop_next_lar_info;
	   assign fb_pop_next_lar_info
	     = fb_pop_next_route_info[0:lar_info_width-1];
	   
	   assign hdr_lar_info_s
	     = hdr_capture ?
	       (two_plus_flits ? fb_pop_next_lar_info : lar_info_in) :
	       hdr_lar_info_q;
	   
	end
   endgenerate
   c_dff
     #(.width(lar_info_width),
       .reset_type(reset_type))
   hdr_lar_infoq
     (.clk(clk),
      .reset(1'b0),
      .active(hdr_active),
      .d(hdr_lar_info_s),
      .q(hdr_lar_info_q));
   
   wire [0:dest_info_width-1] 	     dest_info_in;
   assign dest_info_in = route_info_in[lar_info_width:
				       lar_info_width+dest_info_width-1];
   
   wire [0:dest_info_width-1] 	     hdr_dest_info_s, hdr_dest_info_q;
   generate
      if(atomic_vc_allocation)
	assign hdr_dest_info_s = hdr_capture ? dest_info_in : hdr_dest_info_q;
      else
	begin
	   
	   wire [0:dest_info_width-1] fb_pop_next_dest_info;
	   assign fb_pop_next_dest_info
	     = fb_pop_next_route_info[lar_info_width:
				      lar_info_width+dest_info_width-1];
	   
	   assign hdr_dest_info_s
	     = hdr_capture ?
	       (two_plus_flits ? fb_pop_next_dest_info : dest_info_in) :
	       hdr_dest_info_q;
	   
	end
   endgenerate
   c_dff
     #(.width(dest_info_width),
       .reset_type(reset_type))
   hdr_dest_infoq
     (.clk(clk),
      .reset(1'b0),
      .active(hdr_active),
      .d(hdr_dest_info_s),
      .q(hdr_dest_info_q));
   
   



   
   wire [0:port_idx_width-1] 	      route_port_in;
   assign route_port_in = lar_info_in[0:port_idx_width-1];
   
   wire [0:num_ports-1] 	      route_in_op;
   c_decode
     #(.num_ports(num_ports))
   route_in_op_dec
     (.data_in(route_port_in),
      .data_out(route_in_op));
   
   wire [0:port_idx_width-1] 	      hdr_route_port;
   assign hdr_route_port = hdr_lar_info_q[0:port_idx_width-1];
   
   wire [0:num_ports-1] 	      hdr_route_op;
   c_decode
     #(.num_ports(num_ports))
   hdr_route_op_dec
     (.data_in(hdr_route_port),
      .data_out(hdr_route_op));
   
   wire 			      bypass_route_info;
   generate
      if(atomic_vc_allocation)
	assign bypass_route_info = flit_valid_sel_head_in;
      else
	assign bypass_route_info = fb_empty & flit_valid_sel_head_in;
   endgenerate
   
   wire [0:num_ports-1] 	      route_unmasked_op;
   assign route_unmasked_op = bypass_route_info ? route_in_op : hdr_route_op;
   
   wire [0:num_resource_classes-1]    route_unmasked_orc;
   
   generate
      
      if(num_resource_classes == 1)
	assign route_unmasked_orc = 1'b1;
      else if(num_resource_classes > 1)
	begin
	   
	   wire [0:resource_class_idx_width-1] route_rcsel_in;
	   assign route_rcsel_in
	     = lar_info_in[port_idx_width:
			   port_idx_width+resource_class_idx_width-1];
	   
	   wire [0:num_resource_classes-1]     route_in_orc;
	   c_decode
	     #(.num_ports(num_resource_classes))
	   route_in_orc_dec
	     (.data_in(route_rcsel_in),
	      .data_out(route_in_orc));
	   
	   wire [0:resource_class_idx_width-1] hdr_route_rcsel;
	   assign hdr_route_rcsel
	     = hdr_lar_info_q[port_idx_width:
				   port_idx_width+resource_class_idx_width-1];
	   
	   wire [0:num_resource_classes-1]     hdr_route_orc;
	   c_decode
	     #(.num_ports(num_resource_classes))
	   hdr_route_orc_dec
	     (.data_in(hdr_route_rcsel),
	      .data_out(hdr_route_orc));
	   
	   assign route_unmasked_orc
	     = bypass_route_info ? route_in_orc : hdr_route_orc;
	   
	end
      
   endgenerate
   
   wire [0:1] 				       rf_errors;
   rtr_route_filter
     #(.num_message_classes(num_message_classes),
       .num_resource_classes(num_resource_classes),
       .num_vcs_per_class(num_vcs_per_class),
       .num_ports(num_ports),
       .num_neighbors_per_dim(num_neighbors_per_dim),
       .num_nodes_per_router(num_nodes_per_router),
       .restrict_turns(restrict_turns),
       .connectivity(connectivity),
       .routing_type(routing_type),
       .dim_order(dim_order),
       .port_id(port_id),
       .vc_id(vc_id))
   rf
     (.clk(clk),
      .route_valid(flit_valid),
      .route_in_op(route_unmasked_op),
      .route_in_orc(route_unmasked_orc),
      .route_out_op(route_op),
      .route_out_orc(route_orc),
      .errors(rf_errors));
   
   wire 				       error_invalid_port;
   assign error_invalid_port = rf_errors[0];
   
   wire 				       error_invalid_class;
   assign error_invalid_class = rf_errors[1];
   
   



   
   wire [0:dest_info_width-1] 		       dest_info;
   assign dest_info = bypass_route_info ? dest_info_in : hdr_dest_info_q;
   
   wire [0:lar_info_width-1] 		       lar_info;
   assign lar_info = bypass_route_info ? lar_info_in : hdr_lar_info_q;
   
   wire [0:router_addr_width-1] 	       next_router_address;
   rtr_next_hop_addr
     #(.num_resource_classes(num_resource_classes),
       .num_routers_per_dim(num_routers_per_dim),
       .num_dimensions(num_dimensions),
       .num_nodes_per_router(num_nodes_per_router),
       .connectivity(connectivity),
       .routing_type(routing_type))
   nha
     (.router_address(router_address),
      .dest_info(dest_info),
      .lar_info(lar_info),
      .next_router_address(next_router_address));
   
   wire [0:num_message_classes-1] 	       sel_mc;
   c_align
     #(.in_width(1),
       .out_width(num_message_classes),
       .offset(message_class))
   sel_mc_agn
     (.data_in(1'b1),
      .dest_in({num_message_classes{1'b0}}),
      .data_out(sel_mc));
   
   wire [0:num_ports-1] 		       next_route_op;
   wire [0:num_resource_classes-1] 	       next_route_orc;
   rtr_routing_logic
     #(.num_message_classes(num_message_classes),
       .num_resource_classes(num_resource_classes),
       .num_routers_per_dim(num_routers_per_dim),
       .num_dimensions(num_dimensions),
       .num_nodes_per_router(num_nodes_per_router),
       .connectivity(connectivity),
       .routing_type(routing_type),
       .dim_order(dim_order))
   rtl
     (.router_address(next_router_address),
      .sel_mc(sel_mc),
      .sel_irc(route_orc),
      .dest_info(dest_info),
      .route_op(next_route_op),
      .route_orc(next_route_orc));
   
   wire [0:port_idx_width-1] 		       next_route_port;
   c_encode
     #(.num_ports(num_ports))
   next_route_port_enc
     (.data_in(next_route_op),
      .data_out(next_route_port));
   
   assign next_lar_info[0:port_idx_width-1] = next_route_port;
   
   generate
      
      if(num_resource_classes > 1)
	begin
	   
	   wire [0:resource_class_idx_width-1] next_route_rcsel;
	   c_encode
	     #(.num_ports(num_resource_classes))
	   next_route_rcsel_enc
	     (.data_in(next_route_orc),
	      .data_out(next_route_rcsel));
	   
	   assign next_lar_info[port_idx_width:
				port_idx_width+resource_class_idx_width-1]
	     = next_route_rcsel;
	   
	end
      
   endgenerate
   
   



   
   wire 				       cred_track_active;
   assign cred_track_active = pop_active | allocated;
   
   wire [0:num_vcs-1] 			       almost_full_ovc;
   c_select_1ofn
     #(.num_ports(num_ports),
       .width(num_vcs))
   almost_full_ovc_sel
     (.select(route_op),
      .data_in(almost_full_op_ovc),
      .data_out(almost_full_ovc));
   
   wire [0:num_vcs-1] 			       full_ovc;
   c_select_1ofn
     #(.num_ports(num_ports),
       .width(num_vcs))
   full_ovc_sel
     (.select(route_op),
      .data_in(full_op_ovc),
      .data_out(full_ovc));
   
   wire 				       reduce;
   
   generate
      
      if(fb_mgmt_type == `FB_MGMT_TYPE_STATIC)
	assign reduce = flit_sent;
      else
	begin
	   
	   c_select_1ofn
	     #(.num_ports(num_ports),
	       .width(1))
	   reduce_sel
	     (.select(route_op),
	      .data_in(sw_gnt_op),
	      .data_out(reduce));
	   
	end
      
   endgenerate
   
   wire [0:num_vcs-1] 			       next_free_ovc;
   assign next_free_ovc = ~full_ovc & ~(almost_full_ovc & {num_vcs{reduce}});
   
   wire [0:num_vcs_per_message_class-1]        next_free_orc_ocvc;
   assign next_free_orc_ocvc
     = next_free_ovc[message_class*num_vcs_per_message_class:
		     (message_class+1)*num_vcs_per_message_class-1];
   
   wire 				       free_nonspec_muxed;
   c_select_1ofn
     #(.num_ports(num_vcs_per_message_class),
       .width(1))
   free_nonspec_muxed_sel
     (.select(vc_allocated_next_orc_ocvc),
      .data_in(next_free_orc_ocvc),
      .data_out(free_nonspec_muxed));
   
   wire 				       free_nonspec_s, free_nonspec_q;
   assign free_nonspec_s = free_nonspec_muxed;
   c_dff
     #(.width(1),
       .reset_value(1'b1),
       .reset_type(reset_type))
   free_nonspecq
     (.clk(clk),
      .reset(1'b0),
      .active(cred_track_active),
      .d(free_nonspec_s),
      .q(free_nonspec_q));
   
   assign free_nonspec = free_nonspec_q;
   
   wire [0:num_vcs-1] 			       free_spec_ovc;
   assign free_spec_ovc = ~full_ovc;
   
   c_select_1ofn
     #(.num_ports(num_vcs),
       .width(1))
   free_spec_sel
     (.select(vc_sel_ovc),
      .data_in(free_spec_ovc),
      .data_out(free_spec));
   
   wire 				       sw_gnt_sel;
   assign sw_gnt_sel = sw_gnt & sw_sel;
   
   generate
      
      if(sw_alloc_spec)
	begin
	   if(elig_mask == `ELIG_MASK_NONE)
	     assign flit_sent = sw_gnt_sel & ((vc_gnt & free_spec) | allocated);
	   else
	     assign flit_sent = sw_gnt_sel & (vc_gnt | allocated);
	end
      else
	assign flit_sent = sw_gnt_sel;
      
   endgenerate
   
   



   
   wire ftc_active;
   assign ftc_active = flit_valid_in;
   
   wire error_invalid_flit_type;
   rtr_flit_type_check
     #(.reset_type(reset_type))
   ftc
     (.clk(clk),
      .reset(reset),
      .active(ftc_active),
      .flit_valid(flit_valid_sel_in),
      .flit_head(flit_head_in),
      .flit_tail(flit_tail_in),
      .error(error_invalid_flit_type));
   
   assign errors[0] = error_invalid_port;
   assign errors[1] = error_invalid_class;
   assign errors[2] = error_invalid_flit_type;
   
endmodule