data/full_repos/permissive/479308240/datapath.v
1: b"%Error: data/full_repos/permissive/479308240/datapath.v:43: Cannot find file containing module: 'demux'\ndemux U1(AYEA,BEEA,PortOUT,seldst,clk,buswires,dsten);\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/479308240,data/full_repos/permissive/479308240/demux\n             data/full_repos/permissive/479308240,data/full_repos/permissive/479308240/demux.v\n             data/full_repos/permissive/479308240,data/full_repos/permissive/479308240/demux.sv\n             demux\n             demux.v\n             demux.sv\n             obj_dir/demux\n             obj_dir/demux.v\n             obj_dir/demux.sv\n%Error: data/full_repos/permissive/479308240/datapath.v:44: Cannot find file containing module: 'sourcemux'\nsourcemux U2(AYEQ,BEEQ,INQ,selsrc,clk,buswires,srcen);\n^~~~~~~~~\n%Error: data/full_repos/permissive/479308240/datapath.v:45: Cannot find file containing module: 'regbasic'\nregbasic U3(INQ,PortIN,rst,clk);\n^~~~~~~~\n%Error: data/full_repos/permissive/479308240/datapath.v:46: Cannot find file containing module: 'regbasic'\nregbasic U4(AYEQ,AYEA,rst,clk);\n^~~~~~~~\n%Error: data/full_repos/permissive/479308240/datapath.v:47: Cannot find file containing module: 'regbasic'\nregbasic U5(BEEQ,BEEA,rst,clk);\n^~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module datapath(
    input wire [7:0] PortIN,
    output wire [7:0] PortOUT,
    input wire [2:0] seldst,
    input wire [2:0] selsrc,
    input wire dsten,
    input wire srcen,
    input wire clk,
    input wire rst
    );

wire [7:0] INA;
wire [7:0] INQ;
wire [7:0] OUTA;
wire [7:0] OUTQ;
wire [7:0] AYEA;
wire [7:0] AYEQ;
wire [7:0] BEEA;
wire [7:0] BEEQ;
wire [7:0] nulling;
wire [7:0] buswires;  

demux U1(AYEA,BEEA,PortOUT,seldst,clk,buswires,dsten);
sourcemux U2(AYEQ,BEEQ,INQ,selsrc,clk,buswires,srcen);
regbasic U3(INQ,PortIN,rst,clk);
regbasic U4(AYEQ,AYEA,rst,clk);
regbasic U5(BEEQ,BEEA,rst,clk);
        
endmodule
module datapath(
    input wire [7:0] PortIN,
    output wire [7:0] PortOUT,
    input wire [2:0] seldst,
    input wire [2:0] selsrc,
    input wire dsten,
    input wire srcen,
    input wire clk,
    input wire rst
    );


wire [7:0] INA;
wire [7:0] INQ;
wire [7:0] OUTA;
wire [7:0] OUTQ;
wire [7:0] AYEA;
wire [7:0] AYEQ;
wire [7:0] BEEA;
wire [7:0] BEEQ;
wire [7:0] nulling;
wire [7:0] buswires;  

demux U1(AYEA,BEEA,PortOUT,seldst,clk,buswires,dsten);
sourcemux U2(AYEQ,BEEQ,INQ,selsrc,clk,buswires,srcen);
regbasic U3(INQ,PortIN,rst,clk);
regbasic U4(AYEQ,AYEA,rst,clk);
regbasic U5(BEEQ,BEEA,rst,clk);
        
endmodule