data/full_repos/permissive/482470447/verilog/adder8_8.v
1: b"%Error: data/full_repos/permissive/482470447/verilog/adder8_8.v:5: Cannot find file containing module: 'blockSize8'\n blockSize8 b0(a[7:0],b[7:0],1'b0,sum[7:0],c0);\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/482470447/verilog,data/full_repos/permissive/482470447/blockSize8\n             data/full_repos/permissive/482470447/verilog,data/full_repos/permissive/482470447/blockSize8.v\n             data/full_repos/permissive/482470447/verilog,data/full_repos/permissive/482470447/blockSize8.sv\n             blockSize8\n             blockSize8.v\n             blockSize8.sv\n             obj_dir/blockSize8\n             obj_dir/blockSize8.v\n             obj_dir/blockSize8.sv\n%Error: Exiting due to 1 error(s)\n"
module adder8_8(a,b,sum);
	input [7:0]a,b;
	output [8:0] sum;
	wire c0;
	blockSize8 b0(a[7:0],b[7:0],1'b0,sum[7:0],c0);
	assign sum[8] = c0;
endmodule
module adder8_8(a,b,sum);

	input [7:0]a,b;
	output [8:0] sum;
	wire c0;
	blockSize8 b0(a[7:0],b[7:0],1'b0,sum[7:0],c0);
	assign sum[8] = c0;
endmodule