data/full_repos/permissive/441359809/src/yosys/tests/simple/generate.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/tests/simple/generate.v:43: Multiple top level modules\n                                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                            : ... Top module \'gen_test1\'\nmodule gen_test1(clk, a, b, y);\n       ^~~~~~~~~\n                                                                                            : ... Top module \'gen_test2\'\nmodule gen_test2(clk, a, b, y);\n       ^~~~~~~~~\n                                                                                            : ... Top module \'gen_test3\'\nmodule gen_test3(a, b, sel, y, z);\n       ^~~~~~~~~\n                                                                                            : ... Top module \'gen_test4\'\nmodule gen_test4(a, b);\n       ^~~~~~~~~\n                                                                                            : ... Top module \'gen_test5\'\nmodule gen_test5(input_bits, out);\n       ^~~~~~~~~\n                                                                                            : ... Top module \'gen_test6\'\nmodule gen_test6(output [3:0] o);\n       ^~~~~~~~~\n                                                                                            : ... Top module \'gen_test7\'\nmodule gen_test7;\n       ^~~~~~~~~\n                                                                                            : ... Top module \'gen_test8\'\nmodule gen_test8;\n       ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/generate.v:177: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'x\' generates 32 bits.\n                                                                                          : ... In instance gen_test7\n    out1 = x;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/generate.v:178: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'x\' generates 32 bits.\n                                                                                          : ... In instance gen_test7\n    sub_out1 = x;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/generate.v:183: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'x\' generates 32 bits.\n                                                                                          : ... In instance gen_test7\n    out2 = x;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/generate.v:184: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'x\' generates 32 bits.\n                                                                                          : ... In instance gen_test7\n    sub_out2 = x;\n             ^\n%Error: Exiting due to 5 warning(s)\n'
module gen_test7;
	reg [2:0] out1;
	reg [2:0] out2;
	wire [2:0] out3;
	generate
		begin : cond
			reg [2:0] sub_out1;
			reg [2:0] sub_out2;
			wire [2:0] sub_out3;
			initial begin : init
				reg signed [31:0] x;
				x = 2 ** 2;
				out1 = x;
				sub_out1 = x;
			end
			always @* begin : proc
				reg signed [31:0] x;
				x = 2 ** 1;
				out2 = x;
				sub_out2 = x;
			end
			genvar x;
			for (x = 0; x < 3; x = x + 1) begin
				assign out3[x] = 1;
				assign sub_out3[x] = 1;
			end
		end
	endgenerate


`ifdef VERIFY
	assert property (out1 == 4);
	assert property (out2 == 2);
	assert property (out3 == 7);
	assert property (cond.sub_out1 == 4);
	assert property (cond.sub_out2 == 2);
	assert property (cond.sub_out3 == 7);
`endif
endmodule
module gen_test7;

	reg [2:0] out1;
	reg [2:0] out2;
	wire [2:0] out3;
	generate
		begin : cond
			reg [2:0] sub_out1;
			reg [2:0] sub_out2;
			wire [2:0] sub_out3;
			initial begin : init
				reg signed [31:0] x;
				x = 2 ** 2;
				out1 = x;
				sub_out1 = x;
			end
			always @* begin : proc
				reg signed [31:0] x;
				x = 2 ** 1;
				out2 = x;
				sub_out2 = x;
			end
			genvar x;
			for (x = 0; x < 3; x = x + 1) begin
				assign out3[x] = 1;
				assign sub_out3[x] = 1;
			end
		end
	endgenerate


`ifdef VERIFY
	assert property (out1 == 4);
	assert property (out2 == 2);
	assert property (out3 == 7);
	assert property (cond.sub_out1 == 4);
	assert property (cond.sub_out2 == 2);
	assert property (cond.sub_out3 == 7);
`endif
endmodule