data/full_repos/permissive/528509847/src/alu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/528509847/src/alu.v:27: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'alu_result\' generates 32 bits.\n                                                                 : ... In instance alu\n    assign zero = (alu_result) ? 1\'b0 : 1\'b1;  \n                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/528509847/src/alu.v:41: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SHIFTRS generates 33 bits.\n                                                                 : ... In instance alu\n            5\'d8:   alu_result = $signed({1\'b0, src_a}) >>> src_b[4:0];                     \n                               ^\n%Warning-WIDTH: data/full_repos/permissive/528509847/src/alu.v:42: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SHIFTRS generates 33 bits.\n                                                                 : ... In instance alu\n            5\'d9:   alu_result = $signed({src_a[31], src_a}) >>> src_b[4:0];                \n                               ^\n%Error: Exiting due to 3 warning(s)\n'
module alu (
    input wire [31:0] src_a, src_b,
    input wire [4:0] alu_control,
    output reg [31:0] alu_result,
    output wire zero
    );

    assign zero = (alu_result) ? 1'b0 : 1'b1;
	

    always @(*) begin
        case (alu_control)

            `ALU_CONTROL_ADD:   alu_result = src_a + src_b;
            `ALU_CONTROL_SUB:   alu_result = src_a - src_b;
            `ALU_CONTROL_SLT:   alu_result = ($signed(src_a) < $signed(src_b)) ? 32'b1 : 32'b0 ;
            `ALU_CONTROL_SLTU:  alu_result = (src_a < src_b) ? 32'b1 : 32'b0;
            `ALU_CONTROL_XOR:   alu_result = src_a ^ src_b;
            `ALU_CONTROL_OR:    alu_result = src_a | src_b;
            `ALU_CONTROL_AND:   alu_result = src_a & src_b;
            `ALU_CONTROL_SLL:   alu_result = src_a << src_b[4:0];
            `ALU_CONTROL_SRL:   alu_result = $signed({1'b0, src_a}) >>> src_b[4:0];
            `ALU_CONTROL_SRA:   alu_result = $signed({src_a[31], src_a}) >>> src_b[4:0];
            default:            alu_result = 32'b0;
        endcase
    end

















endmodule
module alu (
    input wire [31:0] src_a, src_b,
    input wire [4:0] alu_control,
    output reg [31:0] alu_result,
    output wire zero
    );


    assign zero = (alu_result) ? 1'b0 : 1'b1;
	

    always @(*) begin
        case (alu_control)

            `ALU_CONTROL_ADD:   alu_result = src_a + src_b;
            `ALU_CONTROL_SUB:   alu_result = src_a - src_b;
            `ALU_CONTROL_SLT:   alu_result = ($signed(src_a) < $signed(src_b)) ? 32'b1 : 32'b0 ;
            `ALU_CONTROL_SLTU:  alu_result = (src_a < src_b) ? 32'b1 : 32'b0;
            `ALU_CONTROL_XOR:   alu_result = src_a ^ src_b;
            `ALU_CONTROL_OR:    alu_result = src_a | src_b;
            `ALU_CONTROL_AND:   alu_result = src_a & src_b;
            `ALU_CONTROL_SLL:   alu_result = src_a << src_b[4:0];
            `ALU_CONTROL_SRL:   alu_result = $signed({1'b0, src_a}) >>> src_b[4:0];
            `ALU_CONTROL_SRA:   alu_result = $signed({src_a[31], src_a}) >>> src_b[4:0];
            default:            alu_result = 32'b0;
        endcase
    end

















endmodule