data/full_repos/permissive/469669161/verilog/rtl/buyruk_bellegi_sram.v
1: b"%Error: data/full_repos/permissive/469669161/verilog/rtl/buyruk_bellegi_sram.v:20: Define or directive not defined: '`BB_ADRES_BIT'\n    input           [`BB_ADRES_BIT-1:0]             addra                   ,\n                     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/buyruk_bellegi_sram.v:32: Define or directive not defined: '`BB_ADRES_BIT'\n    output          [`BB_ADRES_BIT-1:0]             addr0                   ,\n                     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/469669161/verilog/rtl/buyruk_bellegi_sram.v:37: Define or directive not defined: '`BB_ADRES_BIT'\n    output          [`BB_ADRES_BIT-1:0]             addr1                   ,\n                     ^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module buyruk_bellegi_sram
(
    input           [`BB_ADRES_BIT-1:0]             addra                   ,
    input                                           clka                    ,
    input           [31:0]                          dina                    ,
    input                                           ena                     ,
    input           [3:0]                           wea                     ,
                
    output          [31:0]                          douta                   ,


    output                                          csb0                    ,
    output                                          web0                    ,
    output          [3:0]                           wmask0                  ,
    output          [`BB_ADRES_BIT-1:0]             addr0                   ,
    output          [31:0]                          din0                    ,
    input           [31:0]                          dout0                   ,

    output                                          csb1                    ,
    output          [`BB_ADRES_BIT-1:0]             addr1                   ,
    input           [31:0]                          dout1                         

);

    assign      csb0        =           ~(ena&(|wea))       ;
    assign      web0        =           ~(|wea)             ;
    assign      wmask0      =           wea                 ;

    assign      addr0       =           addra               ;
    assign      din0        =           dina                ;


    assign      csb1        =           ~(ena&(~(|wea)))    ;
    assign      addr1       =           addra               ;
    assign      douta       =           dout1               ;


endmodule
module buyruk_bellegi_sram
(
    input           [`BB_ADRES_BIT-1:0]             addra                   ,
    input                                           clka                    ,
    input           [31:0]                          dina                    ,
    input                                           ena                     ,
    input           [3:0]                           wea                     ,
                
    output          [31:0]                          douta                   ,


    output                                          csb0                    ,
    output                                          web0                    ,
    output          [3:0]                           wmask0                  ,
    output          [`BB_ADRES_BIT-1:0]             addr0                   ,
    output          [31:0]                          din0                    ,
    input           [31:0]                          dout0                   ,

    output                                          csb1                    ,
    output          [`BB_ADRES_BIT-1:0]             addr1                   ,
    input           [31:0]                          dout1                         

);


    assign      csb0        =           ~(ena&(|wea))       ;
    assign      web0        =           ~(|wea)             ;
    assign      wmask0      =           wea                 ;

    assign      addr0       =           addra               ;
    assign      din0        =           dina                ;


    assign      csb1        =           ~(ena&(~(|wea)))    ;
    assign      addr1       =           addra               ;
    assign      douta       =           dout1               ;


endmodule