data/full_repos/permissive/524073646/Code/verilog_wrapper.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/524073646/Code/verilog_wrapper.v:10: Unsupported: Ignoring delay on this delayed statement.\nalways #(Clockperiod/2) clock = ~clock;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/524073646/Code/verilog_wrapper.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #5000000   $fclose(f);  \n    ^\n%Error: data/full_repos/permissive/524073646/Code/verilog_wrapper.v:21: syntax error, unexpected \'@\'\n    @(posedge UUT.Builder.Builder_Ready);\n    ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module verilog_wrapper( );
reg clock;
parameter Clockperiod = 5;
integer f;


initial clock = 1'b0;
always #(Clockperiod/2) clock = ~clock;

initial begin
    f = $fopen("Verilog_Output_img_f.txt","w");
    #5000000   $fclose(f);
end

Main_tb UUT (.clk_v(clock));


always @(posedge UUT.Builder.Builder_Ready) begin
    @(posedge UUT.Builder.Builder_Ready);
    $fwrite(f,"%d,\n", UUT.Builder.Img_bit );
    $display("%d",UUT.Builder.Result_Addr_to_Bram,"  :  ", "%d",  UUT.Builder.Img_bit);
end 



endmodule
module verilog_wrapper( );

reg clock;
parameter Clockperiod = 5;
integer f;


initial clock = 1'b0;
always #(Clockperiod/2) clock = ~clock;

initial begin
    f = $fopen("Verilog_Output_img_f.txt","w");
    #5000000   $fclose(f);
end

Main_tb UUT (.clk_v(clock));


always @(posedge UUT.Builder.Builder_Ready) begin
    @(posedge UUT.Builder.Builder_Ready);
    $fwrite(f,"%d,\n", UUT.Builder.Img_bit );
    $display("%d",UUT.Builder.Result_Addr_to_Bram,"  :  ", "%d",  UUT.Builder.Img_bit);
end 



endmodule