data/full_repos/permissive/424292861/guia8/ALU.v
1: b"%Error: data/full_repos/permissive/424292861/guia8/ALU.v:60: syntax error, unexpected '=', expecting IDENTIFIER\n s1 = and1;\n    ^\n%Error: data/full_repos/permissive/424292861/guia8/ALU.v:106: syntax error, unexpected '=', expecting IDENTIFIER\n soma = 5'b0001;\n      ^\n%Error: Exiting due to 2 error(s)\n"
module fullsub(a,b,c,s0,s1);
	input a,b,c;
	output s0,s1;
	reg s0,s1;
	wire sub1,sub2,sub3;
	
	halfsub SUB1(a,b,sub1,sub2);
	halfsub SUB2(sub1,c,s0,sub3);
	or      OR(s1,sub2,sub1);
endmodule
module fullsub(a,b,c,s0,s1);

	input a,b,c;
	output s0,s1;
	reg s0,s1;
	wire sub1,sub2,sub3;
	
	halfsub SUB1(a,b,sub1,sub2);
	halfsub SUB2(sub1,c,s0,sub3);
	or      OR(s1,sub2,sub1);
endmodule