data/full_repos/permissive/445929378/encrypting_entity.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/445929378/encrypting_entity.v:72: Signal definition not found, creating implicitly: \'output_tvalid\'\n                                                                              : ... Suggested alternative: \'output_a_tvalid\'\n   assign output_tvalid = out_a_valid & out_b_valid;\n          ^~~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/445929378/encrypting_entity.v:84: Cannot find file containing module: \'LFSR\'\n   LFSR private_key_generator (\n   ^~~~\n        ... Looked in:\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/LFSR\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/LFSR.v\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/LFSR.sv\n             LFSR\n             LFSR.v\n             LFSR.sv\n             obj_dir/LFSR\n             obj_dir/LFSR.v\n             obj_dir/LFSR.sv\n%Error: data/full_repos/permissive/445929378/encrypting_entity.v:93: Cannot find file containing module: \'mod_exp\'\n   mod_exp public_key_generator(\n   ^~~~~~~\n%Error: data/full_repos/permissive/445929378/encrypting_entity.v:110: Cannot find file containing module: \'multiplication_modulo\'\n   multiplication_modulo encrypt(\n   ^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module encrypting_entity #(parameter SIZE = 64)
   (
    input wire 		     clk, rst,

    wire [SIZE-1 : 0] 	     input_p_tdata,
    input wire 		     input_p_tvalid,
    output wire 	     input_p_tready,

    input wire [SIZE-1 : 0]  input_a_key_tdata,
    input wire 		     input_a_key_tvalid, 
    output wire 	     input_a_key_tready, 

    input wire [SIZE-1 : 0]  input_m_tdata,
    input wire 		     input_m_tvalid, 
    output wire 	     input_m_tready, 

    output wire [SIZE-1 : 0] output_a_tdata,
    output wire 	     output_a_tvalid, 
    input wire 		     output_a_tready,
   
    output wire [SIZE-1 : 0] output_b_tdata,
    output wire 	     output_b_tvalid, 
    input wire 		     output_b_tready
    );
   
   reg [SIZE-1 : 0] 	     p;

   reg [SIZE-1 : 0] 	     a_key;

   reg [SIZE-1 : 0] 	     m;

   reg [SIZE-1 : 0] 	     private_key;
   wire [SIZE-1 : 0] 	     private_key_wire;
   wire 		     private_key_ready;
   
   reg [SIZE-1 : 0] 	     public_key;
   wire [SIZE-1 : 0] 	     public_key_wire;
   wire 		     public_key_ready;

   reg [SIZE-1 : 0] 	     cryptogram;
   wire [SIZE-1 : 0] 	     cryptogram_wire;
   wire 		     cryptogram_ready;
   
   reg 			     out_a_valid, out_b_valid;
   reg 			     state = 0;


   reg 			     generate_private_key = 0;
   wire 		     seed_ready = generate_private_key;

   reg 			     generate_public_key = 0;
   wire 		     run_public_key = generate_public_key;
   wire 		     run_encryption = state;
   
   reg 			     data_read = 0;
   wire 		     input_read;
   wire 		     input_rdy = input_p_tvalid & input_a_key_tvalid & input_m_tvalid;

   reg 			     reset = 0;
   wire 		     finish;

   wire 		     rst_mult, rst_rng, rst_mod_exp;
   reg 			     out_valid;
   
   assign input_read = data_read;
   assign output_tvalid = out_a_valid & out_b_valid;
   assign output_a_tdata = public_key;
   assign output_b_tdata = cryptogram;

   assign rst_rng = reset;
   assign rst_mod_exp = reset;
   assign rst_mult = reset;
   
   assign output_a_tvalid = out_valid;
   assign output_b_tvalid = out_valid;
   
   
   LFSR private_key_generator (
			       .clk(clk), 
			       .rst(rst_rng),
			       .input_tvalid(seed_ready),
			       .seed(a_key),
			       .output_tvalid(private_key_ready),
			       .rnd(private_key_wire)
			       );
   
   mod_exp public_key_generator(
				.clk(clk), 
				.rst(rst_mod_exp), 
				.input_base_tdata(a_key),
				.input_base_tvalid(input_read), 

				.input_power_tdata(private_key), 
				.input_power_tvalid(run_public_key), 

				.input_modulus_tdata(p), 
				.input_modulus_tvalid(input_read), 

				.output_tdata(public_key_wire), 
				.output_tvalid(public_key_ready), 
				.output_tready(input_read)
				);

   multiplication_modulo encrypt(
				 .clk(clk), 
				 .rst(rst_mult), 
				 .input_multiplier_tdata(m), 
				 .input_multiplier_tvalid(run_encryption),
				 .input_multiplicand_tdata(public_key), 
				 .input_multiplicand_tvalid(run_encryption), 
				 .input_modulus_tdata(p), 
				 .input_modulus_tvalid(run_encryption), 
				 .output_tdata(cryptogram_wire), 
				 .output_tvalid(finish), 
				 .output_tready(run_encryption)
				 );   

   always @(posedge clk)
     begin
	if(rst) begin
	   p <= 0;

	   state <= 0;
	   public_key <= 0;
	   cryptogram <= 0;
	   m <= 0;
	   a_key <= 0;
	   out_valid <= 0;
	end else begin
	   if(!state) begin

	      if(!input_read) begin
		 p <= input_p_tdata;

		 m <= input_m_tdata;
		 a_key <= input_a_key_tdata;
		 if(input_rdy) begin 
		    data_read <= 1;
		    generate_private_key <= 1;
		 end
	      end else begin
		 if(private_key_ready) begin
		    private_key <= private_key_wire;
		    generate_private_key <= 0;
		    if(private_key < (p + 1)) begin
		       generate_public_key <= 1;

		    end
		 end
		 if(public_key_ready) begin
		    generate_public_key <= 0;
		    public_key <= public_key_wire;
		    state <= 1;
		 end
	      end
	   end else begin

	      if(finish) begin
		 cryptogram <= cryptogram_wire;
		 out_valid <= 1;
		 reset <= 1;
	      end
	   end
	end
	if(reset) reset <= 0;
	
     end
endmodule
module encrypting_entity #(parameter SIZE = 64)
   (
    input wire 		     clk, rst,

    wire [SIZE-1 : 0] 	     input_p_tdata,
    input wire 		     input_p_tvalid,
    output wire 	     input_p_tready,

    input wire [SIZE-1 : 0]  input_a_key_tdata,
    input wire 		     input_a_key_tvalid, 
    output wire 	     input_a_key_tready, 

    input wire [SIZE-1 : 0]  input_m_tdata,
    input wire 		     input_m_tvalid, 
    output wire 	     input_m_tready, 

    output wire [SIZE-1 : 0] output_a_tdata,
    output wire 	     output_a_tvalid, 
    input wire 		     output_a_tready,
   
    output wire [SIZE-1 : 0] output_b_tdata,
    output wire 	     output_b_tvalid, 
    input wire 		     output_b_tready
    );

   
   reg [SIZE-1 : 0] 	     p;

   reg [SIZE-1 : 0] 	     a_key;

   reg [SIZE-1 : 0] 	     m;

   reg [SIZE-1 : 0] 	     private_key;
   wire [SIZE-1 : 0] 	     private_key_wire;
   wire 		     private_key_ready;
   
   reg [SIZE-1 : 0] 	     public_key;
   wire [SIZE-1 : 0] 	     public_key_wire;
   wire 		     public_key_ready;

   reg [SIZE-1 : 0] 	     cryptogram;
   wire [SIZE-1 : 0] 	     cryptogram_wire;
   wire 		     cryptogram_ready;
   
   reg 			     out_a_valid, out_b_valid;
   reg 			     state = 0;


   reg 			     generate_private_key = 0;
   wire 		     seed_ready = generate_private_key;

   reg 			     generate_public_key = 0;
   wire 		     run_public_key = generate_public_key;
   wire 		     run_encryption = state;
   
   reg 			     data_read = 0;
   wire 		     input_read;
   wire 		     input_rdy = input_p_tvalid & input_a_key_tvalid & input_m_tvalid;

   reg 			     reset = 0;
   wire 		     finish;

   wire 		     rst_mult, rst_rng, rst_mod_exp;
   reg 			     out_valid;
   
   assign input_read = data_read;
   assign output_tvalid = out_a_valid & out_b_valid;
   assign output_a_tdata = public_key;
   assign output_b_tdata = cryptogram;

   assign rst_rng = reset;
   assign rst_mod_exp = reset;
   assign rst_mult = reset;
   
   assign output_a_tvalid = out_valid;
   assign output_b_tvalid = out_valid;
   
   
   LFSR private_key_generator (
			       .clk(clk), 
			       .rst(rst_rng),
			       .input_tvalid(seed_ready),
			       .seed(a_key),
			       .output_tvalid(private_key_ready),
			       .rnd(private_key_wire)
			       );
   
   mod_exp public_key_generator(
				.clk(clk), 
				.rst(rst_mod_exp), 
				.input_base_tdata(a_key),
				.input_base_tvalid(input_read), 

				.input_power_tdata(private_key), 
				.input_power_tvalid(run_public_key), 

				.input_modulus_tdata(p), 
				.input_modulus_tvalid(input_read), 

				.output_tdata(public_key_wire), 
				.output_tvalid(public_key_ready), 
				.output_tready(input_read)
				);

   multiplication_modulo encrypt(
				 .clk(clk), 
				 .rst(rst_mult), 
				 .input_multiplier_tdata(m), 
				 .input_multiplier_tvalid(run_encryption),
				 .input_multiplicand_tdata(public_key), 
				 .input_multiplicand_tvalid(run_encryption), 
				 .input_modulus_tdata(p), 
				 .input_modulus_tvalid(run_encryption), 
				 .output_tdata(cryptogram_wire), 
				 .output_tvalid(finish), 
				 .output_tready(run_encryption)
				 );   

   always @(posedge clk)
     begin
	if(rst) begin
	   p <= 0;

	   state <= 0;
	   public_key <= 0;
	   cryptogram <= 0;
	   m <= 0;
	   a_key <= 0;
	   out_valid <= 0;
	end else begin
	   if(!state) begin

	      if(!input_read) begin
		 p <= input_p_tdata;

		 m <= input_m_tdata;
		 a_key <= input_a_key_tdata;
		 if(input_rdy) begin 
		    data_read <= 1;
		    generate_private_key <= 1;
		 end
	      end else begin
		 if(private_key_ready) begin
		    private_key <= private_key_wire;
		    generate_private_key <= 0;
		    if(private_key < (p + 1)) begin
		       generate_public_key <= 1;

		    end
		 end
		 if(public_key_ready) begin
		    generate_public_key <= 0;
		    public_key <= public_key_wire;
		    state <= 1;
		 end
	      end
	   end else begin

	      if(finish) begin
		 cryptogram <= cryptogram_wire;
		 out_valid <= 1;
		 reset <= 1;
	      end
	   end
	end
	if(reset) reset <= 0;
	
     end
endmodule