data/full_repos/permissive/417288846/List_2/Task_3/two_way_counter_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/417288846/List_2/Task_3/two_way_counter_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n        #1 rst = 0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_2/Task_3/two_way_counter_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n        repeat (32) #1 clk = ~clk;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_2/Task_3/two_way_counter_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n        repeat (64) #1 clk = ~clk;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_2/Task_3/two_way_counter_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #1 zero = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_2/Task_3/two_way_counter_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #1 clk = ~clk;\n        ^\n%Error: data/full_repos/permissive/417288846/List_2/Task_3/two_way_counter_tb.v:22: Unsupported or unknown PLI call: $monitor\n    initial $monitor ($time, " out: %b, clk: %d", out, clk);\n            ^~~~~~~~\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
    reg clk, rst, dir, zero; 
    wire [15:0] out;

    two_way_counter twc(.clk(clk), .rst(rst), .dir(dir), .zero(zero), .out(out));
    initial begin
        clk = 0;
        dir = 0;
        zero = 0;
        rst = 1;
        #1 rst = 0;

        repeat (32) #1 clk = ~clk;
        
        dir = 1;
        repeat (64) #1 clk = ~clk;

        #1 zero = 1;
        #1 clk = ~clk;
    end

    initial $monitor ($time, " out: %b, clk: %d", out, clk);
endmodule
module testbench;

    reg clk, rst, dir, zero; 
    wire [15:0] out;

    two_way_counter twc(.clk(clk), .rst(rst), .dir(dir), .zero(zero), .out(out));
    initial begin
        clk = 0;
        dir = 0;
        zero = 0;
        rst = 1;
        #1 rst = 0;

        repeat (32) #1 clk = ~clk;
        
        dir = 1;
        repeat (64) #1 clk = ~clk;

        #1 zero = 1;
        #1 clk = ~clk;
    end

    initial $monitor ($time, " out: %b, clk: %d", out, clk);
endmodule