data/full_repos/permissive/444327372/datapath.v
1: b'%Error: data/full_repos/permissive/444327372/datapath.v:22: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/444327372,data/full_repos/permissive/444327372/defines.vh\n             data/full_repos/permissive/444327372,data/full_repos/permissive/444327372/defines.vh.v\n             data/full_repos/permissive/444327372,data/full_repos/permissive/444327372/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/444327372/datapath.v:206: syntax error, unexpected type\n signext se(.a(instrD[15:0]), .type(instrD[29:28]), .y(signimmD));\n                               ^~~~\n%Error: Exiting due to 2 error(s)\n'
module datapath(
	input wire clk,rst,

	output wire[31:0] pcF,
	input wire[31:0] instrF,
	

	input wire pcsrcD,
	input wire branchD, jumpD, 
	input wire jalD, jrD, balD,
	output wire equalD,
	output wire stallD,
	output wire [31:0] instrD,

	output wire[5:0] opD,functD,
	

	input wire memtoregE,
	input wire alusrcE,regdstE,
	input wire regwriteE,
	input wire[7:0] alucontrolE,
	input wire hi_weE, lo_weE,
	input wire div_validE, signed_divE,
	input wire jalE,jrE,balE,
	output wire stallE,
	output wire flushE,
	

	input wire memenM,
	input wire memtoregM,
	input wire regwriteM,
	output wire[31:0] aluoutM, 
	output wire[31:0] writedata2M,
	input wire[31:0] readdataM,

	input wire[7:0] alucontrolM,
	output wire[3:0] selM,
	output wire [1:0] sizeM,

	

	input wire memtoregW,
	input wire regwriteW,


	output wire[31:0] pcW,
	output wire[3 :0] rf_wen,
	output wire[4 :0] writeregW,
	output wire[31:0] resultW
    );


	wire stallF;
	

	wire [31:0] pcnextFD,pcnextbrFD,pcplus4F,pcbranchD;

	

	wire [31:0] pcD;
	wire [31:0] pcplus4D;
	wire [1:0] jumpjrjalD;
	wire forwardaD,forwardbD;
	wire [4:0] rsD,rtD,rdD, saD;

	wire [31:0] signimmD,signimmshD;
	wire [31:0] srcaD,srca2D,srcbD,srcb2D;



	wire [1:0] forwardaE,forwardbE;
	wire [4:0] rsE,rtE,rdE, saE;
	wire [4:0] writeregE;
	wire [31:0] signimmE;
	wire [31:0] srcaE,srca2E,srcbE,srcb2E,srcb3E;
	wire [31:0] aluoutE;

	wire [31:0] hi_inE;
	wire [31:0] hi_outE;

	wire [31:0] lo_inE;
	wire [31:0] lo_outE;


	wire div_stallE;
	wire [63:0] div_resE;



	wire [31:0] pcE;
	wire [4:0] writereg2E;
	wire [31:0] aluout2E;
	wire [31:0] pcplus8F, pcplus8D, pcplus8E;



	wire [31:0] pcM;
	wire [4:0] writeregM;
	wire [31:0] writedataM;
	wire [31:0] readdata2M;
	




	wire [31:0] aluoutW;
	wire [31:0] readdataW;

	
	assign rf_wen = {4{regwriteW}};


	hazard h(

		.stallF(stallF),


		.rsD(rsD),
		.rtD(rtD),
		
		.branchD(branchD),
		.jumpD(jumpD), 
		.jrD(jrD),

		.forwardaD(forwardaD),
		.forwardbD(forwardbD),
		.stallD(stallD),



		.rsE(rsE),
		.rtE(rtE),
		.writeregE(writeregE),
		.regwriteE(regwriteE),
		.memtoregE(memtoregE),
		.forwardaE(forwardaE),
		.forwardbE(forwardbE),
		.stallE(stallE),
		.flushE(flushE),
		.div_stallE(div_stallE),


		.writeregM(writeregM),
		.regwriteM(regwriteM),
		.memtoregM(memtoregM),


		.writeregW(writeregW),
		.regwriteW(regwriteW)
		);


	mux2 #(32) pcbrmux(pcplus4F, pcbranchD,
					   pcsrcD, pcnextbrFD); 
	

	assign jumpjrjalD = (!jumpD & !jrD & !jalD) ? 2'b00:
					    ((jumpD & !jrD) | jalD) ? 2'b01:
					 	(jrD)					? 2'b10:
					 							  2'b00;

	mux3 #(32) pcmux(pcnextbrFD, {pcplus4D[31:28],instrD[25:0],2'b00}, srca2D,
					 jumpjrjalD, pcnextFD);


	regfile rf(clk,regwriteW,rsD,rtD,writeregW,resultW,srcaD,srcbD);


	pc #(32) pcreg(.clk(clk), .rst(rst),
				   .en(~stallF),
				   .d(pcnextFD), .q(pcF));
	adder pcadd1(pcF,32'b100,pcplus4F);
	adder pcadd2(pcF,32'b1000,pcplus8F);



	flopenrc #(32) r1D(.clk(clk), .rst(rst), .en(~stallD), .d(pcplus4F),.q(pcplus4D));

	flopenrc #(32) r2D(.clk(clk), .rst(rst), .en(~stallD), .d(instrF),  .q(instrD));
	flopenrc #(32) r3D(.clk(clk), .rst(rst), .en(~stallD), .d(pcplus8F),.q(pcplus8D));
	flopenrc #(32) r4D(.clk(clk), .rst(rst), .en(~stallD), .d(pcF),     .q(pcD));

	
	signext se(.a(instrD[15:0]), .type(instrD[29:28]), .y(signimmD));
	sl2 immsh(signimmD,signimmshD);

	adder pcadd3(pcplus4D,signimmshD,pcbranchD);

	mux2 #(32) forwardamux(srcaD,aluoutM,forwardaD,srca2D);
	mux2 #(32) forwardbmux(srcbD,aluoutM,forwardbD,srcb2D);
	eqcmp comp(srca2D,srcb2D,opD,rtD,equalD);

	assign opD = instrD[31:26];
	assign rsD = instrD[25:21];
	assign rtD = instrD[20:16];
	assign rdD = instrD[15:11];
	assign saD = instrD[10:6];
	assign functD = instrD[5:0];


	flopenrc #(32) r1E(clk,rst,~stallE,flushE,srcaD,srcaE);
	flopenrc #(32) r2E(clk,rst,~stallE,flushE,srcbD,srcbE);
	flopenrc #(32) r3E(clk,rst,~stallE,flushE,signimmD,signimmE);

	flopenrc #(5)  r4E(clk,rst,~stallE,flushE,rsD,rsE);
	flopenrc #(5)  r5E(clk,rst,~stallE,flushE,rtD,rtE);
	flopenrc #(5)  r6E(clk,rst,~stallE,flushE,rdD,rdE);
	flopenrc #(5)  r7E(.clk(clk), .rst(rst), .en(~stallE), .clear(flushE), .d(saD), .q(saE));
	flopenrc #(32) r8E(clk,rst,~stallE,flushE,pcplus8D,pcplus8E);
	flopenrc #(32) r10E(clk,rst,~stallE,flushE,pcD,pcE);
	
	mux3 #(32) forwardaemux(srcaE,resultW,aluoutM,forwardaE,srca2E);
	mux3 #(32) forwardbemux(srcbE,resultW,aluoutM,forwardbE,srcb2E);
	mux2 #(32) srcbmux(srcb2E,signimmE,alusrcE,srcb3E);
	

	divider div(.clk(~clk), .rst(rst), 
				   .a(srca2E), .b(srcb3E), 
				   .valid(div_validE), .sign(signed_divE), .div_stall(div_stallE), 
				   .result(div_resE)); 
	alu alu(
			.a(srca2E), .b(srcb3E), .alucontrol(alucontrolE), 
	        .sa(saE), 
			.hi_in(hi_inE), .lo_in(lo_inE), .hi_out(hi_outE), .lo_out(lo_outE),
			.div_res(div_resE),
			.y(aluoutE)
			);
	mux2 #(5) wrmux(rtE,rdE,regdstE,writeregE);
	mux2 #(5) wrmux2(writeregE, 5'b11111, jalE|balE, writereg2E);
	mux2 #(32) wrmux3(aluoutE, pcplus8E, jalE|jrE|balE, aluout2E);



	flopr #(32) r1M(clk,rst,srcb2E,writedataM);
	flopr #(32) r2M(clk,rst,aluout2E,aluoutM);
	flopr #(5)  r3M(clk,rst,writereg2E,writeregM);
	flopr #(32) r5M(clk,rst,pcE,pcM);
	

	flopenr #(32) rHIM(.clk(clk), .rst(rst), .en((hi_weE&(~flushE))), .d(hi_outE), .q(hi_inE));

	flopenr #(32) rLOM(.clk(clk), .rst(rst), .en((lo_weE&(~flushE))), .d(lo_outE), .q(lo_inE));

	data_mem_sel data_mem_sel(.op(alucontrolM), .addr(aluoutM[1:0]), 
							  .writedata(writedataM), .readdata(readdataM),
							  .sel(selM),

							  .writedata2(writedata2M), .readdata2(readdata2M),

							  .size(sizeM));



	flopr #(32) r1W(clk,rst,aluoutM,aluoutW);
	flopr #(32) r2W(clk,rst,readdata2M,readdataW);
	flopr #(5) r3W(clk,rst,writeregM,writeregW);
	flopr #(32) r5W(clk,rst,pcM,pcW);


	mux2 #(32) resmux(aluoutW,readdataW,memtoregW,resultW);


endmodule
module datapath(
	input wire clk,rst,

	output wire[31:0] pcF,
	input wire[31:0] instrF,
	

	input wire pcsrcD,
	input wire branchD, jumpD, 
	input wire jalD, jrD, balD,
	output wire equalD,
	output wire stallD,
	output wire [31:0] instrD,

	output wire[5:0] opD,functD,
	

	input wire memtoregE,
	input wire alusrcE,regdstE,
	input wire regwriteE,
	input wire[7:0] alucontrolE,
	input wire hi_weE, lo_weE,
	input wire div_validE, signed_divE,
	input wire jalE,jrE,balE,
	output wire stallE,
	output wire flushE,
	

	input wire memenM,
	input wire memtoregM,
	input wire regwriteM,
	output wire[31:0] aluoutM, 
	output wire[31:0] writedata2M,
	input wire[31:0] readdataM,

	input wire[7:0] alucontrolM,
	output wire[3:0] selM,
	output wire [1:0] sizeM,

	

	input wire memtoregW,
	input wire regwriteW,


	output wire[31:0] pcW,
	output wire[3 :0] rf_wen,
	output wire[4 :0] writeregW,
	output wire[31:0] resultW
    );



	wire stallF;
	

	wire [31:0] pcnextFD,pcnextbrFD,pcplus4F,pcbranchD;

	

	wire [31:0] pcD;
	wire [31:0] pcplus4D;
	wire [1:0] jumpjrjalD;
	wire forwardaD,forwardbD;
	wire [4:0] rsD,rtD,rdD, saD;

	wire [31:0] signimmD,signimmshD;
	wire [31:0] srcaD,srca2D,srcbD,srcb2D;



	wire [1:0] forwardaE,forwardbE;
	wire [4:0] rsE,rtE,rdE, saE;
	wire [4:0] writeregE;
	wire [31:0] signimmE;
	wire [31:0] srcaE,srca2E,srcbE,srcb2E,srcb3E;
	wire [31:0] aluoutE;

	wire [31:0] hi_inE;
	wire [31:0] hi_outE;

	wire [31:0] lo_inE;
	wire [31:0] lo_outE;


	wire div_stallE;
	wire [63:0] div_resE;



	wire [31:0] pcE;
	wire [4:0] writereg2E;
	wire [31:0] aluout2E;
	wire [31:0] pcplus8F, pcplus8D, pcplus8E;



	wire [31:0] pcM;
	wire [4:0] writeregM;
	wire [31:0] writedataM;
	wire [31:0] readdata2M;
	




	wire [31:0] aluoutW;
	wire [31:0] readdataW;

	
	assign rf_wen = {4{regwriteW}};


	hazard h(

		.stallF(stallF),


		.rsD(rsD),
		.rtD(rtD),
		
		.branchD(branchD),
		.jumpD(jumpD), 
		.jrD(jrD),

		.forwardaD(forwardaD),
		.forwardbD(forwardbD),
		.stallD(stallD),



		.rsE(rsE),
		.rtE(rtE),
		.writeregE(writeregE),
		.regwriteE(regwriteE),
		.memtoregE(memtoregE),
		.forwardaE(forwardaE),
		.forwardbE(forwardbE),
		.stallE(stallE),
		.flushE(flushE),
		.div_stallE(div_stallE),


		.writeregM(writeregM),
		.regwriteM(regwriteM),
		.memtoregM(memtoregM),


		.writeregW(writeregW),
		.regwriteW(regwriteW)
		);


	mux2 #(32) pcbrmux(pcplus4F, pcbranchD,
					   pcsrcD, pcnextbrFD); 
	

	assign jumpjrjalD = (!jumpD & !jrD & !jalD) ? 2'b00:
					    ((jumpD & !jrD) | jalD) ? 2'b01:
					 	(jrD)					? 2'b10:
					 							  2'b00;

	mux3 #(32) pcmux(pcnextbrFD, {pcplus4D[31:28],instrD[25:0],2'b00}, srca2D,
					 jumpjrjalD, pcnextFD);


	regfile rf(clk,regwriteW,rsD,rtD,writeregW,resultW,srcaD,srcbD);


	pc #(32) pcreg(.clk(clk), .rst(rst),
				   .en(~stallF),
				   .d(pcnextFD), .q(pcF));
	adder pcadd1(pcF,32'b100,pcplus4F);
	adder pcadd2(pcF,32'b1000,pcplus8F);



	flopenrc #(32) r1D(.clk(clk), .rst(rst), .en(~stallD), .d(pcplus4F),.q(pcplus4D));

	flopenrc #(32) r2D(.clk(clk), .rst(rst), .en(~stallD), .d(instrF),  .q(instrD));
	flopenrc #(32) r3D(.clk(clk), .rst(rst), .en(~stallD), .d(pcplus8F),.q(pcplus8D));
	flopenrc #(32) r4D(.clk(clk), .rst(rst), .en(~stallD), .d(pcF),     .q(pcD));

	
	signext se(.a(instrD[15:0]), .type(instrD[29:28]), .y(signimmD));
	sl2 immsh(signimmD,signimmshD);

	adder pcadd3(pcplus4D,signimmshD,pcbranchD);

	mux2 #(32) forwardamux(srcaD,aluoutM,forwardaD,srca2D);
	mux2 #(32) forwardbmux(srcbD,aluoutM,forwardbD,srcb2D);
	eqcmp comp(srca2D,srcb2D,opD,rtD,equalD);

	assign opD = instrD[31:26];
	assign rsD = instrD[25:21];
	assign rtD = instrD[20:16];
	assign rdD = instrD[15:11];
	assign saD = instrD[10:6];
	assign functD = instrD[5:0];


	flopenrc #(32) r1E(clk,rst,~stallE,flushE,srcaD,srcaE);
	flopenrc #(32) r2E(clk,rst,~stallE,flushE,srcbD,srcbE);
	flopenrc #(32) r3E(clk,rst,~stallE,flushE,signimmD,signimmE);

	flopenrc #(5)  r4E(clk,rst,~stallE,flushE,rsD,rsE);
	flopenrc #(5)  r5E(clk,rst,~stallE,flushE,rtD,rtE);
	flopenrc #(5)  r6E(clk,rst,~stallE,flushE,rdD,rdE);
	flopenrc #(5)  r7E(.clk(clk), .rst(rst), .en(~stallE), .clear(flushE), .d(saD), .q(saE));
	flopenrc #(32) r8E(clk,rst,~stallE,flushE,pcplus8D,pcplus8E);
	flopenrc #(32) r10E(clk,rst,~stallE,flushE,pcD,pcE);
	
	mux3 #(32) forwardaemux(srcaE,resultW,aluoutM,forwardaE,srca2E);
	mux3 #(32) forwardbemux(srcbE,resultW,aluoutM,forwardbE,srcb2E);
	mux2 #(32) srcbmux(srcb2E,signimmE,alusrcE,srcb3E);
	

	divider div(.clk(~clk), .rst(rst), 
				   .a(srca2E), .b(srcb3E), 
				   .valid(div_validE), .sign(signed_divE), .div_stall(div_stallE), 
				   .result(div_resE)); 
	alu alu(
			.a(srca2E), .b(srcb3E), .alucontrol(alucontrolE), 
	        .sa(saE), 
			.hi_in(hi_inE), .lo_in(lo_inE), .hi_out(hi_outE), .lo_out(lo_outE),
			.div_res(div_resE),
			.y(aluoutE)
			);
	mux2 #(5) wrmux(rtE,rdE,regdstE,writeregE);
	mux2 #(5) wrmux2(writeregE, 5'b11111, jalE|balE, writereg2E);
	mux2 #(32) wrmux3(aluoutE, pcplus8E, jalE|jrE|balE, aluout2E);



	flopr #(32) r1M(clk,rst,srcb2E,writedataM);
	flopr #(32) r2M(clk,rst,aluout2E,aluoutM);
	flopr #(5)  r3M(clk,rst,writereg2E,writeregM);
	flopr #(32) r5M(clk,rst,pcE,pcM);
	

	flopenr #(32) rHIM(.clk(clk), .rst(rst), .en((hi_weE&(~flushE))), .d(hi_outE), .q(hi_inE));

	flopenr #(32) rLOM(.clk(clk), .rst(rst), .en((lo_weE&(~flushE))), .d(lo_outE), .q(lo_inE));

	data_mem_sel data_mem_sel(.op(alucontrolM), .addr(aluoutM[1:0]), 
							  .writedata(writedataM), .readdata(readdataM),
							  .sel(selM),

							  .writedata2(writedata2M), .readdata2(readdata2M),

							  .size(sizeM));



	flopr #(32) r1W(clk,rst,aluoutM,aluoutW);
	flopr #(32) r2W(clk,rst,readdata2M,readdataW);
	flopr #(5) r3W(clk,rst,writeregM,writeregW);
	flopr #(32) r5W(clk,rst,pcM,pcW);


	mux2 #(32) resmux(aluoutW,readdataW,memtoregW,resultW);


endmodule