data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/DATA_RAM.v
data/verilator_xmls/0d9ff212-e206-48bd-8ae8-276890757c94.xml
module data_ram(

	input	wire										clk,
	input wire										I_FROMMEM_ce,
	input wire										I_FROMMEM_we,
	input wire[31:0]			I_FROMMEM_addr,
	input wire[3:0]								I_FROMMEM_sel,
	input wire[31:0]						I_FROMMEM_data,
	output reg[31:0]					O_TOMEM_data
	
);

	reg[7:0]  data_mem0[0:131071-1];
	reg[7:0]  data_mem1[0:131071-1];
	reg[7:0]  data_mem2[0:131071-1];
	reg[7:0]  data_mem3[0:131071-1];

	always @ (posedge clk) begin
		if (I_FROMMEM_ce == 1'b0) begin

		end else if(I_FROMMEM_we == 1'b1) begin
			  if (I_FROMMEM_sel[3] == 1'b1) begin
		      data_mem3[I_FROMMEM_addr[17+1:2]] <= I_FROMMEM_data[31:24];
		    end
			  if (I_FROMMEM_sel[2] == 1'b1) begin
		      data_mem2[I_FROMMEM_addr[17+1:2]] <= I_FROMMEM_data[23:16];
		    end
		    if (I_FROMMEM_sel[1] == 1'b1) begin
		      data_mem1[I_FROMMEM_addr[17+1:2]] <= I_FROMMEM_data[15:8];
		    end
			  if (I_FROMMEM_sel[0] == 1'b1) begin
		      data_mem0[I_FROMMEM_addr[17+1:2]] <= I_FROMMEM_data[7:0];
		    end			   	    
		end
	end

	always @ (*) begin
		if (I_FROMMEM_ce == 1'b0) begin
			O_TOMEM_data <= 32'h00000000;
	  end else if(I_FROMMEM_we == 1'b0) begin
		    O_TOMEM_data <= {data_mem3[I_FROMMEM_addr[17+1:2]],
		               data_mem2[I_FROMMEM_addr[17+1:2]],
		               data_mem1[I_FROMMEM_addr[17+1:2]],
		               data_mem0[I_FROMMEM_addr[17+1:2]]};
		end else begin
				O_TOMEM_data <= 32'h00000000;
		end
	end		

endmodule
module data_ram(

	input	wire										clk,
	input wire										I_FROMMEM_ce,
	input wire										I_FROMMEM_we,
	input wire[31:0]			I_FROMMEM_addr,
	input wire[3:0]								I_FROMMEM_sel,
	input wire[31:0]						I_FROMMEM_data,
	output reg[31:0]					O_TOMEM_data
	
);


	reg[7:0]  data_mem0[0:131071-1];
	reg[7:0]  data_mem1[0:131071-1];
	reg[7:0]  data_mem2[0:131071-1];
	reg[7:0]  data_mem3[0:131071-1];

	always @ (posedge clk) begin
		if (I_FROMMEM_ce == 1'b0) begin

		end else if(I_FROMMEM_we == 1'b1) begin
			  if (I_FROMMEM_sel[3] == 1'b1) begin
		      data_mem3[I_FROMMEM_addr[17+1:2]] <= I_FROMMEM_data[31:24];
		    end
			  if (I_FROMMEM_sel[2] == 1'b1) begin
		      data_mem2[I_FROMMEM_addr[17+1:2]] <= I_FROMMEM_data[23:16];
		    end
		    if (I_FROMMEM_sel[1] == 1'b1) begin
		      data_mem1[I_FROMMEM_addr[17+1:2]] <= I_FROMMEM_data[15:8];
		    end
			  if (I_FROMMEM_sel[0] == 1'b1) begin
		      data_mem0[I_FROMMEM_addr[17+1:2]] <= I_FROMMEM_data[7:0];
		    end			   	    
		end
	end

	always @ (*) begin
		if (I_FROMMEM_ce == 1'b0) begin
			O_TOMEM_data <= 32'h00000000;
	  end else if(I_FROMMEM_we == 1'b0) begin
		    O_TOMEM_data <= {data_mem3[I_FROMMEM_addr[17+1:2]],
		               data_mem2[I_FROMMEM_addr[17+1:2]],
		               data_mem1[I_FROMMEM_addr[17+1:2]],
		               data_mem0[I_FROMMEM_addr[17+1:2]]};
		end else begin
				O_TOMEM_data <= 32'h00000000;
		end
	end		

endmodule