data/full_repos/permissive/503973366/SIM/rf_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/rf_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n            #(10/2) CLK = ~CLK;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/503973366/SIM/rf_tb.v:49: Unsupported or unknown PLI call: $monitor\n        $monitor("Write_En = %b, Write_Addr = %b, Write_DATA = %b, Read_Addr = %b, Read_Data = %b",\n        ^~~~~~~~\n%Error: data/full_repos/permissive/503973366/SIM/rf_tb.v:61: syntax error, unexpected \'@\'\n        @(posedge CLK);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/rf_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n        #(3)\n        ^\n%Error: data/full_repos/permissive/503973366/SIM/rf_tb.v:68: syntax error, unexpected \'@\'\n        @(posedge CLK);\n        ^\n%Error: data/full_repos/permissive/503973366/SIM/rf_tb.v:73: syntax error, unexpected \'@\'\n        @(posedge CLK);\n        ^\n%Error: data/full_repos/permissive/503973366/SIM/rf_tb.v:78: syntax error, unexpected \'@\'\n        @(posedge CLK);\n        ^\n%Error: data/full_repos/permissive/503973366/SIM/rf_tb.v:83: syntax error, unexpected \'@\'\n        @(posedge CLK);\n        ^\n%Error: data/full_repos/permissive/503973366/SIM/rf_tb.v:88: syntax error, unexpected \'@\'\n        @(posedge CLK);\n        ^\n%Error: data/full_repos/permissive/503973366/SIM/rf_tb.v:92: syntax error, unexpected \'@\'\n        @(posedge CLK);\n        ^\n%Error: data/full_repos/permissive/503973366/SIM/rf_tb.v:96: syntax error, unexpected \'@\'\n        @(posedge CLK);\n        ^\n%Error: data/full_repos/permissive/503973366/SIM/rf_tb.v:99: syntax error, unexpected \'@\'\n        @(posedge CLK);\n        ^\n%Error: Exiting due to 10 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module REG_FILE_TB #(

    parameter   DATA_WIDTH = 32,
    parameter   ADDR_WIDTH = 5
    )
    (


    );
    

    reg                       CLK;        
    reg                       WE;
    reg   [ADDR_WIDTH-1:0]    WA;
    reg   [DATA_WIDTH-1:0]    WD;
    reg   [ADDR_WIDTH-1:0]    RA;
    wire  [DATA_WIDTH-1:0]    RD;


    REG_FILE #(
        .DATA_WIDTH(DATA_WIDTH),
        .ADDR_WIDTH(ADDR_WIDTH)
    ) DUT (

        .clk    (CLK),
        .we_i   (WE),
        .wa_i   (WA),
        .wd_i   (WD),
        .ra_i   (RA),
        .rd_o   (RD)
    );



    initial begin
        CLK = 1'b0;
        forever begin
            #(`CLOCK_PERIOD/2) CLK = ~CLK;
        end
    end



    initial begin 
        $monitor("Write_En = %b, Write_Addr = %b, Write_DATA = %b, Read_Addr = %b, Read_Data = %b",
                    WE, WA, WD, RA, RD);
    end
    

    initial begin
        WE = 1'b0;
        WA = {(ADDR_WIDTH){1'b0}};
        WD = {(DATA_WIDTH){1'b0}};
        RA = {(ADDR_WIDTH){1'b0}};
        
        $display("Write1");
        @(posedge CLK);
        #(`DELTA)
            WE = 1'b1;
            WA = 'd1;
            WD = 'd1;
        
        $display("Write2");
        @(posedge CLK);
            WA = 'd2;
            WD = 'd2;

        $display("Write3");
        @(posedge CLK);
            WA = 'd3;
            WD = 'd3;
            
        $display("Write4");
        @(posedge CLK);
            WA = 'd4;
            WD = 'd4;
        
        $display("Read1");
        @(posedge CLK);
            WE = 1'b0;
            RA = 'd1;
            
        $display("Read2");
        @(posedge CLK);
            RA = 'd2;

        $display("Read3");
        @(posedge CLK);
            RA = 'd3;

        $display("Read4");
        @(posedge CLK);
            RA = 'd4;
            
        @(posedge CLK);

        $display("finished testbench");
        $finish;
    end

endmodule
module REG_FILE_TB #(

    parameter   DATA_WIDTH = 32,
    parameter   ADDR_WIDTH = 5
    )
    (


    );

    

    reg                       CLK;        
    reg                       WE;
    reg   [ADDR_WIDTH-1:0]    WA;
    reg   [DATA_WIDTH-1:0]    WD;
    reg   [ADDR_WIDTH-1:0]    RA;
    wire  [DATA_WIDTH-1:0]    RD;


    REG_FILE #(
        .DATA_WIDTH(DATA_WIDTH),
        .ADDR_WIDTH(ADDR_WIDTH)
    ) DUT (

        .clk    (CLK),
        .we_i   (WE),
        .wa_i   (WA),
        .wd_i   (WD),
        .ra_i   (RA),
        .rd_o   (RD)
    );



    initial begin
        CLK = 1'b0;
        forever begin
            #(`CLOCK_PERIOD/2) CLK = ~CLK;
        end
    end



    initial begin 
        $monitor("Write_En = %b, Write_Addr = %b, Write_DATA = %b, Read_Addr = %b, Read_Data = %b",
                    WE, WA, WD, RA, RD);
    end
    

    initial begin
        WE = 1'b0;
        WA = {(ADDR_WIDTH){1'b0}};
        WD = {(DATA_WIDTH){1'b0}};
        RA = {(ADDR_WIDTH){1'b0}};
        
        $display("Write1");
        @(posedge CLK);
        #(`DELTA)
            WE = 1'b1;
            WA = 'd1;
            WD = 'd1;
        
        $display("Write2");
        @(posedge CLK);
            WA = 'd2;
            WD = 'd2;

        $display("Write3");
        @(posedge CLK);
            WA = 'd3;
            WD = 'd3;
            
        $display("Write4");
        @(posedge CLK);
            WA = 'd4;
            WD = 'd4;
        
        $display("Read1");
        @(posedge CLK);
            WE = 1'b0;
            RA = 'd1;
            
        $display("Read2");
        @(posedge CLK);
            RA = 'd2;

        $display("Read3");
        @(posedge CLK);
            RA = 'd3;

        $display("Read4");
        @(posedge CLK);
            RA = 'd4;
            
        @(posedge CLK);

        $display("finished testbench");
        $finish;
    end

endmodule