data/full_repos/permissive/441359809/src/yosys/tests/various/const_func.v
1: b'%Warning-REALCVT: data/full_repos/permissive/441359809/src/yosys/tests/various/const_func.v:63: Implicit conversion of real to integer\n    localparam signed Z = negate($floor(W / X));\n                                 ^~~~~~\n                  ... Use "/* verilator lint_off REALCVT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/const_func.v:25: Operator FUNCREF \'flip\' expects 24 bits on the Function Argument, but Function Argument\'s SEL generates 8 bits.\n                                                                                            : ... In instance top.e4\n        for (i = 0; i != flip(flip(OUTPUT[15:8])); i = i + 1)\n                              ^~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/const_func.v:25: Operator NEQ expects 32 bits on the RHS, but RHS\'s FUNCREF \'flip\' generates 24 bits.\n                                                                                            : ... In instance top.e4\n        for (i = 0; i != flip(flip(OUTPUT[15:8])); i = i + 1)\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/const_func.v:33: Operator FUNCREF \'flip\' expects 24 bits on the Function Argument, but Function Argument\'s SEL generates 8 bits.\n                                                                                            : ... In instance top.e3\n        for (j = 0; j != flip(flip(OUTPUT[15:8])); j = j + 1)\n                              ^~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/const_func.v:33: Operator NEQ expects 32 bits on the RHS, but RHS\'s FUNCREF \'flip\' generates 24 bits.\n                                                                                            : ... In instance top.e3\n        for (j = 0; j != flip(flip(OUTPUT[15:8])); j = j + 1)\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/const_func.v:34: Operator EQ expects 32 bits on the RHS, but RHS\'s FUNCREF \'flip\' generates 24 bits.\n                                                                                            : ... In instance top.e3\n            if (j + 1 == flip(flip("O")))\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/const_func.v:50: Operator ASSIGNW expects 196 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 200 bits.\n                                                                                            : ... In instance top\n    assign out = {\n               ^\n%Error: Exiting due to 7 warning(s)\n'
module top(out);
    wire [23:0] a1, a2, a3, a4;
    wire [23:0] b1, b2, b3, b4;
    wire        c1, c2, c3, c4;
    wire        d1, d2, d3, d4;
    Example          e1(a1, b1, c1, d1);
    Example #("FOO") e2(a2, b2, c2, d2);
    Example #("BAR") e3(a3, b3, c3, d3);
    Example #("BAZ") e4(a4, b4, c4, d4);

    output wire [24 * 8 - 1 + 4 :0] out;
    assign out = {
        a1, a2, a3, a4,
        b1, b2, b3, b4,
        c1, c2, c3, c4,
        d1, d2, d3, d4};

    function signed [31:0] negate;
        input integer inp;
        negate = ~inp;
    endfunction
    parameter W = 10;
    parameter X = 3;
    localparam signed Y = $floor(W / X);
    localparam signed Z = negate($floor(W / X));


`ifdef VERIFY
    assert property (a1 == 0);
    assert property (a2 == 0);
    assert property (a3 == "BAR");
    assert property (a4 == 0);
    assert property (b1 == "FOO");
    assert property (b2 == "FOO");
    assert property (b3 == 0);
    assert property (b4 == "HI");
    assert property (c1 == 1);
    assert property (c2 == 1);
    assert property (c3 == 0);
    assert property (c4 == 0);
    assert property (d1 == 0);
    assert property (d2 == 0);
    assert property (d3 == 1);
    assert property (d4 == 1);

    assert property (Y == 3);
    assert property (Z == ~3);
`endif
endmodule
module top(out);

    wire [23:0] a1, a2, a3, a4;
    wire [23:0] b1, b2, b3, b4;
    wire        c1, c2, c3, c4;
    wire        d1, d2, d3, d4;
    Example          e1(a1, b1, c1, d1);
    Example #("FOO") e2(a2, b2, c2, d2);
    Example #("BAR") e3(a3, b3, c3, d3);
    Example #("BAZ") e4(a4, b4, c4, d4);

    output wire [24 * 8 - 1 + 4 :0] out;
    assign out = {
        a1, a2, a3, a4,
        b1, b2, b3, b4,
        c1, c2, c3, c4,
        d1, d2, d3, d4};

    function signed [31:0] negate;
        input integer inp;
        negate = ~inp;
    endfunction
    parameter W = 10;
    parameter X = 3;
    localparam signed Y = $floor(W / X);
    localparam signed Z = negate($floor(W / X));


`ifdef VERIFY
    assert property (a1 == 0);
    assert property (a2 == 0);
    assert property (a3 == "BAR");
    assert property (a4 == 0);
    assert property (b1 == "FOO");
    assert property (b2 == "FOO");
    assert property (b3 == 0);
    assert property (b4 == "HI");
    assert property (c1 == 1);
    assert property (c2 == 1);
    assert property (c3 == 0);
    assert property (c4 == 0);
    assert property (d1 == 0);
    assert property (d2 == 0);
    assert property (d3 == 1);
    assert property (d4 == 1);

    assert property (Y == 3);
    assert property (Z == ~3);
`endif
endmodule