data/full_repos/permissive/497337299/basics/src/reg8.v
data/verilator_xmls/e778e026-cade-4c22-ac48-675ee6c941a5.xml
module reg8 #(
    N = 8
) (
    input rst, clk, en, 
    input [N-1: 0] d, 
    output reg [N-1: 0] q 
); 

    always @(posedge clk, posedge rst) begin
        if (rst) begin 
            q <= 0; 
        end
        else if (en) begin 
            q <= d; 
        end
    end
endmodule
module reg8 #(
    N = 8
) (
    input rst, clk, en, 
    input [N-1: 0] d, 
    output reg [N-1: 0] q 
);
 

    always @(posedge clk, posedge rst) begin
        if (rst) begin 
            q <= 0; 
        end
        else if (en) begin 
            q <= d; 
        end
    end
endmodule