data/full_repos/permissive/481044442/BDCDrv/power_on_reset.v
data/verilator_xmls/2c7d6346-3369-459e-a3d1-206f06e02ba1.xml
module power_on_reset(clk,reset);

input clk;
output reset;






parameter CNT_TXCLK=12'd2559;
reg [11:0] cnt4txclk;
reg txclk;


always@(posedge clk or posedge reset)
begin
	if(reset)
		begin
			txclk<=0;
			cnt4txclk<=12'd0;
		end
	else
		if(cnt4txclk==CNT_TXCLK)
			begin
				txclk<=~txclk;
				cnt4txclk<=12'd0;
			end
		else
			cnt4txclk<=cnt4txclk+1'b1;
end



reg [31:0] count = 0;

always @(posedge clk) 
begin
		if(txclk) begin
					if(count == 32'h0xfffffff) 
						count <= count;
					else
						count <= count + 1'b1;
		end
end

assign reset = (count==32'h0xffffffe) ? 1'b1 : 1'b0;
endmodule
module power_on_reset(clk,reset);


input clk;
output reset;






parameter CNT_TXCLK=12'd2559;
reg [11:0] cnt4txclk;
reg txclk;


always@(posedge clk or posedge reset)
begin
	if(reset)
		begin
			txclk<=0;
			cnt4txclk<=12'd0;
		end
	else
		if(cnt4txclk==CNT_TXCLK)
			begin
				txclk<=~txclk;
				cnt4txclk<=12'd0;
			end
		else
			cnt4txclk<=cnt4txclk+1'b1;
end



reg [31:0] count = 0;

always @(posedge clk) 
begin
		if(txclk) begin
					if(count == 32'h0xfffffff) 
						count <= count;
					else
						count <= count + 1'b1;
		end
end

assign reset = (count==32'h0xffffffe) ? 1'b1 : 1'b0;
endmodule