data/full_repos/permissive/524532083/verilog/rtl/dot_driver.v
data/verilator_xmls/deeac705-978c-49d0-82f4-3e0dd8fd3b73.xml
module dot_driver(
  input   wire  clock,

  input   wire  dot_enable,
  input   wire  output_enable,
  input   wire  dot_state,
  input   wire  dot_invert,
  output  reg   data,
  output  reg   enable
);
 
  always@(posedge clock)
  begin


      data <= dot_invert ? ~dot_state : dot_state;


  end

  always@(posedge clock)
  begin

    case({dot_enable,output_enable})
      2'b11   : enable <= dot_enable;
      default : enable <= 1'b0;
    endcase
  end


endmodule
module dot_driver(
  input   wire  clock,

  input   wire  dot_enable,
  input   wire  output_enable,
  input   wire  dot_state,
  input   wire  dot_invert,
  output  reg   data,
  output  reg   enable
);

 
  always@(posedge clock)
  begin


      data <= dot_invert ? ~dot_state : dot_state;


  end

  always@(posedge clock)
  begin

    case({dot_enable,output_enable})
      2'b11   : enable <= dot_enable;
      default : enable <= 1'b0;
    endcase
  end


endmodule