data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_nopl/montpro.v
1: b'%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_nopl/montpro.v:85: Cannot find file containing module: \'mux_xx1\'\nmux_xx1 #(WID) imxa (ZERO,b,asrg[0],mxao);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_nopl,data/full_repos/permissive/530013823/mux_xx1\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_nopl,data/full_repos/permissive/530013823/mux_xx1.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_nopl,data/full_repos/permissive/530013823/mux_xx1.sv\n             mux_xx1\n             mux_xx1.v\n             mux_xx1.sv\n             obj_dir/mux_xx1\n             obj_dir/mux_xx1.v\n             obj_dir/mux_xx1.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_nopl/montpro.v:91: Cannot find file containing module: \'cla\'\ncla #(WID+1) iclaa (adari,{1\'b0,mxao},adars[WID:0],adars[WID+1]);\n^~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_nopl/montpro.v:96: Cannot find file containing module: \'mux_xx1\'\nmux_xx1 #(WID) imxm (ZERO,m,adars[0],mxmo);\n^~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_nopl/montpro.v:101: Cannot find file containing module: \'cla\'\ncla #(WID+2) iclam (adars,{2\'b0,mxmo},admrs[WID+1:0],admrs[WID+2]);\n^~~\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_nopl/montpro.v:110: Operator ASSIGNDLY expects 259 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 258 bits.\n                                                                                                                                       : ... In instance montpro\n        rsrg <= {2\'b0,ZERO};\n             ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_nopl/montpro.v:114: Operator ASSIGNDLY expects 259 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 258 bits.\n                                                                                                                                       : ... In instance montpro\n        rsrg <= {2\'b0,ZERO};\n             ^~\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module montpro
    (
     clk,
     rst,
     
     a,
     b,
     m,
     

     ldnew,

     
     r
     );




parameter WID = 256;
parameter ZERO = 256'b0;




input     clk;
input     rst;

input [WID-1:0] a;
input [WID-1:0] b;
input [WID-1:0] m;


input           ldnew;


output [WID:0] r;









reg [WID-1:0]    asrg;

always@(posedge clk)
    begin
    if(rst)
        begin
        asrg <= ZERO;
        end
    else if(ldnew)
        begin
        asrg <= a;
        end




    else
        begin
        asrg <= {1'b0,asrg[WID-1:1]};
        end
    end


wire [WID-1:0] mxao;

mux_xx1 #(WID) imxa (ZERO,b,asrg[0],mxao);


wire [WID:0] adari;
wire [WID+1:0]   adars;

cla #(WID+1) iclaa (adari,{1'b0,mxao},adars[WID:0],adars[WID+1]);


wire [WID-1:0] mxmo;

mux_xx1 #(WID) imxm (ZERO,m,adars[0],mxmo);


wire [WID+2:0]   admrs;

cla #(WID+2) iclam (adars,{2'b0,mxmo},admrs[WID+1:0],admrs[WID+2]);


reg [WID+2:0]    rsrg;

always@(posedge clk)
    begin
    if(rst)
        begin
        rsrg <= {2'b0,ZERO};
        end
    else if(ldnew)
        begin
        rsrg <= {2'b0,ZERO};
        end




    else
        begin
        rsrg <= {1'b0,admrs[WID+2:1]};
        end
    end

assign r = rsrg[WID:0];
assign adari = rsrg[WID:0];
  
endmodule
module montpro
    (
     clk,
     rst,
     
     a,
     b,
     m,
     

     ldnew,

     
     r
     );





parameter WID = 256;
parameter ZERO = 256'b0;




input     clk;
input     rst;

input [WID-1:0] a;
input [WID-1:0] b;
input [WID-1:0] m;


input           ldnew;


output [WID:0] r;









reg [WID-1:0]    asrg;

always@(posedge clk)
    begin
    if(rst)
        begin
        asrg <= ZERO;
        end
    else if(ldnew)
        begin
        asrg <= a;
        end




    else
        begin
        asrg <= {1'b0,asrg[WID-1:1]};
        end
    end


wire [WID-1:0] mxao;

mux_xx1 #(WID) imxa (ZERO,b,asrg[0],mxao);


wire [WID:0] adari;
wire [WID+1:0]   adars;

cla #(WID+1) iclaa (adari,{1'b0,mxao},adars[WID:0],adars[WID+1]);


wire [WID-1:0] mxmo;

mux_xx1 #(WID) imxm (ZERO,m,adars[0],mxmo);


wire [WID+2:0]   admrs;

cla #(WID+2) iclam (adars,{2'b0,mxmo},admrs[WID+1:0],admrs[WID+2]);


reg [WID+2:0]    rsrg;

always@(posedge clk)
    begin
    if(rst)
        begin
        rsrg <= {2'b0,ZERO};
        end
    else if(ldnew)
        begin
        rsrg <= {2'b0,ZERO};
        end




    else
        begin
        rsrg <= {1'b0,admrs[WID+2:1]};
        end
    end

assign r = rsrg[WID:0];
assign adari = rsrg[WID:0];
  
endmodule