data/full_repos/permissive/505514178/source_code/Register_File.v
data/verilator_xmls/f28105a9-2894-4302-a005-22395b4172da.xml
module Register_File(
    input [4:0] Read_Reg_1,
    input [4:0] Read_Reg_2,
    input [4:0] Write_Reg,
    input [31:0] Write_Data,
    output [31:0] Read_Data_1,
    output [31:0] Read_Data_2,
    input RegWrite,
    input reset
    );
reg [31:0] RegMemory [31:0];
reg flag;

always@(reset,Write_Reg,Write_Data)
if(reset == 0)
flag = 1'b0;
else
flag = ~flag;

always@(reset,RegWrite,flag)
begin
if(reset == 0)
$readmemh("RegisterFile.mem",RegMemory);
else if(RegWrite == 1 && Write_Reg != 0)
RegMemory[Write_Reg] = Write_Data;
end

assign Read_Data_1 = RegMemory[Read_Reg_1];
assign Read_Data_2 = RegMemory[Read_Reg_2];

endmodule
module Register_File(
    input [4:0] Read_Reg_1,
    input [4:0] Read_Reg_2,
    input [4:0] Write_Reg,
    input [31:0] Write_Data,
    output [31:0] Read_Data_1,
    output [31:0] Read_Data_2,
    input RegWrite,
    input reset
    );

reg [31:0] RegMemory [31:0];
reg flag;

always@(reset,Write_Reg,Write_Data)
if(reset == 0)
flag = 1'b0;
else
flag = ~flag;

always@(reset,RegWrite,flag)
begin
if(reset == 0)
$readmemh("RegisterFile.mem",RegMemory);
else if(RegWrite == 1 && Write_Reg != 0)
RegMemory[Write_Reg] = Write_Data;
end

assign Read_Data_1 = RegMemory[Read_Reg_1];
assign Read_Data_2 = RegMemory[Read_Reg_2];

endmodule