data/full_repos/permissive/417288846/List_3/Task_1/div_3_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/417288846/List_3/Task_1/div_3_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n                    #1;\n                    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/417288846/List_3/Task_1/div_3_tb.v:31: Unsupported or unknown PLI call: $monitor\n    initial $monitor ($time, " out: %d, num: %h", out, num);\n            ^~~~~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
    integer i, j, k;
    parameter length = 4;
    reg [4*length:0] num;
    wire out;

    div_3 #(length) div2(.num(num), .divisable(out));

    initial begin
        num = 16'b0;

        for (k = 0; k < 10 ; k = k + 1)
        begin
            num[11:8] = k;
            for (j = 0; j < 10 ; j = j + 1)
            begin
                num[7:4] = j;
                for (i = 0; i < 10 ; i = i + 1)
                begin
                    num[3:0] = i;
                    #1;
                end
            end
        end

    end

    initial $monitor ($time, " out: %d, num: %h", out, num);
endmodule
module testbench;

    integer i, j, k;
    parameter length = 4;
    reg [4*length:0] num;
    wire out;

    div_3 #(length) div2(.num(num), .divisable(out));

    initial begin
        num = 16'b0;

        for (k = 0; k < 10 ; k = k + 1)
        begin
            num[11:8] = k;
            for (j = 0; j < 10 ; j = j + 1)
            begin
                num[7:4] = j;
                for (i = 0; i < 10 ; i = i + 1)
                begin
                    num[3:0] = i;
                    #1;
                end
            end
        end

    end

    initial $monitor ($time, " out: %d, num: %h", out, num);
endmodule