data/full_repos/permissive/502764644/mpeg_audio_video/ETHERNET/Bitstream_Parser/System_Buffer.v
1: b'%Error: data/full_repos/permissive/502764644/mpeg_audio_video/ETHERNET/Bitstream_Parser/System_Buffer.v:17: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502764644/mpeg_audio_video/ETHERNET/Bitstream_Parser,data/full_repos/permissive/502764644/defines.v\n             data/full_repos/permissive/502764644/mpeg_audio_video/ETHERNET/Bitstream_Parser,data/full_repos/permissive/502764644/defines.v.v\n             data/full_repos/permissive/502764644/mpeg_audio_video/ETHERNET/Bitstream_Parser,data/full_repos/permissive/502764644/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/ETHERNET/Bitstream_Parser/System_Buffer.v:31: Define or directive not defined: \'`SYSTEM_BUFFER_ADDR_WIDTH\'\ninput [`SYSTEM_BUFFER_ADDR_WIDTH-1:0] Address_A_I;\n       ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/ETHERNET/Bitstream_Parser/System_Buffer.v:35: Define or directive not defined: \'`SYSTEM_BUFFER_ADDR_WIDTH\'\ninput [`SYSTEM_BUFFER_ADDR_WIDTH-1:0] Address_B_I;\n       ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module System_Buffer(
   in_clock,
	out_clock,
   Address_A_I,
   Write_Enable_A_I,
   Data_A_I,
   Enable_B_I,
   Address_B_I,
   Data_B_O
);

input             in_clock;
input             out_clock;
input [`SYSTEM_BUFFER_ADDR_WIDTH-1:0] Address_A_I;
input             Write_Enable_A_I;
input    [31:0]   Data_A_I;
input             Enable_B_I;
input [`SYSTEM_BUFFER_ADDR_WIDTH-1:0] Address_B_I;
output   [31:0]   Data_B_O;

RAMB16_S18_S18 System_Buffer_RAM_H (
   .DOA(),
   .DOB(Data_B_O[31:16]),
   .DOPA(),
   .DOPB(),
   .ADDRA(Address_A_I[9:0]),
   .ADDRB(Address_B_I[9:0]),
   .CLKA(in_clock),
   .CLKB(out_clock),
   .DIA(Data_A_I[31:16]),
   .DIB(16'h0000),
   .DIPA(2'b00),
   .DIPB(2'b00),
   .ENA(1'b1),
   .ENB(Enable_B_I),
   .SSRA(1'b0),
   .SSRB(1'b0),
   .WEA(Write_Enable_A_I),
   .WEB(1'b0)
);

RAMB16_S18_S18 System_Buffer_RAM_L (
   .DOA(),
   .DOB(Data_B_O[15:0]),
   .DOPA(),
   .DOPB(),
   .ADDRA(Address_A_I[9:0]),
   .ADDRB(Address_B_I[9:0]),
   .CLKA(in_clock),
   .CLKB(out_clock),
   .DIA(Data_A_I[15:0]),
   .DIB(16'h0000),
   .DIPA(2'b00),
   .DIPB(2'b00),
   .ENA(1'b1),
   .ENB(Enable_B_I),
   .SSRA(1'b0),
   .SSRB(1'b0),
   .WEA(Write_Enable_A_I),
   .WEB(1'b0)
);

endmodule
module System_Buffer(
   in_clock,
	out_clock,
   Address_A_I,
   Write_Enable_A_I,
   Data_A_I,
   Enable_B_I,
   Address_B_I,
   Data_B_O
);


input             in_clock;
input             out_clock;
input [`SYSTEM_BUFFER_ADDR_WIDTH-1:0] Address_A_I;
input             Write_Enable_A_I;
input    [31:0]   Data_A_I;
input             Enable_B_I;
input [`SYSTEM_BUFFER_ADDR_WIDTH-1:0] Address_B_I;
output   [31:0]   Data_B_O;

RAMB16_S18_S18 System_Buffer_RAM_H (
   .DOA(),
   .DOB(Data_B_O[31:16]),
   .DOPA(),
   .DOPB(),
   .ADDRA(Address_A_I[9:0]),
   .ADDRB(Address_B_I[9:0]),
   .CLKA(in_clock),
   .CLKB(out_clock),
   .DIA(Data_A_I[31:16]),
   .DIB(16'h0000),
   .DIPA(2'b00),
   .DIPB(2'b00),
   .ENA(1'b1),
   .ENB(Enable_B_I),
   .SSRA(1'b0),
   .SSRB(1'b0),
   .WEA(Write_Enable_A_I),
   .WEB(1'b0)
);

RAMB16_S18_S18 System_Buffer_RAM_L (
   .DOA(),
   .DOB(Data_B_O[15:0]),
   .DOPA(),
   .DOPB(),
   .ADDRA(Address_A_I[9:0]),
   .ADDRB(Address_B_I[9:0]),
   .CLKA(in_clock),
   .CLKB(out_clock),
   .DIA(Data_A_I[15:0]),
   .DIB(16'h0000),
   .DIPA(2'b00),
   .DIPB(2'b00),
   .ENA(1'b1),
   .ENB(Enable_B_I),
   .SSRA(1'b0),
   .SSRB(1'b0),
   .WEA(Write_Enable_A_I),
   .WEB(1'b0)
);

endmodule