data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/lutrams_map.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/lutrams_map.v:34: Multiple top level modules\n                                                                                                  : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                  : ... Top module \'$__XILINX_RAM16X1D\'\nmodule \\$__XILINX_RAM16X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);\n       ^~~~~~~~~~~~~~~~~~~\n                                                                                                  : ... Top module \'$__XILINX_RAM32X1D\'\nmodule \\$__XILINX_RAM32X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);\n       ^~~~~~~~~~~~~~~~~~~\n                                                                                                  : ... Top module \'$__XILINX_RAM64X1D\'\nmodule \\$__XILINX_RAM64X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);\n       ^~~~~~~~~~~~~~~~~~~\n                                                                                                  : ... Top module \'$__XILINX_RAM128X1D\'\nmodule \\$__XILINX_RAM128X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);\n       ^~~~~~~~~~~~~~~~~~~~\n                                                                                                  : ... Top module \'$__XILINX_RAM32X6SDP\'\nmodule \\$__XILINX_RAM32X6SDP (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);\n       ^~~~~~~~~~~~~~~~~~~~~\n                                                                                                  : ... Top module \'$__XILINX_RAM64X3SDP\'\nmodule \\$__XILINX_RAM64X3SDP (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);\n       ^~~~~~~~~~~~~~~~~~~~~\n                                                                                                  : ... Top module \'$__XILINX_RAM32X2Q\'\nmodule \\$__XILINX_RAM32X2Q (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, B1ADDR, B1DATA, B1EN);\n       ^~~~~~~~~~~~~~~~~~~\n                                                                                                  : ... Top module \'$__XILINX_RAM64X1Q\'\nmodule \\$__XILINX_RAM64X1Q (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, B1ADDR, B1DATA, B1EN);\n       ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/lutrams_map.v:257: Cannot find file containing module: \'RAM64M\'\n RAM64M #(\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx,data/full_repos/permissive/441359809/RAM64M\n             data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx,data/full_repos/permissive/441359809/RAM64M.v\n             data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx,data/full_repos/permissive/441359809/RAM64M.sv\n             RAM64M\n             RAM64M.v\n             RAM64M.sv\n             obj_dir/RAM64M\n             obj_dir/RAM64M.v\n             obj_dir/RAM64M.sv\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/lutrams_map.v:221: Cannot find file containing module: \'RAM32M\'\n RAM32M #(\n ^~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/lutrams_map.v:184: Cannot find file containing module: \'RAM64M\'\n RAM64M #(\n ^~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/lutrams_map.v:145: Cannot find file containing module: \'RAM32M\'\n RAM32M #(\n ^~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/lutrams_map.v:116: Cannot find file containing module: \'RAM128X1D\'\n RAM128X1D #(\n ^~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/lutrams_map.v:80: Cannot find file containing module: \'RAM64X1D\'\n RAM64X1D #(\n ^~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/lutrams_map.v:46: Cannot find file containing module: \'RAM32X1D\'\n RAM32X1D #(\n ^~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/lutrams_map.v:14: Cannot find file containing module: \'RAM16X1D\'\n RAM16X1D #(\n ^~~~~~~~\n%Error: Exiting due to 8 error(s), 1 warning(s)\n'
module \$__XILINX_RAM64X1Q (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, B1ADDR, B1DATA, B1EN);
	parameter [63:0] INIT = 64'bx;
	parameter CLKPOL2 = 1;
	input CLK1;

	input [5:0] A1ADDR, A2ADDR, A3ADDR;
	output A1DATA, A2DATA, A3DATA;

	input [5:0] B1ADDR;
	input B1DATA;
	input B1EN;

	RAM64M #(
		.INIT_A(INIT),
		.INIT_B(INIT),
		.INIT_C(INIT),
		.INIT_D(INIT),
		.IS_WCLK_INVERTED(!CLKPOL2)
	) _TECHMAP_REPLACE_ (
		.ADDRA(A1ADDR),
		.ADDRB(A2ADDR),
		.ADDRC(A3ADDR),
		.DOA(A1DATA),
		.DOB(A2DATA),
		.DOC(A3DATA),

		.ADDRD(B1ADDR),
		.DIA(B1DATA),
		.DIB(B1DATA),
		.DIC(B1DATA),
		.DID(B1DATA),
		.WCLK(CLK1),
		.WE(B1EN)
	);
endmodule
module \$__XILINX_RAM64X1Q (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, B1ADDR, B1DATA, B1EN);

	parameter [63:0] INIT = 64'bx;
	parameter CLKPOL2 = 1;
	input CLK1;

	input [5:0] A1ADDR, A2ADDR, A3ADDR;
	output A1DATA, A2DATA, A3DATA;

	input [5:0] B1ADDR;
	input B1DATA;
	input B1EN;

	RAM64M #(
		.INIT_A(INIT),
		.INIT_B(INIT),
		.INIT_C(INIT),
		.INIT_D(INIT),
		.IS_WCLK_INVERTED(!CLKPOL2)
	) _TECHMAP_REPLACE_ (
		.ADDRA(A1ADDR),
		.ADDRB(A2ADDR),
		.ADDRC(A3ADDR),
		.DOA(A1DATA),
		.DOB(A2DATA),
		.DOC(A3DATA),

		.ADDRD(B1ADDR),
		.DIA(B1DATA),
		.DIB(B1DATA),
		.DIC(B1DATA),
		.DID(B1DATA),
		.WCLK(CLK1),
		.WE(B1EN)
	);
endmodule