data/full_repos/permissive/516385853/kernel_bc/kernel_bc_start_for_write_back55_U0.v
1: b'%Warning-WIDTH: data/full_repos/permissive/516385853/kernel_bc/kernel_bc_start_for_write_back55_U0.v:29: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'DEPTH\' generates 3 bits.\n                                                                                                       : ... In instance kernel_bc_start_for_write_back55_U0.U_kernel_bc_start_for_write_back55_U0_ram\n            for (i=0;i<DEPTH-1;i=i+1)\n                            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module kernel_bc_start_for_write_back55_U0_shiftReg (
    clk,
    data,
    ce,
    a,
    q);

parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 3'd4;

input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;

reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;

always @ (posedge clk)
    begin
        if (ce)
        begin
            for (i=0;i<DEPTH-1;i=i+1)
                SRL_SIG[i+1] <= SRL_SIG[i];
            SRL_SIG[0] <= data;
        end
    end

assign q = SRL_SIG[a];

endmodule
module kernel_bc_start_for_write_back55_U0_shiftReg (
    clk,
    data,
    ce,
    a,
    q);


parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 3'd4;

input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;

reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;

always @ (posedge clk)
    begin
        if (ce)
        begin
            for (i=0;i<DEPTH-1;i=i+1)
                SRL_SIG[i+1] <= SRL_SIG[i];
            SRL_SIG[0] <= data;
        end
    end

assign q = SRL_SIG[a];

endmodule