data/full_repos/permissive/423547971/Verilog Introductory Tutorial Book/D_ff_TB.v
1: b'%Error: Cannot find file containing module: Introductory\n        ... Looked in:\n             data/full_repos/permissive/423547971/Verilog/Introductory\n             data/full_repos/permissive/423547971/Verilog/Introductory.v\n             data/full_repos/permissive/423547971/Verilog/Introductory.sv\n             Introductory\n             Introductory.v\n             Introductory.sv\n             obj_dir/Introductory\n             obj_dir/Introductory.v\n             obj_dir/Introductory.sv\n%Error: Cannot find file containing module: Tutorial\n%Error: Cannot find file containing module: Book,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/Verilog\n%Error: Cannot find file containing module: Book/D_ff_TB.v\n%Error: Exiting due to 5 error(s)\n'
module D_ff_TB();	

reg CLOCK, D;				

wire Q, Q_not;		


D_ff D1(
	.CLOCK(CLOCK),
	.D(D),
	.Q(Q),
	.Q_not(Q_not)
);


always begin
	#10 CLOCK = !CLOCK; 
  end


initial begin
	CLOCK = 0;
	D = 0;
	
	#50
	D = 1;
	
	#100	
	D = 0;
	
	#20
	D = 1;

	#40
	D = 0;
	
	#1000 $finish;	
  end
  

initial begin
    $dumpfile("D_ff_TB.vcd");
	$dumpvars(0, D_ff_TB);
  end
  
endmodule
module D_ff_TB();
	

reg CLOCK, D;				

wire Q, Q_not;		


D_ff D1(
	.CLOCK(CLOCK),
	.D(D),
	.Q(Q),
	.Q_not(Q_not)
);


always begin
	#10 CLOCK = !CLOCK; 
  end


initial begin
	CLOCK = 0;
	D = 0;
	
	#50
	D = 1;
	
	#100	
	D = 0;
	
	#20
	D = 1;

	#40
	D = 0;
	
	#1000 $finish;	
  end
  

initial begin
    $dumpfile("D_ff_TB.vcd");
	$dumpvars(0, D_ff_TB);
  end
  
endmodule