data/full_repos/permissive/507850313/rtl/core/core.v
1: b'%Error: data/full_repos/permissive/507850313/rtl/core/core.v:17: Cannot find include file: core_defines.v\n`include "core_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507850313/rtl/core,data/full_repos/permissive/507850313/core_defines.v\n             data/full_repos/permissive/507850313/rtl/core,data/full_repos/permissive/507850313/core_defines.v.v\n             data/full_repos/permissive/507850313/rtl/core,data/full_repos/permissive/507850313/core_defines.v.sv\n             core_defines.v\n             core_defines.v.v\n             core_defines.v.sv\n             obj_dir/core_defines.v\n             obj_dir/core_defines.v.v\n             obj_dir/core_defines.v.sv\n%Error: data/full_repos/permissive/507850313/rtl/core/core.v:24: Define or directive not defined: \'`CPU_PC_SIZE\'\n    output [`CPU_PC_SIZE-1:0]    ifu_pc_addr,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core.v:25: Define or directive not defined: \'`CPU_INSTR_SIZE\'\n    input  [`CPU_INSTR_SIZE-1:0] ifu_instr_fetched,\n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core.v:33: Define or directive not defined: \'`CPU_PC_SIZE\'\nwire [`CPU_PC_SIZE-1:0]       if2id_pc,\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core.v:34: syntax error, unexpected wire, expecting IDENTIFIER or do or final\nwire [`CPU_INSTR_SIZE-1:0]    if2id_instr,\n^~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core.v:34: Define or directive not defined: \'`CPU_INSTR_SIZE\'\nwire [`CPU_INSTR_SIZE-1:0]    if2id_instr,\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core.v:35: Define or directive not defined: \'`CPU_PC_SIZE\'\nwire [`CPU_PC_SIZE-1:0]       id2ex_pc,\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core.v:36: Define or directive not defined: \'`CPU_INSTR_SIZE\'\nwire [`CPU_INSTR_SIZE-1:0]    id2ex_instr,\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core.v:37: Define or directive not defined: \'`CPU_RFIDX_WIDTH\'\nwire [`CPU_RFIDX_WIDTH-1:0]   id2ex_rs1_idx,\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core.v:38: Define or directive not defined: \'`CPU_RFIDX_WIDTH\'\nwire [`CPU_RFIDX_WIDTH-1:0]   id2ex_rs2_idx,\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core.v:39: Define or directive not defined: \'`CPU_RFIDX_WIDTH\'\nwire [`CPU_RFIDX_WIDTH-1:0]   id2ex_rsd_idx,\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core.v:40: Define or directive not defined: \'`CPU_XLEN\'\nwire [`CPU_XLEN-1:0]          id2ex_rs1_data,\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core.v:41: Define or directive not defined: \'`CPU_XLEN\'\nwire [`CPU_XLEN-1:0]          id2ex_rs2_data,\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core.v:42: Define or directive not defined: \'`CPU_PC_SIZE\'\nwire [`CPU_PC_SIZE-1:0]       ex2mem_pc,\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core.v:43: Define or directive not defined: \'`CPU_INSTR_SIZE\'\nwire [`CPU_INSTR_SIZE-1:0]    ex2mem_instr,\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core.v:44: Define or directive not defined: \'`CPU_RFIDX_WIDTH\'\nwire [`CPU_RFIDX_WIDTH-1:0]   ex2mem_rs1_idx,\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core.v:45: Define or directive not defined: \'`CPU_RFIDX_WIDTH\'\nwire [`CPU_RFIDX_WIDTH-1:0]   ex2mem_rs2_idx,\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core.v:46: Define or directive not defined: \'`CPU_RFIDX_WIDTH\'\nwire [`CPU_RFIDX_WIDTH-1:0]   ex2mem_rsd_idx,\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core.v:47: Define or directive not defined: \'`CPU_XLEN\'\nwire [`CPU_XLEN-1:0]          ex2mem_rs1_data,\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core.v:48: Define or directive not defined: \'`CPU_XLEN\'\nwire [`CPU_XLEN-1:0]          ex2mem_rs2_data,\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core.v:49: Define or directive not defined: \'`CPU_XLEN\'\nwire [`CPU_XLEN-1:0]          ex2mem_rsd_data,\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core.v:50: Define or directive not defined: \'`CPU_PC_SIZE\'\nwire [`CPU_PC_SIZE-1:0]       mem2wb_pc,\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core.v:51: Define or directive not defined: \'`CPU_INSTR_SIZE\'\nwire [`CPU_INSTR_SIZE-1:0]    mem2wb_instr,\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core.v:52: Define or directive not defined: \'`CPU_RFIDX_WIDTH\'\nwire [`CPU_RFIDX_WIDTH-1:0]   mem2wb_rs1_idx,\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core.v:53: Define or directive not defined: \'`CPU_RFIDX_WIDTH\'\nwire [`CPU_RFIDX_WIDTH-1:0]   mem2wb_rs2_idx,\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core.v:54: Define or directive not defined: \'`CPU_RFIDX_WIDTH\'\nwire [`CPU_RFIDX_WIDTH-1:0]   mem2wb_rsd_idx,\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core.v:55: Define or directive not defined: \'`CPU_XLEN\'\nwire [`CPU_XLEN-1:0]          mem2wb_rs1_data,\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core.v:56: Define or directive not defined: \'`CPU_XLEN\'\nwire [`CPU_XLEN-1:0]          mem2wb_rs2_data,\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/507850313/rtl/core/core.v:57: Define or directive not defined: \'`CPU_XLEN\'\nwire [`CPU_XLEN-1:0]          mem2wb_rsd_data,\n      ^~~~~~~~~\n%Error: Exiting due to 29 error(s)\n'
module core #(

) (


    output [`CPU_PC_SIZE-1:0]    ifu_pc_addr,
    input  [`CPU_INSTR_SIZE-1:0] ifu_instr_fetched,


    input clk,
    input rst_n
);


wire [`CPU_PC_SIZE-1:0]       if2id_pc,
wire [`CPU_INSTR_SIZE-1:0]    if2id_instr,
wire [`CPU_PC_SIZE-1:0]       id2ex_pc,
wire [`CPU_INSTR_SIZE-1:0]    id2ex_instr,
wire [`CPU_RFIDX_WIDTH-1:0]   id2ex_rs1_idx,
wire [`CPU_RFIDX_WIDTH-1:0]   id2ex_rs2_idx,
wire [`CPU_RFIDX_WIDTH-1:0]   id2ex_rsd_idx,
wire [`CPU_XLEN-1:0]          id2ex_rs1_data,
wire [`CPU_XLEN-1:0]          id2ex_rs2_data,
wire [`CPU_PC_SIZE-1:0]       ex2mem_pc,
wire [`CPU_INSTR_SIZE-1:0]    ex2mem_instr,
wire [`CPU_RFIDX_WIDTH-1:0]   ex2mem_rs1_idx,
wire [`CPU_RFIDX_WIDTH-1:0]   ex2mem_rs2_idx,
wire [`CPU_RFIDX_WIDTH-1:0]   ex2mem_rsd_idx,
wire [`CPU_XLEN-1:0]          ex2mem_rs1_data,
wire [`CPU_XLEN-1:0]          ex2mem_rs2_data,
wire [`CPU_XLEN-1:0]          ex2mem_rsd_data,
wire [`CPU_PC_SIZE-1:0]       mem2wb_pc,
wire [`CPU_INSTR_SIZE-1:0]    mem2wb_instr,
wire [`CPU_RFIDX_WIDTH-1:0]   mem2wb_rs1_idx,
wire [`CPU_RFIDX_WIDTH-1:0]   mem2wb_rs2_idx,
wire [`CPU_RFIDX_WIDTH-1:0]   mem2wb_rsd_idx,
wire [`CPU_XLEN-1:0]          mem2wb_rs1_data,
wire [`CPU_XLEN-1:0]          mem2wb_rs2_data,
wire [`CPU_XLEN-1:0]          mem2wb_rsd_data,


core_ifu u_core_ifu(
    .pc_addr          (ifu_pc_addr       ),
    .instr_fetched    (ifu_instr_fetched ),
    .pc_o             (if2id_pc          ),
    .instr_o          (if2id_instr       ),

    .clk              (clk           ),
    .rst_n            (rst_n         )
);


core_idu u_core_idu(
    .pc_i             (if2id_pc         ),
    .instr_i          (if2id_instr      ),

    .pc_o             (id2ex_pc         ),
    .instr_o          (id2ex_instr      ),
    .rs1_idx_o        (id2ex_rs1_idx    ),
    .rs2_idx_o        (id2ex_rs2_idx    ),
    .rsd_idx_o        (id2ex_rsd_idx    ),
    .rs1_data_o       (id2ex_rs1_data   ),
    .rs2_data_o       (id2ex_rs2_data   ),

    .clk              (clk        ),
    .rst_n            (rst_n      )
);


core_exu u_core_exu(
    .pc_i             (id2ex_pc         ),
    .instr_i          (id2ex_instr      ),
    .rs1_idx_i        (id2ex_rs1_idx    ),
    .rs2_idx_i        (id2ex_rs2_idx    ),
    .rsd_idx_i        (id2ex_rsd_idx    ),
    .rs1_data_i       (id2ex_rs1_data   ),
    .rs2_data_i       (id2ex_rs2_data   ),

    .pc_o             (ex2mem_pc       ),
    .instr_o          (ex2mem_instr    ),
    .rs1_idx_o        (ex2mem_rs1_idx  ),
    .rs2_idx_o        (ex2mem_rs2_idx  ),
    .rsd_idx_o        (ex2mem_rsd_idx  ),
    .rs1_data_o       (ex2mem_rs1_data ),
    .rs2_data_o       (ex2mem_rs2_data ),
    .rsd_data_o       (ex2mem_rsd_data ),

    .clk              (clk        ),
    .rst_n            (rst_n      )
);

core_mem u_core_mem(
    .pc_i             (ex2mem_pc         ),
    .instr_i          (ex2mem_instr      ),
    .rs1_idx_i        (ex2mem_rs1_idx    ),
    .rs2_idx_i        (ex2mem_rs2_idx    ),
    .rsd_idx_i        (ex2mem_rsd_idx    ),
    .rs1_data_i       (ex2mem_rs1_data   ),
    .rs2_data_i       (ex2mem_rs2_data   ),
    .rsd_data_i       (ex2mem_rsd_data   ),

    .pc_o             (mem2wb_pc         ),
    .instr_o          (mem2wb_instr      ),
    .rs1_idx_o        (mem2wb_rs1_idx    ),
    .rs2_idx_o        (mem2wb_rs2_idx    ),
    .rsd_idx_o        (mem2wb_rsd_idx    ),
    .rs1_data_o       (mem2wb_rs1_data   ),
    .rs2_data_o       (mem2wb_rs2_data   ),
    .rsd_data_o       (mem2wb_rsd_data   ),

    .clk              (clk        ),
    .rst_n            (rst_n      )
);

core_wb u_core_wb(
    .pc_i             (mem2wb_pc         ),
    .instr_i          (mem2wb_instr      ),
    .rs1_idx_i        (mem2wb_rs1_idx    ),
    .rs2_idx_i        (mem2wb_rs2_idx    ),
    .rsd_idx_i        (mem2wb_rsd_idx    ),
    .rs1_data_i       (mem2wb_rs1_data   ),
    .rs2_data_i       (mem2wb_rs2_data   ),
    .rsd_data_i       (mem2wb_rsd_data   ),

    .clk              (clk        ),
    .rst_n            (rst_n      )
);

core_regfile u_core_regfile(

    .clk              (clk   ),
    .rst_n            (rst_n )
);


    
endmodule
module core #(

) (


    output [`CPU_PC_SIZE-1:0]    ifu_pc_addr,
    input  [`CPU_INSTR_SIZE-1:0] ifu_instr_fetched,


    input clk,
    input rst_n
);



wire [`CPU_PC_SIZE-1:0]       if2id_pc,
wire [`CPU_INSTR_SIZE-1:0]    if2id_instr,
wire [`CPU_PC_SIZE-1:0]       id2ex_pc,
wire [`CPU_INSTR_SIZE-1:0]    id2ex_instr,
wire [`CPU_RFIDX_WIDTH-1:0]   id2ex_rs1_idx,
wire [`CPU_RFIDX_WIDTH-1:0]   id2ex_rs2_idx,
wire [`CPU_RFIDX_WIDTH-1:0]   id2ex_rsd_idx,
wire [`CPU_XLEN-1:0]          id2ex_rs1_data,
wire [`CPU_XLEN-1:0]          id2ex_rs2_data,
wire [`CPU_PC_SIZE-1:0]       ex2mem_pc,
wire [`CPU_INSTR_SIZE-1:0]    ex2mem_instr,
wire [`CPU_RFIDX_WIDTH-1:0]   ex2mem_rs1_idx,
wire [`CPU_RFIDX_WIDTH-1:0]   ex2mem_rs2_idx,
wire [`CPU_RFIDX_WIDTH-1:0]   ex2mem_rsd_idx,
wire [`CPU_XLEN-1:0]          ex2mem_rs1_data,
wire [`CPU_XLEN-1:0]          ex2mem_rs2_data,
wire [`CPU_XLEN-1:0]          ex2mem_rsd_data,
wire [`CPU_PC_SIZE-1:0]       mem2wb_pc,
wire [`CPU_INSTR_SIZE-1:0]    mem2wb_instr,
wire [`CPU_RFIDX_WIDTH-1:0]   mem2wb_rs1_idx,
wire [`CPU_RFIDX_WIDTH-1:0]   mem2wb_rs2_idx,
wire [`CPU_RFIDX_WIDTH-1:0]   mem2wb_rsd_idx,
wire [`CPU_XLEN-1:0]          mem2wb_rs1_data,
wire [`CPU_XLEN-1:0]          mem2wb_rs2_data,
wire [`CPU_XLEN-1:0]          mem2wb_rsd_data,


core_ifu u_core_ifu(
    .pc_addr          (ifu_pc_addr       ),
    .instr_fetched    (ifu_instr_fetched ),
    .pc_o             (if2id_pc          ),
    .instr_o          (if2id_instr       ),

    .clk              (clk           ),
    .rst_n            (rst_n         )
);


core_idu u_core_idu(
    .pc_i             (if2id_pc         ),
    .instr_i          (if2id_instr      ),

    .pc_o             (id2ex_pc         ),
    .instr_o          (id2ex_instr      ),
    .rs1_idx_o        (id2ex_rs1_idx    ),
    .rs2_idx_o        (id2ex_rs2_idx    ),
    .rsd_idx_o        (id2ex_rsd_idx    ),
    .rs1_data_o       (id2ex_rs1_data   ),
    .rs2_data_o       (id2ex_rs2_data   ),

    .clk              (clk        ),
    .rst_n            (rst_n      )
);


core_exu u_core_exu(
    .pc_i             (id2ex_pc         ),
    .instr_i          (id2ex_instr      ),
    .rs1_idx_i        (id2ex_rs1_idx    ),
    .rs2_idx_i        (id2ex_rs2_idx    ),
    .rsd_idx_i        (id2ex_rsd_idx    ),
    .rs1_data_i       (id2ex_rs1_data   ),
    .rs2_data_i       (id2ex_rs2_data   ),

    .pc_o             (ex2mem_pc       ),
    .instr_o          (ex2mem_instr    ),
    .rs1_idx_o        (ex2mem_rs1_idx  ),
    .rs2_idx_o        (ex2mem_rs2_idx  ),
    .rsd_idx_o        (ex2mem_rsd_idx  ),
    .rs1_data_o       (ex2mem_rs1_data ),
    .rs2_data_o       (ex2mem_rs2_data ),
    .rsd_data_o       (ex2mem_rsd_data ),

    .clk              (clk        ),
    .rst_n            (rst_n      )
);

core_mem u_core_mem(
    .pc_i             (ex2mem_pc         ),
    .instr_i          (ex2mem_instr      ),
    .rs1_idx_i        (ex2mem_rs1_idx    ),
    .rs2_idx_i        (ex2mem_rs2_idx    ),
    .rsd_idx_i        (ex2mem_rsd_idx    ),
    .rs1_data_i       (ex2mem_rs1_data   ),
    .rs2_data_i       (ex2mem_rs2_data   ),
    .rsd_data_i       (ex2mem_rsd_data   ),

    .pc_o             (mem2wb_pc         ),
    .instr_o          (mem2wb_instr      ),
    .rs1_idx_o        (mem2wb_rs1_idx    ),
    .rs2_idx_o        (mem2wb_rs2_idx    ),
    .rsd_idx_o        (mem2wb_rsd_idx    ),
    .rs1_data_o       (mem2wb_rs1_data   ),
    .rs2_data_o       (mem2wb_rs2_data   ),
    .rsd_data_o       (mem2wb_rsd_data   ),

    .clk              (clk        ),
    .rst_n            (rst_n      )
);

core_wb u_core_wb(
    .pc_i             (mem2wb_pc         ),
    .instr_i          (mem2wb_instr      ),
    .rs1_idx_i        (mem2wb_rs1_idx    ),
    .rs2_idx_i        (mem2wb_rs2_idx    ),
    .rsd_idx_i        (mem2wb_rsd_idx    ),
    .rs1_data_i       (mem2wb_rs1_data   ),
    .rs2_data_i       (mem2wb_rs2_data   ),
    .rsd_data_i       (mem2wb_rsd_data   ),

    .clk              (clk        ),
    .rst_n            (rst_n      )
);

core_regfile u_core_regfile(

    .clk              (clk   ),
    .rst_n            (rst_n )
);


    
endmodule