data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/MICROBENCHMARKS/bm_dag2_log.v
data/verilator_xmls/0cfd6e35-eb35-4d07-b47e-f07c00680c23.xml
module 	bm_dag2_log(clock, 
		reset_n, 
		a_in, 
		b_in, 
		out);


input	clock;
input 	reset_n;

input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;

output [`BITS-1:0] out;

wire [`BITS-1:0]    out;
wire [`BITS-1:0]    temp1;
wire [`BITS-1:0]    temp2;
wire [`BITS-1:0]    temp3;


assign out = temp1 & temp2;
assign temp1 = a_in | b_in;
assign temp2 = temp1 ^ b_in;

endmodule
module 	bm_dag2_log(clock, 
		reset_n, 
		a_in, 
		b_in, 
		out);



input	clock;
input 	reset_n;

input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;

output [`BITS-1:0] out;

wire [`BITS-1:0]    out;
wire [`BITS-1:0]    temp1;
wire [`BITS-1:0]    temp2;
wire [`BITS-1:0]    temp3;


assign out = temp1 & temp2;
assign temp1 = a_in | b_in;
assign temp2 = temp1 ^ b_in;

endmodule