data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/Or32B5Way.v
data/verilator_xmls/d4170423-60f1-40fd-b883-8a64f39e2f80.xml
module Or32B5Way(
    input [31:0] aIn,
    input [31:0] bIn,
    input [31:0] cIn,
    input [31:0] dIn,
    input [31:0] eIn,
    output [31:0] dOut
  );
  


  genvar i;
  generate
  for (i = 0; i < 32; i = i + 1) begin : or32loop
    assign dOut[i] = aIn[i] | bIn[i] | cIn[i] | dIn[i] | eIn[i];
  end
  endgenerate
  
endmodule
module Or32B5Way(
    input [31:0] aIn,
    input [31:0] bIn,
    input [31:0] cIn,
    input [31:0] dIn,
    input [31:0] eIn,
    output [31:0] dOut
  );

  


  genvar i;
  generate
  for (i = 0; i < 32; i = i + 1) begin : or32loop
    assign dOut[i] = aIn[i] | bIn[i] | cIn[i] | dIn[i] | eIn[i];
  end
  endgenerate
  
endmodule