data/full_repos/permissive/518669498/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/518669498/verilog/rtl/user_proj_example.v:868: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/518669498/verilog/rtl/user_proj_example.v:869: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/518669498/verilog/rtl/user_proj_example.v:870: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/518669498/verilog/rtl/user_proj_example.v:878: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_in;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/518669498/verilog/rtl/user_proj_example.v:879: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_out;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/518669498/verilog/rtl/user_proj_example.v:880: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_oeb;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/518669498/verilog/rtl/user_proj_example.v:898: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};\n                      ^~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module mul2x2(
  input  [1:0] a,
  input  [1:0] b,
  output [3:0] c
);

  wire [3:0] tmp;

  assign tmp[0] = a[0] & b[0];
  assign tmp[1] = (a[1]&b[0]) ^ (a[0]&b[1]);
  assign tmp[2] = (a[0]&b[1]) & (a[1]&b[0]) ^ (a[1]&b[1]);
  assign tmp[3] = (a[0]&b[1]) & (a[1]&b[0]) & (a[1]&b[1]);
  assign c 	= {tmp[3],tmp[2],tmp[1],tmp[0]};

endmodule
module mul2x2(
  input  [1:0] a,
  input  [1:0] b,
  output [3:0] c
);


  wire [3:0] tmp;

  assign tmp[0] = a[0] & b[0];
  assign tmp[1] = (a[1]&b[0]) ^ (a[0]&b[1]);
  assign tmp[2] = (a[0]&b[1]) & (a[1]&b[0]) ^ (a[1]&b[1]);
  assign tmp[3] = (a[0]&b[1]) & (a[1]&b[0]) & (a[1]&b[1]);
  assign c 	= {tmp[3],tmp[2],tmp[1],tmp[0]};

endmodule