data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_rx_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_rx_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n   initial #1000 reset = 0;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_rx_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n   always #50 clk = ~clk;\n          ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_rx_tb.v:32: Unsupported or unknown PLI call: $dumpfile\n   initial $dumpfile("vita_rx_tb.vcd");\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_rx_tb.v:33: Unsupported or unknown PLI call: $dumpvars\n   initial $dumpvars(0,vita_rx_tb);\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_rx_tb.v:110: syntax error, unexpected \'@\'\n @(negedge reset);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_rx_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n #10000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_rx_tb.v:174: Unsupported: Ignoring delay on this delayed statement.\n #100000 $finish;\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_rx_tb.v:182: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_rx_tb.v:186: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: Exiting due to 5 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module vita_rx_tb;

   localparam DECIM  = 8'd4;
   localparam MAXCHAN=1;
   localparam NUMCHAN=1;
   
   reg clk 	     = 0;
   reg reset 	     = 1;

   initial #1000 reset = 0;
   always #50 clk = ~clk;

   initial $dumpfile("vita_rx_tb.vcd");
   initial $dumpvars(0,vita_rx_tb);

   wire [(MAXCHAN*32)-1:0] sample;
   wire        strobe, run;
   wire [35:0] data_o;
   wire        src_rdy;
   reg 	       dst_rdy = 1;
   wire [63:0] vita_time;

   reg 	       set_stb = 0;
   reg [7:0]   set_addr;
   reg [31:0]  set_data;
   wire        set_stb_dsp;
   wire [7:0]  set_addr_dsp;
   wire [31:0] set_data_dsp;


   
   wire        sample_dst_rdy, sample_src_rdy;

   wire [64+5+(MAXCHAN*32)-1:0] sample_data_o;

   vita_rx_control #(.BASE(0), .WIDTH(32*MAXCHAN)) vita_rx_control
     (.clk(clk), .reset(reset), .clear(0),
      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
      .vita_time(vita_time), .overrun(overrun),
      .sample_fifo_o(sample_data_o), .sample_fifo_dst_rdy_i(sample_dst_rdy), .sample_fifo_src_rdy_o(sample_src_rdy),
      .sample(sample), .run(run), .strobe(strobe));

   vita_rx_framer #(.BASE(0), .MAXCHAN(MAXCHAN)) vita_rx_framer
     (.clk(clk), .reset(reset), .clear(0),
      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
      .data_o(data_o), .dst_rdy_i(dst_rdy), .src_rdy_o(src_rdy),
      .sample_fifo_i(sample_data_o), .sample_fifo_dst_rdy_o(sample_dst_rdy), .sample_fifo_src_rdy_i(sample_src_rdy),
      .fifo_occupied(), .fifo_full(), .fifo_empty() );
   
   rx_dsp_model rx_dsp_model
     (.clk(clk), .reset(reset), .run(run), .decim(DECIM), .strobe(strobe), .sample(sample[31:0]));

   generate
      if(MAXCHAN>1)
	assign sample[(MAXCHAN*32)-1:32] = 0;
   endgenerate
   
   time_64bit #(.TICKS_PER_SEC(120000000), .BASE(0)) time_64bit
     (.clk(clk), .rst(reset),
      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
      .pps(0), .vita_time(vita_time));
   
   always @(posedge clk)
     if(src_rdy & dst_rdy)
       begin
	  if(data_o[32] & ~data_o[33])
	    begin
	       $display("RX-PKT-START %d",$time);
	       $display("       RX-PKT-DAT %x",data_o[31:0]);
	    end
	  else if(data_o[32] & data_o[33])
	    begin
	       $display("       RX-PKT-DAT %x -- With ERR",data_o[31:0]);
	       $display("RX-PKT-ERR %d",$time);
	    end
	  else if(~data_o[32] & data_o[33])
	    begin
	       $display("       RX-PKT-DAT %x",data_o[31:0]);
	       $display("RX-PKT-END %d",$time);
	    end
	  else
	    $display("       RX-PKT DAT %x",data_o[31:0]);
       end

   initial 
     begin
	@(negedge reset);
	@(posedge clk);
	write_setting(4,32'h15F00000);
	write_setting(5,32'hF00D1234);
	write_setting(6,32'hE0000000);
	write_setting(7,8);
	write_setting(8,NUMCHAN);

	queue_rx_cmd(1,1,0,10,32'h0,32'h0);
	#10000;
	
	queue_rx_cmd(1,0,0,0,32'h0,32'h0);

	

	

	#100000 $finish;
     end

   task write_setting;
      input [7:0] addr;
      input [31:0] data;
      begin
	 set_stb <= 0;
	 @(posedge clk);
	 set_addr <= addr;
	 set_data <= data;
	 set_stb  <= 1;
	 @(posedge clk);
	 set_stb <= 0;
      end
   endtask
   
   task queue_rx_cmd;
      input send_imm;
      input chain;
      input reload;
      input [28:0] lines;
      input [31:0] secs;
      input [31:0] tics;
      begin
	 write_setting(0,{send_imm,chain,reload,lines});
	 write_setting(1,secs);
	 write_setting(2,tics);
      end
   endtask
   
endmodule
module vita_rx_tb;


   localparam DECIM  = 8'd4;
   localparam MAXCHAN=1;
   localparam NUMCHAN=1;
   
   reg clk 	     = 0;
   reg reset 	     = 1;

   initial #1000 reset = 0;
   always #50 clk = ~clk;

   initial $dumpfile("vita_rx_tb.vcd");
   initial $dumpvars(0,vita_rx_tb);

   wire [(MAXCHAN*32)-1:0] sample;
   wire        strobe, run;
   wire [35:0] data_o;
   wire        src_rdy;
   reg 	       dst_rdy = 1;
   wire [63:0] vita_time;

   reg 	       set_stb = 0;
   reg [7:0]   set_addr;
   reg [31:0]  set_data;
   wire        set_stb_dsp;
   wire [7:0]  set_addr_dsp;
   wire [31:0] set_data_dsp;


   
   wire        sample_dst_rdy, sample_src_rdy;

   wire [64+5+(MAXCHAN*32)-1:0] sample_data_o;

   vita_rx_control #(.BASE(0), .WIDTH(32*MAXCHAN)) vita_rx_control
     (.clk(clk), .reset(reset), .clear(0),
      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
      .vita_time(vita_time), .overrun(overrun),
      .sample_fifo_o(sample_data_o), .sample_fifo_dst_rdy_i(sample_dst_rdy), .sample_fifo_src_rdy_o(sample_src_rdy),
      .sample(sample), .run(run), .strobe(strobe));

   vita_rx_framer #(.BASE(0), .MAXCHAN(MAXCHAN)) vita_rx_framer
     (.clk(clk), .reset(reset), .clear(0),
      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
      .data_o(data_o), .dst_rdy_i(dst_rdy), .src_rdy_o(src_rdy),
      .sample_fifo_i(sample_data_o), .sample_fifo_dst_rdy_o(sample_dst_rdy), .sample_fifo_src_rdy_i(sample_src_rdy),
      .fifo_occupied(), .fifo_full(), .fifo_empty() );
   
   rx_dsp_model rx_dsp_model
     (.clk(clk), .reset(reset), .run(run), .decim(DECIM), .strobe(strobe), .sample(sample[31:0]));

   generate
      if(MAXCHAN>1)
	assign sample[(MAXCHAN*32)-1:32] = 0;
   endgenerate
   
   time_64bit #(.TICKS_PER_SEC(120000000), .BASE(0)) time_64bit
     (.clk(clk), .rst(reset),
      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
      .pps(0), .vita_time(vita_time));
   
   always @(posedge clk)
     if(src_rdy & dst_rdy)
       begin
	  if(data_o[32] & ~data_o[33])
	    begin
	       $display("RX-PKT-START %d",$time);
	       $display("       RX-PKT-DAT %x",data_o[31:0]);
	    end
	  else if(data_o[32] & data_o[33])
	    begin
	       $display("       RX-PKT-DAT %x -- With ERR",data_o[31:0]);
	       $display("RX-PKT-ERR %d",$time);
	    end
	  else if(~data_o[32] & data_o[33])
	    begin
	       $display("       RX-PKT-DAT %x",data_o[31:0]);
	       $display("RX-PKT-END %d",$time);
	    end
	  else
	    $display("       RX-PKT DAT %x",data_o[31:0]);
       end

   initial 
     begin
	@(negedge reset);
	@(posedge clk);
	write_setting(4,32'h15F00000);
	write_setting(5,32'hF00D1234);
	write_setting(6,32'hE0000000);
	write_setting(7,8);
	write_setting(8,NUMCHAN);

	queue_rx_cmd(1,1,0,10,32'h0,32'h0);
	#10000;
	
	queue_rx_cmd(1,0,0,0,32'h0,32'h0);

	

	

	#100000 $finish;
     end

   task write_setting;
      input [7:0] addr;
      input [31:0] data;
      begin
	 set_stb <= 0;
	 @(posedge clk);
	 set_addr <= addr;
	 set_data <= data;
	 set_stb  <= 1;
	 @(posedge clk);
	 set_stb <= 0;
      end
   endtask
   
   task queue_rx_cmd;
      input send_imm;
      input chain;
      input reload;
      input [28:0] lines;
      input [31:0] secs;
      input [31:0] tics;
      begin
	 write_setting(0,{send_imm,chain,reload,lines});
	 write_setting(1,secs);
	 write_setting(2,tics);
      end
   endtask
   
endmodule