data/full_repos/permissive/42434302/ivltests/memsynth3.v
1: b'%Error: data/full_repos/permissive/42434302/ivltests/memsynth3.v:6: syntax error, unexpected bit, expecting IDENTIFIER or \'=\' or do or final\n   reg      bit, rst, clk;\n            ^~~\n%Error: data/full_repos/permissive/42434302/ivltests/memsynth3.v:18: syntax error, unexpected \';\', expecting "\'{"\n foo[adr] <= bit;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/memsynth3.v:30: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/memsynth3.v:31: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/memsynth3.v:43: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/memsynth3.v:44: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/memsynth3.v:54: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/memsynth3.v:55: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 0;\n      ^\n%Error: data/full_repos/permissive/42434302/ivltests/memsynth3.v:62: syntax error, unexpected \'=\', expecting "\'{"\n      bit = 1;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/memsynth3.v:66: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/memsynth3.v:67: Unsupported: Ignoring delay on this delayed statement.\n      #1 clk = 0;\n      ^\n%Error: data/full_repos/permissive/42434302/ivltests/memsynth3.v:70: syntax error, unexpected \')\', expecting "\'{"\n  $display("FAILED -- foo=%b, adr=%b, bit=%b", foo, adr, bit);\n                                                            ^\n%Error: Exiting due to 4 error(s), 8 warning(s)\n'
module main;

   reg [3:0] foo, bar;
   reg [1:0] adr;

   reg	     bit, rst, clk;
   reg	     load_enable, write_enable;

   (* ivl_synthesis_on *)
   always @(posedge clk or posedge rst)
     if (rst) begin
	foo <= 0;

     end else if (load_enable) begin
	foo <= bar;

     end else if (write_enable) begin
	foo[adr] <= bit;

     end

   (* ivl_synthesis_off *)
   initial begin
      rst = 1;
      clk = 0;
      bar = 4'bzzzz;
      load_enable = 0;
      write_enable = 0;

      #1 clk = 1;
      #1 clk = 0;

      if (foo !== 4'b0000) begin
	 $display("FAILED -- reset foo=%b", foo);
	 $finish;
      end

      rst = 0;
      bar = 4'b1001;
      load_enable = 1;
      write_enable = 0;

      #1 clk = 1;
      #1 clk = 0;

      if (foo !== bar) begin
	 $display("FAILED -- load foo=%b, bar=%b", foo, bar);
	 $finish;
      end

      load_enable = 0;
      write_enable = 0;

      #1 clk = 1;
      #1 clk = 0;
      if (foo !== 4'b1001) begin
	 $display("FAILED -- foo=%b after clk", foo);
	 $finish;
      end

      adr = 1;
      bit = 1;
      load_enable = 0;
      write_enable = 1;

      #1 clk = 1;
      #1 clk = 0;

      if (foo !== 4'b1011) begin
	 $display("FAILED -- foo=%b, adr=%b, bit=%b", foo, adr, bit);
	 $finish;
      end

      $display("PASSED");
      $finish;
   end

endmodule
module main;


   reg [3:0] foo, bar;
   reg [1:0] adr;

   reg	     bit, rst, clk;
   reg	     load_enable, write_enable;

   (* ivl_synthesis_on *)
   always @(posedge clk or posedge rst)
     if (rst) begin
	foo <= 0;

     end else if (load_enable) begin
	foo <= bar;

     end else if (write_enable) begin
	foo[adr] <= bit;

     end

   (* ivl_synthesis_off *)
   initial begin
      rst = 1;
      clk = 0;
      bar = 4'bzzzz;
      load_enable = 0;
      write_enable = 0;

      #1 clk = 1;
      #1 clk = 0;

      if (foo !== 4'b0000) begin
	 $display("FAILED -- reset foo=%b", foo);
	 $finish;
      end

      rst = 0;
      bar = 4'b1001;
      load_enable = 1;
      write_enable = 0;

      #1 clk = 1;
      #1 clk = 0;

      if (foo !== bar) begin
	 $display("FAILED -- load foo=%b, bar=%b", foo, bar);
	 $finish;
      end

      load_enable = 0;
      write_enable = 0;

      #1 clk = 1;
      #1 clk = 0;
      if (foo !== 4'b1001) begin
	 $display("FAILED -- foo=%b after clk", foo);
	 $finish;
      end

      adr = 1;
      bit = 1;
      load_enable = 0;
      write_enable = 1;

      #1 clk = 1;
      #1 clk = 0;

      if (foo !== 4'b1011) begin
	 $display("FAILED -- foo=%b, adr=%b, bit=%b", foo, adr, bit);
	 $finish;
      end

      $display("PASSED");
      $finish;
   end

endmodule