data/full_repos/permissive/459277146/BCD_convert.v
1: b'%Warning-WIDTH: data/full_repos/permissive/459277146/BCD_convert.v:23: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                     : ... In instance BCD_convert\n            BCD_out = {BCD_out[DWIDTH+1:0], bin_in[DWIDTH+1 - i]};\n                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module BCD_convert #(parameter DWIDTH = 8)(
    input [DWIDTH-1:0] bin_in,
    output reg [11:0] BCD_out
    );
    
   
    integer i;
    
    always @(bin_in)
    begin
        BCD_out = 0;
        for (i = 0; i < DWIDTH+1; i = i + 1)
        begin

            if (BCD_out[3:0] > 4)
                BCD_out[3:0] = BCD_out[3:0] + 3;
            if (BCD_out[7:4] > 4)
                BCD_out[7:4] = BCD_out[7:4] + 3;
            if (BCD_out[11:8] > 4)
                BCD_out[11:8] = BCD_out[11:8] + 3;
            BCD_out = {BCD_out[DWIDTH+1:0], bin_in[DWIDTH+1 - i]};
        end
    end
    
endmodule
module BCD_convert #(parameter DWIDTH = 8)(
    input [DWIDTH-1:0] bin_in,
    output reg [11:0] BCD_out
    );

    
   
    integer i;
    
    always @(bin_in)
    begin
        BCD_out = 0;
        for (i = 0; i < DWIDTH+1; i = i + 1)
        begin

            if (BCD_out[3:0] > 4)
                BCD_out[3:0] = BCD_out[3:0] + 3;
            if (BCD_out[7:4] > 4)
                BCD_out[7:4] = BCD_out[7:4] + 3;
            if (BCD_out[11:8] > 4)
                BCD_out[11:8] = BCD_out[11:8] + 3;
            BCD_out = {BCD_out[DWIDTH+1:0], bin_in[DWIDTH+1 - i]};
        end
    end
    
endmodule