data/full_repos/permissive/405799749/amg_new2/adder/FSA_16_64_Carry_select_adder.v
data/verilator_xmls/a1e22f4f-1bee-4d86-a007-eae88622d5c2.xml
module UBPriCSlA_63_0(S, X, Y, Cin);
  output [64:0] S;
  input Cin;
  input [63:0] X;
  input [63:0] Y;
  wire C0;
  wire C1;
  wire C10;
  wire C2;
  wire C3;
  wire C4;
  wire C5;
  wire C6;
  wire C7;
  wire C8;
  wire C9;
  UBRCB_0_0 U0 (C0, S[0], X[0], Y[0], Cin);
  UBCSlB_1_1 U1 (C1, S[1], X[1], Y[1], C0);
  UBCSlB_3_2 U2 (C2, S[3:2], X[3:2], Y[3:2], C1);
  UBCSlB_6_4 U3 (C3, S[6:4], X[6:4], Y[6:4], C2);
  UBCSlB_10_7 U4 (C4, S[10:7], X[10:7], Y[10:7], C3);
  UBCSlB_15_11 U5 (C5, S[15:11], X[15:11], Y[15:11], C4);
  UBCSlB_21_16 U6 (C6, S[21:16], X[21:16], Y[21:16], C5);
  UBCSlB_28_22 U7 (C7, S[28:22], X[28:22], Y[28:22], C6);
  UBCSlB_36_29 U8 (C8, S[36:29], X[36:29], Y[36:29], C7);
  UBCSlB_45_37 U9 (C9, S[45:37], X[45:37], Y[45:37], C8);
  UBCSlB_55_46 U10 (C10, S[55:46], X[55:46], Y[55:46], C9);
  UBCSlB_63_56 U11 (S[64], S[63:56], X[63:56], Y[63:56], C10);
endmodule
module UBPriCSlA_63_0(S, X, Y, Cin);

  output [64:0] S;
  input Cin;
  input [63:0] X;
  input [63:0] Y;
  wire C0;
  wire C1;
  wire C10;
  wire C2;
  wire C3;
  wire C4;
  wire C5;
  wire C6;
  wire C7;
  wire C8;
  wire C9;
  UBRCB_0_0 U0 (C0, S[0], X[0], Y[0], Cin);
  UBCSlB_1_1 U1 (C1, S[1], X[1], Y[1], C0);
  UBCSlB_3_2 U2 (C2, S[3:2], X[3:2], Y[3:2], C1);
  UBCSlB_6_4 U3 (C3, S[6:4], X[6:4], Y[6:4], C2);
  UBCSlB_10_7 U4 (C4, S[10:7], X[10:7], Y[10:7], C3);
  UBCSlB_15_11 U5 (C5, S[15:11], X[15:11], Y[15:11], C4);
  UBCSlB_21_16 U6 (C6, S[21:16], X[21:16], Y[21:16], C5);
  UBCSlB_28_22 U7 (C7, S[28:22], X[28:22], Y[28:22], C6);
  UBCSlB_36_29 U8 (C8, S[36:29], X[36:29], Y[36:29], C7);
  UBCSlB_45_37 U9 (C9, S[45:37], X[45:37], Y[45:37], C8);
  UBCSlB_55_46 U10 (C10, S[55:46], X[55:46], Y[55:46], C9);
  UBCSlB_63_56 U11 (S[64], S[63:56], X[63:56], Y[63:56], C10);
endmodule