data/full_repos/permissive/447976230/fpga/usrp1/megacells/dspclkpll_bb.v
data/verilator_xmls/f4068519-3c71-429c-928c-e379d2dc9579.xml
module dspclkpll (
	inclk0,
	c0,
	c1);

	input	  inclk0;
	output	  c0;
	output	  c1;

endmodule
module dspclkpll (
	inclk0,
	c0,
	c1);


	input	  inclk0;
	output	  c0;
	output	  c1;

endmodule