data/full_repos/permissive/4632054/cores/asfifo/rtl/graycounter.v
data/verilator_xmls/242a49e7-1e5c-4884-ba61-dcfc1c79d075.xml
module graycounter
   #(parameter   COUNTER_WIDTH = 2)
   
    (output reg  [COUNTER_WIDTH-1:0]    GrayCount_out,
    
     input wire                         Enable_in,
     input wire                         rst,
    
     input wire                         Clk);


    reg    [COUNTER_WIDTH-1:0]         BinaryCount;


    
    always @ (posedge Clk)
        if (rst) begin
            BinaryCount   <= {COUNTER_WIDTH{1'b 0}} + 1;
            GrayCount_out <= {COUNTER_WIDTH{1'b 0}};
        end
        else if (Enable_in) begin
            BinaryCount   <= BinaryCount + 1;
            GrayCount_out <= {BinaryCount[COUNTER_WIDTH-1],
                              BinaryCount[COUNTER_WIDTH-2:0] ^ BinaryCount[COUNTER_WIDTH-1:1]};
        end

endmodule
module graycounter
   #(parameter   COUNTER_WIDTH = 2)
   
    (output reg  [COUNTER_WIDTH-1:0]    GrayCount_out,
    
     input wire                         Enable_in,
     input wire                         rst,
    
     input wire                         Clk);



    reg    [COUNTER_WIDTH-1:0]         BinaryCount;


    
    always @ (posedge Clk)
        if (rst) begin
            BinaryCount   <= {COUNTER_WIDTH{1'b 0}} + 1;
            GrayCount_out <= {COUNTER_WIDTH{1'b 0}};
        end
        else if (Enable_in) begin
            BinaryCount   <= BinaryCount + 1;
            GrayCount_out <= {BinaryCount[COUNTER_WIDTH-1],
                              BinaryCount[COUNTER_WIDTH-2:0] ^ BinaryCount[COUNTER_WIDTH-1:1]};
        end

endmodule