data/full_repos/permissive/423410371/src/sim/SB_LUT4.v
data/verilator_xmls/e95ad960-7029-4728-ba31-629ed50407d9.xml
module SB_LUT4(
               input wire I0,
               output wire O
              );

  parameter LUT_INIT = 1'h1;

  assign O = I0 ^ LUT_INIT;

endmodule
module SB_LUT4(
               input wire I0,
               output wire O
              );


  parameter LUT_INIT = 1'h1;

  assign O = I0 ^ LUT_INIT;

endmodule