data/full_repos/permissive/509468557/generators/testchipip/src/main/resources/testchipip/vsrc/ClockUtil.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/509468557/generators/testchipip/src/main/resources/testchipip/vsrc/ClockUtil.v:15: Multiple top level modules\n                                                                                                                               : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                                               : ... Top module \'ClockFlop\'\nmodule ClockFlop (\n       ^~~~~~~~~\n                                                                                                                               : ... Top module \'ClockSignalNor2\'\nmodule ClockSignalNor2 (\n       ^~~~~~~~~~~~~~~\n                                                                                                                               : ... Top module \'ClockInverter\'\nmodule ClockInverter (\n       ^~~~~~~~~~~~~\n                                                                                                                               : ... Top module \'ClockMux2\'\nmodule ClockMux2 (\n       ^~~~~~~~~\n                                                                                                                               : ... Top module \'ClockOr2\'\nmodule ClockOr2 (\n       ^~~~~~~~\n                                                                                                                               : ... Top module \'PeriodMonitor\'\nmodule PeriodMonitor #(\n       ^~~~~~~~~~~~~\n                                                                                                                               : ... Top module \'ClockGenerator\'\nmodule ClockGenerator #(\n       ^~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module PeriodMonitor #(
    parameter longint minperiodps = 1000,
    parameter longint maxperiodps = 1000
) (
    input clock,
    input enable
);

`ifndef VERILATOR
    time edgetime = 1ps;
`else
    time edgetime = 1;
`endif
    longint period;

    always @(posedge clock) begin
`ifndef VERILATOR
        period = $realtime/1ps - edgetime;
        edgetime = $realtime/1ps;
`else
        period = $time - edgetime;
        edgetime = $time;
`endif
        if (period > 0) begin
            if (enable && (period < minperiodps)) begin
                $display("PeriodMonitor detected a small period of %d ps at time %0t", period, $realtime);
                $fatal;
            end
            if (enable && (maxperiodps > 0) && (period > maxperiodps)) begin
                $display("PeriodMonitor detected a large period of %d ps at time %0t", period, $realtime);
                $fatal;
            end
        end
    end

endmodule
module PeriodMonitor #(
    parameter longint minperiodps = 1000,
    parameter longint maxperiodps = 1000
) (
    input clock,
    input enable
);


`ifndef VERILATOR
    time edgetime = 1ps;
`else
    time edgetime = 1;
`endif
    longint period;

    always @(posedge clock) begin
`ifndef VERILATOR
        period = $realtime/1ps - edgetime;
        edgetime = $realtime/1ps;
`else
        period = $time - edgetime;
        edgetime = $time;
`endif
        if (period > 0) begin
            if (enable && (period < minperiodps)) begin
                $display("PeriodMonitor detected a small period of %d ps at time %0t", period, $realtime);
                $fatal;
            end
            if (enable && (maxperiodps > 0) && (period > maxperiodps)) begin
                $display("PeriodMonitor detected a large period of %d ps at time %0t", period, $realtime);
                $fatal;
            end
        end
    end

endmodule