data/full_repos/permissive/434187796/src/SQUARE_WAVE_GENERATOR.v
1: b"%Error: data/full_repos/permissive/434187796/src/SQUARE_WAVE_GENERATOR.v:3: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'cycle'\n                                                                          : ... In instance SQUARE_WAVE_GENERATOR\n                parameter [31:0] cycle                   \n                                 ^~~~~\n%Error: data/full_repos/permissive/434187796/src/SQUARE_WAVE_GENERATOR.v:13: Expecting expression to be constant, but variable isn't const: 'cycle'\n                                                                           : ... In instance SQUARE_WAVE_GENERATOR\n        localparam [31:0] target_cycle = cycle >> 1;     \n                                         ^~~~~\n%Error: Exiting due to 2 error(s)\n"
module SQUARE_WAVE_GENERATOR
        #(
                parameter [31:0] cycle
        )
        (
                input clk,
                input rst,
                output reg sw
        );
        
        wire clk_target;

        localparam [31:0] target_cycle = cycle >> 1;

        TIMER #(.cycle(target_cycle)) timer (.clk(clk), .rst(rst), .cy(clk_target));

        initial begin
                sw <= 1'b0;
        end

        always @(posedge clk_target or negedge rst) begin
                if (rst == 1'b0) begin
                        sw <= 0;
                end else begin
                        sw <= ~sw;
                end
        end
endmodule
module SQUARE_WAVE_GENERATOR
        #(
                parameter [31:0] cycle
        )
        (
                input clk,
                input rst,
                output reg sw
        );

        
        wire clk_target;

        localparam [31:0] target_cycle = cycle >> 1;

        TIMER #(.cycle(target_cycle)) timer (.clk(clk), .rst(rst), .cy(clk_target));

        initial begin
                sw <= 1'b0;
        end

        always @(posedge clk_target or negedge rst) begin
                if (rst == 1'b0) begin
                        sw <= 0;
                end else begin
                        sw <= ~sw;
                end
        end
endmodule