data/full_repos/permissive/527007664/openlane/rlbp/src/rlbp.v
1: b"%Error-ASSIGNIN: data/full_repos/permissive/527007664/openlane/rlbp/src/rlbp.v:245: Assigning to input/const variable: 'ce_d1'\n .ce_d1(ce_d1), \n        ^~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/527007664/openlane/rlbp/src/rlbp.v:246: Assigning to input/const variable: 'ce_d2'\n .ce_d2(ce_d2), \n        ^~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/527007664/openlane/rlbp/src/rlbp.v:247: Assigning to input/const variable: 'ce_d3'\n .ce_d3(ce_d3),\n        ^~~~~\n%Error: Exiting due to 3 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module rlbp_fsm (clk, reset, reset_fsm, gpio_start, ce_d1, ce_d2, ce_d3, logic_analyzer_start, control_signals, rlbp_done);
	input clk, reset, gpio_start, logic_analyzer_start;
	output reg reset_fsm, ce_d1, ce_d2, ce_d3, rlbp_done;

	output reg [1:0] control_signals;
	reg [3:0] state_rlbp;
	reg [3:0] next_state_rlbp;
	
	parameter RESET_RLBP = 4'b0000; parameter S_REG_1_3 = 4'b0001; parameter S_REG_1_2 = 4'b0010; parameter S_REG_1_1 = 4'b0011; 
	parameter S_REG_2_3 = 4'b0100; parameter S_REG_2_2 = 4'b0101; parameter S_REG_2_1 = 4'b0110; 
	parameter S_REG_3_3 = 4'b0111; parameter S_REG_3_2 = 4'b1000; parameter S_REG_3_1 = 4'b1001; parameter WAIT = 4'b1010; 
	
	initial begin
		state_rlbp = 4'b0000;
		ce_d1 = 1'b0;
		ce_d2 = 1'b0;
		ce_d3 = 1'b0;
	end
	
	always @(posedge clk or posedge reset)
	begin
		if (reset) state_rlbp <= RESET_RLBP;
		else state_rlbp <= next_state_rlbp;
	end

	always @(state_rlbp or gpio_start or logic_analyzer_start)
	begin
		case (state_rlbp)
			RESET_RLBP:	if (gpio_start==1'b0 && logic_analyzer_start==1'b0) begin
						next_state_rlbp = RESET_RLBP; end
					else if (gpio_start==1'b1 && logic_analyzer_start==1'b1) begin
						next_state_rlbp = RESET_RLBP; end
					else begin
		       			 next_state_rlbp = S_REG_1_3; end
			S_REG_1_3:	next_state_rlbp = S_REG_1_2;
			S_REG_1_2:	next_state_rlbp = S_REG_1_1;
			S_REG_1_1:	next_state_rlbp = S_REG_2_3;
			S_REG_2_3:	next_state_rlbp = S_REG_2_2;
			S_REG_2_2:	next_state_rlbp = S_REG_2_1;
			S_REG_2_1:	next_state_rlbp = S_REG_3_3;
			S_REG_3_3:	next_state_rlbp = S_REG_3_2;
			S_REG_3_2:	next_state_rlbp = S_REG_3_1;
			S_REG_3_1:	next_state_rlbp = WAIT;

			WAIT: 	if (gpio_start==1'b0 && logic_analyzer_start==1'b0) begin
						next_state_rlbp = RESET_RLBP; end
					else if (gpio_start==1'b1 && logic_analyzer_start==1'b1) begin
						next_state_rlbp = RESET_RLBP; end
					else begin
						next_state_rlbp = WAIT; end
			default: next_state_rlbp = RESET_RLBP;
		endcase
	end

	
	always @(state_rlbp)
	begin
		case (state_rlbp)
			RESET_RLBP: 	begin
					reset_fsm = 1'b1;
					control_signals = 2'b00;
					ce_d1 = 1'b0;
					ce_d2 = 1'b0;
					ce_d3 = 1'b0;
					rlbp_done = 1'b0;
					end
			S_REG_1_3:	begin
					reset_fsm = 1'b0;
					control_signals = 2'b01;
					ce_d1 = 1'b1;
					ce_d2 = 1'b0;
					ce_d3 = 1'b0;
					rlbp_done = 1'b0;
					end
			S_REG_1_2:	begin
					reset_fsm = 1'b0;
					control_signals = 2'b01;
					ce_d1 = 1'b1;
					ce_d2 = 1'b0;
					ce_d3 = 1'b0;
					rlbp_done = 1'b0;
					end
			S_REG_1_1:	begin
					reset_fsm = 1'b0;
					control_signals = 2'b01;
					ce_d1 = 1'b1;
					ce_d2 = 1'b0;
					ce_d3 = 1'b0;
					rlbp_done = 1'b0;
					end
			S_REG_2_3:	begin
					reset_fsm = 1'b0;
					control_signals = 2'b10;
					ce_d1 = 1'b0;
					ce_d2 = 1'b1;
					ce_d3 = 1'b0;
					rlbp_done = 1'b0;
					end
			S_REG_2_2:	begin
					reset_fsm = 1'b0;
					control_signals = 2'b10;
					ce_d1 = 1'b0;
					ce_d2 = 1'b1;
					ce_d3 = 1'b0;
					rlbp_done = 1'b0;
					end
			S_REG_2_1:	begin
					reset_fsm = 1'b0;
					control_signals = 2'b10;
					ce_d1 = 1'b0;
					ce_d2 = 1'b1;
					ce_d3 = 1'b0;
					rlbp_done = 1'b0;
					end
			S_REG_3_3:	begin
					reset_fsm = 1'b0;
					control_signals = 2'b11;
					ce_d1 = 1'b0;
					ce_d2 = 1'b0;
					ce_d3 = 1'b1;
					rlbp_done = 1'b0;
					end
			S_REG_3_2:	begin
					reset_fsm = 1'b0;
					control_signals = 2'b11;
					ce_d1 = 1'b0;
					ce_d2 = 1'b0;
					ce_d3 = 1'b1;
					rlbp_done = 1'b0;
					end		
			S_REG_3_1:	begin
					reset_fsm = 1'b0;
					control_signals = 2'b11;
					ce_d1 = 1'b0;
					ce_d2 = 1'b0;
					ce_d3 = 1'b1;
					rlbp_done = 1'b1;
					end
			WAIT:		begin
					reset_fsm = 1'b0;
					control_signals = 2'b00;
					ce_d1 = 1'b0;
					ce_d2 = 1'b0;
					ce_d3 = 1'b0;
					rlbp_done = 1'b1;
					end
		endcase
	end

endmodule
module rlbp_fsm (clk, reset, reset_fsm, gpio_start, ce_d1, ce_d2, ce_d3, logic_analyzer_start, control_signals, rlbp_done);

	input clk, reset, gpio_start, logic_analyzer_start;
	output reg reset_fsm, ce_d1, ce_d2, ce_d3, rlbp_done;

	output reg [1:0] control_signals;
	reg [3:0] state_rlbp;
	reg [3:0] next_state_rlbp;
	
	parameter RESET_RLBP = 4'b0000; parameter S_REG_1_3 = 4'b0001; parameter S_REG_1_2 = 4'b0010; parameter S_REG_1_1 = 4'b0011; 
	parameter S_REG_2_3 = 4'b0100; parameter S_REG_2_2 = 4'b0101; parameter S_REG_2_1 = 4'b0110; 
	parameter S_REG_3_3 = 4'b0111; parameter S_REG_3_2 = 4'b1000; parameter S_REG_3_1 = 4'b1001; parameter WAIT = 4'b1010; 
	
	initial begin
		state_rlbp = 4'b0000;
		ce_d1 = 1'b0;
		ce_d2 = 1'b0;
		ce_d3 = 1'b0;
	end
	
	always @(posedge clk or posedge reset)
	begin
		if (reset) state_rlbp <= RESET_RLBP;
		else state_rlbp <= next_state_rlbp;
	end

	always @(state_rlbp or gpio_start or logic_analyzer_start)
	begin
		case (state_rlbp)
			RESET_RLBP:	if (gpio_start==1'b0 && logic_analyzer_start==1'b0) begin
						next_state_rlbp = RESET_RLBP; end
					else if (gpio_start==1'b1 && logic_analyzer_start==1'b1) begin
						next_state_rlbp = RESET_RLBP; end
					else begin
		       			 next_state_rlbp = S_REG_1_3; end
			S_REG_1_3:	next_state_rlbp = S_REG_1_2;
			S_REG_1_2:	next_state_rlbp = S_REG_1_1;
			S_REG_1_1:	next_state_rlbp = S_REG_2_3;
			S_REG_2_3:	next_state_rlbp = S_REG_2_2;
			S_REG_2_2:	next_state_rlbp = S_REG_2_1;
			S_REG_2_1:	next_state_rlbp = S_REG_3_3;
			S_REG_3_3:	next_state_rlbp = S_REG_3_2;
			S_REG_3_2:	next_state_rlbp = S_REG_3_1;
			S_REG_3_1:	next_state_rlbp = WAIT;

			WAIT: 	if (gpio_start==1'b0 && logic_analyzer_start==1'b0) begin
						next_state_rlbp = RESET_RLBP; end
					else if (gpio_start==1'b1 && logic_analyzer_start==1'b1) begin
						next_state_rlbp = RESET_RLBP; end
					else begin
						next_state_rlbp = WAIT; end
			default: next_state_rlbp = RESET_RLBP;
		endcase
	end

	
	always @(state_rlbp)
	begin
		case (state_rlbp)
			RESET_RLBP: 	begin
					reset_fsm = 1'b1;
					control_signals = 2'b00;
					ce_d1 = 1'b0;
					ce_d2 = 1'b0;
					ce_d3 = 1'b0;
					rlbp_done = 1'b0;
					end
			S_REG_1_3:	begin
					reset_fsm = 1'b0;
					control_signals = 2'b01;
					ce_d1 = 1'b1;
					ce_d2 = 1'b0;
					ce_d3 = 1'b0;
					rlbp_done = 1'b0;
					end
			S_REG_1_2:	begin
					reset_fsm = 1'b0;
					control_signals = 2'b01;
					ce_d1 = 1'b1;
					ce_d2 = 1'b0;
					ce_d3 = 1'b0;
					rlbp_done = 1'b0;
					end
			S_REG_1_1:	begin
					reset_fsm = 1'b0;
					control_signals = 2'b01;
					ce_d1 = 1'b1;
					ce_d2 = 1'b0;
					ce_d3 = 1'b0;
					rlbp_done = 1'b0;
					end
			S_REG_2_3:	begin
					reset_fsm = 1'b0;
					control_signals = 2'b10;
					ce_d1 = 1'b0;
					ce_d2 = 1'b1;
					ce_d3 = 1'b0;
					rlbp_done = 1'b0;
					end
			S_REG_2_2:	begin
					reset_fsm = 1'b0;
					control_signals = 2'b10;
					ce_d1 = 1'b0;
					ce_d2 = 1'b1;
					ce_d3 = 1'b0;
					rlbp_done = 1'b0;
					end
			S_REG_2_1:	begin
					reset_fsm = 1'b0;
					control_signals = 2'b10;
					ce_d1 = 1'b0;
					ce_d2 = 1'b1;
					ce_d3 = 1'b0;
					rlbp_done = 1'b0;
					end
			S_REG_3_3:	begin
					reset_fsm = 1'b0;
					control_signals = 2'b11;
					ce_d1 = 1'b0;
					ce_d2 = 1'b0;
					ce_d3 = 1'b1;
					rlbp_done = 1'b0;
					end
			S_REG_3_2:	begin
					reset_fsm = 1'b0;
					control_signals = 2'b11;
					ce_d1 = 1'b0;
					ce_d2 = 1'b0;
					ce_d3 = 1'b1;
					rlbp_done = 1'b0;
					end		
			S_REG_3_1:	begin
					reset_fsm = 1'b0;
					control_signals = 2'b11;
					ce_d1 = 1'b0;
					ce_d2 = 1'b0;
					ce_d3 = 1'b1;
					rlbp_done = 1'b1;
					end
			WAIT:		begin
					reset_fsm = 1'b0;
					control_signals = 2'b00;
					ce_d1 = 1'b0;
					ce_d2 = 1'b0;
					ce_d3 = 1'b0;
					rlbp_done = 1'b1;
					end
		endcase
	end

endmodule