data/full_repos/permissive/512077043/rgb_fifo/r-ptr-empty.v
1: b'%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_fifo/r-ptr-empty.v:45: Operator AND expects 5 bits on the LHS, but LHS\'s VARREF \'r_inc\' generates 1 bits.\n                                                                              : ... In instance r_ptr_empty\n    assign r_bin_next = r_bin + (r_inc & ~r_empty);\n                                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_fifo/r-ptr-empty.v:45: Operator NOT expects 5 bits on the LHS, but LHS\'s VARREF \'r_empty\' generates 1 bits.\n                                                                              : ... In instance r_ptr_empty\n    assign r_bin_next = r_bin + (r_inc & ~r_empty);\n                                         ^\n%Error: Exiting due to 2 warning(s)\n'
module r_ptr_empty #(


    parameter   ADDR_SIZE = 4
) (
    

    input       [ADDR_SIZE:0]   r_syn_w_gray,
    input                       r_inc,
    input                       r_clk,
    input                       r_rst,


    output      [ADDR_SIZE-1:0] r_addr,
    output  reg [ADDR_SIZE:0]   r_gray,
    output  reg                 r_empty
);
    

    wire    [ADDR_SIZE:0]   r_gray_next;
    wire    [ADDR_SIZE:0]   r_bin_next;
    wire                    r_empty_val;
    

    reg     [ADDR_SIZE:0]   r_bin;
    

    assign r_addr = r_bin[ADDR_SIZE-1:0];
    

    assign r_bin_next = r_bin + (r_inc & ~r_empty);
    

    assign r_gray_next = (r_bin_next >> 1) ^ r_bin_next;
    


    assign r_empty_val = (r_gray_next == r_syn_w_gray);
    

    always @ (posedge r_clk or posedge r_rst) begin
        if (r_rst == 1'b1) begin
            r_bin <= 0;
            r_gray <= 0;
        end else begin
            r_bin <= r_bin_next;
            r_gray <= r_gray_next;
        end
    end
    

    always @ (posedge r_clk or posedge r_rst) begin
        if (r_rst == 1'b1) begin
            r_empty <= 1'b1;
        end else begin
            r_empty <= r_empty_val;
        end
    end
    
endmodule
module r_ptr_empty #(


    parameter   ADDR_SIZE = 4
) (
    

    input       [ADDR_SIZE:0]   r_syn_w_gray,
    input                       r_inc,
    input                       r_clk,
    input                       r_rst,


    output      [ADDR_SIZE-1:0] r_addr,
    output  reg [ADDR_SIZE:0]   r_gray,
    output  reg                 r_empty
);

    

    wire    [ADDR_SIZE:0]   r_gray_next;
    wire    [ADDR_SIZE:0]   r_bin_next;
    wire                    r_empty_val;
    

    reg     [ADDR_SIZE:0]   r_bin;
    

    assign r_addr = r_bin[ADDR_SIZE-1:0];
    

    assign r_bin_next = r_bin + (r_inc & ~r_empty);
    

    assign r_gray_next = (r_bin_next >> 1) ^ r_bin_next;
    


    assign r_empty_val = (r_gray_next == r_syn_w_gray);
    

    always @ (posedge r_clk or posedge r_rst) begin
        if (r_rst == 1'b1) begin
            r_bin <= 0;
            r_gray <= 0;
        end else begin
            r_bin <= r_bin_next;
            r_gray <= r_gray_next;
        end
    end
    

    always @ (posedge r_clk or posedge r_rst) begin
        if (r_rst == 1'b1) begin
            r_empty <= 1'b1;
        end else begin
            r_empty <= r_empty_val;
        end
    end
    
endmodule