data/full_repos/permissive/482719158/verilog/dv/microwatt/simplebus_minimal/simplebus_minimal_tb.v
1: b'%Error: data/full_repos/permissive/482719158/verilog/dv/microwatt/simplebus_minimal/simplebus_minimal_tb.v:23: Cannot find include file: uprj_netlists.v\n`include "uprj_netlists.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/482719158/verilog/dv/microwatt/simplebus_minimal,data/full_repos/permissive/482719158/uprj_netlists.v\n             data/full_repos/permissive/482719158/verilog/dv/microwatt/simplebus_minimal,data/full_repos/permissive/482719158/uprj_netlists.v.v\n             data/full_repos/permissive/482719158/verilog/dv/microwatt/simplebus_minimal,data/full_repos/permissive/482719158/uprj_netlists.v.sv\n             uprj_netlists.v\n             uprj_netlists.v.v\n             uprj_netlists.v.sv\n             obj_dir/uprj_netlists.v\n             obj_dir/uprj_netlists.v.v\n             obj_dir/uprj_netlists.v.sv\n%Error: data/full_repos/permissive/482719158/verilog/dv/microwatt/simplebus_minimal/simplebus_minimal_tb.v:24: Cannot find include file: caravel_netlists.v\n`include "caravel_netlists.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/482719158/verilog/dv/microwatt/simplebus_minimal/simplebus_minimal_tb.v:25: Cannot find include file: spiflash.v\n`include "spiflash.v" \n         ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/simplebus_minimal/simplebus_minimal_tb.v:228: Unsupported: Ignoring delay on this delayed statement.\n always #5 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/482719158/verilog/dv/microwatt/simplebus_minimal/simplebus_minimal_tb.v:244: syntax error, unexpected \'@\'\n   @(posedge clock);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/simplebus_minimal/simplebus_minimal_tb.v:254: Unsupported: Ignoring delay on this delayed statement.\n  #2000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/simplebus_minimal/simplebus_minimal_tb.v:266: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/simplebus_minimal/simplebus_minimal_tb.v:268: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/simplebus_minimal/simplebus_minimal_tb.v:273: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/simplebus_minimal/simplebus_minimal_tb.v:275: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/482719158/verilog/dv/microwatt/simplebus_minimal/simplebus_minimal_tb.v:281: Unsupported: wait statements\n  wait(checkbit == 1\'h1);\n  ^~~~\n%Error: Exiting due to 5 error(s), 6 warning(s)\n'
module simplebus_minimal_tb;
	reg clock;
	reg RSTB;
	reg microwatt_reset;
	reg power1, power2;
	reg power3, power4;

	wire gpio;
	wire [37:0] mprj_io;
	wire checkbit;
	wire user_flash_csb;
	wire user_flash_clk;
	inout user_flash_io0;
	inout user_flash_io1;

	assign mprj_io[7] = microwatt_reset;

	assign mprj_io[35] = 1'b1;

	wire ext_bus_clk;
	wire [7:0] ext_bus_in;
	wire ext_bus_pty_in;
	wire [7:0] ext_bus_out;
	wire ext_bus_pty_out;

	assign user_flash_csb = mprj_io[8];
	assign user_flash_clk = mprj_io[9];
	assign user_flash_io0 = mprj_io[10];
	assign mprj_io[11] = user_flash_io1;

	assign checkbit = mprj_io[37];

	assign mprj_io[3] = 1'b1;


	assign mprj_io[5] = 1;


	assign mprj_io[15:13] = 0;

	assign ext_bus_clk = mprj_io[16];
	assign ext_bus_in[7:0] = mprj_io[24:17];
	assign ext_bus_pty_in = mprj_io[25];
	assign mprj_io[33:26] = ext_bus_out[7:0];
	assign mprj_io[34] = ext_bus_pty_out;


	always #5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
	end

	initial begin



		$display("Microwatt external bus minimal test");




		repeat (40000) begin
			@(posedge clock);
		end

		$display("Timeout, test failed");
		$fatal;
	end

	initial begin
		RSTB <= 1'b0;
		microwatt_reset <= 1'b1;
		#2000;



		microwatt_reset <= 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;



		#1000;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end

	initial begin

		wait(checkbit == 1'h1);
		$display("Success!");
		$finish;
	end

	wire VDD3V3 = power1;
	wire VDD1V8 = power2;
	wire USER_VDD3V3 = power3;
	wire USER_VDD1V8 = power4;
	wire VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (USER_VDD3V3),
		.vdda1_2  (USER_VDD3V3),
		.vdda2    (USER_VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (USER_VDD1V8),
		.vccd2	  (USER_VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock	  (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("microwatt.hex")
	) spiflash_microwatt (
		.csb(user_flash_csb),
		.clk(user_flash_clk),
		.io0(user_flash_io0),
		.io1(user_flash_io1),
		.io2(),
		.io3()
	);

	simplebus_tb simplebus_tb (
		.clk(ext_bus_clk),
		.ext_bus_in(ext_bus_in),
		.ext_bus_pty_in(ext_bus_pty_in),
		.ext_bus_out(ext_bus_out),
		.ext_bus_pty_out(ext_bus_pty_out)
	);
endmodule
module simplebus_minimal_tb;

	reg clock;
	reg RSTB;
	reg microwatt_reset;
	reg power1, power2;
	reg power3, power4;

	wire gpio;
	wire [37:0] mprj_io;
	wire checkbit;
	wire user_flash_csb;
	wire user_flash_clk;
	inout user_flash_io0;
	inout user_flash_io1;

	assign mprj_io[7] = microwatt_reset;

	assign mprj_io[35] = 1'b1;

	wire ext_bus_clk;
	wire [7:0] ext_bus_in;
	wire ext_bus_pty_in;
	wire [7:0] ext_bus_out;
	wire ext_bus_pty_out;

	assign user_flash_csb = mprj_io[8];
	assign user_flash_clk = mprj_io[9];
	assign user_flash_io0 = mprj_io[10];
	assign mprj_io[11] = user_flash_io1;

	assign checkbit = mprj_io[37];

	assign mprj_io[3] = 1'b1;


	assign mprj_io[5] = 1;


	assign mprj_io[15:13] = 0;

	assign ext_bus_clk = mprj_io[16];
	assign ext_bus_in[7:0] = mprj_io[24:17];
	assign ext_bus_pty_in = mprj_io[25];
	assign mprj_io[33:26] = ext_bus_out[7:0];
	assign mprj_io[34] = ext_bus_pty_out;


	always #5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
	end

	initial begin



		$display("Microwatt external bus minimal test");




		repeat (40000) begin
			@(posedge clock);
		end

		$display("Timeout, test failed");
		$fatal;
	end

	initial begin
		RSTB <= 1'b0;
		microwatt_reset <= 1'b1;
		#2000;



		microwatt_reset <= 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;



		#1000;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end

	initial begin

		wait(checkbit == 1'h1);
		$display("Success!");
		$finish;
	end

	wire VDD3V3 = power1;
	wire VDD1V8 = power2;
	wire USER_VDD3V3 = power3;
	wire USER_VDD1V8 = power4;
	wire VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (USER_VDD3V3),
		.vdda1_2  (USER_VDD3V3),
		.vdda2    (USER_VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (USER_VDD1V8),
		.vccd2	  (USER_VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock	  (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("microwatt.hex")
	) spiflash_microwatt (
		.csb(user_flash_csb),
		.clk(user_flash_clk),
		.io0(user_flash_io0),
		.io1(user_flash_io1),
		.io2(),
		.io3()
	);

	simplebus_tb simplebus_tb (
		.clk(ext_bus_clk),
		.ext_bus_in(ext_bus_in),
		.ext_bus_pty_in(ext_bus_pty_in),
		.ext_bus_out(ext_bus_out),
		.ext_bus_pty_out(ext_bus_pty_out)
	);
endmodule