data/full_repos/permissive/41989639/american_put_cyclone/src/DE2_70_flash_word_tester.v
1: b"%Error: data/full_repos/permissive/41989639/american_put_cyclone/src/DE2_70_flash_word_tester.v:220: Cannot find file containing module: 'flash_writer'\nflash_writer f1(\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/41989639/american_put_cyclone/src,data/full_repos/permissive/41989639/flash_writer\n             data/full_repos/permissive/41989639/american_put_cyclone/src,data/full_repos/permissive/41989639/flash_writer.v\n             data/full_repos/permissive/41989639/american_put_cyclone/src,data/full_repos/permissive/41989639/flash_writer.sv\n             flash_writer\n             flash_writer.v\n             flash_writer.sv\n             obj_dir/flash_writer\n             obj_dir/flash_writer.v\n             obj_dir/flash_writer.sv\n%Error: data/full_repos/permissive/41989639/american_put_cyclone/src/DE2_70_flash_word_tester.v:247: Cannot find file containing module: 'Flash_Controller'\nFlash_Controller u5(\n^~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module DE2_70_flash_word_tester (
input           TIME_OUT,
input  		    iCLK_28,
input  		    iSTART,
output reg      oEND,
output reg      oERASE_STATUS,
output 		    oSTATUS,
	
	
inout	[14:0]	FLASH_DQ,
inout			FLASH_DQ15_AM1,
output	[25:0]	oFLASH_A,
output			oFLASH_WE_N,
output			oFLASH_RST_N,
output			oFLASH_WP_N,
input			iFLASH_RY_N,
output			oFLASH_BYTE_N,
output			oFLASH_OE_N,
output			oFLASH_CE_N	,


output reg   ERASE,
output reg   PROG,
output reg   READ,
output reg   RESET,

output reg   OK  ,
output reg   FAIL,

output       VERIFY_TIME,
output [21:0]flash_addr,
output [3:0] flash_cmd



);



wire WR_END;

reg [5:0]ST;

reg [1:0]SW;

reg [31:0]disp_cnt ;
always @(posedge iCLK_28) disp_cnt <= disp_cnt + 1;


always @( posedge disp_cnt[24]) begin
if (!iSTART) begin
	ST = 30;
	ERASE=0;
	oERASE_STATUS = 0;
	PROG =0;
	READ =0;
	OK   =0;	
	FAIL =0;	
	RESET=1;
	oEND =0;
end
else begin
if ( ( TIME_OUT )  && ( !oEND ) ) begin oEND = 1; FAIL = 1; ST = 5; end
case (ST)
	30:begin 
		ST    = 27;
		RESET = 0;
	end

	29:begin 
		ST    = ST-1;
	end

	28:begin 
		ST    = ST-1;
	end

	27:begin 
		ST    = 24;
		ERASE = 1;
	end

	26:begin 
		ST    = ST-1;
	end
	25:begin 
		ST    = ST-1;
	end

	24:begin 
		ST    = 21;
		ERASE = 0;
	end
	23:begin 
		ST    = ST-1;
	end
	22:begin 
		ST    = ST-1;
	end
	

	21:begin 
		if ( flash_ready ) ST = 18;
	end

	20:begin 
		ST    = ST-1;
	end
	19:begin 
		ST    = ST-1;
	end

	18:begin 
		if ( iFLASH_RY_N )  begin
			oERASE_STATUS = 1;
			ST    = ST-1;
		end
	end

	17:begin 
		ST    = ST-1;
		READ  = 1;
		SW    = 3;
	end
	16:begin 
		ST    = ST-1;
		READ  = 0;
	end
    
	15:begin 
		if (WR_END)  ST=ST-1;
	end

	14:begin 
		ST    = 12;
		PROG  = 1;
		SW    = 2;
	end
	
	13:begin 
		ST    = ST-1;
	end

	12:begin 
		ST    = 10;
		PROG  = 0;
	end
	11:begin 
		ST    = ST-1;
	end

	10:begin 
		if (WR_END)  ST=ST-1;
	end

	9:begin 
		ST    = ST-1;
		READ  = 1;
		SW    = 2;
	end
	8:begin 
		ST    = ST-1;
		READ  = 0;
	end
    
	7:begin 
		if (WR_END)  ST=ST-1;
	end	
	6:begin 
		oEND = 1;
		ST=4;
		if ( oSTATUS )  OK = 1; else  FAIL = 1;
	end                                
	                                
	5:begin 
		ST=ST-1;
	end
	
	4:begin 
	 OK = 0;
	 FAIL = 0;
	end		
	
endcase
end
end








wire [15:0]flash_data;

wire flash_tr;
wire flash_ready;

assign flash_data = (
	( SW[1:0] ==0)? flash_addr[15:0]:  (
	( SW[1:0] ==1)? 16'haaaa: 		    (
	( SW[1:0] ==2)? 16'h0000:  16'hffff
	)));


reg  error ;

always @(posedge RESET or posedge oFLASH_OE_N) begin
if ( RESET ) error = 1;
else if ((VERIFY_TIME ) && (error))
	error = ~( { FLASH_DQ15_AM1 , FLASH_DQ } != flash_data ) ;
end

wire WE_CLK;
wire p_ready;
flash_writer f1(
    .WE_CLK(WE_CLK),
    .p_ready(p_ready),
	.iFLASH_RY_N ( iFLASH_RY_N ),
	.iOSC_28     ( iCLK_28  ),  
	.iERASE      ( ERASE    ), 
	.iPROGRAM    ( PROG ), 
	.iVERIFY     ( READ     ), 
	.iOK(OK),
	.iFAIL(FAIL),
	

	.iRESET_N    ( RESET ),
	.oREAD_PRO_END (WR_END),
	.oVERIFY_TIME(VERIFY_TIME),

	.oFLASH_ADDR ( flash_addr),
	.oFLASH_CMD  ( flash_cmd ), 
	.oFLASH_TR   ( flash_tr  )   

);


wire FL_CE_o;



Flash_Controller u5(
    .p_ready(p_ready),
	.iFLASH_RY_N (iFLASH_RY_N ),	
	.iCLK  	( iCLK_28  ),
	.iRST_n	( 1'b1     ),
	.iStart	( flash_tr ),
	.iDATA	( flash_data ),
	.iADDR	( flash_addr ), 
	.iCMD 	( flash_cmd ),     
	.oReady	( flash_ready ),
	.WE_CLK(WE_CLK),


	.FL_DQ   ( { FLASH_DQ15_AM1 , FLASH_DQ }    ) ,
	.FL_ADDR (  oFLASH_A[21:0]  ),
	.FL_WE_n (  oFLASH_WE_N ),
	.FL_CE_n ( oFLASH_CE_N ),
	.FL_OE_n ( oFLASH_OE_N )

);

assign   oFLASH_RST_N  = ~RESET;
assign	 oFLASH_WP_N   = 1;
assign	 oFLASH_BYTE_N = 1;


assign   oSTATUS = error;


endmodule
module DE2_70_flash_word_tester (
input           TIME_OUT,
input  		    iCLK_28,
input  		    iSTART,
output reg      oEND,
output reg      oERASE_STATUS,
output 		    oSTATUS,
	
	
inout	[14:0]	FLASH_DQ,
inout			FLASH_DQ15_AM1,
output	[25:0]	oFLASH_A,
output			oFLASH_WE_N,
output			oFLASH_RST_N,
output			oFLASH_WP_N,
input			iFLASH_RY_N,
output			oFLASH_BYTE_N,
output			oFLASH_OE_N,
output			oFLASH_CE_N	,


output reg   ERASE,
output reg   PROG,
output reg   READ,
output reg   RESET,

output reg   OK  ,
output reg   FAIL,

output       VERIFY_TIME,
output [21:0]flash_addr,
output [3:0] flash_cmd



);




wire WR_END;

reg [5:0]ST;

reg [1:0]SW;

reg [31:0]disp_cnt ;
always @(posedge iCLK_28) disp_cnt <= disp_cnt + 1;


always @( posedge disp_cnt[24]) begin
if (!iSTART) begin
	ST = 30;
	ERASE=0;
	oERASE_STATUS = 0;
	PROG =0;
	READ =0;
	OK   =0;	
	FAIL =0;	
	RESET=1;
	oEND =0;
end
else begin
if ( ( TIME_OUT )  && ( !oEND ) ) begin oEND = 1; FAIL = 1; ST = 5; end
case (ST)
	30:begin 
		ST    = 27;
		RESET = 0;
	end

	29:begin 
		ST    = ST-1;
	end

	28:begin 
		ST    = ST-1;
	end

	27:begin 
		ST    = 24;
		ERASE = 1;
	end

	26:begin 
		ST    = ST-1;
	end
	25:begin 
		ST    = ST-1;
	end

	24:begin 
		ST    = 21;
		ERASE = 0;
	end
	23:begin 
		ST    = ST-1;
	end
	22:begin 
		ST    = ST-1;
	end
	

	21:begin 
		if ( flash_ready ) ST = 18;
	end

	20:begin 
		ST    = ST-1;
	end
	19:begin 
		ST    = ST-1;
	end

	18:begin 
		if ( iFLASH_RY_N )  begin
			oERASE_STATUS = 1;
			ST    = ST-1;
		end
	end

	17:begin 
		ST    = ST-1;
		READ  = 1;
		SW    = 3;
	end
	16:begin 
		ST    = ST-1;
		READ  = 0;
	end
    
	15:begin 
		if (WR_END)  ST=ST-1;
	end

	14:begin 
		ST    = 12;
		PROG  = 1;
		SW    = 2;
	end
	
	13:begin 
		ST    = ST-1;
	end

	12:begin 
		ST    = 10;
		PROG  = 0;
	end
	11:begin 
		ST    = ST-1;
	end

	10:begin 
		if (WR_END)  ST=ST-1;
	end

	9:begin 
		ST    = ST-1;
		READ  = 1;
		SW    = 2;
	end
	8:begin 
		ST    = ST-1;
		READ  = 0;
	end
    
	7:begin 
		if (WR_END)  ST=ST-1;
	end	
	6:begin 
		oEND = 1;
		ST=4;
		if ( oSTATUS )  OK = 1; else  FAIL = 1;
	end                                
	                                
	5:begin 
		ST=ST-1;
	end
	
	4:begin 
	 OK = 0;
	 FAIL = 0;
	end		
	
endcase
end
end








wire [15:0]flash_data;

wire flash_tr;
wire flash_ready;

assign flash_data = (
	( SW[1:0] ==0)? flash_addr[15:0]:  (
	( SW[1:0] ==1)? 16'haaaa: 		    (
	( SW[1:0] ==2)? 16'h0000:  16'hffff
	)));


reg  error ;

always @(posedge RESET or posedge oFLASH_OE_N) begin
if ( RESET ) error = 1;
else if ((VERIFY_TIME ) && (error))
	error = ~( { FLASH_DQ15_AM1 , FLASH_DQ } != flash_data ) ;
end

wire WE_CLK;
wire p_ready;
flash_writer f1(
    .WE_CLK(WE_CLK),
    .p_ready(p_ready),
	.iFLASH_RY_N ( iFLASH_RY_N ),
	.iOSC_28     ( iCLK_28  ),  
	.iERASE      ( ERASE    ), 
	.iPROGRAM    ( PROG ), 
	.iVERIFY     ( READ     ), 
	.iOK(OK),
	.iFAIL(FAIL),
	

	.iRESET_N    ( RESET ),
	.oREAD_PRO_END (WR_END),
	.oVERIFY_TIME(VERIFY_TIME),

	.oFLASH_ADDR ( flash_addr),
	.oFLASH_CMD  ( flash_cmd ), 
	.oFLASH_TR   ( flash_tr  )   

);


wire FL_CE_o;



Flash_Controller u5(
    .p_ready(p_ready),
	.iFLASH_RY_N (iFLASH_RY_N ),	
	.iCLK  	( iCLK_28  ),
	.iRST_n	( 1'b1     ),
	.iStart	( flash_tr ),
	.iDATA	( flash_data ),
	.iADDR	( flash_addr ), 
	.iCMD 	( flash_cmd ),     
	.oReady	( flash_ready ),
	.WE_CLK(WE_CLK),


	.FL_DQ   ( { FLASH_DQ15_AM1 , FLASH_DQ }    ) ,
	.FL_ADDR (  oFLASH_A[21:0]  ),
	.FL_WE_n (  oFLASH_WE_N ),
	.FL_CE_n ( oFLASH_CE_N ),
	.FL_OE_n ( oFLASH_OE_N )

);

assign   oFLASH_RST_N  = ~RESET;
assign	 oFLASH_WP_N   = 1;
assign	 oFLASH_BYTE_N = 1;


assign   oSTATUS = error;


endmodule