data/full_repos/permissive/446312960/Verilog_Simulation/11_d_latch/latch.v
data/verilator_xmls/71b01e08-9d16-448c-a51a-b3f535ad21f5.xml
module latch(CLK, D, Q, Qb);
input   CLK, D;
output  Q, Qb;

reg Q;
assign Qb = ~Q;


always @ ( CLK or D ) 
    if  ( CLK )
        Q <= D; 



endmodule
module latch(CLK, D, Q, Qb);

input   CLK, D;
output  Q, Qb;

reg Q;
assign Qb = ~Q;


always @ ( CLK or D ) 
    if  ( CLK )
        Q <= D; 



endmodule