data/full_repos/permissive/451048101/src/fpga/zynq7020/gmii_to_134b_pkt.v
1: b'%Warning-WIDTH: data/full_repos/permissive/451048101/src/fpga/zynq7020/gmii_to_134b_pkt.v:88: Operator EQ expects 32 bits on the RHS, but RHS\'s VARREF \'cnt_valid\' generates 4 bits.\n                                                                                            : ... In instance gmii_to_134b_pkt\n            if(i==cnt_valid)  pkt_tag[i]  <= gmii_data;\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/451048101/src/fpga/zynq7020/gmii_to_134b_pkt.v:114: Operator EQ expects 32 bits on the RHS, but RHS\'s VARREF \'cnt_valid\' generates 4 bits.\n                                                                                             : ... In instance gmii_to_134b_pkt\n            if(i==cnt_valid)  pkt_tag[i]  <= gmii_data;\n                ^~\n%Error: Exiting due to 2 warning(s)\n'
module gmii_to_134b_pkt #(parameter PORT_NUM = 8'd0)(
  input               rst_n,
  input               clk,
  input       [7:0]   gmii_data,
  input               gmii_data_valid,

  output  reg [133:0] pkt_data,
  output  reg         pkt_data_valid,

  output  reg [127:0] metadata,
  output  reg         metadata_valid,

  input       [15:0]  bufferID
);

reg   [1:0] head_tag;
reg   [7:0] pkt_tag[15:0];
reg   [3:0] cnt_valid;
reg   [7:0] cnt_16B;
reg   [3:0] state_accu;
localparam  IDLE_S          = 4'd0,
            WAIT_TAIL_S     = 4'd1,
            OVERFLOW_S      = 4'd2;

`ifdef OPEN_COUNTER
  (* mark_debug = "true"*)reg   [31:0]  cnt_discard_gmii2pkt;
  (* mark_debug = "true"*)reg   [31:0]  cnt_meta_gmii2pkt;
`endif

integer i;
always @(posedge clk or negedge rst_n) begin
  if(!rst_n) begin
    pkt_data_valid          <= 1'b0;
    pkt_data                <= 134'b0;
    cnt_valid               <= 4'b0;
    head_tag                <= 2'b0;
    cnt_16B                 <= 8'b0;
    state_accu              <= IDLE_S;
    `ifdef
      cnt_discard_gmii2pkt  <= 32'd0;
    `endif

    for(i=0; i<16; i=i+1) begin
      pkt_tag[i]            <= 8'b0;
    end
  end
  else begin
    case(state_accu)
      IDLE_S: begin
        pkt_data_valid      <= 1'b0;
        pkt_data            <= 134'b0;
        head_tag            <= 2'b01;
        cnt_16B             <= 8'b0;

        if(gmii_data_valid == 1'b1) begin
          for(i=0; i<16; i=i+1) begin
            if(i==cnt_valid)  pkt_tag[i]  <= gmii_data;
            else              pkt_tag[i]  <= pkt_tag[i];
          end
          cnt_valid         <= cnt_valid + 4'd1;
        end
        else begin
          cnt_valid         <= 4'd0;
        end
        

        if(cnt_valid == 4'd15) begin
          if(bufferID == 16'hffff) begin
            state_accu      <= OVERFLOW_S;
            `ifdef OPEN_COUNTER
              cnt_discard_gmii2pkt <= cnt_discard_gmii2pkt + 32'd1;
            `endif
          end
          else
            state_accu      <= WAIT_TAIL_S;
        end
      end
      WAIT_TAIL_S: begin
        pkt_data_valid      <= 1'b0;
        if(gmii_data_valid == 1'b1) begin

          for(i=0; i<16; i=i+1) begin
            if(i==cnt_valid)  pkt_tag[i]  <= gmii_data;
            else              pkt_tag[i]  <= pkt_tag[i];
          end
          cnt_valid         <= cnt_valid + 4'd1;
        

          head_tag          <= 2'b0;

          if(cnt_valid == 4'd0) begin

            cnt_16B         <= cnt_16B + 8'd1;
            if(cnt_16B == 8'd130) begin
              state_accu      <= OVERFLOW_S;
              pkt_data_valid  <= 1'b1;
              pkt_data        <= {2'b10,4'hf,pkt_tag[0],pkt_tag[1],pkt_tag[2],
                        pkt_tag[3],pkt_tag[4],pkt_tag[5],pkt_tag[6],pkt_tag[7],
                        pkt_tag[8],pkt_tag[9],pkt_tag[10],pkt_tag[11],
                        pkt_tag[12],pkt_tag[13],pkt_tag[14],pkt_tag[15]};
            end
            else begin
              pkt_data_valid  <= 1'b1;
              pkt_data        <= {head_tag,4'hf,pkt_tag[0],pkt_tag[1],pkt_tag[2],
                        pkt_tag[3],pkt_tag[4],pkt_tag[5],pkt_tag[6],pkt_tag[7],
                        pkt_tag[8],pkt_tag[9],pkt_tag[10],pkt_tag[11],
                        pkt_tag[12],pkt_tag[13],pkt_tag[14],pkt_tag[15]};
            end
          end
        end
        else begin
          pkt_data_valid    <= 1'b1;
          pkt_data          <= {2'b10,cnt_valid-4'd1,pkt_tag[0],pkt_tag[1],pkt_tag[2],
                        pkt_tag[3],pkt_tag[4],pkt_tag[5],pkt_tag[6],pkt_tag[7],
                        pkt_tag[8],pkt_tag[9],pkt_tag[10],pkt_tag[11],
                        pkt_tag[12],pkt_tag[13],pkt_tag[14],pkt_tag[15]};
          state_accu        <= IDLE_S;
          cnt_valid         <= 4'd0;

          if(head_tag == 2'b01)
            pkt_data_valid  <= 1'b0;
        end
        
      end
      OVERFLOW_S: begin
        pkt_data_valid      <= 1'b0;
        cnt_valid           <= 4'd0;
        if(gmii_data_valid == 1'b0)
          state_accu        <= IDLE_S;
      end
      default: begin
        state_accu          <= IDLE_S;
      end
    endcase
  end
end



reg   [31:0]  temp_valid;
always @(posedge clk or negedge rst_n) begin
  if(!rst_n) begin
    metadata_valid          <= 1'b0;
    metadata                <= 128'b0;
    temp_valid              <= 32'b0;
    `ifdef OPEN_COUNTER
      cnt_meta_gmii2pkt     <= 32'b0;
    `endif
  end
  else begin
    if(pkt_data_valid == 1'b1 && pkt_data[133:132] == 2'b01) begin
      temp_valid[0]         <= 1'b1;

      metadata              <= {72'b0,(pkt_data[127:80] == 48'h0001_0203_0405),
                                4'b0,pkt_data[74:72],
                              PORT_NUM[7:0],8'b0,
                              pkt_data[87:80],pkt_data[39:32],bufferID};
      `ifdef OPEN_COUNTER
        cnt_meta_gmii2pkt   <= cnt_meta_gmii2pkt + 32'd1;
      `endif
    end
    else begin
      temp_valid[0]         <= 1'b0;
    end
    {metadata_valid,temp_valid[31:1]} <= temp_valid;
  end
end






endmodule
module gmii_to_134b_pkt #(parameter PORT_NUM = 8'd0)(
  input               rst_n,
  input               clk,
  input       [7:0]   gmii_data,
  input               gmii_data_valid,

  output  reg [133:0] pkt_data,
  output  reg         pkt_data_valid,

  output  reg [127:0] metadata,
  output  reg         metadata_valid,

  input       [15:0]  bufferID
);


reg   [1:0] head_tag;
reg   [7:0] pkt_tag[15:0];
reg   [3:0] cnt_valid;
reg   [7:0] cnt_16B;
reg   [3:0] state_accu;
localparam  IDLE_S          = 4'd0,
            WAIT_TAIL_S     = 4'd1,
            OVERFLOW_S      = 4'd2;

`ifdef OPEN_COUNTER
  (* mark_debug = "true"*)reg   [31:0]  cnt_discard_gmii2pkt;
  (* mark_debug = "true"*)reg   [31:0]  cnt_meta_gmii2pkt;
`endif

integer i;
always @(posedge clk or negedge rst_n) begin
  if(!rst_n) begin
    pkt_data_valid          <= 1'b0;
    pkt_data                <= 134'b0;
    cnt_valid               <= 4'b0;
    head_tag                <= 2'b0;
    cnt_16B                 <= 8'b0;
    state_accu              <= IDLE_S;
    `ifdef
      cnt_discard_gmii2pkt  <= 32'd0;
    `endif

    for(i=0; i<16; i=i+1) begin
      pkt_tag[i]            <= 8'b0;
    end
  end
  else begin
    case(state_accu)
      IDLE_S: begin
        pkt_data_valid      <= 1'b0;
        pkt_data            <= 134'b0;
        head_tag            <= 2'b01;
        cnt_16B             <= 8'b0;

        if(gmii_data_valid == 1'b1) begin
          for(i=0; i<16; i=i+1) begin
            if(i==cnt_valid)  pkt_tag[i]  <= gmii_data;
            else              pkt_tag[i]  <= pkt_tag[i];
          end
          cnt_valid         <= cnt_valid + 4'd1;
        end
        else begin
          cnt_valid         <= 4'd0;
        end
        

        if(cnt_valid == 4'd15) begin
          if(bufferID == 16'hffff) begin
            state_accu      <= OVERFLOW_S;
            `ifdef OPEN_COUNTER
              cnt_discard_gmii2pkt <= cnt_discard_gmii2pkt + 32'd1;
            `endif
          end
          else
            state_accu      <= WAIT_TAIL_S;
        end
      end
      WAIT_TAIL_S: begin
        pkt_data_valid      <= 1'b0;
        if(gmii_data_valid == 1'b1) begin

          for(i=0; i<16; i=i+1) begin
            if(i==cnt_valid)  pkt_tag[i]  <= gmii_data;
            else              pkt_tag[i]  <= pkt_tag[i];
          end
          cnt_valid         <= cnt_valid + 4'd1;
        

          head_tag          <= 2'b0;

          if(cnt_valid == 4'd0) begin

            cnt_16B         <= cnt_16B + 8'd1;
            if(cnt_16B == 8'd130) begin
              state_accu      <= OVERFLOW_S;
              pkt_data_valid  <= 1'b1;
              pkt_data        <= {2'b10,4'hf,pkt_tag[0],pkt_tag[1],pkt_tag[2],
                        pkt_tag[3],pkt_tag[4],pkt_tag[5],pkt_tag[6],pkt_tag[7],
                        pkt_tag[8],pkt_tag[9],pkt_tag[10],pkt_tag[11],
                        pkt_tag[12],pkt_tag[13],pkt_tag[14],pkt_tag[15]};
            end
            else begin
              pkt_data_valid  <= 1'b1;
              pkt_data        <= {head_tag,4'hf,pkt_tag[0],pkt_tag[1],pkt_tag[2],
                        pkt_tag[3],pkt_tag[4],pkt_tag[5],pkt_tag[6],pkt_tag[7],
                        pkt_tag[8],pkt_tag[9],pkt_tag[10],pkt_tag[11],
                        pkt_tag[12],pkt_tag[13],pkt_tag[14],pkt_tag[15]};
            end
          end
        end
        else begin
          pkt_data_valid    <= 1'b1;
          pkt_data          <= {2'b10,cnt_valid-4'd1,pkt_tag[0],pkt_tag[1],pkt_tag[2],
                        pkt_tag[3],pkt_tag[4],pkt_tag[5],pkt_tag[6],pkt_tag[7],
                        pkt_tag[8],pkt_tag[9],pkt_tag[10],pkt_tag[11],
                        pkt_tag[12],pkt_tag[13],pkt_tag[14],pkt_tag[15]};
          state_accu        <= IDLE_S;
          cnt_valid         <= 4'd0;

          if(head_tag == 2'b01)
            pkt_data_valid  <= 1'b0;
        end
        
      end
      OVERFLOW_S: begin
        pkt_data_valid      <= 1'b0;
        cnt_valid           <= 4'd0;
        if(gmii_data_valid == 1'b0)
          state_accu        <= IDLE_S;
      end
      default: begin
        state_accu          <= IDLE_S;
      end
    endcase
  end
end



reg   [31:0]  temp_valid;
always @(posedge clk or negedge rst_n) begin
  if(!rst_n) begin
    metadata_valid          <= 1'b0;
    metadata                <= 128'b0;
    temp_valid              <= 32'b0;
    `ifdef OPEN_COUNTER
      cnt_meta_gmii2pkt     <= 32'b0;
    `endif
  end
  else begin
    if(pkt_data_valid == 1'b1 && pkt_data[133:132] == 2'b01) begin
      temp_valid[0]         <= 1'b1;

      metadata              <= {72'b0,(pkt_data[127:80] == 48'h0001_0203_0405),
                                4'b0,pkt_data[74:72],
                              PORT_NUM[7:0],8'b0,
                              pkt_data[87:80],pkt_data[39:32],bufferID};
      `ifdef OPEN_COUNTER
        cnt_meta_gmii2pkt   <= cnt_meta_gmii2pkt + 32'd1;
      `endif
    end
    else begin
      temp_valid[0]         <= 1'b0;
    end
    {metadata_valid,temp_valid[31:1]} <= temp_valid;
  end
end






endmodule