data/full_repos/permissive/453763315/alu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/453763315/alu.v:22: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                             : ... In instance alu\n      4\'h9: out <= a + b + flags[1];\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/453763315/alu.v:23: Operator SUB expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                             : ... In instance alu\n      4\'hA: out <= a - b - flags[2];\n                         ^\n%Warning-UNSIGNED: data/full_repos/permissive/453763315/alu.v:27: Comparison is constant due to unsigned arithmetic\n                                                                : ... In instance alu\n    flags[2] <= (out < 0) ? 1 : 0;  \n                     ^\n%Error: Exiting due to 3 warning(s)\n'
module alu(a, b, out, sel, flags, clk, en);
  input [7:0] a;
  input [7:0] b;
  input reg [3:0] sel;
  input clk;
  output reg [7:0] out;
  output reg [2:0] flags;
  input en;

  always @(posedge clk or negedge clk) begin
    if (en) begin
    case (sel)
      4'h0: out <= a + b;
      4'h1: out <= a - b;
      4'h2: out <= a & b;
      4'h3: out <= a | b;
      4'h4: out <= a ^ b;
      4'h5: out <= ~a;
      4'h6: out <= a << b;
      4'h7: out <= a >> b;
      4'h8: out <= a;
      4'h9: out <= a + b + flags[1];
      4'hA: out <= a - b - flags[2];
    endcase
    flags[0] <= (out == 0) ? 1 : 0;
    flags[1] <= (out > 255) ? 1 : 0;
    flags[2] <= (out < 0) ? 1 : 0;
   end
  end
endmodule
module alu(a, b, out, sel, flags, clk, en);

  input [7:0] a;
  input [7:0] b;
  input reg [3:0] sel;
  input clk;
  output reg [7:0] out;
  output reg [2:0] flags;
  input en;

  always @(posedge clk or negedge clk) begin
    if (en) begin
    case (sel)
      4'h0: out <= a + b;
      4'h1: out <= a - b;
      4'h2: out <= a & b;
      4'h3: out <= a | b;
      4'h4: out <= a ^ b;
      4'h5: out <= ~a;
      4'h6: out <= a << b;
      4'h7: out <= a >> b;
      4'h8: out <= a;
      4'h9: out <= a + b + flags[1];
      4'hA: out <= a - b - flags[2];
    endcase
    flags[0] <= (out == 0) ? 1 : 0;
    flags[1] <= (out > 255) ? 1 : 0;
    flags[2] <= (out < 0) ? 1 : 0;
   end
  end
endmodule