data/full_repos/permissive/472586361/machine/ALU.v
data/verilator_xmls/640f3363-d81f-4565-8a50-5e5ce29a0916.xml
module ALU(input op, input [7:0] A, input [7:0] B,input FLAGENABLE ,output [8:0] res);
wire flag;
wire [8:0] outdata;
assign outdata[8:0] = op ? (A[7:0] - B[7:0]) : (A[7:0] + B[7:0]);
assign res[7:0]=outdata[7:0];
assign res[8]=FLAGENABLE? outdata[8]: 1'b0;
endmodule
module ALU(input op, input [7:0] A, input [7:0] B,input FLAGENABLE ,output [8:0] res);

wire flag;
wire [8:0] outdata;
assign outdata[8:0] = op ? (A[7:0] - B[7:0]) : (A[7:0] + B[7:0]);
assign res[7:0]=outdata[7:0];
assign res[8]=FLAGENABLE? outdata[8]: 1'b0;
endmodule