data/full_repos/permissive/490716708/Verilog/iCE40.v
1: b'%Error: data/full_repos/permissive/490716708/Verilog/iCE40.v:2: Cannot find include file: CPU6.v\n`include "CPU6.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/490716708/Verilog,data/full_repos/permissive/490716708/CPU6.v\n             data/full_repos/permissive/490716708/Verilog,data/full_repos/permissive/490716708/CPU6.v.v\n             data/full_repos/permissive/490716708/Verilog,data/full_repos/permissive/490716708/CPU6.v.sv\n             CPU6.v\n             CPU6.v.v\n             CPU6.v.sv\n             obj_dir/CPU6.v\n             obj_dir/CPU6.v.v\n             obj_dir/CPU6.v.sv\n%Error: data/full_repos/permissive/490716708/Verilog/iCE40.v:3: Cannot find include file: LEDPanel.v\n`include "LEDPanel.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/490716708/Verilog/iCE40.v:4: Cannot find include file: PLL.v\n`include "PLL.v" \n         ^~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module BlockRAM(input wire clock, input wire [18:0] address, input wire write_en, input wire [7:0] data_in,
    output wire [7:0] data_out);

    initial begin
        $readmemh("programs/cylon.txt", ram_cells);
    end

    reg [7:0] ram_cells[0:255];

    wire [7:0] mapped_address = address[7:0];
    assign data_out = ram_cells[mapped_address]; 

    always @(posedge clock) begin
        if (write_en == 1 && address[15:8] == 8'hff) begin
            ram_cells[mapped_address] <= data_in;
        end
    end
endmodule
module BlockRAM(input wire clock, input wire [18:0] address, input wire write_en, input wire [7:0] data_in,
    output wire [7:0] data_out);


    initial begin
        $readmemh("programs/cylon.txt", ram_cells);
    end

    reg [7:0] ram_cells[0:255];

    wire [7:0] mapped_address = address[7:0];
    assign data_out = ram_cells[mapped_address]; 

    always @(posedge clock) begin
        if (write_en == 1 && address[15:8] == 8'hff) begin
            ram_cells[mapped_address] <= data_in;
        end
    end
endmodule