data/full_repos/permissive/43858668/final_verilog/src/clib/c_binary_op.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_binary_op.v:35: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_constants.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_constants.v.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_constants.v.sv\n             c_constants.v\n             c_constants.v.v\n             c_constants.v.sv\n             obj_dir/c_constants.v\n             obj_dir/c_constants.v.v\n             obj_dir/c_constants.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_binary_op.v:44: Define or directive not defined: \'`BINARY_OP_XOR\'\n   parameter op = `BINARY_OP_XOR;\n                  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_binary_op.v:44: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter op = `BINARY_OP_XOR;\n                                ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_binary_op.v:69: Define or directive not defined: \'`BINARY_OP_AND\'\n      `BINARY_OP_AND:\n      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_binary_op.v:69: syntax error, unexpected \':\', expecting endcase\n      `BINARY_OP_AND:\n                    ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_binary_op.v:72: Define or directive not defined: \'`BINARY_OP_NAND\'\n      `BINARY_OP_NAND:\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_binary_op.v:75: Define or directive not defined: \'`BINARY_OP_OR\'\n      `BINARY_OP_OR:\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_binary_op.v:78: Define or directive not defined: \'`BINARY_OP_NOR\'\n      `BINARY_OP_NOR:\n      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_binary_op.v:81: Define or directive not defined: \'`BINARY_OP_XOR\'\n      `BINARY_OP_XOR:\n      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_binary_op.v:84: Define or directive not defined: \'`BINARY_OP_XNOR\'\n      `BINARY_OP_XNOR:\n      ^~~~~~~~~~~~~~~\n%Error: Cannot continue\n'
module c_binary_op
  (data_in, data_out);
   
`include "c_constants.v"


   parameter num_ports = 2;
   

   parameter width = 1;
   

   parameter op = `BINARY_OP_XOR;
   

   input [0:width*num_ports-1] data_in;
   

   output [0:width-1] data_out;
   wire [0:width-1] data_out;
   
   generate
      
      genvar 	    i;
      for(i = 0; i < width; i = i + 1)
	begin:bit_positions
	   
	   wire [0:num_ports-1] data;
	   
	   genvar 		j;
	   for(j = 0; j < num_ports; j = j + 1)
	     begin:input_ports
		assign data[j] = data_in[j*width+i];
	     end
	   
	   case(op)
	     
	     `BINARY_OP_AND:
	       assign data_out[i] = &data;
	     
	     `BINARY_OP_NAND:
	       assign data_out[i] = ~&data;
	     
	     `BINARY_OP_OR:
	       assign data_out[i] = |data;
	     
	     `BINARY_OP_NOR:
	       assign data_out[i] = ~|data;
	     
	     `BINARY_OP_XOR:
	       assign data_out[i] = ^data;
	     
	     `BINARY_OP_XNOR:
	       assign data_out[i] = ~^data;
	     
	   endcase
	   
	end
      
   endgenerate
   
endmodule
module c_binary_op
  (data_in, data_out);

   
`include "c_constants.v"


   parameter num_ports = 2;
   

   parameter width = 1;
   

   parameter op = `BINARY_OP_XOR;
   

   input [0:width*num_ports-1] data_in;
   

   output [0:width-1] data_out;
   wire [0:width-1] data_out;
   
   generate
      
      genvar 	    i;
      for(i = 0; i < width; i = i + 1)
	begin:bit_positions
	   
	   wire [0:num_ports-1] data;
	   
	   genvar 		j;
	   for(j = 0; j < num_ports; j = j + 1)
	     begin:input_ports
		assign data[j] = data_in[j*width+i];
	     end
	   
	   case(op)
	     
	     `BINARY_OP_AND:
	       assign data_out[i] = &data;
	     
	     `BINARY_OP_NAND:
	       assign data_out[i] = ~&data;
	     
	     `BINARY_OP_OR:
	       assign data_out[i] = |data;
	     
	     `BINARY_OP_NOR:
	       assign data_out[i] = ~|data;
	     
	     `BINARY_OP_XOR:
	       assign data_out[i] = ^data;
	     
	     `BINARY_OP_XNOR:
	       assign data_out[i] = ~^data;
	     
	   endcase
	   
	end
      
   endgenerate
   
endmodule