data/full_repos/permissive/492007370/YODA_MinMax/YODA_MinMax.srcs/sources_1/new/STDDev.v
1: b'%Warning-WIDTH: data/full_repos/permissive/492007370/YODA_MinMax/YODA_MinMax.srcs/sources_1/new/STDDev.v:127: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 16 bits.\n                                                                                                            : ... In instance std\n    x_value = rom_memory[i];             \n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/492007370/YODA_MinMax/YODA_MinMax.srcs/sources_1/new/STDDev.v:128: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'mean\' generates 1 bits.\n                                                                                                            : ... In instance std\n    top=x_value-mean;                    \n               ^\n%Error: Exiting due to 2 warning(s)\n'
module std(
    input clk, mean,
    output reg [15:0] std
    );

parameter SIZE = 1024;
reg [15:0] rom_memory [SIZE-1:0];
integer i, std_sum,x_value, count,top,top_sqrd,inside_brackets;


    reg [15:0] sqr;



    function [15:0] sqrt;
        input [31:0] num;

        reg [31:0] a;
        reg [15:0] q;
        reg [17:0] left,right,r;    
        integer i;
    begin

        a = num;
        q = 0;
        i = 0;
        left = 0;
        right = 0;
        r = 0;

        for(i=0;i<16;i=i+1) begin 
            right = {q,r[17],1'b1};
            left = {r[15:0],a[31:30]};
            a = {a[29:0],2'b00};
            if (r[17] == 1)
                r = left + right;
            else
                r = left - right;
            q = {q[14:0],!r[17]};       
        end
        sqrt = q;
    end
    endfunction


initial begin
    $readmemh("sine_LUT_values.mem", rom_memory);
    i = 0;
    std=0;
    count=1;


    x_value=0;
    top=0;
    top_sqrd=0;
    std_sum=0;
    inside_brackets=0;

end

always@(posedge clk) begin
    x_value = rom_memory[i];
    top=x_value-mean;
    top_sqrd=top*top;
    std_sum=std_sum+top_sqrd;
    i =  i+ 1;
    count=count+1;
    inside_brackets=std_sum/count;
    std = sqrt(inside_brackets);
    
    if(i == SIZE)
        i = 0;
end

endmodule
module std(
    input clk, mean,
    output reg [15:0] std
    );


parameter SIZE = 1024;
reg [15:0] rom_memory [SIZE-1:0];
integer i, std_sum,x_value, count,top,top_sqrd,inside_brackets;


    reg [15:0] sqr;



    function [15:0] sqrt;
        input [31:0] num;

        reg [31:0] a;
        reg [15:0] q;
        reg [17:0] left,right,r;    
        integer i;
    begin

        a = num;
        q = 0;
        i = 0;
        left = 0;
        right = 0;
        r = 0;

        for(i=0;i<16;i=i+1) begin 
            right = {q,r[17],1'b1};
            left = {r[15:0],a[31:30]};
            a = {a[29:0],2'b00};
            if (r[17] == 1)
                r = left + right;
            else
                r = left - right;
            q = {q[14:0],!r[17]};       
        end
        sqrt = q;
    end
    endfunction


initial begin
    $readmemh("sine_LUT_values.mem", rom_memory);
    i = 0;
    std=0;
    count=1;


    x_value=0;
    top=0;
    top_sqrd=0;
    std_sum=0;
    inside_brackets=0;

end

always@(posedge clk) begin
    x_value = rom_memory[i];
    top=x_value-mean;
    top_sqrd=top*top;
    std_sum=std_sum+top_sqrd;
    i =  i+ 1;
    count=count+1;
    inside_brackets=std_sum/count;
    std = sqrt(inside_brackets);
    
    if(i == SIZE)
        i = 0;
end

endmodule