data/full_repos/permissive/446623173/tb2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/446623173/tb2.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/446623173/tb2.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #100000$finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/446623173/tb2.v:71: Unsupported: Ignoring delay on this delayed statement.\nalways #10 clk = ~ clk;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/446623173/tb2.v:72: Unsupported: Ignoring delay on this delayed statement.\nalways #2500button = ~ button;      \n       ^\n%Error: data/full_repos/permissive/446623173/tb2.v:38: Cannot find file containing module: \'system\'\n system uut (\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/446623173,data/full_repos/permissive/446623173/system\n             data/full_repos/permissive/446623173,data/full_repos/permissive/446623173/system.v\n             data/full_repos/permissive/446623173,data/full_repos/permissive/446623173/system.sv\n             system\n             system.v\n             system.sv\n             obj_dir/system\n             obj_dir/system.v\n             obj_dir/system.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb2;


	reg clk;
	reg reset;
	reg button;
	reg [31:0] message1;
	reg [31:0] message2;
	
	wire [3:0]hex0;
	wire [3:0]hex1;
	wire [3:0]hex2;
	wire [3:0]hex3;

	system uut (
		.clk(clk), 
		.reset(reset),
		.button(button),
		.message1(message1),
		.message2(message2),
		.hex0(hex0),
		.hex1(hex1),
		.hex2(hex2),
		.hex3(hex3)
	);

	initial begin

		reset = 1;
		clk = 0;
		button=0;
		
		message1=32'b00000001001000110100010101100111;
		message2=32'b10001001101010111100110111101111;


		#100;
        

		reset=0;
		button=1;
		

		#100000$finish;
		
	end
	
always #10 clk = ~ clk;
always #2500button = ~ button;      
endmodule
module tb2;



	reg clk;
	reg reset;
	reg button;
	reg [31:0] message1;
	reg [31:0] message2;
	
	wire [3:0]hex0;
	wire [3:0]hex1;
	wire [3:0]hex2;
	wire [3:0]hex3;

	system uut (
		.clk(clk), 
		.reset(reset),
		.button(button),
		.message1(message1),
		.message2(message2),
		.hex0(hex0),
		.hex1(hex1),
		.hex2(hex2),
		.hex3(hex3)
	);

	initial begin

		reset = 1;
		clk = 0;
		button=0;
		
		message1=32'b00000001001000110100010101100111;
		message2=32'b10001001101010111100110111101111;


		#100;
        

		reset=0;
		button=1;
		

		#100000$finish;
		
	end
	
always #10 clk = ~ clk;
always #2500button = ~ button;      
endmodule