data/full_repos/permissive/458134463/Modules/mux2x1_32bit_tb.v
1: b'%Error: data/full_repos/permissive/458134463/Modules/mux2x1_32bit_tb.v:18: Unsupported or unknown PLI call: $monitor\n$monitor("Inputs(32 bit -> hexadecimal)\\n------\\n0) %8h \\n1) %8h \\n",\n^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/mux2x1_32bit_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/458134463/Modules/mux2x1_32bit_tb.v:28: Unsupported or unknown PLI call: $monitor\n#5 $monitor("\\nTime  : %1d\\nselect: %1b\\nresult: %8h", $time, select, result);\n   ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/mux2x1_32bit_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n#5 $monitor("\\nTime  : %1d\\nselect: %1b\\nresult: %8h", $time, select, result);\n^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux2x1_32bit_tb();

reg select;
reg [31:0] input1;
reg [31:0] input2;

wire [31:0] result;


mux2x1_32bit mux(input1, input2, select, result);


initial begin
input1 = 32'hAAAAAAAA; 
input2 = 32'h11111111;

$monitor("Inputs(32 bit -> hexadecimal)\n------\n0) %8h \n1) %8h \n",
			input1,
			input2);

select = 1'b0;
#`DELAY
select = 1'b1;
end

initial begin
#5 $monitor("\nTime  : %1d\nselect: %1b\nresult: %8h", $time, select, result);
end

endmodule
module mux2x1_32bit_tb();


reg select;
reg [31:0] input1;
reg [31:0] input2;

wire [31:0] result;


mux2x1_32bit mux(input1, input2, select, result);


initial begin
input1 = 32'hAAAAAAAA; 
input2 = 32'h11111111;

$monitor("Inputs(32 bit -> hexadecimal)\n------\n0) %8h \n1) %8h \n",
			input1,
			input2);

select = 1'b0;
#`DELAY
select = 1'b1;
end

initial begin
#5 $monitor("\nTime  : %1d\nselect: %1b\nresult: %8h", $time, select, result);
end

endmodule