data/full_repos/permissive/469979476/language/8.v
data/verilator_xmls/64e4dcf4-ef49-40de-92f2-78a11f95ce18.xml
module top_module( 
    input a, 
    input b, 
    output out );
    assign out = ~(a^b);
endmodule
module top_module( 
    input a, 
    input b, 
    output out );

    assign out = ~(a^b);
endmodule