data/full_repos/permissive/482979608/ADPCM.srcs/sim_1/new/tb_ADPCM.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/482979608/ADPCM.srcs/sim_1/new/tb_ADPCM.v:32: Unsupported: Ignoring delay on this delayed statement.\n    always #(ClockPeriod/2) CLK = ~CLK;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/482979608/ADPCM.srcs/sim_1/new/tb_ADPCM.v:36: Unsupported: $fopen with multichannel descriptor.  Add ,"w" as second argument to open a file descriptor.\n        c = $fopen("codeSignBinaryOutputs.txt");\n            ^~~~~~\n%Error: data/full_repos/permissive/482979608/ADPCM.srcs/sim_1/new/tb_ADPCM.v:43: syntax error, unexpected \'@\'\n        @(posedge CLK) EN =\'b1; RST = \'b0;\n        ^\n%Error: data/full_repos/permissive/482979608/ADPCM.srcs/sim_1/new/tb_ADPCM.v:46: syntax error, unexpected \'@\'\n            @(posedge CLK) x = inputValues[i]; $fwrite(c,"%b\\n",codeSign);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/482979608/ADPCM.srcs/sim_1/new/tb_ADPCM.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #10 $fclose(c); $finish;\n    ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_ADPCM;
    parameter WLI = 1, WLF = 15, WL = WLI + WLF; 
    reg CLK, RST, EN;
    reg signed [WL-1:0] x;
    wire codeWord;
    wire signed [1:0] codeSign;
    
    ADPCM #(.WLI(WLI),.WLF(WLF)) DUT (.CLK(CLK),.RST(RST),.EN(EN),.x(x),.codeWord(codeWord),.codeSign(codeSign));
    
    parameter ClockPeriod = 10;
    initial CLK = 0;
    always #(ClockPeriod/2) CLK = ~CLK;
    
    integer c;
    initial begin
        c = $fopen("codeSignBinaryOutputs.txt");
    end
    integer i;
    reg [15:0] inputValues [220567:0];
    
    initial begin
        RST = 'b1;
        @(posedge CLK) EN ='b1; RST = 'b0;
        $readmemb("gettysbergBinaryInputs.mem", inputValues);
        for(i = 0; i < 220568; i=i+1) begin
            @(posedge CLK) x = inputValues[i]; $fwrite(c,"%b\n",codeSign);
        end           
        $fwrite(c,"%b\n",codeSign);
    #10 $fclose(c); $finish;
    end
endmodule
module tb_ADPCM;

    parameter WLI = 1, WLF = 15, WL = WLI + WLF; 
    reg CLK, RST, EN;
    reg signed [WL-1:0] x;
    wire codeWord;
    wire signed [1:0] codeSign;
    
    ADPCM #(.WLI(WLI),.WLF(WLF)) DUT (.CLK(CLK),.RST(RST),.EN(EN),.x(x),.codeWord(codeWord),.codeSign(codeSign));
    
    parameter ClockPeriod = 10;
    initial CLK = 0;
    always #(ClockPeriod/2) CLK = ~CLK;
    
    integer c;
    initial begin
        c = $fopen("codeSignBinaryOutputs.txt");
    end
    integer i;
    reg [15:0] inputValues [220567:0];
    
    initial begin
        RST = 'b1;
        @(posedge CLK) EN ='b1; RST = 'b0;
        $readmemb("gettysbergBinaryInputs.mem", inputValues);
        for(i = 0; i < 220568; i=i+1) begin
            @(posedge CLK) x = inputValues[i]; $fwrite(c,"%b\n",codeSign);
        end           
        $fwrite(c,"%b\n",codeSign);
    #10 $fclose(c); $finish;
    end
endmodule