data/full_repos/permissive/446312960/Verilog_Simulation/04_demux/demux_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/04_demux/demux_test.v:14: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/04_demux/demux_test.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/04_demux/demux_test.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/04_demux/demux_test.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module demux_test(t1, t2, p1, p2, p3, p4);
output t1;
output [1:0]t2;
input p1, p2, p3, p4;


reg       t1;
reg [1:0] t2;

initial begin
   t1 <= 1'b1;
   t2 <= 2'b00;

   #100;
   t2 <= 2'b01;

    #100;
   t2 <= 2'b10;

    #100;
   t2 <= 2'b11;

    #100;
   $finish;
end

endmodule
module demux_test(t1, t2, p1, p2, p3, p4);

output t1;
output [1:0]t2;
input p1, p2, p3, p4;


reg       t1;
reg [1:0] t2;

initial begin
   t1 <= 1'b1;
   t2 <= 2'b00;

   #100;
   t2 <= 2'b01;

    #100;
   t2 <= 2'b10;

    #100;
   t2 <= 2'b11;

    #100;
   $finish;
end

endmodule