data/full_repos/permissive/441359809/src/yosys/manual/PRESENTATION_ExAdv/mymul_test.v
data/verilator_xmls/fc27bfc0-68a2-47de-ab51-74c898f46970.xml
module test(A, B, Y);
    input  [1:0] A, B;
    output [1:0] Y = A * B;
endmodule
module test(A, B, Y);

    input  [1:0] A, B;
    output [1:0] Y = A * B;
endmodule