data/full_repos/permissive/512077043/rgb_sinp/rgb_sinp.v
1: b'%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_sinp/rgb_sinp.v:105: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                            : ... In instance rgb_sinp\n                    count <= 1\'b1;\n                          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module  rgb_sinp #(
    

    parameter COUNTER_MAX = 5000,
    parameter STREAM_RESET_CLKS = 4800,
    parameter SAMPLE_TIME_CLKS   = 57
) (


    input           clk,
    input           rst,
    input           sig,
    

    output  reg     strobe,
    output  reg     sbit_value,
    output  reg     stream_reset
);


    localparam WIDTH = $clog2(COUNTER_MAX + 1);
    

    wire            sig_edge;


    reg             ff_1;
    reg             ff_2;
    reg             strobe_stretch;
    reg             rstff_1;
    reg             rstff_2;
    reg [WIDTH-1:0] count = 0;

    

    assign sig_edge = ff_1 ^ ff_2;


    always @ (posedge clk) begin

        if (rst == 1'b1) begin
            rstff_2 <= 1'b1;
            rstff_1 <= 1'b1;
        end else begin
            rstff_2 <= rstff_1;
            rstff_1 <= 1'b0;
        end


        if (rstff_2 == 1'b1) begin
            ff_1 <= ~sig;
            ff_2 <= 1'b0;
            sbit_value <= 1'b0;
            strobe <= 1'b0;
            strobe_stretch <= 1'b0;
            stream_reset <= 1'b0;
            count <= 0;
        

        end else begin
            ff_1 <= sig;
            ff_2 <= ff_1;
            if (sig_edge) begin
                if (ff_1 == 1'b1) begin
                    count <= 1'b1;
                    strobe <= 1'b0;
                    strobe_stretch <= 1'b0;
                    sbit_value <= 1'b0;
                    stream_reset <= 1'b0;
                end
            end else begin

                if (strobe == 1'b1) begin
                    if (strobe_stretch == 1'b1) begin
                        strobe_stretch <= 1'b0;
                    end else begin
                        strobe <= 1'b0;
                        sbit_value <= 1'b0;
                        stream_reset <= 1'b0;
                    end
                end

                if (count < SAMPLE_TIME_CLKS) begin
                    count <= count + 1;
                end else if (count == SAMPLE_TIME_CLKS) begin
                    count <= count + 1;
                    strobe <= 1'b1;
                    strobe_stretch <= 1'b1;
                    sbit_value <= ff_2;
                end else if (count < STREAM_RESET_CLKS) begin
                    count <= count + 1;
                end else if (count == STREAM_RESET_CLKS) begin
                    count <= count + 1;
                    strobe <= 1'b1;
                    strobe_stretch <= 1'b1;
                    stream_reset <= 1'b1;
                end
            end
        end
    end
    
endmodule
module  rgb_sinp #(
    

    parameter COUNTER_MAX = 5000,
    parameter STREAM_RESET_CLKS = 4800,
    parameter SAMPLE_TIME_CLKS   = 57
) (


    input           clk,
    input           rst,
    input           sig,
    

    output  reg     strobe,
    output  reg     sbit_value,
    output  reg     stream_reset
);



    localparam WIDTH = $clog2(COUNTER_MAX + 1);
    

    wire            sig_edge;


    reg             ff_1;
    reg             ff_2;
    reg             strobe_stretch;
    reg             rstff_1;
    reg             rstff_2;
    reg [WIDTH-1:0] count = 0;

    

    assign sig_edge = ff_1 ^ ff_2;


    always @ (posedge clk) begin

        if (rst == 1'b1) begin
            rstff_2 <= 1'b1;
            rstff_1 <= 1'b1;
        end else begin
            rstff_2 <= rstff_1;
            rstff_1 <= 1'b0;
        end


        if (rstff_2 == 1'b1) begin
            ff_1 <= ~sig;
            ff_2 <= 1'b0;
            sbit_value <= 1'b0;
            strobe <= 1'b0;
            strobe_stretch <= 1'b0;
            stream_reset <= 1'b0;
            count <= 0;
        

        end else begin
            ff_1 <= sig;
            ff_2 <= ff_1;
            if (sig_edge) begin
                if (ff_1 == 1'b1) begin
                    count <= 1'b1;
                    strobe <= 1'b0;
                    strobe_stretch <= 1'b0;
                    sbit_value <= 1'b0;
                    stream_reset <= 1'b0;
                end
            end else begin

                if (strobe == 1'b1) begin
                    if (strobe_stretch == 1'b1) begin
                        strobe_stretch <= 1'b0;
                    end else begin
                        strobe <= 1'b0;
                        sbit_value <= 1'b0;
                        stream_reset <= 1'b0;
                    end
                end

                if (count < SAMPLE_TIME_CLKS) begin
                    count <= count + 1;
                end else if (count == SAMPLE_TIME_CLKS) begin
                    count <= count + 1;
                    strobe <= 1'b1;
                    strobe_stretch <= 1'b1;
                    sbit_value <= ff_2;
                end else if (count < STREAM_RESET_CLKS) begin
                    count <= count + 1;
                end else if (count == STREAM_RESET_CLKS) begin
                    count <= count + 1;
                    strobe <= 1'b1;
                    strobe_stretch <= 1'b1;
                    stream_reset <= 1'b1;
                end
            end
        end
    end
    
endmodule