data/full_repos/permissive/46981098/mux/mux5_2to1.v
data/verilator_xmls/5ee641a9-1a14-4ad2-9599-537fb3f72ec5.xml
module mux5_2to1(out, in0, in1, sel);
	output reg  [4:0] out;
	input [4:0] in0;
	input [4:0] in1;
	input sel;

  	always @(sel)
    begin
		case (sel)
			1'b0: out = in0;
			1'b1: out = in1;
		endcase
    end
endmodule
module mux5_2to1(out, in0, in1, sel);

	output reg  [4:0] out;
	input [4:0] in0;
	input [4:0] in1;
	input sel;

  	always @(sel)
    begin
		case (sel)
			1'b0: out = in0;
			1'b1: out = in1;
		endcase
    end
endmodule