data/full_repos/permissive/476728999/Experiment4/decoder_3x8.v
data/verilator_xmls/0525e90a-6240-49bf-b6a9-016d40d95d21.xml
module decoder_3x8(a,b,c,en,d);

    input a,b,c,en;
    output [7:0] d;
    

    assign d[0] = en & ~a & ~b & ~c;
    assign d[1] = en & ~a & ~b & c;
    assign d[2] = en & ~a & b & ~c;
    assign d[3] = en & ~a & b & c;
    assign d[4] = en & a & ~b & ~c;
    assign d[5] = en & a & ~b & c;
    assign d[6] = en & a & b & ~c;
    assign d[7] = en & a & b & c;
    
endmodule
module decoder_3x8(a,b,c,en,d);


    input a,b,c,en;
    output [7:0] d;
    

    assign d[0] = en & ~a & ~b & ~c;
    assign d[1] = en & ~a & ~b & c;
    assign d[2] = en & ~a & b & ~c;
    assign d[3] = en & ~a & b & c;
    assign d[4] = en & a & ~b & ~c;
    assign d[5] = en & a & ~b & c;
    assign d[6] = en & a & b & ~c;
    assign d[7] = en & a & b & c;
    
endmodule