data/full_repos/permissive/420518472/testbenches/test_uart_comm.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:10: Unsupported: Ignoring delay on this delayed statement.\n initial while(1) #5 comm_clk = ~comm_clk;\n                  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:11: Unsupported: Ignoring delay on this delayed statement.\n initial while(1) #1 hash_clk = ~hash_clk;\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:132: Unsupported: Ignoring delay on this delayed statement.\n  #30000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:145: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:191: syntax error, unexpected \'@\'\n  @(posedge uut.meta_new_golden_nonce);\n  ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:240: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("uart_comm_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:241: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, uut);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:247: Unsupported: Ignoring delay on this delayed statement.\n  #1600;\n  ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:257: syntax error, unexpected byte, expecting IDENTIFIER\n input [7:0] byte;\n             ^~~~\n%Error: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:260: syntax error, unexpected \'[\', expecting "\'{"\n  uut_rx = byte[0]; #160\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:259: Unsupported: Ignoring delay on this delayed statement.\n  uut_rx = 0;       #160\n                    ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:261: syntax error, unexpected \'[\', expecting "\'{"\n  uut_rx = byte[1]; #160;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:260: Unsupported: Ignoring delay on this delayed statement.\n  uut_rx = byte[0]; #160\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:261: Unsupported: Ignoring delay on this delayed statement.\n  uut_rx = byte[1]; #160;\n                    ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:262: syntax error, unexpected \'[\', expecting "\'{"\n  uut_rx = byte[2]; #160;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:262: Unsupported: Ignoring delay on this delayed statement.\n  uut_rx = byte[2]; #160;\n                    ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:263: syntax error, unexpected \'[\', expecting "\'{"\n  uut_rx = byte[3]; #160;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:263: Unsupported: Ignoring delay on this delayed statement.\n  uut_rx = byte[3]; #160;\n                    ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:264: syntax error, unexpected \'[\', expecting "\'{"\n  uut_rx = byte[4]; #160;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:264: Unsupported: Ignoring delay on this delayed statement.\n  uut_rx = byte[4]; #160;\n                    ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:265: syntax error, unexpected \'[\', expecting "\'{"\n  uut_rx = byte[5]; #160;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:265: Unsupported: Ignoring delay on this delayed statement.\n  uut_rx = byte[5]; #160;\n                    ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:266: syntax error, unexpected \'[\', expecting "\'{"\n  uut_rx = byte[6]; #160;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:266: Unsupported: Ignoring delay on this delayed statement.\n  uut_rx = byte[6]; #160;\n                    ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:267: syntax error, unexpected \'[\', expecting "\'{"\n  uut_rx = byte[7]; #160;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:267: Unsupported: Ignoring delay on this delayed statement.\n  uut_rx = byte[7]; #160;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:268: Unsupported: Ignoring delay on this delayed statement.\n  uut_rx = 1; #160;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:270: Unsupported: Ignoring delay on this delayed statement.\n  while (($random & 3) != 0) #10;\n                             ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:286: syntax error, unexpected byte, expecting IDENTIFIER\n output [7:0] byte;\n              ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:289: Unsupported: Ignoring delay on this delayed statement.\n  #80;\n  ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:295: syntax error, unexpected \'[\', expecting "\'{"\n  #160 byte[0] = uut_tx;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:295: Unsupported: Ignoring delay on this delayed statement.\n  #160 byte[0] = uut_tx;\n  ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:296: syntax error, unexpected \'[\', expecting "\'{"\n  #160 byte[1] = uut_tx;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:296: Unsupported: Ignoring delay on this delayed statement.\n  #160 byte[1] = uut_tx;\n  ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:297: syntax error, unexpected \'[\', expecting "\'{"\n  #160 byte[2] = uut_tx;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:297: Unsupported: Ignoring delay on this delayed statement.\n  #160 byte[2] = uut_tx;\n  ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:298: syntax error, unexpected \'[\', expecting "\'{"\n  #160 byte[3] = uut_tx;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:298: Unsupported: Ignoring delay on this delayed statement.\n  #160 byte[3] = uut_tx;\n  ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:299: syntax error, unexpected \'[\', expecting "\'{"\n  #160 byte[4] = uut_tx;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:299: Unsupported: Ignoring delay on this delayed statement.\n  #160 byte[4] = uut_tx;\n  ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:300: syntax error, unexpected \'[\', expecting "\'{"\n  #160 byte[5] = uut_tx;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:300: Unsupported: Ignoring delay on this delayed statement.\n  #160 byte[5] = uut_tx;\n  ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:301: syntax error, unexpected \'[\', expecting "\'{"\n  #160 byte[6] = uut_tx;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:301: Unsupported: Ignoring delay on this delayed statement.\n  #160 byte[6] = uut_tx;\n  ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:302: syntax error, unexpected \'[\', expecting "\'{"\n  #160 byte[7] = uut_tx;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:302: Unsupported: Ignoring delay on this delayed statement.\n  #160 byte[7] = uut_tx;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:303: Unsupported: Ignoring delay on this delayed statement.\n  #160;\n  ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:314: syntax error, unexpected byte, expecting IDENTIFIER\n input [7:0] byte;\n             ^~~~\n%Error: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:315: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [7:0] tmp;\n           ^~~\n%Error: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:319: syntax error, unexpected \')\', expecting "\'{"\n  if (tmp != byte)\n                 ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_uart_comm.v:324: syntax error, unexpected end\n end\n ^~~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module uart_comm_tb;
	`define SIM 1


	reg comm_clk = 0;
	reg hash_clk = 0;
	initial while(1) #5 comm_clk = ~comm_clk;
	initial while(1) #1 hash_clk = ~hash_clk;

	reg test_passed = 0;


	reg uut_rx = 1'b1;
	reg uut_need_work = 1'b0;
	reg uut_new_nonce = 1'b0;
	reg [31:0] uut_golden_nonce = 32'd0;

	wire uut_tx;
	wire uut_new_work;
	wire [255:0] uut_midstate;
	wire [95:0] uut_data;
	wire [31:0] uut_noncemin, uut_noncemax;

	localparam baud_rate = 1;
	localparam sys_clk_freq = 16;


	uart_comm #(
		.baud_rate(baud_rate),
		.sys_clk_freq(sys_clk_freq)
	) uut (
		.hash_clk (hash_clk),
        .comm_clk (comm_clk),
        .work_data (uut_data),
		.nonce_min (uut_noncemin),
		.nonce_max (uut_noncemax),
        .midstate (uut_midstate),
        .rx_serial (uut_rx),
		.tx_serial (uut_tx),
		.new_work (uut_new_work),
		.new_golden_nonce (uut_new_nonce),
		.golden_nonce (uut_golden_nonce)

	);


	initial
	begin
		#100;
		uart_delay;


		uart_send_byte (8'h00);
		uart_delay;


		uart_send_byte (8'h08);
		uart_send_byte (8'h00);
		uart_send_byte (8'h00);
		uart_send_byte (8'h00);
		uart_send_byte (8'hf9);
		uart_send_byte (8'hea);
		uart_send_byte (8'h98);
		uart_send_byte (8'h0a);
		uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay;
		uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay;


		uart_send_byte (8'h6);
		uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay;


		uart_send_byte (8'd60);
		uart_send_byte (8'h00);
		uart_send_byte (8'h00);
		uart_send_byte (8'h02);
		uart_send_word (32'h00000000);
		uart_send_word (32'hFFFFFFFF);
		uart_send_word (32'h0b0a0908);
		uart_send_word (32'h0f0e0d0c);
		uart_send_word (32'h13121110);
		uart_send_word (32'h17161514);
		uart_send_word (32'h1b1a1918);
		uart_send_word (32'h1f1e1d1c);
		uart_send_word (32'h23222120);
		uart_send_word (32'h27262524);
		uart_send_word (32'h2b2a2928);
		uart_send_word (32'h2f2e2d2c);
		uart_send_word (32'h33323130);
		uart_send_word (32'h4ec14d61);
		uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay;


































		uut_golden_nonce <= 32'h38b9b05a;
		uut_new_nonce <= 1;

		#30000;
		if (test_passed)
			$display ("\n*** TEST PASSED ***\n");
		else
			$display ("TEST FAILED: Not enough output data.\n");
		$finish;
	end


	reg tmp;

	initial
	begin
		#100;


		$display ("\nExpecting PONG...");
		uart_expect_byte (8'h01);
		$display ("PASSED: PONG\n");


		$display ("Expecting INFO...");
		uart_expect_byte (8'd16);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'hde);
		uart_expect_byte (8'had);
		uart_expect_byte (8'hbe);
		uart_expect_byte (8'hef);
		uart_expect_byte (8'h13);
		uart_expect_byte (8'h37);
		uart_expect_byte (8'h0d);
		uart_expect_byte (8'h13);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		$display ("PASSED: INFO\n");


		$display ("Expecting INVALID...");
		uart_expect_byte (8'd08);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd01);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		$display ("PASSED: INVALID\n");


		$display ("Expecting ACK for push job...");
		uart_expect_byte (8'd01);
		$display ("PASSED: ACK\n");

		$display ("Expecting MSG_NONCE...");

		@(posedge uut.meta_new_golden_nonce);
		uart_expect_byte (8'd8);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd03);
		uart_expect_byte (8'h38);
		uart_expect_byte (8'hb9);
		uart_expect_byte (8'hb0);
		uart_expect_byte (8'h5a);
		$display ("PASSED: MSG_NONCE\n");


























		if (uut_noncemin != 32'hFFFFFFFF || uut_noncemax != 32'h00000000 || uut_data != 96'h131211100f0e0d0c0b0a0908 || uut_midstate != 256'h333231302f2e2d2c2b2a292827262524232221201f1e1d1c1b1a191817161514)
		begin
			$display ("TEST FAILED: Incorrect job:\n");
			$display ("noncemin: %4X\nnoncemax: %4X\ndata: %24X\nmidstate: %64X\n", uut_noncemin, uut_noncemax, uut_data, uut_midstate);
			$finish;
		end

		test_passed = 1;
	end


	initial
	begin
		$dumpfile("uart_comm_tb.vcd");
		$dumpvars(0, uut);
	end


	task uart_delay;
	begin
		#1600;
	end
	endtask






	task uart_send_byte;
	input [7:0] byte;
	begin
		uut_rx = 0;       #160
		uut_rx = byte[0]; #160
		uut_rx = byte[1]; #160;
		uut_rx = byte[2]; #160;
		uut_rx = byte[3]; #160;
		uut_rx = byte[4]; #160;
		uut_rx = byte[5]; #160;
		uut_rx = byte[6]; #160;
		uut_rx = byte[7]; #160;
		uut_rx = 1; #160;

		while (($random & 3) != 0) #10;
	end
	endtask


	task uart_send_word;
	input [31:0] word;
	begin
		uart_send_byte (word[7:0]);
		uart_send_byte (word[15:8]);
		uart_send_byte (word[23:16]);
		uart_send_byte (word[31:24]);
	end
	endtask

	task uart_recv_byte;
	output [7:0] byte;
	begin
		@ (negedge uut_tx);
		#80;
		if (uut_tx)
		begin
			$display ("TEST FAILED: Floating start bit on uut_tx.\n");
			$finish;
		end
		#160 byte[0] = uut_tx;
		#160 byte[1] = uut_tx;
		#160 byte[2] = uut_tx;
		#160 byte[3] = uut_tx;
		#160 byte[4] = uut_tx;
		#160 byte[5] = uut_tx;
		#160 byte[6] = uut_tx;
		#160 byte[7] = uut_tx;
		#160;
		if (~uut_tx)
		begin
			$display ("TEST FAILED: Floating stop bit on uut_tx.\n");
			$finish;
		end
	end
	endtask


	task uart_expect_byte;
	input [7:0] byte;
	reg [7:0] tmp;
	begin
		uart_recv_byte (tmp);

		if (tmp != byte)
		begin
			$display ("TEST FAILED: Expected 0x%02X got 0x%02X.", byte, tmp);
			$finish;
		end
	end
	endtask

endmodule
module uart_comm_tb;

	`define SIM 1


	reg comm_clk = 0;
	reg hash_clk = 0;
	initial while(1) #5 comm_clk = ~comm_clk;
	initial while(1) #1 hash_clk = ~hash_clk;

	reg test_passed = 0;


	reg uut_rx = 1'b1;
	reg uut_need_work = 1'b0;
	reg uut_new_nonce = 1'b0;
	reg [31:0] uut_golden_nonce = 32'd0;

	wire uut_tx;
	wire uut_new_work;
	wire [255:0] uut_midstate;
	wire [95:0] uut_data;
	wire [31:0] uut_noncemin, uut_noncemax;

	localparam baud_rate = 1;
	localparam sys_clk_freq = 16;


	uart_comm #(
		.baud_rate(baud_rate),
		.sys_clk_freq(sys_clk_freq)
	) uut (
		.hash_clk (hash_clk),
        .comm_clk (comm_clk),
        .work_data (uut_data),
		.nonce_min (uut_noncemin),
		.nonce_max (uut_noncemax),
        .midstate (uut_midstate),
        .rx_serial (uut_rx),
		.tx_serial (uut_tx),
		.new_work (uut_new_work),
		.new_golden_nonce (uut_new_nonce),
		.golden_nonce (uut_golden_nonce)

	);


	initial
	begin
		#100;
		uart_delay;


		uart_send_byte (8'h00);
		uart_delay;


		uart_send_byte (8'h08);
		uart_send_byte (8'h00);
		uart_send_byte (8'h00);
		uart_send_byte (8'h00);
		uart_send_byte (8'hf9);
		uart_send_byte (8'hea);
		uart_send_byte (8'h98);
		uart_send_byte (8'h0a);
		uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay;
		uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay;


		uart_send_byte (8'h6);
		uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay;


		uart_send_byte (8'd60);
		uart_send_byte (8'h00);
		uart_send_byte (8'h00);
		uart_send_byte (8'h02);
		uart_send_word (32'h00000000);
		uart_send_word (32'hFFFFFFFF);
		uart_send_word (32'h0b0a0908);
		uart_send_word (32'h0f0e0d0c);
		uart_send_word (32'h13121110);
		uart_send_word (32'h17161514);
		uart_send_word (32'h1b1a1918);
		uart_send_word (32'h1f1e1d1c);
		uart_send_word (32'h23222120);
		uart_send_word (32'h27262524);
		uart_send_word (32'h2b2a2928);
		uart_send_word (32'h2f2e2d2c);
		uart_send_word (32'h33323130);
		uart_send_word (32'h4ec14d61);
		uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay;


































		uut_golden_nonce <= 32'h38b9b05a;
		uut_new_nonce <= 1;

		#30000;
		if (test_passed)
			$display ("\n*** TEST PASSED ***\n");
		else
			$display ("TEST FAILED: Not enough output data.\n");
		$finish;
	end


	reg tmp;

	initial
	begin
		#100;


		$display ("\nExpecting PONG...");
		uart_expect_byte (8'h01);
		$display ("PASSED: PONG\n");


		$display ("Expecting INFO...");
		uart_expect_byte (8'd16);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'hde);
		uart_expect_byte (8'had);
		uart_expect_byte (8'hbe);
		uart_expect_byte (8'hef);
		uart_expect_byte (8'h13);
		uart_expect_byte (8'h37);
		uart_expect_byte (8'h0d);
		uart_expect_byte (8'h13);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		$display ("PASSED: INFO\n");


		$display ("Expecting INVALID...");
		uart_expect_byte (8'd08);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd01);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		$display ("PASSED: INVALID\n");


		$display ("Expecting ACK for push job...");
		uart_expect_byte (8'd01);
		$display ("PASSED: ACK\n");

		$display ("Expecting MSG_NONCE...");

		@(posedge uut.meta_new_golden_nonce);
		uart_expect_byte (8'd8);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd03);
		uart_expect_byte (8'h38);
		uart_expect_byte (8'hb9);
		uart_expect_byte (8'hb0);
		uart_expect_byte (8'h5a);
		$display ("PASSED: MSG_NONCE\n");


























		if (uut_noncemin != 32'hFFFFFFFF || uut_noncemax != 32'h00000000 || uut_data != 96'h131211100f0e0d0c0b0a0908 || uut_midstate != 256'h333231302f2e2d2c2b2a292827262524232221201f1e1d1c1b1a191817161514)
		begin
			$display ("TEST FAILED: Incorrect job:\n");
			$display ("noncemin: %4X\nnoncemax: %4X\ndata: %24X\nmidstate: %64X\n", uut_noncemin, uut_noncemax, uut_data, uut_midstate);
			$finish;
		end

		test_passed = 1;
	end


	initial
	begin
		$dumpfile("uart_comm_tb.vcd");
		$dumpvars(0, uut);
	end


	task uart_delay;
	begin
		#1600;
	end
	endtask






	task uart_send_byte;
	input [7:0] byte;
	begin
		uut_rx = 0;       #160
		uut_rx = byte[0]; #160
		uut_rx = byte[1]; #160;
		uut_rx = byte[2]; #160;
		uut_rx = byte[3]; #160;
		uut_rx = byte[4]; #160;
		uut_rx = byte[5]; #160;
		uut_rx = byte[6]; #160;
		uut_rx = byte[7]; #160;
		uut_rx = 1; #160;

		while (($random & 3) != 0) #10;
	end
	endtask


	task uart_send_word;
	input [31:0] word;
	begin
		uart_send_byte (word[7:0]);
		uart_send_byte (word[15:8]);
		uart_send_byte (word[23:16]);
		uart_send_byte (word[31:24]);
	end
	endtask

	task uart_recv_byte;
	output [7:0] byte;
	begin
		@ (negedge uut_tx);
		#80;
		if (uut_tx)
		begin
			$display ("TEST FAILED: Floating start bit on uut_tx.\n");
			$finish;
		end
		#160 byte[0] = uut_tx;
		#160 byte[1] = uut_tx;
		#160 byte[2] = uut_tx;
		#160 byte[3] = uut_tx;
		#160 byte[4] = uut_tx;
		#160 byte[5] = uut_tx;
		#160 byte[6] = uut_tx;
		#160 byte[7] = uut_tx;
		#160;
		if (~uut_tx)
		begin
			$display ("TEST FAILED: Floating stop bit on uut_tx.\n");
			$finish;
		end
	end
	endtask


	task uart_expect_byte;
	input [7:0] byte;
	reg [7:0] tmp;
	begin
		uart_recv_byte (tmp);

		if (tmp != byte)
		begin
			$display ("TEST FAILED: Expected 0x%02X got 0x%02X.", byte, tmp);
			$finish;
		end
	end
	endtask

endmodule