data/full_repos/permissive/451970862/rtl/peripheral/gpio.v
data/verilator_xmls/96339a42-c5b2-4e8b-b35a-e07661a3d916.xml
module gpio (

input           sb_clk,
input           sb_rst_n,

input           sb_arvalid,
output          sb_arready,
input   [31:0]  sb_araddr,

output          sb_rvalid,
input           sb_rready,
output  [31:0]  sb_rdata,

input           sb_wvalid,
output          sb_wready,
input   [31:0]  sb_waddr,
input   [31:0]  sb_wdata,
input   [3:0]   sb_wstrb,

output          sb_bvalid,
input           sb_bready,
output          sb_bresp,

input   [15:0]  gpio_i,
output  [15:0]  gpio_o

);

reg   [15:0]  gpio_odr;

reg           sb_bvalid_r;
reg           sb_rvalid_r;
reg   [31:0]  sb_rdata_r;

assign        sb_wready   = 1'b1;
assign        sb_bvalid   = sb_bvalid_r;
assign        sb_bresp    = 1'b0;
assign        sb_arready  = 1'b1;
assign        sb_rvalid   = sb_rvalid_r;
assign        sb_rdata    = sb_rdata_r;



always @ (posedge sb_clk) begin
  if(!sb_rst_n) begin
    gpio_odr <= 16'b0;
    sb_bvalid_r <=  1'b0;
  end
  else if(sb_wvalid & sb_wready) begin
    if(~sb_waddr[2])
      gpio_odr  <= sb_wdata[15:0];
    sb_bvalid_r <= 1'b1;
  end
  else if(sb_bready) begin
    sb_bvalid_r <= 1'b0;
  end
end

always @ (posedge sb_clk) begin
  if(!sb_rst_n) begin
    sb_rdata_r <= 32'b0;
    sb_rvalid_r <=  1'b0;
  end
  else if(sb_arvalid & sb_arready) begin
    case (sb_araddr[2])
      1'b0: sb_rdata_r  <=  {16'b0,gpio_odr};
      1'b1: sb_rdata_r  <=  {16'b0,gpio_i};
    endcase
    sb_rvalid_r <= 1'b1;
  end
  else if(sb_rready) begin
    sb_rvalid_r <= 1'b0;
  end
end


assign  gpio_o = gpio_odr;

endmodule
module gpio (

input           sb_clk,
input           sb_rst_n,

input           sb_arvalid,
output          sb_arready,
input   [31:0]  sb_araddr,

output          sb_rvalid,
input           sb_rready,
output  [31:0]  sb_rdata,

input           sb_wvalid,
output          sb_wready,
input   [31:0]  sb_waddr,
input   [31:0]  sb_wdata,
input   [3:0]   sb_wstrb,

output          sb_bvalid,
input           sb_bready,
output          sb_bresp,

input   [15:0]  gpio_i,
output  [15:0]  gpio_o

);


reg   [15:0]  gpio_odr;

reg           sb_bvalid_r;
reg           sb_rvalid_r;
reg   [31:0]  sb_rdata_r;

assign        sb_wready   = 1'b1;
assign        sb_bvalid   = sb_bvalid_r;
assign        sb_bresp    = 1'b0;
assign        sb_arready  = 1'b1;
assign        sb_rvalid   = sb_rvalid_r;
assign        sb_rdata    = sb_rdata_r;



always @ (posedge sb_clk) begin
  if(!sb_rst_n) begin
    gpio_odr <= 16'b0;
    sb_bvalid_r <=  1'b0;
  end
  else if(sb_wvalid & sb_wready) begin
    if(~sb_waddr[2])
      gpio_odr  <= sb_wdata[15:0];
    sb_bvalid_r <= 1'b1;
  end
  else if(sb_bready) begin
    sb_bvalid_r <= 1'b0;
  end
end

always @ (posedge sb_clk) begin
  if(!sb_rst_n) begin
    sb_rdata_r <= 32'b0;
    sb_rvalid_r <=  1'b0;
  end
  else if(sb_arvalid & sb_arready) begin
    case (sb_araddr[2])
      1'b0: sb_rdata_r  <=  {16'b0,gpio_odr};
      1'b1: sb_rdata_r  <=  {16'b0,gpio_i};
    endcase
    sb_rvalid_r <= 1'b1;
  end
  else if(sb_rready) begin
    sb_rvalid_r <= 1'b0;
  end
end


assign  gpio_o = gpio_odr;

endmodule