data/full_repos/permissive/421380819/verilog/rtl/wishboneSlave/wbSlave.v
1: b'%Warning-WIDTH: data/full_repos/permissive/421380819/verilog/rtl/wishboneSlave/wbSlave.v:63: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                           : ... In instance wbSlave\n            ACK_O_Q     <= 1\'b0;\n                        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module wbSlave (

    input   wire            CLK_I,
    input   wire            RST_I,
    input   wire            STB_I,
    input   wire            CYC_I,
    input   wire            WE_I,
    input   wire    [3:0]   SEL_I,
    input   wire    [31:0]  DAT_I,
    input   wire    [31:0]  ADR_I,
    output  wire            ACK_O,
    output  wire    [31:0]  DAT_O,

    output  wire            CTRL_WE,
    output  wire    [3:0]   CTRL_ADDR,
    output  wire    [31:0]  CTRL_DATA_IN,
    input   wire    [31:0]  CTRL_DATA_OUT,

    output  wire            RAM_CSb,
    output  wire            RAM_WEb,
    output  wire    [7:0]   RAM_ADDR,
    output  wire    [31:0]  RAM_DATA_IN,
    input   wire    [31:0]  RAM_DATA_OUT
);


    reg     [1:0]   ACK_O_Q;

    wire            RAM_WE_i;
    reg             RAM_WE_Q;

    wire            CTRL_WE_i;
    reg             CTRL_WE_Q;


    assign RAM_CSb      = (ADR_I[7] == 1'b1) ? 1'b0 : 1'b1;
    assign RAM_WE_i     = (ADR_I[7] == 1'b1) ? CYC_I & STB_I & WE_I : 1'b0;
    assign RAM_WEb      = !(!RAM_WE_Q & RAM_WE_i);
    assign RAM_ADDR     = ADR_I[7:0];
    assign RAM_DATA_IN  = DAT_I;


    assign CTRL_WE_i    = (ADR_I[7] == 1'b0) ? CYC_I & STB_I & WE_I : 1'b0;
    assign CTRL_WE      = !CTRL_WE_Q & CTRL_WE_i;
    assign CTRL_ADDR    = ADR_I[3:0];
    assign CTRL_DATA_IN = DAT_I;


    assign DAT_O = (ADR_I[7] == 1'b1) ? RAM_DATA_OUT : CTRL_DATA_OUT;


    assign ACK_O = ((CYC_I & STB_I) == 1'b0) ? 1'b0 : ACK_O_Q[1];


    always @(posedge CLK_I, posedge RST_I) begin
        if (RST_I == 1'b1) begin
            ACK_O_Q     <= 1'b0;
            RAM_WE_Q    <= 1'b0;
            CTRL_WE_Q   <= 1'b0;
        end else begin
            ACK_O_Q         <= {ACK_O_Q[0], CYC_I & STB_I}; 
            RAM_WE_Q    <= RAM_WE_i;
            CTRL_WE_Q   <= CTRL_WE_i;
        end
    end
    
endmodule
module wbSlave (

    input   wire            CLK_I,
    input   wire            RST_I,
    input   wire            STB_I,
    input   wire            CYC_I,
    input   wire            WE_I,
    input   wire    [3:0]   SEL_I,
    input   wire    [31:0]  DAT_I,
    input   wire    [31:0]  ADR_I,
    output  wire            ACK_O,
    output  wire    [31:0]  DAT_O,

    output  wire            CTRL_WE,
    output  wire    [3:0]   CTRL_ADDR,
    output  wire    [31:0]  CTRL_DATA_IN,
    input   wire    [31:0]  CTRL_DATA_OUT,

    output  wire            RAM_CSb,
    output  wire            RAM_WEb,
    output  wire    [7:0]   RAM_ADDR,
    output  wire    [31:0]  RAM_DATA_IN,
    input   wire    [31:0]  RAM_DATA_OUT
);



    reg     [1:0]   ACK_O_Q;

    wire            RAM_WE_i;
    reg             RAM_WE_Q;

    wire            CTRL_WE_i;
    reg             CTRL_WE_Q;


    assign RAM_CSb      = (ADR_I[7] == 1'b1) ? 1'b0 : 1'b1;
    assign RAM_WE_i     = (ADR_I[7] == 1'b1) ? CYC_I & STB_I & WE_I : 1'b0;
    assign RAM_WEb      = !(!RAM_WE_Q & RAM_WE_i);
    assign RAM_ADDR     = ADR_I[7:0];
    assign RAM_DATA_IN  = DAT_I;


    assign CTRL_WE_i    = (ADR_I[7] == 1'b0) ? CYC_I & STB_I & WE_I : 1'b0;
    assign CTRL_WE      = !CTRL_WE_Q & CTRL_WE_i;
    assign CTRL_ADDR    = ADR_I[3:0];
    assign CTRL_DATA_IN = DAT_I;


    assign DAT_O = (ADR_I[7] == 1'b1) ? RAM_DATA_OUT : CTRL_DATA_OUT;


    assign ACK_O = ((CYC_I & STB_I) == 1'b0) ? 1'b0 : ACK_O_Q[1];


    always @(posedge CLK_I, posedge RST_I) begin
        if (RST_I == 1'b1) begin
            ACK_O_Q     <= 1'b0;
            RAM_WE_Q    <= 1'b0;
            CTRL_WE_Q   <= 1'b0;
        end else begin
            ACK_O_Q         <= {ACK_O_Q[0], CYC_I & STB_I}; 
            RAM_WE_Q    <= RAM_WE_i;
            CTRL_WE_Q   <= CTRL_WE_i;
        end
    end
    
endmodule