data/full_repos/permissive/493441306/Verilog Language/procedures/05_alwayscase2.v
1: b'%Error: Cannot find file containing module: Language/procedures,data/full_repos/permissive/493441306\n        ... Looked in:\n             data/full_repos/permissive/493441306/Verilog/Language/procedures,data/full_repos/permissive/493441306\n             data/full_repos/permissive/493441306/Verilog/Language/procedures,data/full_repos/permissive/493441306.v\n             data/full_repos/permissive/493441306/Verilog/Language/procedures,data/full_repos/permissive/493441306.sv\n             Language/procedures,data/full_repos/permissive/493441306\n             Language/procedures,data/full_repos/permissive/493441306.v\n             Language/procedures,data/full_repos/permissive/493441306.sv\n             obj_dir/Language/procedures,data/full_repos/permissive/493441306\n             obj_dir/Language/procedures,data/full_repos/permissive/493441306.v\n             obj_dir/Language/procedures,data/full_repos/permissive/493441306.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/493441306/Verilog\n%Error: Cannot find file containing module: Language/procedures/05_alwayscase2.v\n%Error: Exiting due to 3 error(s)\n'
module top_module (
    input [3:0] in,
    output reg [1:0] pos  );
    
    always@(*) begin
        casex(in)
            4'bxxx1 : pos = 2'b00;
            4'bxx10 : pos = 2'b01;
            4'bx100 : pos = 2'b10;
            4'b1000 : pos = 2'b11;
            default : pos = 0;
        endcase
    end
            
endmodule
module top_module (
    input [3:0] in,
    output reg [1:0] pos  );

    
    always@(*) begin
        casex(in)
            4'bxxx1 : pos = 2'b00;
            4'bxx10 : pos = 2'b01;
            4'bx100 : pos = 2'b10;
            4'b1000 : pos = 2'b11;
            default : pos = 0;
        endcase
    end
            
endmodule