data/full_repos/permissive/519309743/circuito-parte4.v
1: b"%Error: data/full_repos/permissive/519309743/circuito-parte4.v:1: syntax error, unexpected ';', expecting ')' or ','\nmodule controlador (clk,ch_vm,enb_3,Vint_z,qs,qes,qees,rstn,se,see,seee ;\n                                                                        ^\n%Error: data/full_repos/permissive/519309743/circuito-parte4.v:5: syntax error, unexpected output\n     output reg [3:0] se,see,seee;\n     ^~~~~~\n%Error: data/full_repos/permissive/519309743/circuito-parte4.v:12: syntax error, unexpected initial\n initial begin\n ^~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module combinado (clk, reset, q, qe, qee, qs, qes,  qees, a1, b1, c1, d1, e1, f1,g1, a2, b2, c2, d2, e2, f2, g2, a3, b3, c3, d3, e3, f3, g3,  Vint_z, ch_vm,enb_3, se, see, seee) ;
	input clk;
  	input Vint_z,ch_vm;
    	output reg reset;
  	output reg[3:0] q,qe,qee,qs,qes,qees,se,see,seee;
    	output reg enb_3;
	output a1, b1, c1, d1, e1, f1, g1;
	output a2, b2, c2, d2, e2, f2, g2;
	output a3, b3, c3, d3, e3, f3, g3;
  	initial begin
    		enb_3 = 1'b0;
    	end

   	 contador4b u1 (clk, reset, q, qe, qee, qs, qes, qees, a1, b1, c1, d1, e1, f1,g1, a2, b2, c2, d2, e2, f2, g2, a3, b3, c3, d3, e3, f3, g3);

    	controlador u2 (clk, ch_vm, enb_3, Vint_z, qs, qes, qees, reset, se, see, seee);
   	always @ * begin
      	if(q == 4'b0111)
      		enb_3 = 1'b1;
      	else
        		enb_3 = 1'b0;
    	end   
 endmodule
module combinado (clk, reset, q, qe, qee, qs, qes,  qees, a1, b1, c1, d1, e1, f1,g1, a2, b2, c2, d2, e2, f2, g2, a3, b3, c3, d3, e3, f3, g3,  Vint_z, ch_vm,enb_3, se, see, seee) ;

	input clk;
  	input Vint_z,ch_vm;
    	output reg reset;
  	output reg[3:0] q,qe,qee,qs,qes,qees,se,see,seee;
    	output reg enb_3;
	output a1, b1, c1, d1, e1, f1, g1;
	output a2, b2, c2, d2, e2, f2, g2;
	output a3, b3, c3, d3, e3, f3, g3;
  	initial begin
    		enb_3 = 1'b0;
    	end

   	 contador4b u1 (clk, reset, q, qe, qee, qs, qes, qees, a1, b1, c1, d1, e1, f1,g1, a2, b2, c2, d2, e2, f2, g2, a3, b3, c3, d3, e3, f3, g3);

    	controlador u2 (clk, ch_vm, enb_3, Vint_z, qs, qes, qees, reset, se, see, seee);
   	always @ * begin
      	if(q == 4'b0111)
      		enb_3 = 1'b1;
      	else
        		enb_3 = 1'b0;
    	end   
 endmodule