data/full_repos/permissive/493514142/verilog/rtl/FPU/FMADD_mantissa_generator.v
data/verilator_xmls/b18f01c1-bcce-4e8d-bc03-6bd085ea962b.xml
module FMADD_Mantissa_Generator (Mantissa_Generator_input_IEEE_A,Mantissa_Generator_input_IEEE_B,Mantissa_Generator_input_IEEE_C,Mantissa_Generator_input_Activation_signal,Mantissa_Generator_output_IEEE_A,Mantissa_Generator_output_IEEE_B,Mantissa_Generator_output_IEEE_C,Mantissa_Generator_output_A_Sub_norm,Mantissa_Generator_output_B_Sub_norm,Mantissa_Generator_output_A_pos_exp,Mantissa_Generator_output_B_pos_exp,Mantissa_Generator_output_A_neg_exp,Mantissa_Generator_output_B_neg_exp);


parameter std = 31;
parameter man = 22;
parameter exp = 7;



input [std:0]  Mantissa_Generator_input_IEEE_A,Mantissa_Generator_input_IEEE_B,Mantissa_Generator_input_IEEE_C;
input Mantissa_Generator_input_Activation_signal;


output [std+1:0] Mantissa_Generator_output_IEEE_A,Mantissa_Generator_output_IEEE_B,Mantissa_Generator_output_IEEE_C;
output Mantissa_Generator_output_A_Sub_norm,Mantissa_Generator_output_B_Sub_norm,Mantissa_Generator_output_A_pos_exp,Mantissa_Generator_output_B_pos_exp,Mantissa_Generator_output_A_neg_exp,Mantissa_Generator_output_B_neg_exp;


wire A_subnormal,B_subnormal,C_subnormal;


assign A_subnormal=  (&(~(Mantissa_Generator_input_IEEE_A[std-1:man+1]))) ;
assign Mantissa_Generator_output_A_Sub_norm = A_subnormal & Mantissa_Generator_input_Activation_signal;

assign B_subnormal=  (&(~(Mantissa_Generator_input_IEEE_B[std-1:man+1]))) ;
assign Mantissa_Generator_output_B_Sub_norm = B_subnormal & Mantissa_Generator_input_Activation_signal;

assign C_subnormal=  (&(~(Mantissa_Generator_input_IEEE_C[std-1:man+1]))) ;


assign Mantissa_Generator_output_A_neg_exp = ( (~(A_subnormal)) & ( ~(Mantissa_Generator_input_IEEE_A[std-1]) )  & (~ ( & (Mantissa_Generator_input_IEEE_A[std-2:man+1]) ) ));
assign Mantissa_Generator_output_A_pos_exp = ( (~(A_subnormal))  &  (~(Mantissa_Generator_output_A_neg_exp))) ;
assign Mantissa_Generator_output_B_neg_exp = ( (~(B_subnormal)) & ( ~(Mantissa_Generator_input_IEEE_B[std-1]) )  & (~ ( & (Mantissa_Generator_input_IEEE_B[std-2:man+1]) ) ));
assign Mantissa_Generator_output_B_pos_exp = ( (~(B_subnormal)) &  (~(Mantissa_Generator_output_B_neg_exp)) );



assign Mantissa_Generator_output_IEEE_A  =  ( Mantissa_Generator_input_Activation_signal ) ? ( (A_subnormal) ? { Mantissa_Generator_input_IEEE_A[std], {exp{1'b0}},1'b1, 1'b0, Mantissa_Generator_input_IEEE_A[man:0] } : {Mantissa_Generator_input_IEEE_A[std], Mantissa_Generator_input_IEEE_A[std-1:man+1], 1'b1, Mantissa_Generator_input_IEEE_A[man:0] }) : {{std{1'b0}},1'b0, 1'b0 } ;
assign Mantissa_Generator_output_IEEE_B  =  ( Mantissa_Generator_input_Activation_signal ) ? ( (B_subnormal) ? { Mantissa_Generator_input_IEEE_B[std], {exp{1'b0}},1'b1, 1'b0, Mantissa_Generator_input_IEEE_B[man:0] } : {Mantissa_Generator_input_IEEE_B[std], Mantissa_Generator_input_IEEE_B[std-1:man+1], 1'b1, Mantissa_Generator_input_IEEE_B[man:0] }) : {{std{1'b0}},1'b0, 1'b0 } ;
assign Mantissa_Generator_output_IEEE_C  =  ( Mantissa_Generator_input_Activation_signal ) ? ( (C_subnormal) ? { Mantissa_Generator_input_IEEE_C[std], {exp{1'b0}},1'b1, 1'b0, Mantissa_Generator_input_IEEE_C[man:0] } : {Mantissa_Generator_input_IEEE_C[std], Mantissa_Generator_input_IEEE_C[std-1:man+1], 1'b1, Mantissa_Generator_input_IEEE_C[man:0] }) : {{std{1'b0}},1'b0, 1'b0 } ;
endmodule
module FMADD_Mantissa_Generator (Mantissa_Generator_input_IEEE_A,Mantissa_Generator_input_IEEE_B,Mantissa_Generator_input_IEEE_C,Mantissa_Generator_input_Activation_signal,Mantissa_Generator_output_IEEE_A,Mantissa_Generator_output_IEEE_B,Mantissa_Generator_output_IEEE_C,Mantissa_Generator_output_A_Sub_norm,Mantissa_Generator_output_B_Sub_norm,Mantissa_Generator_output_A_pos_exp,Mantissa_Generator_output_B_pos_exp,Mantissa_Generator_output_A_neg_exp,Mantissa_Generator_output_B_neg_exp);



parameter std = 31;
parameter man = 22;
parameter exp = 7;



input [std:0]  Mantissa_Generator_input_IEEE_A,Mantissa_Generator_input_IEEE_B,Mantissa_Generator_input_IEEE_C;
input Mantissa_Generator_input_Activation_signal;


output [std+1:0] Mantissa_Generator_output_IEEE_A,Mantissa_Generator_output_IEEE_B,Mantissa_Generator_output_IEEE_C;
output Mantissa_Generator_output_A_Sub_norm,Mantissa_Generator_output_B_Sub_norm,Mantissa_Generator_output_A_pos_exp,Mantissa_Generator_output_B_pos_exp,Mantissa_Generator_output_A_neg_exp,Mantissa_Generator_output_B_neg_exp;


wire A_subnormal,B_subnormal,C_subnormal;


assign A_subnormal=  (&(~(Mantissa_Generator_input_IEEE_A[std-1:man+1]))) ;
assign Mantissa_Generator_output_A_Sub_norm = A_subnormal & Mantissa_Generator_input_Activation_signal;

assign B_subnormal=  (&(~(Mantissa_Generator_input_IEEE_B[std-1:man+1]))) ;
assign Mantissa_Generator_output_B_Sub_norm = B_subnormal & Mantissa_Generator_input_Activation_signal;

assign C_subnormal=  (&(~(Mantissa_Generator_input_IEEE_C[std-1:man+1]))) ;


assign Mantissa_Generator_output_A_neg_exp = ( (~(A_subnormal)) & ( ~(Mantissa_Generator_input_IEEE_A[std-1]) )  & (~ ( & (Mantissa_Generator_input_IEEE_A[std-2:man+1]) ) ));
assign Mantissa_Generator_output_A_pos_exp = ( (~(A_subnormal))  &  (~(Mantissa_Generator_output_A_neg_exp))) ;
assign Mantissa_Generator_output_B_neg_exp = ( (~(B_subnormal)) & ( ~(Mantissa_Generator_input_IEEE_B[std-1]) )  & (~ ( & (Mantissa_Generator_input_IEEE_B[std-2:man+1]) ) ));
assign Mantissa_Generator_output_B_pos_exp = ( (~(B_subnormal)) &  (~(Mantissa_Generator_output_B_neg_exp)) );



assign Mantissa_Generator_output_IEEE_A  =  ( Mantissa_Generator_input_Activation_signal ) ? ( (A_subnormal) ? { Mantissa_Generator_input_IEEE_A[std], {exp{1'b0}},1'b1, 1'b0, Mantissa_Generator_input_IEEE_A[man:0] } : {Mantissa_Generator_input_IEEE_A[std], Mantissa_Generator_input_IEEE_A[std-1:man+1], 1'b1, Mantissa_Generator_input_IEEE_A[man:0] }) : {{std{1'b0}},1'b0, 1'b0 } ;
assign Mantissa_Generator_output_IEEE_B  =  ( Mantissa_Generator_input_Activation_signal ) ? ( (B_subnormal) ? { Mantissa_Generator_input_IEEE_B[std], {exp{1'b0}},1'b1, 1'b0, Mantissa_Generator_input_IEEE_B[man:0] } : {Mantissa_Generator_input_IEEE_B[std], Mantissa_Generator_input_IEEE_B[std-1:man+1], 1'b1, Mantissa_Generator_input_IEEE_B[man:0] }) : {{std{1'b0}},1'b0, 1'b0 } ;
assign Mantissa_Generator_output_IEEE_C  =  ( Mantissa_Generator_input_Activation_signal ) ? ( (C_subnormal) ? { Mantissa_Generator_input_IEEE_C[std], {exp{1'b0}},1'b1, 1'b0, Mantissa_Generator_input_IEEE_C[man:0] } : {Mantissa_Generator_input_IEEE_C[std], Mantissa_Generator_input_IEEE_C[std-1:man+1], 1'b1, Mantissa_Generator_input_IEEE_C[man:0] }) : {{std{1'b0}},1'b0, 1'b0 } ;
endmodule