data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new/ALUDecoder.v
data/verilator_xmls/9520c49f-1d17-4c8d-bac9-7a9211948933.xml
module ALUDecoder(
    input [1:0] ALUOp,
    input [5:0] Funct,
    output reg [2:0] ALUSel
    );
    
    always@(ALUOp or Funct) begin
        if (ALUOp == 2'b00) begin
            ALUSel <= 3'b010;
        end
        else if (ALUOp == 2'b01) begin
            ALUSel <= 3'b110;
        end
        else if (ALUOp == 2'b10) begin
            if (Funct == 6'b100000) begin
                ALUSel <= 3'b010;
            end
            else if (Funct == 6'b100010) begin
                ALUSel <= 3'b110;
            end
            else if (Funct == 6'b000000) begin
                ALUSel <= 3'b011;
            end
            else if (Funct == 6'b000100) begin
                ALUSel <= 3'b100;
            end
            else if (Funct == 6'b000111) begin
                ALUSel <= 3'b101;
            end
        end
    end
endmodule
module ALUDecoder(
    input [1:0] ALUOp,
    input [5:0] Funct,
    output reg [2:0] ALUSel
    );

    
    always@(ALUOp or Funct) begin
        if (ALUOp == 2'b00) begin
            ALUSel <= 3'b010;
        end
        else if (ALUOp == 2'b01) begin
            ALUSel <= 3'b110;
        end
        else if (ALUOp == 2'b10) begin
            if (Funct == 6'b100000) begin
                ALUSel <= 3'b010;
            end
            else if (Funct == 6'b100010) begin
                ALUSel <= 3'b110;
            end
            else if (Funct == 6'b000000) begin
                ALUSel <= 3'b011;
            end
            else if (Funct == 6'b000100) begin
                ALUSel <= 3'b100;
            end
            else if (Funct == 6'b000111) begin
                ALUSel <= 3'b101;
            end
        end
    end
endmodule