data/full_repos/permissive/447223480/02_alu/cpu.v
data/verilator_xmls/7a4fc256-10e2-47ef-8a2b-3d13412b55fb.xml
module pmem(addr, data);
	input[31:0] addr;
	output[15:0] data;

	reg [15:0] mem[0:1023];

	assign data = mem[addr[10:1]];

endmodule
module pmem(addr, data);

	input[31:0] addr;
	output[15:0] data;

	reg [15:0] mem[0:1023];

	assign data = mem[addr[10:1]];

endmodule