data/full_repos/permissive/434840709/作业/组合电路5/cg.v
data/verilator_xmls/21a86181-a70c-40e2-a13c-aff5b9f5d885.xml
module top_module (

        input [3:0] a,

        input [3:0] b,

        input [3:0] c,

        input [3:0] d,

        input [3:0] e,

        output [3:0] q );

reg [3:0] t;

always @(*)
    case(c)
        0:t=b;
        1:t=e;
        2:t=a;
        3:t=d;
    default:t=15;
    endcase

assign q[3:0] = t[3:0];

endmodule
module top_module (

        input [3:0] a,

        input [3:0] b,

        input [3:0] c,

        input [3:0] d,

        input [3:0] e,

        output [3:0] q );


reg [3:0] t;

always @(*)
    case(c)
        0:t=b;
        1:t=e;
        2:t=a;
        3:t=d;
    default:t=15;
    endcase

assign q[3:0] = t[3:0];

endmodule