data/full_repos/permissive/472097485/Chu04/Pwm_02a/Counter.v
data/verilator_xmls/d6219f85-2b5c-438d-b100-1cb0ce8a2f59.xml
module Counter #( parameter N = 1 )( input clk, input reset, input en, output [N-1:0] count );

reg [N-1:0] counter;
wire [N-1:0] next;


always @( posedge clk, posedge reset )
begin
	if( reset )
		counter <= 0;
	else
		counter <= next;
end


assign next = en ? counter + 1 : counter;


assign count = counter;

endmodule
module Counter #( parameter N = 1 )( input clk, input reset, input en, output [N-1:0] count );


reg [N-1:0] counter;
wire [N-1:0] next;


always @( posedge clk, posedge reset )
begin
	if( reset )
		counter <= 0;
	else
		counter <= next;
end


assign next = en ? counter + 1 : counter;


assign count = counter;

endmodule