data/full_repos/permissive/420819839/Basics/DeclaringWires.v
data/verilator_xmls/e9f00b0a-e734-40e8-8410-f7692f33d178.xml
module top_module(
        input a,
        input b,
        input c,
        input d,
        output out,
        output out_n   );
    wire fio;
    assign fio = (a && b) || (c && d);
    assign out = fio;
    assign out_n = !fio;

endmodule
module top_module(
        input a,
        input b,
        input c,
        input d,
        output out,
        output out_n   );

    wire fio;
    assign fio = (a && b) || (c && d);
    assign out = fio;
    assign out_n = !fio;

endmodule