data/full_repos/permissive/481307378/source_files/ProgramCounter/pc_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/ProgramCounter/pc_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n            #10 CLK = ~CLK;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/481307378/source_files/ProgramCounter/pc_tb.v:40: syntax error, unexpected \'@\'\n        @(negedge CLK);  \n        ^\n%Error: data/full_repos/permissive/481307378/source_files/ProgramCounter/pc_tb.v:57: syntax error, unexpected \'@\'\n            @(posedge CLK);\n            ^\n%Error: data/full_repos/permissive/481307378/source_files/ProgramCounter/pc_tb.v:72: syntax error, unexpected \'@\'\n            @(posedge CLK);\n            ^\n%Error: data/full_repos/permissive/481307378/source_files/ProgramCounter/pc_tb.v:85: syntax error, unexpected \'@\'\n        @(posedge CLK);\n        ^\n%Error: data/full_repos/permissive/481307378/source_files/ProgramCounter/pc_tb.v:96: syntax error, unexpected \'@\'\n        @(posedge CLK);\n        ^\n%Error: Exiting due to 5 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pc_tb();


    reg CLK;
    reg RES;
    reg ENABLE;
    reg MODE;
    reg [31 : 0] D;
    

    wire [31 : 0] PC_OUT;
    

    reg [31:0]L;
    
    integer i;
    
    pc dut(.CLK(CLK), .RES(RES), .ENABLE(ENABLE), .MODE(MODE), .D(D),   .PC_OUT(PC_OUT));
    

        initial begin 
            CLK = 1'b0;
        end
    




        always begin
            #10 CLK = ~CLK;
        end    
    

        initial begin
        

        RES = 1;
        @(negedge CLK);
        RES = 0;
L=32'h1A00_0000;
        if(PC_OUT != L)
        begin
            $display("Test pattern 1 failed: PC_OUT=%h L=%h", PC_OUT, L);
            $finish;
        end   
        $display("Reset test passed!");
        
        

        RES=0; ENABLE=1'b1; MODE=1'b0; L=32'h1A00_0000;
        
        for(i = 1; i <= 100; i = i + 1)
        begin
            L = L + 32'd4;
            @(posedge CLK);
            @(negedge CLK);
            if(PC_OUT != L)
            begin
                $display("Test pattern 2 failed at iteration %d: PC_OUT=%h L=%h", i, PC_OUT, L);
                $finish;
            end            
        end
        $display("ENABLE = 1, Program counter incremented by 4, test passed!");
        
        

        RES=0; ENABLE=1'b0; MODE=1'b0; L=PC_OUT;
        for(i = 1; i <= 10; i = i + 1)
        begin
            @(posedge CLK);
            @(negedge CLK);
            if(PC_OUT != L)
            begin
                $display("Test pattern 3 failed at iteration %d: PC_OUT=%h L=%h", i, PC_OUT, L);
                $finish;
            end
        end
        $display("ENABLE = 0, Program counter not incremented, test passed!");
        
        

        RES=0; ENABLE=1'b1; MODE=1'b1; D=32'hF1E2_A960; L=D;
        @(posedge CLK);
        @(negedge CLK);
        if(PC_OUT != L)
        begin
            $display("Test pattern 4 failed: PC_OUT=%h L=%h", PC_OUT, L);
            $finish;
        end
        $display("ENABLE = 1, New Jump address loaded into Program counter, test passed!");
        

        RES=0; ENABLE=1'b0; MODE=1'b1; D=32'h0000_0000; L=32'hF1E2_A960;
        @(posedge CLK);
        @(negedge CLK);
        if(PC_OUT != L)
        begin
            $display("Test pattern 5 failed: PC_OUT=%h L=%h", PC_OUT, L);
            $finish;
        end
        $display("ENABLE = 0, New Jump address not loaded into Program counter, test passed!");
        
        $display("All tests passed!");
        $finish;
   end
endmodule
module pc_tb();



    reg CLK;
    reg RES;
    reg ENABLE;
    reg MODE;
    reg [31 : 0] D;
    

    wire [31 : 0] PC_OUT;
    

    reg [31:0]L;
    
    integer i;
    
    pc dut(.CLK(CLK), .RES(RES), .ENABLE(ENABLE), .MODE(MODE), .D(D),   .PC_OUT(PC_OUT));
    

        initial begin 
            CLK = 1'b0;
        end
    




        always begin
            #10 CLK = ~CLK;
        end    
    

        initial begin
        

        RES = 1;
        @(negedge CLK);
        RES = 0;
L=32'h1A00_0000;
        if(PC_OUT != L)
        begin
            $display("Test pattern 1 failed: PC_OUT=%h L=%h", PC_OUT, L);
            $finish;
        end   
        $display("Reset test passed!");
        
        

        RES=0; ENABLE=1'b1; MODE=1'b0; L=32'h1A00_0000;
        
        for(i = 1; i <= 100; i = i + 1)
        begin
            L = L + 32'd4;
            @(posedge CLK);
            @(negedge CLK);
            if(PC_OUT != L)
            begin
                $display("Test pattern 2 failed at iteration %d: PC_OUT=%h L=%h", i, PC_OUT, L);
                $finish;
            end            
        end
        $display("ENABLE = 1, Program counter incremented by 4, test passed!");
        
        

        RES=0; ENABLE=1'b0; MODE=1'b0; L=PC_OUT;
        for(i = 1; i <= 10; i = i + 1)
        begin
            @(posedge CLK);
            @(negedge CLK);
            if(PC_OUT != L)
            begin
                $display("Test pattern 3 failed at iteration %d: PC_OUT=%h L=%h", i, PC_OUT, L);
                $finish;
            end
        end
        $display("ENABLE = 0, Program counter not incremented, test passed!");
        
        

        RES=0; ENABLE=1'b1; MODE=1'b1; D=32'hF1E2_A960; L=D;
        @(posedge CLK);
        @(negedge CLK);
        if(PC_OUT != L)
        begin
            $display("Test pattern 4 failed: PC_OUT=%h L=%h", PC_OUT, L);
            $finish;
        end
        $display("ENABLE = 1, New Jump address loaded into Program counter, test passed!");
        

        RES=0; ENABLE=1'b0; MODE=1'b1; D=32'h0000_0000; L=32'hF1E2_A960;
        @(posedge CLK);
        @(negedge CLK);
        if(PC_OUT != L)
        begin
            $display("Test pattern 5 failed: PC_OUT=%h L=%h", PC_OUT, L);
            $finish;
        end
        $display("ENABLE = 0, New Jump address not loaded into Program counter, test passed!");
        
        $display("All tests passed!");
        $finish;
   end
endmodule