data/full_repos/permissive/46989236/alu/alu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/46989236/alu/alu.v:13: Operator ADD expects 8 bits on the LHS, but LHS\'s VARREF \'b\' generates 4 bits.\n                                                                : ... In instance alu\n 3\'b000:{ah,al}<=b+c;\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/46989236/alu/alu.v:13: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'c\' generates 4 bits.\n                                                                : ... In instance alu\n 3\'b000:{ah,al}<=b+c;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/46989236/alu/alu.v:14: Operator SUB expects 8 bits on the LHS, but LHS\'s VARREF \'b\' generates 4 bits.\n                                                                : ... In instance alu\n 3\'b001:{ah,al}<=b-c;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/46989236/alu/alu.v:14: Operator SUB expects 8 bits on the RHS, but RHS\'s VARREF \'c\' generates 4 bits.\n                                                                : ... In instance alu\n 3\'b001:{ah,al}<=b-c;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/46989236/alu/alu.v:16: Operator SHIFTL expects 8 bits on the LHS, but LHS\'s VARREF \'b\' generates 4 bits.\n                                                                : ... In instance alu\n 3\'b011:{ah,al}<=b<<c;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/46989236/alu/alu.v:17: Operator AND expects 8 bits on the LHS, but LHS\'s VARREF \'b\' generates 4 bits.\n                                                                : ... In instance alu\n 3\'b100:{ah,al}<=b&c;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/46989236/alu/alu.v:17: Operator AND expects 8 bits on the RHS, but RHS\'s VARREF \'c\' generates 4 bits.\n                                                                : ... In instance alu\n 3\'b100:{ah,al}<=b&c;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/46989236/alu/alu.v:18: Operator OR expects 8 bits on the LHS, but LHS\'s VARREF \'b\' generates 4 bits.\n                                                                : ... In instance alu\n 3\'b101:{ah,al}<=b|c;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/46989236/alu/alu.v:18: Operator OR expects 8 bits on the RHS, but RHS\'s VARREF \'c\' generates 4 bits.\n                                                                : ... In instance alu\n 3\'b101:{ah,al}<=b|c;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/46989236/alu/alu.v:19: Operator XOR expects 8 bits on the LHS, but LHS\'s VARREF \'b\' generates 4 bits.\n                                                                : ... In instance alu\n 3\'b110:{ah,al}<=b^c;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/46989236/alu/alu.v:19: Operator XOR expects 8 bits on the RHS, but RHS\'s VARREF \'c\' generates 4 bits.\n                                                                : ... In instance alu\n 3\'b110:{ah,al}<=b^c;\n                  ^\n%Error: Exiting due to 11 warning(s)\n'
module alu(clock,opcode,b,c,al,ah,reset);
input wire clock,reset;
input wire [2:0]opcode;
input wire [3:0]b,c;
output reg [3:0]al,ah;
always @ (posedge clock or posedge reset)
if (reset)
	begin
	{ah,al}<=8'b00000000;
	end
else
	case(opcode)
	3'b000:{ah,al}<=b+c;
	3'b001:{ah,al}<=b-c;
	3'b010:{ah,al}<=b*c;
	3'b011:{ah,al}<=b<<c;
	3'b100:{ah,al}<=b&c;
	3'b101:{ah,al}<=b|c;
	3'b110:{ah,al}<=b^c;
	default:{ah,al}<=8'd0;
	endcase
endmodule
module alu(clock,opcode,b,c,al,ah,reset);

input wire clock,reset;
input wire [2:0]opcode;
input wire [3:0]b,c;
output reg [3:0]al,ah;
always @ (posedge clock or posedge reset)
if (reset)
	begin
	{ah,al}<=8'b00000000;
	end
else
	case(opcode)
	3'b000:{ah,al}<=b+c;
	3'b001:{ah,al}<=b-c;
	3'b010:{ah,al}<=b*c;
	3'b011:{ah,al}<=b<<c;
	3'b100:{ah,al}<=b&c;
	3'b101:{ah,al}<=b|c;
	3'b110:{ah,al}<=b^c;
	default:{ah,al}<=8'd0;
	endcase
endmodule