data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_tx_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_tx_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n   initial #1000 reset = 0;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_tx_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n   always #50 clk = ~clk;\n          ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_tx_tb.v:34: Unsupported or unknown PLI call: $dumpfile\n   initial $dumpfile("vita_tx_tb.vcd");\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_tx_tb.v:35: Unsupported or unknown PLI call: $dumpvars\n   initial $dumpvars(0,vita_tx_tb);\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_tx_tb.v:93: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_tx_tb.v:97: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_tx_tb.v:104: syntax error, unexpected \'@\'\n @(negedge reset);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_tx_tb.v:111: Unsupported: Ignoring delay on this delayed statement.\n #10000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_tx_tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n #300000 $finish;\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_tx_tb.v:138: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_tx_tb.v:141: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_tx_tb.v:147: syntax error, unexpected \'@\'\n       @(posedge clk);\n       ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_tx_tb.v:149: syntax error, unexpected \'@\'\n       @(posedge clk);\n       ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_tx_tb.v:151: syntax error, unexpected \'@\'\n       @(posedge clk);\n       ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_tx_tb.v:156: syntax error, unexpected \'@\'\n       @(posedge clk);\n       ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_tx_tb.v:161: syntax error, unexpected \'@\'\n       @(posedge clk);\n       ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_tx_tb.v:166: syntax error, unexpected \'@\'\n       @(posedge clk);\n       ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_tx_tb.v:168: syntax error, unexpected \'@\'\n       @(posedge clk);\n       ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/vrt/vita_tx_tb.v:171: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: Exiting due to 15 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tx_dsp_model
  (input clk, input reset,
   input run,
   input [7:0] interp,
   output strobe,
   input [31:0] sample);

   cic_strober strober(.clock(clk), .reset(reset), .enable(run), .rate(interp), .strobe_fast(1), .strobe_slow(strobe));

   always @(posedge clk)
     if(strobe)
       $display("Time %d, Sent Sample %x",$time,sample);
   
   
endmodule
module tx_dsp_model
  (input clk, input reset,
   input run,
   input [7:0] interp,
   output strobe,
   input [31:0] sample);


   cic_strober strober(.clock(clk), .reset(reset), .enable(run), .rate(interp), .strobe_fast(1), .strobe_slow(strobe));

   always @(posedge clk)
     if(strobe)
       $display("Time %d, Sent Sample %x",$time,sample);
   
   
endmodule