data/full_repos/permissive/425308566/Testing_code_work.v
1: b'%Error: data/full_repos/permissive/425308566/Testing_code_work.v:1: syntax error, unexpected --\n-----------------------------------Part00:start of counter--------------------------------------------------------------------\n^~\n%Error: data/full_repos/permissive/425308566/Testing_code_work.v:22: syntax error, unexpected --\n-----------------------------------Part00:end of counter--------------------------------------------------------------------\n^~\n%Warning-STMTDLY: data/full_repos/permissive/425308566/Testing_code_work.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #10 sys_clk=k;   \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/425308566/Testing_code_work.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #5 $finish;\n        ^\n%Error: Unsupported: module decls within module decls\n%Error: data/full_repos/permissive/425308566/Testing_code_work.v:58: syntax error, unexpected --\n-----------------------------------Part01:End of Counter--------------------------------------------------------------------\n^~\n%Warning-STMTDLY: data/full_repos/permissive/425308566/Testing_code_work.v:93: Unsupported: Ignoring delay on this delayed statement.\n        #10 CLK=k;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/425308566/Testing_code_work.v:95: Unsupported: Ignoring delay on this delayed statement.\n        #5 $finish;\n        ^\n%Error: data/full_repos/permissive/425308566/Testing_code_work.v:99: syntax error, unexpected --\n-----------------------------------Part02:End of Counter--------------------------------------------------------------------\n^~\n%Error: Exiting due to 5 error(s), 4 warning(s)\n'
module top(
    input wire [7:0] MISO,
    output reg [7:0] MOSI,
    output reg CS,
    input wire [7:0] CLK
    );
    reg [7:0] counter;
    initial begin
    
    MOSI<=8'b0;
    counter<=8'b0;
    end
    always@(posedge CLK[0])
    begin  
       CS=CLK[0];
       MOSI=MOSI+1;
    end 
endmodule
module top(
    input wire [7:0] MISO,
    output reg [7:0] MOSI,
    output reg CS,
    input wire [7:0] CLK
    );

    reg [7:0] counter;
    initial begin
    
    MOSI<=8'b0;
    counter<=8'b0;
    end
    always@(posedge CLK[0])
    begin  
       CS=CLK[0];
       MOSI=MOSI+1;
    end 
endmodule