data/full_repos/permissive/434840709/USTB_digital_logic_homework/task2/top.v
1: b"%Error: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task2/top.v:36: Cannot find file containing module: 'clkDiv'\n clkDiv U1(clk100mhz,clk190hz,clk3hz);\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/434840709/USTB_digital_logic_homework/task2,data/full_repos/permissive/434840709/clkDiv\n             data/full_repos/permissive/434840709/USTB_digital_logic_homework/task2,data/full_repos/permissive/434840709/clkDiv.v\n             data/full_repos/permissive/434840709/USTB_digital_logic_homework/task2,data/full_repos/permissive/434840709/clkDiv.sv\n             clkDiv\n             clkDiv.v\n             clkDiv.sv\n             obj_dir/clkDiv\n             obj_dir/clkDiv.v\n             obj_dir/clkDiv.sv\n%Error: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task2/top.v:37: Cannot find file containing module: 'key_xd'\n key_xd Ukey_wei_xd(\n ^~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task2/top.v:43: Cannot find file containing module: 'key_xd'\n key_xd Ukey_enter_xd(\n ^~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task2/top.v:49: Cannot find file containing module: 'key_xd'\n key_xd Ukey_input_xd(\n ^~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task2/top.v:55: Cannot find file containing module: 'key_xd'\n key_xd Ukey_shuzi_xd(\n ^~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task2/top.v:61: Cannot find file containing module: 'key_xd'\n key_xd Ukey_disp_xd(\n ^~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task2/top.v:67: Cannot find file containing module: 'key_ctrl'\n key_ctrl Ukey_ctrl(\n ^~~~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task2/top.v:80: Cannot find file containing module: 'GPU'\n    GPU UGPU(\n    ^~~\n%Error: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task2/top.v:87: Cannot find file containing module: 'segMsg'\n segMsg UsegMsg_f(\n ^~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task2/top.v:93: Cannot find file containing module: 'segMsg'\n segMsg UsegMsg_b(\n ^~~~~~\n%Error: Exiting due to 10 error(s)\n"
module top(
input 				clk100mhz,
input 				clr,
input				key_wei,
input				key_shuzi,
input				key_enter,
input				key_input,
input				key_disp,
output 		[3:0] 	pos_f,
output 		[7:0] 	seg_f,
output 		[3:0] 	pos_b,
output 		[7:0] 	seg_b
);

    wire clk190hz,clk3hz;
    wire 	[15:0]	dataBus_f;
	wire	[3:0]	pos_f_tmp;
	wire	[15:0]	dataBus_b;
	wire	[3:0]	pos_b_tmp;
	wire	[31:0]	disp_data;
	wire	[31:0]	disp_data_b;
	wire	[3:0]	shuzi;
	wire	[3:0]	weishu;
	wire			disp_data_en;
	assign	dataBus_f={weishu,4'h0,shuzi,4'h0};

	assign	pos_f={pos_f_tmp[3],1'b0,pos_f_tmp[1],1'b0};
	assign	pos_b={pos_b_tmp[0],pos_b_tmp[1],pos_b_tmp[2],pos_b_tmp[3]};

	clkDiv U1(clk100mhz,clk190hz,clk3hz);
	key_xd Ukey_wei_xd(
	.clk			(clk100mhz),
	.rst_n			(clr),
	.key_in			(key_wei),
	.key_out        (key_wei_out)
		);
	key_xd Ukey_enter_xd(
	.clk			(clk100mhz),
	.rst_n			(clr),
	.key_in			(key_enter),
	.key_out        (key_enter_out)
		);
	key_xd Ukey_input_xd(
	.clk			(clk100mhz),
	.rst_n			(clr),
	.key_in			(key_input),
	.key_out        (key_input_out)
		);
	key_xd Ukey_shuzi_xd(
	.clk			(clk100mhz),
	.rst_n			(clr),
	.key_in			(key_shuzi),
	.key_out        (key_shuzi_out)
		);
	key_xd Ukey_disp_xd(
	.clk			(clk100mhz),
	.rst_n			(clr),
	.key_in			(key_disp),
	.key_out        (key_disp_out)
		);
	key_ctrl Ukey_ctrl(
	.clk			(clk100mhz),
	.rst_n			(clr),
	.key_wei		(key_wei_out	),
	.key_shuzi		(key_shuzi_out	),
	.key_enter		(key_enter_out	),
	.key_input		(key_input_out	),
	.key_disp		(key_disp_out	),
	.weishu			(weishu),
	.shuzi			(shuzi),
	.disp_data		(disp_data_b),
	.disp_data_en	(disp_data_en)
);
    GPU UGPU(
	.clk3hz			(clk3hz),
	.clr			(clr),
	.disp_data_en	(disp_data_en),
	.datain			(disp_data_b),
	.dataBus    	(dataBus_b)
    );
	segMsg UsegMsg_f(
	.clk190hz		(clk190hz),
	.dataBus		(dataBus_f),
	.pos			(pos_f_tmp),
	.seg            (seg_f)
    );
	segMsg UsegMsg_b(
	.clk190hz		(clk190hz),
	.dataBus		(dataBus_b),
	.pos			(pos_b_tmp),
	.seg            (seg_b)
    );
endmodule
module top(
input 				clk100mhz,
input 				clr,
input				key_wei,
input				key_shuzi,
input				key_enter,
input				key_input,
input				key_disp,
output 		[3:0] 	pos_f,
output 		[7:0] 	seg_f,
output 		[3:0] 	pos_b,
output 		[7:0] 	seg_b
);


    wire clk190hz,clk3hz;
    wire 	[15:0]	dataBus_f;
	wire	[3:0]	pos_f_tmp;
	wire	[15:0]	dataBus_b;
	wire	[3:0]	pos_b_tmp;
	wire	[31:0]	disp_data;
	wire	[31:0]	disp_data_b;
	wire	[3:0]	shuzi;
	wire	[3:0]	weishu;
	wire			disp_data_en;
	assign	dataBus_f={weishu,4'h0,shuzi,4'h0};

	assign	pos_f={pos_f_tmp[3],1'b0,pos_f_tmp[1],1'b0};
	assign	pos_b={pos_b_tmp[0],pos_b_tmp[1],pos_b_tmp[2],pos_b_tmp[3]};

	clkDiv U1(clk100mhz,clk190hz,clk3hz);
	key_xd Ukey_wei_xd(
	.clk			(clk100mhz),
	.rst_n			(clr),
	.key_in			(key_wei),
	.key_out        (key_wei_out)
		);
	key_xd Ukey_enter_xd(
	.clk			(clk100mhz),
	.rst_n			(clr),
	.key_in			(key_enter),
	.key_out        (key_enter_out)
		);
	key_xd Ukey_input_xd(
	.clk			(clk100mhz),
	.rst_n			(clr),
	.key_in			(key_input),
	.key_out        (key_input_out)
		);
	key_xd Ukey_shuzi_xd(
	.clk			(clk100mhz),
	.rst_n			(clr),
	.key_in			(key_shuzi),
	.key_out        (key_shuzi_out)
		);
	key_xd Ukey_disp_xd(
	.clk			(clk100mhz),
	.rst_n			(clr),
	.key_in			(key_disp),
	.key_out        (key_disp_out)
		);
	key_ctrl Ukey_ctrl(
	.clk			(clk100mhz),
	.rst_n			(clr),
	.key_wei		(key_wei_out	),
	.key_shuzi		(key_shuzi_out	),
	.key_enter		(key_enter_out	),
	.key_input		(key_input_out	),
	.key_disp		(key_disp_out	),
	.weishu			(weishu),
	.shuzi			(shuzi),
	.disp_data		(disp_data_b),
	.disp_data_en	(disp_data_en)
);
    GPU UGPU(
	.clk3hz			(clk3hz),
	.clr			(clr),
	.disp_data_en	(disp_data_en),
	.datain			(disp_data_b),
	.dataBus    	(dataBus_b)
    );
	segMsg UsegMsg_f(
	.clk190hz		(clk190hz),
	.dataBus		(dataBus_f),
	.pos			(pos_f_tmp),
	.seg            (seg_f)
    );
	segMsg UsegMsg_b(
	.clk190hz		(clk190hz),
	.dataBus		(dataBus_b),
	.pos			(pos_b_tmp),
	.seg            (seg_b)
    );
endmodule