data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_test.v
1: b'%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_test.v:1: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog,data/full_repos/permissive/411838135/timescale.v\n             data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog,data/full_repos/permissive/411838135/timescale.v.v\n             data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog,data/full_repos/permissive/411838135/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_test.v:4: Cannot find include file: UART_defines.v\n`include "UART_defines.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_test.v:8: Define or directive not defined: \'`ADDR_WIDTH\'\nreg [`ADDR_WIDTH-1:0] wb_addr_ir;\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_test.v:49: Define or directive not defined: \'`ADDR_WIDTH\'\nreg [`ADDR_WIDTH-1:0] wb1_addr_ir;\n     ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_test.v:118: Unsupported: Ignoring delay on this delayed statement.\n #20000 $finish;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_test.v:126: syntax error, unexpected \'@\'\n @(negedge clk)\n ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_test.v:133: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_test.v:132: Unsupported: wait statements\n wait (wb_ack_o==1)\n ^~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_test.v:145: syntax error, unexpected \'@\'\n @(negedge clk)\n ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_test.v:152: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_test.v:151: Unsupported: wait statements\n wait (wb1_ack_o==1)\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_test.v:162: Unsupported: Ignoring delay on this delayed statement.\n #1 wb_rst_ir = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_test.v:163: Unsupported: Ignoring delay on this delayed statement.\n #10 wb_rst_ir = 0;\n ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_test.v:170: Define or directive not defined: \'`REG_LC\'\n cycle(1, `REG_LC, 8\'b10011011);\n          ^~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_test.v:172: Define or directive not defined: \'`REG_DL1\'\n cycle(1, `REG_DL1, 8\'d2);\n          ^~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_test.v:173: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_test.v:176: Define or directive not defined: \'`REG_LC\'\n cycle(1, `REG_LC, 8\'b00011011);\n          ^~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_test.v:178: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_test.v:181: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_test.v:182: Unsupported: wait statements\n wait (uart_snd.regs.state==0 && uart_snd.regs.tf_count==0);\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_test.v:183: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_test.v:191: Unsupported: Ignoring delay on this delayed statement.\n #11;\n ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_test.v:198: Define or directive not defined: \'`REG_LC\'\n cycle1(1, `REG_LC, 8\'b10011011);\n           ^~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_test.v:200: Define or directive not defined: \'`REG_DL1\'\n cycle1(1, `REG_DL1, 8\'d2);\n           ^~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_test.v:201: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_test.v:204: Define or directive not defined: \'`REG_LC\'\n cycle1(1, `REG_LC, 8\'b00011011);\n           ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_test.v:214: Unsupported: Ignoring delay on this delayed statement.\n #5 clkr = ~clk;\n ^\n%Error: Exiting due to 20 error(s), 7 warning(s)\n'
module UART_test ();

`include "UART_defines.v"

reg				clkr;
reg				wb_rst_ir;
reg	[`ADDR_WIDTH-1:0]	wb_addr_ir;
reg	[7:0]			wb_dat_ir;
wire	[7:0]			wb_dat_o;
reg				wb_we_ir;
reg				wb_stb_ir;
reg				wb_cyc_ir;
wire				wb_ack_o;
wire				int_o;
wire				stx_o;
reg				srx_ir;
wire				rts_o;
reg				cts_ir;
wire				dtr_o;
reg				dsr_ir;
reg				ri_ir;
reg				dcd_ir;
wire	[2:0]			wb_addr_i;
wire	[7:0]			wb_dat_i;




UART_top	uart_snd(
	clk, 
	

	wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o,	
	int_o,



	stx_o, srx_i,


	rts_o, cts_i, dtr_o, dsr_i, ri_i, dcd_i

	);




reg	[`ADDR_WIDTH-1:0]	wb1_addr_ir;
reg	[7:0]			wb1_dat_ir;
wire	[7:0]			wb1_dat_o;
reg				wb1_we_ir;
reg				wb1_stb_ir;
reg				wb1_cyc_ir;
wire				wb1_ack_o;
wire				int1_o;
wire				stx1_o;
reg				srx1_ir;
wire				rts1_o;
reg				cts1_ir;
wire				dtr1_o;
reg				dsr1_ir;
reg				ri1_ir;
reg				dcd1_ir;
wire	[2:0]			wb1_addr_i;
wire	[7:0]			wb1_dat_i;


UART_top	uart_rcv(
	clk, 
	

	wb_rst_i, wb1_addr_i, wb1_dat_i, wb1_dat_o, wb1_we_i, wb1_stb_i, wb1_cyc_i, wb1_ack_o,	
	int1_o,



	stx1_o, srx1_i,


	rts1_o, cts1_i, dtr1_o, dsr1_i, ri1_i, dcd1_i

	);

assign clk = clkr;
assign wb_dat_i = wb_dat_ir;
assign wb_we_i = wb_we_ir;
assign wb_rst_i = wb_rst_ir;
assign wb_addr_i = wb_addr_ir;
assign wb_stb_i = wb_stb_ir;
assign wb_cyc_i = wb_cyc_ir;
assign srx_i = srx_ir;
assign cts_i = cts_ir;
assign dsr_i = dsr_ir;
assign ri_i = ri_ir;
assign dcd_i = dcd_ir;

assign wb1_dat_i = wb1_dat_ir;
assign wb1_we_i = wb1_we_ir;
assign wb1_addr_i = wb1_addr_ir;
assign wb1_stb_i = wb1_stb_ir;
assign wb1_cyc_i = wb1_cyc_ir;
assign srx1_i = srx1_ir;
assign cts1_i = cts1_ir;
assign dsr1_i = dsr1_ir;
assign ri1_i = ri1_ir;
assign dcd1_i = dcd1_ir;


always @(stx_o)
begin
	srx1_ir = stx_o;	
end

initial
begin
	clkr = 0;
	#20000 $finish;
end

task cycle;
input		we;
input	[2:0]	addr;
input	[7:0]	dat;		
begin
	@(negedge clk)
	wb_addr_ir <= #1 addr;
	wb_we_ir <= #1 we;
	wb_dat_ir <= #1 dat;
	wb_stb_ir <= #1 1;
	wb_cyc_ir <= #1 1;
	wait (wb_ack_o==1)
	@(posedge clk);
	wb_we_ir <= #1 0;
	wb_stb_ir<= #1 0;
	wb_cyc_ir<= #1 0;
end
endtask

task cycle1;
input		we;
input	[2:0]	addr;
input	[7:0]	dat;		
begin
	@(negedge clk)
	wb1_addr_ir <= #1 addr;
	wb1_we_ir <= #1 we;
	wb1_dat_ir <= #1 dat;
	wb1_stb_ir <= #1 1;
	wb1_cyc_ir <= #1 1;
	wait (wb1_ack_o==1)
	@(posedge clk);
	wb1_we_ir <= #1 0;
	wb1_stb_ir<= #1 0;
	wb1_cyc_ir<= #1 0;
end
endtask


initial
begin
	#1 wb_rst_ir = 1;
	#10 wb_rst_ir = 0;
	wb_stb_ir = 0;
	wb_cyc_ir = 0;
	wb_we_ir = 0;
	


	cycle(1, `REG_LC, 8'b10011011);

	cycle(1, `REG_DL1, 8'd2);
	@(posedge clk);
	@(posedge clk);

	cycle(1, `REG_LC, 8'b00011011);
	cycle(1, 0, 8'b01101011);
	@(posedge clk);
	@(posedge clk);
	cycle(1, 0, 8'b01000101);
	#100;
	wait (uart_snd.regs.state==0 && uart_snd.regs.tf_count==0);
	#100;
	$finish;
	
end


initial
begin
	#11;
	wb1_stb_ir = 0;
	wb1_cyc_ir = 0;
	wb1_we_ir = 0;
	


	cycle1(1, `REG_LC, 8'b10011011);

	cycle1(1, `REG_DL1, 8'd2);
	@(posedge clk);
	@(posedge clk);

	cycle1(1, `REG_LC, 8'b00011011);
end






always
begin
	#5 clkr = ~clk;
end

endmodule
module UART_test ();


`include "UART_defines.v"

reg				clkr;
reg				wb_rst_ir;
reg	[`ADDR_WIDTH-1:0]	wb_addr_ir;
reg	[7:0]			wb_dat_ir;
wire	[7:0]			wb_dat_o;
reg				wb_we_ir;
reg				wb_stb_ir;
reg				wb_cyc_ir;
wire				wb_ack_o;
wire				int_o;
wire				stx_o;
reg				srx_ir;
wire				rts_o;
reg				cts_ir;
wire				dtr_o;
reg				dsr_ir;
reg				ri_ir;
reg				dcd_ir;
wire	[2:0]			wb_addr_i;
wire	[7:0]			wb_dat_i;




UART_top	uart_snd(
	clk, 
	

	wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o,	
	int_o,



	stx_o, srx_i,


	rts_o, cts_i, dtr_o, dsr_i, ri_i, dcd_i

	);




reg	[`ADDR_WIDTH-1:0]	wb1_addr_ir;
reg	[7:0]			wb1_dat_ir;
wire	[7:0]			wb1_dat_o;
reg				wb1_we_ir;
reg				wb1_stb_ir;
reg				wb1_cyc_ir;
wire				wb1_ack_o;
wire				int1_o;
wire				stx1_o;
reg				srx1_ir;
wire				rts1_o;
reg				cts1_ir;
wire				dtr1_o;
reg				dsr1_ir;
reg				ri1_ir;
reg				dcd1_ir;
wire	[2:0]			wb1_addr_i;
wire	[7:0]			wb1_dat_i;


UART_top	uart_rcv(
	clk, 
	

	wb_rst_i, wb1_addr_i, wb1_dat_i, wb1_dat_o, wb1_we_i, wb1_stb_i, wb1_cyc_i, wb1_ack_o,	
	int1_o,



	stx1_o, srx1_i,


	rts1_o, cts1_i, dtr1_o, dsr1_i, ri1_i, dcd1_i

	);

assign clk = clkr;
assign wb_dat_i = wb_dat_ir;
assign wb_we_i = wb_we_ir;
assign wb_rst_i = wb_rst_ir;
assign wb_addr_i = wb_addr_ir;
assign wb_stb_i = wb_stb_ir;
assign wb_cyc_i = wb_cyc_ir;
assign srx_i = srx_ir;
assign cts_i = cts_ir;
assign dsr_i = dsr_ir;
assign ri_i = ri_ir;
assign dcd_i = dcd_ir;

assign wb1_dat_i = wb1_dat_ir;
assign wb1_we_i = wb1_we_ir;
assign wb1_addr_i = wb1_addr_ir;
assign wb1_stb_i = wb1_stb_ir;
assign wb1_cyc_i = wb1_cyc_ir;
assign srx1_i = srx1_ir;
assign cts1_i = cts1_ir;
assign dsr1_i = dsr1_ir;
assign ri1_i = ri1_ir;
assign dcd1_i = dcd1_ir;


always @(stx_o)
begin
	srx1_ir = stx_o;	
end

initial
begin
	clkr = 0;
	#20000 $finish;
end

task cycle;
input		we;
input	[2:0]	addr;
input	[7:0]	dat;		
begin
	@(negedge clk)
	wb_addr_ir <= #1 addr;
	wb_we_ir <= #1 we;
	wb_dat_ir <= #1 dat;
	wb_stb_ir <= #1 1;
	wb_cyc_ir <= #1 1;
	wait (wb_ack_o==1)
	@(posedge clk);
	wb_we_ir <= #1 0;
	wb_stb_ir<= #1 0;
	wb_cyc_ir<= #1 0;
end
endtask

task cycle1;
input		we;
input	[2:0]	addr;
input	[7:0]	dat;		
begin
	@(negedge clk)
	wb1_addr_ir <= #1 addr;
	wb1_we_ir <= #1 we;
	wb1_dat_ir <= #1 dat;
	wb1_stb_ir <= #1 1;
	wb1_cyc_ir <= #1 1;
	wait (wb1_ack_o==1)
	@(posedge clk);
	wb1_we_ir <= #1 0;
	wb1_stb_ir<= #1 0;
	wb1_cyc_ir<= #1 0;
end
endtask


initial
begin
	#1 wb_rst_ir = 1;
	#10 wb_rst_ir = 0;
	wb_stb_ir = 0;
	wb_cyc_ir = 0;
	wb_we_ir = 0;
	


	cycle(1, `REG_LC, 8'b10011011);

	cycle(1, `REG_DL1, 8'd2);
	@(posedge clk);
	@(posedge clk);

	cycle(1, `REG_LC, 8'b00011011);
	cycle(1, 0, 8'b01101011);
	@(posedge clk);
	@(posedge clk);
	cycle(1, 0, 8'b01000101);
	#100;
	wait (uart_snd.regs.state==0 && uart_snd.regs.tf_count==0);
	#100;
	$finish;
	
end


initial
begin
	#11;
	wb1_stb_ir = 0;
	wb1_cyc_ir = 0;
	wb1_we_ir = 0;
	


	cycle1(1, `REG_LC, 8'b10011011);

	cycle1(1, `REG_DL1, 8'd2);
	@(posedge clk);
	@(posedge clk);

	cycle1(1, `REG_LC, 8'b00011011);
end






always
begin
	#5 clkr = ~clk;
end

endmodule