data/full_repos/permissive/445357518/regfile.v
data/verilator_xmls/552fc6b0-b9bc-4c4f-a7cc-ce192500d309.xml
module vDFF1(clk, in, RNin, out);
	parameter n = 16;
	input clk;
	input [n-1:0] in;
	input RNin;
	output [n-1:0] out;
	reg [n-1:0] out;
	

	always @(posedge clk)
		if (RNin == 1'b1)
			out = in;
                else out=out;
	
endmodule
module vDFF1(clk, in, RNin, out);

	parameter n = 16;
	input clk;
	input [n-1:0] in;
	input RNin;
	output [n-1:0] out;
	reg [n-1:0] out;
	

	always @(posedge clk)
		if (RNin == 1'b1)
			out = in;
                else out=out;
	
endmodule