data/full_repos/permissive/470590146/core/mem_stage.v
1: b'%Warning-WIDTH: data/full_repos/permissive/470590146/core/mem_stage.v:76: Operator ASSIGNW expects 38 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 39 bits.\n                                                                        : ... In instance mem_stage\nassign ms2ws_bus_reg = {\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module mem_stage (
	 input 			clk
	,input 			rst_n

    ,input  es_valid
    ,input  ws_ready
    ,output ms_ready
    ,output ms_valid

    ,output             data_ram_wen
    ,output             data_ram_ren
    ,output     [31:0]  data_ram_addr
    ,output     [31:0]  data_ram_wdata
    ,input      [31:0]  data_ram_rdata
    ,output     [31:0]  ms_mem_out

	,output 		    pc_src
    ,output     [31:0]  ms_pc

    ,input      [106:0] es2ms_bus
    ,output reg [ 37:0] ms2ws_bus
);

wire [31:0] es_pc            ;
wire [31:0] es_alu_result    ;
wire [31:0] es_data_ram_wdata;
wire [ 4:0] es_rd            ;
wire [ 4:0] es_ctrl          ;
wire 		es_zero          ;

assign {
    es_pc,
    es_alu_result,
    es_data_ram_wdata,
    es_rd,
    es_ctrl,
    es_zero
} = es2ms_bus;

wire branch                  ;
wire mem_read                ;
wire mem_write               ;

assign branch    = es_ctrl[4];
assign mem_read  = es_ctrl[3];
assign mem_write = es_ctrl[2];

wire [31:0] ms_alu_result;
wire [ 4:0] ms_rd        ;
wire [ 1:0] ms_ctrl      ;


assign pc_src        = branch & es_zero;
assign ms_pc         = es_pc;


assign ms_alu_result = es_alu_result    ;
assign ms_rd         = es_rd            ;
assign ms_ctrl       = es_ctrl[1:0]     ;

wire [37:0] ms2ws_bus_reg;
assign ms2ws_bus_reg = {
    ms_alu_result,
    ms_rd        ,
    ms_ctrl
};

wire ms_ok_go = 1'b1;
reg  ms_valid_pre;

assign ms_ready = !es_valid || ms_ok_go && ws_ready;
assign ms_valid = ms_valid_pre && ms_ok_go;

always @(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0) begin
        ms_valid_pre <= 0;
    end
    else if (ms_ready) begin
        ms_valid_pre <= es_valid;
    end


    if (ms_ready && es_valid) begin
        ms2ws_bus <= ms2ws_bus_reg;
    end
end

assign data_ram_wen  = mem_write && ms_ready && es_valid;
assign data_ram_ren  = mem_read  && ms_ready && es_valid;
assign data_ram_addr = es_alu_result                    ;
assign data_ram_wdata = es_data_ram_wdata;
assign ms_mem_out    = data_ram_rdata                   ;

endmodule
module mem_stage (
	 input 			clk
	,input 			rst_n

    ,input  es_valid
    ,input  ws_ready
    ,output ms_ready
    ,output ms_valid

    ,output             data_ram_wen
    ,output             data_ram_ren
    ,output     [31:0]  data_ram_addr
    ,output     [31:0]  data_ram_wdata
    ,input      [31:0]  data_ram_rdata
    ,output     [31:0]  ms_mem_out

	,output 		    pc_src
    ,output     [31:0]  ms_pc

    ,input      [106:0] es2ms_bus
    ,output reg [ 37:0] ms2ws_bus
);


wire [31:0] es_pc            ;
wire [31:0] es_alu_result    ;
wire [31:0] es_data_ram_wdata;
wire [ 4:0] es_rd            ;
wire [ 4:0] es_ctrl          ;
wire 		es_zero          ;

assign {
    es_pc,
    es_alu_result,
    es_data_ram_wdata,
    es_rd,
    es_ctrl,
    es_zero
} = es2ms_bus;

wire branch                  ;
wire mem_read                ;
wire mem_write               ;

assign branch    = es_ctrl[4];
assign mem_read  = es_ctrl[3];
assign mem_write = es_ctrl[2];

wire [31:0] ms_alu_result;
wire [ 4:0] ms_rd        ;
wire [ 1:0] ms_ctrl      ;


assign pc_src        = branch & es_zero;
assign ms_pc         = es_pc;


assign ms_alu_result = es_alu_result    ;
assign ms_rd         = es_rd            ;
assign ms_ctrl       = es_ctrl[1:0]     ;

wire [37:0] ms2ws_bus_reg;
assign ms2ws_bus_reg = {
    ms_alu_result,
    ms_rd        ,
    ms_ctrl
};

wire ms_ok_go = 1'b1;
reg  ms_valid_pre;

assign ms_ready = !es_valid || ms_ok_go && ws_ready;
assign ms_valid = ms_valid_pre && ms_ok_go;

always @(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0) begin
        ms_valid_pre <= 0;
    end
    else if (ms_ready) begin
        ms_valid_pre <= es_valid;
    end


    if (ms_ready && es_valid) begin
        ms2ws_bus <= ms2ws_bus_reg;
    end
end

assign data_ram_wen  = mem_write && ms_ready && es_valid;
assign data_ram_ren  = mem_read  && ms_ready && es_valid;
assign data_ram_addr = es_alu_result                    ;
assign data_ram_wdata = es_data_ram_wdata;
assign ms_mem_out    = data_ram_rdata                   ;

endmodule