data/full_repos/permissive/519458744/BLI201V32ITL/rtl/periph/bli201v32itl_gpio.v
1: b'%Error: data/full_repos/permissive/519458744/BLI201V32ITL/rtl/periph/bli201v32itl_gpio.v:1: Cannot find include file: bli201v32itl_tl_defines.vh\n`include "bli201v32itl_tl_defines.vh" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/519458744/BLI201V32ITL/rtl/periph,data/full_repos/permissive/519458744/bli201v32itl_tl_defines.vh\n             data/full_repos/permissive/519458744/BLI201V32ITL/rtl/periph,data/full_repos/permissive/519458744/bli201v32itl_tl_defines.vh.v\n             data/full_repos/permissive/519458744/BLI201V32ITL/rtl/periph,data/full_repos/permissive/519458744/bli201v32itl_tl_defines.vh.sv\n             bli201v32itl_tl_defines.vh\n             bli201v32itl_tl_defines.vh.v\n             bli201v32itl_tl_defines.vh.sv\n             obj_dir/bli201v32itl_tl_defines.vh\n             obj_dir/bli201v32itl_tl_defines.vh.v\n             obj_dir/bli201v32itl_tl_defines.vh.sv\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/rtl/periph/bli201v32itl_gpio.v:7: Define or directive not defined: \'`TL_A_WIDTH_OPCODE\'\n  input  [`TL_A_WIDTH_OPCODE-1:0]   gpio_i_tl_a_opcode,\n          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/rtl/periph/bli201v32itl_gpio.v:8: Define or directive not defined: \'`TL_A_WIDTH_PARAM\'\n  input  [`TL_A_WIDTH_PARAM-1:0]    gpio_i_tl_a_param,\n          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/rtl/periph/bli201v32itl_gpio.v:9: Define or directive not defined: \'`TL_A_WIDTH_SIZE\'\n  input  [`TL_A_WIDTH_SIZE-1:0]     gpio_i_tl_a_size,\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/rtl/periph/bli201v32itl_gpio.v:10: Define or directive not defined: \'`TL_A_WIDTH_SOURCE\'\n  input  [`TL_A_WIDTH_SOURCE-1:0]   gpio_i_tl_a_source,\n          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/rtl/periph/bli201v32itl_gpio.v:11: Define or directive not defined: \'`TL_A_WIDTH_ADDRESS\'\n  input  [`TL_A_WIDTH_ADDRESS-1:0]  gpio_i_tl_a_address,\n          ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/rtl/periph/bli201v32itl_gpio.v:12: Define or directive not defined: \'`TL_A_WIDTH_MASK\'\n  input  [`TL_A_WIDTH_MASK-1:0]     gpio_i_tl_a_mask,\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/rtl/periph/bli201v32itl_gpio.v:13: Define or directive not defined: \'`TL_A_WIDTH_DATA\'\n  input  [`TL_A_WIDTH_DATA-1:0]     gpio_i_tl_a_data,\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/rtl/periph/bli201v32itl_gpio.v:14: Define or directive not defined: \'`TL_A_WIDTH_CORRUPT\'\n  input  [`TL_A_WIDTH_CORRUPT-1:0]  gpio_i_tl_a_corrupt,\n          ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/rtl/periph/bli201v32itl_gpio.v:18: Define or directive not defined: \'`TL_D_WIDTH_OPCODE\'\n  output [`TL_D_WIDTH_OPCODE-1:0]   gpio_o_tl_d_opcode,\n          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/rtl/periph/bli201v32itl_gpio.v:19: Define or directive not defined: \'`TL_D_WIDTH_PARAM\'\n  output [`TL_D_WIDTH_PARAM-1:0]    gpio_o_tl_d_param,\n          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/rtl/periph/bli201v32itl_gpio.v:20: Define or directive not defined: \'`TL_D_WIDTH_SIZE\'\n  output [`TL_D_WIDTH_SIZE-1:0]     gpio_o_tl_d_size,\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/rtl/periph/bli201v32itl_gpio.v:21: Define or directive not defined: \'`TL_D_WIDTH_SOURCE\'\n  output [`TL_D_WIDTH_SOURCE-1:0]   gpio_o_tl_d_source,\n          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/rtl/periph/bli201v32itl_gpio.v:22: Define or directive not defined: \'`TL_D_WIDTH_SINK\'\n  output [`TL_D_WIDTH_SINK-1:0]     gpio_o_tl_d_sink,\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/rtl/periph/bli201v32itl_gpio.v:23: Define or directive not defined: \'`TL_D_WIDTH_DENIED\'\n  output [`TL_D_WIDTH_DENIED-1:0]   gpio_o_tl_d_denied,\n          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/rtl/periph/bli201v32itl_gpio.v:24: Define or directive not defined: \'`TL_D_WIDTH_DATA\'\n  output [`TL_D_WIDTH_DATA-1:0]     gpio_o_tl_d_data,\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/rtl/periph/bli201v32itl_gpio.v:25: Define or directive not defined: \'`TL_D_WIDTH_CORRUPT\'\n  output [`TL_D_WIDTH_CORRUPT-1:0]  gpio_o_tl_d_corrupt,\n          ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 17 error(s)\n'
module gpio (
  input  clk,
  input  rst,
  
  input  [`TL_A_WIDTH_OPCODE-1:0]   gpio_i_tl_a_opcode,
  input  [`TL_A_WIDTH_PARAM-1:0]    gpio_i_tl_a_param,
  input  [`TL_A_WIDTH_SIZE-1:0]     gpio_i_tl_a_size,
  input  [`TL_A_WIDTH_SOURCE-1:0]   gpio_i_tl_a_source,
  input  [`TL_A_WIDTH_ADDRESS-1:0]  gpio_i_tl_a_address,
  input  [`TL_A_WIDTH_MASK-1:0]     gpio_i_tl_a_mask,
  input  [`TL_A_WIDTH_DATA-1:0]     gpio_i_tl_a_data,
  input  [`TL_A_WIDTH_CORRUPT-1:0]  gpio_i_tl_a_corrupt,
  input                             gpio_i_tl_a_valid,
  output                            gpio_o_tl_a_ready,
  
  output [`TL_D_WIDTH_OPCODE-1:0]   gpio_o_tl_d_opcode,
  output [`TL_D_WIDTH_PARAM-1:0]    gpio_o_tl_d_param,
  output [`TL_D_WIDTH_SIZE-1:0]     gpio_o_tl_d_size,
  output [`TL_D_WIDTH_SOURCE-1:0]   gpio_o_tl_d_source,
  output [`TL_D_WIDTH_SINK-1:0]     gpio_o_tl_d_sink,
  output [`TL_D_WIDTH_DENIED-1:0]   gpio_o_tl_d_denied,
  output [`TL_D_WIDTH_DATA-1:0]     gpio_o_tl_d_data,
  output [`TL_D_WIDTH_CORRUPT-1:0]  gpio_o_tl_d_corrupt,
  output                            gpio_o_tl_d_valid,
  input                             gpio_i_tl_d_ready,
  
  output [3:0] gpio_o_gpio_led,
  input  [3:0] gpio_i_gpio_btn,
  input  [3:0] gpio_i_gpio_sw
);

  wire [31:0] address;
  wire        w_en;
  wire [31:0] w_data;
  wire [31:0] r_data;
  
  wire is_gpio_idr;
  wire is_gpio_odr;

  wire [31:0] gpio_idr_rdata;
  wire [31:0] gpio_odr_rdata;
  
  assign is_gpio_idr = address === 'h0000_0000;
  assign is_gpio_odr = address === 'h0000_0004;
   
  assign r_data = is_gpio_idr ? gpio_idr_rdata :
                  is_gpio_odr ? gpio_odr_rdata : 
                  'hCCCC_CCCC;
  
  
  assign gpio_o_gpio_led = gpio_odr_rdata[3:0];
  
  tl2reg_adapter u_adapter (
    .clk(clk),
    .rst(rst),
    
    .adapter_i_tl_a_opcode(gpio_i_tl_a_opcode),
    .adapter_i_tl_a_param(gpio_i_tl_a_param),
    .adapter_i_tl_a_size(gpio_i_tl_a_size),
    .adapter_i_tl_a_source(gpio_i_tl_a_source),
    .adapter_i_tl_a_address(gpio_i_tl_a_address),
    .adapter_i_tl_a_mask(gpio_i_tl_a_mask),
    .adapter_i_tl_a_data(gpio_i_tl_a_data),
    .adapter_i_tl_a_corrupt(gpio_i_tl_a_corrupt),
    .adapter_i_tl_a_valid(gpio_i_tl_a_valid),
    .adapter_o_tl_a_ready(gpio_o_tl_a_ready),

    .adapter_o_tl_d_opcode(gpio_o_tl_d_opcode),
    .adapter_o_tl_d_param(gpio_o_tl_d_param),
    .adapter_o_tl_d_size(gpio_o_tl_d_size),
    .adapter_o_tl_d_source(gpio_o_tl_d_source),
    .adapter_o_tl_d_sink(gpio_o_tl_d_sink),
    .adapter_o_tl_d_denied(gpio_o_tl_d_denied),
    .adapter_o_tl_d_data(gpio_o_tl_d_data),
    .adapter_o_tl_d_corrupt(gpio_o_tl_d_corrupt),
    .adapter_o_tl_d_valid(gpio_o_tl_d_valid),
    .adapter_i_tl_d_ready(gpio_i_tl_d_ready),
    
    .adapter_o_address(address),
    .adapter_o_r_en(),
    .adapter_o_w_en(w_en),
    .adapter_o_wmask(),
    .adapter_o_wdata(w_data),
    .adapter_i_rdata(r_data),
    .adapter_i_err('b0)
  );

  DFF_REG #(.N(32)) u_gpio_idr (
    .C(clk),
    .D({24'h0, gpio_i_gpio_btn, gpio_i_gpio_sw}),
    .Q(gpio_idr_rdata)
  );
  
  DFF_REG_RCE #(.N(32)) u_gpio_odr (
    .C(clk),
    .R(rst),
    .CE(is_gpio_odr && w_en),
    .D(w_data),
    .Q(gpio_odr_rdata)
  );

endmodule
module gpio (
  input  clk,
  input  rst,
  
  input  [`TL_A_WIDTH_OPCODE-1:0]   gpio_i_tl_a_opcode,
  input  [`TL_A_WIDTH_PARAM-1:0]    gpio_i_tl_a_param,
  input  [`TL_A_WIDTH_SIZE-1:0]     gpio_i_tl_a_size,
  input  [`TL_A_WIDTH_SOURCE-1:0]   gpio_i_tl_a_source,
  input  [`TL_A_WIDTH_ADDRESS-1:0]  gpio_i_tl_a_address,
  input  [`TL_A_WIDTH_MASK-1:0]     gpio_i_tl_a_mask,
  input  [`TL_A_WIDTH_DATA-1:0]     gpio_i_tl_a_data,
  input  [`TL_A_WIDTH_CORRUPT-1:0]  gpio_i_tl_a_corrupt,
  input                             gpio_i_tl_a_valid,
  output                            gpio_o_tl_a_ready,
  
  output [`TL_D_WIDTH_OPCODE-1:0]   gpio_o_tl_d_opcode,
  output [`TL_D_WIDTH_PARAM-1:0]    gpio_o_tl_d_param,
  output [`TL_D_WIDTH_SIZE-1:0]     gpio_o_tl_d_size,
  output [`TL_D_WIDTH_SOURCE-1:0]   gpio_o_tl_d_source,
  output [`TL_D_WIDTH_SINK-1:0]     gpio_o_tl_d_sink,
  output [`TL_D_WIDTH_DENIED-1:0]   gpio_o_tl_d_denied,
  output [`TL_D_WIDTH_DATA-1:0]     gpio_o_tl_d_data,
  output [`TL_D_WIDTH_CORRUPT-1:0]  gpio_o_tl_d_corrupt,
  output                            gpio_o_tl_d_valid,
  input                             gpio_i_tl_d_ready,
  
  output [3:0] gpio_o_gpio_led,
  input  [3:0] gpio_i_gpio_btn,
  input  [3:0] gpio_i_gpio_sw
);


  wire [31:0] address;
  wire        w_en;
  wire [31:0] w_data;
  wire [31:0] r_data;
  
  wire is_gpio_idr;
  wire is_gpio_odr;

  wire [31:0] gpio_idr_rdata;
  wire [31:0] gpio_odr_rdata;
  
  assign is_gpio_idr = address === 'h0000_0000;
  assign is_gpio_odr = address === 'h0000_0004;
   
  assign r_data = is_gpio_idr ? gpio_idr_rdata :
                  is_gpio_odr ? gpio_odr_rdata : 
                  'hCCCC_CCCC;
  
  
  assign gpio_o_gpio_led = gpio_odr_rdata[3:0];
  
  tl2reg_adapter u_adapter (
    .clk(clk),
    .rst(rst),
    
    .adapter_i_tl_a_opcode(gpio_i_tl_a_opcode),
    .adapter_i_tl_a_param(gpio_i_tl_a_param),
    .adapter_i_tl_a_size(gpio_i_tl_a_size),
    .adapter_i_tl_a_source(gpio_i_tl_a_source),
    .adapter_i_tl_a_address(gpio_i_tl_a_address),
    .adapter_i_tl_a_mask(gpio_i_tl_a_mask),
    .adapter_i_tl_a_data(gpio_i_tl_a_data),
    .adapter_i_tl_a_corrupt(gpio_i_tl_a_corrupt),
    .adapter_i_tl_a_valid(gpio_i_tl_a_valid),
    .adapter_o_tl_a_ready(gpio_o_tl_a_ready),

    .adapter_o_tl_d_opcode(gpio_o_tl_d_opcode),
    .adapter_o_tl_d_param(gpio_o_tl_d_param),
    .adapter_o_tl_d_size(gpio_o_tl_d_size),
    .adapter_o_tl_d_source(gpio_o_tl_d_source),
    .adapter_o_tl_d_sink(gpio_o_tl_d_sink),
    .adapter_o_tl_d_denied(gpio_o_tl_d_denied),
    .adapter_o_tl_d_data(gpio_o_tl_d_data),
    .adapter_o_tl_d_corrupt(gpio_o_tl_d_corrupt),
    .adapter_o_tl_d_valid(gpio_o_tl_d_valid),
    .adapter_i_tl_d_ready(gpio_i_tl_d_ready),
    
    .adapter_o_address(address),
    .adapter_o_r_en(),
    .adapter_o_w_en(w_en),
    .adapter_o_wmask(),
    .adapter_o_wdata(w_data),
    .adapter_i_rdata(r_data),
    .adapter_i_err('b0)
  );

  DFF_REG #(.N(32)) u_gpio_idr (
    .C(clk),
    .D({24'h0, gpio_i_gpio_btn, gpio_i_gpio_sw}),
    .Q(gpio_idr_rdata)
  );
  
  DFF_REG_RCE #(.N(32)) u_gpio_odr (
    .C(clk),
    .R(rst),
    .CE(is_gpio_odr && w_en),
    .D(w_data),
    .Q(gpio_odr_rdata)
  );

endmodule