data/full_repos/permissive/496266817/tb/tb_scrypt_new_proposed.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/496266817/tb/tb_scrypt_new_proposed.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #(HALF_PERIOD_CLOCK) clk <= ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/496266817/tb/tb_scrypt_new_proposed.v:66: Unsupported: Ignoring delay on this delayed statement.\n   #(HALF_PERIOD_CLOCK*2*num_delay)      reset_n = 1\'b1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/496266817/tb/tb_scrypt_new_proposed.v:67: Unsupported: Ignoring delay on this delayed statement.\n   #(HALF_PERIOD_CLOCK*2)    init    = 1\'b1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/496266817/tb/tb_scrypt_new_proposed.v:81: Unsupported: Ignoring delay on this delayed statement.\n        #(HALF_PERIOD_CLOCK*2*2)\n        ^\n%Error: data/full_repos/permissive/496266817/tb/tb_scrypt_new_proposed.v:18: Cannot find file containing module: \'scrypt_new_proposed\'\n scrypt_new_proposed scrypt_new_ip(\n ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/496266817/tb,data/full_repos/permissive/496266817/scrypt_new_proposed\n             data/full_repos/permissive/496266817/tb,data/full_repos/permissive/496266817/scrypt_new_proposed.v\n             data/full_repos/permissive/496266817/tb,data/full_repos/permissive/496266817/scrypt_new_proposed.sv\n             scrypt_new_proposed\n             scrypt_new_proposed.v\n             scrypt_new_proposed.sv\n             obj_dir/scrypt_new_proposed\n             obj_dir/scrypt_new_proposed.v\n             obj_dir/scrypt_new_proposed.sv\n%Warning-WIDTH: data/full_repos/permissive/496266817/tb/tb_scrypt_new_proposed.v:46: Operator SUB expects 64 bits on the RHS, but RHS\'s VARREF \'start_time\' generates 32 bits.\n                                                                                   : ... In instance tb_scrypt_new_proposed\n   $display("Output scrypt: %x cycle: %f", out_scrypt, ($time-start_time)/(HALF_PERIOD_CLOCK*2));\n                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/496266817/tb/tb_scrypt_new_proposed.v:68: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s TIME generates 64 bits.\n                                                                                   : ... In instance tb_scrypt_new_proposed\n   start_time = $time;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/496266817/tb/tb_scrypt_new_proposed.v:88: Operator TASKREF \'reset_task\' expects 8 bits on the Function Argument, but Function Argument\'s CONST \'3\'h5\' generates 3 bits.\n                                                                                   : ... In instance tb_scrypt_new_proposed\n  reset_task(3\'d5);\n  ^~~~~~~~~~\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_scrypt_new_proposed();
    reg                             clk                                 ;
    reg                             reset_n                             ;
    reg                             init                                ;
    reg    [639:0]                  in                                  ;
    wire   [255:0]                  out_scrypt                          ;
    wire                            valid                               ;
    wire                            ready_in                            ;

    integer                         count_in = 0                        ;       
    parameter	WIDTH_IN		= 640;
    parameter	WIDTH_OUT		= 256;
    parameter	NUM_TESTCASE	= 40;
    reg 	[WIDTH_IN - 1:0]		SCRYPT_IN		[0:NUM_TESTCASE-1]  ;
    reg 	[WIDTH_OUT - 1:0]		SCRYPT_OUT		[0:NUM_TESTCASE-1]  ;
    
	scrypt_new_proposed	scrypt_new_ip(
				.clk       	(clk        ) ,
				.reset_n   	(reset_n    ) ,
				.init      	(init       ) ,
				.in        	(in         ) ,
				.out_scrypt	(out_scrypt ) ,
                .ready_in   (ready_in   ) ,
				.valid	    (valid      )
	);
	
	initial begin
		$readmemh("E:/Projects/scrypt_155MHz_9037reg_9583LUT_29BRAM/Testcases/BlockHeader.txt", SCRYPT_IN);
		$readmemh("E:/Projects/scrypt_155MHz_9037reg_9583LUT_29BRAM/Testcases/ScryptOut.txt", SCRYPT_OUT);
	end
    integer num_valid = 0;
	parameter HALF_PERIOD_CLOCK = 10;
	integer i;
	integer start_time;
	integer display_pbdkf2 = 1;
	always @(*) 
	begin: clock_generator
		#(HALF_PERIOD_CLOCK) clk <= ~clk;
	end
	always @(posedge valid) 
	begin
		if(valid== 1'b1) begin
            $display("Time: %t", $time);
            $display("Test cases: %d", num_valid);
			$display("Output scrypt: %x cycle: %f", out_scrypt, ($time-start_time)/(HALF_PERIOD_CLOCK*2));
            $display("Golden out:   %x", SCRYPT_OUT[num_valid]);
            if(num_valid == NUM_TESTCASE - 1) begin
                $display("Test completed, time: %t!", $time);
               $stop;
            end
            num_valid = num_valid + 1;
		end
	end
	task init_task();
		begin
			clk  		=   1'b0                ;
			init 		=   1'b0                ;
			reset_n 	=   1'b0                ;
            in          =   SCRYPT_IN[count_in] ;
		end
	endtask
	
	task reset_task (input reg[7:0] num_delay);
		begin
			#(HALF_PERIOD_CLOCK*2*num_delay) 	    reset_n = 1'b1;
			#(HALF_PERIOD_CLOCK*2)				init    = 1'b1;
			start_time = $time;
		end
	endtask
    
	always @(posedge ready_in) begin
        if(count_in < NUM_TESTCASE) begin
            count_in <= count_in + 1    ;
        end
        else begin
            count_in <= count_in        ;
        end
        init  <=   1'b0                  ;
        in    <=   SCRYPT_IN[count_in + 1]   ;
        #(HALF_PERIOD_CLOCK*2*2)
        init  <=   1'b1                  ;
    end
    
	initial begin: main_test
		$display("Test starts!");
		init_task();
		reset_task(3'd5);
	end
		
endmodule
module tb_scrypt_new_proposed();

    reg                             clk                                 ;
    reg                             reset_n                             ;
    reg                             init                                ;
    reg    [639:0]                  in                                  ;
    wire   [255:0]                  out_scrypt                          ;
    wire                            valid                               ;
    wire                            ready_in                            ;

    integer                         count_in = 0                        ;       
    parameter	WIDTH_IN		= 640;
    parameter	WIDTH_OUT		= 256;
    parameter	NUM_TESTCASE	= 40;
    reg 	[WIDTH_IN - 1:0]		SCRYPT_IN		[0:NUM_TESTCASE-1]  ;
    reg 	[WIDTH_OUT - 1:0]		SCRYPT_OUT		[0:NUM_TESTCASE-1]  ;
    
	scrypt_new_proposed	scrypt_new_ip(
				.clk       	(clk        ) ,
				.reset_n   	(reset_n    ) ,
				.init      	(init       ) ,
				.in        	(in         ) ,
				.out_scrypt	(out_scrypt ) ,
                .ready_in   (ready_in   ) ,
				.valid	    (valid      )
	);
	
	initial begin
		$readmemh("E:/Projects/scrypt_155MHz_9037reg_9583LUT_29BRAM/Testcases/BlockHeader.txt", SCRYPT_IN);
		$readmemh("E:/Projects/scrypt_155MHz_9037reg_9583LUT_29BRAM/Testcases/ScryptOut.txt", SCRYPT_OUT);
	end
    integer num_valid = 0;
	parameter HALF_PERIOD_CLOCK = 10;
	integer i;
	integer start_time;
	integer display_pbdkf2 = 1;
	always @(*) 
	begin: clock_generator
		#(HALF_PERIOD_CLOCK) clk <= ~clk;
	end
	always @(posedge valid) 
	begin
		if(valid== 1'b1) begin
            $display("Time: %t", $time);
            $display("Test cases: %d", num_valid);
			$display("Output scrypt: %x cycle: %f", out_scrypt, ($time-start_time)/(HALF_PERIOD_CLOCK*2));
            $display("Golden out:   %x", SCRYPT_OUT[num_valid]);
            if(num_valid == NUM_TESTCASE - 1) begin
                $display("Test completed, time: %t!", $time);
               $stop;
            end
            num_valid = num_valid + 1;
		end
	end
	task init_task();
		begin
			clk  		=   1'b0                ;
			init 		=   1'b0                ;
			reset_n 	=   1'b0                ;
            in          =   SCRYPT_IN[count_in] ;
		end
	endtask
	
	task reset_task (input reg[7:0] num_delay);
		begin
			#(HALF_PERIOD_CLOCK*2*num_delay) 	    reset_n = 1'b1;
			#(HALF_PERIOD_CLOCK*2)				init    = 1'b1;
			start_time = $time;
		end
	endtask
    
	always @(posedge ready_in) begin
        if(count_in < NUM_TESTCASE) begin
            count_in <= count_in + 1    ;
        end
        else begin
            count_in <= count_in        ;
        end
        init  <=   1'b0                  ;
        in    <=   SCRYPT_IN[count_in + 1]   ;
        #(HALF_PERIOD_CLOCK*2*2)
        init  <=   1'b1                  ;
    end
    
	initial begin: main_test
		$display("Test starts!");
		init_task();
		reset_task(3'd5);
	end
		
endmodule