data/full_repos/permissive/520452389/source_codes/mem_ld_sv.v
data/verilator_xmls/51d08d3b-81b9-4396-857b-4868e5380a9d.xml
module data_memory (input reset,input MemWrite,input MemRead,input [31:0]ALU_output,input [31:0]read_data2,output reg [31:0]read_data);
reg [31:0]mem[0:31];
reg [31:0]i;

always @(*) begin 
    if(reset)begin 
    for(i = 0; i < 31 ; i = i+1) begin
		mem[i] = 0;
		end
	end
     if(MemRead) begin 
          read_data = mem[ALU_output];
     end
     if(MemWrite) begin 
          mem[ALU_output] = read_data2;
     end
end
endmodule
module data_memory (input reset,input MemWrite,input MemRead,input [31:0]ALU_output,input [31:0]read_data2,output reg [31:0]read_data);

reg [31:0]mem[0:31];
reg [31:0]i;

always @(*) begin 
    if(reset)begin 
    for(i = 0; i < 31 ; i = i+1) begin
		mem[i] = 0;
		end
	end
     if(MemRead) begin 
          read_data = mem[ALU_output];
     end
     if(MemWrite) begin 
          mem[ALU_output] = read_data2;
     end
end
endmodule