data/full_repos/permissive/439731184/simple_task.v
1: b'%Error: data/full_repos/permissive/439731184/simple_task.v:23: Unsupported or unknown PLI call: $monitor\n    $monitor("%b\\t%b", original, reversed);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/439731184/simple_task.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #1 original = 8\'b00000000;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/439731184/simple_task.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #1 original = 8\'b01010101;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/simple_task.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #1 original = 8\'b11110000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/simple_task.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #1 original = 8\'b11001100;\n    ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module simple_task();

parameter N_BITS = 8;

task reverse;
    input [N_BITS-1:0] in;
    output [N_BITS-1:0] out;
    begin
        integer i;
        for (i=0; i<N_BITS; i=i+1) begin
            out[i] = in[N_BITS-i-1];
        end
    end
endtask

reg [N_BITS-1:0] original;
reg [N_BITS-1:0] reversed;

always @ (original) reverse(original, reversed);

initial begin
    $display("original\treversed");
    $monitor("%b\t%b", original, reversed);
    #1 original = 8'b00000000;
    #1 original = 8'b01010101;
    #1 original = 8'b11110000;
    #1 original = 8'b11001100;
end

endmodule
module simple_task();


parameter N_BITS = 8;

task reverse;
    input [N_BITS-1:0] in;
    output [N_BITS-1:0] out;
    begin
        integer i;
        for (i=0; i<N_BITS; i=i+1) begin
            out[i] = in[N_BITS-i-1];
        end
    end
endtask

reg [N_BITS-1:0] original;
reg [N_BITS-1:0] reversed;

always @ (original) reverse(original, reversed);

initial begin
    $display("original\treversed");
    $monitor("%b\t%b", original, reversed);
    #1 original = 8'b00000000;
    #1 original = 8'b01010101;
    #1 original = 8'b11110000;
    #1 original = 8'b11001100;
end

endmodule