data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco/grant_mask.sv
1: b'%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco/grant_mask.sv:44: Cannot find include file: parameters.v\n`include "parameters.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco,data/full_repos/permissive/489147019/parameters.v\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco,data/full_repos/permissive/489147019/parameters.v.v\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco,data/full_repos/permissive/489147019/parameters.v.sv\n             parameters.v\n             parameters.v.v\n             parameters.v.sv\n             obj_dir/parameters.v\n             obj_dir/parameters.v.v\n             obj_dir/parameters.v.sv\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco/grant_mask.sv:79: Define or directive not defined: \'`ADDR_OFFSET\'\n    localparam ADDR_OFFSET = `ADDR_OFFSET(DATA_WIDTH);\n                             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco/grant_mask.sv:134: Define or directive not defined: \'`log2\'\n            case({enable_PIPE_req_i[ data_add_i[`log2(N_SLAVE-1)+ADDR_OFFSET-1:ADDR_OFFSET] ], enable_PIPE_resp_i[data_add_i[`log2(N_SLAVE-1)+ADDR_OFFSET-1:ADDR_OFFSET]]})\n                                                ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco/grant_mask.sv:134: Define or directive not defined: \'`log2\'\n            case({enable_PIPE_req_i[ data_add_i[`log2(N_SLAVE-1)+ADDR_OFFSET-1:ADDR_OFFSET] ], enable_PIPE_resp_i[data_add_i[`log2(N_SLAVE-1)+ADDR_OFFSET-1:ADDR_OFFSET]]})\n                                                                                                                             ^~~~~\n%Error: Exiting due to 4 error(s)\n'
module grant_mask
#(
    parameter ADDR_WIDTH = 32,
    parameter DATA_WIDTH = 32,
    parameter BE_WIDTH   = DATA_WIDTH/8,

    parameter N_SLAVE    = 8,
    parameter TO_SCM_BIT = 15
)
(
    input  logic                         data_req_i,
    input  logic [ADDR_WIDTH-1:0]        data_add_i,
    input  logic                         data_wen_i,
    input  logic [DATA_WIDTH-1:0]        data_wdata_i,
    input  logic [BE_WIDTH-1:0]          data_be_i,
    output logic                         data_gnt_o,

    output  logic                        data_req_o,
    output  logic [ADDR_WIDTH-1:0]       data_add_o,
    output  logic                        data_wen_o,
    output  logic [DATA_WIDTH-1:0]       data_wdata_o,
    output  logic [BE_WIDTH-1:0]         data_be_o,
    input   logic                        data_gnt_i,

    input   logic [N_SLAVE-1:0]          enable_PIPE_req_i,
    input   logic [N_SLAVE-1:0]          enable_PIPE_resp_i,

    output  logic                         data_r_valid_o,

    input logic                         clk,
    input logic                         rst_n
);

    localparam ADDR_OFFSET = `ADDR_OFFSET(DATA_WIDTH);

    enum logic [1:0] {IDLE, SRAM_0, SRAM_1} CS, NS;

    logic to_SCM;

    assign data_add_o   = data_add_i;
    assign data_wen_o   = data_wen_i;
    assign data_wdata_o = data_wdata_i;
    assign data_be_o    = data_be_i;

    always_comb
    begin
      if(data_add_i[TO_SCM_BIT])
        to_SCM = 1'b1;
      else
        to_SCM = 1'b0;
    end

    always_ff @(posedge clk, negedge rst_n)
    begin
      if(rst_n == 1'b0)
      begin
        CS <= IDLE;
        data_r_valid_o <= 1'b0;
      end
      else begin
        CS <= NS;
        data_r_valid_o <= data_req_i & data_gnt_o;
      end
    end


    always_comb
    begin

      data_gnt_o      = 1'b0;
      data_req_o      = 1'b0;
      NS              = CS;

      case(CS)

      IDLE :
        begin
          if(data_req_i)
          begin
          if(to_SCM)
          begin
            data_gnt_o = data_gnt_i;
            data_req_o = data_req_i;
            NS = IDLE;
          end
          else
          begin

            case({enable_PIPE_req_i[ data_add_i[`log2(N_SLAVE-1)+ADDR_OFFSET-1:ADDR_OFFSET] ], enable_PIPE_resp_i[data_add_i[`log2(N_SLAVE-1)+ADDR_OFFSET-1:ADDR_OFFSET]]})

            2'b00: 
            begin 
                NS = IDLE; 
                data_gnt_o = data_gnt_i; 
                data_req_o = data_req_i; 
            end

            2'b01: 
            begin 
                data_gnt_o = 1'b0; 
                data_req_o = data_req_i; 
                if(data_gnt_i)
                  NS = SRAM_0;
                else
                  NS = IDLE;
            end

            2'b10:
            begin 
                data_gnt_o = 1'b0; 
                data_req_o = data_req_i; 
                if(data_gnt_i)
                  NS = SRAM_0;
                else
                  NS = IDLE;
            end

            2'b11: 
            begin 
                data_gnt_o = 1'b0; 
                data_req_o = data_req_i; 
                if(data_gnt_i)
                  NS = SRAM_1;
                else
                  NS = IDLE;
            end

            endcase
          end

          end
          else
          begin
            NS = IDLE; data_gnt_o = 1'b0; data_req_o = 1'b0;
          end

        end

      SRAM_0 : 
        begin
          NS = IDLE; data_gnt_o = 1'b1; data_req_o = 1'b0;
        end

      SRAM_1 :
        begin
          NS = SRAM_0; data_gnt_o = 1'b0; data_req_o = 1'b0; 
        end

      default :
        begin
          NS = IDLE; data_gnt_o = 1'b0; data_req_o = 1'b0;
        end

      endcase
    end





endmodule
module grant_mask
#(
    parameter ADDR_WIDTH = 32,
    parameter DATA_WIDTH = 32,
    parameter BE_WIDTH   = DATA_WIDTH/8,

    parameter N_SLAVE    = 8,
    parameter TO_SCM_BIT = 15
)
(
    input  logic                         data_req_i,
    input  logic [ADDR_WIDTH-1:0]        data_add_i,
    input  logic                         data_wen_i,
    input  logic [DATA_WIDTH-1:0]        data_wdata_i,
    input  logic [BE_WIDTH-1:0]          data_be_i,
    output logic                         data_gnt_o,

    output  logic                        data_req_o,
    output  logic [ADDR_WIDTH-1:0]       data_add_o,
    output  logic                        data_wen_o,
    output  logic [DATA_WIDTH-1:0]       data_wdata_o,
    output  logic [BE_WIDTH-1:0]         data_be_o,
    input   logic                        data_gnt_i,

    input   logic [N_SLAVE-1:0]          enable_PIPE_req_i,
    input   logic [N_SLAVE-1:0]          enable_PIPE_resp_i,

    output  logic                         data_r_valid_o,

    input logic                         clk,
    input logic                         rst_n
);


    localparam ADDR_OFFSET = `ADDR_OFFSET(DATA_WIDTH);

    enum logic [1:0] {IDLE, SRAM_0, SRAM_1} CS, NS;

    logic to_SCM;

    assign data_add_o   = data_add_i;
    assign data_wen_o   = data_wen_i;
    assign data_wdata_o = data_wdata_i;
    assign data_be_o    = data_be_i;

    always_comb
    begin
      if(data_add_i[TO_SCM_BIT])
        to_SCM = 1'b1;
      else
        to_SCM = 1'b0;
    end

    always_ff @(posedge clk, negedge rst_n)
    begin
      if(rst_n == 1'b0)
      begin
        CS <= IDLE;
        data_r_valid_o <= 1'b0;
      end
      else begin
        CS <= NS;
        data_r_valid_o <= data_req_i & data_gnt_o;
      end
    end


    always_comb
    begin

      data_gnt_o      = 1'b0;
      data_req_o      = 1'b0;
      NS              = CS;

      case(CS)

      IDLE :
        begin
          if(data_req_i)
          begin
          if(to_SCM)
          begin
            data_gnt_o = data_gnt_i;
            data_req_o = data_req_i;
            NS = IDLE;
          end
          else
          begin

            case({enable_PIPE_req_i[ data_add_i[`log2(N_SLAVE-1)+ADDR_OFFSET-1:ADDR_OFFSET] ], enable_PIPE_resp_i[data_add_i[`log2(N_SLAVE-1)+ADDR_OFFSET-1:ADDR_OFFSET]]})

            2'b00: 
            begin 
                NS = IDLE; 
                data_gnt_o = data_gnt_i; 
                data_req_o = data_req_i; 
            end

            2'b01: 
            begin 
                data_gnt_o = 1'b0; 
                data_req_o = data_req_i; 
                if(data_gnt_i)
                  NS = SRAM_0;
                else
                  NS = IDLE;
            end

            2'b10:
            begin 
                data_gnt_o = 1'b0; 
                data_req_o = data_req_i; 
                if(data_gnt_i)
                  NS = SRAM_0;
                else
                  NS = IDLE;
            end

            2'b11: 
            begin 
                data_gnt_o = 1'b0; 
                data_req_o = data_req_i; 
                if(data_gnt_i)
                  NS = SRAM_1;
                else
                  NS = IDLE;
            end

            endcase
          end

          end
          else
          begin
            NS = IDLE; data_gnt_o = 1'b0; data_req_o = 1'b0;
          end

        end

      SRAM_0 : 
        begin
          NS = IDLE; data_gnt_o = 1'b1; data_req_o = 1'b0;
        end

      SRAM_1 :
        begin
          NS = SRAM_0; data_gnt_o = 1'b0; data_req_o = 1'b0; 
        end

      default :
        begin
          NS = IDLE; data_gnt_o = 1'b0; data_req_o = 1'b0;
        end

      endcase
    end





endmodule