data/full_repos/permissive/431487364/src/perips/gpio.v
1: b'%Error: data/full_repos/permissive/431487364/src/perips/gpio.v:1: Cannot find include file: ../headers/buceros_header.v\n`include "../headers/buceros_header.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/431487364/src/perips,data/full_repos/permissive/431487364/../headers/buceros_header.v\n             data/full_repos/permissive/431487364/src/perips,data/full_repos/permissive/431487364/../headers/buceros_header.v.v\n             data/full_repos/permissive/431487364/src/perips,data/full_repos/permissive/431487364/../headers/buceros_header.v.sv\n             ../headers/buceros_header.v\n             ../headers/buceros_header.v.v\n             ../headers/buceros_header.v.sv\n             obj_dir/../headers/buceros_header.v\n             obj_dir/../headers/buceros_header.v.v\n             obj_dir/../headers/buceros_header.v.sv\n%Error: data/full_repos/permissive/431487364/src/perips/gpio.v:8: Define or directive not defined: \'`MemAddrBus\'\n    input  wire [`MemAddrBus] addr_i,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/src/perips/gpio.v:8: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input  wire [`MemAddrBus] addr_i,\n                            ^\n%Error: data/full_repos/permissive/431487364/src/perips/gpio.v:10: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire [`MemDataBus] w_data_i,\n    ^~~~~\n%Error: data/full_repos/permissive/431487364/src/perips/gpio.v:10: Define or directive not defined: \'`MemDataBus\'\n    input  wire [`MemDataBus] w_data_i,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/src/perips/gpio.v:13: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [`MemDataBus] r_data_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/431487364/src/perips/gpio.v:13: Define or directive not defined: \'`MemDataBus\'\n    output wire [`MemDataBus] r_data_o,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/src/perips/gpio.v:15: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [        3:0] pin_seg_sel_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/431487364/src/perips/gpio.v:16: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [       15:0] pin_led_o\n    ^~~~~~\n%Error: data/full_repos/permissive/431487364/src/perips/gpio.v:17: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/431487364/src/perips/gpio.v:37: syntax error, unexpected assign\n    assign r_en = en_i & r_en_i;\n    ^~~~~~\n%Error: Exiting due to 11 error(s)\n'
module gpio (
    input  wire               clk,
    input  wire               rst_n,
    input  wire               en_i,

    input  wire               r_en_i,
    input  wire [`MemAddrBus] addr_i,
    input  wire               w_en_i,
    input  wire [`MemDataBus] w_data_i,
    input  wire [       15:0] pin_sw_i,

    output wire [`MemDataBus] r_data_o,
    output wire [        7:0] pin_seg_o,
    output wire [        3:0] pin_seg_sel_o,
    output wire [       15:0] pin_led_o
);

    reg [ 7:0] seg;
    reg [ 3:0] seg_sel;
    reg [15:0] led;

    wire       r_en;
    wire       w_en;
    wire       r_seg;
    wire       r_seg_sel;
    wire       r_led;
    wire       r_sw;
    wire       w_seg;
    wire       w_seg_sel;
    wire       w_led;
    wire       led_en;
    wire       seg_en;
    wire       seg_sel_en;
    wire       sw_en;

    assign r_en = en_i & r_en_i;
    assign w_en = en_i & w_en_i;
    

    assign led_en     = ~addr_i[28] & ~addr_i[3] & ~addr_i[2];
    assign r_led      = r_en & led_en;
    assign w_led      = w_en & led_en;

    assign seg_en = ~addr_i[28] & ~addr_i[3] & addr_i[2];
    assign r_seg = r_en & seg_en;
    assign w_seg = w_en & seg_en;

    assign seg_sel_en = ~addr_i[28] & addr_i[3];
    assign r_seg_sel  = r_en & seg_sel_en;
    assign w_seg_sel  = w_en & seg_sel_en;

    assign sw_en      = addr_i[28];
    assign r_sw       = r_en & sw_en;

    assign pin_seg_sel_o = ~seg_sel;
    assign pin_seg_o     = seg;
    assign pin_led_o     = led;

    assign r_data_o = {16'b0, {16{    r_led}} & led}     |
                      {24'b0, { 8{    r_seg}} & seg}     |
                      {28'b0, { 4{r_seg_sel}} & seg_sel} |
                      {16'b0, {16{     r_sw}} & pin_sw_i};
                      
    always @(posedge clk or negedge rst_n) begin
        if(~rst_n) begin
            seg     <= 8'b0;
            seg_sel <= 4'b0;
            led     <= 16'b0;
        end else begin
            seg     <= w_seg     ? w_data_i[ 7:0] : seg;
            seg_sel <= w_seg_sel ? w_data_i[ 3:0] : seg_sel;
            led     <= w_led     ? w_data_i[15:0] : led;
        end
    end

endmodule
module gpio (
    input  wire               clk,
    input  wire               rst_n,
    input  wire               en_i,

    input  wire               r_en_i,
    input  wire [`MemAddrBus] addr_i,
    input  wire               w_en_i,
    input  wire [`MemDataBus] w_data_i,
    input  wire [       15:0] pin_sw_i,

    output wire [`MemDataBus] r_data_o,
    output wire [        7:0] pin_seg_o,
    output wire [        3:0] pin_seg_sel_o,
    output wire [       15:0] pin_led_o
);


    reg [ 7:0] seg;
    reg [ 3:0] seg_sel;
    reg [15:0] led;

    wire       r_en;
    wire       w_en;
    wire       r_seg;
    wire       r_seg_sel;
    wire       r_led;
    wire       r_sw;
    wire       w_seg;
    wire       w_seg_sel;
    wire       w_led;
    wire       led_en;
    wire       seg_en;
    wire       seg_sel_en;
    wire       sw_en;

    assign r_en = en_i & r_en_i;
    assign w_en = en_i & w_en_i;
    

    assign led_en     = ~addr_i[28] & ~addr_i[3] & ~addr_i[2];
    assign r_led      = r_en & led_en;
    assign w_led      = w_en & led_en;

    assign seg_en = ~addr_i[28] & ~addr_i[3] & addr_i[2];
    assign r_seg = r_en & seg_en;
    assign w_seg = w_en & seg_en;

    assign seg_sel_en = ~addr_i[28] & addr_i[3];
    assign r_seg_sel  = r_en & seg_sel_en;
    assign w_seg_sel  = w_en & seg_sel_en;

    assign sw_en      = addr_i[28];
    assign r_sw       = r_en & sw_en;

    assign pin_seg_sel_o = ~seg_sel;
    assign pin_seg_o     = seg;
    assign pin_led_o     = led;

    assign r_data_o = {16'b0, {16{    r_led}} & led}     |
                      {24'b0, { 8{    r_seg}} & seg}     |
                      {28'b0, { 4{r_seg_sel}} & seg_sel} |
                      {16'b0, {16{     r_sw}} & pin_sw_i};
                      
    always @(posedge clk or negedge rst_n) begin
        if(~rst_n) begin
            seg     <= 8'b0;
            seg_sel <= 4'b0;
            led     <= 16'b0;
        end else begin
            seg     <= w_seg     ? w_data_i[ 7:0] : seg;
            seg_sel <= w_seg_sel ? w_data_i[ 3:0] : seg_sel;
            led     <= w_led     ? w_data_i[15:0] : led;
        end
    end

endmodule