data/full_repos/permissive/48004801/ServoCommander.srcs/sources_1/imports/new/bin_to_bcd.v
1: b'%Warning-WIDTH: data/full_repos/permissive/48004801/ServoCommander.srcs/sources_1/imports/new/bin_to_bcd.v:51: Operator LT expects 32 bits on the LHS, but LHS\'s VARREF \'buffer\' generates 11 bits.\n                                                                                                             : ... In instance bin_to_bcd\n   if(buffer < sub*THOU) begin\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/48004801/ServoCommander.srcs/sources_1/imports/new/bin_to_bcd.v:54: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'buffer\' generates 11 bits.\n                                                                                                             : ... In instance bin_to_bcd\n      buffer = buffer - sub*THOU;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/48004801/ServoCommander.srcs/sources_1/imports/new/bin_to_bcd.v:54: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                                                             : ... In instance bin_to_bcd\n      buffer = buffer - sub*THOU;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/48004801/ServoCommander.srcs/sources_1/imports/new/bin_to_bcd.v:55: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'sub\' generates 32 bits.\n                                                                                                             : ... In instance bin_to_bcd\n      thousands = sub;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/48004801/ServoCommander.srcs/sources_1/imports/new/bin_to_bcd.v:64: Operator LT expects 32 bits on the LHS, but LHS\'s VARREF \'buffer\' generates 11 bits.\n                                                                                                             : ... In instance bin_to_bcd\n   if(buffer < sub*HUND) begin\n             ^\n%Warning-WIDTH: data/full_repos/permissive/48004801/ServoCommander.srcs/sources_1/imports/new/bin_to_bcd.v:67: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'buffer\' generates 11 bits.\n                                                                                                             : ... In instance bin_to_bcd\n      buffer = buffer - sub*HUND;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/48004801/ServoCommander.srcs/sources_1/imports/new/bin_to_bcd.v:67: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                                                             : ... In instance bin_to_bcd\n      buffer = buffer - sub*HUND;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/48004801/ServoCommander.srcs/sources_1/imports/new/bin_to_bcd.v:68: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'sub\' generates 32 bits.\n                                                                                                             : ... In instance bin_to_bcd\n      hundreds = sub;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/48004801/ServoCommander.srcs/sources_1/imports/new/bin_to_bcd.v:77: Operator LT expects 32 bits on the LHS, but LHS\'s VARREF \'buffer\' generates 11 bits.\n                                                                                                             : ... In instance bin_to_bcd\n   if(buffer < sub*TENS) begin\n             ^\n%Warning-WIDTH: data/full_repos/permissive/48004801/ServoCommander.srcs/sources_1/imports/new/bin_to_bcd.v:80: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'buffer\' generates 11 bits.\n                                                                                                             : ... In instance bin_to_bcd\n      buffer = buffer - sub*TENS;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/48004801/ServoCommander.srcs/sources_1/imports/new/bin_to_bcd.v:80: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                                                             : ... In instance bin_to_bcd\n      buffer = buffer - sub*TENS;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/48004801/ServoCommander.srcs/sources_1/imports/new/bin_to_bcd.v:81: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'sub\' generates 32 bits.\n                                                                                                             : ... In instance bin_to_bcd\n      tens = sub;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/48004801/ServoCommander.srcs/sources_1/imports/new/bin_to_bcd.v:90: Operator LT expects 32 bits on the LHS, but LHS\'s VARREF \'buffer\' generates 11 bits.\n                                                                                                             : ... In instance bin_to_bcd\n   if(buffer < sub) begin\n             ^\n%Warning-WIDTH: data/full_repos/permissive/48004801/ServoCommander.srcs/sources_1/imports/new/bin_to_bcd.v:93: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'buffer\' generates 11 bits.\n                                                                                                             : ... In instance bin_to_bcd\n      buffer = buffer - sub;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/48004801/ServoCommander.srcs/sources_1/imports/new/bin_to_bcd.v:93: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                                                             : ... In instance bin_to_bcd\n      buffer = buffer - sub;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/48004801/ServoCommander.srcs/sources_1/imports/new/bin_to_bcd.v:94: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'sub\' generates 32 bits.\n                                                                                                             : ... In instance bin_to_bcd\n      ones = sub;\n           ^\n%Error: Exiting due to 16 warning(s)\n'
module bin_to_bcd(
    input wire [10:0] bin,
    output reg [3:0] ones,
    output reg [3:0] tens,
    output reg [3:0] hundreds,
    output reg [3:0] thousands
);
parameter THOU = 1000;
parameter HUND = 100;
parameter TENS = 10;
parameter ONES = 1;

reg [10:0] buffer;
integer i;
integer sub;

always @ (*)
begin
	buffer = bin;
	ones = 4'd0;
    tens = 4'd0;
    hundreds = 4'd0;
    thousands = 4'd0;
    sub = 0;
     if(buffer >= THOU) begin
     	for(i = 0; i < 10; i = i + 1) begin
     		if(i*THOU < buffer) begin
     			sub = sub + 1;
     		end
     	end
 		if(buffer < sub*THOU) begin
 			sub = sub - 1;
 		end
     	buffer = buffer - sub*THOU;
     	thousands = sub;
     end
     sub = 0;
     if(buffer >= HUND) begin
     	for(i = 0; i < 10; i = i + 1) begin
     		if(i*HUND < buffer) begin
     			sub = sub + 1;
     		end
     	end
 		if(buffer < sub*HUND) begin
 			sub = sub - 1;
 		end
     	buffer = buffer - sub*HUND;
     	hundreds = sub;
     end
     sub = 0;
     if(buffer >= TENS) begin
     	for(i = 0; i < 10; i = i + 1) begin
     		if(i*TENS < buffer) begin
     			sub = sub + 1;
     		end
     	end
 		if(buffer < sub*TENS) begin
 			sub = sub - 1;
 		end
     	buffer = buffer - sub*TENS;
     	tens = sub;
     end
     sub = 0;
     if(buffer >= ONES) begin
     	for(i = 0; i < 10; i = i + 1) begin
     		if(i*ONES < buffer) begin
     			sub = sub + 1;
     		end
     	end
 		if(buffer < sub) begin
 			sub = sub - 1;
 		end
     	buffer = buffer - sub;
     	ones = sub;
     end
end

endmodule
module bin_to_bcd(
    input wire [10:0] bin,
    output reg [3:0] ones,
    output reg [3:0] tens,
    output reg [3:0] hundreds,
    output reg [3:0] thousands
);

parameter THOU = 1000;
parameter HUND = 100;
parameter TENS = 10;
parameter ONES = 1;

reg [10:0] buffer;
integer i;
integer sub;

always @ (*)
begin
	buffer = bin;
	ones = 4'd0;
    tens = 4'd0;
    hundreds = 4'd0;
    thousands = 4'd0;
    sub = 0;
     if(buffer >= THOU) begin
     	for(i = 0; i < 10; i = i + 1) begin
     		if(i*THOU < buffer) begin
     			sub = sub + 1;
     		end
     	end
 		if(buffer < sub*THOU) begin
 			sub = sub - 1;
 		end
     	buffer = buffer - sub*THOU;
     	thousands = sub;
     end
     sub = 0;
     if(buffer >= HUND) begin
     	for(i = 0; i < 10; i = i + 1) begin
     		if(i*HUND < buffer) begin
     			sub = sub + 1;
     		end
     	end
 		if(buffer < sub*HUND) begin
 			sub = sub - 1;
 		end
     	buffer = buffer - sub*HUND;
     	hundreds = sub;
     end
     sub = 0;
     if(buffer >= TENS) begin
     	for(i = 0; i < 10; i = i + 1) begin
     		if(i*TENS < buffer) begin
     			sub = sub + 1;
     		end
     	end
 		if(buffer < sub*TENS) begin
 			sub = sub - 1;
 		end
     	buffer = buffer - sub*TENS;
     	tens = sub;
     end
     sub = 0;
     if(buffer >= ONES) begin
     	for(i = 0; i < 10; i = i + 1) begin
     		if(i*ONES < buffer) begin
     			sub = sub + 1;
     		end
     	end
 		if(buffer < sub) begin
 			sub = sub - 1;
 		end
     	buffer = buffer - sub;
     	ones = sub;
     end
end

endmodule