data/full_repos/permissive/51595169/VerilogSource/ALLBUTCU/RegisterFile.v
1: b"%Error: data/full_repos/permissive/51595169/VerilogSource/ALLBUTCU/RegisterFile.v:8: Cannot find file containing module: 'Decoder4x16'\nDecoder4x16 DRd(.IN(RSLCT[15:12]),.OUT(DecoderRd));  \n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/51595169/VerilogSource/ALLBUTCU,data/full_repos/permissive/51595169/Decoder4x16\n             data/full_repos/permissive/51595169/VerilogSource/ALLBUTCU,data/full_repos/permissive/51595169/Decoder4x16.v\n             data/full_repos/permissive/51595169/VerilogSource/ALLBUTCU,data/full_repos/permissive/51595169/Decoder4x16.sv\n             Decoder4x16\n             Decoder4x16.v\n             Decoder4x16.sv\n             obj_dir/Decoder4x16\n             obj_dir/Decoder4x16.v\n             obj_dir/Decoder4x16.sv\n%Error: data/full_repos/permissive/51595169/VerilogSource/ALLBUTCU/RegisterFile.v:13: Cannot find file containing module: 'Multiplexer'\nMultiplexer mux(RSLCT[19:16],RSLCT[3:0],IR_CU,_RN_CU);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/ALLBUTCU/RegisterFile.v:16: Cannot find file containing module: 'Decoder4x16'\nDecoder4x16 DRn_CU(.IN(_RN_CU),.OUT(DecoderRn_CU)); \n^~~~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/ALLBUTCU/RegisterFile.v:21: Cannot find file containing module: 'Decoder4x16'\nDecoder4x16 DRm(.IN(RSLCT[7:4]),.OUT(DecoderRm)); \n^~~~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/ALLBUTCU/RegisterFile.v:26: Cannot find file containing module: 'Decoder4x16'\nDecoder4x16 DRs(.IN(RSLCT[11:8]),.OUT(DecoderRs)); \n^~~~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/ALLBUTCU/RegisterFile.v:29: Cannot find file containing module: 'Buffer32_32'\nBuffer32_32 pcbufffer1(.IN(Pcin),.Store(LOADPC&!(DecoderRd[15]&LOAD)),.OUT(_pcin));\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/ALLBUTCU/RegisterFile.v:30: Cannot find file containing module: 'Buffer32_32'\nBuffer32_32 pcbufffer2(.IN(in),.Store((DecoderRd[15]&LOAD)),.OUT(_pcin));\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/ALLBUTCU/RegisterFile.v:38: Cannot find file containing module: 'Register'\n  Register test_reg(.IN(in),\n  ^~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/ALLBUTCU/RegisterFile.v:46: Cannot find file containing module: 'Register'\n   Register test_reg(.IN(_pcin),\n   ^~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/ALLBUTCU/RegisterFile.v:55: Cannot find file containing module: 'Buffer32_32'\n Buffer32_32 bufffer(.IN(Q[i]),.Store(DecoderRn_CU[i]),.OUT(Rn));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/ALLBUTCU/RegisterFile.v:59: Cannot find file containing module: 'Buffer32_32'\n Buffer32_32 bufffer2(.IN(Q[i]),.Store(DecoderRm[i]),.OUT(Rm));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/ALLBUTCU/RegisterFile.v:63: Cannot find file containing module: 'Buffer32_32'\n Buffer32_32 bufffer3(.IN(Q[i]),.Store(DecoderRs[i]),.OUT(Rs));\n ^~~~~~~~~~~\n%Error: Exiting due to 12 error(s)\n"
module RegisterFile(input [31:0] in,Pcin,input [19:0] RSLCT,input Clk, RESET, LOADPC, LOAD,IR_CU, output [31:0] Rn,Rm,Rs,PCout);

wire [31:0] Q[15:0];


wire [15:0] DecoderRd;

Decoder4x16 DRd(.IN(RSLCT[15:12]),.OUT(DecoderRd));


wire [3:0] _RN_CU; 

Multiplexer mux(RSLCT[19:16],RSLCT[3:0],IR_CU,_RN_CU);
wire [15:0] DecoderRn_CU;

Decoder4x16 DRn_CU(.IN(_RN_CU),.OUT(DecoderRn_CU));


wire [15:0] DecoderRm;

Decoder4x16 DRm(.IN(RSLCT[7:4]),.OUT(DecoderRm));


wire [15:0] DecoderRs;

Decoder4x16 DRs(.IN(RSLCT[11:8]),.OUT(DecoderRs));

wire [31:0] _pcin;
Buffer32_32 pcbufffer1(.IN(Pcin),.Store(LOADPC&!(DecoderRd[15]&LOAD)),.OUT(_pcin));
Buffer32_32 pcbufffer2(.IN(in),.Store((DecoderRd[15]&LOAD)),.OUT(_pcin));
			

generate
  genvar i;
  for (i=0; i<=15; i=i+1) begin : registers
	if(i<15)

		Register test_reg(.IN(in),
					  .Clk(Clk),
					  .Reset(RESET),
					  .Load(DecoderRd[i]&LOAD),
					  .OUT(Q[i]));
	else
		begin

			Register test_reg(.IN(_pcin),
						  .Clk(Clk),
						  .Reset(RESET),
						  .Load((DecoderRd[i]&LOAD)||LOADPC),
						  .OUT(Q[i]));
		end
  end
  for (i=0; i<=15; i=i+1) begin : buffers

	Buffer32_32 bufffer(.IN(Q[i]),.Store(DecoderRn_CU[i]),.OUT(Rn));
  end
  for (i=0; i<=15; i=i+1) begin : buffers2

	Buffer32_32 bufffer2(.IN(Q[i]),.Store(DecoderRm[i]),.OUT(Rm));
  end
  for (i=0; i<=15; i=i+1) begin : buffers3

	Buffer32_32 bufffer3(.IN(Q[i]),.Store(DecoderRs[i]),.OUT(Rs));
  end
endgenerate

endmodule
module RegisterFile(input [31:0] in,Pcin,input [19:0] RSLCT,input Clk, RESET, LOADPC, LOAD,IR_CU, output [31:0] Rn,Rm,Rs,PCout);


wire [31:0] Q[15:0];


wire [15:0] DecoderRd;

Decoder4x16 DRd(.IN(RSLCT[15:12]),.OUT(DecoderRd));


wire [3:0] _RN_CU; 

Multiplexer mux(RSLCT[19:16],RSLCT[3:0],IR_CU,_RN_CU);
wire [15:0] DecoderRn_CU;

Decoder4x16 DRn_CU(.IN(_RN_CU),.OUT(DecoderRn_CU));


wire [15:0] DecoderRm;

Decoder4x16 DRm(.IN(RSLCT[7:4]),.OUT(DecoderRm));


wire [15:0] DecoderRs;

Decoder4x16 DRs(.IN(RSLCT[11:8]),.OUT(DecoderRs));

wire [31:0] _pcin;
Buffer32_32 pcbufffer1(.IN(Pcin),.Store(LOADPC&!(DecoderRd[15]&LOAD)),.OUT(_pcin));
Buffer32_32 pcbufffer2(.IN(in),.Store((DecoderRd[15]&LOAD)),.OUT(_pcin));
			

generate
  genvar i;
  for (i=0; i<=15; i=i+1) begin : registers
	if(i<15)

		Register test_reg(.IN(in),
					  .Clk(Clk),
					  .Reset(RESET),
					  .Load(DecoderRd[i]&LOAD),
					  .OUT(Q[i]));
	else
		begin

			Register test_reg(.IN(_pcin),
						  .Clk(Clk),
						  .Reset(RESET),
						  .Load((DecoderRd[i]&LOAD)||LOADPC),
						  .OUT(Q[i]));
		end
  end
  for (i=0; i<=15; i=i+1) begin : buffers

	Buffer32_32 bufffer(.IN(Q[i]),.Store(DecoderRn_CU[i]),.OUT(Rn));
  end
  for (i=0; i<=15; i=i+1) begin : buffers2

	Buffer32_32 bufffer2(.IN(Q[i]),.Store(DecoderRm[i]),.OUT(Rm));
  end
  for (i=0; i<=15; i=i+1) begin : buffers3

	Buffer32_32 bufffer3(.IN(Q[i]),.Store(DecoderRs[i]),.OUT(Rs));
  end
endgenerate

endmodule