data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_top.v
1: b'%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_top.v:28: Cannot find include file: or1k_defines.v\n`include "or1k_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog,data/full_repos/permissive/447681894/or1k_defines.v\n             data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog,data/full_repos/permissive/447681894/or1k_defines.v.v\n             data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog,data/full_repos/permissive/447681894/or1k_defines.v.sv\n             or1k_defines.v\n             or1k_defines.v.v\n             or1k_defines.v.sv\n             obj_dir/or1k_defines.v\n             obj_dir/or1k_defines.v.v\n             obj_dir/or1k_defines.v.sv\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_top.v:78: Define or directive not defined: \'`OR1K_RESET_VECTOR\'\n                                          `OR1K_RESET_VECTOR,8\'d0},\n                                          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_top.v:78: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                                          `OR1K_RESET_VECTOR,8\'d0},\n                                                            ^\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_top.v:81: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter FEATURE_CSYNC              = "NONE",\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_top.v:83: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter FEATURE_MULTICORE          = "NONE",\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_top.v:84: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter OPTION_RF_NUM_SHADOW_GPR   = 0        \n  ^~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_top.v:85: syntax error, unexpected \')\', expecting \';\'\n)\n^\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_top.v:184: syntax error, unexpected IDENTIFIER\n  or1k_marocchino_bus_if_wb32\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_top.v:204: Define or directive not defined: \'`OR1K_INSN_WIDTH\'\n    .cpu_dat_o        (ibus2cpu_dat[`OR1K_INSN_WIDTH-1:0]),  \n                                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_top.v:356: Define or directive not defined: \'`OR1K_INSN_WIDTH\'\n    .ibus_dat_i               (ibus2cpu_dat[`OR1K_INSN_WIDTH-1:0]),  \n                                            ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 10 error(s)\n'
module or1k_marocchino_top
#(
  parameter OPTION_OPERAND_WIDTH        = 32,


  parameter OPTION_DCACHE_BLOCK_WIDTH   =  5,
  parameter OPTION_DCACHE_SET_WIDTH     =  8,
  parameter OPTION_DCACHE_WAYS          =  2,
  parameter OPTION_DCACHE_LIMIT_WIDTH   = 32,
  parameter OPTION_DCACHE_SNOOP         = "NONE",
  parameter OPTION_DCACHE_CLEAR_ON_INIT =  0,


  parameter FEATURE_DMMU_HW_TLB_RELOAD  = "NONE",
  parameter OPTION_DMMU_SET_WIDTH       =  6,
  parameter OPTION_DMMU_WAYS            =  1,
  parameter OPTION_DMMU_CLEAR_ON_INIT   =  0,


  parameter OPTION_STORE_BUFFER_DEPTH_WIDTH   = 4,
  parameter OPTION_STORE_BUFFER_CLEAR_ON_INIT = 0,


  parameter OPTION_ICACHE_BLOCK_WIDTH   =  5,
  parameter OPTION_ICACHE_SET_WIDTH     =  8,
  parameter OPTION_ICACHE_WAYS          =  2,
  parameter OPTION_ICACHE_LIMIT_WIDTH   = 32,
  parameter OPTION_ICACHE_CLEAR_ON_INIT =  0,


  parameter FEATURE_IMMU_HW_TLB_RELOAD = "NONE",
  parameter OPTION_IMMU_SET_WIDTH      =  6,
  parameter OPTION_IMMU_WAYS           =  1,
  parameter OPTION_IMMU_CLEAR_ON_INIT  =  0,


  parameter FEATURE_DEBUGUNIT          = "NONE",
  parameter FEATURE_PERFCOUNTERS       = "NONE",


  parameter OPTION_PIC_TRIGGER         = "LEVEL",
  parameter OPTION_PIC_NMI_WIDTH       =  0,

  parameter OPTION_RF_CLEAR_ON_INIT    =  0,
  parameter OPTION_RF_ADDR_WIDTH       =  5,
  parameter OPTION_RF_WORDS            = 32,

  parameter OPTION_RESET_PC            = {{(OPTION_OPERAND_WIDTH-13){1'b0}},
                                          `OR1K_RESET_VECTOR,8'd0},

  parameter FEATURE_PSYNC              = "NONE",
  parameter FEATURE_CSYNC              = "NONE",

  parameter FEATURE_MULTICORE          = "NONE",
  parameter OPTION_RF_NUM_SHADOW_GPR   = 0
)
(

  input                             wb_clk,
  input                             wb_rst,


  input                             cpu_clk,
  input                             cpu_rst,


  output [31:0]                     iwbm_adr_o,
  output                            iwbm_stb_o,
  output                            iwbm_cyc_o,
  output [3:0]                      iwbm_sel_o,
  output                            iwbm_we_o,
  output [2:0]                      iwbm_cti_o,
  output [1:0]                      iwbm_bte_o,
  output [31:0]                     iwbm_dat_o,
  input                             iwbm_err_i,
  input                             iwbm_ack_i,
  input [31:0]                      iwbm_dat_i,
  input                             iwbm_rty_i,


  output [31:0]                     dwbm_adr_o,
  output                            dwbm_stb_o,
  output                            dwbm_cyc_o,
  output [3:0]                      dwbm_sel_o,
  output                            dwbm_we_o,
  output [2:0]                      dwbm_cti_o,
  output [1:0]                      dwbm_bte_o,
  output [31:0]                     dwbm_dat_o,
  input                             dwbm_err_i,
  input                             dwbm_ack_i,
  input [31:0]                      dwbm_dat_i,
  input                             dwbm_rty_i,


  input [31:0]                      irq_i,


  input [15:0]                      du_addr_i,
  input                             du_stb_i,
  input [OPTION_OPERAND_WIDTH-1:0]  du_dat_i,
  input                             du_we_i,
  output [OPTION_OPERAND_WIDTH-1:0] du_dat_o,
  output                            du_ack_o,

  input                             du_stall_i,
  output                            du_stall_o,


  input [OPTION_OPERAND_WIDTH-1:0]  multicore_coreid_i,

  input [OPTION_OPERAND_WIDTH-1:0]  multicore_numcores_i,

  input [31:0]                     snoop_adr_i,
  input                            snoop_en_i
);


  wire [OPTION_OPERAND_WIDTH-1:0] cpu2dbus_adr;
  wire [3:0]                      cpu2dbus_bsel;
  wire                            cpu2dbus_burst;
  wire [OPTION_OPERAND_WIDTH-1:0] cpu2dbus_dat;
  wire                            cpu2dbus_req;
  wire                            cpu2dbus_lwa_cmd;
  wire                            cpu2dbus_stna_cmd;
  wire                            cpu2dbus_swa_cmd;
  wire                            dbus2cpu_err;
  wire                            dbus2cpu_ack;
  wire [OPTION_OPERAND_WIDTH-1:0] dbus2cpu_dat;
  wire                            dbus2cpu_burst_last;

  wire                            pipeline_flush;
  wire                            dbus2cpu_atomic_flg;

  wire [OPTION_OPERAND_WIDTH-1:0] dbus2cpu_snoop_adr;
  wire                            dbus2cpu_snoop_en;



  wire [OPTION_OPERAND_WIDTH-1:0] cpu2ibus_adr;
  wire                            cpu2ibus_burst;
  wire                            cpu2ibus_req;
  wire                            ibus2cpu_err;
  wire                            ibus2cpu_ack;
  wire [OPTION_OPERAND_WIDTH-1:0] ibus2cpu_dat;
  wire                            ibus2cpu_burst_last;


  wire [15:0]                     spr_bus_addr_o;
  wire [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_o;
  wire                            spr_bus_stb_o;
  wire                            spr_bus_we_o;



  or1k_marocchino_bus_if_wb32
  #(
    .DRIVER_TYPE          ("I_CACHE"),
    .BURST_LENGTH         ((OPTION_ICACHE_BLOCK_WIDTH == 4) ? 4 :
                           (OPTION_ICACHE_BLOCK_WIDTH == 5) ? 8 : 1),
    .OPTION_DCACHE_SNOOP  ("NONE")
  )
  ibus_bridge
  (

    .wb_clk           (wb_clk),
    .wb_rst           (wb_rst),

    .cpu_clk          (cpu_clk),
    .cpu_rst          (cpu_rst),

    .pipeline_flush_i (1'b0),

    .cpu_err_o        (ibus2cpu_err),
    .cpu_ack_o        (ibus2cpu_ack),
    .cpu_dat_o        (ibus2cpu_dat[`OR1K_INSN_WIDTH-1:0]),
    .cpu_burst_last_o (ibus2cpu_burst_last),
    .cpu_adr_i        (cpu2ibus_adr),
    .cpu_dat_i        ({OPTION_OPERAND_WIDTH{1'b0}}),
    .cpu_req_i        (cpu2ibus_req),
    .cpu_bsel_i       (4'b1111),
    .cpu_lwa_cmd_i    (1'b0),
    .cpu_stna_cmd_i   (1'b0),
    .cpu_swa_cmd_i    (1'b0),
    .cpu_burst_i      (cpu2ibus_burst),

    .cpu_atomic_flg_o (),

    .cpu_snoop_adr_o  (),
    .cpu_snoop_en_o   (),

    .wbm_adr_o        (iwbm_adr_o),
    .wbm_stb_o        (iwbm_stb_o),
    .wbm_cyc_o        (iwbm_cyc_o),
    .wbm_sel_o        (iwbm_sel_o),
    .wbm_we_o         (iwbm_we_o),
    .wbm_cti_o        (iwbm_cti_o),
    .wbm_bte_o        (iwbm_bte_o),
    .wbm_dat_o        (iwbm_dat_o),
    .wbm_err_i        (iwbm_err_i),
    .wbm_ack_i        (iwbm_ack_i),
    .wbm_dat_i        (iwbm_dat_i),
    .wbm_rty_i        (iwbm_rty_i),

    .snoop_adr_i      (32'd0),
    .snoop_en_i       (1'b0)
  );


  or1k_marocchino_bus_if_wb32
  #(
    .DRIVER_TYPE          ("D_CACHE"),
    .BURST_LENGTH         ((OPTION_DCACHE_BLOCK_WIDTH == 4) ? 4 :
                           (OPTION_DCACHE_BLOCK_WIDTH == 5) ? 8 : 1),
    .OPTION_DCACHE_SNOOP  (OPTION_DCACHE_SNOOP)
  )
  dbus_bridge
  (

    .wb_clk           (wb_clk),
    .wb_rst           (wb_rst),

    .cpu_clk          (cpu_clk),
    .cpu_rst          (cpu_rst),

    .pipeline_flush_i (pipeline_flush),

    .cpu_err_o        (dbus2cpu_err),
    .cpu_ack_o        (dbus2cpu_ack),
    .cpu_dat_o        (dbus2cpu_dat),
    .cpu_burst_last_o (dbus2cpu_burst_last),
    .cpu_adr_i        (cpu2dbus_adr),
    .cpu_dat_i        (cpu2dbus_dat),
    .cpu_req_i        (cpu2dbus_req),
    .cpu_bsel_i       (cpu2dbus_bsel),
    .cpu_lwa_cmd_i    (cpu2dbus_lwa_cmd),
    .cpu_stna_cmd_i   (cpu2dbus_stna_cmd),
    .cpu_swa_cmd_i    (cpu2dbus_swa_cmd),
    .cpu_burst_i      (cpu2dbus_burst),

    .cpu_atomic_flg_o (dbus2cpu_atomic_flg),

    .cpu_snoop_adr_o  (dbus2cpu_snoop_adr),
    .cpu_snoop_en_o   (dbus2cpu_snoop_en),

    .wbm_adr_o        (dwbm_adr_o),
    .wbm_stb_o        (dwbm_stb_o),
    .wbm_cyc_o        (dwbm_cyc_o),
    .wbm_sel_o        (dwbm_sel_o),
    .wbm_we_o         (dwbm_we_o),
    .wbm_cti_o        (dwbm_cti_o),
    .wbm_bte_o        (dwbm_bte_o),
    .wbm_dat_o        (dwbm_dat_o),
    .wbm_err_i        (dwbm_err_i),
    .wbm_ack_i        (dwbm_ack_i),
    .wbm_dat_i        (dwbm_dat_i),
    .wbm_rty_i        (dwbm_rty_i),

    .snoop_adr_i      (snoop_adr_i),
    .snoop_en_i       (snoop_en_i)
  );


  or1k_marocchino_cpu
  #(
    .OPTION_OPERAND_WIDTH             (OPTION_OPERAND_WIDTH),

    .OPTION_DCACHE_BLOCK_WIDTH        (OPTION_DCACHE_BLOCK_WIDTH),
    .OPTION_DCACHE_SET_WIDTH          (OPTION_DCACHE_SET_WIDTH),
    .OPTION_DCACHE_WAYS               (OPTION_DCACHE_WAYS),
    .OPTION_DCACHE_LIMIT_WIDTH        (OPTION_DCACHE_LIMIT_WIDTH),
    .OPTION_DCACHE_SNOOP              (OPTION_DCACHE_SNOOP),
    .OPTION_DCACHE_CLEAR_ON_INIT      (OPTION_DCACHE_CLEAR_ON_INIT),

    .FEATURE_DMMU_HW_TLB_RELOAD       (FEATURE_DMMU_HW_TLB_RELOAD),
    .OPTION_DMMU_SET_WIDTH            (OPTION_DMMU_SET_WIDTH),
    .OPTION_DMMU_WAYS                 (OPTION_DMMU_WAYS),
    .OPTION_DMMU_CLEAR_ON_INIT        (OPTION_DMMU_CLEAR_ON_INIT),

    .OPTION_STORE_BUFFER_DEPTH_WIDTH    (OPTION_STORE_BUFFER_DEPTH_WIDTH),
    .OPTION_STORE_BUFFER_CLEAR_ON_INIT  (OPTION_STORE_BUFFER_CLEAR_ON_INIT),

    .OPTION_ICACHE_BLOCK_WIDTH        (OPTION_ICACHE_BLOCK_WIDTH),
    .OPTION_ICACHE_SET_WIDTH          (OPTION_ICACHE_SET_WIDTH),
    .OPTION_ICACHE_WAYS               (OPTION_ICACHE_WAYS),
    .OPTION_ICACHE_LIMIT_WIDTH        (OPTION_ICACHE_LIMIT_WIDTH),
    .OPTION_ICACHE_CLEAR_ON_INIT      (OPTION_ICACHE_CLEAR_ON_INIT),

    .FEATURE_IMMU_HW_TLB_RELOAD       (FEATURE_IMMU_HW_TLB_RELOAD),
    .OPTION_IMMU_SET_WIDTH            (OPTION_IMMU_SET_WIDTH),
    .OPTION_IMMU_WAYS                 (OPTION_IMMU_WAYS),
    .OPTION_IMMU_CLEAR_ON_INIT        (OPTION_IMMU_CLEAR_ON_INIT),

    .OPTION_PIC_TRIGGER               (OPTION_PIC_TRIGGER),
    .OPTION_PIC_NMI_WIDTH             (OPTION_PIC_NMI_WIDTH),

    .FEATURE_DEBUGUNIT                (FEATURE_DEBUGUNIT),
    .FEATURE_PERFCOUNTERS             (FEATURE_PERFCOUNTERS),

    .FEATURE_MULTICORE                (FEATURE_MULTICORE),
    .OPTION_RF_NUM_SHADOW_GPR         (OPTION_RF_NUM_SHADOW_GPR),

    .OPTION_RF_CLEAR_ON_INIT          (OPTION_RF_CLEAR_ON_INIT),
    .OPTION_RF_ADDR_WIDTH             (OPTION_RF_ADDR_WIDTH),


    .OPTION_RESET_PC                  (OPTION_RESET_PC),

    .FEATURE_PSYNC                    (FEATURE_PSYNC),
    .FEATURE_CSYNC                    (FEATURE_CSYNC)
  )
  u_cpu
  (

    .wb_clk                   (wb_clk),
    .wb_rst                   (wb_rst),

    .cpu_clk                  (cpu_clk),
    .cpu_rst                  (cpu_rst),

    .pipeline_flush_o         (pipeline_flush),

    .ibus_adr_o               (cpu2ibus_adr),
    .ibus_req_o               (cpu2ibus_req),
    .ibus_burst_o             (cpu2ibus_burst),
    .ibus_err_i               (ibus2cpu_err),
    .ibus_ack_i               (ibus2cpu_ack),
    .ibus_dat_i               (ibus2cpu_dat[`OR1K_INSN_WIDTH-1:0]),
    .ibus_burst_last_i        (ibus2cpu_burst_last),

    .dbus_adr_o               (cpu2dbus_adr),
    .dbus_dat_o               (cpu2dbus_dat),
    .dbus_req_o               (cpu2dbus_req),
    .dbus_bsel_o              (cpu2dbus_bsel),
    .dbus_lwa_cmd_o           (cpu2dbus_lwa_cmd),
    .dbus_stna_cmd_o          (cpu2dbus_stna_cmd),
    .dbus_swa_cmd_o           (cpu2dbus_swa_cmd),
    .dbus_burst_o             (cpu2dbus_burst),
    .dbus_err_i               (dbus2cpu_err),
    .dbus_ack_i               (dbus2cpu_ack),
    .dbus_dat_i               (dbus2cpu_dat),
    .dbus_burst_last_i        (dbus2cpu_burst_last),

    .dbus_atomic_flg_i        (dbus2cpu_atomic_flg),

    .irq_i                    (irq_i[31:0]),

    .du_dat_o                 (du_dat_o),
    .du_ack_o                 (du_ack_o),
    .du_addr_i                (du_addr_i),
    .du_stb_i                 (du_stb_i),
    .du_dat_i                 (du_dat_i),
    .du_we_i                  (du_we_i),

    .du_stall_i               (du_stall_i),
    .du_stall_o               (du_stall_o),

    .spr_bus_addr_o           (spr_bus_addr_o[15:0]),
    .spr_bus_we_o             (spr_bus_we_o),
    .spr_bus_stb_o            (spr_bus_stb_o),
    .spr_bus_dat_o            (spr_bus_dat_o),

    .multicore_coreid_i       (multicore_coreid_i),
    .multicore_numcores_i     (multicore_numcores_i),
    .snoop_adr_i              (dbus2cpu_snoop_adr),
    .snoop_en_i               (dbus2cpu_snoop_en)
  );

endmodule
module or1k_marocchino_top
#(
  parameter OPTION_OPERAND_WIDTH        = 32,


  parameter OPTION_DCACHE_BLOCK_WIDTH   =  5,
  parameter OPTION_DCACHE_SET_WIDTH     =  8,
  parameter OPTION_DCACHE_WAYS          =  2,
  parameter OPTION_DCACHE_LIMIT_WIDTH   = 32,
  parameter OPTION_DCACHE_SNOOP         = "NONE",
  parameter OPTION_DCACHE_CLEAR_ON_INIT =  0,


  parameter FEATURE_DMMU_HW_TLB_RELOAD  = "NONE",
  parameter OPTION_DMMU_SET_WIDTH       =  6,
  parameter OPTION_DMMU_WAYS            =  1,
  parameter OPTION_DMMU_CLEAR_ON_INIT   =  0,


  parameter OPTION_STORE_BUFFER_DEPTH_WIDTH   = 4,
  parameter OPTION_STORE_BUFFER_CLEAR_ON_INIT = 0,


  parameter OPTION_ICACHE_BLOCK_WIDTH   =  5,
  parameter OPTION_ICACHE_SET_WIDTH     =  8,
  parameter OPTION_ICACHE_WAYS          =  2,
  parameter OPTION_ICACHE_LIMIT_WIDTH   = 32,
  parameter OPTION_ICACHE_CLEAR_ON_INIT =  0,


  parameter FEATURE_IMMU_HW_TLB_RELOAD = "NONE",
  parameter OPTION_IMMU_SET_WIDTH      =  6,
  parameter OPTION_IMMU_WAYS           =  1,
  parameter OPTION_IMMU_CLEAR_ON_INIT  =  0,


  parameter FEATURE_DEBUGUNIT          = "NONE",
  parameter FEATURE_PERFCOUNTERS       = "NONE",


  parameter OPTION_PIC_TRIGGER         = "LEVEL",
  parameter OPTION_PIC_NMI_WIDTH       =  0,

  parameter OPTION_RF_CLEAR_ON_INIT    =  0,
  parameter OPTION_RF_ADDR_WIDTH       =  5,
  parameter OPTION_RF_WORDS            = 32,

  parameter OPTION_RESET_PC            = {{(OPTION_OPERAND_WIDTH-13){1'b0}},
                                          `OR1K_RESET_VECTOR,8'd0},

  parameter FEATURE_PSYNC              = "NONE",
  parameter FEATURE_CSYNC              = "NONE",

  parameter FEATURE_MULTICORE          = "NONE",
  parameter OPTION_RF_NUM_SHADOW_GPR   = 0
)
(

  input                             wb_clk,
  input                             wb_rst,


  input                             cpu_clk,
  input                             cpu_rst,


  output [31:0]                     iwbm_adr_o,
  output                            iwbm_stb_o,
  output                            iwbm_cyc_o,
  output [3:0]                      iwbm_sel_o,
  output                            iwbm_we_o,
  output [2:0]                      iwbm_cti_o,
  output [1:0]                      iwbm_bte_o,
  output [31:0]                     iwbm_dat_o,
  input                             iwbm_err_i,
  input                             iwbm_ack_i,
  input [31:0]                      iwbm_dat_i,
  input                             iwbm_rty_i,


  output [31:0]                     dwbm_adr_o,
  output                            dwbm_stb_o,
  output                            dwbm_cyc_o,
  output [3:0]                      dwbm_sel_o,
  output                            dwbm_we_o,
  output [2:0]                      dwbm_cti_o,
  output [1:0]                      dwbm_bte_o,
  output [31:0]                     dwbm_dat_o,
  input                             dwbm_err_i,
  input                             dwbm_ack_i,
  input [31:0]                      dwbm_dat_i,
  input                             dwbm_rty_i,


  input [31:0]                      irq_i,


  input [15:0]                      du_addr_i,
  input                             du_stb_i,
  input [OPTION_OPERAND_WIDTH-1:0]  du_dat_i,
  input                             du_we_i,
  output [OPTION_OPERAND_WIDTH-1:0] du_dat_o,
  output                            du_ack_o,

  input                             du_stall_i,
  output                            du_stall_o,


  input [OPTION_OPERAND_WIDTH-1:0]  multicore_coreid_i,

  input [OPTION_OPERAND_WIDTH-1:0]  multicore_numcores_i,

  input [31:0]                     snoop_adr_i,
  input                            snoop_en_i
);



  wire [OPTION_OPERAND_WIDTH-1:0] cpu2dbus_adr;
  wire [3:0]                      cpu2dbus_bsel;
  wire                            cpu2dbus_burst;
  wire [OPTION_OPERAND_WIDTH-1:0] cpu2dbus_dat;
  wire                            cpu2dbus_req;
  wire                            cpu2dbus_lwa_cmd;
  wire                            cpu2dbus_stna_cmd;
  wire                            cpu2dbus_swa_cmd;
  wire                            dbus2cpu_err;
  wire                            dbus2cpu_ack;
  wire [OPTION_OPERAND_WIDTH-1:0] dbus2cpu_dat;
  wire                            dbus2cpu_burst_last;

  wire                            pipeline_flush;
  wire                            dbus2cpu_atomic_flg;

  wire [OPTION_OPERAND_WIDTH-1:0] dbus2cpu_snoop_adr;
  wire                            dbus2cpu_snoop_en;



  wire [OPTION_OPERAND_WIDTH-1:0] cpu2ibus_adr;
  wire                            cpu2ibus_burst;
  wire                            cpu2ibus_req;
  wire                            ibus2cpu_err;
  wire                            ibus2cpu_ack;
  wire [OPTION_OPERAND_WIDTH-1:0] ibus2cpu_dat;
  wire                            ibus2cpu_burst_last;


  wire [15:0]                     spr_bus_addr_o;
  wire [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_o;
  wire                            spr_bus_stb_o;
  wire                            spr_bus_we_o;



  or1k_marocchino_bus_if_wb32
  #(
    .DRIVER_TYPE          ("I_CACHE"),
    .BURST_LENGTH         ((OPTION_ICACHE_BLOCK_WIDTH == 4) ? 4 :
                           (OPTION_ICACHE_BLOCK_WIDTH == 5) ? 8 : 1),
    .OPTION_DCACHE_SNOOP  ("NONE")
  )
  ibus_bridge
  (

    .wb_clk           (wb_clk),
    .wb_rst           (wb_rst),

    .cpu_clk          (cpu_clk),
    .cpu_rst          (cpu_rst),

    .pipeline_flush_i (1'b0),

    .cpu_err_o        (ibus2cpu_err),
    .cpu_ack_o        (ibus2cpu_ack),
    .cpu_dat_o        (ibus2cpu_dat[`OR1K_INSN_WIDTH-1:0]),
    .cpu_burst_last_o (ibus2cpu_burst_last),
    .cpu_adr_i        (cpu2ibus_adr),
    .cpu_dat_i        ({OPTION_OPERAND_WIDTH{1'b0}}),
    .cpu_req_i        (cpu2ibus_req),
    .cpu_bsel_i       (4'b1111),
    .cpu_lwa_cmd_i    (1'b0),
    .cpu_stna_cmd_i   (1'b0),
    .cpu_swa_cmd_i    (1'b0),
    .cpu_burst_i      (cpu2ibus_burst),

    .cpu_atomic_flg_o (),

    .cpu_snoop_adr_o  (),
    .cpu_snoop_en_o   (),

    .wbm_adr_o        (iwbm_adr_o),
    .wbm_stb_o        (iwbm_stb_o),
    .wbm_cyc_o        (iwbm_cyc_o),
    .wbm_sel_o        (iwbm_sel_o),
    .wbm_we_o         (iwbm_we_o),
    .wbm_cti_o        (iwbm_cti_o),
    .wbm_bte_o        (iwbm_bte_o),
    .wbm_dat_o        (iwbm_dat_o),
    .wbm_err_i        (iwbm_err_i),
    .wbm_ack_i        (iwbm_ack_i),
    .wbm_dat_i        (iwbm_dat_i),
    .wbm_rty_i        (iwbm_rty_i),

    .snoop_adr_i      (32'd0),
    .snoop_en_i       (1'b0)
  );


  or1k_marocchino_bus_if_wb32
  #(
    .DRIVER_TYPE          ("D_CACHE"),
    .BURST_LENGTH         ((OPTION_DCACHE_BLOCK_WIDTH == 4) ? 4 :
                           (OPTION_DCACHE_BLOCK_WIDTH == 5) ? 8 : 1),
    .OPTION_DCACHE_SNOOP  (OPTION_DCACHE_SNOOP)
  )
  dbus_bridge
  (

    .wb_clk           (wb_clk),
    .wb_rst           (wb_rst),

    .cpu_clk          (cpu_clk),
    .cpu_rst          (cpu_rst),

    .pipeline_flush_i (pipeline_flush),

    .cpu_err_o        (dbus2cpu_err),
    .cpu_ack_o        (dbus2cpu_ack),
    .cpu_dat_o        (dbus2cpu_dat),
    .cpu_burst_last_o (dbus2cpu_burst_last),
    .cpu_adr_i        (cpu2dbus_adr),
    .cpu_dat_i        (cpu2dbus_dat),
    .cpu_req_i        (cpu2dbus_req),
    .cpu_bsel_i       (cpu2dbus_bsel),
    .cpu_lwa_cmd_i    (cpu2dbus_lwa_cmd),
    .cpu_stna_cmd_i   (cpu2dbus_stna_cmd),
    .cpu_swa_cmd_i    (cpu2dbus_swa_cmd),
    .cpu_burst_i      (cpu2dbus_burst),

    .cpu_atomic_flg_o (dbus2cpu_atomic_flg),

    .cpu_snoop_adr_o  (dbus2cpu_snoop_adr),
    .cpu_snoop_en_o   (dbus2cpu_snoop_en),

    .wbm_adr_o        (dwbm_adr_o),
    .wbm_stb_o        (dwbm_stb_o),
    .wbm_cyc_o        (dwbm_cyc_o),
    .wbm_sel_o        (dwbm_sel_o),
    .wbm_we_o         (dwbm_we_o),
    .wbm_cti_o        (dwbm_cti_o),
    .wbm_bte_o        (dwbm_bte_o),
    .wbm_dat_o        (dwbm_dat_o),
    .wbm_err_i        (dwbm_err_i),
    .wbm_ack_i        (dwbm_ack_i),
    .wbm_dat_i        (dwbm_dat_i),
    .wbm_rty_i        (dwbm_rty_i),

    .snoop_adr_i      (snoop_adr_i),
    .snoop_en_i       (snoop_en_i)
  );


  or1k_marocchino_cpu
  #(
    .OPTION_OPERAND_WIDTH             (OPTION_OPERAND_WIDTH),

    .OPTION_DCACHE_BLOCK_WIDTH        (OPTION_DCACHE_BLOCK_WIDTH),
    .OPTION_DCACHE_SET_WIDTH          (OPTION_DCACHE_SET_WIDTH),
    .OPTION_DCACHE_WAYS               (OPTION_DCACHE_WAYS),
    .OPTION_DCACHE_LIMIT_WIDTH        (OPTION_DCACHE_LIMIT_WIDTH),
    .OPTION_DCACHE_SNOOP              (OPTION_DCACHE_SNOOP),
    .OPTION_DCACHE_CLEAR_ON_INIT      (OPTION_DCACHE_CLEAR_ON_INIT),

    .FEATURE_DMMU_HW_TLB_RELOAD       (FEATURE_DMMU_HW_TLB_RELOAD),
    .OPTION_DMMU_SET_WIDTH            (OPTION_DMMU_SET_WIDTH),
    .OPTION_DMMU_WAYS                 (OPTION_DMMU_WAYS),
    .OPTION_DMMU_CLEAR_ON_INIT        (OPTION_DMMU_CLEAR_ON_INIT),

    .OPTION_STORE_BUFFER_DEPTH_WIDTH    (OPTION_STORE_BUFFER_DEPTH_WIDTH),
    .OPTION_STORE_BUFFER_CLEAR_ON_INIT  (OPTION_STORE_BUFFER_CLEAR_ON_INIT),

    .OPTION_ICACHE_BLOCK_WIDTH        (OPTION_ICACHE_BLOCK_WIDTH),
    .OPTION_ICACHE_SET_WIDTH          (OPTION_ICACHE_SET_WIDTH),
    .OPTION_ICACHE_WAYS               (OPTION_ICACHE_WAYS),
    .OPTION_ICACHE_LIMIT_WIDTH        (OPTION_ICACHE_LIMIT_WIDTH),
    .OPTION_ICACHE_CLEAR_ON_INIT      (OPTION_ICACHE_CLEAR_ON_INIT),

    .FEATURE_IMMU_HW_TLB_RELOAD       (FEATURE_IMMU_HW_TLB_RELOAD),
    .OPTION_IMMU_SET_WIDTH            (OPTION_IMMU_SET_WIDTH),
    .OPTION_IMMU_WAYS                 (OPTION_IMMU_WAYS),
    .OPTION_IMMU_CLEAR_ON_INIT        (OPTION_IMMU_CLEAR_ON_INIT),

    .OPTION_PIC_TRIGGER               (OPTION_PIC_TRIGGER),
    .OPTION_PIC_NMI_WIDTH             (OPTION_PIC_NMI_WIDTH),

    .FEATURE_DEBUGUNIT                (FEATURE_DEBUGUNIT),
    .FEATURE_PERFCOUNTERS             (FEATURE_PERFCOUNTERS),

    .FEATURE_MULTICORE                (FEATURE_MULTICORE),
    .OPTION_RF_NUM_SHADOW_GPR         (OPTION_RF_NUM_SHADOW_GPR),

    .OPTION_RF_CLEAR_ON_INIT          (OPTION_RF_CLEAR_ON_INIT),
    .OPTION_RF_ADDR_WIDTH             (OPTION_RF_ADDR_WIDTH),


    .OPTION_RESET_PC                  (OPTION_RESET_PC),

    .FEATURE_PSYNC                    (FEATURE_PSYNC),
    .FEATURE_CSYNC                    (FEATURE_CSYNC)
  )
  u_cpu
  (

    .wb_clk                   (wb_clk),
    .wb_rst                   (wb_rst),

    .cpu_clk                  (cpu_clk),
    .cpu_rst                  (cpu_rst),

    .pipeline_flush_o         (pipeline_flush),

    .ibus_adr_o               (cpu2ibus_adr),
    .ibus_req_o               (cpu2ibus_req),
    .ibus_burst_o             (cpu2ibus_burst),
    .ibus_err_i               (ibus2cpu_err),
    .ibus_ack_i               (ibus2cpu_ack),
    .ibus_dat_i               (ibus2cpu_dat[`OR1K_INSN_WIDTH-1:0]),
    .ibus_burst_last_i        (ibus2cpu_burst_last),

    .dbus_adr_o               (cpu2dbus_adr),
    .dbus_dat_o               (cpu2dbus_dat),
    .dbus_req_o               (cpu2dbus_req),
    .dbus_bsel_o              (cpu2dbus_bsel),
    .dbus_lwa_cmd_o           (cpu2dbus_lwa_cmd),
    .dbus_stna_cmd_o          (cpu2dbus_stna_cmd),
    .dbus_swa_cmd_o           (cpu2dbus_swa_cmd),
    .dbus_burst_o             (cpu2dbus_burst),
    .dbus_err_i               (dbus2cpu_err),
    .dbus_ack_i               (dbus2cpu_ack),
    .dbus_dat_i               (dbus2cpu_dat),
    .dbus_burst_last_i        (dbus2cpu_burst_last),

    .dbus_atomic_flg_i        (dbus2cpu_atomic_flg),

    .irq_i                    (irq_i[31:0]),

    .du_dat_o                 (du_dat_o),
    .du_ack_o                 (du_ack_o),
    .du_addr_i                (du_addr_i),
    .du_stb_i                 (du_stb_i),
    .du_dat_i                 (du_dat_i),
    .du_we_i                  (du_we_i),

    .du_stall_i               (du_stall_i),
    .du_stall_o               (du_stall_o),

    .spr_bus_addr_o           (spr_bus_addr_o[15:0]),
    .spr_bus_we_o             (spr_bus_we_o),
    .spr_bus_stb_o            (spr_bus_stb_o),
    .spr_bus_dat_o            (spr_bus_dat_o),

    .multicore_coreid_i       (multicore_coreid_i),
    .multicore_numcores_i     (multicore_numcores_i),
    .snoop_adr_i              (dbus2cpu_snoop_adr),
    .snoop_en_i               (dbus2cpu_snoop_en)
  );

endmodule