data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/utils/spi_control_utils.vh
1: b'%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/utils/spi_control_utils.vh:27: Bit extraction of var[31:0] requires 5 bit index, not 4 bits.\n    ss_data[ss_input] = 1\'b1;\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
function automatic [31:0] set_ss_bit;
input  [3:0]  ss_input;
reg   [31:0]  ss_data;
begin
    ss_data           = 32'h0;
    ss_data[ss_input] = 1'b1;
    set_ss_bit        = ss_data;
end
endfunction
function automatic [31:0] set_ss_bit;

input  [3:0]  ss_input;
reg   [31:0]  ss_data;
begin
    ss_data           = 32'h0;
    ss_data[ss_input] = 1'b1;
    set_ss_bit        = ss_data;
end
endfunction