data/full_repos/permissive/521337848/Hardware/SPISD/spi.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/521337848/Hardware/SPISD/spi.v:141: Multiple top level modules\n                                                                                : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                : ... Top module \'spi\'\nmodule spi(\n       ^~~\n                                                                                : ... Top module \'dclkb\'\nmodule dclkb(\n       ^~~~~\n%Error: Exiting due to 1 warning(s)\n'
module dclkb(
	input clk,
	input rst,
	
	output reg dclk = 0
);

reg f_dclk = 0;

reg[1:0] f_tim = 0;
reg[1:0] n_tim = 0;
 
always@(posedge clk or posedge rst)begin
	if(rst) begin
		f_tim <= 0;
		dclk <= 0;
	end
	else begin
		f_tim <= n_tim;
		dclk <= f_dclk;
	end
end
	
always@(*)begin
	n_tim = f_tim + 1;
	f_dclk = dclk;
	
	if(f_tim == 2)begin
		f_dclk = ~dclk;
		n_tim = 0;
	end
		
end


endmodule
module dclkb(
	input clk,
	input rst,
	
	output reg dclk = 0
);


reg f_dclk = 0;

reg[1:0] f_tim = 0;
reg[1:0] n_tim = 0;
 
always@(posedge clk or posedge rst)begin
	if(rst) begin
		f_tim <= 0;
		dclk <= 0;
	end
	else begin
		f_tim <= n_tim;
		dclk <= f_dclk;
	end
end
	
always@(*)begin
	n_tim = f_tim + 1;
	f_dclk = dclk;
	
	if(f_tim == 2)begin
		f_dclk = ~dclk;
		n_tim = 0;
	end
		
end


endmodule