data/full_repos/permissive/479997390/src/Extender.v
1: b'%Error: data/full_repos/permissive/479997390/src/Extender.v:1: Cannot find include file: CtrlDef.v\n`include "CtrlDef.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/479997390/src,data/full_repos/permissive/479997390/CtrlDef.v\n             data/full_repos/permissive/479997390/src,data/full_repos/permissive/479997390/CtrlDef.v.v\n             data/full_repos/permissive/479997390/src,data/full_repos/permissive/479997390/CtrlDef.v.sv\n             CtrlDef.v\n             CtrlDef.v.v\n             CtrlDef.v.sv\n             obj_dir/CtrlDef.v\n             obj_dir/CtrlDef.v.v\n             obj_dir/CtrlDef.v.sv\n%Error: data/full_repos/permissive/479997390/src/Extender.v:19: Define or directive not defined: \'`EXT_ZERO\'\n         `EXT_ZERO:    Imm32 = ZeroExt;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Extender.v:19: syntax error, unexpected \':\', expecting endcase\n         `EXT_ZERO:    Imm32 = ZeroExt;\n                  ^\n%Error: data/full_repos/permissive/479997390/src/Extender.v:20: Define or directive not defined: \'`EXT_SIGNED\'\n         `EXT_SIGNED:  Imm32 = SignedExt;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/Extender.v:21: Define or directive not defined: \'`EXT_HIGHPOS\'\n         `EXT_HIGHPOS: Imm32 = HighPos;\n         ^~~~~~~~~~~~\n%Error: Cannot continue\n'
module Extender( Imm16, ExtOp, Imm32 );
    
   input  [15:0] Imm16;
   input  [1:0]  ExtOp;
   output reg [31:0] Imm32;
   
   wire [31:0] ZeroExt, SignedExt, HighPos;

   assign ZeroExt = {16'd0, Imm16};
   assign SignedExt = {{16{Imm16[15]}}, Imm16};
   assign HighPos = {Imm16, 16'd0};
    
   always @(*) begin
      case (ExtOp)



         `EXT_ZERO:    Imm32 = ZeroExt;
         `EXT_SIGNED:  Imm32 = SignedExt;
         `EXT_HIGHPOS: Imm32 = HighPos;
         default: ;
      endcase
   end
    
endmodule
module Extender( Imm16, ExtOp, Imm32 );

    
   input  [15:0] Imm16;
   input  [1:0]  ExtOp;
   output reg [31:0] Imm32;
   
   wire [31:0] ZeroExt, SignedExt, HighPos;

   assign ZeroExt = {16'd0, Imm16};
   assign SignedExt = {{16{Imm16[15]}}, Imm16};
   assign HighPos = {Imm16, 16'd0};
    
   always @(*) begin
      case (ExtOp)



         `EXT_ZERO:    Imm32 = ZeroExt;
         `EXT_SIGNED:  Imm32 = SignedExt;
         `EXT_HIGHPOS: Imm32 = HighPos;
         default: ;
      endcase
   end
    
endmodule