data/full_repos/permissive/435997396/fpga/boards/nexys4DDR/e-class/fpga_top.v
1: b"%Error: data/full_repos/permissive/435997396/fpga/boards/nexys4DDR/e-class/fpga_top.v:232: Cannot find file containing module: 'clk_divider'\n   clk_divider clk_div (\n   ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/435997396/fpga/boards/nexys4DDR/e-class,data/full_repos/permissive/435997396/clk_divider\n             data/full_repos/permissive/435997396/fpga/boards/nexys4DDR/e-class,data/full_repos/permissive/435997396/clk_divider.v\n             data/full_repos/permissive/435997396/fpga/boards/nexys4DDR/e-class,data/full_repos/permissive/435997396/clk_divider.sv\n             clk_divider\n             clk_divider.v\n             clk_divider.sv\n             obj_dir/clk_divider\n             obj_dir/clk_divider.v\n             obj_dir/clk_divider.sv\n%Error: data/full_repos/permissive/435997396/fpga/boards/nexys4DDR/e-class/fpga_top.v:243: Cannot find file containing module: 'mig_ddr2'\n   mig_ddr2 mig_ddr2 (\n   ^~~~~~~~\n%Error: data/full_repos/permissive/435997396/fpga/boards/nexys4DDR/e-class/fpga_top.v:327: Cannot find file containing module: 'clk_converter'\n   clk_converter clock_converter (\n   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/435997396/fpga/boards/nexys4DDR/e-class/fpga_top.v:414: Cannot find file containing module: 'mkSoc'\n   mkSoc core(\n   ^~~~~\n%Error: Exiting due to 4 error(s)\n"
module fpga_top#
  (
   parameter AXI_ID_WIDTH   = 4,
   parameter AXI_ADDR_WIDTH = 27
   )
  (


   inout [15:0]   ddr2_dq,
   inout [1:0]    ddr2_dqs_n,
   inout [1:0]    ddr2_dqs_p,

   output [12:0] ddr2_addr,
   output [2:0]  ddr2_ba,
   output        ddr2_ras_n,
   output        ddr2_cas_n,
   output        ddr2_we_n,
   output        ddr2_ck_p,
   output        ddr2_ck_n,
   output        ddr2_cke,
   
   output        ddr2_cs_n,
   
   output [1:0]  ddr2_dm,
  
   output        ddr2_odt,

  `ifndef JTAG_BSCAN2E
    input       pin_tck,
    input       pin_trst,
    input       pin_tms,
    input       pin_tdi,
    output      pin_tdo,
  `endif
    
   output        init_calib_complete,
   

   input         uart_SIN,
   output        uart_SOUT,   


   inout         i2c_sda,
   inout         i2c_scl,








   input         sys_rst,
   

   input         sys_clk
   );
    

   

   
   wire                            soc_reset;
   wire                            core_clk;
   wire                            ddr2_main;
   wire                            ddr2_ref;
   wire                            locked;
   wire                            clk;
   wire                            rst;
   wire                            mmcm_locked;
   reg                             aresetn;
   reg                             aresetn_s;
  

   wire [AXI_ID_WIDTH-1:0]           m_axi_awid;
   wire [AXI_ADDR_WIDTH-1:0]         m_axi_awaddr;
   wire [7:0]                        m_axi_awlen;
   wire [2:0]                        m_axi_awsize;
   wire [1:0]                        m_axi_awburst;
   wire [0:0]                        m_axi_awlock;
   wire [3:0]                        m_axi_awcache;
   wire [2:0]                        m_axi_awprot;
   wire                              m_axi_awvalid;
   wire                              m_axi_awready;

   wire [63:0]                      m_axi_wdata;
   wire [7:0]                       m_axi_wstrb;
   wire                              m_axi_wlast;
   wire                              m_axi_wvalid;
   wire                              m_axi_wready;

   wire                              m_axi_bready;
   wire [AXI_ID_WIDTH-1:0]           m_axi_bid;
   wire [1:0]                        m_axi_bresp;
   wire                              m_axi_bvalid;

   wire [AXI_ID_WIDTH-1:0]           m_axi_arid;
   wire [AXI_ADDR_WIDTH-1:0]         m_axi_araddr;
   wire [7:0]                        m_axi_arlen;
   wire [2:0]                        m_axi_arsize;
   wire [1:0]                        m_axi_arburst;
   wire [0:0]                        m_axi_arlock;
   wire [3:0]                        m_axi_arcache;
   wire [2:0]                        m_axi_arprot;
   wire                              m_axi_arvalid;
   wire                              m_axi_arready;

   wire                              m_axi_rready;
   wire [AXI_ID_WIDTH-1:0]           m_axi_rid;
   wire [127:0]                      m_axi_rdata;
   wire [1:0]                        m_axi_rresp;
   wire                              m_axi_rlast;
   wire                              m_axi_rvalid;


   wire [AXI_ID_WIDTH-1:0]           s_axi_awid;
   wire [AXI_ADDR_WIDTH-1:0]         s_axi_awaddr;
   wire [7:0]                        s_axi_awlen;
   wire [2:0]                        s_axi_awsize;
   wire [1:0]                        s_axi_awburst;
   wire [0:0]                        s_axi_awlock;
   wire [3:0]                        s_axi_awcache;
   wire [2:0]                        s_axi_awprot;
   wire                              s_axi_awvalid;
   wire                              s_axi_awready;

   wire [63:0]                       s_axi_wdata;
   wire [7:0]                        s_axi_wstrb;
   wire                              s_axi_wlast;
   wire                              s_axi_wvalid;
   wire                              s_axi_wready;
   
   wire                              s_axi_bready;
   wire [AXI_ID_WIDTH-1:0]           s_axi_bid;
   wire [1:0]                        s_axi_bresp;
   wire                              s_axi_bvalid;
   
   wire [AXI_ID_WIDTH-1:0]           s_axi_arid;
   wire [AXI_ADDR_WIDTH-1:0]         s_axi_araddr;
   wire [7:0]                        s_axi_arlen;
   wire [2:0]                        s_axi_arsize;
   wire [1:0]                        s_axi_arburst;
   wire [0:0]                        s_axi_arlock;
   wire [3:0]                        s_axi_arcache;
   wire [2:0]                        s_axi_arprot;
   wire                              s_axi_arvalid;
   wire                              s_axi_arready;
   
   wire                              s_axi_rready;
   wire [AXI_ID_WIDTH-1:0]           s_axi_rid;
   wire [63:0]                       s_axi_rdata;
   wire [1:0]                        s_axi_rresp;
   wire                              s_axi_rlast;
   wire                              s_axi_rvalid;
 

   

   
   

  `ifdef JTAG_BSCAN2E
    wire wire_tck_clk;
    wire wire_trst;
    wire wire_capture;
    wire wire_run_test;
    wire wire_sel;
    wire wire_shift;
    wire wire_tdi;
    wire wire_tms;
    wire wire_update;
    wire wire_tdo;

    BSCANE2 #(
      .JTAG_CHAIN(4)
    )
    bse2_inst (
      .CAPTURE(wire_capture),
      .DRCK(),
      .RESET(wire_trst),
      .RUNTEST(wire_run_test),
      .SEL(wire_sel),
      .SHIFT(wire_shift),
      .TCK(wire_tck_clk),
      .TDI(wire_tdi),
      .TMS(wire_tms),
      .UPDATE(wire_update),
      .TDO(wire_tdo)
    );
  `endif
  
   
   

   wire [31:0] temp_s_axi_awaddr, temp_s_axi_araddr;
   assign s_axi_awaddr= temp_s_axi_awaddr [AXI_ADDR_WIDTH-1:0];
   assign s_axi_araddr= temp_s_axi_araddr [AXI_ADDR_WIDTH-1:0];
   assign soc_reset = locked;



   
   clk_divider clk_div (
                       .clk_in1(sys_clk),  
                       .clk_out1(core_clk),
                       .clk_out2(ddr2_main),
                       .clk_out3(ddr2_ref),
                       .resetn(sys_rst), 
                       .locked(locked) );




   mig_ddr2 mig_ddr2 (

       .ddr2_addr                      (ddr2_addr),
       .ddr2_ba                        (ddr2_ba),
       .ddr2_cas_n                     (ddr2_cas_n),
       .ddr2_ck_n                      (ddr2_ck_n),
       .ddr2_ck_p                      (ddr2_ck_p),
       .ddr2_cke                       (ddr2_cke),
       .ddr2_ras_n                     (ddr2_ras_n),
       .ddr2_we_n                      (ddr2_we_n),
       .ddr2_dq                        (ddr2_dq),
       .ddr2_dqs_n                     (ddr2_dqs_n),
       .ddr2_dqs_p                     (ddr2_dqs_p),
       .init_calib_complete            (init_calib_complete),
     
       .ddr2_cs_n                      (ddr2_cs_n),
       .ddr2_dm                        (ddr2_dm),
       .ddr2_odt                       (ddr2_odt),
       .ui_clk                         (clk),
       .ui_clk_sync_rst                (rst),

       .mmcm_locked                    (mmcm_locked),
       .aresetn                        (aresetn),
       .app_sr_req                     ( 1'b0),
       .app_ref_req                    ( 1'b0),
       .app_zq_req                     ( 1'b0),
       .app_sr_active                  (),
       .app_ref_ack                    (),
       .app_zq_ack                     (),


       .s_axi_awid                     (m_axi_awid),
       .s_axi_awaddr                   (m_axi_awaddr),
       .s_axi_awlen                    (m_axi_awlen),
       .s_axi_awsize                   (m_axi_awsize),
       .s_axi_awburst                  (m_axi_awburst),
       .s_axi_awlock                   (m_axi_awlock),
       .s_axi_awcache                  (m_axi_awcache),
       .s_axi_awprot                   (m_axi_awprot),
       .s_axi_awqos                    (4'h0),
       .s_axi_awvalid                  (m_axi_awvalid),
       .s_axi_awready                  (m_axi_awready),

       .s_axi_wdata                    (m_axi_wdata),
       .s_axi_wstrb                    (m_axi_wstrb),
       .s_axi_wlast                    (m_axi_wlast),
       .s_axi_wvalid                   (m_axi_wvalid),
       .s_axi_wready                   (m_axi_wready),

       .s_axi_bid                      (m_axi_bid),
       .s_axi_bresp                    (m_axi_bresp),
       .s_axi_bvalid                   (m_axi_bvalid),
       .s_axi_bready                   (m_axi_bready),

       .s_axi_arid                     (m_axi_arid),
       .s_axi_araddr                   (m_axi_araddr),
       .s_axi_arlen                    (m_axi_arlen),
       .s_axi_arsize                   (m_axi_arsize),
       .s_axi_arburst                  (m_axi_arburst),
       .s_axi_arlock                   (m_axi_arlock),
       .s_axi_arcache                  (m_axi_arcache),
       .s_axi_arprot                   (m_axi_arprot),
       .s_axi_arqos                    (4'h0),
       .s_axi_arvalid                  (m_axi_arvalid),
       .s_axi_arready                  (m_axi_arready),

       .s_axi_rid                      (m_axi_rid),
       .s_axi_rdata                    (m_axi_rdata),
       .s_axi_rresp                    (m_axi_rresp),
       .s_axi_rlast                    (m_axi_rlast),
       .s_axi_rvalid                   (m_axi_rvalid),
       .s_axi_rready                   (m_axi_rready),

       .sys_clk_i                      (ddr2_main),
       .clk_ref_i                      (ddr2_ref),
       .sys_rst                        (locked)
   );

   always @(posedge clk) begin
     aresetn <= ~rst;
   end
   


   clk_converter clock_converter (
       .s_axi_aclk(core_clk),
       .s_axi_aresetn(locked),
       .s_axi_awid(s_axi_awid),
       .s_axi_awaddr(s_axi_awaddr),
       .s_axi_awlen(s_axi_awlen),
       .s_axi_awsize(s_axi_awsize),
       .s_axi_awburst(s_axi_awburst),
       .s_axi_awlock(1'b0),
       .s_axi_awcache(4'b10),
       .s_axi_awprot(s_axi_awprot),
       .s_axi_awregion(4'b0),
       .s_axi_awqos(4'b0),
       .s_axi_awvalid(s_axi_awvalid),
       .s_axi_awready(s_axi_awready),
       .s_axi_wdata(s_axi_wdata),
       .s_axi_wstrb(s_axi_wstrb),
       .s_axi_wlast(s_axi_wlast),
       .s_axi_wvalid(s_axi_wvalid),
       .s_axi_wready(s_axi_wready),
       .s_axi_bid(s_axi_bid),
       .s_axi_bresp(s_axi_bresp),
       .s_axi_bvalid(s_axi_bvalid),
       .s_axi_bready(s_axi_bready),
       .s_axi_arid(s_axi_arid),
       .s_axi_araddr(s_axi_araddr),
       .s_axi_arlen(s_axi_arlen),
       .s_axi_arsize(s_axi_arsize),
       .s_axi_arburst(s_axi_arburst),
       .s_axi_arlock(1'b0),
       .s_axi_arcache(4'b10),
       .s_axi_arprot(s_axi_arprot),
       .s_axi_arregion(4'b0),
       .s_axi_arqos(4'b0),
       .s_axi_arvalid(s_axi_arvalid),
       .s_axi_arready(s_axi_arready),
       .s_axi_rid(s_axi_rid),
       .s_axi_rdata(s_axi_rdata),
       .s_axi_rresp(s_axi_rresp),
       .s_axi_rlast(s_axi_rlast),
       .s_axi_rvalid(s_axi_rvalid),
       .s_axi_rready(s_axi_rready),
       .m_axi_aclk(clk),
       .m_axi_aresetn(aresetn),
       .m_axi_awid(m_axi_awid),
       .m_axi_awaddr(m_axi_awaddr),
       .m_axi_awlen(m_axi_awlen),
       .m_axi_awsize(m_axi_awsize),
       .m_axi_awburst(m_axi_awburst),
       .m_axi_awlock(m_axi_awlock),
       .m_axi_awcache(m_axi_awcache),
       .m_axi_awprot(m_axi_awprot),
       .m_axi_awregion(),
       .m_axi_awqos(),
       .m_axi_awvalid(m_axi_awvalid),
       .m_axi_awready(m_axi_awready),
       .m_axi_wdata(m_axi_wdata),
       .m_axi_wstrb(m_axi_wstrb),
       .m_axi_wlast(m_axi_wlast),
       .m_axi_wvalid(m_axi_wvalid),
       .m_axi_wready(m_axi_wready),
       .m_axi_bid(m_axi_bid),
       .m_axi_bresp(m_axi_bresp),
       .m_axi_bvalid(m_axi_bvalid),
       .m_axi_bready(m_axi_bready),
       .m_axi_arid(m_axi_arid),
       .m_axi_araddr(m_axi_araddr),
       .m_axi_arlen(m_axi_arlen),
       .m_axi_arsize(m_axi_arsize),
       .m_axi_arburst(m_axi_arburst),
       .m_axi_arlock(m_axi_arlock),
       .m_axi_arcache(m_axi_arcache),
       .m_axi_arprot(m_axi_arprot),
       .m_axi_arregion(),
       .m_axi_arqos(),
       .m_axi_arvalid(m_axi_arvalid),
       .m_axi_arready(m_axi_arready),
       .m_axi_rid(m_axi_rid),
       .m_axi_rdata(m_axi_rdata),
       .m_axi_rresp(m_axi_rresp),
       .m_axi_rlast(m_axi_rlast),
       .m_axi_rvalid(m_axi_rvalid), 
       .m_axi_rready(m_axi_rready)
   );

   

   mkSoc core(

       .CLK(core_clk),
       .RST_N(soc_reset),
`ifndef JTAG_BSCAN2E       

       .CLK_tck_clk(pin_tck),
       .RST_N_trst(pin_trst),
       .wire_tms_tms_in(pin_tms),
       .wire_tdi_tdi_in(pin_tdi),
       .wire_tdo(pin_tdo),
`else
        .CLK_tck_clk(wire_tck_clk),
        .RST_N_trst(~wire_trst),
        .wire_capture_capture_in(wire_capture),     
        .wire_run_test_run_test_in(wire_run_test),     
        .wire_sel_sel_in(wire_sel),     
        .wire_shift_shift_in(wire_shift),     
        .wire_tdi_tdi_in(wire_tdi),     
        .wire_tms_tms_in(wire_tms),     
        .wire_update_update_in(wire_update),     
        .wire_tdo(wire_tdo),
`endif

       .uart_io_SIN(uart_SIN),
       .uart_io_SOUT(uart_SOUT),


		   .mem_master_AWVALID (s_axi_awvalid),
		   .mem_master_AWADDR  (temp_s_axi_awaddr),
		   .mem_master_AWSIZE  (s_axi_awsize),
		   .mem_master_AWPROT  (s_axi_awprot),
		   .mem_master_AWLEN   (s_axi_awlen),
		   .mem_master_AWBURST (s_axi_awburst),
		   .mem_master_AWID    (s_axi_awid),
		   .mem_master_AWREADY (s_axi_awready),
                
		   .mem_master_WVALID  (s_axi_wvalid),
		   .mem_master_WDATA   (s_axi_wdata),
		   .mem_master_WSTRB   (s_axi_wstrb),
		   .mem_master_WLAST   (s_axi_wlast),
		   .mem_master_WID     (),
		   .mem_master_WREADY  (s_axi_wready),
                
		   .mem_master_BVALID  (s_axi_bvalid),
		   .mem_master_BRESP   (s_axi_bresp),
		   .mem_master_BID     (s_axi_bid),
		   .mem_master_BREADY  (s_axi_bready),
                
		   .mem_master_ARVALID (s_axi_arvalid),
		   .mem_master_ARADDR  (temp_s_axi_araddr),
		   .mem_master_ARSIZE  (s_axi_arsize),
		   .mem_master_ARPROT  (s_axi_arprot),
		   .mem_master_ARLEN   (s_axi_arlen),
		   .mem_master_ARBURST (s_axi_arburst),
		   .mem_master_ARID    (s_axi_arid),
		   .mem_master_ARREADY (s_axi_arready),
                
		   .mem_master_RVALID (s_axi_rvalid),
		   .mem_master_RRESP  (s_axi_rresp),
		   .mem_master_RDATA  (s_axi_rdata),
		   .mem_master_RLAST  (s_axi_rlast),
		   .mem_master_RID    (s_axi_rid),
		   .mem_master_RREADY(s_axi_rready)



       




   );















endmodule
module fpga_top#
  (
   parameter AXI_ID_WIDTH   = 4,
   parameter AXI_ADDR_WIDTH = 27
   )
  (


   inout [15:0]   ddr2_dq,
   inout [1:0]    ddr2_dqs_n,
   inout [1:0]    ddr2_dqs_p,

   output [12:0] ddr2_addr,
   output [2:0]  ddr2_ba,
   output        ddr2_ras_n,
   output        ddr2_cas_n,
   output        ddr2_we_n,
   output        ddr2_ck_p,
   output        ddr2_ck_n,
   output        ddr2_cke,
   
   output        ddr2_cs_n,
   
   output [1:0]  ddr2_dm,
  
   output        ddr2_odt,

  `ifndef JTAG_BSCAN2E
    input       pin_tck,
    input       pin_trst,
    input       pin_tms,
    input       pin_tdi,
    output      pin_tdo,
  `endif
    
   output        init_calib_complete,
   

   input         uart_SIN,
   output        uart_SOUT,   


   inout         i2c_sda,
   inout         i2c_scl,








   input         sys_rst,
   

   input         sys_clk
   );

    

   

   
   wire                            soc_reset;
   wire                            core_clk;
   wire                            ddr2_main;
   wire                            ddr2_ref;
   wire                            locked;
   wire                            clk;
   wire                            rst;
   wire                            mmcm_locked;
   reg                             aresetn;
   reg                             aresetn_s;
  

   wire [AXI_ID_WIDTH-1:0]           m_axi_awid;
   wire [AXI_ADDR_WIDTH-1:0]         m_axi_awaddr;
   wire [7:0]                        m_axi_awlen;
   wire [2:0]                        m_axi_awsize;
   wire [1:0]                        m_axi_awburst;
   wire [0:0]                        m_axi_awlock;
   wire [3:0]                        m_axi_awcache;
   wire [2:0]                        m_axi_awprot;
   wire                              m_axi_awvalid;
   wire                              m_axi_awready;

   wire [63:0]                      m_axi_wdata;
   wire [7:0]                       m_axi_wstrb;
   wire                              m_axi_wlast;
   wire                              m_axi_wvalid;
   wire                              m_axi_wready;

   wire                              m_axi_bready;
   wire [AXI_ID_WIDTH-1:0]           m_axi_bid;
   wire [1:0]                        m_axi_bresp;
   wire                              m_axi_bvalid;

   wire [AXI_ID_WIDTH-1:0]           m_axi_arid;
   wire [AXI_ADDR_WIDTH-1:0]         m_axi_araddr;
   wire [7:0]                        m_axi_arlen;
   wire [2:0]                        m_axi_arsize;
   wire [1:0]                        m_axi_arburst;
   wire [0:0]                        m_axi_arlock;
   wire [3:0]                        m_axi_arcache;
   wire [2:0]                        m_axi_arprot;
   wire                              m_axi_arvalid;
   wire                              m_axi_arready;

   wire                              m_axi_rready;
   wire [AXI_ID_WIDTH-1:0]           m_axi_rid;
   wire [127:0]                      m_axi_rdata;
   wire [1:0]                        m_axi_rresp;
   wire                              m_axi_rlast;
   wire                              m_axi_rvalid;


   wire [AXI_ID_WIDTH-1:0]           s_axi_awid;
   wire [AXI_ADDR_WIDTH-1:0]         s_axi_awaddr;
   wire [7:0]                        s_axi_awlen;
   wire [2:0]                        s_axi_awsize;
   wire [1:0]                        s_axi_awburst;
   wire [0:0]                        s_axi_awlock;
   wire [3:0]                        s_axi_awcache;
   wire [2:0]                        s_axi_awprot;
   wire                              s_axi_awvalid;
   wire                              s_axi_awready;

   wire [63:0]                       s_axi_wdata;
   wire [7:0]                        s_axi_wstrb;
   wire                              s_axi_wlast;
   wire                              s_axi_wvalid;
   wire                              s_axi_wready;
   
   wire                              s_axi_bready;
   wire [AXI_ID_WIDTH-1:0]           s_axi_bid;
   wire [1:0]                        s_axi_bresp;
   wire                              s_axi_bvalid;
   
   wire [AXI_ID_WIDTH-1:0]           s_axi_arid;
   wire [AXI_ADDR_WIDTH-1:0]         s_axi_araddr;
   wire [7:0]                        s_axi_arlen;
   wire [2:0]                        s_axi_arsize;
   wire [1:0]                        s_axi_arburst;
   wire [0:0]                        s_axi_arlock;
   wire [3:0]                        s_axi_arcache;
   wire [2:0]                        s_axi_arprot;
   wire                              s_axi_arvalid;
   wire                              s_axi_arready;
   
   wire                              s_axi_rready;
   wire [AXI_ID_WIDTH-1:0]           s_axi_rid;
   wire [63:0]                       s_axi_rdata;
   wire [1:0]                        s_axi_rresp;
   wire                              s_axi_rlast;
   wire                              s_axi_rvalid;
 

   

   
   

  `ifdef JTAG_BSCAN2E
    wire wire_tck_clk;
    wire wire_trst;
    wire wire_capture;
    wire wire_run_test;
    wire wire_sel;
    wire wire_shift;
    wire wire_tdi;
    wire wire_tms;
    wire wire_update;
    wire wire_tdo;

    BSCANE2 #(
      .JTAG_CHAIN(4)
    )
    bse2_inst (
      .CAPTURE(wire_capture),
      .DRCK(),
      .RESET(wire_trst),
      .RUNTEST(wire_run_test),
      .SEL(wire_sel),
      .SHIFT(wire_shift),
      .TCK(wire_tck_clk),
      .TDI(wire_tdi),
      .TMS(wire_tms),
      .UPDATE(wire_update),
      .TDO(wire_tdo)
    );
  `endif
  
   
   

   wire [31:0] temp_s_axi_awaddr, temp_s_axi_araddr;
   assign s_axi_awaddr= temp_s_axi_awaddr [AXI_ADDR_WIDTH-1:0];
   assign s_axi_araddr= temp_s_axi_araddr [AXI_ADDR_WIDTH-1:0];
   assign soc_reset = locked;



   
   clk_divider clk_div (
                       .clk_in1(sys_clk),  
                       .clk_out1(core_clk),
                       .clk_out2(ddr2_main),
                       .clk_out3(ddr2_ref),
                       .resetn(sys_rst), 
                       .locked(locked) );




   mig_ddr2 mig_ddr2 (

       .ddr2_addr                      (ddr2_addr),
       .ddr2_ba                        (ddr2_ba),
       .ddr2_cas_n                     (ddr2_cas_n),
       .ddr2_ck_n                      (ddr2_ck_n),
       .ddr2_ck_p                      (ddr2_ck_p),
       .ddr2_cke                       (ddr2_cke),
       .ddr2_ras_n                     (ddr2_ras_n),
       .ddr2_we_n                      (ddr2_we_n),
       .ddr2_dq                        (ddr2_dq),
       .ddr2_dqs_n                     (ddr2_dqs_n),
       .ddr2_dqs_p                     (ddr2_dqs_p),
       .init_calib_complete            (init_calib_complete),
     
       .ddr2_cs_n                      (ddr2_cs_n),
       .ddr2_dm                        (ddr2_dm),
       .ddr2_odt                       (ddr2_odt),
       .ui_clk                         (clk),
       .ui_clk_sync_rst                (rst),

       .mmcm_locked                    (mmcm_locked),
       .aresetn                        (aresetn),
       .app_sr_req                     ( 1'b0),
       .app_ref_req                    ( 1'b0),
       .app_zq_req                     ( 1'b0),
       .app_sr_active                  (),
       .app_ref_ack                    (),
       .app_zq_ack                     (),


       .s_axi_awid                     (m_axi_awid),
       .s_axi_awaddr                   (m_axi_awaddr),
       .s_axi_awlen                    (m_axi_awlen),
       .s_axi_awsize                   (m_axi_awsize),
       .s_axi_awburst                  (m_axi_awburst),
       .s_axi_awlock                   (m_axi_awlock),
       .s_axi_awcache                  (m_axi_awcache),
       .s_axi_awprot                   (m_axi_awprot),
       .s_axi_awqos                    (4'h0),
       .s_axi_awvalid                  (m_axi_awvalid),
       .s_axi_awready                  (m_axi_awready),

       .s_axi_wdata                    (m_axi_wdata),
       .s_axi_wstrb                    (m_axi_wstrb),
       .s_axi_wlast                    (m_axi_wlast),
       .s_axi_wvalid                   (m_axi_wvalid),
       .s_axi_wready                   (m_axi_wready),

       .s_axi_bid                      (m_axi_bid),
       .s_axi_bresp                    (m_axi_bresp),
       .s_axi_bvalid                   (m_axi_bvalid),
       .s_axi_bready                   (m_axi_bready),

       .s_axi_arid                     (m_axi_arid),
       .s_axi_araddr                   (m_axi_araddr),
       .s_axi_arlen                    (m_axi_arlen),
       .s_axi_arsize                   (m_axi_arsize),
       .s_axi_arburst                  (m_axi_arburst),
       .s_axi_arlock                   (m_axi_arlock),
       .s_axi_arcache                  (m_axi_arcache),
       .s_axi_arprot                   (m_axi_arprot),
       .s_axi_arqos                    (4'h0),
       .s_axi_arvalid                  (m_axi_arvalid),
       .s_axi_arready                  (m_axi_arready),

       .s_axi_rid                      (m_axi_rid),
       .s_axi_rdata                    (m_axi_rdata),
       .s_axi_rresp                    (m_axi_rresp),
       .s_axi_rlast                    (m_axi_rlast),
       .s_axi_rvalid                   (m_axi_rvalid),
       .s_axi_rready                   (m_axi_rready),

       .sys_clk_i                      (ddr2_main),
       .clk_ref_i                      (ddr2_ref),
       .sys_rst                        (locked)
   );

   always @(posedge clk) begin
     aresetn <= ~rst;
   end
   


   clk_converter clock_converter (
       .s_axi_aclk(core_clk),
       .s_axi_aresetn(locked),
       .s_axi_awid(s_axi_awid),
       .s_axi_awaddr(s_axi_awaddr),
       .s_axi_awlen(s_axi_awlen),
       .s_axi_awsize(s_axi_awsize),
       .s_axi_awburst(s_axi_awburst),
       .s_axi_awlock(1'b0),
       .s_axi_awcache(4'b10),
       .s_axi_awprot(s_axi_awprot),
       .s_axi_awregion(4'b0),
       .s_axi_awqos(4'b0),
       .s_axi_awvalid(s_axi_awvalid),
       .s_axi_awready(s_axi_awready),
       .s_axi_wdata(s_axi_wdata),
       .s_axi_wstrb(s_axi_wstrb),
       .s_axi_wlast(s_axi_wlast),
       .s_axi_wvalid(s_axi_wvalid),
       .s_axi_wready(s_axi_wready),
       .s_axi_bid(s_axi_bid),
       .s_axi_bresp(s_axi_bresp),
       .s_axi_bvalid(s_axi_bvalid),
       .s_axi_bready(s_axi_bready),
       .s_axi_arid(s_axi_arid),
       .s_axi_araddr(s_axi_araddr),
       .s_axi_arlen(s_axi_arlen),
       .s_axi_arsize(s_axi_arsize),
       .s_axi_arburst(s_axi_arburst),
       .s_axi_arlock(1'b0),
       .s_axi_arcache(4'b10),
       .s_axi_arprot(s_axi_arprot),
       .s_axi_arregion(4'b0),
       .s_axi_arqos(4'b0),
       .s_axi_arvalid(s_axi_arvalid),
       .s_axi_arready(s_axi_arready),
       .s_axi_rid(s_axi_rid),
       .s_axi_rdata(s_axi_rdata),
       .s_axi_rresp(s_axi_rresp),
       .s_axi_rlast(s_axi_rlast),
       .s_axi_rvalid(s_axi_rvalid),
       .s_axi_rready(s_axi_rready),
       .m_axi_aclk(clk),
       .m_axi_aresetn(aresetn),
       .m_axi_awid(m_axi_awid),
       .m_axi_awaddr(m_axi_awaddr),
       .m_axi_awlen(m_axi_awlen),
       .m_axi_awsize(m_axi_awsize),
       .m_axi_awburst(m_axi_awburst),
       .m_axi_awlock(m_axi_awlock),
       .m_axi_awcache(m_axi_awcache),
       .m_axi_awprot(m_axi_awprot),
       .m_axi_awregion(),
       .m_axi_awqos(),
       .m_axi_awvalid(m_axi_awvalid),
       .m_axi_awready(m_axi_awready),
       .m_axi_wdata(m_axi_wdata),
       .m_axi_wstrb(m_axi_wstrb),
       .m_axi_wlast(m_axi_wlast),
       .m_axi_wvalid(m_axi_wvalid),
       .m_axi_wready(m_axi_wready),
       .m_axi_bid(m_axi_bid),
       .m_axi_bresp(m_axi_bresp),
       .m_axi_bvalid(m_axi_bvalid),
       .m_axi_bready(m_axi_bready),
       .m_axi_arid(m_axi_arid),
       .m_axi_araddr(m_axi_araddr),
       .m_axi_arlen(m_axi_arlen),
       .m_axi_arsize(m_axi_arsize),
       .m_axi_arburst(m_axi_arburst),
       .m_axi_arlock(m_axi_arlock),
       .m_axi_arcache(m_axi_arcache),
       .m_axi_arprot(m_axi_arprot),
       .m_axi_arregion(),
       .m_axi_arqos(),
       .m_axi_arvalid(m_axi_arvalid),
       .m_axi_arready(m_axi_arready),
       .m_axi_rid(m_axi_rid),
       .m_axi_rdata(m_axi_rdata),
       .m_axi_rresp(m_axi_rresp),
       .m_axi_rlast(m_axi_rlast),
       .m_axi_rvalid(m_axi_rvalid), 
       .m_axi_rready(m_axi_rready)
   );

   

   mkSoc core(

       .CLK(core_clk),
       .RST_N(soc_reset),
`ifndef JTAG_BSCAN2E       

       .CLK_tck_clk(pin_tck),
       .RST_N_trst(pin_trst),
       .wire_tms_tms_in(pin_tms),
       .wire_tdi_tdi_in(pin_tdi),
       .wire_tdo(pin_tdo),
`else
        .CLK_tck_clk(wire_tck_clk),
        .RST_N_trst(~wire_trst),
        .wire_capture_capture_in(wire_capture),     
        .wire_run_test_run_test_in(wire_run_test),     
        .wire_sel_sel_in(wire_sel),     
        .wire_shift_shift_in(wire_shift),     
        .wire_tdi_tdi_in(wire_tdi),     
        .wire_tms_tms_in(wire_tms),     
        .wire_update_update_in(wire_update),     
        .wire_tdo(wire_tdo),
`endif

       .uart_io_SIN(uart_SIN),
       .uart_io_SOUT(uart_SOUT),


		   .mem_master_AWVALID (s_axi_awvalid),
		   .mem_master_AWADDR  (temp_s_axi_awaddr),
		   .mem_master_AWSIZE  (s_axi_awsize),
		   .mem_master_AWPROT  (s_axi_awprot),
		   .mem_master_AWLEN   (s_axi_awlen),
		   .mem_master_AWBURST (s_axi_awburst),
		   .mem_master_AWID    (s_axi_awid),
		   .mem_master_AWREADY (s_axi_awready),
                
		   .mem_master_WVALID  (s_axi_wvalid),
		   .mem_master_WDATA   (s_axi_wdata),
		   .mem_master_WSTRB   (s_axi_wstrb),
		   .mem_master_WLAST   (s_axi_wlast),
		   .mem_master_WID     (),
		   .mem_master_WREADY  (s_axi_wready),
                
		   .mem_master_BVALID  (s_axi_bvalid),
		   .mem_master_BRESP   (s_axi_bresp),
		   .mem_master_BID     (s_axi_bid),
		   .mem_master_BREADY  (s_axi_bready),
                
		   .mem_master_ARVALID (s_axi_arvalid),
		   .mem_master_ARADDR  (temp_s_axi_araddr),
		   .mem_master_ARSIZE  (s_axi_arsize),
		   .mem_master_ARPROT  (s_axi_arprot),
		   .mem_master_ARLEN   (s_axi_arlen),
		   .mem_master_ARBURST (s_axi_arburst),
		   .mem_master_ARID    (s_axi_arid),
		   .mem_master_ARREADY (s_axi_arready),
                
		   .mem_master_RVALID (s_axi_rvalid),
		   .mem_master_RRESP  (s_axi_rresp),
		   .mem_master_RDATA  (s_axi_rdata),
		   .mem_master_RLAST  (s_axi_rlast),
		   .mem_master_RID    (s_axi_rid),
		   .mem_master_RREADY(s_axi_rready)



       




   );















endmodule