data/full_repos/permissive/453648766/design_file/top_design_file_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/453648766/design_file/top_design_file_TB.v:37: Unsupported: Ignoring delay on this delayed statement.\n always #10 clk = ~clk ;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/453648766/design_file/top_design_file_TB.v:39: Unsupported: Ignoring delay on this delayed statement.\n #0 clk = 0 ; rst = 1; data_in = 0 ;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/453648766/design_file/top_design_file_TB.v:40: Unsupported: Ignoring delay on this delayed statement.\n #30 rst = 0 ; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/453648766/design_file/top_design_file_TB.v:41: Unsupported: Ignoring delay on this delayed statement.\n#20 data_in = 9 ;\n^\n%Warning-STMTDLY: data/full_repos/permissive/453648766/design_file/top_design_file_TB.v:42: Unsupported: Ignoring delay on this delayed statement.\n#60 data_in = 7 ;\n^\n%Warning-STMTDLY: data/full_repos/permissive/453648766/design_file/top_design_file_TB.v:43: Unsupported: Ignoring delay on this delayed statement.\n#90 data_in = 8 ;\n^\n%Warning-STMTDLY: data/full_repos/permissive/453648766/design_file/top_design_file_TB.v:44: Unsupported: Ignoring delay on this delayed statement.\n#100 $stop ;    \n^\n%Error: data/full_repos/permissive/453648766/design_file/top_design_file_TB.v:33: Cannot find file containing module: \'top_design_file\'\n    top_design_file  DUT (\n    ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/453648766/design_file,data/full_repos/permissive/453648766/top_design_file\n             data/full_repos/permissive/453648766/design_file,data/full_repos/permissive/453648766/top_design_file.v\n             data/full_repos/permissive/453648766/design_file,data/full_repos/permissive/453648766/top_design_file.sv\n             top_design_file\n             top_design_file.v\n             top_design_file.sv\n             obj_dir/top_design_file\n             obj_dir/top_design_file.v\n             obj_dir/top_design_file.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_design_file_TB(

    );
    
    reg [3:0] data_in ;
    reg clk, rst  ;
    wire [3:0] data_out , Reg1, Reg2 , Reg3 ;
    wire [1:0] state ;
    
    
    top_design_file  DUT (
 clk ,rst ,  data_in ,  data_out
 , state, Reg1, Reg2 , Reg3  );
 
 always #10 clk = ~clk ;
 initial begin
 #0 clk = 0 ; rst = 1; data_in = 0 ;
 #30 rst = 0 ; 
#20 data_in = 9 ;
#60 data_in = 7 ;
#90 data_in = 8 ;
#100 $stop ;    
 end
 
endmodule
module top_design_file_TB(

    );

    
    reg [3:0] data_in ;
    reg clk, rst  ;
    wire [3:0] data_out , Reg1, Reg2 , Reg3 ;
    wire [1:0] state ;
    
    
    top_design_file  DUT (
 clk ,rst ,  data_in ,  data_out
 , state, Reg1, Reg2 , Reg3  );
 
 always #10 clk = ~clk ;
 initial begin
 #0 clk = 0 ; rst = 1; data_in = 0 ;
 #30 rst = 0 ; 
#20 data_in = 9 ;
#60 data_in = 7 ;
#90 data_in = 8 ;
#100 $stop ;    
 end
 
endmodule