data/full_repos/permissive/445929378/multiplication_modulo_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/445929378/multiplication_modulo_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/445929378/multiplication_modulo_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n      #5;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/445929378/multiplication_modulo_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n      #200;\n      ^\n%Error: data/full_repos/permissive/445929378/multiplication_modulo_tb.v:24: Cannot find file containing module: \'multiplication_modulo\'\n   multiplication_modulo uut(\n   ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/multiplication_modulo\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/multiplication_modulo.v\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/multiplication_modulo.sv\n             multiplication_modulo\n             multiplication_modulo.v\n             multiplication_modulo.sv\n             obj_dir/multiplication_modulo\n             obj_dir/multiplication_modulo.v\n             obj_dir/multiplication_modulo.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module multiplication_modulo_tb #(parameter SIZE = 64);


   reg clk;
   reg rst;
   reg [SIZE-1 : 0] multiplier;
   reg 			multiplier_tvalid;
   reg [SIZE-1 : 0] multiplicand;
   reg 			multiplicand_tvalid;
   reg [SIZE-1 : 0] modulus;
   reg 			modulus_tvalid;
   reg 			output_tready;


   wire 		multiplier_tready;
   wire 		multiplicand_tready;
   wire [SIZE-1 : 0] 	output_tdata;
   wire 		output_tvalid;
   


   multiplication_modulo uut(
	      .clk(clk), 
	      .rst(rst), 
	      .input_multiplier_tdata(multiplier), 
	      .input_multiplier_tvalid(multiplier_tvalid), 
	      .input_multiplier_tready(multiplier_tready), 
	      .input_multiplicand_tdata(multiplicand), 
	      .input_multiplicand_tvalid(multiplicand_tvalid), 
	      .input_multiplicand_tready(multiplicand_tready),
	      .input_modulus_tdata(modulus), 
	      .input_modulus_tvalid(modulus_tvalid), 
	      .input_modulus_tready(modulus_tready), 
	      .output_tdata(output_tdata), 
	      .output_tvalid(output_tvalid), 
	      .output_tready(output_tready)
	      );
   
   initial begin
      clk = 0;
      forever begin
	 #10 clk = ~clk;
      end
   end

   initial begin

      rst = 0;

      multiplier = 64'd9223372036854775337;

      multiplier_tvalid = 1;


      multiplicand = 64'd9223372036854775337;
      multiplicand_tvalid = 1;

      modulus = 64'd9223372036854775433;
      modulus_tvalid = 1;
      
      output_tready = 0;
      #5;
      output_tready = 1;	

      

      #200;
      


   end
   
endmodule
module multiplication_modulo_tb #(parameter SIZE = 64);



   reg clk;
   reg rst;
   reg [SIZE-1 : 0] multiplier;
   reg 			multiplier_tvalid;
   reg [SIZE-1 : 0] multiplicand;
   reg 			multiplicand_tvalid;
   reg [SIZE-1 : 0] modulus;
   reg 			modulus_tvalid;
   reg 			output_tready;


   wire 		multiplier_tready;
   wire 		multiplicand_tready;
   wire [SIZE-1 : 0] 	output_tdata;
   wire 		output_tvalid;
   


   multiplication_modulo uut(
	      .clk(clk), 
	      .rst(rst), 
	      .input_multiplier_tdata(multiplier), 
	      .input_multiplier_tvalid(multiplier_tvalid), 
	      .input_multiplier_tready(multiplier_tready), 
	      .input_multiplicand_tdata(multiplicand), 
	      .input_multiplicand_tvalid(multiplicand_tvalid), 
	      .input_multiplicand_tready(multiplicand_tready),
	      .input_modulus_tdata(modulus), 
	      .input_modulus_tvalid(modulus_tvalid), 
	      .input_modulus_tready(modulus_tready), 
	      .output_tdata(output_tdata), 
	      .output_tvalid(output_tvalid), 
	      .output_tready(output_tready)
	      );
   
   initial begin
      clk = 0;
      forever begin
	 #10 clk = ~clk;
      end
   end

   initial begin

      rst = 0;

      multiplier = 64'd9223372036854775337;

      multiplier_tvalid = 1;


      multiplicand = 64'd9223372036854775337;
      multiplicand_tvalid = 1;

      modulus = 64'd9223372036854775433;
      modulus_tvalid = 1;
      
      output_tready = 0;
      #5;
      output_tready = 1;	

      

      #200;
      


   end
   
endmodule