data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_pkg.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_pkg.sv:130: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'h1\' generates 4 bits.\n    unique case (len)\n           ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_pkg.sv:130: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'h3\' generates 4 bits.\n    unique case (len)\n           ^~~~\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_pkg.sv:130: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'h7\' generates 4 bits.\n    unique case (len)\n           ^~~~\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_pkg.sv:130: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'hf\' generates 4 bits.\n    unique case (len)\n           ^~~~\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_pkg.sv:167: Operator ADD expects 128 bits on the LHS, but LHS\'s VARREF \'len\' generates 8 bits.\n        ret_addr = ret_addr - (num_bytes(size) * (len + 1));\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_pkg.sv:166: Operator ADD expects 128 bits on the LHS, but LHS\'s VARREF \'len\' generates 8 bits.\n      if (burst == BURST_WRAP && ret_addr >= wrp_bond + (num_bytes(size) * (len + 1))) begin\n                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_pkg.sv:178: Operator DIV expects 128 bits on the RHS, but RHS\'s VARREF \'strobe_width\' generates 16 bits.\n    return _addr - (_addr / strobe_width) * strobe_width;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_pkg.sv:178: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SUB generates 128 bits.\n    return _addr - (_addr / strobe_width) * strobe_width;\n    ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_pkg.sv:186: Operator SUB expects 128 bits on the LHS, but LHS\'s FUNCREF \'num_bytes\' generates 16 bits.\n      return aligned_addr(addr, size) + (num_bytes(size) - 1) - (addr / strobe_width) * strobe_width;\n                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_pkg.sv:186: Operator DIV expects 128 bits on the RHS, but RHS\'s VARREF \'strobe_width\' generates 16 bits.\n      return aligned_addr(addr, size) + (num_bytes(size) - 1) - (addr / strobe_width) * strobe_width;\n                                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_pkg.sv:186: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SUB generates 128 bits.\n      return aligned_addr(addr, size) + (num_bytes(size) - 1) - (addr / strobe_width) * strobe_width;\n      ^~~~~~\n%Error: Exiting due to 11 warning(s)\n'
function automatic largest_addr_t
  beat_addr(largest_addr_t addr, size_t size, len_t len, burst_t burst, shortint unsigned i_beat);
    largest_addr_t ret_addr = addr;
    largest_addr_t wrp_bond = '0;
    if (burst == BURST_WRAP) begin

      wrp_bond = wrap_boundary(addr, size, len);
    end
    if (i_beat != 0 && burst != BURST_FIXED) begin




      ret_addr = aligned_addr(addr, size) + i_beat * num_bytes(size);











      if (burst == BURST_WRAP && ret_addr >= wrp_bond + (num_bytes(size) * (len + 1))) begin
        ret_addr = ret_addr - (num_bytes(size) * (len + 1));
      end
    end
    return ret_addr;
  endfunction
function automatic largest_addr_t
  beat_addr(largest_addr_t addr, size_t size, len_t len, burst_t burst, shortint unsigned i_beat);

    largest_addr_t ret_addr = addr;
    largest_addr_t wrp_bond = '0;
    if (burst == BURST_WRAP) begin

      wrp_bond = wrap_boundary(addr, size, len);
    end
    if (i_beat != 0 && burst != BURST_FIXED) begin




      ret_addr = aligned_addr(addr, size) + i_beat * num_bytes(size);











      if (burst == BURST_WRAP && ret_addr >= wrp_bond + (num_bytes(size) * (len + 1))) begin
        ret_addr = ret_addr - (num_bytes(size) * (len + 1));
      end
    end
    return ret_addr;
  endfunction