data/full_repos/permissive/476728999/Experiment5/controller_tb.v
1: b'%Error: data/full_repos/permissive/476728999/Experiment5/controller_tb.v:3: Cannot find include file: controller.v\n`include "controller.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/476728999/Experiment5,data/full_repos/permissive/476728999/controller.v\n             data/full_repos/permissive/476728999/Experiment5,data/full_repos/permissive/476728999/controller.v.v\n             data/full_repos/permissive/476728999/Experiment5,data/full_repos/permissive/476728999/controller.v.sv\n             controller.v\n             controller.v.v\n             controller.v.sv\n             obj_dir/controller.v\n             obj_dir/controller.v.v\n             obj_dir/controller.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment5/controller_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n        # 5 clock = 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment5/controller_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n        # 5 clock = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment5/controller_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #50 reset = 0; x = 0; y = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment5/controller_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #50 y = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment5/controller_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #50 x = 1; y = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment5/controller_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #50 x = 0; y = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment5/controller_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #50 x = 1; y = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment5/controller_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #50 x = 1; y = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment5/controller_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #50 x = 1; y = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment5/controller_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #50 x = 0; y = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment5/controller_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #10 x = 1; y = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment5/controller_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #40 x = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment5/controller_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #50 y = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment5/controller_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #10 x = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment5/controller_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #10 x = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment5/controller_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #10 y = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment5/controller_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #20 x = 0; y = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment5/controller_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #10 x = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment5/controller_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #10 x = 0; y = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Experiment5/controller_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #30 $finish;\n    ^\n%Error: Exiting due to 1 error(s), 20 warning(s)\n'
module controller_tb();
    reg x, y, clock, reset;
    wire F1, F0;
    controller UUT(.X(x), .Y(y), .F1(F1), .F0(F0), .clock(clock), .reset(reset));
    
    always begin
        # 5 clock = 1;
        # 5 clock = 0;
    end
    
    initial begin
    reset = 1; clock = 0;
    #50 reset = 0; x = 0; y = 0;
    #50 y = 1;
    #50 x = 1; y = 0;
    #50 x = 0; y = 0;
    #50 x = 1; y = 1;
    #50 x = 1; y = 0;
    #50 x = 1; y = 1;
    #50 x = 0; y = 0;
    #10 x = 1; y = 1;
    #40 x = 0;
    #50 y = 0;
    #10 x = 1;
    #10 x = 0;
    #10 y = 1;
    #20 x = 0; y = 0;
    #10 x = 1;
    #10 x = 0; y = 1;
    

    
    #30 $finish;
    end
   
endmodule
module controller_tb();

    reg x, y, clock, reset;
    wire F1, F0;
    controller UUT(.X(x), .Y(y), .F1(F1), .F0(F0), .clock(clock), .reset(reset));
    
    always begin
        # 5 clock = 1;
        # 5 clock = 0;
    end
    
    initial begin
    reset = 1; clock = 0;
    #50 reset = 0; x = 0; y = 0;
    #50 y = 1;
    #50 x = 1; y = 0;
    #50 x = 0; y = 0;
    #50 x = 1; y = 1;
    #50 x = 1; y = 0;
    #50 x = 1; y = 1;
    #50 x = 0; y = 0;
    #10 x = 1; y = 1;
    #40 x = 0;
    #50 y = 0;
    #10 x = 1;
    #10 x = 0;
    #10 y = 1;
    #20 x = 0; y = 0;
    #10 x = 1;
    #10 x = 0; y = 1;
    

    
    #30 $finish;
    end
   
endmodule