data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_pipelining/cachelib/v_rtl/dut_DECODE_4U_4_4.v
data/verilator_xmls/8de9c65b-a7c6-44c0-9218-851778258bf4.xml
module dut_DECODE_4U_4_4 (
	in1,
	out1
	);
input [1:0] in1;
output [3:0] out1;
wire [3:0] asc001;

assign asc001 = 4'B0001 << in1;

assign out1 = asc001;
endmodule
module dut_DECODE_4U_4_4 (
	in1,
	out1
	);

input [1:0] in1;
output [3:0] out1;
wire [3:0] asc001;

assign asc001 = 4'B0001 << in1;

assign out1 = asc001;
endmodule