data/full_repos/permissive/419538859/lab1_1/lab1_1.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/419538859/lab1_1/lab1_1.v:8: Signal definition not found, creating implicitly: \'clk_work\'\nfreq_div#(20) M1 (clk, reset, clk_work); \n                              ^~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module lab1_1 (clk, reset, shift_out, ctl_bit);
input clk;
input reset;
output[7:0]shift_out; 

output ctl_bit;
assign ctl_bit= 1'b1;
freq_div#(20) M1 (clk, reset, clk_work); 
lab01_1 M2 (clk_work, reset, shift_out);
endmodule
module lab1_1 (clk, reset, shift_out, ctl_bit);

input clk;
input reset;
output[7:0]shift_out; 

output ctl_bit;
assign ctl_bit= 1'b1;
freq_div#(20) M1 (clk, reset, clk_work); 
lab01_1 M2 (clk_work, reset, shift_out);
endmodule