data/full_repos/permissive/418749135/mux_tb.v
1: b'%Error: data/full_repos/permissive/418749135/mux_tb.v:12: Unsupported or unknown PLI call: $monitor\n       $monitor("[%0t] sel=0x%0h a=0x%0h b=0x%0h c=0x%0h d=0x%0h out=0x%0h",$time, sel, a, b, c, d, out);\n       ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/418749135/mux_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n           #5 sel<=i;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/418749135/mux_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n       #5 $finish;\n       ^\n%Error: data/full_repos/permissive/418749135/mux_tb.v:24: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("dump.vcd"); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/418749135/mux_tb.v:25: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_4to1_mux;
  reg [3:0] a;
  reg [3:0] b;
  reg [3:0] c;
  reg [3:0] d;
  wire [3:0] out;
  reg [1:0] sel;
  integer i;

 mux_4to1_case mux0( .a(a), .b(b), .c(c), .d(d), .sel(sel), .out(out)); 
   initial begin
       $monitor("[%0t] sel=0x%0h a=0x%0h b=0x%0h c=0x%0h d=0x%0h out=0x%0h",$time, sel, a, b, c, d, out);
       sel <=0;
       a<= $random;
       b<= $random;
       c<= $random;
       d<= $random;
       for(i=1;i<4;i=i+1)begin
           #5 sel<=i;
       end
       #5 $finish;
   end
   initial begin
	$dumpfile("dump.vcd"); 
	$dumpvars;
	end
endmodule
module tb_4to1_mux;

  reg [3:0] a;
  reg [3:0] b;
  reg [3:0] c;
  reg [3:0] d;
  wire [3:0] out;
  reg [1:0] sel;
  integer i;

 mux_4to1_case mux0( .a(a), .b(b), .c(c), .d(d), .sel(sel), .out(out)); 
   initial begin
       $monitor("[%0t] sel=0x%0h a=0x%0h b=0x%0h c=0x%0h d=0x%0h out=0x%0h",$time, sel, a, b, c, d, out);
       sel <=0;
       a<= $random;
       b<= $random;
       c<= $random;
       d<= $random;
       for(i=1;i<4;i=i+1)begin
           #5 sel<=i;
       end
       #5 $finish;
   end
   initial begin
	$dumpfile("dump.vcd"); 
	$dumpvars;
	end
endmodule