data/full_repos/permissive/527007664/openlane/pixel/src/Pixel.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/527007664/openlane/pixel/src/Pixel.v:287: Cell has missing pin: \'reset\'\n loc_timer_int inst2(\n               ^~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/527007664/openlane/pixel/src/Pixel.v:294: Cell has missing pin: \'reset\'\n adj_timer_int inst3(\n               ^~~~~\n%Error: Exiting due to 2 warning(s)\n'
module demux (data_in, data_sel, data_out);
		input data_in;
		input [3:0] data_sel; 
		output reg [15:0] data_out;
		
		always @(data_in, data_sel) 
		begin
			case (data_sel)
   			4'b0000 : begin data_out[15:0] = 0; end 
			4'b0001 : begin data_out[0] = data_in; data_out[15:1] = 0; end 
			4'b0010 : begin data_out[1] = data_in; data_out[0] = 0; end 
			4'b0011 : begin data_out[2] = data_in; data_out[1:0] = 0; end 
			4'b0100 : begin data_out[3] = data_in; data_out[2:0] = 0; end 
			4'b0101 : begin data_out[4] = data_in; data_out[3:0] = 0; end 
			4'b0110 : begin data_out[5] = data_in; data_out[4:0] = 0; end 
			4'b0111 : begin data_out[6] = data_in; data_out[5:0] = 0; end 
			4'b1000 : begin data_out[7] = data_in; data_out[6:0] = 0; end 
			4'b1001 : begin data_out[8] = data_in; data_out[7:0] = 0; end 
			4'b1010 : begin data_out[9] = data_in; data_out[8:0] = 0; end 
			4'b1011 : begin data_out[10] = data_in; data_out[9:0] = 0; end 
			4'b1100 : begin data_out[11] = data_in; data_out[10:0] = 0; end 
			4'b1101 : begin data_out[12] = data_in; data_out[11:0] = 0; end 
			4'b1110 : begin data_out[13] = data_in; data_out[12:0] = 0; end 
			4'b1111 : begin data_out[14] = data_in; data_out[13:0] = 0; end 
			default : begin data_out[15:0] = 0; end
    			endcase   
		end
endmodule
module demux (data_in, data_sel, data_out);

		input data_in;
		input [3:0] data_sel; 
		output reg [15:0] data_out;
		
		always @(data_in, data_sel) 
		begin
			case (data_sel)
   			4'b0000 : begin data_out[15:0] = 0; end 
			4'b0001 : begin data_out[0] = data_in; data_out[15:1] = 0; end 
			4'b0010 : begin data_out[1] = data_in; data_out[0] = 0; end 
			4'b0011 : begin data_out[2] = data_in; data_out[1:0] = 0; end 
			4'b0100 : begin data_out[3] = data_in; data_out[2:0] = 0; end 
			4'b0101 : begin data_out[4] = data_in; data_out[3:0] = 0; end 
			4'b0110 : begin data_out[5] = data_in; data_out[4:0] = 0; end 
			4'b0111 : begin data_out[6] = data_in; data_out[5:0] = 0; end 
			4'b1000 : begin data_out[7] = data_in; data_out[6:0] = 0; end 
			4'b1001 : begin data_out[8] = data_in; data_out[7:0] = 0; end 
			4'b1010 : begin data_out[9] = data_in; data_out[8:0] = 0; end 
			4'b1011 : begin data_out[10] = data_in; data_out[9:0] = 0; end 
			4'b1100 : begin data_out[11] = data_in; data_out[10:0] = 0; end 
			4'b1101 : begin data_out[12] = data_in; data_out[11:0] = 0; end 
			4'b1110 : begin data_out[13] = data_in; data_out[12:0] = 0; end 
			4'b1111 : begin data_out[14] = data_in; data_out[13:0] = 0; end 
			default : begin data_out[15:0] = 0; end
    			endcase   
		end
endmodule