data/full_repos/permissive/518460376/verilog/rtl/ips/apb/apb_spi_master/spi_master_apb_if.v
1: b'%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/apb/apb_spi_master/spi_master_apb_if.v:118: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'sh0\' generates 1 bits.\n                                                                                                               : ... In instance spi_master_apb_if\n   spi_clk_div <= 1\'sb0;\n               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/apb/apb_spi_master/spi_master_apb_if.v:119: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'sh0\' generates 1 bits.\n                                                                                                               : ... In instance spi_master_apb_if\n   spi_cmd <= 1\'sb0;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/apb/apb_spi_master/spi_master_apb_if.v:120: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'sh0\' generates 1 bits.\n                                                                                                               : ... In instance spi_master_apb_if\n   spi_addr <= 1\'sb0;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/apb/apb_spi_master/spi_master_apb_if.v:121: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'sh0\' generates 1 bits.\n                                                                                                               : ... In instance spi_master_apb_if\n   spi_cmd_len <= 1\'sb0;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/apb/apb_spi_master/spi_master_apb_if.v:122: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'sh0\' generates 1 bits.\n                                                                                                               : ... In instance spi_master_apb_if\n   spi_addr_len <= 1\'sb0;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/apb/apb_spi_master/spi_master_apb_if.v:123: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'sh0\' generates 1 bits.\n                                                                                                               : ... In instance spi_master_apb_if\n   spi_data_len <= 1\'sb0;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/apb/apb_spi_master/spi_master_apb_if.v:124: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'sh0\' generates 1 bits.\n                                                                                                               : ... In instance spi_master_apb_if\n   spi_dummy_rd <= 1\'sb0;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/apb/apb_spi_master/spi_master_apb_if.v:125: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'sh0\' generates 1 bits.\n                                                                                                               : ... In instance spi_master_apb_if\n   spi_dummy_wr <= 1\'sb0;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/apb/apb_spi_master/spi_master_apb_if.v:126: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'sh0\' generates 1 bits.\n                                                                                                               : ... In instance spi_master_apb_if\n   spi_csreg <= 1\'sb0;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/apb/apb_spi_master/spi_master_apb_if.v:127: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'sh0\' generates 1 bits.\n                                                                                                               : ... In instance spi_master_apb_if\n   spi_int_th_tx <= 1\'sb0;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/apb/apb_spi_master/spi_master_apb_if.v:128: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'sh0\' generates 1 bits.\n                                                                                                               : ... In instance spi_master_apb_if\n   spi_int_th_rx <= 1\'sb0;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/apb/apb_spi_master/spi_master_apb_if.v:129: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'sh0\' generates 1 bits.\n                                                                                                               : ... In instance spi_master_apb_if\n   spi_int_cnt_tx <= 1\'sb0;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/apb/apb_spi_master/spi_master_apb_if.v:130: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'sh0\' generates 1 bits.\n                                                                                                               : ... In instance spi_master_apb_if\n   spi_int_cnt_rx <= 1\'sb0;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/apb/apb_spi_master/spi_master_apb_if.v:196: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'sh0\' generates 1 bits.\n                                                                                                               : ... In instance spi_master_apb_if\n    PRDATA = 1\'sb0;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/apb/apb_spi_master/spi_master_apb_if.v:204: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'sh0\' generates 1 bits.\n                                                                                                               : ... In instance spi_master_apb_if\n   default: PRDATA = 1\'sb0;\n                   ^\n%Error: Exiting due to 15 warning(s)\n'
module spi_master_apb_if 
#(
    parameter BUFFER_DEPTH   = 10,
    parameter APB_ADDR_WIDTH = 12,
    parameter LOG_BUFFER_DEPTH = `log2(BUFFER_DEPTH)
)
(
	HCLK,
	HRESETn,
	PADDR,
	PWDATA,
	PWRITE,
	PSEL,
	PENABLE,
	PRDATA,
	PREADY,
	PSLVERR,
	spi_clk_div,
	spi_clk_div_valid,
	spi_status,
	spi_addr,
	spi_addr_len,
	spi_cmd,
	spi_cmd_len,
	spi_csreg,
	spi_data_len,
	spi_dummy_rd,
	spi_dummy_wr,
	spi_int_th_tx,
	spi_int_th_rx,
	spi_int_cnt_tx,
	spi_int_cnt_rx,
	spi_int_en,
	spi_int_cnt_en,
	spi_int_rd_sta,
	spi_swrst,
	spi_rd,
	spi_wr,
	spi_qrd,
	spi_qwr,
	spi_data_tx,
	spi_data_tx_valid,
	spi_data_tx_ready,
	spi_data_rx,
	spi_data_rx_valid,
	spi_data_rx_ready
);



	input wire HCLK;
	input wire HRESETn;
	input wire [APB_ADDR_WIDTH - 1:0] PADDR;
	input wire [31:0] PWDATA;
	input wire PWRITE;
	input wire PSEL;
	input wire PENABLE;
	output reg [31:0] PRDATA;
	output wire PREADY;
	output wire PSLVERR;
	output reg [7:0] spi_clk_div;
	output reg spi_clk_div_valid;
	input wire [31:0] spi_status;
	output reg [31:0] spi_addr;
	output reg [5:0] spi_addr_len;
	output reg [31:0] spi_cmd;
	output reg [5:0] spi_cmd_len;
	output reg [3:0] spi_csreg;
	output reg [15:0] spi_data_len;
	output reg [15:0] spi_dummy_rd;
	output reg [15:0] spi_dummy_wr;
	output reg [LOG_BUFFER_DEPTH:0] spi_int_th_tx;
	output reg [LOG_BUFFER_DEPTH:0] spi_int_th_rx;
	output reg [LOG_BUFFER_DEPTH:0] spi_int_cnt_tx;
	output reg [LOG_BUFFER_DEPTH:0] spi_int_cnt_rx;
	output reg spi_int_en;
	output reg spi_int_cnt_en;
	output wire spi_int_rd_sta;
	output reg spi_swrst;
	output reg spi_rd;
	output reg spi_wr;
	output reg spi_qrd;
	output reg spi_qwr;
	output wire [31:0] spi_data_tx;
	output wire spi_data_tx_valid;
	input wire spi_data_tx_ready;
	input wire [31:0] spi_data_rx;
	input wire spi_data_rx_valid;
	output wire spi_data_rx_ready;
	wire [3:0] write_address;
	wire [3:0] read_address;
	assign write_address = PADDR[5:2];
	assign read_address = PADDR[5:2];
	assign PSLVERR = 1'b0;
	assign PREADY = 1'b1;
	assign spi_int_rd_sta = ((PSEL & PENABLE) & ~PWRITE) & (read_address == 4'b1010);
	always @(posedge HCLK or negedge HRESETn)
		if (HRESETn == 1'b0) begin
			spi_swrst <= 1'b0;
			spi_rd <= 1'b0;
			spi_wr <= 1'b0;
			spi_qrd <= 1'b0;
			spi_qwr <= 1'b0;
			spi_clk_div_valid <= 1'b0;
			spi_clk_div <= 1'sb0;
			spi_cmd <= 1'sb0;
			spi_addr <= 1'sb0;
			spi_cmd_len <= 1'sb0;
			spi_addr_len <= 1'sb0;
			spi_data_len <= 1'sb0;
			spi_dummy_rd <= 1'sb0;
			spi_dummy_wr <= 1'sb0;
			spi_csreg <= 1'sb0;
			spi_int_th_tx <= 1'sb0;
			spi_int_th_rx <= 1'sb0;
			spi_int_cnt_tx <= 1'sb0;
			spi_int_cnt_rx <= 1'sb0;
			spi_int_cnt_en <= 1'b0;
			spi_int_en <= 1'b0;
		end
		else if ((PSEL && PENABLE) && PWRITE) begin
			spi_swrst <= 1'b0;
			spi_rd <= 1'b0;
			spi_wr <= 1'b0;
			spi_qrd <= 1'b0;
			spi_qwr <= 1'b0;
			spi_clk_div_valid <= 1'b0;
			case (write_address)
				4'b0000: begin
					spi_rd <= PWDATA[0];
					spi_wr <= PWDATA[1];
					spi_qrd <= PWDATA[2];
					spi_qwr <= PWDATA[3];
					spi_swrst <= PWDATA[4];
					spi_csreg <= PWDATA[11:8];
				end
				4'b0001: begin
					spi_clk_div <= PWDATA[7:0];
					spi_clk_div_valid <= 1'b1;
				end
				4'b0010: spi_cmd <= PWDATA;
				4'b0011: spi_addr <= PWDATA;
				4'b0100: begin
					spi_cmd_len <= PWDATA[5:0];
					spi_addr_len <= PWDATA[13:8];
					spi_data_len[7:0] <= PWDATA[23:16];
					spi_data_len[15:8] <= PWDATA[31:24];
				end
				4'b0101: begin
					spi_dummy_rd[7:0] <= PWDATA[7:0];
					spi_dummy_rd[15:8] <= PWDATA[15:8];
					spi_dummy_wr[7:0] <= PWDATA[23:16];
					spi_dummy_wr[15:8] <= PWDATA[31:24];
				end
				4'b1001: begin
					spi_int_th_tx <= PWDATA[LOG_BUFFER_DEPTH:0];
					spi_int_th_rx <= PWDATA[8 + LOG_BUFFER_DEPTH:8];
					spi_int_cnt_tx <= PWDATA[16 + LOG_BUFFER_DEPTH:16];
					spi_int_cnt_rx <= PWDATA[24 + LOG_BUFFER_DEPTH:24];
					spi_int_cnt_en <= PWDATA[30];
					spi_int_en <= PWDATA[31];
				end
			endcase
		end
		else begin
			spi_swrst <= 1'b0;
			spi_rd <= 1'b0;
			spi_wr <= 1'b0;
			spi_qrd <= 1'b0;
			spi_qwr <= 1'b0;
			spi_clk_div_valid <= 1'b0;
		end
	always @(*)
		case (read_address)
			4'b0000: PRDATA = spi_status;
			4'b0001: PRDATA = {24'h000000, spi_clk_div};
			4'b0010: PRDATA = spi_cmd;
			4'b0011: PRDATA = spi_addr;
			4'b0100: PRDATA = {spi_data_len, 2'b00, spi_addr_len, 2'b00, spi_cmd_len};
			4'b0101: PRDATA = {spi_dummy_wr, spi_dummy_rd};
			4'b1000: PRDATA = spi_data_rx;
			4'b1001: begin
				PRDATA = 1'sb0;
				PRDATA[LOG_BUFFER_DEPTH:0] = spi_int_th_tx;
				PRDATA[8 + LOG_BUFFER_DEPTH:8] = spi_int_th_rx;
				PRDATA[16 + LOG_BUFFER_DEPTH:16] = spi_int_cnt_tx;
				PRDATA[24 + LOG_BUFFER_DEPTH:24] = spi_int_cnt_rx;
				PRDATA[30] = spi_int_cnt_en;
				PRDATA[31] = spi_int_en;
			end
			default: PRDATA = 1'sb0;
		endcase
	assign spi_data_tx = PWDATA;
	assign spi_data_tx_valid = ((PSEL & PENABLE) & PWRITE) & (write_address == 4'b0110);
	assign spi_data_rx_ready = ((PSEL & PENABLE) & ~PWRITE) & (read_address == 4'b1000);
endmodule
module spi_master_apb_if 
#(
    parameter BUFFER_DEPTH   = 10,
    parameter APB_ADDR_WIDTH = 12,
    parameter LOG_BUFFER_DEPTH = `log2(BUFFER_DEPTH)
)
(
	HCLK,
	HRESETn,
	PADDR,
	PWDATA,
	PWRITE,
	PSEL,
	PENABLE,
	PRDATA,
	PREADY,
	PSLVERR,
	spi_clk_div,
	spi_clk_div_valid,
	spi_status,
	spi_addr,
	spi_addr_len,
	spi_cmd,
	spi_cmd_len,
	spi_csreg,
	spi_data_len,
	spi_dummy_rd,
	spi_dummy_wr,
	spi_int_th_tx,
	spi_int_th_rx,
	spi_int_cnt_tx,
	spi_int_cnt_rx,
	spi_int_en,
	spi_int_cnt_en,
	spi_int_rd_sta,
	spi_swrst,
	spi_rd,
	spi_wr,
	spi_qrd,
	spi_qwr,
	spi_data_tx,
	spi_data_tx_valid,
	spi_data_tx_ready,
	spi_data_rx,
	spi_data_rx_valid,
	spi_data_rx_ready
);




	input wire HCLK;
	input wire HRESETn;
	input wire [APB_ADDR_WIDTH - 1:0] PADDR;
	input wire [31:0] PWDATA;
	input wire PWRITE;
	input wire PSEL;
	input wire PENABLE;
	output reg [31:0] PRDATA;
	output wire PREADY;
	output wire PSLVERR;
	output reg [7:0] spi_clk_div;
	output reg spi_clk_div_valid;
	input wire [31:0] spi_status;
	output reg [31:0] spi_addr;
	output reg [5:0] spi_addr_len;
	output reg [31:0] spi_cmd;
	output reg [5:0] spi_cmd_len;
	output reg [3:0] spi_csreg;
	output reg [15:0] spi_data_len;
	output reg [15:0] spi_dummy_rd;
	output reg [15:0] spi_dummy_wr;
	output reg [LOG_BUFFER_DEPTH:0] spi_int_th_tx;
	output reg [LOG_BUFFER_DEPTH:0] spi_int_th_rx;
	output reg [LOG_BUFFER_DEPTH:0] spi_int_cnt_tx;
	output reg [LOG_BUFFER_DEPTH:0] spi_int_cnt_rx;
	output reg spi_int_en;
	output reg spi_int_cnt_en;
	output wire spi_int_rd_sta;
	output reg spi_swrst;
	output reg spi_rd;
	output reg spi_wr;
	output reg spi_qrd;
	output reg spi_qwr;
	output wire [31:0] spi_data_tx;
	output wire spi_data_tx_valid;
	input wire spi_data_tx_ready;
	input wire [31:0] spi_data_rx;
	input wire spi_data_rx_valid;
	output wire spi_data_rx_ready;
	wire [3:0] write_address;
	wire [3:0] read_address;
	assign write_address = PADDR[5:2];
	assign read_address = PADDR[5:2];
	assign PSLVERR = 1'b0;
	assign PREADY = 1'b1;
	assign spi_int_rd_sta = ((PSEL & PENABLE) & ~PWRITE) & (read_address == 4'b1010);
	always @(posedge HCLK or negedge HRESETn)
		if (HRESETn == 1'b0) begin
			spi_swrst <= 1'b0;
			spi_rd <= 1'b0;
			spi_wr <= 1'b0;
			spi_qrd <= 1'b0;
			spi_qwr <= 1'b0;
			spi_clk_div_valid <= 1'b0;
			spi_clk_div <= 1'sb0;
			spi_cmd <= 1'sb0;
			spi_addr <= 1'sb0;
			spi_cmd_len <= 1'sb0;
			spi_addr_len <= 1'sb0;
			spi_data_len <= 1'sb0;
			spi_dummy_rd <= 1'sb0;
			spi_dummy_wr <= 1'sb0;
			spi_csreg <= 1'sb0;
			spi_int_th_tx <= 1'sb0;
			spi_int_th_rx <= 1'sb0;
			spi_int_cnt_tx <= 1'sb0;
			spi_int_cnt_rx <= 1'sb0;
			spi_int_cnt_en <= 1'b0;
			spi_int_en <= 1'b0;
		end
		else if ((PSEL && PENABLE) && PWRITE) begin
			spi_swrst <= 1'b0;
			spi_rd <= 1'b0;
			spi_wr <= 1'b0;
			spi_qrd <= 1'b0;
			spi_qwr <= 1'b0;
			spi_clk_div_valid <= 1'b0;
			case (write_address)
				4'b0000: begin
					spi_rd <= PWDATA[0];
					spi_wr <= PWDATA[1];
					spi_qrd <= PWDATA[2];
					spi_qwr <= PWDATA[3];
					spi_swrst <= PWDATA[4];
					spi_csreg <= PWDATA[11:8];
				end
				4'b0001: begin
					spi_clk_div <= PWDATA[7:0];
					spi_clk_div_valid <= 1'b1;
				end
				4'b0010: spi_cmd <= PWDATA;
				4'b0011: spi_addr <= PWDATA;
				4'b0100: begin
					spi_cmd_len <= PWDATA[5:0];
					spi_addr_len <= PWDATA[13:8];
					spi_data_len[7:0] <= PWDATA[23:16];
					spi_data_len[15:8] <= PWDATA[31:24];
				end
				4'b0101: begin
					spi_dummy_rd[7:0] <= PWDATA[7:0];
					spi_dummy_rd[15:8] <= PWDATA[15:8];
					spi_dummy_wr[7:0] <= PWDATA[23:16];
					spi_dummy_wr[15:8] <= PWDATA[31:24];
				end
				4'b1001: begin
					spi_int_th_tx <= PWDATA[LOG_BUFFER_DEPTH:0];
					spi_int_th_rx <= PWDATA[8 + LOG_BUFFER_DEPTH:8];
					spi_int_cnt_tx <= PWDATA[16 + LOG_BUFFER_DEPTH:16];
					spi_int_cnt_rx <= PWDATA[24 + LOG_BUFFER_DEPTH:24];
					spi_int_cnt_en <= PWDATA[30];
					spi_int_en <= PWDATA[31];
				end
			endcase
		end
		else begin
			spi_swrst <= 1'b0;
			spi_rd <= 1'b0;
			spi_wr <= 1'b0;
			spi_qrd <= 1'b0;
			spi_qwr <= 1'b0;
			spi_clk_div_valid <= 1'b0;
		end
	always @(*)
		case (read_address)
			4'b0000: PRDATA = spi_status;
			4'b0001: PRDATA = {24'h000000, spi_clk_div};
			4'b0010: PRDATA = spi_cmd;
			4'b0011: PRDATA = spi_addr;
			4'b0100: PRDATA = {spi_data_len, 2'b00, spi_addr_len, 2'b00, spi_cmd_len};
			4'b0101: PRDATA = {spi_dummy_wr, spi_dummy_rd};
			4'b1000: PRDATA = spi_data_rx;
			4'b1001: begin
				PRDATA = 1'sb0;
				PRDATA[LOG_BUFFER_DEPTH:0] = spi_int_th_tx;
				PRDATA[8 + LOG_BUFFER_DEPTH:8] = spi_int_th_rx;
				PRDATA[16 + LOG_BUFFER_DEPTH:16] = spi_int_cnt_tx;
				PRDATA[24 + LOG_BUFFER_DEPTH:24] = spi_int_cnt_rx;
				PRDATA[30] = spi_int_cnt_en;
				PRDATA[31] = spi_int_en;
			end
			default: PRDATA = 1'sb0;
		endcase
	assign spi_data_tx = PWDATA;
	assign spi_data_tx_valid = ((PSEL & PENABLE) & PWRITE) & (write_address == 4'b0110);
	assign spi_data_rx_ready = ((PSEL & PENABLE) & ~PWRITE) & (read_address == 4'b1000);
endmodule