data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo/tb_circular_fifo_rev1.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo/tb_circular_fifo_rev1.v:71: Unsupported: Ignoring delay on this delayed statement.\n    # ( one_clk / 2)    tb_clk  =   ~tb_clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo/tb_circular_fifo_rev1.v:89: Unsupported: Ignoring delay on this delayed statement.\n    # ( 1 * one_clk );\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo/tb_circular_fifo_rev1.v:92: Unsupported: Ignoring delay on this delayed statement.\n    # ( 16 * delay );\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo/tb_circular_fifo_rev1.v:98: Unsupported: Ignoring delay on this delayed statement.\n    # ( 1 * one_clk );\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo/tb_circular_fifo_rev1.v:101: Unsupported: Ignoring delay on this delayed statement.\n    # ( 1 * one_clk );\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo/tb_circular_fifo_rev1.v:104: Unsupported: Ignoring delay on this delayed statement.\n    # ( 1 * one_clk );\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo/tb_circular_fifo_rev1.v:107: Unsupported: Ignoring delay on this delayed statement.\n    # ( 1 * one_clk );\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo/tb_circular_fifo_rev1.v:112: Unsupported: Ignoring delay on this delayed statement.\n    # ( 1 * one_clk );\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo/tb_circular_fifo_rev1.v:116: Unsupported: Ignoring delay on this delayed statement.\n    # ( 2 * one_clk );\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo/tb_circular_fifo_rev1.v:120: Unsupported: Ignoring delay on this delayed statement.\n    # ( 1 * one_clk );\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo/tb_circular_fifo_rev1.v:124: Unsupported: Ignoring delay on this delayed statement.\n    # ( 1 * one_clk );\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo/tb_circular_fifo_rev1.v:128: Unsupported: Ignoring delay on this delayed statement.\n    # ( 1 * one_clk );\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo/tb_circular_fifo_rev1.v:132: Unsupported: Ignoring delay on this delayed statement.\n    # ( 1 * one_clk );\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo/tb_circular_fifo_rev1.v:136: Unsupported: Ignoring delay on this delayed statement.\n    # ( 1 * one_clk );\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo/tb_circular_fifo_rev1.v:140: Unsupported: Ignoring delay on this delayed statement.\n    # ( 1 * one_clk );\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo/tb_circular_fifo_rev1.v:146: Unsupported: Ignoring delay on this delayed statement.\n    # ( 1 * one_clk );\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo/tb_circular_fifo_rev1.v:152: Unsupported: Ignoring delay on this delayed statement.\n    # ( 1 * one_clk );\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo/tb_circular_fifo_rev1.v:158: Unsupported: Ignoring delay on this delayed statement.\n    # ( 2 * one_clk );\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo/tb_circular_fifo_rev1.v:163: Unsupported: Ignoring delay on this delayed statement.\n    # ( 1 * one_clk );\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo/tb_circular_fifo_rev1.v:167: Unsupported: Ignoring delay on this delayed statement.\n  # ( 1 * one_clk );\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo/tb_circular_fifo_rev1.v:171: Unsupported: Ignoring delay on this delayed statement.\n    # ( 1 * one_clk );\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo/tb_circular_fifo_rev1.v:175: Unsupported: Ignoring delay on this delayed statement.\n  # ( 1 * one_clk );\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo/tb_circular_fifo_rev1.v:179: Unsupported: Ignoring delay on this delayed statement.\n    # ( 1 * one_clk );\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo/tb_circular_fifo_rev1.v:183: Unsupported: Ignoring delay on this delayed statement.\n  # ( 1 * one_clk );\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo/tb_circular_fifo_rev1.v:187: Unsupported: Ignoring delay on this delayed statement.\n    # ( 1 * one_clk );\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo/tb_circular_fifo_rev1.v:191: Unsupported: Ignoring delay on this delayed statement.\n  # ( 1 * one_clk );\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo/tb_circular_fifo_rev1.v:198: Unsupported: Ignoring delay on this delayed statement.\n    # ( 3 * one_clk )\n    ^\n%Error: data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo/tb_circular_fifo_rev1.v:40: Cannot find file containing module: \'circular_fifo_rev1\'\ncircular_fifo_rev1 #(\n^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo,data/full_repos/permissive/468612001/circular_fifo_rev1\n             data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo,data/full_repos/permissive/468612001/circular_fifo_rev1.v\n             data/full_repos/permissive/468612001/Project_FIFO_Queue/project_fifo,data/full_repos/permissive/468612001/circular_fifo_rev1.sv\n             circular_fifo_rev1\n             circular_fifo_rev1.v\n             circular_fifo_rev1.sv\n             obj_dir/circular_fifo_rev1\n             obj_dir/circular_fifo_rev1.v\n             obj_dir/circular_fifo_rev1.sv\n%Error: Exiting due to 1 error(s), 27 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_circular_fifo_rev1;




parameter   delay           =   0.1;
parameter   one_clk         =   2.0;

parameter   TB_DATA_WIDTH   =   8;
parameter   TB_ADDR_WIDTH   =   2;
parameter   TB_RAM_DEPTH    =   1 << TB_ADDR_WIDTH;




reg                         tb_clk;
reg                         tb_reset;
reg                         tb_wr_cs;
reg                         tb_wr_en;

reg                         tb_rd_cs;

reg                         tb_rd_en;

reg     [TB_DATA_WIDTH-1:0] tb_data_in;

wire    [TB_DATA_WIDTH-1:0] tb_data_out;
wire                        tb_full;
wire                        tb_empty;

wire	  [TB_ADDR_WIDTH:0]      tb_data_counter;
wire 	  [TB_ADDR_WIDTH-1:0]	 tb_wr_pointer;
wire 	  [TB_ADDR_WIDTH-1:0] 	 tb_rd_pointer;	




circular_fifo_rev1 #(
    .DATA_WIDTH     ( TB_DATA_WIDTH ),
    .ADDR_WIDTH     ( TB_ADDR_WIDTH ),
    .RAM_DEPTH      ( TB_RAM_DEPTH )
)
U0_RAM_SP_SR_SW
(
    .clk            ( tb_clk ),
    .reset          ( tb_reset ),
    .wr_cs          ( tb_wr_cs ),
    .rd_cs          ( tb_rd_cs ),
    .data_in        ( tb_data_in ),
    .rd_en          ( tb_rd_en ),
    .wr_en          ( tb_wr_en ),

    .data_out       ( tb_data_out ),
    .full           ( tb_full ),
    .empty          ( tb_empty ),
	 .data_counter_out(tb_data_counter),
	 .wr_pointer_out(tb_wr_pointer),
	 .rd_pointer_out(tb_rd_pointer)
);







always 
begin
    # ( one_clk / 2)    tb_clk  =   ~tb_clk;
end



initial 
begin
    

    tb_clk      =   1'b1;
    tb_reset    =   1'b1;
    tb_wr_cs    =   1'b0;
    tb_rd_cs    =   1'b0;
    tb_data_in  =   'h0;
    tb_rd_en    =   1'b0;
    tb_wr_en    =   1'b0;
    

    # ( 1 * one_clk );
    tb_reset    =   1'b0;

    # ( 16 * delay );

    tb_wr_cs    =   1'b1;
    tb_wr_en    =   1'b1;
    tb_data_in  =   'hAA;

    # ( 1 * one_clk );
    tb_data_in  =   'hBB;

    # ( 1 * one_clk );
    tb_data_in  =   'hCC;

    # ( 1 * one_clk );
    tb_data_in  =   'hDD;

    # ( 1 * one_clk );
    tb_data_in  =   'hEE;
	 
	 
	 
    # ( 1 * one_clk );
    tb_wr_cs    =   1'b0;
    tb_wr_en    =   1'b0;

    # ( 2 * one_clk );
    tb_rd_cs    =   1'b1;
    tb_rd_en    =   1'b1;

    # ( 1 * one_clk );
    tb_rd_cs    =   1'b0;
    tb_rd_en    =   1'b0;    

    # ( 1 * one_clk );
    tb_rd_cs    =   1'b1;
    tb_rd_en    =   1'b1;

    # ( 1 * one_clk );
    tb_rd_cs    =   1'b0;
    tb_rd_en    =   1'b0;

    # ( 1 * one_clk );
    tb_rd_cs    =   1'b1;
    tb_rd_en    =   1'b1;

    # ( 1 * one_clk );
    tb_rd_cs    =   1'b0;
    tb_rd_en    =   1'b0; 

    # ( 1 * one_clk );
    tb_wr_cs    =   1'b1;
    tb_wr_en    =   1'b1;
    tb_data_in  =   'h77;


    # ( 1 * one_clk );

    tb_data_in  =   'h66;



    # ( 1 * one_clk );

    tb_data_in  =   'h55;



    # ( 2 * one_clk );
    tb_wr_cs    =   1'b0;
    tb_wr_en    =   1'b0;	 
	 
	 
    # ( 1 * one_clk );
    tb_rd_cs    =   1'b1;
    tb_rd_en    =   1'b1;
	 
	 # ( 1 * one_clk );
    tb_rd_cs    =   1'b0;
    tb_rd_en    =   1'b0; 

    # ( 1 * one_clk );
    tb_rd_cs    =   1'b1;
    tb_rd_en    =   1'b1;
	 
	 # ( 1 * one_clk );
    tb_rd_cs    =   1'b0;
    tb_rd_en    =   1'b0; 
	
    # ( 1 * one_clk );
    tb_rd_cs    =   1'b1;
    tb_rd_en    =   1'b1;
	 
	 # ( 1 * one_clk );
    tb_rd_cs    =   1'b0;
    tb_rd_en    =   1'b0; 

    # ( 1 * one_clk );
    tb_rd_cs    =   1'b1;
    tb_rd_en    =   1'b1;
	 
	 # ( 1 * one_clk );
    tb_rd_cs    =   1'b0;
    tb_rd_en    =   1'b0;
	  	 

	 
	 	 	 
    # ( 3 * one_clk )
    $display ( "Simulation end");
    $stop();
end
endmodule
module tb_circular_fifo_rev1;





parameter   delay           =   0.1;
parameter   one_clk         =   2.0;

parameter   TB_DATA_WIDTH   =   8;
parameter   TB_ADDR_WIDTH   =   2;
parameter   TB_RAM_DEPTH    =   1 << TB_ADDR_WIDTH;




reg                         tb_clk;
reg                         tb_reset;
reg                         tb_wr_cs;
reg                         tb_wr_en;

reg                         tb_rd_cs;

reg                         tb_rd_en;

reg     [TB_DATA_WIDTH-1:0] tb_data_in;

wire    [TB_DATA_WIDTH-1:0] tb_data_out;
wire                        tb_full;
wire                        tb_empty;

wire	  [TB_ADDR_WIDTH:0]      tb_data_counter;
wire 	  [TB_ADDR_WIDTH-1:0]	 tb_wr_pointer;
wire 	  [TB_ADDR_WIDTH-1:0] 	 tb_rd_pointer;	




circular_fifo_rev1 #(
    .DATA_WIDTH     ( TB_DATA_WIDTH ),
    .ADDR_WIDTH     ( TB_ADDR_WIDTH ),
    .RAM_DEPTH      ( TB_RAM_DEPTH )
)
U0_RAM_SP_SR_SW
(
    .clk            ( tb_clk ),
    .reset          ( tb_reset ),
    .wr_cs          ( tb_wr_cs ),
    .rd_cs          ( tb_rd_cs ),
    .data_in        ( tb_data_in ),
    .rd_en          ( tb_rd_en ),
    .wr_en          ( tb_wr_en ),

    .data_out       ( tb_data_out ),
    .full           ( tb_full ),
    .empty          ( tb_empty ),
	 .data_counter_out(tb_data_counter),
	 .wr_pointer_out(tb_wr_pointer),
	 .rd_pointer_out(tb_rd_pointer)
);







always 
begin
    # ( one_clk / 2)    tb_clk  =   ~tb_clk;
end



initial 
begin
    

    tb_clk      =   1'b1;
    tb_reset    =   1'b1;
    tb_wr_cs    =   1'b0;
    tb_rd_cs    =   1'b0;
    tb_data_in  =   'h0;
    tb_rd_en    =   1'b0;
    tb_wr_en    =   1'b0;
    

    # ( 1 * one_clk );
    tb_reset    =   1'b0;

    # ( 16 * delay );

    tb_wr_cs    =   1'b1;
    tb_wr_en    =   1'b1;
    tb_data_in  =   'hAA;

    # ( 1 * one_clk );
    tb_data_in  =   'hBB;

    # ( 1 * one_clk );
    tb_data_in  =   'hCC;

    # ( 1 * one_clk );
    tb_data_in  =   'hDD;

    # ( 1 * one_clk );
    tb_data_in  =   'hEE;
	 
	 
	 
    # ( 1 * one_clk );
    tb_wr_cs    =   1'b0;
    tb_wr_en    =   1'b0;

    # ( 2 * one_clk );
    tb_rd_cs    =   1'b1;
    tb_rd_en    =   1'b1;

    # ( 1 * one_clk );
    tb_rd_cs    =   1'b0;
    tb_rd_en    =   1'b0;    

    # ( 1 * one_clk );
    tb_rd_cs    =   1'b1;
    tb_rd_en    =   1'b1;

    # ( 1 * one_clk );
    tb_rd_cs    =   1'b0;
    tb_rd_en    =   1'b0;

    # ( 1 * one_clk );
    tb_rd_cs    =   1'b1;
    tb_rd_en    =   1'b1;

    # ( 1 * one_clk );
    tb_rd_cs    =   1'b0;
    tb_rd_en    =   1'b0; 

    # ( 1 * one_clk );
    tb_wr_cs    =   1'b1;
    tb_wr_en    =   1'b1;
    tb_data_in  =   'h77;


    # ( 1 * one_clk );

    tb_data_in  =   'h66;



    # ( 1 * one_clk );

    tb_data_in  =   'h55;



    # ( 2 * one_clk );
    tb_wr_cs    =   1'b0;
    tb_wr_en    =   1'b0;	 
	 
	 
    # ( 1 * one_clk );
    tb_rd_cs    =   1'b1;
    tb_rd_en    =   1'b1;
	 
	 # ( 1 * one_clk );
    tb_rd_cs    =   1'b0;
    tb_rd_en    =   1'b0; 

    # ( 1 * one_clk );
    tb_rd_cs    =   1'b1;
    tb_rd_en    =   1'b1;
	 
	 # ( 1 * one_clk );
    tb_rd_cs    =   1'b0;
    tb_rd_en    =   1'b0; 
	
    # ( 1 * one_clk );
    tb_rd_cs    =   1'b1;
    tb_rd_en    =   1'b1;
	 
	 # ( 1 * one_clk );
    tb_rd_cs    =   1'b0;
    tb_rd_en    =   1'b0; 

    # ( 1 * one_clk );
    tb_rd_cs    =   1'b1;
    tb_rd_en    =   1'b1;
	 
	 # ( 1 * one_clk );
    tb_rd_cs    =   1'b0;
    tb_rd_en    =   1'b0;
	  	 

	 
	 	 	 
    # ( 3 * one_clk )
    $display ( "Simulation end");
    $stop();
end
endmodule