data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/MICROBENCHMARKS/bm_if_reset.v
data/verilator_xmls/ad333bb9-e529-485a-b0d7-176147168cd8.xml
module a(clock,
		a_in,
		out);

input	clock;
input [`BITS-1:0] a_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;

always @(posedge clock)
begin
	case (a_in)
		2'b00: out <= 2'b11 ;
		2'b01: out <= 2'b10 ;
		2'b10: out <= 2'b01 ;
		2'b11: out <= 2'b00 ;
	endcase
end

endmodule
module a(clock,
		a_in,
		out);


input	clock;
input [`BITS-1:0] a_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;

always @(posedge clock)
begin
	case (a_in)
		2'b00: out <= 2'b11 ;
		2'b01: out <= 2'b10 ;
		2'b10: out <= 2'b01 ;
		2'b11: out <= 2'b00 ;
	endcase
end

endmodule