data/full_repos/permissive/490013975/caravel_edu_tpu/edu_tpu_tb.v
1: b'%Error: data/full_repos/permissive/490013975/caravel_edu_tpu/edu_tpu_tb.v:24: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile ("edu_tpu.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/490013975/caravel_edu_tpu/edu_tpu_tb.v:25: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars (0, edu_tpu_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/490013975/caravel_edu_tpu/edu_tpu_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module edu_tpu_tb;
    initial begin

        $dumpfile ("edu_tpu.vcd");
        $dumpvars (0, edu_tpu_tb);
        #1;
    end

    reg clk;
    reg RSTB;
    reg power1, power2;
    reg power3, power4;

    wire gpio;
    wire [37:0] mprj_io;



    wire dbg_active         = mprj_io[29];
    wire [15:0] out1 = mprj_io[23:8];
    wire [3:0] load_end = mprj_io[27:24];
    wire en         = mprj_io[28];

    

    wire flash_csb;
    wire flash_clk;
    wire flash_io0;
    wire flash_io1;

    wire VDD3V3 = power1;
    wire VDD1V8 = power2;
    wire USER_VDD3V3 = power3;
    wire USER_VDD1V8 = power4;
    wire VSS = 1'b0;

    caravel uut (
        .vddio    (VDD3V3),
        .vssio    (VSS),
        .vdda     (VDD3V3),
        .vssa     (VSS),
        .vccd     (VDD1V8),
        .vssd     (VSS),
        .vdda1    (USER_VDD3V3),
        .vdda2    (USER_VDD3V3),
        .vssa1    (VSS),
        .vssa2    (VSS),
        .vccd1    (USER_VDD1V8),
        .vccd2    (USER_VDD1V8),
        .vssd1    (VSS),
        .vssd2    (VSS),
        .clock    (clk),
        .gpio     (gpio),
        .mprj_io  (mprj_io),
        .flash_csb(flash_csb),
        .flash_clk(flash_clk),
        .flash_io0(flash_io0),
        .flash_io1(flash_io1),
        .resetb   (RSTB)
    );

    spiflash #(

        .FILENAME("edu_tpu.hex")
    ) spiflash (
        .csb(flash_csb),
        .clk(flash_clk),
        .io0(flash_io0),
        .io1(flash_io1),
        .io2(),
        .io3()
    );

endmodule
module edu_tpu_tb;

    initial begin

        $dumpfile ("edu_tpu.vcd");
        $dumpvars (0, edu_tpu_tb);
        #1;
    end

    reg clk;
    reg RSTB;
    reg power1, power2;
    reg power3, power4;

    wire gpio;
    wire [37:0] mprj_io;



    wire dbg_active         = mprj_io[29];
    wire [15:0] out1 = mprj_io[23:8];
    wire [3:0] load_end = mprj_io[27:24];
    wire en         = mprj_io[28];

    

    wire flash_csb;
    wire flash_clk;
    wire flash_io0;
    wire flash_io1;

    wire VDD3V3 = power1;
    wire VDD1V8 = power2;
    wire USER_VDD3V3 = power3;
    wire USER_VDD1V8 = power4;
    wire VSS = 1'b0;

    caravel uut (
        .vddio    (VDD3V3),
        .vssio    (VSS),
        .vdda     (VDD3V3),
        .vssa     (VSS),
        .vccd     (VDD1V8),
        .vssd     (VSS),
        .vdda1    (USER_VDD3V3),
        .vdda2    (USER_VDD3V3),
        .vssa1    (VSS),
        .vssa2    (VSS),
        .vccd1    (USER_VDD1V8),
        .vccd2    (USER_VDD1V8),
        .vssd1    (VSS),
        .vssd2    (VSS),
        .clock    (clk),
        .gpio     (gpio),
        .mprj_io  (mprj_io),
        .flash_csb(flash_csb),
        .flash_clk(flash_clk),
        .flash_io0(flash_io0),
        .flash_io1(flash_io1),
        .resetb   (RSTB)
    );

    spiflash #(

        .FILENAME("edu_tpu.hex")
    ) spiflash (
        .csb(flash_csb),
        .clk(flash_clk),
        .io0(flash_io0),
        .io1(flash_io1),
        .io2(),
        .io3()
    );

endmodule