data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/db_gpio_reordering.v
data/verilator_xmls/c5c0a2cf-d380-4e50-b36f-b00600ef73a2.xml
module db_gpio_reordering (

  output wire [19:0] db0_gpio_in_int,
  input  wire [19:0] db0_gpio_out_int,
  input  wire [19:0] db0_gpio_out_en_int,
  output wire [19:0] db1_gpio_in_int,
  input  wire [19:0] db1_gpio_out_int,
  input  wire [19:0] db1_gpio_out_en_int,


  input  wire [19:0] db0_gpio_in_ext,
  output wire [19:0] db0_gpio_out_ext,
  output wire [19:0] db0_gpio_out_en_ext,
  input  wire [19:0] db1_gpio_in_ext,
  output wire [19:0] db1_gpio_out_ext,
  output wire [19:0] db1_gpio_out_en_ext
);


  localparam ENTRY_BITWIDTH = 5;
  localparam NUM_ENTRIES = 20;
  localparam [ENTRY_BITWIDTH*NUM_ENTRIES-1:0] PORT0_MAPPING = {
    5'd 19,
    5'd 17,
    5'd  0,
    5'd 14,
    5'd 15,
    5'd 10,
    5'd  4,
    5'd  5,
    5'd 16,
    5'd 18,
    5'd  8,
    5'd  6,
    5'd  1,
    5'd  9,
    5'd  2,
    5'd  3,
    5'd 11,
    5'd  7,
    5'd 13,
    5'd 12 };
  localparam [ENTRY_BITWIDTH*NUM_ENTRIES-1:0] PORT1_MAPPING = {
    5'd 10,
    5'd  6,
    5'd  7,
    5'd  2,
    5'd  3,
    5'd  0,
    5'd  1,
    5'd  4,
    5'd  8,
    5'd  9,
    5'd 11,
    5'd  5,
    5'd 13,
    5'd 12,
    5'd 15,
    5'd 14,
    5'd 19,
    5'd 18,
    5'd 17,
    5'd 16 };


  generate
    genvar i;
    for (i=0; i<NUM_ENTRIES; i=i+1) begin : reordering_gen

      assign db0_gpio_in_int[i] = db0_gpio_in_ext[PORT0_MAPPING[i*ENTRY_BITWIDTH +: ENTRY_BITWIDTH]];
      assign db1_gpio_in_int[i] = db1_gpio_in_ext[PORT1_MAPPING[i*ENTRY_BITWIDTH +: ENTRY_BITWIDTH]];


      assign db0_gpio_out_ext[PORT0_MAPPING[i*ENTRY_BITWIDTH +: ENTRY_BITWIDTH]] = db0_gpio_out_int[i];
      assign db1_gpio_out_ext[PORT1_MAPPING[i*ENTRY_BITWIDTH +: ENTRY_BITWIDTH]] = db1_gpio_out_int[i];


      assign db0_gpio_out_en_ext[PORT0_MAPPING[i*ENTRY_BITWIDTH +: ENTRY_BITWIDTH]] = db0_gpio_out_en_int[i];
      assign db1_gpio_out_en_ext[PORT1_MAPPING[i*ENTRY_BITWIDTH +: ENTRY_BITWIDTH]] = db1_gpio_out_en_int[i];
    end
  endgenerate
endmodule
module db_gpio_reordering (

  output wire [19:0] db0_gpio_in_int,
  input  wire [19:0] db0_gpio_out_int,
  input  wire [19:0] db0_gpio_out_en_int,
  output wire [19:0] db1_gpio_in_int,
  input  wire [19:0] db1_gpio_out_int,
  input  wire [19:0] db1_gpio_out_en_int,


  input  wire [19:0] db0_gpio_in_ext,
  output wire [19:0] db0_gpio_out_ext,
  output wire [19:0] db0_gpio_out_en_ext,
  input  wire [19:0] db1_gpio_in_ext,
  output wire [19:0] db1_gpio_out_ext,
  output wire [19:0] db1_gpio_out_en_ext
);



  localparam ENTRY_BITWIDTH = 5;
  localparam NUM_ENTRIES = 20;
  localparam [ENTRY_BITWIDTH*NUM_ENTRIES-1:0] PORT0_MAPPING = {
    5'd 19,
    5'd 17,
    5'd  0,
    5'd 14,
    5'd 15,
    5'd 10,
    5'd  4,
    5'd  5,
    5'd 16,
    5'd 18,
    5'd  8,
    5'd  6,
    5'd  1,
    5'd  9,
    5'd  2,
    5'd  3,
    5'd 11,
    5'd  7,
    5'd 13,
    5'd 12 };
  localparam [ENTRY_BITWIDTH*NUM_ENTRIES-1:0] PORT1_MAPPING = {
    5'd 10,
    5'd  6,
    5'd  7,
    5'd  2,
    5'd  3,
    5'd  0,
    5'd  1,
    5'd  4,
    5'd  8,
    5'd  9,
    5'd 11,
    5'd  5,
    5'd 13,
    5'd 12,
    5'd 15,
    5'd 14,
    5'd 19,
    5'd 18,
    5'd 17,
    5'd 16 };


  generate
    genvar i;
    for (i=0; i<NUM_ENTRIES; i=i+1) begin : reordering_gen

      assign db0_gpio_in_int[i] = db0_gpio_in_ext[PORT0_MAPPING[i*ENTRY_BITWIDTH +: ENTRY_BITWIDTH]];
      assign db1_gpio_in_int[i] = db1_gpio_in_ext[PORT1_MAPPING[i*ENTRY_BITWIDTH +: ENTRY_BITWIDTH]];


      assign db0_gpio_out_ext[PORT0_MAPPING[i*ENTRY_BITWIDTH +: ENTRY_BITWIDTH]] = db0_gpio_out_int[i];
      assign db1_gpio_out_ext[PORT1_MAPPING[i*ENTRY_BITWIDTH +: ENTRY_BITWIDTH]] = db1_gpio_out_int[i];


      assign db0_gpio_out_en_ext[PORT0_MAPPING[i*ENTRY_BITWIDTH +: ENTRY_BITWIDTH]] = db0_gpio_out_en_int[i];
      assign db1_gpio_out_en_ext[PORT1_MAPPING[i*ENTRY_BITWIDTH +: ENTRY_BITWIDTH]] = db1_gpio_out_en_int[i];
    end
  endgenerate
endmodule