data/full_repos/permissive/472586361/humanmachine/PC.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/472586361/humanmachine/PC.v:15: Unsupported: Ignoring delay on this delayed statement.\n        #delaytime count1 <= 2\'b00;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/472586361/humanmachine/PC.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #delaytime count2 <= 2\'b00;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/472586361/humanmachine/PC.v:22: Unsupported: Ignoring delay on this delayed statement.\n            #delaytime count1 <= 2\'b00;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/472586361/humanmachine/PC.v:23: Unsupported: Ignoring delay on this delayed statement.\n            #delaytime count2 <= count2+1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/472586361/humanmachine/PC.v:27: Unsupported: Ignoring delay on this delayed statement.\n            #delaytime count1 <= count1+1;\n            ^\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module PC(input clk, input rst, input enable, input [3:0] jmploc, input jmp, output reg [1:0] count1,output reg [1:0]count2);
wire CLK;
parameter delaytime=5;
assign CLK = (clk & enable);
initial begin
    count1 <= 2'b00;
    count2 <= 2'b00;
end
always @(posedge CLK)
begin
    if(rst)
    begin
        #delaytime count1 <= 2'b00;
        #delaytime count2 <= 2'b00;
    end
    else
    begin
        if(count1==2'b11)
        begin
            #delaytime count1 <= 2'b00;
            #delaytime count2 <= count2+1;
        end
        else 
            begin
            #delaytime count1 <= count1+1;
            end
        end
    end


endmodule
module PC(input clk, input rst, input enable, input [3:0] jmploc, input jmp, output reg [1:0] count1,output reg [1:0]count2);

wire CLK;
parameter delaytime=5;
assign CLK = (clk & enable);
initial begin
    count1 <= 2'b00;
    count2 <= 2'b00;
end
always @(posedge CLK)
begin
    if(rst)
    begin
        #delaytime count1 <= 2'b00;
        #delaytime count2 <= 2'b00;
    end
    else
    begin
        if(count1==2'b11)
        begin
            #delaytime count1 <= 2'b00;
            #delaytime count2 <= count2+1;
        end
        else 
            begin
            #delaytime count1 <= count1+1;
            end
        end
    end


endmodule