data/full_repos/permissive/493441306/Verilog Language/procedures/00_alwaysblock1.v
1: b'%Error: Cannot find file containing module: Language/procedures,data/full_repos/permissive/493441306\n        ... Looked in:\n             data/full_repos/permissive/493441306/Verilog/Language/procedures,data/full_repos/permissive/493441306\n             data/full_repos/permissive/493441306/Verilog/Language/procedures,data/full_repos/permissive/493441306.v\n             data/full_repos/permissive/493441306/Verilog/Language/procedures,data/full_repos/permissive/493441306.sv\n             Language/procedures,data/full_repos/permissive/493441306\n             Language/procedures,data/full_repos/permissive/493441306.v\n             Language/procedures,data/full_repos/permissive/493441306.sv\n             obj_dir/Language/procedures,data/full_repos/permissive/493441306\n             obj_dir/Language/procedures,data/full_repos/permissive/493441306.v\n             obj_dir/Language/procedures,data/full_repos/permissive/493441306.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/493441306/Verilog\n%Error: Cannot find file containing module: Language/procedures/00_alwaysblock1.v\n%Error: Exiting due to 3 error(s)\n'
module top_module(
    input a, 
    input b,
    output wire out_assign,
    output reg out_alwaysblock
);

    assign out_assign = a & b;

    always@(*)


        out_alwaysblock = out_assign;

endmodule
module top_module(
    input a, 
    input b,
    output wire out_assign,
    output reg out_alwaysblock
);


    assign out_assign = a & b;

    always@(*)


        out_alwaysblock = out_assign;

endmodule