data/full_repos/permissive/445379100/a4/branch_controller_ALU.v
data/verilator_xmls/aa6d1c54-b8b8-40e3-8d74-60f138393cfa.xml
module branch_controller_ALU (
    input is_branch_type ,
    input jal ,
    input auipc ,
    input is_conditional_branch_type ,
    input [31:0] input_iaddr ,
    input [31:0] alu_out ,
    input [31:0] branch_condition ,
    input [31:0] input_imm12_ext ,
    output reg [31:0] next_addr_branch ,
    output reg take_branch
);
    always @(*) begin
        if ( is_branch_type ) begin
            if ( is_conditional_branch_type == 0 ) begin
                next_addr_branch = alu_out ;
                take_branch = 1 ; 

            end

            else if ( is_conditional_branch_type == 1 && alu_out == branch_condition ) begin  
                next_addr_branch = input_iaddr + (input_imm12_ext<<1) ;
                take_branch = 1 ;  
            end

            else begin
                next_addr_branch = 0 ;
                take_branch = 0 ;  
            end
        end

        else if (auipc == 1'b1) begin
            next_addr_branch = input_iaddr + input_imm12_ext ;
            take_branch = 0 ;
        end

        else if (jal == 1'b1) begin
            next_addr_branch = input_iaddr + (input_imm12_ext<<1) ;
            take_branch = 1 ;  
        end

        else begin
            next_addr_branch = 0 ;  
            take_branch = 0 ;
        end    
    end  
endmodule
module branch_controller_ALU (
    input is_branch_type ,
    input jal ,
    input auipc ,
    input is_conditional_branch_type ,
    input [31:0] input_iaddr ,
    input [31:0] alu_out ,
    input [31:0] branch_condition ,
    input [31:0] input_imm12_ext ,
    output reg [31:0] next_addr_branch ,
    output reg take_branch
);

    always @(*) begin
        if ( is_branch_type ) begin
            if ( is_conditional_branch_type == 0 ) begin
                next_addr_branch = alu_out ;
                take_branch = 1 ; 

            end

            else if ( is_conditional_branch_type == 1 && alu_out == branch_condition ) begin  
                next_addr_branch = input_iaddr + (input_imm12_ext<<1) ;
                take_branch = 1 ;  
            end

            else begin
                next_addr_branch = 0 ;
                take_branch = 0 ;  
            end
        end

        else if (auipc == 1'b1) begin
            next_addr_branch = input_iaddr + input_imm12_ext ;
            take_branch = 0 ;
        end

        else if (jal == 1'b1) begin
            next_addr_branch = input_iaddr + (input_imm12_ext<<1) ;
            take_branch = 1 ;  
        end

        else begin
            next_addr_branch = 0 ;  
            take_branch = 0 ;
        end    
    end  
endmodule