data/full_repos/permissive/474275312/Day 2/counter/counter_tb.v
1: b'%Error: Cannot find file containing module: 2/counter,data/full_repos/permissive/474275312\n        ... Looked in:\n             data/full_repos/permissive/474275312/Day/2/counter,data/full_repos/permissive/474275312\n             data/full_repos/permissive/474275312/Day/2/counter,data/full_repos/permissive/474275312.v\n             data/full_repos/permissive/474275312/Day/2/counter,data/full_repos/permissive/474275312.sv\n             2/counter,data/full_repos/permissive/474275312\n             2/counter,data/full_repos/permissive/474275312.v\n             2/counter,data/full_repos/permissive/474275312.sv\n             obj_dir/2/counter,data/full_repos/permissive/474275312\n             obj_dir/2/counter,data/full_repos/permissive/474275312.v\n             obj_dir/2/counter,data/full_repos/permissive/474275312.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/474275312/Day\n%Error: Cannot find file containing module: 2/counter/counter_tb.v\n%Error: Exiting due to 3 error(s)\n'
module upcounter_testbench();

reg clk, reset, enable;
wire [3:0] out;



up_counter dut(enable, clk, reset, out[0], out[1], out[2], out[3]);


initial $sdf_annotate("/home/nanditha/Documents/fpga/osfpga/vtr_work/quickstart/counter_gui_earch/post_synth/up_counter_post_synthesis.sdf", dut);

initial begin




clk=0;
enable=0;
reset=1;

#20;
reset=0;
enable=1;

end


always 
#5 clk=~clk;


endmodule
module upcounter_testbench();


reg clk, reset, enable;
wire [3:0] out;



up_counter dut(enable, clk, reset, out[0], out[1], out[2], out[3]);


initial $sdf_annotate("/home/nanditha/Documents/fpga/osfpga/vtr_work/quickstart/counter_gui_earch/post_synth/up_counter_post_synthesis.sdf", dut);

initial begin




clk=0;
enable=0;
reset=1;

#20;
reset=0;
enable=1;

end


always 
#5 clk=~clk;


endmodule