data/full_repos/permissive/411838135/rv/synth/vsram.v
1: b'%Error: No top level module found\n%Error: Exiting due to 1 error(s)\n'
module sd_out_fifo(
	input		reset,
	input 		wr_clk,
	input  		wr_en,
	input	  [63:0]din,
	output		full,

	input		rd_clk,
	input		rd_en,
	output		empty,
	output    [63:0]dout
	);

	reg r_empty;
	reg r_full;
	assign full=r_full;
	assign empty = r_empty;

	reg [63:0]r_mem[0:(256/(64/8))-1];
	reg [$clog2((256/(64/8)))-1:0]r_inp;
	reg [$clog2((256/(64/8)))-1:0]r_outp;

	assign dout=r_mem[r_outp];

	wire [$clog2((256/(64/8)))-1:0]in_inc = r_inp+1;
	always @(posedge wr_clk) 
	if (reset) begin
		r_inp <= 0;
		r_full <= 0;
	end else begin
		if (wr_en) begin
			r_mem[r_inp] <= din;
			r_inp <= in_inc;
			r_full <= (in_inc == r_outp);
		end else begin
			r_full <= r_full&&(r_inp==r_outp);
		end
	end

	wire [$clog2((256/(64/8)))-1:0]out_inc = r_outp+1;
	always @(posedge rd_clk) 
	if (reset) begin
		r_outp <= 0;
		r_empty <= 1;
	end else begin
		if (rd_en) begin
			r_outp <= out_inc;
			r_empty <= out_inc == r_inp;
		end else begin
			r_empty <= r_empty&&(r_inp==r_outp);
		end
	end
	

endmodule
module sd_out_fifo(
	input		reset,
	input 		wr_clk,
	input  		wr_en,
	input	  [63:0]din,
	output		full,

	input		rd_clk,
	input		rd_en,
	output		empty,
	output    [63:0]dout
	);


	reg r_empty;
	reg r_full;
	assign full=r_full;
	assign empty = r_empty;

	reg [63:0]r_mem[0:(256/(64/8))-1];
	reg [$clog2((256/(64/8)))-1:0]r_inp;
	reg [$clog2((256/(64/8)))-1:0]r_outp;

	assign dout=r_mem[r_outp];

	wire [$clog2((256/(64/8)))-1:0]in_inc = r_inp+1;
	always @(posedge wr_clk) 
	if (reset) begin
		r_inp <= 0;
		r_full <= 0;
	end else begin
		if (wr_en) begin
			r_mem[r_inp] <= din;
			r_inp <= in_inc;
			r_full <= (in_inc == r_outp);
		end else begin
			r_full <= r_full&&(r_inp==r_outp);
		end
	end

	wire [$clog2((256/(64/8)))-1:0]out_inc = r_outp+1;
	always @(posedge rd_clk) 
	if (reset) begin
		r_outp <= 0;
		r_empty <= 1;
	end else begin
		if (rd_en) begin
			r_outp <= out_inc;
			r_empty <= out_inc == r_inp;
		end else begin
			r_empty <= r_empty&&(r_inp==r_outp);
		end
	end
	

endmodule