data/full_repos/permissive/437632408/NVDLA/nvdla/bdma/NV_NVDLA_bdma.v
1: b"%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/bdma/NV_NVDLA_bdma.v:121: Cannot find file containing module: 'NV_NVDLA_BDMA_csb'\nNV_NVDLA_BDMA_csb u_csb (\n^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/437632408/NVDLA/nvdla/bdma,data/full_repos/permissive/437632408/NV_NVDLA_BDMA_csb\n             data/full_repos/permissive/437632408/NVDLA/nvdla/bdma,data/full_repos/permissive/437632408/NV_NVDLA_BDMA_csb.v\n             data/full_repos/permissive/437632408/NVDLA/nvdla/bdma,data/full_repos/permissive/437632408/NV_NVDLA_BDMA_csb.sv\n             NV_NVDLA_BDMA_csb\n             NV_NVDLA_BDMA_csb.v\n             NV_NVDLA_BDMA_csb.sv\n             obj_dir/NV_NVDLA_BDMA_csb\n             obj_dir/NV_NVDLA_BDMA_csb.v\n             obj_dir/NV_NVDLA_BDMA_csb.sv\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/bdma/NV_NVDLA_bdma.v:158: Cannot find file containing module: 'NV_NVDLA_BDMA_gate'\nNV_NVDLA_BDMA_gate u_gate (\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/bdma/NV_NVDLA_bdma.v:169: Cannot find file containing module: 'NV_NVDLA_BDMA_load'\nNV_NVDLA_BDMA_load u_load (\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/bdma/NV_NVDLA_bdma.v:205: Cannot find file containing module: 'NV_NVDLA_BDMA_store'\nNV_NVDLA_BDMA_store u_store (\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/bdma/NV_NVDLA_bdma.v:236: Cannot find file containing module: 'NV_NVDLA_BDMA_cq'\nNV_NVDLA_BDMA_cq u_cq (\n^~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module NV_NVDLA_bdma (
   bdma2cvif_rd_req_ready
  ,bdma2cvif_wr_req_ready
  ,bdma2mcif_rd_req_ready
  ,bdma2mcif_wr_req_ready
  ,csb2bdma_req_pd
  ,csb2bdma_req_pvld
  ,cvif2bdma_rd_rsp_pd
  ,cvif2bdma_rd_rsp_valid
  ,cvif2bdma_wr_rsp_complete
  ,dla_clk_ovr_on_sync
  ,global_clk_ovr_on_sync
  ,mcif2bdma_rd_rsp_pd
  ,mcif2bdma_rd_rsp_valid
  ,mcif2bdma_wr_rsp_complete
  ,nvdla_core_clk
  ,nvdla_core_rstn
  ,pwrbus_ram_pd
  ,tmc2slcg_disable_clock_gating
  ,bdma2csb_resp_pd
  ,bdma2csb_resp_valid
  ,bdma2cvif_rd_cdt_lat_fifo_pop
  ,bdma2cvif_rd_req_pd
  ,bdma2cvif_rd_req_valid
  ,bdma2cvif_wr_req_pd
  ,bdma2cvif_wr_req_valid
  ,bdma2glb_done_intr_pd
  ,bdma2mcif_rd_cdt_lat_fifo_pop
  ,bdma2mcif_rd_req_pd
  ,bdma2mcif_rd_req_valid
  ,bdma2mcif_wr_req_pd
  ,bdma2mcif_wr_req_valid
  ,csb2bdma_req_prdy
  ,cvif2bdma_rd_rsp_ready
  ,mcif2bdma_rd_rsp_ready
  );



input nvdla_core_clk;
input nvdla_core_rstn;
output bdma2csb_resp_valid;
output [33:0] bdma2csb_resp_pd;
output bdma2cvif_rd_cdt_lat_fifo_pop;
output bdma2cvif_rd_req_valid;
input bdma2cvif_rd_req_ready;
output [78:0] bdma2cvif_rd_req_pd;
output bdma2cvif_wr_req_valid;
input bdma2cvif_wr_req_ready;
output [514:0] bdma2cvif_wr_req_pd;
output [1:0] bdma2glb_done_intr_pd;
output bdma2mcif_rd_cdt_lat_fifo_pop;
output bdma2mcif_rd_req_valid;
input bdma2mcif_rd_req_ready;
output [78:0] bdma2mcif_rd_req_pd;
output bdma2mcif_wr_req_valid;
input bdma2mcif_wr_req_ready;
output [514:0] bdma2mcif_wr_req_pd;
input csb2bdma_req_pvld;
output csb2bdma_req_prdy;
input [62:0] csb2bdma_req_pd;
input cvif2bdma_rd_rsp_valid;
output cvif2bdma_rd_rsp_ready;
input [513:0] cvif2bdma_rd_rsp_pd;
input cvif2bdma_wr_rsp_complete;
input mcif2bdma_rd_rsp_valid;
output mcif2bdma_rd_rsp_ready;
input [513:0] mcif2bdma_rd_rsp_pd;
input mcif2bdma_wr_rsp_complete;
input [31:0] pwrbus_ram_pd;

input dla_clk_ovr_on_sync;
input global_clk_ovr_on_sync;
input tmc2slcg_disable_clock_gating;
wire csb2gate_slcg_en;
wire csb2ld_rdy;
wire csb2ld_vld;
wire [31:0] dma_write_stall_count;
wire dma_write_stall_count_cen;
wire ld2csb_grp0_dma_stall_inc;
wire ld2csb_grp1_dma_stall_inc;
wire ld2csb_idle;
wire ld2gate_slcg_en;
wire [160:0] ld2st_rd_pd;
wire ld2st_rd_prdy;
wire ld2st_rd_pvld;
wire ld2st_wr_idle;
wire [160:0] ld2st_wr_pd;
wire ld2st_wr_prdy;
wire ld2st_wr_pvld;
wire nvdla_gated_clk;
wire reg2dp_cmd_dst_ram_type;
wire reg2dp_cmd_interrupt;
wire reg2dp_cmd_interrupt_ptr;
wire reg2dp_cmd_src_ram_type;
wire [31:0] reg2dp_dst_addr_high_v8;
wire [26:0] reg2dp_dst_addr_low_v32;
wire [26:0] reg2dp_dst_line_stride;
wire [26:0] reg2dp_dst_surf_stride;
wire [23:0] reg2dp_line_repeat_number;
wire [12:0] reg2dp_line_size;
wire [31:0] reg2dp_src_addr_high_v8;
wire [26:0] reg2dp_src_addr_low_v32;
wire [26:0] reg2dp_src_line_stride;
wire [26:0] reg2dp_src_surf_stride;
wire [23:0] reg2dp_surf_repeat_number;
wire st2csb_grp0_done;
wire st2csb_grp1_done;
wire st2csb_idle;
wire st2gate_slcg_en;
wire st2ld_load_idle;

NV_NVDLA_BDMA_csb u_csb (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.csb2bdma_req_pvld (csb2bdma_req_pvld)
  ,.csb2bdma_req_prdy (csb2bdma_req_prdy)
  ,.csb2bdma_req_pd (csb2bdma_req_pd[62:0])
  ,.bdma2csb_resp_valid (bdma2csb_resp_valid)
  ,.bdma2csb_resp_pd (bdma2csb_resp_pd[33:0])
  ,.bdma2glb_done_intr_pd (bdma2glb_done_intr_pd[1:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  ,.st2csb_grp0_done (st2csb_grp0_done)
  ,.st2csb_grp1_done (st2csb_grp1_done)
  ,.st2csb_idle (st2csb_idle)
  ,.reg2dp_cmd_dst_ram_type (reg2dp_cmd_dst_ram_type)
  ,.reg2dp_cmd_interrupt (reg2dp_cmd_interrupt)
  ,.reg2dp_cmd_interrupt_ptr (reg2dp_cmd_interrupt_ptr)
  ,.reg2dp_cmd_src_ram_type (reg2dp_cmd_src_ram_type)
  ,.reg2dp_dst_addr_high_v8 (reg2dp_dst_addr_high_v8[31:0])
  ,.reg2dp_dst_addr_low_v32 (reg2dp_dst_addr_low_v32[26:0])
  ,.reg2dp_dst_line_stride (reg2dp_dst_line_stride[26:0])
  ,.reg2dp_dst_surf_stride (reg2dp_dst_surf_stride[26:0])
  ,.reg2dp_line_repeat_number (reg2dp_line_repeat_number[23:0])
  ,.reg2dp_line_size (reg2dp_line_size[12:0])
  ,.reg2dp_src_addr_high_v8 (reg2dp_src_addr_high_v8[31:0])
  ,.reg2dp_src_addr_low_v32 (reg2dp_src_addr_low_v32[26:0])
  ,.reg2dp_src_line_stride (reg2dp_src_line_stride[26:0])
  ,.reg2dp_src_surf_stride (reg2dp_src_surf_stride[26:0])
  ,.reg2dp_surf_repeat_number (reg2dp_surf_repeat_number[23:0])
  ,.csb2ld_rdy (csb2ld_rdy)
  ,.ld2csb_grp0_dma_stall_inc (ld2csb_grp0_dma_stall_inc)
  ,.ld2csb_grp1_dma_stall_inc (ld2csb_grp1_dma_stall_inc)
  ,.ld2csb_idle (ld2csb_idle)
  ,.csb2ld_vld (csb2ld_vld)
  ,.csb2gate_slcg_en (csb2gate_slcg_en)
  ,.dma_write_stall_count (dma_write_stall_count[31:0])
  ,.dma_write_stall_count_cen (dma_write_stall_count_cen)
  );
NV_NVDLA_BDMA_gate u_gate (
   .csb2gate_slcg_en (csb2gate_slcg_en)
  ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync)
  ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync)
  ,.ld2gate_slcg_en (ld2gate_slcg_en)
  ,.nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.st2gate_slcg_en (st2gate_slcg_en)
  ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating)
  ,.nvdla_gated_clk (nvdla_gated_clk)
  );
NV_NVDLA_BDMA_load u_load (
   .nvdla_core_clk (nvdla_gated_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.bdma2mcif_rd_req_valid (bdma2mcif_rd_req_valid)
  ,.bdma2mcif_rd_req_ready (bdma2mcif_rd_req_ready)
  ,.bdma2mcif_rd_req_pd (bdma2mcif_rd_req_pd[78:0])
  ,.bdma2cvif_rd_req_valid (bdma2cvif_rd_req_valid)
  ,.bdma2cvif_rd_req_ready (bdma2cvif_rd_req_ready)
  ,.bdma2cvif_rd_req_pd (bdma2cvif_rd_req_pd[78:0])
  ,.ld2st_wr_pvld (ld2st_wr_pvld)
  ,.ld2st_wr_prdy (ld2st_wr_prdy)
  ,.ld2st_wr_pd (ld2st_wr_pd[160:0])
  ,.reg2dp_cmd_dst_ram_type (reg2dp_cmd_dst_ram_type)
  ,.reg2dp_cmd_interrupt (reg2dp_cmd_interrupt)
  ,.reg2dp_cmd_interrupt_ptr (reg2dp_cmd_interrupt_ptr)
  ,.reg2dp_cmd_src_ram_type (reg2dp_cmd_src_ram_type)
  ,.reg2dp_dst_addr_high_v8 (reg2dp_dst_addr_high_v8[31:0])
  ,.reg2dp_dst_addr_low_v32 (reg2dp_dst_addr_low_v32[26:0])
  ,.reg2dp_dst_line_stride (reg2dp_dst_line_stride[26:0])
  ,.reg2dp_dst_surf_stride (reg2dp_dst_surf_stride[26:0])
  ,.reg2dp_line_repeat_number (reg2dp_line_repeat_number[23:0])
  ,.reg2dp_line_size (reg2dp_line_size[12:0])
  ,.reg2dp_src_addr_high_v8 (reg2dp_src_addr_high_v8[31:0])
  ,.reg2dp_src_addr_low_v32 (reg2dp_src_addr_low_v32[26:0])
  ,.reg2dp_src_line_stride (reg2dp_src_line_stride[26:0])
  ,.reg2dp_src_surf_stride (reg2dp_src_surf_stride[26:0])
  ,.reg2dp_surf_repeat_number (reg2dp_surf_repeat_number[23:0])
  ,.csb2ld_vld (csb2ld_vld)
  ,.csb2ld_rdy (csb2ld_rdy)
  ,.ld2csb_grp0_dma_stall_inc (ld2csb_grp0_dma_stall_inc)
  ,.ld2csb_grp1_dma_stall_inc (ld2csb_grp1_dma_stall_inc)
  ,.ld2csb_idle (ld2csb_idle)
  ,.ld2st_wr_idle (ld2st_wr_idle)
  ,.st2ld_load_idle (st2ld_load_idle)
  ,.ld2gate_slcg_en (ld2gate_slcg_en)
  );
NV_NVDLA_BDMA_store u_store (
   .nvdla_core_clk (nvdla_gated_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.mcif2bdma_rd_rsp_valid (mcif2bdma_rd_rsp_valid)
  ,.mcif2bdma_rd_rsp_ready (mcif2bdma_rd_rsp_ready)
  ,.mcif2bdma_rd_rsp_pd (mcif2bdma_rd_rsp_pd[513:0])
  ,.cvif2bdma_rd_rsp_valid (cvif2bdma_rd_rsp_valid)
  ,.cvif2bdma_rd_rsp_ready (cvif2bdma_rd_rsp_ready)
  ,.cvif2bdma_rd_rsp_pd (cvif2bdma_rd_rsp_pd[513:0])
  ,.bdma2mcif_rd_cdt_lat_fifo_pop (bdma2mcif_rd_cdt_lat_fifo_pop)
  ,.bdma2cvif_rd_cdt_lat_fifo_pop (bdma2cvif_rd_cdt_lat_fifo_pop)
  ,.bdma2mcif_wr_req_valid (bdma2mcif_wr_req_valid)
  ,.bdma2mcif_wr_req_ready (bdma2mcif_wr_req_ready)
  ,.bdma2mcif_wr_req_pd (bdma2mcif_wr_req_pd[514:0])
  ,.bdma2cvif_wr_req_valid (bdma2cvif_wr_req_valid)
  ,.bdma2cvif_wr_req_ready (bdma2cvif_wr_req_ready)
  ,.bdma2cvif_wr_req_pd (bdma2cvif_wr_req_pd[514:0])
  ,.mcif2bdma_wr_rsp_complete (mcif2bdma_wr_rsp_complete)
  ,.cvif2bdma_wr_rsp_complete (cvif2bdma_wr_rsp_complete)
  ,.ld2st_rd_pvld (ld2st_rd_pvld)
  ,.ld2st_rd_prdy (ld2st_rd_prdy)
  ,.ld2st_rd_pd (ld2st_rd_pd[160:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  ,.st2ld_load_idle (st2ld_load_idle)
  ,.st2csb_grp0_done (st2csb_grp0_done)
  ,.st2csb_grp1_done (st2csb_grp1_done)
  ,.st2csb_idle (st2csb_idle)
  ,.st2gate_slcg_en (st2gate_slcg_en)
  ,.dma_write_stall_count (dma_write_stall_count[31:0])
  ,.dma_write_stall_count_cen (dma_write_stall_count_cen)
  );
NV_NVDLA_BDMA_cq u_cq (
   .nvdla_core_clk (nvdla_gated_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.ld2st_wr_prdy (ld2st_wr_prdy)
  ,.ld2st_wr_idle (ld2st_wr_idle)
  ,.ld2st_wr_pvld (ld2st_wr_pvld)
  ,.ld2st_wr_pd (ld2st_wr_pd[160:0])
  ,.ld2st_rd_prdy (ld2st_rd_prdy)
  ,.ld2st_rd_pvld (ld2st_rd_pvld)
  ,.ld2st_rd_pd (ld2st_rd_pd[160:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  );
endmodule
module NV_NVDLA_bdma (
   bdma2cvif_rd_req_ready
  ,bdma2cvif_wr_req_ready
  ,bdma2mcif_rd_req_ready
  ,bdma2mcif_wr_req_ready
  ,csb2bdma_req_pd
  ,csb2bdma_req_pvld
  ,cvif2bdma_rd_rsp_pd
  ,cvif2bdma_rd_rsp_valid
  ,cvif2bdma_wr_rsp_complete
  ,dla_clk_ovr_on_sync
  ,global_clk_ovr_on_sync
  ,mcif2bdma_rd_rsp_pd
  ,mcif2bdma_rd_rsp_valid
  ,mcif2bdma_wr_rsp_complete
  ,nvdla_core_clk
  ,nvdla_core_rstn
  ,pwrbus_ram_pd
  ,tmc2slcg_disable_clock_gating
  ,bdma2csb_resp_pd
  ,bdma2csb_resp_valid
  ,bdma2cvif_rd_cdt_lat_fifo_pop
  ,bdma2cvif_rd_req_pd
  ,bdma2cvif_rd_req_valid
  ,bdma2cvif_wr_req_pd
  ,bdma2cvif_wr_req_valid
  ,bdma2glb_done_intr_pd
  ,bdma2mcif_rd_cdt_lat_fifo_pop
  ,bdma2mcif_rd_req_pd
  ,bdma2mcif_rd_req_valid
  ,bdma2mcif_wr_req_pd
  ,bdma2mcif_wr_req_valid
  ,csb2bdma_req_prdy
  ,cvif2bdma_rd_rsp_ready
  ,mcif2bdma_rd_rsp_ready
  );




input nvdla_core_clk;
input nvdla_core_rstn;
output bdma2csb_resp_valid;
output [33:0] bdma2csb_resp_pd;
output bdma2cvif_rd_cdt_lat_fifo_pop;
output bdma2cvif_rd_req_valid;
input bdma2cvif_rd_req_ready;
output [78:0] bdma2cvif_rd_req_pd;
output bdma2cvif_wr_req_valid;
input bdma2cvif_wr_req_ready;
output [514:0] bdma2cvif_wr_req_pd;
output [1:0] bdma2glb_done_intr_pd;
output bdma2mcif_rd_cdt_lat_fifo_pop;
output bdma2mcif_rd_req_valid;
input bdma2mcif_rd_req_ready;
output [78:0] bdma2mcif_rd_req_pd;
output bdma2mcif_wr_req_valid;
input bdma2mcif_wr_req_ready;
output [514:0] bdma2mcif_wr_req_pd;
input csb2bdma_req_pvld;
output csb2bdma_req_prdy;
input [62:0] csb2bdma_req_pd;
input cvif2bdma_rd_rsp_valid;
output cvif2bdma_rd_rsp_ready;
input [513:0] cvif2bdma_rd_rsp_pd;
input cvif2bdma_wr_rsp_complete;
input mcif2bdma_rd_rsp_valid;
output mcif2bdma_rd_rsp_ready;
input [513:0] mcif2bdma_rd_rsp_pd;
input mcif2bdma_wr_rsp_complete;
input [31:0] pwrbus_ram_pd;

input dla_clk_ovr_on_sync;
input global_clk_ovr_on_sync;
input tmc2slcg_disable_clock_gating;
wire csb2gate_slcg_en;
wire csb2ld_rdy;
wire csb2ld_vld;
wire [31:0] dma_write_stall_count;
wire dma_write_stall_count_cen;
wire ld2csb_grp0_dma_stall_inc;
wire ld2csb_grp1_dma_stall_inc;
wire ld2csb_idle;
wire ld2gate_slcg_en;
wire [160:0] ld2st_rd_pd;
wire ld2st_rd_prdy;
wire ld2st_rd_pvld;
wire ld2st_wr_idle;
wire [160:0] ld2st_wr_pd;
wire ld2st_wr_prdy;
wire ld2st_wr_pvld;
wire nvdla_gated_clk;
wire reg2dp_cmd_dst_ram_type;
wire reg2dp_cmd_interrupt;
wire reg2dp_cmd_interrupt_ptr;
wire reg2dp_cmd_src_ram_type;
wire [31:0] reg2dp_dst_addr_high_v8;
wire [26:0] reg2dp_dst_addr_low_v32;
wire [26:0] reg2dp_dst_line_stride;
wire [26:0] reg2dp_dst_surf_stride;
wire [23:0] reg2dp_line_repeat_number;
wire [12:0] reg2dp_line_size;
wire [31:0] reg2dp_src_addr_high_v8;
wire [26:0] reg2dp_src_addr_low_v32;
wire [26:0] reg2dp_src_line_stride;
wire [26:0] reg2dp_src_surf_stride;
wire [23:0] reg2dp_surf_repeat_number;
wire st2csb_grp0_done;
wire st2csb_grp1_done;
wire st2csb_idle;
wire st2gate_slcg_en;
wire st2ld_load_idle;

NV_NVDLA_BDMA_csb u_csb (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.csb2bdma_req_pvld (csb2bdma_req_pvld)
  ,.csb2bdma_req_prdy (csb2bdma_req_prdy)
  ,.csb2bdma_req_pd (csb2bdma_req_pd[62:0])
  ,.bdma2csb_resp_valid (bdma2csb_resp_valid)
  ,.bdma2csb_resp_pd (bdma2csb_resp_pd[33:0])
  ,.bdma2glb_done_intr_pd (bdma2glb_done_intr_pd[1:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  ,.st2csb_grp0_done (st2csb_grp0_done)
  ,.st2csb_grp1_done (st2csb_grp1_done)
  ,.st2csb_idle (st2csb_idle)
  ,.reg2dp_cmd_dst_ram_type (reg2dp_cmd_dst_ram_type)
  ,.reg2dp_cmd_interrupt (reg2dp_cmd_interrupt)
  ,.reg2dp_cmd_interrupt_ptr (reg2dp_cmd_interrupt_ptr)
  ,.reg2dp_cmd_src_ram_type (reg2dp_cmd_src_ram_type)
  ,.reg2dp_dst_addr_high_v8 (reg2dp_dst_addr_high_v8[31:0])
  ,.reg2dp_dst_addr_low_v32 (reg2dp_dst_addr_low_v32[26:0])
  ,.reg2dp_dst_line_stride (reg2dp_dst_line_stride[26:0])
  ,.reg2dp_dst_surf_stride (reg2dp_dst_surf_stride[26:0])
  ,.reg2dp_line_repeat_number (reg2dp_line_repeat_number[23:0])
  ,.reg2dp_line_size (reg2dp_line_size[12:0])
  ,.reg2dp_src_addr_high_v8 (reg2dp_src_addr_high_v8[31:0])
  ,.reg2dp_src_addr_low_v32 (reg2dp_src_addr_low_v32[26:0])
  ,.reg2dp_src_line_stride (reg2dp_src_line_stride[26:0])
  ,.reg2dp_src_surf_stride (reg2dp_src_surf_stride[26:0])
  ,.reg2dp_surf_repeat_number (reg2dp_surf_repeat_number[23:0])
  ,.csb2ld_rdy (csb2ld_rdy)
  ,.ld2csb_grp0_dma_stall_inc (ld2csb_grp0_dma_stall_inc)
  ,.ld2csb_grp1_dma_stall_inc (ld2csb_grp1_dma_stall_inc)
  ,.ld2csb_idle (ld2csb_idle)
  ,.csb2ld_vld (csb2ld_vld)
  ,.csb2gate_slcg_en (csb2gate_slcg_en)
  ,.dma_write_stall_count (dma_write_stall_count[31:0])
  ,.dma_write_stall_count_cen (dma_write_stall_count_cen)
  );
NV_NVDLA_BDMA_gate u_gate (
   .csb2gate_slcg_en (csb2gate_slcg_en)
  ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync)
  ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync)
  ,.ld2gate_slcg_en (ld2gate_slcg_en)
  ,.nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.st2gate_slcg_en (st2gate_slcg_en)
  ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating)
  ,.nvdla_gated_clk (nvdla_gated_clk)
  );
NV_NVDLA_BDMA_load u_load (
   .nvdla_core_clk (nvdla_gated_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.bdma2mcif_rd_req_valid (bdma2mcif_rd_req_valid)
  ,.bdma2mcif_rd_req_ready (bdma2mcif_rd_req_ready)
  ,.bdma2mcif_rd_req_pd (bdma2mcif_rd_req_pd[78:0])
  ,.bdma2cvif_rd_req_valid (bdma2cvif_rd_req_valid)
  ,.bdma2cvif_rd_req_ready (bdma2cvif_rd_req_ready)
  ,.bdma2cvif_rd_req_pd (bdma2cvif_rd_req_pd[78:0])
  ,.ld2st_wr_pvld (ld2st_wr_pvld)
  ,.ld2st_wr_prdy (ld2st_wr_prdy)
  ,.ld2st_wr_pd (ld2st_wr_pd[160:0])
  ,.reg2dp_cmd_dst_ram_type (reg2dp_cmd_dst_ram_type)
  ,.reg2dp_cmd_interrupt (reg2dp_cmd_interrupt)
  ,.reg2dp_cmd_interrupt_ptr (reg2dp_cmd_interrupt_ptr)
  ,.reg2dp_cmd_src_ram_type (reg2dp_cmd_src_ram_type)
  ,.reg2dp_dst_addr_high_v8 (reg2dp_dst_addr_high_v8[31:0])
  ,.reg2dp_dst_addr_low_v32 (reg2dp_dst_addr_low_v32[26:0])
  ,.reg2dp_dst_line_stride (reg2dp_dst_line_stride[26:0])
  ,.reg2dp_dst_surf_stride (reg2dp_dst_surf_stride[26:0])
  ,.reg2dp_line_repeat_number (reg2dp_line_repeat_number[23:0])
  ,.reg2dp_line_size (reg2dp_line_size[12:0])
  ,.reg2dp_src_addr_high_v8 (reg2dp_src_addr_high_v8[31:0])
  ,.reg2dp_src_addr_low_v32 (reg2dp_src_addr_low_v32[26:0])
  ,.reg2dp_src_line_stride (reg2dp_src_line_stride[26:0])
  ,.reg2dp_src_surf_stride (reg2dp_src_surf_stride[26:0])
  ,.reg2dp_surf_repeat_number (reg2dp_surf_repeat_number[23:0])
  ,.csb2ld_vld (csb2ld_vld)
  ,.csb2ld_rdy (csb2ld_rdy)
  ,.ld2csb_grp0_dma_stall_inc (ld2csb_grp0_dma_stall_inc)
  ,.ld2csb_grp1_dma_stall_inc (ld2csb_grp1_dma_stall_inc)
  ,.ld2csb_idle (ld2csb_idle)
  ,.ld2st_wr_idle (ld2st_wr_idle)
  ,.st2ld_load_idle (st2ld_load_idle)
  ,.ld2gate_slcg_en (ld2gate_slcg_en)
  );
NV_NVDLA_BDMA_store u_store (
   .nvdla_core_clk (nvdla_gated_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.mcif2bdma_rd_rsp_valid (mcif2bdma_rd_rsp_valid)
  ,.mcif2bdma_rd_rsp_ready (mcif2bdma_rd_rsp_ready)
  ,.mcif2bdma_rd_rsp_pd (mcif2bdma_rd_rsp_pd[513:0])
  ,.cvif2bdma_rd_rsp_valid (cvif2bdma_rd_rsp_valid)
  ,.cvif2bdma_rd_rsp_ready (cvif2bdma_rd_rsp_ready)
  ,.cvif2bdma_rd_rsp_pd (cvif2bdma_rd_rsp_pd[513:0])
  ,.bdma2mcif_rd_cdt_lat_fifo_pop (bdma2mcif_rd_cdt_lat_fifo_pop)
  ,.bdma2cvif_rd_cdt_lat_fifo_pop (bdma2cvif_rd_cdt_lat_fifo_pop)
  ,.bdma2mcif_wr_req_valid (bdma2mcif_wr_req_valid)
  ,.bdma2mcif_wr_req_ready (bdma2mcif_wr_req_ready)
  ,.bdma2mcif_wr_req_pd (bdma2mcif_wr_req_pd[514:0])
  ,.bdma2cvif_wr_req_valid (bdma2cvif_wr_req_valid)
  ,.bdma2cvif_wr_req_ready (bdma2cvif_wr_req_ready)
  ,.bdma2cvif_wr_req_pd (bdma2cvif_wr_req_pd[514:0])
  ,.mcif2bdma_wr_rsp_complete (mcif2bdma_wr_rsp_complete)
  ,.cvif2bdma_wr_rsp_complete (cvif2bdma_wr_rsp_complete)
  ,.ld2st_rd_pvld (ld2st_rd_pvld)
  ,.ld2st_rd_prdy (ld2st_rd_prdy)
  ,.ld2st_rd_pd (ld2st_rd_pd[160:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  ,.st2ld_load_idle (st2ld_load_idle)
  ,.st2csb_grp0_done (st2csb_grp0_done)
  ,.st2csb_grp1_done (st2csb_grp1_done)
  ,.st2csb_idle (st2csb_idle)
  ,.st2gate_slcg_en (st2gate_slcg_en)
  ,.dma_write_stall_count (dma_write_stall_count[31:0])
  ,.dma_write_stall_count_cen (dma_write_stall_count_cen)
  );
NV_NVDLA_BDMA_cq u_cq (
   .nvdla_core_clk (nvdla_gated_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.ld2st_wr_prdy (ld2st_wr_prdy)
  ,.ld2st_wr_idle (ld2st_wr_idle)
  ,.ld2st_wr_pvld (ld2st_wr_pvld)
  ,.ld2st_wr_pd (ld2st_wr_pd[160:0])
  ,.ld2st_rd_prdy (ld2st_rd_prdy)
  ,.ld2st_rd_pvld (ld2st_rd_pvld)
  ,.ld2st_rd_pd (ld2st_rd_pd[160:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  );
endmodule