data/full_repos/permissive/46132596/processor/SingleCycleDatapath/Alu.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/46132596/processor/SingleCycleDatapath/Alu.v:30: Multiple top level modules\n                                                                                             : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                             : ... Top module \'Alu\'\nmodule Alu(input[31:0] op1,\n       ^~~\n                                                                                             : ... Top module \'Mult_Div_Alu\'\nmodule Mult_Div_Alu(input[31:0] op1,\n       ^~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module Mult_Div_Alu(input[31:0] op1,
                    input[31:0] op2,
                    input[3:0] f,
		    input en,
                    output reg[31:0] result_hi,
                    output reg[31:0] result_lo);

    always @(op1, op2, f)
	if(en) begin
       case (f)
    	    0: begin
                result_lo = $signed(op1) / $signed(op2);
                result_hi = $signed(op1) % $signed(op2);
            end
            1: begin
                result_lo = op1 / op2;
                result_hi = op1 % op2;
            end
            2: begin
		{result_hi, result_lo} = $signed(op1) * $signed(op2);
	    end
            3: begin
		{result_hi, result_lo} = op1 * op2;
	    end

        endcase

	
	$display("\tR[lo] = %x (hex)", result_lo);
	$display("\tR[hi] = %x (hex)", result_hi);
	end
endmodule
module Mult_Div_Alu(input[31:0] op1,
                    input[31:0] op2,
                    input[3:0] f,
		    input en,
                    output reg[31:0] result_hi,
                    output reg[31:0] result_lo);


    always @(op1, op2, f)
	if(en) begin
       case (f)
    	    0: begin
                result_lo = $signed(op1) / $signed(op2);
                result_hi = $signed(op1) % $signed(op2);
            end
            1: begin
                result_lo = op1 / op2;
                result_hi = op1 % op2;
            end
            2: begin
		{result_hi, result_lo} = $signed(op1) * $signed(op2);
	    end
            3: begin
		{result_hi, result_lo} = op1 * op2;
	    end

        endcase

	
	$display("\tR[lo] = %x (hex)", result_lo);
	$display("\tR[hi] = %x (hex)", result_hi);
	end
endmodule