data/full_repos/permissive/521337848/Hardware/IO/IOmodule.v
1: b'%Error: data/full_repos/permissive/521337848/Hardware/IO/IOmodule.v:34: Cannot find file containing module: \'RTC\'\nRTC rtc(.clk(clk),\n^~~\n        ... Looked in:\n             data/full_repos/permissive/521337848/Hardware/IO,data/full_repos/permissive/521337848/RTC\n             data/full_repos/permissive/521337848/Hardware/IO,data/full_repos/permissive/521337848/RTC.v\n             data/full_repos/permissive/521337848/Hardware/IO,data/full_repos/permissive/521337848/RTC.sv\n             RTC\n             RTC.v\n             RTC.sv\n             obj_dir/RTC\n             obj_dir/RTC.v\n             obj_dir/RTC.sv\n%Error: data/full_repos/permissive/521337848/Hardware/IO/IOmodule.v:60: Cannot find file containing module: \'UART_TEST\'\nUART_TEST ut(.clk(clk),\n^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/IO/IOmodule.v:76: Input port connection \'sel\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'sel\' generates 2 bits.\n                                                                              : ... In instance IOmodule\n      .sel(sel),\n       ^~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module IOmodule(
	input clk,
	
	input rst,
	
	input start,
	input[23:0] in,
	
	output[3:0] led,
	
	output rdy,
	output[23:0] out,
	
	output[15:0] gpio_out,
	input[15:0] gpio_in,
	
	output tx1,
	input rx1,
	
	output tx2,
	input rx2,
	
	output wrst
	
);

wire rdy1;
wire send;
wire[7:0] out1;
wire[7:0] in1;

wire[1:0] sel;

RTC rtc(.clk(clk),
				.rst(rst),
				
				.sel(sel),
				.start(start),
				.in(in),
	
				.rdy(rdy),
				.out(out),
				
				.led(led),
				
				.gpio_in(gpio_in),
				.gpio_out(gpio_out),
				
				.rdy1(rdy1),
				.send(send),
				.out1(out1),
				.in1(in1),
				
				.wrst(wrst)
);

wire b_tx;
wire b_rx;

UART_TEST ut(.clk(clk),
				 .rst(rst),
	
				.in(out1),
				.send(send),
				
				.out(in1),
				.rdy(rdy1),
				
				.tx(b_tx),
				.rx(b_rx)
);

uartSelector uS(.clk(clk),
					 .rst(rst),
	
					 .sel(sel),
	
					 .txIn(b_tx),
	
					 .txIn1(tx1),
					 .txIn2(tx2),
					
					 .rxIn1(rx1),
					 .rxIn2(rx2),
	
					 .rxIn(b_rx)

);
endmodule
module IOmodule(
	input clk,
	
	input rst,
	
	input start,
	input[23:0] in,
	
	output[3:0] led,
	
	output rdy,
	output[23:0] out,
	
	output[15:0] gpio_out,
	input[15:0] gpio_in,
	
	output tx1,
	input rx1,
	
	output tx2,
	input rx2,
	
	output wrst
	
);


wire rdy1;
wire send;
wire[7:0] out1;
wire[7:0] in1;

wire[1:0] sel;

RTC rtc(.clk(clk),
				.rst(rst),
				
				.sel(sel),
				.start(start),
				.in(in),
	
				.rdy(rdy),
				.out(out),
				
				.led(led),
				
				.gpio_in(gpio_in),
				.gpio_out(gpio_out),
				
				.rdy1(rdy1),
				.send(send),
				.out1(out1),
				.in1(in1),
				
				.wrst(wrst)
);

wire b_tx;
wire b_rx;

UART_TEST ut(.clk(clk),
				 .rst(rst),
	
				.in(out1),
				.send(send),
				
				.out(in1),
				.rdy(rdy1),
				
				.tx(b_tx),
				.rx(b_rx)
);

uartSelector uS(.clk(clk),
					 .rst(rst),
	
					 .sel(sel),
	
					 .txIn(b_tx),
	
					 .txIn1(tx1),
					 .txIn2(tx2),
					
					 .rxIn1(rx1),
					 .rxIn2(rx2),
	
					 .rxIn(b_rx)

);
endmodule