data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v
1: b'%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:3: Cannot find include file: noc_parameter.vh\n    `include "noc_parameter.vh" \n             ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh\n             data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.v\n             data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.sv\n             noc_parameter.vh\n             noc_parameter.vh.v\n             noc_parameter.vh.sv\n             obj_dir/noc_parameter.vh\n             obj_dir/noc_parameter.vh.v\n             obj_dir/noc_parameter.vh.sv\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:4: Cannot find include file: tcu_parameter.vh\n    ,`include "tcu_parameter.vh" \n              ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:51: Cannot find include file: tcu_functions.v\n    `include "tcu_functions.v" \n             ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:4: syntax error, unexpected \',\', expecting \'[\'\n    , \n    ^\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:6: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter [31:0] TIMEOUT_SEND_CYCLES = 0\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:7: syntax error, unexpected \')\', expecting \';\'\n)(\n^\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:9: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          reset_n_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:13: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                     [1:0] mas_mem_en_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:14: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output wire  [TCU_MEM_ADDR_SIZE-1:0] mas_mem_addr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:15: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                          mas_mem_rdata_valid_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          mas_mem_rdata_avail_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:17: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire  [TCU_MEM_DATA_SIZE-1:0] mas_mem_wdata_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:18: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          mas_mem_stall_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:20: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          noc_stall_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:21: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                           noc_wrreq_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:22: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg                           noc_burst_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:23: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg       [NOC_BSEL_SIZE-1:0] noc_bsel_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:24: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg       [NOC_DATA_SIZE-1:0] noc_data0_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:25: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output wire      [NOC_ADDR_SIZE-1:0] noc_addr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:26: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg       [NOC_MODE_SIZE-1:0] noc_mode_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:27: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output wire    [NOC_CHIPID_SIZE-1:0] noc_chipid_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:28: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire     [NOC_MODID_SIZE-1:0] noc_modid_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:29: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          noc_ack_recv_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:30: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire      [NOC_ADDR_SIZE-1:0] noc_ack_addr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:31: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire    [NOC_CHIPID_SIZE-1:0] noc_ack_chipid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:32: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire     [NOC_MODID_SIZE-1:0] noc_ack_modid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:33: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                   [31:0] noc_ack_size_i,     \n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:37: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          mas_start_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:38: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire    [TCU_OPCODE_SIZE-1:0] mas_opcode_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:39: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                   [31:0] mas_laddr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:40: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                   [31:0] mas_raddr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:41: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                   [31:0] mas_size_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:42: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire    [NOC_CHIPID_SIZE-1:0] mas_chipid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:43: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire     [NOC_MODID_SIZE-1:0] mas_modid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:44: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          mas_abort_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:45: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                          mas_active_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:46: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                          mas_noc_active_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:47: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                          mas_done_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:48: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire     [TCU_ERROR_SIZE-1:0] mas_error_o\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:49: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_send.v:104: syntax error, unexpected always\n    always @(posedge clk_i) begin\n    ^~~~~~\n%Error: Exiting due to 41 error(s)\n'
module tcu_ctrl_mem_access_send #(
    `include "noc_parameter.vh"
    ,`include "tcu_parameter.vh"
    ,parameter TCU_ENABLE_DRAM           = 0,
    parameter [31:0] TIMEOUT_SEND_CYCLES = 0
)(
    input  wire                          clk_i,
    input  wire                          reset_n_i,



    output reg                     [1:0] mas_mem_en_o,
    output wire  [TCU_MEM_ADDR_SIZE-1:0] mas_mem_addr_o,
    output wire                          mas_mem_rdata_valid_o,
    input  wire                          mas_mem_rdata_avail_i,
    output wire  [TCU_MEM_DATA_SIZE-1:0] mas_mem_wdata_o,
    input  wire                          mas_mem_stall_i,

    input  wire                          noc_stall_i,
    output reg                           noc_wrreq_o,
    output reg                           noc_burst_o,
    output reg       [NOC_BSEL_SIZE-1:0] noc_bsel_o,
    output reg       [NOC_DATA_SIZE-1:0] noc_data0_o,
    output wire      [NOC_ADDR_SIZE-1:0] noc_addr_o,
    output reg       [NOC_MODE_SIZE-1:0] noc_mode_o,
    output wire    [NOC_CHIPID_SIZE-1:0] noc_chipid_o,
    output wire     [NOC_MODID_SIZE-1:0] noc_modid_o,
    input  wire                          noc_ack_recv_i,
    input  wire      [NOC_ADDR_SIZE-1:0] noc_ack_addr_i,
    input  wire    [NOC_CHIPID_SIZE-1:0] noc_ack_chipid_i,
    input  wire     [NOC_MODID_SIZE-1:0] noc_ack_modid_i,
    input  wire                   [31:0] noc_ack_size_i,



    input  wire                          mas_start_i,
    input  wire    [TCU_OPCODE_SIZE-1:0] mas_opcode_i,
    input  wire                   [31:0] mas_laddr_i,
    input  wire                   [31:0] mas_raddr_i,
    input  wire                   [31:0] mas_size_i,
    input  wire    [NOC_CHIPID_SIZE-1:0] mas_chipid_i,
    input  wire     [NOC_MODID_SIZE-1:0] mas_modid_i,
    input  wire                          mas_abort_i,
    output wire                          mas_active_o,
    output wire                          mas_noc_active_o,
    output wire                          mas_done_o,
    output wire     [TCU_ERROR_SIZE-1:0] mas_error_o
);

    `include "tcu_functions.v"


    localparam CTRL_MAS_STATES_SIZE     = 4;
    localparam S_CTRL_MAS_IDLE          = 4'h0;
    localparam S_CTRL_MAS_PREPARE_MEM1  = 4'h1;
    localparam S_CTRL_MAS_PREPARE_MEM2  = 4'h2;
    localparam S_CTRL_MAS_MEM_WRITE1    = 4'h3;
    localparam S_CTRL_MAS_MEM_WRITE2    = 4'h4;
    localparam S_CTRL_MAS_MEM_WRITE3    = 4'h5;
    localparam S_CTRL_MAS_REQ_ERROR     = 4'h6;
    localparam S_CTRL_MAS_ABORT         = 4'h7;
    localparam S_CTRL_MAS_WAIT_ACK      = 4'h8;
    localparam S_CTRL_MAS_FINISH        = 4'hF;

    reg [CTRL_MAS_STATES_SIZE-1:0] ctrl_mas_state, next_ctrl_mas_state;



    reg [TCU_OPCODE_SIZE-1:0] r_opcode, rin_opcode;
    reg                [31:0] r_laddr, rin_laddr;
    reg                [31:0] r_size, rin_size;
    reg                [31:0] r_write_size, rin_write_size;
    reg                [15:0] r_tmp_size, rin_tmp_size;
    reg                [31:0] r_raddr, rin_raddr;
    reg                [31:0] r_write_raddr, rin_write_raddr;
    reg [NOC_CHIPID_SIZE-1:0] r_chipid, rin_chipid;
    reg  [NOC_MODID_SIZE-1:0] r_modid, rin_modid;

    reg r_stall;
    reg r_mas_mem_en;


    reg [TCU_ERROR_SIZE-1:0] r_mas_error, rin_mas_error;


    reg [31:0] r_mas_timeout, rin_mas_timeout;


    reg [31:0] r_ack_size, rin_ack_size;



    wire [5:0] end_addr = r_laddr[3:0] + r_tmp_size[3:0];


    wire [12:0] burst_length = noc_data0_o;


    wire [31:0] write_addr_end = r_write_raddr + r_write_size;



    always @(posedge clk_i) begin
        if (reset_n_i == 1'b0) begin
            ctrl_mas_state <= S_CTRL_MAS_IDLE;
            
            r_opcode <= {TCU_OPCODE_SIZE{1'b0}};
            r_laddr <= 32'h0;
            r_raddr <= 32'h0;
            r_write_raddr <= 32'h0;
            r_size <= 32'h0;
            r_write_size <= 32'h0;
            r_tmp_size <= 16'h0;
            r_chipid <= {NOC_CHIPID_SIZE{1'b0}};
            r_modid <= {NOC_MODID_SIZE{1'b0}};

            r_stall <= 1'b0;
            r_mas_mem_en <= 1'b0;

            r_mas_error <= TCU_ERROR_NONE;

            r_mas_timeout <= 32'h0;

            r_ack_size <= 32'h0;
        end
        else begin
            ctrl_mas_state <= next_ctrl_mas_state;
            
            r_opcode <= rin_opcode;
            r_laddr <= rin_laddr;
            r_raddr <= rin_raddr;
            r_write_raddr <= rin_write_raddr;
            r_size <= rin_size;
            r_write_size <= rin_write_size;
            r_tmp_size <= rin_tmp_size;
            r_chipid <= rin_chipid;
            r_modid <= rin_modid;

            r_stall <= noc_stall_i || mas_mem_stall_i;
            r_mas_mem_en <= mas_mem_en_o[0];

            r_mas_error <= rin_mas_error;

            r_mas_timeout <= rin_mas_timeout;

            r_ack_size <= rin_ack_size;
        end
    end






    always @* begin
        next_ctrl_mas_state = ctrl_mas_state;

        noc_wrreq_o = 1'b0;
        noc_burst_o = 1'b0;
        noc_bsel_o = {NOC_BSEL_SIZE{1'b0}};
        noc_data0_o = {NOC_DATA_SIZE{1'b0}};

        rin_opcode = r_opcode;
        rin_laddr = r_laddr;
        rin_size = r_size;
        rin_write_size = r_write_size;
        rin_tmp_size = r_tmp_size;
        rin_raddr = r_raddr;
        rin_write_raddr = r_write_raddr;
        rin_chipid = r_chipid;
        rin_modid = r_modid;

        rin_mas_error = r_mas_error;

        rin_mas_timeout = 32'h0;


        case (ctrl_mas_state)



            S_CTRL_MAS_IDLE: begin
                if (mas_start_i) begin
                    rin_opcode = mas_opcode_i;
                    rin_laddr = mas_laddr_i;
                    rin_raddr = mas_raddr_i;
                    rin_write_raddr = mas_raddr_i;
                    rin_size = mas_size_i;
                    rin_write_size = mas_size_i;
                    rin_chipid = mas_chipid_i;
                    rin_modid = mas_modid_i;


                    if (mas_size_i[31:4] >= MAX_BURST_LENGTH) begin
                        if (mas_laddr_i[3:0] != 'd0) begin
                            rin_tmp_size = (MAX_BURST_LENGTH << 4) - mas_laddr_i[3:0];
                        end else begin
                            rin_tmp_size = MAX_BURST_LENGTH << 4;
                        end
                    end else begin
                        rin_tmp_size = mas_size_i;
                    end
                    

                    if ((mas_opcode_i == TCU_OPCODE_WRITE) ||
                        (mas_opcode_i == TCU_OPCODE_WRITE_RSP) ||
                        (mas_opcode_i == TCU_OPCODE_WRITE_RSP_2)) begin


                        if (TCU_ENABLE_DRAM) begin
                            next_ctrl_mas_state = S_CTRL_MAS_PREPARE_MEM1;
                        end


                        else if (mas_size_i > 'd8) begin
                            next_ctrl_mas_state = S_CTRL_MAS_MEM_WRITE2;
                        end else begin
                            next_ctrl_mas_state = S_CTRL_MAS_MEM_WRITE1;
                        end
                    end

                    else begin
                        next_ctrl_mas_state = S_CTRL_MAS_FINISH;
                    end

                    rin_mas_error = TCU_ERROR_NONE;
                end
            end



            S_CTRL_MAS_PREPARE_MEM1: begin
                if (!mas_mem_stall_i) begin
                    next_ctrl_mas_state = S_CTRL_MAS_PREPARE_MEM2;
                end
            end

            S_CTRL_MAS_PREPARE_MEM2: begin

                if (mas_mem_rdata_avail_i) begin


                    if (r_size > 'd8) begin
                        next_ctrl_mas_state = S_CTRL_MAS_MEM_WRITE2;
                    end else begin
                        next_ctrl_mas_state = S_CTRL_MAS_MEM_WRITE1;
                    end
                end


                else if (TIMEOUT_SEND_CYCLES != 32'h0) begin
                    rin_mas_timeout = r_mas_timeout + 32'd1;
                    if (r_mas_timeout > TIMEOUT_SEND_CYCLES) begin
                        rin_mas_error = TCU_ERROR_TIMEOUT_MEM;



                        if ((r_opcode == TCU_OPCODE_WRITE_RSP) || (r_opcode == TCU_OPCODE_WRITE_RSP_2)) begin
                            rin_opcode = TCU_OPCODE_WRITE_ERROR;
                            next_ctrl_mas_state = S_CTRL_MAS_REQ_ERROR;
                        end
                        else begin
                            next_ctrl_mas_state = S_CTRL_MAS_FINISH;
                        end
                    end
                end
            end



            S_CTRL_MAS_MEM_WRITE1: begin
                if (!mas_mem_stall_i && !noc_stall_i) begin
                    noc_bsel_o = set_bsel8(r_laddr[2:0], r_size[3:0]);


                    if ((r_laddr[2:0] + r_size[3:0]) > 4'h8) begin
                        rin_laddr = {(r_laddr[31:3]+'h1), 3'h0};
                        rin_size = r_size - (4'h8 - r_laddr[2:0]);
                        rin_raddr = r_raddr + (4'h8 - r_laddr[2:0]);

                        next_ctrl_mas_state = S_CTRL_MAS_MEM_WRITE1;
                    end


                    else begin
                        rin_tmp_size = 'd0;

                        if (r_opcode == TCU_OPCODE_WRITE) begin
                            next_ctrl_mas_state = S_CTRL_MAS_WAIT_ACK;
                        end else begin
                            next_ctrl_mas_state = S_CTRL_MAS_FINISH;
                        end
                    end
                end


                else if (mas_mem_stall_i && (TIMEOUT_SEND_CYCLES != 32'h0)) begin
                    rin_mas_timeout = r_mas_timeout + 32'd1;
                    if (r_mas_timeout > TIMEOUT_SEND_CYCLES) begin
                        rin_mas_error = TCU_ERROR_TIMEOUT_MEM;



                        if ((r_opcode == TCU_OPCODE_WRITE_RSP) || (r_opcode == TCU_OPCODE_WRITE_RSP_2)) begin
                            rin_opcode = TCU_OPCODE_WRITE_ERROR;
                            next_ctrl_mas_state = S_CTRL_MAS_REQ_ERROR;
                        end
                        else begin
                            next_ctrl_mas_state = S_CTRL_MAS_FINISH;
                        end
                    end
                end
            end

            S_CTRL_MAS_MEM_WRITE2: begin

                if (mas_abort_i) begin
                    rin_mas_error = TCU_ERROR_ABORT;
                    next_ctrl_mas_state = S_CTRL_MAS_FINISH;
                end
                else if (!mas_mem_stall_i && !noc_stall_i) begin
                    rin_size = r_size - r_tmp_size;


                    if (r_tmp_size > 'd8) begin


                        noc_wrreq_o = 1'b1;
                        noc_burst_o = 1'b1;


                        if (r_size[31:4] < MAX_BURST_LENGTH) begin
                            noc_bsel_o = {(((r_laddr[3:0]+r_tmp_size[3:0]) & 4'hF) - 'b1), ~r_laddr[3:0]};




                            noc_data0_o = r_tmp_size[15:4] + ((end_addr != 5'd0) ? 1 : 0) + ((end_addr > 5'd16) ? 1 : 0);
                        end
                        else begin
                            noc_bsel_o = {{(NOC_BSEL_SIZE/2){1'b1}}, ~r_laddr[3:0]};
                            noc_data0_o = MAX_BURST_LENGTH;
                        end

                        rin_laddr = r_laddr + 'd16;
                        rin_raddr = r_raddr + (5'd16 - r_laddr[3:0]);


                        if (burst_length == 'd1) begin
                            rin_tmp_size = 'd0;
                        end else begin
                            rin_tmp_size = r_tmp_size - (5'd16 - r_laddr[3:0]);
                        end

                        next_ctrl_mas_state = S_CTRL_MAS_MEM_WRITE3;
                    end


                    else begin
                        rin_tmp_size = 'd0;
                        noc_burst_o = 1'b0;
                        noc_bsel_o = set_bsel8(r_laddr[2:0], r_tmp_size[3:0]);


                        if (r_opcode == TCU_OPCODE_WRITE) begin
                            next_ctrl_mas_state = S_CTRL_MAS_WAIT_ACK;
                        end else begin
                            next_ctrl_mas_state = S_CTRL_MAS_FINISH;
                        end
                    end
                end


                else if (mas_mem_stall_i && (TIMEOUT_SEND_CYCLES != 32'h0)) begin
                    rin_mas_timeout = r_mas_timeout + 32'd1;
                    if (r_mas_timeout > TIMEOUT_SEND_CYCLES) begin
                        rin_mas_error = TCU_ERROR_TIMEOUT_MEM;
                        


                        if ((r_opcode == TCU_OPCODE_WRITE_RSP) || (r_opcode == TCU_OPCODE_WRITE_RSP_2)) begin
                            rin_opcode = TCU_OPCODE_WRITE_ERROR;
                            next_ctrl_mas_state = S_CTRL_MAS_REQ_ERROR;
                        end
                        else begin
                            next_ctrl_mas_state = S_CTRL_MAS_FINISH;
                        end
                    end
                end
            end

            S_CTRL_MAS_MEM_WRITE3: begin
                if (!noc_stall_i) begin

                    if (mas_mem_stall_i && (r_tmp_size > 'd0)) begin
                        noc_burst_o = 1'b1;
                        noc_bsel_o = {NOC_BSEL_SIZE{1'b1}};
                        next_ctrl_mas_state = S_CTRL_MAS_MEM_WRITE3;


                        if (mas_abort_i) begin
                            noc_bsel_o = {NOC_BSEL_SIZE{1'b0}};
                            rin_mas_error = TCU_ERROR_ABORT;
                            next_ctrl_mas_state = S_CTRL_MAS_ABORT;
                        end


                        else if (TIMEOUT_SEND_CYCLES != 32'h0) begin
                            rin_mas_timeout = r_mas_timeout + 32'd1;
                            if (r_mas_timeout > TIMEOUT_SEND_CYCLES) begin
                                noc_bsel_o = {NOC_BSEL_SIZE{1'b0}};
                                rin_mas_error = TCU_ERROR_TIMEOUT_MEM;
                                next_ctrl_mas_state = S_CTRL_MAS_ABORT;
                            end
                        end
                    end
                    else begin
                        noc_bsel_o = {NOC_BSEL_SIZE{1'b1}};


                        if (r_tmp_size > 'd0) begin
                            
                            rin_laddr = r_laddr + 'd16;
                            rin_tmp_size  = (r_tmp_size > 'd16) ? (r_tmp_size - 'd16) : 'd0;
                            rin_raddr = r_raddr + 'd16;

                            noc_burst_o = 1'b1;


                            if (mas_abort_i) begin
                                noc_bsel_o = {NOC_BSEL_SIZE{1'b0}};
                                rin_mas_error = TCU_ERROR_ABORT;
                                next_ctrl_mas_state = S_CTRL_MAS_ABORT;
                            end
                            else begin
                                next_ctrl_mas_state = S_CTRL_MAS_MEM_WRITE3;
                            end
                        end


                        else begin
                            noc_burst_o = 1'b0;
                        

                            if (r_size > 'h0) begin
                                rin_laddr = {r_laddr[31:4], 4'h0};

                                if (r_size[31:4] < MAX_BURST_LENGTH) begin
                                    rin_tmp_size = r_size[15:0]; 
                                end else begin
                                    rin_tmp_size = MAX_BURST_LENGTH << 4;
                                end

                                next_ctrl_mas_state = S_CTRL_MAS_MEM_WRITE2;
                            end


                            else if (r_opcode == TCU_OPCODE_WRITE) begin
                                next_ctrl_mas_state = S_CTRL_MAS_WAIT_ACK;
                            end else begin
                                next_ctrl_mas_state = S_CTRL_MAS_FINISH;
                            end
                        end
                    end
                end
            end




            S_CTRL_MAS_REQ_ERROR: begin
                if (!noc_stall_i) begin
                    noc_wrreq_o = 1'b1;
                    noc_bsel_o = {NOC_BSEL_SIZE{1'b1}};
                    noc_data0_o = r_mas_error;

                    next_ctrl_mas_state = S_CTRL_MAS_FINISH;
                end
            end




            S_CTRL_MAS_ABORT: begin
                noc_bsel_o = {NOC_BSEL_SIZE{1'b0}};
                
                if (!noc_stall_i) begin
                    noc_wrreq_o = 1'b1;

                    if (r_tmp_size > 'd16) begin
                        rin_tmp_size = r_tmp_size - 'd16;
                        noc_burst_o = 1'b1;
                    end


                    else begin
                        rin_size = 'd0;
                        rin_tmp_size = 'd0;
                        noc_burst_o = 1'b0;
                        next_ctrl_mas_state = S_CTRL_MAS_FINISH;
                    end
                end
            end




            S_CTRL_MAS_WAIT_ACK: begin

                if ((r_write_raddr >= TCU_REGADDR_START) || (r_ack_size >= r_write_size)) begin
                    next_ctrl_mas_state = S_CTRL_MAS_FINISH;
                end


                else if (TIMEOUT_SEND_CYCLES != 32'h0) begin
                    rin_mas_timeout = r_mas_timeout + 32'd1;
                    if (r_mas_timeout > TIMEOUT_SEND_CYCLES) begin
                        rin_mas_error = TCU_ERROR_TIMEOUT_NOC;
                        next_ctrl_mas_state = S_CTRL_MAS_FINISH;
                    end
                end
            end


            S_CTRL_MAS_FINISH: begin

                if (!noc_stall_i) begin
                    next_ctrl_mas_state = S_CTRL_MAS_IDLE;
                end
            end

            default: next_ctrl_mas_state = S_CTRL_MAS_IDLE;

        endcase
    end




    always @* begin
        rin_ack_size = r_ack_size;


        if (mas_active_o && (r_opcode == TCU_OPCODE_WRITE)) begin
            if (noc_ack_recv_i &&
                (noc_ack_chipid_i == r_chipid) &&
                (noc_ack_modid_i == r_modid) &&
                (noc_ack_addr_i >= r_write_raddr) && (noc_ack_addr_i < write_addr_end)) begin
                rin_ack_size = r_ack_size + noc_ack_size_i;
            end
        end
        else begin
            rin_ack_size = 32'h0;
        end
    end




    always @* begin
        mas_mem_en_o = 2'b00;

        if (ctrl_mas_state == S_CTRL_MAS_PREPARE_MEM1) begin
            mas_mem_en_o = 2'b10;
        end
        if ((ctrl_mas_state == S_CTRL_MAS_MEM_WRITE1) ||
            (ctrl_mas_state == S_CTRL_MAS_MEM_WRITE2) ||
            ((ctrl_mas_state == S_CTRL_MAS_MEM_WRITE3) && (r_tmp_size > 'd0))) begin
            mas_mem_en_o = 2'b01;
        end
    end


    assign mas_mem_addr_o = r_laddr;
    assign mas_mem_rdata_valid_o = r_mas_mem_en && !r_stall;
    assign mas_mem_wdata_o = r_size;

    assign mas_error_o = r_mas_error;
    assign mas_active_o = (ctrl_mas_state != S_CTRL_MAS_IDLE);
    assign mas_noc_active_o = mas_active_o && (ctrl_mas_state < S_CTRL_MAS_WAIT_ACK);
    assign mas_done_o = (ctrl_mas_state == S_CTRL_MAS_FINISH) && !noc_stall_i;

    assign noc_addr_o = r_raddr;
    assign noc_chipid_o = r_chipid;
    assign noc_modid_o = r_modid;
    
    

    always @* begin
        case (r_opcode)
            TCU_OPCODE_WRITE:       noc_mode_o = MODE_WRITE_POSTED;
            TCU_OPCODE_WRITE_RSP:   noc_mode_o = MODE_READ_RSP;
            TCU_OPCODE_WRITE_RSP_2: noc_mode_o = MODE_READ_RSP_2;
            TCU_OPCODE_WRITE_ERROR: noc_mode_o = MODE_ERROR;
            default:                noc_mode_o = MODE_WRITE_POSTED;
        endcase
    end

    
endmodule
module tcu_ctrl_mem_access_send #(
    `include "noc_parameter.vh"
    ,`include "tcu_parameter.vh"
    ,parameter TCU_ENABLE_DRAM           = 0,
    parameter [31:0] TIMEOUT_SEND_CYCLES = 0
)(
    input  wire                          clk_i,
    input  wire                          reset_n_i,



    output reg                     [1:0] mas_mem_en_o,
    output wire  [TCU_MEM_ADDR_SIZE-1:0] mas_mem_addr_o,
    output wire                          mas_mem_rdata_valid_o,
    input  wire                          mas_mem_rdata_avail_i,
    output wire  [TCU_MEM_DATA_SIZE-1:0] mas_mem_wdata_o,
    input  wire                          mas_mem_stall_i,

    input  wire                          noc_stall_i,
    output reg                           noc_wrreq_o,
    output reg                           noc_burst_o,
    output reg       [NOC_BSEL_SIZE-1:0] noc_bsel_o,
    output reg       [NOC_DATA_SIZE-1:0] noc_data0_o,
    output wire      [NOC_ADDR_SIZE-1:0] noc_addr_o,
    output reg       [NOC_MODE_SIZE-1:0] noc_mode_o,
    output wire    [NOC_CHIPID_SIZE-1:0] noc_chipid_o,
    output wire     [NOC_MODID_SIZE-1:0] noc_modid_o,
    input  wire                          noc_ack_recv_i,
    input  wire      [NOC_ADDR_SIZE-1:0] noc_ack_addr_i,
    input  wire    [NOC_CHIPID_SIZE-1:0] noc_ack_chipid_i,
    input  wire     [NOC_MODID_SIZE-1:0] noc_ack_modid_i,
    input  wire                   [31:0] noc_ack_size_i,



    input  wire                          mas_start_i,
    input  wire    [TCU_OPCODE_SIZE-1:0] mas_opcode_i,
    input  wire                   [31:0] mas_laddr_i,
    input  wire                   [31:0] mas_raddr_i,
    input  wire                   [31:0] mas_size_i,
    input  wire    [NOC_CHIPID_SIZE-1:0] mas_chipid_i,
    input  wire     [NOC_MODID_SIZE-1:0] mas_modid_i,
    input  wire                          mas_abort_i,
    output wire                          mas_active_o,
    output wire                          mas_noc_active_o,
    output wire                          mas_done_o,
    output wire     [TCU_ERROR_SIZE-1:0] mas_error_o
);


    `include "tcu_functions.v"


    localparam CTRL_MAS_STATES_SIZE     = 4;
    localparam S_CTRL_MAS_IDLE          = 4'h0;
    localparam S_CTRL_MAS_PREPARE_MEM1  = 4'h1;
    localparam S_CTRL_MAS_PREPARE_MEM2  = 4'h2;
    localparam S_CTRL_MAS_MEM_WRITE1    = 4'h3;
    localparam S_CTRL_MAS_MEM_WRITE2    = 4'h4;
    localparam S_CTRL_MAS_MEM_WRITE3    = 4'h5;
    localparam S_CTRL_MAS_REQ_ERROR     = 4'h6;
    localparam S_CTRL_MAS_ABORT         = 4'h7;
    localparam S_CTRL_MAS_WAIT_ACK      = 4'h8;
    localparam S_CTRL_MAS_FINISH        = 4'hF;

    reg [CTRL_MAS_STATES_SIZE-1:0] ctrl_mas_state, next_ctrl_mas_state;



    reg [TCU_OPCODE_SIZE-1:0] r_opcode, rin_opcode;
    reg                [31:0] r_laddr, rin_laddr;
    reg                [31:0] r_size, rin_size;
    reg                [31:0] r_write_size, rin_write_size;
    reg                [15:0] r_tmp_size, rin_tmp_size;
    reg                [31:0] r_raddr, rin_raddr;
    reg                [31:0] r_write_raddr, rin_write_raddr;
    reg [NOC_CHIPID_SIZE-1:0] r_chipid, rin_chipid;
    reg  [NOC_MODID_SIZE-1:0] r_modid, rin_modid;

    reg r_stall;
    reg r_mas_mem_en;


    reg [TCU_ERROR_SIZE-1:0] r_mas_error, rin_mas_error;


    reg [31:0] r_mas_timeout, rin_mas_timeout;


    reg [31:0] r_ack_size, rin_ack_size;



    wire [5:0] end_addr = r_laddr[3:0] + r_tmp_size[3:0];


    wire [12:0] burst_length = noc_data0_o;


    wire [31:0] write_addr_end = r_write_raddr + r_write_size;



    always @(posedge clk_i) begin
        if (reset_n_i == 1'b0) begin
            ctrl_mas_state <= S_CTRL_MAS_IDLE;
            
            r_opcode <= {TCU_OPCODE_SIZE{1'b0}};
            r_laddr <= 32'h0;
            r_raddr <= 32'h0;
            r_write_raddr <= 32'h0;
            r_size <= 32'h0;
            r_write_size <= 32'h0;
            r_tmp_size <= 16'h0;
            r_chipid <= {NOC_CHIPID_SIZE{1'b0}};
            r_modid <= {NOC_MODID_SIZE{1'b0}};

            r_stall <= 1'b0;
            r_mas_mem_en <= 1'b0;

            r_mas_error <= TCU_ERROR_NONE;

            r_mas_timeout <= 32'h0;

            r_ack_size <= 32'h0;
        end
        else begin
            ctrl_mas_state <= next_ctrl_mas_state;
            
            r_opcode <= rin_opcode;
            r_laddr <= rin_laddr;
            r_raddr <= rin_raddr;
            r_write_raddr <= rin_write_raddr;
            r_size <= rin_size;
            r_write_size <= rin_write_size;
            r_tmp_size <= rin_tmp_size;
            r_chipid <= rin_chipid;
            r_modid <= rin_modid;

            r_stall <= noc_stall_i || mas_mem_stall_i;
            r_mas_mem_en <= mas_mem_en_o[0];

            r_mas_error <= rin_mas_error;

            r_mas_timeout <= rin_mas_timeout;

            r_ack_size <= rin_ack_size;
        end
    end






    always @* begin
        next_ctrl_mas_state = ctrl_mas_state;

        noc_wrreq_o = 1'b0;
        noc_burst_o = 1'b0;
        noc_bsel_o = {NOC_BSEL_SIZE{1'b0}};
        noc_data0_o = {NOC_DATA_SIZE{1'b0}};

        rin_opcode = r_opcode;
        rin_laddr = r_laddr;
        rin_size = r_size;
        rin_write_size = r_write_size;
        rin_tmp_size = r_tmp_size;
        rin_raddr = r_raddr;
        rin_write_raddr = r_write_raddr;
        rin_chipid = r_chipid;
        rin_modid = r_modid;

        rin_mas_error = r_mas_error;

        rin_mas_timeout = 32'h0;


        case (ctrl_mas_state)



            S_CTRL_MAS_IDLE: begin
                if (mas_start_i) begin
                    rin_opcode = mas_opcode_i;
                    rin_laddr = mas_laddr_i;
                    rin_raddr = mas_raddr_i;
                    rin_write_raddr = mas_raddr_i;
                    rin_size = mas_size_i;
                    rin_write_size = mas_size_i;
                    rin_chipid = mas_chipid_i;
                    rin_modid = mas_modid_i;


                    if (mas_size_i[31:4] >= MAX_BURST_LENGTH) begin
                        if (mas_laddr_i[3:0] != 'd0) begin
                            rin_tmp_size = (MAX_BURST_LENGTH << 4) - mas_laddr_i[3:0];
                        end else begin
                            rin_tmp_size = MAX_BURST_LENGTH << 4;
                        end
                    end else begin
                        rin_tmp_size = mas_size_i;
                    end
                    

                    if ((mas_opcode_i == TCU_OPCODE_WRITE) ||
                        (mas_opcode_i == TCU_OPCODE_WRITE_RSP) ||
                        (mas_opcode_i == TCU_OPCODE_WRITE_RSP_2)) begin


                        if (TCU_ENABLE_DRAM) begin
                            next_ctrl_mas_state = S_CTRL_MAS_PREPARE_MEM1;
                        end


                        else if (mas_size_i > 'd8) begin
                            next_ctrl_mas_state = S_CTRL_MAS_MEM_WRITE2;
                        end else begin
                            next_ctrl_mas_state = S_CTRL_MAS_MEM_WRITE1;
                        end
                    end

                    else begin
                        next_ctrl_mas_state = S_CTRL_MAS_FINISH;
                    end

                    rin_mas_error = TCU_ERROR_NONE;
                end
            end



            S_CTRL_MAS_PREPARE_MEM1: begin
                if (!mas_mem_stall_i) begin
                    next_ctrl_mas_state = S_CTRL_MAS_PREPARE_MEM2;
                end
            end

            S_CTRL_MAS_PREPARE_MEM2: begin

                if (mas_mem_rdata_avail_i) begin


                    if (r_size > 'd8) begin
                        next_ctrl_mas_state = S_CTRL_MAS_MEM_WRITE2;
                    end else begin
                        next_ctrl_mas_state = S_CTRL_MAS_MEM_WRITE1;
                    end
                end


                else if (TIMEOUT_SEND_CYCLES != 32'h0) begin
                    rin_mas_timeout = r_mas_timeout + 32'd1;
                    if (r_mas_timeout > TIMEOUT_SEND_CYCLES) begin
                        rin_mas_error = TCU_ERROR_TIMEOUT_MEM;



                        if ((r_opcode == TCU_OPCODE_WRITE_RSP) || (r_opcode == TCU_OPCODE_WRITE_RSP_2)) begin
                            rin_opcode = TCU_OPCODE_WRITE_ERROR;
                            next_ctrl_mas_state = S_CTRL_MAS_REQ_ERROR;
                        end
                        else begin
                            next_ctrl_mas_state = S_CTRL_MAS_FINISH;
                        end
                    end
                end
            end



            S_CTRL_MAS_MEM_WRITE1: begin
                if (!mas_mem_stall_i && !noc_stall_i) begin
                    noc_bsel_o = set_bsel8(r_laddr[2:0], r_size[3:0]);


                    if ((r_laddr[2:0] + r_size[3:0]) > 4'h8) begin
                        rin_laddr = {(r_laddr[31:3]+'h1), 3'h0};
                        rin_size = r_size - (4'h8 - r_laddr[2:0]);
                        rin_raddr = r_raddr + (4'h8 - r_laddr[2:0]);

                        next_ctrl_mas_state = S_CTRL_MAS_MEM_WRITE1;
                    end


                    else begin
                        rin_tmp_size = 'd0;

                        if (r_opcode == TCU_OPCODE_WRITE) begin
                            next_ctrl_mas_state = S_CTRL_MAS_WAIT_ACK;
                        end else begin
                            next_ctrl_mas_state = S_CTRL_MAS_FINISH;
                        end
                    end
                end


                else if (mas_mem_stall_i && (TIMEOUT_SEND_CYCLES != 32'h0)) begin
                    rin_mas_timeout = r_mas_timeout + 32'd1;
                    if (r_mas_timeout > TIMEOUT_SEND_CYCLES) begin
                        rin_mas_error = TCU_ERROR_TIMEOUT_MEM;



                        if ((r_opcode == TCU_OPCODE_WRITE_RSP) || (r_opcode == TCU_OPCODE_WRITE_RSP_2)) begin
                            rin_opcode = TCU_OPCODE_WRITE_ERROR;
                            next_ctrl_mas_state = S_CTRL_MAS_REQ_ERROR;
                        end
                        else begin
                            next_ctrl_mas_state = S_CTRL_MAS_FINISH;
                        end
                    end
                end
            end

            S_CTRL_MAS_MEM_WRITE2: begin

                if (mas_abort_i) begin
                    rin_mas_error = TCU_ERROR_ABORT;
                    next_ctrl_mas_state = S_CTRL_MAS_FINISH;
                end
                else if (!mas_mem_stall_i && !noc_stall_i) begin
                    rin_size = r_size - r_tmp_size;


                    if (r_tmp_size > 'd8) begin


                        noc_wrreq_o = 1'b1;
                        noc_burst_o = 1'b1;


                        if (r_size[31:4] < MAX_BURST_LENGTH) begin
                            noc_bsel_o = {(((r_laddr[3:0]+r_tmp_size[3:0]) & 4'hF) - 'b1), ~r_laddr[3:0]};




                            noc_data0_o = r_tmp_size[15:4] + ((end_addr != 5'd0) ? 1 : 0) + ((end_addr > 5'd16) ? 1 : 0);
                        end
                        else begin
                            noc_bsel_o = {{(NOC_BSEL_SIZE/2){1'b1}}, ~r_laddr[3:0]};
                            noc_data0_o = MAX_BURST_LENGTH;
                        end

                        rin_laddr = r_laddr + 'd16;
                        rin_raddr = r_raddr + (5'd16 - r_laddr[3:0]);


                        if (burst_length == 'd1) begin
                            rin_tmp_size = 'd0;
                        end else begin
                            rin_tmp_size = r_tmp_size - (5'd16 - r_laddr[3:0]);
                        end

                        next_ctrl_mas_state = S_CTRL_MAS_MEM_WRITE3;
                    end


                    else begin
                        rin_tmp_size = 'd0;
                        noc_burst_o = 1'b0;
                        noc_bsel_o = set_bsel8(r_laddr[2:0], r_tmp_size[3:0]);


                        if (r_opcode == TCU_OPCODE_WRITE) begin
                            next_ctrl_mas_state = S_CTRL_MAS_WAIT_ACK;
                        end else begin
                            next_ctrl_mas_state = S_CTRL_MAS_FINISH;
                        end
                    end
                end


                else if (mas_mem_stall_i && (TIMEOUT_SEND_CYCLES != 32'h0)) begin
                    rin_mas_timeout = r_mas_timeout + 32'd1;
                    if (r_mas_timeout > TIMEOUT_SEND_CYCLES) begin
                        rin_mas_error = TCU_ERROR_TIMEOUT_MEM;
                        


                        if ((r_opcode == TCU_OPCODE_WRITE_RSP) || (r_opcode == TCU_OPCODE_WRITE_RSP_2)) begin
                            rin_opcode = TCU_OPCODE_WRITE_ERROR;
                            next_ctrl_mas_state = S_CTRL_MAS_REQ_ERROR;
                        end
                        else begin
                            next_ctrl_mas_state = S_CTRL_MAS_FINISH;
                        end
                    end
                end
            end

            S_CTRL_MAS_MEM_WRITE3: begin
                if (!noc_stall_i) begin

                    if (mas_mem_stall_i && (r_tmp_size > 'd0)) begin
                        noc_burst_o = 1'b1;
                        noc_bsel_o = {NOC_BSEL_SIZE{1'b1}};
                        next_ctrl_mas_state = S_CTRL_MAS_MEM_WRITE3;


                        if (mas_abort_i) begin
                            noc_bsel_o = {NOC_BSEL_SIZE{1'b0}};
                            rin_mas_error = TCU_ERROR_ABORT;
                            next_ctrl_mas_state = S_CTRL_MAS_ABORT;
                        end


                        else if (TIMEOUT_SEND_CYCLES != 32'h0) begin
                            rin_mas_timeout = r_mas_timeout + 32'd1;
                            if (r_mas_timeout > TIMEOUT_SEND_CYCLES) begin
                                noc_bsel_o = {NOC_BSEL_SIZE{1'b0}};
                                rin_mas_error = TCU_ERROR_TIMEOUT_MEM;
                                next_ctrl_mas_state = S_CTRL_MAS_ABORT;
                            end
                        end
                    end
                    else begin
                        noc_bsel_o = {NOC_BSEL_SIZE{1'b1}};


                        if (r_tmp_size > 'd0) begin
                            
                            rin_laddr = r_laddr + 'd16;
                            rin_tmp_size  = (r_tmp_size > 'd16) ? (r_tmp_size - 'd16) : 'd0;
                            rin_raddr = r_raddr + 'd16;

                            noc_burst_o = 1'b1;


                            if (mas_abort_i) begin
                                noc_bsel_o = {NOC_BSEL_SIZE{1'b0}};
                                rin_mas_error = TCU_ERROR_ABORT;
                                next_ctrl_mas_state = S_CTRL_MAS_ABORT;
                            end
                            else begin
                                next_ctrl_mas_state = S_CTRL_MAS_MEM_WRITE3;
                            end
                        end


                        else begin
                            noc_burst_o = 1'b0;
                        

                            if (r_size > 'h0) begin
                                rin_laddr = {r_laddr[31:4], 4'h0};

                                if (r_size[31:4] < MAX_BURST_LENGTH) begin
                                    rin_tmp_size = r_size[15:0]; 
                                end else begin
                                    rin_tmp_size = MAX_BURST_LENGTH << 4;
                                end

                                next_ctrl_mas_state = S_CTRL_MAS_MEM_WRITE2;
                            end


                            else if (r_opcode == TCU_OPCODE_WRITE) begin
                                next_ctrl_mas_state = S_CTRL_MAS_WAIT_ACK;
                            end else begin
                                next_ctrl_mas_state = S_CTRL_MAS_FINISH;
                            end
                        end
                    end
                end
            end




            S_CTRL_MAS_REQ_ERROR: begin
                if (!noc_stall_i) begin
                    noc_wrreq_o = 1'b1;
                    noc_bsel_o = {NOC_BSEL_SIZE{1'b1}};
                    noc_data0_o = r_mas_error;

                    next_ctrl_mas_state = S_CTRL_MAS_FINISH;
                end
            end




            S_CTRL_MAS_ABORT: begin
                noc_bsel_o = {NOC_BSEL_SIZE{1'b0}};
                
                if (!noc_stall_i) begin
                    noc_wrreq_o = 1'b1;

                    if (r_tmp_size > 'd16) begin
                        rin_tmp_size = r_tmp_size - 'd16;
                        noc_burst_o = 1'b1;
                    end


                    else begin
                        rin_size = 'd0;
                        rin_tmp_size = 'd0;
                        noc_burst_o = 1'b0;
                        next_ctrl_mas_state = S_CTRL_MAS_FINISH;
                    end
                end
            end




            S_CTRL_MAS_WAIT_ACK: begin

                if ((r_write_raddr >= TCU_REGADDR_START) || (r_ack_size >= r_write_size)) begin
                    next_ctrl_mas_state = S_CTRL_MAS_FINISH;
                end


                else if (TIMEOUT_SEND_CYCLES != 32'h0) begin
                    rin_mas_timeout = r_mas_timeout + 32'd1;
                    if (r_mas_timeout > TIMEOUT_SEND_CYCLES) begin
                        rin_mas_error = TCU_ERROR_TIMEOUT_NOC;
                        next_ctrl_mas_state = S_CTRL_MAS_FINISH;
                    end
                end
            end


            S_CTRL_MAS_FINISH: begin

                if (!noc_stall_i) begin
                    next_ctrl_mas_state = S_CTRL_MAS_IDLE;
                end
            end

            default: next_ctrl_mas_state = S_CTRL_MAS_IDLE;

        endcase
    end




    always @* begin
        rin_ack_size = r_ack_size;


        if (mas_active_o && (r_opcode == TCU_OPCODE_WRITE)) begin
            if (noc_ack_recv_i &&
                (noc_ack_chipid_i == r_chipid) &&
                (noc_ack_modid_i == r_modid) &&
                (noc_ack_addr_i >= r_write_raddr) && (noc_ack_addr_i < write_addr_end)) begin
                rin_ack_size = r_ack_size + noc_ack_size_i;
            end
        end
        else begin
            rin_ack_size = 32'h0;
        end
    end




    always @* begin
        mas_mem_en_o = 2'b00;

        if (ctrl_mas_state == S_CTRL_MAS_PREPARE_MEM1) begin
            mas_mem_en_o = 2'b10;
        end
        if ((ctrl_mas_state == S_CTRL_MAS_MEM_WRITE1) ||
            (ctrl_mas_state == S_CTRL_MAS_MEM_WRITE2) ||
            ((ctrl_mas_state == S_CTRL_MAS_MEM_WRITE3) && (r_tmp_size > 'd0))) begin
            mas_mem_en_o = 2'b01;
        end
    end


    assign mas_mem_addr_o = r_laddr;
    assign mas_mem_rdata_valid_o = r_mas_mem_en && !r_stall;
    assign mas_mem_wdata_o = r_size;

    assign mas_error_o = r_mas_error;
    assign mas_active_o = (ctrl_mas_state != S_CTRL_MAS_IDLE);
    assign mas_noc_active_o = mas_active_o && (ctrl_mas_state < S_CTRL_MAS_WAIT_ACK);
    assign mas_done_o = (ctrl_mas_state == S_CTRL_MAS_FINISH) && !noc_stall_i;

    assign noc_addr_o = r_raddr;
    assign noc_chipid_o = r_chipid;
    assign noc_modid_o = r_modid;
    
    

    always @* begin
        case (r_opcode)
            TCU_OPCODE_WRITE:       noc_mode_o = MODE_WRITE_POSTED;
            TCU_OPCODE_WRITE_RSP:   noc_mode_o = MODE_READ_RSP;
            TCU_OPCODE_WRITE_RSP_2: noc_mode_o = MODE_READ_RSP_2;
            TCU_OPCODE_WRITE_ERROR: noc_mode_o = MODE_ERROR;
            default:                noc_mode_o = MODE_WRITE_POSTED;
        endcase
    end

    
endmodule