data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Saber_blocks/s_mul.v
data/verilator_xmls/56879d82-ea8c-4af8-a785-f78c6ef3024e.xml
module small_alu(Ri, a, s, s_sign, result);
input [12:0] Ri, a;
input [2:0] s;
input s_sign;
output [12:0] result;

wire [12:0] ax3 = a + {a[11:0],1'b0};

wire [12:0] a_mul_s = (s==3'd0) ? 13'd0
					:(s==3'd1) ? a
					:(s==3'd2) ? {a[11:0],1'b0}
					:(s==3'd3) ? ax3
					:{a[10:0],2'b00};
					
wire [12:0] result = (s_sign) ? (Ri - a_mul_s) : (Ri + a_mul_s);

endmodule
module small_alu(Ri, a, s, s_sign, result);

input [12:0] Ri, a;
input [2:0] s;
input s_sign;
output [12:0] result;

wire [12:0] ax3 = a + {a[11:0],1'b0};

wire [12:0] a_mul_s = (s==3'd0) ? 13'd0
					:(s==3'd1) ? a
					:(s==3'd2) ? {a[11:0],1'b0}
					:(s==3'd3) ? ax3
					:{a[10:0],2'b00};
					
wire [12:0] result = (s_sign) ? (Ri - a_mul_s) : (Ri + a_mul_s);

endmodule