data/full_repos/permissive/479997390/src/MIPS_tb.v
1: b'%Error: data/full_repos/permissive/479997390/src/MIPS_tb.v:12: Unsupported or unknown PLI call: $monitor\n    $monitor("PC = 0x%8X, IR = 0x%8X", U_MIPS.U_IF.U_PC, U_MIPS.U_IF.Instr ); \n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/479997390/src/MIPS_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #5 ;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/479997390/src/MIPS_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #20 ;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/479997390/src/MIPS_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #(50) clk = ~clk;\n    ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module MIPS_tb ();
  reg clk, rst;

  MIPS_Pipeline U_MIPS(
    .clk(clk), 
    .rst(rst)
  );

  initial begin
    $readmemh( "../test21.txt" , U_MIPS.U_IF.U_IM4K.imem ) ;
    $monitor("PC = 0x%8X, IR = 0x%8X", U_MIPS.U_IF.U_PC, U_MIPS.U_IF.Instr ); 
    clk = 1 ;
    rst = 0 ;
    #5 ;
    rst = 1 ;
    #20 ;
    rst = 0 ;
  end
  
  always
    #(50) clk = ~clk;
  
endmodule
module MIPS_tb ();

  reg clk, rst;

  MIPS_Pipeline U_MIPS(
    .clk(clk), 
    .rst(rst)
  );

  initial begin
    $readmemh( "../test21.txt" , U_MIPS.U_IF.U_IM4K.imem ) ;
    $monitor("PC = 0x%8X, IR = 0x%8X", U_MIPS.U_IF.U_PC, U_MIPS.U_IF.Instr ); 
    clk = 1 ;
    rst = 0 ;
    #5 ;
    rst = 1 ;
    #20 ;
    rst = 0 ;
  end
  
  always
    #(50) clk = ~clk;
  
endmodule