data/full_repos/permissive/424312442/lab_5_seven seg displays/sources_1/new/bcd_seg_complete.v
1: b'%Error: Cannot find file containing module: seg\n        ... Looked in:\n             data/full_repos/permissive/424312442/lab_5_seven/seg\n             data/full_repos/permissive/424312442/lab_5_seven/seg.v\n             data/full_repos/permissive/424312442/lab_5_seven/seg.sv\n             seg\n             seg.v\n             seg.sv\n             obj_dir/seg\n             obj_dir/seg.v\n             obj_dir/seg.sv\n%Error: Cannot find file containing module: displays/sources_1/new,data/full_repos/permissive/424312442\n%Error: Cannot find file containing module: data/full_repos/permissive/424312442/lab_5_seven\n%Error: Cannot find file containing module: displays/sources_1/new/bcd_seg_complete.v\n%Error: Exiting due to 4 error(s)\n'
module complete_tb;
reg CLK;
reg [3:0] BCD0;
reg [3:0] BCD1;
reg [3:0] BCD2;
reg [3:0] BCD3;
wire [3:0] AN;
wire [6:0] SEGN;

always
begin
    CLK = 1'b0;
    #5;
    CLK = 1'b1;
    #5;
end

bcd_seg_complete dut (CLK, BCD0, BCD1, BCD2, BCD3, AN, SEGN);

initial begin
    BCD0 = 4'b0000;
    BCD1 = 4'b0000;
    BCD2 = 4'b0000;
    BCD3 = 4'b0000;
    #250
    BCD0 = 4'b0001;
    BCD1 = 4'b0010;
    BCD2 = 4'b0011;
    BCD3 = 4'b0100;
    #250
    BCD0 = 4'b0101;
    BCD1 = 4'b0110;
    BCD2 = 4'b0111;
    BCD3 = 4'b1000;
    #250
    BCD0 = 4'b1001;
    BCD1 = 4'b1010;
    BCD2 = 4'b1101;
    BCD3 = 4'b1111;
end
endmodule
module complete_tb;

reg CLK;
reg [3:0] BCD0;
reg [3:0] BCD1;
reg [3:0] BCD2;
reg [3:0] BCD3;
wire [3:0] AN;
wire [6:0] SEGN;

always
begin
    CLK = 1'b0;
    #5;
    CLK = 1'b1;
    #5;
end

bcd_seg_complete dut (CLK, BCD0, BCD1, BCD2, BCD3, AN, SEGN);

initial begin
    BCD0 = 4'b0000;
    BCD1 = 4'b0000;
    BCD2 = 4'b0000;
    BCD3 = 4'b0000;
    #250
    BCD0 = 4'b0001;
    BCD1 = 4'b0010;
    BCD2 = 4'b0011;
    BCD3 = 4'b0100;
    #250
    BCD0 = 4'b0101;
    BCD1 = 4'b0110;
    BCD2 = 4'b0111;
    BCD3 = 4'b1000;
    #250
    BCD0 = 4'b1001;
    BCD1 = 4'b1010;
    BCD2 = 4'b1101;
    BCD3 = 4'b1111;
end
endmodule