data/full_repos/permissive/451853158/MIPS_Multi_Cycle_Processor/instrdataMem.v
data/verilator_xmls/2bf9ccd8-7b40-430b-8f1b-9444d735546f.xml
module instrdataMem (
  input              clk, wrEn,
  input       [31:0] addr,
  input       [31:0] wrData,
  output wire [31:0] rdData
);



reg [31:0] mem [63:0];

always @(posedge clk)
  if (wrEn)
    mem[addr[7:2]] = wrData;

assign rdData = mem[addr[7:2]];

initial $readmemh("memfile.dat", mem);

endmodule
module instrdataMem (
  input              clk, wrEn,
  input       [31:0] addr,
  input       [31:0] wrData,
  output wire [31:0] rdData
);




reg [31:0] mem [63:0];

always @(posedge clk)
  if (wrEn)
    mem[addr[7:2]] = wrData;

assign rdData = mem[addr[7:2]];

initial $readmemh("memfile.dat", mem);

endmodule