data/full_repos/permissive/487478597/riscv_pipedline_cpu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:307: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Raddr1 = instruction[19:15];\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:308: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Raddr2 = instruction[24:20];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:309: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Waddr = instruction[11:7];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:26: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s EQ generates 1 bits.\n                                                                             : ... In instance top.uut11\n            4\'h4: ALUResult = (in1 == in2);  \n                            ^\n%Error: Exiting due to 4 warning(s)\n'
module forward_unit #(parameter addr_width = 8)(
    input [addr_width-1:0] rs1,
    input [addr_width-1:0] rs2,
    input [addr_width-1:0] MEM_rd,
    input [addr_width-1:0] WB_rd,
    input MEM_RegWrite,
    input WB_RegWrite,
    output reg [1:0] forward_A,
    output reg [1:0] forward_B 
);
    initial begin forward_A = 0; forward_B = 0; end
    always @(*) begin
        if (MEM_RegWrite == 1'b1 & MEM_rd != 0 & MEM_rd == rs1) begin forward_A <= 2'b10; end
        else if (WB_RegWrite == 1'b1 & WB_rd != 0 & WB_rd == rs1) begin forward_A <= 2'b01; end
        else begin forward_A <= 0; end
    end
    always @(*) begin
        if (MEM_RegWrite == 1'b1 & MEM_rd != 0 & MEM_rd == rs2) begin forward_B <= 2'b10; end
        else if (WB_RegWrite == 1'b1 & WB_rd != 0 & WB_rd == rs2) begin forward_B <= 2'b01; end
        else begin forward_B <= 0; end
    end
endmodule
module forward_unit #(parameter addr_width = 8)(
    input [addr_width-1:0] rs1,
    input [addr_width-1:0] rs2,
    input [addr_width-1:0] MEM_rd,
    input [addr_width-1:0] WB_rd,
    input MEM_RegWrite,
    input WB_RegWrite,
    output reg [1:0] forward_A,
    output reg [1:0] forward_B 
);

    initial begin forward_A = 0; forward_B = 0; end
    always @(*) begin
        if (MEM_RegWrite == 1'b1 & MEM_rd != 0 & MEM_rd == rs1) begin forward_A <= 2'b10; end
        else if (WB_RegWrite == 1'b1 & WB_rd != 0 & WB_rd == rs1) begin forward_A <= 2'b01; end
        else begin forward_A <= 0; end
    end
    always @(*) begin
        if (MEM_RegWrite == 1'b1 & MEM_rd != 0 & MEM_rd == rs2) begin forward_B <= 2'b10; end
        else if (WB_RegWrite == 1'b1 & WB_rd != 0 & WB_rd == rs2) begin forward_B <= 2'b01; end
        else begin forward_B <= 0; end
    end
endmodule