data/full_repos/permissive/418819021/lab-08/interrupt_controller.v
1: b'%Error: data/full_repos/permissive/418819021/lab-08/interrupt_controller.v:4: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418819021/lab-08,data/full_repos/permissive/418819021/defines.vh\n             data/full_repos/permissive/418819021/lab-08,data/full_repos/permissive/418819021/defines.vh.v\n             data/full_repos/permissive/418819021/lab-08,data/full_repos/permissive/418819021/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/418819021/lab-08/interrupt_controller.v:21: Define or directive not defined: \'`FLAGS_I\'\n    assign if_ext  = {DATA_WIDTH{mem_sreg[`FLAGS_I]}};\n                                          ^~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-08/interrupt_controller.v:21: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign if_ext  = {DATA_WIDTH{mem_sreg[`FLAGS_I]}};\n                                                  ^\n%Error: data/full_repos/permissive/418819021/lab-08/interrupt_controller.v:48: Define or directive not defined: \'`OCF0B\'\n            if (int_src[`OCF0B]) begin\n                        ^~~~~~\n%Error: data/full_repos/permissive/418819021/lab-08/interrupt_controller.v:48: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n            if (int_src[`OCF0B]) begin\n                              ^\n%Error: data/full_repos/permissive/418819021/lab-08/interrupt_controller.v:50: Define or directive not defined: \'`TIM0_COMPB_ISR\'\n                vector <= `TIM0_COMPB_ISR;\n                          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-08/interrupt_controller.v:50: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                vector <= `TIM0_COMPB_ISR;\n                                         ^\n%Error: data/full_repos/permissive/418819021/lab-08/interrupt_controller.v:51: Define or directive not defined: \'`OCF0A\'\n            end else if (int_src[`OCF0A]) begin\n                                 ^~~~~~\n%Error: data/full_repos/permissive/418819021/lab-08/interrupt_controller.v:53: Define or directive not defined: \'`TIM0_COMPA_ISR\'\n                vector <= `TIM0_COMPA_ISR;\n                          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-08/interrupt_controller.v:53: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                vector <= `TIM0_COMPA_ISR;\n                                         ^\n%Error: data/full_repos/permissive/418819021/lab-08/interrupt_controller.v:54: Define or directive not defined: \'`TOV0\'\n            end else if (int_src[`TOV0]) begin\n                                 ^~~~~\n%Error: data/full_repos/permissive/418819021/lab-08/interrupt_controller.v:56: Define or directive not defined: \'`TIM0_OVF_ISR\'\n                vector <= `TIM0_OVF_ISR;\n                          ^~~~~~~~~~~~~\n%Error: Cannot continue\n'
module interrupt_controller #(
        parameter   DATA_WIDTH = 8,
        parameter I_ADDR_WIDTH = 10
    )(
        input wire                    clk,
        input wire                    reset,
        input wire   [DATA_WIDTH-1:0] mem_tifr,
        input wire   [DATA_WIDTH-1:0] mem_timsk,
        input wire   [DATA_WIDTH-1:0] mem_sreg,
        output reg                    irq,
        output reg [I_ADDR_WIDTH-1:0] vector
    );

    wire [DATA_WIDTH-1:0] if_ext;
    wire [DATA_WIDTH-1:0] int_src;

    assign if_ext  = {DATA_WIDTH{mem_sreg[`FLAGS_I]}};
    assign int_src = mem_tifr & mem_timsk & if_ext;

    always @(posedge clk) begin
        if (reset) begin
            irq    <= 0;
            vector <= 0;
        end else begin


            if (int_src[`OCF0B]) begin
                irq    <= 1;
                vector <= `TIM0_COMPB_ISR;
            end else if (int_src[`OCF0A]) begin
                irq    <= 1;
                vector <= `TIM0_COMPA_ISR;
            end else if (int_src[`TOV0]) begin
                irq    <= 1;
                vector <= `TIM0_OVF_ISR;
            end else begin
                irq    <= 0;


            end
        end
    end
endmodule
module interrupt_controller #(
        parameter   DATA_WIDTH = 8,
        parameter I_ADDR_WIDTH = 10
    )(
        input wire                    clk,
        input wire                    reset,
        input wire   [DATA_WIDTH-1:0] mem_tifr,
        input wire   [DATA_WIDTH-1:0] mem_timsk,
        input wire   [DATA_WIDTH-1:0] mem_sreg,
        output reg                    irq,
        output reg [I_ADDR_WIDTH-1:0] vector
    );


    wire [DATA_WIDTH-1:0] if_ext;
    wire [DATA_WIDTH-1:0] int_src;

    assign if_ext  = {DATA_WIDTH{mem_sreg[`FLAGS_I]}};
    assign int_src = mem_tifr & mem_timsk & if_ext;

    always @(posedge clk) begin
        if (reset) begin
            irq    <= 0;
            vector <= 0;
        end else begin


            if (int_src[`OCF0B]) begin
                irq    <= 1;
                vector <= `TIM0_COMPB_ISR;
            end else if (int_src[`OCF0A]) begin
                irq    <= 1;
                vector <= `TIM0_COMPA_ISR;
            end else if (int_src[`TOV0]) begin
                irq    <= 1;
                vector <= `TIM0_OVF_ISR;
            end else begin
                irq    <= 0;


            end
        end
    end
endmodule