data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/serial_deglitch.sv
data/verilator_xmls/967e3135-af88-4fbe-a702-0642a464ada4.xml
module serial_deglitch #(
    parameter int unsigned SIZE = 4
)(
    input  logic clk_i,
    input  logic rst_ni,
    input  logic en_i,
    input  logic d_i,
    output logic q_o
);
    logic [SIZE-1:0] count_q;
    logic q;

    always_ff @(posedge clk_i or negedge rst_ni) begin
        if (~rst_ni) begin
            count_q <= '0;
            q       <= 1'b0;
        end else begin
            if (en_i) begin
                if (d_i == 1'b1 && count_q != SIZE[SIZE-1:0]) begin
                    count_q <= count_q + 1;
                end else if (d_i == 1'b0 && count_q != SIZE[SIZE-1:0]) begin
                    count_q <= count_q - 1;
                end
            end
        end
    end


    always_comb begin
        if (count_q == SIZE[SIZE-1:0]) begin
            q_o = 1'b1;
        end else if (count_q == 0) begin
            q_o = 1'b0;
        end
    end
endmodule
module serial_deglitch #(
    parameter int unsigned SIZE = 4
)(
    input  logic clk_i,
    input  logic rst_ni,
    input  logic en_i,
    input  logic d_i,
    output logic q_o
);

    logic [SIZE-1:0] count_q;
    logic q;

    always_ff @(posedge clk_i or negedge rst_ni) begin
        if (~rst_ni) begin
            count_q <= '0;
            q       <= 1'b0;
        end else begin
            if (en_i) begin
                if (d_i == 1'b1 && count_q != SIZE[SIZE-1:0]) begin
                    count_q <= count_q + 1;
                end else if (d_i == 1'b0 && count_q != SIZE[SIZE-1:0]) begin
                    count_q <= count_q - 1;
                end
            end
        end
    end


    always_comb begin
        if (count_q == SIZE[SIZE-1:0]) begin
            q_o = 1'b1;
        end else if (count_q == 0) begin
            q_o = 1'b0;
        end
    end
endmodule