data/full_repos/permissive/452215364/rtl/opl2/operator/tremolo.v
1: b'%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/tremolo.v:51: Cannot find include file: opl3.vh\n`include "opl3.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/452215364/rtl/opl2/operator,data/full_repos/permissive/452215364/opl3.vh\n             data/full_repos/permissive/452215364/rtl/opl2/operator,data/full_repos/permissive/452215364/opl3.vh.v\n             data/full_repos/permissive/452215364/rtl/opl2/operator,data/full_repos/permissive/452215364/opl3.vh.sv\n             opl3.vh\n             opl3.vh.v\n             opl3.vh.sv\n             obj_dir/opl3.vh\n             obj_dir/opl3.vh.v\n             obj_dir/opl3.vh.sv\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/tremolo.v:57: Define or directive not defined: \'`OP_NUM_WIDTH\'\n    input wire [`OP_NUM_WIDTH-1:0] op_num,            \n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/tremolo.v:59: Define or directive not defined: \'`AM_VAL_WIDTH\'\n    output reg [`AM_VAL_WIDTH-1:0] am_val\n                ^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module tremolo (
    input wire clk,
    input wire reset,
    input wire sample_clk_en,
    input wire [`OP_NUM_WIDTH-1:0] op_num,            
    input wire dam,
    output reg [`AM_VAL_WIDTH-1:0] am_val
);
    localparam TREMOLO_MAX_COUNT = 13*1024;
    localparam TREMOLO_INDEX_WIDTH = 14;
    
    reg [TREMOLO_INDEX_WIDTH-1:0] tremolo_index;
    wire [TREMOLO_INDEX_WIDTH-8-1:0] am_val_tmp0;
    wire [TREMOLO_INDEX_WIDTH-8-1:0] am_val_tmp1;
    

    always @(posedge clk)
        if (reset)
            tremolo_index <= 0;
        else if (sample_clk_en && op_num == 0)
            if (tremolo_index == TREMOLO_MAX_COUNT - 1)
                tremolo_index <= 0;
            else
                tremolo_index <= tremolo_index + 1;
    
    assign am_val_tmp0 = tremolo_index >> 8;
    assign am_val_tmp1 = (am_val_tmp0 > 26) ? (2*26 + ~am_val_tmp0) : am_val_tmp0;
        
    always @(posedge clk)
        if (reset)
            am_val <= 0;
        else if (dam)
            am_val <= am_val_tmp1;
        else
            am_val <= am_val_tmp1 >> 2;
endmodule
module tremolo (
    input wire clk,
    input wire reset,
    input wire sample_clk_en,
    input wire [`OP_NUM_WIDTH-1:0] op_num,            
    input wire dam,
    output reg [`AM_VAL_WIDTH-1:0] am_val
);

    localparam TREMOLO_MAX_COUNT = 13*1024;
    localparam TREMOLO_INDEX_WIDTH = 14;
    
    reg [TREMOLO_INDEX_WIDTH-1:0] tremolo_index;
    wire [TREMOLO_INDEX_WIDTH-8-1:0] am_val_tmp0;
    wire [TREMOLO_INDEX_WIDTH-8-1:0] am_val_tmp1;
    

    always @(posedge clk)
        if (reset)
            tremolo_index <= 0;
        else if (sample_clk_en && op_num == 0)
            if (tremolo_index == TREMOLO_MAX_COUNT - 1)
                tremolo_index <= 0;
            else
                tremolo_index <= tremolo_index + 1;
    
    assign am_val_tmp0 = tremolo_index >> 8;
    assign am_val_tmp1 = (am_val_tmp0 > 26) ? (2*26 + ~am_val_tmp0) : am_val_tmp0;
        
    always @(posedge clk)
        if (reset)
            am_val <= 0;
        else if (dam)
            am_val <= am_val_tmp1;
        else
            am_val <= am_val_tmp1 >> 2;
endmodule