data/full_repos/permissive/524553217/testbench/cpu_pdra_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/524553217/testbench/cpu_pdra_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #1 reset_pc = 0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/524553217/testbench/cpu_pdra_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n            #1 clk = ~clk;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/524553217/testbench/cpu_pdra_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n        #20 $stop;\n        ^\n%Error: data/full_repos/permissive/524553217/testbench/cpu_pdra_tb.v:40: Cannot find file containing module: \'mux2to1_32\'\n    mux2to1_32 _jumpsw(jump_e, next_pc, alu_out, pc_in);  \n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/524553217/testbench,data/full_repos/permissive/524553217/mux2to1_32\n             data/full_repos/permissive/524553217/testbench,data/full_repos/permissive/524553217/mux2to1_32.v\n             data/full_repos/permissive/524553217/testbench,data/full_repos/permissive/524553217/mux2to1_32.sv\n             mux2to1_32\n             mux2to1_32.v\n             mux2to1_32.sv\n             obj_dir/mux2to1_32\n             obj_dir/mux2to1_32.v\n             obj_dir/mux2to1_32.sv\n%Error: data/full_repos/permissive/524553217/testbench/cpu_pdra_tb.v:41: Cannot find file containing module: \'adder_32\'\n    adder_32 _pcadd(32\'d4, pc_out, next_pc);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/524553217/testbench/cpu_pdra_tb.v:42: Cannot find file containing module: \'program_counter\'\n    program_counter _pc(pc_in, reset_pc, clk, pc_out);\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/524553217/testbench/cpu_pdra_tb.v:43: Cannot find file containing module: \'instr_memory\'\n    instr_memory _im(pc_out, opcode);\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/524553217/testbench/cpu_pdra_tb.v:45: Cannot find file containing module: \'decoder_core\'\n    decoder_core _dc(opcode, rd_e, rd, rs1_e, rs1, rs2_e, rs2, imm_e, imm, pc_e, jump_e, full_inst);\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/524553217/testbench/cpu_pdra_tb.v:46: Cannot find file containing module: \'register\'\n    register _re(rd_e, rd, rd_v, rs1_e, rs1, rs2_e, rs2, clk, rs1_v, rs2_v);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/524553217/testbench/cpu_pdra_tb.v:48: Cannot find file containing module: \'mux2to1_32\'\n    mux2to1_32 _pcsw(pc_e, rs1_v, pc_out, value_1);  \n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/524553217/testbench/cpu_pdra_tb.v:49: Cannot find file containing module: \'mux2to1_32\'\n    mux2to1_32 _immsw(imm_e, rs2_v, imm, value_2);  \n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/524553217/testbench/cpu_pdra_tb.v:51: Cannot find file containing module: \'alu\'\n    alu _alu(full_inst, value_1, value_2, alu_out);\n    ^~~\n%Error: data/full_repos/permissive/524553217/testbench/cpu_pdra_tb.v:52: Cannot find file containing module: \'branch\'\n    branch _branch(full_inst, rs1_v, rs2_v, branch_e);\n    ^~~~~~\n%Error: data/full_repos/permissive/524553217/testbench/cpu_pdra_tb.v:54: Cannot find file containing module: \'mux4to1_32\'\n    mux4to1_32 rd_sw({1\'b0, branch_e}, alu_out, next_pc, 32\'b0, 32\'b0, rd_v);  \n    ^~~~~~~~~~\n%Error: Exiting due to 11 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cpu_pdra_tb(

    );

    reg clk;
    reg reset_pc;

    wire branch_e, jump_e;
    wire [31:0] pc_in, pc_out, next_pc;
    wire [31:0] opcode;
    wire rd_e, rs1_e, rs2_e, imm_e, pc_e;
    wire [4:0] rd, rs1, rs2;
    wire [16:0] full_inst;
    wire [31:0] rd_v, rs1_v, rs2_v, imm;
    wire [31:0] value_1, value_2;
    wire [31:0] alu_out;

    mux2to1_32 _jumpsw(jump_e, next_pc, alu_out, pc_in);
    adder_32 _pcadd(32'd4, pc_out, next_pc);
    program_counter _pc(pc_in, reset_pc, clk, pc_out);
    instr_memory _im(pc_out, opcode);

    decoder_core _dc(opcode, rd_e, rd, rs1_e, rs1, rs2_e, rs2, imm_e, imm, pc_e, jump_e, full_inst);
    register _re(rd_e, rd, rd_v, rs1_e, rs1, rs2_e, rs2, clk, rs1_v, rs2_v);

    mux2to1_32 _pcsw(pc_e, rs1_v, pc_out, value_1);
    mux2to1_32 _immsw(imm_e, rs2_v, imm, value_2);

    alu _alu(full_inst, value_1, value_2, alu_out);
    branch _branch(full_inst, rs1_v, rs2_v, branch_e);

    mux4to1_32 rd_sw({1'b0, branch_e}, alu_out, next_pc, 32'b0, 32'b0, rd_v);

    initial begin
        clk = 0; reset_pc = 1;
        #1 reset_pc = 0;
        forever begin
            #1 clk = ~clk;
        end
    end

    initial begin
        #20 $stop;
    end

endmodule
module cpu_pdra_tb(

    );


    reg clk;
    reg reset_pc;

    wire branch_e, jump_e;
    wire [31:0] pc_in, pc_out, next_pc;
    wire [31:0] opcode;
    wire rd_e, rs1_e, rs2_e, imm_e, pc_e;
    wire [4:0] rd, rs1, rs2;
    wire [16:0] full_inst;
    wire [31:0] rd_v, rs1_v, rs2_v, imm;
    wire [31:0] value_1, value_2;
    wire [31:0] alu_out;

    mux2to1_32 _jumpsw(jump_e, next_pc, alu_out, pc_in);
    adder_32 _pcadd(32'd4, pc_out, next_pc);
    program_counter _pc(pc_in, reset_pc, clk, pc_out);
    instr_memory _im(pc_out, opcode);

    decoder_core _dc(opcode, rd_e, rd, rs1_e, rs1, rs2_e, rs2, imm_e, imm, pc_e, jump_e, full_inst);
    register _re(rd_e, rd, rd_v, rs1_e, rs1, rs2_e, rs2, clk, rs1_v, rs2_v);

    mux2to1_32 _pcsw(pc_e, rs1_v, pc_out, value_1);
    mux2to1_32 _immsw(imm_e, rs2_v, imm, value_2);

    alu _alu(full_inst, value_1, value_2, alu_out);
    branch _branch(full_inst, rs1_v, rs2_v, branch_e);

    mux4to1_32 rd_sw({1'b0, branch_e}, alu_out, next_pc, 32'b0, 32'b0, rd_v);

    initial begin
        clk = 0; reset_pc = 1;
        #1 reset_pc = 0;
        forever begin
            #1 clk = ~clk;
        end
    end

    initial begin
        #20 $stop;
    end

endmodule