data/full_repos/permissive/428125225/fifo_in_out.v
1: b"%Error: data/full_repos/permissive/428125225/fifo_in_out.v:13: Duplicate declaration of signal: 'vs_s'\n                                                             : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nwire            vs_s    ;        \n                ^~~~\n        data/full_repos/permissive/428125225/fifo_in_out.v:6: ... Location of original declaration\n    input       vs_s       ,\n                ^~~~\n%Error: data/full_repos/permissive/428125225/fifo_in_out.v:16: Duplicate declaration of signal: 'sum1'\nwire     [8:0]    sum1   ;\n                  ^~~~\n        data/full_repos/permissive/428125225/fifo_in_out.v:5: ... Location of original declaration\n    input [8:0] sum1       , \n                ^~~~\n%Error: data/full_repos/permissive/428125225/fifo_in_out.v:17: Duplicate declaration of signal: 'rdreq'\nwire            rdreq   ;        \n                ^~~~~\n        data/full_repos/permissive/428125225/fifo_in_out.v:8: ... Location of original declaration\n    output       rdreq      \n                 ^~~~~\n%Error: Exiting due to 3 error(s)\n"
module fifo_in_out(
    input       sys_clk    ,
    input       cj_clk     ,
    input       rst_n      ,
    input [8:0] sum1       , 
    input       vs_s       ,
    output      data_fifo  ,
    output       rdreq      
);



wire            vs_s    ;        
wire   [8:0]    data    ;         

wire     [8:0]    sum1   ;
wire            rdreq   ;        
wire    [8:0]   q       ;         
wire            empty ;        
wire            full  ;         

















fifo u_fifo(
    .wr_data(sum1),
    .wr_en(vs_s),
    .wr_clk(cj_clk),
    .full(),
    .wr_rst(~rst_n ),
    .almost_full(  full   ),
    .rd_data(data),
    .rd_en(rdreq),
    .rd_clk(sys_clk),
    .empty(),
    .rd_rst(~rst_n ),
    .almost_empty(   empty      )
);



fifo_rd u_fifo_rd(
    .clk     (sys_clk ),
    .rst_n   (~rst_n   ),

    .rdreq   (rdreq   ),
    .data     (data       ),
    .empty (empty ),
    .full  (full  ),
    .fifodate  (data_fifo)
   
);

endmodule
module fifo_in_out(
    input       sys_clk    ,
    input       cj_clk     ,
    input       rst_n      ,
    input [8:0] sum1       , 
    input       vs_s       ,
    output      data_fifo  ,
    output       rdreq      
);




wire            vs_s    ;        
wire   [8:0]    data    ;         

wire     [8:0]    sum1   ;
wire            rdreq   ;        
wire    [8:0]   q       ;         
wire            empty ;        
wire            full  ;         

















fifo u_fifo(
    .wr_data(sum1),
    .wr_en(vs_s),
    .wr_clk(cj_clk),
    .full(),
    .wr_rst(~rst_n ),
    .almost_full(  full   ),
    .rd_data(data),
    .rd_en(rdreq),
    .rd_clk(sys_clk),
    .empty(),
    .rd_rst(~rst_n ),
    .almost_empty(   empty      )
);



fifo_rd u_fifo_rd(
    .clk     (sys_clk ),
    .rst_n   (~rst_n   ),

    .rdreq   (rdreq   ),
    .data     (data       ),
    .empty (empty ),
    .full  (full  ),
    .fifodate  (data_fifo)
   
);

endmodule