data/full_repos/permissive/521695319/async_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/521695319/async_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n            #(T_WRITE/2)\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/521695319/async_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n            #(T_READ/2)\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/521695319/async_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n            #(T_READ/4);       \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/521695319/async_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n            #(DELAY); \n            ^\n%Error: data/full_repos/permissive/521695319/async_tb.v:93: syntax error, unexpected \'@\'\n            @(posedge r_clk) w_en = 1; \n            ^\n%Error: data/full_repos/permissive/521695319/async_tb.v:96: syntax error, unexpected \'@\'\n                    @(posedge w_clk) in = i+7;  \n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/521695319/async_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n            #(T_READ/2);\n            ^\n%Error: data/full_repos/permissive/521695319/async_tb.v:107: syntax error, unexpected \'@\'\n                    @(posedge r_clk)\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/521695319/async_tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n            #(T_WRITE/2);\n            ^\n%Error: data/full_repos/permissive/521695319/async_tb.v:117: syntax error, unexpected \'@\'\n                    @(posedge w_clk) in = (i ^ 7) + 7;\n                    ^\n%Error: Exiting due to 4 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module async_fifo_tb
    #(  parameter WIDTH   = 5,
        parameter DEPTH   = 16,   
        parameter T_READ  = 20,
        parameter T_WRITE = 10 
     );
     
     reg                w_clk;
     reg                w_en;
     reg [WIDTH - 1:0]  in;
     wire               full;
     wire               almost_full;
     
     reg                r_clk; 
     reg                r_en; 
     wire [WIDTH - 1:0] out; 
     wire               empty;
     wire               almost_empty; 


    always
        begin
            #(T_WRITE/2)
            w_clk <= (~w_clk);
        end          
    

    always
        begin
            #(T_READ/2)
            r_clk <= (~r_clk);
        end
        
    reg rst;    
    reg r1_r_rst, r2_r_rst; 
    reg r1_w_rst, r2_w_rst;
    
    initial
        begin
            w_en   = 0;
            r_en   = 0;
            in     = 0;
            w_clk  = 0;
            r_clk  = 0;
            rst    = 1;
            #(T_READ/4);       
            rst    = 0;
        end
        

    
    always @(posedge r_clk or posedge rst)
        begin
            if(rst) {r2_r_rst, r1_r_rst} <= {2'b11};
            else    {r2_r_rst, r1_r_rst} <= {r1_r_rst, 1'b0};               
        end 
    always @(posedge w_clk or posedge rst)
        begin
            if(rst) {r2_w_rst, r1_w_rst} <= {2'b11};
            else    {r2_w_rst, r1_w_rst} <= {r1_w_rst, 1'b0}; 
        end 
    
    async_fifo #( .DEPTH(DEPTH), .WIDTH(WIDTH))
    UUT
    (   .w_clk(w_clk                 ),
        .w_rst(r2_w_rst              ),
        .w_en(w_en                   ),
        .i_dat(in                    ),
        .w_full(full                 ),
        .w_almost_full(almost_full   ),
        
        .r_clk(r_clk                 ),
        .r_rst(r2_r_rst              ),
        .r_en(r_en                   ),
        .o_dat(out                   ),
        .r_empty(empty               ),
        .r_almost_empty(almost_empty )
     );   
    


    
    localparam DELAY  = 3*T_READ;
    initial
        begin: TB
            integer i;
            #(DELAY); 
            


            @(posedge r_clk) w_en = 1; 
            for(i = 0; i < DEPTH+5; i = i + 1)
                begin
                    @(posedge w_clk) in = i+7;  
                end 
                 
            @(posedge w_clk) w_en = 0; 
            #(T_READ/2);
            r_en = 1; 
            


            for(i = 0; i < DEPTH+5; i = i + 1)
                begin
                    @(posedge r_clk)
                    ;               
                end
                
            @(posedge w_clk) w_en = 1;
            #(T_WRITE/2);
             

            for(i = 0; i < DEPTH+10; i = i + 1)
                begin
                    @(posedge w_clk) in = (i ^ 7) + 7;
                end     
            $finish(); 
                 
        end
endmodule
module async_fifo_tb
    #(  parameter WIDTH   = 5,
        parameter DEPTH   = 16,   
        parameter T_READ  = 20,
        parameter T_WRITE = 10 
     );

     
     reg                w_clk;
     reg                w_en;
     reg [WIDTH - 1:0]  in;
     wire               full;
     wire               almost_full;
     
     reg                r_clk; 
     reg                r_en; 
     wire [WIDTH - 1:0] out; 
     wire               empty;
     wire               almost_empty; 


    always
        begin
            #(T_WRITE/2)
            w_clk <= (~w_clk);
        end          
    

    always
        begin
            #(T_READ/2)
            r_clk <= (~r_clk);
        end
        
    reg rst;    
    reg r1_r_rst, r2_r_rst; 
    reg r1_w_rst, r2_w_rst;
    
    initial
        begin
            w_en   = 0;
            r_en   = 0;
            in     = 0;
            w_clk  = 0;
            r_clk  = 0;
            rst    = 1;
            #(T_READ/4);       
            rst    = 0;
        end
        

    
    always @(posedge r_clk or posedge rst)
        begin
            if(rst) {r2_r_rst, r1_r_rst} <= {2'b11};
            else    {r2_r_rst, r1_r_rst} <= {r1_r_rst, 1'b0};               
        end 
    always @(posedge w_clk or posedge rst)
        begin
            if(rst) {r2_w_rst, r1_w_rst} <= {2'b11};
            else    {r2_w_rst, r1_w_rst} <= {r1_w_rst, 1'b0}; 
        end 
    
    async_fifo #( .DEPTH(DEPTH), .WIDTH(WIDTH))
    UUT
    (   .w_clk(w_clk                 ),
        .w_rst(r2_w_rst              ),
        .w_en(w_en                   ),
        .i_dat(in                    ),
        .w_full(full                 ),
        .w_almost_full(almost_full   ),
        
        .r_clk(r_clk                 ),
        .r_rst(r2_r_rst              ),
        .r_en(r_en                   ),
        .o_dat(out                   ),
        .r_empty(empty               ),
        .r_almost_empty(almost_empty )
     );   
    


    
    localparam DELAY  = 3*T_READ;
    initial
        begin: TB
            integer i;
            #(DELAY); 
            


            @(posedge r_clk) w_en = 1; 
            for(i = 0; i < DEPTH+5; i = i + 1)
                begin
                    @(posedge w_clk) in = i+7;  
                end 
                 
            @(posedge w_clk) w_en = 0; 
            #(T_READ/2);
            r_en = 1; 
            


            for(i = 0; i < DEPTH+5; i = i + 1)
                begin
                    @(posedge r_clk)
                    ;               
                end
                
            @(posedge w_clk) w_en = 1;
            #(T_WRITE/2);
             

            for(i = 0; i < DEPTH+10; i = i + 1)
                begin
                    @(posedge w_clk) in = (i ^ 7) + 7;
                end     
            $finish(); 
                 
        end
endmodule