data/full_repos/permissive/472385934/multipler.v
data/verilator_xmls/c40ea4d1-47fe-45f0-8199-3bd6aa679241.xml
module multipler(
input [31:0] a,
input [31:0] b,
input clk,
input sign,
output reg [31:0]multout);

wire signed [31:0]a_sign,b_sign;
reg signed [31:0]multout_sign;

always@(*) begin
    if (sign) 
        multout = a*b;
    else begin
        multout_sign = a_sign*b_sign;
        multout = multout_sign;
    end
end

endmodule
module multipler(
input [31:0] a,
input [31:0] b,
input clk,
input sign,
output reg [31:0]multout);


wire signed [31:0]a_sign,b_sign;
reg signed [31:0]multout_sign;

always@(*) begin
    if (sign) 
        multout = a*b;
    else begin
        multout_sign = a_sign*b_sign;
        multout = multout_sign;
    end
end

endmodule