data/full_repos/permissive/45677639/rtl/mips_fifosync.v
1: b'%Warning-WIDTH: data/full_repos/permissive/45677639/rtl/mips_fifosync.v:44: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n                                                                          : ... In instance mips_fifosync\n    wr_counter<= {(SPOWER2_MEM){1\'b0}};\n              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/45677639/rtl/mips_fifosync.v:45: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n                                                                          : ... In instance mips_fifosync\n    rd_counter<= {(SPOWER2_MEM){1\'b0}};\n              ^~\n%Error: Exiting due to 2 warning(s)\n'
module mips_fifosync #(parameter S_WORD= 8,
                       parameter SPOWER2_MEM= 4)
                      (
                      input               clk,
                      input               rst,

                      input               wr_en,
                      input[S_WORD-1:0]   wr_data,

                      input               rd_en,
                      output[S_WORD-1:0]  rd_data,

                      output              fifo_full,
                      output              fifo_empty
                      );




  localparam         S_MEM= 1<<SPOWER2_MEM;
	reg[S_WORD-1:0]    mem[S_MEM-1:0];
	reg[SPOWER2_MEM:0] wr_counter;
	reg[SPOWER2_MEM:0] rd_counter;




  assign rd_data=    mem[rd_counter[SPOWER2_MEM-1:0]];
  assign fifo_empty= wr_counter==rd_counter;
  assign fifo_full=  wr_counter[SPOWER2_MEM]!=rd_counter[SPOWER2_MEM] &
                     wr_counter[SPOWER2_MEM-1:0]==rd_counter[SPOWER2_MEM-1:0];

	always @(posedge clk)
  begin
  if(rst)
    begin
    wr_counter<= {(SPOWER2_MEM){1'b0}};
    rd_counter<= {(SPOWER2_MEM){1'b0}};
    end
  else
    begin
    rd_counter<= rd_en ? rd_counter+1'b1 : rd_counter;
    wr_counter<= wr_en ? wr_counter+1'b1 : wr_counter;
    end
  end

	generate
	genvar i;
	for(i=0; i<S_MEM; i=i+1)
		begin:array
		always @(posedge clk)
		if(rst) mem[i]<= {(S_WORD){1'b0}};
		else mem[i]<= wr_counter[SPOWER2_MEM-1:0]==i & wr_en ? wr_data : mem[i];
		end
	endgenerate




endmodule
module mips_fifosync #(parameter S_WORD= 8,
                       parameter SPOWER2_MEM= 4)
                      (
                      input               clk,
                      input               rst,

                      input               wr_en,
                      input[S_WORD-1:0]   wr_data,

                      input               rd_en,
                      output[S_WORD-1:0]  rd_data,

                      output              fifo_full,
                      output              fifo_empty
                      );





  localparam         S_MEM= 1<<SPOWER2_MEM;
	reg[S_WORD-1:0]    mem[S_MEM-1:0];
	reg[SPOWER2_MEM:0] wr_counter;
	reg[SPOWER2_MEM:0] rd_counter;




  assign rd_data=    mem[rd_counter[SPOWER2_MEM-1:0]];
  assign fifo_empty= wr_counter==rd_counter;
  assign fifo_full=  wr_counter[SPOWER2_MEM]!=rd_counter[SPOWER2_MEM] &
                     wr_counter[SPOWER2_MEM-1:0]==rd_counter[SPOWER2_MEM-1:0];

	always @(posedge clk)
  begin
  if(rst)
    begin
    wr_counter<= {(SPOWER2_MEM){1'b0}};
    rd_counter<= {(SPOWER2_MEM){1'b0}};
    end
  else
    begin
    rd_counter<= rd_en ? rd_counter+1'b1 : rd_counter;
    wr_counter<= wr_en ? wr_counter+1'b1 : wr_counter;
    end
  end

	generate
	genvar i;
	for(i=0; i<S_MEM; i=i+1)
		begin:array
		always @(posedge clk)
		if(rst) mem[i]<= {(S_WORD){1'b0}};
		else mem[i]<= wr_counter[SPOWER2_MEM-1:0]==i & wr_en ? wr_data : mem[i];
		end
	endgenerate




endmodule