data/full_repos/permissive/437835038/RISCV_Lite/RISCV_Lite_SYN/Simulation/TB_RISCV.v
1: b"%Error: data/full_repos/permissive/437835038/RISCV_Lite/RISCV_Lite_SYN/Simulation/TB_RISCV.v:22: Cannot find file containing module: 'clk_gen'\n   clk_gen CG(   \n   ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/437835038/RISCV_Lite/RISCV_Lite_SYN/Simulation,data/full_repos/permissive/437835038/clk_gen\n             data/full_repos/permissive/437835038/RISCV_Lite/RISCV_Lite_SYN/Simulation,data/full_repos/permissive/437835038/clk_gen.v\n             data/full_repos/permissive/437835038/RISCV_Lite/RISCV_Lite_SYN/Simulation,data/full_repos/permissive/437835038/clk_gen.sv\n             clk_gen\n             clk_gen.v\n             clk_gen.sv\n             obj_dir/clk_gen\n             obj_dir/clk_gen.v\n             obj_dir/clk_gen.sv\n%Error: data/full_repos/permissive/437835038/RISCV_Lite/RISCV_Lite_SYN/Simulation/TB_RISCV.v:28: Cannot find file containing module: 'RISCV'\n   RISCV UUT(       .Clk(Clk_i),\n   ^~~~~\n%Error: data/full_repos/permissive/437835038/RISCV_Lite/RISCV_Lite_SYN/Simulation/TB_RISCV.v:38: Cannot find file containing module: 'IRAM'\n IRAM  IRAM_I(\n ^~~~\n%Error: data/full_repos/permissive/437835038/RISCV_Lite/RISCV_Lite_SYN/Simulation/TB_RISCV.v:43: Cannot find file containing module: 'DRAM'\n     DRAM DRAM_D(\n     ^~~~\n%Error: Exiting due to 4 error(s)\n"
module TB_RISCV ();

    wire Clk_i;
   	wire Rst_i;


	wire [31:0] DRAMout_i;
	wire [31:0] Instruction_i;

    wire [63:0] PCtoIM_i;
    wire [63:0] ALUtoMEMORY_i;      
    wire [63:0] OUT2RFtoMEMORY_i;

    wire memoryenable_i;
    wire ReadNotWrite_i;
         

   clk_gen CG(   
  	               .Clk(Clk_i),
	                .Rst(Rst_i));



   RISCV UUT(       .Clk(Clk_i),
	                .Rst(Rst_i),
                  .DRAMout(DRAMout_i),
                  .Instruction(Instruction_i),
                  .PCtoIM(PCtoIM_i),
                  .ALUtoMEMORY(ALUtoMEMORY_i),
                  .OUT2RFtoMEMORY(OUT2RFtoMEMORY_i),
                  .memoryEnable(memoryenable_i),
                  .ReadNotWrite(ReadNotWrite_i));
 
	IRAM  IRAM_I(
        .Rst   (Rst_i),
         .Addr  (PCtoIM_i[31:0]),
         .Dout (Instruction_i));
     
     DRAM DRAM_D(
      .Clk(Clk_i) ,        
      .Rst(Rst_i),        
      .MemoryEnable(memoryenable_i),
      .ReadNotWrite(ReadNotWrite_i),
      .DRAMadd(ALUtoMEMORY_i[31:0]),
      .DRAMin(OUT2RFtoMEMORY_i[31:0]),
      .DRAMout(DRAMout_i));

endmodule
module TB_RISCV ();


    wire Clk_i;
   	wire Rst_i;


	wire [31:0] DRAMout_i;
	wire [31:0] Instruction_i;

    wire [63:0] PCtoIM_i;
    wire [63:0] ALUtoMEMORY_i;      
    wire [63:0] OUT2RFtoMEMORY_i;

    wire memoryenable_i;
    wire ReadNotWrite_i;
         

   clk_gen CG(   
  	               .Clk(Clk_i),
	                .Rst(Rst_i));



   RISCV UUT(       .Clk(Clk_i),
	                .Rst(Rst_i),
                  .DRAMout(DRAMout_i),
                  .Instruction(Instruction_i),
                  .PCtoIM(PCtoIM_i),
                  .ALUtoMEMORY(ALUtoMEMORY_i),
                  .OUT2RFtoMEMORY(OUT2RFtoMEMORY_i),
                  .memoryEnable(memoryenable_i),
                  .ReadNotWrite(ReadNotWrite_i));
 
	IRAM  IRAM_I(
        .Rst   (Rst_i),
         .Addr  (PCtoIM_i[31:0]),
         .Dout (Instruction_i));
     
     DRAM DRAM_D(
      .Clk(Clk_i) ,        
      .Rst(Rst_i),        
      .MemoryEnable(memoryenable_i),
      .ReadNotWrite(ReadNotWrite_i),
      .DRAMadd(ALUtoMEMORY_i[31:0]),
      .DRAMin(OUT2RFtoMEMORY_i[31:0]),
      .DRAMout(DRAMout_i));

endmodule