data/full_repos/permissive/405799749/arithmetic_netlists/muliplier/16-bit unsigned multiplier using wallace tree/multi_8bit_unsigned.v
1: b'%Error: Cannot find file containing module: unsigned\n        ... Looked in:\n             data/full_repos/permissive/405799749/arithmetic_netlists/muliplier/16-bit/unsigned\n             data/full_repos/permissive/405799749/arithmetic_netlists/muliplier/16-bit/unsigned.v\n             data/full_repos/permissive/405799749/arithmetic_netlists/muliplier/16-bit/unsigned.sv\n             unsigned\n             unsigned.v\n             unsigned.sv\n             obj_dir/unsigned\n             obj_dir/unsigned.v\n             obj_dir/unsigned.sv\n%Error: Cannot find file containing module: multiplier\n%Error: Cannot find file containing module: using\n%Error: Cannot find file containing module: wallace\n%Error: Cannot find file containing module: tree,data/full_repos/permissive/405799749\n%Error: Cannot find file containing module: data/full_repos/permissive/405799749/arithmetic_netlists/muliplier/16-bit\n%Error: Cannot find file containing module: tree/multi_8bit_unsigned.v\n%Error: Exiting due to 7 error(s)\n'
module accumulator(res,md,cla_sub,load,clk,rst);
	output [15:0] res;
	input [10:0] md;
	input clk,rst,load,cla_sub;
	
	wire [20:0] par_res, shift_par_res, reg_res;
	wire [11:0] cla_res;
	wire rst_new;
	cla_ripple_12bit cr12b1(.sum(cla_res),.c12(x),.a({1'b0,reg_res[20:10]}),.b({1'd0,md}),.c0(cla_sub));
	assign par_res[20:10] =  cla_res[10:0];
	assign par_res[9:0] = reg_res[9:0];
	assign shift_par_res = {par_res[20],par_res[20],par_res[20:2]};
	assign rst_new = rst | load;
	dff d1(.q(reg_res),.d(shift_par_res),.clk(clk),.rst(rst_new));
	assign res = reg_res[15:0];
endmodule
module accumulator(res,md,cla_sub,load,clk,rst);

	output [15:0] res;
	input [10:0] md;
	input clk,rst,load,cla_sub;
	
	wire [20:0] par_res, shift_par_res, reg_res;
	wire [11:0] cla_res;
	wire rst_new;
	cla_ripple_12bit cr12b1(.sum(cla_res),.c12(x),.a({1'b0,reg_res[20:10]}),.b({1'd0,md}),.c0(cla_sub));
	assign par_res[20:10] =  cla_res[10:0];
	assign par_res[9:0] = reg_res[9:0];
	assign shift_par_res = {par_res[20],par_res[20],par_res[20:2]};
	assign rst_new = rst | load;
	dff d1(.q(reg_res),.d(shift_par_res),.clk(clk),.rst(rst_new));
	assign res = reg_res[15:0];
endmodule