data/full_repos/permissive/48004801/ServoCommander.srcs/sources_1/imports/new/segment.v
1: b'%Warning-WIDTH: data/full_repos/permissive/48004801/ServoCommander.srcs/sources_1/imports/new/segment.v:32: Operator CASE expects 11 bits on the Case expression, but Case expression\'s VARREF \'in\' generates 10 bits.\n                                                                                                          : ... In instance Segment\n casex(in)\n ^~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Segment(
    input wire [9:0] in,
    output reg [10:0] out,
    output reg valid
);

always @(in) begin
	valid = 1;
	casex(in)
		11'b1xxxxxxxxx: out = 2000;
		11'b01xxxxxxxx: out = 1800;
		11'b001xxxxxxx: out = 1600;
		11'b0001xxxxxx: out = 1400;
		11'b00001xxxxx: out = 1200;
		11'b000001xxxx: out = 1000;
		11'b0000001xxx: out = 800;
		11'b00000001xx: out = 600;
		11'b000000001x: out = 400;
		11'b0000000001: out = 200;
		default: begin
			valid = 0;
			out = 11'b0;
		end
	endcase
end
endmodule
module Segment(
    input wire [9:0] in,
    output reg [10:0] out,
    output reg valid
);


always @(in) begin
	valid = 1;
	casex(in)
		11'b1xxxxxxxxx: out = 2000;
		11'b01xxxxxxxx: out = 1800;
		11'b001xxxxxxx: out = 1600;
		11'b0001xxxxxx: out = 1400;
		11'b00001xxxxx: out = 1200;
		11'b000001xxxx: out = 1000;
		11'b0000001xxx: out = 800;
		11'b00000001xx: out = 600;
		11'b000000001x: out = 400;
		11'b0000000001: out = 200;
		default: begin
			valid = 0;
			out = 11'b0;
		end
	endcase
end
endmodule