data/full_repos/permissive/481623724/hw/cores/common/bsv.vivado/UltraRAM_SDP.v
data/verilator_xmls/a98687f8-d987-421b-9a3d-3f90b6c29fa9.xml
module UltraRAM_SDP
  #(
    parameter AWIDTH = 12,
    parameter DWIDTH = 72,
    parameter NBPIPE = 3
    ) (
       input                   clk,
       input                   rstb,
       input                   wea,
       input                   regceb,
       input                   mem_en,
       input [DWIDTH-1:0]      dina,
       input [AWIDTH-1:0]      addra,
       input [AWIDTH-1:0]      addrb,
       output reg [DWIDTH-1:0] doutb
       );

  (* ram_style = "ultra" *)
  reg [DWIDTH-1:0]             mem[(1<<AWIDTH)-1:0];
  reg [DWIDTH-1:0]             memreg;
  reg [DWIDTH-1:0]             mem_pipe_reg[NBPIPE-1:0];
  reg              [NBPIPE:0]  mem_en_pipe_reg;

  integer                      i;


always @ (posedge clk) begin
  if(mem_en)
      memreg <= mem[addrb];

  if(wea)
    mem[addra] <= dina;
end




always @ (posedge clk) begin
  mem_en_pipe_reg[0] <= mem_en;
  for (i=0; i<NBPIPE; i=i+1)
    mem_en_pipe_reg[i+1] <= mem_en_pipe_reg[i];
end


always @ (posedge clk) begin
  if (mem_en_pipe_reg[0])
    mem_pipe_reg[0] <= memreg;
end

always @ (posedge clk) begin
  for (i = 0; i < NBPIPE-1; i = i+1)
    if (mem_en_pipe_reg[i+1]) begin
      mem_pipe_reg[i+1] <= mem_pipe_reg[i];
    end
end



always @ (posedge clk) begin
  if (rstb)
    doutb <= 0;
  else if (mem_en_pipe_reg[NBPIPE] && regceb) begin

    doutb <= mem_pipe_reg[NBPIPE-1];
  end

  else if (mem_en_pipe_reg[NBPIPE]) begin
    $display("%t, Missed %h", $time, mem_pipe_reg[NBPIPE-1]);
  end

end

endmodule
module UltraRAM_SDP
  #(
    parameter AWIDTH = 12,
    parameter DWIDTH = 72,
    parameter NBPIPE = 3
    ) (
       input                   clk,
       input                   rstb,
       input                   wea,
       input                   regceb,
       input                   mem_en,
       input [DWIDTH-1:0]      dina,
       input [AWIDTH-1:0]      addra,
       input [AWIDTH-1:0]      addrb,
       output reg [DWIDTH-1:0] doutb
       );


  (* ram_style = "ultra" *)
  reg [DWIDTH-1:0]             mem[(1<<AWIDTH)-1:0];
  reg [DWIDTH-1:0]             memreg;
  reg [DWIDTH-1:0]             mem_pipe_reg[NBPIPE-1:0];
  reg              [NBPIPE:0]  mem_en_pipe_reg;

  integer                      i;


always @ (posedge clk) begin
  if(mem_en)
      memreg <= mem[addrb];

  if(wea)
    mem[addra] <= dina;
end




always @ (posedge clk) begin
  mem_en_pipe_reg[0] <= mem_en;
  for (i=0; i<NBPIPE; i=i+1)
    mem_en_pipe_reg[i+1] <= mem_en_pipe_reg[i];
end


always @ (posedge clk) begin
  if (mem_en_pipe_reg[0])
    mem_pipe_reg[0] <= memreg;
end

always @ (posedge clk) begin
  for (i = 0; i < NBPIPE-1; i = i+1)
    if (mem_en_pipe_reg[i+1]) begin
      mem_pipe_reg[i+1] <= mem_pipe_reg[i];
    end
end



always @ (posedge clk) begin
  if (rstb)
    doutb <= 0;
  else if (mem_en_pipe_reg[NBPIPE] && regceb) begin

    doutb <= mem_pipe_reg[NBPIPE-1];
  end

  else if (mem_en_pipe_reg[NBPIPE]) begin
    $display("%t, Missed %h", $time, mem_pipe_reg[NBPIPE-1]);
  end

end

endmodule