data/full_repos/permissive/46804359/pc_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/46804359/pc_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk=~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/46804359/pc_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #15\n    ^\n%Error: data/full_repos/permissive/46804359/pc_tb.v:10: Cannot find file containing module: \'pc\'\npc DUT(in, clk, rst, en, out);\n^~\n        ... Looked in:\n             data/full_repos/permissive/46804359,data/full_repos/permissive/46804359/pc\n             data/full_repos/permissive/46804359,data/full_repos/permissive/46804359/pc.v\n             data/full_repos/permissive/46804359,data/full_repos/permissive/46804359/pc.sv\n             pc\n             pc.v\n             pc.sv\n             obj_dir/pc\n             obj_dir/pc.v\n             obj_dir/pc.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pc_tb;

reg clk;
reg rst;
reg en;
reg [31:0] in;

wire [31:0] out;

pc DUT(in, clk, rst, en, out);


initial begin
    clk=0;
    rst=0;
    en=0;
end


always #5 clk=~clk;


initial begin
    rst=1;
    en=1;

    #15
    rst=0;
end

endmodule
module pc_tb;


reg clk;
reg rst;
reg en;
reg [31:0] in;

wire [31:0] out;

pc DUT(in, clk, rst, en, out);


initial begin
    clk=0;
    rst=0;
    en=0;
end


always #5 clk=~clk;


initial begin
    rst=1;
    en=1;

    #15
    rst=0;
end

endmodule