data/full_repos/permissive/437204475/common/dbg_mems/dbg_dmem.v
1: b'%Error: data/full_repos/permissive/437204475/common/dbg_mems/dbg_dmem.v:5: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/437204475/common/dbg_mems,data/full_repos/permissive/437204475/defines.v\n             data/full_repos/permissive/437204475/common/dbg_mems,data/full_repos/permissive/437204475/defines.v.v\n             data/full_repos/permissive/437204475/common/dbg_mems,data/full_repos/permissive/437204475/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/437204475/common/dbg_mems/dbg_dmem.v:8: Define or directive not defined: \'`WORD_WIDTH\'\n    parameter W = `WORD_WIDTH,\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/common/dbg_mems/dbg_dmem.v:8: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    parameter W = `WORD_WIDTH,\n                             ^\n%Error: data/full_repos/permissive/437204475/common/dbg_mems/dbg_dmem.v:10: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter DATA_SEGMENT = `WORD_WIDTH\'h10010000  \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/437204475/common/dbg_mems/dbg_dmem.v:10: Define or directive not defined: \'`WORD_WIDTH\'\n    parameter DATA_SEGMENT = `WORD_WIDTH\'h10010000  \n                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/common/dbg_mems/dbg_dmem.v:11: syntax error, unexpected \')\', expecting \';\'\n) (\n^\n%Error: data/full_repos/permissive/437204475/common/dbg_mems/dbg_dmem.v:14: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire read_en,\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/common/dbg_mems/dbg_dmem.v:15: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[W-1:0] read_addr,\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/common/dbg_mems/dbg_dmem.v:16: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg[W-1:0] read_data,\n    ^~~~~~\n%Error: data/full_repos/permissive/437204475/common/dbg_mems/dbg_dmem.v:18: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input wire write_en,\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/common/dbg_mems/dbg_dmem.v:19: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[W-1:0] write_addr,\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/common/dbg_mems/dbg_dmem.v:20: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[W-1:0] write_data\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/common/dbg_mems/dbg_dmem.v:21: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/437204475/common/dbg_mems/dbg_dmem.v:31: syntax error, unexpected initial\n    initial begin\n    ^~~~~~~\n%Error: data/full_repos/permissive/437204475/common/dbg_mems/dbg_dmem.v:32: Define or directive not defined: \'`DMEM_SIM_FILE\'\n        $readmemh(`DMEM_SIM_FILE, mem);\n                  ^~~~~~~~~~~~~~\n%Error: Exiting due to 15 error(s)\n'
module dbg_dmem #(
    parameter W = `WORD_WIDTH,
    parameter DMEM_SIZE = 4096,
    parameter DATA_SEGMENT = `WORD_WIDTH'h10010000
) (
    input wire clk, rst,

    input wire read_en,
    input wire[W-1:0] read_addr,
    output reg[W-1:0] read_data,

    input wire write_en,
    input wire[W-1:0] write_addr,
    input wire[W-1:0] write_data
);

    reg[W-1:0] mem[DMEM_SIZE-1:0];


    wire[W-1:0] read_addr_d = read_addr - DATA_SEGMENT;
    wire[W-1:0] write_addr_d = write_addr - DATA_SEGMENT;


    integer mem_dump_file, i;
    initial begin
        $readmemh(`DMEM_SIM_FILE, mem);

    end


    always @(posedge clk) begin
        if (write_en) begin
            mem[write_addr_d[18:2]] <= write_data;
        end
    end
    

    always @(*) begin
        if (read_en) begin
            read_data <= mem[read_addr_d[18:2]];
        end
    end
endmodule
module dbg_dmem #(
    parameter W = `WORD_WIDTH,
    parameter DMEM_SIZE = 4096,
    parameter DATA_SEGMENT = `WORD_WIDTH'h10010000
) (
    input wire clk, rst,

    input wire read_en,
    input wire[W-1:0] read_addr,
    output reg[W-1:0] read_data,

    input wire write_en,
    input wire[W-1:0] write_addr,
    input wire[W-1:0] write_data
);


    reg[W-1:0] mem[DMEM_SIZE-1:0];


    wire[W-1:0] read_addr_d = read_addr - DATA_SEGMENT;
    wire[W-1:0] write_addr_d = write_addr - DATA_SEGMENT;


    integer mem_dump_file, i;
    initial begin
        $readmemh(`DMEM_SIM_FILE, mem);

    end


    always @(posedge clk) begin
        if (write_en) begin
            mem[write_addr_d[18:2]] <= write_data;
        end
    end
    

    always @(*) begin
        if (read_en) begin
            read_data <= mem[read_addr_d[18:2]];
        end
    end
endmodule