data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa/i2424vedic.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa/i2424vedic.v:43: Cannot find file containing module: 'i1212vedic'\ni1212vedic i1212vedic1i\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa,data/full_repos/permissive/530013823/i1212vedic\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa,data/full_repos/permissive/530013823/i1212vedic.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa,data/full_repos/permissive/530013823/i1212vedic.sv\n             i1212vedic\n             i1212vedic.v\n             i1212vedic.sv\n             obj_dir/i1212vedic\n             obj_dir/i1212vedic.v\n             obj_dir/i1212vedic.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa/i2424vedic.v:52: Cannot find file containing module: 'i1212vedic'\ni1212vedic i1212vedic2i\n^~~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa/i2424vedic.v:61: Cannot find file containing module: 'i1212vedic'\ni1212vedic i1212vedic3i\n^~~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa/i2424vedic.v:70: Cannot find file containing module: 'i1212vedic'\ni1212vedic i1212vedic4i\n^~~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa/i2424vedic.v:80: Cannot find file containing module: 'cla'\ncla #(24) i2424cla1i\n^~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa/i2424vedic.v:91: Cannot find file containing module: 'cla'\ncla #(24) i2424cla2i\n^~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa/i2424vedic.v:105: Cannot find file containing module: 'cla'\ncla #(24) i2424cla3i\n^~~\n%Error: Exiting due to 7 error(s)\n"
module i2424vedic
    (
     a,
     b,
     rslt
     );




parameter WIDTH = 24;
parameter RSWID = 48;




input [WIDTH-1:0] a;
input [WIDTH-1:0] b;

output [RSWID-1:0] rslt;







wire [WIDTH-1:0]   w1212rslt1;

i1212vedic i1212vedic1i
    (
     .a(a[11:0]),
     .b(b[11:0]),
     .rslt(w1212rslt1)
     );

wire [WIDTH-1:0]   w1212rslt2;

i1212vedic i1212vedic2i
    (
     .a(a[11:0]),
     .b(b[23:12]),
     .rslt(w1212rslt2)
     );

wire [WIDTH-1:0]   w1212rslt3;

i1212vedic i1212vedic3i
    (
     .a(a[23:12]),
     .b(b[11:0]),
     .rslt(w1212rslt3)
     );

wire [WIDTH-1:0]   w1212rslt4;

i1212vedic i1212vedic4i
    (
     .a(a[23:12]),
     .b(b[23:12]),
     .rslt(w1212rslt4)
     );

wire [WIDTH-1:0]   cla1rslt;
wire               cla1carry;

cla #(24) i2424cla1i
    (
     .a(w1212rslt2),
     .b(w1212rslt3),
     .sum(cla1rslt),
     .c(cla1carry)
     );

wire [WIDTH-1:0]   cla2rslt;
wire               cla2carry;

cla #(24) i2424cla2i
    (
     .a({12'b0,w1212rslt1[23:12]}),
     .b(cla1rslt),
     .sum(cla2rslt),
     .c(cla2carry)
     );

wire [WIDTH-1:0]   cla3rslt;
wire               cla3carry;
wire               cla3cin;

assign             cla3cin = cla2carry | cla1carry;

cla #(24) i2424cla3i
    (
     .a(w1212rslt4),
     .b({11'b0,cla3cin,cla2rslt[23:12]}),
     .sum(cla3rslt),
     .c(cla3carry)
     );

assign             rslt = {cla3rslt,cla2rslt[11:0],w1212rslt1[11:0]};

endmodule
module i2424vedic
    (
     a,
     b,
     rslt
     );





parameter WIDTH = 24;
parameter RSWID = 48;




input [WIDTH-1:0] a;
input [WIDTH-1:0] b;

output [RSWID-1:0] rslt;







wire [WIDTH-1:0]   w1212rslt1;

i1212vedic i1212vedic1i
    (
     .a(a[11:0]),
     .b(b[11:0]),
     .rslt(w1212rslt1)
     );

wire [WIDTH-1:0]   w1212rslt2;

i1212vedic i1212vedic2i
    (
     .a(a[11:0]),
     .b(b[23:12]),
     .rslt(w1212rslt2)
     );

wire [WIDTH-1:0]   w1212rslt3;

i1212vedic i1212vedic3i
    (
     .a(a[23:12]),
     .b(b[11:0]),
     .rslt(w1212rslt3)
     );

wire [WIDTH-1:0]   w1212rslt4;

i1212vedic i1212vedic4i
    (
     .a(a[23:12]),
     .b(b[23:12]),
     .rslt(w1212rslt4)
     );

wire [WIDTH-1:0]   cla1rslt;
wire               cla1carry;

cla #(24) i2424cla1i
    (
     .a(w1212rslt2),
     .b(w1212rslt3),
     .sum(cla1rslt),
     .c(cla1carry)
     );

wire [WIDTH-1:0]   cla2rslt;
wire               cla2carry;

cla #(24) i2424cla2i
    (
     .a({12'b0,w1212rslt1[23:12]}),
     .b(cla1rslt),
     .sum(cla2rslt),
     .c(cla2carry)
     );

wire [WIDTH-1:0]   cla3rslt;
wire               cla3carry;
wire               cla3cin;

assign             cla3cin = cla2carry | cla1carry;

cla #(24) i2424cla3i
    (
     .a(w1212rslt4),
     .b({11'b0,cla3cin,cla2rslt[23:12]}),
     .sum(cla3rslt),
     .c(cla3carry)
     );

assign             rslt = {cla3rslt,cla2rslt[11:0],w1212rslt1[11:0]};

endmodule