data/full_repos/permissive/523492216/verilog/subword.v
1: b"%Error: data/full_repos/permissive/523492216/verilog/subword.v:10: Cannot find file containing module: 'sbox'\n      sbox sbox_inst (.byte_in(word_in[i*8+:8]), .byte_out(word_out[i*8+:8]), .clk(clk));\n      ^~~~\n        ... Looked in:\n             data/full_repos/permissive/523492216/verilog,data/full_repos/permissive/523492216/sbox\n             data/full_repos/permissive/523492216/verilog,data/full_repos/permissive/523492216/sbox.v\n             data/full_repos/permissive/523492216/verilog,data/full_repos/permissive/523492216/sbox.sv\n             sbox\n             sbox.v\n             sbox.sv\n             obj_dir/sbox\n             obj_dir/sbox.v\n             obj_dir/sbox.sv\n%Error: Exiting due to 1 error(s)\n"
module subword(word_in, word_out, clk);

  input [31:0] word_in;
  output [31:0] word_out;
  input clk;

  genvar i;
  generate
    for (i = 0; i < 4; i = i + 1) begin : subword_sboxes
      sbox sbox_inst (.byte_in(word_in[i*8+:8]), .byte_out(word_out[i*8+:8]), .clk(clk));
    end
  endgenerate

endmodule
module subword(word_in, word_out, clk);


  input [31:0] word_in;
  output [31:0] word_out;
  input clk;

  genvar i;
  generate
    for (i = 0; i < 4; i = i + 1) begin : subword_sboxes
      sbox sbox_inst (.byte_in(word_in[i*8+:8]), .byte_out(word_out[i*8+:8]), .clk(clk));
    end
  endgenerate

endmodule