data/full_repos/permissive/479923049/cpu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/479923049/cpu.v:163: Operator CASE expects 11 bits on the Case expression, but Case expression\'s REPLICATE generates 10 bits.\n                                                              : ... In instance cpu.FSM\n   casex({state, opcode, op})\n   ^~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/479923049/cpu.v:163: Operator CASE expects 11 bits on the Case Item, but Case Item\'s REPLICATE generates 10 bits.\n                                                              : ... In instance cpu.FSM\n   casex({state, opcode, op})\n   ^~~~~\n%Error: data/full_repos/permissive/479923049/cpu.v:77: Cannot find file containing module: \'vDFFE\'\n    vDFFE #(16) instruction_register (clk, load_ir, read_data, ir_out);\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/479923049,data/full_repos/permissive/479923049/vDFFE\n             data/full_repos/permissive/479923049,data/full_repos/permissive/479923049/vDFFE.v\n             data/full_repos/permissive/479923049,data/full_repos/permissive/479923049/vDFFE.sv\n             vDFFE\n             vDFFE.v\n             vDFFE.sv\n             obj_dir/vDFFE\n             obj_dir/vDFFE.v\n             obj_dir/vDFFE.sv\n%Error: data/full_repos/permissive/479923049/cpu.v:91: Cannot find file containing module: \'datapath\'\n    datapath DP(\n    ^~~~~~~~\n%Error: data/full_repos/permissive/479923049/cpu.v:99: Cannot find file containing module: \'vDFFE\'\n    vDFFE #(9) program_counter (clk, load_pc, next_pc, PC);\n    ^~~~~\n%Error: data/full_repos/permissive/479923049/cpu.v:100: Cannot find file containing module: \'vDFFE\'\n    vDFFE #(9) data_address (clk, load_addr, datapath_out[8:0], data_addr_out);\n    ^~~~~\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module cpu(clk,reset,N,V,Z,mem_cmd, mem_addr, write_data, read_data);

    input clk, reset;
    input [15:0] read_data;
    output N, V, Z;
    output [1:0] mem_cmd; 
    output [8:0] mem_addr;
    output [15:0] write_data;


    wire [1:0] op, ALUop, shift;
    wire [2:0] nsel;
    wire [15:0] sximm5, sximm8;
    wire [2:0] opcode, readnum, writenum;
    wire [15:0] ir_out;
    wire load_ir;

    vDFFE #(16) instruction_register (clk, load_ir, read_data, ir_out);

    wire [2:0] status_out;
    wire [1:0] vsel, dp_shift; 
    wire write, loada, loadb, asel, bsel, loadc, loads;
    wire [15:0]datapath_out;
    wire [8:0] PC;
    wire load_pc, reset_pc, load_addr, addr_sel;

    InstructionDecoder ID(ir_out, opcode, op, nsel, ALUop, sximm5, sximm8, shift, readnum, writenum);

    StateMachine FSM(clk, reset, opcode, op, nsel, vsel, write, loada, loadb, dp_shift, 
                    asel, bsel, loadc, loads, reset_pc, load_addr, load_pc, load_ir, addr_sel, mem_cmd);
                
    datapath DP(
                .clk(clk), .readnum(readnum), .vsel(vsel), .loada(loada), .loadb(loadb), .shift(shift), .asel(asel),
                .bsel(bsel), .ALUop(ALUop), .loadc(loadc), .loads(loads), .writenum(writenum), .write(write), .mdata(read_data), .sximm8(sximm8), 
                .sximm5(sximm5), .PC_dp(PC[7:0]), .status_out(status_out), .datapath_out(datapath_out)
                );

    wire [8:0] data_addr_out, next_pc;

    vDFFE #(9) program_counter (clk, load_pc, next_pc, PC);
    vDFFE #(9) data_address (clk, load_addr, datapath_out[8:0], data_addr_out);

    assign mem_addr = addr_sel ? PC: data_addr_out;
    assign next_pc = reset_pc ? 9'd0 : PC + 1'b1;
    
    assign N = status_out[2];
    assign V = status_out[1];
    assign Z = status_out[0];



    assign write_data = datapath_out;

endmodule
module cpu(clk,reset,N,V,Z,mem_cmd, mem_addr, write_data, read_data);


    input clk, reset;
    input [15:0] read_data;
    output N, V, Z;
    output [1:0] mem_cmd; 
    output [8:0] mem_addr;
    output [15:0] write_data;


    wire [1:0] op, ALUop, shift;
    wire [2:0] nsel;
    wire [15:0] sximm5, sximm8;
    wire [2:0] opcode, readnum, writenum;
    wire [15:0] ir_out;
    wire load_ir;

    vDFFE #(16) instruction_register (clk, load_ir, read_data, ir_out);

    wire [2:0] status_out;
    wire [1:0] vsel, dp_shift; 
    wire write, loada, loadb, asel, bsel, loadc, loads;
    wire [15:0]datapath_out;
    wire [8:0] PC;
    wire load_pc, reset_pc, load_addr, addr_sel;

    InstructionDecoder ID(ir_out, opcode, op, nsel, ALUop, sximm5, sximm8, shift, readnum, writenum);

    StateMachine FSM(clk, reset, opcode, op, nsel, vsel, write, loada, loadb, dp_shift, 
                    asel, bsel, loadc, loads, reset_pc, load_addr, load_pc, load_ir, addr_sel, mem_cmd);
                
    datapath DP(
                .clk(clk), .readnum(readnum), .vsel(vsel), .loada(loada), .loadb(loadb), .shift(shift), .asel(asel),
                .bsel(bsel), .ALUop(ALUop), .loadc(loadc), .loads(loads), .writenum(writenum), .write(write), .mdata(read_data), .sximm8(sximm8), 
                .sximm5(sximm5), .PC_dp(PC[7:0]), .status_out(status_out), .datapath_out(datapath_out)
                );

    wire [8:0] data_addr_out, next_pc;

    vDFFE #(9) program_counter (clk, load_pc, next_pc, PC);
    vDFFE #(9) data_address (clk, load_addr, datapath_out[8:0], data_addr_out);

    assign mem_addr = addr_sel ? PC: data_addr_out;
    assign next_pc = reset_pc ? 9'd0 : PC + 1'b1;
    
    assign N = status_out[2];
    assign V = status_out[1];
    assign Z = status_out[0];



    assign write_data = datapath_out;

endmodule