data/full_repos/permissive/503578084/pipeline/alu_mux.v
1: b'%Error: data/full_repos/permissive/503578084/pipeline/alu_mux.v:21: Cannot find include file: param.v\n`include "param.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/503578084/pipeline,data/full_repos/permissive/503578084/param.v\n             data/full_repos/permissive/503578084/pipeline,data/full_repos/permissive/503578084/param.v.v\n             data/full_repos/permissive/503578084/pipeline,data/full_repos/permissive/503578084/param.v.sv\n             param.v\n             param.v.v\n             param.v.sv\n             obj_dir/param.v\n             obj_dir/param.v.v\n             obj_dir/param.v.sv\n%Error: data/full_repos/permissive/503578084/pipeline/alu_mux.v:34: Define or directive not defined: \'`ADD\'\n        `ADD:mux_o=mux_i_0;\n        ^~~~\n%Error: data/full_repos/permissive/503578084/pipeline/alu_mux.v:34: syntax error, unexpected \':\', expecting endcase\n        `ADD:mux_o=mux_i_0;\n            ^\n%Error: data/full_repos/permissive/503578084/pipeline/alu_mux.v:35: Define or directive not defined: \'`SUB\'\n        `SUB:mux_o=mux_i_0;\n        ^~~~\n%Error: data/full_repos/permissive/503578084/pipeline/alu_mux.v:36: Define or directive not defined: \'`AND\'\n        `AND:mux_o=mux_i_1;\n        ^~~~\n%Error: data/full_repos/permissive/503578084/pipeline/alu_mux.v:37: Define or directive not defined: \'`OR\'\n        `OR:mux_o=mux_i_1;\n        ^~~\n%Error: data/full_repos/permissive/503578084/pipeline/alu_mux.v:38: Define or directive not defined: \'`XOR\'\n        `XOR:mux_o=mux_i_1;\n        ^~~~\n%Error: data/full_repos/permissive/503578084/pipeline/alu_mux.v:39: Define or directive not defined: \'`SLL\'\n        `SLL:mux_o=mux_i_2;\n        ^~~~\n%Error: data/full_repos/permissive/503578084/pipeline/alu_mux.v:40: Define or directive not defined: \'`SRL\'\n        `SRL:mux_o=mux_i_2;\n        ^~~~\n%Error: data/full_repos/permissive/503578084/pipeline/alu_mux.v:41: Define or directive not defined: \'`SRA\'\n        `SRA:mux_o=mux_i_2;\n        ^~~~\n%Error: data/full_repos/permissive/503578084/pipeline/alu_mux.v:42: Define or directive not defined: \'`SEL_B\'\n        `SEL_B:mux_o=mux_i_3;\n        ^~~~~~\n%Error: Cannot continue\n'
module alu_mux(
    input   [3:0]   alu_op,
    input   [31:0]  mux_i_0,
    input   [31:0]  mux_i_1,
    input   [31:0]  mux_i_2,
    input   [31:0]  mux_i_3,
    output  reg [31:0]  mux_o
    );
    
always @ (*) begin
    case(alu_op)
        `ADD:mux_o=mux_i_0;
        `SUB:mux_o=mux_i_0;
        `AND:mux_o=mux_i_1;
        `OR:mux_o=mux_i_1;
        `XOR:mux_o=mux_i_1;
        `SLL:mux_o=mux_i_2;
        `SRL:mux_o=mux_i_2;
        `SRA:mux_o=mux_i_2;
        `SEL_B:mux_o=mux_i_3;
        default:mux_o=32'b0;
    endcase
end

endmodule
module alu_mux(
    input   [3:0]   alu_op,
    input   [31:0]  mux_i_0,
    input   [31:0]  mux_i_1,
    input   [31:0]  mux_i_2,
    input   [31:0]  mux_i_3,
    output  reg [31:0]  mux_o
    );

    
always @ (*) begin
    case(alu_op)
        `ADD:mux_o=mux_i_0;
        `SUB:mux_o=mux_i_0;
        `AND:mux_o=mux_i_1;
        `OR:mux_o=mux_i_1;
        `XOR:mux_o=mux_i_1;
        `SLL:mux_o=mux_i_2;
        `SRL:mux_o=mux_i_2;
        `SRA:mux_o=mux_i_2;
        `SEL_B:mux_o=mux_i_3;
        default:mux_o=32'b0;
    endcase
end

endmodule