data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new/Top.v
1: b"%Error: data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new/Top.v:83: Cannot find file containing module: 'PC'\n    PC ProgramCounter(\n    ^~\n        ... Looked in:\n             data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new,data/full_repos/permissive/482974936/PC\n             data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new,data/full_repos/permissive/482974936/PC.v\n             data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new,data/full_repos/permissive/482974936/PC.sv\n             PC\n             PC.v\n             PC.sv\n             obj_dir/PC\n             obj_dir/PC.v\n             obj_dir/PC.sv\n%Error: data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new/Top.v:88: Cannot find file containing module: 'AdrMux'\n    AdrMux AdrM(\n    ^~~~~~\n%Error: data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new/Top.v:93: Cannot find file containing module: 'MEM'\n    MEM Memory(\n    ^~~\n%Error: data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new/Top.v:99: Cannot find file containing module: 'IR'\n    IR InstructionRegister(\n    ^~\n%Error: data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new/Top.v:104: Cannot find file containing module: 'DR'\n    DR DataRegister(\n    ^~\n%Error: data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new/Top.v:108: Cannot find file containing module: 'RFDSelMux'\n    RFDSelMux RFDSelM(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new/Top.v:113: Cannot find file containing module: 'MtoRFSelMux'\n    MtoRFSelMux MtoRFSelM(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new/Top.v:118: Cannot find file containing module: 'RF'\n    RF RegisterFile(\n    ^~\n%Error: data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new/Top.v:127: Cannot find file containing module: 'ABR'\n    ABR ABRegister(\n    ^~~\n%Error: data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new/Top.v:133: Cannot find file containing module: 'ALUIn1Mux'\n    ALUIn1Mux ALUIn1M(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new/Top.v:138: Cannot find file containing module: 'SE'\n    SE SignExtender(\n    ^~\n%Error: data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new/Top.v:141: Cannot find file containing module: 'ALUIn2Mux'\n    ALUIn2Mux ALUIn2M(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new/Top.v:147: Cannot find file containing module: 'ALU'\n    ALU ArithmeticLogicUnit(\n    ^~~\n%Error: data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new/Top.v:154: Cannot find file containing module: 'AND'\n    AND ANDGate(\n    ^~~\n%Error: data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new/Top.v:158: Cannot find file containing module: 'OR'\n    OR ORGate(\n    ^~\n%Error: data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new/Top.v:162: Cannot find file containing module: 'ALUOutR'\n    ALUOutR ArithmeticLogicUnitOutRegister(\n    ^~~~~~~\n%Error: data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new/Top.v:166: Cannot find file containing module: 'PCSelMux'\n    PCSelMux PCSelM(\n    ^~~~~~~~\n%Error: data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new/Top.v:173: Cannot find file containing module: 'CU'\n    CU ControlUnit(\n    ^~\n%Error: data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new/Top.v:188: Cannot find file containing module: 'ALUDecoder'\n    ALUDecoder ALUD(\n    ^~~~~~~~~~\n%Error: Exiting due to 19 error(s)\n"
module Top(
    input clk
    );
    

    wire [31:0] PCOut;
    

    wire [31:0] Adr;
    







    wire [31:0] MRD;
    

    wire [31:0] IROut;
    

    wire [31:0] DROut;
    

    wire [4:0] RFDSelOut;
    

    wire [31:0] MtoRFSelOut;
    

    wire [31:0] RFRD1;
    wire [31:0] RFRD2;
    

    wire [31:0] AOut;
    wire [31:0] BOut;
    

    wire [31:0] SImm;


    wire [31:0] ALUIn1MuxOut;
    

    wire [31:0] ALUIn2MuxOut;
    

    wire [31:0] ALUOut;
    wire Zero;
    

    wire ANDOut;
    wire OROut;
    

    wire [31:0] ALUOutROut;
    

    wire [31:0] PCSelOut;


    wire MtoRFSel;
    wire RFDSel;
    wire IDSel;
    wire PCSel;
    wire ALUIn1Sel;
    wire [1:0] ALUIn2Sel;
    wire IRWE;
    wire MWE;
    wire PCWE;
    wire Branch;
    wire RFWE;
    wire [1:0] ALUOp;
    

    wire [2:0] ALUSel;
    

    PC ProgramCounter(
        .clk(clk),
        .PCWE(OROut),
        .PCIn(PCSelOut),
        .PCOut(PCOut));
    AdrMux AdrM(
        .Sel(IDSel),
        .In0(PCOut),
        .In1(ALUOutROut),
        .MuxOut(Adr));
    MEM Memory(
        .clk(clk),
        .MWE(MWE),
        .MRA(Adr),
        .MWD(BOut),
        .MRD(MRD));
    IR InstructionRegister(
        .clk(clk),
        .IRWE(IRWE),
        .IRIn(MRD),
        .IROut(IROut));
    DR DataRegister(
        .clk(clk),
        .DRIn(MRD),
        .DROut(DROut));    
    RFDSelMux RFDSelM(
        .Sel(RFDSel),
        .In0(IROut[20:16]),
        .In1(IROut[15:11]),
        .MuxOut(RFDSelOut));
    MtoRFSelMux MtoRFSelM(
        .Sel(MtoRFSel),
        .In0(ALUOutROut),
        .In1(DROut),
        .MuxOut(MtoRFSelOut));
    RF RegisterFile(
        .clk(clk),
        .RFWE(RFWE),
        .RFRA1(IROut[25:21]),
        .RFRA2(IROut[20:16]),
        .RFWA(RFDSelOut),
        .RFWD(MtoRFSelOut),
        .RFRD1(RFRD1),
        .RFRD2(RFRD2));
    ABR ABRegister(
        .clk(clk),
        .AIn(RFRD1),
        .BIn(RFRD2),
        .AOut(AOut),
        .BOut(BOut));
    ALUIn1Mux ALUIn1M(
        .ALUIn1Sel(ALUIn1Sel),
        .ALUIn1In0(PCOut),
        .ALUIn1In1(AOut),
        .ALUIn1MuxOut(ALUIn1MuxOut));
    SE SignExtender(
        .Imm(IROut[15:0]),
        .SImm(SImm));
    ALUIn2Mux ALUIn2M(
        .ALUIn2Sel(ALUIn2Sel),
        .In00(BOut),
        .In01(32'b1),
        .In10(SImm),
        .ALUIn2MuxOut(ALUIn2MuxOut));
    ALU ArithmeticLogicUnit(
        .ALUSel(ALUSel),
        .ALUIn1(ALUIn1MuxOut),
        .ALUIn2(ALUIn2MuxOut),
        .shamt(IROut[10:6]),
        .Zero(Zero),
        .ALUOut(ALUOut));
    AND ANDGate(
        .Branch(Branch),
        .Zero(Zero),
        .ANDOut(ANDOut));
    OR ORGate(
        .PCWE(PCWE),
        .ANDOut(ANDOut),
        .OROut(OROut));
    ALUOutR ArithmeticLogicUnitOutRegister(
        .clk(clk),
        .ALUOutRIn(ALUOut),
        .ALUOutROut(ALUOutROut));       
    PCSelMux PCSelM(
        .PCSel(PCSel),
        .In00(ALUOut),
        .In01(ALUOutROut),
        .In10({PCOut[31:26],IROut[25:0]}),
        .MuxOut(PCSelOut));
        
    CU ControlUnit(
        .clk(clk),
        .Op(IROut[31:26]),
        .MtoRFSel(MtoRFSel),
        .RFDSel(RFDSel),
        .IDSel(IDSel),
        .PCSel(PCSel),
        .ALUIn1Sel(ALUIn1Sel),
        .ALUIn2Sel(ALUIn2Sel),
        .IRWE(IRWE),
        .MWE(MWE),
        .PCWE(PCWE),
        .Branch(Branch),
        .RFWE(RFWE),
        .ALUOp(ALUOp));
    ALUDecoder ALUD(
        .ALUOp(ALUOp),
        .Funct(IROut[5:0]),
        .ALUSel(ALUSel));
endmodule
module Top(
    input clk
    );

    

    wire [31:0] PCOut;
    

    wire [31:0] Adr;
    







    wire [31:0] MRD;
    

    wire [31:0] IROut;
    

    wire [31:0] DROut;
    

    wire [4:0] RFDSelOut;
    

    wire [31:0] MtoRFSelOut;
    

    wire [31:0] RFRD1;
    wire [31:0] RFRD2;
    

    wire [31:0] AOut;
    wire [31:0] BOut;
    

    wire [31:0] SImm;


    wire [31:0] ALUIn1MuxOut;
    

    wire [31:0] ALUIn2MuxOut;
    

    wire [31:0] ALUOut;
    wire Zero;
    

    wire ANDOut;
    wire OROut;
    

    wire [31:0] ALUOutROut;
    

    wire [31:0] PCSelOut;


    wire MtoRFSel;
    wire RFDSel;
    wire IDSel;
    wire PCSel;
    wire ALUIn1Sel;
    wire [1:0] ALUIn2Sel;
    wire IRWE;
    wire MWE;
    wire PCWE;
    wire Branch;
    wire RFWE;
    wire [1:0] ALUOp;
    

    wire [2:0] ALUSel;
    

    PC ProgramCounter(
        .clk(clk),
        .PCWE(OROut),
        .PCIn(PCSelOut),
        .PCOut(PCOut));
    AdrMux AdrM(
        .Sel(IDSel),
        .In0(PCOut),
        .In1(ALUOutROut),
        .MuxOut(Adr));
    MEM Memory(
        .clk(clk),
        .MWE(MWE),
        .MRA(Adr),
        .MWD(BOut),
        .MRD(MRD));
    IR InstructionRegister(
        .clk(clk),
        .IRWE(IRWE),
        .IRIn(MRD),
        .IROut(IROut));
    DR DataRegister(
        .clk(clk),
        .DRIn(MRD),
        .DROut(DROut));    
    RFDSelMux RFDSelM(
        .Sel(RFDSel),
        .In0(IROut[20:16]),
        .In1(IROut[15:11]),
        .MuxOut(RFDSelOut));
    MtoRFSelMux MtoRFSelM(
        .Sel(MtoRFSel),
        .In0(ALUOutROut),
        .In1(DROut),
        .MuxOut(MtoRFSelOut));
    RF RegisterFile(
        .clk(clk),
        .RFWE(RFWE),
        .RFRA1(IROut[25:21]),
        .RFRA2(IROut[20:16]),
        .RFWA(RFDSelOut),
        .RFWD(MtoRFSelOut),
        .RFRD1(RFRD1),
        .RFRD2(RFRD2));
    ABR ABRegister(
        .clk(clk),
        .AIn(RFRD1),
        .BIn(RFRD2),
        .AOut(AOut),
        .BOut(BOut));
    ALUIn1Mux ALUIn1M(
        .ALUIn1Sel(ALUIn1Sel),
        .ALUIn1In0(PCOut),
        .ALUIn1In1(AOut),
        .ALUIn1MuxOut(ALUIn1MuxOut));
    SE SignExtender(
        .Imm(IROut[15:0]),
        .SImm(SImm));
    ALUIn2Mux ALUIn2M(
        .ALUIn2Sel(ALUIn2Sel),
        .In00(BOut),
        .In01(32'b1),
        .In10(SImm),
        .ALUIn2MuxOut(ALUIn2MuxOut));
    ALU ArithmeticLogicUnit(
        .ALUSel(ALUSel),
        .ALUIn1(ALUIn1MuxOut),
        .ALUIn2(ALUIn2MuxOut),
        .shamt(IROut[10:6]),
        .Zero(Zero),
        .ALUOut(ALUOut));
    AND ANDGate(
        .Branch(Branch),
        .Zero(Zero),
        .ANDOut(ANDOut));
    OR ORGate(
        .PCWE(PCWE),
        .ANDOut(ANDOut),
        .OROut(OROut));
    ALUOutR ArithmeticLogicUnitOutRegister(
        .clk(clk),
        .ALUOutRIn(ALUOut),
        .ALUOutROut(ALUOutROut));       
    PCSelMux PCSelM(
        .PCSel(PCSel),
        .In00(ALUOut),
        .In01(ALUOutROut),
        .In10({PCOut[31:26],IROut[25:0]}),
        .MuxOut(PCSelOut));
        
    CU ControlUnit(
        .clk(clk),
        .Op(IROut[31:26]),
        .MtoRFSel(MtoRFSel),
        .RFDSel(RFDSel),
        .IDSel(IDSel),
        .PCSel(PCSel),
        .ALUIn1Sel(ALUIn1Sel),
        .ALUIn2Sel(ALUIn2Sel),
        .IRWE(IRWE),
        .MWE(MWE),
        .PCWE(PCWE),
        .Branch(Branch),
        .RFWE(RFWE),
        .ALUOp(ALUOp));
    ALUDecoder ALUD(
        .ALUOp(ALUOp),
        .Funct(IROut[5:0]),
        .ALUSel(ALUSel));
endmodule