data/full_repos/permissive/457576926/sparse_dnn_challenge/xclbin/noc/src/EB_Element.v
data/verilator_xmls/8fc446bd-fee0-4bd5-8cd0-87208d6f9c99.xml
module EBHB_Element
#(
DATA_WIDTH = 32
)
(
  clk,

  data_in,
  ready_out,
  valid_in,
  data_out,
  ready_in,
  valid_out
);
  input clk;


  input [DATA_WIDTH-1:0] data_in;
  output ready_out;
  input valid_in;
  
  output reg [DATA_WIDTH-1:0] data_out;
  input ready_in;
  output valid_out;
  
  reg full = 0;
  
  assign valid_out = full;
  assign ready_out = ~(full);
  
  always @(posedge clk)
  begin






        if ( valid_in == 1 && full == 0 )
        begin
                full = 1;
                data_out = data_in;
        end
        else if ( ready_in == 1 && full == 1 )
             begin
                 full = 0;
             end
        end


endmodule
module EBHB_Element
#(
DATA_WIDTH = 32
)
(
  clk,

  data_in,
  ready_out,
  valid_in,
  data_out,
  ready_in,
  valid_out
);

  input clk;


  input [DATA_WIDTH-1:0] data_in;
  output ready_out;
  input valid_in;
  
  output reg [DATA_WIDTH-1:0] data_out;
  input ready_in;
  output valid_out;
  
  reg full = 0;
  
  assign valid_out = full;
  assign ready_out = ~(full);
  
  always @(posedge clk)
  begin






        if ( valid_in == 1 && full == 0 )
        begin
                full = 1;
                data_out = data_in;
        end
        else if ( ready_in == 1 && full == 1 )
             begin
                 full = 0;
             end
        end


endmodule