data/full_repos/permissive/412668290/DW8051_I2C_Master_IP/sfr_mem.v
1: b"%Error-ASSIGNIN: data/full_repos/permissive/412668290/DW8051_I2C_Master_IP/sfr_mem.v:23: Assigning to input/const variable: 'data_out'\nassign data_out = mem[addr];\n       ^~~~~~~~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module  sfr_mem(        clk, 
                        addr,     
                        data_in,
                        data_out,
                        wr_n,       
                        rd_n) ; 
input           clk;                        
input   [7:0]   addr;         
input   [7:0]   data_out;     
output  [7:0]   data_in;  
input           wr_n;
input           rd_n;   
reg     [7:0]   mem [255:0];
integer   i;
initial
  begin
  for (i=0;i<=255;i=i+1)
    mem[i] = 0;
  end
  

assign data_out = mem[addr];

always @(clk)  
  begin
  if(!wr_n)     
    mem[addr] <=#1 data_in;       
  end  
  
endmodule
module  sfr_mem(        clk, 
                        addr,     
                        data_in,
                        data_out,
                        wr_n,       
                        rd_n) ;
 
input           clk;                        
input   [7:0]   addr;         
input   [7:0]   data_out;     
output  [7:0]   data_in;  
input           wr_n;
input           rd_n;   
reg     [7:0]   mem [255:0];
integer   i;
initial
  begin
  for (i=0;i<=255;i=i+1)
    mem[i] = 0;
  end
  

assign data_out = mem[addr];

always @(clk)  
  begin
  if(!wr_n)     
    mem[addr] <=#1 data_in;       
  end  
  
endmodule