data/full_repos/permissive/500128826/HDLBits/Procedures/Always_case2/top_module_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/500128826/HDLBits/Procedures/Always_case2/top_module_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #1 in = $random;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/500128826/HDLBits/Procedures/Always_case2/top_module_tb.v:28: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("top_module_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/500128826/HDLBits/Procedures/Always_case2/top_module_tb.v:29: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, top_module_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/500128826/HDLBits/Procedures/Always_case2/top_module_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #(ITERATIONS) $display("Done simulating.");\n    ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_module_tb ();

  wire [1:0] pos;

  reg [3:0] in = 32'd0;

  localparam ITERATIONS = 60;

  always begin
    #1 in = $random;
  end

  top_module uut (
      .in(in),
      .pos(pos)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule
module top_module_tb ();


  wire [1:0] pos;

  reg [3:0] in = 32'd0;

  localparam ITERATIONS = 60;

  always begin
    #1 in = $random;
  end

  top_module uut (
      .in(in),
      .pos(pos)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule