data/full_repos/permissive/418819021/lab-02/control_unit.v
1: b'%Error: data/full_repos/permissive/418819021/lab-02/control_unit.v:5: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418819021/lab-02,data/full_repos/permissive/418819021/defines.vh\n             data/full_repos/permissive/418819021/lab-02,data/full_repos/permissive/418819021/defines.vh.v\n             data/full_repos/permissive/418819021/lab-02,data/full_repos/permissive/418819021/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/418819021/lab-02/control_unit.v:19: Define or directive not defined: \'`STAGE_COUNT\'\n        output wire [`STAGE_COUNT-1:0]   pipeline_stage,\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/control_unit.v:33: Define or directive not defined: \'`OPSEL_COUNT\'\n        output reg    [`OPSEL_COUNT-1:0] alu_opsel,\n                       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/control_unit.v:42: Define or directive not defined: \'`SIGNAL_COUNT\'\n    wire [`SIGNAL_COUNT-1:0] signals;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/control_unit.v:43: Define or directive not defined: \'`OPCODE_COUNT\'\n    wire [`OPCODE_COUNT-1:0] opcode_type;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/control_unit.v:45: Define or directive not defined: \'`GROUP_COUNT\'\n    wire [`GROUP_COUNT-1:0]  opcode_group;\n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/control_unit.v:101: Define or directive not defined: \'`STAGE_WB\'\n        end else if (pipeline_stage == `STAGE_WB) begin\n                                       ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/control_unit.v:101: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        end else if (pipeline_stage == `STAGE_WB) begin\n                                                ^\n%Error: data/full_repos/permissive/418819021/lab-02/control_unit.v:124: Define or directive not defined: \'`STAGE_IF\'\n        else if (pipeline_stage == `STAGE_IF)\n                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/control_unit.v:124: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        else if (pipeline_stage == `STAGE_IF)\n                                            ^\n%Error: data/full_repos/permissive/418819021/lab-02/control_unit.v:130: Define or directive not defined: \'`STAGE_EX\'\n        else if (pipeline_stage == `STAGE_EX)\n                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/control_unit.v:130: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        else if (pipeline_stage == `STAGE_EX)\n                                            ^\n%Error: data/full_repos/permissive/418819021/lab-02/control_unit.v:143: Define or directive not defined: \'`STAGE_EX\'\n    assign alu_enable = (pipeline_stage == `STAGE_EX);\n                                           ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/control_unit.v:143: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign alu_enable = (pipeline_stage == `STAGE_EX);\n                                                    ^\n%Error: data/full_repos/permissive/418819021/lab-02/control_unit.v:149: Define or directive not defined: \'`OPSEL_COUNT\'\n            alu_opsel = `OPSEL_COUNT\'bx;\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/control_unit.v:153: Define or directive not defined: \'`TYPE_ADC\'\n            `TYPE_ADC:\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/control_unit.v:153: syntax error, unexpected \':\', expecting endcase\n            `TYPE_ADC:\n                     ^\n%Error: data/full_repos/permissive/418819021/lab-02/control_unit.v:154: Define or directive not defined: \'`OPSEL_ADC\'\n                alu_opsel = `OPSEL_ADC;\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/control_unit.v:156: Define or directive not defined: \'`TYPE_NOP\'\n            `TYPE_NOP:\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/control_unit.v:157: Define or directive not defined: \'`OPSEL_NOP\'\n                alu_opsel = `OPSEL_NOP;\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/control_unit.v:159: Define or directive not defined: \'`TYPE_NEG\'\n            `TYPE_NEG:\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/control_unit.v:160: Define or directive not defined: \'`OPSEL_NEG\'\n                alu_opsel = `OPSEL_NEG;\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/control_unit.v:162: Define or directive not defined: \'`TYPE_ADD\'\n            `TYPE_ADD:\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/control_unit.v:163: Define or directive not defined: \'`OPSEL_ADD\'\n                alu_opsel = `OPSEL_ADD;\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/control_unit.v:165: Define or directive not defined: \'`TYPE_SUB\'\n            `TYPE_SUB:\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/control_unit.v:166: Define or directive not defined: \'`OPSEL_SUB\'\n                alu_opsel = `OPSEL_SUB;\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/control_unit.v:168: Define or directive not defined: \'`TYPE_AND\'\n            `TYPE_AND:\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/control_unit.v:169: Define or directive not defined: \'`OPSEL_AND\'\n                alu_opsel = `OPSEL_AND;\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/control_unit.v:171: Define or directive not defined: \'`TYPE_OR\'\n            `TYPE_OR:\n            ^~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/control_unit.v:172: Define or directive not defined: \'`OPSEL_OR\'\n                alu_opsel = `OPSEL_OR;\n                            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/control_unit.v:175: Define or directive not defined: \'`OPSEL_NONE\'\n                alu_opsel = `OPSEL_NONE;\n                            ^~~~~~~~~~~\n%Error: Cannot continue\n'
module control_unit #(
        parameter  INSTR_WIDTH = 16,
        parameter   DATA_WIDTH = 8,
        parameter I_ADDR_WIDTH = 10,
        parameter R_ADDR_WIDTH = 5
    )(
        input  wire                    clk,
        input  wire                    reset,

        output reg  [I_ADDR_WIDTH-1:0]   program_counter,
        input  wire  [INSTR_WIDTH-1:0]   instruction,

        output wire [`STAGE_COUNT-1:0]   pipeline_stage,

        output wire [R_ADDR_WIDTH-1:0]   rr_addr,
        output wire [R_ADDR_WIDTH-1:0]   rd_addr,
        inout  wire   [DATA_WIDTH-1:0]   rr_data,
        inout  wire   [DATA_WIDTH-1:0]   rd_data,
        output wire                      rr_cs,
        output wire                      rd_cs,
        output wire                      rr_we,
        output wire                      rd_we,
        output wire                      rr_oe,
        output wire                      rd_oe,

        output wire                      alu_enable,
        output reg    [`OPSEL_COUNT-1:0] alu_opsel,
        output wire   [DATA_WIDTH-1:0]   alu_flags_in,
        input  wire   [DATA_WIDTH-1:0]   alu_flags_out,
        output reg    [DATA_WIDTH-1:0]   alu_rr,
        output reg    [DATA_WIDTH-1:0]   alu_rd,
        input  wire   [DATA_WIDTH-1:0]   alu_out
    );


    wire [`SIGNAL_COUNT-1:0] signals;
    wire [`OPCODE_COUNT-1:0] opcode_type;

    wire [`GROUP_COUNT-1:0]  opcode_group;



    reg  [INSTR_WIDTH-1:0]   instr_buffer;
    reg  [DATA_WIDTH-1:0]    alu_out_buffer;
    reg  [DATA_WIDTH-1:0]    writeback_value;
    reg  [DATA_WIDTH-1:0]    sreg;

    state_machine fsm (
        .pipeline_stage (pipeline_stage),
        .clk            (clk),
        .reset          (reset)
    );

    decode_unit #(
        .INSTR_WIDTH(INSTR_WIDTH)
    ) decode (
        .instruction  (instr_buffer),
        .opcode_type  (opcode_type),
        .opcode_group (opcode_group),
        .opcode_rd    (rd_addr),
        .opcode_rr    (rr_addr)
    );

    signal_generation_unit sig (
        .pipeline_stage (pipeline_stage),
        .signals        (signals),
        .opcode_type    (opcode_type),
        .opcode_group   (opcode_group)
    );

    reg_file_interface_unit #(
        .DATA_WIDTH   (DATA_WIDTH),
        .INSTR_WIDTH  (INSTR_WIDTH),
        .R_ADDR_WIDTH (R_ADDR_WIDTH)
    ) rf_int (
        .opcode_type     (opcode_type),
        .writeback_value (writeback_value),
        .signals         (signals),
        .rr_addr         (rr_addr),
        .rd_addr         (rd_addr),
        .rr_data         (rr_data),
        .rd_data         (rd_data),
        .rr_cs           (rr_cs),
        .rd_cs           (rd_cs),
        .rr_we           (rr_we),
        .rd_we           (rd_we),
        .rr_oe           (rr_oe),
        .rd_oe           (rd_oe)
    );


    always @(posedge clk, posedge reset) begin
        if (reset) begin
            program_counter <= 0;
        end else if (pipeline_stage == `STAGE_WB) begin
            program_counter <= program_counter + 1;
        end
    end

    assign alu_flags_in = sreg;

    always @(posedge clk, posedge reset)
        if (reset)
            sreg <= 0;
        else sreg <= alu_flags_out;

    always @(posedge clk, posedge reset) begin
        if (reset)
            writeback_value <= {DATA_WIDTH{1'b0}};
        else
            writeback_value <= alu_out_buffer;
    end


    always @(posedge clk, posedge reset)
        if (reset)
            instr_buffer <= 0;
        else if (pipeline_stage == `STAGE_IF)
             instr_buffer <= instruction;

    always @(posedge clk, posedge reset)
        if (reset)
            alu_out_buffer <= 0;
        else if (pipeline_stage == `STAGE_EX)
             alu_out_buffer <= alu_out;


    always @(posedge clk, posedge reset)
        if (reset) begin
            alu_rd <= 0;
            alu_rr <= 0;
        end else begin
              alu_rd <= rd_data;
              alu_rr <= rr_data;
        end

    assign alu_enable = (pipeline_stage == `STAGE_EX);


    always @* begin
        if (alu_enable == 0)
            alu_opsel = `OPSEL_COUNT'bx;
        else begin
            case (opcode_type)

            `TYPE_ADC:
                alu_opsel = `OPSEL_ADC;

            `TYPE_NOP:
                alu_opsel = `OPSEL_NOP;
            
            `TYPE_NEG:
                alu_opsel = `OPSEL_NEG;
            
            `TYPE_ADD:
                alu_opsel = `OPSEL_ADD;
            
            `TYPE_SUB:
                alu_opsel = `OPSEL_SUB;
			
            `TYPE_AND:
                alu_opsel = `OPSEL_AND;
            
            `TYPE_OR:
                alu_opsel = `OPSEL_OR;

            default:
                alu_opsel = `OPSEL_NONE;
            endcase
        end
    end

endmodule
module control_unit #(
        parameter  INSTR_WIDTH = 16,
        parameter   DATA_WIDTH = 8,
        parameter I_ADDR_WIDTH = 10,
        parameter R_ADDR_WIDTH = 5
    )(
        input  wire                    clk,
        input  wire                    reset,

        output reg  [I_ADDR_WIDTH-1:0]   program_counter,
        input  wire  [INSTR_WIDTH-1:0]   instruction,

        output wire [`STAGE_COUNT-1:0]   pipeline_stage,

        output wire [R_ADDR_WIDTH-1:0]   rr_addr,
        output wire [R_ADDR_WIDTH-1:0]   rd_addr,
        inout  wire   [DATA_WIDTH-1:0]   rr_data,
        inout  wire   [DATA_WIDTH-1:0]   rd_data,
        output wire                      rr_cs,
        output wire                      rd_cs,
        output wire                      rr_we,
        output wire                      rd_we,
        output wire                      rr_oe,
        output wire                      rd_oe,

        output wire                      alu_enable,
        output reg    [`OPSEL_COUNT-1:0] alu_opsel,
        output wire   [DATA_WIDTH-1:0]   alu_flags_in,
        input  wire   [DATA_WIDTH-1:0]   alu_flags_out,
        output reg    [DATA_WIDTH-1:0]   alu_rr,
        output reg    [DATA_WIDTH-1:0]   alu_rd,
        input  wire   [DATA_WIDTH-1:0]   alu_out
    );



    wire [`SIGNAL_COUNT-1:0] signals;
    wire [`OPCODE_COUNT-1:0] opcode_type;

    wire [`GROUP_COUNT-1:0]  opcode_group;



    reg  [INSTR_WIDTH-1:0]   instr_buffer;
    reg  [DATA_WIDTH-1:0]    alu_out_buffer;
    reg  [DATA_WIDTH-1:0]    writeback_value;
    reg  [DATA_WIDTH-1:0]    sreg;

    state_machine fsm (
        .pipeline_stage (pipeline_stage),
        .clk            (clk),
        .reset          (reset)
    );

    decode_unit #(
        .INSTR_WIDTH(INSTR_WIDTH)
    ) decode (
        .instruction  (instr_buffer),
        .opcode_type  (opcode_type),
        .opcode_group (opcode_group),
        .opcode_rd    (rd_addr),
        .opcode_rr    (rr_addr)
    );

    signal_generation_unit sig (
        .pipeline_stage (pipeline_stage),
        .signals        (signals),
        .opcode_type    (opcode_type),
        .opcode_group   (opcode_group)
    );

    reg_file_interface_unit #(
        .DATA_WIDTH   (DATA_WIDTH),
        .INSTR_WIDTH  (INSTR_WIDTH),
        .R_ADDR_WIDTH (R_ADDR_WIDTH)
    ) rf_int (
        .opcode_type     (opcode_type),
        .writeback_value (writeback_value),
        .signals         (signals),
        .rr_addr         (rr_addr),
        .rd_addr         (rd_addr),
        .rr_data         (rr_data),
        .rd_data         (rd_data),
        .rr_cs           (rr_cs),
        .rd_cs           (rd_cs),
        .rr_we           (rr_we),
        .rd_we           (rd_we),
        .rr_oe           (rr_oe),
        .rd_oe           (rd_oe)
    );


    always @(posedge clk, posedge reset) begin
        if (reset) begin
            program_counter <= 0;
        end else if (pipeline_stage == `STAGE_WB) begin
            program_counter <= program_counter + 1;
        end
    end

    assign alu_flags_in = sreg;

    always @(posedge clk, posedge reset)
        if (reset)
            sreg <= 0;
        else sreg <= alu_flags_out;

    always @(posedge clk, posedge reset) begin
        if (reset)
            writeback_value <= {DATA_WIDTH{1'b0}};
        else
            writeback_value <= alu_out_buffer;
    end


    always @(posedge clk, posedge reset)
        if (reset)
            instr_buffer <= 0;
        else if (pipeline_stage == `STAGE_IF)
             instr_buffer <= instruction;

    always @(posedge clk, posedge reset)
        if (reset)
            alu_out_buffer <= 0;
        else if (pipeline_stage == `STAGE_EX)
             alu_out_buffer <= alu_out;


    always @(posedge clk, posedge reset)
        if (reset) begin
            alu_rd <= 0;
            alu_rr <= 0;
        end else begin
              alu_rd <= rd_data;
              alu_rr <= rr_data;
        end

    assign alu_enable = (pipeline_stage == `STAGE_EX);


    always @* begin
        if (alu_enable == 0)
            alu_opsel = `OPSEL_COUNT'bx;
        else begin
            case (opcode_type)

            `TYPE_ADC:
                alu_opsel = `OPSEL_ADC;

            `TYPE_NOP:
                alu_opsel = `OPSEL_NOP;
            
            `TYPE_NEG:
                alu_opsel = `OPSEL_NEG;
            
            `TYPE_ADD:
                alu_opsel = `OPSEL_ADD;
            
            `TYPE_SUB:
                alu_opsel = `OPSEL_SUB;
			
            `TYPE_AND:
                alu_opsel = `OPSEL_AND;
            
            `TYPE_OR:
                alu_opsel = `OPSEL_OR;

            default:
                alu_opsel = `OPSEL_NONE;
            endcase
        end
    end

endmodule