data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv
1: b'%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:371: Cannot find include file: axi/assign.svh\n`include "axi/assign.svh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src,data/full_repos/permissive/489147019/axi/assign.svh\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src,data/full_repos/permissive/489147019/axi/assign.svh.v\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src,data/full_repos/permissive/489147019/axi/assign.svh.sv\n             axi/assign.svh\n             axi/assign.svh.v\n             axi/assign.svh.sv\n             obj_dir/axi/assign.svh\n             obj_dir/axi/assign.svh.v\n             obj_dir/axi/assign.svh.sv\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:372: Cannot find include file: axi/typedef.svh\n`include "axi/typedef.svh" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:129: syntax error, unexpected ::\n            || ((slv_req_i.aw_valid && slv_req_i.aw.atop[5:4] == axi_pkg::ATOP_NONE)\n                                                                        ^~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:136: syntax error, unexpected if, expecting endcase\n        if (slv_req_i.aw_valid && slv_req_i.aw.atop[5:4] != axi_pkg::ATOP_NONE) begin\n        ^~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:141: syntax error, unexpected ::\n          if (slv_req_i.aw.atop[5:4] != axi_pkg::ATOP_ATOMICSTORE) begin\n                                               ^~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:149: syntax error, unexpected \'=\', expecting IDENTIFIER\n            w_state_d = BLOCK_AW;\n                      ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:152: syntax error, unexpected \'=\', expecting IDENTIFIER\n            mst_req_o.w_valid  = 1\'b0;  \n                               ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:153: syntax error, unexpected \'=\', expecting IDENTIFIER\n            slv_resp_o.w_ready = 1\'b1;  \n                               ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:159: syntax error, unexpected \'=\', expecting IDENTIFIER\n                w_state_d = HOLD_B;\n                          ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:161: syntax error, unexpected \'=\', expecting IDENTIFIER\n                w_state_d = INJECT_B;\n                          ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:165: syntax error, unexpected \'=\', expecting IDENTIFIER\n              w_state_d = ABSORB_W;\n                        ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:168: syntax error, unexpected end\n        end\n        ^~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:175: syntax error, unexpected \'=\', expecting IDENTIFIER\n          slv_resp_o.w_ready = mst_resp_i.w_ready;\n                             ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:182: syntax error, unexpected \'=\', expecting IDENTIFIER\n              w_state_d = HOLD_B;\n                        ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:184: syntax error, unexpected \'=\', expecting IDENTIFIER\n              w_state_d = INJECT_B;\n                        ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:188: syntax error, unexpected \'=\', expecting IDENTIFIER\n            w_state_d = ABSORB_W;\n                      ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:198: syntax error, unexpected \'=\', expecting IDENTIFIER\n            w_state_d = HOLD_B;\n                      ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:200: syntax error, unexpected \'=\', expecting IDENTIFIER\n            w_state_d = INJECT_B;\n                      ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:203: syntax error, unexpected end\n      end\n      ^~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:218: syntax error, unexpected \'=\', expecting IDENTIFIER\n        slv_resp_o.b = \'0;\n                     ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:219: syntax error, unexpected \'.\', expecting IDENTIFIER\n        slv_resp_o.b.id = id_q;\n                    ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:220: syntax error, unexpected \'.\', expecting IDENTIFIER\n        slv_resp_o.b.resp = axi_pkg::RESP_SLVERR;\n                    ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:221: syntax error, unexpected \'=\', expecting IDENTIFIER\n        slv_resp_o.b_valid = 1\'b1;\n                           ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:226: syntax error, unexpected \'=\', expecting IDENTIFIER\n            w_state_d = WAIT_R;\n                      ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:228: syntax error, unexpected \'=\', expecting IDENTIFIER\n            w_state_d = W_FEEDTHROUGH;\n                      ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:231: syntax error, unexpected end\n      end\n      ^~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:250: syntax error, unexpected \'.\', expecting IDENTIFIER\n    mst_req_o.aw.atop = \'0;\n                ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:285: syntax error, unexpected ::, expecting \';\'\n        slv_resp_o.r.resp  = axi_pkg::RESP_SLVERR;\n                                    ^~\n                                                                                                 : ... Perhaps \'axi_pkg\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:403: Define or directive not defined: \'`AXI_TYPEDEF_AW_CHAN_T\'\n  `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)\n  ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:403: syntax error, unexpected \'(\'\n  `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:404: Define or directive not defined: \'`AXI_TYPEDEF_W_CHAN_T\'\n  `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)\n  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:405: Define or directive not defined: \'`AXI_TYPEDEF_B_CHAN_T\'\n  `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)\n  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:406: Define or directive not defined: \'`AXI_TYPEDEF_AR_CHAN_T\'\n  `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)\n  ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:407: Define or directive not defined: \'`AXI_TYPEDEF_R_CHAN_T\'\n  `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)\n  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:408: Define or directive not defined: \'`AXI_TYPEDEF_REQ_T\'\n  `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)\n  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:409: Define or directive not defined: \'`AXI_TYPEDEF_RESP_T\'\n  `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)\n  ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:414: Define or directive not defined: \'`AXI_ASSIGN_TO_REQ\'\n  `AXI_ASSIGN_TO_REQ(slv_req, slv)\n  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:414: syntax error, unexpected \'(\'\n  `AXI_ASSIGN_TO_REQ(slv_req, slv)\n                     ^~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:415: Define or directive not defined: \'`AXI_ASSIGN_FROM_RESP\'\n  `AXI_ASSIGN_FROM_RESP(slv, slv_resp)\n  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:417: Define or directive not defined: \'`AXI_ASSIGN_FROM_REQ\'\n  `AXI_ASSIGN_FROM_REQ(mst, mst_req)\n  ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/src/axi_atop_filter.sv:418: Define or directive not defined: \'`AXI_ASSIGN_TO_RESP\'\n  `AXI_ASSIGN_TO_RESP(mst_resp, mst)\n  ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 41 error(s)\n'
module axi_atop_filter_intf #(

  parameter int unsigned AXI_ID_WIDTH   = 0,

  parameter int unsigned AXI_ADDR_WIDTH = 0,

  parameter int unsigned AXI_DATA_WIDTH = 0,

  parameter int unsigned AXI_USER_WIDTH = 0,

  parameter int unsigned AXI_MAX_WRITE_TXNS = 0
) (

  input  logic    clk_i,

  input  logic    rst_ni,

  AXI_BUS.Slave   slv,

  AXI_BUS.Master  mst
);

  typedef logic [AXI_ID_WIDTH-1:0]     id_t;
  typedef logic [AXI_ADDR_WIDTH-1:0]   addr_t;
  typedef logic [AXI_DATA_WIDTH-1:0]   data_t;
  typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
  typedef logic [AXI_USER_WIDTH-1:0]   user_t;

  `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
  `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
  `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
  `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
  `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
  `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
  `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)

  req_t  slv_req,  mst_req;
  resp_t slv_resp, mst_resp;

  `AXI_ASSIGN_TO_REQ(slv_req, slv)
  `AXI_ASSIGN_FROM_RESP(slv, slv_resp)

  `AXI_ASSIGN_FROM_REQ(mst, mst_req)
  `AXI_ASSIGN_TO_RESP(mst_resp, mst)

  axi_atop_filter #(
    .AxiIdWidth      ( AXI_ID_WIDTH       ),

    .AxiMaxWriteTxns ( AXI_MAX_WRITE_TXNS ),

    .req_t           ( req_t              ),
    .resp_t          ( resp_t             )
  ) i_axi_atop_filter (
    .clk_i,
    .rst_ni,
    .slv_req_i  ( slv_req  ),
    .slv_resp_o ( slv_resp ),
    .mst_req_o  ( mst_req  ),
    .mst_resp_i ( mst_resp )
  );

`ifndef VERILATOR
  initial begin: p_assertions
    assert (AXI_ADDR_WIDTH >= 1) else $fatal(1, "AXI ADDR width must be at least 1!");
    assert (AXI_DATA_WIDTH >= 1) else $fatal(1, "AXI DATA width must be at least 1!");
    assert (AXI_USER_WIDTH >= 1) else $fatal(1, "AXI USER width must be at least 1!");
  end
`endif

endmodule
module axi_atop_filter_intf #(

  parameter int unsigned AXI_ID_WIDTH   = 0,

  parameter int unsigned AXI_ADDR_WIDTH = 0,

  parameter int unsigned AXI_DATA_WIDTH = 0,

  parameter int unsigned AXI_USER_WIDTH = 0,

  parameter int unsigned AXI_MAX_WRITE_TXNS = 0
) (

  input  logic    clk_i,

  input  logic    rst_ni,

  AXI_BUS.Slave   slv,

  AXI_BUS.Master  mst
);


  typedef logic [AXI_ID_WIDTH-1:0]     id_t;
  typedef logic [AXI_ADDR_WIDTH-1:0]   addr_t;
  typedef logic [AXI_DATA_WIDTH-1:0]   data_t;
  typedef logic [AXI_DATA_WIDTH/8-1:0] strb_t;
  typedef logic [AXI_USER_WIDTH-1:0]   user_t;

  `AXI_TYPEDEF_AW_CHAN_T(aw_chan_t, addr_t, id_t, user_t)
  `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t)
  `AXI_TYPEDEF_B_CHAN_T(b_chan_t, id_t, user_t)
  `AXI_TYPEDEF_AR_CHAN_T(ar_chan_t, addr_t, id_t, user_t)
  `AXI_TYPEDEF_R_CHAN_T(r_chan_t, data_t, id_t, user_t)
  `AXI_TYPEDEF_REQ_T(req_t, aw_chan_t, w_chan_t, ar_chan_t)
  `AXI_TYPEDEF_RESP_T(resp_t, b_chan_t, r_chan_t)

  req_t  slv_req,  mst_req;
  resp_t slv_resp, mst_resp;

  `AXI_ASSIGN_TO_REQ(slv_req, slv)
  `AXI_ASSIGN_FROM_RESP(slv, slv_resp)

  `AXI_ASSIGN_FROM_REQ(mst, mst_req)
  `AXI_ASSIGN_TO_RESP(mst_resp, mst)

  axi_atop_filter #(
    .AxiIdWidth      ( AXI_ID_WIDTH       ),

    .AxiMaxWriteTxns ( AXI_MAX_WRITE_TXNS ),

    .req_t           ( req_t              ),
    .resp_t          ( resp_t             )
  ) i_axi_atop_filter (
    .clk_i,
    .rst_ni,
    .slv_req_i  ( slv_req  ),
    .slv_resp_o ( slv_resp ),
    .mst_req_o  ( mst_req  ),
    .mst_resp_i ( mst_resp )
  );

`ifndef VERILATOR
  initial begin: p_assertions
    assert (AXI_ADDR_WIDTH >= 1) else $fatal(1, "AXI ADDR width must be at least 1!");
    assert (AXI_DATA_WIDTH >= 1) else $fatal(1, "AXI DATA width must be at least 1!");
    assert (AXI_USER_WIDTH >= 1) else $fatal(1, "AXI USER width must be at least 1!");
  end
`endif

endmodule