data/full_repos/permissive/482979608/ADPCM.srcs/sources_1/new/DELTA_PLUS.v
data/verilator_xmls/698b51d6-ca34-44d7-9b12-4cbfce62d37c.xml
module DELTA_PLUS #(parameter WLI = 1, WLF = 15, WL = WLI + WLF)(
    input signed [WL-1:0] delta,
    input codeWord,
    output reg signed [WL-1:0] deltaP1
    );
    wire [WL-1:0] deltaDiv, deltaMult;
    assign deltaDiv = delta >>> 1;
    assign deltaMult = delta <<< 1;
    
    always @(*) begin
        if (codeWord == 'b0)
            deltaP1 = deltaDiv;
        else if (codeWord == 'b1) 
            deltaP1 = deltaMult;
    end
endmodule
module DELTA_PLUS #(parameter WLI = 1, WLF = 15, WL = WLI + WLF)(
    input signed [WL-1:0] delta,
    input codeWord,
    output reg signed [WL-1:0] deltaP1
    );

    wire [WL-1:0] deltaDiv, deltaMult;
    assign deltaDiv = delta >>> 1;
    assign deltaMult = delta <<< 1;
    
    always @(*) begin
        if (codeWord == 'b0)
            deltaP1 = deltaDiv;
        else if (codeWord == 'b1) 
            deltaP1 = deltaMult;
    end
endmodule