data/full_repos/permissive/507312280/rtl/perips/sysio/gpio.v
1: b'%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/gpio.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507312280/rtl/perips/sysio,data/full_repos/permissive/507312280/defines.v\n             data/full_repos/permissive/507312280/rtl/perips/sysio,data/full_repos/permissive/507312280/defines.v.v\n             data/full_repos/permissive/507312280/rtl/perips/sysio,data/full_repos/permissive/507312280/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/gpio.v:7: Define or directive not defined: \'`MemBus\'\n    input wire[`MemBus] data_i,\n               ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/gpio.v:7: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire[`MemBus] data_i,\n                      ^\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/gpio.v:9: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire we_i,\n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/gpio.v:10: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[7:0] raddr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/gpio.v:11: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire rd_i,\n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/gpio.v:12: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg[`MemBus] data_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/gpio.v:12: Define or directive not defined: \'`MemBus\'\n    output reg[`MemBus] data_o,\n               ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/gpio.v:15: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n output reg [31:0]gpio_out, \n ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/gpio.v:16: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input wire [31:0]gpio_in \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/gpio.v:17: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/gpio.v:47: syntax error, unexpected always\nalways @ (posedge clk ) begin\n^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/gpio.v:88: syntax error, unexpected always\nalways @(posedge clk) begin\n^~~~~~\n%Error: Exiting due to 13 error(s)\n'
module gpio (
    input wire clk,
    input wire rst_n,

    input wire[7:0] waddr_i,
    input wire[`MemBus] data_i,
    input wire[3:0] sel_i,
    input wire we_i,
    input wire[7:0] raddr_i,
    input wire rd_i,
    output reg[`MemBus] data_o,

	output reg [31:0]gpio_oe,
	output reg [31:0]gpio_out,
    input wire [31:0]gpio_in
);
genvar i;

localparam GPIO_DIN = 8'h0;
localparam GPIO_OPT = 8'h4;
localparam GPIO_OEC = 8'h8;
localparam GPIO_OMD = 8'hc;



reg [31:0] gpio_din;



reg [31:0] gpio_opt;


reg [31:0] gpio_oec;
reg [31:0] gpio_omd;



always @ (posedge clk) begin






        if (we_i == 1'b1) begin
            case (waddr_i)
                GPIO_DIN: ;
                GPIO_OPT: gpio_opt <= data_i;
                GPIO_OEC: gpio_oec <= data_i;
                GPIO_OMD: gpio_omd <= data_i;
                default: ;
            endcase
        end 
        else begin
        end

end


always @ (posedge clk) begin
    if (rd_i == 1'b1) begin
        case (raddr_i)
                GPIO_DIN: data_o <= gpio_din;
                GPIO_OPT: data_o <= gpio_opt;
                GPIO_OEC: data_o <= gpio_oec;
                GPIO_OMD: data_o <= gpio_omd;
            default: begin
                data_o <= 32'h0;
            end
        endcase
    end
    else begin
        data_o <= data_o;
    end
end


reg [31:0] gpio_in_r;
always @(posedge clk) begin
	gpio_in_r <= gpio_in;
end
generate
for (i=0; i<32; i=i+1) begin
    always @(posedge clk) begin
        if({gpio_oec, gpio_omd[i]}==2'b01)
            gpio_din[i] <= gpio_din[i];
        else
            gpio_din[i] <= gpio_in_r[i];
    end
end
endgenerate


generate
for (i=0; i<32; i=i+1) begin
    always @(*) begin
        case ({gpio_oec[i], gpio_omd[i]})
            2'b00: begin
                gpio_oe [i] = 1'b0;
                gpio_out[i] = 1'bx;
            end
            2'b01: begin
                gpio_oe [i] = 1'b0;
                gpio_out[i] = 1'bx;
            end
            2'b10: begin
                gpio_oe [i] = 1'b1;
                gpio_out[i] = gpio_opt[i];
            end
            2'b11: begin
                gpio_oe [i] = ~gpio_opt[i];
                gpio_out[i] = 1'b0;
            end
        endcase
    end
end
endgenerate


endmodule
module gpio (
    input wire clk,
    input wire rst_n,

    input wire[7:0] waddr_i,
    input wire[`MemBus] data_i,
    input wire[3:0] sel_i,
    input wire we_i,
    input wire[7:0] raddr_i,
    input wire rd_i,
    output reg[`MemBus] data_o,

	output reg [31:0]gpio_oe,
	output reg [31:0]gpio_out,
    input wire [31:0]gpio_in
);

genvar i;

localparam GPIO_DIN = 8'h0;
localparam GPIO_OPT = 8'h4;
localparam GPIO_OEC = 8'h8;
localparam GPIO_OMD = 8'hc;



reg [31:0] gpio_din;



reg [31:0] gpio_opt;


reg [31:0] gpio_oec;
reg [31:0] gpio_omd;



always @ (posedge clk) begin






        if (we_i == 1'b1) begin
            case (waddr_i)
                GPIO_DIN: ;
                GPIO_OPT: gpio_opt <= data_i;
                GPIO_OEC: gpio_oec <= data_i;
                GPIO_OMD: gpio_omd <= data_i;
                default: ;
            endcase
        end 
        else begin
        end

end


always @ (posedge clk) begin
    if (rd_i == 1'b1) begin
        case (raddr_i)
                GPIO_DIN: data_o <= gpio_din;
                GPIO_OPT: data_o <= gpio_opt;
                GPIO_OEC: data_o <= gpio_oec;
                GPIO_OMD: data_o <= gpio_omd;
            default: begin
                data_o <= 32'h0;
            end
        endcase
    end
    else begin
        data_o <= data_o;
    end
end


reg [31:0] gpio_in_r;
always @(posedge clk) begin
	gpio_in_r <= gpio_in;
end
generate
for (i=0; i<32; i=i+1) begin
    always @(posedge clk) begin
        if({gpio_oec, gpio_omd[i]}==2'b01)
            gpio_din[i] <= gpio_din[i];
        else
            gpio_din[i] <= gpio_in_r[i];
    end
end
endgenerate


generate
for (i=0; i<32; i=i+1) begin
    always @(*) begin
        case ({gpio_oec[i], gpio_omd[i]})
            2'b00: begin
                gpio_oe [i] = 1'b0;
                gpio_out[i] = 1'bx;
            end
            2'b01: begin
                gpio_oe [i] = 1'b0;
                gpio_out[i] = 1'bx;
            end
            2'b10: begin
                gpio_oe [i] = 1'b1;
                gpio_out[i] = gpio_opt[i];
            end
            2'b11: begin
                gpio_oe [i] = ~gpio_opt[i];
                gpio_out[i] = 1'b0;
            end
        endcase
    end
end
endgenerate


endmodule