data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/main.v
1: b"%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/main.v:71: syntax error, unexpected output, expecting ')' or ','\nmodule nor5 (input wire i0, i1, i2, i3, i4 output wire o);\n                                           ^~~~~~\n%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/main.v:73: syntax error, unexpected IDENTIFIER\n   or2 or2_0 (i0, i1, t0);\n   ^~~\n%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/main.v:387: syntax error, unexpected IDENTIFIER, expecting ',' or ';'\n pc_inc = load_ir\n ^~~~~~\n%Error: Cannot continue\n"
module reg_alu (input wire clk, reset, sel, wr, input wire [1:0] op, input wire [2:0] rd_addr_a,
  rd_addr_b, wr_addr, input wire [15:0] d_in, output wire [15:0] d_out_a, d_out_b, output wire cout);
  wire [15:0] d_in_alu, d_in_reg; wire cout_0;
  alu alu_0 (op, d_out_a, d_out_b, d_in_alu, cout_0);
  reg_file reg_file_0 (clk, reset, wr, rd_addr_a, rd_addr_b, wr_addr, d_in_reg, d_out_a, d_out_b);
  mux2_16 mux2_16_0 (d_in, d_in_alu, sel, d_in_reg);
  dfr dfr_0 (clk, reset, cout_0, cout);
endmodule
module reg_alu (input wire clk, reset, sel, wr, input wire [1:0] op, input wire [2:0] rd_addr_a,
  rd_addr_b, wr_addr, input wire [15:0] d_in, output wire [15:0] d_out_a, d_out_b, output wire cout);

  wire [15:0] d_in_alu, d_in_reg; wire cout_0;
  alu alu_0 (op, d_out_a, d_out_b, d_in_alu, cout_0);
  reg_file reg_file_0 (clk, reset, wr, rd_addr_a, rd_addr_b, wr_addr, d_in_reg, d_out_a, d_out_b);
  mux2_16 mux2_16_0 (d_in, d_in_alu, sel, d_in_reg);
  dfr dfr_0 (clk, reset, cout_0, cout);
endmodule