data/full_repos/permissive/432564927/Lab5HN (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new/CPU.v
1: b'%Error: Cannot find file containing module: (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927\n        ... Looked in:\n             data/full_repos/permissive/432564927/Lab5HN/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927\n             data/full_repos/permissive/432564927/Lab5HN/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             data/full_repos/permissive/432564927/Lab5HN/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927\n             (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             obj_dir/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927\n             obj_dir/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             obj_dir/(Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/432564927/Lab5HN\n%Error: Cannot find file containing module: (Verilog)/Lab5HN_Unal/Lab5HonorsOption.srcs/sources_1/new/CPU.v\n%Error: Exiting due to 3 error(s)\n'
module ForwardAMux(fwda,qa,maluOut,mqb,dmOut,fwda_out);



    input [1:0] fwda;
    input [31:0] qa, maluOut, mqb, dmOut;
    output fwda_out;
    reg [31:0] fwda_out;
    
    always @ (qa or maluOut or mqb or dmOut or fwda)
    begin
        case (fwda)
            2'b00: fwda_out <= qa;
            2'b01: fwda_out <= maluOut;
            2'b10: fwda_out <= mqb;
            2'b11: fwda_out <= dmOut;
        endcase
    end
endmodule
module ForwardAMux(fwda,qa,maluOut,mqb,dmOut,fwda_out);




    input [1:0] fwda;
    input [31:0] qa, maluOut, mqb, dmOut;
    output fwda_out;
    reg [31:0] fwda_out;
    
    always @ (qa or maluOut or mqb or dmOut or fwda)
    begin
        case (fwda)
            2'b00: fwda_out <= qa;
            2'b01: fwda_out <= maluOut;
            2'b10: fwda_out <= mqb;
            2'b11: fwda_out <= dmOut;
        endcase
    end
endmodule