data/full_repos/permissive/497870922/testbench/SPI slave/spi_slave_model.v
1: b'%Error: Cannot find file containing module: slave,data/full_repos/permissive/497870922\n        ... Looked in:\n             data/full_repos/permissive/497870922/testbench/SPI/slave,data/full_repos/permissive/497870922\n             data/full_repos/permissive/497870922/testbench/SPI/slave,data/full_repos/permissive/497870922.v\n             data/full_repos/permissive/497870922/testbench/SPI/slave,data/full_repos/permissive/497870922.sv\n             slave,data/full_repos/permissive/497870922\n             slave,data/full_repos/permissive/497870922.v\n             slave,data/full_repos/permissive/497870922.sv\n             obj_dir/slave,data/full_repos/permissive/497870922\n             obj_dir/slave,data/full_repos/permissive/497870922.v\n             obj_dir/slave,data/full_repos/permissive/497870922.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/497870922/testbench/SPI\n%Error: Cannot find file containing module: slave/spi_slave_model.v\n%Error: Exiting due to 3 error(s)\n'
module spi_slave_model_2 (
	input  wire clock,
	input  wire csn,
	input  wire sck,
	input  wire di,
	output wire do,
	input  wire cpol_i,
	input  wire cpha_i
);

	reg [5:0] reset_cnt = 0;
	wire resetn = &reset_cnt;

	always @(posedge clock) begin
		reset_cnt <= reset_cnt + !resetn;
	end








	reg [7:0] mem [7:0];
	reg [2:0] mem_adr = 0;

	reg [7:0] sri = 0;
	reg [7:0] sro = 0;

	reg [2:0] bit_cnt = 3'b111;
	reg       ld = 0;

	wire clk;

	reg [16:0] mem_cnt = 0;





	assign clk = cpol_i ^ cpha_i ^ sck;


	always @(posedge clk)
	  		sri <= {sri[6:0],di};



	always @(negedge clk)
		if (&bit_cnt)
			sro <=  mem[mem_adr];
		else
			sro <=  {sro[6:0],1'b0};

	assign do = sro[7];


	always @(posedge clk, posedge csn)
		if(csn)
	    	bit_cnt <=  3'b111;
	  	else
	    	bit_cnt <=  bit_cnt - 3'h1;


    always @(posedge clk)
		ld <= ~(|bit_cnt);

	always @(negedge clock) begin
		if (ld && clk && mem_cnt == 1) begin
			mem[mem_adr] <=  sri;
	    	mem_adr      <= mem_adr + 1'b1;
	    end else begin
	    	mem[mem_adr] <=  mem[mem_adr];
	    	mem_adr      <=  mem_adr;
	    end
	end

	always @(posedge clock) begin
		if(ld && clk) begin
			mem_cnt <= mem_cnt + 1;
		end
		else mem_cnt <= 0;
	end


endmodule
module spi_slave_model_2 (
	input  wire clock,
	input  wire csn,
	input  wire sck,
	input  wire di,
	output wire do,
	input  wire cpol_i,
	input  wire cpha_i
);


	reg [5:0] reset_cnt = 0;
	wire resetn = &reset_cnt;

	always @(posedge clock) begin
		reset_cnt <= reset_cnt + !resetn;
	end








	reg [7:0] mem [7:0];
	reg [2:0] mem_adr = 0;

	reg [7:0] sri = 0;
	reg [7:0] sro = 0;

	reg [2:0] bit_cnt = 3'b111;
	reg       ld = 0;

	wire clk;

	reg [16:0] mem_cnt = 0;





	assign clk = cpol_i ^ cpha_i ^ sck;


	always @(posedge clk)
	  		sri <= {sri[6:0],di};



	always @(negedge clk)
		if (&bit_cnt)
			sro <=  mem[mem_adr];
		else
			sro <=  {sro[6:0],1'b0};

	assign do = sro[7];


	always @(posedge clk, posedge csn)
		if(csn)
	    	bit_cnt <=  3'b111;
	  	else
	    	bit_cnt <=  bit_cnt - 3'h1;


    always @(posedge clk)
		ld <= ~(|bit_cnt);

	always @(negedge clock) begin
		if (ld && clk && mem_cnt == 1) begin
			mem[mem_adr] <=  sri;
	    	mem_adr      <= mem_adr + 1'b1;
	    end else begin
	    	mem[mem_adr] <=  mem[mem_adr];
	    	mem_adr      <=  mem_adr;
	    end
	end

	always @(posedge clock) begin
		if(ld && clk) begin
			mem_cnt <= mem_cnt + 1;
		end
		else mem_cnt <= 0;
	end


endmodule