data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Counters/Count15/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Counters/Count15,data/full_repos/permissive/500128826\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/Count15,data/full_repos/permissive/500128826\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/Count15,data/full_repos/permissive/500128826.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/Count15,data/full_repos/permissive/500128826.sv\n             Logic/Counters/Count15,data/full_repos/permissive/500128826\n             Logic/Counters/Count15,data/full_repos/permissive/500128826.v\n             Logic/Counters/Count15,data/full_repos/permissive/500128826.sv\n             obj_dir/Logic/Counters/Count15,data/full_repos/permissive/500128826\n             obj_dir/Logic/Counters/Count15,data/full_repos/permissive/500128826.v\n             obj_dir/Logic/Counters/Count15,data/full_repos/permissive/500128826.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Logic/Counters/Count15/top_module.v\n%Error: Exiting due to 3 error(s)\n'
module top_module (
    input  wire       clk,
    input  wire       reset,
    output wire [3:0] q
);

  reg [3:0] counter = 4'b0;

  always @(posedge clk) begin
    if (reset) counter <= 4'b0;
    else counter <= counter + 1'b1;
  end

  assign q = counter;

endmodule
module top_module (
    input  wire       clk,
    input  wire       reset,
    output wire [3:0] q
);


  reg [3:0] counter = 4'b0;

  always @(posedge clk) begin
    if (reset) counter <= 4'b0;
    else counter <= counter + 1'b1;
  end

  assign q = counter;

endmodule