data/full_repos/permissive/51595169/VerilogSource/CPU/Register2.v
data/verilator_xmls/4dda1cce-3903-4481-8461-9006b7f3515c.xml
module Register2(input [31:0] IN,IN2,input Clk, Reset,Load,Load2,output [31:0] OUT);
reg [31:0] d;
assign OUT = d;
always@(negedge Clk)
begin
	if(Load)
		d=IN;
	else if(Load2)
		d=IN2;
end

always@(Reset)
	d=0;

endmodule
module Register2(input [31:0] IN,IN2,input Clk, Reset,Load,Load2,output [31:0] OUT);

reg [31:0] d;
assign OUT = d;
always@(negedge Clk)
begin
	if(Load)
		d=IN;
	else if(Load2)
		d=IN2;
end

always@(Reset)
	d=0;

endmodule