data/full_repos/permissive/449807379/CPU_design/final_design_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/final_design_testbench.v:14: Unsupported: Ignoring delay on this delayed statement.\n#5 pc_reset = 1;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/449807379/CPU_design/final_design_testbench.v:17: Unsupported or unknown PLI call: $writememb\n#40 $writememb("ram_output.txt", fd.mcwr1.ram1.RAM); $finish;\n    ^~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/final_design_testbench.v:17: Unsupported: Ignoring delay on this delayed statement.\n#40 $writememb("ram_output.txt", fd.mcwr1.ram1.RAM); $finish;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/final_design_testbench.v:23: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n%Error: data/full_repos/permissive/449807379/CPU_design/final_design_testbench.v:28: Unsupported or unknown PLI call: $monitor\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module final_design_test;

reg clk;
reg pc_reset;
wire [3:0] flags;

initial
begin

$readmemb("demo_v2_c1.txt", fd.mcwr1.ram1.RAM);
$readmemb("demo_v2_c1.txt", fd.mcwr1.ram2.RAM);

clk = 0; pc_reset = 0;
#5 pc_reset = 1;


#40 $writememb("ram_output.txt", fd.mcwr1.ram1.RAM); $finish;


end


always #5 clk = ~clk;


initial
begin
$monitor("r0 =%d,r1 =%d,r2 =%d,r3 =%d\nr4 =%d,r5 =%d,r6 =%d,r7 =%d\nr8 =%d,r9 =%d,r10=%d,r11=%d\nr12=%d,r13=%d,r14=%d,r15=%d\nFLAGS (NZCV)=%b\npc_counter=%d\n\n\ninstruction=%b", fd.rgb1.out1, fd.rgb1.out2, fd.rgb1.out3, fd.rgb1.out4, fd.rgb1.out5, fd.rgb1.out6, fd.rgb1.out7, fd.rgb1.out8, fd.rgb1.out9, fd.rgb1.out10, fd.rgb1.out11, fd.rgb1.out12, fd.rgb1.out13, fd.rgb1.out14, fd.rgb1.out15, fd.rgb1.out16,flags,  fd.pc_counter, fd.instruction);

end

final_design fd(clk, pc_reset, flags);

endmodule
module final_design_test;


reg clk;
reg pc_reset;
wire [3:0] flags;

initial
begin

$readmemb("demo_v2_c1.txt", fd.mcwr1.ram1.RAM);
$readmemb("demo_v2_c1.txt", fd.mcwr1.ram2.RAM);

clk = 0; pc_reset = 0;
#5 pc_reset = 1;


#40 $writememb("ram_output.txt", fd.mcwr1.ram1.RAM); $finish;


end


always #5 clk = ~clk;


initial
begin
$monitor("r0 =%d,r1 =%d,r2 =%d,r3 =%d\nr4 =%d,r5 =%d,r6 =%d,r7 =%d\nr8 =%d,r9 =%d,r10=%d,r11=%d\nr12=%d,r13=%d,r14=%d,r15=%d\nFLAGS (NZCV)=%b\npc_counter=%d\n\n\ninstruction=%b", fd.rgb1.out1, fd.rgb1.out2, fd.rgb1.out3, fd.rgb1.out4, fd.rgb1.out5, fd.rgb1.out6, fd.rgb1.out7, fd.rgb1.out8, fd.rgb1.out9, fd.rgb1.out10, fd.rgb1.out11, fd.rgb1.out12, fd.rgb1.out13, fd.rgb1.out14, fd.rgb1.out15, fd.rgb1.out16,flags,  fd.pc_counter, fd.instruction);

end

final_design fd(clk, pc_reset, flags);

endmodule