data/full_repos/permissive/477054115/Mips16_singlecycle/decoder.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/477054115/Mips16_singlecycle/decoder.v:45: Signal definition not found, creating implicitly: \'f1\'\n  and #(50) and1(f1,a,b,c,d),  \n                 ^~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/477054115/Mips16_singlecycle/decoder.v:51: Signal definition not found, creating implicitly: \'Nota\'\n not #(50) Inv4(Nota, Adr[4]);  \n                ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/477054115/Mips16_singlecycle/decoder.v:52: Signal definition not found, creating implicitly: \'Notb\'\n                                                                                       : ... Suggested alternative: \'Nota\'\n not #(50) Inv3(Notb, Adr[3]);  \n                ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/477054115/Mips16_singlecycle/decoder.v:53: Signal definition not found, creating implicitly: \'Notc\'\n                                                                                       : ... Suggested alternative: \'Nota\'\n not #(50) Inv2(Notc, Adr[2]);  \n                ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/477054115/Mips16_singlecycle/decoder.v:54: Signal definition not found, creating implicitly: \'Notd\'\n                                                                                       : ... Suggested alternative: \'Nota\'\n not #(50) Inv1(Notd, Adr[1]);  \n                ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/477054115/Mips16_singlecycle/decoder.v:55: Signal definition not found, creating implicitly: \'Note\'\n                                                                                       : ... Suggested alternative: \'Nota\'\n not #(50) Inv0(Note, Adr[0]);  \n                ^~~~\n%Error: Exiting due to 6 warning(s)\n'
module andmore(g,a,b,c,d,e);  
  output g;  
  input a,b,c,d,e;  
  and #(50) and1(f1,a,b,c,d),  
       and2(g,f1,e);  
 endmodule
module andmore(g,a,b,c,d,e);
  
  output g;  
  input a,b,c,d,e;  
  and #(50) and1(f1,a,b,c,d),  
       and2(g,f1,e);  
 endmodule