data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/mem_ext_big.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/mem_ext_big.v:29: Multiple top level modules\n                                                                                                        : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                        : ... Top module \'data_arrays_0_ext\'\nmodule data_arrays_0_ext(\n       ^~~~~~~~~~~~~~~~~\n                                                                                                        : ... Top module \'tag_array_ext\'\nmodule tag_array_ext(\n       ^~~~~~~~~~~~~\n                                                                                                        : ... Top module \'tag_array_0_ext\'\nmodule tag_array_0_ext(\n       ^~~~~~~~~~~~~~~\n                                                                                                        : ... Top module \'data_arrays_0_0_ext\'\nmodule data_arrays_0_0_ext(\n       ^~~~~~~~~~~~~~~~~~~\n                                                                                                        : ... Top module \'l2_tlb_ram_ext\'\nmodule l2_tlb_ram_ext(\n       ^~~~~~~~~~~~~~\n                                                                                                        : ... Top module \'cc_dir_ext\'\nmodule cc_dir_ext(\n       ^~~~~~~~~~\n                                                                                                        : ... Top module \'cc_banks_0_ext\'\nmodule cc_banks_0_ext(\n       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/mem_ext_big.v:323: Cannot find file containing module: \'mem_sp_wrap\'\n    mem_sp_wrap #(\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog,data/full_repos/permissive/463204869/mem_sp_wrap\n             data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog,data/full_repos/permissive/463204869/mem_sp_wrap.v\n             data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog,data/full_repos/permissive/463204869/mem_sp_wrap.sv\n             mem_sp_wrap\n             mem_sp_wrap.v\n             mem_sp_wrap.sv\n             obj_dir/mem_sp_wrap\n             obj_dir/mem_sp_wrap.v\n             obj_dir/mem_sp_wrap.sv\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/mem_ext_big.v:269: Cannot find file containing module: \'mem_sp_wrap\'\n    mem_sp_wrap #(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/mem_ext_big.v:283: Cannot find file containing module: \'mem_sp_wrap\'\n    mem_sp_wrap #(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/mem_ext_big.v:297: Cannot find file containing module: \'mem_sp_wrap\'\n    mem_sp_wrap #(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/mem_ext_big.v:216: Cannot find file containing module: \'mem_sp_wrap\'\n    mem_sp_wrap #(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/mem_ext_big.v:189: Cannot find file containing module: \'mem_sp_wrap\'\n    mem_sp_wrap #(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/mem_ext_big.v:120: Cannot find file containing module: \'mem_sp_wrap\'\n    mem_sp_wrap #(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/mem_ext_big.v:134: Cannot find file containing module: \'mem_sp_wrap\'\n    mem_sp_wrap #(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/mem_ext_big.v:148: Cannot find file containing module: \'mem_sp_wrap\'\n    mem_sp_wrap #(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/mem_ext_big.v:162: Cannot find file containing module: \'mem_sp_wrap\'\n    mem_sp_wrap #(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/mem_ext_big.v:45: Cannot find file containing module: \'mem_sp_wrap\'\n    mem_sp_wrap #(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/mem_ext_big.v:59: Cannot find file containing module: \'mem_sp_wrap\'\n    mem_sp_wrap #(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/mem_ext_big.v:73: Cannot find file containing module: \'mem_sp_wrap\'\n    mem_sp_wrap #(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/mem_ext_big.v:87: Cannot find file containing module: \'mem_sp_wrap\'\n    mem_sp_wrap #(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/mem_ext_big.v:12: Cannot find file containing module: \'mem_sp_wrap\'\n    mem_sp_wrap #(\n    ^~~~~~~~~~~\n%Error: Exiting due to 15 error(s), 1 warning(s)\n'
module cc_dir_ext(
  input  [9:0]   RW0_addr,
  input          RW0_clk,
  input  [159:0] RW0_wdata,
  output [159:0] RW0_rdata,
  input          RW0_en,
  input          RW0_wmode,
  input  [7:0]   RW0_wmask
);

    wire [63:0] tmp_rdata0;
    wire [63:0] tmp_rdata1;
    wire [63:0] tmp_rdata2;
    assign RW0_rdata = {tmp_rdata2[59:40], tmp_rdata2[35:16], tmp_rdata2[11:0],
                        tmp_rdata1[63:56], tmp_rdata1[51:32], tmp_rdata1[27:8], tmp_rdata1[3:0],
                        tmp_rdata0[63:48], tmp_rdata0[43:24], tmp_rdata0[19:0]};



    wire [63:0] tmp_wdata0 = {RW0_wdata[55:40], 4'h0, RW0_wdata[39:20], 4'h0, RW0_wdata[19:0]};
    wire [63:0] tmp_wdata1 = {RW0_wdata[107:100], 4'h0, RW0_wdata[99:80], 4'h0, RW0_wdata[79:60], 4'h0, RW0_wdata[59:56]};
    wire [63:0] tmp_wdata2 = {4'h0, RW0_wdata[159:140], 4'h0, RW0_wdata[139:120], 4'h0, RW0_wdata[119:108]};

    wire [7:0] tmp_wmask0 = {RW0_wmask[2], RW0_wmask[2],
                             RW0_wmask[1], RW0_wmask[1],
                             RW0_wmask[1], RW0_wmask[0],
                             RW0_wmask[0], RW0_wmask[0]};
    wire [7:0] tmp_wmask1 = {RW0_wmask[5], RW0_wmask[4],
                             RW0_wmask[4], RW0_wmask[4],
                             RW0_wmask[3], RW0_wmask[3],
                             RW0_wmask[3], RW0_wmask[2]};
    wire [7:0] tmp_wmask2 = {RW0_wmask[7], RW0_wmask[7],
                             RW0_wmask[7], RW0_wmask[6],
                             RW0_wmask[6], RW0_wmask[6],
                             RW0_wmask[5], RW0_wmask[5]};

    mem_sp_wrap #(
        .MEM_TYPE("block"),
        .MEM_DATAWIDTH(64),
        .MEM_ADDRWIDTH(10)
    ) cc_dir_ext_64x1024_0 (
        .clk    (RW0_clk),
        .reset  (1'b0),
        .en     (RW0_en),
        .we     ({8{RW0_wmode}} & tmp_wmask0),
        .addr   (RW0_addr),
        .din    (tmp_wdata0),
        .dout   (tmp_rdata0)
    );

    mem_sp_wrap #(
        .MEM_TYPE("block"),
        .MEM_DATAWIDTH(64),
        .MEM_ADDRWIDTH(10)
    ) cc_dir_ext_64x1024_1 (
        .clk    (RW0_clk),
        .reset  (1'b0),
        .en     (RW0_en),
        .we     ({8{RW0_wmode}} & tmp_wmask1),
        .addr   (RW0_addr),
        .din    (tmp_wdata1),
        .dout   (tmp_rdata1)
    );

    mem_sp_wrap #(
        .MEM_TYPE("block"),
        .MEM_DATAWIDTH(64),
        .MEM_ADDRWIDTH(10)
    ) cc_dir_ext_64x1024_2 (
        .clk    (RW0_clk),
        .reset  (1'b0),
        .en     (RW0_en),
        .we     ({8{RW0_wmode}} & tmp_wmask2),
        .addr   (RW0_addr),
        .din    (tmp_wdata2),
        .dout   (tmp_rdata2)
    );

endmodule
module cc_dir_ext(
  input  [9:0]   RW0_addr,
  input          RW0_clk,
  input  [159:0] RW0_wdata,
  output [159:0] RW0_rdata,
  input          RW0_en,
  input          RW0_wmode,
  input  [7:0]   RW0_wmask
);


    wire [63:0] tmp_rdata0;
    wire [63:0] tmp_rdata1;
    wire [63:0] tmp_rdata2;
    assign RW0_rdata = {tmp_rdata2[59:40], tmp_rdata2[35:16], tmp_rdata2[11:0],
                        tmp_rdata1[63:56], tmp_rdata1[51:32], tmp_rdata1[27:8], tmp_rdata1[3:0],
                        tmp_rdata0[63:48], tmp_rdata0[43:24], tmp_rdata0[19:0]};



    wire [63:0] tmp_wdata0 = {RW0_wdata[55:40], 4'h0, RW0_wdata[39:20], 4'h0, RW0_wdata[19:0]};
    wire [63:0] tmp_wdata1 = {RW0_wdata[107:100], 4'h0, RW0_wdata[99:80], 4'h0, RW0_wdata[79:60], 4'h0, RW0_wdata[59:56]};
    wire [63:0] tmp_wdata2 = {4'h0, RW0_wdata[159:140], 4'h0, RW0_wdata[139:120], 4'h0, RW0_wdata[119:108]};

    wire [7:0] tmp_wmask0 = {RW0_wmask[2], RW0_wmask[2],
                             RW0_wmask[1], RW0_wmask[1],
                             RW0_wmask[1], RW0_wmask[0],
                             RW0_wmask[0], RW0_wmask[0]};
    wire [7:0] tmp_wmask1 = {RW0_wmask[5], RW0_wmask[4],
                             RW0_wmask[4], RW0_wmask[4],
                             RW0_wmask[3], RW0_wmask[3],
                             RW0_wmask[3], RW0_wmask[2]};
    wire [7:0] tmp_wmask2 = {RW0_wmask[7], RW0_wmask[7],
                             RW0_wmask[7], RW0_wmask[6],
                             RW0_wmask[6], RW0_wmask[6],
                             RW0_wmask[5], RW0_wmask[5]};

    mem_sp_wrap #(
        .MEM_TYPE("block"),
        .MEM_DATAWIDTH(64),
        .MEM_ADDRWIDTH(10)
    ) cc_dir_ext_64x1024_0 (
        .clk    (RW0_clk),
        .reset  (1'b0),
        .en     (RW0_en),
        .we     ({8{RW0_wmode}} & tmp_wmask0),
        .addr   (RW0_addr),
        .din    (tmp_wdata0),
        .dout   (tmp_rdata0)
    );

    mem_sp_wrap #(
        .MEM_TYPE("block"),
        .MEM_DATAWIDTH(64),
        .MEM_ADDRWIDTH(10)
    ) cc_dir_ext_64x1024_1 (
        .clk    (RW0_clk),
        .reset  (1'b0),
        .en     (RW0_en),
        .we     ({8{RW0_wmode}} & tmp_wmask1),
        .addr   (RW0_addr),
        .din    (tmp_wdata1),
        .dout   (tmp_rdata1)
    );

    mem_sp_wrap #(
        .MEM_TYPE("block"),
        .MEM_DATAWIDTH(64),
        .MEM_ADDRWIDTH(10)
    ) cc_dir_ext_64x1024_2 (
        .clk    (RW0_clk),
        .reset  (1'b0),
        .en     (RW0_en),
        .we     ({8{RW0_wmode}} & tmp_wmask2),
        .addr   (RW0_addr),
        .din    (tmp_wdata2),
        .dout   (tmp_rdata2)
    );

endmodule