data/full_repos/permissive/493019833/test/testcase/firrtl/PassOn.lo/sbt/PassOn.lo.v
data/verilator_xmls/18a167af-3bc7-4936-8cfa-6f2d0a4f1b10.xml
module PassOn(
  input         clock,
  input         reset,
  input  [63:0] io_in,
  output [63:0] io_out
);
  assign io_out = io_in;
endmodule
module PassOn(
  input         clock,
  input         reset,
  input  [63:0] io_in,
  output [63:0] io_out
);

  assign io_out = io_in;
endmodule