data/full_repos/permissive/469129654/src/full_adder_assign.v
data/verilator_xmls/e16fb650-0c84-4b43-9309-337472c49f70.xml
module full_adder_assign(a, b, carry_in, sum, carry_out);
    input a, b, carry_in;
    output sum, carry_out;

    assign #(24) {carry_out, sum} = a + b + carry_in;
endmodule
module full_adder_assign(a, b, carry_in, sum, carry_out);

    input a, b, carry_in;
    output sum, carry_out;

    assign #(24) {carry_out, sum} = a + b + carry_in;
endmodule