data/full_repos/permissive/491135068/decoder.v
data/verilator_xmls/947dda0c-9b8e-4843-a98d-bb0393b3c023.xml
module decoder(
    input [4:0] r_in,
    output wire [31:0] r_out
    );
    assign r_out = 32'b1 << r_in;

endmodule
module decoder(
    input [4:0] r_in,
    output wire [31:0] r_out
    );

    assign r_out = 32'b1 << r_in;

endmodule