data/full_repos/permissive/46276558/fpga/nexys4/rtl/clock/clock.v
1: b"%Error: data/full_repos/permissive/46276558/fpga/nexys4/rtl/clock/clock.v:37: Cannot find file containing module: 'clk_wiz_0'\n    clk_wiz_0 clkgen(CLK_IN, CLK_OUT, VGA_CLK_OUT, LOCKED);\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/46276558/fpga/nexys4/rtl/clock,data/full_repos/permissive/46276558/clk_wiz_0\n             data/full_repos/permissive/46276558/fpga/nexys4/rtl/clock,data/full_repos/permissive/46276558/clk_wiz_0.v\n             data/full_repos/permissive/46276558/fpga/nexys4/rtl/clock,data/full_repos/permissive/46276558/clk_wiz_0.sv\n             clk_wiz_0\n             clk_wiz_0.v\n             clk_wiz_0.sv\n             obj_dir/clk_wiz_0\n             obj_dir/clk_wiz_0.v\n             obj_dir/clk_wiz_0.sv\n%Error: Exiting due to 1 error(s)\n"
module RSTGEN(CLK, RST_X_I, RST_X_O);
    input  CLK, RST_X_I;
    output RST_X_O;

    reg [23:0] cnt;
    assign RST_X_O = cnt[23];

    always @(posedge CLK or negedge RST_X_I) begin
        if      (!RST_X_I) cnt <= 0;
        else if (~RST_X_O) cnt <= (cnt + 1'b1);
    end
endmodule
module RSTGEN(CLK, RST_X_I, RST_X_O);

    input  CLK, RST_X_I;
    output RST_X_O;

    reg [23:0] cnt;
    assign RST_X_O = cnt[23];

    always @(posedge CLK or negedge RST_X_I) begin
        if      (!RST_X_I) cnt <= 0;
        else if (~RST_X_O) cnt <= (cnt + 1'b1);
    end
endmodule