data/full_repos/permissive/469509877/rtl/HorizontalObstacles.v
1: b'%Error: data/full_repos/permissive/469509877/rtl/HorizontalObstacles.v:31: Cannot find file containing module: \'H1\'\n    H1 H1 (.Hcount(Hcount), .Vcount(Vcount), .Red({Red1[3:0]}));    \n    ^~\n        ... Looked in:\n             data/full_repos/permissive/469509877/rtl,data/full_repos/permissive/469509877/H1\n             data/full_repos/permissive/469509877/rtl,data/full_repos/permissive/469509877/H1.v\n             data/full_repos/permissive/469509877/rtl,data/full_repos/permissive/469509877/H1.sv\n             H1\n             H1.v\n             H1.sv\n             obj_dir/H1\n             obj_dir/H1.v\n             obj_dir/H1.sv\n%Error: data/full_repos/permissive/469509877/rtl/HorizontalObstacles.v:32: Cannot find file containing module: \'H2\'\n    H2 H2 (.Hcount(Hcount), .Vcount(Vcount), .Red({Red2[3:0]}));\n    ^~\n%Error: data/full_repos/permissive/469509877/rtl/HorizontalObstacles.v:33: Cannot find file containing module: \'H3\'\n    H3 H3 (.Hcount(Hcount), .Vcount(Vcount), .Red({Red3[3:0]}));    \n    ^~\n%Error: data/full_repos/permissive/469509877/rtl/HorizontalObstacles.v:34: Cannot find file containing module: \'H4\'\n    H4 H4 (.Hcount(Hcount), .Vcount(Vcount), .Red({Red4[3:0]}));\n    ^~\n%Error: data/full_repos/permissive/469509877/rtl/HorizontalObstacles.v:35: Cannot find file containing module: \'H5\'\n    H5 H5 (.Hcount(Hcount), .Vcount(Vcount), .Red({Red5[3:0]}));    \n    ^~\n%Error: data/full_repos/permissive/469509877/rtl/HorizontalObstacles.v:36: Cannot find file containing module: \'H6\'\n    H6 H6 (.Hcount(Hcount), .Vcount(Vcount), .Red({Red6[3:0]}));\n    ^~\n%Error: data/full_repos/permissive/469509877/rtl/HorizontalObstacles.v:37: Cannot find file containing module: \'H7\'\n    H7 H7 (.Hcount(Hcount), .Vcount(Vcount), .Red({Red7[3:0]}));    \n    ^~\n%Warning-WIDTH: data/full_repos/permissive/469509877/rtl/HorizontalObstacles.v:40: Operator OR expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                                 : ... In instance HorizontalObstacles\n    assign Red[3] = Red3[3] | Red1[3] | Red2[3] | Red4[3]| Red5[3] | Red6[3:0] | Red7[3:0];\n                            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/469509877/rtl/HorizontalObstacles.v:40: Operator OR expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                 : ... In instance HorizontalObstacles\n    assign Red[3] = Red3[3] | Red1[3] | Red2[3] | Red4[3]| Red5[3] | Red6[3:0] | Red7[3:0];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/469509877/rtl/HorizontalObstacles.v:40: Operator OR expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                 : ... In instance HorizontalObstacles\n    assign Red[3] = Red3[3] | Red1[3] | Red2[3] | Red4[3]| Red5[3] | Red6[3:0] | Red7[3:0];\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/469509877/rtl/HorizontalObstacles.v:40: Operator OR expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                 : ... In instance HorizontalObstacles\n    assign Red[3] = Red3[3] | Red1[3] | Red2[3] | Red4[3]| Red5[3] | Red6[3:0] | Red7[3:0];\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/469509877/rtl/HorizontalObstacles.v:40: Operator OR expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                 : ... In instance HorizontalObstacles\n    assign Red[3] = Red3[3] | Red1[3] | Red2[3] | Red4[3]| Red5[3] | Red6[3:0] | Red7[3:0];\n                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/469509877/rtl/HorizontalObstacles.v:40: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s OR generates 4 bits.\n                                                                                 : ... In instance HorizontalObstacles\n    assign Red[3] = Red3[3] | Red1[3] | Red2[3] | Red4[3]| Red5[3] | Red6[3:0] | Red7[3:0];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/469509877/rtl/HorizontalObstacles.v:41: Operator OR expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                                 : ... In instance HorizontalObstacles\n    assign Red[2] = Red3[2] | Red1[2] | Red2[2] | Red4[2]| Red5[2] | Red6[3:0] | Red7[3:0]; \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/469509877/rtl/HorizontalObstacles.v:41: Operator OR expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                 : ... In instance HorizontalObstacles\n    assign Red[2] = Red3[2] | Red1[2] | Red2[2] | Red4[2]| Red5[2] | Red6[3:0] | Red7[3:0]; \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/469509877/rtl/HorizontalObstacles.v:41: Operator OR expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                 : ... In instance HorizontalObstacles\n    assign Red[2] = Red3[2] | Red1[2] | Red2[2] | Red4[2]| Red5[2] | Red6[3:0] | Red7[3:0]; \n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/469509877/rtl/HorizontalObstacles.v:41: Operator OR expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                 : ... In instance HorizontalObstacles\n    assign Red[2] = Red3[2] | Red1[2] | Red2[2] | Red4[2]| Red5[2] | Red6[3:0] | Red7[3:0]; \n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/469509877/rtl/HorizontalObstacles.v:41: Operator OR expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                 : ... In instance HorizontalObstacles\n    assign Red[2] = Red3[2] | Red1[2] | Red2[2] | Red4[2]| Red5[2] | Red6[3:0] | Red7[3:0]; \n                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/469509877/rtl/HorizontalObstacles.v:41: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s OR generates 4 bits.\n                                                                                 : ... In instance HorizontalObstacles\n    assign Red[2] = Red3[2] | Red1[2] | Red2[2] | Red4[2]| Red5[2] | Red6[3:0] | Red7[3:0]; \n                  ^\n%Warning-WIDTH: data/full_repos/permissive/469509877/rtl/HorizontalObstacles.v:42: Operator OR expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                                 : ... In instance HorizontalObstacles\n    assign Red[1] = Red3[1] | Red1[1] | Red2[1] | Red4[1]| Red5[1] | Red6[3:0] | Red7[3:0]; \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/469509877/rtl/HorizontalObstacles.v:42: Operator OR expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                 : ... In instance HorizontalObstacles\n    assign Red[1] = Red3[1] | Red1[1] | Red2[1] | Red4[1]| Red5[1] | Red6[3:0] | Red7[3:0]; \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/469509877/rtl/HorizontalObstacles.v:42: Operator OR expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                 : ... In instance HorizontalObstacles\n    assign Red[1] = Red3[1] | Red1[1] | Red2[1] | Red4[1]| Red5[1] | Red6[3:0] | Red7[3:0]; \n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/469509877/rtl/HorizontalObstacles.v:42: Operator OR expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                 : ... In instance HorizontalObstacles\n    assign Red[1] = Red3[1] | Red1[1] | Red2[1] | Red4[1]| Red5[1] | Red6[3:0] | Red7[3:0]; \n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/469509877/rtl/HorizontalObstacles.v:42: Operator OR expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                 : ... In instance HorizontalObstacles\n    assign Red[1] = Red3[1] | Red1[1] | Red2[1] | Red4[1]| Red5[1] | Red6[3:0] | Red7[3:0]; \n                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/469509877/rtl/HorizontalObstacles.v:42: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s OR generates 4 bits.\n                                                                                 : ... In instance HorizontalObstacles\n    assign Red[1] = Red3[1] | Red1[1] | Red2[1] | Red4[1]| Red5[1] | Red6[3:0] | Red7[3:0]; \n                  ^\n%Warning-WIDTH: data/full_repos/permissive/469509877/rtl/HorizontalObstacles.v:43: Operator OR expects 4 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                                 : ... In instance HorizontalObstacles\n    assign Red[0] = Red3[0] | Red1[0] | Red2[0] | Red4[0]| Red5[0] | Red6[3:0] | Red7[3:0];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/469509877/rtl/HorizontalObstacles.v:43: Operator OR expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                 : ... In instance HorizontalObstacles\n    assign Red[0] = Red3[0] | Red1[0] | Red2[0] | Red4[0]| Red5[0] | Red6[3:0] | Red7[3:0];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/469509877/rtl/HorizontalObstacles.v:43: Operator OR expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                 : ... In instance HorizontalObstacles\n    assign Red[0] = Red3[0] | Red1[0] | Red2[0] | Red4[0]| Red5[0] | Red6[3:0] | Red7[3:0];\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/469509877/rtl/HorizontalObstacles.v:43: Operator OR expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                 : ... In instance HorizontalObstacles\n    assign Red[0] = Red3[0] | Red1[0] | Red2[0] | Red4[0]| Red5[0] | Red6[3:0] | Red7[3:0];\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/469509877/rtl/HorizontalObstacles.v:43: Operator OR expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                 : ... In instance HorizontalObstacles\n    assign Red[0] = Red3[0] | Red1[0] | Red2[0] | Red4[0]| Red5[0] | Red6[3:0] | Red7[3:0];\n                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/469509877/rtl/HorizontalObstacles.v:43: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s OR generates 4 bits.\n                                                                                 : ... In instance HorizontalObstacles\n    assign Red[0] = Red3[0] | Red1[0] | Red2[0] | Red4[0]| Red5[0] | Red6[3:0] | Red7[3:0];\n                  ^\n%Error: Exiting due to 7 error(s), 24 warning(s)\n'
module HorizontalObstacles(
    input [9:0] Hcount,
    input [9:0] Vcount,
    output[3:0] Red
    );
    
    wire [3:0] Red1, Red2, Red3, Red4, Red5, Red6, Red7;
    
    H1 H1 (.Hcount(Hcount), .Vcount(Vcount), .Red({Red1[3:0]}));    
    H2 H2 (.Hcount(Hcount), .Vcount(Vcount), .Red({Red2[3:0]}));
    H3 H3 (.Hcount(Hcount), .Vcount(Vcount), .Red({Red3[3:0]}));    
    H4 H4 (.Hcount(Hcount), .Vcount(Vcount), .Red({Red4[3:0]}));
    H5 H5 (.Hcount(Hcount), .Vcount(Vcount), .Red({Red5[3:0]}));    
    H6 H6 (.Hcount(Hcount), .Vcount(Vcount), .Red({Red6[3:0]}));
    H7 H7 (.Hcount(Hcount), .Vcount(Vcount), .Red({Red7[3:0]}));    

            
    assign Red[3] = Red3[3] | Red1[3] | Red2[3] | Red4[3]| Red5[3] | Red6[3:0] | Red7[3:0];
    assign Red[2] = Red3[2] | Red1[2] | Red2[2] | Red4[2]| Red5[2] | Red6[3:0] | Red7[3:0]; 
    assign Red[1] = Red3[1] | Red1[1] | Red2[1] | Red4[1]| Red5[1] | Red6[3:0] | Red7[3:0]; 
    assign Red[0] = Red3[0] | Red1[0] | Red2[0] | Red4[0]| Red5[0] | Red6[3:0] | Red7[3:0];
     
endmodule
module HorizontalObstacles(
    input [9:0] Hcount,
    input [9:0] Vcount,
    output[3:0] Red
    );

    
    wire [3:0] Red1, Red2, Red3, Red4, Red5, Red6, Red7;
    
    H1 H1 (.Hcount(Hcount), .Vcount(Vcount), .Red({Red1[3:0]}));    
    H2 H2 (.Hcount(Hcount), .Vcount(Vcount), .Red({Red2[3:0]}));
    H3 H3 (.Hcount(Hcount), .Vcount(Vcount), .Red({Red3[3:0]}));    
    H4 H4 (.Hcount(Hcount), .Vcount(Vcount), .Red({Red4[3:0]}));
    H5 H5 (.Hcount(Hcount), .Vcount(Vcount), .Red({Red5[3:0]}));    
    H6 H6 (.Hcount(Hcount), .Vcount(Vcount), .Red({Red6[3:0]}));
    H7 H7 (.Hcount(Hcount), .Vcount(Vcount), .Red({Red7[3:0]}));    

            
    assign Red[3] = Red3[3] | Red1[3] | Red2[3] | Red4[3]| Red5[3] | Red6[3:0] | Red7[3:0];
    assign Red[2] = Red3[2] | Red1[2] | Red2[2] | Red4[2]| Red5[2] | Red6[3:0] | Red7[3:0]; 
    assign Red[1] = Red3[1] | Red1[1] | Red2[1] | Red4[1]| Red5[1] | Red6[3:0] | Red7[3:0]; 
    assign Red[0] = Red3[0] | Red1[0] | Red2[0] | Red4[0]| Red5[0] | Red6[3:0] | Red7[3:0];
     
endmodule