data/full_repos/permissive/52196097/DSP/Radar_DSP/FPGA/Serial_Ram.v
1: b'%Warning-WIDTH: data/full_repos/permissive/52196097/DSP/Radar_DSP/FPGA/Serial_Ram.v:21: Bit extraction of array[2047:0] requires 11 bit index, not 2048 bits.\n                                                                                      : ... In instance Serial_Ram\n   ram[addr_a] <= data_a;\n      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/52196097/DSP/Radar_DSP/FPGA/Serial_Ram.v:26: Bit extraction of array[2047:0] requires 11 bit index, not 2048 bits.\n                                                                                      : ... In instance Serial_Ram\n   q_a <= ram[addr_a];\n             ^\n%Warning-WIDTH: data/full_repos/permissive/52196097/DSP/Radar_DSP/FPGA/Serial_Ram.v:35: Bit extraction of array[2047:0] requires 11 bit index, not 2048 bits.\n                                                                                      : ... In instance Serial_Ram\n   ram[addr_b] <= data_b;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/52196097/DSP/Radar_DSP/FPGA/Serial_Ram.v:40: Bit extraction of array[2047:0] requires 11 bit index, not 2048 bits.\n                                                                                      : ... In instance Serial_Ram\n   q_b <= ram[addr_b];\n             ^\n%Error: Exiting due to 4 warning(s)\n'
module Serial_Ram
#(parameter DATA_WIDTH=12, parameter ADDR_WIDTH=2048)
(
	input [(DATA_WIDTH-1):0] data_a, data_b,
	input [(ADDR_WIDTH-1):0] addr_a, addr_b,
	input we_a, we_b, clk,
	output reg [(DATA_WIDTH-1):0] q_a, q_b
);


	reg [11:0] ram[2047:0];


	always @ (posedge clk)
	begin
		if (we_a) 
		begin
			ram[addr_a] <= data_a;
			q_a <= data_a;
		end
		else 
		begin
			q_a <= ram[addr_a];
		end 
	end 


	always @ (posedge clk)
	begin
		if (we_b) 
		begin
			ram[addr_b] <= data_b;
			q_b <= data_b;
		end
		else 
		begin
			q_b <= ram[addr_b];
		end 
	end

endmodule
module Serial_Ram
#(parameter DATA_WIDTH=12, parameter ADDR_WIDTH=2048)
(
	input [(DATA_WIDTH-1):0] data_a, data_b,
	input [(ADDR_WIDTH-1):0] addr_a, addr_b,
	input we_a, we_b, clk,
	output reg [(DATA_WIDTH-1):0] q_a, q_b
);



	reg [11:0] ram[2047:0];


	always @ (posedge clk)
	begin
		if (we_a) 
		begin
			ram[addr_a] <= data_a;
			q_a <= data_a;
		end
		else 
		begin
			q_a <= ram[addr_a];
		end 
	end 


	always @ (posedge clk)
	begin
		if (we_b) 
		begin
			ram[addr_b] <= data_b;
			q_b <= data_b;
		end
		else 
		begin
			q_b <= ram[addr_b];
		end 
	end

endmodule