data/full_repos/permissive/42581625/PersonalComputer/ALU.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/42581625/PersonalComputer/ALU.v:72: Signal definition not found, creating implicitly: \'CF\'\n                                                                                : ... Suggested alternative: \'OF\'\n  {32{Func[5:0]==6\'b101011}} & {31\'h0,~CF} | \n                                       ^~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/42581625/PersonalComputer/ALU.v:36: Cannot find file containing module: \'AdderAndSubber64\'\nAdderAndSubber64 adder64 (\n^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/42581625/PersonalComputer,data/full_repos/permissive/42581625/AdderAndSubber64\n             data/full_repos/permissive/42581625/PersonalComputer,data/full_repos/permissive/42581625/AdderAndSubber64.v\n             data/full_repos/permissive/42581625/PersonalComputer,data/full_repos/permissive/42581625/AdderAndSubber64.sv\n             AdderAndSubber64\n             AdderAndSubber64.v\n             AdderAndSubber64.sv\n             obj_dir/AdderAndSubber64\n             obj_dir/AdderAndSubber64.v\n             obj_dir/AdderAndSubber64.sv\n%Error: data/full_repos/permissive/42581625/PersonalComputer/ALU.v:50: Cannot find file containing module: \'Rotator\'\nRotator rotator (\n^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/42581625/PersonalComputer/ALU.v:63: Operator AND expects 64 bits on the LHS, but LHS\'s REPLICATE generates 32 bits.\n                                                                             : ... In instance ALU\n {32{ALUop[1]==0}} & AddOrSubResult |\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/42581625/PersonalComputer/ALU.v:64: Operator AND expects 64 bits on the LHS, but LHS\'s REPLICATE generates 32 bits.\n                                                                             : ... In instance ALU\n {32{ALUop[1]==1}} & (\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/42581625/PersonalComputer/ALU.v:65: Operator AND expects 64 bits on the LHS, but LHS\'s REPLICATE generates 32 bits.\n                                                                             : ... In instance ALU\n  {32{Func[5:3]==3\'b000}} & RotatorOut |  \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/42581625/PersonalComputer/ALU.v:65: Operator AND expects 64 bits on the RHS, but RHS\'s VARREF \'RotatorOut\' generates 32 bits.\n                                                                             : ... In instance ALU\n  {32{Func[5:3]==3\'b000}} & RotatorOut |  \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/42581625/PersonalComputer/ALU.v:66: Operator AND expects 64 bits on the LHS, but LHS\'s REPLICATE generates 32 bits.\n                                                                             : ... In instance ALU\n  {32{Func[5:2]==4\'b1000}} & AddOrSubResult |  \n                           ^\n%Warning-WIDTH: data/full_repos/permissive/42581625/PersonalComputer/ALU.v:67: Operator AND expects 64 bits on the LHS, but LHS\'s REPLICATE generates 32 bits.\n                                                                             : ... In instance ALU\n  {32{Func[5:0]==6\'b100100}} & (A & B) | \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/42581625/PersonalComputer/ALU.v:67: Operator AND expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                                             : ... In instance ALU\n  {32{Func[5:0]==6\'b100100}} & (A & B) | \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/42581625/PersonalComputer/ALU.v:67: Operator AND expects 64 bits on the RHS, but RHS\'s VARREF \'B\' generates 32 bits.\n                                                                             : ... In instance ALU\n  {32{Func[5:0]==6\'b100100}} & (A & B) | \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/42581625/PersonalComputer/ALU.v:68: Operator AND expects 64 bits on the LHS, but LHS\'s REPLICATE generates 32 bits.\n                                                                             : ... In instance ALU\n  {32{Func[5:0]==6\'b100101}} & (A | B) | \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/42581625/PersonalComputer/ALU.v:68: Operator OR expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                                             : ... In instance ALU\n  {32{Func[5:0]==6\'b100101}} & (A | B) | \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/42581625/PersonalComputer/ALU.v:68: Operator OR expects 64 bits on the RHS, but RHS\'s VARREF \'B\' generates 32 bits.\n                                                                             : ... In instance ALU\n  {32{Func[5:0]==6\'b100101}} & (A | B) | \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/42581625/PersonalComputer/ALU.v:69: Operator AND expects 64 bits on the LHS, but LHS\'s REPLICATE generates 32 bits.\n                                                                             : ... In instance ALU\n  {32{Func[5:0]==6\'b100110}} & (A ^ B) | \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/42581625/PersonalComputer/ALU.v:69: Operator XOR expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                                             : ... In instance ALU\n  {32{Func[5:0]==6\'b100110}} & (A ^ B) | \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/42581625/PersonalComputer/ALU.v:69: Operator XOR expects 64 bits on the RHS, but RHS\'s VARREF \'B\' generates 32 bits.\n                                                                             : ... In instance ALU\n  {32{Func[5:0]==6\'b100110}} & (A ^ B) | \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/42581625/PersonalComputer/ALU.v:70: Operator AND expects 64 bits on the LHS, but LHS\'s REPLICATE generates 32 bits.\n                                                                             : ... In instance ALU\n  {32{Func[5:0]==6\'b100111}} & ~(A | B) | \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/42581625/PersonalComputer/ALU.v:70: Operator OR expects 64 bits on the LHS, but LHS\'s VARREF \'A\' generates 32 bits.\n                                                                             : ... In instance ALU\n  {32{Func[5:0]==6\'b100111}} & ~(A | B) | \n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/42581625/PersonalComputer/ALU.v:70: Operator OR expects 64 bits on the RHS, but RHS\'s VARREF \'B\' generates 32 bits.\n                                                                             : ... In instance ALU\n  {32{Func[5:0]==6\'b100111}} & ~(A | B) | \n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/42581625/PersonalComputer/ALU.v:71: Operator AND expects 64 bits on the LHS, but LHS\'s REPLICATE generates 32 bits.\n                                                                             : ... In instance ALU\n  {32{Func[5:0]==6\'b101010}} & {31\'h0,SF^OF} | \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/42581625/PersonalComputer/ALU.v:71: Operator AND expects 64 bits on the RHS, but RHS\'s REPLICATE generates 32 bits.\n                                                                             : ... In instance ALU\n  {32{Func[5:0]==6\'b101010}} & {31\'h0,SF^OF} | \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/42581625/PersonalComputer/ALU.v:72: Operator AND expects 64 bits on the LHS, but LHS\'s REPLICATE generates 32 bits.\n                                                                             : ... In instance ALU\n  {32{Func[5:0]==6\'b101011}} & {31\'h0,~CF} | \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/42581625/PersonalComputer/ALU.v:72: Operator AND expects 64 bits on the RHS, but RHS\'s REPLICATE generates 32 bits.\n                                                                             : ... In instance ALU\n  {32{Func[5:0]==6\'b101011}} & {31\'h0,~CF} | \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/42581625/PersonalComputer/ALU.v:73: Operator AND expects 64 bits on the LHS, but LHS\'s REPLICATE generates 32 bits.\n                                                                             : ... In instance ALU\n  {32{Func[5:0]==6\'b111111}} & mulResult\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/42581625/PersonalComputer/ALU.v:73: Operator AND expects 64 bits on the RHS, but RHS\'s VARREF \'mulResult\' generates 32 bits.\n                                                                             : ... In instance ALU\n  {32{Func[5:0]==6\'b111111}} & mulResult\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/42581625/PersonalComputer/ALU.v:62: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s OR generates 64 bits.\n                                                                             : ... In instance ALU\nassign result = \n              ^\n%Error: Exiting due to 2 error(s), 25 warning(s)\n'
module ALU(
input[31:0] A,
input[31:0] B,
input[1:0] ALUop,
input[5:0] Func,
output[31:0] result,
output ZF
    );


wire AddOrSub,SF,OF;
wire[63:0] AddOrSubResult;
assign AddOrSub = 
	(ALUop[1]==0) & ALUop[0] |
	(ALUop[1]==1) & Func[1];
AdderAndSubber64 adder64 (
    .A({ {32{A[31]}}, A}), 
    .B({ {32{B[31]}}, B}), 
    .mode(AddOrSub), 
    .result(AddOrSubResult), 
    .OF(OF), 
    .SF(SF), 
    .ZF(ZF), 
    .CF(CF)
    );
	 

wire[31:0] RotatorOut;
Rotator rotator (
    .RotatorIn(B), 
    .RotatorBitNum(A[4:0]), 
    .RotatorOp(Func[1:0]), 
    .RotatorOut(RotatorOut)
    );
	 

wire[31:0] mulResult;
assign mulResult = A*B;


assign result = 
	{32{ALUop[1]==0}} & AddOrSubResult |
	{32{ALUop[1]==1}} & (
		{32{Func[5:3]==3'b000}} & RotatorOut |
		{32{Func[5:2]==4'b1000}} & AddOrSubResult |
		{32{Func[5:0]==6'b100100}} & (A & B) |
		{32{Func[5:0]==6'b100101}} & (A | B) |
		{32{Func[5:0]==6'b100110}} & (A ^ B) |
		{32{Func[5:0]==6'b100111}} & ~(A | B) |
		{32{Func[5:0]==6'b101010}} & {31'h0,SF^OF} |
		{32{Func[5:0]==6'b101011}} & {31'h0,~CF} |
		{32{Func[5:0]==6'b111111}} & mulResult
	);
	
endmodule
module ALU(
input[31:0] A,
input[31:0] B,
input[1:0] ALUop,
input[5:0] Func,
output[31:0] result,
output ZF
    );



wire AddOrSub,SF,OF;
wire[63:0] AddOrSubResult;
assign AddOrSub = 
	(ALUop[1]==0) & ALUop[0] |
	(ALUop[1]==1) & Func[1];
AdderAndSubber64 adder64 (
    .A({ {32{A[31]}}, A}), 
    .B({ {32{B[31]}}, B}), 
    .mode(AddOrSub), 
    .result(AddOrSubResult), 
    .OF(OF), 
    .SF(SF), 
    .ZF(ZF), 
    .CF(CF)
    );
	 

wire[31:0] RotatorOut;
Rotator rotator (
    .RotatorIn(B), 
    .RotatorBitNum(A[4:0]), 
    .RotatorOp(Func[1:0]), 
    .RotatorOut(RotatorOut)
    );
	 

wire[31:0] mulResult;
assign mulResult = A*B;


assign result = 
	{32{ALUop[1]==0}} & AddOrSubResult |
	{32{ALUop[1]==1}} & (
		{32{Func[5:3]==3'b000}} & RotatorOut |
		{32{Func[5:2]==4'b1000}} & AddOrSubResult |
		{32{Func[5:0]==6'b100100}} & (A & B) |
		{32{Func[5:0]==6'b100101}} & (A | B) |
		{32{Func[5:0]==6'b100110}} & (A ^ B) |
		{32{Func[5:0]==6'b100111}} & ~(A | B) |
		{32{Func[5:0]==6'b101010}} & {31'h0,SF^OF} |
		{32{Func[5:0]==6'b101011}} & {31'h0,~CF} |
		{32{Func[5:0]==6'b111111}} & mulResult
	);
	
endmodule