data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/IF_ID_reg.v
data/verilator_xmls/e19e5189-79ba-4179-8146-d6ded11b2e58.xml
module IF_ID_reg(input clk, reset, write,
                 input [31:0] pc_in, instruction_in,
                 output reg [31:0] pc_out,  instruction_out);
    always @(posedge clk) begin
        if (reset) begin
            instruction_out <= 0;
            pc_out <= 0;
        end
        else if (write) begin
            instruction_out <= instruction_in;
            pc_out <= pc_in;
        end
    end
endmodule
module IF_ID_reg(input clk, reset, write,
                 input [31:0] pc_in, instruction_in,
                 output reg [31:0] pc_out,  instruction_out);

    always @(posedge clk) begin
        if (reset) begin
            instruction_out <= 0;
            pc_out <= 0;
        end
        else if (write) begin
            instruction_out <= instruction_in;
            pc_out <= pc_in;
        end
    end
endmodule