data/full_repos/permissive/463223850/sim/tb/tb_z80.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/463223850/sim/tb/tb_z80.v:13: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/463223850/sim/tb/tb_z80.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/463223850/sim/tb/tb_z80.v:41: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Error: data/full_repos/permissive/463223850/sim/tb/tb_z80.v:22: Cannot find file containing module: \'cpu_z80\'\ncpu_z80 uut(.DI(DI), .DO(DO),\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463223850/sim/tb,data/full_repos/permissive/463223850/cpu_z80\n             data/full_repos/permissive/463223850/sim/tb,data/full_repos/permissive/463223850/cpu_z80.v\n             data/full_repos/permissive/463223850/sim/tb,data/full_repos/permissive/463223850/cpu_z80.sv\n             cpu_z80\n             cpu_z80.v\n             cpu_z80.sv\n             obj_dir/cpu_z80\n             obj_dir/cpu_z80.v\n             obj_dir/cpu_z80.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_z80();
	reg [7:0] DI;
	reg CLK, RESET, INT, NMI, WAIT;
        reg [7:0] mem1 [0:7];
	wire [7:0] DO;
	wire [15:0] ADDR;
	wire WR, MREQ, IORQ, HALT, M1;
	integer count;
	
	always begin
		CLK = 0;
		#5;
		CLK = 1;
		#5;
		DI = mem1[count];
		count = count + 1;
		if(count == 7) count = 0;
		
	end

cpu_z80 uut(.DI(DI), .DO(DO),
.ADDR(ADDR), .WR(WR), .MREQ(MREQ), .IORQ(IORQ),
.HALT(HALT), .M1(M1), .CLK(CLK), .RESET(RESET),
.INT(INT), .NMI(NMI), .WAIT(WAIT) );

initial begin

        mem1[0] = 8'h3e;
	mem1[1] = 8'h0f;
	mem1[2] = 8'h06;
	mem1[3] = 8'h07;
	mem1[4] = 8'h80;
	mem1[5] = 8'hd3;
	mem1[6] = 8'h76;

	count = 0;
	
	RESET = 1; NMI = 0; INT = 0;
	WAIT = 0;
	#1
	RESET = 0;

	end
endmodule
module tb_z80();

	reg [7:0] DI;
	reg CLK, RESET, INT, NMI, WAIT;
        reg [7:0] mem1 [0:7];
	wire [7:0] DO;
	wire [15:0] ADDR;
	wire WR, MREQ, IORQ, HALT, M1;
	integer count;
	
	always begin
		CLK = 0;
		#5;
		CLK = 1;
		#5;
		DI = mem1[count];
		count = count + 1;
		if(count == 7) count = 0;
		
	end

cpu_z80 uut(.DI(DI), .DO(DO),
.ADDR(ADDR), .WR(WR), .MREQ(MREQ), .IORQ(IORQ),
.HALT(HALT), .M1(M1), .CLK(CLK), .RESET(RESET),
.INT(INT), .NMI(NMI), .WAIT(WAIT) );

initial begin

        mem1[0] = 8'h3e;
	mem1[1] = 8'h0f;
	mem1[2] = 8'h06;
	mem1[3] = 8'h07;
	mem1[4] = 8'h80;
	mem1[5] = 8'hd3;
	mem1[6] = 8'h76;

	count = 0;
	
	RESET = 1; NMI = 0; INT = 0;
	WAIT = 0;
	#1
	RESET = 0;

	end
endmodule