data/full_repos/permissive/495988601/random.sv
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/495988601/random.sv:14: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'randnum_b'\n                                                                     : ... In instance random\n   randnum_b <= 3'b111;\n   ^~~~~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/495988601/random.sv:16: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'randnum_b'\n                                                                     : ... In instance random\n   randnum_b <= 3'b111;\n   ^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module random (input Clk,
				input frame_clk,
				input Reset,
				output [2:0] randnum_b
	);
	
	logic frame_clk_delayed, frame_clk_rising_edge;
	always_ff @ (posedge Clk)
	begin
		frame_clk_delayed <= frame_clk;
		frame_clk_rising_edge <= (frame_clk == 1'b1) && (frame_clk_delayed == 1'b0);
	
		if (Reset)
			randnum_b <= 3'b111;
		else if (randnum_b == 3'b000)
			randnum_b	<= 3'b111;
		else if (frame_clk_rising_edge)
		begin
			randnum_b[2] <= randnum_b[1];
			randnum_b[1] <= randnum_b[0]^randnum_b[2];
			randnum_b[0] <= randnum_b[2];
		end
	end	
	
endmodule
module random (input Clk,
				input frame_clk,
				input Reset,
				output [2:0] randnum_b
	);

	
	logic frame_clk_delayed, frame_clk_rising_edge;
	always_ff @ (posedge Clk)
	begin
		frame_clk_delayed <= frame_clk;
		frame_clk_rising_edge <= (frame_clk == 1'b1) && (frame_clk_delayed == 1'b0);
	
		if (Reset)
			randnum_b <= 3'b111;
		else if (randnum_b == 3'b000)
			randnum_b	<= 3'b111;
		else if (frame_clk_rising_edge)
		begin
			randnum_b[2] <= randnum_b[1];
			randnum_b[1] <= randnum_b[0]^randnum_b[2];
			randnum_b[0] <= randnum_b[2];
		end
	end	
	
endmodule