data/full_repos/permissive/420726213/verilog/dv/tb/io_filter_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/420726213/verilog/dv/tb/io_filter_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/420726213/verilog/dv/tb/io_filter_tb.v:71: Unsupported or unknown PLI call: $monitor\n   $monitor("time %4d pin_data_in %4b pin_data_out %4b port_active_in %6b port_active_out %6b port_data_in %24b port_data_out %24b",\n   ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/420726213/verilog/dv/tb/io_filter_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n   #40\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/420726213/verilog/dv/tb/io_filter_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n   #40\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/420726213/verilog/dv/tb/io_filter_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n   #40\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/420726213/verilog/dv/tb/io_filter_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n   #10 port_active_out <= 6\'b0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/420726213/verilog/dv/tb/io_filter_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n   #30\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/420726213/verilog/dv/tb/io_filter_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n   #10 port_active_out <= 6\'b0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/420726213/verilog/dv/tb/io_filter_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n   #30\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/420726213/verilog/dv/tb/io_filter_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n   #10 port_active_out <= 6\'b0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/420726213/verilog/dv/tb/io_filter_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n   #30\n   ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module io_filter_tb();

parameter IO_PINS = 4;
parameter DATA_WIDTH = 8;

reg clk;
reg rst_n;
reg [IO_PINS-1:0] pin_dir;
wire [IO_PINS-1:0] pin_data_in_raw;
wire [IO_PINS-1:0] pin_data_out_raw;
wire [IO_PINS+2-1:0] port_active_in_raw;
wire [IO_PINS+2-1:0] port_active_out_raw;
wire [(IO_PINS+2)*DATA_WIDTH-1:0] port_data_in_raw;
wire [(IO_PINS+2)*DATA_WIDTH-1:0] port_data_out_raw;

io_filter #(
   .IO_PINS(IO_PINS),
   .DATA_WIDTH(DATA_WIDTH)
) io_filter_dut (
   .clk(clk),
   .rst_n(rst_n),
   .pin_dir(pin_dir),
   .pin_data_in(pin_data_in_raw),
   .pin_data_out(pin_data_out_raw),
   .port_active_in(port_active_in_raw),
   .port_active_out(port_active_out_raw),
   .port_data_in(port_data_in_raw),
   .port_data_out(port_data_out_raw)
);






wire [IO_PINS-1:0] pin_data_out;
reg [IO_PINS+2-1:0] port_active_out;
reg [(IO_PINS+2)*DATA_WIDTH-1:0] port_data_out;

reg [IO_PINS-1:0] pin_data_in;
wire [IO_PINS+2-1:0] port_active_in;
wire [(IO_PINS+2)*DATA_WIDTH-1:0] port_data_in;

generate genvar pin;
for (pin=0; pin<IO_PINS; pin=pin+1) begin:g_pin

   assign port_active_out_raw[pin] = port_active_out[pin];
   assign port_data_out_raw[pin*DATA_WIDTH +: DATA_WIDTH] = port_data_out[pin*DATA_WIDTH +: DATA_WIDTH];
   assign pin_data_out = pin_data_out_raw;

   assign pin_data_in_raw[pin] = pin_data_in[pin];
   assign port_active_in[pin] = port_active_in_raw[pin];
   assign port_data_in[pin*DATA_WIDTH +: DATA_WIDTH] = port_data_in_raw[pin*DATA_WIDTH +: DATA_WIDTH];
end
endgenerate

assign port_active_out_raw[IO_PINS +: 2] = {1'b0, port_active_out[IO_PINS]};
assign port_data_out_raw[IO_PINS*DATA_WIDTH +: 2*DATA_WIDTH] = {{(DATA_WIDTH){1'b0}}, port_data_out[IO_PINS*DATA_WIDTH +: DATA_WIDTH]};

assign port_active_in[IO_PINS +: 2] = {port_active_in_raw[IO_PINS+1], 1'b0};
assign port_data_in[IO_PINS*DATA_WIDTH +: 2*DATA_WIDTH] = {port_data_in_raw[(IO_PINS+1)*DATA_WIDTH +: DATA_WIDTH], {(DATA_WIDTH){1'b0}}};

always #5 clk = ~clk;

initial begin
   $monitor("time %4d pin_data_in %4b pin_data_out %4b port_active_in %6b port_active_out %6b port_data_in %24b port_data_out %24b",
               $time, pin_data_in_raw, pin_data_out_raw, port_active_in_raw, port_active_out_raw, port_data_in_raw, port_data_out_raw);
   clk <= 0;
   rst_n <= 0;
   #40
   rst_n <= 1;
   pin_dir <= 4'b0101;
   port_active_out <= 6'b0;
   port_data_out <= 48'b0;
   pin_data_in <= 4'b0;
   #40
   pin_data_in <= 4'b1000;
   #40
   port_active_out <= 6'b000100;
   port_data_out <= 48'b00000000_00000000_00000000_11111111_00000000_11111111;
   #10 port_active_out <= 6'b0;
   #30
   port_active_out <= 6'b010000;
   port_data_out <= 48'b00000000_00000001_00000000_00000000_00000000_00000000;
   #10 port_active_out <= 6'b0;
   #30
   port_active_out <= 6'b010001;
   port_data_out <= 48'b00000000_00000011_00000000_00000000_00000000_00000000;
   #10 port_active_out <= 6'b0;
   #30
   $stop;
end

endmodule
module io_filter_tb();


parameter IO_PINS = 4;
parameter DATA_WIDTH = 8;

reg clk;
reg rst_n;
reg [IO_PINS-1:0] pin_dir;
wire [IO_PINS-1:0] pin_data_in_raw;
wire [IO_PINS-1:0] pin_data_out_raw;
wire [IO_PINS+2-1:0] port_active_in_raw;
wire [IO_PINS+2-1:0] port_active_out_raw;
wire [(IO_PINS+2)*DATA_WIDTH-1:0] port_data_in_raw;
wire [(IO_PINS+2)*DATA_WIDTH-1:0] port_data_out_raw;

io_filter #(
   .IO_PINS(IO_PINS),
   .DATA_WIDTH(DATA_WIDTH)
) io_filter_dut (
   .clk(clk),
   .rst_n(rst_n),
   .pin_dir(pin_dir),
   .pin_data_in(pin_data_in_raw),
   .pin_data_out(pin_data_out_raw),
   .port_active_in(port_active_in_raw),
   .port_active_out(port_active_out_raw),
   .port_data_in(port_data_in_raw),
   .port_data_out(port_data_out_raw)
);






wire [IO_PINS-1:0] pin_data_out;
reg [IO_PINS+2-1:0] port_active_out;
reg [(IO_PINS+2)*DATA_WIDTH-1:0] port_data_out;

reg [IO_PINS-1:0] pin_data_in;
wire [IO_PINS+2-1:0] port_active_in;
wire [(IO_PINS+2)*DATA_WIDTH-1:0] port_data_in;

generate genvar pin;
for (pin=0; pin<IO_PINS; pin=pin+1) begin:g_pin

   assign port_active_out_raw[pin] = port_active_out[pin];
   assign port_data_out_raw[pin*DATA_WIDTH +: DATA_WIDTH] = port_data_out[pin*DATA_WIDTH +: DATA_WIDTH];
   assign pin_data_out = pin_data_out_raw;

   assign pin_data_in_raw[pin] = pin_data_in[pin];
   assign port_active_in[pin] = port_active_in_raw[pin];
   assign port_data_in[pin*DATA_WIDTH +: DATA_WIDTH] = port_data_in_raw[pin*DATA_WIDTH +: DATA_WIDTH];
end
endgenerate

assign port_active_out_raw[IO_PINS +: 2] = {1'b0, port_active_out[IO_PINS]};
assign port_data_out_raw[IO_PINS*DATA_WIDTH +: 2*DATA_WIDTH] = {{(DATA_WIDTH){1'b0}}, port_data_out[IO_PINS*DATA_WIDTH +: DATA_WIDTH]};

assign port_active_in[IO_PINS +: 2] = {port_active_in_raw[IO_PINS+1], 1'b0};
assign port_data_in[IO_PINS*DATA_WIDTH +: 2*DATA_WIDTH] = {port_data_in_raw[(IO_PINS+1)*DATA_WIDTH +: DATA_WIDTH], {(DATA_WIDTH){1'b0}}};

always #5 clk = ~clk;

initial begin
   $monitor("time %4d pin_data_in %4b pin_data_out %4b port_active_in %6b port_active_out %6b port_data_in %24b port_data_out %24b",
               $time, pin_data_in_raw, pin_data_out_raw, port_active_in_raw, port_active_out_raw, port_data_in_raw, port_data_out_raw);
   clk <= 0;
   rst_n <= 0;
   #40
   rst_n <= 1;
   pin_dir <= 4'b0101;
   port_active_out <= 6'b0;
   port_data_out <= 48'b0;
   pin_data_in <= 4'b0;
   #40
   pin_data_in <= 4'b1000;
   #40
   port_active_out <= 6'b000100;
   port_data_out <= 48'b00000000_00000000_00000000_11111111_00000000_11111111;
   #10 port_active_out <= 6'b0;
   #30
   port_active_out <= 6'b010000;
   port_data_out <= 48'b00000000_00000001_00000000_00000000_00000000_00000000;
   #10 port_active_out <= 6'b0;
   #30
   port_active_out <= 6'b010001;
   port_data_out <= 48'b00000000_00000011_00000000_00000000_00000000_00000000;
   #10 port_active_out <= 6'b0;
   #30
   $stop;
end

endmodule