data/full_repos/permissive/490492655/M1.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/490492655/M1.v:6: Little bit endian vector: MSB < LSB of bit range: 0:6\n output reg [0:6] out,  \n            ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module M1 (
	output reg [0:6] out,
	input rst, clk,
	input [1:0] sel,
	input [2:0] in1, in2
);

	reg [3:0] a;
	

	always @ (in1, in2)
	begin
		case(sel)
			0: a = {1'b0, in2};
			1: a = in1 + in2;
			2: a = {1'b0, in1};
			default: a = 4'bxxxx;
		endcase
	end
	

	always @ (posedge rst, posedge clk)
	begin
		if (rst == 1)
			out <= 0;
		else
			out <= out + {3'b000, a};
	end
	
endmodule
module M1 (
	output reg [0:6] out,
	input rst, clk,
	input [1:0] sel,
	input [2:0] in1, in2
);


	reg [3:0] a;
	

	always @ (in1, in2)
	begin
		case(sel)
			0: a = {1'b0, in2};
			1: a = in1 + in2;
			2: a = {1'b0, in1};
			default: a = 4'bxxxx;
		endcase
	end
	

	always @ (posedge rst, posedge clk)
	begin
		if (rst == 1)
			out <= 0;
		else
			out <= out + {3'b000, a};
	end
	
endmodule