data/full_repos/permissive/408590255/WorkPackage6/tb_simple_CPU.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/408590255/WorkPackage6/tb_simple_CPU.v:19: Unsupported: Ignoring delay on this delayed statement.\n        repeat(3) #1 clk=!clk;\n                  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/408590255/WorkPackage6/tb_simple_CPU.v:21: Unsupported: Ignoring delay on this delayed statement.\n        repeat(2) #1 clk=!clk;\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/408590255/WorkPackage6/tb_simple_CPU.v:32: Unsupported: Ignoring delay on this delayed statement.\n        repeat(8) #1 clk=!clk;  \n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/408590255/WorkPackage6/tb_simple_CPU.v:37: Unsupported: Ignoring delay on this delayed statement.\n        repeat(6) #1 clk=!clk; \n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/408590255/WorkPackage6/tb_simple_CPU.v:42: Unsupported: Ignoring delay on this delayed statement.\n        repeat(6) #1 clk=!clk;\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/408590255/WorkPackage6/tb_simple_CPU.v:47: Unsupported: Ignoring delay on this delayed statement.\n        repeat(6) #1 clk=!clk;\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/408590255/WorkPackage6/tb_simple_CPU.v:52: Unsupported: Ignoring delay on this delayed statement.\n        repeat(6) #1 clk=!clk;\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/408590255/WorkPackage6/tb_simple_CPU.v:57: Unsupported: Ignoring delay on this delayed statement.\n        repeat(7) #1 clk=!clk;\n                  ^\n%Error: data/full_repos/permissive/408590255/WorkPackage6/tb_simple_CPU.v:13: Cannot find file containing module: \'simple_cpu\'\n    simple_cpu  #(DATA_WIDTH,ADDR_BITS,INSTR_WIDTH) SCPU_DUT(clk, rst, instruction);\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/408590255/WorkPackage6,data/full_repos/permissive/408590255/simple_cpu\n             data/full_repos/permissive/408590255/WorkPackage6,data/full_repos/permissive/408590255/simple_cpu.v\n             data/full_repos/permissive/408590255/WorkPackage6,data/full_repos/permissive/408590255/simple_cpu.sv\n             simple_cpu\n             simple_cpu.v\n             simple_cpu.sv\n             obj_dir/simple_cpu\n             obj_dir/simple_cpu.v\n             obj_dir/simple_cpu.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_simple_CPU;
       
    parameter DATA_WIDTH = 8;
    parameter ADDR_BITS = 5;
    parameter INSTR_WIDTH =20;
   
    reg clk, rst;
    reg [INSTR_WIDTH-1:0] instruction;

    
    simple_cpu  #(DATA_WIDTH,ADDR_BITS,INSTR_WIDTH) SCPU_DUT(clk, rst, instruction);
    
    initial begin
        clk = 1'b1;
        rst = 1'b1;
        instruction = 20'd0;
        repeat(3) #1 clk=!clk;
        rst = 1'b0;
        repeat(2) #1 clk=!clk;
                
                

            


        instruction = 20'b01000111000000000000;
        repeat(8) #1 clk=!clk;
        


        instruction = 20'b01010011000000000000;
        repeat(6) #1 clk=!clk; 
                


        instruction = 20'b01110010000000000001;
        repeat(6) #1 clk=!clk;
        


        instruction = 20'b11011000000011110000;
        repeat(6) #1 clk=!clk;
        


        instruction = 20'b11001100000101100000;
        repeat(6) #1 clk=!clk;



        instruction = 20'b10111000000011110000;
        repeat(7) #1 clk=!clk;
        
        
    end
    
    
endmodule
module tb_simple_CPU;

       
    parameter DATA_WIDTH = 8;
    parameter ADDR_BITS = 5;
    parameter INSTR_WIDTH =20;
   
    reg clk, rst;
    reg [INSTR_WIDTH-1:0] instruction;

    
    simple_cpu  #(DATA_WIDTH,ADDR_BITS,INSTR_WIDTH) SCPU_DUT(clk, rst, instruction);
    
    initial begin
        clk = 1'b1;
        rst = 1'b1;
        instruction = 20'd0;
        repeat(3) #1 clk=!clk;
        rst = 1'b0;
        repeat(2) #1 clk=!clk;
                
                

            


        instruction = 20'b01000111000000000000;
        repeat(8) #1 clk=!clk;
        


        instruction = 20'b01010011000000000000;
        repeat(6) #1 clk=!clk; 
                


        instruction = 20'b01110010000000000001;
        repeat(6) #1 clk=!clk;
        


        instruction = 20'b11011000000011110000;
        repeat(6) #1 clk=!clk;
        


        instruction = 20'b11001100000101100000;
        repeat(6) #1 clk=!clk;



        instruction = 20'b10111000000011110000;
        repeat(7) #1 clk=!clk;
        
        
    end
    
    
endmodule