data/full_repos/permissive/423547971/College Coursework/Digital Design II Final Project/sensor_mode_TB.v
1: b'%Error: Cannot find file containing module: Coursework/Digital\n        ... Looked in:\n             data/full_repos/permissive/423547971/College/Coursework/Digital\n             data/full_repos/permissive/423547971/College/Coursework/Digital.v\n             data/full_repos/permissive/423547971/College/Coursework/Digital.sv\n             Coursework/Digital\n             Coursework/Digital.v\n             Coursework/Digital.sv\n             obj_dir/Coursework/Digital\n             obj_dir/Coursework/Digital.v\n             obj_dir/Coursework/Digital.sv\n%Error: Cannot find file containing module: Design\n%Error: Cannot find file containing module: II\n%Error: Cannot find file containing module: Final\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/College\n%Error: Cannot find file containing module: Project/sensor_mode_TB.v\n%Error: Exiting due to 7 error(s)\n'
module sensor_mode_TB;

reg CLOCK;
reg RESET;
reg enable_sensor_mode;
reg SET_srl;

wire D0, D1, D2, D3, D4, counter3_RST;


sensor_mode SM(
	.CLOCK(CLOCK),
	.RESET(RESET),
	.SET_srl(SET_srl),
	.enable_sensor_mode(enable_sensor_mode),
	
	.D0(D0),
	.D1(D1),
	.D2(D2),
	.D3(D3),
	.D4(D4),
	.counter3_RST(counter3_RST)
);


always
  #10 CLOCK = ~CLOCK ;
  

initial
begin
  $dumpfile("sensor_mode_TB.vcd") ;
  $dumpvars(0, sensor_mode_TB) ;
end


initial
begin
		enable_sensor_mode = 0 ;
		SET_srl = 0 ;
		CLOCK  = 0 ;
		RESET  = 1 ;
  #25 	RESET  = 0 ;
  #100  enable_sensor_mode = 1 ;
  #100  SET_srl = 1 ;
  #20  SET_srl = 0 ;


  #5000 $finish ; 
end
 
endmodule
module sensor_mode_TB;


reg CLOCK;
reg RESET;
reg enable_sensor_mode;
reg SET_srl;

wire D0, D1, D2, D3, D4, counter3_RST;


sensor_mode SM(
	.CLOCK(CLOCK),
	.RESET(RESET),
	.SET_srl(SET_srl),
	.enable_sensor_mode(enable_sensor_mode),
	
	.D0(D0),
	.D1(D1),
	.D2(D2),
	.D3(D3),
	.D4(D4),
	.counter3_RST(counter3_RST)
);


always
  #10 CLOCK = ~CLOCK ;
  

initial
begin
  $dumpfile("sensor_mode_TB.vcd") ;
  $dumpvars(0, sensor_mode_TB) ;
end


initial
begin
		enable_sensor_mode = 0 ;
		SET_srl = 0 ;
		CLOCK  = 0 ;
		RESET  = 1 ;
  #25 	RESET  = 0 ;
  #100  enable_sensor_mode = 1 ;
  #100  SET_srl = 1 ;
  #20  SET_srl = 0 ;


  #5000 $finish ; 
end
 
endmodule