data/full_repos/permissive/500711628/garbage/buffer/buffer.v
1: b'%Warning-WIDTH: data/full_repos/permissive/500711628/garbage/buffer/buffer.v:10: Operator ASSIGNDLY expects 100 bits on the Assign RHS, but Assign RHS\'s VARREF \'idata\' generates 1 bits.\n                                                                               : ... In instance buffer\n  data <= idata;\n       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/500711628/garbage/buffer/buffer.v:11: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'data\' generates 100 bits.\n                                                                               : ... In instance buffer\n  odata <= data;\n        ^~\n%Error: Exiting due to 2 warning(s)\n'
module buffer(
	input clock,
	input idata,
	output reg odata
);

	reg [99:0] data;

	always@(posedge clock) begin 
		data <= idata;
		odata <= data;
	end
endmodule
module buffer(
	input clock,
	input idata,
	output reg odata
);


	reg [99:0] data;

	always@(posedge clock) begin 
		data <= idata;
		odata <= data;
	end
endmodule