data/full_repos/permissive/476810618/AD3_AD4/AD4/app_2_mux.v
data/verilator_xmls/77df90d7-53da-4616-b376-53a20cde5ed8.xml
module rout0 (
    output rout,
    input a,
    input b,
    input bin, qs

);
    wire diff;
    assign diff = a^b^bin;
    assign rout = qs&diff | ~qs&a;
endmodule
module rout0 (
    output rout,
    input a,
    input b,
    input bin, qs

);

    wire diff;
    assign diff = a^b^bin;
    assign rout = qs&diff | ~qs&a;
endmodule