data/full_repos/permissive/494305189/dispdrive_test/dispdrive_test.v
1: b"%Error: data/full_repos/permissive/494305189/dispdrive_test/dispdrive_test.v:11: Cannot find file containing module: 'dispdrive'\n dispdrive displaydriver(clk, rst, thsnds, hundrs, tens, uni, seldig, disp);\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/494305189/dispdrive_test,data/full_repos/permissive/494305189/dispdrive\n             data/full_repos/permissive/494305189/dispdrive_test,data/full_repos/permissive/494305189/dispdrive.v\n             data/full_repos/permissive/494305189/dispdrive_test,data/full_repos/permissive/494305189/dispdrive.sv\n             dispdrive\n             dispdrive.v\n             dispdrive.sv\n             obj_dir/dispdrive\n             obj_dir/dispdrive.v\n             obj_dir/dispdrive.sv\n%Error: Exiting due to 1 error(s)\n"
module dispdrive_test(input clk, input rst, output[6:0] disp, output[3:0] seldig);
	reg[3:0] uni, tens, hundrs, thsnds;
	reg[19:0] count;
	reg count_clk;
	
	dispdrive displaydriver(clk, rst, thsnds, hundrs, tens, uni, seldig, disp);
	
	always @(posedge clk)
	begin
		if (rst)
		begin
			count = 0;
			count_clk = 0;
		end
		else if (count == 1048575)
		begin
			count = 0;
			count_clk = !count_clk;
		end
		else
			count = count + 1;
	end
	
	always @(posedge count_clk)
	begin
		if (rst)
		begin
			uni = 0;
			tens = 0;
			hundrs = 0;
			thsnds = 0;
		end
		else
		begin
			if (uni == 9)
			begin
				uni = 0;
				if (tens == 9)
				begin
					tens = 0;
					if (hundrs == 9)
					begin
						hundrs = 0;
						if (thsnds == 9)
							thsnds = 0;
						else
							thsnds = thsnds + 1;
					end
					else
						hundrs = hundrs + 1;
				end
				else
					tens = tens + 1;
			end
			else
				uni = uni + 1;
		end
	end
	
endmodule
module dispdrive_test(input clk, input rst, output[6:0] disp, output[3:0] seldig);

	reg[3:0] uni, tens, hundrs, thsnds;
	reg[19:0] count;
	reg count_clk;
	
	dispdrive displaydriver(clk, rst, thsnds, hundrs, tens, uni, seldig, disp);
	
	always @(posedge clk)
	begin
		if (rst)
		begin
			count = 0;
			count_clk = 0;
		end
		else if (count == 1048575)
		begin
			count = 0;
			count_clk = !count_clk;
		end
		else
			count = count + 1;
	end
	
	always @(posedge count_clk)
	begin
		if (rst)
		begin
			uni = 0;
			tens = 0;
			hundrs = 0;
			thsnds = 0;
		end
		else
		begin
			if (uni == 9)
			begin
				uni = 0;
				if (tens == 9)
				begin
					tens = 0;
					if (hundrs == 9)
					begin
						hundrs = 0;
						if (thsnds == 9)
							thsnds = 0;
						else
							thsnds = thsnds + 1;
					end
					else
						hundrs = hundrs + 1;
				end
				else
					tens = tens + 1;
			end
			else
				uni = uni + 1;
		end
	end
	
endmodule