data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gclk_inv_r90_192x.v
data/verilator_xmls/45cf15a9-891d-4772-92ec-24a803359dbf.xml
module bw_clk_gclk_inv_r90_192x (
    clkout,
    clkin );

    output clkout;
    input  clkin;
 
    assign clkout = ~( clkin );

endmodule
module bw_clk_gclk_inv_r90_192x (
    clkout,
    clkin );


    output clkout;
    input  clkin;
 
    assign clkout = ~( clkin );

endmodule