data/full_repos/permissive/444559342/mp1/fifo/hdl/fifo.sv
1: b'%Error: data/full_repos/permissive/444559342/mp1/fifo/hdl/fifo.sv:1: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport fifo_types::*;\n       ^~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n'
module fifo_synch_1r1w
(
    input logic clk_i,
    input logic reset_n_i,


    input word_t data_i,
    input logic valid_i,
    output logic ready_o,


    output logic valid_o,
    output word_t data_o,
    input logic yumi_i
);



logic [width_p-1:0] queue [cap_p-1:0];


ptr_t read_ptr, write_ptr, read_ptr_next, write_ptr_next;


logic empty, full, ptr_eq, sign_match;
logic  enqueue, dequeue;



logic [width_p-1:0] output_buffer_r;



assign ready_o = ~full;
assign valid_o = ~empty;
assign data_o = output_buffer_r;



assign full = ptr_eq & (~sign_match);
assign ptr_eq = |(read_ptr[ptr_width_p-1:0] == write_ptr[ptr_width_p-1:0]);
assign sign_match = read_ptr[ptr_width_p] == write_ptr[ptr_width_p];
assign empty = ptr_eq & sign_match;
assign enqueue = ready_o & valid_i;
assign dequeue = valid_o & yumi_i;
assign write_ptr_next = write_ptr + 1;
assign read_ptr_next = read_ptr + 1;



always_ff @(posedge clk_i, negedge reset_n_i) begin

    if (~reset_n_i) begin
        read_ptr  <= 0;
        write_ptr <= 0;
    end
    else begin
        case ({enqueue, dequeue})
            2'b00: ;
            2'b01: begin : dequeue_case
                output_buffer_r <= queue[read_ptr_next[ptr_width_p-1:0]];
                read_ptr <= read_ptr_next;
            end
            2'b10: begin : enqueue_case
                queue[write_ptr[ptr_width_p-1:0]] <= data_i;
                write_ptr <= write_ptr_next;
                if (empty) begin
                    output_buffer_r <= data_i;
                end
            end




            2'b11: begin : dequeue_and_enqueue_case

                output_buffer_r <= read_ptr_next[ptr_width_p-1:0] ==
                                     write_ptr[ptr_width_p-1:0] ?
                                        data_i :
                                        queue[read_ptr_next[ptr_width_p-1:0]];
                read_ptr <= read_ptr_next;


                queue[write_ptr[ptr_width_p-1:0]] <= data_i;
                write_ptr <= write_ptr_next;

            end
        endcase
    end

end

endmodule
module fifo_synch_1r1w
(
    input logic clk_i,
    input logic reset_n_i,


    input word_t data_i,
    input logic valid_i,
    output logic ready_o,


    output logic valid_o,
    output word_t data_o,
    input logic yumi_i
);




logic [width_p-1:0] queue [cap_p-1:0];


ptr_t read_ptr, write_ptr, read_ptr_next, write_ptr_next;


logic empty, full, ptr_eq, sign_match;
logic  enqueue, dequeue;



logic [width_p-1:0] output_buffer_r;



assign ready_o = ~full;
assign valid_o = ~empty;
assign data_o = output_buffer_r;



assign full = ptr_eq & (~sign_match);
assign ptr_eq = |(read_ptr[ptr_width_p-1:0] == write_ptr[ptr_width_p-1:0]);
assign sign_match = read_ptr[ptr_width_p] == write_ptr[ptr_width_p];
assign empty = ptr_eq & sign_match;
assign enqueue = ready_o & valid_i;
assign dequeue = valid_o & yumi_i;
assign write_ptr_next = write_ptr + 1;
assign read_ptr_next = read_ptr + 1;



always_ff @(posedge clk_i, negedge reset_n_i) begin

    if (~reset_n_i) begin
        read_ptr  <= 0;
        write_ptr <= 0;
    end
    else begin
        case ({enqueue, dequeue})
            2'b00: ;
            2'b01: begin : dequeue_case
                output_buffer_r <= queue[read_ptr_next[ptr_width_p-1:0]];
                read_ptr <= read_ptr_next;
            end
            2'b10: begin : enqueue_case
                queue[write_ptr[ptr_width_p-1:0]] <= data_i;
                write_ptr <= write_ptr_next;
                if (empty) begin
                    output_buffer_r <= data_i;
                end
            end




            2'b11: begin : dequeue_and_enqueue_case

                output_buffer_r <= read_ptr_next[ptr_width_p-1:0] ==
                                     write_ptr[ptr_width_p-1:0] ?
                                        data_i :
                                        queue[read_ptr_next[ptr_width_p-1:0]];
                read_ptr <= read_ptr_next;


                queue[write_ptr[ptr_width_p-1:0]] <= data_i;
                write_ptr <= write_ptr_next;

            end
        endcase
    end

end

endmodule