data/full_repos/permissive/42434302/ivltests/undef_lval_select2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/undef_lval_select2.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (vec !== 4\'bxxx) begin\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/undef_lval_select2.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (vec !== 4\'bxxxx) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/undef_lval_select2.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (vec !== 4\'bxxxx) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/undef_lval_select2.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (vec !== 4\'bxxxx) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/undef_lval_select2.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (vec !== 4\'bxxxx) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/undef_lval_select2.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (vec !== 4\'bxxxx) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/undef_lval_select2.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (vec !== 4\'bxxxx) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/undef_lval_select2.v:62: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (vec !== 4\'bxxxx) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/undef_lval_select2.v:69: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (vec !== 4\'bxxxx) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/undef_lval_select2.v:76: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (vec !== 4\'bxxxx) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/undef_lval_select2.v:83: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (vec !== 4\'bxxxx) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/undef_lval_select2.v:90: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (vec !== 4\'bxxxx) begin\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/undef_lval_select2.v:97: Unsupported: Ignoring delay on this delayed statement.\n    #1 if (vec !== 4\'bxxxx) begin\n    ^\n%Error: Internal Error: ../V3Number.cpp:723: toUInt with 4-state 1\'bx\n                        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg pass;
  reg [2:-1] vec;
  integer idx;

  initial begin
    pass = 1'b1;

    idx = 'bx;

    vec = 4'bxxxx;
    vec[1'bx] <= 1'b1;
    #1 if (vec !== 4'bxxx) begin
      $display("Failed vec[1'bx], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end

    vec = 4'bxxxx;
    vec[idx] <= 1'b1;
    #1 if (vec !== 4'bxxxx) begin
      $display("Failed vec[1'bx], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end

    vec = 4'bxxxx;
    vec[1'bx:0] <= 1'b1;
    #1 if (vec !== 4'bxxxx) begin
      $display("Failed vec[1'bx:0], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end

    vec = 4'bxxxx;
    vec[0:1'bx] <= 1'b1;
    #1 if (vec !== 4'bxxxx) begin
      $display("Failed vec[0:1'bx], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end

    vec = 4'bxxxx;
    vec[1'bx:1'bx] <= 1'b1;
    #1 if (vec !== 4'bxxxx) begin
      $display("Failed vec[1'bx:1'bx], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end

    vec = 4'bxxxx;
    vec[1'bx+:1] <= 1'b1;
    #1 if (vec !== 4'bxxxx) begin
      $display("Failed vec[1'bx+:1], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end

    vec = 4'bxxxx;
    vec[1'bx+:2] <= 2'b01;
    #1 if (vec !== 4'bxxxx) begin
      $display("Failed vec[1'bx+:2], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end

    vec = 4'bxxxx;
    vec[1'bx-:1] <= 1'b1;
    #1 if (vec !== 4'bxxxx) begin
      $display("Failed vec[1'bx-:1], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end

    vec = 4'bxxxx;
    vec[1'bx-:2] <= 2'b01;
    #1 if (vec !== 4'bxxxx) begin
      $display("Failed vec[1'bx-:2], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end

    vec = 4'bxxxx;
    vec[idx+:1] <= 1'b1;
    #1 if (vec !== 4'bxxxx) begin
      $display("Failed vec[idx+:1], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end

    vec = 4'bxxxx;
    vec[idx+:2] <= 2'b01;
    #1 if (vec !== 4'bxxxx) begin
      $display("Failed vec[idx+:2], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end

    vec = 4'bxxxx;
    vec[idx-:1] <= 1'b1;
    #1 if (vec !== 4'bxxxx) begin
      $display("Failed vec[idx-:1], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end

    vec = 4'bxxxx;
    vec[idx-:2] <= 2'b01;
    #1 if (vec !== 4'bxxxx) begin
      $display("Failed vec[idx-:2], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule
module top;

  reg pass;
  reg [2:-1] vec;
  integer idx;

  initial begin
    pass = 1'b1;

    idx = 'bx;

    vec = 4'bxxxx;
    vec[1'bx] <= 1'b1;
    #1 if (vec !== 4'bxxx) begin
      $display("Failed vec[1'bx], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end

    vec = 4'bxxxx;
    vec[idx] <= 1'b1;
    #1 if (vec !== 4'bxxxx) begin
      $display("Failed vec[1'bx], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end

    vec = 4'bxxxx;
    vec[1'bx:0] <= 1'b1;
    #1 if (vec !== 4'bxxxx) begin
      $display("Failed vec[1'bx:0], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end

    vec = 4'bxxxx;
    vec[0:1'bx] <= 1'b1;
    #1 if (vec !== 4'bxxxx) begin
      $display("Failed vec[0:1'bx], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end

    vec = 4'bxxxx;
    vec[1'bx:1'bx] <= 1'b1;
    #1 if (vec !== 4'bxxxx) begin
      $display("Failed vec[1'bx:1'bx], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end

    vec = 4'bxxxx;
    vec[1'bx+:1] <= 1'b1;
    #1 if (vec !== 4'bxxxx) begin
      $display("Failed vec[1'bx+:1], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end

    vec = 4'bxxxx;
    vec[1'bx+:2] <= 2'b01;
    #1 if (vec !== 4'bxxxx) begin
      $display("Failed vec[1'bx+:2], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end

    vec = 4'bxxxx;
    vec[1'bx-:1] <= 1'b1;
    #1 if (vec !== 4'bxxxx) begin
      $display("Failed vec[1'bx-:1], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end

    vec = 4'bxxxx;
    vec[1'bx-:2] <= 2'b01;
    #1 if (vec !== 4'bxxxx) begin
      $display("Failed vec[1'bx-:2], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end

    vec = 4'bxxxx;
    vec[idx+:1] <= 1'b1;
    #1 if (vec !== 4'bxxxx) begin
      $display("Failed vec[idx+:1], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end

    vec = 4'bxxxx;
    vec[idx+:2] <= 2'b01;
    #1 if (vec !== 4'bxxxx) begin
      $display("Failed vec[idx+:2], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end

    vec = 4'bxxxx;
    vec[idx-:1] <= 1'b1;
    #1 if (vec !== 4'bxxxx) begin
      $display("Failed vec[idx-:1], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end

    vec = 4'bxxxx;
    vec[idx-:2] <= 2'b01;
    #1 if (vec !== 4'bxxxx) begin
      $display("Failed vec[idx-:2], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule