data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/ffxkclkx.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/ffxkclkx.v:45: Cannot find file containing module: 'ffxkclk'\n    ffxkclk #(K)    flxodat (clk,rst,idat[bit_idx],odat[bit_idx]);\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl,data/full_repos/permissive/530013823/ffxkclk\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl,data/full_repos/permissive/530013823/ffxkclk.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl,data/full_repos/permissive/530013823/ffxkclk.sv\n             ffxkclk\n             ffxkclk.v\n             ffxkclk.sv\n             obj_dir/ffxkclk\n             obj_dir/ffxkclk.v\n             obj_dir/ffxkclk.sv\n%Error: Exiting due to 1 error(s)\n"
module ffxkclkx
    (
     clk,
     rst,
     idat,
     odat
     );



parameter           K = 3;
parameter           W = 10;



input               clk;
input               rst;
input [W-1:0]       idat;
output [W-1:0]      odat;
  


wire [W-1:0]        odat;




generate
    genvar bit_idx;
for (bit_idx=0;bit_idx<W;bit_idx=bit_idx+1'b1)
    begin: i_bit
    ffxkclk #(K)    flxodat (clk,rst,idat[bit_idx],odat[bit_idx]);
    end
endgenerate

endmodule
module ffxkclkx
    (
     clk,
     rst,
     idat,
     odat
     );




parameter           K = 3;
parameter           W = 10;



input               clk;
input               rst;
input [W-1:0]       idat;
output [W-1:0]      odat;
  


wire [W-1:0]        odat;




generate
    genvar bit_idx;
for (bit_idx=0;bit_idx<W;bit_idx=bit_idx+1'b1)
    begin: i_bit
    ffxkclk #(K)    flxodat (clk,rst,idat[bit_idx],odat[bit_idx]);
    end
endgenerate

endmodule