data/full_repos/permissive/518305321/iiitb_sipo.v
data/verilator_xmls/5e90298d-f281-4702-845e-311723497ed6.xml
module dff(d,rst,clk,q);
    input d,clk,rst;
    output reg q;
    always @ (posedge clk)
    begin
    if(~rst)
    q<=0;
    else
    q<=d;
    end
endmodule
module dff(d,rst,clk,q);

    input d,clk,rst;
    output reg q;
    always @ (posedge clk)
    begin
    if(~rst)
    q<=0;
    else
    q<=d;
    end
endmodule