data/full_repos/permissive/411457613/Pyverilog/verilogcode/blocking.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/411457613/Pyverilog/verilogcode/blocking.v:20: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'OUT'\n                                                                                            : ... In instance TOP\n          OUT = 8'h0;\n          ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/411457613/Pyverilog/verilogcode/blocking.v:29: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'OUT'\n                                                                                            : ... In instance TOP\n          OUT = cnt;\n          ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/411457613/Pyverilog/verilogcode/blocking.v:38: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'OUT'\n                                                                                            : ... In instance TOP\n          OUT = cnt - 8;\n          ^~~\n%Error: Exiting due to 3 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module TOP(CLK, RST_X, IN, OUT);
  input CLK, RST_X;
  input [7:0] IN;
  output [7:0] OUT;

  reg [7:0] state;
  reg [7:0] cnt;
  
  reg [7:0] ncnt;
  reg [7:0] nstate;
  reg ctrljump;

  always @* begin

    case(state)
      0: begin
        ncnt = 0;
        ctrljump = 1;
        if(ctrljump) begin
          OUT = 8'h0;
          nstate = 1;
        end
      end
      
      1: begin
        ncnt = cnt + 1;
        ctrljump = cnt > 7;
        if(ctrljump) begin
          OUT = cnt;
          nstate = 2;
        end
      end
      
      2: begin
        ncnt = cnt + 2;
        ctrljump = cnt > 20;
        if(ctrljump) begin
          OUT = cnt - 8;
          nstate = 0;
        end
      end
    endcase
  end
  
  always @(posedge CLK) begin
    if(!RST_X) begin
      state <= 0;
      ncnt <= 0;
    end else begin
      state <= nstate;
      cnt <= ncnt;
    end
  end
  
endmodule
module TOP(CLK, RST_X, IN, OUT);

  input CLK, RST_X;
  input [7:0] IN;
  output [7:0] OUT;

  reg [7:0] state;
  reg [7:0] cnt;
  
  reg [7:0] ncnt;
  reg [7:0] nstate;
  reg ctrljump;

  always @* begin

    case(state)
      0: begin
        ncnt = 0;
        ctrljump = 1;
        if(ctrljump) begin
          OUT = 8'h0;
          nstate = 1;
        end
      end
      
      1: begin
        ncnt = cnt + 1;
        ctrljump = cnt > 7;
        if(ctrljump) begin
          OUT = cnt;
          nstate = 2;
        end
      end
      
      2: begin
        ncnt = cnt + 2;
        ctrljump = cnt > 20;
        if(ctrljump) begin
          OUT = cnt - 8;
          nstate = 0;
        end
      end
    endcase
  end
  
  always @(posedge CLK) begin
    if(!RST_X) begin
      state <= 0;
      ncnt <= 0;
    end else begin
      state <= nstate;
      cnt <= ncnt;
    end
  end
  
endmodule