data/full_repos/permissive/416058412/hw/rtl/pulse_gen.sv
1: b'%Warning-LITENDIAN: data/full_repos/permissive/416058412/hw/rtl/pulse_gen.sv:24: Little bit endian vector: MSB < LSB of bit range: -1:0\n    logic[CNT_WIDTH-1:0] cnt;\n         ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/416058412/hw/rtl/pulse_gen.sv:27: Replication value of 0 is only legal under a concatenation (IEEE 1800-2017 11.4.12.1)\n                                                                   : ... In instance pulse_gen\n            cnt <= {(CNT_WIDTH){1\'b0}};\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/416058412/hw/rtl/pulse_gen.sv:27: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 1 bits.\n                                                                           : ... In instance pulse_gen\n            cnt <= {(CNT_WIDTH){1\'b0}};\n                ^~\n%Error: data/full_repos/permissive/416058412/hw/rtl/pulse_gen.sv:36: Replication value of 0 is only legal under a concatenation (IEEE 1800-2017 11.4.12.1)\n                                                                   : ... In instance pulse_gen\n                    cnt <= {(CNT_WIDTH){1\'b0}};\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/416058412/hw/rtl/pulse_gen.sv:36: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 1 bits.\n                                                                           : ... In instance pulse_gen\n                    cnt <= {(CNT_WIDTH){1\'b0}};\n                        ^~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module pulse_gen
    #(
        parameter N_OF_CYCLES = 1
    )
    (
        input logic clk,
        input logic reset,
        input logic sig_in,

        output logic pulse_out
    );

    localparam CNT_WIDTH = $clog2(N_OF_CYCLES);

    logic pulse;
    logic[CNT_WIDTH-1:0] cnt;
    always_ff @(posedge clk) begin
        if (reset) begin
            cnt <= {(CNT_WIDTH){1'b0}};
            pulse <= 1'b0;
        end else begin
            if (sig_in) begin
                pulse <= 1'b1;
            end
            if (pulse) begin
                if (cnt == N_OF_CYCLES - 1) begin
                    pulse <= 1'b0;
                    cnt <= {(CNT_WIDTH){1'b0}};
                end else begin
                    cnt <= cnt + 1;
                end
            end
        end
    end

    assign pulse_out = pulse;


endmodule
module pulse_gen
    #(
        parameter N_OF_CYCLES = 1
    )
    (
        input logic clk,
        input logic reset,
        input logic sig_in,

        output logic pulse_out
    );


    localparam CNT_WIDTH = $clog2(N_OF_CYCLES);

    logic pulse;
    logic[CNT_WIDTH-1:0] cnt;
    always_ff @(posedge clk) begin
        if (reset) begin
            cnt <= {(CNT_WIDTH){1'b0}};
            pulse <= 1'b0;
        end else begin
            if (sig_in) begin
                pulse <= 1'b1;
            end
            if (pulse) begin
                if (cnt == N_OF_CYCLES - 1) begin
                    pulse <= 1'b0;
                    cnt <= {(CNT_WIDTH){1'b0}};
                end else begin
                    cnt <= cnt + 1;
                end
            end
        end
    end

    assign pulse_out = pulse;


endmodule