data/full_repos/permissive/494962889/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/494962889/verilog/rtl/user_proj_example.v:78: Duplicate declaration of signal: 'io_in'\n                                                                               : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n    wire [38-1:0] io_in;\n                  ^~~~~\n        data/full_repos/permissive/494962889/verilog/rtl/user_proj_example.v:65: ... Location of original declaration\n    input  [38-1:0] io_in,\n                    ^~~~~\n%Error: data/full_repos/permissive/494962889/verilog/rtl/user_proj_example.v:79: Duplicate declaration of signal: 'io_out'\n    wire [38-1:0] io_out;\n                  ^~~~~~\n        data/full_repos/permissive/494962889/verilog/rtl/user_proj_example.v:66: ... Location of original declaration\n    output [38-1:0] io_out,\n                    ^~~~~~\n%Error: data/full_repos/permissive/494962889/verilog/rtl/user_proj_example.v:80: Duplicate declaration of signal: 'io_oeb'\n    wire [38-1:0] io_oeb;\n                  ^~~~~~\n        data/full_repos/permissive/494962889/verilog/rtl/user_proj_example.v:67: ... Location of original declaration\n    output [38-1:0] io_oeb,\n                    ^~~~~~\n%Error: Exiting due to 3 error(s)\n"
module user_proj_example #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,


    output [2:0] irq
);
    wire clk;
    wire rst;
    wire rx_i;
    wire [15:0] FPU_hp_result;
    wire [15:0] CLKS_PER_BIT;

    wire [`MPRJ_IO_PADS-1:0] io_in;
    wire [`MPRJ_IO_PADS-1:0] io_out;
    wire [`MPRJ_IO_PADS-1:0] io_oeb;



    assign io_oeb[5] = 1'b1;
    assign io_oeb[23:8] = 16'h0000;
    assign io_out[23:8] = FPU_hp_result;
    

    assign rx_i = (~la_oenb[1]) ? la_data_in[1] : io_in[5];


    assign irq = 3'b000;


    assign la_data_out[31:0] = 32'h00000000;
    assign la_data_out[47:32] = (&la_oenb[47:32]) ? FPU_hp_result : 16'h0000;
    assign la_data_out[127:48] = {80{1'b0}};
    

    assign clk = (~la_oenb[64]) ? la_data_in[64] : wb_clk_i;
    assign rst = (~la_oenb[65]) ? la_data_in[65] : ~wb_rst_i;
    assign CLKS_PER_BIT = (la_oenb[31:16] == 16'h0000) ? la_data_in[31:16] : 16'd348;
   

    FPU_FSM_TOP FPU_Bfloat16_Precision_Top (
    					`ifdef USE_POWER_PINS
    					   .vccd1(vccd1),
    					   .vssd1(vssd1),
					`endif
    					  .clk(clk),
    					  .rst_l(rst),
    					  .r_Rx_Serial(rx_i),
    					  .CLKS_PER_BIT(CLKS_PER_BIT),
    					  .FPU_hp_result(FPU_hp_result)
    					  );

endmodule
module user_proj_example #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,


    output [2:0] irq
);

    wire clk;
    wire rst;
    wire rx_i;
    wire [15:0] FPU_hp_result;
    wire [15:0] CLKS_PER_BIT;

    wire [`MPRJ_IO_PADS-1:0] io_in;
    wire [`MPRJ_IO_PADS-1:0] io_out;
    wire [`MPRJ_IO_PADS-1:0] io_oeb;



    assign io_oeb[5] = 1'b1;
    assign io_oeb[23:8] = 16'h0000;
    assign io_out[23:8] = FPU_hp_result;
    

    assign rx_i = (~la_oenb[1]) ? la_data_in[1] : io_in[5];


    assign irq = 3'b000;


    assign la_data_out[31:0] = 32'h00000000;
    assign la_data_out[47:32] = (&la_oenb[47:32]) ? FPU_hp_result : 16'h0000;
    assign la_data_out[127:48] = {80{1'b0}};
    

    assign clk = (~la_oenb[64]) ? la_data_in[64] : wb_clk_i;
    assign rst = (~la_oenb[65]) ? la_data_in[65] : ~wb_rst_i;
    assign CLKS_PER_BIT = (la_oenb[31:16] == 16'h0000) ? la_data_in[31:16] : 16'd348;
   

    FPU_FSM_TOP FPU_Bfloat16_Precision_Top (
    					`ifdef USE_POWER_PINS
    					   .vccd1(vccd1),
    					   .vssd1(vssd1),
					`endif
    					  .clk(clk),
    					  .rst_l(rst),
    					  .r_Rx_Serial(rx_i),
    					  .CLKS_PER_BIT(CLKS_PER_BIT),
    					  .FPU_hp_result(FPU_hp_result)
    					  );

endmodule