data/full_repos/permissive/447976230/fpga/usrp2/boot_cpld/boot_cpld.v
1: b"%Error: data/full_repos/permissive/447976230/fpga/usrp2/boot_cpld/boot_cpld.v:61: Cannot find file containing module: 'spi_boot'\n   spi_boot #(.width_set_sel_g(4),   \n   ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp2/boot_cpld,data/full_repos/permissive/447976230/spi_boot\n             data/full_repos/permissive/447976230/fpga/usrp2/boot_cpld,data/full_repos/permissive/447976230/spi_boot.v\n             data/full_repos/permissive/447976230/fpga/usrp2/boot_cpld,data/full_repos/permissive/447976230/spi_boot.sv\n             spi_boot\n             spi_boot.v\n             spi_boot.sv\n             obj_dir/spi_boot\n             obj_dir/spi_boot.v\n             obj_dir/spi_boot.sv\n%Error: Exiting due to 1 error(s)\n"
module boot_cpld
  (input CLK_25MHZ,
   output CLK_25MHZ_EN,
   output [2:0] LED,
   output [8:0] DEBUG,
   input 	 POR,
   

   output 	 SD_nCS,
   output 	 SD_Din,
   output 	 SD_CLK,
   input 	 SD_Dout,
   input 	 SD_DAT1,
   input 	 SD_DAT2,
   input         SD_prot,
   input         SD_det,
   

   input 	 CFG_INIT_B,
   output 	 CFG_Din,
   output 	 CFG_CCLK,
   input 	 CFG_DONE,
   output 	 CFG_PROG_B,
   

   output 	 CPLD_CLK,
   input 	 START,
   input 	 MODE,
   input 	 DONE,
   output 	 detached,
   input         CPLD_misc
   );
   
   assign 	 CLK_25MHZ_EN = 1'b1;
   
   assign 	 LED[0] = ~CFG_DONE;
   assign 	 LED[1] = CFG_INIT_B;
   assign 	 LED[2] = ~CFG_PROG_B;
   			
   wire 	 en_outs;
   wire [3:0] 	 set_sel = 4'd0;
   
   assign 	 CPLD_CLK = CFG_CCLK;
   assign 	 DEBUG[8:0] = { CLK_25MHZ, SD_nCS, SD_CLK, SD_Din, SD_Dout, 
				START, MODE, DONE, CPLD_misc};


   wire 	 fpga_takeover = ~CPLD_misc;
   wire 	 SD_CLK_int, SD_nCS_int, SD_Din_int, CFG_Din_int;

   assign 	 SD_CLK = fpga_takeover ? START : SD_CLK_int;
   assign 	 SD_nCS = fpga_takeover ? MODE : SD_nCS_int;
   assign 	 SD_Din = fpga_takeover ? DONE : SD_Din_int;
   assign 	 CFG_Din = fpga_takeover ? SD_Dout : CFG_Din_int;

   spi_boot #(.width_set_sel_g(4),
	      .width_bit_cnt_g(6),
	      .width_img_cnt_g(2),
	      .num_bits_per_img_g(20),
	      .sd_init_g(1),
	      .mmc_compat_clk_div_g(0),
	      .width_mmc_clk_div_g(0),
	      .reset_level_g(0))
     
     spi_boot(.clk_i(CLK_25MHZ), 
	      .reset_i(POR),
	      

	      .spi_clk_o(SD_CLK_int), 
	      .spi_cs_n_o(SD_nCS_int),
	      .spi_data_in_i(SD_Dout), 
	      .spi_data_out_o(SD_Din_int), 
	      .spi_en_outs_o(en_outs), 
	      

	      .start_i(START),
	      .mode_i(MODE),
	      .detached_o(detached), 
	      .dat_done_i(DONE), 
	      .set_sel_i(set_sel),
	      

	      .config_n_o(CFG_PROG_B), 
	      .cfg_init_n_i(CFG_INIT_B), 
	      .cfg_done_i(CFG_DONE), 
	      .cfg_clk_o(CFG_CCLK), 
	      .cfg_dat_o(CFG_Din_int)
	      );
   
endmodule
module boot_cpld
  (input CLK_25MHZ,
   output CLK_25MHZ_EN,
   output [2:0] LED,
   output [8:0] DEBUG,
   input 	 POR,
   

   output 	 SD_nCS,
   output 	 SD_Din,
   output 	 SD_CLK,
   input 	 SD_Dout,
   input 	 SD_DAT1,
   input 	 SD_DAT2,
   input         SD_prot,
   input         SD_det,
   

   input 	 CFG_INIT_B,
   output 	 CFG_Din,
   output 	 CFG_CCLK,
   input 	 CFG_DONE,
   output 	 CFG_PROG_B,
   

   output 	 CPLD_CLK,
   input 	 START,
   input 	 MODE,
   input 	 DONE,
   output 	 detached,
   input         CPLD_misc
   );

   
   assign 	 CLK_25MHZ_EN = 1'b1;
   
   assign 	 LED[0] = ~CFG_DONE;
   assign 	 LED[1] = CFG_INIT_B;
   assign 	 LED[2] = ~CFG_PROG_B;
   			
   wire 	 en_outs;
   wire [3:0] 	 set_sel = 4'd0;
   
   assign 	 CPLD_CLK = CFG_CCLK;
   assign 	 DEBUG[8:0] = { CLK_25MHZ, SD_nCS, SD_CLK, SD_Din, SD_Dout, 
				START, MODE, DONE, CPLD_misc};


   wire 	 fpga_takeover = ~CPLD_misc;
   wire 	 SD_CLK_int, SD_nCS_int, SD_Din_int, CFG_Din_int;

   assign 	 SD_CLK = fpga_takeover ? START : SD_CLK_int;
   assign 	 SD_nCS = fpga_takeover ? MODE : SD_nCS_int;
   assign 	 SD_Din = fpga_takeover ? DONE : SD_Din_int;
   assign 	 CFG_Din = fpga_takeover ? SD_Dout : CFG_Din_int;

   spi_boot #(.width_set_sel_g(4),
	      .width_bit_cnt_g(6),
	      .width_img_cnt_g(2),
	      .num_bits_per_img_g(20),
	      .sd_init_g(1),
	      .mmc_compat_clk_div_g(0),
	      .width_mmc_clk_div_g(0),
	      .reset_level_g(0))
     
     spi_boot(.clk_i(CLK_25MHZ), 
	      .reset_i(POR),
	      

	      .spi_clk_o(SD_CLK_int), 
	      .spi_cs_n_o(SD_nCS_int),
	      .spi_data_in_i(SD_Dout), 
	      .spi_data_out_o(SD_Din_int), 
	      .spi_en_outs_o(en_outs), 
	      

	      .start_i(START),
	      .mode_i(MODE),
	      .detached_o(detached), 
	      .dat_done_i(DONE), 
	      .set_sel_i(set_sel),
	      

	      .config_n_o(CFG_PROG_B), 
	      .cfg_init_n_i(CFG_INIT_B), 
	      .cfg_done_i(CFG_DONE), 
	      .cfg_clk_o(CFG_CCLK), 
	      .cfg_dat_o(CFG_Din_int)
	      );
   
endmodule