data/full_repos/permissive/416548358/Adder.srcs/sources_1/new/top_level.v
1: b"%Error: data/full_repos/permissive/416548358/Adder.srcs/sources_1/new/top_level.v:35: Duplicate declaration of cell: 'bit_full_adder_0'\n    bit_full_adder bit_full_adder_0(Input[8],  Input[9],  carry[4],  Output[4], carry[5]);\n                   ^~~~~~~~~~~~~~~~\n        data/full_repos/permissive/416548358/Adder.srcs/sources_1/new/top_level.v:30: ... Location of original declaration\n    bit_full_adder bit_full_adder_0(Input[0], Input[1], 0,           Output[0], carry[1]);\n                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/416548358/Adder.srcs/sources_1/new/top_level.v:36: Duplicate declaration of cell: 'bit_full_adder_1'\n    bit_full_adder bit_full_adder_1(Input[10], Input[11], carry[5],  Output[5], carry[6]);\n                   ^~~~~~~~~~~~~~~~\n        data/full_repos/permissive/416548358/Adder.srcs/sources_1/new/top_level.v:31: ... Location of original declaration\n    bit_full_adder bit_full_adder_1(Input[2], Input[3], carry[1],    Output[1], carry[2]);\n                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/416548358/Adder.srcs/sources_1/new/top_level.v:37: Duplicate declaration of cell: 'bit_full_adder_2'\n    bit_full_adder bit_full_adder_2(Input[12], Input[13], carry[6],  Output[6], carry[7]);\n                   ^~~~~~~~~~~~~~~~\n        data/full_repos/permissive/416548358/Adder.srcs/sources_1/new/top_level.v:32: ... Location of original declaration\n    bit_full_adder bit_full_adder_2(Input[4], Input[5], carry[2],    Output[2], carry[3]);\n                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/416548358/Adder.srcs/sources_1/new/top_level.v:38: Duplicate declaration of cell: 'bit_full_adder_3'\n    bit_full_adder bit_full_adder_3(Input[14], Input[15], carry[7],  Output[7], carry[8]);\n                   ^~~~~~~~~~~~~~~~\n        data/full_repos/permissive/416548358/Adder.srcs/sources_1/new/top_level.v:33: ... Location of original declaration\n    bit_full_adder bit_full_adder_3(Input[6], Input[7], carry[3],    Output[3], carry[4]);\n                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/416548358/Adder.srcs/sources_1/new/top_level.v:40: Duplicate declaration of cell: 'bit_full_adder_0'\n    bit_full_adder bit_full_adder_0(Input[16], Input[17], carry[8],  Output[8], carry[9]);\n                   ^~~~~~~~~~~~~~~~\n        data/full_repos/permissive/416548358/Adder.srcs/sources_1/new/top_level.v:35: ... Location of original declaration\n    bit_full_adder bit_full_adder_0(Input[8],  Input[9],  carry[4],  Output[4], carry[5]);\n                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/416548358/Adder.srcs/sources_1/new/top_level.v:41: Duplicate declaration of cell: 'bit_full_adder_1'\n    bit_full_adder bit_full_adder_1(Input[18], Input[19], carry[9],  Output[9], carry[10]);\n                   ^~~~~~~~~~~~~~~~\n        data/full_repos/permissive/416548358/Adder.srcs/sources_1/new/top_level.v:36: ... Location of original declaration\n    bit_full_adder bit_full_adder_1(Input[10], Input[11], carry[5],  Output[5], carry[6]);\n                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/416548358/Adder.srcs/sources_1/new/top_level.v:42: Duplicate declaration of cell: 'bit_full_adder_2'\n    bit_full_adder bit_full_adder_2(Input[20], Input[21], carry[10], Output[10], carry[11]);\n                   ^~~~~~~~~~~~~~~~\n        data/full_repos/permissive/416548358/Adder.srcs/sources_1/new/top_level.v:37: ... Location of original declaration\n    bit_full_adder bit_full_adder_2(Input[12], Input[13], carry[6],  Output[6], carry[7]);\n                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/416548358/Adder.srcs/sources_1/new/top_level.v:43: Duplicate declaration of cell: 'bit_full_adder_3'\n    bit_full_adder bit_full_adder_3(Input[22], Input[23], carry[11], Output[11], carry[12]);\n                   ^~~~~~~~~~~~~~~~\n        data/full_repos/permissive/416548358/Adder.srcs/sources_1/new/top_level.v:38: ... Location of original declaration\n    bit_full_adder bit_full_adder_3(Input[14], Input[15], carry[7],  Output[7], carry[8]);\n                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/416548358/Adder.srcs/sources_1/new/top_level.v:45: Duplicate declaration of cell: 'bit_full_adder_0'\n    bit_full_adder bit_full_adder_0(Input[24], Input[25], carry[12], Output[12], carry[13]);\n                   ^~~~~~~~~~~~~~~~\n        data/full_repos/permissive/416548358/Adder.srcs/sources_1/new/top_level.v:40: ... Location of original declaration\n    bit_full_adder bit_full_adder_0(Input[16], Input[17], carry[8],  Output[8], carry[9]);\n                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/416548358/Adder.srcs/sources_1/new/top_level.v:46: Duplicate declaration of cell: 'bit_full_adder_1'\n    bit_full_adder bit_full_adder_1(Input[26], Input[27], carry[13], Output[13], carry[14]);\n                   ^~~~~~~~~~~~~~~~\n        data/full_repos/permissive/416548358/Adder.srcs/sources_1/new/top_level.v:41: ... Location of original declaration\n    bit_full_adder bit_full_adder_1(Input[18], Input[19], carry[9],  Output[9], carry[10]);\n                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/416548358/Adder.srcs/sources_1/new/top_level.v:47: Duplicate declaration of cell: 'bit_full_adder_2'\n    bit_full_adder bit_full_adder_2(Input[28], Input[29], carry[14], Output[14], carry[15]);\n                   ^~~~~~~~~~~~~~~~\n        data/full_repos/permissive/416548358/Adder.srcs/sources_1/new/top_level.v:42: ... Location of original declaration\n    bit_full_adder bit_full_adder_2(Input[20], Input[21], carry[10], Output[10], carry[11]);\n                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/416548358/Adder.srcs/sources_1/new/top_level.v:48: Duplicate declaration of cell: 'bit_full_adder_3'\n    bit_full_adder bit_full_adder_3(Input[30], Input[31], carry[15], Output[15], carry[16]);\n                   ^~~~~~~~~~~~~~~~\n        data/full_repos/permissive/416548358/Adder.srcs/sources_1/new/top_level.v:43: ... Location of original declaration\n    bit_full_adder bit_full_adder_3(Input[22], Input[23], carry[11], Output[11], carry[12]);\n                   ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 12 error(s)\n"
module top_level(
    input [31:0] Input,
    output [31:0] Output
    );
   
    wire [16:0] carry;
    
    bit_full_adder bit_full_adder_0(Input[0], Input[1], 0,           Output[0], carry[1]);
    bit_full_adder bit_full_adder_1(Input[2], Input[3], carry[1],    Output[1], carry[2]);
    bit_full_adder bit_full_adder_2(Input[4], Input[5], carry[2],    Output[2], carry[3]);
    bit_full_adder bit_full_adder_3(Input[6], Input[7], carry[3],    Output[3], carry[4]);
    
    bit_full_adder bit_full_adder_0(Input[8],  Input[9],  carry[4],  Output[4], carry[5]);
    bit_full_adder bit_full_adder_1(Input[10], Input[11], carry[5],  Output[5], carry[6]);
    bit_full_adder bit_full_adder_2(Input[12], Input[13], carry[6],  Output[6], carry[7]);
    bit_full_adder bit_full_adder_3(Input[14], Input[15], carry[7],  Output[7], carry[8]);
    
    bit_full_adder bit_full_adder_0(Input[16], Input[17], carry[8],  Output[8], carry[9]);
    bit_full_adder bit_full_adder_1(Input[18], Input[19], carry[9],  Output[9], carry[10]);
    bit_full_adder bit_full_adder_2(Input[20], Input[21], carry[10], Output[10], carry[11]);
    bit_full_adder bit_full_adder_3(Input[22], Input[23], carry[11], Output[11], carry[12]);
    
    bit_full_adder bit_full_adder_0(Input[24], Input[25], carry[12], Output[12], carry[13]);
    bit_full_adder bit_full_adder_1(Input[26], Input[27], carry[13], Output[13], carry[14]);
    bit_full_adder bit_full_adder_2(Input[28], Input[29], carry[14], Output[14], carry[15]);
    bit_full_adder bit_full_adder_3(Input[30], Input[31], carry[15], Output[15], carry[16]);
        
endmodule
module top_level(
    input [31:0] Input,
    output [31:0] Output
    );

   
    wire [16:0] carry;
    
    bit_full_adder bit_full_adder_0(Input[0], Input[1], 0,           Output[0], carry[1]);
    bit_full_adder bit_full_adder_1(Input[2], Input[3], carry[1],    Output[1], carry[2]);
    bit_full_adder bit_full_adder_2(Input[4], Input[5], carry[2],    Output[2], carry[3]);
    bit_full_adder bit_full_adder_3(Input[6], Input[7], carry[3],    Output[3], carry[4]);
    
    bit_full_adder bit_full_adder_0(Input[8],  Input[9],  carry[4],  Output[4], carry[5]);
    bit_full_adder bit_full_adder_1(Input[10], Input[11], carry[5],  Output[5], carry[6]);
    bit_full_adder bit_full_adder_2(Input[12], Input[13], carry[6],  Output[6], carry[7]);
    bit_full_adder bit_full_adder_3(Input[14], Input[15], carry[7],  Output[7], carry[8]);
    
    bit_full_adder bit_full_adder_0(Input[16], Input[17], carry[8],  Output[8], carry[9]);
    bit_full_adder bit_full_adder_1(Input[18], Input[19], carry[9],  Output[9], carry[10]);
    bit_full_adder bit_full_adder_2(Input[20], Input[21], carry[10], Output[10], carry[11]);
    bit_full_adder bit_full_adder_3(Input[22], Input[23], carry[11], Output[11], carry[12]);
    
    bit_full_adder bit_full_adder_0(Input[24], Input[25], carry[12], Output[12], carry[13]);
    bit_full_adder bit_full_adder_1(Input[26], Input[27], carry[13], Output[13], carry[14]);
    bit_full_adder bit_full_adder_2(Input[28], Input[29], carry[14], Output[14], carry[15]);
    bit_full_adder bit_full_adder_3(Input[30], Input[31], carry[15], Output[15], carry[16]);
        
endmodule