data/full_repos/permissive/493019833/test/testcase/firrtl/StreamingAutocorrelator/sbt/StreamingAutocorrelator.v
data/verilator_xmls/122dc502-941b-4708-90a5-0fed93fff279.xml
module StreamingAutocorrelator(
  input         clock,
  input         reset,
  input  [9:0]  io_input,
  output [19:0] io_output
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif
  wire  firFilter_clock;
  wire [9:0] firFilter_io_input;
  wire [19:0] firFilter_io_output;
  wire [9:0] firFilter_io_taps_0;
  wire [9:0] firFilter_io_taps_1;
  wire [9:0] firFilter_io_taps_2;
  reg [9:0] delays_1;
  reg [9:0] delays_2;
  reg [9:0] delays_3;
  reg [9:0] delays_4;
  reg [9:0] delays_5;
  TransposedStreamingFIR firFilter (
    .clock(firFilter_clock),
    .io_input(firFilter_io_input),
    .io_output(firFilter_io_output),
    .io_taps_0(firFilter_io_taps_0),
    .io_taps_1(firFilter_io_taps_1),
    .io_taps_2(firFilter_io_taps_2)
  );
  assign io_output = firFilter_io_output;
  assign firFilter_clock = clock;
  assign firFilter_io_input = io_input;
  assign firFilter_io_taps_0 = delays_5;
  assign firFilter_io_taps_1 = delays_4;
  assign firFilter_io_taps_2 = delays_3;
  always @(posedge clock) begin
    delays_1 <= io_input;
    delays_2 <= delays_1;
    delays_3 <= delays_2;
    delays_4 <= delays_3;
    delays_5 <= delays_4;
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  delays_1 = _RAND_0[9:0];
  _RAND_1 = {1{`RANDOM}};
  delays_2 = _RAND_1[9:0];
  _RAND_2 = {1{`RANDOM}};
  delays_3 = _RAND_2[9:0];
  _RAND_3 = {1{`RANDOM}};
  delays_4 = _RAND_3[9:0];
  _RAND_4 = {1{`RANDOM}};
  delays_5 = _RAND_4[9:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module StreamingAutocorrelator(
  input         clock,
  input         reset,
  input  [9:0]  io_input,
  output [19:0] io_output
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif
  wire  firFilter_clock;
  wire [9:0] firFilter_io_input;
  wire [19:0] firFilter_io_output;
  wire [9:0] firFilter_io_taps_0;
  wire [9:0] firFilter_io_taps_1;
  wire [9:0] firFilter_io_taps_2;
  reg [9:0] delays_1;
  reg [9:0] delays_2;
  reg [9:0] delays_3;
  reg [9:0] delays_4;
  reg [9:0] delays_5;
  TransposedStreamingFIR firFilter (
    .clock(firFilter_clock),
    .io_input(firFilter_io_input),
    .io_output(firFilter_io_output),
    .io_taps_0(firFilter_io_taps_0),
    .io_taps_1(firFilter_io_taps_1),
    .io_taps_2(firFilter_io_taps_2)
  );
  assign io_output = firFilter_io_output;
  assign firFilter_clock = clock;
  assign firFilter_io_input = io_input;
  assign firFilter_io_taps_0 = delays_5;
  assign firFilter_io_taps_1 = delays_4;
  assign firFilter_io_taps_2 = delays_3;
  always @(posedge clock) begin
    delays_1 <= io_input;
    delays_2 <= delays_1;
    delays_3 <= delays_2;
    delays_4 <= delays_3;
    delays_5 <= delays_4;
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  delays_1 = _RAND_0[9:0];
  _RAND_1 = {1{`RANDOM}};
  delays_2 = _RAND_1[9:0];
  _RAND_2 = {1{`RANDOM}};
  delays_3 = _RAND_2[9:0];
  _RAND_3 = {1{`RANDOM}};
  delays_4 = _RAND_3[9:0];
  _RAND_4 = {1{`RANDOM}};
  delays_5 = _RAND_4[9:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule