data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/SYNTAX_BENCHMARKS/delay_syntax.v
data/verilator_xmls/f0a46c92-6ac4-463d-b691-fe4e3aa5a699.xml
module delay_syntax (clock,a,b,c,d);

input clock;
input a;
output b;
output c;
output d;

reg x;
reg y;
reg delayed;

assign b = x;
assign c = y;
assign #10 d = delayed;

always @ (posedge clock)
	begin
		x <= a;
		y <= x;
		delayed <= x;
	end
	
endmodule
module delay_syntax (clock,a,b,c,d);


input clock;
input a;
output b;
output c;
output d;

reg x;
reg y;
reg delayed;

assign b = x;
assign c = y;
assign #10 d = delayed;

always @ (posedge clock)
	begin
		x <= a;
		y <= x;
		delayed <= x;
	end
	
endmodule