data/full_repos/permissive/434840709/lab3/3.1/clkDiv.v
data/verilator_xmls/a37235ee-e9a4-4dd1-a48a-23ef59001199.xml
module clkDiv(
    input clk100mhz,
    output clk190hz,
    output clk3hz
    );

    reg [25:0] count = 0;
    assign clk190hz = count[18];
    assign clk3hz = count[25];
    always @(posedge clk100mhz) begin
       count <= count + 1; 
    end

endmodule
module clkDiv(
    input clk100mhz,
    output clk190hz,
    output clk3hz
    );


    reg [25:0] count = 0;
    assign clk190hz = count[18];
    assign clk3hz = count[25];
    always @(posedge clk100mhz) begin
       count <= count + 1; 
    end

endmodule