data/full_repos/permissive/52703097/alu.test.v
1: b'%Error: data/full_repos/permissive/52703097/alu.test.v:1: Cannot find include file: alu.v\n`include "alu.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52703097,data/full_repos/permissive/52703097/alu.v\n             data/full_repos/permissive/52703097,data/full_repos/permissive/52703097/alu.v.v\n             data/full_repos/permissive/52703097,data/full_repos/permissive/52703097/alu.v.sv\n             alu.v\n             alu.v.v\n             alu.v.sv\n             obj_dir/alu.v\n             obj_dir/alu.v.v\n             obj_dir/alu.v.sv\n%Error: data/full_repos/permissive/52703097/alu.test.v:2: Cannot find include file: sim.v\n`include "sim.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/52703097/alu.test.v:33: Define or directive not defined: \'`OP_NOP\'\nreg [3:0] op = `OP_NOP;\n               ^~~~~~~\n%Error: data/full_repos/permissive/52703097/alu.test.v:33: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nreg [3:0] op = `OP_NOP;\n                      ^\n%Error: data/full_repos/permissive/52703097/alu.test.v:45: Define or directive not defined: \'`OP_LEFT_SHIFTL\'\n   op <= `OP_LEFT_SHIFTL;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/52703097/alu.test.v:45: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   op <= `OP_LEFT_SHIFTL;\n                        ^\n%Error: Exiting due to 6 error(s)\n'
module test();

wire reset;
wire clk;


wire [31:0] alu_a;
wire [31:0] alu_b;
wire [3:0] alu_cmd;

wire [31:0] alu_result;
wire        alu_res_valid;
wire        alu_ready;


reg [32+32-1:0] tests [0:`TESTS-1];
reg done = 1'b0;


integer i;
integer tmp;

reg [31:0] t = 5'h0;

reg [31:0] a,b,res;
reg [3:0] op = `OP_NOP;

assign alu_a   = a;
assign alu_b   = b;
assign alu_cmd = op;


initial begin
  for(i = 0; i < `TESTS; i = i + 1) begin
      tmp = $random % 32;
      tests[i] <= {{$random},{tmp}};
  end
   op <= `OP_LEFT_SHIFTL;
end

always @(posedge alu_res_valid) begin
  if (alu_result != res)
    $display("Result wrong!");
end

always @(posedge alu_ready) begin
   a <= tests[t][63:32];
   b <= tests[t][31:0];
   res <= tests[t][63:32] << tests[t][31:0];
   if (t + 1 < `TESTS)
     t = t + 1;
   else begin

     t = 0;
     done = 1'b1;
   end
end



alu my_alu
(
  .clk(clk),
  .reset(reset),

  .i_a(alu_a),
  .i_b(alu_b),
  .i_cmd(alu_cmd),

  .o_result(alu_result),
  .o_valid(alu_res_valid),
  .o_ready(alu_ready)
);


sim my_sim(
  .clk(clk),
  .reset(reset)
);

endmodule
module test();


wire reset;
wire clk;


wire [31:0] alu_a;
wire [31:0] alu_b;
wire [3:0] alu_cmd;

wire [31:0] alu_result;
wire        alu_res_valid;
wire        alu_ready;


reg [32+32-1:0] tests [0:`TESTS-1];
reg done = 1'b0;


integer i;
integer tmp;

reg [31:0] t = 5'h0;

reg [31:0] a,b,res;
reg [3:0] op = `OP_NOP;

assign alu_a   = a;
assign alu_b   = b;
assign alu_cmd = op;


initial begin
  for(i = 0; i < `TESTS; i = i + 1) begin
      tmp = $random % 32;
      tests[i] <= {{$random},{tmp}};
  end
   op <= `OP_LEFT_SHIFTL;
end

always @(posedge alu_res_valid) begin
  if (alu_result != res)
    $display("Result wrong!");
end

always @(posedge alu_ready) begin
   a <= tests[t][63:32];
   b <= tests[t][31:0];
   res <= tests[t][63:32] << tests[t][31:0];
   if (t + 1 < `TESTS)
     t = t + 1;
   else begin

     t = 0;
     done = 1'b1;
   end
end



alu my_alu
(
  .clk(clk),
  .reset(reset),

  .i_a(alu_a),
  .i_b(alu_b),
  .i_cmd(alu_cmd),

  .o_result(alu_result),
  .o_valid(alu_res_valid),
  .o_ready(alu_ready)
);


sim my_sim(
  .clk(clk),
  .reset(reset)
);

endmodule