data/full_repos/permissive/477054115/Mips16_singlecycle/fourBitCounter.v
data/verilator_xmls/491a4e66-6bfc-4595-8ca0-bce25ae78b3f.xml
module counter(count,enable,clk,rst_n);  
  input enable,clk,rst_n;  
  output reg[3:0] count;  
  always @(posedge clk or negedge rst_n)  
  begin  
   if(~rst_n) count <= 4'b0000;  
   else if(enable)  
    count <= count + 4'b0001;  
  end
 endmodule
module counter(count,enable,clk,rst_n);
  
  input enable,clk,rst_n;  
  output reg[3:0] count;  
  always @(posedge clk or negedge rst_n)  
  begin  
   if(~rst_n) count <= 4'b0000;  
   else if(enable)  
    count <= count + 4'b0001;  
  end
 endmodule