data/full_repos/permissive/522145661/Test_TOP_MODULE.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_TOP_MODULE.v:45: Unsupported: Ignoring delay on this delayed statement.\n always #10 CLK=~CLK;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_TOP_MODULE.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_TOP_MODULE.v:148: Unsupported: Ignoring delay on this delayed statement.\n  #200 U1_REQ = 0; U1_LOCK = 0; U1_WRITE = 0; U1_ADDR = 12\'b0; U1_WDATA = 32\'b0; U1_SLAVE = 2\'b00;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_TOP_MODULE.v:150: Unsupported: Ignoring delay on this delayed statement.\n  #100 U1_REQ = 1; U1_LOCK = 0; U1_WRITE = 1; U1_ADDR = 12\'d9; U1_WDATA = $random; U1_SLAVE = 2\'b01;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_TOP_MODULE.v:152: Unsupported: Ignoring delay on this delayed statement.\n  #100 U1_REQ = 0; U1_LOCK = 0; U1_WRITE = 1; U1_ADDR = 12\'d9; U1_SLAVE = 2\'b01;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_TOP_MODULE.v:154: Unsupported: Ignoring delay on this delayed statement.\n  #200 U1_REQ = 0; U1_LOCK = 0; U1_WRITE = 0; U1_ADDR = 12\'d0; U1_WDATA = 32\'b0; U1_SLAVE = 2\'b00;    \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_TOP_MODULE.v:157: Unsupported: Ignoring delay on this delayed statement.\n  #100 U1_REQ = 1; U1_LOCK = 0; U1_WRITE = 0; U1_ADDR = 12\'d9;  U1_SLAVE = 2\'b01;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_TOP_MODULE.v:159: Unsupported: Ignoring delay on this delayed statement.\n  #100 U1_REQ = 0; U1_LOCK = 0; U1_WRITE = 0; U1_ADDR = 12\'d9;  U1_SLAVE = 2\'b01; U_SPLIT = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_TOP_MODULE.v:164: Unsupported: Ignoring delay on this delayed statement.\n   #200 U2_REQ = 0; U2_LOCK = 0; U2_WRITE = 0; U2_ADDR = 12\'b0; U2_WDATA = 32\'b0; U2_SLAVE = 2\'b00;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_TOP_MODULE.v:166: Unsupported: Ignoring delay on this delayed statement.\n   #100 U2_REQ = 1; U2_LOCK = 0; U2_WRITE = 1; U2_ADDR = 12\'d6; U2_WDATA = $random; U2_SLAVE = 2\'b10;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_TOP_MODULE.v:168: Unsupported: Ignoring delay on this delayed statement.\n   #100 U2_REQ = 0; U2_LOCK = 0; U2_WRITE = 1; U2_ADDR = 12\'d6; U2_SLAVE = 2\'b10;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_TOP_MODULE.v:170: Unsupported: Ignoring delay on this delayed statement.\n   #200 U2_REQ = 0; U2_LOCK = 0; U2_WRITE = 0; U2_ADDR = 12\'d0; U2_WDATA = 32\'b0; U2_SLAVE = 2\'b00;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_TOP_MODULE.v:174: Unsupported: Ignoring delay on this delayed statement.\n  #200 U1_REQ = 0; U1_LOCK = 0; U1_WRITE = 0; U1_ADDR = 12\'d9;  U1_SLAVE = 2\'b01; U_SPLIT = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_TOP_MODULE.v:176: Unsupported: Ignoring delay on this delayed statement.\n  #100 U1_REQ = 0; U1_LOCK = 0; U1_WRITE = 0; U1_ADDR = 12\'d9;  U1_SLAVE = 2\'b00;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_TOP_MODULE.v:178: Unsupported: Ignoring delay on this delayed statement.\n  #200 U1_REQ = 0; U2_REQ = 0; U1_LOCK = 0; U2_LOCK = 0; U1_WRITE = 0; U2_WRITE = 0; U1_ADDR = 12\'b0; \n  ^\n%Error: data/full_repos/permissive/522145661/Test_TOP_MODULE.v:26: Cannot find file containing module: \'TOP_MODULE\'\n TOP_MODULE uut (\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/522145661,data/full_repos/permissive/522145661/TOP_MODULE\n             data/full_repos/permissive/522145661,data/full_repos/permissive/522145661/TOP_MODULE.v\n             data/full_repos/permissive/522145661,data/full_repos/permissive/522145661/TOP_MODULE.sv\n             TOP_MODULE\n             TOP_MODULE.v\n             TOP_MODULE.sv\n             obj_dir/TOP_MODULE\n             obj_dir/TOP_MODULE.v\n             obj_dir/TOP_MODULE.sv\n%Error: Exiting due to 1 error(s), 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Test_TOP_MODULE;


	reg RST;
	reg CLK;
	reg U1_REQ;
	reg U1_LOCK;
	reg U1_WRITE;
	reg [11:0] U1_ADDR;
	reg [31:0] U1_WDATA;
	reg [1:0] U1_SLAVE;
	reg U2_REQ;
	reg U2_LOCK;
	reg U2_WRITE;
	reg [11:0] U2_ADDR;
	reg [31:0] U2_WDATA;
	reg [1:0] U2_SLAVE;
	reg U_SPLIT;


	wire AB;


	TOP_MODULE uut (
		.RST(RST), 
		.CLK(CLK), 
		.U1_REQ(U1_REQ), 
		.U1_LOCK(U1_LOCK), 
		.U1_WRITE(U1_WRITE), 
		.U1_ADDR(U1_ADDR), 
		.U1_WDATA(U1_WDATA), 
		.U1_SLAVE(U1_SLAVE), 
		.U2_REQ(U2_REQ), 
		.U2_LOCK(U2_LOCK), 
		.U2_WRITE(U2_WRITE), 
		.U2_ADDR(U2_ADDR), 
		.U2_WDATA(U2_WDATA), 
		.U2_SLAVE(U2_SLAVE), 
		.U_SPLIT(U_SPLIT), 
		.AB(AB)
	);
	
	always #10 CLK=~CLK;


	initial begin

		RST = 0;
		CLK = 0;
		U1_REQ = 0;
		U1_LOCK = 0;
		U1_WRITE = 0;
		U1_ADDR = 0;
		U1_WDATA = 0;
		U1_SLAVE = 0;
		U2_REQ = 0;
		U2_LOCK = 0;
		U2_WRITE = 0;
		U2_ADDR = 0;
		U2_WDATA = 0;
		U2_SLAVE = 0;
		U_SPLIT = 0;


		#100;
        

		

		

	








	

		#200 U1_REQ = 0; U1_LOCK = 0; U1_WRITE = 0; U1_ADDR = 12'b0; U1_WDATA = 32'b0; U1_SLAVE = 2'b00;
		
		#100 U1_REQ = 1; U1_LOCK = 0; U1_WRITE = 1; U1_ADDR = 12'd9; U1_WDATA = $random; U1_SLAVE = 2'b01;
		
		#100 U1_REQ = 0; U1_LOCK = 0; U1_WRITE = 1; U1_ADDR = 12'd9; U1_SLAVE = 2'b01;
			
		#200 U1_REQ = 0; U1_LOCK = 0; U1_WRITE = 0; U1_ADDR = 12'd0; U1_WDATA = 32'b0; U1_SLAVE = 2'b00; 		 
	

		#100 U1_REQ = 1; U1_LOCK = 0; U1_WRITE = 0; U1_ADDR = 12'd9;  U1_SLAVE = 2'b01;
				
		#100 U1_REQ = 0; U1_LOCK = 0; U1_WRITE = 0; U1_ADDR = 12'd9;  U1_SLAVE = 2'b01; U_SPLIT = 1;
		

		

			#200 U2_REQ = 0; U2_LOCK = 0; U2_WRITE = 0; U2_ADDR = 12'b0; U2_WDATA = 32'b0; U2_SLAVE = 2'b00;
			
			#100 U2_REQ = 1; U2_LOCK = 0; U2_WRITE = 1; U2_ADDR = 12'd6; U2_WDATA = $random; U2_SLAVE = 2'b10;
			
			#100 U2_REQ = 0; U2_LOCK = 0; U2_WRITE = 1; U2_ADDR = 12'd6; U2_SLAVE = 2'b10;
				
			#200 U2_REQ = 0; U2_LOCK = 0; U2_WRITE = 0; U2_ADDR = 12'd0; U2_WDATA = 32'b0; U2_SLAVE = 2'b00;
		

		
		#200 U1_REQ = 0; U1_LOCK = 0; U1_WRITE = 0; U1_ADDR = 12'd9;  U1_SLAVE = 2'b01; U_SPLIT = 0;
		
		#100 U1_REQ = 0; U1_LOCK = 0; U1_WRITE = 0; U1_ADDR = 12'd9;  U1_SLAVE = 2'b00;
	
		#200 U1_REQ = 0; U2_REQ = 0; U1_LOCK = 0; U2_LOCK = 0; U1_WRITE = 0; U2_WRITE = 0; U1_ADDR = 12'b0; 
			  U2_ADDR = 12'b0; U1_WDATA = 32'b0; U2_WDATA = 32'b0; U1_SLAVE = 2'b00; U2_SLAVE = 2'b00;
		



	end
      
endmodule
module Test_TOP_MODULE;



	reg RST;
	reg CLK;
	reg U1_REQ;
	reg U1_LOCK;
	reg U1_WRITE;
	reg [11:0] U1_ADDR;
	reg [31:0] U1_WDATA;
	reg [1:0] U1_SLAVE;
	reg U2_REQ;
	reg U2_LOCK;
	reg U2_WRITE;
	reg [11:0] U2_ADDR;
	reg [31:0] U2_WDATA;
	reg [1:0] U2_SLAVE;
	reg U_SPLIT;


	wire AB;


	TOP_MODULE uut (
		.RST(RST), 
		.CLK(CLK), 
		.U1_REQ(U1_REQ), 
		.U1_LOCK(U1_LOCK), 
		.U1_WRITE(U1_WRITE), 
		.U1_ADDR(U1_ADDR), 
		.U1_WDATA(U1_WDATA), 
		.U1_SLAVE(U1_SLAVE), 
		.U2_REQ(U2_REQ), 
		.U2_LOCK(U2_LOCK), 
		.U2_WRITE(U2_WRITE), 
		.U2_ADDR(U2_ADDR), 
		.U2_WDATA(U2_WDATA), 
		.U2_SLAVE(U2_SLAVE), 
		.U_SPLIT(U_SPLIT), 
		.AB(AB)
	);
	
	always #10 CLK=~CLK;


	initial begin

		RST = 0;
		CLK = 0;
		U1_REQ = 0;
		U1_LOCK = 0;
		U1_WRITE = 0;
		U1_ADDR = 0;
		U1_WDATA = 0;
		U1_SLAVE = 0;
		U2_REQ = 0;
		U2_LOCK = 0;
		U2_WRITE = 0;
		U2_ADDR = 0;
		U2_WDATA = 0;
		U2_SLAVE = 0;
		U_SPLIT = 0;


		#100;
        

		

		

	








	

		#200 U1_REQ = 0; U1_LOCK = 0; U1_WRITE = 0; U1_ADDR = 12'b0; U1_WDATA = 32'b0; U1_SLAVE = 2'b00;
		
		#100 U1_REQ = 1; U1_LOCK = 0; U1_WRITE = 1; U1_ADDR = 12'd9; U1_WDATA = $random; U1_SLAVE = 2'b01;
		
		#100 U1_REQ = 0; U1_LOCK = 0; U1_WRITE = 1; U1_ADDR = 12'd9; U1_SLAVE = 2'b01;
			
		#200 U1_REQ = 0; U1_LOCK = 0; U1_WRITE = 0; U1_ADDR = 12'd0; U1_WDATA = 32'b0; U1_SLAVE = 2'b00; 		 
	

		#100 U1_REQ = 1; U1_LOCK = 0; U1_WRITE = 0; U1_ADDR = 12'd9;  U1_SLAVE = 2'b01;
				
		#100 U1_REQ = 0; U1_LOCK = 0; U1_WRITE = 0; U1_ADDR = 12'd9;  U1_SLAVE = 2'b01; U_SPLIT = 1;
		

		

			#200 U2_REQ = 0; U2_LOCK = 0; U2_WRITE = 0; U2_ADDR = 12'b0; U2_WDATA = 32'b0; U2_SLAVE = 2'b00;
			
			#100 U2_REQ = 1; U2_LOCK = 0; U2_WRITE = 1; U2_ADDR = 12'd6; U2_WDATA = $random; U2_SLAVE = 2'b10;
			
			#100 U2_REQ = 0; U2_LOCK = 0; U2_WRITE = 1; U2_ADDR = 12'd6; U2_SLAVE = 2'b10;
				
			#200 U2_REQ = 0; U2_LOCK = 0; U2_WRITE = 0; U2_ADDR = 12'd0; U2_WDATA = 32'b0; U2_SLAVE = 2'b00;
		

		
		#200 U1_REQ = 0; U1_LOCK = 0; U1_WRITE = 0; U1_ADDR = 12'd9;  U1_SLAVE = 2'b01; U_SPLIT = 0;
		
		#100 U1_REQ = 0; U1_LOCK = 0; U1_WRITE = 0; U1_ADDR = 12'd9;  U1_SLAVE = 2'b00;
	
		#200 U1_REQ = 0; U2_REQ = 0; U1_LOCK = 0; U2_LOCK = 0; U1_WRITE = 0; U2_WRITE = 0; U1_ADDR = 12'b0; 
			  U2_ADDR = 12'b0; U1_WDATA = 32'b0; U2_WDATA = 32'b0; U1_SLAVE = 2'b00; U2_SLAVE = 2'b00;
		



	end
      
endmodule