data/full_repos/permissive/476477303/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/476477303/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n always #12.5 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v:62: syntax error, unexpected \'@\'\n  @(posedge nextTestOutput);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v:68: syntax error, unexpected \'@\'\n  @(posedge nextTestOutput);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v:71: syntax error, unexpected \'@\'\n  @(posedge nextTestOutput);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v:74: syntax error, unexpected \'@\'\n  @(posedge nextTestOutput);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v:79: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("peripheralsGPIO.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v:84: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(1, peripheralsGPIO_tb);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v:85: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(2, peripheralsGPIO_tb.uut.mprj);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v:90: syntax error, unexpected \'@\'\n   repeat (1000) @(posedge clock);\n                 ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v:105: Unsupported: wait statements\n  wait(outputTestData == 4\'b0000);\n  ^~~~\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v:106: Unsupported: wait statements\n  wait(outputTestData == 4\'b0001);\n  ^~~~\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v:107: Unsupported: wait statements\n  wait(outputTestData == 4\'b0011);\n  ^~~~\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v:108: Unsupported: wait statements\n  wait(outputTestData == 4\'b0111);\n  ^~~~\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v:109: Unsupported: wait statements\n  wait(outputTestData == 4\'b1111);\n  ^~~~\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v:110: Unsupported: wait statements\n  wait(outputTestData == 4\'b0000);\n  ^~~~\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v:111: Unsupported: wait statements\n  wait(outputTestData == 4\'b1111);\n  ^~~~\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v:112: Unsupported: wait statements\n  wait(outputTestData == 4\'b1110);\n  ^~~~\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v:113: Unsupported: wait statements\n  wait(outputTestData == 4\'b1100);\n  ^~~~\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v:114: Unsupported: wait statements\n  wait(outputTestData == 4\'b1000);\n  ^~~~\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v:115: Unsupported: wait statements\n  wait(outputTestData == 4\'b0000);\n  ^~~~\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v:118: syntax error, unexpected \'@\'\n  @(posedge nextTestOutput);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/476477303/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n  #2000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/476477303/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v:152: Unsupported: Ignoring delay on this delayed statement.\n  #300000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/476477303/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v:161: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/476477303/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v:163: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/476477303/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v:165: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/476477303/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v:167: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/476477303/verilog/dv/peripheralsGPIO/peripheralsGPIO_tb.v:172: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("Success:0b%b Next test:0b%b Output:0b%b Input:0b%b", succesOutput, nextTestOutput, outputTestData, inputTestData);\n  ^\n%Error: Exiting due to 20 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module peripheralsGPIO_tb;
	reg clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

	wire gpio;
	wire [37:0] mprj_io;

	reg[1:0] inputTestData;
	wire succesOutput = mprj_io[12];
	wire nextTestOutput = mprj_io[13];
	wire[3:0] outputTestData = mprj_io[17:14];


	pullup(mprj_io[3]);
	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
	
	assign mprj_io[20:19] = inputTestData;
	assign mprj_io[7] = 1'b1;


	assign mprj_io[2:0] = 3'b0;
	assign mprj_io[6:4] = 3'b0;
	assign mprj_io[11:8] = 4'b0;
	assign mprj_io[18] = 1'b0;
	assign mprj_io[37:21] = 17'b0;




	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
		inputTestData = 4'b0;
	end


	initial begin

		@(posedge nextTestOutput);


		@(posedge nextTestOutput);
		inputTestData = 2'b10;
		
		@(posedge nextTestOutput);
		inputTestData = 2'b01;
		
		@(posedge nextTestOutput);
		inputTestData = 2'b11;

		@(posedge nextTestOutput);
		inputTestData = 2'b00;
	end

	initial begin
		$dumpfile("peripheralsGPIO.vcd");

`ifdef SIM
		$dumpvars(0, peripheralsGPIO_tb);
`else
		$dumpvars(1, peripheralsGPIO_tb);
		$dumpvars(2, peripheralsGPIO_tb.uut.mprj);
`endif


		repeat (400) begin
			repeat (1000) @(posedge clock);

		end
		$display("%c[1;35m",27);
		`ifdef GL
			$display ("Monitor: Timeout, Peripherals GPIO Test (GL) Failed");
		`else
			$display ("Monitor: Timeout, Peripherals GPIO Test (RTL) Failed");
		`endif
		$display("%c[0m",27);
		$finish;
	end

	initial begin

		wait(outputTestData == 4'b0000);
		wait(outputTestData == 4'b0001);
		wait(outputTestData == 4'b0011);
		wait(outputTestData == 4'b0111);
		wait(outputTestData == 4'b1111);
		wait(outputTestData == 4'b0000);
		wait(outputTestData == 4'b1111);
		wait(outputTestData == 4'b1110);
		wait(outputTestData == 4'b1100);
		wait(outputTestData == 4'b1000);
		wait(outputTestData == 4'b0000);


		@(posedge nextTestOutput);
		@(posedge nextTestOutput);
		@(posedge nextTestOutput);
		@(posedge nextTestOutput);
		@(posedge nextTestOutput);


		@(posedge nextTestOutput);
		
		if (succesOutput) begin
			$display("%c[1;92m",27);
			`ifdef GL
				$display("Monitor: Peripherals GPIO Test (GL) Passed");
			`else
				$display("Monitor: Peripherals GPIO Test (RTL) Passed");
			`endif
			$display("%c[0m",27);
		end else begin
			$display("%c[1;31m",27);
			`ifdef GL
				$display ("Monitor: Peripherals GPIO Test (GL) Failed");
			`else
				$display ("Monitor: Peripherals GPIO Test (RTL) Failed");
			`endif
			$display("%c[0m",27);
		end
	    $finish;
	end

	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#300000;
		CSB = 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end

	always @(succesOutput, nextTestOutput, outputTestData, inputTestData) begin
		#1 $display("Success:0b%b Next test:0b%b Output:0b%b Input:0b%b", succesOutput, nextTestOutput, outputTestData, inputTestData);
	end

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3;
	wire VDD1V8;
	wire VSS;
	
	assign VDD3V3 = power1;
	assign VDD1V8 = power2;
	assign VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda1_2  (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock    (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("peripheralsGPIO.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule
module peripheralsGPIO_tb;

	reg clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

	wire gpio;
	wire [37:0] mprj_io;

	reg[1:0] inputTestData;
	wire succesOutput = mprj_io[12];
	wire nextTestOutput = mprj_io[13];
	wire[3:0] outputTestData = mprj_io[17:14];


	pullup(mprj_io[3]);
	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
	
	assign mprj_io[20:19] = inputTestData;
	assign mprj_io[7] = 1'b1;


	assign mprj_io[2:0] = 3'b0;
	assign mprj_io[6:4] = 3'b0;
	assign mprj_io[11:8] = 4'b0;
	assign mprj_io[18] = 1'b0;
	assign mprj_io[37:21] = 17'b0;




	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
		inputTestData = 4'b0;
	end


	initial begin

		@(posedge nextTestOutput);


		@(posedge nextTestOutput);
		inputTestData = 2'b10;
		
		@(posedge nextTestOutput);
		inputTestData = 2'b01;
		
		@(posedge nextTestOutput);
		inputTestData = 2'b11;

		@(posedge nextTestOutput);
		inputTestData = 2'b00;
	end

	initial begin
		$dumpfile("peripheralsGPIO.vcd");

`ifdef SIM
		$dumpvars(0, peripheralsGPIO_tb);
`else
		$dumpvars(1, peripheralsGPIO_tb);
		$dumpvars(2, peripheralsGPIO_tb.uut.mprj);
`endif


		repeat (400) begin
			repeat (1000) @(posedge clock);

		end
		$display("%c[1;35m",27);
		`ifdef GL
			$display ("Monitor: Timeout, Peripherals GPIO Test (GL) Failed");
		`else
			$display ("Monitor: Timeout, Peripherals GPIO Test (RTL) Failed");
		`endif
		$display("%c[0m",27);
		$finish;
	end

	initial begin

		wait(outputTestData == 4'b0000);
		wait(outputTestData == 4'b0001);
		wait(outputTestData == 4'b0011);
		wait(outputTestData == 4'b0111);
		wait(outputTestData == 4'b1111);
		wait(outputTestData == 4'b0000);
		wait(outputTestData == 4'b1111);
		wait(outputTestData == 4'b1110);
		wait(outputTestData == 4'b1100);
		wait(outputTestData == 4'b1000);
		wait(outputTestData == 4'b0000);


		@(posedge nextTestOutput);
		@(posedge nextTestOutput);
		@(posedge nextTestOutput);
		@(posedge nextTestOutput);
		@(posedge nextTestOutput);


		@(posedge nextTestOutput);
		
		if (succesOutput) begin
			$display("%c[1;92m",27);
			`ifdef GL
				$display("Monitor: Peripherals GPIO Test (GL) Passed");
			`else
				$display("Monitor: Peripherals GPIO Test (RTL) Passed");
			`endif
			$display("%c[0m",27);
		end else begin
			$display("%c[1;31m",27);
			`ifdef GL
				$display ("Monitor: Peripherals GPIO Test (GL) Failed");
			`else
				$display ("Monitor: Peripherals GPIO Test (RTL) Failed");
			`endif
			$display("%c[0m",27);
		end
	    $finish;
	end

	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#300000;
		CSB = 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end

	always @(succesOutput, nextTestOutput, outputTestData, inputTestData) begin
		#1 $display("Success:0b%b Next test:0b%b Output:0b%b Input:0b%b", succesOutput, nextTestOutput, outputTestData, inputTestData);
	end

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3;
	wire VDD1V8;
	wire VSS;
	
	assign VDD3V3 = power1;
	assign VDD1V8 = power2;
	assign VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda1_2  (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock    (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("peripheralsGPIO.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule