data/full_repos/permissive/509809169/Circuits/Sequential Logic/More Circuits/Rule 110.v
1: b'%Error: Cannot find file containing module: Logic/More\n        ... Looked in:\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/More\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/More.v\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/More.sv\n             Logic/More\n             Logic/More.v\n             Logic/More.sv\n             obj_dir/Logic/More\n             obj_dir/Logic/More.v\n             obj_dir/Logic/More.sv\n%Error: Cannot find file containing module: Circuits,data/full_repos/permissive/509809169\n%Error: Cannot find file containing module: data/full_repos/permissive/509809169/Circuits/Sequential\n%Error: Cannot find file containing module: Circuits/Rule\n%Error: Cannot find file containing module: 110.v\n%Error: Exiting due to 5 error(s)\n'
module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q
); 
    integer i;
    always @(posedge clk) begin
        if(load) q<=data;
        else begin
            q[511] <= (q[511]^q[510])|(~0&q[511]);
            for(i=510;i>0;i=i-1) begin
                q[i] <= (q[i]^q[i-1]) | (~q[i+1]&q[i]);
            end
            
            q[0] <= (q[0]^0)|(~q[1]&q[0]);
        end
    end

endmodule
module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q
);
 
    integer i;
    always @(posedge clk) begin
        if(load) q<=data;
        else begin
            q[511] <= (q[511]^q[510])|(~0&q[511]);
            for(i=510;i>0;i=i-1) begin
                q[i] <= (q[i]^q[i-1]) | (~q[i+1]&q[i]);
            end
            
            q[0] <= (q[0]^0)|(~q[1]&q[0]);
        end
    end

endmodule