data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_stride.sv
1: b'%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_stride.sv:1: Cannot find include file: VX_tex_define.vh\n`include "VX_tex_define.vh" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/473423187/hw/rtl/tex_unit,data/full_repos/permissive/473423187/VX_tex_define.vh\n             data/full_repos/permissive/473423187/hw/rtl/tex_unit,data/full_repos/permissive/473423187/VX_tex_define.vh.v\n             data/full_repos/permissive/473423187/hw/rtl/tex_unit,data/full_repos/permissive/473423187/VX_tex_define.vh.sv\n             VX_tex_define.vh\n             VX_tex_define.vh.v\n             VX_tex_define.vh.sv\n             obj_dir/VX_tex_define.vh\n             obj_dir/VX_tex_define.vh.v\n             obj_dir/VX_tex_define.vh.sv\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_stride.sv:6: Define or directive not defined: \'`TEX_FORMAT_BITS\'\n    input wire [`TEX_FORMAT_BITS-1:0]  format,\n                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_stride.sv:7: Define or directive not defined: \'`TEX_STRIDE_BITS\'\n    output wire [`TEX_STRIDE_BITS-1:0] log_stride\n                 ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_stride.sv:9: Define or directive not defined: \'`UNUSED_PARAM\'\n    `UNUSED_PARAM (CORE_ID)\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_stride.sv:9: syntax error, unexpected \'(\'\n    `UNUSED_PARAM (CORE_ID)\n                   ^~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_stride.sv:11: Define or directive not defined: \'`TEX_STRIDE_BITS\'\n    reg [`TEX_STRIDE_BITS-1:0] log_stride_r;  \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_stride.sv:15: Define or directive not defined: \'`TEX_FORMAT_A8\'\n            `TEX_FORMAT_A8:       log_stride_r = 0;\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_stride.sv:15: syntax error, unexpected \':\', expecting endcase\n            `TEX_FORMAT_A8:       log_stride_r = 0;\n                          ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_stride.sv:16: Define or directive not defined: \'`TEX_FORMAT_L8\'\n            `TEX_FORMAT_L8:       log_stride_r = 0;\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_stride.sv:17: Define or directive not defined: \'`TEX_FORMAT_L8A8\'\n            `TEX_FORMAT_L8A8:     log_stride_r = 1;\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_stride.sv:18: Define or directive not defined: \'`TEX_FORMAT_R5G6B5\'\n            `TEX_FORMAT_R5G6B5:   log_stride_r = 1;\n            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/tex_unit/VX_tex_stride.sv:19: Define or directive not defined: \'`TEX_FORMAT_R4G4B4A4\'\n            `TEX_FORMAT_R4G4B4A4: log_stride_r = 1;\n            ^~~~~~~~~~~~~~~~~~~~\n%Error: Cannot continue\n'
module VX_tex_stride #(
    parameter CORE_ID = 0
) (
    input wire [`TEX_FORMAT_BITS-1:0]  format,
    output wire [`TEX_STRIDE_BITS-1:0] log_stride
);  
    `UNUSED_PARAM (CORE_ID)

    reg [`TEX_STRIDE_BITS-1:0] log_stride_r;  

    always @(*) begin
        case (format)
            `TEX_FORMAT_A8:       log_stride_r = 0;
            `TEX_FORMAT_L8:       log_stride_r = 0;
            `TEX_FORMAT_L8A8:     log_stride_r = 1;
            `TEX_FORMAT_R5G6B5:   log_stride_r = 1;
            `TEX_FORMAT_R4G4B4A4: log_stride_r = 1;

            default:              log_stride_r = 2;
        endcase
    end

    assign log_stride = log_stride_r;

endmodule
module VX_tex_stride #(
    parameter CORE_ID = 0
) (
    input wire [`TEX_FORMAT_BITS-1:0]  format,
    output wire [`TEX_STRIDE_BITS-1:0] log_stride
);
  
    `UNUSED_PARAM (CORE_ID)

    reg [`TEX_STRIDE_BITS-1:0] log_stride_r;  

    always @(*) begin
        case (format)
            `TEX_FORMAT_A8:       log_stride_r = 0;
            `TEX_FORMAT_L8:       log_stride_r = 0;
            `TEX_FORMAT_L8A8:     log_stride_r = 1;
            `TEX_FORMAT_R5G6B5:   log_stride_r = 1;
            `TEX_FORMAT_R4G4B4A4: log_stride_r = 1;

            default:              log_stride_r = 2;
        endcase
    end

    assign log_stride = log_stride_r;

endmodule