data/full_repos/permissive/424312442/HW3/Question 1/HW3_1.v
1: b'%Error: Cannot find file containing module: 1,data/full_repos/permissive/424312442\n        ... Looked in:\n             data/full_repos/permissive/424312442/HW3/Question/1,data/full_repos/permissive/424312442\n             data/full_repos/permissive/424312442/HW3/Question/1,data/full_repos/permissive/424312442.v\n             data/full_repos/permissive/424312442/HW3/Question/1,data/full_repos/permissive/424312442.sv\n             1,data/full_repos/permissive/424312442\n             1,data/full_repos/permissive/424312442.v\n             1,data/full_repos/permissive/424312442.sv\n             obj_dir/1,data/full_repos/permissive/424312442\n             obj_dir/1,data/full_repos/permissive/424312442.v\n             obj_dir/1,data/full_repos/permissive/424312442.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/424312442/HW3/Question\n%Error: Cannot find file containing module: 1/HW3_1.v\n%Error: Exiting due to 3 error(s)\n'
module hw_3_1_tb;
reg clk = 0;
reg S0 = 0;
reg S1 = 0;
reg SP = 0;
reg AR = 0;
reg D = 0;
reg BUF_OUT = 0;
wire OUT, FB;

always begin
clk = !clk;
#5;
end

HW3 dut(clk, S0, S1, SP, AR, D, BUF_OUT, OUT, FB);

initial begin
#10;
D = 1; S1 = 1;
#5;
S0 = 1;
#15;
S0 = 0; S1 = 0;
#5;
D = 0;
#12;
SP = 1;
#7;
AR = 1;
#6;
S0 = 1;

end
endmodule
module hw_3_1_tb;

reg clk = 0;
reg S0 = 0;
reg S1 = 0;
reg SP = 0;
reg AR = 0;
reg D = 0;
reg BUF_OUT = 0;
wire OUT, FB;

always begin
clk = !clk;
#5;
end

HW3 dut(clk, S0, S1, SP, AR, D, BUF_OUT, OUT, FB);

initial begin
#10;
D = 1; S1 = 1;
#5;
S0 = 1;
#15;
S0 = 0; S1 = 0;
#5;
D = 0;
#12;
SP = 1;
#7;
AR = 1;
#6;
S0 = 1;

end
endmodule