data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/VGA.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/VGA.v:75: Signal definition not found, creating implicitly: \'clk_25\'\nalways @(posedge clk_25) \n                 ^~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/VGA.v:46: Cannot find file containing module: \'clk_wiz_0\'\nclk_wiz_0 divider(.clk_in1(clk_100),.clk_out1(clk_25));\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new,data/full_repos/permissive/432862802/clk_wiz_0\n             data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new,data/full_repos/permissive/432862802/clk_wiz_0.v\n             data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new,data/full_repos/permissive/432862802/clk_wiz_0.sv\n             clk_wiz_0\n             clk_wiz_0.v\n             clk_wiz_0.sv\n             obj_dir/clk_wiz_0\n             obj_dir/clk_wiz_0.v\n             obj_dir/clk_wiz_0.sv\n%Error: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/VGA.v:104: Cannot find file containing module: \'Pixel_Mapping\'\nPixel_Mapping p_m_inst(\n^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module VGA(
    input clk_100,

    input [1:0] state,

    input [3:0] note_0,
    input [3:0] note_1,
    input [3:0] note_2,
    input [3:0] note_3,
    input [1:0] octave_0,
    input [1:0] octave_1,
    input [1:0] octave_2,
    input [1:0] octave_3,
    input [11:0] pwm_level,

    output [3:0] R_OUT,
    output [3:0] G_OUT,
    output [3:0] B_OUT,
    output reg hsync,
    output reg vsync
    );


clk_wiz_0 divider(.clk_in1(clk_100),.clk_out1(clk_25));


localparam VISIBLE_HORIZONTAL = 640;
localparam FRONT_H = 16;
localparam SYNC_H = 96;
localparam BACK_H = 48; 



localparam TOTAL_H = VISIBLE_HORIZONTAL+FRONT_H+SYNC_H+BACK_H;
localparam VISIBLE_VERTICAL = 480;
localparam FRONT_V = 10;
localparam SYNC_V = 2;
localparam BACK_V = 33;


localparam TOTAL_V = VISIBLE_VERTICAL+FRONT_V+SYNC_V+BACK_V;

(*dont_touch = "true"*) reg [10:0] hcount = 11'd0;
(*dont_touch = "true"*) reg [10:0] vcount = 11'd0;


always @(posedge clk_25) 
begin
    if(hcount == TOTAL_H-1)
    begin
        hcount <= 0;
        if(vcount == TOTAL_V-1)
            vcount <=0;
        else begin
            vcount <= vcount + 1'b1;
        end
    end
    else begin
        hcount <= hcount + 1'b1;
    end

    if (vcount < SYNC_V)
        vsync <= 1'b0;
    else begin
        vsync <= 1'b1;
    end

    if (hcount < SYNC_H)
        hsync <= 1'b0;
    else begin
        hsync <= 1'b1;
    end
end


Pixel_Mapping p_m_inst(
    .clk_25(clk_25),
    .state(state),
    .hcount(hcount),
    .vcount(vcount),
    .note_0(note_0),
    .note_1(note_1),
    .note_2(note_2),
    .note_3(note_3),
    .octave_0(octave_0),
    .octave_1(octave_1),
    .octave_2(octave_2),
    .octave_3(octave_3),
    .pwm_level(pwm_level),
    .R_OUT(R_OUT),
    .G_OUT(G_OUT),
    .B_OUT(B_OUT));

endmodule
module VGA(
    input clk_100,

    input [1:0] state,

    input [3:0] note_0,
    input [3:0] note_1,
    input [3:0] note_2,
    input [3:0] note_3,
    input [1:0] octave_0,
    input [1:0] octave_1,
    input [1:0] octave_2,
    input [1:0] octave_3,
    input [11:0] pwm_level,

    output [3:0] R_OUT,
    output [3:0] G_OUT,
    output [3:0] B_OUT,
    output reg hsync,
    output reg vsync
    );



clk_wiz_0 divider(.clk_in1(clk_100),.clk_out1(clk_25));


localparam VISIBLE_HORIZONTAL = 640;
localparam FRONT_H = 16;
localparam SYNC_H = 96;
localparam BACK_H = 48; 



localparam TOTAL_H = VISIBLE_HORIZONTAL+FRONT_H+SYNC_H+BACK_H;
localparam VISIBLE_VERTICAL = 480;
localparam FRONT_V = 10;
localparam SYNC_V = 2;
localparam BACK_V = 33;


localparam TOTAL_V = VISIBLE_VERTICAL+FRONT_V+SYNC_V+BACK_V;

(*dont_touch = "true"*) reg [10:0] hcount = 11'd0;
(*dont_touch = "true"*) reg [10:0] vcount = 11'd0;


always @(posedge clk_25) 
begin
    if(hcount == TOTAL_H-1)
    begin
        hcount <= 0;
        if(vcount == TOTAL_V-1)
            vcount <=0;
        else begin
            vcount <= vcount + 1'b1;
        end
    end
    else begin
        hcount <= hcount + 1'b1;
    end

    if (vcount < SYNC_V)
        vsync <= 1'b0;
    else begin
        vsync <= 1'b1;
    end

    if (hcount < SYNC_H)
        hsync <= 1'b0;
    else begin
        hsync <= 1'b1;
    end
end


Pixel_Mapping p_m_inst(
    .clk_25(clk_25),
    .state(state),
    .hcount(hcount),
    .vcount(vcount),
    .note_0(note_0),
    .note_1(note_1),
    .note_2(note_2),
    .note_3(note_3),
    .octave_0(octave_0),
    .octave_1(octave_1),
    .octave_2(octave_2),
    .octave_3(octave_3),
    .pwm_level(pwm_level),
    .R_OUT(R_OUT),
    .G_OUT(G_OUT),
    .B_OUT(B_OUT));

endmodule