data/full_repos/permissive/459277146/adder.v
data/verilator_xmls/737f953d-9c5a-43db-b8ec-0e528daccd8b.xml
module adder #(parameter DWIDTH = 8)(in1, in2, carry_in, sum, carry_out);

input [DWIDTH - 1:0] in1;
input [DWIDTH - 1:0] in2;
input carry_in;
output [DWIDTH - 1:0] sum;
output carry_out;



wire [DWIDTH - 1:0] gen;
wire [DWIDTH - 1:0] pro;
wire [DWIDTH:0] carry_tmp;

genvar j, i;
generate

 assign carry_tmp[0] = carry_in;
 

 for(j = 0; j < DWIDTH; j = j + 1) begin: carry_generator
 assign gen[j] = in1[j] & in2[j];
 assign pro[j] = in1[j] | in2[j];
 assign carry_tmp[j+1] = gen[j] | pro[j] & carry_tmp[j];
 end
 

 assign carry_out = carry_tmp[DWIDTH];
 


 for(i = 0; i < DWIDTH; i = i+1) begin: sum_without_carry
 assign sum[i] = in1[i] ^ in2[i] ^ carry_tmp[i];
 end 
endgenerate 
endmodule
module adder #(parameter DWIDTH = 8)(in1, in2, carry_in, sum, carry_out);


input [DWIDTH - 1:0] in1;
input [DWIDTH - 1:0] in2;
input carry_in;
output [DWIDTH - 1:0] sum;
output carry_out;



wire [DWIDTH - 1:0] gen;
wire [DWIDTH - 1:0] pro;
wire [DWIDTH:0] carry_tmp;

genvar j, i;
generate

 assign carry_tmp[0] = carry_in;
 

 for(j = 0; j < DWIDTH; j = j + 1) begin: carry_generator
 assign gen[j] = in1[j] & in2[j];
 assign pro[j] = in1[j] | in2[j];
 assign carry_tmp[j+1] = gen[j] | pro[j] & carry_tmp[j];
 end
 

 assign carry_out = carry_tmp[DWIDTH];
 


 for(i = 0; i < DWIDTH; i = i+1) begin: sum_without_carry
 assign sum[i] = in1[i] ^ in2[i] ^ carry_tmp[i];
 end 
endgenerate 
endmodule