data/full_repos/permissive/46343463/src/Dram_TestBench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/46343463/src/Dram_TestBench.v:11: Unsupported: Ignoring delay on this delayed statement.\n always #(100/2) clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/46343463/src/Dram_TestBench.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #(100/4)\n  ^\n%Error: data/full_repos/permissive/46343463/src/Dram_TestBench.v:28: Unsupported: fork statements\n  fork   \n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/46343463/src/Dram_TestBench.v:29: Unsupported: Ignoring delay on this delayed statement.\n      #0\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/46343463/src/Dram_TestBench.v:34: Unsupported: Ignoring delay on this delayed statement.\n      #1 \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/46343463/src/Dram_TestBench.v:39: Unsupported: Ignoring delay on this delayed statement.\n   #1\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/46343463/src/Dram_TestBench.v:42: Unsupported: Ignoring delay on this delayed statement.\n      #20\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/46343463/src/Dram_TestBench.v:45: Unsupported: Ignoring delay on this delayed statement.\n      #21\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/46343463/src/Dram_TestBench.v:47: Unsupported: Ignoring delay on this delayed statement.\n      #35\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/46343463/src/Dram_TestBench.v:52: Unsupported: Ignoring delay on this delayed statement.\n   #36\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/46343463/src/Dram_TestBench.v:56: Unsupported: Ignoring delay on this delayed statement.\n   #50\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/46343463/src/Dram_TestBench.v:59: Unsupported: Ignoring delay on this delayed statement.\n      #51\n      ^\n%Error: Exiting due to 1 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Dram_Testbench;

	reg 	[31:0]		data_i;
	reg		[31:0]		addr_i;
	reg 	clk, cs, we;
	wire				ack;
	wire 	[31:0]		data_o;

	always #(`CYCLE_TIME/2) clk = ~clk;

	DRAM #(.delay(10)) dram(
		.clk(clk),
		.addr_i(addr_i),
		.cs(cs),
		.we(we),
		.data_i(data_i),
		.data_o(data_o),
		.ack(ack)
	);

	initial begin		
		#(`CYCLE_TIME/4)

		clk = 0;

		fork   
	    	#0
	    		addr_i = 32'd0;
				data_i = 32'd0;
				cs = 0;
				we = 0;
	    	#1	
	    		addr_i = 32'd2;
				data_i = 32'd10;
				cs = 1;
				we = 1;
			#1
				cs = 0;
				we = 0;
		    #20
		    	addr_i = 32'd2;
		    	cs = 1;
		    #21
		    	cs = 0;
		    #35
		    	addr_i = 32'd2;
				data_i = 32'd120;
				cs = 1;
				we = 1;
			#36
				cs = 0;
				we = 0;

			#50
				addr_i = 32'd2;
		    	cs = 1;
		    #51
		    	cs = 0;
		join
	end

endmodule
module Dram_Testbench;


	reg 	[31:0]		data_i;
	reg		[31:0]		addr_i;
	reg 	clk, cs, we;
	wire				ack;
	wire 	[31:0]		data_o;

	always #(`CYCLE_TIME/2) clk = ~clk;

	DRAM #(.delay(10)) dram(
		.clk(clk),
		.addr_i(addr_i),
		.cs(cs),
		.we(we),
		.data_i(data_i),
		.data_o(data_o),
		.ack(ack)
	);

	initial begin		
		#(`CYCLE_TIME/4)

		clk = 0;

		fork   
	    	#0
	    		addr_i = 32'd0;
				data_i = 32'd0;
				cs = 0;
				we = 0;
	    	#1	
	    		addr_i = 32'd2;
				data_i = 32'd10;
				cs = 1;
				we = 1;
			#1
				cs = 0;
				we = 0;
		    #20
		    	addr_i = 32'd2;
		    	cs = 1;
		    #21
		    	cs = 0;
		    #35
		    	addr_i = 32'd2;
				data_i = 32'd120;
				cs = 1;
				we = 1;
			#36
				cs = 0;
				we = 0;

			#50
				addr_i = 32'd2;
		    	cs = 1;
		    #51
		    	cs = 0;
		join
	end

endmodule