data/full_repos/permissive/494905093/PUF/ROPUF/TIME.v
data/verilator_xmls/a8691033-23ac-4da1-af79-52829443efdf.xml
module Time(clk,reset,CLK, CLK2);
    input clk,reset;
    output reg CLK, CLK2;
    reg [26:0]Count;
    
    always @(posedge clk or posedge reset) begin

        if (reset) begin
            Count <= 27'd0;
            CLK <= 1'b0; 
            CLK2 <= 1'b0;
        end
        

        
        else begin
            Count <= Count+27'd1; 
            CLK2 <= Count[5];
            CLK <= Count[26];
        end

    end

endmodule
module Time(clk,reset,CLK, CLK2);

    input clk,reset;
    output reg CLK, CLK2;
    reg [26:0]Count;
    
    always @(posedge clk or posedge reset) begin

        if (reset) begin
            Count <= 27'd0;
            CLK <= 1'b0; 
            CLK2 <= 1'b0;
        end
        

        
        else begin
            Count <= Count+27'd1; 
            CLK2 <= Count[5];
            CLK <= Count[26];
        end

    end

endmodule