data/full_repos/permissive/495910568/rtl/adjustable_frequency_divider/test.v
1: b'%Error: data/full_repos/permissive/495910568/rtl/adjustable_frequency_divider/test.v:2: Cannot find include file: adjustable_frequency_divider.v\n`include "adjustable_frequency_divider.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/495910568/rtl/adjustable_frequency_divider,data/full_repos/permissive/495910568/adjustable_frequency_divider.v\n             data/full_repos/permissive/495910568/rtl/adjustable_frequency_divider,data/full_repos/permissive/495910568/adjustable_frequency_divider.v.v\n             data/full_repos/permissive/495910568/rtl/adjustable_frequency_divider,data/full_repos/permissive/495910568/adjustable_frequency_divider.v.sv\n             adjustable_frequency_divider.v\n             adjustable_frequency_divider.v.v\n             adjustable_frequency_divider.v.sv\n             obj_dir/adjustable_frequency_divider.v\n             obj_dir/adjustable_frequency_divider.v.v\n             obj_dir/adjustable_frequency_divider.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/495910568/rtl/adjustable_frequency_divider/test.v:26: Unsupported: Ignoring delay on this delayed statement.\n            forever #10 clock_in = ~clock_in;\n                    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/495910568/rtl/adjustable_frequency_divider/test.v:33: Unsupported: Ignoring delay on this delayed statement.\n            #20 nreset = 1\'b1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/495910568/rtl/adjustable_frequency_divider/test.v:35: Unsupported: Ignoring delay on this delayed statement.\n                  #500 step_divisor = ~step_divisor;\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/495910568/rtl/adjustable_frequency_divider/test.v:36: Unsupported: Ignoring delay on this delayed statement.\n                  #5 step_divisor = ~step_divisor;\n                  ^\n%Error: data/full_repos/permissive/495910568/rtl/adjustable_frequency_divider/test.v:43: Unsupported or unknown PLI call: $dumpvars\n            $dumpvars;\n            ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/495910568/rtl/adjustable_frequency_divider/test.v:44: Unsupported: Ignoring delay on this delayed statement.\n            #50000 nreset = 1\'b0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/495910568/rtl/adjustable_frequency_divider/test.v:45: Unsupported: Ignoring delay on this delayed statement.\n            #50 nreset = 1\'b1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/495910568/rtl/adjustable_frequency_divider/test.v:46: Unsupported: Ignoring delay on this delayed statement.\n            #100000 $finish;\n            ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n'
module test;

      reg clock_in;
      reg nreset;
      reg step_divisor;


      wire clock_out;


      adjustable_frequency_divider uut (
            .clock_in(clock_in), 
            .clock_out(clock_out),
            .nreset(nreset),
            .step_divisor(step_divisor)
      );
      initial begin

            clock_in = 0;

            forever #10 clock_in = ~clock_in;
      end


      initial begin
            nreset = 1'b0;
            step_divisor = 1'b0;
            #20 nreset = 1'b1;
            forever begin
                  #500 step_divisor = ~step_divisor;
                  #5 step_divisor = ~step_divisor;
            end

      end

      initial begin

            $dumpvars;
            #50000 nreset = 1'b0;
            #50 nreset = 1'b1;
            #100000 $finish;
      end

endmodule
module test;


      reg clock_in;
      reg nreset;
      reg step_divisor;


      wire clock_out;


      adjustable_frequency_divider uut (
            .clock_in(clock_in), 
            .clock_out(clock_out),
            .nreset(nreset),
            .step_divisor(step_divisor)
      );
      initial begin

            clock_in = 0;

            forever #10 clock_in = ~clock_in;
      end


      initial begin
            nreset = 1'b0;
            step_divisor = 1'b0;
            #20 nreset = 1'b1;
            forever begin
                  #500 step_divisor = ~step_divisor;
                  #5 step_divisor = ~step_divisor;
            end

      end

      initial begin

            $dumpvars;
            #50000 nreset = 1'b0;
            #50 nreset = 1'b1;
            #100000 $finish;
      end

endmodule