data/full_repos/permissive/518460376/verilog/rtl/rtl/mba_sp_ram_wrap.v
1: b'%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/rtl/mba_sp_ram_wrap.v:85: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_i\' generates 15 bits.\n                                                                                         : ... In instance mba_sp_ram_wrap\nassign mba_mem_addr0_o  = addr_i;\n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/rtl/mba_sp_ram_wrap.v:89: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'addr_i\' generates 15 bits.\n                                                                                         : ... In instance mba_sp_ram_wrap\nassign mba_mem_addr1_o = addr_i;\n                       ^\n%Error: Exiting due to 2 warning(s)\n'
module mba_sp_ram_wrap 
#(
    parameter RAM_SIZE   = 32768,
    parameter ADDR_WIDTH = $clog2(RAM_SIZE),
    parameter DATA_WIDTH = 32
  )
(




	clk,
	rstn_i,
	en_i,
	addr_i,
	wdata_i,
	rdata_o,
	we_i,
	be_i,
	bypass_en_i,

	mba_mem_csb0_o		,
	mba_mem_web0_o		,
	mba_mem_wmask0_o	,
	mba_mem_addr0_o		,
	mba_mem_din0_o		,
	mba_mem_dout0_i		,
	mba_mem_csb1_o		,
	mba_mem_addr1_o		

);








output wire 		mba_mem_csb0_o;
output wire 		mba_mem_web0_o;
output wire [3:0]	mba_mem_wmask0_o;
output wire [31:0]	mba_mem_addr0_o;
output wire [31:0] 	mba_mem_din0_o;
input  wire [31:0] 	mba_mem_dout0_i;
output wire 		mba_mem_csb1_o;
output wire [31:0] 	mba_mem_addr1_o;

	input wire clk;
	input wire rstn_i;
	input wire en_i;
	input wire [ADDR_WIDTH - 1:0] addr_i;
	input wire [DATA_WIDTH - 1:0] wdata_i;
	output wire [DATA_WIDTH - 1:0] rdata_o;
	input wire we_i;
	input wire [(DATA_WIDTH / 8) - 1:0] be_i;
	input wire bypass_en_i;
	wire [31:0] ram_out_int;
	assign rdata_o = ram_out_int;




















assign mba_mem_csb0_o 	= 1'b0;
assign mba_mem_web0_o	= ~(we_i & ~bypass_en_i);	
assign mba_mem_wmask0_o	= be_i;
assign mba_mem_addr0_o  = addr_i;
assign mba_mem_din0_o   = wdata_i;
assign ram_out_int 		= mba_mem_dout0_i;
assign mba_mem_csb1_o	= 1'b1;
assign mba_mem_addr1_o	= addr_i;



endmodule
module mba_sp_ram_wrap 
#(
    parameter RAM_SIZE   = 32768,
    parameter ADDR_WIDTH = $clog2(RAM_SIZE),
    parameter DATA_WIDTH = 32
  )
(




	clk,
	rstn_i,
	en_i,
	addr_i,
	wdata_i,
	rdata_o,
	we_i,
	be_i,
	bypass_en_i,

	mba_mem_csb0_o		,
	mba_mem_web0_o		,
	mba_mem_wmask0_o	,
	mba_mem_addr0_o		,
	mba_mem_din0_o		,
	mba_mem_dout0_i		,
	mba_mem_csb1_o		,
	mba_mem_addr1_o		

);









output wire 		mba_mem_csb0_o;
output wire 		mba_mem_web0_o;
output wire [3:0]	mba_mem_wmask0_o;
output wire [31:0]	mba_mem_addr0_o;
output wire [31:0] 	mba_mem_din0_o;
input  wire [31:0] 	mba_mem_dout0_i;
output wire 		mba_mem_csb1_o;
output wire [31:0] 	mba_mem_addr1_o;

	input wire clk;
	input wire rstn_i;
	input wire en_i;
	input wire [ADDR_WIDTH - 1:0] addr_i;
	input wire [DATA_WIDTH - 1:0] wdata_i;
	output wire [DATA_WIDTH - 1:0] rdata_o;
	input wire we_i;
	input wire [(DATA_WIDTH / 8) - 1:0] be_i;
	input wire bypass_en_i;
	wire [31:0] ram_out_int;
	assign rdata_o = ram_out_int;




















assign mba_mem_csb0_o 	= 1'b0;
assign mba_mem_web0_o	= ~(we_i & ~bypass_en_i);	
assign mba_mem_wmask0_o	= be_i;
assign mba_mem_addr0_o  = addr_i;
assign mba_mem_din0_o   = wdata_i;
assign ram_out_int 		= mba_mem_dout0_i;
assign mba_mem_csb1_o	= 1'b1;
assign mba_mem_addr1_o	= addr_i;



endmodule