data/full_repos/permissive/469509877/rtl/TopStateMachine.v
1: b"%Error: data/full_repos/permissive/469509877/rtl/TopStateMachine.v:41: Cannot find file containing module: 'TopStateMachineLogic'\n    TopStateMachineLogic TopStateMachineLogic (.clk(clk), .btnUDLR(btnUDLR), .btnC(btnC), .WinDetect(WinDetect), .LossDetect(LossDetect), .Q(Q), .reset(reset),\n    ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/469509877/rtl,data/full_repos/permissive/469509877/TopStateMachineLogic\n             data/full_repos/permissive/469509877/rtl,data/full_repos/permissive/469509877/TopStateMachineLogic.v\n             data/full_repos/permissive/469509877/rtl,data/full_repos/permissive/469509877/TopStateMachineLogic.sv\n             TopStateMachineLogic\n             TopStateMachineLogic.v\n             TopStateMachineLogic.sv\n             obj_dir/TopStateMachineLogic\n             obj_dir/TopStateMachineLogic.v\n             obj_dir/TopStateMachineLogic.sv\n%Error: data/full_repos/permissive/469509877/rtl/TopStateMachine.v:45: Cannot find file containing module: 'FDRE'\n        FDRE #(.INIT(1'b1)) Q0_FF (.C(clk), .CE(1'b1), .D(D[0]), .Q(Q[0]));\n        ^~~~\n%Error: data/full_repos/permissive/469509877/rtl/TopStateMachine.v:46: Cannot find file containing module: 'FDRE'\n        FDRE #(.INIT(1'b0)) Q1_FF (.C(clk), .CE(1'b1), .D(D[1]), .Q(Q[1]));\n        ^~~~\n%Error: data/full_repos/permissive/469509877/rtl/TopStateMachine.v:47: Cannot find file containing module: 'FDRE'\n        FDRE #(.INIT(1'b0)) Q2_FF (.C(clk), .CE(1'b1), .D(D[2]), .Q(Q[2]));\n        ^~~~\n%Error: data/full_repos/permissive/469509877/rtl/TopStateMachine.v:48: Cannot find file containing module: 'FDRE'\n        FDRE #(.INIT(1'b0)) Q3_FF (.C(clk), .CE(1'b1), .D(D[3]), .Q(Q[3]));\n        ^~~~\n%Error: Exiting due to 5 error(s)\n"
module TopStateMachine(
    input clk,
    input btnUDLR,
    input btnC,
    input WinDetect,
    input LossDetect,
    output reset,
    output btnCenable,
    output btnUDLRenable,
    output TimerEnable,
    output flashSlug,
    output flashBorder,
    output [3:0] state
    );
    
    wire [3:0] Q;
    wire [3:0] D;
    
    TopStateMachineLogic TopStateMachineLogic (.clk(clk), .btnUDLR(btnUDLR), .btnC(btnC), .WinDetect(WinDetect), .LossDetect(LossDetect), .Q(Q), .reset(reset),
                                               .btnCenable(btnCenable), .btnUDLRenable(btnUDLRenable), .TimerEnable(TimerEnable), .flashSlug(flashSlug),
                                               .flashBorder(flashBorder), .D(D));
    
        FDRE #(.INIT(1'b1)) Q0_FF (.C(clk), .CE(1'b1), .D(D[0]), .Q(Q[0]));
        FDRE #(.INIT(1'b0)) Q1_FF (.C(clk), .CE(1'b1), .D(D[1]), .Q(Q[1]));
        FDRE #(.INIT(1'b0)) Q2_FF (.C(clk), .CE(1'b1), .D(D[2]), .Q(Q[2]));
        FDRE #(.INIT(1'b0)) Q3_FF (.C(clk), .CE(1'b1), .D(D[3]), .Q(Q[3]));
        
        assign state[0] = Q[0];
        assign state[1] = Q[1];
        assign state[2] = Q[2];
        assign state[3] = Q[3];
        
endmodule
module TopStateMachine(
    input clk,
    input btnUDLR,
    input btnC,
    input WinDetect,
    input LossDetect,
    output reset,
    output btnCenable,
    output btnUDLRenable,
    output TimerEnable,
    output flashSlug,
    output flashBorder,
    output [3:0] state
    );

    
    wire [3:0] Q;
    wire [3:0] D;
    
    TopStateMachineLogic TopStateMachineLogic (.clk(clk), .btnUDLR(btnUDLR), .btnC(btnC), .WinDetect(WinDetect), .LossDetect(LossDetect), .Q(Q), .reset(reset),
                                               .btnCenable(btnCenable), .btnUDLRenable(btnUDLRenable), .TimerEnable(TimerEnable), .flashSlug(flashSlug),
                                               .flashBorder(flashBorder), .D(D));
    
        FDRE #(.INIT(1'b1)) Q0_FF (.C(clk), .CE(1'b1), .D(D[0]), .Q(Q[0]));
        FDRE #(.INIT(1'b0)) Q1_FF (.C(clk), .CE(1'b1), .D(D[1]), .Q(Q[1]));
        FDRE #(.INIT(1'b0)) Q2_FF (.C(clk), .CE(1'b1), .D(D[2]), .Q(Q[2]));
        FDRE #(.INIT(1'b0)) Q3_FF (.C(clk), .CE(1'b1), .D(D[3]), .Q(Q[3]));
        
        assign state[0] = Q[0];
        assign state[1] = Q[1];
        assign state[2] = Q[2];
        assign state[3] = Q[3];
        
endmodule