data/full_repos/permissive/487455827/cpu/rtl/core/csr.v
1: b'%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/487455827/cpu/rtl/core,data/full_repos/permissive/487455827/defines.v\n             data/full_repos/permissive/487455827/cpu/rtl/core,data/full_repos/permissive/487455827/defines.v.v\n             data/full_repos/permissive/487455827/cpu/rtl/core,data/full_repos/permissive/487455827/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:12: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus]           data_i,\n            ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:12: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`RegBus]           data_i,\n                   ^\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:15: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[`RegBus]           current_inst_addr_i,\n ^~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:15: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus]           current_inst_addr_i,\n            ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:17: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus]           data_o,\n            ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:18: Define or directive not defined: \'`RegBus\'\n output wire[`RegBus]    mstatus_o,\n             ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:19: Define or directive not defined: \'`RegBus\'\n output wire[`RegBus]    mepc_o,\n             ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:20: Define or directive not defined: \'`RegBus\'\n output wire[`RegBus]    mie_o,\n             ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:21: Define or directive not defined: \'`RegBus\'\n output wire[`RegBus]    mip_o,\n             ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:22: Define or directive not defined: \'`RegBus\'\n output wire[`RegBus]    mtvec_o,\n             ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:25: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:27: Define or directive not defined: \'`RegBus\'\n reg[`RegBus]    fflags;  \n     ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:27: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus]    fflags;  \n            ^\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:28: Define or directive not defined: \'`RegBus\'\n reg[`RegBus]    frm;   \n     ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:28: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus]    frm;   \n            ^\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:29: Define or directive not defined: \'`RegBus\'\n reg[`RegBus]    fcsr;   \n     ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:29: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus]    fcsr;   \n            ^\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:30: Define or directive not defined: \'`RegBus\'\n reg[`RegBus]    mstatus;  \n     ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:30: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus]    mstatus;  \n            ^\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:31: Define or directive not defined: \'`RegBus\'\n reg[`RegBus]    misa;   \n     ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:31: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus]    misa;   \n            ^\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:32: Define or directive not defined: \'`RegBus\'\n reg[`RegBus]    mie;   \n     ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:32: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus]    mie;   \n            ^\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:33: Define or directive not defined: \'`RegBus\'\n reg[`RegBus]    mtvec;   \n     ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:33: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus]    mtvec;   \n            ^\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:34: Define or directive not defined: \'`RegBus\'\n reg[`RegBus]    mscratch;  \n     ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:34: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus]    mscratch;  \n            ^\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:35: Define or directive not defined: \'`RegBus\'\n reg[`RegBus]    mepc;   \n     ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:35: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus]    mepc;   \n            ^\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:36: Define or directive not defined: \'`RegBus\'\n reg[`RegBus]    mcause;  \n     ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:36: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus]    mcause;  \n            ^\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:37: Define or directive not defined: \'`RegBus\'\n reg[`RegBus]    mtval;   \n     ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:37: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus]    mtval;   \n            ^\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:38: Define or directive not defined: \'`RegBus\'\n reg[`RegBus]    mip;   \n     ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:38: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus]    mip;   \n            ^\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:39: Define or directive not defined: \'`RegBus\'\n reg[`RegBus]    mcycle;  \n     ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:39: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus]    mcycle;  \n            ^\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:40: Define or directive not defined: \'`RegBus\'\n reg[`RegBus]    mcycleh;  \n     ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:40: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus]    mcycleh;  \n            ^\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:41: Define or directive not defined: \'`RegBus\'\n reg[`RegBus]    minstret;  \n     ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:41: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus]    minstret;  \n            ^\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:42: Define or directive not defined: \'`RegBus\'\n reg[`RegBus]    minstreth;  \n     ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:42: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus]    minstreth;  \n            ^\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:43: Define or directive not defined: \'`RegBus\'\n reg[`RegBus]    mvendorid;  \n     ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:43: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus]    mvendorid;  \n            ^\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:44: Define or directive not defined: \'`RegBus\'\n reg[`RegBus]    marchid;  \n     ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:44: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus]    marchid;  \n            ^\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:45: Define or directive not defined: \'`RegBus\'\n reg[`RegBus]    mimpid;  \n     ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/core/csr.v:45: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`RegBus]    mimpid;  \n            ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module csr(

	input	wire										clk,
	input wire										rst,
	
	
	input wire                    we_i,
	input wire[11:0]              waddr_i,
	input wire[11:0]              raddr_i,
	input wire[`RegBus]           data_i,
	
	input wire[31:0]              excepttype_i,
	input wire[`RegBus]           current_inst_addr_i,
	
	output reg[`RegBus]           data_o,
	output wire[`RegBus]				mstatus_o,
	output wire[`RegBus]				mepc_o,
	output wire[`RegBus]				mie_o,
	output wire[`RegBus]				mip_o,
	output wire[`RegBus]				mtvec_o,
	
	output reg[1:0]					curr_mode
);

	reg[`RegBus]				fflags;
	reg[`RegBus]				frm;
	reg[`RegBus]				fcsr;
	reg[`RegBus]				mstatus;
	reg[`RegBus]				misa;
	reg[`RegBus]				mie;
	reg[`RegBus]				mtvec;
	reg[`RegBus]				mscratch;
	reg[`RegBus]				mepc;
	reg[`RegBus]				mcause;
	reg[`RegBus]				mtval;
	reg[`RegBus]				mip;
	reg[`RegBus]				mcycle;
	reg[`RegBus]				mcycleh;
	reg[`RegBus]				minstret;
	reg[`RegBus]				minstreth;
	reg[`RegBus]				mvendorid;
	reg[`RegBus]				marchid;
	reg[`RegBus]				mimpid;
	reg[`RegBus]				mhartid;

	initial begin
		misa <= 32'h40001100;
		mvendorid <= 32'h00000000;
		marchid <= 32'h00000000;
		mimpid <= 32'h00000000;
		mhartid <= 32'h00000000;
		mstatus <= 32'h00000000;
		curr_mode <= `m_mode;
	end
	
	assign mstatus_o = mstatus;
	assign mepc_o = mepc;
	assign mie_o = mie;
	assign mip_o = mip;
	assign mtvec_o = mtvec;


	always @ (posedge clk) begin
		if(rst == `RstEnable) begin

			mie <= `ZeroWord;
			mtvec <= `ZeroWord;
			mscratch <= `ZeroWord;
			mepc <= `ZeroWord;
			mcause <= `ZeroWord;
			mtval <= `ZeroWord;
			mip <= `ZeroWord;
			mcycle <= `ZeroWord;
			mcycleh <= `ZeroWord;
			minstret <= `ZeroWord;
			minstreth <= `ZeroWord;
			marchid <= `ZeroWord;
			mhartid <= `ZeroWord;
		end else begin
			if(mcycle == 32'hffffffff) begin
				mcycle <= 32'h00000000;
				mcycleh <= mcycleh + 1;
			end else if(mcycle != 32'hffffffff) begin
				mcycle <= mcycle + 1;
			end
			if(we_i == `WriteEnable) begin
				case (waddr_i) 
					`CSR_REG_FFLAGS:		begin
						fflags <= data_i ;
					end
					`CSR_REG_FRM:	begin
						frm <= data_i ;
					end
					`CSR_REG_FCSR:	begin
						fcsr <= data_i ;
					end
					`CSR_REG_MSTATUS:	begin
						mstatus <= data_i ;
					end
					`CSR_REG_MISA:	begin
						misa <= data_i ;
					end
					`CSR_REG_MIE:	begin
						mie <= data_i ;
					end
					`CSR_REG_MTVEC:	begin
						mtvec <= data_i ;
					end
					`CSR_REG_MSCRATCH:	begin
						mscratch <= data_i ;
					end
					`CSR_REG_MEPC:	begin
						mepc <= data_i ;
					end
					`CSR_REG_MCAUSE:	begin
						mcause <= data_i ;
					end
					`CSR_REG_MTVAL:	begin
						mtval <= data_i ;
					end
					`CSR_REG_MIP:	begin
						mip <= data_i ;
					end
					`CSR_REG_MCYCLE:	begin
						mcycle <= data_i ;
					end
					`CSR_REG_MCYCLEH:	begin
						mcycleh <= data_i ;
					end
					`CSR_REG_MINSTRET:	begin
						minstret <= data_i ;
					end
					`CSR_REG_MINSTRETH:	begin
						minstreth <= data_i ;
					end
					`CSR_REG_MVENDORID:	begin
						mvendorid <= data_i ;
					end
					`CSR_REG_MARCHID:	begin
						marchid <= data_i ;
					end
					`CSR_REG_MIMPID:	begin
						mimpid <= data_i ;
					end
					`CSR_REG_MHARTID:	begin
						mhartid <= data_i ;
					end
					default: 	begin
					end			
				endcase
			end
			
			if(excepttype_i[31] == 1'b1) begin
				case (excepttype_i[3:0])
					4'd11:		begin
							mcause <= excepttype_i;
							mepc <= current_inst_addr_i + 4;
							mstatus[7] <= mstatus[3];
							mstatus[3] <= 1'b0;

							mstatus[12:11] <= `u_mode;
							curr_mode <= `m_mode;

					end
					4'd7:			begin
							mcause <= excepttype_i;
							mepc <= current_inst_addr_i + 4;
							mstatus[7] <= mstatus[3];
							mstatus[3] <= 1'b0;

							mstatus[12:11] <= `u_mode;
							curr_mode <= `m_mode;
					end
					4'd0:			begin
							mcause <= excepttype_i;
							mepc <= current_inst_addr_i + 4;
							mstatus[7] <= mstatus[3];
							mstatus[3] <= 1'b0;

							mstatus[12:11] <= `u_mode;
							curr_mode <= `m_mode;
					end
				endcase
			end else if(excepttype_i[31] == 1'b0) begin
				case (excepttype_i[30:0])		
					{3'b0, 28'h0000008}:		begin
						mcause <= {3'b0, 28'h000000b};
						mepc <= current_inst_addr_i;
						mstatus[7] <= mstatus[3];
						mstatus[3] <= 1'b0;

						mstatus[12:11] <= `u_mode;
						curr_mode <= `m_mode;
					end
					{3'b0, 28'h0000002}:		begin
						mcause <= {3'b0, 28'h0000002};
						mepc <= current_inst_addr_i;
						mstatus[7] <= mstatus[3];
						mstatus[3] <= 1'b0;

						mstatus[12:11] <= `u_mode;
						curr_mode <= `m_mode;
						mtval <= current_inst_addr_i;
					end
					{3'b0, 28'h000000a}:		begin
						mcause <= {3'b0, 28'h000000a};
						mstatus[3] <= mstatus[7];
						mstatus[7] <= 1'b1;

						curr_mode <= mstatus[12:11];
					end
				endcase
			end
		end
	end
			
	always @ (*) begin
		if(rst == `RstEnable) begin
			data_o = `ZeroWord;
		end else begin
				case (raddr_i) 
					`CSR_REG_FFLAGS:		begin
						data_o = fflags ;
					end
					`CSR_REG_FRM:	begin
						data_o = frm ;
					end
					`CSR_REG_FCSR:	begin
						data_o = fcsr ;
					end
					`CSR_REG_MSTATUS:	begin
						data_o = mstatus ;
					end
					`CSR_REG_MISA:	begin
						data_o = misa ;
					end
					`CSR_REG_MIE:	begin
						data_o = mie ;
					end
					`CSR_REG_MTVEC:	begin
						data_o = mtvec ;
					end
					`CSR_REG_MSCRATCH:	begin
						data_o = mscratch ;
					end
					`CSR_REG_MEPC:	begin
						data_o = mepc ;
					end
					`CSR_REG_MCAUSE:	begin
						data_o = mcause ;
					end
					`CSR_REG_MTVAL:	begin
						data_o = mtval ;
					end
					`CSR_REG_MIP:	begin
						data_o = mip ;
					end
					`CSR_REG_MCYCLE:	begin
						data_o = mcycle ;
					end
					`CSR_REG_MCYCLEH:	begin
						data_o = mcycleh ;
					end
					`CSR_REG_MINSTRET:	begin
						data_o = minstret ;
					end
					`CSR_REG_MINSTRETH:	begin
						data_o = minstreth ;
					end
					`CSR_REG_MVENDORID:	begin
						data_o = mvendorid ;
					end
					`CSR_REG_MARCHID:	begin
						data_o = marchid ;
					end
					`CSR_REG_MIMPID:	begin
						data_o = mimpid ;
					end
					`CSR_REG_MHARTID:	begin
						data_o = mhartid ;
					end
					default: 	begin
					end			
				endcase
		end
	end

endmodule
module csr(

	input	wire										clk,
	input wire										rst,
	
	
	input wire                    we_i,
	input wire[11:0]              waddr_i,
	input wire[11:0]              raddr_i,
	input wire[`RegBus]           data_i,
	
	input wire[31:0]              excepttype_i,
	input wire[`RegBus]           current_inst_addr_i,
	
	output reg[`RegBus]           data_o,
	output wire[`RegBus]				mstatus_o,
	output wire[`RegBus]				mepc_o,
	output wire[`RegBus]				mie_o,
	output wire[`RegBus]				mip_o,
	output wire[`RegBus]				mtvec_o,
	
	output reg[1:0]					curr_mode
);


	reg[`RegBus]				fflags;
	reg[`RegBus]				frm;
	reg[`RegBus]				fcsr;
	reg[`RegBus]				mstatus;
	reg[`RegBus]				misa;
	reg[`RegBus]				mie;
	reg[`RegBus]				mtvec;
	reg[`RegBus]				mscratch;
	reg[`RegBus]				mepc;
	reg[`RegBus]				mcause;
	reg[`RegBus]				mtval;
	reg[`RegBus]				mip;
	reg[`RegBus]				mcycle;
	reg[`RegBus]				mcycleh;
	reg[`RegBus]				minstret;
	reg[`RegBus]				minstreth;
	reg[`RegBus]				mvendorid;
	reg[`RegBus]				marchid;
	reg[`RegBus]				mimpid;
	reg[`RegBus]				mhartid;

	initial begin
		misa <= 32'h40001100;
		mvendorid <= 32'h00000000;
		marchid <= 32'h00000000;
		mimpid <= 32'h00000000;
		mhartid <= 32'h00000000;
		mstatus <= 32'h00000000;
		curr_mode <= `m_mode;
	end
	
	assign mstatus_o = mstatus;
	assign mepc_o = mepc;
	assign mie_o = mie;
	assign mip_o = mip;
	assign mtvec_o = mtvec;


	always @ (posedge clk) begin
		if(rst == `RstEnable) begin

			mie <= `ZeroWord;
			mtvec <= `ZeroWord;
			mscratch <= `ZeroWord;
			mepc <= `ZeroWord;
			mcause <= `ZeroWord;
			mtval <= `ZeroWord;
			mip <= `ZeroWord;
			mcycle <= `ZeroWord;
			mcycleh <= `ZeroWord;
			minstret <= `ZeroWord;
			minstreth <= `ZeroWord;
			marchid <= `ZeroWord;
			mhartid <= `ZeroWord;
		end else begin
			if(mcycle == 32'hffffffff) begin
				mcycle <= 32'h00000000;
				mcycleh <= mcycleh + 1;
			end else if(mcycle != 32'hffffffff) begin
				mcycle <= mcycle + 1;
			end
			if(we_i == `WriteEnable) begin
				case (waddr_i) 
					`CSR_REG_FFLAGS:		begin
						fflags <= data_i ;
					end
					`CSR_REG_FRM:	begin
						frm <= data_i ;
					end
					`CSR_REG_FCSR:	begin
						fcsr <= data_i ;
					end
					`CSR_REG_MSTATUS:	begin
						mstatus <= data_i ;
					end
					`CSR_REG_MISA:	begin
						misa <= data_i ;
					end
					`CSR_REG_MIE:	begin
						mie <= data_i ;
					end
					`CSR_REG_MTVEC:	begin
						mtvec <= data_i ;
					end
					`CSR_REG_MSCRATCH:	begin
						mscratch <= data_i ;
					end
					`CSR_REG_MEPC:	begin
						mepc <= data_i ;
					end
					`CSR_REG_MCAUSE:	begin
						mcause <= data_i ;
					end
					`CSR_REG_MTVAL:	begin
						mtval <= data_i ;
					end
					`CSR_REG_MIP:	begin
						mip <= data_i ;
					end
					`CSR_REG_MCYCLE:	begin
						mcycle <= data_i ;
					end
					`CSR_REG_MCYCLEH:	begin
						mcycleh <= data_i ;
					end
					`CSR_REG_MINSTRET:	begin
						minstret <= data_i ;
					end
					`CSR_REG_MINSTRETH:	begin
						minstreth <= data_i ;
					end
					`CSR_REG_MVENDORID:	begin
						mvendorid <= data_i ;
					end
					`CSR_REG_MARCHID:	begin
						marchid <= data_i ;
					end
					`CSR_REG_MIMPID:	begin
						mimpid <= data_i ;
					end
					`CSR_REG_MHARTID:	begin
						mhartid <= data_i ;
					end
					default: 	begin
					end			
				endcase
			end
			
			if(excepttype_i[31] == 1'b1) begin
				case (excepttype_i[3:0])
					4'd11:		begin
							mcause <= excepttype_i;
							mepc <= current_inst_addr_i + 4;
							mstatus[7] <= mstatus[3];
							mstatus[3] <= 1'b0;

							mstatus[12:11] <= `u_mode;
							curr_mode <= `m_mode;

					end
					4'd7:			begin
							mcause <= excepttype_i;
							mepc <= current_inst_addr_i + 4;
							mstatus[7] <= mstatus[3];
							mstatus[3] <= 1'b0;

							mstatus[12:11] <= `u_mode;
							curr_mode <= `m_mode;
					end
					4'd0:			begin
							mcause <= excepttype_i;
							mepc <= current_inst_addr_i + 4;
							mstatus[7] <= mstatus[3];
							mstatus[3] <= 1'b0;

							mstatus[12:11] <= `u_mode;
							curr_mode <= `m_mode;
					end
				endcase
			end else if(excepttype_i[31] == 1'b0) begin
				case (excepttype_i[30:0])		
					{3'b0, 28'h0000008}:		begin
						mcause <= {3'b0, 28'h000000b};
						mepc <= current_inst_addr_i;
						mstatus[7] <= mstatus[3];
						mstatus[3] <= 1'b0;

						mstatus[12:11] <= `u_mode;
						curr_mode <= `m_mode;
					end
					{3'b0, 28'h0000002}:		begin
						mcause <= {3'b0, 28'h0000002};
						mepc <= current_inst_addr_i;
						mstatus[7] <= mstatus[3];
						mstatus[3] <= 1'b0;

						mstatus[12:11] <= `u_mode;
						curr_mode <= `m_mode;
						mtval <= current_inst_addr_i;
					end
					{3'b0, 28'h000000a}:		begin
						mcause <= {3'b0, 28'h000000a};
						mstatus[3] <= mstatus[7];
						mstatus[7] <= 1'b1;

						curr_mode <= mstatus[12:11];
					end
				endcase
			end
		end
	end
			
	always @ (*) begin
		if(rst == `RstEnable) begin
			data_o = `ZeroWord;
		end else begin
				case (raddr_i) 
					`CSR_REG_FFLAGS:		begin
						data_o = fflags ;
					end
					`CSR_REG_FRM:	begin
						data_o = frm ;
					end
					`CSR_REG_FCSR:	begin
						data_o = fcsr ;
					end
					`CSR_REG_MSTATUS:	begin
						data_o = mstatus ;
					end
					`CSR_REG_MISA:	begin
						data_o = misa ;
					end
					`CSR_REG_MIE:	begin
						data_o = mie ;
					end
					`CSR_REG_MTVEC:	begin
						data_o = mtvec ;
					end
					`CSR_REG_MSCRATCH:	begin
						data_o = mscratch ;
					end
					`CSR_REG_MEPC:	begin
						data_o = mepc ;
					end
					`CSR_REG_MCAUSE:	begin
						data_o = mcause ;
					end
					`CSR_REG_MTVAL:	begin
						data_o = mtval ;
					end
					`CSR_REG_MIP:	begin
						data_o = mip ;
					end
					`CSR_REG_MCYCLE:	begin
						data_o = mcycle ;
					end
					`CSR_REG_MCYCLEH:	begin
						data_o = mcycleh ;
					end
					`CSR_REG_MINSTRET:	begin
						data_o = minstret ;
					end
					`CSR_REG_MINSTRETH:	begin
						data_o = minstreth ;
					end
					`CSR_REG_MVENDORID:	begin
						data_o = mvendorid ;
					end
					`CSR_REG_MARCHID:	begin
						data_o = marchid ;
					end
					`CSR_REG_MIMPID:	begin
						data_o = mimpid ;
					end
					`CSR_REG_MHARTID:	begin
						data_o = mhartid ;
					end
					default: 	begin
					end			
				endcase
		end
	end

endmodule