data/full_repos/permissive/475928601/J Component/mealy_tb.v
1: b'%Error: Cannot find file containing module: Component,data/full_repos/permissive/475928601\n        ... Looked in:\n             data/full_repos/permissive/475928601/J/Component,data/full_repos/permissive/475928601\n             data/full_repos/permissive/475928601/J/Component,data/full_repos/permissive/475928601.v\n             data/full_repos/permissive/475928601/J/Component,data/full_repos/permissive/475928601.sv\n             Component,data/full_repos/permissive/475928601\n             Component,data/full_repos/permissive/475928601.v\n             Component,data/full_repos/permissive/475928601.sv\n             obj_dir/Component,data/full_repos/permissive/475928601\n             obj_dir/Component,data/full_repos/permissive/475928601.v\n             obj_dir/Component,data/full_repos/permissive/475928601.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/475928601/J\n%Error: Cannot find file containing module: Component/mealy_tb.v\n%Error: Exiting due to 3 error(s)\n'
module mealy_tb;
    reg clk, reset, in;
    wire out;

    mealy uut(clk, reset, in, out);

    initial begin
        $dumpfile("dump.vcd");
        $dumpvars(1);


        {reset, in, clk} = 3'b000; #20;
        {reset, in, clk} = 3'b001; #20;
        {reset, in, clk} = 3'b010; #20;
        {reset, in, clk} = 3'b011; #20;
        {reset, in, clk} = 3'b010; #20;
        {reset, in, clk} = 3'b111; #20;


        {reset, in, clk} = 3'b000; #20;
        {reset, in, clk} = 3'b001; #20;
        {reset, in, clk} = 3'b100; #20;
        {reset, in, clk} = 3'b101; #20;
    end
endmodule
module mealy_tb;

    reg clk, reset, in;
    wire out;

    mealy uut(clk, reset, in, out);

    initial begin
        $dumpfile("dump.vcd");
        $dumpvars(1);


        {reset, in, clk} = 3'b000; #20;
        {reset, in, clk} = 3'b001; #20;
        {reset, in, clk} = 3'b010; #20;
        {reset, in, clk} = 3'b011; #20;
        {reset, in, clk} = 3'b010; #20;
        {reset, in, clk} = 3'b111; #20;


        {reset, in, clk} = 3'b000; #20;
        {reset, in, clk} = 3'b001; #20;
        {reset, in, clk} = 3'b100; #20;
        {reset, in, clk} = 3'b101; #20;
    end
endmodule