data/full_repos/permissive/423014416/MA7_Clock.srcs/sources_1/new/SevenSegmentDisplayDecoder.v
data/verilator_xmls/f6345eea-fb78-4e41-b9a7-c241c98446c3.xml
module SevenSegmentDisplayDecoder(
    input clk,
    input [15:0] value,
    input [3:0] decimalPoint,

    output [7:0] displayOut,
    output reg [3:0] enableOut
);
    reg [6:0] displayOutNoDecimal;
    reg [1:0] enableCounter;
    reg [3:0] activeValue;
    reg [17:0] accessCounter;
    reg activeDecimalValue;
    

    assign displayOut = {displayOutNoDecimal[6:4], activeDecimalValue, displayOutNoDecimal[3:0]};


    initial begin
        displayOutNoDecimal = 7'b1111111;
        enableOut = 4'b1111;
        accessCounter = 0;
    end

    always @(posedge clk) begin
        accessCounter <= accessCounter + 1;
        if(accessCounter == 0)
        begin
            enableCounter <= enableCounter + 1;
            case(enableCounter)
                2'b00: begin
                    enableOut <= 4'b0111;
                    activeValue <= value[3:0];
                    activeDecimalValue <= ~decimalPoint[3];
                end
                2'b01: begin
                    enableOut <= 4'b1110;
                    activeValue <= value[7:4];
                    activeDecimalValue <= ~decimalPoint[0];
                end
                2'b10: begin
                    enableOut <= 4'b1101;
                    activeValue <= value[11:8];
                    activeDecimalValue <= ~decimalPoint[1];
                end
                2'b11: begin
                    enableOut <= 4'b1011;
                    activeValue <= value[15:12];
                    activeDecimalValue <= ~decimalPoint[2];
                end
            endcase

            case(activeValue)
                4'b0000: displayOutNoDecimal <= 7'b0000001;
                4'b0001: displayOutNoDecimal <= 7'b1100111;
                4'b0010: displayOutNoDecimal <= 7'b0010010;
                4'b0011: displayOutNoDecimal <= 7'b1000010;
                4'b0100: displayOutNoDecimal <= 7'b1100100;
                4'b0101: displayOutNoDecimal <= 7'b1001000;
                4'b0110: displayOutNoDecimal <= 7'b0001000;
                4'b0111: displayOutNoDecimal <= 7'b1100011;
                4'b1000: displayOutNoDecimal <= 7'b0000000;
                4'b1001: displayOutNoDecimal <= 7'b1000000;
                4'b1010: displayOutNoDecimal <= 7'b0100000;
                4'b1011: displayOutNoDecimal <= 7'b0001100;
                4'b1100: displayOutNoDecimal <= 7'b0011001;
                4'b1101: displayOutNoDecimal <= 7'b0000110;
                4'b1110: displayOutNoDecimal <= 7'b0011000;
                4'b1111: displayOutNoDecimal <= 7'b0111000;
            endcase
        end
    end
endmodule
module SevenSegmentDisplayDecoder(
    input clk,
    input [15:0] value,
    input [3:0] decimalPoint,

    output [7:0] displayOut,
    output reg [3:0] enableOut
);

    reg [6:0] displayOutNoDecimal;
    reg [1:0] enableCounter;
    reg [3:0] activeValue;
    reg [17:0] accessCounter;
    reg activeDecimalValue;
    

    assign displayOut = {displayOutNoDecimal[6:4], activeDecimalValue, displayOutNoDecimal[3:0]};


    initial begin
        displayOutNoDecimal = 7'b1111111;
        enableOut = 4'b1111;
        accessCounter = 0;
    end

    always @(posedge clk) begin
        accessCounter <= accessCounter + 1;
        if(accessCounter == 0)
        begin
            enableCounter <= enableCounter + 1;
            case(enableCounter)
                2'b00: begin
                    enableOut <= 4'b0111;
                    activeValue <= value[3:0];
                    activeDecimalValue <= ~decimalPoint[3];
                end
                2'b01: begin
                    enableOut <= 4'b1110;
                    activeValue <= value[7:4];
                    activeDecimalValue <= ~decimalPoint[0];
                end
                2'b10: begin
                    enableOut <= 4'b1101;
                    activeValue <= value[11:8];
                    activeDecimalValue <= ~decimalPoint[1];
                end
                2'b11: begin
                    enableOut <= 4'b1011;
                    activeValue <= value[15:12];
                    activeDecimalValue <= ~decimalPoint[2];
                end
            endcase

            case(activeValue)
                4'b0000: displayOutNoDecimal <= 7'b0000001;
                4'b0001: displayOutNoDecimal <= 7'b1100111;
                4'b0010: displayOutNoDecimal <= 7'b0010010;
                4'b0011: displayOutNoDecimal <= 7'b1000010;
                4'b0100: displayOutNoDecimal <= 7'b1100100;
                4'b0101: displayOutNoDecimal <= 7'b1001000;
                4'b0110: displayOutNoDecimal <= 7'b0001000;
                4'b0111: displayOutNoDecimal <= 7'b1100011;
                4'b1000: displayOutNoDecimal <= 7'b0000000;
                4'b1001: displayOutNoDecimal <= 7'b1000000;
                4'b1010: displayOutNoDecimal <= 7'b0100000;
                4'b1011: displayOutNoDecimal <= 7'b0001100;
                4'b1100: displayOutNoDecimal <= 7'b0011001;
                4'b1101: displayOutNoDecimal <= 7'b0000110;
                4'b1110: displayOutNoDecimal <= 7'b0011000;
                4'b1111: displayOutNoDecimal <= 7'b0111000;
            endcase
        end
    end
endmodule