data/full_repos/permissive/517292562/C910_RTL_FACTORY/gen_rtl/ifu/rtl/ct_ifu_decd_normal.v
data/verilator_xmls/d9284725-a69e-42b2-880e-ddf6323e1874.xml
module ct_ifu_decd_normal(
  cp0_ifu_vl,
  cp0_ifu_vsetvli_pred_disable,
  x_auipc,
  x_br,
  x_branch,
  x_chgflw,
  x_con_br,
  x_dst_vld,
  x_ind_br,
  x_inst,
  x_jal,
  x_jalr,
  x_ld,
  x_offset,
  x_pc_oper,
  x_pcall,
  x_preturn,
  x_st,
  x_vlmax,
  x_vlmul,
  x_vsetvli,
  x_vsew
);


input   [7 :0]  cp0_ifu_vl;                  
input           cp0_ifu_vsetvli_pred_disable; 
input           x_br;                        
input   [31:0]  x_inst;                      
output          x_auipc;                     
output          x_branch;                    
output          x_chgflw;                    
output          x_con_br;                    
output          x_dst_vld;                   
output          x_ind_br;                    
output          x_jal;                       
output          x_jalr;                      
output          x_ld;                        
output  [20:0]  x_offset;                    
output          x_pc_oper;                   
output          x_pcall;                     
output          x_preturn;                   
output          x_st;                        
output  [7 :0]  x_vlmax;                     
output  [1 :0]  x_vlmul;                     
output          x_vsetvli;                   
output  [2 :0]  x_vsew;                      




wire    [7 :0]  cp0_ifu_vl;                  
wire            cp0_ifu_vsetvli_pred_disable; 
wire            x_ab_br;                     
wire            x_auipc;                     
wire            x_br;                        
wire            x_branch;                    
wire            x_chgflw;                    
wire            x_con_br;                    
wire            x_dst_vld;                   
wire            x_ind_br;                    
wire    [31:0]  x_inst;                      
wire            x_jal;                       
wire            x_jalr;                      
wire            x_ld;                        
wire    [20:0]  x_offset;                    
wire    [20:0]  x_offset_12_ab_br;           
wire            x_offset_12_ab_br_vld;       
wire    [20:0]  x_offset_12_ind_br;          
wire            x_offset_12_ind_br_vld;      
wire    [20:0]  x_offset_13_con_br;          
wire            x_offset_13_con_br_vld;      
wire    [20:0]  x_offset_21_ab_br;           
wire            x_offset_21_ab_br_vld;       
wire    [20:0]  x_offset_9_con_br;           
wire            x_offset_9_con_br_vld;       
wire            x_pc_oper;                   
wire            x_pcall;                     
wire            x_preturn;                   
wire            x_st;                        
wire    [7 :0]  x_vlmax;                     
wire    [1 :0]  x_vlmul;                     
wire            x_vsetvli;                   
wire    [2 :0]  x_vsew;                      









assign x_ab_br = x_br && 
                 (
                   (x_inst[2:1] == 2'b11) ||
                   ({x_inst[14],x_inst[1]} == 2'b00)
                 );

assign x_con_br = x_br && 
                  (
                    (x_inst[2:1] == 2'b01) ||
                    ({x_inst[14],x_inst[1]} == 2'b10)
                  );



assign x_auipc = (x_inst[6:0] == 7'b0010111);



assign x_pc_oper = x_br ||
                 ({x_inst[14:12],x_inst[6:0]} == 10'b000_1100111) ||
                 ({x_inst[15:13],x_inst[6:0]} == 10'b100_00000_10) && (x_inst[11:7] != 5'b0) ||
                 (x_inst[6:0] == 7'b0010111);

                  


assign x_chgflw = ({x_inst[14:12],x_inst[6:0]} == 10'b000_1100111) ||
                  ({x_inst[15:13],x_inst[6:0]} == 10'b100_00000_10) && (x_inst[11:7] != 5'b0) ||
                  x_ab_br;




assign x_branch = ({x_inst[14:12],x_inst[6:0]} == 10'b000_1100111) ||
                  ({x_inst[15:13],x_inst[6:0]} == 10'b100_00000_10) && (x_inst[11:7] != 5'b0) ||
                  x_br;

                

assign x_jal = (x_inst[6:0] == 7'b1101111) ||
                ({x_inst[15:13], x_inst[1:0]} == 5'b10101);



assign x_jalr = ({x_inst[14:12],x_inst[6:0]} == 10'b000_1100111) ||
                ({x_inst[15:13],x_inst[6:0]} == 10'b100_00000_10) && (x_inst[11:7] != 5'b0);



assign x_dst_vld = ((x_inst[6:0] == 7'b1101111) || ({x_inst[14:12],x_inst[6:0]} == 10'b000_1100111)) && (x_inst[11:7] != 5'b0)
                || ({x_inst[15:12],x_inst[6:0]} == 11'b1001_00000_10) && (x_inst[11:7] != 5'b0);

























assign x_pcall = (
                  ({x_inst[14:12],x_inst[6:0]} == 10'b000_1100111) &&
                  (
                   (x_inst[11:7] == 5'b00001) ||
                   (x_inst[11:7] == 5'b00101)
                  )
                 ) || 
                 (
                  (x_inst[6:0] == 7'b1101111) &&
                  (     
                   (x_inst[11:7] == 5'b00001) ||
                   (x_inst[11:7] == 5'b00101)
                  )
                 ) ||
                 (
                   ({x_inst[15:12],x_inst[6:0]} == 11'b1001_00000_10) &&
                   (x_inst[11:7] != 5'b0)
                 ); 





assign x_preturn = (
                    ({x_inst[14:12],x_inst[6:0]} == 10'b000_1100111) &&
                    (x_inst[11:7] != x_inst[19:15]) &&
                    (
                     (x_inst[19:15] == 5'b00001) ||
                     (x_inst[19:15] == 5'b00101)
                    ) &&
                    (x_inst[31:20] == 12'b0)
                   ) ||
                   (
                    ({x_inst[15:12],x_inst[6:0]} == 11'b1000_00000_10) &&
                    (
                     (x_inst[11:7] == 5'b00001) ||
                     (x_inst[11:7] == 5'b00101)
                    ) &&
                     (x_inst[11:7] != 5'b00000)
                   ) ||
                   (
                     ({x_inst[15:12],x_inst[6:0]} == 11'b1001_00000_10) &&
                     (x_inst[11:7] == 5'b00101)
                   ); 



assign x_ind_br  = (
                    ({x_inst[14:12],x_inst[6:0]} == 10'b000_1100111) &&
                    (
                     ( 
                      ((x_inst[19:15] != 5'b1) &&
                       (x_inst[19:15] != 5'b00101)
                      ) ||
                      (x_inst[31:20] != 12'b0)
                     ) ||
                     (x_inst[11:7] == x_inst[19:15])
                    )
                   ) ||
                   (
                    ({x_inst[15:12],x_inst[6:0]} == 11'b1000_00000_10) &&
                    !(x_inst[11:7] == 5'b00001) &&
                    !(x_inst[11:7] == 5'b00101) &&
                    !(x_inst[11:7] == 5'b0)
                   ) ||
                   (
                     ({x_inst[15:12],x_inst[6:0]} == 11'b1001_00000_10) &&
                     !(x_inst[11:7] == 5'b00101) && !(x_inst[11:7] == 5'b0)
                   ); 
                





assign x_st =  ({x_inst[14:12],x_inst[6:0]} == 10'b000_0100011)
           ||  ({x_inst[14:12],x_inst[6:0]} == 10'b001_0100011)
           ||  ({x_inst[14:12],x_inst[6:0]} == 10'b010_0100011)
           ||  ({x_inst[14:12],x_inst[6:0]} == 10'b011_0100011)
           ||  (x_inst[6:0] == 7'b0100111)
           ||  ({x_inst[15:13],x_inst[1:0]} == 5'b101_00)
           ||  ({x_inst[15:13],x_inst[1:0]} == 5'b110_00)
           ||  ({x_inst[15:13],x_inst[1:0]} == 5'b111_00)
           ||  ({x_inst[15:13],x_inst[1:0]} == 5'b101_10)
           ||  ({x_inst[15:13],x_inst[1:0]} == 5'b110_10)
           ||  ({x_inst[15:13],x_inst[1:0]} == 5'b111_10)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00000_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00100_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01000_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01100_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00010_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00110_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01010_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01110_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00001_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00011_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00101_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00111_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01001_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01011_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01101_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01111_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11100_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11111_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01000_111_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01100_111_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01010_111_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01110_111_0001011);






assign x_ld=({x_inst[14:12],x_inst[6:0]} == 10'b000_0000011)
        ||  ({x_inst[14:12],x_inst[6:0]} == 10'b001_0000011)
        ||  ({x_inst[14:12],x_inst[6:0]} == 10'b010_0000011)
        ||  ({x_inst[14:12],x_inst[6:0]} == 10'b011_0000011)
        ||  ({x_inst[14:12],x_inst[6:0]} == 10'b100_0000011)
        ||  ({x_inst[14:12],x_inst[6:0]} == 10'b101_0000011)
        ||  ({x_inst[14:12],x_inst[6:0]} == 10'b110_0000011)
        ||  (x_inst[6:0] == 7'b0000111)
        ||  ({x_inst[15:13],x_inst[1:0]} == 5'b001_00)
        ||  ({x_inst[15:13],x_inst[1:0]} == 5'b010_00)
        ||  ({x_inst[15:13],x_inst[1:0]} == 5'b011_00)
        ||  ({x_inst[15:13],x_inst[1:0]} == 5'b001_10)
        ||  ({x_inst[15:13],x_inst[1:0]} == 5'b010_10)
            && (x_inst[11:7] != 5'b0)
        ||  ({x_inst[15:13],x_inst[1:0]} == 5'b011_10)
            && (x_inst[11:7] != 5'b0)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00000_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00100_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01000_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01100_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b10000_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b10100_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11000_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00010_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00110_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01010_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01110_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b10010_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b10110_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11010_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00001_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00011_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00101_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00111_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01001_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01011_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01101_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01111_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b10001_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b10011_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b10101_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b10111_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11001_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11011_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11100_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11110_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11111_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01000_110_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01100_110_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01010_110_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01110_110_0001011);









assign x_vsetvli = !x_inst[31]
                && (x_inst[14:12] == 3'b111)
                && (x_inst[6:0] == 7'b1010111);







assign x_vsew[2:0]  = x_inst[24:22];
assign x_vlmul[1:0] = x_inst[21:20]; 
assign x_vlmax[7:0] = (cp0_ifu_vsetvli_pred_disable) 
                      ? cp0_ifu_vl[7:0]
                      : ((8'b00010000 >> x_inst[23:22]) <<x_inst[21:20]);




assign x_offset_21_ab_br_vld   = (x_inst[6:0] == 7'b1101111);
assign x_offset_21_ab_br[20:0] = {
                                  x_inst[31],  
                                  x_inst[19:12], 
                                  x_inst[20],
                                  x_inst[30:21],
                                  1'b0
                                 };

assign x_offset_12_ind_br_vld   = (x_inst[6:0] == 7'b1100111);
assign x_offset_12_ind_br[20:0] = {
                                   {9{x_inst[31]}},
                                   x_inst[31:20]
                                  };

assign x_offset_13_con_br_vld   = (x_inst[6:0] == 7'b1100011);
assign x_offset_13_con_br[20:0] = {
                                   {9{x_inst[31]}},
                                    x_inst[7],
                                    x_inst[30:25],
                                    x_inst[11:8],
                                    1'b0
                                  };

assign x_offset_12_ab_br_vld    = ({x_inst[15:13],x_inst[1:0]} == 5'b10101);
assign x_offset_12_ab_br[20:0]  = {
                                   {10{x_inst[12]}},
                                   x_inst[8],
                                   x_inst[10:9],
                                   x_inst[6],
                                   x_inst[7],
                                   x_inst[2],
                                   x_inst[11],
                                   x_inst[5:3],
                                   1'b0
                                  };

assign x_offset_9_con_br_vld    = ({x_inst[15:14],x_inst[1:0]} == 4'b1101);
assign x_offset_9_con_br[20:0]  = {
                                   {13{x_inst[12]}},
                                   x_inst[6:5],
                                   x_inst[2],
                                   x_inst[11:10],
                                   x_inst[4:3],
                                   1'b0
                                  };


assign x_offset[20:0] = 
    {21{x_offset_21_ab_br_vld}}  & x_offset_21_ab_br[20:0]
  | {21{x_offset_12_ind_br_vld}} & x_offset_12_ind_br[20:0]
  | {21{x_offset_13_con_br_vld}} & x_offset_13_con_br[20:0]
  | {21{x_offset_12_ab_br_vld}}  & x_offset_12_ab_br[20:0]
  | {21{x_offset_9_con_br_vld}}  & x_offset_9_con_br[20:0];


endmodule
module ct_ifu_decd_normal(
  cp0_ifu_vl,
  cp0_ifu_vsetvli_pred_disable,
  x_auipc,
  x_br,
  x_branch,
  x_chgflw,
  x_con_br,
  x_dst_vld,
  x_ind_br,
  x_inst,
  x_jal,
  x_jalr,
  x_ld,
  x_offset,
  x_pc_oper,
  x_pcall,
  x_preturn,
  x_st,
  x_vlmax,
  x_vlmul,
  x_vsetvli,
  x_vsew
);



input   [7 :0]  cp0_ifu_vl;                  
input           cp0_ifu_vsetvli_pred_disable; 
input           x_br;                        
input   [31:0]  x_inst;                      
output          x_auipc;                     
output          x_branch;                    
output          x_chgflw;                    
output          x_con_br;                    
output          x_dst_vld;                   
output          x_ind_br;                    
output          x_jal;                       
output          x_jalr;                      
output          x_ld;                        
output  [20:0]  x_offset;                    
output          x_pc_oper;                   
output          x_pcall;                     
output          x_preturn;                   
output          x_st;                        
output  [7 :0]  x_vlmax;                     
output  [1 :0]  x_vlmul;                     
output          x_vsetvli;                   
output  [2 :0]  x_vsew;                      




wire    [7 :0]  cp0_ifu_vl;                  
wire            cp0_ifu_vsetvli_pred_disable; 
wire            x_ab_br;                     
wire            x_auipc;                     
wire            x_br;                        
wire            x_branch;                    
wire            x_chgflw;                    
wire            x_con_br;                    
wire            x_dst_vld;                   
wire            x_ind_br;                    
wire    [31:0]  x_inst;                      
wire            x_jal;                       
wire            x_jalr;                      
wire            x_ld;                        
wire    [20:0]  x_offset;                    
wire    [20:0]  x_offset_12_ab_br;           
wire            x_offset_12_ab_br_vld;       
wire    [20:0]  x_offset_12_ind_br;          
wire            x_offset_12_ind_br_vld;      
wire    [20:0]  x_offset_13_con_br;          
wire            x_offset_13_con_br_vld;      
wire    [20:0]  x_offset_21_ab_br;           
wire            x_offset_21_ab_br_vld;       
wire    [20:0]  x_offset_9_con_br;           
wire            x_offset_9_con_br_vld;       
wire            x_pc_oper;                   
wire            x_pcall;                     
wire            x_preturn;                   
wire            x_st;                        
wire    [7 :0]  x_vlmax;                     
wire    [1 :0]  x_vlmul;                     
wire            x_vsetvli;                   
wire    [2 :0]  x_vsew;                      









assign x_ab_br = x_br && 
                 (
                   (x_inst[2:1] == 2'b11) ||
                   ({x_inst[14],x_inst[1]} == 2'b00)
                 );

assign x_con_br = x_br && 
                  (
                    (x_inst[2:1] == 2'b01) ||
                    ({x_inst[14],x_inst[1]} == 2'b10)
                  );



assign x_auipc = (x_inst[6:0] == 7'b0010111);



assign x_pc_oper = x_br ||
                 ({x_inst[14:12],x_inst[6:0]} == 10'b000_1100111) ||
                 ({x_inst[15:13],x_inst[6:0]} == 10'b100_00000_10) && (x_inst[11:7] != 5'b0) ||
                 (x_inst[6:0] == 7'b0010111);

                  


assign x_chgflw = ({x_inst[14:12],x_inst[6:0]} == 10'b000_1100111) ||
                  ({x_inst[15:13],x_inst[6:0]} == 10'b100_00000_10) && (x_inst[11:7] != 5'b0) ||
                  x_ab_br;




assign x_branch = ({x_inst[14:12],x_inst[6:0]} == 10'b000_1100111) ||
                  ({x_inst[15:13],x_inst[6:0]} == 10'b100_00000_10) && (x_inst[11:7] != 5'b0) ||
                  x_br;

                

assign x_jal = (x_inst[6:0] == 7'b1101111) ||
                ({x_inst[15:13], x_inst[1:0]} == 5'b10101);



assign x_jalr = ({x_inst[14:12],x_inst[6:0]} == 10'b000_1100111) ||
                ({x_inst[15:13],x_inst[6:0]} == 10'b100_00000_10) && (x_inst[11:7] != 5'b0);



assign x_dst_vld = ((x_inst[6:0] == 7'b1101111) || ({x_inst[14:12],x_inst[6:0]} == 10'b000_1100111)) && (x_inst[11:7] != 5'b0)
                || ({x_inst[15:12],x_inst[6:0]} == 11'b1001_00000_10) && (x_inst[11:7] != 5'b0);

























assign x_pcall = (
                  ({x_inst[14:12],x_inst[6:0]} == 10'b000_1100111) &&
                  (
                   (x_inst[11:7] == 5'b00001) ||
                   (x_inst[11:7] == 5'b00101)
                  )
                 ) || 
                 (
                  (x_inst[6:0] == 7'b1101111) &&
                  (     
                   (x_inst[11:7] == 5'b00001) ||
                   (x_inst[11:7] == 5'b00101)
                  )
                 ) ||
                 (
                   ({x_inst[15:12],x_inst[6:0]} == 11'b1001_00000_10) &&
                   (x_inst[11:7] != 5'b0)
                 ); 





assign x_preturn = (
                    ({x_inst[14:12],x_inst[6:0]} == 10'b000_1100111) &&
                    (x_inst[11:7] != x_inst[19:15]) &&
                    (
                     (x_inst[19:15] == 5'b00001) ||
                     (x_inst[19:15] == 5'b00101)
                    ) &&
                    (x_inst[31:20] == 12'b0)
                   ) ||
                   (
                    ({x_inst[15:12],x_inst[6:0]} == 11'b1000_00000_10) &&
                    (
                     (x_inst[11:7] == 5'b00001) ||
                     (x_inst[11:7] == 5'b00101)
                    ) &&
                     (x_inst[11:7] != 5'b00000)
                   ) ||
                   (
                     ({x_inst[15:12],x_inst[6:0]} == 11'b1001_00000_10) &&
                     (x_inst[11:7] == 5'b00101)
                   ); 



assign x_ind_br  = (
                    ({x_inst[14:12],x_inst[6:0]} == 10'b000_1100111) &&
                    (
                     ( 
                      ((x_inst[19:15] != 5'b1) &&
                       (x_inst[19:15] != 5'b00101)
                      ) ||
                      (x_inst[31:20] != 12'b0)
                     ) ||
                     (x_inst[11:7] == x_inst[19:15])
                    )
                   ) ||
                   (
                    ({x_inst[15:12],x_inst[6:0]} == 11'b1000_00000_10) &&
                    !(x_inst[11:7] == 5'b00001) &&
                    !(x_inst[11:7] == 5'b00101) &&
                    !(x_inst[11:7] == 5'b0)
                   ) ||
                   (
                     ({x_inst[15:12],x_inst[6:0]} == 11'b1001_00000_10) &&
                     !(x_inst[11:7] == 5'b00101) && !(x_inst[11:7] == 5'b0)
                   ); 
                





assign x_st =  ({x_inst[14:12],x_inst[6:0]} == 10'b000_0100011)
           ||  ({x_inst[14:12],x_inst[6:0]} == 10'b001_0100011)
           ||  ({x_inst[14:12],x_inst[6:0]} == 10'b010_0100011)
           ||  ({x_inst[14:12],x_inst[6:0]} == 10'b011_0100011)
           ||  (x_inst[6:0] == 7'b0100111)
           ||  ({x_inst[15:13],x_inst[1:0]} == 5'b101_00)
           ||  ({x_inst[15:13],x_inst[1:0]} == 5'b110_00)
           ||  ({x_inst[15:13],x_inst[1:0]} == 5'b111_00)
           ||  ({x_inst[15:13],x_inst[1:0]} == 5'b101_10)
           ||  ({x_inst[15:13],x_inst[1:0]} == 5'b110_10)
           ||  ({x_inst[15:13],x_inst[1:0]} == 5'b111_10)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00000_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00100_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01000_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01100_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00010_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00110_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01010_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01110_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00001_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00011_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00101_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00111_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01001_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01011_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01101_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01111_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11100_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11111_101_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01000_111_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01100_111_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01010_111_0001011)
           ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01110_111_0001011);






assign x_ld=({x_inst[14:12],x_inst[6:0]} == 10'b000_0000011)
        ||  ({x_inst[14:12],x_inst[6:0]} == 10'b001_0000011)
        ||  ({x_inst[14:12],x_inst[6:0]} == 10'b010_0000011)
        ||  ({x_inst[14:12],x_inst[6:0]} == 10'b011_0000011)
        ||  ({x_inst[14:12],x_inst[6:0]} == 10'b100_0000011)
        ||  ({x_inst[14:12],x_inst[6:0]} == 10'b101_0000011)
        ||  ({x_inst[14:12],x_inst[6:0]} == 10'b110_0000011)
        ||  (x_inst[6:0] == 7'b0000111)
        ||  ({x_inst[15:13],x_inst[1:0]} == 5'b001_00)
        ||  ({x_inst[15:13],x_inst[1:0]} == 5'b010_00)
        ||  ({x_inst[15:13],x_inst[1:0]} == 5'b011_00)
        ||  ({x_inst[15:13],x_inst[1:0]} == 5'b001_10)
        ||  ({x_inst[15:13],x_inst[1:0]} == 5'b010_10)
            && (x_inst[11:7] != 5'b0)
        ||  ({x_inst[15:13],x_inst[1:0]} == 5'b011_10)
            && (x_inst[11:7] != 5'b0)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00000_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00100_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01000_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01100_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b10000_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b10100_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11000_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00010_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00110_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01010_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01110_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b10010_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b10110_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11010_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00001_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00011_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00101_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b00111_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01001_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01011_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01101_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01111_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b10001_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b10011_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b10101_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b10111_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11001_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11011_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11100_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11110_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b11111_100_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01000_110_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01100_110_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01010_110_0001011)
        ||  ({x_inst[31:27],x_inst[14:12],x_inst[6:0]} == 15'b01110_110_0001011);









assign x_vsetvli = !x_inst[31]
                && (x_inst[14:12] == 3'b111)
                && (x_inst[6:0] == 7'b1010111);







assign x_vsew[2:0]  = x_inst[24:22];
assign x_vlmul[1:0] = x_inst[21:20]; 
assign x_vlmax[7:0] = (cp0_ifu_vsetvli_pred_disable) 
                      ? cp0_ifu_vl[7:0]
                      : ((8'b00010000 >> x_inst[23:22]) <<x_inst[21:20]);




assign x_offset_21_ab_br_vld   = (x_inst[6:0] == 7'b1101111);
assign x_offset_21_ab_br[20:0] = {
                                  x_inst[31],  
                                  x_inst[19:12], 
                                  x_inst[20],
                                  x_inst[30:21],
                                  1'b0
                                 };

assign x_offset_12_ind_br_vld   = (x_inst[6:0] == 7'b1100111);
assign x_offset_12_ind_br[20:0] = {
                                   {9{x_inst[31]}},
                                   x_inst[31:20]
                                  };

assign x_offset_13_con_br_vld   = (x_inst[6:0] == 7'b1100011);
assign x_offset_13_con_br[20:0] = {
                                   {9{x_inst[31]}},
                                    x_inst[7],
                                    x_inst[30:25],
                                    x_inst[11:8],
                                    1'b0
                                  };

assign x_offset_12_ab_br_vld    = ({x_inst[15:13],x_inst[1:0]} == 5'b10101);
assign x_offset_12_ab_br[20:0]  = {
                                   {10{x_inst[12]}},
                                   x_inst[8],
                                   x_inst[10:9],
                                   x_inst[6],
                                   x_inst[7],
                                   x_inst[2],
                                   x_inst[11],
                                   x_inst[5:3],
                                   1'b0
                                  };

assign x_offset_9_con_br_vld    = ({x_inst[15:14],x_inst[1:0]} == 4'b1101);
assign x_offset_9_con_br[20:0]  = {
                                   {13{x_inst[12]}},
                                   x_inst[6:5],
                                   x_inst[2],
                                   x_inst[11:10],
                                   x_inst[4:3],
                                   1'b0
                                  };


assign x_offset[20:0] = 
    {21{x_offset_21_ab_br_vld}}  & x_offset_21_ab_br[20:0]
  | {21{x_offset_12_ind_br_vld}} & x_offset_12_ind_br[20:0]
  | {21{x_offset_13_con_br_vld}} & x_offset_13_con_br[20:0]
  | {21{x_offset_12_ab_br_vld}}  & x_offset_12_ab_br[20:0]
  | {21{x_offset_9_con_br_vld}}  & x_offset_9_con_br[20:0];


endmodule