data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_which_clock.v
data/verilator_xmls/64cc3b9d-d9e0-497b-bf58-2101f76b6dfc.xml
module which_clock (x,y,q,d);
input x,y,d;
output q;
reg q;

always @ (posedge x or posedge y)
   if (x) 
     q <= 1'b0;
   else
     q <= d;

endmodule
module which_clock (x,y,q,d);

input x,y,d;
output q;
reg q;

always @ (posedge x or posedge y)
   if (x) 
     q <= 1'b0;
   else
     q <= d;

endmodule