data/full_repos/permissive/461069000/uart/tb/uart_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/461069000/uart/tb/uart_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n        #(CLOCK_PERIOD_NS/2) clk <= !clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/461069000/uart/tb/uart_tb.v:80: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("uart_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/461069000/uart/tb/uart_tb.v:81: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/461069000/uart/tb/uart_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n        #(CLOCK_PERIOD_NS*2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/461069000/uart/tb/uart_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n        #(CLOCK_PERIOD_NS*2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/461069000/uart/tb/uart_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n        #(CLOCK_PERIOD_NS*2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/461069000/uart/tb/uart_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n        #(CLOCK_PERIOD_NS*2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/461069000/uart/tb/uart_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n        #(CLOCK_PERIOD_NS*2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/461069000/uart/tb/uart_tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n        #(CLOCK_PERIOD_NS*2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/461069000/uart/tb/uart_tb.v:130: Unsupported: Ignoring delay on this delayed statement.\n        #(CLOCK_PERIOD_NS*2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/461069000/uart/tb/uart_tb.v:143: Unsupported: Ignoring delay on this delayed statement.\n        #(BIT_PERIOD_NS*15);\n        ^\n%Error: Exiting due to 2 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module uart_tb;
    localparam CLOCK_PERIOD_NS = 100;
    localparam CLOCKS_PER_BIT = 87;
    localparam BIT_PERIOD_NS = CLOCKS_PER_BIT * CLOCK_PERIOD_NS;


    reg clk = 0;
    reg ext_clk = 0;
    reg rst = 1;

    reg enable_0 = 0;
    reg enable_1 = 0;
    
    reg [2:0] config_address_0 = 0;
    reg [2:0] config_address_1 = 0;
    
    reg config_write_enable_0 = 0;
    reg config_write_enable_1 = 0;
    
    reg [7:0] write_data_0 = 0;
    reg [7:0] write_data_1 = 0;

    wire [7:0] read_data_0;
    wire [7:0] read_data_1;

    wire tx0;
    wire rx0 = 1;
    wire tx1 = 1;




    wire rx_data_int_0;
    wire tx_done_int_0;
    wire rx_error_int_0;

    wire rx_data_int_1;
    wire tx_done_int_1;
    wire rx_error_int_1;

    uart uart_0(
        .clk(clk),
        .rst(rst),
        .enable(enable_0),
        .write_enable(config_write_enable_0),
        .address(config_address_0),
        .write_data(write_data_0),
        .read_data(read_data_0),
        .rx(rx0),
        .tx(tx0),
        .rx_data_int(rx_data_int_0),
        .tx_done_int(tx_done_int_0),
        .rx_error_int(rx_error_int_0)
   );

    uart uart_1(
        .clk(clk),
        .rst(rst),
        .enable(enable_1),
        .write_enable(config_write_enable_1),
        .address(config_address_1),
        .write_data(write_data_1),
        .read_data(read_data_1),
        .rx(tx0),
        .tx(tx1),
        .rx_data_int(rx_data_int_1),
        .tx_done_int(tx_done_int_1),
        .rx_error_int(rx_error_int_1)
   );

  

    always 
        #(CLOCK_PERIOD_NS/2) clk <= !clk;

    initial 
    begin
        $dumpfile("uart_tb.vcd");
        $dumpvars;

        rst = 0;
        #(CLOCK_PERIOD_NS*2);
        rst = 1;
        #(CLOCK_PERIOD_NS*2);



    
        enable_0 = 1;
        enable_1 = 0;
 
        config_write_enable_0 = 1;
        config_write_enable_1 = 0;

        config_address_0 = 0;
        write_data_0 = 8'b0_0_100_100;
        #(CLOCK_PERIOD_NS*2);

        config_address_0 = 1;
        write_data_0 = 8'b0_0_1_0_0_0_0_0;

        #(CLOCK_PERIOD_NS*2);

        config_address_0 = 2;
        write_data_0 = 8'hAB;


        #(CLOCK_PERIOD_NS*2);


        enable_0 = 0;
        enable_1 = 1;

        config_write_enable_0 = 0;
        config_write_enable_1 = 1;


        config_address_1 = 0;
        write_data_1 = 8'b0_1_100_100;

        #(CLOCK_PERIOD_NS*2);

        config_address_1 = 1;
        write_data_1 = 8'b1_1_0_0_0_0_0_0;



        #(CLOCK_PERIOD_NS*2);

        enable_0 = 1;
        enable_1 = 1;

        config_write_enable_0 = 1;
        config_write_enable_1 = 0;

        config_address_1 = 3;
        
        config_address_0 = 0;
        write_data_0 = 8'b1_0_100_100;

        #(BIT_PERIOD_NS*15);

        $finish;
    end




endmodule
module uart_tb;

    localparam CLOCK_PERIOD_NS = 100;
    localparam CLOCKS_PER_BIT = 87;
    localparam BIT_PERIOD_NS = CLOCKS_PER_BIT * CLOCK_PERIOD_NS;


    reg clk = 0;
    reg ext_clk = 0;
    reg rst = 1;

    reg enable_0 = 0;
    reg enable_1 = 0;
    
    reg [2:0] config_address_0 = 0;
    reg [2:0] config_address_1 = 0;
    
    reg config_write_enable_0 = 0;
    reg config_write_enable_1 = 0;
    
    reg [7:0] write_data_0 = 0;
    reg [7:0] write_data_1 = 0;

    wire [7:0] read_data_0;
    wire [7:0] read_data_1;

    wire tx0;
    wire rx0 = 1;
    wire tx1 = 1;




    wire rx_data_int_0;
    wire tx_done_int_0;
    wire rx_error_int_0;

    wire rx_data_int_1;
    wire tx_done_int_1;
    wire rx_error_int_1;

    uart uart_0(
        .clk(clk),
        .rst(rst),
        .enable(enable_0),
        .write_enable(config_write_enable_0),
        .address(config_address_0),
        .write_data(write_data_0),
        .read_data(read_data_0),
        .rx(rx0),
        .tx(tx0),
        .rx_data_int(rx_data_int_0),
        .tx_done_int(tx_done_int_0),
        .rx_error_int(rx_error_int_0)
   );

    uart uart_1(
        .clk(clk),
        .rst(rst),
        .enable(enable_1),
        .write_enable(config_write_enable_1),
        .address(config_address_1),
        .write_data(write_data_1),
        .read_data(read_data_1),
        .rx(tx0),
        .tx(tx1),
        .rx_data_int(rx_data_int_1),
        .tx_done_int(tx_done_int_1),
        .rx_error_int(rx_error_int_1)
   );

  

    always 
        #(CLOCK_PERIOD_NS/2) clk <= !clk;

    initial 
    begin
        $dumpfile("uart_tb.vcd");
        $dumpvars;

        rst = 0;
        #(CLOCK_PERIOD_NS*2);
        rst = 1;
        #(CLOCK_PERIOD_NS*2);



    
        enable_0 = 1;
        enable_1 = 0;
 
        config_write_enable_0 = 1;
        config_write_enable_1 = 0;

        config_address_0 = 0;
        write_data_0 = 8'b0_0_100_100;
        #(CLOCK_PERIOD_NS*2);

        config_address_0 = 1;
        write_data_0 = 8'b0_0_1_0_0_0_0_0;

        #(CLOCK_PERIOD_NS*2);

        config_address_0 = 2;
        write_data_0 = 8'hAB;


        #(CLOCK_PERIOD_NS*2);


        enable_0 = 0;
        enable_1 = 1;

        config_write_enable_0 = 0;
        config_write_enable_1 = 1;


        config_address_1 = 0;
        write_data_1 = 8'b0_1_100_100;

        #(CLOCK_PERIOD_NS*2);

        config_address_1 = 1;
        write_data_1 = 8'b1_1_0_0_0_0_0_0;



        #(CLOCK_PERIOD_NS*2);

        enable_0 = 1;
        enable_1 = 1;

        config_write_enable_0 = 1;
        config_write_enable_1 = 0;

        config_address_1 = 3;
        
        config_address_0 = 0;
        write_data_0 = 8'b1_0_100_100;

        #(BIT_PERIOD_NS*15);

        $finish;
    end




endmodule