data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v
1: b'%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:17: Cannot find include file: /project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v\n    `include "/project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v" \n             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/422650017/verilog/rtl/elpis,data/full_repos/permissive/422650017//project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v\n             data/full_repos/permissive/422650017/verilog/rtl/elpis,data/full_repos/permissive/422650017//project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v.v\n             data/full_repos/permissive/422650017/verilog/rtl/elpis,data/full_repos/permissive/422650017//project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v.sv\n             /project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v\n             /project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v.v\n             /project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v.sv\n             obj_dir//project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v\n             obj_dir//project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v.v\n             obj_dir//project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v.sv\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:56: Define or directive not defined: \'`FUNCT3_BRANCH_NO\'\n  branch_code = `FUNCT3_BRANCH_NO;\n                ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:56: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  branch_code = `FUNCT3_BRANCH_NO;\n                                 ^\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:69: Define or directive not defined: \'`OPCODE_AL\'\n   `OPCODE_AL: begin\n   ^~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:69: syntax error, unexpected \':\', expecting endcase\n   `OPCODE_AL: begin\n             ^\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:71: Define or directive not defined: \'`FUNCT3_OP_ADD_SUB\'\n     `FUNCT3_OP_ADD_SUB: begin\n     ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:73: Define or directive not defined: \'`NOP\'\n      if (instr != `NOP) begin\n                   ^~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:73: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      if (instr != `NOP) begin\n                       ^\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:77: Define or directive not defined: \'`FUNCT7_OP_ADD\'\n       `FUNCT7_OP_ADD: begin\n       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:77: syntax error, unexpected \':\', expecting endcase\n       `FUNCT7_OP_ADD: begin\n                     ^\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:78: Define or directive not defined: \'`ALU_OP_ADD\'\n        op_alu = `ALU_OP_ADD;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:80: Define or directive not defined: \'`FUNCT7_OP_SUB\'\n       `FUNCT7_OP_SUB: begin\n       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:81: Define or directive not defined: \'`ALU_OP_SUB\'\n        op_alu = `ALU_OP_SUB;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:83: Define or directive not defined: \'`FUNCT7_OP_MUL\'\n       `FUNCT7_OP_MUL: begin\n       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:84: Define or directive not defined: \'`ALU_OP_MUL\'\n                    op_alu = `ALU_OP_MUL;\n                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:92: Define or directive not defined: \'`FUNCT3_OP_OR\'\n     `FUNCT3_OP_OR: begin\n     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:95: Define or directive not defined: \'`ALU_OP_OR\'\n      op_alu = `ALU_OP_OR;\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:97: Define or directive not defined: \'`FUNCT3_OP_XOR\'\n     `FUNCT3_OP_XOR: begin\n     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:100: Define or directive not defined: \'`ALU_OP_XOR\'\n      op_alu = `ALU_OP_XOR;\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:102: Define or directive not defined: \'`FUNCT3_OP_AND\'\n     `FUNCT3_OP_AND: begin\n     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:105: Define or directive not defined: \'`ALU_OP_AND\'\n      op_alu = `ALU_OP_AND;\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:107: Define or directive not defined: \'`FUNCT3_OP_SLL\'\n     `FUNCT3_OP_SLL: begin\n     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:110: Define or directive not defined: \'`ALU_OP_SLL\'\n      op_alu = `ALU_OP_SLL;\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:112: Define or directive not defined: \'`FUNCT3_OP_SRL_SRA\'\n     `FUNCT3_OP_SRL_SRA: begin\n     ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:116: Define or directive not defined: \'`FUNCT7_OP_SRL\'\n       `FUNCT7_OP_SRL: begin\n       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:116: syntax error, unexpected \':\', expecting endcase\n       `FUNCT7_OP_SRL: begin\n                     ^\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:117: Define or directive not defined: \'`ALU_OP_SRL\'\n        op_alu = `ALU_OP_SRL;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:119: Define or directive not defined: \'`FUNCT7_OP_SRA\'\n       `FUNCT7_OP_SRA: begin\n       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:120: Define or directive not defined: \'`ALU_OP_SRA\'\n        op_alu = `ALU_OP_SRA;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:132: Define or directive not defined: \'`OPCODE_ALI\'\n   `OPCODE_ALI: begin\n   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:137: Define or directive not defined: \'`FUNCT3_OP_ADD_SUB\'\n     `FUNCT3_OP_ADD_SUB: begin\n     ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:137: syntax error, unexpected \':\', expecting endcase\n     `FUNCT3_OP_ADD_SUB: begin\n                       ^\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:139: Define or directive not defined: \'`ALU_OP_ADD\'\n      op_alu = `ALU_OP_ADD;\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:141: Define or directive not defined: \'`FUNCT3_OP_OR\'\n     `FUNCT3_OP_OR: begin\n     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:143: Define or directive not defined: \'`ALU_OP_OR\'\n      op_alu = `ALU_OP_OR;\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:145: Define or directive not defined: \'`FUNCT3_OP_XOR\'\n     `FUNCT3_OP_XOR: begin\n     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:147: Define or directive not defined: \'`ALU_OP_XOR\'\n      op_alu = `ALU_OP_XOR;\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:149: Define or directive not defined: \'`FUNCT3_OP_AND\'\n     `FUNCT3_OP_AND: begin\n     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:151: Define or directive not defined: \'`ALU_OP_AND\'\n      op_alu = `ALU_OP_AND;\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:153: Define or directive not defined: \'`FUNCT3_OP_SLL\'\n     `FUNCT3_OP_SLL: begin\n     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:155: Define or directive not defined: \'`ALU_OP_SLL\'\n      op_alu = `ALU_OP_SLL;\n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:157: Define or directive not defined: \'`FUNCT3_OP_SRL_SRA\'\n     `FUNCT3_OP_SRL_SRA: begin\n     ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:160: Define or directive not defined: \'`FUNCT7_OP_SRL\'\n       `FUNCT7_OP_SRL: begin\n       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:160: syntax error, unexpected \':\', expecting endcase\n       `FUNCT7_OP_SRL: begin\n                     ^\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:161: Define or directive not defined: \'`ALU_OP_SRL\'\n        op_alu = `ALU_OP_SRL;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:163: Define or directive not defined: \'`FUNCT7_OP_SRA\'\n       `FUNCT7_OP_SRA: begin\n       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:164: Define or directive not defined: \'`ALU_OP_SRA\'\n        op_alu = `ALU_OP_SRA;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:178: Define or directive not defined: \'`OPCODE_LD\'\n   `OPCODE_LD: begin\n   ^~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:182: Define or directive not defined: \'`ALU_OP_ADD\'\n    op_alu = `ALU_OP_ADD;\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/decoder.v:186: Define or directive not defined: \'`FUNCT3_OP_LB\'\n      `FUNCT3_OP_LB:\n      ^~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module decoder(
	input rst,
	input[31:0] instr,
	output reg[3:0] op_alu,
	output reg wrd_reg,
	output reg[4:0] addr_d,
	output reg rb_immed,
	output reg[31:0] imm,
	output reg mem_to_reg,
	output reg wrd_mem,
	output reg[2:0] branch_code,
	output reg is_a_jump,
	output reg is_byte,
	output reg[1:0] is_mov,
	output reg is_illegal,
	output reg is_tlbwrite,
	output reg is_iret,
	output reg is_ecall,
	output reg[6:0] io_code
);

	wire[6:0] opcode = instr[6:0];
	wire[4:0] reg_dest = instr[11:7];
	wire[2:0] funct3 = instr[14:12];
	wire[6:0] funct7 = instr[31:25];
	wire[4:0] shamt = instr[24:20];
	wire[11:0] ld_ali_immediate = instr[31:20];
	wire[11:0] st_immediate = {instr[31:25], instr[11:7]};
	wire[12:0] branch_inmediate = {instr[31], instr[7], instr[30:25], instr[11:8], 1'b0};
	wire[19:0] jump_inmediate = {instr[31:20], instr[14:7]};

	always@(*) begin
		wrd_reg = 0;
		wrd_mem = 0;
		rb_immed = 0;
		mem_to_reg = 0;
		branch_code = `FUNCT3_BRANCH_NO;
		is_a_jump = 0;
		is_byte = 0;
		is_mov = 0;
		is_illegal = 0;
		is_tlbwrite = 0;
		is_iret = 0;
		is_ecall = 0;
		io_code = 7'b0;
		op_alu = 0;
		imm = 32'b0;
		addr_d = 5'b0;
		case(opcode)
			`OPCODE_AL: begin
				case(funct3)
					`FUNCT3_OP_ADD_SUB: begin
						addr_d = reg_dest;
						if (instr != `NOP) begin
						  wrd_reg = 1;
						end
						case(funct7)
							`FUNCT7_OP_ADD: begin
								op_alu = `ALU_OP_ADD;
							end
							`FUNCT7_OP_SUB: begin
								op_alu = `ALU_OP_SUB;
							end
							`FUNCT7_OP_MUL: begin
               					op_alu = `ALU_OP_MUL;
							end
							default: begin
								is_illegal = 1;
								wrd_reg = 0;
							end
						endcase
					end
					`FUNCT3_OP_OR: begin
						addr_d = reg_dest;
						wrd_reg = 1;
						op_alu = `ALU_OP_OR;
					end
					`FUNCT3_OP_XOR: begin
						addr_d = reg_dest;
						wrd_reg = 1;
						op_alu = `ALU_OP_XOR;
					end
					`FUNCT3_OP_AND: begin
						addr_d = reg_dest;
						wrd_reg = 1;
						op_alu = `ALU_OP_AND;
					end
					`FUNCT3_OP_SLL: begin
						addr_d = reg_dest;
						wrd_reg = 1;
						op_alu = `ALU_OP_SLL;
					end
					`FUNCT3_OP_SRL_SRA: begin
						addr_d = reg_dest;
						wrd_reg = 1;
						case(funct7) 
							`FUNCT7_OP_SRL: begin
								op_alu = `ALU_OP_SRL;
							end
							`FUNCT7_OP_SRA: begin
								op_alu = `ALU_OP_SRA;
							end
							default: begin
								wrd_reg = 0;
								is_illegal = 1;
							end
						endcase
					end
					default:
						is_illegal = 1;
				endcase
			end
			`OPCODE_ALI: begin
				rb_immed = 1;
				addr_d = reg_dest;
				wrd_reg = 1;
				case(funct3)
					`FUNCT3_OP_ADD_SUB: begin
						imm = $signed(ld_ali_immediate);
						op_alu = `ALU_OP_ADD;
					end
					`FUNCT3_OP_OR: begin
						imm = $signed(ld_ali_immediate);
						op_alu = `ALU_OP_OR;
					end
					`FUNCT3_OP_XOR: begin
						imm = $signed(ld_ali_immediate);
						op_alu = `ALU_OP_XOR;
					end
					`FUNCT3_OP_AND: begin
						imm = $signed(ld_ali_immediate);
						op_alu = `ALU_OP_AND;
					end
					`FUNCT3_OP_SLL: begin
						imm = $signed(shamt);
						op_alu = `ALU_OP_SLL;
					end
					`FUNCT3_OP_SRL_SRA: begin
						imm = $signed(shamt);
						case(funct7) 
							`FUNCT7_OP_SRL: begin
								op_alu = `ALU_OP_SRL;
							end
							`FUNCT7_OP_SRA: begin
								op_alu = `ALU_OP_SRA;
							end
							default: begin
								wrd_reg = 0;
								is_illegal = 1;
							end
						endcase
					end
					default: begin
						is_illegal = 1;
						wrd_reg = 0;
					end
				endcase
			end
			`OPCODE_LD: begin
				wrd_reg = 1;
				mem_to_reg = 1;
				rb_immed = 1;
				op_alu = `ALU_OP_ADD;
				addr_d = reg_dest;
				imm = $signed(ld_ali_immediate);
				case (funct3)
				  `FUNCT3_OP_LB:
				   	is_byte = 1;
				  `FUNCT3_OP_LW: begin
					is_byte = 0;
				   end
				  default:
					is_illegal = 1;
				endcase
			end
			`OPCODE_ST: begin
				wrd_mem = 1;
				rb_immed = 1;
				op_alu = `ALU_OP_ADD;
				imm = $signed(st_immediate);
				case (funct3)
					`FUNCT3_OP_SB:
						is_byte = 1;
					`FUNCT3_OP_SW: begin

				  	end
					default:
						is_illegal = 1;
				endcase
			end
			`OPCODE_BRANCH: begin
				op_alu = `ALU_OP_BRANCH;
				rb_immed = 1;
				imm = $signed(branch_inmediate);
				branch_code = funct3;
				case(funct3)
					`FUNCT3_BRANCH_BEQ: begin

					end
					`FUNCT3_BRANCH_BNE: begin

					end
					`FUNCT3_BRANCH_BLT: begin

					end
					`FUNCT3_BRANCH_BGE: begin
						
					end
					default:
						is_illegal = 1;
				endcase
			end
			`OPCODE_JUMP: begin
				is_a_jump = 1;
				op_alu = `ALU_OP_BRANCH;
				rb_immed = 1;
				imm = $signed(jump_inmediate);
			end
			`OPCODE_MOV: begin
				op_alu = `ALU_OP_ADD;
				addr_d = reg_dest;
				case(funct7)
					`FUNCT7_MOV_RM_TO_REGULAR: begin
						wrd_reg = 1;
						is_mov = `MOV_RM_TO_REGULAR; 
					end
					`FUNCT7_MOV_REGULAR_TO_RM: begin
						is_mov = `MOV_REGULAR_TO_RM;
					end
					default:
						is_illegal = 1;
				endcase
			end
			`OPCODE_TLBWRITE: begin
				op_alu = `ALU_OP_ADD;
				is_tlbwrite = 1;
			end
			`OPCODE_IRET: begin
				is_a_jump = 1;
				is_iret = 1;
				op_alu = `ALU_OP_ADD;
			end
			`OPCODE_ECALL: begin
				imm = $signed(ld_ali_immediate);
				rb_immed = 1;
				is_ecall = 1;
				op_alu = `ALU_OP_ADD;
			end
			`OPCODE_IO: begin
				wrd_reg = 0;
				case(funct7)
					`FUNCT7_IO_PRINT_HEX: begin
						io_code = `FUNCT7_IO_PRINT_HEX;
					end
					`FUNCT7_IO_READ_SW: begin
						io_code = `FUNCT7_IO_READ_SW;
					end
					default:
						is_illegal = 1;
				endcase
			end
			default: 
				if (rst) is_illegal = 0;
				else is_illegal = 1;
		endcase
	end
	
endmodule
module decoder(
	input rst,
	input[31:0] instr,
	output reg[3:0] op_alu,
	output reg wrd_reg,
	output reg[4:0] addr_d,
	output reg rb_immed,
	output reg[31:0] imm,
	output reg mem_to_reg,
	output reg wrd_mem,
	output reg[2:0] branch_code,
	output reg is_a_jump,
	output reg is_byte,
	output reg[1:0] is_mov,
	output reg is_illegal,
	output reg is_tlbwrite,
	output reg is_iret,
	output reg is_ecall,
	output reg[6:0] io_code
);


	wire[6:0] opcode = instr[6:0];
	wire[4:0] reg_dest = instr[11:7];
	wire[2:0] funct3 = instr[14:12];
	wire[6:0] funct7 = instr[31:25];
	wire[4:0] shamt = instr[24:20];
	wire[11:0] ld_ali_immediate = instr[31:20];
	wire[11:0] st_immediate = {instr[31:25], instr[11:7]};
	wire[12:0] branch_inmediate = {instr[31], instr[7], instr[30:25], instr[11:8], 1'b0};
	wire[19:0] jump_inmediate = {instr[31:20], instr[14:7]};

	always@(*) begin
		wrd_reg = 0;
		wrd_mem = 0;
		rb_immed = 0;
		mem_to_reg = 0;
		branch_code = `FUNCT3_BRANCH_NO;
		is_a_jump = 0;
		is_byte = 0;
		is_mov = 0;
		is_illegal = 0;
		is_tlbwrite = 0;
		is_iret = 0;
		is_ecall = 0;
		io_code = 7'b0;
		op_alu = 0;
		imm = 32'b0;
		addr_d = 5'b0;
		case(opcode)
			`OPCODE_AL: begin
				case(funct3)
					`FUNCT3_OP_ADD_SUB: begin
						addr_d = reg_dest;
						if (instr != `NOP) begin
						  wrd_reg = 1;
						end
						case(funct7)
							`FUNCT7_OP_ADD: begin
								op_alu = `ALU_OP_ADD;
							end
							`FUNCT7_OP_SUB: begin
								op_alu = `ALU_OP_SUB;
							end
							`FUNCT7_OP_MUL: begin
               					op_alu = `ALU_OP_MUL;
							end
							default: begin
								is_illegal = 1;
								wrd_reg = 0;
							end
						endcase
					end
					`FUNCT3_OP_OR: begin
						addr_d = reg_dest;
						wrd_reg = 1;
						op_alu = `ALU_OP_OR;
					end
					`FUNCT3_OP_XOR: begin
						addr_d = reg_dest;
						wrd_reg = 1;
						op_alu = `ALU_OP_XOR;
					end
					`FUNCT3_OP_AND: begin
						addr_d = reg_dest;
						wrd_reg = 1;
						op_alu = `ALU_OP_AND;
					end
					`FUNCT3_OP_SLL: begin
						addr_d = reg_dest;
						wrd_reg = 1;
						op_alu = `ALU_OP_SLL;
					end
					`FUNCT3_OP_SRL_SRA: begin
						addr_d = reg_dest;
						wrd_reg = 1;
						case(funct7) 
							`FUNCT7_OP_SRL: begin
								op_alu = `ALU_OP_SRL;
							end
							`FUNCT7_OP_SRA: begin
								op_alu = `ALU_OP_SRA;
							end
							default: begin
								wrd_reg = 0;
								is_illegal = 1;
							end
						endcase
					end
					default:
						is_illegal = 1;
				endcase
			end
			`OPCODE_ALI: begin
				rb_immed = 1;
				addr_d = reg_dest;
				wrd_reg = 1;
				case(funct3)
					`FUNCT3_OP_ADD_SUB: begin
						imm = $signed(ld_ali_immediate);
						op_alu = `ALU_OP_ADD;
					end
					`FUNCT3_OP_OR: begin
						imm = $signed(ld_ali_immediate);
						op_alu = `ALU_OP_OR;
					end
					`FUNCT3_OP_XOR: begin
						imm = $signed(ld_ali_immediate);
						op_alu = `ALU_OP_XOR;
					end
					`FUNCT3_OP_AND: begin
						imm = $signed(ld_ali_immediate);
						op_alu = `ALU_OP_AND;
					end
					`FUNCT3_OP_SLL: begin
						imm = $signed(shamt);
						op_alu = `ALU_OP_SLL;
					end
					`FUNCT3_OP_SRL_SRA: begin
						imm = $signed(shamt);
						case(funct7) 
							`FUNCT7_OP_SRL: begin
								op_alu = `ALU_OP_SRL;
							end
							`FUNCT7_OP_SRA: begin
								op_alu = `ALU_OP_SRA;
							end
							default: begin
								wrd_reg = 0;
								is_illegal = 1;
							end
						endcase
					end
					default: begin
						is_illegal = 1;
						wrd_reg = 0;
					end
				endcase
			end
			`OPCODE_LD: begin
				wrd_reg = 1;
				mem_to_reg = 1;
				rb_immed = 1;
				op_alu = `ALU_OP_ADD;
				addr_d = reg_dest;
				imm = $signed(ld_ali_immediate);
				case (funct3)
				  `FUNCT3_OP_LB:
				   	is_byte = 1;
				  `FUNCT3_OP_LW: begin
					is_byte = 0;
				   end
				  default:
					is_illegal = 1;
				endcase
			end
			`OPCODE_ST: begin
				wrd_mem = 1;
				rb_immed = 1;
				op_alu = `ALU_OP_ADD;
				imm = $signed(st_immediate);
				case (funct3)
					`FUNCT3_OP_SB:
						is_byte = 1;
					`FUNCT3_OP_SW: begin

				  	end
					default:
						is_illegal = 1;
				endcase
			end
			`OPCODE_BRANCH: begin
				op_alu = `ALU_OP_BRANCH;
				rb_immed = 1;
				imm = $signed(branch_inmediate);
				branch_code = funct3;
				case(funct3)
					`FUNCT3_BRANCH_BEQ: begin

					end
					`FUNCT3_BRANCH_BNE: begin

					end
					`FUNCT3_BRANCH_BLT: begin

					end
					`FUNCT3_BRANCH_BGE: begin
						
					end
					default:
						is_illegal = 1;
				endcase
			end
			`OPCODE_JUMP: begin
				is_a_jump = 1;
				op_alu = `ALU_OP_BRANCH;
				rb_immed = 1;
				imm = $signed(jump_inmediate);
			end
			`OPCODE_MOV: begin
				op_alu = `ALU_OP_ADD;
				addr_d = reg_dest;
				case(funct7)
					`FUNCT7_MOV_RM_TO_REGULAR: begin
						wrd_reg = 1;
						is_mov = `MOV_RM_TO_REGULAR; 
					end
					`FUNCT7_MOV_REGULAR_TO_RM: begin
						is_mov = `MOV_REGULAR_TO_RM;
					end
					default:
						is_illegal = 1;
				endcase
			end
			`OPCODE_TLBWRITE: begin
				op_alu = `ALU_OP_ADD;
				is_tlbwrite = 1;
			end
			`OPCODE_IRET: begin
				is_a_jump = 1;
				is_iret = 1;
				op_alu = `ALU_OP_ADD;
			end
			`OPCODE_ECALL: begin
				imm = $signed(ld_ali_immediate);
				rb_immed = 1;
				is_ecall = 1;
				op_alu = `ALU_OP_ADD;
			end
			`OPCODE_IO: begin
				wrd_reg = 0;
				case(funct7)
					`FUNCT7_IO_PRINT_HEX: begin
						io_code = `FUNCT7_IO_PRINT_HEX;
					end
					`FUNCT7_IO_READ_SW: begin
						io_code = `FUNCT7_IO_READ_SW;
					end
					default:
						is_illegal = 1;
				endcase
			end
			default: 
				if (rst) is_illegal = 0;
				else is_illegal = 1;
		endcase
	end
	
endmodule