data/full_repos/permissive/42149584/hw1problem3/hw1problem3.v
data/verilator_xmls/a30b9038-8813-4e2f-89ae-bba0925158b4.xml
module hw1problem3(X, Z, RESET, CLOCK);
	input X, RESET, CLOCK;
	output Z;
	
	reg Q1;
	reg Q0;
	wire D1;
	wire D0;
	
	always @ (posedge CLOCK)
		if (RESET == 1) begin Q1 <= 0; Q0 <= 0; end
		else begin Q1 <= D1; Q0 <= D0; end

	assign Z = Q1 & Q0;

	assign D1 = ~X & Q1 & ~Q0 | X & Q0;
	assign D0 = ~X;

endmodule
module hw1problem3(X, Z, RESET, CLOCK);

	input X, RESET, CLOCK;
	output Z;
	
	reg Q1;
	reg Q0;
	wire D1;
	wire D0;
	
	always @ (posedge CLOCK)
		if (RESET == 1) begin Q1 <= 0; Q0 <= 0; end
		else begin Q1 <= D1; Q0 <= D0; end

	assign Z = Q1 & Q0;

	assign D1 = ~X & Q1 & ~Q0 | X & Q0;
	assign D0 = ~X;

endmodule