data/full_repos/permissive/43264243/testbench_uart.v
1: b'%Error: data/full_repos/permissive/43264243/testbench_uart.v:47: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, testbench); \n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/43264243/testbench_uart.v:52: Unsupported: Ignoring delay on this delayed statement.\n  # 10\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/43264243/testbench_uart.v:54: Unsupported: Ignoring delay on this delayed statement.\n  # 10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43264243/testbench_uart.v:56: Unsupported: Ignoring delay on this delayed statement.\n  # 10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43264243/testbench_uart.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #8700\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43264243/testbench_uart.v:61: Unsupported: Ignoring delay on this delayed statement.\n  # 10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43264243/testbench_uart.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #100000 $finish; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43264243/testbench_uart.v:68: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = ~clk;\n        ^\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
  

	reg clk; 
	reg clk184;
	reg ce;
	reg rstn;
	reg load;
	reg [7:0] inbyte;
	
	wire busy;
	
	utx utx0(
		.clk(clk),
		.rstn(rstn),
		.inbyte(inbyte),
		.load(load),
		.busy(busy)
	);


	initial begin
		$dumpvars(0, testbench);	
		clk = 0;
		rstn = 0;
		load = 0;
		inbyte = 8'h55;
		# 10
		rstn = 1;
		# 10
		load = 1;
		# 10
		load = 0;
		#8700
		inbyte = 8'haa;
		load = 1;
		# 10
		load = 0;
		
		
		#100000 $finish; 
	end
 
	always #5 clk = ~clk;

endmodule
module testbench;

  

	reg clk; 
	reg clk184;
	reg ce;
	reg rstn;
	reg load;
	reg [7:0] inbyte;
	
	wire busy;
	
	utx utx0(
		.clk(clk),
		.rstn(rstn),
		.inbyte(inbyte),
		.load(load),
		.busy(busy)
	);


	initial begin
		$dumpvars(0, testbench);	
		clk = 0;
		rstn = 0;
		load = 0;
		inbyte = 8'h55;
		# 10
		rstn = 1;
		# 10
		load = 1;
		# 10
		load = 0;
		#8700
		inbyte = 8'haa;
		load = 1;
		# 10
		load = 0;
		
		
		#100000 $finish; 
	end
 
	always #5 clk = ~clk;

endmodule