data/full_repos/permissive/52900389/TB_MDF.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/52900389/TB_MDF.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/52900389/TB_MDF.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #10000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52900389/TB_MDF.v:59: Unsupported: Ignoring delay on this delayed statement.\n always #1000 clk = ~clk;\n        ^\n%Error: data/full_repos/permissive/52900389/TB_MDF.v:38: Cannot find file containing module: \'MDF\'\n MDF uut (\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/52900389,data/full_repos/permissive/52900389/MDF\n             data/full_repos/permissive/52900389,data/full_repos/permissive/52900389/MDF.v\n             data/full_repos/permissive/52900389,data/full_repos/permissive/52900389/MDF.sv\n             MDF\n             MDF.v\n             MDF.sv\n             obj_dir/MDF\n             obj_dir/MDF.v\n             obj_dir/MDF.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TB_MDF;


	reg clk;
	reg rst;
	reg [3:0] entrada;


	wire salida;
	wire [15:0]q;



	MDF uut (
		.clk(clk), 
		.rst(rst), 
		.entrada(entrada), 
		.salida(salida),
		.q(q)
	);
  
	initial begin

		clk = 0;
		rst = 0;
		entrada = 0;
		


		#10;
		entrada = 4'b1111;
		#10000;
		entrada = 4'b1010;
	end      
	always #1000 clk = ~clk;
	 

endmodule
module TB_MDF;



	reg clk;
	reg rst;
	reg [3:0] entrada;


	wire salida;
	wire [15:0]q;



	MDF uut (
		.clk(clk), 
		.rst(rst), 
		.entrada(entrada), 
		.salida(salida),
		.q(q)
	);
  
	initial begin

		clk = 0;
		rst = 0;
		entrada = 0;
		


		#10;
		entrada = 4'b1111;
		#10000;
		entrada = 4'b1010;
	end      
	always #1000 clk = ~clk;
	 

endmodule