data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/bram_mem.v
1: b'%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/bram_mem.v:33: Cannot find include file: nf_sume_blueswitch_register_define.v\n`include "nf_sume_blueswitch_register_define.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog,data/full_repos/permissive/498471995/nf_sume_blueswitch_register_define.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog,data/full_repos/permissive/498471995/nf_sume_blueswitch_register_define.v.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog,data/full_repos/permissive/498471995/nf_sume_blueswitch_register_define.v.sv\n             nf_sume_blueswitch_register_define.v\n             nf_sume_blueswitch_register_define.v.v\n             nf_sume_blueswitch_register_define.v.sv\n             obj_dir/nf_sume_blueswitch_register_define.v\n             obj_dir/nf_sume_blueswitch_register_define.v.v\n             obj_dir/nf_sume_blueswitch_register_define.v.sv\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/bram_mem.v:34: Cannot find include file: nf_sume_blueswitch_parameter_define.v\n`include "nf_sume_blueswitch_parameter_define.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module bram_mem
#(
   parameter   ADDR_WIDTH   =  32,
   parameter   DATA_WIDTH   =  32
)
(
   input                         CLK,
   input                         WR,
   input    [ADDR_WIDTH-1:0]     ADDR_WR,
   input    [DATA_WIDTH-1:0]     DIN,
   input                         RD,
   input    [ADDR_WIDTH-1:0]     ADDR_RD,
   output   [DATA_WIDTH-1:0]     DOUT
);

(* RAM_STYLE = "BLOCK" *)
reg   [DATA_WIDTH-1:0]  mem[(2**ADDR_WIDTH)-1:0];
reg   [DATA_WIDTH-1:0]  rd_data;

always @(posedge CLK) begin
   if (WR)  mem[ADDR_WR]   <= DIN;
end

always @(posedge CLK) begin
   if (RD & WR & (ADDR_WR == ADDR_RD))  rd_data <= DIN;
   else if (RD) rd_data <= mem[ADDR_RD];
end
      
assign   DOUT  =  rd_data;

endmodule
module bram_mem
#(
   parameter   ADDR_WIDTH   =  32,
   parameter   DATA_WIDTH   =  32
)
(
   input                         CLK,
   input                         WR,
   input    [ADDR_WIDTH-1:0]     ADDR_WR,
   input    [DATA_WIDTH-1:0]     DIN,
   input                         RD,
   input    [ADDR_WIDTH-1:0]     ADDR_RD,
   output   [DATA_WIDTH-1:0]     DOUT
);


(* RAM_STYLE = "BLOCK" *)
reg   [DATA_WIDTH-1:0]  mem[(2**ADDR_WIDTH)-1:0];
reg   [DATA_WIDTH-1:0]  rd_data;

always @(posedge CLK) begin
   if (WR)  mem[ADDR_WR]   <= DIN;
end

always @(posedge CLK) begin
   if (RD & WR & (ADDR_WR == ADDR_RD))  rd_data <= DIN;
   else if (RD) rd_data <= mem[ADDR_RD];
end
      
assign   DOUT  =  rd_data;

endmodule