data/full_repos/permissive/441359809/src/yosys/tests/hana/test_parser.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_parser.v:7: Multiple top level modules\n                                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                            : ... Top module \'f1_test\'\nmodule f1_test;\n       ^~~~~~~\n                                                                                            : ... Top module \'f2_test\'\nmodule f2_test #( parameter v2kparam = 5)\n       ^~~~~~~\n                                                                                            : ... Top module \'f3_test\'\nmodule f3_test(in, out, io, vin, vout, vio);\n       ^~~~~~~\n                                                                                            : ... Top module \'f4_ahmad\'\nmodule f4_ahmad();\n       ^~~~~~~~\n                                                                                            : ... Top module \'f5_test\'\nmodule f5_test(out, i0, i1, i2, i3, s1, s0);\n       ^~~~~~~\n                                                                                            : ... Top module \'f5_ternaryop\'\nmodule f5_ternaryop(out, i0, i1, i2, i3, s1, s0);\n       ^~~~~~~~~~~~\n                                                                                            : ... Top module \'f5_fulladd4\'\nmodule f5_fulladd4(sum, c_out, a, b, c_in);\n       ^~~~~~~~~~~\n                                                                                            : ... Top module \'f6_adder\'\nmodule f6_adder(sum , co, a, b, ci);\n       ^~~~~~~~\n                                                                                            : ... Top module \'f7_test\'\nmodule f7_test(q, d, clk, reset);\n       ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_parser.v:67: Operator ADD expects 5 bits on the RHS, but RHS\'s VARREF \'c_in\' generates 1 bits.\n                                                                                          : ... In instance f5_fulladd4\nassign {c_out, sum} = a + b + c_in;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_parser.v:36: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sha\' generates 32 or 4 bits.\n                                                                                          : ... In instance f4_ahmad\nassign w = 10;\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_parser.v:25: Little bit endian vector: MSB < LSB of bit range: 0:3\ninout [0:3] vio;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_parser.v:14: Little bit endian vector: MSB < LSB of bit range: 0:3\ninout [0:3] vio;\n      ^\n%Error: Exiting due to 5 warning(s)\n'
module f5_ternaryop(out, i0, i1, i2, i3, s1, s0);
output out;
input i0, i1, i2, i3;
input s1, s0;

assign out = s1 ? (s0 ? i3 : i2) : (s0 ? i1 : i0);

endmodule
module f5_ternaryop(out, i0, i1, i2, i3, s1, s0);

output out;
input i0, i1, i2, i3;
input s1, s0;

assign out = s1 ? (s0 ? i3 : i2) : (s0 ? i1 : i0);

endmodule