data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Counters/ece241_2014_q7a/top_module_tb.v
1: b'%Error: Cannot find file containing module: Logic/Counters/ece241_2014_q7a,data/full_repos/permissive/500128826\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/ece241_2014_q7a,data/full_repos/permissive/500128826\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/ece241_2014_q7a,data/full_repos/permissive/500128826.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/ece241_2014_q7a,data/full_repos/permissive/500128826.sv\n             Logic/Counters/ece241_2014_q7a,data/full_repos/permissive/500128826\n             Logic/Counters/ece241_2014_q7a,data/full_repos/permissive/500128826.v\n             Logic/Counters/ece241_2014_q7a,data/full_repos/permissive/500128826.sv\n             obj_dir/Logic/Counters/ece241_2014_q7a,data/full_repos/permissive/500128826\n             obj_dir/Logic/Counters/ece241_2014_q7a,data/full_repos/permissive/500128826.v\n             obj_dir/Logic/Counters/ece241_2014_q7a,data/full_repos/permissive/500128826.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Logic/Counters/ece241_2014_q7a/top_module_tb.v\n%Error: Exiting due to 3 error(s)\n'
module top_module_tb ();
  wire [3:0] Q;
  wire c_enable;
  wire c_load;
  wire [3:0] c_d;

  reg clk = 1'd1;
  reg reset = 1'd0;
  reg enable = 1'd0;

  localparam ITERATIONS = 300;

  always begin
    #1 clk = clk + 1;
  end

  always begin
    #20 enable = enable + 1;
  end

  always begin
    #98 reset = reset + 1;
    #2 reset = reset + 1;
  end


  top_module uut (
      .clk(clk),
      .reset(reset),
      .enable(enable),
      .Q(Q),
      .c_enable(c_enable),
      .c_load(c_load),
      .c_d(c_d)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule
module top_module_tb ();

  wire [3:0] Q;
  wire c_enable;
  wire c_load;
  wire [3:0] c_d;

  reg clk = 1'd1;
  reg reset = 1'd0;
  reg enable = 1'd0;

  localparam ITERATIONS = 300;

  always begin
    #1 clk = clk + 1;
  end

  always begin
    #20 enable = enable + 1;
  end

  always begin
    #98 reset = reset + 1;
    #2 reset = reset + 1;
  end


  top_module uut (
      .clk(clk),
      .reset(reset),
      .enable(enable),
      .Q(Q),
      .c_enable(c_enable),
      .c_load(c_load),
      .c_d(c_d)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule