data/full_repos/permissive/527007664/openlane/rlbp/src/rlbp.v
1: b"%Error-ASSIGNIN: data/full_repos/permissive/527007664/openlane/rlbp/src/rlbp.v:245: Assigning to input/const variable: 'ce_d1'\n .ce_d1(ce_d1), \n        ^~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/527007664/openlane/rlbp/src/rlbp.v:246: Assigning to input/const variable: 'ce_d2'\n .ce_d2(ce_d2), \n        ^~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/527007664/openlane/rlbp/src/rlbp.v:247: Assigning to input/const variable: 'ce_d3'\n .ce_d3(ce_d3),\n        ^~~~~\n%Error: Exiting due to 3 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module rlbp (clk, ce_d1, ce_d2, ce_d3, reset, reset_fsm, gpio_start, logic_analyzer_start, control_signals, rlbp_done, data_in, data_sel, data_out, d, q1_3, q1_2, q1_1, q2_3, q2_2, q2_1, q3_3, q3_2, q3_1);
	input clk, ce_d1, ce_d2, ce_d3, reset, gpio_start, logic_analyzer_start, data_in;
	input [1:0] data_sel;  
	input [3:0] d;
	output [3:0] data_out;
	output [1:0] control_signals;
	output reset_fsm, rlbp_done, q1_3, q1_2, q1_1, q2_3, q2_2, q2_1, q3_3, q3_2, q3_1;



	wire ce_d1_net, ce_d2_net, ce_d3_net;
	wire [1:0] sel_net;
	wire [3:0] data_net;
	assign sel_net = control_signals;
	assign data_net = data_out;	
	assign ce_d1_net = ce_d1;
	assign ce_d2_net = ce_d2;
	assign ce_d3_net = ce_d3;
	
	rlbp_fsm inst1(
	.clk(clk), 
	.reset(reset), 
	.reset_fsm(reset_fsm),
	.gpio_start(gpio_start), 
	.logic_analyzer_start(logic_analyzer_start),
	.ce_d1(ce_d1), 
	.ce_d2(ce_d2), 
	.ce_d3(ce_d3),
	.rlbp_done(rlbp_done),
	.control_signals(control_signals)	
	);
	
	shift_register inst2(
	.clk(clk),
	.ce_d1(ce_d1_net), 
	.ce_d2(ce_d2_net), 
	.ce_d3(ce_d3_net),
	.reset(reset),
	.d(data_net),
	.q1_3(q1_3), 
	.q1_2(q1_2), 
	.q1_1(q1_1), 
	.q2_3(q2_3), 
	.q2_2(q2_2), 
	.q2_1(q2_1), 
	.q3_3(q3_3), 
	.q3_2(q3_2), 
	.q3_1(q3_1)
	);
		
	rlbp_demux inst3(
	.data_in(data_in),
	.data_sel(sel_net),
	.data_out(data_out)
	);
	
endmodule
module rlbp (clk, ce_d1, ce_d2, ce_d3, reset, reset_fsm, gpio_start, logic_analyzer_start, control_signals, rlbp_done, data_in, data_sel, data_out, d, q1_3, q1_2, q1_1, q2_3, q2_2, q2_1, q3_3, q3_2, q3_1);

	input clk, ce_d1, ce_d2, ce_d3, reset, gpio_start, logic_analyzer_start, data_in;
	input [1:0] data_sel;  
	input [3:0] d;
	output [3:0] data_out;
	output [1:0] control_signals;
	output reset_fsm, rlbp_done, q1_3, q1_2, q1_1, q2_3, q2_2, q2_1, q3_3, q3_2, q3_1;



	wire ce_d1_net, ce_d2_net, ce_d3_net;
	wire [1:0] sel_net;
	wire [3:0] data_net;
	assign sel_net = control_signals;
	assign data_net = data_out;	
	assign ce_d1_net = ce_d1;
	assign ce_d2_net = ce_d2;
	assign ce_d3_net = ce_d3;
	
	rlbp_fsm inst1(
	.clk(clk), 
	.reset(reset), 
	.reset_fsm(reset_fsm),
	.gpio_start(gpio_start), 
	.logic_analyzer_start(logic_analyzer_start),
	.ce_d1(ce_d1), 
	.ce_d2(ce_d2), 
	.ce_d3(ce_d3),
	.rlbp_done(rlbp_done),
	.control_signals(control_signals)	
	);
	
	shift_register inst2(
	.clk(clk),
	.ce_d1(ce_d1_net), 
	.ce_d2(ce_d2_net), 
	.ce_d3(ce_d3_net),
	.reset(reset),
	.d(data_net),
	.q1_3(q1_3), 
	.q1_2(q1_2), 
	.q1_1(q1_1), 
	.q2_3(q2_3), 
	.q2_2(q2_2), 
	.q2_1(q2_1), 
	.q3_3(q3_3), 
	.q3_2(q3_2), 
	.q3_1(q3_1)
	);
		
	rlbp_demux inst3(
	.data_in(data_in),
	.data_sel(sel_net),
	.data_out(data_out)
	);
	
endmodule