data/full_repos/permissive/448698580/rtl/basics/src/ripple_carry_adder.v
1: b"%Error: data/full_repos/permissive/448698580/rtl/basics/src/ripple_carry_adder.v:14: Cannot find file containing module: 'full_adder'\n        full_adder adder\n        ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/448698580/rtl/basics/src,data/full_repos/permissive/448698580/full_adder\n             data/full_repos/permissive/448698580/rtl/basics/src,data/full_repos/permissive/448698580/full_adder.v\n             data/full_repos/permissive/448698580/rtl/basics/src,data/full_repos/permissive/448698580/full_adder.sv\n             full_adder\n             full_adder.v\n             full_adder.sv\n             obj_dir/full_adder\n             obj_dir/full_adder.v\n             obj_dir/full_adder.sv\n%Error: Exiting due to 1 error(s)\n"
module ripple_carry_adder #(parameter WIDTH = 10)
       (input [WIDTH - 1 : 0] a,
        input [WIDTH - 1 : 0] b,
        output [WIDTH : 0] o_sum);

wire [WIDTH: 0] w_carry;
wire [WIDTH - 1: 0] w_sum;


assign w_carry[0] = 1'b0;
genvar i;
generate
    for (i = 0 ; i < WIDTH ; i = i + 1) begin
        full_adder adder
                   (.x(a[i]),
                    .y(b[i]),
                    .carry_in(w_carry[i]),
                    .carry_out(w_carry[i + 1]),
                    .sum(w_sum[i]));
    end
endgenerate
endmodule
module ripple_carry_adder #(parameter WIDTH = 10)
       (input [WIDTH - 1 : 0] a,
        input [WIDTH - 1 : 0] b,
        output [WIDTH : 0] o_sum);


wire [WIDTH: 0] w_carry;
wire [WIDTH - 1: 0] w_sum;


assign w_carry[0] = 1'b0;
genvar i;
generate
    for (i = 0 ; i < WIDTH ; i = i + 1) begin
        full_adder adder
                   (.x(a[i]),
                    .y(b[i]),
                    .carry_in(w_carry[i]),
                    .carry_out(w_carry[i + 1]),
                    .sum(w_sum[i]));
    end
endgenerate
endmodule