data/full_repos/permissive/435877241/prj_3.v
data/verilator_xmls/0ee0b7b0-391b-4e27-a7a9-ee1a48e9e1a3.xml
module prj_3(
    input [1:0] data,
    output even
    );
    assign even=^data;
endmodule
module prj_3(
    input [1:0] data,
    output even
    );

    assign even=^data;
endmodule