data/full_repos/permissive/512077043/rgb_sbit2wrd/rgb_sbit2wrd.v
data/verilator_xmls/0b744af7-e4e0-476b-9c7e-e9cb14a36314.xml
module  rgb_sbit2wrd
(


    input           clk,
    input           rst,
    input           in_strobe,
    input           in_sbit_value,
    input           in_stream_reset,
    input           in_wr_fifo_full,

    

    output reg [31:0]   out_word,
    output reg          out_strobe,
    output reg          out_wr_fifo_overflow
);

    localparam bnum_first_data_bit  = 5'd23;
    localparam bnum_last_data_bit   = 5'd0;
    localparam bnum_stream_reset    = 5'd30;
    localparam bnum_valid           = 5'd31;

    reg [1:0]       rstff = 2'b00;
    reg [4:0]       bcount = bnum_first_data_bit;
    reg             saw_in_strobe = 1'b0;
    reg             wait_for_stream_reset = 1'b0;
    reg             out_data_stretch = 1'b0;


    always @ (posedge clk) begin

        if (rst == 1'b1) rstff <= 2'b11;
        else             rstff <= {rstff[0], 1'b0};

        if (rstff[1] == 1'b1) begin
            out_word    <= 32'd0;
            out_strobe  <= 1'b0;
            out_data_stretch <= 1'b0;
            out_wr_fifo_overflow <= 1'b0;
            wait_for_stream_reset <= 1'b0;
            saw_in_strobe  <= 1'b0;
            bcount      <= bnum_first_data_bit;
        end else begin
            if ((out_strobe == 1'b1) && (out_data_stretch == 1'b1)) begin
                out_strobe <= 1'b0;
            end else if ((out_strobe == 1'b0) && (out_data_stretch == 1'b1)) begin
                out_data_stretch <= 1'b0;
                out_word[bnum_valid] <= 1'b0;
                out_word[bnum_stream_reset] <= 1'b0;
                bcount <= bnum_first_data_bit;
            end
            if (in_strobe == 1'b0) begin
                saw_in_strobe <= 1'b0;
            end else if ((saw_in_strobe == 1'b0) && (in_strobe == 1'b1)) begin
                saw_in_strobe  <= 1'b1;
                out_word[bcount] <= in_sbit_value;
                out_word[bnum_stream_reset] <= (in_stream_reset | in_wr_fifo_full);
                if ((in_stream_reset == 1'b1) || (bcount == bnum_last_data_bit)) begin
                    if (in_wr_fifo_full == 1'b1) begin
                        out_wr_fifo_overflow <= 1'b1;
                        wait_for_stream_reset <= 1'b1;
                    end else begin
                        if ((1'b0 == wait_for_stream_reset) || ((1'b1 == wait_for_stream_reset) && (1'b1 == in_stream_reset))) begin
                            out_strobe <= 1'b1;
                            out_data_stretch <= 1'b1; 
                            out_word[bnum_valid] <= 1'b1;
                            wait_for_stream_reset <= 1'b0;
                        end
                    end
                    bcount <= bnum_first_data_bit;
                end else begin
                    bcount <= bcount-5'd1;
                end
            end
        end
    end
endmodule
module  rgb_sbit2wrd
(


    input           clk,
    input           rst,
    input           in_strobe,
    input           in_sbit_value,
    input           in_stream_reset,
    input           in_wr_fifo_full,

    

    output reg [31:0]   out_word,
    output reg          out_strobe,
    output reg          out_wr_fifo_overflow
);


    localparam bnum_first_data_bit  = 5'd23;
    localparam bnum_last_data_bit   = 5'd0;
    localparam bnum_stream_reset    = 5'd30;
    localparam bnum_valid           = 5'd31;

    reg [1:0]       rstff = 2'b00;
    reg [4:0]       bcount = bnum_first_data_bit;
    reg             saw_in_strobe = 1'b0;
    reg             wait_for_stream_reset = 1'b0;
    reg             out_data_stretch = 1'b0;


    always @ (posedge clk) begin

        if (rst == 1'b1) rstff <= 2'b11;
        else             rstff <= {rstff[0], 1'b0};

        if (rstff[1] == 1'b1) begin
            out_word    <= 32'd0;
            out_strobe  <= 1'b0;
            out_data_stretch <= 1'b0;
            out_wr_fifo_overflow <= 1'b0;
            wait_for_stream_reset <= 1'b0;
            saw_in_strobe  <= 1'b0;
            bcount      <= bnum_first_data_bit;
        end else begin
            if ((out_strobe == 1'b1) && (out_data_stretch == 1'b1)) begin
                out_strobe <= 1'b0;
            end else if ((out_strobe == 1'b0) && (out_data_stretch == 1'b1)) begin
                out_data_stretch <= 1'b0;
                out_word[bnum_valid] <= 1'b0;
                out_word[bnum_stream_reset] <= 1'b0;
                bcount <= bnum_first_data_bit;
            end
            if (in_strobe == 1'b0) begin
                saw_in_strobe <= 1'b0;
            end else if ((saw_in_strobe == 1'b0) && (in_strobe == 1'b1)) begin
                saw_in_strobe  <= 1'b1;
                out_word[bcount] <= in_sbit_value;
                out_word[bnum_stream_reset] <= (in_stream_reset | in_wr_fifo_full);
                if ((in_stream_reset == 1'b1) || (bcount == bnum_last_data_bit)) begin
                    if (in_wr_fifo_full == 1'b1) begin
                        out_wr_fifo_overflow <= 1'b1;
                        wait_for_stream_reset <= 1'b1;
                    end else begin
                        if ((1'b0 == wait_for_stream_reset) || ((1'b1 == wait_for_stream_reset) && (1'b1 == in_stream_reset))) begin
                            out_strobe <= 1'b1;
                            out_data_stretch <= 1'b1; 
                            out_word[bnum_valid] <= 1'b1;
                            wait_for_stream_reset <= 1'b0;
                        end
                    end
                    bcount <= bnum_first_data_bit;
                end else begin
                    bcount <= bcount-5'd1;
                end
            end
        end
    end
endmodule