data/full_repos/permissive/524616929/tb/tb_core_icarus/tb_top.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/524616929/tb/tb_core_icarus/tb_top.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #2\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/524616929/tb/tb_core_icarus/tb_top.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/524616929/tb/tb_core_icarus/tb_top.v:23: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n%Error: data/full_repos/permissive/524616929/tb/tb_core_icarus/tb_top.v:25: Cannot find file containing module: \'riscv_tcm_top\'\nriscv_tcm_top  u_riscv_tcm_top (\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/524616929/tb/tb_core_icarus,data/full_repos/permissive/524616929/riscv_tcm_top\n             data/full_repos/permissive/524616929/tb/tb_core_icarus,data/full_repos/permissive/524616929/riscv_tcm_top.v\n             data/full_repos/permissive/524616929/tb/tb_core_icarus,data/full_repos/permissive/524616929/riscv_tcm_top.sv\n             riscv_tcm_top\n             riscv_tcm_top.v\n             riscv_tcm_top.sv\n             obj_dir/riscv_tcm_top\n             obj_dir/riscv_tcm_top.v\n             obj_dir/riscv_tcm_top.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_top;

reg clk;
reg rst_n;
wire    [31:0]  mem_d_data_wr_w_test;





initial
begin
    $display("Starting bench");

    clk = 0;
    rst_n = 1;
    #2
    rst_n = 0;
    #20
    rst_n = 1;
end

always #5 clk = ~clk;

riscv_tcm_top  u_riscv_tcm_top (
    .clk                     ( clk                    ),
    .rst_n                   ( rst_n                  ),
    .mem_d_data_wr_w_test    ( mem_d_data_wr_w_test   )
);

endmodule
module tb_top;


reg clk;
reg rst_n;
wire    [31:0]  mem_d_data_wr_w_test;





initial
begin
    $display("Starting bench");

    clk = 0;
    rst_n = 1;
    #2
    rst_n = 0;
    #20
    rst_n = 1;
end

always #5 clk = ~clk;

riscv_tcm_top  u_riscv_tcm_top (
    .clk                     ( clk                    ),
    .rst_n                   ( rst_n                  ),
    .mem_d_data_wr_w_test    ( mem_d_data_wr_w_test   )
);

endmodule