data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_pipelining/cachelib/v_rtl/dut_Mul_8Ux8U_16U_4.v
data/verilator_xmls/deef22a1-1605-4831-b01b-451289d7e3ac.xml
module dut_Mul_8Ux8U_16U_4 (
	in2,
	in1,
	out1
	);
input [7:0] in2,
	in1;
output [15:0] out1;
wire [15:0] asc001;

assign asc001 = 
	+(in1 * in2);

assign out1 = asc001;
endmodule
module dut_Mul_8Ux8U_16U_4 (
	in2,
	in1,
	out1
	);

input [7:0] in2,
	in1;
output [15:0] out1;
wire [15:0] asc001;

assign asc001 = 
	+(in1 * in2);

assign out1 = asc001;
endmodule