data/full_repos/permissive/502764644/mpeg_audio_video/ETHERNET/tb_ETH_ZBT_emulator.v
1: b'%Error: data/full_repos/permissive/502764644/mpeg_audio_video/ETHERNET/tb_ETH_ZBT_emulator.v:17: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502764644/mpeg_audio_video/ETHERNET,data/full_repos/permissive/502764644/defines.v\n             data/full_repos/permissive/502764644/mpeg_audio_video/ETHERNET,data/full_repos/permissive/502764644/defines.v.v\n             data/full_repos/permissive/502764644/mpeg_audio_video/ETHERNET,data/full_repos/permissive/502764644/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/ETHERNET/tb_ETH_ZBT_emulator.v:65: Define or directive not defined: \'`ZBT_input_file\'\n $write("Opening file %s for ZBT read\\n", `ZBT_input_file);\n                                          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/ETHERNET/tb_ETH_ZBT_emulator.v:65: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n $write("Opening file %s for ZBT read\\n", `ZBT_input_file);\n                                                         ^\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/ETHERNET/tb_ETH_ZBT_emulator.v:66: Define or directive not defined: \'`ZBT_input_file\'\n file_pointer = $fopen(`ZBT_input_file, "rb");\n                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/ETHERNET/tb_ETH_ZBT_emulator.v:66: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n file_pointer = $fopen(`ZBT_input_file, "rb");\n                                      ^\n%Error: Exiting due to 5 error(s)\n'
module ZBT_model(
	clock,
	Address,
	Read_data,
	Write_data,
	Write_en
);

input clock;
input [18:0] Address;
output reg [31:0] Read_data;
input [31:0] Write_data;
input Write_en;

reg [31:0] memory [524287:0];
reg [31:0] data_1, data_2, data_3;

always @(posedge clock) begin

	Read_data <= data_3;
	data_3 <= data_2;
	data_2 <= data_1;

	if (Write_en) begin
		memory[Address] <= Write_data;
		data_1 <= Write_data;
	end else data_1 <= memory[Address];	
end

endmodule
module ZBT_model(
	clock,
	Address,
	Read_data,
	Write_data,
	Write_en
);


input clock;
input [18:0] Address;
output reg [31:0] Read_data;
input [31:0] Write_data;
input Write_en;

reg [31:0] memory [524287:0];
reg [31:0] data_1, data_2, data_3;

always @(posedge clock) begin

	Read_data <= data_3;
	data_3 <= data_2;
	data_2 <= data_1;

	if (Write_en) begin
		memory[Address] <= Write_data;
		data_1 <= Write_data;
	end else data_1 <= memory[Address];	
end

endmodule