data/full_repos/permissive/458737381/src/verilog-parser/tests/generate.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/generate.v:7: Cannot find file containing module: 'memory'\n      memory U (read, write, \n      ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/memory\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/memory.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/memory.sv\n             memory\n             memory.v\n             memory.sv\n             obj_dir/memory\n             obj_dir/memory.v\n             obj_dir/memory.sv\n%Error: Exiting due to 1 error(s)\n"
module tb_generate;
genvar i;

generate
    for (i=0; i < 4; i=i+1) begin : MEM
      memory U (read, write, 
                data_in[(i*8)+7:(i*8)], 
                address,data_out[(i*8)+7:(i*8)]);
    end
endgenerate

endmodule
module tb_generate;

genvar i;

generate
    for (i=0; i < 4; i=i+1) begin : MEM
      memory U (read, write, 
                data_in[(i*8)+7:(i*8)], 
                address,data_out[(i*8)+7:(i*8)]);
    end
endgenerate

endmodule