data/full_repos/permissive/502540587/Verilog/SpiritMemory.v
1: b'%Warning-WIDTH: data/full_repos/permissive/502540587/Verilog/SpiritMemory.v:13: Operator SUB expects 27 bits on the RHS, but RHS\'s CONST \'12\'h100\' generates 12 bits.\n                                                                              : ... In instance SpiritMemory\n    wire [11:0] write_address = i_waddr - 12\'h100;\n                                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/502540587/Verilog/SpiritMemory.v:13: Operator ASSIGNW expects 12 bits on the Assign RHS, but Assign RHS\'s SUB generates 27 bits.\n                                                                              : ... In instance SpiritMemory\n    wire [11:0] write_address = i_waddr - 12\'h100;\n                              ^\n%Error: data/full_repos/permissive/502540587/Verilog/SpiritMemory.v:19: Cannot find file containing module: \'spirit_block_mem\'\n    spirit_block_mem spirit_block_mem_inst (\n    ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502540587/Verilog,data/full_repos/permissive/502540587/spirit_block_mem\n             data/full_repos/permissive/502540587/Verilog,data/full_repos/permissive/502540587/spirit_block_mem.v\n             data/full_repos/permissive/502540587/Verilog,data/full_repos/permissive/502540587/spirit_block_mem.sv\n             spirit_block_mem\n             spirit_block_mem.v\n             spirit_block_mem.sv\n             obj_dir/spirit_block_mem\n             obj_dir/spirit_block_mem.v\n             obj_dir/spirit_block_mem.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module SpiritMemory (
    input wire clk,

    input wire [8:0] i_spirit_idx,
    output wire [63:0] o_spirit_position_struct,

    input wire[31:0] i_wdata,
    input wire i_wea,
    input wire [3:0] i_wselect,
    input wire [26:0] i_waddr
);
    wire [3:0] select_with_we = {4{i_wea}} & i_wselect;
    wire [11:0] write_address = i_waddr - 12'h100;

    wire[63:0] raw_spirit_struct;

    assign o_spirit_position_struct = {16'h0, raw_spirit_struct[55:48], raw_spirit_struct[63:56], raw_spirit_struct[15:0], raw_spirit_struct[31:16]};

    spirit_block_mem spirit_block_mem_inst (
        .clka(clk),
        .wea(select_with_we),
        .addra(write_address[11:2]),
        .dina(i_wdata),
        .clkb(clk),
        .addrb(i_spirit_idx),
        .doutb(raw_spirit_struct)
    );
endmodule
module SpiritMemory (
    input wire clk,

    input wire [8:0] i_spirit_idx,
    output wire [63:0] o_spirit_position_struct,

    input wire[31:0] i_wdata,
    input wire i_wea,
    input wire [3:0] i_wselect,
    input wire [26:0] i_waddr
);

    wire [3:0] select_with_we = {4{i_wea}} & i_wselect;
    wire [11:0] write_address = i_waddr - 12'h100;

    wire[63:0] raw_spirit_struct;

    assign o_spirit_position_struct = {16'h0, raw_spirit_struct[55:48], raw_spirit_struct[63:56], raw_spirit_struct[15:0], raw_spirit_struct[31:16]};

    spirit_block_mem spirit_block_mem_inst (
        .clka(clk),
        .wea(select_with_we),
        .addra(write_address[11:2]),
        .dina(i_wdata),
        .clkb(clk),
        .addrb(i_spirit_idx),
        .doutb(raw_spirit_struct)
    );
endmodule