data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/register.v
data/verilator_xmls/b6eb7d4d-6333-4228-bd34-bf0bc2f19684.xml
module register
    #(parameter C_WIDTH = 1,
      parameter C_VALUE = 0
      )
    (input CLK,
     input                RST_IN,
     output [C_WIDTH-1:0] RD_DATA,
     input [C_WIDTH-1:0]  WR_DATA,
     input                WR_EN
     );

    reg [C_WIDTH-1:0]     rData;

    assign RD_DATA = rData;
    always @(posedge CLK) begin
        if(RST_IN) begin
            rData <= C_VALUE;
        end else if(WR_EN) begin
            rData <= WR_DATA;
        end 
    end

endmodule
module register
    #(parameter C_WIDTH = 1,
      parameter C_VALUE = 0
      )
    (input CLK,
     input                RST_IN,
     output [C_WIDTH-1:0] RD_DATA,
     input [C_WIDTH-1:0]  WR_DATA,
     input                WR_EN
     );


    reg [C_WIDTH-1:0]     rData;

    assign RD_DATA = rData;
    always @(posedge CLK) begin
        if(RST_IN) begin
            rData <= C_VALUE;
        end else if(WR_EN) begin
            rData <= WR_DATA;
        end 
    end

endmodule