data/full_repos/permissive/492140037/CPU/设计文件/decode32.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/492140037/CPU/\xe8\xae\xbe\xe8\xae\xa1\xe6\x96\x87\xe4\xbb\xb6/decode32.v:30: Signal definition not found, creating implicitly: \'andi\'\n    assign extend=(andi==1\'b1||ori==1\'b1||xori==1\'b1||Instruction[31:26]==6\'b001001||Instruction[31:26]==6\'b001011)\n                   ^~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/492140037/CPU/\xe8\xae\xbe\xe8\xae\xa1\xe6\x96\x87\xe4\xbb\xb6/decode32.v:30: Signal definition not found, creating implicitly: \'ori\'\n    assign extend=(andi==1\'b1||ori==1\'b1||xori==1\'b1||Instruction[31:26]==6\'b001001||Instruction[31:26]==6\'b001011)\n                               ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/492140037/CPU/\xe8\xae\xbe\xe8\xae\xa1\xe6\x96\x87\xe4\xbb\xb6/decode32.v:30: Signal definition not found, creating implicitly: \'xori\'\n                                                                                      : ... Suggested alternative: \'ori\'\n    assign extend=(andi==1\'b1||ori==1\'b1||xori==1\'b1||Instruction[31:26]==6\'b001001||Instruction[31:26]==6\'b001011)\n                                          ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/492140037/CPU/\xe8\xae\xbe\xe8\xae\xa1\xe6\x96\x87\xe4\xbb\xb6/decode32.v:36: Signal definition not found, creating implicitly: \'lui\'\n    assign lui=Instruction[31:26]==6\'b001111;\n           ^~~\n%Warning-WIDTH: data/full_repos/permissive/492140037/CPU/\xe8\xae\xbe\xe8\xae\xa1\xe6\x96\x87\xe4\xbb\xb6/decode32.v:78: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                                   : ... In instance decode32\n          for(k = 5\'b00000; k <= 5\'b11111; k= k + 5\'b00001) begin\n                ^\n%Warning-WIDTH: data/full_repos/permissive/492140037/CPU/\xe8\xae\xbe\xe8\xae\xa1\xe6\x96\x87\xe4\xbb\xb6/decode32.v:78: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'5\'h1\' generates 5 bits.\n                                                                                   : ... In instance decode32\n          for(k = 5\'b00000; k <= 5\'b11111; k= k + 5\'b00001) begin\n                                                ^\n%Error: Exiting due to 6 warning(s)\n'
module decode32(read_data_1,read_data_2,Instruction,mem_data,ALU_result,
                 Jal,RegWrite,MemtoReg,RegDst,Sign_extend,clock,reset,opcplus4);
    output[31:0] read_data_1;
    output[31:0] read_data_2;
    input[31:0]  Instruction;
    input[31:0]  mem_data;
    input[31:0]  ALU_result;
    input        Jal;
    input        RegWrite;
    input        MemtoReg;
    input        RegDst;             
    output[31:0] Sign_extend;
    input		 clock,reset;
    input[31:0]  opcplus4;
    
    reg [31:0] registers[0:31];
    
    reg [31:0] write_data;

    reg [4:0] write_address;
    wire[15:0] Immediate;
    wire [4:0]rd;
    wire [4:0]rt;
    wire extend;


    assign read_data_1=registers[Instruction[25:21]];
    assign read_data_2=registers[Instruction[20:16]];

    assign extend=(andi==1'b1||ori==1'b1||xori==1'b1||Instruction[31:26]==6'b001001||Instruction[31:26]==6'b001011)
    ?1'b0:Immediate[15];
    assign Immediate=Instruction[15:0];
    assign andi=Instruction[31:26]==6'b001100;
    assign ori=Instruction[31:26]==6'b001101;
    assign xori=Instruction[31:26]==6'b001110;
    assign lui=Instruction[31:26]==6'b001111;
    assign Sign_extend=(lui==1'b1)?{Immediate,{16'b0}}:
    ((Instruction[31:26]==6'b000100||Instruction[31:26]==6'b000101)?
    {{14{Immediate[15]}},Immediate,2'b0}:{{16{extend}},Immediate});
    
    assign rd = Instruction[15:11];
    assign rt = Instruction[20:16];
    
  always @(*) begin
    if(RegWrite == 1'b1)begin
        if(Jal == 1'b1)begin
            write_address=5'b11111;
        end
        else if(RegDst == 1'b1)
        begin
            write_address = rd;
        end
        else begin
        write_address = rt;
        end
    end
    else begin
        write_address = write_address;
    end
  end

  always @(*) begin
    if(MemtoReg == 1'b1)begin
        write_data = mem_data;
    end
    else if(Jal == 1'b1)begin
        write_data = opcplus4;
    end
    else begin
        write_data = ALU_result;
    end
    end
  
      integer k;

  always @(posedge clock or posedge reset) begin
      if(reset==1'b1)begin
          for(k = 5'b00000; k <= 5'b11111; k= k + 5'b00001) begin
              registers[k]=32'b0;
          end
      end
      else if(RegWrite == 1'b1 && write_address > 0) begin
          registers[write_address] = write_data;
      end
      else begin
          registers[write_address] = registers[write_address];
      end
  end
    endmodule
module decode32(read_data_1,read_data_2,Instruction,mem_data,ALU_result,
                 Jal,RegWrite,MemtoReg,RegDst,Sign_extend,clock,reset,opcplus4);

    output[31:0] read_data_1;
    output[31:0] read_data_2;
    input[31:0]  Instruction;
    input[31:0]  mem_data;
    input[31:0]  ALU_result;
    input        Jal;
    input        RegWrite;
    input        MemtoReg;
    input        RegDst;             
    output[31:0] Sign_extend;
    input		 clock,reset;
    input[31:0]  opcplus4;
    
    reg [31:0] registers[0:31];
    
    reg [31:0] write_data;

    reg [4:0] write_address;
    wire[15:0] Immediate;
    wire [4:0]rd;
    wire [4:0]rt;
    wire extend;


    assign read_data_1=registers[Instruction[25:21]];
    assign read_data_2=registers[Instruction[20:16]];

    assign extend=(andi==1'b1||ori==1'b1||xori==1'b1||Instruction[31:26]==6'b001001||Instruction[31:26]==6'b001011)
    ?1'b0:Immediate[15];
    assign Immediate=Instruction[15:0];
    assign andi=Instruction[31:26]==6'b001100;
    assign ori=Instruction[31:26]==6'b001101;
    assign xori=Instruction[31:26]==6'b001110;
    assign lui=Instruction[31:26]==6'b001111;
    assign Sign_extend=(lui==1'b1)?{Immediate,{16'b0}}:
    ((Instruction[31:26]==6'b000100||Instruction[31:26]==6'b000101)?
    {{14{Immediate[15]}},Immediate,2'b0}:{{16{extend}},Immediate});
    
    assign rd = Instruction[15:11];
    assign rt = Instruction[20:16];
    
  always @(*) begin
    if(RegWrite == 1'b1)begin
        if(Jal == 1'b1)begin
            write_address=5'b11111;
        end
        else if(RegDst == 1'b1)
        begin
            write_address = rd;
        end
        else begin
        write_address = rt;
        end
    end
    else begin
        write_address = write_address;
    end
  end

  always @(*) begin
    if(MemtoReg == 1'b1)begin
        write_data = mem_data;
    end
    else if(Jal == 1'b1)begin
        write_data = opcplus4;
    end
    else begin
        write_data = ALU_result;
    end
    end
  
      integer k;

  always @(posedge clock or posedge reset) begin
      if(reset==1'b1)begin
          for(k = 5'b00000; k <= 5'b11111; k= k + 5'b00001) begin
              registers[k]=32'b0;
          end
      end
      else if(RegWrite == 1'b1 && write_address > 0) begin
          registers[write_address] = write_data;
      end
      else begin
          registers[write_address] = registers[write_address];
      end
  end
    endmodule