data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_code = 1; rst_in = 1; rst_open = 1; rst_timer = 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_code = 0; rst_in = 0; rst_open = 0; rst_timer = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:66: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_code = 1; rst_in = 1; rst_open = 1; rst_timer = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #10 change = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:67: Unsupported: Ignoring delay on this delayed statement.\n    #50\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:72: Unsupported: Ignoring delay on this delayed statement.\n    #10 change = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:75: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_code = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:76: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_code = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:77: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0000_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:78: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:79: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:80: Unsupported: Ignoring delay on this delayed statement.\n        #10 din = 10\'b00_0000_0000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:81: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:82: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:83: Unsupported: Ignoring delay on this delayed statement.\n        #10 din = 10\'b00_0000_0000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:84: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:85: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:86: Unsupported: Ignoring delay on this delayed statement.\n        #10 din = 10\'b00_0000_0000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:87: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:88: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:91: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:92: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:93: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:96: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:97: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:98: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:100: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:101: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:102: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:104: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:105: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:106: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:110: Unsupported: Ignoring delay on this delayed statement.\n    #20 sure = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:111: Unsupported: Ignoring delay on this delayed statement.\n    #20 sure = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:112: Unsupported: Ignoring delay on this delayed statement.\n    #20 rst = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:113: Unsupported: Ignoring delay on this delayed statement.\n    #20 rst = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:119: Unsupported: Ignoring delay on this delayed statement.\n  #10 rst_open = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:114: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:120: Unsupported: Ignoring delay on this delayed statement.\n  #10 rst_open = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:121: Unsupported: Ignoring delay on this delayed statement.\n    #10 open = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:122: Unsupported: Ignoring delay on this delayed statement.\n    #10 open = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:123: Unsupported: Ignoring delay on this delayed statement.\n   #10 rst_in = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:124: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_in = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:125: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:126: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:127: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:129: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:130: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:131: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:133: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:134: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:135: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:137: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:138: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:139: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:143: Unsupported: Ignoring delay on this delayed statement.\n    #20 sure = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:144: Unsupported: Ignoring delay on this delayed statement.\n    #20 sure = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:146: Unsupported: Ignoring delay on this delayed statement.\n    #50 rst_open = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:147: Unsupported: Ignoring delay on this delayed statement.\n    #50 rst_open = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:152: Unsupported: Ignoring delay on this delayed statement.\n    #10 open = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:148: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:153: Unsupported: Ignoring delay on this delayed statement.\n    #10 open = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:154: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:155: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_in = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:156: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:157: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:158: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:160: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0010_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:161: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:162: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:164: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:165: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:166: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:168: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:169: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:170: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:172: Unsupported: Ignoring delay on this delayed statement.\n    #20 sure = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:173: Unsupported: Ignoring delay on this delayed statement.\n    #20 sure = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:175: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:174: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:176: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_in = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:177: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:178: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:179: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:181: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0010_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:182: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:183: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:185: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:186: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:187: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:189: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:190: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:191: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:195: Unsupported: Ignoring delay on this delayed statement.\n    #20 sure = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:196: Unsupported: Ignoring delay on this delayed statement.\n    #20 sure = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:199: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:198: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:200: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_in = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:201: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:202: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:203: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:205: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0010_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:206: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:207: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:209: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:210: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:211: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:213: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:214: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:215: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:219: Unsupported: Ignoring delay on this delayed statement.\n    #20 sure = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:220: Unsupported: Ignoring delay on this delayed statement.\n    #20 sure = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:223: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:222: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:224: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_in = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:225: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:226: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:227: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:229: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0010_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:230: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:231: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:233: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:234: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:235: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:237: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:238: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:239: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:243: Unsupported: Ignoring delay on this delayed statement.\n    #20 sure = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:244: Unsupported: Ignoring delay on this delayed statement.\n    #20 sure = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:247: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:246: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:248: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_in = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:249: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:250: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:251: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:253: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0010_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:254: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:255: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:257: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:258: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:259: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:261: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:262: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:263: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:267: Unsupported: Ignoring delay on this delayed statement.\n    #20 sure = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:268: Unsupported: Ignoring delay on this delayed statement.\n    #20 sure = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:271: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:270: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:272: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_in = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:273: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:274: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:275: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:277: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0010_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:278: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:279: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:281: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:282: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:283: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:285: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:286: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:287: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:291: Unsupported: Ignoring delay on this delayed statement.\n    #20 sure = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:292: Unsupported: Ignoring delay on this delayed statement.\n    #20 sure = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:295: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:294: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:296: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_in = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:297: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:298: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:299: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:301: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0010_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:302: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:303: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:305: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:306: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:307: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:309: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:310: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:311: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:315: Unsupported: Ignoring delay on this delayed statement.\n    #20 sure = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:316: Unsupported: Ignoring delay on this delayed statement.\n    #20 sure = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:318: Unsupported: Ignoring delay on this delayed statement.\n    #50 rst_open = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:319: Unsupported: Ignoring delay on this delayed statement.\n    #50 rst_open = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:325: Unsupported: Ignoring delay on this delayed statement.\n    #10 change = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:322: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:326: Unsupported: Ignoring delay on this delayed statement.\n    #10 change = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:327: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:328: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_in = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:330: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:331: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_in = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:332: Unsupported: Ignoring delay on this delayed statement.\n     #10 din = 10\'b00_1000_0000;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:333: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:334: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:336: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0100_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:337: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:338: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:340: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0010_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:341: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:342: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:344: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:345: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:346: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:348: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_1000_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:349: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:350: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:352: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0100_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:353: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:354: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:356: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0010_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:357: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:358: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:360: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:361: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:362: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:363: Unsupported: Ignoring delay on this delayed statement.\n    #10 sure = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:364: Unsupported: Ignoring delay on this delayed statement.\n    #10 sure = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:369: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:368: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:370: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_in = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:371: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:372: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:373: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:375: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:376: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:377: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:379: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:380: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:381: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:383: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:384: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:385: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:388: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_1000_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:389: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:390: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:392: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0100_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:393: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:394: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:396: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0010_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:397: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:398: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:400: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:401: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:402: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:403: Unsupported: Ignoring delay on this delayed statement.\n    #10 sure = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:404: Unsupported: Ignoring delay on this delayed statement.\n    #10 sure = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:410: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:405: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:411: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:412: Unsupported: Ignoring delay on this delayed statement.\n    #10 open = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:413: Unsupported: Ignoring delay on this delayed statement.\n    #10 open = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:414: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:415: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_in = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:416: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:417: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:418: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:420: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:421: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:422: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:424: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:425: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:426: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:428: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:429: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:430: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:431: Unsupported: Ignoring delay on this delayed statement.\n    #10 sure = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:432: Unsupported: Ignoring delay on this delayed statement.\n    #10 sure = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:435: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:433: Unsupported: Ignoring delay on this delayed statement.\n    #100\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:436: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_in = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:437: Unsupported: Ignoring delay on this delayed statement.\n      #10 din = 10\'b00_1000_0000;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:438: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:439: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:441: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0100_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:442: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:443: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:445: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0010_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:446: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:447: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:449: Unsupported: Ignoring delay on this delayed statement.\n    #10 din = 10\'b00_0001_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:450: Unsupported: Ignoring delay on this delayed statement.\n    #10 load = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:451: Unsupported: Ignoring delay on this delayed statement.\n    #10  load = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:452: Unsupported: Ignoring delay on this delayed statement.\n    #10 sure = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:453: Unsupported: Ignoring delay on this delayed statement.\n    #10 sure = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:456: Unsupported: Ignoring delay on this delayed statement.\nalways # 1 clk = ~clk;\n       ^\n%Error: data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes/sim_Lock_status.v:457: Cannot find file containing module: \'Lock\'\nLock  lock(\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes,data/full_repos/permissive/426072575/Lock\n             data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes,data/full_repos/permissive/426072575/Lock.v\n             data/full_repos/permissive/426072575/labs/final_project_digital_lock/codes,data/full_repos/permissive/426072575/Lock.sv\n             Lock\n             Lock.v\n             Lock.sv\n             obj_dir/Lock\n             obj_dir/Lock.v\n             obj_dir/Lock.sv\n%Error: Exiting due to 1 error(s), 283 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sim_lock_imp;
reg clk, rst_in, rst_code, rst_open, load, change, open, rst, rst_timer;
reg [9:0] din;
reg sure;
wire rest_times;
wire succ, fail, locked, open_now, change_now;
wire change_succ;
initial begin
    clk = 0;
    rst_timer = 0;
    rst = 0;
    rst_code = 0;
    rst_in = 0;
    rst_open = 0;
    load = 0;
    change = 0;
    
    sure = 0;
    open = 0;
    #10 rst_code = 1; rst_in = 1; rst_open = 1; rst_timer = 1;
    #10 rst_code = 0; rst_in = 0; rst_open = 0; rst_timer = 1;
    #10 rst_code = 1; rst_in = 1; rst_open = 1; rst_timer = 1;
    #50

    

    #10 change = 1;
    #10 change = 0;


    #10 rst_code = 0;
    #10 rst_code = 1;
    #10 din = 10'b00_0000_0000;
    #10 load = 1;
    #10  load = 0;
        #10 din = 10'b00_0000_0000;
    #10 load = 1;
    #10  load = 0;
        #10 din = 10'b00_0000_0000;
    #10 load = 1;
    #10  load = 0;
        #10 din = 10'b00_0000_0000;
    #10 load = 1;
    #10  load = 0;
    

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;


    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;



    #20 sure = 1;
    #20 sure = 0;
    #20 rst = 1;
    #20 rst = 0;
    #100



    
  #10 rst_open = 0;
  #10 rst_open = 1;
    #10 open = 1;
    #10 open = 0;
   #10 rst_in = 0;
    #10 rst_in = 1;
    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;



    #20 sure = 1;
    #20 sure = 0;

    #50 rst_open = 0;
    #50 rst_open = 1;
    #100
    


    #10 open = 1;
    #10 open = 0;
    #10 rst_in = 0;
    #10 rst_in = 1;
    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0010_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #20 sure = 1;
    #20 sure = 0;
    #100
    #10 rst_in = 0;
    #10 rst_in = 1;
    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0010_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;



    #20 sure = 1;
    #20 sure = 0;
        
    #100
    #10 rst_in = 0;
    #10 rst_in = 1;
    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0010_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;



    #20 sure = 1;
    #20 sure = 0;
    
    #100
    #10 rst_in = 0;
    #10 rst_in = 1;
    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0010_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;



    #20 sure = 1;
    #20 sure = 0;
    
    #100
    #10 rst_in = 0;
    #10 rst_in = 1;
    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0010_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;



    #20 sure = 1;
    #20 sure = 0;
    
    #100
    #10 rst_in = 0;
    #10 rst_in = 1;
    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0010_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;



    #20 sure = 1;
    #20 sure = 0;
    
    #100
    #10 rst_in = 0;
    #10 rst_in = 1;
    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0010_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;



    #20 sure = 1;
    #20 sure = 0;
    
    #50 rst_open = 0;
    #50 rst_open = 1;
    

    #100


    #10 change = 1;
    #10 change = 0;
    #10 rst_in = 0;
    #10 rst_in = 1;

    #10 rst_in = 0;
    #10 rst_in = 1;
     #10 din = 10'b00_1000_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0100_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0010_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_1000_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0100_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0010_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;
    #10 sure = 1;
    #10 sure = 0;



    #100
    #10 rst_in = 0;
    #10 rst_in = 1;
    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;


    #10 din = 10'b00_1000_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0100_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0010_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;
    #10 sure = 1;
    #10 sure = 0;
    #100


    

    #10 rst = 1;
    #10 rst = 0;
    #10 open = 1;
    #10 open = 0;
    #10 rst_in = 0;
    #10 rst_in = 1;
    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;
    #10 sure = 1;
    #10 sure = 0;
    #100

    #10 rst_in = 0;
    #10 rst_in = 1;
      #10 din = 10'b00_1000_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0100_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0010_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;
    #10 sure = 1;
    #10 sure = 0;
end

always # 1 clk = ~clk;
Lock  lock(
    clk, rst_in, rst_code, rst_open, rst_timer, rst,
    load, sure, change, open,
    din,
    succ, fail, locked, change_succ, rest_times,
    open_now, change_now
);
endmodule
module sim_lock_imp;

reg clk, rst_in, rst_code, rst_open, load, change, open, rst, rst_timer;
reg [9:0] din;
reg sure;
wire rest_times;
wire succ, fail, locked, open_now, change_now;
wire change_succ;
initial begin
    clk = 0;
    rst_timer = 0;
    rst = 0;
    rst_code = 0;
    rst_in = 0;
    rst_open = 0;
    load = 0;
    change = 0;
    
    sure = 0;
    open = 0;
    #10 rst_code = 1; rst_in = 1; rst_open = 1; rst_timer = 1;
    #10 rst_code = 0; rst_in = 0; rst_open = 0; rst_timer = 1;
    #10 rst_code = 1; rst_in = 1; rst_open = 1; rst_timer = 1;
    #50

    

    #10 change = 1;
    #10 change = 0;


    #10 rst_code = 0;
    #10 rst_code = 1;
    #10 din = 10'b00_0000_0000;
    #10 load = 1;
    #10  load = 0;
        #10 din = 10'b00_0000_0000;
    #10 load = 1;
    #10  load = 0;
        #10 din = 10'b00_0000_0000;
    #10 load = 1;
    #10  load = 0;
        #10 din = 10'b00_0000_0000;
    #10 load = 1;
    #10  load = 0;
    

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;


    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;



    #20 sure = 1;
    #20 sure = 0;
    #20 rst = 1;
    #20 rst = 0;
    #100



    
  #10 rst_open = 0;
  #10 rst_open = 1;
    #10 open = 1;
    #10 open = 0;
   #10 rst_in = 0;
    #10 rst_in = 1;
    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;



    #20 sure = 1;
    #20 sure = 0;

    #50 rst_open = 0;
    #50 rst_open = 1;
    #100
    


    #10 open = 1;
    #10 open = 0;
    #10 rst_in = 0;
    #10 rst_in = 1;
    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0010_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #20 sure = 1;
    #20 sure = 0;
    #100
    #10 rst_in = 0;
    #10 rst_in = 1;
    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0010_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;



    #20 sure = 1;
    #20 sure = 0;
        
    #100
    #10 rst_in = 0;
    #10 rst_in = 1;
    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0010_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;



    #20 sure = 1;
    #20 sure = 0;
    
    #100
    #10 rst_in = 0;
    #10 rst_in = 1;
    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0010_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;



    #20 sure = 1;
    #20 sure = 0;
    
    #100
    #10 rst_in = 0;
    #10 rst_in = 1;
    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0010_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;



    #20 sure = 1;
    #20 sure = 0;
    
    #100
    #10 rst_in = 0;
    #10 rst_in = 1;
    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0010_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;



    #20 sure = 1;
    #20 sure = 0;
    
    #100
    #10 rst_in = 0;
    #10 rst_in = 1;
    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0010_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;



    #20 sure = 1;
    #20 sure = 0;
    
    #50 rst_open = 0;
    #50 rst_open = 1;
    

    #100


    #10 change = 1;
    #10 change = 0;
    #10 rst_in = 0;
    #10 rst_in = 1;

    #10 rst_in = 0;
    #10 rst_in = 1;
     #10 din = 10'b00_1000_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0100_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0010_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_1000_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0100_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0010_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;
    #10 sure = 1;
    #10 sure = 0;



    #100
    #10 rst_in = 0;
    #10 rst_in = 1;
    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;


    #10 din = 10'b00_1000_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0100_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0010_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;
    #10 sure = 1;
    #10 sure = 0;
    #100


    

    #10 rst = 1;
    #10 rst = 0;
    #10 open = 1;
    #10 open = 0;
    #10 rst_in = 0;
    #10 rst_in = 1;
    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;
    #10 sure = 1;
    #10 sure = 0;
    #100

    #10 rst_in = 0;
    #10 rst_in = 1;
      #10 din = 10'b00_1000_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0100_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0010_0000;
    #10 load = 1;
    #10  load = 0;

    #10 din = 10'b00_0001_0000;
    #10 load = 1;
    #10  load = 0;
    #10 sure = 1;
    #10 sure = 0;
end

always # 1 clk = ~clk;
Lock  lock(
    clk, rst_in, rst_code, rst_open, rst_timer, rst,
    load, sure, change, open,
    din,
    succ, fail, locked, change_succ, rest_times,
    open_now, change_now
);
endmodule