data/full_repos/permissive/451853158/MIPS_Pipeline_Processor/adder.v
data/verilator_xmls/eae23b10-8a08-4afe-b97a-446b0fa31b67.xml
module adder (
  input [31:0] a, b,
  output wire [31:0] y
);

assign y = a + b;

endmodule
module adder (
  input [31:0] a, b,
  output wire [31:0] y
);


assign y = a + b;

endmodule