data/full_repos/permissive/517239653/uart.v
1: b'%Warning-WIDTH: data/full_repos/permissive/517239653/uart.v:121: Bit extraction of var[511:0] requires 9 bit index, not 16 bits.\n                                                               : ... In instance uart\n    rx_bytevect[(rx_byte_ind << 3) + rx_bit_ind] = rx_line;\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/517239653/uart.v:182: Bit extraction of var[511:0] requires 9 bit index, not 16 bits.\n                                                               : ... In instance uart\n   tx_data = bytevect_in[(tx_byte_ind << 3) + (tx_bit_ind)];\n                        ^\n%Error: Exiting due to 2 warning(s)\n'
module uart(bytevect_out, rx_size_ready, rx_buffer_full, tx_done, rx_state_out, tx_line, rx_line, rx_reset, clk, bytevect_in, tx_size, tx_go);

parameter RX_PACKET_SIZE = 64;
parameter TX_PACKET_SIZE = 64;
parameter BIT_TIMING 	 = 434;
parameter IDLE_TIME 	 = BIT_TIMING;

output [8*RX_PACKET_SIZE-1:0] bytevect_out;
output [15:0] rx_size_ready;
output rx_buffer_full;
output tx_done;
output [2:0] rx_state_out;
output tx_line;
input rx_line;
input rx_reset;
input clk;
input [8*TX_PACKET_SIZE-1:0] bytevect_in;
input [15:0] tx_size;
input tx_go;

parameter 		TX_INIT 			= 0,
				TX_SEND_START_BIT 	= 1,
				TX_SEND_DATA_BIT 	= 2,
				TX_SEND_STOP_BIT 	= 3,
				TX_IDLE 			= 4;

parameter 		RX_INIT 				= 0,
				RX_WAIT_FOR_START_BIT 	= 1,
				RX_RECEIVE_DATA			= 2,
				RX_WAIT_FOR_STOP_BIT	= 3,
				RX_BUFFER_FULL 			= 4;

reg last_rx_line = 1;
reg last_rx_reset = 0;
reg last_tx_go = 0;
reg [8*RX_PACKET_SIZE-1:0] rx_bytevect;
reg [15:0] rx_byte_ind = 0;
reg [15:0] rx_bit_ind = 0;
reg [15:0] tx_byte_ind = 0;
reg [15:0] tx_bit_ind = 0;
reg [2:0] rx_state = RX_WAIT_FOR_START_BIT;
reg [2:0] tx_state = TX_IDLE;
reg tx_data = 1;
reg rx_buf_full_reg = 0;
reg tx_done_reg = 1;
reg [31:0] rx_timer = 0;
reg [31:0] tx_timer = 0;
reg start_cond_detected = 0;

assign bytevect_out = rx_bytevect;
assign rx_size_ready = rx_byte_ind;
assign tx_line = tx_data;
assign rx_buffer_full = rx_buf_full_reg;
assign tx_done = tx_done_reg;
assign rx_state_out = rx_state;


always @(posedge clk) begin


	if (rx_reset && !last_rx_reset) begin
		rx_state = RX_INIT;
	end
	last_rx_reset = rx_reset;
	
	rx_timer = rx_timer + 1;


	case (rx_state)
		RX_INIT: begin

			rx_byte_ind = 0;
			rx_bit_ind = 0;
			last_rx_line = rx_line;
			rx_state = RX_WAIT_FOR_START_BIT;
			rx_timer = 0;
			rx_buf_full_reg = 0;
			start_cond_detected = 0;
		end
		RX_WAIT_FOR_START_BIT: begin

			if (!rx_line && last_rx_line) begin

				start_cond_detected = 1;
				rx_timer = 0;
			end
			
			if (start_cond_detected && rx_timer >= BIT_TIMING) begin
				rx_state = RX_RECEIVE_DATA;
				rx_timer = BIT_TIMING >> 1;
				rx_bit_ind = 0;
			end
			last_rx_line <= rx_line;
		end
		RX_RECEIVE_DATA: begin
			if(rx_timer >= BIT_TIMING) begin

				rx_bytevect[(rx_byte_ind << 3) + rx_bit_ind] = rx_line;
				rx_bit_ind = rx_bit_ind + 1;
				rx_timer = 0;
			end
			

			if (rx_bit_ind == 8) begin
				rx_byte_ind = rx_byte_ind + 1;
				rx_timer = 0;
				rx_state = RX_WAIT_FOR_STOP_BIT;
			end
		end
		RX_WAIT_FOR_STOP_BIT: begin
			if (rx_timer >= (BIT_TIMING >> 1)) begin
				if (rx_line) begin

					last_rx_line = rx_line;
					rx_timer = 0;
					start_cond_detected = 0;
					rx_state = RX_WAIT_FOR_START_BIT;
					if(rx_byte_ind >= RX_PACKET_SIZE) begin
						rx_buf_full_reg = 'b1;
						rx_state = RX_BUFFER_FULL;
					end
				end
			end
		end
		RX_BUFFER_FULL: begin

			rx_buf_full_reg = 'b1;
		end
		default: begin
			rx_state <= RX_INIT;
		end
	endcase


	tx_timer = tx_timer + 1;
	if (tx_go && !last_tx_go) begin
		tx_state = TX_INIT;
	end


	case (tx_state) 
		TX_INIT: begin
			tx_byte_ind = 0;
			tx_bit_ind = 0;
			tx_timer = 0;
			tx_done_reg = 0;
			tx_state = TX_SEND_START_BIT;
		end
		TX_SEND_START_BIT: begin
			tx_data = 0;

			if (tx_timer >= BIT_TIMING) begin
				tx_timer = 0;
				tx_bit_ind = 0;
				tx_state = TX_SEND_DATA_BIT;
			end
		end
		TX_SEND_DATA_BIT: begin
			tx_data = bytevect_in[(tx_byte_ind << 3) + (tx_bit_ind)];

			if (tx_timer >= BIT_TIMING) begin
				tx_bit_ind = tx_bit_ind + 1;
				tx_timer = 0;
			end

			if (tx_bit_ind >= 8) begin
				tx_byte_ind = tx_byte_ind + 1;
				tx_timer = 0;
				tx_state = TX_SEND_STOP_BIT;
			end
		end
		TX_SEND_STOP_BIT: begin
			tx_data = 'b1;
			if (tx_timer >= (BIT_TIMING + IDLE_TIME)) begin
				tx_timer = 0;
				if (tx_byte_ind >= tx_size || tx_byte_ind >= TX_PACKET_SIZE) begin
					tx_done_reg = 'b1;
					tx_state = TX_IDLE;
				end else begin
					tx_state = TX_SEND_START_BIT;
				end
			end
		end
		default: begin
			tx_state = TX_IDLE;
		end
	endcase

	last_tx_go = tx_go;
end

endmodule
module uart(bytevect_out, rx_size_ready, rx_buffer_full, tx_done, rx_state_out, tx_line, rx_line, rx_reset, clk, bytevect_in, tx_size, tx_go);


parameter RX_PACKET_SIZE = 64;
parameter TX_PACKET_SIZE = 64;
parameter BIT_TIMING 	 = 434;
parameter IDLE_TIME 	 = BIT_TIMING;

output [8*RX_PACKET_SIZE-1:0] bytevect_out;
output [15:0] rx_size_ready;
output rx_buffer_full;
output tx_done;
output [2:0] rx_state_out;
output tx_line;
input rx_line;
input rx_reset;
input clk;
input [8*TX_PACKET_SIZE-1:0] bytevect_in;
input [15:0] tx_size;
input tx_go;

parameter 		TX_INIT 			= 0,
				TX_SEND_START_BIT 	= 1,
				TX_SEND_DATA_BIT 	= 2,
				TX_SEND_STOP_BIT 	= 3,
				TX_IDLE 			= 4;

parameter 		RX_INIT 				= 0,
				RX_WAIT_FOR_START_BIT 	= 1,
				RX_RECEIVE_DATA			= 2,
				RX_WAIT_FOR_STOP_BIT	= 3,
				RX_BUFFER_FULL 			= 4;

reg last_rx_line = 1;
reg last_rx_reset = 0;
reg last_tx_go = 0;
reg [8*RX_PACKET_SIZE-1:0] rx_bytevect;
reg [15:0] rx_byte_ind = 0;
reg [15:0] rx_bit_ind = 0;
reg [15:0] tx_byte_ind = 0;
reg [15:0] tx_bit_ind = 0;
reg [2:0] rx_state = RX_WAIT_FOR_START_BIT;
reg [2:0] tx_state = TX_IDLE;
reg tx_data = 1;
reg rx_buf_full_reg = 0;
reg tx_done_reg = 1;
reg [31:0] rx_timer = 0;
reg [31:0] tx_timer = 0;
reg start_cond_detected = 0;

assign bytevect_out = rx_bytevect;
assign rx_size_ready = rx_byte_ind;
assign tx_line = tx_data;
assign rx_buffer_full = rx_buf_full_reg;
assign tx_done = tx_done_reg;
assign rx_state_out = rx_state;


always @(posedge clk) begin


	if (rx_reset && !last_rx_reset) begin
		rx_state = RX_INIT;
	end
	last_rx_reset = rx_reset;
	
	rx_timer = rx_timer + 1;


	case (rx_state)
		RX_INIT: begin

			rx_byte_ind = 0;
			rx_bit_ind = 0;
			last_rx_line = rx_line;
			rx_state = RX_WAIT_FOR_START_BIT;
			rx_timer = 0;
			rx_buf_full_reg = 0;
			start_cond_detected = 0;
		end
		RX_WAIT_FOR_START_BIT: begin

			if (!rx_line && last_rx_line) begin

				start_cond_detected = 1;
				rx_timer = 0;
			end
			
			if (start_cond_detected && rx_timer >= BIT_TIMING) begin
				rx_state = RX_RECEIVE_DATA;
				rx_timer = BIT_TIMING >> 1;
				rx_bit_ind = 0;
			end
			last_rx_line <= rx_line;
		end
		RX_RECEIVE_DATA: begin
			if(rx_timer >= BIT_TIMING) begin

				rx_bytevect[(rx_byte_ind << 3) + rx_bit_ind] = rx_line;
				rx_bit_ind = rx_bit_ind + 1;
				rx_timer = 0;
			end
			

			if (rx_bit_ind == 8) begin
				rx_byte_ind = rx_byte_ind + 1;
				rx_timer = 0;
				rx_state = RX_WAIT_FOR_STOP_BIT;
			end
		end
		RX_WAIT_FOR_STOP_BIT: begin
			if (rx_timer >= (BIT_TIMING >> 1)) begin
				if (rx_line) begin

					last_rx_line = rx_line;
					rx_timer = 0;
					start_cond_detected = 0;
					rx_state = RX_WAIT_FOR_START_BIT;
					if(rx_byte_ind >= RX_PACKET_SIZE) begin
						rx_buf_full_reg = 'b1;
						rx_state = RX_BUFFER_FULL;
					end
				end
			end
		end
		RX_BUFFER_FULL: begin

			rx_buf_full_reg = 'b1;
		end
		default: begin
			rx_state <= RX_INIT;
		end
	endcase


	tx_timer = tx_timer + 1;
	if (tx_go && !last_tx_go) begin
		tx_state = TX_INIT;
	end


	case (tx_state) 
		TX_INIT: begin
			tx_byte_ind = 0;
			tx_bit_ind = 0;
			tx_timer = 0;
			tx_done_reg = 0;
			tx_state = TX_SEND_START_BIT;
		end
		TX_SEND_START_BIT: begin
			tx_data = 0;

			if (tx_timer >= BIT_TIMING) begin
				tx_timer = 0;
				tx_bit_ind = 0;
				tx_state = TX_SEND_DATA_BIT;
			end
		end
		TX_SEND_DATA_BIT: begin
			tx_data = bytevect_in[(tx_byte_ind << 3) + (tx_bit_ind)];

			if (tx_timer >= BIT_TIMING) begin
				tx_bit_ind = tx_bit_ind + 1;
				tx_timer = 0;
			end

			if (tx_bit_ind >= 8) begin
				tx_byte_ind = tx_byte_ind + 1;
				tx_timer = 0;
				tx_state = TX_SEND_STOP_BIT;
			end
		end
		TX_SEND_STOP_BIT: begin
			tx_data = 'b1;
			if (tx_timer >= (BIT_TIMING + IDLE_TIME)) begin
				tx_timer = 0;
				if (tx_byte_ind >= tx_size || tx_byte_ind >= TX_PACKET_SIZE) begin
					tx_done_reg = 'b1;
					tx_state = TX_IDLE;
				end else begin
					tx_state = TX_SEND_START_BIT;
				end
			end
		end
		default: begin
			tx_state = TX_IDLE;
		end
	endcase

	last_tx_go = tx_go;
end

endmodule