data/full_repos/permissive/506562943/HDLBits/Circuits/Sequential Logic/Counters/exams_ece241_2014_q7b.v
1: b'%Error: Cannot find file containing module: Logic/Counters,data/full_repos/permissive/506562943\n        ... Looked in:\n             data/full_repos/permissive/506562943/HDLBits/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/506562943\n             data/full_repos/permissive/506562943/HDLBits/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/506562943.v\n             data/full_repos/permissive/506562943/HDLBits/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/506562943.sv\n             Logic/Counters,data/full_repos/permissive/506562943\n             Logic/Counters,data/full_repos/permissive/506562943.v\n             Logic/Counters,data/full_repos/permissive/506562943.sv\n             obj_dir/Logic/Counters,data/full_repos/permissive/506562943\n             obj_dir/Logic/Counters,data/full_repos/permissive/506562943.v\n             obj_dir/Logic/Counters,data/full_repos/permissive/506562943.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/506562943/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Logic/Counters/exams_ece241_2014_q7b.v\n%Error: Exiting due to 3 error(s)\n'
module top_module (
    input clk,
    input reset,
    output OneHertz,
    output [2:0] c_enable
);

    reg [3:0] l, m, h;
    initial l = 4'b0;
    initial m = 4'b0;
    initial h = 4'b0;
    
    assign OneHertz = (h == 4'd9 && m == 4'd9 && l == 4'd9);
    assign c_enable = {m == 4'd9 && l == 4'd9, l == 4'd9, 1'b1};
    
    bcdcount counter0 (clk, reset, c_enable[0], l);
    bcdcount counter1 (clk, reset, c_enable[1], m);
    bcdcount counter2 (clk, reset, c_enable[2], h);

endmodule
module top_module (
    input clk,
    input reset,
    output OneHertz,
    output [2:0] c_enable
);


    reg [3:0] l, m, h;
    initial l = 4'b0;
    initial m = 4'b0;
    initial h = 4'b0;
    
    assign OneHertz = (h == 4'd9 && m == 4'd9 && l == 4'd9);
    assign c_enable = {m == 4'd9 && l == 4'd9, l == 4'd9, 1'b1};
    
    bcdcount counter0 (clk, reset, c_enable[0], l);
    bcdcount counter1 (clk, reset, c_enable[1], m);
    bcdcount counter2 (clk, reset, c_enable[2], h);

endmodule