data/full_repos/permissive/446350722/cpuSim.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/446350722/cpuSim.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #40 $finish;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/446350722/cpuSim.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #1 CLOCK = ~CLOCK; RESET = 1\'b0;\n        ^\n%Error: data/full_repos/permissive/446350722/cpuSim.v:39: Cannot find file containing module: \'ARM_CPU\'\n    ARM_CPU core(RESET, CLOCK, IC_wire, mem_data_out, PC_wire, mem_address, mem_data_in, control_memwrite, control_memread);\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/446350722,data/full_repos/permissive/446350722/ARM_CPU\n             data/full_repos/permissive/446350722,data/full_repos/permissive/446350722/ARM_CPU.v\n             data/full_repos/permissive/446350722,data/full_repos/permissive/446350722/ARM_CPU.sv\n             ARM_CPU\n             ARM_CPU.v\n             ARM_CPU.sv\n             obj_dir/ARM_CPU\n             obj_dir/ARM_CPU.v\n             obj_dir/ARM_CPU.sv\n%Error: data/full_repos/permissive/446350722/cpuSim.v:40: Cannot find file containing module: \'Instr_Memory\'\n    Instr_Memory IM(PC_wire, IC_wire);\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/446350722/cpuSim.v:41: Cannot find file containing module: \'Data_Memory\'\n    Data_Memory DM(mem_address, mem_data_in, control_memwrite, control_memread, mem_data_out);\n    ^~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cpuSim;

    reg RESET;
    reg CLOCK;


    wire [63:0] PC_wire;
    wire [31:0] IC_wire;


    wire [63:0] mem_address;
    wire [63:0] mem_data_in;
    wire control_memwrite;
    wire control_memread;
    wire [63:0] mem_data_out;


    ARM_CPU core(RESET, CLOCK, IC_wire, mem_data_out, PC_wire, mem_address, mem_data_in, control_memwrite, control_memread);
    Instr_Memory IM(PC_wire, IC_wire);
    Data_Memory DM(mem_address, mem_data_in, control_memwrite, control_memread, mem_data_out);


    initial begin
        CLOCK = 1'b0;
        RESET = 1'b1;
        #40 $finish;
    end

    always begin
        #1 CLOCK = ~CLOCK; RESET = 1'b0;
    end
endmodule
module cpuSim;


    reg RESET;
    reg CLOCK;


    wire [63:0] PC_wire;
    wire [31:0] IC_wire;


    wire [63:0] mem_address;
    wire [63:0] mem_data_in;
    wire control_memwrite;
    wire control_memread;
    wire [63:0] mem_data_out;


    ARM_CPU core(RESET, CLOCK, IC_wire, mem_data_out, PC_wire, mem_address, mem_data_in, control_memwrite, control_memread);
    Instr_Memory IM(PC_wire, IC_wire);
    Data_Memory DM(mem_address, mem_data_in, control_memwrite, control_memread, mem_data_out);


    initial begin
        CLOCK = 1'b0;
        RESET = 1'b1;
        #40 $finish;
    end

    always begin
        #1 CLOCK = ~CLOCK; RESET = 1'b0;
    end
endmodule