data/full_repos/permissive/443556793/lab_4/sim/testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/443556793/lab_4/sim/testbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/443556793/lab_4/sim/testbench.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/443556793/lab_4/sim/testbench.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Error: data/full_repos/permissive/443556793/lab_4/sim/testbench.v:30: Cannot find file containing module: \'top\'\n top dut(clk,rst,writedata,dataadr,memwrite);\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/443556793/lab_4/sim,data/full_repos/permissive/443556793/top\n             data/full_repos/permissive/443556793/lab_4/sim,data/full_repos/permissive/443556793/top.v\n             data/full_repos/permissive/443556793/lab_4/sim,data/full_repos/permissive/443556793/top.sv\n             top\n             top.v\n             top.sv\n             obj_dir/top\n             obj_dir/top.v\n             obj_dir/top.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();
	reg clk;
	reg rst;

	wire[31:0] writedata,dataadr;
	wire memwrite;

	top dut(clk,rst,writedata,dataadr,memwrite);

	initial begin 
		rst <= 1;
		#100;
		rst <= 0;
	end

	always begin
		clk <= 1;
		#5;
		clk <= 0;
		#5;
	
	end















endmodule
module testbench();

	reg clk;
	reg rst;

	wire[31:0] writedata,dataadr;
	wire memwrite;

	top dut(clk,rst,writedata,dataadr,memwrite);

	initial begin 
		rst <= 1;
		#100;
		rst <= 0;
	end

	always begin
		clk <= 1;
		#5;
		clk <= 0;
		#5;
	
	end















endmodule