data/full_repos/permissive/470392519/rtl/ControlUnit.v
1: b'%Error: data/full_repos/permissive/470392519/rtl/ControlUnit.v:1: Cannot find include file: types.vh\n`include "types.vh" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/470392519/rtl,data/full_repos/permissive/470392519/types.vh\n             data/full_repos/permissive/470392519/rtl,data/full_repos/permissive/470392519/types.vh.v\n             data/full_repos/permissive/470392519/rtl,data/full_repos/permissive/470392519/types.vh.sv\n             types.vh\n             types.vh.v\n             types.vh.sv\n             obj_dir/types.vh\n             obj_dir/types.vh.v\n             obj_dir/types.vh.sv\n%Error: data/full_repos/permissive/470392519/rtl/ControlUnit.v:14: Define or directive not defined: \'`R\'\n            `R          : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `R_CTRL;\n            ^~\n%Error: data/full_repos/permissive/470392519/rtl/ControlUnit.v:14: syntax error, unexpected \':\', expecting endcase\n            `R          : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `R_CTRL;\n                        ^\n%Error: data/full_repos/permissive/470392519/rtl/ControlUnit.v:14: Define or directive not defined: \'`R_CTRL\'\n            `R          : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `R_CTRL;\n                                                                                                     ^~~~~~~\n%Error: data/full_repos/permissive/470392519/rtl/ControlUnit.v:15: Define or directive not defined: \'`I_JUMP\'\n            `I_JUMP     : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `I_JUMP_CTRL;\n            ^~~~~~~\n%Error: data/full_repos/permissive/470392519/rtl/ControlUnit.v:15: Define or directive not defined: \'`I_JUMP_CTRL\'\n            `I_JUMP     : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `I_JUMP_CTRL;\n                                                                                                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/470392519/rtl/ControlUnit.v:16: Define or directive not defined: \'`I_LOAD\'\n            `I_LOAD     : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `I_LOAD_CTRL;\n            ^~~~~~~\n%Error: data/full_repos/permissive/470392519/rtl/ControlUnit.v:16: Define or directive not defined: \'`I_LOAD_CTRL\'\n            `I_LOAD     : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `I_LOAD_CTRL;\n                                                                                                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/470392519/rtl/ControlUnit.v:17: Define or directive not defined: \'`I_ARITH\'\n            `I_ARITH    : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `I_ARITH_CTRL;\n            ^~~~~~~~\n%Error: data/full_repos/permissive/470392519/rtl/ControlUnit.v:17: Define or directive not defined: \'`I_ARITH_CTRL\'\n            `I_ARITH    : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `I_ARITH_CTRL;\n                                                                                                     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/470392519/rtl/ControlUnit.v:18: Define or directive not defined: \'`I_SYS\'\n            `I_SYS      : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `I_SYS_CTRL;\n            ^~~~~~\n%Error: data/full_repos/permissive/470392519/rtl/ControlUnit.v:18: Define or directive not defined: \'`I_SYS_CTRL\'\n            `I_SYS      : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `I_SYS_CTRL;\n                                                                                                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/470392519/rtl/ControlUnit.v:19: Define or directive not defined: \'`I_FENCE\'\n            `I_FENCE    : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `I_FENCE_CTRL;\n            ^~~~~~~~\n%Error: data/full_repos/permissive/470392519/rtl/ControlUnit.v:19: Define or directive not defined: \'`I_FENCE_CTRL\'\n            `I_FENCE    : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `I_FENCE_CTRL;\n                                                                                                     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/470392519/rtl/ControlUnit.v:20: Define or directive not defined: \'`S\'\n            `S          : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `S_CTRL;\n            ^~\n%Error: data/full_repos/permissive/470392519/rtl/ControlUnit.v:20: Define or directive not defined: \'`S_CTRL\'\n            `S          : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `S_CTRL;\n                                                                                                     ^~~~~~~\n%Error: data/full_repos/permissive/470392519/rtl/ControlUnit.v:21: Define or directive not defined: \'`B\'\n            `B          : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `B_CTRL;\n            ^~\n%Error: data/full_repos/permissive/470392519/rtl/ControlUnit.v:21: Define or directive not defined: \'`B_CTRL\'\n            `B          : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `B_CTRL;\n                                                                                                     ^~~~~~~\n%Error: data/full_repos/permissive/470392519/rtl/ControlUnit.v:22: Define or directive not defined: \'`U_LUI\'\n            `U_LUI      : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `U_LUI_CTRL;\n            ^~~~~~\n%Error: data/full_repos/permissive/470392519/rtl/ControlUnit.v:22: Define or directive not defined: \'`U_LUI_CTRL\'\n            `U_LUI      : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `U_LUI_CTRL;\n                                                                                                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/470392519/rtl/ControlUnit.v:23: Define or directive not defined: \'`U_AUIPC\'\n            `U_AUIPC    : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `U_AUIPC_CTRL;\n            ^~~~~~~~\n%Error: data/full_repos/permissive/470392519/rtl/ControlUnit.v:23: Define or directive not defined: \'`U_AUIPC_CTRL\'\n            `U_AUIPC    : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `U_AUIPC_CTRL;\n                                                                                                     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/470392519/rtl/ControlUnit.v:24: Define or directive not defined: \'`J\'\n            `J          : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `J_CTRL;\n            ^~\n%Error: data/full_repos/permissive/470392519/rtl/ControlUnit.v:24: Define or directive not defined: \'`J_CTRL\'\n            `J          : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `J_CTRL;\n                                                                                                     ^~~~~~~\n%Error: Cannot continue\n'
module ControlUnit (
    input       [6:0]   i_opcode,
    output  reg [3:0]   o_aluOp,
    output  reg         o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp
);

    always @* begin
        case (i_opcode)

            default     : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = 11'd0;

            `R          : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `R_CTRL;
            `I_JUMP     : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `I_JUMP_CTRL;
            `I_LOAD     : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `I_LOAD_CTRL;
            `I_ARITH    : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `I_ARITH_CTRL;
            `I_SYS      : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `I_SYS_CTRL;
            `I_FENCE    : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `I_FENCE_CTRL;
            `S          : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `S_CTRL;
            `B          : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `B_CTRL;
            `U_LUI      : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `U_LUI_CTRL;
            `U_AUIPC    : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `U_AUIPC_CTRL;
            `J          : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `J_CTRL;
        endcase
    end
endmodule
module ControlUnit (
    input       [6:0]   i_opcode,
    output  reg [3:0]   o_aluOp,
    output  reg         o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp
);


    always @* begin
        case (i_opcode)

            default     : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = 11'd0;

            `R          : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `R_CTRL;
            `I_JUMP     : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `I_JUMP_CTRL;
            `I_LOAD     : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `I_LOAD_CTRL;
            `I_ARITH    : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `I_ARITH_CTRL;
            `I_SYS      : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `I_SYS_CTRL;
            `I_FENCE    : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `I_FENCE_CTRL;
            `S          : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `S_CTRL;
            `B          : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `B_CTRL;
            `U_LUI      : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `U_LUI_CTRL;
            `U_AUIPC    : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `U_AUIPC_CTRL;
            `J          : {o_aluOp, o_exec_a, o_exec_b, o_mem_w, o_reg_w, o_mem2reg, o_bra, o_jmp} = `J_CTRL;
        endcase
    end
endmodule