data/full_repos/permissive/418284997/src/blocks/bram.v
data/verilator_xmls/f387c72a-acb5-4d1e-98f1-bfc3eae77b6d.xml
module bram
  #(
    parameter memSize_p = 8,
    parameter dataWidth_p = 16
  )
  (
    input wire clk_i,
    input wire write_i,
    input wire [dataWidth_p-1:0] data_i,

    input wire [(memSize_p - 1):0]  addr_i,

    output reg [(dataWidth_p - 1):0] data_o
  );

  reg [(dataWidth_p - 1):0] memory [2**memSize_p-1:0];

  always @(posedge clk_i) begin
    if (write_i) begin
      memory[addr_i] <= data_i;
      data_o <= data_i;
    end else
      data_o <= memory[addr_i];
  end

  `ifdef FORMAL

    reg timeValid_f = 0;
    always @(posedge clk_i) timeValid_f <= 1;

    always @(posedge clk_i) begin

      if (timeValid_f && $past(write_i)) begin
        assert(memory[$past(addr_i)] == $past(data_i));
      end





    end
    
  `endif

endmodule
module bram
  #(
    parameter memSize_p = 8,
    parameter dataWidth_p = 16
  )
  (
    input wire clk_i,
    input wire write_i,
    input wire [dataWidth_p-1:0] data_i,

    input wire [(memSize_p - 1):0]  addr_i,

    output reg [(dataWidth_p - 1):0] data_o
  );


  reg [(dataWidth_p - 1):0] memory [2**memSize_p-1:0];

  always @(posedge clk_i) begin
    if (write_i) begin
      memory[addr_i] <= data_i;
      data_o <= data_i;
    end else
      data_o <= memory[addr_i];
  end

  `ifdef FORMAL

    reg timeValid_f = 0;
    always @(posedge clk_i) timeValid_f <= 1;

    always @(posedge clk_i) begin

      if (timeValid_f && $past(write_i)) begin
        assert(memory[$past(addr_i)] == $past(data_i));
      end





    end
    
  `endif

endmodule