data/full_repos/permissive/485610894/tianqn-mips-env/tb/core_tb.v
1: b'%Error: data/full_repos/permissive/485610894/tianqn-mips-env/tb/core_tb.v:12: Cannot find include file: pa_soc_param.v\n`include "pa_soc_param.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/485610894/tianqn-mips-env/tb,data/full_repos/permissive/485610894/pa_soc_param.v\n             data/full_repos/permissive/485610894/tianqn-mips-env/tb,data/full_repos/permissive/485610894/pa_soc_param.v.v\n             data/full_repos/permissive/485610894/tianqn-mips-env/tb,data/full_repos/permissive/485610894/pa_soc_param.v.sv\n             pa_soc_param.v\n             pa_soc_param.v.v\n             pa_soc_param.v.sv\n             obj_dir/pa_soc_param.v\n             obj_dir/pa_soc_param.v.v\n             obj_dir/pa_soc_param.v.sv\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/tb/core_tb.v:54: syntax error, unexpected \'@\'\n    @ (posedge sys_clk) sys_rst_n = 0;\n    ^\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/tb/core_tb.v:58: syntax error, unexpected \'@\'\n        @ (posedge sys_clk);\n        ^\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/tb/core_tb.v:64: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nwire [`DATA_BUS_WIDTH-1:0]      k0 = u_pa_soc_core.u_pa_soc_xreg._xreg[26];\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/tb/core_tb.v:70: Unsupported: wait statements\n    wait (k0 == 32\'b1);\n    ^~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/tb/core_tb.v:71: Define or directive not defined: \'`CPU_FREQ_HZ\'\n    # ((32\'d1_000_000_000/`CPU_FREQ_HZ)*2);\n                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/tb/core_tb.v:71: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    # ((32\'d1_000_000_000/`CPU_FREQ_HZ)*2);\n                                      ^\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/tb/core_tb.v:85: Define or directive not defined: \'`CPU_FREQ_HZ\'\nalways #((32\'d1_000_000_000/`CPU_FREQ_HZ)/2) sys_clk = ~sys_clk;\n                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/tb/core_tb.v:85: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nalways #((32\'d1_000_000_000/`CPU_FREQ_HZ)/2) sys_clk = ~sys_clk;\n                                        ^\n%Error: Exiting due to 9 error(s)\n'
module core_tb(
    );

`define CPU_CYCLE               (32'd1_000_000_000/`CPU_FREQ_HZ)

reg                             sys_clk;
reg                             sys_rst_n;

wire                            TXD;

initial begin
`ifdef DUMP_VCD
    $dumpfile("wave.vcd");
    $dumpvars(0, core_tb);
`endif
end

pa_soc_core u_pa_soc_core (
    .clk_i                      (sys_clk),
    .rst_n_i                    (sys_rst_n),

    .txd                        (TXD)
);

core_uart_monitor_tb u_core_uart_monitor_tb (
    .clk_i                      (sys_clk),
    .rst_n_i                    (sys_rst_n),

    .rxd                        (TXD),
    .txd                        ()
);

initial begin
    sys_clk = 1;
    sys_rst_n = 0;

    $readmemh("image.pat", u_pa_soc_core.u_pa_soc_itcm._rom);
end

always begin
    @ (posedge sys_clk) sys_rst_n = 0;
    @ (posedge sys_clk) sys_rst_n = 1;

    while (1) begin
        @ (posedge sys_clk);
    end

    $stop();
end

wire [`DATA_BUS_WIDTH-1:0]      k0 = u_pa_soc_core.u_pa_soc_xreg._xreg[26];
`ifdef TEST_ISA
wire [`DATA_BUS_WIDTH-1:0]      k1 = u_pa_soc_core.u_pa_soc_xreg._xreg[27];
`endif

always begin
    wait (k0 == 32'b1);
    # (`CPU_CYCLE*2);

`ifdef TEST_ISA
    if (k1 == 32'b1) begin
        $display("TEST PASSED.");
    end
    else begin
        $display("TEST FAILED!");
    end
`endif

    $stop();
end

always #(`CPU_CYCLE/2) sys_clk = ~sys_clk;

endmodule
module core_tb(
    );


`define CPU_CYCLE               (32'd1_000_000_000/`CPU_FREQ_HZ)

reg                             sys_clk;
reg                             sys_rst_n;

wire                            TXD;

initial begin
`ifdef DUMP_VCD
    $dumpfile("wave.vcd");
    $dumpvars(0, core_tb);
`endif
end

pa_soc_core u_pa_soc_core (
    .clk_i                      (sys_clk),
    .rst_n_i                    (sys_rst_n),

    .txd                        (TXD)
);

core_uart_monitor_tb u_core_uart_monitor_tb (
    .clk_i                      (sys_clk),
    .rst_n_i                    (sys_rst_n),

    .rxd                        (TXD),
    .txd                        ()
);

initial begin
    sys_clk = 1;
    sys_rst_n = 0;

    $readmemh("image.pat", u_pa_soc_core.u_pa_soc_itcm._rom);
end

always begin
    @ (posedge sys_clk) sys_rst_n = 0;
    @ (posedge sys_clk) sys_rst_n = 1;

    while (1) begin
        @ (posedge sys_clk);
    end

    $stop();
end

wire [`DATA_BUS_WIDTH-1:0]      k0 = u_pa_soc_core.u_pa_soc_xreg._xreg[26];
`ifdef TEST_ISA
wire [`DATA_BUS_WIDTH-1:0]      k1 = u_pa_soc_core.u_pa_soc_xreg._xreg[27];
`endif

always begin
    wait (k0 == 32'b1);
    # (`CPU_CYCLE*2);

`ifdef TEST_ISA
    if (k1 == 32'b1) begin
        $display("TEST PASSED.");
    end
    else begin
        $display("TEST FAILED!");
    end
`endif

    $stop();
end

always #(`CPU_CYCLE/2) sys_clk = ~sys_clk;

endmodule