data/full_repos/permissive/431362747/Processor/Processor.srcs/sources_1/new/MBRU.v
data/verilator_xmls/07ad0e14-2556-4e9b-bc78-b282ffb384e4.xml
module MBRU(
    input clk,

    input fetch,
    input [25:0] instruction_in,
    output reg [7:0] instruction_out,
    output reg [27:0] data_out
    );
    
        




    
    
    always @(posedge clk)
       
        begin
            if (fetch == 1)
            begin
            instruction_out<=instruction_in[25:18];
                                          
             data_out<={10'b0000000000,instruction_in[17:0]};
             
            end
         end
  
  
        

            



                 


endmodule
module MBRU(
    input clk,

    input fetch,
    input [25:0] instruction_in,
    output reg [7:0] instruction_out,
    output reg [27:0] data_out
    );

    
        




    
    
    always @(posedge clk)
       
        begin
            if (fetch == 1)
            begin
            instruction_out<=instruction_in[25:18];
                                          
             data_out<={10'b0000000000,instruction_in[17:0]};
             
            end
         end
  
  
        

            



                 


endmodule