data/full_repos/permissive/421048855/Circuits/Sequential Logic/Counters/Count clock.v
1: b'%Error: Cannot find file containing module: Logic/Counters,data/full_repos/permissive/421048855\n        ... Looked in:\n             data/full_repos/permissive/421048855/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/421048855\n             data/full_repos/permissive/421048855/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/421048855.v\n             data/full_repos/permissive/421048855/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/421048855.sv\n             Logic/Counters,data/full_repos/permissive/421048855\n             Logic/Counters,data/full_repos/permissive/421048855.v\n             Logic/Counters,data/full_repos/permissive/421048855.sv\n             obj_dir/Logic/Counters,data/full_repos/permissive/421048855\n             obj_dir/Logic/Counters,data/full_repos/permissive/421048855.v\n             obj_dir/Logic/Counters,data/full_repos/permissive/421048855.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/421048855/Circuits/Sequential\n%Error: Cannot find file containing module: Logic/Counters/Count\n%Error: Cannot find file containing module: clock.v\n%Error: Exiting due to 4 error(s)\n'
module cnt_hh_ten(
input clk,
input reset,
input ena,
output reg [3:0] hh_ten
);
always @(posedge clk) begin
	if(reset) begin
		hh_ten <= 'd1;
	end
	else if(ena) begin
		if(hh_ten == 'd1) begin
			hh_ten <= 'd0;
		end
		else begin
			hh_ten <= 'd1;
		end
	end
end

endmodule
module cnt_hh_ten(
input clk,
input reset,
input ena,
output reg [3:0] hh_ten
);

always @(posedge clk) begin
	if(reset) begin
		hh_ten <= 'd1;
	end
	else if(ena) begin
		if(hh_ten == 'd1) begin
			hh_ten <= 'd0;
		end
		else begin
			hh_ten <= 'd1;
		end
	end
end

endmodule