data/full_repos/permissive/41334298/tests/elementary/t6.v
data/verilator_xmls/649b70f3-8bec-417c-99c7-744084da84cb.xml
module top (a, b, c, y);
input a, b, c;
output y;

nand (y, a, b, c);

endmodule
module top (a, b, c, y);

input a, b, c;
output y;

nand (y, a, b, c);

endmodule