data/full_repos/permissive/505446010/4_state_CPU_1/InstAndDataMemory-3.v
data/verilator_xmls/35e18dc7-2ab9-40bb-8346-605cb23b626a.xml
module InstAndDataMemory(reset, clk, Address, Write_data, MemRead, MemWrite, Mem_data);

	input reset;
	input clk;

	input [31:0] Address;
	input [31:0] Write_data;

	input MemRead;
	input MemWrite;

	output [31:0] Mem_data;
	
	parameter RAM_SIZE = 256;
	parameter RAM_SIZE_BIT = 8;
	parameter RAM_INST_SIZE = 32;
	
	reg [31:0] RAM_data[RAM_SIZE - 1: 0];


	assign Mem_data = MemRead? RAM_data[Address[RAM_SIZE_BIT + 1:2]]: 32'h00000000;
	

	integer i;
	always @(posedge reset or posedge clk) begin
		if (reset) begin


			RAM_data[8'd0] <= {6'h08, 5'd0, 5'd4, 16'h000a};

			RAM_data[8'd1] <= {6'h08, 5'd0, 5'd2, 16'h0000};


			RAM_data[8'd2] <= {6'h04, 5'd4 , 5'd0 , 16'h000a};

			RAM_data[8'd3] <= {6'h00, 5'd4, 5'd4, 5'd8, 5'd0, 6'h20};

			RAM_data[8'd4] <= {6'h08, 5'd8, 5'd8, 16'hfff8};

			RAM_data[8'd5] <= {6'h00, 5'd8, 5'd0, 5'd9, 5'd0, 6'h2a};

			RAM_data[8'd6] <= {6'h00, 5'd0, 5'd9, 5'd9, 5'd31, 6'h00};

			RAM_data[8'd7] <= {6'h00, 5'd0, 5'd9, 5'd9, 5'd31, 6'h03};

			RAM_data[8'd8] <= {6'h00, 5'd8, 5'd9, 5'd10, 5'd0, 6'h24};

			RAM_data[8'd9] <= {6'h08, 5'd10, 5'd10, 16'h0004};

			RAM_data[8'd10] <= {6'h00, 5'd2, 5'd10, 5'd2, 5'd0, 6'h20};

			RAM_data[8'd11] <= {6'h08, 5'd4, 5'd4, 16'hffff};

			RAM_data[8'd12] <= {6'h02, 26'd2};


			RAM_data[8'd13] <= {6'h02, 26'd13};
       


			for (i = RAM_INST_SIZE; i < RAM_SIZE; i = i + 1)
				RAM_data[i] <= 32'h00000000;
		end else if (MemWrite) begin
			RAM_data[Address[RAM_SIZE_BIT + 1:2]] <= Write_data;
		end
	end

endmodule
module InstAndDataMemory(reset, clk, Address, Write_data, MemRead, MemWrite, Mem_data);


	input reset;
	input clk;

	input [31:0] Address;
	input [31:0] Write_data;

	input MemRead;
	input MemWrite;

	output [31:0] Mem_data;
	
	parameter RAM_SIZE = 256;
	parameter RAM_SIZE_BIT = 8;
	parameter RAM_INST_SIZE = 32;
	
	reg [31:0] RAM_data[RAM_SIZE - 1: 0];


	assign Mem_data = MemRead? RAM_data[Address[RAM_SIZE_BIT + 1:2]]: 32'h00000000;
	

	integer i;
	always @(posedge reset or posedge clk) begin
		if (reset) begin


			RAM_data[8'd0] <= {6'h08, 5'd0, 5'd4, 16'h000a};

			RAM_data[8'd1] <= {6'h08, 5'd0, 5'd2, 16'h0000};


			RAM_data[8'd2] <= {6'h04, 5'd4 , 5'd0 , 16'h000a};

			RAM_data[8'd3] <= {6'h00, 5'd4, 5'd4, 5'd8, 5'd0, 6'h20};

			RAM_data[8'd4] <= {6'h08, 5'd8, 5'd8, 16'hfff8};

			RAM_data[8'd5] <= {6'h00, 5'd8, 5'd0, 5'd9, 5'd0, 6'h2a};

			RAM_data[8'd6] <= {6'h00, 5'd0, 5'd9, 5'd9, 5'd31, 6'h00};

			RAM_data[8'd7] <= {6'h00, 5'd0, 5'd9, 5'd9, 5'd31, 6'h03};

			RAM_data[8'd8] <= {6'h00, 5'd8, 5'd9, 5'd10, 5'd0, 6'h24};

			RAM_data[8'd9] <= {6'h08, 5'd10, 5'd10, 16'h0004};

			RAM_data[8'd10] <= {6'h00, 5'd2, 5'd10, 5'd2, 5'd0, 6'h20};

			RAM_data[8'd11] <= {6'h08, 5'd4, 5'd4, 16'hffff};

			RAM_data[8'd12] <= {6'h02, 26'd2};


			RAM_data[8'd13] <= {6'h02, 26'd13};
       


			for (i = RAM_INST_SIZE; i < RAM_SIZE; i = i + 1)
				RAM_data[i] <= 32'h00000000;
		end else if (MemWrite) begin
			RAM_data[Address[RAM_SIZE_BIT + 1:2]] <= Write_data;
		end
	end

endmodule