data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/fpga-support/behav/common/modules/ClkRstGen.sv
1: b"%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/fpga-support/behav/common/modules/ClkRstGen.sv:34: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n    parameter CLK_LOW_TIME  = 5ns,\n                              ^~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/fpga-support/behav/common/modules/ClkRstGen.sv:35: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n    parameter CLK_HIGH_TIME = 5ns,\n                              ^~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/fpga-support/behav/common/modules/ClkRstGen.sv:36: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n    parameter RST_TIME      = 100ns\n                              ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/fpga-support/behav/common/modules/ClkRstGen.sv:43: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic  Clk_CO,\n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/fpga-support/behav/common/modules/ClkRstGen.sv:44: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic  Rst_RBO\n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/fpga-support/behav/common/modules/ClkRstGen.sv:53: syntax error, unexpected always\n  always begin\n  ^~~~~~\n%Error: Exiting due to 6 error(s)\n"
module ClkRstGen


  #(
    parameter CLK_LOW_TIME  = 5ns,
    parameter CLK_HIGH_TIME = 5ns,
    parameter RST_TIME      = 100ns
  )



  (
    input  logic  EndOfSim_SI,
    output logic  Clk_CO,
    output logic  Rst_RBO
  );



  localparam time CLK_PERIOD  = CLK_LOW_TIME + CLK_HIGH_TIME;



  always begin
    Clk_CO  = 0;
    if (Rst_RBO) begin

      if (~EndOfSim_SI) begin
        Clk_CO = 1;
        #CLK_HIGH_TIME;
        Clk_CO = 0;
        #CLK_LOW_TIME;
      end else begin
        $stop(0);
      end
    end else begin

      #CLK_PERIOD;
    end
  end



  initial begin
    Rst_RBO = 0;
    #RST_TIME;
    Rst_RBO = 1;
  end


endmodule
module ClkRstGen


  #(
    parameter CLK_LOW_TIME  = 5ns,
    parameter CLK_HIGH_TIME = 5ns,
    parameter RST_TIME      = 100ns
  )



  (
    input  logic  EndOfSim_SI,
    output logic  Clk_CO,
    output logic  Rst_RBO
  );




  localparam time CLK_PERIOD  = CLK_LOW_TIME + CLK_HIGH_TIME;



  always begin
    Clk_CO  = 0;
    if (Rst_RBO) begin

      if (~EndOfSim_SI) begin
        Clk_CO = 1;
        #CLK_HIGH_TIME;
        Clk_CO = 0;
        #CLK_LOW_TIME;
      end else begin
        $stop(0);
      end
    end else begin

      #CLK_PERIOD;
    end
  end



  initial begin
    Rst_RBO = 0;
    #RST_TIME;
    Rst_RBO = 1;
  end


endmodule