data/full_repos/permissive/433362717/verilog/rtl/controller/UART_SERVER/uart.v
1: b"%Error: data/full_repos/permissive/433362717/verilog/rtl/controller/UART_SERVER/uart.v:70: Cannot find file containing module: 'uart_tx'\nuart_tx #(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/433362717/verilog/rtl/controller/UART_SERVER,data/full_repos/permissive/433362717/uart_tx\n             data/full_repos/permissive/433362717/verilog/rtl/controller/UART_SERVER,data/full_repos/permissive/433362717/uart_tx.v\n             data/full_repos/permissive/433362717/verilog/rtl/controller/UART_SERVER,data/full_repos/permissive/433362717/uart_tx.sv\n             uart_tx\n             uart_tx.v\n             uart_tx.sv\n             obj_dir/uart_tx\n             obj_dir/uart_tx.v\n             obj_dir/uart_tx.sv\n%Error: data/full_repos/permissive/433362717/verilog/rtl/controller/UART_SERVER/uart.v:88: Cannot find file containing module: 'uart_rx'\nuart_rx #(\n^~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module uart #
(
    parameter DATA_WIDTH = 8
)
(
    input  wire                   clk,
    input  wire                   rst,


    input  wire [DATA_WIDTH-1:0]  s_axis_tdata,
    input  wire                   s_axis_tvalid,
    output wire                   s_axis_tready,


    output wire [DATA_WIDTH-1:0]  m_axis_tdata,
    output wire                   m_axis_tvalid,
    input  wire                   m_axis_tready,


    input  wire                   rxd,
    output wire                   txd,


    output wire                   tx_busy,
    output wire                   rx_busy,
    output wire                   rx_overrun_error,
    output wire                   rx_frame_error,


    input  wire [15:0]            prescale

);

uart_tx #(
    .DATA_WIDTH(DATA_WIDTH)
)
uart_tx_inst (
    .clk(clk),
    .rst(rst),

    .s_axis_tdata(s_axis_tdata),
    .s_axis_tvalid(s_axis_tvalid),
    .s_axis_tready(s_axis_tready),

    .txd(txd),

    .busy(tx_busy),

    .prescale(prescale)
);

uart_rx #(
    .DATA_WIDTH(DATA_WIDTH)
)
uart_rx_inst (
    .clk(clk),
    .rst(rst),

    .m_axis_tdata(m_axis_tdata),
    .m_axis_tvalid(m_axis_tvalid),
    .m_axis_tready(m_axis_tready),

    .rxd(rxd),

    .busy(rx_busy),
    .overrun_error(rx_overrun_error),
    .frame_error(rx_frame_error),

    .prescale(prescale)
);

endmodule
module uart #
(
    parameter DATA_WIDTH = 8
)
(
    input  wire                   clk,
    input  wire                   rst,


    input  wire [DATA_WIDTH-1:0]  s_axis_tdata,
    input  wire                   s_axis_tvalid,
    output wire                   s_axis_tready,


    output wire [DATA_WIDTH-1:0]  m_axis_tdata,
    output wire                   m_axis_tvalid,
    input  wire                   m_axis_tready,


    input  wire                   rxd,
    output wire                   txd,


    output wire                   tx_busy,
    output wire                   rx_busy,
    output wire                   rx_overrun_error,
    output wire                   rx_frame_error,


    input  wire [15:0]            prescale

);


uart_tx #(
    .DATA_WIDTH(DATA_WIDTH)
)
uart_tx_inst (
    .clk(clk),
    .rst(rst),

    .s_axis_tdata(s_axis_tdata),
    .s_axis_tvalid(s_axis_tvalid),
    .s_axis_tready(s_axis_tready),

    .txd(txd),

    .busy(tx_busy),

    .prescale(prescale)
);

uart_rx #(
    .DATA_WIDTH(DATA_WIDTH)
)
uart_rx_inst (
    .clk(clk),
    .rst(rst),

    .m_axis_tdata(m_axis_tdata),
    .m_axis_tvalid(m_axis_tvalid),
    .m_axis_tready(m_axis_tready),

    .rxd(rxd),

    .busy(rx_busy),
    .overrun_error(rx_overrun_error),
    .frame_error(rx_frame_error),

    .prescale(prescale)
);

endmodule