data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new/PCSelMux.v
1: b'%Warning-WIDTH: data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new/PCSelMux.v:20: Operator EQ expects 2 bits on the LHS, but LHS\'s VARREF \'PCSel\' generates 1 bits.\n                                                                                                : ... In instance PCSelMux\n        else if(PCSel == 2\'b10)begin\n                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new/PCSelMux.v:16: Operator EQ expects 2 bits on the LHS, but LHS\'s VARREF \'PCSel\' generates 1 bits.\n                                                                                                : ... In instance PCSelMux\n        else if(PCSel == 2\'b01)begin\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new/PCSelMux.v:12: Operator EQ expects 2 bits on the LHS, but LHS\'s VARREF \'PCSel\' generates 1 bits.\n                                                                                                : ... In instance PCSelMux\n        if(PCSel == 2\'b00)begin\n                 ^~\n%Error: Exiting due to 3 warning(s)\n'
module PCSelMux(
    input PCSel,
    input [31:0] In00,
    input [31:0] In01,
    input [31:0] In10,
    output reg [31:0] MuxOut
    );
    
    always@(PCSel or In00 or In01 or In10)begin
        if(PCSel == 2'b00)begin
            MuxOut <= In00;
        end
    
        else if(PCSel == 2'b01)begin
            MuxOut <= In01;
        end

        else if(PCSel == 2'b10)begin
            MuxOut <= In10;
        end
    end
    
endmodule
module PCSelMux(
    input PCSel,
    input [31:0] In00,
    input [31:0] In01,
    input [31:0] In10,
    output reg [31:0] MuxOut
    );

    
    always@(PCSel or In00 or In01 or In10)begin
        if(PCSel == 2'b00)begin
            MuxOut <= In00;
        end
    
        else if(PCSel == 2'b01)begin
            MuxOut <= In01;
        end

        else if(PCSel == 2'b10)begin
            MuxOut <= In10;
        end
    end
    
endmodule