data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v
1: b"%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:540: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\breaker.loop_breaker  (\n  ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block,data/full_repos/permissive/496906136/fpga_tech_buffer\n             data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block,data/full_repos/permissive/496906136/fpga_tech_buffer.v\n             data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block,data/full_repos/permissive/496906136/fpga_tech_buffer.sv\n             fpga_tech_buffer\n             fpga_tech_buffer.v\n             fpga_tech_buffer.sv\n             obj_dir/fpga_tech_buffer\n             obj_dir/fpga_tech_buffer.v\n             obj_dir/fpga_tech_buffer.sv\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:544: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\breaker.lut_tfinish  (\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:548: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\breaker.lut_tstart  (\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:347: Cannot find file containing module: 'fpga_tech_register'\n  fpga_tech_register cell_reg (\n  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:355: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\in_bufs:1.cell_tstart  (\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:359: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\in_bufs:2.cell_tstart  (\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:363: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\in_bufs:3.cell_tstart  (\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:367: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\in_bufs:4.cell_tstart  (\n  ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module fpga_routing_mux_16_4_7(config_i, route_i, route_o);
  wire _00_;
  wire _01_;
  wire _02_;
  wire _03_;
  wire _04_;
  wire _05_;
  wire _06_;
  wire _07_;
  wire _08_;
  wire _09_;
  wire _10_;
  wire _11_;
  wire _12_;
  wire _13_;
  wire _14_;
  input [3:0] config_i;
  input [15:0] route_i;
  wire [15:0] route_int;
  output route_o;
  assign _00_ = config_i[0] ? route_int[1] : route_int[0];
  assign _01_ = config_i[0] ? route_int[5] : route_int[4];
  assign _02_ = config_i[0] ? route_int[9] : route_int[8];
  assign _03_ = config_i[0] ? route_int[13] : route_int[12];
  assign _04_ = config_i[2] ? _11_ : _10_;
  assign _05_ = config_i[0] ? route_int[3] : route_int[2];
  assign _06_ = config_i[0] ? route_int[7] : route_int[6];
  assign _07_ = config_i[0] ? route_int[11] : route_int[10];
  assign _08_ = config_i[0] ? route_int[15] : route_int[14];
  assign _09_ = config_i[2] ? _13_ : _12_;
  assign _10_ = config_i[1] ? _05_ : _00_;
  assign _11_ = config_i[1] ? _06_ : _01_;
  assign _12_ = config_i[1] ? _07_ : _02_;
  assign _13_ = config_i[1] ? _08_ : _03_;
  assign _14_ = config_i[3] ? _09_ : _04_;
  assign route_int = { route_i[15:8], 1'h0, route_i[6:0] };
  assign route_o = _14_;
endmodule
module fpga_routing_mux_16_4_7(config_i, route_i, route_o);

  wire _00_;
  wire _01_;
  wire _02_;
  wire _03_;
  wire _04_;
  wire _05_;
  wire _06_;
  wire _07_;
  wire _08_;
  wire _09_;
  wire _10_;
  wire _11_;
  wire _12_;
  wire _13_;
  wire _14_;
  input [3:0] config_i;
  input [15:0] route_i;
  wire [15:0] route_int;
  output route_o;
  assign _00_ = config_i[0] ? route_int[1] : route_int[0];
  assign _01_ = config_i[0] ? route_int[5] : route_int[4];
  assign _02_ = config_i[0] ? route_int[9] : route_int[8];
  assign _03_ = config_i[0] ? route_int[13] : route_int[12];
  assign _04_ = config_i[2] ? _11_ : _10_;
  assign _05_ = config_i[0] ? route_int[3] : route_int[2];
  assign _06_ = config_i[0] ? route_int[7] : route_int[6];
  assign _07_ = config_i[0] ? route_int[11] : route_int[10];
  assign _08_ = config_i[0] ? route_int[15] : route_int[14];
  assign _09_ = config_i[2] ? _13_ : _12_;
  assign _10_ = config_i[1] ? _05_ : _00_;
  assign _11_ = config_i[1] ? _06_ : _01_;
  assign _12_ = config_i[1] ? _07_ : _02_;
  assign _13_ = config_i[1] ? _08_ : _03_;
  assign _14_ = config_i[3] ? _09_ : _04_;
  assign route_int = { route_i[15:8], 1'h0, route_i[6:0] };
  assign route_o = _14_;
endmodule