data/full_repos/permissive/515565147/LIFO_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/515565147/LIFO_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/515565147/LIFO_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #30 rstn = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/515565147/LIFO_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/515565147/LIFO_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n #10 push = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/515565147/LIFO_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/515565147/LIFO_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/515565147/LIFO_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/515565147/LIFO_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/515565147/LIFO_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/515565147/LIFO_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/515565147/LIFO_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/515565147/LIFO_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/515565147/LIFO_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/515565147/LIFO_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Error: data/full_repos/permissive/515565147/LIFO_tb.v:86: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("lifo.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/515565147/LIFO_tb.v:87: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(1);\n  ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Stack_tb;


 reg clk;
 reg rstn;
 reg pop;
 reg push;
 reg [7:0] din;


 wire empty;
 wire full;
 wire [7:0] dout;


 LIFO uut (
  .clk(clk), 
  .rstn(rstn), 
  .pop(pop), 
  .push(push), 
  .empty(empty), 
  .full(full), 
  .din(din), 
  .dout(dout)
 );

 always #5 clk = ~clk;
 
 task reset();
 begin
 clk = 1'b1;
 rstn = 1'b0;
 pop = 1'b0;
 push = 1'b0;
 din = 8'd0;
 #30 rstn = 1'b1;
 end
 endtask

 task read_stack();
 begin
 pop = 1'b1;
 #10
 pop = 1'b0;
 end
 endtask
   
 task write_stack([7:0]din_tb);
 begin
 push = 1'b1;
 din = din_tb;
 #10 push = 1'b0;
 end
 endtask
  

 initial
 begin
 reset();
 #10;
 repeat(2)
 begin
 write_stack(8'h11);
 #10;
 write_stack(8'h22);
 #10;
 write_stack(8'h33);
 #10;
 write_stack(8'h44);
 #40;
 end
 read_stack();
 #20;
 read_stack();
 #20;
 write_stack(8'hAA);
 #10;
 write_stack(8'hBB);
 #40;
 read_stack();
 #20;
 $finish;
 end
  
initial begin
  $dumpfile("lifo.vcd");
  $dumpvars(1);
end
      
endmodule
module Stack_tb;



 reg clk;
 reg rstn;
 reg pop;
 reg push;
 reg [7:0] din;


 wire empty;
 wire full;
 wire [7:0] dout;


 LIFO uut (
  .clk(clk), 
  .rstn(rstn), 
  .pop(pop), 
  .push(push), 
  .empty(empty), 
  .full(full), 
  .din(din), 
  .dout(dout)
 );

 always #5 clk = ~clk;
 
 task reset();
 begin
 clk = 1'b1;
 rstn = 1'b0;
 pop = 1'b0;
 push = 1'b0;
 din = 8'd0;
 #30 rstn = 1'b1;
 end
 endtask

 task read_stack();
 begin
 pop = 1'b1;
 #10
 pop = 1'b0;
 end
 endtask
   
 task write_stack([7:0]din_tb);
 begin
 push = 1'b1;
 din = din_tb;
 #10 push = 1'b0;
 end
 endtask
  

 initial
 begin
 reset();
 #10;
 repeat(2)
 begin
 write_stack(8'h11);
 #10;
 write_stack(8'h22);
 #10;
 write_stack(8'h33);
 #10;
 write_stack(8'h44);
 #40;
 end
 read_stack();
 #20;
 read_stack();
 #20;
 write_stack(8'hAA);
 #10;
 write_stack(8'hBB);
 #40;
 read_stack();
 #20;
 $finish;
 end
  
initial begin
  $dumpfile("lifo.vcd");
  $dumpvars(1);
end
      
endmodule