data/full_repos/permissive/491169855/LimeSDR-Mini_lms7_trx/mico32_patform/platform1/components/i2cm_opencores/rtl/verilog/i2c_master_core.v
1: b'%Error: data/full_repos/permissive/491169855/LimeSDR-Mini_lms7_trx/mico32_patform/platform1/components/i2cm_opencores/rtl/verilog/i2c_master_core.v:76: Cannot find include file: system_conf.v\n`include "system_conf.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/491169855/LimeSDR-Mini_lms7_trx/mico32_patform/platform1/components/i2cm_opencores/rtl/verilog,data/full_repos/permissive/491169855/system_conf.v\n             data/full_repos/permissive/491169855/LimeSDR-Mini_lms7_trx/mico32_patform/platform1/components/i2cm_opencores/rtl/verilog,data/full_repos/permissive/491169855/system_conf.v.v\n             data/full_repos/permissive/491169855/LimeSDR-Mini_lms7_trx/mico32_patform/platform1/components/i2cm_opencores/rtl/verilog,data/full_repos/permissive/491169855/system_conf.v.sv\n             system_conf.v\n             system_conf.v.v\n             system_conf.v.sv\n             obj_dir/system_conf.v\n             obj_dir/system_conf.v.v\n             obj_dir/system_conf.v.sv\n%Error: data/full_repos/permissive/491169855/LimeSDR-Mini_lms7_trx/mico32_patform/platform1/components/i2cm_opencores/rtl/verilog/i2c_master_core.v:79: Cannot find include file: ./timescale.v\n`include "./timescale.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/491169855/LimeSDR-Mini_lms7_trx/mico32_patform/platform1/components/i2cm_opencores/rtl/verilog/i2c_master_core.v:82: Cannot find include file: ./i2c_master_defines.v\n`include "./i2c_master_defines.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module i2cm_opencores 
 		#(parameter SPEED = 400,
		  parameter SYSCLK = 50)
 		(SDA        ,
		 SCL        ,
		 CLK_I      ,
		 RST_I      ,
		 INTR_N     ,

		 I2CM_ADR_I  ,
		 I2CM_DAT_I  ,
		 I2CM_WE_I   ,
		 I2CM_CYC_I  ,
		 I2CM_STB_I  ,
		 I2CM_SEL_I  ,
		 I2CM_CTI_I  ,
		 I2CM_BTE_I  ,
		 I2CM_LOCK_I ,
		 I2CM_DAT_O  ,
		 I2CM_ACK_O  ,
		 I2CM_ERR_O  ,
		 I2CM_RTY_O  
		 );

   inout       SDA;
   inout       SCL;
   input       CLK_I;
   input       RST_I;
   
   output      INTR_N;
   
   input [31:0]	I2CM_ADR_I;  
   input [31:0]	I2CM_DAT_I;
   input		I2CM_WE_I;   
   input		I2CM_CYC_I;   
   input		I2CM_STB_I;   
   input [3:0]	I2CM_SEL_I;   
   input [2:0]	I2CM_CTI_I;
   input [1:0]	I2CM_BTE_I;
   input		I2CM_LOCK_I;
   output [31:0] I2CM_DAT_O;   
   output		I2CM_ACK_O;   
   output		I2CM_ERR_O;   
   output		I2CM_RTY_O;



	parameter ARST_LVL = 1'b0;
	parameter PRESCALE = (((SYSCLK*1000000)/(5*SPEED*1000))-1);






	wire        wb_clk;
	assign wb_clk = CLK_I;
	wire        wb_rst;
	assign wb_rst = 1'b0;
	wire        arst;
	assign arst =	~RST_I;
	wire  [2:0] wb_adr;
	assign wb_adr = I2CM_ADR_I[4:2];
	wire  [7:0] wb_dat_i;
	assign wb_dat_i = I2CM_DAT_I[7:0];
	reg [7:0] wb_dat_o;
	assign I2CM_DAT_O[7:0] = wb_dat_o;
	wire        wb_we;
	assign wb_we = I2CM_WE_I;
	wire        wb_stb;
	assign wb_stb = I2CM_STB_I;
	wire        wb_cyc;
	assign wb_cyc = I2CM_CYC_I;
	reg       wb_ack;
	assign I2CM_ACK_O = wb_ack;
	reg       wb_inta;
	assign INTR_N = wb_inta;
	assign I2CM_ERR_O = 1'b0;
	assign I2CM_RTY_O = 1'b0;



	wire scl_i;
	wire scl_o;
	wire scl_oen;


	BB scl_inst(.I(scl_o), .T(scl_oen), .O(scl_i), .B(SCL));


	wire sda_i;
	wire sda_o;
	wire sda_oen;


	BB sda_inst(.I(sda_o), .T(sda_oen), .O(sda_i), .B(SDA));
	





	reg  [15:0] prer;
	reg  [ 7:0] ctr;
	reg  [ 7:0] txr;
	wire [ 7:0] rxr;
	reg  [ 7:0] cr;
	wire [ 7:0] sr;


	wire done;



	wire irxack;
	reg  rxack;
	reg  tip;
	reg  irq_flag;
	wire i2c_busy;
	wire i2c_al;
	reg  al;


	wire core_en;
	wire ien;






	wire rst = arst ^ ARST_LVL;


	wire wb_wacc = wb_cyc & wb_stb & wb_we;


	always @(posedge wb_clk)
	  wb_ack <= #1 wb_cyc & wb_stb & ~wb_ack;


	always @(posedge wb_clk)
	begin
	  case (wb_adr)
	    3'b000: wb_dat_o <= #1 prer[ 7:0];
	    3'b001: wb_dat_o <= #1 prer[15:8];
	    3'b010: wb_dat_o <= #1 ctr;
	    3'b011: wb_dat_o <= #1 rxr;
	    3'b100: wb_dat_o <= #1 sr;
	    3'b101: wb_dat_o <= #1 txr;
	    3'b110: wb_dat_o <= #1 cr;
	    3'b111: wb_dat_o <= #1 0;
	  endcase
	end


	always @(posedge wb_clk or negedge rst)
	  if (!rst)
	    begin
	        prer <= #1 16'hffff;

	        ctr  <= #1  8'h0;
	        txr  <= #1  8'h0;
	    end
	  else if (wb_rst)
	    begin
	        prer <= #1 16'hffff;

	        ctr  <= #1  8'h0;
	        txr  <= #1  8'h0;
	    end
	  else
	    if (wb_wacc)
	      case (wb_adr)
	         3'b000 : prer [ 7:0] <= #1 wb_dat_i;
	         3'b001 : prer [15:8] <= #1 wb_dat_i;
	         3'b010 : ctr         <= #1 wb_dat_i;
	         3'b011 : txr         <= #1 wb_dat_i;
	         default: ;
	      endcase


	always @(posedge wb_clk or negedge rst)
	  if (~rst)
	    cr <= #1 8'h0;
	  else if (wb_rst)
	    cr <= #1 8'h0;
	  else if (wb_wacc)
	    begin
	        if (core_en & (wb_adr == 3'b100) )
	          cr <= #1 wb_dat_i;
	    end
	  else
	    begin
	        if (done | i2c_al)
	          cr[7:4] <= #1 4'h0;

	        cr[2:1] <= #1 2'b0;
	        cr[0]   <= #1 1'b0;
	    end



	wire sta  = cr[7];
	wire sto  = cr[6];
	wire rd   = cr[5];
	wire wr   = cr[4];
	wire ack  = cr[3];
	wire iack = cr[0];


	assign core_en = ctr[7];
	assign ien = ctr[6];


	i2c_master_byte_ctrl byte_controller (
		.clk      ( wb_clk     ),
		.rst      ( wb_rst     ),
		.nReset   ( rst        ),
		.ena      ( core_en      ),
		.clk_cnt  ( prer         ),
		.start    ( sta          ),
		.stop     ( sto          ),
		.read     ( rd           ),
		.write    ( wr           ),
		.ack_in   ( ack          ),
		.din      ( txr          ),
		.cmd_ack  ( done         ),
		.ack_out  ( irxack       ),
		.dout     ( rxr          ),
		.i2c_busy ( i2c_busy     ),
		.i2c_al   ( i2c_al       ),
		.scl_i    ( scl_i    ),
		.scl_o    ( scl_o    ),
		.scl_oen  ( scl_oen ),
		.sda_i    ( sda_i    ),
		.sda_o    ( sda_o    ),
		.sda_oen  ( sda_oen )
	);


	always @(posedge wb_clk or negedge rst)
	  if (!rst)
	    begin
	        al       <= #1 1'b0;
	        rxack    <= #1 1'b0;
	        tip      <= #1 1'b0;
	        irq_flag <= #1 1'b0;
	    end
	  else if (wb_rst)
	    begin
	        al       <= #1 1'b0;
	        rxack    <= #1 1'b0;
	        tip      <= #1 1'b0;
	        irq_flag <= #1 1'b0;
	    end
	  else
	    begin
	        al       <= #1 i2c_al | (al & ~sta);
	        rxack    <= #1 irxack;
	        tip      <= #1 ((rd | wr) & core_en);
	        irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack;
	    end


	always @(posedge wb_clk or negedge rst)
	  if (!rst)
	    wb_inta <= #1 1'b0;
	  else if (wb_rst)
	    wb_inta <= #1 1'b0;
	  else
	    wb_inta <= #1 irq_flag && ien;


	assign sr[7]   = rxack;
	assign sr[6]   = i2c_busy;
	assign sr[5]   = al;
	assign sr[4:2] = 3'h0;
	assign sr[1]   = tip;
	assign sr[0]   = irq_flag;

endmodule
module i2cm_opencores 
 		#(parameter SPEED = 400,
		  parameter SYSCLK = 50)
 		(SDA        ,
		 SCL        ,
		 CLK_I      ,
		 RST_I      ,
		 INTR_N     ,

		 I2CM_ADR_I  ,
		 I2CM_DAT_I  ,
		 I2CM_WE_I   ,
		 I2CM_CYC_I  ,
		 I2CM_STB_I  ,
		 I2CM_SEL_I  ,
		 I2CM_CTI_I  ,
		 I2CM_BTE_I  ,
		 I2CM_LOCK_I ,
		 I2CM_DAT_O  ,
		 I2CM_ACK_O  ,
		 I2CM_ERR_O  ,
		 I2CM_RTY_O  
		 );


   inout       SDA;
   inout       SCL;
   input       CLK_I;
   input       RST_I;
   
   output      INTR_N;
   
   input [31:0]	I2CM_ADR_I;  
   input [31:0]	I2CM_DAT_I;
   input		I2CM_WE_I;   
   input		I2CM_CYC_I;   
   input		I2CM_STB_I;   
   input [3:0]	I2CM_SEL_I;   
   input [2:0]	I2CM_CTI_I;
   input [1:0]	I2CM_BTE_I;
   input		I2CM_LOCK_I;
   output [31:0] I2CM_DAT_O;   
   output		I2CM_ACK_O;   
   output		I2CM_ERR_O;   
   output		I2CM_RTY_O;



	parameter ARST_LVL = 1'b0;
	parameter PRESCALE = (((SYSCLK*1000000)/(5*SPEED*1000))-1);






	wire        wb_clk;
	assign wb_clk = CLK_I;
	wire        wb_rst;
	assign wb_rst = 1'b0;
	wire        arst;
	assign arst =	~RST_I;
	wire  [2:0] wb_adr;
	assign wb_adr = I2CM_ADR_I[4:2];
	wire  [7:0] wb_dat_i;
	assign wb_dat_i = I2CM_DAT_I[7:0];
	reg [7:0] wb_dat_o;
	assign I2CM_DAT_O[7:0] = wb_dat_o;
	wire        wb_we;
	assign wb_we = I2CM_WE_I;
	wire        wb_stb;
	assign wb_stb = I2CM_STB_I;
	wire        wb_cyc;
	assign wb_cyc = I2CM_CYC_I;
	reg       wb_ack;
	assign I2CM_ACK_O = wb_ack;
	reg       wb_inta;
	assign INTR_N = wb_inta;
	assign I2CM_ERR_O = 1'b0;
	assign I2CM_RTY_O = 1'b0;



	wire scl_i;
	wire scl_o;
	wire scl_oen;


	BB scl_inst(.I(scl_o), .T(scl_oen), .O(scl_i), .B(SCL));


	wire sda_i;
	wire sda_o;
	wire sda_oen;


	BB sda_inst(.I(sda_o), .T(sda_oen), .O(sda_i), .B(SDA));
	





	reg  [15:0] prer;
	reg  [ 7:0] ctr;
	reg  [ 7:0] txr;
	wire [ 7:0] rxr;
	reg  [ 7:0] cr;
	wire [ 7:0] sr;


	wire done;



	wire irxack;
	reg  rxack;
	reg  tip;
	reg  irq_flag;
	wire i2c_busy;
	wire i2c_al;
	reg  al;


	wire core_en;
	wire ien;






	wire rst = arst ^ ARST_LVL;


	wire wb_wacc = wb_cyc & wb_stb & wb_we;


	always @(posedge wb_clk)
	  wb_ack <= #1 wb_cyc & wb_stb & ~wb_ack;


	always @(posedge wb_clk)
	begin
	  case (wb_adr)
	    3'b000: wb_dat_o <= #1 prer[ 7:0];
	    3'b001: wb_dat_o <= #1 prer[15:8];
	    3'b010: wb_dat_o <= #1 ctr;
	    3'b011: wb_dat_o <= #1 rxr;
	    3'b100: wb_dat_o <= #1 sr;
	    3'b101: wb_dat_o <= #1 txr;
	    3'b110: wb_dat_o <= #1 cr;
	    3'b111: wb_dat_o <= #1 0;
	  endcase
	end


	always @(posedge wb_clk or negedge rst)
	  if (!rst)
	    begin
	        prer <= #1 16'hffff;

	        ctr  <= #1  8'h0;
	        txr  <= #1  8'h0;
	    end
	  else if (wb_rst)
	    begin
	        prer <= #1 16'hffff;

	        ctr  <= #1  8'h0;
	        txr  <= #1  8'h0;
	    end
	  else
	    if (wb_wacc)
	      case (wb_adr)
	         3'b000 : prer [ 7:0] <= #1 wb_dat_i;
	         3'b001 : prer [15:8] <= #1 wb_dat_i;
	         3'b010 : ctr         <= #1 wb_dat_i;
	         3'b011 : txr         <= #1 wb_dat_i;
	         default: ;
	      endcase


	always @(posedge wb_clk or negedge rst)
	  if (~rst)
	    cr <= #1 8'h0;
	  else if (wb_rst)
	    cr <= #1 8'h0;
	  else if (wb_wacc)
	    begin
	        if (core_en & (wb_adr == 3'b100) )
	          cr <= #1 wb_dat_i;
	    end
	  else
	    begin
	        if (done | i2c_al)
	          cr[7:4] <= #1 4'h0;

	        cr[2:1] <= #1 2'b0;
	        cr[0]   <= #1 1'b0;
	    end



	wire sta  = cr[7];
	wire sto  = cr[6];
	wire rd   = cr[5];
	wire wr   = cr[4];
	wire ack  = cr[3];
	wire iack = cr[0];


	assign core_en = ctr[7];
	assign ien = ctr[6];


	i2c_master_byte_ctrl byte_controller (
		.clk      ( wb_clk     ),
		.rst      ( wb_rst     ),
		.nReset   ( rst        ),
		.ena      ( core_en      ),
		.clk_cnt  ( prer         ),
		.start    ( sta          ),
		.stop     ( sto          ),
		.read     ( rd           ),
		.write    ( wr           ),
		.ack_in   ( ack          ),
		.din      ( txr          ),
		.cmd_ack  ( done         ),
		.ack_out  ( irxack       ),
		.dout     ( rxr          ),
		.i2c_busy ( i2c_busy     ),
		.i2c_al   ( i2c_al       ),
		.scl_i    ( scl_i    ),
		.scl_o    ( scl_o    ),
		.scl_oen  ( scl_oen ),
		.sda_i    ( sda_i    ),
		.sda_o    ( sda_o    ),
		.sda_oen  ( sda_oen )
	);


	always @(posedge wb_clk or negedge rst)
	  if (!rst)
	    begin
	        al       <= #1 1'b0;
	        rxack    <= #1 1'b0;
	        tip      <= #1 1'b0;
	        irq_flag <= #1 1'b0;
	    end
	  else if (wb_rst)
	    begin
	        al       <= #1 1'b0;
	        rxack    <= #1 1'b0;
	        tip      <= #1 1'b0;
	        irq_flag <= #1 1'b0;
	    end
	  else
	    begin
	        al       <= #1 i2c_al | (al & ~sta);
	        rxack    <= #1 irxack;
	        tip      <= #1 ((rd | wr) & core_en);
	        irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack;
	    end


	always @(posedge wb_clk or negedge rst)
	  if (!rst)
	    wb_inta <= #1 1'b0;
	  else if (wb_rst)
	    wb_inta <= #1 1'b0;
	  else
	    wb_inta <= #1 irq_flag && ien;


	assign sr[7]   = rxack;
	assign sr[6]   = i2c_busy;
	assign sr[5]   = al;
	assign sr[4:2] = 3'h0;
	assign sr[1]   = tip;
	assign sr[0]   = irq_flag;

endmodule