data/full_repos/permissive/434840709/USTB_digital_logic_homework/task3/clkDiv.v
data/verilator_xmls/0fd5b199-704c-4915-b0e6-33382bcb8b2f.xml
module clkDiv(
input clk100mhz,
output clk190hz,
output clk3hz,
output	reg	clk10m=0
    );
	reg	[2:0]	cnt=0;
    reg[25:0] count=0;
    assign clk190hz = count[18];
    assign clk3hz = count[25];
	



	
    always@(posedge clk100mhz)
        count<=count+1;
	always@(posedge clk100mhz)
		begin
			if(cnt==4)
				cnt<=0;
			else
				cnt<=cnt+1;
		end
	always@(posedge clk100mhz)
		begin
			if(cnt==4)
				clk10m<=~clk10m;
			else
				;
		end
endmodule
module clkDiv(
input clk100mhz,
output clk190hz,
output clk3hz,
output	reg	clk10m=0
    );

	reg	[2:0]	cnt=0;
    reg[25:0] count=0;
    assign clk190hz = count[18];
    assign clk3hz = count[25];
	



	
    always@(posedge clk100mhz)
        count<=count+1;
	always@(posedge clk100mhz)
		begin
			if(cnt==4)
				cnt<=0;
			else
				cnt<=cnt+1;
		end
	always@(posedge clk100mhz)
		begin
			if(cnt==4)
				clk10m<=~clk10m;
			else
				;
		end
endmodule