data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/auc_mmul2.v
1: b'%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/auc_mmul2.v:293: syntax error, unexpected final, expecting TYPE-IDENTIFIER\nassign    finalisidle = final == F_IDLE;\n                        ^~~~~\n%Error: Exiting due to 1 error(s)\n'
module auc_mmul
    (
     clk,
     rst,
     

     mmul_en,


     mmul_auvld,
     mmul_audat,
     

     mmul_done,


     mmul_opcode,
     mmul_auen,
     mmul_carry,
     

     mmul_radd,
     mmul_rdat,
     mmul_wadd,
     mmul_wen,
     mmul_wdat
     );



parameter           WID   = 256;
parameter           CURWID = 255;
parameter           AWID  = 5;
parameter           OPWID = 4;

localparam          INIT   = 0;
localparam          X25519 = 9;
localparam          A24    = 256'd121665;
localparam          EXP_K  = 256'd19;
localparam          EXP_2K = 256'd361;



localparam          X_G     = 0;
localparam          Y_G     = 1;
localparam          X_3G    = 2;
localparam          Y_3G    = 3;
localparam          Z_3G    = 3;
localparam          X_5G    = 5;
localparam          Y_5G    = 6;
localparam          Z_5G    = 7;
localparam          X_7G    = 8;
localparam          Y_7G    = 9;
localparam          Z_7G    = 10;

localparam          K_NUM   = 11;
localparam          K_INV   = 12;
localparam          R_NUM   = 13;
localparam          S_NUM   = 14;
localparam          X_KG    = 15;
localparam          HASH    = 16;
localparam          PKEY    = 17;
localparam          ZRRAM   = 18;
localparam          ONERAM  = 19;

localparam          TEMP0   = 20;
localparam          TEMP1   = 21;
localparam          TEMP2   = 22;
localparam          TEMP3   = 23;
localparam          TEMP4   = 24;
localparam          TEMP5   = 25;
localparam          TEMP6   = 26;   
localparam          TEMP7   = 27;
localparam          TEMP8   = 28;


localparam          X_2   = 20;
localparam          Z_2   = 21;
localparam          X_3   = 22;
localparam          Z_3   = 23;
localparam          A     = 24;
localparam          DA    = 24;
localparam          B     = 25;
localparam          CB    = 25;
localparam          AA    = 26;
localparam          C     = 26;
localparam          DACBS = 26;
localparam          BB    = 27;
localparam          Z2TEMP= 27;
localparam          D     = 27;
localparam          DACB  = 27;
localparam          E     = 28;
localparam          DACB2 = 28;
localparam          U255  = 30;
localparam          A24   = 31;



localparam          X_2   = 20;
localparam          Z_2   = 21;
localparam          X_3   = 22;
localparam          Z_3   = 23;
localparam          E     = 24;
localparam          TY    = 25;
localparam          POWZ  = 26;


localparam          S_RP    = 29;
localparam          S_RPH   = 30;
localparam          BLNK    = 31;




localparam          Z2VL   = 0;
localparam          X3VL   = X25519;
localparam          Z3VL   = 1;


localparam          IDLE    = 2'b00;
localparam          INIT    = 2'b01;
localparam          COMP    = 2'b10;
localparam          FINAL   = 2'b11;


localparam          ISWID    = 3;
localparam          I_IDLE   = 3'b000;
localparam          I_INITX2 = 3'b001;
localparam          I_INITZ2 = 3'b010;
localparam          I_INITX3 = 3'b011;
localparam          I_INITZ3 = 3'b100;
localparam          I_INITA24= 3'b101;
localparam          I_INITU  = 3'b110;




localparam          FSWID       = 5;
localparam          F_IDLE      = 5'b00000;
localparam          F_SWAPZ2    = 5'b00001;
localparam          F_SWAPZ3    = 5'b00010;
localparam          F_SWAPX2    = 5'b00011;
localparam          F_SWAPX3    = 5'b00100;
localparam          F_SWAPL     = 5'b00101;
localparam          F_FINALEK   = 5'b00110;
localparam          F_MPTY1     = 5'b00111;
localparam          F_MPTY2     = 5'b01000;

localparam          F_EETY      = 5'b01001;

localparam          F_EETY2     = 5'b01010;

localparam          F_TYTY1     = 5'b01011;
localparam          F_TYTY2     = 5'b01100;


localparam          F_POWZ1     = 5'b01101;
localparam          F_POWZ2     = 5'b01110;
localparam          F_RSLT1     = 5'b01111;
localparam          F_RSLT2     = 5'b10000;





input     clk;
input     rst;
     

input     mmul_en;


input [WID-1:0] mmul_audat;
input           mmul_auvld;


output          mmul_done;


output [OPWID-1:0] mmul_opcode;
output             mmul_auen;
output             mmul_carry;


output [AWID-1:0]  mmul_radd;
output [AWID-1:0]  mmul_wadd;
output             mmul_wen;
output [WID-1:0]   mmul_wdat;






reg                init_done;
reg                comp_done;
reg                final_done;

reg [1:0]          main;

wire      mainisidle;

assign    mainisidle = main == IDLE;

wire      mainenidle;

assign    mainenidle = mainisidle & mmul_en;

reg       main_en;

wire      mainisinit;

assign    mainisinit = main == INIT;

wire      maineninit;

assign    maineninit = mainisinit & main_en;

wire      mainiscomp;

assign    mainiscomp = main == COMP;

wire      mainencomp;

assign    mainencomp = mainiscomp & main_en;

wire      mainisfinal;

assign    mainisfinal = main == FINAL;

wire      mainenfinal;

assign    mainenfinal = mainisfinal & main_en;

always@(posedge clk)
    begin
    if(rst)
        begin
        main <= IDLE;
        main_en <= 1'b0;
        end
    else
        begin
        if(mainenidle)
            begin
            main <= INIT;
            main_en <= 1'b1;
            end
        else if(maindoneinit)
            begin
            main <= COMP;
            main_en <= 1'b1;
            end
        else if(maindonecomp)
            begin
            main <= FINAL;
            main_en <= 1'b1;
            end
        else if(maindonefinal)
            begin
            main <= IDLE;
            main_en <= 1'b0;
            end
        else
            begin
            main <= main;
            main_en <= 1'b0;
            end
        end
    end




reg [FSWID-1:0] final_state;

wire      finalisidle; 

assign    finalisidle = final == F_IDLE;

wire      finalisidlevld; 

assign    finalisidlevld = finalisidle & mmul_auvld;

always@(posedge clk)
    begin
    if(rst)
        begin
        final_state <= F_IDLE;
        final_done <= 1'b0;
        end
    else
        begin
        if(mainenfinal & finalisidle)
            begin
            final_state <= F_SWAPZ2;
            final_done <= 1'b0;
            end
        else if(finalisswapz2)
            begin
            final_state <= F_SWAPZ3;
            final_done <= 1'b0;
            end
        else if(finalisswapz3vld)
            begin
            final_state <= F_SWAPX2;
            final_done <= 1'b0;
            end
        else if(finalisswapx2)
            begin
            final_state <= F_SWAPX3;
            final_done <= 1'b0;
            end
        else if(finalisswapx3vld)
            begin
            final_state <= F_SWAPL;
            final_done <= 1'b0;
            end
        else if(finalisswapl)
            begin
            final_state <= F_FINALEK;
            final_done <= 1'b0;
            end
        else if(finalisfinalek)
            begin
            final_state <= F_MPTY1;
            final_done <= 1'b0;
            end
        else if(finalismpty1)
            begin
            final_state <= F_MPTY2;
            final_done <= 1'b0;
            end
        else if(finalismpty2)
            begin
            final_state <= F_EETY;
            final_done <= 1'b0;
            end
        else if(finaliseety)
            begin
            final_state <= F_EETY2;
            final_done <= 1'b0;
            end
        else if(finaliseety2)
            begin
            final_state <= F_TYTY1;
            final_done <= 1'b0;
            end
        else if(finalistyty1)
            begin
            final_state <= F_TYTY2;
            final_done <= 1'b0;
            end
        else if(finalistyty2)
            begin
            final_state <= F_POWZ1;
            final_done <= 1'b0;
            end
        else if(finalispowz1)
            begin
            final_state <= F_POWZ2;
            final_done <= 1'b0;
            end
        else if(finalispowz2)
            begin
            final_state <= F_RSLT1;
            final_done <= 1'b0;
            end
        else if(finalisrslt1)
            begin
            final_state <= F_RSLT2;
            final_done <= 1'b0;
            end
        else if(finalisrslt2)
            begin
            final_state <= F_IDLE;
            final_done <= 1'b0;
            end
        else
            begin
            final_state <= final_state;
            final_done <= 1'b0;
            end
        end
    end
endmodule
module auc_mmul
    (
     clk,
     rst,
     

     mmul_en,


     mmul_auvld,
     mmul_audat,
     

     mmul_done,


     mmul_opcode,
     mmul_auen,
     mmul_carry,
     

     mmul_radd,
     mmul_rdat,
     mmul_wadd,
     mmul_wen,
     mmul_wdat
     );




parameter           WID   = 256;
parameter           CURWID = 255;
parameter           AWID  = 5;
parameter           OPWID = 4;

localparam          INIT   = 0;
localparam          X25519 = 9;
localparam          A24    = 256'd121665;
localparam          EXP_K  = 256'd19;
localparam          EXP_2K = 256'd361;



localparam          X_G     = 0;
localparam          Y_G     = 1;
localparam          X_3G    = 2;
localparam          Y_3G    = 3;
localparam          Z_3G    = 3;
localparam          X_5G    = 5;
localparam          Y_5G    = 6;
localparam          Z_5G    = 7;
localparam          X_7G    = 8;
localparam          Y_7G    = 9;
localparam          Z_7G    = 10;

localparam          K_NUM   = 11;
localparam          K_INV   = 12;
localparam          R_NUM   = 13;
localparam          S_NUM   = 14;
localparam          X_KG    = 15;
localparam          HASH    = 16;
localparam          PKEY    = 17;
localparam          ZRRAM   = 18;
localparam          ONERAM  = 19;

localparam          TEMP0   = 20;
localparam          TEMP1   = 21;
localparam          TEMP2   = 22;
localparam          TEMP3   = 23;
localparam          TEMP4   = 24;
localparam          TEMP5   = 25;
localparam          TEMP6   = 26;   
localparam          TEMP7   = 27;
localparam          TEMP8   = 28;


localparam          X_2   = 20;
localparam          Z_2   = 21;
localparam          X_3   = 22;
localparam          Z_3   = 23;
localparam          A     = 24;
localparam          DA    = 24;
localparam          B     = 25;
localparam          CB    = 25;
localparam          AA    = 26;
localparam          C     = 26;
localparam          DACBS = 26;
localparam          BB    = 27;
localparam          Z2TEMP= 27;
localparam          D     = 27;
localparam          DACB  = 27;
localparam          E     = 28;
localparam          DACB2 = 28;
localparam          U255  = 30;
localparam          A24   = 31;



localparam          X_2   = 20;
localparam          Z_2   = 21;
localparam          X_3   = 22;
localparam          Z_3   = 23;
localparam          E     = 24;
localparam          TY    = 25;
localparam          POWZ  = 26;


localparam          S_RP    = 29;
localparam          S_RPH   = 30;
localparam          BLNK    = 31;




localparam          Z2VL   = 0;
localparam          X3VL   = X25519;
localparam          Z3VL   = 1;


localparam          IDLE    = 2'b00;
localparam          INIT    = 2'b01;
localparam          COMP    = 2'b10;
localparam          FINAL   = 2'b11;


localparam          ISWID    = 3;
localparam          I_IDLE   = 3'b000;
localparam          I_INITX2 = 3'b001;
localparam          I_INITZ2 = 3'b010;
localparam          I_INITX3 = 3'b011;
localparam          I_INITZ3 = 3'b100;
localparam          I_INITA24= 3'b101;
localparam          I_INITU  = 3'b110;




localparam          FSWID       = 5;
localparam          F_IDLE      = 5'b00000;
localparam          F_SWAPZ2    = 5'b00001;
localparam          F_SWAPZ3    = 5'b00010;
localparam          F_SWAPX2    = 5'b00011;
localparam          F_SWAPX3    = 5'b00100;
localparam          F_SWAPL     = 5'b00101;
localparam          F_FINALEK   = 5'b00110;
localparam          F_MPTY1     = 5'b00111;
localparam          F_MPTY2     = 5'b01000;

localparam          F_EETY      = 5'b01001;

localparam          F_EETY2     = 5'b01010;

localparam          F_TYTY1     = 5'b01011;
localparam          F_TYTY2     = 5'b01100;


localparam          F_POWZ1     = 5'b01101;
localparam          F_POWZ2     = 5'b01110;
localparam          F_RSLT1     = 5'b01111;
localparam          F_RSLT2     = 5'b10000;





input     clk;
input     rst;
     

input     mmul_en;


input [WID-1:0] mmul_audat;
input           mmul_auvld;


output          mmul_done;


output [OPWID-1:0] mmul_opcode;
output             mmul_auen;
output             mmul_carry;


output [AWID-1:0]  mmul_radd;
output [AWID-1:0]  mmul_wadd;
output             mmul_wen;
output [WID-1:0]   mmul_wdat;






reg                init_done;
reg                comp_done;
reg                final_done;

reg [1:0]          main;

wire      mainisidle;

assign    mainisidle = main == IDLE;

wire      mainenidle;

assign    mainenidle = mainisidle & mmul_en;

reg       main_en;

wire      mainisinit;

assign    mainisinit = main == INIT;

wire      maineninit;

assign    maineninit = mainisinit & main_en;

wire      mainiscomp;

assign    mainiscomp = main == COMP;

wire      mainencomp;

assign    mainencomp = mainiscomp & main_en;

wire      mainisfinal;

assign    mainisfinal = main == FINAL;

wire      mainenfinal;

assign    mainenfinal = mainisfinal & main_en;

always@(posedge clk)
    begin
    if(rst)
        begin
        main <= IDLE;
        main_en <= 1'b0;
        end
    else
        begin
        if(mainenidle)
            begin
            main <= INIT;
            main_en <= 1'b1;
            end
        else if(maindoneinit)
            begin
            main <= COMP;
            main_en <= 1'b1;
            end
        else if(maindonecomp)
            begin
            main <= FINAL;
            main_en <= 1'b1;
            end
        else if(maindonefinal)
            begin
            main <= IDLE;
            main_en <= 1'b0;
            end
        else
            begin
            main <= main;
            main_en <= 1'b0;
            end
        end
    end




reg [FSWID-1:0] final_state;

wire      finalisidle; 

assign    finalisidle = final == F_IDLE;

wire      finalisidlevld; 

assign    finalisidlevld = finalisidle & mmul_auvld;

always@(posedge clk)
    begin
    if(rst)
        begin
        final_state <= F_IDLE;
        final_done <= 1'b0;
        end
    else
        begin
        if(mainenfinal & finalisidle)
            begin
            final_state <= F_SWAPZ2;
            final_done <= 1'b0;
            end
        else if(finalisswapz2)
            begin
            final_state <= F_SWAPZ3;
            final_done <= 1'b0;
            end
        else if(finalisswapz3vld)
            begin
            final_state <= F_SWAPX2;
            final_done <= 1'b0;
            end
        else if(finalisswapx2)
            begin
            final_state <= F_SWAPX3;
            final_done <= 1'b0;
            end
        else if(finalisswapx3vld)
            begin
            final_state <= F_SWAPL;
            final_done <= 1'b0;
            end
        else if(finalisswapl)
            begin
            final_state <= F_FINALEK;
            final_done <= 1'b0;
            end
        else if(finalisfinalek)
            begin
            final_state <= F_MPTY1;
            final_done <= 1'b0;
            end
        else if(finalismpty1)
            begin
            final_state <= F_MPTY2;
            final_done <= 1'b0;
            end
        else if(finalismpty2)
            begin
            final_state <= F_EETY;
            final_done <= 1'b0;
            end
        else if(finaliseety)
            begin
            final_state <= F_EETY2;
            final_done <= 1'b0;
            end
        else if(finaliseety2)
            begin
            final_state <= F_TYTY1;
            final_done <= 1'b0;
            end
        else if(finalistyty1)
            begin
            final_state <= F_TYTY2;
            final_done <= 1'b0;
            end
        else if(finalistyty2)
            begin
            final_state <= F_POWZ1;
            final_done <= 1'b0;
            end
        else if(finalispowz1)
            begin
            final_state <= F_POWZ2;
            final_done <= 1'b0;
            end
        else if(finalispowz2)
            begin
            final_state <= F_RSLT1;
            final_done <= 1'b0;
            end
        else if(finalisrslt1)
            begin
            final_state <= F_RSLT2;
            final_done <= 1'b0;
            end
        else if(finalisrslt2)
            begin
            final_state <= F_IDLE;
            final_done <= 1'b0;
            end
        else
            begin
            final_state <= final_state;
            final_done <= 1'b0;
            end
        end
    end
endmodule