data/full_repos/permissive/427885334/rtl/apu/n64_sample_i2s.v
data/verilator_xmls/a9b9a618-31ae-4451-8504-c730f4c35702.xml
module n64_sample_i2s (
  MCLK_i,
  nRST_i,


  SCLK_i,
  SDATA_i,
  LRCLK_i,


  PDATA_LEFT_o,
  PDATA_RIGHT_o,
  PDATA_VALID_o
);

input MCLK_i;
input nRST_i;

input SCLK_i;
input SDATA_i;
input LRCLK_i;

output reg signed [15:0] PDATA_LEFT_o = 16'h0;
output reg signed [15:0] PDATA_RIGHT_o = 16'h0;
output reg PDATA_VALID_o = 1'b0;



wire new_sample,get_sdata;
wire ch_i_sel;
wire rst_marker;


reg [2:0] SCLK_ibuf;
reg [2:0] SDATA_ibuf;
reg [2:0] LRCLK_ibuf;

reg signed [15:0] audio_lr_tmp [0:1];
reg [1:0] pdata_valid_tmp = 2'b00;

reg [3:0] bit_i_sel;
reg [1:0] ch_rd_done;

reg [7:0] cnt_256x;




always @(posedge MCLK_i or negedge nRST_i)
  if (!nRST_i) begin
    SCLK_ibuf <= 3'b0;
    SDATA_ibuf <= 3'b0;
    LRCLK_ibuf <= 3'b0;
  end else begin
    SCLK_ibuf <= {SCLK_ibuf[1:0],SCLK_i};
    SDATA_ibuf <= {SDATA_ibuf[1:0],SDATA_i};
    LRCLK_ibuf <= {LRCLK_ibuf[1:0],LRCLK_i};
  end









assign new_sample = !LRCLK_ibuf[2] & LRCLK_ibuf[1];
assign get_sdata = !SCLK_ibuf[2] & SCLK_ibuf[1];
assign ch_i_sel = LRCLK_ibuf[1];
assign rst_marker = (!LRCLK_ibuf[2] &  LRCLK_ibuf[1]) |
                    ( LRCLK_ibuf[2] & !LRCLK_ibuf[1]);

always @(posedge MCLK_i or negedge nRST_i)
  if (!nRST_i) begin
    audio_lr_tmp[1] <= 16'h0;
    audio_lr_tmp[0] <= 16'h0;
    PDATA_LEFT_o <= 16'h0;
    PDATA_RIGHT_o <= 16'h0;
    pdata_valid_tmp <= 2'b00;
    bit_i_sel <= 4'd15;
    ch_rd_done <= 2'b00;
  end else begin
    if (get_sdata & !ch_rd_done[1]) begin
      audio_lr_tmp[ch_i_sel][bit_i_sel] <= SDATA_ibuf[1];
      if (~|bit_i_sel) begin
        ch_rd_done[1] <= ch_rd_done[0];
        ch_rd_done[0] <= 1'b1;
      end
      bit_i_sel <= bit_i_sel - 1'b1;
    end
    if (rst_marker) begin
      bit_i_sel <= 4'd0;
      ch_rd_done <= 2'b00;
    end
    if (new_sample) begin
      PDATA_LEFT_o <= audio_lr_tmp[1];
      PDATA_RIGHT_o <= audio_lr_tmp[0];
      pdata_valid_tmp <= {pdata_valid_tmp[0],1'b1};
    end
  end




always @(posedge MCLK_i or negedge nRST_i)
  if (!nRST_i) begin
    PDATA_VALID_o <= 1'b0;
    cnt_256x <= 8'h00;
  end else begin
    if (pdata_valid_tmp[1]) begin
      PDATA_VALID_o <= ~|cnt_256x;
      cnt_256x <= cnt_256x + 1'b1;
    end
  end

endmodule
module n64_sample_i2s (
  MCLK_i,
  nRST_i,


  SCLK_i,
  SDATA_i,
  LRCLK_i,


  PDATA_LEFT_o,
  PDATA_RIGHT_o,
  PDATA_VALID_o
);


input MCLK_i;
input nRST_i;

input SCLK_i;
input SDATA_i;
input LRCLK_i;

output reg signed [15:0] PDATA_LEFT_o = 16'h0;
output reg signed [15:0] PDATA_RIGHT_o = 16'h0;
output reg PDATA_VALID_o = 1'b0;



wire new_sample,get_sdata;
wire ch_i_sel;
wire rst_marker;


reg [2:0] SCLK_ibuf;
reg [2:0] SDATA_ibuf;
reg [2:0] LRCLK_ibuf;

reg signed [15:0] audio_lr_tmp [0:1];
reg [1:0] pdata_valid_tmp = 2'b00;

reg [3:0] bit_i_sel;
reg [1:0] ch_rd_done;

reg [7:0] cnt_256x;




always @(posedge MCLK_i or negedge nRST_i)
  if (!nRST_i) begin
    SCLK_ibuf <= 3'b0;
    SDATA_ibuf <= 3'b0;
    LRCLK_ibuf <= 3'b0;
  end else begin
    SCLK_ibuf <= {SCLK_ibuf[1:0],SCLK_i};
    SDATA_ibuf <= {SDATA_ibuf[1:0],SDATA_i};
    LRCLK_ibuf <= {LRCLK_ibuf[1:0],LRCLK_i};
  end









assign new_sample = !LRCLK_ibuf[2] & LRCLK_ibuf[1];
assign get_sdata = !SCLK_ibuf[2] & SCLK_ibuf[1];
assign ch_i_sel = LRCLK_ibuf[1];
assign rst_marker = (!LRCLK_ibuf[2] &  LRCLK_ibuf[1]) |
                    ( LRCLK_ibuf[2] & !LRCLK_ibuf[1]);

always @(posedge MCLK_i or negedge nRST_i)
  if (!nRST_i) begin
    audio_lr_tmp[1] <= 16'h0;
    audio_lr_tmp[0] <= 16'h0;
    PDATA_LEFT_o <= 16'h0;
    PDATA_RIGHT_o <= 16'h0;
    pdata_valid_tmp <= 2'b00;
    bit_i_sel <= 4'd15;
    ch_rd_done <= 2'b00;
  end else begin
    if (get_sdata & !ch_rd_done[1]) begin
      audio_lr_tmp[ch_i_sel][bit_i_sel] <= SDATA_ibuf[1];
      if (~|bit_i_sel) begin
        ch_rd_done[1] <= ch_rd_done[0];
        ch_rd_done[0] <= 1'b1;
      end
      bit_i_sel <= bit_i_sel - 1'b1;
    end
    if (rst_marker) begin
      bit_i_sel <= 4'd0;
      ch_rd_done <= 2'b00;
    end
    if (new_sample) begin
      PDATA_LEFT_o <= audio_lr_tmp[1];
      PDATA_RIGHT_o <= audio_lr_tmp[0];
      pdata_valid_tmp <= {pdata_valid_tmp[0],1'b1};
    end
  end




always @(posedge MCLK_i or negedge nRST_i)
  if (!nRST_i) begin
    PDATA_VALID_o <= 1'b0;
    cnt_256x <= 8'h00;
  end else begin
    if (pdata_valid_tmp[1]) begin
      PDATA_VALID_o <= ~|cnt_256x;
      cnt_256x <= cnt_256x + 1'b1;
    end
  end

endmodule