data/full_repos/permissive/447976230/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v
1: b"%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v:42: Cannot find file containing module: 'aeMB_edk32'\n   aeMB_edk32 #(.IW(ISIZ),.DW(DSIZ),.MUL(MUL),.BSF(BSF))\n   ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp2/opencores/aemb/rtl/verilog,data/full_repos/permissive/447976230/aeMB_edk32\n             data/full_repos/permissive/447976230/fpga/usrp2/opencores/aemb/rtl/verilog,data/full_repos/permissive/447976230/aeMB_edk32.v\n             data/full_repos/permissive/447976230/fpga/usrp2/opencores/aemb/rtl/verilog,data/full_repos/permissive/447976230/aeMB_edk32.sv\n             aeMB_edk32\n             aeMB_edk32.v\n             aeMB_edk32.sv\n             obj_dir/aeMB_edk32\n             obj_dir/aeMB_edk32.v\n             obj_dir/aeMB_edk32.sv\n%Error: Exiting due to 1 error(s)\n"
module aeMB_core_BE
  #(parameter ISIZ=32, parameter DSIZ=32, 
    parameter MUL=0, parameter BSF=0)
    (input sys_clk_i,
     input sys_rst_i,

     output [ISIZ-1:0] if_adr,
     input [31:0] if_dat,

     output dwb_we_o,
     output dwb_stb_o,
     output [DSIZ-1:0] dwb_adr_o,
     output [31:0] dwb_dat_o,
     input [31:0] dwb_dat_i,
     input dwb_ack_i,
     output [3:0] dwb_sel_o,
     output dwb_cyc_o,
     
     input sys_int_i, 
     input sys_exc_i);


   wire [ISIZ-1:0] iwb_adr_o;
   wire [31:0] 	   iwb_dat_i;
   wire 	   iwb_ack_i;
   wire 	   iwb_stb_o;
   
   assign dwb_cyc_o = dwb_stb_o;
   assign iwb_ack_i = 1'b1;
   assign if_adr = iwb_adr_o[ISIZ-1:0];
   assign iwb_dat_i = if_dat;



   aeMB_edk32 #(.IW(ISIZ),.DW(DSIZ),.MUL(MUL),.BSF(BSF))
     aeMB_edk32 (.sys_clk_i(sys_clk_i), 
		 .sys_rst_i(sys_rst_i),

		 .iwb_stb_o(iwb_stb_o),
		 .iwb_adr_o(iwb_adr_o[ISIZ-1:2]),
		 .iwb_ack_i(iwb_ack_i),
		 .iwb_dat_i(iwb_dat_i),

		 .dwb_wre_o(dwb_we_o),
		 .dwb_stb_o(dwb_stb_o),
		 .dwb_adr_o(dwb_adr_o[DSIZ-1:2]),
		 .dwb_ack_i(dwb_ack_i),
		 .dwb_sel_o(dwb_sel_o),
		 .dwb_dat_i(dwb_dat_i),
		 .dwb_dat_o(dwb_dat_o),
	
		 .fsl_wre_o(),
		 .fsl_tag_o(),
		 .fsl_stb_o(),
		 .fsl_dat_o(),
		 .fsl_adr_o(),
		 .fsl_dat_i(32'b0),
		 .fsl_ack_i(1'b0),
		 .sys_int_i(sys_int_i) );
   
   assign  iwb_adr_o[1:0] = 2'b0;
   assign  dwb_adr_o[1:0] = 2'b0;

endmodule
module aeMB_core_BE
  #(parameter ISIZ=32, parameter DSIZ=32, 
    parameter MUL=0, parameter BSF=0)
    (input sys_clk_i,
     input sys_rst_i,

     output [ISIZ-1:0] if_adr,
     input [31:0] if_dat,

     output dwb_we_o,
     output dwb_stb_o,
     output [DSIZ-1:0] dwb_adr_o,
     output [31:0] dwb_dat_o,
     input [31:0] dwb_dat_i,
     input dwb_ack_i,
     output [3:0] dwb_sel_o,
     output dwb_cyc_o,
     
     input sys_int_i, 
     input sys_exc_i);



   wire [ISIZ-1:0] iwb_adr_o;
   wire [31:0] 	   iwb_dat_i;
   wire 	   iwb_ack_i;
   wire 	   iwb_stb_o;
   
   assign dwb_cyc_o = dwb_stb_o;
   assign iwb_ack_i = 1'b1;
   assign if_adr = iwb_adr_o[ISIZ-1:0];
   assign iwb_dat_i = if_dat;



   aeMB_edk32 #(.IW(ISIZ),.DW(DSIZ),.MUL(MUL),.BSF(BSF))
     aeMB_edk32 (.sys_clk_i(sys_clk_i), 
		 .sys_rst_i(sys_rst_i),

		 .iwb_stb_o(iwb_stb_o),
		 .iwb_adr_o(iwb_adr_o[ISIZ-1:2]),
		 .iwb_ack_i(iwb_ack_i),
		 .iwb_dat_i(iwb_dat_i),

		 .dwb_wre_o(dwb_we_o),
		 .dwb_stb_o(dwb_stb_o),
		 .dwb_adr_o(dwb_adr_o[DSIZ-1:2]),
		 .dwb_ack_i(dwb_ack_i),
		 .dwb_sel_o(dwb_sel_o),
		 .dwb_dat_i(dwb_dat_i),
		 .dwb_dat_o(dwb_dat_o),
	
		 .fsl_wre_o(),
		 .fsl_tag_o(),
		 .fsl_stb_o(),
		 .fsl_dat_o(),
		 .fsl_adr_o(),
		 .fsl_dat_i(32'b0),
		 .fsl_ack_i(1'b0),
		 .sys_int_i(sys_int_i) );
   
   assign  iwb_adr_o[1:0] = 2'b0;
   assign  dwb_adr_o[1:0] = 2'b0;

endmodule