data/full_repos/permissive/419538859/lab8/lab8.v
data/verilator_xmls/72eaa1fa-e1a0-4b8a-9606-e8f8e9cdaa6a.xml
module 	shift(left, right, reset, unable, out, clk);
input 		left, right, reset, clk, unable;
output reg	[7:0]out;

always@(posedge clk or posedge reset)
begin
	if(reset)
		out<=8'b0000_1000;
	else if(unable)
 		out<=8'b0000_0000;
 	else if(left)
		out={out[6:0],out[7]};
	else if(right)
		out ={out[0],out[7:1]};
 	else
  		out<=out;
end
endmodule
module 	shift(left, right, reset, unable, out, clk);

input 		left, right, reset, clk, unable;
output reg	[7:0]out;

always@(posedge clk or posedge reset)
begin
	if(reset)
		out<=8'b0000_1000;
	else if(unable)
 		out<=8'b0000_0000;
 	else if(left)
		out={out[6:0],out[7]};
	else if(right)
		out ={out[0],out[7:1]};
 	else
  		out<=out;
end
endmodule