data/full_repos/permissive/43856783/j1_soc/hdl/Multiplier_V2/booth_tst.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Multiplier_V2/booth_tst.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Multiplier_V2/booth_tst.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #15 en = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Multiplier_V2/booth_tst.v:64: Unsupported: Ignoring delay on this delayed statement.\n  while(!busy)begin #1; end\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Multiplier_V2/booth_tst.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #10 en = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Multiplier_V2/booth_tst.v:66: Unsupported: Ignoring delay on this delayed statement.\n  while(busy)begin #1; end\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Multiplier_V2/booth_tst.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #20 en = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Multiplier_V2/booth_tst.v:70: Unsupported: Ignoring delay on this delayed statement.\n  while(!busy)begin #1; end\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Multiplier_V2/booth_tst.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #10 en = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Multiplier_V2/booth_tst.v:72: Unsupported: Ignoring delay on this delayed statement.\n  while(busy)begin #1; end\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Multiplier_V2/booth_tst.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #20 en = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Multiplier_V2/booth_tst.v:76: Unsupported: Ignoring delay on this delayed statement.\n  while(!busy)begin #1; end\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Multiplier_V2/booth_tst.v:77: Unsupported: Ignoring delay on this delayed statement.\n  #10 en = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Multiplier_V2/booth_tst.v:78: Unsupported: Ignoring delay on this delayed statement.\n  while(busy)begin #1; end\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Multiplier_V2/booth_tst.v:79: Unsupported: Ignoring delay on this delayed statement.\n  #20 en = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Multiplier_V2/booth_tst.v:82: Unsupported: Ignoring delay on this delayed statement.\n  while(!busy)begin #1; end\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Multiplier_V2/booth_tst.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #10 en = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Multiplier_V2/booth_tst.v:85: Unsupported: Ignoring delay on this delayed statement.\n      always #5 clk = !clk;\n             ^\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/Multiplier_V2/booth_tst.v:39: Cannot find file containing module: \'booth_mult\'\n booth_mult uut (\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43856783/j1_soc/hdl/Multiplier_V2,data/full_repos/permissive/43856783/booth_mult\n             data/full_repos/permissive/43856783/j1_soc/hdl/Multiplier_V2,data/full_repos/permissive/43856783/booth_mult.v\n             data/full_repos/permissive/43856783/j1_soc/hdl/Multiplier_V2,data/full_repos/permissive/43856783/booth_mult.sv\n             booth_mult\n             booth_mult.v\n             booth_mult.sv\n             obj_dir/booth_mult\n             obj_dir/booth_mult.v\n             obj_dir/booth_mult.sv\n%Error: Exiting due to 1 error(s), 17 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module booth_tst;


	reg clk;
	reg rst;
	reg en;
	reg [15:0] A;
	reg [15:0] B;


	wire busy;
	wire [31:0] R;


	booth_mult uut (
		.clk(clk), 
		.rst(rst), 
		.en(en), 
		.A(A), 
		.B(B), 
		.busy(busy), 
		.R(R)
	);

	initial begin

		clk = 0;
		rst = 1;
		en = 0;
		A = 0;
		B = 0;


		#100;
			rst = 0;
			A = 16'd4;
			B = 16'd4;

		#15 en = 1;
		while(!busy)begin #1; end
		#10 en = 0;
		while(busy)begin #1; end
		#20 en = 1;
			A = -16'd4;
			B = -16'd4;
		while(!busy)begin #1; end
		#10 en = 0;
		while(busy)begin #1; end
		#20 en = 1;
			A = -16'd4;
			B = 16'd4;
		while(!busy)begin #1; end
		#10 en = 0;
		while(busy)begin #1; end
		#20 en = 1;
			A = 16'd4;
			B = -16'd4;
		while(!busy)begin #1; end
		#10 en = 0;
	end
      always #5 clk = !clk;
endmodule
module booth_tst;



	reg clk;
	reg rst;
	reg en;
	reg [15:0] A;
	reg [15:0] B;


	wire busy;
	wire [31:0] R;


	booth_mult uut (
		.clk(clk), 
		.rst(rst), 
		.en(en), 
		.A(A), 
		.B(B), 
		.busy(busy), 
		.R(R)
	);

	initial begin

		clk = 0;
		rst = 1;
		en = 0;
		A = 0;
		B = 0;


		#100;
			rst = 0;
			A = 16'd4;
			B = 16'd4;

		#15 en = 1;
		while(!busy)begin #1; end
		#10 en = 0;
		while(busy)begin #1; end
		#20 en = 1;
			A = -16'd4;
			B = -16'd4;
		while(!busy)begin #1; end
		#10 en = 0;
		while(busy)begin #1; end
		#20 en = 1;
			A = -16'd4;
			B = 16'd4;
		while(!busy)begin #1; end
		#10 en = 0;
		while(busy)begin #1; end
		#20 en = 1;
			A = 16'd4;
			B = -16'd4;
		while(!busy)begin #1; end
		#10 en = 0;
	end
      always #5 clk = !clk;
endmodule