data/full_repos/permissive/46981098/mux/mux32_2to1.v
data/verilator_xmls/9d95ad3f-5e15-4f23-b046-741eeccff3d2.xml
module mux32_2to1 (
	output reg  [31:0] out,
	input [31:0] in0,
	input [31:0] in1,
	input sel
	);

  	always @(sel)
    begin
      if (sel == 0)
            out = in0;
      else
            out = in1;
    end
endmodule
module mux32_2to1 (
	output reg  [31:0] out,
	input [31:0] in0,
	input [31:0] in1,
	input sel
	);


  	always @(sel)
    begin
      if (sel == 0)
            out = in0;
      else
            out = in1;
    end
endmodule