data/full_repos/permissive/451577625/system/divider_32.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/451577625/system/divider_32.v:119: Unsupported: Ignoring delay on this delayed statement.\n  forever #10 clk = ~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/451577625/system/divider_32.v:18: Cannot find file containing module: \'adder_32\'\n adder_32 invert_dividend (.in_x (~in_dividend),\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/adder_32\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/adder_32.v\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/adder_32.sv\n             adder_32\n             adder_32.v\n             adder_32.sv\n             obj_dir/adder_32\n             obj_dir/adder_32.v\n             obj_dir/adder_32.sv\n%Error: data/full_repos/permissive/451577625/system/divider_32.v:24: Cannot find file containing module: \'adder_32\'\n adder_32 invert_divisor (.in_x (~in_divisor),\n ^~~~~~~~\n%Error: data/full_repos/permissive/451577625/system/divider_32.v:30: Cannot find file containing module: \'adder_32\'\n adder_32 invert_quotient(.in_x (~w_pos_quotient),\n ^~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module divider_32(input clk, 
	input in_reset,
	input [31:0] in_dividend,
	input [31:0] in_divisor,
	output reg [31:0] out_quotient,
	output [31:0] out_remainder);
	

	
	reg [31:0] w_pos_divisor;
	reg [31:0] w_pos_dividend;
	wire [31:0] w_inv_divisor;
	wire [31:0] w_inv_dividend;
	wire [31:0] w_neg_quotient;
	wire [31:0] w_pos_quotient;
		

	adder_32 invert_dividend (.in_x (~in_dividend),
		.in_y (32'b0),
		.in_carry (1'b1),
		.out_sum (w_inv_dividend),
		.out_carry ());
	
	adder_32 invert_divisor (.in_x (~in_divisor),
		.in_y (32'b0),
		.in_carry (1'b1),
		.out_sum (w_inv_divisor),
		.out_carry ());
	
	adder_32 invert_quotient(.in_x (~w_pos_quotient),
		.in_y (32'b0),
		.in_carry (1'b1),
		.out_sum (w_neg_quotient),
		.out_carry ());
		
	reg [31:0] r_a;
	reg [31:0] r_m;
	reg [31:0] r_q;
	reg [63:0] r_shift;
		
	assign out_remainder = r_a;
	assign w_pos_quotient = r_q;
	


	
	always @(posedge clk, posedge in_reset) begin
		if(in_reset) begin 
			r_a = 32'b0;
			r_q = w_pos_dividend;
			r_m = w_pos_divisor;
		end else begin
			r_shift = {r_a, r_q} << 1;
			r_a = r_shift[63:32];
			r_q = r_q << 1;
			r_a = r_a - r_m;
			
			if(r_a[31]) begin
				r_q[0] = 1'b0;
				r_a = r_a + r_m;
			end else begin
				r_q[0] = 1'b1;
			end
		end
	end
	
	always @(*) begin
		if (in_divisor[31] == 0) begin
			w_pos_divisor = in_divisor;
		end else begin
			w_pos_divisor = w_inv_divisor;
		end
		
		if (in_dividend[31] == 0) begin
			w_pos_dividend = in_dividend;
		end else begin
			w_pos_dividend = w_inv_dividend;
		end
		
		if(in_divisor[31] ^ in_dividend[31]) begin
			out_quotient = w_neg_quotient;
		end else begin
			out_quotient = w_pos_quotient;
		end
		
	end

endmodule
module divider_32(input clk, 
	input in_reset,
	input [31:0] in_dividend,
	input [31:0] in_divisor,
	output reg [31:0] out_quotient,
	output [31:0] out_remainder);

	

	
	reg [31:0] w_pos_divisor;
	reg [31:0] w_pos_dividend;
	wire [31:0] w_inv_divisor;
	wire [31:0] w_inv_dividend;
	wire [31:0] w_neg_quotient;
	wire [31:0] w_pos_quotient;
		

	adder_32 invert_dividend (.in_x (~in_dividend),
		.in_y (32'b0),
		.in_carry (1'b1),
		.out_sum (w_inv_dividend),
		.out_carry ());
	
	adder_32 invert_divisor (.in_x (~in_divisor),
		.in_y (32'b0),
		.in_carry (1'b1),
		.out_sum (w_inv_divisor),
		.out_carry ());
	
	adder_32 invert_quotient(.in_x (~w_pos_quotient),
		.in_y (32'b0),
		.in_carry (1'b1),
		.out_sum (w_neg_quotient),
		.out_carry ());
		
	reg [31:0] r_a;
	reg [31:0] r_m;
	reg [31:0] r_q;
	reg [63:0] r_shift;
		
	assign out_remainder = r_a;
	assign w_pos_quotient = r_q;
	


	
	always @(posedge clk, posedge in_reset) begin
		if(in_reset) begin 
			r_a = 32'b0;
			r_q = w_pos_dividend;
			r_m = w_pos_divisor;
		end else begin
			r_shift = {r_a, r_q} << 1;
			r_a = r_shift[63:32];
			r_q = r_q << 1;
			r_a = r_a - r_m;
			
			if(r_a[31]) begin
				r_q[0] = 1'b0;
				r_a = r_a + r_m;
			end else begin
				r_q[0] = 1'b1;
			end
		end
	end
	
	always @(*) begin
		if (in_divisor[31] == 0) begin
			w_pos_divisor = in_divisor;
		end else begin
			w_pos_divisor = w_inv_divisor;
		end
		
		if (in_dividend[31] == 0) begin
			w_pos_dividend = in_dividend;
		end else begin
			w_pos_dividend = w_inv_dividend;
		end
		
		if(in_divisor[31] ^ in_dividend[31]) begin
			out_quotient = w_neg_quotient;
		end else begin
			out_quotient = w_pos_quotient;
		end
		
	end

endmodule