data/full_repos/permissive/491294671/timer_input_control/div_100/div_100.v
data/verilator_xmls/7649de25-a148-44ef-90bc-e1729a2a9fc7.xml
module div_2(input clock, output reg clock_div);

  reg Q = 0;
  
  always @(posedge clock)
    begin
      Q <= ~Q;
      clock_div = Q;
    end
  always @(negedge clock)
    begin
      clock_div = Q;
    end
             
endmodule
module div_2(input clock, output reg clock_div);


  reg Q = 0;
  
  always @(posedge clock)
    begin
      Q <= ~Q;
      clock_div = Q;
    end
  always @(negedge clock)
    begin
      clock_div = Q;
    end
             
endmodule