data/full_repos/permissive/430026064/testbench.sv
1: b'%Error: data/full_repos/permissive/430026064/testbench.sv:17: Cannot find include file: clock.v\n`include "clock.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/430026064,data/full_repos/permissive/430026064/clock.v\n             data/full_repos/permissive/430026064,data/full_repos/permissive/430026064/clock.v.v\n             data/full_repos/permissive/430026064,data/full_repos/permissive/430026064/clock.v.sv\n             clock.v\n             clock.v.v\n             clock.v.sv\n             obj_dir/clock.v\n             obj_dir/clock.v.v\n             obj_dir/clock.v.sv\n%Error: data/full_repos/permissive/430026064/testbench.sv:18: Cannot find include file: top.v\n`include "top.v" \n         ^~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module testbench();
  wire clk;
  reg clk_enable;
  wire PC_enable;
  
  initial begin
    clk_enable = 1;

  end
  
  clock_generator clock_gen_obj(clk_enable, clk);
  top top_obj(clk, PC_enable);
  assign PC_enable = 1;
 
  integer i = 0;
  always@(posedge clk) begin 
  	i = i+1;
    if (i == `TOTAL_INSTRCUTIONS) begin clk_enable = 0; end
  end
  



  
  task display;
    $display("clk_enable: %0h, Initial clk: %0h", clk_enable, clk);
  endtask
  
endmodule
module testbench();

  wire clk;
  reg clk_enable;
  wire PC_enable;
  
  initial begin
    clk_enable = 1;

  end
  
  clock_generator clock_gen_obj(clk_enable, clk);
  top top_obj(clk, PC_enable);
  assign PC_enable = 1;
 
  integer i = 0;
  always@(posedge clk) begin 
  	i = i+1;
    if (i == `TOTAL_INSTRCUTIONS) begin clk_enable = 0; end
  end
  



  
  task display;
    $display("clk_enable: %0h, Initial clk: %0h", clk_enable, clk);
  endtask
  
endmodule