data/full_repos/permissive/42149584/Lab4-Part2-RAMwithHyperTerminalDisplay/ModeControllerTest.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab4-Part2-RAMwithHyperTerminalDisplay/ModeControllerTest.v:31: Unsupported: Ignoring delay on this delayed statement.\n  DataIn = 6\'d12; RAMaddressSend = 0; RAMaddressUpdate = 0; Mode = 0; WriteOrReadSend = 0; #10;\n                                                                                           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab4-Part2-RAMwithHyperTerminalDisplay/ModeControllerTest.v:32: Unsupported: Ignoring delay on this delayed statement.\n  WriteOrReadSend = 1; #10;\n                       ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab4-Part2-RAMwithHyperTerminalDisplay/ModeControllerTest.v:33: Unsupported: Ignoring delay on this delayed statement.\n  RAMaddressUpdate = 29; #10;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab4-Part2-RAMwithHyperTerminalDisplay/ModeControllerTest.v:34: Unsupported: Ignoring delay on this delayed statement.\n  Mode = 1; #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab4-Part2-RAMwithHyperTerminalDisplay/ModeControllerTest.v:35: Unsupported: Ignoring delay on this delayed statement.\n  RAMaddressUpdate = 22; #10;\n                         ^\n%Error: data/full_repos/permissive/42149584/Lab4-Part2-RAMwithHyperTerminalDisplay/ModeControllerTest.v:19: Cannot find file containing module: \'ModeController\'\n ModeController uut (\n ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/42149584/Lab4-Part2-RAMwithHyperTerminalDisplay,data/full_repos/permissive/42149584/ModeController\n             data/full_repos/permissive/42149584/Lab4-Part2-RAMwithHyperTerminalDisplay,data/full_repos/permissive/42149584/ModeController.v\n             data/full_repos/permissive/42149584/Lab4-Part2-RAMwithHyperTerminalDisplay,data/full_repos/permissive/42149584/ModeController.sv\n             ModeController\n             ModeController.v\n             ModeController.sv\n             obj_dir/ModeController\n             obj_dir/ModeController.v\n             obj_dir/ModeController.sv\n%Warning-WIDTH: data/full_repos/permissive/42149584/Lab4-Part2-RAMwithHyperTerminalDisplay/ModeControllerTest.v:31: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'hc\' generates 6 bits.\n                                                                                                                  : ... In instance ModeControllerTest\n  DataIn = 6\'d12; RAMaddressSend = 0; RAMaddressUpdate = 0; Mode = 0; WriteOrReadSend = 0; #10;\n         ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ModeControllerTest;
	reg [6:0] DataIn;
	reg [5:0] RAMaddressSend;
	reg [5:0] RAMaddressUpdate;
	reg Mode;
	reg WriteOrReadSend;
	wire [5:0] NumberOfChars;
	wire [5:0] RAMaddress;
	wire WriteOrRead;
	ModeController uut (
		.DataIn(DataIn), 
		.RAMaddressSend(RAMaddressSend), 
		.RAMaddressUpdate(RAMaddressUpdate), 
		.Mode(Mode), 
		.WriteOrReadSend(WriteOrReadSend), 
		.NumberOfChars(NumberOfChars), 
		.RAMaddress(RAMaddress), 
		.WriteOrRead(WriteOrRead)
	);

	initial begin
		DataIn = 6'd12; RAMaddressSend = 0; RAMaddressUpdate = 0; Mode = 0; WriteOrReadSend = 0; #10;
		WriteOrReadSend = 1; #10;
		RAMaddressUpdate = 29; #10;
		Mode = 1; #10;
		RAMaddressUpdate = 22; #10;
		$stop;
	end
endmodule
module ModeControllerTest;

	reg [6:0] DataIn;
	reg [5:0] RAMaddressSend;
	reg [5:0] RAMaddressUpdate;
	reg Mode;
	reg WriteOrReadSend;
	wire [5:0] NumberOfChars;
	wire [5:0] RAMaddress;
	wire WriteOrRead;
	ModeController uut (
		.DataIn(DataIn), 
		.RAMaddressSend(RAMaddressSend), 
		.RAMaddressUpdate(RAMaddressUpdate), 
		.Mode(Mode), 
		.WriteOrReadSend(WriteOrReadSend), 
		.NumberOfChars(NumberOfChars), 
		.RAMaddress(RAMaddress), 
		.WriteOrRead(WriteOrRead)
	);

	initial begin
		DataIn = 6'd12; RAMaddressSend = 0; RAMaddressUpdate = 0; Mode = 0; WriteOrReadSend = 0; #10;
		WriteOrReadSend = 1; #10;
		RAMaddressUpdate = 29; #10;
		Mode = 1; #10;
		RAMaddressUpdate = 22; #10;
		$stop;
	end
endmodule