data/full_repos/permissive/423547971/College Coursework/Advanced Computer Architecture Final Project/verilog CPU/register.v
1: b'%Error: Cannot find file containing module: Coursework/Advanced\n        ... Looked in:\n             data/full_repos/permissive/423547971/College/Coursework/Advanced\n             data/full_repos/permissive/423547971/College/Coursework/Advanced.v\n             data/full_repos/permissive/423547971/College/Coursework/Advanced.sv\n             Coursework/Advanced\n             Coursework/Advanced.v\n             Coursework/Advanced.sv\n             obj_dir/Coursework/Advanced\n             obj_dir/Coursework/Advanced.v\n             obj_dir/Coursework/Advanced.sv\n%Error: Cannot find file containing module: Computer\n%Error: Cannot find file containing module: Architecture\n%Error: Cannot find file containing module: Final\n%Error: Cannot find file containing module: Project/verilog\n%Error: Cannot find file containing module: CPU,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/College\n%Error: Cannot find file containing module: CPU/register.v\n%Error: Exiting due to 8 error(s)\n'
module register(clock, enable, data_in, data_out);
  input			clock;
  input			enable;
  input      [15:0] 	data_in;
  output reg [15:0] 	data_out;

always @(negedge clock)
  begin
    if( enable )
    begin
      data_out <= data_in;
    end
  end

endmodule
module register(clock, enable, data_in, data_out);

  input			clock;
  input			enable;
  input      [15:0] 	data_in;
  output reg [15:0] 	data_out;

always @(negedge clock)
  begin
    if( enable )
    begin
      data_out <= data_in;
    end
  end

endmodule