data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ippcsge/core/ippcsge_core.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ippcsge/core/ippcsge_core.v:544: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n     .do    (ram_rdat)\n      ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ippcsge/core/ippcsge_core.v:544: syntax error, unexpected '(', expecting ')'\n     .do    (ram_rdat)\n             ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module ippcsge_core
    (

     rxclk,
     rxrst_,
     
     tbi_rxdat,

     gmii_rxdat,
     gmii_rxdv,
     gmii_rxer,

     txclk,
     txrst_,

     gmii_txdat,
     gmii_txen,
     gmii_txer,

     tbi_txdat,
     

     linkdown,
     

     sysclk,
     sysrst_,
     upact,     
     upen,
     uprs,
     upws,
     upa,
     updi,
     updo,
     uprdy
     );








input           rxclk;
input           rxrst_;

input [9:0]     tbi_rxdat;

output [7:0]    gmii_rxdat;
output          gmii_rxdv;
output          gmii_rxer;

input           txclk;
input           txrst_;

input [7:0]     gmii_txdat;
input           gmii_txen;
input           gmii_txer;

output [9:0]    tbi_txdat;


output          linkdown;
         

input           sysclk;
input           sysrst_;

input           upact;
input           upen;
input           uprs;
input           upws;
input [5:0]     upa;
input [15:0]    updi;
output [15:0]   updo;
output          uprdy;








wire                sytx_upen;
wire   [15:0]       sytx_updo;
wire                sytx_uprdy;


wire                tx_upen;
wire   [15:0]       tx_updo;
wire                tx_uprdy;


wire                sk_upen;
wire   [15:0]       sk_updo;
wire                sk_uprdy;


wire                el_upen;
wire   [15:0]       el_updo;
wire                el_uprdy;


wire                syrx_upen;
wire   [15:0]       syrx_updo;
wire                syrx_uprdy;

assign  sytx_updo   = (tx_updo  |
                       sk_updo  |
                       el_updo  );

wire    sytx_uprdy0;
fflopx #(2) iffsytxuprdy (sysclk, sysrst_, {sytx_upen & (uprs | upws), sytx_uprdy0}, {sytx_uprdy0, sytx_uprdy});
                          
assign updo [15:0]  = sytx_updo  | syrx_updo;
assign uprdy        = sytx_uprdy | syrx_uprdy;

assign sytx_upen    = upen & (upa [5:4]  == 2'b11);
assign syrx_upen    = upen & (~sytx_upen );

assign tx_upen      = sytx_upen & (upa [5:0] == 6'h3F);
assign sk_upen      = sytx_upen & (upa [5:0] == 6'h3E);
assign el_upen      = sytx_upen & (upa [5:0] == 6'h3D);



wire                elff_wrerr;
wire                elff_rderr;
wire                elff_flush;
wire [3:0]          elff_thsh;


pconfigx #(5, {1'b0, 4'd5}) elasticfifo_control 
    (
     .clk           (sysclk),
     .rst_          (sysrst_),
     .upen          (el_upen),
     .upws          (upws),
     .updi          (updi[4:0]),
     .out           ({elff_flush, elff_thsh}),
     .updo          (el_updo[4:0])
     );

assign              el_updo [15:5] = 11'b0;

stickyx #(2) elasticfifo_stky
    (
     .clk       (sysclk),
     .rst_      (sysrst_),
     .upactive  (upact),
     .alarm     ({elff_rderr, elff_wrerr}),
     .upen      (sk_upen),
     .upws      (upws),
     .updi      (updi[1:0]),
     .updo      (sk_updo [1:0]),
     .lalarm    ()
     );

assign              sk_updo [15:2] = 14'b0;


wire                rx_upen;
wire                rx_uprs;
wire                rx_upws;
wire [5:0]          rx_upa;
wire   [15:0]       rx_updi;
wire   [15:0]       rx_updo;
wire                rx_uprdy;


ippcsge_cpuadap #(6, 16) icpuadap
    (

     .syclk     (sysclk),
     .syrst_    (sysrst_),
     .syupen    (syrx_upen),
     .syupa     (upa),
     .syuprs    (uprs),
     .syupws    (upws),
     .syupdi    (updi),
     .syupdo    (syrx_updo),
     .syuprdy   (syrx_uprdy),


     .rxclk     (rxclk),
     .rxrst_    (rxrst_),
     .rxupen    (rx_upen),
     .rxupa     (rx_upa),
     .rxuprs    (rx_uprs),
     .rxupws    (rx_upws),
     .rxupdi    (rx_updi),
     .rxupdo    (rx_updo),
     .rxuprdy   (rx_uprdy)
     );


wire                receiving;
wire   [15:0]       tx_cfdata;
wire   [1:0]        xmit;

wire [7:0]          gmii_redat;
wire                gmii_redv;
wire                gmii_reer;

ippcsge_pcs_rx   ipcs_rx
    (
     .rxclk     (rxclk),
     .rst_      (rxrst_),

     .rxdi      (tbi_rxdat),
     .rxdo      (gmii_redat),
     .rxdvl     (gmii_redv),
     .rxerr     (gmii_reer),


     .receiving (receiving),
     .tx_cfdata (tx_cfdata),
     .xmit      (xmit),


     .linkdown  (linkdown),


     .pact      (upact),
     .pen       (rx_upen),
     .prs       (rx_uprs),
     .pws       (rx_upws),
     .pa        (rx_upa [5:0]),
     .pdi       (rx_updi [15:0]),
     .pdo       (rx_updo [15:0]),
     .prdy      (rx_uprdy)
     );


`ifndef RTL_OFF_PCSRX_ELASTIC_FIFO

ippcsge_elasticfifo #(9,4,16) ielasticfifo
    (

     .inclk         (rxclk),
     .inrst_        (rxrst_),
     
     .indata        ({gmii_reer, gmii_redat}),
     .invld         (gmii_redv),


     .outclk        (txclk),
     .outrst_       (txrst_),
     
     .outdata       ({gmii_rxer, gmii_rxdat}),
     .outvld        (gmii_rxdv),
     

     .wrerr         (elff_wrerr),
     .rderr         (elff_rderr),

     .upact         (upact),
     .upflush       (elff_flush),
     .upthsh        (elff_thsh)
     );

`else
assign              {gmii_rxer, gmii_rxdat, gmii_rxdv} = {gmii_reer, gmii_redat, gmii_redv};

`endif


ippcsge_pcs_tx   ipcs_tx
    (
     .sclk125   (txclk),
     .rst_      (txrst_),

     .txen      (gmii_txen),
     .txerr     (gmii_txer),


     .receiving (receiving),
     .xmit      (xmit),
     .tx_cfdata (tx_cfdata),

     .col       (),
     .crs       (),
     .txdi      (gmii_txdat),
     .txdo      (tbi_txdat),


     .sysclk    (sysclk),
     .sysrst_   (sysrst_),
     .pact      (upact),
     .pen       (tx_upen),
     .pws       (upws),
     .prs       (uprs),
     .pdi       (updi [15:0]),
     .pdo       (tx_updo [15:0]),
     .prdy      (tx_uprdy)
     );

endmodule
module ippcsge_core
    (

     rxclk,
     rxrst_,
     
     tbi_rxdat,

     gmii_rxdat,
     gmii_rxdv,
     gmii_rxer,

     txclk,
     txrst_,

     gmii_txdat,
     gmii_txen,
     gmii_txer,

     tbi_txdat,
     

     linkdown,
     

     sysclk,
     sysrst_,
     upact,     
     upen,
     uprs,
     upws,
     upa,
     updi,
     updo,
     uprdy
     );









input           rxclk;
input           rxrst_;

input [9:0]     tbi_rxdat;

output [7:0]    gmii_rxdat;
output          gmii_rxdv;
output          gmii_rxer;

input           txclk;
input           txrst_;

input [7:0]     gmii_txdat;
input           gmii_txen;
input           gmii_txer;

output [9:0]    tbi_txdat;


output          linkdown;
         

input           sysclk;
input           sysrst_;

input           upact;
input           upen;
input           uprs;
input           upws;
input [5:0]     upa;
input [15:0]    updi;
output [15:0]   updo;
output          uprdy;








wire                sytx_upen;
wire   [15:0]       sytx_updo;
wire                sytx_uprdy;


wire                tx_upen;
wire   [15:0]       tx_updo;
wire                tx_uprdy;


wire                sk_upen;
wire   [15:0]       sk_updo;
wire                sk_uprdy;


wire                el_upen;
wire   [15:0]       el_updo;
wire                el_uprdy;


wire                syrx_upen;
wire   [15:0]       syrx_updo;
wire                syrx_uprdy;

assign  sytx_updo   = (tx_updo  |
                       sk_updo  |
                       el_updo  );

wire    sytx_uprdy0;
fflopx #(2) iffsytxuprdy (sysclk, sysrst_, {sytx_upen & (uprs | upws), sytx_uprdy0}, {sytx_uprdy0, sytx_uprdy});
                          
assign updo [15:0]  = sytx_updo  | syrx_updo;
assign uprdy        = sytx_uprdy | syrx_uprdy;

assign sytx_upen    = upen & (upa [5:4]  == 2'b11);
assign syrx_upen    = upen & (~sytx_upen );

assign tx_upen      = sytx_upen & (upa [5:0] == 6'h3F);
assign sk_upen      = sytx_upen & (upa [5:0] == 6'h3E);
assign el_upen      = sytx_upen & (upa [5:0] == 6'h3D);



wire                elff_wrerr;
wire                elff_rderr;
wire                elff_flush;
wire [3:0]          elff_thsh;


pconfigx #(5, {1'b0, 4'd5}) elasticfifo_control 
    (
     .clk           (sysclk),
     .rst_          (sysrst_),
     .upen          (el_upen),
     .upws          (upws),
     .updi          (updi[4:0]),
     .out           ({elff_flush, elff_thsh}),
     .updo          (el_updo[4:0])
     );

assign              el_updo [15:5] = 11'b0;

stickyx #(2) elasticfifo_stky
    (
     .clk       (sysclk),
     .rst_      (sysrst_),
     .upactive  (upact),
     .alarm     ({elff_rderr, elff_wrerr}),
     .upen      (sk_upen),
     .upws      (upws),
     .updi      (updi[1:0]),
     .updo      (sk_updo [1:0]),
     .lalarm    ()
     );

assign              sk_updo [15:2] = 14'b0;


wire                rx_upen;
wire                rx_uprs;
wire                rx_upws;
wire [5:0]          rx_upa;
wire   [15:0]       rx_updi;
wire   [15:0]       rx_updo;
wire                rx_uprdy;


ippcsge_cpuadap #(6, 16) icpuadap
    (

     .syclk     (sysclk),
     .syrst_    (sysrst_),
     .syupen    (syrx_upen),
     .syupa     (upa),
     .syuprs    (uprs),
     .syupws    (upws),
     .syupdi    (updi),
     .syupdo    (syrx_updo),
     .syuprdy   (syrx_uprdy),


     .rxclk     (rxclk),
     .rxrst_    (rxrst_),
     .rxupen    (rx_upen),
     .rxupa     (rx_upa),
     .rxuprs    (rx_uprs),
     .rxupws    (rx_upws),
     .rxupdi    (rx_updi),
     .rxupdo    (rx_updo),
     .rxuprdy   (rx_uprdy)
     );


wire                receiving;
wire   [15:0]       tx_cfdata;
wire   [1:0]        xmit;

wire [7:0]          gmii_redat;
wire                gmii_redv;
wire                gmii_reer;

ippcsge_pcs_rx   ipcs_rx
    (
     .rxclk     (rxclk),
     .rst_      (rxrst_),

     .rxdi      (tbi_rxdat),
     .rxdo      (gmii_redat),
     .rxdvl     (gmii_redv),
     .rxerr     (gmii_reer),


     .receiving (receiving),
     .tx_cfdata (tx_cfdata),
     .xmit      (xmit),


     .linkdown  (linkdown),


     .pact      (upact),
     .pen       (rx_upen),
     .prs       (rx_uprs),
     .pws       (rx_upws),
     .pa        (rx_upa [5:0]),
     .pdi       (rx_updi [15:0]),
     .pdo       (rx_updo [15:0]),
     .prdy      (rx_uprdy)
     );


`ifndef RTL_OFF_PCSRX_ELASTIC_FIFO

ippcsge_elasticfifo #(9,4,16) ielasticfifo
    (

     .inclk         (rxclk),
     .inrst_        (rxrst_),
     
     .indata        ({gmii_reer, gmii_redat}),
     .invld         (gmii_redv),


     .outclk        (txclk),
     .outrst_       (txrst_),
     
     .outdata       ({gmii_rxer, gmii_rxdat}),
     .outvld        (gmii_rxdv),
     

     .wrerr         (elff_wrerr),
     .rderr         (elff_rderr),

     .upact         (upact),
     .upflush       (elff_flush),
     .upthsh        (elff_thsh)
     );

`else
assign              {gmii_rxer, gmii_rxdat, gmii_rxdv} = {gmii_reer, gmii_redat, gmii_redv};

`endif


ippcsge_pcs_tx   ipcs_tx
    (
     .sclk125   (txclk),
     .rst_      (txrst_),

     .txen      (gmii_txen),
     .txerr     (gmii_txer),


     .receiving (receiving),
     .xmit      (xmit),
     .tx_cfdata (tx_cfdata),

     .col       (),
     .crs       (),
     .txdi      (gmii_txdat),
     .txdo      (tbi_txdat),


     .sysclk    (sysclk),
     .sysrst_   (sysrst_),
     .pact      (upact),
     .pen       (tx_upen),
     .pws       (upws),
     .prs       (uprs),
     .pdi       (updi [15:0]),
     .pdo       (tx_updo [15:0]),
     .prdy      (tx_uprdy)
     );

endmodule