data/full_repos/permissive/48695884/test_mandelbrot.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/48695884/test_mandelbrot.v:14: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = !clk;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/48695884/test_mandelbrot.v:22: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n%Warning-STMTDLY: data/full_repos/permissive/48695884/test_mandelbrot.v:20: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/48695884/test_mandelbrot.v:26: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n%Warning-STMTDLY: data/full_repos/permissive/48695884/test_mandelbrot.v:30: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n%Error: data/full_repos/permissive/48695884/test_mandelbrot.v:11: Cannot find file containing module: \'mandelbrot\'\nmandelbrot m(clk, reset, c_real, c_imag, overflow, out_real, out_imag);\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/48695884,data/full_repos/permissive/48695884/mandelbrot\n             data/full_repos/permissive/48695884,data/full_repos/permissive/48695884/mandelbrot.v\n             data/full_repos/permissive/48695884,data/full_repos/permissive/48695884/mandelbrot.sv\n             mandelbrot\n             mandelbrot.v\n             mandelbrot.sv\n             obj_dir/mandelbrot\n             obj_dir/mandelbrot.v\n             obj_dir/mandelbrot.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_mandelbrot;

reg                clk;
reg					 reset;
reg  signed [31:0] c_real;
reg  signed [31:0] c_imag;
wire               overflow;
wire signed [31:0] out_real;
wire signed [31:0] out_imag;

mandelbrot m(clk, reset, c_real, c_imag, overflow, out_real, out_imag);

always begin
	#1 clk = !clk;
end

initial begin
	clk = 0;
	reset = 1;
	#1
	
	#2
	c_real  = 32'h800000;
	c_imag  = 32'h800000;
	
	#2
	c_real = 32'hb851e;
	c_imag = 32'h1a3d70;
	
	#2
	c_real  = 32'h800000;
	c_imag  = 32'h800000;
end
	
endmodule
module test_mandelbrot;


reg                clk;
reg					 reset;
reg  signed [31:0] c_real;
reg  signed [31:0] c_imag;
wire               overflow;
wire signed [31:0] out_real;
wire signed [31:0] out_imag;

mandelbrot m(clk, reset, c_real, c_imag, overflow, out_real, out_imag);

always begin
	#1 clk = !clk;
end

initial begin
	clk = 0;
	reset = 1;
	#1
	
	#2
	c_real  = 32'h800000;
	c_imag  = 32'h800000;
	
	#2
	c_real = 32'hb851e;
	c_imag = 32'h1a3d70;
	
	#2
	c_real  = 32'h800000;
	c_imag  = 32'h800000;
end
	
endmodule