data/full_repos/permissive/514437299/digital/rtl/servant.v
1: b"%Error: data/full_repos/permissive/514437299/digital/rtl/servant.v:220: Cannot find file containing module: 'serv_rf_top'\n   serv_rf_top\n   ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514437299/digital/rtl,data/full_repos/permissive/514437299/serv_rf_top\n             data/full_repos/permissive/514437299/digital/rtl,data/full_repos/permissive/514437299/serv_rf_top.v\n             data/full_repos/permissive/514437299/digital/rtl,data/full_repos/permissive/514437299/serv_rf_top.sv\n             serv_rf_top\n             serv_rf_top.v\n             serv_rf_top.sv\n             obj_dir/serv_rf_top\n             obj_dir/serv_rf_top.v\n             obj_dir/serv_rf_top.sv\n%Error: Exiting due to 1 error(s)\n"
module servant_mux
  (
   input wire         clk,
   input wire         rst_n,
   input wire [31:0]  i_wb_cpu_adr,
   input wire [31:0]  i_wb_cpu_dat,
   input wire [3:0]   i_wb_cpu_sel,
   input wire         i_wb_cpu_we,
   input wire         i_wb_cpu_cyc,
   output wire [31:0] o_wb_cpu_rdt,
   output reg         o_wb_cpu_ack,

   output wire [31:0] o_wb_mem_adr,
   output wire [31:0] o_wb_mem_dat,
   output wire [3:0]  o_wb_mem_sel,
   output wire        o_wb_mem_we,
   output wire        o_wb_mem_cyc,
   input wire [31:0]  i_wb_mem_rdt,

   output wire [1:0]  o_wb_gpio_dat,
   output wire        o_wb_gpio_we,
   output wire        o_wb_gpio_cyc,
   input wire  [1:0]  i_wb_gpio_rdt);

   wire [1:0]     s = i_wb_cpu_adr[31:30];

   assign o_wb_cpu_rdt = s[0] ? {30'd0,i_wb_gpio_rdt} : i_wb_mem_rdt;
   always @(posedge clk or negedge rst_n) begin
      if (!rst_n)
        o_wb_cpu_ack <= 1'b0;
      else begin
        o_wb_cpu_ack <= 1'b0;
        if (i_wb_cpu_cyc & !o_wb_cpu_ack)
          o_wb_cpu_ack <= 1'b1;
      end
   end

   assign o_wb_mem_adr = i_wb_cpu_adr;
   assign o_wb_mem_dat = i_wb_cpu_dat;
   assign o_wb_mem_sel = i_wb_cpu_sel;
   assign o_wb_mem_we  = i_wb_cpu_we;
   assign o_wb_mem_cyc = i_wb_cpu_cyc & (s == 2'b00);

   assign o_wb_gpio_dat = i_wb_cpu_dat[1:0];
   assign o_wb_gpio_we  = i_wb_cpu_we;
   assign o_wb_gpio_cyc = i_wb_cpu_cyc & (s == 2'b01);

endmodule
module servant_mux
  (
   input wire         clk,
   input wire         rst_n,
   input wire [31:0]  i_wb_cpu_adr,
   input wire [31:0]  i_wb_cpu_dat,
   input wire [3:0]   i_wb_cpu_sel,
   input wire         i_wb_cpu_we,
   input wire         i_wb_cpu_cyc,
   output wire [31:0] o_wb_cpu_rdt,
   output reg         o_wb_cpu_ack,

   output wire [31:0] o_wb_mem_adr,
   output wire [31:0] o_wb_mem_dat,
   output wire [3:0]  o_wb_mem_sel,
   output wire        o_wb_mem_we,
   output wire        o_wb_mem_cyc,
   input wire [31:0]  i_wb_mem_rdt,

   output wire [1:0]  o_wb_gpio_dat,
   output wire        o_wb_gpio_we,
   output wire        o_wb_gpio_cyc,
   input wire  [1:0]  i_wb_gpio_rdt);


   wire [1:0]     s = i_wb_cpu_adr[31:30];

   assign o_wb_cpu_rdt = s[0] ? {30'd0,i_wb_gpio_rdt} : i_wb_mem_rdt;
   always @(posedge clk or negedge rst_n) begin
      if (!rst_n)
        o_wb_cpu_ack <= 1'b0;
      else begin
        o_wb_cpu_ack <= 1'b0;
        if (i_wb_cpu_cyc & !o_wb_cpu_ack)
          o_wb_cpu_ack <= 1'b1;
      end
   end

   assign o_wb_mem_adr = i_wb_cpu_adr;
   assign o_wb_mem_dat = i_wb_cpu_dat;
   assign o_wb_mem_sel = i_wb_cpu_sel;
   assign o_wb_mem_we  = i_wb_cpu_we;
   assign o_wb_mem_cyc = i_wb_cpu_cyc & (s == 2'b00);

   assign o_wb_gpio_dat = i_wb_cpu_dat[1:0];
   assign o_wb_gpio_we  = i_wb_cpu_we;
   assign o_wb_gpio_cyc = i_wb_cpu_cyc & (s == 2'b01);

endmodule