data/full_repos/permissive/447976230/fpga/usrp2/control_lib/reset_sync.v
data/verilator_xmls/b389e331-f85d-44f7-870c-8c3fe2ac578e.xml
module reset_sync
  (input clk,
   input reset_in,
   output reg reset_out);

   reg 	      reset_int;

   always @(posedge clk or posedge reset_in)
     if(reset_in)
       {reset_out,reset_int} <= 2'b11;
     else
       {reset_out,reset_int} <= {reset_int,1'b0};
   
endmodule
module reset_sync
  (input clk,
   input reset_in,
   output reg reset_out);


   reg 	      reset_int;

   always @(posedge clk or posedge reset_in)
     if(reset_in)
       {reset_out,reset_int} <= 2'b11;
     else
       {reset_out,reset_int} <= {reset_int,1'b0};
   
endmodule