data/full_repos/permissive/456468799/Verilog/Sequencer.v
data/verilator_xmls/fd1139bc-bf3d-489b-8073-cdacee3498c3.xml
module Sequencer(input RESET,
                 input M1_n,
                 input IORQ_n,
                 input RD_n,
                 input CLK_n,
                 output reg[7 : 0] S);
  reg u204;
  always
    @(posedge CLK_n)
      begin
        u204 <= (RESET & ~M1_n & ~IORQ_n & ~RD_n) | (S[6] & ~S[7]);
        S[0] <= ~S[7];
        S[1] <= S[0] | u204;
        S[2] <= S[1] | u204;
        S[3] <= S[2] | u204;
        S[4] <= S[3] | u204;
        S[5] <= S[4] | u204;
        S[6] <= S[5] | u204;
        S[7] <= S[6];
      end
endmodule
module Sequencer(input RESET,
                 input M1_n,
                 input IORQ_n,
                 input RD_n,
                 input CLK_n,
                 output reg[7 : 0] S);

  reg u204;
  always
    @(posedge CLK_n)
      begin
        u204 <= (RESET & ~M1_n & ~IORQ_n & ~RD_n) | (S[6] & ~S[7]);
        S[0] <= ~S[7];
        S[1] <= S[0] | u204;
        S[2] <= S[1] | u204;
        S[3] <= S[2] | u204;
        S[4] <= S[3] | u204;
        S[5] <= S[4] | u204;
        S[6] <= S[5] | u204;
        S[7] <= S[6];
      end
endmodule