data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv
1: b'%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:14: Cannot find include file: prim_assert.sv\n`include "prim_assert.sv" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig,data/full_repos/permissive/419809304/prim_assert.sv\n             data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig,data/full_repos/permissive/419809304/prim_assert.sv.v\n             data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig,data/full_repos/permissive/419809304/prim_assert.sv.sv\n             prim_assert.sv\n             prim_assert.sv.v\n             prim_assert.sv.sv\n             obj_dir/prim_assert.sv\n             obj_dir/prim_assert.sv.v\n             obj_dir/prim_assert.sv.sv\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:15: Cannot find include file: dv_fcov_macros.svh\n`include "dv_fcov_macros.svh" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:25: syntax error, unexpected ::, expecting \')\' or \',\'\n  input  ibex_pkg::wb_instr_type_e instr_type_wb_i,\n                 ^~\n                                                                                                : ... Perhaps \'ibex_pkg\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:27: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input  logic                     instr_is_compressed_id_i,\n  ^~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:28: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input  logic                     instr_perf_count_id_i,\n  ^~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:30: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output logic                     ready_wb_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:31: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output logic                     rf_write_wb_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:32: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output logic                     outstanding_load_wb_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:33: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output logic                     outstanding_store_wb_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:34: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output logic [31:0]              pc_wb_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:35: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output logic                     perf_instr_ret_wb_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:36: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output logic                     perf_instr_ret_compressed_wb_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:37: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output logic                     perf_instr_ret_wb_spec_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:38: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output logic                     perf_instr_ret_compressed_wb_spec_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:40: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input  logic [4:0]               rf_waddr_id_i,\n  ^~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:41: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input  logic [31:0]              rf_wdata_id_i,\n  ^~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:42: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input  logic                     rf_we_id_i,\n  ^~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:44: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input  logic [31:0]              rf_wdata_lsu_i,\n  ^~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:45: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input  logic                     rf_we_lsu_i,\n  ^~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:47: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output logic [31:0]              rf_wdata_fwd_wb_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:49: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output logic [4:0]               rf_waddr_wb_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:50: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output logic [31:0]              rf_wdata_wb_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:51: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output logic                     rf_we_wb_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:53: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input logic                      lsu_resp_valid_i,\n  ^~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:54: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input logic                      lsu_resp_err_i,\n  ^~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:56: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output logic                     instr_done_wb_o\n  ^~~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:66: syntax error, unexpected if\n  if (WritebackStage) begin : g_writeback_stage\n  ^~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:77: syntax error, unexpected IDENTIFIER\n    wb_instr_type_e wb_instr_type_q;\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:83: syntax error, unexpected assign\n    assign wb_valid_d = (en_wb_i & ready_wb_o) | (wb_valid_q & ~wb_done);\n    ^~~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:186: syntax error, unexpected IDENTIFIER\n    wb_instr_type_e unused_instr_type_wb;\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:189: syntax error, unexpected assign\n    assign unused_clk            = clk_i;\n    ^~~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:211: Define or directive not defined: \'`DV_FCOV_SIGNAL_GEN_IF\'\n  `DV_FCOV_SIGNAL_GEN_IF(logic, wb_valid, g_writeback_stage.wb_valid_q, WritebackStage)\n  ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_wb_stage.sv:213: Define or directive not defined: \'`ASSERT\'\n  `ASSERT(RFWriteFromOneSourceOnly, $onehot0(rf_wdata_wb_mux_we))\n  ^~~~~~~\n%Error: Exiting due to 33 error(s)\n'
module ibex_wb_stage #(
  parameter bit ResetAll       = 1'b0,
  parameter bit WritebackStage = 1'b0
) (
  input  logic                     clk_i,
  input  logic                     rst_ni,

  input  logic                     en_wb_i,
  input  ibex_pkg::wb_instr_type_e instr_type_wb_i,
  input  logic [31:0]              pc_id_i,
  input  logic                     instr_is_compressed_id_i,
  input  logic                     instr_perf_count_id_i,

  output logic                     ready_wb_o,
  output logic                     rf_write_wb_o,
  output logic                     outstanding_load_wb_o,
  output logic                     outstanding_store_wb_o,
  output logic [31:0]              pc_wb_o,
  output logic                     perf_instr_ret_wb_o,
  output logic                     perf_instr_ret_compressed_wb_o,
  output logic                     perf_instr_ret_wb_spec_o,
  output logic                     perf_instr_ret_compressed_wb_spec_o,

  input  logic [4:0]               rf_waddr_id_i,
  input  logic [31:0]              rf_wdata_id_i,
  input  logic                     rf_we_id_i,

  input  logic [31:0]              rf_wdata_lsu_i,
  input  logic                     rf_we_lsu_i,

  output logic [31:0]              rf_wdata_fwd_wb_o,

  output logic [4:0]               rf_waddr_wb_o,
  output logic [31:0]              rf_wdata_wb_o,
  output logic                     rf_we_wb_o,

  input logic                      lsu_resp_valid_i,
  input logic                      lsu_resp_err_i,

  output logic                     instr_done_wb_o
);

  import ibex_pkg::*;



  logic [31:0] rf_wdata_wb_mux    [2];
  logic [1:0]  rf_wdata_wb_mux_we;

  if (WritebackStage) begin : g_writeback_stage
    logic [31:0]    rf_wdata_wb_q;
    logic           rf_we_wb_q;
    logic [4:0]     rf_waddr_wb_q;

    logic           wb_done;

    logic           wb_valid_q;
    logic [31:0]    wb_pc_q;
    logic           wb_compressed_q;
    logic           wb_count_q;
    wb_instr_type_e wb_instr_type_q;

    logic           wb_valid_d;



    assign wb_valid_d = (en_wb_i & ready_wb_o) | (wb_valid_q & ~wb_done);




    assign wb_done = (wb_instr_type_q == WB_INSTR_OTHER) | lsu_resp_valid_i;

    always_ff @(posedge clk_i or negedge rst_ni) begin
      if (!rst_ni) begin
        wb_valid_q <= 1'b0;
      end else begin
        wb_valid_q <= wb_valid_d;
      end
    end

    if (ResetAll) begin : g_wb_regs_ra
      always_ff @(posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
          rf_we_wb_q      <= '0;
          rf_waddr_wb_q   <= '0;
          rf_wdata_wb_q   <= '0;
          wb_instr_type_q <= wb_instr_type_e'(0);
          wb_pc_q         <= '0;
          wb_compressed_q <= '0;
          wb_count_q      <= '0;
        end else if (en_wb_i) begin
          rf_we_wb_q      <= rf_we_id_i;
          rf_waddr_wb_q   <= rf_waddr_id_i;
          rf_wdata_wb_q   <= rf_wdata_id_i;
          wb_instr_type_q <= instr_type_wb_i;
          wb_pc_q         <= pc_id_i;
          wb_compressed_q <= instr_is_compressed_id_i;
          wb_count_q      <= instr_perf_count_id_i;
        end
      end
    end else begin : g_wb_regs_nr
      always_ff @(posedge clk_i) begin
        if (en_wb_i) begin
          rf_we_wb_q      <= rf_we_id_i;
          rf_waddr_wb_q   <= rf_waddr_id_i;
          rf_wdata_wb_q   <= rf_wdata_id_i;
          wb_instr_type_q <= instr_type_wb_i;
          wb_pc_q         <= pc_id_i;
          wb_compressed_q <= instr_is_compressed_id_i;
          wb_count_q      <= instr_perf_count_id_i;
        end
      end
    end

    assign rf_waddr_wb_o         = rf_waddr_wb_q;
    assign rf_wdata_wb_mux[0]    = rf_wdata_wb_q;
    assign rf_wdata_wb_mux_we[0] = rf_we_wb_q & wb_valid_q;

    assign ready_wb_o = ~wb_valid_q | wb_done;



    assign rf_write_wb_o = wb_valid_q & (rf_we_wb_q | (wb_instr_type_q == WB_INSTR_LOAD));

    assign outstanding_load_wb_o  = wb_valid_q & (wb_instr_type_q == WB_INSTR_LOAD);
    assign outstanding_store_wb_o = wb_valid_q & (wb_instr_type_q == WB_INSTR_STORE);

    assign pc_wb_o = wb_pc_q;

    assign instr_done_wb_o = wb_valid_q & wb_done;





    assign perf_instr_ret_wb_spec_o            = wb_count_q;
    assign perf_instr_ret_compressed_wb_spec_o = perf_instr_ret_wb_spec_o & wb_compressed_q;
    assign perf_instr_ret_wb_o                 = instr_done_wb_o & wb_count_q &
                                                 ~(lsu_resp_valid_i & lsu_resp_err_i);
    assign perf_instr_ret_compressed_wb_o      = perf_instr_ret_wb_o & wb_compressed_q;




    assign rf_wdata_fwd_wb_o = rf_wdata_wb_q;
  end else begin : g_bypass_wb

    assign rf_waddr_wb_o         = rf_waddr_id_i;
    assign rf_wdata_wb_mux[0]    = rf_wdata_id_i;
    assign rf_wdata_wb_mux_we[0] = rf_we_id_i;




    assign perf_instr_ret_wb_spec_o            = 1'b0;
    assign perf_instr_ret_compressed_wb_spec_o = 1'b0;
    assign perf_instr_ret_wb_o                 = instr_perf_count_id_i & en_wb_i &
                                                 ~(lsu_resp_valid_i & lsu_resp_err_i);
    assign perf_instr_ret_compressed_wb_o      = perf_instr_ret_wb_o & instr_is_compressed_id_i;


    assign ready_wb_o    = 1'b1;




    logic           unused_clk;
    logic           unused_rst;
    wb_instr_type_e unused_instr_type_wb;
    logic [31:0]    unused_pc_id;

    assign unused_clk            = clk_i;
    assign unused_rst            = rst_ni;
    assign unused_instr_type_wb  = instr_type_wb_i;
    assign unused_pc_id          = pc_id_i;

    assign outstanding_load_wb_o  = 1'b0;
    assign outstanding_store_wb_o = 1'b0;
    assign pc_wb_o                = '0;
    assign rf_write_wb_o          = 1'b0;
    assign rf_wdata_fwd_wb_o      = 32'b0;
    assign instr_done_wb_o        = 1'b0;
  end

  assign rf_wdata_wb_mux[1]    = rf_wdata_lsu_i;
  assign rf_wdata_wb_mux_we[1] = rf_we_lsu_i;



  assign rf_wdata_wb_o = ({32{rf_wdata_wb_mux_we[0]}} & rf_wdata_wb_mux[0]) |
                         ({32{rf_wdata_wb_mux_we[1]}} & rf_wdata_wb_mux[1]);
  assign rf_we_wb_o    = |rf_wdata_wb_mux_we;

  `DV_FCOV_SIGNAL_GEN_IF(logic, wb_valid, g_writeback_stage.wb_valid_q, WritebackStage)

  `ASSERT(RFWriteFromOneSourceOnly, $onehot0(rf_wdata_wb_mux_we))
endmodule
module ibex_wb_stage #(
  parameter bit ResetAll       = 1'b0,
  parameter bit WritebackStage = 1'b0
) (
  input  logic                     clk_i,
  input  logic                     rst_ni,

  input  logic                     en_wb_i,
  input  ibex_pkg::wb_instr_type_e instr_type_wb_i,
  input  logic [31:0]              pc_id_i,
  input  logic                     instr_is_compressed_id_i,
  input  logic                     instr_perf_count_id_i,

  output logic                     ready_wb_o,
  output logic                     rf_write_wb_o,
  output logic                     outstanding_load_wb_o,
  output logic                     outstanding_store_wb_o,
  output logic [31:0]              pc_wb_o,
  output logic                     perf_instr_ret_wb_o,
  output logic                     perf_instr_ret_compressed_wb_o,
  output logic                     perf_instr_ret_wb_spec_o,
  output logic                     perf_instr_ret_compressed_wb_spec_o,

  input  logic [4:0]               rf_waddr_id_i,
  input  logic [31:0]              rf_wdata_id_i,
  input  logic                     rf_we_id_i,

  input  logic [31:0]              rf_wdata_lsu_i,
  input  logic                     rf_we_lsu_i,

  output logic [31:0]              rf_wdata_fwd_wb_o,

  output logic [4:0]               rf_waddr_wb_o,
  output logic [31:0]              rf_wdata_wb_o,
  output logic                     rf_we_wb_o,

  input logic                      lsu_resp_valid_i,
  input logic                      lsu_resp_err_i,

  output logic                     instr_done_wb_o
);


  import ibex_pkg::*;



  logic [31:0] rf_wdata_wb_mux    [2];
  logic [1:0]  rf_wdata_wb_mux_we;

  if (WritebackStage) begin : g_writeback_stage
    logic [31:0]    rf_wdata_wb_q;
    logic           rf_we_wb_q;
    logic [4:0]     rf_waddr_wb_q;

    logic           wb_done;

    logic           wb_valid_q;
    logic [31:0]    wb_pc_q;
    logic           wb_compressed_q;
    logic           wb_count_q;
    wb_instr_type_e wb_instr_type_q;

    logic           wb_valid_d;



    assign wb_valid_d = (en_wb_i & ready_wb_o) | (wb_valid_q & ~wb_done);




    assign wb_done = (wb_instr_type_q == WB_INSTR_OTHER) | lsu_resp_valid_i;

    always_ff @(posedge clk_i or negedge rst_ni) begin
      if (!rst_ni) begin
        wb_valid_q <= 1'b0;
      end else begin
        wb_valid_q <= wb_valid_d;
      end
    end

    if (ResetAll) begin : g_wb_regs_ra
      always_ff @(posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
          rf_we_wb_q      <= '0;
          rf_waddr_wb_q   <= '0;
          rf_wdata_wb_q   <= '0;
          wb_instr_type_q <= wb_instr_type_e'(0);
          wb_pc_q         <= '0;
          wb_compressed_q <= '0;
          wb_count_q      <= '0;
        end else if (en_wb_i) begin
          rf_we_wb_q      <= rf_we_id_i;
          rf_waddr_wb_q   <= rf_waddr_id_i;
          rf_wdata_wb_q   <= rf_wdata_id_i;
          wb_instr_type_q <= instr_type_wb_i;
          wb_pc_q         <= pc_id_i;
          wb_compressed_q <= instr_is_compressed_id_i;
          wb_count_q      <= instr_perf_count_id_i;
        end
      end
    end else begin : g_wb_regs_nr
      always_ff @(posedge clk_i) begin
        if (en_wb_i) begin
          rf_we_wb_q      <= rf_we_id_i;
          rf_waddr_wb_q   <= rf_waddr_id_i;
          rf_wdata_wb_q   <= rf_wdata_id_i;
          wb_instr_type_q <= instr_type_wb_i;
          wb_pc_q         <= pc_id_i;
          wb_compressed_q <= instr_is_compressed_id_i;
          wb_count_q      <= instr_perf_count_id_i;
        end
      end
    end

    assign rf_waddr_wb_o         = rf_waddr_wb_q;
    assign rf_wdata_wb_mux[0]    = rf_wdata_wb_q;
    assign rf_wdata_wb_mux_we[0] = rf_we_wb_q & wb_valid_q;

    assign ready_wb_o = ~wb_valid_q | wb_done;



    assign rf_write_wb_o = wb_valid_q & (rf_we_wb_q | (wb_instr_type_q == WB_INSTR_LOAD));

    assign outstanding_load_wb_o  = wb_valid_q & (wb_instr_type_q == WB_INSTR_LOAD);
    assign outstanding_store_wb_o = wb_valid_q & (wb_instr_type_q == WB_INSTR_STORE);

    assign pc_wb_o = wb_pc_q;

    assign instr_done_wb_o = wb_valid_q & wb_done;





    assign perf_instr_ret_wb_spec_o            = wb_count_q;
    assign perf_instr_ret_compressed_wb_spec_o = perf_instr_ret_wb_spec_o & wb_compressed_q;
    assign perf_instr_ret_wb_o                 = instr_done_wb_o & wb_count_q &
                                                 ~(lsu_resp_valid_i & lsu_resp_err_i);
    assign perf_instr_ret_compressed_wb_o      = perf_instr_ret_wb_o & wb_compressed_q;




    assign rf_wdata_fwd_wb_o = rf_wdata_wb_q;
  end else begin : g_bypass_wb

    assign rf_waddr_wb_o         = rf_waddr_id_i;
    assign rf_wdata_wb_mux[0]    = rf_wdata_id_i;
    assign rf_wdata_wb_mux_we[0] = rf_we_id_i;




    assign perf_instr_ret_wb_spec_o            = 1'b0;
    assign perf_instr_ret_compressed_wb_spec_o = 1'b0;
    assign perf_instr_ret_wb_o                 = instr_perf_count_id_i & en_wb_i &
                                                 ~(lsu_resp_valid_i & lsu_resp_err_i);
    assign perf_instr_ret_compressed_wb_o      = perf_instr_ret_wb_o & instr_is_compressed_id_i;


    assign ready_wb_o    = 1'b1;




    logic           unused_clk;
    logic           unused_rst;
    wb_instr_type_e unused_instr_type_wb;
    logic [31:0]    unused_pc_id;

    assign unused_clk            = clk_i;
    assign unused_rst            = rst_ni;
    assign unused_instr_type_wb  = instr_type_wb_i;
    assign unused_pc_id          = pc_id_i;

    assign outstanding_load_wb_o  = 1'b0;
    assign outstanding_store_wb_o = 1'b0;
    assign pc_wb_o                = '0;
    assign rf_write_wb_o          = 1'b0;
    assign rf_wdata_fwd_wb_o      = 32'b0;
    assign instr_done_wb_o        = 1'b0;
  end

  assign rf_wdata_wb_mux[1]    = rf_wdata_lsu_i;
  assign rf_wdata_wb_mux_we[1] = rf_we_lsu_i;



  assign rf_wdata_wb_o = ({32{rf_wdata_wb_mux_we[0]}} & rf_wdata_wb_mux[0]) |
                         ({32{rf_wdata_wb_mux_we[1]}} & rf_wdata_wb_mux[1]);
  assign rf_we_wb_o    = |rf_wdata_wb_mux_we;

  `DV_FCOV_SIGNAL_GEN_IF(logic, wb_valid, g_writeback_stage.wb_valid_q, WritebackStage)

  `ASSERT(RFWriteFromOneSourceOnly, $onehot0(rf_wdata_wb_mux_we))
endmodule