data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_4/new/tester.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_4/new/tester.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #10 clock=~clock;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_4/new/tester.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #6 d=~d;\n    ^\n%Error: data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_4/new/tester.v:34: Unsupported or unknown PLI call: $monitor\n        $monitor("time %t: {%b %b} <- {%d}", $time,qA[0],qA[1],d);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_4/new/tester.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #0 d=0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_4/new/tester.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #200 $finish;\n        ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tester();
    reg clock, d;
    wire[1:0] qA, qB;
    shiftA sa(qA,clock,d);
    shiftB sb(qB,clock,d);
    always
    #10 clock=~clock;
    always
    #6 d=~d;
    initial
    begin
        $monitor("time %t: {%b %b} <- {%d}", $time,qA[0],qA[1],d);


        #0 d=0;
        clock=0;
        #200 $finish;
    end
endmodule
module tester();

    reg clock, d;
    wire[1:0] qA, qB;
    shiftA sa(qA,clock,d);
    shiftB sb(qB,clock,d);
    always
    #10 clock=~clock;
    always
    #6 d=~d;
    initial
    begin
        $monitor("time %t: {%b %b} <- {%d}", $time,qA[0],qA[1],d);


        #0 d=0;
        clock=0;
        #200 $finish;
    end
endmodule