data/full_repos/permissive/42061259/LIFO_FIFO/tb.v
1: b'%Error: data/full_repos/permissive/42061259/LIFO_FIFO/tb.v:9: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("test.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/42061259/LIFO_FIFO/tb.v:10: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/42061259/LIFO_FIFO/tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #30 Rst = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42061259/LIFO_FIFO/tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #20 Rst = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/42061259/LIFO_FIFO/tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #20 Wren = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/42061259/LIFO_FIFO/tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #10 Datain = 10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/42061259/LIFO_FIFO/tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #10 Datain = 30;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/42061259/LIFO_FIFO/tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #10 Datain = 40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/42061259/LIFO_FIFO/tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #10 Datain = 50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/42061259/LIFO_FIFO/tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #10 Wren = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/42061259/LIFO_FIFO/tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #25 Rden = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/42061259/LIFO_FIFO/tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #70 Rden = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/42061259/LIFO_FIFO/tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #250 $finish;\n  ^\n%Error: Exiting due to 2 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb(	output reg [32-1:0]  Datain,
			output reg	      Wren,
			output reg	      Rden,
			output reg		  Rst);


	initial begin

		$dumpfile("test.vcd");
		$dumpvars(0);
		Rst = 0;
		Datain = 0;
		Wren = 0;
		Rden = 0;
		#30 Rst = 1;
		#20 Rst = 0;
		#20 Wren = 1;
		Datain = 20;
		#10 Datain = 10;
		#10 Datain = 30;
		#10 Datain = 40;
		#10 Datain = 50;
		#10 Wren = 0;
		#25 Rden = 1;
		#70 Rden = 0;
		#250 $finish;
		
	end
      
endmodule
module tb(	output reg [32-1:0]  Datain,
			output reg	      Wren,
			output reg	      Rden,
			output reg		  Rst);



	initial begin

		$dumpfile("test.vcd");
		$dumpvars(0);
		Rst = 0;
		Datain = 0;
		Wren = 0;
		Rden = 0;
		#30 Rst = 1;
		#20 Rst = 0;
		#20 Wren = 1;
		Datain = 20;
		#10 Datain = 10;
		#10 Datain = 30;
		#10 Datain = 40;
		#10 Datain = 50;
		#10 Wren = 0;
		#25 Rden = 1;
		#70 Rden = 0;
		#250 $finish;
		
	end
      
endmodule