data/full_repos/permissive/440139665/src/last_round.v
1: b"%Error: data/full_repos/permissive/440139665/src/last_round.v:35: Cannot find file containing module: 'sbox'\n            sbox sbox_i (.data_in(data_in[i * 8  + 7 : i * 8]), .data_out(data_out_sbox[i*8+7:i*8]));\n            ^~~~\n        ... Looked in:\n             data/full_repos/permissive/440139665/src,data/full_repos/permissive/440139665/sbox\n             data/full_repos/permissive/440139665/src,data/full_repos/permissive/440139665/sbox.v\n             data/full_repos/permissive/440139665/src,data/full_repos/permissive/440139665/sbox.sv\n             sbox\n             sbox.v\n             sbox.sv\n             obj_dir/sbox\n             obj_dir/sbox.v\n             obj_dir/sbox.sv\n%Error: data/full_repos/permissive/440139665/src/last_round.v:43: Cannot find file containing module: 'shift_rows'\n        shift_rows shift_rows_1 (.data_in(data_out_sbox), .data_out(data_out_shift_prereg));\n        ^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module last_round(
    input clk,
    input data_active_in,
    output reg data_active_out,
    input [127:0] data_in,
    input [127:0] key_in,
    output [127:0] data_out
    );    
    
    wire [127:0] data_out_sbox;
    generate
        for (genvar i=0; i < 16; i = i + 1) begin : gen_blk
            sbox sbox_i (.data_in(data_in[i * 8  + 7 : i * 8]), .data_out(data_out_sbox[i*8+7:i*8]));
        end
    endgenerate
    
    
    
    reg [127:0] data_out_shift;
    wire [127:0] data_out_shift_prereg;
        shift_rows shift_rows_1 (.data_in(data_out_sbox), .data_out(data_out_shift_prereg));
        
    wire [127:0] data_out_prereg;
    
    assign data_out_prereg = data_out_shift ^ key_in;
        
    reg [127:0] data_out_reg;
    always @(posedge clk)
    begin
	data_out_shift <= data_out_shift_prereg;
        data_out_reg <= data_out_prereg;
        
    end
    
    
    reg tmp_data_active;
    always @(posedge clk) begin
	    tmp_data_active <= data_active_in;
	    data_active_out <= tmp_data_active;
    end
   
    assign data_out = data_out_reg;

endmodule
module last_round(
    input clk,
    input data_active_in,
    output reg data_active_out,
    input [127:0] data_in,
    input [127:0] key_in,
    output [127:0] data_out
    );
    
    
    wire [127:0] data_out_sbox;
    generate
        for (genvar i=0; i < 16; i = i + 1) begin : gen_blk
            sbox sbox_i (.data_in(data_in[i * 8  + 7 : i * 8]), .data_out(data_out_sbox[i*8+7:i*8]));
        end
    endgenerate
    
    
    
    reg [127:0] data_out_shift;
    wire [127:0] data_out_shift_prereg;
        shift_rows shift_rows_1 (.data_in(data_out_sbox), .data_out(data_out_shift_prereg));
        
    wire [127:0] data_out_prereg;
    
    assign data_out_prereg = data_out_shift ^ key_in;
        
    reg [127:0] data_out_reg;
    always @(posedge clk)
    begin
	data_out_shift <= data_out_shift_prereg;
        data_out_reg <= data_out_prereg;
        
    end
    
    
    reg tmp_data_active;
    always @(posedge clk) begin
	    tmp_data_active <= data_active_in;
	    data_active_out <= tmp_data_active;
    end
   
    assign data_out = data_out_reg;

endmodule