data/full_repos/permissive/487568919/basic_verilog/vm80a.v
1: b'%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/vm80a.v:826: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'cl\' generates 1 bits.\n                                                                              : ... In instance vm80a.core\n          | ((id_rxc | id_ora | id_ana | id_xra) ? 8\'h00 : (x + r + cl))\n                                                                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module vm80a
(
   input          pin_clk,
   input          pin_f1,
   input          pin_f2,
   input          pin_reset,
   output[15:0]   pin_a,
   inout [7:0]    pin_d,
   input          pin_hold,
   output         pin_hlda,
   input          pin_ready,
   output         pin_wait,
   input          pin_int,
   output         pin_inte,
   output         pin_sync,
   output         pin_dbin,
   output         pin_wr_n
);

wire pin_aena, pin_dena;
wire [7:0] pin_din, pin_dout;
wire [15:0] pin_addr;
reg f1_core, f2_core;

assign pin_a = pin_aena ? pin_addr : 16'hZZZZ;
assign pin_d = pin_dena ? pin_dout : 8'hZZ;
assign pin_din = pin_d;

always @(posedge pin_clk)
begin
   f1_core <= pin_f1;
   f2_core <= pin_f2;
end

vm80a_core core
(
   .pin_clk    (pin_clk),
   .pin_f1     (f1_core),
   .pin_f2     (f2_core),
   .pin_reset  (pin_reset),
   .pin_a      (pin_addr),
   .pin_dout   (pin_dout),
   .pin_din    (pin_din),
   .pin_aena   (pin_aena),
   .pin_dena   (pin_dena),
   .pin_hold   (pin_hold),
   .pin_hlda   (pin_hlda),
   .pin_ready  (pin_ready),
   .pin_wait   (pin_wait),
   .pin_int    (pin_int),
   .pin_inte   (pin_inte),
   .pin_sync   (pin_sync),
   .pin_dbin   (pin_dbin),
   .pin_wr_n   (pin_wr_n)
);
endmodule
module vm80a
(
   input          pin_clk,
   input          pin_f1,
   input          pin_f2,
   input          pin_reset,
   output[15:0]   pin_a,
   inout [7:0]    pin_d,
   input          pin_hold,
   output         pin_hlda,
   input          pin_ready,
   output         pin_wait,
   input          pin_int,
   output         pin_inte,
   output         pin_sync,
   output         pin_dbin,
   output         pin_wr_n
);


wire pin_aena, pin_dena;
wire [7:0] pin_din, pin_dout;
wire [15:0] pin_addr;
reg f1_core, f2_core;

assign pin_a = pin_aena ? pin_addr : 16'hZZZZ;
assign pin_d = pin_dena ? pin_dout : 8'hZZ;
assign pin_din = pin_d;

always @(posedge pin_clk)
begin
   f1_core <= pin_f1;
   f2_core <= pin_f2;
end

vm80a_core core
(
   .pin_clk    (pin_clk),
   .pin_f1     (f1_core),
   .pin_f2     (f2_core),
   .pin_reset  (pin_reset),
   .pin_a      (pin_addr),
   .pin_dout   (pin_dout),
   .pin_din    (pin_din),
   .pin_aena   (pin_aena),
   .pin_dena   (pin_dena),
   .pin_hold   (pin_hold),
   .pin_hlda   (pin_hlda),
   .pin_ready  (pin_ready),
   .pin_wait   (pin_wait),
   .pin_int    (pin_int),
   .pin_inte   (pin_inte),
   .pin_sync   (pin_sync),
   .pin_dbin   (pin_dbin),
   .pin_wr_n   (pin_wr_n)
);
endmodule