data/full_repos/permissive/449370139/verilog_code/vga.v
1: b'%Error: data/full_repos/permissive/449370139/verilog_code/vga.v:58: Cannot find file containing module: \'divider\'\ndivider #(.NUM_DIV(4)) div(.I_CLK(I_clk),.rst(!I_rst_n),.O_CLK(R_clk_25M));\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/449370139/verilog_code,data/full_repos/permissive/449370139/divider\n             data/full_repos/permissive/449370139/verilog_code,data/full_repos/permissive/449370139/divider.v\n             data/full_repos/permissive/449370139/verilog_code,data/full_repos/permissive/449370139/divider.sv\n             divider\n             divider.v\n             divider.sv\n             obj_dir/divider\n             obj_dir/divider.v\n             obj_dir/divider.sv\n%Warning-WIDTH: data/full_repos/permissive/449370139/verilog_code/vga.v:66: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                          : ... In instance vga\n        R_h_cnt <=  9\'d0   ;\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/449370139/verilog_code/vga.v:68: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                          : ... In instance vga\n        R_h_cnt <=  9\'d0   ;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/449370139/verilog_code/vga.v:80: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                          : ... In instance vga\n        R_v_cnt <=  9\'d0   ;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/449370139/verilog_code/vga.v:82: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                          : ... In instance vga\n        R_v_cnt <=  9\'d0   ;\n                ^~\n%Error: data/full_repos/permissive/449370139/verilog_code/vga.v:101: Cannot find file containing module: \'vga_site\'\nvga_site site(\n^~~~~~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n'
module vga(
    input    signed [15:0]   site_X  ,
    input    signed [15:0]   site_Y  ,
    input           [4 :0]   state   ,
    input           [1485:0] broad   ,
    input                    I_clk   ,
    input                    I_rst_n ,
    output   wire   [3:0]    O_red   ,
    output   wire   [3:0]    O_green ,
    output   wire   [3:0]    O_blue  ,
    output                   O_hs    ,  
    output                   O_vs       
);


parameter      C_H_SYNC_PULSE      =   96  ;
parameter      C_H_BACK_PORCH      =   48  ;
parameter      C_H_ACTIVE_TIME     =   640 ;
parameter      C_H_FRONT_PORCH     =   16  ;
parameter      C_H_LINE_PERIOD     =   800 ;


parameter      C_V_SYNC_PULSE      =   2   ; 
parameter      C_V_BACK_PORCH      =   33  ;
parameter      C_V_ACTIVE_TIME     =   480 ;
parameter      C_V_FRONT_PORCH     =   10  ;
parameter      C_V_FRAME_PERIOD    =   525 ;
  
reg [9:0]       R_h_cnt         ;
reg [9:0]       R_v_cnt         ;
wire            R_clk_25M       ;
wire            W_active_flag   ;




divider #(.NUM_DIV(4)) div(.I_CLK(I_clk),.rst(!I_rst_n),.O_CLK(R_clk_25M));




always @(posedge R_clk_25M or negedge I_rst_n)
begin
    if(!I_rst_n)
        R_h_cnt <=  9'd0   ;
    else if(R_h_cnt == C_H_LINE_PERIOD - 1'b1)
        R_h_cnt <=  9'd0   ;
    else
        R_h_cnt <=  R_h_cnt + 1'b1  ;                
end                
assign O_hs =   (R_h_cnt < C_H_SYNC_PULSE||!I_rst_n) ? 1'b0 : 1'b1    ; 




always @(posedge R_clk_25M or negedge I_rst_n)
begin
    if(!I_rst_n)
        R_v_cnt <=  9'd0   ;
    else if(R_v_cnt == C_V_FRAME_PERIOD - 1'b1)
        R_v_cnt <=  9'd0   ;
    else if(R_h_cnt == C_H_LINE_PERIOD - 1'b1)
        R_v_cnt <=  R_v_cnt + 1'b1  ;
    else
        R_v_cnt <=  R_v_cnt ;                        
end                
assign O_vs =   (R_v_cnt < C_V_SYNC_PULSE||!I_rst_n) ? 1'b0 : 1'b1    ; 




assign W_active_flag =  (R_h_cnt >= (C_H_SYNC_PULSE + C_H_BACK_PORCH                  ))  &&
                        (R_h_cnt <= (C_H_SYNC_PULSE + C_H_BACK_PORCH + C_H_ACTIVE_TIME))  && 
                        (R_v_cnt >= (C_V_SYNC_PULSE + C_V_BACK_PORCH                  ))  &&
                        (R_v_cnt <= (C_V_SYNC_PULSE + C_V_BACK_PORCH + C_V_ACTIVE_TIME))  ;                     




vga_site site(
    .state(state),
    .broad(broad),
    .site_X(site_X),
    .site_Y(site_Y),
    .I_rst_n(I_rst_n),
    .R_clk_25M(R_clk_25M),
    .W_active_flag(W_active_flag),    
    .R_h_cnt(R_h_cnt),
    .R_v_cnt(R_v_cnt),     
    .O_red(O_red)   ,
    .O_green(O_green) ,
    .O_blue(O_blue)
);

endmodule
module vga(
    input    signed [15:0]   site_X  ,
    input    signed [15:0]   site_Y  ,
    input           [4 :0]   state   ,
    input           [1485:0] broad   ,
    input                    I_clk   ,
    input                    I_rst_n ,
    output   wire   [3:0]    O_red   ,
    output   wire   [3:0]    O_green ,
    output   wire   [3:0]    O_blue  ,
    output                   O_hs    ,  
    output                   O_vs       
);



parameter      C_H_SYNC_PULSE      =   96  ;
parameter      C_H_BACK_PORCH      =   48  ;
parameter      C_H_ACTIVE_TIME     =   640 ;
parameter      C_H_FRONT_PORCH     =   16  ;
parameter      C_H_LINE_PERIOD     =   800 ;


parameter      C_V_SYNC_PULSE      =   2   ; 
parameter      C_V_BACK_PORCH      =   33  ;
parameter      C_V_ACTIVE_TIME     =   480 ;
parameter      C_V_FRONT_PORCH     =   10  ;
parameter      C_V_FRAME_PERIOD    =   525 ;
  
reg [9:0]       R_h_cnt         ;
reg [9:0]       R_v_cnt         ;
wire            R_clk_25M       ;
wire            W_active_flag   ;




divider #(.NUM_DIV(4)) div(.I_CLK(I_clk),.rst(!I_rst_n),.O_CLK(R_clk_25M));




always @(posedge R_clk_25M or negedge I_rst_n)
begin
    if(!I_rst_n)
        R_h_cnt <=  9'd0   ;
    else if(R_h_cnt == C_H_LINE_PERIOD - 1'b1)
        R_h_cnt <=  9'd0   ;
    else
        R_h_cnt <=  R_h_cnt + 1'b1  ;                
end                
assign O_hs =   (R_h_cnt < C_H_SYNC_PULSE||!I_rst_n) ? 1'b0 : 1'b1    ; 




always @(posedge R_clk_25M or negedge I_rst_n)
begin
    if(!I_rst_n)
        R_v_cnt <=  9'd0   ;
    else if(R_v_cnt == C_V_FRAME_PERIOD - 1'b1)
        R_v_cnt <=  9'd0   ;
    else if(R_h_cnt == C_H_LINE_PERIOD - 1'b1)
        R_v_cnt <=  R_v_cnt + 1'b1  ;
    else
        R_v_cnt <=  R_v_cnt ;                        
end                
assign O_vs =   (R_v_cnt < C_V_SYNC_PULSE||!I_rst_n) ? 1'b0 : 1'b1    ; 




assign W_active_flag =  (R_h_cnt >= (C_H_SYNC_PULSE + C_H_BACK_PORCH                  ))  &&
                        (R_h_cnt <= (C_H_SYNC_PULSE + C_H_BACK_PORCH + C_H_ACTIVE_TIME))  && 
                        (R_v_cnt >= (C_V_SYNC_PULSE + C_V_BACK_PORCH                  ))  &&
                        (R_v_cnt <= (C_V_SYNC_PULSE + C_V_BACK_PORCH + C_V_ACTIVE_TIME))  ;                     




vga_site site(
    .state(state),
    .broad(broad),
    .site_X(site_X),
    .site_Y(site_Y),
    .I_rst_n(I_rst_n),
    .R_clk_25M(R_clk_25M),
    .W_active_flag(W_active_flag),    
    .R_h_cnt(R_h_cnt),
    .R_v_cnt(R_v_cnt),     
    .O_red(O_red)   ,
    .O_green(O_green) ,
    .O_blue(O_blue)
);

endmodule