data/full_repos/permissive/489075769/test bench/read_data_ms_tb.v
1: b'%Error: Cannot find file containing module: bench,data/full_repos/permissive/489075769\n        ... Looked in:\n             data/full_repos/permissive/489075769/test/bench,data/full_repos/permissive/489075769\n             data/full_repos/permissive/489075769/test/bench,data/full_repos/permissive/489075769.v\n             data/full_repos/permissive/489075769/test/bench,data/full_repos/permissive/489075769.sv\n             bench,data/full_repos/permissive/489075769\n             bench,data/full_repos/permissive/489075769.v\n             bench,data/full_repos/permissive/489075769.sv\n             obj_dir/bench,data/full_repos/permissive/489075769\n             obj_dir/bench,data/full_repos/permissive/489075769.v\n             obj_dir/bench,data/full_repos/permissive/489075769.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/489075769/test\n%Error: Cannot find file containing module: bench/read_data_ms_tb.v\n%Error: Exiting due to 3 error(s)\n'
module read_data_ms_tb;

reg ACLK, ARESETn;
reg RVALID, RREADY;
reg [31:0] i_RDATA;
reg [1:0] i_RRESP;

wire [31:0] o_RDATA;
wire [1:0] o_RRESP;

read_data_ms uut(ACLK, ARESETn, RVALID, RREADY, i_RDATA, o_RDATA, i_RRESP, o_RRESP);

initial	begin
i_RDATA = 32'hffffffff;
i_RRESP=2'b01;
#5 RREADY=1'b0;  RVALID=1'b1;
#5 RREADY=1'b0;  RVALID=1'b1;
#5 RREADY=1'b0;  RVALID=1'b1;
#5 RREADY=1'b1;  RVALID=1'b1;
#5 RREADY=1'b1;  RVALID=1'b1;
#5 RREADY=1'b1;  RVALID=1'b0;
#5 RREADY=1'b1;  RVALID=1'b0;
#5 RREADY=1'b1;  RVALID=1'b0;
#5 RREADY=1'b1;  RVALID=1'b0;


#200 $finish;
end
initial begin
ACLK=1'b0;
forever #3 ACLK<=~ACLK;
end
endmodule
module read_data_ms_tb;


reg ACLK, ARESETn;
reg RVALID, RREADY;
reg [31:0] i_RDATA;
reg [1:0] i_RRESP;

wire [31:0] o_RDATA;
wire [1:0] o_RRESP;

read_data_ms uut(ACLK, ARESETn, RVALID, RREADY, i_RDATA, o_RDATA, i_RRESP, o_RRESP);

initial	begin
i_RDATA = 32'hffffffff;
i_RRESP=2'b01;
#5 RREADY=1'b0;  RVALID=1'b1;
#5 RREADY=1'b0;  RVALID=1'b1;
#5 RREADY=1'b0;  RVALID=1'b1;
#5 RREADY=1'b1;  RVALID=1'b1;
#5 RREADY=1'b1;  RVALID=1'b1;
#5 RREADY=1'b1;  RVALID=1'b0;
#5 RREADY=1'b1;  RVALID=1'b0;
#5 RREADY=1'b1;  RVALID=1'b0;
#5 RREADY=1'b1;  RVALID=1'b0;


#200 $finish;
end
initial begin
ACLK=1'b0;
forever #3 ACLK<=~ACLK;
end
endmodule