data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-un-striping/probador_byte_un_striping.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-un-striping/probador_byte_un_striping.v:14: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk_2f = ~clk_2f;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-un-striping/probador_byte_un_striping.v:17: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile ("prueba_byte_un_striping.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-un-striping/probador_byte_un_striping.v:18: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-un-striping/probador_byte_un_striping.v:25: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-un-striping/probador_byte_un_striping.v:29: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-un-striping/probador_byte_un_striping.v:32: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-un-striping/probador_byte_un_striping.v:34: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-un-striping/probador_byte_un_striping.v:36: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-un-striping/probador_byte_un_striping.v:39: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-un-striping/probador_byte_un_striping.v:42: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-un-striping/probador_byte_un_striping.v:45: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-un-striping/probador_byte_un_striping.v:48: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-un-striping/probador_byte_un_striping.v:51: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-un-striping/probador_byte_un_striping.v:54: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-un-striping/probador_byte_un_striping.v:57: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-un-striping/probador_byte_un_striping.v:60: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-un-striping/probador_byte_un_striping.v:63: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-un-striping/probador_byte_un_striping.v:66: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-un-striping/probador_byte_un_striping.v:69: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-un-striping/probador_byte_un_striping.v:72: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-un-striping/probador_byte_un_striping.v:75: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-un-striping/probador_byte_un_striping.v:78: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-un-striping/probador_byte_un_striping.v:87: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n reg [1:0] checker; \n           ^~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-un-striping/probador_byte_un_striping.v:87: syntax error, unexpected \';\', expecting IDENTIFIER or \'=\' or do or final\n reg [1:0] checker; \n                  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-un-striping/probador_byte_un_striping.v:89: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  if (Data_out_c == Data_out_e) checker[1] = 1;\n                                ^~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-un-striping/probador_byte_un_striping.v:89: syntax error, unexpected \'[\'\n  if (Data_out_c == Data_out_e) checker[1] = 1;\n                                       ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-un-striping/probador_byte_un_striping.v:90: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  else checker[1] = 0;\n       ^~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-un-striping/probador_byte_un_striping.v:92: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  if (valid_out_c == valid_out_e) checker[0] = 1;\n                                  ^~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-un-striping/probador_byte_un_striping.v:92: syntax error, unexpected \'[\'\n  if (valid_out_c == valid_out_e) checker[0] = 1;\n                                         ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-un-striping/probador_byte_un_striping.v:93: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  else checker[0] = 0;\n       ^~~~~~~\n%Error: Exiting due to 29 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module probador_byte_un_striping (
	output reg clk_2f,
	output reg reset,
	output reg valid_0,
	output reg [31:0] lane_0,
	output reg valid_1,
	output reg [31:0] lane_1,
	input valid_out_c,
	input [31:0] Data_out_c,
	input valid_out_e,
	input [31:0] Data_out_e
);
	initial clk_2f = 0;
	always #1 clk_2f = ~clk_2f;

	initial begin
		$dumpfile ("prueba_byte_un_striping.vcd");
		$dumpvars;

		reset <= 0;
		valid_0 <= 0;
		lane_0 <= 0;
		valid_1 <= 0;
		lane_1 <= 0;
		@(posedge clk_2f);
		reset <= 1;
		valid_0 <= 1;
		lane_0 <= 'hFFFFFFFF;
		@(posedge clk_2f);
		valid_1 <= 1;
		lane_1 <= 'hEEEEEEEE;
		@(posedge clk_2f);
		lane_0 <= 'hDDDDDDDD;
		@(posedge clk_2f);
		lane_1 <= 'hCCCCCCCC;
		@(posedge clk_2f);
		valid_0 <= 0;
		lane_0 <= 32'b0;
		@(posedge clk_2f);
		valid_1 <= 0;
		lane_1 <= 32'b0;
		@(posedge clk_2f);
		valid_0 <= 1;
		lane_0 <= 'h00000003;
		@(posedge clk_2f);
		valid_1 <= 1;
		lane_1 <= 'h00000004;
		@(posedge clk_2f);
		valid_0 <= 0;
		lane_0 <= 32'b0;
		@(posedge clk_2f);
		valid_1 <= 0;
		lane_1 <= 32'b0;
		@(posedge clk_2f);
		valid_0 <= 1;
		lane_0 <= 'hAAAAAAAA;
		@(posedge clk_2f);
		valid_1 <= 1;
		lane_1 <= 'h99999999;
		@(posedge clk_2f);
		valid_0 <= 0;
		lane_0 <= 'h11111111;
		@(posedge clk_2f);
		valid_1 <= 0;
		lane_1 <= 32'b0;
		@(posedge clk_2f);
		valid_0 <= 1;
		lane_0 <= 'h00000007;
		@(posedge clk_2f);
		valid_1 <= 1;
		lane_1 <= 'h00000008;
		@(posedge clk_2f);
		valid_0 <= 0;
		lane_0 <= 32'b0;
		@(posedge clk_2f);
		valid_1 <= 1;
		lane_1 <= 'h22222222;
		@(posedge clk_2f);
		@(posedge clk_2f);
		@(posedge clk_2f);
		$finish;
	end




	reg [1:0] checker; 
	always @(*) begin
		if (Data_out_c == Data_out_e) checker[1] = 1;
		else checker[1] = 0;

		if (valid_out_c == valid_out_e) checker[0] = 1;
		else checker[0] = 0;
	end
endmodule
module probador_byte_un_striping (
	output reg clk_2f,
	output reg reset,
	output reg valid_0,
	output reg [31:0] lane_0,
	output reg valid_1,
	output reg [31:0] lane_1,
	input valid_out_c,
	input [31:0] Data_out_c,
	input valid_out_e,
	input [31:0] Data_out_e
);

	initial clk_2f = 0;
	always #1 clk_2f = ~clk_2f;

	initial begin
		$dumpfile ("prueba_byte_un_striping.vcd");
		$dumpvars;

		reset <= 0;
		valid_0 <= 0;
		lane_0 <= 0;
		valid_1 <= 0;
		lane_1 <= 0;
		@(posedge clk_2f);
		reset <= 1;
		valid_0 <= 1;
		lane_0 <= 'hFFFFFFFF;
		@(posedge clk_2f);
		valid_1 <= 1;
		lane_1 <= 'hEEEEEEEE;
		@(posedge clk_2f);
		lane_0 <= 'hDDDDDDDD;
		@(posedge clk_2f);
		lane_1 <= 'hCCCCCCCC;
		@(posedge clk_2f);
		valid_0 <= 0;
		lane_0 <= 32'b0;
		@(posedge clk_2f);
		valid_1 <= 0;
		lane_1 <= 32'b0;
		@(posedge clk_2f);
		valid_0 <= 1;
		lane_0 <= 'h00000003;
		@(posedge clk_2f);
		valid_1 <= 1;
		lane_1 <= 'h00000004;
		@(posedge clk_2f);
		valid_0 <= 0;
		lane_0 <= 32'b0;
		@(posedge clk_2f);
		valid_1 <= 0;
		lane_1 <= 32'b0;
		@(posedge clk_2f);
		valid_0 <= 1;
		lane_0 <= 'hAAAAAAAA;
		@(posedge clk_2f);
		valid_1 <= 1;
		lane_1 <= 'h99999999;
		@(posedge clk_2f);
		valid_0 <= 0;
		lane_0 <= 'h11111111;
		@(posedge clk_2f);
		valid_1 <= 0;
		lane_1 <= 32'b0;
		@(posedge clk_2f);
		valid_0 <= 1;
		lane_0 <= 'h00000007;
		@(posedge clk_2f);
		valid_1 <= 1;
		lane_1 <= 'h00000008;
		@(posedge clk_2f);
		valid_0 <= 0;
		lane_0 <= 32'b0;
		@(posedge clk_2f);
		valid_1 <= 1;
		lane_1 <= 'h22222222;
		@(posedge clk_2f);
		@(posedge clk_2f);
		@(posedge clk_2f);
		$finish;
	end




	reg [1:0] checker; 
	always @(*) begin
		if (Data_out_c == Data_out_e) checker[1] = 1;
		else checker[1] = 0;

		if (valid_out_c == valid_out_e) checker[0] = 1;
		else checker[0] = 0;
	end
endmodule