data/full_repos/permissive/441359809/src/yosys/techlibs/anlogic/lutrams_map.v
1: b'%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/anlogic/lutrams_map.v:13: Cannot find include file: lutram_init_16x4.vh\n  `include "lutram_init_16x4.vh" \n           ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/441359809/src/yosys/techlibs/anlogic,data/full_repos/permissive/441359809/lutram_init_16x4.vh\n             data/full_repos/permissive/441359809/src/yosys/techlibs/anlogic,data/full_repos/permissive/441359809/lutram_init_16x4.vh.v\n             data/full_repos/permissive/441359809/src/yosys/techlibs/anlogic,data/full_repos/permissive/441359809/lutram_init_16x4.vh.sv\n             lutram_init_16x4.vh\n             lutram_init_16x4.vh.v\n             lutram_init_16x4.vh.sv\n             obj_dir/lutram_init_16x4.vh\n             obj_dir/lutram_init_16x4.vh.v\n             obj_dir/lutram_init_16x4.vh.sv\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/anlogic/lutrams_map.v:20: Unexpected \'do\': \'do\' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n  .do(A1DATA)\n   ^~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/anlogic/lutrams_map.v:20: syntax error, unexpected \'(\', expecting \')\'\n  .do(A1DATA)\n      ^~~~~~\n%Error: Exiting due to 3 error(s)\n'
module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
	parameter [63:0]INIT = 64'bx;
	input CLK1;

	input [3:0] A1ADDR;
	output [3:0] A1DATA;

	input [3:0] B1ADDR;
	input [3:0] B1DATA;
	input B1EN;

	EG_LOGIC_DRAM16X4 #(
		`include "lutram_init_16x4.vh"
	) _TECHMAP_REPLACE_ (
		.di(B1DATA),
		.waddr(B1ADDR),
		.wclk(CLK1),
		.we(B1EN),
		.raddr(A1ADDR),
		.do(A1DATA)
	);
endmodule
module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);

	parameter [63:0]INIT = 64'bx;
	input CLK1;

	input [3:0] A1ADDR;
	output [3:0] A1DATA;

	input [3:0] B1ADDR;
	input [3:0] B1DATA;
	input B1EN;

	EG_LOGIC_DRAM16X4 #(
		`include "lutram_init_16x4.vh"
	) _TECHMAP_REPLACE_ (
		.di(B1DATA),
		.waddr(B1ADDR),
		.wclk(CLK1),
		.we(B1EN),
		.raddr(A1ADDR),
		.do(A1DATA)
	);
endmodule