data/full_repos/permissive/446128190/rtl/Bitlet_Prim_BufferArray.v
1: b"%Error: data/full_repos/permissive/446128190/rtl/Bitlet_Prim_BufferArray.v:29: Cannot find file containing module: 'Bitlet_Prim_Decoder_Decimal_to_Onehot'\nBitlet_Prim_Decoder_Decimal_to_Onehot #(.W(N)) UDECODER\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/446128190/rtl,data/full_repos/permissive/446128190/Bitlet_Prim_Decoder_Decimal_to_Onehot\n             data/full_repos/permissive/446128190/rtl,data/full_repos/permissive/446128190/Bitlet_Prim_Decoder_Decimal_to_Onehot.v\n             data/full_repos/permissive/446128190/rtl,data/full_repos/permissive/446128190/Bitlet_Prim_Decoder_Decimal_to_Onehot.sv\n             Bitlet_Prim_Decoder_Decimal_to_Onehot\n             Bitlet_Prim_Decoder_Decimal_to_Onehot.v\n             Bitlet_Prim_Decoder_Decimal_to_Onehot.sv\n             obj_dir/Bitlet_Prim_Decoder_Decimal_to_Onehot\n             obj_dir/Bitlet_Prim_Decoder_Decimal_to_Onehot.v\n             obj_dir/Bitlet_Prim_Decoder_Decimal_to_Onehot.sv\n%Error: Exiting due to 1 error(s)\n"
module Bitlet_Prim_Buffer
#(
    parameter   W = 16
)
(
    input               clk,
    input               rst_n,
    input               enw,
    input       [W-1:0] DI,
    output reg  [W-1:0] DO
);

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
        DO  <= 'b0;
    else if (enw)
        DO  <= DI;
end

endmodule
module Bitlet_Prim_Buffer
#(
    parameter   W = 16
)
(
    input               clk,
    input               rst_n,
    input               enw,
    input       [W-1:0] DI,
    output reg  [W-1:0] DO
);


always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
        DO  <= 'b0;
    else if (enw)
        DO  <= DI;
end

endmodule