data/full_repos/permissive/488093047/Verilog Codes/TB_Register_4bit.v
1: b'%Error: Cannot find file containing module: Codes,data/full_repos/permissive/488093047\n        ... Looked in:\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.v\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.sv\n             Codes,data/full_repos/permissive/488093047\n             Codes,data/full_repos/permissive/488093047.v\n             Codes,data/full_repos/permissive/488093047.sv\n             obj_dir/Codes,data/full_repos/permissive/488093047\n             obj_dir/Codes,data/full_repos/permissive/488093047.v\n             obj_dir/Codes,data/full_repos/permissive/488093047.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/488093047/Verilog\n%Error: Cannot find file containing module: Codes/TB_Register_4bit.v\n%Error: Exiting due to 3 error(s)\n'
module TB_Register_4bit();
reg [3:0]D;
reg reset,clk;
wire [3:0]Q;

Register_4bit DUT1 ( .D(D), .clk(clk), .reset(reset), .Q(Q));
initial begin

D = 4'b0;
clk = 1'b1;
reset = 1'b1;
#100;

reset = 1'b0;
#200;
forever #50 D = D+1;
end

always #10 clk = ~clk;




endmodule
module TB_Register_4bit();

reg [3:0]D;
reg reset,clk;
wire [3:0]Q;

Register_4bit DUT1 ( .D(D), .clk(clk), .reset(reset), .Q(Q));
initial begin

D = 4'b0;
clk = 1'b1;
reset = 1'b1;
#100;

reset = 1'b0;
#200;
forever #50 D = D+1;
end

always #10 clk = ~clk;




endmodule