data/full_repos/permissive/515471991/DownCounter.v
data/verilator_xmls/1731fa5e-5234-4501-b909-3663e4dd0d41.xml
module down_counter(input clk, reset, output [3:0] counter);
    reg [3:0] counter_down;
    always @(posedge clk or posedge reset)
    begin
        if(reset)
            begin
                counter_down = 4'hf;
            end
        else
            begin
                counter_down = counter_down - 4'd1;
            end                                     
    end 
    assign counter = counter_down;
endmodule
module down_counter(input clk, reset, output [3:0] counter);

    reg [3:0] counter_down;
    always @(posedge clk or posedge reset)
    begin
        if(reset)
            begin
                counter_down = 4'hf;
            end
        else
            begin
                counter_down = counter_down - 4'd1;
            end                                     
    end 
    assign counter = counter_down;
endmodule