data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_paupro.v
data/verilator_xmls/a45a9460-fc40-496b-a543-cd55a9b77f66.xml
module ipsmacge_paupro
    (
     txrst_,
     txclk,
     ipauen,
     ipaudi,
     
     possfd,

     opauen,
     opaudi,

     ppaudis
     );






input       txrst_;
input       txclk;

input       ipauen;
input       ipaudi;

input       possfd;

output      opauen;
output      opaudi;

input       ppaudis;




reg         opauen;
always @(posedge txclk or negedge txrst_)
    begin
    if (!txrst_)        opauen <= 1'b0;
    else if (ppaudis)   opauen <= 1'b0;
    else
        begin
        case ({ipauen, possfd})
            2'b10:      opauen <= 1'b1;
            2'b11:      opauen <= 1'b1;
            2'b01:      opauen <= 1'b0;
            default:    opauen <= opauen;
        endcase
        end
    end


reg         opaudi; 
always @(posedge txclk or negedge txrst_) 
    begin
    if (!txrst_)        opaudi <= 1'b0;
    else if (ppaudis)   opaudi <= 1'b0;
    else                opaudi <= ipaudi;
    end

endmodule
module ipsmacge_paupro
    (
     txrst_,
     txclk,
     ipauen,
     ipaudi,
     
     possfd,

     opauen,
     opaudi,

     ppaudis
     );







input       txrst_;
input       txclk;

input       ipauen;
input       ipaudi;

input       possfd;

output      opauen;
output      opaudi;

input       ppaudis;




reg         opauen;
always @(posedge txclk or negedge txrst_)
    begin
    if (!txrst_)        opauen <= 1'b0;
    else if (ppaudis)   opauen <= 1'b0;
    else
        begin
        case ({ipauen, possfd})
            2'b10:      opauen <= 1'b1;
            2'b11:      opauen <= 1'b1;
            2'b01:      opauen <= 1'b0;
            default:    opauen <= opauen;
        endcase
        end
    end


reg         opaudi; 
always @(posedge txclk or negedge txrst_) 
    begin
    if (!txrst_)        opaudi <= 1'b0;
    else if (ppaudis)   opaudi <= 1'b0;
    else                opaudi <= ipaudi;
    end

endmodule