data/full_repos/permissive/423547971/FPGA Projects/Byte Calculator/byte_calculator.v
1: b'%Error: Cannot find file containing module: Projects/Byte\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/Byte\n             data/full_repos/permissive/423547971/FPGA/Projects/Byte.v\n             data/full_repos/permissive/423547971/FPGA/Projects/Byte.sv\n             Projects/Byte\n             Projects/Byte.v\n             Projects/Byte.sv\n             obj_dir/Projects/Byte\n             obj_dir/Projects/Byte.v\n             obj_dir/Projects/Byte.sv\n%Error: Cannot find file containing module: Calculator,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: Calculator/byte_calculator.v\n%Error: Exiting due to 4 error(s)\n'
module byte_calculator(
    input clk,
    input [7:0] byte_A,
    input [7:0] byte_B,
    input [4:0] op_select,
    output reg [8:0] result
    );
    
    wire reset;
    assign reset = op_select[4];





    
    always @(posedge clk or posedge reset) begin
        if(reset)
            result <= 8'b0000_0000;
        else
            case(op_select)
                5'b01000 : result <= byte_A + byte_B;
                5'b00100 : result <= byte_A - byte_B;
                5'b00010 : result <= byte_A * byte_B;
                5'b00001 : result <= byte_A / byte_B;
            endcase
    end
    
    
endmodule
module byte_calculator(
    input clk,
    input [7:0] byte_A,
    input [7:0] byte_B,
    input [4:0] op_select,
    output reg [8:0] result
    );

    
    wire reset;
    assign reset = op_select[4];





    
    always @(posedge clk or posedge reset) begin
        if(reset)
            result <= 8'b0000_0000;
        else
            case(op_select)
                5'b01000 : result <= byte_A + byte_B;
                5'b00100 : result <= byte_A - byte_B;
                5'b00010 : result <= byte_A * byte_B;
                5'b00001 : result <= byte_A / byte_B;
            endcase
    end
    
    
endmodule