data/full_repos/permissive/515598112/3_Circuits/02_Sequential_Logic/02_Counters/05_Counter_1-12.v
1: b"%Error: data/full_repos/permissive/515598112/3_Circuits/02_Sequential_Logic/02_Counters/05_Counter_1-12.v:15: Cannot find file containing module: 'count4'\n    count4 the_counter (\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/515598112/3_Circuits/02_Sequential_Logic/02_Counters,data/full_repos/permissive/515598112/count4\n             data/full_repos/permissive/515598112/3_Circuits/02_Sequential_Logic/02_Counters,data/full_repos/permissive/515598112/count4.v\n             data/full_repos/permissive/515598112/3_Circuits/02_Sequential_Logic/02_Counters,data/full_repos/permissive/515598112/count4.sv\n             count4\n             count4.v\n             count4.sv\n             obj_dir/count4\n             obj_dir/count4.v\n             obj_dir/count4.sv\n%Error: Exiting due to 1 error(s)\n"
module top_module (
    input clk,
    input reset,
    input enable,
    output reg [3:0] Q,
    output c_enable,
    output c_load,
    output [3:0] c_d
);
    
    assign c_d = 4'h1;
    assign c_enable = enable;
    assign c_load = reset | (Q == 4'hc && enable == 1'b1);

    count4 the_counter (
        .clk(clk),
        .enable(c_enable),
        .load(c_load),
        .d(c_d),
        .Q(Q)
    );

endmodule
module top_module (
    input clk,
    input reset,
    input enable,
    output reg [3:0] Q,
    output c_enable,
    output c_load,
    output [3:0] c_d
);

    
    assign c_d = 4'h1;
    assign c_enable = enable;
    assign c_load = reset | (Q == 4'hc && enable == 1'b1);

    count4 the_counter (
        .clk(clk),
        .enable(c_enable),
        .load(c_load),
        .d(c_d),
        .Q(Q)
    );

endmodule