data/full_repos/permissive/444327372/mips.v
1: b"%Error: data/full_repos/permissive/444327372/mips.v:88: Cannot find file containing module: 'controller'\n controller c(\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/444327372,data/full_repos/permissive/444327372/controller\n             data/full_repos/permissive/444327372,data/full_repos/permissive/444327372/controller.v\n             data/full_repos/permissive/444327372,data/full_repos/permissive/444327372/controller.sv\n             controller\n             controller.v\n             controller.sv\n             obj_dir/controller\n             obj_dir/controller.v\n             obj_dir/controller.sv\n%Error: data/full_repos/permissive/444327372/mips.v:135: Cannot find file containing module: 'datapath'\n datapath dp(\n ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module mips(
	input wire clk,rst,
	output wire[31:0] pcF,
	input wire[31:0] instrF,
	output wire memenM,
	output wire memwriteM,
	output wire[31:0] aluoutM,writedataM,


	input wire[31:0] readdataM,
	output wire [3:0] selM,
	output wire [1:0] sizeM,



	output wire [31:0] debug_wb_pc,
	output wire [3 :0] debug_wb_rf_wen,
	output wire [4 :0] debug_wb_rf_wnum,
	output wire [31:0] debug_wb_rf_wdata
    );






	wire [31:0] instrD;
	wire [5 :0] opD;
	wire [5 :0] functD;
	wire 		pcsrcD;
	wire 		equalD;
	wire 		stallD;
	wire 		branchD;
	wire 		jumpD;
	wire 		jalD;
	wire 		jrD;
	wire 		balD;


	wire 		stallE;
	wire 		flushE;
	wire [7 :0] alucontrolE;
	wire 		regdstE;
	wire 		alusrcE;
	wire 		memtoregE;
	wire 		regwriteE;

	wire 		hi_weE;
	wire 		lo_weE;
	wire 		div_validE;
	wire 		signed_divE;
	
	wire 		jalE;
	wire 		balE;
	wire 		jrE;


	wire 		memtoregM;
	wire 		regwriteM;
	wire [7 :0] alucontrolM;


	wire 		memtoregW;
	wire 		regwriteW;

	controller c(
		.clk(clk),
		.rst(rst),
		

		.opD(opD),
		.functD(functD),
		.pcsrcD(pcsrcD),
		.equalD(equalD),

		.branchD(branchD),
		.jumpD(jumpD),
		.jalD(jalD),
		.jrD(jrD),
		.balD(balD),
		
		.instrD(instrD),
		.stallD(stallD),
		

		.flushE(flushE),
		.stallE(stallE),
		.memtoregE(memtoregE),
		.alusrcE(alusrcE),
		.regdstE(regdstE),
		.regwriteE(regwriteE),	
		.alucontrolE(alucontrolE),
		.hi_weE(hi_weE),
		.lo_weE(lo_weE),
		.div_validE(div_validE),
		.signed_divE(signed_divE),
		.jalE(jalE),
		.jrE(jrE),
		.balE(balE),


		.memenM(memenM),
		.memtoregM(memtoregM),
		.memwriteM(memwriteM),
		.regwriteM(regwriteM),
		.alucontrolM(alucontrolM),
		

		.memtoregW(memtoregW),
		.regwriteW(regwriteW)
		);
	
	datapath dp(
		.clk(clk),
		.rst(rst),


		.pcF(pcF),
		.instrF(instrF),


		.pcsrcD(pcsrcD),

		.branchD(branchD),
		.jumpD(jumpD),
		.jalD(jalD),
		.jrD(jrD),
		.balD(balD),

		.equalD(equalD),
		.opD(opD),
		.functD(functD),
		.instrD(instrD),
		.stallD(stallD),


		.memtoregE(memtoregE),
		.alusrcE(alusrcE),
		.regdstE(regdstE),
		.regwriteE(regwriteE),
		.alucontrolE(alucontrolE),
		.hi_weE(hi_weE),
		.lo_weE(lo_weE),
		.div_validE(div_validE),
		.signed_divE(signed_divE),
		.jalE(jalE),
		.jrE(jrE),
		.balE(balE),
		.stallE(stallE),
		.flushE(flushE),



		.memtoregM(memtoregM),
		.regwriteM(regwriteM),
		.aluoutM(aluoutM),

		.writedata2M(writedataM),
		.readdataM(readdataM),
		.alucontrolM(alucontrolM),
		.selM(selM),
		.sizeM(sizeM),


		.memtoregW(memtoregW),
		.regwriteW(regwriteW),


		.pcW(debug_wb_pc),
		.rf_wen(debug_wb_rf_wen),
		.writeregW(debug_wb_rf_wnum),
		.resultW(debug_wb_rf_wdata)
	    );
	
endmodule
module mips(
	input wire clk,rst,
	output wire[31:0] pcF,
	input wire[31:0] instrF,
	output wire memenM,
	output wire memwriteM,
	output wire[31:0] aluoutM,writedataM,


	input wire[31:0] readdataM,
	output wire [3:0] selM,
	output wire [1:0] sizeM,



	output wire [31:0] debug_wb_pc,
	output wire [3 :0] debug_wb_rf_wen,
	output wire [4 :0] debug_wb_rf_wnum,
	output wire [31:0] debug_wb_rf_wdata
    );







	wire [31:0] instrD;
	wire [5 :0] opD;
	wire [5 :0] functD;
	wire 		pcsrcD;
	wire 		equalD;
	wire 		stallD;
	wire 		branchD;
	wire 		jumpD;
	wire 		jalD;
	wire 		jrD;
	wire 		balD;


	wire 		stallE;
	wire 		flushE;
	wire [7 :0] alucontrolE;
	wire 		regdstE;
	wire 		alusrcE;
	wire 		memtoregE;
	wire 		regwriteE;

	wire 		hi_weE;
	wire 		lo_weE;
	wire 		div_validE;
	wire 		signed_divE;
	
	wire 		jalE;
	wire 		balE;
	wire 		jrE;


	wire 		memtoregM;
	wire 		regwriteM;
	wire [7 :0] alucontrolM;


	wire 		memtoregW;
	wire 		regwriteW;

	controller c(
		.clk(clk),
		.rst(rst),
		

		.opD(opD),
		.functD(functD),
		.pcsrcD(pcsrcD),
		.equalD(equalD),

		.branchD(branchD),
		.jumpD(jumpD),
		.jalD(jalD),
		.jrD(jrD),
		.balD(balD),
		
		.instrD(instrD),
		.stallD(stallD),
		

		.flushE(flushE),
		.stallE(stallE),
		.memtoregE(memtoregE),
		.alusrcE(alusrcE),
		.regdstE(regdstE),
		.regwriteE(regwriteE),	
		.alucontrolE(alucontrolE),
		.hi_weE(hi_weE),
		.lo_weE(lo_weE),
		.div_validE(div_validE),
		.signed_divE(signed_divE),
		.jalE(jalE),
		.jrE(jrE),
		.balE(balE),


		.memenM(memenM),
		.memtoregM(memtoregM),
		.memwriteM(memwriteM),
		.regwriteM(regwriteM),
		.alucontrolM(alucontrolM),
		

		.memtoregW(memtoregW),
		.regwriteW(regwriteW)
		);
	
	datapath dp(
		.clk(clk),
		.rst(rst),


		.pcF(pcF),
		.instrF(instrF),


		.pcsrcD(pcsrcD),

		.branchD(branchD),
		.jumpD(jumpD),
		.jalD(jalD),
		.jrD(jrD),
		.balD(balD),

		.equalD(equalD),
		.opD(opD),
		.functD(functD),
		.instrD(instrD),
		.stallD(stallD),


		.memtoregE(memtoregE),
		.alusrcE(alusrcE),
		.regdstE(regdstE),
		.regwriteE(regwriteE),
		.alucontrolE(alucontrolE),
		.hi_weE(hi_weE),
		.lo_weE(lo_weE),
		.div_validE(div_validE),
		.signed_divE(signed_divE),
		.jalE(jalE),
		.jrE(jrE),
		.balE(balE),
		.stallE(stallE),
		.flushE(flushE),



		.memtoregM(memtoregM),
		.regwriteM(regwriteM),
		.aluoutM(aluoutM),

		.writedata2M(writedataM),
		.readdataM(readdataM),
		.alucontrolM(alucontrolM),
		.selM(selM),
		.sizeM(sizeM),


		.memtoregW(memtoregW),
		.regwriteW(regwriteW),


		.pcW(debug_wb_pc),
		.rf_wen(debug_wb_rf_wen),
		.writeregW(debug_wb_rf_wnum),
		.resultW(debug_wb_rf_wdata)
	    );
	
endmodule