data/full_repos/permissive/506186384/project-files/lab6/Data_Hazard_Handler.v
data/verilator_xmls/e8e335a3-1bc6-4f9a-a771-de1fbca9feb9.xml
module Data_Hazard_Handler(

    input Clk,
    input reset,
    

    input [5:0] EX_OpCode,
    input [5:0] EX_Funct,
    input MEM_regWrite,
    input [4:0] MEM_writeReg,
    input WB_regWrite,
    input [4:0] WB_writeReg,
    input [4:0] EX_rs,
    
    output [1:0] Input1_Sel,
    output [1:0] Input2_Sel,
    output [1:0] sw_sel, 
    output [1:0] jr_sel,
    

    input EX_MemRead,
    input [4:0] EX_rt,
    input [31:0] ID_Instr,
    
    output D_Bubble
    );
    
    reg d_bubble;
    
    assign D_Bubble = d_bubble;
    

    always @(ID_Instr or EX_MemRead or EX_rt)
        begin
            if(EX_MemRead == 1 && EX_rt != 0)begin
                casex({ID_Instr[31:26],ID_Instr[5:0]})
                    12'b100011xxxxxx:
                    begin 

                        if(ID_Instr[25:21] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b100100xxxxxx:
                    begin 

                        if(ID_Instr[25:21] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b100101xxxxxx:
                    begin 

                        if(ID_Instr[25:21] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b101011xxxxxx:
                    begin

                        if(ID_Instr[25:21] == EX_rt || ID_Instr[20:16] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b101000xxxxxx:
                    begin

                        if(ID_Instr[25:21] == EX_rt || ID_Instr[20:16] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b101001xxxxxx:
                    begin

                        if(ID_Instr[25:21] == EX_rt || ID_Instr[20:16] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b000100xxxxxx:
                    begin

                        if(ID_Instr[25:21] == EX_rt || ID_Instr[20:16] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b000101xxxxxx:
                    begin

                        if(ID_Instr[25:21] == EX_rt || ID_Instr[20:16] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b000000000000:
                    begin

                        if(ID_Instr[20:16] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b000000000010:
                    begin

                        if(ID_Instr[20:16] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b000000000011:
                    begin

                        if(ID_Instr[20:16] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b000000001000:
                    begin

                        if(ID_Instr[25:21] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b000000xxxxxx:
                    begin

                        if(ID_Instr[25:21] == EX_rt || ID_Instr[20:16] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b001000xxxxxx:
                    begin

                        if(ID_Instr[25:21] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b001001xxxxxx:
                    begin

                        if(ID_Instr[25:21] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b001111xxxxxx:
                    begin
                        d_bubble = 0;
                    end
                    12'b001010xxxxxx:
                    begin

                        if(ID_Instr[25:21] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b001011xxxxxx:
                    begin

                        if(ID_Instr[25:21] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b001100xxxxxx:
                    begin

                        if(ID_Instr[25:21] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b001101xxxxxx:
                    begin

                        if(ID_Instr[25:21] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b001110xxxxxx:
                    begin

                        if(ID_Instr[25:21] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b000011xxxxxx:
                    begin
                        d_bubble = 0;
                    end
                    12'b000010xxxxxx:
                    begin
                        d_bubble = 0;
                    end
                    default:
                        d_bubble = 0;
                endcase
            end
            else d_bubble = 0;
        end
    
    reg [1:0] input1_sel;
    reg [1:0] input2_sel;
    reg [1:0] sw_sel_reg;
    reg [1:0] jr_sel_reg;
    
    assign Input1_Sel = input1_sel;
    assign Input2_Sel = input2_sel;
    assign sw_sel = sw_sel_reg;
    assign jr_sel = jr_sel_reg;
    

    always @(EX_OpCode, EX_Funct, EX_rs, EX_rt, MEM_regWrite, 
        MEM_writeReg, WB_regWrite, WB_writeReg) 
        begin
            
            casex({EX_OpCode,EX_Funct}) 
                12'b100011xxxxxx:
                begin 

                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input1_sel = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input1_sel = 2'b10;
                    end
                    else begin
                        input1_sel = 2'b00;
                    end
                    input2_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b100100xxxxxx:
                begin 

                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input1_sel = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input1_sel = 2'b10;
                    end
                    else begin
                        input1_sel = 2'b00;
                    end
                    input2_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b100101xxxxxx:
                begin 

                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input1_sel = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input1_sel = 2'b10;
                    end
                    else begin
                        input1_sel = 2'b00;
                    end
                    input2_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b101011xxxxxx:
                begin


                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input1_sel = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input1_sel = 2'b10;
                    end
                    else begin
                        input1_sel = 2'b00;
                    end

                    if(EX_rt == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        sw_sel_reg = 2'b01;
                    end
                    else if(EX_rt == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        sw_sel_reg = 2'b10;
                    end
                    else begin
                        sw_sel_reg = 2'b00;
                    end
                    input2_sel = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b101000xxxxxx:
                begin


                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input1_sel = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input1_sel = 2'b10;
                    end
                    else begin
                        input1_sel = 2'b00;
                    end

                    if(EX_rt == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        sw_sel_reg = 2'b01;
                    end
                    else if(EX_rt == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        sw_sel_reg = 2'b10;
                    end
                    else begin
                        sw_sel_reg = 2'b00;
                    end
                    input2_sel = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b101001xxxxxx:
                begin


                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input1_sel = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input1_sel = 2'b10;
                    end
                    else begin
                        input1_sel = 2'b00;
                    end

                    if(EX_rt == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        sw_sel_reg = 2'b01;
                    end
                    else if(EX_rt == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        sw_sel_reg = 2'b10;
                    end
                    else begin
                        sw_sel_reg = 2'b00;
                    end
                    input2_sel = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b000100xxxxxx:
                begin


                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input1_sel = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input1_sel = 2'b10;
                    end
                    else begin
                        input1_sel = 2'b00;
                    end

                    if(EX_rt == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input2_sel = 2'b01;
                    end
                    else if(EX_rt == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input2_sel = 2'b10;
                    end
                    else begin
                        input2_sel = 2'b00;
                    end
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b000101xxxxxx:
                begin


                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input1_sel = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input1_sel = 2'b10;
                    end
                    else begin
                        input1_sel = 2'b00;
                    end

                    if(EX_rt == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input2_sel = 2'b01;
                    end
                    else if(EX_rt == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input2_sel = 2'b10;
                    end
                    else begin
                        input2_sel = 2'b00;
                    end
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b000000000000:
                begin

                    if(EX_rt == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input2_sel = 2'b01;
                    end
                    else if(EX_rt == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input2_sel = 2'b10;
                    end
                    else begin
                        input2_sel = 2'b00;
                    end
                    input1_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b000000000010:
                begin

                    if(EX_rt == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input2_sel = 2'b01;
                    end
                    else if(EX_rt == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input2_sel = 2'b10;
                    end
                    else begin
                        input2_sel = 2'b00;
                    end
                    input1_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b000000000011:
                begin

                    if(EX_rt == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input2_sel = 2'b01;
                    end
                    else if(EX_rt == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input2_sel = 2'b10;
                    end
                    else begin
                        input2_sel = 2'b00;
                    end
                    input1_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b000000001000:
                begin

                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        jr_sel_reg = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        jr_sel_reg = 2'b10;
                    end
                    else begin
                        jr_sel_reg = 2'b00;
                    end
                    input1_sel = 2'b00;
                    input2_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                end
                12'b000000xxxxxx:
                begin


                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input1_sel = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input1_sel = 2'b10;
                    end
                    else begin
                        input1_sel = 2'b00;
                    end

                    if(EX_rt == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input2_sel = 2'b01;
                    end
                    else if(EX_rt == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input2_sel = 2'b10;
                    end
                    else begin
                        input2_sel = 2'b00;
                    end
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b001000xxxxxx:
                begin

                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input1_sel = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input1_sel = 2'b10;
                    end
                    else begin
                        input1_sel = 2'b00;
                    end
                    input2_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b001001xxxxxx:
                begin

                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input1_sel = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input1_sel = 2'b10;
                    end
                    else begin
                        input1_sel = 2'b00;
                    end
                    input2_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b001111xxxxxx:
                begin
                    input1_sel = 2'b00;
                    input2_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b001010xxxxxx:
                begin

                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input1_sel = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input1_sel = 2'b10;
                    end
                    else begin
                        input1_sel = 2'b00;
                    end
                    input2_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b001011xxxxxx:
                begin

                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input1_sel = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input1_sel = 2'b10;
                    end
                    else begin
                        input1_sel = 2'b00;
                    end
                    input2_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b001100xxxxxx:
                begin

                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input1_sel = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input1_sel = 2'b10;
                    end
                    else begin
                        input1_sel = 2'b00;
                    end
                    input2_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b001101xxxxxx:
                begin

                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input1_sel = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input1_sel = 2'b10;
                    end
                    else begin
                        input1_sel = 2'b00;
                    end
                    input2_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b001110xxxxxx:
                begin

                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input1_sel = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input1_sel = 2'b10;
                    end
                    else begin
                        input1_sel = 2'b00;
                    end
                    input2_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b000011xxxxxx:
                begin
                    input1_sel = 2'b00;
                    input2_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b000010xxxxxx:
                begin
                    input1_sel = 2'b00;
                    input2_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                default:
                begin
                    input1_sel = 2'b00;
                    input2_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
            endcase
        end
        
endmodule
module Data_Hazard_Handler(

    input Clk,
    input reset,
    

    input [5:0] EX_OpCode,
    input [5:0] EX_Funct,
    input MEM_regWrite,
    input [4:0] MEM_writeReg,
    input WB_regWrite,
    input [4:0] WB_writeReg,
    input [4:0] EX_rs,
    
    output [1:0] Input1_Sel,
    output [1:0] Input2_Sel,
    output [1:0] sw_sel, 
    output [1:0] jr_sel,
    

    input EX_MemRead,
    input [4:0] EX_rt,
    input [31:0] ID_Instr,
    
    output D_Bubble
    );

    
    reg d_bubble;
    
    assign D_Bubble = d_bubble;
    

    always @(ID_Instr or EX_MemRead or EX_rt)
        begin
            if(EX_MemRead == 1 && EX_rt != 0)begin
                casex({ID_Instr[31:26],ID_Instr[5:0]})
                    12'b100011xxxxxx:
                    begin 

                        if(ID_Instr[25:21] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b100100xxxxxx:
                    begin 

                        if(ID_Instr[25:21] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b100101xxxxxx:
                    begin 

                        if(ID_Instr[25:21] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b101011xxxxxx:
                    begin

                        if(ID_Instr[25:21] == EX_rt || ID_Instr[20:16] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b101000xxxxxx:
                    begin

                        if(ID_Instr[25:21] == EX_rt || ID_Instr[20:16] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b101001xxxxxx:
                    begin

                        if(ID_Instr[25:21] == EX_rt || ID_Instr[20:16] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b000100xxxxxx:
                    begin

                        if(ID_Instr[25:21] == EX_rt || ID_Instr[20:16] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b000101xxxxxx:
                    begin

                        if(ID_Instr[25:21] == EX_rt || ID_Instr[20:16] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b000000000000:
                    begin

                        if(ID_Instr[20:16] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b000000000010:
                    begin

                        if(ID_Instr[20:16] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b000000000011:
                    begin

                        if(ID_Instr[20:16] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b000000001000:
                    begin

                        if(ID_Instr[25:21] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b000000xxxxxx:
                    begin

                        if(ID_Instr[25:21] == EX_rt || ID_Instr[20:16] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b001000xxxxxx:
                    begin

                        if(ID_Instr[25:21] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b001001xxxxxx:
                    begin

                        if(ID_Instr[25:21] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b001111xxxxxx:
                    begin
                        d_bubble = 0;
                    end
                    12'b001010xxxxxx:
                    begin

                        if(ID_Instr[25:21] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b001011xxxxxx:
                    begin

                        if(ID_Instr[25:21] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b001100xxxxxx:
                    begin

                        if(ID_Instr[25:21] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b001101xxxxxx:
                    begin

                        if(ID_Instr[25:21] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b001110xxxxxx:
                    begin

                        if(ID_Instr[25:21] == EX_rt) d_bubble = 1;
                        else d_bubble = 0;
                    end
                    12'b000011xxxxxx:
                    begin
                        d_bubble = 0;
                    end
                    12'b000010xxxxxx:
                    begin
                        d_bubble = 0;
                    end
                    default:
                        d_bubble = 0;
                endcase
            end
            else d_bubble = 0;
        end
    
    reg [1:0] input1_sel;
    reg [1:0] input2_sel;
    reg [1:0] sw_sel_reg;
    reg [1:0] jr_sel_reg;
    
    assign Input1_Sel = input1_sel;
    assign Input2_Sel = input2_sel;
    assign sw_sel = sw_sel_reg;
    assign jr_sel = jr_sel_reg;
    

    always @(EX_OpCode, EX_Funct, EX_rs, EX_rt, MEM_regWrite, 
        MEM_writeReg, WB_regWrite, WB_writeReg) 
        begin
            
            casex({EX_OpCode,EX_Funct}) 
                12'b100011xxxxxx:
                begin 

                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input1_sel = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input1_sel = 2'b10;
                    end
                    else begin
                        input1_sel = 2'b00;
                    end
                    input2_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b100100xxxxxx:
                begin 

                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input1_sel = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input1_sel = 2'b10;
                    end
                    else begin
                        input1_sel = 2'b00;
                    end
                    input2_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b100101xxxxxx:
                begin 

                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input1_sel = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input1_sel = 2'b10;
                    end
                    else begin
                        input1_sel = 2'b00;
                    end
                    input2_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b101011xxxxxx:
                begin


                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input1_sel = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input1_sel = 2'b10;
                    end
                    else begin
                        input1_sel = 2'b00;
                    end

                    if(EX_rt == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        sw_sel_reg = 2'b01;
                    end
                    else if(EX_rt == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        sw_sel_reg = 2'b10;
                    end
                    else begin
                        sw_sel_reg = 2'b00;
                    end
                    input2_sel = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b101000xxxxxx:
                begin


                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input1_sel = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input1_sel = 2'b10;
                    end
                    else begin
                        input1_sel = 2'b00;
                    end

                    if(EX_rt == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        sw_sel_reg = 2'b01;
                    end
                    else if(EX_rt == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        sw_sel_reg = 2'b10;
                    end
                    else begin
                        sw_sel_reg = 2'b00;
                    end
                    input2_sel = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b101001xxxxxx:
                begin


                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input1_sel = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input1_sel = 2'b10;
                    end
                    else begin
                        input1_sel = 2'b00;
                    end

                    if(EX_rt == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        sw_sel_reg = 2'b01;
                    end
                    else if(EX_rt == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        sw_sel_reg = 2'b10;
                    end
                    else begin
                        sw_sel_reg = 2'b00;
                    end
                    input2_sel = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b000100xxxxxx:
                begin


                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input1_sel = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input1_sel = 2'b10;
                    end
                    else begin
                        input1_sel = 2'b00;
                    end

                    if(EX_rt == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input2_sel = 2'b01;
                    end
                    else if(EX_rt == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input2_sel = 2'b10;
                    end
                    else begin
                        input2_sel = 2'b00;
                    end
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b000101xxxxxx:
                begin


                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input1_sel = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input1_sel = 2'b10;
                    end
                    else begin
                        input1_sel = 2'b00;
                    end

                    if(EX_rt == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input2_sel = 2'b01;
                    end
                    else if(EX_rt == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input2_sel = 2'b10;
                    end
                    else begin
                        input2_sel = 2'b00;
                    end
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b000000000000:
                begin

                    if(EX_rt == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input2_sel = 2'b01;
                    end
                    else if(EX_rt == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input2_sel = 2'b10;
                    end
                    else begin
                        input2_sel = 2'b00;
                    end
                    input1_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b000000000010:
                begin

                    if(EX_rt == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input2_sel = 2'b01;
                    end
                    else if(EX_rt == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input2_sel = 2'b10;
                    end
                    else begin
                        input2_sel = 2'b00;
                    end
                    input1_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b000000000011:
                begin

                    if(EX_rt == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input2_sel = 2'b01;
                    end
                    else if(EX_rt == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input2_sel = 2'b10;
                    end
                    else begin
                        input2_sel = 2'b00;
                    end
                    input1_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b000000001000:
                begin

                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        jr_sel_reg = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        jr_sel_reg = 2'b10;
                    end
                    else begin
                        jr_sel_reg = 2'b00;
                    end
                    input1_sel = 2'b00;
                    input2_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                end
                12'b000000xxxxxx:
                begin


                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input1_sel = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input1_sel = 2'b10;
                    end
                    else begin
                        input1_sel = 2'b00;
                    end

                    if(EX_rt == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input2_sel = 2'b01;
                    end
                    else if(EX_rt == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input2_sel = 2'b10;
                    end
                    else begin
                        input2_sel = 2'b00;
                    end
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b001000xxxxxx:
                begin

                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input1_sel = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input1_sel = 2'b10;
                    end
                    else begin
                        input1_sel = 2'b00;
                    end
                    input2_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b001001xxxxxx:
                begin

                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input1_sel = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input1_sel = 2'b10;
                    end
                    else begin
                        input1_sel = 2'b00;
                    end
                    input2_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b001111xxxxxx:
                begin
                    input1_sel = 2'b00;
                    input2_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b001010xxxxxx:
                begin

                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input1_sel = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input1_sel = 2'b10;
                    end
                    else begin
                        input1_sel = 2'b00;
                    end
                    input2_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b001011xxxxxx:
                begin

                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input1_sel = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input1_sel = 2'b10;
                    end
                    else begin
                        input1_sel = 2'b00;
                    end
                    input2_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b001100xxxxxx:
                begin

                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input1_sel = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input1_sel = 2'b10;
                    end
                    else begin
                        input1_sel = 2'b00;
                    end
                    input2_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b001101xxxxxx:
                begin

                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input1_sel = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input1_sel = 2'b10;
                    end
                    else begin
                        input1_sel = 2'b00;
                    end
                    input2_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b001110xxxxxx:
                begin

                    if(EX_rs == MEM_writeReg && MEM_regWrite == 1 && MEM_writeReg != 0) begin
                        input1_sel = 2'b01;
                    end
                    else if(EX_rs == WB_writeReg && WB_regWrite == 1 && WB_writeReg != 0) begin
                        input1_sel = 2'b10;
                    end
                    else begin
                        input1_sel = 2'b00;
                    end
                    input2_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b000011xxxxxx:
                begin
                    input1_sel = 2'b00;
                    input2_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                12'b000010xxxxxx:
                begin
                    input1_sel = 2'b00;
                    input2_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
                default:
                begin
                    input1_sel = 2'b00;
                    input2_sel = 2'b00;
                    sw_sel_reg = 2'b00;
                    jr_sel_reg = 2'b00;
                end
            endcase
        end
        
endmodule