data/full_repos/permissive/447976230/fpga/usrp3/top/e320/e320_clocking.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/447976230/fpga/usrp3/top/e320/e320_clocking.v:206: Signal definition not found, creating implicitly: \'locked_sync\'\n                                                                                               : ... Suggested alternative: \'locked_count\'\n      if (~locked_sync) begin\n           ^~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e320/e320_clocking.v:57: Cannot find file containing module: \'IBUFG\'\n  IBUFG ref_clk_ibuf (\n  ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp3/top/e320,data/full_repos/permissive/447976230/IBUFG\n             data/full_repos/permissive/447976230/fpga/usrp3/top/e320,data/full_repos/permissive/447976230/IBUFG.v\n             data/full_repos/permissive/447976230/fpga/usrp3/top/e320,data/full_repos/permissive/447976230/IBUFG.sv\n             IBUFG\n             IBUFG.v\n             IBUFG.sv\n             obj_dir/IBUFG\n             obj_dir/IBUFG.v\n             obj_dir/IBUFG.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e320/e320_clocking.v:62: Cannot find file containing module: \'BUFG\'\n  BUFG ref_clk_bufg (\n  ^~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e320/e320_clocking.v:76: Cannot find file containing module: \'synchronizer\'\n  synchronizer #(\n  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e320/e320_clocking.v:82: Cannot find file containing module: \'synchronizer\'\n  synchronizer #(\n  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e320/e320_clocking.v:91: Cannot find file containing module: \'synchronizer\'\n  synchronizer #(\n  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e320/e320_clocking.v:124: Cannot find file containing module: \'MMCME2_ADV\'\n  MMCME2_ADV #(\n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e320/e320_clocking.v:178: Cannot find file containing module: \'BUFG\'\n  BUFG clk300_bufg\n  ^~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e320/e320_clocking.v:195: Cannot find file containing module: \'synchronizer\'\n  synchronizer lock_sync_i (\n  ^~~~~~~~~~~~\n%Error: Exiting due to 8 error(s), 1 warning(s)\n'
module e320_clocking (
  input global_rst,


  input ref_clk_from_pin,
  output ref_clk,


  input clk156,


  output ddr3_dma_clk,
  output reg clocks_locked = 1'b0,


  input       ext_pps_from_pin,
  input       gps_pps_from_pin,
  input [1:0] pps_select,
  output reg  pps_refclk
);











  wire ref_clk_buf;





  IBUFG ref_clk_ibuf (
    .O(ref_clk_buf),
    .I(ref_clk_from_pin)
  );

  BUFG ref_clk_bufg (
    .I(ref_clk_buf),
    .O(ref_clk)
  );

  wire pps_ext_refclk;
  wire pps_gps_refclk;
  wire [1:0] pps_select_refclk;






  synchronizer #(
    .FALSE_PATH_TO_IN(0)
  ) ext_pps_dsync (
    .clk(ref_clk), .rst(1'b0), .in(ext_pps_from_pin), .out(pps_ext_refclk)
  );

  synchronizer #(
    .FALSE_PATH_TO_IN(0)
  ) gps_pps_dsync (
    .clk(ref_clk), .rst(1'b0), .in(gps_pps_from_pin), .out(pps_gps_refclk)
  );




  synchronizer #(
    .FALSE_PATH_TO_IN(1),
    .WIDTH(2)
  ) pps_select_dsync (
    .clk(ref_clk), .rst(1'b0), .in(pps_select), .out(pps_select_refclk)
  );


  localparam BIT_PPS_SEL_INT = 0;
  localparam BIT_PPS_SEL_EXT = 1;


  always @(posedge ref_clk) begin







    if (pps_select_refclk[BIT_PPS_SEL_INT]) begin
      pps_refclk <= pps_gps_refclk;
    end else if (pps_select_refclk[BIT_PPS_SEL_EXT]) begin
      pps_refclk <= pps_ext_refclk;
    end else begin
      pps_refclk <= pps_gps_refclk;
    end
  end





  MMCME2_ADV #(
    .BANDWIDTH            ("OPTIMIZED"),
    .CLKOUT4_CASCADE      ("FALSE"),
    .COMPENSATION         ("ZHOLD"),
    .STARTUP_WAIT         ("FALSE"),
    .DIVCLK_DIVIDE        (1),
    .CLKFBOUT_MULT_F      (6.000),
    .CLKFBOUT_PHASE       (0.000),
    .CLKFBOUT_USE_FINE_PS ("FALSE"),
    .CLKOUT0_DIVIDE_F     (3.125),
    .CLKOUT0_PHASE        (0.000),
    .CLKOUT0_DUTY_CYCLE   (0.500),
    .CLKOUT0_USE_FINE_PS  ("FALSE"),
    .CLKIN1_PERIOD        (6.400))
  mmcm_adv_inst (
    .CLKFBOUT            (clkfbout),
    .CLKFBOUTB           (),
    .CLKOUT0             (ddr3_dma_clk_raw),
    .CLKOUT0B            (),
    .CLKOUT1             (),
    .CLKOUT1B            (),
    .CLKOUT2             (),
    .CLKOUT2B            (),
    .CLKOUT3             (),
    .CLKOUT3B            (),
    .CLKOUT4             (),
    .CLKOUT5             (),
    .CLKOUT6             (),

    .CLKFBIN             (clkfbout),
    .CLKIN1              (clk156),
    .CLKIN2              (1'b0),

    .CLKINSEL            (1'b1),

    .DADDR               (7'h0),
    .DCLK                (1'b0),
    .DEN                 (1'b0),
    .DI                  (16'h0),
    .DO                  (),
    .DRDY                (),
    .DWE                 (1'b0),

    .PSCLK               (1'b0),
    .PSEN                (1'b0),
    .PSINCDEC            (1'b0),
    .PSDONE              (),

    .LOCKED              (locked_raw),
    .CLKINSTOPPED        (),
    .CLKFBSTOPPED        (),
    .PWRDWN              (1'b0),
    .RST                 (global_rst));

  BUFG clk300_bufg
     (.O   (ddr3_dma_clk),
      .I   (ddr3_dma_clk_raw));












  reg [9:0] locked_count = ~0;

  synchronizer lock_sync_i (
    .clk(clk156), .rst(1'b0), .in(locked_raw), .out(locked_sync)
  );


  always @(posedge clk156 or posedge global_rst)
  begin
    if (global_rst) begin
      locked_count  <= ~0;
      clocks_locked <=  0;
    end else begin
      if (~locked_sync) begin
        locked_count  <= ~0;
        clocks_locked <= 1'b0;
      end else begin
        if (locked_count == 0) begin
          clocks_locked <= 1'b1;
        end else begin
          clocks_locked <= 1'b0;
          locked_count <= locked_count - 1;
        end
      end
    end
  end

endmodule
module e320_clocking (
  input global_rst,


  input ref_clk_from_pin,
  output ref_clk,


  input clk156,


  output ddr3_dma_clk,
  output reg clocks_locked = 1'b0,


  input       ext_pps_from_pin,
  input       gps_pps_from_pin,
  input [1:0] pps_select,
  output reg  pps_refclk
);












  wire ref_clk_buf;





  IBUFG ref_clk_ibuf (
    .O(ref_clk_buf),
    .I(ref_clk_from_pin)
  );

  BUFG ref_clk_bufg (
    .I(ref_clk_buf),
    .O(ref_clk)
  );

  wire pps_ext_refclk;
  wire pps_gps_refclk;
  wire [1:0] pps_select_refclk;






  synchronizer #(
    .FALSE_PATH_TO_IN(0)
  ) ext_pps_dsync (
    .clk(ref_clk), .rst(1'b0), .in(ext_pps_from_pin), .out(pps_ext_refclk)
  );

  synchronizer #(
    .FALSE_PATH_TO_IN(0)
  ) gps_pps_dsync (
    .clk(ref_clk), .rst(1'b0), .in(gps_pps_from_pin), .out(pps_gps_refclk)
  );




  synchronizer #(
    .FALSE_PATH_TO_IN(1),
    .WIDTH(2)
  ) pps_select_dsync (
    .clk(ref_clk), .rst(1'b0), .in(pps_select), .out(pps_select_refclk)
  );


  localparam BIT_PPS_SEL_INT = 0;
  localparam BIT_PPS_SEL_EXT = 1;


  always @(posedge ref_clk) begin







    if (pps_select_refclk[BIT_PPS_SEL_INT]) begin
      pps_refclk <= pps_gps_refclk;
    end else if (pps_select_refclk[BIT_PPS_SEL_EXT]) begin
      pps_refclk <= pps_ext_refclk;
    end else begin
      pps_refclk <= pps_gps_refclk;
    end
  end





  MMCME2_ADV #(
    .BANDWIDTH            ("OPTIMIZED"),
    .CLKOUT4_CASCADE      ("FALSE"),
    .COMPENSATION         ("ZHOLD"),
    .STARTUP_WAIT         ("FALSE"),
    .DIVCLK_DIVIDE        (1),
    .CLKFBOUT_MULT_F      (6.000),
    .CLKFBOUT_PHASE       (0.000),
    .CLKFBOUT_USE_FINE_PS ("FALSE"),
    .CLKOUT0_DIVIDE_F     (3.125),
    .CLKOUT0_PHASE        (0.000),
    .CLKOUT0_DUTY_CYCLE   (0.500),
    .CLKOUT0_USE_FINE_PS  ("FALSE"),
    .CLKIN1_PERIOD        (6.400))
  mmcm_adv_inst (
    .CLKFBOUT            (clkfbout),
    .CLKFBOUTB           (),
    .CLKOUT0             (ddr3_dma_clk_raw),
    .CLKOUT0B            (),
    .CLKOUT1             (),
    .CLKOUT1B            (),
    .CLKOUT2             (),
    .CLKOUT2B            (),
    .CLKOUT3             (),
    .CLKOUT3B            (),
    .CLKOUT4             (),
    .CLKOUT5             (),
    .CLKOUT6             (),

    .CLKFBIN             (clkfbout),
    .CLKIN1              (clk156),
    .CLKIN2              (1'b0),

    .CLKINSEL            (1'b1),

    .DADDR               (7'h0),
    .DCLK                (1'b0),
    .DEN                 (1'b0),
    .DI                  (16'h0),
    .DO                  (),
    .DRDY                (),
    .DWE                 (1'b0),

    .PSCLK               (1'b0),
    .PSEN                (1'b0),
    .PSINCDEC            (1'b0),
    .PSDONE              (),

    .LOCKED              (locked_raw),
    .CLKINSTOPPED        (),
    .CLKFBSTOPPED        (),
    .PWRDWN              (1'b0),
    .RST                 (global_rst));

  BUFG clk300_bufg
     (.O   (ddr3_dma_clk),
      .I   (ddr3_dma_clk_raw));












  reg [9:0] locked_count = ~0;

  synchronizer lock_sync_i (
    .clk(clk156), .rst(1'b0), .in(locked_raw), .out(locked_sync)
  );


  always @(posedge clk156 or posedge global_rst)
  begin
    if (global_rst) begin
      locked_count  <= ~0;
      clocks_locked <=  0;
    end else begin
      if (~locked_sync) begin
        locked_count  <= ~0;
        clocks_locked <= 1'b0;
      end else begin
        if (locked_count == 0) begin
          clocks_locked <= 1'b1;
        end else begin
          clocks_locked <= 1'b0;
          locked_count <= locked_count - 1;
        end
      end
    end
  end

endmodule