data/full_repos/permissive/531216051/verilog/rtl/BtcMinerUart.v
1: b"%Error: data/full_repos/permissive/531216051/verilog/rtl/BtcMinerUart.v:23: Cannot find file containing module: 'UartCore'\nUartCore u_UartCore (\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/531216051/verilog/rtl,data/full_repos/permissive/531216051/UartCore\n             data/full_repos/permissive/531216051/verilog/rtl,data/full_repos/permissive/531216051/UartCore.v\n             data/full_repos/permissive/531216051/verilog/rtl,data/full_repos/permissive/531216051/UartCore.sv\n             UartCore\n             UartCore.v\n             UartCore.sv\n             obj_dir/UartCore\n             obj_dir/UartCore.v\n             obj_dir/UartCore.sv\n%Error: data/full_repos/permissive/531216051/verilog/rtl/BtcMinerUart.v:43: Cannot find file containing module: 'BaudRateGenerator'\nBaudRateGenerator #(\n^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module BtcMinerUart (
    input  clk,
    input  rst,
    input  uart_rx,
    output uart_tx,

    input  [31:0] wbRData,
    input         wbAck,
    input         wbErr,
    input         wbRty,
    output        wbRst,
    output [ 7:0] wbAddr,
    output [ 3:0] wbSel,
    output        wbWe,
    output [31:0] wbWData,
    output        wbCycle,
    output        wbStrobe,
    output [ 2:0] wbCti,
    output [ 1:0] wbBte

);

UartCore u_UartCore (
  .ck                 (clk),
  .rst                (rst),
  .brgTick            (brgTick),
  .brgOversample8     (brg_oversample),
  .txData             (txData),
  .startTx            (startTx),
  .txReady            (txReady),
  .rxData             (rxData),
  .rxReady            (rxReady),
  .rxParityError      (rxParityError),
  .rxProtocolError    (rxProtocolError),
  .clearFlags         (clearFlags),
  .uartRx_a           (uart_rx),
  .uartTx             (uart_tx)
);

localparam BRG_DIV_FACTOR = 100_000_000 / 115_200;
localparam BRG_COUNTER_WIDTH = $clog2(BRG_DIV_FACTOR);

BaudRateGenerator #(

  .COUNTER_WIDTH    (BRG_COUNTER_WIDTH)
) u_BaudRateGenerator (
  .ck               (clk),
  .arst_n           (1'b1),
  .rst_n            (~rst),
  .divFactor        (BRG_DIV_FACTOR),
  .tick             (brg_tick),
  .tick_inv         (),
  .oversample8      (brg_oversample)
);
endmodule
module BtcMinerUart (
    input  clk,
    input  rst,
    input  uart_rx,
    output uart_tx,

    input  [31:0] wbRData,
    input         wbAck,
    input         wbErr,
    input         wbRty,
    output        wbRst,
    output [ 7:0] wbAddr,
    output [ 3:0] wbSel,
    output        wbWe,
    output [31:0] wbWData,
    output        wbCycle,
    output        wbStrobe,
    output [ 2:0] wbCti,
    output [ 1:0] wbBte

);


UartCore u_UartCore (
  .ck                 (clk),
  .rst                (rst),
  .brgTick            (brgTick),
  .brgOversample8     (brg_oversample),
  .txData             (txData),
  .startTx            (startTx),
  .txReady            (txReady),
  .rxData             (rxData),
  .rxReady            (rxReady),
  .rxParityError      (rxParityError),
  .rxProtocolError    (rxProtocolError),
  .clearFlags         (clearFlags),
  .uartRx_a           (uart_rx),
  .uartTx             (uart_tx)
);

localparam BRG_DIV_FACTOR = 100_000_000 / 115_200;
localparam BRG_COUNTER_WIDTH = $clog2(BRG_DIV_FACTOR);

BaudRateGenerator #(

  .COUNTER_WIDTH    (BRG_COUNTER_WIDTH)
) u_BaudRateGenerator (
  .ck               (clk),
  .arst_n           (1'b1),
  .rst_n            (~rst),
  .divFactor        (BRG_DIV_FACTOR),
  .tick             (brg_tick),
  .tick_inv         (),
  .oversample8      (brg_oversample)
);
endmodule