data/full_repos/permissive/474582223/Decoder/twobyFour/tf.v
1: b'%Error: data/full_repos/permissive/474582223/Decoder/twobyFour/tf.v:31: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("dump.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/474582223/Decoder/twobyFour/tf.v:32: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(1);  \n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/474582223/Decoder/twobyFour/tf.v:37: Unsupported: Ignoring delay on this delayed statement.\n       #100;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/474582223/Decoder/twobyFour/tf.v:42: Unsupported: Ignoring delay on this delayed statement.\n       #100;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/474582223/Decoder/twobyFour/tf.v:47: Unsupported: Ignoring delay on this delayed statement.\n       #100;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/474582223/Decoder/twobyFour/tf.v:52: Unsupported: Ignoring delay on this delayed statement.\n       #100;\n       ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module decodertt;


	reg A1;
	reg A0;
  	reg en;


	wire D3;
  	wire D2;
  	wire D1;
  	wire D0;


	decoder uut (
      .A1(A1),
      .A0(A0),
      .en(en),
      .D3(D3),
      .D2(D2),
      .D1(D1),
      .D0(D0)
	);

	initial begin
      $dumpfile("dump.vcd");
      $dumpvars(1);

      	A0 = 0;
		A1 = 0;
      	en = 1;
      	#100;
      
      	A0 = 0;
		A1 = 1;
      	en = 1;
      	#100;
        
      	A0 = 1;
		A1 = 0;
      	en = 1;
      	#100;
      
      	A0 = 1;
		A1 = 1;
      	en = 1;
      	#100;
	end
endmodule
module decodertt;



	reg A1;
	reg A0;
  	reg en;


	wire D3;
  	wire D2;
  	wire D1;
  	wire D0;


	decoder uut (
      .A1(A1),
      .A0(A0),
      .en(en),
      .D3(D3),
      .D2(D2),
      .D1(D1),
      .D0(D0)
	);

	initial begin
      $dumpfile("dump.vcd");
      $dumpvars(1);

      	A0 = 0;
		A1 = 0;
      	en = 1;
      	#100;
      
      	A0 = 0;
		A1 = 1;
      	en = 1;
      	#100;
        
      	A0 = 1;
		A1 = 0;
      	en = 1;
      	#100;
      
      	A0 = 1;
		A1 = 1;
      	en = 1;
      	#100;
	end
endmodule