data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_hdl_models_mux_using_case.v
data/verilator_xmls/e3c16b64-9d1a-4cd5-9392-ba9cab6da5c1.xml
module  mux_using_case(
din_0      ,
din_1      ,
sel           ,
mux_out
);

input din_0, din_1, sel ;

output mux_out;

reg  mux_out;

always @ (sel or din_0 or din_1)
begin : MUX
 case(sel ) 
    1'b0 : mux_out = din_0;
    1'b1 : mux_out = din_1;
 endcase 
end

endmodule
module  mux_using_case(
din_0      ,
din_1      ,
sel           ,
mux_out
);


input din_0, din_1, sel ;

output mux_out;

reg  mux_out;

always @ (sel or din_0 or din_1)
begin : MUX
 case(sel ) 
    1'b0 : mux_out = din_0;
    1'b1 : mux_out = din_1;
 endcase 
end

endmodule