data/full_repos/permissive/463439324/decap/r3_mul_32.v
1: b'%Warning-WIDTH: data/full_repos/permissive/463439324/decap/r3_mul_32.v:101: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 65 bits.\n                                                                          : ... In instance r3_mul_32\nassign DO_0 = {2\'b00,c0[31:0],c0[62:32]};\n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/463439324/decap/r3_mul_32.v:102: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 65 bits.\n                                                                          : ... In instance r3_mul_32\nassign DO_1 = {2\'b00,c1[31:0],c1[62:32]};\n            ^\n%Error: data/full_repos/permissive/463439324/decap/r3_mul_32.v:139: Cannot find file containing module: \'f0_times_g0\'\n  f0_times_g0 f0_times_g0_(\n  ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463439324/decap,data/full_repos/permissive/463439324/f0_times_g0\n             data/full_repos/permissive/463439324/decap,data/full_repos/permissive/463439324/f0_times_g0.v\n             data/full_repos/permissive/463439324/decap,data/full_repos/permissive/463439324/f0_times_g0.sv\n             f0_times_g0\n             f0_times_g0.v\n             f0_times_g0.sv\n             obj_dir/f0_times_g0\n             obj_dir/f0_times_g0.v\n             obj_dir/f0_times_g0.sv\n%Error: data/full_repos/permissive/463439324/decap/r3_mul_32.v:154: Cannot find file containing module: \'f0_adds_g0\'\n  f0_adds_g0 f0_adds_g0_(\n  ^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module r3_mul_32(clk,rst,in_ready,DI_F0,DI_F1,DI_G0,DI_G1,DO_0,DO_1,valid);

input clk;
input rst;
input in_ready;
input [31:0] DI_F0;
input [31:0] DI_F1;
input [31:0] DI_G0;
input [31:0] DI_G1;

output [63:0] DO_0;
output [63:0] DO_1;
output valid;




reg [31:0] f0;
reg [31:0] f1;
reg [31:0] g0;
reg [31:0] g1;
wire [31:0] f0_w;
wire [31:0] f1_w;
wire [31:0] g0_w;
wire [31:0] g1_w;

wire [31:0] m0;
wire [31:0] m1;

reg [62:0] c0;
reg [62:0] c1;
wire [62:0] c0_w;
wire [62:0] c1_w;

reg [9:0] counter;
wire [9:0] counter_w;

reg [1:0] state;
reg [1:0] state_n;

wire [30:0] a0_in, a1_in;
wire [30:0] a0_out, a1_out;

parameter init = 2'd0, mulstep = 2'd1, finish = 2'd2;
genvar i;


assign counter_w = (state == mulstep || state == finish) ? counter + 1 : 0;


assign f0_w = (state == init && in_ready == 1) ? DI_F0 : f0;
assign f1_w = (state == init && in_ready == 1) ? DI_F1 : f1;
assign g0_w = (state == init && in_ready == 1) ? DI_G0 : 
			  (state == mulstep) ? (g0>>1) : 
			  g0;
assign g1_w = (state == init && in_ready == 1) ? DI_G1 : 
			  (state == mulstep) ? (g1>>1) : 
			  g1;
			  

assign a0_in = m0[30:0];
assign a1_in = m1[30:0];
			   

assign c0_w[0] = (state == init) ? 0 : (state == mulstep) ? a0_out[0] : c0[0];
assign c0_w[30:1] = (state == init) ? 0 : (state == mulstep) ? a0_out[30:1] : c0[30:1];
assign c0_w[31] = (state == init) ? 0 : (state == mulstep) ? m0[31] : c0[31];
assign c0_w[32] = (state == init) ? 0 : (state == mulstep) ? c0[33] : c0[32];
assign c0_w[62:33] = (state == init) ? 0 : (state == mulstep) ? {c0[0],c0[62:34]} : c0[62:33];
						

assign c1_w[0] = (state == init) ? 0 : (state == mulstep) ? a1_out[0] : c1[0];
assign c1_w[30:1] = (state == init) ? 0 : (state == mulstep) ? a1_out[30:1] : c1[30:1];
assign c1_w[31] = (state == init) ? 0 : (state == mulstep) ? m1[31] : c1[31];
assign c1_w[32] = (state == init) ? 0 : (state == mulstep) ? c1[33] : c1[32];
assign c1_w[62:33] = (state == init) ? 0 : (state == mulstep) ? {c1[0],c1[62:34]} :	c1[62:33];
						

assign DO_0 = {2'b00,c0[31:0],c0[62:32]};
assign DO_1 = {2'b00,c1[31:0],c1[62:32]};
assign valid = (state == finish) ? 1 : 0;


always@(*)
begin
	case(state)
	init:
	begin
		if(in_ready == 1)
			state_n = mulstep;
		else
			state_n = init;
	end
	mulstep:
	begin
		if(counter == 10'd31)
			state_n = finish;
		else
			state_n = mulstep;
	end
	finish:
	begin
		if(counter == 10'd35)
			state_n = init;
		else
			state_n = finish;
	end
	default:
		state_n = init;
	endcase
end


generate
	for(i = 0; i < 32; i = i + 1)
	begin : ccc
		f0_times_g0 f0_times_g0_(
			.f0(f0[i]),
			.f1(f1[i]),
			.g0(g0[0]),
			.g1(g1[0]),
			.c0(m0[i]),
			.c1(m1[i])
			);
	end
endgenerate	


generate
	for(i = 0; i < 31; i = i + 1)
	begin : ddd
		f0_adds_g0 f0_adds_g0_(
			.f0(a0_in[i]),
			.f1(a1_in[i]),
			.g0(c0[i+1]),
			.g1(c1[i+1]),
			.c0(a0_out[i]),
			.c1(a1_out[i])
			);
	end
endgenerate


always@(posedge clk)
begin
	if(rst == 1)
	begin
		counter <= 0;
		state <= init;
		f0 <= 0;
		f1 <= 0;
		g0 <= 0;
		g1 <= 0;
		c0 <= 0;
		c1 <= 0;
	end
	else
	begin
		counter <= counter_w;
		state <= state_n;
		f0 <= f0_w;
		f1 <= f1_w;
		g0 <= g0_w;
		g1 <= g1_w;
		c0 <= c0_w;
		c1 <= c1_w;
	end
end	

endmodule
module r3_mul_32(clk,rst,in_ready,DI_F0,DI_F1,DI_G0,DI_G1,DO_0,DO_1,valid);


input clk;
input rst;
input in_ready;
input [31:0] DI_F0;
input [31:0] DI_F1;
input [31:0] DI_G0;
input [31:0] DI_G1;

output [63:0] DO_0;
output [63:0] DO_1;
output valid;




reg [31:0] f0;
reg [31:0] f1;
reg [31:0] g0;
reg [31:0] g1;
wire [31:0] f0_w;
wire [31:0] f1_w;
wire [31:0] g0_w;
wire [31:0] g1_w;

wire [31:0] m0;
wire [31:0] m1;

reg [62:0] c0;
reg [62:0] c1;
wire [62:0] c0_w;
wire [62:0] c1_w;

reg [9:0] counter;
wire [9:0] counter_w;

reg [1:0] state;
reg [1:0] state_n;

wire [30:0] a0_in, a1_in;
wire [30:0] a0_out, a1_out;

parameter init = 2'd0, mulstep = 2'd1, finish = 2'd2;
genvar i;


assign counter_w = (state == mulstep || state == finish) ? counter + 1 : 0;


assign f0_w = (state == init && in_ready == 1) ? DI_F0 : f0;
assign f1_w = (state == init && in_ready == 1) ? DI_F1 : f1;
assign g0_w = (state == init && in_ready == 1) ? DI_G0 : 
			  (state == mulstep) ? (g0>>1) : 
			  g0;
assign g1_w = (state == init && in_ready == 1) ? DI_G1 : 
			  (state == mulstep) ? (g1>>1) : 
			  g1;
			  

assign a0_in = m0[30:0];
assign a1_in = m1[30:0];
			   

assign c0_w[0] = (state == init) ? 0 : (state == mulstep) ? a0_out[0] : c0[0];
assign c0_w[30:1] = (state == init) ? 0 : (state == mulstep) ? a0_out[30:1] : c0[30:1];
assign c0_w[31] = (state == init) ? 0 : (state == mulstep) ? m0[31] : c0[31];
assign c0_w[32] = (state == init) ? 0 : (state == mulstep) ? c0[33] : c0[32];
assign c0_w[62:33] = (state == init) ? 0 : (state == mulstep) ? {c0[0],c0[62:34]} : c0[62:33];
						

assign c1_w[0] = (state == init) ? 0 : (state == mulstep) ? a1_out[0] : c1[0];
assign c1_w[30:1] = (state == init) ? 0 : (state == mulstep) ? a1_out[30:1] : c1[30:1];
assign c1_w[31] = (state == init) ? 0 : (state == mulstep) ? m1[31] : c1[31];
assign c1_w[32] = (state == init) ? 0 : (state == mulstep) ? c1[33] : c1[32];
assign c1_w[62:33] = (state == init) ? 0 : (state == mulstep) ? {c1[0],c1[62:34]} :	c1[62:33];
						

assign DO_0 = {2'b00,c0[31:0],c0[62:32]};
assign DO_1 = {2'b00,c1[31:0],c1[62:32]};
assign valid = (state == finish) ? 1 : 0;


always@(*)
begin
	case(state)
	init:
	begin
		if(in_ready == 1)
			state_n = mulstep;
		else
			state_n = init;
	end
	mulstep:
	begin
		if(counter == 10'd31)
			state_n = finish;
		else
			state_n = mulstep;
	end
	finish:
	begin
		if(counter == 10'd35)
			state_n = init;
		else
			state_n = finish;
	end
	default:
		state_n = init;
	endcase
end


generate
	for(i = 0; i < 32; i = i + 1)
	begin : ccc
		f0_times_g0 f0_times_g0_(
			.f0(f0[i]),
			.f1(f1[i]),
			.g0(g0[0]),
			.g1(g1[0]),
			.c0(m0[i]),
			.c1(m1[i])
			);
	end
endgenerate	


generate
	for(i = 0; i < 31; i = i + 1)
	begin : ddd
		f0_adds_g0 f0_adds_g0_(
			.f0(a0_in[i]),
			.f1(a1_in[i]),
			.g0(c0[i+1]),
			.g1(c1[i+1]),
			.c0(a0_out[i]),
			.c1(a1_out[i])
			);
	end
endgenerate


always@(posedge clk)
begin
	if(rst == 1)
	begin
		counter <= 0;
		state <= init;
		f0 <= 0;
		f1 <= 0;
		g0 <= 0;
		g1 <= 0;
		c0 <= 0;
		c1 <= 0;
	end
	else
	begin
		counter <= counter_w;
		state <= state_n;
		f0 <= f0_w;
		f1 <= f1_w;
		g0 <= g0_w;
		g1 <= g1_w;
		c0 <= c0_w;
		c1 <= c1_w;
	end
end	

endmodule