data/full_repos/permissive/471089853/src/rightshiftersticky8_by_max_8_f400_uid24.v
data/verilator_xmls/f48d0b2f-a3d1-407c-96e4-4f81ae6ea053.xml
module RightShifterSticky8_by_max_8_F400_uid24(clk, X, S, padBit, R, Sticky);
  reg [3:0] _00_;
  wire _01_;
  wire _02_;
  wire _03_;
  wire [7:0] _04_;
  wire _05_;
  wire _06_;
  wire _07_;
  wire _08_;
  wire _09_;
  wire [7:0] _10_;
  reg [3:0] _11_;
  wire _12_;
  wire _13_;
  wire _14_;
  wire _15_;
  wire _16_;
  wire [7:0] _17_;
  wire _18_;
  wire _19_;
  wire _20_;
  wire _21_;
  reg _22_;
  wire _23_;
  wire [7:0] _24_;
  reg [7:0] _25_;
  reg [7:0] _26_;
  reg _27_;
  reg [7:0] _28_;
  reg [7:0] _29_;
  wire _30_;
  output [7:0] R;
  input [3:0] S;
  output Sticky;
  input [7:0] X;
  input clk;
  wire [7:0] level0;
  wire [7:0] level1;
  wire [7:0] level1_d1;
  wire [7:0] level1_d2;
  wire [7:0] level2;
  wire [7:0] level2_d1;
  wire [7:0] level3;
  wire [7:0] level3_d1;
  wire [7:0] level4;
  input padBit;
  wire [3:0] ps;
  wire [3:0] ps_d1;
  wire [3:0] ps_d2;
  wire stk0;
  wire stk1;
  wire stk1_d1;
  wire stk2;
  wire stk3;
  wire stk3_d1;
  always @(posedge clk)
    _00_ <= ps;
  always @(posedge clk)
    _11_ <= ps_d1;
  always @(posedge clk)
    _22_ <= stk3;
  always @(posedge clk)
    _25_ <= level3;
  always @(posedge clk)
    _26_ <= level2;
  always @(posedge clk)
    _27_ <= stk1;
  always @(posedge clk)
    _28_ <= level1;
  always @(posedge clk)
    _29_ <= level1_d1;
  assign _30_ = level4 != 8'h00;
  assign _01_ = _30_ & ps[3];
  assign _02_ = _01_ ? 1'h1 : 1'h0;
  assign _03_ = ~ ps[3];
  assign _04_ = _03_ ? level4 : { padBit, padBit, padBit, padBit, padBit, padBit, padBit, padBit };
  assign _05_ = level3_d1[3:0] != 4'h0;
  assign _06_ = _05_ & ps_d1[2];
  assign _07_ = _06_ | stk3_d1;
  assign _08_ = _07_ ? 1'h1 : 1'h0;
  assign _09_ = ~ ps[2];
  assign _10_ = _09_ ? level3 : { padBit, padBit, padBit, padBit, level3[7:4] };
  assign _12_ = level2_d1[1:0] != 2'h0;
  assign _13_ = _12_ & ps_d1[1];
  assign _14_ = _13_ | stk2;
  assign _15_ = _14_ ? 1'h1 : 1'h0;
  assign _16_ = ~ ps[1];
  assign _17_ = _16_ ? level2 : { padBit, padBit, level2[7:2] };
  assign _18_ = level1_d2[0] != 1'h0;
  assign _19_ = _18_ & ps_d2[0];
  assign _20_ = _19_ | stk1_d1;
  assign _21_ = _20_ ? 1'h1 : 1'h0;
  assign _23_ = ~ ps[0];
  assign _24_ = _23_ ? level1 : { padBit, level1[7:1] };
  assign ps = S;
  assign ps_d1 = _00_;
  assign ps_d2 = _11_;
  assign level4 = X;
  assign stk3 = _02_;
  assign stk3_d1 = _22_;
  assign level3 = _04_;
  assign level3_d1 = _25_;
  assign stk2 = _08_;
  assign level2 = _10_;
  assign level2_d1 = _26_;
  assign stk1 = _15_;
  assign stk1_d1 = _27_;
  assign level1 = _17_;
  assign level1_d1 = _28_;
  assign level1_d2 = _29_;
  assign stk0 = _21_;
  assign level0 = _24_;
  assign R = level0;
  assign Sticky = stk0;
endmodule
module RightShifterSticky8_by_max_8_F400_uid24(clk, X, S, padBit, R, Sticky);

  reg [3:0] _00_;
  wire _01_;
  wire _02_;
  wire _03_;
  wire [7:0] _04_;
  wire _05_;
  wire _06_;
  wire _07_;
  wire _08_;
  wire _09_;
  wire [7:0] _10_;
  reg [3:0] _11_;
  wire _12_;
  wire _13_;
  wire _14_;
  wire _15_;
  wire _16_;
  wire [7:0] _17_;
  wire _18_;
  wire _19_;
  wire _20_;
  wire _21_;
  reg _22_;
  wire _23_;
  wire [7:0] _24_;
  reg [7:0] _25_;
  reg [7:0] _26_;
  reg _27_;
  reg [7:0] _28_;
  reg [7:0] _29_;
  wire _30_;
  output [7:0] R;
  input [3:0] S;
  output Sticky;
  input [7:0] X;
  input clk;
  wire [7:0] level0;
  wire [7:0] level1;
  wire [7:0] level1_d1;
  wire [7:0] level1_d2;
  wire [7:0] level2;
  wire [7:0] level2_d1;
  wire [7:0] level3;
  wire [7:0] level3_d1;
  wire [7:0] level4;
  input padBit;
  wire [3:0] ps;
  wire [3:0] ps_d1;
  wire [3:0] ps_d2;
  wire stk0;
  wire stk1;
  wire stk1_d1;
  wire stk2;
  wire stk3;
  wire stk3_d1;
  always @(posedge clk)
    _00_ <= ps;
  always @(posedge clk)
    _11_ <= ps_d1;
  always @(posedge clk)
    _22_ <= stk3;
  always @(posedge clk)
    _25_ <= level3;
  always @(posedge clk)
    _26_ <= level2;
  always @(posedge clk)
    _27_ <= stk1;
  always @(posedge clk)
    _28_ <= level1;
  always @(posedge clk)
    _29_ <= level1_d1;
  assign _30_ = level4 != 8'h00;
  assign _01_ = _30_ & ps[3];
  assign _02_ = _01_ ? 1'h1 : 1'h0;
  assign _03_ = ~ ps[3];
  assign _04_ = _03_ ? level4 : { padBit, padBit, padBit, padBit, padBit, padBit, padBit, padBit };
  assign _05_ = level3_d1[3:0] != 4'h0;
  assign _06_ = _05_ & ps_d1[2];
  assign _07_ = _06_ | stk3_d1;
  assign _08_ = _07_ ? 1'h1 : 1'h0;
  assign _09_ = ~ ps[2];
  assign _10_ = _09_ ? level3 : { padBit, padBit, padBit, padBit, level3[7:4] };
  assign _12_ = level2_d1[1:0] != 2'h0;
  assign _13_ = _12_ & ps_d1[1];
  assign _14_ = _13_ | stk2;
  assign _15_ = _14_ ? 1'h1 : 1'h0;
  assign _16_ = ~ ps[1];
  assign _17_ = _16_ ? level2 : { padBit, padBit, level2[7:2] };
  assign _18_ = level1_d2[0] != 1'h0;
  assign _19_ = _18_ & ps_d2[0];
  assign _20_ = _19_ | stk1_d1;
  assign _21_ = _20_ ? 1'h1 : 1'h0;
  assign _23_ = ~ ps[0];
  assign _24_ = _23_ ? level1 : { padBit, level1[7:1] };
  assign ps = S;
  assign ps_d1 = _00_;
  assign ps_d2 = _11_;
  assign level4 = X;
  assign stk3 = _02_;
  assign stk3_d1 = _22_;
  assign level3 = _04_;
  assign level3_d1 = _25_;
  assign stk2 = _08_;
  assign level2 = _10_;
  assign level2_d1 = _26_;
  assign stk1 = _15_;
  assign stk1_d1 = _27_;
  assign level1 = _17_;
  assign level1_d1 = _28_;
  assign level1_d2 = _29_;
  assign stk0 = _21_;
  assign level0 = _24_;
  assign R = level0;
  assign Sticky = stk0;
endmodule