data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_lbin.v
1: b'%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_lbin.v:135: Cannot find file containing module: \'fflopxe\'\nfflopxe #(2) ffrxlbsyn (rxclk, rxrst_, (rx_ival & (!rx_idv)), \n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core,data/full_repos/permissive/530013823/fflopxe\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core,data/full_repos/permissive/530013823/fflopxe.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core,data/full_repos/permissive/530013823/fflopxe.sv\n             fflopxe\n             fflopxe.v\n             fflopxe.sv\n             obj_dir/fflopxe\n             obj_dir/fflopxe.v\n             obj_dir/fflopxe.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_lbin.v:139: Cannot find file containing module: \'fflopxe\'\nfflopxe #(2) ffrx2txlbsyn (txclk, txrst_, (tx_ival & (!tx_ien)), \n^~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_lbin.v:144: Cannot find file containing module: \'fflopxe\'\nfflopxe #(2) fftxlbsyn (txclk, txrst_, (tx_ival & (!tx_ien)), \n^~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_lbin.v:148: Cannot find file containing module: \'fflopxe\'\nfflopxe #(2) fftx2rxlbsyn (rxclk, rxrst_, (rx_oval & (!rx_odv)), \n^~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_lbin.v:166: Cannot find file containing module: \'fflopxe\'\nfflopxe #(1) fftxien (txclk, txrst_, tx_ival, tx_ien, tx_ien_1);\n^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_lbin.v:177: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                                                                                                    : ... In instance ipsmacge_lbin\n        lbin_datipg <= 9\'b0;\n                    ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_lbin.v:181: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 9 bits.\n                                                                                                                                                    : ... In instance ipsmacge_lbin\n        lbin_datipg <= {tx_ier,tx_idat};\n                    ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_lbin.v:205: Cannot find file containing module: \'fflopx\'\nfflopx #(2) fflbinnotemp (rxclk, rxrst_, {lbin_rnotempty,  lbin_rnotempty1},\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_lbin.v:247: Cannot find file containing module: \'ipsmacge_delay_k_clk\'\nipsmacge_delay_k_clk #(2) fflbinrdok (rxclk, rxrst_, lbin_read, lbin_rdok);\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_lbin.v:294: Cannot find file containing module: \'convclk_grayffctrl\'\nconvclk_grayffctrl #(LBIN_AW, LBIN_LW) igrayffctrl\n^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s), 2 warning(s)\n'
module ipsmacge_lbin
    (

     rxrst_,
     rxclk,

     rx_idat,
     rx_idv,
     rx_ier,
     rx_ival,

     rx_odat,
     rx_odv,
     rx_oer,
     rx_oval,

     txclk,
     txrst_,

     tx_idat,
     tx_ien,
     tx_ier,
     tx_ival,

     lbin_fifowrerr,
     lbin_fiforderr,

     uplbin,
     upfifofsh,
     uplbffnum,

     lbin_wdat,
     lbin_wena,
     lbin_wadd,
     
     lbin_rdat,
     lbin_rena,
     lbin_radd
     );



parameter LBIN_AW = 4,
          LBIN_LW = 16,
          LBIN_DW = 10;



input           rxrst_;
input           rxclk;

input [7:0]     rx_idat;
input           rx_idv;
input           rx_ier;
input           rx_ival;

output [7:0]    rx_odat;
output          rx_odv;
output          rx_oer;
output          rx_oval;

input           txclk;
input           txrst_;

input [7:0]     tx_idat;
input           tx_ien;
input           tx_ier;
input           tx_ival;

output          lbin_fifowrerr;
output          lbin_fiforderr;


input           uplbin;
input           upfifofsh;
input [3:0]     uplbffnum;

input  [LBIN_DW-1:0] lbin_rdat;
output               lbin_rena;
output [LBIN_AW-1:0] lbin_radd;

output [LBIN_DW-1:0] lbin_wdat;
output               lbin_wena;
output [LBIN_AW-1:0] lbin_wadd;


reg [7:0]       rx_odat;
reg             rx_odv;
reg             rx_oer;
reg             rx_oval;
























wire      rx_synlbin_meta, rx_synlbin;
wire      rx2tx_synlbin_meta, rx2tx_synlbin;

wire      tx_synlbin_meta, tx_synlbin;
wire      tx2rx_synlbin_meta, tx2rx_synlbin;


fflopxe #(2) ffrxlbsyn (rxclk, rxrst_, (rx_ival & (!rx_idv)), 
                        {uplbin         , rx_synlbin_meta}, 
                        {rx_synlbin_meta, rx_synlbin});

fflopxe #(2) ffrx2txlbsyn (txclk, txrst_, (tx_ival & (!tx_ien)), 
                           {rx_synlbin          , rx2tx_synlbin_meta}, 
                           {rx2tx_synlbin_meta  , rx2tx_synlbin});


fflopxe #(2) fftxlbsyn (txclk, txrst_, (tx_ival & (!tx_ien)), 
                        {uplbin          , tx_synlbin_meta}, 
                        {tx_synlbin_meta , tx_synlbin});

fflopxe #(2) fftx2rxlbsyn (rxclk, rxrst_, (rx_oval & (!rx_odv)), 
                           {tx_synlbin         , tx2rx_synlbin_meta}, 
                           {tx2rx_synlbin_meta , tx2rx_synlbin});

wire      lbin_fifofsh;
assign    lbin_fifofsh = (~(rx_synlbin | tx2rx_synlbin)) | upfifofsh;



wire tx_ien_1;
wire lbin_fifowr;
wire lbin_fifofull;
wire lbin_fifowrerr;
wire lbin_write;
wire [3:0] lbin_wraddr;

assign lbin_fifowrerr= lbin_fifowr & lbin_fifofull;

fflopxe #(1) fftxien (txclk, txrst_, tx_ival, tx_ien, tx_ien_1);

assign lbin_fifowr = tx_ival & (tx_ien | tx_ien_1) & (rx2tx_synlbin & tx_synlbin);


reg [9:0] lbin_datipg;

always @(posedge txclk or negedge txrst_)
    begin
    if(!txrst_)
        begin
        lbin_datipg <= 9'b0;
        end
    else if (tx_ival & (~tx_ien))
        begin
        lbin_datipg <= {tx_ier,tx_idat};
        end
    end

assign lbin_wena = lbin_write;
assign lbin_wadd = lbin_wraddr;
assign lbin_wdat = {tx_ier, tx_ien, tx_idat};


wire [9:0] lbin_rddout;   
wire       lbin_rdok;
reg        lbin_state;
wire       lbin_ptknew;

wire       lbin_fiford;
wire       lbin_read;
wire [3:0] lbin_rdaddr;
wire [4:0] lbin_rfifolen;
wire       lbin_rnotempty;
wire       lbin_fiforderr;

wire       lbin_rnotempty1;
wire       lbin_rnotempty2;
assign     lbin_fiforderr = (~lbin_rnotempty2) & lbin_state;
fflopx #(2) fflbinnotemp (rxclk, rxrst_, {lbin_rnotempty,  lbin_rnotempty1},
                                        {lbin_rnotempty1, lbin_rnotempty2});


assign     lbin_ptknew = (lbin_rfifolen >= ({1'b0, uplbffnum}));


always @(posedge rxclk or negedge rxrst_)
    begin
    if(!rxrst_)
        begin
        lbin_state <= 1'b0;
        end
    else if (rx_synlbin | tx2rx_synlbin)
        begin
        if (lbin_rdok & (~lbin_rddout [8] ))
            begin
            lbin_state <= 1'b0;
            end
        else if (lbin_ptknew)
            begin
            lbin_state <= 1'b1;
            end
        else if (lbin_state)
            begin
            lbin_state <= 1'b1;
            end
        else
            begin
            lbin_state <= 1'b0;
            end
        end
    else lbin_state <= 1'b0;
    end

assign lbin_fiford = (((lbin_ptknew & (~lbin_state)) | lbin_state ) & rx_ival) & 
                     (lbin_rnotempty1 & lbin_rnotempty2);

assign lbin_rena = lbin_read;
assign lbin_radd = lbin_rdaddr;

assign lbin_rddout = lbin_rdat;
ipsmacge_delay_k_clk #(2) fflbinrdok (rxclk, rxrst_, lbin_read, lbin_rdok);


always @(posedge rxclk or negedge rxrst_)
    begin
    if(!rxrst_)
        begin
        rx_odat <= 8'b0;
        rx_odv  <= 1'b0;
        rx_oer  <= 1'b0;
        rx_oval <= 1'b0;
        end
    else if (rx_synlbin | tx2rx_synlbin)
        begin
        case ({rx_ival, (lbin_state & lbin_rdok)})
            2'b10:
                begin
                rx_odat <= lbin_datipg [7:0];
                rx_odv  <= 1'b0;
                rx_oer  <= lbin_datipg [8];
                rx_oval <= 1'b1;
                end
            2'b11:
                begin
                rx_odat <= lbin_rddout [7:0];
                rx_odv  <= lbin_rddout [8];
                rx_oer  <= lbin_rddout [9];
                rx_oval <= 1'b1;
                end
            default:
                begin
                rx_odat <= rx_odat;
                rx_odv  <= rx_odv;
                rx_oer  <= rx_oer;
                rx_oval <= 1'b0;
                end
        endcase
        end   
    else
        begin
        rx_odat <= rx_idat;
        rx_odv  <= rx_idv;
        rx_oer  <= rx_ier;
        rx_oval <= rx_ival;
        end
    end

convclk_grayffctrl #(LBIN_AW, LBIN_LW) igrayffctrl
    (
     .wrclk     (txclk),
     .rdclk     (rxclk),
     .wrrst_    (txrst_),
     .rdrst_    (rxrst_),

     .fifowr    (lbin_fifowr),
     .fiford    (lbin_fiford),
     
     .fifoflush (lbin_fifofsh),
     
     .fifofull  (lbin_fifofull),
     .half_full (),
     .fifonemp  (lbin_rnotempty),

     .rdfifolen (lbin_rfifolen),
     .wrfifolen (),
     
     .write     (lbin_write),
     .wraddr    (lbin_wraddr),
     .read      (lbin_read),
     .rdaddr    (lbin_rdaddr)
     );
       
endmodule
module ipsmacge_lbin
    (

     rxrst_,
     rxclk,

     rx_idat,
     rx_idv,
     rx_ier,
     rx_ival,

     rx_odat,
     rx_odv,
     rx_oer,
     rx_oval,

     txclk,
     txrst_,

     tx_idat,
     tx_ien,
     tx_ier,
     tx_ival,

     lbin_fifowrerr,
     lbin_fiforderr,

     uplbin,
     upfifofsh,
     uplbffnum,

     lbin_wdat,
     lbin_wena,
     lbin_wadd,
     
     lbin_rdat,
     lbin_rena,
     lbin_radd
     );




parameter LBIN_AW = 4,
          LBIN_LW = 16,
          LBIN_DW = 10;



input           rxrst_;
input           rxclk;

input [7:0]     rx_idat;
input           rx_idv;
input           rx_ier;
input           rx_ival;

output [7:0]    rx_odat;
output          rx_odv;
output          rx_oer;
output          rx_oval;

input           txclk;
input           txrst_;

input [7:0]     tx_idat;
input           tx_ien;
input           tx_ier;
input           tx_ival;

output          lbin_fifowrerr;
output          lbin_fiforderr;


input           uplbin;
input           upfifofsh;
input [3:0]     uplbffnum;

input  [LBIN_DW-1:0] lbin_rdat;
output               lbin_rena;
output [LBIN_AW-1:0] lbin_radd;

output [LBIN_DW-1:0] lbin_wdat;
output               lbin_wena;
output [LBIN_AW-1:0] lbin_wadd;


reg [7:0]       rx_odat;
reg             rx_odv;
reg             rx_oer;
reg             rx_oval;
























wire      rx_synlbin_meta, rx_synlbin;
wire      rx2tx_synlbin_meta, rx2tx_synlbin;

wire      tx_synlbin_meta, tx_synlbin;
wire      tx2rx_synlbin_meta, tx2rx_synlbin;


fflopxe #(2) ffrxlbsyn (rxclk, rxrst_, (rx_ival & (!rx_idv)), 
                        {uplbin         , rx_synlbin_meta}, 
                        {rx_synlbin_meta, rx_synlbin});

fflopxe #(2) ffrx2txlbsyn (txclk, txrst_, (tx_ival & (!tx_ien)), 
                           {rx_synlbin          , rx2tx_synlbin_meta}, 
                           {rx2tx_synlbin_meta  , rx2tx_synlbin});


fflopxe #(2) fftxlbsyn (txclk, txrst_, (tx_ival & (!tx_ien)), 
                        {uplbin          , tx_synlbin_meta}, 
                        {tx_synlbin_meta , tx_synlbin});

fflopxe #(2) fftx2rxlbsyn (rxclk, rxrst_, (rx_oval & (!rx_odv)), 
                           {tx_synlbin         , tx2rx_synlbin_meta}, 
                           {tx2rx_synlbin_meta , tx2rx_synlbin});

wire      lbin_fifofsh;
assign    lbin_fifofsh = (~(rx_synlbin | tx2rx_synlbin)) | upfifofsh;



wire tx_ien_1;
wire lbin_fifowr;
wire lbin_fifofull;
wire lbin_fifowrerr;
wire lbin_write;
wire [3:0] lbin_wraddr;

assign lbin_fifowrerr= lbin_fifowr & lbin_fifofull;

fflopxe #(1) fftxien (txclk, txrst_, tx_ival, tx_ien, tx_ien_1);

assign lbin_fifowr = tx_ival & (tx_ien | tx_ien_1) & (rx2tx_synlbin & tx_synlbin);


reg [9:0] lbin_datipg;

always @(posedge txclk or negedge txrst_)
    begin
    if(!txrst_)
        begin
        lbin_datipg <= 9'b0;
        end
    else if (tx_ival & (~tx_ien))
        begin
        lbin_datipg <= {tx_ier,tx_idat};
        end
    end

assign lbin_wena = lbin_write;
assign lbin_wadd = lbin_wraddr;
assign lbin_wdat = {tx_ier, tx_ien, tx_idat};


wire [9:0] lbin_rddout;   
wire       lbin_rdok;
reg        lbin_state;
wire       lbin_ptknew;

wire       lbin_fiford;
wire       lbin_read;
wire [3:0] lbin_rdaddr;
wire [4:0] lbin_rfifolen;
wire       lbin_rnotempty;
wire       lbin_fiforderr;

wire       lbin_rnotempty1;
wire       lbin_rnotempty2;
assign     lbin_fiforderr = (~lbin_rnotempty2) & lbin_state;
fflopx #(2) fflbinnotemp (rxclk, rxrst_, {lbin_rnotempty,  lbin_rnotempty1},
                                        {lbin_rnotempty1, lbin_rnotempty2});


assign     lbin_ptknew = (lbin_rfifolen >= ({1'b0, uplbffnum}));


always @(posedge rxclk or negedge rxrst_)
    begin
    if(!rxrst_)
        begin
        lbin_state <= 1'b0;
        end
    else if (rx_synlbin | tx2rx_synlbin)
        begin
        if (lbin_rdok & (~lbin_rddout [8] ))
            begin
            lbin_state <= 1'b0;
            end
        else if (lbin_ptknew)
            begin
            lbin_state <= 1'b1;
            end
        else if (lbin_state)
            begin
            lbin_state <= 1'b1;
            end
        else
            begin
            lbin_state <= 1'b0;
            end
        end
    else lbin_state <= 1'b0;
    end

assign lbin_fiford = (((lbin_ptknew & (~lbin_state)) | lbin_state ) & rx_ival) & 
                     (lbin_rnotempty1 & lbin_rnotempty2);

assign lbin_rena = lbin_read;
assign lbin_radd = lbin_rdaddr;

assign lbin_rddout = lbin_rdat;
ipsmacge_delay_k_clk #(2) fflbinrdok (rxclk, rxrst_, lbin_read, lbin_rdok);


always @(posedge rxclk or negedge rxrst_)
    begin
    if(!rxrst_)
        begin
        rx_odat <= 8'b0;
        rx_odv  <= 1'b0;
        rx_oer  <= 1'b0;
        rx_oval <= 1'b0;
        end
    else if (rx_synlbin | tx2rx_synlbin)
        begin
        case ({rx_ival, (lbin_state & lbin_rdok)})
            2'b10:
                begin
                rx_odat <= lbin_datipg [7:0];
                rx_odv  <= 1'b0;
                rx_oer  <= lbin_datipg [8];
                rx_oval <= 1'b1;
                end
            2'b11:
                begin
                rx_odat <= lbin_rddout [7:0];
                rx_odv  <= lbin_rddout [8];
                rx_oer  <= lbin_rddout [9];
                rx_oval <= 1'b1;
                end
            default:
                begin
                rx_odat <= rx_odat;
                rx_odv  <= rx_odv;
                rx_oer  <= rx_oer;
                rx_oval <= 1'b0;
                end
        endcase
        end   
    else
        begin
        rx_odat <= rx_idat;
        rx_odv  <= rx_idv;
        rx_oer  <= rx_ier;
        rx_oval <= rx_ival;
        end
    end

convclk_grayffctrl #(LBIN_AW, LBIN_LW) igrayffctrl
    (
     .wrclk     (txclk),
     .rdclk     (rxclk),
     .wrrst_    (txrst_),
     .rdrst_    (rxrst_),

     .fifowr    (lbin_fifowr),
     .fiford    (lbin_fiford),
     
     .fifoflush (lbin_fifofsh),
     
     .fifofull  (lbin_fifofull),
     .half_full (),
     .fifonemp  (lbin_rnotempty),

     .rdfifolen (lbin_rfifolen),
     .wrfifolen (),
     
     .write     (lbin_write),
     .wraddr    (lbin_wraddr),
     .read      (lbin_read),
     .rdaddr    (lbin_rdaddr)
     );
       
endmodule