data/full_repos/permissive/474721296/mem/mem_tb.v
1: b'%Error: data/full_repos/permissive/474721296/mem/mem_tb.v:12: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("test.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/474721296/mem/mem_tb.v:13: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, clock, write, address, to_mem, from_mem);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/474721296/mem/mem_tb.v:15: Unsupported or unknown PLI call: $monitor\n  $monitor("#%d:     %b;      0x%h;   0x%h;   0x%h",\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/474721296/mem/mem_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n   #1 clock = 1;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/474721296/mem/mem_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n   #1 clock = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/474721296/mem/mem_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n   #1 clock = 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/474721296/mem/mem_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n   #1 clock = 0;\n   ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mem_tb;
	reg clock;
	reg write;
	reg[7:0] address, to_mem;
	wire[7:0] from_mem;

	initial begin
		$dumpfile("test.vcd");
		$dumpvars(0, clock, write, address, to_mem, from_mem);
		$display("clock   write   address to_mem  from_mem");
		$monitor("#%d:     %b;      0x%h;   0x%h;   0x%h",
			clock, write, address, to_mem, from_mem);
	end

	mem test_mem(clock, write, address, to_mem, from_mem);
	initial begin
		clock = 0;
		write = 1;
		to_mem = 8'b0;
		address = 8'h80;

		for (integer i = 0; i < 16; ++i) begin
			#1 clock = 1;
			#1 clock = 0;
			to_mem = to_mem + 1;
			address = address + 1;
		end

		write = 0;
		address = 8'h80;
		for (integer i = 0; i < 16; ++i) begin
			#1 clock = 1;
			#1 clock = 0;
			to_mem = to_mem + 1;
			address = address + 1;
		end
	end
endmodule
module mem_tb;

	reg clock;
	reg write;
	reg[7:0] address, to_mem;
	wire[7:0] from_mem;

	initial begin
		$dumpfile("test.vcd");
		$dumpvars(0, clock, write, address, to_mem, from_mem);
		$display("clock   write   address to_mem  from_mem");
		$monitor("#%d:     %b;      0x%h;   0x%h;   0x%h",
			clock, write, address, to_mem, from_mem);
	end

	mem test_mem(clock, write, address, to_mem, from_mem);
	initial begin
		clock = 0;
		write = 1;
		to_mem = 8'b0;
		address = 8'h80;

		for (integer i = 0; i < 16; ++i) begin
			#1 clock = 1;
			#1 clock = 0;
			to_mem = to_mem + 1;
			address = address + 1;
		end

		write = 0;
		address = 8'h80;
		for (integer i = 0; i < 16; ++i) begin
			#1 clock = 1;
			#1 clock = 0;
			to_mem = to_mem + 1;
			address = address + 1;
		end
	end
endmodule