data/full_repos/permissive/451577625/system/registerfile_16x32.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/451577625/system/registerfile_16x32.v:142: Unsupported: Ignoring delay on this delayed statement.\n  forever #10 r_clk = ~r_clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/451577625/system/registerfile_16x32.v:128: Cell has missing pin: \'in_BAout\'\nregisterfile_16x32 DUT (\n                   ^~~\n%Error: data/full_repos/permissive/451577625/system/registerfile_16x32.v:21: Cannot find file containing module: \'decoder_4_to_16\'\n decoder_4_to_16 Adecoder(\n ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/decoder_4_to_16\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/decoder_4_to_16.v\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/decoder_4_to_16.sv\n             decoder_4_to_16\n             decoder_4_to_16.v\n             decoder_4_to_16.sv\n             obj_dir/decoder_4_to_16\n             obj_dir/decoder_4_to_16.v\n             obj_dir/decoder_4_to_16.sv\n%Error: data/full_repos/permissive/451577625/system/registerfile_16x32.v:28: Cannot find file containing module: \'decoder_4_to_16\'\n decoder_4_to_16 Cdecoder(\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/451577625/system/registerfile_16x32.v:45: Cannot find file containing module: \'register_32\'\n   register_32 register_inst (\n   ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/451577625/system/registerfile_16x32.v:62: Operator NOT expects 32 bits on the LHS, but LHS\'s VARREF \'in_BAout\' generates 1 bits.\n                                                                                   : ... In instance registerfile_16x32_tb.DUT\n    r_data_out = w_reg_out[0]&(~in_BAout);\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/451577625/system/registerfile_16x32.v:60: Operator CASE expects 16 bits on the Case expression, but Case expression\'s VARREF \'in_Aselect\' generates 4 bits.\n                                                                                   : ... In instance registerfile_16x32_tb.DUT\n  case (in_Aselect)\n  ^~~~\n%Error: Exiting due to 3 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module registerfile_16x32 (
	input [31:0] in_Cdata,
	input [3:0] in_Cselect,

	input [3:0] in_Aselect,
	output[31:0] out_Adata,
	input in_clr,
	input in_write,
	input in_read,
	input in_clk,
	input in_BAout
	);


	wire [15:0] w_A_select;
	wire [15:0] w_C_select;
		

	decoder_4_to_16 Adecoder(
		.in_4 (in_Aselect),
		.out_16 (w_A_select),
		.in_enable(1)
	);
	

	decoder_4_to_16 Cdecoder(
		.in_4 (in_Cselect),
		.out_16 (w_C_select),
		.in_enable(1)
	);
	
	wire [31:0] w_reg_out [0:15];
	
	

	
	

	genvar index;
	generate
	for (index = 0; index < 16; index=index+1)
		begin: gen_registers
			register_32 register_inst (
				.D (in_Cdata),
				.clr (in_clr),
				.clk (in_clk),
				.write(in_write & w_C_select[index]),
				.Q(w_reg_out[index])
			);
			
		end
	endgenerate
	
	reg [31:0] r_data_out;
	

	always @ (*) begin
		case (in_Aselect)
			16'b0000:
				r_data_out = w_reg_out[0]&(~in_BAout);
			16'b0001:
				r_data_out = w_reg_out[1];
			16'b0010:
				r_data_out = w_reg_out[2];
			16'b0011:
				r_data_out = w_reg_out[3];
			16'b0100:
				r_data_out = w_reg_out[4];
			16'b0101:
				r_data_out = w_reg_out[5];
			16'b0110:
				r_data_out = w_reg_out[6];
			16'b0111:
				r_data_out = w_reg_out[7];
			16'b1000:
				r_data_out = w_reg_out[8];
			16'b1001:
				r_data_out = w_reg_out[9];
			16'b1010:
				r_data_out = w_reg_out[10];
			16'b1011:
				r_data_out = w_reg_out[11];
			16'b1100:
				r_data_out = w_reg_out[12];
			16'b1101:
				r_data_out = w_reg_out[13];
			16'b1110:
				r_data_out = w_reg_out[14];
			16'b1111:
				r_data_out = w_reg_out[15];
			default:
				r_data_out = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
		endcase
	end
	
	
	
	assign out_Adata = r_data_out;
	
endmodule
module registerfile_16x32 (
	input [31:0] in_Cdata,
	input [3:0] in_Cselect,

	input [3:0] in_Aselect,
	output[31:0] out_Adata,
	input in_clr,
	input in_write,
	input in_read,
	input in_clk,
	input in_BAout
	);



	wire [15:0] w_A_select;
	wire [15:0] w_C_select;
		

	decoder_4_to_16 Adecoder(
		.in_4 (in_Aselect),
		.out_16 (w_A_select),
		.in_enable(1)
	);
	

	decoder_4_to_16 Cdecoder(
		.in_4 (in_Cselect),
		.out_16 (w_C_select),
		.in_enable(1)
	);
	
	wire [31:0] w_reg_out [0:15];
	
	

	
	

	genvar index;
	generate
	for (index = 0; index < 16; index=index+1)
		begin: gen_registers
			register_32 register_inst (
				.D (in_Cdata),
				.clr (in_clr),
				.clk (in_clk),
				.write(in_write & w_C_select[index]),
				.Q(w_reg_out[index])
			);
			
		end
	endgenerate
	
	reg [31:0] r_data_out;
	

	always @ (*) begin
		case (in_Aselect)
			16'b0000:
				r_data_out = w_reg_out[0]&(~in_BAout);
			16'b0001:
				r_data_out = w_reg_out[1];
			16'b0010:
				r_data_out = w_reg_out[2];
			16'b0011:
				r_data_out = w_reg_out[3];
			16'b0100:
				r_data_out = w_reg_out[4];
			16'b0101:
				r_data_out = w_reg_out[5];
			16'b0110:
				r_data_out = w_reg_out[6];
			16'b0111:
				r_data_out = w_reg_out[7];
			16'b1000:
				r_data_out = w_reg_out[8];
			16'b1001:
				r_data_out = w_reg_out[9];
			16'b1010:
				r_data_out = w_reg_out[10];
			16'b1011:
				r_data_out = w_reg_out[11];
			16'b1100:
				r_data_out = w_reg_out[12];
			16'b1101:
				r_data_out = w_reg_out[13];
			16'b1110:
				r_data_out = w_reg_out[14];
			16'b1111:
				r_data_out = w_reg_out[15];
			default:
				r_data_out = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
		endcase
	end
	
	
	
	assign out_Adata = r_data_out;
	
endmodule