data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/macro/stickystachgx.v
data/verilator_xmls/3fabf833-9191-4a0a-96ce-572de824b35d.xml
module stickystachgx
    (
     clk,
     rst,
     upactive,
     alarmvld,
     alarmsta,
     upen,
     upws,
     updi,
     updo,
     lalarm
     );

parameter           WIDTH = 8;
input               clk;
input               rst;
input               upactive;
input   [1:0]       upen;
input               upws;
input   [WIDTH-1:0] alarmvld,
                    alarmsta;
input   [WIDTH-1:0] updi;

output  [WIDTH-1:0] updo;
output  [WIDTH-1:0] lalarm;

wire                upen_intr,upen_alarm;
assign              {upen_intr,upen_alarm} = upen[1:0];

wire                we;
assign              we = upen_intr & upws;

reg     [WIDTH-1:0] lalarm = {WIDTH{1'b0}};
reg     [WIDTH-1:0] alarm = {WIDTH{1'b0}};

assign updo = upen_alarm ? alarm : upen_intr ? lalarm : {WIDTH{1'b0}};


integer             i;
always @(posedge clk)
    begin
    if (rst)    
        alarm <= {WIDTH{1'b0}};
    else if (~upactive)
        begin
        if(we) alarm <= updi;
        end
    else
        begin
        for (i=0;i<WIDTH;i=i+1) if (alarmvld[i])    alarm[i] <= alarmsta[i];
        end
    end


wire [WIDTH-1:0]    alarmchg;
assign              alarmchg = alarmvld & (alarmsta ^ alarm);

always @(posedge clk)
    begin
    if (rst) 
        lalarm <= {WIDTH{1'b0}};
    else if (~upactive)
        begin
        if(we) lalarm <= updi;
        end
    else if (we)
        lalarm <= alarmchg | (lalarm & ~updi);
    else 
        lalarm <= alarmchg | lalarm;
    end

endmodule
module stickystachgx
    (
     clk,
     rst,
     upactive,
     alarmvld,
     alarmsta,
     upen,
     upws,
     updi,
     updo,
     lalarm
     );


parameter           WIDTH = 8;
input               clk;
input               rst;
input               upactive;
input   [1:0]       upen;
input               upws;
input   [WIDTH-1:0] alarmvld,
                    alarmsta;
input   [WIDTH-1:0] updi;

output  [WIDTH-1:0] updo;
output  [WIDTH-1:0] lalarm;

wire                upen_intr,upen_alarm;
assign              {upen_intr,upen_alarm} = upen[1:0];

wire                we;
assign              we = upen_intr & upws;

reg     [WIDTH-1:0] lalarm = {WIDTH{1'b0}};
reg     [WIDTH-1:0] alarm = {WIDTH{1'b0}};

assign updo = upen_alarm ? alarm : upen_intr ? lalarm : {WIDTH{1'b0}};


integer             i;
always @(posedge clk)
    begin
    if (rst)    
        alarm <= {WIDTH{1'b0}};
    else if (~upactive)
        begin
        if(we) alarm <= updi;
        end
    else
        begin
        for (i=0;i<WIDTH;i=i+1) if (alarmvld[i])    alarm[i] <= alarmsta[i];
        end
    end


wire [WIDTH-1:0]    alarmchg;
assign              alarmchg = alarmvld & (alarmsta ^ alarm);

always @(posedge clk)
    begin
    if (rst) 
        lalarm <= {WIDTH{1'b0}};
    else if (~upactive)
        begin
        if(we) lalarm <= updi;
        end
    else if (we)
        lalarm <= alarmchg | (lalarm & ~updi);
    else 
        lalarm <= alarmchg | lalarm;
    end

endmodule