data/full_repos/permissive/499137621/CheckPoint2_32bit_ALU_project-main/SRA_32.v
1: b"%Error: data/full_repos/permissive/499137621/CheckPoint2_32bit_ALU_project-main/SRA_32.v:34: Cannot find file containing module: 'MUX_2to1'\n   MUX_2to1 mux(out_1[i_1], data_in_[i_1], data_in_[i_1+1], shift_ctrl[0]);\n   ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/499137621/CheckPoint2_32bit_ALU_project-main,data/full_repos/permissive/499137621/MUX_2to1\n             data/full_repos/permissive/499137621/CheckPoint2_32bit_ALU_project-main,data/full_repos/permissive/499137621/MUX_2to1.v\n             data/full_repos/permissive/499137621/CheckPoint2_32bit_ALU_project-main,data/full_repos/permissive/499137621/MUX_2to1.sv\n             MUX_2to1\n             MUX_2to1.v\n             MUX_2to1.sv\n             obj_dir/MUX_2to1\n             obj_dir/MUX_2to1.v\n             obj_dir/MUX_2to1.sv\n%Error: data/full_repos/permissive/499137621/CheckPoint2_32bit_ALU_project-main/SRA_32.v:45: Cannot find file containing module: 'MUX_2to1'\n   MUX_2to1 mux(out_2[i_2], out_1[i_2], out_1[i_2+2],  shift_ctrl[1]);\n   ^~~~~~~~\n%Error: data/full_repos/permissive/499137621/CheckPoint2_32bit_ALU_project-main/SRA_32.v:55: Cannot find file containing module: 'MUX_2to1'\n   MUX_2to1 mux(out_2[i_3], out_1[i_3], data_in_[32],  shift_ctrl[1]);\n   ^~~~~~~~\n%Error: data/full_repos/permissive/499137621/CheckPoint2_32bit_ALU_project-main/SRA_32.v:68: Cannot find file containing module: 'MUX_2to1'\n   MUX_2to1 mux(out_3[i_4], out_2[i_4], out_2[i_4+4],  shift_ctrl[2]);\n   ^~~~~~~~\n%Error: data/full_repos/permissive/499137621/CheckPoint2_32bit_ALU_project-main/SRA_32.v:78: Cannot find file containing module: 'MUX_2to1'\n   MUX_2to1 mux(out_3[i_5], out_2[i_5], data_in_[32],  shift_ctrl[2]);\n   ^~~~~~~~\n%Error: data/full_repos/permissive/499137621/CheckPoint2_32bit_ALU_project-main/SRA_32.v:92: Cannot find file containing module: 'MUX_2to1'\n   MUX_2to1 mux(out_4[i_6], out_3[i_6], out_3[i_6+8],  shift_ctrl[3]);\n   ^~~~~~~~\n%Error: data/full_repos/permissive/499137621/CheckPoint2_32bit_ALU_project-main/SRA_32.v:102: Cannot find file containing module: 'MUX_2to1'\n   MUX_2to1 mux(out_4[i_7], out_3[i_7], data_in_[32],  shift_ctrl[3]);\n   ^~~~~~~~\n%Error: data/full_repos/permissive/499137621/CheckPoint2_32bit_ALU_project-main/SRA_32.v:115: Cannot find file containing module: 'MUX_2to1'\n   MUX_2to1 mux(out_5[i_8], out_4[i_8], out_4[i_8+16],  shift_ctrl[4]);\n   ^~~~~~~~\n%Error: data/full_repos/permissive/499137621/CheckPoint2_32bit_ALU_project-main/SRA_32.v:125: Cannot find file containing module: 'MUX_2to1'\n   MUX_2to1 mux(out_5[i_9], out_4[i_9], data_in_[32],  shift_ctrl[4]);\n   ^~~~~~~~\n%Error: Exiting due to 9 error(s)\n"
module SRA_32(data_out, data_in, shift_ctrl);
	
	input [31:0] data_in; 
	input [4:0] shift_ctrl;
	output [31:0] data_out;

	wire [31:0] out_1, out_2, out_3, out_4, out_5;
	wire [32:0] data_in_;
	


	genvar n;
	generate
		for (n = 0; n < 32; n = n + 1) begin: assign_data
			assign data_in_[n] = data_in[n];
		end
	endgenerate
	
	assign data_in_[32] = data_in[31];
	
	

	genvar i_1;
	generate
		for (i_1 = 0; i_1 < 32; i_1 = i_1 + 1) begin: shift_1
			MUX_2to1 mux(out_1[i_1], data_in_[i_1], data_in_[i_1+1], shift_ctrl[0]);
		end
	endgenerate
	
	
	

	
	genvar i_2;
	generate
		for (i_2 = 0; i_2 < 30; i_2 = i_2 + 1) begin: shift_2
			MUX_2to1 mux(out_2[i_2], out_1[i_2], out_1[i_2+2],  shift_ctrl[1]);
		end
	endgenerate
	
	

	
	genvar i_3;
	generate
		for (i_3 = 30; i_3 < 32; i_3 = i_3 + 1) begin: shift_2_top
			MUX_2to1 mux(out_2[i_3], out_1[i_3], data_in_[32],  shift_ctrl[1]);
		end
	endgenerate
	
	
	

	

	
	genvar i_4;
	generate
		for (i_4 = 0; i_4 < 28; i_4 = i_4 + 1) begin: shift_4
			MUX_2to1 mux(out_3[i_4], out_2[i_4], out_2[i_4+4],  shift_ctrl[2]);
		end
	endgenerate
	


	
	genvar i_5;
	generate
		for (i_5 = 28; i_5 < 32; i_5 = i_5 + 1) begin: shift_4_top
			MUX_2to1 mux(out_3[i_5], out_2[i_5], data_in_[32],  shift_ctrl[2]);
		end
	endgenerate


	


	

	
	genvar i_6;
	generate
		for (i_6 = 0; i_6 < 24; i_6 = i_6 + 1) begin: shift_8
			MUX_2to1 mux(out_4[i_6], out_3[i_6], out_3[i_6+8],  shift_ctrl[3]);
		end
	endgenerate
	


	
	genvar i_7;
	generate
		for (i_7 = 24; i_7 < 32; i_7 = i_7 + 1) begin: shift_8_top
			MUX_2to1 mux(out_4[i_7], out_3[i_7], data_in_[32],  shift_ctrl[3]);
		end
	endgenerate




	

	
	genvar i_8;
	generate
		for (i_8 = 0; i_8 < 16; i_8 = i_8 + 1) begin: shift_16
			MUX_2to1 mux(out_5[i_8], out_4[i_8], out_4[i_8+16],  shift_ctrl[4]);
		end
	endgenerate
	


	
	genvar i_9;
	generate
		for (i_9 = 16; i_9 < 32; i_9 = i_9 + 1) begin: shift_16_top
			MUX_2to1 mux(out_5[i_9], out_4[i_9], data_in_[32],  shift_ctrl[4]);
		end
	endgenerate
	
	
	

	assign data_out = out_5;
	
		
endmodule
module SRA_32(data_out, data_in, shift_ctrl);

	
	input [31:0] data_in; 
	input [4:0] shift_ctrl;
	output [31:0] data_out;

	wire [31:0] out_1, out_2, out_3, out_4, out_5;
	wire [32:0] data_in_;
	


	genvar n;
	generate
		for (n = 0; n < 32; n = n + 1) begin: assign_data
			assign data_in_[n] = data_in[n];
		end
	endgenerate
	
	assign data_in_[32] = data_in[31];
	
	

	genvar i_1;
	generate
		for (i_1 = 0; i_1 < 32; i_1 = i_1 + 1) begin: shift_1
			MUX_2to1 mux(out_1[i_1], data_in_[i_1], data_in_[i_1+1], shift_ctrl[0]);
		end
	endgenerate
	
	
	

	
	genvar i_2;
	generate
		for (i_2 = 0; i_2 < 30; i_2 = i_2 + 1) begin: shift_2
			MUX_2to1 mux(out_2[i_2], out_1[i_2], out_1[i_2+2],  shift_ctrl[1]);
		end
	endgenerate
	
	

	
	genvar i_3;
	generate
		for (i_3 = 30; i_3 < 32; i_3 = i_3 + 1) begin: shift_2_top
			MUX_2to1 mux(out_2[i_3], out_1[i_3], data_in_[32],  shift_ctrl[1]);
		end
	endgenerate
	
	
	

	

	
	genvar i_4;
	generate
		for (i_4 = 0; i_4 < 28; i_4 = i_4 + 1) begin: shift_4
			MUX_2to1 mux(out_3[i_4], out_2[i_4], out_2[i_4+4],  shift_ctrl[2]);
		end
	endgenerate
	


	
	genvar i_5;
	generate
		for (i_5 = 28; i_5 < 32; i_5 = i_5 + 1) begin: shift_4_top
			MUX_2to1 mux(out_3[i_5], out_2[i_5], data_in_[32],  shift_ctrl[2]);
		end
	endgenerate


	


	

	
	genvar i_6;
	generate
		for (i_6 = 0; i_6 < 24; i_6 = i_6 + 1) begin: shift_8
			MUX_2to1 mux(out_4[i_6], out_3[i_6], out_3[i_6+8],  shift_ctrl[3]);
		end
	endgenerate
	


	
	genvar i_7;
	generate
		for (i_7 = 24; i_7 < 32; i_7 = i_7 + 1) begin: shift_8_top
			MUX_2to1 mux(out_4[i_7], out_3[i_7], data_in_[32],  shift_ctrl[3]);
		end
	endgenerate




	

	
	genvar i_8;
	generate
		for (i_8 = 0; i_8 < 16; i_8 = i_8 + 1) begin: shift_16
			MUX_2to1 mux(out_5[i_8], out_4[i_8], out_4[i_8+16],  shift_ctrl[4]);
		end
	endgenerate
	


	
	genvar i_9;
	generate
		for (i_9 = 16; i_9 < 32; i_9 = i_9 + 1) begin: shift_16_top
			MUX_2to1 mux(out_5[i_9], out_4[i_9], data_in_[32],  shift_ctrl[4]);
		end
	endgenerate
	
	
	

	assign data_out = out_5;
	
		
endmodule