data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/auc_wmul_dbl.v
data/verilator_xmls/e10bcc49-7951-4020-a37a-c59060f86031.xml
module auc_wmul_dbl
    (
     clk,
     rst,

     dbl_audat,
     dbl_auvld,
     dbl_en,

     dbl_start,
     dbl_opcode,
     dbl_const,
     dbl_carry,
     dbl_end,

     dbl_radd,
     dbl_wen,
     dbl_wadd,
     dbl_wdat
     );




parameter           WIDTH   = 256;
parameter           ADDR    = 5;

localparam          INIT    = 0;

localparam          X_G     = 0;
localparam          Y_G     = 1;
localparam          X_3G    = 2;
localparam          Y_3G    = 3;
localparam          Z_3G    = 4;
localparam          X_5G    = 5;
localparam          Y_5G    = 6;
localparam          Z_5G    = 7;
localparam          X_7G    = 8;
localparam          Y_7G    = 9;
localparam          Z_7G    = 10;

localparam          K_NUM   = 11;
localparam          K_INV   = 12;
localparam          R_NUM   = 13;
localparam          S_NUM   = 14;
localparam          X_KG    = 15;
localparam          HASH    = 16;
localparam          PKEY    = 17;
localparam          ZRRAM   = 18;
localparam          ONERAM  = 19;

localparam          TEMP0   = 20;
localparam          TEMP1   = 21;
localparam          TEMP2   = 22;
localparam          TEMP3   = 23;
localparam          TEMP4   = 24;
localparam          TEMP5   = 25;
localparam          TEMP6   = 26;   
localparam          TEMP7   = 27;
localparam          TEMP8   = 28;

localparam          S_RP    = 29;
localparam          S_RPH   = 30;
localparam          BLNK    = 31;



localparam          OP_FA   = 4'b0000;
localparam          OP_MUL  = 4'b0001;
localparam          OP_INV  = 4'b0010;




input               clk;
input               rst;

input [WIDTH-1:0]   dbl_audat;
input               dbl_auvld;
input               dbl_en;

output [ADDR-1:0]   dbl_radd;
output              dbl_wen;
output [ADDR-1:0]   dbl_wadd;
output [WIDTH-1:0]  dbl_wdat;

output              dbl_start;
output [3:0]        dbl_opcode;
output [WIDTH-1:0]  dbl_const;
output              dbl_carry;
output              dbl_end;




reg [ADDR-1:0]      dbl_radd;
reg                 dbl_wen;
reg [ADDR-1:0]      dbl_wadd;
reg [WIDTH-1:0]     dbl_wdat;

reg                 dbl_start;
reg [3:0]           dbl_opcode;
reg [WIDTH-1:0]     dbl_const;
reg                 dbl_carry;
reg                 dbl_end;




reg [4:0]           dbl_step;
wire [4:0]          dbl_step_inc;
assign              dbl_step_inc = dbl_step + 1'b1;

reg                 dbl_1more;
reg                 dbl_en_sticky;

always @(posedge clk)
    begin
    if (rst)
        begin
        dbl_radd    <= INIT;
        dbl_wen     <= INIT;
        dbl_wadd    <= INIT;
        dbl_wdat    <= INIT;

        dbl_start   <= INIT;
        dbl_opcode  <= INIT;
        dbl_const   <= INIT;
        dbl_carry   <= INIT;
        dbl_end     <= INIT;

        dbl_step    <= INIT;
        dbl_1more   <= INIT;
        dbl_en_sticky   <= INIT;
        end
    else if (dbl_en)
        begin
        dbl_radd    <= INIT;
        dbl_wen     <= INIT;
        dbl_wadd    <= INIT;
        dbl_wdat    <= INIT;

        dbl_start   <= INIT;
        dbl_opcode  <= INIT;
        dbl_const   <= INIT;
        dbl_carry   <= INIT;
        dbl_end     <= INIT;

        dbl_step    <= INIT;
        dbl_1more   <= INIT;
        dbl_en_sticky   <= 1'b1;
        end
    else if (dbl_en_sticky)
        begin
        case(dbl_step)
            5'd0:
                begin
                case(dbl_1more)
                    1'b0: 
                        begin
                        dbl_start   <= 1'b0;
                        dbl_step    <= dbl_step;
                        end
                    1'b1: 
                        begin
                        dbl_start   <= 1'b1;
                        dbl_step    <= dbl_step_inc;
                        end
                endcase
                dbl_radd    <= TEMP0;
                dbl_1more   <= ~dbl_1more;
                dbl_opcode  <= OP_MUL;
                dbl_const   <= INIT;
                dbl_carry   <= 1'b0;
                dbl_end     <= 1'b0;
                end
            5'd1:
                begin
                if (dbl_auvld)
                    begin
                    dbl_radd    <= TEMP3;
                    dbl_wen     <= 1'b1;
                    dbl_wadd    <= TEMP3;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_MUL;
                    dbl_const   <= 256'd3;
                    dbl_start   <= 1'b1;
                    dbl_carry   <= 1'b0;
                    dbl_step    <= dbl_step_inc;
                    dbl_end     <= 1'b0;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_start   <= 1'b0;
                    dbl_end     <= 1'b0;
                    dbl_1more   <= 1'b0;
                    end
                end
            5'd2:
                begin
                case(dbl_1more)
                    1'b0: 
                        begin
                        dbl_start   <= 1'b0;
                        dbl_step    <= dbl_step;
                        dbl_1more   <= dbl_auvld;
                        end
                    1'b1: 
                        begin
                        dbl_start   <= 1'b1;
                        dbl_step    <= dbl_step_inc;
                        dbl_1more   <= 1'b0;
                        end
                endcase
                if (dbl_auvld)
                    begin
                    dbl_radd    <= TEMP2;
                    dbl_wen     <= ~dbl_wen;
                    dbl_wadd    <= TEMP3;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_MUL;
                    dbl_const   <= INIT;
                    dbl_carry   <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                end
            5'd3:
                begin
                case(dbl_1more)
                    1'b0: 
                        begin
                        dbl_start   <= 1'b0;
                        dbl_step    <= dbl_step;
                        dbl_1more   <= dbl_auvld;
                        end
                    1'b1: 
                        begin
                        dbl_start   <= 1'b1;
                        dbl_step    <= dbl_step_inc;
                        dbl_1more   <= 1'b0;
                        end
                endcase
                if (dbl_auvld)
                    begin
                    dbl_radd    <= TEMP4;
                    dbl_wen     <= ~dbl_wen;
                    dbl_wadd    <= TEMP4;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_MUL;
                    dbl_const   <= INIT;
                    dbl_carry   <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                end
            5'd4:
                begin
                if (dbl_auvld)
                    begin
                    dbl_radd    <= TEMP4;
                    dbl_wen     <= 1'b1;
                    dbl_wadd    <= TEMP4;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_MUL;
                    dbl_const   <= 256'd3;
                    dbl_start   <= 1'b1;
                    dbl_end     <= 1'b0;
                    dbl_carry   <= 1'b0;
                    dbl_step    <= dbl_step_inc;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_start   <= 1'b0;
                    dbl_end     <= 1'b0;
                    dbl_1more   <= 1'b0;
                    end
                end
            5'd5:
                begin
                case(dbl_1more)
                    1'b0: 
                        begin
                        dbl_start   <= 1'b0;
                        dbl_step    <= dbl_step;
                        dbl_radd    <= dbl_auvld? TEMP4: dbl_radd;
                        dbl_1more   <= dbl_auvld;
                        end
                    1'b1: 
                        begin
                        dbl_start   <= 1'b1;
                        dbl_step    <= dbl_step_inc;
                        dbl_radd    <= TEMP3;
                        dbl_1more   <= 1'b0;
                        end
                endcase
                if (dbl_auvld)
                    begin
                    dbl_wen     <= ~dbl_wen;
                    dbl_wadd    <= TEMP4;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_FA;
                    dbl_const   <= INIT;
                    dbl_carry   <= 1'b1;
                    dbl_end     <= 1'b0;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                end
            5'd6:
                begin
                case(dbl_1more)
                    1'b0: 
                        begin
                        dbl_start   <= 1'b0;
                        dbl_step    <= dbl_step;
                        dbl_1more   <= dbl_auvld;
                        end
                    1'b1: 
                        begin
                        dbl_start   <= 1'b1;
                        dbl_step    <= dbl_step_inc;
                        dbl_1more   <= 1'b0;
                        end
                endcase
                if (dbl_auvld)
                    begin
                    dbl_radd    <= TEMP1;
                    dbl_wen     <= ~dbl_wen;
                    dbl_wadd    <= TEMP3;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_MUL;
                    dbl_const   <= INIT;
                    dbl_carry   <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                end
            5'd7:
                begin
                case(dbl_1more)
                     1'b0: 
                         begin
                         dbl_start   <= 1'b0;
                         dbl_step    <= dbl_step;
                         dbl_radd    <= dbl_auvld? TEMP0: dbl_radd;
                         dbl_1more  <= dbl_auvld;
                         end
                     1'b1: 
                         begin
                         dbl_start   <= 1'b1;
                         dbl_step    <= dbl_step_inc;
                         dbl_radd    <= TEMP4;
                         dbl_1more  <= 1'b0;
                         end
                endcase
                if (dbl_auvld)
                    begin
                    dbl_wen     <= ~dbl_wen;
                    dbl_wadd    <= TEMP4;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_MUL;
                    dbl_const   <= INIT;
                    dbl_carry   <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                end
            5'd8:
                begin
                case(dbl_1more)
                    1'b0: 
                        begin
                        dbl_start   <= 1'b0;
                        dbl_step    <= dbl_step;
                        dbl_1more   <= dbl_auvld;
                        end
                    1'b1: 
                        begin
                        dbl_start   <= 1'b1;
                        dbl_step    <= dbl_step_inc;
                        dbl_1more   <= 1'b0;
                        end
                endcase
                if (dbl_auvld)
                    begin
                    dbl_radd    <= TEMP4;
                    dbl_wen     <= ~dbl_wen;
                    dbl_wadd    <= TEMP5;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_MUL;
                    dbl_const   <= INIT;
                    dbl_carry   <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                end
            5'd9:
                begin
                if (dbl_auvld)
                    begin
                    dbl_radd    <= TEMP5;
                    dbl_wen     <= 1'b1;
                    dbl_wadd    <= TEMP4;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_MUL;
                    dbl_const   <= 256'd4;
                    dbl_start   <= 1'b1;
                    dbl_carry   <= 1'b0;
                    dbl_end     <= 1'b0;
                    dbl_step    <= dbl_step_inc;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_start   <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                end
            5'd10:
                begin
                case(dbl_1more)
                    1'b0: 
                        begin
                        dbl_start   <= 1'b0;
                        dbl_step    <= dbl_step;
                        dbl_1more   <= dbl_auvld;
                        end
                    1'b1: 
                        begin
                        dbl_start   <= 1'b1;
                        dbl_step    <= dbl_step_inc;
                        dbl_1more   <= 1'b0;
                        end
                endcase
                if (dbl_auvld)
                    begin
                    dbl_radd    <= TEMP3;
                    dbl_wen     <= ~dbl_wen;
                    dbl_wadd    <= TEMP5;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_MUL;
                    dbl_const   <= INIT;
                    dbl_carry   <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                end
            5'd11:
                begin
                if (dbl_auvld)
                    begin
                    dbl_radd    <= TEMP5;
                    dbl_wen     <= 1'b1;
                    dbl_wadd    <= TEMP6;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_MUL;
                    dbl_const   <= 256'd2;
                    dbl_start   <= 1'b1;
                    dbl_carry   <= 1'b0;
                    dbl_end     <= 1'b0;
                    dbl_step    <= dbl_step_inc;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_start   <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                end
            5'd12:
                begin
                case(dbl_1more)
                    1'b0: 
                        begin
                        dbl_start   <= 1'b0;
                        dbl_step    <= dbl_step;
                        dbl_radd    <= dbl_auvld? TEMP7: dbl_radd;
                        dbl_1more   <= dbl_auvld;
                        end
                    1'b1: 
                        begin
                        dbl_start   <= 1'b1;
                        dbl_step    <= dbl_step_inc;
                        dbl_radd    <= TEMP6;
                        dbl_1more   <= 1'b0;
                        end
                endcase
                if (dbl_auvld)
                    begin
                    dbl_wen     <= ~dbl_wen;
                    dbl_wadd    <= TEMP7;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_FA;
                    dbl_const   <= INIT;
                    dbl_carry   <= 1'b1;
                    dbl_end     <= 1'b0;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                end
            5'd13:
                begin
                case(dbl_1more)
                    1'b0: 
                        begin
                        dbl_start   <= 1'b0;
                        dbl_step    <= dbl_step;
                        dbl_radd    <= dbl_auvld? TEMP1: dbl_radd;
                        dbl_1more   <= dbl_auvld;
                        end
                    1'b1: 
                        begin
                        dbl_start   <= 1'b1;
                        dbl_step    <= dbl_step_inc;
                        dbl_radd    <= TEMP2;
                        dbl_1more   <= 1'b0;
                        end
                endcase
                if (dbl_auvld)
                    begin
                    dbl_wen     <= ~dbl_wen;
                    dbl_wadd    <= TEMP0;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_MUL;
                    dbl_const   <= INIT;
                    dbl_carry   <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                end
            5'd14:
                begin
                if (dbl_auvld)
                    begin
                    dbl_radd    <= TEMP2;
                    dbl_wen     <= 1'b1;
                    dbl_wadd    <= TEMP2;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_MUL;
                    dbl_const   <= 256'd2;
                    dbl_start   <= 1'b1;
                    dbl_carry   <= 1'b0;
                    dbl_end     <= 1'b0;
                    dbl_step    <= dbl_step_inc;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_start   <= 1'b0;
                    dbl_end     <= 1'b0;
                    dbl_1more   <= 1'b0;
                    end
                end
            5'd15:
                begin
                if (dbl_auvld)
                    begin
                    dbl_radd    <= TEMP4;
                    dbl_wen     <= 1'b1;
                    dbl_wadd    <= TEMP2;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_MUL;
                    dbl_const   <= 256'd8;
                    dbl_start   <= 1'b1;
                    dbl_carry   <= 1'b0;
                    dbl_end     <= 1'b0;
                    dbl_step    <= dbl_step_inc;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_start   <= 1'b0;
                    dbl_end     <= 1'b0;
                    dbl_1more   <= 1'b0;
                    end
                end 
            5'd16:
                begin
                case(dbl_1more)
                    1'b0: 
                        begin
                        dbl_start   <= 1'b0;
                        dbl_step    <= dbl_step;
                        dbl_radd    <= dbl_auvld? TEMP0: dbl_radd;
                        dbl_1more   <= dbl_auvld;
                        end
                    1'b1: 
                        begin
                        dbl_start   <= 1'b1;
                        dbl_step    <= dbl_step_inc;
                        dbl_radd    <= TEMP5;
                        dbl_1more   <= 1'b0;
                        end
                endcase
                if (dbl_auvld)
                    begin
                    dbl_wen     <= ~dbl_wen;
                    dbl_wadd    <= TEMP4;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_FA;
                    dbl_const   <= INIT;
                    dbl_carry   <= 1'b1;
                    dbl_end     <= 1'b0;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                end
            5'd17:
                begin
                case(dbl_1more)
                    1'b0: 
                        begin
                        dbl_start   <= 1'b0;
                        dbl_step    <= dbl_step;
                        dbl_radd    <= dbl_auvld? TEMP3: dbl_radd;
                        dbl_1more   <= dbl_auvld;
                        end
                    1'b1: 
                        begin
                        dbl_start   <= 1'b1;
                        dbl_step    <= dbl_step_inc;
                        dbl_radd    <= TEMP5;
                        dbl_1more   <= 1'b0;
                        end
                endcase 
                if (dbl_auvld)
                    begin
                    dbl_wen     <= ~dbl_wen;
                    dbl_wadd    <= TEMP5;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_MUL;
                    dbl_const   <= INIT;
                    dbl_carry   <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                end
            5'd18:
                begin
                case(dbl_1more)
                    1'b0: 
                        begin
                        dbl_start   <= 1'b0;
                        dbl_step    <= dbl_step;
                        dbl_radd    <= dbl_auvld? TEMP4: dbl_radd;
                        dbl_1more   <= dbl_auvld;
                        end
                    1'b1: 
                        begin
                        dbl_start   <= 1'b1;
                        dbl_step    <= dbl_step_inc;
                        dbl_radd    <= TEMP3;
                        dbl_1more   <= 1'b0;
                        end
                endcase
                if (dbl_auvld)
                    begin
                    dbl_wen     <= ~dbl_wen;
                    dbl_wadd    <= TEMP3;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_FA;
                    dbl_const   <= INIT;
                    dbl_carry   <= 1'b1;
                    dbl_end     <= 1'b0;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                end
            5'd19:
                begin
                if (dbl_auvld)
                    begin
                    dbl_const   <= INIT;
                    dbl_wen     <= 1'b1;
                    dbl_wadd    <= TEMP1;
                    dbl_wdat    <= dbl_audat;
                    dbl_end     <= 1'b1;
                    dbl_step    <= dbl_step_inc;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_start   <= 1'b0;
                    dbl_end     <= 1'b0;
                    dbl_1more   <= 1'b0;
                    end
                end
            default:
                begin
                dbl_radd    <= INIT;
                dbl_wen     <= INIT;
                dbl_wadd    <= INIT;
                dbl_wdat    <= INIT;

                dbl_start   <= INIT;
                dbl_opcode  <= INIT;
                dbl_const   <= INIT;
                dbl_carry   <= INIT;

                dbl_step    <= INIT;
                dbl_end     <= INIT;

                dbl_1more   <= INIT;
                dbl_en_sticky   <= INIT;
                end
        endcase
        end
    end

endmodule
module auc_wmul_dbl
    (
     clk,
     rst,

     dbl_audat,
     dbl_auvld,
     dbl_en,

     dbl_start,
     dbl_opcode,
     dbl_const,
     dbl_carry,
     dbl_end,

     dbl_radd,
     dbl_wen,
     dbl_wadd,
     dbl_wdat
     );





parameter           WIDTH   = 256;
parameter           ADDR    = 5;

localparam          INIT    = 0;

localparam          X_G     = 0;
localparam          Y_G     = 1;
localparam          X_3G    = 2;
localparam          Y_3G    = 3;
localparam          Z_3G    = 4;
localparam          X_5G    = 5;
localparam          Y_5G    = 6;
localparam          Z_5G    = 7;
localparam          X_7G    = 8;
localparam          Y_7G    = 9;
localparam          Z_7G    = 10;

localparam          K_NUM   = 11;
localparam          K_INV   = 12;
localparam          R_NUM   = 13;
localparam          S_NUM   = 14;
localparam          X_KG    = 15;
localparam          HASH    = 16;
localparam          PKEY    = 17;
localparam          ZRRAM   = 18;
localparam          ONERAM  = 19;

localparam          TEMP0   = 20;
localparam          TEMP1   = 21;
localparam          TEMP2   = 22;
localparam          TEMP3   = 23;
localparam          TEMP4   = 24;
localparam          TEMP5   = 25;
localparam          TEMP6   = 26;   
localparam          TEMP7   = 27;
localparam          TEMP8   = 28;

localparam          S_RP    = 29;
localparam          S_RPH   = 30;
localparam          BLNK    = 31;



localparam          OP_FA   = 4'b0000;
localparam          OP_MUL  = 4'b0001;
localparam          OP_INV  = 4'b0010;




input               clk;
input               rst;

input [WIDTH-1:0]   dbl_audat;
input               dbl_auvld;
input               dbl_en;

output [ADDR-1:0]   dbl_radd;
output              dbl_wen;
output [ADDR-1:0]   dbl_wadd;
output [WIDTH-1:0]  dbl_wdat;

output              dbl_start;
output [3:0]        dbl_opcode;
output [WIDTH-1:0]  dbl_const;
output              dbl_carry;
output              dbl_end;




reg [ADDR-1:0]      dbl_radd;
reg                 dbl_wen;
reg [ADDR-1:0]      dbl_wadd;
reg [WIDTH-1:0]     dbl_wdat;

reg                 dbl_start;
reg [3:0]           dbl_opcode;
reg [WIDTH-1:0]     dbl_const;
reg                 dbl_carry;
reg                 dbl_end;




reg [4:0]           dbl_step;
wire [4:0]          dbl_step_inc;
assign              dbl_step_inc = dbl_step + 1'b1;

reg                 dbl_1more;
reg                 dbl_en_sticky;

always @(posedge clk)
    begin
    if (rst)
        begin
        dbl_radd    <= INIT;
        dbl_wen     <= INIT;
        dbl_wadd    <= INIT;
        dbl_wdat    <= INIT;

        dbl_start   <= INIT;
        dbl_opcode  <= INIT;
        dbl_const   <= INIT;
        dbl_carry   <= INIT;
        dbl_end     <= INIT;

        dbl_step    <= INIT;
        dbl_1more   <= INIT;
        dbl_en_sticky   <= INIT;
        end
    else if (dbl_en)
        begin
        dbl_radd    <= INIT;
        dbl_wen     <= INIT;
        dbl_wadd    <= INIT;
        dbl_wdat    <= INIT;

        dbl_start   <= INIT;
        dbl_opcode  <= INIT;
        dbl_const   <= INIT;
        dbl_carry   <= INIT;
        dbl_end     <= INIT;

        dbl_step    <= INIT;
        dbl_1more   <= INIT;
        dbl_en_sticky   <= 1'b1;
        end
    else if (dbl_en_sticky)
        begin
        case(dbl_step)
            5'd0:
                begin
                case(dbl_1more)
                    1'b0: 
                        begin
                        dbl_start   <= 1'b0;
                        dbl_step    <= dbl_step;
                        end
                    1'b1: 
                        begin
                        dbl_start   <= 1'b1;
                        dbl_step    <= dbl_step_inc;
                        end
                endcase
                dbl_radd    <= TEMP0;
                dbl_1more   <= ~dbl_1more;
                dbl_opcode  <= OP_MUL;
                dbl_const   <= INIT;
                dbl_carry   <= 1'b0;
                dbl_end     <= 1'b0;
                end
            5'd1:
                begin
                if (dbl_auvld)
                    begin
                    dbl_radd    <= TEMP3;
                    dbl_wen     <= 1'b1;
                    dbl_wadd    <= TEMP3;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_MUL;
                    dbl_const   <= 256'd3;
                    dbl_start   <= 1'b1;
                    dbl_carry   <= 1'b0;
                    dbl_step    <= dbl_step_inc;
                    dbl_end     <= 1'b0;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_start   <= 1'b0;
                    dbl_end     <= 1'b0;
                    dbl_1more   <= 1'b0;
                    end
                end
            5'd2:
                begin
                case(dbl_1more)
                    1'b0: 
                        begin
                        dbl_start   <= 1'b0;
                        dbl_step    <= dbl_step;
                        dbl_1more   <= dbl_auvld;
                        end
                    1'b1: 
                        begin
                        dbl_start   <= 1'b1;
                        dbl_step    <= dbl_step_inc;
                        dbl_1more   <= 1'b0;
                        end
                endcase
                if (dbl_auvld)
                    begin
                    dbl_radd    <= TEMP2;
                    dbl_wen     <= ~dbl_wen;
                    dbl_wadd    <= TEMP3;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_MUL;
                    dbl_const   <= INIT;
                    dbl_carry   <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                end
            5'd3:
                begin
                case(dbl_1more)
                    1'b0: 
                        begin
                        dbl_start   <= 1'b0;
                        dbl_step    <= dbl_step;
                        dbl_1more   <= dbl_auvld;
                        end
                    1'b1: 
                        begin
                        dbl_start   <= 1'b1;
                        dbl_step    <= dbl_step_inc;
                        dbl_1more   <= 1'b0;
                        end
                endcase
                if (dbl_auvld)
                    begin
                    dbl_radd    <= TEMP4;
                    dbl_wen     <= ~dbl_wen;
                    dbl_wadd    <= TEMP4;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_MUL;
                    dbl_const   <= INIT;
                    dbl_carry   <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                end
            5'd4:
                begin
                if (dbl_auvld)
                    begin
                    dbl_radd    <= TEMP4;
                    dbl_wen     <= 1'b1;
                    dbl_wadd    <= TEMP4;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_MUL;
                    dbl_const   <= 256'd3;
                    dbl_start   <= 1'b1;
                    dbl_end     <= 1'b0;
                    dbl_carry   <= 1'b0;
                    dbl_step    <= dbl_step_inc;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_start   <= 1'b0;
                    dbl_end     <= 1'b0;
                    dbl_1more   <= 1'b0;
                    end
                end
            5'd5:
                begin
                case(dbl_1more)
                    1'b0: 
                        begin
                        dbl_start   <= 1'b0;
                        dbl_step    <= dbl_step;
                        dbl_radd    <= dbl_auvld? TEMP4: dbl_radd;
                        dbl_1more   <= dbl_auvld;
                        end
                    1'b1: 
                        begin
                        dbl_start   <= 1'b1;
                        dbl_step    <= dbl_step_inc;
                        dbl_radd    <= TEMP3;
                        dbl_1more   <= 1'b0;
                        end
                endcase
                if (dbl_auvld)
                    begin
                    dbl_wen     <= ~dbl_wen;
                    dbl_wadd    <= TEMP4;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_FA;
                    dbl_const   <= INIT;
                    dbl_carry   <= 1'b1;
                    dbl_end     <= 1'b0;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                end
            5'd6:
                begin
                case(dbl_1more)
                    1'b0: 
                        begin
                        dbl_start   <= 1'b0;
                        dbl_step    <= dbl_step;
                        dbl_1more   <= dbl_auvld;
                        end
                    1'b1: 
                        begin
                        dbl_start   <= 1'b1;
                        dbl_step    <= dbl_step_inc;
                        dbl_1more   <= 1'b0;
                        end
                endcase
                if (dbl_auvld)
                    begin
                    dbl_radd    <= TEMP1;
                    dbl_wen     <= ~dbl_wen;
                    dbl_wadd    <= TEMP3;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_MUL;
                    dbl_const   <= INIT;
                    dbl_carry   <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                end
            5'd7:
                begin
                case(dbl_1more)
                     1'b0: 
                         begin
                         dbl_start   <= 1'b0;
                         dbl_step    <= dbl_step;
                         dbl_radd    <= dbl_auvld? TEMP0: dbl_radd;
                         dbl_1more  <= dbl_auvld;
                         end
                     1'b1: 
                         begin
                         dbl_start   <= 1'b1;
                         dbl_step    <= dbl_step_inc;
                         dbl_radd    <= TEMP4;
                         dbl_1more  <= 1'b0;
                         end
                endcase
                if (dbl_auvld)
                    begin
                    dbl_wen     <= ~dbl_wen;
                    dbl_wadd    <= TEMP4;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_MUL;
                    dbl_const   <= INIT;
                    dbl_carry   <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                end
            5'd8:
                begin
                case(dbl_1more)
                    1'b0: 
                        begin
                        dbl_start   <= 1'b0;
                        dbl_step    <= dbl_step;
                        dbl_1more   <= dbl_auvld;
                        end
                    1'b1: 
                        begin
                        dbl_start   <= 1'b1;
                        dbl_step    <= dbl_step_inc;
                        dbl_1more   <= 1'b0;
                        end
                endcase
                if (dbl_auvld)
                    begin
                    dbl_radd    <= TEMP4;
                    dbl_wen     <= ~dbl_wen;
                    dbl_wadd    <= TEMP5;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_MUL;
                    dbl_const   <= INIT;
                    dbl_carry   <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                end
            5'd9:
                begin
                if (dbl_auvld)
                    begin
                    dbl_radd    <= TEMP5;
                    dbl_wen     <= 1'b1;
                    dbl_wadd    <= TEMP4;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_MUL;
                    dbl_const   <= 256'd4;
                    dbl_start   <= 1'b1;
                    dbl_carry   <= 1'b0;
                    dbl_end     <= 1'b0;
                    dbl_step    <= dbl_step_inc;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_start   <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                end
            5'd10:
                begin
                case(dbl_1more)
                    1'b0: 
                        begin
                        dbl_start   <= 1'b0;
                        dbl_step    <= dbl_step;
                        dbl_1more   <= dbl_auvld;
                        end
                    1'b1: 
                        begin
                        dbl_start   <= 1'b1;
                        dbl_step    <= dbl_step_inc;
                        dbl_1more   <= 1'b0;
                        end
                endcase
                if (dbl_auvld)
                    begin
                    dbl_radd    <= TEMP3;
                    dbl_wen     <= ~dbl_wen;
                    dbl_wadd    <= TEMP5;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_MUL;
                    dbl_const   <= INIT;
                    dbl_carry   <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                end
            5'd11:
                begin
                if (dbl_auvld)
                    begin
                    dbl_radd    <= TEMP5;
                    dbl_wen     <= 1'b1;
                    dbl_wadd    <= TEMP6;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_MUL;
                    dbl_const   <= 256'd2;
                    dbl_start   <= 1'b1;
                    dbl_carry   <= 1'b0;
                    dbl_end     <= 1'b0;
                    dbl_step    <= dbl_step_inc;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_start   <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                end
            5'd12:
                begin
                case(dbl_1more)
                    1'b0: 
                        begin
                        dbl_start   <= 1'b0;
                        dbl_step    <= dbl_step;
                        dbl_radd    <= dbl_auvld? TEMP7: dbl_radd;
                        dbl_1more   <= dbl_auvld;
                        end
                    1'b1: 
                        begin
                        dbl_start   <= 1'b1;
                        dbl_step    <= dbl_step_inc;
                        dbl_radd    <= TEMP6;
                        dbl_1more   <= 1'b0;
                        end
                endcase
                if (dbl_auvld)
                    begin
                    dbl_wen     <= ~dbl_wen;
                    dbl_wadd    <= TEMP7;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_FA;
                    dbl_const   <= INIT;
                    dbl_carry   <= 1'b1;
                    dbl_end     <= 1'b0;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                end
            5'd13:
                begin
                case(dbl_1more)
                    1'b0: 
                        begin
                        dbl_start   <= 1'b0;
                        dbl_step    <= dbl_step;
                        dbl_radd    <= dbl_auvld? TEMP1: dbl_radd;
                        dbl_1more   <= dbl_auvld;
                        end
                    1'b1: 
                        begin
                        dbl_start   <= 1'b1;
                        dbl_step    <= dbl_step_inc;
                        dbl_radd    <= TEMP2;
                        dbl_1more   <= 1'b0;
                        end
                endcase
                if (dbl_auvld)
                    begin
                    dbl_wen     <= ~dbl_wen;
                    dbl_wadd    <= TEMP0;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_MUL;
                    dbl_const   <= INIT;
                    dbl_carry   <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                end
            5'd14:
                begin
                if (dbl_auvld)
                    begin
                    dbl_radd    <= TEMP2;
                    dbl_wen     <= 1'b1;
                    dbl_wadd    <= TEMP2;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_MUL;
                    dbl_const   <= 256'd2;
                    dbl_start   <= 1'b1;
                    dbl_carry   <= 1'b0;
                    dbl_end     <= 1'b0;
                    dbl_step    <= dbl_step_inc;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_start   <= 1'b0;
                    dbl_end     <= 1'b0;
                    dbl_1more   <= 1'b0;
                    end
                end
            5'd15:
                begin
                if (dbl_auvld)
                    begin
                    dbl_radd    <= TEMP4;
                    dbl_wen     <= 1'b1;
                    dbl_wadd    <= TEMP2;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_MUL;
                    dbl_const   <= 256'd8;
                    dbl_start   <= 1'b1;
                    dbl_carry   <= 1'b0;
                    dbl_end     <= 1'b0;
                    dbl_step    <= dbl_step_inc;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_start   <= 1'b0;
                    dbl_end     <= 1'b0;
                    dbl_1more   <= 1'b0;
                    end
                end 
            5'd16:
                begin
                case(dbl_1more)
                    1'b0: 
                        begin
                        dbl_start   <= 1'b0;
                        dbl_step    <= dbl_step;
                        dbl_radd    <= dbl_auvld? TEMP0: dbl_radd;
                        dbl_1more   <= dbl_auvld;
                        end
                    1'b1: 
                        begin
                        dbl_start   <= 1'b1;
                        dbl_step    <= dbl_step_inc;
                        dbl_radd    <= TEMP5;
                        dbl_1more   <= 1'b0;
                        end
                endcase
                if (dbl_auvld)
                    begin
                    dbl_wen     <= ~dbl_wen;
                    dbl_wadd    <= TEMP4;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_FA;
                    dbl_const   <= INIT;
                    dbl_carry   <= 1'b1;
                    dbl_end     <= 1'b0;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                end
            5'd17:
                begin
                case(dbl_1more)
                    1'b0: 
                        begin
                        dbl_start   <= 1'b0;
                        dbl_step    <= dbl_step;
                        dbl_radd    <= dbl_auvld? TEMP3: dbl_radd;
                        dbl_1more   <= dbl_auvld;
                        end
                    1'b1: 
                        begin
                        dbl_start   <= 1'b1;
                        dbl_step    <= dbl_step_inc;
                        dbl_radd    <= TEMP5;
                        dbl_1more   <= 1'b0;
                        end
                endcase 
                if (dbl_auvld)
                    begin
                    dbl_wen     <= ~dbl_wen;
                    dbl_wadd    <= TEMP5;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_MUL;
                    dbl_const   <= INIT;
                    dbl_carry   <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                end
            5'd18:
                begin
                case(dbl_1more)
                    1'b0: 
                        begin
                        dbl_start   <= 1'b0;
                        dbl_step    <= dbl_step;
                        dbl_radd    <= dbl_auvld? TEMP4: dbl_radd;
                        dbl_1more   <= dbl_auvld;
                        end
                    1'b1: 
                        begin
                        dbl_start   <= 1'b1;
                        dbl_step    <= dbl_step_inc;
                        dbl_radd    <= TEMP3;
                        dbl_1more   <= 1'b0;
                        end
                endcase
                if (dbl_auvld)
                    begin
                    dbl_wen     <= ~dbl_wen;
                    dbl_wadd    <= TEMP3;
                    dbl_wdat    <= dbl_audat;

                    dbl_opcode  <= OP_FA;
                    dbl_const   <= INIT;
                    dbl_carry   <= 1'b1;
                    dbl_end     <= 1'b0;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_end     <= 1'b0;
                    end
                end
            5'd19:
                begin
                if (dbl_auvld)
                    begin
                    dbl_const   <= INIT;
                    dbl_wen     <= 1'b1;
                    dbl_wadd    <= TEMP1;
                    dbl_wdat    <= dbl_audat;
                    dbl_end     <= 1'b1;
                    dbl_step    <= dbl_step_inc;
                    end
                else
                    begin
                    dbl_wen     <= 1'b0;
                    dbl_start   <= 1'b0;
                    dbl_end     <= 1'b0;
                    dbl_1more   <= 1'b0;
                    end
                end
            default:
                begin
                dbl_radd    <= INIT;
                dbl_wen     <= INIT;
                dbl_wadd    <= INIT;
                dbl_wdat    <= INIT;

                dbl_start   <= INIT;
                dbl_opcode  <= INIT;
                dbl_const   <= INIT;
                dbl_carry   <= INIT;

                dbl_step    <= INIT;
                dbl_end     <= INIT;

                dbl_1more   <= INIT;
                dbl_en_sticky   <= INIT;
                end
        endcase
        end
    end

endmodule