data/full_repos/permissive/414867793/Universal_Gates/And_Gate/AND_G_tb.v
1: b'%Error: data/full_repos/permissive/414867793/Universal_Gates/And_Gate/AND_G_tb.v:2: Cannot find include file: AND_G.v\n`include "AND_G.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/414867793/Universal_Gates/And_Gate,data/full_repos/permissive/414867793/AND_G.v\n             data/full_repos/permissive/414867793/Universal_Gates/And_Gate,data/full_repos/permissive/414867793/AND_G.v.v\n             data/full_repos/permissive/414867793/Universal_Gates/And_Gate,data/full_repos/permissive/414867793/AND_G.v.sv\n             AND_G.v\n             AND_G.v.v\n             AND_G.v.sv\n             obj_dir/AND_G.v\n             obj_dir/AND_G.v.v\n             obj_dir/AND_G.v.sv\n%Error: data/full_repos/permissive/414867793/Universal_Gates/And_Gate/AND_G_tb.v:8: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("AND_G_tvb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/414867793/Universal_Gates/And_Gate/AND_G_tb.v:9: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(1,AND_G_tb);\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Universal_Gates/And_Gate/AND_G_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Universal_Gates/And_Gate/AND_G_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Universal_Gates/And_Gate/AND_G_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Universal_Gates/And_Gate/AND_G_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n#20\n^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n'
module AND_G_tb();
reg A,B;
wire C;
AND_G uut(A,B,C);
initial begin
  $dumpfile("AND_G_tvb.vcd");
$dumpvars(1,AND_G_tb);

A=0;
B=0;
#20
A=1;
B=0;
#20
A=0;
B=1;
#20
A=1;
B=1;
#20
$display("Test Complete");
end

endmodule
module AND_G_tb();

reg A,B;
wire C;
AND_G uut(A,B,C);
initial begin
  $dumpfile("AND_G_tvb.vcd");
$dumpvars(1,AND_G_tb);

A=0;
B=0;
#20
A=1;
B=0;
#20
A=0;
B=1;
#20
A=1;
B=1;
#20
$display("Test Complete");
end

endmodule