data/full_repos/permissive/42434302/ivltests/pr492.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr492.v:41: Unsupported: Ignoring delay on this delayed statement.\n #60;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr492.v:42: Unsupported: Ignoring delay on this delayed statement.\n   forever #3 clk = ~clk ;  \n           ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr492.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #200 $finish ;\n    ^\n%Warning-INFINITELOOP: data/full_repos/permissive/42434302/ivltests/pr492.v:42: Infinite loop (condition always true)\n                                                                              : ... In instance top\n   forever #3 clk = ~clk ;  \n   ^~~~~~~\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top ;

  reg clk ;
  reg [11:0] x_os_integ, y_os_integ;
  reg [5:0] x_os, y_os;

  initial
	  begin


	  clk = 1'h0 ;
    x_os = 6'h01;
    y_os = 6'h3f;
    x_os_integ = 12'h000;
    y_os_integ = 12'h000;
	  end

  initial
	  begin
	#60;
	  forever #3 clk = ~clk ;
	end

  always @( posedge clk )
    begin

    x_os_integ <= x_os_integ + {{6{x_os[5]}}, {x_os[5:0]}};
    y_os_integ <= y_os_integ + {{6{y_os[5]}}, {y_os[5:0]}};

    $display ("%x %x", x_os_integ, y_os_integ);
    end

  initial
    begin
    #200 $finish ;
    end

endmodule
module top ;


  reg clk ;
  reg [11:0] x_os_integ, y_os_integ;
  reg [5:0] x_os, y_os;

  initial
	  begin


	  clk = 1'h0 ;
    x_os = 6'h01;
    y_os = 6'h3f;
    x_os_integ = 12'h000;
    y_os_integ = 12'h000;
	  end

  initial
	  begin
	#60;
	  forever #3 clk = ~clk ;
	end

  always @( posedge clk )
    begin

    x_os_integ <= x_os_integ + {{6{x_os[5]}}, {x_os[5:0]}};
    y_os_integ <= y_os_integ + {{6{y_os[5]}}, {y_os[5:0]}};

    $display ("%x %x", x_os_integ, y_os_integ);
    end

  initial
    begin
    #200 $finish ;
    end

endmodule