data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_pipelining/bdw_work/modules/dut/BASIC/v_rtl/dut_Add_32Ux32U_33U_4.v
data/verilator_xmls/7b6acc92-750f-4044-aae3-a8b398687a1e.xml
module dut_Add_32Ux32U_33U_4 (
	in2,
	in1,
	out1
	);
input [31:0] in2,
	in1;
output [32:0] out1;
wire [32:0] asc001;

assign asc001 = 
	+(in2)
	+(in1);

assign out1 = asc001;
endmodule
module dut_Add_32Ux32U_33U_4 (
	in2,
	in1,
	out1
	);

input [31:0] in2,
	in1;
output [32:0] out1;
wire [32:0] asc001;

assign asc001 = 
	+(in2)
	+(in1);

assign out1 = asc001;
endmodule