data/full_repos/permissive/418819021/lab-05/bus_interface_unit.v
1: b'%Error: data/full_repos/permissive/418819021/lab-05/bus_interface_unit.v:5: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418819021/lab-05,data/full_repos/permissive/418819021/defines.vh\n             data/full_repos/permissive/418819021/lab-05,data/full_repos/permissive/418819021/defines.vh.v\n             data/full_repos/permissive/418819021/lab-05,data/full_repos/permissive/418819021/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/418819021/lab-05/bus_interface_unit.v:12: Define or directive not defined: \'`GROUP_COUNT\'\n input  wire [ `GROUP_COUNT-1:0] opcode_group ,\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/bus_interface_unit.v:14: Define or directive not defined: \'`SIGNAL_COUNT\'\n input  wire [`SIGNAL_COUNT-1:0] signals      ,\n              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/bus_interface_unit.v:32: Define or directive not defined: \'`CONTROL_MEM_READ\'\n assign should_load   = signals[`CONTROL_MEM_READ];\n                                ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/bus_interface_unit.v:32: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign should_load   = signals[`CONTROL_MEM_READ];\n                                                 ^\n%Error: data/full_repos/permissive/418819021/lab-05/bus_interface_unit.v:33: Define or directive not defined: \'`CONTROL_MEM_WRITE\'\n assign should_store  = signals[`CONTROL_MEM_WRITE];\n                                ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/bus_interface_unit.v:33: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign should_store  = signals[`CONTROL_MEM_WRITE];\n                                                  ^\n%Error: data/full_repos/permissive/418819021/lab-05/bus_interface_unit.v:35: Define or directive not defined: \'`GROUP_LOAD_INDIRECT\'\n  (opcode_group[`GROUP_LOAD_INDIRECT] ||\n                ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/bus_interface_unit.v:35: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  (opcode_group[`GROUP_LOAD_INDIRECT] ||\n                                    ^\n%Error: data/full_repos/permissive/418819021/lab-05/bus_interface_unit.v:36: Define or directive not defined: \'`GROUP_STORE_INDIRECT\'\n   opcode_group[`GROUP_STORE_INDIRECT]);\n                ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/bus_interface_unit.v:37: Define or directive not defined: \'`CONTROL_MEM_READ\'\n assign mem_access = signals[`CONTROL_MEM_READ] ||\n                             ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/bus_interface_unit.v:37: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign mem_access = signals[`CONTROL_MEM_READ] ||\n                                              ^\n%Error: data/full_repos/permissive/418819021/lab-05/bus_interface_unit.v:38: Define or directive not defined: \'`CONTROL_MEM_WRITE\'\n  signals[`CONTROL_MEM_WRITE];\n          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/bus_interface_unit.v:50: Define or directive not defined: \'`CONTROL_MEM_WRITE\'\n assign mem_we = (mem_cs && signals[`CONTROL_MEM_WRITE]) ? 1\'b1 :\n                                    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/bus_interface_unit.v:50: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign mem_we = (mem_cs && signals[`CONTROL_MEM_WRITE]) ? 1\'b1 :\n                                                      ^\n%Error: data/full_repos/permissive/418819021/lab-05/bus_interface_unit.v:51: Define or directive not defined: \'`CONTROL_MEM_READ\'\n  (mem_cs && signals[`CONTROL_MEM_READ])  ? 1\'b0 : 1\'bx;\n                     ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/bus_interface_unit.v:52: Define or directive not defined: \'`CONTROL_MEM_READ\'\n assign mem_oe = (mem_cs && signals[`CONTROL_MEM_READ])  ? 1\'b1 :\n                                    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/bus_interface_unit.v:52: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign mem_oe = (mem_cs && signals[`CONTROL_MEM_READ])  ? 1\'b1 :\n                                                     ^\n%Error: data/full_repos/permissive/418819021/lab-05/bus_interface_unit.v:53: Define or directive not defined: \'`CONTROL_MEM_WRITE\'\n  (mem_cs && signals[`CONTROL_MEM_WRITE]) ? 1\'b0 : 1\'bx;\n                     ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 19 error(s)\n'
module bus_interface_unit #(
	parameter MEM_START_ADDR = 16'h40,
	parameter MEM_STOP_ADDR  = 16'hBF,
	parameter DATA_WIDTH     = 8     ,
	parameter ADDR_WIDTH     = 16
) (
	input  wire [ `GROUP_COUNT-1:0] opcode_group ,
	input  wire [             11:0] opcode_imd   ,
	input  wire [`SIGNAL_COUNT-1:0] signals      ,
	input  wire [   DATA_WIDTH-1:0] data_to_store,
	input  wire [   ADDR_WIDTH-1:0] indirect_addr,
	output wire [   ADDR_WIDTH-1:0] bus_addr     ,
	inout  wire [   DATA_WIDTH-1:0] bus_data     ,
	output wire                     mem_cs       ,
	output wire                     mem_we       ,
	output wire                     mem_oe
);

	wire [ADDR_WIDTH-1:0] internal_mem_addr ;
	wire                  mem_access        ;
    wire                  io_access         ;
	wire                  mem_addr_is_in_mem;
	wire                  uses_indirect     ;
	wire                  should_store      ;
	wire                  should_load       ;

	assign should_load   = signals[`CONTROL_MEM_READ];
	assign should_store  = signals[`CONTROL_MEM_WRITE];
	assign uses_indirect =
		(opcode_group[`GROUP_LOAD_INDIRECT] ||
			opcode_group[`GROUP_STORE_INDIRECT]);
	assign mem_access = signals[`CONTROL_MEM_READ] ||
		signals[`CONTROL_MEM_WRITE];
	assign mem_addr_is_in_mem = mem_access &&
		(internal_mem_addr >= MEM_START_ADDR &&
			internal_mem_addr <= MEM_STOP_ADDR);


	assign internal_mem_addr =
		uses_indirect ?
		indirect_addr :
		{4'b0, opcode_imd};

	assign mem_cs = mem_addr_is_in_mem;
	assign mem_we = (mem_cs && signals[`CONTROL_MEM_WRITE]) ? 1'b1 :
		(mem_cs && signals[`CONTROL_MEM_READ])  ? 1'b0 : 1'bx;
	assign mem_oe = (mem_cs && signals[`CONTROL_MEM_READ])  ? 1'b1 :
		(mem_cs && signals[`CONTROL_MEM_WRITE]) ? 1'b0 : 1'bx;




	assign bus_addr = mem_cs ? internal_mem_addr - MEM_START_ADDR :
		{ADDR_WIDTH{1'bx}};

	assign bus_data = should_store ? data_to_store : {DATA_WIDTH{1'bz}};

endmodule
module bus_interface_unit #(
	parameter MEM_START_ADDR = 16'h40,
	parameter MEM_STOP_ADDR  = 16'hBF,
	parameter DATA_WIDTH     = 8     ,
	parameter ADDR_WIDTH     = 16
) (
	input  wire [ `GROUP_COUNT-1:0] opcode_group ,
	input  wire [             11:0] opcode_imd   ,
	input  wire [`SIGNAL_COUNT-1:0] signals      ,
	input  wire [   DATA_WIDTH-1:0] data_to_store,
	input  wire [   ADDR_WIDTH-1:0] indirect_addr,
	output wire [   ADDR_WIDTH-1:0] bus_addr     ,
	inout  wire [   DATA_WIDTH-1:0] bus_data     ,
	output wire                     mem_cs       ,
	output wire                     mem_we       ,
	output wire                     mem_oe
);


	wire [ADDR_WIDTH-1:0] internal_mem_addr ;
	wire                  mem_access        ;
    wire                  io_access         ;
	wire                  mem_addr_is_in_mem;
	wire                  uses_indirect     ;
	wire                  should_store      ;
	wire                  should_load       ;

	assign should_load   = signals[`CONTROL_MEM_READ];
	assign should_store  = signals[`CONTROL_MEM_WRITE];
	assign uses_indirect =
		(opcode_group[`GROUP_LOAD_INDIRECT] ||
			opcode_group[`GROUP_STORE_INDIRECT]);
	assign mem_access = signals[`CONTROL_MEM_READ] ||
		signals[`CONTROL_MEM_WRITE];
	assign mem_addr_is_in_mem = mem_access &&
		(internal_mem_addr >= MEM_START_ADDR &&
			internal_mem_addr <= MEM_STOP_ADDR);


	assign internal_mem_addr =
		uses_indirect ?
		indirect_addr :
		{4'b0, opcode_imd};

	assign mem_cs = mem_addr_is_in_mem;
	assign mem_we = (mem_cs && signals[`CONTROL_MEM_WRITE]) ? 1'b1 :
		(mem_cs && signals[`CONTROL_MEM_READ])  ? 1'b0 : 1'bx;
	assign mem_oe = (mem_cs && signals[`CONTROL_MEM_READ])  ? 1'b1 :
		(mem_cs && signals[`CONTROL_MEM_WRITE]) ? 1'b0 : 1'bx;




	assign bus_addr = mem_cs ? internal_mem_addr - MEM_START_ADDR :
		{ADDR_WIDTH{1'bx}};

	assign bus_data = should_store ? data_to_store : {DATA_WIDTH{1'bz}};

endmodule