data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_xreg.v
1: b'%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_xreg.v:11: Cannot find include file: pa_soc_param.v\n`include "pa_soc_param.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/485610894/tianqn-mips-env/rtl,data/full_repos/permissive/485610894/pa_soc_param.v\n             data/full_repos/permissive/485610894/tianqn-mips-env/rtl,data/full_repos/permissive/485610894/pa_soc_param.v.v\n             data/full_repos/permissive/485610894/tianqn-mips-env/rtl,data/full_repos/permissive/485610894/pa_soc_param.v.sv\n             pa_soc_param.v\n             pa_soc_param.v.v\n             pa_soc_param.v.sv\n             obj_dir/pa_soc_param.v\n             obj_dir/pa_soc_param.v.v\n             obj_dir/pa_soc_param.v.sv\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_xreg.v:17: Define or directive not defined: \'`REG_BUS_WIDTH\'\n    input  wire [`REG_BUS_WIDTH-1:0]    rs1_addr,\n                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_xreg.v:18: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    output wire [`DATA_BUS_WIDTH-1:0]   rs1_data,\n                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_xreg.v:20: Define or directive not defined: \'`REG_BUS_WIDTH\'\n    input  wire [`REG_BUS_WIDTH-1:0]    rs2_addr,\n                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_xreg.v:21: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    output wire [`DATA_BUS_WIDTH-1:0]   rs2_data,\n                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_xreg.v:23: Define or directive not defined: \'`REG_BUS_WIDTH\'\n    input  wire [`REG_BUS_WIDTH-1:0]    rd_addr,\n                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_xreg.v:24: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    input  wire [`DATA_BUS_WIDTH-1:0]   rd_data,\n                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_xreg.v:28: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nreg  [`DATA_BUS_WIDTH-1:0]              _xreg[0:`REG_NUM-1];\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_xreg.v:28: Define or directive not defined: \'`REG_NUM\'\nreg  [`DATA_BUS_WIDTH-1:0]              _xreg[0:`REG_NUM-1];\n                                                ^~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_xreg.v:32: Define or directive not defined: \'`ZERO_WORD\'\n        _xreg[idx] = `ZERO_WORD;\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_xreg.v:32: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        _xreg[idx] = `ZERO_WORD;\n                               ^\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_xreg.v:39: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n            _xreg[rd_addr] <= rd_data[`DATA_BUS_WIDTH-1:0];\n                                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_xreg.v:44: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nreg  [`DATA_BUS_WIDTH-1:0]              _rs1;\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_xreg.v:45: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nreg  [`DATA_BUS_WIDTH-1:0]              _rs2;\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_xreg.v:49: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n        _rs1[`DATA_BUS_WIDTH-1:0] = `ZERO_WORD;\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_xreg.v:49: Define or directive not defined: \'`ZERO_WORD\'\n        _rs1[`DATA_BUS_WIDTH-1:0] = `ZERO_WORD;\n                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_xreg.v:49: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        _rs1[`DATA_BUS_WIDTH-1:0] = `ZERO_WORD;\n                                              ^\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_xreg.v:52: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n        _rs1[`DATA_BUS_WIDTH-1:0] = _xreg[rs1_addr];\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_xreg.v:58: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n        _rs2[`DATA_BUS_WIDTH-1:0] = `ZERO_WORD;\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_xreg.v:58: Define or directive not defined: \'`ZERO_WORD\'\n        _rs2[`DATA_BUS_WIDTH-1:0] = `ZERO_WORD;\n                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_xreg.v:58: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        _rs2[`DATA_BUS_WIDTH-1:0] = `ZERO_WORD;\n                                              ^\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_xreg.v:61: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n        _rs2[`DATA_BUS_WIDTH-1:0] = _xreg[rs2_addr];\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_xreg.v:65: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nassign rs1_data[`DATA_BUS_WIDTH-1:0] = _rs1[`DATA_BUS_WIDTH-1:0];\n                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_xreg.v:65: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nassign rs1_data[`DATA_BUS_WIDTH-1:0] = _rs1[`DATA_BUS_WIDTH-1:0];\n                                            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_xreg.v:66: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nassign rs2_data[`DATA_BUS_WIDTH-1:0] = _rs2[`DATA_BUS_WIDTH-1:0];\n                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/tianqn-mips-env/rtl/pa_soc_xreg.v:66: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nassign rs2_data[`DATA_BUS_WIDTH-1:0] = _rs2[`DATA_BUS_WIDTH-1:0];\n                                            ^~~~~~~~~~~~~~~\n%Error: Exiting due to 26 error(s)\n'
module pa_soc_xreg (
    input  wire                         clk_i,
    input  wire                         rst_n_i,

    input  wire [`REG_BUS_WIDTH-1:0]    rs1_addr,
    output wire [`DATA_BUS_WIDTH-1:0]   rs1_data,

    input  wire [`REG_BUS_WIDTH-1:0]    rs2_addr,
    output wire [`DATA_BUS_WIDTH-1:0]   rs2_data,

    input  wire [`REG_BUS_WIDTH-1:0]    rd_addr,
    input  wire [`DATA_BUS_WIDTH-1:0]   rd_data,
    input  wire                         rd_data_vld
);

reg  [`DATA_BUS_WIDTH-1:0]              _xreg[0:`REG_NUM-1];

initial begin
    for (integer idx=0; idx<32; idx=idx+1) begin
        _xreg[idx] = `ZERO_WORD;
    end
end

always @ (posedge clk_i) begin
    if (rst_n_i) begin
        if (rd_data_vld && (5'd0 != rd_addr)) begin
            _xreg[rd_addr] <= rd_data[`DATA_BUS_WIDTH-1:0];
        end
    end
end

reg  [`DATA_BUS_WIDTH-1:0]              _rs1;
reg  [`DATA_BUS_WIDTH-1:0]              _rs2;

always @ (*) begin
    if (5'd0 == rs1_addr) begin
        _rs1[`DATA_BUS_WIDTH-1:0] = `ZERO_WORD;
    end
    else begin
        _rs1[`DATA_BUS_WIDTH-1:0] = _xreg[rs1_addr];
    end
end

always @ (*) begin
    if (5'd0 == rs2_addr) begin
        _rs2[`DATA_BUS_WIDTH-1:0] = `ZERO_WORD;
    end
    else begin
        _rs2[`DATA_BUS_WIDTH-1:0] = _xreg[rs2_addr];
    end
end

assign rs1_data[`DATA_BUS_WIDTH-1:0] = _rs1[`DATA_BUS_WIDTH-1:0];
assign rs2_data[`DATA_BUS_WIDTH-1:0] = _rs2[`DATA_BUS_WIDTH-1:0];

endmodule
module pa_soc_xreg (
    input  wire                         clk_i,
    input  wire                         rst_n_i,

    input  wire [`REG_BUS_WIDTH-1:0]    rs1_addr,
    output wire [`DATA_BUS_WIDTH-1:0]   rs1_data,

    input  wire [`REG_BUS_WIDTH-1:0]    rs2_addr,
    output wire [`DATA_BUS_WIDTH-1:0]   rs2_data,

    input  wire [`REG_BUS_WIDTH-1:0]    rd_addr,
    input  wire [`DATA_BUS_WIDTH-1:0]   rd_data,
    input  wire                         rd_data_vld
);


reg  [`DATA_BUS_WIDTH-1:0]              _xreg[0:`REG_NUM-1];

initial begin
    for (integer idx=0; idx<32; idx=idx+1) begin
        _xreg[idx] = `ZERO_WORD;
    end
end

always @ (posedge clk_i) begin
    if (rst_n_i) begin
        if (rd_data_vld && (5'd0 != rd_addr)) begin
            _xreg[rd_addr] <= rd_data[`DATA_BUS_WIDTH-1:0];
        end
    end
end

reg  [`DATA_BUS_WIDTH-1:0]              _rs1;
reg  [`DATA_BUS_WIDTH-1:0]              _rs2;

always @ (*) begin
    if (5'd0 == rs1_addr) begin
        _rs1[`DATA_BUS_WIDTH-1:0] = `ZERO_WORD;
    end
    else begin
        _rs1[`DATA_BUS_WIDTH-1:0] = _xreg[rs1_addr];
    end
end

always @ (*) begin
    if (5'd0 == rs2_addr) begin
        _rs2[`DATA_BUS_WIDTH-1:0] = `ZERO_WORD;
    end
    else begin
        _rs2[`DATA_BUS_WIDTH-1:0] = _xreg[rs2_addr];
    end
end

assign rs1_data[`DATA_BUS_WIDTH-1:0] = _rs1[`DATA_BUS_WIDTH-1:0];
assign rs2_data[`DATA_BUS_WIDTH-1:0] = _rs2[`DATA_BUS_WIDTH-1:0];

endmodule