data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/complement_2.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/complement_2.v:51: Cannot find file containing module: 'full_sub'\nfull_sub\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl,data/full_repos/permissive/530013823/full_sub\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl,data/full_repos/permissive/530013823/full_sub.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl,data/full_repos/permissive/530013823/full_sub.sv\n             full_sub\n             full_sub.v\n             full_sub.sv\n             obj_dir/full_sub\n             obj_dir/full_sub.v\n             obj_dir/full_sub.sv\n%Error: Exiting due to 1 error(s)\n"
module complement_2
    (
     clk,
     rst,
     din,
     en,
     dout
     );




parameter           WIDTH   = 256;

localparam          INIT    = 0;




input               clk;
input               rst;

input [WIDTH-1:0]   din;
input               en;

output [WIDTH-1:0]  dout;




reg [WIDTH-1:0]     dout;




wire [WIDTH-1:0]    comp_2;

full_sub
    #(
      .WIDTH(WIDTH)
      ) ifull_sub
     (
     .a({WIDTH{1'b0}}),
     .b(din),
     .sub(comp_2),
     .c()
      );

always @(posedge clk)
    begin
    if (rst)        dout    <= INIT;
    else if (en)    dout    <= comp_2;
    else            dout    <= din;
    end

endmodule
module complement_2
    (
     clk,
     rst,
     din,
     en,
     dout
     );





parameter           WIDTH   = 256;

localparam          INIT    = 0;




input               clk;
input               rst;

input [WIDTH-1:0]   din;
input               en;

output [WIDTH-1:0]  dout;




reg [WIDTH-1:0]     dout;




wire [WIDTH-1:0]    comp_2;

full_sub
    #(
      .WIDTH(WIDTH)
      ) ifull_sub
     (
     .a({WIDTH{1'b0}}),
     .b(din),
     .sub(comp_2),
     .c()
      );

always @(posedge clk)
    begin
    if (rst)        dout    <= INIT;
    else if (en)    dout    <= comp_2;
    else            dout    <= din;
    end

endmodule