data/full_repos/permissive/463439324/decap/tb_Decap.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/463439324/decap/tb_Decap.v:34: Unsupported: Ignoring delay on this delayed statement.\n always #1 Clk <= ~Clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/463439324/decap/tb_Decap.v:40: Unsupported or unknown PLI call: $fsdbDumpfile\n  $fsdbDumpfile("tb_Decap.fsdb"); \n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/decap/tb_Decap.v:41: Unsupported or unknown PLI call: $fsdbDumpvars\n  $fsdbDumpvars;\n  ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/463439324/decap/tb_Decap.v:97: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/463439324/decap/tb_Decap.v:100: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/463439324/decap/tb_Decap.v:102: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/463439324/decap/tb_Decap.v:104: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/463439324/decap/tb_Decap.v:106: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/463439324/decap/tb_Decap.v:109: Unsupported: Ignoring delay on this delayed statement.\n   #2;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/463439324/decap/tb_Decap.v:124: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/463439324/decap/tb_Decap.v:127: Unsupported: Ignoring delay on this delayed statement.\n  #10000;\n  ^\n%Error: data/full_repos/permissive/463439324/decap/tb_Decap.v:126: Unsupported: wait statements\n  wait(Valid)\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/463439324/decap/tb_Decap.v:131: Unsupported: Ignoring delay on this delayed statement.\n   #2\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/463439324/decap/tb_Decap.v:133: Unsupported: Ignoring delay on this delayed statement.\n   #2;\n   ^\n%Error: Exiting due to 3 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_Decap;

	reg Clk;
	integer i;

	initial begin
		Clk = 1;
	end
	always #1 Clk <= ~Clk;
	initial begin

		$fsdbDumpfile("tb_Decap.fsdb"); 
		$fsdbDumpvars;
	end

	parameter P_WIDTH = 16;
	parameter Q_DEPTH = 10;

	parameter P_WIDTH_K = 8;
	parameter Q_DEPTH_K = 11;

	reg Reset;
	reg [1:0] Cmd;

	reg wr_en_C;
	reg wr_en_sk;
	reg [Q_DEPTH_K-1:0] wr_addr_C;
	reg [Q_DEPTH_K-1:0] wr_addr_sk;

	reg [P_WIDTH_K-1:0] wr_di_C;
	reg [P_WIDTH_K-1:0] wr_di_sk;

	reg [2:0] Addr;

	reg wr_en_k;

	reg [Q_DEPTH_K-1:0] wr_addr_k;

	reg [P_WIDTH_K-1:0] wr_di_k;


	reg wr_en_rho;
	reg [Q_DEPTH_K-1:0] wr_addr_rho;
	reg [P_WIDTH_K-1:0] wr_di_rho;


	wire [31:0] out_r;
	wire [31:0] out_k;






	
	reg	[15:0] ram_C [0:2047];
	reg [7:0] ram_sk [0:2047];
	reg [7:0] ram_k [0:2047];
	reg [7:0] ram_rho [0:2047];

	wire Valid;

	initial begin
		$display("initial memory...");
	    $readmemh("C_bar_hex.txt", ram_C);
	    $readmemh("sk_hex.txt", ram_sk);
	    $readmemh("k_bar_hex.txt", ram_k);
	    $readmemh("rho_hex.txt", ram_rho);
		#20;
		Reset = 1;
		Cmd = 0;
		#20;
		Reset = 0;
		#10;
		Cmd = 1;
		#10;
		Cmd = 0;
		#10;
		for (i=0; i<2047; i=i+1)
		begin
			#2;
			wr_en_C = 1;
			wr_en_sk = 1;
			wr_en_k = 1;
			wr_en_rho = 1;
			wr_addr_C = i;
			wr_addr_sk = i;
			wr_addr_k = i;
			wr_addr_rho = i;
			wr_di_C = ram_C[i];
			wr_di_sk = ram_sk[i];
			wr_di_k = ram_k[i];
			wr_di_rho = ram_rho[i];
		end
		Cmd = 3;
		#10;

		wait(Valid)
		#10000;

		for(i=0;i<8;i=i+1)
		begin
			#2
			Addr=i;
			#2;
			$display("%d r: %h",i ,out_r);
			$display("%d k: %h",i ,out_k);
		end

		$writememh("r_decap.txt",decapsualtion0.mem_r.ram);
		$writememh("mem_rho_decap.txt",decapsualtion0.mem_rho.ram);













































		$finish;
	end

	decapsualtion decapsualtion0(
		.Clk(Clk), 
		.Reset(Reset),
		.Cmd(Cmd),
		.wr_en_k(wr_en_k), .wr_addr_k(wr_addr_k), .wr_di_k(wr_di_k),
		.wr_en_r(), .wr_addr_r(), .wr_di_r(),
		.wr_en_C(wr_en_C), .wr_addr_C(wr_addr_C), .wr_di_C(wr_di_C),
		.wr_en_sk(wr_en_sk), .wr_addr_sk(wr_addr_sk), .wr_di_sk(wr_di_sk),
		.wr_en_rho(wr_en_rho), .wr_addr_rho(wr_addr_rho), .wr_di_rho(wr_di_rho),
		.out_addr(Addr),
		.out_r(out_r), .out_k(out_k), .Valid(Valid));

endmodule
module tb_Decap;


	reg Clk;
	integer i;

	initial begin
		Clk = 1;
	end
	always #1 Clk <= ~Clk;
	initial begin

		$fsdbDumpfile("tb_Decap.fsdb"); 
		$fsdbDumpvars;
	end

	parameter P_WIDTH = 16;
	parameter Q_DEPTH = 10;

	parameter P_WIDTH_K = 8;
	parameter Q_DEPTH_K = 11;

	reg Reset;
	reg [1:0] Cmd;

	reg wr_en_C;
	reg wr_en_sk;
	reg [Q_DEPTH_K-1:0] wr_addr_C;
	reg [Q_DEPTH_K-1:0] wr_addr_sk;

	reg [P_WIDTH_K-1:0] wr_di_C;
	reg [P_WIDTH_K-1:0] wr_di_sk;

	reg [2:0] Addr;

	reg wr_en_k;

	reg [Q_DEPTH_K-1:0] wr_addr_k;

	reg [P_WIDTH_K-1:0] wr_di_k;


	reg wr_en_rho;
	reg [Q_DEPTH_K-1:0] wr_addr_rho;
	reg [P_WIDTH_K-1:0] wr_di_rho;


	wire [31:0] out_r;
	wire [31:0] out_k;






	
	reg	[15:0] ram_C [0:2047];
	reg [7:0] ram_sk [0:2047];
	reg [7:0] ram_k [0:2047];
	reg [7:0] ram_rho [0:2047];

	wire Valid;

	initial begin
		$display("initial memory...");
	    $readmemh("C_bar_hex.txt", ram_C);
	    $readmemh("sk_hex.txt", ram_sk);
	    $readmemh("k_bar_hex.txt", ram_k);
	    $readmemh("rho_hex.txt", ram_rho);
		#20;
		Reset = 1;
		Cmd = 0;
		#20;
		Reset = 0;
		#10;
		Cmd = 1;
		#10;
		Cmd = 0;
		#10;
		for (i=0; i<2047; i=i+1)
		begin
			#2;
			wr_en_C = 1;
			wr_en_sk = 1;
			wr_en_k = 1;
			wr_en_rho = 1;
			wr_addr_C = i;
			wr_addr_sk = i;
			wr_addr_k = i;
			wr_addr_rho = i;
			wr_di_C = ram_C[i];
			wr_di_sk = ram_sk[i];
			wr_di_k = ram_k[i];
			wr_di_rho = ram_rho[i];
		end
		Cmd = 3;
		#10;

		wait(Valid)
		#10000;

		for(i=0;i<8;i=i+1)
		begin
			#2
			Addr=i;
			#2;
			$display("%d r: %h",i ,out_r);
			$display("%d k: %h",i ,out_k);
		end

		$writememh("r_decap.txt",decapsualtion0.mem_r.ram);
		$writememh("mem_rho_decap.txt",decapsualtion0.mem_rho.ram);













































		$finish;
	end

	decapsualtion decapsualtion0(
		.Clk(Clk), 
		.Reset(Reset),
		.Cmd(Cmd),
		.wr_en_k(wr_en_k), .wr_addr_k(wr_addr_k), .wr_di_k(wr_di_k),
		.wr_en_r(), .wr_addr_r(), .wr_di_r(),
		.wr_en_C(wr_en_C), .wr_addr_C(wr_addr_C), .wr_di_C(wr_di_C),
		.wr_en_sk(wr_en_sk), .wr_addr_sk(wr_addr_sk), .wr_di_sk(wr_di_sk),
		.wr_en_rho(wr_en_rho), .wr_addr_rho(wr_addr_rho), .wr_di_rho(wr_di_rho),
		.out_addr(Addr),
		.out_r(out_r), .out_k(out_k), .Valid(Valid));

endmodule