data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_stim_mem/rtl/wfg_stim_mem_top.sv
1: b"%Error: data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_stim_mem/rtl/wfg_stim_mem_top.sv:44: Cannot find file containing module: 'wfg_stim_mem_wishbone_reg'\n    wfg_stim_mem_wishbone_reg wfg_stim_mem_wishbone_reg (\n    ^~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_stim_mem/rtl,data/full_repos/permissive/500717851/wfg_stim_mem_wishbone_reg\n             data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_stim_mem/rtl,data/full_repos/permissive/500717851/wfg_stim_mem_wishbone_reg.v\n             data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_stim_mem/rtl,data/full_repos/permissive/500717851/wfg_stim_mem_wishbone_reg.sv\n             wfg_stim_mem_wishbone_reg\n             wfg_stim_mem_wishbone_reg.v\n             wfg_stim_mem_wishbone_reg.sv\n             obj_dir/wfg_stim_mem_wishbone_reg\n             obj_dir/wfg_stim_mem_wishbone_reg.v\n             obj_dir/wfg_stim_mem_wishbone_reg.sv\n%Error: data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_stim_mem/rtl/wfg_stim_mem_top.sv:70: Cannot find file containing module: 'wfg_stim_mem'\n    wfg_stim_mem wfg_stim_mem (\n    ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module wfg_stim_mem_top #(
    parameter int BUSW = 32
) (

    input                 wb_clk_i,
    input                 wb_rst_i,
    input                 wbs_stb_i,
    input                 wbs_cyc_i,
    input                 wbs_we_i,
    input  [(BUSW/8-1):0] wbs_sel_i,
    input  [  (BUSW-1):0] wbs_dat_i,
    input  [  (BUSW-1):0] wbs_adr_i,
    output                wbs_ack_o,
    output [  (BUSW-1):0] wbs_dat_o,


    input         wfg_axis_tready_i,
    output        wfg_axis_tvalid_o,
    output [31:0] wfg_axis_tdata_o,


    output        csb1,
    output [ 9:0] addr1,
    input  [31:0] dout1
);






    logic [23: 8] cfg_gain_q;
    logic [ 7: 0] cfg_inc_q;
    logic         ctrl_en_q;
    logic [15: 0] end_val_q;
    logic [15: 0] start_val_q;



    wfg_stim_mem_wishbone_reg wfg_stim_mem_wishbone_reg (
        .wb_clk_i (wb_clk_i),
        .wb_rst_i (wb_rst_i),
        .wbs_stb_i(wbs_stb_i),
        .wbs_cyc_i(wbs_cyc_i),
        .wbs_we_i (wbs_we_i),
        .wbs_sel_i(wbs_sel_i),
        .wbs_dat_i(wbs_dat_i),
        .wbs_adr_i(wbs_adr_i),
        .wbs_ack_o(wbs_ack_o),
        .wbs_dat_o(wbs_dat_o),






        .cfg_gain_q_o (cfg_gain_q),
        .cfg_inc_q_o  (cfg_inc_q),
        .ctrl_en_q_o  (ctrl_en_q),
        .end_val_q_o  (end_val_q),
        .start_val_q_o(start_val_q)


    );

    wfg_stim_mem wfg_stim_mem (
        .clk              (wb_clk_i),
        .rst_n            (!wb_rst_i),
        .wfg_axis_tready_i(wfg_axis_tready_i),
        .wfg_axis_tvalid_o(wfg_axis_tvalid_o),
        .wfg_axis_tdata_o (wfg_axis_tdata_o),
        .ctrl_en_q_i      (ctrl_en_q),
        .end_val_q_i      (end_val_q),
        .start_val_q_i    (start_val_q),
        .cfg_inc_q_i      (cfg_inc_q),
        .cfg_gain_q_i     (cfg_gain_q),
        .csb1             (csb1),
        .addr1            (addr1),
        .dout1            (dout1)
    );

endmodule
module wfg_stim_mem_top #(
    parameter int BUSW = 32
) (

    input                 wb_clk_i,
    input                 wb_rst_i,
    input                 wbs_stb_i,
    input                 wbs_cyc_i,
    input                 wbs_we_i,
    input  [(BUSW/8-1):0] wbs_sel_i,
    input  [  (BUSW-1):0] wbs_dat_i,
    input  [  (BUSW-1):0] wbs_adr_i,
    output                wbs_ack_o,
    output [  (BUSW-1):0] wbs_dat_o,


    input         wfg_axis_tready_i,
    output        wfg_axis_tvalid_o,
    output [31:0] wfg_axis_tdata_o,


    output        csb1,
    output [ 9:0] addr1,
    input  [31:0] dout1
);







    logic [23: 8] cfg_gain_q;
    logic [ 7: 0] cfg_inc_q;
    logic         ctrl_en_q;
    logic [15: 0] end_val_q;
    logic [15: 0] start_val_q;



    wfg_stim_mem_wishbone_reg wfg_stim_mem_wishbone_reg (
        .wb_clk_i (wb_clk_i),
        .wb_rst_i (wb_rst_i),
        .wbs_stb_i(wbs_stb_i),
        .wbs_cyc_i(wbs_cyc_i),
        .wbs_we_i (wbs_we_i),
        .wbs_sel_i(wbs_sel_i),
        .wbs_dat_i(wbs_dat_i),
        .wbs_adr_i(wbs_adr_i),
        .wbs_ack_o(wbs_ack_o),
        .wbs_dat_o(wbs_dat_o),






        .cfg_gain_q_o (cfg_gain_q),
        .cfg_inc_q_o  (cfg_inc_q),
        .ctrl_en_q_o  (ctrl_en_q),
        .end_val_q_o  (end_val_q),
        .start_val_q_o(start_val_q)


    );

    wfg_stim_mem wfg_stim_mem (
        .clk              (wb_clk_i),
        .rst_n            (!wb_rst_i),
        .wfg_axis_tready_i(wfg_axis_tready_i),
        .wfg_axis_tvalid_o(wfg_axis_tvalid_o),
        .wfg_axis_tdata_o (wfg_axis_tdata_o),
        .ctrl_en_q_i      (ctrl_en_q),
        .end_val_q_i      (end_val_q),
        .start_val_q_i    (start_val_q),
        .cfg_inc_q_i      (cfg_inc_q),
        .cfg_gain_q_i     (cfg_gain_q),
        .csb1             (csb1),
        .addr1            (addr1),
        .dout1            (dout1)
    );

endmodule