data/full_repos/permissive/448192472/V10_3bit_up_down_counter_Verilog_script/test_counter.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/448192472/V10_3bit_up_down_counter_Verilog_script/test_counter.v:28: Unsupported: Ignoring delay on this delayed statement.\n#100 clear = 0; dir_up = 1;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/448192472/V10_3bit_up_down_counter_Verilog_script/test_counter.v:29: Unsupported: Ignoring delay on this delayed statement.\n#200 dir_up = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/448192472/V10_3bit_up_down_counter_Verilog_script/test_counter.v:30: Unsupported: Ignoring delay on this delayed statement.\n#200;\n^\n%Warning-STMTDLY: data/full_repos/permissive/448192472/V10_3bit_up_down_counter_Verilog_script/test_counter.v:35: Unsupported: Ignoring delay on this delayed statement.\nalways #10 clk = ~clk;\n       ^\n%Error: data/full_repos/permissive/448192472/V10_3bit_up_down_counter_Verilog_script/test_counter.v:17: Cannot find file containing module: \'updown_counter\'\n updown_counter uut (\n ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/448192472/V10_3bit_up_down_counter_Verilog_script,data/full_repos/permissive/448192472/updown_counter\n             data/full_repos/permissive/448192472/V10_3bit_up_down_counter_Verilog_script,data/full_repos/permissive/448192472/updown_counter.v\n             data/full_repos/permissive/448192472/V10_3bit_up_down_counter_Verilog_script,data/full_repos/permissive/448192472/updown_counter.sv\n             updown_counter\n             updown_counter.v\n             updown_counter.sv\n             obj_dir/updown_counter\n             obj_dir/updown_counter.v\n             obj_dir/updown_counter.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_counter;


	reg clk;
	reg dir_up;
	reg clear;


	wire [2:0] count;


	updown_counter uut (
		.clk(clk), 
		.dir_up(dir_up), 
		.clear(clear),
		.count(count)
	);

	initial 
	begin

	clear = 1; clk = 0; dir_up = 0;
#100	clear = 0; dir_up = 1;
#200	dir_up = 0;
#200;
	$finish;

	end

always #10 clk = ~clk;
      
endmodule
module test_counter;



	reg clk;
	reg dir_up;
	reg clear;


	wire [2:0] count;


	updown_counter uut (
		.clk(clk), 
		.dir_up(dir_up), 
		.clear(clear),
		.count(count)
	);

	initial 
	begin

	clear = 1; clk = 0; dir_up = 0;
#100	clear = 0; dir_up = 1;
#200	dir_up = 0;
#200;
	$finish;

	end

always #10 clk = ~clk;
      
endmodule