data/full_repos/permissive/499944578/rtl/src/point_sampler/pointSampler.v
1: b"%Error: data/full_repos/permissive/499944578/rtl/src/point_sampler/pointSampler.v:7: syntax error, unexpected inside, expecting '['\n    output wire inside,\n                ^~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/point_sampler/pointSampler.v:9: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire origin_location,\n    ^~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/point_sampler/pointSampler.v:10: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire areaSign\n    ^~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/point_sampler/pointSampler.v:28: syntax error, unexpected always\n    always @(*) begin\n    ^~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/point_sampler/pointSampler.v:44: syntax error, unexpected IDENTIFIER\n    halfSpaceEquation Eab(Pin,Pa,Pb,outab,lt0ab,gt0ab);\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/point_sampler/pointSampler.v:48: syntax error, unexpected assign\n    assign antiClockInside = gt0ab && gt0bc && gt0ca;  \n    ^~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/point_sampler/pointSampler.v:74: Define or directive not defined: '`round_min'\n    addRecFN #(8,24) fpsub1 (.control(1'b0), .subOp(1'b1), .a(xp), .b(xva), .roundingMode(`round_min), .out(sub1), .exceptionFlags());\n                                                                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/point_sampler/pointSampler.v:75: Define or directive not defined: '`round_min'\n    addRecFN #(8,24) fpsub2 (.control(1'b0), .subOp(1'b1), .a(yvb), .b(yva), .roundingMode(`round_min), .out(sub2), .exceptionFlags());\n                                                                                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/point_sampler/pointSampler.v:76: Define or directive not defined: '`round_min'\n    mulRecFN #(8,24) fpmul1 (.control(1'b0), .a(sub1), .b(sub2), .roundingMode(`round_min), .out(mul1), .exceptionFlags());\n                                                                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/point_sampler/pointSampler.v:78: Define or directive not defined: '`round_min'\n    addRecFN #(8,24) fpsub3 (.control(1'b0), .subOp(1'b1), .a(yp), .b(yva), .roundingMode(`round_min), .out(sub3), .exceptionFlags());\n                                                                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/point_sampler/pointSampler.v:79: Define or directive not defined: '`round_min'\n    addRecFN #(8,24) fpsub4 (.control(1'b0), .subOp(1'b1), .a(xvb), .b(xva), .roundingMode(`round_min), .out(sub4), .exceptionFlags());\n                                                                                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/point_sampler/pointSampler.v:80: Define or directive not defined: '`round_min'\n    mulRecFN #(8,24) fpmul2 (.control(1'b0), .a(sub3), .b(sub4), .roundingMode(`round_min), .out(mul2), .exceptionFlags());\n                                                                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/point_sampler/pointSampler.v:82: Define or directive not defined: '`round_min'\n    addRecFN #(8,24) fpsub5 (.control(1'b0), .subOp(1'b1), .a(mul1), .b(mul2), .roundingMode(`round_min), .out(out), .exceptionFlags());\n                                                                                             ^~~~~~~~~~\n%Error: Exiting due to 13 error(s)\n"
module halfSpaceEquation(
    input wire [65:0] P,
    input wire [65:0] Pa, 
    input wire [65:0] Pb,
    output wire [32:0] out,
    output wire lt0,
    output wire gt0
);
    wire [32:0] xva, xvb, xp, yva, yvb, yp, sub1, sub2, sub3, sub4, mul1, mul2;
    assign xva = Pa[65:33];
    assign xvb = Pb[65:33];
    assign xp = P[65:33];
    assign yp = P[32:0];
    assign yva = Pa[32:0];
    assign yvb = Pb[32:0];
    


    addRecFN #(8,24) fpsub1 (.control(1'b0), .subOp(1'b1), .a(xp), .b(xva), .roundingMode(`round_min), .out(sub1), .exceptionFlags());
    addRecFN #(8,24) fpsub2 (.control(1'b0), .subOp(1'b1), .a(yvb), .b(yva), .roundingMode(`round_min), .out(sub2), .exceptionFlags());
    mulRecFN #(8,24) fpmul1 (.control(1'b0), .a(sub1), .b(sub2), .roundingMode(`round_min), .out(mul1), .exceptionFlags());

    addRecFN #(8,24) fpsub3 (.control(1'b0), .subOp(1'b1), .a(yp), .b(yva), .roundingMode(`round_min), .out(sub3), .exceptionFlags());
    addRecFN #(8,24) fpsub4 (.control(1'b0), .subOp(1'b1), .a(xvb), .b(xva), .roundingMode(`round_min), .out(sub4), .exceptionFlags());
    mulRecFN #(8,24) fpmul2 (.control(1'b0), .a(sub3), .b(sub4), .roundingMode(`round_min), .out(mul2), .exceptionFlags());
   
    addRecFN #(8,24) fpsub5 (.control(1'b0), .subOp(1'b1), .a(mul1), .b(mul2), .roundingMode(`round_min), .out(out), .exceptionFlags());

    assign lt0 = out[32];
    assign gt0 = (out != 33'b0) && ~lt0;
endmodule
module halfSpaceEquation(
    input wire [65:0] P,
    input wire [65:0] Pa, 
    input wire [65:0] Pb,
    output wire [32:0] out,
    output wire lt0,
    output wire gt0
);

    wire [32:0] xva, xvb, xp, yva, yvb, yp, sub1, sub2, sub3, sub4, mul1, mul2;
    assign xva = Pa[65:33];
    assign xvb = Pb[65:33];
    assign xp = P[65:33];
    assign yp = P[32:0];
    assign yva = Pa[32:0];
    assign yvb = Pb[32:0];
    


    addRecFN #(8,24) fpsub1 (.control(1'b0), .subOp(1'b1), .a(xp), .b(xva), .roundingMode(`round_min), .out(sub1), .exceptionFlags());
    addRecFN #(8,24) fpsub2 (.control(1'b0), .subOp(1'b1), .a(yvb), .b(yva), .roundingMode(`round_min), .out(sub2), .exceptionFlags());
    mulRecFN #(8,24) fpmul1 (.control(1'b0), .a(sub1), .b(sub2), .roundingMode(`round_min), .out(mul1), .exceptionFlags());

    addRecFN #(8,24) fpsub3 (.control(1'b0), .subOp(1'b1), .a(yp), .b(yva), .roundingMode(`round_min), .out(sub3), .exceptionFlags());
    addRecFN #(8,24) fpsub4 (.control(1'b0), .subOp(1'b1), .a(xvb), .b(xva), .roundingMode(`round_min), .out(sub4), .exceptionFlags());
    mulRecFN #(8,24) fpmul2 (.control(1'b0), .a(sub3), .b(sub4), .roundingMode(`round_min), .out(mul2), .exceptionFlags());
   
    addRecFN #(8,24) fpsub5 (.control(1'b0), .subOp(1'b1), .a(mul1), .b(mul2), .roundingMode(`round_min), .out(out), .exceptionFlags());

    assign lt0 = out[32];
    assign gt0 = (out != 33'b0) && ~lt0;
endmodule