data/full_repos/permissive/497337299/basics/src/adder.v
1: b'%Warning-WIDTH: data/full_repos/permissive/497337299/basics/src/adder.v:8: Operator ADD expects 6 bits on the LHS, but LHS\'s VARREF \'a\' generates 4 bits.\n                                                                         : ... In instance adder\n    assign {cout, result} = a + b + cin ;\n                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/497337299/basics/src/adder.v:8: Operator ADD expects 6 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n                                                                         : ... In instance adder\n    assign {cout, result} = a + b + cin ;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/497337299/basics/src/adder.v:8: Operator ADD expects 6 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                         : ... In instance adder\n    assign {cout, result} = a + b + cin ;\n                                  ^\n%Error: Exiting due to 3 warning(s)\n'
module adder (
input [3:0] a,b ,
input cin ,
output cout, 
output [4:0] result
);

    assign {cout, result} = a + b + cin ;

endmodule
module adder (
input [3:0] a,b ,
input cin ,
output cout, 
output [4:0] result
);


    assign {cout, result} = a + b + cin ;

endmodule