data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/CLT_RNG_HIST_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/CLT_RNG_HIST_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #rng_clk_h_period;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/CLT_RNG_HIST_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #rng_clk_h_period;\n  ^\n%Error: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/CLT_RNG_HIST_tb.v:49: Unsupported: $fopen with multichannel descriptor.  Add ,"w" as second argument to open a file descriptor.\n  write_data = $fopen("samp_generation.txt");\n               ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/CLT_RNG_HIST_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #rng_clk_h_period;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/CLT_RNG_HIST_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #rng_clk_h_period;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/CLT_RNG_HIST_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n   #rng_clk_h_period;\n   ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module CLT_RNG_HIST_tb;

	localparam rng_samps = 1000000;
	localparam seed1 = 697757461;
	localparam seed2 = 1885540239;
	localparam seed3 = 1505946904;
	localparam seed4 = 2693445;
	localparam seed_width = 32;
	localparam out_width = 12;

	localparam rng_clk_h_period = 5;




	reg rng_clk = 1'b0;
	reg rng_rst = 1'b0;
	wire [out_width - 1:0] rng_out;

	integer write_data;



	TOP_RNG #(
		.OUT_WIDTH(out_width), .SEED_WIDTH(seed_width),
		.A_SEED1(seed1), .A_SEED2(seed2), .A_SEED3(seed3), .A_SEED4(seed4), 
		.B_SEED1(seed1), .B_SEED2(seed2), .B_SEED3(seed3), .B_SEED4(seed4)
	) DELTA_U (
		.clk(rng_clk), .rst(rng_rst), .out_0(rng_out), .out_1()
	);

	always
	begin
		rng_clk = 1'b0;
		#rng_clk_h_period;
		rng_clk = 1'b1;
		#rng_clk_h_period;
	end

	initial
	begin
		write_data = $fopen("samp_generation.txt");
		rng_rst = 1'b1;
		#rng_clk_h_period;
		rng_rst = 1'b0;
		#rng_clk_h_period;
		
		repeat(rng_samps)
		begin
			#rng_clk_h_period;
			$fdisplay(write_data, "%x", rng_out);

		end
		$fclose(write_data);
		$finish;
	end
endmodule
module CLT_RNG_HIST_tb;


	localparam rng_samps = 1000000;
	localparam seed1 = 697757461;
	localparam seed2 = 1885540239;
	localparam seed3 = 1505946904;
	localparam seed4 = 2693445;
	localparam seed_width = 32;
	localparam out_width = 12;

	localparam rng_clk_h_period = 5;




	reg rng_clk = 1'b0;
	reg rng_rst = 1'b0;
	wire [out_width - 1:0] rng_out;

	integer write_data;



	TOP_RNG #(
		.OUT_WIDTH(out_width), .SEED_WIDTH(seed_width),
		.A_SEED1(seed1), .A_SEED2(seed2), .A_SEED3(seed3), .A_SEED4(seed4), 
		.B_SEED1(seed1), .B_SEED2(seed2), .B_SEED3(seed3), .B_SEED4(seed4)
	) DELTA_U (
		.clk(rng_clk), .rst(rng_rst), .out_0(rng_out), .out_1()
	);

	always
	begin
		rng_clk = 1'b0;
		#rng_clk_h_period;
		rng_clk = 1'b1;
		#rng_clk_h_period;
	end

	initial
	begin
		write_data = $fopen("samp_generation.txt");
		rng_rst = 1'b1;
		#rng_clk_h_period;
		rng_rst = 1'b0;
		#rng_clk_h_period;
		
		repeat(rng_samps)
		begin
			#rng_clk_h_period;
			$fdisplay(write_data, "%x", rng_out);

		end
		$fclose(write_data);
		$finish;
	end
endmodule