data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Finite State Machines/Fsm2/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines/Fsm2,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/Fsm2/top_module.v\n%Error: Exiting due to 5 error(s)\n'
module top_module (
    input  wire clk,
    input  wire areset,
    input  wire j,
    input  wire k,
    output reg  out
);

  parameter OFF = 1'b0, ON = 1'b1;
  reg state, next_state;


  always @(*) begin
    casez ({
      j, k, state
    })
      {2'b1z, OFF} : next_state = ON;
      {2'bz0, ON} : next_state = ON;
      default: next_state = OFF;
    endcase
  end


  always @(posedge clk, posedge areset) begin
    if (areset) state <= OFF;
    else if (clk) begin
      state <= next_state;
    end
  end


  always @(*) begin
    case (state)
      ON: out = 1'b1;
      default: out = 1'b0;
    endcase
  end

endmodule
module top_module (
    input  wire clk,
    input  wire areset,
    input  wire j,
    input  wire k,
    output reg  out
);


  parameter OFF = 1'b0, ON = 1'b1;
  reg state, next_state;


  always @(*) begin
    casez ({
      j, k, state
    })
      {2'b1z, OFF} : next_state = ON;
      {2'bz0, ON} : next_state = ON;
      default: next_state = OFF;
    endcase
  end


  always @(posedge clk, posedge areset) begin
    if (areset) state <= OFF;
    else if (clk) begin
      state <= next_state;
    end
  end


  always @(*) begin
    case (state)
      ON: out = 1'b1;
      default: out = 1'b0;
    endcase
  end

endmodule