data/full_repos/permissive/528287433/Add.v
data/verilator_xmls/f1e7d977-8702-4cdb-8d3c-253b7f33fd6a.xml
module Add(
  input         clock,
  input         reset,
  output        io_input1_ready,
  input         io_input1_valid,
  input  [27:0] io_input1_bits,
  output        io_input2_ready,
  input         io_input2_valid,
  input  [27:0] io_input2_bits,
  input         io_output_ready,
  output        io_output_valid,
  output [27:0] io_output_bits
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif
  reg [27:0] x;
  reg [27:0] y;
  reg  busy;
  reg  resultValid;
  wire  _io_input1_ready_T = ~busy;
  wire  _GEN_2 = io_input1_valid & io_input2_valid | ~busy;
  wire  _GEN_6 = io_input1_valid & io_input2_valid | busy;
  assign io_input1_ready = busy ? ~busy : _GEN_2;
  assign io_input2_ready = busy ? _io_input1_ready_T : _GEN_2;
  assign io_output_valid = resultValid;
  assign io_output_bits = x + y;
  always @(posedge clock) begin
    if (!(busy)) begin
      if (io_input1_valid & io_input2_valid) begin
        x <= io_input1_bits;
      end
    end
    if (!(busy)) begin
      if (io_input1_valid & io_input2_valid) begin
        y <= io_input2_bits;
      end
    end
    if (reset) begin
      busy <= 1'h0;
    end else if (busy) begin
      if (io_output_ready & resultValid) begin
        busy <= 1'h0;
      end
    end else begin
      busy <= _GEN_6;
    end
    if (reset) begin
      resultValid <= 1'h0;
    end else if (busy) begin
      if (io_output_ready & resultValid) begin
        resultValid <= 1'h0;
      end else begin
        resultValid <= 1'h1;
      end
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  x = _RAND_0[27:0];
  _RAND_1 = {1{`RANDOM}};
  y = _RAND_1[27:0];
  _RAND_2 = {1{`RANDOM}};
  busy = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  resultValid = _RAND_3[0:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module Add(
  input         clock,
  input         reset,
  output        io_input1_ready,
  input         io_input1_valid,
  input  [27:0] io_input1_bits,
  output        io_input2_ready,
  input         io_input2_valid,
  input  [27:0] io_input2_bits,
  input         io_output_ready,
  output        io_output_valid,
  output [27:0] io_output_bits
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif
  reg [27:0] x;
  reg [27:0] y;
  reg  busy;
  reg  resultValid;
  wire  _io_input1_ready_T = ~busy;
  wire  _GEN_2 = io_input1_valid & io_input2_valid | ~busy;
  wire  _GEN_6 = io_input1_valid & io_input2_valid | busy;
  assign io_input1_ready = busy ? ~busy : _GEN_2;
  assign io_input2_ready = busy ? _io_input1_ready_T : _GEN_2;
  assign io_output_valid = resultValid;
  assign io_output_bits = x + y;
  always @(posedge clock) begin
    if (!(busy)) begin
      if (io_input1_valid & io_input2_valid) begin
        x <= io_input1_bits;
      end
    end
    if (!(busy)) begin
      if (io_input1_valid & io_input2_valid) begin
        y <= io_input2_bits;
      end
    end
    if (reset) begin
      busy <= 1'h0;
    end else if (busy) begin
      if (io_output_ready & resultValid) begin
        busy <= 1'h0;
      end
    end else begin
      busy <= _GEN_6;
    end
    if (reset) begin
      resultValid <= 1'h0;
    end else if (busy) begin
      if (io_output_ready & resultValid) begin
        resultValid <= 1'h0;
      end else begin
        resultValid <= 1'h1;
      end
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  x = _RAND_0[27:0];
  _RAND_1 = {1{`RANDOM}};
  y = _RAND_1[27:0];
  _RAND_2 = {1{`RANDOM}};
  busy = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  resultValid = _RAND_3[0:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule