data/full_repos/permissive/425966734/verilog/rtl/abs.v
data/verilator_xmls/b97d9667-7f39-4c4c-aad6-a969a32ec5e6.xml
module Abs
  #(  parameter n=16)( 
  input signed  [n-1:0] data_in,
  output        [n-1:0] data_out);
	
  assign data_out = ~data_in[n-1] ? data_in : ~data_in; 

endmodule
module Abs
  #(  parameter n=16)( 
  input signed  [n-1:0] data_in,
  output        [n-1:0] data_out);

	
  assign data_out = ~data_in[n-1] ? data_in : ~data_in; 

endmodule