data/full_repos/permissive/423547971/FPGA Projects/NexysA7_Temp_Sensor_I2C/seg7.v
1: b'%Error: Cannot find file containing module: Projects/NexysA7_Temp_Sensor_I2C,data/full_repos/permissive/423547971\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/NexysA7_Temp_Sensor_I2C,data/full_repos/permissive/423547971\n             data/full_repos/permissive/423547971/FPGA/Projects/NexysA7_Temp_Sensor_I2C,data/full_repos/permissive/423547971.v\n             data/full_repos/permissive/423547971/FPGA/Projects/NexysA7_Temp_Sensor_I2C,data/full_repos/permissive/423547971.sv\n             Projects/NexysA7_Temp_Sensor_I2C,data/full_repos/permissive/423547971\n             Projects/NexysA7_Temp_Sensor_I2C,data/full_repos/permissive/423547971.v\n             Projects/NexysA7_Temp_Sensor_I2C,data/full_repos/permissive/423547971.sv\n             obj_dir/Projects/NexysA7_Temp_Sensor_I2C,data/full_repos/permissive/423547971\n             obj_dir/Projects/NexysA7_Temp_Sensor_I2C,data/full_repos/permissive/423547971.v\n             obj_dir/Projects/NexysA7_Temp_Sensor_I2C,data/full_repos/permissive/423547971.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: Projects/NexysA7_Temp_Sensor_I2C/seg7.v\n%Error: Exiting due to 3 error(s)\n'
module seg7(
    input clk_100MHz,
    input [7:0] temp_data,
    output reg [6:0] SEG,
    output reg [3:0] NAN = 4'hF,
    output reg [3:0] AN
    );
    

    wire [3:0] tens, ones;
    assign tens = temp_data / 10;
    assign ones = temp_data % 10;
    

    parameter ZERO  = 7'b000_0001;
    parameter ONE   = 7'b100_1111;
    parameter TWO   = 7'b001_0010;
    parameter THREE = 7'b000_0110;
    parameter FOUR  = 7'b100_1100;
    parameter FIVE  = 7'b010_0100;
    parameter SIX   = 7'b010_0000;
    parameter SEVEN = 7'b000_1111;
    parameter EIGHT = 7'b000_0000;
    parameter NINE  = 7'b000_0100;
    parameter DEG   = 7'b001_1100;
    parameter C     = 7'b011_0001;
    

    reg [1:0] anode_select;
    reg [16:0] anode_timer;
    

    always @(posedge clk_100MHz) begin

        if(anode_timer == 99_999) begin
            anode_timer <= 0;
            anode_select <=  anode_select + 1;
        end
        else
            anode_timer <=  anode_timer + 1;
    end
    

    always @(anode_select) begin
        case(anode_select) 
            2'b00 : AN = 4'b1110;
            2'b01 : AN = 4'b1101;
            2'b10 : AN = 4'b1011;
            2'b11 : AN = 4'b0111;
        endcase
    end
    
    always @*
        case(anode_select)
            2'b00 : SEG = C;
                        
            2'b01 : SEG = DEG;
                    
            2'b10 : begin
                        case(ones)
                            4'b0000 : SEG = ZERO;
                            4'b0001 : SEG = ONE;
                            4'b0010 : SEG = TWO;
                            4'b0011 : SEG = THREE;
                            4'b0100 : SEG = FOUR;
                            4'b0101 : SEG = FIVE;
                            4'b0110 : SEG = SIX;
                            4'b0111 : SEG = SEVEN;
                            4'b1000 : SEG = EIGHT;
                            4'b1001 : SEG = NINE;
                        endcase
                    end
                    
            2'b11 : begin
                        case(tens)
                            4'b0000 : SEG = ZERO;
                            4'b0001 : SEG = ONE;
                            4'b0010 : SEG = TWO;
                            4'b0011 : SEG = THREE;
                            4'b0100 : SEG = FOUR;
                            4'b0101 : SEG = FIVE;
                            4'b0110 : SEG = SIX;
                            4'b0111 : SEG = SEVEN;
                            4'b1000 : SEG = EIGHT;
                            4'b1001 : SEG = NINE;
                        endcase
                    end
        endcase
    
endmodule
module seg7(
    input clk_100MHz,
    input [7:0] temp_data,
    output reg [6:0] SEG,
    output reg [3:0] NAN = 4'hF,
    output reg [3:0] AN
    );

    

    wire [3:0] tens, ones;
    assign tens = temp_data / 10;
    assign ones = temp_data % 10;
    

    parameter ZERO  = 7'b000_0001;
    parameter ONE   = 7'b100_1111;
    parameter TWO   = 7'b001_0010;
    parameter THREE = 7'b000_0110;
    parameter FOUR  = 7'b100_1100;
    parameter FIVE  = 7'b010_0100;
    parameter SIX   = 7'b010_0000;
    parameter SEVEN = 7'b000_1111;
    parameter EIGHT = 7'b000_0000;
    parameter NINE  = 7'b000_0100;
    parameter DEG   = 7'b001_1100;
    parameter C     = 7'b011_0001;
    

    reg [1:0] anode_select;
    reg [16:0] anode_timer;
    

    always @(posedge clk_100MHz) begin

        if(anode_timer == 99_999) begin
            anode_timer <= 0;
            anode_select <=  anode_select + 1;
        end
        else
            anode_timer <=  anode_timer + 1;
    end
    

    always @(anode_select) begin
        case(anode_select) 
            2'b00 : AN = 4'b1110;
            2'b01 : AN = 4'b1101;
            2'b10 : AN = 4'b1011;
            2'b11 : AN = 4'b0111;
        endcase
    end
    
    always @*
        case(anode_select)
            2'b00 : SEG = C;
                        
            2'b01 : SEG = DEG;
                    
            2'b10 : begin
                        case(ones)
                            4'b0000 : SEG = ZERO;
                            4'b0001 : SEG = ONE;
                            4'b0010 : SEG = TWO;
                            4'b0011 : SEG = THREE;
                            4'b0100 : SEG = FOUR;
                            4'b0101 : SEG = FIVE;
                            4'b0110 : SEG = SIX;
                            4'b0111 : SEG = SEVEN;
                            4'b1000 : SEG = EIGHT;
                            4'b1001 : SEG = NINE;
                        endcase
                    end
                    
            2'b11 : begin
                        case(tens)
                            4'b0000 : SEG = ZERO;
                            4'b0001 : SEG = ONE;
                            4'b0010 : SEG = TWO;
                            4'b0011 : SEG = THREE;
                            4'b0100 : SEG = FOUR;
                            4'b0101 : SEG = FIVE;
                            4'b0110 : SEG = SIX;
                            4'b0111 : SEG = SEVEN;
                            4'b1000 : SEG = EIGHT;
                            4'b1001 : SEG = NINE;
                        endcase
                    end
        endcase
    
endmodule