data/full_repos/permissive/502135797/Lab5_March_9_2022/Code/top.v
1: b"%Error: data/full_repos/permissive/502135797/Lab5_March_9_2022/Code/top.v:15: Cannot find file containing module: 'clockmanager'\n    clockmanager clockmanager_wrapper(\n    ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502135797/Lab5_March_9_2022/Code,data/full_repos/permissive/502135797/clockmanager\n             data/full_repos/permissive/502135797/Lab5_March_9_2022/Code,data/full_repos/permissive/502135797/clockmanager.v\n             data/full_repos/permissive/502135797/Lab5_March_9_2022/Code,data/full_repos/permissive/502135797/clockmanager.sv\n             clockmanager\n             clockmanager.v\n             clockmanager.sv\n             obj_dir/clockmanager\n             obj_dir/clockmanager.v\n             obj_dir/clockmanager.sv\n%Error: data/full_repos/permissive/502135797/Lab5_March_9_2022/Code/top.v:23: Cannot find file containing module: 'udcounter'\n    udcounter udcounter_wrapper(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/502135797/Lab5_March_9_2022/Code/top.v:31: Cannot find file containing module: 'bin2bcd'\n    bin2bcd bin2bcd_wrapper(\n    ^~~~~~~\n%Error: data/full_repos/permissive/502135797/Lab5_March_9_2022/Code/top.v:37: Cannot find file containing module: 'segdisplaydriver'\n    segdisplaydriver seg7driver_wrapper(\n    ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module top(
    input clkt,
    input rstt,
    input ent,
    input udt, 
    input [4:0] SW,
    output seg,
    output [6:0] Cnode1,
    output [7:0] AN1
    );
    wire slowclk_out;
    wire [31:0] inDigit; 
    clockmanager clockmanager_wrapper(
        .clk(clkt),
        .SW(SW),
        .clkout(slowclk_out)
    );
    
    
    wire [26:0] tmp_cnt; 
    udcounter udcounter_wrapper(
        .rst1(rstt),
        .en(ent),
        .clk1(slowclk_out), 
        .tmp(tmp_cnt),
        .ud(udt)
    );
    
    bin2bcd bin2bcd_wrapper(
        .bin(tmp_cnt),
        .bcd(inDigit)
    );
    
    
    segdisplaydriver seg7driver_wrapper(
        .nexysCLK(clkt), 
        .inDigit(inDigit),
        .Cnode(Cnode1),
        .dp(seg),
        .AN(AN1)
    );
endmodule
module top(
    input clkt,
    input rstt,
    input ent,
    input udt, 
    input [4:0] SW,
    output seg,
    output [6:0] Cnode1,
    output [7:0] AN1
    );

    wire slowclk_out;
    wire [31:0] inDigit; 
    clockmanager clockmanager_wrapper(
        .clk(clkt),
        .SW(SW),
        .clkout(slowclk_out)
    );
    
    
    wire [26:0] tmp_cnt; 
    udcounter udcounter_wrapper(
        .rst1(rstt),
        .en(ent),
        .clk1(slowclk_out), 
        .tmp(tmp_cnt),
        .ud(udt)
    );
    
    bin2bcd bin2bcd_wrapper(
        .bin(tmp_cnt),
        .bcd(inDigit)
    );
    
    
    segdisplaydriver seg7driver_wrapper(
        .nexysCLK(clkt), 
        .inDigit(inDigit),
        .Cnode(Cnode1),
        .dp(seg),
        .AN(AN1)
    );
endmodule