data/full_repos/permissive/439379810/rtl/common.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/439379810/rtl/common.v:7: Multiple top level modules\n                                                                      : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                      : ... Top module \'syncsignal\'\nmodule syncsignal(input wire clk, input wire in, output reg out);\n       ^~~~~~~~~~\n                                                                      : ... Top module \'syncreset\'\nmodule syncreset(input wire clk, input wire async_reset, output reg sync_reset);\n       ^~~~~~~~~\n                                                                      : ... Top module \'edgedet\'\nmodule edgedet(input wire clk, input wire reset, input wire in, output wire p);\n       ^~~~~~~\n                                                                      : ... Top module \'clkdiv\'\nmodule clkdiv\n       ^~~~~~\n                                                                      : ... Top module \'testdly1\'\nmodule testdly1(\n       ^~~~~~~~\n                                                                      : ... Top module \'testdly2\'\nmodule testdly2(\n       ^~~~~~~~\n                                                                      : ... Top module \'testdly3\'\nmodule testdly3(\n       ^~~~~~~~\n                                                                      : ... Top module \'testdly4\'\nmodule testdly4(\n       ^~~~~~~~\n                                                                      : ... Top module \'dly60ns_edge\'\nmodule dly60ns_edge(\n       ^~~~~~~~~~~~\n                                                                      : ... Top module \'dly100ns\'\nmodule dly100ns(\n       ^~~~~~~~\n                                                                      : ... Top module \'dly100ns_edge\'\nmodule dly100ns_edge(\n       ^~~~~~~~~~~~~\n                                                                      : ... Top module \'dly120ns_edge\'\nmodule dly120ns_edge(\n       ^~~~~~~~~~~~~\n                                                                      : ... Top module \'dly200ns\'\nmodule dly200ns(\n       ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/439379810/rtl/common.v:221: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'cnt\' generates 4 bits.\n                                                                     : ... In instance dly120ns_edge\n  else if(cnt)\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/439379810/rtl/common.v:199: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'cnt\' generates 4 bits.\n                                                                     : ... In instance dly100ns_edge\n  else if(cnt)\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/439379810/rtl/common.v:156: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'cnt\' generates 4 bits.\n                                                                     : ... In instance dly60ns_edge\n  else if(cnt)\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/439379810/rtl/common.v:241: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'cnt\' generates 4 bits.\n                                                                     : ... In instance dly200ns\n  else if(cnt)\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/439379810/rtl/common.v:176: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'cnt\' generates 4 bits.\n                                                                     : ... In instance dly100ns\n  else if(cnt)\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/439379810/rtl/common.v:134: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'cnt\' generates 3 bits.\n                                                                     : ... In instance testdly4\n  else if(cnt)\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/439379810/rtl/common.v:114: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'cnt\' generates 6 bits.\n                                                                     : ... In instance testdly3\n  else if(cnt)\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/439379810/rtl/common.v:94: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'cnt\' generates 9 bits.\n                                                                    : ... In instance testdly2\n  else if(cnt)\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/439379810/rtl/common.v:74: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'cnt\' generates 8 bits.\n                                                                    : ... In instance testdly1\n  else if(cnt)\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/439379810/rtl/common.v:16: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                    : ... In instance syncreset\n   {sync_reset, sync} <= {sync[6:0], 1\'b0};\n                      ^~\n%Error: Exiting due to 11 warning(s)\n'
module edgedet(input wire clk, input wire reset, input wire in, output wire p);
	reg [1:0] x;
	reg [1:0] init = 0;
	always @(posedge clk or posedge reset)
		if(reset)
			init <= 0;
		else begin
			x <= { x[0], in };
			init <= { init[0], 1'b1 };
		end
	assign p = (&init) & x[0] & !x[1];
endmodule
module edgedet(input wire clk, input wire reset, input wire in, output wire p);

	reg [1:0] x;
	reg [1:0] init = 0;
	always @(posedge clk or posedge reset)
		if(reset)
			init <= 0;
		else begin
			x <= { x[0], in };
			init <= { init[0], 1'b1 };
		end
	assign p = (&init) & x[0] & !x[1];
endmodule