data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_pcx_qmon.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_pcx_qmon.v:28: Cannot find include file: sys.h\n`include        "sys.h" // system level definition file which contains the \n                ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: Exiting due to 1 error(s)\n'
module lsu_pcx_qmon (

   so, qwrite, sel_qentry0, 

   rclk, grst_l, arst_l, si, se, send_by_pcx, send_to_pcx
   ) ;                                          

input           rclk ;
input           grst_l;
input           arst_l;
input           si;
input           se;
output          so;

input 	send_by_pcx ;
input 	send_to_pcx ;
 	
output 	qwrite ;
output 	sel_qentry0 ;

wire       clk;
wire 	reset ,dbb_reset_l ;
wire	entry0_rst, entry1_rst ;
wire	entry0_en, entry1_en ;
wire	entry0_din, entry1_din ;
wire	entry0_full,entry1_full;

    dffrl_async rstff(.din (grst_l),
                        .q   (dbb_reset_l),
                        .clk (clk), .se(se), .si(), .so(),
                        .rst_l (arst_l));

assign  reset =  ~dbb_reset_l;
assign  clk = rclk;






































assign entry0_rst = 	reset | 
			(send_by_pcx & ~entry0_en) ;
assign entry0_en  = 	( entry1_full & send_by_pcx)  	|
			(~(entry0_full & ~send_by_pcx) & send_to_pcx) ;		
assign entry0_din = 	entry0_en ;


dffre_s  qstate_entry0 (
        .din    (entry0_din), .q  (entry0_full),
        .rst    (entry0_rst), .en (entry0_en), .clk (clk),
        .se     (1'b0),       .si (), 	       .so ()
        );

assign entry1_rst =	reset | 
			(send_by_pcx & ~entry1_en) ;
assign entry1_en  = 	entry0_full & send_to_pcx 
			& ~(send_by_pcx & ~entry1_full) ;
assign entry1_din = 	entry1_en ;


dffre_s  qstate_entry1 (
        .din    (entry1_din), .q  (entry1_full),
        .rst 	(entry1_rst), .en (entry1_en), 	.clk (clk),
        .se     (1'b0), .si     (), .so ()
        );

assign qwrite = ~entry1_full ; 

assign sel_qentry0 = 
	(~entry0_full & ~send_to_pcx) ; 




endmodule
module lsu_pcx_qmon (

   so, qwrite, sel_qentry0, 

   rclk, grst_l, arst_l, si, se, send_by_pcx, send_to_pcx
   ) ;
                                          

input           rclk ;
input           grst_l;
input           arst_l;
input           si;
input           se;
output          so;

input 	send_by_pcx ;
input 	send_to_pcx ;
 	
output 	qwrite ;
output 	sel_qentry0 ;

wire       clk;
wire 	reset ,dbb_reset_l ;
wire	entry0_rst, entry1_rst ;
wire	entry0_en, entry1_en ;
wire	entry0_din, entry1_din ;
wire	entry0_full,entry1_full;

    dffrl_async rstff(.din (grst_l),
                        .q   (dbb_reset_l),
                        .clk (clk), .se(se), .si(), .so(),
                        .rst_l (arst_l));

assign  reset =  ~dbb_reset_l;
assign  clk = rclk;






































assign entry0_rst = 	reset | 
			(send_by_pcx & ~entry0_en) ;
assign entry0_en  = 	( entry1_full & send_by_pcx)  	|
			(~(entry0_full & ~send_by_pcx) & send_to_pcx) ;		
assign entry0_din = 	entry0_en ;


dffre_s  qstate_entry0 (
        .din    (entry0_din), .q  (entry0_full),
        .rst    (entry0_rst), .en (entry0_en), .clk (clk),
        .se     (1'b0),       .si (), 	       .so ()
        );

assign entry1_rst =	reset | 
			(send_by_pcx & ~entry1_en) ;
assign entry1_en  = 	entry0_full & send_to_pcx 
			& ~(send_by_pcx & ~entry1_full) ;
assign entry1_din = 	entry1_en ;


dffre_s  qstate_entry1 (
        .din    (entry1_din), .q  (entry1_full),
        .rst 	(entry1_rst), .en (entry1_en), 	.clk (clk),
        .se     (1'b0), .si     (), .so ()
        );

assign qwrite = ~entry1_full ; 

assign sel_qentry0 = 
	(~entry0_full & ~send_to_pcx) ; 




endmodule