data/full_repos/permissive/447976230/fpga/usrp2/models/miim_model.v
data/verilator_xmls/5480901d-c319-49ec-8468-326836e52675.xml
module miim_model(input mdc_i, 
		  inout mdio, 
		  input phy_resetn_i, 
		  input phy_clk_i, 
		  output phy_intn_o,
		  output [2:0] speed_o);

   assign 		       phy_intn_o = 1;
   assign 		       speed_o = 3'b100;
   
endmodule
module miim_model(input mdc_i, 
		  inout mdio, 
		  input phy_resetn_i, 
		  input phy_clk_i, 
		  output phy_intn_o,
		  output [2:0] speed_o);


   assign 		       phy_intn_o = 1;
   assign 		       speed_o = 3'b100;
   
endmodule