data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/ATCKROOT9.v
data/verilator_xmls/b07f8c48-732c-4eb4-9337-4acfc824e90e.xml
module ATCKROOT9
    (
     A,
     Y
     );
input A;
output Y;

reg    Y;
always @(A)
    begin

    Y = A;
    end

endmodule
module ATCKROOT9
    (
     A,
     Y
     );

input A;
output Y;

reg    Y;
always @(A)
    begin

    Y = A;
    end

endmodule