data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v
1: b'%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:139: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_pd_d1 <= \'bx;  \n                   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:149: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_mode_d1 <= \'bx;  \n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:166: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data0_d1[43:0] <= \'bx;  \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:176: Unsized constant being X/Z extended to 132 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data0_d1[175:44] <= \'bx;  \n                                 ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:186: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data1_d1[43:0] <= \'bx;  \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:196: Unsized constant being X/Z extended to 132 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data1_d1[175:44] <= \'bx;  \n                                 ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:206: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data2_d1[43:0] <= \'bx;  \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:216: Unsized constant being X/Z extended to 132 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data2_d1[175:44] <= \'bx;  \n                                 ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:226: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data3_d1[43:0] <= \'bx;  \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:236: Unsized constant being X/Z extended to 132 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data3_d1[175:44] <= \'bx;  \n                                 ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:246: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data4_d1[43:0] <= \'bx;  \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:256: Unsized constant being X/Z extended to 132 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data4_d1[175:44] <= \'bx;  \n                                 ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:266: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data5_d1[43:0] <= \'bx;  \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:276: Unsized constant being X/Z extended to 132 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data5_d1[175:44] <= \'bx;  \n                                 ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:286: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data6_d1[43:0] <= \'bx;  \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:296: Unsized constant being X/Z extended to 132 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data6_d1[175:44] <= \'bx;  \n                                 ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:306: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data7_d1[43:0] <= \'bx;  \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:316: Unsized constant being X/Z extended to 132 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data7_d1[175:44] <= \'bx;  \n                                 ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:333: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_pd_d2 <= \'bx;  \n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:343: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_mode_d2 <= \'bx;  \n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:360: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data0_d2[43:0] <= \'bx;  \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:370: Unsized constant being X/Z extended to 132 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data0_d2[175:44] <= \'bx;  \n                                 ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:380: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data1_d2[43:0] <= \'bx;  \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:390: Unsized constant being X/Z extended to 132 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data1_d2[175:44] <= \'bx;  \n                                 ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:400: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data2_d2[43:0] <= \'bx;  \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:410: Unsized constant being X/Z extended to 132 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data2_d2[175:44] <= \'bx;  \n                                 ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:420: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data3_d2[43:0] <= \'bx;  \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:430: Unsized constant being X/Z extended to 132 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data3_d2[175:44] <= \'bx;  \n                                 ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:440: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data4_d2[43:0] <= \'bx;  \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:450: Unsized constant being X/Z extended to 132 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data4_d2[175:44] <= \'bx;  \n                                 ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:460: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data5_d2[43:0] <= \'bx;  \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:470: Unsized constant being X/Z extended to 132 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data5_d2[175:44] <= \'bx;  \n                                 ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:480: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data6_d2[43:0] <= \'bx;  \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:490: Unsized constant being X/Z extended to 132 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data6_d2[175:44] <= \'bx;  \n                                 ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:500: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data7_d2[43:0] <= \'bx;  \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:510: Unsized constant being X/Z extended to 132 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data7_d2[175:44] <= \'bx;  \n                                 ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:527: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_pd_d3 <= \'bx;  \n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:537: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_mode_d3 <= \'bx;  \n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:554: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data0_d3[43:0] <= \'bx;  \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:564: Unsized constant being X/Z extended to 132 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data0_d3[175:44] <= \'bx;  \n                                 ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:574: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data1_d3[43:0] <= \'bx;  \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:584: Unsized constant being X/Z extended to 132 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data1_d3[175:44] <= \'bx;  \n                                 ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:594: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data2_d3[43:0] <= \'bx;  \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:604: Unsized constant being X/Z extended to 132 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data2_d3[175:44] <= \'bx;  \n                                 ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:614: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data3_d3[43:0] <= \'bx;  \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:624: Unsized constant being X/Z extended to 132 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data3_d3[175:44] <= \'bx;  \n                                 ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:634: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data4_d3[43:0] <= \'bx;  \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:644: Unsized constant being X/Z extended to 132 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data4_d3[175:44] <= \'bx;  \n                                 ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:654: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data5_d3[43:0] <= \'bx;  \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:664: Unsized constant being X/Z extended to 132 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data5_d3[175:44] <= \'bx;  \n                                 ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:674: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data6_d3[43:0] <= \'bx;  \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:684: Unsized constant being X/Z extended to 132 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data6_d3[175:44] <= \'bx;  \n                                 ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:694: Unsized constant being X/Z extended to 44 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data7_d3[43:0] <= \'bx;  \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:704: Unsized constant being X/Z extended to 132 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                       : ... In instance NV_NVDLA_RT_cmac_b2cacc\n    mac2accu_data7_d3[175:44] <= \'bx;  \n                                 ^~~\n%Error: Exiting due to 54 warning(s)\n'
module NV_NVDLA_RT_cmac_b2cacc (
   nvdla_core_clk
  ,nvdla_core_rstn
  ,mac2accu_src_pvld
  ,mac2accu_src_mask
  ,mac2accu_src_mode
  ,mac2accu_src_data0
  ,mac2accu_src_data1
  ,mac2accu_src_data2
  ,mac2accu_src_data3
  ,mac2accu_src_data4
  ,mac2accu_src_data5
  ,mac2accu_src_data6
  ,mac2accu_src_data7
  ,mac2accu_src_pd
  ,mac2accu_dst_pvld
  ,mac2accu_dst_mask
  ,mac2accu_dst_mode
  ,mac2accu_dst_data0
  ,mac2accu_dst_data1
  ,mac2accu_dst_data2
  ,mac2accu_dst_data3
  ,mac2accu_dst_data4
  ,mac2accu_dst_data5
  ,mac2accu_dst_data6
  ,mac2accu_dst_data7
  ,mac2accu_dst_pd
  );



input nvdla_core_clk;
input nvdla_core_rstn;
input mac2accu_src_pvld;
input [7:0] mac2accu_src_mask;
input [7:0] mac2accu_src_mode;
input [175:0] mac2accu_src_data0;
input [175:0] mac2accu_src_data1;
input [175:0] mac2accu_src_data2;
input [175:0] mac2accu_src_data3;
input [175:0] mac2accu_src_data4;
input [175:0] mac2accu_src_data5;
input [175:0] mac2accu_src_data6;
input [175:0] mac2accu_src_data7;
input [8:0] mac2accu_src_pd;
output mac2accu_dst_pvld;
output [7:0] mac2accu_dst_mask;
output [7:0] mac2accu_dst_mode;
output [175:0] mac2accu_dst_data0;
output [175:0] mac2accu_dst_data1;
output [175:0] mac2accu_dst_data2;
output [175:0] mac2accu_dst_data3;
output [175:0] mac2accu_dst_data4;
output [175:0] mac2accu_dst_data5;
output [175:0] mac2accu_dst_data6;
output [175:0] mac2accu_dst_data7;
output [8:0] mac2accu_dst_pd;
wire [175:0] mac2accu_data0_d0;
wire [175:0] mac2accu_data1_d0;
wire [175:0] mac2accu_data2_d0;
wire [175:0] mac2accu_data3_d0;
wire [175:0] mac2accu_data4_d0;
wire [175:0] mac2accu_data5_d0;
wire [175:0] mac2accu_data6_d0;
wire [175:0] mac2accu_data7_d0;
wire [7:0] mac2accu_mask_d0;
wire [7:0] mac2accu_mode_d0;
wire [8:0] mac2accu_pd_d0;
wire mac2accu_pvld_d0;
reg [175:0] mac2accu_data0_d1;
reg [175:0] mac2accu_data0_d2;
reg [175:0] mac2accu_data0_d3;
reg [175:0] mac2accu_data1_d1;
reg [175:0] mac2accu_data1_d2;
reg [175:0] mac2accu_data1_d3;
reg [175:0] mac2accu_data2_d1;
reg [175:0] mac2accu_data2_d2;
reg [175:0] mac2accu_data2_d3;
reg [175:0] mac2accu_data3_d1;
reg [175:0] mac2accu_data3_d2;
reg [175:0] mac2accu_data3_d3;
reg [175:0] mac2accu_data4_d1;
reg [175:0] mac2accu_data4_d2;
reg [175:0] mac2accu_data4_d3;
reg [175:0] mac2accu_data5_d1;
reg [175:0] mac2accu_data5_d2;
reg [175:0] mac2accu_data5_d3;
reg [175:0] mac2accu_data6_d1;
reg [175:0] mac2accu_data6_d2;
reg [175:0] mac2accu_data6_d3;
reg [175:0] mac2accu_data7_d1;
reg [175:0] mac2accu_data7_d2;
reg [175:0] mac2accu_data7_d3;
reg [7:0] mac2accu_mask_d1;
reg [7:0] mac2accu_mask_d2;
reg [7:0] mac2accu_mask_d3;
reg [7:0] mac2accu_mode_d1;
reg [7:0] mac2accu_mode_d2;
reg [7:0] mac2accu_mode_d3;
reg [8:0] mac2accu_pd_d1;
reg [8:0] mac2accu_pd_d2;
reg [8:0] mac2accu_pd_d3;
reg mac2accu_pvld_d1;
reg mac2accu_pvld_d2;
reg mac2accu_pvld_d3;
assign mac2accu_pvld_d0 = mac2accu_src_pvld;
assign mac2accu_pd_d0 = mac2accu_src_pd;
assign mac2accu_mask_d0 = mac2accu_src_mask;
assign mac2accu_mode_d0 = mac2accu_src_mode;
assign mac2accu_data0_d0 = mac2accu_src_data0;
assign mac2accu_data1_d0 = mac2accu_src_data1;
assign mac2accu_data2_d0 = mac2accu_src_data2;
assign mac2accu_data3_d0 = mac2accu_src_data3;
assign mac2accu_data4_d0 = mac2accu_src_data4;
assign mac2accu_data5_d0 = mac2accu_src_data5;
assign mac2accu_data6_d0 = mac2accu_src_data6;
assign mac2accu_data7_d0 = mac2accu_src_data7;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    mac2accu_pvld_d1 <= 1'b0;
  end else begin
  mac2accu_pvld_d1 <= mac2accu_pvld_d0;
  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_pvld_d0) == 1'b1) begin
    mac2accu_pd_d1 <= mac2accu_pd_d0;

  end else if ((mac2accu_pvld_d0) == 1'b0) begin
  end else begin
    mac2accu_pd_d1 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_pvld_d0) == 1'b1) begin
    mac2accu_mode_d1 <= mac2accu_mode_d0;

  end else if ((mac2accu_pvld_d0) == 1'b0) begin
  end else begin
    mac2accu_mode_d1 <= 'bx;

  end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    mac2accu_mask_d1 <= {8{1'b0}};
  end else begin
  mac2accu_mask_d1 <= mac2accu_mask_d0;
  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d0[0]) == 1'b1) begin
    mac2accu_data0_d1[43:0] <= mac2accu_data0_d0[43:0];

  end else if ((mac2accu_mask_d0[0]) == 1'b0) begin
  end else begin
    mac2accu_data0_d1[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d0[0] & mac2accu_mode_d0[0]) == 1'b1) begin
    mac2accu_data0_d1[175:44] <= mac2accu_data0_d0[175:44];

  end else if ((mac2accu_mask_d0[0] & mac2accu_mode_d0[0]) == 1'b0) begin
  end else begin
    mac2accu_data0_d1[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d0[1]) == 1'b1) begin
    mac2accu_data1_d1[43:0] <= mac2accu_data1_d0[43:0];

  end else if ((mac2accu_mask_d0[1]) == 1'b0) begin
  end else begin
    mac2accu_data1_d1[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d0[1] & mac2accu_mode_d0[1]) == 1'b1) begin
    mac2accu_data1_d1[175:44] <= mac2accu_data1_d0[175:44];

  end else if ((mac2accu_mask_d0[1] & mac2accu_mode_d0[1]) == 1'b0) begin
  end else begin
    mac2accu_data1_d1[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d0[2]) == 1'b1) begin
    mac2accu_data2_d1[43:0] <= mac2accu_data2_d0[43:0];

  end else if ((mac2accu_mask_d0[2]) == 1'b0) begin
  end else begin
    mac2accu_data2_d1[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d0[2] & mac2accu_mode_d0[2]) == 1'b1) begin
    mac2accu_data2_d1[175:44] <= mac2accu_data2_d0[175:44];

  end else if ((mac2accu_mask_d0[2] & mac2accu_mode_d0[2]) == 1'b0) begin
  end else begin
    mac2accu_data2_d1[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d0[3]) == 1'b1) begin
    mac2accu_data3_d1[43:0] <= mac2accu_data3_d0[43:0];

  end else if ((mac2accu_mask_d0[3]) == 1'b0) begin
  end else begin
    mac2accu_data3_d1[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d0[3] & mac2accu_mode_d0[3]) == 1'b1) begin
    mac2accu_data3_d1[175:44] <= mac2accu_data3_d0[175:44];

  end else if ((mac2accu_mask_d0[3] & mac2accu_mode_d0[3]) == 1'b0) begin
  end else begin
    mac2accu_data3_d1[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d0[4]) == 1'b1) begin
    mac2accu_data4_d1[43:0] <= mac2accu_data4_d0[43:0];

  end else if ((mac2accu_mask_d0[4]) == 1'b0) begin
  end else begin
    mac2accu_data4_d1[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d0[4] & mac2accu_mode_d0[4]) == 1'b1) begin
    mac2accu_data4_d1[175:44] <= mac2accu_data4_d0[175:44];

  end else if ((mac2accu_mask_d0[4] & mac2accu_mode_d0[4]) == 1'b0) begin
  end else begin
    mac2accu_data4_d1[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d0[5]) == 1'b1) begin
    mac2accu_data5_d1[43:0] <= mac2accu_data5_d0[43:0];

  end else if ((mac2accu_mask_d0[5]) == 1'b0) begin
  end else begin
    mac2accu_data5_d1[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d0[5] & mac2accu_mode_d0[5]) == 1'b1) begin
    mac2accu_data5_d1[175:44] <= mac2accu_data5_d0[175:44];

  end else if ((mac2accu_mask_d0[5] & mac2accu_mode_d0[5]) == 1'b0) begin
  end else begin
    mac2accu_data5_d1[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d0[6]) == 1'b1) begin
    mac2accu_data6_d1[43:0] <= mac2accu_data6_d0[43:0];

  end else if ((mac2accu_mask_d0[6]) == 1'b0) begin
  end else begin
    mac2accu_data6_d1[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d0[6] & mac2accu_mode_d0[6]) == 1'b1) begin
    mac2accu_data6_d1[175:44] <= mac2accu_data6_d0[175:44];

  end else if ((mac2accu_mask_d0[6] & mac2accu_mode_d0[6]) == 1'b0) begin
  end else begin
    mac2accu_data6_d1[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d0[7]) == 1'b1) begin
    mac2accu_data7_d1[43:0] <= mac2accu_data7_d0[43:0];

  end else if ((mac2accu_mask_d0[7]) == 1'b0) begin
  end else begin
    mac2accu_data7_d1[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d0[7] & mac2accu_mode_d0[7]) == 1'b1) begin
    mac2accu_data7_d1[175:44] <= mac2accu_data7_d0[175:44];

  end else if ((mac2accu_mask_d0[7] & mac2accu_mode_d0[7]) == 1'b0) begin
  end else begin
    mac2accu_data7_d1[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    mac2accu_pvld_d2 <= 1'b0;
  end else begin
  mac2accu_pvld_d2 <= mac2accu_pvld_d1;
  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_pvld_d1) == 1'b1) begin
    mac2accu_pd_d2 <= mac2accu_pd_d1;

  end else if ((mac2accu_pvld_d1) == 1'b0) begin
  end else begin
    mac2accu_pd_d2 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_pvld_d1) == 1'b1) begin
    mac2accu_mode_d2 <= mac2accu_mode_d1;

  end else if ((mac2accu_pvld_d1) == 1'b0) begin
  end else begin
    mac2accu_mode_d2 <= 'bx;

  end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    mac2accu_mask_d2 <= {8{1'b0}};
  end else begin
  mac2accu_mask_d2 <= mac2accu_mask_d1;
  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d1[0]) == 1'b1) begin
    mac2accu_data0_d2[43:0] <= mac2accu_data0_d1[43:0];

  end else if ((mac2accu_mask_d1[0]) == 1'b0) begin
  end else begin
    mac2accu_data0_d2[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d1[0] & mac2accu_mode_d1[0]) == 1'b1) begin
    mac2accu_data0_d2[175:44] <= mac2accu_data0_d1[175:44];

  end else if ((mac2accu_mask_d1[0] & mac2accu_mode_d1[0]) == 1'b0) begin
  end else begin
    mac2accu_data0_d2[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d1[1]) == 1'b1) begin
    mac2accu_data1_d2[43:0] <= mac2accu_data1_d1[43:0];

  end else if ((mac2accu_mask_d1[1]) == 1'b0) begin
  end else begin
    mac2accu_data1_d2[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d1[1] & mac2accu_mode_d1[1]) == 1'b1) begin
    mac2accu_data1_d2[175:44] <= mac2accu_data1_d1[175:44];

  end else if ((mac2accu_mask_d1[1] & mac2accu_mode_d1[1]) == 1'b0) begin
  end else begin
    mac2accu_data1_d2[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d1[2]) == 1'b1) begin
    mac2accu_data2_d2[43:0] <= mac2accu_data2_d1[43:0];

  end else if ((mac2accu_mask_d1[2]) == 1'b0) begin
  end else begin
    mac2accu_data2_d2[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d1[2] & mac2accu_mode_d1[2]) == 1'b1) begin
    mac2accu_data2_d2[175:44] <= mac2accu_data2_d1[175:44];

  end else if ((mac2accu_mask_d1[2] & mac2accu_mode_d1[2]) == 1'b0) begin
  end else begin
    mac2accu_data2_d2[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d1[3]) == 1'b1) begin
    mac2accu_data3_d2[43:0] <= mac2accu_data3_d1[43:0];

  end else if ((mac2accu_mask_d1[3]) == 1'b0) begin
  end else begin
    mac2accu_data3_d2[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d1[3] & mac2accu_mode_d1[3]) == 1'b1) begin
    mac2accu_data3_d2[175:44] <= mac2accu_data3_d1[175:44];

  end else if ((mac2accu_mask_d1[3] & mac2accu_mode_d1[3]) == 1'b0) begin
  end else begin
    mac2accu_data3_d2[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d1[4]) == 1'b1) begin
    mac2accu_data4_d2[43:0] <= mac2accu_data4_d1[43:0];

  end else if ((mac2accu_mask_d1[4]) == 1'b0) begin
  end else begin
    mac2accu_data4_d2[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d1[4] & mac2accu_mode_d1[4]) == 1'b1) begin
    mac2accu_data4_d2[175:44] <= mac2accu_data4_d1[175:44];

  end else if ((mac2accu_mask_d1[4] & mac2accu_mode_d1[4]) == 1'b0) begin
  end else begin
    mac2accu_data4_d2[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d1[5]) == 1'b1) begin
    mac2accu_data5_d2[43:0] <= mac2accu_data5_d1[43:0];

  end else if ((mac2accu_mask_d1[5]) == 1'b0) begin
  end else begin
    mac2accu_data5_d2[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d1[5] & mac2accu_mode_d1[5]) == 1'b1) begin
    mac2accu_data5_d2[175:44] <= mac2accu_data5_d1[175:44];

  end else if ((mac2accu_mask_d1[5] & mac2accu_mode_d1[5]) == 1'b0) begin
  end else begin
    mac2accu_data5_d2[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d1[6]) == 1'b1) begin
    mac2accu_data6_d2[43:0] <= mac2accu_data6_d1[43:0];

  end else if ((mac2accu_mask_d1[6]) == 1'b0) begin
  end else begin
    mac2accu_data6_d2[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d1[6] & mac2accu_mode_d1[6]) == 1'b1) begin
    mac2accu_data6_d2[175:44] <= mac2accu_data6_d1[175:44];

  end else if ((mac2accu_mask_d1[6] & mac2accu_mode_d1[6]) == 1'b0) begin
  end else begin
    mac2accu_data6_d2[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d1[7]) == 1'b1) begin
    mac2accu_data7_d2[43:0] <= mac2accu_data7_d1[43:0];

  end else if ((mac2accu_mask_d1[7]) == 1'b0) begin
  end else begin
    mac2accu_data7_d2[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d1[7] & mac2accu_mode_d1[7]) == 1'b1) begin
    mac2accu_data7_d2[175:44] <= mac2accu_data7_d1[175:44];

  end else if ((mac2accu_mask_d1[7] & mac2accu_mode_d1[7]) == 1'b0) begin
  end else begin
    mac2accu_data7_d2[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    mac2accu_pvld_d3 <= 1'b0;
  end else begin
  mac2accu_pvld_d3 <= mac2accu_pvld_d2;
  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_pvld_d2) == 1'b1) begin
    mac2accu_pd_d3 <= mac2accu_pd_d2;

  end else if ((mac2accu_pvld_d2) == 1'b0) begin
  end else begin
    mac2accu_pd_d3 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_pvld_d2) == 1'b1) begin
    mac2accu_mode_d3 <= mac2accu_mode_d2;

  end else if ((mac2accu_pvld_d2) == 1'b0) begin
  end else begin
    mac2accu_mode_d3 <= 'bx;

  end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    mac2accu_mask_d3 <= {8{1'b0}};
  end else begin
  mac2accu_mask_d3 <= mac2accu_mask_d2;
  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d2[0]) == 1'b1) begin
    mac2accu_data0_d3[43:0] <= mac2accu_data0_d2[43:0];

  end else if ((mac2accu_mask_d2[0]) == 1'b0) begin
  end else begin
    mac2accu_data0_d3[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d2[0] & mac2accu_mode_d2[0]) == 1'b1) begin
    mac2accu_data0_d3[175:44] <= mac2accu_data0_d2[175:44];

  end else if ((mac2accu_mask_d2[0] & mac2accu_mode_d2[0]) == 1'b0) begin
  end else begin
    mac2accu_data0_d3[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d2[1]) == 1'b1) begin
    mac2accu_data1_d3[43:0] <= mac2accu_data1_d2[43:0];

  end else if ((mac2accu_mask_d2[1]) == 1'b0) begin
  end else begin
    mac2accu_data1_d3[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d2[1] & mac2accu_mode_d2[1]) == 1'b1) begin
    mac2accu_data1_d3[175:44] <= mac2accu_data1_d2[175:44];

  end else if ((mac2accu_mask_d2[1] & mac2accu_mode_d2[1]) == 1'b0) begin
  end else begin
    mac2accu_data1_d3[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d2[2]) == 1'b1) begin
    mac2accu_data2_d3[43:0] <= mac2accu_data2_d2[43:0];

  end else if ((mac2accu_mask_d2[2]) == 1'b0) begin
  end else begin
    mac2accu_data2_d3[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d2[2] & mac2accu_mode_d2[2]) == 1'b1) begin
    mac2accu_data2_d3[175:44] <= mac2accu_data2_d2[175:44];

  end else if ((mac2accu_mask_d2[2] & mac2accu_mode_d2[2]) == 1'b0) begin
  end else begin
    mac2accu_data2_d3[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d2[3]) == 1'b1) begin
    mac2accu_data3_d3[43:0] <= mac2accu_data3_d2[43:0];

  end else if ((mac2accu_mask_d2[3]) == 1'b0) begin
  end else begin
    mac2accu_data3_d3[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d2[3] & mac2accu_mode_d2[3]) == 1'b1) begin
    mac2accu_data3_d3[175:44] <= mac2accu_data3_d2[175:44];

  end else if ((mac2accu_mask_d2[3] & mac2accu_mode_d2[3]) == 1'b0) begin
  end else begin
    mac2accu_data3_d3[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d2[4]) == 1'b1) begin
    mac2accu_data4_d3[43:0] <= mac2accu_data4_d2[43:0];

  end else if ((mac2accu_mask_d2[4]) == 1'b0) begin
  end else begin
    mac2accu_data4_d3[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d2[4] & mac2accu_mode_d2[4]) == 1'b1) begin
    mac2accu_data4_d3[175:44] <= mac2accu_data4_d2[175:44];

  end else if ((mac2accu_mask_d2[4] & mac2accu_mode_d2[4]) == 1'b0) begin
  end else begin
    mac2accu_data4_d3[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d2[5]) == 1'b1) begin
    mac2accu_data5_d3[43:0] <= mac2accu_data5_d2[43:0];

  end else if ((mac2accu_mask_d2[5]) == 1'b0) begin
  end else begin
    mac2accu_data5_d3[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d2[5] & mac2accu_mode_d2[5]) == 1'b1) begin
    mac2accu_data5_d3[175:44] <= mac2accu_data5_d2[175:44];

  end else if ((mac2accu_mask_d2[5] & mac2accu_mode_d2[5]) == 1'b0) begin
  end else begin
    mac2accu_data5_d3[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d2[6]) == 1'b1) begin
    mac2accu_data6_d3[43:0] <= mac2accu_data6_d2[43:0];

  end else if ((mac2accu_mask_d2[6]) == 1'b0) begin
  end else begin
    mac2accu_data6_d3[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d2[6] & mac2accu_mode_d2[6]) == 1'b1) begin
    mac2accu_data6_d3[175:44] <= mac2accu_data6_d2[175:44];

  end else if ((mac2accu_mask_d2[6] & mac2accu_mode_d2[6]) == 1'b0) begin
  end else begin
    mac2accu_data6_d3[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d2[7]) == 1'b1) begin
    mac2accu_data7_d3[43:0] <= mac2accu_data7_d2[43:0];

  end else if ((mac2accu_mask_d2[7]) == 1'b0) begin
  end else begin
    mac2accu_data7_d3[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d2[7] & mac2accu_mode_d2[7]) == 1'b1) begin
    mac2accu_data7_d3[175:44] <= mac2accu_data7_d2[175:44];

  end else if ((mac2accu_mask_d2[7] & mac2accu_mode_d2[7]) == 1'b0) begin
  end else begin
    mac2accu_data7_d3[175:44] <= 'bx;

  end
end
assign mac2accu_dst_pvld = mac2accu_pvld_d3;
assign mac2accu_dst_pd = mac2accu_pd_d3;
assign mac2accu_dst_mask = mac2accu_mask_d3;
assign mac2accu_dst_mode = mac2accu_mode_d3;
assign mac2accu_dst_data0 = mac2accu_data0_d3;
assign mac2accu_dst_data1 = mac2accu_data1_d3;
assign mac2accu_dst_data2 = mac2accu_data2_d3;
assign mac2accu_dst_data3 = mac2accu_data3_d3;
assign mac2accu_dst_data4 = mac2accu_data4_d3;
assign mac2accu_dst_data5 = mac2accu_data5_d3;
assign mac2accu_dst_data6 = mac2accu_data6_d3;
assign mac2accu_dst_data7 = mac2accu_data7_d3;
endmodule
module NV_NVDLA_RT_cmac_b2cacc (
   nvdla_core_clk
  ,nvdla_core_rstn
  ,mac2accu_src_pvld
  ,mac2accu_src_mask
  ,mac2accu_src_mode
  ,mac2accu_src_data0
  ,mac2accu_src_data1
  ,mac2accu_src_data2
  ,mac2accu_src_data3
  ,mac2accu_src_data4
  ,mac2accu_src_data5
  ,mac2accu_src_data6
  ,mac2accu_src_data7
  ,mac2accu_src_pd
  ,mac2accu_dst_pvld
  ,mac2accu_dst_mask
  ,mac2accu_dst_mode
  ,mac2accu_dst_data0
  ,mac2accu_dst_data1
  ,mac2accu_dst_data2
  ,mac2accu_dst_data3
  ,mac2accu_dst_data4
  ,mac2accu_dst_data5
  ,mac2accu_dst_data6
  ,mac2accu_dst_data7
  ,mac2accu_dst_pd
  );




input nvdla_core_clk;
input nvdla_core_rstn;
input mac2accu_src_pvld;
input [7:0] mac2accu_src_mask;
input [7:0] mac2accu_src_mode;
input [175:0] mac2accu_src_data0;
input [175:0] mac2accu_src_data1;
input [175:0] mac2accu_src_data2;
input [175:0] mac2accu_src_data3;
input [175:0] mac2accu_src_data4;
input [175:0] mac2accu_src_data5;
input [175:0] mac2accu_src_data6;
input [175:0] mac2accu_src_data7;
input [8:0] mac2accu_src_pd;
output mac2accu_dst_pvld;
output [7:0] mac2accu_dst_mask;
output [7:0] mac2accu_dst_mode;
output [175:0] mac2accu_dst_data0;
output [175:0] mac2accu_dst_data1;
output [175:0] mac2accu_dst_data2;
output [175:0] mac2accu_dst_data3;
output [175:0] mac2accu_dst_data4;
output [175:0] mac2accu_dst_data5;
output [175:0] mac2accu_dst_data6;
output [175:0] mac2accu_dst_data7;
output [8:0] mac2accu_dst_pd;
wire [175:0] mac2accu_data0_d0;
wire [175:0] mac2accu_data1_d0;
wire [175:0] mac2accu_data2_d0;
wire [175:0] mac2accu_data3_d0;
wire [175:0] mac2accu_data4_d0;
wire [175:0] mac2accu_data5_d0;
wire [175:0] mac2accu_data6_d0;
wire [175:0] mac2accu_data7_d0;
wire [7:0] mac2accu_mask_d0;
wire [7:0] mac2accu_mode_d0;
wire [8:0] mac2accu_pd_d0;
wire mac2accu_pvld_d0;
reg [175:0] mac2accu_data0_d1;
reg [175:0] mac2accu_data0_d2;
reg [175:0] mac2accu_data0_d3;
reg [175:0] mac2accu_data1_d1;
reg [175:0] mac2accu_data1_d2;
reg [175:0] mac2accu_data1_d3;
reg [175:0] mac2accu_data2_d1;
reg [175:0] mac2accu_data2_d2;
reg [175:0] mac2accu_data2_d3;
reg [175:0] mac2accu_data3_d1;
reg [175:0] mac2accu_data3_d2;
reg [175:0] mac2accu_data3_d3;
reg [175:0] mac2accu_data4_d1;
reg [175:0] mac2accu_data4_d2;
reg [175:0] mac2accu_data4_d3;
reg [175:0] mac2accu_data5_d1;
reg [175:0] mac2accu_data5_d2;
reg [175:0] mac2accu_data5_d3;
reg [175:0] mac2accu_data6_d1;
reg [175:0] mac2accu_data6_d2;
reg [175:0] mac2accu_data6_d3;
reg [175:0] mac2accu_data7_d1;
reg [175:0] mac2accu_data7_d2;
reg [175:0] mac2accu_data7_d3;
reg [7:0] mac2accu_mask_d1;
reg [7:0] mac2accu_mask_d2;
reg [7:0] mac2accu_mask_d3;
reg [7:0] mac2accu_mode_d1;
reg [7:0] mac2accu_mode_d2;
reg [7:0] mac2accu_mode_d3;
reg [8:0] mac2accu_pd_d1;
reg [8:0] mac2accu_pd_d2;
reg [8:0] mac2accu_pd_d3;
reg mac2accu_pvld_d1;
reg mac2accu_pvld_d2;
reg mac2accu_pvld_d3;
assign mac2accu_pvld_d0 = mac2accu_src_pvld;
assign mac2accu_pd_d0 = mac2accu_src_pd;
assign mac2accu_mask_d0 = mac2accu_src_mask;
assign mac2accu_mode_d0 = mac2accu_src_mode;
assign mac2accu_data0_d0 = mac2accu_src_data0;
assign mac2accu_data1_d0 = mac2accu_src_data1;
assign mac2accu_data2_d0 = mac2accu_src_data2;
assign mac2accu_data3_d0 = mac2accu_src_data3;
assign mac2accu_data4_d0 = mac2accu_src_data4;
assign mac2accu_data5_d0 = mac2accu_src_data5;
assign mac2accu_data6_d0 = mac2accu_src_data6;
assign mac2accu_data7_d0 = mac2accu_src_data7;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    mac2accu_pvld_d1 <= 1'b0;
  end else begin
  mac2accu_pvld_d1 <= mac2accu_pvld_d0;
  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_pvld_d0) == 1'b1) begin
    mac2accu_pd_d1 <= mac2accu_pd_d0;

  end else if ((mac2accu_pvld_d0) == 1'b0) begin
  end else begin
    mac2accu_pd_d1 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_pvld_d0) == 1'b1) begin
    mac2accu_mode_d1 <= mac2accu_mode_d0;

  end else if ((mac2accu_pvld_d0) == 1'b0) begin
  end else begin
    mac2accu_mode_d1 <= 'bx;

  end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    mac2accu_mask_d1 <= {8{1'b0}};
  end else begin
  mac2accu_mask_d1 <= mac2accu_mask_d0;
  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d0[0]) == 1'b1) begin
    mac2accu_data0_d1[43:0] <= mac2accu_data0_d0[43:0];

  end else if ((mac2accu_mask_d0[0]) == 1'b0) begin
  end else begin
    mac2accu_data0_d1[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d0[0] & mac2accu_mode_d0[0]) == 1'b1) begin
    mac2accu_data0_d1[175:44] <= mac2accu_data0_d0[175:44];

  end else if ((mac2accu_mask_d0[0] & mac2accu_mode_d0[0]) == 1'b0) begin
  end else begin
    mac2accu_data0_d1[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d0[1]) == 1'b1) begin
    mac2accu_data1_d1[43:0] <= mac2accu_data1_d0[43:0];

  end else if ((mac2accu_mask_d0[1]) == 1'b0) begin
  end else begin
    mac2accu_data1_d1[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d0[1] & mac2accu_mode_d0[1]) == 1'b1) begin
    mac2accu_data1_d1[175:44] <= mac2accu_data1_d0[175:44];

  end else if ((mac2accu_mask_d0[1] & mac2accu_mode_d0[1]) == 1'b0) begin
  end else begin
    mac2accu_data1_d1[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d0[2]) == 1'b1) begin
    mac2accu_data2_d1[43:0] <= mac2accu_data2_d0[43:0];

  end else if ((mac2accu_mask_d0[2]) == 1'b0) begin
  end else begin
    mac2accu_data2_d1[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d0[2] & mac2accu_mode_d0[2]) == 1'b1) begin
    mac2accu_data2_d1[175:44] <= mac2accu_data2_d0[175:44];

  end else if ((mac2accu_mask_d0[2] & mac2accu_mode_d0[2]) == 1'b0) begin
  end else begin
    mac2accu_data2_d1[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d0[3]) == 1'b1) begin
    mac2accu_data3_d1[43:0] <= mac2accu_data3_d0[43:0];

  end else if ((mac2accu_mask_d0[3]) == 1'b0) begin
  end else begin
    mac2accu_data3_d1[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d0[3] & mac2accu_mode_d0[3]) == 1'b1) begin
    mac2accu_data3_d1[175:44] <= mac2accu_data3_d0[175:44];

  end else if ((mac2accu_mask_d0[3] & mac2accu_mode_d0[3]) == 1'b0) begin
  end else begin
    mac2accu_data3_d1[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d0[4]) == 1'b1) begin
    mac2accu_data4_d1[43:0] <= mac2accu_data4_d0[43:0];

  end else if ((mac2accu_mask_d0[4]) == 1'b0) begin
  end else begin
    mac2accu_data4_d1[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d0[4] & mac2accu_mode_d0[4]) == 1'b1) begin
    mac2accu_data4_d1[175:44] <= mac2accu_data4_d0[175:44];

  end else if ((mac2accu_mask_d0[4] & mac2accu_mode_d0[4]) == 1'b0) begin
  end else begin
    mac2accu_data4_d1[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d0[5]) == 1'b1) begin
    mac2accu_data5_d1[43:0] <= mac2accu_data5_d0[43:0];

  end else if ((mac2accu_mask_d0[5]) == 1'b0) begin
  end else begin
    mac2accu_data5_d1[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d0[5] & mac2accu_mode_d0[5]) == 1'b1) begin
    mac2accu_data5_d1[175:44] <= mac2accu_data5_d0[175:44];

  end else if ((mac2accu_mask_d0[5] & mac2accu_mode_d0[5]) == 1'b0) begin
  end else begin
    mac2accu_data5_d1[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d0[6]) == 1'b1) begin
    mac2accu_data6_d1[43:0] <= mac2accu_data6_d0[43:0];

  end else if ((mac2accu_mask_d0[6]) == 1'b0) begin
  end else begin
    mac2accu_data6_d1[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d0[6] & mac2accu_mode_d0[6]) == 1'b1) begin
    mac2accu_data6_d1[175:44] <= mac2accu_data6_d0[175:44];

  end else if ((mac2accu_mask_d0[6] & mac2accu_mode_d0[6]) == 1'b0) begin
  end else begin
    mac2accu_data6_d1[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d0[7]) == 1'b1) begin
    mac2accu_data7_d1[43:0] <= mac2accu_data7_d0[43:0];

  end else if ((mac2accu_mask_d0[7]) == 1'b0) begin
  end else begin
    mac2accu_data7_d1[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d0[7] & mac2accu_mode_d0[7]) == 1'b1) begin
    mac2accu_data7_d1[175:44] <= mac2accu_data7_d0[175:44];

  end else if ((mac2accu_mask_d0[7] & mac2accu_mode_d0[7]) == 1'b0) begin
  end else begin
    mac2accu_data7_d1[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    mac2accu_pvld_d2 <= 1'b0;
  end else begin
  mac2accu_pvld_d2 <= mac2accu_pvld_d1;
  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_pvld_d1) == 1'b1) begin
    mac2accu_pd_d2 <= mac2accu_pd_d1;

  end else if ((mac2accu_pvld_d1) == 1'b0) begin
  end else begin
    mac2accu_pd_d2 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_pvld_d1) == 1'b1) begin
    mac2accu_mode_d2 <= mac2accu_mode_d1;

  end else if ((mac2accu_pvld_d1) == 1'b0) begin
  end else begin
    mac2accu_mode_d2 <= 'bx;

  end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    mac2accu_mask_d2 <= {8{1'b0}};
  end else begin
  mac2accu_mask_d2 <= mac2accu_mask_d1;
  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d1[0]) == 1'b1) begin
    mac2accu_data0_d2[43:0] <= mac2accu_data0_d1[43:0];

  end else if ((mac2accu_mask_d1[0]) == 1'b0) begin
  end else begin
    mac2accu_data0_d2[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d1[0] & mac2accu_mode_d1[0]) == 1'b1) begin
    mac2accu_data0_d2[175:44] <= mac2accu_data0_d1[175:44];

  end else if ((mac2accu_mask_d1[0] & mac2accu_mode_d1[0]) == 1'b0) begin
  end else begin
    mac2accu_data0_d2[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d1[1]) == 1'b1) begin
    mac2accu_data1_d2[43:0] <= mac2accu_data1_d1[43:0];

  end else if ((mac2accu_mask_d1[1]) == 1'b0) begin
  end else begin
    mac2accu_data1_d2[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d1[1] & mac2accu_mode_d1[1]) == 1'b1) begin
    mac2accu_data1_d2[175:44] <= mac2accu_data1_d1[175:44];

  end else if ((mac2accu_mask_d1[1] & mac2accu_mode_d1[1]) == 1'b0) begin
  end else begin
    mac2accu_data1_d2[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d1[2]) == 1'b1) begin
    mac2accu_data2_d2[43:0] <= mac2accu_data2_d1[43:0];

  end else if ((mac2accu_mask_d1[2]) == 1'b0) begin
  end else begin
    mac2accu_data2_d2[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d1[2] & mac2accu_mode_d1[2]) == 1'b1) begin
    mac2accu_data2_d2[175:44] <= mac2accu_data2_d1[175:44];

  end else if ((mac2accu_mask_d1[2] & mac2accu_mode_d1[2]) == 1'b0) begin
  end else begin
    mac2accu_data2_d2[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d1[3]) == 1'b1) begin
    mac2accu_data3_d2[43:0] <= mac2accu_data3_d1[43:0];

  end else if ((mac2accu_mask_d1[3]) == 1'b0) begin
  end else begin
    mac2accu_data3_d2[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d1[3] & mac2accu_mode_d1[3]) == 1'b1) begin
    mac2accu_data3_d2[175:44] <= mac2accu_data3_d1[175:44];

  end else if ((mac2accu_mask_d1[3] & mac2accu_mode_d1[3]) == 1'b0) begin
  end else begin
    mac2accu_data3_d2[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d1[4]) == 1'b1) begin
    mac2accu_data4_d2[43:0] <= mac2accu_data4_d1[43:0];

  end else if ((mac2accu_mask_d1[4]) == 1'b0) begin
  end else begin
    mac2accu_data4_d2[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d1[4] & mac2accu_mode_d1[4]) == 1'b1) begin
    mac2accu_data4_d2[175:44] <= mac2accu_data4_d1[175:44];

  end else if ((mac2accu_mask_d1[4] & mac2accu_mode_d1[4]) == 1'b0) begin
  end else begin
    mac2accu_data4_d2[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d1[5]) == 1'b1) begin
    mac2accu_data5_d2[43:0] <= mac2accu_data5_d1[43:0];

  end else if ((mac2accu_mask_d1[5]) == 1'b0) begin
  end else begin
    mac2accu_data5_d2[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d1[5] & mac2accu_mode_d1[5]) == 1'b1) begin
    mac2accu_data5_d2[175:44] <= mac2accu_data5_d1[175:44];

  end else if ((mac2accu_mask_d1[5] & mac2accu_mode_d1[5]) == 1'b0) begin
  end else begin
    mac2accu_data5_d2[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d1[6]) == 1'b1) begin
    mac2accu_data6_d2[43:0] <= mac2accu_data6_d1[43:0];

  end else if ((mac2accu_mask_d1[6]) == 1'b0) begin
  end else begin
    mac2accu_data6_d2[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d1[6] & mac2accu_mode_d1[6]) == 1'b1) begin
    mac2accu_data6_d2[175:44] <= mac2accu_data6_d1[175:44];

  end else if ((mac2accu_mask_d1[6] & mac2accu_mode_d1[6]) == 1'b0) begin
  end else begin
    mac2accu_data6_d2[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d1[7]) == 1'b1) begin
    mac2accu_data7_d2[43:0] <= mac2accu_data7_d1[43:0];

  end else if ((mac2accu_mask_d1[7]) == 1'b0) begin
  end else begin
    mac2accu_data7_d2[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d1[7] & mac2accu_mode_d1[7]) == 1'b1) begin
    mac2accu_data7_d2[175:44] <= mac2accu_data7_d1[175:44];

  end else if ((mac2accu_mask_d1[7] & mac2accu_mode_d1[7]) == 1'b0) begin
  end else begin
    mac2accu_data7_d2[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    mac2accu_pvld_d3 <= 1'b0;
  end else begin
  mac2accu_pvld_d3 <= mac2accu_pvld_d2;
  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_pvld_d2) == 1'b1) begin
    mac2accu_pd_d3 <= mac2accu_pd_d2;

  end else if ((mac2accu_pvld_d2) == 1'b0) begin
  end else begin
    mac2accu_pd_d3 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_pvld_d2) == 1'b1) begin
    mac2accu_mode_d3 <= mac2accu_mode_d2;

  end else if ((mac2accu_pvld_d2) == 1'b0) begin
  end else begin
    mac2accu_mode_d3 <= 'bx;

  end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    mac2accu_mask_d3 <= {8{1'b0}};
  end else begin
  mac2accu_mask_d3 <= mac2accu_mask_d2;
  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d2[0]) == 1'b1) begin
    mac2accu_data0_d3[43:0] <= mac2accu_data0_d2[43:0];

  end else if ((mac2accu_mask_d2[0]) == 1'b0) begin
  end else begin
    mac2accu_data0_d3[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d2[0] & mac2accu_mode_d2[0]) == 1'b1) begin
    mac2accu_data0_d3[175:44] <= mac2accu_data0_d2[175:44];

  end else if ((mac2accu_mask_d2[0] & mac2accu_mode_d2[0]) == 1'b0) begin
  end else begin
    mac2accu_data0_d3[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d2[1]) == 1'b1) begin
    mac2accu_data1_d3[43:0] <= mac2accu_data1_d2[43:0];

  end else if ((mac2accu_mask_d2[1]) == 1'b0) begin
  end else begin
    mac2accu_data1_d3[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d2[1] & mac2accu_mode_d2[1]) == 1'b1) begin
    mac2accu_data1_d3[175:44] <= mac2accu_data1_d2[175:44];

  end else if ((mac2accu_mask_d2[1] & mac2accu_mode_d2[1]) == 1'b0) begin
  end else begin
    mac2accu_data1_d3[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d2[2]) == 1'b1) begin
    mac2accu_data2_d3[43:0] <= mac2accu_data2_d2[43:0];

  end else if ((mac2accu_mask_d2[2]) == 1'b0) begin
  end else begin
    mac2accu_data2_d3[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d2[2] & mac2accu_mode_d2[2]) == 1'b1) begin
    mac2accu_data2_d3[175:44] <= mac2accu_data2_d2[175:44];

  end else if ((mac2accu_mask_d2[2] & mac2accu_mode_d2[2]) == 1'b0) begin
  end else begin
    mac2accu_data2_d3[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d2[3]) == 1'b1) begin
    mac2accu_data3_d3[43:0] <= mac2accu_data3_d2[43:0];

  end else if ((mac2accu_mask_d2[3]) == 1'b0) begin
  end else begin
    mac2accu_data3_d3[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d2[3] & mac2accu_mode_d2[3]) == 1'b1) begin
    mac2accu_data3_d3[175:44] <= mac2accu_data3_d2[175:44];

  end else if ((mac2accu_mask_d2[3] & mac2accu_mode_d2[3]) == 1'b0) begin
  end else begin
    mac2accu_data3_d3[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d2[4]) == 1'b1) begin
    mac2accu_data4_d3[43:0] <= mac2accu_data4_d2[43:0];

  end else if ((mac2accu_mask_d2[4]) == 1'b0) begin
  end else begin
    mac2accu_data4_d3[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d2[4] & mac2accu_mode_d2[4]) == 1'b1) begin
    mac2accu_data4_d3[175:44] <= mac2accu_data4_d2[175:44];

  end else if ((mac2accu_mask_d2[4] & mac2accu_mode_d2[4]) == 1'b0) begin
  end else begin
    mac2accu_data4_d3[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d2[5]) == 1'b1) begin
    mac2accu_data5_d3[43:0] <= mac2accu_data5_d2[43:0];

  end else if ((mac2accu_mask_d2[5]) == 1'b0) begin
  end else begin
    mac2accu_data5_d3[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d2[5] & mac2accu_mode_d2[5]) == 1'b1) begin
    mac2accu_data5_d3[175:44] <= mac2accu_data5_d2[175:44];

  end else if ((mac2accu_mask_d2[5] & mac2accu_mode_d2[5]) == 1'b0) begin
  end else begin
    mac2accu_data5_d3[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d2[6]) == 1'b1) begin
    mac2accu_data6_d3[43:0] <= mac2accu_data6_d2[43:0];

  end else if ((mac2accu_mask_d2[6]) == 1'b0) begin
  end else begin
    mac2accu_data6_d3[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d2[6] & mac2accu_mode_d2[6]) == 1'b1) begin
    mac2accu_data6_d3[175:44] <= mac2accu_data6_d2[175:44];

  end else if ((mac2accu_mask_d2[6] & mac2accu_mode_d2[6]) == 1'b0) begin
  end else begin
    mac2accu_data6_d3[175:44] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d2[7]) == 1'b1) begin
    mac2accu_data7_d3[43:0] <= mac2accu_data7_d2[43:0];

  end else if ((mac2accu_mask_d2[7]) == 1'b0) begin
  end else begin
    mac2accu_data7_d3[43:0] <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((mac2accu_mask_d2[7] & mac2accu_mode_d2[7]) == 1'b1) begin
    mac2accu_data7_d3[175:44] <= mac2accu_data7_d2[175:44];

  end else if ((mac2accu_mask_d2[7] & mac2accu_mode_d2[7]) == 1'b0) begin
  end else begin
    mac2accu_data7_d3[175:44] <= 'bx;

  end
end
assign mac2accu_dst_pvld = mac2accu_pvld_d3;
assign mac2accu_dst_pd = mac2accu_pd_d3;
assign mac2accu_dst_mask = mac2accu_mask_d3;
assign mac2accu_dst_mode = mac2accu_mode_d3;
assign mac2accu_dst_data0 = mac2accu_data0_d3;
assign mac2accu_dst_data1 = mac2accu_data1_d3;
assign mac2accu_dst_data2 = mac2accu_data2_d3;
assign mac2accu_dst_data3 = mac2accu_data3_d3;
assign mac2accu_dst_data4 = mac2accu_data4_d3;
assign mac2accu_dst_data5 = mac2accu_data5_d3;
assign mac2accu_dst_data6 = mac2accu_data6_d3;
assign mac2accu_dst_data7 = mac2accu_data7_d3;
endmodule