data/full_repos/permissive/463333282/Combinator.v
data/verilator_xmls/894de585-4889-4dbc-a817-6ac7abad1db3.xml
module Combinator(
  input         clock,
  input         reset,
  input  [31:0] io_word1,
  input  [31:0] io_word2,
  output [31:0] io_out
);
  wire [47:0] _GEN_0 = {io_word1, 16'h0};
  wire [62:0] word1_16bit = {{15'd0}, _GEN_0};
  wire [31:0] word2_16bit = io_word2 & 32'hffff;
  wire [62:0] _GEN_1 = {{31'd0}, word2_16bit};
  wire [62:0] _io_out_T = word1_16bit | _GEN_1;
  assign io_out = _io_out_T[31:0];
endmodule
module Combinator(
  input         clock,
  input         reset,
  input  [31:0] io_word1,
  input  [31:0] io_word2,
  output [31:0] io_out
);

  wire [47:0] _GEN_0 = {io_word1, 16'h0};
  wire [62:0] word1_16bit = {{15'd0}, _GEN_0};
  wire [31:0] word2_16bit = io_word2 & 32'hffff;
  wire [62:0] _GEN_1 = {{31'd0}, word2_16bit};
  wire [62:0] _io_out_T = word1_16bit | _GEN_1;
  assign io_out = _io_out_T[31:0];
endmodule