data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:16: Unsupported: Ignoring delay on this delayed statement.\n            #0.5;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:18: Unsupported: Ignoring delay on this delayed statement.\n            #0.5;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:60: Unsupported: Ignoring delay on this delayed statement.\n        #2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:65: Unsupported: Ignoring delay on this delayed statement.\n        #1;                   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:67: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:73: Unsupported: Ignoring delay on this delayed statement.\n        #2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:115: Unsupported: Ignoring delay on this delayed statement.\n        #3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:117: Unsupported: Ignoring delay on this delayed statement.\n        #3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:119: Unsupported: Ignoring delay on this delayed statement.\n        #3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:122: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:124: Unsupported: Ignoring delay on this delayed statement.\n        #2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:128: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:130: Unsupported: Ignoring delay on this delayed statement.\n        #2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:135: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:137: Unsupported: Ignoring delay on this delayed statement.\n        #2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:141: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:143: Unsupported: Ignoring delay on this delayed statement.\n        #2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:147: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:149: Unsupported: Ignoring delay on this delayed statement.\n        #2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:153: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:155: Unsupported: Ignoring delay on this delayed statement.\n        #2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:159: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:161: Unsupported: Ignoring delay on this delayed statement.\n        #2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:165: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:167: Unsupported: Ignoring delay on this delayed statement.\n        #2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:171: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:173: Unsupported: Ignoring delay on this delayed statement.\n        #2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:177: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:179: Unsupported: Ignoring delay on this delayed statement.\n        #2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:183: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:185: Unsupported: Ignoring delay on this delayed statement.\n        #2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:189: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:191: Unsupported: Ignoring delay on this delayed statement.\n        #2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:195: Unsupported: Ignoring delay on this delayed statement.\n        #3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:198: Unsupported: Ignoring delay on this delayed statement.\n        #1;                   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:200: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:206: Unsupported: Ignoring delay on this delayed statement.\n        #2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:226: Unsupported: Ignoring delay on this delayed statement.\n        #3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:228: Unsupported: Ignoring delay on this delayed statement.\n        #3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:230: Unsupported: Ignoring delay on this delayed statement.\n        #3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:233: Unsupported: Ignoring delay on this delayed statement.\n        #4;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:237: Unsupported: Ignoring delay on this delayed statement.\n        #4;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:241: Unsupported: Ignoring delay on this delayed statement.\n        #4;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:245: Unsupported: Ignoring delay on this delayed statement.\n        #4;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:249: Unsupported: Ignoring delay on this delayed statement.\n        #4;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:253: Unsupported: Ignoring delay on this delayed statement.\n        #4;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:257: Unsupported: Ignoring delay on this delayed statement.\n        #4;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:261: Unsupported: Ignoring delay on this delayed statement.\n        #4;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:272: Unsupported: Ignoring delay on this delayed statement.\n        #2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:304: Unsupported: Ignoring delay on this delayed statement.\n        #3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:308: Unsupported: Ignoring delay on this delayed statement.\n        #3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:311: Unsupported: Ignoring delay on this delayed statement.\n        #3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:315: Unsupported: Ignoring delay on this delayed statement.\n        #3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:319: Unsupported: Ignoring delay on this delayed statement.\n        #3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:323: Unsupported: Ignoring delay on this delayed statement.\n        #3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:327: Unsupported: Ignoring delay on this delayed statement.\n        #3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:331: Unsupported: Ignoring delay on this delayed statement.\n        #3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:335: Unsupported: Ignoring delay on this delayed statement.\n        #3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:339: Unsupported: Ignoring delay on this delayed statement.\n        #3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:343: Unsupported: Ignoring delay on this delayed statement.\n        #3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:347: Unsupported: Ignoring delay on this delayed statement.\n        #3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:351: Unsupported: Ignoring delay on this delayed statement.\n        #3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:355: Unsupported: Ignoring delay on this delayed statement.\n        #3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:359: Unsupported: Ignoring delay on this delayed statement.\n        #3;                                                                      \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:363: Unsupported: Ignoring delay on this delayed statement.\n        #3;                                                                      \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:367: Unsupported: Ignoring delay on this delayed statement.\n        #3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:371: Unsupported: Ignoring delay on this delayed statement.\n        #3;                                                                      \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:375: Unsupported: Ignoring delay on this delayed statement.\n        #3;                                                                      \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:379: Unsupported: Ignoring delay on this delayed statement.\n        #3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:383: Unsupported: Ignoring delay on this delayed statement.\n         #3;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:387: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:389: Unsupported: Ignoring delay on this delayed statement.\n        #2\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:395: Unsupported: Ignoring delay on this delayed statement.\n        #1;                   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:393: Unsupported: Ignoring delay on this delayed statement.\n        #3\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:397: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:29: Can\'t find definition of scope/variable: \'IMem\'\n        $readmemh("P_TB_test1.mem", IMem.rom); \n                                    ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:39: Can\'t find definition of scope/variable: \'RegFile\'\n        if(RegFile.r[5] != ({20\'d32, 12\'b0})) $fatal(1,"Error in LUI instruction");\n           ^~~~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:43: Can\'t find definition of scope/variable: \'PCnt\'\n        t_pc <= PCnt.data_out;\n                ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:45: Can\'t find definition of scope/variable: \'RegFile\'\n        if(RegFile.r[6] != (t_pc + {20\'d10, 12\'b0})) $fatal(1,"Error in AUIPC instruction");\n           ^~~~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:49: Can\'t find definition of scope/variable: \'PCnt\'\n        t_pc <= PCnt.data_out;\n                ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:51: Can\'t find definition of scope/variable: \'RegFile\'\n        if(RegFile.r[2] != (t_pc + 32\'d4)) $fatal(1,"Error in JAL instruction");\n           ^~~~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:52: Can\'t find definition of scope/variable: \'PCnt\'\n        if(PCnt.data_out != (t_pc + 32\'d8)) $fatal(1,"Error in JAL instruction");\n           ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:59: Can\'t find definition of scope/variable: \'PCnt\'\n        t_pc <= PCnt.data_out;\n                ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:62: Can\'t find definition of scope/variable: \'PCnt\'\n        if(PCnt.data_out != (RegFile.r[2])) $fatal(1,"Error in JALR instruction");\n           ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:62: Can\'t find definition of scope/variable: \'RegFile\'\n        if(PCnt.data_out != (RegFile.r[2])) $fatal(1,"Error in JALR instruction");\n                             ^~~~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:66: Can\'t find definition of scope/variable: \'PCnt\'\n        t_pc <= PCnt.data_out;\n                ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:68: Can\'t find definition of scope/variable: \'PCnt\'\n        if(PCnt.data_out != t_pc) $fatal(1,"Error in ECALL instruction");\n           ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:75: Can\'t find definition of scope/variable: \'Processor\'\n        $readmemh("P_TB_test2.mem", Processor.InstructionMemory.rom);\n                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:75: Can\'t find definition of scope/variable: \'InstructionMemory\'\n        $readmemh("P_TB_test2.mem", Processor.InstructionMemory.rom);\n                                              ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:123: Can\'t find definition of scope/variable: \'PCnt\'\n        t_pc <= PCnt.data_out;\n                ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:125: Can\'t find definition of scope/variable: \'PCnt\'\n        if(PCnt.data_out != (t_pc + 32\'d4)) $fatal(1,"Error in BEQ instruction");\n           ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:129: Can\'t find definition of scope/variable: \'PCnt\'\n        t_pc <= PCnt.data_out;\n                ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:131: Can\'t find definition of scope/variable: \'PCnt\'\n        if(PCnt.data_out != (t_pc + 32\'d8)) $fatal(1,"Error in BEQ instruction");\n           ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:136: Can\'t find definition of scope/variable: \'PCnt\'\n        t_pc <= PCnt.data_out;\n                ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:138: Can\'t find definition of scope/variable: \'PCnt\'\n        if(PCnt.data_out != (t_pc + 32\'d4)) $fatal(1,"Error in BNE instruction");\n           ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:142: Can\'t find definition of scope/variable: \'PCnt\'\n        t_pc <= PCnt.data_out;\n                ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:144: Can\'t find definition of scope/variable: \'PCnt\'\n        if(PCnt.data_out != (t_pc + 32\'d8)) $fatal(1,"Error in BNE instruction");\n           ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:148: Can\'t find definition of scope/variable: \'PCnt\'\n        t_pc <= PCnt.data_out;\n                ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:150: Can\'t find definition of scope/variable: \'PCnt\'\n        if(PCnt.data_out != (t_pc + 32\'d4)) $fatal(1,"Error in BLT instruction");\n           ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:154: Can\'t find definition of scope/variable: \'PCnt\'\n        t_pc <= PCnt.data_out;\n                ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:156: Can\'t find definition of scope/variable: \'PCnt\'\n        if(PCnt.data_out != (t_pc + 32\'d8)) $fatal(1,"Error in BLT instruction");\n           ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:160: Can\'t find definition of scope/variable: \'PCnt\'\n        t_pc <= PCnt.data_out;\n                ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:162: Can\'t find definition of scope/variable: \'PCnt\'\n        if(PCnt.data_out != (t_pc + 32\'d4)) $fatal(1,"Error in BLTU instruction");\n           ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:166: Can\'t find definition of scope/variable: \'PCnt\'\n        t_pc <= PCnt.data_out;\n                ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:168: Can\'t find definition of scope/variable: \'PCnt\'\n        if(PCnt.data_out != (t_pc + 32\'d8)) $fatal(1,"Error in BLTU instruction");\n           ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:172: Can\'t find definition of scope/variable: \'PCnt\'\n        t_pc <= PCnt.data_out;\n                ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:174: Can\'t find definition of scope/variable: \'PCnt\'\n        if(PCnt.data_out != (t_pc + 32\'d4)) $fatal(1,"Error in BGE instruction");\n           ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:178: Can\'t find definition of scope/variable: \'PCnt\'\n        t_pc <= PCnt.data_out;\n                ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:180: Can\'t find definition of scope/variable: \'PCnt\'\n        if(PCnt.data_out != (t_pc + 32\'d8)) $fatal(1,"Error in BGE instruction");\n           ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:184: Can\'t find definition of scope/variable: \'PCnt\'\n        t_pc <= PCnt.data_out;\n                ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:186: Can\'t find definition of scope/variable: \'PCnt\'\n        if(PCnt.data_out != (t_pc + 32\'d4)) $fatal(1,"Error in BGEU instruction");\n           ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:190: Can\'t find definition of scope/variable: \'PCnt\'\n        t_pc <= PCnt.data_out;\n                ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:192: Can\'t find definition of scope/variable: \'PCnt\'\n        if(PCnt.data_out != (t_pc + 32\'d8)) $fatal(1,"Error in BGEU instruction");\n           ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:199: Can\'t find definition of scope/variable: \'PCnt\'\n        t_pc <= PCnt.data_out;\n                ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:201: Can\'t find definition of scope/variable: \'PCnt\'\n        if(PCnt.data_out != t_pc) $fatal(1,"Error in HALT instruction");       \n           ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:208: Can\'t find definition of scope/variable: \'Processor\'\n        $readmemh("P_TB_test3.mem", Processor.InstructionMemory.rom);\n                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:208: Can\'t find definition of scope/variable: \'InstructionMemory\'\n        $readmemh("P_TB_test3.mem", Processor.InstructionMemory.rom);\n                                              ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:234: Can\'t find definition of scope/variable: \'DMem\'\n        if(DMem.ram[2][7:0] != 8\'hFA) $fatal(1,"Error in SB instruction");\n           ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:238: Can\'t find definition of scope/variable: \'DMem\'\n        if(DMem.ram[3][15:0] != 16\'hF0FA) $fatal(1,"Error in SH instruction");\n           ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:242: Can\'t find definition of scope/variable: \'DMem\'\n        if(DMem.ram[1] != 32\'hFB39F0FA) $fatal(1,"Error in SW instruction");\n           ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:246: Can\'t find definition of scope/variable: \'RegFile\'\n        if(RegFile.r[6] != 32\'hFFFFFFFA) $fatal(1,"Error in LB instruction");\n           ^~~~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:250: Can\'t find definition of scope/variable: \'RegFile\'\n        if(RegFile.r[7] != 32\'hFFFFF0FA) $fatal(1,"Error in LH instruction");\n           ^~~~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:254: Can\'t find definition of scope/variable: \'RegFile\'\n        if(RegFile.r[9] != 32\'h000000FA) $fatal(1,"Error in LBU instruction");\n           ^~~~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:258: Can\'t find definition of scope/variable: \'RegFile\'\n        if(RegFile.r[10] != 32\'h0000F0FA) $fatal(1,"Error in LHU instruction");\n           ^~~~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/Processor_TB.v:262: Can\'t find definition of scope/variable: \'RegFile\'\n        if(RegFile.r[8] != 32\'hF53F30FA) $fatal(1,"Error in LW instruction");\n           ^~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n        ... See the manual and https://verilator.org for more assistance.\n'
module Processor_TB(

    );
    reg t_clk = 1;
    reg t_rstn = 0;
    reg [31:0] t_pc;
    
    Processor DUT(.clk(t_clk), .rstn(t_rstn));
    
    initial begin : CLK_GEN
        forever begin
            t_clk <=1;
            #0.5;
            t_clk <=0;
            #0.5;
        end
    end
    
    initial begin : TEST_PROCESS
           
    

    
        #2;
        t_rstn <= 1;
        $readmemh("P_TB_test1.mem", IMem.rom); 






        

        #3;
        if(RegFile.r[5] != ({20'd32, 12'b0})) $fatal(1,"Error in LUI instruction");
        

        #1;
        t_pc <= PCnt.data_out;
        #2;
        if(RegFile.r[6] != (t_pc + {20'd10, 12'b0})) $fatal(1,"Error in AUIPC instruction");
        

        #1;
        t_pc <= PCnt.data_out;
        #2;
        if(RegFile.r[2] != (t_pc + 32'd4)) $fatal(1,"Error in JAL instruction");
        if(PCnt.data_out != (t_pc + 32'd8)) $fatal(1,"Error in JAL instruction");
        

        #3;
        

        #1;
        t_pc <= PCnt.data_out;
        #2;

        if(PCnt.data_out != (RegFile.r[2])) $fatal(1,"Error in JALR instruction");
                       

        #1;                   
        t_pc <= PCnt.data_out;
        #10;
        if(PCnt.data_out != t_pc) $fatal(1,"Error in ECALL instruction");
        


        t_rstn <= 0;
        #2;
        t_rstn <= 1;
        $readmemh("P_TB_test2.mem", Processor.InstructionMemory.rom);
         






































        #3;

        #3;

        #3;
        

        #1;
        t_pc <= PCnt.data_out;
        #2;
        if(PCnt.data_out != (t_pc + 32'd4)) $fatal(1,"Error in BEQ instruction");
        

        #1;
        t_pc <= PCnt.data_out;
        #2;
        if(PCnt.data_out != (t_pc + 32'd8)) $fatal(1,"Error in BEQ instruction");
        

 
        #1;
        t_pc <= PCnt.data_out;
        #2;
        if(PCnt.data_out != (t_pc + 32'd4)) $fatal(1,"Error in BNE instruction");
        

        #1;
        t_pc <= PCnt.data_out;
        #2;
        if(PCnt.data_out != (t_pc + 32'd8)) $fatal(1,"Error in BNE instruction");
         

        #1;
        t_pc <= PCnt.data_out;
        #2;
        if(PCnt.data_out != (t_pc + 32'd4)) $fatal(1,"Error in BLT instruction");
        

        #1;
        t_pc <= PCnt.data_out;
        #2;
        if(PCnt.data_out != (t_pc + 32'd8)) $fatal(1,"Error in BLT instruction");
        

        #1;
        t_pc <= PCnt.data_out;
        #2;
        if(PCnt.data_out != (t_pc + 32'd4)) $fatal(1,"Error in BLTU instruction");
        

        #1;
        t_pc <= PCnt.data_out;
        #2;
        if(PCnt.data_out != (t_pc + 32'd8)) $fatal(1,"Error in BLTU instruction");
        

        #1;
        t_pc <= PCnt.data_out;
        #2;
        if(PCnt.data_out != (t_pc + 32'd4)) $fatal(1,"Error in BGE instruction");
        

        #1;
        t_pc <= PCnt.data_out;
        #2;
        if(PCnt.data_out != (t_pc + 32'd8)) $fatal(1,"Error in BGE instruction");
       

        #1;
        t_pc <= PCnt.data_out;
        #2;
        if(PCnt.data_out != (t_pc + 32'd4)) $fatal(1,"Error in BGEU instruction");
        

        #1;
        t_pc <= PCnt.data_out;
        #2;
        if(PCnt.data_out != (t_pc + 32'd8)) $fatal(1,"Error in BGEU instruction");
        

        #3;
        

        #1;                   
        t_pc <= PCnt.data_out;
        #10;
        if(PCnt.data_out != t_pc) $fatal(1,"Error in HALT instruction");       
        
        

        t_rstn <= 0;
        #2;
        t_rstn <= 1;
        $readmemh("P_TB_test3.mem", Processor.InstructionMemory.rom);















        

        #3;

        #3;

        #3;
         

        #4;
        if(DMem.ram[2][7:0] != 8'hFA) $fatal(1,"Error in SB instruction");
        

        #4;
        if(DMem.ram[3][15:0] != 16'hF0FA) $fatal(1,"Error in SH instruction");
        

        #4;
        if(DMem.ram[1] != 32'hFB39F0FA) $fatal(1,"Error in SW instruction");


        #4;
        if(RegFile.r[6] != 32'hFFFFFFFA) $fatal(1,"Error in LB instruction");
        

        #4;
        if(RegFile.r[7] != 32'hFFFFF0FA) $fatal(1,"Error in LH instruction");
        

        #4;
        if(RegFile.r[9] != 32'h000000FA) $fatal(1,"Error in LBU instruction");
        

        #4;
        if(RegFile.r[10] != 32'h0000F0FA) $fatal(1,"Error in LHU instruction");
        

        #4;
        if(RegFile.r[8] != 32'hF53F30FA) $fatal(1,"Error in LW instruction");
        


        
        



        t_rstn <= 0;
        #2;
        t_rstn <= 1;
        $readmemh("P_TB_test4.mem", Processor.InstructionMemory.rom);  



























        

        #3;
        if(RegFile.r[1] != 32'b10111011) $fatal(1,"Error in ADDI instruction");
        

        #3;
        

        #3;
        if(RegFile.r[3] != 32'd5) $fatal(1,"Error in ADDI instruction");
        

        #3;
        if(RegFile.r[5] != 32'd1) $fatal(1,"Error in SLTI instruction");


        #3;
        if(RegFile.r[6] != 32'd0) $fatal(1,"Error in SLTIU instruction");
        

        #3;
        if(RegFile.r[4] != 32'b00001000) $fatal(1,"Error in XORI instruction");
        

        #3;
        if(RegFile.r[5] != 32'b10111011) $fatal(1,"Error in ORI instruction");
        

        #3;
        if(RegFile.r[6] != 32'b10110010) $fatal(1,"Error in ANDI instruction");
                

        #3;
        if(RegFile.r[4] != 32'b101110110000000) $fatal(1,"Error in SLLI instruction");
        

        #3;
        if(RegFile.r[5] != 32'b10111) $fatal(1,"Error in SRLI instruction");
        

        #3;
        if(RegFile.r[6] != 32'b1011) $fatal(1,"Error in SRAI instruction");
        

        #3;
        if(RegFile.r[4] != 32'd171) $fatal(1,"Error in ADD instruction");
        

        #3;
        if(RegFile.r[5] != 32'd161) $fatal(1,"Error in SUB instruction");
        

        #3;
        if(RegFile.r[6] != 32'b1010011000000) $fatal(1,"Error in SLL instruction");
        

        #3;                                                                      
        if(RegFile.r[7] != 32'd0) $fatal(1,"Error in SLT instruction");
        

        #3;                                                                      
        if(RegFile.r[8] != 32'd0) $fatal(1,"Error in SLTU instruction");
        

        #3;
        if(RegFile.r[4] != 32'b00011101) $fatal(1,"Error in XOR instruction");
        

        #3;                                                                      
        if(RegFile.r[5] != 32'b101) $fatal(1,"Error in SRL instruction");
        

        #3;                                                                      
        if(RegFile.r[6] != 32'b101) $fatal(1,"Error in SRA instruction");
        

        #3;
        if(RegFile.r[7] != 32'b10111111) $fatal(1,"Error in OR instruction");
        

         #3;
        if(RegFile.r[8] != 32'b10100010) $fatal(1,"Error in AND instruction");
        

        #1
        t_pc <= PCnt.data_out;
        #2
        if(PCnt.data_out != (t_pc + 32'd4)) $fatal(1,"Error in FENCE instruction");
        

        #3

        #1;                   
        t_pc <= PCnt.data_out;
        #10;
        if(PCnt.data_out != t_pc) $fatal(1,"Error in HALT instruction");
        
        
        $display("\nAll test Passed\n");
        $finish;
    end
endmodule
module Processor_TB(

    );

    reg t_clk = 1;
    reg t_rstn = 0;
    reg [31:0] t_pc;
    
    Processor DUT(.clk(t_clk), .rstn(t_rstn));
    
    initial begin : CLK_GEN
        forever begin
            t_clk <=1;
            #0.5;
            t_clk <=0;
            #0.5;
        end
    end
    
    initial begin : TEST_PROCESS
           
    

    
        #2;
        t_rstn <= 1;
        $readmemh("P_TB_test1.mem", IMem.rom); 






        

        #3;
        if(RegFile.r[5] != ({20'd32, 12'b0})) $fatal(1,"Error in LUI instruction");
        

        #1;
        t_pc <= PCnt.data_out;
        #2;
        if(RegFile.r[6] != (t_pc + {20'd10, 12'b0})) $fatal(1,"Error in AUIPC instruction");
        

        #1;
        t_pc <= PCnt.data_out;
        #2;
        if(RegFile.r[2] != (t_pc + 32'd4)) $fatal(1,"Error in JAL instruction");
        if(PCnt.data_out != (t_pc + 32'd8)) $fatal(1,"Error in JAL instruction");
        

        #3;
        

        #1;
        t_pc <= PCnt.data_out;
        #2;

        if(PCnt.data_out != (RegFile.r[2])) $fatal(1,"Error in JALR instruction");
                       

        #1;                   
        t_pc <= PCnt.data_out;
        #10;
        if(PCnt.data_out != t_pc) $fatal(1,"Error in ECALL instruction");
        


        t_rstn <= 0;
        #2;
        t_rstn <= 1;
        $readmemh("P_TB_test2.mem", Processor.InstructionMemory.rom);
         






































        #3;

        #3;

        #3;
        

        #1;
        t_pc <= PCnt.data_out;
        #2;
        if(PCnt.data_out != (t_pc + 32'd4)) $fatal(1,"Error in BEQ instruction");
        

        #1;
        t_pc <= PCnt.data_out;
        #2;
        if(PCnt.data_out != (t_pc + 32'd8)) $fatal(1,"Error in BEQ instruction");
        

 
        #1;
        t_pc <= PCnt.data_out;
        #2;
        if(PCnt.data_out != (t_pc + 32'd4)) $fatal(1,"Error in BNE instruction");
        

        #1;
        t_pc <= PCnt.data_out;
        #2;
        if(PCnt.data_out != (t_pc + 32'd8)) $fatal(1,"Error in BNE instruction");
         

        #1;
        t_pc <= PCnt.data_out;
        #2;
        if(PCnt.data_out != (t_pc + 32'd4)) $fatal(1,"Error in BLT instruction");
        

        #1;
        t_pc <= PCnt.data_out;
        #2;
        if(PCnt.data_out != (t_pc + 32'd8)) $fatal(1,"Error in BLT instruction");
        

        #1;
        t_pc <= PCnt.data_out;
        #2;
        if(PCnt.data_out != (t_pc + 32'd4)) $fatal(1,"Error in BLTU instruction");
        

        #1;
        t_pc <= PCnt.data_out;
        #2;
        if(PCnt.data_out != (t_pc + 32'd8)) $fatal(1,"Error in BLTU instruction");
        

        #1;
        t_pc <= PCnt.data_out;
        #2;
        if(PCnt.data_out != (t_pc + 32'd4)) $fatal(1,"Error in BGE instruction");
        

        #1;
        t_pc <= PCnt.data_out;
        #2;
        if(PCnt.data_out != (t_pc + 32'd8)) $fatal(1,"Error in BGE instruction");
       

        #1;
        t_pc <= PCnt.data_out;
        #2;
        if(PCnt.data_out != (t_pc + 32'd4)) $fatal(1,"Error in BGEU instruction");
        

        #1;
        t_pc <= PCnt.data_out;
        #2;
        if(PCnt.data_out != (t_pc + 32'd8)) $fatal(1,"Error in BGEU instruction");
        

        #3;
        

        #1;                   
        t_pc <= PCnt.data_out;
        #10;
        if(PCnt.data_out != t_pc) $fatal(1,"Error in HALT instruction");       
        
        

        t_rstn <= 0;
        #2;
        t_rstn <= 1;
        $readmemh("P_TB_test3.mem", Processor.InstructionMemory.rom);















        

        #3;

        #3;

        #3;
         

        #4;
        if(DMem.ram[2][7:0] != 8'hFA) $fatal(1,"Error in SB instruction");
        

        #4;
        if(DMem.ram[3][15:0] != 16'hF0FA) $fatal(1,"Error in SH instruction");
        

        #4;
        if(DMem.ram[1] != 32'hFB39F0FA) $fatal(1,"Error in SW instruction");


        #4;
        if(RegFile.r[6] != 32'hFFFFFFFA) $fatal(1,"Error in LB instruction");
        

        #4;
        if(RegFile.r[7] != 32'hFFFFF0FA) $fatal(1,"Error in LH instruction");
        

        #4;
        if(RegFile.r[9] != 32'h000000FA) $fatal(1,"Error in LBU instruction");
        

        #4;
        if(RegFile.r[10] != 32'h0000F0FA) $fatal(1,"Error in LHU instruction");
        

        #4;
        if(RegFile.r[8] != 32'hF53F30FA) $fatal(1,"Error in LW instruction");
        


        
        



        t_rstn <= 0;
        #2;
        t_rstn <= 1;
        $readmemh("P_TB_test4.mem", Processor.InstructionMemory.rom);  



























        

        #3;
        if(RegFile.r[1] != 32'b10111011) $fatal(1,"Error in ADDI instruction");
        

        #3;
        

        #3;
        if(RegFile.r[3] != 32'd5) $fatal(1,"Error in ADDI instruction");
        

        #3;
        if(RegFile.r[5] != 32'd1) $fatal(1,"Error in SLTI instruction");


        #3;
        if(RegFile.r[6] != 32'd0) $fatal(1,"Error in SLTIU instruction");
        

        #3;
        if(RegFile.r[4] != 32'b00001000) $fatal(1,"Error in XORI instruction");
        

        #3;
        if(RegFile.r[5] != 32'b10111011) $fatal(1,"Error in ORI instruction");
        

        #3;
        if(RegFile.r[6] != 32'b10110010) $fatal(1,"Error in ANDI instruction");
                

        #3;
        if(RegFile.r[4] != 32'b101110110000000) $fatal(1,"Error in SLLI instruction");
        

        #3;
        if(RegFile.r[5] != 32'b10111) $fatal(1,"Error in SRLI instruction");
        

        #3;
        if(RegFile.r[6] != 32'b1011) $fatal(1,"Error in SRAI instruction");
        

        #3;
        if(RegFile.r[4] != 32'd171) $fatal(1,"Error in ADD instruction");
        

        #3;
        if(RegFile.r[5] != 32'd161) $fatal(1,"Error in SUB instruction");
        

        #3;
        if(RegFile.r[6] != 32'b1010011000000) $fatal(1,"Error in SLL instruction");
        

        #3;                                                                      
        if(RegFile.r[7] != 32'd0) $fatal(1,"Error in SLT instruction");
        

        #3;                                                                      
        if(RegFile.r[8] != 32'd0) $fatal(1,"Error in SLTU instruction");
        

        #3;
        if(RegFile.r[4] != 32'b00011101) $fatal(1,"Error in XOR instruction");
        

        #3;                                                                      
        if(RegFile.r[5] != 32'b101) $fatal(1,"Error in SRL instruction");
        

        #3;                                                                      
        if(RegFile.r[6] != 32'b101) $fatal(1,"Error in SRA instruction");
        

        #3;
        if(RegFile.r[7] != 32'b10111111) $fatal(1,"Error in OR instruction");
        

         #3;
        if(RegFile.r[8] != 32'b10100010) $fatal(1,"Error in AND instruction");
        

        #1
        t_pc <= PCnt.data_out;
        #2
        if(PCnt.data_out != (t_pc + 32'd4)) $fatal(1,"Error in FENCE instruction");
        

        #3

        #1;                   
        t_pc <= PCnt.data_out;
        #10;
        if(PCnt.data_out != t_pc) $fatal(1,"Error in HALT instruction");
        
        
        $display("\nAll test Passed\n");
        $finish;
    end
endmodule