data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_pipe_flow.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_pipe_flow.v:34: Cannot find include file: sys.h\n`include "sys.h" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_pipe_flow.v:111: Unsupported or unknown PLI call: $monInit\n     $monInit();\n     ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
function [5:0] get_match_index;
    input [31:0] pc;
    integer i ;
begin
    for(i=0; i<=63; i=i+1)
    begin
        if(pc_array[i] === pc) get_match_index = i;
    end
end
endfunction
function [5:0] get_match_index;

    input [31:0] pc;
    integer i ;
begin
    for(i=0; i<=63; i=i+1)
    begin
        if(pc_array[i] === pc) get_match_index = i;
    end
end
endfunction