data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/rtlshiftdatx4.v
1: b'%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/rtlshiftdatx4.v:85: Operator COND expects 96 bits on the Conditional True, but Conditional True\'s VARREF \'idat\' generates 32 bits.\n                                                                                                                                    : ... In instance rtlshiftdatx4\nassign              idatlat = (nob == 2\'d0) ? idat : \n                                            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/rtlshiftdatx4.v:86: Operator COND expects 96 bits on the Conditional True, but Conditional True\'s REPLICATE generates 64 bits.\n                                                                                                                                    : ... In instance rtlshiftdatx4\n                              (nob == 2\'d1) ? {odatlat[WID-1:0],idat} : {odatlat[2*WID-1:0],idat};\n                                            ^\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/rtlshiftdatx4.v:88: Cannot find file containing module: \'fflopx\'\nfflopx #(2) ppnob (clk,rst,ivld & ieop ? 2\'d0 : nob + ivld,nob);\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/fflopx\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/fflopx.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/fflopx.sv\n             fflopx\n             fflopx.v\n             fflopx.sv\n             obj_dir/fflopx\n             obj_dir/fflopx.v\n             obj_dir/fflopx.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/rtlshiftdatx4.v:89: Cannot find file containing module: \'fflopx\'\nfflopx #(1) iosoplat (clk,rst,ovld ? 1\'b0 : ivld & isop ? 1\'b1 : osoplat,osoplat);\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/rtlshiftdatx4.v:90: Cannot find file containing module: \'fflopxe\'\nfflopxe #(3*WID) iodatlat (clk,rst,ivld,idatlat,odatlat);\n^~~~~~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module rtlshiftdatx4
    (clk,
     rst,


     idat,
     ivld,
     isop,
     ieop,
     iinf,
     inob,
     

     odat,
     ovld,
     osop,
     oeop,
     oinf,
     onob
     );



parameter           WID = 32;
parameter           NOB = 2;
parameter           INF = 1;




input               clk,
                    rst;


input [WID-1:0]     idat;
input               ivld,
                    isop,
                    ieop;
input [NOB-1:0]     inob;
input [INF-1:0]     iinf;


output [WID*4-1:0]  odat;
output              ovld,
                    osop,
                    oeop;
output [NOB+1:0]    onob;
output [INF-1:0]    oinf;







wire                ovld;
wire [WID*3-1:0]    odatlat,idatlat;
wire [WID*4-1:0]    odat;
wire [NOB+1:0]      onob;
wire [1:0]          nob;            
wire                oeop,osop,osoplat;
wire [INF-1:0]      oinf;

assign              ovld = ivld & (ieop | (&onob));
assign              osop = ovld & osoplat;
assign              oeop = ieop;
assign              oinf = iinf;
assign              odat = (nob == 2'd0) ? {idat,{(3*WID){1'b0}}} :
                           (nob == 2'd1) ? {odatlat[WID-1:0],idat,{(2*WID){1'b0}}} :
                           (nob == 2'd2) ? {odatlat[2*WID-1:0],idat,{(1*WID){1'b0}}} : {odatlat,idat};
assign              onob = {nob,inob};
assign              idatlat = (nob == 2'd0) ? idat : 
                              (nob == 2'd1) ? {odatlat[WID-1:0],idat} : {odatlat[2*WID-1:0],idat};
 
fflopx #(2) ppnob (clk,rst,ivld & ieop ? 2'd0 : nob + ivld,nob);
fflopx #(1) iosoplat (clk,rst,ovld ? 1'b0 : ivld & isop ? 1'b1 : osoplat,osoplat);
fflopxe #(3*WID) iodatlat (clk,rst,ivld,idatlat,odatlat);

endmodule
module rtlshiftdatx4
    (clk,
     rst,


     idat,
     ivld,
     isop,
     ieop,
     iinf,
     inob,
     

     odat,
     ovld,
     osop,
     oeop,
     oinf,
     onob
     );




parameter           WID = 32;
parameter           NOB = 2;
parameter           INF = 1;




input               clk,
                    rst;


input [WID-1:0]     idat;
input               ivld,
                    isop,
                    ieop;
input [NOB-1:0]     inob;
input [INF-1:0]     iinf;


output [WID*4-1:0]  odat;
output              ovld,
                    osop,
                    oeop;
output [NOB+1:0]    onob;
output [INF-1:0]    oinf;







wire                ovld;
wire [WID*3-1:0]    odatlat,idatlat;
wire [WID*4-1:0]    odat;
wire [NOB+1:0]      onob;
wire [1:0]          nob;            
wire                oeop,osop,osoplat;
wire [INF-1:0]      oinf;

assign              ovld = ivld & (ieop | (&onob));
assign              osop = ovld & osoplat;
assign              oeop = ieop;
assign              oinf = iinf;
assign              odat = (nob == 2'd0) ? {idat,{(3*WID){1'b0}}} :
                           (nob == 2'd1) ? {odatlat[WID-1:0],idat,{(2*WID){1'b0}}} :
                           (nob == 2'd2) ? {odatlat[2*WID-1:0],idat,{(1*WID){1'b0}}} : {odatlat,idat};
assign              onob = {nob,inob};
assign              idatlat = (nob == 2'd0) ? idat : 
                              (nob == 2'd1) ? {odatlat[WID-1:0],idat} : {odatlat[2*WID-1:0],idat};
 
fflopx #(2) ppnob (clk,rst,ivld & ieop ? 2'd0 : nob + ivld,nob);
fflopx #(1) iosoplat (clk,rst,ovld ? 1'b0 : ivld & isop ? 1'b1 : osoplat,osoplat);
fflopxe #(3*WID) iodatlat (clk,rst,ivld,idatlat,odatlat);

endmodule