data/full_repos/permissive/447976230/fpga/usrp2/control_lib/bin2gray.v
data/verilator_xmls/1789b7e7-bb5f-4d0c-b474-7660bf8d2dd1.xml
module bin2gray
  #(parameter WIDTH=8)
    (input [WIDTH-1:0] bin,
     output [WIDTH-1:0] gray);

   assign 		gray = (bin >> 1) ^ bin;
   
endmodule
module bin2gray
  #(parameter WIDTH=8)
    (input [WIDTH-1:0] bin,
     output [WIDTH-1:0] gray);


   assign 		gray = (bin >> 1) ^ bin;
   
endmodule