data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_ack_msg.v
1: b'%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_ack_msg.v:3: Cannot find include file: tcu_parameter.vh\n    `include "tcu_parameter.vh" \n             ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog,data/full_repos/permissive/463204869/tcu_parameter.vh\n             data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog,data/full_repos/permissive/463204869/tcu_parameter.vh.v\n             data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog,data/full_repos/permissive/463204869/tcu_parameter.vh.sv\n             tcu_parameter.vh\n             tcu_parameter.vh.v\n             tcu_parameter.vh.sv\n             obj_dir/tcu_parameter.vh\n             obj_dir/tcu_parameter.vh.v\n             obj_dir/tcu_parameter.vh.sv\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_ack_msg.v:4: syntax error, unexpected \',\', expecting \'[\'\n    ,parameter TCU_ENABLE_VIRT_PES = 0\n    ^\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_ack_msg.v:5: syntax error, unexpected \')\', expecting \';\'\n)(\n^\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_ack_msg.v:7: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          reset_n_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_ack_msg.v:11: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                           am_reg_en_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_ack_msg.v:12: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg   [TCU_REG_DATA_SIZE-1:0] am_reg_wben_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_ack_msg.v:13: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output wire  [TCU_REG_ADDR_SIZE-1:0] am_reg_addr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_ack_msg.v:14: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire  [TCU_REG_DATA_SIZE-1:0] am_reg_wdata_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_ack_msg.v:15: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire  [TCU_REG_DATA_SIZE-1:0] am_reg_rdata_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_ack_msg.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          am_reg_stall_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_ack_msg.v:20: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          am_start_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_ack_msg.v:21: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire    [TCU_OPCODE_SIZE-1:0] am_opcode_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_ack_msg.v:22: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                   [31:0] am_rmsgoffset_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_ack_msg.v:23: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire        [TCU_EP_SIZE-1:0] am_recvep_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_ack_msg.v:24: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire               [3*64-1:0] am_epdata_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_ack_msg.v:25: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                   [31:0] am_cur_vpe_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_ack_msg.v:26: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                          am_active_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_ack_msg.v:27: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                          am_done_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_ack_msg.v:28: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire     [TCU_ERROR_SIZE-1:0] am_error_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_ack_msg.v:32: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          tcu_features_virt_pes_i\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_ack_msg.v:98: syntax error, unexpected always\n    always @(posedge clk_i) begin\n    ^~~~~~\n%Error: Exiting due to 21 error(s)\n'
module tcu_ctrl_ack_msg #(
    `include "tcu_parameter.vh"
    ,parameter TCU_ENABLE_VIRT_PES = 0
)(
    input  wire                          clk_i,
    input  wire                          reset_n_i,



    output reg                           am_reg_en_o,
    output reg   [TCU_REG_DATA_SIZE-1:0] am_reg_wben_o,
    output wire  [TCU_REG_ADDR_SIZE-1:0] am_reg_addr_o,
    output wire  [TCU_REG_DATA_SIZE-1:0] am_reg_wdata_o,
    input  wire  [TCU_REG_DATA_SIZE-1:0] am_reg_rdata_i,
    input  wire                          am_reg_stall_i,



    input  wire                          am_start_i,
    input  wire    [TCU_OPCODE_SIZE-1:0] am_opcode_i,
    input  wire                   [31:0] am_rmsgoffset_i,
    input  wire        [TCU_EP_SIZE-1:0] am_recvep_i,
    input  wire               [3*64-1:0] am_epdata_i,
    input  wire                   [31:0] am_cur_vpe_i,
    output wire                          am_active_o,
    output wire                          am_done_o,
    output wire     [TCU_ERROR_SIZE-1:0] am_error_o,



    input  wire                          tcu_features_virt_pes_i
);

    localparam CTRL_AM_STATES_SIZE   = 3;
    localparam S_CTRL_AM_IDLE        = 3'h0;
    localparam S_CTRL_AM_UPDATE_EP1  = 3'h1;
    localparam S_CTRL_AM_UPDATE_EP2  = 3'h2;
    localparam S_CTRL_AM_READ_SEP    = 3'h3;
    localparam S_CTRL_AM_UPDATE_SEP  = 3'h4;
    localparam S_CTRL_AM_UPDATE_VPE1 = 3'h5;
    localparam S_CTRL_AM_UPDATE_VPE2 = 3'h6;
    localparam S_CTRL_AM_FINISH      = 3'h7;

    reg [CTRL_AM_STATES_SIZE-1:0] ctrl_am_state, next_ctrl_am_state;


    reg [TCU_SLOT_SIZE-1:0] r_tmp_pos, rin_tmp_pos;


    reg [63:0] r_rep_0, rin_rep_0;
    reg [63:0] r_rep_2, rin_rep_2;

    reg [TCU_REG_DATA_SIZE-1:0] r_reg_wben, rin_reg_wben;
    reg [TCU_REG_ADDR_SIZE-1:0] r_reg_addr, rin_reg_addr;
    reg [TCU_REG_DATA_SIZE-1:0] r_reg_wdata, rin_reg_wdata;


    reg [31:0] r_recvep_baseaddr, rin_recvep_baseaddr;


    reg [TCU_ERROR_SIZE-1:0] r_am_error, rin_am_error;



    wire [TCU_EP_TYPE_SIZE-1:0] rep_type_s     = am_epdata_i[TCU_EP_TYPE_SIZE-1 : 0];
    wire   [TCU_VPEID_SIZE-1:0] rep_vpeid_s    = am_epdata_i[TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE-1 : TCU_EP_TYPE_SIZE];
    wire      [TCU_EP_SIZE-1:0] rep_rpleps_s   = am_epdata_i[TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE-1 : TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE];
    wire    [TCU_SLOT_SIZE-1:0] rep_slots_s    = am_epdata_i[TCU_SLOT_SIZE+TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE-1 : TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE];
    wire    [TCU_SLOT_SIZE-1:0] rep_slotsize_s = am_epdata_i[2*TCU_SLOT_SIZE+TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE-1 : TCU_SLOT_SIZE+TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE];
    wire    [TCU_SLOT_SIZE-1:0] rep_wpos_s     = am_epdata_i[3*TCU_SLOT_SIZE+TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE-1 : 2*TCU_SLOT_SIZE+TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE];
    wire    [TCU_SLOT_SIZE-1:0] rep_rpos_s     = am_epdata_i[4*TCU_SLOT_SIZE+TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE-1 : 3*TCU_SLOT_SIZE+TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE];
    wire                 [31:0] rep_occupied_s = am_epdata_i[2*64+32-1 : 2*64];
    wire                 [31:0] rep_unread_s   = am_epdata_i[3*64-1 : 2*64+32];


    wire [TCU_EP_TYPE_SIZE-1:0] rep_type     = r_rep_0[TCU_EP_TYPE_SIZE-1 : 0];
    wire   [TCU_VPEID_SIZE-1:0] rep_vpeid    = r_rep_0[TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE-1 : TCU_EP_TYPE_SIZE];
    wire      [TCU_EP_SIZE-1:0] rep_rpleps   = r_rep_0[TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE-1 : TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE];
    wire    [TCU_SLOT_SIZE-1:0] rep_slots    = r_rep_0[TCU_SLOT_SIZE+TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE-1 : TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE];
    wire    [TCU_SLOT_SIZE-1:0] rep_slotsize = r_rep_0[2*TCU_SLOT_SIZE+TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE-1 : TCU_SLOT_SIZE+TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE];
    wire    [TCU_SLOT_SIZE-1:0] rep_wpos     = r_rep_0[3*TCU_SLOT_SIZE+TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE-1 : 2*TCU_SLOT_SIZE+TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE];
    wire    [TCU_SLOT_SIZE-1:0] rep_rpos     = r_rep_0[4*TCU_SLOT_SIZE+TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE-1 : 3*TCU_SLOT_SIZE+TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE];
    wire                 [31:0] rep_occupied = r_rep_2[31:0];
    wire                 [31:0] rep_unread   = r_rep_2[63:32];


    wire     [TCU_SLOT_SIZE-1:0] tmp_pos = am_rmsgoffset_i >> rep_slotsize_s;
    wire [TCU_REG_DATA_SIZE-1:0] set_bit_pos = 32'h1 << r_tmp_pos;

    wire [31:0] recvep_addr = TCU_REGADDR_EP_START + am_recvep_i*TCU_EP_REG_SIZE;


    wire [TCU_REG_DATA_SIZE-1:0] cur_vpe_msgs_decr = am_cur_vpe_i[TCU_VPE_MSGS_SIZE+TCU_VPEID_SIZE-1:TCU_VPEID_SIZE] - 'd1;



    always @(posedge clk_i) begin
        if (reset_n_i == 1'b0) begin
            ctrl_am_state <= S_CTRL_AM_IDLE;

            r_reg_wben <= {TCU_REG_DATA_SIZE{1'b0}};
            r_reg_addr <= {TCU_REG_ADDR_SIZE{1'b0}};
            r_reg_wdata <= {TCU_REG_DATA_SIZE{1'b0}};

            r_tmp_pos <= {TCU_SLOT_SIZE{1'b0}};

            r_rep_0 <= 64'h0;
            r_rep_2 <= 64'h0;

            r_recvep_baseaddr <= 32'h0;

            r_am_error <= TCU_ERROR_NONE;
        end
        else begin
            ctrl_am_state <= next_ctrl_am_state;

            r_reg_wben <= rin_reg_wben;
            r_reg_addr  <= rin_reg_addr;
            r_reg_wdata <= rin_reg_wdata;

            r_tmp_pos <= rin_tmp_pos;

            r_rep_0 <= rin_rep_0;
            r_rep_2 <= rin_rep_2;

            r_recvep_baseaddr <= rin_recvep_baseaddr;

            r_am_error <= rin_am_error;
        end
    end






    always @* begin
        next_ctrl_am_state = ctrl_am_state;

        rin_tmp_pos = r_tmp_pos;
        
        rin_rep_0 = r_rep_0;
        rin_rep_2 = r_rep_2;

        rin_recvep_baseaddr = r_recvep_baseaddr;

        rin_reg_wben = r_reg_wben;
        rin_reg_addr = r_reg_addr;
        rin_reg_wdata = r_reg_wdata;

        rin_am_error = r_am_error;


        case (ctrl_am_state)



            S_CTRL_AM_IDLE: begin
                if (am_start_i && (am_opcode_i == TCU_OPCODE_ACK_MSG)) begin


                    if (rep_type_s == TCU_EP_TYPE_RECEIVE) begin


                        if ((rep_rpleps_s == {TCU_EP_SIZE{1'b1}}) || (rep_rpleps_s+(32'h1 << rep_slots_s) <= TCU_EP_REG_COUNT)) begin


                            if (!(TCU_ENABLE_VIRT_PES && tcu_features_virt_pes_i) || (am_cur_vpe_i[TCU_VPEID_SIZE-1:0] == rep_vpeid_s)) begin


                                if (tmp_pos < ({{(TCU_SLOT_SIZE-1){1'b0}}, 1'b1} << rep_slots_s)) begin
                                    rin_tmp_pos = tmp_pos;

                                    rin_rep_0 = am_epdata_i[63:0];
                                    rin_rep_2 = am_epdata_i[3*64-1:2*64];


                                    rin_recvep_baseaddr = recvep_addr;

                                    rin_am_error = TCU_ERROR_NONE;

                                    if (TCU_ENABLE_VIRT_PES && tcu_features_virt_pes_i) begin
                                        next_ctrl_am_state = S_CTRL_AM_UPDATE_VPE1;
                                    end else begin
                                        next_ctrl_am_state = S_CTRL_AM_UPDATE_EP1;
                                    end
                                end
                                else begin
                                    rin_am_error = TCU_ERROR_INV_MSG_OFF;
                                    next_ctrl_am_state = S_CTRL_AM_FINISH;
                                end
                            end
                            else begin
                                rin_am_error = TCU_ERROR_FOREIGN_EP;
                                next_ctrl_am_state = S_CTRL_AM_FINISH;
                            end
                        end
                        else begin
                            rin_am_error = TCU_ERROR_RECV_INV_RPL_EPS;
                            next_ctrl_am_state = S_CTRL_AM_FINISH;
                        end
                    end
                    else begin
                        rin_am_error = TCU_ERROR_NO_REP;
                        next_ctrl_am_state = S_CTRL_AM_FINISH;
                    end
                end
            end



            S_CTRL_AM_UPDATE_VPE1: begin
                if (TCU_ENABLE_VIRT_PES && tcu_features_virt_pes_i) begin
                    if (rep_unread[r_tmp_pos]) begin

                        rin_reg_wben = {{(TCU_REG_DATA_SIZE-TCU_VPE_MSGS_SIZE){1'b0}}, {TCU_VPE_MSGS_SIZE{1'b1}}} << TCU_VPEID_SIZE;
                        rin_reg_addr = TCU_REGADDR_CUR_VPE;
                        rin_reg_wdata = cur_vpe_msgs_decr << TCU_VPEID_SIZE;

                        next_ctrl_am_state = S_CTRL_AM_UPDATE_VPE2;
                    end
                    else begin
                        next_ctrl_am_state = S_CTRL_AM_UPDATE_EP1;
                    end
                end
            end

            S_CTRL_AM_UPDATE_VPE2: begin
                if (TCU_ENABLE_VIRT_PES) begin
                    if (!am_reg_stall_i) begin
                        next_ctrl_am_state = S_CTRL_AM_UPDATE_EP1;
                    end
                end
            end



            S_CTRL_AM_UPDATE_EP1: begin
                rin_reg_wben = (set_bit_pos<<32) | set_bit_pos;
                rin_reg_addr = r_recvep_baseaddr + 'h10;
                rin_reg_wdata = {TCU_REG_DATA_SIZE{1'b0}};

                next_ctrl_am_state = S_CTRL_AM_UPDATE_EP2;
            end

            S_CTRL_AM_UPDATE_EP2: begin
                if (!am_reg_stall_i) begin

                    if (rep_rpleps != {TCU_EP_SIZE{1'b1}}) begin
                        rin_reg_wben = {TCU_EP_TYPE_SIZE{1'b1}};
                        rin_reg_addr = TCU_REGADDR_EP_START + (rep_rpleps+r_tmp_pos)*TCU_EP_REG_SIZE;
                        rin_reg_wdata = TCU_EP_TYPE_INVALID;

                        next_ctrl_am_state = S_CTRL_AM_UPDATE_SEP;
                    end
                    else begin
                        next_ctrl_am_state = S_CTRL_AM_FINISH;
                    end
                end
            end



            S_CTRL_AM_UPDATE_SEP: begin

                if (!am_reg_stall_i) begin
                    next_ctrl_am_state = S_CTRL_AM_FINISH;
                end
            end


            S_CTRL_AM_FINISH: begin
                next_ctrl_am_state = S_CTRL_AM_IDLE;
            end



        endcase
    end







    always @* begin
        am_reg_en_o = 1'b0;
        am_reg_wben_o = {TCU_REG_DATA_SIZE{1'b0}};

        if ((ctrl_am_state == S_CTRL_AM_UPDATE_EP2) ||
            (ctrl_am_state == S_CTRL_AM_UPDATE_SEP)) begin
            am_reg_en_o = 1'b1;
            am_reg_wben_o = r_reg_wben;
        end
        else if (ctrl_am_state == S_CTRL_AM_READ_SEP) begin
            am_reg_en_o = 1'b1;
            am_reg_wben_o = {TCU_REG_BSEL_SIZE{1'b0}};
        end
        else if (TCU_ENABLE_VIRT_PES && (ctrl_am_state == S_CTRL_AM_UPDATE_VPE2)) begin
            am_reg_en_o = 1'b1;
            am_reg_wben_o = r_reg_wben;
        end
    end

    assign am_reg_addr_o = r_reg_addr;
    assign am_reg_wdata_o = r_reg_wdata;

    assign am_error_o = r_am_error;
    assign am_active_o = (ctrl_am_state != S_CTRL_AM_IDLE);
    assign am_done_o = (ctrl_am_state == S_CTRL_AM_FINISH);


endmodule
module tcu_ctrl_ack_msg #(
    `include "tcu_parameter.vh"
    ,parameter TCU_ENABLE_VIRT_PES = 0
)(
    input  wire                          clk_i,
    input  wire                          reset_n_i,



    output reg                           am_reg_en_o,
    output reg   [TCU_REG_DATA_SIZE-1:0] am_reg_wben_o,
    output wire  [TCU_REG_ADDR_SIZE-1:0] am_reg_addr_o,
    output wire  [TCU_REG_DATA_SIZE-1:0] am_reg_wdata_o,
    input  wire  [TCU_REG_DATA_SIZE-1:0] am_reg_rdata_i,
    input  wire                          am_reg_stall_i,



    input  wire                          am_start_i,
    input  wire    [TCU_OPCODE_SIZE-1:0] am_opcode_i,
    input  wire                   [31:0] am_rmsgoffset_i,
    input  wire        [TCU_EP_SIZE-1:0] am_recvep_i,
    input  wire               [3*64-1:0] am_epdata_i,
    input  wire                   [31:0] am_cur_vpe_i,
    output wire                          am_active_o,
    output wire                          am_done_o,
    output wire     [TCU_ERROR_SIZE-1:0] am_error_o,



    input  wire                          tcu_features_virt_pes_i
);


    localparam CTRL_AM_STATES_SIZE   = 3;
    localparam S_CTRL_AM_IDLE        = 3'h0;
    localparam S_CTRL_AM_UPDATE_EP1  = 3'h1;
    localparam S_CTRL_AM_UPDATE_EP2  = 3'h2;
    localparam S_CTRL_AM_READ_SEP    = 3'h3;
    localparam S_CTRL_AM_UPDATE_SEP  = 3'h4;
    localparam S_CTRL_AM_UPDATE_VPE1 = 3'h5;
    localparam S_CTRL_AM_UPDATE_VPE2 = 3'h6;
    localparam S_CTRL_AM_FINISH      = 3'h7;

    reg [CTRL_AM_STATES_SIZE-1:0] ctrl_am_state, next_ctrl_am_state;


    reg [TCU_SLOT_SIZE-1:0] r_tmp_pos, rin_tmp_pos;


    reg [63:0] r_rep_0, rin_rep_0;
    reg [63:0] r_rep_2, rin_rep_2;

    reg [TCU_REG_DATA_SIZE-1:0] r_reg_wben, rin_reg_wben;
    reg [TCU_REG_ADDR_SIZE-1:0] r_reg_addr, rin_reg_addr;
    reg [TCU_REG_DATA_SIZE-1:0] r_reg_wdata, rin_reg_wdata;


    reg [31:0] r_recvep_baseaddr, rin_recvep_baseaddr;


    reg [TCU_ERROR_SIZE-1:0] r_am_error, rin_am_error;



    wire [TCU_EP_TYPE_SIZE-1:0] rep_type_s     = am_epdata_i[TCU_EP_TYPE_SIZE-1 : 0];
    wire   [TCU_VPEID_SIZE-1:0] rep_vpeid_s    = am_epdata_i[TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE-1 : TCU_EP_TYPE_SIZE];
    wire      [TCU_EP_SIZE-1:0] rep_rpleps_s   = am_epdata_i[TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE-1 : TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE];
    wire    [TCU_SLOT_SIZE-1:0] rep_slots_s    = am_epdata_i[TCU_SLOT_SIZE+TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE-1 : TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE];
    wire    [TCU_SLOT_SIZE-1:0] rep_slotsize_s = am_epdata_i[2*TCU_SLOT_SIZE+TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE-1 : TCU_SLOT_SIZE+TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE];
    wire    [TCU_SLOT_SIZE-1:0] rep_wpos_s     = am_epdata_i[3*TCU_SLOT_SIZE+TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE-1 : 2*TCU_SLOT_SIZE+TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE];
    wire    [TCU_SLOT_SIZE-1:0] rep_rpos_s     = am_epdata_i[4*TCU_SLOT_SIZE+TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE-1 : 3*TCU_SLOT_SIZE+TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE];
    wire                 [31:0] rep_occupied_s = am_epdata_i[2*64+32-1 : 2*64];
    wire                 [31:0] rep_unread_s   = am_epdata_i[3*64-1 : 2*64+32];


    wire [TCU_EP_TYPE_SIZE-1:0] rep_type     = r_rep_0[TCU_EP_TYPE_SIZE-1 : 0];
    wire   [TCU_VPEID_SIZE-1:0] rep_vpeid    = r_rep_0[TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE-1 : TCU_EP_TYPE_SIZE];
    wire      [TCU_EP_SIZE-1:0] rep_rpleps   = r_rep_0[TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE-1 : TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE];
    wire    [TCU_SLOT_SIZE-1:0] rep_slots    = r_rep_0[TCU_SLOT_SIZE+TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE-1 : TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE];
    wire    [TCU_SLOT_SIZE-1:0] rep_slotsize = r_rep_0[2*TCU_SLOT_SIZE+TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE-1 : TCU_SLOT_SIZE+TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE];
    wire    [TCU_SLOT_SIZE-1:0] rep_wpos     = r_rep_0[3*TCU_SLOT_SIZE+TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE-1 : 2*TCU_SLOT_SIZE+TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE];
    wire    [TCU_SLOT_SIZE-1:0] rep_rpos     = r_rep_0[4*TCU_SLOT_SIZE+TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE-1 : 3*TCU_SLOT_SIZE+TCU_EP_SIZE+TCU_VPEID_SIZE+TCU_EP_TYPE_SIZE];
    wire                 [31:0] rep_occupied = r_rep_2[31:0];
    wire                 [31:0] rep_unread   = r_rep_2[63:32];


    wire     [TCU_SLOT_SIZE-1:0] tmp_pos = am_rmsgoffset_i >> rep_slotsize_s;
    wire [TCU_REG_DATA_SIZE-1:0] set_bit_pos = 32'h1 << r_tmp_pos;

    wire [31:0] recvep_addr = TCU_REGADDR_EP_START + am_recvep_i*TCU_EP_REG_SIZE;


    wire [TCU_REG_DATA_SIZE-1:0] cur_vpe_msgs_decr = am_cur_vpe_i[TCU_VPE_MSGS_SIZE+TCU_VPEID_SIZE-1:TCU_VPEID_SIZE] - 'd1;



    always @(posedge clk_i) begin
        if (reset_n_i == 1'b0) begin
            ctrl_am_state <= S_CTRL_AM_IDLE;

            r_reg_wben <= {TCU_REG_DATA_SIZE{1'b0}};
            r_reg_addr <= {TCU_REG_ADDR_SIZE{1'b0}};
            r_reg_wdata <= {TCU_REG_DATA_SIZE{1'b0}};

            r_tmp_pos <= {TCU_SLOT_SIZE{1'b0}};

            r_rep_0 <= 64'h0;
            r_rep_2 <= 64'h0;

            r_recvep_baseaddr <= 32'h0;

            r_am_error <= TCU_ERROR_NONE;
        end
        else begin
            ctrl_am_state <= next_ctrl_am_state;

            r_reg_wben <= rin_reg_wben;
            r_reg_addr  <= rin_reg_addr;
            r_reg_wdata <= rin_reg_wdata;

            r_tmp_pos <= rin_tmp_pos;

            r_rep_0 <= rin_rep_0;
            r_rep_2 <= rin_rep_2;

            r_recvep_baseaddr <= rin_recvep_baseaddr;

            r_am_error <= rin_am_error;
        end
    end






    always @* begin
        next_ctrl_am_state = ctrl_am_state;

        rin_tmp_pos = r_tmp_pos;
        
        rin_rep_0 = r_rep_0;
        rin_rep_2 = r_rep_2;

        rin_recvep_baseaddr = r_recvep_baseaddr;

        rin_reg_wben = r_reg_wben;
        rin_reg_addr = r_reg_addr;
        rin_reg_wdata = r_reg_wdata;

        rin_am_error = r_am_error;


        case (ctrl_am_state)



            S_CTRL_AM_IDLE: begin
                if (am_start_i && (am_opcode_i == TCU_OPCODE_ACK_MSG)) begin


                    if (rep_type_s == TCU_EP_TYPE_RECEIVE) begin


                        if ((rep_rpleps_s == {TCU_EP_SIZE{1'b1}}) || (rep_rpleps_s+(32'h1 << rep_slots_s) <= TCU_EP_REG_COUNT)) begin


                            if (!(TCU_ENABLE_VIRT_PES && tcu_features_virt_pes_i) || (am_cur_vpe_i[TCU_VPEID_SIZE-1:0] == rep_vpeid_s)) begin


                                if (tmp_pos < ({{(TCU_SLOT_SIZE-1){1'b0}}, 1'b1} << rep_slots_s)) begin
                                    rin_tmp_pos = tmp_pos;

                                    rin_rep_0 = am_epdata_i[63:0];
                                    rin_rep_2 = am_epdata_i[3*64-1:2*64];


                                    rin_recvep_baseaddr = recvep_addr;

                                    rin_am_error = TCU_ERROR_NONE;

                                    if (TCU_ENABLE_VIRT_PES && tcu_features_virt_pes_i) begin
                                        next_ctrl_am_state = S_CTRL_AM_UPDATE_VPE1;
                                    end else begin
                                        next_ctrl_am_state = S_CTRL_AM_UPDATE_EP1;
                                    end
                                end
                                else begin
                                    rin_am_error = TCU_ERROR_INV_MSG_OFF;
                                    next_ctrl_am_state = S_CTRL_AM_FINISH;
                                end
                            end
                            else begin
                                rin_am_error = TCU_ERROR_FOREIGN_EP;
                                next_ctrl_am_state = S_CTRL_AM_FINISH;
                            end
                        end
                        else begin
                            rin_am_error = TCU_ERROR_RECV_INV_RPL_EPS;
                            next_ctrl_am_state = S_CTRL_AM_FINISH;
                        end
                    end
                    else begin
                        rin_am_error = TCU_ERROR_NO_REP;
                        next_ctrl_am_state = S_CTRL_AM_FINISH;
                    end
                end
            end



            S_CTRL_AM_UPDATE_VPE1: begin
                if (TCU_ENABLE_VIRT_PES && tcu_features_virt_pes_i) begin
                    if (rep_unread[r_tmp_pos]) begin

                        rin_reg_wben = {{(TCU_REG_DATA_SIZE-TCU_VPE_MSGS_SIZE){1'b0}}, {TCU_VPE_MSGS_SIZE{1'b1}}} << TCU_VPEID_SIZE;
                        rin_reg_addr = TCU_REGADDR_CUR_VPE;
                        rin_reg_wdata = cur_vpe_msgs_decr << TCU_VPEID_SIZE;

                        next_ctrl_am_state = S_CTRL_AM_UPDATE_VPE2;
                    end
                    else begin
                        next_ctrl_am_state = S_CTRL_AM_UPDATE_EP1;
                    end
                end
            end

            S_CTRL_AM_UPDATE_VPE2: begin
                if (TCU_ENABLE_VIRT_PES) begin
                    if (!am_reg_stall_i) begin
                        next_ctrl_am_state = S_CTRL_AM_UPDATE_EP1;
                    end
                end
            end



            S_CTRL_AM_UPDATE_EP1: begin
                rin_reg_wben = (set_bit_pos<<32) | set_bit_pos;
                rin_reg_addr = r_recvep_baseaddr + 'h10;
                rin_reg_wdata = {TCU_REG_DATA_SIZE{1'b0}};

                next_ctrl_am_state = S_CTRL_AM_UPDATE_EP2;
            end

            S_CTRL_AM_UPDATE_EP2: begin
                if (!am_reg_stall_i) begin

                    if (rep_rpleps != {TCU_EP_SIZE{1'b1}}) begin
                        rin_reg_wben = {TCU_EP_TYPE_SIZE{1'b1}};
                        rin_reg_addr = TCU_REGADDR_EP_START + (rep_rpleps+r_tmp_pos)*TCU_EP_REG_SIZE;
                        rin_reg_wdata = TCU_EP_TYPE_INVALID;

                        next_ctrl_am_state = S_CTRL_AM_UPDATE_SEP;
                    end
                    else begin
                        next_ctrl_am_state = S_CTRL_AM_FINISH;
                    end
                end
            end



            S_CTRL_AM_UPDATE_SEP: begin

                if (!am_reg_stall_i) begin
                    next_ctrl_am_state = S_CTRL_AM_FINISH;
                end
            end


            S_CTRL_AM_FINISH: begin
                next_ctrl_am_state = S_CTRL_AM_IDLE;
            end



        endcase
    end







    always @* begin
        am_reg_en_o = 1'b0;
        am_reg_wben_o = {TCU_REG_DATA_SIZE{1'b0}};

        if ((ctrl_am_state == S_CTRL_AM_UPDATE_EP2) ||
            (ctrl_am_state == S_CTRL_AM_UPDATE_SEP)) begin
            am_reg_en_o = 1'b1;
            am_reg_wben_o = r_reg_wben;
        end
        else if (ctrl_am_state == S_CTRL_AM_READ_SEP) begin
            am_reg_en_o = 1'b1;
            am_reg_wben_o = {TCU_REG_BSEL_SIZE{1'b0}};
        end
        else if (TCU_ENABLE_VIRT_PES && (ctrl_am_state == S_CTRL_AM_UPDATE_VPE2)) begin
            am_reg_en_o = 1'b1;
            am_reg_wben_o = r_reg_wben;
        end
    end

    assign am_reg_addr_o = r_reg_addr;
    assign am_reg_wdata_o = r_reg_wdata;

    assign am_error_o = r_am_error;
    assign am_active_o = (ctrl_am_state != S_CTRL_AM_IDLE);
    assign am_done_o = (ctrl_am_state == S_CTRL_AM_FINISH);


endmodule