data/full_repos/permissive/434840709/lab6/code/clkDiv.v
data/verilator_xmls/f851c5a2-4d74-4c66-86aa-2ff6fc182e4f.xml
module clkDiv(
    input clk100mhz,
    output clk190hz,
    output clk12hz,
    output clk1_5hz
);

    reg [26:0]count=0;
    always@(posedge clk100mhz) begin
        count<=count+1; 
    end

    assign clk190hz = count[18];
    assign clk12hz  = count[22];
    assign clk1_5hz = count[25];

endmodule
module clkDiv(
    input clk100mhz,
    output clk190hz,
    output clk12hz,
    output clk1_5hz
);


    reg [26:0]count=0;
    always@(posedge clk100mhz) begin
        count<=count+1; 
    end

    assign clk190hz = count[18];
    assign clk12hz  = count[22];
    assign clk1_5hz = count[25];

endmodule