data/full_repos/permissive/49670587/vtr/ODIN_II/FULL_REGRESSION_TESTS/memory_controller.v
1: b"%Error: data/full_repos/permissive/49670587/vtr/ODIN_II/FULL_REGRESSION_TESTS/memory_controller.v:30: Cannot find file containing module: 'single_port_ram'\n single_port_ram sp_ram (  \n ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/49670587/vtr/ODIN_II/FULL_REGRESSION_TESTS,data/full_repos/permissive/49670587/single_port_ram\n             data/full_repos/permissive/49670587/vtr/ODIN_II/FULL_REGRESSION_TESTS,data/full_repos/permissive/49670587/single_port_ram.v\n             data/full_repos/permissive/49670587/vtr/ODIN_II/FULL_REGRESSION_TESTS,data/full_repos/permissive/49670587/single_port_ram.sv\n             single_port_ram\n             single_port_ram.v\n             single_port_ram.sv\n             obj_dir/single_port_ram\n             obj_dir/single_port_ram.v\n             obj_dir/single_port_ram.sv\n%Error: data/full_repos/permissive/49670587/vtr/ODIN_II/FULL_REGRESSION_TESTS/memory_controller.v:38: Cannot find file containing module: 'dual_port_ram'\n dual_port_ram dp_ram (\n ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module memory_controller
(
	clk,
	addr1,
	addr2,
	we1,
	we2,
	data1,
	data2,
	sp_out, 
	dp_out1,
	dp_out2
);

	input clk;

	input we1, we2; 

	input  [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] addr1,addr2; 

	input  [`MEMORY_CONTROLLER_DATA_SIZE-1:0] data1,data2;

	output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] sp_out,dp_out1,dp_out2;
	wire    [`MEMORY_CONTROLLER_DATA_SIZE-1:0] sp_out,dp_out1,dp_out2;

	single_port_ram sp_ram (		
		.addr (addr1),
		.data (data1),
		.we   (we1),	
		.clk  (clk),	
		.out  (sp_out)
	);

	dual_port_ram dp_ram (
                .addr1 (addr1),
		.addr2 (addr2),
                .data1 (data1),
		.data2 (data2),
        	.we1 (we1),
		.we2 (we2),
	        .clk (clk),
        	.out1 (dp_out1),
		.out2 (dp_out2)
        );

endmodule
module memory_controller
(
	clk,
	addr1,
	addr2,
	we1,
	we2,
	data1,
	data2,
	sp_out, 
	dp_out1,
	dp_out2
);


	input clk;

	input we1, we2; 

	input  [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] addr1,addr2; 

	input  [`MEMORY_CONTROLLER_DATA_SIZE-1:0] data1,data2;

	output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] sp_out,dp_out1,dp_out2;
	wire    [`MEMORY_CONTROLLER_DATA_SIZE-1:0] sp_out,dp_out1,dp_out2;

	single_port_ram sp_ram (		
		.addr (addr1),
		.data (data1),
		.we   (we1),	
		.clk  (clk),	
		.out  (sp_out)
	);

	dual_port_ram dp_ram (
                .addr1 (addr1),
		.addr2 (addr2),
                .data1 (data1),
		.data2 (data2),
        	.we1 (we1),
		.we2 (we2),
	        .clk (clk),
        	.out1 (dp_out1),
		.out2 (dp_out2)
        );

endmodule