data/full_repos/permissive/411838135/rv/uart/uart16550/tags/NewFormat/rtl/verilog-backup/uart_top.v
1: b'%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/NewFormat/rtl/verilog-backup/uart_top.v:80: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/411838135/rv/uart/uart16550/tags/NewFormat/rtl/verilog-backup,data/full_repos/permissive/411838135/timescale.v\n             data/full_repos/permissive/411838135/rv/uart/uart16550/tags/NewFormat/rtl/verilog-backup,data/full_repos/permissive/411838135/timescale.v.v\n             data/full_repos/permissive/411838135/rv/uart/uart16550/tags/NewFormat/rtl/verilog-backup,data/full_repos/permissive/411838135/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/NewFormat/rtl/verilog-backup/uart_top.v:81: Cannot find include file: uart_defines.v\n`include "uart_defines.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/NewFormat/rtl/verilog-backup/uart_top.v:100: Define or directive not defined: \'`UART_ADDR_WIDTH\'\nparameter         uart_addr_width = `UART_ADDR_WIDTH;\n                                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/NewFormat/rtl/verilog-backup/uart_top.v:100: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter         uart_addr_width = `UART_ADDR_WIDTH;\n                                                    ^\n%Error: Exiting due to 4 error(s)\n'
module uart_top	(
	clk, 
	

	wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o,	
	int_o,



	pad_stx_o, pad_srx_i,


	rts_o, cts_i, dtr_o, dsr_i, ri_i, dcd_i

	);

parameter 							 uart_data_width = 8;
parameter 							 uart_addr_width = `UART_ADDR_WIDTH;

input 								 clk;


input 								 wb_rst_i;
input [uart_addr_width-1:0] 	 wb_addr_i;
input [uart_data_width-1:0] 	 wb_dat_i;
output [uart_data_width-1:0] 	 wb_dat_o;
input 								 wb_we_i;
input 								 wb_stb_i;
input 								 wb_cyc_i;
output 								 wb_ack_o;
output 								 int_o;


input 								 pad_srx_i;
output 								 pad_stx_o;
output 								 rts_o;
input 								 cts_i;
output 								 dtr_o;
input 								 dsr_i;
input 								 ri_i;
input 								 dcd_i;

wire 									 pad_stx_o;
wire 									 rts_o;
wire 									 dtr_o;

wire [uart_addr_width-1:0] 	 wb_addr_i;
wire [uart_data_width-1:0] 	 wb_dat_i;
wire [uart_data_width-1:0] 	 wb_dat_o;

wire 									 we_o;






uart_wb		wb_interface(
		.clk(		clk		),
		.wb_rst_i(	wb_rst_i	),
		.wb_we_i(	wb_we_i		),
		.wb_stb_i(	wb_stb_i	),
		.wb_cyc_i(	wb_cyc_i	),
		.wb_ack_o(	wb_ack_o	),
		.we_o(		we_o		)
		);


uart_regs	regs(
		.clk(		clk		),
		.wb_rst_i(	wb_rst_i	),
		.wb_addr_i(	wb_addr_i	),
		.wb_dat_i(	wb_dat_i	),
		.wb_dat_o(	wb_dat_o	),
		.wb_we_i(	we_o		),
		.modem_inputs(	{cts_i, dsr_i,
				 ri_i,  dcd_i}	),
		.pad_stx_o(		pad_stx_o		),
		.pad_srx_i(		pad_srx_i		),
		.enable(	enable		),
		.rts_o(		rts_o		),
		.dtr_o(		dtr_o		),
		.int_o(		int_o		)
		);

endmodule
module uart_top	(
	clk, 
	

	wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o,	
	int_o,



	pad_stx_o, pad_srx_i,


	rts_o, cts_i, dtr_o, dsr_i, ri_i, dcd_i

	);


parameter 							 uart_data_width = 8;
parameter 							 uart_addr_width = `UART_ADDR_WIDTH;

input 								 clk;


input 								 wb_rst_i;
input [uart_addr_width-1:0] 	 wb_addr_i;
input [uart_data_width-1:0] 	 wb_dat_i;
output [uart_data_width-1:0] 	 wb_dat_o;
input 								 wb_we_i;
input 								 wb_stb_i;
input 								 wb_cyc_i;
output 								 wb_ack_o;
output 								 int_o;


input 								 pad_srx_i;
output 								 pad_stx_o;
output 								 rts_o;
input 								 cts_i;
output 								 dtr_o;
input 								 dsr_i;
input 								 ri_i;
input 								 dcd_i;

wire 									 pad_stx_o;
wire 									 rts_o;
wire 									 dtr_o;

wire [uart_addr_width-1:0] 	 wb_addr_i;
wire [uart_data_width-1:0] 	 wb_dat_i;
wire [uart_data_width-1:0] 	 wb_dat_o;

wire 									 we_o;






uart_wb		wb_interface(
		.clk(		clk		),
		.wb_rst_i(	wb_rst_i	),
		.wb_we_i(	wb_we_i		),
		.wb_stb_i(	wb_stb_i	),
		.wb_cyc_i(	wb_cyc_i	),
		.wb_ack_o(	wb_ack_o	),
		.we_o(		we_o		)
		);


uart_regs	regs(
		.clk(		clk		),
		.wb_rst_i(	wb_rst_i	),
		.wb_addr_i(	wb_addr_i	),
		.wb_dat_i(	wb_dat_i	),
		.wb_dat_o(	wb_dat_o	),
		.wb_we_i(	we_o		),
		.modem_inputs(	{cts_i, dsr_i,
				 ri_i,  dcd_i}	),
		.pad_stx_o(		pad_stx_o		),
		.pad_srx_i(		pad_srx_i		),
		.enable(	enable		),
		.rts_o(		rts_o		),
		.dtr_o(		dtr_o		),
		.int_o(		int_o		)
		);

endmodule