data/full_repos/permissive/451577625/system/clock_divider.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/451577625/system/clock_divider.v:39: Unsupported: Ignoring delay on this delayed statement.\n  forever #10 in = ~in;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-INFINITELOOP: data/full_repos/permissive/451577625/system/clock_divider.v:39: Infinite loop (condition always true)\n                                                                                     : ... In instance clock_divider_tb\n  forever #10 in = ~in;\n  ^~~~~~~\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module clock_divider_tb;
	
	reg in;
	wire out;
	
	clock_divider DUT(.in_clock (in),
		.out_clock (out));
		
	initial begin
		in = 0;
		forever #10 in = ~in;
	end

endmodule
module clock_divider_tb;

	
	reg in;
	wire out;
	
	clock_divider DUT(.in_clock (in),
		.out_clock (out));
		
	initial begin
		in = 0;
		forever #10 in = ~in;
	end

endmodule