data/full_repos/permissive/499137621/CheckPoint3_regfile-main/_2to4decoder.v
1: b"%Error: data/full_repos/permissive/499137621/CheckPoint3_regfile-main/_2to4decoder.v:18: Cannot find file containing module: 'AND_3'\n AND_3 AND0(out[0], not_ctrl_1, not_ctrl_0, Enable);\n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/499137621/CheckPoint3_regfile-main,data/full_repos/permissive/499137621/AND_3\n             data/full_repos/permissive/499137621/CheckPoint3_regfile-main,data/full_repos/permissive/499137621/AND_3.v\n             data/full_repos/permissive/499137621/CheckPoint3_regfile-main,data/full_repos/permissive/499137621/AND_3.sv\n             AND_3\n             AND_3.v\n             AND_3.sv\n             obj_dir/AND_3\n             obj_dir/AND_3.v\n             obj_dir/AND_3.sv\n%Error: data/full_repos/permissive/499137621/CheckPoint3_regfile-main/_2to4decoder.v:19: Cannot find file containing module: 'AND_3'\n AND_3 AND1(out[1], not_ctrl_1, ctrl[0], Enable); \n ^~~~~\n%Error: data/full_repos/permissive/499137621/CheckPoint3_regfile-main/_2to4decoder.v:20: Cannot find file containing module: 'AND_3'\n AND_3 AND2(out[2], ctrl[1], not_ctrl_0, Enable);  \n ^~~~~\n%Error: data/full_repos/permissive/499137621/CheckPoint3_regfile-main/_2to4decoder.v:21: Cannot find file containing module: 'AND_3'\n AND_3 AND3(out[3], ctrl[1], ctrl[0], Enable);   \n ^~~~~\n%Error: Exiting due to 4 error(s)\n"
module _2to4decoder(out, ctrl, Enable);

   input [1:0] ctrl;
	input Enable;
   output [3:0] out;

	
	wire not_ctrl_0;
	wire not_ctrl_1;

	not not_0(not_ctrl_0, ctrl[0]);	
	not not_1(not_ctrl_1, ctrl[1]);
	
	AND_3 AND0(out[0], not_ctrl_1, not_ctrl_0, Enable);
	AND_3 AND1(out[1], not_ctrl_1, ctrl[0], Enable);	
	AND_3 AND2(out[2], ctrl[1], not_ctrl_0, Enable);		
	AND_3 AND3(out[3], ctrl[1], ctrl[0], Enable);			
	

endmodule
module _2to4decoder(out, ctrl, Enable);


   input [1:0] ctrl;
	input Enable;
   output [3:0] out;

	
	wire not_ctrl_0;
	wire not_ctrl_1;

	not not_0(not_ctrl_0, ctrl[0]);	
	not not_1(not_ctrl_1, ctrl[1]);
	
	AND_3 AND0(out[0], not_ctrl_1, not_ctrl_0, Enable);
	AND_3 AND1(out[1], not_ctrl_1, ctrl[0], Enable);	
	AND_3 AND2(out[2], ctrl[1], not_ctrl_0, Enable);		
	AND_3 AND3(out[3], ctrl[1], ctrl[0], Enable);			
	

endmodule