data/full_repos/permissive/412284801/registers/register_nbit.v
data/verilator_xmls/18ebebfa-8944-4318-91a2-1ae7972e8547.xml
module register_nbit#(parameter n =8)(d,clk,clr,q);
    
    input [n-1:0]d;
    input clk,clr;
    output reg [n-1:0] q;

    always@( posedge clk ) begin
        if ( clr )
            q <= 0;
        else if (clk == 1)
            q <= d;
    end

endmodule
module register_nbit#(parameter n =8)(d,clk,clr,q);

    
    input [n-1:0]d;
    input clk,clr;
    output reg [n-1:0] q;

    always@( posedge clk ) begin
        if ( clr )
            q <= 0;
        else if (clk == 1)
            q <= d;
    end

endmodule