data/full_repos/permissive/412284801/T_ff/t_ff.v
data/verilator_xmls/674ac8b5-1ec6-461e-a249-f2555efb3cd3.xml
module t_ff(
    input clk,t,reset,
    output reg q,qbar);

always @(posedge clk or posedge reset) begin
    if(reset) begin
        q <= 1'b0;
        qbar <= 1'b1;
    end
    else if (t) begin
        q <= ~q;
        qbar <= ~qbar;
    end
end
endmodule
module t_ff(
    input clk,t,reset,
    output reg q,qbar);


always @(posedge clk or posedge reset) begin
    if(reset) begin
        q <= 1'b0;
        qbar <= 1'b1;
    end
    else if (t) begin
        q <= ~q;
        qbar <= ~qbar;
    end
end
endmodule