data/full_repos/permissive/419677538/Exercise_1/verilog_code/TestBenchFA.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/419677538/Exercise_1/verilog_code/TestBenchFA.v:10: Unsupported: Ignoring delay on this delayed statement.\n     #10 in = in + 1;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/419677538/Exercise_1/verilog_code/TestBenchFA.v:5: Cannot find file containing module: \'FAStruct\'\n   FAStruct fa0(in[2], in[1], in[0], S_struct, Cout_struct);\n   ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/419677538/Exercise_1/verilog_code,data/full_repos/permissive/419677538/FAStruct\n             data/full_repos/permissive/419677538/Exercise_1/verilog_code,data/full_repos/permissive/419677538/FAStruct.v\n             data/full_repos/permissive/419677538/Exercise_1/verilog_code,data/full_repos/permissive/419677538/FAStruct.sv\n             FAStruct\n             FAStruct.v\n             FAStruct.sv\n             obj_dir/FAStruct\n             obj_dir/FAStruct.v\n             obj_dir/FAStruct.sv\n%Error: data/full_repos/permissive/419677538/Exercise_1/verilog_code/TestBenchFA.v:6: Cannot find file containing module: \'FABehav\'\n   FABehav fa1(in[2], in[1], in[0], S_behav, Cout_behav);\n   ^~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TestBenchFA;
   reg [2:0] in;
   wire S_struct, Cout_struct;
   wire S_behav, Cout_behav;
   FAStruct fa0(in[2], in[1], in[0], S_struct, Cout_struct);
   FABehav fa1(in[2], in[1], in[0], S_behav, Cout_behav);
   initial
     in = 3'b000;
   always
     #10 in = in + 1;
endmodule
module TestBenchFA;

   reg [2:0] in;
   wire S_struct, Cout_struct;
   wire S_behav, Cout_behav;
   FAStruct fa0(in[2], in[1], in[0], S_struct, Cout_struct);
   FABehav fa1(in[2], in[1], in[0], S_behav, Cout_behav);
   initial
     in = 3'b000;
   always
     #10 in = in + 1;
endmodule