data/full_repos/permissive/506186384/project-files/lab6/Ctr_Hazard_Handler.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/506186384/project-files/lab6/Ctr_Hazard_Handler.v:50: Unsupported: Ignoring delay on this delayed statement.\n            #1;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Ctr_Hazard_Handler(
    input [31:0] Predict_Next_PC,
    input [31:0] Real_Next_PC,
    input [31:0] MEM_NextSeqPC,
    input D_Bubble,
    input MEM_Predict,
    input Clk,
    input reset,
    output Bubble,
    output [31:0] Correct_Next_PC,
    output [1:0] Two_Bit_Predictor
    );
    
    reg [31:0] History_Predict_PC[0:2];
    integer ptr,recover_cycle;
    reg bubble;
    reg [1:0] TwoBitPredictor;
    
    always @(negedge Clk)
     begin
        History_Predict_PC[ptr] = Predict_Next_PC;
        ptr = (ptr + 1) % 3;
        recover_cycle = (recover_cycle > 0)? recover_cycle - 1 : 0;
     end
    
    always @(Real_Next_PC)
        begin
            #1;
            if(Real_Next_PC != History_Predict_PC[ptr] && recover_cycle == 0) begin
                bubble = 1;
                recover_cycle = 4;
                if(MEM_Predict == 1) begin
                    if(Real_Next_PC == MEM_NextSeqPC) begin
                        case(TwoBitPredictor)
                            2'b11: TwoBitPredictor = 2'b10;
                            2'b10: TwoBitPredictor = 2'b01;
                            2'b01: TwoBitPredictor = 2'b00;
                            2'b00: TwoBitPredictor = 2'b00;
                        endcase
                    end
                    else begin
                        case(TwoBitPredictor)
                            2'b11: TwoBitPredictor = 2'b11;
                            2'b10: TwoBitPredictor = 2'b11;
                            2'b01: TwoBitPredictor = 2'b10;
                            2'b00: TwoBitPredictor = 2'b01;
                        endcase
                    end
                end
            end
            else begin
                bubble = 0;
                if(MEM_Predict == 1 && recover_cycle == 0) begin
                    if(Real_Next_PC == MEM_NextSeqPC) begin
                        case(TwoBitPredictor)
                            2'b11: TwoBitPredictor = 2'b10;
                            2'b10: TwoBitPredictor = 2'b01;
                            2'b01: TwoBitPredictor = 2'b00;
                            2'b00: TwoBitPredictor = 2'b00;
                        endcase
                    end
                    else begin
                        case(TwoBitPredictor)
                            2'b11: TwoBitPredictor = 2'b11;
                            2'b10: TwoBitPredictor = 2'b11;
                            2'b01: TwoBitPredictor = 2'b10;
                            2'b00: TwoBitPredictor = 2'b01;
                        endcase
                    end
                end
            end
        end
    
    always @(D_Bubble) begin
        if(D_Bubble == 1) recover_cycle = 2;
    end
    
    assign Bubble = bubble;
    assign Correct_Next_PC = Real_Next_PC;
    assign Two_Bit_Predictor = TwoBitPredictor;
    
    always @(posedge reset)
        begin
            History_Predict_PC[0] = 0;
            History_Predict_PC[1] = 0;
            History_Predict_PC[2] = 0;
            ptr = 0;
            recover_cycle = 4;
            TwoBitPredictor = 0;
        end
endmodule
module Ctr_Hazard_Handler(
    input [31:0] Predict_Next_PC,
    input [31:0] Real_Next_PC,
    input [31:0] MEM_NextSeqPC,
    input D_Bubble,
    input MEM_Predict,
    input Clk,
    input reset,
    output Bubble,
    output [31:0] Correct_Next_PC,
    output [1:0] Two_Bit_Predictor
    );

    
    reg [31:0] History_Predict_PC[0:2];
    integer ptr,recover_cycle;
    reg bubble;
    reg [1:0] TwoBitPredictor;
    
    always @(negedge Clk)
     begin
        History_Predict_PC[ptr] = Predict_Next_PC;
        ptr = (ptr + 1) % 3;
        recover_cycle = (recover_cycle > 0)? recover_cycle - 1 : 0;
     end
    
    always @(Real_Next_PC)
        begin
            #1;
            if(Real_Next_PC != History_Predict_PC[ptr] && recover_cycle == 0) begin
                bubble = 1;
                recover_cycle = 4;
                if(MEM_Predict == 1) begin
                    if(Real_Next_PC == MEM_NextSeqPC) begin
                        case(TwoBitPredictor)
                            2'b11: TwoBitPredictor = 2'b10;
                            2'b10: TwoBitPredictor = 2'b01;
                            2'b01: TwoBitPredictor = 2'b00;
                            2'b00: TwoBitPredictor = 2'b00;
                        endcase
                    end
                    else begin
                        case(TwoBitPredictor)
                            2'b11: TwoBitPredictor = 2'b11;
                            2'b10: TwoBitPredictor = 2'b11;
                            2'b01: TwoBitPredictor = 2'b10;
                            2'b00: TwoBitPredictor = 2'b01;
                        endcase
                    end
                end
            end
            else begin
                bubble = 0;
                if(MEM_Predict == 1 && recover_cycle == 0) begin
                    if(Real_Next_PC == MEM_NextSeqPC) begin
                        case(TwoBitPredictor)
                            2'b11: TwoBitPredictor = 2'b10;
                            2'b10: TwoBitPredictor = 2'b01;
                            2'b01: TwoBitPredictor = 2'b00;
                            2'b00: TwoBitPredictor = 2'b00;
                        endcase
                    end
                    else begin
                        case(TwoBitPredictor)
                            2'b11: TwoBitPredictor = 2'b11;
                            2'b10: TwoBitPredictor = 2'b11;
                            2'b01: TwoBitPredictor = 2'b10;
                            2'b00: TwoBitPredictor = 2'b01;
                        endcase
                    end
                end
            end
        end
    
    always @(D_Bubble) begin
        if(D_Bubble == 1) recover_cycle = 2;
    end
    
    assign Bubble = bubble;
    assign Correct_Next_PC = Real_Next_PC;
    assign Two_Bit_Predictor = TwoBitPredictor;
    
    always @(posedge reset)
        begin
            History_Predict_PC[0] = 0;
            History_Predict_PC[1] = 0;
            History_Predict_PC[2] = 0;
            ptr = 0;
            recover_cycle = 4;
            TwoBitPredictor = 0;
        end
endmodule