data/full_repos/permissive/458737381/src/verilog-parser/tests/std-2.6.2.v
1: b'%Warning-WIDTH: data/full_repos/permissive/458737381/src/verilog-parser/tests/std-2.6.2.v:6: Operator ASSIGN expects 112 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 136 bits.\n                                                                                           : ... In instance string_test\nstringvar = {stringvar,"!!!"};\n          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module string_test;
reg [8*14:1] stringvar;
initial begin
stringvar = "Hello world";
$display("%s is stored as %h", stringvar,stringvar);
stringvar = {stringvar,"!!!"};
$display("%s is stored as %h", stringvar,stringvar);
end
endmodule
module string_test;

reg [8*14:1] stringvar;
initial begin
stringvar = "Hello world";
$display("%s is stored as %h", stringvar,stringvar);
stringvar = {stringvar,"!!!"};
$display("%s is stored as %h", stringvar,stringvar);
end
endmodule