data/full_repos/permissive/420819839/Basics/Wire.v
data/verilator_xmls/8b4c7e8d-487a-484a-9b60-f30b59689a2b.xml
module top_module( input in, output out );

    assign out = in;
endmodule
module top_module( input in, output out );


    assign out = in;
endmodule