data/full_repos/permissive/489147019/Testcases/mempool/rtl/register_interface/src/reg_demux.sv
1: b'%Warning-LITENDIAN: data/full_repos/permissive/489147019/Testcases/mempool/rtl/register_interface/src/reg_demux.sv:26: Little bit endian vector: MSB < LSB of bit range: -1:0\n  output req_t [NoPorts-1:0] out_req_o,\n               ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/489147019/Testcases/mempool/rtl/register_interface/src/reg_demux.sv:27: Little bit endian vector: MSB < LSB of bit range: -1:0\n  input  rsp_t [NoPorts-1:0] out_rsp_i\n               ^\n%Error: Exiting due to 2 warning(s)\n'
module reg_demux #(
  parameter int unsigned NoPorts = 32'd0,
  parameter type req_t = logic,
  parameter type rsp_t = logic,

  parameter int unsigned SelectWidth    = (NoPorts > 32'd1) ? $clog2(NoPorts) : 32'd1,
  parameter type         select_t       = logic [SelectWidth-1:0]
) (
  input  logic               clk_i,
  input  logic               rst_ni,
  input  select_t            in_select_i,
  input  req_t               in_req_i,
  output rsp_t               in_rsp_o,
  output req_t [NoPorts-1:0] out_req_o,
  input  rsp_t [NoPorts-1:0] out_rsp_i
);

  always_comb begin
    out_req_o = '0;
    in_rsp_o = '0;
    out_req_o[in_select_i] = in_req_i;
    in_rsp_o = out_rsp_i[in_select_i];
  end

endmodule
module reg_demux #(
  parameter int unsigned NoPorts = 32'd0,
  parameter type req_t = logic,
  parameter type rsp_t = logic,

  parameter int unsigned SelectWidth    = (NoPorts > 32'd1) ? $clog2(NoPorts) : 32'd1,
  parameter type         select_t       = logic [SelectWidth-1:0]
) (
  input  logic               clk_i,
  input  logic               rst_ni,
  input  select_t            in_select_i,
  input  req_t               in_req_i,
  output rsp_t               in_rsp_o,
  output req_t [NoPorts-1:0] out_req_o,
  input  rsp_t [NoPorts-1:0] out_rsp_i
);


  always_comb begin
    out_req_o = '0;
    in_rsp_o = '0;
    out_req_o[in_select_i] = in_req_i;
    in_rsp_o = out_rsp_i[in_select_i];
  end

endmodule