data/full_repos/permissive/406635962/src/rtl/exu_commit.v
1: b'%Error: data/full_repos/permissive/406635962/src/rtl/exu_commit.v:6: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_commit.v:13: Define or directive not defined: \'`XLEN\'\n    input [`XLEN-1:0] alu_cmt_i_imm,\n           ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_commit.v:17: Define or directive not defined: \'`PC_SIZE\'\n    input [`PC_SIZE-1:0] alu_cmt_i_pc,\n           ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_commit.v:24: Define or directive not defined: \'`PC_SIZE\'\n    output [`PC_SIZE-1:0] pipe_flush_add_op1,\n            ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_commit.v:25: Define or directive not defined: \'`PC_SIZE\'\n    output [`PC_SIZE-1:0] pipe_flush_add_op2\n            ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_commit.v:29: Define or directive not defined: \'`PC_SIZE\'\n    wire [`PC_SIZE-1:0] alu_brchmis_add_op1;\n          ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_commit.v:30: Define or directive not defined: \'`PC_SIZE\'\n    wire [`PC_SIZE-1:0] alu_brchmis_add_op2;\n          ^~~~~~~~\n%Error: Exiting due to 7 error(s)\n'
module exu_commit (
    output nonflush_cmt_ena,

    input alu_cmt_i_valid,
    output alu_cmt_i_ready,
    input [`XLEN-1:0] alu_cmt_i_imm,
    input alu_cmt_i_bjp,
    input alu_cmt_i_bjp_prdt,
    input alu_cmt_i_bjp_rslv,
    input [`PC_SIZE-1:0] alu_cmt_i_pc,
    input alu_cmt_i_ilegl,

    output flush_pulse,

    input pipe_flush_ack,
    output pipe_flush_req,
    output [`PC_SIZE-1:0] pipe_flush_add_op1,
    output [`PC_SIZE-1:0] pipe_flush_add_op2
);

    wire alu_brchmis_flush_ack = pipe_flush_ack;
    wire [`PC_SIZE-1:0] alu_brchmis_add_op1;
    wire [`PC_SIZE-1:0] alu_brchmis_add_op2;
    assign pipe_flush_add_op1 = alu_brchmis_add_op1;
    assign pipe_flush_add_op2 = alu_brchmis_add_op2;

    exu_branchslv u_exu_branchslv (
        .cmt_i_valid(alu_cmt_i_valid),
        .cmt_i_ready(alu_cmt_i_ready),
        .cmt_i_bjp(alu_cmt_i_bjp),
        .cmt_i_bjp_prdt(alu_cmt_i_bjp_prdt),
        .cmt_i_bjp_rslv(alu_cmt_i_bjp_rslv),
        .cmt_i_pc(alu_cmt_i_pc),
        .cmt_i_imm(alu_cmt_i_imm),
        .brchmis_flush_ack(alu_brchmis_flush_ack),
        .brchmis_flush_req(pipe_flush_req),
        .brchmis_flush_add_op1(alu_brchmis_add_op1),
        .brchmis_flush_add_op2(alu_brchmis_add_op2)
    );
    
    assign flush_pulse = pipe_flush_ack & pipe_flush_req;
    wire cmt_ena = alu_cmt_i_valid & alu_cmt_i_ready;
    assign nonflush_cmt_ena = (~pipe_flush_req) & cmt_ena;
endmodule
module exu_commit (
    output nonflush_cmt_ena,

    input alu_cmt_i_valid,
    output alu_cmt_i_ready,
    input [`XLEN-1:0] alu_cmt_i_imm,
    input alu_cmt_i_bjp,
    input alu_cmt_i_bjp_prdt,
    input alu_cmt_i_bjp_rslv,
    input [`PC_SIZE-1:0] alu_cmt_i_pc,
    input alu_cmt_i_ilegl,

    output flush_pulse,

    input pipe_flush_ack,
    output pipe_flush_req,
    output [`PC_SIZE-1:0] pipe_flush_add_op1,
    output [`PC_SIZE-1:0] pipe_flush_add_op2
);


    wire alu_brchmis_flush_ack = pipe_flush_ack;
    wire [`PC_SIZE-1:0] alu_brchmis_add_op1;
    wire [`PC_SIZE-1:0] alu_brchmis_add_op2;
    assign pipe_flush_add_op1 = alu_brchmis_add_op1;
    assign pipe_flush_add_op2 = alu_brchmis_add_op2;

    exu_branchslv u_exu_branchslv (
        .cmt_i_valid(alu_cmt_i_valid),
        .cmt_i_ready(alu_cmt_i_ready),
        .cmt_i_bjp(alu_cmt_i_bjp),
        .cmt_i_bjp_prdt(alu_cmt_i_bjp_prdt),
        .cmt_i_bjp_rslv(alu_cmt_i_bjp_rslv),
        .cmt_i_pc(alu_cmt_i_pc),
        .cmt_i_imm(alu_cmt_i_imm),
        .brchmis_flush_ack(alu_brchmis_flush_ack),
        .brchmis_flush_req(pipe_flush_req),
        .brchmis_flush_add_op1(alu_brchmis_add_op1),
        .brchmis_flush_add_op2(alu_brchmis_add_op2)
    );
    
    assign flush_pulse = pipe_flush_ack & pipe_flush_req;
    wire cmt_ena = alu_cmt_i_valid & alu_cmt_i_ready;
    assign nonflush_cmt_ena = (~pipe_flush_req) & cmt_ena;
endmodule