data/full_repos/permissive/511241767/barrel_shifter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/511241767/barrel_shifter.v:352: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 7 bits.\n                                                                         : ... In instance barrel_shifter.cl\n    assign a2 = {a[4],a[3],a[2],a[0],a[7],a[6],a[5]};\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module log_left(a,s,y);

    input [7:0] a;
    input [2:0] s;
    output [7:0] y;

    wire [7:0] p1,p2,a2,b1,b2;

    assign a2 = {a[4],a[3],a[2],a[0],{4{1'b0}}};

    genvar i;

    generate
        for(i=0;i<8;i=i+1) begin: logleft3

            mux21 ll3 (a[i],a2[i],s[2],p1[i]);

        end
    endgenerate




    assign p2 = {p1[5],p1[4],p1[3],p1[2],p1[1],p1[0],{2{1'b0}}};


    genvar j;

    generate
        for(j=0;j<8;j=j+1) begin: logleft2

            mux21 ll2 (p1[j],p2[j],s[1],b1[j]);

        end
    endgenerate





    assign b2 = {b1[6],b1[5],b1[4],b1[3],b1[2],b1[1],b1[0],1'b0};

    genvar k;

    generate
        for(k=0;k<8;k=k+1) begin: logleft1

            mux21 ll1 (b1[k],b2[k],s[0],y[k]);

        end
    endgenerate

endmodule
module log_left(a,s,y);


    input [7:0] a;
    input [2:0] s;
    output [7:0] y;

    wire [7:0] p1,p2,a2,b1,b2;

    assign a2 = {a[4],a[3],a[2],a[0],{4{1'b0}}};

    genvar i;

    generate
        for(i=0;i<8;i=i+1) begin: logleft3

            mux21 ll3 (a[i],a2[i],s[2],p1[i]);

        end
    endgenerate




    assign p2 = {p1[5],p1[4],p1[3],p1[2],p1[1],p1[0],{2{1'b0}}};


    genvar j;

    generate
        for(j=0;j<8;j=j+1) begin: logleft2

            mux21 ll2 (p1[j],p2[j],s[1],b1[j]);

        end
    endgenerate





    assign b2 = {b1[6],b1[5],b1[4],b1[3],b1[2],b1[1],b1[0],1'b0};

    genvar k;

    generate
        for(k=0;k<8;k=k+1) begin: logleft1

            mux21 ll1 (b1[k],b2[k],s[0],y[k]);

        end
    endgenerate

endmodule