data/full_repos/permissive/455210247/RTL/router_fifo.v
1: b'%Warning-WIDTH: data/full_repos/permissive/455210247/RTL/router_fifo.v:27: Bit extraction of array[15:0] requires 4 bit index, not 5 bits.\n                                                                         : ... In instance router_fifo\n          {fifo[w_ptr[3:0]][8],fifo[w_ptr][7:0]} <={lfd_state,data_in};   \n                                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/455210247/RTL/router_fifo.v:39: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 9 bits.\n                                                                         : ... In instance router_fifo\n         data_out <= fifo[r_ptr[3:0]];\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/455210247/RTL/router_fifo.v:70: Bit extraction of array[15:0] requires 4 bit index, not 5 bits.\n                                                                         : ... In instance router_fifo\nelse if(fifo[r_ptr][8] && r_en && !empty)\n            ^\n%Error: Exiting due to 3 warning(s)\n'
module router_fifo(clk,resetn,soft_reset,w_en,r_en,lfd_state,data_in,full,empty,data_out);

input clk,resetn,soft_reset,w_en,r_en,lfd_state;
output  full,empty;
input[7:0] data_in;
output reg [7:0] data_out;
reg [8:0] fifo[15:0];
reg[4:0] w_ptr,r_ptr;
reg [5:0] counter;
integer i;


always@(posedge clk)
begin
    if(!resetn)
        begin
      for(i=0;i<16;i=i+1)
        fifo[i] <=0;
         end
   else if(soft_reset)
         begin
       for(i=0;i<16;i=i+1)
        fifo[i] <=0;
         end
   else
         if(w_en && !full)
          {fifo[w_ptr[3:0]][8],fifo[w_ptr][7:0]} <={lfd_state,data_in};   
           
 end


always@(posedge clk)
begin
     if(!resetn)
       data_out <=0;
 else if(soft_reset)
        data_out <=8'dz;
  else if(r_en && !empty)
         data_out <= fifo[r_ptr[3:0]];
   else if(counter==0 && data_out !=0)
           data_out <=8'dz;
       
end


always@(posedge clk)
begin
    if(!resetn || soft_reset)
          begin
          w_ptr <=0;
          r_ptr <=0;
        end
    else
        begin
         if(w_en && !full)
           w_ptr <= w_ptr+1;
         if(r_en && !empty)
            r_ptr <=r_ptr+1;
        end
end



always@(posedge clk)
begin
   if(!resetn) 
      counter <=0;
     else if(soft_reset)
      counter <=0;
else if(fifo[r_ptr][8] && r_en && !empty)
      counter <= fifo[r_ptr[3:0]][7:2]+1;
else if(counter !=0 && r_en && !empty)
        counter <=counter-1;
 end





assign full=((r_ptr[4] != w_ptr[4])&&(w_ptr[3:0]==r_ptr[3:0]))?1'b1:1'b0;
assign empty=(r_ptr==w_ptr);
  
endmodule
module router_fifo(clk,resetn,soft_reset,w_en,r_en,lfd_state,data_in,full,empty,data_out);


input clk,resetn,soft_reset,w_en,r_en,lfd_state;
output  full,empty;
input[7:0] data_in;
output reg [7:0] data_out;
reg [8:0] fifo[15:0];
reg[4:0] w_ptr,r_ptr;
reg [5:0] counter;
integer i;


always@(posedge clk)
begin
    if(!resetn)
        begin
      for(i=0;i<16;i=i+1)
        fifo[i] <=0;
         end
   else if(soft_reset)
         begin
       for(i=0;i<16;i=i+1)
        fifo[i] <=0;
         end
   else
         if(w_en && !full)
          {fifo[w_ptr[3:0]][8],fifo[w_ptr][7:0]} <={lfd_state,data_in};   
           
 end


always@(posedge clk)
begin
     if(!resetn)
       data_out <=0;
 else if(soft_reset)
        data_out <=8'dz;
  else if(r_en && !empty)
         data_out <= fifo[r_ptr[3:0]];
   else if(counter==0 && data_out !=0)
           data_out <=8'dz;
       
end


always@(posedge clk)
begin
    if(!resetn || soft_reset)
          begin
          w_ptr <=0;
          r_ptr <=0;
        end
    else
        begin
         if(w_en && !full)
           w_ptr <= w_ptr+1;
         if(r_en && !empty)
            r_ptr <=r_ptr+1;
        end
end



always@(posedge clk)
begin
   if(!resetn) 
      counter <=0;
     else if(soft_reset)
      counter <=0;
else if(fifo[r_ptr][8] && r_en && !empty)
      counter <= fifo[r_ptr[3:0]][7:2]+1;
else if(counter !=0 && r_en && !empty)
        counter <=counter-1;
 end





assign full=((r_ptr[4] != w_ptr[4])&&(w_ptr[3:0]==r_ptr[3:0]))?1'b1:1'b0;
assign empty=(r_ptr==w_ptr);
  
endmodule