data/full_repos/permissive/424376038/src/NES_Nexys4.v
1: b'%Error: data/full_repos/permissive/424376038/src/NES_Nexys4.v:160: Duplicate declaration of signal: \'cycle\'\n                                                                 : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n  wire [8:0] cycle;\n             ^~~~~\n        data/full_repos/permissive/424376038/src/NES_Nexys4.v:138: ... Location of original declaration\n       output [8:0] cycle,\n                    ^~~~~\n%Error: data/full_repos/permissive/424376038/src/NES_Nexys4.v:161: Duplicate declaration of signal: \'scanline\'\n  wire [8:0] scanline;\n             ^~~~~~~~\n        data/full_repos/permissive/424376038/src/NES_Nexys4.v:139: ... Location of original declaration\n       output [8:0] scanline,\n                    ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/424376038/src/NES_Nexys4.v:224: Signal definition not found, creating implicitly: \'loader_write\'\n                                                                            : ... Suggested alternative: \'loader_done\'\n                          memory_write && run_mem || loader_write,\n                                                     ^~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module MemoryController(
                 input clk,
                 input read_a,
                 input read_b,
                 input write,
                 input [23:0] addr,
                 input [7:0] din,
                 output reg [7:0] dout_a,
                 output reg [7:0] dout_b,
                 output reg busy,

                 output reg MemOE,
                 output reg MemWR,
                 output reg RamCS,
                 output reg [23:0] MemAdr,
                 input [7:0] MemDB_in,
					  output [7:0] MemDB_out );
                 
    reg [7:0] data_to_write;
  assign MemDB_out = data_to_write;
  reg [1:0] cycles;
  reg r_read_a;
  
  always @(posedge clk) begin

    if (!busy) begin
      if (read_a || read_b || write) begin
        MemAdr <= addr[23:0];
        RamCS <= 0;
        MemWR <= !(write != 0);
        MemOE <= !(write == 0);
        busy <= 1;
        data_to_write <= din;
        cycles <= 0;
        r_read_a <= read_a;
      end else begin
        MemOE <= 1;
        MemWR <= 1;
        RamCS <= 1;
        busy <= 0;
        cycles <= 0;
      end
    end else begin
      if (cycles == 2) begin

        if (!MemOE) begin
          if (r_read_a) dout_a <= MemDB_in;
          else dout_b <= MemDB_in;
        end
        MemOE <= 1;
        MemWR <= 1;
        RamCS <= 1;
        busy <= 0;
        cycles <= 0;
      end else begin
        cycles <= cycles + 1;
      end
    end
  end
endmodule
module MemoryController(
                 input clk,
                 input read_a,
                 input read_b,
                 input write,
                 input [23:0] addr,
                 input [7:0] din,
                 output reg [7:0] dout_a,
                 output reg [7:0] dout_b,
                 output reg busy,

                 output reg MemOE,
                 output reg MemWR,
                 output reg RamCS,
                 output reg [23:0] MemAdr,
                 input [7:0] MemDB_in,
					  output [7:0] MemDB_out );

                 
    reg [7:0] data_to_write;
  assign MemDB_out = data_to_write;
  reg [1:0] cycles;
  reg r_read_a;
  
  always @(posedge clk) begin

    if (!busy) begin
      if (read_a || read_b || write) begin
        MemAdr <= addr[23:0];
        RamCS <= 0;
        MemWR <= !(write != 0);
        MemOE <= !(write == 0);
        busy <= 1;
        data_to_write <= din;
        cycles <= 0;
        r_read_a <= read_a;
      end else begin
        MemOE <= 1;
        MemWR <= 1;
        RamCS <= 1;
        busy <= 0;
        cycles <= 0;
      end
    end else begin
      if (cycles == 2) begin

        if (!MemOE) begin
          if (r_read_a) dout_a <= MemDB_in;
          else dout_b <= MemDB_in;
        end
        MemOE <= 1;
        MemWR <= 1;
        RamCS <= 1;
        busy <= 0;
        cycles <= 0;
      end else begin
        cycles <= cycles + 1;
      end
    end
  end
endmodule