data/full_repos/permissive/468066752/tb/CPU_tb.sv
1: b'%Error: data/full_repos/permissive/468066752/tb/CPU_tb.sv:9: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("cpu_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/468066752/tb/CPU_tb.sv:10: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, CPU_tb);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/468066752/tb/CPU_tb.sv:13: syntax error, unexpected \'@\'\n    @(negedge CLK)\n    ^\n%Error: data/full_repos/permissive/468066752/tb/CPU_tb.sv:15: syntax error, unexpected \'@\'\n    repeat(10) @(negedge CLK);\n               ^\n%Error: data/full_repos/permissive/468066752/tb/CPU_tb.sv:17: syntax error, unexpected \'@\'\n    repeat(100) @(negedge CLK);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/468066752/tb/CPU_tb.sv:21: Unsupported: Ignoring delay on this delayed statement.\n    #5 CLK = ~CLK;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 5 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module CPU_tb;

  `timescale 1ps/1ps;
  logic CLK, RESET;

  CPU dut (.ACLK(CLK), .ARESETN(RESET));

  initial begin
    $dumpfile("cpu_tb.vcd");
    $dumpvars(0, CPU_tb);
    RESET = 1'b1;
    CLK = 1'b0;
    @(negedge CLK)
    RESET = 1'b0;
    repeat(10) @(negedge CLK);
    RESET = 1'b1;
    repeat(100) @(negedge CLK);
    $stop;
  end
  always_comb begin
    #5 CLK = ~CLK;
  end

endmodule
module CPU_tb;


  `timescale 1ps/1ps;
  logic CLK, RESET;

  CPU dut (.ACLK(CLK), .ARESETN(RESET));

  initial begin
    $dumpfile("cpu_tb.vcd");
    $dumpvars(0, CPU_tb);
    RESET = 1'b1;
    CLK = 1'b0;
    @(negedge CLK)
    RESET = 1'b0;
    repeat(10) @(negedge CLK);
    RESET = 1'b1;
    repeat(100) @(negedge CLK);
    $stop;
  end
  always_comb begin
    #5 CLK = ~CLK;
  end

endmodule