data/full_repos/permissive/42803760/ftl/Dynamic_Controller/code/SynchronizeClkDomains.v
1: b'%Error: data/full_repos/permissive/42803760/ftl/Dynamic_Controller/code/SynchronizeClkDomains.v:32: Cannot find include file: Dynamic_Controller_Parameters.vh\n`include"Dynamic_Controller_Parameters.vh"  \n        ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/42803760/ftl/Dynamic_Controller/code,data/full_repos/permissive/42803760/Dynamic_Controller_Parameters.vh\n             data/full_repos/permissive/42803760/ftl/Dynamic_Controller/code,data/full_repos/permissive/42803760/Dynamic_Controller_Parameters.vh.v\n             data/full_repos/permissive/42803760/ftl/Dynamic_Controller/code,data/full_repos/permissive/42803760/Dynamic_Controller_Parameters.vh.sv\n             Dynamic_Controller_Parameters.vh\n             Dynamic_Controller_Parameters.vh.v\n             Dynamic_Controller_Parameters.vh.sv\n             obj_dir/Dynamic_Controller_Parameters.vh\n             obj_dir/Dynamic_Controller_Parameters.vh.v\n             obj_dir/Dynamic_Controller_Parameters.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module SynchronizeClkDomains(
  clk_200M,clk_83M,rst_n,

  controller_rb_l,controller_rb_l_o,  read_data_stall  ,read_data_stall_o,

  Target_Addr,  page_offset_addr,  Operation_en,Operation_Type,  
  Target_Addr_o,page_offset_addr_o,Operation_en_o,Operation_Type_o
    );
	 
`include"Dynamic_Controller_Parameters.vh"	
 

input clk_200M;
input clk_83M;
input rst_n;


input controller_rb_l;
input read_data_stall;
output reg controller_rb_l_o;
output reg read_data_stall_o;

input [2:0] Target_Addr;
input [ADDR_WIDTH-4:0] page_offset_addr;
input Operation_en;
input [2:0] Operation_Type;
output reg [2:0] Target_Addr_o;
output reg [ADDR_WIDTH-4:0] page_offset_addr_o;
output reg Operation_en_o;
output reg [2:0] Operation_Type_o;




  reg  controller_rb_l_sync;
  reg  read_data_stall_sync;

always@(posedge clk_200M or negedge rst_n)
begin
 if(!rst_n)
   begin
     controller_rb_l_sync<=1'b0;  
	 read_data_stall_sync<=1'b0;
     controller_rb_l_o<=1'b0;
	 read_data_stall_o<=1'b0;
	end
 else
 begin
     controller_rb_l_sync<=controller_rb_l;
     controller_rb_l_o<=controller_rb_l_sync;
	 read_data_stall_sync<=read_data_stall;
	 read_data_stall_o<=read_data_stall_sync;
 end
end



reg [2:0] Target_Addr_sync;
reg [ADDR_WIDTH-4:0] page_offset_addr_sync;
reg Operation_en_sync;
reg [2:0] Operation_Type_sync;


always@(posedge clk_83M or negedge rst_n)
begin
 if(!rst_n)
   begin
     Target_Addr_sync<=3'b0;
     page_offset_addr_sync<='b0;
	 
     Operation_Type_sync<=3'b0;
	  Operation_en_sync<=1'b0;
	 Target_Addr_o<=3'b0;
     page_offset_addr_o<='b0;	
	 Operation_en_o<=1'b0;
	 Operation_Type_o<=3'b0;
	end
 else
 begin
     Target_Addr_sync<=Target_Addr;
     page_offset_addr_sync<=page_offset_addr;
	 Operation_en_sync<=Operation_en;
     Operation_Type_sync<=Operation_Type;
	  
     Target_Addr_o<=Target_Addr_sync;
     page_offset_addr_o<=page_offset_addr_sync;
	 Operation_en_o<=Operation_en_sync;
     Operation_Type_o<=Operation_Type_sync;
 end
end
endmodule
module SynchronizeClkDomains(
  clk_200M,clk_83M,rst_n,

  controller_rb_l,controller_rb_l_o,  read_data_stall  ,read_data_stall_o,

  Target_Addr,  page_offset_addr,  Operation_en,Operation_Type,  
  Target_Addr_o,page_offset_addr_o,Operation_en_o,Operation_Type_o
    );

	 
`include"Dynamic_Controller_Parameters.vh"	
 

input clk_200M;
input clk_83M;
input rst_n;


input controller_rb_l;
input read_data_stall;
output reg controller_rb_l_o;
output reg read_data_stall_o;

input [2:0] Target_Addr;
input [ADDR_WIDTH-4:0] page_offset_addr;
input Operation_en;
input [2:0] Operation_Type;
output reg [2:0] Target_Addr_o;
output reg [ADDR_WIDTH-4:0] page_offset_addr_o;
output reg Operation_en_o;
output reg [2:0] Operation_Type_o;




  reg  controller_rb_l_sync;
  reg  read_data_stall_sync;

always@(posedge clk_200M or negedge rst_n)
begin
 if(!rst_n)
   begin
     controller_rb_l_sync<=1'b0;  
	 read_data_stall_sync<=1'b0;
     controller_rb_l_o<=1'b0;
	 read_data_stall_o<=1'b0;
	end
 else
 begin
     controller_rb_l_sync<=controller_rb_l;
     controller_rb_l_o<=controller_rb_l_sync;
	 read_data_stall_sync<=read_data_stall;
	 read_data_stall_o<=read_data_stall_sync;
 end
end



reg [2:0] Target_Addr_sync;
reg [ADDR_WIDTH-4:0] page_offset_addr_sync;
reg Operation_en_sync;
reg [2:0] Operation_Type_sync;


always@(posedge clk_83M or negedge rst_n)
begin
 if(!rst_n)
   begin
     Target_Addr_sync<=3'b0;
     page_offset_addr_sync<='b0;
	 
     Operation_Type_sync<=3'b0;
	  Operation_en_sync<=1'b0;
	 Target_Addr_o<=3'b0;
     page_offset_addr_o<='b0;	
	 Operation_en_o<=1'b0;
	 Operation_Type_o<=3'b0;
	end
 else
 begin
     Target_Addr_sync<=Target_Addr;
     page_offset_addr_sync<=page_offset_addr;
	 Operation_en_sync<=Operation_en;
     Operation_Type_sync<=Operation_Type;
	  
     Target_Addr_o<=Target_Addr_sync;
     page_offset_addr_o<=page_offset_addr_sync;
	 Operation_en_o<=Operation_en_sync;
     Operation_Type_o<=Operation_Type_sync;
 end
end
endmodule