data/full_repos/permissive/437157208/src/Sign_Extend.v
data/verilator_xmls/c2bfc880-dcaa-4719-90fd-6662ac32283b.xml
module Sign_Extend
(
	input [15:0] Sign_Ext_i,
	output wire [31:0] Sign_Ext_o
);


assign	Sign_Ext_o = { {16{Sign_Ext_i[15]}}, Sign_Ext_i};
endmodule
module Sign_Extend
(
	input [15:0] Sign_Ext_i,
	output wire [31:0] Sign_Ext_o
);



assign	Sign_Ext_o = { {16{Sign_Ext_i[15]}}, Sign_Ext_i};
endmodule