data/full_repos/permissive/482974522/TimeMultiplexed_FIR.srcs/sources_1/new/3IN_MUX.v
data/verilator_xmls/e5b1653a-ff18-4f41-847d-6e326c27d13c.xml
module MUX3IN #(parameter WI = 2, WF = 6)(
    input CLK,
    input [1:0] sel,
    input [(WI+WF)-1:0] in0,in1,in2, 
    output reg [(WI+WF)-1:0] out
    );
    
    always@(sel,in0,in1,in2)begin
        if(sel == 2'b00)begin
            out <= in0;
        end
    
        else if(sel == 2'b01)begin
            out <= in1;
        end

        else if(sel == 2'b10)begin
            out <= in2;
        end
    end
endmodule
module MUX3IN #(parameter WI = 2, WF = 6)(
    input CLK,
    input [1:0] sel,
    input [(WI+WF)-1:0] in0,in1,in2, 
    output reg [(WI+WF)-1:0] out
    );

    
    always@(sel,in0,in1,in2)begin
        if(sel == 2'b00)begin
            out <= in0;
        end
    
        else if(sel == 2'b01)begin
            out <= in1;
        end

        else if(sel == 2'b10)begin
            out <= in2;
        end
    end
endmodule