data/full_repos/permissive/481307378/source_files/ALU/alu.v
data/verilator_xmls/a11f8b91-2354-4ce4-a048-ddb51865084c.xml
module alu (
input [ 4 : 0 ] S ,
input [ 31 : 0 ] A,
input [ 31 : 0 ] B,
output reg CMP,
output reg [ 31 : 0 ] Q
);

	always @( S , A, B)

		begin

			Q=32'd0 ; CMP = 0;



			casez ( S )

				`SUB: Q = $signed(A) - $signed(B);
				`ADD: Q = $signed(A) + $signed(B);
                `MUL: Q = $signed(A) * $signed(B);

				`AND: Q = A & B;
				`OR: Q = A | B;
				`XOR: Q = A ^ B; 

				`SLL: Q = A << B;
				`SRA: Q = $signed(A) >>> $signed(B);
				`SRL: Q = A >> B;

				`SLT: begin Q = ($signed(A) < $signed(B)) ? 32'd1 : 32'd0; 
							 CMP = ($signed(A) < $signed(B)) ? 1 : 0;
							 end 

				`SLTU: begin Q = (A < B) ? 32'd1 : 32'd0; 
				              CMP = (A < B) ? 1 : 0;
				              end

				`BEQ: CMP = (A == B) ? 1 : 0;
				`BNE: CMP = (A != B) ? 1 : 0;
				`BLT: CMP = ($signed(A) < $signed(B)) ? 1 : 0;
				`BGE: CMP = ($signed(A) >= $signed(B)) ? 1 : 0;
				`BLTU: CMP = (A < B) ? 1 : 0;
				`BGEU: CMP = (A >= B) ? 1 : 0;


				`SLLI: Q = A << B[4 : 0];
				`SRAI: Q = $signed(A) >>> $signed(B[4 : 0]);
				`SRLI: Q = A >> B[4 : 0];

				`AUIPC: begin Q = A + B;
                              CMP = 1;
				            end

				`LUI: Q = A + B;	
						  		  

			endcase

		end


endmodule
module alu (
input [ 4 : 0 ] S ,
input [ 31 : 0 ] A,
input [ 31 : 0 ] B,
output reg CMP,
output reg [ 31 : 0 ] Q
);


	always @( S , A, B)

		begin

			Q=32'd0 ; CMP = 0;



			casez ( S )

				`SUB: Q = $signed(A) - $signed(B);
				`ADD: Q = $signed(A) + $signed(B);
                `MUL: Q = $signed(A) * $signed(B);

				`AND: Q = A & B;
				`OR: Q = A | B;
				`XOR: Q = A ^ B; 

				`SLL: Q = A << B;
				`SRA: Q = $signed(A) >>> $signed(B);
				`SRL: Q = A >> B;

				`SLT: begin Q = ($signed(A) < $signed(B)) ? 32'd1 : 32'd0; 
							 CMP = ($signed(A) < $signed(B)) ? 1 : 0;
							 end 

				`SLTU: begin Q = (A < B) ? 32'd1 : 32'd0; 
				              CMP = (A < B) ? 1 : 0;
				              end

				`BEQ: CMP = (A == B) ? 1 : 0;
				`BNE: CMP = (A != B) ? 1 : 0;
				`BLT: CMP = ($signed(A) < $signed(B)) ? 1 : 0;
				`BGE: CMP = ($signed(A) >= $signed(B)) ? 1 : 0;
				`BLTU: CMP = (A < B) ? 1 : 0;
				`BGEU: CMP = (A >= B) ? 1 : 0;


				`SLLI: Q = A << B[4 : 0];
				`SRAI: Q = $signed(A) >>> $signed(B[4 : 0]);
				`SRLI: Q = A >> B[4 : 0];

				`AUIPC: begin Q = A + B;
                              CMP = 1;
				            end

				`LUI: Q = A + B;	
						  		  

			endcase

		end


endmodule