data/full_repos/permissive/468612001/Week09/FIR_filter_pipeline/tb_FIR_Filter.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/468612001/Week09/FIR_filter_pipeline/tb_FIR_Filter.v:16: Unsupported: Ignoring delay on this delayed statement.\n always #5 CLK = ~CLK;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week09/FIR_filter_pipeline/tb_FIR_Filter.v:19: Unsupported: Ignoring delay on this delayed statement.\n   #5;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week09/FIR_filter_pipeline/tb_FIR_Filter.v:21: Unsupported: Ignoring delay on this delayed statement.\n   #15;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week09/FIR_filter_pipeline/tb_FIR_Filter.v:22: Unsupported: Ignoring delay on this delayed statement.\n   Xin = -3; #10;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week09/FIR_filter_pipeline/tb_FIR_Filter.v:23: Unsupported: Ignoring delay on this delayed statement.\n   Xin =  1; #10;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week09/FIR_filter_pipeline/tb_FIR_Filter.v:24: Unsupported: Ignoring delay on this delayed statement.\n   Xin =  0; #10;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week09/FIR_filter_pipeline/tb_FIR_Filter.v:25: Unsupported: Ignoring delay on this delayed statement.\n   Xin = -2; #10;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week09/FIR_filter_pipeline/tb_FIR_Filter.v:26: Unsupported: Ignoring delay on this delayed statement.\n   Xin = -1; #10;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week09/FIR_filter_pipeline/tb_FIR_Filter.v:27: Unsupported: Ignoring delay on this delayed statement.\n   Xin =  4; #10;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week09/FIR_filter_pipeline/tb_FIR_Filter.v:28: Unsupported: Ignoring delay on this delayed statement.\n   Xin = -5; #10;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week09/FIR_filter_pipeline/tb_FIR_Filter.v:29: Unsupported: Ignoring delay on this delayed statement.\n   Xin =  6; #10;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week09/FIR_filter_pipeline/tb_FIR_Filter.v:30: Unsupported: Ignoring delay on this delayed statement.\n   Xin =  0; #10;\n             ^\n%Error: data/full_repos/permissive/468612001/Week09/FIR_filter_pipeline/tb_FIR_Filter.v:11: Cannot find file containing module: \'FIR_Filter_pipe\'\n FIR_Filter_pipe f1(.clock(CLK), .reset(RST), .data_in(Xin), .data_out(Yout));\n ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/468612001/Week09/FIR_filter_pipeline,data/full_repos/permissive/468612001/FIR_Filter_pipe\n             data/full_repos/permissive/468612001/Week09/FIR_filter_pipeline,data/full_repos/permissive/468612001/FIR_Filter_pipe.v\n             data/full_repos/permissive/468612001/Week09/FIR_filter_pipeline,data/full_repos/permissive/468612001/FIR_Filter_pipe.sv\n             FIR_Filter_pipe\n             FIR_Filter_pipe.v\n             FIR_Filter_pipe.sv\n             obj_dir/FIR_Filter_pipe\n             obj_dir/FIR_Filter_pipe.v\n             obj_dir/FIR_Filter_pipe.sv\n%Error: Exiting due to 1 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_FIR_Filter();
	
	reg CLK;
	reg RST;
	reg [11:0] Xin;
	
	wire [11:0] Yout;
	
	FIR_Filter_pipe f1(.clock(CLK), .reset(RST), .data_in(Xin), .data_out(Yout));
	
	initial CLK = 0;
	initial RST = 0;
	
	always #5 CLK = ~CLK;
		initial begin
			Xin = 0;
			#5;
			RST = !RST;
			#15;
			Xin = -3; #10;
			Xin =  1; #10;
			Xin =  0; #10;
			Xin = -2; #10;
			Xin = -1; #10;
			Xin =  4; #10;
			Xin = -5; #10;
			Xin =  6; #10;
			Xin =  0; #10;
		end
endmodule
module tb_FIR_Filter();

	
	reg CLK;
	reg RST;
	reg [11:0] Xin;
	
	wire [11:0] Yout;
	
	FIR_Filter_pipe f1(.clock(CLK), .reset(RST), .data_in(Xin), .data_out(Yout));
	
	initial CLK = 0;
	initial RST = 0;
	
	always #5 CLK = ~CLK;
		initial begin
			Xin = 0;
			#5;
			RST = !RST;
			#15;
			Xin = -3; #10;
			Xin =  1; #10;
			Xin =  0; #10;
			Xin = -2; #10;
			Xin = -1; #10;
			Xin =  4; #10;
			Xin = -5; #10;
			Xin =  6; #10;
			Xin =  0; #10;
		end
endmodule