data/full_repos/permissive/488093047/Verilog Codes/TB_HalfAdder.v
1: b'%Error: Cannot find file containing module: Codes,data/full_repos/permissive/488093047\n        ... Looked in:\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.v\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.sv\n             Codes,data/full_repos/permissive/488093047\n             Codes,data/full_repos/permissive/488093047.v\n             Codes,data/full_repos/permissive/488093047.sv\n             obj_dir/Codes,data/full_repos/permissive/488093047\n             obj_dir/Codes,data/full_repos/permissive/488093047.v\n             obj_dir/Codes,data/full_repos/permissive/488093047.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/488093047/Verilog\n%Error: Cannot find file containing module: Codes/TB_HalfAdder.v\n%Error: Exiting due to 3 error(s)\n'
module TB_HalfAdder();
reg A,B;
wire Sum,Cout;
HalfAdder DUT1(.A(A),.B(B),.Sum(Sum),.Cout(Cout));
initial begin
A=1'b0;B=1'b0;
#10 A=1'b0;B=1'b1;
#10 A=1'b1;B=1'b0;
#10 A=1'b1;B=1'b1;

end

endmodule
module TB_HalfAdder();

reg A,B;
wire Sum,Cout;
HalfAdder DUT1(.A(A),.B(B),.Sum(Sum),.Cout(Cout));
initial begin
A=1'b0;B=1'b0;
#10 A=1'b0;B=1'b1;
#10 A=1'b1;B=1'b0;
#10 A=1'b1;B=1'b1;

end

endmodule