data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v
1: b'%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:51: Cannot find include file: ../opl3.vh\n`include "../opl3.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/452215364/rtl/opl3/operator,data/full_repos/permissive/452215364/../opl3.vh\n             data/full_repos/permissive/452215364/rtl/opl3/operator,data/full_repos/permissive/452215364/../opl3.vh.v\n             data/full_repos/permissive/452215364/rtl/opl3/operator,data/full_repos/permissive/452215364/../opl3.vh.sv\n             ../opl3.vh\n             ../opl3.vh.v\n             ../opl3.vh.sv\n             obj_dir/../opl3.vh\n             obj_dir/../opl3.vh.v\n             obj_dir/../opl3.vh.sv\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:57: Define or directive not defined: \'`BANK_NUM_WIDTH\'\n    input wire [`BANK_NUM_WIDTH-1:0] bank_num,\n                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:58: Define or directive not defined: \'`OP_NUM_WIDTH\'\n    input wire [`OP_NUM_WIDTH-1:0] op_num,              \n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:59: Define or directive not defined: \'`REG_FNUM_WIDTH\'\n    input wire [`REG_FNUM_WIDTH-1:0] fnum,\n                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:60: Define or directive not defined: \'`REG_MULT_WIDTH\'\n    input wire [`REG_MULT_WIDTH-1:0] mult,\n                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:61: Define or directive not defined: \'`REG_BLOCK_WIDTH\'\n    input wire [`REG_BLOCK_WIDTH-1:0] block,\n                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:62: Define or directive not defined: \'`REG_WS_WIDTH\'\n    input wire [`REG_WS_WIDTH-1:0] ws,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:65: Define or directive not defined: \'`NUM_OPERATORS_PER_BANK\'\n    input wire [`NUM_OPERATORS_PER_BANK-1:0] kon_bank0,  \n                ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:66: Define or directive not defined: \'`NUM_OPERATORS_PER_BANK\'\n    input wire [`NUM_OPERATORS_PER_BANK-1:0] kon_bank1,  \n                ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:67: Define or directive not defined: \'`REG_ENV_WIDTH\'\n    input wire [`REG_ENV_WIDTH-1:0] ar,  \n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:68: Define or directive not defined: \'`REG_ENV_WIDTH\'\n    input wire [`REG_ENV_WIDTH-1:0] dr,  \n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:69: Define or directive not defined: \'`REG_ENV_WIDTH\'\n    input wire [`REG_ENV_WIDTH-1:0] sl,  \n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:70: Define or directive not defined: \'`REG_ENV_WIDTH\'\n    input wire [`REG_ENV_WIDTH-1:0] rr,  \n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:71: Define or directive not defined: \'`REG_TL_WIDTH\'\n    input wire [`REG_TL_WIDTH-1:0] tl,   \n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:73: Define or directive not defined: \'`REG_KSL_WIDTH\'\n    input wire [`REG_KSL_WIDTH-1:0] ksl,  \n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:84: Define or directive not defined: \'`REG_FB_WIDTH\'\n    input wire [`REG_FB_WIDTH-1:0] fb,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:85: Define or directive not defined: \'`OP_OUT_WIDTH\'\n    input wire [`OP_OUT_WIDTH-1:0] modulation,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:88: Define or directive not defined: \'`OP_OUT_WIDTH\'\n    output wire signed [`OP_OUT_WIDTH-1:0] out\n                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:90: Define or directive not defined: \'`NUM_OPERATORS_PER_BANK\'\n    wire [`NUM_OPERATORS_PER_BANK-1:0] kon [`NUM_BANKS-1:0];  \n          ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:90: Define or directive not defined: \'`NUM_BANKS\'\n    wire [`NUM_OPERATORS_PER_BANK-1:0] kon [`NUM_BANKS-1:0];  \n                                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:91: Define or directive not defined: \'`PHASE_ACC_WIDTH\'\n    wire [`PHASE_ACC_WIDTH-1:0] phase_inc;\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:93: Define or directive not defined: \'`NUM_BANKS\'\n    wire key_on_pulse_array [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];\n                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:93: Define or directive not defined: \'`NUM_OPERATORS_PER_BANK\'\n    wire key_on_pulse_array [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];\n                                             ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:95: Define or directive not defined: \'`NUM_BANKS\'\n    wire key_off_pulse_array [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];\n                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:95: Define or directive not defined: \'`NUM_OPERATORS_PER_BANK\'\n    wire key_off_pulse_array [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];\n                                              ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:96: Define or directive not defined: \'`ENV_WIDTH\'\n    wire [`ENV_WIDTH-1:0] env;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:97: Define or directive not defined: \'`OP_OUT_WIDTH\'\n    reg signed [`OP_OUT_WIDTH-1:0] feedback1 [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:97: Define or directive not defined: \'`NUM_BANKS\'\n    reg signed [`OP_OUT_WIDTH-1:0] feedback1 [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];\n                                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:97: Define or directive not defined: \'`NUM_OPERATORS_PER_BANK\'\n    reg signed [`OP_OUT_WIDTH-1:0] feedback1 [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];\n                                                              ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:98: Define or directive not defined: \'`OP_OUT_WIDTH\'\n    reg signed [`OP_OUT_WIDTH-1:0] feedback2 [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:98: Define or directive not defined: \'`NUM_BANKS\'\n    reg signed [`OP_OUT_WIDTH-1:0] feedback2 [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];\n                                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:98: Define or directive not defined: \'`NUM_OPERATORS_PER_BANK\'\n    reg signed [`OP_OUT_WIDTH-1:0] feedback2 [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];\n                                                              ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:99: Define or directive not defined: \'`OP_OUT_WIDTH\'\n    wire signed [`OP_OUT_WIDTH-1:0] feedback_result;\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:100: Define or directive not defined: \'`OP_OUT_WIDTH\'\n    reg signed [`OP_OUT_WIDTH+1+2**`REG_FB_WIDTH-1:0] feedback_result_p0;\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:100: Define or directive not defined: \'`REG_FB_WIDTH\'\n    reg signed [`OP_OUT_WIDTH+1+2**`REG_FB_WIDTH-1:0] feedback_result_p0;\n                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:113: Define or directive not defined: \'`NUM_BANKS\'\n        for (i = 0; i < `NUM_BANKS; i = i + 1) begin: detecti\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:113: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        for (i = 0; i < `NUM_BANKS; i = i + 1) begin: detecti\n                                  ^\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:114: Define or directive not defined: \'`NUM_OPERATORS_PER_BANK\'\n            for (j = 0; j < `NUM_OPERATORS_PER_BANK; j = j + 1) begin: detectj\n                            ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:132: Define or directive not defined: \'`OP_NORMAL\'\n                    .clk_en(i == bank_num && j == op_num && sample_clk_en && op_type == `OP_NORMAL),\n                                                                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:132: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n                    .clk_en(i == bank_num && j == op_num && sample_clk_en && op_type == `OP_NORMAL),\n                                                                                                  ^\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:145: Define or directive not defined: \'`OP_BASS_DRUM\'\n        .clk_en(op_type == `OP_BASS_DRUM && sample_clk_en),\n                           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:154: Define or directive not defined: \'`OP_SNARE_DRUM\'\n        .clk_en(op_type == `OP_SNARE_DRUM && sample_clk_en),\n                           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:154: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n        .clk_en(op_type == `OP_SNARE_DRUM && sample_clk_en),\n                                          ^~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:163: Define or directive not defined: \'`OP_TOM_TOM\'\n        .clk_en(op_type == `OP_TOM_TOM && sample_clk_en),\n                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:163: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n        .clk_en(op_type == `OP_TOM_TOM && sample_clk_en),\n                                       ^~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:172: Define or directive not defined: \'`OP_TOP_CYMBAL\'\n        .clk_en(op_type == `OP_TOP_CYMBAL && sample_clk_en),\n                           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:172: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n        .clk_en(op_type == `OP_TOP_CYMBAL && sample_clk_en),\n                                          ^~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:181: Define or directive not defined: \'`OP_HI_HAT\'\n        .clk_en(op_type == `OP_HI_HAT && sample_clk_en),\n                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:181: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n        .clk_en(op_type == `OP_HI_HAT && sample_clk_en),\n                                      ^~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/operator.v:188: Define or directive not defined: \'`OP_BASS_DRUM\'\n     (op_type == `OP_BASS_DRUM && bd_on_pulse) ||\n                 ^~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module operator (
    input wire clk,
    input wire sample_clk_en,
    input wire is_new,    
    input wire [`BANK_NUM_WIDTH-1:0] bank_num,
    input wire [`OP_NUM_WIDTH-1:0] op_num,              
    input wire [`REG_FNUM_WIDTH-1:0] fnum,
    input wire [`REG_MULT_WIDTH-1:0] mult,
    input wire [`REG_BLOCK_WIDTH-1:0] block,
    input wire [`REG_WS_WIDTH-1:0] ws,
    input wire vib,
    input wire dvb,
    input wire [`NUM_OPERATORS_PER_BANK-1:0] kon_bank0,  
    input wire [`NUM_OPERATORS_PER_BANK-1:0] kon_bank1,  
    input wire [`REG_ENV_WIDTH-1:0] ar,
    input wire [`REG_ENV_WIDTH-1:0] dr,
    input wire [`REG_ENV_WIDTH-1:0] sl,
    input wire [`REG_ENV_WIDTH-1:0] rr,
    input wire [`REG_TL_WIDTH-1:0] tl,
    input wire ksr,
    input wire [`REG_KSL_WIDTH-1:0] ksl,
    input wire egt,
    input wire am,
    input wire dam,
    input wire nts,
    input wire bd,
    input wire sd,
    input wire tom,
    input wire tc,
    input wire hh,        
    input wire use_feedback,
    input wire [`REG_FB_WIDTH-1:0] fb,
    input wire [`OP_OUT_WIDTH-1:0] modulation,
    input wire latch_feedback_pulse,
    input wire [2:0] op_type,
    output wire signed [`OP_OUT_WIDTH-1:0] out
);
    wire [`NUM_OPERATORS_PER_BANK-1:0] kon [`NUM_BANKS-1:0];  
    wire [`PHASE_ACC_WIDTH-1:0] phase_inc;
    wire key_on_pulse;
    wire key_on_pulse_array [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];
    wire key_off_pulse;
    wire key_off_pulse_array [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];
    wire [`ENV_WIDTH-1:0] env;
    reg signed [`OP_OUT_WIDTH-1:0] feedback1 [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];
    reg signed [`OP_OUT_WIDTH-1:0] feedback2 [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];
    wire signed [`OP_OUT_WIDTH-1:0] feedback_result;
    reg signed [`OP_OUT_WIDTH+1+2**`REG_FB_WIDTH-1:0] feedback_result_p0;
    wire bd_on_pulse;
    wire sd_on_pulse;
    wire tom_on_pulse;
    wire tc_on_pulse;
    wire hh_on_pulse;
    wire rhythm_kon_pulse;

    assign kon[0] = kon_bank0;
    assign kon[1] = kon_bank1;

    genvar i, j;
    generate
        for (i = 0; i < `NUM_BANKS; i = i + 1) begin: detecti
            for (j = 0; j < `NUM_OPERATORS_PER_BANK; j = j + 1) begin: detectj

                edge_detector #(
                    .EDGE_LEVEL(1), 
                    .CLK_DLY(1)
                ) key_on_edge_detect (
                    .clk_en(i == bank_num && j == op_num && sample_clk_en),
                    .in(kon[i][j]), 
                    .edge_detected(key_on_pulse_array[i][j]),
                    .clk(clk)
                );
                
                edge_detector #(
                    .EDGE_LEVEL(0), 
                    .CLK_DLY(1)
                ) key_off_edge_detect (
                    .clk_en(i == bank_num && j == op_num && sample_clk_en && op_type == `OP_NORMAL),
                    .in(kon[i][j]), 
                    .edge_detected(key_off_pulse_array[i][j]),
                    .clk(clk)
                );                                   
            end
        end
    endgenerate  
    
    edge_detector #(
        .EDGE_LEVEL(1), 
        .CLK_DLY(1)
    ) bd_edge_detect (
        .clk_en(op_type == `OP_BASS_DRUM && sample_clk_en),
        .in(bd), 
        .edge_detected(bd_on_pulse),
        .clk(clk)
    );
    edge_detector #(
        .EDGE_LEVEL(1), 
        .CLK_DLY(1)
    ) sd_edge_detect (
        .clk_en(op_type == `OP_SNARE_DRUM && sample_clk_en),
        .in(sd), 
        .edge_detected(sd_on_pulse),
        .clk(clk)
    );
    edge_detector #(
        .EDGE_LEVEL(1), 
        .CLK_DLY(1)
    ) tom_edge_detect (
        .clk_en(op_type == `OP_TOM_TOM && sample_clk_en),
        .in(tom), 
        .edge_detected(tom_on_pulse),
        .clk(clk)
    );       
    edge_detector #(
        .EDGE_LEVEL(1), 
        .CLK_DLY(1)
    ) tc_edge_detect (
        .clk_en(op_type == `OP_TOP_CYMBAL && sample_clk_en),
        .in(tc), 
        .edge_detected(tc_on_pulse),
        .clk(clk)
    );
    edge_detector #(
        .EDGE_LEVEL(1), 
        .CLK_DLY(1)
    ) hh_edge_detect (
        .clk_en(op_type == `OP_HI_HAT && sample_clk_en),
        .in(hh), 
        .edge_detected(hh_on_pulse),
        .clk(clk)
    ); 
    
    assign rhythm_kon_pulse =
     (op_type == `OP_BASS_DRUM && bd_on_pulse) ||
     (op_type == `OP_SNARE_DRUM && sd_on_pulse) ||
     (op_type == `OP_TOM_TOM && tom_on_pulse) ||
     (op_type == `OP_TOP_CYMBAL && tc_on_pulse) ||
     (op_type == `OP_HI_HAT && hh_on_pulse);
    
    assign key_on_pulse = key_on_pulse_array[bank_num][op_num] || rhythm_kon_pulse;
    assign key_off_pulse = key_off_pulse_array[bank_num][op_num];
    

    always @(posedge clk)
        if (latch_feedback_pulse) begin
            feedback1[bank_num][op_num] <= out;
            feedback2[bank_num][op_num] <= feedback1[bank_num][op_num];
        end
    
    always @ *
        if (fb == 0)
            feedback_result_p0 = 0;
        else
            feedback_result_p0 = ((feedback1[bank_num][op_num] +
             feedback2[bank_num][op_num]) <<< fb);
        
    assign feedback_result = feedback_result_p0 >>> 9;
    
    calc_phase_inc calc_phase_inc (
        .clk(clk),
        .sample_clk_en(sample_clk_en),
        .fnum(fnum),
        .mult(mult),
        .block(block),
        .vib(vib),
        .dvb(dvb),
        .phase_inc(phase_inc)
    ); 
    
    envelope_generator envelope_generator (
        .clk(clk),
        .sample_clk_en(sample_clk_en),
        .bank_num(bank_num),
        .op_num(op_num),
        .ar(ar),
        .dr(dr),
        .sl(sl),
        .rr(rr),
        .tl(tl),
        .ksr(ksr),
        .ksl(ksl),
        .egt(egt),
        .am(am),
        .dam(dam),
        .nts(nts),
        .fnum(fnum),
        .block(block),
        .key_on_pulse(key_on_pulse),
        .key_off_pulse(key_off_pulse),
        .env(env)
    );


    phase_generator phase_generator (
        .clk(clk),
        .sample_clk_en(sample_clk_en),
        .is_new(is_new),
        .bank_num(bank_num),
        .op_num(op_num),
        .phase_inc(phase_inc),
        .ws(ws),
        .env(env),
        .key_on_pulse(key_on_pulse),
        .modulation(use_feedback ? feedback_result : modulation),
        .op_type(op_type),
        .out(out)
    );
endmodule
module operator (
    input wire clk,
    input wire sample_clk_en,
    input wire is_new,    
    input wire [`BANK_NUM_WIDTH-1:0] bank_num,
    input wire [`OP_NUM_WIDTH-1:0] op_num,              
    input wire [`REG_FNUM_WIDTH-1:0] fnum,
    input wire [`REG_MULT_WIDTH-1:0] mult,
    input wire [`REG_BLOCK_WIDTH-1:0] block,
    input wire [`REG_WS_WIDTH-1:0] ws,
    input wire vib,
    input wire dvb,
    input wire [`NUM_OPERATORS_PER_BANK-1:0] kon_bank0,  
    input wire [`NUM_OPERATORS_PER_BANK-1:0] kon_bank1,  
    input wire [`REG_ENV_WIDTH-1:0] ar,
    input wire [`REG_ENV_WIDTH-1:0] dr,
    input wire [`REG_ENV_WIDTH-1:0] sl,
    input wire [`REG_ENV_WIDTH-1:0] rr,
    input wire [`REG_TL_WIDTH-1:0] tl,
    input wire ksr,
    input wire [`REG_KSL_WIDTH-1:0] ksl,
    input wire egt,
    input wire am,
    input wire dam,
    input wire nts,
    input wire bd,
    input wire sd,
    input wire tom,
    input wire tc,
    input wire hh,        
    input wire use_feedback,
    input wire [`REG_FB_WIDTH-1:0] fb,
    input wire [`OP_OUT_WIDTH-1:0] modulation,
    input wire latch_feedback_pulse,
    input wire [2:0] op_type,
    output wire signed [`OP_OUT_WIDTH-1:0] out
);

    wire [`NUM_OPERATORS_PER_BANK-1:0] kon [`NUM_BANKS-1:0];  
    wire [`PHASE_ACC_WIDTH-1:0] phase_inc;
    wire key_on_pulse;
    wire key_on_pulse_array [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];
    wire key_off_pulse;
    wire key_off_pulse_array [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];
    wire [`ENV_WIDTH-1:0] env;
    reg signed [`OP_OUT_WIDTH-1:0] feedback1 [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];
    reg signed [`OP_OUT_WIDTH-1:0] feedback2 [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];
    wire signed [`OP_OUT_WIDTH-1:0] feedback_result;
    reg signed [`OP_OUT_WIDTH+1+2**`REG_FB_WIDTH-1:0] feedback_result_p0;
    wire bd_on_pulse;
    wire sd_on_pulse;
    wire tom_on_pulse;
    wire tc_on_pulse;
    wire hh_on_pulse;
    wire rhythm_kon_pulse;

    assign kon[0] = kon_bank0;
    assign kon[1] = kon_bank1;

    genvar i, j;
    generate
        for (i = 0; i < `NUM_BANKS; i = i + 1) begin: detecti
            for (j = 0; j < `NUM_OPERATORS_PER_BANK; j = j + 1) begin: detectj

                edge_detector #(
                    .EDGE_LEVEL(1), 
                    .CLK_DLY(1)
                ) key_on_edge_detect (
                    .clk_en(i == bank_num && j == op_num && sample_clk_en),
                    .in(kon[i][j]), 
                    .edge_detected(key_on_pulse_array[i][j]),
                    .clk(clk)
                );
                
                edge_detector #(
                    .EDGE_LEVEL(0), 
                    .CLK_DLY(1)
                ) key_off_edge_detect (
                    .clk_en(i == bank_num && j == op_num && sample_clk_en && op_type == `OP_NORMAL),
                    .in(kon[i][j]), 
                    .edge_detected(key_off_pulse_array[i][j]),
                    .clk(clk)
                );                                   
            end
        end
    endgenerate  
    
    edge_detector #(
        .EDGE_LEVEL(1), 
        .CLK_DLY(1)
    ) bd_edge_detect (
        .clk_en(op_type == `OP_BASS_DRUM && sample_clk_en),
        .in(bd), 
        .edge_detected(bd_on_pulse),
        .clk(clk)
    );
    edge_detector #(
        .EDGE_LEVEL(1), 
        .CLK_DLY(1)
    ) sd_edge_detect (
        .clk_en(op_type == `OP_SNARE_DRUM && sample_clk_en),
        .in(sd), 
        .edge_detected(sd_on_pulse),
        .clk(clk)
    );
    edge_detector #(
        .EDGE_LEVEL(1), 
        .CLK_DLY(1)
    ) tom_edge_detect (
        .clk_en(op_type == `OP_TOM_TOM && sample_clk_en),
        .in(tom), 
        .edge_detected(tom_on_pulse),
        .clk(clk)
    );       
    edge_detector #(
        .EDGE_LEVEL(1), 
        .CLK_DLY(1)
    ) tc_edge_detect (
        .clk_en(op_type == `OP_TOP_CYMBAL && sample_clk_en),
        .in(tc), 
        .edge_detected(tc_on_pulse),
        .clk(clk)
    );
    edge_detector #(
        .EDGE_LEVEL(1), 
        .CLK_DLY(1)
    ) hh_edge_detect (
        .clk_en(op_type == `OP_HI_HAT && sample_clk_en),
        .in(hh), 
        .edge_detected(hh_on_pulse),
        .clk(clk)
    ); 
    
    assign rhythm_kon_pulse =
     (op_type == `OP_BASS_DRUM && bd_on_pulse) ||
     (op_type == `OP_SNARE_DRUM && sd_on_pulse) ||
     (op_type == `OP_TOM_TOM && tom_on_pulse) ||
     (op_type == `OP_TOP_CYMBAL && tc_on_pulse) ||
     (op_type == `OP_HI_HAT && hh_on_pulse);
    
    assign key_on_pulse = key_on_pulse_array[bank_num][op_num] || rhythm_kon_pulse;
    assign key_off_pulse = key_off_pulse_array[bank_num][op_num];
    

    always @(posedge clk)
        if (latch_feedback_pulse) begin
            feedback1[bank_num][op_num] <= out;
            feedback2[bank_num][op_num] <= feedback1[bank_num][op_num];
        end
    
    always @ *
        if (fb == 0)
            feedback_result_p0 = 0;
        else
            feedback_result_p0 = ((feedback1[bank_num][op_num] +
             feedback2[bank_num][op_num]) <<< fb);
        
    assign feedback_result = feedback_result_p0 >>> 9;
    
    calc_phase_inc calc_phase_inc (
        .clk(clk),
        .sample_clk_en(sample_clk_en),
        .fnum(fnum),
        .mult(mult),
        .block(block),
        .vib(vib),
        .dvb(dvb),
        .phase_inc(phase_inc)
    ); 
    
    envelope_generator envelope_generator (
        .clk(clk),
        .sample_clk_en(sample_clk_en),
        .bank_num(bank_num),
        .op_num(op_num),
        .ar(ar),
        .dr(dr),
        .sl(sl),
        .rr(rr),
        .tl(tl),
        .ksr(ksr),
        .ksl(ksl),
        .egt(egt),
        .am(am),
        .dam(dam),
        .nts(nts),
        .fnum(fnum),
        .block(block),
        .key_on_pulse(key_on_pulse),
        .key_off_pulse(key_off_pulse),
        .env(env)
    );


    phase_generator phase_generator (
        .clk(clk),
        .sample_clk_en(sample_clk_en),
        .is_new(is_new),
        .bank_num(bank_num),
        .op_num(op_num),
        .phase_inc(phase_inc),
        .ws(ws),
        .env(env),
        .key_on_pulse(key_on_pulse),
        .modulation(use_feedback ? feedback_result : modulation),
        .op_type(op_type),
        .out(out)
    );
endmodule