data/full_repos/permissive/490203627/verilog/dv/ann_dbg_mem/ann_dbg_mem_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/490203627/verilog/dv/ann_dbg_mem/ann_dbg_mem_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n    always #50 clock <= (clock === 1\'b0);\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/490203627/verilog/dv/ann_dbg_mem/ann_dbg_mem_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n    always #3 io_clk <= (io_clk === 1\'b0);\n           ^\n%Error: data/full_repos/permissive/490203627/verilog/dv/ann_dbg_mem/ann_dbg_mem_tb.v:110: Unsupported or unknown PLI call: $timeformat\n        $timeformat(-9, 2, "ns", 20);\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/490203627/verilog/dv/ann_dbg_mem/ann_dbg_mem_tb.v:111: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("ann_dbg_mem.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/490203627/verilog/dv/ann_dbg_mem/ann_dbg_mem_tb.v:112: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, ann_dbg_mem_tb);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/490203627/verilog/dv/ann_dbg_mem/ann_dbg_mem_tb.v:128: Unsupported: wait statements\n        wait(wbs_cfg_done);\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/490203627/verilog/dv/ann_dbg_mem/ann_dbg_mem_tb.v:132: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/490203627/verilog/dv/ann_dbg_mem/ann_dbg_mem_tb.v:134: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n%Error: data/full_repos/permissive/490203627/verilog/dv/ann_dbg_mem/ann_dbg_mem_tb.v:139: syntax error, unexpected \'@\'\n        @(negedge io_clk) load_kdtree = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/490203627/verilog/dv/ann_dbg_mem/ann_dbg_mem_tb.v:136: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n%Error: data/full_repos/permissive/490203627/verilog/dv/ann_dbg_mem/ann_dbg_mem_tb.v:142: syntax error, unexpected \'@\'\n        @(negedge io_clk) load_kdtree = 1\'b0;\n        ^\n%Error: data/full_repos/permissive/490203627/verilog/dv/ann_dbg_mem/ann_dbg_mem_tb.v:148: syntax error, unexpected \'@\'\n            @(negedge io_clk)\n            ^\n%Error: data/full_repos/permissive/490203627/verilog/dv/ann_dbg_mem/ann_dbg_mem_tb.v:156: syntax error, unexpected \'@\'\n        @(negedge io_clk)\n        ^\n%Error: data/full_repos/permissive/490203627/verilog/dv/ann_dbg_mem/ann_dbg_mem_tb.v:165: syntax error, unexpected \'@\'\n            @(negedge io_clk)\n            ^\n%Error: data/full_repos/permissive/490203627/verilog/dv/ann_dbg_mem/ann_dbg_mem_tb.v:169: syntax error, unexpected \'@\'\n        @(negedge io_clk)\n        ^\n%Error: data/full_repos/permissive/490203627/verilog/dv/ann_dbg_mem/ann_dbg_mem_tb.v:180: syntax error, unexpected \'@\'\n            @(negedge io_clk)\n            ^\n%Error: data/full_repos/permissive/490203627/verilog/dv/ann_dbg_mem/ann_dbg_mem_tb.v:187: syntax error, unexpected \'@\'\n        @(negedge io_clk)\n        ^\n%Error: data/full_repos/permissive/490203627/verilog/dv/ann_dbg_mem/ann_dbg_mem_tb.v:202: syntax error, unexpected \'@\'\n            repeat (1000) @(posedge clock);\n                          ^\n%Error: data/full_repos/permissive/490203627/verilog/dv/ann_dbg_mem/ann_dbg_mem_tb.v:212: Unsupported: wait statements\n        wait(wbs_done == 1);\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/490203627/verilog/dv/ann_dbg_mem/ann_dbg_mem_tb.v:233: Unsupported: Ignoring delay on this delayed statement.\n        #2000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/490203627/verilog/dv/ann_dbg_mem/ann_dbg_mem_tb.v:235: Unsupported: Ignoring delay on this delayed statement.\n        #100000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/490203627/verilog/dv/ann_dbg_mem/ann_dbg_mem_tb.v:242: Unsupported: Ignoring delay on this delayed statement.\n        #200;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/490203627/verilog/dv/ann_dbg_mem/ann_dbg_mem_tb.v:244: Unsupported: Ignoring delay on this delayed statement.\n        #200;\n        ^\n%Error: Exiting due to 14 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ann_dbg_mem_tb;
    parameter DATA_WIDTH = 11;
    parameter LEAF_SIZE = 8;
    parameter PATCH_SIZE = 5;
    parameter ROW_SIZE = 32;
    parameter COL_SIZE = 16;
    parameter NUM_QUERYS = ROW_SIZE * COL_SIZE;
    parameter NUM_LEAVES = 64;
    parameter NUM_NODES = NUM_LEAVES - 1;
    parameter BLOCKING = 4;
    parameter ADDR_WIDTH = $clog2(NUM_LEAVES);

    reg clock;
    reg RSTB;
    reg CSB;
    reg power1, power2;
    reg power3, power4;

    wire gpio;
    wire [37:0] mprj_io;

    reg                                 io_clk;
    reg                                 io_rst_n;
    reg                                 fsm_start;
    wire                                fsm_done;
    reg                                 send_best_arr;
    wire                                send_done;
    reg                                 load_kdtree;
    wire                                load_done;
    reg                                 in_fifo_wenq;
    reg [10:0]                          in_fifo_wdata;
    wire                                in_fifo_wfull_n;
    reg                                 out_fifo_deq;
    wire [10:0]                         out_fifo_rdata;
    wire                                out_fifo_rempty_n;
    wire                                wbs_done;
    wire                                wbs_busy;
    wire                                wbs_cfg_done;


    assign mprj_io[0] = io_clk;
    assign mprj_io[1] = io_rst_n;
    assign mprj_io[2] = in_fifo_wenq;
    assign mprj_io[13:3] = in_fifo_wdata;
    assign in_fifo_wfull_n = mprj_io[14];
    assign mprj_io[15] = fsm_start;
    assign mprj_io[16] = send_best_arr;
    assign mprj_io[17] = load_kdtree;
    assign load_done = mprj_io[18];
    assign fsm_done = mprj_io[19];
    assign send_done = mprj_io[20];
    assign wbs_done = mprj_io[21];
    assign wbs_busy = mprj_io[22];
    assign wbs_cfg_done = mprj_io[23];
    assign mprj_io[25] = out_fifo_deq;
    assign out_fifo_rdata = mprj_io[36:26];
    assign out_fifo_rempty_n = mprj_io[37];





    always #50 clock <= (clock === 1'b0);
    always #3 io_clk <= (io_clk === 1'b0);

    initial begin
        clock = 0;
        io_clk = 0;
    end


    integer x;
    integer xi;
    integer y;
    integer addr;
    real simtime;
    real kdtreetime;
    real querytime;
    real fsmtime;
    real outputtime;
    integer i;
    integer px;
    integer agg;
    integer node_data_file;
    integer leaf_data_file;
    integer query_data_file;
    reg [21:0] tmp_node;
    reg [54:0] tmp_query;

    initial begin
        $timeformat(-9, 2, "ns", 20);
        $dumpfile("ann_dbg_mem.vcd");
        $dumpvars(0, ann_dbg_mem_tb);

        node_data_file = $fopen("node.txt", "w");
        leaf_data_file = $fopen("leaf.txt", "w");
        query_data_file = $fopen("query.txt", "w");
        
        fsm_start = 0;
        send_best_arr = 0;
        load_kdtree = 0;
        io_rst_n = 1'b1;
        in_fifo_wenq = 0;
        in_fifo_wdata = 11'd0;
        out_fifo_deq = 0;



        wait(wbs_cfg_done);



        #100
        io_rst_n = 0;
        #100
        io_rst_n = 1'b1;
        #100


        @(negedge io_clk) load_kdtree = 1'b1;
        simtime = $realtime;
        $display("[T=%0t] Start sending KD tree internal nodes and leaves", $realtime);
        @(negedge io_clk) load_kdtree = 1'b0;




        for(i=0; i<NUM_NODES*2; i=i+1) begin
            @(negedge io_clk)
            in_fifo_wenq = 1'b1;
            in_fifo_wdata = i;
            if (i % 2 == 1) begin
                tmp_node[i[0] * 11 +: 11] = i[10:0];
                $fwrite(node_data_file, "%h\n", tmp_node);
            end else tmp_node[i[0] * 11 +: 11] = {8'd0, i[2:0]};
        end
        @(negedge io_clk)
        in_fifo_wenq = 0;
        in_fifo_wdata = 11'd0;





        for(i=0; i<NUM_LEAVES*6*8; i=i+1) begin
            @(negedge io_clk)
            in_fifo_wenq = 1'b1;
            in_fifo_wdata = i;
        end
        @(negedge io_clk)
        in_fifo_wenq = 0;
        in_fifo_wdata = 11'd0;
        $display("[T=%0t] Finished sending KD tree internal nodes and leaves", $realtime);
        kdtreetime = $realtime - simtime;
        
        $display("[T=%0t] Start sending queries", $realtime);
        simtime = $realtime;


        for(i=0; i<NUM_QUERYS*5; i=i+1) begin
            @(negedge io_clk)
            in_fifo_wenq = 1'b1;
            in_fifo_wdata = i;
            tmp_query[(i % 5) * 11 +: 11] = i[10:0];
            if (i % 5 == 4)
                $fwrite(query_data_file, "%h\n", tmp_query);
        end
        @(negedge io_clk)
        in_fifo_wenq = 0;
        in_fifo_wdata = 11'd0;
        $display("[T=%0t] Finished sending queries", $realtime);
        querytime = $realtime - simtime;


        $display("===============Runtime Summary===============");
        $display("KD tree: %t", kdtreetime);
        $display("Query patches: %t", querytime);
    end

    initial begin

        repeat (150) begin
            repeat (1000) @(posedge clock);
            $display("+1000 cycles");
        end
        $display("%c[1;31m",27);
        $display("%c[0m",27);
        $finish;
    end

    initial begin
        $display("Monitor: MPRJ-Logic WB Started");
        wait(wbs_done == 1);
        if (wbs_cfg_done == 1) begin
            `ifdef GL
                $display("Monitor: Mega-Project WB (GL) Passed");
            `else
                $display("Monitor: Mega-Project WB (RTL) Passed");
            `endif
        end
        else begin
            `ifdef GL
                $display ("Monitor: Test Mega-Project WB Port (GL) Failed");
            `else
                $display ("Monitor: Test Mega-Project WB Port (RTL) Failed");
            `endif
        end
        $finish;
    end

    initial begin
        RSTB <= 1'b0;
        CSB  <= 1'b1;
        #2000;
        RSTB <= 1'b1;
        #100000;
        CSB = 1'b0;
    end

    initial begin
        power1 <= 1'b0;
        power2 <= 1'b0;
        #200;
        power1 <= 1'b1;
        #200;
        power2 <= 1'b1;
    end

    wire flash_csb;
    wire flash_clk;
    wire flash_io0;
    wire flash_io1;

    wire VDD3V3 = power1;
    wire VDD1V8 = power2;
    wire USER_VDD3V3 = power3;
    wire USER_VDD1V8 = power4;
    wire VSS = 1'b0;

    caravel uut (
        .vddio	  (VDD3V3),
        .vddio_2  (VDD3V3),
        .vssio	  (VSS),
        .vssio_2  (VSS),
        .vdda	  (VDD3V3),
        .vssa	  (VSS),
        .vccd	  (VDD1V8),
        .vssd	  (VSS),
        .vdda1    (VDD3V3),
        .vdda1_2  (VDD3V3),
        .vdda2    (VDD3V3),
        .vssa1	  (VSS),
        .vssa1_2  (VSS),
        .vssa2	  (VSS),
        .vccd1	  (VDD1V8),
        .vccd2	  (VDD1V8),
        .vssd1	  (VSS),
        .vssd2	  (VSS),
        .clock    (clock),
        .gpio     (gpio),
        .mprj_io  (mprj_io),
        .flash_csb(flash_csb),
        .flash_clk(flash_clk),
        .flash_io0(flash_io0),
        .flash_io1(flash_io1),
        .resetb	  (RSTB)
    );

    spiflash #(
        .FILENAME("ann_dbg_mem.hex")
    ) spiflash (
        .csb(flash_csb),
        .clk(flash_clk),
        .io0(flash_io0),
        .io1(flash_io1),
        .io2(),
        .io3()
    );

    `ifdef ENABLE_SDF
		initial begin
			$sdf_annotate("../../../sdf/user_project_wrapper.sdf", uut.mprj);
			$sdf_annotate("../../../sdf/user_proj_example.sdf", uut.mprj.mprj);
		end
	`endif 

endmodule
module ann_dbg_mem_tb;

    parameter DATA_WIDTH = 11;
    parameter LEAF_SIZE = 8;
    parameter PATCH_SIZE = 5;
    parameter ROW_SIZE = 32;
    parameter COL_SIZE = 16;
    parameter NUM_QUERYS = ROW_SIZE * COL_SIZE;
    parameter NUM_LEAVES = 64;
    parameter NUM_NODES = NUM_LEAVES - 1;
    parameter BLOCKING = 4;
    parameter ADDR_WIDTH = $clog2(NUM_LEAVES);

    reg clock;
    reg RSTB;
    reg CSB;
    reg power1, power2;
    reg power3, power4;

    wire gpio;
    wire [37:0] mprj_io;

    reg                                 io_clk;
    reg                                 io_rst_n;
    reg                                 fsm_start;
    wire                                fsm_done;
    reg                                 send_best_arr;
    wire                                send_done;
    reg                                 load_kdtree;
    wire                                load_done;
    reg                                 in_fifo_wenq;
    reg [10:0]                          in_fifo_wdata;
    wire                                in_fifo_wfull_n;
    reg                                 out_fifo_deq;
    wire [10:0]                         out_fifo_rdata;
    wire                                out_fifo_rempty_n;
    wire                                wbs_done;
    wire                                wbs_busy;
    wire                                wbs_cfg_done;


    assign mprj_io[0] = io_clk;
    assign mprj_io[1] = io_rst_n;
    assign mprj_io[2] = in_fifo_wenq;
    assign mprj_io[13:3] = in_fifo_wdata;
    assign in_fifo_wfull_n = mprj_io[14];
    assign mprj_io[15] = fsm_start;
    assign mprj_io[16] = send_best_arr;
    assign mprj_io[17] = load_kdtree;
    assign load_done = mprj_io[18];
    assign fsm_done = mprj_io[19];
    assign send_done = mprj_io[20];
    assign wbs_done = mprj_io[21];
    assign wbs_busy = mprj_io[22];
    assign wbs_cfg_done = mprj_io[23];
    assign mprj_io[25] = out_fifo_deq;
    assign out_fifo_rdata = mprj_io[36:26];
    assign out_fifo_rempty_n = mprj_io[37];





    always #50 clock <= (clock === 1'b0);
    always #3 io_clk <= (io_clk === 1'b0);

    initial begin
        clock = 0;
        io_clk = 0;
    end


    integer x;
    integer xi;
    integer y;
    integer addr;
    real simtime;
    real kdtreetime;
    real querytime;
    real fsmtime;
    real outputtime;
    integer i;
    integer px;
    integer agg;
    integer node_data_file;
    integer leaf_data_file;
    integer query_data_file;
    reg [21:0] tmp_node;
    reg [54:0] tmp_query;

    initial begin
        $timeformat(-9, 2, "ns", 20);
        $dumpfile("ann_dbg_mem.vcd");
        $dumpvars(0, ann_dbg_mem_tb);

        node_data_file = $fopen("node.txt", "w");
        leaf_data_file = $fopen("leaf.txt", "w");
        query_data_file = $fopen("query.txt", "w");
        
        fsm_start = 0;
        send_best_arr = 0;
        load_kdtree = 0;
        io_rst_n = 1'b1;
        in_fifo_wenq = 0;
        in_fifo_wdata = 11'd0;
        out_fifo_deq = 0;



        wait(wbs_cfg_done);



        #100
        io_rst_n = 0;
        #100
        io_rst_n = 1'b1;
        #100


        @(negedge io_clk) load_kdtree = 1'b1;
        simtime = $realtime;
        $display("[T=%0t] Start sending KD tree internal nodes and leaves", $realtime);
        @(negedge io_clk) load_kdtree = 1'b0;




        for(i=0; i<NUM_NODES*2; i=i+1) begin
            @(negedge io_clk)
            in_fifo_wenq = 1'b1;
            in_fifo_wdata = i;
            if (i % 2 == 1) begin
                tmp_node[i[0] * 11 +: 11] = i[10:0];
                $fwrite(node_data_file, "%h\n", tmp_node);
            end else tmp_node[i[0] * 11 +: 11] = {8'd0, i[2:0]};
        end
        @(negedge io_clk)
        in_fifo_wenq = 0;
        in_fifo_wdata = 11'd0;





        for(i=0; i<NUM_LEAVES*6*8; i=i+1) begin
            @(negedge io_clk)
            in_fifo_wenq = 1'b1;
            in_fifo_wdata = i;
        end
        @(negedge io_clk)
        in_fifo_wenq = 0;
        in_fifo_wdata = 11'd0;
        $display("[T=%0t] Finished sending KD tree internal nodes and leaves", $realtime);
        kdtreetime = $realtime - simtime;
        
        $display("[T=%0t] Start sending queries", $realtime);
        simtime = $realtime;


        for(i=0; i<NUM_QUERYS*5; i=i+1) begin
            @(negedge io_clk)
            in_fifo_wenq = 1'b1;
            in_fifo_wdata = i;
            tmp_query[(i % 5) * 11 +: 11] = i[10:0];
            if (i % 5 == 4)
                $fwrite(query_data_file, "%h\n", tmp_query);
        end
        @(negedge io_clk)
        in_fifo_wenq = 0;
        in_fifo_wdata = 11'd0;
        $display("[T=%0t] Finished sending queries", $realtime);
        querytime = $realtime - simtime;


        $display("===============Runtime Summary===============");
        $display("KD tree: %t", kdtreetime);
        $display("Query patches: %t", querytime);
    end

    initial begin

        repeat (150) begin
            repeat (1000) @(posedge clock);
            $display("+1000 cycles");
        end
        $display("%c[1;31m",27);
        $display("%c[0m",27);
        $finish;
    end

    initial begin
        $display("Monitor: MPRJ-Logic WB Started");
        wait(wbs_done == 1);
        if (wbs_cfg_done == 1) begin
            `ifdef GL
                $display("Monitor: Mega-Project WB (GL) Passed");
            `else
                $display("Monitor: Mega-Project WB (RTL) Passed");
            `endif
        end
        else begin
            `ifdef GL
                $display ("Monitor: Test Mega-Project WB Port (GL) Failed");
            `else
                $display ("Monitor: Test Mega-Project WB Port (RTL) Failed");
            `endif
        end
        $finish;
    end

    initial begin
        RSTB <= 1'b0;
        CSB  <= 1'b1;
        #2000;
        RSTB <= 1'b1;
        #100000;
        CSB = 1'b0;
    end

    initial begin
        power1 <= 1'b0;
        power2 <= 1'b0;
        #200;
        power1 <= 1'b1;
        #200;
        power2 <= 1'b1;
    end

    wire flash_csb;
    wire flash_clk;
    wire flash_io0;
    wire flash_io1;

    wire VDD3V3 = power1;
    wire VDD1V8 = power2;
    wire USER_VDD3V3 = power3;
    wire USER_VDD1V8 = power4;
    wire VSS = 1'b0;

    caravel uut (
        .vddio	  (VDD3V3),
        .vddio_2  (VDD3V3),
        .vssio	  (VSS),
        .vssio_2  (VSS),
        .vdda	  (VDD3V3),
        .vssa	  (VSS),
        .vccd	  (VDD1V8),
        .vssd	  (VSS),
        .vdda1    (VDD3V3),
        .vdda1_2  (VDD3V3),
        .vdda2    (VDD3V3),
        .vssa1	  (VSS),
        .vssa1_2  (VSS),
        .vssa2	  (VSS),
        .vccd1	  (VDD1V8),
        .vccd2	  (VDD1V8),
        .vssd1	  (VSS),
        .vssd2	  (VSS),
        .clock    (clock),
        .gpio     (gpio),
        .mprj_io  (mprj_io),
        .flash_csb(flash_csb),
        .flash_clk(flash_clk),
        .flash_io0(flash_io0),
        .flash_io1(flash_io1),
        .resetb	  (RSTB)
    );

    spiflash #(
        .FILENAME("ann_dbg_mem.hex")
    ) spiflash (
        .csb(flash_csb),
        .clk(flash_clk),
        .io0(flash_io0),
        .io1(flash_io1),
        .io2(),
        .io3()
    );

    `ifdef ENABLE_SDF
		initial begin
			$sdf_annotate("../../../sdf/user_project_wrapper.sdf", uut.mprj);
			$sdf_annotate("../../../sdf/user_proj_example.sdf", uut.mprj.mprj);
		end
	`endif 

endmodule