data/full_repos/permissive/426889244/tb/DMEM_IO.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/426889244/tb/DMEM_IO.v:29: Signal definition not found, creating implicitly: \'result\'\n    assign result = display_result;\n           ^~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/426889244/tb/DMEM_IO.v:29: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'display_result\' generates 16 bits.\n                                                                    : ... In instance DMEM\n    assign result = display_result;\n                  ^\n%Error: data/full_repos/permissive/426889244/tb/DMEM_IO.v:31: Cannot find file containing module: \'bram\'\n    bram bram_inst (\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/426889244/tb,data/full_repos/permissive/426889244/bram\n             data/full_repos/permissive/426889244/tb,data/full_repos/permissive/426889244/bram.v\n             data/full_repos/permissive/426889244/tb,data/full_repos/permissive/426889244/bram.sv\n             bram\n             bram.v\n             bram.sv\n             obj_dir/bram\n             obj_dir/bram.v\n             obj_dir/bram.sv\n%Warning-WIDTH: data/full_repos/permissive/426889244/tb/DMEM_IO.v:46: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'wdata\' generates 32 bits.\n                                                                    : ... In instance DMEM\n                            toss_cnt <= wdata;\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/426889244/tb/DMEM_IO.v:51: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'wdata\' generates 32 bits.\n                                                                    : ... In instance DMEM\n                            egg_cnt <= wdata;\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/426889244/tb/DMEM_IO.v:56: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'wdata\' generates 32 bits.\n                                                                    : ... In instance DMEM\n                            is_egg_break <= wdata;\n                                         ^~\n%Error: Exiting due to 1 error(s), 5 warning(s)\n'
module DMEM (
    input wire clk,
    input wire we,
    input wire[31:0] ask_addr,
    input wire[31:0] fetch_addr,
    input wire[31:0] wdata,
    
    output wire[31:0] rdata,


    input wire[7:0] opr1,
    input wire[7:0] opr2,
    output reg[15:0] toss_cnt,
    output reg[15:0] egg_cnt,
    output reg[15:0] is_egg_break
);
    wire[31:0] bram_result;
    wire bram_we = ~ask_addr[31] & we;

    reg[7:0] opr1_reg;
    reg[7:0] opr2_reg;

    assign rdata = fetch_addr[31] ? (fetch_addr[2] ? {24'h0, opr2_reg} : {24'h0, opr1_reg})
                    : bram_result;



    reg[15:0] display_result;
    assign result = display_result;

    bram bram_inst (
        .clka(clk),

        .wea(bram_we),
        .addra(ask_addr[17:2]),
        .dina(wdata),
        .douta(bram_result)
    );

    always @(posedge clk) begin
        if (we) begin
            if (ask_addr[31]) begin
                case (ask_addr[4:0])
                    5'h08:
                        begin
                            toss_cnt <= wdata;
                        end

                    5'h0c:
                        begin
                            egg_cnt <= wdata;
                        end

                    5'h10:
                        begin
                            is_egg_break <= wdata;
                        end
                endcase
                display_result <= wdata[15:0];
            end
        end

        opr1_reg <= opr1;
        opr2_reg <= opr2;
    end
endmodule
module DMEM (
    input wire clk,
    input wire we,
    input wire[31:0] ask_addr,
    input wire[31:0] fetch_addr,
    input wire[31:0] wdata,
    
    output wire[31:0] rdata,


    input wire[7:0] opr1,
    input wire[7:0] opr2,
    output reg[15:0] toss_cnt,
    output reg[15:0] egg_cnt,
    output reg[15:0] is_egg_break
);

    wire[31:0] bram_result;
    wire bram_we = ~ask_addr[31] & we;

    reg[7:0] opr1_reg;
    reg[7:0] opr2_reg;

    assign rdata = fetch_addr[31] ? (fetch_addr[2] ? {24'h0, opr2_reg} : {24'h0, opr1_reg})
                    : bram_result;



    reg[15:0] display_result;
    assign result = display_result;

    bram bram_inst (
        .clka(clk),

        .wea(bram_we),
        .addra(ask_addr[17:2]),
        .dina(wdata),
        .douta(bram_result)
    );

    always @(posedge clk) begin
        if (we) begin
            if (ask_addr[31]) begin
                case (ask_addr[4:0])
                    5'h08:
                        begin
                            toss_cnt <= wdata;
                        end

                    5'h0c:
                        begin
                            egg_cnt <= wdata;
                        end

                    5'h10:
                        begin
                            is_egg_break <= wdata;
                        end
                endcase
                display_result <= wdata[15:0];
            end
        end

        opr1_reg <= opr1;
        opr2_reg <= opr2;
    end
endmodule