data/full_repos/permissive/428158935/sources_1/new/AdderModule.v
data/verilator_xmls/dff4d8a6-ea7a-49c3-a5fc-75c71889658f.xml
module CLA_Add_16bit(
    input[15:0] A,
    input[15:0] B,
    input CI_0,
    output[15:0] S,
    output GM,
    output PM
);

wire[3:0] G;
wire[3:0] P;
wire[4:1] CI;

CLA_Add_4bit u1(
    .A (A[3:0]),
    .B (B[3:0]),
    .CI_0 (CI_0),
    .S (S[3:0]),
    .Gm (G[0]),
    .Pm (P[0])
);
    
CLA_Add_4bit u2(
    .A (A[7:4]),
    .B (B[7:4]),
    .CI_0 (CI[1]),
    .S (S[7:4]),
    .Gm (G[1]),
    .Pm (P[1])
);
    
CLA_Add_4bit u3(
    .A (A[11:8]),
    .B (B[11:8]),
    .CI_0 (CI[2]),
    .S (S[11:8]),
    .Gm (G[2]),
    .Pm (P[2])
);
    
CLA_Add_4bit u4(
    .A (A[15:12]),
    .B (B[15:12]),
    .CI_0 (CI[3]),
    .S (S[15:12]),
    .Gm (G[3]),
    .Pm (P[3])
);

CLA_4bit U(
    .P (P),
    .G (G),
    .CI_0 (CI_0),
    .CI (CI),
    .Gm (GM),
    .Pm (PM)
);
    
endmodule
module CLA_Add_16bit(
    input[15:0] A,
    input[15:0] B,
    input CI_0,
    output[15:0] S,
    output GM,
    output PM
);


wire[3:0] G;
wire[3:0] P;
wire[4:1] CI;

CLA_Add_4bit u1(
    .A (A[3:0]),
    .B (B[3:0]),
    .CI_0 (CI_0),
    .S (S[3:0]),
    .Gm (G[0]),
    .Pm (P[0])
);
    
CLA_Add_4bit u2(
    .A (A[7:4]),
    .B (B[7:4]),
    .CI_0 (CI[1]),
    .S (S[7:4]),
    .Gm (G[1]),
    .Pm (P[1])
);
    
CLA_Add_4bit u3(
    .A (A[11:8]),
    .B (B[11:8]),
    .CI_0 (CI[2]),
    .S (S[11:8]),
    .Gm (G[2]),
    .Pm (P[2])
);
    
CLA_Add_4bit u4(
    .A (A[15:12]),
    .B (B[15:12]),
    .CI_0 (CI[3]),
    .S (S[15:12]),
    .Gm (G[3]),
    .Pm (P[3])
);

CLA_4bit U(
    .P (P),
    .G (G),
    .CI_0 (CI_0),
    .CI (CI),
    .Gm (GM),
    .Pm (PM)
);
    
endmodule