data/full_repos/permissive/490649362/single-cycle/src/DM.v
data/verilator_xmls/b30452e2-b4f9-4683-ae12-0835c922a0e6.xml
module DM(clk, addr, write_data, read_data, MemWrite, MemRead);

    parameter size = 64;

    input         clk;
    input         MemRead, MemWrite;
    input  [31:0] addr, write_data;
    output [31:0] read_data;

    reg [31:0] data_memory [0:size-1];


    initial begin
        for (integer i = 0; i < size; i = i + 1)
            data_memory[i] = 32'b0;
    end


    always @(posedge clk) begin
        if (MemWrite) begin
            data_memory[addr >> 2] = write_data;
        end
    end


    assign read_data = MemRead ? data_memory[addr >> 2] : 32'b0;

endmodule
module DM(clk, addr, write_data, read_data, MemWrite, MemRead);


    parameter size = 64;

    input         clk;
    input         MemRead, MemWrite;
    input  [31:0] addr, write_data;
    output [31:0] read_data;

    reg [31:0] data_memory [0:size-1];


    initial begin
        for (integer i = 0; i < size; i = i + 1)
            data_memory[i] = 32'b0;
    end


    always @(posedge clk) begin
        if (MemWrite) begin
            data_memory[addr >> 2] = write_data;
        end
    end


    assign read_data = MemRead ? data_memory[addr >> 2] : 32'b0;

endmodule