data/full_repos/permissive/499944578/rtl/src/memory/memory.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/499944578/rtl/src/memory/memory.v:178: Multiple top level modules\n                                                                                   : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                   : ... Top module \'FIFO\'\nmodule FIFO #(\n       ^~~~\n                                                                                   : ... Top module \'single_port_ram\'\nmodule single_port_ram\n       ^~~~~~~~~~~~~~~\n                                                                                   : ... Top module \'ROM\'\nmodule ROM #(\n       ^~~\n                                                                                   : ... Top module \'simple_ram_dual_clock\'\nmodule simple_ram_dual_clock #(\n       ^~~~~~~~~~~~~~~~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/499944578/rtl/src/memory/memory.v:247: Little bit endian vector: MSB < LSB of bit range: -1:0\n    reg [(2**ADDR_WIDTH)-1:0][DATA_WIDTH-1:0] ram;  \n        ^\n%Error: Exiting due to 2 warning(s)\n'
module read_pointer#(
    parameter DATAWIDTH = 8,
    parameter DEPTH = 16
)(
    output reg [$clog2(DEPTH):0] rptr,
    output wire fifo_rd,
    input  wire rd,
    input  wire fifo_empty,
    input  wire clk,
    input  wire resetn
);  
    assign fifo_rd = (~fifo_empty)& rd;  
    always @(posedge clk or negedge resetn) begin  
        if(~resetn) 
            rptr <= 'b0;  
        else if(fifo_rd)  
            rptr <= rptr + 'b1;  
        else  
            rptr <= rptr;  
    end  
endmodule
module read_pointer#(
    parameter DATAWIDTH = 8,
    parameter DEPTH = 16
)(
    output reg [$clog2(DEPTH):0] rptr,
    output wire fifo_rd,
    input  wire rd,
    input  wire fifo_empty,
    input  wire clk,
    input  wire resetn
);
  
    assign fifo_rd = (~fifo_empty)& rd;  
    always @(posedge clk or negedge resetn) begin  
        if(~resetn) 
            rptr <= 'b0;  
        else if(fifo_rd)  
            rptr <= rptr + 'b1;  
        else  
            rptr <= rptr;  
    end  
endmodule