data/full_repos/permissive/515599642/Simple CPU module using Verilog/MUX.v
1: b'%Error: Cannot find file containing module: CPU\n        ... Looked in:\n             data/full_repos/permissive/515599642/Simple/CPU\n             data/full_repos/permissive/515599642/Simple/CPU.v\n             data/full_repos/permissive/515599642/Simple/CPU.sv\n             CPU\n             CPU.v\n             CPU.sv\n             obj_dir/CPU\n             obj_dir/CPU.v\n             obj_dir/CPU.sv\n%Error: Cannot find file containing module: module\n%Error: Cannot find file containing module: using\n%Error: Cannot find file containing module: Verilog,data/full_repos/permissive/515599642\n%Error: Cannot find file containing module: data/full_repos/permissive/515599642/Simple\n%Error: Cannot find file containing module: Verilog/MUX.v\n%Error: Exiting due to 6 error(s)\n'
module MUX(B, R, MUX_SEL, M);	
input [3:0] B;
input [3:0] R;
input MUX_SEL;
output reg[3:0] M;

always@(*)begin
	if (MUX_SEL == 1)
		M = B;
		else
		M = R;
	end
	
endmodule
module MUX(B, R, MUX_SEL, M);
	
input [3:0] B;
input [3:0] R;
input MUX_SEL;
output reg[3:0] M;

always@(*)begin
	if (MUX_SEL == 1)
		M = B;
		else
		M = R;
	end
	
endmodule