data/full_repos/permissive/46240546/ripple_cc.v
data/verilator_xmls/12a295a2-a0c5-4a74-8d00-18be5a0ae96f.xml
module tff(
  output reg q,
  input clk,
  input reset);
  
  always @(posedge reset or negedge clk) begin
    if(reset) begin
      q <= 1'b0;
    end else begin
      q <= ~q;
    end
  end
endmodule
module tff(
  output reg q,
  input clk,
  input reset);

  
  always @(posedge reset or negedge clk) begin
    if(reset) begin
      q <= 1'b0;
    end else begin
      q <= ~q;
    end
  end
endmodule