data/full_repos/permissive/422178762/verilog/rtl/dirctrl_ssp.v
1: b'%Warning-WIDTH: data/full_repos/permissive/422178762/verilog/rtl/dirctrl_ssp.v:117: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s LTE generates 1 bits.\n                                                                                  : ... In instance dirctrl_ssp\n                            default        : begin apb_rdata  <= apb_rdata  <= 32\'h0000_0000; end\n                                                              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module dirctrl_ssp (
    input              clock,
    input              rst_n,
    input  [31:0]      apb_addr,
    input              apb_sel,
    input              apb_write,
    input              apb_ena,
    input  [31:0]      apb_wdata,
    output reg [31:0]  apb_rdata,
    input  [3:0]       apb_pstb,
    output             apb_rready,
    
    output reg   	uart_txd_dir,
    output reg         uart_rxd_dir,
    
    output reg [4:0] 	spi_dir,
    
    output reg  	scl_dir,
    output reg   	sda_dir,
    
    output reg [1:0]  	pwm_dir,
    
    output reg       	led_dir,
    
    output reg       	i2s_dir,
    
    output reg         rst_n_ctrl,
   
    output reg         aud_clk_mux ,
    
    output reg         jtag_mux,
    
    output reg         qspi_mux
    
    );
    localparam UART_DADDR    	= 8'h10;
    localparam SPI_DADDR    	= 8'h00;
    localparam I2C_DADDR    	= 8'h04;
    localparam PWM_DADDR   	= 8'h08;
    localparam LED_DADDR   	= 8'h0C;
    localparam I2S_DADDR   	= 8'h14;
    localparam RESET_ADDR   	= 8'h1C;
    localparam AUDCLK_MUX      = 8'h20;
    localparam JTAG_MUXADDR        = 8'h2c;
    localparam QSPI_MUXADDR        = 8'h30;
    
    assign apb_rready = 1'b1;
    
   
     
    always @(posedge clock or negedge rst_n) begin 
        if(!rst_n) begin
        	
            uart_txd_dir <= 1'b0;
            uart_rxd_dir <= 1'b1;
            spi_dir <= 5'b01000;
            scl_dir <= 1'b0;
            sda_dir <= 1'b0;
            pwm_dir <= 2'b00;
            led_dir <= 1'b0;
            i2s_dir <= 1'b0;
            rst_n_ctrl   <= 1'b0;
            aud_clk_mux  <= 1'b0;
            jtag_mux     <= 1'b0;
            qspi_mux     <= 1'b0;
        end else begin
        
            if(apb_sel && apb_write) begin 
                case(apb_addr[7:0]) 
                            SPI_DADDR     : begin spi_dir    <= apb_wdata[4:0] ;end
                            I2C_DADDR     : begin scl_dir     <= apb_wdata[0] ;
                                                  sda_dir     <= apb_wdata[1] ;
                                            end
                           PWM_DADDR      : begin  pwm_dir    <= apb_wdata[1:0] ; end
                           LED_DADDR      : begin  led_dir    <= apb_wdata[0] ;  end
                           UART_DADDR     : begin   uart_txd_dir <= apb_wdata[0] ;  
                           			      uart_rxd_dir <= apb_wdata[1] ;  
                           		      end
                           I2S_DADDR      : begin     i2s_dir   <= apb_wdata[0] ;  end    
                           RESET_ADDR     : begin     rst_n_ctrl    <= apb_wdata[0] ; end
                           
                           AUDCLK_MUX     : begin aud_clk_mux <= apb_wdata[0] ; end
                           
                           JTAG_MUXADDR     : begin     jtag_mux    <= apb_wdata[0] ; end
                           QSPI_MUXADDR  : begin     qspi_mux    <= apb_wdata[0] ; end
                            
                 endcase        
              end
              
             if(apb_sel && !apb_write) begin 
                    case(apb_addr[7:0]) 
                            SPI_DADDR      : begin apb_rdata  <= {24'h000000,3'b000,spi_dir}  ;end
                            I2C_DADDR      : begin apb_rdata  <= {28'h0000000,2'b00,sda_dir,scl_dir}  ;end
                            PWM_DADDR      : begin apb_rdata  <= {28'h0000000,2'b00,pwm_dir}    ;end
                            LED_DADDR      : begin apb_rdata  <= {28'h0000000,3'b000,led_dir}  ;end
                            UART_DADDR     : begin apb_rdata  <= {28'h0000000,2'b00,uart_rxd_dir,uart_txd_dir}    ;end
                            I2S_DADDR      : begin apb_rdata  <= {28'h0000000,3'b000,i2s_dir}  ;end
                             RESET_ADDR     : begin apb_rdata  <= {28'h0000000,3'b000,rst_n_ctrl}  ;end
                             AUDCLK_MUX     : begin apb_rdata  <= {28'h0000000,3'b000,aud_clk_mux}  ;end
                              JTAG_MUXADDR     : begin    apb_rdata  <= {28'h0000000,3'b000,jtag_mux}   ; end
                           QSPI_MUXADDR  : begin    apb_rdata  <= {28'h0000000,3'b000,qspi_mux}    ; end
                             
                            default        : begin apb_rdata  <= apb_rdata  <= 32'h0000_0000; end
                    endcase      
                            
            end            
            
              
              
              
              
              
             
        
        end
    
    end
    
    
    
    
    
    
    
    
    
    
endmodule
module dirctrl_ssp (
    input              clock,
    input              rst_n,
    input  [31:0]      apb_addr,
    input              apb_sel,
    input              apb_write,
    input              apb_ena,
    input  [31:0]      apb_wdata,
    output reg [31:0]  apb_rdata,
    input  [3:0]       apb_pstb,
    output             apb_rready,
    
    output reg   	uart_txd_dir,
    output reg         uart_rxd_dir,
    
    output reg [4:0] 	spi_dir,
    
    output reg  	scl_dir,
    output reg   	sda_dir,
    
    output reg [1:0]  	pwm_dir,
    
    output reg       	led_dir,
    
    output reg       	i2s_dir,
    
    output reg         rst_n_ctrl,
   
    output reg         aud_clk_mux ,
    
    output reg         jtag_mux,
    
    output reg         qspi_mux
    
    );

    localparam UART_DADDR    	= 8'h10;
    localparam SPI_DADDR    	= 8'h00;
    localparam I2C_DADDR    	= 8'h04;
    localparam PWM_DADDR   	= 8'h08;
    localparam LED_DADDR   	= 8'h0C;
    localparam I2S_DADDR   	= 8'h14;
    localparam RESET_ADDR   	= 8'h1C;
    localparam AUDCLK_MUX      = 8'h20;
    localparam JTAG_MUXADDR        = 8'h2c;
    localparam QSPI_MUXADDR        = 8'h30;
    
    assign apb_rready = 1'b1;
    
   
     
    always @(posedge clock or negedge rst_n) begin 
        if(!rst_n) begin
        	
            uart_txd_dir <= 1'b0;
            uart_rxd_dir <= 1'b1;
            spi_dir <= 5'b01000;
            scl_dir <= 1'b0;
            sda_dir <= 1'b0;
            pwm_dir <= 2'b00;
            led_dir <= 1'b0;
            i2s_dir <= 1'b0;
            rst_n_ctrl   <= 1'b0;
            aud_clk_mux  <= 1'b0;
            jtag_mux     <= 1'b0;
            qspi_mux     <= 1'b0;
        end else begin
        
            if(apb_sel && apb_write) begin 
                case(apb_addr[7:0]) 
                            SPI_DADDR     : begin spi_dir    <= apb_wdata[4:0] ;end
                            I2C_DADDR     : begin scl_dir     <= apb_wdata[0] ;
                                                  sda_dir     <= apb_wdata[1] ;
                                            end
                           PWM_DADDR      : begin  pwm_dir    <= apb_wdata[1:0] ; end
                           LED_DADDR      : begin  led_dir    <= apb_wdata[0] ;  end
                           UART_DADDR     : begin   uart_txd_dir <= apb_wdata[0] ;  
                           			      uart_rxd_dir <= apb_wdata[1] ;  
                           		      end
                           I2S_DADDR      : begin     i2s_dir   <= apb_wdata[0] ;  end    
                           RESET_ADDR     : begin     rst_n_ctrl    <= apb_wdata[0] ; end
                           
                           AUDCLK_MUX     : begin aud_clk_mux <= apb_wdata[0] ; end
                           
                           JTAG_MUXADDR     : begin     jtag_mux    <= apb_wdata[0] ; end
                           QSPI_MUXADDR  : begin     qspi_mux    <= apb_wdata[0] ; end
                            
                 endcase        
              end
              
             if(apb_sel && !apb_write) begin 
                    case(apb_addr[7:0]) 
                            SPI_DADDR      : begin apb_rdata  <= {24'h000000,3'b000,spi_dir}  ;end
                            I2C_DADDR      : begin apb_rdata  <= {28'h0000000,2'b00,sda_dir,scl_dir}  ;end
                            PWM_DADDR      : begin apb_rdata  <= {28'h0000000,2'b00,pwm_dir}    ;end
                            LED_DADDR      : begin apb_rdata  <= {28'h0000000,3'b000,led_dir}  ;end
                            UART_DADDR     : begin apb_rdata  <= {28'h0000000,2'b00,uart_rxd_dir,uart_txd_dir}    ;end
                            I2S_DADDR      : begin apb_rdata  <= {28'h0000000,3'b000,i2s_dir}  ;end
                             RESET_ADDR     : begin apb_rdata  <= {28'h0000000,3'b000,rst_n_ctrl}  ;end
                             AUDCLK_MUX     : begin apb_rdata  <= {28'h0000000,3'b000,aud_clk_mux}  ;end
                              JTAG_MUXADDR     : begin    apb_rdata  <= {28'h0000000,3'b000,jtag_mux}   ; end
                           QSPI_MUXADDR  : begin    apb_rdata  <= {28'h0000000,3'b000,qspi_mux}    ; end
                             
                            default        : begin apb_rdata  <= apb_rdata  <= 32'h0000_0000; end
                    endcase      
                            
            end            
            
              
              
              
              
              
             
        
        end
    
    end
    
    
    
    
    
    
    
    
    
    
endmodule