data/full_repos/permissive/507307707/generated/CellProcessing.v
data/verilator_xmls/ab97e684-dfea-49c9-88b0-d7fe90873c62.xml
module ConfMux_1(
  input  [2:0]   io_selector,
  input  [191:0] io_mux_input,
  output [31:0]  io_mux_output
);
  wire [31:0] inputs_0 = io_mux_input[31:0];
  wire [31:0] inputs_1 = io_mux_input[63:32];
  wire [31:0] inputs_2 = io_mux_input[95:64];
  wire [31:0] inputs_3 = io_mux_input[127:96];
  wire [31:0] inputs_4 = io_mux_input[159:128];
  wire [31:0] inputs_5 = io_mux_input[191:160];
  wire [31:0] _GEN_1 = 3'h1 == io_selector ? inputs_1 : inputs_0;
  wire [31:0] _GEN_2 = 3'h2 == io_selector ? inputs_2 : _GEN_1;
  wire [31:0] _GEN_3 = 3'h3 == io_selector ? inputs_3 : _GEN_2;
  wire [31:0] _GEN_4 = 3'h4 == io_selector ? inputs_4 : _GEN_3;
  assign io_mux_output = 3'h5 == io_selector ? inputs_5 : _GEN_4;
endmodule
module ConfMux_1(
  input  [2:0]   io_selector,
  input  [191:0] io_mux_input,
  output [31:0]  io_mux_output
);

  wire [31:0] inputs_0 = io_mux_input[31:0];
  wire [31:0] inputs_1 = io_mux_input[63:32];
  wire [31:0] inputs_2 = io_mux_input[95:64];
  wire [31:0] inputs_3 = io_mux_input[127:96];
  wire [31:0] inputs_4 = io_mux_input[159:128];
  wire [31:0] inputs_5 = io_mux_input[191:160];
  wire [31:0] _GEN_1 = 3'h1 == io_selector ? inputs_1 : inputs_0;
  wire [31:0] _GEN_2 = 3'h2 == io_selector ? inputs_2 : _GEN_1;
  wire [31:0] _GEN_3 = 3'h3 == io_selector ? inputs_3 : _GEN_2;
  wire [31:0] _GEN_4 = 3'h4 == io_selector ? inputs_4 : _GEN_3;
  assign io_mux_output = 3'h5 == io_selector ? inputs_5 : _GEN_4;
endmodule