data/full_repos/permissive/504677412/src/spi_slave.v
1: b'%Error: data/full_repos/permissive/504677412/src/spi_slave.v:3: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/504677412/src,data/full_repos/permissive/504677412/defines.v\n             data/full_repos/permissive/504677412/src,data/full_repos/permissive/504677412/defines.v.v\n             data/full_repos/permissive/504677412/src,data/full_repos/permissive/504677412/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:4: Cannot find include file: reg_addr_defines.v\n`include "reg_addr_defines.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:29: Define or directive not defined: \'`REG_ADDR_WIDTH\'\n  output wire [`REG_ADDR_WIDTH-1:0] wr_addr;\n               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:31: Define or directive not defined: \'`REG_SIZE\'\n  output wire [`REG_SIZE-1:0]       wr_data;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:32: Define or directive not defined: \'`REG_ADDR_WIDTH\'\n  output wire [`REG_ADDR_WIDTH-1:0] rd_addr;\n               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:34: Define or directive not defined: \'`REG_SIZE\'\n  input  wire [`REG_SIZE-1:0]       rd_data;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:36: Define or directive not defined: \'`BURST_WIDTH\'\n  input  wire [`BURST_WIDTH-1:0]    wr_burst_size;\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:37: Define or directive not defined: \'`BURST_WIDTH\'\n  input  wire [`BURST_WIDTH-1:0]    rd_burst_size;\n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:59: Define or directive not defined: \'`DATA_LENGTH\'\n  reg [`DATA_LENGTH-1:0]            rx_shift_data;\n       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:60: Define or directive not defined: \'`DATA_LENGTH\'\n  reg [`DATA_LENGTH-1:0]            rx_byte;\n       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:100: Define or directive not defined: \'`REG_ADDR_WIDTH\'\n  reg  [`REG_ADDR_WIDTH-1:0]        addr;\n        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:101: Define or directive not defined: \'`BURST_WIDTH\'\n  wire [`BURST_WIDTH-1:0]           burst_size;\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:212: Define or directive not defined: \'`CLOCK_PHASE\'\n  if (!(`CLOCK_PHASE ^ `CLOCK_POLARITY))\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:212: Define or directive not defined: \'`CLOCK_POLARITY\'\n  if (!(`CLOCK_PHASE ^ `CLOCK_POLARITY))\n                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:212: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  if (!(`CLOCK_PHASE ^ `CLOCK_POLARITY))\n                                      ^\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:218: Define or directive not defined: \'`SHIFT_DIRECTION\'\n           if (`SHIFT_DIRECTION)\n               ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:219: Define or directive not defined: \'`DATA_LENGTH\'\n              rx_shift_data <= {mosi_d2,rx_shift_data[`DATA_LENGTH-1:1]};\n                                                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:221: Define or directive not defined: \'`DATA_LENGTH\'\n              rx_shift_data <= {rx_shift_data[`DATA_LENGTH-2:0],mosi_d2};\n                                              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:226: Define or directive not defined: \'`DATA_LENGTH\'\n         else if (rx_data_cnt == `DATA_LENGTH-1)\n                                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:234: Define or directive not defined: \'`DATA_LENGTH\'\n         else if (rx_data_cnt == `DATA_LENGTH-1)\n                                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:239: syntax error, unexpected end\n  end\n  ^~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:247: Define or directive not defined: \'`SHIFT_DIRECTION\'\n           if (`SHIFT_DIRECTION)\n               ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:248: Define or directive not defined: \'`DATA_LENGTH\'\n             rx_shift_data <= {mosi_d2,rx_shift_data[`DATA_LENGTH-1:1]};\n                                                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:250: Define or directive not defined: \'`DATA_LENGTH\'\n             rx_shift_data <= {rx_shift_data[`DATA_LENGTH-2:0],mosi_d2};\n                                             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:255: Define or directive not defined: \'`DATA_LENGTH\'\n         else if (rx_data_cnt == `DATA_LENGTH - 1)\n                                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:263: Define or directive not defined: \'`DATA_LENGTH\'\n         else if (rx_data_cnt == `DATA_LENGTH - 1)\n                                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:267: syntax error, unexpected end\n  end\n  ^~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:275: Define or directive not defined: \'`CLOCK_PHASE\'\n  if (`CLOCK_PHASE ^ `CLOCK_POLARITY)\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:275: Define or directive not defined: \'`CLOCK_POLARITY\'\n  if (`CLOCK_PHASE ^ `CLOCK_POLARITY)\n                     ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:281: Define or directive not defined: \'`SHIFT_DIRECTION\'\n           miso_i <= `SHIFT_DIRECTION ? rd_data[tx_data_cnt] :\n                     ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:282: Define or directive not defined: \'`DATA_LENGTH\'\n                                        rd_data[`DATA_LENGTH-tx_data_cnt-1];\n                                                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:287: Define or directive not defined: \'`DATA_LENGTH\'\n         else if (tx_data_cnt == `DATA_LENGTH - 1)\n                                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:295: Define or directive not defined: \'`DATA_LENGTH\'\n         else if (tx_data_cnt == `DATA_LENGTH - 1)\n                                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:301: syntax error, unexpected end\n  end\n  ^~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:310: Define or directive not defined: \'`SHIFT_DIRECTION\'\n           miso_i <= `SHIFT_DIRECTION ? rd_data[tx_data_cnt] :\n                     ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:311: Define or directive not defined: \'`DATA_LENGTH\'\n                                        rd_data[`DATA_LENGTH-tx_data_cnt-1];\n                                                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:316: Define or directive not defined: \'`DATA_LENGTH\'\n         else if (tx_data_cnt == `DATA_LENGTH - 1)\n                                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:324: Define or directive not defined: \'`DATA_LENGTH\'\n         else if (tx_data_cnt == `DATA_LENGTH - 1)\n                                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:330: syntax error, unexpected end\n  end\n  ^~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:421: Define or directive not defined: \'`READ_ON\'\n                     if (!rd_on | (rd_on & rx_byte == `READ_ON)) begin\n                                                      ^~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:421: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n                     if (!rd_on | (rd_on & rx_byte == `READ_ON)) begin\n                                                              ^\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:488: Define or directive not defined: \'`READ_ON\'\n    end else if (wr_en & wr_addr == `READ_ON & wr_data[0]) begin\n                                    ^~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:535: Define or directive not defined: \'`BURST_WR_DATA\'\n  assign burst_size = (addr == `BURST_WR_DATA) ? wr_burst_size :\n                               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:535: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  assign burst_size = (addr == `BURST_WR_DATA) ? wr_burst_size :\n                                             ^\n%Error: data/full_repos/permissive/504677412/src/spi_slave.v:536: Define or directive not defined: \'`BURST_RD_DATA\'\n                      (addr == `BURST_RD_DATA) ? rd_burst_size :\n                               ^~~~~~~~~~~~~~\n%Error: Exiting due to 45 error(s)\n'
module spi_slave (

  clk,
  rst_n,
  wr_addr,
  wr_en,
  wr_data,
  rd_addr,
  rd_en,
  rd_data,
  clr_err,
  wr_burst_size,
  rd_burst_size,

  SCLK,
  MOSI,
  MISO,
  SS
);


  input  wire                       clk;
  input  wire                       rst_n;
  output wire [`REG_ADDR_WIDTH-1:0] wr_addr;
  output reg                        wr_en;
  output wire [`REG_SIZE-1:0]       wr_data;
  output wire [`REG_ADDR_WIDTH-1:0] rd_addr;
  output reg                        rd_en;
  input  wire [`REG_SIZE-1:0]       rd_data;
  input  wire                       clr_err;
  input  wire [`BURST_WIDTH-1:0]    wr_burst_size;
  input  wire [`BURST_WIDTH-1:0]    rd_burst_size;
  
  input  wire                       SCLK;
  input  wire                       MOSI;
  output wire                       MISO;
  input  wire                       SS;


  localparam [2:0]                  IDLE      = 3'b000;
  localparam [2:0]                  SPI_ADDR  = 3'b001; 
  localparam [2:0]                  ADDR_DONE = 3'b010;
  localparam [2:0]                  READ_ADDR = 3'b011;
  localparam [2:0]                  WRITE_REG = 3'b100;
  localparam [2:0]                  READ_REG  = 3'b101;
                                    
  localparam [2:0]                  SCLK_IDLE = 3'b000;
  localparam [2:0]                  SCLK_HIGH = 3'b001; 
  localparam [2:0]                  SCLK_LOW  = 3'b010;
  localparam [2:0]                  SCLK_POL_ERR = 3'b011;
  
  reg [2:0]                         rx_data_cnt;
  reg [2:0]                         tx_data_cnt;
  reg [`DATA_LENGTH-1:0]            rx_shift_data;
  reg [`DATA_LENGTH-1:0]            rx_byte;
                                    
  reg                               rx_done;
  reg                               rx_done_d1;
  reg                               rx_done_d2;
  wire                              byte_rx_done_pulse;
  reg                               byte_rx_done_pulse_d1;

  reg                               tx_done;
  reg                               tx_done_d1;
  reg                               tx_done_d2;
  wire                              byte_tx_done_pulse;
  reg                               byte_tx_done_pulse_d1;
  
  reg [2:0]                         c_state;
  reg [2:0]                         n_state;
                                    
  reg                               rd_addr_done;
  reg                               cs_d1;
  reg                               cs_d2;
  reg                               sclk_d1;
  reg                               sclk_d2;
  reg                               sclk_d3;
  wire                              sclk_sync_fe;
  reg                               mosi_d1;
  reg                               mosi_d2;
  reg                               address_done;
  reg                               miso_i;
  wire                              burst_done;
  wire                              burst_done_d1;
  wire                              rd_wr_done;
  wire                              clr_rd_on;
  wire                              rd_done;
  wire                              wr_done;
  wire                              rd_wr_done_d1;
  reg  [15:0]                       burst_cntr;
  reg  [7:0]                        sclk_low_cntr;
  reg                               rd_on;
  wire                              sclk_stable;
  wire                              sclk_low_cntr_done;
  reg  [`REG_ADDR_WIDTH-1:0]        addr;
  wire [`BURST_WIDTH-1:0]           burst_size;
  reg [1:0]                         sclk_c_state;
  reg [1:0]                         sclk_n_state;
  reg [15:0]                        dbg_rd_burst_size_cntr;
  reg [15:0]                        dbg_lch_rd_burst_size_cntr;
  wire                              clr_dbg_cntr;




  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      sclk_d1 <= 1'b1;
      sclk_d2 <= 1'b1;
      mosi_d1 <= 1'b1;
      mosi_d2 <= 1'b1;
    end else begin
      sclk_d1 <= SCLK;
      sclk_d2 <= sclk_d1;
      sclk_d3 <= sclk_d2;
      mosi_d1 <= MOSI;
      mosi_d2 <= mosi_d1;
    end
  end
  
  assign sclk_sync_fe = (!sclk_d1) & sclk_d2;
  
  /
  assign burst_done_d1 = burst_done;
  assign rd_wr_done = cs_d2 & burst_done_d1 ? 1'b1 : 1'b0;

  assign rd_wr_done_d1 = rd_wr_done;

  assign wr_data = rx_byte;
  
endmodule
module spi_slave (

  clk,
  rst_n,
  wr_addr,
  wr_en,
  wr_data,
  rd_addr,
  rd_en,
  rd_data,
  clr_err,
  wr_burst_size,
  rd_burst_size,

  SCLK,
  MOSI,
  MISO,
  SS
);



  input  wire                       clk;
  input  wire                       rst_n;
  output wire [`REG_ADDR_WIDTH-1:0] wr_addr;
  output reg                        wr_en;
  output wire [`REG_SIZE-1:0]       wr_data;
  output wire [`REG_ADDR_WIDTH-1:0] rd_addr;
  output reg                        rd_en;
  input  wire [`REG_SIZE-1:0]       rd_data;
  input  wire                       clr_err;
  input  wire [`BURST_WIDTH-1:0]    wr_burst_size;
  input  wire [`BURST_WIDTH-1:0]    rd_burst_size;
  
  input  wire                       SCLK;
  input  wire                       MOSI;
  output wire                       MISO;
  input  wire                       SS;


  localparam [2:0]                  IDLE      = 3'b000;
  localparam [2:0]                  SPI_ADDR  = 3'b001; 
  localparam [2:0]                  ADDR_DONE = 3'b010;
  localparam [2:0]                  READ_ADDR = 3'b011;
  localparam [2:0]                  WRITE_REG = 3'b100;
  localparam [2:0]                  READ_REG  = 3'b101;
                                    
  localparam [2:0]                  SCLK_IDLE = 3'b000;
  localparam [2:0]                  SCLK_HIGH = 3'b001; 
  localparam [2:0]                  SCLK_LOW  = 3'b010;
  localparam [2:0]                  SCLK_POL_ERR = 3'b011;
  
  reg [2:0]                         rx_data_cnt;
  reg [2:0]                         tx_data_cnt;
  reg [`DATA_LENGTH-1:0]            rx_shift_data;
  reg [`DATA_LENGTH-1:0]            rx_byte;
                                    
  reg                               rx_done;
  reg                               rx_done_d1;
  reg                               rx_done_d2;
  wire                              byte_rx_done_pulse;
  reg                               byte_rx_done_pulse_d1;

  reg                               tx_done;
  reg                               tx_done_d1;
  reg                               tx_done_d2;
  wire                              byte_tx_done_pulse;
  reg                               byte_tx_done_pulse_d1;
  
  reg [2:0]                         c_state;
  reg [2:0]                         n_state;
                                    
  reg                               rd_addr_done;
  reg                               cs_d1;
  reg                               cs_d2;
  reg                               sclk_d1;
  reg                               sclk_d2;
  reg                               sclk_d3;
  wire                              sclk_sync_fe;
  reg                               mosi_d1;
  reg                               mosi_d2;
  reg                               address_done;
  reg                               miso_i;
  wire                              burst_done;
  wire                              burst_done_d1;
  wire                              rd_wr_done;
  wire                              clr_rd_on;
  wire                              rd_done;
  wire                              wr_done;
  wire                              rd_wr_done_d1;
  reg  [15:0]                       burst_cntr;
  reg  [7:0]                        sclk_low_cntr;
  reg                               rd_on;
  wire                              sclk_stable;
  wire                              sclk_low_cntr_done;
  reg  [`REG_ADDR_WIDTH-1:0]        addr;
  wire [`BURST_WIDTH-1:0]           burst_size;
  reg [1:0]                         sclk_c_state;
  reg [1:0]                         sclk_n_state;
  reg [15:0]                        dbg_rd_burst_size_cntr;
  reg [15:0]                        dbg_lch_rd_burst_size_cntr;
  wire                              clr_dbg_cntr;




  always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      sclk_d1 <= 1'b1;
      sclk_d2 <= 1'b1;
      mosi_d1 <= 1'b1;
      mosi_d2 <= 1'b1;
    end else begin
      sclk_d1 <= SCLK;
      sclk_d2 <= sclk_d1;
      sclk_d3 <= sclk_d2;
      mosi_d1 <= MOSI;
      mosi_d2 <= mosi_d1;
    end
  end
  
  assign sclk_sync_fe = (!sclk_d1) & sclk_d2;
  
  /
  assign burst_done_d1 = burst_done;
  assign rd_wr_done = cs_d2 & burst_done_d1 ? 1'b1 : 1'b0;

  assign rd_wr_done_d1 = rd_wr_done;

  assign wr_data = rx_byte;
  
endmodule