data/full_repos/permissive/464128338/SD-card-SPI-to-speaker-verilog-program/src/Enable_generation.v
data/verilator_xmls/0f50287e-f528-4a07-8cb2-b0a52a643301.xml
module Enable_generation(
         output reg CS, Data_Out, CLK,
         output reg Init_Data_In, CMD18_Data_In,       
         input Data_In, Init_pass,         
         input Init_CS,  Init_Data_Out,  Init_CLK,       
         input CMD18_CS, CMD18_Data_Out, CMD18_CLK,
         input Clock_100MHz, Clear_n
       );
       
      
  always@(posedge Clock_100MHz, negedge Clear_n)
    if(!Clear_n) 
      begin 
        CS <= 1; Data_Out <= 1; CLK <= 0;
        Init_Data_In <= 1; CMD18_Data_In <= 1; 
      end  
    else if(Init_pass)
      begin
        CS <= CMD18_CS; Data_Out <= CMD18_Data_Out; CLK <= CMD18_CLK; 
        CMD18_Data_In <= Data_In; Init_Data_In <= 1; 
      end
    else
      begin
        CS <= Init_CS; Data_Out <= Init_Data_Out; CLK <= Init_CLK; 
        Init_Data_In <= Data_In; CMD18_Data_In <= 1;
      end 
      
endmodule
module Enable_generation(
         output reg CS, Data_Out, CLK,
         output reg Init_Data_In, CMD18_Data_In,       
         input Data_In, Init_pass,         
         input Init_CS,  Init_Data_Out,  Init_CLK,       
         input CMD18_CS, CMD18_Data_Out, CMD18_CLK,
         input Clock_100MHz, Clear_n
       );

       
      
  always@(posedge Clock_100MHz, negedge Clear_n)
    if(!Clear_n) 
      begin 
        CS <= 1; Data_Out <= 1; CLK <= 0;
        Init_Data_In <= 1; CMD18_Data_In <= 1; 
      end  
    else if(Init_pass)
      begin
        CS <= CMD18_CS; Data_Out <= CMD18_Data_Out; CLK <= CMD18_CLK; 
        CMD18_Data_In <= Data_In; Init_Data_In <= 1; 
      end
    else
      begin
        CS <= Init_CS; Data_Out <= Init_Data_Out; CLK <= Init_CLK; 
        Init_Data_In <= Data_In; CMD18_Data_In <= 1;
      end 
      
endmodule