data/full_repos/permissive/446939020/risc-v/design.sv
1: b'%Error: data/full_repos/permissive/446939020/risc-v/design.sv:1: Cannot find include file: next_pc.v\n`include "next_pc.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/446939020/risc-v,data/full_repos/permissive/446939020/next_pc.v\n             data/full_repos/permissive/446939020/risc-v,data/full_repos/permissive/446939020/next_pc.v.v\n             data/full_repos/permissive/446939020/risc-v,data/full_repos/permissive/446939020/next_pc.v.sv\n             next_pc.v\n             next_pc.v.v\n             next_pc.v.sv\n             obj_dir/next_pc.v\n             obj_dir/next_pc.v.v\n             obj_dir/next_pc.v.sv\n%Error: data/full_repos/permissive/446939020/risc-v/design.sv:2: Cannot find include file: inst_mem.v\n`include "inst_mem.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/446939020/risc-v/design.sv:3: Cannot find include file: cont_unit.v\n`include "cont_unit.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/446939020/risc-v/design.sv:4: Cannot find include file: inst_fet.v\n`include "inst_fet.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/446939020/risc-v/design.sv:5: Cannot find include file: sign_extend.v\n`include "sign_extend.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/446939020/risc-v/design.sv:6: Cannot find include file: adr_gen.v\n`include "adr_gen.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/446939020/risc-v/design.sv:7: Cannot find include file: reg_fil.v\n`include "reg_fil.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/446939020/risc-v/design.sv:8: Cannot find include file: mux2.v\n`include "mux2.v" \n         ^~~~~~~~\n%Error: data/full_repos/permissive/446939020/risc-v/design.sv:9: Cannot find include file: mux22.v\n`include "mux22.v" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/446939020/risc-v/design.sv:10: Cannot find include file: alu.v\n`include "alu.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/446939020/risc-v/design.sv:11: Cannot find include file: dat_mem.v\n`include "dat_mem.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/446939020/risc-v/design.sv:12: Cannot find include file: pipe1.v\n`include "pipe1.v" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/446939020/risc-v/design.sv:13: Cannot find include file: pipe2.v\n`include "pipe2.v" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/446939020/risc-v/design.sv:14: Cannot find include file: pipe3.v\n`include "pipe3.v" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/446939020/risc-v/design.sv:15: Cannot find include file: pipe4.v\n`include "pipe4.v" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/446939020/risc-v/design.sv:16: Cannot find include file: hazard_unit.v\n`include "hazard_unit.v" \n         ^~~~~~~~~~~~~~~\n%Error: Exiting due to 16 error(s)\n'
module Top_Module(input clk,reset);
	
  reg [1:0]immsrc;
  reg [3:0]ALU_Sel;
  reg [1:0]Resultsrc;
  reg regWrite,PCSrc,ALUsrc,MemWrite,Branch,Jump;
  reg [31:0]pc;
  reg [31:0]PCnext;
  reg [31:0] instruction;
  reg [31:0]PCplus4;
  reg [24:0]sign_ext;
  reg [4:0]addR1,addR2,dest_reg;
  reg [31:0] tot_inst;
  reg [31:0]immext;
  reg [31:0]Din;
  reg [31:0]Port_A;
  reg [31:0]Port_B; 
  reg [31:0]y; 
  reg [31:0] ALU_Out;
  reg CarryOut,ZeroOut;
  reg [31:0] Data_Out;
  reg [31:0]PCTarget;
  
  
  
  reg StallD,StallF,FlushE,FlushD;
  

  

  assign PCnext = PCSrc ? PCTarget : PCplus4;
  


  next_pc m1(pc,PCnext ,clk, reset,StallF);
  
  
 


  
  assign PCplus4=pc+32'h4;

  
  
   


  Instruction_Memory m2(pc,instruction);
  


  reg [31:0] PCplus41,PCnext1,instruction1;
  reg1 r1(PCplus41,PCnext1,instruction1,PCplus4,PCnext,instruction,reset,clk,StallD,FlushD); 
  


  


  Instruction_fetch m4(instruction1,addR1,addR2,dest_reg,sign_ext,tot_inst);
  
  



  control_unit m3(instruction1, regWrite, immsrc, ALUsrc, MemWrite, Resultsrc, Branch, ALU_Sel, Jump,reset);

     


  
  reg [4:0]dest_reg4;
  reg regWrite4;
  register_file m7(Port_A, Port_B, Din, addR1, addR2, dest_reg4, regWrite4,clk,reset);




  extend m5(sign_ext,immsrc,immext);
  
 











  
  
  reg [31:0] PCplus42,PCnext2,immext2,Port_A2, Port_B2; 
  reg [4:0]dest_reg2;
  reg regWrite2, ALUsrc2, MemWrite2, Branch2, Jump2;
  reg [3:0]ALU_Sel2;
  reg [1:0]Resultsrc2;
  reg [4:0]Rs1E,Rs2E;
  
  reg2 r2(PCplus42,PCnext2,immext2,Port_A2, Port_B2, 
          dest_reg2, 
          regWrite2, ALUsrc2, MemWrite2, Branch2, Jump2,
          ALU_Sel2, 
          Resultsrc2,
          Rs1E,Rs2E,
          
            
          PCplus41,PCnext1,immext,Port_A, Port_B, 
          dest_reg, 
          reset,clk, 
          regWrite, ALUsrc, MemWrite, Branch, Jump,
          ALU_Sel,
          Resultsrc,
         addR1,addR2,
         FlushE);
  

  
  reg [1:0]ForwardAE,ForwardBE;
  reg [31:0]ALU_inp1,ALU_inp2,ALU_Out3;
  
  mux22 m12(Port_A2,Din,ALU_Out3,ForwardAE,ALU_inp1);
  mux22 m18(Port_B2,Din,ALU_Out3,ForwardBE,ALU_inp2);
  
  


  mux2 m8(ALU_inp2,immext2,ALUsrc2,y);
  
  assign PCTarget=immext2+PCnext2;
  
  


  alu m9(ALU_inp1,y,ALU_Sel2,ALU_Out,CarryOut,ZeroOut);
  

  assign PCSrc=(ZeroOut && Branch2) || Jump2;

  
  
  
  
  





  





  
  reg [31:0] PCplus43, Port_B3; 
  reg [4:0]dest_reg3;
  reg regWrite3, MemWrite3;
  reg [1:0]Resultsrc3; 
            
  reg3 r3(PCplus43, Port_B3, ALU_Out3,
         dest_reg3,
         regWrite3, MemWrite3,
         Resultsrc3,
         PCplus42, Port_B2, ALU_Out,
         dest_reg2,
         reset,clk,
         regWrite2, MemWrite2,
         Resultsrc2);
  

  
  

  



  Data_Memory m10(Data_Out,ALU_Out3,Port_B3,MemWrite3,reset,clk);
  
  
  




            





  
  
  reg [31:0] PCplus44, Data_Out4, ALU_Out4;
  
  
  reg [1:0]Resultsrc4;
  
  reg4 r4(PCplus44, Data_Out4, ALU_Out4, 	
          dest_reg4, 
          regWrite4,
          Resultsrc4,
          PCplus43, Data_Out, ALU_Out3,
          dest_reg3,
          reset,clk,
          regWrite3,
          Resultsrc3);
  
  
  

  
  


  mux22 m11(ALU_Out4,Data_Out4,PCplus44,Resultsrc4,Din);

  
  

  
  hazard h1(Rs1E,Rs2E,dest_reg3,dest_reg4, 
             regWrite3,regWrite4,
            Resultsrc2[0],
             addR1,addR2,dest_reg2,
             PCSrc,reset,
             StallD,StallF,FlushE,FlushD,
             ForwardAE,ForwardBE);
endmodule
module Top_Module(input clk,reset);

	
  reg [1:0]immsrc;
  reg [3:0]ALU_Sel;
  reg [1:0]Resultsrc;
  reg regWrite,PCSrc,ALUsrc,MemWrite,Branch,Jump;
  reg [31:0]pc;
  reg [31:0]PCnext;
  reg [31:0] instruction;
  reg [31:0]PCplus4;
  reg [24:0]sign_ext;
  reg [4:0]addR1,addR2,dest_reg;
  reg [31:0] tot_inst;
  reg [31:0]immext;
  reg [31:0]Din;
  reg [31:0]Port_A;
  reg [31:0]Port_B; 
  reg [31:0]y; 
  reg [31:0] ALU_Out;
  reg CarryOut,ZeroOut;
  reg [31:0] Data_Out;
  reg [31:0]PCTarget;
  
  
  
  reg StallD,StallF,FlushE,FlushD;
  

  

  assign PCnext = PCSrc ? PCTarget : PCplus4;
  


  next_pc m1(pc,PCnext ,clk, reset,StallF);
  
  
 


  
  assign PCplus4=pc+32'h4;

  
  
   


  Instruction_Memory m2(pc,instruction);
  


  reg [31:0] PCplus41,PCnext1,instruction1;
  reg1 r1(PCplus41,PCnext1,instruction1,PCplus4,PCnext,instruction,reset,clk,StallD,FlushD); 
  


  


  Instruction_fetch m4(instruction1,addR1,addR2,dest_reg,sign_ext,tot_inst);
  
  



  control_unit m3(instruction1, regWrite, immsrc, ALUsrc, MemWrite, Resultsrc, Branch, ALU_Sel, Jump,reset);

     


  
  reg [4:0]dest_reg4;
  reg regWrite4;
  register_file m7(Port_A, Port_B, Din, addR1, addR2, dest_reg4, regWrite4,clk,reset);




  extend m5(sign_ext,immsrc,immext);
  
 











  
  
  reg [31:0] PCplus42,PCnext2,immext2,Port_A2, Port_B2; 
  reg [4:0]dest_reg2;
  reg regWrite2, ALUsrc2, MemWrite2, Branch2, Jump2;
  reg [3:0]ALU_Sel2;
  reg [1:0]Resultsrc2;
  reg [4:0]Rs1E,Rs2E;
  
  reg2 r2(PCplus42,PCnext2,immext2,Port_A2, Port_B2, 
          dest_reg2, 
          regWrite2, ALUsrc2, MemWrite2, Branch2, Jump2,
          ALU_Sel2, 
          Resultsrc2,
          Rs1E,Rs2E,
          
            
          PCplus41,PCnext1,immext,Port_A, Port_B, 
          dest_reg, 
          reset,clk, 
          regWrite, ALUsrc, MemWrite, Branch, Jump,
          ALU_Sel,
          Resultsrc,
         addR1,addR2,
         FlushE);
  

  
  reg [1:0]ForwardAE,ForwardBE;
  reg [31:0]ALU_inp1,ALU_inp2,ALU_Out3;
  
  mux22 m12(Port_A2,Din,ALU_Out3,ForwardAE,ALU_inp1);
  mux22 m18(Port_B2,Din,ALU_Out3,ForwardBE,ALU_inp2);
  
  


  mux2 m8(ALU_inp2,immext2,ALUsrc2,y);
  
  assign PCTarget=immext2+PCnext2;
  
  


  alu m9(ALU_inp1,y,ALU_Sel2,ALU_Out,CarryOut,ZeroOut);
  

  assign PCSrc=(ZeroOut && Branch2) || Jump2;

  
  
  
  
  





  





  
  reg [31:0] PCplus43, Port_B3; 
  reg [4:0]dest_reg3;
  reg regWrite3, MemWrite3;
  reg [1:0]Resultsrc3; 
            
  reg3 r3(PCplus43, Port_B3, ALU_Out3,
         dest_reg3,
         regWrite3, MemWrite3,
         Resultsrc3,
         PCplus42, Port_B2, ALU_Out,
         dest_reg2,
         reset,clk,
         regWrite2, MemWrite2,
         Resultsrc2);
  

  
  

  



  Data_Memory m10(Data_Out,ALU_Out3,Port_B3,MemWrite3,reset,clk);
  
  
  




            





  
  
  reg [31:0] PCplus44, Data_Out4, ALU_Out4;
  
  
  reg [1:0]Resultsrc4;
  
  reg4 r4(PCplus44, Data_Out4, ALU_Out4, 	
          dest_reg4, 
          regWrite4,
          Resultsrc4,
          PCplus43, Data_Out, ALU_Out3,
          dest_reg3,
          reset,clk,
          regWrite3,
          Resultsrc3);
  
  
  

  
  


  mux22 m11(ALU_Out4,Data_Out4,PCplus44,Resultsrc4,Din);

  
  

  
  hazard h1(Rs1E,Rs2E,dest_reg3,dest_reg4, 
             regWrite3,regWrite4,
            Resultsrc2[0],
             addR1,addR2,dest_reg2,
             PCSrc,reset,
             StallD,StallF,FlushE,FlushD,
             ForwardAE,ForwardBE);
endmodule