data/full_repos/permissive/493441306/Verilog Language/modules_hierarchy/07_modulecseladd.v
1: b'%Error: Cannot find file containing module: Language/modules_hierarchy,data/full_repos/permissive/493441306\n        ... Looked in:\n             data/full_repos/permissive/493441306/Verilog/Language/modules_hierarchy,data/full_repos/permissive/493441306\n             data/full_repos/permissive/493441306/Verilog/Language/modules_hierarchy,data/full_repos/permissive/493441306.v\n             data/full_repos/permissive/493441306/Verilog/Language/modules_hierarchy,data/full_repos/permissive/493441306.sv\n             Language/modules_hierarchy,data/full_repos/permissive/493441306\n             Language/modules_hierarchy,data/full_repos/permissive/493441306.v\n             Language/modules_hierarchy,data/full_repos/permissive/493441306.sv\n             obj_dir/Language/modules_hierarchy,data/full_repos/permissive/493441306\n             obj_dir/Language/modules_hierarchy,data/full_repos/permissive/493441306.v\n             obj_dir/Language/modules_hierarchy,data/full_repos/permissive/493441306.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/493441306/Verilog\n%Error: Cannot find file containing module: Language/modules_hierarchy/07_modulecseladd.v\n%Error: Exiting due to 3 error(s)\n'
module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    wire sel;
    wire [15:0] sumH0, sumH1;
    
    add16 addL (.a(a[15:0]), .b(b[15:0]), .cout(sel), .sum(sum[15:0]) );
    add16 addH0 (.a(a[31:16]), .b(b[31:16]), .cin(0), .sum(sumH0) );
    add16 addH1 (.a(a[31:16]), .b(b[31:16]), .cin(1), .sum(sumH1) );
    
    assign sum[31:16] = (sel) ? sumH1 : sumH0;

endmodule
module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);

    wire sel;
    wire [15:0] sumH0, sumH1;
    
    add16 addL (.a(a[15:0]), .b(b[15:0]), .cout(sel), .sum(sum[15:0]) );
    add16 addH0 (.a(a[31:16]), .b(b[31:16]), .cin(0), .sum(sumH0) );
    add16 addH1 (.a(a[31:16]), .b(b[31:16]), .cin(1), .sum(sumH1) );
    
    assign sum[31:16] = (sel) ? sumH1 : sumH0;

endmodule