data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_ibus.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_ibus.sv:14: Unsupported: Ignoring delay on this delayed statement.\n forever #(0.5) clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_ibus.sv:23: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_ibus.sv:25: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Error: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_ibus.sv:35: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_ibus.sv:36: Unsupported: Ignoring delay on this delayed statement.\n  #0.1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_ibus.sv:43: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_ibus.sv:50: Unsupported: Ignoring delay on this delayed statement.\n #4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_ibus.sv:53: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_ibus.sv:71: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tb.lxt");   \n ^~~~~~~~~\n%Error: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_ibus.sv:72: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, test);    \n ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_ibus();

parameter DW=16;
parameter AW=16;

logic clk,rst;
logic [DW-1:0]dout;
logic [AW-1:0]addr;


initial begin
	clk = '0;
	forever #(0.5) clk = ~clk;
end


task sysrst;
	input rstb;
begin
	rst <= rstb;
	addr <= 0;
	#2;
	rst <= ~rstb;
	#2;
end
endtask : sysrst



task read_d;
	input [AW-1:0]r_addr;
	begin
		addr=r_addr;
		@(posedge clk);
		#0.1;
	end
endtask : read_d


initial begin
	sysrst(1);
	#1;
	read_d(16'h0);
	read_d(16'h1);
	read_d(16'h2);
	read_d(16'h3);
	read_d(16'h0);
	read_d(16'h1);
	#4;
	read_d(16'h1);
	$display("|--------Yduck ibus pass---------|");
	#10
	$finish;
end


ibus #(
	.DW     		( 16 		),
	.AW     		( 16 		),
	.RAM_AW 		( 7  		))
	test (

	.clk  		( clk  		),
	.addr 		( addr 		),
	.dout 		( dout 		)
);


initial begin
	$dumpfile("tb.lxt");
	$dumpvars(0, test);
end

endmodule
module tb_ibus();


parameter DW=16;
parameter AW=16;

logic clk,rst;
logic [DW-1:0]dout;
logic [AW-1:0]addr;


initial begin
	clk = '0;
	forever #(0.5) clk = ~clk;
end


task sysrst;
	input rstb;
begin
	rst <= rstb;
	addr <= 0;
	#2;
	rst <= ~rstb;
	#2;
end
endtask : sysrst



task read_d;
	input [AW-1:0]r_addr;
	begin
		addr=r_addr;
		@(posedge clk);
		#0.1;
	end
endtask : read_d


initial begin
	sysrst(1);
	#1;
	read_d(16'h0);
	read_d(16'h1);
	read_d(16'h2);
	read_d(16'h3);
	read_d(16'h0);
	read_d(16'h1);
	#4;
	read_d(16'h1);
	$display("|--------Yduck ibus pass---------|");
	#10
	$finish;
end


ibus #(
	.DW     		( 16 		),
	.AW     		( 16 		),
	.RAM_AW 		( 7  		))
	test (

	.clk  		( clk  		),
	.addr 		( addr 		),
	.dout 		( dout 		)
);


initial begin
	$dumpfile("tb.lxt");
	$dumpvars(0, test);
end

endmodule