data/full_repos/permissive/435885222/sources/id_ex.v
data/verilator_xmls/b5294790-29a8-46da-9377-20f0340775f9.xml
module id_ex(
    input clk,
    input rst,
    input [7:0] id_aluop,
    input [2:0] id_alusel,
    input [31:0] id_reg1,
    input [31:0] id_reg2,
    input [4:0] id_wd,
    input id_wreg,
    input [31:0] id_link_address,
    input [31:0] id_inst,
    output reg[7:0] ex_aluop,
    output reg[2:0] ex_alusel,
    output reg[31:0] ex_reg1,
    output reg[31:0] ex_reg2,
    output reg[4:0] ex_wd,
    output reg ex_wreg,
    output reg[31:0] ex_link_address,
    output reg[31:0] ex_inst
    );
    always @(posedge clk)begin
        if(rst==1'b1)begin
            ex_aluop<=8'b00000000;
            ex_alusel<=3'b000;
            ex_reg1<=32'h00000000;
            ex_reg2<=32'h00000000;
            ex_wd<=5'b00000;
            ex_wreg<=1'b0;
            ex_link_address<=32'h00000000;
            ex_inst<=32'h00000000;
        end else begin
            ex_aluop<=id_aluop;
            ex_alusel<=id_alusel;
            ex_reg1<=id_reg1;
            ex_reg2<=id_reg2;
            ex_wd<=id_wd;
            ex_wreg<=id_wreg;
            ex_link_address<=id_link_address;
            ex_inst<=id_inst;
        end
    end
endmodule
module id_ex(
    input clk,
    input rst,
    input [7:0] id_aluop,
    input [2:0] id_alusel,
    input [31:0] id_reg1,
    input [31:0] id_reg2,
    input [4:0] id_wd,
    input id_wreg,
    input [31:0] id_link_address,
    input [31:0] id_inst,
    output reg[7:0] ex_aluop,
    output reg[2:0] ex_alusel,
    output reg[31:0] ex_reg1,
    output reg[31:0] ex_reg2,
    output reg[4:0] ex_wd,
    output reg ex_wreg,
    output reg[31:0] ex_link_address,
    output reg[31:0] ex_inst
    );

    always @(posedge clk)begin
        if(rst==1'b1)begin
            ex_aluop<=8'b00000000;
            ex_alusel<=3'b000;
            ex_reg1<=32'h00000000;
            ex_reg2<=32'h00000000;
            ex_wd<=5'b00000;
            ex_wreg<=1'b0;
            ex_link_address<=32'h00000000;
            ex_inst<=32'h00000000;
        end else begin
            ex_aluop<=id_aluop;
            ex_alusel<=id_alusel;
            ex_reg1<=id_reg1;
            ex_reg2<=id_reg2;
            ex_wd<=id_wd;
            ex_wreg<=id_wreg;
            ex_link_address<=id_link_address;
            ex_inst<=id_inst;
        end
    end
endmodule