data/full_repos/permissive/423958267/lab01/lab01.srcs/sources_1/new/lab01.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/423958267/lab01/lab01.srcs/sources_1/new/lab01.v:39: Multiple top level modules\n                                                                                                 : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                 : ... Top module \'full_adder\'\nmodule full_adder(\n       ^~~~~~~~~~\n                                                                                                 : ... Top module \'full_adder2\'\nmodule full_adder2(cout, s, a, b, cin);\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/423958267/lab01/lab01.srcs/sources_1/new/lab01.v:31: Duplicate declaration of signal: \'cout\'\n                                                                                      : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n    reg cout, s;\n        ^~~~\n        data/full_repos/permissive/423958267/lab01/lab01.srcs/sources_1/new/lab01.v:24: ... Location of original declaration\n    output cout,\n           ^~~~\n%Error: data/full_repos/permissive/423958267/lab01/lab01.srcs/sources_1/new/lab01.v:31: Duplicate declaration of signal: \'s\'\n    reg cout, s;\n              ^\n        data/full_repos/permissive/423958267/lab01/lab01.srcs/sources_1/new/lab01.v:25: ... Location of original declaration\n    output s,\n           ^\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module full_adder(
    output cout,
    output s,
    input a,
    input b,
    input cin
);

    reg cout, s;

    always@(a, b, cin)
    begin
        {cout, s} = a + b + cin;
    end
endmodule
module full_adder(
    output cout,
    output s,
    input a,
    input b,
    input cin
);


    reg cout, s;

    always@(a, b, cin)
    begin
        {cout, s} = a + b + cin;
    end
endmodule