data/full_repos/permissive/4847981/td4.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/4847981/td4.v:110: Signal definition not found, creating implicitly: \'loadA\'\n Register regA (aluOut, regAOut, loadA, ZERO, CLK);\n                                 ^~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/4847981/td4.v:113: Signal definition not found, creating implicitly: \'loadB\'\n                                                               : ... Suggested alternative: \'loadA\'\n Register regB (aluOut, regBOut, loadB, ZERO, CLK);\n                                 ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/4847981/td4.v:116: Signal definition not found, creating implicitly: \'loadC\'\n                                                               : ... Suggested alternative: \'loadA\'\n Register out (aluOut, OUT, loadC, ZERO, CLK);\n                            ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/4847981/td4.v:119: Signal definition not found, creating implicitly: \'loadD\'\n                                                               : ... Suggested alternative: \'loadA\'\n Register pc (aluOut, MEM_ADDR, loadD, ONE, CLK);\n                                ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/4847981/td4.v:125: Signal definition not found, creating implicitly: \'carryIn\'\n FlipFlop carry(carryIn, carryOut, ZERO[3:0], CLK);\n                ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/4847981/td4.v:125: Signal definition not found, creating implicitly: \'carryOut\'\n FlipFlop carry(carryIn, carryOut, ZERO[3:0], CLK);\n                         ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/4847981/td4.v:110: Input port connection \'COUNTUP\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'ZERO\' generates 4 bits.\n                                                            : ... In instance td4\n Register regA (aluOut, regAOut, loadA, ZERO, CLK);\n                                        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/4847981/td4.v:113: Input port connection \'COUNTUP\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'ZERO\' generates 4 bits.\n                                                            : ... In instance td4\n Register regB (aluOut, regBOut, loadB, ZERO, CLK);\n                                        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/4847981/td4.v:116: Input port connection \'COUNTUP\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'ZERO\' generates 4 bits.\n                                                            : ... In instance td4\n Register out (aluOut, OUT, loadC, ZERO, CLK);\n                                   ^~~~\n%Warning-WIDTH: data/full_repos/permissive/4847981/td4.v:119: Input port connection \'COUNTUP\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'ONE\' generates 4 bits.\n                                                            : ... In instance td4\n Register pc (aluOut, MEM_ADDR, loadD, ONE, CLK);\n                                       ^~~\n%Warning-WIDTH: data/full_repos/permissive/4847981/td4.v:125: Input port connection \'LOAD\' expects 1 bits on the pin connection, but pin connection\'s SEL generates 4 bits.\n                                                            : ... In instance td4\n FlipFlop carry(carryIn, carryOut, ZERO[3:0], CLK);\n                                       ^\n%Error: Exiting due to 11 warning(s)\n'
module ALU(
	input [3:0] A,
	input [3:0] B,
	output [3:0] OUT,
	output CARRY
);

	assign {CARRY, OUT}=A+B;
endmodule
module ALU(
	input [3:0] A,
	input [3:0] B,
	output [3:0] OUT,
	output CARRY
);


	assign {CARRY, OUT}=A+B;
endmodule