data/full_repos/permissive/528047272/bench/tb_top.v
1: b'%Error: data/full_repos/permissive/528047272/bench/tb_top.v:2: Cannot find include file: ../rtl/risc_v_core.v\n`include "../rtl/risc_v_core.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/528047272/bench,data/full_repos/permissive/528047272/../rtl/risc_v_core.v\n             data/full_repos/permissive/528047272/bench,data/full_repos/permissive/528047272/../rtl/risc_v_core.v.v\n             data/full_repos/permissive/528047272/bench,data/full_repos/permissive/528047272/../rtl/risc_v_core.v.sv\n             ../rtl/risc_v_core.v\n             ../rtl/risc_v_core.v.v\n             ../rtl/risc_v_core.v.sv\n             obj_dir/../rtl/risc_v_core.v\n             obj_dir/../rtl/risc_v_core.v.v\n             obj_dir/../rtl/risc_v_core.v.sv\n%Error: data/full_repos/permissive/528047272/bench/tb_top.v:11: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/528047272/bench/tb_top.v:12: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module tb_top;

risc_v_core risc_v_core_tb (.*);

initial begin
  $dumpvars;
  `TIME_SIM;
  $finish;
end

endmodule
module tb_top;


risc_v_core risc_v_core_tb (.*);

initial begin
  $dumpvars;
  `TIME_SIM;
  $finish;
end

endmodule