data/full_repos/permissive/425166201/02_ps2timing/keyboard.v
data/verilator_xmls/0acf998a-f478-4894-ba37-94ddb9ce38c4.xml
module keyboard
(
    input   wire        clock_25,
    inout   wire        PS2_CLK,
    inout   wire        PS2_DAT,
    output  reg         keyb_ready,
    output  reg [7:0]   keyb_data
);





reg         state;
reg [ 9:0]  data;
reg [ 3:0]  cnt;
reg [ 1:0]  k;





always @(negedge clock_25) begin

    keyb_ready <= 1'b0;

    case (state)


    0: if (k == 2'b10) begin state <= 1'b1; cnt <= 0; end


    1: if (k == 2'b01) begin



        if (cnt == 10) begin




            state       <= 1'b0;
            keyb_ready  <= (PS2_DAT == 1'b1) && (data[0] == 1'b0);
            keyb_data   <= data[8:1];

        end


        data  <= {PS2_DAT, data[9:1]};
        cnt   <= cnt + 1;

    end

    endcase

    k <= {k[0], PS2_CLK};

end

endmodule
module keyboard
(
    input   wire        clock_25,
    inout   wire        PS2_CLK,
    inout   wire        PS2_DAT,
    output  reg         keyb_ready,
    output  reg [7:0]   keyb_data
);






reg         state;
reg [ 9:0]  data;
reg [ 3:0]  cnt;
reg [ 1:0]  k;





always @(negedge clock_25) begin

    keyb_ready <= 1'b0;

    case (state)


    0: if (k == 2'b10) begin state <= 1'b1; cnt <= 0; end


    1: if (k == 2'b01) begin



        if (cnt == 10) begin




            state       <= 1'b0;
            keyb_ready  <= (PS2_DAT == 1'b1) && (data[0] == 1'b0);
            keyb_data   <= data[8:1];

        end


        data  <= {PS2_DAT, data[9:1]};
        cnt   <= cnt + 1;

    end

    endcase

    k <= {k[0], PS2_CLK};

end

endmodule