data/full_repos/permissive/46132596/processor/SingleCycleDatapath/Adder4.v
data/verilator_xmls/d36a9227-6f02-41ee-aa40-105e4675a4f0.xml
module Adder4(input[31:0] in,
		output[31:0] out);

	assign out = in + 4;
endmodule
module Adder4(input[31:0] in,
		output[31:0] out);


	assign out = in + 4;
endmodule