data/full_repos/permissive/51625123/src/vga.v
1: b'%Error: data/full_repos/permissive/51625123/src/vga.v:47: Unsupported: wand\nwand RED;\n^~~~\n%Error: data/full_repos/permissive/51625123/src/vga.v:48: Unsupported: wand\nwand GREEN;\n^~~~\n%Error: data/full_repos/permissive/51625123/src/vga.v:49: Unsupported: wand\nwand BLUE;\n^~~~\n%Error: Exiting due to 3 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bgfill(clk, hsync, vsync, r, g, b);
	input clk, hsync, vsync;
	output r, g, b;
	reg ff1, ff2;
	always @(negedge clk) begin
		if (vsync)
			ff1 <= ~ff1;
		else ff1 <= 0;
	end
	always @(negedge hsync) begin
		if (vsync)
			ff2 <= ~ff2;
		else ff2 <= 0;
	end
	assign r = (1'b0 &  ~(ff1^ff2));
	assign g = (1'b0 & (ff1^ff2));
	assign b = (1'b1 & (ff1^ff2));
endmodule
module bgfill(clk, hsync, vsync, r, g, b);

	input clk, hsync, vsync;
	output r, g, b;
	reg ff1, ff2;
	always @(negedge clk) begin
		if (vsync)
			ff1 <= ~ff1;
		else ff1 <= 0;
	end
	always @(negedge hsync) begin
		if (vsync)
			ff2 <= ~ff2;
		else ff2 <= 0;
	end
	assign r = (1'b0 &  ~(ff1^ff2));
	assign g = (1'b0 & (ff1^ff2));
	assign b = (1'b1 & (ff1^ff2));
endmodule