data/full_repos/permissive/445357518/top.v
1: b"%Error: data/full_repos/permissive/445357518/top.v:42: Cannot find file containing module: 'cpu'\ncpu CPU(clk,reset,read_data,datapath_out,N,V,Z,mem_cmd,mem_addr);\n^~~\n        ... Looked in:\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/cpu\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/cpu.v\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/cpu.sv\n             cpu\n             cpu.v\n             cpu.sv\n             obj_dir/cpu\n             obj_dir/cpu.v\n             obj_dir/cpu.sv\n%Error: data/full_repos/permissive/445357518/top.v:72: Cannot find file containing module: 'vDFF1'\nvDFF1 #(8) LED_REG(clk, write_data[7:0], loadOut, LEDR[7:0]);\n^~~~~\n%Error: Exiting due to 2 error(s)\n"
module RAM(clk,read_address,write_address,write,din,dout);
  parameter data_width = 32; 
  parameter addr_width = 4;
  parameter filename = "data.txt";

  input clk;
  input [addr_width-1:0] read_address, write_address;
  input write;
  input [data_width-1:0] din;
  output [data_width-1:0] dout;
  reg [data_width-1:0] dout;

  reg [data_width-1:0] mem [2**addr_width-1:0];

  initial $readmemb(filename, mem);


  always @ (posedge clk) begin
    if (write)
      mem[write_address] <= din;
    dout <= mem[read_address];

  end 
endmodule
module RAM(clk,read_address,write_address,write,din,dout);

  parameter data_width = 32; 
  parameter addr_width = 4;
  parameter filename = "data.txt";

  input clk;
  input [addr_width-1:0] read_address, write_address;
  input write;
  input [data_width-1:0] din;
  output [data_width-1:0] dout;
  reg [data_width-1:0] dout;

  reg [data_width-1:0] mem [2**addr_width-1:0];

  initial $readmemb(filename, mem);


  always @ (posedge clk) begin
    if (write)
      mem[write_address] <= din;
    dout <= mem[read_address];

  end 
endmodule