data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v
1: b'%Error: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:19: Define or directive not defined: \'`round_max\'\n    recFNToIN#(8,24,32) maxxCiel2int(.control(1\'b0),.in(maxx),.roundingMode(`round_max),.signedOut(1\'b1),.out(maxx_int),.intExceptionFlags());\n                                                                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:20: Define or directive not defined: \'`round_min\'\n    recFNToIN#(8,24,32) minxFloor2int(.control(1\'b0),.in(minx),.roundingMode(`round_min),.signedOut(1\'b1),.out(minx_int),.intExceptionFlags());\n                                                                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:21: Define or directive not defined: \'`round_max\'\n    recFNToIN#(8,24,32) maxyCiel2int(.control(1\'b0),.in(maxy),.roundingMode(`round_max),.signedOut(1\'b1),.out(maxy_int),.intExceptionFlags());\n                                                                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:22: Define or directive not defined: \'`round_min\'\n    recFNToIN#(8,24,32) minyFloor2int(.control(1\'b0),.in(miny),.roundingMode(`round_min),.signedOut(1\'b1),.out(miny_int),.intExceptionFlags());\n                                                                             ^~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:110: Unsupported: Ignoring delay on this delayed statement.\n        #10 \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:114: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:120: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:124: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:130: Unsupported: Ignoring delay on this delayed statement.\n        #10 \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:134: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:140: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:144: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:150: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:154: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:160: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:164: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Error: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:169: Unsupported or unknown PLI call: $dumpfile\n            $dumpfile("limitBB_tb.vcd");\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:170: Unsupported or unknown PLI call: $dumpvars\n            $dumpvars(0,limitBB_tb);\n            ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:171: Unsupported: Ignoring delay on this delayed statement.\n            #1;\n            ^\n%Error: Exiting due to 6 error(s), 13 warning(s)\n'
module minmax(
    input wire [32:0] a,
    input wire [32:0] b,
    input wire [32:0] c,
    output reg [32:0] max,
    output reg [32:0] min
);
    wire altb, aeqb, agtb;
    wire altc, aeqc, agtc;
    wire bltc, beqc, bgtc;
    wire abUnordered, acUnordered, bcUnordered;
    compareRecFN#(8, 24) compareRecFNab (a,b,1'b0,altb,aeqb,agtb,abUnordered,);
    compareRecFN#(8, 24) compareRecFNac (a,c,1'b0,altc,aeqc,agtc,acUnordered,);
    compareRecFN#(8, 24) compareRecFNbc (b,c,1'b0,bltc,beqc,bgtc,bcUnordered,);

    wire bgta, cgta, cgtb;
    assign bgta = altb;
    assign cgta = altc;
    assign cgtb = bltc;

    always @(*) begin
        if ((agtb || aeqb) && (agtc || aeqc)) max = a;
        if ((bgtc || beqc) && (bgta || aeqb)) max = b;
        if ((cgta || aeqc) && (cgtb || beqc)) max = c;
    end

    wire clta, blta, cltb;
    assign clta = agtc;
    assign blta = agtb;
    assign cltb = bgtc;
    always @(*) begin
        if ((altb || aeqb) && (altc || aeqc)) min = a;
        if ((bltc || beqc) && (blta || aeqb)) min = b;
        if ((clta || aeqc) && (cltb || beqc)) min = c;
    end










          

endmodule
module minmax(
    input wire [32:0] a,
    input wire [32:0] b,
    input wire [32:0] c,
    output reg [32:0] max,
    output reg [32:0] min
);

    wire altb, aeqb, agtb;
    wire altc, aeqc, agtc;
    wire bltc, beqc, bgtc;
    wire abUnordered, acUnordered, bcUnordered;
    compareRecFN#(8, 24) compareRecFNab (a,b,1'b0,altb,aeqb,agtb,abUnordered,);
    compareRecFN#(8, 24) compareRecFNac (a,c,1'b0,altc,aeqc,agtc,acUnordered,);
    compareRecFN#(8, 24) compareRecFNbc (b,c,1'b0,bltc,beqc,bgtc,bcUnordered,);

    wire bgta, cgta, cgtb;
    assign bgta = altb;
    assign cgta = altc;
    assign cgtb = bltc;

    always @(*) begin
        if ((agtb || aeqb) && (agtc || aeqc)) max = a;
        if ((bgtc || beqc) && (bgta || aeqb)) max = b;
        if ((cgta || aeqc) && (cgtb || beqc)) max = c;
    end

    wire clta, blta, cltb;
    assign clta = agtc;
    assign blta = agtb;
    assign cltb = bgtc;
    always @(*) begin
        if ((altb || aeqb) && (altc || aeqc)) min = a;
        if ((bltc || beqc) && (blta || aeqb)) min = b;
        if ((clta || aeqc) && (cltb || beqc)) min = c;
    end










          

endmodule