data/full_repos/permissive/530059868/src/serial_load_lut_tt_tb.v
1: b'%Error: data/full_repos/permissive/530059868/src/serial_load_lut_tt_tb.v:31: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("dump.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/530059868/src/serial_load_lut_tt_tb.v:32: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(1, test);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/530059868/src/serial_load_lut_tt_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = 0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/530059868/src/serial_load_lut_tt_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #10 cs_n = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/530059868/src/serial_load_lut_tt_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #10 rot_n = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/530059868/src/serial_load_lut_tt_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_n = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/530059868/src/serial_load_lut_tt_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_n = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/530059868/src/serial_load_lut_tt_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_n = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/530059868/src/serial_load_lut_tt_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst_n = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/530059868/src/serial_load_lut_tt_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #10 cs_n = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/530059868/src/serial_load_lut_tt_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n   #10 cs_n = 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/530059868/src/serial_load_lut_tt_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n   #10 clk = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/530059868/src/serial_load_lut_tt_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n      #10 sel = ic;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/530059868/src/serial_load_lut_tt_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/530059868/src/serial_load_lut_tt_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #10 sel = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/530059868/src/serial_load_lut_tt_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n    #10 rot_n = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/530059868/src/serial_load_lut_tt_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n    #10 rot_n = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/530059868/src/serial_load_lut_tt_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n      #10 clk = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/530059868/src/serial_load_lut_tt_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n      #10 clk = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/530059868/src/serial_load_lut_tt_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n      #10 clk = 0;\n      ^\n%Error: Exiting due to 2 error(s), 18 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;
  reg [63:0] in;
  reg [3:0] sel;
  wire [7:0] out;
  reg clk;
  reg d;
  reg rst_n;
  reg cs_n;
  reg rot_n;
  

  wire [7:0] io_in;
  wire [7:0] io_out;
  
  assign io_in[0] = d;
  assign io_in[1] = clk;
  assign io_in[2] = rst_n;
  assign io_in[3] = cs_n;
  assign io_in[5:4] = sel[2:0];
  assign io_in[6] = rot_n;
  
  assign out[7:0] = io_out[7:0];
  
  
  user_module_1f985e14df1ed789231bb6e0189d6e39 lut(.io_in(io_in), .io_out(io_out));
  
  integer ic;
  
  initial begin

    $dumpfile("dump.vcd");
    $dumpvars(1, test);
    
    in = 64'h9876543210FEDCBA;
    
        
    #10 clk = 0;
    #10 cs_n = 1;
    #10 rot_n = 1;
    #10 rst_n = 1;
    #10 rst_n = 0;
    #10 rst_n = 1;
    #10 rst_n = 1;
    
    #10 cs_n = 0;
    
    for (ic = 63; ic >= 0; ic = ic - 1) begin
      d = in[ic];
      pulse_clk;
    end
  
  	#10 cs_n = 1;
  	#10 clk = 0;
    
    for (ic = 0; ic < 32; ic = ic + 1) begin
      #10 sel = ic;
    end
    
    #10 clk = 0;
    #10 sel = 0;
    
    #10 rot_n = 0;
    
    for (ic = 0; ic < 16; ic = ic + 1) begin
      pulse_clk;
    end
    
    #10 rot_n = 1;
    
    pulse_clk;
    pulse_clk;
    pulse_clk;
    
  end
  
  task pulse_clk;
    begin
      #10 clk = 0;
      #10 clk = 1;
      #10 clk = 0;
    end
  endtask
  
endmodule
module test;

  reg [63:0] in;
  reg [3:0] sel;
  wire [7:0] out;
  reg clk;
  reg d;
  reg rst_n;
  reg cs_n;
  reg rot_n;
  

  wire [7:0] io_in;
  wire [7:0] io_out;
  
  assign io_in[0] = d;
  assign io_in[1] = clk;
  assign io_in[2] = rst_n;
  assign io_in[3] = cs_n;
  assign io_in[5:4] = sel[2:0];
  assign io_in[6] = rot_n;
  
  assign out[7:0] = io_out[7:0];
  
  
  user_module_1f985e14df1ed789231bb6e0189d6e39 lut(.io_in(io_in), .io_out(io_out));
  
  integer ic;
  
  initial begin

    $dumpfile("dump.vcd");
    $dumpvars(1, test);
    
    in = 64'h9876543210FEDCBA;
    
        
    #10 clk = 0;
    #10 cs_n = 1;
    #10 rot_n = 1;
    #10 rst_n = 1;
    #10 rst_n = 0;
    #10 rst_n = 1;
    #10 rst_n = 1;
    
    #10 cs_n = 0;
    
    for (ic = 63; ic >= 0; ic = ic - 1) begin
      d = in[ic];
      pulse_clk;
    end
  
  	#10 cs_n = 1;
  	#10 clk = 0;
    
    for (ic = 0; ic < 32; ic = ic + 1) begin
      #10 sel = ic;
    end
    
    #10 clk = 0;
    #10 sel = 0;
    
    #10 rot_n = 0;
    
    for (ic = 0; ic < 16; ic = ic + 1) begin
      pulse_clk;
    end
    
    #10 rot_n = 1;
    
    pulse_clk;
    pulse_clk;
    pulse_clk;
    
  end
  
  task pulse_clk;
    begin
      #10 clk = 0;
      #10 clk = 1;
      #10 clk = 0;
    end
  endtask
  
endmodule