data/full_repos/permissive/437654144/width_convert/up_width_conv.v
1: b'%Warning-WIDTH: data/full_repos/permissive/437654144/width_convert/up_width_conv.v:96: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                     : ... In instance up_width_conv\n            temp_din   <= {DOUT_WIDTH{1\'b0}};\n                       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/437654144/width_convert/up_width_conv.v:97: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n                                                                                     : ... In instance up_width_conv\n            temp_strb  <= {DOUT_WIDTH/8{1\'b0}};\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/437654144/width_convert/up_width_conv.v:129: Operator EQ expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'data_cnt\' generates 2 bits.\n                                                                                      : ... In instance up_width_conv\n                        if ((data_cnt == WIDTH_RATIO - 1) || din_last || (temp_valid & temp_last)) begin\n                                      ^~\n%Error: Exiting due to 3 warning(s)\n'
function integer clog2;
        input integer value;
        integer i;
        begin
            clog2 = 0;
            for (i = 0; 2**i < value; i = i + 1) begin
                clog2 = i + 1;
            end
        end
    endfunction
function integer clog2;

        input integer value;
        integer i;
        begin
            clog2 = 0;
            for (i = 0; 2**i < value; i = i + 1) begin
                clog2 = i + 1;
            end
        end
    endfunction