data/full_repos/permissive/461069000/timer/src/timer.v
1: b"%Error: data/full_repos/permissive/461069000/timer/src/timer.v:44: Cannot find file containing module: 'timer_input_controller'\n    timer_input_controller input_ctrl \n    ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/461069000/timer/src,data/full_repos/permissive/461069000/timer_input_controller\n             data/full_repos/permissive/461069000/timer/src,data/full_repos/permissive/461069000/timer_input_controller.v\n             data/full_repos/permissive/461069000/timer/src,data/full_repos/permissive/461069000/timer_input_controller.sv\n             timer_input_controller\n             timer_input_controller.v\n             timer_input_controller.sv\n             obj_dir/timer_input_controller\n             obj_dir/timer_input_controller.v\n             obj_dir/timer_input_controller.sv\n%Error: data/full_repos/permissive/461069000/timer/src/timer.v:57: Cannot find file containing module: 'timer_output_controller'\n    timer_output_controller out_ctrl\n    ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/461069000/timer/src/timer.v:70: Cannot find file containing module: 'up_down_counter'\n    up_down_counter #(\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/461069000/timer/src/timer.v:85: Cannot find file containing module: 'timer_register'\n    timer_register #(\n    ^~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module timer
#(
    parameter COUNTER_BIT_WIDTH = 8
)(

    input clk,
    input ext_clk,
    input enable,
    input rst, 
    input [3:0] config_address,
    input config_write_enable,
    input [COUNTER_BIT_WIDTH-1:0] write_data,


    output [COUNTER_BIT_WIDTH-1:0] read_data,
    output comparator_1_output,
    output comparator_0_output);

    wire clock_selector;


    wire count_mode;
    wire cmp_0_int_en;
    wire cmp_1_int_en;
    wire start;

    wire [COUNTER_BIT_WIDTH-6:0] prescaler;
    wire [COUNTER_BIT_WIDTH-1:0] count;
    wire [COUNTER_BIT_WIDTH-1:0] cmp_1_value;
    wire [COUNTER_BIT_WIDTH-1:0] cmp_0_value;
    wire [COUNTER_BIT_WIDTH-1:0] count_max;
    wire [COUNTER_BIT_WIDTH-1:0] count_min;

    wire modified_ext_clk;
    wire clock_valid;
    wire cmp_0_match;
    wire cmp_1_match;



    timer_input_controller input_ctrl 
    (
        .clk(clk),
        .ext_clk(ext_clk),
        .enable(enable),
        .clock_selector(clock_selector),
        .prescaler_in(prescaler),
        .modified_ext_clk(modified_ext_clk),
        .clock_valid(clock_valid)
    );
   


    timer_output_controller out_ctrl
    (
        .counter(count),
        .cmp_1_value(cmp_1_value),
        .cmp_0_value(cmp_0_value),
        .cmp_1_match(cmp_1_match),
        .cmp_0_match(cmp_0_match)
    ) ;



    wire counter_enabled = (clock_valid & start);

    up_down_counter #(
        .COUNTER_BIT_WIDTH(COUNTER_BIT_WIDTH)
    ) counter_1 (
        .clk(clk),
        .rst(rst),
        .enable(counter_enabled),
        .count_mode(count_mode),
        .count_max(count_max),
        .count_min(count_min),
        .count(count)
    );




    timer_register #(
        .COUNTER_BIT_WIDTH(COUNTER_BIT_WIDTH)
    ) register_file (
        .clk(clk),
        .rst(rst),
        .enable(enable),
        .write_enable(config_write_enable),
        .write_data(write_data),
        .read_data(read_data),
        .address(config_address),
        .clock_selector(clock_selector),
        .cmp_0_int_en(cmp_0_int_en),
        .cmp_1_int_en(cmp_1_int_en),
        .count_mode(count_mode),
        .start(start),
        .cmp_1_f(cmp_1_match),
        .cmp_0_f(cmp_0_match),
        .prescaler(prescaler),
        .count(count),
        .count_max(count_max),
        .count_min(count_min),
        .cmp_1_value(cmp_1_value),
        .cmp_0_value(cmp_0_value)
    );

    assign comparator_1_output = cmp_1_int_en & cmp_1_match;
    assign comparator_0_output = cmp_0_int_en & cmp_0_match;

endmodule
module timer
#(
    parameter COUNTER_BIT_WIDTH = 8
)(

    input clk,
    input ext_clk,
    input enable,
    input rst, 
    input [3:0] config_address,
    input config_write_enable,
    input [COUNTER_BIT_WIDTH-1:0] write_data,


    output [COUNTER_BIT_WIDTH-1:0] read_data,
    output comparator_1_output,
    output comparator_0_output);


    wire clock_selector;


    wire count_mode;
    wire cmp_0_int_en;
    wire cmp_1_int_en;
    wire start;

    wire [COUNTER_BIT_WIDTH-6:0] prescaler;
    wire [COUNTER_BIT_WIDTH-1:0] count;
    wire [COUNTER_BIT_WIDTH-1:0] cmp_1_value;
    wire [COUNTER_BIT_WIDTH-1:0] cmp_0_value;
    wire [COUNTER_BIT_WIDTH-1:0] count_max;
    wire [COUNTER_BIT_WIDTH-1:0] count_min;

    wire modified_ext_clk;
    wire clock_valid;
    wire cmp_0_match;
    wire cmp_1_match;



    timer_input_controller input_ctrl 
    (
        .clk(clk),
        .ext_clk(ext_clk),
        .enable(enable),
        .clock_selector(clock_selector),
        .prescaler_in(prescaler),
        .modified_ext_clk(modified_ext_clk),
        .clock_valid(clock_valid)
    );
   


    timer_output_controller out_ctrl
    (
        .counter(count),
        .cmp_1_value(cmp_1_value),
        .cmp_0_value(cmp_0_value),
        .cmp_1_match(cmp_1_match),
        .cmp_0_match(cmp_0_match)
    ) ;



    wire counter_enabled = (clock_valid & start);

    up_down_counter #(
        .COUNTER_BIT_WIDTH(COUNTER_BIT_WIDTH)
    ) counter_1 (
        .clk(clk),
        .rst(rst),
        .enable(counter_enabled),
        .count_mode(count_mode),
        .count_max(count_max),
        .count_min(count_min),
        .count(count)
    );




    timer_register #(
        .COUNTER_BIT_WIDTH(COUNTER_BIT_WIDTH)
    ) register_file (
        .clk(clk),
        .rst(rst),
        .enable(enable),
        .write_enable(config_write_enable),
        .write_data(write_data),
        .read_data(read_data),
        .address(config_address),
        .clock_selector(clock_selector),
        .cmp_0_int_en(cmp_0_int_en),
        .cmp_1_int_en(cmp_1_int_en),
        .count_mode(count_mode),
        .start(start),
        .cmp_1_f(cmp_1_match),
        .cmp_0_f(cmp_0_match),
        .prescaler(prescaler),
        .count(count),
        .count_max(count_max),
        .count_min(count_min),
        .cmp_1_value(cmp_1_value),
        .cmp_0_value(cmp_0_value)
    );

    assign comparator_1_output = cmp_1_int_en & cmp_1_match;
    assign comparator_0_output = cmp_0_int_en & cmp_0_match;

endmodule