data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/atr_delay.v
data/verilator_xmls/d6285cc8-7e87-4ef8-9c67-14887c51a143.xml
module atr_delay(clk_i,rst_i,ena_i,tx_empty_i,tx_delay_i,rx_delay_i,atr_tx_o);
   input        clk_i;
   input        rst_i;
   input        ena_i;
   input        tx_empty_i;
   input [11:0] tx_delay_i;
   input [11:0] rx_delay_i;
   output       atr_tx_o;

   reg [3:0] 	state;
   reg [11:0] 	count;

   `define ST_RX_DELAY 4'b0001
   `define ST_RX       4'b0010
   `define ST_TX_DELAY 4'b0100
   `define ST_TX       4'b1000

   always @(posedge clk_i)
     if (rst_i | ~ena_i)
       begin
	  state <= `ST_RX;
	  count <= 12'b0;
       end
     else
       case (state)
	 `ST_RX:
	   if (!tx_empty_i)
	     begin
		state <= `ST_TX_DELAY;
		count <= tx_delay_i;
	     end

	 `ST_TX_DELAY:
	   if (count == 0)
	     state <= `ST_TX;
	   else
	     count <= count - 1;

	 `ST_TX:
	   if (tx_empty_i)
	     begin
		state <= `ST_RX_DELAY;
		count <= rx_delay_i;
	     end

	 `ST_RX_DELAY:
	   if (count == 0)
	     state <= `ST_RX;
	   else
	     count <= count - 1;
	 
	 default:
	   begin
	      state <= `ST_RX;
	      count <= 0;
	   end
       endcase
   
   assign atr_tx_o = (state == `ST_TX) | (state == `ST_RX_DELAY);
   
endmodule
module atr_delay(clk_i,rst_i,ena_i,tx_empty_i,tx_delay_i,rx_delay_i,atr_tx_o);

   input        clk_i;
   input        rst_i;
   input        ena_i;
   input        tx_empty_i;
   input [11:0] tx_delay_i;
   input [11:0] rx_delay_i;
   output       atr_tx_o;

   reg [3:0] 	state;
   reg [11:0] 	count;

   `define ST_RX_DELAY 4'b0001
   `define ST_RX       4'b0010
   `define ST_TX_DELAY 4'b0100
   `define ST_TX       4'b1000

   always @(posedge clk_i)
     if (rst_i | ~ena_i)
       begin
	  state <= `ST_RX;
	  count <= 12'b0;
       end
     else
       case (state)
	 `ST_RX:
	   if (!tx_empty_i)
	     begin
		state <= `ST_TX_DELAY;
		count <= tx_delay_i;
	     end

	 `ST_TX_DELAY:
	   if (count == 0)
	     state <= `ST_TX;
	   else
	     count <= count - 1;

	 `ST_TX:
	   if (tx_empty_i)
	     begin
		state <= `ST_RX_DELAY;
		count <= rx_delay_i;
	     end

	 `ST_RX_DELAY:
	   if (count == 0)
	     state <= `ST_RX;
	   else
	     count <= count - 1;
	 
	 default:
	   begin
	      state <= `ST_RX;
	      count <= 0;
	   end
       endcase
   
   assign atr_tx_o = (state == `ST_TX) | (state == `ST_RX_DELAY);
   
endmodule