data/full_repos/permissive/450915285/snake.v
1: b'%Error: data/full_repos/permissive/450915285/snake.v:70: Cannot find file containing module: \'clk_div\'\n  clk_div c1(clk, clk_d);\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/450915285,data/full_repos/permissive/450915285/clk_div\n             data/full_repos/permissive/450915285,data/full_repos/permissive/450915285/clk_div.v\n             data/full_repos/permissive/450915285,data/full_repos/permissive/450915285/clk_div.sv\n             clk_div\n             clk_div.v\n             clk_div.sv\n             obj_dir/clk_div\n             obj_dir/clk_div.v\n             obj_dir/clk_div.sv\n%Error: data/full_repos/permissive/450915285/snake.v:71: Cannot find file containing module: \'clockupdate\'\n  clockupdate T1(clk,clk_update);\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/450915285/snake.v:72: Cannot find file containing module: \'vga_sync\'\n  vga_sync V1(clk_d, h_count,v_count,video_on,h_sync,v_sync);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/450915285/snake.v:73: Cannot find file containing module: \'Random\'\n  Random R1(clk_d,rX,rY);\n  ^~~~~~\n%Error: data/full_repos/permissive/450915285/snake.v:74: Cannot find file containing module: \'Inputkey\'\n  Inputkey I1(clk,left,right,up,down,direction);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/450915285/snake.v:76: Cannot find file containing module: \'Segment_display\'\n  Segment_display display(.clk(clk_d), .gameOver(gameOver), .an(temp_an), .seg(temp_seg));\n  ^~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/450915285/snake.v:83: Operator GT expects 11 bits on the RHS, but RHS\'s VARREF \'appleX\' generates 10 bits.\n                                                               : ... In instance snake\n    inX <= (h_count > appleX & h_count < (appleX + 10));\n                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/450915285/snake.v:94: Operator MODDIV expects 32 or 10 bits on the LHS, but LHS\'s VARREF \'randomY\' generates 9 bits.\n                                                               : ... In instance snake\n      appleY = randomY % 350;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/450915285/snake.v:98: Operator MODDIV expects 32 or 10 bits on the LHS, but LHS\'s VARREF \'randomY\' generates 9 bits.\n                                                               : ... In instance snake\n      appleY <= randomY % 350;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/450915285/snake.v:104: Operator LTE expects 10 bits on the LHS, but LHS\'s LTE generates 1 bits.\n                                                                : ... In instance snake\n    snakeX[10] <= snakeX[9] <= snakeX[8]<= snakeX[7]<= snakeX[6]<= snakeX[5]<= snakeX[4]<= snakeX[3]<= snakeX[2]<= snakeX[1]<= snakeX[0];\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/450915285/snake.v:104: Operator LTE expects 10 bits on the LHS, but LHS\'s LTE generates 1 bits.\n                                                                : ... In instance snake\n    snakeX[10] <= snakeX[9] <= snakeX[8]<= snakeX[7]<= snakeX[6]<= snakeX[5]<= snakeX[4]<= snakeX[3]<= snakeX[2]<= snakeX[1]<= snakeX[0];\n                                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/450915285/snake.v:104: Operator LTE expects 10 bits on the LHS, but LHS\'s LTE generates 1 bits.\n                                                                : ... In instance snake\n    snakeX[10] <= snakeX[9] <= snakeX[8]<= snakeX[7]<= snakeX[6]<= snakeX[5]<= snakeX[4]<= snakeX[3]<= snakeX[2]<= snakeX[1]<= snakeX[0];\n                                                                ^~\n%Warning-WIDTH: data/full_repos/permissive/450915285/snake.v:104: Operator LTE expects 10 bits on the LHS, but LHS\'s LTE generates 1 bits.\n                                                                : ... In instance snake\n    snakeX[10] <= snakeX[9] <= snakeX[8]<= snakeX[7]<= snakeX[6]<= snakeX[5]<= snakeX[4]<= snakeX[3]<= snakeX[2]<= snakeX[1]<= snakeX[0];\n                                                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/450915285/snake.v:104: Operator LTE expects 10 bits on the LHS, but LHS\'s LTE generates 1 bits.\n                                                                : ... In instance snake\n    snakeX[10] <= snakeX[9] <= snakeX[8]<= snakeX[7]<= snakeX[6]<= snakeX[5]<= snakeX[4]<= snakeX[3]<= snakeX[2]<= snakeX[1]<= snakeX[0];\n                                                                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/450915285/snake.v:104: Operator LTE expects 10 bits on the LHS, but LHS\'s LTE generates 1 bits.\n                                                                : ... In instance snake\n    snakeX[10] <= snakeX[9] <= snakeX[8]<= snakeX[7]<= snakeX[6]<= snakeX[5]<= snakeX[4]<= snakeX[3]<= snakeX[2]<= snakeX[1]<= snakeX[0];\n                                                                                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/450915285/snake.v:104: Operator LTE expects 10 bits on the LHS, but LHS\'s LTE generates 1 bits.\n                                                                : ... In instance snake\n    snakeX[10] <= snakeX[9] <= snakeX[8]<= snakeX[7]<= snakeX[6]<= snakeX[5]<= snakeX[4]<= snakeX[3]<= snakeX[2]<= snakeX[1]<= snakeX[0];\n                                                                                                                ^~\n%Warning-WIDTH: data/full_repos/permissive/450915285/snake.v:104: Operator LTE expects 10 bits on the LHS, but LHS\'s LTE generates 1 bits.\n                                                                : ... In instance snake\n    snakeX[10] <= snakeX[9] <= snakeX[8]<= snakeX[7]<= snakeX[6]<= snakeX[5]<= snakeX[4]<= snakeX[3]<= snakeX[2]<= snakeX[1]<= snakeX[0];\n                                                                                                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/450915285/snake.v:104: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s LTE generates 1 bits.\n                                                                : ... In instance snake\n    snakeX[10] <= snakeX[9] <= snakeX[8]<= snakeX[7]<= snakeX[6]<= snakeX[5]<= snakeX[4]<= snakeX[3]<= snakeX[2]<= snakeX[1]<= snakeX[0];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/450915285/snake.v:105: Operator LTE expects 9 bits on the LHS, but LHS\'s LTE generates 1 bits.\n                                                                : ... In instance snake\n    snakeY[10] <= snakeY[9]<= snakeY[8]<= snakeY[7]<= snakeY[6]<= snakeY[5]<= snakeY[4]<= snakeY[3]<= snakeY[2]<= snakeY[1]<= snakeY[0];\n                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/450915285/snake.v:105: Operator LTE expects 9 bits on the LHS, but LHS\'s LTE generates 1 bits.\n                                                                : ... In instance snake\n    snakeY[10] <= snakeY[9]<= snakeY[8]<= snakeY[7]<= snakeY[6]<= snakeY[5]<= snakeY[4]<= snakeY[3]<= snakeY[2]<= snakeY[1]<= snakeY[0];\n                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/450915285/snake.v:105: Operator LTE expects 9 bits on the LHS, but LHS\'s LTE generates 1 bits.\n                                                                : ... In instance snake\n    snakeY[10] <= snakeY[9]<= snakeY[8]<= snakeY[7]<= snakeY[6]<= snakeY[5]<= snakeY[4]<= snakeY[3]<= snakeY[2]<= snakeY[1]<= snakeY[0];\n                                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/450915285/snake.v:105: Operator LTE expects 9 bits on the LHS, but LHS\'s LTE generates 1 bits.\n                                                                : ... In instance snake\n    snakeY[10] <= snakeY[9]<= snakeY[8]<= snakeY[7]<= snakeY[6]<= snakeY[5]<= snakeY[4]<= snakeY[3]<= snakeY[2]<= snakeY[1]<= snakeY[0];\n                                                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/450915285/snake.v:105: Operator LTE expects 9 bits on the LHS, but LHS\'s LTE generates 1 bits.\n                                                                : ... In instance snake\n    snakeY[10] <= snakeY[9]<= snakeY[8]<= snakeY[7]<= snakeY[6]<= snakeY[5]<= snakeY[4]<= snakeY[3]<= snakeY[2]<= snakeY[1]<= snakeY[0];\n                                                                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/450915285/snake.v:105: Operator LTE expects 9 bits on the LHS, but LHS\'s LTE generates 1 bits.\n                                                                : ... In instance snake\n    snakeY[10] <= snakeY[9]<= snakeY[8]<= snakeY[7]<= snakeY[6]<= snakeY[5]<= snakeY[4]<= snakeY[3]<= snakeY[2]<= snakeY[1]<= snakeY[0];\n                                                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/450915285/snake.v:105: Operator LTE expects 9 bits on the LHS, but LHS\'s LTE generates 1 bits.\n                                                                : ... In instance snake\n    snakeY[10] <= snakeY[9]<= snakeY[8]<= snakeY[7]<= snakeY[6]<= snakeY[5]<= snakeY[4]<= snakeY[3]<= snakeY[2]<= snakeY[1]<= snakeY[0];\n                                                                                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/450915285/snake.v:105: Operator LTE expects 9 bits on the LHS, but LHS\'s LTE generates 1 bits.\n                                                                : ... In instance snake\n    snakeY[10] <= snakeY[9]<= snakeY[8]<= snakeY[7]<= snakeY[6]<= snakeY[5]<= snakeY[4]<= snakeY[3]<= snakeY[2]<= snakeY[1]<= snakeY[0];\n                                                                                                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/450915285/snake.v:105: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s LTE generates 1 bits.\n                                                                : ... In instance snake\n    snakeY[10] <= snakeY[9]<= snakeY[8]<= snakeY[7]<= snakeY[6]<= snakeY[5]<= snakeY[4]<= snakeY[3]<= snakeY[2]<= snakeY[1]<= snakeY[0];\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/450915285/snake.v:115: Operator GT expects 11 bits on the RHS, but RHS\'s ARRAYSEL generates 10 bits.\n                                                                : ... In instance snake\n    snake = ((h_count > snakeX[1] & h_count < snakeX[10]+10) & (v_count > snakeY[1] & v_count < snakeY[10]+10));\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/450915285/snake.v:115: Operator GT expects 10 bits on the RHS, but RHS\'s ARRAYSEL generates 9 bits.\n                                                                : ... In instance snake\n    snake = ((h_count > snakeX[1] & h_count < snakeX[10]+10) & (v_count > snakeY[1] & v_count < snakeY[10]+10));\n                                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/450915285/snake.v:118: Operator GT expects 11 bits on the RHS, but RHS\'s ARRAYSEL generates 10 bits.\n                                                                : ... In instance snake\n    head  <= (h_count > snakeX[0] & h_count < (snakeX[0]+10)) & (v_count > snakeY[0] & v_count < (snakeY[0]+10));\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/450915285/snake.v:118: Operator GT expects 10 bits on the RHS, but RHS\'s ARRAYSEL generates 9 bits.\n                                                                : ... In instance snake\n    head  <= (h_count > snakeX[0] & h_count < (snakeX[0]+10)) & (v_count > snakeY[0] & v_count < (snakeY[0]+10));\n                                                                         ^\n%Error: Exiting due to 6 error(s), 25 warning(s)\n'
module snake(clk,reset,up,down,left,right,red,green,blue,h_sync,v_sync,seg,an);
    input clk;
    input reset;
    input up;
    input down;
    input left;
    input right;
  output [3:0] red;
  output [3:0] green;
  output [3:0] blue;
    output h_sync;
    output v_sync;
  reg [3:0] red;
  reg [3:0] blue;
  reg [3:0] green;
  
  output [3:0] an;
  output [7:0] seg;
  
  reg [3:0] an;
  reg [7:0] seg;
	
  reg apple,border,eat,snake,stop,inX,inY,snakeHead,snakeBody,head,gameOver,fail;
  wire clk_d,clk_update,video_on ;
  wire[10:0] h_count;
  wire [3:0] direction;
  wire [9:0] v_count,rX;
  wire [9:0] randomX;
  reg [9:0] appleX,appleY;
  reg [9:0] headX,headY;
  wire [8:0] rY;
  wire [8:0] randomY;
  wire R,G,B;


  reg [9:0] snakeX[0:10];
  reg [8:0] snakeY[0:10];
  
  wire [7:0] temp_seg;
  wire [3:0] temp_an;
  
  
  clk_div c1(clk, clk_d);
  clockupdate T1(clk,clk_update);
  vga_sync V1(clk_d, h_count,v_count,video_on,h_sync,v_sync);
  Random R1(clk_d,rX,rY);
  Inputkey I1(clk,left,right,up,down,direction);

  Segment_display display(.clk(clk_d), .gameOver(gameOver), .an(temp_an), .seg(temp_seg));

  
  assign randomX = rX;
  assign randomY = rY;
  
  always @(posedge clk_d) begin
    inX <= (h_count > appleX & h_count < (appleX + 10));
    inY <= (v_count > appleY & v_count < (appleY + 10));
    apple <= inX & inY;
  end
  always@(posedge clk_d) begin
    border <= (((h_count >= 0) & (h_count < 15) | (h_count >= 630) & (h_count < 641)) | ((v_count >= 0) & (v_count < 15) | (v_count >= 465) & (v_count < 481)));
  end
  
  always@(posedge clk_d) begin
    if(reset) begin
      appleX = randomX % 500;
      appleY = randomY % 350;
    end 
    if(apple & head) begin
      appleX <= randomX % 500;
      appleY <= randomY % 350;
    end
    
  end
  
  always@(posedge clk_update) begin
    snakeX[10] <= snakeX[9] <= snakeX[8]<= snakeX[7]<= snakeX[6]<= snakeX[5]<= snakeX[4]<= snakeX[3]<= snakeX[2]<= snakeX[1]<= snakeX[0];
    snakeY[10] <= snakeY[9]<= snakeY[8]<= snakeY[7]<= snakeY[6]<= snakeY[5]<= snakeY[4]<= snakeY[3]<= snakeY[2]<= snakeY[1]<= snakeY[0];
    case(direction)
      4'b0100:snakeX[0] = snakeX[0] - 7;
      4'b1000:snakeX[0] = snakeX[0] + 7;
      4'b0001:snakeY[0] = snakeY[0] - 7;
      4'b0010:snakeY[0] = snakeY[0] + 7;
    endcase 
  end 
  
  always@(posedge clk_d) begin
    snake = ((h_count > snakeX[1] & h_count < snakeX[10]+10) & (v_count > snakeY[1] & v_count < snakeY[10]+10));
  end
  always@(posedge clk_d) begin
    head  <= (h_count > snakeX[0] & h_count < (snakeX[0]+10)) & (v_count > snakeY[0] & v_count < (snakeY[0]+10));
  end
  always @(posedge clk_d) begin
    if((border & (snake|head)) | reset) gameOver<=1; 
    else gameOver=0;
  end
 
  
  assign R = (video_on & (apple | gameOver));
  assign G = (video_on & ( (snake|head) & ~gameOver));
  assign B = (video_on & (border & ~gameOver));
  always@(posedge clk_d) begin
    red = {4{R}};
    green = {4{G}};
    blue = {4{B}};
  end          
              
endmodule
module snake(clk,reset,up,down,left,right,red,green,blue,h_sync,v_sync,seg,an);

    input clk;
    input reset;
    input up;
    input down;
    input left;
    input right;
  output [3:0] red;
  output [3:0] green;
  output [3:0] blue;
    output h_sync;
    output v_sync;
  reg [3:0] red;
  reg [3:0] blue;
  reg [3:0] green;
  
  output [3:0] an;
  output [7:0] seg;
  
  reg [3:0] an;
  reg [7:0] seg;
	
  reg apple,border,eat,snake,stop,inX,inY,snakeHead,snakeBody,head,gameOver,fail;
  wire clk_d,clk_update,video_on ;
  wire[10:0] h_count;
  wire [3:0] direction;
  wire [9:0] v_count,rX;
  wire [9:0] randomX;
  reg [9:0] appleX,appleY;
  reg [9:0] headX,headY;
  wire [8:0] rY;
  wire [8:0] randomY;
  wire R,G,B;


  reg [9:0] snakeX[0:10];
  reg [8:0] snakeY[0:10];
  
  wire [7:0] temp_seg;
  wire [3:0] temp_an;
  
  
  clk_div c1(clk, clk_d);
  clockupdate T1(clk,clk_update);
  vga_sync V1(clk_d, h_count,v_count,video_on,h_sync,v_sync);
  Random R1(clk_d,rX,rY);
  Inputkey I1(clk,left,right,up,down,direction);

  Segment_display display(.clk(clk_d), .gameOver(gameOver), .an(temp_an), .seg(temp_seg));

  
  assign randomX = rX;
  assign randomY = rY;
  
  always @(posedge clk_d) begin
    inX <= (h_count > appleX & h_count < (appleX + 10));
    inY <= (v_count > appleY & v_count < (appleY + 10));
    apple <= inX & inY;
  end
  always@(posedge clk_d) begin
    border <= (((h_count >= 0) & (h_count < 15) | (h_count >= 630) & (h_count < 641)) | ((v_count >= 0) & (v_count < 15) | (v_count >= 465) & (v_count < 481)));
  end
  
  always@(posedge clk_d) begin
    if(reset) begin
      appleX = randomX % 500;
      appleY = randomY % 350;
    end 
    if(apple & head) begin
      appleX <= randomX % 500;
      appleY <= randomY % 350;
    end
    
  end
  
  always@(posedge clk_update) begin
    snakeX[10] <= snakeX[9] <= snakeX[8]<= snakeX[7]<= snakeX[6]<= snakeX[5]<= snakeX[4]<= snakeX[3]<= snakeX[2]<= snakeX[1]<= snakeX[0];
    snakeY[10] <= snakeY[9]<= snakeY[8]<= snakeY[7]<= snakeY[6]<= snakeY[5]<= snakeY[4]<= snakeY[3]<= snakeY[2]<= snakeY[1]<= snakeY[0];
    case(direction)
      4'b0100:snakeX[0] = snakeX[0] - 7;
      4'b1000:snakeX[0] = snakeX[0] + 7;
      4'b0001:snakeY[0] = snakeY[0] - 7;
      4'b0010:snakeY[0] = snakeY[0] + 7;
    endcase 
  end 
  
  always@(posedge clk_d) begin
    snake = ((h_count > snakeX[1] & h_count < snakeX[10]+10) & (v_count > snakeY[1] & v_count < snakeY[10]+10));
  end
  always@(posedge clk_d) begin
    head  <= (h_count > snakeX[0] & h_count < (snakeX[0]+10)) & (v_count > snakeY[0] & v_count < (snakeY[0]+10));
  end
  always @(posedge clk_d) begin
    if((border & (snake|head)) | reset) gameOver<=1; 
    else gameOver=0;
  end
 
  
  assign R = (video_on & (apple | gameOver));
  assign G = (video_on & ( (snake|head) & ~gameOver));
  assign B = (video_on & (border & ~gameOver));
  always@(posedge clk_d) begin
    red = {4{R}};
    green = {4{G}};
    blue = {4{B}};
  end          
              
endmodule