data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v
1: b'%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:4: Cannot find include file: AXIOutputRegisters_v1_0_tb_include.vh\n`include "AXIOutputRegisters_v1_0_tb_include.vh" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design,data/full_repos/permissive/506208052/AXIOutputRegisters_v1_0_tb_include.vh\n             data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design,data/full_repos/permissive/506208052/AXIOutputRegisters_v1_0_tb_include.vh.v\n             data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design,data/full_repos/permissive/506208052/AXIOutputRegisters_v1_0_tb_include.vh.sv\n             AXIOutputRegisters_v1_0_tb_include.vh\n             AXIOutputRegisters_v1_0_tb_include.vh.v\n             AXIOutputRegisters_v1_0_tb_include.vh.sv\n             obj_dir/AXIOutputRegisters_v1_0_tb_include.vh\n             obj_dir/AXIOutputRegisters_v1_0_tb_include.vh.v\n             obj_dir/AXIOutputRegisters_v1_0_tb_include.vh.sv\n%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:24: Define or directive not defined: \'`BD_WRAPPER\'\n `BD_WRAPPER dut (.ACLK(tb_ACLK),\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:24: syntax error, unexpected \'(\', expecting IDENTIFIER\n `BD_WRAPPER dut (.ACLK(tb_ACLK),\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n   #500;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:45: syntax error, unexpected \'@\'\n  @(posedge tb_ACLK);\n  ^\n%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:47: syntax error, unexpected \'@\'\n  @(posedge tb_ACLK);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n always #10 tb_ACLK = !tb_ACLK;\n        ^\n%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:116: Define or directive not defined: \'`S00_AXI_SLAVE_ADDRESS\'\n   S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;\n                          ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:116: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;\n                                                ^\n%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:124: Define or directive not defined: \'`BD_INST_NAME\'\n     dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:124: syntax error, unexpected \'.\'\n     dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,\n                      ^\n%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:131: Define or directive not defined: \'`BD_INST_NAME\'\n     dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:131: syntax error, unexpected \'.\'\n     dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,\n                      ^\n%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:156: syntax error, unexpected \'@\'\n  wait(tb_ARESETn === 0) @(posedge tb_ACLK);\n                         ^\n%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:156: Unsupported: wait statements\n  wait(tb_ARESETn === 0) @(posedge tb_ACLK);\n  ^~~~\n%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:157: syntax error, unexpected \'@\'\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);\n                         ^\n%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:157: Unsupported: wait statements\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);\n  ^~~~\n%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:158: syntax error, unexpected \'@\'\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);     \n                         ^\n%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:158: Unsupported: wait statements\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);     \n  ^~~~\n%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:159: syntax error, unexpected \'@\'\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);     \n                         ^\n%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:159: Unsupported: wait statements\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);     \n  ^~~~\n%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:160: syntax error, unexpected \'@\'\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);  \n                         ^\n%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:160: Unsupported: wait statements\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);  \n  ^~~~\n%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:162: Define or directive not defined: \'`BD_INST_NAME\'\n  dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:162: syntax error, unexpected \'.\'\n  dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);\n                   ^\n%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:174: syntax error, unexpected \'@\'\n  wait(tb_ARESETn === 0) @(posedge tb_ACLK);\n                         ^\n%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:174: Unsupported: wait statements\n  wait(tb_ARESETn === 0) @(posedge tb_ACLK);\n  ^~~~\n%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:175: syntax error, unexpected \'@\'\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);\n                         ^\n%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:175: Unsupported: wait statements\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);\n  ^~~~\n%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:176: syntax error, unexpected \'@\'\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);     \n                         ^\n%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:176: Unsupported: wait statements\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);     \n  ^~~~\n%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:177: syntax error, unexpected \'@\'\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);     \n                         ^\n%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:177: Unsupported: wait statements\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);     \n  ^~~~\n%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:178: syntax error, unexpected \'@\'\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);     \n                         ^\n%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/example_designs/bfm_design/AXIOutputRegisters_v1_0_tb.v:178: Unsupported: wait statements\n  wait(tb_ARESETn === 1) @(posedge tb_ACLK);     \n  ^~~~\n%Error: Exiting due to 33 error(s), 2 warning(s)\n'
module AXIOutputRegisters_v1_0_tb;
	reg tb_ACLK;
	reg tb_ARESETn;


	`BD_WRAPPER dut (.ACLK(tb_ACLK),
				.ARESETN(tb_ARESETn));




	reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
	reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
	reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
	reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
	reg [3-1:0]   S00_AXI_mtestProtection_lite;
	integer S00_AXI_mtestvectorlite;
	integer S00_AXI_mtestdatasizelite;
	integer result_slave_lite;



	initial begin
		tb_ARESETn = 1'b0;
	  #500;

		@(posedge tb_ACLK);
	  tb_ARESETn = 1'b1;
		@(posedge tb_ACLK);
	end


	initial tb_ACLK = 1'b0;
	always #10 tb_ACLK = !tb_ACLK;








	task automatic CHECK_RESPONSE_OKAY;
		input [`RESP_BUS_WIDTH-1:0] response;
		begin
		  if (response !== `RESPONSE_OKAY) begin
			  $display("TESTBENCH ERROR! lite_response is not OKAY",
				         "\n expected = 0x%h",`RESPONSE_OKAY,
				         "\n actual   = 0x%h",response);
		    $stop;
		  end
		end
	endtask










	task automatic COMPARE_LITE_DATA;
		input expected;
		input actual;
		begin
			if (expected === 'hx || actual === 'hx) begin
				$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
		    result_slave_lite = 0;
		    $stop;
		  end

			if (actual != expected) begin
				$display("TESTBENCH ERROR! Data expected is not equal to actual.",
				         "\nexpected = 0x%h",expected,
				         "\nactual   = 0x%h",actual);
		    result_slave_lite = 0;
		    $stop;
		  end
			else 
			begin
			   $display("TESTBENCH Passed! Data expected is equal to actual.",
			            "\n expected = 0x%h",expected,
			            "\n actual   = 0x%h",actual);
			end
		end
	endtask

	task automatic S00_AXI_TEST;
		begin
			$display("---------------------------------------------------------");
			$display("EXAMPLE TEST : S00_AXI");
			$display("Simple register write and read example");
			$display("---------------------------------------------------------");

			S00_AXI_mtestvectorlite = 0;
			S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
			S00_AXI_mtestProtection_lite = 0;
			S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;

			 result_slave_lite = 1;

			for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
			begin
			  dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
				                     S00_AXI_mtestProtection_lite,
				                     S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
				                     S00_AXI_mtestdatasizelite,
				                     S00_AXI_lite_response);
			  $display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
			  CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
			  dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
				                     S00_AXI_mtestProtection_lite,
				                     S00_AXI_rd_data_lite,
				                     S00_AXI_lite_response);
			  $display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
			  CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
			  COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
			  $display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
			  S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
			end

			$display("---------------------------------------------------------");
			$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
				if ( result_slave_lite ) begin                                        
					$display("PTGEN_TEST: PASSED!");                 
				end	else begin                                         
					$display("PTGEN_TEST: FAILED!");                 
				end							   
			$display("---------------------------------------------------------");
		end
	endtask


	initial begin

		wait(tb_ARESETn === 0) @(posedge tb_ACLK);
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);     
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);     
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);  

		dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);


		S00_AXI_test_data_lite[0] = 32'h0101FFFF;
		S00_AXI_test_data_lite[1] = 32'habcd0001;
		S00_AXI_test_data_lite[2] = 32'hdead0011;
		S00_AXI_test_data_lite[3] = 32'hbeef0011;
	end


	initial begin

		wait(tb_ARESETn === 0) @(posedge tb_ACLK);
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);     
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);     
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);     

		S00_AXI_TEST();

	end

endmodule
module AXIOutputRegisters_v1_0_tb;

	reg tb_ACLK;
	reg tb_ARESETn;


	`BD_WRAPPER dut (.ACLK(tb_ACLK),
				.ARESETN(tb_ARESETn));




	reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
	reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
	reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
	reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
	reg [3-1:0]   S00_AXI_mtestProtection_lite;
	integer S00_AXI_mtestvectorlite;
	integer S00_AXI_mtestdatasizelite;
	integer result_slave_lite;



	initial begin
		tb_ARESETn = 1'b0;
	  #500;

		@(posedge tb_ACLK);
	  tb_ARESETn = 1'b1;
		@(posedge tb_ACLK);
	end


	initial tb_ACLK = 1'b0;
	always #10 tb_ACLK = !tb_ACLK;








	task automatic CHECK_RESPONSE_OKAY;
		input [`RESP_BUS_WIDTH-1:0] response;
		begin
		  if (response !== `RESPONSE_OKAY) begin
			  $display("TESTBENCH ERROR! lite_response is not OKAY",
				         "\n expected = 0x%h",`RESPONSE_OKAY,
				         "\n actual   = 0x%h",response);
		    $stop;
		  end
		end
	endtask










	task automatic COMPARE_LITE_DATA;
		input expected;
		input actual;
		begin
			if (expected === 'hx || actual === 'hx) begin
				$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
		    result_slave_lite = 0;
		    $stop;
		  end

			if (actual != expected) begin
				$display("TESTBENCH ERROR! Data expected is not equal to actual.",
				         "\nexpected = 0x%h",expected,
				         "\nactual   = 0x%h",actual);
		    result_slave_lite = 0;
		    $stop;
		  end
			else 
			begin
			   $display("TESTBENCH Passed! Data expected is equal to actual.",
			            "\n expected = 0x%h",expected,
			            "\n actual   = 0x%h",actual);
			end
		end
	endtask

	task automatic S00_AXI_TEST;
		begin
			$display("---------------------------------------------------------");
			$display("EXAMPLE TEST : S00_AXI");
			$display("Simple register write and read example");
			$display("---------------------------------------------------------");

			S00_AXI_mtestvectorlite = 0;
			S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
			S00_AXI_mtestProtection_lite = 0;
			S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;

			 result_slave_lite = 1;

			for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
			begin
			  dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
				                     S00_AXI_mtestProtection_lite,
				                     S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
				                     S00_AXI_mtestdatasizelite,
				                     S00_AXI_lite_response);
			  $display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
			  CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
			  dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
				                     S00_AXI_mtestProtection_lite,
				                     S00_AXI_rd_data_lite,
				                     S00_AXI_lite_response);
			  $display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
			  CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
			  COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
			  $display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
			  S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
			end

			$display("---------------------------------------------------------");
			$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
				if ( result_slave_lite ) begin                                        
					$display("PTGEN_TEST: PASSED!");                 
				end	else begin                                         
					$display("PTGEN_TEST: FAILED!");                 
				end							   
			$display("---------------------------------------------------------");
		end
	endtask


	initial begin

		wait(tb_ARESETn === 0) @(posedge tb_ACLK);
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);     
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);     
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);  

		dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);


		S00_AXI_test_data_lite[0] = 32'h0101FFFF;
		S00_AXI_test_data_lite[1] = 32'habcd0001;
		S00_AXI_test_data_lite[2] = 32'hdead0011;
		S00_AXI_test_data_lite[3] = 32'hbeef0011;
	end


	initial begin

		wait(tb_ARESETn === 0) @(posedge tb_ACLK);
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);     
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);     
		wait(tb_ARESETn === 1) @(posedge tb_ACLK);     

		S00_AXI_TEST();

	end

endmodule