data/full_repos/permissive/441359809/src/yosys/tests/sva/sva_range.sv
1: b"%Error: data/full_repos/permissive/441359809/src/yosys/tests/sva/sva_range.sv:8: syntax error, unexpected ##, expecting ')'\n  a ##[*] b |=> c until d\n    ^~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/sva/sva_range.sv:8: Unsupported: SystemVerilog 2009 reserved word not implemented: 'until'\n  a ##[*] b |=> c until d\n                  ^~~~~\n%Error: Exiting due to 2 error(s)\n"
module top (
	input clk,
	input a, b, c, d
);
	default clocking @(posedge clk); endclocking

	assert property (
		a ##[*] b |=> c until d
	);

`ifndef FAIL
	assume property (
		b |=> ##5 d
	);
	assume property (
		b || (c && !d) |=> c
	);
`endif
endmodule
module top (
	input clk,
	input a, b, c, d
);

	default clocking @(posedge clk); endclocking

	assert property (
		a ##[*] b |=> c until d
	);

`ifndef FAIL
	assume property (
		b |=> ##5 d
	);
	assume property (
		b || (c && !d) |=> c
	);
`endif
endmodule