data/full_repos/permissive/493694849/rtl/AES_128_Core.v
1: b"%Error: data/full_repos/permissive/493694849/rtl/AES_128_Core.v:73: Cannot find file containing module: 'AES_128_Encipher_Block'\nAES_128_Encipher_Block enc_block (\n^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/493694849/rtl,data/full_repos/permissive/493694849/AES_128_Encipher_Block\n             data/full_repos/permissive/493694849/rtl,data/full_repos/permissive/493694849/AES_128_Encipher_Block.v\n             data/full_repos/permissive/493694849/rtl,data/full_repos/permissive/493694849/AES_128_Encipher_Block.sv\n             AES_128_Encipher_Block\n             AES_128_Encipher_Block.v\n             AES_128_Encipher_Block.sv\n             obj_dir/AES_128_Encipher_Block\n             obj_dir/AES_128_Encipher_Block.v\n             obj_dir/AES_128_Encipher_Block.sv\n%Error: data/full_repos/permissive/493694849/rtl/AES_128_Core.v:87: Cannot find file containing module: 'AES_128_Decipher_Block'\nAES_128_Decipher_Block dec_block (\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493694849/rtl/AES_128_Core.v:99: Cannot find file containing module: 'AES_128_Key_Mem'\nAES_128_Key_Mem keymem (\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493694849/rtl/AES_128_Core.v:112: Cannot find file containing module: 'AES_Sbox'\nAES_Sbox sbox_inst (\n^~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module AES_128_Core(
    input wire clk,
    input wire reset_n,
    input wire encdec,
    input wire init,
    input wire next,
    input wire [127:0] key,
    input wire [127:0] block,
    
    output wire ready,
    output wire [127:0] result,
    output wire result_valid
);




localparam CTRL_IDLE = 2'h0;
localparam CTRL_INIT = 2'h1;
localparam CTRL_NEXT = 2'h2;




reg [1:0] aes_core_ctrl_reg;
reg [1:0] aes_core_ctrl_new;
reg aes_core_ctrl_we;

reg result_valid_reg;
reg result_valid_new;
reg result_valid_we;

reg ready_reg;
reg ready_new;
reg ready_we;




reg init_state;

wire [127:0] round_key;
wire key_ready;

reg enc_next;
wire [3:0] enc_round_nr;
wire [127:0] enc_new_block;
wire enc_ready;
wire [31:0] enc_sbox;

reg dec_next;
wire [3:0] dec_round_nr;
wire [127:0] dec_new_block;
wire dec_ready;

reg [127:0] muxed_new_block;
reg [3:0] muxed_round_nr;
reg muxed_ready;

wire [31:0] keymem_sbox;

reg [31:0] muxed_sbox;
wire [31:0] new_sbox;




AES_128_Encipher_Block enc_block (
    .clk(clk),
    .reset_n(reset_n),
    .next(enc_next),
    .round_key(round_key),
    .new_sbox(new_sbox),
    .block(block),

    .round(enc_round_nr),
    .sbox(enc_sbox),
    .new_block(enc_new_block),
    .ready(enc_ready)
);

AES_128_Decipher_Block dec_block (
    .clk(clk),
    .reset_n(reset_n),
    .next(dec_next),
    .round_key(round_key),
    .block(block),

    .round(dec_round_nr),
    .new_block(dec_new_block),
    .ready(dec_ready)
);

AES_128_Key_Mem keymem (
    .clk(clk),
    .reset_n(reset_n),
    .key(key),
    .init(init),
    .round(muxed_round_nr),
    .sbox(keymem_sbox),

    .round_key(round_key),
    .ready(key_ready),
    .new_sbox(new_sbox)
);

AES_Sbox sbox_inst (
    .sbox(muxed_sbox),
    .new_sbox(new_sbox)
);




assign ready = ready_reg;
assign result = muxed_new_block;
assign result_valid = result_valid_reg;








always @(posedge clk or negedge reset_n) begin: reg_update
    if (!reset_n) begin
        result_valid_reg <= 1'b0;
        ready_reg <= 1'b1;
        aes_core_ctrl_reg <= CTRL_IDLE;
    end
    else begin
        if (result_valid_we)
            result_valid_reg <= result_valid_new;
        if (ready_we)
            ready_reg <= ready_new;
        if (aes_core_ctrl_we)
            aes_core_ctrl_reg <= aes_core_ctrl_new;
    end
end







always @(*) begin: sbox_mux
    if (init_state)
        muxed_sbox = keymem_sbox;
    else 
        muxed_sbox = enc_sbox;
end








always @(*) begin: encdex_mux
    enc_next = 1'b0;
    dec_next = 1'b0;

    if (encdec) begin

        enc_next = next;
        muxed_round_nr = enc_round_nr;
        muxed_new_block = enc_new_block;
        muxed_ready = enc_ready;
    end
    else begin

        dec_next = next;
        muxed_round_nr = dec_round_nr;
        muxed_new_block = dec_new_block;
        muxed_ready = dec_ready;
    end
end









always @(*) begin: aes_core_ctrl
    init_state = 1'b0;
    ready_new = 1'b0;
    ready_we = 1'b0;
    result_valid_new = 1'b0;
    result_valid_we = 1'b0;
    aes_core_ctrl_new = CTRL_IDLE;
    aes_core_ctrl_we = 1'b0;
    
    case (aes_core_ctrl_reg)
        CTRL_IDLE: begin
            if (init) begin
                init_state = 1'b1;
                ready_new = 1'b0;
                ready_we = 1'b1;
                result_valid_new = 1'b0;
                result_valid_we = 1'b1;
                aes_core_ctrl_new = CTRL_INIT;
                aes_core_ctrl_we = 1'b1;
            end
            else if (next) begin
                init_state = 1'b0;
                ready_new = 1'b0;
                ready_we = 1'b1;
                result_valid_new = 1'b0;
                result_valid_we = 1'b1;
                aes_core_ctrl_new = CTRL_NEXT;
                aes_core_ctrl_we = 1'b1;
            end
        end

        CTRL_INIT: begin
            init_state = 1'b1;

            if (key_ready) begin
                ready_new = 1'b1;
                ready_we = 1'b1;
                aes_core_ctrl_new = CTRL_IDLE;
                aes_core_ctrl_we = 1'b1;
            end
        end

        CTRL_NEXT: begin
            init_state = 1'b0;

            if (muxed_ready) begin
                ready_new = 1'b1;
                ready_we = 1'b1;
                result_valid_new = 1'b1;
                result_valid_we = 1'b1;
                aes_core_ctrl_new = CTRL_IDLE;
                aes_core_ctrl_we = 1'b1;
            end
        end

        default: begin
        end
    endcase
end


endmodule
module AES_128_Core(
    input wire clk,
    input wire reset_n,
    input wire encdec,
    input wire init,
    input wire next,
    input wire [127:0] key,
    input wire [127:0] block,
    
    output wire ready,
    output wire [127:0] result,
    output wire result_valid
);





localparam CTRL_IDLE = 2'h0;
localparam CTRL_INIT = 2'h1;
localparam CTRL_NEXT = 2'h2;




reg [1:0] aes_core_ctrl_reg;
reg [1:0] aes_core_ctrl_new;
reg aes_core_ctrl_we;

reg result_valid_reg;
reg result_valid_new;
reg result_valid_we;

reg ready_reg;
reg ready_new;
reg ready_we;




reg init_state;

wire [127:0] round_key;
wire key_ready;

reg enc_next;
wire [3:0] enc_round_nr;
wire [127:0] enc_new_block;
wire enc_ready;
wire [31:0] enc_sbox;

reg dec_next;
wire [3:0] dec_round_nr;
wire [127:0] dec_new_block;
wire dec_ready;

reg [127:0] muxed_new_block;
reg [3:0] muxed_round_nr;
reg muxed_ready;

wire [31:0] keymem_sbox;

reg [31:0] muxed_sbox;
wire [31:0] new_sbox;




AES_128_Encipher_Block enc_block (
    .clk(clk),
    .reset_n(reset_n),
    .next(enc_next),
    .round_key(round_key),
    .new_sbox(new_sbox),
    .block(block),

    .round(enc_round_nr),
    .sbox(enc_sbox),
    .new_block(enc_new_block),
    .ready(enc_ready)
);

AES_128_Decipher_Block dec_block (
    .clk(clk),
    .reset_n(reset_n),
    .next(dec_next),
    .round_key(round_key),
    .block(block),

    .round(dec_round_nr),
    .new_block(dec_new_block),
    .ready(dec_ready)
);

AES_128_Key_Mem keymem (
    .clk(clk),
    .reset_n(reset_n),
    .key(key),
    .init(init),
    .round(muxed_round_nr),
    .sbox(keymem_sbox),

    .round_key(round_key),
    .ready(key_ready),
    .new_sbox(new_sbox)
);

AES_Sbox sbox_inst (
    .sbox(muxed_sbox),
    .new_sbox(new_sbox)
);




assign ready = ready_reg;
assign result = muxed_new_block;
assign result_valid = result_valid_reg;








always @(posedge clk or negedge reset_n) begin: reg_update
    if (!reset_n) begin
        result_valid_reg <= 1'b0;
        ready_reg <= 1'b1;
        aes_core_ctrl_reg <= CTRL_IDLE;
    end
    else begin
        if (result_valid_we)
            result_valid_reg <= result_valid_new;
        if (ready_we)
            ready_reg <= ready_new;
        if (aes_core_ctrl_we)
            aes_core_ctrl_reg <= aes_core_ctrl_new;
    end
end







always @(*) begin: sbox_mux
    if (init_state)
        muxed_sbox = keymem_sbox;
    else 
        muxed_sbox = enc_sbox;
end








always @(*) begin: encdex_mux
    enc_next = 1'b0;
    dec_next = 1'b0;

    if (encdec) begin

        enc_next = next;
        muxed_round_nr = enc_round_nr;
        muxed_new_block = enc_new_block;
        muxed_ready = enc_ready;
    end
    else begin

        dec_next = next;
        muxed_round_nr = dec_round_nr;
        muxed_new_block = dec_new_block;
        muxed_ready = dec_ready;
    end
end









always @(*) begin: aes_core_ctrl
    init_state = 1'b0;
    ready_new = 1'b0;
    ready_we = 1'b0;
    result_valid_new = 1'b0;
    result_valid_we = 1'b0;
    aes_core_ctrl_new = CTRL_IDLE;
    aes_core_ctrl_we = 1'b0;
    
    case (aes_core_ctrl_reg)
        CTRL_IDLE: begin
            if (init) begin
                init_state = 1'b1;
                ready_new = 1'b0;
                ready_we = 1'b1;
                result_valid_new = 1'b0;
                result_valid_we = 1'b1;
                aes_core_ctrl_new = CTRL_INIT;
                aes_core_ctrl_we = 1'b1;
            end
            else if (next) begin
                init_state = 1'b0;
                ready_new = 1'b0;
                ready_we = 1'b1;
                result_valid_new = 1'b0;
                result_valid_we = 1'b1;
                aes_core_ctrl_new = CTRL_NEXT;
                aes_core_ctrl_we = 1'b1;
            end
        end

        CTRL_INIT: begin
            init_state = 1'b1;

            if (key_ready) begin
                ready_new = 1'b1;
                ready_we = 1'b1;
                aes_core_ctrl_new = CTRL_IDLE;
                aes_core_ctrl_we = 1'b1;
            end
        end

        CTRL_NEXT: begin
            init_state = 1'b0;

            if (muxed_ready) begin
                ready_new = 1'b1;
                ready_we = 1'b1;
                result_valid_new = 1'b1;
                result_valid_we = 1'b1;
                aes_core_ctrl_new = CTRL_IDLE;
                aes_core_ctrl_we = 1'b1;
            end
        end

        default: begin
        end
    endcase
end


endmodule