data/full_repos/permissive/463555432/Codes/amsg_prewitt_h.v
1: b'%Warning-WIDTH: data/full_repos/permissive/463555432/Codes/amsg_prewitt_h.v:13: Operator SUB expects 16 bits on the LHS, but LHS\'s VARREF \'add4\' generates 9 bits.\n                                                                              : ... In instance AMSG_prewitt_h\n    assign ys1 = add4 - add3;\n                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/463555432/Codes/amsg_prewitt_h.v:13: Operator SUB expects 16 bits on the RHS, but RHS\'s VARREF \'add3\' generates 9 bits.\n                                                                              : ... In instance AMSG_prewitt_h\n    assign ys1 = add4 - add3;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/463555432/Codes/amsg_prewitt_h.v:19: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'ys1\' generates 16 bits.\n                                                                              : ... In instance AMSG_prewitt_h\n      y1 <= ys1;\n         ^~\n%Error: Exiting due to 3 warning(s)\n'
module AMSG_prewitt_h(
  input [7:0] p1, p2, p3, p7, p8, p9,
  output reg [7:0] y1
    );
    wire [15:0] ys1;
    wire [8:0] add1, add2, add3, add4;
    assign add1 = p1 + p2;
    assign add2 = p7 + p8;
    assign add3 = add1 + p3;
    assign add4 = add2 + p9;
    assign ys1 = add4 - add3;
    always@(ys1)
    begin
    if(ys1 > 255)
      y1 <= 255;
    else
      y1 <= ys1;
    end
endmodule
module AMSG_prewitt_h(
  input [7:0] p1, p2, p3, p7, p8, p9,
  output reg [7:0] y1
    );

    wire [15:0] ys1;
    wire [8:0] add1, add2, add3, add4;
    assign add1 = p1 + p2;
    assign add2 = p7 + p8;
    assign add3 = add1 + p3;
    assign add4 = add2 + p9;
    assign ys1 = add4 - add3;
    always@(ys1)
    begin
    if(ys1 > 255)
      y1 <= 255;
    else
      y1 <= ys1;
    end
endmodule