data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/bram_mem_true_dual.v
1: b'%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/bram_mem_true_dual.v:33: Cannot find include file: nf_sume_blueswitch_register_define.v\n`include "nf_sume_blueswitch_register_define.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog,data/full_repos/permissive/498471995/nf_sume_blueswitch_register_define.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog,data/full_repos/permissive/498471995/nf_sume_blueswitch_register_define.v.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog,data/full_repos/permissive/498471995/nf_sume_blueswitch_register_define.v.sv\n             nf_sume_blueswitch_register_define.v\n             nf_sume_blueswitch_register_define.v.v\n             nf_sume_blueswitch_register_define.v.sv\n             obj_dir/nf_sume_blueswitch_register_define.v\n             obj_dir/nf_sume_blueswitch_register_define.v.v\n             obj_dir/nf_sume_blueswitch_register_define.v.sv\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/bram_mem_true_dual.v:34: Cannot find include file: nf_sume_blueswitch_parameter_define.v\n`include "nf_sume_blueswitch_parameter_define.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module bram_mem_true_dual
#(
   parameter   ADDR_WIDTH   =  32,
   parameter   DATA_WIDTH   =  32
)
(
   input                         CLK_0,
   input                         WR_0,
   input    [ADDR_WIDTH-1:0]     ADDR_WR_0,
   input    [DATA_WIDTH-1:0]     DIN_0,
   input                         RD_0,
   input    [ADDR_WIDTH-1:0]     ADDR_RD_0,
   output   [DATA_WIDTH-1:0]     DOUT_0,

   input                         CLK_1,
   input                         WR_1,
   input    [ADDR_WIDTH-1:0]     ADDR_WR_1,
   input    [DATA_WIDTH-1:0]     DIN_1,
   input                         RD_1,
   input    [ADDR_WIDTH-1:0]     ADDR_RD_1,
   output   [DATA_WIDTH-1:0]     DOUT_1
);

`ifdef XIL_BRAM

wire  [ADDR_WIDTH-1:0]  addra = (WR_0) ? ADDR_WR_0 : ADDR_RD_0;
wire  [ADDR_WIDTH-1:0]  addrb = (WR_1) ? ADDR_WR_1 : ADDR_RD_1;

generate
   if (ADDR_WIDTH == 4) begin
      if (DATA_WIDTH == 16) begin : true_dual16x16
         true_dual16x16 true_dual16x16 (
            .clka    (  CLK_0          ),
            .ena     (  RD_0  |  WR_0  ),
            .wea     (  WR_0           ),
            .addra   (  addra          ),
            .dina    (  DIN_0          ),
            .douta   (  DOUT_0         ),
            .clkb    (  CLK_1          ),
            .enb     (  RD_1  |  WR_1  ),
            .web     (  WR_1           ),
            .addrb   (  addrb          ),
            .dinb    (  DIN_1          ),
            .doutb   (  DOUT_1         )
         );
      end
      else if (DATA_WIDTH == 32) begin : true_dual16x32
         true_dual16x32 true_dual16x32 (
            .clka    (  CLK_0          ),
            .ena     (  RD_0  |  WR_0  ),
            .wea     (  WR_0           ),
            .addra   (  addra          ),
            .dina    (  DIN_0          ),
            .douta   (  DOUT_0         ),
            .clkb    (  CLK_1          ),
            .enb     (  RD_1  |  WR_1  ),
            .web     (  WR_1           ),
            .addrb   (  addrb          ),
            .dinb    (  DIN_1          ),
            .doutb   (  DOUT_1         )
         );
      end
      else if (DATA_WIDTH == 48) begin : true_dual16x48
         true_dual16x48 true_dual16x48 (
            .clka    (  CLK_0          ),
            .ena     (  RD_0  |  WR_0  ),
            .wea     (  WR_0           ),
            .addra   (  addra          ),
            .dina    (  DIN_0          ),
            .douta   (  DOUT_0         ),
            .clkb    (  CLK_1          ),
            .enb     (  RD_1  |  WR_1  ),
            .web     (  WR_1           ),
            .addrb   (  addrb          ),
            .dinb    (  RD_1           ),
            .doutb   (  DOUT_1         )
         );
      end
   end
   else if (ADDR_WIDTH == 5) begin
      if (DATA_WIDTH == 16) begin : true_dual32x16
         true_dual32x16 true_dual32x16 (
            .clka    (  CLK_0          ),
            .ena     (  RD_0  |  WR_0  ),
            .wea     (  WR_0           ),
            .addra   (  addra          ),
            .dina    (  DIN_0          ),
            .douta   (  DOUT_0         ),
            .clkb    (  CLK_1          ),
            .enb     (  RD_1  |  WR_1  ),
            .web     (  WR_1           ),
            .addrb   (  addrb          ),
            .dinb    (  DIN_1          ),
            .doutb   (  DOUT_1         )
         );
      end
      else if (DATA_WIDTH == 32) begin : true_dual32x32
         true_dual32x32 true_dual32x32 (
            .clka    (  CLK_0          ),
            .ena     (  RD_0  |  WR_0  ),
            .wea     (  WR_0           ),
            .addra   (  addra          ),
            .dina    (  DIN_0          ),
            .douta   (  DOUT_0         ),
            .clkb    (  CLK_1          ),
            .enb     (  RD_1  |  WR_1  ),
            .web     (  WR_1           ),
            .addrb   (  addrb          ),
            .dinb    (  DIN_1          ),
            .doutb   (  DOUT_1         )
         );
      end
      else if (DATA_WIDTH == 48) begin : true_dual32x48
         true_dual32x48 true_dual32x48 (
            .clka    (  CLK_0    ),
            .ena     (  RD_0  |  WR_0  ),
            .wea     (  WR_0           ),
            .addra   (  addra          ),
            .dina    (  DIN_0          ),
            .douta   (  DOUT_0         ),
            .clkb    (  CLK_1          ),
            .enb     (  RD_1  |  WR_1  ),
            .web     (  WR_1           ),
            .addrb   (  addrb          ),
            .dinb    (  DIN_1          ),
            .doutb   (  DOUT_1         )
         );
      end
   end
endgenerate

`else

(* RAM_STYLE = "BLOCK" *)
reg   [DATA_WIDTH-1:0]  mem[(2**ADDR_WIDTH)-1:0];
reg   [ADDR_WIDTH-1:0]  rd_addr_0, rd_addr_1;

always @(posedge CLK_0) begin
   if (WR_0)  mem[ADDR_WR_0]   <= DIN_0;
end

always @(posedge CLK_1) begin
   if (WR_1)  mem[ADDR_WR_1]   <= DIN_1;
end

always @(posedge CLK_0) begin
   if (RD_0)  rd_addr_0 <= ADDR_RD_0;
end

always @(posedge CLK_1) begin
   if (RD_1)  rd_addr_1 <= ADDR_RD_1;
end

assign   DOUT_0  =  mem[rd_addr_0];
assign   DOUT_1  =  mem[rd_addr_1];

`endif

endmodule
module bram_mem_true_dual
#(
   parameter   ADDR_WIDTH   =  32,
   parameter   DATA_WIDTH   =  32
)
(
   input                         CLK_0,
   input                         WR_0,
   input    [ADDR_WIDTH-1:0]     ADDR_WR_0,
   input    [DATA_WIDTH-1:0]     DIN_0,
   input                         RD_0,
   input    [ADDR_WIDTH-1:0]     ADDR_RD_0,
   output   [DATA_WIDTH-1:0]     DOUT_0,

   input                         CLK_1,
   input                         WR_1,
   input    [ADDR_WIDTH-1:0]     ADDR_WR_1,
   input    [DATA_WIDTH-1:0]     DIN_1,
   input                         RD_1,
   input    [ADDR_WIDTH-1:0]     ADDR_RD_1,
   output   [DATA_WIDTH-1:0]     DOUT_1
);


`ifdef XIL_BRAM

wire  [ADDR_WIDTH-1:0]  addra = (WR_0) ? ADDR_WR_0 : ADDR_RD_0;
wire  [ADDR_WIDTH-1:0]  addrb = (WR_1) ? ADDR_WR_1 : ADDR_RD_1;

generate
   if (ADDR_WIDTH == 4) begin
      if (DATA_WIDTH == 16) begin : true_dual16x16
         true_dual16x16 true_dual16x16 (
            .clka    (  CLK_0          ),
            .ena     (  RD_0  |  WR_0  ),
            .wea     (  WR_0           ),
            .addra   (  addra          ),
            .dina    (  DIN_0          ),
            .douta   (  DOUT_0         ),
            .clkb    (  CLK_1          ),
            .enb     (  RD_1  |  WR_1  ),
            .web     (  WR_1           ),
            .addrb   (  addrb          ),
            .dinb    (  DIN_1          ),
            .doutb   (  DOUT_1         )
         );
      end
      else if (DATA_WIDTH == 32) begin : true_dual16x32
         true_dual16x32 true_dual16x32 (
            .clka    (  CLK_0          ),
            .ena     (  RD_0  |  WR_0  ),
            .wea     (  WR_0           ),
            .addra   (  addra          ),
            .dina    (  DIN_0          ),
            .douta   (  DOUT_0         ),
            .clkb    (  CLK_1          ),
            .enb     (  RD_1  |  WR_1  ),
            .web     (  WR_1           ),
            .addrb   (  addrb          ),
            .dinb    (  DIN_1          ),
            .doutb   (  DOUT_1         )
         );
      end
      else if (DATA_WIDTH == 48) begin : true_dual16x48
         true_dual16x48 true_dual16x48 (
            .clka    (  CLK_0          ),
            .ena     (  RD_0  |  WR_0  ),
            .wea     (  WR_0           ),
            .addra   (  addra          ),
            .dina    (  DIN_0          ),
            .douta   (  DOUT_0         ),
            .clkb    (  CLK_1          ),
            .enb     (  RD_1  |  WR_1  ),
            .web     (  WR_1           ),
            .addrb   (  addrb          ),
            .dinb    (  RD_1           ),
            .doutb   (  DOUT_1         )
         );
      end
   end
   else if (ADDR_WIDTH == 5) begin
      if (DATA_WIDTH == 16) begin : true_dual32x16
         true_dual32x16 true_dual32x16 (
            .clka    (  CLK_0          ),
            .ena     (  RD_0  |  WR_0  ),
            .wea     (  WR_0           ),
            .addra   (  addra          ),
            .dina    (  DIN_0          ),
            .douta   (  DOUT_0         ),
            .clkb    (  CLK_1          ),
            .enb     (  RD_1  |  WR_1  ),
            .web     (  WR_1           ),
            .addrb   (  addrb          ),
            .dinb    (  DIN_1          ),
            .doutb   (  DOUT_1         )
         );
      end
      else if (DATA_WIDTH == 32) begin : true_dual32x32
         true_dual32x32 true_dual32x32 (
            .clka    (  CLK_0          ),
            .ena     (  RD_0  |  WR_0  ),
            .wea     (  WR_0           ),
            .addra   (  addra          ),
            .dina    (  DIN_0          ),
            .douta   (  DOUT_0         ),
            .clkb    (  CLK_1          ),
            .enb     (  RD_1  |  WR_1  ),
            .web     (  WR_1           ),
            .addrb   (  addrb          ),
            .dinb    (  DIN_1          ),
            .doutb   (  DOUT_1         )
         );
      end
      else if (DATA_WIDTH == 48) begin : true_dual32x48
         true_dual32x48 true_dual32x48 (
            .clka    (  CLK_0    ),
            .ena     (  RD_0  |  WR_0  ),
            .wea     (  WR_0           ),
            .addra   (  addra          ),
            .dina    (  DIN_0          ),
            .douta   (  DOUT_0         ),
            .clkb    (  CLK_1          ),
            .enb     (  RD_1  |  WR_1  ),
            .web     (  WR_1           ),
            .addrb   (  addrb          ),
            .dinb    (  DIN_1          ),
            .doutb   (  DOUT_1         )
         );
      end
   end
endgenerate

`else

(* RAM_STYLE = "BLOCK" *)
reg   [DATA_WIDTH-1:0]  mem[(2**ADDR_WIDTH)-1:0];
reg   [ADDR_WIDTH-1:0]  rd_addr_0, rd_addr_1;

always @(posedge CLK_0) begin
   if (WR_0)  mem[ADDR_WR_0]   <= DIN_0;
end

always @(posedge CLK_1) begin
   if (WR_1)  mem[ADDR_WR_1]   <= DIN_1;
end

always @(posedge CLK_0) begin
   if (RD_0)  rd_addr_0 <= ADDR_RD_0;
end

always @(posedge CLK_1) begin
   if (RD_1)  rd_addr_1 <= ADDR_RD_1;
end

assign   DOUT_0  =  mem[rd_addr_0];
assign   DOUT_1  =  mem[rd_addr_1];

`endif

endmodule