data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v
1: b'%Error: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:2: Cannot find include file: q3.v\n`include "q3.v" \n         ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/528677531/LAB-3/Q3,data/full_repos/permissive/528677531/q3.v\n             data/full_repos/permissive/528677531/LAB-3/Q3,data/full_repos/permissive/528677531/q3.v.v\n             data/full_repos/permissive/528677531/LAB-3/Q3,data/full_repos/permissive/528677531/q3.v.sv\n             q3.v\n             q3.v.v\n             q3.v.sv\n             obj_dir/q3.v\n             obj_dir/q3.v.v\n             obj_dir/q3.v.sv\n%Error: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:9: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("q3_tb.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:10: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0,q3_tb);\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b0; x2=1\'b0; x3=1\'b0; x4=1\'b0; x5=1\'b0; #20;\n                                             ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b0; x2=1\'b0; x3=1\'b0; x4=1\'b0; x5=1\'b1; #20;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b0; x2=1\'b0; x3=1\'b0; x4=1\'b1; x5=1\'b0; #20;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b0; x2=1\'b0; x3=1\'b0; x4=1\'b1; x5=1\'b1; #20;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b0; x2=1\'b0; x3=1\'b1; x4=1\'b0; x5=1\'b0; #20;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b0; x2=1\'b0; x3=1\'b1; x4=1\'b0; x5=1\'b1; #20;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b0; x2=1\'b0; x3=1\'b1; x4=1\'b1; x5=1\'b0; #20;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b0; x2=1\'b0; x3=1\'b1; x4=1\'b1; x5=1\'b1; #20;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b0; x2=1\'b1; x3=1\'b0; x4=1\'b0; x5=1\'b0; #20;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b0; x2=1\'b1; x3=1\'b0; x4=1\'b0; x5=1\'b1; #20;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b0; x2=1\'b1; x3=1\'b0; x4=1\'b1; x5=1\'b0; #20;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b0; x2=1\'b1; x3=1\'b0; x4=1\'b1; x5=1\'b1; #20;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b0; x2=1\'b1; x3=1\'b1; x4=1\'b0; x5=1\'b0; #20;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b0; x2=1\'b1; x3=1\'b1; x4=1\'b0; x5=1\'b1; #20;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b0; x2=1\'b1; x3=1\'b1; x4=1\'b1; x5=1\'b0; #20;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b0; x2=1\'b1; x3=1\'b1; x4=1\'b1; x5=1\'b1; #20;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b1; x2=1\'b0; x3=1\'b0; x4=1\'b0; x5=1\'b0; #20;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b1; x2=1\'b0; x3=1\'b0; x4=1\'b0; x5=1\'b1; #20;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b1; x2=1\'b0; x3=1\'b0; x4=1\'b1; x5=1\'b0; #20;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b1; x2=1\'b0; x3=1\'b0; x4=1\'b1; x5=1\'b1; #20;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b1; x2=1\'b0; x3=1\'b1; x4=1\'b0; x5=1\'b0; #20;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b1; x2=1\'b0; x3=1\'b1; x4=1\'b0; x5=1\'b1; #20;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b1; x2=1\'b0; x3=1\'b1; x4=1\'b1; x5=1\'b0; #20;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b1; x2=1\'b0; x3=1\'b1; x4=1\'b1; x5=1\'b1; #20;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b1; x2=1\'b1; x3=1\'b0; x4=1\'b0; x5=1\'b0; #20;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b1; x2=1\'b1; x3=1\'b0; x4=1\'b0; x5=1\'b1; #20;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b1; x2=1\'b1; x3=1\'b0; x4=1\'b1; x5=1\'b0; #20;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b1; x2=1\'b1; x3=1\'b0; x4=1\'b1; x5=1\'b1; #20;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b1; x2=1\'b1; x3=1\'b1; x4=1\'b0; x5=1\'b0; #20;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b1; x2=1\'b1; x3=1\'b1; x4=1\'b0; x5=1\'b1; #20;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b1; x2=1\'b1; x3=1\'b1; x4=1\'b1; x5=1\'b0; #20;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-3/Q3/q3_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b1; x2=1\'b1; x3=1\'b1; x4=1\'b1; x5=1\'b1; #20;\n                                             ^\n%Error: Exiting due to 3 error(s), 32 warning(s)\n'
module q3_tb();
reg x1,x2,x3,x4,x5;
wire f;
q3 q3(x1,x2,x3,x4,x5,f);
initial
begin
$dumpfile("q3_tb.vcd");
$dumpvars(0,q3_tb);

x1=1'b0; x2=1'b0; x3=1'b0; x4=1'b0; x5=1'b0; #20;
x1=1'b0; x2=1'b0; x3=1'b0; x4=1'b0; x5=1'b1; #20;
x1=1'b0; x2=1'b0; x3=1'b0; x4=1'b1; x5=1'b0; #20;
x1=1'b0; x2=1'b0; x3=1'b0; x4=1'b1; x5=1'b1; #20;
x1=1'b0; x2=1'b0; x3=1'b1; x4=1'b0; x5=1'b0; #20;
x1=1'b0; x2=1'b0; x3=1'b1; x4=1'b0; x5=1'b1; #20;
x1=1'b0; x2=1'b0; x3=1'b1; x4=1'b1; x5=1'b0; #20;
x1=1'b0; x2=1'b0; x3=1'b1; x4=1'b1; x5=1'b1; #20;
x1=1'b0; x2=1'b1; x3=1'b0; x4=1'b0; x5=1'b0; #20;
x1=1'b0; x2=1'b1; x3=1'b0; x4=1'b0; x5=1'b1; #20;
x1=1'b0; x2=1'b1; x3=1'b0; x4=1'b1; x5=1'b0; #20;
x1=1'b0; x2=1'b1; x3=1'b0; x4=1'b1; x5=1'b1; #20;
x1=1'b0; x2=1'b1; x3=1'b1; x4=1'b0; x5=1'b0; #20;
x1=1'b0; x2=1'b1; x3=1'b1; x4=1'b0; x5=1'b1; #20;
x1=1'b0; x2=1'b1; x3=1'b1; x4=1'b1; x5=1'b0; #20;
x1=1'b0; x2=1'b1; x3=1'b1; x4=1'b1; x5=1'b1; #20;
x1=1'b1; x2=1'b0; x3=1'b0; x4=1'b0; x5=1'b0; #20;
x1=1'b1; x2=1'b0; x3=1'b0; x4=1'b0; x5=1'b1; #20;
x1=1'b1; x2=1'b0; x3=1'b0; x4=1'b1; x5=1'b0; #20;
x1=1'b1; x2=1'b0; x3=1'b0; x4=1'b1; x5=1'b1; #20;
x1=1'b1; x2=1'b0; x3=1'b1; x4=1'b0; x5=1'b0; #20;
x1=1'b1; x2=1'b0; x3=1'b1; x4=1'b0; x5=1'b1; #20;
x1=1'b1; x2=1'b0; x3=1'b1; x4=1'b1; x5=1'b0; #20;
x1=1'b1; x2=1'b0; x3=1'b1; x4=1'b1; x5=1'b1; #20;
x1=1'b1; x2=1'b1; x3=1'b0; x4=1'b0; x5=1'b0; #20;
x1=1'b1; x2=1'b1; x3=1'b0; x4=1'b0; x5=1'b1; #20;
x1=1'b1; x2=1'b1; x3=1'b0; x4=1'b1; x5=1'b0; #20;
x1=1'b1; x2=1'b1; x3=1'b0; x4=1'b1; x5=1'b1; #20;
x1=1'b1; x2=1'b1; x3=1'b1; x4=1'b0; x5=1'b0; #20;
x1=1'b1; x2=1'b1; x3=1'b1; x4=1'b0; x5=1'b1; #20;
x1=1'b1; x2=1'b1; x3=1'b1; x4=1'b1; x5=1'b0; #20;
x1=1'b1; x2=1'b1; x3=1'b1; x4=1'b1; x5=1'b1; #20;

$display("Test x4omplete");
end
endmodule
module q3_tb();

reg x1,x2,x3,x4,x5;
wire f;
q3 q3(x1,x2,x3,x4,x5,f);
initial
begin
$dumpfile("q3_tb.vcd");
$dumpvars(0,q3_tb);

x1=1'b0; x2=1'b0; x3=1'b0; x4=1'b0; x5=1'b0; #20;
x1=1'b0; x2=1'b0; x3=1'b0; x4=1'b0; x5=1'b1; #20;
x1=1'b0; x2=1'b0; x3=1'b0; x4=1'b1; x5=1'b0; #20;
x1=1'b0; x2=1'b0; x3=1'b0; x4=1'b1; x5=1'b1; #20;
x1=1'b0; x2=1'b0; x3=1'b1; x4=1'b0; x5=1'b0; #20;
x1=1'b0; x2=1'b0; x3=1'b1; x4=1'b0; x5=1'b1; #20;
x1=1'b0; x2=1'b0; x3=1'b1; x4=1'b1; x5=1'b0; #20;
x1=1'b0; x2=1'b0; x3=1'b1; x4=1'b1; x5=1'b1; #20;
x1=1'b0; x2=1'b1; x3=1'b0; x4=1'b0; x5=1'b0; #20;
x1=1'b0; x2=1'b1; x3=1'b0; x4=1'b0; x5=1'b1; #20;
x1=1'b0; x2=1'b1; x3=1'b0; x4=1'b1; x5=1'b0; #20;
x1=1'b0; x2=1'b1; x3=1'b0; x4=1'b1; x5=1'b1; #20;
x1=1'b0; x2=1'b1; x3=1'b1; x4=1'b0; x5=1'b0; #20;
x1=1'b0; x2=1'b1; x3=1'b1; x4=1'b0; x5=1'b1; #20;
x1=1'b0; x2=1'b1; x3=1'b1; x4=1'b1; x5=1'b0; #20;
x1=1'b0; x2=1'b1; x3=1'b1; x4=1'b1; x5=1'b1; #20;
x1=1'b1; x2=1'b0; x3=1'b0; x4=1'b0; x5=1'b0; #20;
x1=1'b1; x2=1'b0; x3=1'b0; x4=1'b0; x5=1'b1; #20;
x1=1'b1; x2=1'b0; x3=1'b0; x4=1'b1; x5=1'b0; #20;
x1=1'b1; x2=1'b0; x3=1'b0; x4=1'b1; x5=1'b1; #20;
x1=1'b1; x2=1'b0; x3=1'b1; x4=1'b0; x5=1'b0; #20;
x1=1'b1; x2=1'b0; x3=1'b1; x4=1'b0; x5=1'b1; #20;
x1=1'b1; x2=1'b0; x3=1'b1; x4=1'b1; x5=1'b0; #20;
x1=1'b1; x2=1'b0; x3=1'b1; x4=1'b1; x5=1'b1; #20;
x1=1'b1; x2=1'b1; x3=1'b0; x4=1'b0; x5=1'b0; #20;
x1=1'b1; x2=1'b1; x3=1'b0; x4=1'b0; x5=1'b1; #20;
x1=1'b1; x2=1'b1; x3=1'b0; x4=1'b1; x5=1'b0; #20;
x1=1'b1; x2=1'b1; x3=1'b0; x4=1'b1; x5=1'b1; #20;
x1=1'b1; x2=1'b1; x3=1'b1; x4=1'b0; x5=1'b0; #20;
x1=1'b1; x2=1'b1; x3=1'b1; x4=1'b0; x5=1'b1; #20;
x1=1'b1; x2=1'b1; x3=1'b1; x4=1'b1; x5=1'b0; #20;
x1=1'b1; x2=1'b1; x3=1'b1; x4=1'b1; x5=1'b1; #20;

$display("Test x4omplete");
end
endmodule