data/full_repos/permissive/472097485/Chu03/BcdInc_03/BoardTest.v
1: b"%Error: data/full_repos/permissive/472097485/Chu03/BcdInc_03/BoardTest.v:14: Cannot find file containing module: 'BcdInc'\n BcdInc dig1( bt[3:0], 1'b1, r1, c1 );\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/472097485/Chu03/BcdInc_03,data/full_repos/permissive/472097485/BcdInc\n             data/full_repos/permissive/472097485/Chu03/BcdInc_03,data/full_repos/permissive/472097485/BcdInc.v\n             data/full_repos/permissive/472097485/Chu03/BcdInc_03,data/full_repos/permissive/472097485/BcdInc.sv\n             BcdInc\n             BcdInc.v\n             BcdInc.sv\n             obj_dir/BcdInc\n             obj_dir/BcdInc.v\n             obj_dir/BcdInc.sv\n%Error: data/full_repos/permissive/472097485/Chu03/BcdInc_03/BoardTest.v:15: Cannot find file containing module: 'BcdInc'\n BcdInc dig2( dp[3:0], c1, r2, c2 );\n ^~~~~~\n%Error: data/full_repos/permissive/472097485/Chu03/BcdInc_03/BoardTest.v:16: Cannot find file containing module: 'BcdInc'\n BcdInc dig3( dp[7:4], c2, r3, c3 );\n ^~~~~~\n%Error: data/full_repos/permissive/472097485/Chu03/BcdInc_03/BoardTest.v:21: Cannot find file containing module: 'Hex2Sseg'\n Hex2Sseg seg1( r1, c1, ss1 );\n ^~~~~~~~\n%Error: data/full_repos/permissive/472097485/Chu03/BcdInc_03/BoardTest.v:22: Cannot find file containing module: 'Hex2Sseg'\n Hex2Sseg seg2( r2, c2, ss2 );\n ^~~~~~~~\n%Error: data/full_repos/permissive/472097485/Chu03/BcdInc_03/BoardTest.v:23: Cannot find file containing module: 'Hex2Sseg'\n Hex2Sseg seg3( r3, c3, ss3 );\n ^~~~~~~~\n%Error: data/full_repos/permissive/472097485/Chu03/BcdInc_03/BoardTest.v:25: Cannot find file containing module: 'SsegMux'\n SsegMux sm( clk, 1'b0, ss3, ss2, ss1, en, ss );\n ^~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module BoardTest( input wire clk, input wire [7:0] dp, input wire [3:0] bt, output wire [7:0] ss, output wire [2:0] en );


	wire [3:0] r1, r2, r3;
	wire c1, c2, c3;
	wire [7:0] ss1, ss2, ss3;

	BcdInc dig1( bt[3:0], 1'b1, r1, c1 );
	BcdInc dig2( dp[3:0], c1, r2, c2 );
	BcdInc dig3( dp[7:4], c2, r3, c3 );
	


	
	Hex2Sseg seg1( r1, c1, ss1 );
	Hex2Sseg seg2( r2, c2, ss2 );
	Hex2Sseg seg3( r3, c3, ss3 );
	
	SsegMux sm( clk, 1'b0, ss3, ss2, ss1, en, ss );

endmodule
module BoardTest( input wire clk, input wire [7:0] dp, input wire [3:0] bt, output wire [7:0] ss, output wire [2:0] en );



	wire [3:0] r1, r2, r3;
	wire c1, c2, c3;
	wire [7:0] ss1, ss2, ss3;

	BcdInc dig1( bt[3:0], 1'b1, r1, c1 );
	BcdInc dig2( dp[3:0], c1, r2, c2 );
	BcdInc dig3( dp[7:4], c2, r3, c3 );
	


	
	Hex2Sseg seg1( r1, c1, ss1 );
	Hex2Sseg seg2( r2, c2, ss2 );
	Hex2Sseg seg3( r3, c3, ss3 );
	
	SsegMux sm( clk, 1'b0, ss3, ss2, ss1, en, ss );

endmodule