data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/lib/dff_full/dff_full.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/lib/dff_full/dff_full.v:19: Multiple top level modules\n                                                                                                               : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                               : ... Top module \'MUX\'\nmodule MUX\n       ^~~\n                                                                                                               : ... Top module \'HADDER\'\nmodule HADDER\n       ^~~~~~\n                                                                                                               : ... Top module \'FADDER\'\nmodule FADDER\n       ^~~~~~\n                                                                                                               : ... Top module \'AND\'\nmodule AND\n       ^~~\n                                                                                                               : ... Top module \'ANDN\'\nmodule ANDN\n       ^~~~\n                                                                                                               : ... Top module \'NAND\'\nmodule NAND\n       ^~~~\n                                                                                                               : ... Top module \'NANDN\'\nmodule NANDN\n       ^~~~~\n                                                                                                               : ... Top module \'OR\'\nmodule OR\n       ^~\n                                                                                                               : ... Top module \'ORN\'\nmodule ORN\n       ^~~\n                                                                                                               : ... Top module \'NOR\'\nmodule NOR\n       ^~~\n                                                                                                               : ... Top module \'NORN\'\nmodule NORN\n       ^~~~\n                                                                                                               : ... Top module \'XOR\'\nmodule XOR\n       ^~~\n                                                                                                               : ... Top module \'XNOR\'\nmodule XNOR\n       ^~~~\n                                                                                                               : ... Top module \'IV\'\nmodule IV\n       ^~\n                                                                                                               : ... Top module \'DFF\'\nmodule DFF\n       ^~~\n%Error: Exiting due to 1 warning(s)\n'
module NAND
( 
  A, 
  B,
  Z
);

  input A, B;
  output Z;

  assign Z = ~(A&B);

endmodule
module NAND
( 
  A, 
  B,
  Z
);


  input A, B;
  output Z;

  assign Z = ~(A&B);

endmodule