data/full_repos/permissive/427281804/FPU/verilog/sp_sram.v
data/verilator_xmls/63433cdf-d365-42b6-b0b8-e43562ae6a40.xml
module sp_sram #(
	parameter ADDR_WIDTH = 4,
	parameter DATA_WIDTH = 16,
	parameter DEPTH = 2**ADDR_WIDTH   
)(
	input                       clk,
	input [ADDR_WIDTH-1:0]      addr,
	input [DATA_WIDTH-1:0]      din,
	input                       wr,
	output reg [DATA_WIDTH-1:0] qout
);

reg [DATA_WIDTH-1:0] mem [DEPTH-1:0];
always @(posedge clk) begin
	if(wr) begin
		mem[addr] <= din;
		qout      <= {DATA_WIDTH{1'bx}};
	end else 
		qout      <= mem[addr];
end

endmodule
module sp_sram #(
	parameter ADDR_WIDTH = 4,
	parameter DATA_WIDTH = 16,
	parameter DEPTH = 2**ADDR_WIDTH   
)(
	input                       clk,
	input [ADDR_WIDTH-1:0]      addr,
	input [DATA_WIDTH-1:0]      din,
	input                       wr,
	output reg [DATA_WIDTH-1:0] qout
);


reg [DATA_WIDTH-1:0] mem [DEPTH-1:0];
always @(posedge clk) begin
	if(wr) begin
		mem[addr] <= din;
		qout      <= {DATA_WIDTH{1'bx}};
	end else 
		qout      <= mem[addr];
end

endmodule