data/full_repos/permissive/441359809/src/yosys/tests/memories/firrtl_938.v
data/verilator_xmls/09e7f12d-43bc-4dee-90f6-bfcdf3c379a9.xml
module top
(
	input [7:0] data_a,
	input [6:1] addr_a,
	input we_a, clk,
	output reg [7:0] q_a
);

	reg [7:0] ram[63:0];


	always @ (posedge clk)
	begin
		if (we_a)
		begin
			ram[addr_a] <= data_a;
			q_a <= data_a;
		end
			q_a <= ram[addr_a];
	end

endmodule
module top
(
	input [7:0] data_a,
	input [6:1] addr_a,
	input we_a, clk,
	output reg [7:0] q_a
);


	reg [7:0] ram[63:0];


	always @ (posedge clk)
	begin
		if (we_a)
		begin
			ram[addr_a] <= data_a;
			q_a <= data_a;
		end
			q_a <= ram[addr_a];
	end

endmodule