data/full_repos/permissive/436253691/hardware/testbench/RAM_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/436253691/hardware/testbench/RAM_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #(tb_clk_period/2);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/436253691/hardware/testbench/RAM_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #(tb_clk_period/2);\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/RAM_tb.v:77: syntax error, unexpected \'@\'\n  @(negedge tb_clk)\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/RAM_tb.v:81: syntax error, unexpected \'@\'\n  @(posedge tb_clk)\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/RAM_tb.v:86: syntax error, unexpected \'@\'\n @(negedge tb_clk)\n ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/RAM_tb.v:92: syntax error, unexpected \'@\'\n @(posedge tb_clk)\n ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/RAM_tb.v:98: syntax error, unexpected \'@\'\n  @(negedge tb_clk)\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/RAM_tb.v:106: syntax error, unexpected \'@\'\n @(negedge tb_clk)\n ^\n%Error: Exiting due to 6 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module RAM_tb();


parameter tb_data_width=32;
parameter tb_mem_size=1024;
parameter tb_addr_width=10;
parameter tb_clk_period=20;
integer addr;
integer data;


reg tb_clk;
reg tb_we;
reg tb_oe;
reg [tb_addr_width-1:0] tb_addr;
reg [tb_data_width-1:0] tb_data_in;


wire [tb_data_width-1:0] tb_data_out;
reg  [tb_data_width-1:0] tb_expected_out;



RAM #(.DATA_WIDTH(tb_data_width),.MEM_SIZE(tb_mem_size),.ADDR_WIDTH(tb_addr_width)) Ram (

.RAM_Clk(tb_clk),
.RAM_We(tb_we),
.RAM_Oe(tb_oe),
.RAM_Address(tb_addr),
.RAM_Data_In(tb_data_in),
.RAM_Data_Out(tb_data_out)
);


always
begin
		tb_clk=1'b1;
		#(tb_clk_period/2);
		tb_clk=1'b0;
		#(tb_clk_period/2);
end


initial
begin
	tb_we<=0;
	tb_oe<=0;
	tb_addr<=0;
	tb_data_in<=0;
	data<=10;
	tb_expected_out<='hz;
	
	for (addr=0; addr<10;addr=addr+1)begin
		@(negedge tb_clk)
			tb_we<=1;
			tb_addr<=addr;
			tb_data_in<=data;
		@(posedge tb_clk)
			tb_we<=1;
			data<=data+10;
	end
	
	@(negedge tb_clk)
	tb_we<=0;
	tb_oe<=0;
	tb_addr<=0;
	tb_data_in<=0;
	data<=10;
	@(posedge tb_clk)
	tb_oe<=1;
	tb_expected_out<=data;
	data<=data+10;
	
	for (addr=1; addr<10;addr=addr+1)begin
		@(negedge tb_clk)
		tb_addr<=addr;
		@(posedge tb_clk)
		tb_expected_out<=data;
		data<=data+10;
		verify_output(tb_data_out,tb_expected_out);
	end
	
	@(negedge tb_clk)
	tb_oe<=0;
	tb_addr<=0;
	data<=10;
	
	$display($time," << Test passed >> ");
	
	$stop;
	
end

task verify_output;
	input [tb_data_width-1:0] out;
	input [tb_data_width-1:0] expected_out;
	
	begin
		if(expected_out==out)
			begin
				$display($time," << Correct Output >> ");
			end
		else
			begin
				$error($time," << Error - incorrect output, expected %d, given %d >> ",expected_out,out);
				$stop;
			end
	end
	
endtask




endmodule
module RAM_tb();



parameter tb_data_width=32;
parameter tb_mem_size=1024;
parameter tb_addr_width=10;
parameter tb_clk_period=20;
integer addr;
integer data;


reg tb_clk;
reg tb_we;
reg tb_oe;
reg [tb_addr_width-1:0] tb_addr;
reg [tb_data_width-1:0] tb_data_in;


wire [tb_data_width-1:0] tb_data_out;
reg  [tb_data_width-1:0] tb_expected_out;



RAM #(.DATA_WIDTH(tb_data_width),.MEM_SIZE(tb_mem_size),.ADDR_WIDTH(tb_addr_width)) Ram (

.RAM_Clk(tb_clk),
.RAM_We(tb_we),
.RAM_Oe(tb_oe),
.RAM_Address(tb_addr),
.RAM_Data_In(tb_data_in),
.RAM_Data_Out(tb_data_out)
);


always
begin
		tb_clk=1'b1;
		#(tb_clk_period/2);
		tb_clk=1'b0;
		#(tb_clk_period/2);
end


initial
begin
	tb_we<=0;
	tb_oe<=0;
	tb_addr<=0;
	tb_data_in<=0;
	data<=10;
	tb_expected_out<='hz;
	
	for (addr=0; addr<10;addr=addr+1)begin
		@(negedge tb_clk)
			tb_we<=1;
			tb_addr<=addr;
			tb_data_in<=data;
		@(posedge tb_clk)
			tb_we<=1;
			data<=data+10;
	end
	
	@(negedge tb_clk)
	tb_we<=0;
	tb_oe<=0;
	tb_addr<=0;
	tb_data_in<=0;
	data<=10;
	@(posedge tb_clk)
	tb_oe<=1;
	tb_expected_out<=data;
	data<=data+10;
	
	for (addr=1; addr<10;addr=addr+1)begin
		@(negedge tb_clk)
		tb_addr<=addr;
		@(posedge tb_clk)
		tb_expected_out<=data;
		data<=data+10;
		verify_output(tb_data_out,tb_expected_out);
	end
	
	@(negedge tb_clk)
	tb_oe<=0;
	tb_addr<=0;
	data<=10;
	
	$display($time," << Test passed >> ");
	
	$stop;
	
end

task verify_output;
	input [tb_data_width-1:0] out;
	input [tb_data_width-1:0] expected_out;
	
	begin
		if(expected_out==out)
			begin
				$display($time," << Correct Output >> ");
			end
		else
			begin
				$error($time," << Error - incorrect output, expected %d, given %d >> ",expected_out,out);
				$stop;
			end
	end
	
endtask




endmodule