data/full_repos/permissive/487082250/sources/letterdataflow.v
data/verilator_xmls/ba18396d-a76c-4c4f-8542-449663f94aa8.xml
module LDF(
input [4:0] d,
	output reg [6:0] seg
	);

always @ (d) begin
case (d)
0: seg <= 7'b0001000;
1: seg <= 7'b1100000;
2: seg <= 7'b0110001;
3: seg <= 7'b1000010;
4: seg <= 7'b0110000;
5: seg <= 7'b0111000;
6: seg <= 7'b1101000;
7: seg <= 7'b1110001;
8: seg <= 7'b1101010;
9: seg <= 7'b1100010;
10: seg <= 7'b0011000;
11: seg <= 7'b1111010;
12: seg <= 7'b0100100;
13: seg <= 7'b1000001;
14: seg <= 7'b1000100;

default:
seg <= 7'b1110111;
endcase
end
endmodule
module LDF(
input [4:0] d,
	output reg [6:0] seg
	);


always @ (d) begin
case (d)
0: seg <= 7'b0001000;
1: seg <= 7'b1100000;
2: seg <= 7'b0110001;
3: seg <= 7'b1000010;
4: seg <= 7'b0110000;
5: seg <= 7'b0111000;
6: seg <= 7'b1101000;
7: seg <= 7'b1110001;
8: seg <= 7'b1101010;
9: seg <= 7'b1100010;
10: seg <= 7'b0011000;
11: seg <= 7'b1111010;
12: seg <= 7'b0100100;
13: seg <= 7'b1000001;
14: seg <= 7'b1000100;

default:
seg <= 7'b1110111;
endcase
end
endmodule