data/full_repos/permissive/511902453/alu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/511902453/alu.v:117: Operator ADD expects 33 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                              : ... In instance alu.adder\n    assign {add_carry,add_result}=a+b+cin;\n                                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/511902453/alu.v:94: Operator SUB expects 6 bits on the RHS, but RHS\'s VARREF \'shiftctr\' generates 2 bits.\n                                                             : ... In instance alu.shifter\n  assign shift_n = 6\'d32 - shiftctr;\n                         ^\n%Error: Exiting due to 2 warning(s)\n'
module shifter(input [31:0] alu_da,
               input [4:0] alu_shift,
			   input [1:0] shiftctr,
			   output reg [31:0] shift_result);
			   

     wire [5:0] shift_n;
	 assign shift_n = 6'd32 - shiftctr;
     always@(*) begin
	   case(shiftctr)
	   2'b00:shift_result = alu_da << alu_shift;
	   2'b01:shift_result = alu_da >> alu_shift;
	   2'b10:shift_result = ({32{alu_da[31]}} << shift_n) | (alu_da >> alu_shift);
	   default:shift_result = alu_da;
	   endcase
	 end


endmodule
module shifter(input [31:0] alu_da,
               input [4:0] alu_shift,
			   input [1:0] shiftctr,
			   output reg [31:0] shift_result);

			   

     wire [5:0] shift_n;
	 assign shift_n = 6'd32 - shiftctr;
     always@(*) begin
	   case(shiftctr)
	   2'b00:shift_result = alu_da << alu_shift;
	   2'b01:shift_result = alu_da >> alu_shift;
	   2'b10:shift_result = ({32{alu_da[31]}} << shift_n) | (alu_da >> alu_shift);
	   default:shift_result = alu_da;
	   endcase
	 end


endmodule