data/full_repos/permissive/458737381/src/verilog-parser/tests/mb2cpx.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/mb2cpx.v:37: Cannot find include file: ccx2mb.h\n`include "ccx2mb.h" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/ccx2mb.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/ccx2mb.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/ccx2mb.h.sv\n             ccx2mb.h\n             ccx2mb.h.v\n             ccx2mb.h.sv\n             obj_dir/ccx2mb.h\n             obj_dir/ccx2mb.h.v\n             obj_dir/ccx2mb.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/mb2cpx.v:56: Define or directive not defined: \'`CPX_WIDTH\'\n    parameter CPX_GEAR_RATIO = (((`CPX_WIDTH+1-1)/`FSL_D_WIDTH)+1);\n                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/mb2cpx.v:56: Define or directive not defined: \'`FSL_D_WIDTH\'\n    parameter CPX_GEAR_RATIO = (((`CPX_WIDTH+1-1)/`FSL_D_WIDTH)+1);\n                                                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/mb2cpx.v:56: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    parameter CPX_GEAR_RATIO = (((`CPX_WIDTH+1-1)/`FSL_D_WIDTH)+1);\n                                                              ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/mb2cpx.v:57: Define or directive not defined: \'`FSL_D_WIDTH\'\n    parameter CPX_FSL_EXTRA_BITS  = (`FSL_D_WIDTH * CPX_GEAR_RATIO) -\n                                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/mb2cpx.v:57: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n    parameter CPX_FSL_EXTRA_BITS  = (`FSL_D_WIDTH * CPX_GEAR_RATIO) -\n                                                  ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/mb2cpx.v:58: Define or directive not defined: \'`CPX_WIDTH\'\n        (`CPX_WIDTH+1);\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/mb2cpx.v:65: Define or directive not defined: \'`CPX_WIDTH\'\n    output [`CPX_WIDTH-1:0] cpx_spc_data_cx2;\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/mb2cpx.v:78: Define or directive not defined: \'`FSL_D_WIDTH\'\n    input [`FSL_D_WIDTH-1:0] fsl_cpx_s_data;\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/mb2cpx.v:85: Define or directive not defined: \'`CPX_WIDTH\'\n    wire [`CPX_WIDTH-1:0] cpx_spc_data_cx2;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/mb2cpx.v:93: Define or directive not defined: \'`FSL_D_WIDTH\'\n    reg [CPX_GEAR_RATIO*`FSL_D_WIDTH-1:0] fsl_input_reg;\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/mb2cpx.v:94: Define or directive not defined: \'`CPX_WIDTH\'\n    reg [`CPX_WIDTH-1:0] cpx_output_reg;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/mb2cpx.v:97: Define or directive not defined: \'`FSL_D_WIDTH\'\n    assign atomic_txn = fsl_cpx_s_data[`FSL_D_WIDTH-CPX_FSL_EXTRA_BITS-1];\n                                       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/mb2cpx.v:102: Define or directive not defined: \'`FSL_D_WIDTH\'\n  {fsl_input_reg[(CPX_GEAR_RATIO -1)*`FSL_D_WIDTH-1:0],\n                                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/mb2cpx.v:109: Define or directive not defined: \'`CPX_WIDTH\'\n cpx_output_reg <= cpx_shift_out ? fsl_input_reg[`CPX_WIDTH-1:0] :\n                                                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/mb2cpx.v:113: Define or directive not defined: \'`CPX_WIDTH\'\n    assign cpx_spc_data_cx2 = cpx_spc_data_rdy_cx2 ? cpx_output_reg : {`CPX_WIDTH{1\'b0}};\n                                                                       ^~~~~~~~~~\n%Error: Exiting due to 16 error(s)\n'
module mb2cpx (

	cpx_spc_data_rdy_cx2,
	cpx_spc_data_cx2,

	cpx_fsl_s_read,


	rclk,
	reset_l,

	fsl_cpx_s_exists,
	fsl_cpx_s_control,
	fsl_cpx_s_data
	);

    parameter CPX_GEAR_RATIO = (((`CPX_WIDTH+1-1)/`FSL_D_WIDTH)+1);
    parameter CPX_FSL_EXTRA_BITS  = (`FSL_D_WIDTH * CPX_GEAR_RATIO) -
				    (`CPX_WIDTH+1);





    output                  cpx_spc_data_rdy_cx2;
    output [`CPX_WIDTH-1:0] cpx_spc_data_cx2;


    output cpx_fsl_s_read;



    input rclk;
    input reset_l;


    input                    fsl_cpx_s_exists;
    input                    fsl_cpx_s_control;
    input [`FSL_D_WIDTH-1:0] fsl_cpx_s_data;





    wire                  cpx_spc_data_rdy_cx2;
    wire [`CPX_WIDTH-1:0] cpx_spc_data_cx2;


    wire cpx_fsl_s_read;


    wire atomic_txn;
    wire cpx_shift_out;
    reg [CPX_GEAR_RATIO*`FSL_D_WIDTH-1:0] fsl_input_reg;
    reg [`CPX_WIDTH-1:0] cpx_output_reg;


    assign atomic_txn = fsl_cpx_s_data[`FSL_D_WIDTH-CPX_FSL_EXTRA_BITS-1];


    always @(posedge rclk) begin
	fsl_input_reg <= (fsl_cpx_s_exists && cpx_fsl_s_read) ?
		{fsl_input_reg[(CPX_GEAR_RATIO -1)*`FSL_D_WIDTH-1:0],
			fsl_cpx_s_data} :
		fsl_input_reg;
    end


    always @(posedge rclk) begin
	cpx_output_reg <= cpx_shift_out ? fsl_input_reg[`CPX_WIDTH-1:0] :
			cpx_output_reg;
    end

    assign cpx_spc_data_cx2 = cpx_spc_data_rdy_cx2 ? cpx_output_reg : {`CPX_WIDTH{1'b0}};



    mb2cpx_sm cpx_sm (

	.cpx_fsl_s_read(cpx_fsl_s_read),
	.cpx_shift_out(cpx_shift_out),
	.cpx_spc_data_rdy_cx2(cpx_spc_data_rdy_cx2),


	.rclk(rclk),
	.reset_l(reset_l),

	.fsl_cpx_s_exists(fsl_cpx_s_exists),
	.fsl_cpx_s_control(fsl_cpx_s_control),
	.atomic_txn(atomic_txn)
	);

endmodule
module mb2cpx (

	cpx_spc_data_rdy_cx2,
	cpx_spc_data_cx2,

	cpx_fsl_s_read,


	rclk,
	reset_l,

	fsl_cpx_s_exists,
	fsl_cpx_s_control,
	fsl_cpx_s_data
	);


    parameter CPX_GEAR_RATIO = (((`CPX_WIDTH+1-1)/`FSL_D_WIDTH)+1);
    parameter CPX_FSL_EXTRA_BITS  = (`FSL_D_WIDTH * CPX_GEAR_RATIO) -
				    (`CPX_WIDTH+1);





    output                  cpx_spc_data_rdy_cx2;
    output [`CPX_WIDTH-1:0] cpx_spc_data_cx2;


    output cpx_fsl_s_read;



    input rclk;
    input reset_l;


    input                    fsl_cpx_s_exists;
    input                    fsl_cpx_s_control;
    input [`FSL_D_WIDTH-1:0] fsl_cpx_s_data;





    wire                  cpx_spc_data_rdy_cx2;
    wire [`CPX_WIDTH-1:0] cpx_spc_data_cx2;


    wire cpx_fsl_s_read;


    wire atomic_txn;
    wire cpx_shift_out;
    reg [CPX_GEAR_RATIO*`FSL_D_WIDTH-1:0] fsl_input_reg;
    reg [`CPX_WIDTH-1:0] cpx_output_reg;


    assign atomic_txn = fsl_cpx_s_data[`FSL_D_WIDTH-CPX_FSL_EXTRA_BITS-1];


    always @(posedge rclk) begin
	fsl_input_reg <= (fsl_cpx_s_exists && cpx_fsl_s_read) ?
		{fsl_input_reg[(CPX_GEAR_RATIO -1)*`FSL_D_WIDTH-1:0],
			fsl_cpx_s_data} :
		fsl_input_reg;
    end


    always @(posedge rclk) begin
	cpx_output_reg <= cpx_shift_out ? fsl_input_reg[`CPX_WIDTH-1:0] :
			cpx_output_reg;
    end

    assign cpx_spc_data_cx2 = cpx_spc_data_rdy_cx2 ? cpx_output_reg : {`CPX_WIDTH{1'b0}};



    mb2cpx_sm cpx_sm (

	.cpx_fsl_s_read(cpx_fsl_s_read),
	.cpx_shift_out(cpx_shift_out),
	.cpx_spc_data_rdy_cx2(cpx_spc_data_rdy_cx2),


	.rclk(rclk),
	.reset_l(reset_l),

	.fsl_cpx_s_exists(fsl_cpx_s_exists),
	.fsl_cpx_s_control(fsl_cpx_s_control),
	.atomic_txn(atomic_txn)
	);

endmodule