data/full_repos/permissive/502744275/db/ip/lab7_soc/submodules/vga_text_avl_interface.sv
1: b'%Error: data/full_repos/permissive/502744275/db/ip/lab7_soc/submodules/vga_text_avl_interface.sv:77: Cannot find file containing module: \'vga_controller\'\n vga_controller vc0 (\n ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502744275/db/ip/lab7_soc/submodules,data/full_repos/permissive/502744275/vga_controller\n             data/full_repos/permissive/502744275/db/ip/lab7_soc/submodules,data/full_repos/permissive/502744275/vga_controller.v\n             data/full_repos/permissive/502744275/db/ip/lab7_soc/submodules,data/full_repos/permissive/502744275/vga_controller.sv\n             vga_controller\n             vga_controller.v\n             vga_controller.sv\n             obj_dir/vga_controller\n             obj_dir/vga_controller.v\n             obj_dir/vga_controller.sv\n%Error: data/full_repos/permissive/502744275/db/ip/lab7_soc/submodules/vga_text_avl_interface.sv:89: Cannot find file containing module: \'font_rom\'\n font_rom fr0 (\n ^~~~~~~~\n%Error: data/full_repos/permissive/502744275/db/ip/lab7_soc/submodules/vga_text_avl_interface.sv:94: Cannot find file containing module: \'ram\'\n ram ram0 (\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/502744275/db/ip/lab7_soc/submodules/vga_text_avl_interface.sv:112: Operator ADD expects 32 or 12 bits on the RHS, but RHS\'s SEL generates 7 bits.\n                                                                                                            : ... In instance vga_text_avl_interface\n address = (drawY[9:4] * 80 + drawX[9:3]);\n                            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/502744275/db/ip/lab7_soc/submodules/vga_text_avl_interface.sv:113: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s SEL generates 11 bits.\n                                                                                                            : ... In instance vga_text_avl_interface\n ram_read_address = address[11:1];\n                  ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module vga_text_avl_interface (


	input logic CLK,
	

	input logic RESET,
	

	input  logic AVL_READ,
	input  logic AVL_WRITE,
	input  logic AVL_CS,
	input  logic [3:0] AVL_BYTE_EN,
	input  logic [11:0] AVL_ADDR,
	input  logic [31:0] AVL_WRITEDATA,
	output logic [31:0] AVL_READDATA,
	

	output logic [3:0]  red, green, blue,
	output logic hs, vs
);



logic [9:0] drawX, drawY;
logic [10:0] index;
logic [7:0] charData;
logic [11:0] address;
logic currentBit;
logic inverse;
logic pixel_clk;
logic blank, sync;


logic [31:0] ram_output;
logic [11:0] ram_read_address;


logic [31:0] PALETTE_REG [8];

always_ff @(posedge CLK) begin
	if(AVL_WRITE & AVL_ADDR[11])
		PALETTE_REG[AVL_ADDR[2:0]] <= AVL_WRITEDATA;
		
	if(AVL_READ & AVL_ADDR[11])
		AVL_READDATA <= PALETTE_REG[AVL_ADDR[2:0]];
end


	vga_controller vc0 (
		.Clk(CLK),
		.Reset(RESET),
		.hs(hs),
		.vs(vs),
		.pixel_clk(pixel_clk),
		.blank(blank),
		.sync(sync),
		.DrawX(drawX),
		.DrawY(drawY)
	);
	
	font_rom fr0 (
		.addr(index),
		.data(charData)
	);
	
	ram ram0 (
		.address_a(AVL_ADDR),
		.address_b(ram_read_address),
		.byteena_a(AVL_BYTE_EN),
		.byteena_b(),
		.clock(CLK),
		.data_a(AVL_WRITEDATA),
		.data_b(),
		.rden_a(1'b1),
		.rden_b(1'b1),
		.wren_a(AVL_CS & AVL_WRITE & ~AVL_ADDR[11]),
		.wren_b(1'b0),
		.q_a(),
		.q_b(ram_output)
	);
  

always_comb begin
	address = (drawY[9:4] * 80 + drawX[9:3]);
	ram_read_address = address[11:1];
	
	case (address[0])
		0: begin
			index = {ram_output[14:8], drawY[3:0]};
			inverse = ram_output[15];
		end
		1: begin
			index = {ram_output[30:24], drawY[3:0]};
			inverse = ram_output[31];
		end
	endcase

	currentBit = charData[~drawX[2:0]];
	
	if (inverse) begin
		currentBit = ~currentBit;
	end
end

always_ff @(posedge pixel_clk) begin
	if (!blank) begin
		red <= 4'h0;
		green <= 4'h0;
		blue <= 4'h0;
	end
	
	else begin
		case (address[0])
			0: begin
				if (currentBit) begin
					red	<= ram_output[4] ? PALETTE_REG[ram_output[7:5]][24:21] : PALETTE_REG[ram_output[7:5]][12:9];
					green <= ram_output[4] ? PALETTE_REG[ram_output[7:5]][20:17] : PALETTE_REG[ram_output[7:5]][8:5];
					blue 	<= ram_output[4] ? PALETTE_REG[ram_output[7:5]][16:13] : PALETTE_REG[ram_output[7:5]][4:1];
				end
				
				else begin
					red	<= ram_output[0] ? PALETTE_REG[ram_output[3:1]][24:21] : PALETTE_REG[ram_output[3:1]][12:9];
					green <= ram_output[0] ? PALETTE_REG[ram_output[3:1]][20:17] : PALETTE_REG[ram_output[3:1]][8:5];
					blue 	<= ram_output[0] ? PALETTE_REG[ram_output[3:1]][16:13] : PALETTE_REG[ram_output[3:1]][4:1];
				end
			end
			1: begin
				if (currentBit) begin
					red	<= ram_output[20] ? PALETTE_REG[ram_output[23:21]][24:21] : PALETTE_REG[ram_output[23:21]][12:9];
					green <= ram_output[20] ? PALETTE_REG[ram_output[23:21]][20:17] : PALETTE_REG[ram_output[23:21]][8:5];
					blue 	<= ram_output[20] ? PALETTE_REG[ram_output[23:21]][16:13] : PALETTE_REG[ram_output[23:21]][4:1];
				end
				
				else begin
					red	<= ram_output[16] ? PALETTE_REG[ram_output[19:17]][24:21] : PALETTE_REG[ram_output[19:17]][12:9];
					green <= ram_output[16] ? PALETTE_REG[ram_output[19:17]][20:17] : PALETTE_REG[ram_output[19:17]][8:5];
					blue 	<= ram_output[16] ? PALETTE_REG[ram_output[19:17]][16:13] : PALETTE_REG[ram_output[19:17]][4:1];
				end
			end
		endcase
	end
end

endmodule
module vga_text_avl_interface (


	input logic CLK,
	

	input logic RESET,
	

	input  logic AVL_READ,
	input  logic AVL_WRITE,
	input  logic AVL_CS,
	input  logic [3:0] AVL_BYTE_EN,
	input  logic [11:0] AVL_ADDR,
	input  logic [31:0] AVL_WRITEDATA,
	output logic [31:0] AVL_READDATA,
	

	output logic [3:0]  red, green, blue,
	output logic hs, vs
);




logic [9:0] drawX, drawY;
logic [10:0] index;
logic [7:0] charData;
logic [11:0] address;
logic currentBit;
logic inverse;
logic pixel_clk;
logic blank, sync;


logic [31:0] ram_output;
logic [11:0] ram_read_address;


logic [31:0] PALETTE_REG [8];

always_ff @(posedge CLK) begin
	if(AVL_WRITE & AVL_ADDR[11])
		PALETTE_REG[AVL_ADDR[2:0]] <= AVL_WRITEDATA;
		
	if(AVL_READ & AVL_ADDR[11])
		AVL_READDATA <= PALETTE_REG[AVL_ADDR[2:0]];
end


	vga_controller vc0 (
		.Clk(CLK),
		.Reset(RESET),
		.hs(hs),
		.vs(vs),
		.pixel_clk(pixel_clk),
		.blank(blank),
		.sync(sync),
		.DrawX(drawX),
		.DrawY(drawY)
	);
	
	font_rom fr0 (
		.addr(index),
		.data(charData)
	);
	
	ram ram0 (
		.address_a(AVL_ADDR),
		.address_b(ram_read_address),
		.byteena_a(AVL_BYTE_EN),
		.byteena_b(),
		.clock(CLK),
		.data_a(AVL_WRITEDATA),
		.data_b(),
		.rden_a(1'b1),
		.rden_b(1'b1),
		.wren_a(AVL_CS & AVL_WRITE & ~AVL_ADDR[11]),
		.wren_b(1'b0),
		.q_a(),
		.q_b(ram_output)
	);
  

always_comb begin
	address = (drawY[9:4] * 80 + drawX[9:3]);
	ram_read_address = address[11:1];
	
	case (address[0])
		0: begin
			index = {ram_output[14:8], drawY[3:0]};
			inverse = ram_output[15];
		end
		1: begin
			index = {ram_output[30:24], drawY[3:0]};
			inverse = ram_output[31];
		end
	endcase

	currentBit = charData[~drawX[2:0]];
	
	if (inverse) begin
		currentBit = ~currentBit;
	end
end

always_ff @(posedge pixel_clk) begin
	if (!blank) begin
		red <= 4'h0;
		green <= 4'h0;
		blue <= 4'h0;
	end
	
	else begin
		case (address[0])
			0: begin
				if (currentBit) begin
					red	<= ram_output[4] ? PALETTE_REG[ram_output[7:5]][24:21] : PALETTE_REG[ram_output[7:5]][12:9];
					green <= ram_output[4] ? PALETTE_REG[ram_output[7:5]][20:17] : PALETTE_REG[ram_output[7:5]][8:5];
					blue 	<= ram_output[4] ? PALETTE_REG[ram_output[7:5]][16:13] : PALETTE_REG[ram_output[7:5]][4:1];
				end
				
				else begin
					red	<= ram_output[0] ? PALETTE_REG[ram_output[3:1]][24:21] : PALETTE_REG[ram_output[3:1]][12:9];
					green <= ram_output[0] ? PALETTE_REG[ram_output[3:1]][20:17] : PALETTE_REG[ram_output[3:1]][8:5];
					blue 	<= ram_output[0] ? PALETTE_REG[ram_output[3:1]][16:13] : PALETTE_REG[ram_output[3:1]][4:1];
				end
			end
			1: begin
				if (currentBit) begin
					red	<= ram_output[20] ? PALETTE_REG[ram_output[23:21]][24:21] : PALETTE_REG[ram_output[23:21]][12:9];
					green <= ram_output[20] ? PALETTE_REG[ram_output[23:21]][20:17] : PALETTE_REG[ram_output[23:21]][8:5];
					blue 	<= ram_output[20] ? PALETTE_REG[ram_output[23:21]][16:13] : PALETTE_REG[ram_output[23:21]][4:1];
				end
				
				else begin
					red	<= ram_output[16] ? PALETTE_REG[ram_output[19:17]][24:21] : PALETTE_REG[ram_output[19:17]][12:9];
					green <= ram_output[16] ? PALETTE_REG[ram_output[19:17]][20:17] : PALETTE_REG[ram_output[19:17]][8:5];
					blue 	<= ram_output[16] ? PALETTE_REG[ram_output[19:17]][16:13] : PALETTE_REG[ram_output[19:17]][4:1];
				end
			end
		endcase
	end
end

endmodule