data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_reset.v
1: b"%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_reset.v:38: Cannot find file containing module: 'util_reset_sync'\n    util_reset_sync i_reset_sync_tcu_ctrl (\n    ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog,data/full_repos/permissive/463204869/util_reset_sync\n             data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog,data/full_repos/permissive/463204869/util_reset_sync.v\n             data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog,data/full_repos/permissive/463204869/util_reset_sync.sv\n             util_reset_sync\n             util_reset_sync.v\n             util_reset_sync.sv\n             obj_dir/util_reset_sync\n             obj_dir/util_reset_sync.v\n             obj_dir/util_reset_sync.sv\n%Error: Exiting due to 1 error(s)\n"
module tcu_ctrl_reset
(
    input  wire clk_i,
    input  wire reset_n_i,
    output wire reset_sync_n_o,
    input  wire tcu_reset_i
);


    reg       r_tcu_reset, rin_tcu_reset;
    reg [3:0] r_tcu_reset_count, rin_tcu_reset_count;


    always @(posedge clk_i or negedge reset_n_i) begin
        if(reset_n_i == 1'b0) begin
            r_tcu_reset <= 1'b0;
            r_tcu_reset_count <= 4'd0;
        end else begin
            r_tcu_reset <= rin_tcu_reset;
            r_tcu_reset_count <= rin_tcu_reset_count;
        end
    end
    
    always @* begin
        rin_tcu_reset = 1'b0;
        rin_tcu_reset_count = r_tcu_reset_count;
        


        if (tcu_reset_i || (r_tcu_reset_count > 4'd0)) begin
            rin_tcu_reset_count = r_tcu_reset_count + 4'd1;
            rin_tcu_reset = 1'b1;
        end
    end


    util_reset_sync i_reset_sync_tcu_ctrl (
        .clk_i           (clk_i),
        .reset_q_i       (reset_n_i & (~r_tcu_reset)),
        .scan_mode_i     (1'b0),
        .sync_reset_q_o  (reset_sync_n_o)
    );


endmodule
module tcu_ctrl_reset
(
    input  wire clk_i,
    input  wire reset_n_i,
    output wire reset_sync_n_o,
    input  wire tcu_reset_i
);



    reg       r_tcu_reset, rin_tcu_reset;
    reg [3:0] r_tcu_reset_count, rin_tcu_reset_count;


    always @(posedge clk_i or negedge reset_n_i) begin
        if(reset_n_i == 1'b0) begin
            r_tcu_reset <= 1'b0;
            r_tcu_reset_count <= 4'd0;
        end else begin
            r_tcu_reset <= rin_tcu_reset;
            r_tcu_reset_count <= rin_tcu_reset_count;
        end
    end
    
    always @* begin
        rin_tcu_reset = 1'b0;
        rin_tcu_reset_count = r_tcu_reset_count;
        


        if (tcu_reset_i || (r_tcu_reset_count > 4'd0)) begin
            rin_tcu_reset_count = r_tcu_reset_count + 4'd1;
            rin_tcu_reset = 1'b1;
        end
    end


    util_reset_sync i_reset_sync_tcu_ctrl (
        .clk_i           (clk_i),
        .reset_q_i       (reset_n_i & (~r_tcu_reset)),
        .scan_mode_i     (1'b0),
        .sync_reset_q_o  (reset_sync_n_o)
    );


endmodule