data/full_repos/permissive/43858668/final_verilog/src/rtr_op_ctrl_mac.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_op_ctrl_mac.v:37: Cannot find include file: c_functions.v\n`include "c_functions.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v.v\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v.sv\n             c_functions.v\n             c_functions.v.v\n             c_functions.v.sv\n             obj_dir/c_functions.v\n             obj_dir/c_functions.v.v\n             obj_dir/c_functions.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_op_ctrl_mac.v:38: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_op_ctrl_mac.v:39: Cannot find include file: rtr_constants.v\n`include "rtr_constants.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_op_ctrl_mac.v:56: Define or directive not defined: \'`PACKET_FORMAT_EXPLICIT_LENGTH\'\n   parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;\n                             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_op_ctrl_mac.v:56: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;\n                                                           ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_op_ctrl_mac.v:59: Define or directive not defined: \'`FLOW_CTRL_TYPE_CREDIT\'\n   parameter flow_ctrl_type = `FLOW_CTRL_TYPE_CREDIT;\n                              ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_op_ctrl_mac.v:59: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter flow_ctrl_type = `FLOW_CTRL_TYPE_CREDIT;\n                                                    ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_op_ctrl_mac.v:66: Define or directive not defined: \'`FB_MGMT_TYPE_STATIC\'\n   parameter fb_mgmt_type = `FB_MGMT_TYPE_STATIC;\n                            ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_op_ctrl_mac.v:66: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter fb_mgmt_type = `FB_MGMT_TYPE_STATIC;\n                                                ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_op_ctrl_mac.v:75: Define or directive not defined: \'`ELIG_MASK_NONE\'\n   parameter elig_mask = `ELIG_MASK_NONE;\n                         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_op_ctrl_mac.v:75: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter elig_mask = `ELIG_MASK_NONE;\n                                        ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_op_ctrl_mac.v:87: Define or directive not defined: \'`ERROR_CAPTURE_MODE_NO_HOLD\'\n   parameter error_capture_mode = `ERROR_CAPTURE_MODE_NO_HOLD;\n                                  ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_op_ctrl_mac.v:87: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter error_capture_mode = `ERROR_CAPTURE_MODE_NO_HOLD;\n                                                             ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_op_ctrl_mac.v:89: Define or directive not defined: \'`RESET_TYPE_ASYNC\'\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_op_ctrl_mac.v:89: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                                           ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_op_ctrl_mac.v:101: Define or directive not defined: \'`FLOW_CTRL_TYPE_CREDIT\'\n     = (flow_ctrl_type == `FLOW_CTRL_TYPE_CREDIT) ? (1 + vc_idx_width) :\n                          ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_op_ctrl_mac.v:101: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n     = (flow_ctrl_type == `FLOW_CTRL_TYPE_CREDIT) ? (1 + vc_idx_width) :\n                                                ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_op_ctrl_mac.v:109: Define or directive not defined: \'`PACKET_FORMAT_HEAD_TAIL\'\n     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_op_ctrl_mac.v:109: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? \n                                                 ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_op_ctrl_mac.v:111: Define or directive not defined: \'`PACKET_FORMAT_TAIL_ONLY\'\n       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_op_ctrl_mac.v:113: Define or directive not defined: \'`PACKET_FORMAT_EXPLICIT_LENGTH\'\n       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_op_ctrl_mac.v:124: Define or directive not defined: \'`ELIG_MASK_USED\'\n       ((elig_mask == `ELIG_MASK_USED) || vc_alloc_prefer_empty);\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_op_ctrl_mac.v:124: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n       ((elig_mask == `ELIG_MASK_USED) || vc_alloc_prefer_empty);\n                                     ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_op_ctrl_mac.v:322: Define or directive not defined: \'`ELIG_MASK_NONE\'\n      `ELIG_MASK_NONE:\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_op_ctrl_mac.v:322: syntax error, unexpected \':\', expecting endcase\n      `ELIG_MASK_NONE:\n                     ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_op_ctrl_mac.v:325: Define or directive not defined: \'`ELIG_MASK_FULL\'\n      `ELIG_MASK_FULL:\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_op_ctrl_mac.v:328: Define or directive not defined: \'`ELIG_MASK_USED\'\n      `ELIG_MASK_USED:\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_op_ctrl_mac.v:346: Define or directive not defined: \'`ERROR_CAPTURE_MODE_NONE\'\n      if(error_capture_mode != `ERROR_CAPTURE_MODE_NONE)\n                               ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_op_ctrl_mac.v:346: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      if(error_capture_mode != `ERROR_CAPTURE_MODE_NONE)\n                                                       ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_op_ctrl_mac.v:364: syntax error, unexpected end\n end\n ^~~\n%Error: Exiting due to 30 error(s)\n'
module rtr_op_ctrl_mac
  (clk, reset, flow_ctrl_in, flit_valid_in, flit_head_in, flit_tail_in, 
   flit_sel_in_ovc, flit_data_in, channel_out, elig_out_ovc, empty_out_ovc, 
   almost_full_out_ovc, full_out_ovc, error);
   
`include "c_functions.v"
`include "c_constants.v"
`include "rtr_constants.v"
   
   



   

   parameter buffer_size = 32;
   

   parameter num_vcs = 4;
   

   parameter num_ports = 5;
   

   parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;
   

   parameter flow_ctrl_type = `FLOW_CTRL_TYPE_CREDIT;
   


   parameter flow_ctrl_bypass = 1;
   

   parameter fb_mgmt_type = `FB_MGMT_TYPE_STATIC;
   




   parameter disable_static_reservations = 0;
   

   parameter elig_mask = `ELIG_MASK_NONE;
   

   parameter vc_alloc_prefer_empty = 0;
   

   parameter enable_link_pm = 1;
   

   parameter flit_data_width = 64;
   

   parameter error_capture_mode = `ERROR_CAPTURE_MODE_NO_HOLD;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   



   

   localparam vc_idx_width = clogb(num_vcs);
   

   localparam flow_ctrl_width
     = (flow_ctrl_type == `FLOW_CTRL_TYPE_CREDIT) ? (1 + vc_idx_width) :
       -1;
   

   localparam link_ctrl_width = enable_link_pm ? 1 : 0;
   

   localparam flit_ctrl_width
     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? 
       (1 + vc_idx_width + 1 + 1) : 
       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? 
       (1 + vc_idx_width + 1) : 
       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? 
       (1 + vc_idx_width + 1) : 
       -1;
   

   localparam channel_width
     = link_ctrl_width + flit_ctrl_width + flit_data_width;
   

   localparam fast_almost_empty
     = flow_ctrl_bypass && 
       ((elig_mask == `ELIG_MASK_USED) || vc_alloc_prefer_empty);
   
   



   
   input clk;
   input reset;
   

   input [0:flow_ctrl_width-1] flow_ctrl_in;
   

   input 		       flit_valid_in;
   

   input 		       flit_head_in;
   

   input 		       flit_tail_in;
   

   input [0:num_vcs-1] 	       flit_sel_in_ovc;
   

   input [0:flit_data_width-1] flit_data_in;
   

   output [0:channel_width-1]  channel_out;
   wire [0:channel_width-1]    channel_out;
   

   output [0:num_vcs-1]        elig_out_ovc;
   wire [0:num_vcs-1] 	       elig_out_ovc;
   

   output [0:num_vcs-1]        empty_out_ovc;
   wire [0:num_vcs-1] 	       empty_out_ovc;
   

   output [0:num_vcs-1]        almost_full_out_ovc;
   wire [0:num_vcs-1] 	       almost_full_out_ovc;
   

   output [0:num_vcs-1]        full_out_ovc;
   wire [0:num_vcs-1] 	       full_out_ovc;
   

   output 		       error;
   wire 		       error;
   
   



   
   wire 		       flow_ctrl_active;
   
   wire 		       fc_event_valid;
   wire [0:num_vcs-1] 	       fc_event_sel_ovc;
   rtr_flow_ctrl_input
     #(.num_vcs(num_vcs),
       .flow_ctrl_type(flow_ctrl_type),
       .reset_type(reset_type))
   fci
     (.clk(clk),
      .reset(reset),
      .active(flow_ctrl_active),
      .flow_ctrl_in(flow_ctrl_in),
      .fc_event_valid_out(fc_event_valid),
      .fc_event_sel_out_ovc(fc_event_sel_ovc));
   
   



   
   wire 		       channel_active;
   assign channel_active = flit_valid_in;
   
   rtr_channel_output
     #(.num_vcs(num_vcs),
       .packet_format(packet_format),
       .enable_link_pm(enable_link_pm),
       .flit_data_width(flit_data_width),
       .reset_type(reset_type))
   cho
     (.clk(clk),
      .reset(reset),
      .active(channel_active),
      .flit_valid_in(flit_valid_in),
      .flit_head_in(flit_head_in),
      .flit_tail_in(flit_tail_in),
      .flit_data_in(flit_data_in),
      .flit_sel_in_ovc(flit_sel_in_ovc),
      .channel_out(channel_out));
   
   



   
   wire 		       fcs_active;
   assign fcs_active = flit_valid_in | fc_event_valid;
   
   wire 		       fcs_fc_active;
   wire [0:num_vcs-1] 	       fcs_empty_ovc;
   wire [0:num_vcs-1] 	       fcs_almost_full_ovc;
   wire [0:num_vcs-1] 	       fcs_full_ovc;
   wire [0:num_vcs-1] 	       fcs_full_prev_ovc;
   wire [0:num_vcs*2-1]        fcs_errors_ovc;
   rtr_fc_state
     #(.num_vcs(num_vcs),
       .buffer_size(buffer_size),
       .flow_ctrl_type(flow_ctrl_type),
       .flow_ctrl_bypass(flow_ctrl_bypass),
       .mgmt_type(fb_mgmt_type),
       .fast_almost_empty(fast_almost_empty),
       .disable_static_reservations(disable_static_reservations),
       .reset_type(reset_type))
   fcs
     (.clk(clk),
      .reset(reset),
      .active(fcs_active),
      .flit_valid(flit_valid_in),
      .flit_head(flit_head_in),
      .flit_tail(flit_tail_in),
      .flit_sel_ovc(flit_sel_in_ovc),
      .fc_event_valid(fc_event_valid),
      .fc_event_sel_ovc(fc_event_sel_ovc),
      .fc_active(fcs_fc_active),
      .empty_ovc(fcs_empty_ovc),
      .almost_full_ovc(fcs_almost_full_ovc),
      .full_ovc(fcs_full_ovc),
      .full_prev_ovc(fcs_full_prev_ovc),
      .errors_ovc(fcs_errors_ovc));
   
   assign empty_out_ovc = fcs_empty_ovc;
   assign almost_full_out_ovc = fcs_almost_full_ovc;
   assign full_out_ovc = fcs_full_ovc;
   
   assign flow_ctrl_active = fcs_fc_active;
   
   wire 		       ovc_active;
   assign ovc_active = flit_valid_in;
   
   genvar 		       ovc;
   
   generate
      
      for(ovc = 0; ovc < num_vcs; ovc = ovc + 1)
	begin:ovcs
	   
	   wire flit_sel_in;
	   assign flit_sel_in = flit_sel_in_ovc[ovc];
	   
	   wire flit_valid_sel_in;
	   assign flit_valid_sel_in = flit_valid_in & flit_sel_in;
	   
	   wire fcs_empty;
	   assign fcs_empty = fcs_empty_ovc[ovc];

	   wire fcs_full;
	   assign fcs_full = fcs_full_ovc[ovc];	   
	   
	   



	   






	   
	   wire allocated;
	   
	   wire allocated_s, allocated_q;
	   assign allocated_s = allocated;
	   c_dff
	     #(.width(1),
	       .reset_type(reset_type))
	   allocatedq
	     (.clk(clk),
	      .reset(reset),
	      .active(ovc_active),
	      .d(allocated_s),
	      .q(allocated_q));
	   
	   assign allocated = flit_valid_sel_in ? ~flit_tail_in : allocated_q;
	   
	   wire elig;
	   
	   case(elig_mask)
	     
	     `ELIG_MASK_NONE:
	       assign elig = ~allocated;
	     
	     `ELIG_MASK_FULL:
	       assign elig = ~allocated & ~fcs_full;
	     
	     `ELIG_MASK_USED:
	       assign elig = ~allocated & fcs_empty;
	     
	   endcase
	   
	   assign elig_out_ovc[ovc] = elig;
	   
	end
      
   endgenerate
   
   



   
   generate
      
      if(error_capture_mode != `ERROR_CAPTURE_MODE_NONE)
	begin
	   
	   wire [0:num_vcs*2-1] errors_s, errors_q;
	   assign errors_s = fcs_errors_ovc;
	   c_err_rpt
	     #(.num_errors(num_vcs*2),
	       .capture_mode(error_capture_mode),
	       .reset_type(reset_type))
	   chk
	     (.clk(clk),
	      .reset(reset),
	      .active(1'b1),
	      .errors_in(errors_s),
	      .errors_out(errors_q));
	   
	   assign error = |errors_q;
	   
	end
      else
	assign error = 1'bx;
      
   endgenerate
   
endmodule
module rtr_op_ctrl_mac
  (clk, reset, flow_ctrl_in, flit_valid_in, flit_head_in, flit_tail_in, 
   flit_sel_in_ovc, flit_data_in, channel_out, elig_out_ovc, empty_out_ovc, 
   almost_full_out_ovc, full_out_ovc, error);

   
`include "c_functions.v"
`include "c_constants.v"
`include "rtr_constants.v"
   
   



   

   parameter buffer_size = 32;
   

   parameter num_vcs = 4;
   

   parameter num_ports = 5;
   

   parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;
   

   parameter flow_ctrl_type = `FLOW_CTRL_TYPE_CREDIT;
   


   parameter flow_ctrl_bypass = 1;
   

   parameter fb_mgmt_type = `FB_MGMT_TYPE_STATIC;
   




   parameter disable_static_reservations = 0;
   

   parameter elig_mask = `ELIG_MASK_NONE;
   

   parameter vc_alloc_prefer_empty = 0;
   

   parameter enable_link_pm = 1;
   

   parameter flit_data_width = 64;
   

   parameter error_capture_mode = `ERROR_CAPTURE_MODE_NO_HOLD;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   



   

   localparam vc_idx_width = clogb(num_vcs);
   

   localparam flow_ctrl_width
     = (flow_ctrl_type == `FLOW_CTRL_TYPE_CREDIT) ? (1 + vc_idx_width) :
       -1;
   

   localparam link_ctrl_width = enable_link_pm ? 1 : 0;
   

   localparam flit_ctrl_width
     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? 
       (1 + vc_idx_width + 1 + 1) : 
       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? 
       (1 + vc_idx_width + 1) : 
       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? 
       (1 + vc_idx_width + 1) : 
       -1;
   

   localparam channel_width
     = link_ctrl_width + flit_ctrl_width + flit_data_width;
   

   localparam fast_almost_empty
     = flow_ctrl_bypass && 
       ((elig_mask == `ELIG_MASK_USED) || vc_alloc_prefer_empty);
   
   



   
   input clk;
   input reset;
   

   input [0:flow_ctrl_width-1] flow_ctrl_in;
   

   input 		       flit_valid_in;
   

   input 		       flit_head_in;
   

   input 		       flit_tail_in;
   

   input [0:num_vcs-1] 	       flit_sel_in_ovc;
   

   input [0:flit_data_width-1] flit_data_in;
   

   output [0:channel_width-1]  channel_out;
   wire [0:channel_width-1]    channel_out;
   

   output [0:num_vcs-1]        elig_out_ovc;
   wire [0:num_vcs-1] 	       elig_out_ovc;
   

   output [0:num_vcs-1]        empty_out_ovc;
   wire [0:num_vcs-1] 	       empty_out_ovc;
   

   output [0:num_vcs-1]        almost_full_out_ovc;
   wire [0:num_vcs-1] 	       almost_full_out_ovc;
   

   output [0:num_vcs-1]        full_out_ovc;
   wire [0:num_vcs-1] 	       full_out_ovc;
   

   output 		       error;
   wire 		       error;
   
   



   
   wire 		       flow_ctrl_active;
   
   wire 		       fc_event_valid;
   wire [0:num_vcs-1] 	       fc_event_sel_ovc;
   rtr_flow_ctrl_input
     #(.num_vcs(num_vcs),
       .flow_ctrl_type(flow_ctrl_type),
       .reset_type(reset_type))
   fci
     (.clk(clk),
      .reset(reset),
      .active(flow_ctrl_active),
      .flow_ctrl_in(flow_ctrl_in),
      .fc_event_valid_out(fc_event_valid),
      .fc_event_sel_out_ovc(fc_event_sel_ovc));
   
   



   
   wire 		       channel_active;
   assign channel_active = flit_valid_in;
   
   rtr_channel_output
     #(.num_vcs(num_vcs),
       .packet_format(packet_format),
       .enable_link_pm(enable_link_pm),
       .flit_data_width(flit_data_width),
       .reset_type(reset_type))
   cho
     (.clk(clk),
      .reset(reset),
      .active(channel_active),
      .flit_valid_in(flit_valid_in),
      .flit_head_in(flit_head_in),
      .flit_tail_in(flit_tail_in),
      .flit_data_in(flit_data_in),
      .flit_sel_in_ovc(flit_sel_in_ovc),
      .channel_out(channel_out));
   
   



   
   wire 		       fcs_active;
   assign fcs_active = flit_valid_in | fc_event_valid;
   
   wire 		       fcs_fc_active;
   wire [0:num_vcs-1] 	       fcs_empty_ovc;
   wire [0:num_vcs-1] 	       fcs_almost_full_ovc;
   wire [0:num_vcs-1] 	       fcs_full_ovc;
   wire [0:num_vcs-1] 	       fcs_full_prev_ovc;
   wire [0:num_vcs*2-1]        fcs_errors_ovc;
   rtr_fc_state
     #(.num_vcs(num_vcs),
       .buffer_size(buffer_size),
       .flow_ctrl_type(flow_ctrl_type),
       .flow_ctrl_bypass(flow_ctrl_bypass),
       .mgmt_type(fb_mgmt_type),
       .fast_almost_empty(fast_almost_empty),
       .disable_static_reservations(disable_static_reservations),
       .reset_type(reset_type))
   fcs
     (.clk(clk),
      .reset(reset),
      .active(fcs_active),
      .flit_valid(flit_valid_in),
      .flit_head(flit_head_in),
      .flit_tail(flit_tail_in),
      .flit_sel_ovc(flit_sel_in_ovc),
      .fc_event_valid(fc_event_valid),
      .fc_event_sel_ovc(fc_event_sel_ovc),
      .fc_active(fcs_fc_active),
      .empty_ovc(fcs_empty_ovc),
      .almost_full_ovc(fcs_almost_full_ovc),
      .full_ovc(fcs_full_ovc),
      .full_prev_ovc(fcs_full_prev_ovc),
      .errors_ovc(fcs_errors_ovc));
   
   assign empty_out_ovc = fcs_empty_ovc;
   assign almost_full_out_ovc = fcs_almost_full_ovc;
   assign full_out_ovc = fcs_full_ovc;
   
   assign flow_ctrl_active = fcs_fc_active;
   
   wire 		       ovc_active;
   assign ovc_active = flit_valid_in;
   
   genvar 		       ovc;
   
   generate
      
      for(ovc = 0; ovc < num_vcs; ovc = ovc + 1)
	begin:ovcs
	   
	   wire flit_sel_in;
	   assign flit_sel_in = flit_sel_in_ovc[ovc];
	   
	   wire flit_valid_sel_in;
	   assign flit_valid_sel_in = flit_valid_in & flit_sel_in;
	   
	   wire fcs_empty;
	   assign fcs_empty = fcs_empty_ovc[ovc];

	   wire fcs_full;
	   assign fcs_full = fcs_full_ovc[ovc];	   
	   
	   



	   






	   
	   wire allocated;
	   
	   wire allocated_s, allocated_q;
	   assign allocated_s = allocated;
	   c_dff
	     #(.width(1),
	       .reset_type(reset_type))
	   allocatedq
	     (.clk(clk),
	      .reset(reset),
	      .active(ovc_active),
	      .d(allocated_s),
	      .q(allocated_q));
	   
	   assign allocated = flit_valid_sel_in ? ~flit_tail_in : allocated_q;
	   
	   wire elig;
	   
	   case(elig_mask)
	     
	     `ELIG_MASK_NONE:
	       assign elig = ~allocated;
	     
	     `ELIG_MASK_FULL:
	       assign elig = ~allocated & ~fcs_full;
	     
	     `ELIG_MASK_USED:
	       assign elig = ~allocated & fcs_empty;
	     
	   endcase
	   
	   assign elig_out_ovc[ovc] = elig;
	   
	end
      
   endgenerate
   
   



   
   generate
      
      if(error_capture_mode != `ERROR_CAPTURE_MODE_NONE)
	begin
	   
	   wire [0:num_vcs*2-1] errors_s, errors_q;
	   assign errors_s = fcs_errors_ovc;
	   c_err_rpt
	     #(.num_errors(num_vcs*2),
	       .capture_mode(error_capture_mode),
	       .reset_type(reset_type))
	   chk
	     (.clk(clk),
	      .reset(reset),
	      .active(1'b1),
	      .errors_in(errors_s),
	      .errors_out(errors_q));
	   
	   assign error = |errors_q;
	   
	end
      else
	assign error = 1'bx;
      
   endgenerate
   
endmodule