data/full_repos/permissive/452305748/L4/counter/counter.v
data/verilator_xmls/847ad548-8867-45a8-9973-9320c45fb978.xml
module counter (clk,
                res,
                y);
    input clk;
    input res;
    output[7:0] y;
    
    reg[7:0] y;
    


    
    always @(posedge clk or negedge res) begin
        if (~res) begin
            y <= 0;
        end
        else begin
            y <= y+1;
        end
    end
    
endmodule
module counter (clk,
                res,
                y);

    input clk;
    input res;
    output[7:0] y;
    
    reg[7:0] y;
    


    
    always @(posedge clk or negedge res) begin
        if (~res) begin
            y <= 0;
        end
        else begin
            y <= y+1;
        end
    end
    
endmodule