data/full_repos/permissive/515598112/3_Circuits/01_Combinational_Logic/02_Multiplexers/01_2-to-1_multiplexer.v
data/verilator_xmls/95ce64da-e4f3-45ed-b91a-5ea89c013c19.xml
module top_module( 
    input a, b, sel,
    output out
);
    
    assign out = sel ? b : a;

endmodule
module top_module( 
    input a, b, sel,
    output out
);

    
    assign out = sel ? b : a;

endmodule