data/full_repos/permissive/441359809/src/yosys/tests/arch/xilinx/macc.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/tests/arch/xilinx/macc.v:44: Multiple top level modules\n                                                                                             : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                             : ... Top module \'macc\'\nmodule macc # (parameter SIZEIN = 16, SIZEOUT = 40) (\n       ^~~~\n                                                                                             : ... Top module \'macc2\'\nmodule macc2 # (parameter SIZEIN = 16, SIZEOUT = 40) (\n       ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/arch/xilinx/macc.v:66: Operator ADD expects 41 bits on the RHS, but RHS\'s VARREF \'mult_reg\' generates 32 bits.\n                                                                                          : ... In instance macc2\n  adder_out <= adder_out + mult_reg;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/arch/xilinx/macc.v:82: Operator ASSIGNW expects 40 bits on the Assign RHS, but Assign RHS\'s COND generates 41 bits.\n                                                                                          : ... In instance macc2\nassign accum_out = overflow ? 2**(SIZEOUT-1)-1 : adder_out;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/arch/xilinx/macc.v:35: Operator ADD expects 40 bits on the RHS, but RHS\'s VARREF \'mult_reg\' generates 32 bits.\n                                                                                          : ... In instance macc\n  adder_out <= old_result + mult_reg;\n                          ^\n%Error: Exiting due to 4 warning(s)\n'
module macc2 # (parameter SIZEIN = 16, SIZEOUT = 40) (
	input clk,
	input ce,
	input rst,
	input signed [SIZEIN-1:0] a, b,
	output signed [SIZEOUT-1:0] accum_out,
	output overflow
);

reg signed [SIZEIN-1:0] a_reg = 0, b_reg = 0, a_reg2 = 0, b_reg2 = 0;
reg signed [2*SIZEIN-1:0] mult_reg = 0;
reg signed [SIZEOUT:0] adder_out = 0;
reg overflow_reg = 0;
always @(posedge clk) begin

	begin
		a_reg <= a;
		b_reg <= b;
		a_reg2 <= a_reg;
		b_reg2 <= b_reg;
		mult_reg <= a_reg2 * b_reg2;

		adder_out <= adder_out + mult_reg;
		overflow_reg <= overflow;
	end
	if (rst) begin
		a_reg <= 0;
		a_reg2 <= 0;
		b_reg <= 0;
		b_reg2 <= 0;
		mult_reg <= 0;
		adder_out <= 0;
		overflow_reg <= 1'b0;
	end
end
assign overflow = (adder_out >= 2**(SIZEOUT-1)) | overflow_reg;


assign accum_out = overflow ? 2**(SIZEOUT-1)-1 : adder_out;

endmodule
module macc2 # (parameter SIZEIN = 16, SIZEOUT = 40) (
	input clk,
	input ce,
	input rst,
	input signed [SIZEIN-1:0] a, b,
	output signed [SIZEOUT-1:0] accum_out,
	output overflow
);


reg signed [SIZEIN-1:0] a_reg = 0, b_reg = 0, a_reg2 = 0, b_reg2 = 0;
reg signed [2*SIZEIN-1:0] mult_reg = 0;
reg signed [SIZEOUT:0] adder_out = 0;
reg overflow_reg = 0;
always @(posedge clk) begin

	begin
		a_reg <= a;
		b_reg <= b;
		a_reg2 <= a_reg;
		b_reg2 <= b_reg;
		mult_reg <= a_reg2 * b_reg2;

		adder_out <= adder_out + mult_reg;
		overflow_reg <= overflow;
	end
	if (rst) begin
		a_reg <= 0;
		a_reg2 <= 0;
		b_reg <= 0;
		b_reg2 <= 0;
		mult_reg <= 0;
		adder_out <= 0;
		overflow_reg <= 1'b0;
	end
end
assign overflow = (adder_out >= 2**(SIZEOUT-1)) | overflow_reg;


assign accum_out = overflow ? 2**(SIZEOUT-1)-1 : adder_out;

endmodule