data/full_repos/permissive/405799749/amg_new2/adder/FSA_16_64_Carry_select_adder.v
data/verilator_xmls/a1e22f4f-1bee-4d86-a007-eae88622d5c2.xml
module UBCSlB_45_37(Co, S, X, Y, Ci);
  output Co;
  output [45:37] S;
  input Ci;
  input [45:37] X;
  input [45:37] Y;
  wire Ci_0;
  wire Ci_1;
  wire Co_0;
  wire Co_1;
  wire [45:37] S_0;
  wire [45:37] S_1;
  assign S[37] = ( S_0[37] & ( ~ Ci ) ) | ( S_1[37] & Ci );
  assign S[38] = ( S_0[38] & ( ~ Ci ) ) | ( S_1[38] & Ci );
  assign S[39] = ( S_0[39] & ( ~ Ci ) ) | ( S_1[39] & Ci );
  assign S[40] = ( S_0[40] & ( ~ Ci ) ) | ( S_1[40] & Ci );
  assign S[41] = ( S_0[41] & ( ~ Ci ) ) | ( S_1[41] & Ci );
  assign S[42] = ( S_0[42] & ( ~ Ci ) ) | ( S_1[42] & Ci );
  assign S[43] = ( S_0[43] & ( ~ Ci ) ) | ( S_1[43] & Ci );
  assign S[44] = ( S_0[44] & ( ~ Ci ) ) | ( S_1[44] & Ci );
  assign S[45] = ( S_0[45] & ( ~ Ci ) ) | ( S_1[45] & Ci );
  assign Co = ( Co_0 & ( ~ Ci ) ) | ( Co_1 & Ci );
  UBOne_37 U0 (Ci_1);
  UBZero_37_37 U1 (Ci_0);
  UBRCB_45_37 U2 (Co_0, S_0, X, Y, Ci_0);
  UBRCB_45_37 U3 (Co_1, S_1, X, Y, Ci_1);
endmodule
module UBCSlB_45_37(Co, S, X, Y, Ci);

  output Co;
  output [45:37] S;
  input Ci;
  input [45:37] X;
  input [45:37] Y;
  wire Ci_0;
  wire Ci_1;
  wire Co_0;
  wire Co_1;
  wire [45:37] S_0;
  wire [45:37] S_1;
  assign S[37] = ( S_0[37] & ( ~ Ci ) ) | ( S_1[37] & Ci );
  assign S[38] = ( S_0[38] & ( ~ Ci ) ) | ( S_1[38] & Ci );
  assign S[39] = ( S_0[39] & ( ~ Ci ) ) | ( S_1[39] & Ci );
  assign S[40] = ( S_0[40] & ( ~ Ci ) ) | ( S_1[40] & Ci );
  assign S[41] = ( S_0[41] & ( ~ Ci ) ) | ( S_1[41] & Ci );
  assign S[42] = ( S_0[42] & ( ~ Ci ) ) | ( S_1[42] & Ci );
  assign S[43] = ( S_0[43] & ( ~ Ci ) ) | ( S_1[43] & Ci );
  assign S[44] = ( S_0[44] & ( ~ Ci ) ) | ( S_1[44] & Ci );
  assign S[45] = ( S_0[45] & ( ~ Ci ) ) | ( S_1[45] & Ci );
  assign Co = ( Co_0 & ( ~ Ci ) ) | ( Co_1 & Ci );
  UBOne_37 U0 (Ci_1);
  UBZero_37_37 U1 (Ci_0);
  UBRCB_45_37 U2 (Co_0, S_0, X, Y, Ci_0);
  UBRCB_45_37 U3 (Co_1, S_1, X, Y, Ci_1);
endmodule