data/full_repos/permissive/453763315/design.v
1: b'%Error: data/full_repos/permissive/453763315/design.v:1: Cannot find include file: alu.sv\n`include "alu.sv" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/453763315,data/full_repos/permissive/453763315/alu.sv\n             data/full_repos/permissive/453763315,data/full_repos/permissive/453763315/alu.sv.v\n             data/full_repos/permissive/453763315,data/full_repos/permissive/453763315/alu.sv.sv\n             alu.sv\n             alu.sv.v\n             alu.sv.sv\n             obj_dir/alu.sv\n             obj_dir/alu.sv.v\n             obj_dir/alu.sv.sv\n%Error: data/full_repos/permissive/453763315/design.v:2: Cannot find include file: regarray.sv\n`include "regarray.sv" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/453763315/design.v:3: Cannot find include file: branch.sv\n`include "branch.sv" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/453763315/design.v:4: Cannot find include file: datacache.sv\n`include "datacache.sv" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/453763315/design.v:5: Cannot find include file: pc.sv\n`include "pc.sv" \n         ^~~~~~~\n%Error: data/full_repos/permissive/453763315/design.v:6: Cannot find include file: ram.sv\n`include "ram.sv" \n         ^~~~~~~~\n%Error: Exiting due to 6 error(s)\n'
module processor(clk);

  input reg clk;

  reg en, we;
  reg [5:0] sela, selb;
  reg [7:0] reada, readb, write;

  reg [7:0] out;
  reg [3:0] sel;
  reg [2:0] flags;

  regarray array(.clk(clk), .en(en), .we(we), .sela(sela), .selb(selb), .reada(reada),  .readb(readb),.write(write));

  alu alu(.a(reada), .b(readb), .out(out), .sel(sel), .flags(flags), .clk(clk), .en(en));


endmodule
module processor(clk);


  input reg clk;

  reg en, we;
  reg [5:0] sela, selb;
  reg [7:0] reada, readb, write;

  reg [7:0] out;
  reg [3:0] sel;
  reg [2:0] flags;

  regarray array(.clk(clk), .en(en), .we(we), .sela(sela), .selb(selb), .reada(reada),  .readb(readb),.write(write));

  alu alu(.a(reada), .b(readb), .out(out), .sel(sel), .flags(flags), .clk(clk), .en(en));


endmodule