data/full_repos/permissive/472385934/reg_file.v
1: b'%Warning-WIDTH: data/full_repos/permissive/472385934/reg_file.v:30: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'a1\' generates 5 bits.\n                                                                  : ... In instance reg_file\nassign rd1 = a1?rf[a1]:0; \n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/472385934/reg_file.v:31: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'a2\' generates 5 bits.\n                                                                  : ... In instance reg_file\nassign rd2 = a2?rf[a2]:0; \n               ^\n%Error: Exiting due to 2 warning(s)\n'
module reg_file(
input [31:0] wd,
input [4:0] a3,
input clk,reg_wr,rst_n,
input [4:0] a1,a2,
output [31:0]rd1,rd2);

reg [31:0] rf [31:0];
integer i;

always@(negedge clk or negedge rst_n) begin
    if (!rst_n) begin 
        for (i=0;i<32;i=i+1) begin rf[i] <= 0; end
    end
    else begin 
        if (reg_wr) begin rf[a3] <= wd; end
    end
end 


assign rd1 = a1?rf[a1]:0; 
assign rd2 = a2?rf[a2]:0; 

endmodule
module reg_file(
input [31:0] wd,
input [4:0] a3,
input clk,reg_wr,rst_n,
input [4:0] a1,a2,
output [31:0]rd1,rd2);


reg [31:0] rf [31:0];
integer i;

always@(negedge clk or negedge rst_n) begin
    if (!rst_n) begin 
        for (i=0;i<32;i=i+1) begin rf[i] <= 0; end
    end
    else begin 
        if (reg_wr) begin rf[a3] <= wd; end
    end
end 


assign rd1 = a1?rf[a1]:0; 
assign rd2 = a2?rf[a2]:0; 

endmodule