data/full_repos/permissive/469129654/src/full_adder_modular_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/469129654/src/full_adder_modular_testbench.v:9: Unsupported: Ignoring delay on this delayed statement.\n        #100 a=1\'b0; b=1\'b1; carry_in=1\'b0;  \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/469129654/src/full_adder_modular_testbench.v:10: Unsupported: Ignoring delay on this delayed statement.\n        #100 a=1\'b1; b=1\'b0; carry_in=1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/469129654/src/full_adder_modular_testbench.v:11: Unsupported: Ignoring delay on this delayed statement.\n        #100 a=1\'b1; b=1\'b1; carry_in=1\'b0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/469129654/src/full_adder_modular_testbench.v:13: Unsupported: Ignoring delay on this delayed statement.\n        #100 a=1\'b0; b=1\'b0; carry_in=1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/469129654/src/full_adder_modular_testbench.v:14: Unsupported: Ignoring delay on this delayed statement.\n        #100 a=1\'b0; b=1\'b1; carry_in=1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/469129654/src/full_adder_modular_testbench.v:15: Unsupported: Ignoring delay on this delayed statement.\n        #100 a=1\'b1; b=1\'b0; carry_in=1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/469129654/src/full_adder_modular_testbench.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #100 a=1\'b1; b=1\'b1; carry_in=1\'b1;  \n        ^\n%Error: data/full_repos/permissive/469129654/src/full_adder_modular_testbench.v:5: Cannot find file containing module: \'full_adder_modular\'\n    full_adder_modular fa0(a, b, carry_in, sum, carry_out);\n    ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/469129654/src,data/full_repos/permissive/469129654/full_adder_modular\n             data/full_repos/permissive/469129654/src,data/full_repos/permissive/469129654/full_adder_modular.v\n             data/full_repos/permissive/469129654/src,data/full_repos/permissive/469129654/full_adder_modular.sv\n             full_adder_modular\n             full_adder_modular.v\n             full_adder_modular.sv\n             obj_dir/full_adder_modular\n             obj_dir/full_adder_modular.v\n             obj_dir/full_adder_modular.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module full_adder_modular_testbench;
    reg a, b, carry_in;
    wire sum, carry_out;

    full_adder_modular fa0(a, b, carry_in, sum, carry_out);

    initial begin
             a=1'b0; b=1'b0; carry_in=1'b0;
        #100 a=1'b0; b=1'b1; carry_in=1'b0;
        #100 a=1'b1; b=1'b0; carry_in=1'b0;
        #100 a=1'b1; b=1'b1; carry_in=1'b0;

        #100 a=1'b0; b=1'b0; carry_in=1'b1;
        #100 a=1'b0; b=1'b1; carry_in=1'b1;
        #100 a=1'b1; b=1'b0; carry_in=1'b1;
        #100 a=1'b1; b=1'b1; carry_in=1'b1;
    end

endmodule
module full_adder_modular_testbench;

    reg a, b, carry_in;
    wire sum, carry_out;

    full_adder_modular fa0(a, b, carry_in, sum, carry_out);

    initial begin
             a=1'b0; b=1'b0; carry_in=1'b0;
        #100 a=1'b0; b=1'b1; carry_in=1'b0;
        #100 a=1'b1; b=1'b0; carry_in=1'b0;
        #100 a=1'b1; b=1'b1; carry_in=1'b0;

        #100 a=1'b0; b=1'b0; carry_in=1'b1;
        #100 a=1'b0; b=1'b1; carry_in=1'b1;
        #100 a=1'b1; b=1'b0; carry_in=1'b1;
        #100 a=1'b1; b=1'b1; carry_in=1'b1;
    end

endmodule