data/full_repos/permissive/41807012/rtl/cia/sdio_cis.v
1: b'%Warning-WIDTH: data/full_repos/permissive/41807012/rtl/cia/sdio_cis.v:63: Bit extraction of array[10:0] requires 4 bit index, not 18 bits.\n                                                                         : ... In instance sdio_cis\n        o_data_out      <=  rom[i_address];\n                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module sdio_cis #(
  parameter                 FILE_LENGTH = 10,
  parameter                 FILENAME = "cis.rom"
)(
  input                     clk,
  input                     rst,

  input                     i_activate,
  input         [17:0]      i_address,
  input                     i_data_stb,
  output  reg   [7:0]       o_data_out
);


reg   [7:0]                 rom [0:FILE_LENGTH];




initial begin
  $readmemh(FILENAME, rom, 0, FILE_LENGTH - 1);
end

always @ (posedge clk) begin

  if (rst) begin
    o_data_out          <=  0;
  end
  else begin
    if (i_activate) begin
      if (i_data_stb) begin
        o_data_out      <=  rom[i_address];
      end
    end
  end
end

endmodule
module sdio_cis #(
  parameter                 FILE_LENGTH = 10,
  parameter                 FILENAME = "cis.rom"
)(
  input                     clk,
  input                     rst,

  input                     i_activate,
  input         [17:0]      i_address,
  input                     i_data_stb,
  output  reg   [7:0]       o_data_out
);



reg   [7:0]                 rom [0:FILE_LENGTH];




initial begin
  $readmemh(FILENAME, rom, 0, FILE_LENGTH - 1);
end

always @ (posedge clk) begin

  if (rst) begin
    o_data_out          <=  0;
  end
  else begin
    if (i_activate) begin
      if (i_data_stb) begin
        o_data_out      <=  rom[i_address];
      end
    end
  end
end

endmodule