data/full_repos/permissive/446312960/Verilog_Simulation/12_ff/ff_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/12_ff/ff_test.v:10: Unsupported: Ignoring delay on this delayed statement.\n   forever #50 t1 = ~t1;    \n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/12_ff/ff_test.v:19: Unsupported: Ignoring delay on this delayed statement.\n   #75;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/12_ff/ff_test.v:22: Unsupported: Ignoring delay on this delayed statement.\n   #85;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/12_ff/ff_test.v:25: Unsupported: Ignoring delay on this delayed statement.\n   #10;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/12_ff/ff_test.v:28: Unsupported: Ignoring delay on this delayed statement.\n   #35;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/12_ff/ff_test.v:31: Unsupported: Ignoring delay on this delayed statement.\n   #5;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/12_ff/ff_test.v:34: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-INFINITELOOP: data/full_repos/permissive/446312960/Verilog_Simulation/12_ff/ff_test.v:10: Infinite loop (condition always true)\n                                                                                                 : ... In instance ff_test\n   forever #50 t1 = ~t1;    \n   ^~~~~~~\n%Error: Exiting due to 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ff_test(t1, t2, p);

input  p;
output t1, t2;

reg t1, t2;


initial begin
   forever #50 t1 = ~t1;
end


initial begin
   t1 = 1'b0;

   t2 = 1'b0;
   
   #75;
   t2 = 1'b1;

   #85;
   t2 = 1'b0;

   #10;
   t2 = 1'b1;

   #35;
   t2 = 1'b0;

   #5;
   t2 = 1'b1;

   #100;
   $finish;
end

endmodule
module ff_test(t1, t2, p);


input  p;
output t1, t2;

reg t1, t2;


initial begin
   forever #50 t1 = ~t1;
end


initial begin
   t1 = 1'b0;

   t2 = 1'b0;
   
   #75;
   t2 = 1'b1;

   #85;
   t2 = 1'b0;

   #10;
   t2 = 1'b1;

   #35;
   t2 = 1'b0;

   #5;
   t2 = 1'b1;

   #100;
   $finish;
end

endmodule