data/full_repos/permissive/423216833/Introduction to Verilog Programming/1607021/testbench_1607021.v
1: b'%Error: Cannot find file containing module: to\n        ... Looked in:\n             data/full_repos/permissive/423216833/Introduction/to\n             data/full_repos/permissive/423216833/Introduction/to.v\n             data/full_repos/permissive/423216833/Introduction/to.sv\n             to\n             to.v\n             to.sv\n             obj_dir/to\n             obj_dir/to.v\n             obj_dir/to.sv\n%Error: Cannot find file containing module: Verilog\n%Error: Cannot find file containing module: Programming/1607021,data/full_repos/permissive/423216833\n%Error: Cannot find file containing module: data/full_repos/permissive/423216833/Introduction\n%Error: Cannot find file containing module: Programming/1607021/testbench_1607021.v\n%Error: Exiting due to 5 error(s)\n'
module tb_alu;
 reg[15:0] A,B;
 reg[3:0] ALU_Sel;

 wire[15:0] ALU_Out;
 wire CarryOut;

 integer i;
 alu test_unit(
            A,B,                 
            ALU_Sel,
            ALU_Out,
            CarryOut
     );

    initial begin
      A = 16'h0ABC;
      B = 16'h02BC;
      ALU_Sel = 4'h0;
      
      for (i=0;i<=15;i=i+1)
      begin
       ALU_Sel = ALU_Sel + 4'h1;
       #10;
      end
      
      A = 16'hF623;
      B = 16'h0A12;
      
    end
endmodule
module tb_alu;

 reg[15:0] A,B;
 reg[3:0] ALU_Sel;

 wire[15:0] ALU_Out;
 wire CarryOut;

 integer i;
 alu test_unit(
            A,B,                 
            ALU_Sel,
            ALU_Out,
            CarryOut
     );

    initial begin
      A = 16'h0ABC;
      B = 16'h02BC;
      ALU_Sel = 4'h0;
      
      for (i=0;i<=15;i=i+1)
      begin
       ALU_Sel = ALU_Sel + 4'h1;
       #10;
      end
      
      A = 16'hF623;
      B = 16'h0A12;
      
    end
endmodule