data/full_repos/permissive/524522105/sr74194/src/sr74194_test.v
1: b'%Warning-WIDTH: data/full_repos/permissive/524522105/sr74194/src/sr74194_test.v:11: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                  : ... In instance sr74194_test\n  reg  [5:0] counter = 4\'d0;\n                       ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/524522105/sr74194/src/sr74194_test.v:12: Cannot find file containing module: \'Gowin_CLKDIV\'\n  Gowin_CLKDIV       slow_clock ( .clkout(test_clock),\n  ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/524522105/sr74194/src,data/full_repos/permissive/524522105/Gowin_CLKDIV\n             data/full_repos/permissive/524522105/sr74194/src,data/full_repos/permissive/524522105/Gowin_CLKDIV.v\n             data/full_repos/permissive/524522105/sr74194/src,data/full_repos/permissive/524522105/Gowin_CLKDIV.sv\n             Gowin_CLKDIV\n             Gowin_CLKDIV.v\n             Gowin_CLKDIV.sv\n             obj_dir/Gowin_CLKDIV\n             obj_dir/Gowin_CLKDIV.v\n             obj_dir/Gowin_CLKDIV.sv\n%Error: data/full_repos/permissive/524522105/sr74194/src/sr74194_test.v:15: Cannot find file containing module: \'sr74194\'\n  sr74194            sr ( .clock (test_clock),\n  ^~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module sr74194_test ( input        clock,
                      output [6:0] diag );

  wire       test_clock;
  reg        serial_in;
  wire [3:0] data;
  reg  [5:0] counter = 4'd0;
  Gowin_CLKDIV       slow_clock ( .clkout(test_clock),
                                  .hclkin(clock),
                                  .resetn(1'b1) );
  sr74194            sr ( .clock (test_clock),
                          .serial_in(serial_in),
                          .parallel_out(data),
                          .parallel_in(4'b1111), 
                          .mode(counter[4]) );
  assign diag[3:0] = data;
  assign diag[4]   = serial_in;
  assign diag[5]   = counter[4];
  assign diag[6]   = test_clock;  

  always @ ( posedge test_clock )
  begin
    counter <= counter + 1;
    serial_in <= ~serial_in;
  end

endmodule
module sr74194_test ( input        clock,
                      output [6:0] diag );


  wire       test_clock;
  reg        serial_in;
  wire [3:0] data;
  reg  [5:0] counter = 4'd0;
  Gowin_CLKDIV       slow_clock ( .clkout(test_clock),
                                  .hclkin(clock),
                                  .resetn(1'b1) );
  sr74194            sr ( .clock (test_clock),
                          .serial_in(serial_in),
                          .parallel_out(data),
                          .parallel_in(4'b1111), 
                          .mode(counter[4]) );
  assign diag[3:0] = data;
  assign diag[4]   = serial_in;
  assign diag[5]   = counter[4];
  assign diag[6]   = test_clock;  

  always @ ( posedge test_clock )
  begin
    counter <= counter + 1;
    serial_in <= ~serial_in;
  end

endmodule