data/full_repos/permissive/499596866/FPGA/sources_1/new/clock_div.v
data/verilator_xmls/5902bfe0-c43a-4f11-8ad0-07e914e0f3af.xml
module clockDivider #(parameter n = 5 )  (input clk, rst, output reg clk_out, 
output reg [31:0]count);

    always @ (posedge(clk), posedge(rst))
     begin
        if (rst)
            begin
                count <= 32'b0;
                clk_out <= 1'b0;
            end
        else
            begin
                if (count == n-1) begin
                    count <= 32'b0;
                    clk_out <= ~clk_out; end
                else begin
                    count <= count + 1;
                    clk_out <= clk_out;
                end
            end
    end
endmodule
module clockDivider #(parameter n = 5 )  (input clk, rst, output reg clk_out, 
output reg [31:0]count);


    always @ (posedge(clk), posedge(rst))
     begin
        if (rst)
            begin
                count <= 32'b0;
                clk_out <= 1'b0;
            end
        else
            begin
                if (count == n-1) begin
                    count <= 32'b0;
                    clk_out <= ~clk_out; end
                else begin
                    count <= count + 1;
                    clk_out <= clk_out;
                end
            end
    end
endmodule