data/full_repos/permissive/447976230/fpga/usrp1/tb/decim_tb.v
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp1/tb/decim_tb.v:27: Cannot find include file: usrp_tasks.v\n`include "usrp_tasks.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp1/tb,data/full_repos/permissive/447976230/usrp_tasks.v\n             data/full_repos/permissive/447976230/fpga/usrp1/tb,data/full_repos/permissive/447976230/usrp_tasks.v.v\n             data/full_repos/permissive/447976230/fpga/usrp1/tb,data/full_repos/permissive/447976230/usrp_tasks.v.sv\n             usrp_tasks.v\n             usrp_tasks.v.v\n             usrp_tasks.v.sv\n             obj_dir/usrp_tasks.v\n             obj_dir/usrp_tasks.v.v\n             obj_dir/usrp_tasks.v.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/tb/decim_tb.v:58: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("decim_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/tb/decim_tb.v:59: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, fc_tb);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp1/tb/decim_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\ninitial #100000 $finish;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/tb/decim_tb.v:70: Unsupported or unknown PLI call: $monitor\ninitial $monitor(dac1_data);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp1/tb/decim_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\nalways #48 clk_120mhz = ~clk_120mhz;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp1/tb/decim_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\nalways #120 usbclk = ~usbclk;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp1/tb/decim_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\ninitial #500 reset = 1\'b0;\n        ^\n%Error: Exiting due to 4 error(s), 4 warning(s)\n'
module decim_tb();

`include "usrp_tasks.v"
   
	reg clk_120mhz;
	reg usbclk;
	reg reset;

	reg [11:0] adc1_data, adc2_data;
	wire [13:0] dac1_data, dac2_data;

	wire [5:0] usbctl;
	wire [5:0] usbrdy;

	wire [15:0] usbdata;

	reg WE, RD, OE;

        assign usbctl[0] = WE;
        assign usbctl[1] = RD;
        assign usbctl[2] = OE;
	assign usbctl[5:3] = 0;

	reg tb_oe;
	assign usbdata = tb_oe ? usbdatareg : 16'hxxxx;
	reg serload, serenable, serclk, serdata;
	reg enable_tx, enable_rx;
	reg [15:0] usbdatareg;



initial
begin
	$dumpfile("decim_tb.vcd");
	$dumpvars(0, fc_tb);
end

initial #100000 $finish;




reg [7:0] counter_decim;
wire [7:0] decim_rate;
assign decim_rate = 32;
initial $monitor(dac1_data);

       always @(posedge clk_120mhz)
        begin
                if(reset | ~enable_tx)
                        counter_decim <= #1 0;
                else if(counter_decim == 0)
                        counter_decim <= #1 decim_rate - 8'b1;
                else
                        counter_decim <= #1 counter_decim - 8'b1;
        end




initial clk_120mhz = 0;
initial usbclk = 0;
always #48 clk_120mhz = ~clk_120mhz;
always #120 usbclk = ~usbclk;

initial reset = 1'b1;
initial #500 reset = 1'b0;


initial enable_tx = 1'b1;

	wire [31:0] decim_out, q_decim_out;
	wire [31:0] decim_out;
	wire [31:0] phase;
			
	cic_decim #(.bitwidth(32),.stages(4)) 
		decim_i(.clock(clk_120mhz),.reset(reset),.enable(enable_tx),
			.strobe(counter_decim == 8'b0),.signal_in(32'h1),.signal_out(decim_out));

	cic_decim #(.bitwidth(32),.stages(4)) 
		decim(.clock(clk_120mhz),.reset(reset),.enable(enable_tx),
			.strobe(counter_decim == 8'b0),.signal_in(32'h1),.signal_out(decim_out));
			
endmodule
module decim_tb();


`include "usrp_tasks.v"
   
	reg clk_120mhz;
	reg usbclk;
	reg reset;

	reg [11:0] adc1_data, adc2_data;
	wire [13:0] dac1_data, dac2_data;

	wire [5:0] usbctl;
	wire [5:0] usbrdy;

	wire [15:0] usbdata;

	reg WE, RD, OE;

        assign usbctl[0] = WE;
        assign usbctl[1] = RD;
        assign usbctl[2] = OE;
	assign usbctl[5:3] = 0;

	reg tb_oe;
	assign usbdata = tb_oe ? usbdatareg : 16'hxxxx;
	reg serload, serenable, serclk, serdata;
	reg enable_tx, enable_rx;
	reg [15:0] usbdatareg;



initial
begin
	$dumpfile("decim_tb.vcd");
	$dumpvars(0, fc_tb);
end

initial #100000 $finish;




reg [7:0] counter_decim;
wire [7:0] decim_rate;
assign decim_rate = 32;
initial $monitor(dac1_data);

       always @(posedge clk_120mhz)
        begin
                if(reset | ~enable_tx)
                        counter_decim <= #1 0;
                else if(counter_decim == 0)
                        counter_decim <= #1 decim_rate - 8'b1;
                else
                        counter_decim <= #1 counter_decim - 8'b1;
        end




initial clk_120mhz = 0;
initial usbclk = 0;
always #48 clk_120mhz = ~clk_120mhz;
always #120 usbclk = ~usbclk;

initial reset = 1'b1;
initial #500 reset = 1'b0;


initial enable_tx = 1'b1;

	wire [31:0] decim_out, q_decim_out;
	wire [31:0] decim_out;
	wire [31:0] phase;
			
	cic_decim #(.bitwidth(32),.stages(4)) 
		decim_i(.clock(clk_120mhz),.reset(reset),.enable(enable_tx),
			.strobe(counter_decim == 8'b0),.signal_in(32'h1),.signal_out(decim_out));

	cic_decim #(.bitwidth(32),.stages(4)) 
		decim(.clock(clk_120mhz),.reset(reset),.enable(enable_tx),
			.strobe(counter_decim == 8'b0),.signal_in(32'h1),.signal_out(decim_out));
			
endmodule