data/full_repos/permissive/52900389/TB_Contador_16bits.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/52900389/TB_Contador_16bits.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/52900389/TB_Contador_16bits.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52900389/TB_Contador_16bits.v:55: Unsupported: Ignoring delay on this delayed statement.\nalways #10 clk = ~clk;\n       ^\n%Error: data/full_repos/permissive/52900389/TB_Contador_16bits.v:35: Cannot find file containing module: \'Universal_Binary_Counter\'\n Universal_Binary_Counter uut (\n ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52900389,data/full_repos/permissive/52900389/Universal_Binary_Counter\n             data/full_repos/permissive/52900389,data/full_repos/permissive/52900389/Universal_Binary_Counter.v\n             data/full_repos/permissive/52900389,data/full_repos/permissive/52900389/Universal_Binary_Counter.sv\n             Universal_Binary_Counter\n             Universal_Binary_Counter.v\n             Universal_Binary_Counter.sv\n             obj_dir/Universal_Binary_Counter\n             obj_dir/Universal_Binary_Counter.v\n             obj_dir/Universal_Binary_Counter.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TB_Contador_16bits;


	reg clk;
	reg rst;


	wire [15:0] out;


	Universal_Binary_Counter uut (
		.clk(clk), 
		.rst(rst), 
		.out(out)
	);

	initial 
	begin

		clk = 0;
		rst = 0;

		#100;
		rst = 1;
		#10;
		rst = 0;  


	end
	
always #10 clk = ~clk;


      
endmodule
module TB_Contador_16bits;



	reg clk;
	reg rst;


	wire [15:0] out;


	Universal_Binary_Counter uut (
		.clk(clk), 
		.rst(rst), 
		.out(out)
	);

	initial 
	begin

		clk = 0;
		rst = 0;

		#100;
		rst = 1;
		#10;
		rst = 0;  


	end
	
always #10 clk = ~clk;


      
endmodule