data/full_repos/permissive/480580678/hardware/testbench/system_core_tb.v
1: b'%Error: data/full_repos/permissive/480580678/hardware/testbench/system_core_tb.v:3: Cannot find include file: system.vh\n`include "system.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/480580678/hardware/testbench,data/full_repos/permissive/480580678/system.vh\n             data/full_repos/permissive/480580678/hardware/testbench,data/full_repos/permissive/480580678/system.vh.v\n             data/full_repos/permissive/480580678/hardware/testbench,data/full_repos/permissive/480580678/system.vh.sv\n             system.vh\n             system.vh.v\n             system.vh.sv\n             obj_dir/system.vh\n             obj_dir/system.vh.v\n             obj_dir/system.vh.sv\n%Error: data/full_repos/permissive/480580678/hardware/testbench/system_core_tb.v:283: Cannot find include file: cpu_tasks.v\n`include "cpu_tasks.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/480580678/hardware/testbench/system_core_tb.v:10: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n   parameter realtime clk_per = 1s/`FREQ;\n                                ^~\n%Error: data/full_repos/permissive/480580678/hardware/testbench/system_core_tb.v:10: Define or directive not defined: \'`FREQ\'\n   parameter realtime clk_per = 1s/`FREQ;\n                                   ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/480580678/hardware/testbench/system_core_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n   always #(clk_per/2) clk = ~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/480580678/hardware/testbench/system_core_tb.v:25: Define or directive not defined: \'`UART_ADDR_W\'\n   reg [`UART_ADDR_W-1:0] uart_addr;\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/480580678/hardware/testbench/system_core_tb.v:26: Define or directive not defined: \'`DATA_W\'\n   reg [`DATA_W-1:0]      uart_wdata;\n        ^~~~~~~\n%Error: data/full_repos/permissive/480580678/hardware/testbench/system_core_tb.v:28: Define or directive not defined: \'`DATA_W\'\n   wire [`DATA_W-1:0]     uart_rdata;\n         ^~~~~~~\n%Error: data/full_repos/permissive/480580678/hardware/testbench/system_core_tb.v:55: syntax error, unexpected \'@\'\n      repeat (100) @(posedge clk) #1;\n                   ^\n%Error: data/full_repos/permissive/480580678/hardware/testbench/system_core_tb.v:59: syntax error, unexpected \'@\'\n      repeat (10) @(posedge clk) #1;\n                  ^\n%Error: data/full_repos/permissive/480580678/hardware/testbench/system_core_tb.v:73: Define or directive not defined: \'`ENQ\'\n           `ENQ: begin\n           ^~~~\n%Error: data/full_repos/permissive/480580678/hardware/testbench/system_core_tb.v:73: syntax error, unexpected \':\', expecting endcase\n           `ENQ: begin\n               ^\n%Error: data/full_repos/permissive/480580678/hardware/testbench/system_core_tb.v:80: Define or directive not defined: \'`ACK\'\n                 cpu_putchar(`ACK);              \n                             ^~~~\n%Error: data/full_repos/permissive/480580678/hardware/testbench/system_core_tb.v:85: Define or directive not defined: \'`EOT\'\n           `EOT: begin\n           ^~~~\n%Error: data/full_repos/permissive/480580678/hardware/testbench/system_core_tb.v:85: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n           `EOT: begin\n                 ^~~~~\n%Error: data/full_repos/permissive/480580678/hardware/testbench/system_core_tb.v:90: Define or directive not defined: \'`FRX\'\n           `FRX: begin\n           ^~~~\n%Error: data/full_repos/permissive/480580678/hardware/testbench/system_core_tb.v:90: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n           `FRX: begin\n                 ^~~~~\n%Error: data/full_repos/permissive/480580678/hardware/testbench/system_core_tb.v:95: Define or directive not defined: \'`FTX\'\n           `FTX: begin\n           ^~~~\n%Error: data/full_repos/permissive/480580678/hardware/testbench/system_core_tb.v:95: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n           `FTX: begin\n                 ^~~~~\n%Error: data/full_repos/permissive/480580678/hardware/testbench/system_core_tb.v:100: syntax error, unexpected default\n           default: begin\n           ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/480580678/hardware/testbench/system_core_tb.v:287: Unsupported: Ignoring delay on this delayed statement.\n      #10 $display("Found CPU trap condition");\n      ^\n%Error: Exiting due to 19 error(s), 2 warning(s)\n'
module system_tb;

   parameter realtime clk_per = 1s/`FREQ;


   reg clk = 1;
   always #(clk_per/2) clk = ~clk;


   reg reset = 1;


   reg [7:0] cpu_char = 0;



   reg       uart_valid;
   reg [`UART_ADDR_W-1:0] uart_addr;
   reg [`DATA_W-1:0]      uart_wdata;
   reg [3:0]              uart_wstrb;
   wire [`DATA_W-1:0]     uart_rdata;
   wire                   uart_ready;


   integer                i;


   reg                    gotENQ;
   


   



   initial begin

`ifdef VCD
      $dumpfile("system.vcd");
      $dumpvars();
`endif


      uart_valid = 0;
      uart_wstrb = 0;
      

      repeat (100) @(posedge clk) #1;
      reset <= 0;


      repeat (10) @(posedge clk) #1;


      cpu_inituart();

      
      gotENQ = 0;
      
      $write("TESTBENCH: connecting");
      
      while(1) begin
         cpu_getchar(cpu_char);

         case(cpu_char)
           `ENQ: begin
              $write(".");
              if(!gotENQ) begin
                 gotENQ = 1;
`ifdef LD_FW
                 cpu_putchar(`FRX);
`else
                 cpu_putchar(`ACK);              
`endif      
              end
           end
           
           `EOT: begin
              $display("TESTBENCH: exiting\n\n\n");
              $finish;
           end
           
           `FRX: begin
              $display("TESTBENCH: got file send request");
              cpu_sendfile();
           end

           `FTX: begin
              $display("TESTBENCH: got file receive request");
              cpu_recvfile();
           end

           default: begin
              $write("%c", cpu_char);
           end

         endcase         
      end

   end

   





`ifdef USE_DDR

   wire [0:0] ddr_awid;
   wire [`DDR_ADDR_W-1:0] ddr_awaddr;
   wire [7:0]              ddr_awlen;
   wire [2:0]              ddr_awsize;
   wire [1:0]              ddr_awburst;
   wire                    ddr_awlock;
   wire [3:0]              ddr_awcache;
   wire [2:0]              ddr_awprot;
   wire [3:0]              ddr_awqos;
   wire                    ddr_awvalid;
   wire                    ddr_awready;

   wire [31:0]             ddr_wdata;
   wire [3:0]              ddr_wstrb;
   wire                    ddr_wlast;
   wire                    ddr_wvalid;
   wire                    ddr_wready;

   wire [7:0]              ddr_bid;
   wire [1:0]              ddr_bresp;
   wire                    ddr_bvalid;
   wire                    ddr_bready;

   wire [0:0]              ddr_arid;
   wire [`DDR_ADDR_W-1:0] ddr_araddr;
   wire [7:0]              ddr_arlen;
   wire [2:0]              ddr_arsize;
   wire [1:0]              ddr_arburst;
   wire                    ddr_arlock;
   wire [3:0]              ddr_arcache;
   wire [2:0]              ddr_arprot;
   wire [3:0]              ddr_arqos;
   wire                    ddr_arvalid;
   wire                    ddr_arready;

   wire [7:0]              ddr_rid;
   wire [31:0]             ddr_rdata;
   wire [1:0]              ddr_rresp;
   wire                    ddr_rlast;
   wire                    ddr_rvalid;
   wire                    ddr_rready;
`endif


   wire                    trap;
   



   system uut (

`ifdef USE_DDR

	       .m_axi_awid    (ddr_awid),
	       .m_axi_awaddr  (ddr_awaddr),
	       .m_axi_awlen   (ddr_awlen),
	       .m_axi_awsize  (ddr_awsize),
	       .m_axi_awburst (ddr_awburst),
	       .m_axi_awlock  (ddr_awlock),
	       .m_axi_awcache (ddr_awcache),
	       .m_axi_awprot  (ddr_awprot),
	       .m_axi_awqos   (ddr_awqos),
	       .m_axi_awvalid (ddr_awvalid),
	       .m_axi_awready (ddr_awready),
               

	       .m_axi_wdata   (ddr_wdata),
	       .m_axi_wstrb   (ddr_wstrb),
	       .m_axi_wlast   (ddr_wlast),
	       .m_axi_wvalid  (ddr_wvalid),
	       .m_axi_wready  (ddr_wready),
               

	       .m_axi_bid     (ddr_bid[0]),
	       .m_axi_bresp   (ddr_bresp),
	       .m_axi_bvalid  (ddr_bvalid),
	       .m_axi_bready  (ddr_bready),
               

	       .m_axi_arid    (ddr_arid),
	       .m_axi_araddr  (ddr_araddr),
	       .m_axi_arlen   (ddr_arlen),
	       .m_axi_arsize  (ddr_arsize),
	       .m_axi_arburst (ddr_arburst),
	       .m_axi_arlock  (ddr_arlock),
	       .m_axi_arcache (ddr_arcache),
	       .m_axi_arprot  (ddr_arprot),
	       .m_axi_arqos   (ddr_arqos),
	       .m_axi_arvalid (ddr_arvalid),
	       .m_axi_arready (ddr_arready),
               

	       .m_axi_rid     (ddr_rid[0]),
	       .m_axi_rdata   (ddr_rdata),
	       .m_axi_rresp   (ddr_rresp),
	       .m_axi_rlast   (ddr_rlast),
	       .m_axi_rvalid  (ddr_rvalid),
	       .m_axi_rready  (ddr_rready),	
`endif               
	       .clk           (clk),
	       .reset         (reset),
	       .trap          (trap)
	       );



`ifdef USE_DDR
   axi_ram 
     #(
 `ifdef DDR_INIT
       .FILE("firmware.hex"),
 `endif
       .DATA_WIDTH (`DATA_W),
       .ADDR_WIDTH (`DDR_ADDR_W)
       )
   ddr_model_mem(

                 .clk            (clk),
                 .rst            (reset),
		 .s_axi_awid     ({8{ddr_awid}}),
		 .s_axi_awaddr   (ddr_awaddr[`DDR_ADDR_W-1:0]),
                 .s_axi_awlen    (ddr_awlen),
                 .s_axi_awsize   (ddr_awsize),
                 .s_axi_awburst  (ddr_awburst),
                 .s_axi_awlock   (ddr_awlock),
		 .s_axi_awprot   (ddr_awprot),
		 .s_axi_awcache  (ddr_awcache),
     		 .s_axi_awvalid  (ddr_awvalid),
		 .s_axi_awready  (ddr_awready),
      

		 .s_axi_wvalid   (ddr_wvalid),
		 .s_axi_wready   (ddr_wready),
		 .s_axi_wdata    (ddr_wdata),
		 .s_axi_wstrb    (ddr_wstrb),
                 .s_axi_wlast    (ddr_wlast),
      

		 .s_axi_bready   (ddr_bready),
                 .s_axi_bid      (ddr_bid),
                 .s_axi_bresp    (ddr_bresp),
		 .s_axi_bvalid   (ddr_bvalid),
      

		 .s_axi_arid     ({8{ddr_arid}}),
		 .s_axi_araddr   (ddr_araddr[`DDR_ADDR_W-1:0]),
		 .s_axi_arlen    (ddr_arlen), 
		 .s_axi_arsize   (ddr_arsize),    
                 .s_axi_arburst  (ddr_arburst),
                 .s_axi_arlock   (ddr_arlock),
                 .s_axi_arcache  (ddr_arcache),
                 .s_axi_arprot   (ddr_arprot),
		 .s_axi_arvalid  (ddr_arvalid),
		 .s_axi_arready  (ddr_arready),
      

		 .s_axi_rready   (ddr_rready),
		 .s_axi_rid      (ddr_rid),
		 .s_axi_rdata    (ddr_rdata),
		 .s_axi_rresp    (ddr_rresp),
                 .s_axi_rlast    (ddr_rlast),
		 .s_axi_rvalid   (ddr_rvalid)
                 );   
`endif


`include "cpu_tasks.v"
   

   always @(posedge trap) begin
      #10 $display("Found CPU trap condition");
      $finish;
   end



   
endmodule
module system_tb;


   parameter realtime clk_per = 1s/`FREQ;


   reg clk = 1;
   always #(clk_per/2) clk = ~clk;


   reg reset = 1;


   reg [7:0] cpu_char = 0;



   reg       uart_valid;
   reg [`UART_ADDR_W-1:0] uart_addr;
   reg [`DATA_W-1:0]      uart_wdata;
   reg [3:0]              uart_wstrb;
   wire [`DATA_W-1:0]     uart_rdata;
   wire                   uart_ready;


   integer                i;


   reg                    gotENQ;
   


   



   initial begin

`ifdef VCD
      $dumpfile("system.vcd");
      $dumpvars();
`endif


      uart_valid = 0;
      uart_wstrb = 0;
      

      repeat (100) @(posedge clk) #1;
      reset <= 0;


      repeat (10) @(posedge clk) #1;


      cpu_inituart();

      
      gotENQ = 0;
      
      $write("TESTBENCH: connecting");
      
      while(1) begin
         cpu_getchar(cpu_char);

         case(cpu_char)
           `ENQ: begin
              $write(".");
              if(!gotENQ) begin
                 gotENQ = 1;
`ifdef LD_FW
                 cpu_putchar(`FRX);
`else
                 cpu_putchar(`ACK);              
`endif      
              end
           end
           
           `EOT: begin
              $display("TESTBENCH: exiting\n\n\n");
              $finish;
           end
           
           `FRX: begin
              $display("TESTBENCH: got file send request");
              cpu_sendfile();
           end

           `FTX: begin
              $display("TESTBENCH: got file receive request");
              cpu_recvfile();
           end

           default: begin
              $write("%c", cpu_char);
           end

         endcase         
      end

   end

   





`ifdef USE_DDR

   wire [0:0] ddr_awid;
   wire [`DDR_ADDR_W-1:0] ddr_awaddr;
   wire [7:0]              ddr_awlen;
   wire [2:0]              ddr_awsize;
   wire [1:0]              ddr_awburst;
   wire                    ddr_awlock;
   wire [3:0]              ddr_awcache;
   wire [2:0]              ddr_awprot;
   wire [3:0]              ddr_awqos;
   wire                    ddr_awvalid;
   wire                    ddr_awready;

   wire [31:0]             ddr_wdata;
   wire [3:0]              ddr_wstrb;
   wire                    ddr_wlast;
   wire                    ddr_wvalid;
   wire                    ddr_wready;

   wire [7:0]              ddr_bid;
   wire [1:0]              ddr_bresp;
   wire                    ddr_bvalid;
   wire                    ddr_bready;

   wire [0:0]              ddr_arid;
   wire [`DDR_ADDR_W-1:0] ddr_araddr;
   wire [7:0]              ddr_arlen;
   wire [2:0]              ddr_arsize;
   wire [1:0]              ddr_arburst;
   wire                    ddr_arlock;
   wire [3:0]              ddr_arcache;
   wire [2:0]              ddr_arprot;
   wire [3:0]              ddr_arqos;
   wire                    ddr_arvalid;
   wire                    ddr_arready;

   wire [7:0]              ddr_rid;
   wire [31:0]             ddr_rdata;
   wire [1:0]              ddr_rresp;
   wire                    ddr_rlast;
   wire                    ddr_rvalid;
   wire                    ddr_rready;
`endif


   wire                    trap;
   



   system uut (

`ifdef USE_DDR

	       .m_axi_awid    (ddr_awid),
	       .m_axi_awaddr  (ddr_awaddr),
	       .m_axi_awlen   (ddr_awlen),
	       .m_axi_awsize  (ddr_awsize),
	       .m_axi_awburst (ddr_awburst),
	       .m_axi_awlock  (ddr_awlock),
	       .m_axi_awcache (ddr_awcache),
	       .m_axi_awprot  (ddr_awprot),
	       .m_axi_awqos   (ddr_awqos),
	       .m_axi_awvalid (ddr_awvalid),
	       .m_axi_awready (ddr_awready),
               

	       .m_axi_wdata   (ddr_wdata),
	       .m_axi_wstrb   (ddr_wstrb),
	       .m_axi_wlast   (ddr_wlast),
	       .m_axi_wvalid  (ddr_wvalid),
	       .m_axi_wready  (ddr_wready),
               

	       .m_axi_bid     (ddr_bid[0]),
	       .m_axi_bresp   (ddr_bresp),
	       .m_axi_bvalid  (ddr_bvalid),
	       .m_axi_bready  (ddr_bready),
               

	       .m_axi_arid    (ddr_arid),
	       .m_axi_araddr  (ddr_araddr),
	       .m_axi_arlen   (ddr_arlen),
	       .m_axi_arsize  (ddr_arsize),
	       .m_axi_arburst (ddr_arburst),
	       .m_axi_arlock  (ddr_arlock),
	       .m_axi_arcache (ddr_arcache),
	       .m_axi_arprot  (ddr_arprot),
	       .m_axi_arqos   (ddr_arqos),
	       .m_axi_arvalid (ddr_arvalid),
	       .m_axi_arready (ddr_arready),
               

	       .m_axi_rid     (ddr_rid[0]),
	       .m_axi_rdata   (ddr_rdata),
	       .m_axi_rresp   (ddr_rresp),
	       .m_axi_rlast   (ddr_rlast),
	       .m_axi_rvalid  (ddr_rvalid),
	       .m_axi_rready  (ddr_rready),	
`endif               
	       .clk           (clk),
	       .reset         (reset),
	       .trap          (trap)
	       );



`ifdef USE_DDR
   axi_ram 
     #(
 `ifdef DDR_INIT
       .FILE("firmware.hex"),
 `endif
       .DATA_WIDTH (`DATA_W),
       .ADDR_WIDTH (`DDR_ADDR_W)
       )
   ddr_model_mem(

                 .clk            (clk),
                 .rst            (reset),
		 .s_axi_awid     ({8{ddr_awid}}),
		 .s_axi_awaddr   (ddr_awaddr[`DDR_ADDR_W-1:0]),
                 .s_axi_awlen    (ddr_awlen),
                 .s_axi_awsize   (ddr_awsize),
                 .s_axi_awburst  (ddr_awburst),
                 .s_axi_awlock   (ddr_awlock),
		 .s_axi_awprot   (ddr_awprot),
		 .s_axi_awcache  (ddr_awcache),
     		 .s_axi_awvalid  (ddr_awvalid),
		 .s_axi_awready  (ddr_awready),
      

		 .s_axi_wvalid   (ddr_wvalid),
		 .s_axi_wready   (ddr_wready),
		 .s_axi_wdata    (ddr_wdata),
		 .s_axi_wstrb    (ddr_wstrb),
                 .s_axi_wlast    (ddr_wlast),
      

		 .s_axi_bready   (ddr_bready),
                 .s_axi_bid      (ddr_bid),
                 .s_axi_bresp    (ddr_bresp),
		 .s_axi_bvalid   (ddr_bvalid),
      

		 .s_axi_arid     ({8{ddr_arid}}),
		 .s_axi_araddr   (ddr_araddr[`DDR_ADDR_W-1:0]),
		 .s_axi_arlen    (ddr_arlen), 
		 .s_axi_arsize   (ddr_arsize),    
                 .s_axi_arburst  (ddr_arburst),
                 .s_axi_arlock   (ddr_arlock),
                 .s_axi_arcache  (ddr_arcache),
                 .s_axi_arprot   (ddr_arprot),
		 .s_axi_arvalid  (ddr_arvalid),
		 .s_axi_arready  (ddr_arready),
      

		 .s_axi_rready   (ddr_rready),
		 .s_axi_rid      (ddr_rid),
		 .s_axi_rdata    (ddr_rdata),
		 .s_axi_rresp    (ddr_rresp),
                 .s_axi_rlast    (ddr_rlast),
		 .s_axi_rvalid   (ddr_rvalid)
                 );   
`endif


`include "cpu_tasks.v"
   

   always @(posedge trap) begin
      #10 $display("Found CPU trap condition");
      $finish;
   end



   
endmodule