data/full_repos/permissive/522534105/RTL_files/Multiplicand_M.v
data/verilator_xmls/80b7772f-0fac-4db4-afa2-edd5b6e3ac80.xml
module Multiplicand_M(
input i_clk , 
input i_rst_n , 
input ld_M , 
input [`WIDTH_M-1:0] data_M  , 
output [`WIDTH_M-1:0] o_data_M
    );
 reg [`WIDTH_M-1:0] o_Mout ;
 
 
 always @(posedge i_clk)
       begin
           if (~i_rst_n)
               o_Mout <= 0;
                 else 
                   begin
                        if (ld_M==1'b1)
                          o_Mout <= data_M ;
                            else
                         o_Mout <= o_Mout ;
                    end
        end 
    assign o_data_M = o_Mout ;                                     
endmodule
module Multiplicand_M(
input i_clk , 
input i_rst_n , 
input ld_M , 
input [`WIDTH_M-1:0] data_M  , 
output [`WIDTH_M-1:0] o_data_M
    );

 reg [`WIDTH_M-1:0] o_Mout ;
 
 
 always @(posedge i_clk)
       begin
           if (~i_rst_n)
               o_Mout <= 0;
                 else 
                   begin
                        if (ld_M==1'b1)
                          o_Mout <= data_M ;
                            else
                         o_Mout <= o_Mout ;
                    end
        end 
    assign o_data_M = o_Mout ;                                     
endmodule