data/full_repos/permissive/44389528/rtl/aes_128.v
1: b"%Error: data/full_repos/permissive/44389528/rtl/aes_128.v:80: Cannot find file containing module: 'S4'\n    S4\n    ^~\n        ... Looked in:\n             data/full_repos/permissive/44389528/rtl,data/full_repos/permissive/44389528/S4\n             data/full_repos/permissive/44389528/rtl,data/full_repos/permissive/44389528/S4.v\n             data/full_repos/permissive/44389528/rtl,data/full_repos/permissive/44389528/S4.sv\n             S4\n             S4.v\n             S4.sv\n             obj_dir/S4\n             obj_dir/S4.v\n             obj_dir/S4.sv\n%Error: data/full_repos/permissive/44389528/rtl/aes_128.v:44: Cannot find file containing module: 'one_round'\n    one_round\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/44389528/rtl/aes_128.v:55: Cannot find file containing module: 'final_round'\n    final_round\n    ^~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module expand_key_128(in, out_1, out_2, rcon);
    
    input      [127:0] in;
    input      [7:0]   rcon;
    output reg [127:0] out_1;
    output     [127:0] out_2;
    wire       [31:0]  k0, k1, k2, k3,
                       v0, v1, v2, v3;
    reg        [31:0]  k0a, k1a, k2a, k3a;
    wire       [31:0]  k0b, k1b, k2b, k3b, k4a;

    assign {k0, k1, k2, k3} = in;
    
    assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
    assign v1 = v0 ^ k1;
    assign v2 = v1 ^ k2;
    assign v3 = v2 ^ k3;

    always @ (*)
        {k0a, k1a, k2a, k3a} <= {v0, v1, v2, v3};

    S4
        S4_0 ({k3[23:0], k3[31:24]}, k4a);

    assign k0b = k0a ^ k4a;
    assign k1b = k1a ^ k4a;
    assign k2b = k2a ^ k4a;
    assign k3b = k3a ^ k4a;

    always @ (*)
        out_1 <= {k0b, k1b, k2b, k3b};

    assign out_2 = {k0b, k1b, k2b, k3b};
endmodule
module expand_key_128(in, out_1, out_2, rcon);

    
    input      [127:0] in;
    input      [7:0]   rcon;
    output reg [127:0] out_1;
    output     [127:0] out_2;
    wire       [31:0]  k0, k1, k2, k3,
                       v0, v1, v2, v3;
    reg        [31:0]  k0a, k1a, k2a, k3a;
    wire       [31:0]  k0b, k1b, k2b, k3b, k4a;

    assign {k0, k1, k2, k3} = in;
    
    assign v0 = {k0[31:24] ^ rcon, k0[23:0]};
    assign v1 = v0 ^ k1;
    assign v2 = v1 ^ k2;
    assign v3 = v2 ^ k3;

    always @ (*)
        {k0a, k1a, k2a, k3a} <= {v0, v1, v2, v3};

    S4
        S4_0 ({k3[23:0], k3[31:24]}, k4a);

    assign k0b = k0a ^ k4a;
    assign k1b = k1a ^ k4a;
    assign k2b = k2a ^ k4a;
    assign k3b = k3a ^ k4a;

    always @ (*)
        out_1 <= {k0b, k1b, k2b, k3b};

    assign out_2 = {k0b, k1b, k2b, k3b};
endmodule