data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/RegFile_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/RegFile_TB.v:22: Unsupported: Ignoring delay on this delayed statement.\n            #5;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/RegFile_TB.v:24: Unsupported: Ignoring delay on this delayed statement.\n            #5;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/RegFile_TB.v:36: Unsupported: Ignoring delay on this delayed statement.\n       #10;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/RegFile_TB.v:44: Unsupported: Ignoring delay on this delayed statement.\n       #10;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/RegFile_TB.v:52: Unsupported: Ignoring delay on this delayed statement.\n       #1;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/RegFile_TB.v:54: Unsupported: Ignoring delay on this delayed statement.\n       #9;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/RegFile_TB.v:63: Unsupported: Ignoring delay on this delayed statement.\n       #1;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/RegFile_TB.v:65: Unsupported: Ignoring delay on this delayed statement.\n       #9;\n       ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/RegFile_TB.v:16: Cannot find file containing module: \'RegFile\'\n    RegFile DUT(.clk(clk), .we(we), .rd(rd),.rs1(rs1), .rs2(rs2),\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new,data/full_repos/permissive/433174928/RegFile\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new,data/full_repos/permissive/433174928/RegFile.v\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new,data/full_repos/permissive/433174928/RegFile.sv\n             RegFile\n             RegFile.v\n             RegFile.sv\n             obj_dir/RegFile\n             obj_dir/RegFile.v\n             obj_dir/RegFile.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module RegFile_TB(

    );

    reg clk;
    reg [4:0] rs1;                 
    reg [4:0] rs2;                 
    reg [4:0] rd;                  
    reg we;                        
    reg [31:0] rd_data_in;         
    wire [31:0] rs1_data;          
    wire [31:0] rs2_data;
    
    RegFile DUT(.clk(clk), .we(we), .rd(rd),.rs1(rs1), .rs2(rs2),
                .rd_data_in(rd_data_in),.rs1_data(rs1_data), .rs2_data(rs2_data));    
    
    initial begin: CLK_GEN
        forever begin
            clk <=1;
            #5;
            clk <=0;
            #5;
        end
    end
    
    initial begin : TEST_PROCESS
    

       rs1 <= 5'b00001;            
       rs2 <= 5'b00010;            
       we <=1;
       rd <= 5'b00101;             
       rd_data_in <= 32'h89ABCDEF;
       #10;
       

       we <=1;
       rs1 <= 5'b00001;            
       rs2 <= 5'b00010;            
       rd <=5'b00110;  
       rd_data_in <= 32'h01234567;
       #10;


       we <=0;
       rs1 <= 5'b00101;            
       rs2 <= 5'b00110;            
       rd <=5'b00001;  
       rd_data_in <= 32'd0;
       #1;
       if((rs1_data!=32'h89ABCDEF)&(rs2_data!=32'h01234567)) $fatal("Read Operation failed");
       #9;
       
       

       we<=1;
       rs1 <= 5'b00000;            
       rs2 <= 5'b00000;            
       rd <=5'b00000;
       rd_data_in <= 32'h01234567;
       #1;
       if((rs1_data!=32'h00000000)&(rs2_data!=32'h00000000)) $fatal("Register 0 is special read-only register, we cannot write to it even if write enable is high");
       #9;
  
       $display("All tests passed");
       $finish;
     
    end

endmodule
module RegFile_TB(

    );


    reg clk;
    reg [4:0] rs1;                 
    reg [4:0] rs2;                 
    reg [4:0] rd;                  
    reg we;                        
    reg [31:0] rd_data_in;         
    wire [31:0] rs1_data;          
    wire [31:0] rs2_data;
    
    RegFile DUT(.clk(clk), .we(we), .rd(rd),.rs1(rs1), .rs2(rs2),
                .rd_data_in(rd_data_in),.rs1_data(rs1_data), .rs2_data(rs2_data));    
    
    initial begin: CLK_GEN
        forever begin
            clk <=1;
            #5;
            clk <=0;
            #5;
        end
    end
    
    initial begin : TEST_PROCESS
    

       rs1 <= 5'b00001;            
       rs2 <= 5'b00010;            
       we <=1;
       rd <= 5'b00101;             
       rd_data_in <= 32'h89ABCDEF;
       #10;
       

       we <=1;
       rs1 <= 5'b00001;            
       rs2 <= 5'b00010;            
       rd <=5'b00110;  
       rd_data_in <= 32'h01234567;
       #10;


       we <=0;
       rs1 <= 5'b00101;            
       rs2 <= 5'b00110;            
       rd <=5'b00001;  
       rd_data_in <= 32'd0;
       #1;
       if((rs1_data!=32'h89ABCDEF)&(rs2_data!=32'h01234567)) $fatal("Read Operation failed");
       #9;
       
       

       we<=1;
       rs1 <= 5'b00000;            
       rs2 <= 5'b00000;            
       rd <=5'b00000;
       rd_data_in <= 32'h01234567;
       #1;
       if((rs1_data!=32'h00000000)&(rs2_data!=32'h00000000)) $fatal("Register 0 is special read-only register, we cannot write to it even if write enable is high");
       #9;
  
       $display("All tests passed");
       $finish;
     
    end

endmodule