data/full_repos/permissive/458208177/hdl/32_bit_add_cla_tree.v
data/verilator_xmls/58351226-0f93-46d8-8a2a-3b95175c06b8.xml
module cla_gp_8_bit(S, C, G, P, C0, A, B);
    output [7:0] S;
    output [7:0] C;
    output G, P;

    input C0;
    input [7:0] A;
    input [7:0] B;


    wire [7:0] g_fa_out;
    wire [7:0] p_fa_out;

    wire [7:0] C_in;



    wire [3:0] g_hl_out_level_1;
    wire [3:0] p_hl_out_level_1;
    wire [3:0] c_in_level_1;


    wire [1:0] g_hl_out_level_2;
    wire [1:0] p_hl_out_level_2;
    wire [1:0] c_in_level_2;



    full_adder_gp fa_arr[7:0] (S, C, g_fa_out, p_fa_out, A, B, C_in);




    gpc GPC1_l1(g_hl_out_level_1[0], p_hl_out_level_1[0], C_in[1], C_in[0], g_fa_out[1], p_fa_out[1], g_fa_out[0], p_fa_out[0], c_in_level_1[0]);
    gpc GPC2_l1(g_hl_out_level_1[1], p_hl_out_level_1[1], C_in[3], C_in[2], g_fa_out[3], p_fa_out[3], g_fa_out[2], p_fa_out[2], c_in_level_1[1]);
    gpc GPC3_l1(g_hl_out_level_1[2], p_hl_out_level_1[2], C_in[5], C_in[4], g_fa_out[5], p_fa_out[5], g_fa_out[4], p_fa_out[4], c_in_level_1[2]);
    gpc GPC4_l1(g_hl_out_level_1[3], p_hl_out_level_1[3], C_in[7], C_in[6], g_fa_out[7], p_fa_out[7], g_fa_out[6], p_fa_out[6], c_in_level_1[3]);



    gpc GPC1_l2(g_hl_out_level_2[0], p_hl_out_level_2[0], c_in_level_1[1], c_in_level_1[0],
        g_hl_out_level_1[1], p_hl_out_level_1[1], g_hl_out_level_1[0], p_hl_out_level_1[0], c_in_level_2[0]);
    gpc GPC2_l2(g_hl_out_level_2[1], p_hl_out_level_2[1], c_in_level_1[3], c_in_level_1[2],
        g_hl_out_level_1[3], p_hl_out_level_1[3], g_hl_out_level_1[2], p_hl_out_level_1[2], c_in_level_2[1]);


    gpc GPC1_l3(G, P, c_in_level_2[1], c_in_level_2[0], g_hl_out_level_2[1], p_hl_out_level_2[1], g_hl_out_level_2[0], p_hl_out_level_2[0], C0);
endmodule
module cla_gp_8_bit(S, C, G, P, C0, A, B);

    output [7:0] S;
    output [7:0] C;
    output G, P;

    input C0;
    input [7:0] A;
    input [7:0] B;


    wire [7:0] g_fa_out;
    wire [7:0] p_fa_out;

    wire [7:0] C_in;



    wire [3:0] g_hl_out_level_1;
    wire [3:0] p_hl_out_level_1;
    wire [3:0] c_in_level_1;


    wire [1:0] g_hl_out_level_2;
    wire [1:0] p_hl_out_level_2;
    wire [1:0] c_in_level_2;



    full_adder_gp fa_arr[7:0] (S, C, g_fa_out, p_fa_out, A, B, C_in);




    gpc GPC1_l1(g_hl_out_level_1[0], p_hl_out_level_1[0], C_in[1], C_in[0], g_fa_out[1], p_fa_out[1], g_fa_out[0], p_fa_out[0], c_in_level_1[0]);
    gpc GPC2_l1(g_hl_out_level_1[1], p_hl_out_level_1[1], C_in[3], C_in[2], g_fa_out[3], p_fa_out[3], g_fa_out[2], p_fa_out[2], c_in_level_1[1]);
    gpc GPC3_l1(g_hl_out_level_1[2], p_hl_out_level_1[2], C_in[5], C_in[4], g_fa_out[5], p_fa_out[5], g_fa_out[4], p_fa_out[4], c_in_level_1[2]);
    gpc GPC4_l1(g_hl_out_level_1[3], p_hl_out_level_1[3], C_in[7], C_in[6], g_fa_out[7], p_fa_out[7], g_fa_out[6], p_fa_out[6], c_in_level_1[3]);



    gpc GPC1_l2(g_hl_out_level_2[0], p_hl_out_level_2[0], c_in_level_1[1], c_in_level_1[0],
        g_hl_out_level_1[1], p_hl_out_level_1[1], g_hl_out_level_1[0], p_hl_out_level_1[0], c_in_level_2[0]);
    gpc GPC2_l2(g_hl_out_level_2[1], p_hl_out_level_2[1], c_in_level_1[3], c_in_level_1[2],
        g_hl_out_level_1[3], p_hl_out_level_1[3], g_hl_out_level_1[2], p_hl_out_level_1[2], c_in_level_2[1]);


    gpc GPC1_l3(G, P, c_in_level_2[1], c_in_level_2[0], g_hl_out_level_2[1], p_hl_out_level_2[1], g_hl_out_level_2[0], p_hl_out_level_2[0], C0);
endmodule