data/full_repos/permissive/464047548/display_timings.v
data/verilator_xmls/b756907b-b3ec-4ab1-9066-a6d7e7f00da2.xml
module display_timings #(
    parameter H_RES=640,
    parameter V_RES=480,
    parameter H_FP=16,
    parameter H_SYNC=96,
    parameter H_BP=48,
    parameter V_FP=10,
    parameter V_SYNC=2,
    parameter V_BP=33,
    parameter H_POL=0,
    parameter V_POL=0
    )
    (
    input  wire i_pix_clk,
    input  wire i_rst,
    output wire o_hs,
    output wire o_vs,
    output wire o_de,
    output wire o_frame,
    output reg signed [15:0] o_sx,
    output reg signed [15:0] o_sy
    );


    localparam signed H_STA  = 0 - H_FP - H_SYNC - H_BP;
    localparam signed HS_STA = H_STA + H_FP;
    localparam signed HS_END = HS_STA + H_SYNC;
    localparam signed HA_STA = 0;
    localparam signed HA_END = H_RES - 1;


    localparam signed V_STA  = 0 - V_FP - V_SYNC - V_BP;
    localparam signed VS_STA = V_STA + V_FP;
    localparam signed VS_END = VS_STA + V_SYNC;
    localparam signed VA_STA = 0;
    localparam signed VA_END = V_RES - 1;


    assign o_hs = H_POL ? (o_sx > HS_STA && o_sx <= HS_END)
        : ~(o_sx > HS_STA && o_sx <= HS_END);
    assign o_vs = V_POL ? (o_sy > VS_STA && o_sy <= VS_END)
        : ~(o_sy > VS_STA && o_sy <= VS_END);


    assign o_de = (o_sx >= 0 && o_sy >= 0);


    assign o_frame = (o_sy == V_STA && o_sx == H_STA);

    always @ (posedge i_pix_clk)
    begin
        if (i_rst)
        begin
            o_sx <= H_STA;
            o_sy <= V_STA;
        end
        else
        begin
            if (o_sx == HA_END)
            begin
                o_sx <= H_STA;
                if (o_sy == VA_END)
                    o_sy <= V_STA;
                else
                    o_sy <= o_sy + 16'sh1;
            end
            else
                o_sx <= o_sx + 16'sh1;
        end
    end
endmodule
module display_timings #(
    parameter H_RES=640,
    parameter V_RES=480,
    parameter H_FP=16,
    parameter H_SYNC=96,
    parameter H_BP=48,
    parameter V_FP=10,
    parameter V_SYNC=2,
    parameter V_BP=33,
    parameter H_POL=0,
    parameter V_POL=0
    )
    (
    input  wire i_pix_clk,
    input  wire i_rst,
    output wire o_hs,
    output wire o_vs,
    output wire o_de,
    output wire o_frame,
    output reg signed [15:0] o_sx,
    output reg signed [15:0] o_sy
    );



    localparam signed H_STA  = 0 - H_FP - H_SYNC - H_BP;
    localparam signed HS_STA = H_STA + H_FP;
    localparam signed HS_END = HS_STA + H_SYNC;
    localparam signed HA_STA = 0;
    localparam signed HA_END = H_RES - 1;


    localparam signed V_STA  = 0 - V_FP - V_SYNC - V_BP;
    localparam signed VS_STA = V_STA + V_FP;
    localparam signed VS_END = VS_STA + V_SYNC;
    localparam signed VA_STA = 0;
    localparam signed VA_END = V_RES - 1;


    assign o_hs = H_POL ? (o_sx > HS_STA && o_sx <= HS_END)
        : ~(o_sx > HS_STA && o_sx <= HS_END);
    assign o_vs = V_POL ? (o_sy > VS_STA && o_sy <= VS_END)
        : ~(o_sy > VS_STA && o_sy <= VS_END);


    assign o_de = (o_sx >= 0 && o_sy >= 0);


    assign o_frame = (o_sy == V_STA && o_sx == H_STA);

    always @ (posedge i_pix_clk)
    begin
        if (i_rst)
        begin
            o_sx <= H_STA;
            o_sy <= V_STA;
        end
        else
        begin
            if (o_sx == HA_END)
            begin
                o_sx <= H_STA;
                if (o_sy == VA_END)
                    o_sy <= V_STA;
                else
                    o_sy <= o_sy + 16'sh1;
            end
            else
                o_sx <= o_sx + 16'sh1;
        end
    end
endmodule