data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/custom_gen/my_D_FF.v
data/verilator_xmls/8d025452-aa12-4a78-bbd7-8676c384e04b.xml
module my_D_FF
(
	input d,
	input clk,
	input rst,
	output q
);
reg int_q;

assign q = int_q;

always @(posedge clk or negedge rst)
	if (~rst)
	begin
		int_q = 1'b0;
	end
	else
	begin
		int_q = d;
	end

endmodule
module my_D_FF
(
	input d,
	input clk,
	input rst,
	output q
);

reg int_q;

assign q = int_q;

always @(posedge clk or negedge rst)
	if (~rst)
	begin
		int_q = 1'b0;
	end
	else
	begin
		int_q = d;
	end

endmodule