data/full_repos/permissive/412289941/HDB3.v
1: b"%Error: data/full_repos/permissive/412289941/HDB3.v:21: Cannot find file containing module: 'even256_div'\neven256_div div256(clk,rst,clk_256);\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/412289941,data/full_repos/permissive/412289941/even256_div\n             data/full_repos/permissive/412289941,data/full_repos/permissive/412289941/even256_div.v\n             data/full_repos/permissive/412289941,data/full_repos/permissive/412289941/even256_div.sv\n             even256_div\n             even256_div.v\n             even256_div.sv\n             obj_dir/even256_div\n             obj_dir/even256_div.v\n             obj_dir/even256_div.sv\n%Error: data/full_repos/permissive/412289941/HDB3.v:22: Cannot find file containing module: 'even16_div'\neven16_div div16(clk_256,rst,clk_16);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/412289941/HDB3.v:24: Cannot find file containing module: 'm_sequence'\nm_sequence m(clk_16,rst,ena,outm,load);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/412289941/HDB3.v:26: Cannot find file containing module: 'add_v'\nadd_v u1(rst,outm,outv,clk_16);\n^~~~~\n%Error: data/full_repos/permissive/412289941/HDB3.v:27: Cannot find file containing module: 'add_b'\nadd_b u2(rst,outv,outb,clk_16);\n^~~~~\n%Error: data/full_repos/permissive/412289941/HDB3.v:28: Cannot find file containing module: 'polar'\npolar u3(rst,outb,outP,outN,clk_16);\n^~~~~\n%Error: data/full_repos/permissive/412289941/HDB3.v:29: Cannot find file containing module: 'change'\nchange u4(rst,outP,outN,data_out,clk_16);\n^~~~~~\n%Error: data/full_repos/permissive/412289941/HDB3.v:31: Cannot find file containing module: 'recover'\nrecover u8(clk_256, rst, data_out_ad, clk_recover);\n^~~~~~~\n%Error: data/full_repos/permissive/412289941/HDB3.v:33: Cannot find file containing module: 'trans8to1'\ntrans8to1 u5(rst, data_out_ad, outdata_P, outdata_N,clk_recover);\n^~~~~~~~~\n%Error: data/full_repos/permissive/412289941/HDB3.v:34: Cannot find file containing module: 'findv'\nfindv u6(rst, outdata_P, outdata_N, outdata_v,clk_recover);\n^~~~~\n%Error: data/full_repos/permissive/412289941/HDB3.v:35: Cannot find file containing module: 'delvb'\ndelvb u7(rst, outdata_v, finallyout,clk_recover);\n^~~~~\n%Error: Exiting due to 11 error(s)\n"
module HDB3(rst,
                clk,clk_256,clk_16,clk_recover,clk_256_ad,clk_256_da,
                ena,
                data_out,data_out_ad,outm,outv,outb,outP,outN,data_out_check,
                finallyout,outdata_P,outdata_N,outdata_v
                );


input  rst,clk,ena;
input [7:0]data_out_ad;
output clk_256,clk_16,clk_recover,clk_256_ad,clk_256_da;
output [7:0]data_out_check;
output [7:0]data_out;
output [1:0]outv;
output [1:0]outb;
output outm,outP,outN;
output outdata_P,outdata_N;
output [1:0]outdata_v;
output finallyout;

even256_div div256(clk,rst,clk_256);
even16_div div16(clk_256,rst,clk_16);

m_sequence m(clk_16,rst,ena,outm,load);

add_v u1(rst,outm,outv,clk_16);
add_b u2(rst,outv,outb,clk_16);
polar u3(rst,outb,outP,outN,clk_16);
change u4(rst,outP,outN,data_out,clk_16);

recover u8(clk_256, rst, data_out_ad, clk_recover);

trans8to1 u5(rst, data_out_ad, outdata_P, outdata_N,clk_recover);
findv u6(rst, outdata_P, outdata_N, outdata_v,clk_recover);
delvb u7(rst, outdata_v, finallyout,clk_recover);

assign clk_256_ad = clk_256;
assign clk_256_da = clk_256;
assign data_out_check = data_out_ad;

endmodule
module HDB3(rst,
                clk,clk_256,clk_16,clk_recover,clk_256_ad,clk_256_da,
                ena,
                data_out,data_out_ad,outm,outv,outb,outP,outN,data_out_check,
                finallyout,outdata_P,outdata_N,outdata_v
                );



input  rst,clk,ena;
input [7:0]data_out_ad;
output clk_256,clk_16,clk_recover,clk_256_ad,clk_256_da;
output [7:0]data_out_check;
output [7:0]data_out;
output [1:0]outv;
output [1:0]outb;
output outm,outP,outN;
output outdata_P,outdata_N;
output [1:0]outdata_v;
output finallyout;

even256_div div256(clk,rst,clk_256);
even16_div div16(clk_256,rst,clk_16);

m_sequence m(clk_16,rst,ena,outm,load);

add_v u1(rst,outm,outv,clk_16);
add_b u2(rst,outv,outb,clk_16);
polar u3(rst,outb,outP,outN,clk_16);
change u4(rst,outP,outN,data_out,clk_16);

recover u8(clk_256, rst, data_out_ad, clk_recover);

trans8to1 u5(rst, data_out_ad, outdata_P, outdata_N,clk_recover);
findv u6(rst, outdata_P, outdata_N, outdata_v,clk_recover);
delvb u7(rst, outdata_v, finallyout,clk_recover);

assign clk_256_ad = clk_256;
assign clk_256_da = clk_256;
assign data_out_check = data_out_ad;

endmodule