data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/DoG.v
1: b'%Error: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/DoG.v:90: Cannot find file containing module: \'block11x11\'\n block11x11 blk1(\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift,data/full_repos/permissive/507203156/block11x11\n             data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift,data/full_repos/permissive/507203156/block11x11.v\n             data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift,data/full_repos/permissive/507203156/block11x11.sv\n             block11x11\n             block11x11.v\n             block11x11.sv\n             obj_dir/block11x11\n             obj_dir/block11x11.v\n             obj_dir/block11x11.sv\n%Error: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/DoG.v:97: Cannot find file containing module: \'block11x11_2\'\n    block11x11_2 blk2(\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/DoG.v:117: Cannot find file containing module: \'CONV\'\n CONV gf0(.clk(clk), .clk_90(clk_90), .rst(start_flag), .din1(data[0]), .din2(data[1]),\n ^~~~\n%Error: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/DoG.v:126: Cannot find file containing module: \'CONV\'\n CONV gf1(.clk(clk), .clk_90(clk_90), .rst(start_flag), .din1(data[0]), .din2(data[1]),\n ^~~~\n%Error: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/DoG.v:135: Cannot find file containing module: \'CONV\'\n CONV gf2(.clk(clk), .clk_90(clk_90), .rst(start_flag), .din1(data[0]), .din2(data[1]),\n ^~~~\n%Error: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/DoG.v:144: Cannot find file containing module: \'CONV\'\n CONV gf3(.clk(clk), .clk_90(clk_90), .rst(start_flag), .din1(data[0]), .din2(data[1]),\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/DoG.v:153: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 18 bits.\n                                                                                           : ... In instance DoG\n assign diff0=(dout2-dout1)>>10;\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/DoG.v:154: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 18 bits.\n                                                                                           : ... In instance DoG\n assign diff1=(dout3-dout2)>>10;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/DoG.v:155: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 18 bits.\n                                                                                           : ... In instance DoG\n assign diff2=(dout4-dout3)>>10;\n             ^\n%Error: Exiting due to 6 error(s), 3 warning(s)\n'
module DoG(
		input clk,
		input clk_90,
		input rst,
		input [7:0] din,
		output [17:0] dout1,
		output [17:0] dout2,
		output [17:0] dout3,
		output [17:0] dout4,
		output signed [7:0] diff0,
		output signed [7:0] diff1,
		output signed [7:0] diff2,
		output out_en,
		output [20:0] addr,
		output complete1,
		output complete2
    );
	
	wire start_flag;
	wire [87:0] data[10:0];
	
	wire [87:0] data1[10:0];
	wire [87:0] data2[10:0];


	 parameter zero = 88'h00_00_00_00_00_00_00_00_00_00_00;


	 parameter gf3_1= 48'h00_00_01_01_02_02;
	 parameter gf3_2= 48'h00_01_02_03_05_06;
	 parameter gf3_3= 48'h01_02_04_08_0c_0d;
	 parameter gf3_4= 48'h01_03_08_0f_16_19;
	 parameter gf3_5= 48'h02_05_0c_16_20_24;
	 parameter gf3_6= 48'h02_06_0d_19_24_29;

	 parameter gf2_2= 48'h00_00_00_01_02_03;
	 parameter gf2_3= 48'h00_00_02_05_09_0b;
	 parameter gf2_4= 48'h00_01_05_0d_18_1d;
	 parameter gf2_5= 48'h00_02_09_18_2b_34;
	 parameter gf2_6= 48'h00_03_0b_1d_34_40;

	 parameter gf1_2= 48'h00_00_00_00_01_01;
	 parameter gf1_3= 48'h00_00_00_02_05_07;
	 parameter gf1_4= 48'h00_00_02_09_16_1e;
	 parameter gf1_5= 48'h00_01_05_16_35_48;
	 parameter gf1_6= 48'h00_01_07_1e_48_60;

	 parameter gf0_3= 48'h00_00_00_01_02_03;
	 parameter gf0_4= 48'h00_00_01_05_11_1a;
	 parameter gf0_5= 48'h00_00_02_11_3b_59;
	 parameter gf0_6= 48'h00_00_03_1a_59_87;

	 
	 

	 wire [20:0] addr1;
	 wire [20:0] addr2;
	 
	 wire start_flag1;
	 wire start_flag2;
	 
	 
	 assign addr = complete1 ? addr2 : addr1;
	 assign start_flag = complete1 ? start_flag2 : start_flag1;


	block11x11 blk1(
			.clk(clk), .rst(rst), .din(din), .dout1(data1[0]), .dout2(data1[1]), .dout3(data1[2]),
			.dout4(data1[3]), .dout5(data1[4]), .dout6(data1[5]), .dout7(data1[6]), 
			.dout8(data1[7]), .dout9(data1[8]), .dout10(data1[9]), .dout11(data1[10]), 
			.start_flag(start_flag1) ,.cnt(addr1), .complete(complete1)
			);
						 
   	block11x11_2 blk2(
		   .clk(clk), .rst(complete1), .din(din), .dout1(data2[0]), .dout2(data2[1]), .dout3(data2[2]),	
		   .dout4(data2[3]), .dout5(data2[4]), .dout6(data2[5]), .dout7(data2[6]), 
           .dout8(data2[7]), .dout9(data2[8]), .dout10(data2[9]), .dout11(data2[10]), 
		   .start_flag(start_flag2) ,.cnt(addr2) ,.complete(complete2)
		   );

	assign data[0]=complete1?data2[0]:data1[0];
	assign data[1]=complete1?data2[1]:data1[1];
	assign data[2]=complete1?data2[2]:data1[2];
	assign data[3]=complete1?data2[3]:data1[3];
	assign data[4]=complete1?data2[4]:data1[4];
	assign data[5]=complete1?data2[5]:data1[5];
	assign data[6]=complete1?data2[6]:data1[6];
	assign data[7]=complete1?data2[7]:data1[7];
	assign data[8]=complete1?data2[8]:data1[8];
	assign data[9]=complete1?data2[9]:data1[9];
	assign data[10]=complete1?data2[10]:data1[10];
	

	CONV gf0(.clk(clk), .clk_90(clk_90), .rst(start_flag), .din1(data[0]), .din2(data[1]),
								 .din3(data[2]),.din4(data[3]), .din5(data[4]), .din6(data[5]), .din7(data[6]),
								 .din8(data[7]),.din9(data[8]), .din10(data[9]), .din11(data[10]),
								 .df1_1(zero), .df1_2(zero),
								 .df1_3(gf0_3), .df1_4(gf0_4), .df1_5(gf0_5), .df1_6(gf0_6), 
								 .df1_7(gf0_5), .df1_8(gf0_4), .df1_9(gf0_3),
								 .df1_10(zero), .df1_11(zero), 
								 .dout(dout1));
								 
	CONV gf1(.clk(clk), .clk_90(clk_90), .rst(start_flag), .din1(data[0]), .din2(data[1]),
								 .din3(data[2]),.din4(data[3]), .din5(data[4]), .din6(data[5]), .din7(data[6]),
								 .din8(data[7]),.din9(data[8]), .din10(data[9]), .din11(data[10]),
								 .df1_1(zero), 
								 .df1_2(gf1_2),.df1_3(gf1_3), .df1_4(gf1_4), .df1_5(gf1_5), .df1_6(gf1_6),
								 .df1_7(gf1_5),.df1_8(gf1_4), .df1_9(gf1_3), .df1_10(gf1_2),
								 .df1_11(zero),
								 .dout(dout2),.out_en(out_en));
								 
	CONV gf2(.clk(clk), .clk_90(clk_90), .rst(start_flag), .din1(data[0]), .din2(data[1]),
								 .din3(data[2]),.din4(data[3]), .din5(data[4]), .din6(data[5]), .din7(data[6]),
								 .din8(data[7]),.din9(data[8]), .din10(data[9]), .din11(data[10]),
								 .df1_1(zero),
								 .df1_2(gf2_2),.df1_3(gf2_3), .df1_4(gf2_4), .df1_5(gf2_5), .df1_6(gf2_6),
								 .df1_7(gf2_5),.df1_8(gf2_4), .df1_9(gf2_3), .df1_10(gf2_2),
								 .df1_11(zero),
								 .dout(dout3));
								 
	CONV gf3(.clk(clk), .clk_90(clk_90), .rst(start_flag), .din1(data[0]), .din2(data[1]),
								 .din3(data[2]),.din4(data[3]), .din5(data[4]), .din6(data[5]), .din7(data[6]),
								 .din8(data[7]),.din9(data[8]), .din10(data[9]), .din11(data[10]),
								 .df1_1(gf3_1),
								 .df1_2(gf3_2),.df1_3(gf3_3), .df1_4(gf3_4), .df1_5(gf3_5), .df1_6(gf3_6),
								 .df1_7(gf3_5),.df1_8(gf3_4), .df1_9(gf3_3), .df1_10(gf3_2),
								 .df1_11(gf3_1),
								 .dout(dout4));

	assign diff0=(dout2-dout1)>>10;
	assign diff1=(dout3-dout2)>>10;
	assign diff2=(dout4-dout3)>>10;
	
endmodule
module DoG(
		input clk,
		input clk_90,
		input rst,
		input [7:0] din,
		output [17:0] dout1,
		output [17:0] dout2,
		output [17:0] dout3,
		output [17:0] dout4,
		output signed [7:0] diff0,
		output signed [7:0] diff1,
		output signed [7:0] diff2,
		output out_en,
		output [20:0] addr,
		output complete1,
		output complete2
    );

	
	wire start_flag;
	wire [87:0] data[10:0];
	
	wire [87:0] data1[10:0];
	wire [87:0] data2[10:0];


	 parameter zero = 88'h00_00_00_00_00_00_00_00_00_00_00;


	 parameter gf3_1= 48'h00_00_01_01_02_02;
	 parameter gf3_2= 48'h00_01_02_03_05_06;
	 parameter gf3_3= 48'h01_02_04_08_0c_0d;
	 parameter gf3_4= 48'h01_03_08_0f_16_19;
	 parameter gf3_5= 48'h02_05_0c_16_20_24;
	 parameter gf3_6= 48'h02_06_0d_19_24_29;

	 parameter gf2_2= 48'h00_00_00_01_02_03;
	 parameter gf2_3= 48'h00_00_02_05_09_0b;
	 parameter gf2_4= 48'h00_01_05_0d_18_1d;
	 parameter gf2_5= 48'h00_02_09_18_2b_34;
	 parameter gf2_6= 48'h00_03_0b_1d_34_40;

	 parameter gf1_2= 48'h00_00_00_00_01_01;
	 parameter gf1_3= 48'h00_00_00_02_05_07;
	 parameter gf1_4= 48'h00_00_02_09_16_1e;
	 parameter gf1_5= 48'h00_01_05_16_35_48;
	 parameter gf1_6= 48'h00_01_07_1e_48_60;

	 parameter gf0_3= 48'h00_00_00_01_02_03;
	 parameter gf0_4= 48'h00_00_01_05_11_1a;
	 parameter gf0_5= 48'h00_00_02_11_3b_59;
	 parameter gf0_6= 48'h00_00_03_1a_59_87;

	 
	 

	 wire [20:0] addr1;
	 wire [20:0] addr2;
	 
	 wire start_flag1;
	 wire start_flag2;
	 
	 
	 assign addr = complete1 ? addr2 : addr1;
	 assign start_flag = complete1 ? start_flag2 : start_flag1;


	block11x11 blk1(
			.clk(clk), .rst(rst), .din(din), .dout1(data1[0]), .dout2(data1[1]), .dout3(data1[2]),
			.dout4(data1[3]), .dout5(data1[4]), .dout6(data1[5]), .dout7(data1[6]), 
			.dout8(data1[7]), .dout9(data1[8]), .dout10(data1[9]), .dout11(data1[10]), 
			.start_flag(start_flag1) ,.cnt(addr1), .complete(complete1)
			);
						 
   	block11x11_2 blk2(
		   .clk(clk), .rst(complete1), .din(din), .dout1(data2[0]), .dout2(data2[1]), .dout3(data2[2]),	
		   .dout4(data2[3]), .dout5(data2[4]), .dout6(data2[5]), .dout7(data2[6]), 
           .dout8(data2[7]), .dout9(data2[8]), .dout10(data2[9]), .dout11(data2[10]), 
		   .start_flag(start_flag2) ,.cnt(addr2) ,.complete(complete2)
		   );

	assign data[0]=complete1?data2[0]:data1[0];
	assign data[1]=complete1?data2[1]:data1[1];
	assign data[2]=complete1?data2[2]:data1[2];
	assign data[3]=complete1?data2[3]:data1[3];
	assign data[4]=complete1?data2[4]:data1[4];
	assign data[5]=complete1?data2[5]:data1[5];
	assign data[6]=complete1?data2[6]:data1[6];
	assign data[7]=complete1?data2[7]:data1[7];
	assign data[8]=complete1?data2[8]:data1[8];
	assign data[9]=complete1?data2[9]:data1[9];
	assign data[10]=complete1?data2[10]:data1[10];
	

	CONV gf0(.clk(clk), .clk_90(clk_90), .rst(start_flag), .din1(data[0]), .din2(data[1]),
								 .din3(data[2]),.din4(data[3]), .din5(data[4]), .din6(data[5]), .din7(data[6]),
								 .din8(data[7]),.din9(data[8]), .din10(data[9]), .din11(data[10]),
								 .df1_1(zero), .df1_2(zero),
								 .df1_3(gf0_3), .df1_4(gf0_4), .df1_5(gf0_5), .df1_6(gf0_6), 
								 .df1_7(gf0_5), .df1_8(gf0_4), .df1_9(gf0_3),
								 .df1_10(zero), .df1_11(zero), 
								 .dout(dout1));
								 
	CONV gf1(.clk(clk), .clk_90(clk_90), .rst(start_flag), .din1(data[0]), .din2(data[1]),
								 .din3(data[2]),.din4(data[3]), .din5(data[4]), .din6(data[5]), .din7(data[6]),
								 .din8(data[7]),.din9(data[8]), .din10(data[9]), .din11(data[10]),
								 .df1_1(zero), 
								 .df1_2(gf1_2),.df1_3(gf1_3), .df1_4(gf1_4), .df1_5(gf1_5), .df1_6(gf1_6),
								 .df1_7(gf1_5),.df1_8(gf1_4), .df1_9(gf1_3), .df1_10(gf1_2),
								 .df1_11(zero),
								 .dout(dout2),.out_en(out_en));
								 
	CONV gf2(.clk(clk), .clk_90(clk_90), .rst(start_flag), .din1(data[0]), .din2(data[1]),
								 .din3(data[2]),.din4(data[3]), .din5(data[4]), .din6(data[5]), .din7(data[6]),
								 .din8(data[7]),.din9(data[8]), .din10(data[9]), .din11(data[10]),
								 .df1_1(zero),
								 .df1_2(gf2_2),.df1_3(gf2_3), .df1_4(gf2_4), .df1_5(gf2_5), .df1_6(gf2_6),
								 .df1_7(gf2_5),.df1_8(gf2_4), .df1_9(gf2_3), .df1_10(gf2_2),
								 .df1_11(zero),
								 .dout(dout3));
								 
	CONV gf3(.clk(clk), .clk_90(clk_90), .rst(start_flag), .din1(data[0]), .din2(data[1]),
								 .din3(data[2]),.din4(data[3]), .din5(data[4]), .din6(data[5]), .din7(data[6]),
								 .din8(data[7]),.din9(data[8]), .din10(data[9]), .din11(data[10]),
								 .df1_1(gf3_1),
								 .df1_2(gf3_2),.df1_3(gf3_3), .df1_4(gf3_4), .df1_5(gf3_5), .df1_6(gf3_6),
								 .df1_7(gf3_5),.df1_8(gf3_4), .df1_9(gf3_3), .df1_10(gf3_2),
								 .df1_11(gf3_1),
								 .dout(dout4));

	assign diff0=(dout2-dout1)>>10;
	assign diff1=(dout3-dout2)>>10;
	assign diff2=(dout4-dout3)>>10;
	
endmodule