data/full_repos/permissive/437654144/width_convert/width_conv.v
1: b"%Error: data/full_repos/permissive/437654144/width_convert/width_conv.v:99: Cannot find file containing module: 'up_width_conv'\n                up_width_conv #\n                ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/437654144/width_convert,data/full_repos/permissive/437654144/up_width_conv\n             data/full_repos/permissive/437654144/width_convert,data/full_repos/permissive/437654144/up_width_conv.v\n             data/full_repos/permissive/437654144/width_convert,data/full_repos/permissive/437654144/up_width_conv.sv\n             up_width_conv\n             up_width_conv.v\n             up_width_conv.sv\n             obj_dir/up_width_conv\n             obj_dir/up_width_conv.v\n             obj_dir/up_width_conv.sv\n%Error: Exiting due to 1 error(s)\n"
module width_conv #
(
    parameter DIN_WIDTH  = 8,
    parameter DOUT_WIDTH = 32
)
(
    input   wire                            clk,
    input   wire                            cen,
    input   wire                            rstn,
    
    input   wire    [DIN_WIDTH - 1:0]       din,
    input   wire    [DIN_WIDTH/8 - 1:0]     din_strb,
    input   wire                            din_last,
    input   wire                            din_valid,
    output  wire                            din_ready,
    
    output  wire    [DOUT_WIDTH - 1:0]      dout,
    output  wire    [DOUT_WIDTH/8 - 1:0]    dout_strb,
    output  wire                            dout_last,
    output  wire                            dout_valid,
    input   wire                            dout_ready
);



    generate
        if ((DIN_WIDTH  < 1)                                              ||
            (DOUT_WIDTH < 1)                                              ||
            ((DOUT_WIDTH % 8) != 0)                                       ||
            ((DIN_WIDTH % 8)  != 0)                                       ||
            ((DIN_WIDTH > DOUT_WIDTH) && ((DIN_WIDTH % DOUT_WIDTH) != 0)) ||
            ((DIN_WIDTH < DOUT_WIDTH) && ((DOUT_WIDTH % DIN_WIDTH) != 0))) begin

            INVALID_PARAMETER invalid_parameters_msg();
        end
    endgenerate



    generate
        if (DIN_WIDTH == DOUT_WIDTH) begin
            assign dout       = din;
            assign dout_strb  = din_strb;
            assign dout_last  = din_last;
            assign dout_valid = din_valid;
            assign din_ready  = dout_ready;
        end else begin
            if (DIN_WIDTH > DOUT_WIDTH) begin
                
                down_width_conv #
                (
                    .DIN_WIDTH  ( DIN_WIDTH  ),
                    .DOUT_WIDTH ( DOUT_WIDTH )
                )
                down_width_conv_inst
                (
                    .clk        ( clk        ),
                    .cen        ( cen        ),
                    .rstn       ( rstn       ),
                    
                    .din        ( din        ),
                    .din_strb   ( din_strb   ),
                    .din_last   ( din_last   ),
                    .din_valid  ( din_valid  ),
                    .din_ready  ( din_ready  ),
                    
                    .dout       ( dout       ),
                    .dout_strb  ( dout_strb  ),
                    .dout_last  ( dout_last  ),
                    .dout_valid ( dout_valid ),
                    .dout_ready ( dout_ready )
                );
                
            end else begin
            
                up_width_conv #
                (
                    .DIN_WIDTH  ( DIN_WIDTH  ),
                    .DOUT_WIDTH ( DOUT_WIDTH )
                )
                up_width_conv_inst
                (
                    .clk        ( clk        ),
                    .cen        ( cen        ),
                    .rstn       ( rstn       ),
                    
                    .din        ( din        ),
                    .din_strb   ( din_strb   ),
                    .din_last   ( din_last   ),
                    .din_valid  ( din_valid  ),
                    .din_ready  ( din_ready  ),
                    
                    .dout       ( dout       ),
                    .dout_strb  ( dout_strb  ),
                    .dout_last  ( dout_last  ),
                    .dout_valid ( dout_valid ),
                    .dout_ready ( dout_ready )
                );
                
            end
        end
    endgenerate
    

    
endmodule
module width_conv #
(
    parameter DIN_WIDTH  = 8,
    parameter DOUT_WIDTH = 32
)
(
    input   wire                            clk,
    input   wire                            cen,
    input   wire                            rstn,
    
    input   wire    [DIN_WIDTH - 1:0]       din,
    input   wire    [DIN_WIDTH/8 - 1:0]     din_strb,
    input   wire                            din_last,
    input   wire                            din_valid,
    output  wire                            din_ready,
    
    output  wire    [DOUT_WIDTH - 1:0]      dout,
    output  wire    [DOUT_WIDTH/8 - 1:0]    dout_strb,
    output  wire                            dout_last,
    output  wire                            dout_valid,
    input   wire                            dout_ready
);




    generate
        if ((DIN_WIDTH  < 1)                                              ||
            (DOUT_WIDTH < 1)                                              ||
            ((DOUT_WIDTH % 8) != 0)                                       ||
            ((DIN_WIDTH % 8)  != 0)                                       ||
            ((DIN_WIDTH > DOUT_WIDTH) && ((DIN_WIDTH % DOUT_WIDTH) != 0)) ||
            ((DIN_WIDTH < DOUT_WIDTH) && ((DOUT_WIDTH % DIN_WIDTH) != 0))) begin

            INVALID_PARAMETER invalid_parameters_msg();
        end
    endgenerate



    generate
        if (DIN_WIDTH == DOUT_WIDTH) begin
            assign dout       = din;
            assign dout_strb  = din_strb;
            assign dout_last  = din_last;
            assign dout_valid = din_valid;
            assign din_ready  = dout_ready;
        end else begin
            if (DIN_WIDTH > DOUT_WIDTH) begin
                
                down_width_conv #
                (
                    .DIN_WIDTH  ( DIN_WIDTH  ),
                    .DOUT_WIDTH ( DOUT_WIDTH )
                )
                down_width_conv_inst
                (
                    .clk        ( clk        ),
                    .cen        ( cen        ),
                    .rstn       ( rstn       ),
                    
                    .din        ( din        ),
                    .din_strb   ( din_strb   ),
                    .din_last   ( din_last   ),
                    .din_valid  ( din_valid  ),
                    .din_ready  ( din_ready  ),
                    
                    .dout       ( dout       ),
                    .dout_strb  ( dout_strb  ),
                    .dout_last  ( dout_last  ),
                    .dout_valid ( dout_valid ),
                    .dout_ready ( dout_ready )
                );
                
            end else begin
            
                up_width_conv #
                (
                    .DIN_WIDTH  ( DIN_WIDTH  ),
                    .DOUT_WIDTH ( DOUT_WIDTH )
                )
                up_width_conv_inst
                (
                    .clk        ( clk        ),
                    .cen        ( cen        ),
                    .rstn       ( rstn       ),
                    
                    .din        ( din        ),
                    .din_strb   ( din_strb   ),
                    .din_last   ( din_last   ),
                    .din_valid  ( din_valid  ),
                    .din_ready  ( din_ready  ),
                    
                    .dout       ( dout       ),
                    .dout_strb  ( dout_strb  ),
                    .dout_last  ( dout_last  ),
                    .dout_valid ( dout_valid ),
                    .dout_ready ( dout_ready )
                );
                
            end
        end
    endgenerate
    

    
endmodule