data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh
1: b'%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:26: Cannot find include file: ltlib_v1_0_0_ver.vh\n`include "ltlib_v1_0_0_ver.vh" \n         ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog,data/full_repos/permissive/487568919/ltlib_v1_0_0_ver.vh\n             data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog,data/full_repos/permissive/487568919/ltlib_v1_0_0_ver.vh.v\n             data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog,data/full_repos/permissive/487568919/ltlib_v1_0_0_ver.vh.sv\n             ltlib_v1_0_0_ver.vh\n             ltlib_v1_0_0_ver.vh.v\n             ltlib_v1_0_0_ver.vh.sv\n             obj_dir/ltlib_v1_0_0_ver.vh\n             obj_dir/ltlib_v1_0_0_ver.vh.v\n             obj_dir/ltlib_v1_0_0_ver.vh.sv\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:44: Define or directive not defined: \'`FAMILY_NAME_LENGTH\'\n    input [`FAMILY_NAME_LENGTH*8-1:0] familyName;\n           ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:44: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n    input [`FAMILY_NAME_LENGTH*8-1:0] familyName;\n                              ^\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:45: Define or directive not defined: \'`FAMILY_NAME_LENGTH\'\n    input [`FAMILY_NAME_LENGTH*8-1:0] expectedName;\n           ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:53: Define or directive not defined: \'`FAMILY_NAME_LENGTH\'\n      for (i=0; i<`FAMILY_NAME_LENGTH; i=i+1)\n                  ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:53: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      for (i=0; i<`FAMILY_NAME_LENGTH; i=i+1)\n                                     ^\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:53: syntax error, unexpected \')\', expecting \';\'\n      for (i=0; i<`FAMILY_NAME_LENGTH; i=i+1)\n                                            ^\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:66: syntax error, unexpected end\n      end\n      ^~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:70: Define or directive not defined: \'`FAMILY_NAME_LENGTH\'\n        i = `FAMILY_NAME_LENGTH;\n            ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:70: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        i = `FAMILY_NAME_LENGTH;\n                               ^\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:76: Define or directive not defined: \'`FAMILY_NAME_LENGTH\'\n    input [`FAMILY_NAME_LENGTH-1:0] familyName;\n           ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:78: Define or directive not defined: \'`FAMILY_VIRTEX7\'\n      if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)\n                                     ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:78: Define or directive not defined: \'`FAMILY_VIRTEX7_LENGTH\'\n      if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)\n                                                     ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:78: Define or directive not defined: \'`FAMILY_KINTEX7\'\n      if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)\n                                                                                                                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:78: Define or directive not defined: \'`FAMILY_KINTEX7_LENGTH\'\n      if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)\n                                                                                                                                ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:78: Define or directive not defined: \'`FAMILY_ARTIX7\'\n      if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)\n                                                                                                                                                                                           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:78: Define or directive not defined: \'`FAMILY_ARTIX7_LENGTH\'\n      if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)\n                                                                                                                                                                                                          ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:78: Define or directive not defined: \'`FAMILY_ZYNQ\'\n      if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)\n                                                                                                                                                                                                                                                                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:78: Define or directive not defined: \'`FAMILY_ZYNQ_LENGTH\'\n      if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)\n                                                                                                                                                                                                                                                                                 ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:86: Define or directive not defined: \'`FAMILY_NAME_LENGTH\'\n    input [`FAMILY_NAME_LENGTH-1:0] familyName;\n           ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:88: Define or directive not defined: \'`FAMILY_VIRTEX7\'\n      if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)\n                                     ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:88: Define or directive not defined: \'`FAMILY_VIRTEX7_LENGTH\'\n      if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)\n                                                     ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:88: Define or directive not defined: \'`FAMILY_KINTEX7\'\n      if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)\n                                                                                                                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:88: Define or directive not defined: \'`FAMILY_KINTEX7_LENGTH\'\n      if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)\n                                                                                                                                ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:88: Define or directive not defined: \'`FAMILY_ARTIX7\'\n      if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)\n                                                                                                                                                                                           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:88: Define or directive not defined: \'`FAMILY_ARTIX7_LENGTH\'\n      if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)\n                                                                                                                                                                                                          ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:88: Define or directive not defined: \'`FAMILY_ZYNQ\'\n      if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)\n                                                                                                                                                                                                                                                                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:88: Define or directive not defined: \'`FAMILY_ZYNQ_LENGTH\'\n      if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)\n                                                                                                                                                                                                                                                                                 ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:96: Define or directive not defined: \'`FAMILY_NAME_LENGTH\'\n    input [`FAMILY_NAME_LENGTH-1:0] familyName;\n           ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:98: Define or directive not defined: \'`FAMILY_VIRTEX7\'\n      if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)\n                                     ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:98: Define or directive not defined: \'`FAMILY_VIRTEX7_LENGTH\'\n      if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)\n                                                     ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:98: Define or directive not defined: \'`FAMILY_KINTEX7\'\n      if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)\n                                                                                                                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:98: Define or directive not defined: \'`FAMILY_KINTEX7_LENGTH\'\n      if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)\n                                                                                                                                ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:98: Define or directive not defined: \'`FAMILY_ARTIX7\'\n      if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)\n                                                                                                                                                                                           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:98: Define or directive not defined: \'`FAMILY_ARTIX7_LENGTH\'\n      if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)\n                                                                                                                                                                                                          ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:98: Define or directive not defined: \'`FAMILY_ZYNQ\'\n      if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)\n                                                                                                                                                                                                                                                                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/example_projects/vivado_test_prj_template_v2/test.srcs/sources_1/ip/vio_0/hdl/verilog/ltlib_v1_0_0_lib_fn.vh:98: Define or directive not defined: \'`FAMILY_ZYNQ_LENGTH\'\n      if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)\n                                                                                                                                                                                                                                                                                 ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 37 error(s)\n'
function integer supports_series7_startup;
    input [`FAMILY_NAME_LENGTH-1:0] familyName;
    begin
      if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)
        supports_series7_startup = 1;
      else
        supports_series7_startup = 0;
    end
  endfunction
function integer supports_series7_startup;

    input [`FAMILY_NAME_LENGTH-1:0] familyName;
    begin
      if (string_contains(familyName,`FAMILY_VIRTEX7,`FAMILY_VIRTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_KINTEX7,`FAMILY_KINTEX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ARTIX7,`FAMILY_ARTIX7_LENGTH) == 1 || string_contains(familyName,`FAMILY_ZYNQ,`FAMILY_ZYNQ_LENGTH) == 1)
        supports_series7_startup = 1;
      else
        supports_series7_startup = 0;
    end
  endfunction