data/full_repos/permissive/450072296/verilog/rtl/stud_d_flip_flop.v
data/verilator_xmls/b896f7e2-e8e3-485f-8f92-98b96cda4117.xml
module stud_d_flip_flop (input clk_i, rst_n_i, data_i, 
					output reg output_o);
	always @(posedge clk_i) begin
		if(~rst_n_i) begin
			output_o <= 1'b0;
		end else begin
			output_o <= data_i;
		end
	end
endmodule
module stud_d_flip_flop (input clk_i, rst_n_i, data_i, 
					output reg output_o);

	always @(posedge clk_i) begin
		if(~rst_n_i) begin
			output_o <= 1'b0;
		end else begin
			output_o <= data_i;
		end
	end
endmodule