data/full_repos/permissive/515598112/3_Circuits/01_Combinational_Logic/01_Basic_Gates/03_NOR.v
data/verilator_xmls/7b132949-b441-4a90-b017-3fe7fe84f4f1.xml
module top_module (
    input in1,
    input in2,
    output out
);
    
    assign out = ~(in1 | in2);

endmodule
module top_module (
    input in1,
    input in2,
    output out
);

    
    assign out = ~(in1 | in2);

endmodule