data/full_repos/permissive/485085993/verilog/rtl/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v:20: Little bit endian vector: MSB < LSB of bit range: 0:3\ninput [0:3] lut4_in;\n      ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v:22: Little bit endian vector: MSB < LSB of bit range: 0:15\ninput [0:15] bl;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v:24: Little bit endian vector: MSB < LSB of bit range: 0:15\ninput [0:15] wl;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v:38: Little bit endian vector: MSB < LSB of bit range: 0:15\nwire [0:15] lut4_0_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v:39: Little bit endian vector: MSB < LSB of bit range: 0:15\nwire [0:15] lut4_0_sram_inv;\n     ^\n%Error: data/full_repos/permissive/485085993/verilog/rtl/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v:46: Cannot find file containing module: \'lut4\'\n lut4 lut4_0_ (\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/lut4\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/lut4.v\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/lut4.sv\n             lut4\n             lut4.v\n             lut4.sv\n             obj_dir/lut4\n             obj_dir/lut4.v\n             obj_dir/lut4.sv\n%Error: data/full_repos/permissive/485085993/verilog/rtl/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v:52: Cannot find file containing module: \'lut4_SRAM_mem\'\n lut4_SRAM_mem lut4_SRAM_mem (\n ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 5 warning(s)\n'
module logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4(lut4_in,
                                                                                bl,
                                                                                wl,
                                                                                lut4_out);

input [0:3] lut4_in;

input [0:15] bl;

input [0:15] wl;

output [0:0] lut4_out;


wire [0:3] lut4_in;
wire [0:0] lut4_out;







wire [0:15] lut4_0_sram;
wire [0:15] lut4_0_sram_inv;






	lut4 lut4_0_ (
		.in(lut4_in[0:3]),
		.sram(lut4_0_sram[0:15]),
		.sram_inv(lut4_0_sram_inv[0:15]),
		.out(lut4_out));

	lut4_SRAM_mem lut4_SRAM_mem (
		.bl(bl[0:15]),
		.wl(wl[0:15]),
		.mem_out(lut4_0_sram[0:15]),
		.mem_outb(lut4_0_sram_inv[0:15]));

endmodule
module logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4(lut4_in,
                                                                                bl,
                                                                                wl,
                                                                                lut4_out);


input [0:3] lut4_in;

input [0:15] bl;

input [0:15] wl;

output [0:0] lut4_out;


wire [0:3] lut4_in;
wire [0:0] lut4_out;







wire [0:15] lut4_0_sram;
wire [0:15] lut4_0_sram_inv;






	lut4 lut4_0_ (
		.in(lut4_in[0:3]),
		.sram(lut4_0_sram[0:15]),
		.sram_inv(lut4_0_sram_inv[0:15]),
		.out(lut4_out));

	lut4_SRAM_mem lut4_SRAM_mem (
		.bl(bl[0:15]),
		.wl(wl[0:15]),
		.mem_out(lut4_0_sram[0:15]),
		.mem_outb(lut4_0_sram_inv[0:15]));

endmodule