data/full_repos/permissive/458134463/Modules/register_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/register_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n forever #2 clock = ~clock;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/register_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n#4;\n^\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/register_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n#4;\n^\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/register_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n#4;\n^\n%Warning-STMTDLY: data/full_repos/permissive/458134463/Modules/register_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n#4;\n^\n%Error: data/full_repos/permissive/458134463/Modules/register_tb.v:46: Unsupported or unknown PLI call: $monitor\n$monitor("Time: %3d | Clock: %1b | RegWrite: %1b | Read Register 1: %3b | Read Register 2: %3b | Write Register: %3b\\nWrite Data : %32b\\nRead Data 1: %32b\\nRead Data 2: %32b", \n^~~~~~~~\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module register_tb();

reg [2:0] read_reg1;
reg [2:0] read_reg2;
reg [2:0] write_reg;
reg [31:0]write_data;
reg RegWrite, clock;

wire [31:0] read_data1;
wire [31:0] read_data2;


register r(read_reg1, read_reg2, write_reg, write_data, RegWrite, read_data1, read_data2, clock);

initial begin
	clock = 1'b0;
	forever #2 clock = ~clock;
end


initial begin

read_reg1  = 3'b001;
read_reg2  = 3'b010;

write_reg  = 3'b001;
write_data = 32'hFFFF1111;
RegWrite   = 1'b1;
#4;

RegWrite = 1'b0;
#4;

write_reg  = 3'b010;
write_data = 32'hFFFF0000;
RegWrite = 1'b1;
#4;

RegWrite = 1'b0;
#4;

end


initial begin
$monitor("Time: %3d | Clock: %1b | RegWrite: %1b | Read Register 1: %3b | Read Register 2: %3b | Write Register: %3b\nWrite Data : %32b\nRead Data 1: %32b\nRead Data 2: %32b", 
			$time, clock, RegWrite, read_reg1, read_reg2, write_reg, 
			write_data, read_data1, read_data2);
end

endmodule
module register_tb();


reg [2:0] read_reg1;
reg [2:0] read_reg2;
reg [2:0] write_reg;
reg [31:0]write_data;
reg RegWrite, clock;

wire [31:0] read_data1;
wire [31:0] read_data2;


register r(read_reg1, read_reg2, write_reg, write_data, RegWrite, read_data1, read_data2, clock);

initial begin
	clock = 1'b0;
	forever #2 clock = ~clock;
end


initial begin

read_reg1  = 3'b001;
read_reg2  = 3'b010;

write_reg  = 3'b001;
write_data = 32'hFFFF1111;
RegWrite   = 1'b1;
#4;

RegWrite = 1'b0;
#4;

write_reg  = 3'b010;
write_data = 32'hFFFF0000;
RegWrite = 1'b1;
#4;

RegWrite = 1'b0;
#4;

end


initial begin
$monitor("Time: %3d | Clock: %1b | RegWrite: %1b | Read Register 1: %3b | Read Register 2: %3b | Write Register: %3b\nWrite Data : %32b\nRead Data 1: %32b\nRead Data 2: %32b", 
			$time, clock, RegWrite, read_reg1, read_reg2, write_reg, 
			write_data, read_data1, read_data2);
end

endmodule