data/full_repos/permissive/500396778/Microprocessor-Control-Logic-using/tb_mproc_mem.v
1: b'%Error: data/full_repos/permissive/500396778/Microprocessor-Control-Logic-using/tb_mproc_mem.v:7: Unsupported or unknown PLI call: $dumpfile\n  initial begin $dumpfile("tb_mproc_mem.vcd"); $dumpvars(0,tb); end\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/500396778/Microprocessor-Control-Logic-using/tb_mproc_mem.v:7: Unsupported or unknown PLI call: $dumpvars\n  initial begin $dumpfile("tb_mproc_mem.vcd"); $dumpvars(0,tb); end\n                                               ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/500396778/Microprocessor-Control-Logic-using/tb_mproc_mem.v:8: Unsupported: Ignoring delay on this delayed statement.\n  initial begin reset = 1\'b1; #12.5 reset = 1\'b0; end\n                              ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/500396778/Microprocessor-Control-Logic-using/tb_mproc_mem.v:9: Unsupported: Ignoring delay on this delayed statement.\n  initial clk = 1\'b0; always #5 clk =~ clk;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/500396778/Microprocessor-Control-Logic-using/tb_mproc_mem.v:13: Unsupported: Ignoring delay on this delayed statement.\n      begin #10; end\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/500396778/Microprocessor-Control-Logic-using/tb_mproc_mem.v:12: Unsupported: Ignoring delay on this delayed statement.\n    #6 for(i=0;i<500;i=i+1)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/500396778/Microprocessor-Control-Logic-using/tb_mproc_mem.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #100 $finish;\n    ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;
  reg clk, reset;
  integer i;
  initial begin $dumpfile("tb_mproc_mem.vcd"); $dumpvars(0,tb); end
  initial begin reset = 1'b1; #12.5 reset = 1'b0; end
  initial clk = 1'b0; always #5 clk =~ clk;
  mproc_mem mproc_mem_0 (clk, reset);
  initial begin
    #6 for(i=0;i<`TESTVECS;i=i+1)
      begin #10; end
    #100 $finish;
  end
endmodule
module tb;

  reg clk, reset;
  integer i;
  initial begin $dumpfile("tb_mproc_mem.vcd"); $dumpvars(0,tb); end
  initial begin reset = 1'b1; #12.5 reset = 1'b0; end
  initial clk = 1'b0; always #5 clk =~ clk;
  mproc_mem mproc_mem_0 (clk, reset);
  initial begin
    #6 for(i=0;i<`TESTVECS;i=i+1)
      begin #10; end
    #100 $finish;
  end
endmodule