data/full_repos/permissive/460468583/data/yosys/anlogic/brams_map.v
1: b'%Error: data/full_repos/permissive/460468583/data/yosys/anlogic/brams_map.v:64: Cannot find include file: brams_init_9.vh\n   `include "brams_init_9.vh" \n            ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/460468583/data/yosys/anlogic,data/full_repos/permissive/460468583/brams_init_9.vh\n             data/full_repos/permissive/460468583/data/yosys/anlogic,data/full_repos/permissive/460468583/brams_init_9.vh.v\n             data/full_repos/permissive/460468583/data/yosys/anlogic,data/full_repos/permissive/460468583/brams_init_9.vh.sv\n             brams_init_9.vh\n             brams_init_9.vh.v\n             brams_init_9.vh.sv\n             obj_dir/brams_init_9.vh\n             obj_dir/brams_init_9.vh.v\n             obj_dir/brams_init_9.vh.sv\n%Error: data/full_repos/permissive/460468583/data/yosys/anlogic/brams_map.v:95: Cannot find include file: brams_init_8.vh\n   `include "brams_init_8.vh" \n            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/anlogic/brams_map.v:150: Cannot find include file: brams_init_16.vh\n  `include "brams_init_16.vh" \n           ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module \$__ANLOGIC_BRAM32K (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
	parameter CFG_ABITS = 11;
	parameter CFG_DBITS = 16;

	parameter CLKPOL2 = 1;
	parameter CLKPOL3 = 1;
	parameter [32767:0] INIT = 32768'bx;

	input CLK2;
	input CLK3;

	input [CFG_ABITS-1:0] A1ADDR;
	output [CFG_DBITS-1:0] A1DATA;
	input A1EN;

	input [CFG_ABITS-1:0] B1ADDR;
	input [CFG_DBITS-1:0] B1DATA;
	input [1:0] B1EN;

	localparam CLKAMUX = CLKPOL2 ? "SIG" : "INV";
	localparam CLKBMUX = CLKPOL3 ? "SIG" : "INV";

	wire byteweb = B1EN[1] ^ B1EN[0];
	wire byteb = B1EN[1];

	EG_PHY_BRAM32K #(
		.MODE("DP16K"),
		.DATA_WIDTH_A("16"),
		.DATA_WIDTH_B("16"),
		.REGMODE_A("NOREG"),
		.REGMODE_B("NOREG"),
		.WRITEMODE_A("NORMAL"),
		.WRITEMODE_B("NORMAL"),
		.SRMODE("ASYNC"),
		.CSAMUX("SIG"), .CSBMUX("SIG"),
		.OCEAMUX("1"), .OCEBMUX("1"),
		.RSTAMUX("0"), .RSTBMUX("0"),
		.CLKAMUX(CLKAMUX),
		.CLKBMUX(CLKBMUX),
		.WEAMUX("0"), .WEBMUX("SIG"),
		.READBACK("OFF"),
		`include "brams_init_16.vh"
	) _TECHMAP_REPLACE_ (
		.doa(A1DATA), .dib(B1DATA),
		.addra(A1ADDR), .addrb(B1ADDR),
		.bytea(1'b0), .byteb(byteb),
		.bytewea(1'b0), .byteweb(byteweb),
		.csa(A1EN), .csb(|B1EN),
		.wea(1'b0), .web(|B1EN),
		.clka(CLK2), .clkb(CLK3),
		.rsta(1'b0), .rstb(1'b0),
		.ocea(1'b1), .oceb(1'b1)
	);
endmodule
module \$__ANLOGIC_BRAM32K (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);

	parameter CFG_ABITS = 11;
	parameter CFG_DBITS = 16;

	parameter CLKPOL2 = 1;
	parameter CLKPOL3 = 1;
	parameter [32767:0] INIT = 32768'bx;

	input CLK2;
	input CLK3;

	input [CFG_ABITS-1:0] A1ADDR;
	output [CFG_DBITS-1:0] A1DATA;
	input A1EN;

	input [CFG_ABITS-1:0] B1ADDR;
	input [CFG_DBITS-1:0] B1DATA;
	input [1:0] B1EN;

	localparam CLKAMUX = CLKPOL2 ? "SIG" : "INV";
	localparam CLKBMUX = CLKPOL3 ? "SIG" : "INV";

	wire byteweb = B1EN[1] ^ B1EN[0];
	wire byteb = B1EN[1];

	EG_PHY_BRAM32K #(
		.MODE("DP16K"),
		.DATA_WIDTH_A("16"),
		.DATA_WIDTH_B("16"),
		.REGMODE_A("NOREG"),
		.REGMODE_B("NOREG"),
		.WRITEMODE_A("NORMAL"),
		.WRITEMODE_B("NORMAL"),
		.SRMODE("ASYNC"),
		.CSAMUX("SIG"), .CSBMUX("SIG"),
		.OCEAMUX("1"), .OCEBMUX("1"),
		.RSTAMUX("0"), .RSTBMUX("0"),
		.CLKAMUX(CLKAMUX),
		.CLKBMUX(CLKBMUX),
		.WEAMUX("0"), .WEBMUX("SIG"),
		.READBACK("OFF"),
		`include "brams_init_16.vh"
	) _TECHMAP_REPLACE_ (
		.doa(A1DATA), .dib(B1DATA),
		.addra(A1ADDR), .addrb(B1ADDR),
		.bytea(1'b0), .byteb(byteb),
		.bytewea(1'b0), .byteweb(byteweb),
		.csa(A1EN), .csb(|B1EN),
		.wea(1'b0), .web(|B1EN),
		.clka(CLK2), .clkb(CLK3),
		.rsta(1'b0), .rstb(1'b0),
		.ocea(1'b1), .oceb(1'b1)
	);
endmodule