data/full_repos/permissive/458737381/src/verilog-parser/tests/std-3.11.1-specparam.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/std-3.11.1-specparam.v:1: Input/output/inout declaration not found for port: 'DOUT'\nmodule RAM16GEN (DOUT, DIN, ADR, WE, CE);\n                 ^~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/std-3.11.1-specparam.v:1: Input/output/inout declaration not found for port: 'DIN'\nmodule RAM16GEN (DOUT, DIN, ADR, WE, CE);\n                       ^~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/std-3.11.1-specparam.v:1: Input/output/inout declaration not found for port: 'ADR'\nmodule RAM16GEN (DOUT, DIN, ADR, WE, CE);\n                            ^~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/std-3.11.1-specparam.v:1: Input/output/inout declaration not found for port: 'WE'\nmodule RAM16GEN (DOUT, DIN, ADR, WE, CE);\n                                 ^~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/std-3.11.1-specparam.v:1: Input/output/inout declaration not found for port: 'CE'\nmodule RAM16GEN (DOUT, DIN, ADR, WE, CE);\n                                     ^~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/std-3.11.1-specparam.v:5: Can't find definition of variable: 'dhold'\nparameter regsize = dhold + 1.0;\n                    ^~~~~\n%Error: Exiting due to 6 error(s)\n"
module RAM16GEN (DOUT, DIN, ADR, WE, CE);
specparam dhold = 1.0;
specparam ddly = 1.0;
parameter width = 1;
parameter regsize = dhold + 1.0;



specify
specparam tRise_clk_q = 150, tFall_clk_q = 200;
specparam tRise_control = 40, tFall_control = 50;
endspecify

endmodule
module RAM16GEN (DOUT, DIN, ADR, WE, CE);

specparam dhold = 1.0;
specparam ddly = 1.0;
parameter width = 1;
parameter regsize = dhold + 1.0;



specify
specparam tRise_clk_q = 150, tFall_clk_q = 200;
specparam tRise_control = 40, tFall_control = 50;
endspecify

endmodule