data/full_repos/permissive/528147991/scr/inst_mem.v
data/verilator_xmls/f65ffb96-e70c-4927-a366-bf77609349c4.xml
module inst_mem(clk, addr, read);

	input clk;
	input [31:0] addr;
	output [31:0] read;
	
	integer Spulse = 0;
	
	reg [31:0] mem[100:0];
	
	
	always @ (posedge clk )
	begin
	
		if (Spulse==0)
		begin

			
			mem[0] <= 32'b00000000000000000000000000000000;
			mem[1] <= 32'b010011_00000_00000_0000000001111011;
			mem[2] <= 32'b010011_00001_00000_0000000101011001;
			mem[3] <= 32'b010011_00010_00000_1111110111001001;
			mem[4] <= 32'b010011_00011_00000_0000001100010101;
			mem[5] <= 32'b000001_00011_00000_00001_00000000000;
			mem[6] <= 32'b000001_00001_00011_00010_00000000000;
			mem[7] <= 32'b000011_00100_00001_00010_00000000000;
			
			Spulse = 1;
		end
	end
	
	assign read = mem[addr];
	
endmodule
module inst_mem(clk, addr, read);


	input clk;
	input [31:0] addr;
	output [31:0] read;
	
	integer Spulse = 0;
	
	reg [31:0] mem[100:0];
	
	
	always @ (posedge clk )
	begin
	
		if (Spulse==0)
		begin

			
			mem[0] <= 32'b00000000000000000000000000000000;
			mem[1] <= 32'b010011_00000_00000_0000000001111011;
			mem[2] <= 32'b010011_00001_00000_0000000101011001;
			mem[3] <= 32'b010011_00010_00000_1111110111001001;
			mem[4] <= 32'b010011_00011_00000_0000001100010101;
			mem[5] <= 32'b000001_00011_00000_00001_00000000000;
			mem[6] <= 32'b000001_00001_00011_00010_00000000000;
			mem[7] <= 32'b000011_00100_00001_00010_00000000000;
			
			Spulse = 1;
		end
	end
	
	assign read = mem[addr];
	
endmodule