data/full_repos/permissive/412289941/recover.v
data/verilator_xmls/17f6d9d4-4171-463a-b934-1a63915eec14.xml
module recover(clk_in, rst_n, indata_8, clk_out);

input clk_in, rst_n;
input [7:0]indata_8;
output reg clk_out;
reg [3:0]counter;
reg [7:0]buffer;
reg flag;

always @(posedge clk_in or negedge rst_n) begin

    if(!rst_n) buffer<=8'b0;
    else buffer<=indata_8;
end


always @(posedge clk_in or negedge rst_n) begin
    if(!rst_n) begin

        clk_out<=0;
        flag <=0;
        counter <=1;
    end
    else begin



        if ((buffer >= 8'h58 && indata_8 <=8'h3f) || (buffer <=8'h3f && buffer >= 8'h30 && (indata_8 >= 8'h58 || indata_8 <= 8'h0f)) || 
                (buffer <= 8'h0f && indata_8 >= 8'h30)) flag<= 1;
        if(flag == 1) begin
            if (counter==4'h8) begin

                clk_out=~clk_out;
                counter<=1;
            end    
            else begin

                counter <= counter+1;
            end
        end
    end
end

endmodule
module recover(clk_in, rst_n, indata_8, clk_out);


input clk_in, rst_n;
input [7:0]indata_8;
output reg clk_out;
reg [3:0]counter;
reg [7:0]buffer;
reg flag;

always @(posedge clk_in or negedge rst_n) begin

    if(!rst_n) buffer<=8'b0;
    else buffer<=indata_8;
end


always @(posedge clk_in or negedge rst_n) begin
    if(!rst_n) begin

        clk_out<=0;
        flag <=0;
        counter <=1;
    end
    else begin



        if ((buffer >= 8'h58 && indata_8 <=8'h3f) || (buffer <=8'h3f && buffer >= 8'h30 && (indata_8 >= 8'h58 || indata_8 <= 8'h0f)) || 
                (buffer <= 8'h0f && indata_8 >= 8'h30)) flag<= 1;
        if(flag == 1) begin
            if (counter==4'h8) begin

                clk_out=~clk_out;
                counter<=1;
            end    
            else begin

                counter <= counter+1;
            end
        end
    end
end

endmodule