data/full_repos/permissive/497571993/vending_machine.v
data/verilator_xmls/e89a5800-b22b-4c22-88ae-d19c5fddecc2.xml
module vending_machine (clk,rst,in,out,change);
input clk,rst;
input [1:0]in;
output reg out;
output reg [1:0]change;

parameter S0 = 2'b00,
		  S1 = 2'b01,
		  S2 = 2'b10;
		  
	reg [1:0] present_state,next_state;
	
	always@ (posedge clk)
	begin
	if (rst)
	begin
	present_state <= 2'b00;
	next_state =2'b00;
	change = 2'b00;
	out =0;
	end
	else
	present_state <= next_state;
	
	case (present_state)
	  S0 :
	  if (in == 2'b00)
	  begin
	    next_state = S0;
		out = 0;
		change = 2'b00;
		end
      else if (in == 2'b01)
        begin
        next_state=S1;
		out=0;
		change=2'b00;
		end
	  else if (in == 2'b10)
        begin
        next_state=S2;
		out=0;
		change=2'b00;
		end
	  
       S1 :
	  if (in == 2'b00)
	  begin
	    next_state = S0;
		out = 0;
		change = 2'b01;
		end
      else if (in == 2'b01)
        begin
        next_state=S2;
		out=0;
		change=2'b00;
		end
	  else if (in == 2'b10)
        begin
        next_state=S0;
		out=1;
		change=2'b00;
		end		
			
	  S2 :
	  if (in == 2'b00)
	  begin
	    next_state = S0;
		out = 0;
		change = 2'b10;
		end
      else if (in == 2'b01)
        begin
        next_state=S0;
		out=1;
		change=2'b00;
		end
	  else if (in == 2'b10)
        begin
        next_state=S0;
		out=1;
		change=2'b01;
		end	
		endcase
		end
	endmodule
module vending_machine (clk,rst,in,out,change);

input clk,rst;
input [1:0]in;
output reg out;
output reg [1:0]change;

parameter S0 = 2'b00,
		  S1 = 2'b01,
		  S2 = 2'b10;
		  
	reg [1:0] present_state,next_state;
	
	always@ (posedge clk)
	begin
	if (rst)
	begin
	present_state <= 2'b00;
	next_state =2'b00;
	change = 2'b00;
	out =0;
	end
	else
	present_state <= next_state;
	
	case (present_state)
	  S0 :
	  if (in == 2'b00)
	  begin
	    next_state = S0;
		out = 0;
		change = 2'b00;
		end
      else if (in == 2'b01)
        begin
        next_state=S1;
		out=0;
		change=2'b00;
		end
	  else if (in == 2'b10)
        begin
        next_state=S2;
		out=0;
		change=2'b00;
		end
	  
       S1 :
	  if (in == 2'b00)
	  begin
	    next_state = S0;
		out = 0;
		change = 2'b01;
		end
      else if (in == 2'b01)
        begin
        next_state=S2;
		out=0;
		change=2'b00;
		end
	  else if (in == 2'b10)
        begin
        next_state=S0;
		out=1;
		change=2'b00;
		end		
			
	  S2 :
	  if (in == 2'b00)
	  begin
	    next_state = S0;
		out = 0;
		change = 2'b10;
		end
      else if (in == 2'b01)
        begin
        next_state=S0;
		out=1;
		change=2'b00;
		end
	  else if (in == 2'b10)
        begin
        next_state=S0;
		out=1;
		change=2'b01;
		end	
		endcase
		end
	endmodule