data/full_repos/permissive/428158935/sources_1/new/AdderModule.v
data/verilator_xmls/dff4d8a6-ea7a-49c3-a5fc-75c71889658f.xml
module CLA_Add_32bit(
    input[31:0] A,
    input[31:0] B,
    input CI_0,
    output[31:0] S,
    output CO
);

wire CI_16;
wire[1:0] G;
wire[1:0] P;

CLA_Add_16bit u1(
    .A (A[15:0]),
    .B (B[15:0]),
    .CI_0 (CI_0),
    .S (S[15:0]),
    .GM (G[0]),
    .PM (P[0])
);

CLA_Add_16bit u2(
    .A (A[31:16]),
    .B (B[31:16]),
    .CI_0 (CI_16),
    .S (S[31:16]),
    .GM (G[1]),
    .PM (P[1])
);

wire temp[2:0];
and(temp[0],CI_0,P[0]);
and(temp[1],temp[0],P[1]);
and(temp[2],G[0],P[1]);
or(CI_16,G[0],temp[0]);
or(CO,G[1],temp[2],temp[1]);

endmodule
module CLA_Add_32bit(
    input[31:0] A,
    input[31:0] B,
    input CI_0,
    output[31:0] S,
    output CO
);


wire CI_16;
wire[1:0] G;
wire[1:0] P;

CLA_Add_16bit u1(
    .A (A[15:0]),
    .B (B[15:0]),
    .CI_0 (CI_0),
    .S (S[15:0]),
    .GM (G[0]),
    .PM (P[0])
);

CLA_Add_16bit u2(
    .A (A[31:16]),
    .B (B[31:16]),
    .CI_0 (CI_16),
    .S (S[31:16]),
    .GM (G[1]),
    .PM (P[1])
);

wire temp[2:0];
and(temp[0],CI_0,P[0]);
and(temp[1],temp[0],P[1]);
and(temp[2],G[0],P[1]);
or(CI_16,G[0],temp[0]);
or(CO,G[1],temp[2],temp[1]);

endmodule