data/full_repos/permissive/499494419/bo.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/499494419/bo.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/499494419/bo.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/bo.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/499494419/bo.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: data/full_repos/permissive/499494419/bo.v:36: Cannot find file containing module: \'ma\'\n ma uut (\n ^~\n        ... Looked in:\n             data/full_repos/permissive/499494419,data/full_repos/permissive/499494419/ma\n             data/full_repos/permissive/499494419,data/full_repos/permissive/499494419/ma.v\n             data/full_repos/permissive/499494419,data/full_repos/permissive/499494419/ma.sv\n             ma\n             ma.v\n             ma.sv\n             obj_dir/ma\n             obj_dir/ma.v\n             obj_dir/ma.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bo;


	reg A;


	wire wa;
	wire ka;
	wire re;


	ma uut (
		.A(A), 
		.wa(wa), 
		.re(re),
		.ka(ka)
	);

	initial begin

		A = 0;


		#100;
		A=1;
		#10;
		A=0;
		#10;
		A=1;
		#10;
		A=0;
        


	end
      
endmodule
module bo;



	reg A;


	wire wa;
	wire ka;
	wire re;


	ma uut (
		.A(A), 
		.wa(wa), 
		.re(re),
		.ka(ka)
	);

	initial begin

		A = 0;


		#100;
		A=1;
		#10;
		A=0;
		#10;
		A=1;
		#10;
		A=0;
        


	end
      
endmodule