data/full_repos/permissive/461069000/timer/src/timer_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/461069000/timer/src/timer_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #(c_CLOCK_PERIOD_NS/2) clk <= !clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/461069000/timer/src/timer_tb.v:36: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("timer_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/461069000/timer/src/timer_tb.v:37: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;  \n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/461069000/timer/src/timer_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #(c_CLOCK_PERIOD_NS*2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/461069000/timer/src/timer_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #(c_CLOCK_PERIOD_NS*2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/461069000/timer/src/timer_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #(c_CLOCK_PERIOD_NS*2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/461069000/timer/src/timer_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #(c_CLOCK_PERIOD_NS*2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/461069000/timer/src/timer_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #(c_CLOCK_PERIOD_NS*2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/461069000/timer/src/timer_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n        #(c_CLOCK_PERIOD_NS*2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/461069000/timer/src/timer_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n        #c_CLOCK_PERIOD_NS;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/461069000/timer/src/timer_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n        #(c_CLOCK_PERIOD_NS*24000);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/461069000/timer/src/timer_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n        #(c_CLOCK_PERIOD_NS);\n        ^\n%Error: Exiting due to 2 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module timer_tb();

    localparam  c_CLOCK_PERIOD_NS = 100;

    reg clk = 0;
    reg ext_clk = 0;
    reg rst = 1;
    reg enable = 1;
    reg [3:0] config_address = 0;
    reg config_write_enable = 0;
    reg [7:0] write_data = 0;
    wire comparator_1_output;
    wire comparator_0_output;
    wire [7:0] read_data;

    timer timer_0(
        .clk(clk),
        .ext_clk(ext_clk),
        .enable(enable),
        .rst(rst), 
        .config_address(config_address),
        .config_write_enable(config_write_enable),
        .write_data(write_data),
        .read_data(read_data),
        .comparator_1_output(comparator_1_output),
        .comparator_0_output(comparator_0_output)
    );

    always 
        #(c_CLOCK_PERIOD_NS/2) clk <= !clk;

    initial begin
        $dumpfile("timer_tb.vcd");
        $dumpvars;  
        rst = 0;
        #(c_CLOCK_PERIOD_NS*2);
        rst = 1;
        #(c_CLOCK_PERIOD_NS*2);

        config_write_enable = 1;
        config_address = 0;
        write_data = 8'b1_0_0_1_0_000;

        #(c_CLOCK_PERIOD_NS*2);

        config_write_enable = 1;
        config_address = 6;
        write_data = 8'hFA;

        #(c_CLOCK_PERIOD_NS*2);

        config_write_enable = 1;
        config_address = 5;
        write_data = 8'hEA;
        
        #(c_CLOCK_PERIOD_NS*2);

        config_write_enable = 1;
        config_address = 3;
        write_data = 8'hED;
        
        #(c_CLOCK_PERIOD_NS*2);


        config_write_enable = 1;
        config_address = 0;
        write_data = 8'b1_1_0_1_1_000;
        #c_CLOCK_PERIOD_NS;

        config_write_enable = 0;
        config_address = 2;

        #(c_CLOCK_PERIOD_NS*24000);

        config_write_enable = 1;
        config_address = 1;
        write_data = 8'b1_1_000000;

        #(c_CLOCK_PERIOD_NS);
        config_write_enable = 0;
        


        $finish;
    end




endmodule
module timer_tb();


    localparam  c_CLOCK_PERIOD_NS = 100;

    reg clk = 0;
    reg ext_clk = 0;
    reg rst = 1;
    reg enable = 1;
    reg [3:0] config_address = 0;
    reg config_write_enable = 0;
    reg [7:0] write_data = 0;
    wire comparator_1_output;
    wire comparator_0_output;
    wire [7:0] read_data;

    timer timer_0(
        .clk(clk),
        .ext_clk(ext_clk),
        .enable(enable),
        .rst(rst), 
        .config_address(config_address),
        .config_write_enable(config_write_enable),
        .write_data(write_data),
        .read_data(read_data),
        .comparator_1_output(comparator_1_output),
        .comparator_0_output(comparator_0_output)
    );

    always 
        #(c_CLOCK_PERIOD_NS/2) clk <= !clk;

    initial begin
        $dumpfile("timer_tb.vcd");
        $dumpvars;  
        rst = 0;
        #(c_CLOCK_PERIOD_NS*2);
        rst = 1;
        #(c_CLOCK_PERIOD_NS*2);

        config_write_enable = 1;
        config_address = 0;
        write_data = 8'b1_0_0_1_0_000;

        #(c_CLOCK_PERIOD_NS*2);

        config_write_enable = 1;
        config_address = 6;
        write_data = 8'hFA;

        #(c_CLOCK_PERIOD_NS*2);

        config_write_enable = 1;
        config_address = 5;
        write_data = 8'hEA;
        
        #(c_CLOCK_PERIOD_NS*2);

        config_write_enable = 1;
        config_address = 3;
        write_data = 8'hED;
        
        #(c_CLOCK_PERIOD_NS*2);


        config_write_enable = 1;
        config_address = 0;
        write_data = 8'b1_1_0_1_1_000;
        #c_CLOCK_PERIOD_NS;

        config_write_enable = 0;
        config_address = 2;

        #(c_CLOCK_PERIOD_NS*24000);

        config_write_enable = 1;
        config_address = 1;
        write_data = 8'b1_1_000000;

        #(c_CLOCK_PERIOD_NS);
        config_write_enable = 0;
        


        $finish;
    end




endmodule