data/full_repos/permissive/456824115/testbench/MidSort_tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/456824115/testbench/MidSort_tb.sv:49: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/456824115/testbench/MidSort_tb.sv:55: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/456824115/testbench/MidSort_tb.sv:57: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Error: data/full_repos/permissive/456824115/testbench/MidSort_tb.sv:61: syntax error, unexpected \'@\'\n                @(posedge clk);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/456824115/testbench/MidSort_tb.sv:62: Unsupported: Ignoring delay on this delayed statement.\n                #2\n                ^\n%Error: data/full_repos/permissive/456824115/testbench/MidSort_tb.sv:74: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/456824115/testbench/MidSort_tb.sv:76: Unsupported: Ignoring delay on this delayed statement.\n        #200 $finish;\n        ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module MidSort_tb;
parameter DATA_WIDTH = 8;
bit clk;
bit arstn;
bit din_valid;
bit [DATA_WIDTH-1:0]din00;
bit [DATA_WIDTH-1:0]din01;
bit [DATA_WIDTH-1:0]din02;
bit [DATA_WIDTH-1:0]din10;
bit [DATA_WIDTH-1:0]din11;
bit [DATA_WIDTH-1:0]din12;
bit [DATA_WIDTH-1:0]din20;
bit [DATA_WIDTH-1:0]din21;
bit [DATA_WIDTH-1:0]din22;
wire [DATA_WIDTH-1:0]dout_data;
wire dout_valid;
wire [DATA_WIDTH-1:0]out0;
wire [DATA_WIDTH-1:0]out1;
wire [DATA_WIDTH-1:0]out2;
wire [DATA_WIDTH-1:0]out3;
wire [DATA_WIDTH-1:0]out4;
wire [DATA_WIDTH-1:0]out5;
wire [DATA_WIDTH-1:0]out6;
wire [DATA_WIDTH-1:0]out7;
wire [DATA_WIDTH-1:0]out8;
integer i;
always #5 clk = ~clk;

initial
    begin
        arstn = 1'b1;
        din_valid = 1'b0;
        #20
        arstn = 1'b0;
        #20
        arstn = 1'b1;
        for(i=0;i<64;i=i+1)
            begin
                @(posedge clk);
                #2
                    din00 = $random()%256;
                    din01 = $random()%256;
                    din02 = $random()%256;
                    din10 = $random()%256;
                    din11 = $random()%256;
                    din12 = $random()%256;
                    din20 = $random()%256;
                    din21 = $random()%256;
                    din22 = $random()%256;
                    din_valid = 1'b1;
            end
        @(posedge clk);
        din_valid = 1'b0;
        #200 $finish;
    end

MidSort3x3 #(
    .DATA_WIDTH(DATA_WIDTH)
)DUT(clk,arstn,din00,din01,din02,din10,din11,din12,
    din20,din21,din22,din_valid,dout_data,dout_valid,out0,out1,out2,
    out3,out4,out5,out6,out7,out8);
endmodule
module MidSort_tb;

parameter DATA_WIDTH = 8;
bit clk;
bit arstn;
bit din_valid;
bit [DATA_WIDTH-1:0]din00;
bit [DATA_WIDTH-1:0]din01;
bit [DATA_WIDTH-1:0]din02;
bit [DATA_WIDTH-1:0]din10;
bit [DATA_WIDTH-1:0]din11;
bit [DATA_WIDTH-1:0]din12;
bit [DATA_WIDTH-1:0]din20;
bit [DATA_WIDTH-1:0]din21;
bit [DATA_WIDTH-1:0]din22;
wire [DATA_WIDTH-1:0]dout_data;
wire dout_valid;
wire [DATA_WIDTH-1:0]out0;
wire [DATA_WIDTH-1:0]out1;
wire [DATA_WIDTH-1:0]out2;
wire [DATA_WIDTH-1:0]out3;
wire [DATA_WIDTH-1:0]out4;
wire [DATA_WIDTH-1:0]out5;
wire [DATA_WIDTH-1:0]out6;
wire [DATA_WIDTH-1:0]out7;
wire [DATA_WIDTH-1:0]out8;
integer i;
always #5 clk = ~clk;

initial
    begin
        arstn = 1'b1;
        din_valid = 1'b0;
        #20
        arstn = 1'b0;
        #20
        arstn = 1'b1;
        for(i=0;i<64;i=i+1)
            begin
                @(posedge clk);
                #2
                    din00 = $random()%256;
                    din01 = $random()%256;
                    din02 = $random()%256;
                    din10 = $random()%256;
                    din11 = $random()%256;
                    din12 = $random()%256;
                    din20 = $random()%256;
                    din21 = $random()%256;
                    din22 = $random()%256;
                    din_valid = 1'b1;
            end
        @(posedge clk);
        din_valid = 1'b0;
        #200 $finish;
    end

MidSort3x3 #(
    .DATA_WIDTH(DATA_WIDTH)
)DUT(clk,arstn,din00,din01,din02,din10,din11,din12,
    din20,din21,din22,din_valid,dout_data,dout_valid,out0,out1,out2,
    out3,out4,out5,out6,out7,out8);
endmodule