data/full_repos/permissive/449807379/CPU_design/immediateMov.v
1: b'%Warning-WIDTH: data/full_repos/permissive/449807379/CPU_design/immediateMov.v:10: Operator ASSIGN expects 36 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                 : ... In instance immediateMov\n r1={16\'b0,n};\n   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/449807379/CPU_design/immediateMov.v:14: Operator ASSIGN expects 36 bits on the Assign RHS, but Assign RHS\'s CONST \'35\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz\' generates 35 bits.\n                                                                                 : ... In instance immediateMov\nr1=35\'bz;\n  ^\n%Error: Exiting due to 2 warning(s)\n'
module immediateMov(n, r1, add_en);
input  [15:0] n;
input add_en;
output reg [35:0] r1;

always @*
begin 
if(add_en==1'b1)
begin
	r1={16'b0,n};
	r1[35:32] = 4'b0;
end
else
r1=35'bz;
end

endmodule
module immediateMov(n, r1, add_en);

input  [15:0] n;
input add_en;
output reg [35:0] r1;

always @*
begin 
if(add_en==1'b1)
begin
	r1={16'b0,n};
	r1[35:32] = 4'b0;
end
else
r1=35'bz;
end

endmodule