data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/stack_machine/test/stackMachine_test.v
1: b'%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/stack_machine/test/stackMachine_test.v:39: syntax error, unexpected \'@\'\n  @(negedge clk);\n  ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/stack_machine/test/stackMachine_test.v:45: syntax error, unexpected \'@\'\n  @(negedge clk);\n  ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/stack_machine/test/stackMachine_test.v:48: syntax error, unexpected \'@\'\n  @(negedge clk);\n  ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/stack_machine/test/stackMachine_test.v:51: syntax error, unexpected \'@\'\n  @(negedge clk);\n  ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/stack_machine/test/stackMachine_test.v:53: syntax error, unexpected \'@\'\n  @(negedge clk);\n  ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/stack_machine/test/stackMachine_test.v:56: syntax error, unexpected \'@\'\n  @(negedge clk);\n  ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/stack_machine/test/stackMachine_test.v:58: syntax error, unexpected \'@\'\n  @(negedge clk);\n  ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/stack_machine/test/stackMachine_test.v:60: syntax error, unexpected \'@\'\n  @(negedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/stack_machine/test/stackMachine_test.v:70: Unsupported: Ignoring delay on this delayed statement.\n  always  #5  clk=~clk; \n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 8 error(s), 1 warning(s)\n'
module stackMachine_test();


	parameter N=8;
	parameter S=8;

	reg clk, rst;

	reg [N-1:0] x;
	reg [2:0] opcode;

	wire [N-1:0] o;



	stackMachine #(
	.N(N),
	.S(S)
	)
	UUT
	(
		.clk(clk),
		.rst(rst),
		.x(x),
		.opcode(opcode),
		.o(o)
	);


	initial
	begin
		clk = 0;
		rst = 1;
		x = 0;
		opcode = 0;
		@(negedge clk);
		@(negedge clk);
		@(negedge clk);
		rst = 0;
		x = 2;
		opcode = 4;
		@(negedge clk);
		x = 4;
		opcode = 4;
		@(negedge clk);
		x = 5;
		opcode = 4;
		@(negedge clk);
		opcode = 3;
		@(negedge clk);
		x = 6;
		opcode = 4;
		@(negedge clk);
		opcode = 1;
		@(negedge clk);
		opcode = 1;
		@(negedge clk);
		if (o !== 2+4*5+6)
        begin 
          $display("Error"); 
          $finish; 
        end
        $display("Good.");
		$finish;
	end

 	always  #5  clk=~clk; 

endmodule
module stackMachine_test();



	parameter N=8;
	parameter S=8;

	reg clk, rst;

	reg [N-1:0] x;
	reg [2:0] opcode;

	wire [N-1:0] o;



	stackMachine #(
	.N(N),
	.S(S)
	)
	UUT
	(
		.clk(clk),
		.rst(rst),
		.x(x),
		.opcode(opcode),
		.o(o)
	);


	initial
	begin
		clk = 0;
		rst = 1;
		x = 0;
		opcode = 0;
		@(negedge clk);
		@(negedge clk);
		@(negedge clk);
		rst = 0;
		x = 2;
		opcode = 4;
		@(negedge clk);
		x = 4;
		opcode = 4;
		@(negedge clk);
		x = 5;
		opcode = 4;
		@(negedge clk);
		opcode = 3;
		@(negedge clk);
		x = 6;
		opcode = 4;
		@(negedge clk);
		opcode = 1;
		@(negedge clk);
		opcode = 1;
		@(negedge clk);
		if (o !== 2+4*5+6)
        begin 
          $display("Error"); 
          $finish; 
        end
        $display("Good.");
		$finish;
	end

 	always  #5  clk=~clk; 

endmodule