data/full_repos/permissive/477054115/iitb-risc/ALU.v
data/verilator_xmls/829c6e74-1cdf-4d14-8d7a-a9a2e1d0f59f.xml
module alu
(
    input   [15:0]  a,
    input   [15:0]  b,
    input   [1:0]   alu_control,
    output reg [15:0]   result,
    output reg zero,
    output reg carry
);

    reg [16:0] total_sum;

    initial begin
        zero = 1'b0;
        carry = 1'b0;
        result = 0;
    end

    always @(*) begin
        case(alu_control)
            2'b00: total_sum = {1'b0, a} + {1'b0, b};
            2'b01: result = ~(a & b);
            default: result = 0;
        endcase
        result = (alu_control == 2'b00) ? total_sum[15:0]: result;
        if (alu_control == 2'b00 || alu_control == 2'b01) begin
            zero = (result == 0) ? 1'b1 : 1'b0;
            carry = (~(a[15] ^ b[15]) && (total_sum[15] ^ a[15])) ? 1'b1 : 1'b0;
        end
        else begin
            zero = 1'b0;
            carry = 1'b0;
        end
    end

endmodule
module alu
(
    input   [15:0]  a,
    input   [15:0]  b,
    input   [1:0]   alu_control,
    output reg [15:0]   result,
    output reg zero,
    output reg carry
);


    reg [16:0] total_sum;

    initial begin
        zero = 1'b0;
        carry = 1'b0;
        result = 0;
    end

    always @(*) begin
        case(alu_control)
            2'b00: total_sum = {1'b0, a} + {1'b0, b};
            2'b01: result = ~(a & b);
            default: result = 0;
        endcase
        result = (alu_control == 2'b00) ? total_sum[15:0]: result;
        if (alu_control == 2'b00 || alu_control == 2'b01) begin
            zero = (result == 0) ? 1'b1 : 1'b0;
            carry = (~(a[15] ^ b[15]) && (total_sum[15] ^ a[15])) ? 1'b1 : 1'b0;
        end
        else begin
            zero = 1'b0;
            carry = 1'b0;
        end
    end

endmodule