data/full_repos/permissive/477770962/mux41_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/477770962/mux41_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n #15 $finish;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/477770962/mux41_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #1\n  ^\n%Error: data/full_repos/permissive/477770962/mux41_tb.v:33: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("output.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/477770962/mux41_tb.v:34: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0);\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux41_tb();
	reg [3:0] i1, i2, i3, i4;
	reg [1:0] sel;
	wire [3:0] z_8107;
	
	integer i;

mux41 u1(i1, i2, i3, i4, sel, z_8107); 

initial begin

	i1= 4'b0000;  i2= 4'b0000;  i3= 4'b0000; i4= 4'b0000; sel= 2'b00; 
	#15 $finish;
end


always begin
	for (i = 0; i < 4; i = i + 1) begin
		#1
		i1= $random; 
		i2= $random;
		i3= $random;
		i4= $random;
		sel= i; 
	end
		
end	


initial begin
  $dumpfile("output.vcd");
	$dumpvars(0);
end

endmodule
module mux41_tb();

	reg [3:0] i1, i2, i3, i4;
	reg [1:0] sel;
	wire [3:0] z_8107;
	
	integer i;

mux41 u1(i1, i2, i3, i4, sel, z_8107); 

initial begin

	i1= 4'b0000;  i2= 4'b0000;  i3= 4'b0000; i4= 4'b0000; sel= 2'b00; 
	#15 $finish;
end


always begin
	for (i = 0; i < 4; i = i + 1) begin
		#1
		i1= $random; 
		i2= $random;
		i3= $random;
		i4= $random;
		sel= i; 
	end
		
end	


initial begin
  $dumpfile("output.vcd");
	$dumpvars(0);
end

endmodule