data/full_repos/permissive/503053625/resources/unused/pulse_FSM_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/unused/pulse_FSM_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #ADC_H_period;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/unused/pulse_FSM_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #ADC_H_period;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/unused/pulse_FSM_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #TRIG_H_period;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/unused/pulse_FSM_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #TRIG_H_period;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/unused/pulse_FSM_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #ADC_H_period;\n  ^\n%Error: data/full_repos/permissive/503053625/resources/unused/pulse_FSM_tb.v:14: Cannot find file containing module: \'pulse_FSM\'\n pulse_FSM FSM0 (\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/503053625/resources/unused,data/full_repos/permissive/503053625/pulse_FSM\n             data/full_repos/permissive/503053625/resources/unused,data/full_repos/permissive/503053625/pulse_FSM.v\n             data/full_repos/permissive/503053625/resources/unused,data/full_repos/permissive/503053625/pulse_FSM.sv\n             pulse_FSM\n             pulse_FSM.v\n             pulse_FSM.sv\n             obj_dir/pulse_FSM\n             obj_dir/pulse_FSM.v\n             obj_dir/pulse_FSM.sv\n%Error: data/full_repos/permissive/503053625/resources/unused/pulse_FSM_tb.v:24: Cannot find file containing module: \'pulse_counter\'\n pulse_counter #(\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/503053625/resources/unused/pulse_FSM_tb.v:32: Cannot find file containing module: \'gen_reg\'\n gen_reg #(\n ^~~~~~~\n%Error: Exiting due to 3 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pulse_FSM_tb;
	localparam TRIG_H_period=50;
	localparam ADC_H_period=2;

	wire P;
	reg ADC_CLK = 1'b0;
	reg TRIG_CLK = 1'b0;
	reg PULSE_RST = 1'b0;
	wire [32-1:0] PULSE_COUNT;
	reg [32-1:0] REG_OUT = 32'h0000_0000;

	wire DONE;

	pulse_FSM FSM0 (
		.s(TRIG_CLK),
		.clk(ADC_CLK),
		.rst(PULSE_RST),
		.P(P),
		.L(),
		.A(),
		.B()
	);

	pulse_counter #(
		.DATA_WIDTH(32)
	) PULSE_COUNT0 (
		.clk(ADC_CLK),
		.en(!P),
		.count_val(PULSE_COUNT)
	);

	gen_reg #(
		.DATA_WIDTH(32)
	) REG0 (
		.data_in(PULSE_COUNT),
		.clk(ADC_CLK),
		.wrt(P),
		.rst(REG_RST),
		.data_out(REG_OUT)
);

	always
	begin
		ADC_CLK = 1'b0;
		#ADC_H_period;
		ADC_CLK = 1'b1;
		#ADC_H_period;
	end

	always
	begin
		TRIG_CLK = 1'b0;
		#TRIG_H_period;
		TRIG_CLK = 1'b1;
		#TRIG_H_period;
	end

	initial
	begin
		PULSE_RST = 1'b0;
		#ADC_H_period;
		PULSE_RST = 1'b1;
	end
endmodule
module pulse_FSM_tb;

	localparam TRIG_H_period=50;
	localparam ADC_H_period=2;

	wire P;
	reg ADC_CLK = 1'b0;
	reg TRIG_CLK = 1'b0;
	reg PULSE_RST = 1'b0;
	wire [32-1:0] PULSE_COUNT;
	reg [32-1:0] REG_OUT = 32'h0000_0000;

	wire DONE;

	pulse_FSM FSM0 (
		.s(TRIG_CLK),
		.clk(ADC_CLK),
		.rst(PULSE_RST),
		.P(P),
		.L(),
		.A(),
		.B()
	);

	pulse_counter #(
		.DATA_WIDTH(32)
	) PULSE_COUNT0 (
		.clk(ADC_CLK),
		.en(!P),
		.count_val(PULSE_COUNT)
	);

	gen_reg #(
		.DATA_WIDTH(32)
	) REG0 (
		.data_in(PULSE_COUNT),
		.clk(ADC_CLK),
		.wrt(P),
		.rst(REG_RST),
		.data_out(REG_OUT)
);

	always
	begin
		ADC_CLK = 1'b0;
		#ADC_H_period;
		ADC_CLK = 1'b1;
		#ADC_H_period;
	end

	always
	begin
		TRIG_CLK = 1'b0;
		#TRIG_H_period;
		TRIG_CLK = 1'b1;
		#TRIG_H_period;
	end

	initial
	begin
		PULSE_RST = 1'b0;
		#ADC_H_period;
		PULSE_RST = 1'b1;
	end
endmodule