data/full_repos/permissive/495525032/TL-Verilog/tb_adder.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/495525032/TL-Verilog/tb_adder.v:10: Unsupported: Ignoring delay on this delayed statement.\n            #10\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/495525032/TL-Verilog/tb_adder.v:13: Unsupported: Ignoring delay on this delayed statement.\n            #10\n            ^\n%Error: data/full_repos/permissive/495525032/TL-Verilog/tb_adder.v:4: Cannot find file containing module: \'adder\'\n      adder dut(.a(a), .b(b), .c(c));\n      ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/495525032/TL-Verilog,data/full_repos/permissive/495525032/adder\n             data/full_repos/permissive/495525032/TL-Verilog,data/full_repos/permissive/495525032/adder.v\n             data/full_repos/permissive/495525032/TL-Verilog,data/full_repos/permissive/495525032/adder.sv\n             adder\n             adder.v\n             adder.sv\n             obj_dir/adder\n             obj_dir/adder.v\n             obj_dir/adder.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_adder(input clk);
      reg [2:0] a,b;
      wire [3:0] c;
      adder dut(.a(a), .b(b), .c(c));
      initial 
         begin
            $display("Starting Simulation of adder");
            a = 1;
            b = 2;
            #10
            a = 2;
            b = 2;
            #10
            a = 3;
            b = 1;
         end
   endmodule
module tb_adder(input clk);

      reg [2:0] a,b;
      wire [3:0] c;
      adder dut(.a(a), .b(b), .c(c));
      initial 
         begin
            $display("Starting Simulation of adder");
            a = 1;
            b = 2;
            #10
            a = 2;
            b = 2;
            #10
            a = 3;
            b = 1;
         end
   endmodule