data/full_repos/permissive/515445239/shift_register_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/515445239/shift_register_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n     forever #5 clk=~clk;   \n             ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/515445239/shift_register_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515445239/shift_register_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515445239/shift_register_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515445239/shift_register_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515445239/shift_register_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515445239/shift_register_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515445239/shift_register_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515445239/shift_register_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515445239/shift_register_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n%Error: data/full_repos/permissive/515445239/shift_register_tb.v:73: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("test_bench.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/515445239/shift_register_tb.v:74: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars();\n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_bench;
  reg [3:0] ip;
  reg [1:0] sel;
  reg  load,rst,clk;
  wire [3:0] op;

  shift_reg dut (.op(op), .ip(ip), .sel(sel), .load(load) , .rst(rst) , .clk(clk));
initial
  begin
     clk=1'b1;
     forever #5 clk=~clk;   
  end
  
initial
  begin
    ip   = 4'b1100;
    rst  = 1'b1;
    load = 1'b1;
    sel  = 2'b00;
    #10;
    
    ip   = 4'b1100;
    rst  = 1'b0;
    load = 1'b1;
    sel  = 2'b00;
    #10;
    
    ip   = 4'b1100;
    rst  = 1'b0;
    load = 1'b0;
    sel  = 2'b00;
    #10;
    
    ip   = 4'b1000;
    rst  = 1'b0;
    load = 1'b1;
    sel  = 2'b01;
    #10;
    
    ip   = 4'b1100;
    load = 1'b0;
    sel  = 2'b01;
    #10;
    
    ip   = 4'b1010;
    load = 1'b1;
    sel  = 2'b10;
    #10;
    
    ip   = 4'b1100;

    load = 1'b0;
    sel  = 2'b10;
    #10;

    ip   = 4'b1110;
    load = 1'b1;
    sel  = 2'b11;
    #10;

    ip   = 4'b1111;
    load = 1'b0;
    sel  = 3'b11;
    #10;

    $finish;
  end 
  
  always@(*)
     $display("time =%d, load=%b, sel=%b , ip=%b , rst=%b , op=%b " , $time, load,sel,ip,rst,op);
  
  initial begin
    $dumpfile("test_bench.vcd");
    $dumpvars();
  end
  
endmodule
module test_bench;

  reg [3:0] ip;
  reg [1:0] sel;
  reg  load,rst,clk;
  wire [3:0] op;

  shift_reg dut (.op(op), .ip(ip), .sel(sel), .load(load) , .rst(rst) , .clk(clk));
initial
  begin
     clk=1'b1;
     forever #5 clk=~clk;   
  end
  
initial
  begin
    ip   = 4'b1100;
    rst  = 1'b1;
    load = 1'b1;
    sel  = 2'b00;
    #10;
    
    ip   = 4'b1100;
    rst  = 1'b0;
    load = 1'b1;
    sel  = 2'b00;
    #10;
    
    ip   = 4'b1100;
    rst  = 1'b0;
    load = 1'b0;
    sel  = 2'b00;
    #10;
    
    ip   = 4'b1000;
    rst  = 1'b0;
    load = 1'b1;
    sel  = 2'b01;
    #10;
    
    ip   = 4'b1100;
    load = 1'b0;
    sel  = 2'b01;
    #10;
    
    ip   = 4'b1010;
    load = 1'b1;
    sel  = 2'b10;
    #10;
    
    ip   = 4'b1100;

    load = 1'b0;
    sel  = 2'b10;
    #10;

    ip   = 4'b1110;
    load = 1'b1;
    sel  = 2'b11;
    #10;

    ip   = 4'b1111;
    load = 1'b0;
    sel  = 3'b11;
    #10;

    $finish;
  end 
  
  always@(*)
     $display("time =%d, load=%b, sel=%b , ip=%b , rst=%b , op=%b " , $time, load,sel,ip,rst,op);
  
  initial begin
    $dumpfile("test_bench.vcd");
    $dumpvars();
  end
  
endmodule