data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/xc6s_brams_map.v
1: b'%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/xc6s_brams_map.v:35: Cannot find include file: brams_init_9.vh\n  `include "brams_init_9.vh" \n           ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx,data/full_repos/permissive/441359809/brams_init_9.vh\n             data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx,data/full_repos/permissive/441359809/brams_init_9.vh.v\n             data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx,data/full_repos/permissive/441359809/brams_init_9.vh.sv\n             brams_init_9.vh\n             brams_init_9.vh.v\n             brams_init_9.vh.sv\n             obj_dir/brams_init_9.vh\n             obj_dir/brams_init_9.vh.v\n             obj_dir/brams_init_9.vh.sv\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/xc6s_brams_map.v:103: Cannot find include file: brams_init_18.vh\n   `include "brams_init_18.vh" \n            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/xc6s_brams_map.v:133: Cannot find include file: brams_init_16.vh\n   `include "brams_init_16.vh" \n            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/xc6s_brams_map.v:202: Cannot find include file: brams_init_9.vh\n   `include "brams_init_9.vh" \n            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/xc6s_brams_map.v:233: Cannot find include file: brams_init_8.vh\n   `include "brams_init_8.vh" \n            ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module \$__XILINX_RAMB16BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
	parameter CFG_ABITS = 9;
	parameter CFG_DBITS = 36;
	parameter CFG_ENABLE_B = 4;

	parameter CLKPOL2 = 1;
	parameter CLKPOL3 = 1;
	parameter [18431:0] INIT = 18432'bx;

	input CLK2;
	input CLK3;

	input [CFG_ABITS-1:0] A1ADDR;
	output [CFG_DBITS-1:0] A1DATA;
	input A1EN;

	input [CFG_ABITS-1:0] B1ADDR;
	input [CFG_DBITS-1:0] B1DATA;
	input [CFG_ENABLE_B-1:0] B1EN;

	wire [13:0] A1ADDR_14 = A1ADDR << (14 - CFG_ABITS);
	wire [13:0] B1ADDR_14 = B1ADDR << (14 - CFG_ABITS);
	wire [3:0] B1EN_4 = {4{B1EN}};

	wire [3:0] DIP, DOP;
	wire [31:0] DI, DO;

	wire [31:0] DOB;
	wire [3:0] DOPB;

	assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
	assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;

	generate if (CFG_DBITS > 8) begin
		RAMB16BWER #(
			.DATA_WIDTH_A(CFG_DBITS),
			.DATA_WIDTH_B(CFG_DBITS),
			.WRITE_MODE_A("READ_FIRST"),
			.WRITE_MODE_B("READ_FIRST"),
			`include "brams_init_18.vh"
		) _TECHMAP_REPLACE_ (
			.DIA(32'd0),
			.DIPA(4'd0),
			.DOA(DO[31:0]),
			.DOPA(DOP[3:0]),
			.ADDRA(A1ADDR_14),
			.CLKA(CLK2 ^ !CLKPOL2),
			.ENA(A1EN),
			.REGCEA(|1),
			.RSTA(|0),
			.WEA(4'b0),

			.DIB(DI),
			.DIPB(DIP),
			.DOB(DOB),
			.DOPB(DOPB),
			.ADDRB(B1ADDR_14),
			.CLKB(CLK3 ^ !CLKPOL3),
			.ENB(|1),
			.REGCEB(|0),
			.RSTB(|0),
			.WEB(B1EN_4)
		);
	end else begin
		RAMB16BWER #(
			.DATA_WIDTH_A(CFG_DBITS),
			.DATA_WIDTH_B(CFG_DBITS),
			.WRITE_MODE_A("READ_FIRST"),
			.WRITE_MODE_B("READ_FIRST"),
			`include "brams_init_16.vh"
		) _TECHMAP_REPLACE_ (
			.DIA(32'd0),
			.DIPA(4'd0),
			.DOA(DO[31:0]),
			.DOPA(DOP[3:0]),
			.ADDRA(A1ADDR_14),
			.CLKA(CLK2 ^ !CLKPOL2),
			.ENA(A1EN),
			.REGCEA(|1),
			.RSTA(|0),
			.WEA(4'b0),

			.DIB(DI),
			.DIPB(DIP),
			.DOB(DOB),
			.DOPB(DOPB),
			.ADDRB(B1ADDR_14),
			.CLKB(CLK3 ^ !CLKPOL3),
			.ENB(|1),
			.REGCEB(|0),
			.RSTB(|0),
			.WEB(B1EN_4)
		);
	end endgenerate
endmodule
module \$__XILINX_RAMB16BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);

	parameter CFG_ABITS = 9;
	parameter CFG_DBITS = 36;
	parameter CFG_ENABLE_B = 4;

	parameter CLKPOL2 = 1;
	parameter CLKPOL3 = 1;
	parameter [18431:0] INIT = 18432'bx;

	input CLK2;
	input CLK3;

	input [CFG_ABITS-1:0] A1ADDR;
	output [CFG_DBITS-1:0] A1DATA;
	input A1EN;

	input [CFG_ABITS-1:0] B1ADDR;
	input [CFG_DBITS-1:0] B1DATA;
	input [CFG_ENABLE_B-1:0] B1EN;

	wire [13:0] A1ADDR_14 = A1ADDR << (14 - CFG_ABITS);
	wire [13:0] B1ADDR_14 = B1ADDR << (14 - CFG_ABITS);
	wire [3:0] B1EN_4 = {4{B1EN}};

	wire [3:0] DIP, DOP;
	wire [31:0] DI, DO;

	wire [31:0] DOB;
	wire [3:0] DOPB;

	assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
	assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;

	generate if (CFG_DBITS > 8) begin
		RAMB16BWER #(
			.DATA_WIDTH_A(CFG_DBITS),
			.DATA_WIDTH_B(CFG_DBITS),
			.WRITE_MODE_A("READ_FIRST"),
			.WRITE_MODE_B("READ_FIRST"),
			`include "brams_init_18.vh"
		) _TECHMAP_REPLACE_ (
			.DIA(32'd0),
			.DIPA(4'd0),
			.DOA(DO[31:0]),
			.DOPA(DOP[3:0]),
			.ADDRA(A1ADDR_14),
			.CLKA(CLK2 ^ !CLKPOL2),
			.ENA(A1EN),
			.REGCEA(|1),
			.RSTA(|0),
			.WEA(4'b0),

			.DIB(DI),
			.DIPB(DIP),
			.DOB(DOB),
			.DOPB(DOPB),
			.ADDRB(B1ADDR_14),
			.CLKB(CLK3 ^ !CLKPOL3),
			.ENB(|1),
			.REGCEB(|0),
			.RSTB(|0),
			.WEB(B1EN_4)
		);
	end else begin
		RAMB16BWER #(
			.DATA_WIDTH_A(CFG_DBITS),
			.DATA_WIDTH_B(CFG_DBITS),
			.WRITE_MODE_A("READ_FIRST"),
			.WRITE_MODE_B("READ_FIRST"),
			`include "brams_init_16.vh"
		) _TECHMAP_REPLACE_ (
			.DIA(32'd0),
			.DIPA(4'd0),
			.DOA(DO[31:0]),
			.DOPA(DOP[3:0]),
			.ADDRA(A1ADDR_14),
			.CLKA(CLK2 ^ !CLKPOL2),
			.ENA(A1EN),
			.REGCEA(|1),
			.RSTA(|0),
			.WEA(4'b0),

			.DIB(DI),
			.DIPB(DIP),
			.DOB(DOB),
			.DOPB(DOPB),
			.ADDRB(B1ADDR_14),
			.CLKB(CLK3 ^ !CLKPOL3),
			.ENB(|1),
			.REGCEB(|0),
			.RSTB(|0),
			.WEB(B1EN_4)
		);
	end endgenerate
endmodule