data/full_repos/permissive/437204475/multicycle/cpu.v
1: b'%Error: data/full_repos/permissive/437204475/multicycle/cpu.v:3: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/437204475/multicycle,data/full_repos/permissive/437204475/defines.v\n             data/full_repos/permissive/437204475/multicycle,data/full_repos/permissive/437204475/defines.v.v\n             data/full_repos/permissive/437204475/multicycle,data/full_repos/permissive/437204475/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/437204475/multicycle/cpu.v:6: Define or directive not defined: \'`WORD_WIDTH\'\n    parameter W = `WORD_WIDTH\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/multicycle/cpu.v:7: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n) (\n^\n%Error: data/full_repos/permissive/437204475/multicycle/cpu.v:11: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire pc_clk, pc_en,\n    ^~~~~~\n%Error: data/full_repos/permissive/437204475/multicycle/cpu.v:12: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire[W-1:0] pc,\n ^~~~~~\n%Error: data/full_repos/permissive/437204475/multicycle/cpu.v:13: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[W-1:0] read_inst,\n ^~~~~\n%Error: data/full_repos/permissive/437204475/multicycle/cpu.v:15: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire load_clk, load_en,\n    ^~~~~~\n%Error: data/full_repos/permissive/437204475/multicycle/cpu.v:16: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire[W-1:0] l_addr,\n    ^~~~~~\n%Error: data/full_repos/permissive/437204475/multicycle/cpu.v:17: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[W-1:0] l_data,\n ^~~~~\n%Error: data/full_repos/permissive/437204475/multicycle/cpu.v:19: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire store_clk, store_en,\n ^~~~~~\n%Error: data/full_repos/permissive/437204475/multicycle/cpu.v:20: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire[W-1:0] s_addr,\n    ^~~~~~\n%Error: data/full_repos/permissive/437204475/multicycle/cpu.v:21: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire[W-1:0] s_data\n ^~~~~~\n%Error: data/full_repos/permissive/437204475/multicycle/cpu.v:22: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/437204475/multicycle/cpu.v:27: Define or directive not defined: \'`OP_WIDTH\'\n    wire[`OP_WIDTH-1:0] op_code;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/437204475/multicycle/cpu.v:28: Define or directive not defined: \'`FUNCT_WIDTH\'\n    wire[`FUNCT_WIDTH-1:0] funct;\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/multicycle/cpu.v:29: syntax error, unexpected IDENTIFIER\n    counter counter_inst(\n    ^~~~~~~\n%Error: data/full_repos/permissive/437204475/multicycle/cpu.v:49: syntax error, unexpected IDENTIFIER\n    pc_with_addr_mux pc_inst(\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/multicycle/cpu.v:68: Define or directive not defined: \'`REG_ADDR_W\'\n    wire[`REG_ADDR_W-1:0] rs_addr, rt_addr, rd_addr;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/multicycle/cpu.v:69: Define or directive not defined: \'`WORD_INDEX_W\'\n    wire[`WORD_INDEX_W-1:0] shamt;\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/multicycle/cpu.v:71: Define or directive not defined: \'`ALUOP_WIDTH\'\n    wire[`ALUOP_WIDTH-1:0] alu_op;\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/multicycle/cpu.v:72: Define or directive not defined: \'`ALU_SRC_WIDTH\'\n    wire[`ALU_SRC_WIDTH-1:0] alu_op1_src, alu_op2_src;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/multicycle/cpu.v:74: Define or directive not defined: \'`REG_W_SRC_WIDTH\'\n    wire[`REG_W_SRC_WIDTH-1:0] reg_write_src;\n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/multicycle/cpu.v:75: Define or directive not defined: \'`REG_ADDR_W\'\n    wire[`REG_ADDR_W-1:0] reg_write_addr;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/multicycle/cpu.v:77: Define or directive not defined: \'`L_S_MODE_W\'\n    wire[`L_S_MODE_W-1:0] l_s_mode;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/multicycle/cpu.v:79: syntax error, unexpected IDENTIFIER\n    decoder decoder_inst(\n    ^~~~~~~\n%Error: data/full_repos/permissive/437204475/multicycle/cpu.v:81: Define or directive not defined: \'`FALSE\'\n        .stall(`FALSE), .bubble(`FALSE),\n               ^~~~~~\n%Error: data/full_repos/permissive/437204475/multicycle/cpu.v:81: Define or directive not defined: \'`FALSE\'\n        .stall(`FALSE), .bubble(`FALSE),\n                                ^~~~~~\n%Error: data/full_repos/permissive/437204475/multicycle/cpu.v:108: syntax error, unexpected IDENTIFIER\n    regfile regfile_inst(\n    ^~~~~~~\n%Error: data/full_repos/permissive/437204475/multicycle/cpu.v:125: Define or directive not defined: \'`FALSE\'\n        .stall(`FALSE),\n               ^~~~~~\n%Error: data/full_repos/permissive/437204475/multicycle/cpu.v:136: syntax error, unexpected IDENTIFIER\n    mem mem_inst(\n    ^~~\n%Error: Exiting due to 30 error(s)\n'
module cpu #(
    parameter W = `WORD_WIDTH
) (

	input wire clk, rst,

    output wire pc_clk, pc_en,
	output wire[W-1:0] pc,
	input wire[W-1:0] read_inst,

    output wire load_clk, load_en,
    output wire[W-1:0] l_addr,
	input wire[W-1:0] l_data,

	output wire store_clk, store_en,
    output wire[W-1:0] s_addr,
	output wire[W-1:0] s_data
);



    wire if_clk, id_clk, ex_clk, mem_clk, wb_clk;
    wire[`OP_WIDTH-1:0] op_code;
    wire[`FUNCT_WIDTH-1:0] funct;
    counter counter_inst(
        .clk(clk), .rst(rst),
        .op_code(op_code), .funct(funct),

        .if_clk(if_clk),
        .id_clk(id_clk),
        .ex_clk(ex_clk),
        .mem_clk(mem_clk),
        .wb_clk(wb_clk),

        .inst_read_en(pc_en)
    );
    assign pc_clk = if_clk, load_clk = mem_clk, store_clk = mem_clk;




    wire can_branchm, jump, targ_else_offset, pc_addr_src_reg;
    wire[W-1:0] inst, rs_val, rt_val, rd_val, imm, alu_result;

    pc_with_addr_mux pc_inst(
        .clk(if_clk), .rst(rst),
        .can_branch(can_branch),
        .jump(jump),
        .branch_take(alu_result[0]),
        .targ_else_offset(targ_else_offset),

        .pc_addr_src_reg(pc_addr_src_reg),
        .rs_val(rs_val),
        .imm(imm),

        .pc(pc),
        .read_inst(read_inst),
        .inst(inst)
    );




    wire[`REG_ADDR_W-1:0] rs_addr, rt_addr, rd_addr;
    wire[`WORD_INDEX_W-1:0] shamt;

    wire[`ALUOP_WIDTH-1:0] alu_op;
    wire[`ALU_SRC_WIDTH-1:0] alu_op1_src, alu_op2_src;
    wire rs_read_en, rt_read_en, reg_write;
    wire[`REG_W_SRC_WIDTH-1:0] reg_write_src;
    wire[`REG_ADDR_W-1:0] reg_write_addr;
    wire mem_read_en, mem_write_en;
    wire[`L_S_MODE_W-1:0] l_s_mode;

    decoder decoder_inst(
        .clk(id_clk), .rst(rst),
        .stall(`FALSE), .bubble(`FALSE),
        .inst(inst),

        .op_code(op_code), .funct(funct),

        .rs(rs_addr), .rt(rt_addr),
        .imm(imm),
        .rd(rd_addr),
        .shamt(shamt),

        .alu_op(alu_op),
        .alu_op1_src(alu_op1_src),
        .alu_op2_src(alu_op2_src),
        .can_branch(can_branch),
        .jump(jump),
        .targ_else_offset(targ_else_offset),
        .pc_addr_src_reg(pc_addr_src_reg),
        .rs_read_en(rs_read_en), .rt_read_en(rt_read_en), .reg_write(reg_write),
        .reg_write_src(reg_write_src),
        .reg_write_addr(reg_write_addr),
        .mem_read_en(mem_read_en), .mem_write_en(mem_write_en),
        .l_s_mode(l_s_mode)
    );

    wire write_en;
    wire[W-1:0] reg_write_data;

    regfile regfile_inst(
        .clk(wb_clk), .rst(rst),
        .rs_en(rs_read_en),
        .rs_addr(rs_addr),
        .rs_data(rs_val),
        .rt_en(rt_read_en),
        .rt_addr(rt_addr),
        .rt_data(rt_val),
        .write_en(write_en),
        .write_addr(reg_write_addr),
        .write_data(reg_write_data)
    );



    alu_with_src_mux alu_inst(
        .clk(ex_clk),
        .stall(`FALSE),
        .alu_op1_src(alu_op1_src), .alu_op2_src(alu_op2_src),
        .rs_val(rs_val), .rt_val(rt_val), .imm(imm), .pc(pc),
        .alu_op(alu_op),
        .result(alu_result)
    );



    wire[W-1:0] mem_write_data, mem_read_data;

    mem mem_inst(
        .clk(mem_clk), .rst(rst),

        .mem_read_en(mem_read_en), .mem_write_en(mem_write_en),
        .mem_addr(alu_result),
        .l_s_mode(l_s_mode),
        .mem_write_data(rt_val), .mem_read_data(mem_read_data),

        .load_en(load_en),
        .l_addr(l_addr),
        .l_data(l_data),
        .store_en(store_en),
        .s_addr(s_addr),
        .s_data(s_data)
    );



    writeback wb_inst(
        .reg_write(reg_write),
        .alu_result(alu_result), .mem_data(mem_read_data), .pc(pc), .imm(imm),
        .reg_write_src(reg_write_src),

        .write_en(write_en),
        .reg_write_data(reg_write_data)
    );
    
endmodule
module cpu #(
    parameter W = `WORD_WIDTH
) (

	input wire clk, rst,

    output wire pc_clk, pc_en,
	output wire[W-1:0] pc,
	input wire[W-1:0] read_inst,

    output wire load_clk, load_en,
    output wire[W-1:0] l_addr,
	input wire[W-1:0] l_data,

	output wire store_clk, store_en,
    output wire[W-1:0] s_addr,
	output wire[W-1:0] s_data
);




    wire if_clk, id_clk, ex_clk, mem_clk, wb_clk;
    wire[`OP_WIDTH-1:0] op_code;
    wire[`FUNCT_WIDTH-1:0] funct;
    counter counter_inst(
        .clk(clk), .rst(rst),
        .op_code(op_code), .funct(funct),

        .if_clk(if_clk),
        .id_clk(id_clk),
        .ex_clk(ex_clk),
        .mem_clk(mem_clk),
        .wb_clk(wb_clk),

        .inst_read_en(pc_en)
    );
    assign pc_clk = if_clk, load_clk = mem_clk, store_clk = mem_clk;




    wire can_branchm, jump, targ_else_offset, pc_addr_src_reg;
    wire[W-1:0] inst, rs_val, rt_val, rd_val, imm, alu_result;

    pc_with_addr_mux pc_inst(
        .clk(if_clk), .rst(rst),
        .can_branch(can_branch),
        .jump(jump),
        .branch_take(alu_result[0]),
        .targ_else_offset(targ_else_offset),

        .pc_addr_src_reg(pc_addr_src_reg),
        .rs_val(rs_val),
        .imm(imm),

        .pc(pc),
        .read_inst(read_inst),
        .inst(inst)
    );




    wire[`REG_ADDR_W-1:0] rs_addr, rt_addr, rd_addr;
    wire[`WORD_INDEX_W-1:0] shamt;

    wire[`ALUOP_WIDTH-1:0] alu_op;
    wire[`ALU_SRC_WIDTH-1:0] alu_op1_src, alu_op2_src;
    wire rs_read_en, rt_read_en, reg_write;
    wire[`REG_W_SRC_WIDTH-1:0] reg_write_src;
    wire[`REG_ADDR_W-1:0] reg_write_addr;
    wire mem_read_en, mem_write_en;
    wire[`L_S_MODE_W-1:0] l_s_mode;

    decoder decoder_inst(
        .clk(id_clk), .rst(rst),
        .stall(`FALSE), .bubble(`FALSE),
        .inst(inst),

        .op_code(op_code), .funct(funct),

        .rs(rs_addr), .rt(rt_addr),
        .imm(imm),
        .rd(rd_addr),
        .shamt(shamt),

        .alu_op(alu_op),
        .alu_op1_src(alu_op1_src),
        .alu_op2_src(alu_op2_src),
        .can_branch(can_branch),
        .jump(jump),
        .targ_else_offset(targ_else_offset),
        .pc_addr_src_reg(pc_addr_src_reg),
        .rs_read_en(rs_read_en), .rt_read_en(rt_read_en), .reg_write(reg_write),
        .reg_write_src(reg_write_src),
        .reg_write_addr(reg_write_addr),
        .mem_read_en(mem_read_en), .mem_write_en(mem_write_en),
        .l_s_mode(l_s_mode)
    );

    wire write_en;
    wire[W-1:0] reg_write_data;

    regfile regfile_inst(
        .clk(wb_clk), .rst(rst),
        .rs_en(rs_read_en),
        .rs_addr(rs_addr),
        .rs_data(rs_val),
        .rt_en(rt_read_en),
        .rt_addr(rt_addr),
        .rt_data(rt_val),
        .write_en(write_en),
        .write_addr(reg_write_addr),
        .write_data(reg_write_data)
    );



    alu_with_src_mux alu_inst(
        .clk(ex_clk),
        .stall(`FALSE),
        .alu_op1_src(alu_op1_src), .alu_op2_src(alu_op2_src),
        .rs_val(rs_val), .rt_val(rt_val), .imm(imm), .pc(pc),
        .alu_op(alu_op),
        .result(alu_result)
    );



    wire[W-1:0] mem_write_data, mem_read_data;

    mem mem_inst(
        .clk(mem_clk), .rst(rst),

        .mem_read_en(mem_read_en), .mem_write_en(mem_write_en),
        .mem_addr(alu_result),
        .l_s_mode(l_s_mode),
        .mem_write_data(rt_val), .mem_read_data(mem_read_data),

        .load_en(load_en),
        .l_addr(l_addr),
        .l_data(l_data),
        .store_en(store_en),
        .s_addr(s_addr),
        .s_data(s_data)
    );



    writeback wb_inst(
        .reg_write(reg_write),
        .alu_result(alu_result), .mem_data(mem_read_data), .pc(pc), .imm(imm),
        .reg_write_src(reg_write_src),

        .write_en(write_en),
        .reg_write_data(reg_write_data)
    );
    
endmodule