data/full_repos/permissive/427221126/src/ReLU.v
data/verilator_xmls/39bbb914-bc9c-47b8-8ef3-f61779ce4ae1.xml
module ReLU
  #(
    parameter INWIDTH = 16,
    parameter signed [INWIDTH-1:0] ZERO = 'sh0000
  )
  (
    input                       CLK     ,
    input                       RESET   ,
    input                       EN      ,
    input  signed [INWIDTH-1:0] X       ,
    input                       X_VLD   ,
    output signed [INWIDTH-1:0] Y       ,
    output                      Y_VLD   ,
    output signed [INWIDTH-1:0] PASSTHRU 
  );
  reg signed [INWIDTH-1:0] din;
  reg                      din_valid;
  reg signed [INWIDTH-1:0] dout;
  reg                      dout_valid;

  reg  signed [INWIDTH-1:0] din_d;
  reg  signed [INWIDTH-1:0] din_dd;


  always @(posedge CLK) begin
    if (RESET) begin
      din <= 0;
      dout <= 0;
      din_valid <= 0;
      dout_valid <= 0;
    end else if (EN) begin
      if (X_VLD) begin
        din <= X;
        din_valid = 1;
      end
      else begin
        din <= din;
        din_valid <= 0;
      end
      if (din_valid) begin
        dout <= (din > ZERO) ? din : ZERO;
        dout_valid <= 1;
      end
      else begin
        dout <= dout;
        dout_valid <= 0;
      end
    end
  end

  always @(posedge CLK) begin
    if (RESET == 1'b1) begin
      din_d  <= {INWIDTH{1'b0}};
      din_dd <= {INWIDTH{1'b0}};
    end
    else if (EN) begin
      din_d  <= X;
      din_dd <= din_d;
    end
  end

  assign Y = dout;
  assign Y_VLD = dout_valid;
  assign PASSTHRU = din_dd;
endmodule
module ReLU
  #(
    parameter INWIDTH = 16,
    parameter signed [INWIDTH-1:0] ZERO = 'sh0000
  )
  (
    input                       CLK     ,
    input                       RESET   ,
    input                       EN      ,
    input  signed [INWIDTH-1:0] X       ,
    input                       X_VLD   ,
    output signed [INWIDTH-1:0] Y       ,
    output                      Y_VLD   ,
    output signed [INWIDTH-1:0] PASSTHRU 
  );

  reg signed [INWIDTH-1:0] din;
  reg                      din_valid;
  reg signed [INWIDTH-1:0] dout;
  reg                      dout_valid;

  reg  signed [INWIDTH-1:0] din_d;
  reg  signed [INWIDTH-1:0] din_dd;


  always @(posedge CLK) begin
    if (RESET) begin
      din <= 0;
      dout <= 0;
      din_valid <= 0;
      dout_valid <= 0;
    end else if (EN) begin
      if (X_VLD) begin
        din <= X;
        din_valid = 1;
      end
      else begin
        din <= din;
        din_valid <= 0;
      end
      if (din_valid) begin
        dout <= (din > ZERO) ? din : ZERO;
        dout_valid <= 1;
      end
      else begin
        dout <= dout;
        dout_valid <= 0;
      end
    end
  end

  always @(posedge CLK) begin
    if (RESET == 1'b1) begin
      din_d  <= {INWIDTH{1'b0}};
      din_dd <= {INWIDTH{1'b0}};
    end
    else if (EN) begin
      din_d  <= X;
      din_dd <= din_d;
    end
  end

  assign Y = dout;
  assign Y_VLD = dout_valid;
  assign PASSTHRU = din_dd;
endmodule