data/full_repos/permissive/418749135/jk_ff.v
1: b"%Error: data/full_repos/permissive/418749135/jk_ff.v:6: Duplicate declaration of signal: 'q'\n                                                      : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n   reg q;\n       ^\n        data/full_repos/permissive/418749135/jk_ff.v:4: ... Location of original declaration\n               output q);\n                      ^\n%Error: Exiting due to 1 error(s)\n"
module jk_ff ( input j,
               input k,
               input clk,
               output q);

   reg q;

   always @ (posedge clk)
      case ({j,k})
         2'b00 :  q <= q;
         2'b01 :  q <= 0;
         2'b10 :  q <= 1;
         2'b11 :  q <= ~q;
      endcase
endmodule
module jk_ff ( input j,
               input k,
               input clk,
               output q);


   reg q;

   always @ (posedge clk)
      case ({j,k})
         2'b00 :  q <= q;
         2'b01 :  q <= 0;
         2'b10 :  q <= 1;
         2'b11 :  q <= ~q;
      endcase
endmodule