data/full_repos/permissive/423412549/src/rtl/disp_ctrl.v
1: b'%Error: data/full_repos/permissive/423412549/src/rtl/disp_ctrl.v:9: Cannot find include file: ../header/define.v\n`include "../header/define.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423412549/src/rtl,data/full_repos/permissive/423412549/../header/define.v\n             data/full_repos/permissive/423412549/src/rtl,data/full_repos/permissive/423412549/../header/define.v.v\n             data/full_repos/permissive/423412549/src/rtl,data/full_repos/permissive/423412549/../header/define.v.sv\n             ../header/define.v\n             ../header/define.v.v\n             ../header/define.v.sv\n             obj_dir/../header/define.v\n             obj_dir/../header/define.v.v\n             obj_dir/../header/define.v.sv\n%Error: data/full_repos/permissive/423412549/src/rtl/disp_ctrl.v:16: Define or directive not defined: \'`COLOR_RGB_DEPTH\'\n        input  wire  [`COLOR_RGB_DEPTH-1:0] me_rgb_i,\n                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/disp_ctrl.v:18: Define or directive not defined: \'`COLOR_RGB_DEPTH\'\n        input  wire  [`COLOR_RGB_DEPTH-1:0] bullet_rgb_i,\n                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/disp_ctrl.v:20: Define or directive not defined: \'`COLOR_RGB_DEPTH\'\n        input  wire  [`COLOR_RGB_DEPTH-1:0] enemy_rgb_i,\n                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/disp_ctrl.v:22: Define or directive not defined: \'`COLOR_RGB_DEPTH\'\n        input  wire  [`COLOR_RGB_DEPTH-1:0] bonus_rgb_i,\n                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/disp_ctrl.v:26: Define or directive not defined: \'`H_DISP_LEN\'\n        output wire  [     `H_DISP_LEN-1:0] req_x_addr_o,\n                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/disp_ctrl.v:27: Define or directive not defined: \'`V_DISP_LEN\'\n        output wire  [     `V_DISP_LEN-1:0] req_y_addr_o,\n                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/disp_ctrl.v:28: Define or directive not defined: \'`COLOR_R_DEPTH\'\n        output wire  [  `COLOR_R_DEPTH-1:0] vga_r_o,\n                        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/disp_ctrl.v:29: Define or directive not defined: \'`COLOR_G_DEPTH\'\n        output wire  [  `COLOR_G_DEPTH-1:0] vga_g_o,\n                        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/disp_ctrl.v:30: Define or directive not defined: \'`COLOR_B_DEPTH\'\n        output wire  [  `COLOR_B_DEPTH-1:0] vga_b_o,\n                        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/disp_ctrl.v:36: Define or directive not defined: \'`COLOR_RGB_DEPTH\'\n    reg  [`COLOR_RGB_DEPTH-1:0] vga_rgb;\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/disp_ctrl.v:72: Define or directive not defined: \'`BG_COLOR_R\'\n                    vga_rgb <= {`BG_COLOR_R, `BG_COLOR_G, `BG_COLOR_B};\n                                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/disp_ctrl.v:72: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                    vga_rgb <= {`BG_COLOR_R, `BG_COLOR_G, `BG_COLOR_B};\n                                           ^\n%Error: data/full_repos/permissive/423412549/src/rtl/disp_ctrl.v:72: Define or directive not defined: \'`BG_COLOR_G\'\n                    vga_rgb <= {`BG_COLOR_R, `BG_COLOR_G, `BG_COLOR_B};\n                                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/disp_ctrl.v:72: Define or directive not defined: \'`BG_COLOR_B\'\n                    vga_rgb <= {`BG_COLOR_R, `BG_COLOR_G, `BG_COLOR_B};\n                                                          ^~~~~~~~~~~\n%Error: Exiting due to 15 error(s)\n'
module disp_ctrl (
        input  wire                         clk_vga,
        input  wire                         clk_run,
        input  wire                         rst,

        input  wire  [`COLOR_RGB_DEPTH-1:0] me_rgb_i,
        input  wire                         me_alpha_i,
        input  wire  [`COLOR_RGB_DEPTH-1:0] bullet_rgb_i,
        input  wire                         bullet_alpha_i,
        input  wire  [`COLOR_RGB_DEPTH-1:0] enemy_rgb_i,
        input  wire                         enemy_alpha_i,
        input  wire  [`COLOR_RGB_DEPTH-1:0] bonus_rgb_i,
        input  wire                         bonus_alpha_i,
        input  wire                         info_alpha_i,

        output wire  [     `H_DISP_LEN-1:0] req_x_addr_o,
        output wire  [     `V_DISP_LEN-1:0] req_y_addr_o,
        output wire  [  `COLOR_R_DEPTH-1:0] vga_r_o,
        output wire  [  `COLOR_G_DEPTH-1:0] vga_g_o,
        output wire  [  `COLOR_B_DEPTH-1:0] vga_b_o,
        output wire                         h_sync_o,
        output wire                         v_sync_o,
        output wire                         disp_o
    );

    reg  [`COLOR_RGB_DEPTH-1:0] vga_rgb;
    assign {vga_r_o, vga_g_o, vga_b_o} = vga_rgb;

    dri_vga dri_vga_dut(
                .clk(clk_vga),
                .rst(rst),
                .en_i(1'b1),
                .h_sync_o(h_sync_o),
                .v_sync_o(v_sync_o),
                .disp_o(disp_o),
                .req_x_addr_o(req_x_addr_o),
                .req_y_addr_o(req_y_addr_o)
            );

    always @(posedge clk_vga or posedge rst) begin
        if(rst) begin
            vga_rgb <= 12'b0;
        end
        else begin
            if(disp_o) begin
                if(bullet_alpha_i) begin
                    vga_rgb <= bullet_rgb_i;
                end
                else if(enemy_alpha_i) begin
                    vga_rgb <= enemy_rgb_i;
                end
                else if(bonus_alpha_i) begin
                    vga_rgb <= bonus_rgb_i;
                end
                else if(info_alpha_i) begin
                    vga_rgb <= 12'hf00;
                end
                else if(me_alpha_i) begin
                    vga_rgb <= me_rgb_i;
                end
                else begin
                    vga_rgb <= {`BG_COLOR_R, `BG_COLOR_G, `BG_COLOR_B};
                end
            end
            else begin
                vga_rgb <= 12'b0;
            end
        end
    end
endmodule
module disp_ctrl (
        input  wire                         clk_vga,
        input  wire                         clk_run,
        input  wire                         rst,

        input  wire  [`COLOR_RGB_DEPTH-1:0] me_rgb_i,
        input  wire                         me_alpha_i,
        input  wire  [`COLOR_RGB_DEPTH-1:0] bullet_rgb_i,
        input  wire                         bullet_alpha_i,
        input  wire  [`COLOR_RGB_DEPTH-1:0] enemy_rgb_i,
        input  wire                         enemy_alpha_i,
        input  wire  [`COLOR_RGB_DEPTH-1:0] bonus_rgb_i,
        input  wire                         bonus_alpha_i,
        input  wire                         info_alpha_i,

        output wire  [     `H_DISP_LEN-1:0] req_x_addr_o,
        output wire  [     `V_DISP_LEN-1:0] req_y_addr_o,
        output wire  [  `COLOR_R_DEPTH-1:0] vga_r_o,
        output wire  [  `COLOR_G_DEPTH-1:0] vga_g_o,
        output wire  [  `COLOR_B_DEPTH-1:0] vga_b_o,
        output wire                         h_sync_o,
        output wire                         v_sync_o,
        output wire                         disp_o
    );


    reg  [`COLOR_RGB_DEPTH-1:0] vga_rgb;
    assign {vga_r_o, vga_g_o, vga_b_o} = vga_rgb;

    dri_vga dri_vga_dut(
                .clk(clk_vga),
                .rst(rst),
                .en_i(1'b1),
                .h_sync_o(h_sync_o),
                .v_sync_o(v_sync_o),
                .disp_o(disp_o),
                .req_x_addr_o(req_x_addr_o),
                .req_y_addr_o(req_y_addr_o)
            );

    always @(posedge clk_vga or posedge rst) begin
        if(rst) begin
            vga_rgb <= 12'b0;
        end
        else begin
            if(disp_o) begin
                if(bullet_alpha_i) begin
                    vga_rgb <= bullet_rgb_i;
                end
                else if(enemy_alpha_i) begin
                    vga_rgb <= enemy_rgb_i;
                end
                else if(bonus_alpha_i) begin
                    vga_rgb <= bonus_rgb_i;
                end
                else if(info_alpha_i) begin
                    vga_rgb <= 12'hf00;
                end
                else if(me_alpha_i) begin
                    vga_rgb <= me_rgb_i;
                end
                else begin
                    vga_rgb <= {`BG_COLOR_R, `BG_COLOR_G, `BG_COLOR_B};
                end
            end
            else begin
                vga_rgb <= 12'b0;
            end
        end
    end
endmodule