data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_iodll_code_adjust.v
1: b'%Warning-CMPCONST: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_iodll_code_adjust.v:124: Comparison is constant due to limited range\n                                                                                                           : ... In instance bw_iodll_code_adjust\n       if ( s_interim_out <= 5\'b11111 && s_interim_out >= 5\'b10100 )\n                          ^~\n                   ... Use "/* verilator lint_off CMPCONST */" and lint_on around source to disable this message.\n%Warning-CMPCONST: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_iodll_code_adjust.v:162: Comparison is constant due to limited range\n                                                                                                           : ... In instance bw_iodll_code_adjust\n       if ( s_interim_out <= 5\'b11111 && s_interim_out >= 5\'b11000 )\n                          ^~\n%Warning-CMPCONST: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_iodll_code_adjust.v:248: Comparison is constant due to limited range\n                                                                                                           : ... In instance bw_iodll_code_adjust\n                                                        if ( s_interim_out <= 5\'b11111 && s_interim_out >= 5\'b11010 )\n                                                                           ^~\n%Error: Exiting due to 3 warning(s)\n'
module bw_iodll_code_adjust (

         s_percent_ctrl_out, so,

        bypass_data, ddr_clk_in, delay_ctrl, io_dll_bypass_l, iodll_reset_l, s_controller_out, se, si
        );

	input [4:0]	bypass_data;
        input           ddr_clk_in;
        input [2:0]     delay_ctrl;
        input		io_dll_bypass_l;
        input           iodll_reset_l;
        input [4:0]     s_controller_out;
        input           se;
        input           si;

        output [4:0]    s_percent_ctrl_out;
        output          so;

        reg    [4:0]    s_percent_ctrl_out;
        reg    [4:0]    s_interim_out;		


always @(posedge ddr_clk_in or negedge iodll_reset_l)
begin

	if(~iodll_reset_l) 
        begin

 		s_percent_ctrl_out = 5'b00000;
                s_interim_out = 5'b00000;
        end
	else
	if(~io_dll_bypass_l)

		s_percent_ctrl_out = bypass_data;

	else
        begin
		if(bypass_data[0] == 1'b1)
		begin

                	case(delay_ctrl)  
                                        3'b111 : begin








                                                        if (s_controller_out == 5'b11111)
                                                                s_interim_out = s_controller_out - 5'b00001;
                                                        else 
							if (s_controller_out == 5'b00000)

								s_interim_out = s_controller_out;
							else
                                                                s_interim_out = s_controller_out - 5'b00011;



							
							if ( s_interim_out == 5'b00000 || s_interim_out == 5'b00001 )	
 								s_percent_ctrl_out = s_interim_out;
							else
								s_percent_ctrl_out = s_interim_out - 5'b00001;
                                                 end

					3'b110 : begin
							








							if (s_controller_out == 5'b11111)
                                                                s_interim_out = s_controller_out - 5'b00001;
							else
                                                        if (s_controller_out == 5'b00000)

                                                                s_interim_out = s_controller_out;
                                                        else    
								s_interim_out = s_controller_out - 5'b00010;

        




							
							if ( s_interim_out <= 5'b11111 && s_interim_out >= 5'b10100 )
								s_percent_ctrl_out = s_interim_out - 5'b00011;
							else
							if( s_interim_out <= 5'b10011 && s_interim_out >= 5'b01001)
								s_percent_ctrl_out = s_interim_out - 5'b00010;
							else
							if( s_interim_out <= 5'b01000 && s_interim_out >= 5'b00001 )
								s_percent_ctrl_out = s_interim_out - 5'b00001;
							else
								s_percent_ctrl_out = s_interim_out;
						 end

        				3'b101 : begin








                                                        
                                                        if (s_controller_out == 5'b00000)

                                                                s_interim_out = s_controller_out;
                                                        else
								s_interim_out = s_controller_out - 5'b00001;











							if ( s_interim_out <= 5'b11111 && s_interim_out >= 5'b11000 )
                                                                s_percent_ctrl_out = s_interim_out - 5'b00110;
                                                        else
                                                        if ( s_interim_out <= 5'b10111 && s_interim_out >= 5'b10001 )
                                                                s_percent_ctrl_out = s_interim_out - 5'b00101;
                                                        else
                                                        if ( s_interim_out <= 5'b10000 && s_interim_out >= 5'b01100 )
                                                                s_percent_ctrl_out = s_interim_out - 5'b00100;
                                                        else
                                                        if ( s_interim_out <= 5'b01011 && s_interim_out >= 5'b00110 )
                                                                s_percent_ctrl_out = s_interim_out - 5'b00011;
                                                        else
                                                        if ( s_interim_out <= 5'b00101 && s_interim_out >= 5'b00010 ) 
                                                                s_percent_ctrl_out = s_interim_out - 5'b00010;
                                                        else
							if ( s_interim_out == 5'b00001 )
								s_percent_ctrl_out = s_interim_out - 5'b00001;
							else
                                                        if ( s_interim_out == 5'b00000 )
                                                                s_percent_ctrl_out = s_interim_out;
                                                 end

					3'b100 : begin

							
							s_interim_out = s_controller_out;							

							s_percent_ctrl_out = s_interim_out; 
                                        
                                                 end
					
					3'b011 : begin



                                                        if(s_controller_out == 5'b00000 || s_controller_out == 5'b11111) 

                                                                s_interim_out = s_controller_out;
                                                        else
                                                                s_interim_out = s_controller_out + 5'b00001;

            


                                                        if ( s_interim_out == 5'b00000 || s_interim_out == 5'b00001 || s_interim_out == 5'b11111 )
                                                                s_percent_ctrl_out = s_interim_out;
							else
								s_percent_ctrl_out = s_interim_out + 5'b00001;

						 end

					3'b010 : begin



                                                        s_interim_out = s_controller_out;                                                 
                                                        
                                                        s_percent_ctrl_out = s_interim_out;

                                                 end

                                        3'b001 : begin



                                                        s_interim_out = s_controller_out;                                                  
                                                        
                                                        s_percent_ctrl_out = s_interim_out;
                                                        
                                                 end    

					3'b000 : begin


                                                        
                                                                s_interim_out = s_controller_out;


                                                        






                                                        
                                                        if ( s_interim_out <= 5'b11111 && s_interim_out >= 5'b11010 )
                                                                s_percent_ctrl_out = s_interim_out - 5'b00101;
                                                        else
                                                        if ( s_interim_out <= 5'b11001 && s_interim_out >= 5'b10011 )
                                                                s_percent_ctrl_out = s_interim_out - 5'b00100;
                                                        else
                                                        if ( s_interim_out <= 5'b10010 && s_interim_out >= 5'b01011 )
                                                                s_percent_ctrl_out = s_interim_out - 5'b00011;
                                                        else
                                                        if ( s_interim_out <= 5'b01010 && s_interim_out >= 5'b00010 )
                                                                s_percent_ctrl_out = s_interim_out - 5'b00010;
                                                        else
                                                        if ( s_interim_out == 5'b00001 )
                                                                s_percent_ctrl_out = s_interim_out - 5'b00001;
                                                        else
                                                        if ( s_interim_out == 5'b00000 )   
                                                                s_percent_ctrl_out = s_interim_out;
						
						 end				
			endcase			
	
		end
        	else
        	if(bypass_data[0] == 1'b0)

			s_percent_ctrl_out = s_controller_out;

	end


end

endmodule
module bw_iodll_code_adjust (

         s_percent_ctrl_out, so,

        bypass_data, ddr_clk_in, delay_ctrl, io_dll_bypass_l, iodll_reset_l, s_controller_out, se, si
        );


	input [4:0]	bypass_data;
        input           ddr_clk_in;
        input [2:0]     delay_ctrl;
        input		io_dll_bypass_l;
        input           iodll_reset_l;
        input [4:0]     s_controller_out;
        input           se;
        input           si;

        output [4:0]    s_percent_ctrl_out;
        output          so;

        reg    [4:0]    s_percent_ctrl_out;
        reg    [4:0]    s_interim_out;		


always @(posedge ddr_clk_in or negedge iodll_reset_l)
begin

	if(~iodll_reset_l) 
        begin

 		s_percent_ctrl_out = 5'b00000;
                s_interim_out = 5'b00000;
        end
	else
	if(~io_dll_bypass_l)

		s_percent_ctrl_out = bypass_data;

	else
        begin
		if(bypass_data[0] == 1'b1)
		begin

                	case(delay_ctrl)  
                                        3'b111 : begin








                                                        if (s_controller_out == 5'b11111)
                                                                s_interim_out = s_controller_out - 5'b00001;
                                                        else 
							if (s_controller_out == 5'b00000)

								s_interim_out = s_controller_out;
							else
                                                                s_interim_out = s_controller_out - 5'b00011;



							
							if ( s_interim_out == 5'b00000 || s_interim_out == 5'b00001 )	
 								s_percent_ctrl_out = s_interim_out;
							else
								s_percent_ctrl_out = s_interim_out - 5'b00001;
                                                 end

					3'b110 : begin
							








							if (s_controller_out == 5'b11111)
                                                                s_interim_out = s_controller_out - 5'b00001;
							else
                                                        if (s_controller_out == 5'b00000)

                                                                s_interim_out = s_controller_out;
                                                        else    
								s_interim_out = s_controller_out - 5'b00010;

        




							
							if ( s_interim_out <= 5'b11111 && s_interim_out >= 5'b10100 )
								s_percent_ctrl_out = s_interim_out - 5'b00011;
							else
							if( s_interim_out <= 5'b10011 && s_interim_out >= 5'b01001)
								s_percent_ctrl_out = s_interim_out - 5'b00010;
							else
							if( s_interim_out <= 5'b01000 && s_interim_out >= 5'b00001 )
								s_percent_ctrl_out = s_interim_out - 5'b00001;
							else
								s_percent_ctrl_out = s_interim_out;
						 end

        				3'b101 : begin








                                                        
                                                        if (s_controller_out == 5'b00000)

                                                                s_interim_out = s_controller_out;
                                                        else
								s_interim_out = s_controller_out - 5'b00001;











							if ( s_interim_out <= 5'b11111 && s_interim_out >= 5'b11000 )
                                                                s_percent_ctrl_out = s_interim_out - 5'b00110;
                                                        else
                                                        if ( s_interim_out <= 5'b10111 && s_interim_out >= 5'b10001 )
                                                                s_percent_ctrl_out = s_interim_out - 5'b00101;
                                                        else
                                                        if ( s_interim_out <= 5'b10000 && s_interim_out >= 5'b01100 )
                                                                s_percent_ctrl_out = s_interim_out - 5'b00100;
                                                        else
                                                        if ( s_interim_out <= 5'b01011 && s_interim_out >= 5'b00110 )
                                                                s_percent_ctrl_out = s_interim_out - 5'b00011;
                                                        else
                                                        if ( s_interim_out <= 5'b00101 && s_interim_out >= 5'b00010 ) 
                                                                s_percent_ctrl_out = s_interim_out - 5'b00010;
                                                        else
							if ( s_interim_out == 5'b00001 )
								s_percent_ctrl_out = s_interim_out - 5'b00001;
							else
                                                        if ( s_interim_out == 5'b00000 )
                                                                s_percent_ctrl_out = s_interim_out;
                                                 end

					3'b100 : begin

							
							s_interim_out = s_controller_out;							

							s_percent_ctrl_out = s_interim_out; 
                                        
                                                 end
					
					3'b011 : begin



                                                        if(s_controller_out == 5'b00000 || s_controller_out == 5'b11111) 

                                                                s_interim_out = s_controller_out;
                                                        else
                                                                s_interim_out = s_controller_out + 5'b00001;

            


                                                        if ( s_interim_out == 5'b00000 || s_interim_out == 5'b00001 || s_interim_out == 5'b11111 )
                                                                s_percent_ctrl_out = s_interim_out;
							else
								s_percent_ctrl_out = s_interim_out + 5'b00001;

						 end

					3'b010 : begin



                                                        s_interim_out = s_controller_out;                                                 
                                                        
                                                        s_percent_ctrl_out = s_interim_out;

                                                 end

                                        3'b001 : begin



                                                        s_interim_out = s_controller_out;                                                  
                                                        
                                                        s_percent_ctrl_out = s_interim_out;
                                                        
                                                 end    

					3'b000 : begin


                                                        
                                                                s_interim_out = s_controller_out;


                                                        






                                                        
                                                        if ( s_interim_out <= 5'b11111 && s_interim_out >= 5'b11010 )
                                                                s_percent_ctrl_out = s_interim_out - 5'b00101;
                                                        else
                                                        if ( s_interim_out <= 5'b11001 && s_interim_out >= 5'b10011 )
                                                                s_percent_ctrl_out = s_interim_out - 5'b00100;
                                                        else
                                                        if ( s_interim_out <= 5'b10010 && s_interim_out >= 5'b01011 )
                                                                s_percent_ctrl_out = s_interim_out - 5'b00011;
                                                        else
                                                        if ( s_interim_out <= 5'b01010 && s_interim_out >= 5'b00010 )
                                                                s_percent_ctrl_out = s_interim_out - 5'b00010;
                                                        else
                                                        if ( s_interim_out == 5'b00001 )
                                                                s_percent_ctrl_out = s_interim_out - 5'b00001;
                                                        else
                                                        if ( s_interim_out == 5'b00000 )   
                                                                s_percent_ctrl_out = s_interim_out;
						
						 end				
			endcase			
	
		end
        	else
        	if(bypass_data[0] == 1'b0)

			s_percent_ctrl_out = s_controller_out;

	end


end

endmodule