data/full_repos/permissive/509098780/Design_Part4.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/509098780/Design_Part4.v:24: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'signal'\n                                                                          : ... In instance top_module.B\n            signal=0;\n            ^~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/509098780/Design_Part4.v:34: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'signal'\n                                                                          : ... In instance top_module.B\n            signal=0;\n            ^~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/509098780/Design_Part4.v:44: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'signal'\n                                                                          : ... In instance top_module.B\n            signal=1;\n            ^~~~~~\n%Error-PROCASSWIRE: data/full_repos/permissive/509098780/Design_Part4.v:50: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'signal'\n                                                                          : ... In instance top_module.B\n            signal=1;\n            ^~~~~~\n%Error: Exiting due to 4 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module counter (

    input clk,

    input reset,

    input areset,

    output signal);

    reg [5:0] count;
  
  

    always@(posedge clk)begin
      

        if(areset || (reset && count<6'd19) )

            begin

            count=6'd0;

            signal=0;

            end

        else if(~reset && count<6'd19)

            begin

            count++;

            signal=0;

            end

        else if(reset && count>=6'd19)

            begin

            count=6'd0;

            signal=1;

            end

        else

            signal=1;

            

    end

endmodule
module counter (

    input clk,

    input reset,

    input areset,

    output signal);


    reg [5:0] count;
  
  

    always@(posedge clk)begin
      

        if(areset || (reset && count<6'd19) )

            begin

            count=6'd0;

            signal=0;

            end

        else if(~reset && count<6'd19)

            begin

            count++;

            signal=0;

            end

        else if(reset && count>=6'd19)

            begin

            count=6'd0;

            signal=1;

            end

        else

            signal=1;

            

    end

endmodule