data/full_repos/permissive/501535128/alu.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/501535128/alu.v:23: Unsupported: Ignoring delay on this delayed statement.\n#2 a=4\'b0001;b=4\'b0011;s=2\'b00;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/501535128/alu.v:24: Unsupported: Ignoring delay on this delayed statement.\n#2 a=4\'b0011;b=4\'b0001;s=2\'b01;\n^\n%Warning-STMTDLY: data/full_repos/permissive/501535128/alu.v:25: Unsupported: Ignoring delay on this delayed statement.\n#2 a=4\'b0100;b=4\'b0010;s=2\'b10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/501535128/alu.v:26: Unsupported: Ignoring delay on this delayed statement.\n#2 a=4\'b0010;b=4\'b0001;s=2\'b11;\n^\n%Warning-STMTDLY: data/full_repos/permissive/501535128/alu.v:27: Unsupported: Ignoring delay on this delayed statement.\n#50 $stop;\n^\n%Warning-WIDTH: data/full_repos/permissive/501535128/alu.v:8: Operator ADD expects 8 bits on the LHS, but LHS\'s VARREF \'a\' generates 4 bits.\n                                                            : ... In instance alutb.a1\n2\'b00:y=a+b;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/501535128/alu.v:8: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n                                                            : ... In instance alutb.a1\n2\'b00:y=a+b;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/501535128/alu.v:9: Operator SUB expects 8 bits on the LHS, but LHS\'s VARREF \'a\' generates 4 bits.\n                                                            : ... In instance alutb.a1\n2\'b01:y=a-b;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/501535128/alu.v:9: Operator SUB expects 8 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n                                                            : ... In instance alutb.a1\n2\'b01:y=a-b;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/501535128/alu.v:11: Operator DIV expects 8 bits on the LHS, but LHS\'s VARREF \'a\' generates 4 bits.\n                                                             : ... In instance alutb.a1\n2\'b11:y=a/b;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/501535128/alu.v:11: Operator DIV expects 8 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n                                                             : ... In instance alutb.a1\n2\'b11:y=a/b;\n         ^\n%Error: Exiting due to 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alutb();
reg[3:0]a,b;
reg[1:0]s;
wire[7:0]y;
alu a1(a,b,s,y);
initial
begin
#2 a=4'b0001;b=4'b0011;s=2'b00;
#2 a=4'b0011;b=4'b0001;s=2'b01;
#2 a=4'b0100;b=4'b0010;s=2'b10;
#2 a=4'b0010;b=4'b0001;s=2'b11;
#50 $stop;
end
endmodule
module alutb();

reg[3:0]a,b;
reg[1:0]s;
wire[7:0]y;
alu a1(a,b,s,y);
initial
begin
#2 a=4'b0001;b=4'b0011;s=2'b00;
#2 a=4'b0011;b=4'b0001;s=2'b01;
#2 a=4'b0100;b=4'b0010;s=2'b10;
#2 a=4'b0010;b=4'b0001;s=2'b11;
#50 $stop;
end
endmodule