data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:169: Signal definition not found, creating implicitly: \'scr0_buf_we\'\n                                                                                                  : ... Suggested alternative: \'scr0_buf_addr\'\n    .BUF_WE(scr0_buf_we),\n            ^~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:200: Signal definition not found, creating implicitly: \'scr1_buf_we\'\n                                                                                                  : ... Suggested alternative: \'scr0_buf_we\'\n    .BUF_WE(scr1_buf_we),\n            ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:231: Signal definition not found, creating implicitly: \'scr2_buf_we\'\n                                                                                                  : ... Suggested alternative: \'scr0_buf_we\'\n    .BUF_WE(scr2_buf_we),\n            ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:341: Operator SHIFTR expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'SCROLL_Y_POS\' generates 13 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\nwire [15:0] row = (((SCROLL_Y_POS >> 4) + y) << 6) & \'h7C0;\n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:341: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'y\' generates 9 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\nwire [15:0] row = (((SCROLL_Y_POS >> 4) + y) << 6) & \'h7C0;\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:342: Operator SHIFTR expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'SCROLL_X_POS\' generates 13 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\nwire [15:0] column = ((((SCROLL_X_POS >> 4) + x) << 1) & \'h3E);\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:342: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'x\' generates 9 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\nwire [15:0] column = ((((SCROLL_X_POS >> 4) + x) << 1) & \'h3E);\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:354: Operator ASSIGNW expects 14 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 16 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\nwire [13:0] rd_scr_q_addr = (priority_i*21) + scr_queue_i;\n                          ^\n%Error: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:363: Cannot find file containing module: \'jtframe_dual_ram\'\njtframe_dual_ram #(.dw(64), .aw(9)) u_scr_pri_q(\n^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/525423410/modules/raizing_video,data/full_repos/permissive/525423410/jtframe_dual_ram\n             data/full_repos/permissive/525423410/modules/raizing_video,data/full_repos/permissive/525423410/jtframe_dual_ram.v\n             data/full_repos/permissive/525423410/modules/raizing_video,data/full_repos/permissive/525423410/jtframe_dual_ram.sv\n             jtframe_dual_ram\n             jtframe_dual_ram.v\n             jtframe_dual_ram.sv\n             obj_dir/jtframe_dual_ram\n             obj_dir/jtframe_dual_ram.v\n             obj_dir/jtframe_dual_ram.sv\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:380: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\nwire [15:0] tile_num_attr = scr_q_out[63:32];\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:381: Operator ASSIGNW expects 12 bits on the Assign RHS, but Assign RHS\'s AND generates 32 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\nwire [11:0] tile_palette = ((scr_q_out[63:32] >> 12 ) & \'h07F0);\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:387: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s AND generates 32 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\nwire [3:0] tile_code = (((tile_line >> (tx*4)) & \'h0F));\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:388: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'tx\' generates 3 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\nwire [9:0] buf_code = (tile_x_pos + (8 * scr_x_render) + tx);\n                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:388: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 16 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\nwire [9:0] buf_code = (tile_x_pos + (8 * scr_x_render) + tx);\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:390: Operator ADD expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'VRENDER\' generates 9 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\nwire [15:0] lines_down = VRENDER + (SCROLL_Y_POS & 15);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:390: Operator AND expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'SCROLL_Y_POS\' generates 13 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\nwire [15:0] lines_down = VRENDER + (SCROLL_Y_POS & 15);\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:392: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 16 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\nwire tile_down = (lines_down >> 3);\n               ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:441: Operator ADD expects 32 or 13 bits on the LHS, but LHS\'s VARREF \'VRENDER\' generates 9 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n            y <= (VRENDER + (SCROLL_Y_POS & 15)) >> 4;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:441: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 or 13 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n            y <= (VRENDER + (SCROLL_Y_POS & 15)) >> 4;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:465: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 16 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                        SCR_GP9001RAM_GCU_ADDR <= row+column+1;  \n                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:486: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                        scroll_queue_priority_n_scan_buf_i <= scroll_queue_priority_n[((priority_i+1)<<3)-1 -: 8];\n                                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:504: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s ADD generates 16 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                    SCR_GP9001RAM_GCU_ADDR <= row+column;  \n                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:508: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s VARREF \'SCR_GP9001RAM_GCU_DOUT\' generates 16 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                        tile_num<=SCR_GP9001RAM_GCU_DOUT;\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:507: Operator LTE expects 32 or 25 bits on the LHS, but LHS\'s VARREF \'SCR_GP9001RAM_GCU_DOUT\' generates 16 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                    if(SCR_GP9001RAM_GCU_DOUT > 0 && SCR_GP9001RAM_GCU_DOUT <= max_tile) begin\n                                                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:517: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s AND generates 32 or 16 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                    priority_l = (tile_attrib>>8) & \'h0F;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:520: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'x\' generates 9 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                    xpos_t = (((x<<4) - (SCROLL_X_POS & 15)));\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:520: Operator AND expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'SCROLL_X_POS\' generates 13 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                    xpos_t = (((x<<4) - (SCROLL_X_POS & 15)));\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:521: Operator SHIFTL expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'y\' generates 9 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                    ypos_t = (((y<<4) - (SCROLL_Y_POS & 15)));\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:521: Operator AND expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'SCROLL_Y_POS\' generates 13 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                    ypos_t = (((y<<4) - (SCROLL_Y_POS & 15)));\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:529: Bit extraction of var[15:0] requires 4 bit index, not 5 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                    pri_has_tile[priority_i]<=0;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:536: Operator ASSIGNDLY expects 15 bits on the Assign RHS, but Assign RHS\'s SHIFTL generates 32 or 16 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                            SCR_TILE_NUMBER<=(tile_num_attr & \'h1FFF) << 2;\n                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:537: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'tile_down\' generates 1 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                            SCR_TILE_NUMBER_OFFS<= ((tile_down << 6) + (scr_x_render << 5)) + excess_line;\n                                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:537: Operator SHIFTL expects 16 bits on the LHS, but LHS\'s VARREF \'scr_x_render\' generates 2 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                            SCR_TILE_NUMBER_OFFS<= ((tile_down << 6) + (scr_x_render << 5)) + excess_line;\n                                                                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:538: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s AND generates 32 or 16 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                            SCR_TILE_BANK<=(tile_num_attr >> 13) & 7;\n                                         ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:570: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                            scroll_queue_priority_n_scan_buf_i<=scroll_queue_priority_n[((priority_i+1)<<3)-1 -: 8];\n                                                              ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:533: Operator LT expects 16 bits on the RHS, but RHS\'s VARREF \'scroll_queue_priority_n_scan_buf_i\' generates 5 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                    if(scr_queue_i < scroll_queue_priority_n_scan_buf_i) begin\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:608: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'tx\' generates 3 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                                BUF_ADDR<=(FLIPX ? 319-(tile_x_pos+tx) : (tile_x_pos+tx))&\'h1FF;\n                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:608: Operator ADD expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'tx\' generates 3 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                                BUF_ADDR<=(FLIPX ? 319-(tile_x_pos+tx) : (tile_x_pos+tx))&\'h1FF;\n                                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:608: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s AND generates 32 or 16 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                                BUF_ADDR<=(FLIPX ? 319-(tile_x_pos+tx) : (tile_x_pos+tx))&\'h1FF;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:609: Operator SHIFTL expects 15 bits on the LHS, but LHS\'s SEL generates 4 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                                BUF_DATA<=(priority_i[3:0] << 12) + tile_palette + tile_code;\n                                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:609: Operator ADD expects 15 bits on the RHS, but RHS\'s VARREF \'tile_palette\' generates 12 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                                BUF_DATA<=(priority_i[3:0] << 12) + tile_palette + tile_code;\n                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:609: Operator ADD expects 15 bits on the RHS, but RHS\'s VARREF \'tile_code\' generates 4 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                                BUF_DATA<=(priority_i[3:0] << 12) + tile_palette + tile_code;\n                                                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:606: Operator NEGATE expects 16 bits on the LHS, but LHS\'s VARREF \'tx\' generates 3 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                            if(tile_x_pos > -tx && tile_x_pos < (320-tx)) begin\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:606: Operator SUB expects 32 or 16 bits on the RHS, but RHS\'s VARREF \'tx\' generates 3 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                            if(tile_x_pos > -tx && tile_x_pos < (320-tx)) begin\n                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:614: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s AND generates 32 or 10 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                            BUF_ADDR<=(FLIPX ? 319-buf_code : buf_code)&\'h1FF;\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:615: Operator SHIFTL expects 15 bits on the LHS, but LHS\'s SEL generates 4 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                            BUF_DATA<=(priority_i[3:0] << 12) + tile_palette + tile_code;\n                                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:615: Operator ADD expects 15 bits on the RHS, but RHS\'s VARREF \'tile_palette\' generates 12 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                            BUF_DATA<=(priority_i[3:0] << 12) + tile_palette + tile_code;\n                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:615: Operator ADD expects 15 bits on the RHS, but RHS\'s VARREF \'tile_code\' generates 4 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                            BUF_DATA<=(priority_i[3:0] << 12) + tile_palette + tile_code;\n                                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:617: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s AND generates 32 or 10 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                            BUF_ADDR<=(FLIPX ? 319-buf_code : buf_code)&\'h1ff;\n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:621: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s AND generates 32 or 10 bits.\n                                                                                               : ... In instance raizing_scroll.u_scroll2\n                        BUF_ADDR<=(FLIPX ? 319-buf_code : buf_code)&\'h1ff;\n                                ^~\n%Error: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:99: Cannot find file containing module: \'jtframe_linebuf\'\njtframe_linebuf #(.DW(15)) u_scr0_line (\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:111: Cannot find file containing module: \'jtframe_linebuf\'\njtframe_linebuf #(.DW(15)) u_scr1_line (\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525423410/modules/raizing_video/raizing_scroll.v:123: Cannot find file containing module: \'jtframe_linebuf\'\njtframe_linebuf #(.DW(15)) u_scr2_line (\n^~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s), 49 warning(s)\n'
module raizing_scroll (
    input CLK,
    input CLK96,
    input PIXEL_CEN,
    input RESET,
    input RESET96,
    input [8:0] VRENDER,
    input [8:0] H,
    input ACTIVE,
    input HB,
    input VB,
    input FLIPX,


     output [12:0] SCR0_GP9001RAM_GCU_ADDR,
    input  [15:0] SCR0_GP9001RAM_GCU_DOUT,
    output [12:0] SCR1_GP9001RAM_GCU_ADDR,
    input  [15:0] SCR1_GP9001RAM_GCU_DOUT,
    output [12:0] SCR2_GP9001RAM_GCU_ADDR,
    input  [15:0] SCR2_GP9001RAM_GCU_DOUT,


    output GFXSCR0_CS,
    input GFXSCR0_OK,
    output [14:0] SCR0_TILE_NUMBER,
    output [15:0] SCR0_TILE_NUMBER_OFFS,
    output [3:0] SCR0_TILE_BANK,
    input  [31:0] SCR0_GFX_DATA,

    output GFXSCR1_CS,
    input GFXSCR1_OK,
    output [14:0] SCR1_TILE_NUMBER,
    output [15:0] SCR1_TILE_NUMBER_OFFS,
    output [3:0] SCR1_TILE_BANK,
    input  [31:0] SCR1_GFX_DATA,

    output GFXSCR2_CS,
    input GFXSCR2_OK,
    output [14:0] SCR2_TILE_NUMBER,
    output [15:0] SCR2_TILE_NUMBER_OFFS,
    output [3:0] SCR2_TILE_BANK,
    input  [31:0] SCR2_GFX_DATA,


    input signed [12:0] BACKGROUND_SCROLL_X,
    input signed [12:0] BACKGROUND_SCROLL_Y,
    input signed [12:0] BACKGROUND_SCROLL_XOFFS,
    input signed [12:0] BACKGROUND_SCROLL_YOFFS,
    input signed [12:0] FOREGROUND_SCROLL_X,
    input signed [12:0] FOREGROUND_SCROLL_Y,
    input signed [12:0] FOREGROUND_SCROLL_XOFFS,
    input signed [12:0] FOREGROUND_SCROLL_YOFFS,
    input signed [12:0] TEXT_SCROLL_X,
    input signed [12:0] TEXT_SCROLL_Y,
    input signed [12:0] TEXT_SCROLL_XOFFS,
    input signed [12:0] TEXT_SCROLL_YOFFS,

    output reg [14:0] SCROLL0_PIXEL,
    output reg [14:0] SCROLL1_PIXEL,
    output reg [14:0] SCROLL2_PIXEL
);

wire [14:0] scr0_buf_data;
wire [8:0] scr0_buf_addr;
wire [14:0] scr1_buf_data;
wire [8:0] scr1_buf_addr;
wire [14:0] scr2_buf_data;
wire [8:0] scr2_buf_addr;

wire [14:0] prescr0_pxl, prescr1_pxl, prescr2_pxl;
wire [8:0] scr0_buf_addr_out = H;
wire [8:0] scr1_buf_addr_out = H;
wire [8:0] scr2_buf_addr_out = H;
reg last_HB = 0, start = 0;
wire pedg_HB = !HB && last_HB;
reg busy = 1'b0;

jtframe_linebuf #(.DW(15)) u_scr0_line (
    .clk(CLK96),
    .LHBL(~HB),
    .wr_addr(scr0_buf_addr),
    .pxl_cen(PIXEL_CEN),
    .wr_data(scr0_buf_data),
    .we(scr0_buf_we),
    .rd_addr(scr0_buf_addr_out),
    .rd_data(prescr0_pxl),
    .rd_gated()
);

jtframe_linebuf #(.DW(15)) u_scr1_line (
    .clk(CLK96),
    .LHBL(~HB),
    .wr_addr(scr1_buf_addr),
    .pxl_cen(PIXEL_CEN),
    .wr_data(scr1_buf_data),
    .we(scr1_buf_we),
    .rd_addr(scr1_buf_addr_out),
    .rd_data(prescr1_pxl),
    .rd_gated()
);

jtframe_linebuf #(.DW(15)) u_scr2_line (
    .clk(CLK96),
    .LHBL(~HB),
    .wr_addr(scr2_buf_addr),
    .pxl_cen(PIXEL_CEN),
    .wr_data(scr2_buf_data),
    .we(scr2_buf_we),
    .rd_addr(scr2_buf_addr_out),
    .rd_data(prescr2_pxl),
    .rd_gated()
);

wire scr0_busy, scr0_done;
reg scr0_start;
wire scr1_busy, scr1_done;
reg scr1_start;
wire scr2_busy, scr2_done;
reg scr2_start;

raizing_scroll_qr u_scroll0 (
    .CLK(CLK),
    .CLK96(CLK96),
    .PIXEL_CEN(PIXEL_CEN),
    .RESET(RESET),
    .RESET96(RESET96),
    .VRENDER(VRENDER),
    .H(H),
    .ACTIVE(ACTIVE),
    .HB(HB),
    .VB(VB),
    .FLIPX(FLIPX),
    .SCR_GP9001RAM_GCU_ADDR(SCR0_GP9001RAM_GCU_ADDR),
    .SCR_GP9001RAM_GCU_DOUT(SCR0_GP9001RAM_GCU_DOUT),
    .SCROLL_X_POS(BACKGROUND_SCROLL_X+BACKGROUND_SCROLL_XOFFS),
    .SCROLL_Y_POS(BACKGROUND_SCROLL_Y+BACKGROUND_SCROLL_YOFFS),
    .GFXSCR_CS(GFXSCR0_CS),
    .GFXSCR_OK(GFXSCR0_OK),
    .SCR_TILE_NUMBER(SCR0_TILE_NUMBER),
    .SCR_TILE_NUMBER_OFFS(SCR0_TILE_NUMBER_OFFS),
    .SCR_TILE_BANK(SCR0_TILE_BANK),
    .SCR_GFX_DATA(SCR0_GFX_DATA),
    .BUSY(scr0_busy),
    .DONE(scr0_done),
    .START(scr0_start),
    .BUF_ADDR(scr0_buf_addr),
    .BUF_DATA(scr0_buf_data),
    .BUF_WE(scr0_buf_we),
    .DEBUG_SCRN(0)
);

raizing_scroll_qr u_scroll1 (
    .CLK(CLK),
    .CLK96(CLK96),
    .PIXEL_CEN(PIXEL_CEN),
    .RESET(RESET),
    .RESET96(RESET96),
    .VRENDER(VRENDER),
    .H(H),
    .ACTIVE(ACTIVE),
    .HB(HB),
    .VB(VB),
    .FLIPX(FLIPX),
    .SCR_GP9001RAM_GCU_ADDR(SCR1_GP9001RAM_GCU_ADDR),
    .SCR_GP9001RAM_GCU_DOUT(SCR1_GP9001RAM_GCU_DOUT),
    .SCROLL_X_POS(FOREGROUND_SCROLL_X+FOREGROUND_SCROLL_XOFFS),
    .SCROLL_Y_POS(FOREGROUND_SCROLL_Y+FOREGROUND_SCROLL_YOFFS),
    .GFXSCR_CS(GFXSCR1_CS),
    .GFXSCR_OK(GFXSCR1_OK),
    .SCR_TILE_NUMBER(SCR1_TILE_NUMBER),
    .SCR_TILE_NUMBER_OFFS(SCR1_TILE_NUMBER_OFFS),
    .SCR_TILE_BANK(SCR1_TILE_BANK),
    .SCR_GFX_DATA(SCR1_GFX_DATA),
    .BUSY(scr1_busy),
    .DONE(scr1_done),
    .START(scr1_start),
    .BUF_ADDR(scr1_buf_addr),
    .BUF_DATA(scr1_buf_data),
    .BUF_WE(scr1_buf_we),
    .DEBUG_SCRN(1)
);

raizing_scroll_qr u_scroll2 (
    .CLK(CLK),
    .CLK96(CLK96),
    .PIXEL_CEN(PIXEL_CEN),
    .RESET(RESET),
    .RESET96(RESET96),
    .VRENDER(VRENDER),
    .H(H),
    .ACTIVE(ACTIVE),
    .HB(HB),
    .VB(VB),
    .FLIPX(FLIPX),
    .SCR_GP9001RAM_GCU_ADDR(SCR2_GP9001RAM_GCU_ADDR),
    .SCR_GP9001RAM_GCU_DOUT(SCR2_GP9001RAM_GCU_DOUT),
    .SCROLL_X_POS(TEXT_SCROLL_X+TEXT_SCROLL_XOFFS),
    .SCROLL_Y_POS(TEXT_SCROLL_Y+TEXT_SCROLL_YOFFS),
    .GFXSCR_CS(GFXSCR2_CS),
    .GFXSCR_OK(GFXSCR2_OK),
    .SCR_TILE_NUMBER(SCR2_TILE_NUMBER),
    .SCR_TILE_NUMBER_OFFS(SCR2_TILE_NUMBER_OFFS),
    .SCR_TILE_BANK(SCR2_TILE_BANK),
    .SCR_GFX_DATA(SCR2_GFX_DATA),
    .BUSY(scr2_busy),
    .DONE(scr2_done),
    .START(scr2_start),
    .BUF_ADDR(scr2_buf_addr),
    .BUF_DATA(scr2_buf_data),
    .BUF_WE(scr2_buf_we),
    .DEBUG_SCRN(2)
);
reg done0=0, done1=0, done2=0;

always @(posedge CLK96, posedge RESET96) begin
    if(RESET96) begin
    end else begin
        if(PIXEL_CEN && ACTIVE) begin

            SCROLL0_PIXEL<=prescr0_pxl;
            SCROLL1_PIXEL<=prescr1_pxl;
            SCROLL2_PIXEL<=prescr2_pxl;
        end
    end
end
always @(posedge CLK96, posedge RESET96) begin
    if(RESET96) begin
    end else begin
        last_HB    <= HB;

        if( (pedg_HB && !VB)  || (((!FLIPX && VRENDER == 0) || (FLIPX && VRENDER == 239)) && pedg_HB) ) begin
            start <= 1'b1;
        end

        if(start && !busy) begin


            start<=1'b0;
            busy<=1'b1;
            scr0_start<=1'b1;
            scr1_start<=1'b1;
            scr2_start<=1'b1;
            done0<=1'b0;
            done1<=1'b0;
            done2<=1'b0;
        end else if (busy) begin
            if(done0 && done1 && done2) begin

                busy<=1'b0;
                start<=1'b0;
                scr0_start<=1'b0;
                scr1_start<=1'b0;
                scr2_start<=1'b0;
                done0<=1'b0;
                done1<=1'b0;
                done2<=1'b0;
            end else begin
                if(scr0_done) begin 
                    done0<=1'b1;
                    scr0_start<=1'b0;
                end
                if(scr1_done) begin 
                    done1<=1'b1;
                    scr1_start<=1'b0;
                end
                if(scr2_done) begin
                    done2<=1'b1;
                    scr2_start<=1'b0;
                end
            end
        end
    end
end

endmodule
module raizing_scroll (
    input CLK,
    input CLK96,
    input PIXEL_CEN,
    input RESET,
    input RESET96,
    input [8:0] VRENDER,
    input [8:0] H,
    input ACTIVE,
    input HB,
    input VB,
    input FLIPX,


     output [12:0] SCR0_GP9001RAM_GCU_ADDR,
    input  [15:0] SCR0_GP9001RAM_GCU_DOUT,
    output [12:0] SCR1_GP9001RAM_GCU_ADDR,
    input  [15:0] SCR1_GP9001RAM_GCU_DOUT,
    output [12:0] SCR2_GP9001RAM_GCU_ADDR,
    input  [15:0] SCR2_GP9001RAM_GCU_DOUT,


    output GFXSCR0_CS,
    input GFXSCR0_OK,
    output [14:0] SCR0_TILE_NUMBER,
    output [15:0] SCR0_TILE_NUMBER_OFFS,
    output [3:0] SCR0_TILE_BANK,
    input  [31:0] SCR0_GFX_DATA,

    output GFXSCR1_CS,
    input GFXSCR1_OK,
    output [14:0] SCR1_TILE_NUMBER,
    output [15:0] SCR1_TILE_NUMBER_OFFS,
    output [3:0] SCR1_TILE_BANK,
    input  [31:0] SCR1_GFX_DATA,

    output GFXSCR2_CS,
    input GFXSCR2_OK,
    output [14:0] SCR2_TILE_NUMBER,
    output [15:0] SCR2_TILE_NUMBER_OFFS,
    output [3:0] SCR2_TILE_BANK,
    input  [31:0] SCR2_GFX_DATA,


    input signed [12:0] BACKGROUND_SCROLL_X,
    input signed [12:0] BACKGROUND_SCROLL_Y,
    input signed [12:0] BACKGROUND_SCROLL_XOFFS,
    input signed [12:0] BACKGROUND_SCROLL_YOFFS,
    input signed [12:0] FOREGROUND_SCROLL_X,
    input signed [12:0] FOREGROUND_SCROLL_Y,
    input signed [12:0] FOREGROUND_SCROLL_XOFFS,
    input signed [12:0] FOREGROUND_SCROLL_YOFFS,
    input signed [12:0] TEXT_SCROLL_X,
    input signed [12:0] TEXT_SCROLL_Y,
    input signed [12:0] TEXT_SCROLL_XOFFS,
    input signed [12:0] TEXT_SCROLL_YOFFS,

    output reg [14:0] SCROLL0_PIXEL,
    output reg [14:0] SCROLL1_PIXEL,
    output reg [14:0] SCROLL2_PIXEL
);


wire [14:0] scr0_buf_data;
wire [8:0] scr0_buf_addr;
wire [14:0] scr1_buf_data;
wire [8:0] scr1_buf_addr;
wire [14:0] scr2_buf_data;
wire [8:0] scr2_buf_addr;

wire [14:0] prescr0_pxl, prescr1_pxl, prescr2_pxl;
wire [8:0] scr0_buf_addr_out = H;
wire [8:0] scr1_buf_addr_out = H;
wire [8:0] scr2_buf_addr_out = H;
reg last_HB = 0, start = 0;
wire pedg_HB = !HB && last_HB;
reg busy = 1'b0;

jtframe_linebuf #(.DW(15)) u_scr0_line (
    .clk(CLK96),
    .LHBL(~HB),
    .wr_addr(scr0_buf_addr),
    .pxl_cen(PIXEL_CEN),
    .wr_data(scr0_buf_data),
    .we(scr0_buf_we),
    .rd_addr(scr0_buf_addr_out),
    .rd_data(prescr0_pxl),
    .rd_gated()
);

jtframe_linebuf #(.DW(15)) u_scr1_line (
    .clk(CLK96),
    .LHBL(~HB),
    .wr_addr(scr1_buf_addr),
    .pxl_cen(PIXEL_CEN),
    .wr_data(scr1_buf_data),
    .we(scr1_buf_we),
    .rd_addr(scr1_buf_addr_out),
    .rd_data(prescr1_pxl),
    .rd_gated()
);

jtframe_linebuf #(.DW(15)) u_scr2_line (
    .clk(CLK96),
    .LHBL(~HB),
    .wr_addr(scr2_buf_addr),
    .pxl_cen(PIXEL_CEN),
    .wr_data(scr2_buf_data),
    .we(scr2_buf_we),
    .rd_addr(scr2_buf_addr_out),
    .rd_data(prescr2_pxl),
    .rd_gated()
);

wire scr0_busy, scr0_done;
reg scr0_start;
wire scr1_busy, scr1_done;
reg scr1_start;
wire scr2_busy, scr2_done;
reg scr2_start;

raizing_scroll_qr u_scroll0 (
    .CLK(CLK),
    .CLK96(CLK96),
    .PIXEL_CEN(PIXEL_CEN),
    .RESET(RESET),
    .RESET96(RESET96),
    .VRENDER(VRENDER),
    .H(H),
    .ACTIVE(ACTIVE),
    .HB(HB),
    .VB(VB),
    .FLIPX(FLIPX),
    .SCR_GP9001RAM_GCU_ADDR(SCR0_GP9001RAM_GCU_ADDR),
    .SCR_GP9001RAM_GCU_DOUT(SCR0_GP9001RAM_GCU_DOUT),
    .SCROLL_X_POS(BACKGROUND_SCROLL_X+BACKGROUND_SCROLL_XOFFS),
    .SCROLL_Y_POS(BACKGROUND_SCROLL_Y+BACKGROUND_SCROLL_YOFFS),
    .GFXSCR_CS(GFXSCR0_CS),
    .GFXSCR_OK(GFXSCR0_OK),
    .SCR_TILE_NUMBER(SCR0_TILE_NUMBER),
    .SCR_TILE_NUMBER_OFFS(SCR0_TILE_NUMBER_OFFS),
    .SCR_TILE_BANK(SCR0_TILE_BANK),
    .SCR_GFX_DATA(SCR0_GFX_DATA),
    .BUSY(scr0_busy),
    .DONE(scr0_done),
    .START(scr0_start),
    .BUF_ADDR(scr0_buf_addr),
    .BUF_DATA(scr0_buf_data),
    .BUF_WE(scr0_buf_we),
    .DEBUG_SCRN(0)
);

raizing_scroll_qr u_scroll1 (
    .CLK(CLK),
    .CLK96(CLK96),
    .PIXEL_CEN(PIXEL_CEN),
    .RESET(RESET),
    .RESET96(RESET96),
    .VRENDER(VRENDER),
    .H(H),
    .ACTIVE(ACTIVE),
    .HB(HB),
    .VB(VB),
    .FLIPX(FLIPX),
    .SCR_GP9001RAM_GCU_ADDR(SCR1_GP9001RAM_GCU_ADDR),
    .SCR_GP9001RAM_GCU_DOUT(SCR1_GP9001RAM_GCU_DOUT),
    .SCROLL_X_POS(FOREGROUND_SCROLL_X+FOREGROUND_SCROLL_XOFFS),
    .SCROLL_Y_POS(FOREGROUND_SCROLL_Y+FOREGROUND_SCROLL_YOFFS),
    .GFXSCR_CS(GFXSCR1_CS),
    .GFXSCR_OK(GFXSCR1_OK),
    .SCR_TILE_NUMBER(SCR1_TILE_NUMBER),
    .SCR_TILE_NUMBER_OFFS(SCR1_TILE_NUMBER_OFFS),
    .SCR_TILE_BANK(SCR1_TILE_BANK),
    .SCR_GFX_DATA(SCR1_GFX_DATA),
    .BUSY(scr1_busy),
    .DONE(scr1_done),
    .START(scr1_start),
    .BUF_ADDR(scr1_buf_addr),
    .BUF_DATA(scr1_buf_data),
    .BUF_WE(scr1_buf_we),
    .DEBUG_SCRN(1)
);

raizing_scroll_qr u_scroll2 (
    .CLK(CLK),
    .CLK96(CLK96),
    .PIXEL_CEN(PIXEL_CEN),
    .RESET(RESET),
    .RESET96(RESET96),
    .VRENDER(VRENDER),
    .H(H),
    .ACTIVE(ACTIVE),
    .HB(HB),
    .VB(VB),
    .FLIPX(FLIPX),
    .SCR_GP9001RAM_GCU_ADDR(SCR2_GP9001RAM_GCU_ADDR),
    .SCR_GP9001RAM_GCU_DOUT(SCR2_GP9001RAM_GCU_DOUT),
    .SCROLL_X_POS(TEXT_SCROLL_X+TEXT_SCROLL_XOFFS),
    .SCROLL_Y_POS(TEXT_SCROLL_Y+TEXT_SCROLL_YOFFS),
    .GFXSCR_CS(GFXSCR2_CS),
    .GFXSCR_OK(GFXSCR2_OK),
    .SCR_TILE_NUMBER(SCR2_TILE_NUMBER),
    .SCR_TILE_NUMBER_OFFS(SCR2_TILE_NUMBER_OFFS),
    .SCR_TILE_BANK(SCR2_TILE_BANK),
    .SCR_GFX_DATA(SCR2_GFX_DATA),
    .BUSY(scr2_busy),
    .DONE(scr2_done),
    .START(scr2_start),
    .BUF_ADDR(scr2_buf_addr),
    .BUF_DATA(scr2_buf_data),
    .BUF_WE(scr2_buf_we),
    .DEBUG_SCRN(2)
);
reg done0=0, done1=0, done2=0;

always @(posedge CLK96, posedge RESET96) begin
    if(RESET96) begin
    end else begin
        if(PIXEL_CEN && ACTIVE) begin

            SCROLL0_PIXEL<=prescr0_pxl;
            SCROLL1_PIXEL<=prescr1_pxl;
            SCROLL2_PIXEL<=prescr2_pxl;
        end
    end
end
always @(posedge CLK96, posedge RESET96) begin
    if(RESET96) begin
    end else begin
        last_HB    <= HB;

        if( (pedg_HB && !VB)  || (((!FLIPX && VRENDER == 0) || (FLIPX && VRENDER == 239)) && pedg_HB) ) begin
            start <= 1'b1;
        end

        if(start && !busy) begin


            start<=1'b0;
            busy<=1'b1;
            scr0_start<=1'b1;
            scr1_start<=1'b1;
            scr2_start<=1'b1;
            done0<=1'b0;
            done1<=1'b0;
            done2<=1'b0;
        end else if (busy) begin
            if(done0 && done1 && done2) begin

                busy<=1'b0;
                start<=1'b0;
                scr0_start<=1'b0;
                scr1_start<=1'b0;
                scr2_start<=1'b0;
                done0<=1'b0;
                done1<=1'b0;
                done2<=1'b0;
            end else begin
                if(scr0_done) begin 
                    done0<=1'b1;
                    scr0_start<=1'b0;
                end
                if(scr1_done) begin 
                    done1<=1'b1;
                    scr1_start<=1'b0;
                end
                if(scr2_done) begin
                    done2<=1'b1;
                    scr2_start<=1'b0;
                end
            end
        end
    end
end

endmodule