data/full_repos/permissive/486812922/src/ctrl.v
1: b'%Error: data/full_repos/permissive/486812922/src/ctrl.v:2: Cannot find include file: ctrl_encode_def.v\n`include "ctrl_encode_def.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/486812922/src,data/full_repos/permissive/486812922/ctrl_encode_def.v\n             data/full_repos/permissive/486812922/src,data/full_repos/permissive/486812922/ctrl_encode_def.v.v\n             data/full_repos/permissive/486812922/src,data/full_repos/permissive/486812922/ctrl_encode_def.v.sv\n             ctrl_encode_def.v\n             ctrl_encode_def.v.v\n             ctrl_encode_def.v.sv\n             obj_dir/ctrl_encode_def.v\n             obj_dir/ctrl_encode_def.v.v\n             obj_dir/ctrl_encode_def.v.sv\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:3: Cannot find include file: instruction_def.v\n`include "instruction_def.v"  \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:33: Define or directive not defined: \'`INSTR_RTYPE_OP\'\nassign RType = (opcode == `INSTR_RTYPE_OP) & !nop;\n                          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:33: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign RType = (opcode == `INSTR_RTYPE_OP) & !nop;\n                                         ^\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:35: Define or directive not defined: \'`INSTR_ADDI_OP\'\nassign addi = (opcode == `INSTR_ADDI_OP);\n                         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:35: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign addi = (opcode == `INSTR_ADDI_OP);\n                                       ^\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:36: Define or directive not defined: \'`INSTR_ADDIU_OP\'\nassign addiu = (opcode == `INSTR_ADDIU_OP);\n                          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:36: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign addiu = (opcode == `INSTR_ADDIU_OP);\n                                         ^\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:37: Define or directive not defined: \'`INSTR_ANDI_OP\'\nassign andi = (opcode == `INSTR_ANDI_OP);\n                         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:37: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign andi = (opcode == `INSTR_ANDI_OP);\n                                       ^\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:38: Define or directive not defined: \'`INSTR_ORI_OP\'\nassign ori = (opcode == `INSTR_ORI_OP);\n                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:38: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign ori = (opcode == `INSTR_ORI_OP);\n                                     ^\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:39: Define or directive not defined: \'`INSTR_XORI_OP\'\nassign xori = (opcode == `INSTR_XORI_OP);\n                         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:39: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign xori = (opcode == `INSTR_XORI_OP);\n                                       ^\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:40: Define or directive not defined: \'`INSTR_LUI_OP\'\nassign lui = (opcode == `INSTR_LUI_OP);\n                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:40: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign lui = (opcode == `INSTR_LUI_OP);\n                                     ^\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:41: Define or directive not defined: \'`INSTR_LW_OP\'\nassign lw = (opcode == `INSTR_LW_OP);\n                       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:41: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign lw = (opcode == `INSTR_LW_OP);\n                                   ^\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:42: Define or directive not defined: \'`INSTR_SW_OP\'\nassign sw = (opcode == `INSTR_SW_OP);\n                       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:42: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign sw = (opcode == `INSTR_SW_OP);\n                                   ^\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:43: Define or directive not defined: \'`INSTR_SLTI_OP\'\nassign slti = (opcode == `INSTR_SLTI_OP);\n                         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:43: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign slti = (opcode == `INSTR_SLTI_OP);\n                                       ^\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:44: Define or directive not defined: \'`INSTR_SLTIU_OP\'\nassign sltiu = (opcode == `INSTR_SLTIU_OP);\n                          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:44: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign sltiu = (opcode == `INSTR_SLTIU_OP);\n                                         ^\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:47: Define or directive not defined: \'`INSTR_BEQ_OP\'\nassign beq = (opcode == `INSTR_BEQ_OP);\n                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:47: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign beq = (opcode == `INSTR_BEQ_OP);\n                                     ^\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:48: Define or directive not defined: \'`INSTR_BNE_OP\'\nassign bne = (opcode == `INSTR_BNE_OP);\n                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:48: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign bne = (opcode == `INSTR_BNE_OP);\n                                     ^\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:51: Define or directive not defined: \'`INSTR_J_OP\'\nassign j = (opcode == `INSTR_J_OP);\n                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:51: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign j = (opcode == `INSTR_J_OP);\n                                 ^\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:52: Define or directive not defined: \'`INSTR_JAL_OP\'\nassign jal = (opcode == `INSTR_JAL_OP);\n                        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:52: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign jal = (opcode == `INSTR_JAL_OP);\n                                     ^\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:58: Define or directive not defined: \'`INSTR_RTYPE_OP\'\nassign shamt_sign = (opcode == `INSTR_RTYPE_OP) && (\n                               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:58: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign shamt_sign = (opcode == `INSTR_RTYPE_OP) && (\n                                              ^\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:59: Define or directive not defined: \'`INSTR_SLL_FUNCT\'\n           funct == `INSTR_SLL_FUNCT ||\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:60: Define or directive not defined: \'`INSTR_SRL_FUNCT\'\n           funct == `INSTR_SRL_FUNCT ||\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:61: Define or directive not defined: \'`INSTR_SRA_FUNCT\'\n           funct == `INSTR_SRA_FUNCT);\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:80: Define or directive not defined: \'`NPC_PLUS4\'\n        NPCOp = `NPC_PLUS4;\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:80: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        NPCOp = `NPC_PLUS4;\n                          ^\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:86: Define or directive not defined: \'`GPRSel_RD\'\n        GPRSel = `GPRSel_RD;\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:86: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        GPRSel = `GPRSel_RD;\n                           ^\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:88: Define or directive not defined: \'`WDSel_FromALU\'\n        WDSel = `WDSel_FromALU;\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:88: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        WDSel = `WDSel_FromALU;\n                              ^\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:97: Define or directive not defined: \'`INSTR_ADD_FUNCT\'\n                `INSTR_ADD_FUNCT:\n                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:97: syntax error, unexpected \':\', expecting endcase\n                `INSTR_ADD_FUNCT:\n                                ^\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:98: Define or directive not defined: \'`ALUOp_ADD\'\n                    ALUOp = `ALUOp_ADD;\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:99: Define or directive not defined: \'`INSTR_ADDU_FUNCT\'\n                `INSTR_ADDU_FUNCT:\n                ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:100: Define or directive not defined: \'`ALUOp_ADDU\'\n                    ALUOp = `ALUOp_ADDU;\n                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:101: Define or directive not defined: \'`INSTR_SUB_FUNCT\'\n                `INSTR_SUB_FUNCT:\n                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486812922/src/ctrl.v:102: Define or directive not defined: \'`ALUOp_SUB\'\n                    ALUOp = `ALUOp_SUB;\n                            ^~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module ctrl(opcode, funct, rt, nop, Zero, RFWr, DMWr, ALUOp, NPCOp, BSel, EXTOp, ASel, GPRSel, WDSel);

input [5: 0] opcode;
input [5: 0] funct;
input [4: 0] rt;

input nop, Zero;

output reg RFWr;

output reg DMWr;

output reg [4: 0] ALUOp;

output reg [2: 0] NPCOp;

output reg ASel, BSel;

output reg [1: 0] EXTOp;

output reg [1: 0] GPRSel;
output reg [2: 0] WDSel;


reg flush;



assign RType = (opcode == `INSTR_RTYPE_OP) & !nop;

assign addi = (opcode == `INSTR_ADDI_OP);
assign addiu = (opcode == `INSTR_ADDIU_OP);
assign andi = (opcode == `INSTR_ANDI_OP);
assign ori = (opcode == `INSTR_ORI_OP);
assign xori = (opcode == `INSTR_XORI_OP);
assign lui = (opcode == `INSTR_LUI_OP);
assign lw = (opcode == `INSTR_LW_OP);
assign sw = (opcode == `INSTR_SW_OP);
assign slti = (opcode == `INSTR_SLTI_OP);
assign sltiu = (opcode == `INSTR_SLTIU_OP);
assign IType = addi | addiu | andi | ori | xori | lui | lw | sw | slti | sltiu;

assign beq = (opcode == `INSTR_BEQ_OP);
assign bne = (opcode == `INSTR_BNE_OP);
assign BrType = beq | bne;

assign j = (opcode == `INSTR_J_OP);
assign jal = (opcode == `INSTR_JAL_OP);
assign JType = j | jal;


assign SignExtend = addi | addiu | lw | sw;

assign shamt_sign = (opcode == `INSTR_RTYPE_OP) && (
           funct == `INSTR_SLL_FUNCT ||
           funct == `INSTR_SRL_FUNCT ||
           funct == `INSTR_SRA_FUNCT);

always @( * ) begin
    if (nop) begin

        NPCOp = 0;
        RFWr = 1'b0;
        DMWr = 1'b0;
        EXTOp = 0;
        GPRSel = 0;
        WDSel = 0;
        BSel = 1'b0;
        ASel = 1'b0;
        ALUOp = 0;
        flush = 0;
    end
    else if (RType) begin


        NPCOp = `NPC_PLUS4;

        RFWr = 1'b1;
        DMWr = 1'b0;
        EXTOp = 0;

        GPRSel = `GPRSel_RD;

        WDSel = `WDSel_FromALU;

        BSel <= 1'b0;

        ASel <= (shamt_sign) ? 1'b1 : 1'b0;
        flush = 0;
        begin

            case (funct)
                `INSTR_ADD_FUNCT:
                    ALUOp = `ALUOp_ADD;
                `INSTR_ADDU_FUNCT:
                    ALUOp = `ALUOp_ADDU;
                `INSTR_SUB_FUNCT:
                    ALUOp = `ALUOp_SUB;
                `INSTR_SUBU_FUNCT:
                    ALUOp = `ALUOp_SUBU;
                `INSTR_AND_FUNCT:
                    ALUOp = `ALUOp_AND;
                `INSTR_OR_FUNCT:
                    ALUOp = `ALUOp_OR;
                `INSTR_XOR_FUNCT:
                    ALUOp = `ALUOp_XOR;
                `INSTR_NOR_FUNCT:
                    ALUOp = `ALUOp_NOR;
                `INSTR_SLT_FUNCT:
                    ALUOp = `ALUOp_SLT;
                `INSTR_SLTU_FUNCT:
                    ALUOp = `ALUOp_SLTU;
                `INSTR_SLL_FUNCT:
                    ALUOp = `ALUOp_SLL;
                `INSTR_SRL_FUNCT:
                    ALUOp = `ALUOp_SRL;
                `INSTR_SRA_FUNCT:
                    ALUOp = `ALUOp_SRA;
                `INSTR_SLLV_FUNCT:
                    ALUOp = `ALUOp_SLLV;
                `INSTR_SRLV_FUNCT:
                    ALUOp = `ALUOp_SRLV;
                `INSTR_SRAV_FUNCT:
                    ALUOp = `ALUOp_SRAV;
                `INSTR_JR_FUNCT: begin
                    NPCOp = `NPC_JR;

                    BSel = 1'b1;
                    ALUOp = `ALUOp_NOP;
                end
                default:
                    ALUOp = `ALUOp_ERROR;
            endcase
        end
    end
    else if (IType) begin

        NPCOp = `NPC_PLUS4;
        DMWr = 1'b0;
        RFWr = 1'b1;
        WDSel = `WDSel_FromALU;


        if (SignExtend)
            EXTOp = `EXT_SIGNED;
        else
            EXTOp = 0;

        GPRSel = `GPRSel_RT;

        BSel = 1'b1;
        ASel = 1'b0;
        flush = 0;

        if (addi)
            ALUOp = `ALUOp_ADDI;
        else if (addiu)
            ALUOp = `ALUOp_ADDIU;
        else if (andi)
            ALUOp = `ALUOp_ANDI;
        else if (ori)
            ALUOp = `ALUOp_ORI;
        else if (xori)
            ALUOp = `ALUOp_XORI;
        else if (lui)
            ALUOp = `ALUOp_LUI;
        else if (slti)
            ALUOp = `ALUOp_SLTI;
        else if (sltiu)
            ALUOp = `ALUOp_SLTIU;
        else if (sw) begin
            ALUOp = `ALUOp_ADD;
            RFWr = 1'b0;
            DMWr = 1'b1;
        end
        else if (lw) begin
            ALUOp = `ALUOp_ADD;
            WDSel = `WDSel_FromMem;
        end
    end
    else if (BrType ) begin


        NPCOp = (Zero) ? `NPC_BRANCH : `NPC_PLUS4;
        RFWr = 1'b0;
        DMWr = 1'b0;
        EXTOp = 0;
        GPRSel = `GPRSel_RD;
        WDSel = `WDSel_FromPC;
        BSel = 1'b0;
        ASel = 1'b0;
        flush = 0;

        if (beq)
            ALUOp = `ALUOp_BEQ;
        else if (bne)
            ALUOp = `ALUOp_BNE;
    end
    else if (JType) begin
        NPCOp = `NPC_JUMP;
        EXTOp = `EXT_SIGNED;
        WDSel = `WDSel_FromPC;
        BSel = 1'b0;
        ASel = 1'b0;
        ALUOp = `ALUOp_NOP;
        DMWr = 1'b0;
        flush = 0;

        if (jal) begin
            RFWr = 1'b1;
            GPRSel = `GPRSel_31;
        end
        else begin
            RFWr = 1'b0;
            GPRSel = `GPRSel_RD;
        end
    end
    else begin
        NPCOp = `NPC_EXCEPT;
        RFWr = 1'b0;
        DMWr = 1'b0;
        EXTOp = 0;
        GPRSel = 0;
        WDSel = 0;
        BSel = 1'b0;
        ASel = 1'b0;
        ALUOp = 0;
        flush = 0;
    end
end
endmodule
module ctrl(opcode, funct, rt, nop, Zero, RFWr, DMWr, ALUOp, NPCOp, BSel, EXTOp, ASel, GPRSel, WDSel);


input [5: 0] opcode;
input [5: 0] funct;
input [4: 0] rt;

input nop, Zero;

output reg RFWr;

output reg DMWr;

output reg [4: 0] ALUOp;

output reg [2: 0] NPCOp;

output reg ASel, BSel;

output reg [1: 0] EXTOp;

output reg [1: 0] GPRSel;
output reg [2: 0] WDSel;


reg flush;



assign RType = (opcode == `INSTR_RTYPE_OP) & !nop;

assign addi = (opcode == `INSTR_ADDI_OP);
assign addiu = (opcode == `INSTR_ADDIU_OP);
assign andi = (opcode == `INSTR_ANDI_OP);
assign ori = (opcode == `INSTR_ORI_OP);
assign xori = (opcode == `INSTR_XORI_OP);
assign lui = (opcode == `INSTR_LUI_OP);
assign lw = (opcode == `INSTR_LW_OP);
assign sw = (opcode == `INSTR_SW_OP);
assign slti = (opcode == `INSTR_SLTI_OP);
assign sltiu = (opcode == `INSTR_SLTIU_OP);
assign IType = addi | addiu | andi | ori | xori | lui | lw | sw | slti | sltiu;

assign beq = (opcode == `INSTR_BEQ_OP);
assign bne = (opcode == `INSTR_BNE_OP);
assign BrType = beq | bne;

assign j = (opcode == `INSTR_J_OP);
assign jal = (opcode == `INSTR_JAL_OP);
assign JType = j | jal;


assign SignExtend = addi | addiu | lw | sw;

assign shamt_sign = (opcode == `INSTR_RTYPE_OP) && (
           funct == `INSTR_SLL_FUNCT ||
           funct == `INSTR_SRL_FUNCT ||
           funct == `INSTR_SRA_FUNCT);

always @( * ) begin
    if (nop) begin

        NPCOp = 0;
        RFWr = 1'b0;
        DMWr = 1'b0;
        EXTOp = 0;
        GPRSel = 0;
        WDSel = 0;
        BSel = 1'b0;
        ASel = 1'b0;
        ALUOp = 0;
        flush = 0;
    end
    else if (RType) begin


        NPCOp = `NPC_PLUS4;

        RFWr = 1'b1;
        DMWr = 1'b0;
        EXTOp = 0;

        GPRSel = `GPRSel_RD;

        WDSel = `WDSel_FromALU;

        BSel <= 1'b0;

        ASel <= (shamt_sign) ? 1'b1 : 1'b0;
        flush = 0;
        begin

            case (funct)
                `INSTR_ADD_FUNCT:
                    ALUOp = `ALUOp_ADD;
                `INSTR_ADDU_FUNCT:
                    ALUOp = `ALUOp_ADDU;
                `INSTR_SUB_FUNCT:
                    ALUOp = `ALUOp_SUB;
                `INSTR_SUBU_FUNCT:
                    ALUOp = `ALUOp_SUBU;
                `INSTR_AND_FUNCT:
                    ALUOp = `ALUOp_AND;
                `INSTR_OR_FUNCT:
                    ALUOp = `ALUOp_OR;
                `INSTR_XOR_FUNCT:
                    ALUOp = `ALUOp_XOR;
                `INSTR_NOR_FUNCT:
                    ALUOp = `ALUOp_NOR;
                `INSTR_SLT_FUNCT:
                    ALUOp = `ALUOp_SLT;
                `INSTR_SLTU_FUNCT:
                    ALUOp = `ALUOp_SLTU;
                `INSTR_SLL_FUNCT:
                    ALUOp = `ALUOp_SLL;
                `INSTR_SRL_FUNCT:
                    ALUOp = `ALUOp_SRL;
                `INSTR_SRA_FUNCT:
                    ALUOp = `ALUOp_SRA;
                `INSTR_SLLV_FUNCT:
                    ALUOp = `ALUOp_SLLV;
                `INSTR_SRLV_FUNCT:
                    ALUOp = `ALUOp_SRLV;
                `INSTR_SRAV_FUNCT:
                    ALUOp = `ALUOp_SRAV;
                `INSTR_JR_FUNCT: begin
                    NPCOp = `NPC_JR;

                    BSel = 1'b1;
                    ALUOp = `ALUOp_NOP;
                end
                default:
                    ALUOp = `ALUOp_ERROR;
            endcase
        end
    end
    else if (IType) begin

        NPCOp = `NPC_PLUS4;
        DMWr = 1'b0;
        RFWr = 1'b1;
        WDSel = `WDSel_FromALU;


        if (SignExtend)
            EXTOp = `EXT_SIGNED;
        else
            EXTOp = 0;

        GPRSel = `GPRSel_RT;

        BSel = 1'b1;
        ASel = 1'b0;
        flush = 0;

        if (addi)
            ALUOp = `ALUOp_ADDI;
        else if (addiu)
            ALUOp = `ALUOp_ADDIU;
        else if (andi)
            ALUOp = `ALUOp_ANDI;
        else if (ori)
            ALUOp = `ALUOp_ORI;
        else if (xori)
            ALUOp = `ALUOp_XORI;
        else if (lui)
            ALUOp = `ALUOp_LUI;
        else if (slti)
            ALUOp = `ALUOp_SLTI;
        else if (sltiu)
            ALUOp = `ALUOp_SLTIU;
        else if (sw) begin
            ALUOp = `ALUOp_ADD;
            RFWr = 1'b0;
            DMWr = 1'b1;
        end
        else if (lw) begin
            ALUOp = `ALUOp_ADD;
            WDSel = `WDSel_FromMem;
        end
    end
    else if (BrType ) begin


        NPCOp = (Zero) ? `NPC_BRANCH : `NPC_PLUS4;
        RFWr = 1'b0;
        DMWr = 1'b0;
        EXTOp = 0;
        GPRSel = `GPRSel_RD;
        WDSel = `WDSel_FromPC;
        BSel = 1'b0;
        ASel = 1'b0;
        flush = 0;

        if (beq)
            ALUOp = `ALUOp_BEQ;
        else if (bne)
            ALUOp = `ALUOp_BNE;
    end
    else if (JType) begin
        NPCOp = `NPC_JUMP;
        EXTOp = `EXT_SIGNED;
        WDSel = `WDSel_FromPC;
        BSel = 1'b0;
        ASel = 1'b0;
        ALUOp = `ALUOp_NOP;
        DMWr = 1'b0;
        flush = 0;

        if (jal) begin
            RFWr = 1'b1;
            GPRSel = `GPRSel_31;
        end
        else begin
            RFWr = 1'b0;
            GPRSel = `GPRSel_RD;
        end
    end
    else begin
        NPCOp = `NPC_EXCEPT;
        RFWr = 1'b0;
        DMWr = 1'b0;
        EXTOp = 0;
        GPRSel = 0;
        WDSel = 0;
        BSel = 1'b0;
        ASel = 1'b0;
        ALUOp = 0;
        flush = 0;
    end
end
endmodule