data/full_repos/permissive/443770883/lab6/Lab5-Student copy/reg_alu.v
1: b'%Error: Cannot find file containing module: copy,data/full_repos/permissive/443770883\n        ... Looked in:\n             data/full_repos/permissive/443770883/lab6/Lab5-Student/copy,data/full_repos/permissive/443770883\n             data/full_repos/permissive/443770883/lab6/Lab5-Student/copy,data/full_repos/permissive/443770883.v\n             data/full_repos/permissive/443770883/lab6/Lab5-Student/copy,data/full_repos/permissive/443770883.sv\n             copy,data/full_repos/permissive/443770883\n             copy,data/full_repos/permissive/443770883.v\n             copy,data/full_repos/permissive/443770883.sv\n             obj_dir/copy,data/full_repos/permissive/443770883\n             obj_dir/copy,data/full_repos/permissive/443770883.v\n             obj_dir/copy,data/full_repos/permissive/443770883.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/443770883/lab6/Lab5-Student\n%Error: Cannot find file containing module: copy/reg_alu.v\n%Error: Exiting due to 3 error(s)\n'
module dfrl16(input wire clk,reset,load,input wire [15:0] in ,output wire [15:0] out);

	dfrl f0(clk,reset,load,in[0],out[0]);
	dfrl f1(clk,reset,load,in[1],out[1]);
	dfrl f2(clk,reset,load,in[2],out[2]);
	dfrl f3(clk,reset,load,in[3],out[3]);
	dfrl f4(clk,reset,load,in[4],out[4]);
	dfrl f5(clk,reset,load,in[5],out[5]);
	dfrl f6(clk,reset,load,in[6],out[6]);
	dfrl f7(clk,reset,load,in[7],out[7]);
	dfrl f8(clk,reset,load,in[8],out[8]);
	dfrl f9(clk,reset,load,in[9],out[9]);
	dfrl f10(clk,reset,load,in[10],out[10]);
	dfrl f11(clk,reset,load,in[11],out[11]);
	dfrl f12(clk,reset,load,in[12],out[12]);
	dfrl f13(clk,reset,load,in[13],out[13]);
	dfrl f14(clk,reset,load,in[14],out[14]);
	dfrl f15(clk,reset,load,in[15],out[15]);

endmodule
module dfrl16(input wire clk,reset,load,input wire [15:0] in ,output wire [15:0] out);


	dfrl f0(clk,reset,load,in[0],out[0]);
	dfrl f1(clk,reset,load,in[1],out[1]);
	dfrl f2(clk,reset,load,in[2],out[2]);
	dfrl f3(clk,reset,load,in[3],out[3]);
	dfrl f4(clk,reset,load,in[4],out[4]);
	dfrl f5(clk,reset,load,in[5],out[5]);
	dfrl f6(clk,reset,load,in[6],out[6]);
	dfrl f7(clk,reset,load,in[7],out[7]);
	dfrl f8(clk,reset,load,in[8],out[8]);
	dfrl f9(clk,reset,load,in[9],out[9]);
	dfrl f10(clk,reset,load,in[10],out[10]);
	dfrl f11(clk,reset,load,in[11],out[11]);
	dfrl f12(clk,reset,load,in[12],out[12]);
	dfrl f13(clk,reset,load,in[13],out[13]);
	dfrl f14(clk,reset,load,in[14],out[14]);
	dfrl f15(clk,reset,load,in[15],out[15]);

endmodule