data/full_repos/permissive/510695465/Add8bit.v
data/verilator_xmls/3aa01ad3-2314-4235-bd46-d5f251772dc8.xml
module Add8bit(A,B,out);

input [7:0]A,B;
output [7:0]out;

assign out = A+B;

endmodule
module Add8bit(A,B,out);


input [7:0]A,B;
output [7:0]out;

assign out = A+B;

endmodule