data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gclk_inv_r90_256x.v
data/verilator_xmls/d4cda3ae-b955-4867-9e4f-fd16b25c35d3.xml
module bw_clk_gclk_inv_r90_256x (
    clkout,
    clkin );

    output clkout;
    input  clkin;
 
    assign clkout = ~( clkin );

endmodule
module bw_clk_gclk_inv_r90_256x (
    clkout,
    clkin );


    output clkout;
    input  clkin;
 
    assign clkout = ~( clkin );

endmodule