data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_synch_holdable_driver.sv
1: b"%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_synch_holdable_driver.sv:19: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n  parameter time  ApplDelay = 0ps\n                              ^~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_synch_holdable_driver.sv:22: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic    rst_ni,\n  ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_synch_holdable_driver.sv:24: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic    hold_i,\n  ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_synch_holdable_driver.sv:25: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output data_t   data_o\n  ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_synch_holdable_driver.sv:30: syntax error, unexpected IDENTIFIER\n    data_o = '0;\n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_synch_holdable_driver.sv:34: Unsupported: SystemVerilog 2005 reserved word not implemented: 'randomize'\n      rand_success = std::randomize(rand_delay) with {\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_synch_holdable_driver.sv:34: Unsupported: SystemVerilog 2005 reserved word not implemented: 'with'\n      rand_success = std::randomize(rand_delay) with {\n                                                ^~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_synch_holdable_driver.sv:44: Unsupported: SystemVerilog 2005 reserved word not implemented: 'randomize'\n        void'(std::randomize(data_o));\n                   ^~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module rand_synch_holdable_driver #(
  parameter type  data_t = logic,

  parameter int   MinWaitCycles = -1,

  parameter int   MaxWaitCycles = -1,

  parameter time  ApplDelay = 0ps
) (
  input  logic    clk_i,
  input  logic    rst_ni,

  input  logic    hold_i,
  output data_t   data_o
);

  initial begin
    int unsigned rand_delay, rand_success;
    data_o = '0;
    wait (rst_ni);
    @(posedge clk_i);
    forever begin
      rand_success = std::randomize(rand_delay) with {
        rand_delay >= MinWaitCycles;
        rand_delay <= MaxWaitCycles;
      };
      assert (rand_success) else $error("Failed to randomize wait cycles!");
      repeat(rand_delay) begin
        @(posedge clk_i);
      end
      #(ApplDelay);
      if (!hold_i) begin
        void'(std::randomize(data_o));
      end
    end
  end


`ifndef VERILATOR
  initial begin: validate_params
    assert (MinWaitCycles >= 0)
      else $fatal("The minimum number of wait cycles must be at least 0!");
    assert (MaxWaitCycles >= 0)
      else $fatal("The maximum number of wait cycles must be at least 0!");
    assert (MaxWaitCycles >= MinWaitCycles)
      else $fatal("The maximum number of wait cycles must be at least the minimum number of wait cycles!");
    assert (ApplDelay > 0ps)
      else $fatal("The application delay must be greater than 0!");
  end
`endif

endmodule
module rand_synch_holdable_driver #(
  parameter type  data_t = logic,

  parameter int   MinWaitCycles = -1,

  parameter int   MaxWaitCycles = -1,

  parameter time  ApplDelay = 0ps
) (
  input  logic    clk_i,
  input  logic    rst_ni,

  input  logic    hold_i,
  output data_t   data_o
);


  initial begin
    int unsigned rand_delay, rand_success;
    data_o = '0;
    wait (rst_ni);
    @(posedge clk_i);
    forever begin
      rand_success = std::randomize(rand_delay) with {
        rand_delay >= MinWaitCycles;
        rand_delay <= MaxWaitCycles;
      };
      assert (rand_success) else $error("Failed to randomize wait cycles!");
      repeat(rand_delay) begin
        @(posedge clk_i);
      end
      #(ApplDelay);
      if (!hold_i) begin
        void'(std::randomize(data_o));
      end
    end
  end


`ifndef VERILATOR
  initial begin: validate_params
    assert (MinWaitCycles >= 0)
      else $fatal("The minimum number of wait cycles must be at least 0!");
    assert (MaxWaitCycles >= 0)
      else $fatal("The maximum number of wait cycles must be at least 0!");
    assert (MaxWaitCycles >= MinWaitCycles)
      else $fatal("The maximum number of wait cycles must be at least the minimum number of wait cycles!");
    assert (ApplDelay > 0ps)
      else $fatal("The application delay must be greater than 0!");
  end
`endif

endmodule