data/full_repos/permissive/450205124/Assignment3/Q2-parity-checker/A3Q2_parity_checker_tb.v
1: b'%Error: data/full_repos/permissive/450205124/Assignment3/Q2-parity-checker/A3Q2_parity_checker_tb.v:1: Cannot find include file: A3Q2_parity_checker.v\n`include "A3Q2_parity_checker.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/450205124/Assignment3/Q2-parity-checker,data/full_repos/permissive/450205124/A3Q2_parity_checker.v\n             data/full_repos/permissive/450205124/Assignment3/Q2-parity-checker,data/full_repos/permissive/450205124/A3Q2_parity_checker.v.v\n             data/full_repos/permissive/450205124/Assignment3/Q2-parity-checker,data/full_repos/permissive/450205124/A3Q2_parity_checker.v.sv\n             A3Q2_parity_checker.v\n             A3Q2_parity_checker.v.v\n             A3Q2_parity_checker.v.sv\n             obj_dir/A3Q2_parity_checker.v\n             obj_dir/A3Q2_parity_checker.v.v\n             obj_dir/A3Q2_parity_checker.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment3/Q2-parity-checker/A3Q2_parity_checker_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment3/Q2-parity-checker/A3Q2_parity_checker_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n   #29  \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment3/Q2-parity-checker/A3Q2_parity_checker_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n   #1 reset=0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment3/Q2-parity-checker/A3Q2_parity_checker_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #5 clk=~clk;\n    ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n'
module clock_module(clk);
	output reg clk=1'b1;
	initial begin
		repeat(8) begin
			repeat(6) begin
				#5 clk=~clk;
			end
		end
	end
endmodule
module clock_module(clk);

	output reg clk=1'b1;
	initial begin
		repeat(8) begin
			repeat(6) begin
				#5 clk=~clk;
			end
		end
	end
endmodule