data/full_repos/permissive/49989726/cordic.v
1: b'%Error: data/full_repos/permissive/49989726/cordic.v:1: Cannot find include file: cordic.vh\n`include "cordic.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/49989726,data/full_repos/permissive/49989726/cordic.vh\n             data/full_repos/permissive/49989726,data/full_repos/permissive/49989726/cordic.vh.v\n             data/full_repos/permissive/49989726,data/full_repos/permissive/49989726/cordic.vh.sv\n             cordic.vh\n             cordic.vh.v\n             cordic.vh.sv\n             obj_dir/cordic.vh\n             obj_dir/cordic.vh.v\n             obj_dir/cordic.vh.sv\n%Error: data/full_repos/permissive/49989726/cordic.v:7: Define or directive not defined: \'`MOD_CIR\'\n  parameter MOD = `MOD_CIR,  \n                  ^~~~~~~~\n%Error: data/full_repos/permissive/49989726/cordic.v:7: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  parameter MOD = `MOD_CIR,  \n                          ^\n%Error: data/full_repos/permissive/49989726/cordic.v:8: Define or directive not defined: \'`DIR_ROT\'\n  parameter DIR = `DIR_ROT  \n                  ^~~~~~~~\n%Error: data/full_repos/permissive/49989726/cordic.v:9: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n)\n^\n%Error: data/full_repos/permissive/49989726/cordic.v:26: syntax error, unexpected input\n  input clk;\n  ^~~~~\n%Error: data/full_repos/permissive/49989726/cordic.v:57: syntax error, unexpected IDENTIFIER\n  alpha_table\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/49989726/cordic.v:70: Define or directive not defined: \'`DIR_ROT\'\n    if(DIR==`DIR_ROT) begin\n            ^~~~~~~~\n%Error: data/full_repos/permissive/49989726/cordic.v:107: Define or directive not defined: \'`MOD_HYP\'\n      if(MOD==`MOD_HYP) begin\n              ^~~~~~~~\n%Error: data/full_repos/permissive/49989726/cordic.v:109: Define or directive not defined: \'`MOD_LIN\'\n      end else if(MOD==`MOD_LIN) begin\n                       ^~~~~~~~\n%Error: data/full_repos/permissive/49989726/cordic.v:117: Define or directive not defined: \'`MOD_HYP\'\n      if(MOD==`MOD_HYP) begin\n              ^~~~~~~~\n%Error: data/full_repos/permissive/49989726/cordic.v:119: Define or directive not defined: \'`MOD_LIN\'\n      end else if(MOD==`MOD_LIN) begin\n                       ^~~~~~~~\n%Error: Exiting due to 12 error(s)\n'
module cordic
#(
  parameter DEC = 2,
  parameter FRAC = 14,
  parameter MOD = `MOD_CIR,
  parameter DIR = `DIR_ROT
)
(
  clk,
  rst,
  x,
  y,
  z,
  a,
  b,
  c,
  done
);
  
  localparam L = DEC + FRAC;
  localparam ITER = FRAC + 1;
  localparam LOG_ITER = $clog2(ITER);

  input clk;
  input rst;
  input  [L-1:0] x;
  input  [L-1:0] y;
  input  [L-1:0] z;
  output [L-1:0] a;
  output [L-1:0] b;
  output [L-1:0] c;
  output done;


  reg [L-1:0] xi;
  reg [L-1:0] yi;
  reg [L-1:0] zi;
  reg [L-1:0] xd;
  reg [L-1:0] yd;
  reg [L-1:0] zd;
  wire [L-1:0] xs;
  wire [L-1:0] ys;
  wire [L-1:0] xi_next;
  wire [L-1:0] yi_next;
  wire [L-1:0] zi_next;

  reg [LOG_ITER:0] iter;

  wire [L-1:0] alphai;
  wire di;
  wire [1:0] mu;



  alpha_table
  #( 
    .DEC(DEC),
    .FRAC(FRAC),
    .MOD(MOD)
  )
  _alpha_table
  (
    .iter(iter[LOG_ITER-1:0]),
    .alphai(alphai)
  );

  generate
    if(DIR==`DIR_ROT) begin
      assign di = zi[L-1];
    end else begin
      assign di = xi[L-1]&yi[L-1];
    end
  endgenerate
  




  barrel_shifter_left
  #(
    .N(L)
  )
  _barrel_shifter_left_1
  (
    .a(xi),
    .shift(iter),
    .o(xs)
  );

  barrel_shifter_left
  #(
    .N(L)
  )
  _barrel_shifter_left_2
  (
    .a(yi),
    .shift(iter),
    .o(ys)
  );

  always @(*) begin
    if(di==0) begin
      yd = xs;
      zd = -alphai;
      if(MOD==`MOD_HYP) begin
        xd = ys;
      end else if(MOD==`MOD_LIN) begin
        xd = 0;
      end else begin
        xd = -ys;
      end
    end else begin
      yd = -xs;
      zd = alphai;
      if(MOD==`MOD_HYP) begin
        xd = -ys;
      end else if(MOD==`MOD_LIN) begin
        xd = 0;
      end else begin
        xd = ys;
      end
    end
  end

  assign xi_next = xi + xd;
  assign yi_next = yi + yd;
  assign zi_next = zi + zd;



  always @(posedge clk or posedge rst) begin
    if (rst) begin
      xi <= x;
      yi <= y;
      zi <= z;
      iter <= 0;
    end else begin
      if(iter < ITER) begin
        iter <= iter + 1;
        xi <= xi_next;
        yi <= yi_next;
        zi <= zi_next;
      end
    end
  end

  assign a = xi;
  assign b = yi;
  assign c = zi;


  assign done = (iter == ITER);

endmodule
module cordic
#(
  parameter DEC = 2,
  parameter FRAC = 14,
  parameter MOD = `MOD_CIR,
  parameter DIR = `DIR_ROT
)
(
  clk,
  rst,
  x,
  y,
  z,
  a,
  b,
  c,
  done
);

  
  localparam L = DEC + FRAC;
  localparam ITER = FRAC + 1;
  localparam LOG_ITER = $clog2(ITER);

  input clk;
  input rst;
  input  [L-1:0] x;
  input  [L-1:0] y;
  input  [L-1:0] z;
  output [L-1:0] a;
  output [L-1:0] b;
  output [L-1:0] c;
  output done;


  reg [L-1:0] xi;
  reg [L-1:0] yi;
  reg [L-1:0] zi;
  reg [L-1:0] xd;
  reg [L-1:0] yd;
  reg [L-1:0] zd;
  wire [L-1:0] xs;
  wire [L-1:0] ys;
  wire [L-1:0] xi_next;
  wire [L-1:0] yi_next;
  wire [L-1:0] zi_next;

  reg [LOG_ITER:0] iter;

  wire [L-1:0] alphai;
  wire di;
  wire [1:0] mu;



  alpha_table
  #( 
    .DEC(DEC),
    .FRAC(FRAC),
    .MOD(MOD)
  )
  _alpha_table
  (
    .iter(iter[LOG_ITER-1:0]),
    .alphai(alphai)
  );

  generate
    if(DIR==`DIR_ROT) begin
      assign di = zi[L-1];
    end else begin
      assign di = xi[L-1]&yi[L-1];
    end
  endgenerate
  




  barrel_shifter_left
  #(
    .N(L)
  )
  _barrel_shifter_left_1
  (
    .a(xi),
    .shift(iter),
    .o(xs)
  );

  barrel_shifter_left
  #(
    .N(L)
  )
  _barrel_shifter_left_2
  (
    .a(yi),
    .shift(iter),
    .o(ys)
  );

  always @(*) begin
    if(di==0) begin
      yd = xs;
      zd = -alphai;
      if(MOD==`MOD_HYP) begin
        xd = ys;
      end else if(MOD==`MOD_LIN) begin
        xd = 0;
      end else begin
        xd = -ys;
      end
    end else begin
      yd = -xs;
      zd = alphai;
      if(MOD==`MOD_HYP) begin
        xd = -ys;
      end else if(MOD==`MOD_LIN) begin
        xd = 0;
      end else begin
        xd = ys;
      end
    end
  end

  assign xi_next = xi + xd;
  assign yi_next = yi + yd;
  assign zi_next = zi + zd;



  always @(posedge clk or posedge rst) begin
    if (rst) begin
      xi <= x;
      yi <= y;
      zi <= z;
      iter <= 0;
    end else begin
      if(iter < ITER) begin
        iter <= iter + 1;
        xi <= xi_next;
        yi <= yi_next;
        zi <= zi_next;
      end
    end
  end

  assign a = xi;
  assign b = yi;
  assign c = zi;


  assign done = (iter == ITER);

endmodule