data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld/ctrlport_to_spi.v
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld/ctrlport_to_spi.v:49: Cannot find include file: ../../../lib/rfnoc/core/ctrlport.vh\n  `include "../../../lib/rfnoc/core/ctrlport.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld,data/full_repos/permissive/447976230/../../../lib/rfnoc/core/ctrlport.vh\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld,data/full_repos/permissive/447976230/../../../lib/rfnoc/core/ctrlport.vh.v\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld,data/full_repos/permissive/447976230/../../../lib/rfnoc/core/ctrlport.vh.sv\n             ../../../lib/rfnoc/core/ctrlport.vh\n             ../../../lib/rfnoc/core/ctrlport.vh.v\n             ../../../lib/rfnoc/core/ctrlport.vh.sv\n             obj_dir/../../../lib/rfnoc/core/ctrlport.vh\n             obj_dir/../../../lib/rfnoc/core/ctrlport.vh.v\n             obj_dir/../../../lib/rfnoc/core/ctrlport.vh.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld/ctrlport_to_spi.v:50: Cannot find include file: ./regmap/spi_regmap_utils.vh\n  `include "./regmap/spi_regmap_utils.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module ctrlport_to_spi #(
  parameter BASE_ADDRESS = 0
) (




  input  wire        ctrlport_clk,
  input  wire        ctrlport_rst,

  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [31:0] s_ctrlport_req_data,

  output reg         s_ctrlport_resp_ack,
  output reg  [ 1:0] s_ctrlport_resp_status  = 0,
  output reg  [31:0] s_ctrlport_resp_data    = 0,





  output wire        sclk,
  output wire        mosi,
  output wire [15:0] ss,
  input  wire        miso
);

  `include "../../../lib/rfnoc/core/ctrlport.vh"
  `include "./regmap/spi_regmap_utils.vh"





  reg         wb_cyc_i;
  reg         wb_we_i  = 1'b0;
  reg  [ 4:0] wb_adr_i = 5'b0;
  reg  [31:0] wb_dat_i = 32'b0;
  wire        wb_ack_o;
  wire [31:0] wb_dat_o;
  wire        wb_err_o;


  localparam NUM_ADDRESSES = 32;
  wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) &&
                          (s_ctrlport_req_addr < BASE_ADDRESS + NUM_ADDRESSES);



  always @(posedge ctrlport_clk) begin

    if (ctrlport_rst) begin
      wb_cyc_i <= 1'b0;
      s_ctrlport_resp_ack <= 1'b0;

    end else begin

      s_ctrlport_resp_ack <= 1'b0;


      if (wb_cyc_i) begin
        if (wb_ack_o) begin

          wb_cyc_i <= 1'b0;
          s_ctrlport_resp_ack  <= 1'b1;
          s_ctrlport_resp_data <= wb_dat_o;

          if (wb_err_o) begin
            s_ctrlport_resp_status <= CTRL_STS_CMDERR;
          end else begin
            s_ctrlport_resp_status <= CTRL_STS_OKAY;
          end
        end


      end else if (s_ctrlport_req_wr) begin

        wb_cyc_i <= 1'b1;
        wb_we_i <= 1'b1;
        wb_dat_i <= s_ctrlport_req_data;

        case (s_ctrlport_req_addr)
          BASE_ADDRESS + TX_DATA_LOW: begin
            wb_adr_i <= 5'h00;
          end

          BASE_ADDRESS + TX_DATA_HIGH: begin
            wb_adr_i <= 5'h04;
          end

          BASE_ADDRESS + CONTROL: begin
            wb_adr_i <= 5'h10;
          end

          BASE_ADDRESS + CLOCK_DIVIDER: begin
            wb_adr_i <= 5'h14;
          end

          BASE_ADDRESS + SLAVE_SELECT: begin
            wb_adr_i <= 5'h18;
          end


          default: begin
            wb_cyc_i <= 1'b0;

            if (address_in_range) begin
              s_ctrlport_resp_status <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack <= 1'b0;
            end
          end
        endcase


      end else if (s_ctrlport_req_rd) begin

        wb_cyc_i <= 1'b1;
        wb_we_i <= 1'b0;

        case (s_ctrlport_req_addr)
          BASE_ADDRESS + RX_DATA_LOW: begin
            wb_adr_i <= 5'h00;
          end

          BASE_ADDRESS + RX_DATA_HIGH: begin
            wb_adr_i <= 5'h04;
          end

          BASE_ADDRESS + CONTROL: begin
            wb_adr_i <= 5'h10;
          end

          BASE_ADDRESS + CLOCK_DIVIDER: begin
            wb_adr_i <= 5'h14;
          end

          BASE_ADDRESS + SLAVE_SELECT: begin
            wb_adr_i <= 5'h18;
          end


          default: begin
            wb_cyc_i <= 1'b0;

            if (address_in_range) begin
              s_ctrlport_resp_status <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack <= 1'b0;
            end
          end
        endcase


      end else begin
        s_ctrlport_resp_ack <= 1'b0;
      end
    end
  end





  spi_top spi_master (
    .wb_clk_i   (ctrlport_clk),
    .wb_rst_i   (ctrlport_rst),
    .wb_adr_i   (wb_adr_i),
    .wb_dat_i   (wb_dat_i),
    .wb_dat_o   (wb_dat_o),
    .wb_sel_i   (4'hF),
    .wb_we_i    (wb_we_i),
    .wb_stb_i   (wb_cyc_i),
    .wb_cyc_i   (wb_cyc_i),
    .wb_ack_o   (wb_ack_o),
    .wb_err_o   (wb_err_o),
    .wb_int_o   (),
    .ss_pad_o   (ss),
    .sclk_pad_o (sclk),
    .mosi_pad_o (mosi),
    .miso_pad_i (miso)
  );

endmodule
module ctrlport_to_spi #(
  parameter BASE_ADDRESS = 0
) (




  input  wire        ctrlport_clk,
  input  wire        ctrlport_rst,

  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [31:0] s_ctrlport_req_data,

  output reg         s_ctrlport_resp_ack,
  output reg  [ 1:0] s_ctrlport_resp_status  = 0,
  output reg  [31:0] s_ctrlport_resp_data    = 0,





  output wire        sclk,
  output wire        mosi,
  output wire [15:0] ss,
  input  wire        miso
);


  `include "../../../lib/rfnoc/core/ctrlport.vh"
  `include "./regmap/spi_regmap_utils.vh"





  reg         wb_cyc_i;
  reg         wb_we_i  = 1'b0;
  reg  [ 4:0] wb_adr_i = 5'b0;
  reg  [31:0] wb_dat_i = 32'b0;
  wire        wb_ack_o;
  wire [31:0] wb_dat_o;
  wire        wb_err_o;


  localparam NUM_ADDRESSES = 32;
  wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) &&
                          (s_ctrlport_req_addr < BASE_ADDRESS + NUM_ADDRESSES);



  always @(posedge ctrlport_clk) begin

    if (ctrlport_rst) begin
      wb_cyc_i <= 1'b0;
      s_ctrlport_resp_ack <= 1'b0;

    end else begin

      s_ctrlport_resp_ack <= 1'b0;


      if (wb_cyc_i) begin
        if (wb_ack_o) begin

          wb_cyc_i <= 1'b0;
          s_ctrlport_resp_ack  <= 1'b1;
          s_ctrlport_resp_data <= wb_dat_o;

          if (wb_err_o) begin
            s_ctrlport_resp_status <= CTRL_STS_CMDERR;
          end else begin
            s_ctrlport_resp_status <= CTRL_STS_OKAY;
          end
        end


      end else if (s_ctrlport_req_wr) begin

        wb_cyc_i <= 1'b1;
        wb_we_i <= 1'b1;
        wb_dat_i <= s_ctrlport_req_data;

        case (s_ctrlport_req_addr)
          BASE_ADDRESS + TX_DATA_LOW: begin
            wb_adr_i <= 5'h00;
          end

          BASE_ADDRESS + TX_DATA_HIGH: begin
            wb_adr_i <= 5'h04;
          end

          BASE_ADDRESS + CONTROL: begin
            wb_adr_i <= 5'h10;
          end

          BASE_ADDRESS + CLOCK_DIVIDER: begin
            wb_adr_i <= 5'h14;
          end

          BASE_ADDRESS + SLAVE_SELECT: begin
            wb_adr_i <= 5'h18;
          end


          default: begin
            wb_cyc_i <= 1'b0;

            if (address_in_range) begin
              s_ctrlport_resp_status <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack <= 1'b0;
            end
          end
        endcase


      end else if (s_ctrlport_req_rd) begin

        wb_cyc_i <= 1'b1;
        wb_we_i <= 1'b0;

        case (s_ctrlport_req_addr)
          BASE_ADDRESS + RX_DATA_LOW: begin
            wb_adr_i <= 5'h00;
          end

          BASE_ADDRESS + RX_DATA_HIGH: begin
            wb_adr_i <= 5'h04;
          end

          BASE_ADDRESS + CONTROL: begin
            wb_adr_i <= 5'h10;
          end

          BASE_ADDRESS + CLOCK_DIVIDER: begin
            wb_adr_i <= 5'h14;
          end

          BASE_ADDRESS + SLAVE_SELECT: begin
            wb_adr_i <= 5'h18;
          end


          default: begin
            wb_cyc_i <= 1'b0;

            if (address_in_range) begin
              s_ctrlport_resp_status <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack <= 1'b0;
            end
          end
        endcase


      end else begin
        s_ctrlport_resp_ack <= 1'b0;
      end
    end
  end





  spi_top spi_master (
    .wb_clk_i   (ctrlport_clk),
    .wb_rst_i   (ctrlport_rst),
    .wb_adr_i   (wb_adr_i),
    .wb_dat_i   (wb_dat_i),
    .wb_dat_o   (wb_dat_o),
    .wb_sel_i   (4'hF),
    .wb_we_i    (wb_we_i),
    .wb_stb_i   (wb_cyc_i),
    .wb_cyc_i   (wb_cyc_i),
    .wb_ack_o   (wb_ack_o),
    .wb_err_o   (wb_err_o),
    .wb_int_o   (),
    .ss_pad_o   (ss),
    .sclk_pad_o (sclk),
    .mosi_pad_o (mosi),
    .miso_pad_i (miso)
  );

endmodule