data/full_repos/permissive/425106492/rtl/adc1410.v
1: b"%Error: data/full_repos/permissive/425106492/rtl/adc1410.v:64: Cannot find file containing module: 'ZmodADC1410_Controller_0'\n    ZmodADC1410_Controller_0\n    ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/425106492/rtl,data/full_repos/permissive/425106492/ZmodADC1410_Controller_0\n             data/full_repos/permissive/425106492/rtl,data/full_repos/permissive/425106492/ZmodADC1410_Controller_0.v\n             data/full_repos/permissive/425106492/rtl,data/full_repos/permissive/425106492/ZmodADC1410_Controller_0.sv\n             ZmodADC1410_Controller_0\n             ZmodADC1410_Controller_0.v\n             ZmodADC1410_Controller_0.sv\n             obj_dir/ZmodADC1410_Controller_0\n             obj_dir/ZmodADC1410_Controller_0.v\n             obj_dir/ZmodADC1410_Controller_0.sv\n%Error: Exiting due to 1 error(s)\n"
module adc1410 #
(
    parameter   ZMOD_DATA_SIZE      = 14
)
(
    input  wire                                 i_sys_clock,
    input  wire                                 i_adc_clock,
    input  wire                                 i_reset,
    input  wire [ ZMOD_DATA_SIZE    - 1 : 0 ]   i_adc_data,
    inout  wire                                 io_adc_sdio,
    input  wire                                 i_adc_dco_clock_p,
    output wire                                 o_adc_dco_clock_n,
    output wire                                 o_adc_sclk,
    output wire                                 o_adc_clock_in_n,
    output wire                                 o_adc_clock_in_p,
    output wire                                 o_adc_ch1_coupling_h,
    output wire                                 o_adc_ch1_coupling_l,
    output wire                                 o_adc_ch2_coupling_h,
    output wire                                 o_adc_ch2_coupling_l,
    output wire                                 o_adc_ch2_gain_h,
    output wire                                 o_adc_ch2_gain_l,
    output wire                                 o_adc_ch1_gain_l,
    output wire                                 o_adc_ch1_gain_h,
    output wire                                 o_adc_relay_com_l,
    output wire                                 o_adc_relay_com_h,
    output wire                                 o_adc_cs,
    output wire                                 o_adc_sync,
    output wire [ ZMOD_DATA_SIZE    - 1 : 0 ]   o_adc_data_out_ch1,
    output wire [ ZMOD_DATA_SIZE    - 1 : 0 ]   o_adc_data_out_ch2,
    output wire                                 o_adc_init_done
);
    
    localparam ADC_OUT_DATA_SIZE    = 16;
    
    wire                                test_mode;
    wire                                init_done;
    wire [ ADC_OUT_DATA_SIZE - 1 : 0 ]  data_out_ch1;
    wire [ ADC_OUT_DATA_SIZE - 1 : 0 ]  data_out_ch2;
    
    assign test_mode            = 1'b0;
    assign o_adc_dco_clock_n    = 1'b0;
    assign o_adc_init_done      = ~init_done;
    assign o_adc_data_out_ch1   = data_out_ch1[ 15 : 2 ];
    assign o_adc_data_out_ch2   = data_out_ch2[ 15 : 2 ];
    

    ZmodADC1410_Controller_0
    u_ZmodADC1410_Controller_0
    (
        .SysClk             ( i_sys_clock           ),
        .ADC_InClk          ( i_adc_clock           ),
        .sRst_n             ( ~i_reset              ),
        .sInitDone_n        ( init_done             ),
        .FIFO_EMPTY_CHA     (                       ),
        .FIFO_EMPTY_CHB     (                       ),
        .sCh1Out            ( data_out_ch1          ),
        .sCh2Out            ( data_out_ch2          ),
        .sTestMode          ( test_mode             ),
        .adcClkIn_p         ( o_adc_clock_in_p      ),
        .adcClkIn_n         ( o_adc_clock_in_n      ),
        .adcSync            ( o_adc_sync            ),
        .DcoClk             ( i_adc_dco_clock_p     ),
        .dADC_Data          ( i_adc_data            ),
        .sADC_SDIO          ( io_adc_sdio           ),
        .sADC_CS            ( o_adc_cs              ),
        .sADC_Sclk          ( o_adc_sclk            ),
        .sCh1CouplingH      ( o_adc_ch1_coupling_h  ),
        .sCh1CouplingL      ( o_adc_ch1_coupling_l  ),
        .sCh2CouplingH      ( o_adc_ch2_coupling_h  ),
        .sCh2CouplingL      ( o_adc_ch2_coupling_l  ),
        .sCh1GainH          ( o_adc_ch1_gain_h      ),
        .sCh1GainL          ( o_adc_ch1_gain_l      ),
        .sCh2GainH          ( o_adc_ch2_gain_h      ),
        .sCh2GainL          ( o_adc_ch2_gain_l      ),
        .sRelayComH         ( o_adc_relay_com_h     ),
        .sRelayComL         ( o_adc_relay_com_l     )
    );
    
endmodule
module adc1410 #
(
    parameter   ZMOD_DATA_SIZE      = 14
)
(
    input  wire                                 i_sys_clock,
    input  wire                                 i_adc_clock,
    input  wire                                 i_reset,
    input  wire [ ZMOD_DATA_SIZE    - 1 : 0 ]   i_adc_data,
    inout  wire                                 io_adc_sdio,
    input  wire                                 i_adc_dco_clock_p,
    output wire                                 o_adc_dco_clock_n,
    output wire                                 o_adc_sclk,
    output wire                                 o_adc_clock_in_n,
    output wire                                 o_adc_clock_in_p,
    output wire                                 o_adc_ch1_coupling_h,
    output wire                                 o_adc_ch1_coupling_l,
    output wire                                 o_adc_ch2_coupling_h,
    output wire                                 o_adc_ch2_coupling_l,
    output wire                                 o_adc_ch2_gain_h,
    output wire                                 o_adc_ch2_gain_l,
    output wire                                 o_adc_ch1_gain_l,
    output wire                                 o_adc_ch1_gain_h,
    output wire                                 o_adc_relay_com_l,
    output wire                                 o_adc_relay_com_h,
    output wire                                 o_adc_cs,
    output wire                                 o_adc_sync,
    output wire [ ZMOD_DATA_SIZE    - 1 : 0 ]   o_adc_data_out_ch1,
    output wire [ ZMOD_DATA_SIZE    - 1 : 0 ]   o_adc_data_out_ch2,
    output wire                                 o_adc_init_done
);

    
    localparam ADC_OUT_DATA_SIZE    = 16;
    
    wire                                test_mode;
    wire                                init_done;
    wire [ ADC_OUT_DATA_SIZE - 1 : 0 ]  data_out_ch1;
    wire [ ADC_OUT_DATA_SIZE - 1 : 0 ]  data_out_ch2;
    
    assign test_mode            = 1'b0;
    assign o_adc_dco_clock_n    = 1'b0;
    assign o_adc_init_done      = ~init_done;
    assign o_adc_data_out_ch1   = data_out_ch1[ 15 : 2 ];
    assign o_adc_data_out_ch2   = data_out_ch2[ 15 : 2 ];
    

    ZmodADC1410_Controller_0
    u_ZmodADC1410_Controller_0
    (
        .SysClk             ( i_sys_clock           ),
        .ADC_InClk          ( i_adc_clock           ),
        .sRst_n             ( ~i_reset              ),
        .sInitDone_n        ( init_done             ),
        .FIFO_EMPTY_CHA     (                       ),
        .FIFO_EMPTY_CHB     (                       ),
        .sCh1Out            ( data_out_ch1          ),
        .sCh2Out            ( data_out_ch2          ),
        .sTestMode          ( test_mode             ),
        .adcClkIn_p         ( o_adc_clock_in_p      ),
        .adcClkIn_n         ( o_adc_clock_in_n      ),
        .adcSync            ( o_adc_sync            ),
        .DcoClk             ( i_adc_dco_clock_p     ),
        .dADC_Data          ( i_adc_data            ),
        .sADC_SDIO          ( io_adc_sdio           ),
        .sADC_CS            ( o_adc_cs              ),
        .sADC_Sclk          ( o_adc_sclk            ),
        .sCh1CouplingH      ( o_adc_ch1_coupling_h  ),
        .sCh1CouplingL      ( o_adc_ch1_coupling_l  ),
        .sCh2CouplingH      ( o_adc_ch2_coupling_h  ),
        .sCh2CouplingL      ( o_adc_ch2_coupling_l  ),
        .sCh1GainH          ( o_adc_ch1_gain_h      ),
        .sCh1GainL          ( o_adc_ch1_gain_l      ),
        .sCh2GainH          ( o_adc_ch2_gain_h      ),
        .sCh2GainL          ( o_adc_ch2_gain_l      ),
        .sRelayComH         ( o_adc_relay_com_h     ),
        .sRelayComL         ( o_adc_relay_com_l     )
    );
    
endmodule