data/full_repos/permissive/458737381/src/verilog-parser/tests/ccx_spc_rpt.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ccx_spc_rpt.v:21: Cannot find include file: sys.h\n`include "sys.h" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ccx_spc_rpt.v:22: Cannot find include file: iop.h\n`include "iop.h" \n         ^~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ccx_spc_rpt.v:37: Define or directive not defined: \'`PCX_WIDTH\'\ninput  [`PCX_WIDTH-1:0] spc_pcx_data_pa;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ccx_spc_rpt.v:40: Define or directive not defined: \'`CPX_WIDTH\'\ninput  [`CPX_WIDTH-1:0] cpx_spc_data_cx2;      \n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ccx_spc_rpt.v:45: Define or directive not defined: \'`PCX_WIDTH\'\noutput [`PCX_WIDTH-1:0] spc_pcx_data_pa_buf;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ccx_spc_rpt.v:48: Define or directive not defined: \'`CPX_WIDTH\'\noutput [`CPX_WIDTH-1:0] cpx_spc_data_cx2_buf;\n        ^~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n'
module ccx_spc_rpt (

   spc_pcx_req_pq_buf, spc_pcx_atom_pq_buf, spc_pcx_data_pa_buf, 
   pcx_spc_grant_px_buf, cpx_spc_data_cx2_buf, 
   cpx_spc_data_rdy_cx2_buf, 

   spc_pcx_req_pq, spc_pcx_atom_pq, spc_pcx_data_pa, 
   pcx_spc_grant_px, cpx_spc_data_cx2, cpx_spc_data_rdy_cx2
   );


input  [4:0]            spc_pcx_req_pq;
input                   spc_pcx_atom_pq;
input  [`PCX_WIDTH-1:0] spc_pcx_data_pa;
input  [4:0]            pcx_spc_grant_px;
   
input  [`CPX_WIDTH-1:0] cpx_spc_data_cx2;      
input                   cpx_spc_data_rdy_cx2;

output [4:0]            spc_pcx_req_pq_buf;
output                  spc_pcx_atom_pq_buf;
output [`PCX_WIDTH-1:0] spc_pcx_data_pa_buf;
output  [4:0]            pcx_spc_grant_px_buf;
   
output [`CPX_WIDTH-1:0] cpx_spc_data_cx2_buf;
output                  cpx_spc_data_rdy_cx2_buf;    

   
assign  spc_pcx_req_pq_buf  =  spc_pcx_req_pq;
assign  spc_pcx_atom_pq_buf  =  spc_pcx_atom_pq;
assign  spc_pcx_data_pa_buf   =  spc_pcx_data_pa;
assign  pcx_spc_grant_px_buf  =  pcx_spc_grant_px;
assign  cpx_spc_data_cx2_buf  =  cpx_spc_data_cx2;
assign  cpx_spc_data_rdy_cx2_buf  =  cpx_spc_data_rdy_cx2;


endmodule
module ccx_spc_rpt (

   spc_pcx_req_pq_buf, spc_pcx_atom_pq_buf, spc_pcx_data_pa_buf, 
   pcx_spc_grant_px_buf, cpx_spc_data_cx2_buf, 
   cpx_spc_data_rdy_cx2_buf, 

   spc_pcx_req_pq, spc_pcx_atom_pq, spc_pcx_data_pa, 
   pcx_spc_grant_px, cpx_spc_data_cx2, cpx_spc_data_rdy_cx2
   );



input  [4:0]            spc_pcx_req_pq;
input                   spc_pcx_atom_pq;
input  [`PCX_WIDTH-1:0] spc_pcx_data_pa;
input  [4:0]            pcx_spc_grant_px;
   
input  [`CPX_WIDTH-1:0] cpx_spc_data_cx2;      
input                   cpx_spc_data_rdy_cx2;

output [4:0]            spc_pcx_req_pq_buf;
output                  spc_pcx_atom_pq_buf;
output [`PCX_WIDTH-1:0] spc_pcx_data_pa_buf;
output  [4:0]            pcx_spc_grant_px_buf;
   
output [`CPX_WIDTH-1:0] cpx_spc_data_cx2_buf;
output                  cpx_spc_data_rdy_cx2_buf;    

   
assign  spc_pcx_req_pq_buf  =  spc_pcx_req_pq;
assign  spc_pcx_atom_pq_buf  =  spc_pcx_atom_pq;
assign  spc_pcx_data_pa_buf   =  spc_pcx_data_pa;
assign  pcx_spc_grant_px_buf  =  pcx_spc_grant_px;
assign  cpx_spc_data_cx2_buf  =  cpx_spc_data_cx2;
assign  cpx_spc_data_rdy_cx2_buf  =  cpx_spc_data_rdy_cx2;


endmodule