data/full_repos/permissive/500396778/3-Bit-Synchronous-Up-Down-Counter/Down_tb.v
1: b'%Error: data/full_repos/permissive/500396778/3-Bit-Synchronous-Up-Down-Counter/Down_tb.v:11: Unsupported or unknown PLI call: $dumpfile\n  initial begin $dumpfile("down.vcd"); $dumpvars(0,tb); end\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/500396778/3-Bit-Synchronous-Up-Down-Counter/Down_tb.v:11: Unsupported or unknown PLI call: $dumpvars\n  initial begin $dumpfile("down.vcd"); $dumpvars(0,tb); end\n                                       ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/500396778/3-Bit-Synchronous-Up-Down-Counter/Down_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk =~ clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/500396778/3-Bit-Synchronous-Up-Down-Counter/Down_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n      begin #10 \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/500396778/3-Bit-Synchronous-Up-Down-Counter/Down_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #6 for(i=0;i<7;i=i+1)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/500396778/3-Bit-Synchronous-Up-Down-Counter/Down_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #100 $finish;\n    ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;
  reg clk, set;
  reg inc; reg count;
  wire [2:0] q; wire cout;
wire [1:0]y;
  integer i;
  initial begin $dumpfile("down.vcd"); $dumpvars(0,tb); end

  initial begin set = 1'b1;count=1'b1;inc= 1'b1;end
  
  initial clk = 1'b0; always 
	 #5 clk =~ clk;
  
  bit3 b1(.clk(clk),.set(set),.count(count),.inc(inc),.cout(cout),.q(q));
  initial begin
    #6 for(i=0;i<`TESTVECS;i=i+1)
      begin #10 
	 set=0'b0; 
	end
    #100 $finish;
  end
endmodule
module tb;

  reg clk, set;
  reg inc; reg count;
  wire [2:0] q; wire cout;
wire [1:0]y;
  integer i;
  initial begin $dumpfile("down.vcd"); $dumpvars(0,tb); end

  initial begin set = 1'b1;count=1'b1;inc= 1'b1;end
  
  initial clk = 1'b0; always 
	 #5 clk =~ clk;
  
  bit3 b1(.clk(clk),.set(set),.count(count),.inc(inc),.cout(cout),.q(q));
  initial begin
    #6 for(i=0;i<`TESTVECS;i=i+1)
      begin #10 
	 set=0'b0; 
	end
    #100 $finish;
  end
endmodule