data/full_repos/permissive/502544928/ra_mem_system_wrapper.v
1: b"%Error: data/full_repos/permissive/502544928/ra_mem_system_wrapper.v:159: Cannot find file containing module: 'ra_core_interface'\nra_core_interface #(CORE, ID_BITS, REAL_ADDR_BITS, DATA_WIDTH, ADDRESS_BITS) core_inter(\n^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502544928,data/full_repos/permissive/502544928/ra_core_interface\n             data/full_repos/permissive/502544928,data/full_repos/permissive/502544928/ra_core_interface.v\n             data/full_repos/permissive/502544928,data/full_repos/permissive/502544928/ra_core_interface.sv\n             ra_core_interface\n             ra_core_interface.v\n             ra_core_interface.sv\n             obj_dir/ra_core_interface\n             obj_dir/ra_core_interface.v\n             obj_dir/ra_core_interface.sv\n%Error: data/full_repos/permissive/502544928/ra_mem_system_wrapper.v:201: Cannot find file containing module: 'ra_cache_interface'\nra_cache_interface #(CORE, ID_BITS, REAL_ADDR_BITS, DATA_WIDTH, ADDRESS_BITS) cache_inter (\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502544928/ra_mem_system_wrapper.v:236: Cannot find file containing module: 'ra_packetizer'\nra_packetizer #(CORE, DATA_WIDTH, ADDRESS_BITS, REAL_ADDR_BITS, \n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502544928/ra_mem_system_wrapper.v:275: Cannot find file containing module: 'unified_caches'\nunified_caches #(CORE, DATA_WIDTH, INDEX_BITS, OFFSET_BITS, ADDRESS_BITS, MSG_BITS) \n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502544928/ra_mem_system_wrapper.v:290: Cannot find file containing module: 'main_memory'\nmain_memory #(CORE, DATA_WIDTH, ADDRESS_BITS, REAL_ADDR_BITS, NUM_CACHES, MSG_BITS, OFFSET_BITS, INIT_FILE) \n^~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module ra_mem_system_wrapper #(parameter CORE = 0, ID_BITS = 4, REAL_ADDR_BITS = 16, 
							DATA_WIDTH = 32, INDEX_BITS = 6, OFFSET_BITS = 3, 
							ADDRESS_BITS = 32, INIT_FILE = "memory.mem",IN_PORTS = 1, 
							OUT_PORTS = 1, VC_BITS = 1, VC_DEPTH_BITS = 4,
                            MSG_BITS = 3, EXTRA  = 2, TYPE_BITS = 2)(

             		 clock, reset,  
				     i_read, i_write, 
					 i_address, i_in_data, 
					 
				     i_out_addr, i_out_data, 
					 i_valid, i_ready,
				     
				     d_read, d_write, 
					 d_address, d_in_data, 
					 
				     d_out_addr, d_out_data, 
					 d_valid, d_ready, 
				     
				     from_core_flit, v_from_core, 
				     from_core_empty, from_core_full,
  
  					 to_core_flit, v_to_core,
  					 to_core_empty, to_core_full, 

					 report
);

localparam VC_PER_PORTS    = (1 << VC_BITS); 
localparam FLOW_BITS       = (2*ID_BITS) + EXTRA;
localparam FLIT_WIDTH      = FLOW_BITS + TYPE_BITS + VC_BITS + DATA_WIDTH;
localparam NUM_CACHES      = 2;
localparam TOTAL_CORES     = 1 << ID_BITS; 
localparam MEM_ADDR_BITS   = REAL_ADDR_BITS + ID_BITS;
localparam TOTAL_MEM_SPACE = 1 << MEM_ADDR_BITS; 
localparam LOCAL_MEM_SIZE  = 1 << (MEM_ADDR_BITS - ID_BITS); 

input clock, reset;
input  i_read, i_write;
input  [ADDRESS_BITS-1:0] i_address;
input  [DATA_WIDTH-1:0] i_in_data;

output i_valid, i_ready;
output [DATA_WIDTH-1:0] i_out_data;
output [ADDRESS_BITS-1:0] i_out_addr;

input  d_read, d_write;
input  [ADDRESS_BITS-1:0] d_address;
input  [DATA_WIDTH-1:0] d_in_data;

output d_valid, d_ready;
output [DATA_WIDTH-1:0] d_out_data;
output [ADDRESS_BITS-1:0] d_out_addr;

output [(FLIT_WIDTH * IN_PORTS) -1:0] from_core_flit;
output [IN_PORTS-1: 0] v_from_core;
output [(VC_PER_PORTS * IN_PORTS) -1:0] from_core_empty;
output [(VC_PER_PORTS * IN_PORTS) -1:0] from_core_full; 
  
input  [(FLIT_WIDTH * OUT_PORTS) -1:0] to_core_flit;
input  [OUT_PORTS-1: 0] v_to_core;
input  [(VC_PER_PORTS * IN_PORTS) -1:0] to_core_empty;
input  [(VC_PER_PORTS * IN_PORTS) -1:0] to_core_full;
input  report;

wire [ID_BITS - 1: 0] core_ID = CORE; 

wire  [(MSG_BITS * NUM_CACHES)-1:0]    cache2mem_msg; 
wire [(ADDRESS_BITS * NUM_CACHES)-1:0] cache2mem_address; 
wire [(DATA_WIDTH * NUM_CACHES)-1:0]   cache2mem_data;

wire [(MSG_BITS * NUM_CACHES)-1:0]     mem2cache_msg; 
wire [(ADDRESS_BITS * NUM_CACHES)-1:0] mem2cache_address; 
wire [(DATA_WIDTH * NUM_CACHES)-1:0]   mem2cache_data;


wire  core2cache_iRead, core2cache_iWrite;
wire  [ADDRESS_BITS-1:0] core2cache_iAddr; 
wire  [DATA_WIDTH-1:0]   core2cache_iData;  

wire  [ADDRESS_BITS-1:0] cache2core_iAddr; 
wire  [DATA_WIDTH-1:0]   cache2core_iData;
wire  cache2core_iValid, cache2core_iReady;

wire  core2cache_dRead, core2cache_dWrite;
wire  [ADDRESS_BITS-1:0] core2cache_dAddr; 
wire  [DATA_WIDTH-1:0]   core2cache_dData;  
				     
wire  [ADDRESS_BITS-1:0] cache2core_dAddr; 
wire  [DATA_WIDTH-1:0]   cache2core_dData; 
wire  cache2core_dValid, cache2core_dReady;


wire  net2cache_iRead, net2cache_iWrite;
wire  [ADDRESS_BITS-1:0]net2cache_iAddr; 
wire  [DATA_WIDTH-1:0]   net2cache_iData;

wire [ADDRESS_BITS-1:0] cache2net_iAddr; 
wire [DATA_WIDTH-1:0] cache2net_iData;
wire cache2net_iValid, cache2net_iReady;

wire  net2cache_dRead, net2cache_dWrite; 
wire  [ADDRESS_BITS-1:0] net2cache_dAddr;
wire  [DATA_WIDTH-1:0]   net2cache_dData;

wire [ADDRESS_BITS-1:0] cache2net_dAddr; 
wire [DATA_WIDTH-1:0] cache2net_dData;
wire cache2net_dValid, cache2net_dReady;

wire  core2net_iRead, core2net_iWrite;
wire  [ADDRESS_BITS-1:0] core2net_iAddr; 
wire  [DATA_WIDTH-1:0]   core2net_iData;  

wire  [ADDRESS_BITS-1:0] net2core_iAddr; 
wire  [DATA_WIDTH-1:0]   net2core_iData;
wire  net2core_iValid, net2core_iReady;

wire  core2net_dRead, core2net_dWrite;
wire  [ADDRESS_BITS-1:0] core2net_dAddr; 
wire  [DATA_WIDTH-1:0]   core2net_dData;  
				     
wire  [ADDRESS_BITS-1:0] net2core_dAddr; 
wire  [DATA_WIDTH-1:0]   net2core_dData; 
wire  net2core_dValid, net2core_dReady;


wire [1:0] read, write;	  
wire [(2*ADDRESS_BITS)-1:0] address;	 
wire [(2*DATA_WIDTH)-1:0] in_data; 

wire [1:0] valid, ready;
wire[(2*DATA_WIDTH)-1:0] out_data;
wire[(2*ADDRESS_BITS)-1:0] out_address;	


ra_core_interface #(CORE, ID_BITS, REAL_ADDR_BITS, DATA_WIDTH, ADDRESS_BITS) core_inter(
             		 clock, reset, 
				     i_read, i_write, 
					 i_address, i_in_data, 
					 
				     i_out_addr, i_out_data, 
					 i_valid, i_ready,
				     
				     d_read, d_write, 
					 d_address, d_in_data, 
					 
				     d_out_addr, d_out_data, 
					 d_valid, d_ready, 
					 

					core2cache_iRead, core2cache_iWrite, 
					core2cache_iAddr, core2cache_iData, 

					cache2core_iAddr, cache2core_iData, 
					cache2core_iValid, cache2core_iReady,

					core2cache_dRead, core2cache_dWrite, 
					core2cache_dAddr, core2cache_dData, 

					cache2core_dAddr, cache2core_dData, 
					cache2core_dValid, cache2core_dReady, 
					 

				     core2net_iRead, core2net_iWrite, 
					 core2net_iAddr, core2net_iData, 
					 
				     net2core_iAddr, net2core_iData, 
					 net2core_iValid, net2core_iReady,
				     
				     core2net_dRead, core2net_dWrite, 
					 core2net_dAddr, core2net_dData, 
					 
				     net2core_dAddr, net2core_dData, 
					 net2core_dValid, net2core_dReady, 
					 report
);

ra_cache_interface #(CORE, ID_BITS, REAL_ADDR_BITS, DATA_WIDTH, ADDRESS_BITS) cache_inter (
             		 clock, reset,


					core2cache_iRead, core2cache_iWrite, 
					core2cache_iAddr, core2cache_iData, 

					cache2core_iAddr, cache2core_iData, 
					cache2core_iValid, cache2core_iReady,

					core2cache_dRead, core2cache_dWrite, 
					core2cache_dAddr, core2cache_dData, 

					cache2core_dAddr, cache2core_dData, 
					cache2core_dValid, cache2core_dReady, 
		

				     net2cache_iRead, net2cache_iWrite, 
					 net2cache_iAddr, net2cache_iData, 
					 
				     cache2net_iAddr, cache2net_iData, 
					 cache2net_iValid, cache2net_iReady,
				     
				     net2cache_dRead, net2cache_dWrite, 
					 net2cache_dAddr, net2cache_dData, 
					 
				     cache2net_dAddr, cache2net_dData, 
					 cache2net_dValid, cache2net_dReady, 
					 

					 read, write, address, in_data, 
				     out_address, out_data, valid, ready, 
					 report
);

ra_packetizer #(CORE, DATA_WIDTH, ADDRESS_BITS, REAL_ADDR_BITS, 
             MEM_ADDR_BITS, IN_PORTS, OUT_PORTS, VC_BITS, VC_DEPTH_BITS,
             ID_BITS, EXTRA, TYPE_BITS) network_packetizer (
				     clock, reset, 
				     		

				     net2cache_iRead, net2cache_iWrite, 
					 net2cache_iAddr, net2cache_iData, 
					 
				     cache2net_iAddr, cache2net_iData, 
					 cache2net_iValid, cache2net_iReady,
				     
				     net2cache_dRead, net2cache_dWrite, 
					 net2cache_dAddr, net2cache_dData, 
					 
				     cache2net_dAddr, cache2net_dData, 
					 cache2net_dValid, cache2net_dReady,
					 

				     core2net_iRead, core2net_iWrite, 
					 core2net_iAddr, core2net_iData, 
					 
				     net2core_iAddr, net2core_iData, 
					 net2core_iValid, net2core_iReady,
				     
				     core2net_dRead, core2net_dWrite, 
					 core2net_dAddr, core2net_dData, 
					 
				     net2core_dAddr, net2core_dData, 
					 net2core_dValid, net2core_dReady,
					 

				     from_core_flit, v_from_core, 
				     from_core_empty, from_core_full,
  
  					 to_core_flit, v_to_core,
  					 to_core_empty, to_core_full 
);

unified_caches #(CORE, DATA_WIDTH, INDEX_BITS, OFFSET_BITS, ADDRESS_BITS, MSG_BITS) 
             unified (
				     clock, reset,
				       
				     read, write, address, in_data, 
				     out_address, out_data, valid, ready,
				     
				     mem2cache_msg, 
				     mem2cache_address, mem2cache_data, 
				     
				     cache2mem_msg, 
				     cache2mem_address, cache2mem_data, 
					 report
); 

main_memory #(CORE, DATA_WIDTH, ADDRESS_BITS, REAL_ADDR_BITS, NUM_CACHES, MSG_BITS, OFFSET_BITS, INIT_FILE) 
              m_memory (
				     clock, reset,  
				     				     
				     cache2mem_msg, 
				     cache2mem_address, cache2mem_data,
				     
				     mem2cache_msg, 
				     mem2cache_address, mem2cache_data
);


endmodule
module ra_mem_system_wrapper #(parameter CORE = 0, ID_BITS = 4, REAL_ADDR_BITS = 16, 
							DATA_WIDTH = 32, INDEX_BITS = 6, OFFSET_BITS = 3, 
							ADDRESS_BITS = 32, INIT_FILE = "memory.mem",IN_PORTS = 1, 
							OUT_PORTS = 1, VC_BITS = 1, VC_DEPTH_BITS = 4,
                            MSG_BITS = 3, EXTRA  = 2, TYPE_BITS = 2)(

             		 clock, reset,  
				     i_read, i_write, 
					 i_address, i_in_data, 
					 
				     i_out_addr, i_out_data, 
					 i_valid, i_ready,
				     
				     d_read, d_write, 
					 d_address, d_in_data, 
					 
				     d_out_addr, d_out_data, 
					 d_valid, d_ready, 
				     
				     from_core_flit, v_from_core, 
				     from_core_empty, from_core_full,
  
  					 to_core_flit, v_to_core,
  					 to_core_empty, to_core_full, 

					 report
);


localparam VC_PER_PORTS    = (1 << VC_BITS); 
localparam FLOW_BITS       = (2*ID_BITS) + EXTRA;
localparam FLIT_WIDTH      = FLOW_BITS + TYPE_BITS + VC_BITS + DATA_WIDTH;
localparam NUM_CACHES      = 2;
localparam TOTAL_CORES     = 1 << ID_BITS; 
localparam MEM_ADDR_BITS   = REAL_ADDR_BITS + ID_BITS;
localparam TOTAL_MEM_SPACE = 1 << MEM_ADDR_BITS; 
localparam LOCAL_MEM_SIZE  = 1 << (MEM_ADDR_BITS - ID_BITS); 

input clock, reset;
input  i_read, i_write;
input  [ADDRESS_BITS-1:0] i_address;
input  [DATA_WIDTH-1:0] i_in_data;

output i_valid, i_ready;
output [DATA_WIDTH-1:0] i_out_data;
output [ADDRESS_BITS-1:0] i_out_addr;

input  d_read, d_write;
input  [ADDRESS_BITS-1:0] d_address;
input  [DATA_WIDTH-1:0] d_in_data;

output d_valid, d_ready;
output [DATA_WIDTH-1:0] d_out_data;
output [ADDRESS_BITS-1:0] d_out_addr;

output [(FLIT_WIDTH * IN_PORTS) -1:0] from_core_flit;
output [IN_PORTS-1: 0] v_from_core;
output [(VC_PER_PORTS * IN_PORTS) -1:0] from_core_empty;
output [(VC_PER_PORTS * IN_PORTS) -1:0] from_core_full; 
  
input  [(FLIT_WIDTH * OUT_PORTS) -1:0] to_core_flit;
input  [OUT_PORTS-1: 0] v_to_core;
input  [(VC_PER_PORTS * IN_PORTS) -1:0] to_core_empty;
input  [(VC_PER_PORTS * IN_PORTS) -1:0] to_core_full;
input  report;

wire [ID_BITS - 1: 0] core_ID = CORE; 

wire  [(MSG_BITS * NUM_CACHES)-1:0]    cache2mem_msg; 
wire [(ADDRESS_BITS * NUM_CACHES)-1:0] cache2mem_address; 
wire [(DATA_WIDTH * NUM_CACHES)-1:0]   cache2mem_data;

wire [(MSG_BITS * NUM_CACHES)-1:0]     mem2cache_msg; 
wire [(ADDRESS_BITS * NUM_CACHES)-1:0] mem2cache_address; 
wire [(DATA_WIDTH * NUM_CACHES)-1:0]   mem2cache_data;


wire  core2cache_iRead, core2cache_iWrite;
wire  [ADDRESS_BITS-1:0] core2cache_iAddr; 
wire  [DATA_WIDTH-1:0]   core2cache_iData;  

wire  [ADDRESS_BITS-1:0] cache2core_iAddr; 
wire  [DATA_WIDTH-1:0]   cache2core_iData;
wire  cache2core_iValid, cache2core_iReady;

wire  core2cache_dRead, core2cache_dWrite;
wire  [ADDRESS_BITS-1:0] core2cache_dAddr; 
wire  [DATA_WIDTH-1:0]   core2cache_dData;  
				     
wire  [ADDRESS_BITS-1:0] cache2core_dAddr; 
wire  [DATA_WIDTH-1:0]   cache2core_dData; 
wire  cache2core_dValid, cache2core_dReady;


wire  net2cache_iRead, net2cache_iWrite;
wire  [ADDRESS_BITS-1:0]net2cache_iAddr; 
wire  [DATA_WIDTH-1:0]   net2cache_iData;

wire [ADDRESS_BITS-1:0] cache2net_iAddr; 
wire [DATA_WIDTH-1:0] cache2net_iData;
wire cache2net_iValid, cache2net_iReady;

wire  net2cache_dRead, net2cache_dWrite; 
wire  [ADDRESS_BITS-1:0] net2cache_dAddr;
wire  [DATA_WIDTH-1:0]   net2cache_dData;

wire [ADDRESS_BITS-1:0] cache2net_dAddr; 
wire [DATA_WIDTH-1:0] cache2net_dData;
wire cache2net_dValid, cache2net_dReady;

wire  core2net_iRead, core2net_iWrite;
wire  [ADDRESS_BITS-1:0] core2net_iAddr; 
wire  [DATA_WIDTH-1:0]   core2net_iData;  

wire  [ADDRESS_BITS-1:0] net2core_iAddr; 
wire  [DATA_WIDTH-1:0]   net2core_iData;
wire  net2core_iValid, net2core_iReady;

wire  core2net_dRead, core2net_dWrite;
wire  [ADDRESS_BITS-1:0] core2net_dAddr; 
wire  [DATA_WIDTH-1:0]   core2net_dData;  
				     
wire  [ADDRESS_BITS-1:0] net2core_dAddr; 
wire  [DATA_WIDTH-1:0]   net2core_dData; 
wire  net2core_dValid, net2core_dReady;


wire [1:0] read, write;	  
wire [(2*ADDRESS_BITS)-1:0] address;	 
wire [(2*DATA_WIDTH)-1:0] in_data; 

wire [1:0] valid, ready;
wire[(2*DATA_WIDTH)-1:0] out_data;
wire[(2*ADDRESS_BITS)-1:0] out_address;	


ra_core_interface #(CORE, ID_BITS, REAL_ADDR_BITS, DATA_WIDTH, ADDRESS_BITS) core_inter(
             		 clock, reset, 
				     i_read, i_write, 
					 i_address, i_in_data, 
					 
				     i_out_addr, i_out_data, 
					 i_valid, i_ready,
				     
				     d_read, d_write, 
					 d_address, d_in_data, 
					 
				     d_out_addr, d_out_data, 
					 d_valid, d_ready, 
					 

					core2cache_iRead, core2cache_iWrite, 
					core2cache_iAddr, core2cache_iData, 

					cache2core_iAddr, cache2core_iData, 
					cache2core_iValid, cache2core_iReady,

					core2cache_dRead, core2cache_dWrite, 
					core2cache_dAddr, core2cache_dData, 

					cache2core_dAddr, cache2core_dData, 
					cache2core_dValid, cache2core_dReady, 
					 

				     core2net_iRead, core2net_iWrite, 
					 core2net_iAddr, core2net_iData, 
					 
				     net2core_iAddr, net2core_iData, 
					 net2core_iValid, net2core_iReady,
				     
				     core2net_dRead, core2net_dWrite, 
					 core2net_dAddr, core2net_dData, 
					 
				     net2core_dAddr, net2core_dData, 
					 net2core_dValid, net2core_dReady, 
					 report
);

ra_cache_interface #(CORE, ID_BITS, REAL_ADDR_BITS, DATA_WIDTH, ADDRESS_BITS) cache_inter (
             		 clock, reset,


					core2cache_iRead, core2cache_iWrite, 
					core2cache_iAddr, core2cache_iData, 

					cache2core_iAddr, cache2core_iData, 
					cache2core_iValid, cache2core_iReady,

					core2cache_dRead, core2cache_dWrite, 
					core2cache_dAddr, core2cache_dData, 

					cache2core_dAddr, cache2core_dData, 
					cache2core_dValid, cache2core_dReady, 
		

				     net2cache_iRead, net2cache_iWrite, 
					 net2cache_iAddr, net2cache_iData, 
					 
				     cache2net_iAddr, cache2net_iData, 
					 cache2net_iValid, cache2net_iReady,
				     
				     net2cache_dRead, net2cache_dWrite, 
					 net2cache_dAddr, net2cache_dData, 
					 
				     cache2net_dAddr, cache2net_dData, 
					 cache2net_dValid, cache2net_dReady, 
					 

					 read, write, address, in_data, 
				     out_address, out_data, valid, ready, 
					 report
);

ra_packetizer #(CORE, DATA_WIDTH, ADDRESS_BITS, REAL_ADDR_BITS, 
             MEM_ADDR_BITS, IN_PORTS, OUT_PORTS, VC_BITS, VC_DEPTH_BITS,
             ID_BITS, EXTRA, TYPE_BITS) network_packetizer (
				     clock, reset, 
				     		

				     net2cache_iRead, net2cache_iWrite, 
					 net2cache_iAddr, net2cache_iData, 
					 
				     cache2net_iAddr, cache2net_iData, 
					 cache2net_iValid, cache2net_iReady,
				     
				     net2cache_dRead, net2cache_dWrite, 
					 net2cache_dAddr, net2cache_dData, 
					 
				     cache2net_dAddr, cache2net_dData, 
					 cache2net_dValid, cache2net_dReady,
					 

				     core2net_iRead, core2net_iWrite, 
					 core2net_iAddr, core2net_iData, 
					 
				     net2core_iAddr, net2core_iData, 
					 net2core_iValid, net2core_iReady,
				     
				     core2net_dRead, core2net_dWrite, 
					 core2net_dAddr, core2net_dData, 
					 
				     net2core_dAddr, net2core_dData, 
					 net2core_dValid, net2core_dReady,
					 

				     from_core_flit, v_from_core, 
				     from_core_empty, from_core_full,
  
  					 to_core_flit, v_to_core,
  					 to_core_empty, to_core_full 
);

unified_caches #(CORE, DATA_WIDTH, INDEX_BITS, OFFSET_BITS, ADDRESS_BITS, MSG_BITS) 
             unified (
				     clock, reset,
				       
				     read, write, address, in_data, 
				     out_address, out_data, valid, ready,
				     
				     mem2cache_msg, 
				     mem2cache_address, mem2cache_data, 
				     
				     cache2mem_msg, 
				     cache2mem_address, cache2mem_data, 
					 report
); 

main_memory #(CORE, DATA_WIDTH, ADDRESS_BITS, REAL_ADDR_BITS, NUM_CACHES, MSG_BITS, OFFSET_BITS, INIT_FILE) 
              m_memory (
				     clock, reset,  
				     				     
				     cache2mem_msg, 
				     cache2mem_address, cache2mem_data,
				     
				     mem2cache_msg, 
				     mem2cache_address, mem2cache_data
);


endmodule