data/full_repos/permissive/458737381/src/verilog-parser/tests/nand_switch.v
data/verilator_xmls/dcaad6c0-7ff3-4f49-84aa-1216d5da817c.xml
module nand_switch(a,b,out);
input a,b;
output out;

supply0 vss;
supply1 vdd;
wire net1;

pmos p1 (vdd,out,a);
pmos p2 (vdd,out,b);
nmos n1 (vss,net1,a);
nmos n2 (net1,out,b);

endmodule
module nand_switch(a,b,out);

input a,b;
output out;

supply0 vss;
supply1 vdd;
wire net1;

pmos p1 (vdd,out,a);
pmos p2 (vdd,out,b);
nmos n1 (vss,net1,a);
nmos n2 (net1,out,b);

endmodule