data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco/tcdm_xbar_wrap.sv
1: b"%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco/tcdm_xbar_wrap.sv:56: Cannot find file containing module: 'XBAR_TCDM'\n  XBAR_TCDM #(\n  ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco,data/full_repos/permissive/489147019/XBAR_TCDM\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco,data/full_repos/permissive/489147019/XBAR_TCDM.v\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco,data/full_repos/permissive/489147019/XBAR_TCDM.sv\n             XBAR_TCDM\n             XBAR_TCDM.v\n             XBAR_TCDM.sv\n             obj_dir/XBAR_TCDM\n             obj_dir/XBAR_TCDM.v\n             obj_dir/XBAR_TCDM.sv\n%Error: Exiting due to 1 error(s)\n"
module tcdm_xbar_wrap #(
    parameter NumMaster      = 8,
    parameter NumSlave       = 16,
    parameter AddrWidth      = 32,
    parameter DataWidth      = 32,
    parameter BeWidth        = DataWidth/8,
    parameter AddrMemWidth   = 12
) (
    input  logic                                   clk_i,
    input  logic                                   rst_ni,

    input  logic [NumMaster-1:0]                   req_i,
    input  logic [NumMaster-1:0][AddrWidth-1:0]    add_i,
    input  logic [NumMaster-1:0]                   wen_i,
    input  logic [NumMaster-1:0][DataWidth-1:0]    wdata_i,
    input  logic [NumMaster-1:0][BeWidth-1:0]      be_i,
    output logic [NumMaster-1:0]                   gnt_o,
    output logic [NumMaster-1:0]                   vld_o,
    output logic [NumMaster-1:0][DataWidth-1:0]    rdata_o,

    output logic [NumSlave-1:0]                    req_o,
    input  logic [NumSlave-1:0]                    gnt_i,
    output logic [NumSlave-1:0][AddrMemWidth-1:0]  add_o,
    output logic [NumSlave-1:0]                    wen_o,
    output logic [NumSlave-1:0][DataWidth-1:0]     wdata_o,
    output logic [NumSlave-1:0][BeWidth-1:0]       be_o,
    input  logic [NumSlave-1:0][DataWidth-1:0]     rdata_i
);

  logic [NumSlave-1:0][NumMaster-1:0] id_d, id_q;
  logic [NumSlave-1:0] vld_d, vld_q;
  logic [NumMaster-1:0][AddrWidth:0] add;


  assign vld_d = req_o & gnt_i;


  for (genvar k = 0; k < NumMaster; k++) begin : gen_ts
    assign add[k] = {1'b0, add_i[k]};
  end

  XBAR_TCDM #(
    .N_CH0          ( NumMaster    ),
    .N_CH1          ( 0            ),
    .N_SLAVE        ( NumSlave     ),
    .ADDR_WIDTH     ( AddrWidth+1  ),
    .DATA_WIDTH     ( DataWidth    ),
    .BE_WIDTH       ( BeWidth      ),
    .ADDR_MEM_WIDTH ( AddrMemWidth ),
    .TEST_SET_BIT   ( 32           )
  ) i_XBAR_TCDM (
    .data_req_i        ( req_i         ),
    .data_add_i        ( add           ),
    .data_wen_i        ( wen_i         ),
    .data_wdata_i      ( wdata_i       ),
    .data_be_i         ( be_i          ),
    .data_gnt_o        ( gnt_o         ),
    .data_r_valid_o    ( vld_o         ),
    .data_r_rdata_o    ( rdata_o       ),
    .data_req_o        ( req_o         ),
    .data_ts_set_o     (               ),
    .data_add_o        ( add_o         ),
    .data_wen_o        ( wen_o         ),
    .data_wdata_o      ( wdata_o       ),
    .data_be_o         ( be_o          ),
    .data_ID_o         ( id_d          ),
    .data_gnt_i        ( gnt_i         ),
    .data_r_rdata_i    ( rdata_i       ),
    .data_r_valid_i    ( vld_q         ),
    .data_r_ID_i       ( id_q          ),
    .TCDM_arb_policy_i ( '0            ),
    .clk               ( clk_i         ),
    .rst_n             ( rst_ni        )
  );

  always_ff @(posedge clk_i) begin : p_regs
    if (!rst_ni) begin
      id_q  <= '0;
      vld_q <= '0;
    end else begin
      id_q  <= id_d;
      vld_q <= vld_d;
    end
  end

endmodule
module tcdm_xbar_wrap #(
    parameter NumMaster      = 8,
    parameter NumSlave       = 16,
    parameter AddrWidth      = 32,
    parameter DataWidth      = 32,
    parameter BeWidth        = DataWidth/8,
    parameter AddrMemWidth   = 12
) (
    input  logic                                   clk_i,
    input  logic                                   rst_ni,

    input  logic [NumMaster-1:0]                   req_i,
    input  logic [NumMaster-1:0][AddrWidth-1:0]    add_i,
    input  logic [NumMaster-1:0]                   wen_i,
    input  logic [NumMaster-1:0][DataWidth-1:0]    wdata_i,
    input  logic [NumMaster-1:0][BeWidth-1:0]      be_i,
    output logic [NumMaster-1:0]                   gnt_o,
    output logic [NumMaster-1:0]                   vld_o,
    output logic [NumMaster-1:0][DataWidth-1:0]    rdata_o,

    output logic [NumSlave-1:0]                    req_o,
    input  logic [NumSlave-1:0]                    gnt_i,
    output logic [NumSlave-1:0][AddrMemWidth-1:0]  add_o,
    output logic [NumSlave-1:0]                    wen_o,
    output logic [NumSlave-1:0][DataWidth-1:0]     wdata_o,
    output logic [NumSlave-1:0][BeWidth-1:0]       be_o,
    input  logic [NumSlave-1:0][DataWidth-1:0]     rdata_i
);


  logic [NumSlave-1:0][NumMaster-1:0] id_d, id_q;
  logic [NumSlave-1:0] vld_d, vld_q;
  logic [NumMaster-1:0][AddrWidth:0] add;


  assign vld_d = req_o & gnt_i;


  for (genvar k = 0; k < NumMaster; k++) begin : gen_ts
    assign add[k] = {1'b0, add_i[k]};
  end

  XBAR_TCDM #(
    .N_CH0          ( NumMaster    ),
    .N_CH1          ( 0            ),
    .N_SLAVE        ( NumSlave     ),
    .ADDR_WIDTH     ( AddrWidth+1  ),
    .DATA_WIDTH     ( DataWidth    ),
    .BE_WIDTH       ( BeWidth      ),
    .ADDR_MEM_WIDTH ( AddrMemWidth ),
    .TEST_SET_BIT   ( 32           )
  ) i_XBAR_TCDM (
    .data_req_i        ( req_i         ),
    .data_add_i        ( add           ),
    .data_wen_i        ( wen_i         ),
    .data_wdata_i      ( wdata_i       ),
    .data_be_i         ( be_i          ),
    .data_gnt_o        ( gnt_o         ),
    .data_r_valid_o    ( vld_o         ),
    .data_r_rdata_o    ( rdata_o       ),
    .data_req_o        ( req_o         ),
    .data_ts_set_o     (               ),
    .data_add_o        ( add_o         ),
    .data_wen_o        ( wen_o         ),
    .data_wdata_o      ( wdata_o       ),
    .data_be_o         ( be_o          ),
    .data_ID_o         ( id_d          ),
    .data_gnt_i        ( gnt_i         ),
    .data_r_rdata_i    ( rdata_i       ),
    .data_r_valid_i    ( vld_q         ),
    .data_r_ID_i       ( id_q          ),
    .TCDM_arb_policy_i ( '0            ),
    .clk               ( clk_i         ),
    .rst_n             ( rst_ni        )
  );

  always_ff @(posedge clk_i) begin : p_regs
    if (!rst_ni) begin
      id_q  <= '0;
      vld_q <= '0;
    end else begin
      id_q  <= id_d;
      vld_q <= vld_d;
    end
  end

endmodule