data/full_repos/permissive/455210247/TestBench/router_top_tb.v
1: b'%Error: data/full_repos/permissive/455210247/TestBench/router_top_tb.v:8: Unsupported: event data types\nevent a;\n^~~~~\n%Error: data/full_repos/permissive/455210247/TestBench/router_top_tb.v:9: Unsupported: event data types\nevent b;\n^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/455210247/TestBench/router_top_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n#5 clk= ~clk;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/455210247/TestBench/router_top_tb.v:28: syntax error, unexpected \'@\'\n@(negedge clk);\n^\n%Error: data/full_repos/permissive/455210247/TestBench/router_top_tb.v:30: syntax error, unexpected \'@\'\n@(negedge clk);\n^\n%Error: data/full_repos/permissive/455210247/TestBench/router_top_tb.v:40: syntax error, unexpected \'@\'\n           @(negedge clk);\n           ^\n%Error: data/full_repos/permissive/455210247/TestBench/router_top_tb.v:43: syntax error, unexpected \'@\'\n           @(negedge clk);\n           ^\n%Error: data/full_repos/permissive/455210247/TestBench/router_top_tb.v:41: Unsupported: wait statements\n           wait(!busy)\n           ^~~~\n%Error: data/full_repos/permissive/455210247/TestBench/router_top_tb.v:51: syntax error, unexpected \'@\'\n          @(negedge clk);\n          ^\n%Error: data/full_repos/permissive/455210247/TestBench/router_top_tb.v:57: syntax error, unexpected \'@\'\n          @(negedge clk);\n          ^\n%Error: data/full_repos/permissive/455210247/TestBench/router_top_tb.v:58: Unsupported: wait statements\n            wait(!busy)\n            ^~~~\n%Error: data/full_repos/permissive/455210247/TestBench/router_top_tb.v:52: Unsupported: wait statements\n            wait(!busy)\n            ^~~~\n%Error: data/full_repos/permissive/455210247/TestBench/router_top_tb.v:63: syntax error, unexpected \'@\'\n          @(negedge clk);\n          ^\n%Error: data/full_repos/permissive/455210247/TestBench/router_top_tb.v:64: Unsupported: wait statements\n            wait(!busy)\n            ^~~~\n%Error: data/full_repos/permissive/455210247/TestBench/router_top_tb.v:67: syntax error, unexpected ->\n     ->b;\n     ^~\n%Error: data/full_repos/permissive/455210247/TestBench/router_top_tb.v:76: syntax error, unexpected \'@\'\n          @(negedge clk);\n          ^\n%Error: data/full_repos/permissive/455210247/TestBench/router_top_tb.v:79: syntax error, unexpected \'@\'\n           @(negedge clk);\n           ^\n%Error: data/full_repos/permissive/455210247/TestBench/router_top_tb.v:77: Unsupported: wait statements\n           wait(!busy)\n           ^~~~\n%Error: data/full_repos/permissive/455210247/TestBench/router_top_tb.v:87: syntax error, unexpected \'@\'\n          @(negedge clk);\n          ^\n%Error: data/full_repos/permissive/455210247/TestBench/router_top_tb.v:93: syntax error, unexpected \'@\'\n           @(negedge clk);\n           ^\n%Error: data/full_repos/permissive/455210247/TestBench/router_top_tb.v:94: Unsupported: wait statements\n             wait(!busy)\n             ^~~~\n%Error: data/full_repos/permissive/455210247/TestBench/router_top_tb.v:97: syntax error, unexpected ->\n     -> a;\n     ^~\n%Error: data/full_repos/permissive/455210247/TestBench/router_top_tb.v:88: Unsupported: wait statements\n              wait(!busy)\n              ^~~~\n%Error: data/full_repos/permissive/455210247/TestBench/router_top_tb.v:100: syntax error, unexpected \'@\'\n      @(negedge clk);\n      ^\n%Error: data/full_repos/permissive/455210247/TestBench/router_top_tb.v:101: Unsupported: wait statements\n            wait(!busy)\n            ^~~~\n%Error: data/full_repos/permissive/455210247/TestBench/router_top_tb.v:109: syntax error, unexpected \'@\'\n@(a);\n^\n%Error: data/full_repos/permissive/455210247/TestBench/router_top_tb.v:110: Unsupported: wait statements\nwait(vld_out_2)\n^~~~\n%Error: data/full_repos/permissive/455210247/TestBench/router_top_tb.v:117: syntax error, unexpected \'@\'\n@(b);\n^\n%Error: data/full_repos/permissive/455210247/TestBench/router_top_tb.v:118: Unsupported: wait statements\nwait(vld_out_1)\n^~~~\n%Warning-STMTDLY: data/full_repos/permissive/455210247/TestBench/router_top_tb.v:130: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Error: Exiting due to 28 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module router_top_tb();

reg [7:0]data_in;
reg pkt_valid,clk,resetn,read_enb_0,read_enb_1,read_enb_2;
wire [7:0]data_out_0,data_out_1,data_out_2;
wire vld_out_0,vld_out_1,vld_out_2,err,busy;
integer i;
event a;
event b;
router_top dut(clk,resetn,data_in,pkt_valid,read_enb_0,read_enb_1,read_enb_2,
                    data_out_0,data_out_1,data_out_2,vld_out_0,vld_out_1,vld_out_2,err,busy);

always
begin
forever
#5 clk= ~clk;
end

task initialize;
begin
resetn=1'b1;
{clk,pkt_valid,read_enb_0,read_enb_1,read_enb_2}=0;
end
endtask

task reset;
begin
@(negedge clk);
resetn=1'b0;
@(negedge clk);
resetn=1'b1;
end
endtask

task pkt_gen1;
reg [7:0] header,payload_data,parity;
reg [5:0] payload_l;
reg [1:0] des_addf;
          begin
           @(negedge clk);
           wait(!busy)
           begin
           @(negedge clk);
           pkt_valid=1'b1;
          payload_l=6'd14;
           des_addf=2'b01;
           header={payload_l,des_addf};
           data_in=header;
           parity=0^header;
           end
          @(negedge clk);
            wait(!busy)
      
    for(i=0;i<payload_l;i=i+1)

           begin
          @(negedge clk);
            wait(!busy)
           payload_data={$random}%256;
           data_in=payload_data;
           parity=parity^data_in;
           end
          @(negedge clk);
            wait(!busy)
           pkt_valid=0;
           data_in=parity;
		   ->b;
          end
endtask

task pkt_gen2;
reg [7:0] header,payload_data,parity;
reg [5:0] payload_l;
reg [1:0] des_addf;
          begin
          @(negedge clk);
           wait(!busy)
           begin
           @(negedge clk);
           pkt_valid=1'b1;
          payload_l=6'd17;
           des_addf=2'b10;
           header={payload_l,des_addf};
           data_in=header;
           parity=0^header;
           end
          @(negedge clk);
              wait(!busy)
      for(i=0;i<payload_l;i=i+1)

           begin
           
           @(negedge clk);
             wait(!busy)
           payload_data={$random}%256;
           data_in=payload_data;
		   -> a;
           parity=parity^data_in;
           end
      @(negedge clk);
            wait(!busy)
           pkt_valid=0;
           data_in=parity;
   end
endtask

initial
begin
@(a);
wait(vld_out_2)
	begin
	read_enb_2=1;
	end
end
initial
begin
@(b);
wait(vld_out_1)
begin
read_enb_1=1;
end
end

initial
begin
initialize;
reset;
pkt_gen1;
pkt_gen2;
#1000;
$finish;
end
endmodule
module router_top_tb();


reg [7:0]data_in;
reg pkt_valid,clk,resetn,read_enb_0,read_enb_1,read_enb_2;
wire [7:0]data_out_0,data_out_1,data_out_2;
wire vld_out_0,vld_out_1,vld_out_2,err,busy;
integer i;
event a;
event b;
router_top dut(clk,resetn,data_in,pkt_valid,read_enb_0,read_enb_1,read_enb_2,
                    data_out_0,data_out_1,data_out_2,vld_out_0,vld_out_1,vld_out_2,err,busy);

always
begin
forever
#5 clk= ~clk;
end

task initialize;
begin
resetn=1'b1;
{clk,pkt_valid,read_enb_0,read_enb_1,read_enb_2}=0;
end
endtask

task reset;
begin
@(negedge clk);
resetn=1'b0;
@(negedge clk);
resetn=1'b1;
end
endtask

task pkt_gen1;
reg [7:0] header,payload_data,parity;
reg [5:0] payload_l;
reg [1:0] des_addf;
          begin
           @(negedge clk);
           wait(!busy)
           begin
           @(negedge clk);
           pkt_valid=1'b1;
          payload_l=6'd14;
           des_addf=2'b01;
           header={payload_l,des_addf};
           data_in=header;
           parity=0^header;
           end
          @(negedge clk);
            wait(!busy)
      
    for(i=0;i<payload_l;i=i+1)

           begin
          @(negedge clk);
            wait(!busy)
           payload_data={$random}%256;
           data_in=payload_data;
           parity=parity^data_in;
           end
          @(negedge clk);
            wait(!busy)
           pkt_valid=0;
           data_in=parity;
		   ->b;
          end
endtask

task pkt_gen2;
reg [7:0] header,payload_data,parity;
reg [5:0] payload_l;
reg [1:0] des_addf;
          begin
          @(negedge clk);
           wait(!busy)
           begin
           @(negedge clk);
           pkt_valid=1'b1;
          payload_l=6'd17;
           des_addf=2'b10;
           header={payload_l,des_addf};
           data_in=header;
           parity=0^header;
           end
          @(negedge clk);
              wait(!busy)
      for(i=0;i<payload_l;i=i+1)

           begin
           
           @(negedge clk);
             wait(!busy)
           payload_data={$random}%256;
           data_in=payload_data;
		   -> a;
           parity=parity^data_in;
           end
      @(negedge clk);
            wait(!busy)
           pkt_valid=0;
           data_in=parity;
   end
endtask

initial
begin
@(a);
wait(vld_out_2)
	begin
	read_enb_2=1;
	end
end
initial
begin
@(b);
wait(vld_out_1)
begin
read_enb_1=1;
end
end

initial
begin
initialize;
reset;
pkt_gen1;
pkt_gen2;
#1000;
$finish;
end
endmodule