data/full_repos/permissive/486954482/netlists/masked_sign64.v
data/verilator_xmls/d66a2e57-1213-45a1-a09a-ccbb0b816b1c.xml
module relu(
    input [63:0] g_input,
    input [63:0] e_input,
    output [63:0] o
    );
    wire [63:0] unmasked;
    assign unmasked = g_input + e_input;
    assign o = (unmasked[63] == 0)? g_input + 1 : g_input;
endmodule
module relu(
    input [63:0] g_input,
    input [63:0] e_input,
    output [63:0] o
    );

    wire [63:0] unmasked;
    assign unmasked = g_input + e_input;
    assign o = (unmasked[63] == 0)? g_input + 1 : g_input;
endmodule