data/full_repos/permissive/446997925/hw3/and.v
data/verilator_xmls/e2b82ace-9d56-43df-a68f-94f4fe8a4f8c.xml
module and_64(out, a, b);
input [63:0] a, b;
output [63:0] out;

and_32 f(out[31:0], a[31:0], b[31:0]),
          s(out[63:32], a[63:32], b[63:32]);
endmodule
module and_64(out, a, b);

input [63:0] a, b;
output [63:0] out;

and_32 f(out[31:0], a[31:0], b[31:0]),
          s(out[63:32], a[63:32], b[63:32]);
endmodule