data/full_repos/permissive/437204475/pipeline/if.v
1: b'%Error: data/full_repos/permissive/437204475/pipeline/if.v:3: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/437204475/pipeline,data/full_repos/permissive/437204475/defines.v\n             data/full_repos/permissive/437204475/pipeline,data/full_repos/permissive/437204475/defines.v.v\n             data/full_repos/permissive/437204475/pipeline,data/full_repos/permissive/437204475/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/437204475/pipeline/if.v:6: Define or directive not defined: \'`WORD_WIDTH\'\n    parameter W = `WORD_WIDTH\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/if.v:7: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n) (\n^\n%Error: data/full_repos/permissive/437204475/pipeline/if.v:9: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire stall,            \n    ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/if.v:10: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire flush,            \n    ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/if.v:11: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[W-1:0] flush_addr,\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/if.v:13: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg[W-1:0] pc,\n    ^~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/if.v:14: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input wire[W-1:0] read_inst,\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/if.v:15: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg[W-1:0] inst\n    ^~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/if.v:16: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/437204475/pipeline/if.v:19: Define or directive not defined: \'`ZERO_WORD\'\n            inst <= `ZERO_WORD;\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/if.v:20: Define or directive not defined: \'`ZERO_WORD\'\n            pc <= `ZERO_WORD;\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/if.v:26: Define or directive not defined: \'`ZERO_WORD\'\n            pc <= `ZERO_WORD;\n                  ^~~~~~~~~~\n%Error: Exiting due to 13 error(s)\n'
module pc_assume_not_take #(
    parameter W = `WORD_WIDTH
) (
    input wire clk, rst,
    input wire stall,
    input wire flush,
    input wire[W-1:0] flush_addr,

    output reg[W-1:0] pc,
    input wire[W-1:0] read_inst,
    output reg[W-1:0] inst
);
    always @(*) begin
        if (rst) begin
            inst <= `ZERO_WORD;
            pc <= `ZERO_WORD;
        end
    end

    always @(posedge clk) begin
        if (rst) begin
            pc <= `ZERO_WORD;
        end
        else if (stall) begin
            pc <= pc;
        end
        else if (flush) begin
            pc <= flush_addr;
        end
        else begin
            pc <= pc + 4;
        end
    end

    always @(negedge clk) begin
        inst <= read_inst;
    end
endmodule
module pc_assume_not_take #(
    parameter W = `WORD_WIDTH
) (
    input wire clk, rst,
    input wire stall,
    input wire flush,
    input wire[W-1:0] flush_addr,

    output reg[W-1:0] pc,
    input wire[W-1:0] read_inst,
    output reg[W-1:0] inst
);

    always @(*) begin
        if (rst) begin
            inst <= `ZERO_WORD;
            pc <= `ZERO_WORD;
        end
    end

    always @(posedge clk) begin
        if (rst) begin
            pc <= `ZERO_WORD;
        end
        else if (stall) begin
            pc <= pc;
        end
        else if (flush) begin
            pc <= flush_addr;
        end
        else begin
            pc <= pc + 4;
        end
    end

    always @(negedge clk) begin
        inst <= read_inst;
    end
endmodule