data/full_repos/permissive/458737381/src/verilog-parser/tests/dffsle_ns.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dffsle_ns.v:73: Cannot find file containing module: 'dffe_ns'\n  dffe_ns #(SIZE) dff_reg (.din(din_wire[SIZE-1:0]), .en(en_wire), .q(q_wire[SIZE-1:0]), .clk(clk));\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/dffe_ns\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/dffe_ns.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/dffe_ns.sv\n             dffe_ns\n             dffe_ns.v\n             dffe_ns.sv\n             obj_dir/dffe_ns\n             obj_dir/dffe_ns.v\n             obj_dir/dffe_ns.sv\n%Error: Exiting due to 1 error(s)\n"
module dffsle_ns (

  q, 

  din, en, set_l, clk
  );


  parameter SIZE = 1;

  input  [SIZE-1:0] din;
  input 	    en;
  input 	    set_l;
  input 	    clk;

  output [SIZE-1:0] q;

  wire              en_wire;
  wire 	 [SIZE-1:0] din_wire, q_wire;



















  assign din_wire[SIZE-1:0] =  ((en)? din[SIZE-1:0]: q_wire[SIZE-1:0]) | {SIZE{(~set_l)}};
  assign en_wire = en || (~set_l);

  dffe_ns #(SIZE) dff_reg (.din(din_wire[SIZE-1:0]), .en(en_wire), .q(q_wire[SIZE-1:0]), .clk(clk));

  assign q = q_wire;

  endmodule
module dffsle_ns (

  q, 

  din, en, set_l, clk
  );



  parameter SIZE = 1;

  input  [SIZE-1:0] din;
  input 	    en;
  input 	    set_l;
  input 	    clk;

  output [SIZE-1:0] q;

  wire              en_wire;
  wire 	 [SIZE-1:0] din_wire, q_wire;



















  assign din_wire[SIZE-1:0] =  ((en)? din[SIZE-1:0]: q_wire[SIZE-1:0]) | {SIZE{(~set_l)}};
  assign en_wire = en || (~set_l);

  dffe_ns #(SIZE) dff_reg (.din(din_wire[SIZE-1:0]), .en(en_wire), .q(q_wire[SIZE-1:0]), .clk(clk));

  assign q = q_wire;

  endmodule