data/full_repos/permissive/496096937/verilog/rtl/quad_mux.v
data/verilator_xmls/f3b9d171-57d3-4b51-9632-8daf81dccff1.xml
module quad_mux(
`ifdef USE_POWER_PINS
	inout vccd1,
	inout vssd1,
`endif
    input [1:0]       S,
    input [63:0]      A0,
    input [63:0]      A1,
    input [63:0]      A2,
    input [63:0]      A3,
    output reg [63:0] Y
);

always @* begin
    case (S)
        2'b00:   Y = A0;
        2'b01:   Y = A1;
        2'b10:   Y = A2;
        2'b11:   Y = A3;
    endcase
end

endmodule
module quad_mux(
`ifdef USE_POWER_PINS
	inout vccd1,
	inout vssd1,
`endif
    input [1:0]       S,
    input [63:0]      A0,
    input [63:0]      A1,
    input [63:0]      A2,
    input [63:0]      A3,
    output reg [63:0] Y
);


always @* begin
    case (S)
        2'b00:   Y = A0;
        2'b01:   Y = A1;
        2'b10:   Y = A2;
        2'b11:   Y = A3;
    endcase
end

endmodule