data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_loop_unrolling/cachelib/v_rtl/dut_Add_4Sx2S_4S_4.v
data/verilator_xmls/cd3ab80b-f800-4b92-8fcb-c3d93c71e256.xml
module dut_Add_4Sx2S_4S_4 (
	in2,
	in1,
	out1
	);
input [3:0] in2;
input [1:0] in1;
output [3:0] out1;
wire [3:0] asc001;

assign asc001 = 
	+(in2)
	+({{2{in1[1]}}, in1});

assign out1 = asc001;
endmodule
module dut_Add_4Sx2S_4S_4 (
	in2,
	in1,
	out1
	);

input [3:0] in2;
input [1:0] in1;
output [3:0] out1;
wire [3:0] asc001;

assign asc001 = 
	+(in2)
	+({{2{in1[1]}}, in1});

assign out1 = asc001;
endmodule