data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_temp_diode.v
data/verilator_xmls/c17140cf-4e71-469b-ae28-f7c636cf0270.xml
module bw_temp_diode (b, c, e);
    inout b;
    inout c;
    inout e;

endmodule
module bw_temp_diode (b, c, e);

    inout b;
    inout c;
    inout e;

endmodule