data/full_repos/permissive/487368624/Lab M/hrLib/rf.v
1: b'%Error: Cannot find file containing module: M/hrLib,data/full_repos/permissive/487368624\n        ... Looked in:\n             data/full_repos/permissive/487368624/Lab/M/hrLib,data/full_repos/permissive/487368624\n             data/full_repos/permissive/487368624/Lab/M/hrLib,data/full_repos/permissive/487368624.v\n             data/full_repos/permissive/487368624/Lab/M/hrLib,data/full_repos/permissive/487368624.sv\n             M/hrLib,data/full_repos/permissive/487368624\n             M/hrLib,data/full_repos/permissive/487368624.v\n             M/hrLib,data/full_repos/permissive/487368624.sv\n             obj_dir/M/hrLib,data/full_repos/permissive/487368624\n             obj_dir/M/hrLib,data/full_repos/permissive/487368624.v\n             obj_dir/M/hrLib,data/full_repos/permissive/487368624.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/487368624/Lab\n%Error: Cannot find file containing module: M/hrLib/rf.v\n%Error: Exiting due to 3 error(s)\n'
module rf(RD1,RD2, RN1,RN2, WN,WD, clk, W);

parameter DEBUG = 0;

input clk, W;
input [4:0] RN1, RN2, WN;
input [31:0] WD;
output [31:0] RD1, RD2;

reg [31:0] RD1, RD2;
reg [31:0] arr [1:31];

always @(RN1 or arr[RN1])
	if (RN1 == 0)
		RD1 = 0;
	else
	begin
		RD1 = arr[RN1];
		if (DEBUG != 0) $display("RF: read %0dd from reg#%0d", RD1, RN1);
	end

always @(RN2 or arr[RN2])
	if (RN2 == 0)
		RD2 = 0;
	else
	begin
		RD2 = arr[RN2];
		if (DEBUG != 0) $display("RF: read %0dd from reg#%0d", RD2, RN2);
	end
		

always @(posedge clk) 
	if (W == 1 && WN != 0)
	begin
		arr[WN] = WD;
		if (DEBUG != 0) $display("RF: wrote %0dd to reg#%0d", WD, WN);
	end

endmodule
module rf(RD1,RD2, RN1,RN2, WN,WD, clk, W);


parameter DEBUG = 0;

input clk, W;
input [4:0] RN1, RN2, WN;
input [31:0] WD;
output [31:0] RD1, RD2;

reg [31:0] RD1, RD2;
reg [31:0] arr [1:31];

always @(RN1 or arr[RN1])
	if (RN1 == 0)
		RD1 = 0;
	else
	begin
		RD1 = arr[RN1];
		if (DEBUG != 0) $display("RF: read %0dd from reg#%0d", RD1, RN1);
	end

always @(RN2 or arr[RN2])
	if (RN2 == 0)
		RD2 = 0;
	else
	begin
		RD2 = arr[RN2];
		if (DEBUG != 0) $display("RF: read %0dd from reg#%0d", RD2, RN2);
	end
		

always @(posedge clk) 
	if (W == 1 && WN != 0)
	begin
		arr[WN] = WD;
		if (DEBUG != 0) $display("RF: wrote %0dd to reg#%0d", WD, WN);
	end

endmodule