data/full_repos/permissive/507506290/RTL_Files/MUX_REG.v
data/verilator_xmls/8641f0fe-ff93-43a7-b8b9-61e800933f5f.xml
module MUX_REG(i_1, i_2, sel_1  , mux_o1 );
input [`WIDTH_MUX-1:0] i_1 ,i_2 ;
input sel_1 ;
output [`WIDTH_MUX-1:0] mux_o1 ;

assign mux_o1 = sel_1?i_2 :i_1 ; 
endmodule
module MUX_REG(i_1, i_2, sel_1  , mux_o1 );

input [`WIDTH_MUX-1:0] i_1 ,i_2 ;
input sel_1 ;
output [`WIDTH_MUX-1:0] mux_o1 ;

assign mux_o1 = sel_1?i_2 :i_1 ; 
endmodule