data/full_repos/permissive/495276914/ALU.v
1: b'%Warning-WIDTH: data/full_repos/permissive/495276914/ALU.v:122: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 63 bits.\n                                                              : ... In instance ALU\n                    3\'b010:begin alu_out={31\'b0,s_comp};end    \n                                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/495276914/ALU.v:123: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 63 bits.\n                                                              : ... In instance ALU\n                    3\'b011:begin alu_out={31\'b0,us_comp}; end  \n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/495276914/ALU.v:157: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                              : ... In instance ALU\n                        alu_out = in2[7:0];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/495276914/ALU.v:160: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 16 bits.\n                                                              : ... In instance ALU\n                        alu_out = in2[15:0];\n                                ^\n%Error: Exiting due to 4 warning(s)\n'
module compare(arg1,arg2,s_comp,us_comp);
    input[31:0] arg1,arg2;
    output[31:0] s_comp, us_comp;    
    assign s_comp = ($signed(arg1) < $signed(arg2)) ? 1 : 0;
    wire[31:0] a1,a2;
    assign a1=($signed(arg1) < 0) ? -$signed(arg1) : arg1;
    assign a2=($signed(arg2) < 0) ? -$signed(arg2) : arg2;
    assign us_comp = a1 < a2 ? 1 : 0;
endmodule
module compare(arg1,arg2,s_comp,us_comp);

    input[31:0] arg1,arg2;
    output[31:0] s_comp, us_comp;    
    assign s_comp = ($signed(arg1) < $signed(arg2)) ? 1 : 0;
    wire[31:0] a1,a2;
    assign a1=($signed(arg1) < 0) ? -$signed(arg1) : arg1;
    assign a2=($signed(arg2) < 0) ? -$signed(arg2) : arg2;
    assign us_comp = a1 < a2 ? 1 : 0;
endmodule