data/full_repos/permissive/471242277/VerilogCode/registerFile.v
data/verilator_xmls/ea43379c-756f-4fcb-80eb-20f8d34fca7e.xml
module RegFile (
   input [3:0] addrA, addrB, addrW,
   input [31:0] dataIn,
   input WE,
   input clk,
   output [31:0] A,B
);
   

   reg [31:0] regfile [15:0];

   assign A = regfile[addrA];
   assign B = regfile[addrB];

   always @(posedge clk) begin
      if(WE) begin
         regfile[addrW] <= dataIn;
      end
   end

endmodule
module RegFile (
   input [3:0] addrA, addrB, addrW,
   input [31:0] dataIn,
   input WE,
   input clk,
   output [31:0] A,B
);

   

   reg [31:0] regfile [15:0];

   assign A = regfile[addrA];
   assign B = regfile[addrB];

   always @(posedge clk) begin
      if(WE) begin
         regfile[addrW] <= dataIn;
      end
   end

endmodule