data/full_repos/permissive/500128826/HDLBits/More Verilog Features/Bcdadd100/top_module.v
1: b'%Error: Cannot find file containing module: Verilog\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/More/Verilog\n             data/full_repos/permissive/500128826/HDLBits/More/Verilog.v\n             data/full_repos/permissive/500128826/HDLBits/More/Verilog.sv\n             Verilog\n             Verilog.v\n             Verilog.sv\n             obj_dir/Verilog\n             obj_dir/Verilog.v\n             obj_dir/Verilog.sv\n%Error: Cannot find file containing module: Features/Bcdadd100,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/More\n%Error: Cannot find file containing module: Features/Bcdadd100/top_module.v\n%Error: Exiting due to 4 error(s)\n'
module top_module (
    input wire [399:0] a,
    input wire [399:0] b,
    input wire cin,
    output wire cout,
    output wire [399:0] sum
);

  wire [99:0] carry;

  generate
    genvar i;
    for (i = 0; i < 100; i = i + 1) begin : fooName
      bcd_fadd bcd_add_N (
          a[4*i+:4],
          b[4*i+:4],
          (i == 0) ? cin : carry[i-1],
          carry[i],
          sum[4*i+:4]
      );
    end
  endgenerate

  assign cout = carry[99];


endmodule
module top_module (
    input wire [399:0] a,
    input wire [399:0] b,
    input wire cin,
    output wire cout,
    output wire [399:0] sum
);


  wire [99:0] carry;

  generate
    genvar i;
    for (i = 0; i < 100; i = i + 1) begin : fooName
      bcd_fadd bcd_add_N (
          a[4*i+:4],
          b[4*i+:4],
          (i == 0) ? cin : carry[i-1],
          carry[i],
          sum[4*i+:4]
      );
    end
  endgenerate

  assign cout = carry[99];


endmodule