data/full_repos/permissive/491573622/register.v
data/verilator_xmls/908c07b5-c29c-498f-a9d8-f54304ea260a.xml
module register(
    input clk,
    input [31:0] din,
    output reg [31:0] dout
    );

    always@(posedge clk)
    begin
        dout <= din;
    end
endmodule
module register(
    input clk,
    input [31:0] din,
    output reg [31:0] dout
    );


    always@(posedge clk)
    begin
        dout <= din;
    end
endmodule