data/full_repos/permissive/501791642/ISE_devel/uart/uart_fsm.v
data/verilator_xmls/7643f1e1-176a-4cfe-9d1b-c9d810d55a7e.xml
module uart_fsm(
    input 			CLK,
	input 			CLR,
	input 			CE,
	input 			DI,
	input           HB,
	input           BD,
	input           LB,
	output  [2:0]  STATUS
    );
    

    parameter IDLE = 3'b000;
    parameter START = 3'b001;
    parameter START_CHECK = 3'b010;
    parameter READ = 3'b011;
    parameter STOP = 3'b100;
    
    reg [2:0] state = IDLE;
    assign STATUS = state;
    
    always@(posedge CLK)
    begin
        if(CLR)
            state <= IDLE;
        else begin
            if(CE)
            begin
                case(state)
                   IDLE:
                       if(!DI)
                            state <= START;
                       else
                            state <= IDLE;
                    
                    START:
                        if(HB)
                            state <= START_CHECK;
                        else
                            state <= START;
                   
                   START_CHECK:
                        if(DI)
                            state <= IDLE;
                        else
                            state <= READ;
                            
                   READ:
                        if(LB)
                            state <= STOP;
                        else
                            state <= READ;
                            
                   STOP:
                        if(BD)
                            state <= IDLE;
                        else
                            state <= STOP;   
                endcase
            end
        end
    end
    
endmodule
module uart_fsm(
    input 			CLK,
	input 			CLR,
	input 			CE,
	input 			DI,
	input           HB,
	input           BD,
	input           LB,
	output  [2:0]  STATUS
    );

    

    parameter IDLE = 3'b000;
    parameter START = 3'b001;
    parameter START_CHECK = 3'b010;
    parameter READ = 3'b011;
    parameter STOP = 3'b100;
    
    reg [2:0] state = IDLE;
    assign STATUS = state;
    
    always@(posedge CLK)
    begin
        if(CLR)
            state <= IDLE;
        else begin
            if(CE)
            begin
                case(state)
                   IDLE:
                       if(!DI)
                            state <= START;
                       else
                            state <= IDLE;
                    
                    START:
                        if(HB)
                            state <= START_CHECK;
                        else
                            state <= START;
                   
                   START_CHECK:
                        if(DI)
                            state <= IDLE;
                        else
                            state <= READ;
                            
                   READ:
                        if(LB)
                            state <= STOP;
                        else
                            state <= READ;
                            
                   STOP:
                        if(BD)
                            state <= IDLE;
                        else
                            state <= STOP;   
                endcase
            end
        end
    end
    
endmodule