data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Multiplexers/61_Mux2to1.v
data/verilator_xmls/3f702515-7fbb-4611-beb1-353f5781ef12.xml
module top_module( 
    input a, b, sel,
    output out ); 

    assign out = sel ? b : a;



endmodule
module top_module( 
    input a, b, sel,
    output out );
 

    assign out = sel ? b : a;



endmodule