data/full_repos/permissive/490456910/rtl/cpuA_B/AlphaMissionCore_CPU_A_B_sync.sv
1: b"%Error: data/full_repos/permissive/490456910/rtl/cpuA_B/AlphaMissionCore_CPU_A_B_sync.sv:77: Cannot find file containing module: 'selector_cpuAB_rom'\n    selector_cpuAB_rom selector\n    ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/490456910/rtl/cpuA_B,data/full_repos/permissive/490456910/selector_cpuAB_rom\n             data/full_repos/permissive/490456910/rtl/cpuA_B,data/full_repos/permissive/490456910/selector_cpuAB_rom.v\n             data/full_repos/permissive/490456910/rtl/cpuA_B,data/full_repos/permissive/490456910/selector_cpuAB_rom.sv\n             selector_cpuAB_rom\n             selector_cpuAB_rom.v\n             selector_cpuAB_rom.sv\n             obj_dir/selector_cpuAB_rom\n             obj_dir/selector_cpuAB_rom.v\n             obj_dir/selector_cpuAB_rom.sv\n%Error: data/full_repos/permissive/490456910/rtl/cpuA_B/AlphaMissionCore_CPU_A_B_sync.sv:101: Cannot find file containing module: 'DFF_pseudoAsyncClrPre2'\n    DFF_pseudoAsyncClrPre2 #(.W(1)) e4_1 (\n    ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/490456910/rtl/cpuA_B/AlphaMissionCore_CPU_A_B_sync.sv:141: Cannot find file containing module: 'T80pa'\n        T80pa z80_E5 (\n        ^~~~~\n%Error: data/full_repos/permissive/490456910/rtl/cpuA_B/AlphaMissionCore_CPU_A_B_sync.sv:180: Cannot find file containing module: 'ttl_74139_nodly'\n    ttl_74139_nodly c5_1(.Enable_bar(1'b0), .A_2D(cpuA_A[15:14]), .Y_2D({C5_1_Y3n, CS_ROM_P3n, CS_ROM_P2n, CS_ROM_P1n}));\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/490456910/rtl/cpuA_B/AlphaMissionCore_CPU_A_B_sync.sv:220: Cannot find file containing module: 'ttl_74138_nodly'\n    ttl_74138_nodly c8 (.Enable1_bar(C7_4_OR), .Enable2_bar(C7_3_OR), .Enable3(C2_2_INV), .A(cpuA_A[10:8]), \n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/490456910/rtl/cpuA_B/AlphaMissionCore_CPU_A_B_sync.sv:235: Cannot find file containing module: 'eprom_16K'\n    eprom_16K P3_5D\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/490456910/rtl/cpuA_B/AlphaMissionCore_CPU_A_B_sync.sv:247: Cannot find file containing module: 'eprom_16K'\n    eprom_16K P2_7D\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/490456910/rtl/cpuA_B/AlphaMissionCore_CPU_A_B_sync.sv:259: Cannot find file containing module: 'eprom_16K'\n    eprom_16K P1_8D\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/490456910/rtl/cpuA_B/AlphaMissionCore_CPU_A_B_sync.sv:307: Cannot find file containing module: 'DFF_pseudoAsyncClrPre'\n    DFF_pseudoAsyncClrPre #(.W(1)) e4_2 (\n    ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/490456910/rtl/cpuA_B/AlphaMissionCore_CPU_A_B_sync.sv:322: Cannot find file containing module: 'T80pa'\n        T80pa z80_E1 (\n        ^~~~~\n%Error: data/full_repos/permissive/490456910/rtl/cpuA_B/AlphaMissionCore_CPU_A_B_sync.sv:357: Cannot find file containing module: 'ttl_74139_nodly'\n    ttl_74139_nodly c5_2(.Enable_bar(1'b0), .A_2D(cpuB_A[15:14]), .Y_2D({C5_2_Y3n, CS_ROM_P6n, CS_ROM_P5n, CS_ROM_P4n}));\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/490456910/rtl/cpuA_B/AlphaMissionCore_CPU_A_B_sync.sv:382: Cannot find file containing module: 'eprom_16K'\n    eprom_16K P6_1D\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/490456910/rtl/cpuA_B/AlphaMissionCore_CPU_A_B_sync.sv:394: Cannot find file containing module: 'eprom_16K'\n    eprom_16K P5_2D\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/490456910/rtl/cpuA_B/AlphaMissionCore_CPU_A_B_sync.sv:406: Cannot find file containing module: 'eprom_16K'\n    eprom_16K P4_3D\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/490456910/rtl/cpuA_B/AlphaMissionCore_CPU_A_B_sync.sv:459: Cannot find file containing module: 'DFF_pseudoAsyncClrPre'\n    DFF_pseudoAsyncClrPre #(.W(1)) c1_1 (\n    ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/490456910/rtl/cpuA_B/AlphaMissionCore_CPU_A_B_sync.sv:470: Cannot find file containing module: 'DFF_pseudoAsyncClrPre'\n    DFF_pseudoAsyncClrPre #(.W(1)) c1_2 (\n    ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/490456910/rtl/cpuA_B/AlphaMissionCore_CPU_A_B_sync.sv:497: Cannot find file containing module: 'pal16l6c_A1_nodly'\n    pal16l6c_A1_nodly pal16l6_a01_nodly(\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/490456910/rtl/cpuA_B/AlphaMissionCore_CPU_A_B_sync.sv:529: Cannot find file containing module: 'ttl_74157'\n    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) a2 (.Enable_bar(1'b0), .Select(A_B),\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/490456910/rtl/cpuA_B/AlphaMissionCore_CPU_A_B_sync.sv:532: Cannot find file containing module: 'ttl_74157'\n    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) a3 (.Enable_bar(1'b0), .Select(A_B),\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/490456910/rtl/cpuA_B/AlphaMissionCore_CPU_A_B_sync.sv:535: Cannot find file containing module: 'ttl_74157'\n    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) a4 (.Enable_bar(1'b0), .Select(A_B),\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/490456910/rtl/cpuA_B/AlphaMissionCore_CPU_A_B_sync.sv:549: Cannot find file containing module: 'ttl_74138_nodly'\n    ttl_74138_nodly a7(\n    ^~~~~~~~~~~~~~~\n%Error: Exiting due to 21 error(s)\n"
module AlphaMissionCore_CPU_A_B_sync
(
    input  wire VIDEO_RSTn,
    input  wire clk,
    input  wire pause_cpu,
    input  wire H0,
    input  wire Cen_p,
    input  wire Cen_n,
    input wire clk_13p4b_cen,
    input  wire RESETn,
    input wire [15:0] PLAYER1,
    input wire [15:0] PLAYER2,
	 input wire [15:0] DSW,
    input  wire VBL,
    input  wire BWA,
    input  wire A_B,
    input  wire RLA,
    input  wire RLB,
    input  wire WBA,
    input  wire WBB,
    input  wire VDG,
    output logic VRDn,
    output logic AE,
    output logic BE,

    output logic [7:0] CPUAD,
    output logic CPUA_RD,
    output logic CPUA_WR,


    output logic [11:0] VA,

    output logic [7:0] V_out,
    input  wire  [7:0] V_in,


	input wire         [24:0] ioctl_addr,
	input wire         [7:0] ioctl_data,
	input wire         ioctl_wr,
    

    input  wire  SND_BUSY,
    output logic COIN,
    output logic P1,
    output logic P2,
    output logic P1_P2,
    output logic MCODE,
    output logic DIP1,
    output logic DIP2,


    output logic FRONT_VIDEO_CSn,
    output logic SIDE_VRAM_CSn,
    output logic DISC,
    output logic MSB,
    output logic FSX,
    output logic FSY,
    output logic B1SX,
    output logic B1SY,
    output logic SIDE_COLOR_BANK,
    output logic BACK1_TILE_COLOR_BANK,
    output logic BACK1_VRAM_CSn
);
    logic VD_to_cpuAdbus;
    logic VD_to_cpuBdbus;



    logic P1_8D_cs, P2_7D_cs, P3_5D_cs;
    logic P4_3D_cs, P5_2D_cs, P6_1D_cs;
    selector_cpuAB_rom selector
    (
        .ioctl_addr(ioctl_addr),
        .P1_8D_cs(P1_8D_cs), .P2_7D_cs(P2_7D_cs), .P3_5D_cs(P3_5D_cs),
        .P4_3D_cs(P4_3D_cs), .P5_2D_cs(P5_2D_cs), .P6_1D_cs(P6_1D_cs)
    );



    logic cpuA_nM1;
    logic cpuA_nMR;
    logic cpuA_nIO;
    logic cpuA_nRD;
    logic cpuA_nWR;
    logic cpuA_nRFSH;
    logic cpuA_nHALT;
    logic cpuA_nBUSACK;

    logic cpuA_nINT;
    logic cpuA_nNMI;
    logic [15:0] cpuA_A;
    logic [7:0] cpuA_Vin, cpuB_Vin;

    logic E4_1_Qn;
    DFF_pseudoAsyncClrPre2 #(.W(1)) e4_1 (
        .clk(clk),
        .rst(~VIDEO_RSTn),
        .din(1'b1),
        .q(),
        .qn(cpuA_nINT),
        .set(1'b0),
        .clr(~cpuA_nIO),
        .cen(VBL)
    );

    reg [7:0] cpuA_Din;
    reg [7:0] cpuA_Dout;


    reg reset_n=1'b0;
    reg [5:0] rst_cnt;

    always @(posedge clk)
        if( ~RESETn ) begin
            rst_cnt <= 'd0;
            reset_n <= 1'b0;
        end else begin
            if( rst_cnt != ~6'b0 ) begin
                reset_n <= 1'b0;
                rst_cnt <= rst_cnt + 6'd1;
            end else reset_n <= 1'b1;
        end



    logic Cen_pr1;
    logic Cen_nr1;

    always @(posedge clk) begin
        Cen_pr1 <= Cen_p;
        Cen_nr1 <= Cen_n;
    end


        T80pa z80_E5 (
        .RESET_n(reset_n),
        .CLK    (clk),
        .CEN_p  (Cen_pr1 & ~pause_cpu),
        .CEN_n  (Cen_nr1 & ~pause_cpu),

        .WAIT_n (1'b1),
        .INT_n  (cpuA_nINT),
        .NMI_n  (cpuA_nNMI),
        .RD_n   (cpuA_nRD),
        .WR_n   (cpuA_nWR),
        .A      (cpuA_A),
        .DI     (cpuA_Din),
        .DO     (cpuA_Dout),
        .IORQ_n (cpuA_nIO),
        .M1_n   (cpuA_nM1),
        .MREQ_n (cpuA_nMR),
        .BUSRQ_n(1'b1),
        .BUSAK_n(cpuA_nBUSACK),
        .OUT0   (1'b0),
        .RFSH_n (cpuA_nRFSH),
        .HALT_n (cpuA_nHALT)
    );

    assign CPUA_WR = cpuA_nWR;
    assign CPUA_RD = cpuA_nRD;
    



     logic C5_1_Y3n;
     logic CS_ROM_P3n;
     logic CS_ROM_P2n;
     logic CS_ROM_P1n;





    ttl_74139_nodly c5_1(.Enable_bar(1'b0), .A_2D(cpuA_A[15:14]), .Y_2D({C5_1_Y3n, CS_ROM_P3n, CS_ROM_P2n, CS_ROM_P1n}));

    logic C7_3_OR;
    assign C7_3_OR = cpuA_nMR | C5_1_Y3n;  


    logic C7_1_OR;
    logic C6_1_NOR;
    logic AE_addr;

    assign C7_1_OR = |cpuA_A[13:12];
    assign C6_1_NOR = ~(C7_1_OR | cpuA_A[11]);

     logic c6nor1_r;
    always @(posedge clk) begin
        c6nor1_r <= C6_1_NOR;
    end
    assign AE_addr = c6nor1_r | C5_1_Y3n;
    
    assign AE = ~(AE_addr | cpuA_nMR);


    logic cpuB_NMI_TRIG_R_cpuA_NMI_ACK_W_CTRL;
    logic C2_2_INV;
    logic C7_4_OR;


    assign C2_2_INV = ~cpuA_A[11];
    assign C7_4_OR = |cpuA_A[13:12];











    ttl_74138_nodly c8 (.Enable1_bar(C7_4_OR), .Enable2_bar(C7_3_OR), .Enable3(C2_2_INV), .A(cpuA_A[10:8]), 
                  .Y({cpuB_NMI_TRIG_R_cpuA_NMI_ACK_W_CTRL, DIP2, DIP1, MCODE, P1_P2, P2, P1, COIN}));


    always @(posedge clk) begin


        if(!cpuA_nMR && !C5_1_Y3n) CPUAD <= cpuA_Dout;
        else CPUAD <= 8'hff;
    end

    logic [7:0] data_P3_5D;
    logic [7:0] data_P2_7D;
    logic [7:0] data_P1_8D;
    
    eprom_16K P3_5D
    (
        .ADDR(cpuA_A[13:0]),
        .CLK(clk),
        .DATA(data_P3_5D),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data),
        .CS_DL(P3_5D_cs),
        .WR(ioctl_wr)
    );
    
    eprom_16K P2_7D
    (
        .ADDR(cpuA_A[13:0]),
        .CLK(clk),
        .DATA(data_P2_7D),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data),
        .CS_DL(P2_7D_cs),
        .WR(ioctl_wr)
    );
    
    eprom_16K P1_8D
    (
        .ADDR(cpuA_A[13:0]),
        .CLK(clk),
        .DATA(data_P1_8D),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data),
        .CS_DL(P1_8D_cs),
        .WR(ioctl_wr)
    );



    always @(posedge clk) begin
             if(!CS_ROM_P3n && !cpuA_nMR)              cpuA_Din <= data_P3_5D;
        else if(!CS_ROM_P2n && !cpuA_nMR)              cpuA_Din <= data_P2_7D; 
        else if(!CS_ROM_P1n && !cpuA_nMR)              cpuA_Din <= data_P1_8D;

        else if(!COIN)                                 cpuA_Din <= {2'b11,SND_BUSY,PLAYER2[1],PLAYER1[1],(PLAYER1[9] & PLAYER2[9]),1'b1,(PLAYER1[0] & PLAYER2[0])};
        else if(!P1)                                   cpuA_Din <= {1'b1,PLAYER1[3],PLAYER1[2],PLAYER1[4],PLAYER1[11],PLAYER1[10],PLAYER1[12],PLAYER1[13]};
        else if(!P2)                                   cpuA_Din <= {1'b1,PLAYER2[3],PLAYER2[2],PLAYER2[4],PLAYER2[11],PLAYER2[10],PLAYER2[12],PLAYER2[13]};
        else if(!P1_P2)                                cpuA_Din <= 8'hFF;
        else if(!DIP1)                                 cpuA_Din <= DSW[7:0];
        else if(!DIP2)                                 cpuA_Din <= DSW[15:8];
        else if(!cpuB_NMI_TRIG_R_cpuA_NMI_ACK_W_CTRL)  cpuA_Din <= 8'hFF;

        else if(!VD_to_cpuAdbus)                       cpuA_Din <= cpuA_Vin;
        else                                           cpuA_Din <= 8'hFF;          
    end



    logic cpuB_nM1;
    logic cpuB_nMR;
    logic cpuB_nIO;
    logic cpuB_nRD;
    logic cpuB_nWR;
    logic cpuB_nRFSH;
    logic cpuB_nHALT;
    logic cpuB_nBUSACK;

    logic cpuB_nINT;
    logic cpuB_nNMI;
    logic cpuB_nBR = 1'b1;
    logic [15:0] cpuB_A;

    logic E4_2_Qn;
    DFF_pseudoAsyncClrPre #(.W(1)) e4_2 (
        .clk(clk),
        .rst(~VIDEO_RSTn),
        .din(1'b1),
        .q(),
        .qn(cpuB_nINT),
        .set(1'b0),
        .clr(~cpuB_nIO),
        .cen(VBL)
    );

    logic  [7:0] cpuB_Din;
    logic  [7:0] cpuB_Dout;


        T80pa z80_E1 (
        .RESET_n(reset_n),
        .CLK    (clk),
        .CEN_p  (Cen_pr1 & ~pause_cpu),
        .CEN_n  (Cen_nr1 & ~pause_cpu),

        .WAIT_n (BWA),
        .INT_n  (cpuB_nINT),
        .NMI_n  (cpuB_nNMI),
        .RD_n   (cpuB_nRD),
        .WR_n   (cpuB_nWR),
        .A      (cpuB_A),
        .DI     (cpuB_Din),
        .DO     (cpuB_Dout),
        .IORQ_n (cpuB_nIO),
        .M1_n   (cpuB_nM1),
        .MREQ_n (cpuB_nMR),
        .BUSRQ_n(1'b1),
        .BUSAK_n(cpuB_nBUSACK),
        .OUT0   (1'b0),
        .RFSH_n (cpuB_nRFSH),
        .HALT_n (cpuB_nHALT)
    );



    logic C5_2_Y3n;
    logic CS_ROM_P6n;
    logic CS_ROM_P5n;
    logic CS_ROM_P4n;





    ttl_74139_nodly c5_2(.Enable_bar(1'b0), .A_2D(cpuB_A[15:14]), .Y_2D({C5_2_Y3n, CS_ROM_P6n, CS_ROM_P5n, CS_ROM_P4n}));
    

    logic C4_1_OR;
    logic C6_4_NOR;
    logic BE_addr;
    logic cpuA_NMI_TRIG_R_cpuB_NMI_ACK_W_CTRL;

    assign C4_1_OR = |cpuB_A[13:12];
    assign C6_4_NOR = ~(C4_1_OR | cpuB_A[11]);

    logic c6nor4_r;
    always @(posedge clk) begin
        c6nor4_r <= C6_4_NOR;
    end
    assign BE_addr = c6nor4_r | C5_2_Y3n; 
    assign BE = ~(BE_addr | cpuB_nMR);




    logic [7:0] data_P6_1D;
    logic [7:0] data_P5_2D;
    logic [7:0] data_P4_3D;

    eprom_16K P6_1D
    (
        .ADDR(cpuB_A[13:0]),
        .CLK(clk),
        .DATA(data_P6_1D),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data),
        .CS_DL(P6_1D_cs),
        .WR(ioctl_wr)
    );

    eprom_16K P5_2D
    (
        .ADDR(cpuB_A[13:0]),
        .CLK(clk),
        .DATA(data_P5_2D),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data),
        .CS_DL(P5_2D_cs),
        .WR(ioctl_wr)
    );

    eprom_16K P4_3D
    (
        .ADDR(cpuB_A[13:0]),
        .CLK(clk),
        .DATA(data_P4_3D),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data),
        .CS_DL(P4_3D_cs),
        .WR(ioctl_wr)
    );



    always @(posedge clk) begin
        if(!CS_ROM_P6n && !cpuB_nMR)                          cpuB_Din <= data_P6_1D;
        else if(!CS_ROM_P5n && !cpuB_nMR)                          cpuB_Din <= data_P5_2D; 
        else if(!CS_ROM_P4n && !cpuB_nMR)                          cpuB_Din <= data_P4_3D;

        else if(!cpuA_NMI_TRIG_R_cpuB_NMI_ACK_W_CTRL && !cpuB_nRD) cpuB_Din <= 8'hFF;    

        else if(!VD_to_cpuBdbus)                                   cpuB_Din <= cpuB_Vin;
        else                                                       cpuB_Din <= 8'hFF; 
    end


    logic cpuB_NMI_TRIG_R;
    logic cpuA_NMI_ACK_W;
    
    assign cpuB_NMI_TRIG_R = cpuB_NMI_TRIG_R_cpuA_NMI_ACK_W_CTRL | cpuA_nRD;
    assign cpuA_NMI_ACK_W  = cpuB_NMI_TRIG_R_cpuA_NMI_ACK_W_CTRL | cpuA_nWR;

    logic C4_4_OR;
    logic C3_2_3NOR;
    logic C3_1_3NOR;
    logic C3_3_3NOR;




    assign C4_4_OR                               = cpuB_A[12] | cpuB_A[11];
    assign C3_2_3NOR                             = ~(C4_4_OR | cpuB_A[13] | C5_2_Y3n);
    assign cpuA_NMI_TRIG_R_cpuB_NMI_ACK_W_CTRL   = ~C3_2_3NOR;
    
    assign C3_3_3NOR = ~(cpuA_NMI_TRIG_R_cpuB_NMI_ACK_W_CTRL | cpuB_nMR | cpuB_nRD);
    assign C3_1_3NOR = ~(cpuA_NMI_TRIG_R_cpuB_NMI_ACK_W_CTRL | cpuB_nMR | cpuB_nWR);

    logic cpuB_NMI_ACK_W;
    logic cpuA_NMI_TRIG_R;

    assign cpuA_NMI_TRIG_R = ~C3_3_3NOR;
    assign cpuB_NMI_ACK_W  = ~C3_1_3NOR;

    DFF_pseudoAsyncClrPre #(.W(1)) c1_1 (
        .clk(clk),
        .rst(~VIDEO_RSTn),
        .din(1'b1),
        .q(),
        .qn(cpuA_nNMI),
        .set(1'b0),
        .clr(~cpuA_NMI_ACK_W),
        .cen(cpuA_NMI_TRIG_R)
    );

    DFF_pseudoAsyncClrPre #(.W(1)) c1_2 (
        .clk(clk),
        .rst(~VIDEO_RSTn),
        .din(1'b1),
        .q(),
        .qn(cpuB_nNMI),
        .set(1'b0),
        .clr(~cpuB_NMI_ACK_W),
        .cen(cpuB_NMI_TRIG_R)
    );

















    pal16l6c_A1_nodly pal16l6_a01_nodly(

        .AMRn(cpuA_nMR),

        .AE_addr(AE_addr),
        .A_addr13(cpuA_A[13]),
        .A_addr12(cpuA_A[12]),
        .A_addr11(cpuA_A[11]),
        .BMRn(cpuB_nMR),

        .BE_addr(BE_addr),
        .B_addr13(cpuB_A[13]),
        .B_addr12(cpuB_A[12]),
        .B_addr11(cpuB_A[11]),
        .ARDn(cpuA_nRD),
        .BRDn(cpuB_nRD),


        .AB_Sel(A_B),

        .FRONT_VIDEO_CSn(FRONT_VIDEO_CSn),
        .VRDn(VRDn),
        .SIDE_VRAM_CSn(SIDE_VRAM_CSn),
        .DISC(DISC),
        .BACK1_VRAM_CSn(BACK1_VRAM_CSn)
    );  

    assign VD_to_cpuAdbus = cpuA_nRD | AE_addr;
    assign VD_to_cpuBdbus = cpuB_nRD | BE_addr;



    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) a2 (.Enable_bar(1'b0), .Select(A_B),
                .A_2D({cpuB_A[3],cpuA_A[3],cpuB_A[2],cpuA_A[2],cpuB_A[1],cpuA_A[1],cpuB_A[0],cpuA_A[0]}), .Y(VA[3:0]));

    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) a3 (.Enable_bar(1'b0), .Select(A_B),
                .A_2D({cpuB_A[7],cpuA_A[7],cpuB_A[6],cpuA_A[6],cpuB_A[5],cpuA_A[5],cpuB_A[4],cpuA_A[4]}), .Y(VA[7:4]));

    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) a4 (.Enable_bar(1'b0), .Select(A_B),
                .A_2D({cpuB_A[11],cpuA_A[11],cpuB_A[10],cpuA_A[10],cpuB_A[9],cpuA_A[9],cpuB_A[8],cpuA_A[8]}), .Y(VA[11:8]));











    logic A7_Y5;
    ttl_74138_nodly a7(
        .Enable1_bar(DISC),
        .Enable2_bar(VDG),
        .Enable3(1'b1),
        .A(VA[10:8]),
        .Y({BACK1_TILE_COLOR_BANK, SIDE_COLOR_BANK, A7_Y5, B1SY, B1SX, FSY, FSX, MSB})
    );





    assign V_out = ((!WBA) ? CPUAD : ( 
                    (!WBB) ? cpuB_Dout : 8'hff ));

    logic [7:0] cpuA_Vin_r, cpuB_Vin_r;

    always @(posedge clk) begin
        if(!VIDEO_RSTn) begin
            cpuA_Vin_r <= 0;
            cpuB_Vin_r <= 0;
        end
        else begin
            if (RLA)
                cpuA_Vin_r <= V_in;
            else
                cpuA_Vin_r <= cpuA_Vin; 

            if (RLB)
                cpuB_Vin_r <= V_in;
            else
                cpuB_Vin_r <= cpuB_Vin;
        end
    end
    assign cpuA_Vin = (!VD_to_cpuAdbus) ? cpuA_Vin_r : 8'hff;
    assign cpuB_Vin = (!VD_to_cpuBdbus) ? cpuB_Vin_r : 8'hff;
endmodule
module AlphaMissionCore_CPU_A_B_sync
(
    input  wire VIDEO_RSTn,
    input  wire clk,
    input  wire pause_cpu,
    input  wire H0,
    input  wire Cen_p,
    input  wire Cen_n,
    input wire clk_13p4b_cen,
    input  wire RESETn,
    input wire [15:0] PLAYER1,
    input wire [15:0] PLAYER2,
	 input wire [15:0] DSW,
    input  wire VBL,
    input  wire BWA,
    input  wire A_B,
    input  wire RLA,
    input  wire RLB,
    input  wire WBA,
    input  wire WBB,
    input  wire VDG,
    output logic VRDn,
    output logic AE,
    output logic BE,

    output logic [7:0] CPUAD,
    output logic CPUA_RD,
    output logic CPUA_WR,


    output logic [11:0] VA,

    output logic [7:0] V_out,
    input  wire  [7:0] V_in,


	input wire         [24:0] ioctl_addr,
	input wire         [7:0] ioctl_data,
	input wire         ioctl_wr,
    

    input  wire  SND_BUSY,
    output logic COIN,
    output logic P1,
    output logic P2,
    output logic P1_P2,
    output logic MCODE,
    output logic DIP1,
    output logic DIP2,


    output logic FRONT_VIDEO_CSn,
    output logic SIDE_VRAM_CSn,
    output logic DISC,
    output logic MSB,
    output logic FSX,
    output logic FSY,
    output logic B1SX,
    output logic B1SY,
    output logic SIDE_COLOR_BANK,
    output logic BACK1_TILE_COLOR_BANK,
    output logic BACK1_VRAM_CSn
);

    logic VD_to_cpuAdbus;
    logic VD_to_cpuBdbus;



    logic P1_8D_cs, P2_7D_cs, P3_5D_cs;
    logic P4_3D_cs, P5_2D_cs, P6_1D_cs;
    selector_cpuAB_rom selector
    (
        .ioctl_addr(ioctl_addr),
        .P1_8D_cs(P1_8D_cs), .P2_7D_cs(P2_7D_cs), .P3_5D_cs(P3_5D_cs),
        .P4_3D_cs(P4_3D_cs), .P5_2D_cs(P5_2D_cs), .P6_1D_cs(P6_1D_cs)
    );



    logic cpuA_nM1;
    logic cpuA_nMR;
    logic cpuA_nIO;
    logic cpuA_nRD;
    logic cpuA_nWR;
    logic cpuA_nRFSH;
    logic cpuA_nHALT;
    logic cpuA_nBUSACK;

    logic cpuA_nINT;
    logic cpuA_nNMI;
    logic [15:0] cpuA_A;
    logic [7:0] cpuA_Vin, cpuB_Vin;

    logic E4_1_Qn;
    DFF_pseudoAsyncClrPre2 #(.W(1)) e4_1 (
        .clk(clk),
        .rst(~VIDEO_RSTn),
        .din(1'b1),
        .q(),
        .qn(cpuA_nINT),
        .set(1'b0),
        .clr(~cpuA_nIO),
        .cen(VBL)
    );

    reg [7:0] cpuA_Din;
    reg [7:0] cpuA_Dout;


    reg reset_n=1'b0;
    reg [5:0] rst_cnt;

    always @(posedge clk)
        if( ~RESETn ) begin
            rst_cnt <= 'd0;
            reset_n <= 1'b0;
        end else begin
            if( rst_cnt != ~6'b0 ) begin
                reset_n <= 1'b0;
                rst_cnt <= rst_cnt + 6'd1;
            end else reset_n <= 1'b1;
        end



    logic Cen_pr1;
    logic Cen_nr1;

    always @(posedge clk) begin
        Cen_pr1 <= Cen_p;
        Cen_nr1 <= Cen_n;
    end


        T80pa z80_E5 (
        .RESET_n(reset_n),
        .CLK    (clk),
        .CEN_p  (Cen_pr1 & ~pause_cpu),
        .CEN_n  (Cen_nr1 & ~pause_cpu),

        .WAIT_n (1'b1),
        .INT_n  (cpuA_nINT),
        .NMI_n  (cpuA_nNMI),
        .RD_n   (cpuA_nRD),
        .WR_n   (cpuA_nWR),
        .A      (cpuA_A),
        .DI     (cpuA_Din),
        .DO     (cpuA_Dout),
        .IORQ_n (cpuA_nIO),
        .M1_n   (cpuA_nM1),
        .MREQ_n (cpuA_nMR),
        .BUSRQ_n(1'b1),
        .BUSAK_n(cpuA_nBUSACK),
        .OUT0   (1'b0),
        .RFSH_n (cpuA_nRFSH),
        .HALT_n (cpuA_nHALT)
    );

    assign CPUA_WR = cpuA_nWR;
    assign CPUA_RD = cpuA_nRD;
    



     logic C5_1_Y3n;
     logic CS_ROM_P3n;
     logic CS_ROM_P2n;
     logic CS_ROM_P1n;





    ttl_74139_nodly c5_1(.Enable_bar(1'b0), .A_2D(cpuA_A[15:14]), .Y_2D({C5_1_Y3n, CS_ROM_P3n, CS_ROM_P2n, CS_ROM_P1n}));

    logic C7_3_OR;
    assign C7_3_OR = cpuA_nMR | C5_1_Y3n;  


    logic C7_1_OR;
    logic C6_1_NOR;
    logic AE_addr;

    assign C7_1_OR = |cpuA_A[13:12];
    assign C6_1_NOR = ~(C7_1_OR | cpuA_A[11]);

     logic c6nor1_r;
    always @(posedge clk) begin
        c6nor1_r <= C6_1_NOR;
    end
    assign AE_addr = c6nor1_r | C5_1_Y3n;
    
    assign AE = ~(AE_addr | cpuA_nMR);


    logic cpuB_NMI_TRIG_R_cpuA_NMI_ACK_W_CTRL;
    logic C2_2_INV;
    logic C7_4_OR;


    assign C2_2_INV = ~cpuA_A[11];
    assign C7_4_OR = |cpuA_A[13:12];











    ttl_74138_nodly c8 (.Enable1_bar(C7_4_OR), .Enable2_bar(C7_3_OR), .Enable3(C2_2_INV), .A(cpuA_A[10:8]), 
                  .Y({cpuB_NMI_TRIG_R_cpuA_NMI_ACK_W_CTRL, DIP2, DIP1, MCODE, P1_P2, P2, P1, COIN}));


    always @(posedge clk) begin


        if(!cpuA_nMR && !C5_1_Y3n) CPUAD <= cpuA_Dout;
        else CPUAD <= 8'hff;
    end

    logic [7:0] data_P3_5D;
    logic [7:0] data_P2_7D;
    logic [7:0] data_P1_8D;
    
    eprom_16K P3_5D
    (
        .ADDR(cpuA_A[13:0]),
        .CLK(clk),
        .DATA(data_P3_5D),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data),
        .CS_DL(P3_5D_cs),
        .WR(ioctl_wr)
    );
    
    eprom_16K P2_7D
    (
        .ADDR(cpuA_A[13:0]),
        .CLK(clk),
        .DATA(data_P2_7D),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data),
        .CS_DL(P2_7D_cs),
        .WR(ioctl_wr)
    );
    
    eprom_16K P1_8D
    (
        .ADDR(cpuA_A[13:0]),
        .CLK(clk),
        .DATA(data_P1_8D),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data),
        .CS_DL(P1_8D_cs),
        .WR(ioctl_wr)
    );



    always @(posedge clk) begin
             if(!CS_ROM_P3n && !cpuA_nMR)              cpuA_Din <= data_P3_5D;
        else if(!CS_ROM_P2n && !cpuA_nMR)              cpuA_Din <= data_P2_7D; 
        else if(!CS_ROM_P1n && !cpuA_nMR)              cpuA_Din <= data_P1_8D;

        else if(!COIN)                                 cpuA_Din <= {2'b11,SND_BUSY,PLAYER2[1],PLAYER1[1],(PLAYER1[9] & PLAYER2[9]),1'b1,(PLAYER1[0] & PLAYER2[0])};
        else if(!P1)                                   cpuA_Din <= {1'b1,PLAYER1[3],PLAYER1[2],PLAYER1[4],PLAYER1[11],PLAYER1[10],PLAYER1[12],PLAYER1[13]};
        else if(!P2)                                   cpuA_Din <= {1'b1,PLAYER2[3],PLAYER2[2],PLAYER2[4],PLAYER2[11],PLAYER2[10],PLAYER2[12],PLAYER2[13]};
        else if(!P1_P2)                                cpuA_Din <= 8'hFF;
        else if(!DIP1)                                 cpuA_Din <= DSW[7:0];
        else if(!DIP2)                                 cpuA_Din <= DSW[15:8];
        else if(!cpuB_NMI_TRIG_R_cpuA_NMI_ACK_W_CTRL)  cpuA_Din <= 8'hFF;

        else if(!VD_to_cpuAdbus)                       cpuA_Din <= cpuA_Vin;
        else                                           cpuA_Din <= 8'hFF;          
    end



    logic cpuB_nM1;
    logic cpuB_nMR;
    logic cpuB_nIO;
    logic cpuB_nRD;
    logic cpuB_nWR;
    logic cpuB_nRFSH;
    logic cpuB_nHALT;
    logic cpuB_nBUSACK;

    logic cpuB_nINT;
    logic cpuB_nNMI;
    logic cpuB_nBR = 1'b1;
    logic [15:0] cpuB_A;

    logic E4_2_Qn;
    DFF_pseudoAsyncClrPre #(.W(1)) e4_2 (
        .clk(clk),
        .rst(~VIDEO_RSTn),
        .din(1'b1),
        .q(),
        .qn(cpuB_nINT),
        .set(1'b0),
        .clr(~cpuB_nIO),
        .cen(VBL)
    );

    logic  [7:0] cpuB_Din;
    logic  [7:0] cpuB_Dout;


        T80pa z80_E1 (
        .RESET_n(reset_n),
        .CLK    (clk),
        .CEN_p  (Cen_pr1 & ~pause_cpu),
        .CEN_n  (Cen_nr1 & ~pause_cpu),

        .WAIT_n (BWA),
        .INT_n  (cpuB_nINT),
        .NMI_n  (cpuB_nNMI),
        .RD_n   (cpuB_nRD),
        .WR_n   (cpuB_nWR),
        .A      (cpuB_A),
        .DI     (cpuB_Din),
        .DO     (cpuB_Dout),
        .IORQ_n (cpuB_nIO),
        .M1_n   (cpuB_nM1),
        .MREQ_n (cpuB_nMR),
        .BUSRQ_n(1'b1),
        .BUSAK_n(cpuB_nBUSACK),
        .OUT0   (1'b0),
        .RFSH_n (cpuB_nRFSH),
        .HALT_n (cpuB_nHALT)
    );



    logic C5_2_Y3n;
    logic CS_ROM_P6n;
    logic CS_ROM_P5n;
    logic CS_ROM_P4n;





    ttl_74139_nodly c5_2(.Enable_bar(1'b0), .A_2D(cpuB_A[15:14]), .Y_2D({C5_2_Y3n, CS_ROM_P6n, CS_ROM_P5n, CS_ROM_P4n}));
    

    logic C4_1_OR;
    logic C6_4_NOR;
    logic BE_addr;
    logic cpuA_NMI_TRIG_R_cpuB_NMI_ACK_W_CTRL;

    assign C4_1_OR = |cpuB_A[13:12];
    assign C6_4_NOR = ~(C4_1_OR | cpuB_A[11]);

    logic c6nor4_r;
    always @(posedge clk) begin
        c6nor4_r <= C6_4_NOR;
    end
    assign BE_addr = c6nor4_r | C5_2_Y3n; 
    assign BE = ~(BE_addr | cpuB_nMR);




    logic [7:0] data_P6_1D;
    logic [7:0] data_P5_2D;
    logic [7:0] data_P4_3D;

    eprom_16K P6_1D
    (
        .ADDR(cpuB_A[13:0]),
        .CLK(clk),
        .DATA(data_P6_1D),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data),
        .CS_DL(P6_1D_cs),
        .WR(ioctl_wr)
    );

    eprom_16K P5_2D
    (
        .ADDR(cpuB_A[13:0]),
        .CLK(clk),
        .DATA(data_P5_2D),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data),
        .CS_DL(P5_2D_cs),
        .WR(ioctl_wr)
    );

    eprom_16K P4_3D
    (
        .ADDR(cpuB_A[13:0]),
        .CLK(clk),
        .DATA(data_P4_3D),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data),
        .CS_DL(P4_3D_cs),
        .WR(ioctl_wr)
    );



    always @(posedge clk) begin
        if(!CS_ROM_P6n && !cpuB_nMR)                          cpuB_Din <= data_P6_1D;
        else if(!CS_ROM_P5n && !cpuB_nMR)                          cpuB_Din <= data_P5_2D; 
        else if(!CS_ROM_P4n && !cpuB_nMR)                          cpuB_Din <= data_P4_3D;

        else if(!cpuA_NMI_TRIG_R_cpuB_NMI_ACK_W_CTRL && !cpuB_nRD) cpuB_Din <= 8'hFF;    

        else if(!VD_to_cpuBdbus)                                   cpuB_Din <= cpuB_Vin;
        else                                                       cpuB_Din <= 8'hFF; 
    end


    logic cpuB_NMI_TRIG_R;
    logic cpuA_NMI_ACK_W;
    
    assign cpuB_NMI_TRIG_R = cpuB_NMI_TRIG_R_cpuA_NMI_ACK_W_CTRL | cpuA_nRD;
    assign cpuA_NMI_ACK_W  = cpuB_NMI_TRIG_R_cpuA_NMI_ACK_W_CTRL | cpuA_nWR;

    logic C4_4_OR;
    logic C3_2_3NOR;
    logic C3_1_3NOR;
    logic C3_3_3NOR;




    assign C4_4_OR                               = cpuB_A[12] | cpuB_A[11];
    assign C3_2_3NOR                             = ~(C4_4_OR | cpuB_A[13] | C5_2_Y3n);
    assign cpuA_NMI_TRIG_R_cpuB_NMI_ACK_W_CTRL   = ~C3_2_3NOR;
    
    assign C3_3_3NOR = ~(cpuA_NMI_TRIG_R_cpuB_NMI_ACK_W_CTRL | cpuB_nMR | cpuB_nRD);
    assign C3_1_3NOR = ~(cpuA_NMI_TRIG_R_cpuB_NMI_ACK_W_CTRL | cpuB_nMR | cpuB_nWR);

    logic cpuB_NMI_ACK_W;
    logic cpuA_NMI_TRIG_R;

    assign cpuA_NMI_TRIG_R = ~C3_3_3NOR;
    assign cpuB_NMI_ACK_W  = ~C3_1_3NOR;

    DFF_pseudoAsyncClrPre #(.W(1)) c1_1 (
        .clk(clk),
        .rst(~VIDEO_RSTn),
        .din(1'b1),
        .q(),
        .qn(cpuA_nNMI),
        .set(1'b0),
        .clr(~cpuA_NMI_ACK_W),
        .cen(cpuA_NMI_TRIG_R)
    );

    DFF_pseudoAsyncClrPre #(.W(1)) c1_2 (
        .clk(clk),
        .rst(~VIDEO_RSTn),
        .din(1'b1),
        .q(),
        .qn(cpuB_nNMI),
        .set(1'b0),
        .clr(~cpuB_NMI_ACK_W),
        .cen(cpuB_NMI_TRIG_R)
    );

















    pal16l6c_A1_nodly pal16l6_a01_nodly(

        .AMRn(cpuA_nMR),

        .AE_addr(AE_addr),
        .A_addr13(cpuA_A[13]),
        .A_addr12(cpuA_A[12]),
        .A_addr11(cpuA_A[11]),
        .BMRn(cpuB_nMR),

        .BE_addr(BE_addr),
        .B_addr13(cpuB_A[13]),
        .B_addr12(cpuB_A[12]),
        .B_addr11(cpuB_A[11]),
        .ARDn(cpuA_nRD),
        .BRDn(cpuB_nRD),


        .AB_Sel(A_B),

        .FRONT_VIDEO_CSn(FRONT_VIDEO_CSn),
        .VRDn(VRDn),
        .SIDE_VRAM_CSn(SIDE_VRAM_CSn),
        .DISC(DISC),
        .BACK1_VRAM_CSn(BACK1_VRAM_CSn)
    );  

    assign VD_to_cpuAdbus = cpuA_nRD | AE_addr;
    assign VD_to_cpuBdbus = cpuB_nRD | BE_addr;



    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) a2 (.Enable_bar(1'b0), .Select(A_B),
                .A_2D({cpuB_A[3],cpuA_A[3],cpuB_A[2],cpuA_A[2],cpuB_A[1],cpuA_A[1],cpuB_A[0],cpuA_A[0]}), .Y(VA[3:0]));

    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) a3 (.Enable_bar(1'b0), .Select(A_B),
                .A_2D({cpuB_A[7],cpuA_A[7],cpuB_A[6],cpuA_A[6],cpuB_A[5],cpuA_A[5],cpuB_A[4],cpuA_A[4]}), .Y(VA[7:4]));

    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) a4 (.Enable_bar(1'b0), .Select(A_B),
                .A_2D({cpuB_A[11],cpuA_A[11],cpuB_A[10],cpuA_A[10],cpuB_A[9],cpuA_A[9],cpuB_A[8],cpuA_A[8]}), .Y(VA[11:8]));











    logic A7_Y5;
    ttl_74138_nodly a7(
        .Enable1_bar(DISC),
        .Enable2_bar(VDG),
        .Enable3(1'b1),
        .A(VA[10:8]),
        .Y({BACK1_TILE_COLOR_BANK, SIDE_COLOR_BANK, A7_Y5, B1SY, B1SX, FSY, FSX, MSB})
    );





    assign V_out = ((!WBA) ? CPUAD : ( 
                    (!WBB) ? cpuB_Dout : 8'hff ));

    logic [7:0] cpuA_Vin_r, cpuB_Vin_r;

    always @(posedge clk) begin
        if(!VIDEO_RSTn) begin
            cpuA_Vin_r <= 0;
            cpuB_Vin_r <= 0;
        end
        else begin
            if (RLA)
                cpuA_Vin_r <= V_in;
            else
                cpuA_Vin_r <= cpuA_Vin; 

            if (RLB)
                cpuB_Vin_r <= V_in;
            else
                cpuB_Vin_r <= cpuB_Vin;
        end
    end
    assign cpuA_Vin = (!VD_to_cpuAdbus) ? cpuA_Vin_r : 8'hff;
    assign cpuB_Vin = (!VD_to_cpuBdbus) ? cpuB_Vin_r : 8'hff;
endmodule