data/full_repos/permissive/475642691/simulations/new/simSTM.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/475642691/simulations/new/simSTM.v:12: Unsupported: Ignoring delay on this delayed statement.\nalways #5 CLK = ~CLK;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/475642691/simulations/new/simSTM.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #12 ST = 1; CN[1]= 1; CN[0] = 0;FS =0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/475642691/simulations/new/simSTM.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #10 ST = 1; CN[1] = 1; CN[0] = 1;FS =0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/475642691/simulations/new/simSTM.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #10 ST = 1; CN[1] = 0; CN[0] = 1;FS =0; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/475642691/simulations/new/simSTM.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #70 $finish;\n    ^\n%Error: data/full_repos/permissive/475642691/simulations/new/simSTM.v:11: Cannot find file containing module: \'STM\'\nSTM K(ST,RST,CN,CLK,FS,FD);\n^~~\n        ... Looked in:\n             data/full_repos/permissive/475642691/simulations/new,data/full_repos/permissive/475642691/STM\n             data/full_repos/permissive/475642691/simulations/new,data/full_repos/permissive/475642691/STM.v\n             data/full_repos/permissive/475642691/simulations/new,data/full_repos/permissive/475642691/STM.sv\n             STM\n             STM.v\n             STM.sv\n             obj_dir/STM\n             obj_dir/STM.v\n             obj_dir/STM.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module simSTM();
reg ST;
reg CLK;
reg[1:0]CN;
reg RST;
reg FS;
wire FD;

STM K(ST,RST,CN,CLK,FS,FD);
always #5 CLK = ~CLK;
initial
begin
ST=1;
RST=0;
CN[0] =0;
CN[1] =0;
FS=0;
CLK=0;

        #12 ST = 1; CN[1]= 1; CN[0] = 0;FS =0;
        #10 ST = 1; CN[1] = 1; CN[0] = 1;FS =0;
        #10 ST = 1; CN[1] = 0; CN[0] = 1;FS =0;

end
initial
begin
    #70 $finish;
end
endmodule
module simSTM();

reg ST;
reg CLK;
reg[1:0]CN;
reg RST;
reg FS;
wire FD;

STM K(ST,RST,CN,CLK,FS,FD);
always #5 CLK = ~CLK;
initial
begin
ST=1;
RST=0;
CN[0] =0;
CN[1] =0;
FS=0;
CLK=0;

        #12 ST = 1; CN[1]= 1; CN[0] = 0;FS =0;
        #10 ST = 1; CN[1] = 1; CN[0] = 1;FS =0;
        #10 ST = 1; CN[1] = 0; CN[0] = 1;FS =0;

end
initial
begin
    #70 $finish;
end
endmodule