data/full_repos/permissive/43339463/alu.v
1: b'%Error: data/full_repos/permissive/43339463/alu.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43339463,data/full_repos/permissive/43339463/defines.v\n             data/full_repos/permissive/43339463,data/full_repos/permissive/43339463/defines.v.v\n             data/full_repos/permissive/43339463,data/full_repos/permissive/43339463/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/43339463/alu.v:30: Define or directive not defined: \'`ALU_ADD\'\n   `ALU_ADD : begin\n   ^~~~~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:30: syntax error, unexpected \':\', expecting endcase\n   `ALU_ADD : begin\n            ^\n%Error: data/full_repos/permissive/43339463/alu.v:31: Define or directive not defined: \'`ALUF_CF\'\n    {flag[`ALUF_CF], r1} = a[SIZE-1:0] + b[SIZE-1:0];\n          ^~~~~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:32: Define or directive not defined: \'`ALUF_OF\'\n    flag[`ALUF_OF] = (a[SIZE-1] & b[SIZE-1] & ~r1[SIZE-1])|(~a[SIZE-1] & ~b[SIZE-1] & r1[SIZE-1]);\n         ^~~~~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:32: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    flag[`ALUF_OF] = (a[SIZE-1] & b[SIZE-1] & ~r1[SIZE-1])|(~a[SIZE-1] & ~b[SIZE-1] & r1[SIZE-1]);\n                 ^\n%Error: data/full_repos/permissive/43339463/alu.v:34: Define or directive not defined: \'`ALU_SUB\'\n   `ALU_SUB : begin\n   ^~~~~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:34: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n   `ALU_SUB : begin\n              ^~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:35: Define or directive not defined: \'`ALUF_CF\'\n    {flag[`ALUF_CF], r1} = a[SIZE-1:0] - b[SIZE-1:0];\n          ^~~~~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:36: Define or directive not defined: \'`ALUF_OF\'\n    flag[`ALUF_OF] = (a[SIZE-1] & ~b[SIZE-1] & ~r1[SIZE-1])|(~a[SIZE-1] & b[SIZE-1] & r1[SIZE-1]);\n         ^~~~~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:36: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    flag[`ALUF_OF] = (a[SIZE-1] & ~b[SIZE-1] & ~r1[SIZE-1])|(~a[SIZE-1] & b[SIZE-1] & r1[SIZE-1]);\n                 ^\n%Error: data/full_repos/permissive/43339463/alu.v:38: Define or directive not defined: \'`ALU_AND\'\n   `ALU_AND : begin\n   ^~~~~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:38: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n   `ALU_AND : begin\n              ^~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:40: Define or directive not defined: \'`ALUF_CF\'\n    flag[`ALUF_CF] = 0;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:40: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    flag[`ALUF_CF] = 0;\n                 ^\n%Error: data/full_repos/permissive/43339463/alu.v:41: Define or directive not defined: \'`ALUF_OF\'\n    flag[`ALUF_OF] = 0;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:41: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    flag[`ALUF_OF] = 0;\n                 ^\n%Error: data/full_repos/permissive/43339463/alu.v:43: Define or directive not defined: \'`ALU_OR\'\n   `ALU_OR : begin\n   ^~~~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:43: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n   `ALU_OR : begin\n             ^~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:45: Define or directive not defined: \'`ALUF_CF\'\n    flag[`ALUF_CF] = 0;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:45: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    flag[`ALUF_CF] = 0;\n                 ^\n%Error: data/full_repos/permissive/43339463/alu.v:46: Define or directive not defined: \'`ALUF_OF\'\n    flag[`ALUF_OF] = 0;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:46: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    flag[`ALUF_OF] = 0;\n                 ^\n%Error: data/full_repos/permissive/43339463/alu.v:48: Define or directive not defined: \'`ALU_OR\'\n   `ALU_OR : begin\n   ^~~~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:48: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n   `ALU_OR : begin\n             ^~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:50: Define or directive not defined: \'`ALUF_CF\'\n    flag[`ALUF_CF] = 0;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:50: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    flag[`ALUF_CF] = 0;\n                 ^\n%Error: data/full_repos/permissive/43339463/alu.v:51: Define or directive not defined: \'`ALUF_OF\'\n    flag[`ALUF_OF] = 0;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:51: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    flag[`ALUF_OF] = 0;\n                 ^\n%Error: data/full_repos/permissive/43339463/alu.v:53: Define or directive not defined: \'`ALU_XOR\'\n   `ALU_XOR : begin\n   ^~~~~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:53: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n   `ALU_XOR : begin\n              ^~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:55: Define or directive not defined: \'`ALUF_CF\'\n    flag[`ALUF_CF] = 0;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:55: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    flag[`ALUF_CF] = 0;\n                 ^\n%Error: data/full_repos/permissive/43339463/alu.v:56: Define or directive not defined: \'`ALUF_OF\'\n    flag[`ALUF_OF] = 0;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:56: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    flag[`ALUF_OF] = 0;\n                 ^\n%Error: data/full_repos/permissive/43339463/alu.v:58: Define or directive not defined: \'`ALU_MUL\'\n   `ALU_MUL : begin\n   ^~~~~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:58: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n   `ALU_MUL : begin\n              ^~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:60: Define or directive not defined: \'`ALUF_CF\'\n    flag[`ALUF_CF] = (r2 != 0);\n         ^~~~~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:60: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    flag[`ALUF_CF] = (r2 != 0);\n                 ^\n%Error: data/full_repos/permissive/43339463/alu.v:61: Define or directive not defined: \'`ALUF_OF\'\n    flag[`ALUF_OF] = (r2 != 0);\n         ^~~~~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:61: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    flag[`ALUF_OF] = (r2 != 0);\n                 ^\n%Error: data/full_repos/permissive/43339463/alu.v:63: Define or directive not defined: \'`ALU_DIV\'\n   `ALU_DIV : begin\n   ^~~~~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:63: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n   `ALU_DIV : begin\n              ^~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:69: Define or directive not defined: \'`ALU_IMUL\'\n   `ALU_IMUL : begin\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:69: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n   `ALU_IMUL : begin\n               ^~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:71: Define or directive not defined: \'`ALUF_CF\'\n    flag[`ALUF_CF] = (r2 != 0);\n         ^~~~~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:71: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    flag[`ALUF_CF] = (r2 != 0);\n                 ^\n%Error: data/full_repos/permissive/43339463/alu.v:72: Define or directive not defined: \'`ALUF_OF\'\n    flag[`ALUF_OF] = (r2 != 0);\n         ^~~~~~~~\n%Error: data/full_repos/permissive/43339463/alu.v:72: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    flag[`ALUF_OF] = (r2 != 0);\n                 ^\n%Error: data/full_repos/permissive/43339463/alu.v:74: Define or directive not defined: \'`ALU_IDIV\'\n   `ALU_IDIV : begin\n   ^~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module alu_impl #(parameter SIZE = 16, parameter LOG2 = 4) (input [SIZE*2-1:0] a, b, output [SIZE-1:0] o1, o2, input [4:0] func, input [15:0] flag_i, output [15:0] flag_o, input en);
	reg [SIZE-1:0] r1, r2;
	reg [15:0] flag;
	
	always @(posedge en) begin
		case (func)
			`ALU_ADD : begin
				{flag[`ALUF_CF], r1} = a[SIZE-1:0] + b[SIZE-1:0];
				flag[`ALUF_OF] = (a[SIZE-1] & b[SIZE-1] & ~r1[SIZE-1])|(~a[SIZE-1] & ~b[SIZE-1] & r1[SIZE-1]);
			end
			`ALU_SUB : begin
				{flag[`ALUF_CF], r1} = a[SIZE-1:0] - b[SIZE-1:0];
				flag[`ALUF_OF] = (a[SIZE-1] & ~b[SIZE-1] & ~r1[SIZE-1])|(~a[SIZE-1] & b[SIZE-1] & r1[SIZE-1]);
			end
			`ALU_AND : begin
				r1 = a[SIZE-1:0] & b[SIZE-1:0];
				flag[`ALUF_CF] = 0;
				flag[`ALUF_OF] = 0;
			end
			`ALU_OR : begin
				r1 = a[SIZE-1:0] & b[SIZE-1:0];
				flag[`ALUF_CF] = 0;
				flag[`ALUF_OF] = 0;
			end
			`ALU_OR : begin
				r1 = a[SIZE-1:0] | b[SIZE-1:0];
				flag[`ALUF_CF] = 0;
				flag[`ALUF_OF] = 0;
			end
			`ALU_XOR : begin
				r1 = a[SIZE-1:0] ^ b[SIZE-1:0];
				flag[`ALUF_CF] = 0;
				flag[`ALUF_OF] = 0;
			end
			`ALU_MUL : begin
				{r2, r1} = a[SIZE-1:0] * b[SIZE-1:0];
				flag[`ALUF_CF] = (r2 != 0);
				flag[`ALUF_OF] = (r2 != 0);
			end
			`ALU_DIV : begin
				r2 = b[SIZE*2-1:0] % a[SIZE-1:0];
				r1 = b[SIZE*2-1:0] / a[SIZE-1:0];


			end
			`ALU_IMUL : begin
				{r2, r1} = $signed(a[SIZE-1:0]) * $signed(b[SIZE-1:0]);
				flag[`ALUF_CF] = (r2 != 0);
				flag[`ALUF_OF] = (r2 != 0);
			end
			`ALU_IDIV : begin

				r2 = $signed(b[SIZE*2-1:0]) % $signed(a[SIZE*2-1:0]);
				r1 = $signed(b[SIZE*2-1:0]) / $signed(a[SIZE*2-1:0]);


			end
			`ALU_NOT : begin
				r1 = ~a[SIZE-1:0];
			end
			`ALU_NEG : begin
				r1 = - a[SIZE-1:0];
				flag[`ALUF_CF] = (r1 == 0);
			end
			`ALU_INC : begin
				r1 = a[SIZE-1:0] + 16'd1;
			end
			`ALU_DEC : begin
				r1 = a[SIZE-1:0] - 16'd1;
			end
			`ALU_SAL : begin
				if (b[LOG2-1:0] != 0) begin
					{flag[`ALUF_CF], r1} = a[SIZE-1:0] << b[LOG2-1:0];
				end
			end
			`ALU_SAR : begin
				if (b[LOG2-1:0] != 0) begin
					r1 = $signed(a[SIZE-1:0]) >>> b[LOG2-1:0];
					flag[`ALUF_CF] = a[b[LOG2-1:0] - 1];
				end
			end
			`ALU_SHR : begin
				if (b[LOG2-1:0] != 0) begin
					r1 = a[SIZE-1:0] >> b[LOG2-1:0];
					flag[`ALUF_CF] = a[b[LOG2-1:0] - 1];
				end
			end
			`ALU_RCL : begin
				if (b[LOG2-1:0] != 0) begin
					{flag[`ALUF_CF], r1, r2} = {a[SIZE-1:0], flag[`ALUF_CF], a[SIZE-1:0]} << (b[LOG2-1:0] - 1);
				end
			end
			`ALU_RCR : begin
				if (b[LOG2-1:0] != 0) begin
					{flag[`ALUF_CF], r1} = {a[SIZE-1:0], flag[`ALUF_CF], a[SIZE-1:0]} >> b[LOG2-1:0];
				end
			end
			`ALU_ROL : begin
				if (b[LOG2-1:0] != 0) begin
					{r1, r2} = {a[SIZE-1:0], a[SIZE-1:0]} << b[LOG2-1:0];
					flag[`ALUF_CF] = r1[0];
				end
			end
			`ALU_ROR : begin
				if (b[LOG2-1:0] != 0) begin
					{r2, r1} = {a[SIZE-1:0], a[SIZE-1:0]} >> b[LOG2-1:0];
					flag[`ALUF_CF] = r1[SIZE-1];
				end
			end
		endcase
		flag[`ALUF_ZF] = (r1 == 0);
		flag[`ALUF_SF] = r1[SIZE-1];
	end
	
	assign o1 = (en) ? r1 : {SIZE{1'bz}};
	assign o2 = (en) ? r2 : {SIZE{1'bz}};
	assign flag_o = flag;
endmodule
module alu_impl #(parameter SIZE = 16, parameter LOG2 = 4) (input [SIZE*2-1:0] a, b, output [SIZE-1:0] o1, o2, input [4:0] func, input [15:0] flag_i, output [15:0] flag_o, input en);

	reg [SIZE-1:0] r1, r2;
	reg [15:0] flag;
	
	always @(posedge en) begin
		case (func)
			`ALU_ADD : begin
				{flag[`ALUF_CF], r1} = a[SIZE-1:0] + b[SIZE-1:0];
				flag[`ALUF_OF] = (a[SIZE-1] & b[SIZE-1] & ~r1[SIZE-1])|(~a[SIZE-1] & ~b[SIZE-1] & r1[SIZE-1]);
			end
			`ALU_SUB : begin
				{flag[`ALUF_CF], r1} = a[SIZE-1:0] - b[SIZE-1:0];
				flag[`ALUF_OF] = (a[SIZE-1] & ~b[SIZE-1] & ~r1[SIZE-1])|(~a[SIZE-1] & b[SIZE-1] & r1[SIZE-1]);
			end
			`ALU_AND : begin
				r1 = a[SIZE-1:0] & b[SIZE-1:0];
				flag[`ALUF_CF] = 0;
				flag[`ALUF_OF] = 0;
			end
			`ALU_OR : begin
				r1 = a[SIZE-1:0] & b[SIZE-1:0];
				flag[`ALUF_CF] = 0;
				flag[`ALUF_OF] = 0;
			end
			`ALU_OR : begin
				r1 = a[SIZE-1:0] | b[SIZE-1:0];
				flag[`ALUF_CF] = 0;
				flag[`ALUF_OF] = 0;
			end
			`ALU_XOR : begin
				r1 = a[SIZE-1:0] ^ b[SIZE-1:0];
				flag[`ALUF_CF] = 0;
				flag[`ALUF_OF] = 0;
			end
			`ALU_MUL : begin
				{r2, r1} = a[SIZE-1:0] * b[SIZE-1:0];
				flag[`ALUF_CF] = (r2 != 0);
				flag[`ALUF_OF] = (r2 != 0);
			end
			`ALU_DIV : begin
				r2 = b[SIZE*2-1:0] % a[SIZE-1:0];
				r1 = b[SIZE*2-1:0] / a[SIZE-1:0];


			end
			`ALU_IMUL : begin
				{r2, r1} = $signed(a[SIZE-1:0]) * $signed(b[SIZE-1:0]);
				flag[`ALUF_CF] = (r2 != 0);
				flag[`ALUF_OF] = (r2 != 0);
			end
			`ALU_IDIV : begin

				r2 = $signed(b[SIZE*2-1:0]) % $signed(a[SIZE*2-1:0]);
				r1 = $signed(b[SIZE*2-1:0]) / $signed(a[SIZE*2-1:0]);


			end
			`ALU_NOT : begin
				r1 = ~a[SIZE-1:0];
			end
			`ALU_NEG : begin
				r1 = - a[SIZE-1:0];
				flag[`ALUF_CF] = (r1 == 0);
			end
			`ALU_INC : begin
				r1 = a[SIZE-1:0] + 16'd1;
			end
			`ALU_DEC : begin
				r1 = a[SIZE-1:0] - 16'd1;
			end
			`ALU_SAL : begin
				if (b[LOG2-1:0] != 0) begin
					{flag[`ALUF_CF], r1} = a[SIZE-1:0] << b[LOG2-1:0];
				end
			end
			`ALU_SAR : begin
				if (b[LOG2-1:0] != 0) begin
					r1 = $signed(a[SIZE-1:0]) >>> b[LOG2-1:0];
					flag[`ALUF_CF] = a[b[LOG2-1:0] - 1];
				end
			end
			`ALU_SHR : begin
				if (b[LOG2-1:0] != 0) begin
					r1 = a[SIZE-1:0] >> b[LOG2-1:0];
					flag[`ALUF_CF] = a[b[LOG2-1:0] - 1];
				end
			end
			`ALU_RCL : begin
				if (b[LOG2-1:0] != 0) begin
					{flag[`ALUF_CF], r1, r2} = {a[SIZE-1:0], flag[`ALUF_CF], a[SIZE-1:0]} << (b[LOG2-1:0] - 1);
				end
			end
			`ALU_RCR : begin
				if (b[LOG2-1:0] != 0) begin
					{flag[`ALUF_CF], r1} = {a[SIZE-1:0], flag[`ALUF_CF], a[SIZE-1:0]} >> b[LOG2-1:0];
				end
			end
			`ALU_ROL : begin
				if (b[LOG2-1:0] != 0) begin
					{r1, r2} = {a[SIZE-1:0], a[SIZE-1:0]} << b[LOG2-1:0];
					flag[`ALUF_CF] = r1[0];
				end
			end
			`ALU_ROR : begin
				if (b[LOG2-1:0] != 0) begin
					{r2, r1} = {a[SIZE-1:0], a[SIZE-1:0]} >> b[LOG2-1:0];
					flag[`ALUF_CF] = r1[SIZE-1];
				end
			end
		endcase
		flag[`ALUF_ZF] = (r1 == 0);
		flag[`ALUF_SF] = r1[SIZE-1];
	end
	
	assign o1 = (en) ? r1 : {SIZE{1'bz}};
	assign o2 = (en) ? r2 : {SIZE{1'bz}};
	assign flag_o = flag;
endmodule