data/full_repos/permissive/419538859/lab6/sim/lab6_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/419538859/lab6/sim/lab6_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #(clkper / 2)  clk = ~clk;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab6/sim/lab6_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #20;   \n ^\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab6/sim/lab6_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n #32;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab6/sim/lab6_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab6/sim/lab6_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab6/sim/lab6_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab6/sim/lab6_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab6/sim/lab6_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab6/sim/lab6_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab6/sim/lab6_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n #500;\n ^\n%Error: data/full_repos/permissive/419538859/lab6/sim/lab6_tb.v:51: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("wave.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/419538859/lab6/sim/lab6_tb.v:52: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,testbench);\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module 	testbench;
reg		clk, reset;
reg		[2:0]column;
wire	[2:0]sel;		
wire	[6:0]seg7;		
wire 	clk_sel;
wire	[3:0] key_code;

lab6 lab6_instance(
		.clk(clk),
		.reset(reset),
		.column(column),
		.sel(sel),
		.seg7(seg7));

parameter	exp = 1; 
parameter clkper = 2;
initial clk=1;

always 
begin
	#(clkper / 2)  clk = ~clk;
end

initial
begin
 reset = 1'b1;		
 #20;			
 reset = 1'b0;
 #32;
 column= 3'b011;
 #100;
 column= 3'b101;
 #100;
 column= 3'b110;
 #100;
 column= 3'b011;
 #100;
 column= 3'b101;
 #100;
 column= 3'b110;
 #100;
 #500;
 $finish;
end


initial begin
	$dumpfile("wave.vcd");
	$dumpvars(0,testbench);
end

endmodule
module 	testbench;

reg		clk, reset;
reg		[2:0]column;
wire	[2:0]sel;		
wire	[6:0]seg7;		
wire 	clk_sel;
wire	[3:0] key_code;

lab6 lab6_instance(
		.clk(clk),
		.reset(reset),
		.column(column),
		.sel(sel),
		.seg7(seg7));

parameter	exp = 1; 
parameter clkper = 2;
initial clk=1;

always 
begin
	#(clkper / 2)  clk = ~clk;
end

initial
begin
 reset = 1'b1;		
 #20;			
 reset = 1'b0;
 #32;
 column= 3'b011;
 #100;
 column= 3'b101;
 #100;
 column= 3'b110;
 #100;
 column= 3'b011;
 #100;
 column= 3'b101;
 #100;
 column= 3'b110;
 #100;
 #500;
 $finish;
end


initial begin
	$dumpfile("wave.vcd");
	$dumpvars(0,testbench);
end

endmodule