data/full_repos/permissive/432333689/uart with aes/decryption_uart/sim_1/imports/new/rx_sim.v
1: b'%Error: Cannot find file containing module: with\n        ... Looked in:\n             data/full_repos/permissive/432333689/uart/with\n             data/full_repos/permissive/432333689/uart/with.v\n             data/full_repos/permissive/432333689/uart/with.sv\n             with\n             with.v\n             with.sv\n             obj_dir/with\n             obj_dir/with.v\n             obj_dir/with.sv\n%Error: Cannot find file containing module: aes/decryption_uart/sim_1/imports/new,data/full_repos/permissive/432333689\n%Error: Cannot find file containing module: data/full_repos/permissive/432333689/uart\n%Error: Cannot find file containing module: aes/decryption_uart/sim_1/imports/new/rx_sim.v\n%Error: Exiting due to 4 error(s)\n'
module rx_sim(  );

parameter clock_per_bit=104170*2;
parameter data_size=10;
parameter data_freq=16;
parameter data_times=3;
reg clk,data_in;
wire  out_tx;


localparam [7:0]T=8'b01010100;
localparam [7:0]h=8'b01101000;
localparam [7:0]e=8'b01100101;
localparam [7:0]s=8'b00100000;
localparam [7:0]a=8'b01100001;
localparam [7:0]r=8'b01110010;
localparam [7:0]t=8'b01110100 ;
localparam [7:0]o=8'b01101111;
localparam [7:0]f=8'b01100110;
localparam [7:0]c=8'b01100011;
localparam [7:0]d=8'b01100100;
localparam [7:0]F=8'b00101110;


localparam [data_size*data_freq-1:0]data={data_uart(T),data_uart(h),data_uart(e),data_uart(s),data_uart(a),data_uart(r),data_uart(t),data_uart(s),data_uart(o),data_uart(f),data_uart(s),data_uart(c),data_uart(o),data_uart(d),data_uart(e),data_uart(F)};


main uut1(
    clk,
    data_in,

    out_tx

    );
integer i=0,j=0,k=0;


initial begin
clk=0;
    for(i=0;i<data_times;i=i+1)
    begin
    for (j=data_freq-1; j>=0; j=j-1)
    begin
    for (k=0; k<data_size; k=k+1)
       begin
        data_in=data[j*data_size+k];
        #clock_per_bit;
       end
    end
    end

end

always 
#10 clk =  ! clk;


function [data_size-1:0] data_uart;
    input[7:0] val;
begin
    data_uart={1'b1,val,1'b0};
end
endfunction
endmodule
module rx_sim(  );


parameter clock_per_bit=104170*2;
parameter data_size=10;
parameter data_freq=16;
parameter data_times=3;
reg clk,data_in;
wire  out_tx;


localparam [7:0]T=8'b01010100;
localparam [7:0]h=8'b01101000;
localparam [7:0]e=8'b01100101;
localparam [7:0]s=8'b00100000;
localparam [7:0]a=8'b01100001;
localparam [7:0]r=8'b01110010;
localparam [7:0]t=8'b01110100 ;
localparam [7:0]o=8'b01101111;
localparam [7:0]f=8'b01100110;
localparam [7:0]c=8'b01100011;
localparam [7:0]d=8'b01100100;
localparam [7:0]F=8'b00101110;


localparam [data_size*data_freq-1:0]data={data_uart(T),data_uart(h),data_uart(e),data_uart(s),data_uart(a),data_uart(r),data_uart(t),data_uart(s),data_uart(o),data_uart(f),data_uart(s),data_uart(c),data_uart(o),data_uart(d),data_uart(e),data_uart(F)};


main uut1(
    clk,
    data_in,

    out_tx

    );
integer i=0,j=0,k=0;


initial begin
clk=0;
    for(i=0;i<data_times;i=i+1)
    begin
    for (j=data_freq-1; j>=0; j=j-1)
    begin
    for (k=0; k<data_size; k=k+1)
       begin
        data_in=data[j*data_size+k];
        #clock_per_bit;
       end
    end
    end

end

always 
#10 clk =  ! clk;


function [data_size-1:0] data_uart;
    input[7:0] val;
begin
    data_uart={1'b1,val,1'b0};
end
endfunction
endmodule