data/full_repos/permissive/469273213/multiplier/rtl/fullAdder.v
data/verilator_xmls/7929ae27-31ba-4cd0-b6f5-c5e07bae1ead.xml
module fullAdder (   
    input wire  a,
    input wire  b,
    input wire  c_in,
    output wire c_out,
    output wire s 
);
    
        assign {c_out, s} = a + b + c_in;    


endmodule
module fullAdder (   
    input wire  a,
    input wire  b,
    input wire  c_in,
    output wire c_out,
    output wire s 
);

    
        assign {c_out, s} = a + b + c_in;    


endmodule