data/full_repos/permissive/421048855/Circuits/Sequential Logic/Counters/Count clock.v
1: b'%Error: Cannot find file containing module: Logic/Counters,data/full_repos/permissive/421048855\n        ... Looked in:\n             data/full_repos/permissive/421048855/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/421048855\n             data/full_repos/permissive/421048855/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/421048855.v\n             data/full_repos/permissive/421048855/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/421048855.sv\n             Logic/Counters,data/full_repos/permissive/421048855\n             Logic/Counters,data/full_repos/permissive/421048855.v\n             Logic/Counters,data/full_repos/permissive/421048855.sv\n             obj_dir/Logic/Counters,data/full_repos/permissive/421048855\n             obj_dir/Logic/Counters,data/full_repos/permissive/421048855.v\n             obj_dir/Logic/Counters,data/full_repos/permissive/421048855.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/421048855/Circuits/Sequential\n%Error: Cannot find file containing module: Logic/Counters/Count\n%Error: Cannot find file containing module: clock.v\n%Error: Exiting due to 4 error(s)\n'
module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 
wire over[4:0];
reg am_pm;
assign over[1] = (ss[7:4] == 'd5) && (ss[3:0] == 'd9);
assign over[2] = (ss[7:4] == 'd5) && (ss[3:0] == 'd9) && (mm[3:0] == 'd9);
assign over[3] = (ss[7:4] == 'd5) && (ss[3:0] == 'd9) && (mm[3:0] == 'd9) && (mm[7:4] == 'd5);
assign over[4] = (ss[7:4] == 'd5) && (ss[3:0] == 'd9) && (mm[3:0] == 'd9) && (mm[7:4] == 'd5) && ((hh[3:0]== 'd2) && (hh[7:4] == 'd1)) || ((ss[7:4] == 'd5) && (ss[3:0] == 'd9) && (mm[3:0] == 'd9) && (mm[7:4] == 'd5) && ((hh[3:0]== 'd9) && (hh[7:4] == 'd0)));
cnt u_cnt_s(
.clk (clk),
.reset (reset),
.ena (ena),
.upper (4'd9),
.num (ss[3:0]),
.over (over[0])
);
cnt u_cnt_ss(
.clk (clk),
.reset (reset),
.ena (over[0]),
.upper (4'd5),
.num (ss[7:4]),
.over ()
);

cnt u_cnt_m(
.clk (clk),
.reset (reset),
.ena (over[1]),
.upper (4'd9),
.num (mm[3:0]),
.over ()
);

cnt u_cnt_mm(
.clk (clk),
.reset (reset),
.ena (over[2]),
.upper (4'd5),
.num (mm[7:4]),
.over ()
);

cnt_hh_one u_cnt_hh_one(
.clk (clk),
.reset (reset),
.ena	(over[3]),
.hh_ten (hh[7:4]),
.hh_one (hh[3:0]),
.over 	()
);

cnt_hh_ten u_cnt_hh_ten(
.clk	(clk),
.reset	(reset),
.ena	(over[4]),
.hh_ten	(hh[7:4])
);
 always @(posedge clk) begin
	if(reset) begin
		am_pm <= 'b0;
	end
	else if((ss[7:4] == 'd5) && (ss[3:0] == 'd9) && (mm[3:0] == 'd9) && (mm[7:4] == 'd5) && ((hh[3:0]== 'd1) && (hh[7:4] == 'd1))) begin
		am_pm <= ~ am_pm;
	end
end
assign pm = am_pm; 
endmodule
module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss);
 
wire over[4:0];
reg am_pm;
assign over[1] = (ss[7:4] == 'd5) && (ss[3:0] == 'd9);
assign over[2] = (ss[7:4] == 'd5) && (ss[3:0] == 'd9) && (mm[3:0] == 'd9);
assign over[3] = (ss[7:4] == 'd5) && (ss[3:0] == 'd9) && (mm[3:0] == 'd9) && (mm[7:4] == 'd5);
assign over[4] = (ss[7:4] == 'd5) && (ss[3:0] == 'd9) && (mm[3:0] == 'd9) && (mm[7:4] == 'd5) && ((hh[3:0]== 'd2) && (hh[7:4] == 'd1)) || ((ss[7:4] == 'd5) && (ss[3:0] == 'd9) && (mm[3:0] == 'd9) && (mm[7:4] == 'd5) && ((hh[3:0]== 'd9) && (hh[7:4] == 'd0)));
cnt u_cnt_s(
.clk (clk),
.reset (reset),
.ena (ena),
.upper (4'd9),
.num (ss[3:0]),
.over (over[0])
);
cnt u_cnt_ss(
.clk (clk),
.reset (reset),
.ena (over[0]),
.upper (4'd5),
.num (ss[7:4]),
.over ()
);

cnt u_cnt_m(
.clk (clk),
.reset (reset),
.ena (over[1]),
.upper (4'd9),
.num (mm[3:0]),
.over ()
);

cnt u_cnt_mm(
.clk (clk),
.reset (reset),
.ena (over[2]),
.upper (4'd5),
.num (mm[7:4]),
.over ()
);

cnt_hh_one u_cnt_hh_one(
.clk (clk),
.reset (reset),
.ena	(over[3]),
.hh_ten (hh[7:4]),
.hh_one (hh[3:0]),
.over 	()
);

cnt_hh_ten u_cnt_hh_ten(
.clk	(clk),
.reset	(reset),
.ena	(over[4]),
.hh_ten	(hh[7:4])
);
 always @(posedge clk) begin
	if(reset) begin
		am_pm <= 'b0;
	end
	else if((ss[7:4] == 'd5) && (ss[3:0] == 'd9) && (mm[3:0] == 'd9) && (mm[7:4] == 'd5) && ((hh[3:0]== 'd1) && (hh[7:4] == 'd1))) begin
		am_pm <= ~ am_pm;
	end
end
assign pm = am_pm; 
endmodule