data/full_repos/permissive/484799296/verilog/rom/top_tb.v
1: b'%Error: data/full_repos/permissive/484799296/verilog/rom/top_tb.v:13: Unsupported or unknown PLI call: $monitor\n        $monitor("%d\\t%h", addr, data);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/rom/top_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n        #1 addr=1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/rom/top_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #1 addr=2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/rom/top_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #1 addr=3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/rom/top_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #1 addr=4;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/rom/top_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #1 addr=5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/rom/top_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #1 addr=6;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/rom/top_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #1 addr=7;\n        ^\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();

    reg [11:0] addr;
    wire [7:0] data;

    rom ROM(addr, data);

    initial begin
        addr=0;
        $display("addr\tdata\t");
        $monitor("%d\t%h", addr, data);

        #1 addr=1;
        #1 addr=2;
        #1 addr=3;
        #1 addr=4;
        #1 addr=5;
        #1 addr=6;
        #1 addr=7;

    end

endmodule
module testbench();


    reg [11:0] addr;
    wire [7:0] data;

    rom ROM(addr, data);

    initial begin
        addr=0;
        $display("addr\tdata\t");
        $monitor("%d\t%h", addr, data);

        #1 addr=1;
        #1 addr=2;
        #1 addr=3;
        #1 addr=4;
        #1 addr=5;
        #1 addr=6;
        #1 addr=7;

    end

endmodule