data/full_repos/permissive/434837003/test/generate.v
1: b"%Error: data/full_repos/permissive/434837003/test/generate.v:20: syntax error, unexpected bit, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nfor (i=0; i<SIZE; i=i+1) begin : bit\n                                 ^~~\n%Error: data/full_repos/permissive/434837003/test/generate.v:57: syntax error, unexpected bit, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nfor(i=0; i<SIZE; i=i+1) begin:bit\n                              ^~~\n%Error: data/full_repos/permissive/434837003/test/generate.v:164: syntax error, unexpected byte, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\n        for (i=0; i<8; i=i+1) begin:byte\n                                    ^~~~\n%Error: data/full_repos/permissive/434837003/test/generate.v:178: syntax error, unexpected '[', expecting IDENTIFIER or '=' or do or final\n            byte[7].p.read_mem(address, data[63:56]);\n                ^\n%Error: Exiting due to 4 error(s)\n"
module test;
parameter p = 0, q = 0;
wire a, b, c;






if (p == 1)
    if (q == 0) begin : u1
        and g1(a, b, c);
    end
    else if (q == 2) begin : u1
        or g1(a, b, c);
    end

    else ;
else if (p == 2)
    case (q)
    0, 1, 2: begin : u1
        xor g1(a, b, c);
    end
    default: begin : u1
        xnor g1(a, b, c);
    end
    endcase

endmodule
module test;

parameter p = 0, q = 0;
wire a, b, c;






if (p == 1)
    if (q == 0) begin : u1
        and g1(a, b, c);
    end
    else if (q == 2) begin : u1
        or g1(a, b, c);
    end

    else ;
else if (p == 2)
    case (q)
    0, 1, 2: begin : u1
        xor g1(a, b, c);
    end
    default: begin : u1
        xnor g1(a, b, c);
    end
    endcase

endmodule