data/full_repos/permissive/431362747/Processor/Processor.srcs/sources_1/new/top_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/431362747/Processor/Processor.srcs/sources_1/new/top_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n            forever #1 clk = ~clk;\n                    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/431362747/Processor/Processor.srcs/sources_1/new/top_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n            forever #1 enable = 1\'b1;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/431362747/Processor/Processor.srcs/sources_1/new/top_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n            #10\n            ^\n%Error: data/full_repos/permissive/431362747/Processor/Processor.srcs/sources_1/new/top_tb.v:30: Cannot find file containing module: \'Processor\'\n    Processor Processor_DUT(\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/431362747/Processor/Processor.srcs/sources_1/new,data/full_repos/permissive/431362747/Processor\n             data/full_repos/permissive/431362747/Processor/Processor.srcs/sources_1/new,data/full_repos/permissive/431362747/Processor.v\n             data/full_repos/permissive/431362747/Processor/Processor.srcs/sources_1/new,data/full_repos/permissive/431362747/Processor.sv\n             Processor\n             Processor.v\n             Processor.sv\n             obj_dir/Processor\n             obj_dir/Processor.v\n             obj_dir/Processor.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_tb(

    );
    
    reg clk;
    reg enable;
    
    Processor Processor_DUT(
    .en(enable),
    .clk(clk)    
    );
    

    initial 
        begin
            clk = 1'b0;
            forever #1 clk = ~clk;
        end





    initial 
        begin
            enable = 1'b0;
            #10
            forever #1 enable = 1'b1;
            
        end
   
endmodule
module top_tb(

    );

    
    reg clk;
    reg enable;
    
    Processor Processor_DUT(
    .en(enable),
    .clk(clk)    
    );
    

    initial 
        begin
            clk = 1'b0;
            forever #1 clk = ~clk;
        end





    initial 
        begin
            enable = 1'b0;
            #10
            forever #1 enable = 1'b1;
            
        end
   
endmodule