data/full_repos/permissive/465389471/TLC_topModule_labsland.v
1: b'%Warning-WIDTH: data/full_repos/permissive/465389471/TLC_topModule_labsland.v:60: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'an\' generates 4 bits.\n                                                                                : ... In instance TLC_topModule_labsland\n    assign LEDG[0] = an;\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/465389471/TLC_topModule_labsland.v:67: Cannot find file containing module: \'TwelveHourBCDclock\'\nTwelveHourBCDclock BCD_clk(\n^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/465389471,data/full_repos/permissive/465389471/TwelveHourBCDclock\n             data/full_repos/permissive/465389471,data/full_repos/permissive/465389471/TwelveHourBCDclock.v\n             data/full_repos/permissive/465389471,data/full_repos/permissive/465389471/TwelveHourBCDclock.sv\n             TwelveHourBCDclock\n             TwelveHourBCDclock.v\n             TwelveHourBCDclock.sv\n             obj_dir/TwelveHourBCDclock\n             obj_dir/TwelveHourBCDclock.v\n             obj_dir/TwelveHourBCDclock.sv\n%Error: data/full_repos/permissive/465389471/TLC_topModule_labsland.v:77: Cannot find file containing module: \'peak_offpeak\'\npeak_offpeak BCD_peak(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/465389471/TLC_topModule_labsland.v:83: Cannot find file containing module: \'TLC_main\'\nTLC_main Tlc_1(\n^~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module TLC_topModule_labsland(
    input CLOCK_50,
    input [5:0] SW,
    output [17:0] LEDR,
    output [2:0] LEDG,
    output [6:0] HEX0,                    
    output [6:0] HEX1,
    output [6:0] HEX2,
    output [6:0] HEX3,
    output [6:0] HEX4,
    output [6:0] HEX5,
    output [6:0] HEX6,
    output [6:0] HEX7
);

    wire reset,ena,sensor1,sensor2,peak1,reset1;
    wire [1:0] TL1,TL2,TL3,TL4,TL5,TL6;
    wire peak,pm,p,p1;
    wire [7:0] hh, mm, ss;
    wire [3:0] an;
    wire clk;
   
    localparam log2_slow_down_factor = 25;
    reg[24:0] counter = 0;
    assign clk = counter[24];
    always @(posedge CLOCK_50) counter = counter + 1;
    wire [7:0] timer;
    wire [11:0] timer_bcd;
    
  

    assign reset = ~SW[0];
    assign ena =   ~SW[1];
    assign sensor1 = SW[2];
    assign sensor2 = SW[3];
    assign peak = ~SW[4];
    assign peak1 = ~SW[5];
    assign an[0] = pm;
    

    assign LEDR[0] = (TL1 == 0)? 1:0;
    assign LEDR[1] = (TL1 == 1)? 1:0;
    assign LEDR[2] = (TL1 == 2)? 1:0;
    assign LEDR[3] = (TL2 == 0)? 1:0;
    assign LEDR[4] = (TL2 == 1)? 1:0;
    assign LEDR[5] = (TL2 == 2)? 1:0;
    assign LEDR[6] = (TL3 == 0)? 1:0;
    assign LEDR[7] = (TL3 == 1)? 1:0;
    assign LEDR[8] = (TL3 == 2)? 1:0;
    assign LEDR[9] = (TL4 == 0)? 1:0;
    assign LEDR[10] = (TL4 == 1)? 1:0;
    assign LEDR[11] = (TL4 == 2)? 1:0;
    assign LEDR[12] = (TL5 == 0)? 1:0;
    assign LEDR[13] = (TL5 == 1)? 1:0;
    assign LEDR[14] = (TL5 == 2)? 1:0;
    assign LEDR[15] = (TL6 == 0)? 1:0;
    assign LEDR[16] = (TL6 == 1)? 1:0;
    assign LEDR[17] = (TL6 == 2)? 1:0;

    assign LEDG[0] = an;
    assign LEDG[1] = (SW[4])? 0:1;
    assign LEDG[2] = (SW[5])? 0:1;

   


TwelveHourBCDclock BCD_clk(
    .clk(clk),
    .ena(ena),
    .reset(reset),
    .hh(hh),
    .mm(mm),
    .ss(ss),
    .pm(pm)
);

peak_offpeak BCD_peak(
    .hours(hh),
    .pm(pm),
    .peak1(peak1)
);

TLC_main Tlc_1(
    .clk(clk),
    .reset(reset),
    .sensor1(sensor1),
    .sensor2(sensor2),
    .TL1(TL1),
    .TL2(TL2),
    .TL3(TL3),
    .TL4(TL4),
    .TL5(TL5),
    .TL6(TL6),
    .peak(peak),
    .Timer(timer)
);

bin2bcd M1(
    .bin(timer),
    .bcd(timer_bcd)
);

sevenseg_driver timer1(
 .clk(clk), 
 .clr(1'b0), 
 .in1(hh[7:4]), 
 .in2(hh[3:0]), 
 .in3(mm[7:4]), 
 .in4(mm[3:0]),
 .in5(ss[7:4]),
 .in6(ss[3:0]),
 .seg1(HEX7), 
 .seg2(HEX6), 
 .seg3(HEX5), 
 .seg4(HEX4),
 .seg5(HEX3),
 .seg6(HEX2)
 );

sevenseg_driver1 timer2(
 .clk(clk), 
 .clr(1'b0), 
 .in5(timer_bcd[7:4]),
 .in6(timer_bcd[3:0]),
 .seg7(HEX1), 
 .seg8(HEX0)
 );




endmodule
module TLC_topModule_labsland(
    input CLOCK_50,
    input [5:0] SW,
    output [17:0] LEDR,
    output [2:0] LEDG,
    output [6:0] HEX0,                    
    output [6:0] HEX1,
    output [6:0] HEX2,
    output [6:0] HEX3,
    output [6:0] HEX4,
    output [6:0] HEX5,
    output [6:0] HEX6,
    output [6:0] HEX7
);


    wire reset,ena,sensor1,sensor2,peak1,reset1;
    wire [1:0] TL1,TL2,TL3,TL4,TL5,TL6;
    wire peak,pm,p,p1;
    wire [7:0] hh, mm, ss;
    wire [3:0] an;
    wire clk;
   
    localparam log2_slow_down_factor = 25;
    reg[24:0] counter = 0;
    assign clk = counter[24];
    always @(posedge CLOCK_50) counter = counter + 1;
    wire [7:0] timer;
    wire [11:0] timer_bcd;
    
  

    assign reset = ~SW[0];
    assign ena =   ~SW[1];
    assign sensor1 = SW[2];
    assign sensor2 = SW[3];
    assign peak = ~SW[4];
    assign peak1 = ~SW[5];
    assign an[0] = pm;
    

    assign LEDR[0] = (TL1 == 0)? 1:0;
    assign LEDR[1] = (TL1 == 1)? 1:0;
    assign LEDR[2] = (TL1 == 2)? 1:0;
    assign LEDR[3] = (TL2 == 0)? 1:0;
    assign LEDR[4] = (TL2 == 1)? 1:0;
    assign LEDR[5] = (TL2 == 2)? 1:0;
    assign LEDR[6] = (TL3 == 0)? 1:0;
    assign LEDR[7] = (TL3 == 1)? 1:0;
    assign LEDR[8] = (TL3 == 2)? 1:0;
    assign LEDR[9] = (TL4 == 0)? 1:0;
    assign LEDR[10] = (TL4 == 1)? 1:0;
    assign LEDR[11] = (TL4 == 2)? 1:0;
    assign LEDR[12] = (TL5 == 0)? 1:0;
    assign LEDR[13] = (TL5 == 1)? 1:0;
    assign LEDR[14] = (TL5 == 2)? 1:0;
    assign LEDR[15] = (TL6 == 0)? 1:0;
    assign LEDR[16] = (TL6 == 1)? 1:0;
    assign LEDR[17] = (TL6 == 2)? 1:0;

    assign LEDG[0] = an;
    assign LEDG[1] = (SW[4])? 0:1;
    assign LEDG[2] = (SW[5])? 0:1;

   


TwelveHourBCDclock BCD_clk(
    .clk(clk),
    .ena(ena),
    .reset(reset),
    .hh(hh),
    .mm(mm),
    .ss(ss),
    .pm(pm)
);

peak_offpeak BCD_peak(
    .hours(hh),
    .pm(pm),
    .peak1(peak1)
);

TLC_main Tlc_1(
    .clk(clk),
    .reset(reset),
    .sensor1(sensor1),
    .sensor2(sensor2),
    .TL1(TL1),
    .TL2(TL2),
    .TL3(TL3),
    .TL4(TL4),
    .TL5(TL5),
    .TL6(TL6),
    .peak(peak),
    .Timer(timer)
);

bin2bcd M1(
    .bin(timer),
    .bcd(timer_bcd)
);

sevenseg_driver timer1(
 .clk(clk), 
 .clr(1'b0), 
 .in1(hh[7:4]), 
 .in2(hh[3:0]), 
 .in3(mm[7:4]), 
 .in4(mm[3:0]),
 .in5(ss[7:4]),
 .in6(ss[3:0]),
 .seg1(HEX7), 
 .seg2(HEX6), 
 .seg3(HEX5), 
 .seg4(HEX4),
 .seg5(HEX3),
 .seg6(HEX2)
 );

sevenseg_driver1 timer2(
 .clk(clk), 
 .clr(1'b0), 
 .in5(timer_bcd[7:4]),
 .in6(timer_bcd[3:0]),
 .seg7(HEX1), 
 .seg8(HEX0)
 );




endmodule