data/full_repos/permissive/501470173/verilog/rtl/mem_video.v
1: b'%Warning-WIDTH: data/full_repos/permissive/501470173/verilog/rtl/mem_video.v:36: Bit extraction of array[2048:0] requires 12 bit index, not 11 bits.\n                                                                               : ... In instance mem_video\n    ram_video[addr_write] <= din;\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/501470173/verilog/rtl/mem_video.v:37: Bit extraction of array[2048:0] requires 12 bit index, not 11 bits.\n                                                                               : ... In instance mem_video\n   dout <= ram_video[addr_read];\n                    ^\n%Error: Exiting due to 2 warning(s)\n'
module mem_video(
    input clk,
	 input we,
    input [10:0] addr_write,
    input [10:0] addr_read,
    input [2:0] din,
    output reg [2:0] dout
    );

	reg [2:0] ram_video [2048:0];
	
	  
   always @(posedge clk) 
		begin
			if (we)
				ram_video[addr_write] <= din;
			dout <= ram_video[addr_read];
		end
		
endmodule
module mem_video(
    input clk,
	 input we,
    input [10:0] addr_write,
    input [10:0] addr_read,
    input [2:0] din,
    output reg [2:0] dout
    );


	reg [2:0] ram_video [2048:0];
	
	  
   always @(posedge clk) 
		begin
			if (we)
				ram_video[addr_write] <= din;
			dout <= ram_video[addr_read];
		end
		
endmodule