data/full_repos/permissive/446997925/hw4/AND_n_bit.v
data/verilator_xmls/26abf460-365b-4a12-a4ca-f3e0dc795185.xml
module AND_n_bit(AND_out, R2, R3);

parameter	word_size = 32;

input		[31:0]	R2, R3;
output	[31:0]	AND_out;

and AND1[31:0]	(AND_out, R2, R3);

endmodule
module AND_n_bit(AND_out, R2, R3);


parameter	word_size = 32;

input		[31:0]	R2, R3;
output	[31:0]	AND_out;

and AND1[31:0]	(AND_out, R2, R3);

endmodule