data/full_repos/permissive/408802108/Parts/AHB_Peripherals/ClockDivider/ClockDiv_XilinxS6.v
1: b"%Error: data/full_repos/permissive/408802108/Parts/AHB_Peripherals/ClockDivider/ClockDiv_XilinxS6.v:26: Cannot find file containing module: 'BUFIO2'\nBUFIO2 #\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/408802108/Parts/AHB_Peripherals/ClockDivider,data/full_repos/permissive/408802108/BUFIO2\n             data/full_repos/permissive/408802108/Parts/AHB_Peripherals/ClockDivider,data/full_repos/permissive/408802108/BUFIO2.v\n             data/full_repos/permissive/408802108/Parts/AHB_Peripherals/ClockDivider,data/full_repos/permissive/408802108/BUFIO2.sv\n             BUFIO2\n             BUFIO2.v\n             BUFIO2.sv\n             obj_dir/BUFIO2\n             obj_dir/BUFIO2.v\n             obj_dir/BUFIO2.sv\n%Error: data/full_repos/permissive/408802108/Parts/AHB_Peripherals/ClockDivider/ClockDiv_XilinxS6.v:37: Cannot find file containing module: 'BUFG'\nBUFG uBUFG(\n^~~~\n%Error: Exiting due to 2 error(s)\n"
module ClockDiv(

			input wire 	CLK_I,

			output wire CLK_O

    );




wire ck;

BUFIO2 #
	(	.DIVIDE(2),
		.DIVIDE_BYPASS(0)
	)
	uBUFIO2(
	.I				(CLK_I),
	.DIVCLK		(ck),
	.IOCLK		(),
	.SERDESSTROBE()
	);

BUFG uBUFG(
	.I(ck),
	.O(CLK_O)
	);


endmodule
module ClockDiv(

			input wire 	CLK_I,

			output wire CLK_O

    );





wire ck;

BUFIO2 #
	(	.DIVIDE(2),
		.DIVIDE_BYPASS(0)
	)
	uBUFIO2(
	.I				(CLK_I),
	.DIVCLK		(ck),
	.IOCLK		(),
	.SERDESSTROBE()
	);

BUFG uBUFG(
	.I(ck),
	.O(CLK_O)
	);


endmodule