data/full_repos/permissive/455421905/src/even_odd.v
1: b"%Error: data/full_repos/permissive/455421905/src/even_odd.v:80: Cannot find file containing module: 'COMPARATOR'\n  COMPARATOR #(FLOAT, SIGNED, KEYW)\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/COMPARATOR\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/COMPARATOR.v\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/COMPARATOR.sv\n             COMPARATOR\n             COMPARATOR.v\n             COMPARATOR.sv\n             obj_dir/COMPARATOR\n             obj_dir/COMPARATOR.v\n             obj_dir/COMPARATOR.sv\n%Error: Exiting due to 1 error(s)\n"
module BOX #(parameter                       P_LOG  = 4,
             parameter                       FLOAT  = "no",
             parameter                       SIGNED = "no",
             parameter                       DATW   = 64,
             parameter                       KEYW   = 32)
            (input  wire                     CLK,
             input  wire [(DATW<<P_LOG)-1:0] DIN,
             output wire [(DATW<<P_LOG)-1:0] DOT);

  localparam PAYW = DATW - KEYW;

  genvar i, j, k;
  generate
    if (PAYW == 0) begin
      reg [(DATW<<P_LOG)-1:0] pd [P_LOG-1:0];
      for (i=0; i<P_LOG; i=i+1) begin: stage
        wire [(DATW<<P_LOG)-1:0] dot;
        if (i == 0) begin
          for (j=0; j<(1<<(P_LOG-1)); j=j+1) begin: caes
            CAE #(FLOAT, SIGNED, DATW, KEYW) cae(CLK,
                                                 DIN[DATW*(j+1)-1:DATW*j],
                                                 DIN[DATW*((j+1)+(1<<(P_LOG-1)))-1:DATW*(j+(1<<(P_LOG-1)))],
                                                 dot[DATW*(j+1)-1:DATW*j],
                                                 dot[DATW*((j+1)+(1<<(P_LOG-1)))-1:DATW*(j+(1<<(P_LOG-1)))]);
          end
          always @(posedge CLK) pd[i] <= dot;
        end else begin
          for (k=0; k<((1<<i)-1); k=k+1) begin: blocks
            for (j=0; j<(1<<(P_LOG-(i+1))); j=j+1) begin: caes
              CAE #(FLOAT, SIGNED, DATW, KEYW) cae(CLK,
                                                   pd[i-1][DATW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))-1:DATW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))],
                                                   pd[i-1][DATW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))-1:DATW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))],
                                                   dot[DATW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))-1:DATW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))],
                                                   dot[DATW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))-1:DATW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))]);
            end
          end
          reg [DATW*(1<<(P_LOG-(i+1)))-1:0] pd_upper_buf;
          reg [DATW*(1<<(P_LOG-(i+1)))-1:0] pd_lower_buf;
          always @(posedge CLK) pd_upper_buf <= pd[i-1][(DATW<<P_LOG)-1:DATW*((1<<P_LOG)-(1<<(P_LOG-(i+1))))];
          always @(posedge CLK) pd_lower_buf <= pd[i-1][DATW*(1<<(P_LOG-(i+1)))-1:0];
          always @(posedge CLK) pd[i] <= {pd_upper_buf,
                                          dot[DATW*((1<<P_LOG)-(1<<(P_LOG-(i+1))))-1:DATW*(1<<(P_LOG-(i+1)))],
                                          pd_lower_buf};
        end
      end
      assign DOT = pd[P_LOG-1];
    end else begin

      wire [(KEYW<<P_LOG)-1:0] i_key;
      wire [(PAYW<<P_LOG)-1:0] i_payload;
      for (i=0; i<(1<<P_LOG); i=i+1) begin: set_i_data
        assign i_key[KEYW*(i+1)-1:KEYW*i] = DIN[(KEYW+DATW*i)-1:DATW*i];
        assign i_payload[PAYW*(i+1)-1:PAYW*i] = DIN[DATW*(i+1)-1:(KEYW+DATW*i)];
      end

      reg [(KEYW<<P_LOG)-1:0] k_preg [P_LOG-1:0];
      reg [(PAYW<<P_LOG)-1:0] p_preg [P_LOG-1:0];
      integer p;
      reg [(PAYW<<P_LOG)-1:0] p_sreg [P_LOG-1:0];
      always @(posedge CLK) begin
        p_sreg[0] <= i_payload;
        for (p=1; p<P_LOG; p=p+1) begin
          p_sreg[p] <= p_sreg[p-1];
        end
      end
      for (i=0; i<P_LOG; i=i+1) begin: stage
        wire [(KEYW<<P_LOG)-1:0] o_key;
        wire [(PAYW<<P_LOG)-1:0] o_payload;
        if (i == 0) begin

          for (j=0; j<(1<<(P_LOG-1)); j=j+1) begin: k_caes
            wire o_cmp;
            wire i_cmp;
            K_CAE #(FLOAT, SIGNED, KEYW) k_cae(CLK,
                                               i_key[KEYW*(j+1)-1:KEYW*j],
                                               i_key[KEYW*((j+1)+(1<<(P_LOG-1)))-1:KEYW*(j+(1<<(P_LOG-1)))],
                                               o_key[KEYW*(j+1)-1:KEYW*j],
                                               o_key[KEYW*((j+1)+(1<<(P_LOG-1)))-1:KEYW*(j+(1<<(P_LOG-1)))],
                                               o_cmp);
            if (P_LOG-(i+1) == 0) begin
              assign i_cmp = o_cmp;
            end else begin
              reg [(P_LOG-(i+1))-1:0] cmp_buf;
              always @(posedge CLK) begin
                cmp_buf[0] <= o_cmp;
                for (p=1; p<(P_LOG-(i+1)); p=p+1) begin
                  cmp_buf[p] <= cmp_buf[p-1];
                end
              end
              assign i_cmp = cmp_buf[(P_LOG-(i+1))-1];
            end
          end
          always @(posedge CLK) k_preg[i] <= o_key;

          for (j=0; j<(1<<(P_LOG-1)); j=j+1) begin: p_exchanges
            P_EXCHANGE #(PAYW) p_exchange(k_caes[j].i_cmp,
                                          p_sreg[P_LOG-1][PAYW*(j+1)-1:PAYW*j],
                                          p_sreg[P_LOG-1][PAYW*((j+1)+(1<<(P_LOG-1)))-1:PAYW*(j+(1<<(P_LOG-1)))],
                                          o_payload[PAYW*(j+1)-1:PAYW*j],
                                          o_payload[PAYW*((j+1)+(1<<(P_LOG-1)))-1:PAYW*(j+(1<<(P_LOG-1)))]);
          end
          always @(posedge CLK) p_preg[i] <= o_payload;
        end else begin

          for (k=0; k<((1<<i)-1); k=k+1) begin: k_blocks
            for (j=0; j<(1<<(P_LOG-(i+1))); j=j+1) begin: k_caes
              wire o_cmp;
              wire i_cmp;
              K_CAE #(FLOAT, SIGNED, KEYW) k_cae(CLK,
                                                 k_preg[i-1][KEYW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))-1:KEYW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))],
                                                 k_preg[i-1][KEYW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))-1:KEYW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))],
                                                 o_key[KEYW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))-1:KEYW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))],
                                                 o_key[KEYW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))-1:KEYW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))],
                                                 o_cmp);
              if (P_LOG-(i+1) == 0) begin
                assign i_cmp = o_cmp;
              end else begin
                reg [(P_LOG-(i+1))-1:0] cmp_buf;
                always @(posedge CLK) begin
                  cmp_buf[0] <= o_cmp;
                  for (p=1; p<(P_LOG-(i+1)); p=p+1) begin
                    cmp_buf[p] <= cmp_buf[p-1];
                  end
                end
                assign i_cmp = cmp_buf[(P_LOG-(i+1))-1];
              end
            end
          end
          reg [KEYW*(1<<(P_LOG-(i+1)))-1:0] k_preg_upper_buf;
          reg [KEYW*(1<<(P_LOG-(i+1)))-1:0] k_preg_lower_buf;
          always @(posedge CLK) k_preg_upper_buf <= k_preg[i-1][(KEYW<<P_LOG)-1:KEYW*((1<<P_LOG)-(1<<(P_LOG-(i+1))))];
          always @(posedge CLK) k_preg_lower_buf <= k_preg[i-1][KEYW*(1<<(P_LOG-(i+1)))-1:0];
          always @(posedge CLK) k_preg[i] <= {k_preg_upper_buf,
                                              o_key[KEYW*((1<<P_LOG)-(1<<(P_LOG-(i+1))))-1:KEYW*(1<<(P_LOG-(i+1)))],
                                              k_preg_lower_buf};

          for (k=0; k<((1<<i)-1); k=k+1) begin: p_blocks
            for (j=0; j<(1<<(P_LOG-(i+1))); j=j+1) begin: p_exchanges
              P_EXCHANGE #(PAYW) p_exchange(k_blocks[k].k_caes[j].i_cmp,
                                            p_preg[i-1][PAYW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))-1:PAYW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))],
                                            p_preg[i-1][PAYW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))-1:PAYW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))],
                                            o_payload[PAYW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))-1:PAYW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))],
                                            o_payload[PAYW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))-1:PAYW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))]);
            end
          end
          always @(posedge CLK) p_preg[i] <= {p_preg[i-1][(PAYW<<P_LOG)-1:PAYW*((1<<P_LOG)-(1<<(P_LOG-(i+1))))],
                                              o_payload[PAYW*((1<<P_LOG)-(1<<(P_LOG-(i+1))))-1:PAYW*(1<<(P_LOG-(i+1)))],
                                              p_preg[i-1][PAYW*(1<<(P_LOG-(i+1)))-1:0]};
        end
      end

      for (i=0; i<(1<<P_LOG); i=i+1) begin: set_o_data
        assign DOT[DATW*(i+1)-1:DATW*i] = {p_preg[P_LOG-1][PAYW*(i+1)-1:PAYW*i], k_preg[P_LOG-1][KEYW*(i+1)-1:KEYW*i]};
      end
    end
  endgenerate

endmodule
module BOX #(parameter                       P_LOG  = 4,
             parameter                       FLOAT  = "no",
             parameter                       SIGNED = "no",
             parameter                       DATW   = 64,
             parameter                       KEYW   = 32)
            (input  wire                     CLK,
             input  wire [(DATW<<P_LOG)-1:0] DIN,
             output wire [(DATW<<P_LOG)-1:0] DOT);


  localparam PAYW = DATW - KEYW;

  genvar i, j, k;
  generate
    if (PAYW == 0) begin
      reg [(DATW<<P_LOG)-1:0] pd [P_LOG-1:0];
      for (i=0; i<P_LOG; i=i+1) begin: stage
        wire [(DATW<<P_LOG)-1:0] dot;
        if (i == 0) begin
          for (j=0; j<(1<<(P_LOG-1)); j=j+1) begin: caes
            CAE #(FLOAT, SIGNED, DATW, KEYW) cae(CLK,
                                                 DIN[DATW*(j+1)-1:DATW*j],
                                                 DIN[DATW*((j+1)+(1<<(P_LOG-1)))-1:DATW*(j+(1<<(P_LOG-1)))],
                                                 dot[DATW*(j+1)-1:DATW*j],
                                                 dot[DATW*((j+1)+(1<<(P_LOG-1)))-1:DATW*(j+(1<<(P_LOG-1)))]);
          end
          always @(posedge CLK) pd[i] <= dot;
        end else begin
          for (k=0; k<((1<<i)-1); k=k+1) begin: blocks
            for (j=0; j<(1<<(P_LOG-(i+1))); j=j+1) begin: caes
              CAE #(FLOAT, SIGNED, DATW, KEYW) cae(CLK,
                                                   pd[i-1][DATW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))-1:DATW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))],
                                                   pd[i-1][DATW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))-1:DATW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))],
                                                   dot[DATW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))-1:DATW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))],
                                                   dot[DATW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))-1:DATW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))]);
            end
          end
          reg [DATW*(1<<(P_LOG-(i+1)))-1:0] pd_upper_buf;
          reg [DATW*(1<<(P_LOG-(i+1)))-1:0] pd_lower_buf;
          always @(posedge CLK) pd_upper_buf <= pd[i-1][(DATW<<P_LOG)-1:DATW*((1<<P_LOG)-(1<<(P_LOG-(i+1))))];
          always @(posedge CLK) pd_lower_buf <= pd[i-1][DATW*(1<<(P_LOG-(i+1)))-1:0];
          always @(posedge CLK) pd[i] <= {pd_upper_buf,
                                          dot[DATW*((1<<P_LOG)-(1<<(P_LOG-(i+1))))-1:DATW*(1<<(P_LOG-(i+1)))],
                                          pd_lower_buf};
        end
      end
      assign DOT = pd[P_LOG-1];
    end else begin

      wire [(KEYW<<P_LOG)-1:0] i_key;
      wire [(PAYW<<P_LOG)-1:0] i_payload;
      for (i=0; i<(1<<P_LOG); i=i+1) begin: set_i_data
        assign i_key[KEYW*(i+1)-1:KEYW*i] = DIN[(KEYW+DATW*i)-1:DATW*i];
        assign i_payload[PAYW*(i+1)-1:PAYW*i] = DIN[DATW*(i+1)-1:(KEYW+DATW*i)];
      end

      reg [(KEYW<<P_LOG)-1:0] k_preg [P_LOG-1:0];
      reg [(PAYW<<P_LOG)-1:0] p_preg [P_LOG-1:0];
      integer p;
      reg [(PAYW<<P_LOG)-1:0] p_sreg [P_LOG-1:0];
      always @(posedge CLK) begin
        p_sreg[0] <= i_payload;
        for (p=1; p<P_LOG; p=p+1) begin
          p_sreg[p] <= p_sreg[p-1];
        end
      end
      for (i=0; i<P_LOG; i=i+1) begin: stage
        wire [(KEYW<<P_LOG)-1:0] o_key;
        wire [(PAYW<<P_LOG)-1:0] o_payload;
        if (i == 0) begin

          for (j=0; j<(1<<(P_LOG-1)); j=j+1) begin: k_caes
            wire o_cmp;
            wire i_cmp;
            K_CAE #(FLOAT, SIGNED, KEYW) k_cae(CLK,
                                               i_key[KEYW*(j+1)-1:KEYW*j],
                                               i_key[KEYW*((j+1)+(1<<(P_LOG-1)))-1:KEYW*(j+(1<<(P_LOG-1)))],
                                               o_key[KEYW*(j+1)-1:KEYW*j],
                                               o_key[KEYW*((j+1)+(1<<(P_LOG-1)))-1:KEYW*(j+(1<<(P_LOG-1)))],
                                               o_cmp);
            if (P_LOG-(i+1) == 0) begin
              assign i_cmp = o_cmp;
            end else begin
              reg [(P_LOG-(i+1))-1:0] cmp_buf;
              always @(posedge CLK) begin
                cmp_buf[0] <= o_cmp;
                for (p=1; p<(P_LOG-(i+1)); p=p+1) begin
                  cmp_buf[p] <= cmp_buf[p-1];
                end
              end
              assign i_cmp = cmp_buf[(P_LOG-(i+1))-1];
            end
          end
          always @(posedge CLK) k_preg[i] <= o_key;

          for (j=0; j<(1<<(P_LOG-1)); j=j+1) begin: p_exchanges
            P_EXCHANGE #(PAYW) p_exchange(k_caes[j].i_cmp,
                                          p_sreg[P_LOG-1][PAYW*(j+1)-1:PAYW*j],
                                          p_sreg[P_LOG-1][PAYW*((j+1)+(1<<(P_LOG-1)))-1:PAYW*(j+(1<<(P_LOG-1)))],
                                          o_payload[PAYW*(j+1)-1:PAYW*j],
                                          o_payload[PAYW*((j+1)+(1<<(P_LOG-1)))-1:PAYW*(j+(1<<(P_LOG-1)))]);
          end
          always @(posedge CLK) p_preg[i] <= o_payload;
        end else begin

          for (k=0; k<((1<<i)-1); k=k+1) begin: k_blocks
            for (j=0; j<(1<<(P_LOG-(i+1))); j=j+1) begin: k_caes
              wire o_cmp;
              wire i_cmp;
              K_CAE #(FLOAT, SIGNED, KEYW) k_cae(CLK,
                                                 k_preg[i-1][KEYW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))-1:KEYW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))],
                                                 k_preg[i-1][KEYW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))-1:KEYW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))],
                                                 o_key[KEYW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))-1:KEYW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))],
                                                 o_key[KEYW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))-1:KEYW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))],
                                                 o_cmp);
              if (P_LOG-(i+1) == 0) begin
                assign i_cmp = o_cmp;
              end else begin
                reg [(P_LOG-(i+1))-1:0] cmp_buf;
                always @(posedge CLK) begin
                  cmp_buf[0] <= o_cmp;
                  for (p=1; p<(P_LOG-(i+1)); p=p+1) begin
                    cmp_buf[p] <= cmp_buf[p-1];
                  end
                end
                assign i_cmp = cmp_buf[(P_LOG-(i+1))-1];
              end
            end
          end
          reg [KEYW*(1<<(P_LOG-(i+1)))-1:0] k_preg_upper_buf;
          reg [KEYW*(1<<(P_LOG-(i+1)))-1:0] k_preg_lower_buf;
          always @(posedge CLK) k_preg_upper_buf <= k_preg[i-1][(KEYW<<P_LOG)-1:KEYW*((1<<P_LOG)-(1<<(P_LOG-(i+1))))];
          always @(posedge CLK) k_preg_lower_buf <= k_preg[i-1][KEYW*(1<<(P_LOG-(i+1)))-1:0];
          always @(posedge CLK) k_preg[i] <= {k_preg_upper_buf,
                                              o_key[KEYW*((1<<P_LOG)-(1<<(P_LOG-(i+1))))-1:KEYW*(1<<(P_LOG-(i+1)))],
                                              k_preg_lower_buf};

          for (k=0; k<((1<<i)-1); k=k+1) begin: p_blocks
            for (j=0; j<(1<<(P_LOG-(i+1))); j=j+1) begin: p_exchanges
              P_EXCHANGE #(PAYW) p_exchange(k_blocks[k].k_caes[j].i_cmp,
                                            p_preg[i-1][PAYW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))-1:PAYW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))],
                                            p_preg[i-1][PAYW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))-1:PAYW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))],
                                            o_payload[PAYW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))-1:PAYW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1))))],
                                            o_payload[PAYW*((j+1)+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))-1:PAYW*(j+(k*(1<<(P_LOG-i)))+(1<<(P_LOG-(i+1)))+(1<<(P_LOG-(i+1))))]);
            end
          end
          always @(posedge CLK) p_preg[i] <= {p_preg[i-1][(PAYW<<P_LOG)-1:PAYW*((1<<P_LOG)-(1<<(P_LOG-(i+1))))],
                                              o_payload[PAYW*((1<<P_LOG)-(1<<(P_LOG-(i+1))))-1:PAYW*(1<<(P_LOG-(i+1)))],
                                              p_preg[i-1][PAYW*(1<<(P_LOG-(i+1)))-1:0]};
        end
      end

      for (i=0; i<(1<<P_LOG); i=i+1) begin: set_o_data
        assign DOT[DATW*(i+1)-1:DATW*i] = {p_preg[P_LOG-1][PAYW*(i+1)-1:PAYW*i], k_preg[P_LOG-1][KEYW*(i+1)-1:KEYW*i]};
      end
    end
  endgenerate

endmodule