data/full_repos/permissive/494696040/data_memory.v
data/verilator_xmls/d6525bb2-d95f-404a-ab98-aeb4295df9c4.xml
module data_memory(
    input [31:0] address,
    input [31:0] write_data,
    input mem_write,
    input mem_read,
    input CLK,
    output reg [31:0] read_data
    );
    

    reg [31:0] memory[0:63];
    

    always @(mem_read or address)
    begin

        if(mem_read) read_data <= memory[address >> 2];
    end

    always @(posedge CLK)
    begin
        if (mem_write == 1'b1) memory[address >> 2] <= write_data;
    end
    


    initial begin
        memory[0] <= 32'd0;
        memory[1] <= 32'd12;
        memory[2] <= 32'd327;
        
        memory[4] <= 32'd100;
        memory[5] <= 32'd47583;
        memory[6] <= 32'd125543;
    end

endmodule
module data_memory(
    input [31:0] address,
    input [31:0] write_data,
    input mem_write,
    input mem_read,
    input CLK,
    output reg [31:0] read_data
    );

    

    reg [31:0] memory[0:63];
    

    always @(mem_read or address)
    begin

        if(mem_read) read_data <= memory[address >> 2];
    end

    always @(posedge CLK)
    begin
        if (mem_write == 1'b1) memory[address >> 2] <= write_data;
    end
    


    initial begin
        memory[0] <= 32'd0;
        memory[1] <= 32'd12;
        memory[2] <= 32'd327;
        
        memory[4] <= 32'd100;
        memory[5] <= 32'd47583;
        memory[6] <= 32'd125543;
    end

endmodule