data/full_repos/permissive/406635962/src/rtl/lsu.v
1: b'%Error: data/full_repos/permissive/406635962/src/rtl/lsu.v:6: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu.v:12: Define or directive not defined: \'`XLEN\'\n    output [`XLEN-1:0] lsu_o_wbck_data,\n            ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu.v:13: Define or directive not defined: \'`ITAG_WIDTH\'\n    output [`ITAG_WIDTH-1:0] lsu_o_wbck_itag,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu.v:18: Define or directive not defined: \'`DTCM_ADDR_WIDTH\'\n    input [`DTCM_ADDR_WIDTH-1:0] agu_cmd_addr,\n           ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu.v:19: Define or directive not defined: \'`XLEN\'\n    input [`XLEN-1:0] agu_cmd_wdata,\n           ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu.v:20: Define or directive not defined: \'`XLEN\'\n    input [`XLEN/8-1:0] agu_cmd_wmask,\n           ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu.v:20: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n    input [`XLEN/8-1:0] agu_cmd_wmask,\n                ^\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu.v:21: Define or directive not defined: \'`ITAG_WIDTH\'\n    input [`ITAG_WIDTH-1:0] agu_cmd_itag,\n           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu.v:31: Define or directive not defined: \'`DTCM_ADDR_WIDTH\'\n    output [`DTCM_ADDR_WIDTH-1:0] dtcm_cmd_addr,\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu.v:32: Define or directive not defined: \'`XLEN\'\n    output [`XLEN-1:0] dtcm_cmd_wdata,\n            ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu.v:33: Define or directive not defined: \'`XLEN\'\n    output [`XLEN/8-1:0] dtcm_cmd_wmask,\n            ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu.v:36: Define or directive not defined: \'`XLEN\'\n    input [`XLEN-1:0] dtcm_rsp_rdata,\n           ^~~~~\n%Error: Exiting due to 12 error(s)\n'
module lsu (

    output lsu_o_valid,
    input lsu_o_ready,
    output [`XLEN-1:0] lsu_o_wbck_data,
    output [`ITAG_WIDTH-1:0] lsu_o_wbck_itag,

    input agu_cmd_valid,
    output agu_cmd_ready,
    input agu_cmd_read,
    input [`DTCM_ADDR_WIDTH-1:0] agu_cmd_addr,
    input [`XLEN-1:0] agu_cmd_wdata,
    input [`XLEN/8-1:0] agu_cmd_wmask,
    input [`ITAG_WIDTH-1:0] agu_cmd_itag,
    input agu_cmd_usign,
    input [1:0] agu_cmd_size,
    output agu_rsp_valid,
    input agu_rsp_ready,


    output dtcm_cmd_valid,
    input dtcm_cmd_ready,
    output dtcm_cmd_read,
    output [`DTCM_ADDR_WIDTH-1:0] dtcm_cmd_addr,
    output [`XLEN-1:0] dtcm_cmd_wdata,
    output [`XLEN/8-1:0] dtcm_cmd_wmask,
    input dtcm_rsp_valid,
    output dtcm_rsp_ready,
    input [`XLEN-1:0] dtcm_rsp_rdata,
    
    input clk,
    input rst_n
);

lsu_ctrl u_lsu_ctrl (
    .lsu_o_valid(lsu_o_valid),
    .lsu_o_ready(lsu_o_ready),
    .lsu_o_wbck_data(lsu_o_wbck_data),
    .lsu_o_wbck_itag(lsu_o_wbck_itag),
    .agu_cmd_valid(agu_cmd_valid),
    .agu_cmd_ready(agu_cmd_ready),
    .agu_cmd_read(agu_cmd_read),
    .agu_cmd_addr(agu_cmd_addr),
    .agu_cmd_wdata(agu_cmd_wdata),
    .agu_cmd_wmask(agu_cmd_wmask),
    .agu_cmd_itag(agu_cmd_itag),
     .agu_cmd_usign(agu_cmd_usign),
    .agu_cmd_size(agu_cmd_size),
    .agu_rsp_valid(agu_rsp_valid),
    .agu_rsp_ready(agu_rsp_ready),
    .dtcm_cmd_valid(dtcm_cmd_valid),
    .dtcm_cmd_ready(dtcm_cmd_ready),
    .dtcm_cmd_read(dtcm_cmd_read),
    .dtcm_cmd_addr(dtcm_cmd_addr),
    .dtcm_cmd_wdata(dtcm_cmd_wdata),
    .dtcm_cmd_wmask(dtcm_cmd_wmask),
    .dtcm_rsp_valid(dtcm_rsp_valid),
    .dtcm_rsp_ready(dtcm_rsp_ready),
    .dtcm_rsp_rdata(dtcm_rsp_rdata),
    .clk(clk),
    .rst_n(rst_n)
);
    
endmodule
module lsu (

    output lsu_o_valid,
    input lsu_o_ready,
    output [`XLEN-1:0] lsu_o_wbck_data,
    output [`ITAG_WIDTH-1:0] lsu_o_wbck_itag,

    input agu_cmd_valid,
    output agu_cmd_ready,
    input agu_cmd_read,
    input [`DTCM_ADDR_WIDTH-1:0] agu_cmd_addr,
    input [`XLEN-1:0] agu_cmd_wdata,
    input [`XLEN/8-1:0] agu_cmd_wmask,
    input [`ITAG_WIDTH-1:0] agu_cmd_itag,
    input agu_cmd_usign,
    input [1:0] agu_cmd_size,
    output agu_rsp_valid,
    input agu_rsp_ready,


    output dtcm_cmd_valid,
    input dtcm_cmd_ready,
    output dtcm_cmd_read,
    output [`DTCM_ADDR_WIDTH-1:0] dtcm_cmd_addr,
    output [`XLEN-1:0] dtcm_cmd_wdata,
    output [`XLEN/8-1:0] dtcm_cmd_wmask,
    input dtcm_rsp_valid,
    output dtcm_rsp_ready,
    input [`XLEN-1:0] dtcm_rsp_rdata,
    
    input clk,
    input rst_n
);


lsu_ctrl u_lsu_ctrl (
    .lsu_o_valid(lsu_o_valid),
    .lsu_o_ready(lsu_o_ready),
    .lsu_o_wbck_data(lsu_o_wbck_data),
    .lsu_o_wbck_itag(lsu_o_wbck_itag),
    .agu_cmd_valid(agu_cmd_valid),
    .agu_cmd_ready(agu_cmd_ready),
    .agu_cmd_read(agu_cmd_read),
    .agu_cmd_addr(agu_cmd_addr),
    .agu_cmd_wdata(agu_cmd_wdata),
    .agu_cmd_wmask(agu_cmd_wmask),
    .agu_cmd_itag(agu_cmd_itag),
     .agu_cmd_usign(agu_cmd_usign),
    .agu_cmd_size(agu_cmd_size),
    .agu_rsp_valid(agu_rsp_valid),
    .agu_rsp_ready(agu_rsp_ready),
    .dtcm_cmd_valid(dtcm_cmd_valid),
    .dtcm_cmd_ready(dtcm_cmd_ready),
    .dtcm_cmd_read(dtcm_cmd_read),
    .dtcm_cmd_addr(dtcm_cmd_addr),
    .dtcm_cmd_wdata(dtcm_cmd_wdata),
    .dtcm_cmd_wmask(dtcm_cmd_wmask),
    .dtcm_rsp_valid(dtcm_rsp_valid),
    .dtcm_rsp_ready(dtcm_rsp_ready),
    .dtcm_rsp_rdata(dtcm_rsp_rdata),
    .clk(clk),
    .rst_n(rst_n)
);
    
endmodule