data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/OFFSET_ADDER.v
data/verilator_xmls/f16d422e-2ade-4769-a854-f12f8aca8113.xml
module OFFSET_ADDER #(parameter BITWIDTH=10)(


OFFSET_ADDER_clk,
OFFSET_ADDER_Sum_En,
OFFSET_ADDER_Reset,
OFFSET_ADDER_offset,


OFFSET_ADDER_Lower_Limit
);




input OFFSET_ADDER_clk;
input OFFSET_ADDER_Sum_En;
input OFFSET_ADDER_Reset;
input [BITWIDTH-1:0] OFFSET_ADDER_offset;
output [BITWIDTH-1:0] OFFSET_ADDER_Lower_Limit;




reg [BITWIDTH-1:0] Reg_Lower_Limit;


always @(posedge OFFSET_ADDER_clk or negedge OFFSET_ADDER_Reset)
begin

	if(!OFFSET_ADDER_Reset)
		Reg_Lower_Limit<=0;
		
	else if(OFFSET_ADDER_Sum_En)
		Reg_Lower_Limit<=Reg_Lower_Limit+OFFSET_ADDER_offset+1'b1;
end




assign OFFSET_ADDER_Lower_Limit=Reg_Lower_Limit;

endmodule
module OFFSET_ADDER #(parameter BITWIDTH=10)(


OFFSET_ADDER_clk,
OFFSET_ADDER_Sum_En,
OFFSET_ADDER_Reset,
OFFSET_ADDER_offset,


OFFSET_ADDER_Lower_Limit
);





input OFFSET_ADDER_clk;
input OFFSET_ADDER_Sum_En;
input OFFSET_ADDER_Reset;
input [BITWIDTH-1:0] OFFSET_ADDER_offset;
output [BITWIDTH-1:0] OFFSET_ADDER_Lower_Limit;




reg [BITWIDTH-1:0] Reg_Lower_Limit;


always @(posedge OFFSET_ADDER_clk or negedge OFFSET_ADDER_Reset)
begin

	if(!OFFSET_ADDER_Reset)
		Reg_Lower_Limit<=0;
		
	else if(OFFSET_ADDER_Sum_En)
		Reg_Lower_Limit<=Reg_Lower_Limit+OFFSET_ADDER_offset+1'b1;
end




assign OFFSET_ADDER_Lower_Limit=Reg_Lower_Limit;

endmodule