data/full_repos/permissive/487455827/cpu/rtl/perips/plic.v
1: b'%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/plic.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/487455827/cpu/rtl/perips,data/full_repos/permissive/487455827/defines.v\n             data/full_repos/permissive/487455827/cpu/rtl/perips,data/full_repos/permissive/487455827/defines.v.v\n             data/full_repos/permissive/487455827/cpu/rtl/perips,data/full_repos/permissive/487455827/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/plic.v:22: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] csr_mie,\n            ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/plic.v:22: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`RegBus] csr_mie,\n                   ^\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/plic.v:23: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus] csr_mstatus\n            ^~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/plic.v:35: syntax error, unexpected priority, expecting IDENTIFIER or \'=\' or do or final\n reg[31:0] priority[0:6];\n           ^~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/plic.v:42: syntax error, unexpected always\n    always @(posedge wb_clk_i) begin\n    ^~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/plic.v:45: Define or directive not defined: \'`ZeroWord\'\n    wb_dat_o <= `ZeroWord;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/plic.v:53: Define or directive not defined: \'`PLIC_BASE\'\n     if((wb_adr_i >= `PLIC_BASE) && (wb_adr_i <= `PLIC_BASE + irq_max * 4)) begin\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/plic.v:53: Define or directive not defined: \'`PLIC_BASE\'\n     if((wb_adr_i >= `PLIC_BASE) && (wb_adr_i <= `PLIC_BASE + irq_max * 4)) begin\n                                                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/plic.v:54: Define or directive not defined: \'`PLIC_BASE\'\n      priority[(wb_adr_i - `PLIC_BASE)/4] <= wb_dat_i;\n                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/plic.v:55: Define or directive not defined: \'`PLIC_BASE\'\n     end else if(wb_adr_i == `PLIC_BASE + 32\'h2000) begin\n                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/plic.v:57: Define or directive not defined: \'`PLIC_BASE\'\n     end else if(wb_adr_i == `PLIC_BASE + 32\'h200000) begin\n                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/plic.v:59: Define or directive not defined: \'`PLIC_BASE\'\n     end else if(wb_adr_i == `PLIC_BASE + 32\'h200004) begin\n                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/plic.v:63: Define or directive not defined: \'`PLIC_BASE\'\n     if((wb_adr_i >= `PLIC_BASE) && (wb_adr_i <= `PLIC_BASE + irq_max * 4)) begin\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/plic.v:63: Define or directive not defined: \'`PLIC_BASE\'\n     if((wb_adr_i >= `PLIC_BASE) && (wb_adr_i <= `PLIC_BASE + irq_max * 4)) begin\n                                                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/plic.v:64: Define or directive not defined: \'`PLIC_BASE\'\n      wb_dat_o <= priority[(wb_adr_i - `PLIC_BASE)/4];\n                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/plic.v:65: Define or directive not defined: \'`PLIC_BASE\'\n     end else if(wb_adr_i == `PLIC_BASE + 32\'h2000) begin\n                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/plic.v:67: Define or directive not defined: \'`PLIC_BASE\'\n     end else if(wb_adr_i == `PLIC_BASE + 32\'h200000) begin\n                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/plic.v:69: Define or directive not defined: \'`PLIC_BASE\'\n     end else if(wb_adr_i == `PLIC_BASE + 32\'h200004) begin\n                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/487455827/cpu/rtl/perips/plic.v:81: Define or directive not defined: \'`ZeroWord\'\n   irq = `ZeroWord;\n         ^~~~~~~~~\n%Error: Exiting due to 20 error(s)\n'
module plic(
	input  wire 	wb_clk_i,
	input  wire   	wb_rst_i,
	input  wire   	[31:0] wb_adr_i,
	output reg 		[31:0] wb_dat_o,
	input  wire   	[31:0] wb_dat_i,
	input  wire   	[3:0] wb_sel_i,
	input  wire   	wb_we_i,
	input  wire   	wb_stb_i,
	input  wire   	wb_cyc_i,
	output reg 		wb_ack_o,

	input wire uart_int,
	input wire gpio_int,

	output reg Interrupt,
	output reg [30:0] Exception_code,
	

	input wire[`RegBus]	csr_mie,
	input wire[`RegBus]	csr_mstatus
);

    parameter aw = 32;
    parameter dw = 32;
	 parameter irq_max = 6;


    wire wb_acc = wb_cyc_i & wb_stb_i;
    wire wb_wr  = wb_acc & wb_we_i;
    wire wb_rd  = wb_acc & !wb_we_i;

	reg[31:0] priority[0:6];
	reg[31:0] pending;
	reg[31:0] enable;
	reg[31:0] threshold;
	reg[31:0] irq;
	reg complete;
	
    always @(posedge wb_clk_i) begin
        if( wb_rst_i == 1'b1 ) begin
            wb_ack_o <= 1'b0;
				wb_dat_o <= `ZeroWord;
				enable <= 32'h00000000;
        end else if(wb_acc == 1'b0) begin
            wb_ack_o <= 1'b0;
				complete <= 1'b0;

        end else if(wb_acc == 1'b1) begin
				if(wb_wr == 1'b1) begin
					if((wb_adr_i >= `PLIC_BASE) && (wb_adr_i <= `PLIC_BASE + irq_max * 4)) begin
						priority[(wb_adr_i - `PLIC_BASE)/4] <= wb_dat_i;
					end else if(wb_adr_i == `PLIC_BASE + 32'h2000) begin
						enable <= wb_dat_i;
					end else if(wb_adr_i == `PLIC_BASE + 32'h200000) begin
						threshold <= wb_dat_i;
					end else if(wb_adr_i == `PLIC_BASE + 32'h200004) begin
						complete <= 1'b1;
					end
				end else if(wb_rd == 1'b1) begin
					if((wb_adr_i >= `PLIC_BASE) && (wb_adr_i <= `PLIC_BASE + irq_max * 4)) begin
						wb_dat_o <= priority[(wb_adr_i - `PLIC_BASE)/4];
					end else if(wb_adr_i == `PLIC_BASE + 32'h2000) begin
						wb_dat_o <= enable;
					end else if(wb_adr_i == `PLIC_BASE + 32'h200000) begin
						wb_dat_o <= threshold;
					end else if(wb_adr_i == `PLIC_BASE + 32'h200004) begin
						wb_dat_o <= irq;
					end
				end
				 wb_ack_o <= 1'b1;
        end
      end
	
	always @ (*) begin
		if(wb_rst_i == 1'b1) begin
			Interrupt = 1'b0;
			Exception_code = {3'b0, 28'h0000000};
			irq = `ZeroWord;
		end else begin
			if((uart_int == 1'b1) && (priority[1] > threshold) && (enable[1] == 1'b1) &&
							(csr_mstatus[3] == 1'b1) &&
								(csr_mie[11] == 1'b1))begin
				Interrupt = 1'b1;
				Exception_code = {3'b0, 28'h000000b};
				irq = 32'h00000001;
			end else begin
				Interrupt = 1'b0;
				Exception_code = {3'b0, 28'h0000000};
			end
			if(complete == 1'b1) begin
				Interrupt = 1'b0;
				Exception_code = {3'b0, 28'h0000000};
			end
		end
	end
	
	
endmodule
module plic(
	input  wire 	wb_clk_i,
	input  wire   	wb_rst_i,
	input  wire   	[31:0] wb_adr_i,
	output reg 		[31:0] wb_dat_o,
	input  wire   	[31:0] wb_dat_i,
	input  wire   	[3:0] wb_sel_i,
	input  wire   	wb_we_i,
	input  wire   	wb_stb_i,
	input  wire   	wb_cyc_i,
	output reg 		wb_ack_o,

	input wire uart_int,
	input wire gpio_int,

	output reg Interrupt,
	output reg [30:0] Exception_code,
	

	input wire[`RegBus]	csr_mie,
	input wire[`RegBus]	csr_mstatus
);


    parameter aw = 32;
    parameter dw = 32;
	 parameter irq_max = 6;


    wire wb_acc = wb_cyc_i & wb_stb_i;
    wire wb_wr  = wb_acc & wb_we_i;
    wire wb_rd  = wb_acc & !wb_we_i;

	reg[31:0] priority[0:6];
	reg[31:0] pending;
	reg[31:0] enable;
	reg[31:0] threshold;
	reg[31:0] irq;
	reg complete;
	
    always @(posedge wb_clk_i) begin
        if( wb_rst_i == 1'b1 ) begin
            wb_ack_o <= 1'b0;
				wb_dat_o <= `ZeroWord;
				enable <= 32'h00000000;
        end else if(wb_acc == 1'b0) begin
            wb_ack_o <= 1'b0;
				complete <= 1'b0;

        end else if(wb_acc == 1'b1) begin
				if(wb_wr == 1'b1) begin
					if((wb_adr_i >= `PLIC_BASE) && (wb_adr_i <= `PLIC_BASE + irq_max * 4)) begin
						priority[(wb_adr_i - `PLIC_BASE)/4] <= wb_dat_i;
					end else if(wb_adr_i == `PLIC_BASE + 32'h2000) begin
						enable <= wb_dat_i;
					end else if(wb_adr_i == `PLIC_BASE + 32'h200000) begin
						threshold <= wb_dat_i;
					end else if(wb_adr_i == `PLIC_BASE + 32'h200004) begin
						complete <= 1'b1;
					end
				end else if(wb_rd == 1'b1) begin
					if((wb_adr_i >= `PLIC_BASE) && (wb_adr_i <= `PLIC_BASE + irq_max * 4)) begin
						wb_dat_o <= priority[(wb_adr_i - `PLIC_BASE)/4];
					end else if(wb_adr_i == `PLIC_BASE + 32'h2000) begin
						wb_dat_o <= enable;
					end else if(wb_adr_i == `PLIC_BASE + 32'h200000) begin
						wb_dat_o <= threshold;
					end else if(wb_adr_i == `PLIC_BASE + 32'h200004) begin
						wb_dat_o <= irq;
					end
				end
				 wb_ack_o <= 1'b1;
        end
      end
	
	always @ (*) begin
		if(wb_rst_i == 1'b1) begin
			Interrupt = 1'b0;
			Exception_code = {3'b0, 28'h0000000};
			irq = `ZeroWord;
		end else begin
			if((uart_int == 1'b1) && (priority[1] > threshold) && (enable[1] == 1'b1) &&
							(csr_mstatus[3] == 1'b1) &&
								(csr_mie[11] == 1'b1))begin
				Interrupt = 1'b1;
				Exception_code = {3'b0, 28'h000000b};
				irq = 32'h00000001;
			end else begin
				Interrupt = 1'b0;
				Exception_code = {3'b0, 28'h0000000};
			end
			if(complete == 1'b1) begin
				Interrupt = 1'b0;
				Exception_code = {3'b0, 28'h0000000};
			end
		end
	end
	
	
endmodule