data/full_repos/permissive/504248338/verilog/dv/risc_boot/risc_boot_tb.v
1: b'%Error: data/full_repos/permissive/504248338/verilog/dv/risc_boot/risc_boot_tb.v:74: Cannot find include file: uart_agent.v\n`include "uart_agent.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/504248338/verilog/dv/risc_boot,data/full_repos/permissive/504248338/uart_agent.v\n             data/full_repos/permissive/504248338/verilog/dv/risc_boot,data/full_repos/permissive/504248338/uart_agent.v.v\n             data/full_repos/permissive/504248338/verilog/dv/risc_boot,data/full_repos/permissive/504248338/uart_agent.v.sv\n             uart_agent.v\n             uart_agent.v.v\n             uart_agent.v.sv\n             obj_dir/uart_agent.v\n             obj_dir/uart_agent.v.v\n             obj_dir/uart_agent.v.sv\n%Error: data/full_repos/permissive/504248338/verilog/dv/risc_boot/risc_boot_tb.v:366: Cannot find include file: s25fl256s.sv\n`include "s25fl256s.sv" \n         ^~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/risc_boot/risc_boot_tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n always #12.5 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/504248338/verilog/dv/risc_boot/risc_boot_tb.v:146: syntax error, unexpected \'@\'\n   repeat (2000) @(posedge clock);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/risc_boot/risc_boot_tb.v:172: Unsupported: Ignoring delay on this delayed statement.\n           #200;  \n           ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/risc_boot/risc_boot_tb.v:175: Unsupported: wait statements\n  wait(checkbits == 16\'h AB60);\n  ^~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/risc_boot/risc_boot_tb.v:179: syntax error, unexpected \'@\'\n  repeat (50000) @(posedge clock);  \n                 ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/risc_boot/risc_boot_tb.v:189: Unsupported: fork statements\n  fork\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/risc_boot/risc_boot_tb.v:206: Unsupported: Ignoring delay on this delayed statement.\n                 #100\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/risc_boot/risc_boot_tb.v:235: Unsupported: Ignoring delay on this delayed statement.\n              #100\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/risc_boot/risc_boot_tb.v:243: Unsupported: Ignoring delay on this delayed statement.\n  #2000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/risc_boot/risc_boot_tb.v:245: Unsupported: Ignoring delay on this delayed statement.\n  #170000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/risc_boot/risc_boot_tb.v:254: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/risc_boot/risc_boot_tb.v:256: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/risc_boot/risc_boot_tb.v:258: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/risc_boot/risc_boot_tb.v:260: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: Exiting due to 6 error(s), 10 warning(s)\n'
module risc_boot_tb;
	reg clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

	wire gpio;
	wire [37:0] mprj_io;
	wire [7:0] mprj_io_0;
	wire [15:0] checkbits;




        reg [1:0]      uart_data_bit        ;
        reg	       uart_stop_bits       ;
        reg	       uart_stick_parity    ;
        reg	       uart_parity_en       ;
        reg	       uart_even_odd_parity ;
        
        reg [7:0]      uart_data            ;
        reg [15:0]     uart_divisor         ;
        reg [15:0]     uart_timeout         ;
        
        reg [15:0]     uart_rx_nu           ;
        reg [15:0]     uart_tx_nu           ;
        reg [7:0]      uart_write_data [0:39];
        reg 	       uart_fifo_enable     ;
	reg            test_fail            ;
        
        integer i,j;

	
	assign checkbits = mprj_io[31:16];

	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;





	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
	end

pullup(mprj_io[3]); 


	`ifdef WFDUMP
        initial
        begin
           $dumpfile("simx.vcd");
           $dumpvars(1,risc_boot_tb);


           $dumpvars(1,risc_boot_tb.uut.mprj);
           $dumpvars(0,risc_boot_tb.uut.mprj.u_wb_host);


	   $display("Waveform Dump started");
        end
        `endif

	initial begin


		repeat (80) begin
			repeat (2000) @(posedge clock);

		end
		$display("%c[1;31m",27);
		$display ("##########################################################");
		`ifdef GL
			$display ("Monitor: Timeout, Test Risc Boot (GL) Failed");
		`else
			$display ("Monitor: Timeout, Test Risc Boot (RTL) Failed");
		`endif
		$display ("##########################################################");
		$display("%c[0m",27);
		$finish;
	end

        initial
        begin
           uart_data_bit           = 2'b11;
           uart_stop_bits          = 0;
           uart_stick_parity       = 0;
           uart_parity_en          = 0;
           uart_even_odd_parity    = 1;
           uart_divisor            = 15;
           uart_timeout            = 500;
           uart_fifo_enable        = 0;
        
           #200;


		wait(checkbits == 16'h AB60);
		$display("Monitor: Test User Risc Boot Started");


		repeat (50000) @(posedge clock);  
		tb_uart.uart_init;
		tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, 
					     uart_stick_parity, uart_timeout, uart_divisor);

		for (i=0; i<40; i=i+1)
		uart_write_data[i] = $random;



		fork
		 begin
		    for (i=0; i<40; i=i+1)
		    begin
		      $display ("\n... UART Agent Writing char %x ...", uart_write_data[i]);
		       tb_uart.write_char (uart_write_data[i]);
		    end
		 end

		 begin
		    for (j=0; j<40; j=j+1)
		    begin
		      tb_uart.read_char_chk(uart_write_data[j]);
		    end
		 end
		 join
              
                 #100
                 tb_uart.report_status(uart_rx_nu, uart_tx_nu);
              
                 test_fail = 0;
        




                 if(uart_tx_nu != 40) test_fail = 1;
                 if(uart_rx_nu != 40) test_fail = 1;
                 if(tb_uart.err_cnt != 0) test_fail = 1;
        

              $display("###################################################");
              if(test_fail == 0) begin
                 `ifdef GL
                     $display("Monitor: Standalone User Risc Boot Test (GL) Passed");
                 `else
                     $display("Monitor: Standalone User Risc Boot Test (RTL) Passed");
                 `endif
              end else begin
                  `ifdef GL
                      $display("Monitor: Standalone User Risc Boot Test (GL) Failed");
                  `else
                      $display("Monitor: Standalone User Risc Boot Test (RTL) Failed");
                  `endif
               end
              $display("###################################################");
              #100
              $finish;
        end


	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#170000;
		CSB = 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end





	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3 = power1;
	wire VDD1V8 = power2;
	wire USER_VDD3V3 = power3;
	wire USER_VDD1V8 = power4;
	wire VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vssio	  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (USER_VDD3V3),
		.vdda2    (USER_VDD3V3),
		.vssa1	  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (USER_VDD1V8),
		.vccd2	  (USER_VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock	  (clock),
		.gpio     (gpio),
        .mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("risc_boot.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);





   wire user_flash_clk = mprj_io[24];
   wire user_flash_csb = mprj_io[25];







     s25fl256s #(.mem_file_name("user_uart.hex"),
	         .otp_file_name("none"), 
                 .TimingModel("S25FL512SAGMFI010_F_30pF")) 
		 u_spi_flash_256mb (

       .SI      (mprj_io[29]),
       .SO      (mprj_io[30]),

       .SCK     (user_flash_clk),
       .CSNeg   (user_flash_csb),
       .WPNeg   (mprj_io[31]),
       .HOLDNeg (mprj_io[32]),
       .RSTNeg  (RSTB)

       );




wire uart_txd,uart_rxd;

assign uart_txd   = mprj_io[2];
assign mprj_io[1]  = uart_rxd ;
 
uart_agent tb_uart(
	.mclk                (clock              ),
	.txd                 (uart_rxd           ),
	.rxd                 (uart_txd           )
	);


`ifndef GL

initial begin
end
`endif    
endmodule
module risc_boot_tb;

	reg clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

	wire gpio;
	wire [37:0] mprj_io;
	wire [7:0] mprj_io_0;
	wire [15:0] checkbits;




        reg [1:0]      uart_data_bit        ;
        reg	       uart_stop_bits       ;
        reg	       uart_stick_parity    ;
        reg	       uart_parity_en       ;
        reg	       uart_even_odd_parity ;
        
        reg [7:0]      uart_data            ;
        reg [15:0]     uart_divisor         ;
        reg [15:0]     uart_timeout         ;
        
        reg [15:0]     uart_rx_nu           ;
        reg [15:0]     uart_tx_nu           ;
        reg [7:0]      uart_write_data [0:39];
        reg 	       uart_fifo_enable     ;
	reg            test_fail            ;
        
        integer i,j;

	
	assign checkbits = mprj_io[31:16];

	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;





	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
	end

pullup(mprj_io[3]); 


	`ifdef WFDUMP
        initial
        begin
           $dumpfile("simx.vcd");
           $dumpvars(1,risc_boot_tb);


           $dumpvars(1,risc_boot_tb.uut.mprj);
           $dumpvars(0,risc_boot_tb.uut.mprj.u_wb_host);


	   $display("Waveform Dump started");
        end
        `endif

	initial begin


		repeat (80) begin
			repeat (2000) @(posedge clock);

		end
		$display("%c[1;31m",27);
		$display ("##########################################################");
		`ifdef GL
			$display ("Monitor: Timeout, Test Risc Boot (GL) Failed");
		`else
			$display ("Monitor: Timeout, Test Risc Boot (RTL) Failed");
		`endif
		$display ("##########################################################");
		$display("%c[0m",27);
		$finish;
	end

        initial
        begin
           uart_data_bit           = 2'b11;
           uart_stop_bits          = 0;
           uart_stick_parity       = 0;
           uart_parity_en          = 0;
           uart_even_odd_parity    = 1;
           uart_divisor            = 15;
           uart_timeout            = 500;
           uart_fifo_enable        = 0;
        
           #200;


		wait(checkbits == 16'h AB60);
		$display("Monitor: Test User Risc Boot Started");


		repeat (50000) @(posedge clock);  
		tb_uart.uart_init;
		tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, 
					     uart_stick_parity, uart_timeout, uart_divisor);

		for (i=0; i<40; i=i+1)
		uart_write_data[i] = $random;



		fork
		 begin
		    for (i=0; i<40; i=i+1)
		    begin
		      $display ("\n... UART Agent Writing char %x ...", uart_write_data[i]);
		       tb_uart.write_char (uart_write_data[i]);
		    end
		 end

		 begin
		    for (j=0; j<40; j=j+1)
		    begin
		      tb_uart.read_char_chk(uart_write_data[j]);
		    end
		 end
		 join
              
                 #100
                 tb_uart.report_status(uart_rx_nu, uart_tx_nu);
              
                 test_fail = 0;
        




                 if(uart_tx_nu != 40) test_fail = 1;
                 if(uart_rx_nu != 40) test_fail = 1;
                 if(tb_uart.err_cnt != 0) test_fail = 1;
        

              $display("###################################################");
              if(test_fail == 0) begin
                 `ifdef GL
                     $display("Monitor: Standalone User Risc Boot Test (GL) Passed");
                 `else
                     $display("Monitor: Standalone User Risc Boot Test (RTL) Passed");
                 `endif
              end else begin
                  `ifdef GL
                      $display("Monitor: Standalone User Risc Boot Test (GL) Failed");
                  `else
                      $display("Monitor: Standalone User Risc Boot Test (RTL) Failed");
                  `endif
               end
              $display("###################################################");
              #100
              $finish;
        end


	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#170000;
		CSB = 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end





	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3 = power1;
	wire VDD1V8 = power2;
	wire USER_VDD3V3 = power3;
	wire USER_VDD1V8 = power4;
	wire VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vssio	  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (USER_VDD3V3),
		.vdda2    (USER_VDD3V3),
		.vssa1	  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (USER_VDD1V8),
		.vccd2	  (USER_VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock	  (clock),
		.gpio     (gpio),
        .mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("risc_boot.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);





   wire user_flash_clk = mprj_io[24];
   wire user_flash_csb = mprj_io[25];







     s25fl256s #(.mem_file_name("user_uart.hex"),
	         .otp_file_name("none"), 
                 .TimingModel("S25FL512SAGMFI010_F_30pF")) 
		 u_spi_flash_256mb (

       .SI      (mprj_io[29]),
       .SO      (mprj_io[30]),

       .SCK     (user_flash_clk),
       .CSNeg   (user_flash_csb),
       .WPNeg   (mprj_io[31]),
       .HOLDNeg (mprj_io[32]),
       .RSTNeg  (RSTB)

       );




wire uart_txd,uart_rxd;

assign uart_txd   = mprj_io[2];
assign mprj_io[1]  = uart_rxd ;
 
uart_agent tb_uart(
	.mclk                (clock              ),
	.txd                 (uart_rxd           ),
	.rxd                 (uart_txd           )
	);


`ifndef GL

initial begin
end
`endif    
endmodule