data/full_repos/permissive/460664642/bcd.v
data/verilator_xmls/67c8df58-6c98-4868-ace0-b80265168d9c.xml
module shift_add_3(
input[3:0] In,
output[3:0] Out
);
assign {Out[3:0]} = (In > 4) ? (In + 3) : In;
endmodule
module shift_add_3(
input[3:0] In,
output[3:0] Out
);

assign {Out[3:0]} = (In > 4) ? (In + 3) : In;
endmodule