data/full_repos/permissive/497530416/sequential/memory.v
1: b'%Warning-WIDTH: data/full_repos/permissive/497530416/sequential/memory.v:15: Bit extraction of array[127:0] requires 7 bit index, not 64 bits.\n                                                                           : ... In instance memory_seq\n    begin valM = memory[valE]; end\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/497530416/sequential/memory.v:18: Bit extraction of array[127:0] requires 7 bit index, not 64 bits.\n                                                                           : ... In instance memory_seq\n    begin valM = memory[valA]; end\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/497530416/sequential/memory.v:21: Bit extraction of array[127:0] requires 7 bit index, not 64 bits.\n                                                                           : ... In instance memory_seq\n    begin valM = memory[valA]; end\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/497530416/sequential/memory.v:30: Bit extraction of array[127:0] requires 7 bit index, not 64 bits.\n                                                                           : ... In instance memory_seq\n    begin memory[valE] = valA; end\n                ^\n%Warning-WIDTH: data/full_repos/permissive/497530416/sequential/memory.v:33: Bit extraction of array[127:0] requires 7 bit index, not 64 bits.\n                                                                           : ... In instance memory_seq\n    begin memory[valE] = valP; end\n                ^\n%Warning-WIDTH: data/full_repos/permissive/497530416/sequential/memory.v:36: Bit extraction of array[127:0] requires 7 bit index, not 64 bits.\n                                                                           : ... In instance memory_seq\n    begin memory[valE] = valA; end\n                ^\n%Error: Exiting due to 6 warning(s)\n'
module memory_seq(clk, icode, valA, valB, valP, valE, valM);

input clk;
input wire [3:0] icode;
input wire [63:0] valA, valB, valP, valE;

output reg [63:0] valM;
reg [63:0] memory [0:127];

always @(*)
begin
    case(icode)

    4'b0101:
    begin valM = memory[valE]; end

    4'b1001:
    begin valM = memory[valA]; end

    4'b1011:
    begin valM = memory[valA]; end
    
    endcase
end

always @(posedge clk) begin
    case(icode)

    4'b0100:
    begin memory[valE] = valA; end

    4'b1000:
    begin memory[valE] = valP; end

    4'b1010:
    begin memory[valE] = valA; end

    endcase
end

endmodule
module memory_seq(clk, icode, valA, valB, valP, valE, valM);


input clk;
input wire [3:0] icode;
input wire [63:0] valA, valB, valP, valE;

output reg [63:0] valM;
reg [63:0] memory [0:127];

always @(*)
begin
    case(icode)

    4'b0101:
    begin valM = memory[valE]; end

    4'b1001:
    begin valM = memory[valA]; end

    4'b1011:
    begin valM = memory[valA]; end
    
    endcase
end

always @(posedge clk) begin
    case(icode)

    4'b0100:
    begin memory[valE] = valA; end

    4'b1000:
    begin memory[valE] = valP; end

    4'b1010:
    begin memory[valE] = valA; end

    endcase
end

endmodule