data/full_repos/permissive/500696213/verilog/rtl/user_analog_proj_example.v
1: b'%Error: data/full_repos/permissive/500696213/verilog/rtl/user_analog_proj_example.v:18: Cannot find include file: example_por.v\n`include "example_por.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/500696213/verilog/rtl,data/full_repos/permissive/500696213/example_por.v\n             data/full_repos/permissive/500696213/verilog/rtl,data/full_repos/permissive/500696213/example_por.v.v\n             data/full_repos/permissive/500696213/verilog/rtl,data/full_repos/permissive/500696213/example_por.v.sv\n             example_por.v\n             example_por.v.v\n             example_por.v.sv\n             obj_dir/example_por.v\n             obj_dir/example_por.v.v\n             obj_dir/example_por.v.sv\n%Error: data/full_repos/permissive/500696213/verilog/rtl/user_analog_proj_example.v:111: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500696213/verilog/rtl/user_analog_proj_example.v:111: Define or directive not defined: \'`ANALOG_PADS\'\n    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,\n                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/500696213/verilog/rtl/user_analog_proj_example.v:112: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500696213/verilog/rtl/user_analog_proj_example.v:112: Define or directive not defined: \'`ANALOG_PADS\'\n    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,\n                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/500696213/verilog/rtl/user_analog_proj_example.v:113: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500696213/verilog/rtl/user_analog_proj_example.v:113: Define or directive not defined: \'`ANALOG_PADS\'\n    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,\n                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/500696213/verilog/rtl/user_analog_proj_example.v:114: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500696213/verilog/rtl/user_analog_proj_example.v:114: Define or directive not defined: \'`ANALOG_PADS\'\n    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,\n                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/500696213/verilog/rtl/user_analog_proj_example.v:117: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500696213/verilog/rtl/user_analog_proj_example.v:117: Define or directive not defined: \'`ANALOG_PADS\'\n    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,\n                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/500696213/verilog/rtl/user_analog_proj_example.v:118: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500696213/verilog/rtl/user_analog_proj_example.v:118: Define or directive not defined: \'`ANALOG_PADS\'\n    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,\n                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/500696213/verilog/rtl/user_analog_proj_example.v:121: Define or directive not defined: \'`ANALOG_PADS\'\n    inout [`ANALOG_PADS-1:0] io_analog,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/500696213/verilog/rtl/user_analog_proj_example.v:131: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500696213/verilog/rtl/user_analog_proj_example.v:131: Define or directive not defined: \'`ANALOG_PADS\'\n    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in;\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/500696213/verilog/rtl/user_analog_proj_example.v:132: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500696213/verilog/rtl/user_analog_proj_example.v:132: Define or directive not defined: \'`ANALOG_PADS\'\n    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3;\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/500696213/verilog/rtl/user_analog_proj_example.v:133: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500696213/verilog/rtl/user_analog_proj_example.v:133: Define or directive not defined: \'`ANALOG_PADS\'\n    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out;\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/500696213/verilog/rtl/user_analog_proj_example.v:134: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500696213/verilog/rtl/user_analog_proj_example.v:134: Define or directive not defined: \'`ANALOG_PADS\'\n    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb;\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/500696213/verilog/rtl/user_analog_proj_example.v:135: Define or directive not defined: \'`ANALOG_PADS\'\n    wire [`ANALOG_PADS-1:0] io_analog;\n          ^~~~~~~~~~~~\n%Error: Exiting due to 23 error(s)\n'
module user_analog_proj_example (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,


    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,


    inout [`ANALOG_PADS-1:0] io_analog,
    inout [2:0] io_clamp_high,
    inout [2:0] io_clamp_low,


    input   user_clock2,


    output [2:0] irq
);
    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in;
    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3;
    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out;
    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb;
    wire [`ANALOG_PADS-1:0] io_analog;







    wire isupply;
    wire io16, io15, io12, io11;

















    assign io_out[12:11] = {io12, io11};
    assign io_oeb[12:11] = {vssd1, vssd1};

    assign io_out[16:15] = {io16, io15};
    assign io_oeb[16:15] = {vssd1, vssd1};


    assign irq = 3'b000;










    wire vdd, vss;

    analog_top a_top (
	`ifdef USE_POWER_PINS
	    .vdd(vdd),
	    .vss(vss),
	`endif
        clk(clk),
        rst_n(rst_n),
        debug(debug),
        mod_op(mod_op),
        ip(ip),
        in(in),
        i_bias_1(i_bias_1),
        i_bias_2(i_bias_2),
        a_probe_0(a_probe_0),
        a_probe_1(a_probe_1),
        a_probe_2(a_probe_2),
        a_probe_3(a_probe_3)
    );

    digital_filter d_filter (
    `ifdef USE_POWER_PINS
	    .vdd(vdd),
	    .vss(vss),
    `endif
        clk(clk),
        rst_n(rst_n),
        sclk(sclk),
        cs_n(cs_n),
        data_in(mod_op),
        data_out(data_out),
        new_data(new_data),
        serial_data_out(serial_data_out)
    );

    sky130_fd_pr__cap_mim_m3_1_PXTAZD pxtazd_decap (
        .m4(vdd),
        .m3(vss)
    );






    `ifdef USE_POWER_PINS
	assign isupply = io_analog[4];
    	assign io_clamp_high[0] = isupply;
    	assign io_clamp_low[0] = vssa1;


    	assign io_clamp_high[2:1] = vssa1;
    	assign io_clamp_low[2:1] = vssa1;
    `endif




  

endmodule
module user_analog_proj_example (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,


    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,


    inout [`ANALOG_PADS-1:0] io_analog,
    inout [2:0] io_clamp_high,
    inout [2:0] io_clamp_low,


    input   user_clock2,


    output [2:0] irq
);

    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in;
    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3;
    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out;
    wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb;
    wire [`ANALOG_PADS-1:0] io_analog;







    wire isupply;
    wire io16, io15, io12, io11;

















    assign io_out[12:11] = {io12, io11};
    assign io_oeb[12:11] = {vssd1, vssd1};

    assign io_out[16:15] = {io16, io15};
    assign io_oeb[16:15] = {vssd1, vssd1};


    assign irq = 3'b000;










    wire vdd, vss;

    analog_top a_top (
	`ifdef USE_POWER_PINS
	    .vdd(vdd),
	    .vss(vss),
	`endif
        clk(clk),
        rst_n(rst_n),
        debug(debug),
        mod_op(mod_op),
        ip(ip),
        in(in),
        i_bias_1(i_bias_1),
        i_bias_2(i_bias_2),
        a_probe_0(a_probe_0),
        a_probe_1(a_probe_1),
        a_probe_2(a_probe_2),
        a_probe_3(a_probe_3)
    );

    digital_filter d_filter (
    `ifdef USE_POWER_PINS
	    .vdd(vdd),
	    .vss(vss),
    `endif
        clk(clk),
        rst_n(rst_n),
        sclk(sclk),
        cs_n(cs_n),
        data_in(mod_op),
        data_out(data_out),
        new_data(new_data),
        serial_data_out(serial_data_out)
    );

    sky130_fd_pr__cap_mim_m3_1_PXTAZD pxtazd_decap (
        .m4(vdd),
        .m3(vss)
    );






    `ifdef USE_POWER_PINS
	assign isupply = io_analog[4];
    	assign io_clamp_high[0] = isupply;
    	assign io_clamp_low[0] = vssa1;


    	assign io_clamp_high[2:1] = vssa1;
    	assign io_clamp_low[2:1] = vssa1;
    `endif




  

endmodule