data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/BUGS/flip_flop_enable.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/BUGS/flip_flop_enable.v:9: Signal definition not found, creating implicitly: \'d2\'\n                                                                                                                        : ... Suggested alternative: \'d0\'\nposedge_reg_sync_reset zzxx_posedge_reg_sync_reset_zzxx (d2,clk,resetn,en,q2);\n                                                         ^~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/BUGS/flip_flop_enable.v:9: Signal definition not found, creating implicitly: \'q2\'\n                                                                                                                        : ... Suggested alternative: \'q0\'\nposedge_reg_sync_reset zzxx_posedge_reg_sync_reset_zzxx (d2,clk,resetn,en,q2);\n                                                                          ^~\n%Error: Exiting due to 2 warning(s)\n'
module posedge_reg_sync_reset(d,clk,resetn,en,q);


input clk;
input resetn;
input en;
input d;
output  q;
reg q;

always @(posedge clk )		
begin
	if (resetn==0)
		q<=0;
	else if (en==1)
		q<=d;
end

endmodule
module posedge_reg_sync_reset(d,clk,resetn,en,q);



input clk;
input resetn;
input en;
input d;
output  q;
reg q;

always @(posedge clk )		
begin
	if (resetn==0)
		q<=0;
	else if (en==1)
		q<=d;
end

endmodule