data/full_repos/permissive/530404104/src/user_module_341364381657858642.v
1: b'%Warning-WIDTH: data/full_repos/permissive/530404104/src/user_module_341364381657858642.v:67: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s REPLICATE generates 5 bits.\n                                                                                            : ... In instance user_module_341364381657858642.mcpu6bit_top\nassign dataout   = clk ?  {1\'b00,adreg} : accumulator[5:0]; \n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module mcpu6bit(datain,dataout,we,rst,clk);

input [5:0] datain;
output [5:0] dataout;
output we;
input rst;
input clk;

reg [6:0] accumulator;
reg [3:0] adreg;
reg [3:0] pc;
reg [2:0] states;

initial begin
end

	always @(posedge clk)
		if (~rst) begin
			adreg 	  <= 0;
			states	  <= 0;
			accumulator <= 0;	
			pc <= 0;
		end
		else begin

			if (~|states) begin
				pc	 <= adreg + 1'b1;
				adreg <= datain[3:0];
			end
			else adreg <= pc;
		

			case(states)
				3'b010 : accumulator 	 <= {1'b0, accumulator[5:0]} + {1'b0, datain};
				3'b011 : accumulator[5:0] <= ~(accumulator[5:0]|datain);
				3'b101 : accumulator[6]   <= 1'b0;
			endcase


			if (|states) states <= 0;
			else begin 
				if ( &datain[5:4] && accumulator[6] ) states <= 3'b101;
				else states <= {1'b0, ~datain[5:4]};
			end
		end

assign dataout   = clk ?  {1'b00,adreg} : accumulator[5:0]; 
assign we     =  ~rst | (states!=3'b001) ; 

endmodule
module mcpu6bit(datain,dataout,we,rst,clk);


input [5:0] datain;
output [5:0] dataout;
output we;
input rst;
input clk;

reg [6:0] accumulator;
reg [3:0] adreg;
reg [3:0] pc;
reg [2:0] states;

initial begin
end

	always @(posedge clk)
		if (~rst) begin
			adreg 	  <= 0;
			states	  <= 0;
			accumulator <= 0;	
			pc <= 0;
		end
		else begin

			if (~|states) begin
				pc	 <= adreg + 1'b1;
				adreg <= datain[3:0];
			end
			else adreg <= pc;
		

			case(states)
				3'b010 : accumulator 	 <= {1'b0, accumulator[5:0]} + {1'b0, datain};
				3'b011 : accumulator[5:0] <= ~(accumulator[5:0]|datain);
				3'b101 : accumulator[6]   <= 1'b0;
			endcase


			if (|states) states <= 0;
			else begin 
				if ( &datain[5:4] && accumulator[6] ) states <= 3'b101;
				else states <= {1'b0, ~datain[5:4]};
			end
		end

assign dataout   = clk ?  {1'b00,adreg} : accumulator[5:0]; 
assign we     =  ~rst | (states!=3'b001) ; 

endmodule