data/full_repos/permissive/44929513/testa_decrement.v
1: b'%Error: data/full_repos/permissive/44929513/testa_decrement.v:1: Cannot find include file: decrement.v\n`include "decrement.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/44929513,data/full_repos/permissive/44929513/decrement.v\n             data/full_repos/permissive/44929513,data/full_repos/permissive/44929513/decrement.v.v\n             data/full_repos/permissive/44929513,data/full_repos/permissive/44929513/decrement.v.sv\n             decrement.v\n             decrement.v.v\n             decrement.v.sv\n             obj_dir/decrement.v\n             obj_dir/decrement.v.v\n             obj_dir/decrement.v.sv\n%Error: data/full_repos/permissive/44929513/testa_decrement.v:7: Unsupported or unknown PLI call: $monitor\n    $monitor("a(%d): %b b(%d): %b out(%d): %b gray: %b", a,a,b,b,out,out,carry);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/44929513/testa_decrement.v:8: Unsupported: Ignoring delay on this delayed statement.\n    #1 a <= -2;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/44929513/testa_decrement.v:10: Unsupported: Ignoring delay on this delayed statement.\n    #1 a <=3;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/44929513/testa_decrement.v:12: Unsupported: Ignoring delay on this delayed statement.\n    #1 a <=3;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/44929513/testa_decrement.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #1 a <= 7;\n    ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n'
module main;
reg signed [3:0] a, b;
wire signed [3:0] out;
wire carry;
initial begin
    $monitor("a(%d): %b b(%d): %b out(%d): %b gray: %b", a,a,b,b,out,out,carry);
    #1 a <= -2;
    b <= -1;
    #1 a <=3;
    b<=2;
    #1 a <=3;
    b<=0;
    #1 a <= 7;
    b <= -2;
end
decrement U_decrement(a,b,out,carry);
endmodule
module main;

reg signed [3:0] a, b;
wire signed [3:0] out;
wire carry;
initial begin
    $monitor("a(%d): %b b(%d): %b out(%d): %b gray: %b", a,a,b,b,out,out,carry);
    #1 a <= -2;
    b <= -1;
    #1 a <=3;
    b<=2;
    #1 a <=3;
    b<=0;
    #1 a <= 7;
    b <= -2;
end
decrement U_decrement(a,b,out,carry);
endmodule