data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/ClockCycleGraph_ALU_REG_OP.v
1: b'%Error: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/ClockCycleGraph_ALU_REG_OP.v:11: Unsupported: fork statements\ninitial fork \n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/ClockCycleGraph_ALU_REG_OP.v:13: Unsupported: Ignoring delay on this delayed statement.\n #((sim_time/4)+cudelay) load =1 ;#((sim_time/4)+cudelay) alu_out = 1 ;#((sim_time/4)+cudelay) ir_cu =1 ; #((sim_time/4)+cudelay) opcode =4 ; \n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/ClockCycleGraph_ALU_REG_OP.v:13: Unsupported: Ignoring delay on this delayed statement.\n #((sim_time/4)+cudelay) load =1 ;#((sim_time/4)+cudelay) alu_out = 1 ;#((sim_time/4)+cudelay) ir_cu =1 ; #((sim_time/4)+cudelay) opcode =4 ; \n                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/ClockCycleGraph_ALU_REG_OP.v:13: Unsupported: Ignoring delay on this delayed statement.\n #((sim_time/4)+cudelay) load =1 ;#((sim_time/4)+cudelay) alu_out = 1 ;#((sim_time/4)+cudelay) ir_cu =1 ; #((sim_time/4)+cudelay) opcode =4 ; \n                                                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/ClockCycleGraph_ALU_REG_OP.v:13: Unsupported: Ignoring delay on this delayed statement.\n #((sim_time/4)+cudelay) load =1 ;#((sim_time/4)+cudelay) alu_out = 1 ;#((sim_time/4)+cudelay) ir_cu =1 ; #((sim_time/4)+cudelay) opcode =4 ; \n                                                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/ClockCycleGraph_ALU_REG_OP.v:14: Unsupported: Ignoring delay on this delayed statement.\n #((sim_time/4)+rfdelay+cudelay) A = 5;#((sim_time/4)+rfdelay+cudelay) B = 5;#((sim_time/4)+rfdelay+cudelay) C = 5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/ClockCycleGraph_ALU_REG_OP.v:14: Unsupported: Ignoring delay on this delayed statement.\n #((sim_time/4)+rfdelay+cudelay) A = 5;#((sim_time/4)+rfdelay+cudelay) B = 5;#((sim_time/4)+rfdelay+cudelay) C = 5;\n                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/ClockCycleGraph_ALU_REG_OP.v:14: Unsupported: Ignoring delay on this delayed statement.\n #((sim_time/4)+rfdelay+cudelay) A = 5;#((sim_time/4)+rfdelay+cudelay) B = 5;#((sim_time/4)+rfdelay+cudelay) C = 5;\n                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/ClockCycleGraph_ALU_REG_OP.v:15: Unsupported: Ignoring delay on this delayed statement.\n #((sim_time/4)+rfdelay+cudelay+aludelay) Out = A + B;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/ClockCycleGraph_ALU_REG_OP.v:16: Unsupported: Ignoring delay on this delayed statement.\n #(sim_time/4) Clk = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/ClockCycleGraph_ALU_REG_OP.v:17: Unsupported: Ignoring delay on this delayed statement.\n #(sim_time/2) Clk = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/ClockCycleGraph_ALU_REG_OP.v:18: Unsupported: Ignoring delay on this delayed statement.\n #(sim_time - sim_time/4) Clk = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/ClockCycleGraph_ALU_REG_OP.v:21: Unsupported: Ignoring delay on this delayed statement.\ninitial #sim_time $finish; \n        ^\n%Error: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/ClockCycleGraph_ALU_REG_OP.v:24: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("ClockCycleGraph_ALU_REG_OP.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/ClockCycleGraph_ALU_REG_OP.v:25: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,ClockCycleGraph_ALU_REG_OP);\n ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ClockCycleGraph_ALU_REG_OP;

parameter sim_time = 100*2;
parameter cudelay = (sim_time/10);
parameter rfdelay = (sim_time/20);
parameter bsdelay = (sim_time/20);
parameter aludelay = (sim_time/20);
reg load,alu_out,ir_cu,Clk;
reg [4:0] opcode;
reg [31:0] A,B,C,Out;
initial fork 
	Clk = 1;
	#((sim_time/4)+cudelay) load =1 ;#((sim_time/4)+cudelay) alu_out = 1 ;#((sim_time/4)+cudelay) ir_cu =1 ; #((sim_time/4)+cudelay) opcode =4 ; 
	#((sim_time/4)+rfdelay+cudelay) A = 5;#((sim_time/4)+rfdelay+cudelay) B = 5;#((sim_time/4)+rfdelay+cudelay) C = 5;
	#((sim_time/4)+rfdelay+cudelay+aludelay) Out = A + B;
	#(sim_time/4) Clk = 0;
	#(sim_time/2) Clk = 1;
	#(sim_time - sim_time/4) Clk = 0;
join

initial #sim_time $finish; 

initial begin
	$dumpfile("ClockCycleGraph_ALU_REG_OP.vcd");
	$dumpvars(0,ClockCycleGraph_ALU_REG_OP);
end

endmodule
module ClockCycleGraph_ALU_REG_OP;


parameter sim_time = 100*2;
parameter cudelay = (sim_time/10);
parameter rfdelay = (sim_time/20);
parameter bsdelay = (sim_time/20);
parameter aludelay = (sim_time/20);
reg load,alu_out,ir_cu,Clk;
reg [4:0] opcode;
reg [31:0] A,B,C,Out;
initial fork 
	Clk = 1;
	#((sim_time/4)+cudelay) load =1 ;#((sim_time/4)+cudelay) alu_out = 1 ;#((sim_time/4)+cudelay) ir_cu =1 ; #((sim_time/4)+cudelay) opcode =4 ; 
	#((sim_time/4)+rfdelay+cudelay) A = 5;#((sim_time/4)+rfdelay+cudelay) B = 5;#((sim_time/4)+rfdelay+cudelay) C = 5;
	#((sim_time/4)+rfdelay+cudelay+aludelay) Out = A + B;
	#(sim_time/4) Clk = 0;
	#(sim_time/2) Clk = 1;
	#(sim_time - sim_time/4) Clk = 0;
join

initial #sim_time $finish; 

initial begin
	$dumpfile("ClockCycleGraph_ALU_REG_OP.vcd");
	$dumpvars(0,ClockCycleGraph_ALU_REG_OP);
end

endmodule