data/full_repos/permissive/472097485/Lang0/Not01/TestYou.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/472097485/Lang0/Not01/TestYou.v:21: Unsupported: Ignoring delay on this delayed statement.\n #1 clock =!clock;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Lang0/Not01/TestYou.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: data/full_repos/permissive/472097485/Lang0/Not01/TestYou.v:15: Cannot find file containing module: \'TestMe\'\n TestMe uut (\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/472097485/Lang0/Not01,data/full_repos/permissive/472097485/TestMe\n             data/full_repos/permissive/472097485/Lang0/Not01,data/full_repos/permissive/472097485/TestMe.v\n             data/full_repos/permissive/472097485/Lang0/Not01,data/full_repos/permissive/472097485/TestMe.sv\n             TestMe\n             TestMe.v\n             TestMe.sv\n             obj_dir/TestMe\n             obj_dir/TestMe.v\n             obj_dir/TestMe.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TestYou;


	reg clock;


	wire out;


	TestMe uut (
		.A(clock), 
		.B(out)
	);

	always begin
	#1 clock =!clock;
	end

	initial begin

		clock = 1;


		#10;
	

		$stop;
	end
		
endmodule
module TestYou;



	reg clock;


	wire out;


	TestMe uut (
		.A(clock), 
		.B(out)
	);

	always begin
	#1 clock =!clock;
	end

	initial begin

		clock = 1;


		#10;
	

		$stop;
	end
		
endmodule