data/full_repos/permissive/432880511/xjy1.v
1: b"%Error: data/full_repos/permissive/432880511/xjy1.v:12: Cannot find file containing module: 'clk2'\n clk2 clk2_inst (\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/432880511,data/full_repos/permissive/432880511/clk2\n             data/full_repos/permissive/432880511,data/full_repos/permissive/432880511/clk2.v\n             data/full_repos/permissive/432880511,data/full_repos/permissive/432880511/clk2.sv\n             clk2\n             clk2.v\n             clk2.sv\n             obj_dir/clk2\n             obj_dir/clk2.v\n             obj_dir/clk2.sv\n%Error: Exiting due to 1 error(s)\n"
module xjy1(
input c,
input clk,
output reg e

);

reg[0:0] d1;
wire clk_40M;
wire clk_100M;

	clk2	clk2_inst (
	.inclk0 ( clk ),
	.c0 ( clk_40M ),
	.c1 ( clk_100M )
	);

initial begin
	e  <= 1'b0;
	d1  <= 1'b0;
end

always @(posedge clk_100M)begin
	d1 <= c;
	e <= d1 & (~c);
	end
endmodule
module xjy1(
input c,
input clk,
output reg e

);


reg[0:0] d1;
wire clk_40M;
wire clk_100M;

	clk2	clk2_inst (
	.inclk0 ( clk ),
	.c0 ( clk_40M ),
	.c1 ( clk_100M )
	);

initial begin
	e  <= 1'b0;
	d1  <= 1'b0;
end

always @(posedge clk_100M)begin
	d1 <= c;
	e <= d1 & (~c);
	end
endmodule