data/full_repos/permissive/458935738/common/speedctl2.v
1: b'%Error: data/full_repos/permissive/458935738/common/speedctl2.v:67: Cannot find file containing module: \'pwm\'\npwm pwm_generator(clk, enable, speed, PWM);\n^~~\n        ... Looked in:\n             data/full_repos/permissive/458935738/common,data/full_repos/permissive/458935738/pwm\n             data/full_repos/permissive/458935738/common,data/full_repos/permissive/458935738/pwm.v\n             data/full_repos/permissive/458935738/common,data/full_repos/permissive/458935738/pwm.sv\n             pwm\n             pwm.v\n             pwm.sv\n             obj_dir/pwm\n             obj_dir/pwm.v\n             obj_dir/pwm.sv\n%Warning-WIDTH: data/full_repos/permissive/458935738/common/speedctl2.v:71: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'deg_s\' generates 16 bits.\n                                                                          : ... In instance speedctl2\n    speed <= (enable && deg_s) ? speed + acceleration : 16\'d0;\n                     ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module speedctl2 (
    input clk,
    input enable,
    input encoder,
    input [15:0] deg_s,
    output wire PWM
);

parameter LOG_DIV = 3;
parameter LOG_PROP = 3;
parameter LOG_DERIV = 3;

localparam TICKS = 32'd16000000 >> LOG_DIV;


localparam IDLE = 2'b00;
localparam COUNT = 2'b01;
localparam UPDATE = 2'b10;
reg [1:0] current_state, next_state;

reg enc1, enc2, enc3;
wire pulse;
always @(posedge clk) begin
    enc1 <= encoder;
    enc2 <= enc1;
    enc3 <= enc2;
end
assign pulse = ~enc3 & enc2;

reg signed [15:0] speed;
reg signed [15:0] acceleration;
reg [31:0] timer, timer_next;
reg signed [15:0] counter, counter_next;
reg signed [15:0] error_prev, error_prev_next;

wire signed [15:0] target;
assign target = deg_s >> LOG_DIV;
wire signed [15:0] error;
assign error = target - counter;

pwm pwm_generator(clk, enable, speed, PWM);

always @(posedge clk) begin
    current_state <= next_state;
    speed <= (enable && deg_s) ? speed + acceleration : 16'd0;
    timer <= timer_next;
    counter <= counter_next;
    error_prev <= error_prev_next;
end

always @(*) begin

    acceleration = 0;
    timer_next = TICKS;
    counter_next = 0;
    next_state = IDLE;
    error_prev_next = error_prev;
    case (current_state)
        IDLE: begin
            next_state = enable ? COUNT : IDLE;
        end

        COUNT: begin
            acceleration = 0;
            counter_next = counter + {15'd0, pulse};
            timer_next = timer - 32'd1;
            if (enable) begin
                next_state = (timer == 32'd0) ? UPDATE : COUNT;
            end else begin
                next_state = IDLE;
            end
        end

        UPDATE: begin
            error_prev_next = error;
            acceleration = 
                (error << LOG_PROP) + ((error - error_prev) << LOG_DERIV);
            counter_next = 0;
            timer_next = TICKS;
            next_state = enable ? COUNT : IDLE;
        end
    endcase
end

endmodule
module speedctl2 (
    input clk,
    input enable,
    input encoder,
    input [15:0] deg_s,
    output wire PWM
);


parameter LOG_DIV = 3;
parameter LOG_PROP = 3;
parameter LOG_DERIV = 3;

localparam TICKS = 32'd16000000 >> LOG_DIV;


localparam IDLE = 2'b00;
localparam COUNT = 2'b01;
localparam UPDATE = 2'b10;
reg [1:0] current_state, next_state;

reg enc1, enc2, enc3;
wire pulse;
always @(posedge clk) begin
    enc1 <= encoder;
    enc2 <= enc1;
    enc3 <= enc2;
end
assign pulse = ~enc3 & enc2;

reg signed [15:0] speed;
reg signed [15:0] acceleration;
reg [31:0] timer, timer_next;
reg signed [15:0] counter, counter_next;
reg signed [15:0] error_prev, error_prev_next;

wire signed [15:0] target;
assign target = deg_s >> LOG_DIV;
wire signed [15:0] error;
assign error = target - counter;

pwm pwm_generator(clk, enable, speed, PWM);

always @(posedge clk) begin
    current_state <= next_state;
    speed <= (enable && deg_s) ? speed + acceleration : 16'd0;
    timer <= timer_next;
    counter <= counter_next;
    error_prev <= error_prev_next;
end

always @(*) begin

    acceleration = 0;
    timer_next = TICKS;
    counter_next = 0;
    next_state = IDLE;
    error_prev_next = error_prev;
    case (current_state)
        IDLE: begin
            next_state = enable ? COUNT : IDLE;
        end

        COUNT: begin
            acceleration = 0;
            counter_next = counter + {15'd0, pulse};
            timer_next = timer - 32'd1;
            if (enable) begin
                next_state = (timer == 32'd0) ? UPDATE : COUNT;
            end else begin
                next_state = IDLE;
            end
        end

        UPDATE: begin
            error_prev_next = error;
            acceleration = 
                (error << LOG_PROP) + ((error - error_prev) << LOG_DERIV);
            counter_next = 0;
            timer_next = TICKS;
            next_state = enable ? COUNT : IDLE;
        end
    endcase
end

endmodule