data/full_repos/permissive/423958267/lab05/lab05.srcs/sim_1/new/testALU.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/423958267/lab05/lab05.srcs/sim_1/new/testALU.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #0 A = 32\'h5; B = 32\'hA; Cin = 1; alu_ops = 3\'d0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab05/lab05.srcs/sim_1/new/testALU.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #10 alu_ops = 3\'d1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab05/lab05.srcs/sim_1/new/testALU.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #10 alu_ops = 3\'d2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab05/lab05.srcs/sim_1/new/testALU.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #10 alu_ops = 3\'d3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab05/lab05.srcs/sim_1/new/testALU.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #10 alu_ops = 3\'d4;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab05/lab05.srcs/sim_1/new/testALU.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #10 alu_ops = 3\'d5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab05/lab05.srcs/sim_1/new/testALU.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #10 alu_ops = 3\'d6;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab05/lab05.srcs/sim_1/new/testALU.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #10 alu_ops = 3\'d7;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab05/lab05.srcs/sim_1/new/testALU.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #20 $finish;        \n        ^\n%Error: data/full_repos/permissive/423958267/lab05/lab05.srcs/sim_1/new/testALU.v:33: Cannot find file containing module: \'alu\'\n    alu ALU(S,z,Cout,A,B,Cin,alu_ops);\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/423958267/lab05/lab05.srcs/sim_1/new,data/full_repos/permissive/423958267/alu\n             data/full_repos/permissive/423958267/lab05/lab05.srcs/sim_1/new,data/full_repos/permissive/423958267/alu.v\n             data/full_repos/permissive/423958267/lab05/lab05.srcs/sim_1/new,data/full_repos/permissive/423958267/alu.sv\n             alu\n             alu.v\n             alu.sv\n             obj_dir/alu\n             obj_dir/alu.v\n             obj_dir/alu.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testALU(

    );
    wire [31:0] S;
    wire z;
    wire Cout;
    reg [31:0] A;
    reg [31:0] B;
    reg Cin;
    reg [2:0] alu_ops;
    alu ALU(S,z,Cout,A,B,Cin,alu_ops);
    
    initial
    begin
        #0 A = 32'h5; B = 32'hA; Cin = 1; alu_ops = 3'd0;
        #10 alu_ops = 3'd1;
        #10 alu_ops = 3'd2;
        #10 alu_ops = 3'd3;
        #10 alu_ops = 3'd4;
        #10 alu_ops = 3'd5;
        #10 alu_ops = 3'd6;
        #10 alu_ops = 3'd7;
        #20 $finish;        
    end
endmodule
module testALU(

    );

    wire [31:0] S;
    wire z;
    wire Cout;
    reg [31:0] A;
    reg [31:0] B;
    reg Cin;
    reg [2:0] alu_ops;
    alu ALU(S,z,Cout,A,B,Cin,alu_ops);
    
    initial
    begin
        #0 A = 32'h5; B = 32'hA; Cin = 1; alu_ops = 3'd0;
        #10 alu_ops = 3'd1;
        #10 alu_ops = 3'd2;
        #10 alu_ops = 3'd3;
        #10 alu_ops = 3'd4;
        #10 alu_ops = 3'd5;
        #10 alu_ops = 3'd6;
        #10 alu_ops = 3'd7;
        #20 $finish;        
    end
endmodule