data/full_repos/permissive/518460376/verilog/rtl/rtl/clk_rst_gen.v
1: b'%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/rtl/clk_rst_gen.v:80: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                     : ... In instance clk_rst_gen\n assign fll_r_data_o = 1\'b0;\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/518460376/verilog/rtl/rtl/clk_rst_gen.v:83: Cannot find file containing module: \'rstgen\'\n rstgen i_rst_gen_soc(\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/518460376/verilog/rtl/rtl,data/full_repos/permissive/518460376/rstgen\n             data/full_repos/permissive/518460376/verilog/rtl/rtl,data/full_repos/permissive/518460376/rstgen.v\n             data/full_repos/permissive/518460376/verilog/rtl/rtl,data/full_repos/permissive/518460376/rstgen.sv\n             rstgen\n             rstgen.v\n             rstgen.sv\n             obj_dir/rstgen\n             obj_dir/rstgen.v\n             obj_dir/rstgen.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module clk_rst_gen (




	clk_i,
	rstn_i,
	clk_sel_i,
	clk_standalone_i,
	testmode_i,
	scan_en_i,
	scan_i,
	scan_o,
	fll_req_i,
	fll_wrn_i,
	fll_add_i,
	fll_data_i,
	fll_ack_o,
	fll_r_data_o,
	fll_lock_o,
	clk_o,
	rstn_o,


user_irq,
io_oeb,
io_out,
wbs_ack_o,
wbs_dat_o,
la_data_out

);




	input wire clk_i;
	input wire rstn_i;
	input wire clk_sel_i;
	input wire clk_standalone_i;
	input wire testmode_i;
	input wire scan_en_i;
	input wire scan_i;
	output wire scan_o;
	input wire fll_req_i;
	input wire fll_wrn_i;
	input wire [1:0] fll_add_i;
	input wire [31:0] fll_data_i;
	output wire fll_ack_o;
	output wire [31:0] fll_r_data_o;
	output wire fll_lock_o;
	output wire clk_o;
	output wire rstn_o;

	output wire [2:0] user_irq;
	output wire [37:0] io_oeb;
	output wire [25:0] io_out;
	output wire wbs_ack_o;
	output wire [31:0] wbs_dat_o;
	output wire [63:0] la_data_out;

	wire clk_fll_int;
	wire clk_int;

wire rstn;
assign rstn = ~rstn_i;

	assign user_irq = 3'b000;
	assign io_oeb[37:26] = 12'b000000000000;	
	assign io_out[25:0] = 26'b11111111111111111111111111;
	assign io_oeb[25:0] = 26'b11111111111111111111111111;
	assign wbs_ack_o = 1'b0;
	assign wbs_dat_o = 32'b00000000000000000000000000000000;
	assign la_data_out[63:0] = 64'b0000000000000000000000000000000000000000000000000000000000000000;

	assign clk_int = clk_i;
	assign fll_ack_o = fll_req_i;
	assign fll_r_data_o = 1'b0;
	assign fll_lock_o = 1'b0;
	assign scan_o = 1'b0;
	rstgen i_rst_gen_soc(
		.clk_i(clk_int),


		.rst_ni(rstn),

		.test_mode_i(testmode_i),
		.rst_no(rstn_o),
		.init_no()
	);
	assign clk_o = clk_int;
endmodule
module clk_rst_gen (




	clk_i,
	rstn_i,
	clk_sel_i,
	clk_standalone_i,
	testmode_i,
	scan_en_i,
	scan_i,
	scan_o,
	fll_req_i,
	fll_wrn_i,
	fll_add_i,
	fll_data_i,
	fll_ack_o,
	fll_r_data_o,
	fll_lock_o,
	clk_o,
	rstn_o,


user_irq,
io_oeb,
io_out,
wbs_ack_o,
wbs_dat_o,
la_data_out

);





	input wire clk_i;
	input wire rstn_i;
	input wire clk_sel_i;
	input wire clk_standalone_i;
	input wire testmode_i;
	input wire scan_en_i;
	input wire scan_i;
	output wire scan_o;
	input wire fll_req_i;
	input wire fll_wrn_i;
	input wire [1:0] fll_add_i;
	input wire [31:0] fll_data_i;
	output wire fll_ack_o;
	output wire [31:0] fll_r_data_o;
	output wire fll_lock_o;
	output wire clk_o;
	output wire rstn_o;

	output wire [2:0] user_irq;
	output wire [37:0] io_oeb;
	output wire [25:0] io_out;
	output wire wbs_ack_o;
	output wire [31:0] wbs_dat_o;
	output wire [63:0] la_data_out;

	wire clk_fll_int;
	wire clk_int;

wire rstn;
assign rstn = ~rstn_i;

	assign user_irq = 3'b000;
	assign io_oeb[37:26] = 12'b000000000000;	
	assign io_out[25:0] = 26'b11111111111111111111111111;
	assign io_oeb[25:0] = 26'b11111111111111111111111111;
	assign wbs_ack_o = 1'b0;
	assign wbs_dat_o = 32'b00000000000000000000000000000000;
	assign la_data_out[63:0] = 64'b0000000000000000000000000000000000000000000000000000000000000000;

	assign clk_int = clk_i;
	assign fll_ack_o = fll_req_i;
	assign fll_r_data_o = 1'b0;
	assign fll_lock_o = 1'b0;
	assign scan_o = 1'b0;
	rstgen i_rst_gen_soc(
		.clk_i(clk_int),


		.rst_ni(rstn),

		.test_mode_i(testmode_i),
		.rst_no(rstn_o),
		.init_no()
	);
	assign clk_o = clk_int;
endmodule