data/full_repos/permissive/47537295/src/test_main.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/47537295/src/test_main.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #50000000;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/47537295/src/test_main.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #90000000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/47537295/src/test_main.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #10000000;\n  ^\n%Error: data/full_repos/permissive/47537295/src/test_main.v:36: Cannot find file containing module: \'main\'\n main #(.freq (50), .debouncer_cycles (2)) uut (\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/47537295/src,data/full_repos/permissive/47537295/main\n             data/full_repos/permissive/47537295/src,data/full_repos/permissive/47537295/main.v\n             data/full_repos/permissive/47537295/src,data/full_repos/permissive/47537295/main.sv\n             main\n             main.v\n             main.sv\n             obj_dir/main\n             obj_dir/main.v\n             obj_dir/main.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_main;


	reg rst_in;
	reg clk;
	reg sync;

	wire [7:0] seg;
	wire [3:0] an;


	main #(.freq (50), .debouncer_cycles (2)) uut (
		.rst_in(rst_in), 
		.clk(clk), 
		.seg(seg), 
		.sync (sync),
		.an(an)
	);

	initial begin

		rst_in = 0;
		clk = 0;
		sync = 0;

		#50000000;
      
		rst_in = 1;
		#90000000;
		rst_in=0;


	end
   
	always begin
		clk = ~clk;
		#10000000;
	end
endmodule
module test_main;



	reg rst_in;
	reg clk;
	reg sync;

	wire [7:0] seg;
	wire [3:0] an;


	main #(.freq (50), .debouncer_cycles (2)) uut (
		.rst_in(rst_in), 
		.clk(clk), 
		.seg(seg), 
		.sync (sync),
		.an(an)
	);

	initial begin

		rst_in = 0;
		clk = 0;
		sync = 0;

		#50000000;
      
		rst_in = 1;
		#90000000;
		rst_in=0;


	end
   
	always begin
		clk = ~clk;
		#10000000;
	end
endmodule