data/full_repos/permissive/489642764/src/wb_ctrl/tb.v
1: b'%Error: data/full_repos/permissive/489642764/src/wb_ctrl/tb.v:53: syntax error, unexpected \'@\'\n  @ (negedge arst_n);\n  ^\n%Error: data/full_repos/permissive/489642764/src/wb_ctrl/tb.v:56: syntax error, unexpected \'@\'\n  @ (posedge arst_n);\n  ^\n%Error: data/full_repos/permissive/489642764/src/wb_ctrl/tb.v:59: syntax error, unexpected \'@\'\n   @ ( posedge clk50 );\n   ^\n%Error: data/full_repos/permissive/489642764/src/wb_ctrl/tb.v:66: syntax error, unexpected \'@\'\n    @ (posedge clk50);\n    ^\n%Error: data/full_repos/permissive/489642764/src/wb_ctrl/tb.v:70: syntax error, unexpected \'@\'\n    @ (posedge clk50);\n    ^\n%Error: data/full_repos/permissive/489642764/src/wb_ctrl/tb.v:73: syntax error, unexpected \'@\'\n   @ (posedge clk50);\n   ^\n%Error: data/full_repos/permissive/489642764/src/wb_ctrl/tb.v:80: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("dump.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/489642764/src/wb_ctrl/tb.v:81: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(1, dut);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/489642764/src/wb_ctrl/tb.v:83: syntax error, unexpected \'@\'\n   @ ( posedge clk50 );\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/489642764/src/wb_ctrl/tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n  #(1.24 * 2000);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/489642764/src/wb_ctrl/tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n  #(18.9 * 2000);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489642764/src/wb_ctrl/tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n  #(2000/2);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489642764/src/wb_ctrl/tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n  #(2000/2);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489642764/src/wb_ctrl/tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n  #(800/2);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489642764/src/wb_ctrl/tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n  #(800/2);\n  ^\n%Error: Exiting due to 9 error(s), 6 warning(s)\n'
module clk_gen(
	output arst_n,
	output clk50,
	output clk125,
	output clk50_srst_n,
	output clk125_srst_n
);
	reg arst_n_r;
	reg clk50_r;
	reg clk125_r;
	reg clk50_srst_n_r;
	reg clk125_srst_n_r;
	assign arst_n = arst_n_r;
	assign clk50 = clk50_r;
	assign clk125 = clk125_r;
	assign clk50_srst_n = clk50_srst_n_r;
	assign clk125_srst_n = clk125_srst_n_r;
	initial begin
		arst_n_r = 1'b1;
		#(1.24 * 2000);
		arst_n_r = 1'b0;
		#(18.9 * 2000);
		arst_n_r = 1'b1;
	end
	always begin
		clk50_r = 0;
		#(2000/2);
		clk50_r = 1;
		#(2000/2);
	end
	always begin
		clk125_r = 0;
		#(800/2);
		clk125_r = 1;
		#(800/2);
	end
	always @ (posedge clk50_r or negedge arst_n_r) begin
		if (! arst_n_r) begin
			clk50_srst_n_r <= 1'b0;
		end else begin
			clk50_srst_n_r <= 1'b1;
		end
	end
	always @ (posedge clk125_r or negedge arst_n_r) begin
		if (! arst_n_r) begin
			clk125_srst_n_r <= 1'b0;
		end else begin
			clk125_srst_n_r <= 1'b1;
		end
	end
endmodule
module clk_gen(
	output arst_n,
	output clk50,
	output clk125,
	output clk50_srst_n,
	output clk125_srst_n
);

	reg arst_n_r;
	reg clk50_r;
	reg clk125_r;
	reg clk50_srst_n_r;
	reg clk125_srst_n_r;
	assign arst_n = arst_n_r;
	assign clk50 = clk50_r;
	assign clk125 = clk125_r;
	assign clk50_srst_n = clk50_srst_n_r;
	assign clk125_srst_n = clk125_srst_n_r;
	initial begin
		arst_n_r = 1'b1;
		#(1.24 * 2000);
		arst_n_r = 1'b0;
		#(18.9 * 2000);
		arst_n_r = 1'b1;
	end
	always begin
		clk50_r = 0;
		#(2000/2);
		clk50_r = 1;
		#(2000/2);
	end
	always begin
		clk125_r = 0;
		#(800/2);
		clk125_r = 1;
		#(800/2);
	end
	always @ (posedge clk50_r or negedge arst_n_r) begin
		if (! arst_n_r) begin
			clk50_srst_n_r <= 1'b0;
		end else begin
			clk50_srst_n_r <= 1'b1;
		end
	end
	always @ (posedge clk125_r or negedge arst_n_r) begin
		if (! arst_n_r) begin
			clk125_srst_n_r <= 1'b0;
		end else begin
			clk125_srst_n_r <= 1'b1;
		end
	end
endmodule