data/full_repos/permissive/428819669/fastInvSqrt.v
1: b'%Error: data/full_repos/permissive/428819669/fastInvSqrt.v:24: Cannot find file containing module: \'fpu_16bit\'\n    fpu_16bit u00 (fpuOFUF, fpuDone, fpuResult, compResult, xOp, yOp, opcode, fpuReset, clk);\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/428819669,data/full_repos/permissive/428819669/fpu_16bit\n             data/full_repos/permissive/428819669,data/full_repos/permissive/428819669/fpu_16bit.v\n             data/full_repos/permissive/428819669,data/full_repos/permissive/428819669/fpu_16bit.sv\n             fpu_16bit\n             fpu_16bit.v\n             fpu_16bit.sv\n             obj_dir/fpu_16bit\n             obj_dir/fpu_16bit.v\n             obj_dir/fpu_16bit.sv\n%Warning-WIDTH: data/full_repos/permissive/428819669/fastInvSqrt.v:29: Operator SHIFTR expects 17 bits on the LHS, but LHS\'s VARREF \'Xin\' generates 16 bits.\n                                                                     : ... In instance fastInvSqrt\n        bitHack = 16\'h59BB - (Xin >> 1);\n                                  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/428819669/fastInvSqrt.v:78: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'bitHack\' generates 17 bits.\n                                                                     : ... In instance fastInvSqrt\n                            xOp <= bitHack;\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/428819669/fastInvSqrt.v:79: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'bitHack\' generates 17 bits.\n                                                                     : ... In instance fastInvSqrt\n                            yOp <= bitHack;\n                                ^~\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module fastInvSqrt (
    output reg [1:0] OFUF,
    output reg done,
    output reg [15:0] result,
    input [15:0] Xin,
    input reset, clk
    );

    wire [1:0] fpuOFUF;
    wire [2:0] compResult;
    wire fpuDone;
    wire [15:0] fpuResult;

    reg [3:0] state;
    reg [15:0] xOp, yOp;

    reg fpuReset;
    reg [1:0] opcode;

    reg [15:0] xHalf;
    reg [5:0] expSub;
    reg [16:0] bitHack;

    fpu_16bit u00 (fpuOFUF, fpuDone, fpuResult, compResult, xOp, yOp, opcode, fpuReset, clk);

    always @ (*) begin
        expSub = {1'b0, Xin[14:10]} - 1;
        xHalf = {Xin[15], expSub[4:0], Xin[9:0]};
        bitHack = 16'h59BB - (Xin >> 1);
    end

    always @ (posedge clk or posedge reset) begin
        if (reset) begin
            state <= 0;
            OFUF <= 2'b00;
            done <= 0;
        end 
        else if (fpuOFUF == 2'b10 || fpuOFUF == 2'b01) begin
            OFUF <= fpuOFUF;
            state <= 9;
        end
        else begin
            case (state)
                0: begin
                    if (Xin == 16'b0) begin
                        state <= 1;
                        OFUF <= 2'b10;
                        done <= 1;
                    end 
                    else if (Xin == 16'h3C00) begin
                        result <= 16'h3C00;
                        done <= 1;
                        state <= 2;
                    end 
                    else begin
                        state <= 3;
                    end
                end
                1: begin
                    state <= 1;
                    done <= 1;
                end
                2: begin
                    state <= 2;
                    done <= 1;
                end
                3: begin
                    if (Xin[14:10] == 0) begin
                        OFUF <= 2'b01;
                        state <= 9;
                    end
                    else begin
                        if (bitHack[16] == 1'b1) begin
                            OFUF <= 2'b10;
                            state <= 9;
                        end
                        else begin
                            xOp <= bitHack;
                            yOp <= bitHack;
                            opcode <= 2;
                            fpuReset <= 1;
                            state <= 4;
                        end
                    end
                end
                4: begin
                    fpuReset <= 0;
                    if (fpuDone) begin
                        yOp <= fpuResult;
                        xOp <= xHalf[15:0]; 
                        opcode <= 2;
                        fpuReset <= 1;
                        state <= 5;
                    end
                    else
                        state <= 4;
                end
                5: begin
                    fpuReset <= 0;
                    if (fpuDone) begin
                        yOp <= fpuResult;
                        xOp <= 16'h3E00;
                        opcode <= 1;
                        fpuReset <= 1;
                        state <= 6;
                    end
                    else
                        state <= 5;
                end
                6: begin
                    fpuReset <= 0;
                    if (fpuDone) begin
                        yOp <= fpuResult;
                        xOp <= bitHack[15:0]; 
                        opcode <= 2;
                        fpuReset <= 1;
                        state <= 7;
                    end
                    else
                        state <= 6;
                end
                7: begin
                    fpuReset <= 0;
                    if (fpuDone) begin
                        result <= fpuResult;
                        done <= 1;
                        state <= 8;
                    end
                    else
                        state <= 7;
                end
                8: begin
                    done <= 1;
                    state <= 8;
                end
                9: begin
                    state <= 9;
                    done <= 1;
                end
                default: begin
                    state <= 0;
                end
            endcase
        end
    end

    
endmodule
module fastInvSqrt (
    output reg [1:0] OFUF,
    output reg done,
    output reg [15:0] result,
    input [15:0] Xin,
    input reset, clk
    );


    wire [1:0] fpuOFUF;
    wire [2:0] compResult;
    wire fpuDone;
    wire [15:0] fpuResult;

    reg [3:0] state;
    reg [15:0] xOp, yOp;

    reg fpuReset;
    reg [1:0] opcode;

    reg [15:0] xHalf;
    reg [5:0] expSub;
    reg [16:0] bitHack;

    fpu_16bit u00 (fpuOFUF, fpuDone, fpuResult, compResult, xOp, yOp, opcode, fpuReset, clk);

    always @ (*) begin
        expSub = {1'b0, Xin[14:10]} - 1;
        xHalf = {Xin[15], expSub[4:0], Xin[9:0]};
        bitHack = 16'h59BB - (Xin >> 1);
    end

    always @ (posedge clk or posedge reset) begin
        if (reset) begin
            state <= 0;
            OFUF <= 2'b00;
            done <= 0;
        end 
        else if (fpuOFUF == 2'b10 || fpuOFUF == 2'b01) begin
            OFUF <= fpuOFUF;
            state <= 9;
        end
        else begin
            case (state)
                0: begin
                    if (Xin == 16'b0) begin
                        state <= 1;
                        OFUF <= 2'b10;
                        done <= 1;
                    end 
                    else if (Xin == 16'h3C00) begin
                        result <= 16'h3C00;
                        done <= 1;
                        state <= 2;
                    end 
                    else begin
                        state <= 3;
                    end
                end
                1: begin
                    state <= 1;
                    done <= 1;
                end
                2: begin
                    state <= 2;
                    done <= 1;
                end
                3: begin
                    if (Xin[14:10] == 0) begin
                        OFUF <= 2'b01;
                        state <= 9;
                    end
                    else begin
                        if (bitHack[16] == 1'b1) begin
                            OFUF <= 2'b10;
                            state <= 9;
                        end
                        else begin
                            xOp <= bitHack;
                            yOp <= bitHack;
                            opcode <= 2;
                            fpuReset <= 1;
                            state <= 4;
                        end
                    end
                end
                4: begin
                    fpuReset <= 0;
                    if (fpuDone) begin
                        yOp <= fpuResult;
                        xOp <= xHalf[15:0]; 
                        opcode <= 2;
                        fpuReset <= 1;
                        state <= 5;
                    end
                    else
                        state <= 4;
                end
                5: begin
                    fpuReset <= 0;
                    if (fpuDone) begin
                        yOp <= fpuResult;
                        xOp <= 16'h3E00;
                        opcode <= 1;
                        fpuReset <= 1;
                        state <= 6;
                    end
                    else
                        state <= 5;
                end
                6: begin
                    fpuReset <= 0;
                    if (fpuDone) begin
                        yOp <= fpuResult;
                        xOp <= bitHack[15:0]; 
                        opcode <= 2;
                        fpuReset <= 1;
                        state <= 7;
                    end
                    else
                        state <= 6;
                end
                7: begin
                    fpuReset <= 0;
                    if (fpuDone) begin
                        result <= fpuResult;
                        done <= 1;
                        state <= 8;
                    end
                    else
                        state <= 7;
                end
                8: begin
                    done <= 1;
                    state <= 8;
                end
                9: begin
                    state <= 9;
                    done <= 1;
                end
                default: begin
                    state <= 0;
                end
            endcase
        end
    end

    
endmodule