data/full_repos/permissive/441359809/src/yosys/tests/hana/test_intermout.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_intermout.v:18: Multiple top level modules\n                                                                                                : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                : ... Top module \'f1_test\'\nmodule f1_test(a, b, c, d, z);\n       ^~~~~~~\n                                                                                                : ... Top module \'f2_test\'\nmodule f2_test (in1, in2, out);\n       ^~~~~~~\n                                                                                                : ... Top module \'f3_test\'\nmodule f3_test(a, b, c);\n       ^~~~~~~\n                                                                                                : ... Top module \'f4_test\'\nmodule f4_test(ctrl, in1,  in2, out);\n       ^~~~~~~\n                                                                                                : ... Top module \'f5_NonBlockingEx\'\nmodule f5_NonBlockingEx(clk, merge, er, xmit, fddi, claim);\n       ^~~~~~~~~~~~~~~~\n                                                                                                : ... Top module \'f6_FlipFlop\'\nmodule f6_FlipFlop(clk, cs, ns);\n       ^~~~~~~~~~~\n                                                                                                : ... Top module \'f7_FlipFlop\'\nmodule f7_FlipFlop(clock, cs, ns);\n       ^~~~~~~~~~~\n                                                                                                : ... Top module \'f8_inc\'\nmodule f8_inc(clock, counter);\n       ^~~~~~\n                                                                                                : ... Top module \'f9_NegEdgeClock\'\nmodule f9_NegEdgeClock(q, d, clk, reset);\n       ^~~~~~~~~~~~~~~\n                                                                                                : ... Top module \'f10_MyCounter\'\nmodule f10_MyCounter (clock, preset, updown, presetdata, counter);\n       ^~~~~~~~~~~~~\n                                                                                                : ... Top module \'f11_test\'\nmodule f11_test(en, in, out);\n       ^~~~~~~~\n                                                                                                : ... Top module \'f12_test\'\nmodule f12_test(input in, output out);\n       ^~~~~~~~\n                                                                                                : ... Top module \'f13_test\'\nmodule f13_test(input in, output out);\n       ^~~~~~~~\n                                                                                                : ... Top module \'f14_test\'\nmodule f14_test(in, out);\n       ^~~~~~~~\n                                                                                                : ... Top module \'f15_test\'\nmodule f15_test(in1, in2, out);\n       ^~~~~~~~\n                                                                                                : ... Top module \'f16_test\'\nmodule f16_test(out, in1, in2, vin1, vin2, vout1);\n       ^~~~~~~~\n                                                                                                : ... Top module \'f17_test\'\nmodule f17_test(in1, in2, vin1, vin2, out, vout, vin3, vin4, vout1 );\n       ^~~~~~~~\n                                                                                                : ... Top module \'f18_test\'\nmodule f18_test(output out, input in, output [1:0] vout, input [1:0] vin);\n       ^~~~~~~~\n                                                                                                : ... Top module \'f19_buffer\'\nmodule f19_buffer(in, out, vin, vout);\n       ^~~~~~~~~~\n                                                                                                : ... Top module \'f20_test\'\nmodule f20_test(in1, in2, out,  vin1, vin2, vin3, vin4, vout1, vout2, en1, ven1, ven2);\n       ^~~~~~~~\n                                                                                                : ... Top module \'f21_test\'\nmodule f21_test(in, out, en, vin1, vout1, en1);\n       ^~~~~~~~\n                                                                                                : ... Top module \'f22_test\'\nmodule f22_test(in, out, vin, vout, vin1, vout1, vin2, vout2);\n       ^~~~~~~~\n                                                                                                : ... Top module \'f23_test\'\nmodule f23_test (out, vout);\n       ^~~~~~~~\n                                                                                                : ... Top module \'f24_test\'\nmodule f24_test(out, in1, in2, vin1, vin2, vout1);\n       ^~~~~~~~\n                                                                                                : ... Top module \'f25_test\'\nmodule f25_test(out, vout, in, vin);\n       ^~~~~~~~\n                                                                                                : ... Top module \'f26_test\'\nmodule f26_test(out, in1, in2, vin1, vin2, vout1);\n       ^~~~~~~~\n                                                                                                : ... Top module \'f27_test\'\nmodule f27_test(out, in1, in2, vin1, vin2, vout1);\n       ^~~~~~~~\n                                                                                                : ... Top module \'f28_test\'\nmodule f28_test(output out, input [1:0] vin, output out1, input [3:0] vin1);\n       ^~~~~~~~\n                                                                                                : ... Top module \'f29_Reduction\'\nmodule f29_Reduction (A1, A2, A3, A4, A5, A6, Y1, Y2, Y3, Y4, Y5, Y6);\n       ^~~~~~~~~~~~~\n                                                                                                : ... Top module \'f30_test\'\nmodule f30_test(out, in1, in2, vin1, vin2, vout1);\n       ^~~~~~~~\n                                                                                                : ... Top module \'f31_test\'\nmodule f31_test(output out, input in, output [31:0] vout, input [31:0] vin);\n       ^~~~~~~~\n                                                                                                : ... Top module \'f32_test\'\nmodule f32_test(output out, input in);\n       ^~~~~~~~\n                                                                                                : ... Top module \'f33_test\'\nmodule f33_test(vin0, vout0);\n       ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_intermout.v:392: Operator SUB expects 4 bits on the LHS, but LHS\'s VARREF \'vin1\' generates 2 bits.\n                                                                                              : ... In instance f30_test\nassign vout1 = vin1 - vin2;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_intermout.v:343: Operator MODDIV expects 4 bits on the LHS, but LHS\'s VARREF \'vin1\' generates 2 bits.\n                                                                                              : ... In instance f26_test\nassign vout1 = vin1 % vin2;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_intermout.v:343: Operator MODDIV expects 4 bits on the RHS, but RHS\'s VARREF \'vin2\' generates 3 bits.\n                                                                                              : ... In instance f26_test\nassign vout1 = vin1 % vin2;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_intermout.v:331: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'vin\' generates 4 bits.\n                                                                                              : ... In instance f25_test\nassign vout = !vin;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_intermout.v:322: Operator DIV expects 4 bits on the LHS, but LHS\'s VARREF \'vin1\' generates 2 bits.\n                                                                                              : ... In instance f24_test\nassign vout1 = vin1 / vin2;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_intermout.v:322: Operator DIV expects 4 bits on the RHS, but RHS\'s VARREF \'vin2\' generates 3 bits.\n                                                                                              : ... In instance f24_test\nassign vout1 = vin1 / vin2;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_intermout.v:276: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'ven2\' generates 2 bits.\n                                                                                              : ... In instance f20_test\nassign vout2 = ven2 ? vin3 : vin4;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_intermout.v:244: Logical Operator LOGAND expects 1 bit on the LHS, but LHS\'s VARREF \'vin1\' generates 2 bits.\n                                                                                              : ... In instance f17_test\nassign vout = vin1 && vin2;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_intermout.v:244: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'vin2\' generates 4 bits.\n                                                                                              : ... In instance f17_test\nassign vout = vin1 && vin2;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_intermout.v:245: Logical Operator LOGOR expects 1 bit on the LHS, but LHS\'s VARREF \'vin3\' generates 2 bits.\n                                                                                              : ... In instance f17_test\nassign vout1 = vin3 || vin4;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_intermout.v:245: Logical Operator LOGOR expects 1 bit on the RHS, but RHS\'s VARREF \'vin4\' generates 4 bits.\n                                                                                              : ... In instance f17_test\nassign vout1 = vin3 || vin4;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/hana/test_intermout.v:230: Operator ADD expects 4 bits on the LHS, but LHS\'s VARREF \'vin1\' generates 2 bits.\n                                                                                              : ... In instance f16_test\nassign vout1 = vin1 + vin2;\n                    ^\n%Error: Exiting due to 13 warning(s)\n'
module f15_mybuf(in, out);
input in;
output out;
wire w1, w2, w3, w4;

assign w1 = in;
assign w2 = w1;
assign out = w2;
endmodule
module f15_mybuf(in, out);

input in;
output out;
wire w1, w2, w3, w4;

assign w1 = in;
assign w2 = w1;
assign out = w2;
endmodule