data/full_repos/permissive/445488268/trivium-verilog/cipher_engine.v
1: b"%Error: data/full_repos/permissive/445488268/trivium-verilog/cipher_engine.v:54: Cannot find file containing module: 'shift_reg'\nshift_reg #(\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/445488268/trivium-verilog,data/full_repos/permissive/445488268/shift_reg\n             data/full_repos/permissive/445488268/trivium-verilog,data/full_repos/permissive/445488268/shift_reg.v\n             data/full_repos/permissive/445488268/trivium-verilog,data/full_repos/permissive/445488268/shift_reg.sv\n             shift_reg\n             shift_reg.v\n             shift_reg.sv\n             obj_dir/shift_reg\n             obj_dir/shift_reg.v\n             obj_dir/shift_reg.sv\n%Error: data/full_repos/permissive/445488268/trivium-verilog/cipher_engine.v:70: Cannot find file containing module: 'shift_reg'\nshift_reg #(\n^~~~~~~~~\n%Error: data/full_repos/permissive/445488268/trivium-verilog/cipher_engine.v:86: Cannot find file containing module: 'shift_reg'\nshift_reg #(\n^~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module cipher_engine(

    input   wire            clk_i,
    input   wire            n_rst_i,
    input   wire            ce_i,
    

    input   wire    [31:0]  ld_dat_i,
    input   wire    [2:0]   ld_reg_a_i,
    input   wire    [2:0]   ld_reg_b_i,
    input   wire            dat_i,
    output  wire            dat_o
);




wire    reg_a_out_s;
wire    reg_b_out_s;
wire    reg_c_out_s;
wire    z_a_s;
wire    z_b_s;
wire    z_c_s;
wire    key_stream_s;




shift_reg #(
        .REG_SZ(93),
        .FEED_FWD_IDX(65),
        .FEED_BKWD_IDX(68)
    ) 
    reg_a(
        .clk_i(clk_i),
        .n_rst_i(n_rst_i),
        .ce_i(ce_i),
        .ld_i(ld_reg_a_i),
        .ld_dat_i(ld_dat_i),
        .dat_i(reg_c_out_s),
        .dat_o(reg_a_out_s),
        .z_o(z_a_s)
    );
   
shift_reg #(
        .REG_SZ(84),
        .FEED_FWD_IDX(68),
        .FEED_BKWD_IDX(77)
    ) 
    reg_b(
        .clk_i(clk_i),
        .n_rst_i(n_rst_i),
        .ce_i(ce_i),
        .ld_i(ld_reg_b_i),
        .ld_dat_i(ld_dat_i),
        .dat_i(reg_a_out_s),
        .dat_o(reg_b_out_s),
        .z_o(z_b_s)
    );
   
shift_reg #(
        .REG_SZ(111),
        .FEED_FWD_IDX(65),
        .FEED_BKWD_IDX(86)
    ) 
    reg_c(
        .clk_i(clk_i),
        .n_rst_i(n_rst_i),
        .ce_i(ce_i),
        .ld_i(ld_reg_b_i),
        .ld_dat_i(0),
        .dat_i(reg_b_out_s),
        .dat_o(reg_c_out_s),
        .z_o(z_c_s)
    );
   



assign key_stream_s = z_a_s ^ z_b_s ^ z_c_s;
assign dat_o = dat_i ^ key_stream_s;

endmodule
module cipher_engine(

    input   wire            clk_i,
    input   wire            n_rst_i,
    input   wire            ce_i,
    

    input   wire    [31:0]  ld_dat_i,
    input   wire    [2:0]   ld_reg_a_i,
    input   wire    [2:0]   ld_reg_b_i,
    input   wire            dat_i,
    output  wire            dat_o
);





wire    reg_a_out_s;
wire    reg_b_out_s;
wire    reg_c_out_s;
wire    z_a_s;
wire    z_b_s;
wire    z_c_s;
wire    key_stream_s;




shift_reg #(
        .REG_SZ(93),
        .FEED_FWD_IDX(65),
        .FEED_BKWD_IDX(68)
    ) 
    reg_a(
        .clk_i(clk_i),
        .n_rst_i(n_rst_i),
        .ce_i(ce_i),
        .ld_i(ld_reg_a_i),
        .ld_dat_i(ld_dat_i),
        .dat_i(reg_c_out_s),
        .dat_o(reg_a_out_s),
        .z_o(z_a_s)
    );
   
shift_reg #(
        .REG_SZ(84),
        .FEED_FWD_IDX(68),
        .FEED_BKWD_IDX(77)
    ) 
    reg_b(
        .clk_i(clk_i),
        .n_rst_i(n_rst_i),
        .ce_i(ce_i),
        .ld_i(ld_reg_b_i),
        .ld_dat_i(ld_dat_i),
        .dat_i(reg_a_out_s),
        .dat_o(reg_b_out_s),
        .z_o(z_b_s)
    );
   
shift_reg #(
        .REG_SZ(111),
        .FEED_FWD_IDX(65),
        .FEED_BKWD_IDX(86)
    ) 
    reg_c(
        .clk_i(clk_i),
        .n_rst_i(n_rst_i),
        .ce_i(ce_i),
        .ld_i(ld_reg_b_i),
        .ld_dat_i(0),
        .dat_i(reg_b_out_s),
        .dat_o(reg_c_out_s),
        .z_o(z_c_s)
    );
   



assign key_stream_s = z_a_s ^ z_b_s ^ z_c_s;
assign dat_o = dat_i ^ key_stream_s;

endmodule