data/full_repos/permissive/441359809/src/yosys/tests/various/pmux2shiftx.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/tests/various/pmux2shiftx.v:36: Multiple top level modules\n                                                                                                : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                : ... Top module \'pmux2shiftx_test\'\nmodule pmux2shiftx_test (\n       ^~~~~~~~~~~~~~~~\n                                                                                                : ... Top module \'issue01135\'\nmodule issue01135(input [7:0] i, output reg o);\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/various/pmux2shiftx.v:5: Duplicate declaration of signal: \'D\'\n input [9:0] A, B, C, D, D, E, F, G, H,\n                         ^\n        data/full_repos/permissive/441359809/src/yosys/tests/various/pmux2shiftx.v:5: ... Location of original declaration\n input [9:0] A, B, C, D, D, E, F, G, H,\n                      ^\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/various/pmux2shiftx.v:5: Duplicate declaration of port: \'D\'\n input [9:0] A, B, C, D, D, E, F, G, H,\n                         ^\n        data/full_repos/permissive/441359809/src/yosys/tests/various/pmux2shiftx.v:5: ... Location of original declaration\n input [9:0] A, B, C, D, D, E, F, G, H,\n                      ^\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module issue01135(input [7:0] i, output reg o);
always @*
case (i[6:3])
    4: o <= i[0];
    3: o <= i[2];
    7: o <= i[3];
    default: o <= 1'b0;
endcase
endmodule
module issue01135(input [7:0] i, output reg o);

always @*
case (i[6:3])
    4: o <= i[0];
    3: o <= i[2];
    7: o <= i[3];
    default: o <= 1'b0;
endcase
endmodule