data/full_repos/permissive/52703097/mux.test.v
1: b'%Error: data/full_repos/permissive/52703097/mux.test.v:1: Cannot find include file: mux.v\n`include "mux.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52703097,data/full_repos/permissive/52703097/mux.v\n             data/full_repos/permissive/52703097,data/full_repos/permissive/52703097/mux.v.v\n             data/full_repos/permissive/52703097,data/full_repos/permissive/52703097/mux.v.sv\n             mux.v\n             mux.v.v\n             mux.v.sv\n             obj_dir/mux.v\n             obj_dir/mux.v.v\n             obj_dir/mux.v.sv\n%Error: data/full_repos/permissive/52703097/mux.test.v:18: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("dump.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/52703097/mux.test.v:19: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/52703097/mux.test.v:32: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk_reg <= ~clk_reg;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/52703097/mux.test.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #1 corr_res <= data[select];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/52703097/mux.test.v:43: Unsupported: Ignoring delay on this delayed statement.\n            #10 $finish;\n            ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n'
module test;

    reg[`WIDTH-1:0] data;
    reg[`CHANNELS-1:0] select;
    wire result;

    initial begin
        $dumpfile("dump.vcd");
        $dumpvars;
        data = $random;
        $display("Data = %b", data);
        select = 0;
    end

    reg clk_reg = 1'b0;
    reg corr_res = 1'b0;
    wire clk;
    assign clk = clk_reg;

    mux #(.width(`WIDTH), .channels(`CHANNELS)) uut(data, select, result);

    always #5 clk_reg <= ~clk_reg;

    always @(negedge clk) begin
        if (corr_res != result)
            $display("Incorrect result");
    end

    always @(posedge clk) begin
        select <= select + 1;
        #1 corr_res <= data[select];
        if (select >= `WIDTH - 1)
            #10 $finish;
    end
endmodule
module test;


    reg[`WIDTH-1:0] data;
    reg[`CHANNELS-1:0] select;
    wire result;

    initial begin
        $dumpfile("dump.vcd");
        $dumpvars;
        data = $random;
        $display("Data = %b", data);
        select = 0;
    end

    reg clk_reg = 1'b0;
    reg corr_res = 1'b0;
    wire clk;
    assign clk = clk_reg;

    mux #(.width(`WIDTH), .channels(`CHANNELS)) uut(data, select, result);

    always #5 clk_reg <= ~clk_reg;

    always @(negedge clk) begin
        if (corr_res != result)
            $display("Incorrect result");
    end

    always @(posedge clk) begin
        select <= select + 1;
        #1 corr_res <= data[select];
        if (select >= `WIDTH - 1)
            #10 $finish;
    end
endmodule