data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vfalu/rtl/aq_fcnvt_scalar_dp.v
1: b"%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vfalu/rtl/aq_fcnvt_scalar_dp.v:686: Cannot find file containing module: 'aq_vdsp_64_bit_ff1'\naq_vdsp_64_bit_ff1  x_aq_vdsp_64_bit_ff1 (\n^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vfalu/rtl,data/full_repos/permissive/418750043/aq_vdsp_64_bit_ff1\n             data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vfalu/rtl,data/full_repos/permissive/418750043/aq_vdsp_64_bit_ff1.v\n             data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vfalu/rtl,data/full_repos/permissive/418750043/aq_vdsp_64_bit_ff1.sv\n             aq_vdsp_64_bit_ff1\n             aq_vdsp_64_bit_ff1.v\n             aq_vdsp_64_bit_ff1.sv\n             obj_dir/aq_vdsp_64_bit_ff1\n             obj_dir/aq_vdsp_64_bit_ff1.v\n             obj_dir/aq_vdsp_64_bit_ff1.sv\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vfalu/rtl/aq_fcnvt_scalar_dp.v:895: Cannot find file containing module: 'aq_left_shift_64'\naq_left_shift_64  x_aq_left_shift_64 (\n^~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module aq_fcnvt_scalar_dp(
  bhalf0_final_frac,
  cp0_vpu_xx_bf16,
  double_final_frac,
  double_pipe_bhtod_value,
  double_pipe_bhtox_expnt,
  double_pipe_ex1_special_vld,
  double_pipe_ex1_src_cnan,
  double_pipe_ex1_src_inf,
  double_pipe_ex1_src_qnan,
  double_pipe_ex1_src_snan,
  double_pipe_ex1_src_zero,
  double_pipe_ex2_expt,
  double_pipe_ex2_frac,
  double_pipe_ex2_int,
  double_pipe_ex2_widden_dn_itof_expnt,
  double_pipe_ftoi_int,
  double_pipe_htox_expnt,
  double_pipe_htox_value,
  double_pipe_special_value,
  double_pipe_src_dn,
  double_pipe_stod_expnt,
  double_pipe_stod_value,
  ex1_dest_bhalf,
  ex1_dest_float,
  ex1_dest_half,
  ex1_dest_si,
  ex1_dest_single,
  ex1_double_src,
  ex1_half0_src,
  ex1_l8_0_src,
  ex1_op_bhtod,
  ex1_op_bhtos,
  ex1_op_dtobh,
  ex1_op_dtoh,
  ex1_op_dtos,
  ex1_op_ftoi,
  ex1_op_htod,
  ex1_op_htos,
  ex1_op_stobh,
  ex1_op_stod,
  ex1_op_stoh,
  ex1_single0_src,
  ex1_src_bhalf,
  ex1_src_double,
  ex1_src_float,
  ex1_src_half,
  ex1_src_i,
  ex1_src_l16,
  ex1_src_l32,
  ex1_src_l64,
  ex1_src_l8,
  ex1_src_si,
  ex1_src_single,
  ex2_bh_quod_up,
  ex2_bhalf0_orig_frac,
  ex2_dest_bhalf,
  ex2_dest_double,
  ex2_dest_float,
  ex2_dest_half,
  ex2_dest_l16,
  ex2_dest_l32,
  ex2_dest_l64,
  ex2_dest_l8,
  ex2_dest_si,
  ex2_dest_single,
  ex2_double_orig_frac,
  ex2_h_quod_up,
  ex2_half0_orig_frac,
  ex2_int16_0_result,
  ex2_int32_0_result,
  ex2_int64_result,
  ex2_l16_0_result,
  ex2_l32_0_result,
  ex2_l8_0_result,
  ex2_narrow,
  ex2_op_itof,
  ex2_quod_dn,
  ex2_single0_orig_frac,
  ex2_src_l16,
  ex2_src_l32,
  ex2_src_l64,
  ex2_widden,
  ex3_double_result,
  fcnvt_ex1_pipe_clk,
  fcnvt_ex1_pipedown,
  fcnvt_ex2_pipe_clk,
  fcnvt_ex2_pipedown,
  half0_final_frac,
  ifu_vpu_warm_up,
  l16_0_itof_value,
  l32_0_itof_value,
  l64_itof_value,
  single0_final_frac,
  vfcvt_vpu_ex2_gpr_result,
  vfcvt_vpu_ex3_fflags,
  vfcvt_vpu_ex3_fpr_result,
  vpu_group_1_xx_ex1_func,
  vpu_group_1_xx_ex1_srcv0,
  vpu_group_1_xx_ex1_srcv0_type,
  vpu_group_1_xx_ex1_srcv1
);


input   [15:0]  bhalf0_final_frac;                   
input           cp0_vpu_xx_bf16;                     
input   [63:0]  double_final_frac;                   
input           double_pipe_ex1_special_vld;         
input   [3 :0]  double_pipe_ex2_expt;                
input   [63:0]  double_pipe_ftoi_int;                
input   [63:0]  ex2_int16_0_result;                  
input   [63:0]  ex2_int32_0_result;                  
input   [63:0]  ex2_int64_result;                    
input   [63:0]  ex2_l16_0_result;                    
input   [63:0]  ex2_l32_0_result;                    
input   [7 :0]  ex2_l8_0_result;                     
input   [63:0]  ex3_double_result;                   
input           fcnvt_ex1_pipe_clk;                  
input           fcnvt_ex1_pipedown;                  
input           fcnvt_ex2_pipe_clk;                  
input           fcnvt_ex2_pipedown;                  
input   [15:0]  half0_final_frac;                    
input           ifu_vpu_warm_up;                     
input   [31:0]  single0_final_frac;                  
input   [19:0]  vpu_group_1_xx_ex1_func;             
input   [63:0]  vpu_group_1_xx_ex1_srcv0;            
input   [47:0]  vpu_group_1_xx_ex1_srcv0_type;       
input   [63:0]  vpu_group_1_xx_ex1_srcv1;            
output  [5 :0]  double_pipe_bhtod_value;             
output  [4 :0]  double_pipe_bhtox_expnt;             
output          double_pipe_ex1_src_cnan;            
output          double_pipe_ex1_src_inf;             
output          double_pipe_ex1_src_qnan;            
output          double_pipe_ex1_src_snan;            
output          double_pipe_ex1_src_zero;            
output  [63:0]  double_pipe_ex2_frac;                
output  [63:0]  double_pipe_ex2_int;                 
output  [5 :0]  double_pipe_ex2_widden_dn_itof_expnt; 
output  [4 :0]  double_pipe_htox_expnt;              
output  [8 :0]  double_pipe_htox_value;              
output  [63:0]  double_pipe_special_value;           
output          double_pipe_src_dn;                  
output  [4 :0]  double_pipe_stod_expnt;              
output  [21:0]  double_pipe_stod_value;              
output          ex1_dest_bhalf;                      
output          ex1_dest_float;                      
output          ex1_dest_half;                       
output          ex1_dest_si;                         
output          ex1_dest_single;                     
output  [63:0]  ex1_double_src;                      
output  [15:0]  ex1_half0_src;                       
output  [7 :0]  ex1_l8_0_src;                        
output          ex1_op_bhtod;                        
output          ex1_op_bhtos;                        
output          ex1_op_dtobh;                        
output          ex1_op_dtoh;                         
output          ex1_op_dtos;                         
output          ex1_op_ftoi;                         
output          ex1_op_htod;                         
output          ex1_op_htos;                         
output          ex1_op_stobh;                        
output          ex1_op_stod;                         
output          ex1_op_stoh;                         
output  [31:0]  ex1_single0_src;                     
output          ex1_src_bhalf;                       
output          ex1_src_double;                      
output          ex1_src_float;                       
output          ex1_src_half;                        
output          ex1_src_i;                           
output          ex1_src_l16;                         
output          ex1_src_l32;                         
output          ex1_src_l64;                         
output          ex1_src_l8;                          
output          ex1_src_si;                          
output          ex1_src_single;                      
output          ex2_bh_quod_up;                      
output  [6 :0]  ex2_bhalf0_orig_frac;                
output          ex2_dest_bhalf;                      
output          ex2_dest_double;                     
output          ex2_dest_float;                      
output          ex2_dest_half;                       
output          ex2_dest_l16;                        
output          ex2_dest_l32;                        
output          ex2_dest_l64;                        
output          ex2_dest_l8;                         
output          ex2_dest_si;                         
output          ex2_dest_single;                     
output  [51:0]  ex2_double_orig_frac;                
output          ex2_h_quod_up;                       
output  [9 :0]  ex2_half0_orig_frac;                 
output          ex2_narrow;                          
output          ex2_op_itof;                         
output          ex2_quod_dn;                         
output  [22:0]  ex2_single0_orig_frac;               
output          ex2_src_l16;                         
output          ex2_src_l32;                         
output          ex2_src_l64;                         
output          ex2_widden;                          
output  [15:0]  l16_0_itof_value;                    
output  [31:0]  l32_0_itof_value;                    
output  [63:0]  l64_itof_value;                      
output  [63:0]  vfcvt_vpu_ex2_gpr_result;            
output  [4 :0]  vfcvt_vpu_ex3_fflags;                
output  [63:0]  vfcvt_vpu_ex3_fpr_result;            


reg             ex2_bh_quod_up;                      
reg     [63:0]  ex2_comb_frac;                       
reg     [63:0]  ex2_combin_src;                      
reg             ex2_dest_bhalf_flop;                 
reg             ex2_dest_float;                      
reg             ex2_dest_l16;                        
reg             ex2_dest_l32;                        
reg             ex2_dest_l64;                        
reg             ex2_dest_l8;                         
reg             ex2_dest_si;                         
reg             ex2_h_quod_up;                       
reg     [5 :0]  ex2_left_shift_bit;                  
reg             ex2_narrow;                          
reg             ex2_op_itof;                         
reg             ex2_quod_dn;                         
reg             ex2_src_l16;                         
reg             ex2_src_l32;                         
reg             ex2_src_l64;                         
reg             ex2_src_l8;                          
reg             ex2_widden;                          
reg             ex3_dest_l64;                        
reg     [3 :0]  ex3_expt;                            
reg     [63:0]  ex3_result;                          


wire    [15:0]  bhalf0_final_frac;                   
wire    [63:0]  bhalf0_for_ff1;                      
wire    [15:0]  bhalf0_frac_for_shift;               
wire    [5 :0]  bhtod_shift_bit;                     
wire            cnvt_src0_half0_id;                  
wire            cnvt_src0_half0_inf;                 
wire            cnvt_src0_half0_qnan;                
wire            cnvt_src0_half0_snan;                
wire            cnvt_src0_half0_zero;                
wire            cp0_vpu_xx_bf16;                     
wire            cur_l16;                             
wire            cur_l32;                             
wire            cur_l64;                             
wire            cur_l8;                              
wire    [63:0]  double_final_frac;                   
wire    [5 :0]  double_pipe_bhtod_value;             
wire    [4 :0]  double_pipe_bhtox_expnt;             
wire            double_pipe_ex1_special_vld;         
wire            double_pipe_ex1_src_cnan;            
wire            double_pipe_ex1_src_inf;             
wire            double_pipe_ex1_src_qnan;            
wire            double_pipe_ex1_src_snan;            
wire            double_pipe_ex1_src_zero;            
wire    [3 :0]  double_pipe_ex2_expt;                
wire    [63:0]  double_pipe_ex2_frac;                
wire    [63:0]  double_pipe_ex2_int;                 
wire    [5 :0]  double_pipe_ex2_itof_expnt;          
wire    [5 :0]  double_pipe_ex2_widden_dn_itof_expnt; 
wire    [5 :0]  double_pipe_ex2_xtod_expnt;          
wire    [63:0]  double_pipe_ftoi_int;                
wire    [4 :0]  double_pipe_htox_expnt;              
wire    [8 :0]  double_pipe_htox_value;              
wire    [63:0]  double_pipe_special_value;           
wire            double_pipe_src_dn;                  
wire    [4 :0]  double_pipe_stod_expnt;              
wire    [21:0]  double_pipe_stod_value;              
wire            ex1_bh_quod_up;                      
wire    [63:0]  ex1_combined_src;                    
wire            ex1_dest_bhalf;                      
wire            ex1_dest_double;                     
wire            ex1_dest_float;                      
wire            ex1_dest_half;                       
wire            ex1_dest_l16;                        
wire            ex1_dest_l32;                        
wire            ex1_dest_l64;                        
wire            ex1_dest_l8;                         
wire            ex1_dest_si;                         
wire            ex1_dest_single;                     
wire            ex1_dest_widden;                     
wire    [63:0]  ex1_double_src;                      
wire    [63:0]  ex1_final_norm_frac;                 
wire    [5 :0]  ex1_float_shift_bit;                 
wire    [63:0]  ex1_float_src_tail;                  
wire    [63:0]  ex1_ftoi_int;                        
wire            ex1_h_quod_up;                       
wire    [15:0]  ex1_half0_src;                       
wire    [5 :0]  ex1_itof_shift_bit;                  
wire            ex1_l16_0_src_neg;                   
wire            ex1_l32_0_src_neg;                   
wire            ex1_l64_0_src_neg;                   
wire    [7 :0]  ex1_l8_0_src;                        
wire    [5 :0]  ex1_left_shift_bit;                  
wire            ex1_narrow;                          
wire    [63:0]  ex1_norm_neg_src;                    
wire    [63:0]  ex1_norm_src;                        
wire            ex1_op_bhtod;                        
wire            ex1_op_bhtos;                        
wire            ex1_op_dtobh;                        
wire            ex1_op_dtoh;                         
wire            ex1_op_dtos;                         
wire            ex1_op_ftoi;                         
wire            ex1_op_htod;                         
wire            ex1_op_htos;                         
wire            ex1_op_itof;                         
wire            ex1_op_stobh;                        
wire            ex1_op_stod;                         
wire            ex1_op_stoh;                         
wire            ex1_quod_dn;                         
wire            ex1_quod_up;                         
wire            ex1_same;                            
wire            ex1_sign;                            
wire    [31:0]  ex1_single0_src;                     
wire    [3 :0]  ex1_size;                            
wire            ex1_special_vld;                     
wire            ex1_src_bhalf;                       
wire            ex1_src_double;                      
wire            ex1_src_float;                       
wire            ex1_src_half;                        
wire            ex1_src_i;                           
wire            ex1_src_l16;                         
wire            ex1_src_l32;                         
wire            ex1_src_l64;                         
wire            ex1_src_l8;                          
wire            ex1_src_neg;                         
wire            ex1_src_si;                          
wire            ex1_src_single;                      
wire            ex1_widden;                          
wire    [6 :0]  ex2_bhalf0_orig_frac;                
wire            ex2_dest_bhalf;                      
wire            ex2_dest_double;                     
wire            ex2_dest_half;                       
wire            ex2_dest_single;                     
wire    [51:0]  ex2_double_orig_frac;                
wire    [3 :0]  ex2_expt;                            
wire    [63:0]  ex2_frac;                            
wire    [9 :0]  ex2_half0_orig_frac;                 
wire    [63:0]  ex2_int16_0_result;                  
wire    [63:0]  ex2_int32_0_result;                  
wire    [63:0]  ex2_int64_result;                    
wire    [63:0]  ex2_int_r;                           
wire    [63:0]  ex2_l16_0_result;                    
wire    [63:0]  ex2_l32_0_result;                    
wire    [63:0]  ex2_scalar_int_result;               
wire    [63:0]  ex2_scalar_total_result;             
wire    [63:0]  ex2_shift_src;                       
wire    [22:0]  ex2_single0_orig_frac;               
wire    [63:0]  ex2_total_result;                    
wire    [63:0]  ex3_double_result;                   
wire            fcnvt_ex1_pipe_clk;                  
wire            fcnvt_ex1_pipedown;                  
wire            fcnvt_ex2_pipe_clk;                  
wire            fcnvt_ex2_pipedown;                  
wire    [23:0]  ff1_16_bit;                          
wire    [13:0]  ff1_32_bit;                          
wire    [7 :0]  ff1_64_bit;                          
wire    [39:0]  ff1_8_bit;                           
wire    [63:0]  ff1_src_in;                          
wire    [15:0]  half0_final_frac;                    
wire    [63:0]  half0_for_ff1;                       
wire    [15:0]  half0_frac_for_shift;                
wire    [5 :0]  htox_shift_bit;                      
wire    [5 :0]  i16tof_shift_bit;                    
wire    [5 :0]  i32tof_shift_bit;                    
wire    [5 :0]  i64tof_shift_bit;                    
wire            ifu_vpu_warm_up;                     
wire    [63:0]  int_src_for_shift;                   
wire    [15:0]  l16_0_itof_value;                    
wire    [15:0]  l16_0_shift_out_val;                 
wire    [15:0]  l16_1_shift_out_val;                 
wire    [15:0]  l16_2_shift_out_val;                 
wire    [15:0]  l16_3_shift_out_val;                 
wire    [31:0]  l32_0_itof_value;                    
wire    [31:0]  l32_0_shift_out_val;                 
wire    [31:0]  l32_1_shift_out_val;                 
wire    [63:0]  l64_int_abs_val;                     
wire    [63:0]  l64_itof_value;                      
wire    [63:0]  l64_shift_out_val;                   
wire    [63:0]  neg_adder_op0;                       
wire    [63:0]  neg_adder_op1;                       
wire    [63:0]  neg_result;                          
wire            shift_16;                            
wire    [2 :0]  shift_src_size;                      
wire    [31:0]  single0_final_frac;                  
wire            src0_double_id;                      
wire            src0_double_inf;                     
wire            src0_double_qnan;                    
wire            src0_double_snan;                    
wire            src0_double_zero;                    
wire            src0_half0_cnan;                     
wire            src0_half0_id;                       
wire            src0_half0_inf;                      
wire            src0_half0_qnan;                     
wire            src0_half0_snan;                     
wire            src0_half0_zero;                     
wire            src0_single0_cnan;                   
wire            src0_single0_id;                     
wire            src0_single0_inf;                    
wire            src0_single0_qnan;                   
wire            src0_single0_snan;                   
wire            src0_single0_zero;                   
wire    [47:0]  srcv0_type;                          
wire    [5 :0]  stod_shift_bit;                      
wire    [63:0]  vfcvt_vpu_ex2_gpr_result;            
wire    [4 :0]  vfcvt_vpu_ex3_fflags;                
wire    [63:0]  vfcvt_vpu_ex3_fpr_result;            
wire    [19:0]  vpu_group_1_xx_ex1_func;             
wire    [63:0]  vpu_group_1_xx_ex1_srcv0;            
wire    [47:0]  vpu_group_1_xx_ex1_srcv0_type;       
wire    [63:0]  vpu_group_1_xx_ex1_srcv1;            






















assign ex1_op_ftoi    = !vpu_group_1_xx_ex1_func[1] && vpu_group_1_xx_ex1_func[3];
assign ex1_op_stod    = vpu_group_1_xx_ex1_func[1] && vpu_group_1_xx_ex1_func[3] &&
                        vpu_group_1_xx_ex1_func[6] && ex1_src_l32;
assign ex1_op_dtos    = vpu_group_1_xx_ex1_func[1] && vpu_group_1_xx_ex1_func[3] &&
                        vpu_group_1_xx_ex1_func[5] && ex1_src_l64;
assign ex1_op_htos    = vpu_group_1_xx_ex1_func[1] && vpu_group_1_xx_ex1_func[3] &&
                        vpu_group_1_xx_ex1_func[6] && ex1_src_l16&& !cp0_vpu_xx_bf16; 
assign ex1_op_bhtos    = vpu_group_1_xx_ex1_func[1] && vpu_group_1_xx_ex1_func[3] &&
                        vpu_group_1_xx_ex1_func[6] && ex1_src_l16&& cp0_vpu_xx_bf16;                        
assign ex1_op_stoh    = vpu_group_1_xx_ex1_func[1] && vpu_group_1_xx_ex1_func[3] &&
                        vpu_group_1_xx_ex1_func[5] && ex1_src_l32 && !cp0_vpu_xx_bf16;
assign ex1_op_stobh    = vpu_group_1_xx_ex1_func[1] && vpu_group_1_xx_ex1_func[3] &&
                        vpu_group_1_xx_ex1_func[5] && ex1_src_l32 && cp0_vpu_xx_bf16;
                        
assign ex1_op_itof    = vpu_group_1_xx_ex1_func[1] && !vpu_group_1_xx_ex1_func[3];
assign ex1_op_bhtod   = vpu_group_1_xx_ex1_func[1] && vpu_group_1_xx_ex1_func[3] &&
                        vpu_group_1_xx_ex1_func[8] && ex1_src_bhalf;
assign ex1_op_htod   = vpu_group_1_xx_ex1_func[1] && vpu_group_1_xx_ex1_func[3] &&
                        vpu_group_1_xx_ex1_func[8] && ex1_src_half;
assign ex1_op_dtoh    = vpu_group_1_xx_ex1_func[1] && vpu_group_1_xx_ex1_func[3] &&
                        vpu_group_1_xx_ex1_func[7] && ex1_src_l64 && !cp0_vpu_xx_bf16;
assign ex1_op_dtobh    = vpu_group_1_xx_ex1_func[1] && vpu_group_1_xx_ex1_func[3] &&
                        vpu_group_1_xx_ex1_func[7] && ex1_src_l64 && cp0_vpu_xx_bf16;





assign cur_l64        = vpu_group_1_xx_ex1_func[13:12] == 2'b11;
assign cur_l32        = vpu_group_1_xx_ex1_func[13:12] == 2'b10;
assign cur_l16        = vpu_group_1_xx_ex1_func[13:12] == 2'b01;
assign cur_l8         = vpu_group_1_xx_ex1_func[13:12] == 2'b00;
assign ex1_narrow     = vpu_group_1_xx_ex1_func[5];
assign ex1_same       = vpu_group_1_xx_ex1_func[4];
assign ex1_quod_up    = vpu_group_1_xx_ex1_func[8];
assign ex1_quod_dn    = vpu_group_1_xx_ex1_func[7];

assign ex1_dest_si    = vpu_group_1_xx_ex1_func[1:0] == 2'b00;
assign ex1_dest_widden= vpu_group_1_xx_ex1_func[6];

assign ex1_src_l64    = cur_l64 && ex1_same   ||
                        cur_l32 && ex1_narrow ||
                        cur_l16 && ex1_quod_dn;
assign ex1_src_l32    = cur_l32 && (ex1_same || ex1_widden)  ||
                        cur_l16 && ex1_narrow;
assign ex1_src_l16    = cur_l16 && (ex1_same || ex1_widden || ex1_quod_up)|| cur_l8  &&ex1_narrow;
assign ex1_src_l8     = cur_l8  && ex1_widden;

assign ex1_src_double = ex1_src_l64 && vpu_group_1_xx_ex1_func[3];
assign ex1_src_single = ex1_src_l32 && vpu_group_1_xx_ex1_func[3];
assign ex1_src_half   = ex1_src_l16 && vpu_group_1_xx_ex1_func[3] && !cp0_vpu_xx_bf16;
assign ex1_src_bhalf  = ex1_src_l16 && vpu_group_1_xx_ex1_func[3] && cp0_vpu_xx_bf16;

assign ex1_h_quod_up  = ex1_quod_up && !cp0_vpu_xx_bf16;
assign ex1_bh_quod_up = ex1_quod_up && cp0_vpu_xx_bf16;





assign ex1_src_float  = vpu_group_1_xx_ex1_func[3];
assign ex1_dest_float = vpu_group_1_xx_ex1_func[1];

assign ex1_src_si     = !vpu_group_1_xx_ex1_func[3] && !vpu_group_1_xx_ex1_func[2];
assign ex1_src_i      = !vpu_group_1_xx_ex1_func[3];


assign ex1_dest_l64    = cur_l64 && ex1_same   ||
                         cur_l32 && ex1_widden ||
                         cur_l16 && ex1_quod_up;
assign ex1_dest_l32    = cur_l32 && (ex1_same || ex1_narrow)  ||
                         cur_l16 && ex1_widden;
assign ex1_dest_l16    = cur_l16 && (ex1_same || ex1_narrow || ex1_quod_dn)  ||
                         cur_l8 && ex1_widden;
assign ex1_dest_l8     = cur_l8  && ex1_narrow;

assign ex1_dest_double  = ex1_dest_l64;
assign ex1_dest_single  = ex1_dest_l32;
assign ex1_dest_half    = ex1_dest_l16 && !cp0_vpu_xx_bf16;
assign ex1_dest_bhalf   = ex1_dest_l16 && cp0_vpu_xx_bf16;









assign srcv0_type[47:0]          = vpu_group_1_xx_ex1_srcv0_type[47:0];
assign src0_double_snan    = srcv0_type[47];
assign src0_double_qnan    = srcv0_type[46];
assign src0_double_inf    = srcv0_type[45];
assign src0_double_zero    = srcv0_type[44];
assign src0_double_id    = srcv0_type[43];

assign src0_single0_cnan    = srcv0_type[41];
assign src0_single0_snan    = srcv0_type[40];
assign src0_single0_qnan    = srcv0_type[39];
assign src0_single0_inf    = srcv0_type[38];
assign src0_single0_zero    = srcv0_type[37];
assign src0_single0_id    = srcv0_type[36];

assign src0_half0_cnan    = srcv0_type[27];
assign src0_half0_snan    = srcv0_type[26];
assign src0_half0_qnan    = srcv0_type[25];
assign src0_half0_inf     = srcv0_type[24];
assign src0_half0_zero    = srcv0_type[23];
assign src0_half0_id    = srcv0_type[22];


assign cnvt_src0_half0_inf   = src0_half0_inf;
assign cnvt_src0_half0_snan  = src0_half0_snan;
assign cnvt_src0_half0_qnan  = src0_half0_qnan;
assign cnvt_src0_half0_zero  = src0_half0_zero;
assign cnvt_src0_half0_id    = src0_half0_id;


assign double_pipe_ex1_src_inf      = ex1_src_double && src0_double_inf 
                                      || ex1_src_single && src0_single0_inf 
                                      || (ex1_src_half || ex1_src_bhalf) && cnvt_src0_half0_inf;
assign double_pipe_ex1_src_qnan     = ex1_src_double && src0_double_qnan 
                                      || ex1_src_single && src0_single0_qnan 
                                      || (ex1_src_half || ex1_src_bhalf) && cnvt_src0_half0_qnan;


assign double_pipe_ex1_src_cnan     = ex1_src_single && src0_single0_cnan || (ex1_src_half || ex1_src_bhalf) && src0_half0_cnan;
assign double_pipe_ex1_src_snan     = ex1_src_double && src0_double_snan || ex1_src_single && src0_single0_snan || (ex1_src_half || ex1_src_bhalf) && cnvt_src0_half0_snan;
assign double_pipe_ex1_src_zero     = ex1_src_double && src0_double_zero || ex1_src_single && src0_single0_zero || (ex1_src_half || ex1_src_bhalf) && cnvt_src0_half0_zero;


assign double_pipe_src_dn            = ex1_src_double && src0_double_id  || 
                                       ex1_src_single && src0_single0_id ||
                                       (ex1_src_half||ex1_src_bhalf)   && cnvt_src0_half0_id; 




assign ex1_norm_src[63:0]            = ex1_src_i ? vpu_group_1_xx_ex1_srcv1[63:0] : vpu_group_1_xx_ex1_srcv0[63:0];




assign ex1_double_src[63:0]     = ex1_norm_src[63:0];
assign ex1_single0_src[31:0]    = ex1_norm_src[31:0];
assign ex1_half0_src[15:0]      = ex1_norm_src[15:0];
                                                                 



assign ex1_l8_0_src[7:0]        = 8'b0;











assign ex1_widden                  = ex1_dest_widden;
















































assign ex1_sign                 =   ex1_op_itof && ex1_src_si;
assign ex1_size                 =  {ex1_src_l64,ex1_src_l32,ex1_src_l16,ex1_src_l8};
assign ff1_src_in[63:0]         =   ex1_op_itof ? ex1_norm_src[63:0]
                                                : ex1_float_src_tail[63:0];
assign half0_frac_for_shift[15:0]   = {ex1_norm_src[9:0],6'b0};                                             



assign bhalf0_frac_for_shift[15:0]  = {ex1_norm_src[6:0],9'b0};                                             



assign half0_for_ff1[63:0]          = {48'b0,half0_frac_for_shift[15:0]};
assign bhalf0_for_ff1[63:0]         = {48'b0,bhalf0_frac_for_shift[15:0]};
assign ex1_float_src_tail[63:0]     = {64{ex1_src_l32}}   & {32'b0,ex1_norm_src[22:0],9'b0} |
                                      {64{ex1_src_half}}  & {half0_for_ff1[63:0]}           |
                                      {64{ex1_src_bhalf}} & {bhalf0_for_ff1[63:0]};









aq_vdsp_64_bit_ff1  x_aq_vdsp_64_bit_ff1 (
  .ex1_sign   (ex1_sign  ),
  .ex1_size   (ex1_size  ),
  .ex1_src    (ff1_src_in),
  .ff1_16_bit (ff1_16_bit),
  .ff1_32_bit (ff1_32_bit),
  .ff1_64_bit (ff1_64_bit),
  .ff1_8_bit  (ff1_8_bit )
);






assign  i16tof_shift_bit[5:0]        = {2'b0,ff1_16_bit[3:0]};
assign  i32tof_shift_bit[5:0]        = {1'b0,ff1_32_bit[4:0]};




assign  i64tof_shift_bit[5:0]        = {ff1_64_bit[5:0]};
assign  ex1_itof_shift_bit[5:0]      = {6{ex1_src_l64}} & i64tof_shift_bit[5:0] |
                                       {6{ex1_src_l32}} & i32tof_shift_bit[5:0] |
                                       {6{ex1_src_l16}} & i16tof_shift_bit[5:0];

assign  stod_shift_bit[5:0]          = {1'b0,ff1_32_bit[4:0]};
assign double_pipe_stod_expnt[4:0]    = stod_shift_bit[4:0];

assign  htox_shift_bit[5:0]          = {2'b0,ff1_16_bit[3:0]};

assign bhtod_shift_bit[5:0]          = {2'b0,ff1_16_bit[3:0]};
assign ex1_float_shift_bit[5:0]      = {6{ex1_op_stod}} & stod_shift_bit[5:0] |
                                       {6{ex1_op_htos||
                                          ex1_op_htod}}  & htox_shift_bit[5:0]   |
                                       {6{ex1_op_bhtod}} & bhtod_shift_bit[5:0];
assign double_pipe_bhtox_expnt[4:0]   = {1'b0,bhtod_shift_bit[3:0]};
assign double_pipe_htox_expnt[4:0]    = {1'b0,htox_shift_bit[3:0]};


assign ex1_left_shift_bit[5:0]       = ex1_op_itof ? ex1_itof_shift_bit[5:0]
                                                   : ex1_float_shift_bit[5:0];

assign ex1_norm_neg_src[63:0]  = ~ex1_norm_src[63:0];
assign neg_adder_op0[63:0]     = {64{ex1_src_l64}} & {ex1_norm_neg_src[63:0]} | 
                                 {64{ex1_src_l32}} & {{32{ex1_norm_neg_src[31]}},ex1_norm_neg_src[31:0]} |
                                 {64{ex1_src_l16}} & {{48{ex1_norm_neg_src[15]}},ex1_norm_neg_src[15:0]};
assign neg_adder_op1[63:0]     = 64'b1;

assign neg_result[63:0]        = neg_adder_op0[63:0] + neg_adder_op1[63:0];




assign ex1_l64_0_src_neg       = ex1_norm_src[63] && ex1_src_si;
assign ex1_l32_0_src_neg       = ex1_norm_src[31] && ex1_src_si;
assign ex1_l16_0_src_neg       = ex1_norm_src[15] && ex1_src_si;
assign ex1_src_neg             = ex1_src_l64 && ex1_l64_0_src_neg ||
                                 ex1_src_l32 && ex1_l32_0_src_neg ||
                                 ex1_src_l16 && ex1_l16_0_src_neg;








assign l64_int_abs_val[63:0]   = ex1_src_neg ? neg_result[63:0]  : ex1_norm_src[63:0];





















assign int_src_for_shift[63:0] = l64_int_abs_val[63:0];





assign ex1_ftoi_int[63:0]       = double_pipe_ftoi_int[63:0];


assign ex1_final_norm_frac[63:0] = {64{ex1_dest_double}} & double_final_frac[63:0]   |
                                   {64{ex1_dest_single}} & {32'b0,single0_final_frac[31:0]} |
                                   {64{ex1_dest_half}}   & {48'b0,half0_final_frac[15:0]}   |
                                   {64{ex1_dest_bhalf}}  & {48'b0,bhalf0_final_frac[15:0]};




assign ex1_combined_src[63:0]   = ex1_op_itof ? {int_src_for_shift[63:0]} 
                                              : {ex1_final_norm_frac[63:0]};                                            
assign ex1_special_vld        = double_pipe_ex1_special_vld;
always @(posedge fcnvt_ex1_pipe_clk)
begin
  if(fcnvt_ex1_pipedown && ex1_op_ftoi || ifu_vpu_warm_up) begin

    ex2_combin_src[63:0] <= ex1_ftoi_int[63:0];
  end
end
assign ex2_int_r[63:0]  = ex2_combin_src[63:0];
assign ex2_frac[63:0]   =  ex2_comb_frac[63:0];
assign ex2_shift_src[63:0] = ex2_comb_frac[63:0];


always @(posedge fcnvt_ex1_pipe_clk)
begin
  if(fcnvt_ex1_pipedown && (ex1_dest_float|| ex1_special_vld) || ifu_vpu_warm_up) begin


    ex2_comb_frac[63:0]      <= ex1_combined_src[63:0];
    ex2_left_shift_bit[5:0] <= ex1_left_shift_bit[5:0];
  end
end
always @(posedge fcnvt_ex1_pipe_clk)
begin 
  if(fcnvt_ex1_pipedown || ifu_vpu_warm_up) begin
    ex2_narrow      <= ex1_narrow;
    ex2_widden      <= ex1_widden;
    ex2_quod_dn     <= ex1_quod_dn;
    ex2_h_quod_up   <= ex1_h_quod_up;
    ex2_bh_quod_up  <= ex1_bh_quod_up;
    ex2_op_itof     <= ex1_op_itof;
    ex2_src_l64     <= ex1_src_l64;
    ex2_src_l32     <= ex1_src_l32;
    ex2_src_l16     <= ex1_src_l16;
    ex2_src_l8      <= ex1_src_l8;
    ex2_dest_l64    <= ex1_dest_l64;
    ex2_dest_l32    <= ex1_dest_l32;
    ex2_dest_l16    <= ex1_dest_l16;
    ex2_dest_bhalf_flop  <= ex1_dest_bhalf;
    ex2_dest_l8     <= ex1_dest_l8;
    ex2_dest_float  <= ex1_dest_float;
    ex2_dest_si     <= ex1_dest_si;
  end
end


















assign double_pipe_ex2_itof_expnt[5:0]= ex2_left_shift_bit[5:0];
assign double_pipe_ex2_xtod_expnt[5:0]= {1'b0,ex2_left_shift_bit[4:0]};
assign double_pipe_ex2_widden_dn_itof_expnt[5:0] = ex2_op_itof ? double_pipe_ex2_itof_expnt[5:0]
                                                               : double_pipe_ex2_xtod_expnt[5:0];
                                        

assign ex2_dest_double              =  ex2_dest_l64 && ex2_dest_float;
assign ex2_dest_single              =  ex2_dest_l32 && ex2_dest_float;
assign ex2_dest_half                =  ex2_dest_l16 && ex2_dest_float && !ex2_dest_bhalf;
assign ex2_dest_bhalf               =   ex2_dest_float && ex2_dest_bhalf_flop;



assign double_pipe_ex2_int[63:0]    = ex2_int_r[63:0];

assign double_pipe_ex2_frac[63:0]    = ex2_frac[63:0];



assign ex2_double_orig_frac[51:0]    = ex2_frac[51:0];
assign ex2_single0_orig_frac[22:0]   = ex2_frac[22:0];

assign ex2_half0_orig_frac[9:0]     = ex2_frac[9:0];
assign ex2_bhalf0_orig_frac[6:0]    = ex2_frac[6:0];







assign shift_16             = ex2_src_l16||ex2_src_l8;
assign shift_src_size[2:0]  = {ex2_src_l64,ex2_src_l32,shift_16};





aq_left_shift_64  x_aq_left_shift_64 (
  .input_l16_0_shift_cnt   (ex2_left_shift_bit[3:0]),
  .input_l16_1_shift_cnt   (4'b0                   ),
  .input_l16_2_shift_cnt   (4'b0                   ),
  .input_l16_3_shift_cnt   (4'b0                   ),
  .input_l32_0_shift_cnt   (ex2_left_shift_bit[4:0]),
  .input_l32_1_shift_cnt   (5'b0                   ),
  .input_l64_shift_cnt     (ex2_left_shift_bit[5:0]),
  .input_org_src           (ex2_shift_src          ),
  .input_size              (shift_src_size[2:0]    ),
  .l16_0_shift_out_val     (l16_0_shift_out_val    ),
  .l16_1_shift_out_val     (l16_1_shift_out_val    ),
  .l16_2_shift_out_val     (l16_2_shift_out_val    ),
  .l16_3_shift_out_val     (l16_3_shift_out_val    ),
  .l32_0_shift_out_val     (l32_0_shift_out_val    ),
  .l32_1_shift_out_val     (l32_1_shift_out_val    ),
  .l64_shift_out_val       (l64_shift_out_val      )
);












assign l64_itof_value[63:0]   = l64_shift_out_val[63:0];
assign l32_0_itof_value[31:0] = l32_0_shift_out_val[31:0];
assign l16_0_itof_value[15:0] = l16_0_shift_out_val[15:0];
 
assign double_pipe_stod_value[21:0] = l32_0_shift_out_val[30:9];
assign double_pipe_htox_value[8:0]  = l16_0_shift_out_val[14:6];
assign double_pipe_bhtod_value[5:0] = l16_0_shift_out_val[14:9];



































assign double_pipe_special_value[63:0]    =  ex2_frac[63:0];






assign ex2_scalar_total_result[63:0]    =
                                          {64{ex2_dest_l32}} & {ex2_l32_0_result[63:0]} |
                                          {64{ex2_dest_l16}} & {ex2_l16_0_result[63:0]}; 
assign ex2_scalar_int_result[63:0]      = {64{ex2_dest_l64}} & ex2_int64_result[63:0]     |
                                          {64{ex2_dest_l32}} & {ex2_int32_0_result[63:0]} |
                                          {64{ex2_dest_l16}} & {ex2_int16_0_result[63:0]};       
assign vfcvt_vpu_ex2_gpr_result[63:0]   = ex2_scalar_int_result[63:0];
assign ex2_total_result[63:0]           = ex2_scalar_total_result[63:0];    

assign ex2_expt[3:0]                    = double_pipe_ex2_expt[3:0];
always @(posedge fcnvt_ex2_pipe_clk)
begin
  if(fcnvt_ex2_pipedown) begin
    ex3_result[63:0]     <= ex2_total_result[63:0];
  end
end
always @(posedge fcnvt_ex2_pipe_clk)
begin
  if(fcnvt_ex2_pipedown) begin
    ex3_expt[3:0]      <= ex2_expt[3:0];
    ex3_dest_l64       <= ex2_dest_l64;
  end
end







assign vfcvt_vpu_ex3_fpr_result[63:0]             = ex3_dest_l64 ? ex3_double_result[63:0] : ex3_result[63:0];
assign vfcvt_vpu_ex3_fflags[4:0]                  = {ex3_expt[3],1'b0,ex3_expt[2:0]};







endmodule
module aq_fcnvt_scalar_dp(
  bhalf0_final_frac,
  cp0_vpu_xx_bf16,
  double_final_frac,
  double_pipe_bhtod_value,
  double_pipe_bhtox_expnt,
  double_pipe_ex1_special_vld,
  double_pipe_ex1_src_cnan,
  double_pipe_ex1_src_inf,
  double_pipe_ex1_src_qnan,
  double_pipe_ex1_src_snan,
  double_pipe_ex1_src_zero,
  double_pipe_ex2_expt,
  double_pipe_ex2_frac,
  double_pipe_ex2_int,
  double_pipe_ex2_widden_dn_itof_expnt,
  double_pipe_ftoi_int,
  double_pipe_htox_expnt,
  double_pipe_htox_value,
  double_pipe_special_value,
  double_pipe_src_dn,
  double_pipe_stod_expnt,
  double_pipe_stod_value,
  ex1_dest_bhalf,
  ex1_dest_float,
  ex1_dest_half,
  ex1_dest_si,
  ex1_dest_single,
  ex1_double_src,
  ex1_half0_src,
  ex1_l8_0_src,
  ex1_op_bhtod,
  ex1_op_bhtos,
  ex1_op_dtobh,
  ex1_op_dtoh,
  ex1_op_dtos,
  ex1_op_ftoi,
  ex1_op_htod,
  ex1_op_htos,
  ex1_op_stobh,
  ex1_op_stod,
  ex1_op_stoh,
  ex1_single0_src,
  ex1_src_bhalf,
  ex1_src_double,
  ex1_src_float,
  ex1_src_half,
  ex1_src_i,
  ex1_src_l16,
  ex1_src_l32,
  ex1_src_l64,
  ex1_src_l8,
  ex1_src_si,
  ex1_src_single,
  ex2_bh_quod_up,
  ex2_bhalf0_orig_frac,
  ex2_dest_bhalf,
  ex2_dest_double,
  ex2_dest_float,
  ex2_dest_half,
  ex2_dest_l16,
  ex2_dest_l32,
  ex2_dest_l64,
  ex2_dest_l8,
  ex2_dest_si,
  ex2_dest_single,
  ex2_double_orig_frac,
  ex2_h_quod_up,
  ex2_half0_orig_frac,
  ex2_int16_0_result,
  ex2_int32_0_result,
  ex2_int64_result,
  ex2_l16_0_result,
  ex2_l32_0_result,
  ex2_l8_0_result,
  ex2_narrow,
  ex2_op_itof,
  ex2_quod_dn,
  ex2_single0_orig_frac,
  ex2_src_l16,
  ex2_src_l32,
  ex2_src_l64,
  ex2_widden,
  ex3_double_result,
  fcnvt_ex1_pipe_clk,
  fcnvt_ex1_pipedown,
  fcnvt_ex2_pipe_clk,
  fcnvt_ex2_pipedown,
  half0_final_frac,
  ifu_vpu_warm_up,
  l16_0_itof_value,
  l32_0_itof_value,
  l64_itof_value,
  single0_final_frac,
  vfcvt_vpu_ex2_gpr_result,
  vfcvt_vpu_ex3_fflags,
  vfcvt_vpu_ex3_fpr_result,
  vpu_group_1_xx_ex1_func,
  vpu_group_1_xx_ex1_srcv0,
  vpu_group_1_xx_ex1_srcv0_type,
  vpu_group_1_xx_ex1_srcv1
);



input   [15:0]  bhalf0_final_frac;                   
input           cp0_vpu_xx_bf16;                     
input   [63:0]  double_final_frac;                   
input           double_pipe_ex1_special_vld;         
input   [3 :0]  double_pipe_ex2_expt;                
input   [63:0]  double_pipe_ftoi_int;                
input   [63:0]  ex2_int16_0_result;                  
input   [63:0]  ex2_int32_0_result;                  
input   [63:0]  ex2_int64_result;                    
input   [63:0]  ex2_l16_0_result;                    
input   [63:0]  ex2_l32_0_result;                    
input   [7 :0]  ex2_l8_0_result;                     
input   [63:0]  ex3_double_result;                   
input           fcnvt_ex1_pipe_clk;                  
input           fcnvt_ex1_pipedown;                  
input           fcnvt_ex2_pipe_clk;                  
input           fcnvt_ex2_pipedown;                  
input   [15:0]  half0_final_frac;                    
input           ifu_vpu_warm_up;                     
input   [31:0]  single0_final_frac;                  
input   [19:0]  vpu_group_1_xx_ex1_func;             
input   [63:0]  vpu_group_1_xx_ex1_srcv0;            
input   [47:0]  vpu_group_1_xx_ex1_srcv0_type;       
input   [63:0]  vpu_group_1_xx_ex1_srcv1;            
output  [5 :0]  double_pipe_bhtod_value;             
output  [4 :0]  double_pipe_bhtox_expnt;             
output          double_pipe_ex1_src_cnan;            
output          double_pipe_ex1_src_inf;             
output          double_pipe_ex1_src_qnan;            
output          double_pipe_ex1_src_snan;            
output          double_pipe_ex1_src_zero;            
output  [63:0]  double_pipe_ex2_frac;                
output  [63:0]  double_pipe_ex2_int;                 
output  [5 :0]  double_pipe_ex2_widden_dn_itof_expnt; 
output  [4 :0]  double_pipe_htox_expnt;              
output  [8 :0]  double_pipe_htox_value;              
output  [63:0]  double_pipe_special_value;           
output          double_pipe_src_dn;                  
output  [4 :0]  double_pipe_stod_expnt;              
output  [21:0]  double_pipe_stod_value;              
output          ex1_dest_bhalf;                      
output          ex1_dest_float;                      
output          ex1_dest_half;                       
output          ex1_dest_si;                         
output          ex1_dest_single;                     
output  [63:0]  ex1_double_src;                      
output  [15:0]  ex1_half0_src;                       
output  [7 :0]  ex1_l8_0_src;                        
output          ex1_op_bhtod;                        
output          ex1_op_bhtos;                        
output          ex1_op_dtobh;                        
output          ex1_op_dtoh;                         
output          ex1_op_dtos;                         
output          ex1_op_ftoi;                         
output          ex1_op_htod;                         
output          ex1_op_htos;                         
output          ex1_op_stobh;                        
output          ex1_op_stod;                         
output          ex1_op_stoh;                         
output  [31:0]  ex1_single0_src;                     
output          ex1_src_bhalf;                       
output          ex1_src_double;                      
output          ex1_src_float;                       
output          ex1_src_half;                        
output          ex1_src_i;                           
output          ex1_src_l16;                         
output          ex1_src_l32;                         
output          ex1_src_l64;                         
output          ex1_src_l8;                          
output          ex1_src_si;                          
output          ex1_src_single;                      
output          ex2_bh_quod_up;                      
output  [6 :0]  ex2_bhalf0_orig_frac;                
output          ex2_dest_bhalf;                      
output          ex2_dest_double;                     
output          ex2_dest_float;                      
output          ex2_dest_half;                       
output          ex2_dest_l16;                        
output          ex2_dest_l32;                        
output          ex2_dest_l64;                        
output          ex2_dest_l8;                         
output          ex2_dest_si;                         
output          ex2_dest_single;                     
output  [51:0]  ex2_double_orig_frac;                
output          ex2_h_quod_up;                       
output  [9 :0]  ex2_half0_orig_frac;                 
output          ex2_narrow;                          
output          ex2_op_itof;                         
output          ex2_quod_dn;                         
output  [22:0]  ex2_single0_orig_frac;               
output          ex2_src_l16;                         
output          ex2_src_l32;                         
output          ex2_src_l64;                         
output          ex2_widden;                          
output  [15:0]  l16_0_itof_value;                    
output  [31:0]  l32_0_itof_value;                    
output  [63:0]  l64_itof_value;                      
output  [63:0]  vfcvt_vpu_ex2_gpr_result;            
output  [4 :0]  vfcvt_vpu_ex3_fflags;                
output  [63:0]  vfcvt_vpu_ex3_fpr_result;            


reg             ex2_bh_quod_up;                      
reg     [63:0]  ex2_comb_frac;                       
reg     [63:0]  ex2_combin_src;                      
reg             ex2_dest_bhalf_flop;                 
reg             ex2_dest_float;                      
reg             ex2_dest_l16;                        
reg             ex2_dest_l32;                        
reg             ex2_dest_l64;                        
reg             ex2_dest_l8;                         
reg             ex2_dest_si;                         
reg             ex2_h_quod_up;                       
reg     [5 :0]  ex2_left_shift_bit;                  
reg             ex2_narrow;                          
reg             ex2_op_itof;                         
reg             ex2_quod_dn;                         
reg             ex2_src_l16;                         
reg             ex2_src_l32;                         
reg             ex2_src_l64;                         
reg             ex2_src_l8;                          
reg             ex2_widden;                          
reg             ex3_dest_l64;                        
reg     [3 :0]  ex3_expt;                            
reg     [63:0]  ex3_result;                          


wire    [15:0]  bhalf0_final_frac;                   
wire    [63:0]  bhalf0_for_ff1;                      
wire    [15:0]  bhalf0_frac_for_shift;               
wire    [5 :0]  bhtod_shift_bit;                     
wire            cnvt_src0_half0_id;                  
wire            cnvt_src0_half0_inf;                 
wire            cnvt_src0_half0_qnan;                
wire            cnvt_src0_half0_snan;                
wire            cnvt_src0_half0_zero;                
wire            cp0_vpu_xx_bf16;                     
wire            cur_l16;                             
wire            cur_l32;                             
wire            cur_l64;                             
wire            cur_l8;                              
wire    [63:0]  double_final_frac;                   
wire    [5 :0]  double_pipe_bhtod_value;             
wire    [4 :0]  double_pipe_bhtox_expnt;             
wire            double_pipe_ex1_special_vld;         
wire            double_pipe_ex1_src_cnan;            
wire            double_pipe_ex1_src_inf;             
wire            double_pipe_ex1_src_qnan;            
wire            double_pipe_ex1_src_snan;            
wire            double_pipe_ex1_src_zero;            
wire    [3 :0]  double_pipe_ex2_expt;                
wire    [63:0]  double_pipe_ex2_frac;                
wire    [63:0]  double_pipe_ex2_int;                 
wire    [5 :0]  double_pipe_ex2_itof_expnt;          
wire    [5 :0]  double_pipe_ex2_widden_dn_itof_expnt; 
wire    [5 :0]  double_pipe_ex2_xtod_expnt;          
wire    [63:0]  double_pipe_ftoi_int;                
wire    [4 :0]  double_pipe_htox_expnt;              
wire    [8 :0]  double_pipe_htox_value;              
wire    [63:0]  double_pipe_special_value;           
wire            double_pipe_src_dn;                  
wire    [4 :0]  double_pipe_stod_expnt;              
wire    [21:0]  double_pipe_stod_value;              
wire            ex1_bh_quod_up;                      
wire    [63:0]  ex1_combined_src;                    
wire            ex1_dest_bhalf;                      
wire            ex1_dest_double;                     
wire            ex1_dest_float;                      
wire            ex1_dest_half;                       
wire            ex1_dest_l16;                        
wire            ex1_dest_l32;                        
wire            ex1_dest_l64;                        
wire            ex1_dest_l8;                         
wire            ex1_dest_si;                         
wire            ex1_dest_single;                     
wire            ex1_dest_widden;                     
wire    [63:0]  ex1_double_src;                      
wire    [63:0]  ex1_final_norm_frac;                 
wire    [5 :0]  ex1_float_shift_bit;                 
wire    [63:0]  ex1_float_src_tail;                  
wire    [63:0]  ex1_ftoi_int;                        
wire            ex1_h_quod_up;                       
wire    [15:0]  ex1_half0_src;                       
wire    [5 :0]  ex1_itof_shift_bit;                  
wire            ex1_l16_0_src_neg;                   
wire            ex1_l32_0_src_neg;                   
wire            ex1_l64_0_src_neg;                   
wire    [7 :0]  ex1_l8_0_src;                        
wire    [5 :0]  ex1_left_shift_bit;                  
wire            ex1_narrow;                          
wire    [63:0]  ex1_norm_neg_src;                    
wire    [63:0]  ex1_norm_src;                        
wire            ex1_op_bhtod;                        
wire            ex1_op_bhtos;                        
wire            ex1_op_dtobh;                        
wire            ex1_op_dtoh;                         
wire            ex1_op_dtos;                         
wire            ex1_op_ftoi;                         
wire            ex1_op_htod;                         
wire            ex1_op_htos;                         
wire            ex1_op_itof;                         
wire            ex1_op_stobh;                        
wire            ex1_op_stod;                         
wire            ex1_op_stoh;                         
wire            ex1_quod_dn;                         
wire            ex1_quod_up;                         
wire            ex1_same;                            
wire            ex1_sign;                            
wire    [31:0]  ex1_single0_src;                     
wire    [3 :0]  ex1_size;                            
wire            ex1_special_vld;                     
wire            ex1_src_bhalf;                       
wire            ex1_src_double;                      
wire            ex1_src_float;                       
wire            ex1_src_half;                        
wire            ex1_src_i;                           
wire            ex1_src_l16;                         
wire            ex1_src_l32;                         
wire            ex1_src_l64;                         
wire            ex1_src_l8;                          
wire            ex1_src_neg;                         
wire            ex1_src_si;                          
wire            ex1_src_single;                      
wire            ex1_widden;                          
wire    [6 :0]  ex2_bhalf0_orig_frac;                
wire            ex2_dest_bhalf;                      
wire            ex2_dest_double;                     
wire            ex2_dest_half;                       
wire            ex2_dest_single;                     
wire    [51:0]  ex2_double_orig_frac;                
wire    [3 :0]  ex2_expt;                            
wire    [63:0]  ex2_frac;                            
wire    [9 :0]  ex2_half0_orig_frac;                 
wire    [63:0]  ex2_int16_0_result;                  
wire    [63:0]  ex2_int32_0_result;                  
wire    [63:0]  ex2_int64_result;                    
wire    [63:0]  ex2_int_r;                           
wire    [63:0]  ex2_l16_0_result;                    
wire    [63:0]  ex2_l32_0_result;                    
wire    [63:0]  ex2_scalar_int_result;               
wire    [63:0]  ex2_scalar_total_result;             
wire    [63:0]  ex2_shift_src;                       
wire    [22:0]  ex2_single0_orig_frac;               
wire    [63:0]  ex2_total_result;                    
wire    [63:0]  ex3_double_result;                   
wire            fcnvt_ex1_pipe_clk;                  
wire            fcnvt_ex1_pipedown;                  
wire            fcnvt_ex2_pipe_clk;                  
wire            fcnvt_ex2_pipedown;                  
wire    [23:0]  ff1_16_bit;                          
wire    [13:0]  ff1_32_bit;                          
wire    [7 :0]  ff1_64_bit;                          
wire    [39:0]  ff1_8_bit;                           
wire    [63:0]  ff1_src_in;                          
wire    [15:0]  half0_final_frac;                    
wire    [63:0]  half0_for_ff1;                       
wire    [15:0]  half0_frac_for_shift;                
wire    [5 :0]  htox_shift_bit;                      
wire    [5 :0]  i16tof_shift_bit;                    
wire    [5 :0]  i32tof_shift_bit;                    
wire    [5 :0]  i64tof_shift_bit;                    
wire            ifu_vpu_warm_up;                     
wire    [63:0]  int_src_for_shift;                   
wire    [15:0]  l16_0_itof_value;                    
wire    [15:0]  l16_0_shift_out_val;                 
wire    [15:0]  l16_1_shift_out_val;                 
wire    [15:0]  l16_2_shift_out_val;                 
wire    [15:0]  l16_3_shift_out_val;                 
wire    [31:0]  l32_0_itof_value;                    
wire    [31:0]  l32_0_shift_out_val;                 
wire    [31:0]  l32_1_shift_out_val;                 
wire    [63:0]  l64_int_abs_val;                     
wire    [63:0]  l64_itof_value;                      
wire    [63:0]  l64_shift_out_val;                   
wire    [63:0]  neg_adder_op0;                       
wire    [63:0]  neg_adder_op1;                       
wire    [63:0]  neg_result;                          
wire            shift_16;                            
wire    [2 :0]  shift_src_size;                      
wire    [31:0]  single0_final_frac;                  
wire            src0_double_id;                      
wire            src0_double_inf;                     
wire            src0_double_qnan;                    
wire            src0_double_snan;                    
wire            src0_double_zero;                    
wire            src0_half0_cnan;                     
wire            src0_half0_id;                       
wire            src0_half0_inf;                      
wire            src0_half0_qnan;                     
wire            src0_half0_snan;                     
wire            src0_half0_zero;                     
wire            src0_single0_cnan;                   
wire            src0_single0_id;                     
wire            src0_single0_inf;                    
wire            src0_single0_qnan;                   
wire            src0_single0_snan;                   
wire            src0_single0_zero;                   
wire    [47:0]  srcv0_type;                          
wire    [5 :0]  stod_shift_bit;                      
wire    [63:0]  vfcvt_vpu_ex2_gpr_result;            
wire    [4 :0]  vfcvt_vpu_ex3_fflags;                
wire    [63:0]  vfcvt_vpu_ex3_fpr_result;            
wire    [19:0]  vpu_group_1_xx_ex1_func;             
wire    [63:0]  vpu_group_1_xx_ex1_srcv0;            
wire    [47:0]  vpu_group_1_xx_ex1_srcv0_type;       
wire    [63:0]  vpu_group_1_xx_ex1_srcv1;            






















assign ex1_op_ftoi    = !vpu_group_1_xx_ex1_func[1] && vpu_group_1_xx_ex1_func[3];
assign ex1_op_stod    = vpu_group_1_xx_ex1_func[1] && vpu_group_1_xx_ex1_func[3] &&
                        vpu_group_1_xx_ex1_func[6] && ex1_src_l32;
assign ex1_op_dtos    = vpu_group_1_xx_ex1_func[1] && vpu_group_1_xx_ex1_func[3] &&
                        vpu_group_1_xx_ex1_func[5] && ex1_src_l64;
assign ex1_op_htos    = vpu_group_1_xx_ex1_func[1] && vpu_group_1_xx_ex1_func[3] &&
                        vpu_group_1_xx_ex1_func[6] && ex1_src_l16&& !cp0_vpu_xx_bf16; 
assign ex1_op_bhtos    = vpu_group_1_xx_ex1_func[1] && vpu_group_1_xx_ex1_func[3] &&
                        vpu_group_1_xx_ex1_func[6] && ex1_src_l16&& cp0_vpu_xx_bf16;                        
assign ex1_op_stoh    = vpu_group_1_xx_ex1_func[1] && vpu_group_1_xx_ex1_func[3] &&
                        vpu_group_1_xx_ex1_func[5] && ex1_src_l32 && !cp0_vpu_xx_bf16;
assign ex1_op_stobh    = vpu_group_1_xx_ex1_func[1] && vpu_group_1_xx_ex1_func[3] &&
                        vpu_group_1_xx_ex1_func[5] && ex1_src_l32 && cp0_vpu_xx_bf16;
                        
assign ex1_op_itof    = vpu_group_1_xx_ex1_func[1] && !vpu_group_1_xx_ex1_func[3];
assign ex1_op_bhtod   = vpu_group_1_xx_ex1_func[1] && vpu_group_1_xx_ex1_func[3] &&
                        vpu_group_1_xx_ex1_func[8] && ex1_src_bhalf;
assign ex1_op_htod   = vpu_group_1_xx_ex1_func[1] && vpu_group_1_xx_ex1_func[3] &&
                        vpu_group_1_xx_ex1_func[8] && ex1_src_half;
assign ex1_op_dtoh    = vpu_group_1_xx_ex1_func[1] && vpu_group_1_xx_ex1_func[3] &&
                        vpu_group_1_xx_ex1_func[7] && ex1_src_l64 && !cp0_vpu_xx_bf16;
assign ex1_op_dtobh    = vpu_group_1_xx_ex1_func[1] && vpu_group_1_xx_ex1_func[3] &&
                        vpu_group_1_xx_ex1_func[7] && ex1_src_l64 && cp0_vpu_xx_bf16;





assign cur_l64        = vpu_group_1_xx_ex1_func[13:12] == 2'b11;
assign cur_l32        = vpu_group_1_xx_ex1_func[13:12] == 2'b10;
assign cur_l16        = vpu_group_1_xx_ex1_func[13:12] == 2'b01;
assign cur_l8         = vpu_group_1_xx_ex1_func[13:12] == 2'b00;
assign ex1_narrow     = vpu_group_1_xx_ex1_func[5];
assign ex1_same       = vpu_group_1_xx_ex1_func[4];
assign ex1_quod_up    = vpu_group_1_xx_ex1_func[8];
assign ex1_quod_dn    = vpu_group_1_xx_ex1_func[7];

assign ex1_dest_si    = vpu_group_1_xx_ex1_func[1:0] == 2'b00;
assign ex1_dest_widden= vpu_group_1_xx_ex1_func[6];

assign ex1_src_l64    = cur_l64 && ex1_same   ||
                        cur_l32 && ex1_narrow ||
                        cur_l16 && ex1_quod_dn;
assign ex1_src_l32    = cur_l32 && (ex1_same || ex1_widden)  ||
                        cur_l16 && ex1_narrow;
assign ex1_src_l16    = cur_l16 && (ex1_same || ex1_widden || ex1_quod_up)|| cur_l8  &&ex1_narrow;
assign ex1_src_l8     = cur_l8  && ex1_widden;

assign ex1_src_double = ex1_src_l64 && vpu_group_1_xx_ex1_func[3];
assign ex1_src_single = ex1_src_l32 && vpu_group_1_xx_ex1_func[3];
assign ex1_src_half   = ex1_src_l16 && vpu_group_1_xx_ex1_func[3] && !cp0_vpu_xx_bf16;
assign ex1_src_bhalf  = ex1_src_l16 && vpu_group_1_xx_ex1_func[3] && cp0_vpu_xx_bf16;

assign ex1_h_quod_up  = ex1_quod_up && !cp0_vpu_xx_bf16;
assign ex1_bh_quod_up = ex1_quod_up && cp0_vpu_xx_bf16;





assign ex1_src_float  = vpu_group_1_xx_ex1_func[3];
assign ex1_dest_float = vpu_group_1_xx_ex1_func[1];

assign ex1_src_si     = !vpu_group_1_xx_ex1_func[3] && !vpu_group_1_xx_ex1_func[2];
assign ex1_src_i      = !vpu_group_1_xx_ex1_func[3];


assign ex1_dest_l64    = cur_l64 && ex1_same   ||
                         cur_l32 && ex1_widden ||
                         cur_l16 && ex1_quod_up;
assign ex1_dest_l32    = cur_l32 && (ex1_same || ex1_narrow)  ||
                         cur_l16 && ex1_widden;
assign ex1_dest_l16    = cur_l16 && (ex1_same || ex1_narrow || ex1_quod_dn)  ||
                         cur_l8 && ex1_widden;
assign ex1_dest_l8     = cur_l8  && ex1_narrow;

assign ex1_dest_double  = ex1_dest_l64;
assign ex1_dest_single  = ex1_dest_l32;
assign ex1_dest_half    = ex1_dest_l16 && !cp0_vpu_xx_bf16;
assign ex1_dest_bhalf   = ex1_dest_l16 && cp0_vpu_xx_bf16;









assign srcv0_type[47:0]          = vpu_group_1_xx_ex1_srcv0_type[47:0];
assign src0_double_snan    = srcv0_type[47];
assign src0_double_qnan    = srcv0_type[46];
assign src0_double_inf    = srcv0_type[45];
assign src0_double_zero    = srcv0_type[44];
assign src0_double_id    = srcv0_type[43];

assign src0_single0_cnan    = srcv0_type[41];
assign src0_single0_snan    = srcv0_type[40];
assign src0_single0_qnan    = srcv0_type[39];
assign src0_single0_inf    = srcv0_type[38];
assign src0_single0_zero    = srcv0_type[37];
assign src0_single0_id    = srcv0_type[36];

assign src0_half0_cnan    = srcv0_type[27];
assign src0_half0_snan    = srcv0_type[26];
assign src0_half0_qnan    = srcv0_type[25];
assign src0_half0_inf     = srcv0_type[24];
assign src0_half0_zero    = srcv0_type[23];
assign src0_half0_id    = srcv0_type[22];


assign cnvt_src0_half0_inf   = src0_half0_inf;
assign cnvt_src0_half0_snan  = src0_half0_snan;
assign cnvt_src0_half0_qnan  = src0_half0_qnan;
assign cnvt_src0_half0_zero  = src0_half0_zero;
assign cnvt_src0_half0_id    = src0_half0_id;


assign double_pipe_ex1_src_inf      = ex1_src_double && src0_double_inf 
                                      || ex1_src_single && src0_single0_inf 
                                      || (ex1_src_half || ex1_src_bhalf) && cnvt_src0_half0_inf;
assign double_pipe_ex1_src_qnan     = ex1_src_double && src0_double_qnan 
                                      || ex1_src_single && src0_single0_qnan 
                                      || (ex1_src_half || ex1_src_bhalf) && cnvt_src0_half0_qnan;


assign double_pipe_ex1_src_cnan     = ex1_src_single && src0_single0_cnan || (ex1_src_half || ex1_src_bhalf) && src0_half0_cnan;
assign double_pipe_ex1_src_snan     = ex1_src_double && src0_double_snan || ex1_src_single && src0_single0_snan || (ex1_src_half || ex1_src_bhalf) && cnvt_src0_half0_snan;
assign double_pipe_ex1_src_zero     = ex1_src_double && src0_double_zero || ex1_src_single && src0_single0_zero || (ex1_src_half || ex1_src_bhalf) && cnvt_src0_half0_zero;


assign double_pipe_src_dn            = ex1_src_double && src0_double_id  || 
                                       ex1_src_single && src0_single0_id ||
                                       (ex1_src_half||ex1_src_bhalf)   && cnvt_src0_half0_id; 




assign ex1_norm_src[63:0]            = ex1_src_i ? vpu_group_1_xx_ex1_srcv1[63:0] : vpu_group_1_xx_ex1_srcv0[63:0];




assign ex1_double_src[63:0]     = ex1_norm_src[63:0];
assign ex1_single0_src[31:0]    = ex1_norm_src[31:0];
assign ex1_half0_src[15:0]      = ex1_norm_src[15:0];
                                                                 



assign ex1_l8_0_src[7:0]        = 8'b0;











assign ex1_widden                  = ex1_dest_widden;
















































assign ex1_sign                 =   ex1_op_itof && ex1_src_si;
assign ex1_size                 =  {ex1_src_l64,ex1_src_l32,ex1_src_l16,ex1_src_l8};
assign ff1_src_in[63:0]         =   ex1_op_itof ? ex1_norm_src[63:0]
                                                : ex1_float_src_tail[63:0];
assign half0_frac_for_shift[15:0]   = {ex1_norm_src[9:0],6'b0};                                             



assign bhalf0_frac_for_shift[15:0]  = {ex1_norm_src[6:0],9'b0};                                             



assign half0_for_ff1[63:0]          = {48'b0,half0_frac_for_shift[15:0]};
assign bhalf0_for_ff1[63:0]         = {48'b0,bhalf0_frac_for_shift[15:0]};
assign ex1_float_src_tail[63:0]     = {64{ex1_src_l32}}   & {32'b0,ex1_norm_src[22:0],9'b0} |
                                      {64{ex1_src_half}}  & {half0_for_ff1[63:0]}           |
                                      {64{ex1_src_bhalf}} & {bhalf0_for_ff1[63:0]};









aq_vdsp_64_bit_ff1  x_aq_vdsp_64_bit_ff1 (
  .ex1_sign   (ex1_sign  ),
  .ex1_size   (ex1_size  ),
  .ex1_src    (ff1_src_in),
  .ff1_16_bit (ff1_16_bit),
  .ff1_32_bit (ff1_32_bit),
  .ff1_64_bit (ff1_64_bit),
  .ff1_8_bit  (ff1_8_bit )
);






assign  i16tof_shift_bit[5:0]        = {2'b0,ff1_16_bit[3:0]};
assign  i32tof_shift_bit[5:0]        = {1'b0,ff1_32_bit[4:0]};




assign  i64tof_shift_bit[5:0]        = {ff1_64_bit[5:0]};
assign  ex1_itof_shift_bit[5:0]      = {6{ex1_src_l64}} & i64tof_shift_bit[5:0] |
                                       {6{ex1_src_l32}} & i32tof_shift_bit[5:0] |
                                       {6{ex1_src_l16}} & i16tof_shift_bit[5:0];

assign  stod_shift_bit[5:0]          = {1'b0,ff1_32_bit[4:0]};
assign double_pipe_stod_expnt[4:0]    = stod_shift_bit[4:0];

assign  htox_shift_bit[5:0]          = {2'b0,ff1_16_bit[3:0]};

assign bhtod_shift_bit[5:0]          = {2'b0,ff1_16_bit[3:0]};
assign ex1_float_shift_bit[5:0]      = {6{ex1_op_stod}} & stod_shift_bit[5:0] |
                                       {6{ex1_op_htos||
                                          ex1_op_htod}}  & htox_shift_bit[5:0]   |
                                       {6{ex1_op_bhtod}} & bhtod_shift_bit[5:0];
assign double_pipe_bhtox_expnt[4:0]   = {1'b0,bhtod_shift_bit[3:0]};
assign double_pipe_htox_expnt[4:0]    = {1'b0,htox_shift_bit[3:0]};


assign ex1_left_shift_bit[5:0]       = ex1_op_itof ? ex1_itof_shift_bit[5:0]
                                                   : ex1_float_shift_bit[5:0];

assign ex1_norm_neg_src[63:0]  = ~ex1_norm_src[63:0];
assign neg_adder_op0[63:0]     = {64{ex1_src_l64}} & {ex1_norm_neg_src[63:0]} | 
                                 {64{ex1_src_l32}} & {{32{ex1_norm_neg_src[31]}},ex1_norm_neg_src[31:0]} |
                                 {64{ex1_src_l16}} & {{48{ex1_norm_neg_src[15]}},ex1_norm_neg_src[15:0]};
assign neg_adder_op1[63:0]     = 64'b1;

assign neg_result[63:0]        = neg_adder_op0[63:0] + neg_adder_op1[63:0];




assign ex1_l64_0_src_neg       = ex1_norm_src[63] && ex1_src_si;
assign ex1_l32_0_src_neg       = ex1_norm_src[31] && ex1_src_si;
assign ex1_l16_0_src_neg       = ex1_norm_src[15] && ex1_src_si;
assign ex1_src_neg             = ex1_src_l64 && ex1_l64_0_src_neg ||
                                 ex1_src_l32 && ex1_l32_0_src_neg ||
                                 ex1_src_l16 && ex1_l16_0_src_neg;








assign l64_int_abs_val[63:0]   = ex1_src_neg ? neg_result[63:0]  : ex1_norm_src[63:0];





















assign int_src_for_shift[63:0] = l64_int_abs_val[63:0];





assign ex1_ftoi_int[63:0]       = double_pipe_ftoi_int[63:0];


assign ex1_final_norm_frac[63:0] = {64{ex1_dest_double}} & double_final_frac[63:0]   |
                                   {64{ex1_dest_single}} & {32'b0,single0_final_frac[31:0]} |
                                   {64{ex1_dest_half}}   & {48'b0,half0_final_frac[15:0]}   |
                                   {64{ex1_dest_bhalf}}  & {48'b0,bhalf0_final_frac[15:0]};




assign ex1_combined_src[63:0]   = ex1_op_itof ? {int_src_for_shift[63:0]} 
                                              : {ex1_final_norm_frac[63:0]};                                            
assign ex1_special_vld        = double_pipe_ex1_special_vld;
always @(posedge fcnvt_ex1_pipe_clk)
begin
  if(fcnvt_ex1_pipedown && ex1_op_ftoi || ifu_vpu_warm_up) begin

    ex2_combin_src[63:0] <= ex1_ftoi_int[63:0];
  end
end
assign ex2_int_r[63:0]  = ex2_combin_src[63:0];
assign ex2_frac[63:0]   =  ex2_comb_frac[63:0];
assign ex2_shift_src[63:0] = ex2_comb_frac[63:0];


always @(posedge fcnvt_ex1_pipe_clk)
begin
  if(fcnvt_ex1_pipedown && (ex1_dest_float|| ex1_special_vld) || ifu_vpu_warm_up) begin


    ex2_comb_frac[63:0]      <= ex1_combined_src[63:0];
    ex2_left_shift_bit[5:0] <= ex1_left_shift_bit[5:0];
  end
end
always @(posedge fcnvt_ex1_pipe_clk)
begin 
  if(fcnvt_ex1_pipedown || ifu_vpu_warm_up) begin
    ex2_narrow      <= ex1_narrow;
    ex2_widden      <= ex1_widden;
    ex2_quod_dn     <= ex1_quod_dn;
    ex2_h_quod_up   <= ex1_h_quod_up;
    ex2_bh_quod_up  <= ex1_bh_quod_up;
    ex2_op_itof     <= ex1_op_itof;
    ex2_src_l64     <= ex1_src_l64;
    ex2_src_l32     <= ex1_src_l32;
    ex2_src_l16     <= ex1_src_l16;
    ex2_src_l8      <= ex1_src_l8;
    ex2_dest_l64    <= ex1_dest_l64;
    ex2_dest_l32    <= ex1_dest_l32;
    ex2_dest_l16    <= ex1_dest_l16;
    ex2_dest_bhalf_flop  <= ex1_dest_bhalf;
    ex2_dest_l8     <= ex1_dest_l8;
    ex2_dest_float  <= ex1_dest_float;
    ex2_dest_si     <= ex1_dest_si;
  end
end


















assign double_pipe_ex2_itof_expnt[5:0]= ex2_left_shift_bit[5:0];
assign double_pipe_ex2_xtod_expnt[5:0]= {1'b0,ex2_left_shift_bit[4:0]};
assign double_pipe_ex2_widden_dn_itof_expnt[5:0] = ex2_op_itof ? double_pipe_ex2_itof_expnt[5:0]
                                                               : double_pipe_ex2_xtod_expnt[5:0];
                                        

assign ex2_dest_double              =  ex2_dest_l64 && ex2_dest_float;
assign ex2_dest_single              =  ex2_dest_l32 && ex2_dest_float;
assign ex2_dest_half                =  ex2_dest_l16 && ex2_dest_float && !ex2_dest_bhalf;
assign ex2_dest_bhalf               =   ex2_dest_float && ex2_dest_bhalf_flop;



assign double_pipe_ex2_int[63:0]    = ex2_int_r[63:0];

assign double_pipe_ex2_frac[63:0]    = ex2_frac[63:0];



assign ex2_double_orig_frac[51:0]    = ex2_frac[51:0];
assign ex2_single0_orig_frac[22:0]   = ex2_frac[22:0];

assign ex2_half0_orig_frac[9:0]     = ex2_frac[9:0];
assign ex2_bhalf0_orig_frac[6:0]    = ex2_frac[6:0];







assign shift_16             = ex2_src_l16||ex2_src_l8;
assign shift_src_size[2:0]  = {ex2_src_l64,ex2_src_l32,shift_16};





aq_left_shift_64  x_aq_left_shift_64 (
  .input_l16_0_shift_cnt   (ex2_left_shift_bit[3:0]),
  .input_l16_1_shift_cnt   (4'b0                   ),
  .input_l16_2_shift_cnt   (4'b0                   ),
  .input_l16_3_shift_cnt   (4'b0                   ),
  .input_l32_0_shift_cnt   (ex2_left_shift_bit[4:0]),
  .input_l32_1_shift_cnt   (5'b0                   ),
  .input_l64_shift_cnt     (ex2_left_shift_bit[5:0]),
  .input_org_src           (ex2_shift_src          ),
  .input_size              (shift_src_size[2:0]    ),
  .l16_0_shift_out_val     (l16_0_shift_out_val    ),
  .l16_1_shift_out_val     (l16_1_shift_out_val    ),
  .l16_2_shift_out_val     (l16_2_shift_out_val    ),
  .l16_3_shift_out_val     (l16_3_shift_out_val    ),
  .l32_0_shift_out_val     (l32_0_shift_out_val    ),
  .l32_1_shift_out_val     (l32_1_shift_out_val    ),
  .l64_shift_out_val       (l64_shift_out_val      )
);












assign l64_itof_value[63:0]   = l64_shift_out_val[63:0];
assign l32_0_itof_value[31:0] = l32_0_shift_out_val[31:0];
assign l16_0_itof_value[15:0] = l16_0_shift_out_val[15:0];
 
assign double_pipe_stod_value[21:0] = l32_0_shift_out_val[30:9];
assign double_pipe_htox_value[8:0]  = l16_0_shift_out_val[14:6];
assign double_pipe_bhtod_value[5:0] = l16_0_shift_out_val[14:9];



































assign double_pipe_special_value[63:0]    =  ex2_frac[63:0];






assign ex2_scalar_total_result[63:0]    =
                                          {64{ex2_dest_l32}} & {ex2_l32_0_result[63:0]} |
                                          {64{ex2_dest_l16}} & {ex2_l16_0_result[63:0]}; 
assign ex2_scalar_int_result[63:0]      = {64{ex2_dest_l64}} & ex2_int64_result[63:0]     |
                                          {64{ex2_dest_l32}} & {ex2_int32_0_result[63:0]} |
                                          {64{ex2_dest_l16}} & {ex2_int16_0_result[63:0]};       
assign vfcvt_vpu_ex2_gpr_result[63:0]   = ex2_scalar_int_result[63:0];
assign ex2_total_result[63:0]           = ex2_scalar_total_result[63:0];    

assign ex2_expt[3:0]                    = double_pipe_ex2_expt[3:0];
always @(posedge fcnvt_ex2_pipe_clk)
begin
  if(fcnvt_ex2_pipedown) begin
    ex3_result[63:0]     <= ex2_total_result[63:0];
  end
end
always @(posedge fcnvt_ex2_pipe_clk)
begin
  if(fcnvt_ex2_pipedown) begin
    ex3_expt[3:0]      <= ex2_expt[3:0];
    ex3_dest_l64       <= ex2_dest_l64;
  end
end







assign vfcvt_vpu_ex3_fpr_result[63:0]             = ex3_dest_l64 ? ex3_double_result[63:0] : ex3_result[63:0];
assign vfcvt_vpu_ex3_fflags[4:0]                  = {ex3_expt[3],1'b0,ex3_expt[2:0]};







endmodule