data/full_repos/permissive/489642764/src/top.v
1: b'%Warning-WIDTH: data/full_repos/permissive/489642764/src/top.v:98: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'24\'h0\' generates 24 bits.\n                                                                 : ... In instance top\n   ledcnt_r <= 24\'d0;\n            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/489642764/src/top.v:102: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'24\'h0\' generates 24 bits.\n                                                                  : ... In instance top\n   ledcnt_r <= 24\'d0;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/489642764/src/top.v:109: Operator EQ expects 32 bits on the RHS, but RHS\'s CONST \'24\'h3d0900\' generates 24 bits.\n                                                                  : ... In instance top\n  end else if (ledcnt_r == 24\'d400_0000) begin\n                        ^~\n%Error: Exiting due to 3 warning(s)\n'
function [8:0] led_row_f;
		input [3:0] led_row_arg;
		begin
		case (led_row_arg)
			4'd0: led_row_f = 9'b100000000;
			4'd1: led_row_f = 9'b010000000;
			4'd2: led_row_f = 9'b001000000;
			4'd3: led_row_f = 9'b000100000;
			4'd4: led_row_f = 9'b000010000;
			4'd5: led_row_f = 9'b000001000;
			4'd6: led_row_f = 9'b000000100;
			4'd7: led_row_f = 9'b000000010;
			4'd8: led_row_f = 9'b000000001;
		endcase
		end
	endfunction
function [8:0] led_row_f;

		input [3:0] led_row_arg;
		begin
		case (led_row_arg)
			4'd0: led_row_f = 9'b100000000;
			4'd1: led_row_f = 9'b010000000;
			4'd2: led_row_f = 9'b001000000;
			4'd3: led_row_f = 9'b000100000;
			4'd4: led_row_f = 9'b000010000;
			4'd5: led_row_f = 9'b000001000;
			4'd6: led_row_f = 9'b000000100;
			4'd7: led_row_f = 9'b000000010;
			4'd8: led_row_f = 9'b000000001;
		endcase
		end
	endfunction