data/full_repos/permissive/461141714/src/Pipelined CPU/stage_EX.v
1: b'%Error: Cannot find file containing module: CPU,data/full_repos/permissive/461141714\n        ... Looked in:\n             data/full_repos/permissive/461141714/src/Pipelined/CPU,data/full_repos/permissive/461141714\n             data/full_repos/permissive/461141714/src/Pipelined/CPU,data/full_repos/permissive/461141714.v\n             data/full_repos/permissive/461141714/src/Pipelined/CPU,data/full_repos/permissive/461141714.sv\n             CPU,data/full_repos/permissive/461141714\n             CPU,data/full_repos/permissive/461141714.v\n             CPU,data/full_repos/permissive/461141714.sv\n             obj_dir/CPU,data/full_repos/permissive/461141714\n             obj_dir/CPU,data/full_repos/permissive/461141714.v\n             obj_dir/CPU,data/full_repos/permissive/461141714.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/461141714/src/Pipelined\n%Error: Cannot find file containing module: CPU/stage_EX.v\n%Error: Exiting due to 3 error(s)\n'
module STAGE_EX(
        input clk,
        input reset_n,
        

        input [`WORD_SIZE-1:0] PC,
        input [`WORD_SIZE-1:0] instruction,
        input [`WORD_SIZE-1:0] A,
        input [`WORD_SIZE-1:0] B,
        output [`WORD_SIZE-1:0] aluOut,
        

        input aluSrcA,
        input aluSrcB,
        input [5:0] func
    );
    
    wire [`WORD_SIZE-1:0] offset_ze = {8'b0, instruction[7:0]};
    
    wire [`WORD_SIZE-1:0] aluA = aluSrcA == 1'b0 ? PC : A;
    wire [`WORD_SIZE-1:0] aluB = aluSrcB == 1'b0 ? B : offset_ze ;
    
    ALU alu(
        .A(aluA),
        .B(aluB),
        .C(aluOut),
        .OP(func)
    );
    
    
    
endmodule
module STAGE_EX(
        input clk,
        input reset_n,
        

        input [`WORD_SIZE-1:0] PC,
        input [`WORD_SIZE-1:0] instruction,
        input [`WORD_SIZE-1:0] A,
        input [`WORD_SIZE-1:0] B,
        output [`WORD_SIZE-1:0] aluOut,
        

        input aluSrcA,
        input aluSrcB,
        input [5:0] func
    );

    
    wire [`WORD_SIZE-1:0] offset_ze = {8'b0, instruction[7:0]};
    
    wire [`WORD_SIZE-1:0] aluA = aluSrcA == 1'b0 ? PC : A;
    wire [`WORD_SIZE-1:0] aluB = aluSrcB == 1'b0 ? B : offset_ze ;
    
    ALU alu(
        .A(aluA),
        .B(aluB),
        .C(aluOut),
        .OP(func)
    );
    
    
    
endmodule