data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Basics/Norgate.v
data/verilator_xmls/e427f509-6d9b-4271-a0df-013ce2f199f4.xml
module top_module( 
    input a, 
    input b, 
    output out );

    assign out = ~(a | b);
endmodule
module top_module( 
    input a, 
    input b, 
    output out );


    assign out = ~(a | b);
endmodule