data/full_repos/permissive/435877241/prj_4.v
1: b'%Warning-WIDTH: data/full_repos/permissive/435877241/prj_4.v:35: Bit extraction of var[7:0] requires 3 bit index, not 4 bits.\n                                                               : ... In instance prj_4\n                        S0:crnt=Ks[pos]?S1:S0;\n                                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/435877241/prj_4.v:36: Bit extraction of var[7:0] requires 3 bit index, not 4 bits.\n                                                               : ... In instance prj_4\n                        S1:crnt=!Ks[pos]?S2:S1;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/435877241/prj_4.v:41: Bit extraction of var[7:0] requires 3 bit index, not 4 bits.\n                                                               : ... In instance prj_4\n                                flags[pos]=1;\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/435877241/prj_4.v:38: Bit extraction of var[7:0] requires 3 bit index, not 4 bits.\n                                                               : ... In instance prj_4\n                            if(Ks[pos])begin\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/435877241/prj_4.v:32: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'pos\' generates 4 bits.\n                                                               : ... In instance prj_4\n            if(!pos)begin\n               ^\n%Error: Exiting due to 5 warning(s)\n'
module prj_4(
    input K0,
    input [7:0] Ks,
    input RST,
    output L1,
    output L2,
    output L3,
    output L4,
    output L5,
    output L6,
    output L7,
    output L8,
    output [7:0] NUM
    );
    parameter S0=3'b001,S1=3'b010,S2=3'b100;
    reg [2:0] crnt;
    reg [6:0] num;
    assign NUM={num[6:0],1'b0};
    reg [2:0] cnt;
    reg [3:0] pos;
    reg [7:0] flags;
    assign L8=flags[7],L7=flags[6],L6=flags[5],L5=flags[4],L4=flags[3],L3=flags[2],L2=flags[1],L1=flags[0];
    always @(RST)begin
        if(RST)begin
            if(!pos)begin
                for(pos=0;pos<=7;pos=pos+1)begin
                    case(crnt)
                        S0:crnt=Ks[pos]?S1:S0;
                        S1:crnt=!Ks[pos]?S2:S1;
                        S2:begin
                            if(Ks[pos])begin
                                if(!K0) crnt=S1;
                                else crnt=S0;
                                flags[pos]=1;
                                cnt=cnt+1;
                            end
                            else crnt=S0;
                        end
                        default:crnt=S0;
                    endcase
                end
            end
        end
        else begin
            pos=0;
            cnt=0;
            flags=0;
            crnt=S0;
        end
    end
    always @(cnt)begin
        case(cnt)
            0:num=7'b1111110;
            1:num=7'b0110000;
            2:num=7'b1101101;
            3:num=7'b1111001;
            4:num=7'b0110011;
            5:num=7'b1011011;
            6:num=7'b1011111;
            default:num=7'b0000000;
        endcase
    end
endmodule
module prj_4(
    input K0,
    input [7:0] Ks,
    input RST,
    output L1,
    output L2,
    output L3,
    output L4,
    output L5,
    output L6,
    output L7,
    output L8,
    output [7:0] NUM
    );

    parameter S0=3'b001,S1=3'b010,S2=3'b100;
    reg [2:0] crnt;
    reg [6:0] num;
    assign NUM={num[6:0],1'b0};
    reg [2:0] cnt;
    reg [3:0] pos;
    reg [7:0] flags;
    assign L8=flags[7],L7=flags[6],L6=flags[5],L5=flags[4],L4=flags[3],L3=flags[2],L2=flags[1],L1=flags[0];
    always @(RST)begin
        if(RST)begin
            if(!pos)begin
                for(pos=0;pos<=7;pos=pos+1)begin
                    case(crnt)
                        S0:crnt=Ks[pos]?S1:S0;
                        S1:crnt=!Ks[pos]?S2:S1;
                        S2:begin
                            if(Ks[pos])begin
                                if(!K0) crnt=S1;
                                else crnt=S0;
                                flags[pos]=1;
                                cnt=cnt+1;
                            end
                            else crnt=S0;
                        end
                        default:crnt=S0;
                    endcase
                end
            end
        end
        else begin
            pos=0;
            cnt=0;
            flags=0;
            crnt=S0;
        end
    end
    always @(cnt)begin
        case(cnt)
            0:num=7'b1111110;
            1:num=7'b0110000;
            2:num=7'b1101101;
            3:num=7'b1111001;
            4:num=7'b0110011;
            5:num=7'b1011011;
            6:num=7'b1011111;
            default:num=7'b0000000;
        endcase
    end
endmodule