data/full_repos/permissive/426864978/midterm3/task1/reverse.sv
data/verilator_xmls/7649db4d-1694-404f-82aa-72581db48974.xml
module reverse(
  input logic clk, input logic rst_n,
  input  logic [7:0] din,  input  logic din_valid,
  output logic [7:0] dout, input  logic rdy, output logic ena
);

  parameter N = 4;
  


endmodule
module reverse(
  input logic clk, input logic rst_n,
  input  logic [7:0] din,  input  logic din_valid,
  output logic [7:0] dout, input  logic rdy, output logic ena
);


  parameter N = 4;
  


endmodule