data/full_repos/permissive/522268287/project_1/project_1.srcs/sim_1/new/seg_sim.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/522268287/project_1/project_1.srcs/sim_1/new/seg_sim.v:11: Unsupported: Ignoring delay on this delayed statement.\n#1000 $finish;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/522268287/project_1/project_1.srcs/sim_1/new/seg_sim.v:14: Unsupported: Ignoring delay on this delayed statement.\nalways #1\n       ^\n%Error: data/full_repos/permissive/522268287/project_1/project_1.srcs/sim_1/new/seg_sim.v:5: Cannot find file containing module: \'segment\'\nsegment sg(clk,score,hi,cho,lseg,rseg);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/522268287/project_1/project_1.srcs/sim_1/new,data/full_repos/permissive/522268287/segment\n             data/full_repos/permissive/522268287/project_1/project_1.srcs/sim_1/new,data/full_repos/permissive/522268287/segment.v\n             data/full_repos/permissive/522268287/project_1/project_1.srcs/sim_1/new,data/full_repos/permissive/522268287/segment.sv\n             segment\n             segment.v\n             segment.sv\n             obj_dir/segment\n             obj_dir/segment.v\n             obj_dir/segment.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module seg_sim();
reg clk=0;
reg[9:0] score,hi;
wire[7:0] cho,lseg,rseg;
segment sg(clk,score,hi,cho,lseg,rseg);

initial
begin
score=114;
hi=514;
#1000 $finish;
end

always #1
begin
clk=~clk;
score=score+5;
end


endmodule
module seg_sim();

reg clk=0;
reg[9:0] score,hi;
wire[7:0] cho,lseg,rseg;
segment sg(clk,score,hi,cho,lseg,rseg);

initial
begin
score=114;
hi=514;
#1000 $finish;
end

always #1
begin
clk=~clk;
score=score+5;
end


endmodule