data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_top_intel/modfa.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_top_intel/modfa.v:155: Cannot find file containing module: 'aladder'\naladder ialadder(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_top_intel,data/full_repos/permissive/530013823/aladder\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_top_intel,data/full_repos/permissive/530013823/aladder.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_top_intel,data/full_repos/permissive/530013823/aladder.sv\n             aladder\n             aladder.v\n             aladder.sv\n             obj_dir/aladder\n             obj_dir/aladder.v\n             obj_dir/aladder.sv\n%Error: Exiting due to 1 error(s)\n"
module modfa
    (
     clk,
     rst,
     op1,
     op2,
     mod,
     cin,
     en,
     sum,
     vld
     );




parameter WIDTH = 256;
parameter INIT  = 0;




input     clk;
input     rst;
input [WIDTH-1:0] op1;
input [WIDTH-1:0] op2;
input [WIDTH-1:0] mod;
input             cin;
input             en;

output [WIDTH-1:0] sum;
output             vld; 




reg [WIDTH-1:0]    sum;
reg                vld;




reg [WIDTH-1:0]    a, b;
reg [WIDTH-1:0]    p;
reg                ci;

wire [WIDTH-1:0]   rslt;
wire               co;
 
reg                aldone;

always @(posedge clk)
    begin
    if (rst)
        begin
        a   <= INIT;
        b   <= INIT;
        p   <= INIT;
        ci  <= INIT;
        aldone  <= INIT;
        end
    else if (en)
        begin
        a   <= op1;
        b   <= op2;
        p   <= mod;
        ci  <= cin;
        aldone  <= INIT;
        end
    else
        begin
        a   <= rslt;
        p   <= p;
        case({ci,co})
            2'b00:  
                begin
                b   <= p;
                ci  <= aldone ? 1'b0: 1'b1;
                aldone  <= aldone;
                end
            2'b01: 
                begin
                b   <= p;
                ci  <= 1'b1;
                aldone  <= ~aldone;
                end
            2'b10:  
                begin
                b   <= p;
                ci  <= 1'b0;
                aldone  <= ~aldone;
                end
            2'b11:  
                begin
                b   <= p;
                ci  <= 1'b1;
                aldone  <= aldone;
                end
        endcase
        end
    end



aladder ialadder(
    .cin(ci),
    .clock(clk),
    .dataa(a),
    .datab(b),
    .cout(co),
    .result(rslt)
                 );



reg            stop;

wire           ovf;

assign         ovf = ci^co;

wire           endcon;
assign         endcon = ((rslt < p) && (!stop)) && (~ovf | aldone); 

always @(posedge clk)
    begin
    if (rst)
        begin
        sum <= INIT;
        vld <= INIT;
        stop    <= INIT;
        end
    else if (en)
        begin
        vld <= INIT;
        stop    <= INIT;
        end
    else if (endcon)
        begin
        sum <= rslt;
        vld <= 1'b1;
        stop    <= 1'b1;
        end
    else
        begin
        vld <= INIT;
        end
    end

endmodule
module modfa
    (
     clk,
     rst,
     op1,
     op2,
     mod,
     cin,
     en,
     sum,
     vld
     );





parameter WIDTH = 256;
parameter INIT  = 0;




input     clk;
input     rst;
input [WIDTH-1:0] op1;
input [WIDTH-1:0] op2;
input [WIDTH-1:0] mod;
input             cin;
input             en;

output [WIDTH-1:0] sum;
output             vld; 




reg [WIDTH-1:0]    sum;
reg                vld;




reg [WIDTH-1:0]    a, b;
reg [WIDTH-1:0]    p;
reg                ci;

wire [WIDTH-1:0]   rslt;
wire               co;
 
reg                aldone;

always @(posedge clk)
    begin
    if (rst)
        begin
        a   <= INIT;
        b   <= INIT;
        p   <= INIT;
        ci  <= INIT;
        aldone  <= INIT;
        end
    else if (en)
        begin
        a   <= op1;
        b   <= op2;
        p   <= mod;
        ci  <= cin;
        aldone  <= INIT;
        end
    else
        begin
        a   <= rslt;
        p   <= p;
        case({ci,co})
            2'b00:  
                begin
                b   <= p;
                ci  <= aldone ? 1'b0: 1'b1;
                aldone  <= aldone;
                end
            2'b01: 
                begin
                b   <= p;
                ci  <= 1'b1;
                aldone  <= ~aldone;
                end
            2'b10:  
                begin
                b   <= p;
                ci  <= 1'b0;
                aldone  <= ~aldone;
                end
            2'b11:  
                begin
                b   <= p;
                ci  <= 1'b1;
                aldone  <= aldone;
                end
        endcase
        end
    end



aladder ialadder(
    .cin(ci),
    .clock(clk),
    .dataa(a),
    .datab(b),
    .cout(co),
    .result(rslt)
                 );



reg            stop;

wire           ovf;

assign         ovf = ci^co;

wire           endcon;
assign         endcon = ((rslt < p) && (!stop)) && (~ovf | aldone); 

always @(posedge clk)
    begin
    if (rst)
        begin
        sum <= INIT;
        vld <= INIT;
        stop    <= INIT;
        end
    else if (en)
        begin
        vld <= INIT;
        stop    <= INIT;
        end
    else if (endcon)
        begin
        sum <= rslt;
        vld <= 1'b1;
        stop    <= 1'b1;
        end
    else
        begin
        vld <= INIT;
        end
    end

endmodule