data/full_repos/permissive/484799296/verilog/alu/top_tb.v
1: b'%Error: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:14: Unsupported or unknown PLI call: $monitor\n        $monitor("%b\\t%b\\t%b\\t%b\\t%d\\t%b\\t%b\\t%b\\t", S, A, B, C_in, n, Y, C, Z);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b0000; A=8\'b0000_0010; B=8\'b0000_0001; C_in=0; n=3\'b000;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b0001; A=8\'b0000_0011; B=8\'b0000_0110; C_in=0; n=3\'b000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b0010; A=8\'b0000_0011; B=8\'b0000_0110; C_in=0; n=3\'b000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b0011; A=8\'b1111_1111; B=8\'b0000_0000; C_in=0; n=3\'b000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b0100; A=8\'b1111_1111; B=8\'b0101_1010; C_in=0; n=3\'b000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b0101; A=8\'b0000_1111; B=8\'b0110_0001; C_in=0; n=3\'b000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b0101; A=8\'b0000_1111; B=8\'b1111_0001; C_in=0; n=3\'b000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b0110; A=8\'b0000_1000; B=8\'b0000_0001; C_in=0; n=3\'b000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b0110; A=8\'b0000_0000; B=8\'b0000_0001; C_in=0; n=3\'b000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b0110; A=8\'b0000_0001; B=8\'b0000_0001; C_in=0; n=3\'b000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b0111; A=8\'b1001_0110; B=8\'b1111_0000; C_in=0; n=3\'b000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b1000; A=8\'b1001_0110; B=8\'b1000_1111; C_in=0; n=3\'b000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b1001; A=8\'b1001_0110; B=8\'b1000_1111; C_in=0; n=3\'b000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b1001; A=8\'b1001_0110; B=8\'b0000_1111; C_in=1; n=3\'b000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b1010; A=8\'b1001_0110; B=8\'b1111_0001; C_in=0; n=3\'b000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b1011; A=8\'b1001_0110; B=8\'b1111_0001; C_in=0; n=3\'b000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b1011; A=8\'b1001_0110; B=8\'b1111_0000; C_in=1; n=3\'b000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b1100; A=8\'b1001_0110; B=8\'b0000_0011; C_in=1; n=3\'b000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b1100; A=8\'b1001_0110; B=8\'b1111_1111; C_in=1; n=3\'b000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b1101; A=8\'b1001_0110; B=8\'b0000_0011; C_in=1; n=3\'b000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b1101; A=8\'b1001_0110; B=8\'b0000_0000; C_in=1; n=3\'b000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b1110; A=8\'b1001_0110; B=8\'b1111_1111; C_in=1; n=3\'b000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b1110; A=8\'b1001_0110; B=8\'b1111_1111; C_in=1; n=3\'b001;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b1110; A=8\'b1001_0110; B=8\'b1111_1111; C_in=1; n=3\'b010;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b1110; A=8\'b1001_0110; B=8\'b1111_1111; C_in=1; n=3\'b011;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b1110; A=8\'b1001_0110; B=8\'b1111_1111; C_in=1; n=3\'b100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b1110; A=8\'b1001_0110; B=8\'b1111_1111; C_in=1; n=3\'b101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b1110; A=8\'b1001_0110; B=8\'b1111_1111; C_in=1; n=3\'b110;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b1110; A=8\'b1001_0110; B=8\'b1111_1111; C_in=1; n=3\'b111;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b1111; A=8\'b1001_0110; B=8\'b0000_0000; C_in=1; n=3\'b000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b1111; A=8\'b1001_0110; B=8\'b0000_0000; C_in=1; n=3\'b001;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b1111; A=8\'b1001_0110; B=8\'b0000_0000; C_in=1; n=3\'b010;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b1111; A=8\'b1001_0110; B=8\'b0000_0000; C_in=1; n=3\'b011;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b1111; A=8\'b1001_0110; B=8\'b0000_0000; C_in=1; n=3\'b100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b1111; A=8\'b1001_0110; B=8\'b0000_0000; C_in=1; n=3\'b101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b1111; A=8\'b1001_0110; B=8\'b0000_0000; C_in=1; n=3\'b110;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n        #1 S=4\'b1111; A=8\'b1001_0110; B=8\'b0000_0000; C_in=1; n=3\'b111;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/alu/top_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n        #2 $finish();\n        ^\n%Error: Exiting due to 1 error(s), 38 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench ();
    reg [7:0] A, B;
    reg [3:0] S;
    reg [2:0] n;
    reg C_in;
    wire [7:0] Y;
    wire C, Z;

    alu Alu(A, B, S, n, C_in, Y, C, Z);

    initial begin
        S=4'b0000; A=8'b0000_0000; B=8'b0000_0000; C_in=0; n=3'b000;
        $display("\nS\tA\t\tB\t\tC_in\tn\tY\t\tC\tZ");
        $monitor("%b\t%b\t%b\t%b\t%d\t%b\t%b\t%b\t", S, A, B, C_in, n, Y, C, Z);


        #1 S=4'b0000; A=8'b0000_0010; B=8'b0000_0001; C_in=0; n=3'b000;
        #1 S=4'b0001; A=8'b0000_0011; B=8'b0000_0110; C_in=0; n=3'b000;
        #1 S=4'b0010; A=8'b0000_0011; B=8'b0000_0110; C_in=0; n=3'b000;
        #1 S=4'b0011; A=8'b1111_1111; B=8'b0000_0000; C_in=0; n=3'b000;
        #1 S=4'b0100; A=8'b1111_1111; B=8'b0101_1010; C_in=0; n=3'b000;


        #1 S=4'b0101; A=8'b0000_1111; B=8'b0110_0001; C_in=0; n=3'b000;
        #1 S=4'b0101; A=8'b0000_1111; B=8'b1111_0001; C_in=0; n=3'b000;


        #1 S=4'b0110; A=8'b0000_1000; B=8'b0000_0001; C_in=0; n=3'b000;
        #1 S=4'b0110; A=8'b0000_0000; B=8'b0000_0001; C_in=0; n=3'b000;
        #1 S=4'b0110; A=8'b0000_0001; B=8'b0000_0001; C_in=0; n=3'b000;


        #1 S=4'b0111; A=8'b1001_0110; B=8'b1111_0000; C_in=0; n=3'b000;


        #1 S=4'b1000; A=8'b1001_0110; B=8'b1000_1111; C_in=0; n=3'b000;


        #1 S=4'b1001; A=8'b1001_0110; B=8'b1000_1111; C_in=0; n=3'b000;
        #1 S=4'b1001; A=8'b1001_0110; B=8'b0000_1111; C_in=1; n=3'b000;


        #1 S=4'b1010; A=8'b1001_0110; B=8'b1111_0001; C_in=0; n=3'b000;


        #1 S=4'b1011; A=8'b1001_0110; B=8'b1111_0001; C_in=0; n=3'b000;
        #1 S=4'b1011; A=8'b1001_0110; B=8'b1111_0000; C_in=1; n=3'b000;


        #1 S=4'b1100; A=8'b1001_0110; B=8'b0000_0011; C_in=1; n=3'b000;
        #1 S=4'b1100; A=8'b1001_0110; B=8'b1111_1111; C_in=1; n=3'b000;


        #1 S=4'b1101; A=8'b1001_0110; B=8'b0000_0011; C_in=1; n=3'b000;
        #1 S=4'b1101; A=8'b1001_0110; B=8'b0000_0000; C_in=1; n=3'b000;


        #1 S=4'b1110; A=8'b1001_0110; B=8'b1111_1111; C_in=1; n=3'b000;
        #1 S=4'b1110; A=8'b1001_0110; B=8'b1111_1111; C_in=1; n=3'b001;
        #1 S=4'b1110; A=8'b1001_0110; B=8'b1111_1111; C_in=1; n=3'b010;
        #1 S=4'b1110; A=8'b1001_0110; B=8'b1111_1111; C_in=1; n=3'b011;
        #1 S=4'b1110; A=8'b1001_0110; B=8'b1111_1111; C_in=1; n=3'b100;
        #1 S=4'b1110; A=8'b1001_0110; B=8'b1111_1111; C_in=1; n=3'b101;
        #1 S=4'b1110; A=8'b1001_0110; B=8'b1111_1111; C_in=1; n=3'b110;
        #1 S=4'b1110; A=8'b1001_0110; B=8'b1111_1111; C_in=1; n=3'b111;


        #1 S=4'b1111; A=8'b1001_0110; B=8'b0000_0000; C_in=1; n=3'b000;
        #1 S=4'b1111; A=8'b1001_0110; B=8'b0000_0000; C_in=1; n=3'b001;
        #1 S=4'b1111; A=8'b1001_0110; B=8'b0000_0000; C_in=1; n=3'b010;
        #1 S=4'b1111; A=8'b1001_0110; B=8'b0000_0000; C_in=1; n=3'b011;
        #1 S=4'b1111; A=8'b1001_0110; B=8'b0000_0000; C_in=1; n=3'b100;
        #1 S=4'b1111; A=8'b1001_0110; B=8'b0000_0000; C_in=1; n=3'b101;
        #1 S=4'b1111; A=8'b1001_0110; B=8'b0000_0000; C_in=1; n=3'b110;
        #1 S=4'b1111; A=8'b1001_0110; B=8'b0000_0000; C_in=1; n=3'b111;

        #2 $finish();
    end


endmodule
module testbench ();

    reg [7:0] A, B;
    reg [3:0] S;
    reg [2:0] n;
    reg C_in;
    wire [7:0] Y;
    wire C, Z;

    alu Alu(A, B, S, n, C_in, Y, C, Z);

    initial begin
        S=4'b0000; A=8'b0000_0000; B=8'b0000_0000; C_in=0; n=3'b000;
        $display("\nS\tA\t\tB\t\tC_in\tn\tY\t\tC\tZ");
        $monitor("%b\t%b\t%b\t%b\t%d\t%b\t%b\t%b\t", S, A, B, C_in, n, Y, C, Z);


        #1 S=4'b0000; A=8'b0000_0010; B=8'b0000_0001; C_in=0; n=3'b000;
        #1 S=4'b0001; A=8'b0000_0011; B=8'b0000_0110; C_in=0; n=3'b000;
        #1 S=4'b0010; A=8'b0000_0011; B=8'b0000_0110; C_in=0; n=3'b000;
        #1 S=4'b0011; A=8'b1111_1111; B=8'b0000_0000; C_in=0; n=3'b000;
        #1 S=4'b0100; A=8'b1111_1111; B=8'b0101_1010; C_in=0; n=3'b000;


        #1 S=4'b0101; A=8'b0000_1111; B=8'b0110_0001; C_in=0; n=3'b000;
        #1 S=4'b0101; A=8'b0000_1111; B=8'b1111_0001; C_in=0; n=3'b000;


        #1 S=4'b0110; A=8'b0000_1000; B=8'b0000_0001; C_in=0; n=3'b000;
        #1 S=4'b0110; A=8'b0000_0000; B=8'b0000_0001; C_in=0; n=3'b000;
        #1 S=4'b0110; A=8'b0000_0001; B=8'b0000_0001; C_in=0; n=3'b000;


        #1 S=4'b0111; A=8'b1001_0110; B=8'b1111_0000; C_in=0; n=3'b000;


        #1 S=4'b1000; A=8'b1001_0110; B=8'b1000_1111; C_in=0; n=3'b000;


        #1 S=4'b1001; A=8'b1001_0110; B=8'b1000_1111; C_in=0; n=3'b000;
        #1 S=4'b1001; A=8'b1001_0110; B=8'b0000_1111; C_in=1; n=3'b000;


        #1 S=4'b1010; A=8'b1001_0110; B=8'b1111_0001; C_in=0; n=3'b000;


        #1 S=4'b1011; A=8'b1001_0110; B=8'b1111_0001; C_in=0; n=3'b000;
        #1 S=4'b1011; A=8'b1001_0110; B=8'b1111_0000; C_in=1; n=3'b000;


        #1 S=4'b1100; A=8'b1001_0110; B=8'b0000_0011; C_in=1; n=3'b000;
        #1 S=4'b1100; A=8'b1001_0110; B=8'b1111_1111; C_in=1; n=3'b000;


        #1 S=4'b1101; A=8'b1001_0110; B=8'b0000_0011; C_in=1; n=3'b000;
        #1 S=4'b1101; A=8'b1001_0110; B=8'b0000_0000; C_in=1; n=3'b000;


        #1 S=4'b1110; A=8'b1001_0110; B=8'b1111_1111; C_in=1; n=3'b000;
        #1 S=4'b1110; A=8'b1001_0110; B=8'b1111_1111; C_in=1; n=3'b001;
        #1 S=4'b1110; A=8'b1001_0110; B=8'b1111_1111; C_in=1; n=3'b010;
        #1 S=4'b1110; A=8'b1001_0110; B=8'b1111_1111; C_in=1; n=3'b011;
        #1 S=4'b1110; A=8'b1001_0110; B=8'b1111_1111; C_in=1; n=3'b100;
        #1 S=4'b1110; A=8'b1001_0110; B=8'b1111_1111; C_in=1; n=3'b101;
        #1 S=4'b1110; A=8'b1001_0110; B=8'b1111_1111; C_in=1; n=3'b110;
        #1 S=4'b1110; A=8'b1001_0110; B=8'b1111_1111; C_in=1; n=3'b111;


        #1 S=4'b1111; A=8'b1001_0110; B=8'b0000_0000; C_in=1; n=3'b000;
        #1 S=4'b1111; A=8'b1001_0110; B=8'b0000_0000; C_in=1; n=3'b001;
        #1 S=4'b1111; A=8'b1001_0110; B=8'b0000_0000; C_in=1; n=3'b010;
        #1 S=4'b1111; A=8'b1001_0110; B=8'b0000_0000; C_in=1; n=3'b011;
        #1 S=4'b1111; A=8'b1001_0110; B=8'b0000_0000; C_in=1; n=3'b100;
        #1 S=4'b1111; A=8'b1001_0110; B=8'b0000_0000; C_in=1; n=3'b101;
        #1 S=4'b1111; A=8'b1001_0110; B=8'b0000_0000; C_in=1; n=3'b110;
        #1 S=4'b1111; A=8'b1001_0110; B=8'b0000_0000; C_in=1; n=3'b111;

        #2 $finish();
    end


endmodule