data/full_repos/permissive/461141714/src/Pipelined CPU/stage_ID.v
1: b'%Error: Cannot find file containing module: CPU,data/full_repos/permissive/461141714\n        ... Looked in:\n             data/full_repos/permissive/461141714/src/Pipelined/CPU,data/full_repos/permissive/461141714\n             data/full_repos/permissive/461141714/src/Pipelined/CPU,data/full_repos/permissive/461141714.v\n             data/full_repos/permissive/461141714/src/Pipelined/CPU,data/full_repos/permissive/461141714.sv\n             CPU,data/full_repos/permissive/461141714\n             CPU,data/full_repos/permissive/461141714.v\n             CPU,data/full_repos/permissive/461141714.sv\n             obj_dir/CPU,data/full_repos/permissive/461141714\n             obj_dir/CPU,data/full_repos/permissive/461141714.v\n             obj_dir/CPU,data/full_repos/permissive/461141714.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/461141714/src/Pipelined\n%Error: Cannot find file containing module: CPU/stage_ID.v\n%Error: Exiting due to 3 error(s)\n'
module STAGE_ID(
        input clk,
        input reset_n,
        

        input [1:0] addr1,
        input [1:0] addr2,
        input [1:0] addr3,
        output [`WORD_SIZE-1:0] data1,
        output [`WORD_SIZE-1:0] data2,
        input [`WORD_SIZE-1:0] data3,
        

        input rfWrite
    );
    
    RF register_file(
        .write(rfWrite),
        .clk(clk),
        .reset_n(reset_n),
        .addr1(addr1),
        .addr2(addr2),
        .addr3(addr3),
        .data1(data1),
        .data2(data2),
        .data3(data3)
    );
    
endmodule
module STAGE_ID(
        input clk,
        input reset_n,
        

        input [1:0] addr1,
        input [1:0] addr2,
        input [1:0] addr3,
        output [`WORD_SIZE-1:0] data1,
        output [`WORD_SIZE-1:0] data2,
        input [`WORD_SIZE-1:0] data3,
        

        input rfWrite
    );

    
    RF register_file(
        .write(rfWrite),
        .clk(clk),
        .reset_n(reset_n),
        .addr1(addr1),
        .addr2(addr2),
        .addr3(addr3),
        .data1(data1),
        .data2(data2),
        .data3(data3)
    );
    
endmodule