data/full_repos/permissive/467771222/Dualedge.v
1: b'%Warning-MODDUP: data/full_repos/permissive/467771222/Dualedge.v:25: Duplicate declaration of module: \'top_module\'\nmodule top_module(\n       ^~~~~~~~~~\n                 data/full_repos/permissive/467771222/Dualedge.v:3: ... Location of original declaration\nmodule top_module (\n       ^~~~~~~~~~\n                 ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Error-PROCASSWIRE: data/full_repos/permissive/467771222/Dualedge.v:17: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'q\'\n                                                                      : ... In instance top_module\n            q <= temp1;\n            ^\n%Error-PROCASSWIRE: data/full_repos/permissive/467771222/Dualedge.v:19: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'q\'\n                                                                      : ... In instance top_module\n            q <= temp2;\n            ^\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module top_module (
    input clk,
    input d,
    output q
);
    reg temp1, temp2;
    always@(posedge clk)begin
        temp1 <= d;
    end
    always@(negedge clk)begin
        temp2 <= d;
    end
    always@(clk) begin
        if(clk)
            q <= temp1;
        else
            q <= temp2;
    end

endmodule
module top_module (
    input clk,
    input d,
    output q
);

    reg temp1, temp2;
    always@(posedge clk)begin
        temp1 <= d;
    end
    always@(negedge clk)begin
        temp2 <= d;
    end
    always@(clk) begin
        if(clk)
            q <= temp1;
        else
            q <= temp2;
    end

endmodule