data/full_repos/permissive/451853158/MIPS_Pipeline_Processor/alu.v
data/verilator_xmls/3721c804-8706-4b62-b77f-99c1fb7e76e3.xml
module alu (
  input [31:0] srcA, srcB,
  input [2:0]  ALUCtrl,
  output reg [31:0] ALUResult,
  output wire        Z
);

always @(*)
  casex(ALUCtrl)
    3'b000: ALUResult = srcA & srcB;
    3'b001: ALUResult = srcA | srcB;
    3'b010: ALUResult = srcA + srcB;
    3'b110: ALUResult = srcA - srcB;
    3'b111: begin
      if (srcA[31] ^ srcB[31]) ALUResult = {31'b0,srcA[31]};
      else begin
        if (srcA < srcB) ALUResult = 32'b1;
        else             ALUResult = 32'b0;
      end
    end
    default: ALUResult = 32'bx;
  endcase

assign Z = (ALUResult != 32'b0) ? 1'b0 : 1'b1;

endmodule
module alu (
  input [31:0] srcA, srcB,
  input [2:0]  ALUCtrl,
  output reg [31:0] ALUResult,
  output wire        Z
);


always @(*)
  casex(ALUCtrl)
    3'b000: ALUResult = srcA & srcB;
    3'b001: ALUResult = srcA | srcB;
    3'b010: ALUResult = srcA + srcB;
    3'b110: ALUResult = srcA - srcB;
    3'b111: begin
      if (srcA[31] ^ srcB[31]) ALUResult = {31'b0,srcA[31]};
      else begin
        if (srcA < srcB) ALUResult = 32'b1;
        else             ALUResult = 32'b0;
      end
    end
    default: ALUResult = 32'bx;
  endcase

assign Z = (ALUResult != 32'b0) ? 1'b0 : 1'b1;

endmodule