data/full_repos/permissive/528831163/src/boron_dec.v
1: b'%Warning-WIDTH: data/full_repos/permissive/528831163/src/boron_dec.v:72: Value too large for 5 bit number: 50\n            reg_round_counter <= 5\'d50;\n                                 ^~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/528831163/src/boron_dec.v:17: Cannot find file containing module: \'key_scheduler\'\n    key_scheduler ks(.clk(clk), .rst(rst), .round_counter(reg_round_counter), .i_ks_oldkey(reg_key), .o_ks_newkey(reg_nextkey));\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/528831163/src,data/full_repos/permissive/528831163/key_scheduler\n             data/full_repos/permissive/528831163/src,data/full_repos/permissive/528831163/key_scheduler.v\n             data/full_repos/permissive/528831163/src,data/full_repos/permissive/528831163/key_scheduler.sv\n             key_scheduler\n             key_scheduler.v\n             key_scheduler.sv\n             obj_dir/key_scheduler\n             obj_dir/key_scheduler.v\n             obj_dir/key_scheduler.sv\n%Error: data/full_repos/permissive/528831163/src/boron_dec.v:18: Cannot find file containing module: \'dec_key_scheduler\'\n    dec_key_scheduler dks(.clk(clk), .rst(rst), .round_counter(reg_round_counter), .i_ks_oldkey(reg_key), .o_ks_newkey(dec_reg_nextkey));\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/528831163/src/boron_dec.v:19: Cannot find file containing module: \'dec_add_round_key\'\n    dec_add_round_key ark(.i_ark_cipher(reg_plaintext), .i_ark_key(dec_reg_nextkey[63:0]), .o_ark_msg(reg_nextplaintext));\n    ^~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/528831163/src/boron_dec.v:42: Operator XOR expects 80 bits on the RHS, but RHS\'s VARREF \'plain_text\' generates 64 bits.\n                                                                       : ... In instance boron_dec\n                    reg_plaintext <=(reg_nextkey ^ plain_text);\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/528831163/src/boron_dec.v:42: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s XOR generates 80 bits.\n                                                                       : ... In instance boron_dec\n                    reg_plaintext <=(reg_nextkey ^ plain_text);\n                                  ^~\n%Error: Exiting due to 3 error(s), 3 warning(s)\n'
module boron_dec (
    input  clk, rst, start, [63:0] plain_text, [79:0] master_key,  
    output reg done, reg [63:0] cipher_text 
);


    parameter IDLE = 3'b000, KEYGEN = 3'b011, ROUND = 3'b001, FINAL = 3'b010;

    reg [2:0] reg_sm_main = 3'b0;
    reg [4:0] reg_round_counter = 5'd0;

    reg [63:0] reg_plaintext;
    wire [63:0] reg_nextplaintext;
    reg [79:0] reg_key;
    wire [79:0] reg_nextkey, dec_reg_nextkey;

    key_scheduler ks(.clk(clk), .rst(rst), .round_counter(reg_round_counter), .i_ks_oldkey(reg_key), .o_ks_newkey(reg_nextkey));
    dec_key_scheduler dks(.clk(clk), .rst(rst), .round_counter(reg_round_counter), .i_ks_oldkey(reg_key), .o_ks_newkey(dec_reg_nextkey));
    dec_add_round_key ark(.i_ark_cipher(reg_plaintext), .i_ark_key(dec_reg_nextkey[63:0]), .o_ark_msg(reg_nextplaintext));



    always @(negedge clk ) begin
        case (reg_sm_main)
            IDLE:
                if(start) begin
                   reg_plaintext <= plain_text; 
                    reg_key <= master_key;
                   reg_sm_main <= KEYGEN;
                   reg_round_counter <= 5'b0;
                end
                else
                    reg_sm_main <= IDLE;
            KEYGEN:
                if(reg_round_counter < 25) begin
                    reg_key <= reg_nextkey;
                   reg_sm_main <= KEYGEN;
                                    
                end else begin
                    reg_sm_main <= ROUND;
                    reg_round_counter <= 5'd26;
                    reg_plaintext <=(reg_nextkey ^ plain_text);
                    reg_key <= reg_nextkey;
                end
            ROUND:
                if(reg_round_counter > 0) begin
                   reg_plaintext <= reg_nextplaintext;
                   reg_key <= dec_reg_nextkey;
                    reg_sm_main <= ROUND;
                end
                else if(reg_round_counter == 0) begin
                    


                    reg_sm_main <= FINAL;
                end

            FINAL: 
            begin
                
                
                done <= 1'b1;
            end
                 
            default: 
                reg_sm_main <= IDLE;
        endcase
    end

    always @(posedge clk ) begin
        if(!rst ) begin
            reg_round_counter <= 5'd50;
        end
        else if(reg_sm_main == KEYGEN)
            reg_round_counter <= reg_round_counter + 1;
        else if(reg_sm_main == ROUND) begin
            reg_round_counter <= reg_round_counter - 1;
        end
    end

    
endmodule
module boron_dec (
    input  clk, rst, start, [63:0] plain_text, [79:0] master_key,  
    output reg done, reg [63:0] cipher_text 
);



    parameter IDLE = 3'b000, KEYGEN = 3'b011, ROUND = 3'b001, FINAL = 3'b010;

    reg [2:0] reg_sm_main = 3'b0;
    reg [4:0] reg_round_counter = 5'd0;

    reg [63:0] reg_plaintext;
    wire [63:0] reg_nextplaintext;
    reg [79:0] reg_key;
    wire [79:0] reg_nextkey, dec_reg_nextkey;

    key_scheduler ks(.clk(clk), .rst(rst), .round_counter(reg_round_counter), .i_ks_oldkey(reg_key), .o_ks_newkey(reg_nextkey));
    dec_key_scheduler dks(.clk(clk), .rst(rst), .round_counter(reg_round_counter), .i_ks_oldkey(reg_key), .o_ks_newkey(dec_reg_nextkey));
    dec_add_round_key ark(.i_ark_cipher(reg_plaintext), .i_ark_key(dec_reg_nextkey[63:0]), .o_ark_msg(reg_nextplaintext));



    always @(negedge clk ) begin
        case (reg_sm_main)
            IDLE:
                if(start) begin
                   reg_plaintext <= plain_text; 
                    reg_key <= master_key;
                   reg_sm_main <= KEYGEN;
                   reg_round_counter <= 5'b0;
                end
                else
                    reg_sm_main <= IDLE;
            KEYGEN:
                if(reg_round_counter < 25) begin
                    reg_key <= reg_nextkey;
                   reg_sm_main <= KEYGEN;
                                    
                end else begin
                    reg_sm_main <= ROUND;
                    reg_round_counter <= 5'd26;
                    reg_plaintext <=(reg_nextkey ^ plain_text);
                    reg_key <= reg_nextkey;
                end
            ROUND:
                if(reg_round_counter > 0) begin
                   reg_plaintext <= reg_nextplaintext;
                   reg_key <= dec_reg_nextkey;
                    reg_sm_main <= ROUND;
                end
                else if(reg_round_counter == 0) begin
                    


                    reg_sm_main <= FINAL;
                end

            FINAL: 
            begin
                
                
                done <= 1'b1;
            end
                 
            default: 
                reg_sm_main <= IDLE;
        endcase
    end

    always @(posedge clk ) begin
        if(!rst ) begin
            reg_round_counter <= 5'd50;
        end
        else if(reg_sm_main == KEYGEN)
            reg_round_counter <= reg_round_counter + 1;
        else if(reg_sm_main == ROUND) begin
            reg_round_counter <= reg_round_counter - 1;
        end
    end

    
endmodule