data/full_repos/permissive/497337299/basics/tb/tb_adder.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_adder.v:10: Unsupported: Ignoring delay on this delayed statement.\n        #0      a=0;  b=0; cin=0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_adder.v:11: Unsupported: Ignoring delay on this delayed statement.\n        #20     a=10; b=3; cin=1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_adder.v:12: Unsupported: Ignoring delay on this delayed statement.\n        #20     a=6;  b=9; cin=1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_adder.v:13: Unsupported: Ignoring delay on this delayed statement.\n        #20     a=9;  b=3; cin=0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_adder.v:14: Unsupported: Ignoring delay on this delayed statement.\n        #20     a=15; b=15; cin=1;     \n        ^\n%Error: data/full_repos/permissive/497337299/basics/tb/tb_adder.v:7: Cannot find file containing module: \'adder\'\n    adder dut (.a(a),.b(b),.cin(cin),.result(result));\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/497337299/basics/tb,data/full_repos/permissive/497337299/adder\n             data/full_repos/permissive/497337299/basics/tb,data/full_repos/permissive/497337299/adder.v\n             data/full_repos/permissive/497337299/basics/tb,data/full_repos/permissive/497337299/adder.sv\n             adder\n             adder.v\n             adder.sv\n             obj_dir/adder\n             obj_dir/adder.v\n             obj_dir/adder.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();
    reg [3:0] a,b;
    reg cin;
    wire [4:0] result;

    adder dut (.a(a),.b(b),.cin(cin),.result(result));

    initial begin
        #0      a=0;  b=0; cin=0;
        #20     a=10; b=3; cin=1;
        #20     a=6;  b=9; cin=1;
        #20     a=9;  b=3; cin=0;
        #20     a=15; b=15; cin=1;     
    end
endmodule
module testbench();

    reg [3:0] a,b;
    reg cin;
    wire [4:0] result;

    adder dut (.a(a),.b(b),.cin(cin),.result(result));

    initial begin
        #0      a=0;  b=0; cin=0;
        #20     a=10; b=3; cin=1;
        #20     a=6;  b=9; cin=1;
        #20     a=9;  b=3; cin=0;
        #20     a=15; b=15; cin=1;     
    end
endmodule