data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_stim_mem/rtl/wfg_stim_mem.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_stim_mem/rtl/wfg_stim_mem.sv:86: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'cfg_inc_q_i\' generates 8 bits.\n                                                                                                        : ... In instance wfg_stim_mem\n                        cur_address <= cur_address + cfg_inc_q_i;\n                                                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_stim_mem/rtl/wfg_stim_mem.sv:83: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'cfg_inc_q_i\' generates 8 bits.\n                                                                                                        : ... In instance wfg_stim_mem\n                    if (cur_address + cfg_inc_q_i > end_val_q_i) begin\n                                    ^\n%Error: data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_stim_mem/rtl/wfg_stim_mem.sv:100: Cannot find file containing module: \'dsp_scale_sn_us\'\n    dsp_scale_sn_us #(\n    ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_stim_mem/rtl,data/full_repos/permissive/500717851/dsp_scale_sn_us\n             data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_stim_mem/rtl,data/full_repos/permissive/500717851/dsp_scale_sn_us.v\n             data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_stim_mem/rtl,data/full_repos/permissive/500717851/dsp_scale_sn_us.sv\n             dsp_scale_sn_us\n             dsp_scale_sn_us.v\n             dsp_scale_sn_us.sv\n             obj_dir/dsp_scale_sn_us\n             obj_dir/dsp_scale_sn_us.v\n             obj_dir/dsp_scale_sn_us.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module wfg_stim_mem (
    input wire clk,
    input wire rst_n,

    input  wire        wfg_axis_tready_i,
    output wire        wfg_axis_tvalid_o,
    output wire [31:0] wfg_axis_tdata_o,

    input wire         ctrl_en_q_i,
    input logic [15:0] end_val_q_i,
    input logic [15:0] start_val_q_i,
    input logic [ 7:0] cfg_inc_q_i,
    input logic [15:0] cfg_gain_q_i,


    output              csb1,
    output       [ 9:0] addr1,
    input  logic [31:0] dout1
);
    logic [15:0] cur_address;
    logic [31:0] data;
    logic [31:0] data_calc;
    logic valid;

    assign csb1              = !ctrl_en_q_i;
    assign addr1             = cur_address[9:0];

    assign wfg_axis_tvalid_o = valid;
    assign wfg_axis_tdata_o  = data;

    typedef enum {
        ST_IDLE,
        ST_READ,
        ST_CALC,
        ST_DONE
    } wfg_stim_mem_states_t;

    wfg_stim_mem_states_t cur_state;
    wfg_stim_mem_states_t next_state;

    always_ff @(posedge clk, negedge rst_n) begin
        if (!rst_n) cur_state <= ST_IDLE;
        else cur_state <= next_state;
    end

    always_comb begin
        next_state = cur_state;
        case (cur_state)
            ST_IDLE: begin
                if (ctrl_en_q_i) next_state = ST_READ;
            end
            ST_READ: begin
                next_state = ST_CALC;
            end
            ST_CALC: begin
                next_state = ST_DONE;
            end
            ST_DONE: begin
                if (wfg_axis_tready_i == 1'b1) next_state = ST_IDLE;
            end
        endcase
    end

    always_ff @(posedge clk, negedge rst_n) begin
        if (!rst_n) begin
            cur_address <= '0;
            valid <= '0;
            data <= '0;
        end else begin
            valid <= '0;

            case (cur_state)
                ST_IDLE: begin
                    if (!ctrl_en_q_i) begin
                        cur_address <= start_val_q_i;
                    end
                end
                ST_READ: begin
                    if (cur_address + cfg_inc_q_i > end_val_q_i) begin
                        cur_address <= start_val_q_i;
                    end else begin
                        cur_address <= cur_address + cfg_inc_q_i;
                    end
                end
                ST_CALC: begin
                    data <= data_calc;
                end
                ST_DONE: begin
                    valid <= '1;
                end
                default: valid <= 'x;
            endcase
        end
    end

    dsp_scale_sn_us #(
        .DATA_W(32),
        .SCALE_W(16),
        .SCALE_SHFT(0)
    ) dsp_scale_sn_us_inst (
        .clk     (clk),
        .reset_ni(rst_n),


        .scale_gif_data_in_update_i(next_state == ST_CALC),
        .scale_gif_data_in_i       (dout1),
        .scale_factor_i            (cfg_gain_q_i),
        .scale_gif_result_update_o (),
        .scale_gif_result_o        (data_calc)
    );

endmodule
module wfg_stim_mem (
    input wire clk,
    input wire rst_n,

    input  wire        wfg_axis_tready_i,
    output wire        wfg_axis_tvalid_o,
    output wire [31:0] wfg_axis_tdata_o,

    input wire         ctrl_en_q_i,
    input logic [15:0] end_val_q_i,
    input logic [15:0] start_val_q_i,
    input logic [ 7:0] cfg_inc_q_i,
    input logic [15:0] cfg_gain_q_i,


    output              csb1,
    output       [ 9:0] addr1,
    input  logic [31:0] dout1
);

    logic [15:0] cur_address;
    logic [31:0] data;
    logic [31:0] data_calc;
    logic valid;

    assign csb1              = !ctrl_en_q_i;
    assign addr1             = cur_address[9:0];

    assign wfg_axis_tvalid_o = valid;
    assign wfg_axis_tdata_o  = data;

    typedef enum {
        ST_IDLE,
        ST_READ,
        ST_CALC,
        ST_DONE
    } wfg_stim_mem_states_t;

    wfg_stim_mem_states_t cur_state;
    wfg_stim_mem_states_t next_state;

    always_ff @(posedge clk, negedge rst_n) begin
        if (!rst_n) cur_state <= ST_IDLE;
        else cur_state <= next_state;
    end

    always_comb begin
        next_state = cur_state;
        case (cur_state)
            ST_IDLE: begin
                if (ctrl_en_q_i) next_state = ST_READ;
            end
            ST_READ: begin
                next_state = ST_CALC;
            end
            ST_CALC: begin
                next_state = ST_DONE;
            end
            ST_DONE: begin
                if (wfg_axis_tready_i == 1'b1) next_state = ST_IDLE;
            end
        endcase
    end

    always_ff @(posedge clk, negedge rst_n) begin
        if (!rst_n) begin
            cur_address <= '0;
            valid <= '0;
            data <= '0;
        end else begin
            valid <= '0;

            case (cur_state)
                ST_IDLE: begin
                    if (!ctrl_en_q_i) begin
                        cur_address <= start_val_q_i;
                    end
                end
                ST_READ: begin
                    if (cur_address + cfg_inc_q_i > end_val_q_i) begin
                        cur_address <= start_val_q_i;
                    end else begin
                        cur_address <= cur_address + cfg_inc_q_i;
                    end
                end
                ST_CALC: begin
                    data <= data_calc;
                end
                ST_DONE: begin
                    valid <= '1;
                end
                default: valid <= 'x;
            endcase
        end
    end

    dsp_scale_sn_us #(
        .DATA_W(32),
        .SCALE_W(16),
        .SCALE_SHFT(0)
    ) dsp_scale_sn_us_inst (
        .clk     (clk),
        .reset_ni(rst_n),


        .scale_gif_data_in_update_i(next_state == ST_CALC),
        .scale_gif_data_in_i       (dout1),
        .scale_factor_i            (cfg_gain_q_i),
        .scale_gif_result_update_o (),
        .scale_gif_result_o        (data_calc)
    );

endmodule