data/full_repos/permissive/420070038/examples/bootloader/fusesoc/rtl/pulse_button.v
data/verilator_xmls/73a8f735-4471-4ae9-a313-727534f83501.xml
module biestable_d(
	input clk,
	input reset,
	input d,
	output reg q,
	output not_q);

always @(posedge clk)
begin
	if(reset == 1'b1)
		q <= 1'b0;
	else
		q <= d;
end

assign not_q = ~q;

endmodule
module biestable_d(
	input clk,
	input reset,
	input d,
	output reg q,
	output not_q);


always @(posedge clk)
begin
	if(reset == 1'b1)
		q <= 1'b0;
	else
		q <= d;
end

assign not_q = ~q;

endmodule