data/full_repos/permissive/528677531/LAB-3/Q4/q4.v
data/verilator_xmls/ff4caa9e-9cc0-4825-a8d1-64c810c156e4.xml
module q4(A,B,C,D,f);
input A,B,C,D;
output f;
assign f=~(~(~(A|A)|~(C|C))|~(D|D));
endmodule
module q4(A,B,C,D,f);

input A,B,C,D;
output f;
assign f=~(~(~(A|A)|~(C|C))|~(D|D));
endmodule