data/full_repos/permissive/489994352/Image-Part/toplevelv2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/489994352/Image-Part/toplevelv2.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/489994352/Image-Part/toplevelv2.v:19: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk=~clk;\n       ^\n%Error: data/full_repos/permissive/489994352/Image-Part/toplevelv2.v:24: Cannot find file containing module: \'inputimage\'\ninputimage img (.clk(clk),.rst(rst),.dataout(imgdata),.en(conv1valid));\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489994352/Image-Part,data/full_repos/permissive/489994352/inputimage\n             data/full_repos/permissive/489994352/Image-Part,data/full_repos/permissive/489994352/inputimage.v\n             data/full_repos/permissive/489994352/Image-Part,data/full_repos/permissive/489994352/inputimage.sv\n             inputimage\n             inputimage.v\n             inputimage.sv\n             obj_dir/inputimage\n             obj_dir/inputimage.v\n             obj_dir/inputimage.sv\n%Error: data/full_repos/permissive/489994352/Image-Part/toplevelv2.v:25: Cannot find file containing module: \'conv1v2\'\nconv1v2 conv1 (.clk(clk),.rst(rst),.imgdata(imgdata),.i_data_valid(conv1start), .output_imw(output_imw),.o_convolved_data_valid(conv1valid));\n^~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module toplevelv2();
reg clk, rst;
wire [16*9*3-1:0] imgdata;
reg conv1start;
reg [16-1:0] output_im [0:64-1];
wire [16*64-1:0] output_imw;
integer file;
reg i_data_valid;
wire conv1valid;
initial begin
    clk = 0;
    rst = 1;
    #10;
    rst = 0;
    conv1start = 1;

    file = $fopen("opfconv1.txt","w");
end
always #5 clk=~clk;
integer i;
always @(*)
    for (i=0; i<64; i=i+1)
        output_im[i]=output_imw[i*16+:16];
inputimage img (.clk(clk),.rst(rst),.dataout(imgdata),.en(conv1valid));
conv1v2 conv1 (.clk(clk),.rst(rst),.imgdata(imgdata),.i_data_valid(conv1start), .output_imw(output_imw),.o_convolved_data_valid(conv1valid));
integer sentsize = 0;
always@(posedge clk)
begin
   if(conv1valid) begin
       $fwrite(file,"%h\n",output_im[0]);
       sentsize <= sentsize+'d1;
       if(sentsize=='d12321) begin
           i_data_valid = 0;

       end
   end
end
endmodule
module toplevelv2();

reg clk, rst;
wire [16*9*3-1:0] imgdata;
reg conv1start;
reg [16-1:0] output_im [0:64-1];
wire [16*64-1:0] output_imw;
integer file;
reg i_data_valid;
wire conv1valid;
initial begin
    clk = 0;
    rst = 1;
    #10;
    rst = 0;
    conv1start = 1;

    file = $fopen("opfconv1.txt","w");
end
always #5 clk=~clk;
integer i;
always @(*)
    for (i=0; i<64; i=i+1)
        output_im[i]=output_imw[i*16+:16];
inputimage img (.clk(clk),.rst(rst),.dataout(imgdata),.en(conv1valid));
conv1v2 conv1 (.clk(clk),.rst(rst),.imgdata(imgdata),.i_data_valid(conv1start), .output_imw(output_imw),.o_convolved_data_valid(conv1valid));
integer sentsize = 0;
always@(posedge clk)
begin
   if(conv1valid) begin
       $fwrite(file,"%h\n",output_im[0]);
       sentsize <= sentsize+'d1;
       if(sentsize=='d12321) begin
           i_data_valid = 0;

       end
   end
end
endmodule