data/full_repos/permissive/46981098/sign_extend/tb_sign_extended.v
1: b'%Error: data/full_repos/permissive/46981098/sign_extend/tb_sign_extended.v:11: Unsupported or unknown PLI call: $monitor\n      $monitor("A = %b B = %b",in,out);\n      ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/46981098/sign_extend/tb_sign_extended.v:12: Unsupported: Ignoring delay on this delayed statement.\n      #10 in=16\'b1111111111111111;  \n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/46981098/sign_extend/tb_sign_extended.v:13: Unsupported: Ignoring delay on this delayed statement.\n      #10 in=16\'b0000000000000000;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/46981098/sign_extend/tb_sign_extended.v:14: Unsupported: Ignoring delay on this delayed statement.\n      #10 in=16\'b0101010101010101;\n      ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_sign_extended;
  reg [15:0] in;
  wire [31:0] out; 
  
  sign_extended SE1(in, out);
  initial
    begin
      $display("RESULT");
      $monitor("A = %b B = %b",in,out);
      #10 in=16'b1111111111111111;  
      #10 in=16'b0000000000000000;
      #10 in=16'b0101010101010101;
    end
endmodule
module tb_sign_extended;

  reg [15:0] in;
  wire [31:0] out; 
  
  sign_extended SE1(in, out);
  initial
    begin
      $display("RESULT");
      $monitor("A = %b B = %b",in,out);
      #10 in=16'b1111111111111111;  
      #10 in=16'b0000000000000000;
      #10 in=16'b0101010101010101;
    end
endmodule