data/full_repos/permissive/43856783/Direccion/peripheral_direccion.v
1: b"%Error: data/full_repos/permissive/43856783/Direccion/peripheral_direccion.v:49: Cannot find file containing module: 'direccion'\n direccion direccion1 ( .reversa(reversa[0]) , .adelante(adelante[0]) , .atras(atras[0]) ) ;\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43856783/Direccion,data/full_repos/permissive/43856783/direccion\n             data/full_repos/permissive/43856783/Direccion,data/full_repos/permissive/43856783/direccion.v\n             data/full_repos/permissive/43856783/Direccion,data/full_repos/permissive/43856783/direccion.sv\n             direccion\n             direccion.v\n             direccion.sv\n             obj_dir/direccion\n             obj_dir/direccion.v\n             obj_dir/direccion.sv\n%Error: data/full_repos/permissive/43856783/Direccion/peripheral_direccion.v:50: Cannot find file containing module: 'direccion'\n direccion direccion2 ( .reversa(reversa[1]) , .adelante(adelante[1]) , .atras(atras[1]) ) ;\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module peripheral_uart (

	input 			clk,
	input 			rst,
	input [15:0]	d_in,
	input 			cs,
	input [3:0]		addr,
	input 			rd,
	input 			wr,
	
	output reg [15:0] d_out,
	

	output [1:0] adelante ,
	output [1:0] atras 
	);
	


	reg [1:0] s;
	reg [1:0] reversa;



	always @(*) begin
		case(addr)
			4'h0:		s = (cs && wr) ? 2'b01 : 2'b00 ;
			4'h2:		s = (cs && wr) ? 2'b10 : 2'b00 ;
			default: 	s = 2'b00 ;
		endcase
	end

	always @(negedge clk) begin
		case (s)
			2'b01: 	reversa[0] = d_in[0] ; 
			2'b10: 	reversa[1] = d_in[0] ; 
			default: begin
				reversa[0] = 0 ;
				reversa[1] = 0 ;
			end
		endcase
	end
	
	direccion direccion1 ( .reversa(reversa[0]) , .adelante(adelante[0]) , .atras(atras[0]) ) ;
	direccion direccion2 ( .reversa(reversa[1]) , .adelante(adelante[1]) , .atras(atras[1]) ) ;

endmodule
module peripheral_uart (

	input 			clk,
	input 			rst,
	input [15:0]	d_in,
	input 			cs,
	input [3:0]		addr,
	input 			rd,
	input 			wr,
	
	output reg [15:0] d_out,
	

	output [1:0] adelante ,
	output [1:0] atras 
	);

	


	reg [1:0] s;
	reg [1:0] reversa;



	always @(*) begin
		case(addr)
			4'h0:		s = (cs && wr) ? 2'b01 : 2'b00 ;
			4'h2:		s = (cs && wr) ? 2'b10 : 2'b00 ;
			default: 	s = 2'b00 ;
		endcase
	end

	always @(negedge clk) begin
		case (s)
			2'b01: 	reversa[0] = d_in[0] ; 
			2'b10: 	reversa[1] = d_in[0] ; 
			default: begin
				reversa[0] = 0 ;
				reversa[1] = 0 ;
			end
		endcase
	end
	
	direccion direccion1 ( .reversa(reversa[0]) , .adelante(adelante[0]) , .atras(atras[0]) ) ;
	direccion direccion2 ( .reversa(reversa[1]) , .adelante(adelante[1]) , .atras(atras[1]) ) ;

endmodule