data/full_repos/permissive/440517687/verilog/gl/user_project_wrapper.v
1: b"%Error: data/full_repos/permissive/440517687/verilog/gl/user_project_wrapper.v:86: Cannot find file containing module: 'user_project_core_lambdasoc_cts'\n    user_project_core_lambdasoc_cts core(\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/440517687/verilog/gl,data/full_repos/permissive/440517687/user_project_core_lambdasoc_cts\n             data/full_repos/permissive/440517687/verilog/gl,data/full_repos/permissive/440517687/user_project_core_lambdasoc_cts.v\n             data/full_repos/permissive/440517687/verilog/gl,data/full_repos/permissive/440517687/user_project_core_lambdasoc_cts.sv\n             user_project_core_lambdasoc_cts\n             user_project_core_lambdasoc_cts.v\n             user_project_core_lambdasoc_cts.sv\n             obj_dir/user_project_core_lambdasoc_cts\n             obj_dir/user_project_core_lambdasoc_cts.v\n             obj_dir/user_project_core_lambdasoc_cts.sv\n%Error: Exiting due to 1 error(s)\n"
module via4_3100x3100(
    input vccd1,
    input vssd1
);

endmodule
module via4_3100x3100(
    input vccd1,
    input vssd1
);


endmodule