data/full_repos/permissive/444559342/mp1/multiplier/hdl/add_shift_multiplier.sv
1: b"%Error: data/full_repos/permissive/444559342/mp1/multiplier/hdl/add_shift_multiplier.sv:1: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport mult_types::*;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/444559342/mp1/multiplier/hdl/add_shift_multiplier.sv:42: syntax error, unexpected IDENTIFIER, expecting ')'\nfunction void reset(output mstate_s ms_next);\n                                    ^~~~~~~\n%Error: data/full_repos/permissive/444559342/mp1/multiplier/hdl/add_shift_multiplier.sv:44: syntax error, unexpected '=', expecting IDENTIFIER\n    ms_next.ready = 1'b1;\n                  ^\n%Error: data/full_repos/permissive/444559342/mp1/multiplier/hdl/add_shift_multiplier.sv:51: syntax error, unexpected '=', expecting IDENTIFIER\n    ms_next.ready = 1'b0;\n                  ^\n%Error: data/full_repos/permissive/444559342/mp1/multiplier/hdl/add_shift_multiplier.sv:52: syntax error, unexpected '=', expecting IDENTIFIER\n    ms_next.done = 1'b0;\n                 ^\n%Error: data/full_repos/permissive/444559342/mp1/multiplier/hdl/add_shift_multiplier.sv:53: syntax error, unexpected '=', expecting IDENTIFIER\n    ms_next.iteration = 0;\n                      ^\n%Error: data/full_repos/permissive/444559342/mp1/multiplier/hdl/add_shift_multiplier.sv:54: syntax error, unexpected '=', expecting IDENTIFIER\n    ms_next.op = ADD;\n               ^\n%Error: data/full_repos/permissive/444559342/mp1/multiplier/hdl/add_shift_multiplier.sv:56: syntax error, unexpected '=', expecting IDENTIFIER\n    ms_next.M = multiplicand;\n              ^\n%Error: data/full_repos/permissive/444559342/mp1/multiplier/hdl/add_shift_multiplier.sv:57: syntax error, unexpected '=', expecting IDENTIFIER\n    ms_next.C = 1'b0;\n              ^\n%Error: data/full_repos/permissive/444559342/mp1/multiplier/hdl/add_shift_multiplier.sv:58: syntax error, unexpected '=', expecting IDENTIFIER\n    ms_next.A = 0;\n              ^\n%Error: data/full_repos/permissive/444559342/mp1/multiplier/hdl/add_shift_multiplier.sv:59: syntax error, unexpected '=', expecting IDENTIFIER\n    ms_next.Q = multiplier;\n              ^\n%Error: data/full_repos/permissive/444559342/mp1/multiplier/hdl/add_shift_multiplier.sv:65: syntax error, unexpected '=', expecting IDENTIFIER\n    next.op = SHIFT;\n            ^\n%Error: data/full_repos/permissive/444559342/mp1/multiplier/hdl/add_shift_multiplier.sv:67: syntax error, unexpected '{'\n        {next.C, next.A} = cur.A + cur.M;\n        ^\n%Error: data/full_repos/permissive/444559342/mp1/multiplier/hdl/add_shift_multiplier.sv:69: syntax error, unexpected '=', expecting IDENTIFIER\n        next.C = 1'b0;\n               ^\n%Error: data/full_repos/permissive/444559342/mp1/multiplier/hdl/add_shift_multiplier.sv:76: syntax error, unexpected '=', expecting IDENTIFIER\n      next.op = ADD;\n              ^\n%Error: data/full_repos/permissive/444559342/mp1/multiplier/hdl/add_shift_multiplier.sv:77: syntax error, unexpected +=, expecting IDENTIFIER\n      next.iteration += 1;\n                     ^~\n%Error: data/full_repos/permissive/444559342/mp1/multiplier/hdl/add_shift_multiplier.sv:79: syntax error, unexpected '=', expecting IDENTIFIER\n            next.op = DONE;\n                    ^\n%Error: data/full_repos/permissive/444559342/mp1/multiplier/hdl/add_shift_multiplier.sv:80: syntax error, unexpected '=', expecting IDENTIFIER\n            next.done = 1'b1;\n                      ^\n%Error: data/full_repos/permissive/444559342/mp1/multiplier/hdl/add_shift_multiplier.sv:81: syntax error, unexpected '=', expecting IDENTIFIER\n            next.ready = 1'b1;\n                       ^\n%Error: data/full_repos/permissive/444559342/mp1/multiplier/hdl/add_shift_multiplier.sv:89: syntax error, unexpected '=', expecting IDENTIFIER\n        update_state = 1'b1;\n                     ^\n%Error: data/full_repos/permissive/444559342/mp1/multiplier/hdl/add_shift_multiplier.sv:107: syntax error, unexpected IDENTIFIER, expecting assert or assume or cover or restrict\n                SHIFT: ms <= ms_shift;\n                       ^~\n%Error: Cannot continue\n"
module add_shift_multiplier
(
    input logic clk_i,
    input logic reset_n_i,
    input operand_t multiplicand_i,
    input operand_t multiplier_i,
    input logic start_i,
    output logic ready_o,
    output result_t product_o,
    output logic done_o
);


mstate_s ms;
mstate_s ms_reset;
mstate_s ms_init;
mstate_s ms_add;
mstate_s ms_shift;
logic update_state;




assign ready_o = ms.ready;
assign done_o = ms.done;
assign product_o = {ms.A, ms.Q};













function void reset(output mstate_s ms_next);
    ms_next = 0;
    ms_next.ready = 1'b1;
endfunction


function void init(input logic[width_p-1:0] multiplicand,
                   input logic[width_p-1:0] multiplier,
                   output mstate_s ms_next);
    ms_next.ready = 1'b0;
    ms_next.done = 1'b0;
    ms_next.iteration = 0;
    ms_next.op = ADD;

    ms_next.M = multiplicand;
    ms_next.C = 1'b0;
    ms_next.A = 0;
    ms_next.Q = multiplier;
endfunction


function void add(input mstate_s cur, output mstate_s next);
    next = cur;
    next.op = SHIFT;
    if (cur.Q[0])
        {next.C, next.A} = cur.A + cur.M;
    else
        next.C = 1'b0;
endfunction


function void shift(input mstate_s cur, output mstate_s next);
      next = cur;
      {next.A, next.Q} = {cur.C, cur.A, cur.Q[width_p-1:1]};
      next.op = ADD;
      next.iteration += 1;
      if (next.iteration == width_p) begin
            next.op = DONE;
            next.done = 1'b1;
            next.ready = 1'b1;
      end
endfunction


always_comb begin
    update_state = 1'b0;
    if ((~reset_n_i) | (start_i) | (ms.op == ADD) || (ms.op == SHIFT))
        update_state = 1'b1;
    reset(ms_reset);
    init(multiplicand_i, multiplier_i, ms_init);
    add(ms, ms_add);
    shift(ms, ms_shift);
end


always_ff @(posedge clk_i) begin
    if (~reset_n_i)
            ms <= ms_reset;
    else if (update_state) begin
        if (start_i & ready_o) begin
            ms <= ms_init;
        end
        else begin
            case (ms.op)
                ADD: ms <= ms_add;
                SHIFT: ms <= ms_shift;
                default: ms <= ms_reset;
            endcase
        end
    end
end



















endmodule
module add_shift_multiplier
(
    input logic clk_i,
    input logic reset_n_i,
    input operand_t multiplicand_i,
    input operand_t multiplier_i,
    input logic start_i,
    output logic ready_o,
    output result_t product_o,
    output logic done_o
);



mstate_s ms;
mstate_s ms_reset;
mstate_s ms_init;
mstate_s ms_add;
mstate_s ms_shift;
logic update_state;




assign ready_o = ms.ready;
assign done_o = ms.done;
assign product_o = {ms.A, ms.Q};













function void reset(output mstate_s ms_next);
    ms_next = 0;
    ms_next.ready = 1'b1;
endfunction


function void init(input logic[width_p-1:0] multiplicand,
                   input logic[width_p-1:0] multiplier,
                   output mstate_s ms_next);
    ms_next.ready = 1'b0;
    ms_next.done = 1'b0;
    ms_next.iteration = 0;
    ms_next.op = ADD;

    ms_next.M = multiplicand;
    ms_next.C = 1'b0;
    ms_next.A = 0;
    ms_next.Q = multiplier;
endfunction


function void add(input mstate_s cur, output mstate_s next);
    next = cur;
    next.op = SHIFT;
    if (cur.Q[0])
        {next.C, next.A} = cur.A + cur.M;
    else
        next.C = 1'b0;
endfunction


function void shift(input mstate_s cur, output mstate_s next);
      next = cur;
      {next.A, next.Q} = {cur.C, cur.A, cur.Q[width_p-1:1]};
      next.op = ADD;
      next.iteration += 1;
      if (next.iteration == width_p) begin
            next.op = DONE;
            next.done = 1'b1;
            next.ready = 1'b1;
      end
endfunction


always_comb begin
    update_state = 1'b0;
    if ((~reset_n_i) | (start_i) | (ms.op == ADD) || (ms.op == SHIFT))
        update_state = 1'b1;
    reset(ms_reset);
    init(multiplicand_i, multiplier_i, ms_init);
    add(ms, ms_add);
    shift(ms, ms_shift);
end


always_ff @(posedge clk_i) begin
    if (~reset_n_i)
            ms <= ms_reset;
    else if (update_state) begin
        if (start_i & ready_o) begin
            ms <= ms_init;
        end
        else begin
            case (ms.op)
                ADD: ms <= ms_add;
                SHIFT: ms <= ms_shift;
                default: ms <= ms_reset;
            endcase
        end
    end
end



















endmodule