data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/MUXDC_STATEMACHINE.v
data/verilator_xmls/c6cfcdde-7460-4ceb-b1f6-8e1d2bebd4fe.xml
module MUXDC_STATEMACHINE(


MUXDC_STATEMACHINE_Clk,
MUXDC_STATEMACHINE_Reset,
MUXDC_STATEMACHINE_Start_Conf,
MUXDC_STATEMACHINE_Conf_Already_Ok,
MUXDC_STATEMACHINE_Counter_Bus_Flag,
MUXDC_STATEMACHINE_Counter_W_Size_Flag,



MUXDC_STATEMACHINE_Set_Conf_Already,
MUXDC_STATEMACHINE_Counter_W_Size_En,
MUXDC_STATEMACHINEE_Counter_W_Size_Clr,
MUXDC_STATEMACHINE_Counter_W_Col_En,
MUXDC_STATEMACHINE_Counter_W_Col_Load,
MUXDC_STATEMACHINE_Counter_W_Col_Clr,
MUXDC_STATEMACHINE_Counter_Bus_En,
MUXDC_STATEMACHINE_Counter_Bus_Clr,
MUXDC_STATEMACHINE_Conf_Rutine

);





localparam State_reset = 0;
localparam State_load = 1;
localparam State_Configuring0 = 2;
localparam State_Configuring1 = 3;
localparam State_Wait_Conf = 4;





input MUXDC_STATEMACHINE_Clk;
input MUXDC_STATEMACHINE_Reset;
input MUXDC_STATEMACHINE_Start_Conf;
input MUXDC_STATEMACHINE_Conf_Already_Ok;
input MUXDC_STATEMACHINE_Counter_Bus_Flag;
input MUXDC_STATEMACHINE_Counter_W_Size_Flag;
output reg MUXDC_STATEMACHINE_Set_Conf_Already;
output reg MUXDC_STATEMACHINE_Counter_W_Size_En;
output reg MUXDC_STATEMACHINEE_Counter_W_Size_Clr;
output reg MUXDC_STATEMACHINE_Counter_W_Col_En;
output reg MUXDC_STATEMACHINE_Counter_W_Col_Load;
output reg MUXDC_STATEMACHINE_Counter_W_Col_Clr;
output reg MUXDC_STATEMACHINE_Counter_Bus_En;
output reg MUXDC_STATEMACHINE_Counter_Bus_Clr;
output reg MUXDC_STATEMACHINE_Conf_Rutine;




reg [2:0] State_Register;
reg [2:0] State_Signal;


always @(*)
begin
	case (State_Register)
	
		State_reset: if(MUXDC_STATEMACHINE_Start_Conf)
							State_Signal=State_load;
						 else
							State_Signal=State_reset;
		
		State_load: State_Signal=State_Configuring0;
		
		State_Configuring0:if(MUXDC_STATEMACHINE_Counter_Bus_Flag)
										State_Signal=State_Wait_Conf;
								 else if(MUXDC_STATEMACHINE_Counter_W_Size_Flag)
										State_Signal=State_Configuring1;
								 else
										State_Signal=State_Configuring0;
									
		State_Configuring1: if(MUXDC_STATEMACHINE_Counter_Bus_Flag)
										State_Signal=State_Wait_Conf;
								  else
										State_Signal=State_Configuring1;
		
		State_Wait_Conf: if(MUXDC_STATEMACHINE_Conf_Already_Ok)
									State_Signal=State_reset;
								else
									State_Signal=State_Wait_Conf;
									
		default: State_Signal = State_reset;
								
	endcase

end



always @ (posedge MUXDC_STATEMACHINE_Clk, negedge MUXDC_STATEMACHINE_Reset)
begin
	if (!MUXDC_STATEMACHINE_Reset)
		State_Register <= State_reset;
	else
		State_Register <= State_Signal;
end



always @ (*)
begin
	case(State_Register)
	
		State_reset:
		begin
			MUXDC_STATEMACHINE_Set_Conf_Already = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Size_En = 1'b0;
			MUXDC_STATEMACHINEE_Counter_W_Size_Clr = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Col_En = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Col_Load = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Col_Clr = 1'b0;
			MUXDC_STATEMACHINE_Counter_Bus_En = 1'b0;
			MUXDC_STATEMACHINE_Counter_Bus_Clr = 1'b0;
			MUXDC_STATEMACHINE_Conf_Rutine = 1'b0;
		end
		
		State_load:
		begin
			MUXDC_STATEMACHINE_Set_Conf_Already = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Size_En = 1'b0;
			MUXDC_STATEMACHINEE_Counter_W_Size_Clr = 1'b1;
			MUXDC_STATEMACHINE_Counter_W_Col_En = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Col_Load = 1'b1;
			MUXDC_STATEMACHINE_Counter_W_Col_Clr = 1'b1;
			MUXDC_STATEMACHINE_Counter_Bus_En = 1'b0;
			MUXDC_STATEMACHINE_Counter_Bus_Clr = 1'b1;
			MUXDC_STATEMACHINE_Conf_Rutine = 1'b0;
		end
		
		State_Configuring0:
		begin
			MUXDC_STATEMACHINE_Set_Conf_Already = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Size_En = 1'b1;
			MUXDC_STATEMACHINEE_Counter_W_Size_Clr = 1'b1;
			MUXDC_STATEMACHINE_Counter_W_Col_En = 1'b1;
			MUXDC_STATEMACHINE_Counter_W_Col_Load = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Col_Clr = 1'b1;
			MUXDC_STATEMACHINE_Counter_Bus_En = 1'b1;
			MUXDC_STATEMACHINE_Counter_Bus_Clr = 1'b1;
			MUXDC_STATEMACHINE_Conf_Rutine = 1'b1;
		end
		
		State_Configuring1:
		begin
			MUXDC_STATEMACHINE_Set_Conf_Already = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Size_En = 1'b0;
			MUXDC_STATEMACHINEE_Counter_W_Size_Clr = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Col_En = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Col_Load = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Col_Clr = 1'b0;
			MUXDC_STATEMACHINE_Counter_Bus_En = 1'b1;
			MUXDC_STATEMACHINE_Counter_Bus_Clr = 1'b1;
			MUXDC_STATEMACHINE_Conf_Rutine = 1'b1;
		end
		
		
		State_Wait_Conf:
		begin
			MUXDC_STATEMACHINE_Set_Conf_Already = 1'b1;
			MUXDC_STATEMACHINE_Counter_W_Size_En = 1'b0;
			MUXDC_STATEMACHINEE_Counter_W_Size_Clr = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Col_En = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Col_Load = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Col_Clr = 1'b0;
			MUXDC_STATEMACHINE_Counter_Bus_En = 1'b0;
			MUXDC_STATEMACHINE_Counter_Bus_Clr = 1'b0;
			MUXDC_STATEMACHINE_Conf_Rutine = 1'b0;
		end
		
		
		default:
		begin
			MUXDC_STATEMACHINE_Set_Conf_Already = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Size_En = 1'b0;
			MUXDC_STATEMACHINEE_Counter_W_Size_Clr = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Col_En = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Col_Load = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Col_Clr = 1'b0;
			MUXDC_STATEMACHINE_Counter_Bus_En = 1'b0;
			MUXDC_STATEMACHINE_Counter_Bus_Clr = 1'b0;
			MUXDC_STATEMACHINE_Conf_Rutine = 1'b0;
		end
		
	endcase
	
end


endmodule
module MUXDC_STATEMACHINE(


MUXDC_STATEMACHINE_Clk,
MUXDC_STATEMACHINE_Reset,
MUXDC_STATEMACHINE_Start_Conf,
MUXDC_STATEMACHINE_Conf_Already_Ok,
MUXDC_STATEMACHINE_Counter_Bus_Flag,
MUXDC_STATEMACHINE_Counter_W_Size_Flag,



MUXDC_STATEMACHINE_Set_Conf_Already,
MUXDC_STATEMACHINE_Counter_W_Size_En,
MUXDC_STATEMACHINEE_Counter_W_Size_Clr,
MUXDC_STATEMACHINE_Counter_W_Col_En,
MUXDC_STATEMACHINE_Counter_W_Col_Load,
MUXDC_STATEMACHINE_Counter_W_Col_Clr,
MUXDC_STATEMACHINE_Counter_Bus_En,
MUXDC_STATEMACHINE_Counter_Bus_Clr,
MUXDC_STATEMACHINE_Conf_Rutine

);






localparam State_reset = 0;
localparam State_load = 1;
localparam State_Configuring0 = 2;
localparam State_Configuring1 = 3;
localparam State_Wait_Conf = 4;





input MUXDC_STATEMACHINE_Clk;
input MUXDC_STATEMACHINE_Reset;
input MUXDC_STATEMACHINE_Start_Conf;
input MUXDC_STATEMACHINE_Conf_Already_Ok;
input MUXDC_STATEMACHINE_Counter_Bus_Flag;
input MUXDC_STATEMACHINE_Counter_W_Size_Flag;
output reg MUXDC_STATEMACHINE_Set_Conf_Already;
output reg MUXDC_STATEMACHINE_Counter_W_Size_En;
output reg MUXDC_STATEMACHINEE_Counter_W_Size_Clr;
output reg MUXDC_STATEMACHINE_Counter_W_Col_En;
output reg MUXDC_STATEMACHINE_Counter_W_Col_Load;
output reg MUXDC_STATEMACHINE_Counter_W_Col_Clr;
output reg MUXDC_STATEMACHINE_Counter_Bus_En;
output reg MUXDC_STATEMACHINE_Counter_Bus_Clr;
output reg MUXDC_STATEMACHINE_Conf_Rutine;




reg [2:0] State_Register;
reg [2:0] State_Signal;


always @(*)
begin
	case (State_Register)
	
		State_reset: if(MUXDC_STATEMACHINE_Start_Conf)
							State_Signal=State_load;
						 else
							State_Signal=State_reset;
		
		State_load: State_Signal=State_Configuring0;
		
		State_Configuring0:if(MUXDC_STATEMACHINE_Counter_Bus_Flag)
										State_Signal=State_Wait_Conf;
								 else if(MUXDC_STATEMACHINE_Counter_W_Size_Flag)
										State_Signal=State_Configuring1;
								 else
										State_Signal=State_Configuring0;
									
		State_Configuring1: if(MUXDC_STATEMACHINE_Counter_Bus_Flag)
										State_Signal=State_Wait_Conf;
								  else
										State_Signal=State_Configuring1;
		
		State_Wait_Conf: if(MUXDC_STATEMACHINE_Conf_Already_Ok)
									State_Signal=State_reset;
								else
									State_Signal=State_Wait_Conf;
									
		default: State_Signal = State_reset;
								
	endcase

end



always @ (posedge MUXDC_STATEMACHINE_Clk, negedge MUXDC_STATEMACHINE_Reset)
begin
	if (!MUXDC_STATEMACHINE_Reset)
		State_Register <= State_reset;
	else
		State_Register <= State_Signal;
end



always @ (*)
begin
	case(State_Register)
	
		State_reset:
		begin
			MUXDC_STATEMACHINE_Set_Conf_Already = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Size_En = 1'b0;
			MUXDC_STATEMACHINEE_Counter_W_Size_Clr = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Col_En = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Col_Load = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Col_Clr = 1'b0;
			MUXDC_STATEMACHINE_Counter_Bus_En = 1'b0;
			MUXDC_STATEMACHINE_Counter_Bus_Clr = 1'b0;
			MUXDC_STATEMACHINE_Conf_Rutine = 1'b0;
		end
		
		State_load:
		begin
			MUXDC_STATEMACHINE_Set_Conf_Already = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Size_En = 1'b0;
			MUXDC_STATEMACHINEE_Counter_W_Size_Clr = 1'b1;
			MUXDC_STATEMACHINE_Counter_W_Col_En = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Col_Load = 1'b1;
			MUXDC_STATEMACHINE_Counter_W_Col_Clr = 1'b1;
			MUXDC_STATEMACHINE_Counter_Bus_En = 1'b0;
			MUXDC_STATEMACHINE_Counter_Bus_Clr = 1'b1;
			MUXDC_STATEMACHINE_Conf_Rutine = 1'b0;
		end
		
		State_Configuring0:
		begin
			MUXDC_STATEMACHINE_Set_Conf_Already = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Size_En = 1'b1;
			MUXDC_STATEMACHINEE_Counter_W_Size_Clr = 1'b1;
			MUXDC_STATEMACHINE_Counter_W_Col_En = 1'b1;
			MUXDC_STATEMACHINE_Counter_W_Col_Load = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Col_Clr = 1'b1;
			MUXDC_STATEMACHINE_Counter_Bus_En = 1'b1;
			MUXDC_STATEMACHINE_Counter_Bus_Clr = 1'b1;
			MUXDC_STATEMACHINE_Conf_Rutine = 1'b1;
		end
		
		State_Configuring1:
		begin
			MUXDC_STATEMACHINE_Set_Conf_Already = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Size_En = 1'b0;
			MUXDC_STATEMACHINEE_Counter_W_Size_Clr = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Col_En = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Col_Load = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Col_Clr = 1'b0;
			MUXDC_STATEMACHINE_Counter_Bus_En = 1'b1;
			MUXDC_STATEMACHINE_Counter_Bus_Clr = 1'b1;
			MUXDC_STATEMACHINE_Conf_Rutine = 1'b1;
		end
		
		
		State_Wait_Conf:
		begin
			MUXDC_STATEMACHINE_Set_Conf_Already = 1'b1;
			MUXDC_STATEMACHINE_Counter_W_Size_En = 1'b0;
			MUXDC_STATEMACHINEE_Counter_W_Size_Clr = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Col_En = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Col_Load = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Col_Clr = 1'b0;
			MUXDC_STATEMACHINE_Counter_Bus_En = 1'b0;
			MUXDC_STATEMACHINE_Counter_Bus_Clr = 1'b0;
			MUXDC_STATEMACHINE_Conf_Rutine = 1'b0;
		end
		
		
		default:
		begin
			MUXDC_STATEMACHINE_Set_Conf_Already = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Size_En = 1'b0;
			MUXDC_STATEMACHINEE_Counter_W_Size_Clr = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Col_En = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Col_Load = 1'b0;
			MUXDC_STATEMACHINE_Counter_W_Col_Clr = 1'b0;
			MUXDC_STATEMACHINE_Counter_Bus_En = 1'b0;
			MUXDC_STATEMACHINE_Counter_Bus_Clr = 1'b0;
			MUXDC_STATEMACHINE_Conf_Rutine = 1'b0;
		end
		
	endcase
	
end


endmodule