data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_stream_mst.sv
1: b"%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_stream_mst.sv:19: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n  parameter time  ApplDelay = 0ps,\n                              ^~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_stream_mst.sv:21: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n  parameter time  AcqDelay = 0ps\n                             ^~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_stream_mst.sv:24: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic    rst_ni,\n  ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_stream_mst.sv:26: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output data_t   data_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_stream_mst.sv:27: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output logic    valid_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_stream_mst.sv:28: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic    ready_i\n  ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_stream_mst.sv:33: Unsupported: Static in this context\n  function static void randomize_wait_cycles();\n           ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_stream_mst.sv:35: syntax error, unexpected ::, expecting ';'\n    rand_success = std::randomize(rand_wait_cycles) with {\n                      ^~\n                                                                                                                                          : ... Perhaps 'std' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_stream_mst.sv:35: Unsupported: SystemVerilog 2005 reserved word not implemented: 'randomize'\n    rand_success = std::randomize(rand_wait_cycles) with {\n                        ^~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_stream_mst.sv:35: Unsupported: SystemVerilog 2005 reserved word not implemented: 'with'\n    rand_success = std::randomize(rand_wait_cycles) with {\n                                                    ^~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_stream_mst.sv:38: syntax error, unexpected '}'\n    };\n    ^\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_stream_mst.sv:42: syntax error, unexpected initial\n  initial begin\n  ^~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_stream_mst.sv:57: Unsupported: SystemVerilog 2005 reserved word not implemented: 'randomize'\n      void'(std::randomize(data_o));\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/rand_stream_mst.sv:81: Unsupported: SystemVerilog 2005 reserved word not implemented: 'randomize'\n        void'(std::randomize(data_o));\n                   ^~~~~~~~~\n%Error: Exiting due to 14 error(s)\n"
module rand_stream_mst #(
  parameter type  data_t = logic,

  parameter int   MinWaitCycles = -1,

  parameter int   MaxWaitCycles = -1,

  parameter time  ApplDelay = 0ps,

  parameter time  AcqDelay = 0ps
) (
  input  logic    clk_i,
  input  logic    rst_ni,

  output data_t   data_o,
  output logic    valid_o,
  input  logic    ready_i
);

  int unsigned rand_wait_cycles;

  function static void randomize_wait_cycles();
    int unsigned rand_success;
    rand_success = std::randomize(rand_wait_cycles) with {
      rand_wait_cycles >= MinWaitCycles;
      rand_wait_cycles <= MaxWaitCycles;
    };
    assert (rand_success) else $error("Failed to randomize wait cycles!");
  endfunction

  initial begin
    data_o  = '0;
    valid_o = 1'b0;
    wait (rst_ni);

    randomize_wait_cycles();
    @(posedge clk_i);
    forever begin

      repeat(rand_wait_cycles) begin
        @(posedge clk_i);
      end

      #(ApplDelay);

      void'(std::randomize(data_o));
      valid_o = 1'b1;


      #(AcqDelay-ApplDelay);


      while (!ready_i) begin
        @(posedge clk_i);
        #(AcqDelay);
      end


      randomize_wait_cycles();
      if (rand_wait_cycles == 0) begin


        @(posedge clk_i);
      end else begin


        @(posedge clk_i);
        #(ApplDelay);
        valid_o = 1'b0;
        void'(std::randomize(data_o));
      end
    end
  end


`ifndef VERILATOR
  initial begin: validate_params
    assert (MinWaitCycles >= 0)
      else $fatal("The minimum number of wait cycles must be at least 0!");
    assert (MaxWaitCycles >= 0)
      else $fatal("The maximum number of wait cycles must be at least 0!");
    assert (MaxWaitCycles >= MinWaitCycles)
      else $fatal("The maximum number of wait cycles must be at least the minimum number of wait cycles!");
    assert (ApplDelay > 0ps)
      else $fatal("The application delay must be greater than 0!");
    assert (AcqDelay > 0ps)
      else $fatal("The acquisition delay must be greater than 0!");
    assert (AcqDelay > ApplDelay)
      else $fatal("The acquisition delay must be greater than the application delay!");
  end
`endif

endmodule
module rand_stream_mst #(
  parameter type  data_t = logic,

  parameter int   MinWaitCycles = -1,

  parameter int   MaxWaitCycles = -1,

  parameter time  ApplDelay = 0ps,

  parameter time  AcqDelay = 0ps
) (
  input  logic    clk_i,
  input  logic    rst_ni,

  output data_t   data_o,
  output logic    valid_o,
  input  logic    ready_i
);


  int unsigned rand_wait_cycles;

  function static void randomize_wait_cycles();
    int unsigned rand_success;
    rand_success = std::randomize(rand_wait_cycles) with {
      rand_wait_cycles >= MinWaitCycles;
      rand_wait_cycles <= MaxWaitCycles;
    };
    assert (rand_success) else $error("Failed to randomize wait cycles!");
  endfunction

  initial begin
    data_o  = '0;
    valid_o = 1'b0;
    wait (rst_ni);

    randomize_wait_cycles();
    @(posedge clk_i);
    forever begin

      repeat(rand_wait_cycles) begin
        @(posedge clk_i);
      end

      #(ApplDelay);

      void'(std::randomize(data_o));
      valid_o = 1'b1;


      #(AcqDelay-ApplDelay);


      while (!ready_i) begin
        @(posedge clk_i);
        #(AcqDelay);
      end


      randomize_wait_cycles();
      if (rand_wait_cycles == 0) begin


        @(posedge clk_i);
      end else begin


        @(posedge clk_i);
        #(ApplDelay);
        valid_o = 1'b0;
        void'(std::randomize(data_o));
      end
    end
  end


`ifndef VERILATOR
  initial begin: validate_params
    assert (MinWaitCycles >= 0)
      else $fatal("The minimum number of wait cycles must be at least 0!");
    assert (MaxWaitCycles >= 0)
      else $fatal("The maximum number of wait cycles must be at least 0!");
    assert (MaxWaitCycles >= MinWaitCycles)
      else $fatal("The maximum number of wait cycles must be at least the minimum number of wait cycles!");
    assert (ApplDelay > 0ps)
      else $fatal("The application delay must be greater than 0!");
    assert (AcqDelay > 0ps)
      else $fatal("The acquisition delay must be greater than 0!");
    assert (AcqDelay > ApplDelay)
      else $fatal("The acquisition delay must be greater than the application delay!");
  end
`endif

endmodule