data/full_repos/permissive/490649362/pipeline/src/MEM_WB.v
data/verilator_xmls/394515e8-1208-4d2b-bf0c-24807fc99f4d.xml
module MEM_WB (
    input               clk,
    input               MemtoReg_MEM,
                        RegWrite_MEM,
    input       [31:0]  dmReadData_MEM,
                        ALUResult_MEM,
    input       [4:0]   Dst_MEM,

    output  reg         MemtoReg_WB,
                        RegWrite_WB,
    output  reg [31:0]  dmReadData_WB,
                        ALUResult_WB,
    output  reg [4:0]   Dst_WB
);

    initial begin
        MemtoReg_WB = 1'b0;
        RegWrite_WB = 1'b0;
        dmReadData_WB = 32'b0;
        ALUResult_WB = 32'b0;
        Dst_WB = 5'b0;
    end

    always @(posedge clk) begin
        MemtoReg_WB <= MemtoReg_MEM;
        RegWrite_WB <= RegWrite_MEM;
        dmReadData_WB <= dmReadData_MEM;
        ALUResult_WB <= ALUResult_MEM;
        Dst_WB <= Dst_MEM;
    end

endmodule
module MEM_WB (
    input               clk,
    input               MemtoReg_MEM,
                        RegWrite_MEM,
    input       [31:0]  dmReadData_MEM,
                        ALUResult_MEM,
    input       [4:0]   Dst_MEM,

    output  reg         MemtoReg_WB,
                        RegWrite_WB,
    output  reg [31:0]  dmReadData_WB,
                        ALUResult_WB,
    output  reg [4:0]   Dst_WB
);


    initial begin
        MemtoReg_WB = 1'b0;
        RegWrite_WB = 1'b0;
        dmReadData_WB = 32'b0;
        ALUResult_WB = 32'b0;
        Dst_WB = 5'b0;
    end

    always @(posedge clk) begin
        MemtoReg_WB <= MemtoReg_MEM;
        RegWrite_WB <= RegWrite_MEM;
        dmReadData_WB <= dmReadData_MEM;
        ALUResult_WB <= ALUResult_MEM;
        Dst_WB <= Dst_MEM;
    end

endmodule