data/full_repos/permissive/458113953/LAB 4_2019A8PS0621H/CountFSM.v
1: b'%Error: Cannot find file containing module: 4_2019A8PS0621H,data/full_repos/permissive/458113953\n        ... Looked in:\n             data/full_repos/permissive/458113953/LAB/4_2019A8PS0621H,data/full_repos/permissive/458113953\n             data/full_repos/permissive/458113953/LAB/4_2019A8PS0621H,data/full_repos/permissive/458113953.v\n             data/full_repos/permissive/458113953/LAB/4_2019A8PS0621H,data/full_repos/permissive/458113953.sv\n             4_2019A8PS0621H,data/full_repos/permissive/458113953\n             4_2019A8PS0621H,data/full_repos/permissive/458113953.v\n             4_2019A8PS0621H,data/full_repos/permissive/458113953.sv\n             obj_dir/4_2019A8PS0621H,data/full_repos/permissive/458113953\n             obj_dir/4_2019A8PS0621H,data/full_repos/permissive/458113953.v\n             obj_dir/4_2019A8PS0621H,data/full_repos/permissive/458113953.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/458113953/LAB\n%Error: Cannot find file containing module: 4_2019A8PS0621H/CountFSM.v\n%Error: Exiting due to 3 error(s)\n'
module CountFSM(
    input Clk,
    input Reset,
    input Count_up,
    output reg [3:0] Count
    );

    reg [1:0] next_state,present_state;

    parameter S0=2'b00,S1=2'b01,S2=2'b10,S3=2'b11;

    reg [25:0] Clk_Div;
        always@(posedge Clk,posedge Reset)
        begin
        if(Reset==1)
        Clk_Div=0;
        else
        Clk_Div=Clk_Div+1;
        end
    always@(posedge Clk_Div[25], posedge Reset)
    begin
    if(Reset==1)
    present_state=2'b00;
    else
    present_state=next_state;
    end


    always@(Count_up,present_state)
    begin
    case(present_state)
    S0:begin
       if(Count_up==1)
          next_state=S1;
       else
          next_state=S3;
       end
    S1:begin
       if(Count_up==1)
          next_state=S2;
       else
          next_state=S0;
       end
    
    S2:begin
       if(Count_up==1)
          next_state=S3;
       else
          next_state=S1;
       end
    S3:begin
       if(Count_up==1)
          next_state=S0;
       else
          next_state=S2;
       end
    
    endcase
    end

    always@(present_state)
    begin
    case(present_state)
    S0:Count=4'b0000;
    S1:Count=4'b0010;
    S2:Count=4'b0100;
    S3:Count=4'b0110;
    default:Count=4'b0000;
    endcase
    end
    
    
    
endmodule
module CountFSM(
    input Clk,
    input Reset,
    input Count_up,
    output reg [3:0] Count
    );


    reg [1:0] next_state,present_state;

    parameter S0=2'b00,S1=2'b01,S2=2'b10,S3=2'b11;

    reg [25:0] Clk_Div;
        always@(posedge Clk,posedge Reset)
        begin
        if(Reset==1)
        Clk_Div=0;
        else
        Clk_Div=Clk_Div+1;
        end
    always@(posedge Clk_Div[25], posedge Reset)
    begin
    if(Reset==1)
    present_state=2'b00;
    else
    present_state=next_state;
    end


    always@(Count_up,present_state)
    begin
    case(present_state)
    S0:begin
       if(Count_up==1)
          next_state=S1;
       else
          next_state=S3;
       end
    S1:begin
       if(Count_up==1)
          next_state=S2;
       else
          next_state=S0;
       end
    
    S2:begin
       if(Count_up==1)
          next_state=S3;
       else
          next_state=S1;
       end
    S3:begin
       if(Count_up==1)
          next_state=S0;
       else
          next_state=S2;
       end
    
    endcase
    end

    always@(present_state)
    begin
    case(present_state)
    S0:Count=4'b0000;
    S1:Count=4'b0010;
    S2:Count=4'b0100;
    S3:Count=4'b0110;
    default:Count=4'b0000;
    endcase
    end
    
    
    
endmodule