data/full_repos/permissive/423958267/lab01/lab01.srcs/sources_1/new/DFlipFlop.v
data/verilator_xmls/7908f228-0209-4a50-9260-c3a52b82277d.xml
module DFlipFlop(q,clock,nreset,d);
    output q;
    input clock,nreset,d;
    reg q;
    always @(posedge clock)
    begin
        if (nreset==1)
            q=d;
    end
    always @(nreset)
    begin
        if (nreset==0)
            q=0;
    end
endmodule
module DFlipFlop(q,clock,nreset,d);

    output q;
    input clock,nreset,d;
    reg q;
    always @(posedge clock)
    begin
        if (nreset==1)
            q=d;
    end
    always @(nreset)
    begin
        if (nreset==0)
            q=0;
    end
endmodule