data/full_repos/permissive/444465810/func/axi/EXT.v
1: b'%Warning-WIDTH: data/full_repos/permissive/444465810/func/axi/EXT.v:7: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 16 bits.\n                                                                     : ... In instance EXT\n        0: Out = $signed(In);    \n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/444465810/func/axi/EXT.v:8: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'In\' generates 16 bits.\n                                                                     : ... In instance EXT\n        1: Out = In;             \n               ^\n%Error: Exiting due to 2 warning(s)\n'
module EXT(
    input [15:0]In,
    input [1:0]Op,
    output reg[31:0]Out
);always @(*) begin
    case(Op)
        0: Out = $signed(In);
        1: Out = In;
        2: Out = {In,16'h0000};
    endcase
end
endmodule
module EXT(
    input [15:0]In,
    input [1:0]Op,
    output reg[31:0]Out
);
always @(*) begin
    case(Op)
        0: Out = $signed(In);
        1: Out = In;
        2: Out = {In,16'h0000};
    endcase
end
endmodule