data/full_repos/permissive/43264243/testbench_fifo.v
1: b'%Error: data/full_repos/permissive/43264243/testbench_fifo.v:57: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, testbench);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/43264243/testbench_fifo.v:64: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/43264243/testbench_fifo.v:67: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/43264243/testbench_fifo.v:71: Unsupported: Ignoring delay on this delayed statement.\n #640\n ^\n%Warning-STMTDLY: data/full_repos/permissive/43264243/testbench_fifo.v:73: Unsupported: Ignoring delay on this delayed statement.\n # 10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/43264243/testbench_fifo.v:75: Unsupported: Ignoring delay on this delayed statement.\n #640\n ^\n%Warning-STMTDLY: data/full_repos/permissive/43264243/testbench_fifo.v:77: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/43264243/testbench_fifo.v:82: Unsupported: Ignoring delay on this delayed statement.\n # 10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/43264243/testbench_fifo.v:85: Unsupported: Ignoring delay on this delayed statement.\n # 10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/43264243/testbench_fifo.v:87: Unsupported: Ignoring delay on this delayed statement.\n # 10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/43264243/testbench_fifo.v:89: Unsupported: Ignoring delay on this delayed statement.\n # 10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/43264243/testbench_fifo.v:93: Unsupported: Ignoring delay on this delayed statement.\n # 10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/43264243/testbench_fifo.v:95: Unsupported: Ignoring delay on this delayed statement.\n # 10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/43264243/testbench_fifo.v:97: Unsupported: Ignoring delay on this delayed statement.\n # 10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/43264243/testbench_fifo.v:106: Unsupported: Ignoring delay on this delayed statement.\n    #100000 $finish; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/43264243/testbench_fifo.v:99: Unsupported: Ignoring delay on this delayed statement.\n # 10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/43264243/testbench_fifo.v:109: Unsupported: Ignoring delay on this delayed statement.\n  always #5 clk = ~clk;\n         ^\n%Error: Exiting due to 1 error(s), 16 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
  

  reg clk;
  reg ce;
  reg rstn;
  reg loaden;
  reg unloaden;
  wire empty;
  wire full;
  integer i;
  
  wire [62:0] count;
  reg [63:0] datain;
  wire [63:0] dataout;
  wire [5:0] itemsinfifo;
  
 
	ptrfifo fifo(
		.clk(clk),
		.rstn(rstn),
		.loaden(loaden),
		.unloaden(unloaden),
		.datain(datain),
		.dataout(dataout),
		.itemsinfifo(itemsinfifo)
	);
	defparam fifo.DEPTH = 6;
	defparam fifo.WIDTH = 64;
	

  initial begin
    $dumpvars(0, testbench);
	ce = 0;
    clk = 0;
	rstn = 0;
	loaden = 0;
	unloaden = 0;
	datain = 0;
	#10
	ce = 1;
	rstn = 1;
	#10
	

	loaden = 1;
	#640
	loaden = 0;
	# 10
	unloaden = 1;
	#640
	unloaden = 0;
	#10
	

	datain = 64'h55AA00FFDEADBEEF;
	loaden = 1;
	# 10
	loaden = 0;
	datain = 64'hDEADBEEF55AA00FF;
	# 10
	loaden = 1;
	# 10
	loaden = 0;
	# 10
	

	unloaden = 1;
	# 10
	unloaden = 0;
	# 10
	unloaden = 1;
	# 10
	unloaden = 0;
	# 10
	
	
	
	
	

    #100000 $finish; 
  end
 
  always #5 clk = ~clk;

endmodule
module testbench;

  

  reg clk;
  reg ce;
  reg rstn;
  reg loaden;
  reg unloaden;
  wire empty;
  wire full;
  integer i;
  
  wire [62:0] count;
  reg [63:0] datain;
  wire [63:0] dataout;
  wire [5:0] itemsinfifo;
  
 
	ptrfifo fifo(
		.clk(clk),
		.rstn(rstn),
		.loaden(loaden),
		.unloaden(unloaden),
		.datain(datain),
		.dataout(dataout),
		.itemsinfifo(itemsinfifo)
	);
	defparam fifo.DEPTH = 6;
	defparam fifo.WIDTH = 64;
	

  initial begin
    $dumpvars(0, testbench);
	ce = 0;
    clk = 0;
	rstn = 0;
	loaden = 0;
	unloaden = 0;
	datain = 0;
	#10
	ce = 1;
	rstn = 1;
	#10
	

	loaden = 1;
	#640
	loaden = 0;
	# 10
	unloaden = 1;
	#640
	unloaden = 0;
	#10
	

	datain = 64'h55AA00FFDEADBEEF;
	loaden = 1;
	# 10
	loaden = 0;
	datain = 64'hDEADBEEF55AA00FF;
	# 10
	loaden = 1;
	# 10
	loaden = 0;
	# 10
	

	unloaden = 1;
	# 10
	unloaden = 0;
	# 10
	unloaden = 1;
	# 10
	unloaden = 0;
	# 10
	
	
	
	
	

    #100000 $finish; 
  end
 
  always #5 clk = ~clk;

endmodule