data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/sss_fallthrough_small_fifo_v1_0_0/hdl/sss_small_fifo.v
data/verilator_xmls/580df52b-7809-4ee8-85c5-f4d6e07c9f17.xml
module sss_small_fifo
    #(parameter WIDTH = 72,
      parameter MAX_DEPTH_BITS = 3,
      parameter PROG_FULL_THRESHOLD = 2**MAX_DEPTH_BITS - 1
      )
    (

     input [WIDTH-1:0] din,
     input          wr_en,

     input          rd_en,

     output reg [WIDTH-1:0]  dout,
     output         full,
     output         nearly_full,
     output         prog_full,
     output         empty,

     output reg [MAX_DEPTH_BITS : 0] depth,

     input          reset,
     input          clk
     );


parameter MAX_DEPTH        = 2 ** MAX_DEPTH_BITS;

reg [WIDTH-1:0] queue [MAX_DEPTH - 1 : 0];
reg [MAX_DEPTH_BITS - 1 : 0] rd_ptr;
reg [MAX_DEPTH_BITS - 1 : 0] wr_ptr;


wire [MAX_DEPTH_BITS : 0] queue_depth_debug = depth;
wire wr_en_debug = wr_en;
wire rd_en_debug = rd_en;


always @(posedge clk)
begin
   if (wr_en)
      queue[wr_ptr] <= din;
   if (rd_en)
      dout <=

	      #1

	      queue[rd_ptr];
end

always @(posedge clk)
begin
   if (reset) begin
      rd_ptr <= 'h0;
      wr_ptr <= 'h0;
      depth  <= 'h0;
   end
   else begin
      if (wr_en) wr_ptr <= wr_ptr + 'h1;
      if (rd_en) rd_ptr <= rd_ptr + 'h1;
      if (wr_en & ~rd_en) depth <=

				   #1

				   depth + 'h1;
      else if (~wr_en & rd_en) depth <=

				   #1

				   depth - 'h1;
   end
end

assign full = depth == MAX_DEPTH;
assign prog_full = (depth >= PROG_FULL_THRESHOLD);
assign nearly_full = depth >= MAX_DEPTH-1;
assign empty = depth == 'h0;


always @(posedge clk)
begin
   if (wr_en && depth == MAX_DEPTH && !rd_en)
      $display($time, " ERROR: Attempt to write to full FIFO: %m");
   if (rd_en && depth == 'h0)
      $display($time, " ERROR: Attempt to read an empty FIFO: %m");
end


endmodule
module sss_small_fifo
    #(parameter WIDTH = 72,
      parameter MAX_DEPTH_BITS = 3,
      parameter PROG_FULL_THRESHOLD = 2**MAX_DEPTH_BITS - 1
      )
    (

     input [WIDTH-1:0] din,
     input          wr_en,

     input          rd_en,

     output reg [WIDTH-1:0]  dout,
     output         full,
     output         nearly_full,
     output         prog_full,
     output         empty,

     output reg [MAX_DEPTH_BITS : 0] depth,

     input          reset,
     input          clk
     );



parameter MAX_DEPTH        = 2 ** MAX_DEPTH_BITS;

reg [WIDTH-1:0] queue [MAX_DEPTH - 1 : 0];
reg [MAX_DEPTH_BITS - 1 : 0] rd_ptr;
reg [MAX_DEPTH_BITS - 1 : 0] wr_ptr;


wire [MAX_DEPTH_BITS : 0] queue_depth_debug = depth;
wire wr_en_debug = wr_en;
wire rd_en_debug = rd_en;


always @(posedge clk)
begin
   if (wr_en)
      queue[wr_ptr] <= din;
   if (rd_en)
      dout <=

	      #1

	      queue[rd_ptr];
end

always @(posedge clk)
begin
   if (reset) begin
      rd_ptr <= 'h0;
      wr_ptr <= 'h0;
      depth  <= 'h0;
   end
   else begin
      if (wr_en) wr_ptr <= wr_ptr + 'h1;
      if (rd_en) rd_ptr <= rd_ptr + 'h1;
      if (wr_en & ~rd_en) depth <=

				   #1

				   depth + 'h1;
      else if (~wr_en & rd_en) depth <=

				   #1

				   depth - 'h1;
   end
end

assign full = depth == MAX_DEPTH;
assign prog_full = (depth >= PROG_FULL_THRESHOLD);
assign nearly_full = depth >= MAX_DEPTH-1;
assign empty = depth == 'h0;


always @(posedge clk)
begin
   if (wr_en && depth == MAX_DEPTH && !rd_en)
      $display($time, " ERROR: Attempt to write to full FIFO: %m");
   if (rd_en && depth == 'h0)
      $display($time, " ERROR: Attempt to read an empty FIFO: %m");
end


endmodule