data/full_repos/permissive/44647742/myNot.v
data/verilator_xmls/c735bafa-ac02-4ddd-9952-93410d82ddd7.xml
module myNot(A, B);
    input wire A;
    output wire B;
    assign B = !A;
endmodule
module myNot(A, B);

    input wire A;
    output wire B;
    assign B = !A;
endmodule