data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v
1: b'%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:9: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:19: Define or directive not defined: \'`XLEN\'\n  input  [`XLEN-1:0] agu_i_rs1,\n          ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:20: Define or directive not defined: \'`XLEN\'\n  input  [`XLEN-1:0] agu_i_rs2,\n          ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:21: Define or directive not defined: \'`XLEN\'\n  input  [`XLEN-1:0] agu_i_imm,\n          ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:22: Define or directive not defined: \'`DECINFO_AGU_WIDTH\'\n  input  [`DECINFO_AGU_WIDTH-1:0] agu_i_info,        \n          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:23: Define or directive not defined: \'`ITAG_WIDTH\'\n  input  [`ITAG_WIDTH-1:0] agu_i_itag,\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:31: Define or directive not defined: \'`XLEN\'\n  output [`XLEN-1:0] agu_o_wbck_wdat,\n          ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:39: Define or directive not defined: \'`DTCM_ADDR_WIDTH\'\n  output [`DTCM_ADDR_WIDTH-1:0] agu_cmd_addr,              \n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:41: Define or directive not defined: \'`XLEN\'\n  output [`XLEN-1:0]      agu_cmd_wdata,\n          ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:42: Define or directive not defined: \'`XLEN\'\n  output [`XLEN/8-1:0] agu_cmd_wmask,\n          ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:42: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n  output [`XLEN/8-1:0] agu_cmd_wmask,\n               ^\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:43: Define or directive not defined: \'`ITAG_WIDTH\'\n  output [`ITAG_WIDTH-1:0]agu_cmd_itag,\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:51: Define or directive not defined: \'`XLEN\'\n  output [`XLEN-1:0] agu_req_alu_op1,\n          ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:52: Define or directive not defined: \'`XLEN\'\n  output [`XLEN-1:0] agu_req_alu_op2,\n          ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:62: Define or directive not defined: \'`XLEN\'\n  input  [`XLEN-1:0] agu_req_alu_res,\n          ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:66: Define or directive not defined: \'`XLEN\'\n  output [`XLEN-1:0] agu_sbf_0_nxt,\n          ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:67: Define or directive not defined: \'`XLEN\'\n  input  [`XLEN-1:0] agu_sbf_0_r,\n          ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:70: Define or directive not defined: \'`XLEN\'\n  output [`XLEN-1:0] agu_sbf_1_nxt,\n          ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:71: Define or directive not defined: \'`XLEN\'\n  input  [`XLEN-1:0] agu_sbf_1_r,\n          ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:83: Define or directive not defined: \'`DECINFO_AGU_LOAD\'\nwire       agu_i_load    = agu_i_info [`DECINFO_AGU_LOAD   ];\n                                       ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:83: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire       agu_i_load    = agu_i_info [`DECINFO_AGU_LOAD   ];\n                                                           ^\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:84: Define or directive not defined: \'`DECINFO_AGU_STORE\'\nwire       agu_i_store   = agu_i_info [`DECINFO_AGU_STORE  ];\n                                       ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:84: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire       agu_i_store   = agu_i_info [`DECINFO_AGU_STORE  ];\n                                                           ^\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:85: Define or directive not defined: \'`DECINFO_AGU_SIZE\'\n  wire [1:0] agu_i_size    = agu_i_info [`DECINFO_AGU_SIZE   ];\n                                         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:85: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire [1:0] agu_i_size    = agu_i_info [`DECINFO_AGU_SIZE   ];\n                                                             ^\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:86: Define or directive not defined: \'`DECINFO_AGU_USIGN\'\n  wire       agu_i_usign   = agu_i_info [`DECINFO_AGU_USIGN  ];\n                                         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:86: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire       agu_i_usign   = agu_i_info [`DECINFO_AGU_USIGN  ];\n                                                             ^\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:104: syntax error, unexpected assign\n  assign sta_is_idle    = (state_r == STATE_IDLE);\n  ^~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:115: syntax error, unexpected assign\n  assign state_last_exit_ena = 1\'b0;\n  ^~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:120: Define or directive not defined: \'`XLEN\'\n  wire [`XLEN-1:0] leftover_nxt;\n        ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:121: Define or directive not defined: \'`XLEN\'\n  wire [`XLEN-1:0] leftover_r;\n        ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:125: Define or directive not defined: \'`XLEN\'\n  wire [`XLEN-1:0] leftover_1_r;\n        ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:127: Define or directive not defined: \'`XLEN\'\n  wire [`XLEN-1:0] leftover_1_nxt;\n        ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:150: syntax error, unexpected assign\n  assign agu_req_alu_add  = 1\'b0 | sta_is_idle;\n  ^~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:151: Define or directive not defined: \'`XLEN\'\n  assign agu_req_alu_op1 =  sta_is_idle ? agu_i_rs1: `XLEN\'d0 ;\n                                                     ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:153: Define or directive not defined: \'`XLEN\'\n  wire [`XLEN-1:0] agu_addr_gen_op2 = agu_i_imm;\n        ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:154: syntax error, unexpected assign\n  assign agu_req_alu_op2 =  sta_is_idle   ? agu_addr_gen_op2 : `XLEN\'d0 ;\n  ^~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:154: Define or directive not defined: \'`XLEN\'\n  assign agu_req_alu_op2 =  sta_is_idle   ? agu_addr_gen_op2 : `XLEN\'d0 ;\n                                                               ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:177: Define or directive not defined: \'`XLEN\'\n  assign agu_o_wbck_wdat = {`XLEN{1\'b0 }};\n                            ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:182: Define or directive not defined: \'`DTCM_ADDR_WIDTH\'\n  assign agu_cmd_addr = agu_req_alu_res[`DTCM_ADDR_WIDTH-1:0];\n                                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:187: Define or directive not defined: \'`XLEN\'\n  wire [`XLEN-1:0] algnst_wdata   = \n        ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:188: Define or directive not defined: \'`XLEN\'\n                                    ({`XLEN{agu_i_size_b }} & {4{agu_i_rs2[ 7:0]}})\n                                      ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:189: Define or directive not defined: \'`XLEN\'\n                                  | ({`XLEN{agu_i_size_hw}} & {2{agu_i_rs2[15:0]}})\n                                      ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:190: Define or directive not defined: \'`XLEN\'\n                                  | ({`XLEN{agu_i_size_w }} & {1{agu_i_rs2[31:0]}});\n                                      ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:191: syntax error, unexpected assign\n  assign agu_cmd_wmask =             ({`XLEN/8{agu_i_size_b }} & (4\'b0001 << agu_cmd_addr[1:0]))\n  ^~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:191: Define or directive not defined: \'`XLEN\'\n  assign agu_cmd_wmask =             ({`XLEN/8{agu_i_size_b }} & (4\'b0001 << agu_cmd_addr[1:0]))\n                                       ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:192: Define or directive not defined: \'`XLEN\'\n          | ({`XLEN/8{agu_i_size_hw}} & (4\'b0011 << {agu_cmd_addr[1],1\'b0}))\n              ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_lsuagu.v:193: Define or directive not defined: \'`XLEN\'\n          | ({`XLEN/8{agu_i_size_w }} & (4\'b1111));\n              ^~~~~\n%Error: Exiting due to 48 error(s)\n'
module exu_alu_lsuagu(




  input  agu_i_valid,
  output agu_i_ready,

  input  [`XLEN-1:0] agu_i_rs1,
  input  [`XLEN-1:0] agu_i_rs2,
  input  [`XLEN-1:0] agu_i_imm,
  input  [`DECINFO_AGU_WIDTH-1:0] agu_i_info,
  input  [`ITAG_WIDTH-1:0] agu_i_itag,

  output agu_i_longpipe,



  output agu_o_valid,
  input  agu_o_ready,
  output [`XLEN-1:0] agu_o_wbck_wdat,
  output agu_cmd_usign,
  output [1:0] agu_cmd_size,


  output                  agu_cmd_valid,
  input                   agu_cmd_ready,

  output [`DTCM_ADDR_WIDTH-1:0] agu_cmd_addr,
  output                  agu_cmd_read,
  output [`XLEN-1:0]      agu_cmd_wdata,
  output [`XLEN/8-1:0] agu_cmd_wmask,
  output [`ITAG_WIDTH-1:0]agu_cmd_itag,


  input                        agu_rsp_valid,
  output                       agu_rsp_ready,



  output [`XLEN-1:0] agu_req_alu_op1,
  output [`XLEN-1:0] agu_req_alu_op2,
  output agu_req_alu_swap,
  output agu_req_alu_add ,
  output agu_req_alu_and ,
  output agu_req_alu_or  ,
  output agu_req_alu_xor ,
  output agu_req_alu_max ,
  output agu_req_alu_min ,
  output agu_req_alu_maxu,
  output agu_req_alu_minu,
  input  [`XLEN-1:0] agu_req_alu_res,


  output agu_sbf_0_ena,
  output [`XLEN-1:0] agu_sbf_0_nxt,
  input  [`XLEN-1:0] agu_sbf_0_r,

  output agu_sbf_1_ena,
  output [`XLEN-1:0] agu_sbf_1_nxt,
  input  [`XLEN-1:0] agu_sbf_1_r,

  input  clk,
  input  rst_n
  );


  wire       sta_is_idle;




wire       agu_i_load    = agu_i_info [`DECINFO_AGU_LOAD   ];
wire       agu_i_store   = agu_i_info [`DECINFO_AGU_STORE  ];
  wire [1:0] agu_i_size    = agu_i_info [`DECINFO_AGU_SIZE   ];
  wire       agu_i_usign   = agu_i_info [`DECINFO_AGU_USIGN  ];

  wire agu_i_size_b  = (agu_i_size == 2'b00);
  wire agu_i_size_hw = (agu_i_size == 2'b01);
  wire agu_i_size_w  = (agu_i_size == 2'b10);

  wire state_last_exit_ena;
 
  localparam STATE_WIDTH = 1;

  wire state_ena;
  wire [STATE_WIDTH-1:0] state_nxt;
  wire [STATE_WIDTH-1:0] state_r;


  localparam STATE_IDLE = 1'd0;


  assign sta_is_idle    = (state_r == STATE_IDLE);
   

  assign state_ena = 1'b0;


  assign state_nxt =({STATE_WIDTH{1'b0}});

  gnrl_dfflr #(STATE_WIDTH) state_dfflr (state_ena, state_nxt, state_r, clk, rst_n);
 
  wire  sta_is_last = 1'b0; 
  assign state_last_exit_ena = 1'b0;
 


  wire leftover_ena;
  wire [`XLEN-1:0] leftover_nxt;
  wire [`XLEN-1:0] leftover_r;
  wire leftover_err_nxt;
  wire leftover_err_r;

  wire [`XLEN-1:0] leftover_1_r;
  wire leftover_1_ena;
  wire [`XLEN-1:0] leftover_1_nxt;


  assign agu_req_alu_add  = 1'b0 | sta_is_idle;
  assign agu_req_alu_op1 =  sta_is_idle ? agu_i_rs1: `XLEN'd0 ;

  wire [`XLEN-1:0] agu_addr_gen_op2 = agu_i_imm;
  assign agu_req_alu_op2 =  sta_is_idle   ? agu_addr_gen_op2 : `XLEN'd0 ;

  assign agu_req_alu_swap = 1'b0;
  assign agu_req_alu_and  = 1'b0;
  assign agu_req_alu_or   = 1'b0;
  assign agu_req_alu_xor  = 1'b0;
  assign agu_req_alu_max  = 1'b0;
  assign agu_req_alu_min  = 1'b0;
  assign agu_req_alu_maxu = 1'b0;
  assign agu_req_alu_minu = 1'b0;




  assign agu_i_ready =( 1'b0) ? state_last_exit_ena : (agu_cmd_ready & agu_o_ready) ;
  

  assign agu_i_longpipe = agu_i_load | agu_i_store;
  



  assign agu_o_valid =   agu_i_valid & agu_cmd_ready;
  assign agu_o_wbck_wdat = {`XLEN{1'b0 }};

  assign agu_rsp_ready = 1'b1;
  
  assign agu_cmd_valid = agu_i_valid & agu_o_ready ;
  assign agu_cmd_addr = agu_req_alu_res[`DTCM_ADDR_WIDTH-1:0];

  assign agu_cmd_read = agu_i_load;


  wire [`XLEN-1:0] algnst_wdata   = 
                                    ({`XLEN{agu_i_size_b }} & {4{agu_i_rs2[ 7:0]}})
                                  | ({`XLEN{agu_i_size_hw}} & {2{agu_i_rs2[15:0]}})
                                  | ({`XLEN{agu_i_size_w }} & {1{agu_i_rs2[31:0]}});
  assign agu_cmd_wmask =             ({`XLEN/8{agu_i_size_b }} & (4'b0001 << agu_cmd_addr[1:0]))
          | ({`XLEN/8{agu_i_size_hw}} & (4'b0011 << {agu_cmd_addr[1],1'b0}))
          | ({`XLEN/8{agu_i_size_w }} & (4'b1111));
       
  assign agu_cmd_wdata = algnst_wdata;

           
  assign agu_cmd_itag     = agu_i_itag;
  assign agu_cmd_usign    = agu_i_usign;
  assign agu_cmd_size     = agu_i_size;
endmodule
module exu_alu_lsuagu(




  input  agu_i_valid,
  output agu_i_ready,

  input  [`XLEN-1:0] agu_i_rs1,
  input  [`XLEN-1:0] agu_i_rs2,
  input  [`XLEN-1:0] agu_i_imm,
  input  [`DECINFO_AGU_WIDTH-1:0] agu_i_info,
  input  [`ITAG_WIDTH-1:0] agu_i_itag,

  output agu_i_longpipe,



  output agu_o_valid,
  input  agu_o_ready,
  output [`XLEN-1:0] agu_o_wbck_wdat,
  output agu_cmd_usign,
  output [1:0] agu_cmd_size,


  output                  agu_cmd_valid,
  input                   agu_cmd_ready,

  output [`DTCM_ADDR_WIDTH-1:0] agu_cmd_addr,
  output                  agu_cmd_read,
  output [`XLEN-1:0]      agu_cmd_wdata,
  output [`XLEN/8-1:0] agu_cmd_wmask,
  output [`ITAG_WIDTH-1:0]agu_cmd_itag,


  input                        agu_rsp_valid,
  output                       agu_rsp_ready,



  output [`XLEN-1:0] agu_req_alu_op1,
  output [`XLEN-1:0] agu_req_alu_op2,
  output agu_req_alu_swap,
  output agu_req_alu_add ,
  output agu_req_alu_and ,
  output agu_req_alu_or  ,
  output agu_req_alu_xor ,
  output agu_req_alu_max ,
  output agu_req_alu_min ,
  output agu_req_alu_maxu,
  output agu_req_alu_minu,
  input  [`XLEN-1:0] agu_req_alu_res,


  output agu_sbf_0_ena,
  output [`XLEN-1:0] agu_sbf_0_nxt,
  input  [`XLEN-1:0] agu_sbf_0_r,

  output agu_sbf_1_ena,
  output [`XLEN-1:0] agu_sbf_1_nxt,
  input  [`XLEN-1:0] agu_sbf_1_r,

  input  clk,
  input  rst_n
  );



  wire       sta_is_idle;




wire       agu_i_load    = agu_i_info [`DECINFO_AGU_LOAD   ];
wire       agu_i_store   = agu_i_info [`DECINFO_AGU_STORE  ];
  wire [1:0] agu_i_size    = agu_i_info [`DECINFO_AGU_SIZE   ];
  wire       agu_i_usign   = agu_i_info [`DECINFO_AGU_USIGN  ];

  wire agu_i_size_b  = (agu_i_size == 2'b00);
  wire agu_i_size_hw = (agu_i_size == 2'b01);
  wire agu_i_size_w  = (agu_i_size == 2'b10);

  wire state_last_exit_ena;
 
  localparam STATE_WIDTH = 1;

  wire state_ena;
  wire [STATE_WIDTH-1:0] state_nxt;
  wire [STATE_WIDTH-1:0] state_r;


  localparam STATE_IDLE = 1'd0;


  assign sta_is_idle    = (state_r == STATE_IDLE);
   

  assign state_ena = 1'b0;


  assign state_nxt =({STATE_WIDTH{1'b0}});

  gnrl_dfflr #(STATE_WIDTH) state_dfflr (state_ena, state_nxt, state_r, clk, rst_n);
 
  wire  sta_is_last = 1'b0; 
  assign state_last_exit_ena = 1'b0;
 


  wire leftover_ena;
  wire [`XLEN-1:0] leftover_nxt;
  wire [`XLEN-1:0] leftover_r;
  wire leftover_err_nxt;
  wire leftover_err_r;

  wire [`XLEN-1:0] leftover_1_r;
  wire leftover_1_ena;
  wire [`XLEN-1:0] leftover_1_nxt;


  assign agu_req_alu_add  = 1'b0 | sta_is_idle;
  assign agu_req_alu_op1 =  sta_is_idle ? agu_i_rs1: `XLEN'd0 ;

  wire [`XLEN-1:0] agu_addr_gen_op2 = agu_i_imm;
  assign agu_req_alu_op2 =  sta_is_idle   ? agu_addr_gen_op2 : `XLEN'd0 ;

  assign agu_req_alu_swap = 1'b0;
  assign agu_req_alu_and  = 1'b0;
  assign agu_req_alu_or   = 1'b0;
  assign agu_req_alu_xor  = 1'b0;
  assign agu_req_alu_max  = 1'b0;
  assign agu_req_alu_min  = 1'b0;
  assign agu_req_alu_maxu = 1'b0;
  assign agu_req_alu_minu = 1'b0;




  assign agu_i_ready =( 1'b0) ? state_last_exit_ena : (agu_cmd_ready & agu_o_ready) ;
  

  assign agu_i_longpipe = agu_i_load | agu_i_store;
  



  assign agu_o_valid =   agu_i_valid & agu_cmd_ready;
  assign agu_o_wbck_wdat = {`XLEN{1'b0 }};

  assign agu_rsp_ready = 1'b1;
  
  assign agu_cmd_valid = agu_i_valid & agu_o_ready ;
  assign agu_cmd_addr = agu_req_alu_res[`DTCM_ADDR_WIDTH-1:0];

  assign agu_cmd_read = agu_i_load;


  wire [`XLEN-1:0] algnst_wdata   = 
                                    ({`XLEN{agu_i_size_b }} & {4{agu_i_rs2[ 7:0]}})
                                  | ({`XLEN{agu_i_size_hw}} & {2{agu_i_rs2[15:0]}})
                                  | ({`XLEN{agu_i_size_w }} & {1{agu_i_rs2[31:0]}});
  assign agu_cmd_wmask =             ({`XLEN/8{agu_i_size_b }} & (4'b0001 << agu_cmd_addr[1:0]))
          | ({`XLEN/8{agu_i_size_hw}} & (4'b0011 << {agu_cmd_addr[1],1'b0}))
          | ({`XLEN/8{agu_i_size_w }} & (4'b1111));
       
  assign agu_cmd_wdata = algnst_wdata;

           
  assign agu_cmd_itag     = agu_i_itag;
  assign agu_cmd_usign    = agu_i_usign;
  assign agu_cmd_size     = agu_i_size;
endmodule