data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Finite State Machines/Fsm_onehot/top_module_tb.v
1: b'%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines/Fsm_onehot,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/Fsm_onehot/top_module_tb.v\n%Error: Exiting due to 5 error(s)\n'
module top_module_tb ();
  reg in = 1'd0;
  reg [9:0] state = 10'd0;

  wire out1;
  wire out2;
  wire [9:0] next_state;

  always begin
    #10 state = next_state;
  end

  initial begin
    #1 state = 10'b0000000001;
  end

  initial begin

    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b0;


    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b0;
    #10 in = 1'b0;


    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b0;
    #10 in = 1'b1;
    #10 in = 1'b0;


    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b0;
    #10 in = 1'b0;


    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b0;
    #10 in = 1'b1;
    #10 in = 1'b0;

    #20
    $finish;
  end

  top_module uut (
      .in(in),
      .state(state),
      .next_state(next_state),
      .out1(out1),
      .out2(out2)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);
  end

endmodule
module top_module_tb ();

  reg in = 1'd0;
  reg [9:0] state = 10'd0;

  wire out1;
  wire out2;
  wire [9:0] next_state;

  always begin
    #10 state = next_state;
  end

  initial begin
    #1 state = 10'b0000000001;
  end

  initial begin

    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b0;


    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b0;
    #10 in = 1'b0;


    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b0;
    #10 in = 1'b1;
    #10 in = 1'b0;


    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b0;
    #10 in = 1'b0;


    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b1;
    #10 in = 1'b0;
    #10 in = 1'b1;
    #10 in = 1'b0;

    #20
    $finish;
  end

  top_module uut (
      .in(in),
      .state(state),
      .next_state(next_state),
      .out1(out1),
      .out2(out2)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);
  end

endmodule