data/full_repos/permissive/423539813/testbenches/address_gen_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/address_gen_testbench.v:33: Unsupported: Ignoring delay on this delayed statement.\nforever #30 clk=~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/address_gen_testbench.v:38: Unsupported: Ignoring delay on this delayed statement.\n#30\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/address_gen_testbench.v:40: Unsupported: Ignoring delay on this delayed statement.\n#30\n^\n%Error: data/full_repos/permissive/423539813/testbenches/address_gen_testbench.v:29: Cannot find file containing module: \'address_gen\'\naddress_gen uut2(.pc(pc),.PCNext(PCNext),.clk(clk),.rst(rst));\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423539813/testbenches,data/full_repos/permissive/423539813/address_gen\n             data/full_repos/permissive/423539813/testbenches,data/full_repos/permissive/423539813/address_gen.v\n             data/full_repos/permissive/423539813/testbenches,data/full_repos/permissive/423539813/address_gen.sv\n             address_gen\n             address_gen.v\n             address_gen.sv\n             obj_dir/address_gen\n             obj_dir/address_gen.v\n             obj_dir/address_gen.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module address_gen_testbench;

wire [31:0] pc;
reg [31:0] PCNext;
reg clk,rst;

address_gen uut2(.pc(pc),.PCNext(PCNext),.clk(clk),.rst(rst));

always begin
clk=0;
forever #30 clk=~clk;
end

initial begin
PCNext=32'h0;
#30
PCNext=32'h4;
#30
PCNext=32'h8;
end


endmodule
module address_gen_testbench;


wire [31:0] pc;
reg [31:0] PCNext;
reg clk,rst;

address_gen uut2(.pc(pc),.PCNext(PCNext),.clk(clk),.rst(rst));

always begin
clk=0;
forever #30 clk=~clk;
end

initial begin
PCNext=32'h0;
#30
PCNext=32'h4;
#30
PCNext=32'h8;
end


endmodule