data/full_repos/permissive/426864978/lab3/task5/tb_syn_doublecrack.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task5/tb_syn_doublecrack.sv:24: Unsupported: Ignoring delay on this delayed statement.\n        forever #5 clk = ~clk;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task5/tb_syn_doublecrack.sv:40: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task5/tb_syn_doublecrack.sv:48: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task5/tb_syn_doublecrack.sv:57: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task5/tb_syn_doublecrack.sv:66: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task5/tb_syn_doublecrack.sv:74: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task5/tb_syn_doublecrack.sv:84: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/426864978/lab3/task5/tb_syn_doublecrack.sv:97: Unsupported: wait statements\n        wait (tb_syn_doublecrack.dut.key_valid == 1\'b1);\n        ^~~~\n%Error: Exiting due to 6 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_syn_doublecrack();

    logic clk, rst_n, en, rdy, key_valid, err;
    logic [23:0] key;
    logic [7:0] ct_addr, ct_rddata;


    logic [7:0] ciphertext [255:0];
    logic [7:0] exp_pt [255:0];
    logic [7:0] ct_copy [255:0];

    doublecrack dut(
        .altera_reserved_tms(32'b0),
        .altera_reserved_tck(32'b0),
        .altera_reserved_tdi(32'b0),
        .altera_reserved_tdo(tdo),
        .*
    );

    initial begin
        clk = 0;
        forever #5 clk = ~clk;
    end

    initial begin
        err = 1'b0;






        $readmemh("crack_res1.txt", exp_pt);
        $readmemh("test1.memh", ciphertext);


        rst_n = 1'bx; en = 1'bx;
        #10;
        if (tb_syn_doublecrack.dut.rdy !== 1'bx) begin
            $display("ERROR 1: Expected rdy is %d, actual rdy is %d", 1'bx, tb_syn_doublecrack.dut.rdy);
            err = 1'b1;
        end


        rst_n = 1'b0; en = 1'b0;
        @(posedge clk);
        @(posedge clk);
        if (tb_syn_doublecrack.dut.rdy !== 1'b0) begin
            $display("ERROR 2: Expected rdy is %d, actual rdy is %d", 1'b0, tb_syn_doublecrack.dut.rdy);
            err = 1'b1;
        end


        rst_n = 1'b1;
        @(posedge clk);
        if (tb_syn_doublecrack.dut.rdy !== 1'b0) begin
            $display("ERROR 3: Expected rdy is %d, actual rdy is %d", 1'b0, tb_syn_doublecrack.dut.rdy);
            err = 1'b1;
        end


        en = 1'b1; ct_rddata = ciphertext[tb_syn_doublecrack.dut.ct_addr];
        ct_copy[tb_syn_doublecrack.dut.ct_addr] = ct_rddata;
        @(posedge clk);
        if (tb_syn_doublecrack.dut.rdy !== 1'b1) begin
            $display("ERROR 4: Expected rdy is %d, actual rdy is %d", 1'b1, tb_syn_doublecrack.dut.rdy);
            err = 1'b1;
        end


        en = 1'b0;
        @(posedge clk);
        if (tb_syn_doublecrack.dut.rdy !== 1'b0) begin
            $display("ERROR 5: Expected rdy is %d, actual rdy is %d", 1'b0, tb_syn_doublecrack.dut.rdy);
            err = 1'b1;
        end


        ct_rddata = ciphertext[tb_syn_doublecrack.dut.ct_addr];
        ct_copy[tb_syn_doublecrack.dut.ct_addr] = ct_rddata;
        for (int i = 0; i <= 24'h35; i++) begin
            @(posedge clk);
            @(posedge clk);
            ct_rddata = ciphertext[tb_syn_doublecrack.dut.ct_addr];
            ct_copy[tb_syn_doublecrack.dut.ct_addr] = ct_rddata;
        end
        for (int i = 0; i <= 24'h35; i++) begin
           if (ciphertext[i] !== ct_copy[i]) begin 
                $display("CT MEM [%d] ERROR: Expected ct_copy is %h, actual ct_copy is %h", i[7:0], ciphertext[i], ct_copy[i]);
                err = 1'b1;
            end
        end


        wait (tb_syn_doublecrack.dut.key_valid == 1'b1);


        for (int i = 0; i <= 8'h35; i++) begin
           if (exp_pt[i] !== tb_syn_doublecrack.dut.\pt|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i]) begin 
                $display("PT MEM [%d] ERROR: Expected pt is %h, actual pt is %h", i[7:0], exp_pt[i], tb_syn_doublecrack.dut.\pt|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i]);
                err = 1'b1;
            end
        end

        if (~err)
            $display("SUCCESS: All tests passed.");
        $stop;
    end

endmodule
module tb_syn_doublecrack();


    logic clk, rst_n, en, rdy, key_valid, err;
    logic [23:0] key;
    logic [7:0] ct_addr, ct_rddata;


    logic [7:0] ciphertext [255:0];
    logic [7:0] exp_pt [255:0];
    logic [7:0] ct_copy [255:0];

    doublecrack dut(
        .altera_reserved_tms(32'b0),
        .altera_reserved_tck(32'b0),
        .altera_reserved_tdi(32'b0),
        .altera_reserved_tdo(tdo),
        .*
    );

    initial begin
        clk = 0;
        forever #5 clk = ~clk;
    end

    initial begin
        err = 1'b0;






        $readmemh("crack_res1.txt", exp_pt);
        $readmemh("test1.memh", ciphertext);


        rst_n = 1'bx; en = 1'bx;
        #10;
        if (tb_syn_doublecrack.dut.rdy !== 1'bx) begin
            $display("ERROR 1: Expected rdy is %d, actual rdy is %d", 1'bx, tb_syn_doublecrack.dut.rdy);
            err = 1'b1;
        end


        rst_n = 1'b0; en = 1'b0;
        @(posedge clk);
        @(posedge clk);
        if (tb_syn_doublecrack.dut.rdy !== 1'b0) begin
            $display("ERROR 2: Expected rdy is %d, actual rdy is %d", 1'b0, tb_syn_doublecrack.dut.rdy);
            err = 1'b1;
        end


        rst_n = 1'b1;
        @(posedge clk);
        if (tb_syn_doublecrack.dut.rdy !== 1'b0) begin
            $display("ERROR 3: Expected rdy is %d, actual rdy is %d", 1'b0, tb_syn_doublecrack.dut.rdy);
            err = 1'b1;
        end


        en = 1'b1; ct_rddata = ciphertext[tb_syn_doublecrack.dut.ct_addr];
        ct_copy[tb_syn_doublecrack.dut.ct_addr] = ct_rddata;
        @(posedge clk);
        if (tb_syn_doublecrack.dut.rdy !== 1'b1) begin
            $display("ERROR 4: Expected rdy is %d, actual rdy is %d", 1'b1, tb_syn_doublecrack.dut.rdy);
            err = 1'b1;
        end


        en = 1'b0;
        @(posedge clk);
        if (tb_syn_doublecrack.dut.rdy !== 1'b0) begin
            $display("ERROR 5: Expected rdy is %d, actual rdy is %d", 1'b0, tb_syn_doublecrack.dut.rdy);
            err = 1'b1;
        end


        ct_rddata = ciphertext[tb_syn_doublecrack.dut.ct_addr];
        ct_copy[tb_syn_doublecrack.dut.ct_addr] = ct_rddata;
        for (int i = 0; i <= 24'h35; i++) begin
            @(posedge clk);
            @(posedge clk);
            ct_rddata = ciphertext[tb_syn_doublecrack.dut.ct_addr];
            ct_copy[tb_syn_doublecrack.dut.ct_addr] = ct_rddata;
        end
        for (int i = 0; i <= 24'h35; i++) begin
           if (ciphertext[i] !== ct_copy[i]) begin 
                $display("CT MEM [%d] ERROR: Expected ct_copy is %h, actual ct_copy is %h", i[7:0], ciphertext[i], ct_copy[i]);
                err = 1'b1;
            end
        end


        wait (tb_syn_doublecrack.dut.key_valid == 1'b1);


        for (int i = 0; i <= 8'h35; i++) begin
           if (exp_pt[i] !== tb_syn_doublecrack.dut.\pt|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i]) begin 
                $display("PT MEM [%d] ERROR: Expected pt is %h, actual pt is %h", i[7:0], exp_pt[i], tb_syn_doublecrack.dut.\pt|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i]);
                err = 1'b1;
            end
        end

        if (~err)
            $display("SUCCESS: All tests passed.");
        $stop;
    end

endmodule