data/full_repos/permissive/520471938/iiitb_ba_tb.v
1: b'%Error: data/full_repos/permissive/520471938/iiitb_ba_tb.v:43: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile ("bcdadd.vcd"); \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/520471938/iiitb_ba_tb.v:45: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, iiitb_ba_tb);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/520471938/iiitb_ba_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n        a = 0;  b = 0;  carry_in = 0;   #100;\n                                        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/520471938/iiitb_ba_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n        a = 6;  b = 9;  carry_in = 0;   #100;\n                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/520471938/iiitb_ba_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n        a = 3;  b = 3;  carry_in = 1;   #100;\n                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/520471938/iiitb_ba_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n        a = 4;  b = 5;  carry_in = 0;   #100;\n                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/520471938/iiitb_ba_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n        a = 8;  b = 2;  carry_in = 0;   #100;\n                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/520471938/iiitb_ba_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n        a = 9;  b = 9;  carry_in = 1;   #100;\n                                        ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module iiitb_ba_tb;





    reg [3:0] a;

    reg [3:0] b;

    reg carry_in;





    wire [3:0] sum;

    wire carry;





    iiitb_ba uut (

        .a(a), 

        .b(b), 

        .carry_in(carry_in), 

        .sum(sum), 

        .carry(carry)

    );



    initial begin

    $dumpfile ("bcdadd.vcd"); 

	$dumpvars(0, iiitb_ba_tb);



        a = 0;  b = 0;  carry_in = 0;   #100;

        a = 6;  b = 9;  carry_in = 0;   #100;

        a = 3;  b = 3;  carry_in = 1;   #100;

        a = 4;  b = 5;  carry_in = 0;   #100;

        a = 8;  b = 2;  carry_in = 0;   #100;

        a = 9;  b = 9;  carry_in = 1;   #100;

    end

      

endmodule
module iiitb_ba_tb;






    reg [3:0] a;

    reg [3:0] b;

    reg carry_in;





    wire [3:0] sum;

    wire carry;





    iiitb_ba uut (

        .a(a), 

        .b(b), 

        .carry_in(carry_in), 

        .sum(sum), 

        .carry(carry)

    );



    initial begin

    $dumpfile ("bcdadd.vcd"); 

	$dumpvars(0, iiitb_ba_tb);



        a = 0;  b = 0;  carry_in = 0;   #100;

        a = 6;  b = 9;  carry_in = 0;   #100;

        a = 3;  b = 3;  carry_in = 1;   #100;

        a = 4;  b = 5;  carry_in = 0;   #100;

        a = 8;  b = 2;  carry_in = 0;   #100;

        a = 9;  b = 9;  carry_in = 1;   #100;

    end

      

endmodule