data/full_repos/permissive/522668124/verilog/rtl/ALU.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/ALU.sv:141: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'6\'h1\' generates 6 bits.\n                                                                           : ... In instance ALU\n    else if ((opcode == 7\'b0010011) & (funct3 == 3\'b101) & (immediate[11:5] == 6\'b000001)) begin\n                                                                            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/ALU.sv:241: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'rs1_data\' generates 32 bits.\n                                                                           : ... In instance ALU\n  assign a_input = rs1_data;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/ALU.sv:242: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                           : ... In instance ALU\n  assign b_input = immediate_sel ? immediate : rs2_data;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/ALU.sv:247: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'a_input\' generates 1 bits.\n                                                                           : ... In instance ALU\n      6\'b000000: alu_result = a_input + b_input;    \n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/ALU.sv:247: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'b_input\' generates 1 bits.\n                                                                           : ... In instance ALU\n      6\'b000000: alu_result = a_input + b_input;    \n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/ALU.sv:248: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'a_input\' generates 1 bits.\n                                                                           : ... In instance ALU\n      6\'b000001: alu_result = a_input - b_input;  \n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/ALU.sv:248: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'b_input\' generates 1 bits.\n                                                                           : ... In instance ALU\n      6\'b000001: alu_result = a_input - b_input;  \n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/ALU.sv:249: Operator XOR expects 32 bits on the LHS, but LHS\'s VARREF \'a_input\' generates 1 bits.\n                                                                           : ... In instance ALU\n      6\'b000010: alu_result = a_input ^ b_input;  \n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/ALU.sv:249: Operator XOR expects 32 bits on the RHS, but RHS\'s VARREF \'b_input\' generates 1 bits.\n                                                                           : ... In instance ALU\n      6\'b000010: alu_result = a_input ^ b_input;  \n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/ALU.sv:250: Operator OR expects 32 bits on the LHS, but LHS\'s VARREF \'a_input\' generates 1 bits.\n                                                                           : ... In instance ALU\n      6\'b000011: alu_result = a_input | b_input;  \n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/ALU.sv:250: Operator OR expects 32 bits on the RHS, but RHS\'s VARREF \'b_input\' generates 1 bits.\n                                                                           : ... In instance ALU\n      6\'b000011: alu_result = a_input | b_input;  \n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/ALU.sv:251: Operator AND expects 32 bits on the LHS, but LHS\'s VARREF \'a_input\' generates 1 bits.\n                                                                           : ... In instance ALU\n      6\'b000100: alu_result = a_input & b_input;  \n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/ALU.sv:251: Operator AND expects 32 bits on the RHS, but RHS\'s VARREF \'b_input\' generates 1 bits.\n                                                                           : ... In instance ALU\n      6\'b000100: alu_result = a_input & b_input;  \n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/ALU.sv:252: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'a_input\' generates 1 bits.\n                                                                           : ... In instance ALU\n      6\'b000101: alu_result = a_input << b_input;   \n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/ALU.sv:253: Operator SHIFTR expects 32 bits on the LHS, but LHS\'s VARREF \'a_input\' generates 1 bits.\n                                                                           : ... In instance ALU\n      6\'b000110: alu_result = a_input >> b_input;   \n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/ALU.sv:254: Operator SHIFTR expects 32 bits on the LHS, but LHS\'s VARREF \'a_input\' generates 1 bits.\n                                                                           : ... In instance ALU\n      6\'b000111: alu_result = a_input >>> b_input;  \n                                      ^~~\n%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/ALU.sv:260: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s EQ generates 1 bits.\n                                                                           : ... In instance ALU\n      6\'b011110: alu_result = (a_input == b_input);   \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/ALU.sv:261: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s NEQ generates 1 bits.\n                                                                           : ... In instance ALU\n      6\'b011111: alu_result = (a_input != b_input);   \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/ALU.sv:262: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                                           : ... In instance ALU\n      6\'b100000: alu_result = (a_input < b_input);  \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/ALU.sv:263: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s GTE generates 1 bits.\n                                                                           : ... In instance ALU\n      6\'b100001: alu_result = (a_input >= b_input);   \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/ALU.sv:264: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                                           : ... In instance ALU\n      6\'b100010: alu_result = (a_input < b_input);  \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/ALU.sv:265: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s GTE generates 1 bits.\n                                                                           : ... In instance ALU\n      6\'b100011: alu_result = (a_input >= b_input);   \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/ALU.sv:267: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'b_input\' generates 1 bits.\n                                                                           : ... In instance ALU\n      6\'b100101: alu_result = b_input;   \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/522668124/verilog/rtl/ALU.sv:268: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'b_input\' generates 1 bits.\n                                                                           : ... In instance ALU\n      6\'b100110: alu_result = pc + b_input;  \n                                 ^\n%Error: Exiting due to 24 warning(s)\n'
module ALU

(
  `ifdef USE_POWER_PINS
      inout vccd1,
      inout vssd1,
  `endif
  
  input logic         clk,
  input logic         rst_n,
  input logic  [31:0] pc,
  input logic         reg_write,
  input logic  [5:0]  instruction_type,
  input logic  [6:0]  opcode,
  input logic  [4:0]  rd, 
  input logic  [4:0]  rs1, 
  input logic  [4:0]  rs2, 
  input logic  [2:0]  funct3, 
  input logic  [6:0]  funct7, 
  input logic  [31:0] immediate,
  input logic         immediate_sel,
  input logic  [31:0] read_data,
  
  input  logic [4:0]  la_reg_select,
  
  output logic [31:0] alu_output,
  output logic [31:0] rs1_data,
  output logic [31:0] rs2_data,
  
  output logic [31:0] la_read_data
  
);


  logic [31:0] Data_Registers[31:0];
  
  integer i;
  always_ff @(negedge clk) begin
    if (!rst_n) begin
      for (i=0;i<32;i=i+1)
        Data_Registers[i] = 0;
    end else begin
      if (reg_write && (rd != 0)) begin
        if (instruction_type == 6'b000010 && opcode == 7'b0000011) begin
          case (funct3)
            3'b000: Data_Registers[rd] <= {{24{read_data[7]}}, read_data[7:0]};
            3'b001: Data_Registers[rd] <= {{16{read_data[7]}}, read_data[15:0]};
            3'b010: Data_Registers[rd] <= read_data[31:0];
            3'b100: Data_Registers[rd] <= {{24{1'b0}}, read_data[7:0]};
            3'b101: Data_Registers[rd] <= {{16{1'b0}}, read_data[15:0]};
            default: Data_Registers[rd] <= read_data[31:0];
          endcase 
        end else begin
          Data_Registers[rd] = alu_output;
        end
      end
    end
  end
  
  always_ff @(posedge clk) begin 
    la_read_data <= Data_Registers[la_reg_select];  
  end
  

  always_ff @(posedge clk) begin  
    rs1_data <= Data_Registers[rs1];
    rs2_data <= Data_Registers[rs2];
  end  
  
  logic [5:0] aluctl;
  logic [31:0] alu_result;
  
  always_comb begin
    

    if ((opcode == 7'b0110011) & (funct3 == 3'b000) & (funct7 == 7'b0000000)) begin
      aluctl = 6'b000000;
      end
    else if ((opcode == 7'b0110011) & (funct3 == 3'b000) & (funct7 == 7'b0100000)) begin
      aluctl = 6'b000001;
      end
    else if ((opcode == 7'b0110011) & (funct3 == 3'b100) & (funct7 == 7'b0000000)) begin
      aluctl = 6'b000010;
      end
    else if ((opcode == 7'b0110011) & (funct3 == 3'b110) & (funct7 == 7'b0000000)) begin
      aluctl = 6'b000011;
      end  
    else if ((opcode == 7'b0110011) & (funct3 == 3'b111) & (funct7 == 7'b0000000)) begin
      aluctl = 6'b000100;
      end
    else if ((opcode == 7'b0110011) & (funct3 == 3'b001) & (funct7 == 7'b0000000)) begin
      aluctl = 6'b000101;
      end
    else if ((opcode == 7'b0110011) & (funct3 == 3'b101) & (funct7 == 7'b0000000)) begin
      aluctl = 6'b000110;
      end
    else if ((opcode == 7'b0110011) & (funct3 == 3'b101) & (funct7 == 7'b0100000)) begin
      aluctl = 6'b000111;
      end
    else if ((opcode == 7'b0110011) & (funct3 == 3'b010) & (funct7 == 7'b0000000)) begin
      aluctl = 6'b001000;
      end
    else if ((opcode == 7'b0110011) & (funct3 == 3'b011) & (funct7 == 7'b0000000)) begin
      aluctl = 6'b001001;
      end
      



    else if ((opcode == 7'b0010011) & (funct3 == 3'b000)) begin
      aluctl = 6'b000000;
      end
    else if ((opcode == 7'b0010011) & (funct3 == 3'b100)) begin
      aluctl = 6'b000010;
      end
    else if ((opcode == 7'b0010011) & (funct3 == 3'b110)) begin
      aluctl = 6'b000011;
      end
    else if ((opcode == 7'b0010011) & (funct3 == 3'b111)) begin
      aluctl = 6'b000100;
      end
    else if ((opcode == 7'b0010011) & (funct3 == 3'b001) & (immediate[11:5] == 0)) begin
      aluctl = 6'b000101;
      end
    else if ((opcode == 7'b0010011) & (funct3 == 3'b101) & (immediate[11:5] == 0)) begin
      aluctl = 6'b000110;
      end
    else if ((opcode == 7'b0010011) & (funct3 == 3'b101) & (immediate[11:5] == 6'b000001)) begin
      aluctl = 6'b000111;
      end
    else if ((opcode == 7'b0010011) & (funct3 == 3'b010)) begin
      aluctl = 6'b001000;
      end
    else if ((opcode == 7'b0010011) & (funct3 == 3'b011)) begin
      aluctl = 6'b001001;
      end
    

    else if ((opcode == 7'b0000011) & (funct3 == 3'b000)) begin
      aluctl = 6'b000000;
      end
    else if ((opcode == 7'b0000011) & (funct3 == 3'b001)) begin
      aluctl = 6'b000000;
      end
    else if ((opcode == 7'b0000011) & (funct3 == 3'b010)) begin
      aluctl = 6'b000000;
      end
    else if ((opcode == 7'b0000011) & (funct3 == 3'b100)) begin
      aluctl = 6'b000000;
      end 
    else if ((opcode == 7'b0000011) & (funct3 == 3'b101)) begin
      aluctl = 6'b000000;
      end
    

    else if ((opcode == 7'b1100111) & (funct3 == 3'b000)) begin
      aluctl = 6'b011000;
      end
    

    else if ((opcode == 7'b1110011) & (funct3 == 3'b000) & (immediate == 0)) begin
      aluctl = 6'b011001;
      end
    else if ((opcode == 7'b1110011) & (funct3 == 3'b000) & (immediate == 1)) begin
      aluctl = 6'b011010;
      end
      



    


    else if ((opcode == 7'b0100011) & (funct3 == 3'b000)) begin
      aluctl = 6'b000000;
      end
    else if ((opcode == 7'b0100011) & (funct3 == 3'b001)) begin
      aluctl = 6'b000000;
      end
    else if ((opcode == 7'b0100011) & (funct3 == 3'b010)) begin
      aluctl = 6'b000000;
      end



    else if ((opcode == 7'b1100011) & (funct3 == 3'b000)) begin
      aluctl = 6'b011110;
      end
    else if ((opcode == 7'b1100011) & (funct3 == 3'b001)) begin
      aluctl = 6'b011111;
      end
    else if ((opcode == 7'b1100011) & (funct3 == 3'b100)) begin
      aluctl = 6'b100000;
      end
    else if ((opcode == 7'b1100011) & (funct3 == 3'b101)) begin
      aluctl = 6'b100001;
      end
    else if ((opcode == 7'b1100011) & (funct3 == 3'b110)) begin
      aluctl = 6'b100010;
      end
    else if ((opcode == 7'b1100011) & (funct3 == 3'b111)) begin
      aluctl = 6'b100011;
      end
      


    else if ((opcode == 7'b1101111)) begin
      aluctl = 6'b100100;
      end
    


    else if ((opcode == 7'b0110111)) begin
      aluctl = 6'b100101;
      end
    else if ((opcode == 7'b0010111)) begin
      aluctl = 6'b100110;
      end
      
    else aluctl = 6'b111111;
      
  end
   

  logic a_input;
  logic b_input;
  
  assign a_input = rs1_data;
  assign b_input = immediate_sel ? immediate : rs2_data;


  always_comb begin
    case (aluctl)
      6'b000000: alu_result = a_input + b_input;
      6'b000001: alu_result = a_input - b_input;
      6'b000010: alu_result = a_input ^ b_input;
      6'b000011: alu_result = a_input | b_input;
      6'b000100: alu_result = a_input & b_input;
      6'b000101: alu_result = a_input << b_input;
      6'b000110: alu_result = a_input >> b_input;
      6'b000111: alu_result = a_input >>> b_input;
      6'b001000: alu_result = (a_input < b_input) ? 1 : 0;
      6'b001001: alu_result = (a_input < b_input) ? 1 : 0;
      6'b011000: alu_result = pc + 4;
      6'b011001: alu_result = 0;
      6'b011010: alu_result = 0;
      6'b011110: alu_result = (a_input == b_input);
      6'b011111: alu_result = (a_input != b_input);
      6'b100000: alu_result = (a_input < b_input);
      6'b100001: alu_result = (a_input >= b_input);
      6'b100010: alu_result = (a_input < b_input);
      6'b100011: alu_result = (a_input >= b_input);
      6'b100100: alu_result = pc + 4;
      6'b100101: alu_result = b_input;
      6'b100110: alu_result = pc + b_input;
      default: alu_result = 0;
    endcase
      
  end 
  
  assign alu_output = alu_result;

endmodule
module ALU

(
  `ifdef USE_POWER_PINS
      inout vccd1,
      inout vssd1,
  `endif
  
  input logic         clk,
  input logic         rst_n,
  input logic  [31:0] pc,
  input logic         reg_write,
  input logic  [5:0]  instruction_type,
  input logic  [6:0]  opcode,
  input logic  [4:0]  rd, 
  input logic  [4:0]  rs1, 
  input logic  [4:0]  rs2, 
  input logic  [2:0]  funct3, 
  input logic  [6:0]  funct7, 
  input logic  [31:0] immediate,
  input logic         immediate_sel,
  input logic  [31:0] read_data,
  
  input  logic [4:0]  la_reg_select,
  
  output logic [31:0] alu_output,
  output logic [31:0] rs1_data,
  output logic [31:0] rs2_data,
  
  output logic [31:0] la_read_data
  
);



  logic [31:0] Data_Registers[31:0];
  
  integer i;
  always_ff @(negedge clk) begin
    if (!rst_n) begin
      for (i=0;i<32;i=i+1)
        Data_Registers[i] = 0;
    end else begin
      if (reg_write && (rd != 0)) begin
        if (instruction_type == 6'b000010 && opcode == 7'b0000011) begin
          case (funct3)
            3'b000: Data_Registers[rd] <= {{24{read_data[7]}}, read_data[7:0]};
            3'b001: Data_Registers[rd] <= {{16{read_data[7]}}, read_data[15:0]};
            3'b010: Data_Registers[rd] <= read_data[31:0];
            3'b100: Data_Registers[rd] <= {{24{1'b0}}, read_data[7:0]};
            3'b101: Data_Registers[rd] <= {{16{1'b0}}, read_data[15:0]};
            default: Data_Registers[rd] <= read_data[31:0];
          endcase 
        end else begin
          Data_Registers[rd] = alu_output;
        end
      end
    end
  end
  
  always_ff @(posedge clk) begin 
    la_read_data <= Data_Registers[la_reg_select];  
  end
  

  always_ff @(posedge clk) begin  
    rs1_data <= Data_Registers[rs1];
    rs2_data <= Data_Registers[rs2];
  end  
  
  logic [5:0] aluctl;
  logic [31:0] alu_result;
  
  always_comb begin
    

    if ((opcode == 7'b0110011) & (funct3 == 3'b000) & (funct7 == 7'b0000000)) begin
      aluctl = 6'b000000;
      end
    else if ((opcode == 7'b0110011) & (funct3 == 3'b000) & (funct7 == 7'b0100000)) begin
      aluctl = 6'b000001;
      end
    else if ((opcode == 7'b0110011) & (funct3 == 3'b100) & (funct7 == 7'b0000000)) begin
      aluctl = 6'b000010;
      end
    else if ((opcode == 7'b0110011) & (funct3 == 3'b110) & (funct7 == 7'b0000000)) begin
      aluctl = 6'b000011;
      end  
    else if ((opcode == 7'b0110011) & (funct3 == 3'b111) & (funct7 == 7'b0000000)) begin
      aluctl = 6'b000100;
      end
    else if ((opcode == 7'b0110011) & (funct3 == 3'b001) & (funct7 == 7'b0000000)) begin
      aluctl = 6'b000101;
      end
    else if ((opcode == 7'b0110011) & (funct3 == 3'b101) & (funct7 == 7'b0000000)) begin
      aluctl = 6'b000110;
      end
    else if ((opcode == 7'b0110011) & (funct3 == 3'b101) & (funct7 == 7'b0100000)) begin
      aluctl = 6'b000111;
      end
    else if ((opcode == 7'b0110011) & (funct3 == 3'b010) & (funct7 == 7'b0000000)) begin
      aluctl = 6'b001000;
      end
    else if ((opcode == 7'b0110011) & (funct3 == 3'b011) & (funct7 == 7'b0000000)) begin
      aluctl = 6'b001001;
      end
      



    else if ((opcode == 7'b0010011) & (funct3 == 3'b000)) begin
      aluctl = 6'b000000;
      end
    else if ((opcode == 7'b0010011) & (funct3 == 3'b100)) begin
      aluctl = 6'b000010;
      end
    else if ((opcode == 7'b0010011) & (funct3 == 3'b110)) begin
      aluctl = 6'b000011;
      end
    else if ((opcode == 7'b0010011) & (funct3 == 3'b111)) begin
      aluctl = 6'b000100;
      end
    else if ((opcode == 7'b0010011) & (funct3 == 3'b001) & (immediate[11:5] == 0)) begin
      aluctl = 6'b000101;
      end
    else if ((opcode == 7'b0010011) & (funct3 == 3'b101) & (immediate[11:5] == 0)) begin
      aluctl = 6'b000110;
      end
    else if ((opcode == 7'b0010011) & (funct3 == 3'b101) & (immediate[11:5] == 6'b000001)) begin
      aluctl = 6'b000111;
      end
    else if ((opcode == 7'b0010011) & (funct3 == 3'b010)) begin
      aluctl = 6'b001000;
      end
    else if ((opcode == 7'b0010011) & (funct3 == 3'b011)) begin
      aluctl = 6'b001001;
      end
    

    else if ((opcode == 7'b0000011) & (funct3 == 3'b000)) begin
      aluctl = 6'b000000;
      end
    else if ((opcode == 7'b0000011) & (funct3 == 3'b001)) begin
      aluctl = 6'b000000;
      end
    else if ((opcode == 7'b0000011) & (funct3 == 3'b010)) begin
      aluctl = 6'b000000;
      end
    else if ((opcode == 7'b0000011) & (funct3 == 3'b100)) begin
      aluctl = 6'b000000;
      end 
    else if ((opcode == 7'b0000011) & (funct3 == 3'b101)) begin
      aluctl = 6'b000000;
      end
    

    else if ((opcode == 7'b1100111) & (funct3 == 3'b000)) begin
      aluctl = 6'b011000;
      end
    

    else if ((opcode == 7'b1110011) & (funct3 == 3'b000) & (immediate == 0)) begin
      aluctl = 6'b011001;
      end
    else if ((opcode == 7'b1110011) & (funct3 == 3'b000) & (immediate == 1)) begin
      aluctl = 6'b011010;
      end
      



    


    else if ((opcode == 7'b0100011) & (funct3 == 3'b000)) begin
      aluctl = 6'b000000;
      end
    else if ((opcode == 7'b0100011) & (funct3 == 3'b001)) begin
      aluctl = 6'b000000;
      end
    else if ((opcode == 7'b0100011) & (funct3 == 3'b010)) begin
      aluctl = 6'b000000;
      end



    else if ((opcode == 7'b1100011) & (funct3 == 3'b000)) begin
      aluctl = 6'b011110;
      end
    else if ((opcode == 7'b1100011) & (funct3 == 3'b001)) begin
      aluctl = 6'b011111;
      end
    else if ((opcode == 7'b1100011) & (funct3 == 3'b100)) begin
      aluctl = 6'b100000;
      end
    else if ((opcode == 7'b1100011) & (funct3 == 3'b101)) begin
      aluctl = 6'b100001;
      end
    else if ((opcode == 7'b1100011) & (funct3 == 3'b110)) begin
      aluctl = 6'b100010;
      end
    else if ((opcode == 7'b1100011) & (funct3 == 3'b111)) begin
      aluctl = 6'b100011;
      end
      


    else if ((opcode == 7'b1101111)) begin
      aluctl = 6'b100100;
      end
    


    else if ((opcode == 7'b0110111)) begin
      aluctl = 6'b100101;
      end
    else if ((opcode == 7'b0010111)) begin
      aluctl = 6'b100110;
      end
      
    else aluctl = 6'b111111;
      
  end
   

  logic a_input;
  logic b_input;
  
  assign a_input = rs1_data;
  assign b_input = immediate_sel ? immediate : rs2_data;


  always_comb begin
    case (aluctl)
      6'b000000: alu_result = a_input + b_input;
      6'b000001: alu_result = a_input - b_input;
      6'b000010: alu_result = a_input ^ b_input;
      6'b000011: alu_result = a_input | b_input;
      6'b000100: alu_result = a_input & b_input;
      6'b000101: alu_result = a_input << b_input;
      6'b000110: alu_result = a_input >> b_input;
      6'b000111: alu_result = a_input >>> b_input;
      6'b001000: alu_result = (a_input < b_input) ? 1 : 0;
      6'b001001: alu_result = (a_input < b_input) ? 1 : 0;
      6'b011000: alu_result = pc + 4;
      6'b011001: alu_result = 0;
      6'b011010: alu_result = 0;
      6'b011110: alu_result = (a_input == b_input);
      6'b011111: alu_result = (a_input != b_input);
      6'b100000: alu_result = (a_input < b_input);
      6'b100001: alu_result = (a_input >= b_input);
      6'b100010: alu_result = (a_input < b_input);
      6'b100011: alu_result = (a_input >= b_input);
      6'b100100: alu_result = pc + 4;
      6'b100101: alu_result = b_input;
      6'b100110: alu_result = pc + b_input;
      default: alu_result = 0;
    endcase
      
  end 
  
  assign alu_output = alu_result;

endmodule