data/full_repos/permissive/431687600/Proc_SRC/register_file.v
data/verilator_xmls/241db37d-3742-4607-b152-eccdadbd1fc3.xml
module register_file(
	input clk,reset,i_memWrite,i_memRead,
	input [2:0] i_address1,i_address2,i_destReg,
	input [12:0] i_ALUresult,
	output reg [12:0] o_dataA, o_dataB);

	reg [12:0] memory [7:0];
	
	always@(posedge clk) begin
	if(reset == 1'b1) begin
		memory[0] <= 13'b0000_000_000_001;
		memory[1] <= 13'b0000_000_000_001;
		memory[2] <= 13'b0000_000_000_100;
		memory[3] <= 13'b0000_000_000_110;
		memory[4] <= 13'b0000_000_000_101;
		memory[5] <= 13'b0000_000_000_011;
		memory[6] <= 13'b0000_000_000_101;
	end
	else if(i_memWrite == 1'b1) begin
		memory[i_destReg] <= i_ALUresult;
	end
	else if(i_memRead == 1'b1) begin
		o_dataA <= memory[i_address1];
		o_dataB <= memory[i_address2];
	end




	end
endmodule
module register_file(
	input clk,reset,i_memWrite,i_memRead,
	input [2:0] i_address1,i_address2,i_destReg,
	input [12:0] i_ALUresult,
	output reg [12:0] o_dataA, o_dataB);


	reg [12:0] memory [7:0];
	
	always@(posedge clk) begin
	if(reset == 1'b1) begin
		memory[0] <= 13'b0000_000_000_001;
		memory[1] <= 13'b0000_000_000_001;
		memory[2] <= 13'b0000_000_000_100;
		memory[3] <= 13'b0000_000_000_110;
		memory[4] <= 13'b0000_000_000_101;
		memory[5] <= 13'b0000_000_000_011;
		memory[6] <= 13'b0000_000_000_101;
	end
	else if(i_memWrite == 1'b1) begin
		memory[i_destReg] <= i_ALUresult;
	end
	else if(i_memRead == 1'b1) begin
		o_dataA <= memory[i_address1];
		o_dataB <= memory[i_address2];
	end




	end
endmodule