data/full_repos/permissive/474721296/ctrl/ctrl_tb.v
1: b'%Error: data/full_repos/permissive/474721296/ctrl/ctrl_tb.v:6: Cannot find include file: ../mem/mem.v\n`include "../mem/mem.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/474721296/ctrl,data/full_repos/permissive/474721296/../mem/mem.v\n             data/full_repos/permissive/474721296/ctrl,data/full_repos/permissive/474721296/../mem/mem.v.v\n             data/full_repos/permissive/474721296/ctrl,data/full_repos/permissive/474721296/../mem/mem.v.sv\n             ../mem/mem.v\n             ../mem/mem.v.v\n             ../mem/mem.v.sv\n             obj_dir/../mem/mem.v\n             obj_dir/../mem/mem.v.v\n             obj_dir/../mem/mem.v.sv\n%Error: data/full_repos/permissive/474721296/ctrl/ctrl_tb.v:7: Cannot find include file: ../alu/alu.v\n`include "../alu/alu.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/474721296/ctrl/ctrl_tb.v:8: Cannot find include file: ../mult/mult.v\n`include "../mult/mult.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/474721296/ctrl/ctrl_tb.v:9: Cannot find include file: ../div/div.v\n`include "../div/div.v" \n         ^~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/474721296/ctrl/ctrl_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n always #20 clock = !clock;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/474721296/ctrl/ctrl_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #1 clock <= 1;  \n  ^\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module ctrl_tb;
	reg clock;

	wire mem_clock;
	wire mem_write;
	wire[7:0] address;
	wire[7:0] to_mem;
	wire[7:0] from_mem;

	ctrl test_ctrl(
		clock,

		address,
		from_mem,
		to_mem,
		mem_clock,
		mem_write
	);

	mem test_mem(
		mem_clock,
		mem_write,
		address,
		to_mem,
		from_mem
	);

	always #20 clock = !clock;

	initial begin
		#1 clock <= 1;
	end
endmodule
module ctrl_tb;

	reg clock;

	wire mem_clock;
	wire mem_write;
	wire[7:0] address;
	wire[7:0] to_mem;
	wire[7:0] from_mem;

	ctrl test_ctrl(
		clock,

		address,
		from_mem,
		to_mem,
		mem_clock,
		mem_write
	);

	mem test_mem(
		mem_clock,
		mem_write,
		address,
		to_mem,
		from_mem
	);

	always #20 clock = !clock;

	initial begin
		#1 clock <= 1;
	end
endmodule