data/full_repos/permissive/441359809/src/yosys/examples/igloo2/example.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/examples/igloo2/example.v:37: Multiple top level modules\n                                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                              : ... Top module \'example\'\nmodule example (\n       ^~~~~~~\n                                                                                              : ... Top module \'seg7enc\'\nmodule seg7enc (\n       ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/examples/igloo2/example.v:21: Operator ADD expects 32 or 30 bits on the RHS, but RHS\'s VARREF \'SW1\' generates 1 bits.\n                                                                                           : ... In instance example\n  counter <= counter + SW1 + SW2 + 1;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/examples/igloo2/example.v:21: Operator ADD expects 32 or 30 bits on the RHS, but RHS\'s VARREF \'SW2\' generates 1 bits.\n                                                                                           : ... In instance example\n  counter <= counter + SW1 + SW2 + 1;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/examples/igloo2/example.v:22: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 30 bits.\n                                                                                           : ... In instance example\n  outcnt <= counter >> LOG2DELAY;\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/examples/igloo2/example.v:25: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s XOR generates 8 bits.\n                                                                                           : ... In instance example\n assign {LED1, LED2, LED3, LED4} = outcnt ^ (outcnt >> 1);\n                                 ^\n%Error: Exiting due to 5 warning(s)\n'
module seg7enc (
	input [3:0] dat,
	output [6:0] seg
);
	reg [6:0] seg_inv;
	always @* begin
		seg_inv = 0;
		case (dat)
			4'h0: seg_inv = 7'b 0111111;
			4'h1: seg_inv = 7'b 0000110;
			4'h2: seg_inv = 7'b 1011011;
			4'h3: seg_inv = 7'b 1001111;
			4'h4: seg_inv = 7'b 1100110;
			4'h5: seg_inv = 7'b 1101101;
			4'h6: seg_inv = 7'b 1111101;
			4'h7: seg_inv = 7'b 0000111;
			4'h8: seg_inv = 7'b 1111111;
			4'h9: seg_inv = 7'b 1101111;
			4'hA: seg_inv = 7'b 1110111;
			4'hB: seg_inv = 7'b 1111100;
			4'hC: seg_inv = 7'b 0111001;
			4'hD: seg_inv = 7'b 1011110;
			4'hE: seg_inv = 7'b 1111001;
			4'hF: seg_inv = 7'b 1110001;
		endcase
	end
	assign seg = ~seg_inv;
endmodule
module seg7enc (
	input [3:0] dat,
	output [6:0] seg
);

	reg [6:0] seg_inv;
	always @* begin
		seg_inv = 0;
		case (dat)
			4'h0: seg_inv = 7'b 0111111;
			4'h1: seg_inv = 7'b 0000110;
			4'h2: seg_inv = 7'b 1011011;
			4'h3: seg_inv = 7'b 1001111;
			4'h4: seg_inv = 7'b 1100110;
			4'h5: seg_inv = 7'b 1101101;
			4'h6: seg_inv = 7'b 1111101;
			4'h7: seg_inv = 7'b 0000111;
			4'h8: seg_inv = 7'b 1111111;
			4'h9: seg_inv = 7'b 1101111;
			4'hA: seg_inv = 7'b 1110111;
			4'hB: seg_inv = 7'b 1111100;
			4'hC: seg_inv = 7'b 0111001;
			4'hD: seg_inv = 7'b 1011110;
			4'hE: seg_inv = 7'b 1111001;
			4'hF: seg_inv = 7'b 1110001;
		endcase
	end
	assign seg = ~seg_inv;
endmodule