data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:30: Cannot find include file: sys.h\n`include "sys.h" // system level definition file which contains the  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:32: Cannot find include file: iop.h\n`include        "iop.h" \n                ^~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:72: Define or directive not defined: \'`PCX_WIDTH\'\n   input [`PCX_WIDTH-1:0]        pcx_packet;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:73: Define or directive not defined: \'`UCB_64PAY_PKT_WIDTH\'\n   input [`UCB_64PAY_PKT_WIDTH-1:0]   tap_packet;\n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:77: Define or directive not defined: \'`UCB_PKT_WIDTH\'\n   output [`UCB_PKT_WIDTH-1:0]        cpu_packet_type;\n           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:79: Define or directive not defined: \'`UCB_ADDR_WIDTH\'\n   input [`UCB_ADDR_WIDTH-1:0]        c2i_packet_addr;\n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:83: Define or directive not defined: \'`IOB_CPU_BUF_INDEX\'\n   input [`IOB_CPU_BUF_INDEX:0]       cpu_buf_tail_f;\n          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:83: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   input [`IOB_CPU_BUF_INDEX:0]       cpu_buf_tail_f;\n                            ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:84: Define or directive not defined: \'`IOB_CPU_BUF_INDEX\'\n   output [`IOB_CPU_BUF_INDEX:0]      cpu_buf_head_s;\n           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:84: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   output [`IOB_CPU_BUF_INDEX:0]      cpu_buf_head_s;\n                             ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:93: Define or directive not defined: \'`IOB_CPU_BUF_INDEX\'\n   output [`IOB_CPU_BUF_INDEX-1:0]    cpu_buf_head_ptr;\n           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:135: Define or directive not defined: \'`IOB_CPU_BUF_INDEX\'\n   wire [`IOB_CPU_BUF_INDEX:0]        cpu_buf_head;\n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:135: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   wire [`IOB_CPU_BUF_INDEX:0]        cpu_buf_head;\n                           ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:136: Define or directive not defined: \'`IOB_CPU_BUF_INDEX\'\n   wire [`IOB_CPU_BUF_INDEX:0]        cpu_buf_head_d1;\n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:136: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   wire [`IOB_CPU_BUF_INDEX:0]        cpu_buf_head_d1;\n                           ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:137: Define or directive not defined: \'`IOB_CPU_BUF_INDEX\'\n   wire [`IOB_CPU_BUF_INDEX:0]        cpu_buf_head_plus1;\n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:137: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   wire [`IOB_CPU_BUF_INDEX:0]        cpu_buf_head_plus1;\n                           ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:139: Define or directive not defined: \'`IOB_CPU_BUF_INDEX\'\n   wire [`IOB_CPU_BUF_INDEX:0]        cpu_buf_tail;\n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:139: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   wire [`IOB_CPU_BUF_INDEX:0]        cpu_buf_tail;\n                           ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:152: Define or directive not defined: \'`UCB_PKT_WIDTH\'\n   reg [`UCB_PKT_WIDTH-1:0]        cpu_packet_type;\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:165: Define or directive not defined: \'`ADDR_MAP_HI\'\n   wire [`ADDR_MAP_HI-`ADDR_MAP_LO:0] c2i_packet_addr_msb;\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:165: Define or directive not defined: \'`ADDR_MAP_LO\'\n   wire [`ADDR_MAP_HI-`ADDR_MAP_LO:0] c2i_packet_addr_msb;\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:165: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   wire [`ADDR_MAP_HI-`ADDR_MAP_LO:0] c2i_packet_addr_msb;\n                                  ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:185: Define or directive not defined: \'`IOB_CPU_BUF_INDEX\'\n   dffrl_ns #(`IOB_CPU_BUF_INDEX+1) cpu_buf_head_d1_ff (.din(cpu_buf_head),\n              ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:195: Define or directive not defined: \'`IOB_CPU_BUF_INDEX\'\n   assign  cpu_buf_head_ptr = cpu_buf_head[`IOB_CPU_BUF_INDEX-1:0];\n                                           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:200: Define or directive not defined: \'`IOB_CPU_BUF_INDEX\'\n   dffrl_ns #(`IOB_CPU_BUF_INDEX+1) cpu_buf_tail_ff (.din(cpu_buf_tail_f),\n              ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:260: Define or directive not defined: \'`UCB_PKT_WIDTH\'\n      cpu_packet_type = `UCB_PKT_WIDTH\'bx;\n                        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:261: Define or directive not defined: \'`PCX_RQ_HI\'\n      case (pcx_packet[`PCX_RQ_HI:`PCX_RQ_LO]) \n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:261: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n      case (pcx_packet[`PCX_RQ_HI:`PCX_RQ_LO]) \n                                 ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:261: Define or directive not defined: \'`PCX_RQ_LO\'\n      case (pcx_packet[`PCX_RQ_HI:`PCX_RQ_LO]) \n                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:262: Define or directive not defined: \'`LOAD_RQ\'\n `LOAD_RQ:begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:267: Define or directive not defined: \'`UCB_READ_REQ\'\n    cpu_packet_type = `UCB_READ_REQ;\n                      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:267: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    cpu_packet_type = `UCB_READ_REQ;\n                                   ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:269: Define or directive not defined: \'`IMISS_RQ\'\n `IMISS_RQ:begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:269: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `IMISS_RQ:begin\n           ^~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:274: Define or directive not defined: \'`UCB_IFILL_REQ\'\n    cpu_packet_type = `UCB_IFILL_REQ;\n                      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:274: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    cpu_packet_type = `UCB_IFILL_REQ;\n                                    ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:276: Define or directive not defined: \'`STORE_RQ\'\n `STORE_RQ:begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:276: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `STORE_RQ:begin\n           ^~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:281: Define or directive not defined: \'`UCB_WRITE_REQ\'\n    cpu_packet_type = `UCB_WRITE_REQ;\n                      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:281: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    cpu_packet_type = `UCB_WRITE_REQ;\n                                    ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:283: Define or directive not defined: \'`FWD_RPY\'\n `FWD_RPY:begin\n ^~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:283: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `FWD_RPY:begin\n          ^~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:290: Define or directive not defined: \'`PCX_R\'\n    cpu_packet_type = ~pcx_packet[`PCX_R]       ? `UCB_WRITE_ACK :\n                                  ^~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:290: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    cpu_packet_type = ~pcx_packet[`PCX_R]       ? `UCB_WRITE_ACK :\n                                        ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:290: Define or directive not defined: \'`UCB_WRITE_ACK\'\n    cpu_packet_type = ~pcx_packet[`PCX_R]       ? `UCB_WRITE_ACK :\n                                                  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:291: Define or directive not defined: \'`PCX_ERR_LO\'\n        pcx_packet[`PCX_ERR_LO+1] ? `UCB_READ_NACK :\n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:291: Define or directive not defined: \'`UCB_READ_NACK\'\n        pcx_packet[`PCX_ERR_LO+1] ? `UCB_READ_NACK :\n                                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:292: Define or directive not defined: \'`UCB_READ_ACK\'\n                                    `UCB_READ_ACK;\n                                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sctrl.v:303: Define or directive not defined: \'`PCX_RQ_HI\'\n   assign  cpu_packet_needs_wr_ack = pcx_packet[`PCX_RQ_HI:`PCX_RQ_LO] == `STORE_RQ;\n                                                ^~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module c2i_sctrl (

   iob_tap_busy, cpu_buf_rd, tap_sel, cpu_packet_is_req, 
   cpu_packet_type, cpu_buf_head_s, srvc_wr_ack, cpu_buf_head_ptr, 
   cpu_buf_rd_l, c2i_packet_vld, c2i_packet_is_rd_req, 
   c2i_packet_is_wr_req, jbi_ucb_sel, clk_ucb_sel, dram0_ucb_sel, 
   dram1_ucb_sel, iob_man_ucb_sel, iob_int_ucb_sel, spi_ucb_sel, 
   bounce_ucb_sel, rd_nack_ucb_sel, ucb_buf_acpt, 

   rst_l, clk, tap_iob_packet_vld, pcx_packet, tap_packet, 
   c2i_packet_addr, cpu_buf_tail_f, io_buf_avail, jbi_ucb_buf_acpt, 
   clk_ucb_buf_acpt, dram0_ucb_buf_acpt, dram1_ucb_buf_acpt, 
   iob_man_ucb_buf_acpt, iob_int_ucb_buf_acpt, spi_ucb_buf_acpt, 
   bounce_ucb_buf_acpt, rd_nack_ucb_buf_acpt
   );
   




   input                              rst_l;
   input 			      clk;



   input 			      tap_iob_packet_vld;
   output 			      iob_tap_busy;
   


   input [`PCX_WIDTH-1:0] 	      pcx_packet;
   input [`UCB_64PAY_PKT_WIDTH-1:0]   tap_packet;
   output 			      cpu_buf_rd;
   output 			      tap_sel;
   output 			      cpu_packet_is_req;
   output [`UCB_PKT_WIDTH-1:0] 	      cpu_packet_type;
   
   input [`UCB_ADDR_WIDTH-1:0] 	      c2i_packet_addr;
   
   

   input [`IOB_CPU_BUF_INDEX:0]       cpu_buf_tail_f;
   output [`IOB_CPU_BUF_INDEX:0]      cpu_buf_head_s;



   input 			      io_buf_avail;
   output 			      srvc_wr_ack;

   

   output [`IOB_CPU_BUF_INDEX-1:0]    cpu_buf_head_ptr;
   output 			      cpu_buf_rd_l;
   


   output 			      c2i_packet_vld;
   output 			      c2i_packet_is_rd_req;
   output 			      c2i_packet_is_wr_req;
   
   output 			      jbi_ucb_sel;
   input 			      jbi_ucb_buf_acpt;
   
   output 			      clk_ucb_sel;
   input 			      clk_ucb_buf_acpt;

   output 			      dram0_ucb_sel;
   input 			      dram0_ucb_buf_acpt;

   output 			      dram1_ucb_sel;
   input 			      dram1_ucb_buf_acpt;

   output 			      iob_man_ucb_sel;
   input 			      iob_man_ucb_buf_acpt;
   
   output 			      iob_int_ucb_sel;
   input 			      iob_int_ucb_buf_acpt;
   
   output 			      spi_ucb_sel;
   input 			      spi_ucb_buf_acpt;

   output 			      bounce_ucb_sel;
   input 			      bounce_ucb_buf_acpt;
   
   output 			      rd_nack_ucb_sel;
   input 			      rd_nack_ucb_buf_acpt;

   

   output 			      ucb_buf_acpt;

   

   wire [`IOB_CPU_BUF_INDEX:0] 	      cpu_buf_head;
   wire [`IOB_CPU_BUF_INDEX:0] 	      cpu_buf_head_d1;
   wire [`IOB_CPU_BUF_INDEX:0] 	      cpu_buf_head_plus1;
   wire 			      cpu_buf_head_inc;
   wire [`IOB_CPU_BUF_INDEX:0] 	      cpu_buf_tail;
   wire 			      cpu_buf_empty;
   wire 			      cpu_buf_empty_d1;

   wire 			      cpu_vld;
   wire 			      cpu_vld_next;
   wire 			      tap_vld;
   wire 			      cpu_sel;
   
   reg 				      cpu_packet_is_rd_req;
   reg 				      cpu_packet_is_wr_req;
   reg 				      cpu_packet_is_if_req;
   reg 				      cpu_packet_is_ack;
   reg [`UCB_PKT_WIDTH-1:0] 	      cpu_packet_type;
   wire 			      cpu_packet_needs_wr_ack;
   wire 			      cpu_packet_is_8B;
   
   reg 				      tap_packet_is_rd_req;
   reg 				      tap_packet_is_wr_req;
   reg 				      tap_packet_is_ack;
   wire 			      tap_packet_is_8B;
   
   wire 			      c2i_packet_is_ack;
   wire 			      c2i_packet_is_if_req;
   wire 			      c2i_packet_is_8B;
   
   wire [`ADDR_MAP_HI-`ADDR_MAP_LO:0] c2i_packet_addr_msb;

   wire 			      mem_ucb_sel;
   wire 			      l2_ucb_sel;
   wire 			      tap_ucb_sel;
   wire 			      asi_ucb_sel;
   
   
   wire 			      no_match_ucb;
   
   wire 			      blackhole_acpt;
   
   





   dffrl_ns #(`IOB_CPU_BUF_INDEX+1) cpu_buf_head_d1_ff (.din(cpu_buf_head),
							.clk(clk),
							.rst_l(rst_l),
							.q(cpu_buf_head_d1));
   
   assign       cpu_buf_head_plus1 = cpu_buf_head_d1 + 5'b1;
   
   assign 	cpu_buf_head = cpu_buf_head_inc ? cpu_buf_head_plus1 :
	                                          cpu_buf_head_d1;
   
   assign 	cpu_buf_head_ptr = cpu_buf_head[`IOB_CPU_BUF_INDEX-1:0];
   
   assign 	cpu_buf_head_s = cpu_buf_head_d1;
   

   dffrl_ns #(`IOB_CPU_BUF_INDEX+1) cpu_buf_tail_ff (.din(cpu_buf_tail_f),
						     .clk(clk),
						     .rst_l(rst_l),
						     .q(cpu_buf_tail));


   assign 	cpu_buf_empty = (cpu_buf_head == cpu_buf_tail);

   assign 	cpu_buf_rd_l = cpu_buf_empty;
   
   dff_ns #(1) cpu_buf_empty_d1_ff (.din(cpu_buf_empty|~rst_l),
				    .clk(clk),
				    .q(cpu_buf_empty_d1));

   

   assign 	cpu_buf_rd = ~cpu_buf_empty_d1 &
	                     ((cpu_vld & cpu_sel & ucb_buf_acpt) |
	                      ~cpu_vld);

   assign 	cpu_buf_head_inc = cpu_buf_rd;

   


   assign 	cpu_vld_next = cpu_buf_rd |
	                       (cpu_vld & ~(cpu_sel & ucb_buf_acpt));
   
   dffrl_ns #(1) cpu_vld_ff (.din(cpu_vld_next),
			     .clk(clk),
			     .rst_l(rst_l),
			     .q(cpu_vld));

   assign 	tap_vld = tap_iob_packet_vld;

   

   assign 	tap_sel = tap_vld;
   assign 	cpu_sel = ~tap_vld;


   assign 	iob_tap_busy = tap_vld & ~ucb_buf_acpt;
   

   assign 	c2i_packet_vld = tap_vld |
	                         (cpu_vld &
				  ~(cpu_packet_needs_wr_ack & ~io_buf_avail));
   
   

   always @(pcx_packet) begin

      cpu_packet_is_rd_req = 1'b0;
      cpu_packet_is_wr_req = 1'b0;
      cpu_packet_is_if_req = 1'b0;
      cpu_packet_is_ack = 1'b0;
      cpu_packet_type = `UCB_PKT_WIDTH'bx;
      case (pcx_packet[`PCX_RQ_HI:`PCX_RQ_LO]) 
	`LOAD_RQ:begin
	   cpu_packet_is_rd_req = 1'b1;
	   cpu_packet_is_wr_req = 1'b0;
	   cpu_packet_is_if_req = 1'b0;
	   cpu_packet_is_ack = 1'b0;
	   cpu_packet_type = `UCB_READ_REQ;
	end
	`IMISS_RQ:begin
	   cpu_packet_is_rd_req = 1'b0;
	   cpu_packet_is_wr_req = 1'b0;
	   cpu_packet_is_if_req = 1'b1;
	   cpu_packet_is_ack = 1'b0;
	   cpu_packet_type = `UCB_IFILL_REQ;
	end
	`STORE_RQ:begin
	   cpu_packet_is_rd_req = 1'b0;
	   cpu_packet_is_wr_req = 1'b1;
	   cpu_packet_is_if_req = 1'b0;
	   cpu_packet_is_ack = 1'b0;
	   cpu_packet_type = `UCB_WRITE_REQ;
	end
	`FWD_RPY:begin
	   cpu_packet_is_rd_req = 1'b0;
	   cpu_packet_is_wr_req = 1'b0;
	   cpu_packet_is_if_req = 1'b0;
	   cpu_packet_is_ack = 1'b1;


	   cpu_packet_type = ~pcx_packet[`PCX_R]       ? `UCB_WRITE_ACK :
			     pcx_packet[`PCX_ERR_LO+1] ? `UCB_READ_NACK :
			                                 `UCB_READ_ACK;
	end
      endcase
   end

   assign       cpu_packet_is_req = cpu_packet_is_rd_req |
				    cpu_packet_is_wr_req |
				    cpu_packet_is_if_req;



   assign 	cpu_packet_needs_wr_ack = pcx_packet[`PCX_RQ_HI:`PCX_RQ_LO] == `STORE_RQ;
   
   assign 	cpu_packet_is_8B = pcx_packet[`PCX_SZ_HI:`PCX_SZ_LO] == `PCX_SZ_8B;
   
   

   always @(tap_packet) begin
      tap_packet_is_rd_req = 1'b0;
      tap_packet_is_wr_req = 1'b0;
      tap_packet_is_ack = 1'b0;
      case (tap_packet[`UCB_PKT_HI:`UCB_PKT_LO])
	`UCB_READ_REQ:begin
	   tap_packet_is_rd_req = 1'b1;
	   tap_packet_is_wr_req = 1'b0;
	   tap_packet_is_ack = 1'b0;
	end
	`UCB_WRITE_REQ:begin
	   tap_packet_is_rd_req = 1'b0;
	   tap_packet_is_wr_req = 1'b1;
	   tap_packet_is_ack = 1'b0;
	end
	`UCB_READ_NACK,
	`UCB_READ_ACK:begin
	   tap_packet_is_rd_req = 1'b0;
	   tap_packet_is_wr_req = 1'b0;
	   tap_packet_is_ack = 1'b1;
	end
      endcase
   end
   
   assign 	tap_packet_is_8B = tap_packet[`UCB_SIZE_HI:`UCB_SIZE_LO] == `UCB_SIZE_8B;
   
   

   assign 	c2i_packet_is_rd_req = tap_sel ? tap_packet_is_rd_req :
		                                 cpu_packet_is_rd_req;
   
   assign 	c2i_packet_is_wr_req = tap_sel ? tap_packet_is_wr_req :
		                                 cpu_packet_is_wr_req;
   
   assign 	c2i_packet_is_if_req = tap_sel ? 1'b0 :
		                                 cpu_packet_is_if_req;
   
   assign 	c2i_packet_is_ack = tap_sel ? tap_packet_is_ack :
		                              cpu_packet_is_ack;
   
   assign 	c2i_packet_is_8B = tap_sel ? tap_packet_is_8B :
		                             cpu_packet_is_8B;

   

   assign 	c2i_packet_addr_msb = c2i_packet_addr[`ADDR_MAP_HI:`ADDR_MAP_LO];
   assign 	mem_ucb_sel      = ((c2i_packet_addr_msb <= `DRAM_DATA_HI) &
				    (c2i_packet_addr_msb >= `DRAM_DATA_LO)) &
				     (c2i_packet_is_rd_req | c2i_packet_is_wr_req);
   assign 	l2_ucb_sel       = ((c2i_packet_addr_msb <= `L2C_CSR_HI) &
				    (c2i_packet_addr_msb >= `L2C_CSR_LO)) &
				     (c2i_packet_is_rd_req | c2i_packet_is_wr_req) &
		                     c2i_packet_is_8B;
   assign 	jbi_ucb_sel      = ((c2i_packet_addr_msb == `JBUS1) |
				    ((c2i_packet_addr_msb <= `JBUS2_HI) &
				     (c2i_packet_addr_msb >= `JBUS2_LO))) &
				     (c2i_packet_is_rd_req | c2i_packet_is_wr_req);
   
   assign 	clk_ucb_sel      = (c2i_packet_addr_msb == `CLOCK_UNIT_CSR) &
				     (c2i_packet_is_rd_req | c2i_packet_is_wr_req) &
		                     c2i_packet_is_8B;

   assign 	dram0_ucb_sel    = ((c2i_packet_addr_msb == `DRAM_CSR) &
				    (c2i_packet_addr[12] == 1'b0)) &
				     (c2i_packet_is_rd_req | c2i_packet_is_wr_req) &
		                     c2i_packet_is_8B;
   assign 	dram1_ucb_sel    = ((c2i_packet_addr_msb == `DRAM_CSR) &
				    (c2i_packet_addr[12] == 1'b1)) &
				     (c2i_packet_is_rd_req | c2i_packet_is_wr_req) &
		                     c2i_packet_is_8B;
   assign 	iob_man_ucb_sel  = (c2i_packet_addr_msb == `IOB_MAN_CSR) &
				     (c2i_packet_is_rd_req | c2i_packet_is_wr_req) &
		                     c2i_packet_is_8B;
   assign 	tap_ucb_sel      = (c2i_packet_addr_msb == `TAP_CSR) &
				     (c2i_packet_is_rd_req | c2i_packet_is_wr_req) &
		                     c2i_packet_is_8B;
   assign 	iob_int_ucb_sel  = (c2i_packet_addr_msb == `IOB_INT_CSR) &
				     (c2i_packet_is_rd_req | c2i_packet_is_wr_req) &
		                     c2i_packet_is_8B;
   
   assign 	asi_ucb_sel      = (c2i_packet_addr_msb == `CPU_ASI) &
				     (c2i_packet_is_rd_req | c2i_packet_is_wr_req) &
		                     c2i_packet_is_8B;
   
   assign 	spi_ucb_sel      = (c2i_packet_addr_msb == `SPI_CSR) &
				     (c2i_packet_is_rd_req |
				      c2i_packet_is_wr_req |
				      c2i_packet_is_if_req);



   assign     bounce_ucb_sel = mem_ucb_sel | l2_ucb_sel | tap_ucb_sel |	asi_ucb_sel | c2i_packet_is_ack;


   assign     no_match_ucb = ~(mem_ucb_sel |
			       l2_ucb_sel |
			       jbi_ucb_sel |
			       clk_ucb_sel |
			       dram0_ucb_sel |
			       dram1_ucb_sel |
			       iob_man_ucb_sel |
			       tap_ucb_sel |
			       iob_int_ucb_sel |
			       asi_ucb_sel |
			       spi_ucb_sel);


   assign     rd_nack_ucb_sel = no_match_ucb &
	                        (c2i_packet_is_rd_req | c2i_packet_is_if_req);
   


   assign     blackhole_acpt = c2i_packet_vld &
	                       ((~c2i_packet_is_rd_req &
				 ~c2i_packet_is_wr_req &
				 ~c2i_packet_is_if_req &
				 ~c2i_packet_is_ack) |
				(no_match_ucb & c2i_packet_is_wr_req));
   


   assign     ucb_buf_acpt = (jbi_ucb_buf_acpt |
			      clk_ucb_buf_acpt |
			      dram0_ucb_buf_acpt |
			      dram1_ucb_buf_acpt |
	                      iob_man_ucb_buf_acpt |
	                      iob_int_ucb_buf_acpt |
			      spi_ucb_buf_acpt |
			      bounce_ucb_buf_acpt |
			      rd_nack_ucb_buf_acpt |
			      blackhole_acpt);



   assign     srvc_wr_ack = cpu_sel & ucb_buf_acpt & cpu_packet_needs_wr_ack;

   
endmodule
module c2i_sctrl (

   iob_tap_busy, cpu_buf_rd, tap_sel, cpu_packet_is_req, 
   cpu_packet_type, cpu_buf_head_s, srvc_wr_ack, cpu_buf_head_ptr, 
   cpu_buf_rd_l, c2i_packet_vld, c2i_packet_is_rd_req, 
   c2i_packet_is_wr_req, jbi_ucb_sel, clk_ucb_sel, dram0_ucb_sel, 
   dram1_ucb_sel, iob_man_ucb_sel, iob_int_ucb_sel, spi_ucb_sel, 
   bounce_ucb_sel, rd_nack_ucb_sel, ucb_buf_acpt, 

   rst_l, clk, tap_iob_packet_vld, pcx_packet, tap_packet, 
   c2i_packet_addr, cpu_buf_tail_f, io_buf_avail, jbi_ucb_buf_acpt, 
   clk_ucb_buf_acpt, dram0_ucb_buf_acpt, dram1_ucb_buf_acpt, 
   iob_man_ucb_buf_acpt, iob_int_ucb_buf_acpt, spi_ucb_buf_acpt, 
   bounce_ucb_buf_acpt, rd_nack_ucb_buf_acpt
   );

   




   input                              rst_l;
   input 			      clk;



   input 			      tap_iob_packet_vld;
   output 			      iob_tap_busy;
   


   input [`PCX_WIDTH-1:0] 	      pcx_packet;
   input [`UCB_64PAY_PKT_WIDTH-1:0]   tap_packet;
   output 			      cpu_buf_rd;
   output 			      tap_sel;
   output 			      cpu_packet_is_req;
   output [`UCB_PKT_WIDTH-1:0] 	      cpu_packet_type;
   
   input [`UCB_ADDR_WIDTH-1:0] 	      c2i_packet_addr;
   
   

   input [`IOB_CPU_BUF_INDEX:0]       cpu_buf_tail_f;
   output [`IOB_CPU_BUF_INDEX:0]      cpu_buf_head_s;



   input 			      io_buf_avail;
   output 			      srvc_wr_ack;

   

   output [`IOB_CPU_BUF_INDEX-1:0]    cpu_buf_head_ptr;
   output 			      cpu_buf_rd_l;
   


   output 			      c2i_packet_vld;
   output 			      c2i_packet_is_rd_req;
   output 			      c2i_packet_is_wr_req;
   
   output 			      jbi_ucb_sel;
   input 			      jbi_ucb_buf_acpt;
   
   output 			      clk_ucb_sel;
   input 			      clk_ucb_buf_acpt;

   output 			      dram0_ucb_sel;
   input 			      dram0_ucb_buf_acpt;

   output 			      dram1_ucb_sel;
   input 			      dram1_ucb_buf_acpt;

   output 			      iob_man_ucb_sel;
   input 			      iob_man_ucb_buf_acpt;
   
   output 			      iob_int_ucb_sel;
   input 			      iob_int_ucb_buf_acpt;
   
   output 			      spi_ucb_sel;
   input 			      spi_ucb_buf_acpt;

   output 			      bounce_ucb_sel;
   input 			      bounce_ucb_buf_acpt;
   
   output 			      rd_nack_ucb_sel;
   input 			      rd_nack_ucb_buf_acpt;

   

   output 			      ucb_buf_acpt;

   

   wire [`IOB_CPU_BUF_INDEX:0] 	      cpu_buf_head;
   wire [`IOB_CPU_BUF_INDEX:0] 	      cpu_buf_head_d1;
   wire [`IOB_CPU_BUF_INDEX:0] 	      cpu_buf_head_plus1;
   wire 			      cpu_buf_head_inc;
   wire [`IOB_CPU_BUF_INDEX:0] 	      cpu_buf_tail;
   wire 			      cpu_buf_empty;
   wire 			      cpu_buf_empty_d1;

   wire 			      cpu_vld;
   wire 			      cpu_vld_next;
   wire 			      tap_vld;
   wire 			      cpu_sel;
   
   reg 				      cpu_packet_is_rd_req;
   reg 				      cpu_packet_is_wr_req;
   reg 				      cpu_packet_is_if_req;
   reg 				      cpu_packet_is_ack;
   reg [`UCB_PKT_WIDTH-1:0] 	      cpu_packet_type;
   wire 			      cpu_packet_needs_wr_ack;
   wire 			      cpu_packet_is_8B;
   
   reg 				      tap_packet_is_rd_req;
   reg 				      tap_packet_is_wr_req;
   reg 				      tap_packet_is_ack;
   wire 			      tap_packet_is_8B;
   
   wire 			      c2i_packet_is_ack;
   wire 			      c2i_packet_is_if_req;
   wire 			      c2i_packet_is_8B;
   
   wire [`ADDR_MAP_HI-`ADDR_MAP_LO:0] c2i_packet_addr_msb;

   wire 			      mem_ucb_sel;
   wire 			      l2_ucb_sel;
   wire 			      tap_ucb_sel;
   wire 			      asi_ucb_sel;
   
   
   wire 			      no_match_ucb;
   
   wire 			      blackhole_acpt;
   
   





   dffrl_ns #(`IOB_CPU_BUF_INDEX+1) cpu_buf_head_d1_ff (.din(cpu_buf_head),
							.clk(clk),
							.rst_l(rst_l),
							.q(cpu_buf_head_d1));
   
   assign       cpu_buf_head_plus1 = cpu_buf_head_d1 + 5'b1;
   
   assign 	cpu_buf_head = cpu_buf_head_inc ? cpu_buf_head_plus1 :
	                                          cpu_buf_head_d1;
   
   assign 	cpu_buf_head_ptr = cpu_buf_head[`IOB_CPU_BUF_INDEX-1:0];
   
   assign 	cpu_buf_head_s = cpu_buf_head_d1;
   

   dffrl_ns #(`IOB_CPU_BUF_INDEX+1) cpu_buf_tail_ff (.din(cpu_buf_tail_f),
						     .clk(clk),
						     .rst_l(rst_l),
						     .q(cpu_buf_tail));


   assign 	cpu_buf_empty = (cpu_buf_head == cpu_buf_tail);

   assign 	cpu_buf_rd_l = cpu_buf_empty;
   
   dff_ns #(1) cpu_buf_empty_d1_ff (.din(cpu_buf_empty|~rst_l),
				    .clk(clk),
				    .q(cpu_buf_empty_d1));

   

   assign 	cpu_buf_rd = ~cpu_buf_empty_d1 &
	                     ((cpu_vld & cpu_sel & ucb_buf_acpt) |
	                      ~cpu_vld);

   assign 	cpu_buf_head_inc = cpu_buf_rd;

   


   assign 	cpu_vld_next = cpu_buf_rd |
	                       (cpu_vld & ~(cpu_sel & ucb_buf_acpt));
   
   dffrl_ns #(1) cpu_vld_ff (.din(cpu_vld_next),
			     .clk(clk),
			     .rst_l(rst_l),
			     .q(cpu_vld));

   assign 	tap_vld = tap_iob_packet_vld;

   

   assign 	tap_sel = tap_vld;
   assign 	cpu_sel = ~tap_vld;


   assign 	iob_tap_busy = tap_vld & ~ucb_buf_acpt;
   

   assign 	c2i_packet_vld = tap_vld |
	                         (cpu_vld &
				  ~(cpu_packet_needs_wr_ack & ~io_buf_avail));
   
   

   always @(pcx_packet) begin

      cpu_packet_is_rd_req = 1'b0;
      cpu_packet_is_wr_req = 1'b0;
      cpu_packet_is_if_req = 1'b0;
      cpu_packet_is_ack = 1'b0;
      cpu_packet_type = `UCB_PKT_WIDTH'bx;
      case (pcx_packet[`PCX_RQ_HI:`PCX_RQ_LO]) 
	`LOAD_RQ:begin
	   cpu_packet_is_rd_req = 1'b1;
	   cpu_packet_is_wr_req = 1'b0;
	   cpu_packet_is_if_req = 1'b0;
	   cpu_packet_is_ack = 1'b0;
	   cpu_packet_type = `UCB_READ_REQ;
	end
	`IMISS_RQ:begin
	   cpu_packet_is_rd_req = 1'b0;
	   cpu_packet_is_wr_req = 1'b0;
	   cpu_packet_is_if_req = 1'b1;
	   cpu_packet_is_ack = 1'b0;
	   cpu_packet_type = `UCB_IFILL_REQ;
	end
	`STORE_RQ:begin
	   cpu_packet_is_rd_req = 1'b0;
	   cpu_packet_is_wr_req = 1'b1;
	   cpu_packet_is_if_req = 1'b0;
	   cpu_packet_is_ack = 1'b0;
	   cpu_packet_type = `UCB_WRITE_REQ;
	end
	`FWD_RPY:begin
	   cpu_packet_is_rd_req = 1'b0;
	   cpu_packet_is_wr_req = 1'b0;
	   cpu_packet_is_if_req = 1'b0;
	   cpu_packet_is_ack = 1'b1;


	   cpu_packet_type = ~pcx_packet[`PCX_R]       ? `UCB_WRITE_ACK :
			     pcx_packet[`PCX_ERR_LO+1] ? `UCB_READ_NACK :
			                                 `UCB_READ_ACK;
	end
      endcase
   end

   assign       cpu_packet_is_req = cpu_packet_is_rd_req |
				    cpu_packet_is_wr_req |
				    cpu_packet_is_if_req;



   assign 	cpu_packet_needs_wr_ack = pcx_packet[`PCX_RQ_HI:`PCX_RQ_LO] == `STORE_RQ;
   
   assign 	cpu_packet_is_8B = pcx_packet[`PCX_SZ_HI:`PCX_SZ_LO] == `PCX_SZ_8B;
   
   

   always @(tap_packet) begin
      tap_packet_is_rd_req = 1'b0;
      tap_packet_is_wr_req = 1'b0;
      tap_packet_is_ack = 1'b0;
      case (tap_packet[`UCB_PKT_HI:`UCB_PKT_LO])
	`UCB_READ_REQ:begin
	   tap_packet_is_rd_req = 1'b1;
	   tap_packet_is_wr_req = 1'b0;
	   tap_packet_is_ack = 1'b0;
	end
	`UCB_WRITE_REQ:begin
	   tap_packet_is_rd_req = 1'b0;
	   tap_packet_is_wr_req = 1'b1;
	   tap_packet_is_ack = 1'b0;
	end
	`UCB_READ_NACK,
	`UCB_READ_ACK:begin
	   tap_packet_is_rd_req = 1'b0;
	   tap_packet_is_wr_req = 1'b0;
	   tap_packet_is_ack = 1'b1;
	end
      endcase
   end
   
   assign 	tap_packet_is_8B = tap_packet[`UCB_SIZE_HI:`UCB_SIZE_LO] == `UCB_SIZE_8B;
   
   

   assign 	c2i_packet_is_rd_req = tap_sel ? tap_packet_is_rd_req :
		                                 cpu_packet_is_rd_req;
   
   assign 	c2i_packet_is_wr_req = tap_sel ? tap_packet_is_wr_req :
		                                 cpu_packet_is_wr_req;
   
   assign 	c2i_packet_is_if_req = tap_sel ? 1'b0 :
		                                 cpu_packet_is_if_req;
   
   assign 	c2i_packet_is_ack = tap_sel ? tap_packet_is_ack :
		                              cpu_packet_is_ack;
   
   assign 	c2i_packet_is_8B = tap_sel ? tap_packet_is_8B :
		                             cpu_packet_is_8B;

   

   assign 	c2i_packet_addr_msb = c2i_packet_addr[`ADDR_MAP_HI:`ADDR_MAP_LO];
   assign 	mem_ucb_sel      = ((c2i_packet_addr_msb <= `DRAM_DATA_HI) &
				    (c2i_packet_addr_msb >= `DRAM_DATA_LO)) &
				     (c2i_packet_is_rd_req | c2i_packet_is_wr_req);
   assign 	l2_ucb_sel       = ((c2i_packet_addr_msb <= `L2C_CSR_HI) &
				    (c2i_packet_addr_msb >= `L2C_CSR_LO)) &
				     (c2i_packet_is_rd_req | c2i_packet_is_wr_req) &
		                     c2i_packet_is_8B;
   assign 	jbi_ucb_sel      = ((c2i_packet_addr_msb == `JBUS1) |
				    ((c2i_packet_addr_msb <= `JBUS2_HI) &
				     (c2i_packet_addr_msb >= `JBUS2_LO))) &
				     (c2i_packet_is_rd_req | c2i_packet_is_wr_req);
   
   assign 	clk_ucb_sel      = (c2i_packet_addr_msb == `CLOCK_UNIT_CSR) &
				     (c2i_packet_is_rd_req | c2i_packet_is_wr_req) &
		                     c2i_packet_is_8B;

   assign 	dram0_ucb_sel    = ((c2i_packet_addr_msb == `DRAM_CSR) &
				    (c2i_packet_addr[12] == 1'b0)) &
				     (c2i_packet_is_rd_req | c2i_packet_is_wr_req) &
		                     c2i_packet_is_8B;
   assign 	dram1_ucb_sel    = ((c2i_packet_addr_msb == `DRAM_CSR) &
				    (c2i_packet_addr[12] == 1'b1)) &
				     (c2i_packet_is_rd_req | c2i_packet_is_wr_req) &
		                     c2i_packet_is_8B;
   assign 	iob_man_ucb_sel  = (c2i_packet_addr_msb == `IOB_MAN_CSR) &
				     (c2i_packet_is_rd_req | c2i_packet_is_wr_req) &
		                     c2i_packet_is_8B;
   assign 	tap_ucb_sel      = (c2i_packet_addr_msb == `TAP_CSR) &
				     (c2i_packet_is_rd_req | c2i_packet_is_wr_req) &
		                     c2i_packet_is_8B;
   assign 	iob_int_ucb_sel  = (c2i_packet_addr_msb == `IOB_INT_CSR) &
				     (c2i_packet_is_rd_req | c2i_packet_is_wr_req) &
		                     c2i_packet_is_8B;
   
   assign 	asi_ucb_sel      = (c2i_packet_addr_msb == `CPU_ASI) &
				     (c2i_packet_is_rd_req | c2i_packet_is_wr_req) &
		                     c2i_packet_is_8B;
   
   assign 	spi_ucb_sel      = (c2i_packet_addr_msb == `SPI_CSR) &
				     (c2i_packet_is_rd_req |
				      c2i_packet_is_wr_req |
				      c2i_packet_is_if_req);



   assign     bounce_ucb_sel = mem_ucb_sel | l2_ucb_sel | tap_ucb_sel |	asi_ucb_sel | c2i_packet_is_ack;


   assign     no_match_ucb = ~(mem_ucb_sel |
			       l2_ucb_sel |
			       jbi_ucb_sel |
			       clk_ucb_sel |
			       dram0_ucb_sel |
			       dram1_ucb_sel |
			       iob_man_ucb_sel |
			       tap_ucb_sel |
			       iob_int_ucb_sel |
			       asi_ucb_sel |
			       spi_ucb_sel);


   assign     rd_nack_ucb_sel = no_match_ucb &
	                        (c2i_packet_is_rd_req | c2i_packet_is_if_req);
   


   assign     blackhole_acpt = c2i_packet_vld &
	                       ((~c2i_packet_is_rd_req &
				 ~c2i_packet_is_wr_req &
				 ~c2i_packet_is_if_req &
				 ~c2i_packet_is_ack) |
				(no_match_ucb & c2i_packet_is_wr_req));
   


   assign     ucb_buf_acpt = (jbi_ucb_buf_acpt |
			      clk_ucb_buf_acpt |
			      dram0_ucb_buf_acpt |
			      dram1_ucb_buf_acpt |
	                      iob_man_ucb_buf_acpt |
	                      iob_int_ucb_buf_acpt |
			      spi_ucb_buf_acpt |
			      bounce_ucb_buf_acpt |
			      rd_nack_ucb_buf_acpt |
			      blackhole_acpt);



   assign     srvc_wr_ack = cpu_sel & ucb_buf_acpt & cpu_packet_needs_wr_ack;

   
endmodule