data/full_repos/permissive/419538859/lab3/lab3_1self/sim/freq_div_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/419538859/lab3/lab3_1self/sim/freq_div_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n #(clkper / 2)  clk_in = ~clk_in;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab3/lab3_1self/sim/freq_div_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #20;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab3/lab3_1self/sim/freq_div_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #1980000;  \n ^\n%Error: data/full_repos/permissive/419538859/lab3/lab3_1self/sim/freq_div_tb.v:10: Cannot find file containing module: \'freq_div\'\nfreq_div freq_div_instance(.clk_in(clk_in),.reset(reset),.clk_out(clk_out));\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/419538859/lab3/lab3_1self/sim,data/full_repos/permissive/419538859/freq_div\n             data/full_repos/permissive/419538859/lab3/lab3_1self/sim,data/full_repos/permissive/419538859/freq_div.v\n             data/full_repos/permissive/419538859/lab3/lab3_1self/sim,data/full_repos/permissive/419538859/freq_div.sv\n             freq_div\n             freq_div.v\n             freq_div.sv\n             obj_dir/freq_div\n             obj_dir/freq_div.v\n             obj_dir/freq_div.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module 	testbench;

parameter	exp = 8;   
reg			clk_in, reset;
wire		clk_out;
wire		[exp-1:0] divider;

freq_div freq_div_instance(.clk_in(clk_in),.reset(reset),.clk_out(clk_out));


parameter	clkper = 5;

initial
begin
	clk_in = 1;
end

always 
begin
	#(clkper / 2)  clk_in = ~clk_in;
end

initial
begin
 reset	=1'b1;
 #20;		
 reset  =1'b0;
 #1980000;		
end
endmodule
module 	testbench;


parameter	exp = 8;   
reg			clk_in, reset;
wire		clk_out;
wire		[exp-1:0] divider;

freq_div freq_div_instance(.clk_in(clk_in),.reset(reset),.clk_out(clk_out));


parameter	clkper = 5;

initial
begin
	clk_in = 1;
end

always 
begin
	#(clkper / 2)  clk_in = ~clk_in;
end

initial
begin
 reset	=1'b1;
 #20;		
 reset  =1'b0;
 #1980000;		
end
endmodule