data/full_repos/permissive/460468583/data/yosys/xilinx/cells_map.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/460468583/data/yosys/xilinx/cells_map.v:27: Cell has missing pin: \'SO\'\n  \\$__XILINX_SHREG_ #(.DEPTH(DEPTH), .INIT(INIT), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(DEPTH-1), .E(E), .Q(Q));\n                                                                                  ^~~~~~~~~~~~~~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/460468583/data/yosys/xilinx/cells_map.v:73: Cell has missing pin: \'SO\'\n      \\$__XILINX_SHREG_ #(.DEPTH(DEPTH-32), .INIT(INIT[DEPTH-32-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T1), .L(L), .E(E), .Q(T2));\n                                                                                                       ^~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/460468583/data/yosys/xilinx/cells_map.v:83: Cell has missing pin: \'SO\'\n      \\$__XILINX_SHREG_ #(.DEPTH(DEPTH-64), .INIT(INIT[DEPTH-64-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_2 (.C(C), .D(T3), .L(L[4:0]), .E(E), .Q(T4));\n                                                                                                       ^~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/460468583/data/yosys/xilinx/cells_map.v:94: Cell has missing pin: \'SO\'\n      \\$__XILINX_SHREG_ #(.DEPTH(DEPTH-96), .INIT(INIT[DEPTH-96-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_3 (.C(C), .D(T5), .L(L[4:0]), .E(E), .Q(T6));\n                                                                                                       ^~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/460468583/data/yosys/xilinx/cells_map.v:114: Cell has missing pin: \'SO\'\n      \\$__XILINX_SHREG_ #(.DEPTH(DEPTH-1), .INIT(INIT[DEPTH-1:1]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl      (.C(C), .D(D), .L({32{1\'b1}}), .E(E), .Q(T));\n                                                                                                   ^~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/460468583/data/yosys/xilinx/cells_map.v:115: Cell has missing pin: \'SO\'\n      \\$__XILINX_SHREG_ #(.DEPTH(1),       .INIT(INIT[0]),         .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_last (.C(C), .D(T), .L(L), .E(E), .Q(Q));\n                                                                                                   ^~~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/460468583/data/yosys/xilinx/cells_map.v:119: Cell has missing pin: \'SO\'\n      \\$__XILINX_SHREG_ #(.DEPTH(DEPTH+1), .INIT({INIT,1\'b0}), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q));\n                                                                                               ^~~~~~~~~~~~~~~~~\n%Warning-PINMISSING: data/full_repos/permissive/460468583/data/yosys/xilinx/cells_map.v:132: Cell has missing pin: \'SO\'\n        \\$__XILINX_SHREG_ #(.DEPTH(depthN), .INIT(INIT[depthN-1:0]),               .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_last (.C(C), .D(S[num_srl128]), .L(L[$clog2(depth0)-1:0]), .E(E), .Q(T[num_srl128]));\n                                                                                                                   ^~~~~~~~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/460468583/data/yosys/xilinx/cells_map.v:23: Little bit endian vector: MSB < LSB of bit range: -1:0\n  parameter [DEPTH-1:0] INIT = 0;\n            ^\n%Warning-LITENDIAN: data/full_repos/permissive/460468583/data/yosys/xilinx/cells_map.v:32: Little bit endian vector: MSB < LSB of bit range: -1:0\n  parameter [DEPTH-1:0] INIT = 0;\n            ^\n%Warning-LITENDIAN: data/full_repos/permissive/460468583/data/yosys/xilinx/cells_map.v:46: Little bit endian vector: MSB < LSB of bit range: -1:0\n  localparam [DEPTH-1:0] INIT_R = brev(INIT);\n             ^\n%Warning-LITENDIAN: data/full_repos/permissive/460468583/data/yosys/xilinx/cells_map.v:38: Little bit endian vector: MSB < LSB of bit range: -1:0\n  function [DEPTH-1:0] brev;\n           ^\n%Warning-LITENDIAN: data/full_repos/permissive/460468583/data/yosys/xilinx/cells_map.v:39: Little bit endian vector: MSB < LSB of bit range: -1:0\n    input [DEPTH-1:0] din;\n          ^\n%Error: Internal Error: data/full_repos/permissive/460468583/data/yosys/xilinx/cells_map.v:38: ../V3Simulate.h:294: No value found for node.\n                                                                                             : ... In instance __024___05FSHREG_._TECHMAP_REPLACE_\n  function [DEPTH-1:0] brev;\n                       ^~~~\n'
function integer A_WIDTH_trimmed;
    input integer start;
  begin
    A_WIDTH_trimmed = start;
    while (A_WIDTH_trimmed > 0 && _TECHMAP_CONSTMSK_A_[A_WIDTH_trimmed-1] && _TECHMAP_CONSTVAL_A_[A_WIDTH_trimmed-1] === 1'bx)
      A_WIDTH_trimmed = A_WIDTH_trimmed - 1;
  end
  endfunction
function integer A_WIDTH_trimmed;

    input integer start;
  begin
    A_WIDTH_trimmed = start;
    while (A_WIDTH_trimmed > 0 && _TECHMAP_CONSTMSK_A_[A_WIDTH_trimmed-1] && _TECHMAP_CONSTVAL_A_[A_WIDTH_trimmed-1] === 1'bx)
      A_WIDTH_trimmed = A_WIDTH_trimmed - 1;
  end
  endfunction