data/full_repos/permissive/487082250/sources/showWin.v
1: b'%Error: data/full_repos/permissive/487082250/sources/showWin.v:15: Cannot find file containing module: \'number7seg\'\nnumber7seg nss(clk,nssin,nssout);\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/487082250/sources,data/full_repos/permissive/487082250/number7seg\n             data/full_repos/permissive/487082250/sources,data/full_repos/permissive/487082250/number7seg.v\n             data/full_repos/permissive/487082250/sources,data/full_repos/permissive/487082250/number7seg.sv\n             number7seg\n             number7seg.v\n             number7seg.sv\n             obj_dir/number7seg\n             obj_dir/number7seg.v\n             obj_dir/number7seg.sv\n%Warning-WIDTH: data/full_repos/permissive/487082250/sources/showWin.v:21: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h7\' generates 4 bits.\n                                                                         : ... In instance showWin\n  an = 4\'b0111;\n     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/487082250/sources/showWin.v:26: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'hb\' generates 4 bits.\n                                                                         : ... In instance showWin\n  an = 4\'b1011;\n     ^\n%Warning-WIDTH: data/full_repos/permissive/487082250/sources/showWin.v:31: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'hd\' generates 4 bits.\n                                                                         : ... In instance showWin\n    an = 4\'b1101;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/487082250/sources/showWin.v:34: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'hf\' generates 4 bits.\n                                                                         : ... In instance showWin\n    3: an = 4\'b1111;\n          ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n'
module showWin(
    input clk,
	input slclk,
	input [3:0] tmrs,
	input [3:0] tmrms,
	input [3:0] tmrmms,
	output [6:0] seg,
	output reg [4:0] an,
	output reg dp
);
reg [3:0] nssin;
wire [6:0] nssout;
number7seg nss(clk,nssin,nssout);
reg [1:0] counter = 0;
always @ (posedge slclk) begin
	case (counter)
	0: begin
		nssin = tmrs;
		an = 4'b0111;
		dp <= 0;
		end
	1: begin
		nssin = tmrms;
		an = 4'b1011;
		dp <= 1;
		end
	2: begin
	   nssin = tmrmms;
	   an = 4'b1101;
	   dp <= 1;
	   end
    3: an = 4'b1111;
	endcase
counter = counter + 1;
end
assign seg=nssout;
endmodule
module showWin(
    input clk,
	input slclk,
	input [3:0] tmrs,
	input [3:0] tmrms,
	input [3:0] tmrmms,
	output [6:0] seg,
	output reg [4:0] an,
	output reg dp
);

reg [3:0] nssin;
wire [6:0] nssout;
number7seg nss(clk,nssin,nssout);
reg [1:0] counter = 0;
always @ (posedge slclk) begin
	case (counter)
	0: begin
		nssin = tmrs;
		an = 4'b0111;
		dp <= 0;
		end
	1: begin
		nssin = tmrms;
		an = 4'b1011;
		dp <= 1;
		end
	2: begin
	   nssin = tmrmms;
	   an = 4'b1101;
	   dp <= 1;
	   end
    3: an = 4'b1111;
	endcase
counter = counter + 1;
end
assign seg=nssout;
endmodule