data/full_repos/permissive/42434302/ivltests/pr533.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr533.v:11: Unsupported: Ignoring delay on this delayed statement.\n        #100 r = 1\'bx; a = 5\'bxxxxx; b = 5\'bxxxxx;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr533.v:12: Unsupported: Ignoring delay on this delayed statement.\n        #100 r = 1\'b1; a = 5\'bxxxxx; b = 5\'bxxxxx;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr533.v:13: Unsupported: Ignoring delay on this delayed statement.\n        #100 r = 1\'b1; a = 5\'b00000; b = 5\'b00000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr533.v:14: Unsupported: Ignoring delay on this delayed statement.\n        #100 r = 1\'b0; a = 5\'b00000; b = 5\'b00000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr533.v:15: Unsupported: Ignoring delay on this delayed statement.\n        #100 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr533.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr533.v:22: Unsupported: Ignoring delay on this delayed statement.\n    initial #25 forever begin\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr533.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr533.v:30: Unsupported: Ignoring delay on this delayed statement.\n    initial #50 forever begin\n            ^\n%Warning-INFINITELOOP: data/full_repos/permissive/42434302/ivltests/pr533.v:22: Infinite loop (condition always true)\n                                                                              : ... In instance example\n    initial #25 forever begin\n                ^~~~~~~\n%Warning-INFINITELOOP: data/full_repos/permissive/42434302/ivltests/pr533.v:30: Infinite loop (condition always true)\n                                                                              : ... In instance example\n    initial #50 forever begin\n                ^~~~~~~\n%Error: Exiting due to 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module example;
    reg          r, c, e;
    reg   [4:0]  a, b;
    wire         d;

    assign d = ( r | ( a == b ) ) ? 1'b0 : 1'b1;



    initial begin
        #100 r = 1'bx; a = 5'bxxxxx; b = 5'bxxxxx;
        #100 r = 1'b1; a = 5'bxxxxx; b = 5'bxxxxx;
        #100 r = 1'b1; a = 5'b00000; b = 5'b00000;
        #100 r = 1'b0; a = 5'b00000; b = 5'b00000;
        #100 $finish;
    end





    initial #25 forever begin
        #100
        c = ( r | ( a == b ) ) ? 1'b0 : 1'b1;
        e = d;
    end



    initial #50 forever begin
        #100
        $display( "%b,%b,%b = ( %b | ( %b == %b ) ) ? 0 : 1",
                  c, d, e, r, a, b );
    end

endmodule
module example;

    reg          r, c, e;
    reg   [4:0]  a, b;
    wire         d;

    assign d = ( r | ( a == b ) ) ? 1'b0 : 1'b1;



    initial begin
        #100 r = 1'bx; a = 5'bxxxxx; b = 5'bxxxxx;
        #100 r = 1'b1; a = 5'bxxxxx; b = 5'bxxxxx;
        #100 r = 1'b1; a = 5'b00000; b = 5'b00000;
        #100 r = 1'b0; a = 5'b00000; b = 5'b00000;
        #100 $finish;
    end





    initial #25 forever begin
        #100
        c = ( r | ( a == b ) ) ? 1'b0 : 1'b1;
        e = d;
    end



    initial #50 forever begin
        #100
        $display( "%b,%b,%b = ( %b | ( %b == %b ) ) ? 0 : 1",
                  c, d, e, r, a, b );
    end

endmodule