data/full_repos/permissive/503509790/verilog/rtl/user_project_wrapper.v
1: b"%Error: data/full_repos/permissive/503509790/verilog/rtl/user_project_wrapper.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/503509790/verilog/rtl/user_project_wrapper.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/503509790/verilog/rtl/user_project_wrapper.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/503509790/verilog/rtl/user_project_wrapper.v:72: Define or directive not defined: '`MPRJ_IO_PADS'\n    inout [`MPRJ_IO_PADS-10:0] analog_io,\n           ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module user_project_wrapper #(
    parameter BITS = 32
) (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,





    inout [`MPRJ_IO_PADS-10:0] analog_io,


    input   user_clock2,


    output [2:0] user_irq
);

    assign io_oeb = sram_const_addr1;







    wire clk;
    wire rst;


    wire [1:0] program_sel;


    wire [10:0] gpio_in;
    wire [10:0] gpio_out;


    wire [7:0] dvsr;


    wire rx;
    wire tx;


    wire cm_done;
    wire ct_done;
    wire agent_1_done;



    assign clk              = wb_clk_i;
    assign rst              = io_in[8];


    assign program_sel      = io_in[10:9];


    assign gpio_in          = io_in[26:16];
    assign io_out[37:27]    = gpio_out;


    assign dvsr             = la_data_in[7:0];


    assign rx               = io_in[11];
    assign io_out[12]       = tx;


    assign io_out[13]       = cm_done;
    assign io_out[14]       = ct_done;
    assign io_out[15]       = agent_1_done;





    wire rst_asserted;


    wire agent_1_mem_ctrl_we;
    wire [13:0] agent_1_mem_ctrl_addr;
    wire [31:0] agent_1_mem_ctrl_in;
    wire [31:0] agent_1_mem_ctrl_out;
    wire agent_1_mem_ctrl_req;
    wire agent_1_mem_ctrl_vld;


    wire agent_1_sram0_csb0;
    wire agent_1_sram0_web0;
    wire [31:0] agent_1_sram0_dout0;

    wire agent_1_sram1_csb0;
    wire agent_1_sram1_web0;
    wire [31:0] agent_1_sram1_dout0;

    wire agent_1_sram2_csb0;
    wire agent_1_sram2_web0;
    wire [31:0] agent_1_sram2_dout0;

    wire agent_1_sram3_csb0;
    wire agent_1_sram3_web0;
    wire [31:0] agent_1_sram3_dout0;

    wire agent_1_sram4_csb0;
    wire agent_1_sram4_web0;
    wire [31:0] agent_1_sram4_dout0;

    wire [8:0] agent_1_sram_comm_addr0;
    wire [31:0] agent_1_sram_comm_din0;


    wire cm_mem_ctrl_we;
    wire [13:0] cm_mem_ctrl_addr;
    wire [31:0] cm_mem_ctrl_in;
    wire [31:0] cm_mem_ctrl_out;
    wire cm_mem_ctrl_req;
    wire cm_mem_ctrl_vld;


    wire cm_sram0_csb0;
    wire cm_sram0_web0;
    wire [31:0] cm_sram0_dout0;

    wire cm_sram1_csb0;
    wire cm_sram1_web0;
    wire [31:0] cm_sram1_dout0;

    wire cm_sram2_csb0;
    wire cm_sram2_web0;
    wire [31:0] cm_sram2_dout0;

    wire cm_sram3_csb0;
    wire cm_sram3_web0;
    wire [31:0] cm_sram3_dout0;

    wire cm_sram4_csb0;
    wire cm_sram4_web0;
    wire [31:0] cm_sram4_dout0;

    wire cm_sram5_csb0;
    wire cm_sram5_web0;
    wire [31:0] cm_sram5_dout0;

    wire [8:0] cm_sram_comm_addr0;
    wire [31:0] cm_sram_comm_din0;


    wire ct_mem_ctrl_we;
    wire [13:0] ct_mem_ctrl_addr;
    wire [31:0] ct_mem_ctrl_in;
    wire [31:0] ct_mem_ctrl_out;
    wire ct_mem_ctrl_req;
    wire ct_mem_ctrl_vld;


    wire ct_sram0_csb0;
    wire ct_sram0_web0;
    wire [31:0] ct_sram0_dout0;

    wire ct_sram1_csb0;
    wire ct_sram1_web0;
    wire [31:0] ct_sram1_dout0;

    wire ct_sram2_csb0;
    wire ct_sram2_web0;
    wire [31:0] ct_sram2_dout0;

    wire ct_sram3_csb0;
    wire ct_sram3_web0;
    wire [31:0] ct_sram3_dout0;

    wire ct_sram4_csb0;
    wire ct_sram4_web0;
    wire [31:0] ct_sram4_dout0;

    wire ct_sram5_csb0;
    wire ct_sram5_web0;
    wire [31:0] ct_sram5_dout0;

    wire ct_sram6_csb0;
    wire ct_sram6_web0;
    wire [31:0] ct_sram6_dout0;

    wire [8:0] ct_sram_comm_addr0;
    wire [31:0] ct_sram_comm_din0;


    wire [3:0] sram_const_wmask0;
    wire sram_const_csb1;
    wire [8:0] sram_const_addr1;


    wire main_mem_we;
    wire [5:0] main_mem_addr;
    wire [31:0] main_mem_in;
    wire [31:0] main_mem_out;


    wire rx_fifo_flush_enable;
    wire rd_uart;
    wire wr_uart;
    wire [7:0] w_data;
    wire tx_full;
    wire rx_empty;
    wire [7:0] r_data;


    VerySimpleCPU_core inst_codemaker(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif


        .clk(clk),
        .rst(rst_asserted),


        .mem_ctrl_we(cm_mem_ctrl_we),
        .mem_ctrl_addr(cm_mem_ctrl_addr),
        .mem_ctrl_in(cm_mem_ctrl_in),
        .mem_ctrl_out(cm_mem_ctrl_out),
        .mem_ctrl_vld(cm_mem_ctrl_vld),
        .mem_ctrl_req(cm_mem_ctrl_req),


        .done(cm_done)

    );


    VerySimpleCPU_core inst_control_tower(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif


        .clk(clk),
        .rst(rst_asserted),


        .mem_ctrl_we(ct_mem_ctrl_we),
        .mem_ctrl_addr(ct_mem_ctrl_addr),
        .mem_ctrl_in(ct_mem_ctrl_in),
        .mem_ctrl_out(ct_mem_ctrl_out),
        .mem_ctrl_vld(ct_mem_ctrl_vld),
        .mem_ctrl_req(ct_mem_ctrl_req),


        .done(ct_done)

    );


    VerySimpleCPU_core inst_agent_1(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif


        .clk(clk),
        .rst(rst_asserted),


        .mem_ctrl_we(agent_1_mem_ctrl_we),
        .mem_ctrl_addr(agent_1_mem_ctrl_addr),
        .mem_ctrl_in(agent_1_mem_ctrl_in),
        .mem_ctrl_out(agent_1_mem_ctrl_out),
        .mem_ctrl_req(agent_1_mem_ctrl_req),
        .mem_ctrl_vld(agent_1_mem_ctrl_vld),


        .done(agent_1_done)
    );

    main_controller inst_main_controller(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif


        .clk(clk),
        .rst(rst),
        .rst_asserted(rst_asserted),

        .program_sel(program_sel),


        .cm_mem_ctrl_we(cm_mem_ctrl_we),
        .cm_mem_ctrl_addr(cm_mem_ctrl_addr),
        .cm_mem_ctrl_in(cm_mem_ctrl_in),
        .cm_mem_ctrl_out(cm_mem_ctrl_out),
        .cm_mem_ctrl_vld(cm_mem_ctrl_vld),
        .cm_mem_ctrl_req(cm_mem_ctrl_req),


        .cm_sram0_csb0(cm_sram0_csb0),
        .cm_sram0_web0(cm_sram0_web0),
        .cm_sram0_dout0(cm_sram0_dout0),

        .cm_sram1_csb0(cm_sram1_csb0),
        .cm_sram1_web0(cm_sram1_web0),
        .cm_sram1_dout0(cm_sram1_dout0),

        .cm_sram2_csb0(cm_sram2_csb0),
        .cm_sram2_web0(cm_sram2_web0),
        .cm_sram2_dout0(cm_sram2_dout0),

        .cm_sram3_csb0(cm_sram3_csb0),
        .cm_sram3_web0(cm_sram3_web0),
        .cm_sram3_dout0(cm_sram3_dout0),



        .cm_sram_comm_addr0(cm_sram_comm_addr0),
        .cm_sram_comm_din0(cm_sram_comm_din0),


        .ct_mem_ctrl_we(ct_mem_ctrl_we),
        .ct_mem_ctrl_addr(ct_mem_ctrl_addr),
        .ct_mem_ctrl_in(ct_mem_ctrl_in),
        .ct_mem_ctrl_out(ct_mem_ctrl_out),
        .ct_mem_ctrl_vld(ct_mem_ctrl_vld),
        .ct_mem_ctrl_req(ct_mem_ctrl_req),


        .ct_sram0_csb0(ct_sram0_csb0),
        .ct_sram0_web0(ct_sram0_web0),
        .ct_sram0_dout0(ct_sram0_dout0),

        .ct_sram1_csb0(ct_sram1_csb0),
        .ct_sram1_web0(ct_sram1_web0),
        .ct_sram1_dout0(ct_sram1_dout0),

        .ct_sram2_csb0(ct_sram2_csb0),
        .ct_sram2_web0(ct_sram2_web0),
        .ct_sram2_dout0(ct_sram2_dout0),

        .ct_sram3_csb0(ct_sram3_csb0),
        .ct_sram3_web0(ct_sram3_web0),
        .ct_sram3_dout0(ct_sram3_dout0),

        .ct_sram4_csb0(ct_sram4_csb0),
        .ct_sram4_web0(ct_sram4_web0),
        .ct_sram4_dout0(ct_sram4_dout0),



        .ct_sram_comm_addr0(ct_sram_comm_addr0),
        .ct_sram_comm_din0(ct_sram_comm_din0),


        .agent_1_mem_ctrl_we(agent_1_mem_ctrl_we),
        .agent_1_mem_ctrl_addr(agent_1_mem_ctrl_addr),
        .agent_1_mem_ctrl_in(agent_1_mem_ctrl_in),
        .agent_1_mem_ctrl_out(agent_1_mem_ctrl_out),
        .agent_1_mem_ctrl_vld(agent_1_mem_ctrl_vld),
        .agent_1_mem_ctrl_req(agent_1_mem_ctrl_req),


        .agent_1_sram0_csb0(agent_1_sram0_csb0),
        .agent_1_sram0_web0(agent_1_sram0_web0),
        .agent_1_sram0_dout0(agent_1_sram0_dout0),

        .agent_1_sram1_csb0(agent_1_sram1_csb0),
        .agent_1_sram1_web0(agent_1_sram1_web0),
        .agent_1_sram1_dout0(agent_1_sram1_dout0),

        .agent_1_sram2_csb0(agent_1_sram2_csb0),
        .agent_1_sram2_web0(agent_1_sram2_web0),
        .agent_1_sram2_dout0(agent_1_sram2_dout0),



        .agent_1_sram_comm_addr0(agent_1_sram_comm_addr0),
        .agent_1_sram_comm_din0(agent_1_sram_comm_din0),


        .sram_const_wmask0(sram_const_wmask0),
        .sram_const_csb1(sram_const_csb1),
        .sram_const_addr1(sram_const_addr1),


        .main_mem_we(main_mem_we),
        .main_mem_addr(main_mem_addr),
        .main_mem_in(main_mem_in),
        .main_mem_out(main_mem_out),


        .rx_fifo_flush_enable(rx_fifo_flush_enable),
        .rd_uart(rd_uart),
        .wr_uart(wr_uart),
        .w_data(w_data),
        .tx_full(tx_full),
        .rx_empty(rx_empty),
        .r_data(r_data)

        );


    sky130_sram_2kbyte_1rw1r_32x512_8 codemaker_sram2k_inst0(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif

         .clk0(clk),
         .csb0(cm_sram0_csb0),
         .web0(cm_sram0_web0),
         .wmask0(sram_const_wmask0),
         .addr0(cm_sram_comm_addr0),
         .din0(cm_sram_comm_din0),
         .dout0(cm_sram0_dout0),
         .clk1(clk),
         .csb1(sram_const_csb1),
         .addr1(sram_const_addr1),
         .dout1()
        );

    sky130_sram_2kbyte_1rw1r_32x512_8 codemaker_sram2k_inst1(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif

         .clk0(clk),
         .csb0(cm_sram1_csb0),
         .web0(cm_sram1_web0),
         .wmask0(sram_const_wmask0),
         .addr0(cm_sram_comm_addr0),
         .din0(cm_sram_comm_din0),
         .dout0(cm_sram1_dout0),
         .clk1(clk),
         .csb1(sram_const_csb1),
         .addr1(sram_const_addr1),
         .dout1()
        );

    sky130_sram_2kbyte_1rw1r_32x512_8 codemaker_sram2k_inst2(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif

         .clk0(clk),
         .csb0(cm_sram2_csb0),
         .web0(cm_sram2_web0),
         .wmask0(sram_const_wmask0),
         .addr0(cm_sram_comm_addr0),
         .din0(cm_sram_comm_din0),
         .dout0(cm_sram2_dout0),
         .clk1(clk),
         .csb1(sram_const_csb1),
         .addr1(sram_const_addr1),
         .dout1()
        );

    sky130_sram_2kbyte_1rw1r_32x512_8 codemaker_sram2k_inst3(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif

         .clk0(clk),
         .csb0(cm_sram3_csb0),
         .web0(cm_sram3_web0),
         .wmask0(sram_const_wmask0),
         .addr0(cm_sram_comm_addr0),
         .din0(cm_sram_comm_din0),
         .dout0(cm_sram3_dout0),
         .clk1(clk),
         .csb1(sram_const_csb1),
         .addr1(sram_const_addr1),
         .dout1()
        );




    sky130_sram_2kbyte_1rw1r_32x512_8 control_tower_sram2k_inst0(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif

         .clk0(clk),
         .csb0(ct_sram0_csb0),
         .web0(ct_sram0_web0),
         .wmask0(sram_const_wmask0),
         .addr0(ct_sram_comm_addr0),
         .din0(ct_sram_comm_din0),
         .dout0(ct_sram0_dout0),
         .clk1(clk),
         .csb1(sram_const_csb1),
         .addr1(sram_const_addr1),
         .dout1()
        );

    sky130_sram_2kbyte_1rw1r_32x512_8 control_tower_sram2k_inst1(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif

         .clk0(clk),
         .csb0(ct_sram1_csb0),
         .web0(ct_sram1_web0),
         .wmask0(sram_const_wmask0),
         .addr0(ct_sram_comm_addr0),
         .din0(ct_sram_comm_din0),
         .dout0(ct_sram1_dout0),
         .clk1(clk),
         .csb1(sram_const_csb1),
         .addr1(sram_const_addr1),
         .dout1()
        );

    sky130_sram_2kbyte_1rw1r_32x512_8 control_tower_sram2k_inst2(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif

         .clk0(clk),
         .csb0(ct_sram2_csb0),
         .web0(ct_sram2_web0),
         .wmask0(sram_const_wmask0),
         .addr0(ct_sram_comm_addr0),
         .din0(ct_sram_comm_din0),
         .dout0(ct_sram2_dout0),
         .clk1(clk),
         .csb1(sram_const_csb1),
         .addr1(sram_const_addr1),
         .dout1()
        );

    sky130_sram_2kbyte_1rw1r_32x512_8 control_tower_sram2k_inst3(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif

         .clk0(clk),
         .csb0(ct_sram3_csb0),
         .web0(ct_sram3_web0),
         .wmask0(sram_const_wmask0),
         .addr0(ct_sram_comm_addr0),
         .din0(ct_sram_comm_din0),
         .dout0(ct_sram3_dout0),
         .clk1(clk),
         .csb1(sram_const_csb1),
         .addr1(sram_const_addr1),
         .dout1()
        );

    sky130_sram_2kbyte_1rw1r_32x512_8 control_tower_sram2k_inst4(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif

         .clk0(clk),
         .csb0(ct_sram4_csb0),
         .web0(ct_sram4_web0),
         .wmask0(sram_const_wmask0),
         .addr0(ct_sram_comm_addr0),
         .din0(ct_sram_comm_din0),
         .dout0(ct_sram4_dout0),
         .clk1(clk),
         .csb1(sram_const_csb1),
         .addr1(sram_const_addr1),
         .dout1()
        );




    sky130_sram_2kbyte_1rw1r_32x512_8 agent_1_sram2k_inst0(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif

         .clk0(clk),
         .csb0(agent_1_sram0_csb0),
         .web0(agent_1_sram0_web0),
         .wmask0(sram_const_wmask0),
         .addr0(agent_1_sram_comm_addr0),
         .din0(agent_1_sram_comm_din0),
         .dout0(agent_1_sram0_dout0),
         .clk1(clk),
         .csb1(sram_const_csb1),
         .addr1(sram_const_addr1),
         .dout1()
        );

    sky130_sram_2kbyte_1rw1r_32x512_8 agent_1_sram2k_inst1(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif

         .clk0(clk),
         .csb0(agent_1_sram1_csb0),
         .web0(agent_1_sram1_web0),
         .wmask0(sram_const_wmask0),
         .addr0(agent_1_sram_comm_addr0),
         .din0(agent_1_sram_comm_din0),
         .dout0(agent_1_sram1_dout0),
         .clk1(clk),
         .csb1(sram_const_csb1),
         .addr1(sram_const_addr1),
         .dout1()
        );

    sky130_sram_2kbyte_1rw1r_32x512_8 agent_1_sram2k_inst2(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif

         .clk0(clk),
         .csb0(agent_1_sram2_csb0),
         .web0(agent_1_sram2_web0),
         .wmask0(sram_const_wmask0),
         .addr0(agent_1_sram_comm_addr0),
         .din0(agent_1_sram_comm_din0),
         .dout0(agent_1_sram2_dout0),
         .clk1(clk),
         .csb1(sram_const_csb1),
         .addr1(sram_const_addr1),
         .dout1()
        );




    main_memory inst_main_memory(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif

        .clk(clk),
        .wea(main_mem_we),
        .addra(main_mem_addr),
        .dina(main_mem_in),
        .douta(main_mem_out),
        .gpio_in(gpio_in),
        .gpio_out(gpio_out)

    );


    uart inst_uart(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif

        .clk(clk),
        .reset(rst_asserted),
        .dvsr(dvsr),
        .rx_fifo_flush_enable(rx_fifo_flush_enable),
        .rd_uart(rd_uart),
        .wr_uart(wr_uart),
        .rx(rx),
        .w_data(w_data),
        .tx_full(tx_full),
        .rx_empty(rx_empty),
        .tx(tx),
        .r_data(r_data)

    );

endmodule
module user_project_wrapper #(
    parameter BITS = 32
) (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,





    inout [`MPRJ_IO_PADS-10:0] analog_io,


    input   user_clock2,


    output [2:0] user_irq
);


    assign io_oeb = sram_const_addr1;







    wire clk;
    wire rst;


    wire [1:0] program_sel;


    wire [10:0] gpio_in;
    wire [10:0] gpio_out;


    wire [7:0] dvsr;


    wire rx;
    wire tx;


    wire cm_done;
    wire ct_done;
    wire agent_1_done;



    assign clk              = wb_clk_i;
    assign rst              = io_in[8];


    assign program_sel      = io_in[10:9];


    assign gpio_in          = io_in[26:16];
    assign io_out[37:27]    = gpio_out;


    assign dvsr             = la_data_in[7:0];


    assign rx               = io_in[11];
    assign io_out[12]       = tx;


    assign io_out[13]       = cm_done;
    assign io_out[14]       = ct_done;
    assign io_out[15]       = agent_1_done;





    wire rst_asserted;


    wire agent_1_mem_ctrl_we;
    wire [13:0] agent_1_mem_ctrl_addr;
    wire [31:0] agent_1_mem_ctrl_in;
    wire [31:0] agent_1_mem_ctrl_out;
    wire agent_1_mem_ctrl_req;
    wire agent_1_mem_ctrl_vld;


    wire agent_1_sram0_csb0;
    wire agent_1_sram0_web0;
    wire [31:0] agent_1_sram0_dout0;

    wire agent_1_sram1_csb0;
    wire agent_1_sram1_web0;
    wire [31:0] agent_1_sram1_dout0;

    wire agent_1_sram2_csb0;
    wire agent_1_sram2_web0;
    wire [31:0] agent_1_sram2_dout0;

    wire agent_1_sram3_csb0;
    wire agent_1_sram3_web0;
    wire [31:0] agent_1_sram3_dout0;

    wire agent_1_sram4_csb0;
    wire agent_1_sram4_web0;
    wire [31:0] agent_1_sram4_dout0;

    wire [8:0] agent_1_sram_comm_addr0;
    wire [31:0] agent_1_sram_comm_din0;


    wire cm_mem_ctrl_we;
    wire [13:0] cm_mem_ctrl_addr;
    wire [31:0] cm_mem_ctrl_in;
    wire [31:0] cm_mem_ctrl_out;
    wire cm_mem_ctrl_req;
    wire cm_mem_ctrl_vld;


    wire cm_sram0_csb0;
    wire cm_sram0_web0;
    wire [31:0] cm_sram0_dout0;

    wire cm_sram1_csb0;
    wire cm_sram1_web0;
    wire [31:0] cm_sram1_dout0;

    wire cm_sram2_csb0;
    wire cm_sram2_web0;
    wire [31:0] cm_sram2_dout0;

    wire cm_sram3_csb0;
    wire cm_sram3_web0;
    wire [31:0] cm_sram3_dout0;

    wire cm_sram4_csb0;
    wire cm_sram4_web0;
    wire [31:0] cm_sram4_dout0;

    wire cm_sram5_csb0;
    wire cm_sram5_web0;
    wire [31:0] cm_sram5_dout0;

    wire [8:0] cm_sram_comm_addr0;
    wire [31:0] cm_sram_comm_din0;


    wire ct_mem_ctrl_we;
    wire [13:0] ct_mem_ctrl_addr;
    wire [31:0] ct_mem_ctrl_in;
    wire [31:0] ct_mem_ctrl_out;
    wire ct_mem_ctrl_req;
    wire ct_mem_ctrl_vld;


    wire ct_sram0_csb0;
    wire ct_sram0_web0;
    wire [31:0] ct_sram0_dout0;

    wire ct_sram1_csb0;
    wire ct_sram1_web0;
    wire [31:0] ct_sram1_dout0;

    wire ct_sram2_csb0;
    wire ct_sram2_web0;
    wire [31:0] ct_sram2_dout0;

    wire ct_sram3_csb0;
    wire ct_sram3_web0;
    wire [31:0] ct_sram3_dout0;

    wire ct_sram4_csb0;
    wire ct_sram4_web0;
    wire [31:0] ct_sram4_dout0;

    wire ct_sram5_csb0;
    wire ct_sram5_web0;
    wire [31:0] ct_sram5_dout0;

    wire ct_sram6_csb0;
    wire ct_sram6_web0;
    wire [31:0] ct_sram6_dout0;

    wire [8:0] ct_sram_comm_addr0;
    wire [31:0] ct_sram_comm_din0;


    wire [3:0] sram_const_wmask0;
    wire sram_const_csb1;
    wire [8:0] sram_const_addr1;


    wire main_mem_we;
    wire [5:0] main_mem_addr;
    wire [31:0] main_mem_in;
    wire [31:0] main_mem_out;


    wire rx_fifo_flush_enable;
    wire rd_uart;
    wire wr_uart;
    wire [7:0] w_data;
    wire tx_full;
    wire rx_empty;
    wire [7:0] r_data;


    VerySimpleCPU_core inst_codemaker(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif


        .clk(clk),
        .rst(rst_asserted),


        .mem_ctrl_we(cm_mem_ctrl_we),
        .mem_ctrl_addr(cm_mem_ctrl_addr),
        .mem_ctrl_in(cm_mem_ctrl_in),
        .mem_ctrl_out(cm_mem_ctrl_out),
        .mem_ctrl_vld(cm_mem_ctrl_vld),
        .mem_ctrl_req(cm_mem_ctrl_req),


        .done(cm_done)

    );


    VerySimpleCPU_core inst_control_tower(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif


        .clk(clk),
        .rst(rst_asserted),


        .mem_ctrl_we(ct_mem_ctrl_we),
        .mem_ctrl_addr(ct_mem_ctrl_addr),
        .mem_ctrl_in(ct_mem_ctrl_in),
        .mem_ctrl_out(ct_mem_ctrl_out),
        .mem_ctrl_vld(ct_mem_ctrl_vld),
        .mem_ctrl_req(ct_mem_ctrl_req),


        .done(ct_done)

    );


    VerySimpleCPU_core inst_agent_1(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif


        .clk(clk),
        .rst(rst_asserted),


        .mem_ctrl_we(agent_1_mem_ctrl_we),
        .mem_ctrl_addr(agent_1_mem_ctrl_addr),
        .mem_ctrl_in(agent_1_mem_ctrl_in),
        .mem_ctrl_out(agent_1_mem_ctrl_out),
        .mem_ctrl_req(agent_1_mem_ctrl_req),
        .mem_ctrl_vld(agent_1_mem_ctrl_vld),


        .done(agent_1_done)
    );

    main_controller inst_main_controller(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif


        .clk(clk),
        .rst(rst),
        .rst_asserted(rst_asserted),

        .program_sel(program_sel),


        .cm_mem_ctrl_we(cm_mem_ctrl_we),
        .cm_mem_ctrl_addr(cm_mem_ctrl_addr),
        .cm_mem_ctrl_in(cm_mem_ctrl_in),
        .cm_mem_ctrl_out(cm_mem_ctrl_out),
        .cm_mem_ctrl_vld(cm_mem_ctrl_vld),
        .cm_mem_ctrl_req(cm_mem_ctrl_req),


        .cm_sram0_csb0(cm_sram0_csb0),
        .cm_sram0_web0(cm_sram0_web0),
        .cm_sram0_dout0(cm_sram0_dout0),

        .cm_sram1_csb0(cm_sram1_csb0),
        .cm_sram1_web0(cm_sram1_web0),
        .cm_sram1_dout0(cm_sram1_dout0),

        .cm_sram2_csb0(cm_sram2_csb0),
        .cm_sram2_web0(cm_sram2_web0),
        .cm_sram2_dout0(cm_sram2_dout0),

        .cm_sram3_csb0(cm_sram3_csb0),
        .cm_sram3_web0(cm_sram3_web0),
        .cm_sram3_dout0(cm_sram3_dout0),



        .cm_sram_comm_addr0(cm_sram_comm_addr0),
        .cm_sram_comm_din0(cm_sram_comm_din0),


        .ct_mem_ctrl_we(ct_mem_ctrl_we),
        .ct_mem_ctrl_addr(ct_mem_ctrl_addr),
        .ct_mem_ctrl_in(ct_mem_ctrl_in),
        .ct_mem_ctrl_out(ct_mem_ctrl_out),
        .ct_mem_ctrl_vld(ct_mem_ctrl_vld),
        .ct_mem_ctrl_req(ct_mem_ctrl_req),


        .ct_sram0_csb0(ct_sram0_csb0),
        .ct_sram0_web0(ct_sram0_web0),
        .ct_sram0_dout0(ct_sram0_dout0),

        .ct_sram1_csb0(ct_sram1_csb0),
        .ct_sram1_web0(ct_sram1_web0),
        .ct_sram1_dout0(ct_sram1_dout0),

        .ct_sram2_csb0(ct_sram2_csb0),
        .ct_sram2_web0(ct_sram2_web0),
        .ct_sram2_dout0(ct_sram2_dout0),

        .ct_sram3_csb0(ct_sram3_csb0),
        .ct_sram3_web0(ct_sram3_web0),
        .ct_sram3_dout0(ct_sram3_dout0),

        .ct_sram4_csb0(ct_sram4_csb0),
        .ct_sram4_web0(ct_sram4_web0),
        .ct_sram4_dout0(ct_sram4_dout0),



        .ct_sram_comm_addr0(ct_sram_comm_addr0),
        .ct_sram_comm_din0(ct_sram_comm_din0),


        .agent_1_mem_ctrl_we(agent_1_mem_ctrl_we),
        .agent_1_mem_ctrl_addr(agent_1_mem_ctrl_addr),
        .agent_1_mem_ctrl_in(agent_1_mem_ctrl_in),
        .agent_1_mem_ctrl_out(agent_1_mem_ctrl_out),
        .agent_1_mem_ctrl_vld(agent_1_mem_ctrl_vld),
        .agent_1_mem_ctrl_req(agent_1_mem_ctrl_req),


        .agent_1_sram0_csb0(agent_1_sram0_csb0),
        .agent_1_sram0_web0(agent_1_sram0_web0),
        .agent_1_sram0_dout0(agent_1_sram0_dout0),

        .agent_1_sram1_csb0(agent_1_sram1_csb0),
        .agent_1_sram1_web0(agent_1_sram1_web0),
        .agent_1_sram1_dout0(agent_1_sram1_dout0),

        .agent_1_sram2_csb0(agent_1_sram2_csb0),
        .agent_1_sram2_web0(agent_1_sram2_web0),
        .agent_1_sram2_dout0(agent_1_sram2_dout0),



        .agent_1_sram_comm_addr0(agent_1_sram_comm_addr0),
        .agent_1_sram_comm_din0(agent_1_sram_comm_din0),


        .sram_const_wmask0(sram_const_wmask0),
        .sram_const_csb1(sram_const_csb1),
        .sram_const_addr1(sram_const_addr1),


        .main_mem_we(main_mem_we),
        .main_mem_addr(main_mem_addr),
        .main_mem_in(main_mem_in),
        .main_mem_out(main_mem_out),


        .rx_fifo_flush_enable(rx_fifo_flush_enable),
        .rd_uart(rd_uart),
        .wr_uart(wr_uart),
        .w_data(w_data),
        .tx_full(tx_full),
        .rx_empty(rx_empty),
        .r_data(r_data)

        );


    sky130_sram_2kbyte_1rw1r_32x512_8 codemaker_sram2k_inst0(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif

         .clk0(clk),
         .csb0(cm_sram0_csb0),
         .web0(cm_sram0_web0),
         .wmask0(sram_const_wmask0),
         .addr0(cm_sram_comm_addr0),
         .din0(cm_sram_comm_din0),
         .dout0(cm_sram0_dout0),
         .clk1(clk),
         .csb1(sram_const_csb1),
         .addr1(sram_const_addr1),
         .dout1()
        );

    sky130_sram_2kbyte_1rw1r_32x512_8 codemaker_sram2k_inst1(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif

         .clk0(clk),
         .csb0(cm_sram1_csb0),
         .web0(cm_sram1_web0),
         .wmask0(sram_const_wmask0),
         .addr0(cm_sram_comm_addr0),
         .din0(cm_sram_comm_din0),
         .dout0(cm_sram1_dout0),
         .clk1(clk),
         .csb1(sram_const_csb1),
         .addr1(sram_const_addr1),
         .dout1()
        );

    sky130_sram_2kbyte_1rw1r_32x512_8 codemaker_sram2k_inst2(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif

         .clk0(clk),
         .csb0(cm_sram2_csb0),
         .web0(cm_sram2_web0),
         .wmask0(sram_const_wmask0),
         .addr0(cm_sram_comm_addr0),
         .din0(cm_sram_comm_din0),
         .dout0(cm_sram2_dout0),
         .clk1(clk),
         .csb1(sram_const_csb1),
         .addr1(sram_const_addr1),
         .dout1()
        );

    sky130_sram_2kbyte_1rw1r_32x512_8 codemaker_sram2k_inst3(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif

         .clk0(clk),
         .csb0(cm_sram3_csb0),
         .web0(cm_sram3_web0),
         .wmask0(sram_const_wmask0),
         .addr0(cm_sram_comm_addr0),
         .din0(cm_sram_comm_din0),
         .dout0(cm_sram3_dout0),
         .clk1(clk),
         .csb1(sram_const_csb1),
         .addr1(sram_const_addr1),
         .dout1()
        );




    sky130_sram_2kbyte_1rw1r_32x512_8 control_tower_sram2k_inst0(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif

         .clk0(clk),
         .csb0(ct_sram0_csb0),
         .web0(ct_sram0_web0),
         .wmask0(sram_const_wmask0),
         .addr0(ct_sram_comm_addr0),
         .din0(ct_sram_comm_din0),
         .dout0(ct_sram0_dout0),
         .clk1(clk),
         .csb1(sram_const_csb1),
         .addr1(sram_const_addr1),
         .dout1()
        );

    sky130_sram_2kbyte_1rw1r_32x512_8 control_tower_sram2k_inst1(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif

         .clk0(clk),
         .csb0(ct_sram1_csb0),
         .web0(ct_sram1_web0),
         .wmask0(sram_const_wmask0),
         .addr0(ct_sram_comm_addr0),
         .din0(ct_sram_comm_din0),
         .dout0(ct_sram1_dout0),
         .clk1(clk),
         .csb1(sram_const_csb1),
         .addr1(sram_const_addr1),
         .dout1()
        );

    sky130_sram_2kbyte_1rw1r_32x512_8 control_tower_sram2k_inst2(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif

         .clk0(clk),
         .csb0(ct_sram2_csb0),
         .web0(ct_sram2_web0),
         .wmask0(sram_const_wmask0),
         .addr0(ct_sram_comm_addr0),
         .din0(ct_sram_comm_din0),
         .dout0(ct_sram2_dout0),
         .clk1(clk),
         .csb1(sram_const_csb1),
         .addr1(sram_const_addr1),
         .dout1()
        );

    sky130_sram_2kbyte_1rw1r_32x512_8 control_tower_sram2k_inst3(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif

         .clk0(clk),
         .csb0(ct_sram3_csb0),
         .web0(ct_sram3_web0),
         .wmask0(sram_const_wmask0),
         .addr0(ct_sram_comm_addr0),
         .din0(ct_sram_comm_din0),
         .dout0(ct_sram3_dout0),
         .clk1(clk),
         .csb1(sram_const_csb1),
         .addr1(sram_const_addr1),
         .dout1()
        );

    sky130_sram_2kbyte_1rw1r_32x512_8 control_tower_sram2k_inst4(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif

         .clk0(clk),
         .csb0(ct_sram4_csb0),
         .web0(ct_sram4_web0),
         .wmask0(sram_const_wmask0),
         .addr0(ct_sram_comm_addr0),
         .din0(ct_sram_comm_din0),
         .dout0(ct_sram4_dout0),
         .clk1(clk),
         .csb1(sram_const_csb1),
         .addr1(sram_const_addr1),
         .dout1()
        );




    sky130_sram_2kbyte_1rw1r_32x512_8 agent_1_sram2k_inst0(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif

         .clk0(clk),
         .csb0(agent_1_sram0_csb0),
         .web0(agent_1_sram0_web0),
         .wmask0(sram_const_wmask0),
         .addr0(agent_1_sram_comm_addr0),
         .din0(agent_1_sram_comm_din0),
         .dout0(agent_1_sram0_dout0),
         .clk1(clk),
         .csb1(sram_const_csb1),
         .addr1(sram_const_addr1),
         .dout1()
        );

    sky130_sram_2kbyte_1rw1r_32x512_8 agent_1_sram2k_inst1(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif

         .clk0(clk),
         .csb0(agent_1_sram1_csb0),
         .web0(agent_1_sram1_web0),
         .wmask0(sram_const_wmask0),
         .addr0(agent_1_sram_comm_addr0),
         .din0(agent_1_sram_comm_din0),
         .dout0(agent_1_sram1_dout0),
         .clk1(clk),
         .csb1(sram_const_csb1),
         .addr1(sram_const_addr1),
         .dout1()
        );

    sky130_sram_2kbyte_1rw1r_32x512_8 agent_1_sram2k_inst2(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif

         .clk0(clk),
         .csb0(agent_1_sram2_csb0),
         .web0(agent_1_sram2_web0),
         .wmask0(sram_const_wmask0),
         .addr0(agent_1_sram_comm_addr0),
         .din0(agent_1_sram_comm_din0),
         .dout0(agent_1_sram2_dout0),
         .clk1(clk),
         .csb1(sram_const_csb1),
         .addr1(sram_const_addr1),
         .dout1()
        );




    main_memory inst_main_memory(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif

        .clk(clk),
        .wea(main_mem_we),
        .addra(main_mem_addr),
        .dina(main_mem_in),
        .douta(main_mem_out),
        .gpio_in(gpio_in),
        .gpio_out(gpio_out)

    );


    uart inst_uart(
        `ifdef USE_POWER_PINS
            .vccd1(vccd1),
            .vssd1(vssd1),
        `endif

        .clk(clk),
        .reset(rst_asserted),
        .dvsr(dvsr),
        .rx_fifo_flush_enable(rx_fifo_flush_enable),
        .rd_uart(rd_uart),
        .wr_uart(wr_uart),
        .rx(rx),
        .w_data(w_data),
        .tx_full(tx_full),
        .rx_empty(rx_empty),
        .tx(tx),
        .r_data(r_data)

    );

endmodule