data/full_repos/permissive/447976230/fpga/usrp1/models/fifo_4k.v
1: b"%Error: data/full_repos/permissive/447976230/fpga/usrp1/models/fifo_4k.v:19: Cannot find file containing module: 'fifo'\nfifo #(.width(16),.depth(4096),.addr_bits(12)) fifo_4k \n^~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp1/models,data/full_repos/permissive/447976230/fifo\n             data/full_repos/permissive/447976230/fpga/usrp1/models,data/full_repos/permissive/447976230/fifo.v\n             data/full_repos/permissive/447976230/fpga/usrp1/models,data/full_repos/permissive/447976230/fifo.sv\n             fifo\n             fifo.v\n             fifo.sv\n             obj_dir/fifo\n             obj_dir/fifo.v\n             obj_dir/fifo.sv\n%Error: Exiting due to 1 error(s)\n"
module fifo_4k
  (  input [15:0] data,
     input 	wrreq,
     input 	rdreq,
     input 	rdclk,
     input 	wrclk,
     input 	aclr,
     output [15:0] q,
     output 	 rdfull,
     output 	 rdempty,
     output [11:0] rdusedw,
     output 	 wrfull,
     output 	 wrempty,
     output [11:0]  wrusedw
     );

fifo #(.width(16),.depth(4096),.addr_bits(12)) fifo_4k 
  ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
    rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
   
endmodule
module fifo_4k
  (  input [15:0] data,
     input 	wrreq,
     input 	rdreq,
     input 	rdclk,
     input 	wrclk,
     input 	aclr,
     output [15:0] q,
     output 	 rdfull,
     output 	 rdempty,
     output [11:0] rdusedw,
     output 	 wrfull,
     output 	 wrempty,
     output [11:0]  wrusedw
     );


fifo #(.width(16),.depth(4096),.addr_bits(12)) fifo_4k 
  ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
    rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
   
endmodule