data/full_repos/permissive/487568919/generic_systemverilog_designs_library/full_subtractor/full_subtractor.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/487568919/generic_systemverilog_designs_library/full_subtractor/full_subtractor.sv:9: Operator SUB expects 5 bits on the RHS, but RHS\'s VARREF \'borrow_in\' generates 1 bits.\n                                                                                                                               : ... In instance full_subtractor\nassign {borrow_out, result} = a - b - borrow_in;\n                                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module full_subtractor
  #(parameter WIDTH = 4)
  (input logic [WIDTH - 1: 0] a, 
                              b, 
   input logic borrow_in,
   output logic borrow_out,
   output logic [WIDTH - 1: 0] result);

assign {borrow_out, result} = a - b - borrow_in;

endmodule
module full_subtractor
  #(parameter WIDTH = 4)
  (input logic [WIDTH - 1: 0] a, 
                              b, 
   input logic borrow_in,
   output logic borrow_out,
   output logic [WIDTH - 1: 0] result);


assign {borrow_out, result} = a - b - borrow_in;

endmodule