data/full_repos/permissive/441359809/test/main_test/simple_cases/set_64_1/set_64_1.v
data/verilator_xmls/b5f13668-100a-466a-bc8d-44596b22d603.xml
module set_64_1 (input [6-1:0] sel, input [64-1:0] din, output reg [64-1:0] dout);
  always @* begin dout = din; dout = dout |  (1 << sel); end
endmodule
module set_64_1 (input [6-1:0] sel, input [64-1:0] din, output reg [64-1:0] dout);

  always @* begin dout = din; dout = dout |  (1 << sel); end
endmodule