data/full_repos/permissive/423547971/FPGA Projects/Seven Segment Clock Basys 3(segs on breadboard)/seg_demux.v
1: b'%Error: Cannot find file containing module: Projects/Seven\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/Seven\n             data/full_repos/permissive/423547971/FPGA/Projects/Seven.v\n             data/full_repos/permissive/423547971/FPGA/Projects/Seven.sv\n             Projects/Seven\n             Projects/Seven.v\n             Projects/Seven.sv\n             obj_dir/Projects/Seven\n             obj_dir/Projects/Seven.v\n             obj_dir/Projects/Seven.sv\n%Error: Cannot find file containing module: Segment\n%Error: Cannot find file containing module: Clock\n%Error: Cannot find file containing module: Basys\n%Error: Cannot find file containing module: 3(segs\n%Error: Cannot find file containing module: on\n%Error: Cannot find file containing module: breadboard),data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: breadboard)/seg_demux.v\n%Error: Exiting due to 9 error(s)\n'
module seg_demux(
    input [6:0] mux_in,
    input [1:0] select,
    output reg [6:0] out0,
    output reg [6:0] out1,
    output reg [6:0] out2,
    output reg [6:0] out3
    );
    
    always @(select) begin
        case(select)
            2'b00:  begin
                    out0 = mux_in;
                    out1 = 7'b000_0000;
                    out2 = 7'b000_0000;
                    out3 = 7'b000_0000;
                    end
            2'b01:  begin
                    out0 = 7'b000_0000;
                    out1 = mux_in;
                    out2 = 7'b000_0000;
                    out3 = 7'b000_0000;
                    end
            2'b10:  begin
                    out0 = 7'b000_0000;
                    out1 = 7'b000_0000;
                    out2 = mux_in;
                    out3 = 7'b000_0000;
                    end
            2'b11:  begin
                    out0 = 7'b000_0000;
                    out1 = 7'b000_0000;
                    out2 = 7'b000_0000;
                    out3 = mux_in;
                    end
        endcase
    end 
endmodule
module seg_demux(
    input [6:0] mux_in,
    input [1:0] select,
    output reg [6:0] out0,
    output reg [6:0] out1,
    output reg [6:0] out2,
    output reg [6:0] out3
    );

    
    always @(select) begin
        case(select)
            2'b00:  begin
                    out0 = mux_in;
                    out1 = 7'b000_0000;
                    out2 = 7'b000_0000;
                    out3 = 7'b000_0000;
                    end
            2'b01:  begin
                    out0 = 7'b000_0000;
                    out1 = mux_in;
                    out2 = 7'b000_0000;
                    out3 = 7'b000_0000;
                    end
            2'b10:  begin
                    out0 = 7'b000_0000;
                    out1 = 7'b000_0000;
                    out2 = mux_in;
                    out3 = 7'b000_0000;
                    end
            2'b11:  begin
                    out0 = 7'b000_0000;
                    out1 = 7'b000_0000;
                    out2 = 7'b000_0000;
                    out3 = mux_in;
                    end
        endcase
    end 
endmodule