data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v
1: b'%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:10: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:19: Define or directive not defined: \'`XLEN\'\n  input  [`XLEN-1:0] alu_i_rs1,\n          ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:20: Define or directive not defined: \'`XLEN\'\n  input  [`XLEN-1:0] alu_i_rs2,\n          ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:21: Define or directive not defined: \'`XLEN\'\n  input  [`XLEN-1:0] alu_i_imm,\n          ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:22: Define or directive not defined: \'`PC_SIZE\'\n  input  [`PC_SIZE-1:0] alu_i_pc,\n          ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:23: Define or directive not defined: \'`DECINFO_ALU_WIDTH\'\n  input  [`DECINFO_ALU_WIDTH-1:0] alu_i_info,  \n          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:31: Define or directive not defined: \'`XLEN\'\n  output [`XLEN-1:0] alu_o_wbck_wdat,\n          ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:47: Define or directive not defined: \'`XLEN\'\n  output [`XLEN-1:0] alu_req_alu_op1,\n          ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:48: Define or directive not defined: \'`XLEN\'\n  output [`XLEN-1:0] alu_req_alu_op2,\n          ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:50: Define or directive not defined: \'`XLEN\'\n  input  [`XLEN-1:0] alu_req_alu_res,\n          ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:55: Define or directive not defined: \'`DECINFO_ALU_OP2IMM\'\n  wire op2imm  = alu_i_info [`DECINFO_ALU_OP2IMM];                   \n                             ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:55: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire op2imm  = alu_i_info [`DECINFO_ALU_OP2IMM];                   \n                                                ^\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:56: Define or directive not defined: \'`DECINFO_ALU_OP1PC\'\n  wire op1pc   = alu_i_info [`DECINFO_ALU_OP1PC ];                   \n                             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:56: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire op1pc   = alu_i_info [`DECINFO_ALU_OP1PC ];                   \n                                                ^\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:61: Define or directive not defined: \'`DECINFO_ALU_NOP\'\n  wire nop    = alu_i_info [`DECINFO_ALU_NOP ] ;                      \n                            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:61: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire nop    = alu_i_info [`DECINFO_ALU_NOP ] ;                      \n                                             ^\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:65: Define or directive not defined: \'`DECINFO_ALU_ADD\'\n  assign alu_req_alu_add  = alu_i_info [`DECINFO_ALU_ADD ] & (~nop);  \n                                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:65: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  assign alu_req_alu_add  = alu_i_info [`DECINFO_ALU_ADD ] & (~nop);  \n                                                         ^\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:66: Define or directive not defined: \'`DECINFO_ALU_SUB\'\n  assign alu_req_alu_sub  = alu_i_info [`DECINFO_ALU_SUB ];           \n                                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:66: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  assign alu_req_alu_sub  = alu_i_info [`DECINFO_ALU_SUB ];           \n                                                         ^\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:67: Define or directive not defined: \'`DECINFO_ALU_SLT\'\n  assign alu_req_alu_slt  = alu_i_info [`DECINFO_ALU_SLT ];           \n                                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:67: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  assign alu_req_alu_slt  = alu_i_info [`DECINFO_ALU_SLT ];           \n                                                         ^\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:68: Define or directive not defined: \'`DECINFO_ALU_SLTU\'\n  assign alu_req_alu_sltu = alu_i_info [`DECINFO_ALU_SLTU];           \n                                        ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:68: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  assign alu_req_alu_sltu = alu_i_info [`DECINFO_ALU_SLTU];           \n                                                         ^\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:69: Define or directive not defined: \'`DECINFO_ALU_XOR\'\n  assign alu_req_alu_xor  = alu_i_info [`DECINFO_ALU_XOR ];           \n                                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:69: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  assign alu_req_alu_xor  = alu_i_info [`DECINFO_ALU_XOR ];           \n                                                         ^\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:70: Define or directive not defined: \'`DECINFO_ALU_OR\'\n  assign alu_req_alu_or   = alu_i_info [`DECINFO_ALU_OR  ];           \n                                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:70: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  assign alu_req_alu_or   = alu_i_info [`DECINFO_ALU_OR  ];           \n                                                         ^\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:71: Define or directive not defined: \'`DECINFO_ALU_AND\'\n  assign alu_req_alu_and  = alu_i_info [`DECINFO_ALU_AND ];           \n                                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:71: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  assign alu_req_alu_and  = alu_i_info [`DECINFO_ALU_AND ];           \n                                                         ^\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:72: Define or directive not defined: \'`DECINFO_ALU_SLL\'\n  assign alu_req_alu_sll  = alu_i_info [`DECINFO_ALU_SLL ];           \n                                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:72: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  assign alu_req_alu_sll  = alu_i_info [`DECINFO_ALU_SLL ];           \n                                                         ^\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:73: Define or directive not defined: \'`DECINFO_ALU_SRL\'\n  assign alu_req_alu_srl  = alu_i_info [`DECINFO_ALU_SRL ];           \n                                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:73: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  assign alu_req_alu_srl  = alu_i_info [`DECINFO_ALU_SRL ];           \n                                                         ^\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:74: Define or directive not defined: \'`DECINFO_ALU_SRA\'\n  assign alu_req_alu_sra  = alu_i_info [`DECINFO_ALU_SRA ];           \n                                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:74: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  assign alu_req_alu_sra  = alu_i_info [`DECINFO_ALU_SRA ];           \n                                                         ^\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:75: Define or directive not defined: \'`DECINFO_ALU_LUI\'\n  assign alu_req_alu_lui  = alu_i_info [`DECINFO_ALU_LUI ];           \n                                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_alu_rglr.v:75: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  assign alu_req_alu_lui  = alu_i_info [`DECINFO_ALU_LUI ];           \n                                                         ^\n%Error: Exiting due to 38 error(s)\n'
module exu_alu_rglr(



  input  alu_i_valid,
  output alu_i_ready,

  input  [`XLEN-1:0] alu_i_rs1,
  input  [`XLEN-1:0] alu_i_rs2,
  input  [`XLEN-1:0] alu_i_imm,
  input  [`PC_SIZE-1:0] alu_i_pc,
  input  [`DECINFO_ALU_WIDTH-1:0] alu_i_info,



  output alu_o_valid,
  input  alu_o_ready,


  output [`XLEN-1:0] alu_o_wbck_wdat,




  output alu_req_alu_add ,
  output alu_req_alu_sub ,
  output alu_req_alu_xor ,
  output alu_req_alu_sll ,
  output alu_req_alu_srl ,
  output alu_req_alu_sra ,
  output alu_req_alu_or  ,
  output alu_req_alu_and ,
  output alu_req_alu_slt ,
  output alu_req_alu_sltu,
  output alu_req_alu_lui ,
  output [`XLEN-1:0] alu_req_alu_op1,
  output [`XLEN-1:0] alu_req_alu_op2,

  input  [`XLEN-1:0] alu_req_alu_res,
  input  clk,
  input  rst_n
  );

  wire op2imm  = alu_i_info [`DECINFO_ALU_OP2IMM];
  wire op1pc   = alu_i_info [`DECINFO_ALU_OP1PC ];

  assign alu_req_alu_op1  = op1pc  ? alu_i_pc  : alu_i_rs1;
  assign alu_req_alu_op2  = op2imm ? alu_i_imm : alu_i_rs2;  

  wire nop    = alu_i_info [`DECINFO_ALU_NOP ] ;



  assign alu_req_alu_add  = alu_i_info [`DECINFO_ALU_ADD ] & (~nop);
  assign alu_req_alu_sub  = alu_i_info [`DECINFO_ALU_SUB ];
  assign alu_req_alu_slt  = alu_i_info [`DECINFO_ALU_SLT ];
  assign alu_req_alu_sltu = alu_i_info [`DECINFO_ALU_SLTU];
  assign alu_req_alu_xor  = alu_i_info [`DECINFO_ALU_XOR ];
  assign alu_req_alu_or   = alu_i_info [`DECINFO_ALU_OR  ];
  assign alu_req_alu_and  = alu_i_info [`DECINFO_ALU_AND ];
  assign alu_req_alu_sll  = alu_i_info [`DECINFO_ALU_SLL ];
  assign alu_req_alu_srl  = alu_i_info [`DECINFO_ALU_SRL ];
  assign alu_req_alu_sra  = alu_i_info [`DECINFO_ALU_SRA ];
  assign alu_req_alu_lui  = alu_i_info [`DECINFO_ALU_LUI ];

  assign alu_o_valid = alu_i_valid;
  assign alu_i_ready = alu_o_ready;


  assign alu_o_wbck_wdat = alu_req_alu_res;
   
endmodule
module exu_alu_rglr(



  input  alu_i_valid,
  output alu_i_ready,

  input  [`XLEN-1:0] alu_i_rs1,
  input  [`XLEN-1:0] alu_i_rs2,
  input  [`XLEN-1:0] alu_i_imm,
  input  [`PC_SIZE-1:0] alu_i_pc,
  input  [`DECINFO_ALU_WIDTH-1:0] alu_i_info,



  output alu_o_valid,
  input  alu_o_ready,


  output [`XLEN-1:0] alu_o_wbck_wdat,




  output alu_req_alu_add ,
  output alu_req_alu_sub ,
  output alu_req_alu_xor ,
  output alu_req_alu_sll ,
  output alu_req_alu_srl ,
  output alu_req_alu_sra ,
  output alu_req_alu_or  ,
  output alu_req_alu_and ,
  output alu_req_alu_slt ,
  output alu_req_alu_sltu,
  output alu_req_alu_lui ,
  output [`XLEN-1:0] alu_req_alu_op1,
  output [`XLEN-1:0] alu_req_alu_op2,

  input  [`XLEN-1:0] alu_req_alu_res,
  input  clk,
  input  rst_n
  );


  wire op2imm  = alu_i_info [`DECINFO_ALU_OP2IMM];
  wire op1pc   = alu_i_info [`DECINFO_ALU_OP1PC ];

  assign alu_req_alu_op1  = op1pc  ? alu_i_pc  : alu_i_rs1;
  assign alu_req_alu_op2  = op2imm ? alu_i_imm : alu_i_rs2;  

  wire nop    = alu_i_info [`DECINFO_ALU_NOP ] ;



  assign alu_req_alu_add  = alu_i_info [`DECINFO_ALU_ADD ] & (~nop);
  assign alu_req_alu_sub  = alu_i_info [`DECINFO_ALU_SUB ];
  assign alu_req_alu_slt  = alu_i_info [`DECINFO_ALU_SLT ];
  assign alu_req_alu_sltu = alu_i_info [`DECINFO_ALU_SLTU];
  assign alu_req_alu_xor  = alu_i_info [`DECINFO_ALU_XOR ];
  assign alu_req_alu_or   = alu_i_info [`DECINFO_ALU_OR  ];
  assign alu_req_alu_and  = alu_i_info [`DECINFO_ALU_AND ];
  assign alu_req_alu_sll  = alu_i_info [`DECINFO_ALU_SLL ];
  assign alu_req_alu_srl  = alu_i_info [`DECINFO_ALU_SRL ];
  assign alu_req_alu_sra  = alu_i_info [`DECINFO_ALU_SRA ];
  assign alu_req_alu_lui  = alu_i_info [`DECINFO_ALU_LUI ];

  assign alu_o_valid = alu_i_valid;
  assign alu_i_ready = alu_o_ready;


  assign alu_o_wbck_wdat = alu_req_alu_res;
   
endmodule