data/full_repos/permissive/52881156/fpga_files/quartus_proj/DE0_CAMERA_MOUSE/music/top.v
1: b"%Error: data/full_repos/permissive/52881156/fpga_files/quartus_proj/DE0_CAMERA_MOUSE/music/top.v:35: Cannot find file containing module: 'clk_div'\n clk_div  GEN_10K (CLOCK_50, 21'd2499, clk_10k);    \n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52881156/fpga_files/quartus_proj/DE0_CAMERA_MOUSE/music,data/full_repos/permissive/52881156/clk_div\n             data/full_repos/permissive/52881156/fpga_files/quartus_proj/DE0_CAMERA_MOUSE/music,data/full_repos/permissive/52881156/clk_div.v\n             data/full_repos/permissive/52881156/fpga_files/quartus_proj/DE0_CAMERA_MOUSE/music,data/full_repos/permissive/52881156/clk_div.sv\n             clk_div\n             clk_div.v\n             clk_div.sv\n             obj_dir/clk_div\n             obj_dir/clk_div.v\n             obj_dir/clk_div.sv\n%Error: data/full_repos/permissive/52881156/fpga_files/quartus_proj/DE0_CAMERA_MOUSE/music/top.v:36: Cannot find file containing module: 'pulse_gen'\n pulse_gen  PULSE (ld_pulse, clk_10k, CLOCK_50);   \n ^~~~~~~~~\n%Error: data/full_repos/permissive/52881156/fpga_files/quartus_proj/DE0_CAMERA_MOUSE/music/top.v:38: Cannot find file containing module: 'spi2dac'\n spi2dac SPI_DAC (CLOCK_50, data_out, ld_pulse,    \n ^~~~~~~\n%Error: data/full_repos/permissive/52881156/fpga_files/quartus_proj/DE0_CAMERA_MOUSE/music/top.v:41: Cannot find file containing module: 'spi2adc'\n spi2adc SPI_ADC (             \n ^~~~~~~\n%Error: data/full_repos/permissive/52881156/fpga_files/quartus_proj/DE0_CAMERA_MOUSE/music/top.v:52: Cannot find file containing module: 'processor'\n processor DUMMY (CLOCK_50, data_in, data_valid, data_out,volume);  \n ^~~~~~~~~\n%Error: data/full_repos/permissive/52881156/fpga_files/quartus_proj/DE0_CAMERA_MOUSE/music/top.v:56: Cannot find file containing module: 'hex_to_7seg'\n hex_to_7seg SEG0 (HEX0_D, volume[3:0]);     \n ^~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n"
module top (CLOCK_50, SW, HEX0_D, volume,
					DAC_SDI, SCK, DAC_CS, DAC_LD,
					ADC_SDI, ADC_CS, ADC_SDO);

	input			CLOCK_50;
	input	SW;
	output [6:0] HEX0_D;


	output 		DAC_SDI;
	output 		SCK;
	output		DAC_CS;
	output 		DAC_LD;
	output 		ADC_SDI;
	output		ADC_CS;
	input 		ADC_SDO;
		
	wire			ld_pulse;
	wire			clk_10k;
	wire [9:0] 	data_in;
	wire [9:0] 	data_out;
	wire			data_valid;
	wire			DAC_SCK, ADC_SCK, SCK;
	
	input [3:0]		   volume;
	
	clk_div  GEN_10K (CLOCK_50, 21'd2499, clk_10k);
	pulse_gen  PULSE (ld_pulse, clk_10k, CLOCK_50);

	spi2dac SPI_DAC (CLOCK_50, data_out, ld_pulse,
					DAC_SDI, DAC_CS, DAC_SCK, DAC_LD);
					
	spi2adc SPI_ADC (
		.sysclk (CLOCK_50),
		.channel (SW), 
		.start (ld_pulse),
		.data_from_adc (data_in),
		.data_valid (data_valid),
		.sdata_to_adc (ADC_SDI),
		.adc_cs (ADC_CS),
		.adc_sck (ADC_SCK),
		.sdata_from_adc (ADC_SDO));		
					
	processor	DUMMY (CLOCK_50, data_in, data_valid, data_out,volume);
	
	assign SCK = DAC_SCK | ADC_SCK;
	
	hex_to_7seg SEG0 (HEX0_D, volume[3:0]);
		
endmodule
module top (CLOCK_50, SW, HEX0_D, volume,
					DAC_SDI, SCK, DAC_CS, DAC_LD,
					ADC_SDI, ADC_CS, ADC_SDO);


	input			CLOCK_50;
	input	SW;
	output [6:0] HEX0_D;


	output 		DAC_SDI;
	output 		SCK;
	output		DAC_CS;
	output 		DAC_LD;
	output 		ADC_SDI;
	output		ADC_CS;
	input 		ADC_SDO;
		
	wire			ld_pulse;
	wire			clk_10k;
	wire [9:0] 	data_in;
	wire [9:0] 	data_out;
	wire			data_valid;
	wire			DAC_SCK, ADC_SCK, SCK;
	
	input [3:0]		   volume;
	
	clk_div  GEN_10K (CLOCK_50, 21'd2499, clk_10k);
	pulse_gen  PULSE (ld_pulse, clk_10k, CLOCK_50);

	spi2dac SPI_DAC (CLOCK_50, data_out, ld_pulse,
					DAC_SDI, DAC_CS, DAC_SCK, DAC_LD);
					
	spi2adc SPI_ADC (
		.sysclk (CLOCK_50),
		.channel (SW), 
		.start (ld_pulse),
		.data_from_adc (data_in),
		.data_valid (data_valid),
		.sdata_to_adc (ADC_SDI),
		.adc_cs (ADC_CS),
		.adc_sck (ADC_SCK),
		.sdata_from_adc (ADC_SDO));		
					
	processor	DUMMY (CLOCK_50, data_in, data_valid, data_out,volume);
	
	assign SCK = DAC_SCK | ADC_SCK;
	
	hex_to_7seg SEG0 (HEX0_D, volume[3:0]);
		
endmodule