data/full_repos/permissive/414867793/Universal_Gates/Not_Gate/NOT_G.v
data/verilator_xmls/d8e81e95-4d35-410b-ae6b-d3f1530bd66d.xml
module NOT_G(A,B);
input A;
output B;
assign B=~A;


endmodule
module NOT_G(A,B);

input A;
output B;
assign B=~A;


endmodule