data/full_repos/permissive/52881156/fpga_files/catapult_proj/Background Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1/cycle_mgc_ioport.v
1: b'%Error: Cannot find file containing module: Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156\n        ... Looked in:\n             data/full_repos/permissive/52881156/fpga_files/catapult_proj/Background/Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156\n             data/full_repos/permissive/52881156/fpga_files/catapult_proj/Background/Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156.v\n             data/full_repos/permissive/52881156/fpga_files/catapult_proj/Background/Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156.sv\n             Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156\n             Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156.v\n             Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156.sv\n             obj_dir/Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156\n             obj_dir/Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156.v\n             obj_dir/Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/52881156/fpga_files/catapult_proj/Background\n%Error: Cannot find file containing module: Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1/cycle_mgc_ioport.v\n%Error: Exiting due to 3 error(s)\n'
module funccall_inout (d, ad, bd, z, az, bz);

  parameter integer ram_id = 1;
  parameter integer width = 8;
  parameter integer addr_width = 8;

  output [width-1:0]       d;
  input  [addr_width-1:0]  ad;
  input                    bd;
  input  [width-1:0]       z;
  output [addr_width-1:0]  az;
  output                   bz;

  wire   [width-1:0]       d;
  wire   [addr_width-1:0]  az;
  wire                     bz;

  assign d  = z;
  assign az = ad;
  assign bz = bd;

endmodule
module funccall_inout (d, ad, bd, z, az, bz);


  parameter integer ram_id = 1;
  parameter integer width = 8;
  parameter integer addr_width = 8;

  output [width-1:0]       d;
  input  [addr_width-1:0]  ad;
  input                    bd;
  input  [width-1:0]       z;
  output [addr_width-1:0]  az;
  output                   bz;

  wire   [width-1:0]       d;
  wire   [addr_width-1:0]  az;
  wire                     bz;

  assign d  = z;
  assign az = ad;
  assign bz = bd;

endmodule