data/full_repos/permissive/515598112/2_Verilog_Language/05_More_Verilog_Features/05_Combinational_fo-loop_255_bit_population_count.v
1: b'%Warning-WIDTH: data/full_repos/permissive/515598112/2_Verilog_Language/05_More_Verilog_Features/05_Combinational_fo-loop_255_bit_population_count.v:9: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                                                                      : ... In instance top_module\n            out = out + in[i];\n                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module top_module ( 
    input [254:0] in,
    output reg [7:0] out
);
    
    always @(*) begin
        out = 8'b00000000;
        for (integer i = 0; i < $bits(in); i = i + 1) begin
            out = out + in[i];
        end
    end

endmodule
module top_module ( 
    input [254:0] in,
    output reg [7:0] out
);

    
    always @(*) begin
        out = 8'b00000000;
        for (integer i = 0; i < $bits(in); i = i + 1) begin
            out = out + in[i];
        end
    end

endmodule