data/full_repos/permissive/514992586/1_Verilog_language/More_Verilog_Features/37_Condition.v
data/verilator_xmls/a7c81617-8691-44a6-9ec0-b3e35ee212fc.xml
module top_module (
    input [7:0] a, b, c, d,
    output [7:0] min);


    wire [7:0] w1;
    wire [7:0] w2;
    assign w1 = a < b ? a : b;
    assign w2 = c < d ? c : d;
    assign min = w1 < w2 ? w1 : w2;
endmodule
module top_module (
    input [7:0] a, b, c, d,
    output [7:0] min);



    wire [7:0] w1;
    wire [7:0] w2;
    assign w1 = a < b ? a : b;
    assign w2 = c < d ? c : d;
    assign min = w1 < w2 ? w1 : w2;
endmodule