data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/main.v
1: b"%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/main.v:71: syntax error, unexpected output, expecting ')' or ','\nmodule nor5 (input wire i0, i1, i2, i3, i4 output wire o);\n                                           ^~~~~~\n%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/main.v:73: syntax error, unexpected IDENTIFIER\n   or2 or2_0 (i0, i1, t0);\n   ^~~\n%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/main.v:387: syntax error, unexpected IDENTIFIER, expecting ',' or ';'\n pc_inc = load_ir\n ^~~~~~\n%Error: Cannot continue\n"
module mux2_4 (input wire [3:0] i0, i1, input wire j, output wire [3:0] o);
  mux2 mux2_0 (i0[0], i1[0], j, o[0]);
  mux2 mux2_1 (i0[1], i1[1], j, o[1]);
  mux2 mux2_2 (i0[2], i1[2], j, o[2]);
  mux2 mux2_3 (i0[3], i1[3], j, o[3]);
endmodule
module mux2_4 (input wire [3:0] i0, i1, input wire j, output wire [3:0] o);

  mux2 mux2_0 (i0[0], i1[0], j, o[0]);
  mux2 mux2_1 (i0[1], i1[1], j, o[1]);
  mux2 mux2_2 (i0[2], i1[2], j, o[2]);
  mux2 mux2_3 (i0[3], i1[3], j, o[3]);
endmodule