data/full_repos/permissive/494664634/AxisFifoRead/src/sim/AxisFifoRead_tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/494664634/AxisFifoRead/src/sim/AxisFifoRead_tb.sv:25: Unsupported: Ignoring delay on this delayed statement.\nalways #5ns aclk = ~aclk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/494664634/AxisFifoRead/src/sim/AxisFifoRead_tb.sv:31: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport axi4stream_vip_pkg::*;\n       ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/494664634/AxisFifoRead/src/sim/AxisFifoRead_tb.sv:38: Unsupported: fork statements\n    fork\n    ^~~~\n%Error: data/full_repos/permissive/494664634/AxisFifoRead/src/sim/AxisFifoRead_tb.sv:45: syntax error, unexpected IDENTIFIER\n    design_1_axi4stream_vip_0_0_mst_t driver_agent;\n                                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/494664634/AxisFifoRead/src/sim/AxisFifoRead_tb.sv:47: Unsupported: new with arguments\n    driver_agent = new("driver vip agent", DUT.design_1_i.axi4stream_vip_0.inst.IF);\n                   ^~~\n%Error: data/full_repos/permissive/494664634/AxisFifoRead/src/sim/AxisFifoRead_tb.sv:56: Unsupported: wait statements\n    wait (aresetn == 1);\n    ^~~~\n%Error: data/full_repos/permissive/494664634/AxisFifoRead/src/sim/AxisFifoRead_tb.sv:61: syntax error, unexpected \'@\'\n        if (i%4 == 3 && i != 15) repeat(50) @(negedge aclk);\n                                            ^\n%Error: data/full_repos/permissive/494664634/AxisFifoRead/src/sim/AxisFifoRead_tb.sv:68: syntax error, unexpected IDENTIFIER\n    design_1_axi_vip_0_0_mst_t receiver_agent;\n                               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/494664634/AxisFifoRead/src/sim/AxisFifoRead_tb.sv:70: Unsupported: new with arguments\n    receiver_agent = new("receiver vip agent", DUT.design_1_i.axi_vip_0.inst.IF);\n                     ^~~\n%Error: data/full_repos/permissive/494664634/AxisFifoRead/src/sim/AxisFifoRead_tb.sv:75: syntax error, unexpected \'@\'\n     repeat(5) @(negedge aclk);\n               ^\n%Error: data/full_repos/permissive/494664634/AxisFifoRead/src/sim/AxisFifoRead_tb.sv:93: syntax error, unexpected \'@\'\n    repeat(5) @(negedge aclk);\n              ^\n%Error: Exiting due to 10 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module AxisFifoRead_tb();
bit aclk = 0, aresetn = 0;
always #5ns aclk = ~aclk;
design_1_wrapper DUT(.*);

test t1(.*);
endmodule
module AxisFifoRead_tb();

bit aclk = 0, aresetn = 0;
always #5ns aclk = ~aclk;
design_1_wrapper DUT(.*);

test t1(.*);
endmodule