data/full_repos/permissive/486812922/src/mips_test.v
1: b'%Error: data/full_repos/permissive/486812922/src/mips_test.v:10: Unsupported or unknown PLI call: $monitor\n    $monitor("PC=%8X,Instr=%8X", U_MIPS.PC, U_MIPS.Instr);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/486812922/src/mips_test.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #5;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/486812922/src/mips_test.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486812922/src/mips_test.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #(50) clk = ~clk;\n    ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mips_test();
reg clk, rst;
mips U_MIPS(
         .clk(clk),
         .reset(rst)
     );

initial begin
    $monitor("PC=%8X,Instr=%8X", U_MIPS.PC, U_MIPS.Instr);
    clk = 1;
    rst = 0;
    #5;
    rst = 1;
    #20;
    rst = 0;
end

always
    #(50) clk = ~clk;
endmodule
module mips_test();

reg clk, rst;
mips U_MIPS(
         .clk(clk),
         .reset(rst)
     );

initial begin
    $monitor("PC=%8X,Instr=%8X", U_MIPS.PC, U_MIPS.Instr);
    clk = 1;
    rst = 0;
    #5;
    rst = 1;
    #20;
    rst = 0;
end

always
    #(50) clk = ~clk;
endmodule