data/full_repos/permissive/497530416/sequential/pc_update_tb.v
1: b'%Error: data/full_repos/permissive/497530416/sequential/pc_update_tb.v:12: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("test_pc_update.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/497530416/sequential/pc_update_tb.v:13: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, test_pc_update_seq);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/497530416/sequential/pc_update_tb.v:20: Unsupported or unknown PLI call: $monitor\n        $monitor("time=%0d  icode=%0h  cnd=%0d  valP=%0d  valC=%0d  valM=%0d  new_PC=%0d",$time, icode, cnd, valP, valC, valM, PC_new);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/497530416/sequential/pc_update_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/497530416/sequential/pc_update_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497530416/sequential/pc_update_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497530416/sequential/pc_update_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n        valP = 15; #5;  \n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/497530416/sequential/pc_update_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n        valP = 25; #5;  \n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/497530416/sequential/pc_update_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n        valP = 35; #5;  \n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/497530416/sequential/pc_update_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n        valP = 37; #5;  \n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/497530416/sequential/pc_update_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n        valP = 46; #5;  \n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/497530416/sequential/pc_update_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n        valP = 48; #5;  \n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/497530416/sequential/pc_update_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n        valP = 57; #5;  \n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/497530416/sequential/pc_update_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n        valC = 100; #5;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/497530416/sequential/pc_update_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497530416/sequential/pc_update_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497530416/sequential/pc_update_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497530416/sequential/pc_update_tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Error: Exiting due to 3 error(s), 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_pc_update_seq();

reg cnd;
reg [3:0] icode;
reg [63:0] valC, valM, valP;
wire [63:0] PC_new;

pc_update PC1(icode, cnd, valC, valM, valP, PC_new);

initial
    begin   
        $dumpfile("test_pc_update.vcd");
        $dumpvars(0, test_pc_update_seq);

        valP = 1;
        valC = 2;
        valM = 80;  
        cnd = 0;
        icode = 4'b001;
        $monitor("time=%0d  icode=%0h  cnd=%0d  valP=%0d  valC=%0d  valM=%0d  new_PC=%0d",$time, icode, cnd, valP, valC, valM, PC_new);
        #5;




        icode = 4'b0110;
        valP = 3;
        #5;


        icode = 4'b0010;
        valP = 5;
        #5;


        icode = 4'b0011;
        valP = 15; #5;


        icode = 4'b0100;
        valP = 25; #5;


        icode = 4'b0101;
        valP = 35; #5;


        icode = 4'b0110;
        valP = 37; #5;




        cnd = 0; icode = 4'b0111;
        valC = 100;
        valP = 46; #5;


        icode = 4'b0110;
        valP = 48; #5;



        icode = 4'b0111;
        cnd = 1;
        valC = 150;
        valP = 57; #5;



        icode = 4'b1000;
        valP = 159;
        valC = 100; #5;



        valM = 159; icode = 4'b1001;
        valP = 101;
        #5;



        icode = 4'b1010;
        valP = 161;
        #5;



        icode = 4'b1011;
        valP = 163;
        #5;



        icode = 4'b0000;
        valP = 164;
        #5;

    end
endmodule
module test_pc_update_seq();


reg cnd;
reg [3:0] icode;
reg [63:0] valC, valM, valP;
wire [63:0] PC_new;

pc_update PC1(icode, cnd, valC, valM, valP, PC_new);

initial
    begin   
        $dumpfile("test_pc_update.vcd");
        $dumpvars(0, test_pc_update_seq);

        valP = 1;
        valC = 2;
        valM = 80;  
        cnd = 0;
        icode = 4'b001;
        $monitor("time=%0d  icode=%0h  cnd=%0d  valP=%0d  valC=%0d  valM=%0d  new_PC=%0d",$time, icode, cnd, valP, valC, valM, PC_new);
        #5;




        icode = 4'b0110;
        valP = 3;
        #5;


        icode = 4'b0010;
        valP = 5;
        #5;


        icode = 4'b0011;
        valP = 15; #5;


        icode = 4'b0100;
        valP = 25; #5;


        icode = 4'b0101;
        valP = 35; #5;


        icode = 4'b0110;
        valP = 37; #5;




        cnd = 0; icode = 4'b0111;
        valC = 100;
        valP = 46; #5;


        icode = 4'b0110;
        valP = 48; #5;



        icode = 4'b0111;
        cnd = 1;
        valC = 150;
        valP = 57; #5;



        icode = 4'b1000;
        valP = 159;
        valC = 100; #5;



        valM = 159; icode = 4'b1001;
        valP = 101;
        #5;



        icode = 4'b1010;
        valP = 161;
        #5;



        icode = 4'b1011;
        valP = 163;
        #5;



        icode = 4'b0000;
        valP = 164;
        #5;

    end
endmodule