data/full_repos/permissive/493019833/test/testcase/firrtl/MultiClockSpecanonfun22anonfunapplymcVsp12anon5/reference/MultiClockSpecanonfun22anonfunapplymcVsp12anon5.v
data/verilator_xmls/9272881c-134c-485f-9a70-d6ede1ec1a41.xml
module TAIL(y, in);
    parameter width = 4;
    parameter n = 2;
    output [width-n-1:0] y;
    input [width-1:0] in;
    assign y = in[width-n-1:0];
endmodule
module TAIL(y, in);

    parameter width = 4;
    parameter n = 2;
    output [width-n-1:0] y;
    input [width-1:0] in;
    assign y = in[width-n-1:0];
endmodule