data/full_repos/permissive/433362717/verilog/rtl/controller/status_sender_data.v
1: b'%Warning-WIDTH: data/full_repos/permissive/433362717/verilog/rtl/controller/status_sender_data.v:32: Operator VAR \'ESCAPE_CHARCTER\' expects 9 bits on the Initial value, but Initial value\'s CONST \'8\'hd\' generates 8 bits.\n                                                                                                   : ... In instance status_sender_data\n    parameter [8:0]ESCAPE_CHARCTER = 8\'h0D,\n                   ^~~~~~~~~~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/433362717/verilog/rtl/controller/status_sender_data.v:33: Operator VAR \'CLEAN_CHARCTER\' expects 9 bits on the Initial value, but Initial value\'s CONST \'8\'h20\' generates 8 bits.\n                                                                                                   : ... In instance status_sender_data\n    parameter [8:0]CLEAN_CHARCTER = 8\'h20\n                   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/433362717/verilog/rtl/controller/status_sender_data.v:79: Cannot find file containing module: \'uart\'\n    uart #(\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/433362717/verilog/rtl/controller,data/full_repos/permissive/433362717/uart\n             data/full_repos/permissive/433362717/verilog/rtl/controller,data/full_repos/permissive/433362717/uart.v\n             data/full_repos/permissive/433362717/verilog/rtl/controller,data/full_repos/permissive/433362717/uart.sv\n             uart\n             uart.v\n             uart.sv\n             obj_dir/uart\n             obj_dir/uart.v\n             obj_dir/uart.sv\n%Warning-WIDTH: data/full_repos/permissive/433362717/verilog/rtl/controller/status_sender_data.v:111: Operator ASSIGNDLY expects 52 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                    : ... In instance status_sender_data\n            control_value <= 1\'b0;\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/433362717/verilog/rtl/controller/status_sender_data.v:176: Operator EQ expects 9 bits on the LHS, but LHS\'s VARREF \'uart_rx_axis_tdata\' generates 8 bits.\n                                                                                                    : ... In instance status_sender_data\n                    else if ( uart_rx_axis_tdata == CLEAN_CHARCTER) begin\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/433362717/verilog/rtl/controller/status_sender_data.v:170: Operator EQ expects 9 bits on the LHS, but LHS\'s VARREF \'uart_rx_axis_tdata\' generates 8 bits.\n                                                                                                    : ... In instance status_sender_data\n                    if ( uart_rx_axis_tdata == ESCAPE_CHARCTER)\n                                            ^~\n%Error: Exiting due to 1 error(s), 5 warning(s)\n'
module status_sender_data #
(
    parameter WORD_SIZE = 32,
    parameter INPUT_DATA_SIZE = 52,
    parameter SIZE_WORD = 3,
    parameter STATUS_SIGNALS = 6,
    parameter STATUS_SIGNALS_UART = 4,
    parameter DATA_WIDTH = 8,
    parameter SYMBOL_WITH = 4,
    parameter [8:0]ESCAPE_CHARCTER = 8'h0D,
    parameter [8:0]CLEAN_CHARCTER = 8'h20
    
)
(
    input clk,
    input rxd, 
    input rst,
    input [SIZE_WORD-1:0] size_of_data,
    input [WORD_SIZE-1:0] data_to_send,
    input [15:0] preescalar_value,
    input valid_data,
    output reg [INPUT_DATA_SIZE-1:0] control_value,
    output reg valid_control_value,
    output busy,
    output [STATUS_SIGNALS_UART-1:0]control_uart,
    output txd
    );





    reg [DATA_WIDTH-1:0] uart_tx_axis_tdata;
    reg uart_tx_axis_tvalid;
    wire uart_tx_axis_tready;


    wire [DATA_WIDTH-1:0] uart_rx_axis_tdata;
    wire uart_rx_axis_tvalid;
    reg uart_rx_axis_tready;


    reg [INPUT_DATA_SIZE-1:0] output_value;

    reg [WORD_SIZE-1:0] send_data_register;

    reg sending_data;

    reg [SIZE_WORD-1:0] data_size_actual;



    assign busy = sending_data;



    uart #(
        .DATA_WIDTH(DATA_WIDTH)
    )
    uart_inst(
        .clk(clk),
        .rst(rst),
        .prescale (preescalar_value),
        .s_axis_tdata(uart_tx_axis_tdata),
        .s_axis_tvalid(uart_tx_axis_tvalid),
        .s_axis_tready(uart_tx_axis_tready),

        .m_axis_tdata(uart_rx_axis_tdata),
        .m_axis_tvalid(uart_rx_axis_tvalid),
        .m_axis_tready(uart_rx_axis_tready),
        .rxd(rxd),
        .txd(txd),
        .tx_busy(control_uart[0]),
        .rx_busy(control_uart[1]),
        .rx_overrun_error(control_uart[2]),
        .rx_frame_error(control_uart[3])
    );


    always @(posedge clk) begin
        if (rst) begin
            uart_tx_axis_tdata <= 0;
            uart_rx_axis_tready <= 0;
            uart_tx_axis_tvalid <= 0;
            data_size_actual <= 0;
            output_value <= 0;   
            send_data_register <= 0;
            sending_data <= 0;
            control_value <= 1'b0;
            valid_control_value <= 1'b0;
        end
        else begin

            if (uart_tx_axis_tvalid) begin


                uart_rx_axis_tready <= 0;

                if (uart_tx_axis_tready) begin
                    uart_tx_axis_tvalid <= 0;
                end
            end

            else if (sending_data) begin

                valid_control_value <= 1'b0;
                if (data_size_actual == 3'b000)begin

                    send_data_register <= 0;
                    sending_data <= 0;
                    uart_tx_axis_tvalid <= 0;
                end
                else begin

                    data_size_actual <= data_size_actual - 1'b1;

                    uart_tx_axis_tvalid <= 1'b1;

                    uart_tx_axis_tdata <= send_data_register[DATA_WIDTH-1: 0];

                    send_data_register <= send_data_register >> DATA_WIDTH;
                end
            end

            if (valid_data) begin

                valid_control_value <= 1'b0;

                sending_data <= 1'b1;

                uart_tx_axis_tvalid <= 0;
                send_data_register <= data_to_send;
                data_size_actual <= size_of_data;
            end
            else begin

                uart_rx_axis_tready <= 1;
                valid_control_value <= 1'b0;
                if (uart_rx_axis_tvalid) begin



                    uart_rx_axis_tready <= ~uart_rx_axis_tready;

                    output_value <= output_value << SYMBOL_WITH;
                    output_value [SYMBOL_WITH-1: 0] <= uart_rx_axis_tdata[SYMBOL_WITH-1:0];

                    if ( uart_rx_axis_tdata == ESCAPE_CHARCTER)
                    begin
                        control_value <= output_value;
                        valid_control_value <= 1'b1;
                        output_value <= 0;
                    end
                    else if ( uart_rx_axis_tdata == CLEAN_CHARCTER) begin
                        output_value <= 0;
                    end
                    else begin
                        valid_control_value <= 1'b0;
                    end
                    
                end
            end

        end
    end
endmodule
module status_sender_data #
(
    parameter WORD_SIZE = 32,
    parameter INPUT_DATA_SIZE = 52,
    parameter SIZE_WORD = 3,
    parameter STATUS_SIGNALS = 6,
    parameter STATUS_SIGNALS_UART = 4,
    parameter DATA_WIDTH = 8,
    parameter SYMBOL_WITH = 4,
    parameter [8:0]ESCAPE_CHARCTER = 8'h0D,
    parameter [8:0]CLEAN_CHARCTER = 8'h20
    
)
(
    input clk,
    input rxd, 
    input rst,
    input [SIZE_WORD-1:0] size_of_data,
    input [WORD_SIZE-1:0] data_to_send,
    input [15:0] preescalar_value,
    input valid_data,
    output reg [INPUT_DATA_SIZE-1:0] control_value,
    output reg valid_control_value,
    output busy,
    output [STATUS_SIGNALS_UART-1:0]control_uart,
    output txd
    );






    reg [DATA_WIDTH-1:0] uart_tx_axis_tdata;
    reg uart_tx_axis_tvalid;
    wire uart_tx_axis_tready;


    wire [DATA_WIDTH-1:0] uart_rx_axis_tdata;
    wire uart_rx_axis_tvalid;
    reg uart_rx_axis_tready;


    reg [INPUT_DATA_SIZE-1:0] output_value;

    reg [WORD_SIZE-1:0] send_data_register;

    reg sending_data;

    reg [SIZE_WORD-1:0] data_size_actual;



    assign busy = sending_data;



    uart #(
        .DATA_WIDTH(DATA_WIDTH)
    )
    uart_inst(
        .clk(clk),
        .rst(rst),
        .prescale (preescalar_value),
        .s_axis_tdata(uart_tx_axis_tdata),
        .s_axis_tvalid(uart_tx_axis_tvalid),
        .s_axis_tready(uart_tx_axis_tready),

        .m_axis_tdata(uart_rx_axis_tdata),
        .m_axis_tvalid(uart_rx_axis_tvalid),
        .m_axis_tready(uart_rx_axis_tready),
        .rxd(rxd),
        .txd(txd),
        .tx_busy(control_uart[0]),
        .rx_busy(control_uart[1]),
        .rx_overrun_error(control_uart[2]),
        .rx_frame_error(control_uart[3])
    );


    always @(posedge clk) begin
        if (rst) begin
            uart_tx_axis_tdata <= 0;
            uart_rx_axis_tready <= 0;
            uart_tx_axis_tvalid <= 0;
            data_size_actual <= 0;
            output_value <= 0;   
            send_data_register <= 0;
            sending_data <= 0;
            control_value <= 1'b0;
            valid_control_value <= 1'b0;
        end
        else begin

            if (uart_tx_axis_tvalid) begin


                uart_rx_axis_tready <= 0;

                if (uart_tx_axis_tready) begin
                    uart_tx_axis_tvalid <= 0;
                end
            end

            else if (sending_data) begin

                valid_control_value <= 1'b0;
                if (data_size_actual == 3'b000)begin

                    send_data_register <= 0;
                    sending_data <= 0;
                    uart_tx_axis_tvalid <= 0;
                end
                else begin

                    data_size_actual <= data_size_actual - 1'b1;

                    uart_tx_axis_tvalid <= 1'b1;

                    uart_tx_axis_tdata <= send_data_register[DATA_WIDTH-1: 0];

                    send_data_register <= send_data_register >> DATA_WIDTH;
                end
            end

            if (valid_data) begin

                valid_control_value <= 1'b0;

                sending_data <= 1'b1;

                uart_tx_axis_tvalid <= 0;
                send_data_register <= data_to_send;
                data_size_actual <= size_of_data;
            end
            else begin

                uart_rx_axis_tready <= 1;
                valid_control_value <= 1'b0;
                if (uart_rx_axis_tvalid) begin



                    uart_rx_axis_tready <= ~uart_rx_axis_tready;

                    output_value <= output_value << SYMBOL_WITH;
                    output_value [SYMBOL_WITH-1: 0] <= uart_rx_axis_tdata[SYMBOL_WITH-1:0];

                    if ( uart_rx_axis_tdata == ESCAPE_CHARCTER)
                    begin
                        control_value <= output_value;
                        valid_control_value <= 1'b1;
                        output_value <= 0;
                    end
                    else if ( uart_rx_axis_tdata == CLEAN_CHARCTER) begin
                        output_value <= 0;
                    end
                    else begin
                        valid_control_value <= 1'b0;
                    end
                    
                end
            end

        end
    end
endmodule