data/full_repos/permissive/42434302/ivltests/condit1.v
1: b'%Error: data/full_repos/permissive/42434302/ivltests/condit1.v:6: syntax error, unexpected bit, expecting IDENTIFIER or \'=\' or do or final\n   reg bit, foo, bar;\n       ^~~\n%Error: data/full_repos/permissive/42434302/ivltests/condit1.v:17: syntax error, unexpected \')\', expecting "\'{"\n if (bit)\n        ^\n%Error: data/full_repos/permissive/42434302/ivltests/condit1.v:25: syntax error, unexpected INTEGER NUMBER, expecting new or new-then-paren\n      bit = 0;\n            ^\n%Error: data/full_repos/permissive/42434302/ivltests/condit1.v:27: syntax error, unexpected \',\', expecting "\'{"\n      # 6 $display("bit=%b, foo=%b, bar=%b", bit, foo, bar);\n                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/condit1.v:27: Unsupported: Ignoring delay on this delayed statement.\n      # 6 $display("bit=%b, foo=%b, bar=%b", bit, foo, bar);\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/42434302/ivltests/condit1.v:28: syntax error, unexpected !==, expecting "\'{"\n      if (bit !== 0 || foo !== 0 || bar !== 1) begin\n              ^~~\n%Error: data/full_repos/permissive/42434302/ivltests/condit1.v:33: syntax error, unexpected <=, expecting IDENTIFIER or \'=\' or do or final\n      bit <= 1;\n          ^~\n%Error: data/full_repos/permissive/42434302/ivltests/condit1.v:35: syntax error, unexpected !==, expecting "\'{"\n      if (bit !== 1 || foo !== 1 || bar !== 0) begin\n              ^~~\n%Error: Cannot continue\n'
module main;

   reg bit, foo, bar;





   always @*
     begin
	foo = 0;
	bar = 0;

	if (bit)
	  foo = 1;
	else
	  bar = 1;
     end

   (* ivl_synthesis_off *)
   initial begin
      bit = 0;

      # 6 $display("bit=%b, foo=%b, bar=%b", bit, foo, bar);
      if (bit !== 0 || foo !== 0 || bar !== 1) begin
	 $display("FAILED");
	 $finish;
      end

      bit <= 1;
      #10 $display("bit=%b, foo=%b, bar=%b", bit, foo, bar);
      if (bit !== 1 || foo !== 1 || bar !== 0) begin
	 $display("FAILED");
	 $finish;
      end

      $display("PASSED");
      $finish;
   end

endmodule
module main;


   reg bit, foo, bar;





   always @*
     begin
	foo = 0;
	bar = 0;

	if (bit)
	  foo = 1;
	else
	  bar = 1;
     end

   (* ivl_synthesis_off *)
   initial begin
      bit = 0;

      # 6 $display("bit=%b, foo=%b, bar=%b", bit, foo, bar);
      if (bit !== 0 || foo !== 0 || bar !== 1) begin
	 $display("FAILED");
	 $finish;
      end

      bit <= 1;
      #10 $display("bit=%b, foo=%b, bar=%b", bit, foo, bar);
      if (bit !== 1 || foo !== 1 || bar !== 0) begin
	 $display("FAILED");
	 $finish;
      end

      $display("PASSED");
      $finish;
   end

endmodule