data/full_repos/permissive/447976230/fpga/usrp3/top/x400/rf/common/capture_sysref.v
data/verilator_xmls/c62e0b7e-9f00-4905-afd6-0f09eb981624.xml
module capture_sysref (

  input  wire pll_ref_clk,
  input  wire rfdc_clk,


  input  wire sysref_in,
  input  wire enable_rclk,


  output wire sysref_out_pclk,
  output wire sysref_out_rclk
);

  reg sysref_pclk_ms = 1'b0, sysref_pclk = 1'b0, sysref_rclk = 1'b0;



  always @ (posedge pll_ref_clk) begin
    sysref_pclk_ms <= sysref_in;
    sysref_pclk    <= sysref_pclk_ms;
  end

  assign sysref_out_pclk = sysref_pclk;


  always @ (posedge rfdc_clk) begin
    if (enable_rclk) begin
      sysref_rclk <= sysref_pclk;
    end else begin
      sysref_rclk <= 1'b0;
    end
  end

  assign sysref_out_rclk = sysref_rclk;

endmodule
module capture_sysref (

  input  wire pll_ref_clk,
  input  wire rfdc_clk,


  input  wire sysref_in,
  input  wire enable_rclk,


  output wire sysref_out_pclk,
  output wire sysref_out_rclk
);


  reg sysref_pclk_ms = 1'b0, sysref_pclk = 1'b0, sysref_rclk = 1'b0;



  always @ (posedge pll_ref_clk) begin
    sysref_pclk_ms <= sysref_in;
    sysref_pclk    <= sysref_pclk_ms;
  end

  assign sysref_out_pclk = sysref_pclk;


  always @ (posedge rfdc_clk) begin
    if (enable_rclk) begin
      sysref_rclk <= sysref_pclk;
    end else begin
      sysref_rclk <= 1'b0;
    end
  end

  assign sysref_out_rclk = sysref_rclk;

endmodule