data/full_repos/permissive/444465810/func/axi/ALU.v
data/verilator_xmls/f67254c3-9e0c-498e-a3e9-435a103a9b63.xml
module ALU(
    input [31:0] A,
    input [31:0] B,
    input [3:0] Op,
	input sign,
    output reg [31:0] Out,
	output overflow
);

always @(*) begin
    case(Op)
		0: Out = A + B;
		1: Out = A - B;
		2: Out = A & B;
		3: Out = A | B;
		4: Out = A ^ B;
		5: Out = ~(A | B);
		6: Out = B << A[4:0];
		7: Out = B >> A[4:0];
		8: Out = $signed(B) >>> A[4:0];
		9: Out = ($signed(A) < $signed(B)) ? 1 : 0;
		10: Out = (A < B) ? 1 : 0;
    endcase	
end

	assign overflow = 	(
							((Op == 0) & (A[31] == B[31]) & (A[31] != Out[31])) | 
							((Op == 1) & (A[31] != B[31]) & (A[31]) != Out[31]) 
	) & sign;
endmodule
module ALU(
    input [31:0] A,
    input [31:0] B,
    input [3:0] Op,
	input sign,
    output reg [31:0] Out,
	output overflow
);


always @(*) begin
    case(Op)
		0: Out = A + B;
		1: Out = A - B;
		2: Out = A & B;
		3: Out = A | B;
		4: Out = A ^ B;
		5: Out = ~(A | B);
		6: Out = B << A[4:0];
		7: Out = B >> A[4:0];
		8: Out = $signed(B) >>> A[4:0];
		9: Out = ($signed(A) < $signed(B)) ? 1 : 0;
		10: Out = (A < B) ? 1 : 0;
    endcase	
end

	assign overflow = 	(
							((Op == 0) & (A[31] == B[31]) & (A[31] != Out[31])) | 
							((Op == 1) & (A[31] != B[31]) & (A[31]) != Out[31]) 
	) & sign;
endmodule