data/full_repos/permissive/426889244/tb/SoC_IO_int.v
1: b"%Error: data/full_repos/permissive/426889244/tb/SoC_IO_int.v:27: Cannot find file containing module: 'IMEM'\n    IMEM imem_inst(\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/426889244/tb,data/full_repos/permissive/426889244/IMEM\n             data/full_repos/permissive/426889244/tb,data/full_repos/permissive/426889244/IMEM.v\n             data/full_repos/permissive/426889244/tb,data/full_repos/permissive/426889244/IMEM.sv\n             IMEM\n             IMEM.v\n             IMEM.sv\n             obj_dir/IMEM\n             obj_dir/IMEM.v\n             obj_dir/IMEM.sv\n%Error: data/full_repos/permissive/426889244/tb/SoC_IO_int.v:34: Cannot find file containing module: 'DMEM'\n    DMEM dmem_inst(\n    ^~~~\n%Error: data/full_repos/permissive/426889244/tb/SoC_IO_int.v:48: Cannot find file containing module: 'Core'\n    Core core0(\n    ^~~~\n%Error: data/full_repos/permissive/426889244/tb/SoC_IO_int.v:65: Cannot find file containing module: 'clock'\n    clock clock_inst(\n    ^~~~~\n%Error: data/full_repos/permissive/426889244/tb/SoC_IO_int.v:71: Cannot find file containing module: 'seg7x16'\n    seg7x16 seg7_inst(\n    ^~~~~~~\n%Error: data/full_repos/permissive/426889244/tb/SoC_IO_int.v:80: Cannot find file containing module: 'jitter_proc'\n    jitter_proc jitter_elim_inst(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/426889244/tb/SoC_IO_int.v:88: Cannot find file containing module: 'gen_inter_cycle'\n    gen_inter_cycle inter_cycle_inst(\n    ^~~~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module SoC (
    input wire base_clk,
    input wire[15:0] opr,
    input wire reset,
    input wire interrupt,
    
    output wire[15:0] leds,
    output wire[7:0] o_seg,
    output wire[7:0] o_sel
);

    wire clk_cpu;

    wire[31:0] IMEM_rdata;
    wire[31:0] DMEM_rdata;

    wire[31:0] IMEM_raddr;
    wire[31:0] DMEM_addr;
    wire[31:0] fetch_DMEM_addr;
    wire[31:0] DMEM_wdata;
    wire DMEM_we;

    wire[31:0] latest_result;
    wire jitter_elim_interruption;
    wire single_cycle_interrupt;

    IMEM imem_inst(
        .a(IMEM_raddr[31:2]),

        .spo(IMEM_rdata)
    );

    
    DMEM dmem_inst(
        .clk(clk_cpu),
        .we(DMEM_we),
        .ask_addr(DMEM_addr),
        .fetch_addr(fetch_DMEM_addr),
        .wdata(DMEM_wdata),

        .rdata(DMEM_rdata),

        .opr(opr),
        .result(leds),
        .latest_result(latest_result)
    );

    Core core0(
        .clk(clk_cpu),
        .reset(~reset),
        .cpu_ena(1'b1),
        .out_interruption(single_cycle_interrupt),

        .IMEM_rdata(IMEM_rdata),
        .DMEM_rdata(DMEM_rdata),

        .IMEM_raddr(IMEM_raddr),
        .DMEM_addr(DMEM_addr),
        .fetch_DMEM_addr(fetch_DMEM_addr),
        .DMEM_wdata(DMEM_wdata),
        .DMEM_we(DMEM_we)
    );


    clock clock_inst(
        .clk_in1(base_clk),
        .clk_out1(clk_cpu),
        .resetn(~reset)
    );

    seg7x16 seg7_inst(
        .clk(base_clk),
        .reset(reset),
        .cs(1'b1),
        .i_data(latest_result),
        .o_seg(o_seg),
        .o_sel(o_sel)
    );

    jitter_proc jitter_elim_inst(
        .clk(clk_cpu),
        .reset(~reset),
        .sig_in(interrupt),

        .valid_sig(jitter_elim_interruption)
    );

    gen_inter_cycle inter_cycle_inst(
        .clk(clk_cpu),
        .reset(~reset),
        .sig_in(jitter_elim_interruption),

        .single_cycle_interrupt(single_cycle_interrupt)
    );
endmodule
module SoC (
    input wire base_clk,
    input wire[15:0] opr,
    input wire reset,
    input wire interrupt,
    
    output wire[15:0] leds,
    output wire[7:0] o_seg,
    output wire[7:0] o_sel
);


    wire clk_cpu;

    wire[31:0] IMEM_rdata;
    wire[31:0] DMEM_rdata;

    wire[31:0] IMEM_raddr;
    wire[31:0] DMEM_addr;
    wire[31:0] fetch_DMEM_addr;
    wire[31:0] DMEM_wdata;
    wire DMEM_we;

    wire[31:0] latest_result;
    wire jitter_elim_interruption;
    wire single_cycle_interrupt;

    IMEM imem_inst(
        .a(IMEM_raddr[31:2]),

        .spo(IMEM_rdata)
    );

    
    DMEM dmem_inst(
        .clk(clk_cpu),
        .we(DMEM_we),
        .ask_addr(DMEM_addr),
        .fetch_addr(fetch_DMEM_addr),
        .wdata(DMEM_wdata),

        .rdata(DMEM_rdata),

        .opr(opr),
        .result(leds),
        .latest_result(latest_result)
    );

    Core core0(
        .clk(clk_cpu),
        .reset(~reset),
        .cpu_ena(1'b1),
        .out_interruption(single_cycle_interrupt),

        .IMEM_rdata(IMEM_rdata),
        .DMEM_rdata(DMEM_rdata),

        .IMEM_raddr(IMEM_raddr),
        .DMEM_addr(DMEM_addr),
        .fetch_DMEM_addr(fetch_DMEM_addr),
        .DMEM_wdata(DMEM_wdata),
        .DMEM_we(DMEM_we)
    );


    clock clock_inst(
        .clk_in1(base_clk),
        .clk_out1(clk_cpu),
        .resetn(~reset)
    );

    seg7x16 seg7_inst(
        .clk(base_clk),
        .reset(reset),
        .cs(1'b1),
        .i_data(latest_result),
        .o_seg(o_seg),
        .o_sel(o_sel)
    );

    jitter_proc jitter_elim_inst(
        .clk(clk_cpu),
        .reset(~reset),
        .sig_in(interrupt),

        .valid_sig(jitter_elim_interruption)
    );

    gen_inter_cycle inter_cycle_inst(
        .clk(clk_cpu),
        .reset(~reset),
        .sig_in(jitter_elim_interruption),

        .single_cycle_interrupt(single_cycle_interrupt)
    );
endmodule