data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/ONEDCONV_OEN.v
data/verilator_xmls/3358b7f2-f965-4b8c-802b-bf257a6d6c50.xml
module ONEDCONV_OEN #(parameter BITWIDTH_OF_COLUMS=11, BITWIDTH_STRIDE=4 )(


ONEDCONV_OEN_Clk,
ONEDCONV_OEN_Flag_Om_Full,
ONEDCONV_OEN_En,
ONEDCONV_OEN_Clr,
ONEDCONV_OEN_Of_Colums,
ONEDCONV_OEN_Stride,

ONEDCONV_OEN_Wptclr,
ONEDCONV_OEN_Oen,
ONEDCONV_OEN_Flag_Out_Full,
ONEDCONV_OEN_In_Routine

);






input ONEDCONV_OEN_Clk;
input ONEDCONV_OEN_Flag_Om_Full;
input ONEDCONV_OEN_En;
input ONEDCONV_OEN_Clr;
input [BITWIDTH_OF_COLUMS-1:0] ONEDCONV_OEN_Of_Colums;
input [BITWIDTH_STRIDE-1:0] ONEDCONV_OEN_Stride;
output ONEDCONV_OEN_Wptclr;
output ONEDCONV_OEN_Oen;
output ONEDCONV_OEN_Flag_Out_Full;
output ONEDCONV_OEN_In_Routine;





reg [BITWIDTH_OF_COLUMS-1:0] Oe_counter;
reg [BITWIDTH_STRIDE-1:0] Inner_Str;
reg Start_Rutine;
reg Wptclr;
reg Oe;
reg waitclk;













always @(negedge ONEDCONV_OEN_Clk)
begin
	
	if(!ONEDCONV_OEN_Clr) begin
		Start_Rutine<=0;
		Oe_counter<=0;
		Inner_Str<=0;
		Oe<=0;
		Wptclr<=1;
	end
	
	else
		begin
			if(ONEDCONV_OEN_Flag_Om_Full) begin
				Wptclr<=0;
				Oe<=1;
				Oe_counter<=1;
				Start_Rutine<=1;
			end
			
			else
				begin
					Wptclr<=1;
				end
				
			if (Start_Rutine) begin
				if(Inner_Str==(ONEDCONV_OEN_Stride-1))begin
					Oe<=1;
					Oe_counter<=Oe_counter+1'b1;
					Inner_Str<=0;
				end
				else
					begin
						Inner_Str<=Inner_Str+1'b1;
						Oe<=0;
					end
			end
		end
end






assign ONEDCONV_OEN_Wptclr=Wptclr;
assign ONEDCONV_OEN_Oen= Oe;
assign ONEDCONV_OEN_Flag_Out_Full= (Oe_counter==ONEDCONV_OEN_Of_Colums) ? 1'b1 : 1'b0;
assign ONEDCONV_OEN_In_Routine=Start_Rutine;

endmodule
module ONEDCONV_OEN #(parameter BITWIDTH_OF_COLUMS=11, BITWIDTH_STRIDE=4 )(


ONEDCONV_OEN_Clk,
ONEDCONV_OEN_Flag_Om_Full,
ONEDCONV_OEN_En,
ONEDCONV_OEN_Clr,
ONEDCONV_OEN_Of_Colums,
ONEDCONV_OEN_Stride,

ONEDCONV_OEN_Wptclr,
ONEDCONV_OEN_Oen,
ONEDCONV_OEN_Flag_Out_Full,
ONEDCONV_OEN_In_Routine

);







input ONEDCONV_OEN_Clk;
input ONEDCONV_OEN_Flag_Om_Full;
input ONEDCONV_OEN_En;
input ONEDCONV_OEN_Clr;
input [BITWIDTH_OF_COLUMS-1:0] ONEDCONV_OEN_Of_Colums;
input [BITWIDTH_STRIDE-1:0] ONEDCONV_OEN_Stride;
output ONEDCONV_OEN_Wptclr;
output ONEDCONV_OEN_Oen;
output ONEDCONV_OEN_Flag_Out_Full;
output ONEDCONV_OEN_In_Routine;





reg [BITWIDTH_OF_COLUMS-1:0] Oe_counter;
reg [BITWIDTH_STRIDE-1:0] Inner_Str;
reg Start_Rutine;
reg Wptclr;
reg Oe;
reg waitclk;













always @(negedge ONEDCONV_OEN_Clk)
begin
	
	if(!ONEDCONV_OEN_Clr) begin
		Start_Rutine<=0;
		Oe_counter<=0;
		Inner_Str<=0;
		Oe<=0;
		Wptclr<=1;
	end
	
	else
		begin
			if(ONEDCONV_OEN_Flag_Om_Full) begin
				Wptclr<=0;
				Oe<=1;
				Oe_counter<=1;
				Start_Rutine<=1;
			end
			
			else
				begin
					Wptclr<=1;
				end
				
			if (Start_Rutine) begin
				if(Inner_Str==(ONEDCONV_OEN_Stride-1))begin
					Oe<=1;
					Oe_counter<=Oe_counter+1'b1;
					Inner_Str<=0;
				end
				else
					begin
						Inner_Str<=Inner_Str+1'b1;
						Oe<=0;
					end
			end
		end
end






assign ONEDCONV_OEN_Wptclr=Wptclr;
assign ONEDCONV_OEN_Oen= Oe;
assign ONEDCONV_OEN_Flag_Out_Full= (Oe_counter==ONEDCONV_OEN_Of_Colums) ? 1'b1 : 1'b0;
assign ONEDCONV_OEN_In_Routine=Start_Rutine;

endmodule