data/full_repos/permissive/440170309/src/uart_rx.v
1: b'%Error: data/full_repos/permissive/440170309/src/uart_rx.v:17: syntax error, unexpected byte, expecting IDENTIFIER or do or final\n    output reg [7:0] byte\n                     ^~~~\n%Error: data/full_repos/permissive/440170309/src/uart_rx.v:20: syntax error, unexpected assign\n    assign clk = clk_100M;\n    ^~~~~~\n%Error: data/full_repos/permissive/440170309/src/uart_rx.v:26: syntax error, unexpected always\n    always @(posedge clk) begin\n    ^~~~~~\n%Error: data/full_repos/permissive/440170309/src/uart_rx.v:30: syntax error, unexpected assign\n    assign rx_neg_edge = ~rx & rx_delay;     \n    ^~~~~~\n%Error: data/full_repos/permissive/440170309/src/uart_rx.v:33: syntax error, unexpected always\n    always @(posedge clk) begin\n    ^~~~~~\n%Error: data/full_repos/permissive/440170309/src/uart_rx.v:49: syntax error, unexpected IDENTIFIER\n    baud_gen baud_gen(\n    ^~~~~~~~\n%Error: data/full_repos/permissive/440170309/src/uart_rx.v:58: syntax error, unexpected always\n    always @(posedge clk) begin\n    ^~~~~~\n%Error: data/full_repos/permissive/440170309/src/uart_rx.v:64: syntax error, unexpected assign\n    assign flag_data = rx_cnt!=0 && rx_cnt!=9;\n    ^~~~~~\n%Error: Exiting due to 8 error(s)\n'
module baud_gen (
    input wire clk_100M,
    input wire rst,
    input wire rx_en,

    output wire rx_valid
);
    parameter BAUD_DIV = 868;

    reg [9: 0] counter;
    reg flag_start_bit;
    always @(posedge clk_100M) begin
        if(rx_en) begin
            if(sample1) begin
                counter <= 0;
                flag_start_bit <= 0;
            end
            else if(sample2) begin
                counter <= 0;
            end
            else begin
                counter <= counter + 1;
            end
        end
        else begin
            counter <= 0;
            flag_start_bit <= 1;
        end
    end
    wire sample1 = flag_start_bit && counter == (BAUD_DIV>>1);
    wire sample2 = counter == BAUD_DIV;

    assign rx_valid = sample1 | sample2;
endmodule
module baud_gen (
    input wire clk_100M,
    input wire rst,
    input wire rx_en,

    output wire rx_valid
);

    parameter BAUD_DIV = 868;

    reg [9: 0] counter;
    reg flag_start_bit;
    always @(posedge clk_100M) begin
        if(rx_en) begin
            if(sample1) begin
                counter <= 0;
                flag_start_bit <= 0;
            end
            else if(sample2) begin
                counter <= 0;
            end
            else begin
                counter <= counter + 1;
            end
        end
        else begin
            counter <= 0;
            flag_start_bit <= 1;
        end
    end
    wire sample1 = flag_start_bit && counter == (BAUD_DIV>>1);
    wire sample2 = counter == BAUD_DIV;

    assign rx_valid = sample1 | sample2;
endmodule