data/full_repos/permissive/485129576/cpu.v
1: b'%Error: data/full_repos/permissive/485129576/cpu.v:1: Cannot find include file: alu8.v\n`include "alu8.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/485129576,data/full_repos/permissive/485129576/alu8.v\n             data/full_repos/permissive/485129576,data/full_repos/permissive/485129576/alu8.v.v\n             data/full_repos/permissive/485129576,data/full_repos/permissive/485129576/alu8.v.sv\n             alu8.v\n             alu8.v.v\n             alu8.v.sv\n             obj_dir/alu8.v\n             obj_dir/alu8.v.v\n             obj_dir/alu8.v.sv\n%Error: data/full_repos/permissive/485129576/cpu.v:2: Cannot find include file: buffer8.v\n`include "buffer8.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/485129576/cpu.v:3: Cannot find include file: demux4t1.v\n`include "demux4t1.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/485129576/cpu.v:4: Cannot find include file: mem16.v\n`include "mem16.v" \n         ^~~~~~~~~\n%Error: data/full_repos/permissive/485129576/cpu.v:5: Cannot find include file: mux2t1.v\n`include "mux2t1.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/485129576/cpu.v:6: Cannot find include file: mux4t1.v\n`include "mux4t1.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/485129576/cpu.v:7: Cannot find include file: ram.v\n`include "ram.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/485129576/cpu.v:8: Cannot find include file: reg2.v\n`include "reg2.v" \n         ^~~~~~~~\n%Error: data/full_repos/permissive/485129576/cpu.v:9: Cannot find include file: reg8.v\n`include "reg8.v" \n         ^~~~~~~~\n%Error: data/full_repos/permissive/485129576/cpu.v:10: Cannot find include file: regfile.v\n`include "regfile.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/485129576/cpu.v:18: syntax error, unexpected const, expecting IDENTIFIER or do or final\n    wire [7:0] const, memOut;\n                    ^\n%Error: data/full_repos/permissive/485129576/cpu.v:34: syntax error, unexpected const, expecting TYPE-IDENTIFIER\n    assign const = instruc[11:4];\n                 ^\n%Error: data/full_repos/permissive/485129576/cpu.v:39: syntax error, unexpected const, expecting TYPE-IDENTIFIER\n    MUX2t1 immMux(.A(const), .B(regoutB), .sel(opcode[3]), .R(aluB));\n                          ^\n%Error: data/full_repos/permissive/485129576/cpu.v:42: syntax error, unexpected const, expecting TYPE-IDENTIFIER\n    RAM dataMem(.addr(const), .dataIn(regoutA), .we(memWrite), .clk(memWrite), .dataOut(memOut));\n                           ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #1\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:52: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:54: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:60: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:62: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:68: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:70: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:76: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:78: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:84: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:86: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:92: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:94: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:100: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:102: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:108: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:110: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:117: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:119: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:125: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:127: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:133: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:135: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:141: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:143: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:149: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:151: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:158: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:163: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:165: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:167: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Error: data/full_repos/permissive/485129576/cpu.v:204: syntax error, unexpected const, expecting TYPE-IDENTIFIER\n            pc = const;\n                      ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:208: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:212: Unsupported: Ignoring delay on this delayed statement.\n        #10 clk <= ~clk;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/485129576/cpu.v:224: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/485129576/cpu.v:225: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("out.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/485129576/cpu.v:226: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, clk, instruc, pc, opcode, op2, regfileWrite, enbuf, enjump, regoutA, aluB, data, databuf, flagsStored, memWrite, memMuxSel);\n        ^~~~~~~~~\n%Error: Exiting due to 17 error(s), 34 warning(s)\n'
module CPU();
    wire [15:0] instruc;
    wire [3:0] opcode, op2;
    wire [1:0] Rs1, Rs2, Re;
    wire [7:0] const, memOut;

    wire [1:0] flagsALU, flagsStored;
    wire [7:0] regoutA, regoutB, aluB, data, databuf, aluOut;

    reg [7:0] pc;
    reg clk;
    reg regfileWrite, enbuf, enjump, memWrite, memMuxSel;

    wire [7:0] Q0, Q1, Q2, Q3;

    assign opcode = instruc[15:12];
    assign Rs2 = instruc[5:4];
    assign Rs1 = instruc[3:2];
    assign Re = instruc[1:0];
    assign op2 = instruc[3:0];
    assign const = instruc[11:4];

    ALU8 alu(.op(opcode), .A(regoutA), .B(aluB), .R(aluOut), .flags(flagsALU));
    BUF8 buffer(.in(data), .enable(enbuf), .out(databuf));
    REGFILE rwreg(.selDin(Re), .selAout(Rs1), .selBout(Rs2), .flagsIn(flagsALU), .write(regfileWrite), .data(databuf), .regoutA(regoutA), .regoutB(regoutB), .flagsOut(flagsStored));
    MUX2t1 immMux(.A(const), .B(regoutB), .sel(opcode[3]), .R(aluB));
    MUX2t1 memMux(.A(aluOut), .B(memOut), .sel(memMuxSel), .R(data));
    MEM16 instrucMem(.A(pc), .instruc(instruc));
    RAM dataMem(.addr(const), .dataIn(regoutA), .we(memWrite), .clk(memWrite), .dataOut(memOut));

    always @(posedge clk) begin
        #1
        if (instruc == 16'b0000000000000000)
    		$finish;

    	case(opcode)
    	    4'b1000 : begin
                enbuf = 1;
                #1
                regfileWrite = 1;
                #1
                regfileWrite = 0;
    		    enbuf = 0;
            end
            4'b1001 : begin
                enbuf = 1;
                #1
                regfileWrite = 1;
                #1
                regfileWrite = 0;
    		    enbuf = 0;
            end
            4'b1010 : begin
                enbuf = 1;
                #1
                regfileWrite = 1;
                #1
                regfileWrite = 0;
    		    enbuf = 0;
            end
            4'b1011 : begin
                enbuf = 1;
                #1
                regfileWrite = 1;
                #1
                regfileWrite = 0;
    		    enbuf = 0;
            end
            4'b1100 : begin
                enbuf = 1;
                #1
                regfileWrite = 1;
                #1
                regfileWrite = 0;
    		    enbuf = 0;
            end
            4'b1101 : begin
                enbuf = 1;
                #1
                regfileWrite = 1;
                #1
                regfileWrite = 0;
    		    enbuf = 0;
            end
            4'b1110 : begin
                enbuf = 1;
                #1
                regfileWrite = 1;
                #1
                regfileWrite = 0;
    		    enbuf = 0;
            end
            4'b1111 : begin
                enbuf = 1;
                #1
                regfileWrite = 1;
                #1
                regfileWrite = 0;
    		    enbuf = 0;
            end

    	    4'b0001 : begin
                enbuf = 1;
                #1
                regfileWrite = 1;
                #1
                regfileWrite = 0;
    		    enbuf = 0;
            end
            4'b0010 : begin
                enbuf = 1;
                #1
                regfileWrite = 1;
                #1
                regfileWrite = 0;
    		    enbuf = 0;
            end
            4'b0011 : begin
                enbuf = 1;
                #1
                regfileWrite = 1;
                #1
                regfileWrite = 0;
    		    enbuf = 0;
            end
            4'b0100 : begin
                enbuf = 1;
                #1
                regfileWrite = 1;
                #1
                regfileWrite = 0;
    		    enbuf = 0;
            end
            4'b0101 : begin
                enbuf = 1;
                #1
                regfileWrite = 1;
                #1
                regfileWrite = 0;
    		    enbuf = 0;
            end

            4'b0110 : begin
                memWrite = 1;
                #1
                memWrite = 0;
            end
            4'b0111 : begin
                memMuxSel <= 1;
                #1
                enbuf <= 1;
                #1
                regfileWrite <= 1;
                #1
                regfileWrite = 0;
    		    enbuf = 0;
                memMuxSel = 0;
            end

            4'b0000 : begin
                case(op2)
                    4'b1000 : begin
                        enjump = 1;
                    end
                    4'b0100 : begin
                        if(flagsStored[0] == 1) enjump = 1;
                    end
                    4'b0101 : begin
                        if(flagsStored[0] == 0) enjump = 1;
                    end
                    4'b0110 : begin
                        if(flagsStored[1] == 1) enjump = 1;
                    end
                    4'b0111 : begin
                        if(flagsStored[1] == 0) enjump = 1;
                    end
                endcase
            end

            default : begin
                enbuf <= 0;
                regfileWrite <= 0;
            end
        endcase

    end

    always @(posedge clk) begin
        if(enjump == 0) pc = pc + 1;
        if(enjump == 1) begin 
            pc = const;
            enjump = 0;
        end
    
        #20;
    end

    always begin
        #10 clk <= ~clk;
    end

    initial begin
        clk <= 0;
        pc <= -1;
        enbuf <= 0;
        regfileWrite <= 0;
        enjump <= 0;
        memMuxSel <= 0;
        memWrite <= 0;

        #10;
        $dumpfile("out.vcd");
        $dumpvars(0, clk, instruc, pc, opcode, op2, regfileWrite, enbuf, enjump, regoutA, aluB, data, databuf, flagsStored, memWrite, memMuxSel);
    end

endmodule
module CPU();

    wire [15:0] instruc;
    wire [3:0] opcode, op2;
    wire [1:0] Rs1, Rs2, Re;
    wire [7:0] const, memOut;

    wire [1:0] flagsALU, flagsStored;
    wire [7:0] regoutA, regoutB, aluB, data, databuf, aluOut;

    reg [7:0] pc;
    reg clk;
    reg regfileWrite, enbuf, enjump, memWrite, memMuxSel;

    wire [7:0] Q0, Q1, Q2, Q3;

    assign opcode = instruc[15:12];
    assign Rs2 = instruc[5:4];
    assign Rs1 = instruc[3:2];
    assign Re = instruc[1:0];
    assign op2 = instruc[3:0];
    assign const = instruc[11:4];

    ALU8 alu(.op(opcode), .A(regoutA), .B(aluB), .R(aluOut), .flags(flagsALU));
    BUF8 buffer(.in(data), .enable(enbuf), .out(databuf));
    REGFILE rwreg(.selDin(Re), .selAout(Rs1), .selBout(Rs2), .flagsIn(flagsALU), .write(regfileWrite), .data(databuf), .regoutA(regoutA), .regoutB(regoutB), .flagsOut(flagsStored));
    MUX2t1 immMux(.A(const), .B(regoutB), .sel(opcode[3]), .R(aluB));
    MUX2t1 memMux(.A(aluOut), .B(memOut), .sel(memMuxSel), .R(data));
    MEM16 instrucMem(.A(pc), .instruc(instruc));
    RAM dataMem(.addr(const), .dataIn(regoutA), .we(memWrite), .clk(memWrite), .dataOut(memOut));

    always @(posedge clk) begin
        #1
        if (instruc == 16'b0000000000000000)
    		$finish;

    	case(opcode)
    	    4'b1000 : begin
                enbuf = 1;
                #1
                regfileWrite = 1;
                #1
                regfileWrite = 0;
    		    enbuf = 0;
            end
            4'b1001 : begin
                enbuf = 1;
                #1
                regfileWrite = 1;
                #1
                regfileWrite = 0;
    		    enbuf = 0;
            end
            4'b1010 : begin
                enbuf = 1;
                #1
                regfileWrite = 1;
                #1
                regfileWrite = 0;
    		    enbuf = 0;
            end
            4'b1011 : begin
                enbuf = 1;
                #1
                regfileWrite = 1;
                #1
                regfileWrite = 0;
    		    enbuf = 0;
            end
            4'b1100 : begin
                enbuf = 1;
                #1
                regfileWrite = 1;
                #1
                regfileWrite = 0;
    		    enbuf = 0;
            end
            4'b1101 : begin
                enbuf = 1;
                #1
                regfileWrite = 1;
                #1
                regfileWrite = 0;
    		    enbuf = 0;
            end
            4'b1110 : begin
                enbuf = 1;
                #1
                regfileWrite = 1;
                #1
                regfileWrite = 0;
    		    enbuf = 0;
            end
            4'b1111 : begin
                enbuf = 1;
                #1
                regfileWrite = 1;
                #1
                regfileWrite = 0;
    		    enbuf = 0;
            end

    	    4'b0001 : begin
                enbuf = 1;
                #1
                regfileWrite = 1;
                #1
                regfileWrite = 0;
    		    enbuf = 0;
            end
            4'b0010 : begin
                enbuf = 1;
                #1
                regfileWrite = 1;
                #1
                regfileWrite = 0;
    		    enbuf = 0;
            end
            4'b0011 : begin
                enbuf = 1;
                #1
                regfileWrite = 1;
                #1
                regfileWrite = 0;
    		    enbuf = 0;
            end
            4'b0100 : begin
                enbuf = 1;
                #1
                regfileWrite = 1;
                #1
                regfileWrite = 0;
    		    enbuf = 0;
            end
            4'b0101 : begin
                enbuf = 1;
                #1
                regfileWrite = 1;
                #1
                regfileWrite = 0;
    		    enbuf = 0;
            end

            4'b0110 : begin
                memWrite = 1;
                #1
                memWrite = 0;
            end
            4'b0111 : begin
                memMuxSel <= 1;
                #1
                enbuf <= 1;
                #1
                regfileWrite <= 1;
                #1
                regfileWrite = 0;
    		    enbuf = 0;
                memMuxSel = 0;
            end

            4'b0000 : begin
                case(op2)
                    4'b1000 : begin
                        enjump = 1;
                    end
                    4'b0100 : begin
                        if(flagsStored[0] == 1) enjump = 1;
                    end
                    4'b0101 : begin
                        if(flagsStored[0] == 0) enjump = 1;
                    end
                    4'b0110 : begin
                        if(flagsStored[1] == 1) enjump = 1;
                    end
                    4'b0111 : begin
                        if(flagsStored[1] == 0) enjump = 1;
                    end
                endcase
            end

            default : begin
                enbuf <= 0;
                regfileWrite <= 0;
            end
        endcase

    end

    always @(posedge clk) begin
        if(enjump == 0) pc = pc + 1;
        if(enjump == 1) begin 
            pc = const;
            enjump = 0;
        end
    
        #20;
    end

    always begin
        #10 clk <= ~clk;
    end

    initial begin
        clk <= 0;
        pc <= -1;
        enbuf <= 0;
        regfileWrite <= 0;
        enjump <= 0;
        memMuxSel <= 0;
        memWrite <= 0;

        #10;
        $dumpfile("out.vcd");
        $dumpvars(0, clk, instruc, pc, opcode, op2, regfileWrite, enbuf, enjump, regoutA, aluB, data, databuf, flagsStored, memWrite, memMuxSel);
    end

endmodule