data/full_repos/permissive/515100461/ALU/test_XOR.v
1: b'%Error: data/full_repos/permissive/515100461/ALU/test_XOR.v:10: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("dump.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/515100461/ALU/test_XOR.v:11: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0,test);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/515100461/ALU/test_XOR.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #40 $finish;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/515100461/ALU/test_XOR.v:18: Unsupported: Ignoring delay on this delayed statement.\n  always #10 A = ~A;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/ALU/test_XOR.v:19: Unsupported: Ignoring delay on this delayed statement.\n  always #20 B = ~B;\n         ^\n%Error: data/full_repos/permissive/515100461/ALU/test_XOR.v:24: Unsupported or unknown PLI call: $monitor\n    $monitor("time = %0t,A = %b,B = %b,AND= %b",$time,A,B,OUT);\n    ^~~~~~~~\n%Error: Exiting due to 3 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

reg signed [63:0]A,B;
wire signed [63:0]OUT;


And uut(.A(A),.B(B),.OUT(OUT));

initial begin
  $dumpfile("dump.vcd");
  $dumpvars(0,test);
  A = 64'b0000000000000000000000000000000011111111111111111111111111111111;
  B = 64'b1111111111111111111111111111111100000000000000000000000000000000;

  #40 $finish;
end

  always #10 A = ~A;
  always #20 B = ~B;



initial 
    $monitor("time = %0t,A = %b,B = %b,AND= %b",$time,A,B,OUT);

endmodule
module test;


reg signed [63:0]A,B;
wire signed [63:0]OUT;


And uut(.A(A),.B(B),.OUT(OUT));

initial begin
  $dumpfile("dump.vcd");
  $dumpvars(0,test);
  A = 64'b0000000000000000000000000000000011111111111111111111111111111111;
  B = 64'b1111111111111111111111111111111100000000000000000000000000000000;

  #40 $finish;
end

  always #10 A = ~A;
  always #20 B = ~B;



initial 
    $monitor("time = %0t,A = %b,B = %b,AND= %b",$time,A,B,OUT);

endmodule