data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v
1: b"%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:540: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\breaker.loop_breaker  (\n  ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block,data/full_repos/permissive/496906136/fpga_tech_buffer\n             data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block,data/full_repos/permissive/496906136/fpga_tech_buffer.v\n             data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block,data/full_repos/permissive/496906136/fpga_tech_buffer.sv\n             fpga_tech_buffer\n             fpga_tech_buffer.v\n             fpga_tech_buffer.sv\n             obj_dir/fpga_tech_buffer\n             obj_dir/fpga_tech_buffer.v\n             obj_dir/fpga_tech_buffer.sv\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:544: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\breaker.lut_tfinish  (\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:548: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\breaker.lut_tstart  (\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:347: Cannot find file containing module: 'fpga_tech_register'\n  fpga_tech_register cell_reg (\n  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:355: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\in_bufs:1.cell_tstart  (\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:359: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\in_bufs:2.cell_tstart  (\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:363: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\in_bufs:3.cell_tstart  (\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:367: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\in_bufs:4.cell_tstart  (\n  ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module fpga_logic_block(clk_i, glb_rstn_i, config_clk_i, config_ena_i, config_shift_i, inputs_i, config_shift_o, outputs_o);
  wire _00_;
  wire _01_;
  wire _02_;
  wire _03_;
  wire _04_;
  wire _05_;
  wire _06_;
  wire _07_;
  wire _08_;
  wire _09_;
  wire _10_;
  wire [263:0] _11_;
  wire _12_;
  wire _13_;
  wire _14_;
  wire _15_;
  wire _16_;
  wire _17_;
  wire _18_;
  wire _19_;
  wire _20_;
  wire _21_;
  wire _22_;
  wire _23_;
  wire _24_;
  wire _25_;
  wire _26_;
  wire _27_;
  wire _28_;
  wire _29_;
  wire _30_;
  wire _31_;
  wire _32_;
  wire _33_;
  wire _34_;
  wire _35_;
  wire _36_;
  wire _37_;
  wire _38_;
  wire _39_;
  wire _40_;
  wire _41_;
  wire [31:0] cell_in;
  wire [7:0] cell_out;
  input clk_i;
  input config_clk_i;
  wire [263:0] config_data;
  input config_ena_i;
  wire [263:0] config_record;
  input config_shift_i;
  output config_shift_o;
  input glb_rstn_i;
  input [31:0] inputs_i;
  output [7:0] outputs_o;
  fpga_cfg_shiftreg_264 config_register (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_o(_11_),
    .config_shift_i(config_shift_i),
    .config_shift_o(_10_)
  );
  fpga_routing_mux_16_4_0 \crossbar:1.crossbar_mux  (
    .config_i(config_record[127:124]),
    .route_i({ inputs_i[7:0], cell_out }),
    .route_o(_20_)
  );
  fpga_routing_mux_16_4_2 \crossbar:10.crossbar_mux  (
    .config_i(config_record[91:88]),
    .route_i({ inputs_i[15:8], cell_out }),
    .route_o(_29_)
  );
  fpga_routing_mux_16_4_2 \crossbar:11.crossbar_mux  (
    .config_i(config_record[87:84]),
    .route_i({ inputs_i[23:16], cell_out }),
    .route_o(_30_)
  );
  fpga_routing_mux_16_4_2 \crossbar:12.crossbar_mux  (
    .config_i(config_record[83:80]),
    .route_i({ inputs_i[31:24], cell_out }),
    .route_o(_31_)
  );
  fpga_routing_mux_16_4_3 \crossbar:13.crossbar_mux  (
    .config_i(config_record[79:76]),
    .route_i({ inputs_i[7:0], cell_out }),
    .route_o(_32_)
  );
  fpga_routing_mux_16_4_3 \crossbar:14.crossbar_mux  (
    .config_i(config_record[75:72]),
    .route_i({ inputs_i[15:8], cell_out }),
    .route_o(_33_)
  );
  fpga_routing_mux_16_4_3 \crossbar:15.crossbar_mux  (
    .config_i(config_record[71:68]),
    .route_i({ inputs_i[23:16], cell_out }),
    .route_o(_34_)
  );
  fpga_routing_mux_16_4_3 \crossbar:16.crossbar_mux  (
    .config_i(config_record[67:64]),
    .route_i({ inputs_i[31:24], cell_out }),
    .route_o(_35_)
  );
  fpga_routing_mux_16_4_4 \crossbar:17.crossbar_mux  (
    .config_i(config_record[63:60]),
    .route_i({ inputs_i[7:0], cell_out }),
    .route_o(_36_)
  );
  fpga_routing_mux_16_4_4 \crossbar:18.crossbar_mux  (
    .config_i(config_record[59:56]),
    .route_i({ inputs_i[15:8], cell_out }),
    .route_o(_37_)
  );
  fpga_routing_mux_16_4_4 \crossbar:19.crossbar_mux  (
    .config_i(config_record[55:52]),
    .route_i({ inputs_i[23:16], cell_out }),
    .route_o(_38_)
  );
  fpga_routing_mux_16_4_0 \crossbar:2.crossbar_mux  (
    .config_i(config_record[123:120]),
    .route_i({ inputs_i[15:8], cell_out }),
    .route_o(_21_)
  );
  fpga_routing_mux_16_4_4 \crossbar:20.crossbar_mux  (
    .config_i(config_record[51:48]),
    .route_i({ inputs_i[31:24], cell_out }),
    .route_o(_39_)
  );
  fpga_routing_mux_16_4_5 \crossbar:21.crossbar_mux  (
    .config_i(config_record[47:44]),
    .route_i({ inputs_i[7:0], cell_out }),
    .route_o(_40_)
  );
  fpga_routing_mux_16_4_5 \crossbar:22.crossbar_mux  (
    .config_i(config_record[43:40]),
    .route_i({ inputs_i[15:8], cell_out }),
    .route_o(_41_)
  );
  fpga_routing_mux_16_4_5 \crossbar:23.crossbar_mux  (
    .config_i(config_record[39:36]),
    .route_i({ inputs_i[23:16], cell_out }),
    .route_o(_00_)
  );
  fpga_routing_mux_16_4_5 \crossbar:24.crossbar_mux  (
    .config_i(config_record[35:32]),
    .route_i({ inputs_i[31:24], cell_out }),
    .route_o(_01_)
  );
  fpga_routing_mux_16_4_6 \crossbar:25.crossbar_mux  (
    .config_i(config_record[31:28]),
    .route_i({ inputs_i[7:0], cell_out }),
    .route_o(_02_)
  );
  fpga_routing_mux_16_4_6 \crossbar:26.crossbar_mux  (
    .config_i(config_record[27:24]),
    .route_i({ inputs_i[15:8], cell_out }),
    .route_o(_03_)
  );
  fpga_routing_mux_16_4_6 \crossbar:27.crossbar_mux  (
    .config_i(config_record[23:20]),
    .route_i({ inputs_i[23:16], cell_out }),
    .route_o(_04_)
  );
  fpga_routing_mux_16_4_6 \crossbar:28.crossbar_mux  (
    .config_i(config_record[19:16]),
    .route_i({ inputs_i[31:24], cell_out }),
    .route_o(_05_)
  );
  fpga_routing_mux_16_4_7 \crossbar:29.crossbar_mux  (
    .config_i(config_record[15:12]),
    .route_i({ inputs_i[7:0], cell_out }),
    .route_o(_06_)
  );
  fpga_routing_mux_16_4_0 \crossbar:3.crossbar_mux  (
    .config_i(config_record[119:116]),
    .route_i({ inputs_i[23:16], cell_out }),
    .route_o(_22_)
  );
  fpga_routing_mux_16_4_7 \crossbar:30.crossbar_mux  (
    .config_i(config_record[11:8]),
    .route_i({ inputs_i[15:8], cell_out }),
    .route_o(_07_)
  );
  fpga_routing_mux_16_4_7 \crossbar:31.crossbar_mux  (
    .config_i(config_record[7:4]),
    .route_i({ inputs_i[23:16], cell_out }),
    .route_o(_08_)
  );
  fpga_routing_mux_16_4_7 \crossbar:32.crossbar_mux  (
    .config_i(config_record[3:0]),
    .route_i({ inputs_i[31:24], cell_out }),
    .route_o(_09_)
  );
  fpga_routing_mux_16_4_0 \crossbar:4.crossbar_mux  (
    .config_i(config_record[115:112]),
    .route_i({ inputs_i[31:24], cell_out }),
    .route_o(_23_)
  );
  fpga_routing_mux_16_4_1 \crossbar:5.crossbar_mux  (
    .config_i(config_record[111:108]),
    .route_i({ inputs_i[7:0], cell_out }),
    .route_o(_24_)
  );
  fpga_routing_mux_16_4_1 \crossbar:6.crossbar_mux  (
    .config_i(config_record[107:104]),
    .route_i({ inputs_i[15:8], cell_out }),
    .route_o(_25_)
  );
  fpga_routing_mux_16_4_1 \crossbar:7.crossbar_mux  (
    .config_i(config_record[103:100]),
    .route_i({ inputs_i[23:16], cell_out }),
    .route_o(_26_)
  );
  fpga_routing_mux_16_4_1 \crossbar:8.crossbar_mux  (
    .config_i(config_record[99:96]),
    .route_i({ inputs_i[31:24], cell_out }),
    .route_o(_27_)
  );
  fpga_routing_mux_16_4_2 \crossbar:9.crossbar_mux  (
    .config_i(config_record[95:92]),
    .route_i({ inputs_i[7:0], cell_out }),
    .route_o(_28_)
  );
  fpga_logic_cell \logic_cells:1.cell  (
    .clk_i(clk_i),
    .\config_i.lut_config (config_record[262:247]),
    .\config_i.mux_config (config_record[263]),
    .glb_rstn_i(glb_rstn_i),
    .logic_i(cell_in[31:28]),
    .logic_o(_12_)
  );
  fpga_logic_cell \logic_cells:2.cell  (
    .clk_i(clk_i),
    .\config_i.lut_config (config_record[245:230]),
    .\config_i.mux_config (config_record[246]),
    .glb_rstn_i(glb_rstn_i),
    .logic_i(cell_in[27:24]),
    .logic_o(_13_)
  );
  fpga_logic_cell \logic_cells:3.cell  (
    .clk_i(clk_i),
    .\config_i.lut_config (config_record[228:213]),
    .\config_i.mux_config (config_record[229]),
    .glb_rstn_i(glb_rstn_i),
    .logic_i(cell_in[23:20]),
    .logic_o(_14_)
  );
  fpga_logic_cell \logic_cells:4.cell  (
    .clk_i(clk_i),
    .\config_i.lut_config (config_record[211:196]),
    .\config_i.mux_config (config_record[212]),
    .glb_rstn_i(glb_rstn_i),
    .logic_i(cell_in[19:16]),
    .logic_o(_15_)
  );
  fpga_logic_cell \logic_cells:5.cell  (
    .clk_i(clk_i),
    .\config_i.lut_config (config_record[194:179]),
    .\config_i.mux_config (config_record[195]),
    .glb_rstn_i(glb_rstn_i),
    .logic_i(cell_in[15:12]),
    .logic_o(_16_)
  );
  fpga_logic_cell \logic_cells:6.cell  (
    .clk_i(clk_i),
    .\config_i.lut_config (config_record[177:162]),
    .\config_i.mux_config (config_record[178]),
    .glb_rstn_i(glb_rstn_i),
    .logic_i(cell_in[11:8]),
    .logic_o(_17_)
  );
  fpga_logic_cell \logic_cells:7.cell  (
    .clk_i(clk_i),
    .\config_i.lut_config (config_record[160:145]),
    .\config_i.mux_config (config_record[161]),
    .glb_rstn_i(glb_rstn_i),
    .logic_i(cell_in[7:4]),
    .logic_o(_18_)
  );
  fpga_logic_cell \logic_cells:8.cell  (
    .clk_i(clk_i),
    .\config_i.lut_config (config_record[143:128]),
    .\config_i.mux_config (config_record[144]),
    .glb_rstn_i(glb_rstn_i),
    .logic_i(cell_in[3:0]),
    .logic_o(_19_)
  );
  assign cell_in = { _23_, _22_, _21_, _20_, _27_, _26_, _25_, _24_, _31_, _30_, _29_, _28_, _35_, _34_, _33_, _32_, _39_, _38_, _37_, _36_, _01_, _00_, _41_, _40_, _05_, _04_, _03_, _02_, _09_, _08_, _07_, _06_ };
  assign cell_out = { _19_, _18_, _17_, _16_, _15_, _14_, _13_, _12_ };
  assign config_data = _11_;
  assign config_record = { config_data[144:128], config_data[161:145], config_data[178:162], config_data[195:179], config_data[212:196], config_data[229:213], config_data[246:230], config_data[263:247], config_data[3:0], config_data[7:4], config_data[11:8], config_data[15:12], config_data[19:16], config_data[23:20], config_data[27:24], config_data[31:28], config_data[35:32], config_data[39:36], config_data[43:40], config_data[47:44], config_data[51:48], config_data[55:52], config_data[59:56], config_data[63:60], config_data[67:64], config_data[71:68], config_data[75:72], config_data[79:76], config_data[83:80], config_data[87:84], config_data[91:88], config_data[95:92], config_data[99:96], config_data[103:100], config_data[107:104], config_data[111:108], config_data[115:112], config_data[119:116], config_data[123:120], config_data[127:124] };
  assign config_shift_o = _10_;
  assign outputs_o = cell_out;
endmodule
module fpga_logic_block(clk_i, glb_rstn_i, config_clk_i, config_ena_i, config_shift_i, inputs_i, config_shift_o, outputs_o);

  wire _00_;
  wire _01_;
  wire _02_;
  wire _03_;
  wire _04_;
  wire _05_;
  wire _06_;
  wire _07_;
  wire _08_;
  wire _09_;
  wire _10_;
  wire [263:0] _11_;
  wire _12_;
  wire _13_;
  wire _14_;
  wire _15_;
  wire _16_;
  wire _17_;
  wire _18_;
  wire _19_;
  wire _20_;
  wire _21_;
  wire _22_;
  wire _23_;
  wire _24_;
  wire _25_;
  wire _26_;
  wire _27_;
  wire _28_;
  wire _29_;
  wire _30_;
  wire _31_;
  wire _32_;
  wire _33_;
  wire _34_;
  wire _35_;
  wire _36_;
  wire _37_;
  wire _38_;
  wire _39_;
  wire _40_;
  wire _41_;
  wire [31:0] cell_in;
  wire [7:0] cell_out;
  input clk_i;
  input config_clk_i;
  wire [263:0] config_data;
  input config_ena_i;
  wire [263:0] config_record;
  input config_shift_i;
  output config_shift_o;
  input glb_rstn_i;
  input [31:0] inputs_i;
  output [7:0] outputs_o;
  fpga_cfg_shiftreg_264 config_register (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_o(_11_),
    .config_shift_i(config_shift_i),
    .config_shift_o(_10_)
  );
  fpga_routing_mux_16_4_0 \crossbar:1.crossbar_mux  (
    .config_i(config_record[127:124]),
    .route_i({ inputs_i[7:0], cell_out }),
    .route_o(_20_)
  );
  fpga_routing_mux_16_4_2 \crossbar:10.crossbar_mux  (
    .config_i(config_record[91:88]),
    .route_i({ inputs_i[15:8], cell_out }),
    .route_o(_29_)
  );
  fpga_routing_mux_16_4_2 \crossbar:11.crossbar_mux  (
    .config_i(config_record[87:84]),
    .route_i({ inputs_i[23:16], cell_out }),
    .route_o(_30_)
  );
  fpga_routing_mux_16_4_2 \crossbar:12.crossbar_mux  (
    .config_i(config_record[83:80]),
    .route_i({ inputs_i[31:24], cell_out }),
    .route_o(_31_)
  );
  fpga_routing_mux_16_4_3 \crossbar:13.crossbar_mux  (
    .config_i(config_record[79:76]),
    .route_i({ inputs_i[7:0], cell_out }),
    .route_o(_32_)
  );
  fpga_routing_mux_16_4_3 \crossbar:14.crossbar_mux  (
    .config_i(config_record[75:72]),
    .route_i({ inputs_i[15:8], cell_out }),
    .route_o(_33_)
  );
  fpga_routing_mux_16_4_3 \crossbar:15.crossbar_mux  (
    .config_i(config_record[71:68]),
    .route_i({ inputs_i[23:16], cell_out }),
    .route_o(_34_)
  );
  fpga_routing_mux_16_4_3 \crossbar:16.crossbar_mux  (
    .config_i(config_record[67:64]),
    .route_i({ inputs_i[31:24], cell_out }),
    .route_o(_35_)
  );
  fpga_routing_mux_16_4_4 \crossbar:17.crossbar_mux  (
    .config_i(config_record[63:60]),
    .route_i({ inputs_i[7:0], cell_out }),
    .route_o(_36_)
  );
  fpga_routing_mux_16_4_4 \crossbar:18.crossbar_mux  (
    .config_i(config_record[59:56]),
    .route_i({ inputs_i[15:8], cell_out }),
    .route_o(_37_)
  );
  fpga_routing_mux_16_4_4 \crossbar:19.crossbar_mux  (
    .config_i(config_record[55:52]),
    .route_i({ inputs_i[23:16], cell_out }),
    .route_o(_38_)
  );
  fpga_routing_mux_16_4_0 \crossbar:2.crossbar_mux  (
    .config_i(config_record[123:120]),
    .route_i({ inputs_i[15:8], cell_out }),
    .route_o(_21_)
  );
  fpga_routing_mux_16_4_4 \crossbar:20.crossbar_mux  (
    .config_i(config_record[51:48]),
    .route_i({ inputs_i[31:24], cell_out }),
    .route_o(_39_)
  );
  fpga_routing_mux_16_4_5 \crossbar:21.crossbar_mux  (
    .config_i(config_record[47:44]),
    .route_i({ inputs_i[7:0], cell_out }),
    .route_o(_40_)
  );
  fpga_routing_mux_16_4_5 \crossbar:22.crossbar_mux  (
    .config_i(config_record[43:40]),
    .route_i({ inputs_i[15:8], cell_out }),
    .route_o(_41_)
  );
  fpga_routing_mux_16_4_5 \crossbar:23.crossbar_mux  (
    .config_i(config_record[39:36]),
    .route_i({ inputs_i[23:16], cell_out }),
    .route_o(_00_)
  );
  fpga_routing_mux_16_4_5 \crossbar:24.crossbar_mux  (
    .config_i(config_record[35:32]),
    .route_i({ inputs_i[31:24], cell_out }),
    .route_o(_01_)
  );
  fpga_routing_mux_16_4_6 \crossbar:25.crossbar_mux  (
    .config_i(config_record[31:28]),
    .route_i({ inputs_i[7:0], cell_out }),
    .route_o(_02_)
  );
  fpga_routing_mux_16_4_6 \crossbar:26.crossbar_mux  (
    .config_i(config_record[27:24]),
    .route_i({ inputs_i[15:8], cell_out }),
    .route_o(_03_)
  );
  fpga_routing_mux_16_4_6 \crossbar:27.crossbar_mux  (
    .config_i(config_record[23:20]),
    .route_i({ inputs_i[23:16], cell_out }),
    .route_o(_04_)
  );
  fpga_routing_mux_16_4_6 \crossbar:28.crossbar_mux  (
    .config_i(config_record[19:16]),
    .route_i({ inputs_i[31:24], cell_out }),
    .route_o(_05_)
  );
  fpga_routing_mux_16_4_7 \crossbar:29.crossbar_mux  (
    .config_i(config_record[15:12]),
    .route_i({ inputs_i[7:0], cell_out }),
    .route_o(_06_)
  );
  fpga_routing_mux_16_4_0 \crossbar:3.crossbar_mux  (
    .config_i(config_record[119:116]),
    .route_i({ inputs_i[23:16], cell_out }),
    .route_o(_22_)
  );
  fpga_routing_mux_16_4_7 \crossbar:30.crossbar_mux  (
    .config_i(config_record[11:8]),
    .route_i({ inputs_i[15:8], cell_out }),
    .route_o(_07_)
  );
  fpga_routing_mux_16_4_7 \crossbar:31.crossbar_mux  (
    .config_i(config_record[7:4]),
    .route_i({ inputs_i[23:16], cell_out }),
    .route_o(_08_)
  );
  fpga_routing_mux_16_4_7 \crossbar:32.crossbar_mux  (
    .config_i(config_record[3:0]),
    .route_i({ inputs_i[31:24], cell_out }),
    .route_o(_09_)
  );
  fpga_routing_mux_16_4_0 \crossbar:4.crossbar_mux  (
    .config_i(config_record[115:112]),
    .route_i({ inputs_i[31:24], cell_out }),
    .route_o(_23_)
  );
  fpga_routing_mux_16_4_1 \crossbar:5.crossbar_mux  (
    .config_i(config_record[111:108]),
    .route_i({ inputs_i[7:0], cell_out }),
    .route_o(_24_)
  );
  fpga_routing_mux_16_4_1 \crossbar:6.crossbar_mux  (
    .config_i(config_record[107:104]),
    .route_i({ inputs_i[15:8], cell_out }),
    .route_o(_25_)
  );
  fpga_routing_mux_16_4_1 \crossbar:7.crossbar_mux  (
    .config_i(config_record[103:100]),
    .route_i({ inputs_i[23:16], cell_out }),
    .route_o(_26_)
  );
  fpga_routing_mux_16_4_1 \crossbar:8.crossbar_mux  (
    .config_i(config_record[99:96]),
    .route_i({ inputs_i[31:24], cell_out }),
    .route_o(_27_)
  );
  fpga_routing_mux_16_4_2 \crossbar:9.crossbar_mux  (
    .config_i(config_record[95:92]),
    .route_i({ inputs_i[7:0], cell_out }),
    .route_o(_28_)
  );
  fpga_logic_cell \logic_cells:1.cell  (
    .clk_i(clk_i),
    .\config_i.lut_config (config_record[262:247]),
    .\config_i.mux_config (config_record[263]),
    .glb_rstn_i(glb_rstn_i),
    .logic_i(cell_in[31:28]),
    .logic_o(_12_)
  );
  fpga_logic_cell \logic_cells:2.cell  (
    .clk_i(clk_i),
    .\config_i.lut_config (config_record[245:230]),
    .\config_i.mux_config (config_record[246]),
    .glb_rstn_i(glb_rstn_i),
    .logic_i(cell_in[27:24]),
    .logic_o(_13_)
  );
  fpga_logic_cell \logic_cells:3.cell  (
    .clk_i(clk_i),
    .\config_i.lut_config (config_record[228:213]),
    .\config_i.mux_config (config_record[229]),
    .glb_rstn_i(glb_rstn_i),
    .logic_i(cell_in[23:20]),
    .logic_o(_14_)
  );
  fpga_logic_cell \logic_cells:4.cell  (
    .clk_i(clk_i),
    .\config_i.lut_config (config_record[211:196]),
    .\config_i.mux_config (config_record[212]),
    .glb_rstn_i(glb_rstn_i),
    .logic_i(cell_in[19:16]),
    .logic_o(_15_)
  );
  fpga_logic_cell \logic_cells:5.cell  (
    .clk_i(clk_i),
    .\config_i.lut_config (config_record[194:179]),
    .\config_i.mux_config (config_record[195]),
    .glb_rstn_i(glb_rstn_i),
    .logic_i(cell_in[15:12]),
    .logic_o(_16_)
  );
  fpga_logic_cell \logic_cells:6.cell  (
    .clk_i(clk_i),
    .\config_i.lut_config (config_record[177:162]),
    .\config_i.mux_config (config_record[178]),
    .glb_rstn_i(glb_rstn_i),
    .logic_i(cell_in[11:8]),
    .logic_o(_17_)
  );
  fpga_logic_cell \logic_cells:7.cell  (
    .clk_i(clk_i),
    .\config_i.lut_config (config_record[160:145]),
    .\config_i.mux_config (config_record[161]),
    .glb_rstn_i(glb_rstn_i),
    .logic_i(cell_in[7:4]),
    .logic_o(_18_)
  );
  fpga_logic_cell \logic_cells:8.cell  (
    .clk_i(clk_i),
    .\config_i.lut_config (config_record[143:128]),
    .\config_i.mux_config (config_record[144]),
    .glb_rstn_i(glb_rstn_i),
    .logic_i(cell_in[3:0]),
    .logic_o(_19_)
  );
  assign cell_in = { _23_, _22_, _21_, _20_, _27_, _26_, _25_, _24_, _31_, _30_, _29_, _28_, _35_, _34_, _33_, _32_, _39_, _38_, _37_, _36_, _01_, _00_, _41_, _40_, _05_, _04_, _03_, _02_, _09_, _08_, _07_, _06_ };
  assign cell_out = { _19_, _18_, _17_, _16_, _15_, _14_, _13_, _12_ };
  assign config_data = _11_;
  assign config_record = { config_data[144:128], config_data[161:145], config_data[178:162], config_data[195:179], config_data[212:196], config_data[229:213], config_data[246:230], config_data[263:247], config_data[3:0], config_data[7:4], config_data[11:8], config_data[15:12], config_data[19:16], config_data[23:20], config_data[27:24], config_data[31:28], config_data[35:32], config_data[39:36], config_data[43:40], config_data[47:44], config_data[51:48], config_data[55:52], config_data[59:56], config_data[63:60], config_data[67:64], config_data[71:68], config_data[75:72], config_data[79:76], config_data[83:80], config_data[87:84], config_data[91:88], config_data[95:92], config_data[99:96], config_data[103:100], config_data[107:104], config_data[111:108], config_data[115:112], config_data[119:116], config_data[123:120], config_data[127:124] };
  assign config_shift_o = _10_;
  assign outputs_o = cell_out;
endmodule