data/full_repos/permissive/491294671/timer_input_control/div_100/div_100.v
data/verilator_xmls/7649de25-a148-44ef-90bc-e1729a2a9fc7.xml
module div_5(input clock, output reg clock_div);
  reg [2:0] count = 3'b000;
  reg ff_out = 0;
  
  always @(posedge clock)
    begin
      if(count < 4)
        count <= count+1;
      else
        count <= 0;
      clock_div <= ff_out | count[1];
    end
  always @(negedge clock)
    begin
      ff_out <= count[1];
      clock_div <= ff_out | count[1];
    end
  
  
endmodule
module div_5(input clock, output reg clock_div);

  reg [2:0] count = 3'b000;
  reg ff_out = 0;
  
  always @(posedge clock)
    begin
      if(count < 4)
        count <= count+1;
      else
        count <= 0;
      clock_div <= ff_out | count[1];
    end
  always @(negedge clock)
    begin
      ff_out <= count[1];
      clock_div <= ff_out | count[1];
    end
  
  
endmodule