data/full_repos/permissive/479308240/datapath_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/479308240/datapath_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n          #30 clktb=1\'b0;  seldsttb=3\'h1;        selsrctb=3\'h3;         dstentb=1\'b1;       srcentb=1\'b1;        rsttb=1\'b0;        PortINtb=8\'hFF;  \n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/479308240/datapath_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n          #30 rsttb=1\'b1;  \n          ^\n%Warning-STMTDLY: data/full_repos/permissive/479308240/datapath_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #5 clktb=~clktb;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/479308240/datapath_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #190    seldsttb=3\'h4;  selsrctb=3\'h1; dstentb=1\'b1; srcentb=1\'b1; rsttb=1\'b1;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/479308240/datapath_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #120    seldsttb=3\'h2;  selsrctb=3\'h3; dstentb=1\'b1; srcentb=1\'b1; rsttb=1\'b1; PortINtb=8\'h0F;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/479308240/datapath_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #120    seldsttb=3\'h4;  selsrctb=3\'h2; dstentb=1\'b1; srcentb=1\'b1; rsttb=1\'b1;  \n        ^\n%Error: data/full_repos/permissive/479308240/datapath_tb.v:14: Cannot find file containing module: \'datapath\'\ndatapath UUT (\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/479308240,data/full_repos/permissive/479308240/datapath\n             data/full_repos/permissive/479308240,data/full_repos/permissive/479308240/datapath.v\n             data/full_repos/permissive/479308240,data/full_repos/permissive/479308240/datapath.sv\n             datapath\n             datapath.v\n             datapath.sv\n             obj_dir/datapath\n             obj_dir/datapath.v\n             obj_dir/datapath.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module datapath_tb();

reg [7:0] PortINtb;
wire [7:0] PortOUTtb;
reg [2:0] seldsttb;
reg [2:0] selsrctb;
reg clktb;
reg dstentb;
reg srcentb;
reg rsttb;

datapath UUT (
                .PortIN(PortINtb),
                .PortOUT(PortOUTtb),
                .seldst(seldsttb),
                .selsrc(selsrctb),
                .dsten(dstentb),
                .srcen(srcentb),
                .clk(clktb),
                .rst(rsttb)
                );

initial 
        begin
          #30 clktb=1'b0;  seldsttb=3'h1;        selsrctb=3'h3;         dstentb=1'b1;       srcentb=1'b1;        rsttb=1'b0;        PortINtb=8'hFF;
          #30 rsttb=1'b1;
        end

always 
    begin
    #5 clktb=~clktb;
    end



initial
        begin     
        #190    seldsttb=3'h4;  selsrctb=3'h1; dstentb=1'b1; srcentb=1'b1; rsttb=1'b1;
        #120    seldsttb=3'h2;  selsrctb=3'h3; dstentb=1'b1; srcentb=1'b1; rsttb=1'b1; PortINtb=8'h0F;
        #120    seldsttb=3'h4;  selsrctb=3'h2; dstentb=1'b1; srcentb=1'b1; rsttb=1'b1;
        end


endmodule
module datapath_tb();


reg [7:0] PortINtb;
wire [7:0] PortOUTtb;
reg [2:0] seldsttb;
reg [2:0] selsrctb;
reg clktb;
reg dstentb;
reg srcentb;
reg rsttb;

datapath UUT (
                .PortIN(PortINtb),
                .PortOUT(PortOUTtb),
                .seldst(seldsttb),
                .selsrc(selsrctb),
                .dsten(dstentb),
                .srcen(srcentb),
                .clk(clktb),
                .rst(rsttb)
                );

initial 
        begin
          #30 clktb=1'b0;  seldsttb=3'h1;        selsrctb=3'h3;         dstentb=1'b1;       srcentb=1'b1;        rsttb=1'b0;        PortINtb=8'hFF;
          #30 rsttb=1'b1;
        end

always 
    begin
    #5 clktb=~clktb;
    end



initial
        begin     
        #190    seldsttb=3'h4;  selsrctb=3'h1; dstentb=1'b1; srcentb=1'b1; rsttb=1'b1;
        #120    seldsttb=3'h2;  selsrctb=3'h3; dstentb=1'b1; srcentb=1'b1; rsttb=1'b1; PortINtb=8'h0F;
        #120    seldsttb=3'h4;  selsrctb=3'h2; dstentb=1'b1; srcentb=1'b1; rsttb=1'b1;
        end


endmodule