data/full_repos/permissive/425175279/MIPS_Multi_Cycle/Instr_Data_Memory.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/425175279/MIPS_Multi_Cycle/Instr_Data_Memory.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #1400\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Instr_Data_Memory(

	input				clk,
    input   	[31:0]	A,
	input		[31:0]	WD,
	input				IRWrite,
	input				MemWrite,

	output	reg	[31:0]	Instr,
	output	reg	[31:0]	Data

    
);
	integer fd;
	wire [31:0] RD;
	reg [7:0] Instr_Data_Mem [84:0];



	initial begin
		$readmemh("./memfile.dat",Instr_Data_Mem,0,71);
		fd = $fopen("./MEM_Data.txt", "w");  
        #1400
        $fclose(fd);
	end

    assign RD = {{Instr_Data_Mem[A]},{Instr_Data_Mem[A+32'd1]},{Instr_Data_Mem[A+32'd2]},{Instr_Data_Mem[A+32'd3]}};

	always @(posedge clk) begin
		Data <= RD;
		if (IRWrite) begin
			Instr <= RD;
		end

		if (MemWrite) begin
			{{Instr_Data_Mem[A]},{Instr_Data_Mem[A+32'd1]},{Instr_Data_Mem[A+32'd2]},{Instr_Data_Mem[A+32'd3]}} <= WD;
			$fdisplay(fd,"The Write Address A is %h", A);
            $fdisplay(fd,"DATA_MEM[A] is %h", WD);
		end
	end
endmodule
module Instr_Data_Memory(

	input				clk,
    input   	[31:0]	A,
	input		[31:0]	WD,
	input				IRWrite,
	input				MemWrite,

	output	reg	[31:0]	Instr,
	output	reg	[31:0]	Data

    
);

	integer fd;
	wire [31:0] RD;
	reg [7:0] Instr_Data_Mem [84:0];



	initial begin
		$readmemh("./memfile.dat",Instr_Data_Mem,0,71);
		fd = $fopen("./MEM_Data.txt", "w");  
        #1400
        $fclose(fd);
	end

    assign RD = {{Instr_Data_Mem[A]},{Instr_Data_Mem[A+32'd1]},{Instr_Data_Mem[A+32'd2]},{Instr_Data_Mem[A+32'd3]}};

	always @(posedge clk) begin
		Data <= RD;
		if (IRWrite) begin
			Instr <= RD;
		end

		if (MemWrite) begin
			{{Instr_Data_Mem[A]},{Instr_Data_Mem[A+32'd1]},{Instr_Data_Mem[A+32'd2]},{Instr_Data_Mem[A+32'd3]}} <= WD;
			$fdisplay(fd,"The Write Address A is %h", A);
            $fdisplay(fd,"DATA_MEM[A] is %h", WD);
		end
	end
endmodule