data/full_repos/permissive/524509242/FSM GCD/clock_divider.v
1: b'%Error: Cannot find file containing module: GCD,data/full_repos/permissive/524509242\n        ... Looked in:\n             data/full_repos/permissive/524509242/FSM/GCD,data/full_repos/permissive/524509242\n             data/full_repos/permissive/524509242/FSM/GCD,data/full_repos/permissive/524509242.v\n             data/full_repos/permissive/524509242/FSM/GCD,data/full_repos/permissive/524509242.sv\n             GCD,data/full_repos/permissive/524509242\n             GCD,data/full_repos/permissive/524509242.v\n             GCD,data/full_repos/permissive/524509242.sv\n             obj_dir/GCD,data/full_repos/permissive/524509242\n             obj_dir/GCD,data/full_repos/permissive/524509242.v\n             obj_dir/GCD,data/full_repos/permissive/524509242.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/524509242/FSM\n%Error: Cannot find file containing module: GCD/clock_divider.v\n%Error: Exiting due to 3 error(s)\n'
module clock_divider(clk ,rst, clk_div  );

input clk;
input rst;
output reg clk_div;

localparam constantNumber = 26'd25000000;

reg [25:0] count;

initial
begin
	count = 26'd0;
end
 
always @ (posedge(clk), posedge(rst))
begin
    if (rst == 1'b1)
        count <= 26'b0;
    else if (count == constantNumber - 1)
        count <= 26'b0;
    else
        count <= count + 26'd1;
end

always @ (posedge(clk), posedge(rst))
begin
    if (rst == 1'b1)
        clk_div <= 1'b0;
    else if (count == constantNumber - 1)
        clk_div <= ~clk_div;
    else
        clk_div <= clk_div;
end

endmodule
module clock_divider(clk ,rst, clk_div  );


input clk;
input rst;
output reg clk_div;

localparam constantNumber = 26'd25000000;

reg [25:0] count;

initial
begin
	count = 26'd0;
end
 
always @ (posedge(clk), posedge(rst))
begin
    if (rst == 1'b1)
        count <= 26'b0;
    else if (count == constantNumber - 1)
        count <= 26'b0;
    else
        count <= count + 26'd1;
end

always @ (posedge(clk), posedge(rst))
begin
    if (rst == 1'b1)
        clk_div <= 1'b0;
    else if (count == constantNumber - 1)
        clk_div <= ~clk_div;
    else
        clk_div <= clk_div;
end

endmodule