data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/ciu/rtl/ct_ciu_snb_dp_sel_16.v
data/verilator_xmls/a92fa764-086e-4eae-b36a-f05fad0162a7.xml
module ct_ciu_snb_dp_sel_16(
  entry0_age_vect,
  entry10_age_vect,
  entry11_age_vect,
  entry12_age_vect,
  entry13_age_vect,
  entry14_age_vect,
  entry15_age_vect,
  entry1_age_vect,
  entry2_age_vect,
  entry3_age_vect,
  entry4_age_vect,
  entry5_age_vect,
  entry6_age_vect,
  entry7_age_vect,
  entry8_age_vect,
  entry9_age_vect,
  req_vld,
  sel
);


input   [23:0]  entry0_age_vect; 
input   [23:0]  entry10_age_vect; 
input   [23:0]  entry11_age_vect; 
input   [23:0]  entry12_age_vect; 
input   [23:0]  entry13_age_vect; 
input   [23:0]  entry14_age_vect; 
input   [23:0]  entry15_age_vect; 
input   [23:0]  entry1_age_vect; 
input   [23:0]  entry2_age_vect; 
input   [23:0]  entry3_age_vect; 
input   [23:0]  entry4_age_vect; 
input   [23:0]  entry5_age_vect; 
input   [23:0]  entry6_age_vect; 
input   [23:0]  entry7_age_vect; 
input   [23:0]  entry8_age_vect; 
input   [23:0]  entry9_age_vect; 
input   [15:0]  req_vld;         
output  [15:0]  sel;             




wire    [23:0]  entry0_age_vect; 
wire    [23:0]  entry10_age_vect; 
wire    [23:0]  entry11_age_vect; 
wire    [23:0]  entry12_age_vect; 
wire    [23:0]  entry13_age_vect; 
wire    [23:0]  entry14_age_vect; 
wire    [23:0]  entry15_age_vect; 
wire    [23:0]  entry1_age_vect; 
wire    [23:0]  entry2_age_vect; 
wire    [23:0]  entry3_age_vect; 
wire    [23:0]  entry4_age_vect; 
wire    [23:0]  entry5_age_vect; 
wire    [23:0]  entry6_age_vect; 
wire    [23:0]  entry7_age_vect; 
wire    [23:0]  entry8_age_vect; 
wire    [23:0]  entry9_age_vect; 
wire    [15:0]  req_vld;         
wire    [15:0]  sel;             



















parameter DEPTH = 16;

assign sel[0] = req_vld[0] && !(|(req_vld[DEPTH-1:0] & entry0_age_vect[DEPTH-1:0]));
assign sel[1] = req_vld[1] && !(|(req_vld[DEPTH-1:0] & entry1_age_vect[DEPTH-1:0]));
assign sel[2] = req_vld[2] && !(|(req_vld[DEPTH-1:0] & entry2_age_vect[DEPTH-1:0]));
assign sel[3] = req_vld[3] && !(|(req_vld[DEPTH-1:0] & entry3_age_vect[DEPTH-1:0]));
assign sel[4] = req_vld[4] && !(|(req_vld[DEPTH-1:0] & entry4_age_vect[DEPTH-1:0]));
assign sel[5] = req_vld[5] && !(|(req_vld[DEPTH-1:0] & entry5_age_vect[DEPTH-1:0]));
assign sel[6] = req_vld[6] && !(|(req_vld[DEPTH-1:0] & entry6_age_vect[DEPTH-1:0]));
assign sel[7] = req_vld[7] && !(|(req_vld[DEPTH-1:0] & entry7_age_vect[DEPTH-1:0]));
assign sel[8] = req_vld[8] && !(|(req_vld[DEPTH-1:0] & entry8_age_vect[DEPTH-1:0]));
assign sel[9] = req_vld[9] && !(|(req_vld[DEPTH-1:0] & entry9_age_vect[DEPTH-1:0]));
assign sel[10] = req_vld[10] && !(|(req_vld[DEPTH-1:0] & entry10_age_vect[DEPTH-1:0]));
assign sel[11] = req_vld[11] && !(|(req_vld[DEPTH-1:0] & entry11_age_vect[DEPTH-1:0]));
assign sel[12] = req_vld[12] && !(|(req_vld[DEPTH-1:0] & entry12_age_vect[DEPTH-1:0]));
assign sel[13] = req_vld[13] && !(|(req_vld[DEPTH-1:0] & entry13_age_vect[DEPTH-1:0]));
assign sel[14] = req_vld[14] && !(|(req_vld[DEPTH-1:0] & entry14_age_vect[DEPTH-1:0]));
assign sel[15] = req_vld[15] && !(|(req_vld[DEPTH-1:0] & entry15_age_vect[DEPTH-1:0]));


endmodule
module ct_ciu_snb_dp_sel_16(
  entry0_age_vect,
  entry10_age_vect,
  entry11_age_vect,
  entry12_age_vect,
  entry13_age_vect,
  entry14_age_vect,
  entry15_age_vect,
  entry1_age_vect,
  entry2_age_vect,
  entry3_age_vect,
  entry4_age_vect,
  entry5_age_vect,
  entry6_age_vect,
  entry7_age_vect,
  entry8_age_vect,
  entry9_age_vect,
  req_vld,
  sel
);



input   [23:0]  entry0_age_vect; 
input   [23:0]  entry10_age_vect; 
input   [23:0]  entry11_age_vect; 
input   [23:0]  entry12_age_vect; 
input   [23:0]  entry13_age_vect; 
input   [23:0]  entry14_age_vect; 
input   [23:0]  entry15_age_vect; 
input   [23:0]  entry1_age_vect; 
input   [23:0]  entry2_age_vect; 
input   [23:0]  entry3_age_vect; 
input   [23:0]  entry4_age_vect; 
input   [23:0]  entry5_age_vect; 
input   [23:0]  entry6_age_vect; 
input   [23:0]  entry7_age_vect; 
input   [23:0]  entry8_age_vect; 
input   [23:0]  entry9_age_vect; 
input   [15:0]  req_vld;         
output  [15:0]  sel;             




wire    [23:0]  entry0_age_vect; 
wire    [23:0]  entry10_age_vect; 
wire    [23:0]  entry11_age_vect; 
wire    [23:0]  entry12_age_vect; 
wire    [23:0]  entry13_age_vect; 
wire    [23:0]  entry14_age_vect; 
wire    [23:0]  entry15_age_vect; 
wire    [23:0]  entry1_age_vect; 
wire    [23:0]  entry2_age_vect; 
wire    [23:0]  entry3_age_vect; 
wire    [23:0]  entry4_age_vect; 
wire    [23:0]  entry5_age_vect; 
wire    [23:0]  entry6_age_vect; 
wire    [23:0]  entry7_age_vect; 
wire    [23:0]  entry8_age_vect; 
wire    [23:0]  entry9_age_vect; 
wire    [15:0]  req_vld;         
wire    [15:0]  sel;             



















parameter DEPTH = 16;

assign sel[0] = req_vld[0] && !(|(req_vld[DEPTH-1:0] & entry0_age_vect[DEPTH-1:0]));
assign sel[1] = req_vld[1] && !(|(req_vld[DEPTH-1:0] & entry1_age_vect[DEPTH-1:0]));
assign sel[2] = req_vld[2] && !(|(req_vld[DEPTH-1:0] & entry2_age_vect[DEPTH-1:0]));
assign sel[3] = req_vld[3] && !(|(req_vld[DEPTH-1:0] & entry3_age_vect[DEPTH-1:0]));
assign sel[4] = req_vld[4] && !(|(req_vld[DEPTH-1:0] & entry4_age_vect[DEPTH-1:0]));
assign sel[5] = req_vld[5] && !(|(req_vld[DEPTH-1:0] & entry5_age_vect[DEPTH-1:0]));
assign sel[6] = req_vld[6] && !(|(req_vld[DEPTH-1:0] & entry6_age_vect[DEPTH-1:0]));
assign sel[7] = req_vld[7] && !(|(req_vld[DEPTH-1:0] & entry7_age_vect[DEPTH-1:0]));
assign sel[8] = req_vld[8] && !(|(req_vld[DEPTH-1:0] & entry8_age_vect[DEPTH-1:0]));
assign sel[9] = req_vld[9] && !(|(req_vld[DEPTH-1:0] & entry9_age_vect[DEPTH-1:0]));
assign sel[10] = req_vld[10] && !(|(req_vld[DEPTH-1:0] & entry10_age_vect[DEPTH-1:0]));
assign sel[11] = req_vld[11] && !(|(req_vld[DEPTH-1:0] & entry11_age_vect[DEPTH-1:0]));
assign sel[12] = req_vld[12] && !(|(req_vld[DEPTH-1:0] & entry12_age_vect[DEPTH-1:0]));
assign sel[13] = req_vld[13] && !(|(req_vld[DEPTH-1:0] & entry13_age_vect[DEPTH-1:0]));
assign sel[14] = req_vld[14] && !(|(req_vld[DEPTH-1:0] & entry14_age_vect[DEPTH-1:0]));
assign sel[15] = req_vld[15] && !(|(req_vld[DEPTH-1:0] & entry15_age_vect[DEPTH-1:0]));


endmodule