data/full_repos/permissive/516385853/kernel_kcore/kernel_kcore_fifo_w64_d128_A.v
1: b'%Warning-WIDTH: data/full_repos/permissive/516385853/kernel_kcore/kernel_kcore_fifo_w64_d128_A.v:66: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                   : ... In instance kernel_kcore_fifo_w64_d128_A\nreg  [ADDR_WIDTH-1:0] waddr = 1\'b0;\n                              ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/516385853/kernel_kcore/kernel_kcore_fifo_w64_d128_A.v:67: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                   : ... In instance kernel_kcore_fifo_w64_d128_A\nreg  [ADDR_WIDTH-1:0] raddr = 1\'b0;\n                              ^~~~\n%Warning-WIDTH: data/full_repos/permissive/516385853/kernel_kcore/kernel_kcore_fifo_w64_d128_A.v:72: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                   : ... In instance kernel_kcore_fifo_w64_d128_A\nreg  [ADDR_WIDTH:0]   mOutPtr = 1\'b0;\n                                ^~~~\n%Warning-WIDTH: data/full_repos/permissive/516385853/kernel_kcore/kernel_kcore_fifo_w64_d128_A.v:100: Operator EQ expects 32 or 8 bits on the LHS, but LHS\'s VARREF \'waddr\' generates 7 bits.\n                                                                                                    : ... In instance kernel_kcore_fifo_w64_d128_A\n                    (waddr == DEPTH - 1) ? 1\'b0  :\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/516385853/kernel_kcore/kernel_kcore_fifo_w64_d128_A.v:100: Operator COND expects 7 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                    : ... In instance kernel_kcore_fifo_w64_d128_A\n                    (waddr == DEPTH - 1) ? 1\'b0  :\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/516385853/kernel_kcore/kernel_kcore_fifo_w64_d128_A.v:103: Operator EQ expects 32 or 8 bits on the LHS, but LHS\'s VARREF \'raddr\' generates 7 bits.\n                                                                                                    : ... In instance kernel_kcore_fifo_w64_d128_A\n                    (raddr == DEPTH - 1) ? 1\'b0  :\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/516385853/kernel_kcore/kernel_kcore_fifo_w64_d128_A.v:103: Operator COND expects 7 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                    : ... In instance kernel_kcore_fifo_w64_d128_A\n                    (raddr == DEPTH - 1) ? 1\'b0  :\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/516385853/kernel_kcore/kernel_kcore_fifo_w64_d128_A.v:109: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                    : ... In instance kernel_kcore_fifo_w64_d128_A\n        waddr <= 1\'b0;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/516385853/kernel_kcore/kernel_kcore_fifo_w64_d128_A.v:117: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                    : ... In instance kernel_kcore_fifo_w64_d128_A\n        raddr <= 1\'b0;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/516385853/kernel_kcore/kernel_kcore_fifo_w64_d128_A.v:125: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                    : ... In instance kernel_kcore_fifo_w64_d128_A\n        mOutPtr <= 1\'b0;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/516385853/kernel_kcore/kernel_kcore_fifo_w64_d128_A.v:149: Operator NEQ expects 8 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                                    : ... In instance kernel_kcore_fifo_w64_d128_A\n        empty_n <= (mOutPtr != 1\'b1);\n                            ^~\n%Error: Exiting due to 11 warning(s)\n'
module kernel_kcore_fifo_w64_d128_A
#(parameter
    DATA_WIDTH  = 64,
    ADDR_WIDTH  = 7,
    DEPTH       = 128
)
(

    input  wire                  clk,
    input  wire                  reset,


    output wire                  if_full_n,
    input  wire                  if_write_ce,
    input  wire                  if_write,
    input  wire [DATA_WIDTH-1:0] if_din,


    output wire                  if_empty_n,
    input  wire                  if_read_ce,
    input  wire                  if_read,
    output wire [DATA_WIDTH-1:0] if_dout
);



reg  [ADDR_WIDTH-1:0] waddr = 1'b0;
reg  [ADDR_WIDTH-1:0] raddr = 1'b0;
wire [ADDR_WIDTH-1:0] wnext;
wire [ADDR_WIDTH-1:0] rnext;
wire                  push;
wire                  pop;
reg  [ADDR_WIDTH:0]   mOutPtr = 1'b0;
reg                   full_n = 1'b1;
reg                   empty_n = 1'b0;



kernel_kcore_fifo_w64_d128_A_ram
#(
 .DATA_WIDTH(DATA_WIDTH),
 .ADDR_WIDTH(ADDR_WIDTH),
 .DEPTH(DEPTH))
U_kernel_kcore_fifo_w64_d128_A_ram(
 .clk(clk),
 .we(push),
 .waddr(waddr),
 .din(if_din),
 .raddr(rnext),
 .dout(if_dout)
);




assign if_full_n  = full_n;
assign if_empty_n = empty_n;
assign push       = full_n & if_write_ce & if_write;
assign pop        = empty_n & if_read_ce & if_read;
assign wnext      = !push                ? waddr :
                    (waddr == DEPTH - 1) ? 1'b0  :
                    waddr + 1'b1;
assign rnext      = !pop                 ? raddr :
                    (raddr == DEPTH - 1) ? 1'b0  :
                    raddr + 1'b1;


always @(posedge clk) begin
    if (reset == 1'b1)
        waddr <= 1'b0;
    else
        waddr <= wnext;
end


always @(posedge clk) begin
    if (reset == 1'b1)
        raddr <= 1'b0;
    else
        raddr <= rnext;
end


always @(posedge clk) begin
    if (reset == 1'b1)
        mOutPtr <= 1'b0;
    else if (push & ~pop)
        mOutPtr <= mOutPtr + 1'b1;
    else if (~push & pop)
        mOutPtr <= mOutPtr - 1'b1;
end


always @(posedge clk) begin
    if (reset == 1'b1)
        full_n <= 1'b1;
    else if (push & ~pop)
        full_n <= (mOutPtr != DEPTH - 1);
    else if (~push & pop)
        full_n <= 1'b1;
end


always @(posedge clk) begin
    if (reset == 1'b1)
        empty_n <= 1'b0;
    else if (push & ~pop)
        empty_n <= 1'b1;
    else if (~push & pop)
        empty_n <= (mOutPtr != 1'b1);
end

endmodule
module kernel_kcore_fifo_w64_d128_A
#(parameter
    DATA_WIDTH  = 64,
    ADDR_WIDTH  = 7,
    DEPTH       = 128
)
(

    input  wire                  clk,
    input  wire                  reset,


    output wire                  if_full_n,
    input  wire                  if_write_ce,
    input  wire                  if_write,
    input  wire [DATA_WIDTH-1:0] if_din,


    output wire                  if_empty_n,
    input  wire                  if_read_ce,
    input  wire                  if_read,
    output wire [DATA_WIDTH-1:0] if_dout
);




reg  [ADDR_WIDTH-1:0] waddr = 1'b0;
reg  [ADDR_WIDTH-1:0] raddr = 1'b0;
wire [ADDR_WIDTH-1:0] wnext;
wire [ADDR_WIDTH-1:0] rnext;
wire                  push;
wire                  pop;
reg  [ADDR_WIDTH:0]   mOutPtr = 1'b0;
reg                   full_n = 1'b1;
reg                   empty_n = 1'b0;



kernel_kcore_fifo_w64_d128_A_ram
#(
 .DATA_WIDTH(DATA_WIDTH),
 .ADDR_WIDTH(ADDR_WIDTH),
 .DEPTH(DEPTH))
U_kernel_kcore_fifo_w64_d128_A_ram(
 .clk(clk),
 .we(push),
 .waddr(waddr),
 .din(if_din),
 .raddr(rnext),
 .dout(if_dout)
);




assign if_full_n  = full_n;
assign if_empty_n = empty_n;
assign push       = full_n & if_write_ce & if_write;
assign pop        = empty_n & if_read_ce & if_read;
assign wnext      = !push                ? waddr :
                    (waddr == DEPTH - 1) ? 1'b0  :
                    waddr + 1'b1;
assign rnext      = !pop                 ? raddr :
                    (raddr == DEPTH - 1) ? 1'b0  :
                    raddr + 1'b1;


always @(posedge clk) begin
    if (reset == 1'b1)
        waddr <= 1'b0;
    else
        waddr <= wnext;
end


always @(posedge clk) begin
    if (reset == 1'b1)
        raddr <= 1'b0;
    else
        raddr <= rnext;
end


always @(posedge clk) begin
    if (reset == 1'b1)
        mOutPtr <= 1'b0;
    else if (push & ~pop)
        mOutPtr <= mOutPtr + 1'b1;
    else if (~push & pop)
        mOutPtr <= mOutPtr - 1'b1;
end


always @(posedge clk) begin
    if (reset == 1'b1)
        full_n <= 1'b1;
    else if (push & ~pop)
        full_n <= (mOutPtr != DEPTH - 1);
    else if (~push & pop)
        full_n <= 1'b1;
end


always @(posedge clk) begin
    if (reset == 1'b1)
        empty_n <= 1'b0;
    else if (push & ~pop)
        empty_n <= 1'b1;
    else if (~push & pop)
        empty_n <= (mOutPtr != 1'b1);
end

endmodule