data/full_repos/permissive/522145661/Test_Decoder.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_Decoder.v:33: Unsupported: Ignoring delay on this delayed statement.\n always #15  CLK =  ! CLK;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_Decoder.v:36: Unsupported: Ignoring delay on this delayed statement.\n #500 RST = 1;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_Decoder.v:37: Unsupported: Ignoring delay on this delayed statement.\n #50 RST = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_Decoder.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_Decoder.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #150 HADDR = 15\'b000000000000000;RST = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_Decoder.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #150 HADDR = 15\'b010000000000000;RST = 0;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_Decoder.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #150 HADDR = 15\'b100000000000000;RST = 0;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_Decoder.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #150 HADDR = 15\'b110000000000000;RST = 0;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522145661/Test_Decoder.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #150 HADDR = 15\'b000000000000000;RST = 0;\n  ^\n%Error: data/full_repos/permissive/522145661/Test_Decoder.v:23: Cannot find file containing module: \'Decoder\'\n Decoder uut (\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/522145661,data/full_repos/permissive/522145661/Decoder\n             data/full_repos/permissive/522145661,data/full_repos/permissive/522145661/Decoder.v\n             data/full_repos/permissive/522145661,data/full_repos/permissive/522145661/Decoder.sv\n             Decoder\n             Decoder.v\n             Decoder.sv\n             obj_dir/Decoder\n             obj_dir/Decoder.v\n             obj_dir/Decoder.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Test_Decoder;


	reg RST;
	reg CLK;
	reg [14:0] HADDR;


	wire SEL_1;
	wire SEL_2;
	wire SEL_3;
	wire [1:0] SELR;


	Decoder uut (
		.RST(RST), 
		.CLK(CLK), 
		.HADDR(HADDR), 
		.SEL_1(SEL_1), 
		.SEL_2(SEL_2), 
		.SEL_3(SEL_3), 
		.SELR(SELR)
	);
	
	always #15  CLK =  ! CLK;
	
	initial begin
	#500 RST = 1;
	#50 RST = 0;
	end

	initial begin

		RST = 0;
		CLK = 0;
		HADDR = 0;


		#100;
        

		#150 HADDR = 15'b000000000000000;RST = 0;
		#150 HADDR = 15'b010000000000000;RST = 0;
		#150 HADDR = 15'b100000000000000;RST = 0;
		#150 HADDR = 15'b110000000000000;RST = 0;
		#150 HADDR = 15'b000000000000000;RST = 0;
		
	end
	
endmodule
module Test_Decoder;



	reg RST;
	reg CLK;
	reg [14:0] HADDR;


	wire SEL_1;
	wire SEL_2;
	wire SEL_3;
	wire [1:0] SELR;


	Decoder uut (
		.RST(RST), 
		.CLK(CLK), 
		.HADDR(HADDR), 
		.SEL_1(SEL_1), 
		.SEL_2(SEL_2), 
		.SEL_3(SEL_3), 
		.SELR(SELR)
	);
	
	always #15  CLK =  ! CLK;
	
	initial begin
	#500 RST = 1;
	#50 RST = 0;
	end

	initial begin

		RST = 0;
		CLK = 0;
		HADDR = 0;


		#100;
        

		#150 HADDR = 15'b000000000000000;RST = 0;
		#150 HADDR = 15'b010000000000000;RST = 0;
		#150 HADDR = 15'b100000000000000;RST = 0;
		#150 HADDR = 15'b110000000000000;RST = 0;
		#150 HADDR = 15'b000000000000000;RST = 0;
		
	end
	
endmodule