data/full_repos/permissive/490649362/pipeline/src/Forwarding.v
1: b'%Warning-WIDTH: data/full_repos/permissive/490649362/pipeline/src/Forwarding.v:22: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                 : ... In instance Forwarding\n        Forward1 = 1\'b0;\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/490649362/pipeline/src/Forwarding.v:23: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                 : ... In instance Forwarding\n        Forward2 = 1\'b0;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/490649362/pipeline/src/Forwarding.v:29: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'Dst_WB\' generates 5 bits.\n                                                                                 : ... In instance Forwarding\n        else if (RegWrite_WB && Dst_WB && Dst_WB == Rs_EX)\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/490649362/pipeline/src/Forwarding.v:27: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'Dst_MEM\' generates 5 bits.\n                                                                                 : ... In instance Forwarding\n        if (RegWrite_MEM && Dst_MEM && Dst_MEM == Rs_EX)\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/490649362/pipeline/src/Forwarding.v:36: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'Dst_WB\' generates 5 bits.\n                                                                                 : ... In instance Forwarding\n        else if (RegWrite_WB && Dst_WB && Dst_WB == Rt_EX)\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/490649362/pipeline/src/Forwarding.v:34: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'Dst_MEM\' generates 5 bits.\n                                                                                 : ... In instance Forwarding\n        if (RegWrite_MEM && Dst_MEM && Dst_MEM == Rt_EX)\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/490649362/pipeline/src/Forwarding.v:43: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                 : ... In instance Forwarding\n            Forward1 = 1\'b1;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/490649362/pipeline/src/Forwarding.v:45: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                 : ... In instance Forwarding\n            Forward1 = 1\'b0;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/490649362/pipeline/src/Forwarding.v:42: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'Dst_MEM\' generates 5 bits.\n                                                                                 : ... In instance Forwarding\n        if (RegWrite_MEM && Dst_MEM && Dst_MEM == Rs_ID)\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/490649362/pipeline/src/Forwarding.v:48: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                 : ... In instance Forwarding\n            Forward2 = 1\'b1;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/490649362/pipeline/src/Forwarding.v:50: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                 : ... In instance Forwarding\n            Forward2 = 1\'b0;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/490649362/pipeline/src/Forwarding.v:47: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s VARREF \'Dst_MEM\' generates 5 bits.\n                                                                                 : ... In instance Forwarding\n        if (RegWrite_MEM && Dst_MEM && Dst_MEM == Rt_ID)\n                         ^~\n%Error: Exiting due to 12 warning(s)\n'
module Forwarding(
    input       [4:0]   Rs_ID,
                        Rt_ID,
                        Rs_EX,
                        Rt_EX,
                        Dst_MEM,
                        Dst_WB,
    input               RegWrite_MEM,
                        RegWrite_WB,
    output reg  [1:0]   ForwardA,
                        ForwardB,
                        Forward1,
                        Forward2
);

    initial begin
        ForwardA = 2'b00;
        ForwardB = 2'b00;
        Forward1 = 1'b0;
        Forward2 = 1'b0;
    end

    always @(*) begin
        if (RegWrite_MEM && Dst_MEM && Dst_MEM == Rs_EX)
            ForwardA = 2'b10;
        else if (RegWrite_WB && Dst_WB && Dst_WB == Rs_EX)
            ForwardA = 2'b01;
        else
            ForwardA = 2'b00;

        if (RegWrite_MEM && Dst_MEM && Dst_MEM == Rt_EX)
            ForwardB = 2'b10;
        else if (RegWrite_WB && Dst_WB && Dst_WB == Rt_EX)
            ForwardB = 2'b01;
        else
            ForwardB = 2'b00;


        if (RegWrite_MEM && Dst_MEM && Dst_MEM == Rs_ID)
            Forward1 = 1'b1;
        else
            Forward1 = 1'b0;

        if (RegWrite_MEM && Dst_MEM && Dst_MEM == Rt_ID)
            Forward2 = 1'b1;
        else
            Forward2 = 1'b0;
    end

endmodule
module Forwarding(
    input       [4:0]   Rs_ID,
                        Rt_ID,
                        Rs_EX,
                        Rt_EX,
                        Dst_MEM,
                        Dst_WB,
    input               RegWrite_MEM,
                        RegWrite_WB,
    output reg  [1:0]   ForwardA,
                        ForwardB,
                        Forward1,
                        Forward2
);


    initial begin
        ForwardA = 2'b00;
        ForwardB = 2'b00;
        Forward1 = 1'b0;
        Forward2 = 1'b0;
    end

    always @(*) begin
        if (RegWrite_MEM && Dst_MEM && Dst_MEM == Rs_EX)
            ForwardA = 2'b10;
        else if (RegWrite_WB && Dst_WB && Dst_WB == Rs_EX)
            ForwardA = 2'b01;
        else
            ForwardA = 2'b00;

        if (RegWrite_MEM && Dst_MEM && Dst_MEM == Rt_EX)
            ForwardB = 2'b10;
        else if (RegWrite_WB && Dst_WB && Dst_WB == Rt_EX)
            ForwardB = 2'b01;
        else
            ForwardB = 2'b00;


        if (RegWrite_MEM && Dst_MEM && Dst_MEM == Rs_ID)
            Forward1 = 1'b1;
        else
            Forward1 = 1'b0;

        if (RegWrite_MEM && Dst_MEM && Dst_MEM == Rt_ID)
            Forward2 = 1'b1;
        else
            Forward2 = 1'b0;
    end

endmodule