data/full_repos/permissive/435516446/MIPS/MIPS.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/MIPS.v:25: Unsupported: Ignoring delay on this delayed statement.\n always #10 clock = ~clock;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/435516446/MIPS/MIPS.v:140: Cannot find file containing module: \'OpcodeBasedMux2X1\'\n OpcodeBasedMux2X1 OpcodeBasedMux2X1_m(\n ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/OpcodeBasedMux2X1\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/OpcodeBasedMux2X1.v\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/OpcodeBasedMux2X1.sv\n             OpcodeBasedMux2X1\n             OpcodeBasedMux2X1.v\n             OpcodeBasedMux2X1.sv\n             obj_dir/OpcodeBasedMux2X1\n             obj_dir/OpcodeBasedMux2X1.v\n             obj_dir/OpcodeBasedMux2X1.sv\n%Error: data/full_repos/permissive/435516446/MIPS/MIPS.v:150: Cannot find file containing module: \'Fetch\'\n Fetch fetch_m(\n ^~~~~\n%Error: data/full_repos/permissive/435516446/MIPS/MIPS.v:160: Cannot find file containing module: \'IF_ID_Register\'\n IF_ID_Register IDIFRegister_m(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/435516446/MIPS/MIPS.v:171: Cannot find file containing module: \'Decode\'\n Decode decode_m(\n ^~~~~~\n%Error: data/full_repos/permissive/435516446/MIPS/MIPS.v:187: Cannot find file containing module: \'ControlUnit\'\n ControlUnit control_unit_m(\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/435516446/MIPS/MIPS.v:207: Cannot find file containing module: \'ID_EX_Register\'\n ID_EX_Register ID_EX_Register_m(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/435516446/MIPS/MIPS.v:248: Cannot find file containing module: \'Execute\'\n Execute execute_m(\n ^~~~~~~\n%Error: data/full_repos/permissive/435516446/MIPS/MIPS.v:260: Cannot find file containing module: \'ALU\'\n ALU alu_mips_m(\n ^~~\n%Error: data/full_repos/permissive/435516446/MIPS/MIPS.v:269: Cannot find file containing module: \'multiplexer32bit2X1\'\n multiplexer32bit2X1 multiplexer32bit2X1_mips_m(\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/435516446/MIPS/MIPS.v:277: Cannot find file containing module: \'EM_MEM_Register\'\n  EM_MEM_Register em_mem_register_m (\n  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/435516446/MIPS/MIPS.v:307: Cannot find file containing module: \'DataMemory\'\n DataMemory data_memory_m(\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/435516446/MIPS/MIPS.v:321: Cannot find file containing module: \'MEM_WB_Register\'\n MEM_WB_Register MEM_WB_Register_m(\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/435516446/MIPS/MIPS.v:340: Cannot find file containing module: \'WriteBack\'\n WriteBack write_back_m(\n ^~~~~~~~~\n%Error: Exiting due to 13 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module MIPS();


	 reg clock =0;
	always #10 clock = ~clock;
	reg do_not_care = 0;
	wire [31:0] jump_signal=$random; 
	wire [31:0] jump_signal_out=jump_signal; 

	



		wire [31:0] next_pc_from_fetch;
		wire [31:0] instruction_from_fetch;
		wire hit_from_fetch;




		wire [31:0] next_pc_from_IFID;
		wire [31:0] instruction_from_IFID;
		wire hit_from_IFID;



		wire [5:0] opcode_form_decode;
		wire [31:0] read_data1_form_decode;
		wire [31:0] read_data2_form_decode;
		wire [31:0] sign_extended_immediate_form_decode;
		wire [4:0] rt_form_decode;
		wire [4:0] rd_form_decode;



		wire RegDst_from_controlUnit;
		wire ALUSrc_from_controlUnit;
		wire MemtoReg_from_controlUnit;
		wire RegWrite_from_controlUnit;
		wire MemRead_from_controlUnit;
		wire MemWrite_from_controlUnit;
		wire Branch_from_controlUnit;
		wire [5:0] ALUOp_from_controlUnit;




		wire [31:0] readData1Out_from_IDEX;
		wire [31:0] readData2Out_from_IDEX;
		wire [31:0] signExImmediateOut_from_IDEX;
		wire RegDstOut_from_IDEX;
		wire ALUSrcOut_from_IDEX;
		wire MemtoRegOut_from_IDEX;
		wire RegWriteOut_from_IDEX;
		wire MemReadOut_from_IDEX;
		wire MemWriteOut_from_IDEX;
		wire BranchOut_from_IDEX;
		wire [5:0] ALUOpOut_from_IDEX;
		wire [4:0] rtOut_from_IDEX;
		wire [4:0] rdOut_from_IDEX;
		wire [5:0] functOut_from_IDEX;
		wire [31:0] nextPCOut_from_IDEX;
		wire hitOut_from_IDEX;




		wire [31:0] ALUResult_from_Execute;
		wire zero_from_Execute;



		wire [31:0] branchTarget_from_alu_mips_m;



		wire [4:0] writeRegOut_from_mips_multiplexer;



		wire [31:0] branchTargetOut_from_EM_MEM;
		wire zeroFlagOut_from_EM_MEM;
		wire [31:0] ALUResultOut_from_EM_MEM;
		wire [31:0] readData2Out_from_EM_MEM;
		wire [4:0] writeRegOut_from_EM_MEM;
		wire MemReadOut_from_EM_MEM;
		wire MemWriteOut_from_EM_MEM;
		wire BranchOut_from_EM_MEM;
		wire RegWriteOut_from_EM_MEM;
		wire MemToRegOut_from_EM_MEM;
		wire hitOut_from_EM_MEM;




		wire [31:0] readData_from_DataMemory;



		wire pc_source_from_AND;



		wire hitOut_from_MEM_WB;
		wire [31:0] readDataOut_from_MEM_WB;
		wire [31:0] ALUResultOut_from_MEM_WB;
		wire [4:0] writeRegOut_from_MEM_WB;
		wire RegWriteOut_from_MEM_WB;
		wire MemtoRegOut_from_MEM_WB;



		wire [31:0] writeDataOut_from_wirte_back;

	
		wire [5:0] write_reg_MIPS;
		wire [5:0] write_data_MIPS;
	
		
	OpcodeBasedMux2X1 OpcodeBasedMux2X1_m(
		 RegWrite_from_controlUnit,
		 opcode_form_decode,
		 next_pc_from_fetch,
		 writeRegOut_from_MEM_WB,
		 writeDataOut_from_wirte_back,
		 write_reg_MIPS,
		 write_data_MIPS
		 );
		
	Fetch fetch_m(
		clock,
		branchTargetOut_from_EM_MEM,
		pc_source_from_AND,

		next_pc_from_fetch,
		instruction_from_fetch,
		hit_from_fetch
		);
		
	IF_ID_Register IDIFRegister_m(
		clock,
		next_pc_from_fetch,
		instruction_from_fetch,
		hit_from_fetch,
		instruction_from_IFID,
		next_pc_from_IFID,
		hit_from_IFID
		);
		
		
	Decode decode_m(
      clock,
      instruction_from_IFID,
		RegWrite_from_controlUnit,
		write_reg_MIPS,
		wirte_data_MIPS,
		opcode_form_decode,
		read_data1_form_decode,
		read_data2_form_decode,
		sign_extended_immediate_form_decode,
		rt_form_decode,
		rd_form_decode
    );
	 
	
	 
	ControlUnit control_unit_m(
		opcode_form_decode,
		RegDst_from_controlUnit,
		ALUSrc_from_controlUnit,
		MemtoReg_from_controlUnit,
		RegWrite_from_controlUnit,
		MemRead_from_controlUnit,
		MemWrite_from_controlUnit,
		Branch_from_controlUnit,
		ALUOp_from_controlUnit

		);

	ID_EX_Register ID_EX_Register_m(
		 clock,
		 hit_from_IFID,
		 read_data1_form_decode,
		 read_data2_form_decode,
		 sign_extended_immediate_form_decode,
		 RegDst_from_controlUnit,
		 ALUSrc_from_controlUnit,
		 MemtoReg_from_controlUnit,
		 RegWrite_from_controlUnit,
		 MemRead_from_controlUnit,
		 MemWrite_from_controlUnit,
		 Branch_from_controlUnit,
		 {1'b0, ALUOp_from_controlUnit},
		 rt_form_decode,
		 rd_form_decode,
		 sign_extended_immediate_form_decode[5:0],
		 next_pc_from_fetch,
		 jump_signal,
		 readData1Out_from_IDEX,
		 readData2Out_from_IDEX,
		 signExImmediateOut_from_IDEX,
		 RegDstOut_from_IDEX,
		 ALUSrcOut_from_IDEX,
		 MemtoRegOut_from_IDEX,
		 RegWriteOut_from_IDEX,
		 MemReadOut_from_IDEX,
		 MemWriteOut_from_IDEX,
		 BranchOut_from_IDEX,
		 ALUOpOut_from_IDEX,
		 rtOut_from_IDEX,
		 rdOut_from_IDEX,
		 functOut_from_IDEX,
		 nextPCOut_from_IDEX,
		 hitOut_from_IDEX,
		 jump_signal_out
		);
		
		


	Execute execute_m(
		 clock,
		 readData1Out_from_IDEX,
		 readData2Out_from_IDEX,
		 signExImmediateOut_from_IDEX,
		 functOut_from_IDEX,
		 ALUOpOut_from_IDEX,
		 ALUSrcOut_from_IDEX,
		 ALUResult_from_Execute,
		 zero_from_Execute
    );
	 
	ALU alu_mips_m(
	 0,
    nextPCOut_from_IDEX,
    signExImmediateOut_from_IDEX<<1,
    0,
    branchTarget_from_alu_mips_m,
	 do_not_care
	);
	 
	multiplexer32bit2X1 multiplexer32bit2X1_mips_m(
		rtOut_from_IDEX,
		rdOut_from_IDEX,
		RegDstOut_from_IDEX,
		writeRegOut_from_mips_multiplexer
	);


	 EM_MEM_Register em_mem_register_m (
		clock,
		hitOut_from_IDEX,
		branchTarget_from_alu_mips_m,
		zero_from_Execute,
		ALUResult_from_Execute,
		readData2Out_from_IDEX,
		writeRegOut_from_mips_multiplexer,
		MemReadOut_from_IDEX,
		MemWriteOut_from_IDEX,
		BranchOut_from_IDEX,
		RegWriteOut_from_IDEX,
		MemtoRegOut_from_IDEX,
		jump_signal,
		branchTargetOut_from_EM_MEM,
		zeroFlagOut_from_EM_MEM,
		ALUResultOut_from_EM_MEM,
		readData2Out_from_EM_MEM,
		writeRegOut_from_EM_MEM,
		MemReadOut_from_EM_MEM,
		MemWriteOut_from_EM_MEM,
		BranchOut_from_EM_MEM,
		RegWriteOut_from_EM_MEM,
		MemToRegOut_from_EM_MEM,
		hitOut_from_EM_MEM,
		jump_signal_out
	 );



	DataMemory data_memory_m(
		clock, 
		ALUResultOut_from_EM_MEM, 
		readData2Out_from_EM_MEM, 
		MemReadOut_from_EM_MEM, 
		MemWriteOut_from_EM_MEM, 
		readData_from_DataMemory
	);
	
	assign pc_source_from_AND = BranchOut_from_IDEX & zeroFlagOut_from_EM_MEM;
	



	MEM_WB_Register MEM_WB_Register_m(
		clock,
		hitOut_from_IDEX,
		readData_from_DataMemory,
		ALUResultOut_from_EM_MEM,
		writeRegOut_from_EM_MEM,
		RegWriteOut_from_EM_MEM,
		MemToRegOut_from_EM_MEM,
		hitOut_from_MEM_WB,
		readDataOut_from_MEM_WB,
		ALUResultOut_from_MEM_WB,
		writeRegOut_from_MEM_WB,
		RegWriteOut_from_MEM_WB,
		MemtoRegOut_from_MEM_WB
	); 
	



	WriteBack write_back_m(
		ALUResultOut_from_MEM_WB,
		readDataOut_from_MEM_WB,
		MemtoRegOut_from_MEM_WB,
		writeDataOut_from_wirte_back
	);

endmodule
module MIPS();



	 reg clock =0;
	always #10 clock = ~clock;
	reg do_not_care = 0;
	wire [31:0] jump_signal=$random; 
	wire [31:0] jump_signal_out=jump_signal; 

	



		wire [31:0] next_pc_from_fetch;
		wire [31:0] instruction_from_fetch;
		wire hit_from_fetch;




		wire [31:0] next_pc_from_IFID;
		wire [31:0] instruction_from_IFID;
		wire hit_from_IFID;



		wire [5:0] opcode_form_decode;
		wire [31:0] read_data1_form_decode;
		wire [31:0] read_data2_form_decode;
		wire [31:0] sign_extended_immediate_form_decode;
		wire [4:0] rt_form_decode;
		wire [4:0] rd_form_decode;



		wire RegDst_from_controlUnit;
		wire ALUSrc_from_controlUnit;
		wire MemtoReg_from_controlUnit;
		wire RegWrite_from_controlUnit;
		wire MemRead_from_controlUnit;
		wire MemWrite_from_controlUnit;
		wire Branch_from_controlUnit;
		wire [5:0] ALUOp_from_controlUnit;




		wire [31:0] readData1Out_from_IDEX;
		wire [31:0] readData2Out_from_IDEX;
		wire [31:0] signExImmediateOut_from_IDEX;
		wire RegDstOut_from_IDEX;
		wire ALUSrcOut_from_IDEX;
		wire MemtoRegOut_from_IDEX;
		wire RegWriteOut_from_IDEX;
		wire MemReadOut_from_IDEX;
		wire MemWriteOut_from_IDEX;
		wire BranchOut_from_IDEX;
		wire [5:0] ALUOpOut_from_IDEX;
		wire [4:0] rtOut_from_IDEX;
		wire [4:0] rdOut_from_IDEX;
		wire [5:0] functOut_from_IDEX;
		wire [31:0] nextPCOut_from_IDEX;
		wire hitOut_from_IDEX;




		wire [31:0] ALUResult_from_Execute;
		wire zero_from_Execute;



		wire [31:0] branchTarget_from_alu_mips_m;



		wire [4:0] writeRegOut_from_mips_multiplexer;



		wire [31:0] branchTargetOut_from_EM_MEM;
		wire zeroFlagOut_from_EM_MEM;
		wire [31:0] ALUResultOut_from_EM_MEM;
		wire [31:0] readData2Out_from_EM_MEM;
		wire [4:0] writeRegOut_from_EM_MEM;
		wire MemReadOut_from_EM_MEM;
		wire MemWriteOut_from_EM_MEM;
		wire BranchOut_from_EM_MEM;
		wire RegWriteOut_from_EM_MEM;
		wire MemToRegOut_from_EM_MEM;
		wire hitOut_from_EM_MEM;




		wire [31:0] readData_from_DataMemory;



		wire pc_source_from_AND;



		wire hitOut_from_MEM_WB;
		wire [31:0] readDataOut_from_MEM_WB;
		wire [31:0] ALUResultOut_from_MEM_WB;
		wire [4:0] writeRegOut_from_MEM_WB;
		wire RegWriteOut_from_MEM_WB;
		wire MemtoRegOut_from_MEM_WB;



		wire [31:0] writeDataOut_from_wirte_back;

	
		wire [5:0] write_reg_MIPS;
		wire [5:0] write_data_MIPS;
	
		
	OpcodeBasedMux2X1 OpcodeBasedMux2X1_m(
		 RegWrite_from_controlUnit,
		 opcode_form_decode,
		 next_pc_from_fetch,
		 writeRegOut_from_MEM_WB,
		 writeDataOut_from_wirte_back,
		 write_reg_MIPS,
		 write_data_MIPS
		 );
		
	Fetch fetch_m(
		clock,
		branchTargetOut_from_EM_MEM,
		pc_source_from_AND,

		next_pc_from_fetch,
		instruction_from_fetch,
		hit_from_fetch
		);
		
	IF_ID_Register IDIFRegister_m(
		clock,
		next_pc_from_fetch,
		instruction_from_fetch,
		hit_from_fetch,
		instruction_from_IFID,
		next_pc_from_IFID,
		hit_from_IFID
		);
		
		
	Decode decode_m(
      clock,
      instruction_from_IFID,
		RegWrite_from_controlUnit,
		write_reg_MIPS,
		wirte_data_MIPS,
		opcode_form_decode,
		read_data1_form_decode,
		read_data2_form_decode,
		sign_extended_immediate_form_decode,
		rt_form_decode,
		rd_form_decode
    );
	 
	
	 
	ControlUnit control_unit_m(
		opcode_form_decode,
		RegDst_from_controlUnit,
		ALUSrc_from_controlUnit,
		MemtoReg_from_controlUnit,
		RegWrite_from_controlUnit,
		MemRead_from_controlUnit,
		MemWrite_from_controlUnit,
		Branch_from_controlUnit,
		ALUOp_from_controlUnit

		);

	ID_EX_Register ID_EX_Register_m(
		 clock,
		 hit_from_IFID,
		 read_data1_form_decode,
		 read_data2_form_decode,
		 sign_extended_immediate_form_decode,
		 RegDst_from_controlUnit,
		 ALUSrc_from_controlUnit,
		 MemtoReg_from_controlUnit,
		 RegWrite_from_controlUnit,
		 MemRead_from_controlUnit,
		 MemWrite_from_controlUnit,
		 Branch_from_controlUnit,
		 {1'b0, ALUOp_from_controlUnit},
		 rt_form_decode,
		 rd_form_decode,
		 sign_extended_immediate_form_decode[5:0],
		 next_pc_from_fetch,
		 jump_signal,
		 readData1Out_from_IDEX,
		 readData2Out_from_IDEX,
		 signExImmediateOut_from_IDEX,
		 RegDstOut_from_IDEX,
		 ALUSrcOut_from_IDEX,
		 MemtoRegOut_from_IDEX,
		 RegWriteOut_from_IDEX,
		 MemReadOut_from_IDEX,
		 MemWriteOut_from_IDEX,
		 BranchOut_from_IDEX,
		 ALUOpOut_from_IDEX,
		 rtOut_from_IDEX,
		 rdOut_from_IDEX,
		 functOut_from_IDEX,
		 nextPCOut_from_IDEX,
		 hitOut_from_IDEX,
		 jump_signal_out
		);
		
		


	Execute execute_m(
		 clock,
		 readData1Out_from_IDEX,
		 readData2Out_from_IDEX,
		 signExImmediateOut_from_IDEX,
		 functOut_from_IDEX,
		 ALUOpOut_from_IDEX,
		 ALUSrcOut_from_IDEX,
		 ALUResult_from_Execute,
		 zero_from_Execute
    );
	 
	ALU alu_mips_m(
	 0,
    nextPCOut_from_IDEX,
    signExImmediateOut_from_IDEX<<1,
    0,
    branchTarget_from_alu_mips_m,
	 do_not_care
	);
	 
	multiplexer32bit2X1 multiplexer32bit2X1_mips_m(
		rtOut_from_IDEX,
		rdOut_from_IDEX,
		RegDstOut_from_IDEX,
		writeRegOut_from_mips_multiplexer
	);


	 EM_MEM_Register em_mem_register_m (
		clock,
		hitOut_from_IDEX,
		branchTarget_from_alu_mips_m,
		zero_from_Execute,
		ALUResult_from_Execute,
		readData2Out_from_IDEX,
		writeRegOut_from_mips_multiplexer,
		MemReadOut_from_IDEX,
		MemWriteOut_from_IDEX,
		BranchOut_from_IDEX,
		RegWriteOut_from_IDEX,
		MemtoRegOut_from_IDEX,
		jump_signal,
		branchTargetOut_from_EM_MEM,
		zeroFlagOut_from_EM_MEM,
		ALUResultOut_from_EM_MEM,
		readData2Out_from_EM_MEM,
		writeRegOut_from_EM_MEM,
		MemReadOut_from_EM_MEM,
		MemWriteOut_from_EM_MEM,
		BranchOut_from_EM_MEM,
		RegWriteOut_from_EM_MEM,
		MemToRegOut_from_EM_MEM,
		hitOut_from_EM_MEM,
		jump_signal_out
	 );



	DataMemory data_memory_m(
		clock, 
		ALUResultOut_from_EM_MEM, 
		readData2Out_from_EM_MEM, 
		MemReadOut_from_EM_MEM, 
		MemWriteOut_from_EM_MEM, 
		readData_from_DataMemory
	);
	
	assign pc_source_from_AND = BranchOut_from_IDEX & zeroFlagOut_from_EM_MEM;
	



	MEM_WB_Register MEM_WB_Register_m(
		clock,
		hitOut_from_IDEX,
		readData_from_DataMemory,
		ALUResultOut_from_EM_MEM,
		writeRegOut_from_EM_MEM,
		RegWriteOut_from_EM_MEM,
		MemToRegOut_from_EM_MEM,
		hitOut_from_MEM_WB,
		readDataOut_from_MEM_WB,
		ALUResultOut_from_MEM_WB,
		writeRegOut_from_MEM_WB,
		RegWriteOut_from_MEM_WB,
		MemtoRegOut_from_MEM_WB
	); 
	



	WriteBack write_back_m(
		ALUResultOut_from_MEM_WB,
		readDataOut_from_MEM_WB,
		MemtoRegOut_from_MEM_WB,
		writeDataOut_from_wirte_back
	);

endmodule