data/full_repos/permissive/418749135/d_ff.v
data/verilator_xmls/ebba1980-cf8a-4fe3-9e89-0554043633d8.xml
module dff 	( input d,
              input rstn,
              input clk,
              output reg q);

	always @ (posedge clk or negedge rstn)
       if (!rstn)
          q <= 0;
       else
          q <= d;
endmodule
module dff 	( input d,
              input rstn,
              input clk,
              output reg q);


	always @ (posedge clk or negedge rstn)
       if (!rstn)
          q <= 0;
       else
          q <= d;
endmodule