data/full_repos/permissive/423547971/FPGA Projects/Traffic_Controller_Basys3/traffic_controller.v
1: b'%Error: Cannot find file containing module: Projects/Traffic_Controller_Basys3,data/full_repos/permissive/423547971\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/Traffic_Controller_Basys3,data/full_repos/permissive/423547971\n             data/full_repos/permissive/423547971/FPGA/Projects/Traffic_Controller_Basys3,data/full_repos/permissive/423547971.v\n             data/full_repos/permissive/423547971/FPGA/Projects/Traffic_Controller_Basys3,data/full_repos/permissive/423547971.sv\n             Projects/Traffic_Controller_Basys3,data/full_repos/permissive/423547971\n             Projects/Traffic_Controller_Basys3,data/full_repos/permissive/423547971.v\n             Projects/Traffic_Controller_Basys3,data/full_repos/permissive/423547971.sv\n             obj_dir/Projects/Traffic_Controller_Basys3,data/full_repos/permissive/423547971\n             obj_dir/Projects/Traffic_Controller_Basys3,data/full_repos/permissive/423547971.v\n             obj_dir/Projects/Traffic_Controller_Basys3,data/full_repos/permissive/423547971.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: Projects/Traffic_Controller_Basys3/traffic_controller.v\n%Error: Exiting due to 3 error(s)\n'
module traffic_controller(
    input reset,
    input clk_100MHz,       
    output [2:0] main_st,
    output [2:0] cross_st
    );
    
    wire w_1Hz, w_reset;
    
    state_machine sm(.reset(w_reset), .clk_1Hz(w_1Hz), 
                     .main_st(main_st), .cross_st(cross_st));
    oneHz_gen uno(.clk_100MHz(clk_100MHz), .reset(w_reset), .clk_1Hz(w_1Hz));
    sw_debounce db(.clk(clk_100MHz), .btn_in(reset), .btn_out(w_reset) );
    
endmodule
module traffic_controller(
    input reset,
    input clk_100MHz,       
    output [2:0] main_st,
    output [2:0] cross_st
    );

    
    wire w_1Hz, w_reset;
    
    state_machine sm(.reset(w_reset), .clk_1Hz(w_1Hz), 
                     .main_st(main_st), .cross_st(cross_st));
    oneHz_gen uno(.clk_100MHz(clk_100MHz), .reset(w_reset), .clk_1Hz(w_1Hz));
    sw_debounce db(.clk(clk_100MHz), .btn_in(reset), .btn_out(w_reset) );
    
endmodule