data/full_repos/permissive/458134463/Modules/mux8x1.v
1: b"%Error: data/full_repos/permissive/458134463/Modules/mux8x1.v:23: Cannot find file containing module: 'mux2x1'\nmux2x1 mux1(input1, input2, select[0], mux_result_1),\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458134463/Modules,data/full_repos/permissive/458134463/mux2x1\n             data/full_repos/permissive/458134463/Modules,data/full_repos/permissive/458134463/mux2x1.v\n             data/full_repos/permissive/458134463/Modules,data/full_repos/permissive/458134463/mux2x1.sv\n             mux2x1\n             mux2x1.v\n             mux2x1.sv\n             obj_dir/mux2x1\n             obj_dir/mux2x1.v\n             obj_dir/mux2x1.sv\n%Error: data/full_repos/permissive/458134463/Modules/mux8x1.v:29: Cannot find file containing module: 'mux2x1'\nmux2x1 mux5(mux_result_1, mux_result_2, select[1], mux_result_5),\n^~~~~~\n%Error: data/full_repos/permissive/458134463/Modules/mux8x1.v:33: Cannot find file containing module: 'mux2x1'\nmux2x1 mux7(mux_result_5, mux_result_6, select[2], result);\n^~~~~~\n%Error: Exiting due to 3 error(s)\n"
module mux8x1(input1, input2, input3, input4, input5, input6, input7, input8, select, result);

input [2:0] select;
input input1;
input input2;
input input3;
input input4;
input input5;
input input6;
input input7;
input input8;

output result;

wire mux_result_1;
wire mux_result_2;
wire mux_result_3;
wire mux_result_4;
wire mux_result_5;
wire mux_result_6;


mux2x1 mux1(input1, input2, select[0], mux_result_1),
		 mux2(input3, input4, select[0], mux_result_2),
		 mux3(input5, input6, select[0], mux_result_3),
		 mux4(input7, input8, select[0], mux_result_4);
		 

mux2x1 mux5(mux_result_1, mux_result_2, select[1], mux_result_5),
		 mux6(mux_result_3, mux_result_4, select[1], mux_result_6);


mux2x1 mux7(mux_result_5, mux_result_6, select[2], result);

endmodule
module mux8x1(input1, input2, input3, input4, input5, input6, input7, input8, select, result);


input [2:0] select;
input input1;
input input2;
input input3;
input input4;
input input5;
input input6;
input input7;
input input8;

output result;

wire mux_result_1;
wire mux_result_2;
wire mux_result_3;
wire mux_result_4;
wire mux_result_5;
wire mux_result_6;


mux2x1 mux1(input1, input2, select[0], mux_result_1),
		 mux2(input3, input4, select[0], mux_result_2),
		 mux3(input5, input6, select[0], mux_result_3),
		 mux4(input7, input8, select[0], mux_result_4);
		 

mux2x1 mux5(mux_result_1, mux_result_2, select[1], mux_result_5),
		 mux6(mux_result_3, mux_result_4, select[1], mux_result_6);


mux2x1 mux7(mux_result_5, mux_result_6, select[2], result);

endmodule