data/full_repos/permissive/409977083/bcd_to_cathodes.v
data/verilator_xmls/adfe7e4f-cda4-46e8-b8b0-957e155984cc.xml
module bcd_to_cathodes(
	input [3:0] digit,
	input position_pointer_now,
	output reg [7:0] cathode = 0
);

always@ (position_pointer_now)
begin
	if(position_pointer_now == 1)
		cathode[7] = 1'b0;
	else
		cathode[7] = 1'b1;
end

always@ (digit)
	begin
		case(digit)
			4'd0:
				cathode[6:0] = 7'b1000000;
			4'd1:
				cathode[6:0] = 7'b1111001;
			4'd2:
				cathode[6:0] = 7'b0100100;
			4'd3:
				cathode[6:0] = 7'b0110000;
			4'd4:
				cathode[6:0] = 7'b0011001;
			4'd5:
				cathode[6:0] = 7'b0010010;
			4'd6:
				cathode[6:0] = 7'b0000010;
			4'd7:
				cathode[6:0] = 7'b1111000;
			4'd8:
				cathode[6:0] = 7'b0000000;
			4'd9:
				cathode[6:0] = 7'b0010000;
			default:
				cathode[6:0] = 7'b1000000;
		endcase
	end

endmodule
module bcd_to_cathodes(
	input [3:0] digit,
	input position_pointer_now,
	output reg [7:0] cathode = 0
);


always@ (position_pointer_now)
begin
	if(position_pointer_now == 1)
		cathode[7] = 1'b0;
	else
		cathode[7] = 1'b1;
end

always@ (digit)
	begin
		case(digit)
			4'd0:
				cathode[6:0] = 7'b1000000;
			4'd1:
				cathode[6:0] = 7'b1111001;
			4'd2:
				cathode[6:0] = 7'b0100100;
			4'd3:
				cathode[6:0] = 7'b0110000;
			4'd4:
				cathode[6:0] = 7'b0011001;
			4'd5:
				cathode[6:0] = 7'b0010010;
			4'd6:
				cathode[6:0] = 7'b0000010;
			4'd7:
				cathode[6:0] = 7'b1111000;
			4'd8:
				cathode[6:0] = 7'b0000000;
			4'd9:
				cathode[6:0] = 7'b0010000;
			default:
				cathode[6:0] = 7'b1000000;
		endcase
	end

endmodule