data/full_repos/permissive/494148647/src/peripherals/prng/bench/prng_iom_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/494148647/src/peripherals/prng/bench/prng_iom_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n        repeat(2) #10 clk = ~clk;\n                  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/494148647/src/peripherals/prng/bench/prng_iom_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n        forever #10 clk = ~clk;\n                ^\n%Error: data/full_repos/permissive/494148647/src/peripherals/prng/bench/prng_iom_tb.v:79: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("prng_iom_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/494148647/src/peripherals/prng/bench/prng_iom_tb.v:80: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, prng_iom_tb);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/494148647/src/peripherals/prng/bench/prng_iom_tb.v:83: syntax error, unexpected \'@\'\n        @(negedge rst);\n        ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module prng_iom_tb();

    reg clk, rst;

    wire io_addr_strobe, io_read_strobe, io_write_strobe;
    wire [3:0] io_byte_en;
    wire [31:0] io_addr, io_write_data;
    wire [31:0] io_read_data;
    wire io_ready;

    reg [31:0] value;


    prng_iom DUT (
        .clk(clk),
        .rst(rst),
        .io_addr_strobe(io_addr_strobe),
        .io_read_strobe(io_read_strobe),
        .io_write_strobe(io_write_strobe),
        .io_address(io_addr[11:0]),
        .io_byte_enable(io_byte_en),
        .io_write_data(io_write_data),
        .io_read_data(io_read_data),
        .io_ready(io_ready)
    );


    iobus_master_model io (
        .clk(clk),
        .rst(rst),
        .io_addr_strobe(io_addr_strobe),
        .io_read_strobe(io_read_strobe),
        .io_write_strobe(io_write_strobe),
        .io_addr(io_addr),
        .io_byte_en(io_byte_en),
        .io_write_data(io_write_data),
        .io_read_data(io_read_data),
        .io_ready(io_ready)
    );


    initial begin
        clk = 1'b0;
        rst = 1'b1;
        repeat(2) #10 clk = ~clk;
        rst = 1'b0;
        forever #10 clk = ~clk;
    end

    task read_rand;
        input integer count;
        begin: read_rand_block
            integer i;

            io.io_read(`PRNG_SEED_OFFS, value);
            $display("%t: seed = %h", $time, value);

            for (i = 0; i < count; i = i+1) begin
                io.io_read(`PRNG_RAND_OFFS, value);
                $display("%t: rand = %h", $time, value);
            end
        end
    endtask


    initial begin
        $dumpfile("prng_iom_tb.vcd");
        $dumpvars(0, prng_iom_tb);

        value = 32'b0;
        @(negedge rst);
        @(posedge clk);

        read_rand(4);

        io.io_write(`PRNG_SEED_OFFS, 32'b0);
        read_rand(4);

        io.io_write(`PRNG_SEED_OFFS, 32'hdeadbeef);
        read_rand(4);

        io.io_write(`PRNG_SEED_OFFS, 32'hdeadbeef);
        read_rand(4);

        $finish;
    end

endmodule
module prng_iom_tb();


    reg clk, rst;

    wire io_addr_strobe, io_read_strobe, io_write_strobe;
    wire [3:0] io_byte_en;
    wire [31:0] io_addr, io_write_data;
    wire [31:0] io_read_data;
    wire io_ready;

    reg [31:0] value;


    prng_iom DUT (
        .clk(clk),
        .rst(rst),
        .io_addr_strobe(io_addr_strobe),
        .io_read_strobe(io_read_strobe),
        .io_write_strobe(io_write_strobe),
        .io_address(io_addr[11:0]),
        .io_byte_enable(io_byte_en),
        .io_write_data(io_write_data),
        .io_read_data(io_read_data),
        .io_ready(io_ready)
    );


    iobus_master_model io (
        .clk(clk),
        .rst(rst),
        .io_addr_strobe(io_addr_strobe),
        .io_read_strobe(io_read_strobe),
        .io_write_strobe(io_write_strobe),
        .io_addr(io_addr),
        .io_byte_en(io_byte_en),
        .io_write_data(io_write_data),
        .io_read_data(io_read_data),
        .io_ready(io_ready)
    );


    initial begin
        clk = 1'b0;
        rst = 1'b1;
        repeat(2) #10 clk = ~clk;
        rst = 1'b0;
        forever #10 clk = ~clk;
    end

    task read_rand;
        input integer count;
        begin: read_rand_block
            integer i;

            io.io_read(`PRNG_SEED_OFFS, value);
            $display("%t: seed = %h", $time, value);

            for (i = 0; i < count; i = i+1) begin
                io.io_read(`PRNG_RAND_OFFS, value);
                $display("%t: rand = %h", $time, value);
            end
        end
    endtask


    initial begin
        $dumpfile("prng_iom_tb.vcd");
        $dumpvars(0, prng_iom_tb);

        value = 32'b0;
        @(negedge rst);
        @(posedge clk);

        read_rand(4);

        io.io_write(`PRNG_SEED_OFFS, 32'b0);
        read_rand(4);

        io.io_write(`PRNG_SEED_OFFS, 32'hdeadbeef);
        read_rand(4);

        io.io_write(`PRNG_SEED_OFFS, 32'hdeadbeef);
        read_rand(4);

        $finish;
    end

endmodule