data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:111: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:114: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:122: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:126: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:132: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:136: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:142: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:146: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:149: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:152: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:155: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:158: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:161: Unsupported: wait statements\n  wait(done_shake);\n  ^~~~\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:162: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:172: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:175: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:178: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:181: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:184: Unsupported: wait statements\n  wait(done_shake);\n  ^~~~\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:185: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:195: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:198: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:200: Unsupported: wait statements\n    wait(done_copy);\n    ^~~~\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:201: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:204: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:205: Unsupported: wait statements\n            wait(!done_copy);\n            ^~~~\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:206: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:213: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:215: Unsupported: wait statements\n  wait(done_copy);\n  ^~~~\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:216: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:219: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:220: Unsupported: wait statements\n            wait(!done_copy);\n            ^~~~\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:221: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:227: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:229: Unsupported: wait statements\n    wait(done_copy);\n    ^~~~\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:230: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:233: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:234: Unsupported: wait statements\n            wait(!done_copy);\n            ^~~~\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:235: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:243: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:245: Unsupported: wait statements\n    wait(done_copy);\n    ^~~~\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:246: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:249: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:250: Unsupported: wait statements\n            wait(!done_copy);\n            ^~~~\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:251: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:257: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:259: Unsupported: wait statements\n    wait(done_copy);\n    ^~~~\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:260: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:263: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:264: Unsupported: wait statements\n            wait(!done_copy);\n            ^~~~\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/test_bench/tb_kem_keygen.v:265: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_kem_keygen;


	reg clk;
	reg rst;
    reg [1:0] saber_type;
	reg [9:0] address_ext;
	reg [63:0] dina_ext;
	reg wea_ext;
	reg [34:0] command_in;
	reg command_we0;
	reg command_we1;


	wire [63:0] doutb_ext;
	wire done_shake;
	wire done_vmul;
	wire done_addround;
	wire done_addpack;
	wire done_bs2polvecp;
	wire done_unpack;
	wire done_copy;
	wire done_sampler;
    wire done_verify;
    wire done_cmov;
    wire done_timer;
    

	reg [63:0] random_seed[3:0];
	reg [63:0] random_noiseseed[3:0];
	reg [63:0] pseudo_random[3:0];
	reg [9:0] i;
	

	ComputeCore3 uut (
		.clk(clk), 
		.rst(rst),

		.address_ext(address_ext), 
		.dina_ext(dina_ext), 
		.wea_ext(wea_ext), 
		.command_in(command_in), 
		.command_we0(command_we0), 
		.command_we1(command_we1), 
		.doutb_ext(doutb_ext),
		.done_shake(done_shake), 
		.done_vmul(done_vmul), 
		.done_addround(done_addround), 
		.done_addpack(done_addpack), 
		.done_bs2polvecp(done_bs2polvecp), 
		.done_unpack(done_unpack),
		.done_copy(done_copy),
		.done_sampler(done_sampler),
		.done_verify(done_verify),
        .done_cmov(done_cmov),
        .done_timer(done_timer)        		
	);

	initial begin

		clk = 0;
		rst = 1;
        saber_type = 2'd2;
		address_ext = 0;
		dina_ext = 0;
		wea_ext = 0;
		command_in = 0;
		command_we0 = 0;
		command_we1 = 0;
	
		random_seed[0] = 64'h5e8c154d23501506;
        random_seed[1] = 64'h257aef04fe9555c9;
        random_seed[2] = 64'h79c42bcc242e7f76;
        random_seed[3] = 64'he7fdbc9adc869dd0;
        
        random_noiseseed[0] = 64'hff6da38dbcbc9f1a;
        random_noiseseed[1] = 64'hdb0f17963220be2a;
        random_noiseseed[2] = 64'h79b6fc677f29c397;
        random_noiseseed[3] = 64'hb05302d09f9c71ac;
        
        pseudo_random[0] = 64'hc4105f43f504f0b2;
		pseudo_random[1] = 64'h9bfd7a44481145cd;
		pseudo_random[2] = 64'h3ad0e00d7709b299;
		pseudo_random[3] = 64'h8c6871e56bbcb7cd;


		#100;
        rst = 0;        

		@(posedge clk)
		command_in = 35'd0;
		command_we0 = 1; command_we1 = 0;



		for(i=0; i<4; i=i+1)
		begin
			@(posedge clk);
			address_ext = i; dina_ext = random_seed[i]; wea_ext = 1;
			$display("i=%d din=%h\n", i, dina_ext);
		end
		@(posedge clk);
		address_ext = 0; dina_ext = 0; wea_ext = 0;


		for(i=0; i<4; i=i+1)
		begin
			@(posedge clk);
			address_ext = i+4; dina_ext = random_noiseseed[i]; wea_ext = 1;
			$display("i=%d din=%h\n", i, dina_ext);
		end
		@(posedge clk);
		address_ext = 0; dina_ext = 0; wea_ext = 0;
		

		for(i=0; i<4; i=i+1)
		begin
			@(posedge clk);
			address_ext = i+768; dina_ext = pseudo_random[i]; wea_ext = 1;
			$display("i=%d din=%h\n", i, dina_ext);
		end
		@(posedge clk);
		address_ext = 0; dina_ext = 0; wea_ext = 0;
		
		@(posedge clk)
		command_in = {3'd0,16'd32,16'd32};
		command_we0 = 0; command_we1 = 1;
		@(posedge clk)
		command_in = {10'd0,10'd0,10'd0,5'd0};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_in = {10'd896,10'd0,10'd0,5'd3};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_we0 = 0; command_we1 = 0;

		wait(done_shake);
			@(posedge clk);
			
		@(posedge clk)
		command_in = 35'd0;
		command_we0 = 1; command_we1 = 0;
		
		

        

		@(posedge clk)
		command_in = {3'd0,16'd3744,16'd32};
		command_we0 = 0; command_we1 = 1;
		@(posedge clk)
		command_in = {10'd100,10'd0,10'd896,5'd0};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_in = {10'd100,10'd0,10'd896,5'd3};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_we0 = 0; command_we1 = 0;

		wait(done_shake);
			@(posedge clk);
			
		@(posedge clk)
		command_in = 35'd0;
		command_we0 = 1; command_we1 = 0;

		

		

		@(posedge clk)
		command_in = {10'd568,10'd52,10'd152,5'd12};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_we0 = 0; command_we1 = 0;
		  wait(done_copy);
		@(posedge clk);
        command_in = {10'd0,10'd0,10'd0,5'd0};
        command_we0 = 1; command_we1 = 0;
        @(posedge clk);
            wait(!done_copy);
        @(posedge clk);
            
			

		@(posedge clk)
		command_in = {10'd152,10'd52,10'd256,5'd12};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_we0 = 0; command_we1 = 0;
		wait(done_copy);
		@(posedge clk);
        command_in = {10'd0,10'd0,10'd0,5'd0};
        command_we0 = 1; command_we1 = 0;
        @(posedge clk);
            wait(!done_copy);
        @(posedge clk);
		

		@(posedge clk)
		command_in = {10'd256,10'd52,10'd568,5'd12};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_we0 = 0; command_we1 = 0;
		  wait(done_copy);
		@(posedge clk);
        command_in = {10'd0,10'd0,10'd0,5'd0};
        command_we0 = 1; command_we1 = 0;
        @(posedge clk);
            wait(!done_copy);
        @(posedge clk);
			
			
			

		@(posedge clk)
		command_in = {10'd568,10'd52,10'd204,5'd12};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_we0 = 0; command_we1 = 0;
		  wait(done_copy);
		@(posedge clk);
        command_in = {10'd0,10'd0,10'd0,5'd0};
        command_we0 = 1; command_we1 = 0;
        @(posedge clk);
            wait(!done_copy);
        @(posedge clk);
			

		@(posedge clk)
		command_in = {10'd204,10'd52,10'd412,5'd12};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_we0 = 0; command_we1 = 0;
		  wait(done_copy);
		@(posedge clk);
        command_in = {10'd0,10'd0,10'd0,5'd0};
        command_we0 = 1; command_we1 = 0;
        @(posedge clk);
            wait(!done_copy);
        @(posedge clk);
		

		@(posedge clk)
		command_in = {10'd412,10'd52,10'd568,5'd12};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_we0 = 0; command_we1 = 0;
		  wait(done_copy);
		@(posedge clk);
        command_in = {10'd0,10'd0,10'd0,5'd0};
        command_we0 = 1; command_we1 = 0;
        @(posedge clk);
            wait(!done_copy);
        @(posedge clk);
			
			
			

		@(posedge clk)
		command_in = {10'd568,10'd52,10'd360,5'd12};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_we0 = 0; command_we1 = 0;
		  wait(done_copy);
		@(posedge clk);
        command_in = {10'd0,10'd0,10'd0,5'd0};
        command_we0 = 1; command_we1 = 0;
        @(posedge clk);
            wait(!done_copy);
        @(posedge clk);
			

		@(posedge clk)
		command_in = {10'd360,10'd52,10'd464,5'd12};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_we0 = 0; command_we1 = 0;
        	wait(done_copy);
		@(posedge clk);
        command_in = {10'd0,10'd0,10'd0,5'd0};
        command_we0 = 1; command_we1 = 0;
        @(posedge clk);
            wait(!done_copy);
        @(posedge clk);
		

		@(posedge clk)
		command_in = {10'd464,10'd52,10'd568,5'd12};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_we0 = 0; command_we1 = 0;
		  wait(done_copy);
		@(posedge clk);
        command_in = {10'd0,10'd0,10'd0,5'd0};
        command_we0 = 1; command_we1 = 0;
        @(posedge clk);
            wait(!done_copy);
        @(posedge clk);
		

		
		


		@(posedge clk)
		command_in = {3'd0,16'd768,16'd32};
		command_we0 = 0; command_we1 = 1;
		@(posedge clk)
		command_in = {10'd0,10'd0,10'd0,5'd0};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_in = {10'd900,10'd0,10'd4,5'd3};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_we0 = 0; command_we1 = 0;

		wait(done_shake);
			@(posedge clk);
			
		@(posedge clk)
		command_in = 35'd0;
		command_we0 = 1; command_we1 = 0;



		@(posedge clk)
		command_in = {10'd900,10'd0,10'd900,5'd13};
		command_we0 = 1; command_we1 = 0;
		wait(done_sampler);
			@(posedge clk);
		@(posedge clk)
		command_in = {10'd0,10'd0,10'd0,5'd0};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk);
		wait(!done_sampler);
		@(posedge clk);








		@(posedge clk)
		command_in = {10'd100,10'd900,10'd100,5'd6};
		command_we0 = 1; command_we1 = 0;
		wait(done_vmul);
			@(posedge clk);
		@(posedge clk)
		command_in = {10'd0,10'd0,10'd0,5'd0};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk);
		wait(!done_vmul);
		@(posedge clk);
		

		@(posedge clk)
		command_in = {10'd164,10'd900,10'd256,5'd6};
		command_we0 = 1; command_we1 = 0;
		wait(done_vmul);
			@(posedge clk);
		@(posedge clk)
		command_in = {10'd0,10'd0,10'd0,5'd0};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk);
		wait(!done_vmul);
		@(posedge clk);


		@(posedge clk)
		command_in = {10'd228,10'd900,10'd412,5'd6};
		command_we0 = 1; command_we1 = 0;
		wait(done_vmul);
			@(posedge clk);
		@(posedge clk)
		command_in = {10'd0,10'd0,10'd0,5'd0};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk);
		wait(!done_vmul);
		@(posedge clk);



		@(posedge clk)
		command_in = {10'd776,10'd0,10'd100,5'd7};
		command_we0 = 1; command_we1 = 0;
		wait(done_addround);
			@(posedge clk);
		@(posedge clk)
		command_in = {10'd0,10'd0,10'd0,5'd0};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk);
		wait(!done_addround);
		@(posedge clk);



		@(posedge clk)
		command_in = {3'd0,16'd32,16'd992};
		command_we0 = 0; command_we1 = 1;
		@(posedge clk)
		command_in = {10'd772,10'd0,10'd776,5'd0};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_in = {10'd772,10'd0,10'd776,5'd1};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_we0 = 0; command_we1 = 0;

		wait(done_shake);
			@(posedge clk);
			
		@(posedge clk)
		command_in = 35'd0;
		command_we0 = 1; command_we1 = 0;
		
		



		

	end
   always #5 clk = ~clk;
      
endmodule
module tb_kem_keygen;



	reg clk;
	reg rst;
    reg [1:0] saber_type;
	reg [9:0] address_ext;
	reg [63:0] dina_ext;
	reg wea_ext;
	reg [34:0] command_in;
	reg command_we0;
	reg command_we1;


	wire [63:0] doutb_ext;
	wire done_shake;
	wire done_vmul;
	wire done_addround;
	wire done_addpack;
	wire done_bs2polvecp;
	wire done_unpack;
	wire done_copy;
	wire done_sampler;
    wire done_verify;
    wire done_cmov;
    wire done_timer;
    

	reg [63:0] random_seed[3:0];
	reg [63:0] random_noiseseed[3:0];
	reg [63:0] pseudo_random[3:0];
	reg [9:0] i;
	

	ComputeCore3 uut (
		.clk(clk), 
		.rst(rst),

		.address_ext(address_ext), 
		.dina_ext(dina_ext), 
		.wea_ext(wea_ext), 
		.command_in(command_in), 
		.command_we0(command_we0), 
		.command_we1(command_we1), 
		.doutb_ext(doutb_ext),
		.done_shake(done_shake), 
		.done_vmul(done_vmul), 
		.done_addround(done_addround), 
		.done_addpack(done_addpack), 
		.done_bs2polvecp(done_bs2polvecp), 
		.done_unpack(done_unpack),
		.done_copy(done_copy),
		.done_sampler(done_sampler),
		.done_verify(done_verify),
        .done_cmov(done_cmov),
        .done_timer(done_timer)        		
	);

	initial begin

		clk = 0;
		rst = 1;
        saber_type = 2'd2;
		address_ext = 0;
		dina_ext = 0;
		wea_ext = 0;
		command_in = 0;
		command_we0 = 0;
		command_we1 = 0;
	
		random_seed[0] = 64'h5e8c154d23501506;
        random_seed[1] = 64'h257aef04fe9555c9;
        random_seed[2] = 64'h79c42bcc242e7f76;
        random_seed[3] = 64'he7fdbc9adc869dd0;
        
        random_noiseseed[0] = 64'hff6da38dbcbc9f1a;
        random_noiseseed[1] = 64'hdb0f17963220be2a;
        random_noiseseed[2] = 64'h79b6fc677f29c397;
        random_noiseseed[3] = 64'hb05302d09f9c71ac;
        
        pseudo_random[0] = 64'hc4105f43f504f0b2;
		pseudo_random[1] = 64'h9bfd7a44481145cd;
		pseudo_random[2] = 64'h3ad0e00d7709b299;
		pseudo_random[3] = 64'h8c6871e56bbcb7cd;


		#100;
        rst = 0;        

		@(posedge clk)
		command_in = 35'd0;
		command_we0 = 1; command_we1 = 0;



		for(i=0; i<4; i=i+1)
		begin
			@(posedge clk);
			address_ext = i; dina_ext = random_seed[i]; wea_ext = 1;
			$display("i=%d din=%h\n", i, dina_ext);
		end
		@(posedge clk);
		address_ext = 0; dina_ext = 0; wea_ext = 0;


		for(i=0; i<4; i=i+1)
		begin
			@(posedge clk);
			address_ext = i+4; dina_ext = random_noiseseed[i]; wea_ext = 1;
			$display("i=%d din=%h\n", i, dina_ext);
		end
		@(posedge clk);
		address_ext = 0; dina_ext = 0; wea_ext = 0;
		

		for(i=0; i<4; i=i+1)
		begin
			@(posedge clk);
			address_ext = i+768; dina_ext = pseudo_random[i]; wea_ext = 1;
			$display("i=%d din=%h\n", i, dina_ext);
		end
		@(posedge clk);
		address_ext = 0; dina_ext = 0; wea_ext = 0;
		
		@(posedge clk)
		command_in = {3'd0,16'd32,16'd32};
		command_we0 = 0; command_we1 = 1;
		@(posedge clk)
		command_in = {10'd0,10'd0,10'd0,5'd0};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_in = {10'd896,10'd0,10'd0,5'd3};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_we0 = 0; command_we1 = 0;

		wait(done_shake);
			@(posedge clk);
			
		@(posedge clk)
		command_in = 35'd0;
		command_we0 = 1; command_we1 = 0;
		
		

        

		@(posedge clk)
		command_in = {3'd0,16'd3744,16'd32};
		command_we0 = 0; command_we1 = 1;
		@(posedge clk)
		command_in = {10'd100,10'd0,10'd896,5'd0};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_in = {10'd100,10'd0,10'd896,5'd3};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_we0 = 0; command_we1 = 0;

		wait(done_shake);
			@(posedge clk);
			
		@(posedge clk)
		command_in = 35'd0;
		command_we0 = 1; command_we1 = 0;

		

		

		@(posedge clk)
		command_in = {10'd568,10'd52,10'd152,5'd12};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_we0 = 0; command_we1 = 0;
		  wait(done_copy);
		@(posedge clk);
        command_in = {10'd0,10'd0,10'd0,5'd0};
        command_we0 = 1; command_we1 = 0;
        @(posedge clk);
            wait(!done_copy);
        @(posedge clk);
            
			

		@(posedge clk)
		command_in = {10'd152,10'd52,10'd256,5'd12};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_we0 = 0; command_we1 = 0;
		wait(done_copy);
		@(posedge clk);
        command_in = {10'd0,10'd0,10'd0,5'd0};
        command_we0 = 1; command_we1 = 0;
        @(posedge clk);
            wait(!done_copy);
        @(posedge clk);
		

		@(posedge clk)
		command_in = {10'd256,10'd52,10'd568,5'd12};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_we0 = 0; command_we1 = 0;
		  wait(done_copy);
		@(posedge clk);
        command_in = {10'd0,10'd0,10'd0,5'd0};
        command_we0 = 1; command_we1 = 0;
        @(posedge clk);
            wait(!done_copy);
        @(posedge clk);
			
			
			

		@(posedge clk)
		command_in = {10'd568,10'd52,10'd204,5'd12};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_we0 = 0; command_we1 = 0;
		  wait(done_copy);
		@(posedge clk);
        command_in = {10'd0,10'd0,10'd0,5'd0};
        command_we0 = 1; command_we1 = 0;
        @(posedge clk);
            wait(!done_copy);
        @(posedge clk);
			

		@(posedge clk)
		command_in = {10'd204,10'd52,10'd412,5'd12};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_we0 = 0; command_we1 = 0;
		  wait(done_copy);
		@(posedge clk);
        command_in = {10'd0,10'd0,10'd0,5'd0};
        command_we0 = 1; command_we1 = 0;
        @(posedge clk);
            wait(!done_copy);
        @(posedge clk);
		

		@(posedge clk)
		command_in = {10'd412,10'd52,10'd568,5'd12};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_we0 = 0; command_we1 = 0;
		  wait(done_copy);
		@(posedge clk);
        command_in = {10'd0,10'd0,10'd0,5'd0};
        command_we0 = 1; command_we1 = 0;
        @(posedge clk);
            wait(!done_copy);
        @(posedge clk);
			
			
			

		@(posedge clk)
		command_in = {10'd568,10'd52,10'd360,5'd12};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_we0 = 0; command_we1 = 0;
		  wait(done_copy);
		@(posedge clk);
        command_in = {10'd0,10'd0,10'd0,5'd0};
        command_we0 = 1; command_we1 = 0;
        @(posedge clk);
            wait(!done_copy);
        @(posedge clk);
			

		@(posedge clk)
		command_in = {10'd360,10'd52,10'd464,5'd12};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_we0 = 0; command_we1 = 0;
        	wait(done_copy);
		@(posedge clk);
        command_in = {10'd0,10'd0,10'd0,5'd0};
        command_we0 = 1; command_we1 = 0;
        @(posedge clk);
            wait(!done_copy);
        @(posedge clk);
		

		@(posedge clk)
		command_in = {10'd464,10'd52,10'd568,5'd12};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_we0 = 0; command_we1 = 0;
		  wait(done_copy);
		@(posedge clk);
        command_in = {10'd0,10'd0,10'd0,5'd0};
        command_we0 = 1; command_we1 = 0;
        @(posedge clk);
            wait(!done_copy);
        @(posedge clk);
		

		
		


		@(posedge clk)
		command_in = {3'd0,16'd768,16'd32};
		command_we0 = 0; command_we1 = 1;
		@(posedge clk)
		command_in = {10'd0,10'd0,10'd0,5'd0};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_in = {10'd900,10'd0,10'd4,5'd3};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_we0 = 0; command_we1 = 0;

		wait(done_shake);
			@(posedge clk);
			
		@(posedge clk)
		command_in = 35'd0;
		command_we0 = 1; command_we1 = 0;



		@(posedge clk)
		command_in = {10'd900,10'd0,10'd900,5'd13};
		command_we0 = 1; command_we1 = 0;
		wait(done_sampler);
			@(posedge clk);
		@(posedge clk)
		command_in = {10'd0,10'd0,10'd0,5'd0};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk);
		wait(!done_sampler);
		@(posedge clk);








		@(posedge clk)
		command_in = {10'd100,10'd900,10'd100,5'd6};
		command_we0 = 1; command_we1 = 0;
		wait(done_vmul);
			@(posedge clk);
		@(posedge clk)
		command_in = {10'd0,10'd0,10'd0,5'd0};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk);
		wait(!done_vmul);
		@(posedge clk);
		

		@(posedge clk)
		command_in = {10'd164,10'd900,10'd256,5'd6};
		command_we0 = 1; command_we1 = 0;
		wait(done_vmul);
			@(posedge clk);
		@(posedge clk)
		command_in = {10'd0,10'd0,10'd0,5'd0};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk);
		wait(!done_vmul);
		@(posedge clk);


		@(posedge clk)
		command_in = {10'd228,10'd900,10'd412,5'd6};
		command_we0 = 1; command_we1 = 0;
		wait(done_vmul);
			@(posedge clk);
		@(posedge clk)
		command_in = {10'd0,10'd0,10'd0,5'd0};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk);
		wait(!done_vmul);
		@(posedge clk);



		@(posedge clk)
		command_in = {10'd776,10'd0,10'd100,5'd7};
		command_we0 = 1; command_we1 = 0;
		wait(done_addround);
			@(posedge clk);
		@(posedge clk)
		command_in = {10'd0,10'd0,10'd0,5'd0};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk);
		wait(!done_addround);
		@(posedge clk);



		@(posedge clk)
		command_in = {3'd0,16'd32,16'd992};
		command_we0 = 0; command_we1 = 1;
		@(posedge clk)
		command_in = {10'd772,10'd0,10'd776,5'd0};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_in = {10'd772,10'd0,10'd776,5'd1};
		command_we0 = 1; command_we1 = 0;
		@(posedge clk)
		command_we0 = 0; command_we1 = 0;

		wait(done_shake);
			@(posedge clk);
			
		@(posedge clk)
		command_in = 35'd0;
		command_we0 = 1; command_we1 = 0;
		
		



		

	end
   always #5 clk = ~clk;
      
endmodule