data/full_repos/permissive/48695884/test_mandlbrot_iter.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/48695884/test_mandlbrot_iter.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/48695884/test_mandlbrot_iter.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48695884/test_mandlbrot_iter.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Error: data/full_repos/permissive/48695884/test_mandlbrot_iter.v:11: Cannot find file containing module: \'mandelbrot_iter\'\nmandelbrot_iter m(in_real, in_imag, c_real, c_imag, out_real, out_imag, size_square);\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/48695884,data/full_repos/permissive/48695884/mandelbrot_iter\n             data/full_repos/permissive/48695884,data/full_repos/permissive/48695884/mandelbrot_iter.v\n             data/full_repos/permissive/48695884,data/full_repos/permissive/48695884/mandelbrot_iter.sv\n             mandelbrot_iter\n             mandelbrot_iter.v\n             mandelbrot_iter.sv\n             obj_dir/mandelbrot_iter\n             obj_dir/mandelbrot_iter.v\n             obj_dir/mandelbrot_iter.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_mandelbrot_iter;

reg  signed [31:0] in_real;
reg  signed [31:0] in_imag;
reg  signed [31:0] c_real;
reg  signed [31:0] c_imag;
wire signed [31:0] out_real;
wire signed [31:0] out_imag;
wire signed [31:0] size_square;

mandelbrot_iter m(in_real, in_imag, c_real, c_imag, out_real, out_imag, size_square);

initial 
  begin 
    #5
	 in_real = 0;
	 in_imag = 0;
	 c_real  = 0;
	 c_imag  = 0;
	 
	 #5
	 in_real = 32'h7ae14;
	 in_imag = 32'h599999;
	 c_real  = 32'h800000;
	 c_imag  = 32'h1062;
	 
	 #5
	 in_real = 32'hfff851ec;
	 in_imag = 32'hffa66667;
	 c_real  = 32'h800000;
	 c_imag  = 32'hffffef9e;
	end
	
endmodule
module test_mandelbrot_iter;


reg  signed [31:0] in_real;
reg  signed [31:0] in_imag;
reg  signed [31:0] c_real;
reg  signed [31:0] c_imag;
wire signed [31:0] out_real;
wire signed [31:0] out_imag;
wire signed [31:0] size_square;

mandelbrot_iter m(in_real, in_imag, c_real, c_imag, out_real, out_imag, size_square);

initial 
  begin 
    #5
	 in_real = 0;
	 in_imag = 0;
	 c_real  = 0;
	 c_imag  = 0;
	 
	 #5
	 in_real = 32'h7ae14;
	 in_imag = 32'h599999;
	 c_real  = 32'h800000;
	 c_imag  = 32'h1062;
	 
	 #5
	 in_real = 32'hfff851ec;
	 in_imag = 32'hffa66667;
	 c_real  = 32'h800000;
	 c_imag  = 32'hffffef9e;
	end
	
endmodule