data/full_repos/permissive/512700783/Mips.v
1: b'%Error: data/full_repos/permissive/512700783/Mips.v:1: Cannot find include file: ALU.v\n`include "ALU.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/512700783,data/full_repos/permissive/512700783/ALU.v\n             data/full_repos/permissive/512700783,data/full_repos/permissive/512700783/ALU.v.v\n             data/full_repos/permissive/512700783,data/full_repos/permissive/512700783/ALU.v.sv\n             ALU.v\n             ALU.v.v\n             ALU.v.sv\n             obj_dir/ALU.v\n             obj_dir/ALU.v.v\n             obj_dir/ALU.v.sv\n%Error: data/full_repos/permissive/512700783/Mips.v:2: Cannot find include file: ALU_control_unit.v\n`include "ALU_control_unit.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/512700783/Mips.v:3: Cannot find include file: Instruction_Memory.v\n`include "Instruction_Memory.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/512700783/Mips.v:4: Cannot find include file: Registers.v\n`include "Registers.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/512700783/Mips.v:5: Cannot find include file: Data_Memory.v\n`include "Data_Memory.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/512700783/Mips.v:6: Cannot find include file: Control_unit.v\n`include "Control_unit.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/512700783/Mips.v:7: Cannot find include file: Mux.v\n`include "Mux.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/512700783/Mips.v:8: Cannot find include file: Sign_extender.v\n`include "Sign_extender.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/512700783/Mips.v:9: Cannot find include file: Mux_5_bit.v\n`include "Mux_5_bit.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/512700783/Mips.v:10: Cannot find include file: PC.v\n`include "PC.v" \n         ^~~~~~\n%Error: Exiting due to 10 error(s)\n'
module Mips(clk);
	wire Jump, PC_Src;
	wire [31:0] PC_jump, PC_branch, PC_mux_1_2;
	wire [31:0] PC_1, PC_2;
	wire [31:0] PC_plus_4;
	wire [27:0] PC_slt;
	wire [31:0] Instr;
	wire [31:0] Sign_imm;
	wire [31:0] Sign_imm_mux;

	wire Reg_write, Reg_dst, ALU_src, Branch, Mem_write, Mem_reg;
	wire [1:0] ALU_Op;
	wire [4:0] Write_reg;
	wire [2:0] ALU_control_wire;

	wire [31:0] Src_A, Write_data;

	wire Zero;
	wire [31:0] Src_B, ALU_result;

	wire [31:0] Read_data;

	wire [31:0] Result;
	input clk;
	reg [31:0] Reg;
	Instruction_Memory instr_mem_unit (
    		.A(PC_2),
    		.RD(Instr)
	);
	Registers register_file_unit (
    		.RD1(Src_A),
    		.RD2(Write_data),
    		.A3(Write_reg),      
    		.WE3(Reg_write),
    		.WD3(Result),
    		.A1(Instr[25:21]),
    		.A2(Instr[20:16])
	);
	Control_unit control_unit (
    		.Op(Instr[31:26]),
    		.Mem_reg(Mem_reg),
    		.Mem_write(Mem_write),
    		.Branch(Branch),            
    		.ALU_Op(ALU_Op),
    		.ALU_src(ALU_src),
    		.Reg_dst(Reg_dst),
    		.Reg_write(Reg_write),
    		.Jump(Jump),                
    		.Clk(clk)
	);
	ALU_control_unit alu_control_unit (
    		.ALU_Op(ALU_Op),
    		.Function(Instr[5:0]),
    		.ALU_control(ALU_control_wire)
	);
	ALU alu_unit (
    		.SrcA(Src_A),
    		.SrcB(Src_B),
    		.ALUSec(ALU_control_wire),
    		.Zero(Zero),            
    		.ALU_result(ALU_result)
	);
	Data_memory data_mem_unit (
    		.A(ALU_result),
    		.WD(Write_data),
    		.WE(Mem_write),
    		.RD(Read_data)
	);
	Sign_extender uut5 (
    		.In(Instr[15:0]),
    		.Out(Sign_imm)
	);

	Mux uut6(               
    		.In1(PC_plus_4),
    		.In2(PC_branch),
    		.Out(PC_mux_1_2),
    		.Sel(PC_Src)
	);

	Mux uut7(               
    		.In1(PC_mux_1_2),
    		.In2(PC_jump),
    		.Out(PC_1),
    		.Sel(Jump)
	);

	Mux uut8(               
    		.In1(Write_data),
    		.In2(Sign_imm),
    		.Out(Src_B),
    		.Sel(ALU_src)
	);

	Mux_5_bit uut9 (        
    		.In1(Instr[20:16]),
    		.In2(Instr[15:11]),
    		.Out(Write_reg),
    		.Sel(Reg_dst)
	);

	Mux uut10(              
    		.In1(ALU_result),
    		.In2(Read_data),
    		.Out(Result),
    		.Sel(Mem_reg)
	);
	PC pc_unit(
    		.In(PC_1),
    		.Out(PC_2),
    		.Clk(clk)
	);
	assign PC_plus_4 = PC_2 + 4;
	assign PC_branch = PC_plus_4+(Sign_imm << 2);
	assign PC_slt = Instr << 2;
	assign PC_jump = {PC_plus_4[31:28],PC_slt};
	assign PC_Src = (Branch & Zero);
endmodule
module Mips(clk);

	wire Jump, PC_Src;
	wire [31:0] PC_jump, PC_branch, PC_mux_1_2;
	wire [31:0] PC_1, PC_2;
	wire [31:0] PC_plus_4;
	wire [27:0] PC_slt;
	wire [31:0] Instr;
	wire [31:0] Sign_imm;
	wire [31:0] Sign_imm_mux;

	wire Reg_write, Reg_dst, ALU_src, Branch, Mem_write, Mem_reg;
	wire [1:0] ALU_Op;
	wire [4:0] Write_reg;
	wire [2:0] ALU_control_wire;

	wire [31:0] Src_A, Write_data;

	wire Zero;
	wire [31:0] Src_B, ALU_result;

	wire [31:0] Read_data;

	wire [31:0] Result;
	input clk;
	reg [31:0] Reg;
	Instruction_Memory instr_mem_unit (
    		.A(PC_2),
    		.RD(Instr)
	);
	Registers register_file_unit (
    		.RD1(Src_A),
    		.RD2(Write_data),
    		.A3(Write_reg),      
    		.WE3(Reg_write),
    		.WD3(Result),
    		.A1(Instr[25:21]),
    		.A2(Instr[20:16])
	);
	Control_unit control_unit (
    		.Op(Instr[31:26]),
    		.Mem_reg(Mem_reg),
    		.Mem_write(Mem_write),
    		.Branch(Branch),            
    		.ALU_Op(ALU_Op),
    		.ALU_src(ALU_src),
    		.Reg_dst(Reg_dst),
    		.Reg_write(Reg_write),
    		.Jump(Jump),                
    		.Clk(clk)
	);
	ALU_control_unit alu_control_unit (
    		.ALU_Op(ALU_Op),
    		.Function(Instr[5:0]),
    		.ALU_control(ALU_control_wire)
	);
	ALU alu_unit (
    		.SrcA(Src_A),
    		.SrcB(Src_B),
    		.ALUSec(ALU_control_wire),
    		.Zero(Zero),            
    		.ALU_result(ALU_result)
	);
	Data_memory data_mem_unit (
    		.A(ALU_result),
    		.WD(Write_data),
    		.WE(Mem_write),
    		.RD(Read_data)
	);
	Sign_extender uut5 (
    		.In(Instr[15:0]),
    		.Out(Sign_imm)
	);

	Mux uut6(               
    		.In1(PC_plus_4),
    		.In2(PC_branch),
    		.Out(PC_mux_1_2),
    		.Sel(PC_Src)
	);

	Mux uut7(               
    		.In1(PC_mux_1_2),
    		.In2(PC_jump),
    		.Out(PC_1),
    		.Sel(Jump)
	);

	Mux uut8(               
    		.In1(Write_data),
    		.In2(Sign_imm),
    		.Out(Src_B),
    		.Sel(ALU_src)
	);

	Mux_5_bit uut9 (        
    		.In1(Instr[20:16]),
    		.In2(Instr[15:11]),
    		.Out(Write_reg),
    		.Sel(Reg_dst)
	);

	Mux uut10(              
    		.In1(ALU_result),
    		.In2(Read_data),
    		.Out(Result),
    		.Sel(Mem_reg)
	);
	PC pc_unit(
    		.In(PC_1),
    		.Out(PC_2),
    		.Clk(clk)
	);
	assign PC_plus_4 = PC_2 + 4;
	assign PC_branch = PC_plus_4+(Sign_imm << 2);
	assign PC_slt = Instr << 2;
	assign PC_jump = {PC_plus_4[31:28],PC_slt};
	assign PC_Src = (Branch & Zero);
endmodule