data/full_repos/permissive/431863558/flip-flops/D_flip_flop.v
data/verilator_xmls/7c168e07-c210-4679-b726-055407d29643.xml
module D_FF( Q,
	     D,
             CLK,
	     RST);


	output Q;
	input D, CLK, RST;
	reg Q;

	always @ (posedge CLK,
		  negedge RST)
	begin
		if(!RST) Q <= 1'b0;
		else Q <= D;
	end
	
endmodule
module D_FF( Q,
	     D,
             CLK,
	     RST);



	output Q;
	input D, CLK, RST;
	reg Q;

	always @ (posedge CLK,
		  negedge RST)
	begin
		if(!RST) Q <= 1'b0;
		else Q <= D;
	end
	
endmodule