data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/More Verilog Features/Combinational for-loop_Vector reversal 2.v
1: b'%Error: Cannot find file containing module: Verilog\n        ... Looked in:\n             data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/More/Verilog\n             data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/More/Verilog.v\n             data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/More/Verilog.sv\n             Verilog\n             Verilog.v\n             Verilog.sv\n             obj_dir/Verilog\n             obj_dir/Verilog.v\n             obj_dir/Verilog.sv\n%Error: Cannot find file containing module: Features,data/full_repos/permissive/463549945\n%Error: Cannot find file containing module: data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/More\n%Error: Cannot find file containing module: Features/Combinational\n%Error: Cannot find file containing module: for-loop_Vector\n%Error: Cannot find file containing module: reversal\n%Error: Cannot find file containing module: 2.v\n%Error: Exiting due to 7 error(s)\n'
module top_module( 
    input [99:0] in,
    output [99:0] out
);
    integer j;

    always @(*) begin
        for ( j = 0; j <= 99; j = j+1) begin
            out [99-j] = in [j];
        end
    end
endmodule
module top_module( 
    input [99:0] in,
    output [99:0] out
);

    integer j;

    always @(*) begin
        for ( j = 0; j <= 99; j = j+1) begin
            out [99-j] = in [j];
        end
    end
endmodule