data/full_repos/permissive/476411617/BS_PE_Block.v
1: b'%Warning-SELRANGE: data/full_repos/permissive/476411617/BS_PE_Block.v:158: Selection index out of range: 31:16 outside 15:0\n                                                                         : ... In instance BS_PE_Block\n    Win[31:16]  \n       ^\n                   ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.\n%Warning-SELRANGE: data/full_repos/permissive/476411617/BS_PE_Block.v:184: Selection index out of range: 31:16 outside 15:0\n                                                                         : ... In instance BS_PE_Block\n    Ein[31:16]  \n       ^\n%Warning-SELRANGE: data/full_repos/permissive/476411617/BS_PE_Block.v:211: Selection index out of range: 31:16 outside 15:0\n                                                                         : ... In instance BS_PE_Block\n    Nin[31:16]  \n       ^\n%Warning-SELRANGE: data/full_repos/permissive/476411617/BS_PE_Block.v:237: Selection index out of range: 31:16 outside 15:0\n                                                                         : ... In instance BS_PE_Block\n    Sin[31:16]  \n       ^\n%Warning-WIDTH: data/full_repos/permissive/476411617/BS_PE_Block.v:264: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                      : ... In instance BS_PE_Block\nassign Wout = {DOB[15:0], DOA[15:0]};\n            ^\n%Warning-WIDTH: data/full_repos/permissive/476411617/BS_PE_Block.v:265: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                      : ... In instance BS_PE_Block\nassign Eout = {DOB[15:0], DOA[15:0]};\n            ^\n%Warning-WIDTH: data/full_repos/permissive/476411617/BS_PE_Block.v:266: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                      : ... In instance BS_PE_Block\nassign Nout = {DOB[15:0], DOA[15:0]};\n            ^\n%Warning-WIDTH: data/full_repos/permissive/476411617/BS_PE_Block.v:267: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                      : ... In instance BS_PE_Block\nassign Sout = {DOB[15:0], DOA[15:0]};\n            ^\n%Error: data/full_repos/permissive/476411617/BS_PE_Block.v:280: Cannot find file containing module: \'BRAM\'\nBRAM regfile\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/476411617,data/full_repos/permissive/476411617/BRAM\n             data/full_repos/permissive/476411617,data/full_repos/permissive/476411617/BRAM.v\n             data/full_repos/permissive/476411617,data/full_repos/permissive/476411617/BRAM.sv\n             BRAM\n             BRAM.v\n             BRAM.sv\n             obj_dir/BRAM\n             obj_dir/BRAM.v\n             obj_dir/BRAM.sv\n%Error: data/full_repos/permissive/476411617/BS_PE_Block.v:297: Cannot find file containing module: \'BitSliced_ALU\'\n BitSliced_ALU #(MAX_WORD_LENGTH, Slice_Size) alu \n ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 8 warning(s)\n'
module BS_PE_Block #(parameter SIZE = 1, parameter MAX_WORD_LENGTH = 32, parameter Slice_Size = 4, parameter PE_W = 2, parameter PE_H = 2)
	(
		input clk,
		input reset,

		

		input[3:0] alu_op,


		input wea,
		input web,
		input[9:0] addra,
		input[9:0] addrb,
		input[15:0] DINA,
        input[15:0] DINB,
		output[15:0] DOUTA,
        output[15:0] DOUTB,
        input external,


		input[9:0] count,


		input[2:0] state,
		

		input east,
		input west,
		input south,
		input north,

		input[(Slice_Size*PE_H*2-1):0] Ein,
		input[(Slice_Size*PE_H*2-1):0] Win,
		input[(Slice_Size*PE_W*2-1):0] Nin,
		input[(Slice_Size*PE_W*2-1):0] Sin,
		output[(Slice_Size*PE_H*2-1):0] Eout,
		output[(Slice_Size*PE_H*2-1):0] Wout,
		output[(Slice_Size*PE_W*2-1):0] Nout,
		output[(Slice_Size*PE_W*2-1):0] Sout,

		input [31:0] rs1_cnt,
		input [31:0] rs2_cnt
	);


wire[15:0] DIA; 
wire[15:0] DIB;
wire[15:0] DOB;
wire[15:0] DOA;

wire[15:0] W1, W2;
wire[15:0] E1, E2;
wire[15:0] N1, N2;
wire[15:0] S1, S2;


wire[15:0] alu_out;	
reg[15:0] q1_reg, q0_reg;
wire[15:0] q0;
wire[15:0] q1;

wire[1:0] Q [15:0];




assign E1 = {	









				Win[15:0]
			};                          
				                        
assign E2 = {	                        









				Win[31:16]
			};

assign W1 = {	









				Ein[15:0]
			};
				
assign W2 = {	









				Ein[31:16]
			};
				
				
assign S1 = {	









				Nin[15:0]
			};
				
assign S2 = {	









				Nin[31:16]
			};
				
assign N1 = {	









				Sin[15:0]
			};
				
assign N2 = {	









				Sin[31:16]
			};			
		
























assign Wout = {DOB[15:0], DOA[15:0]};
assign Eout = {DOB[15:0], DOA[15:0]};
assign Nout = {DOB[15:0], DOA[15:0]};
assign Sout = {DOB[15:0], DOA[15:0]};

assign DOUTA = DOA;
assign DOUTB = DOB;


assign DIA = external? DINA : east ? E1 : west ? W1 : south ? S1 : north ? N1 : alu_out ;
assign DIB = external? DINB : east ? E2 : west ? W2 : south ? S2 : north ? N2 : 16'hzzzz;


wire[15:0] DOB_temp;
wire[15:0] DOA_temp;

BRAM regfile
(
	clk,
	reset,
	wea,
	web,
	addra,
	addrb,
	DIA,
	DIB,	
	DOA,
	DOB
);

generate
genvar gi;
  for (gi=0; gi<(16/Slice_Size); gi=gi+1) begin : ALU
	BitSliced_ALU #(MAX_WORD_LENGTH, Slice_Size) alu 
	(
		clk,  
		reset, 
		alu_out[Slice_Size*(gi+1)-1:Slice_Size*gi],
		DOA[Slice_Size*(gi+1)-1:Slice_Size*gi], 
		DOB[Slice_Size*(gi+1)-1:Slice_Size*gi],   
		alu_op,		
		count,	
		wea,
		Q[gi],
		rs1_cnt,
		rs2_cnt

	);
  end
  

endgenerate


endmodule
module BS_PE_Block #(parameter SIZE = 1, parameter MAX_WORD_LENGTH = 32, parameter Slice_Size = 4, parameter PE_W = 2, parameter PE_H = 2)
	(
		input clk,
		input reset,

		

		input[3:0] alu_op,


		input wea,
		input web,
		input[9:0] addra,
		input[9:0] addrb,
		input[15:0] DINA,
        input[15:0] DINB,
		output[15:0] DOUTA,
        output[15:0] DOUTB,
        input external,


		input[9:0] count,


		input[2:0] state,
		

		input east,
		input west,
		input south,
		input north,

		input[(Slice_Size*PE_H*2-1):0] Ein,
		input[(Slice_Size*PE_H*2-1):0] Win,
		input[(Slice_Size*PE_W*2-1):0] Nin,
		input[(Slice_Size*PE_W*2-1):0] Sin,
		output[(Slice_Size*PE_H*2-1):0] Eout,
		output[(Slice_Size*PE_H*2-1):0] Wout,
		output[(Slice_Size*PE_W*2-1):0] Nout,
		output[(Slice_Size*PE_W*2-1):0] Sout,

		input [31:0] rs1_cnt,
		input [31:0] rs2_cnt
	);



wire[15:0] DIA; 
wire[15:0] DIB;
wire[15:0] DOB;
wire[15:0] DOA;

wire[15:0] W1, W2;
wire[15:0] E1, E2;
wire[15:0] N1, N2;
wire[15:0] S1, S2;


wire[15:0] alu_out;	
reg[15:0] q1_reg, q0_reg;
wire[15:0] q0;
wire[15:0] q1;

wire[1:0] Q [15:0];




assign E1 = {	









				Win[15:0]
			};                          
				                        
assign E2 = {	                        









				Win[31:16]
			};

assign W1 = {	









				Ein[15:0]
			};
				
assign W2 = {	









				Ein[31:16]
			};
				
				
assign S1 = {	









				Nin[15:0]
			};
				
assign S2 = {	









				Nin[31:16]
			};
				
assign N1 = {	









				Sin[15:0]
			};
				
assign N2 = {	









				Sin[31:16]
			};			
		
























assign Wout = {DOB[15:0], DOA[15:0]};
assign Eout = {DOB[15:0], DOA[15:0]};
assign Nout = {DOB[15:0], DOA[15:0]};
assign Sout = {DOB[15:0], DOA[15:0]};

assign DOUTA = DOA;
assign DOUTB = DOB;


assign DIA = external? DINA : east ? E1 : west ? W1 : south ? S1 : north ? N1 : alu_out ;
assign DIB = external? DINB : east ? E2 : west ? W2 : south ? S2 : north ? N2 : 16'hzzzz;


wire[15:0] DOB_temp;
wire[15:0] DOA_temp;

BRAM regfile
(
	clk,
	reset,
	wea,
	web,
	addra,
	addrb,
	DIA,
	DIB,	
	DOA,
	DOB
);

generate
genvar gi;
  for (gi=0; gi<(16/Slice_Size); gi=gi+1) begin : ALU
	BitSliced_ALU #(MAX_WORD_LENGTH, Slice_Size) alu 
	(
		clk,  
		reset, 
		alu_out[Slice_Size*(gi+1)-1:Slice_Size*gi],
		DOA[Slice_Size*(gi+1)-1:Slice_Size*gi], 
		DOB[Slice_Size*(gi+1)-1:Slice_Size*gi],   
		alu_op,		
		count,	
		wea,
		Q[gi],
		rs1_cnt,
		rs2_cnt

	);
  end
  

endgenerate


endmodule