data/full_repos/permissive/516809949/digital/rtl/clkg.v
1: b"%Error: data/full_repos/permissive/516809949/digital/rtl/clkg.v:65: Cannot find file containing module: 'CKLNQD1'\n  CKLNQD1 U_CLK_GATE(\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/516809949/digital/rtl,data/full_repos/permissive/516809949/CKLNQD1\n             data/full_repos/permissive/516809949/digital/rtl,data/full_repos/permissive/516809949/CKLNQD1.v\n             data/full_repos/permissive/516809949/digital/rtl,data/full_repos/permissive/516809949/CKLNQD1.sv\n             CKLNQD1\n             CKLNQD1.v\n             CKLNQD1.sv\n             obj_dir/CKLNQD1\n             obj_dir/CKLNQD1.v\n             obj_dir/CKLNQD1.sv\n%Error: data/full_repos/permissive/516809949/digital/rtl/clkg.v:116: Cannot find file containing module: 'INVLONG_OSC37'\n    INVLONG_OSC37 U_CLK_OSC(\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/516809949/digital/rtl/clkg.v:122: Cannot find file containing module: 'INVD2'\n    INVD2 U_CLK_OSC_DRV(\n    ^~~~~\n%Error: data/full_repos/permissive/516809949/digital/rtl/clkg.v:126: Cannot find file containing module: 'MUX2D0'\n    MUX2D0 U_MUX2_JTAG_OSC(\n    ^~~~~~\n%Error: data/full_repos/permissive/516809949/digital/rtl/clkg.v:139: Cannot find file containing module: 'CKLNQD1'\n    CKLNQD1 U_CLK_GATE_SMP(\n    ^~~~~~~\n%Error: data/full_repos/permissive/516809949/digital/rtl/clkg.v:145: Cannot find file containing module: 'CKLNQD1'\n    CKLNQD1 U_CLK_GATE_NCM(\n    ^~~~~~~\n%Error: data/full_repos/permissive/516809949/digital/rtl/clkg.v:151: Cannot find file containing module: 'CKLNQD1'\n    CKLNQD1 U_CLK_GATE_MSK(\n    ^~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module clkdiv256(input wire clk,
                 input wire rst_n,
                 output reg o_clk_div2,
                 output reg o_clk_div4,
                 output reg o_clk_div8,
                 output reg o_clk_div16,
                 output reg o_clk_div32,
                 output reg o_clk_div64,
                 output reg o_clk_div128,
                 output reg o_clk_div256);

  always @(posedge clk or negedge rst_n)
    if (!rst_n) o_clk_div2 <= 1'b0;
    else        o_clk_div2 <= ~o_clk_div2;

  always @(posedge o_clk_div2 or negedge rst_n)
    if (!rst_n) o_clk_div4 <= 1'b0;
    else        o_clk_div4 <= ~o_clk_div4;

  always @(posedge o_clk_div4 or negedge rst_n)
    if (!rst_n) o_clk_div8 <= 1'b0;
    else        o_clk_div8 <= ~o_clk_div8;

  always @(posedge o_clk_div8 or negedge rst_n)
    if (!rst_n) o_clk_div16 <= 1'b0;
    else        o_clk_div16 <= ~o_clk_div16;

  always @(posedge o_clk_div16 or negedge rst_n)
    if (!rst_n) o_clk_div32 <= 1'b0;
    else        o_clk_div32 <= ~o_clk_div32;

  always @(posedge o_clk_div32 or negedge rst_n)
    if (!rst_n) o_clk_div64 <= 1'b0;
    else        o_clk_div64 <= ~o_clk_div64;

  always @(posedge o_clk_div64 or negedge rst_n)
    if (!rst_n) o_clk_div128 <= 1'b0;
    else        o_clk_div128 <= ~o_clk_div128;

  always @(posedge o_clk_div128 or negedge rst_n)
    if (!rst_n) o_clk_div256 <= 1'b0;
    else        o_clk_div256 <= ~o_clk_div256;

endmodule
module clkdiv256(input wire clk,
                 input wire rst_n,
                 output reg o_clk_div2,
                 output reg o_clk_div4,
                 output reg o_clk_div8,
                 output reg o_clk_div16,
                 output reg o_clk_div32,
                 output reg o_clk_div64,
                 output reg o_clk_div128,
                 output reg o_clk_div256);


  always @(posedge clk or negedge rst_n)
    if (!rst_n) o_clk_div2 <= 1'b0;
    else        o_clk_div2 <= ~o_clk_div2;

  always @(posedge o_clk_div2 or negedge rst_n)
    if (!rst_n) o_clk_div4 <= 1'b0;
    else        o_clk_div4 <= ~o_clk_div4;

  always @(posedge o_clk_div4 or negedge rst_n)
    if (!rst_n) o_clk_div8 <= 1'b0;
    else        o_clk_div8 <= ~o_clk_div8;

  always @(posedge o_clk_div8 or negedge rst_n)
    if (!rst_n) o_clk_div16 <= 1'b0;
    else        o_clk_div16 <= ~o_clk_div16;

  always @(posedge o_clk_div16 or negedge rst_n)
    if (!rst_n) o_clk_div32 <= 1'b0;
    else        o_clk_div32 <= ~o_clk_div32;

  always @(posedge o_clk_div32 or negedge rst_n)
    if (!rst_n) o_clk_div64 <= 1'b0;
    else        o_clk_div64 <= ~o_clk_div64;

  always @(posedge o_clk_div64 or negedge rst_n)
    if (!rst_n) o_clk_div128 <= 1'b0;
    else        o_clk_div128 <= ~o_clk_div128;

  always @(posedge o_clk_div128 or negedge rst_n)
    if (!rst_n) o_clk_div256 <= 1'b0;
    else        o_clk_div256 <= ~o_clk_div256;

endmodule