data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_tidbits_wire_example.v
data/verilator_xmls/749cc83a-db66-4e8f-b1cd-0d7cf67b80e9.xml
module wire_example( a, b, y);
  input a, b;
  output y;

  wire a, b, y;

  assign y = a & b;

endmodule
module wire_example( a, b, y);

  input a, b;
  output y;

  wire a, b, y;

  assign y = a & b;

endmodule