data/full_repos/permissive/472671476/verilog/rtl/trng/ringosc_macro.v
1: b"%Error: data/full_repos/permissive/472671476/verilog/rtl/trng/ringosc_macro.v:33: Duplicate declaration of signal: 'trng_o'\n                                                                                : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nwire trng_o;\n     ^~~~~~\n        data/full_repos/permissive/472671476/verilog/rtl/trng/ringosc_macro.v:26: ... Location of original declaration\n    output trng_o\n           ^~~~~~\n%Error: Exiting due to 1 error(s)\n"
module ringosc_macro #(
  parameter TRIM_BITS = 26
) (
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif
    input rst_i,
    input [TRIM_BITS-1:0] trim_fast,
    input [TRIM_BITS-1:0] trim_slow,
    output trng_o
);

wire [1:0] clockp, clockn;
wire [1:0] temp;
wire [1:0] entropy_next;
reg  [1:0] entropy_reg;
wire trng_o;

genvar i;
generate
    for (i = 0; i < 2; i = i + 1) begin : rings
        ring_osc2x13 trng_ring_fast (
            .reset(rst_i),
            .trim(trim_fast),
            .clockp({temp[i],entropy_next[i]})
        );

        ring_osc2x13 trng_ring_slow (
            .reset(rst_i), 
            .trim(trim_slow),
            .clockp({clockn[i],clockp[i]})
        );

        always @(posedge clockp[i])
        begin
            if (rst_i == 1'b1) begin
                entropy_reg[i] <= 1'b0;
            end 
            else begin
                entropy_reg[i] <= entropy_next[i];
            end
        end
    end
endgenerate

assign trng_o = entropy_reg[0] ^ entropy_reg[1];

endmodule
module ringosc_macro #(
  parameter TRIM_BITS = 26
) (
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif
    input rst_i,
    input [TRIM_BITS-1:0] trim_fast,
    input [TRIM_BITS-1:0] trim_slow,
    output trng_o
);


wire [1:0] clockp, clockn;
wire [1:0] temp;
wire [1:0] entropy_next;
reg  [1:0] entropy_reg;
wire trng_o;

genvar i;
generate
    for (i = 0; i < 2; i = i + 1) begin : rings
        ring_osc2x13 trng_ring_fast (
            .reset(rst_i),
            .trim(trim_fast),
            .clockp({temp[i],entropy_next[i]})
        );

        ring_osc2x13 trng_ring_slow (
            .reset(rst_i), 
            .trim(trim_slow),
            .clockp({clockn[i],clockp[i]})
        );

        always @(posedge clockp[i])
        begin
            if (rst_i == 1'b1) begin
                entropy_reg[i] <= 1'b0;
            end 
            else begin
                entropy_reg[i] <= entropy_next[i];
            end
        end
    end
endgenerate

assign trng_o = entropy_reg[0] ^ entropy_reg[1];

endmodule