data/full_repos/permissive/472097485/Chu03/Flt2Int_05b/BoardTest.v
1: b"%Error: data/full_repos/permissive/472097485/Chu03/Flt2Int_05b/BoardTest.v:16: Cannot find file containing module: 'Flt2Int'\n Flt2Int flt2int( { dp[7:0], bt[3:0] }, r, of, uf );   \n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/472097485/Chu03/Flt2Int_05b,data/full_repos/permissive/472097485/Flt2Int\n             data/full_repos/permissive/472097485/Chu03/Flt2Int_05b,data/full_repos/permissive/472097485/Flt2Int.v\n             data/full_repos/permissive/472097485/Chu03/Flt2Int_05b,data/full_repos/permissive/472097485/Flt2Int.sv\n             Flt2Int\n             Flt2Int.v\n             Flt2Int.sv\n             obj_dir/Flt2Int\n             obj_dir/Flt2Int.v\n             obj_dir/Flt2Int.sv\n%Error: data/full_repos/permissive/472097485/Chu03/Flt2Int_05b/BoardTest.v:18: Cannot find file containing module: 'Bin2Bcd'\n Bin2Bcd int2bcd( clk, 1'b0, ~bt[4], { 3'b000, r[6:0] }, ready, done, bcd2[3:0], bcd1[3:0], bcd0[3:0] );\n ^~~~~~~\n%Error: data/full_repos/permissive/472097485/Chu03/Flt2Int_05b/BoardTest.v:27: Cannot find file containing module: 'DispHexMux'\n DispHexMux disp( clk, 1'b0, d2, d1, d0, dp_in, { ready, ready, ready }, en, ss );\n ^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module BoardTest( input wire clk, input wire [4:0] bt, input wire [7:0] dp, output wire [7:0] ss, output wire [2:0] en );

	wire [7:0]r;
	wire uf, of;
	wire [3:0] bcd2, bcd1, bcd0;
	wire ready, done;

	wire [4:0] d2, d1, d0;
	wire [2:0] dp_in;

	Flt2Int flt2int( { dp[7:0], bt[3:0] }, r, of, uf );

	Bin2Bcd int2bcd( clk, 1'b0, ~bt[4], { 3'b000, r[6:0] }, ready, done, bcd2[3:0], bcd1[3:0], bcd0[3:0] );

	assign dp_in = r[7] ? 3'b111 : 3'b000;

	assign d0 = ( of || uf ) ? 5'b01111 : { 1'b0, bcd0 };
	assign d1 = of ? 5'b00000 : uf ? 5'b10000 : { 1'b0, bcd1 };
	assign d2 = ( of || uf ) ? 5'b10010 : { 1'b0, bcd2 };
	

	DispHexMux disp( clk, 1'b0, d2, d1, d0, dp_in, { ready, ready, ready }, en, ss );

endmodule
module BoardTest( input wire clk, input wire [4:0] bt, input wire [7:0] dp, output wire [7:0] ss, output wire [2:0] en );


	wire [7:0]r;
	wire uf, of;
	wire [3:0] bcd2, bcd1, bcd0;
	wire ready, done;

	wire [4:0] d2, d1, d0;
	wire [2:0] dp_in;

	Flt2Int flt2int( { dp[7:0], bt[3:0] }, r, of, uf );

	Bin2Bcd int2bcd( clk, 1'b0, ~bt[4], { 3'b000, r[6:0] }, ready, done, bcd2[3:0], bcd1[3:0], bcd0[3:0] );

	assign dp_in = r[7] ? 3'b111 : 3'b000;

	assign d0 = ( of || uf ) ? 5'b01111 : { 1'b0, bcd0 };
	assign d1 = of ? 5'b00000 : uf ? 5'b10000 : { 1'b0, bcd1 };
	assign d2 = ( of || uf ) ? 5'b10010 : { 1'b0, bcd2 };
	

	DispHexMux disp( clk, 1'b0, d2, d1, d0, dp_in, { ready, ready, ready }, en, ss );

endmodule