data/full_repos/permissive/513199821/decode.v
1: b'%Error: data/full_repos/permissive/513199821/decode.v:1: Cannot find include file: global.inc\n`include "global.inc" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc.v\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc.sv\n             global.inc\n             global.inc.v\n             global.inc.sv\n             obj_dir/global.inc\n             obj_dir/global.inc.v\n             obj_dir/global.inc.sv\n%Error: data/full_repos/permissive/513199821/decode.v:27: syntax error, unexpected new, expecting IDENTIFIER or do or final\n    output reg       new,  \n                        ^\n%Error: data/full_repos/permissive/513199821/decode.v:29: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg [4:0]  rr,\n    ^~~~~~\n%Error: data/full_repos/permissive/513199821/decode.v:30: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg [4:0]  rd,\n    ^~~~~~\n%Error: data/full_repos/permissive/513199821/decode.v:31: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg [2:0]  type,\n    ^~~~~~\n%Error: data/full_repos/permissive/513199821/decode.v:31: syntax error, unexpected type, expecting IDENTIFIER or \'=\' or do or final\n    output reg [2:0]  type,\n                      ^~~~\n%Error: data/full_repos/permissive/513199821/decode.v:33: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg [DATA_WIDTH - 1:0] pc,\n    ^~~~~~\n%Error: data/full_repos/permissive/513199821/decode.v:34: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg [DATA_WIDTH - 1:0] imm\n    ^~~~~~\n%Error: data/full_repos/permissive/513199821/decode.v:35: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/513199821/decode.v:50: syntax error, unexpected assign\nassign d_ready = !(new & !i_ready);\n^~~~~~\n%Error: data/full_repos/permissive/513199821/decode.v:59: Define or directive not defined: \'`R_ZERO\'\nwire[4:0] w_rlz = w_rl == 4\'hF ? `R_ZERO : {1\'b0, w_rl};\n                                 ^~~~~~~\n%Error: data/full_repos/permissive/513199821/decode.v:59: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire[4:0] w_rlz = w_rl == 4\'hF ? `R_ZERO : {1\'b0, w_rl};\n                                         ^\n%Error: data/full_repos/permissive/513199821/decode.v:60: Define or directive not defined: \'`R_ZERO\'\nwire[4:0] w_rrz = w_rr == 4\'hF ? `R_ZERO : {1\'b0, w_rr};\n                                 ^~~~~~~\n%Error: data/full_repos/permissive/513199821/decode.v:60: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire[4:0] w_rrz = w_rr == 4\'hF ? `R_ZERO : {1\'b0, w_rr};\n                                         ^\n%Error: data/full_repos/permissive/513199821/decode.v:75: Define or directive not defined: \'`I_BAD\'\n type <= `I_BAD;\n         ^~~~~~\n%Error: data/full_repos/permissive/513199821/decode.v:76: Define or directive not defined: \'`R_ZERO\'\n rd <= `R_ZERO;\n       ^~~~~~~\n%Error: data/full_repos/permissive/513199821/decode.v:77: Define or directive not defined: \'`R_ZERO\'\n rl <= `R_ZERO;\n       ^~~~~~~\n%Error: data/full_repos/permissive/513199821/decode.v:78: Define or directive not defined: \'`R_ZERO\'\n rr <= `R_ZERO;\n       ^~~~~~~\n%Error: data/full_repos/permissive/513199821/decode.v:79: Define or directive not defined: \'`ALU_OR\'\n fn <= `ALU_OR;\n       ^~~~~~~\n%Error: data/full_repos/permissive/513199821/decode.v:90: Define or directive not defined: \'`I_ONE\'\n      type <= `I_ONE;\n              ^~~~~~\n%Error: data/full_repos/permissive/513199821/decode.v:103: Define or directive not defined: \'`I_ST\'\n       type <= `I_ST;\n               ^~~~~\n%Error: data/full_repos/permissive/513199821/decode.v:109: Define or directive not defined: \'`I_LD\'\n       type <= `I_LD;\n               ^~~~~\n%Error: data/full_repos/permissive/513199821/decode.v:118: Define or directive not defined: \'`I_BRA\'\n     type <= `I_BRA;\n             ^~~~~~\n%Error: data/full_repos/permissive/513199821/decode.v:119: Define or directive not defined: \'`R_ZERO\'\n     rl  <= w_rdz ? `R_ZERO : w_rrd;\n                    ^~~~~~~\n%Error: data/full_repos/permissive/513199821/decode.v:126: Define or directive not defined: \'`I_ONE\'\n     type <= `I_ONE;\n             ^~~~~~\n%Error: data/full_repos/permissive/513199821/decode.v:134: Define or directive not defined: \'`I_ONE\'\n     type <= `I_ONE;\n             ^~~~~~\n%Error: Exiting due to 26 error(s)\n'
module decode  #(
    parameter DATA_WIDTH = 32
  ) (
    input  clk,
    input  rst,
    input  opready,
    input  [15:0] op,
    input  [DATA_WIDTH - 1:0] pc_f,
    input  [DATA_WIDTH - 1:0] pcnext,
    input      i_ready,
    output     d_ready,

    output reg	      new,
    output reg [4:0]  rl,
    output reg [4:0]  rr,
    output reg [4:0]  rd,
    output reg [2:0]  type,
    output reg [3:0]  fn,
    output reg [DATA_WIDTH - 1:0] pc,
    output reg [DATA_WIDTH - 1:0] imm
);

localparam EXT_WIDTH = DATA_WIDTH - 16;


reg [2:0] st;

localparam S_ZERO = 0;
localparam S_IMMI = 1;
localparam S_IMMH = 2;
localparam S_IMML = 3;
localparam S_IMMB = 4;
localparam S_SET  = 5;


assign d_ready = !(new & !i_ready);


wire [3:0] w_rd = op[11:8];
wire [3:0] w_rl = op[ 7:4];
wire [3:0] w_rr = op[ 3:0];

wire	  w_rdz = w_rd == 4'hF;
wire[4:0] w_rrd = {1'b0, w_rd};
wire[4:0] w_rlz = w_rl == 4'hF ? `R_ZERO : {1'b0, w_rl};
wire[4:0] w_rrz = w_rr == 4'hF ? `R_ZERO : {1'b0, w_rr};

always @ (posedge clk)
begin
  if (rst) begin
    st	    <= S_ZERO;
    new     <= 1'b0;
  end else if (d_ready & !opready) begin
    new <= 1'b0;
  end else if (opready) begin
    case (st)
      S_ZERO: begin

	new  <= 1'b0;
	imm	<= {DATA_WIDTH {1'b0}};
	type	<= `I_BAD;
	rd	<= `R_ZERO;
	rl	<= `R_ZERO;
	rr	<= `R_ZERO;
	fn	<= `ALU_OR;
	pc	<= pc_f;


	case (op[15:12])
	  4'h0: begin
	    if (w_rdz) begin
	      if (w_rlz) begin
	      end else begin
		case (op[3:0])
		  4'h9: begin
		    type <= `I_ONE;
		    rl	 <= w_rl;
		    st	 <= S_SET;
		  end
		endcase
	      end
	    end else begin
	    end
	  end

	  4'h1: begin
	    if (op[3]) begin
	      fn   <= {2'b0, op[1:0]};
	      type <= `I_ST;
	      rl   <= w_rrd;
	      rr   <= {1'b0, w_rl};
	      st   <= S_IMMI;
	    end else begin
	      fn   <= {1'b0, op[2:0]};
	      type <= `I_LD;
	      rd   <= w_rrd;
	      rl   <= {1'b0, w_rl};
	      st   <= S_IMMI;
	    end
	  end

	  4'h2: begin
	    fn	 <= op[2:0];
	    type <= `I_BRA;
	    rl	 <= w_rdz ? `R_ZERO : w_rrd;
	    rr	 <= w_rlz;
	    st	 <= S_IMMB;
	  end

	  4'h3: begin
	    fn	 <= op[3:0];
	    type <= `I_ONE;
	    rd	  <= w_rrd;
	    rl	  <= w_rlz;
	    st	  <= S_IMMI;
	  end

	  default: begin
	    fn	 <= op[15:12];
	    type <= `I_ONE;
	    rd	 <= w_rrd;
	    rl	 <= w_rlz;
	    rr	 <= {1'b0, w_rr};
	    new  <= 1'b1;
	  end
	endcase
      end

      S_IMMI: begin

	imm	<= {{EXT_WIDTH {op[15]}}, op};
	st	<= S_ZERO;
	new	<= 1'b1;
      end

      S_IMMH: begin
	imm <= {op, 16'h0000};
	st  <= S_IMML;
      end

      S_IMML: begin
	imm[15:0] <= op;
	st	  <= S_ZERO;
	new	  <= 1'b1;
      end

      S_IMMB: begin

	imm	<= pcnext + {{EXT_WIDTH  - 1 {op[15]}}, op[15:0], 1'b0};
	st	<= S_ZERO;
	new	<= 1'b1;
      end

      S_SET: begin
	rd  <= {1'b1, op[3:0]};
	new <= 1'b1;
	st  <= S_ZERO;
      end
    endcase

`ifdef DECODE_TEST
    $display ("DECODE\t%x st=%d pc=%x pcnext=%x op=%x iready=%x", coreZ0.cycle, st, pc_f, pcnext, op, i_ready);
`endif

  end
end

endmodule
module decode  #(
    parameter DATA_WIDTH = 32
  ) (
    input  clk,
    input  rst,
    input  opready,
    input  [15:0] op,
    input  [DATA_WIDTH - 1:0] pc_f,
    input  [DATA_WIDTH - 1:0] pcnext,
    input      i_ready,
    output     d_ready,

    output reg	      new,
    output reg [4:0]  rl,
    output reg [4:0]  rr,
    output reg [4:0]  rd,
    output reg [2:0]  type,
    output reg [3:0]  fn,
    output reg [DATA_WIDTH - 1:0] pc,
    output reg [DATA_WIDTH - 1:0] imm
);


localparam EXT_WIDTH = DATA_WIDTH - 16;


reg [2:0] st;

localparam S_ZERO = 0;
localparam S_IMMI = 1;
localparam S_IMMH = 2;
localparam S_IMML = 3;
localparam S_IMMB = 4;
localparam S_SET  = 5;


assign d_ready = !(new & !i_ready);


wire [3:0] w_rd = op[11:8];
wire [3:0] w_rl = op[ 7:4];
wire [3:0] w_rr = op[ 3:0];

wire	  w_rdz = w_rd == 4'hF;
wire[4:0] w_rrd = {1'b0, w_rd};
wire[4:0] w_rlz = w_rl == 4'hF ? `R_ZERO : {1'b0, w_rl};
wire[4:0] w_rrz = w_rr == 4'hF ? `R_ZERO : {1'b0, w_rr};

always @ (posedge clk)
begin
  if (rst) begin
    st	    <= S_ZERO;
    new     <= 1'b0;
  end else if (d_ready & !opready) begin
    new <= 1'b0;
  end else if (opready) begin
    case (st)
      S_ZERO: begin

	new  <= 1'b0;
	imm	<= {DATA_WIDTH {1'b0}};
	type	<= `I_BAD;
	rd	<= `R_ZERO;
	rl	<= `R_ZERO;
	rr	<= `R_ZERO;
	fn	<= `ALU_OR;
	pc	<= pc_f;


	case (op[15:12])
	  4'h0: begin
	    if (w_rdz) begin
	      if (w_rlz) begin
	      end else begin
		case (op[3:0])
		  4'h9: begin
		    type <= `I_ONE;
		    rl	 <= w_rl;
		    st	 <= S_SET;
		  end
		endcase
	      end
	    end else begin
	    end
	  end

	  4'h1: begin
	    if (op[3]) begin
	      fn   <= {2'b0, op[1:0]};
	      type <= `I_ST;
	      rl   <= w_rrd;
	      rr   <= {1'b0, w_rl};
	      st   <= S_IMMI;
	    end else begin
	      fn   <= {1'b0, op[2:0]};
	      type <= `I_LD;
	      rd   <= w_rrd;
	      rl   <= {1'b0, w_rl};
	      st   <= S_IMMI;
	    end
	  end

	  4'h2: begin
	    fn	 <= op[2:0];
	    type <= `I_BRA;
	    rl	 <= w_rdz ? `R_ZERO : w_rrd;
	    rr	 <= w_rlz;
	    st	 <= S_IMMB;
	  end

	  4'h3: begin
	    fn	 <= op[3:0];
	    type <= `I_ONE;
	    rd	  <= w_rrd;
	    rl	  <= w_rlz;
	    st	  <= S_IMMI;
	  end

	  default: begin
	    fn	 <= op[15:12];
	    type <= `I_ONE;
	    rd	 <= w_rrd;
	    rl	 <= w_rlz;
	    rr	 <= {1'b0, w_rr};
	    new  <= 1'b1;
	  end
	endcase
      end

      S_IMMI: begin

	imm	<= {{EXT_WIDTH {op[15]}}, op};
	st	<= S_ZERO;
	new	<= 1'b1;
      end

      S_IMMH: begin
	imm <= {op, 16'h0000};
	st  <= S_IMML;
      end

      S_IMML: begin
	imm[15:0] <= op;
	st	  <= S_ZERO;
	new	  <= 1'b1;
      end

      S_IMMB: begin

	imm	<= pcnext + {{EXT_WIDTH  - 1 {op[15]}}, op[15:0], 1'b0};
	st	<= S_ZERO;
	new	<= 1'b1;
      end

      S_SET: begin
	rd  <= {1'b1, op[3:0]};
	new <= 1'b1;
	st  <= S_ZERO;
      end
    endcase

`ifdef DECODE_TEST
    $display ("DECODE\t%x st=%d pc=%x pcnext=%x op=%x iready=%x", coreZ0.cycle, st, pc_f, pcnext, op, i_ready);
`endif

  end
end

endmodule