data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v
1: b"%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:211: Define or directive not defined: '`DIS_VEC_DSTF_VLD'\nassign vpu_rtu_ex1_fp_dirty                 = idu_vidu_ex1_inst_data[`DIS_VEC_DSTF_VLD]\n                                                                     ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:211: syntax error, unexpected ']', expecting TYPE-IDENTIFIER\nassign vpu_rtu_ex1_fp_dirty                 = idu_vidu_ex1_inst_data[`DIS_VEC_DSTF_VLD]\n                                                                                      ^\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:212: Define or directive not defined: '`DIS_VEC_DSTE_VLD'\n                                           || idu_vidu_ex1_inst_data[`DIS_VEC_DSTE_VLD];\n                                                                     ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:213: Define or directive not defined: '`DIS_VEC_DSTV_VLD'\nassign vpu_rtu_ex1_vec_dirty                = idu_vidu_ex1_inst_data[`DIS_VEC_DSTV_VLD] || idu_vidu_ex1_inst_data[`DIS_VEC_DSTV_LATE_VLD];\n                                                                     ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:213: syntax error, unexpected ']', expecting TYPE-IDENTIFIER\nassign vpu_rtu_ex1_vec_dirty                = idu_vidu_ex1_inst_data[`DIS_VEC_DSTV_VLD] || idu_vidu_ex1_inst_data[`DIS_VEC_DSTV_LATE_VLD];\n                                                                                      ^\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:213: Define or directive not defined: '`DIS_VEC_DSTV_LATE_VLD'\nassign vpu_rtu_ex1_vec_dirty                = idu_vidu_ex1_inst_data[`DIS_VEC_DSTV_VLD] || idu_vidu_ex1_inst_data[`DIS_VEC_DSTV_LATE_VLD];\n                                                                                                                  ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:221: Define or directive not defined: '`DIS_VEC_WIDTH'\nassign dp_fp_inst_data[`DIS_VEC_WIDTH-1:0]  = split_fp_dp_inst_data[`DIS_VEC_WIDTH-1:0];\n                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:221: Define or directive not defined: '`DIS_VEC_WIDTH'\nassign dp_fp_inst_data[`DIS_VEC_WIDTH-1:0]  = split_fp_dp_inst_data[`DIS_VEC_WIDTH-1:0];\n                                                                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:226: Define or directive not defined: '`FUNC_WIDTH'\nassign dp_dis_fp_inst_func[`FUNC_WIDTH-1:0] = dp_fp_inst_data[`DIS_VEC_FUNC:`DIS_VEC_FUNC-`FUNC_WIDTH+1];\n                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:226: Define or directive not defined: '`DIS_VEC_FUNC'\nassign dp_dis_fp_inst_func[`FUNC_WIDTH-1:0] = dp_fp_inst_data[`DIS_VEC_FUNC:`DIS_VEC_FUNC-`FUNC_WIDTH+1];\n                                                              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:226: syntax error, unexpected ':', expecting TYPE-IDENTIFIER\nassign dp_dis_fp_inst_func[`FUNC_WIDTH-1:0] = dp_fp_inst_data[`DIS_VEC_FUNC:`DIS_VEC_FUNC-`FUNC_WIDTH+1];\n                                                                           ^\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:226: Define or directive not defined: '`DIS_VEC_FUNC'\nassign dp_dis_fp_inst_func[`FUNC_WIDTH-1:0] = dp_fp_inst_data[`DIS_VEC_FUNC:`DIS_VEC_FUNC-`FUNC_WIDTH+1];\n                                                                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:226: Define or directive not defined: '`FUNC_WIDTH'\nassign dp_dis_fp_inst_func[`FUNC_WIDTH-1:0] = dp_fp_inst_data[`DIS_VEC_FUNC:`DIS_VEC_FUNC-`FUNC_WIDTH+1];\n                                                                                          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:227: Define or directive not defined: '`EU_WIDTH'\nassign dp_dis_fp_inst_eu[`EU_WIDTH-1:0]     = dp_fp_inst_data[`DIS_VEC_EU:`DIS_VEC_EU-`EU_WIDTH+1];\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:227: Define or directive not defined: '`DIS_VEC_EU'\nassign dp_dis_fp_inst_eu[`EU_WIDTH-1:0]     = dp_fp_inst_data[`DIS_VEC_EU:`DIS_VEC_EU-`EU_WIDTH+1];\n                                                              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:227: syntax error, unexpected ':', expecting TYPE-IDENTIFIER\nassign dp_dis_fp_inst_eu[`EU_WIDTH-1:0]     = dp_fp_inst_data[`DIS_VEC_EU:`DIS_VEC_EU-`EU_WIDTH+1];\n                                                                         ^\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:227: Define or directive not defined: '`DIS_VEC_EU'\nassign dp_dis_fp_inst_eu[`EU_WIDTH-1:0]     = dp_fp_inst_data[`DIS_VEC_EU:`DIS_VEC_EU-`EU_WIDTH+1];\n                                                                          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:227: Define or directive not defined: '`EU_WIDTH'\nassign dp_dis_fp_inst_eu[`EU_WIDTH-1:0]     = dp_fp_inst_data[`DIS_VEC_EU:`DIS_VEC_EU-`EU_WIDTH+1];\n                                                                                      ^~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:228: Define or directive not defined: '`DIS_VEC_DSTV_REG'\nassign dp_dis_fp_inst_dstf_reg[4:0]         = dp_fp_inst_data[`DIS_VEC_DSTV_REG-8:`DIS_VEC_DSTV_REG-12];\n                                                              ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:228: Define or directive not defined: '`DIS_VEC_DSTV_REG'\nassign dp_dis_fp_inst_dstf_reg[4:0]         = dp_fp_inst_data[`DIS_VEC_DSTV_REG-8:`DIS_VEC_DSTV_REG-12];\n                                                                                  ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:229: Define or directive not defined: '`DIS_VEC_SRC1_DATA'\nassign dp_dis_fp_inst_src1_data[63:0]       = dp_fp_inst_data[`DIS_VEC_SRC1_DATA:`DIS_VEC_SRC1_DATA-63];\n                                                              ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:229: syntax error, unexpected ':', expecting TYPE-IDENTIFIER\nassign dp_dis_fp_inst_src1_data[63:0]       = dp_fp_inst_data[`DIS_VEC_SRC1_DATA:`DIS_VEC_SRC1_DATA-63];\n                                                                                ^\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:229: Define or directive not defined: '`DIS_VEC_SRC1_DATA'\nassign dp_dis_fp_inst_src1_data[63:0]       = dp_fp_inst_data[`DIS_VEC_SRC1_DATA:`DIS_VEC_SRC1_DATA-63];\n                                                                                 ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:230: Define or directive not defined: '`DIS_VEC_DST0_REG'\nassign dp_dis_fp_inst_dst0_reg[5:0]         = dp_fp_inst_data[`DIS_VEC_DST0_REG:`DIS_VEC_DST0_REG-5];\n                                                              ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:230: syntax error, unexpected ':', expecting TYPE-IDENTIFIER\nassign dp_dis_fp_inst_dst0_reg[5:0]         = dp_fp_inst_data[`DIS_VEC_DST0_REG:`DIS_VEC_DST0_REG-5];\n                                                                               ^\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:230: Define or directive not defined: '`DIS_VEC_DST0_REG'\nassign dp_dis_fp_inst_dst0_reg[5:0]         = dp_fp_inst_data[`DIS_VEC_DST0_REG:`DIS_VEC_DST0_REG-5];\n                                                                                ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:231: Define or directive not defined: '`DIS_VEC_DST0_VLD'\nassign dp_dis_fp_inst_dst0_vld              = dp_fp_inst_data[`DIS_VEC_DST0_VLD];\n                                                              ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:231: syntax error, unexpected ']', expecting TYPE-IDENTIFIER\nassign dp_dis_fp_inst_dst0_vld              = dp_fp_inst_data[`DIS_VEC_DST0_VLD];\n                                                                               ^\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:232: Define or directive not defined: '`DIS_VEC_DSTF_VLD'\nassign dp_dis_fp_inst_dstf_vld              = dp_fp_inst_data[`DIS_VEC_DSTF_VLD];\n                                                              ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:232: syntax error, unexpected ']', expecting TYPE-IDENTIFIER\nassign dp_dis_fp_inst_dstf_vld              = dp_fp_inst_data[`DIS_VEC_DSTF_VLD];\n                                                                               ^\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:233: Define or directive not defined: '`DIS_VEC_DSTE_VLD'\nassign dp_dis_fp_inst_dste_vld              = dp_fp_inst_data[`DIS_VEC_DSTE_VLD];\n                                                              ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:233: syntax error, unexpected ']', expecting TYPE-IDENTIFIER\nassign dp_dis_fp_inst_dste_vld              = dp_fp_inst_data[`DIS_VEC_DSTE_VLD];\n                                                                               ^\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:244: Define or directive not defined: '`DIS_VEC_SRCF0_VLD'\n                              : dp_fp_inst_data[`DIS_VEC_SRCF0_VLD];\n                                                ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:244: syntax error, unexpected ']', expecting TYPE-IDENTIFIER\n                              : dp_fp_inst_data[`DIS_VEC_SRCF0_VLD];\n                                                                  ^\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:247: Define or directive not defined: '`DIS_VEC_SRCF1_VLD'\n                              : dp_fp_inst_data[`DIS_VEC_SRCF1_VLD];\n                                                ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:247: syntax error, unexpected ']', expecting TYPE-IDENTIFIER\n                              : dp_fp_inst_data[`DIS_VEC_SRCF1_VLD];\n                                                                  ^\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:250: Define or directive not defined: '`DIS_VEC_SRCF2_VLD'\n                              : dp_fp_inst_data[`DIS_VEC_SRCF2_VLD];\n                                                ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:250: syntax error, unexpected ']', expecting TYPE-IDENTIFIER\n                              : dp_fp_inst_data[`DIS_VEC_SRCF2_VLD];\n                                                                  ^\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:253: Define or directive not defined: '`DIS_VEC_DSTF_VLD'\n                              : dp_fp_inst_data[`DIS_VEC_DSTF_VLD];\n                                                ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:253: syntax error, unexpected ']', expecting TYPE-IDENTIFIER\n                              : dp_fp_inst_data[`DIS_VEC_DSTF_VLD];\n                                                                 ^\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:257: Define or directive not defined: '`DIS_VEC_SRCV0_REG'\n                              : dp_fp_inst_data[`DIS_VEC_SRCV0_REG-8:`DIS_VEC_SRCV0_REG-12];\n                                                ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:257: Define or directive not defined: '`DIS_VEC_SRCV0_REG'\n                              : dp_fp_inst_data[`DIS_VEC_SRCV0_REG-8:`DIS_VEC_SRCV0_REG-12];\n                                                                     ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:260: Define or directive not defined: '`DIS_VEC_SRCV1_REG'\n                              : dp_fp_inst_data[`DIS_VEC_SRCV1_REG-8:`DIS_VEC_SRCV1_REG-12];\n                                                ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:260: Define or directive not defined: '`DIS_VEC_SRCV1_REG'\n                              : dp_fp_inst_data[`DIS_VEC_SRCV1_REG-8:`DIS_VEC_SRCV1_REG-12];\n                                                                     ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:263: Define or directive not defined: '`DIS_VEC_SRCV2_REG'\n                              : dp_fp_inst_data[`DIS_VEC_SRCV2_REG-8:`DIS_VEC_SRCV2_REG-12];\n                                                ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:263: Define or directive not defined: '`DIS_VEC_SRCV2_REG'\n                              : dp_fp_inst_data[`DIS_VEC_SRCV2_REG-8:`DIS_VEC_SRCV2_REG-12];\n                                                                     ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:266: Define or directive not defined: '`DIS_VEC_DSTV_REG'\n                              : dp_fp_inst_data[`DIS_VEC_DSTV_REG-8:`DIS_VEC_DSTV_REG-12];\n                                                ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:266: Define or directive not defined: '`DIS_VEC_DSTV_REG'\n                              : dp_fp_inst_data[`DIS_VEC_DSTV_REG-8:`DIS_VEC_DSTV_REG-12];\n                                                                    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:280: Define or directive not defined: '`DIS_VEC_EU'\nassign dp_ctrl_dis_fp_inst_store     = dp_fp_inst_data[`DIS_VEC_EU-`EU_WIDTH+1+`EU_VLSU_SEL]\n                                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/vidu/rtl/aq_vidu_vid_dp_fp.v:280: Define or directive not defined: '`EU_WIDTH'\nassign dp_ctrl_dis_fp_inst_store     = dp_fp_inst_data[`DIS_VEC_EU-`EU_WIDTH+1+`EU_VLSU_SEL]\n                                                                   ^~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n"
module aq_vidu_vid_dp_fp(
  ctrl_dp_fgpr_reuse_inst_dp_vld,
  dp_ctrl_dis_fp_inst_dstf_vld,
  dp_ctrl_dis_fp_inst_srcf0_reg,
  dp_ctrl_dis_fp_inst_srcf0_vld,
  dp_ctrl_dis_fp_inst_srcf1_reg,
  dp_ctrl_dis_fp_inst_srcf1_vld,
  dp_ctrl_dis_fp_inst_srcf2_reg,
  dp_ctrl_dis_fp_inst_srcf2_vld,
  dp_ctrl_dis_fp_inst_store,
  dp_ctrl_dis_fp_inst_wb_type,
  dp_gpr_fp_src0_reg,
  dp_gpr_fp_src1_reg,
  dp_gpr_fp_src2_reg,
  dp_vec_fgpr_reuse_dstf_reg,
  dp_vec_fgpr_reuse_dstf_vld,
  dp_vec_fgpr_reuse_srcf0_reg,
  dp_vec_fgpr_reuse_srcf0_vld,
  dp_vec_fgpr_reuse_srcf1_reg,
  dp_vec_fgpr_reuse_srcf1_vld,
  dp_vec_fgpr_reuse_srcf2_reg,
  dp_vec_fgpr_reuse_srcf2_vld,
  dp_wbt_fp_dstv_reg,
  dp_wbt_fp_dstv_type,
  dp_wbt_fp_dstv_vld,
  dp_wbt_fp_srcv0_reg,
  dp_wbt_fp_srcv1_reg,
  dp_wbt_fp_srcv2_reg,
  gpr_fp_dp_src0_data,
  gpr_fp_dp_src1_data,
  gpr_fp_dp_src2_data,
  idu_vidu_ex1_inst_data,
  split_fp_dp_inst_data,
  vidu_vpu_vid_fp_inst_dst_reg,
  vidu_vpu_vid_fp_inst_dst_vld,
  vidu_vpu_vid_fp_inst_dste_vld,
  vidu_vpu_vid_fp_inst_dstf_reg,
  vidu_vpu_vid_fp_inst_dstf_vld,
  vidu_vpu_vid_fp_inst_eu,
  vidu_vpu_vid_fp_inst_func,
  vidu_vpu_vid_fp_inst_src1_data,
  vidu_vpu_vid_fp_inst_srcf0_data,
  vidu_vpu_vid_fp_inst_srcf1_data,
  vidu_vpu_vid_fp_inst_srcf2_data,
  vidu_vpu_vid_fp_inst_srcf2_rdy,
  vidu_vpu_vid_fp_inst_srcf2_vld,
  vpu_rtu_ex1_fp_dirty,
  vpu_rtu_ex1_vec_dirty,
  vpu_vidu_fp_fwd_data,
  vpu_vidu_fp_fwd_reg,
  vpu_vidu_fp_fwd_vld,
  wbt_ctrl_fp_srcv2_info
);


input            ctrl_dp_fgpr_reuse_inst_dp_vld; 
input   [4  :0]  dp_vec_fgpr_reuse_dstf_reg;     
input            dp_vec_fgpr_reuse_dstf_vld;     
input   [4  :0]  dp_vec_fgpr_reuse_srcf0_reg;    
input            dp_vec_fgpr_reuse_srcf0_vld;    
input   [4  :0]  dp_vec_fgpr_reuse_srcf1_reg;    
input            dp_vec_fgpr_reuse_srcf1_vld;    
input   [4  :0]  dp_vec_fgpr_reuse_srcf2_reg;    
input            dp_vec_fgpr_reuse_srcf2_vld;    
input   [63 :0]  gpr_fp_dp_src0_data;            
input   [63 :0]  gpr_fp_dp_src1_data;            
input   [63 :0]  gpr_fp_dp_src2_data;            
input   [179:0]  idu_vidu_ex1_inst_data;         
input   [179:0]  split_fp_dp_inst_data;          
input   [63 :0]  vpu_vidu_fp_fwd_data;           
input   [4  :0]  vpu_vidu_fp_fwd_reg;            
input            vpu_vidu_fp_fwd_vld;            
input   [2  :0]  wbt_ctrl_fp_srcv2_info;         
output           dp_ctrl_dis_fp_inst_dstf_vld;   
output  [4  :0]  dp_ctrl_dis_fp_inst_srcf0_reg;  
output           dp_ctrl_dis_fp_inst_srcf0_vld;  
output  [4  :0]  dp_ctrl_dis_fp_inst_srcf1_reg;  
output           dp_ctrl_dis_fp_inst_srcf1_vld;  
output  [4  :0]  dp_ctrl_dis_fp_inst_srcf2_reg;  
output           dp_ctrl_dis_fp_inst_srcf2_vld;  
output           dp_ctrl_dis_fp_inst_store;      
output           dp_ctrl_dis_fp_inst_wb_type;    
output  [4  :0]  dp_gpr_fp_src0_reg;             
output  [4  :0]  dp_gpr_fp_src1_reg;             
output  [4  :0]  dp_gpr_fp_src2_reg;             
output  [4  :0]  dp_wbt_fp_dstv_reg;             
output           dp_wbt_fp_dstv_type;            
output           dp_wbt_fp_dstv_vld;             
output  [4  :0]  dp_wbt_fp_srcv0_reg;            
output  [4  :0]  dp_wbt_fp_srcv1_reg;            
output  [4  :0]  dp_wbt_fp_srcv2_reg;            
output  [5  :0]  vidu_vpu_vid_fp_inst_dst_reg;   
output           vidu_vpu_vid_fp_inst_dst_vld;   
output           vidu_vpu_vid_fp_inst_dste_vld;  
output  [4  :0]  vidu_vpu_vid_fp_inst_dstf_reg;  
output           vidu_vpu_vid_fp_inst_dstf_vld;  
output  [9  :0]  vidu_vpu_vid_fp_inst_eu;        
output  [19 :0]  vidu_vpu_vid_fp_inst_func;      
output  [63 :0]  vidu_vpu_vid_fp_inst_src1_data; 
output  [63 :0]  vidu_vpu_vid_fp_inst_srcf0_data; 
output  [63 :0]  vidu_vpu_vid_fp_inst_srcf1_data; 
output  [63 :0]  vidu_vpu_vid_fp_inst_srcf2_data; 
output           vidu_vpu_vid_fp_inst_srcf2_rdy; 
output           vidu_vpu_vid_fp_inst_srcf2_vld; 
output           vpu_rtu_ex1_fp_dirty;           
output           vpu_rtu_ex1_vec_dirty;          




wire             ctrl_dp_fgpr_reuse_inst_dp_vld; 
wire             dp_ctrl_dis_fp_inst_dstf_vld;   
wire    [4  :0]  dp_ctrl_dis_fp_inst_srcf0_reg;  
wire             dp_ctrl_dis_fp_inst_srcf0_vld;  
wire    [4  :0]  dp_ctrl_dis_fp_inst_srcf1_reg;  
wire             dp_ctrl_dis_fp_inst_srcf1_vld;  
wire    [4  :0]  dp_ctrl_dis_fp_inst_srcf2_reg;  
wire             dp_ctrl_dis_fp_inst_srcf2_vld;  
wire             dp_ctrl_dis_fp_inst_store;      
wire             dp_ctrl_dis_fp_inst_wb_type;    
wire    [5  :0]  dp_dis_fp_inst_dst0_reg;        
wire             dp_dis_fp_inst_dst0_vld;        
wire             dp_dis_fp_inst_dste_vld;        
wire    [4  :0]  dp_dis_fp_inst_dstf_reg;        
wire             dp_dis_fp_inst_dstf_vld;        
wire    [9  :0]  dp_dis_fp_inst_eu;              
wire    [19 :0]  dp_dis_fp_inst_func;            
wire    [63 :0]  dp_dis_fp_inst_src1_data;       
wire    [63 :0]  dp_dis_fp_inst_srcf0_data;      
wire             dp_dis_fp_inst_srcf0_fwd_vld;   
wire    [63 :0]  dp_dis_fp_inst_srcf1_data;      
wire             dp_dis_fp_inst_srcf1_fwd_vld;   
wire    [63 :0]  dp_dis_fp_inst_srcf2_data;      
wire             dp_dis_fp_inst_srcf2_fwd_vld;   
wire             dp_dis_fp_inst_srcf2_rdy;       
wire             dp_dis_fp_inst_srcf2_vld;       
wire    [4  :0]  dp_fp_dstf_reg;                 
wire             dp_fp_dstf_vld;                 
wire    [179:0]  dp_fp_inst_data;                
wire    [4  :0]  dp_fp_srcf0_reg;                
wire             dp_fp_srcf0_vld;                
wire    [4  :0]  dp_fp_srcf1_reg;                
wire             dp_fp_srcf1_vld;                
wire    [4  :0]  dp_fp_srcf2_reg;                
wire             dp_fp_srcf2_vld;                
wire    [4  :0]  dp_gpr_fp_src0_reg;             
wire    [4  :0]  dp_gpr_fp_src1_reg;             
wire    [4  :0]  dp_gpr_fp_src2_reg;             
wire    [4  :0]  dp_vec_fgpr_reuse_dstf_reg;     
wire             dp_vec_fgpr_reuse_dstf_vld;     
wire    [4  :0]  dp_vec_fgpr_reuse_srcf0_reg;    
wire             dp_vec_fgpr_reuse_srcf0_vld;    
wire    [4  :0]  dp_vec_fgpr_reuse_srcf1_reg;    
wire             dp_vec_fgpr_reuse_srcf1_vld;    
wire    [4  :0]  dp_vec_fgpr_reuse_srcf2_reg;    
wire             dp_vec_fgpr_reuse_srcf2_vld;    
wire             dp_wb_inst_type;                
wire    [4  :0]  dp_wbt_fp_dstv_reg;             
wire             dp_wbt_fp_dstv_type;            
wire             dp_wbt_fp_dstv_vld;             
wire    [4  :0]  dp_wbt_fp_srcv0_reg;            
wire    [4  :0]  dp_wbt_fp_srcv1_reg;            
wire    [4  :0]  dp_wbt_fp_srcv2_reg;            
wire    [63 :0]  gpr_fp_dp_src0_data;            
wire    [63 :0]  gpr_fp_dp_src1_data;            
wire    [63 :0]  gpr_fp_dp_src2_data;            
wire    [179:0]  idu_vidu_ex1_inst_data;         
wire    [179:0]  split_fp_dp_inst_data;          
wire    [5  :0]  vidu_vpu_vid_fp_inst_dst_reg;   
wire             vidu_vpu_vid_fp_inst_dst_vld;   
wire             vidu_vpu_vid_fp_inst_dste_vld;  
wire    [4  :0]  vidu_vpu_vid_fp_inst_dstf_reg;  
wire             vidu_vpu_vid_fp_inst_dstf_vld;  
wire    [9  :0]  vidu_vpu_vid_fp_inst_eu;        
wire    [19 :0]  vidu_vpu_vid_fp_inst_func;      
wire    [63 :0]  vidu_vpu_vid_fp_inst_src1_data; 
wire    [63 :0]  vidu_vpu_vid_fp_inst_srcf0_data; 
wire    [63 :0]  vidu_vpu_vid_fp_inst_srcf1_data; 
wire    [63 :0]  vidu_vpu_vid_fp_inst_srcf2_data; 
wire             vidu_vpu_vid_fp_inst_srcf2_rdy; 
wire             vidu_vpu_vid_fp_inst_srcf2_vld; 
wire             vpu_rtu_ex1_fp_dirty;           
wire             vpu_rtu_ex1_vec_dirty;          
wire    [63 :0]  vpu_vidu_fp_fwd_data;           
wire    [4  :0]  vpu_vidu_fp_fwd_reg;            
wire             vpu_vidu_fp_fwd_vld;            
wire    [2  :0]  wbt_ctrl_fp_srcv2_info;         






assign vpu_rtu_ex1_fp_dirty                 = idu_vidu_ex1_inst_data[`DIS_VEC_DSTF_VLD]
                                           || idu_vidu_ex1_inst_data[`DIS_VEC_DSTE_VLD];
assign vpu_rtu_ex1_vec_dirty                = idu_vidu_ex1_inst_data[`DIS_VEC_DSTV_VLD] || idu_vidu_ex1_inst_data[`DIS_VEC_DSTV_LATE_VLD];







assign dp_fp_inst_data[`DIS_VEC_WIDTH-1:0]  = split_fp_dp_inst_data[`DIS_VEC_WIDTH-1:0];




assign dp_dis_fp_inst_func[`FUNC_WIDTH-1:0] = dp_fp_inst_data[`DIS_VEC_FUNC:`DIS_VEC_FUNC-`FUNC_WIDTH+1];
assign dp_dis_fp_inst_eu[`EU_WIDTH-1:0]     = dp_fp_inst_data[`DIS_VEC_EU:`DIS_VEC_EU-`EU_WIDTH+1];
assign dp_dis_fp_inst_dstf_reg[4:0]         = dp_fp_inst_data[`DIS_VEC_DSTV_REG-8:`DIS_VEC_DSTV_REG-12];
assign dp_dis_fp_inst_src1_data[63:0]       = dp_fp_inst_data[`DIS_VEC_SRC1_DATA:`DIS_VEC_SRC1_DATA-63];
assign dp_dis_fp_inst_dst0_reg[5:0]         = dp_fp_inst_data[`DIS_VEC_DST0_REG:`DIS_VEC_DST0_REG-5];
assign dp_dis_fp_inst_dst0_vld              = dp_fp_inst_data[`DIS_VEC_DST0_VLD];
assign dp_dis_fp_inst_dstf_vld              = dp_fp_inst_data[`DIS_VEC_DSTF_VLD];
assign dp_dis_fp_inst_dste_vld              = dp_fp_inst_data[`DIS_VEC_DSTE_VLD];








assign dp_fp_srcf0_vld      = ctrl_dp_fgpr_reuse_inst_dp_vld
                              ? dp_vec_fgpr_reuse_srcf0_vld
                              : dp_fp_inst_data[`DIS_VEC_SRCF0_VLD];
assign dp_fp_srcf1_vld      = ctrl_dp_fgpr_reuse_inst_dp_vld
                              ? dp_vec_fgpr_reuse_srcf1_vld
                              : dp_fp_inst_data[`DIS_VEC_SRCF1_VLD];
assign dp_fp_srcf2_vld      = ctrl_dp_fgpr_reuse_inst_dp_vld
                              ? dp_vec_fgpr_reuse_srcf2_vld
                              : dp_fp_inst_data[`DIS_VEC_SRCF2_VLD];
assign dp_fp_dstf_vld       = ctrl_dp_fgpr_reuse_inst_dp_vld
                              ? dp_vec_fgpr_reuse_dstf_vld
                              : dp_fp_inst_data[`DIS_VEC_DSTF_VLD];

assign dp_fp_srcf0_reg[4:0] = ctrl_dp_fgpr_reuse_inst_dp_vld
                              ? dp_vec_fgpr_reuse_srcf0_reg[4:0]
                              : dp_fp_inst_data[`DIS_VEC_SRCV0_REG-8:`DIS_VEC_SRCV0_REG-12];
assign dp_fp_srcf1_reg[4:0] = ctrl_dp_fgpr_reuse_inst_dp_vld
                              ? dp_vec_fgpr_reuse_srcf1_reg[4:0]
                              : dp_fp_inst_data[`DIS_VEC_SRCV1_REG-8:`DIS_VEC_SRCV1_REG-12];
assign dp_fp_srcf2_reg[4:0] = ctrl_dp_fgpr_reuse_inst_dp_vld
                              ? dp_vec_fgpr_reuse_srcf2_reg[4:0]
                              : dp_fp_inst_data[`DIS_VEC_SRCV2_REG-8:`DIS_VEC_SRCV2_REG-12];
assign dp_fp_dstf_reg[4:0]  = ctrl_dp_fgpr_reuse_inst_dp_vld
                              ? dp_vec_fgpr_reuse_dstf_reg[4:0]
                              : dp_fp_inst_data[`DIS_VEC_DSTV_REG-8:`DIS_VEC_DSTV_REG-12];




assign dp_ctrl_dis_fp_inst_dstf_vld       = dp_fp_dstf_vld;
assign dp_ctrl_dis_fp_inst_srcf0_vld      = dp_fp_srcf0_vld;
assign dp_ctrl_dis_fp_inst_srcf1_vld      = dp_fp_srcf1_vld;
assign dp_ctrl_dis_fp_inst_srcf2_vld      = dp_fp_srcf2_vld;

assign dp_ctrl_dis_fp_inst_srcf0_reg[4:0] = dp_fp_srcf0_reg[4:0];
assign dp_ctrl_dis_fp_inst_srcf1_reg[4:0] = dp_fp_srcf1_reg[4:0];
assign dp_ctrl_dis_fp_inst_srcf2_reg[4:0] = dp_fp_srcf2_reg[4:0];

assign dp_ctrl_dis_fp_inst_store     = dp_fp_inst_data[`DIS_VEC_EU-`EU_WIDTH+1+`EU_VLSU_SEL]
                                       && dp_fp_inst_data[`DIS_VEC_FUNC-`FUNC_WIDTH+1+`FUNC_STORE_SEL];
assign dp_ctrl_dis_fp_inst_wb_type   = dp_wb_inst_type;




assign dp_wbt_fp_srcv0_reg[4:0] = dp_fp_srcf0_reg[4:0];
assign dp_wbt_fp_srcv1_reg[4:0] = dp_fp_srcf1_reg[4:0];
assign dp_wbt_fp_srcv2_reg[4:0] = dp_fp_srcf2_reg[4:0];
assign dp_wbt_fp_dstv_reg[4:0]  = dp_fp_dstf_reg[4:0];
assign dp_wbt_fp_dstv_vld       = dp_fp_dstf_vld;



assign dp_wb_inst_type = ctrl_dp_fgpr_reuse_inst_dp_vld
                         ? 1'b0 : dp_fp_inst_data[`DIS_VEC_EU-`EU_WIDTH+1+`EU_VLSU_SEL];

assign dp_wbt_fp_dstv_type      = dp_wb_inst_type;







assign dp_gpr_fp_src0_reg[4:0] = dp_fp_srcf0_reg[4:0];
assign dp_gpr_fp_src1_reg[4:0] = dp_fp_srcf1_reg[4:0];
assign dp_gpr_fp_src2_reg[4:0] = dp_fp_srcf2_reg[4:0];




assign dp_dis_fp_inst_srcf0_fwd_vld = vpu_vidu_fp_fwd_vld
                                      && (dp_fp_srcf0_reg[4:0] == vpu_vidu_fp_fwd_reg[4:0]);
assign dp_dis_fp_inst_srcf1_fwd_vld = vpu_vidu_fp_fwd_vld
                                      && (dp_fp_srcf1_reg[4:0] == vpu_vidu_fp_fwd_reg[4:0]);
assign dp_dis_fp_inst_srcf2_fwd_vld = vpu_vidu_fp_fwd_vld
                                      && (dp_fp_srcf2_reg[4:0] == vpu_vidu_fp_fwd_reg[4:0]);



assign dp_dis_fp_inst_srcf2_rdy     = wbt_ctrl_fp_srcv2_info[`WB_VEC_VLD]
                                      || dp_dis_fp_inst_srcf2_fwd_vld
                                      || !dp_fp_inst_data[`DIS_VEC_SRCF2_VLD];

assign dp_dis_fp_inst_srcf2_vld     = dp_fp_srcf2_vld;




assign dp_dis_fp_inst_srcf0_data[63:0] = dp_dis_fp_inst_srcf0_fwd_vld
                                         ? vpu_vidu_fp_fwd_data[63:0]
                                         : gpr_fp_dp_src0_data[63:0];
assign dp_dis_fp_inst_srcf1_data[63:0] = dp_dis_fp_inst_srcf1_fwd_vld
                                         ? vpu_vidu_fp_fwd_data[63:0]
                                         : gpr_fp_dp_src1_data[63:0];
assign dp_dis_fp_inst_srcf2_data[63:0] = dp_dis_fp_inst_srcf2_fwd_vld
                                         ? vpu_vidu_fp_fwd_data[63:0]
                                         : gpr_fp_dp_src2_data[63:0];




assign vidu_vpu_vid_fp_inst_func[`FUNC_WIDTH-1:0] = dp_dis_fp_inst_func[`FUNC_WIDTH-1:0];
assign vidu_vpu_vid_fp_inst_eu[`EU_WIDTH-1:0]     = dp_dis_fp_inst_eu[`EU_WIDTH-1:0];
assign vidu_vpu_vid_fp_inst_dst_vld               = dp_dis_fp_inst_dst0_vld;
assign vidu_vpu_vid_fp_inst_dstf_vld              = dp_dis_fp_inst_dstf_vld;
assign vidu_vpu_vid_fp_inst_dste_vld              = dp_dis_fp_inst_dste_vld;
assign vidu_vpu_vid_fp_inst_dst_reg[5:0]          = dp_dis_fp_inst_dst0_reg[5:0];
assign vidu_vpu_vid_fp_inst_dstf_reg[4:0]         = dp_dis_fp_inst_dstf_reg[4:0];
assign vidu_vpu_vid_fp_inst_src1_data[63:0]       = dp_dis_fp_inst_src1_data[63:0];
assign vidu_vpu_vid_fp_inst_srcf0_data[63:0]      = dp_dis_fp_inst_srcf0_data[63:0];
assign vidu_vpu_vid_fp_inst_srcf1_data[63:0]      = dp_dis_fp_inst_srcf1_data[63:0];
assign vidu_vpu_vid_fp_inst_srcf2_data[63:0]      = dp_dis_fp_inst_srcf2_data[63:0];
assign vidu_vpu_vid_fp_inst_srcf2_rdy             = dp_dis_fp_inst_srcf2_rdy;
assign vidu_vpu_vid_fp_inst_srcf2_vld             = dp_dis_fp_inst_srcf2_vld;


endmodule
module aq_vidu_vid_dp_fp(
  ctrl_dp_fgpr_reuse_inst_dp_vld,
  dp_ctrl_dis_fp_inst_dstf_vld,
  dp_ctrl_dis_fp_inst_srcf0_reg,
  dp_ctrl_dis_fp_inst_srcf0_vld,
  dp_ctrl_dis_fp_inst_srcf1_reg,
  dp_ctrl_dis_fp_inst_srcf1_vld,
  dp_ctrl_dis_fp_inst_srcf2_reg,
  dp_ctrl_dis_fp_inst_srcf2_vld,
  dp_ctrl_dis_fp_inst_store,
  dp_ctrl_dis_fp_inst_wb_type,
  dp_gpr_fp_src0_reg,
  dp_gpr_fp_src1_reg,
  dp_gpr_fp_src2_reg,
  dp_vec_fgpr_reuse_dstf_reg,
  dp_vec_fgpr_reuse_dstf_vld,
  dp_vec_fgpr_reuse_srcf0_reg,
  dp_vec_fgpr_reuse_srcf0_vld,
  dp_vec_fgpr_reuse_srcf1_reg,
  dp_vec_fgpr_reuse_srcf1_vld,
  dp_vec_fgpr_reuse_srcf2_reg,
  dp_vec_fgpr_reuse_srcf2_vld,
  dp_wbt_fp_dstv_reg,
  dp_wbt_fp_dstv_type,
  dp_wbt_fp_dstv_vld,
  dp_wbt_fp_srcv0_reg,
  dp_wbt_fp_srcv1_reg,
  dp_wbt_fp_srcv2_reg,
  gpr_fp_dp_src0_data,
  gpr_fp_dp_src1_data,
  gpr_fp_dp_src2_data,
  idu_vidu_ex1_inst_data,
  split_fp_dp_inst_data,
  vidu_vpu_vid_fp_inst_dst_reg,
  vidu_vpu_vid_fp_inst_dst_vld,
  vidu_vpu_vid_fp_inst_dste_vld,
  vidu_vpu_vid_fp_inst_dstf_reg,
  vidu_vpu_vid_fp_inst_dstf_vld,
  vidu_vpu_vid_fp_inst_eu,
  vidu_vpu_vid_fp_inst_func,
  vidu_vpu_vid_fp_inst_src1_data,
  vidu_vpu_vid_fp_inst_srcf0_data,
  vidu_vpu_vid_fp_inst_srcf1_data,
  vidu_vpu_vid_fp_inst_srcf2_data,
  vidu_vpu_vid_fp_inst_srcf2_rdy,
  vidu_vpu_vid_fp_inst_srcf2_vld,
  vpu_rtu_ex1_fp_dirty,
  vpu_rtu_ex1_vec_dirty,
  vpu_vidu_fp_fwd_data,
  vpu_vidu_fp_fwd_reg,
  vpu_vidu_fp_fwd_vld,
  wbt_ctrl_fp_srcv2_info
);



input            ctrl_dp_fgpr_reuse_inst_dp_vld; 
input   [4  :0]  dp_vec_fgpr_reuse_dstf_reg;     
input            dp_vec_fgpr_reuse_dstf_vld;     
input   [4  :0]  dp_vec_fgpr_reuse_srcf0_reg;    
input            dp_vec_fgpr_reuse_srcf0_vld;    
input   [4  :0]  dp_vec_fgpr_reuse_srcf1_reg;    
input            dp_vec_fgpr_reuse_srcf1_vld;    
input   [4  :0]  dp_vec_fgpr_reuse_srcf2_reg;    
input            dp_vec_fgpr_reuse_srcf2_vld;    
input   [63 :0]  gpr_fp_dp_src0_data;            
input   [63 :0]  gpr_fp_dp_src1_data;            
input   [63 :0]  gpr_fp_dp_src2_data;            
input   [179:0]  idu_vidu_ex1_inst_data;         
input   [179:0]  split_fp_dp_inst_data;          
input   [63 :0]  vpu_vidu_fp_fwd_data;           
input   [4  :0]  vpu_vidu_fp_fwd_reg;            
input            vpu_vidu_fp_fwd_vld;            
input   [2  :0]  wbt_ctrl_fp_srcv2_info;         
output           dp_ctrl_dis_fp_inst_dstf_vld;   
output  [4  :0]  dp_ctrl_dis_fp_inst_srcf0_reg;  
output           dp_ctrl_dis_fp_inst_srcf0_vld;  
output  [4  :0]  dp_ctrl_dis_fp_inst_srcf1_reg;  
output           dp_ctrl_dis_fp_inst_srcf1_vld;  
output  [4  :0]  dp_ctrl_dis_fp_inst_srcf2_reg;  
output           dp_ctrl_dis_fp_inst_srcf2_vld;  
output           dp_ctrl_dis_fp_inst_store;      
output           dp_ctrl_dis_fp_inst_wb_type;    
output  [4  :0]  dp_gpr_fp_src0_reg;             
output  [4  :0]  dp_gpr_fp_src1_reg;             
output  [4  :0]  dp_gpr_fp_src2_reg;             
output  [4  :0]  dp_wbt_fp_dstv_reg;             
output           dp_wbt_fp_dstv_type;            
output           dp_wbt_fp_dstv_vld;             
output  [4  :0]  dp_wbt_fp_srcv0_reg;            
output  [4  :0]  dp_wbt_fp_srcv1_reg;            
output  [4  :0]  dp_wbt_fp_srcv2_reg;            
output  [5  :0]  vidu_vpu_vid_fp_inst_dst_reg;   
output           vidu_vpu_vid_fp_inst_dst_vld;   
output           vidu_vpu_vid_fp_inst_dste_vld;  
output  [4  :0]  vidu_vpu_vid_fp_inst_dstf_reg;  
output           vidu_vpu_vid_fp_inst_dstf_vld;  
output  [9  :0]  vidu_vpu_vid_fp_inst_eu;        
output  [19 :0]  vidu_vpu_vid_fp_inst_func;      
output  [63 :0]  vidu_vpu_vid_fp_inst_src1_data; 
output  [63 :0]  vidu_vpu_vid_fp_inst_srcf0_data; 
output  [63 :0]  vidu_vpu_vid_fp_inst_srcf1_data; 
output  [63 :0]  vidu_vpu_vid_fp_inst_srcf2_data; 
output           vidu_vpu_vid_fp_inst_srcf2_rdy; 
output           vidu_vpu_vid_fp_inst_srcf2_vld; 
output           vpu_rtu_ex1_fp_dirty;           
output           vpu_rtu_ex1_vec_dirty;          




wire             ctrl_dp_fgpr_reuse_inst_dp_vld; 
wire             dp_ctrl_dis_fp_inst_dstf_vld;   
wire    [4  :0]  dp_ctrl_dis_fp_inst_srcf0_reg;  
wire             dp_ctrl_dis_fp_inst_srcf0_vld;  
wire    [4  :0]  dp_ctrl_dis_fp_inst_srcf1_reg;  
wire             dp_ctrl_dis_fp_inst_srcf1_vld;  
wire    [4  :0]  dp_ctrl_dis_fp_inst_srcf2_reg;  
wire             dp_ctrl_dis_fp_inst_srcf2_vld;  
wire             dp_ctrl_dis_fp_inst_store;      
wire             dp_ctrl_dis_fp_inst_wb_type;    
wire    [5  :0]  dp_dis_fp_inst_dst0_reg;        
wire             dp_dis_fp_inst_dst0_vld;        
wire             dp_dis_fp_inst_dste_vld;        
wire    [4  :0]  dp_dis_fp_inst_dstf_reg;        
wire             dp_dis_fp_inst_dstf_vld;        
wire    [9  :0]  dp_dis_fp_inst_eu;              
wire    [19 :0]  dp_dis_fp_inst_func;            
wire    [63 :0]  dp_dis_fp_inst_src1_data;       
wire    [63 :0]  dp_dis_fp_inst_srcf0_data;      
wire             dp_dis_fp_inst_srcf0_fwd_vld;   
wire    [63 :0]  dp_dis_fp_inst_srcf1_data;      
wire             dp_dis_fp_inst_srcf1_fwd_vld;   
wire    [63 :0]  dp_dis_fp_inst_srcf2_data;      
wire             dp_dis_fp_inst_srcf2_fwd_vld;   
wire             dp_dis_fp_inst_srcf2_rdy;       
wire             dp_dis_fp_inst_srcf2_vld;       
wire    [4  :0]  dp_fp_dstf_reg;                 
wire             dp_fp_dstf_vld;                 
wire    [179:0]  dp_fp_inst_data;                
wire    [4  :0]  dp_fp_srcf0_reg;                
wire             dp_fp_srcf0_vld;                
wire    [4  :0]  dp_fp_srcf1_reg;                
wire             dp_fp_srcf1_vld;                
wire    [4  :0]  dp_fp_srcf2_reg;                
wire             dp_fp_srcf2_vld;                
wire    [4  :0]  dp_gpr_fp_src0_reg;             
wire    [4  :0]  dp_gpr_fp_src1_reg;             
wire    [4  :0]  dp_gpr_fp_src2_reg;             
wire    [4  :0]  dp_vec_fgpr_reuse_dstf_reg;     
wire             dp_vec_fgpr_reuse_dstf_vld;     
wire    [4  :0]  dp_vec_fgpr_reuse_srcf0_reg;    
wire             dp_vec_fgpr_reuse_srcf0_vld;    
wire    [4  :0]  dp_vec_fgpr_reuse_srcf1_reg;    
wire             dp_vec_fgpr_reuse_srcf1_vld;    
wire    [4  :0]  dp_vec_fgpr_reuse_srcf2_reg;    
wire             dp_vec_fgpr_reuse_srcf2_vld;    
wire             dp_wb_inst_type;                
wire    [4  :0]  dp_wbt_fp_dstv_reg;             
wire             dp_wbt_fp_dstv_type;            
wire             dp_wbt_fp_dstv_vld;             
wire    [4  :0]  dp_wbt_fp_srcv0_reg;            
wire    [4  :0]  dp_wbt_fp_srcv1_reg;            
wire    [4  :0]  dp_wbt_fp_srcv2_reg;            
wire    [63 :0]  gpr_fp_dp_src0_data;            
wire    [63 :0]  gpr_fp_dp_src1_data;            
wire    [63 :0]  gpr_fp_dp_src2_data;            
wire    [179:0]  idu_vidu_ex1_inst_data;         
wire    [179:0]  split_fp_dp_inst_data;          
wire    [5  :0]  vidu_vpu_vid_fp_inst_dst_reg;   
wire             vidu_vpu_vid_fp_inst_dst_vld;   
wire             vidu_vpu_vid_fp_inst_dste_vld;  
wire    [4  :0]  vidu_vpu_vid_fp_inst_dstf_reg;  
wire             vidu_vpu_vid_fp_inst_dstf_vld;  
wire    [9  :0]  vidu_vpu_vid_fp_inst_eu;        
wire    [19 :0]  vidu_vpu_vid_fp_inst_func;      
wire    [63 :0]  vidu_vpu_vid_fp_inst_src1_data; 
wire    [63 :0]  vidu_vpu_vid_fp_inst_srcf0_data; 
wire    [63 :0]  vidu_vpu_vid_fp_inst_srcf1_data; 
wire    [63 :0]  vidu_vpu_vid_fp_inst_srcf2_data; 
wire             vidu_vpu_vid_fp_inst_srcf2_rdy; 
wire             vidu_vpu_vid_fp_inst_srcf2_vld; 
wire             vpu_rtu_ex1_fp_dirty;           
wire             vpu_rtu_ex1_vec_dirty;          
wire    [63 :0]  vpu_vidu_fp_fwd_data;           
wire    [4  :0]  vpu_vidu_fp_fwd_reg;            
wire             vpu_vidu_fp_fwd_vld;            
wire    [2  :0]  wbt_ctrl_fp_srcv2_info;         






assign vpu_rtu_ex1_fp_dirty                 = idu_vidu_ex1_inst_data[`DIS_VEC_DSTF_VLD]
                                           || idu_vidu_ex1_inst_data[`DIS_VEC_DSTE_VLD];
assign vpu_rtu_ex1_vec_dirty                = idu_vidu_ex1_inst_data[`DIS_VEC_DSTV_VLD] || idu_vidu_ex1_inst_data[`DIS_VEC_DSTV_LATE_VLD];







assign dp_fp_inst_data[`DIS_VEC_WIDTH-1:0]  = split_fp_dp_inst_data[`DIS_VEC_WIDTH-1:0];




assign dp_dis_fp_inst_func[`FUNC_WIDTH-1:0] = dp_fp_inst_data[`DIS_VEC_FUNC:`DIS_VEC_FUNC-`FUNC_WIDTH+1];
assign dp_dis_fp_inst_eu[`EU_WIDTH-1:0]     = dp_fp_inst_data[`DIS_VEC_EU:`DIS_VEC_EU-`EU_WIDTH+1];
assign dp_dis_fp_inst_dstf_reg[4:0]         = dp_fp_inst_data[`DIS_VEC_DSTV_REG-8:`DIS_VEC_DSTV_REG-12];
assign dp_dis_fp_inst_src1_data[63:0]       = dp_fp_inst_data[`DIS_VEC_SRC1_DATA:`DIS_VEC_SRC1_DATA-63];
assign dp_dis_fp_inst_dst0_reg[5:0]         = dp_fp_inst_data[`DIS_VEC_DST0_REG:`DIS_VEC_DST0_REG-5];
assign dp_dis_fp_inst_dst0_vld              = dp_fp_inst_data[`DIS_VEC_DST0_VLD];
assign dp_dis_fp_inst_dstf_vld              = dp_fp_inst_data[`DIS_VEC_DSTF_VLD];
assign dp_dis_fp_inst_dste_vld              = dp_fp_inst_data[`DIS_VEC_DSTE_VLD];








assign dp_fp_srcf0_vld      = ctrl_dp_fgpr_reuse_inst_dp_vld
                              ? dp_vec_fgpr_reuse_srcf0_vld
                              : dp_fp_inst_data[`DIS_VEC_SRCF0_VLD];
assign dp_fp_srcf1_vld      = ctrl_dp_fgpr_reuse_inst_dp_vld
                              ? dp_vec_fgpr_reuse_srcf1_vld
                              : dp_fp_inst_data[`DIS_VEC_SRCF1_VLD];
assign dp_fp_srcf2_vld      = ctrl_dp_fgpr_reuse_inst_dp_vld
                              ? dp_vec_fgpr_reuse_srcf2_vld
                              : dp_fp_inst_data[`DIS_VEC_SRCF2_VLD];
assign dp_fp_dstf_vld       = ctrl_dp_fgpr_reuse_inst_dp_vld
                              ? dp_vec_fgpr_reuse_dstf_vld
                              : dp_fp_inst_data[`DIS_VEC_DSTF_VLD];

assign dp_fp_srcf0_reg[4:0] = ctrl_dp_fgpr_reuse_inst_dp_vld
                              ? dp_vec_fgpr_reuse_srcf0_reg[4:0]
                              : dp_fp_inst_data[`DIS_VEC_SRCV0_REG-8:`DIS_VEC_SRCV0_REG-12];
assign dp_fp_srcf1_reg[4:0] = ctrl_dp_fgpr_reuse_inst_dp_vld
                              ? dp_vec_fgpr_reuse_srcf1_reg[4:0]
                              : dp_fp_inst_data[`DIS_VEC_SRCV1_REG-8:`DIS_VEC_SRCV1_REG-12];
assign dp_fp_srcf2_reg[4:0] = ctrl_dp_fgpr_reuse_inst_dp_vld
                              ? dp_vec_fgpr_reuse_srcf2_reg[4:0]
                              : dp_fp_inst_data[`DIS_VEC_SRCV2_REG-8:`DIS_VEC_SRCV2_REG-12];
assign dp_fp_dstf_reg[4:0]  = ctrl_dp_fgpr_reuse_inst_dp_vld
                              ? dp_vec_fgpr_reuse_dstf_reg[4:0]
                              : dp_fp_inst_data[`DIS_VEC_DSTV_REG-8:`DIS_VEC_DSTV_REG-12];




assign dp_ctrl_dis_fp_inst_dstf_vld       = dp_fp_dstf_vld;
assign dp_ctrl_dis_fp_inst_srcf0_vld      = dp_fp_srcf0_vld;
assign dp_ctrl_dis_fp_inst_srcf1_vld      = dp_fp_srcf1_vld;
assign dp_ctrl_dis_fp_inst_srcf2_vld      = dp_fp_srcf2_vld;

assign dp_ctrl_dis_fp_inst_srcf0_reg[4:0] = dp_fp_srcf0_reg[4:0];
assign dp_ctrl_dis_fp_inst_srcf1_reg[4:0] = dp_fp_srcf1_reg[4:0];
assign dp_ctrl_dis_fp_inst_srcf2_reg[4:0] = dp_fp_srcf2_reg[4:0];

assign dp_ctrl_dis_fp_inst_store     = dp_fp_inst_data[`DIS_VEC_EU-`EU_WIDTH+1+`EU_VLSU_SEL]
                                       && dp_fp_inst_data[`DIS_VEC_FUNC-`FUNC_WIDTH+1+`FUNC_STORE_SEL];
assign dp_ctrl_dis_fp_inst_wb_type   = dp_wb_inst_type;




assign dp_wbt_fp_srcv0_reg[4:0] = dp_fp_srcf0_reg[4:0];
assign dp_wbt_fp_srcv1_reg[4:0] = dp_fp_srcf1_reg[4:0];
assign dp_wbt_fp_srcv2_reg[4:0] = dp_fp_srcf2_reg[4:0];
assign dp_wbt_fp_dstv_reg[4:0]  = dp_fp_dstf_reg[4:0];
assign dp_wbt_fp_dstv_vld       = dp_fp_dstf_vld;



assign dp_wb_inst_type = ctrl_dp_fgpr_reuse_inst_dp_vld
                         ? 1'b0 : dp_fp_inst_data[`DIS_VEC_EU-`EU_WIDTH+1+`EU_VLSU_SEL];

assign dp_wbt_fp_dstv_type      = dp_wb_inst_type;







assign dp_gpr_fp_src0_reg[4:0] = dp_fp_srcf0_reg[4:0];
assign dp_gpr_fp_src1_reg[4:0] = dp_fp_srcf1_reg[4:0];
assign dp_gpr_fp_src2_reg[4:0] = dp_fp_srcf2_reg[4:0];




assign dp_dis_fp_inst_srcf0_fwd_vld = vpu_vidu_fp_fwd_vld
                                      && (dp_fp_srcf0_reg[4:0] == vpu_vidu_fp_fwd_reg[4:0]);
assign dp_dis_fp_inst_srcf1_fwd_vld = vpu_vidu_fp_fwd_vld
                                      && (dp_fp_srcf1_reg[4:0] == vpu_vidu_fp_fwd_reg[4:0]);
assign dp_dis_fp_inst_srcf2_fwd_vld = vpu_vidu_fp_fwd_vld
                                      && (dp_fp_srcf2_reg[4:0] == vpu_vidu_fp_fwd_reg[4:0]);



assign dp_dis_fp_inst_srcf2_rdy     = wbt_ctrl_fp_srcv2_info[`WB_VEC_VLD]
                                      || dp_dis_fp_inst_srcf2_fwd_vld
                                      || !dp_fp_inst_data[`DIS_VEC_SRCF2_VLD];

assign dp_dis_fp_inst_srcf2_vld     = dp_fp_srcf2_vld;




assign dp_dis_fp_inst_srcf0_data[63:0] = dp_dis_fp_inst_srcf0_fwd_vld
                                         ? vpu_vidu_fp_fwd_data[63:0]
                                         : gpr_fp_dp_src0_data[63:0];
assign dp_dis_fp_inst_srcf1_data[63:0] = dp_dis_fp_inst_srcf1_fwd_vld
                                         ? vpu_vidu_fp_fwd_data[63:0]
                                         : gpr_fp_dp_src1_data[63:0];
assign dp_dis_fp_inst_srcf2_data[63:0] = dp_dis_fp_inst_srcf2_fwd_vld
                                         ? vpu_vidu_fp_fwd_data[63:0]
                                         : gpr_fp_dp_src2_data[63:0];




assign vidu_vpu_vid_fp_inst_func[`FUNC_WIDTH-1:0] = dp_dis_fp_inst_func[`FUNC_WIDTH-1:0];
assign vidu_vpu_vid_fp_inst_eu[`EU_WIDTH-1:0]     = dp_dis_fp_inst_eu[`EU_WIDTH-1:0];
assign vidu_vpu_vid_fp_inst_dst_vld               = dp_dis_fp_inst_dst0_vld;
assign vidu_vpu_vid_fp_inst_dstf_vld              = dp_dis_fp_inst_dstf_vld;
assign vidu_vpu_vid_fp_inst_dste_vld              = dp_dis_fp_inst_dste_vld;
assign vidu_vpu_vid_fp_inst_dst_reg[5:0]          = dp_dis_fp_inst_dst0_reg[5:0];
assign vidu_vpu_vid_fp_inst_dstf_reg[4:0]         = dp_dis_fp_inst_dstf_reg[4:0];
assign vidu_vpu_vid_fp_inst_src1_data[63:0]       = dp_dis_fp_inst_src1_data[63:0];
assign vidu_vpu_vid_fp_inst_srcf0_data[63:0]      = dp_dis_fp_inst_srcf0_data[63:0];
assign vidu_vpu_vid_fp_inst_srcf1_data[63:0]      = dp_dis_fp_inst_srcf1_data[63:0];
assign vidu_vpu_vid_fp_inst_srcf2_data[63:0]      = dp_dis_fp_inst_srcf2_data[63:0];
assign vidu_vpu_vid_fp_inst_srcf2_rdy             = dp_dis_fp_inst_srcf2_rdy;
assign vidu_vpu_vid_fp_inst_srcf2_vld             = dp_dis_fp_inst_srcf2_vld;


endmodule