data/full_repos/permissive/424312442/lab_5_seven seg displays/sources_1/new/basys_bcd.v
1: b'%Error: Cannot find file containing module: seg\n        ... Looked in:\n             data/full_repos/permissive/424312442/lab_5_seven/seg\n             data/full_repos/permissive/424312442/lab_5_seven/seg.v\n             data/full_repos/permissive/424312442/lab_5_seven/seg.sv\n             seg\n             seg.v\n             seg.sv\n             obj_dir/seg\n             obj_dir/seg.v\n             obj_dir/seg.sv\n%Error: Cannot find file containing module: displays/sources_1/new,data/full_repos/permissive/424312442\n%Error: Cannot find file containing module: data/full_repos/permissive/424312442/lab_5_seven\n%Error: Cannot find file containing module: displays/sources_1/new/basys_bcd.v\n%Error: Exiting due to 4 error(s)\n'
module basys_bcd(clk, sw, seg, an);
input clk;
input [15:0] sw;
output [6:0] seg;
output [3:0] an;

wire [3:0] BCD0;
wire [3:0] BCD1;
wire [3:0] BCD2;
wire [3:0] BCD3;

assign BCD0[0] = sw[0];
assign BCD0[1] = sw[1];
assign BCD0[2] = sw[2];
assign BCD0[3] = sw[3];
assign BCD1[0] = sw[4];
assign BCD1[1] = sw[5];
assign BCD1[2] = sw[6];
assign BCD1[3] = sw[7];
assign BCD2[0] = sw[8];
assign BCD2[1] = sw[9];
assign BCD2[2] = sw[10];
assign BCD2[3] = sw[11];
assign BCD3[0] = sw[12];
assign BCD3[1] = sw[13];
assign BCD3[2] = sw[14];
assign BCD3[3] = sw[15];

bcd_seg_complete(clk, BCD0, BCD1, BCD2, BCD3, an, seg);

endmodule
module basys_bcd(clk, sw, seg, an);

input clk;
input [15:0] sw;
output [6:0] seg;
output [3:0] an;

wire [3:0] BCD0;
wire [3:0] BCD1;
wire [3:0] BCD2;
wire [3:0] BCD3;

assign BCD0[0] = sw[0];
assign BCD0[1] = sw[1];
assign BCD0[2] = sw[2];
assign BCD0[3] = sw[3];
assign BCD1[0] = sw[4];
assign BCD1[1] = sw[5];
assign BCD1[2] = sw[6];
assign BCD1[3] = sw[7];
assign BCD2[0] = sw[8];
assign BCD2[1] = sw[9];
assign BCD2[2] = sw[10];
assign BCD2[3] = sw[11];
assign BCD3[0] = sw[12];
assign BCD3[1] = sw[13];
assign BCD3[2] = sw[14];
assign BCD3[3] = sw[15];

bcd_seg_complete(clk, BCD0, BCD1, BCD2, BCD3, an, seg);

endmodule