data/full_repos/permissive/493514142/verilog/rtl/FPU/FMADD_LZD_L3.v
1: b"%Error: data/full_repos/permissive/493514142/verilog/rtl/FPU/FMADD_LZD_L3.v:18: Cannot find file containing module: 'FPU_LZD_mux'\nFPU_LZD_mux  L3_0  (.in_val_2(L3_input_pos_val[7]),   .in_pos_2(L3_input_pos_val[6:4]),   .in_val_1(L3_input_pos_val[3]),  .in_pos_1(L3_input_pos_val[2:0]),  .out_pos(L3_wire_output_pos_0), .out_val(L3_wire_output_val_0));  defparam L3_0.layer = 3;\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/493514142/verilog/rtl/FPU,data/full_repos/permissive/493514142/FPU_LZD_mux\n             data/full_repos/permissive/493514142/verilog/rtl/FPU,data/full_repos/permissive/493514142/FPU_LZD_mux.v\n             data/full_repos/permissive/493514142/verilog/rtl/FPU,data/full_repos/permissive/493514142/FPU_LZD_mux.sv\n             FPU_LZD_mux\n             FPU_LZD_mux.v\n             FPU_LZD_mux.sv\n             obj_dir/FPU_LZD_mux\n             obj_dir/FPU_LZD_mux.v\n             obj_dir/FPU_LZD_mux.sv\n%Error: Exiting due to 1 error(s)\n"
module FMADD_LZD_layer_3 (L3_input_pos_val, L3_output_pos_val);

parameter layer = 3;


input [11 :0]L3_input_pos_val;


output [9 : 0] L3_output_pos_val;


wire L3_wire_output_val_0, L3_wire_output_val_1;
wire [layer : 0] L3_wire_output_pos_0, L3_wire_output_pos_1;


FPU_LZD_mux  L3_0  (.in_val_2(L3_input_pos_val[7]),   .in_pos_2(L3_input_pos_val[6:4]),   .in_val_1(L3_input_pos_val[3]),  .in_pos_1(L3_input_pos_val[2:0]),  .out_pos(L3_wire_output_pos_0), .out_val(L3_wire_output_val_0));  defparam L3_0.layer = 3;

assign L3_wire_output_val_1 = L3_input_pos_val[11];
assign L3_wire_output_pos_1 = {1'b1,L3_input_pos_val[10:8]};

assign L3_output_pos_val = 
{L3_wire_output_val_1, L3_wire_output_pos_1,
 L3_wire_output_val_0, L3_wire_output_pos_0};
endmodule
module FMADD_LZD_layer_3 (L3_input_pos_val, L3_output_pos_val);


parameter layer = 3;


input [11 :0]L3_input_pos_val;


output [9 : 0] L3_output_pos_val;


wire L3_wire_output_val_0, L3_wire_output_val_1;
wire [layer : 0] L3_wire_output_pos_0, L3_wire_output_pos_1;


FPU_LZD_mux  L3_0  (.in_val_2(L3_input_pos_val[7]),   .in_pos_2(L3_input_pos_val[6:4]),   .in_val_1(L3_input_pos_val[3]),  .in_pos_1(L3_input_pos_val[2:0]),  .out_pos(L3_wire_output_pos_0), .out_val(L3_wire_output_val_0));  defparam L3_0.layer = 3;

assign L3_wire_output_val_1 = L3_input_pos_val[11];
assign L3_wire_output_pos_1 = {1'b1,L3_input_pos_val[10:8]};

assign L3_output_pos_val = 
{L3_wire_output_val_1, L3_wire_output_pos_1,
 L3_wire_output_val_0, L3_wire_output_pos_0};
endmodule