data/full_repos/permissive/491135068/neg_DFF32.v
data/verilator_xmls/5bfdbc94-fa8a-4a62-8df8-215e7abb5778.xml
module neg_DFF32(Dselect, clk, D, Q);
    input [31:0] D;
    input clk, Dselect;
    output reg [31:0] Q;





    
    
    always @(negedge clk) begin
        if (Dselect==1'b1)  Q = D;
    end
endmodule
module neg_DFF32(Dselect, clk, D, Q);

    input [31:0] D;
    input clk, Dselect;
    output reg [31:0] Q;





    
    
    always @(negedge clk) begin
        if (Dselect==1'b1)  Q = D;
    end
endmodule