data/full_repos/permissive/46981098/mux/mux32_3to1.v
data/verilator_xmls/ce40cbf2-18cb-4542-b471-67836d2eba56.xml
module mux32_3to1 (out, in0, in1, in2, sel);
  	output reg  [31:0] out;
	input [31:0] in0;
	input [31:0] in1;
	input [31:0] in2;
  	input [1:0] sel;

  	always @(sel)
    begin
		case (sel)
			2'b00: out = in0;
			2'b01: out = in1;
			2'b10: out = in2;
		endcase
    end
endmodule
module mux32_3to1 (out, in0, in1, in2, sel);

  	output reg  [31:0] out;
	input [31:0] in0;
	input [31:0] in1;
	input [31:0] in2;
  	input [1:0] sel;

  	always @(sel)
    begin
		case (sel)
			2'b00: out = in0;
			2'b01: out = in1;
			2'b10: out = in2;
		endcase
    end
endmodule