data/full_repos/permissive/493019833/test/testcase/firrtl/RemoveMantissa.lo/reference/RemoveMantissa.lo.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/RemoveMantissa.lo/reference/RemoveMantissa.lo.v:34: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s SEL generates 1 bits.\n                                                                                                                            : ... In instance RemoveMantissa.s_shr_1\n    assign y = n < width ? in[width-1:n] : in[width-1:width-1];\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module RemoveMantissa(
    input clock,
    input reset,
    input [11:0] io_in,
    output [7:0] io_out
);
    wire [11:0] _reg___q;
    wire [11:0] _reg___d;
    DFF_POSCLK #(.width(12)) reg_ (
        .q(_reg___q),
        .d(_reg___d),
        .clk(clock)
    );
    SHR_SIGNED #(.width(12), .n(4)) s_shr_1 (
        .y(io_out),
        .in(_reg___q)
    );
    assign _reg___d = io_in;
endmodule
module RemoveMantissa(
    input clock,
    input reset,
    input [11:0] io_in,
    output [7:0] io_out
);

    wire [11:0] _reg___q;
    wire [11:0] _reg___d;
    DFF_POSCLK #(.width(12)) reg_ (
        .q(_reg___q),
        .d(_reg___d),
        .clk(clock)
    );
    SHR_SIGNED #(.width(12), .n(4)) s_shr_1 (
        .y(io_out),
        .in(_reg___q)
    );
    assign _reg___d = io_in;
endmodule