data/full_repos/permissive/435997396/fpga/boards/artya7-35t/e-class/fpga_top.v
1: b'%Error: data/full_repos/permissive/435997396/fpga/boards/artya7-35t/e-class/fpga_top.v:178: Cannot find file containing module: \'clk_divider\'\n   clk_divider clk_div (\n   ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/435997396/fpga/boards/artya7-35t/e-class,data/full_repos/permissive/435997396/clk_divider\n             data/full_repos/permissive/435997396/fpga/boards/artya7-35t/e-class,data/full_repos/permissive/435997396/clk_divider.v\n             data/full_repos/permissive/435997396/fpga/boards/artya7-35t/e-class,data/full_repos/permissive/435997396/clk_divider.sv\n             clk_divider\n             clk_divider.v\n             clk_divider.sv\n             obj_dir/clk_divider\n             obj_dir/clk_divider.v\n             obj_dir/clk_divider.sv\n%Error: data/full_repos/permissive/435997396/fpga/boards/artya7-35t/e-class/fpga_top.v:187: Cannot find file containing module: \'mkSoc\'\n   mkSoc core(\n   ^~~~~\n%Error: data/full_repos/permissive/435997396/fpga/boards/artya7-35t/e-class/fpga_top.v:278: Cannot find file containing module: \'xadc_wiz_0\'\nxadc_wiz_0 xadc_wiz_inst (\n^~~~~~~~~~\n%Error: data/full_repos/permissive/435997396/fpga/boards/artya7-35t/e-class/fpga_top.v:325: Cannot find file containing module: \'IOBUF\'\n      IOBUF gpio_iobuf_inst (\n      ^~~~~\n%Error: data/full_repos/permissive/435997396/fpga/boards/artya7-35t/e-class/fpga_top.v:334: Cannot find file containing module: \'IOBUF\'\n   IOBUF i2c_scl_inst(\n   ^~~~~\n%Error: data/full_repos/permissive/435997396/fpga/boards/artya7-35t/e-class/fpga_top.v:341: Cannot find file containing module: \'IOBUF\'\n   IOBUF i2c_sda_inst(\n   ^~~~~\n%Error: data/full_repos/permissive/435997396/fpga/boards/artya7-35t/e-class/fpga_top.v:349: Cannot find file containing module: \'STARTUPE2\'\n  STARTUPE2#(.PROG_USR("False"),\n  ^~~~~~~~~\n%Error: Exiting due to 7 error(s)\n'
module fpga_top
  (

  `ifndef JTAG_BSCAN2E
    input       pin_tck,
    input       pin_trst,
    input       pin_tms,
    input       pin_tdi,
    output      pin_tdo,
  `endif


    input         uart0_SIN,
    output        uart0_SOUT,
    input         uart1_SIN,
    output        uart1_SOUT,




    inout         i2c_sda,
    inout         i2c_scl,


   output       spi0_mosi,

   output       spi0_nss,
   input        spi0_miso,
   output       spi1_mosi,
   output       spi1_sclk,
   output       spi1_nss,
   input        spi1_miso,






    output pwm0,
    output pwm1,
    output pwm2,
    output pwm3,
    output pwm4,
    output pwm5,



    inout[31:0] gpio,


    input [1:0] interrupts,


    input         sys_rst,


    input         sys_clk,


    input vauxp0,
    input vauxn0,
    input vauxp4,
    input vauxn4,
    input vauxp5,
    input vauxn5,
    input vauxp6,
    input vauxn6,
    input vauxp7,
    input vauxn7,
    input vauxp12,
    input vauxp13,
    input vauxp14,
    input vauxp15,
    input vauxn12,
    input vauxn13,
    input vauxn14,
    input vauxn15,
    input vp_in,
    input vn_in
   );



   wire                            soc_reset;
   wire                            core_clk;
   wire                            locked;
   wire                            mmcm_locked;

   wire i2c_scl_out, i2c_scl_in, i2c_scl_out_en;
   wire i2c_sda_out, i2c_sda_in, i2c_sda_out_en;

   wire [31:0] gpio_in, gpio_out, gpio_out_en;


  `ifdef JTAG_BSCAN2E
    wire wire_tck_clk;
    wire wire_trst;
    wire wire_capture;
    wire wire_run_test;
    wire wire_sel;
    wire wire_shift;
    wire wire_tdi;
    wire wire_tms;
    wire wire_update;
    wire wire_tdo;

    BSCANE2 #(
      .JTAG_CHAIN(4)
    )
    bse2_inst (
      .CAPTURE(wire_capture),
      .DRCK(),
      .RESET(wire_trst),
      .RUNTEST(wire_run_test),
      .SEL(wire_sel),
      .SHIFT(wire_shift),
      .TCK(wire_tck_clk),
      .TDI(wire_tdi),
      .TMS(wire_tms),
      .UPDATE(wire_update),
      .TDO(wire_tdo)
    );
  `endif


    wire xadc_master_awvalid;
    wire [11-1 : 0] xadc_master_awaddr;
    wire xadc_master_m_awready_awready;
    wire xadc_master_wvalid;
    wire [32-1 : 0] xadc_master_wdata;
    wire [(32/8)-1 : 0] xadc_master_wstrb;
    wire xadc_master_m_wready_wready;
    wire xadc_master_m_bvalid_bvalid;
    wire [1:0] xadc_master_m_bvalid_bresp;
    wire xadc_master_bready;
    wire xadc_master_arvalid;
    wire [11-1 : 0] xadc_master_araddr;
    wire xadc_master_m_arready_arready;
    wire xadc_master_m_rvalid_rvalid;
    wire [1 : 0] xadc_master_m_rvalid_rresp;
    wire [32-1 : 0] xadc_master_m_rvalid_rdata;
    wire xadc_master_rready;


   assign soc_reset = locked;



   clk_divider clk_div (
                       .clk_in1(sys_clk),
                       .clk_out1(core_clk),
                       .resetn(sys_rst),
                       .locked(locked) );




   mkSoc core(

        .CLK(core_clk),
        .RST_N(soc_reset),

`ifndef JTAG_BSCAN2E

        .CLK_tck_clk(pin_tck),
        .RST_N_trst(pin_trst),
        .wire_tms_tms_in(pin_tms),
        .wire_tdi_tdi_in(pin_tdi),
        .wire_tdo(pin_tdo),
`else
        .CLK_tck_clk(wire_tck_clk),
        .RST_N_trst(~wire_trst),
        .wire_capture_capture_in(wire_capture),
        .wire_run_test_run_test_in(wire_run_test),
        .wire_sel_sel_in(wire_sel),
        .wire_shift_shift_in(wire_shift),
        .wire_tdi_tdi_in(wire_tdi),
        .wire_tms_tms_in(wire_tms),
        .wire_update_update_in(wire_update),
        .wire_tdo(wire_tdo),
`endif


        .gpio_io_gpio_in_inp(gpio_in),
        .gpio_io_gpio_out(gpio_out),
        .gpio_io_gpio_out_en(gpio_out_en),


        .pwm0_io_pwm_o(pwm0),
        .pwm1_io_pwm_o(pwm1),
        .pwm2_io_pwm_o(pwm2),
        .pwm3_io_pwm_o(pwm3),
        .pwm4_io_pwm_o(pwm4),
        .pwm5_io_pwm_o(pwm5),


        .spi0_io_mosi(spi0_mosi),
        .spi0_io_sclk(spi0_sclk),
        .spi0_io_nss(spi0_nss),
	      .spi0_io_miso_dat(spi0_miso),
        .spi1_io_mosi(spi1_mosi),
        .spi1_io_sclk(spi1_sclk),
        .spi1_io_nss(spi1_nss),
	      .spi1_io_miso_dat(spi1_miso),






        .uart0_io_SIN(uart0_SIN),
        .uart0_io_SOUT(uart0_SOUT),
        .uart1_io_SIN(uart1_SIN),
        .uart1_io_SOUT(uart1_SOUT),




        .i2c_out_scl_out (i2c_scl_out),
        .i2c_out_scl_in_in(i2c_scl_in),
        .i2c_out_scl_out_en(i2c_scl_out_en),
        .i2c_out_sda_out(i2c_sda_out),
        .i2c_out_sda_in_in(i2c_sda_in),
        .i2c_out_sda_out_en(i2c_sda_out_en),


        .xadc_master_awvalid(xadc_master_awvalid),
        .xadc_master_awaddr(xadc_master_awaddr),
        .xadc_master_m_awready_awready(xadc_master_m_awready_awready),
        .xadc_master_wvalid(xadc_master_wvalid),
        .xadc_master_wdata(xadc_master_wdata),
        .xadc_master_wstrb(xadc_master_wstrb),
        .xadc_master_m_wready_wready(xadc_master_m_wready_wready),
        .xadc_master_m_bvalid_bvalid(xadc_master_m_bvalid_bvalid),
        .xadc_master_m_bvalid_bresp(xadc_master_m_bvalid_bresp),
        .xadc_master_bready(xadc_master_bready),
        .xadc_master_arvalid(xadc_master_arvalid),
        .xadc_master_araddr(xadc_master_araddr),
        .xadc_master_m_arready_arready(xadc_master_m_arready_arready),
        .xadc_master_m_rvalid_rvalid(xadc_master_m_rvalid_rvalid),
        .xadc_master_m_rvalid_rresp(xadc_master_m_rvalid_rresp),
        .xadc_master_m_rvalid_rdata(xadc_master_m_rvalid_rdata),
        .xadc_master_rready(xadc_master_rready),

        .ext_interrupts_i(interrupts)
   );


xadc_wiz_0 xadc_wiz_inst (
        .s_axi_aclk      (core_clk),
        .s_axi_aresetn   (soc_reset),
        .s_axi_awaddr    (xadc_master_awaddr),
        .s_axi_awvalid   (xadc_master_awvalid),
        .s_axi_awready   (xadc_master_m_awready_awready),
        .s_axi_wdata     (xadc_master_wdata),
        .s_axi_wstrb     (xadc_master_wstrb),
        .s_axi_wvalid    (xadc_master_wvalid),
        .s_axi_wready    (xadc_master_m_wready_wready),
        .s_axi_bresp     (xadc_master_m_bvalid_bresp),
        .s_axi_bvalid    (xadc_master_m_bvalid_bvalid),
        .s_axi_bready    (xadc_master_bready),
        .s_axi_araddr    (xadc_master_araddr),
        .s_axi_arvalid   (xadc_master_arvalid),
        .s_axi_arready   (xadc_master_m_arready_arready),
        .s_axi_rdata     (xadc_master_m_rvalid_rdata),
        .s_axi_rresp     (xadc_master_m_rvalid_rresp),
        .s_axi_rvalid    (xadc_master_m_rvalid_rvalid),
        .s_axi_rready    (xadc_master_rready),
        .vauxp0 (vauxp0),
        .vauxn0 (vauxn0),
        .vauxp4 (vauxp4),
        .vauxn4 (vauxn4),
        .vauxp5 (vauxp5),
        .vauxn5 (vauxn5),
        .vauxp6 (vauxp6),
        .vauxn6 (vauxn6),
        .vauxp7 (vauxp7),
        .vauxn7 (vauxn7),
        .vauxp12 (vauxp12),
        .vauxn12 (vauxn12),
        .vauxp13 (vauxp13),
        .vauxn13 (vauxn13),
        .vauxp14 (vauxp14),
        .vauxn14 (vauxn14),
        .vauxp15 (vauxp15),
        .vauxn15 (vauxn15),
        .vp_in (vp_in),
        .vn_in (vn_in)
          );


   genvar index;
   generate
   for(index=0; index<32; index= index+1)
      begin: connect_gpio_tristates
      IOBUF gpio_iobuf_inst (
             .O(gpio_in[index]),
             .IO(gpio[index]),
             .I(gpio_out[index]),
             .T(~gpio_out_en[index])
				 );
      end
   endgenerate

   IOBUF i2c_scl_inst(
             .O(i2c_scl_in),
             .IO(i2c_scl),
             .I(i2c_scl_out),
             .T(~i2c_scl_out_en)
         );

   IOBUF i2c_sda_inst(
             .O(i2c_sda_in),
             .IO(i2c_sda),
             .I(i2c_sda_out),
             .T(~i2c_sda_out_en)
         );


	 STARTUPE2#(.PROG_USR("False"),
               .SIM_CCLK_FREQ(0.0))   startupe2_inst1(
               .CFGCLK(open),
               .CFGMCLK(open),
               .EOS(open),
               .PREQ(open),
               .CLK(0),
               .GSR(0),
               .GTS(0),
               .KEYCLEARB(0),
               .PACK(0),
               .USRCCLKO(spi0_sclk),
               .USRCCLKTS(0),
               .USRDONEO(1),
               .USRDONETS(1));

endmodule
module fpga_top
  (

  `ifndef JTAG_BSCAN2E
    input       pin_tck,
    input       pin_trst,
    input       pin_tms,
    input       pin_tdi,
    output      pin_tdo,
  `endif


    input         uart0_SIN,
    output        uart0_SOUT,
    input         uart1_SIN,
    output        uart1_SOUT,




    inout         i2c_sda,
    inout         i2c_scl,


   output       spi0_mosi,

   output       spi0_nss,
   input        spi0_miso,
   output       spi1_mosi,
   output       spi1_sclk,
   output       spi1_nss,
   input        spi1_miso,






    output pwm0,
    output pwm1,
    output pwm2,
    output pwm3,
    output pwm4,
    output pwm5,



    inout[31:0] gpio,


    input [1:0] interrupts,


    input         sys_rst,


    input         sys_clk,


    input vauxp0,
    input vauxn0,
    input vauxp4,
    input vauxn4,
    input vauxp5,
    input vauxn5,
    input vauxp6,
    input vauxn6,
    input vauxp7,
    input vauxn7,
    input vauxp12,
    input vauxp13,
    input vauxp14,
    input vauxp15,
    input vauxn12,
    input vauxn13,
    input vauxn14,
    input vauxn15,
    input vp_in,
    input vn_in
   );




   wire                            soc_reset;
   wire                            core_clk;
   wire                            locked;
   wire                            mmcm_locked;

   wire i2c_scl_out, i2c_scl_in, i2c_scl_out_en;
   wire i2c_sda_out, i2c_sda_in, i2c_sda_out_en;

   wire [31:0] gpio_in, gpio_out, gpio_out_en;


  `ifdef JTAG_BSCAN2E
    wire wire_tck_clk;
    wire wire_trst;
    wire wire_capture;
    wire wire_run_test;
    wire wire_sel;
    wire wire_shift;
    wire wire_tdi;
    wire wire_tms;
    wire wire_update;
    wire wire_tdo;

    BSCANE2 #(
      .JTAG_CHAIN(4)
    )
    bse2_inst (
      .CAPTURE(wire_capture),
      .DRCK(),
      .RESET(wire_trst),
      .RUNTEST(wire_run_test),
      .SEL(wire_sel),
      .SHIFT(wire_shift),
      .TCK(wire_tck_clk),
      .TDI(wire_tdi),
      .TMS(wire_tms),
      .UPDATE(wire_update),
      .TDO(wire_tdo)
    );
  `endif


    wire xadc_master_awvalid;
    wire [11-1 : 0] xadc_master_awaddr;
    wire xadc_master_m_awready_awready;
    wire xadc_master_wvalid;
    wire [32-1 : 0] xadc_master_wdata;
    wire [(32/8)-1 : 0] xadc_master_wstrb;
    wire xadc_master_m_wready_wready;
    wire xadc_master_m_bvalid_bvalid;
    wire [1:0] xadc_master_m_bvalid_bresp;
    wire xadc_master_bready;
    wire xadc_master_arvalid;
    wire [11-1 : 0] xadc_master_araddr;
    wire xadc_master_m_arready_arready;
    wire xadc_master_m_rvalid_rvalid;
    wire [1 : 0] xadc_master_m_rvalid_rresp;
    wire [32-1 : 0] xadc_master_m_rvalid_rdata;
    wire xadc_master_rready;


   assign soc_reset = locked;



   clk_divider clk_div (
                       .clk_in1(sys_clk),
                       .clk_out1(core_clk),
                       .resetn(sys_rst),
                       .locked(locked) );




   mkSoc core(

        .CLK(core_clk),
        .RST_N(soc_reset),

`ifndef JTAG_BSCAN2E

        .CLK_tck_clk(pin_tck),
        .RST_N_trst(pin_trst),
        .wire_tms_tms_in(pin_tms),
        .wire_tdi_tdi_in(pin_tdi),
        .wire_tdo(pin_tdo),
`else
        .CLK_tck_clk(wire_tck_clk),
        .RST_N_trst(~wire_trst),
        .wire_capture_capture_in(wire_capture),
        .wire_run_test_run_test_in(wire_run_test),
        .wire_sel_sel_in(wire_sel),
        .wire_shift_shift_in(wire_shift),
        .wire_tdi_tdi_in(wire_tdi),
        .wire_tms_tms_in(wire_tms),
        .wire_update_update_in(wire_update),
        .wire_tdo(wire_tdo),
`endif


        .gpio_io_gpio_in_inp(gpio_in),
        .gpio_io_gpio_out(gpio_out),
        .gpio_io_gpio_out_en(gpio_out_en),


        .pwm0_io_pwm_o(pwm0),
        .pwm1_io_pwm_o(pwm1),
        .pwm2_io_pwm_o(pwm2),
        .pwm3_io_pwm_o(pwm3),
        .pwm4_io_pwm_o(pwm4),
        .pwm5_io_pwm_o(pwm5),


        .spi0_io_mosi(spi0_mosi),
        .spi0_io_sclk(spi0_sclk),
        .spi0_io_nss(spi0_nss),
	      .spi0_io_miso_dat(spi0_miso),
        .spi1_io_mosi(spi1_mosi),
        .spi1_io_sclk(spi1_sclk),
        .spi1_io_nss(spi1_nss),
	      .spi1_io_miso_dat(spi1_miso),






        .uart0_io_SIN(uart0_SIN),
        .uart0_io_SOUT(uart0_SOUT),
        .uart1_io_SIN(uart1_SIN),
        .uart1_io_SOUT(uart1_SOUT),




        .i2c_out_scl_out (i2c_scl_out),
        .i2c_out_scl_in_in(i2c_scl_in),
        .i2c_out_scl_out_en(i2c_scl_out_en),
        .i2c_out_sda_out(i2c_sda_out),
        .i2c_out_sda_in_in(i2c_sda_in),
        .i2c_out_sda_out_en(i2c_sda_out_en),


        .xadc_master_awvalid(xadc_master_awvalid),
        .xadc_master_awaddr(xadc_master_awaddr),
        .xadc_master_m_awready_awready(xadc_master_m_awready_awready),
        .xadc_master_wvalid(xadc_master_wvalid),
        .xadc_master_wdata(xadc_master_wdata),
        .xadc_master_wstrb(xadc_master_wstrb),
        .xadc_master_m_wready_wready(xadc_master_m_wready_wready),
        .xadc_master_m_bvalid_bvalid(xadc_master_m_bvalid_bvalid),
        .xadc_master_m_bvalid_bresp(xadc_master_m_bvalid_bresp),
        .xadc_master_bready(xadc_master_bready),
        .xadc_master_arvalid(xadc_master_arvalid),
        .xadc_master_araddr(xadc_master_araddr),
        .xadc_master_m_arready_arready(xadc_master_m_arready_arready),
        .xadc_master_m_rvalid_rvalid(xadc_master_m_rvalid_rvalid),
        .xadc_master_m_rvalid_rresp(xadc_master_m_rvalid_rresp),
        .xadc_master_m_rvalid_rdata(xadc_master_m_rvalid_rdata),
        .xadc_master_rready(xadc_master_rready),

        .ext_interrupts_i(interrupts)
   );


xadc_wiz_0 xadc_wiz_inst (
        .s_axi_aclk      (core_clk),
        .s_axi_aresetn   (soc_reset),
        .s_axi_awaddr    (xadc_master_awaddr),
        .s_axi_awvalid   (xadc_master_awvalid),
        .s_axi_awready   (xadc_master_m_awready_awready),
        .s_axi_wdata     (xadc_master_wdata),
        .s_axi_wstrb     (xadc_master_wstrb),
        .s_axi_wvalid    (xadc_master_wvalid),
        .s_axi_wready    (xadc_master_m_wready_wready),
        .s_axi_bresp     (xadc_master_m_bvalid_bresp),
        .s_axi_bvalid    (xadc_master_m_bvalid_bvalid),
        .s_axi_bready    (xadc_master_bready),
        .s_axi_araddr    (xadc_master_araddr),
        .s_axi_arvalid   (xadc_master_arvalid),
        .s_axi_arready   (xadc_master_m_arready_arready),
        .s_axi_rdata     (xadc_master_m_rvalid_rdata),
        .s_axi_rresp     (xadc_master_m_rvalid_rresp),
        .s_axi_rvalid    (xadc_master_m_rvalid_rvalid),
        .s_axi_rready    (xadc_master_rready),
        .vauxp0 (vauxp0),
        .vauxn0 (vauxn0),
        .vauxp4 (vauxp4),
        .vauxn4 (vauxn4),
        .vauxp5 (vauxp5),
        .vauxn5 (vauxn5),
        .vauxp6 (vauxp6),
        .vauxn6 (vauxn6),
        .vauxp7 (vauxp7),
        .vauxn7 (vauxn7),
        .vauxp12 (vauxp12),
        .vauxn12 (vauxn12),
        .vauxp13 (vauxp13),
        .vauxn13 (vauxn13),
        .vauxp14 (vauxp14),
        .vauxn14 (vauxn14),
        .vauxp15 (vauxp15),
        .vauxn15 (vauxn15),
        .vp_in (vp_in),
        .vn_in (vn_in)
          );


   genvar index;
   generate
   for(index=0; index<32; index= index+1)
      begin: connect_gpio_tristates
      IOBUF gpio_iobuf_inst (
             .O(gpio_in[index]),
             .IO(gpio[index]),
             .I(gpio_out[index]),
             .T(~gpio_out_en[index])
				 );
      end
   endgenerate

   IOBUF i2c_scl_inst(
             .O(i2c_scl_in),
             .IO(i2c_scl),
             .I(i2c_scl_out),
             .T(~i2c_scl_out_en)
         );

   IOBUF i2c_sda_inst(
             .O(i2c_sda_in),
             .IO(i2c_sda),
             .I(i2c_sda_out),
             .T(~i2c_sda_out_en)
         );


	 STARTUPE2#(.PROG_USR("False"),
               .SIM_CCLK_FREQ(0.0))   startupe2_inst1(
               .CFGCLK(open),
               .CFGMCLK(open),
               .EOS(open),
               .PREQ(open),
               .CLK(0),
               .GSR(0),
               .GTS(0),
               .KEYCLEARB(0),
               .PACK(0),
               .USRCCLKO(spi0_sclk),
               .USRCCLKTS(0),
               .USRDONEO(1),
               .USRDONETS(1));

endmodule