data/full_repos/permissive/518460376/verilog/rtl/ips/fpu/hdl/fpu_v0.1/fpu_norm.v
1: b'%Error: data/full_repos/permissive/518460376/verilog/rtl/ips/fpu/hdl/fpu_v0.1/fpu_norm.v:82: Cannot find file containing module: \'fpu_ff\'\n fpu_ff #(.LEN(C_MANT_PRENORM)) LOD(\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/518460376/verilog/rtl/ips/fpu/hdl/fpu_v0.1,data/full_repos/permissive/518460376/fpu_ff\n             data/full_repos/permissive/518460376/verilog/rtl/ips/fpu/hdl/fpu_v0.1,data/full_repos/permissive/518460376/fpu_ff.v\n             data/full_repos/permissive/518460376/verilog/rtl/ips/fpu/hdl/fpu_v0.1,data/full_repos/permissive/518460376/fpu_ff.sv\n             fpu_ff\n             fpu_ff.v\n             fpu_ff.sv\n             obj_dir/fpu_ff\n             obj_dir/fpu_ff.v\n             obj_dir/fpu_ff.sv\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/fpu/hdl/fpu_v0.1/fpu_norm.v:89: Operator EQ expects 10 bits on the RHS, but RHS\'s VARREF \'C_EXP_ZERO\' generates 8 bits.\n                                                                                                   : ... In instance fpu_norm\n assign Denormals_shift_add_D = (~Mant_zero_S & (Exp_in_DI == C_EXP_ZERO)) & ((OP_SI != C_FPU_MUL_CMD) | (~Mant_in_DI[C_MANT_PRENORM - 1] & ~Mant_in_DI[C_MANT_PRENORM - 2]));\n                                                           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/fpu/hdl/fpu_v0.1/fpu_norm.v:90: Operator EQ expects 10 bits on the RHS, but RHS\'s VARREF \'C_EXP_ZERO\' generates 8 bits.\n                                                                                                   : ... In instance fpu_norm\n assign Denormals_exp_add_D = (Mant_in_DI[C_MANT_PRENORM - 2] & (Exp_in_DI == C_EXP_ZERO)) & ((OP_SI == C_FPU_ADD_CMD) | (OP_SI == C_FPU_SUB_CMD));\n                                                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/fpu/hdl/fpu_v0.1/fpu_norm.v:92: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'Denormals_shift_add_D\' generates 1 bits.\n                                                                                                   : ... In instance fpu_norm\n assign Mant_shAmt_D = (Denormal_S ? Exp_in_DI + Denormals_shift_add_D : Mant_leadingOne_D);\n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/fpu/hdl/fpu_v0.1/fpu_norm.v:92: Operator COND expects 10 bits on the Conditional False, but Conditional False\'s VARREF \'Mant_leadingOne_D\' generates 6 bits.\n                                                                                                   : ... In instance fpu_norm\n assign Mant_shAmt_D = (Denormal_S ? Exp_in_DI + Denormals_shift_add_D : Mant_leadingOne_D);\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/fpu/hdl/fpu_v0.1/fpu_norm.v:100: Operator FUNCREF \'sv2v_cast_F3481\' expects 52 bits on the Function Argument, but Function Argument\'s VARREF \'Mant_in_DI\' generates 24 bits.\n                                                                                                    : ... In instance fpu_norm\n  temp = sv2v_cast_F3481(Mant_in_DI) << Mant_shAmt2_D;\n         ^~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/fpu/hdl/fpu_v0.1/fpu_norm.v:110: Operator ADD expects 32 or 10 bits on the RHS, but RHS\'s VARREF \'Denormals_exp_add_D\' generates 1 bits.\n                                                                                                    : ... In instance fpu_norm\n assign Exp_norm_D = ((Exp_in_DI - C_EXP_PRENORM\'($signed(Mant_leadingOne_D))) + 1) + Denormals_exp_add_D;\n                                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/fpu/hdl/fpu_v0.1/fpu_norm.v:111: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'Mant_renorm_S\' generates 1 bits.\n                                                                                                    : ... In instance fpu_norm\n assign Exp_rounded_D = Exp_norm_D + Mant_renorm_S;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/fpu/hdl/fpu_v0.1/fpu_norm.v:139: Operator ADD expects 25 bits on the RHS, but RHS\'s VARREF \'Mant_roundUp_S\' generates 1 bits.\n                                                                                                    : ... In instance fpu_norm\n assign Mant_upperRounded_D = Mant_upper_D + Mant_roundUp_S;\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/518460376/verilog/rtl/ips/fpu/hdl/fpu_v0.1/fpu_norm.v:141: Operator ASSIGNW expects 24 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 25 bits.\n                                                                                                    : ... In instance fpu_norm\n assign Mant_res_DO = Mant_upperRounded_D >> (Mant_renorm_S & ~Denormal_S);\n                    ^\n%Error: Exiting due to 1 error(s), 9 warning(s)\n'
function automatic [(((C_MANT_PRENORM + C_MANT) + 4) >= 0 ? (C_MANT_PRENORM + C_MANT) + 5 : 1 - ((C_MANT_PRENORM + C_MANT) + 4)) - 1:0] sv2v_cast_F3481;
		input reg [(((C_MANT_PRENORM + C_MANT) + 4) >= 0 ? (C_MANT_PRENORM + C_MANT) + 5 : 1 - ((C_MANT_PRENORM + C_MANT) + 4)) - 1:0] inp;
		sv2v_cast_F3481 = inp;
	endfunction
function automatic [(((C_MANT_PRENORM + C_MANT) + 4) >= 0 ? (C_MANT_PRENORM + C_MANT) + 5 : 1 - ((C_MANT_PRENORM + C_MANT) + 4)) - 1:0] sv2v_cast_F3481;

		input reg [(((C_MANT_PRENORM + C_MANT) + 4) >= 0 ? (C_MANT_PRENORM + C_MANT) + 5 : 1 - ((C_MANT_PRENORM + C_MANT) + 4)) - 1:0] inp;
		sv2v_cast_F3481 = inp;
	endfunction