data/full_repos/permissive/424376038/src/NES_Nexys4.v
1: b'%Error: data/full_repos/permissive/424376038/src/NES_Nexys4.v:160: Duplicate declaration of signal: \'cycle\'\n                                                                 : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n  wire [8:0] cycle;\n             ^~~~~\n        data/full_repos/permissive/424376038/src/NES_Nexys4.v:138: ... Location of original declaration\n       output [8:0] cycle,\n                    ^~~~~\n%Error: data/full_repos/permissive/424376038/src/NES_Nexys4.v:161: Duplicate declaration of signal: \'scanline\'\n  wire [8:0] scanline;\n             ^~~~~~~~\n        data/full_repos/permissive/424376038/src/NES_Nexys4.v:139: ... Location of original declaration\n       output [8:0] scanline,\n                    ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/424376038/src/NES_Nexys4.v:224: Signal definition not found, creating implicitly: \'loader_write\'\n                                                                            : ... Suggested alternative: \'loader_done\'\n                          memory_write && run_mem || loader_write,\n                                                     ^~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module GameLoader(input clk, 
						input [127:0] ines_in,
                  output [31:0] mapper_flags,
                  output reg done);
  wire [7:0] ines[0:15];
  
  assign ines[0][7:0] = ines_in[127:120];
  assign ines[1][7:0] = ines_in[119:112];
  assign ines[2][7:0] = ines_in[111:104];
  assign ines[3][7:0] = ines_in[103:96];
  assign ines[4][7:0] = ines_in[95:88];
  assign ines[5][7:0] = ines_in[87:80];
  assign ines[6][7:0] = ines_in[79:72];
  assign ines[7][7:0] = ines_in[71:64];
  assign ines[8][7:0] = ines_in[63:56];
  assign ines[9][7:0] = ines_in[55:48];
  assign ines[10][7:0] = ines_in[47:40];
  assign ines[11][7:0] = ines_in[39:32];
  assign ines[12][7:0] = ines_in[31:24];
  assign ines[13][7:0] = ines_in[23:16];
  assign ines[14][7:0] = ines_in[15:8];
  assign ines[15][7:0] = ines_in[7:0];
  
  wire [7:0] prgrom = ines[4];
  wire [7:0] chrrom = ines[5];
  
  wire [2:0] prg_size = prgrom <= 1  ? 0 :
                        prgrom <= 2  ? 1 : 
                        prgrom <= 4  ? 2 : 
                        prgrom <= 8  ? 3 : 
                        prgrom <= 16 ? 4 : 
                        prgrom <= 32 ? 5 : 
                        prgrom <= 64 ? 6 : 7;
                        
  wire [2:0] chr_size = chrrom <= 1  ? 0 : 
                        chrrom <= 2  ? 1 : 
                        chrrom <= 4  ? 2 : 
                        chrrom <= 8  ? 3 : 
                        chrrom <= 16 ? 4 : 
                        chrrom <= 32 ? 5 : 
                        chrrom <= 64 ? 6 : 7;
  
  wire [7:0] mapper = {ines[7][7:4], ines[6][7:4]};
  wire has_chr_ram = (chrrom == 0);
  assign mapper_flags = {16'b0, has_chr_ram, ines[6][0], chr_size, prg_size, mapper};
  always @(posedge clk) begin
	  done = 1;
  end
endmodule
module GameLoader(input clk, 
						input [127:0] ines_in,
                  output [31:0] mapper_flags,
                  output reg done);

  wire [7:0] ines[0:15];
  
  assign ines[0][7:0] = ines_in[127:120];
  assign ines[1][7:0] = ines_in[119:112];
  assign ines[2][7:0] = ines_in[111:104];
  assign ines[3][7:0] = ines_in[103:96];
  assign ines[4][7:0] = ines_in[95:88];
  assign ines[5][7:0] = ines_in[87:80];
  assign ines[6][7:0] = ines_in[79:72];
  assign ines[7][7:0] = ines_in[71:64];
  assign ines[8][7:0] = ines_in[63:56];
  assign ines[9][7:0] = ines_in[55:48];
  assign ines[10][7:0] = ines_in[47:40];
  assign ines[11][7:0] = ines_in[39:32];
  assign ines[12][7:0] = ines_in[31:24];
  assign ines[13][7:0] = ines_in[23:16];
  assign ines[14][7:0] = ines_in[15:8];
  assign ines[15][7:0] = ines_in[7:0];
  
  wire [7:0] prgrom = ines[4];
  wire [7:0] chrrom = ines[5];
  
  wire [2:0] prg_size = prgrom <= 1  ? 0 :
                        prgrom <= 2  ? 1 : 
                        prgrom <= 4  ? 2 : 
                        prgrom <= 8  ? 3 : 
                        prgrom <= 16 ? 4 : 
                        prgrom <= 32 ? 5 : 
                        prgrom <= 64 ? 6 : 7;
                        
  wire [2:0] chr_size = chrrom <= 1  ? 0 : 
                        chrrom <= 2  ? 1 : 
                        chrrom <= 4  ? 2 : 
                        chrrom <= 8  ? 3 : 
                        chrrom <= 16 ? 4 : 
                        chrrom <= 32 ? 5 : 
                        chrrom <= 64 ? 6 : 7;
  
  wire [7:0] mapper = {ines[7][7:4], ines[6][7:4]};
  wire has_chr_ram = (chrrom == 0);
  assign mapper_flags = {16'b0, has_chr_ram, ines[6][0], chr_size, prg_size, mapper};
  always @(posedge clk) begin
	  done = 1;
  end
endmodule