data/full_repos/permissive/490649362/pipeline/sim/block_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/490649362/pipeline/sim/block_test.v:14: Unsupported: Ignoring delay on this delayed statement.\n        #0 in = 16\'b0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/490649362/pipeline/sim/block_test.v:15: Unsupported: Ignoring delay on this delayed statement.\n        #100 in = 16;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/490649362/pipeline/sim/block_test.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #100 in = -16;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/490649362/pipeline/sim/block_test.v:19: Unsupported: Ignoring delay on this delayed statement.\n    initial #300 $stop;\n            ^\n%Error: data/full_repos/permissive/490649362/pipeline/sim/block_test.v:11: Cannot find file containing module: \'Shift_Left_2\'\n    Shift_Left_2 # (input_size,output_size) sl_2 (in, out);\n    ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/490649362/pipeline/sim,data/full_repos/permissive/490649362/Shift_Left_2\n             data/full_repos/permissive/490649362/pipeline/sim,data/full_repos/permissive/490649362/Shift_Left_2.v\n             data/full_repos/permissive/490649362/pipeline/sim,data/full_repos/permissive/490649362/Shift_Left_2.sv\n             Shift_Left_2\n             Shift_Left_2.v\n             Shift_Left_2.sv\n             obj_dir/Shift_Left_2\n             obj_dir/Shift_Left_2.v\n             obj_dir/Shift_Left_2.sv\n%Warning-WIDTH: data/full_repos/permissive/490649362/pipeline/sim/block_test.v:14: Operator ASSIGN expects 26 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                                 : ... In instance block_test\n        #0 in = 16\'b0;\n              ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module block_test;

    parameter input_size = 26, output_size = 28;

    reg [input_size-1:0] in;
    wire [output_size-1:0] out;

    Shift_Left_2 # (input_size,output_size) sl_2 (in, out);

    initial begin
        #0 in = 16'b0;
        #100 in = 16;
        #100 in = -16;
    end

    initial #300 $stop;

endmodule
module block_test;


    parameter input_size = 26, output_size = 28;

    reg [input_size-1:0] in;
    wire [output_size-1:0] out;

    Shift_Left_2 # (input_size,output_size) sl_2 (in, out);

    initial begin
        #0 in = 16'b0;
        #100 in = 16;
        #100 in = -16;
    end

    initial #300 $stop;

endmodule