data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/ip_core/ddr_v1/src/ccb_ddr_cfg_top.v
1: b"%Error: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/ip_core/ddr_v1/src/ccb_ddr_cfg_top.v:468: Cannot find file containing module: 'DDR_CRG_CORE'\nDDR_CRG_CORE #(\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/ip_core/ddr_v1/src,data/full_repos/permissive/507203156/DDR_CRG_CORE\n             data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/ip_core/ddr_v1/src,data/full_repos/permissive/507203156/DDR_CRG_CORE.v\n             data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/ip_core/ddr_v1/src,data/full_repos/permissive/507203156/DDR_CRG_CORE.sv\n             DDR_CRG_CORE\n             DDR_CRG_CORE.v\n             DDR_CRG_CORE.sv\n             obj_dir/DDR_CRG_CORE\n             obj_dir/DDR_CRG_CORE.v\n             obj_dir/DDR_CRG_CORE.sv\n%Error: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/ip_core/ddr_v1/src/ccb_ddr_cfg_top.v:511: Cannot find file containing module: 'ctrl_wrapper'\nctrl_wrapper #(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/ip_core/ddr_v1/src/ccb_ddr_cfg_top.v:680: Cannot find file containing module: 'phy_wrapper'\nphy_wrapper #(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/ip_core/ddr_v1/src/ccb_ddr_cfg_top.v:896: Cannot find file containing module: 'array2ddr_mux'\narray2ddr_mux mux_inst(\n^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module cme_ddr_core_top_v1(
    I_mc_rstn, I_mc_pclk,
    I_cfg_rstn, I_cfg_pclk,

    I_mc_uclk, I_pbus_aclk0, I_pbus_aclk1,
    
    O_init_done, O_init_pass,
    

    axi_port00_arid, axi_port00_araddr, axi_port00_arlen, 
    axi_port00_arsize, axi_port00_arburst, axi_port00_arvalid, axi_port00_arready,
    axi_port00_rid, axi_port00_rdata, axi_port00_rresp,
    axi_port00_rlast, axi_port00_rvalid, axi_port00_rready,
    axi_port00_awid, axi_port00_awaddr, axi_port00_awlen,
    axi_port00_awsize, axi_port00_awburst, axi_port00_awvalid, axi_port00_awready,
    axi_port00_wid, axi_port00_wdata, axi_port00_wstrb,
    axi_port00_wlast, axi_port00_wvalid, axi_port00_wready,
    axi_port00_bid, axi_port00_bresp, axi_port00_bvalid, axi_port00_bready,
    

    axi_port01_arid, axi_port01_araddr, axi_port01_arlen, 
    axi_port01_arsize, axi_port01_arburst, axi_port01_arvalid, axi_port01_arready,
    axi_port01_rid, axi_port01_rdata, axi_port01_rresp,
    axi_port01_rlast, axi_port01_rvalid, axi_port01_rready,
    axi_port01_awid, axi_port01_awaddr, axi_port01_awlen,
    axi_port01_awsize, axi_port01_awburst, axi_port01_awvalid, axi_port01_awready,
    axi_port01_wid, axi_port01_wdata, axi_port01_wstrb,
    axi_port01_wlast, axi_port01_wvalid, axi_port01_wready,
    axi_port01_bid, axi_port01_bresp, axi_port01_bvalid, axi_port01_bready,
    

    sdii_port00_req, sdii_port00_gnt, sdii_port00_rw,
    sdii_port00_addr, sdii_port00_len, sdii_port00_partial_wrt,
    sdii_port00_wdata_pop, sdii_port00_wdata, sdii_port00_wmask,
    sdii_port00_rdata_psh, sdii_port00_rdata,
    

    sdii_port01_req, sdii_port01_gnt, sdii_port01_rw,
    sdii_port01_addr, sdii_port01_len, sdii_port01_partial_wrt,
    sdii_port01_wdata_pop, sdii_port01_wdata, sdii_port01_wmask,
    sdii_port01_rdata_psh, sdii_port01_rdata,
	
	O_error_status,O_error_status_en
);

parameter CFG_MC_BUS_SEL = 1'b1 ;
parameter CFG_IP2IP_SEL  = 1'B1 ;


parameter reg32_100 = 32'h42000000 ;
parameter reg32_104 = 32'h02080c51 ;
parameter reg32_108 = 32'h0186a000 ;
parameter reg32_10c = 32'h55e00a0a ;
parameter reg32_110 = 32'ha0000164 ;
parameter reg32_114 = 32'h00000a24 ;
parameter reg32_118 = 32'h04040404 ;
parameter reg32_11c = 32'h00000004 ;
parameter reg32_120 = 32'h2f2f2f2f ;
parameter reg32_124 = 32'h0000002f ;
parameter reg32_128 = 32'hbfbfbfbf ;
parameter reg32_12c = 32'h000000bf ;
parameter reg32_130 = 32'hbfbfbfbf ;
parameter reg32_134 = 32'h000000bf ;
parameter reg32_140 = 32'h86000000 ;
parameter reg32_144 = 32'h00008600 ;
parameter reg32_148 = 32'h80000000 ;
parameter reg32_14c = 32'h3f3f3f3f ;
parameter reg32_150 = 32'h0000003f ;
parameter reg32_180 = 32'h00000018 ;
parameter reg32_184 = 32'h1d700046 ;
parameter reg32_188 = 32'h00000000 ;
parameter reg32_18c = 32'h00000000 ;
parameter reg32_190 = 32'h00100008 ;
parameter reg32_1c0 = 32'h00000001 ;
parameter reg32_1e0 = 32'h01000602 ;
parameter reg32_1e4 = 32'h0c060044 ;
parameter reg32_1e8 = 32'hffff000c ;
parameter reg32_1ec = 32'hfffff105 ;
parameter reg32_1f0 = 32'h060a0406 ;
parameter reg32_1f4 = 32'h80060800 ;
parameter reg32_1f8 = 32'h0c400c30 ;
parameter reg32_1fc = 32'h00000000 ;


parameter reg32_00 = 32'h00000001 ;
parameter reg32_04 = 32'h00258000 ;
parameter reg32_08 = 32'h08080c30 ;
parameter reg32_0c = 32'hfffff124 ;
parameter reg32_10 = 32'h02030305 ;
parameter reg32_14 = 32'h03064010 ;
parameter reg32_18 = 32'h06060e06 ;
parameter reg32_1c = 32'h40040006 ;
parameter reg32_20 = 32'h01000044 ;
parameter reg32_24 = 32'h00030602 ;
parameter reg32_28 = 32'h00000018 ;
parameter reg32_2c = 32'h1d700046 ;
parameter reg32_30 = 32'h01000404 ;
parameter reg32_34 = 32'h020a0344 ;
parameter reg32_38 = 32'h00060c08 ;
parameter reg32_3c = 32'h00000800 ;
parameter reg32_50 = 32'h30000001 ;
parameter reg32_54 = 32'h00000000 ;
parameter reg32_58 = 32'h00000000 ;
parameter reg32_64 = 32'hf0000000 ;
parameter reg32_68 = 32'h00002000 ;


parameter DDR23AXISLV_PORT00_DATABUS = 128;
parameter DDR23AXISLV_PORT01_DATABUS = 128;
parameter DDR23AXISLV_PORT02_DATABUS = 128;
parameter DDR23AXISLV_PORT03_DATABUS = 128;
parameter DDR23AXISLV_PORT04_DATABUS = 128;

parameter DDR23AXISLV_PORT00_IDWIDTH = 16;
parameter DDR23AXISLV_PORT01_IDWIDTH = 16;
parameter DDR23AXISLV_PORT02_IDWIDTH = 16;
parameter DDR23AXISLV_PORT03_IDWIDTH = 16;
parameter DDR23AXISLV_PORT04_IDWIDTH = 16;

parameter DDR23AHBSLV_PORT00_DATABUS = 128;
parameter DDR23AHBSLV_PORT01_DATABUS = 128;
parameter DDR23AHBSLV_PORT02_DATABUS = 128;
parameter DDR23AHBSLV_PORT03_DATABUS = 128;
parameter DDR23AHBSLV_PORT04_DATABUS = 128;

parameter DDR23AXISLV_PORT00_BYTENUM = 16;
parameter DDR23AXISLV_PORT01_BYTENUM = 16;
parameter DDR23AXISLV_PORT02_BYTENUM = 16;
parameter DDR23AXISLV_PORT03_BYTENUM = 16;
parameter DDR23AXISLV_PORT04_BYTENUM = 16;

parameter DDR23AXISLV_PORT00_BITNUM = 4;
parameter DDR23AXISLV_PORT01_BITNUM = 4;
parameter DDR23AXISLV_PORT02_BITNUM = 4;
parameter DDR23AXISLV_PORT03_BITNUM = 4;
parameter DDR23AXISLV_PORT04_BITNUM = 4;


parameter DFI_DATA_WIDTH = 128;


input I_mc_rstn;
input I_mc_pclk;

input I_cfg_rstn;
input I_cfg_pclk;

input I_mc_uclk ;
input I_pbus_aclk0;
input I_pbus_aclk1;

output  O_init_done ;
output  O_init_pass ;


input  [DDR23AXISLV_PORT00_IDWIDTH-1:0] axi_port00_arid	;
input  [31:0] axi_port00_araddr ;
input  [3:0]  axi_port00_arlen  ;
input  [2:0]  axi_port00_arsize ;
input  [1:0]  axi_port00_arburst;
input  axi_port00_arvalid ;
output axi_port00_arready ;
output [DDR23AXISLV_PORT00_IDWIDTH-1:0] axi_port00_rid  ;
output [DDR23AXISLV_PORT00_DATABUS-1:0] axi_port00_rdata;
output [1:0] axi_port00_rresp ;
output axi_port00_rlast  ;
output axi_port00_rvalid ;
input  axi_port00_rready ;
input  [DDR23AXISLV_PORT00_IDWIDTH-1:0] axi_port00_awid ;
input  [31:0] axi_port00_awaddr ;
input  [3:0]  axi_port00_awlen  ;
input  [2:0]  axi_port00_awsize ;
input  [1:0]  axi_port00_awburst;
input  axi_port00_awvalid ;
output axi_port00_awready ;
input  [DDR23AXISLV_PORT00_IDWIDTH-1:0] axi_port00_wid ;
input  [DDR23AXISLV_PORT00_DATABUS-1:0] axi_port00_wdata ;
input  [(DDR23AXISLV_PORT00_DATABUS/8)-1:0] axi_port00_wstrb ;
input  axi_port00_wlast ;
input  axi_port00_wvalid ;
output axi_port00_wready ;
output [DDR23AXISLV_PORT00_IDWIDTH-1:0] axi_port00_bid ;
output [1:0] axi_port00_bresp ;
output axi_port00_bvalid ;
input  axi_port00_bready ;


input  [DDR23AXISLV_PORT02_IDWIDTH-1:0] axi_port01_arid ;
input  [31:0] axi_port01_araddr ;
input  [3:0]  axi_port01_arlen ;
input  [2:0]  axi_port01_arsize ;
input  [1:0]  axi_port01_arburst;
input  axi_port01_arvalid ;
output axi_port01_arready ;
output [DDR23AXISLV_PORT02_IDWIDTH-1:0] axi_port01_rid ;
output [DDR23AXISLV_PORT02_DATABUS-1:0] axi_port01_rdata ;
output [1:0] axi_port01_rresp ;
output axi_port01_rlast ;
output axi_port01_rvalid ;
input  axi_port01_rready ;
input  [DDR23AXISLV_PORT02_IDWIDTH-1:0] axi_port01_awid			;
input  [31:0] axi_port01_awaddr ;
input  [3:0]  axi_port01_awlen ;
input  [2:0]  axi_port01_awsize ;
input  [1:0]  axi_port01_awburst;
input  axi_port01_awvalid ;
output axi_port01_awready ;
input  [DDR23AXISLV_PORT02_IDWIDTH-1:0] axi_port01_wid ;
input  [DDR23AXISLV_PORT02_DATABUS-1:0] axi_port01_wdata ;
input  [(DDR23AXISLV_PORT02_DATABUS/8)-1:0] axi_port01_wstrb ;
input  axi_port01_wlast ;
input  axi_port01_wvalid ;
output axi_port01_wready ;
output [DDR23AXISLV_PORT02_IDWIDTH-1:0] axi_port01_bid ;
output [1:0] axi_port01_bresp ;
output axi_port01_bvalid ;
input  axi_port01_bready ;


input  sdii_port00_req ;
output sdii_port00_gnt ;
input  sdii_port00_rw  ;
input  [31:0] sdii_port00_addr ;
input  [5:0]  sdii_port00_len  ;
input  sdii_port00_partial_wrt ;
output sdii_port00_wdata_pop ;
input  [(DFI_DATA_WIDTH-1):0]     sdii_port00_wdata ;
input  [((DFI_DATA_WIDTH/8)-1):0] sdii_port00_wmask ;
output sdii_port00_rdata_psh ;
output [(DFI_DATA_WIDTH-1):0] sdii_port00_rdata ;


input  sdii_port01_req ;
output sdii_port01_gnt ;
input  sdii_port01_rw  ;
input  [31:0] sdii_port01_addr ;
input  [5:0]  sdii_port01_len  ;
input  sdii_port01_partial_wrt ;
output sdii_port01_wdata_pop ;
input  [(DFI_DATA_WIDTH-1):0]     sdii_port01_wdata ;
input  [((DFI_DATA_WIDTH/8)-1):0] sdii_port01_wmask ;
output sdii_port01_rdata_psh ;
output [(DFI_DATA_WIDTH-1):0] sdii_port01_rdata ;

output [2:0]O_error_status;
output O_error_status_en ;









`ifdef SIM_MASTER_CFG_DDR_CORE_EN
	`define SIM_MASTER_CFG_EN  1
`elsif  SIM_MASTER_CFG_DDR_PHY_EN
	`define SIM_MASTER_CFG_EN  1
`else
`endif










wire mc_clk_src;
wire usr_clk;
wire ip_bus_clk;
wire usrbus_clk;
wire cfg_uclk;
wire cfg_pclk;
wire pll_lck;
wire ctl_ahb_cfg_hclk ;












assign mc_clk_src = I_mc_pclk ;
assign usr_clk    = mc_clk_src ;
assign ip_bus_clk = I_pbus_aclk0 ;
assign usrbus_clk = ip_bus_clk ;
assign cfg_pclk = I_cfg_pclk;
assign cfg_uclk = cfg_pclk;
assign ctl_ahb_cfg_hclk = cfg_pclk ;



wire w_x0connection;
wire w_x1connection;
wire mc_clk ;
wire mc_rstn ;

wire         mcfg_rstn;
wire [15:0]  cbi_pbus_addr;
wire         cbi_pbus_req;
wire [31:0]  cbi_pbus_wdata;
wire         cbi_pbus_write;
wire [31:0]  ctl_ahb_cfg_haddr_i;
wire [2:0]   ctl_ahb_cfg_hburst_i;
wire         ctl_ahb_cfg_hready_i;
wire         ctl_ahb_cfg_hsel_i;
wire [2:0]   ctl_ahb_cfg_hsize_i;
wire [1:0]  ctl_ahb_cfg_htrans_i;
wire [31:0] ctl_ahb_cfg_hwdata_i;
wire            ctl_ahb_cfg_hwrite_i;
wire [31:0] hreg_haddr;
wire [1:0]  hreg_htrans;
wire [31:0] hreg_hwdata;
wire            hreg_hwrite;



wire [15:0] pcsps_pbus_addr;
wire           pcsps_pbus_req;
wire [31:0] pcsps_pbus_wdata;
wire           pcsps_pbus_write;
wire [31:0] phy_ahb_haddr_i;
wire [2:0]  phy_ahb_hburst_i;
wire 	   phy_ahb_hready_i;
wire 	   phy_ahb_hsel_i;
wire [2:0]  phy_ahb_hsize_i;
wire [1:0]  phy_ahb_htrans_i;
wire [31:0] phy_ahb_hwdata_i;
wire 	   phy_ahb_hwrite_i;
wire 	   cbi_pbus_gnt;
wire [31:0] cbi_pbus_rdata;


wire [31:0]	ctl_ahb_cfg_hrdata_o;
wire 	ctl_ahb_cfg_hready_o;
wire [0:0]	ctl_ahb_cfg_hresp_o;

wire      fp_cs_rstn;
wire [31:0]	hreg_hrdata;
wire     hreg_hready_out;

wire      psps_pbus_gnt;
wire [31:0] pcsps_pbus_rdata;
wire [31:0] phy_ahb_hrdata_o;
wire     hy_ahb_hready_o;
wire [0:0]	 phy_ahb_hresp_o;

wire usr_pbus_rstn;

wire [19:0]  dram_dfi_addr_p1;
wire [19:0]  dram_dfi_addr_p0;
wire [2:0]   dram_dfi_bank_p1;
wire [2:0]   dram_dfi_bank_p0;
wire         dram_dfi_cas_n_p1;
wire         dram_dfi_cas_n_p0;
wire [0:0]   dram_dfi_cke_p1;
wire [0:0]   dram_dfi_cke_p0;
wire [0:0]   dram_dfi_cs_n_duplicate_p1;
wire [0:0]   dram_dfi_cs_n_duplicate_p0;
wire [0:0]   dram_dfi_cs_n_p1;
wire [0:0]   dram_dfi_cs_n_p0;
wire         dram_dfi_ctrlupd_req;
wire         dram_dfi_dram_clk_disable;
wire [0:0]	  dram_dfi_ecc_rddata_en_p1;
wire [0:0]	  dram_dfi_ecc_rddata_en_p0;
wire [0:0]	  dram_dfi_ecc_wrdata_en_p1;
wire [0:0]	  dram_dfi_ecc_wrdata_en_p0;
wire [15:0]  dram_dfi_ecc_wrdata_p1;
wire [15:0]  dram_dfi_ecc_wrdata_p0;
wire [1:0]   dram_dfi_ecc_wrmask_p1;
wire [1:0]   dram_dfi_ecc_wrmask_p0;
wire         dram_dfi_init_start;
wire         dram_dfi_ras_n_p1;
wire         dram_dfi_ras_n_p0;
wire [3:0]   dram_dfi_rddata_en_p1;
wire [3:0]   dram_dfi_rddata_en_p0;
wire [31:0]  dram_dfi_rdlvl_delay;
wire [31:0]  dram_dfi_rdlvl_delayn;
wire [0:0]	  dram_dfi_rdlvl_edge;
wire [0:0]	  dram_dfi_rdlvl_en;
wire [63:0]	dram_dfi_rdlvl_gate_delay;
wire [0:0]   dram_dfi_rdlvl_gate_en;
wire [0:0]   dram_dfi_rdlvl_load;
wire   dram_dfi_reset_n_p1;
wire   dram_dfi_reset_n_p0;
wire   ram_dfi_we_n_p1;
wire   dram_dfi_we_n_p0;
wire [0:0]	dram_dfi_wodt_p1;
wire [0:0]	dram_dfi_wodt_p0;
wire [3:0]	dram_dfi_wrdata_en_p1;
wire [3:0]	dram_dfi_wrdata_en_p0;
wire [63:0]	dram_dfi_wrdata_p1;
wire [63:0]	dram_dfi_wrdata_p0;
wire [31:0]	dram_dfi_wrlvl_delay;
wire [0:0]	  dram_dfi_wrlvl_en;
wire [0:0]	  dram_dfi_wrlvl_load;
wire [0:0]	  dram_dfi_wrlvl_strobe;
wire [7:0]	  dram_dfi_wrmask_p1;
wire [7:0]	  dram_dfi_wrmask_p0;
wire 	gating_mc_clk;
wire  intr;
wire [2047:0]	r_ddr23phy_reg;
wire [31:0]	r_system_pll_reg;
wire [31:0] ahb_cfg_haddr_i;
wire [2:0]	 ahb_cfg_hburst_i;
wire 	     ahb_cfg_hready_i;
wire 	     ahb_cfg_hsel_i;
wire [2:0]	 ahb_cfg_hsize_i;
wire [1:0]	 ahb_cfg_htrans_i;
wire [31:0] ahb_cfg_hwdata_i;
wire 	     ahb_cfg_hwrite_i;
wire 	axi_port02_aclk;
wire 	axi_port02_arstn;
wire 	axi_port00_aclk;
wire 	axi_port00_arstn;

wire     dram_dfi_ctrlupd_ack;
wire [15:0]	dram_dfi_ecc_rddata_w1;
wire [15:0]	dram_dfi_ecc_rddata_w0;
wire   dram_dfi_init_complete;
wire [3:0]	  dram_dfi_rddata_valid_w1;
wire [3:0]	  dram_dfi_rddata_valid_w0;
wire [63:0]	dram_dfi_rddata_w1;
wire [63:0]	dram_dfi_rddata_w0;
wire [1:0]	  dram_dfi_rdlvl_gate_mode;
wire [1:0]	  dram_dfi_rdlvl_mode;
wire [31:0]	dram_dfi_rdlvl_resp;
wire [1:0]	  dram_dfi_wrlvl_mode;
wire [3:0]	  dram_dfi_wrlvl_resp;
wire    [2047:0]	ro_ddr23phy_reg;

wire       inner_pbus_req ;
wire 	   NC_s0;








wire S_intr ;
wire         pbus_req;
wire         pbus_gnt;
wire         pbus_write;
wire [15:0] pbus_addr;
wire [31:0] pbus_wdata;
wire [31:0] pbus_rdata;

wire [279:0] S_port0_data_to_ip ;
wire [279:0] S_port1_data_to_ip ;
wire [169:0] S_port0_data_to_usr ;
wire [169:0] S_port1_data_to_usr ;




DDR_CRG_CORE #(
		.cfg_gx_soft_prst      ( 0                   ),
		.cfg_mc_bus_sel        ( CFG_MC_BUS_SEL	     )
) u_ddrc_crg(   

		.axi_port00_aclk_ug    ( I_pbus_aclk0          ),
		.axi_port00_aclk_us    ( w_x0connection      ),
		.axi_port02_aclk_ug    ( I_pbus_aclk1          ),
		.axi_port02_aclk_us    ( w_x1connection      ),
		.bypasspll_mc_clk_x4_ug( I_mc_pclk           ),
		.fp_cs_clk             ( cfg_pclk            ),
		.gating_mc_clk         ( gating_mc_clk       ),
		.mc_clk_ug             ( I_mc_pclk           ),
		
		.p_rc                  (  1'B1),
`ifdef SIMULATION_DDRC_EN
		.pbus_rst_n            ( 1),
`endif
		.pclk_ddr              ( cfg_pclk            ),
		.r_system_pll_reg      ( r_system_pll_reg    ),
	

		.axi_port00_aclk     ( axi_port00_aclk     ),
		.axi_port00_arstn    ( axi_port00_arstn    ),
		.axi_port02_aclk     ( axi_port02_aclk     ),
		.axi_port02_arstn    ( axi_port02_arstn    ),
		.bypasspll_mc_clk_x4 ( bypasspll_mc_clk_x4 ),
		.fp_cs_rstn          ( fp_cs_rstn          ),
		.mc_clk              ( mc_clk              ),
		.mc_clk_us           ( ),
		.mc_rstn             ( mc_rstn             ),
		.mcfg_rstn           ( mcfg_rstn           ),
		.prstn_gx            ( prstn_gx            ),
		.rst_p_n             ( rst_p_n             ),
		.usr_pbus_rstn       ( usr_pbus_rstn       ),
		.x0_async_clk        ( w_x0connection      ),
		.x1_async_clk        ( w_x1connection      )


);



ctrl_wrapper #(
	.bus_ctl_sel     ( CFG_MC_BUS_SEL )
	,.ddr_ctl_iso_en ( 1'b1      )
	,.ddr_ctl_pd     ( 1'b0      )
	,.reg32_50       ( reg32_50  )
	,.reg32_100      ( reg32_100 )
	,.reg32_104      ( reg32_104 )
	,.reg32_108      ( reg32_108 )
	,.reg32_10c      ( reg32_10c )
	,.reg32_110      ( reg32_110 )
	,.reg32_140      ( reg32_140 )
	,.reg32_144      ( reg32_144 )
	,.reg32_148      ( reg32_148 )
	,.reg32_14c      ( reg32_14c )
	,.reg32_150      ( reg32_150 )
	,.reg32_190      ( reg32_190 )
	,.reg32_1c0      ( reg32_1c0 )
	,.reg32_180      ( reg32_180 )
	,.reg32_184      ( reg32_184 )
	,.reg32_188      ( reg32_188 )
	,.reg32_18c      ( reg32_18c )
	,.reg32_1e0      ( reg32_1e0 )
	,.reg32_1e4      ( reg32_1e4 )
	,.reg32_1e8      ( reg32_1e8 )
	,.reg32_1ec      ( reg32_1ec )
	,.reg32_1f0      ( reg32_1f0 )
	,.reg32_1f4      ( reg32_1f4 )
	,.reg32_1f8      ( reg32_1f8 )
	,.reg32_1fc      ( reg32_1fc )
	,.reg32_04       ( reg32_04  )
	,.reg32_08       ( reg32_08  )
	,.reg32_0c       ( reg32_0c  )
	,.reg32_10       ( reg32_10  )
	,.reg32_14       ( reg32_14  )
	,.reg32_18       ( reg32_18  )
	,.reg32_1c       ( reg32_1c  )
	,.reg32_20       ( reg32_20  )
	,.reg32_24       ( reg32_24  )
	,.reg32_28       ( reg32_28  )
	,.reg32_2c       ( reg32_2c  )
	,.reg32_30       ( reg32_30  )
	,.reg32_34       ( reg32_34  )
	,.reg32_38       ( reg32_38  )
	,.reg32_3c       ( reg32_3c  )
	,.reg32_54       ( reg32_54  )
	,.reg32_58       ( reg32_58  )
	,.reg32_64       ( reg32_64  )
	,.reg32_68       ( reg32_68  )
	,.reg32_00       ( reg32_00  )
	,.reg32_118      ( reg32_118 )
	,.reg32_11c      ( reg32_11c )
	,.reg32_120      ( reg32_120 )
	,.reg32_124      ( reg32_124 )
	,.reg32_128      ( reg32_128 )
	,.reg32_12c      ( reg32_12c )
	,.reg32_130      ( reg32_130 )
	,.reg32_134      ( reg32_134 )
	,.reg32_114      ( reg32_114 )




) u_ddrc(

	.ro_ddr23phy_reg         ( ro_ddr23phy_reg          )
`ifdef SIM_MASTER_CFG_DDR_CORE_EN
	,.ahb_cfg_haddr_i				 ( ctl_ahb_cfg_haddr_i			)
	,.ahb_cfg_hburst_i			     ( ctl_ahb_cfg_hburst_i			)
	,.ahb_cfg_hclk				     ( ctl_ahb_cfg_hclk			  	)
	,.ahb_cfg_hready_i			     ( ctl_ahb_cfg_hready_i			)
	,.ahb_cfg_hresetn				 ( mcfg_rstn				    )
	,.ahb_cfg_hsel_i				 ( ctl_ahb_cfg_hsel_i		  	)
	,.ahb_cfg_hsize_i				 ( ctl_ahb_cfg_hsize_i			)
	,.ahb_cfg_htrans_i			     ( ctl_ahb_cfg_htrans_i			)
	,.ahb_cfg_hwdata_i			     ( ctl_ahb_cfg_hwdata_i			)
	,.ahb_cfg_hwrite_i			     ( ctl_ahb_cfg_hwrite_i			)
`endif
	,.axi_port00_aclk				( axi_port00_aclk				) 
	,.axi_port00_arstn			    ( axi_port00_arstn				)
	,.axi_port02_aclk				( axi_port02_aclk				) 
	,.axi_port02_arstn				( axi_port02_arstn				)
`ifdef SIM_DFI_BUS
	,.dram_dfi_ctrlupd_ack			( dram_dfi_ctrlupd_ack			)
	,.dram_dfi_ecc_rddata_w0		( dram_dfi_ecc_rddata_w0		)
	,.dram_dfi_ecc_rddata_w1		( dram_dfi_ecc_rddata_w1		)
	,.dram_dfi_init_complete		( dram_dfi_init_complete		)		
	,.dram_dfi_rddata_valid_w0      ( dram_dfi_rddata_valid_w0		) 	
	,.dram_dfi_rddata_valid_w1	    ( dram_dfi_rddata_valid_w1		)
	,.dram_dfi_rddata_w0			( dram_dfi_rddata_w0			)
	,.dram_dfi_rddata_w1			( dram_dfi_rddata_w1			)
	,.dram_dfi_rdlvl_gate_mode		( dram_dfi_rdlvl_gate_mode		) 		
	,.dram_dfi_rdlvl_mode			( dram_dfi_rdlvl_mode			) 	
	,.dram_dfi_rdlvl_resp			( dram_dfi_rdlvl_resp			) 	
	,.dram_dfi_wrlvl_mode			( dram_dfi_wrlvl_mode			)
	,.dram_dfi_wrlvl_resp			( dram_dfi_wrlvl_resp			) 
`endif
	,.i_p0                    ( S_port0_data_to_ip)
	,.i_p1                    ( S_port1_data_to_ip)
	,.mc_clk				          ( mc_clk				        ) 
	,.mc_rstn				          ( mc_rstn				        )
	

	,.r_ddr23phy_reg				( r_ddr23phy_reg				)
`ifdef SIM_MASTER_CFG_DDR_CORE_EN
	,.ahb_cfg_hrdata_o				( ctl_ahb_cfg_hrdata_o			) 
	,.ahb_cfg_hready_o				( ctl_ahb_cfg_hready_o			) 
	,.ahb_cfg_hresp_o				( ctl_ahb_cfg_hresp_o			)
`endif

`ifdef SIM_DFI_BUS
	,.dram_dfi_addr_p0				( dram_dfi_addr_p0				)
	,.dram_dfi_addr_p1				( dram_dfi_addr_p1				) 
	,.dram_dfi_bank_p0				( dram_dfi_bank_p0				) 
	,.dram_dfi_bank_p1				( dram_dfi_bank_p1				)
	,.dram_dfi_cas_n_p0				( dram_dfi_cas_n_p0				)	 
	,.dram_dfi_cas_n_p1				( dram_dfi_cas_n_p1				)
	,.dram_dfi_cke_p0				( dram_dfi_cke_p0				)
	,.dram_dfi_cke_p1				( dram_dfi_cke_p1				)
	,.dram_dfi_cs_n_duplicate_p0	( dram_dfi_cs_n_duplicate_p0	)
	,.dram_dfi_cs_n_duplicate_p1	( dram_dfi_cs_n_duplicate_p1	)
	,.dram_dfi_cs_n_p0				( dram_dfi_cs_n_p0				)
	,.dram_dfi_cs_n_p1				( dram_dfi_cs_n_p1				)
	,.dram_dfi_ctrlupd_req			( dram_dfi_ctrlupd_req			)
	,.dram_dfi_dram_clk_disable		( dram_dfi_dram_clk_disable		)
	,.dram_dfi_ecc_rddata_en_p0		( dram_dfi_ecc_rddata_en_p0		)
	,.dram_dfi_ecc_rddata_en_p1		( dram_dfi_ecc_rddata_en_p1		)
	,.dram_dfi_ecc_wrdata_en_p0		( dram_dfi_ecc_wrdata_en_p0		)
	,.dram_dfi_ecc_wrdata_en_p1		( dram_dfi_ecc_wrdata_en_p1		)
	,.dram_dfi_ecc_wrdata_p0		( dram_dfi_ecc_wrdata_p0		)
	,.dram_dfi_ecc_wrdata_p1		( dram_dfi_ecc_wrdata_p1		)
	,.dram_dfi_ecc_wrmask_p0		( dram_dfi_ecc_wrmask_p0		)
	,.dram_dfi_ecc_wrmask_p1		( dram_dfi_ecc_wrmask_p1		)
	,.dram_dfi_init_start			( dram_dfi_init_start			)
	,.dram_dfi_ras_n_p0				( dram_dfi_ras_n_p0				)
	,.dram_dfi_ras_n_p1				( dram_dfi_ras_n_p1				)
	,.dram_dfi_rddata_en_p0			( dram_dfi_rddata_en_p0			) 
	,.dram_dfi_rddata_en_p1			( dram_dfi_rddata_en_p1			)
	,.dram_dfi_rdlvl_delay			( dram_dfi_rdlvl_delay			)
	,.dram_dfi_rdlvl_delayn			( dram_dfi_rdlvl_delayn			)
	,.dram_dfi_rdlvl_edge			( dram_dfi_rdlvl_edge			)
	,.dram_dfi_rdlvl_en				( dram_dfi_rdlvl_en				)
	,.dram_dfi_rdlvl_gate_delay		( dram_dfi_rdlvl_gate_delay		) 		
	,.dram_dfi_rdlvl_gate_en		( dram_dfi_rdlvl_gate_en		)
	,.dram_dfi_rdlvl_load			( dram_dfi_rdlvl_load			)
 	,.dram_dfi_reset_n_p0			( dram_dfi_reset_n_p0			)
	,.dram_dfi_reset_n_p1			( dram_dfi_reset_n_p1			) 	
	,.dram_dfi_we_n_p0				( dram_dfi_we_n_p0				)	
	,.dram_dfi_we_n_p1				( dram_dfi_we_n_p1				)
	,.dram_dfi_wodt_p0				( dram_dfi_wodt_p0				) 
	,.dram_dfi_wodt_p1				( dram_dfi_wodt_p1				)
	,.dram_dfi_wrdata_en_p0		( dram_dfi_wrdata_en_p0			)
	,.dram_dfi_wrdata_en_p1		( dram_dfi_wrdata_en_p1			) 	
	,.dram_dfi_wrdata_p0			( dram_dfi_wrdata_p0			) 	
	,.dram_dfi_wrdata_p1			( dram_dfi_wrdata_p1			)
	,.dram_dfi_wrlvl_delay		( dram_dfi_wrlvl_delay			)
	,.dram_dfi_wrlvl_en				( dram_dfi_wrlvl_en				) 
	,.dram_dfi_wrlvl_load			( dram_dfi_wrlvl_load			)
	,.dram_dfi_wrlvl_strobe			( dram_dfi_wrlvl_strobe			)
	,.dram_dfi_wrmask_p0			( dram_dfi_wrmask_p0			)	
	,.dram_dfi_wrmask_p1			( dram_dfi_wrmask_p1			)
`endif
	,.gating_mc_clk				    ( gating_mc_clk				    )
	,.intr                          ( intr                          )

	,.o_p0   						( S_port0_data_to_usr)
	,.o_p1   						( S_port1_data_to_usr)
	,.r_system_pll_reg				( r_system_pll_reg				) 
);

phy_wrapper #(
     .phy_test_iddq  ( 1'b0 )
    ,.dfi_sphy_sel   ( 1'b0 )
    ,.ddr_phy_iso_en ( 1'b1 )
    ,.ddr_phy_pd     ( 1'b1 )

) u_ddr23phy (
`ifndef SIM_INTER_WIRE

	.r_ddr23phy_reg				( r_ddr23phy_reg			)
	
`ifdef SIM_MASTER_CFG_DDR_PHY_EN
	,.ahb_haddr_i			    ( phy_ahb_haddr_i			)
	,.ahb_hburst_i				( phy_ahb_hburst_i			)
	,.ahb_hclk				    ( phy_ahb_hclk				)
	,.ahb_hready_i				( phy_ahb_hready_i			)
	,.ahb_hresetn				( phy_ahb_hresetn			)
	,.ahb_hsel_i				( phy_ahb_hsel_i			)
	,.ahb_hsize_i				( phy_ahb_hsize_i			)
	,.ahb_htrans_i				( phy_ahb_htrans_i			)
	,.ahb_hwdata_i				( phy_ahb_hwdata_i			)
	,.ahb_hwrite_i				( phy_ahb_hwrite_i			)
`endif

	,.bypasspll_mc_clk_x4		( bypasspll_mc_clk_x4		)
`ifdef SIM_DFI_BUS
	,.dram_dfi_addr_p0			( dram_dfi_addr_p0			)
	,.dram_dfi_addr_p1			( dram_dfi_addr_p1			)
	,.dram_dfi_bank_p0			( dram_dfi_bank_p0			)
	,.dram_dfi_bank_p1			( dram_dfi_bank_p1			)
	,.dram_dfi_cas_n_p0			( dram_dfi_cas_n_p0			)
	,.dram_dfi_cas_n_p1			( dram_dfi_cas_n_p1			)
	,.dram_dfi_cke_p0			  ( dram_dfi_cke_p0		  	)
	,.dram_dfi_cke_p1			  ( dram_dfi_cke_p1			  )
	,.dram_dfi_cs_n_duplicate_p0( dram_dfi_cs_n_duplicate_p0 )
	,.dram_dfi_cs_n_duplicate_p1( dram_dfi_cs_n_duplicate_p1 )
	,.dram_dfi_cs_n_p0			( dram_dfi_cs_n_p0			)
	,.dram_dfi_cs_n_p1			( dram_dfi_cs_n_p1			)
	,.dram_dfi_ctrlupd_req		( dram_dfi_ctrlupd_req		)
	,.dram_dfi_dram_clk_disable	( dram_dfi_dram_clk_disable	)
	,.dram_dfi_ecc_rddata_en_p0	( dram_dfi_ecc_rddata_en_p0	)
	,.dram_dfi_ecc_rddata_en_p1	( dram_dfi_ecc_rddata_en_p1	)
	,.dram_dfi_ecc_wrdata_en_p0	( dram_dfi_ecc_wrdata_en_p0	)
	,.dram_dfi_ecc_wrdata_en_p1	( dram_dfi_ecc_wrdata_en_p1	)
	,.dram_dfi_ecc_wrdata_p0	( dram_dfi_ecc_wrdata_p0	)
	,.dram_dfi_ecc_wrdata_p1	( dram_dfi_ecc_wrdata_p1	)
	,.dram_dfi_ecc_wrmask_p0	( dram_dfi_ecc_wrmask_p0	)
	,.dram_dfi_ecc_wrmask_p1	( dram_dfi_ecc_wrmask_p1	)
	,.dram_dfi_init_start		( dram_dfi_init_start		)
	,.dram_dfi_ras_n_p0			( dram_dfi_ras_n_p0			)
	,.dram_dfi_ras_n_p1			( dram_dfi_ras_n_p1			)
	,.dram_dfi_rddata_en_p0		( dram_dfi_rddata_en_p0		)
	,.dram_dfi_rddata_en_p1		( dram_dfi_rddata_en_p1		)
	,.dram_dfi_rdlvl_delay		( dram_dfi_rdlvl_delay		)
	,.dram_dfi_rdlvl_delayn		( dram_dfi_rdlvl_delayn		)
	,.dram_dfi_rdlvl_edge		( dram_dfi_rdlvl_edge		)
	,.dram_dfi_rdlvl_en			( dram_dfi_rdlvl_en			)
	,.dram_dfi_rdlvl_gate_delay	( dram_dfi_rdlvl_gate_delay	)
	,.dram_dfi_rdlvl_gate_en	( dram_dfi_rdlvl_gate_en	)
	,.dram_dfi_rdlvl_load		( dram_dfi_rdlvl_load		)
	,.dram_dfi_reset_n_p0		( dram_dfi_reset_n_p0		)
	,.dram_dfi_reset_n_p1		( dram_dfi_reset_n_p1		)
	,.dram_dfi_we_n_p0			( dram_dfi_we_n_p0			)
	,.dram_dfi_we_n_p1			( dram_dfi_we_n_p1			)
	,.dram_dfi_wodt_p0			( dram_dfi_wodt_p0			)
	,.dram_dfi_wodt_p1			( dram_dfi_wodt_p1			)
	,.dram_dfi_wrdata_en_p0		( dram_dfi_wrdata_en_p0		)
	,.dram_dfi_wrdata_en_p1		( dram_dfi_wrdata_en_p1		)
	,.dram_dfi_wrdata_p0		( dram_dfi_wrdata_p0		)
	,.dram_dfi_wrdata_p1		( dram_dfi_wrdata_p1		)
	,.dram_dfi_wrlvl_delay		( dram_dfi_wrlvl_delay		)
	,.dram_dfi_wrlvl_en			( dram_dfi_wrlvl_en			)
	,.dram_dfi_wrlvl_load		( dram_dfi_wrlvl_load		)
	,.dram_dfi_wrlvl_strobe		( dram_dfi_wrlvl_strobe		)
	,.dram_dfi_wrmask_p0		( dram_dfi_wrmask_p0		)
	,.dram_dfi_wrmask_p1		( dram_dfi_wrmask_p1		)
`endif
	,.mc_clk				      ( mc_clk				        )
	,.mc_clk_rst_n				( mc_rstn				      	)
	

	,.ro_ddr23phy_reg			( ro_ddr23phy_reg			  )
`ifdef SIM_MASTER_CFG_DDR_PHY_EN
	,.ahb_hrdata_o				( phy_ahb_hrdata_o			)
	,.ahb_hready_o				( phy_ahb_hready_o			)
	,.ahb_hresp_o			  	( phy_ahb_hresp_o			  )
`endif

`ifdef SIM_DFI_BUS
	,.dram_dfi_ctrlupd_ack		  ( dram_dfi_ctrlupd_ack		  )
	,.dram_dfi_ecc_rddata_w0	  ( dram_dfi_ecc_rddata_w0	  )
	,.dram_dfi_ecc_rddata_w1	  ( dram_dfi_ecc_rddata_w1	  )	
	,.dram_dfi_init_complete	  ( dram_dfi_init_complete	  )
	,.dram_dfi_rddata_valid_w0	( dram_dfi_rddata_valid_w0	)
	,.dram_dfi_rddata_valid_w1	( dram_dfi_rddata_valid_w1	)
	,.dram_dfi_rddata_w0		    ( dram_dfi_rddata_w0		    )
	,.dram_dfi_rddata_w1	    	( dram_dfi_rddata_w1	    	)
	,.dram_dfi_rdlvl_gate_mode	( dram_dfi_rdlvl_gate_mode	)
	,.dram_dfi_rdlvl_mode		    ( dram_dfi_rdlvl_mode		    )
	,.dram_dfi_rdlvl_resp		    ( dram_dfi_rdlvl_resp		    )
	,.dram_dfi_wrlvl_mode		    ( dram_dfi_wrlvl_mode	    	)
	,.dram_dfi_wrlvl_resp		    ( dram_dfi_wrlvl_resp	    	)
`endif

`endif
);

assign O_init_done = 1'b1;
assign O_init_pass = 1'b1;




array2ddr_mux mux_inst(
		.axi_port00_awid      ( axi_port00_awid    )
		,.axi_port00_awaddr   ( axi_port00_awaddr  )
		,.axi_port00_awlen    ( axi_port00_awlen   )  
		,.axi_port00_awsize   ( axi_port00_awsize  ) 
		,.axi_port00_awburst  ( axi_port00_awburst )
		,.axi_port00_awvalid  ( axi_port00_awvalid )
		,.axi_port00_awready  ( axi_port00_awready )
		,.axi_port00_wid      ( axi_port00_wid     )    
		,.axi_port00_wdata    ( axi_port00_wdata   )  
		,.axi_port00_wstrb    ( axi_port00_wstrb   )  
		,.axi_port00_wlast    ( axi_port00_wlast   )  
		,.axi_port00_wvalid   ( axi_port00_wvalid  ) 
		,.axi_port00_wready   ( axi_port00_wready  ) 
		,.axi_port00_bid      ( axi_port00_bid     )    
		,.axi_port00_bresp    ( axi_port00_bresp   )  
		,.axi_port00_bvalid   ( axi_port00_bvalid  ) 
		,.axi_port00_bready   ( axi_port00_bready  ) 
		,.axi_port00_arid     ( axi_port00_arid    )   
		,.axi_port00_araddr   ( axi_port00_araddr  ) 
		,.axi_port00_arlen    ( axi_port00_arlen   )  
		,.axi_port00_arsize   ( axi_port00_arsize  ) 
		,.axi_port00_arburst  ( axi_port00_arburst )
		,.axi_port00_arvalid  ( axi_port00_arvalid )
		,.axi_port00_arready  ( axi_port00_arready )
		,.axi_port00_rid      ( axi_port00_rid     )
		,.axi_port00_rdata    ( axi_port00_rdata   )
		,.axi_port00_rresp    ( axi_port00_rresp   )
		,.axi_port00_rlast    ( axi_port00_rlast   )
		,.axi_port00_rvalid   ( axi_port00_rvalid  )
		,.axi_port00_rready   ( axi_port00_rready  )
		,.axi_port02_awid     ( axi_port01_awid    ) 
		,.axi_port02_awaddr   ( axi_port01_awaddr  )
		,.axi_port02_awlen    ( axi_port01_awlen   )
		,.axi_port02_awsize   ( axi_port01_awsize  )
		,.axi_port02_awburst  ( axi_port01_awburst )
		,.axi_port02_awvalid  ( axi_port01_awvalid )
		,.axi_port02_awready  ( axi_port01_awready )
		,.axi_port02_wid      ( axi_port01_wid     )
		,.axi_port02_wdata    ( axi_port01_wdata   )
		,.axi_port02_wstrb    ( axi_port01_wstrb   )
		,.axi_port02_wlast    ( axi_port01_wlast   )
		,.axi_port02_wvalid   ( axi_port01_wvalid  )
		,.axi_port02_wready   ( axi_port01_wready  )
		,.axi_port02_bid      ( axi_port01_bid     )
		,.axi_port02_bresp    ( axi_port01_bresp   )
		,.axi_port02_bvalid   ( axi_port01_bvalid  )
		,.axi_port02_bready   ( axi_port01_bready  )
		,.axi_port02_arid     ( axi_port01_arid    )
		,.axi_port02_araddr   ( axi_port01_araddr  )
		,.axi_port02_arlen    ( axi_port01_arlen   )
		,.axi_port02_arsize   ( axi_port01_arsize  )
		,.axi_port02_arburst  ( axi_port01_arburst )		
		,.axi_port02_arvalid  ( axi_port01_arvalid )
		,.axi_port02_arready  ( axi_port01_arready )
		,.axi_port02_rid      ( axi_port01_rid     )
		,.axi_port02_rdata    ( axi_port01_rdata   )
		,.axi_port02_rresp    ( axi_port01_rresp   )
		,.axi_port02_rlast    ( axi_port01_rlast   )
		,.axi_port02_rvalid   ( axi_port01_rvalid  )
		,.axi_port02_rready   ( axi_port01_rready  )
		,.sdii_port01_cmd_req        ( sdii_port00_req        )
		,.sdii_port01_cmd_gnt        ( sdii_port00_gnt        )
		,.sdii_port01_cmd_rw         ( sdii_port00_rw         )
		,.sdii_port01_cmd_addr       ( sdii_port00_addr       )
		,.sdii_port01_cmd_len        ( sdii_port00_len        )
		,.sdii_port01_cmd_partial_wrt( sdii_port00_partial_wrt)
		,.sdii_port01_wdata_pop      ( sdii_port00_wdata_pop  )
		,.sdii_port01_wdata          ( sdii_port00_wdata      )
		,.sdii_port01_wmask          ( sdii_port00_wmask      )
		,.sdii_port01_rdata_psh      ( sdii_port00_rdata_psh  )
		,.sdii_port01_rdata          ( sdii_port00_rdata      )
		,.sdii_port03_cmd_req	     ( sdii_port01_req	      )
		,.sdii_port03_cmd_gnt	     ( sdii_port01_gnt	      )
		,.sdii_port03_cmd_rw         ( sdii_port01_rw         )
		,.sdii_port03_cmd_addr       ( sdii_port01_addr       )
		,.sdii_port03_cmd_len        ( sdii_port01_len        )
		,.sdii_port03_cmd_partial_wrt( sdii_port01_partial_wrt)
		,.sdii_port03_wdata_pop      ( sdii_port01_wdata_pop  )
		,.sdii_port03_wdata          ( sdii_port01_wdata      )
		,.sdii_port03_wmask          ( sdii_port01_wmask      )
		,.sdii_port03_rdata_psh      ( sdii_port01_rdata_psh  )
		,.sdii_port03_rdata          ( sdii_port01_rdata      )
		,.i_p0 ( S_port0_data_to_ip  )
		,.i_p1 ( S_port1_data_to_ip  )
		,.o_p0 ( S_port0_data_to_usr )
		,.o_p1 ( S_port1_data_to_usr )
		,.cfg_mc_bus_sel  ( CFG_MC_BUS_SEL )	
	);


endmodule
module cme_ddr_core_top_v1(
    I_mc_rstn, I_mc_pclk,
    I_cfg_rstn, I_cfg_pclk,

    I_mc_uclk, I_pbus_aclk0, I_pbus_aclk1,
    
    O_init_done, O_init_pass,
    

    axi_port00_arid, axi_port00_araddr, axi_port00_arlen, 
    axi_port00_arsize, axi_port00_arburst, axi_port00_arvalid, axi_port00_arready,
    axi_port00_rid, axi_port00_rdata, axi_port00_rresp,
    axi_port00_rlast, axi_port00_rvalid, axi_port00_rready,
    axi_port00_awid, axi_port00_awaddr, axi_port00_awlen,
    axi_port00_awsize, axi_port00_awburst, axi_port00_awvalid, axi_port00_awready,
    axi_port00_wid, axi_port00_wdata, axi_port00_wstrb,
    axi_port00_wlast, axi_port00_wvalid, axi_port00_wready,
    axi_port00_bid, axi_port00_bresp, axi_port00_bvalid, axi_port00_bready,
    

    axi_port01_arid, axi_port01_araddr, axi_port01_arlen, 
    axi_port01_arsize, axi_port01_arburst, axi_port01_arvalid, axi_port01_arready,
    axi_port01_rid, axi_port01_rdata, axi_port01_rresp,
    axi_port01_rlast, axi_port01_rvalid, axi_port01_rready,
    axi_port01_awid, axi_port01_awaddr, axi_port01_awlen,
    axi_port01_awsize, axi_port01_awburst, axi_port01_awvalid, axi_port01_awready,
    axi_port01_wid, axi_port01_wdata, axi_port01_wstrb,
    axi_port01_wlast, axi_port01_wvalid, axi_port01_wready,
    axi_port01_bid, axi_port01_bresp, axi_port01_bvalid, axi_port01_bready,
    

    sdii_port00_req, sdii_port00_gnt, sdii_port00_rw,
    sdii_port00_addr, sdii_port00_len, sdii_port00_partial_wrt,
    sdii_port00_wdata_pop, sdii_port00_wdata, sdii_port00_wmask,
    sdii_port00_rdata_psh, sdii_port00_rdata,
    

    sdii_port01_req, sdii_port01_gnt, sdii_port01_rw,
    sdii_port01_addr, sdii_port01_len, sdii_port01_partial_wrt,
    sdii_port01_wdata_pop, sdii_port01_wdata, sdii_port01_wmask,
    sdii_port01_rdata_psh, sdii_port01_rdata,
	
	O_error_status,O_error_status_en
);


parameter CFG_MC_BUS_SEL = 1'b1 ;
parameter CFG_IP2IP_SEL  = 1'B1 ;


parameter reg32_100 = 32'h42000000 ;
parameter reg32_104 = 32'h02080c51 ;
parameter reg32_108 = 32'h0186a000 ;
parameter reg32_10c = 32'h55e00a0a ;
parameter reg32_110 = 32'ha0000164 ;
parameter reg32_114 = 32'h00000a24 ;
parameter reg32_118 = 32'h04040404 ;
parameter reg32_11c = 32'h00000004 ;
parameter reg32_120 = 32'h2f2f2f2f ;
parameter reg32_124 = 32'h0000002f ;
parameter reg32_128 = 32'hbfbfbfbf ;
parameter reg32_12c = 32'h000000bf ;
parameter reg32_130 = 32'hbfbfbfbf ;
parameter reg32_134 = 32'h000000bf ;
parameter reg32_140 = 32'h86000000 ;
parameter reg32_144 = 32'h00008600 ;
parameter reg32_148 = 32'h80000000 ;
parameter reg32_14c = 32'h3f3f3f3f ;
parameter reg32_150 = 32'h0000003f ;
parameter reg32_180 = 32'h00000018 ;
parameter reg32_184 = 32'h1d700046 ;
parameter reg32_188 = 32'h00000000 ;
parameter reg32_18c = 32'h00000000 ;
parameter reg32_190 = 32'h00100008 ;
parameter reg32_1c0 = 32'h00000001 ;
parameter reg32_1e0 = 32'h01000602 ;
parameter reg32_1e4 = 32'h0c060044 ;
parameter reg32_1e8 = 32'hffff000c ;
parameter reg32_1ec = 32'hfffff105 ;
parameter reg32_1f0 = 32'h060a0406 ;
parameter reg32_1f4 = 32'h80060800 ;
parameter reg32_1f8 = 32'h0c400c30 ;
parameter reg32_1fc = 32'h00000000 ;


parameter reg32_00 = 32'h00000001 ;
parameter reg32_04 = 32'h00258000 ;
parameter reg32_08 = 32'h08080c30 ;
parameter reg32_0c = 32'hfffff124 ;
parameter reg32_10 = 32'h02030305 ;
parameter reg32_14 = 32'h03064010 ;
parameter reg32_18 = 32'h06060e06 ;
parameter reg32_1c = 32'h40040006 ;
parameter reg32_20 = 32'h01000044 ;
parameter reg32_24 = 32'h00030602 ;
parameter reg32_28 = 32'h00000018 ;
parameter reg32_2c = 32'h1d700046 ;
parameter reg32_30 = 32'h01000404 ;
parameter reg32_34 = 32'h020a0344 ;
parameter reg32_38 = 32'h00060c08 ;
parameter reg32_3c = 32'h00000800 ;
parameter reg32_50 = 32'h30000001 ;
parameter reg32_54 = 32'h00000000 ;
parameter reg32_58 = 32'h00000000 ;
parameter reg32_64 = 32'hf0000000 ;
parameter reg32_68 = 32'h00002000 ;


parameter DDR23AXISLV_PORT00_DATABUS = 128;
parameter DDR23AXISLV_PORT01_DATABUS = 128;
parameter DDR23AXISLV_PORT02_DATABUS = 128;
parameter DDR23AXISLV_PORT03_DATABUS = 128;
parameter DDR23AXISLV_PORT04_DATABUS = 128;

parameter DDR23AXISLV_PORT00_IDWIDTH = 16;
parameter DDR23AXISLV_PORT01_IDWIDTH = 16;
parameter DDR23AXISLV_PORT02_IDWIDTH = 16;
parameter DDR23AXISLV_PORT03_IDWIDTH = 16;
parameter DDR23AXISLV_PORT04_IDWIDTH = 16;

parameter DDR23AHBSLV_PORT00_DATABUS = 128;
parameter DDR23AHBSLV_PORT01_DATABUS = 128;
parameter DDR23AHBSLV_PORT02_DATABUS = 128;
parameter DDR23AHBSLV_PORT03_DATABUS = 128;
parameter DDR23AHBSLV_PORT04_DATABUS = 128;

parameter DDR23AXISLV_PORT00_BYTENUM = 16;
parameter DDR23AXISLV_PORT01_BYTENUM = 16;
parameter DDR23AXISLV_PORT02_BYTENUM = 16;
parameter DDR23AXISLV_PORT03_BYTENUM = 16;
parameter DDR23AXISLV_PORT04_BYTENUM = 16;

parameter DDR23AXISLV_PORT00_BITNUM = 4;
parameter DDR23AXISLV_PORT01_BITNUM = 4;
parameter DDR23AXISLV_PORT02_BITNUM = 4;
parameter DDR23AXISLV_PORT03_BITNUM = 4;
parameter DDR23AXISLV_PORT04_BITNUM = 4;


parameter DFI_DATA_WIDTH = 128;


input I_mc_rstn;
input I_mc_pclk;

input I_cfg_rstn;
input I_cfg_pclk;

input I_mc_uclk ;
input I_pbus_aclk0;
input I_pbus_aclk1;

output  O_init_done ;
output  O_init_pass ;


input  [DDR23AXISLV_PORT00_IDWIDTH-1:0] axi_port00_arid	;
input  [31:0] axi_port00_araddr ;
input  [3:0]  axi_port00_arlen  ;
input  [2:0]  axi_port00_arsize ;
input  [1:0]  axi_port00_arburst;
input  axi_port00_arvalid ;
output axi_port00_arready ;
output [DDR23AXISLV_PORT00_IDWIDTH-1:0] axi_port00_rid  ;
output [DDR23AXISLV_PORT00_DATABUS-1:0] axi_port00_rdata;
output [1:0] axi_port00_rresp ;
output axi_port00_rlast  ;
output axi_port00_rvalid ;
input  axi_port00_rready ;
input  [DDR23AXISLV_PORT00_IDWIDTH-1:0] axi_port00_awid ;
input  [31:0] axi_port00_awaddr ;
input  [3:0]  axi_port00_awlen  ;
input  [2:0]  axi_port00_awsize ;
input  [1:0]  axi_port00_awburst;
input  axi_port00_awvalid ;
output axi_port00_awready ;
input  [DDR23AXISLV_PORT00_IDWIDTH-1:0] axi_port00_wid ;
input  [DDR23AXISLV_PORT00_DATABUS-1:0] axi_port00_wdata ;
input  [(DDR23AXISLV_PORT00_DATABUS/8)-1:0] axi_port00_wstrb ;
input  axi_port00_wlast ;
input  axi_port00_wvalid ;
output axi_port00_wready ;
output [DDR23AXISLV_PORT00_IDWIDTH-1:0] axi_port00_bid ;
output [1:0] axi_port00_bresp ;
output axi_port00_bvalid ;
input  axi_port00_bready ;


input  [DDR23AXISLV_PORT02_IDWIDTH-1:0] axi_port01_arid ;
input  [31:0] axi_port01_araddr ;
input  [3:0]  axi_port01_arlen ;
input  [2:0]  axi_port01_arsize ;
input  [1:0]  axi_port01_arburst;
input  axi_port01_arvalid ;
output axi_port01_arready ;
output [DDR23AXISLV_PORT02_IDWIDTH-1:0] axi_port01_rid ;
output [DDR23AXISLV_PORT02_DATABUS-1:0] axi_port01_rdata ;
output [1:0] axi_port01_rresp ;
output axi_port01_rlast ;
output axi_port01_rvalid ;
input  axi_port01_rready ;
input  [DDR23AXISLV_PORT02_IDWIDTH-1:0] axi_port01_awid			;
input  [31:0] axi_port01_awaddr ;
input  [3:0]  axi_port01_awlen ;
input  [2:0]  axi_port01_awsize ;
input  [1:0]  axi_port01_awburst;
input  axi_port01_awvalid ;
output axi_port01_awready ;
input  [DDR23AXISLV_PORT02_IDWIDTH-1:0] axi_port01_wid ;
input  [DDR23AXISLV_PORT02_DATABUS-1:0] axi_port01_wdata ;
input  [(DDR23AXISLV_PORT02_DATABUS/8)-1:0] axi_port01_wstrb ;
input  axi_port01_wlast ;
input  axi_port01_wvalid ;
output axi_port01_wready ;
output [DDR23AXISLV_PORT02_IDWIDTH-1:0] axi_port01_bid ;
output [1:0] axi_port01_bresp ;
output axi_port01_bvalid ;
input  axi_port01_bready ;


input  sdii_port00_req ;
output sdii_port00_gnt ;
input  sdii_port00_rw  ;
input  [31:0] sdii_port00_addr ;
input  [5:0]  sdii_port00_len  ;
input  sdii_port00_partial_wrt ;
output sdii_port00_wdata_pop ;
input  [(DFI_DATA_WIDTH-1):0]     sdii_port00_wdata ;
input  [((DFI_DATA_WIDTH/8)-1):0] sdii_port00_wmask ;
output sdii_port00_rdata_psh ;
output [(DFI_DATA_WIDTH-1):0] sdii_port00_rdata ;


input  sdii_port01_req ;
output sdii_port01_gnt ;
input  sdii_port01_rw  ;
input  [31:0] sdii_port01_addr ;
input  [5:0]  sdii_port01_len  ;
input  sdii_port01_partial_wrt ;
output sdii_port01_wdata_pop ;
input  [(DFI_DATA_WIDTH-1):0]     sdii_port01_wdata ;
input  [((DFI_DATA_WIDTH/8)-1):0] sdii_port01_wmask ;
output sdii_port01_rdata_psh ;
output [(DFI_DATA_WIDTH-1):0] sdii_port01_rdata ;

output [2:0]O_error_status;
output O_error_status_en ;









`ifdef SIM_MASTER_CFG_DDR_CORE_EN
	`define SIM_MASTER_CFG_EN  1
`elsif  SIM_MASTER_CFG_DDR_PHY_EN
	`define SIM_MASTER_CFG_EN  1
`else
`endif










wire mc_clk_src;
wire usr_clk;
wire ip_bus_clk;
wire usrbus_clk;
wire cfg_uclk;
wire cfg_pclk;
wire pll_lck;
wire ctl_ahb_cfg_hclk ;












assign mc_clk_src = I_mc_pclk ;
assign usr_clk    = mc_clk_src ;
assign ip_bus_clk = I_pbus_aclk0 ;
assign usrbus_clk = ip_bus_clk ;
assign cfg_pclk = I_cfg_pclk;
assign cfg_uclk = cfg_pclk;
assign ctl_ahb_cfg_hclk = cfg_pclk ;



wire w_x0connection;
wire w_x1connection;
wire mc_clk ;
wire mc_rstn ;

wire         mcfg_rstn;
wire [15:0]  cbi_pbus_addr;
wire         cbi_pbus_req;
wire [31:0]  cbi_pbus_wdata;
wire         cbi_pbus_write;
wire [31:0]  ctl_ahb_cfg_haddr_i;
wire [2:0]   ctl_ahb_cfg_hburst_i;
wire         ctl_ahb_cfg_hready_i;
wire         ctl_ahb_cfg_hsel_i;
wire [2:0]   ctl_ahb_cfg_hsize_i;
wire [1:0]  ctl_ahb_cfg_htrans_i;
wire [31:0] ctl_ahb_cfg_hwdata_i;
wire            ctl_ahb_cfg_hwrite_i;
wire [31:0] hreg_haddr;
wire [1:0]  hreg_htrans;
wire [31:0] hreg_hwdata;
wire            hreg_hwrite;



wire [15:0] pcsps_pbus_addr;
wire           pcsps_pbus_req;
wire [31:0] pcsps_pbus_wdata;
wire           pcsps_pbus_write;
wire [31:0] phy_ahb_haddr_i;
wire [2:0]  phy_ahb_hburst_i;
wire 	   phy_ahb_hready_i;
wire 	   phy_ahb_hsel_i;
wire [2:0]  phy_ahb_hsize_i;
wire [1:0]  phy_ahb_htrans_i;
wire [31:0] phy_ahb_hwdata_i;
wire 	   phy_ahb_hwrite_i;
wire 	   cbi_pbus_gnt;
wire [31:0] cbi_pbus_rdata;


wire [31:0]	ctl_ahb_cfg_hrdata_o;
wire 	ctl_ahb_cfg_hready_o;
wire [0:0]	ctl_ahb_cfg_hresp_o;

wire      fp_cs_rstn;
wire [31:0]	hreg_hrdata;
wire     hreg_hready_out;

wire      psps_pbus_gnt;
wire [31:0] pcsps_pbus_rdata;
wire [31:0] phy_ahb_hrdata_o;
wire     hy_ahb_hready_o;
wire [0:0]	 phy_ahb_hresp_o;

wire usr_pbus_rstn;

wire [19:0]  dram_dfi_addr_p1;
wire [19:0]  dram_dfi_addr_p0;
wire [2:0]   dram_dfi_bank_p1;
wire [2:0]   dram_dfi_bank_p0;
wire         dram_dfi_cas_n_p1;
wire         dram_dfi_cas_n_p0;
wire [0:0]   dram_dfi_cke_p1;
wire [0:0]   dram_dfi_cke_p0;
wire [0:0]   dram_dfi_cs_n_duplicate_p1;
wire [0:0]   dram_dfi_cs_n_duplicate_p0;
wire [0:0]   dram_dfi_cs_n_p1;
wire [0:0]   dram_dfi_cs_n_p0;
wire         dram_dfi_ctrlupd_req;
wire         dram_dfi_dram_clk_disable;
wire [0:0]	  dram_dfi_ecc_rddata_en_p1;
wire [0:0]	  dram_dfi_ecc_rddata_en_p0;
wire [0:0]	  dram_dfi_ecc_wrdata_en_p1;
wire [0:0]	  dram_dfi_ecc_wrdata_en_p0;
wire [15:0]  dram_dfi_ecc_wrdata_p1;
wire [15:0]  dram_dfi_ecc_wrdata_p0;
wire [1:0]   dram_dfi_ecc_wrmask_p1;
wire [1:0]   dram_dfi_ecc_wrmask_p0;
wire         dram_dfi_init_start;
wire         dram_dfi_ras_n_p1;
wire         dram_dfi_ras_n_p0;
wire [3:0]   dram_dfi_rddata_en_p1;
wire [3:0]   dram_dfi_rddata_en_p0;
wire [31:0]  dram_dfi_rdlvl_delay;
wire [31:0]  dram_dfi_rdlvl_delayn;
wire [0:0]	  dram_dfi_rdlvl_edge;
wire [0:0]	  dram_dfi_rdlvl_en;
wire [63:0]	dram_dfi_rdlvl_gate_delay;
wire [0:0]   dram_dfi_rdlvl_gate_en;
wire [0:0]   dram_dfi_rdlvl_load;
wire   dram_dfi_reset_n_p1;
wire   dram_dfi_reset_n_p0;
wire   ram_dfi_we_n_p1;
wire   dram_dfi_we_n_p0;
wire [0:0]	dram_dfi_wodt_p1;
wire [0:0]	dram_dfi_wodt_p0;
wire [3:0]	dram_dfi_wrdata_en_p1;
wire [3:0]	dram_dfi_wrdata_en_p0;
wire [63:0]	dram_dfi_wrdata_p1;
wire [63:0]	dram_dfi_wrdata_p0;
wire [31:0]	dram_dfi_wrlvl_delay;
wire [0:0]	  dram_dfi_wrlvl_en;
wire [0:0]	  dram_dfi_wrlvl_load;
wire [0:0]	  dram_dfi_wrlvl_strobe;
wire [7:0]	  dram_dfi_wrmask_p1;
wire [7:0]	  dram_dfi_wrmask_p0;
wire 	gating_mc_clk;
wire  intr;
wire [2047:0]	r_ddr23phy_reg;
wire [31:0]	r_system_pll_reg;
wire [31:0] ahb_cfg_haddr_i;
wire [2:0]	 ahb_cfg_hburst_i;
wire 	     ahb_cfg_hready_i;
wire 	     ahb_cfg_hsel_i;
wire [2:0]	 ahb_cfg_hsize_i;
wire [1:0]	 ahb_cfg_htrans_i;
wire [31:0] ahb_cfg_hwdata_i;
wire 	     ahb_cfg_hwrite_i;
wire 	axi_port02_aclk;
wire 	axi_port02_arstn;
wire 	axi_port00_aclk;
wire 	axi_port00_arstn;

wire     dram_dfi_ctrlupd_ack;
wire [15:0]	dram_dfi_ecc_rddata_w1;
wire [15:0]	dram_dfi_ecc_rddata_w0;
wire   dram_dfi_init_complete;
wire [3:0]	  dram_dfi_rddata_valid_w1;
wire [3:0]	  dram_dfi_rddata_valid_w0;
wire [63:0]	dram_dfi_rddata_w1;
wire [63:0]	dram_dfi_rddata_w0;
wire [1:0]	  dram_dfi_rdlvl_gate_mode;
wire [1:0]	  dram_dfi_rdlvl_mode;
wire [31:0]	dram_dfi_rdlvl_resp;
wire [1:0]	  dram_dfi_wrlvl_mode;
wire [3:0]	  dram_dfi_wrlvl_resp;
wire    [2047:0]	ro_ddr23phy_reg;

wire       inner_pbus_req ;
wire 	   NC_s0;








wire S_intr ;
wire         pbus_req;
wire         pbus_gnt;
wire         pbus_write;
wire [15:0] pbus_addr;
wire [31:0] pbus_wdata;
wire [31:0] pbus_rdata;

wire [279:0] S_port0_data_to_ip ;
wire [279:0] S_port1_data_to_ip ;
wire [169:0] S_port0_data_to_usr ;
wire [169:0] S_port1_data_to_usr ;




DDR_CRG_CORE #(
		.cfg_gx_soft_prst      ( 0                   ),
		.cfg_mc_bus_sel        ( CFG_MC_BUS_SEL	     )
) u_ddrc_crg(   

		.axi_port00_aclk_ug    ( I_pbus_aclk0          ),
		.axi_port00_aclk_us    ( w_x0connection      ),
		.axi_port02_aclk_ug    ( I_pbus_aclk1          ),
		.axi_port02_aclk_us    ( w_x1connection      ),
		.bypasspll_mc_clk_x4_ug( I_mc_pclk           ),
		.fp_cs_clk             ( cfg_pclk            ),
		.gating_mc_clk         ( gating_mc_clk       ),
		.mc_clk_ug             ( I_mc_pclk           ),
		
		.p_rc                  (  1'B1),
`ifdef SIMULATION_DDRC_EN
		.pbus_rst_n            ( 1),
`endif
		.pclk_ddr              ( cfg_pclk            ),
		.r_system_pll_reg      ( r_system_pll_reg    ),
	

		.axi_port00_aclk     ( axi_port00_aclk     ),
		.axi_port00_arstn    ( axi_port00_arstn    ),
		.axi_port02_aclk     ( axi_port02_aclk     ),
		.axi_port02_arstn    ( axi_port02_arstn    ),
		.bypasspll_mc_clk_x4 ( bypasspll_mc_clk_x4 ),
		.fp_cs_rstn          ( fp_cs_rstn          ),
		.mc_clk              ( mc_clk              ),
		.mc_clk_us           ( ),
		.mc_rstn             ( mc_rstn             ),
		.mcfg_rstn           ( mcfg_rstn           ),
		.prstn_gx            ( prstn_gx            ),
		.rst_p_n             ( rst_p_n             ),
		.usr_pbus_rstn       ( usr_pbus_rstn       ),
		.x0_async_clk        ( w_x0connection      ),
		.x1_async_clk        ( w_x1connection      )


);



ctrl_wrapper #(
	.bus_ctl_sel     ( CFG_MC_BUS_SEL )
	,.ddr_ctl_iso_en ( 1'b1      )
	,.ddr_ctl_pd     ( 1'b0      )
	,.reg32_50       ( reg32_50  )
	,.reg32_100      ( reg32_100 )
	,.reg32_104      ( reg32_104 )
	,.reg32_108      ( reg32_108 )
	,.reg32_10c      ( reg32_10c )
	,.reg32_110      ( reg32_110 )
	,.reg32_140      ( reg32_140 )
	,.reg32_144      ( reg32_144 )
	,.reg32_148      ( reg32_148 )
	,.reg32_14c      ( reg32_14c )
	,.reg32_150      ( reg32_150 )
	,.reg32_190      ( reg32_190 )
	,.reg32_1c0      ( reg32_1c0 )
	,.reg32_180      ( reg32_180 )
	,.reg32_184      ( reg32_184 )
	,.reg32_188      ( reg32_188 )
	,.reg32_18c      ( reg32_18c )
	,.reg32_1e0      ( reg32_1e0 )
	,.reg32_1e4      ( reg32_1e4 )
	,.reg32_1e8      ( reg32_1e8 )
	,.reg32_1ec      ( reg32_1ec )
	,.reg32_1f0      ( reg32_1f0 )
	,.reg32_1f4      ( reg32_1f4 )
	,.reg32_1f8      ( reg32_1f8 )
	,.reg32_1fc      ( reg32_1fc )
	,.reg32_04       ( reg32_04  )
	,.reg32_08       ( reg32_08  )
	,.reg32_0c       ( reg32_0c  )
	,.reg32_10       ( reg32_10  )
	,.reg32_14       ( reg32_14  )
	,.reg32_18       ( reg32_18  )
	,.reg32_1c       ( reg32_1c  )
	,.reg32_20       ( reg32_20  )
	,.reg32_24       ( reg32_24  )
	,.reg32_28       ( reg32_28  )
	,.reg32_2c       ( reg32_2c  )
	,.reg32_30       ( reg32_30  )
	,.reg32_34       ( reg32_34  )
	,.reg32_38       ( reg32_38  )
	,.reg32_3c       ( reg32_3c  )
	,.reg32_54       ( reg32_54  )
	,.reg32_58       ( reg32_58  )
	,.reg32_64       ( reg32_64  )
	,.reg32_68       ( reg32_68  )
	,.reg32_00       ( reg32_00  )
	,.reg32_118      ( reg32_118 )
	,.reg32_11c      ( reg32_11c )
	,.reg32_120      ( reg32_120 )
	,.reg32_124      ( reg32_124 )
	,.reg32_128      ( reg32_128 )
	,.reg32_12c      ( reg32_12c )
	,.reg32_130      ( reg32_130 )
	,.reg32_134      ( reg32_134 )
	,.reg32_114      ( reg32_114 )




) u_ddrc(

	.ro_ddr23phy_reg         ( ro_ddr23phy_reg          )
`ifdef SIM_MASTER_CFG_DDR_CORE_EN
	,.ahb_cfg_haddr_i				 ( ctl_ahb_cfg_haddr_i			)
	,.ahb_cfg_hburst_i			     ( ctl_ahb_cfg_hburst_i			)
	,.ahb_cfg_hclk				     ( ctl_ahb_cfg_hclk			  	)
	,.ahb_cfg_hready_i			     ( ctl_ahb_cfg_hready_i			)
	,.ahb_cfg_hresetn				 ( mcfg_rstn				    )
	,.ahb_cfg_hsel_i				 ( ctl_ahb_cfg_hsel_i		  	)
	,.ahb_cfg_hsize_i				 ( ctl_ahb_cfg_hsize_i			)
	,.ahb_cfg_htrans_i			     ( ctl_ahb_cfg_htrans_i			)
	,.ahb_cfg_hwdata_i			     ( ctl_ahb_cfg_hwdata_i			)
	,.ahb_cfg_hwrite_i			     ( ctl_ahb_cfg_hwrite_i			)
`endif
	,.axi_port00_aclk				( axi_port00_aclk				) 
	,.axi_port00_arstn			    ( axi_port00_arstn				)
	,.axi_port02_aclk				( axi_port02_aclk				) 
	,.axi_port02_arstn				( axi_port02_arstn				)
`ifdef SIM_DFI_BUS
	,.dram_dfi_ctrlupd_ack			( dram_dfi_ctrlupd_ack			)
	,.dram_dfi_ecc_rddata_w0		( dram_dfi_ecc_rddata_w0		)
	,.dram_dfi_ecc_rddata_w1		( dram_dfi_ecc_rddata_w1		)
	,.dram_dfi_init_complete		( dram_dfi_init_complete		)		
	,.dram_dfi_rddata_valid_w0      ( dram_dfi_rddata_valid_w0		) 	
	,.dram_dfi_rddata_valid_w1	    ( dram_dfi_rddata_valid_w1		)
	,.dram_dfi_rddata_w0			( dram_dfi_rddata_w0			)
	,.dram_dfi_rddata_w1			( dram_dfi_rddata_w1			)
	,.dram_dfi_rdlvl_gate_mode		( dram_dfi_rdlvl_gate_mode		) 		
	,.dram_dfi_rdlvl_mode			( dram_dfi_rdlvl_mode			) 	
	,.dram_dfi_rdlvl_resp			( dram_dfi_rdlvl_resp			) 	
	,.dram_dfi_wrlvl_mode			( dram_dfi_wrlvl_mode			)
	,.dram_dfi_wrlvl_resp			( dram_dfi_wrlvl_resp			) 
`endif
	,.i_p0                    ( S_port0_data_to_ip)
	,.i_p1                    ( S_port1_data_to_ip)
	,.mc_clk				          ( mc_clk				        ) 
	,.mc_rstn				          ( mc_rstn				        )
	

	,.r_ddr23phy_reg				( r_ddr23phy_reg				)
`ifdef SIM_MASTER_CFG_DDR_CORE_EN
	,.ahb_cfg_hrdata_o				( ctl_ahb_cfg_hrdata_o			) 
	,.ahb_cfg_hready_o				( ctl_ahb_cfg_hready_o			) 
	,.ahb_cfg_hresp_o				( ctl_ahb_cfg_hresp_o			)
`endif

`ifdef SIM_DFI_BUS
	,.dram_dfi_addr_p0				( dram_dfi_addr_p0				)
	,.dram_dfi_addr_p1				( dram_dfi_addr_p1				) 
	,.dram_dfi_bank_p0				( dram_dfi_bank_p0				) 
	,.dram_dfi_bank_p1				( dram_dfi_bank_p1				)
	,.dram_dfi_cas_n_p0				( dram_dfi_cas_n_p0				)	 
	,.dram_dfi_cas_n_p1				( dram_dfi_cas_n_p1				)
	,.dram_dfi_cke_p0				( dram_dfi_cke_p0				)
	,.dram_dfi_cke_p1				( dram_dfi_cke_p1				)
	,.dram_dfi_cs_n_duplicate_p0	( dram_dfi_cs_n_duplicate_p0	)
	,.dram_dfi_cs_n_duplicate_p1	( dram_dfi_cs_n_duplicate_p1	)
	,.dram_dfi_cs_n_p0				( dram_dfi_cs_n_p0				)
	,.dram_dfi_cs_n_p1				( dram_dfi_cs_n_p1				)
	,.dram_dfi_ctrlupd_req			( dram_dfi_ctrlupd_req			)
	,.dram_dfi_dram_clk_disable		( dram_dfi_dram_clk_disable		)
	,.dram_dfi_ecc_rddata_en_p0		( dram_dfi_ecc_rddata_en_p0		)
	,.dram_dfi_ecc_rddata_en_p1		( dram_dfi_ecc_rddata_en_p1		)
	,.dram_dfi_ecc_wrdata_en_p0		( dram_dfi_ecc_wrdata_en_p0		)
	,.dram_dfi_ecc_wrdata_en_p1		( dram_dfi_ecc_wrdata_en_p1		)
	,.dram_dfi_ecc_wrdata_p0		( dram_dfi_ecc_wrdata_p0		)
	,.dram_dfi_ecc_wrdata_p1		( dram_dfi_ecc_wrdata_p1		)
	,.dram_dfi_ecc_wrmask_p0		( dram_dfi_ecc_wrmask_p0		)
	,.dram_dfi_ecc_wrmask_p1		( dram_dfi_ecc_wrmask_p1		)
	,.dram_dfi_init_start			( dram_dfi_init_start			)
	,.dram_dfi_ras_n_p0				( dram_dfi_ras_n_p0				)
	,.dram_dfi_ras_n_p1				( dram_dfi_ras_n_p1				)
	,.dram_dfi_rddata_en_p0			( dram_dfi_rddata_en_p0			) 
	,.dram_dfi_rddata_en_p1			( dram_dfi_rddata_en_p1			)
	,.dram_dfi_rdlvl_delay			( dram_dfi_rdlvl_delay			)
	,.dram_dfi_rdlvl_delayn			( dram_dfi_rdlvl_delayn			)
	,.dram_dfi_rdlvl_edge			( dram_dfi_rdlvl_edge			)
	,.dram_dfi_rdlvl_en				( dram_dfi_rdlvl_en				)
	,.dram_dfi_rdlvl_gate_delay		( dram_dfi_rdlvl_gate_delay		) 		
	,.dram_dfi_rdlvl_gate_en		( dram_dfi_rdlvl_gate_en		)
	,.dram_dfi_rdlvl_load			( dram_dfi_rdlvl_load			)
 	,.dram_dfi_reset_n_p0			( dram_dfi_reset_n_p0			)
	,.dram_dfi_reset_n_p1			( dram_dfi_reset_n_p1			) 	
	,.dram_dfi_we_n_p0				( dram_dfi_we_n_p0				)	
	,.dram_dfi_we_n_p1				( dram_dfi_we_n_p1				)
	,.dram_dfi_wodt_p0				( dram_dfi_wodt_p0				) 
	,.dram_dfi_wodt_p1				( dram_dfi_wodt_p1				)
	,.dram_dfi_wrdata_en_p0		( dram_dfi_wrdata_en_p0			)
	,.dram_dfi_wrdata_en_p1		( dram_dfi_wrdata_en_p1			) 	
	,.dram_dfi_wrdata_p0			( dram_dfi_wrdata_p0			) 	
	,.dram_dfi_wrdata_p1			( dram_dfi_wrdata_p1			)
	,.dram_dfi_wrlvl_delay		( dram_dfi_wrlvl_delay			)
	,.dram_dfi_wrlvl_en				( dram_dfi_wrlvl_en				) 
	,.dram_dfi_wrlvl_load			( dram_dfi_wrlvl_load			)
	,.dram_dfi_wrlvl_strobe			( dram_dfi_wrlvl_strobe			)
	,.dram_dfi_wrmask_p0			( dram_dfi_wrmask_p0			)	
	,.dram_dfi_wrmask_p1			( dram_dfi_wrmask_p1			)
`endif
	,.gating_mc_clk				    ( gating_mc_clk				    )
	,.intr                          ( intr                          )

	,.o_p0   						( S_port0_data_to_usr)
	,.o_p1   						( S_port1_data_to_usr)
	,.r_system_pll_reg				( r_system_pll_reg				) 
);

phy_wrapper #(
     .phy_test_iddq  ( 1'b0 )
    ,.dfi_sphy_sel   ( 1'b0 )
    ,.ddr_phy_iso_en ( 1'b1 )
    ,.ddr_phy_pd     ( 1'b1 )

) u_ddr23phy (
`ifndef SIM_INTER_WIRE

	.r_ddr23phy_reg				( r_ddr23phy_reg			)
	
`ifdef SIM_MASTER_CFG_DDR_PHY_EN
	,.ahb_haddr_i			    ( phy_ahb_haddr_i			)
	,.ahb_hburst_i				( phy_ahb_hburst_i			)
	,.ahb_hclk				    ( phy_ahb_hclk				)
	,.ahb_hready_i				( phy_ahb_hready_i			)
	,.ahb_hresetn				( phy_ahb_hresetn			)
	,.ahb_hsel_i				( phy_ahb_hsel_i			)
	,.ahb_hsize_i				( phy_ahb_hsize_i			)
	,.ahb_htrans_i				( phy_ahb_htrans_i			)
	,.ahb_hwdata_i				( phy_ahb_hwdata_i			)
	,.ahb_hwrite_i				( phy_ahb_hwrite_i			)
`endif

	,.bypasspll_mc_clk_x4		( bypasspll_mc_clk_x4		)
`ifdef SIM_DFI_BUS
	,.dram_dfi_addr_p0			( dram_dfi_addr_p0			)
	,.dram_dfi_addr_p1			( dram_dfi_addr_p1			)
	,.dram_dfi_bank_p0			( dram_dfi_bank_p0			)
	,.dram_dfi_bank_p1			( dram_dfi_bank_p1			)
	,.dram_dfi_cas_n_p0			( dram_dfi_cas_n_p0			)
	,.dram_dfi_cas_n_p1			( dram_dfi_cas_n_p1			)
	,.dram_dfi_cke_p0			  ( dram_dfi_cke_p0		  	)
	,.dram_dfi_cke_p1			  ( dram_dfi_cke_p1			  )
	,.dram_dfi_cs_n_duplicate_p0( dram_dfi_cs_n_duplicate_p0 )
	,.dram_dfi_cs_n_duplicate_p1( dram_dfi_cs_n_duplicate_p1 )
	,.dram_dfi_cs_n_p0			( dram_dfi_cs_n_p0			)
	,.dram_dfi_cs_n_p1			( dram_dfi_cs_n_p1			)
	,.dram_dfi_ctrlupd_req		( dram_dfi_ctrlupd_req		)
	,.dram_dfi_dram_clk_disable	( dram_dfi_dram_clk_disable	)
	,.dram_dfi_ecc_rddata_en_p0	( dram_dfi_ecc_rddata_en_p0	)
	,.dram_dfi_ecc_rddata_en_p1	( dram_dfi_ecc_rddata_en_p1	)
	,.dram_dfi_ecc_wrdata_en_p0	( dram_dfi_ecc_wrdata_en_p0	)
	,.dram_dfi_ecc_wrdata_en_p1	( dram_dfi_ecc_wrdata_en_p1	)
	,.dram_dfi_ecc_wrdata_p0	( dram_dfi_ecc_wrdata_p0	)
	,.dram_dfi_ecc_wrdata_p1	( dram_dfi_ecc_wrdata_p1	)
	,.dram_dfi_ecc_wrmask_p0	( dram_dfi_ecc_wrmask_p0	)
	,.dram_dfi_ecc_wrmask_p1	( dram_dfi_ecc_wrmask_p1	)
	,.dram_dfi_init_start		( dram_dfi_init_start		)
	,.dram_dfi_ras_n_p0			( dram_dfi_ras_n_p0			)
	,.dram_dfi_ras_n_p1			( dram_dfi_ras_n_p1			)
	,.dram_dfi_rddata_en_p0		( dram_dfi_rddata_en_p0		)
	,.dram_dfi_rddata_en_p1		( dram_dfi_rddata_en_p1		)
	,.dram_dfi_rdlvl_delay		( dram_dfi_rdlvl_delay		)
	,.dram_dfi_rdlvl_delayn		( dram_dfi_rdlvl_delayn		)
	,.dram_dfi_rdlvl_edge		( dram_dfi_rdlvl_edge		)
	,.dram_dfi_rdlvl_en			( dram_dfi_rdlvl_en			)
	,.dram_dfi_rdlvl_gate_delay	( dram_dfi_rdlvl_gate_delay	)
	,.dram_dfi_rdlvl_gate_en	( dram_dfi_rdlvl_gate_en	)
	,.dram_dfi_rdlvl_load		( dram_dfi_rdlvl_load		)
	,.dram_dfi_reset_n_p0		( dram_dfi_reset_n_p0		)
	,.dram_dfi_reset_n_p1		( dram_dfi_reset_n_p1		)
	,.dram_dfi_we_n_p0			( dram_dfi_we_n_p0			)
	,.dram_dfi_we_n_p1			( dram_dfi_we_n_p1			)
	,.dram_dfi_wodt_p0			( dram_dfi_wodt_p0			)
	,.dram_dfi_wodt_p1			( dram_dfi_wodt_p1			)
	,.dram_dfi_wrdata_en_p0		( dram_dfi_wrdata_en_p0		)
	,.dram_dfi_wrdata_en_p1		( dram_dfi_wrdata_en_p1		)
	,.dram_dfi_wrdata_p0		( dram_dfi_wrdata_p0		)
	,.dram_dfi_wrdata_p1		( dram_dfi_wrdata_p1		)
	,.dram_dfi_wrlvl_delay		( dram_dfi_wrlvl_delay		)
	,.dram_dfi_wrlvl_en			( dram_dfi_wrlvl_en			)
	,.dram_dfi_wrlvl_load		( dram_dfi_wrlvl_load		)
	,.dram_dfi_wrlvl_strobe		( dram_dfi_wrlvl_strobe		)
	,.dram_dfi_wrmask_p0		( dram_dfi_wrmask_p0		)
	,.dram_dfi_wrmask_p1		( dram_dfi_wrmask_p1		)
`endif
	,.mc_clk				      ( mc_clk				        )
	,.mc_clk_rst_n				( mc_rstn				      	)
	

	,.ro_ddr23phy_reg			( ro_ddr23phy_reg			  )
`ifdef SIM_MASTER_CFG_DDR_PHY_EN
	,.ahb_hrdata_o				( phy_ahb_hrdata_o			)
	,.ahb_hready_o				( phy_ahb_hready_o			)
	,.ahb_hresp_o			  	( phy_ahb_hresp_o			  )
`endif

`ifdef SIM_DFI_BUS
	,.dram_dfi_ctrlupd_ack		  ( dram_dfi_ctrlupd_ack		  )
	,.dram_dfi_ecc_rddata_w0	  ( dram_dfi_ecc_rddata_w0	  )
	,.dram_dfi_ecc_rddata_w1	  ( dram_dfi_ecc_rddata_w1	  )	
	,.dram_dfi_init_complete	  ( dram_dfi_init_complete	  )
	,.dram_dfi_rddata_valid_w0	( dram_dfi_rddata_valid_w0	)
	,.dram_dfi_rddata_valid_w1	( dram_dfi_rddata_valid_w1	)
	,.dram_dfi_rddata_w0		    ( dram_dfi_rddata_w0		    )
	,.dram_dfi_rddata_w1	    	( dram_dfi_rddata_w1	    	)
	,.dram_dfi_rdlvl_gate_mode	( dram_dfi_rdlvl_gate_mode	)
	,.dram_dfi_rdlvl_mode		    ( dram_dfi_rdlvl_mode		    )
	,.dram_dfi_rdlvl_resp		    ( dram_dfi_rdlvl_resp		    )
	,.dram_dfi_wrlvl_mode		    ( dram_dfi_wrlvl_mode	    	)
	,.dram_dfi_wrlvl_resp		    ( dram_dfi_wrlvl_resp	    	)
`endif

`endif
);

assign O_init_done = 1'b1;
assign O_init_pass = 1'b1;




array2ddr_mux mux_inst(
		.axi_port00_awid      ( axi_port00_awid    )
		,.axi_port00_awaddr   ( axi_port00_awaddr  )
		,.axi_port00_awlen    ( axi_port00_awlen   )  
		,.axi_port00_awsize   ( axi_port00_awsize  ) 
		,.axi_port00_awburst  ( axi_port00_awburst )
		,.axi_port00_awvalid  ( axi_port00_awvalid )
		,.axi_port00_awready  ( axi_port00_awready )
		,.axi_port00_wid      ( axi_port00_wid     )    
		,.axi_port00_wdata    ( axi_port00_wdata   )  
		,.axi_port00_wstrb    ( axi_port00_wstrb   )  
		,.axi_port00_wlast    ( axi_port00_wlast   )  
		,.axi_port00_wvalid   ( axi_port00_wvalid  ) 
		,.axi_port00_wready   ( axi_port00_wready  ) 
		,.axi_port00_bid      ( axi_port00_bid     )    
		,.axi_port00_bresp    ( axi_port00_bresp   )  
		,.axi_port00_bvalid   ( axi_port00_bvalid  ) 
		,.axi_port00_bready   ( axi_port00_bready  ) 
		,.axi_port00_arid     ( axi_port00_arid    )   
		,.axi_port00_araddr   ( axi_port00_araddr  ) 
		,.axi_port00_arlen    ( axi_port00_arlen   )  
		,.axi_port00_arsize   ( axi_port00_arsize  ) 
		,.axi_port00_arburst  ( axi_port00_arburst )
		,.axi_port00_arvalid  ( axi_port00_arvalid )
		,.axi_port00_arready  ( axi_port00_arready )
		,.axi_port00_rid      ( axi_port00_rid     )
		,.axi_port00_rdata    ( axi_port00_rdata   )
		,.axi_port00_rresp    ( axi_port00_rresp   )
		,.axi_port00_rlast    ( axi_port00_rlast   )
		,.axi_port00_rvalid   ( axi_port00_rvalid  )
		,.axi_port00_rready   ( axi_port00_rready  )
		,.axi_port02_awid     ( axi_port01_awid    ) 
		,.axi_port02_awaddr   ( axi_port01_awaddr  )
		,.axi_port02_awlen    ( axi_port01_awlen   )
		,.axi_port02_awsize   ( axi_port01_awsize  )
		,.axi_port02_awburst  ( axi_port01_awburst )
		,.axi_port02_awvalid  ( axi_port01_awvalid )
		,.axi_port02_awready  ( axi_port01_awready )
		,.axi_port02_wid      ( axi_port01_wid     )
		,.axi_port02_wdata    ( axi_port01_wdata   )
		,.axi_port02_wstrb    ( axi_port01_wstrb   )
		,.axi_port02_wlast    ( axi_port01_wlast   )
		,.axi_port02_wvalid   ( axi_port01_wvalid  )
		,.axi_port02_wready   ( axi_port01_wready  )
		,.axi_port02_bid      ( axi_port01_bid     )
		,.axi_port02_bresp    ( axi_port01_bresp   )
		,.axi_port02_bvalid   ( axi_port01_bvalid  )
		,.axi_port02_bready   ( axi_port01_bready  )
		,.axi_port02_arid     ( axi_port01_arid    )
		,.axi_port02_araddr   ( axi_port01_araddr  )
		,.axi_port02_arlen    ( axi_port01_arlen   )
		,.axi_port02_arsize   ( axi_port01_arsize  )
		,.axi_port02_arburst  ( axi_port01_arburst )		
		,.axi_port02_arvalid  ( axi_port01_arvalid )
		,.axi_port02_arready  ( axi_port01_arready )
		,.axi_port02_rid      ( axi_port01_rid     )
		,.axi_port02_rdata    ( axi_port01_rdata   )
		,.axi_port02_rresp    ( axi_port01_rresp   )
		,.axi_port02_rlast    ( axi_port01_rlast   )
		,.axi_port02_rvalid   ( axi_port01_rvalid  )
		,.axi_port02_rready   ( axi_port01_rready  )
		,.sdii_port01_cmd_req        ( sdii_port00_req        )
		,.sdii_port01_cmd_gnt        ( sdii_port00_gnt        )
		,.sdii_port01_cmd_rw         ( sdii_port00_rw         )
		,.sdii_port01_cmd_addr       ( sdii_port00_addr       )
		,.sdii_port01_cmd_len        ( sdii_port00_len        )
		,.sdii_port01_cmd_partial_wrt( sdii_port00_partial_wrt)
		,.sdii_port01_wdata_pop      ( sdii_port00_wdata_pop  )
		,.sdii_port01_wdata          ( sdii_port00_wdata      )
		,.sdii_port01_wmask          ( sdii_port00_wmask      )
		,.sdii_port01_rdata_psh      ( sdii_port00_rdata_psh  )
		,.sdii_port01_rdata          ( sdii_port00_rdata      )
		,.sdii_port03_cmd_req	     ( sdii_port01_req	      )
		,.sdii_port03_cmd_gnt	     ( sdii_port01_gnt	      )
		,.sdii_port03_cmd_rw         ( sdii_port01_rw         )
		,.sdii_port03_cmd_addr       ( sdii_port01_addr       )
		,.sdii_port03_cmd_len        ( sdii_port01_len        )
		,.sdii_port03_cmd_partial_wrt( sdii_port01_partial_wrt)
		,.sdii_port03_wdata_pop      ( sdii_port01_wdata_pop  )
		,.sdii_port03_wdata          ( sdii_port01_wdata      )
		,.sdii_port03_wmask          ( sdii_port01_wmask      )
		,.sdii_port03_rdata_psh      ( sdii_port01_rdata_psh  )
		,.sdii_port03_rdata          ( sdii_port01_rdata      )
		,.i_p0 ( S_port0_data_to_ip  )
		,.i_p1 ( S_port1_data_to_ip  )
		,.o_p0 ( S_port0_data_to_usr )
		,.o_p1 ( S_port1_data_to_usr )
		,.cfg_mc_bus_sel  ( CFG_MC_BUS_SEL )	
	);


endmodule