data/full_repos/permissive/481885440/verification/digital_filter/digital_filter_tb_random.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/481885440/verification/digital_filter/digital_filter_tb_random.sv:33: Unsupported: Ignoring delay on this delayed statement.\n    always #10 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/481885440/verification/digital_filter/digital_filter_tb_random.sv:42: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/481885440/verification/digital_filter/digital_filter_tb_random.sv:51: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/481885440/verification/digital_filter/digital_filter_tb_random.sv:63: Unsupported: Ignoring delay on this delayed statement.\n            #20;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/481885440/verification/digital_filter/digital_filter_tb_random.sv:55: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/481885440/verification/digital_filter/digital_filter_tb_random.sv:67: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/481885440/verification/digital_filter/digital_filter_tb_random.sv:69: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Error: data/full_repos/permissive/481885440/verification/digital_filter/digital_filter_tb_random.sv:82: syntax error, unexpected \'@\'\n    @(negedge new_data)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/481885440/verification/digital_filter/digital_filter_tb_random.sv:85: Unsupported: Ignoring delay on this delayed statement.\n        #40;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/481885440/verification/digital_filter/digital_filter_tb_random.sv:91: Unsupported: Ignoring delay on this delayed statement.\n                #10;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/481885440/verification/digital_filter/digital_filter_tb_random.sv:93: Unsupported: Ignoring delay on this delayed statement.\n                #10;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/481885440/verification/digital_filter/digital_filter_tb_random.sv:98: Unsupported: Ignoring delay on this delayed statement.\n            #20;\n            ^\n%Error: data/full_repos/permissive/481885440/verification/digital_filter/digital_filter_tb_random.sv:104: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("run.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/481885440/verification/digital_filter/digital_filter_tb_random.sv:105: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, digital_filter_tb_random);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/481885440/verification/digital_filter/digital_filter_tb_random.sv:106: Unsupported: Ignoring delay on this delayed statement.\n        #2000000\n        ^\n%Error: Exiting due to 3 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module digital_filter_tb_random;

    reg clk;
    reg rst_n;
    reg sclk;
    reg cs_n;
    reg unsigned data_in;
    wire unsigned [11:0] data_out;
    wire new_data;
    wire s_data_out;
    supply0 VSS;
    supply1 VDD;


    digital_filter df_inst (
        .clk(clk),
        .rst_n(rst_n),
        .sclk(sclk),
        .cs_n(cs_n),
        .data_in(data_in),
        .data_out(data_out),
        .new_data(new_data),
        .serial_data_out(s_data_out)
        `ifdef USE_POWER_PINS
        ,
        .VSS(VSS),
        .VDD(VDD)
        `endif
    );

    always #10 clk = ~clk;

    initial begin
        clk <= 0;
        rst_n <= 0;
        sclk <= 0;
        cs_n <= 1;
        data_in <= 0;

        #20
        rst_n <= 1;
    end

    integer s1 = 0;
    integer s2 = 0;
    integer count = 0;
    reg unsigned [31:0] adc_out = 0;
    always begin
        #20
        rst_n <= 1;
        data_in <= $random;
        if($realtime > 50) assert(new_data == 0) else $fatal("\033[0;31mERROR\033[0m");
        #20
        while(count < 511) begin
            rst_n <= 1;
            data_in <= $random;
            s1 <= s1 + data_in;
            s2 <= s2 + s1;
            count = count + 1;
            if($realtime > 50) assert(new_data == 0) else $fatal("\033[0;31mERROR\033[0m");
            #20;
        end
        s1 <= s1 + data_in;
        s2 <= s2 + s1;
        #20
        s2 <= s2 + s1;
        #20
        $display("Filter Output Expected: %d, Actual: %d", (s2 >> 6), data_out); 
        assert((s2 >> 6) == data_out) else $fatal("\033[0;31mERROR\033[0m"); 
        assert(new_data == 1) else $fatal("\033[0;31mERROR\033[0m");
        rst_n <= 0;
        adc_out = (s2 >> 6);
        count = 0;
        s1 = 0;
        s2 = 0;
    end

    reg unsigned [11:0] dut_serial_out;
    always begin
    @(negedge new_data)
        #30;
        cs_n <= 0;
        #40;
        if($realtime > 200) begin
            dut_serial_out = 0;
            for(int pos = 0; pos < 12; pos++) begin
                dut_serial_out[11-pos] = s_data_out;
                sclk <= 1;
                #10;
                sclk <= 0;
                #10;
            end
            sclk <= 0;
            $display("Serial Output Expected: %b, Actual: %b", adc_out[11:0], dut_serial_out); 
            assert(adc_out[11:0] == dut_serial_out) else $fatal("\033[0;31mERROR\033[0m");
            #20;
            cs_n <= 1;
        end
    end

    initial begin
        $dumpfile("run.vcd");
        $dumpvars(0, digital_filter_tb_random);
        #2000000
        $display("\033[0;32mPassed!\033[0m");
        $finish(2);
    end

    `ifdef GL
    initial begin
        $sdf_annotate("inputs/design.sdf", df_inst);
    end
    `endif


endmodule
module digital_filter_tb_random;


    reg clk;
    reg rst_n;
    reg sclk;
    reg cs_n;
    reg unsigned data_in;
    wire unsigned [11:0] data_out;
    wire new_data;
    wire s_data_out;
    supply0 VSS;
    supply1 VDD;


    digital_filter df_inst (
        .clk(clk),
        .rst_n(rst_n),
        .sclk(sclk),
        .cs_n(cs_n),
        .data_in(data_in),
        .data_out(data_out),
        .new_data(new_data),
        .serial_data_out(s_data_out)
        `ifdef USE_POWER_PINS
        ,
        .VSS(VSS),
        .VDD(VDD)
        `endif
    );

    always #10 clk = ~clk;

    initial begin
        clk <= 0;
        rst_n <= 0;
        sclk <= 0;
        cs_n <= 1;
        data_in <= 0;

        #20
        rst_n <= 1;
    end

    integer s1 = 0;
    integer s2 = 0;
    integer count = 0;
    reg unsigned [31:0] adc_out = 0;
    always begin
        #20
        rst_n <= 1;
        data_in <= $random;
        if($realtime > 50) assert(new_data == 0) else $fatal("\033[0;31mERROR\033[0m");
        #20
        while(count < 511) begin
            rst_n <= 1;
            data_in <= $random;
            s1 <= s1 + data_in;
            s2 <= s2 + s1;
            count = count + 1;
            if($realtime > 50) assert(new_data == 0) else $fatal("\033[0;31mERROR\033[0m");
            #20;
        end
        s1 <= s1 + data_in;
        s2 <= s2 + s1;
        #20
        s2 <= s2 + s1;
        #20
        $display("Filter Output Expected: %d, Actual: %d", (s2 >> 6), data_out); 
        assert((s2 >> 6) == data_out) else $fatal("\033[0;31mERROR\033[0m"); 
        assert(new_data == 1) else $fatal("\033[0;31mERROR\033[0m");
        rst_n <= 0;
        adc_out = (s2 >> 6);
        count = 0;
        s1 = 0;
        s2 = 0;
    end

    reg unsigned [11:0] dut_serial_out;
    always begin
    @(negedge new_data)
        #30;
        cs_n <= 0;
        #40;
        if($realtime > 200) begin
            dut_serial_out = 0;
            for(int pos = 0; pos < 12; pos++) begin
                dut_serial_out[11-pos] = s_data_out;
                sclk <= 1;
                #10;
                sclk <= 0;
                #10;
            end
            sclk <= 0;
            $display("Serial Output Expected: %b, Actual: %b", adc_out[11:0], dut_serial_out); 
            assert(adc_out[11:0] == dut_serial_out) else $fatal("\033[0;31mERROR\033[0m");
            #20;
            cs_n <= 1;
        end
    end

    initial begin
        $dumpfile("run.vcd");
        $dumpvars(0, digital_filter_tb_random);
        #2000000
        $display("\033[0;32mPassed!\033[0m");
        $finish(2);
    end

    `ifdef GL
    initial begin
        $sdf_annotate("inputs/design.sdf", df_inst);
    end
    `endif


endmodule