data/full_repos/permissive/428611613/cores/edge_detector_v1_0/edge_detector.v
data/verilator_xmls/274e0ec6-71ab-45b9-a30c-828597bff290.xml
module edge_detector
(
  input  wire aclk,

  input  wire din,

  output wire dout
);

  reg [1:0] int_data_reg;

  always @(posedge aclk)
  begin
    int_data_reg <= {int_data_reg[0], din};
  end

  assign dout = ^int_data_reg;

endmodule
module edge_detector
(
  input  wire aclk,

  input  wire din,

  output wire dout
);


  reg [1:0] int_data_reg;

  always @(posedge aclk)
  begin
    int_data_reg <= {int_data_reg[0], din};
  end

  assign dout = ^int_data_reg;

endmodule