data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/xc7_dsp_map.v
1: b'%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/xc7_dsp_map.v:9: Cannot find file containing module: \'DSP48E1\'\n DSP48E1 #(\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx,data/full_repos/permissive/441359809/DSP48E1\n             data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx,data/full_repos/permissive/441359809/DSP48E1.v\n             data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx,data/full_repos/permissive/441359809/DSP48E1.sv\n             DSP48E1\n             DSP48E1.v\n             DSP48E1.sv\n             obj_dir/DSP48E1\n             obj_dir/DSP48E1.v\n             obj_dir/DSP48E1.sv\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/xc7_dsp_map.v:49: Operator ASSIGNW expects 43 bits on the Assign RHS, but Assign RHS\'s VARREF \'P_48\' generates 48 bits.\n                                                                                               : ... In instance __024___05FMUL25X18\n assign Y = P_48;\n          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y);
	parameter A_SIGNED = 0;
	parameter B_SIGNED = 0;
	parameter A_WIDTH = 0;
	parameter B_WIDTH = 0;
	parameter Y_WIDTH = 0;

	wire [47:0] P_48;
	DSP48E1 #(

		.ACASCREG(0),
		.ADREG(0),
		.A_INPUT("DIRECT"),
		.ALUMODEREG(0),
		.AREG(0),
		.BCASCREG(0),
		.B_INPUT("DIRECT"),
		.BREG(0),
		.CARRYINREG(0),
		.CARRYINSELREG(0),
		.CREG(0),
		.DREG(0),
		.INMODEREG(0),
		.MREG(0),
		.OPMODEREG(0),
		.PREG(0),
		.USE_MULT("MULTIPLY"),
		.USE_SIMD("ONE48"),
		.USE_DPORT("FALSE")
	) _TECHMAP_REPLACE_ (

		.A({{5{A[24]}}, A}),
		.B(B),
		.C(48'b0),
		.D(25'b0),
		.CARRYIN(1'b0),
		.P(P_48),

		.INMODE(5'b00000),
		.ALUMODE(4'b0000),
		.OPMODE(7'b000101),
		.CARRYINSEL(3'b000),

		.ACIN(30'b0),
		.BCIN(18'b0),
		.PCIN(48'b0),
		.CARRYIN(1'b0)
	);
	assign Y = P_48;
endmodule
module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y);

	parameter A_SIGNED = 0;
	parameter B_SIGNED = 0;
	parameter A_WIDTH = 0;
	parameter B_WIDTH = 0;
	parameter Y_WIDTH = 0;

	wire [47:0] P_48;
	DSP48E1 #(

		.ACASCREG(0),
		.ADREG(0),
		.A_INPUT("DIRECT"),
		.ALUMODEREG(0),
		.AREG(0),
		.BCASCREG(0),
		.B_INPUT("DIRECT"),
		.BREG(0),
		.CARRYINREG(0),
		.CARRYINSELREG(0),
		.CREG(0),
		.DREG(0),
		.INMODEREG(0),
		.MREG(0),
		.OPMODEREG(0),
		.PREG(0),
		.USE_MULT("MULTIPLY"),
		.USE_SIMD("ONE48"),
		.USE_DPORT("FALSE")
	) _TECHMAP_REPLACE_ (

		.A({{5{A[24]}}, A}),
		.B(B),
		.C(48'b0),
		.D(25'b0),
		.CARRYIN(1'b0),
		.P(P_48),

		.INMODE(5'b00000),
		.ALUMODE(4'b0000),
		.OPMODE(7'b000101),
		.CARRYINSEL(3'b000),

		.ACIN(30'b0),
		.BCIN(18'b0),
		.PCIN(48'b0),
		.CARRYIN(1'b0)
	);
	assign Y = P_48;
endmodule