data/full_repos/permissive/437632408/NVDLA/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_cmd.v
1: b'%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_cmd.v:10: Cannot find include file: simulate_x_tick.vh\n`include "simulate_x_tick.vh" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/437632408/NVDLA/nvdla/rubik,data/full_repos/permissive/437632408/simulate_x_tick.vh\n             data/full_repos/permissive/437632408/NVDLA/nvdla/rubik,data/full_repos/permissive/437632408/simulate_x_tick.vh.v\n             data/full_repos/permissive/437632408/NVDLA/nvdla/rubik,data/full_repos/permissive/437632408/simulate_x_tick.vh.sv\n             simulate_x_tick.vh\n             simulate_x_tick.vh.v\n             simulate_x_tick.vh.sv\n             obj_dir/simulate_x_tick.vh\n             obj_dir/simulate_x_tick.vh.v\n             obj_dir/simulate_x_tick.vh.sv\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_cmd.v:72: Define or directive not defined: \'`x_or_0\'\n            idata_pvld_in <= `x_or_0;\n                             ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_cmd.v:72: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            idata_pvld_in <= `x_or_0;\n                                    ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_cmd.v:108: Define or directive not defined: \'`x_or_0\'\n            idata_count <= {3{`x_or_0}};\n                              ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_cmd.v:108: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n            idata_count <= {3{`x_or_0}};\n                                     ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_cmd.v:161: Define or directive not defined: \'`x_or_0\'\n            odata_adr <= {2{`x_or_0}};\n                            ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_cmd.v:161: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n            odata_adr <= {2{`x_or_0}};\n                                   ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_cmd.v:198: Define or directive not defined: \'`x_or_0\'\n            odata_count_p <= {3{`x_or_0}};\n                                ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_cmd.v:198: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n            odata_count_p <= {3{`x_or_0}};\n                                       ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_cmd.v:219: Define or directive not defined: \'`x_or_0\'\n        odata_pd <= {73{`x_or_0}};\n                        ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_cmd.v:219: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n        odata_pd <= {73{`x_or_0}};\n                               ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_cmd.v:476: Define or directive not defined: \'`x_or_0\'\n    default: dout = {73{`x_or_0}};\n                        ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_cmd.v:476: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n    default: dout = {73{`x_or_0}};\n                               ^\n%Error: Exiting due to 13 error(s)\n'
module NV_NVDLA_RUBIK_wrdma_cmd (
      nvdla_core_clk
    , nvdla_core_rstn
    , idata_prdy
    , idata_pvld
    , idata_pd
    , odata_prdy
    , odata_pvld
    , odata_pd
    , pwrbus_ram_pd
    );

input nvdla_core_clk;
input nvdla_core_rstn;
output idata_prdy;
input idata_pvld;
input [72:0] idata_pd;
input odata_prdy;
output odata_pvld;
output [72:0] odata_pd;
input [31:0] pwrbus_ram_pd;











wire nvdla_core_clk_mgated_enable;
wire nvdla_core_clk_mgated;
NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) );



wire wr_reserving;
reg idata_pvld_in;
reg wr_busy_in;
assign idata_prdy = !wr_busy_in;
wire idata_busy_next;

wire wr_busy_in_next_wr_req_eq_1 = idata_busy_next;
wire wr_busy_in_next_wr_req_eq_0 = (idata_pvld_in && idata_busy_next) && !wr_reserving;
wire wr_busy_in_next = (idata_pvld? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0)
                               ;
wire wr_busy_in_int;
always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin
    if ( !nvdla_core_rstn ) begin
        idata_pvld_in <= 1'b0;
        wr_busy_in <= 1'b0;
    end else begin
        wr_busy_in <= wr_busy_in_next;
        if ( !wr_busy_in_int ) begin
            idata_pvld_in <= idata_pvld && !wr_busy_in;
        end

            else if ( wr_busy_in_int ) begin
        end else begin
            idata_pvld_in <= `x_or_0;
        end

    end
end
reg idata_busy_int;
assign wr_reserving = idata_pvld_in && !idata_busy_int;
wire wr_popping;
reg [2:0] idata_count;
wire [2:0] wr_count_next_wr_popping = wr_reserving ? idata_count : (idata_count - 1'd1);
wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (idata_count + 1'd1) : idata_count;
wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping :
                                               wr_count_next_no_wr_popping;
wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 );
wire wr_count_next_is_4 = wr_popping ? 1'b0 :
                                          wr_count_next_no_wr_popping_is_4;
wire [2:0] wr_limit_muxed;
wire [2:0] wr_limit_reg = wr_limit_muxed;

assign idata_busy_next = wr_count_next_is_4 ||
                          (wr_limit_reg != 3'd0 &&
                           wr_count_next >= wr_limit_reg) ;

assign wr_busy_in_int = idata_pvld_in && idata_busy_int;
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
    if ( !nvdla_core_rstn ) begin
        idata_busy_int <= 1'b0;
        idata_count <= 3'd0;
    end else begin
 idata_busy_int <= idata_busy_next;
 if ( wr_reserving ^ wr_popping ) begin
     idata_count <= wr_count_next;
        end

            else if ( !(wr_reserving ^ wr_popping) ) begin
        end else begin
            idata_count <= {3{`x_or_0}};
        end

    end
end
wire wr_pushing = wr_reserving;



reg [1:0] idata_adr;


wire [1:0] wr_adr_next = idata_adr + 1'd1;
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
    if ( !nvdla_core_rstn ) begin
        idata_adr <= 2'd0;
    end else begin
        if ( wr_pushing ) begin
            idata_adr <= wr_adr_next;
        end
    end
end

wire rd_popping;
reg [1:0] odata_adr;
wire ram_we = wr_pushing && (idata_count > 3'd0 || !rd_popping);
wire ram_iwe = !wr_busy_in && idata_pvld;
wire [72:0] odata_pd_p;
wire [31 : 0] pwrbus_ram_pd;


NV_NVDLA_RUBIK_wrdma_cmd_flopram_rwsa_4x73 ram (
      .clk( nvdla_core_clk )
    , .clk_mgated( nvdla_core_clk_mgated )
    , .pwrbus_ram_pd ( pwrbus_ram_pd )
    , .di ( idata_pd )
    , .iwe ( ram_iwe )
    , .we ( ram_we )
    , .wa ( idata_adr )
    , .ra ( (idata_count == 0) ? 3'd4 : {1'b0,odata_adr} )
    , .dout ( odata_pd_p )
    );
wire [1:0] rd_adr_next_popping = odata_adr + 1'd1;
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
    if ( !nvdla_core_rstn ) begin
        odata_adr <= 2'd0;
    end else begin
        if ( rd_popping ) begin
     odata_adr <= rd_adr_next_popping;
        end

            else if ( !rd_popping ) begin
        end else begin
            odata_adr <= {2{`x_or_0}};
        end

    end
end



assign wr_popping = rd_popping;
wire rd_pushing = wr_pushing;



wire odata_pvld_p;
reg odata_pvld_int;
assign odata_pvld = odata_pvld_int;
assign rd_popping = odata_pvld_p && !(odata_pvld_int && !odata_prdy);
reg [2:0] odata_count_p;

wire [2:0] rd_count_p_next_rd_popping = rd_pushing ? odata_count_p :
                                                                (odata_count_p - 1'd1);
wire [2:0] rd_count_p_next_no_rd_popping = rd_pushing ? (odata_count_p + 1'd1) :
                                                                    odata_count_p;

wire [2:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping :
                                                     rd_count_p_next_no_rd_popping;
assign odata_pvld_p = odata_count_p != 0 || rd_pushing;
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
    if ( !nvdla_core_rstn ) begin
        odata_count_p <= 3'd0;
    end else begin
        if ( rd_pushing || rd_popping ) begin
     odata_count_p <= rd_count_p_next;
        end

            else if ( !(rd_pushing || rd_popping ) ) begin
        end else begin
            odata_count_p <= {3{`x_or_0}};
        end

    end
end
reg [72:0] odata_pd;
wire rd_req_next = (odata_pvld_p || (odata_pvld_int && !odata_prdy)) ;
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
    if ( !nvdla_core_rstn ) begin
        odata_pvld_int <= 1'b0;
    end else begin
        odata_pvld_int <= rd_req_next;
    end
end
always @( posedge nvdla_core_clk_mgated ) begin
    if ( (rd_popping) ) begin
        odata_pd <= odata_pd_p;
    end

        else if ( !((rd_popping)) ) begin
    end else begin
        odata_pd <= {73{`x_or_0}};
    end

end




`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0;
`endif
`endif

assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (idata_pvld_in && !idata_busy_int) || (idata_busy_int != idata_busy_next)) || (rd_pushing || rd_popping || (odata_pvld_int && odata_prdy)) || (wr_pushing))
                               `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED
                               || 1'b1
                               `endif

          `ifndef SYNTH_LEVEL1_COMPILE
          `ifndef SYNTHESIS
                               || master_clk_gating_disabled
          `endif
          `endif

                               ;


`ifdef EMU
`ifdef EMU_FIFO_CFG


assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_RUBIK_wrdma_cmd_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_RUBIK_wrdma_cmd_wr_limit : 3'd0;
`else


assign wr_limit_muxed = 3'd0;
`endif
`else
`ifdef SYNTH_LEVEL1_COMPILE


assign wr_limit_muxed = 3'd0;
`else
`ifdef SYNTHESIS


assign wr_limit_muxed = 3'd0;
`else


reg wr_limit_override;
reg [2:0] wr_limit_override_value;
assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0;
`ifdef NV_ARCHPRO
event reinit;
initial begin
    $display("fifogen reinit initial block %m");
    -> reinit;
end
`endif
`ifdef NV_ARCHPRO
always @( reinit ) begin
`else
initial begin
`endif
    wr_limit_override = 0;
    wr_limit_override_value = 0;
    if ( $test$plusargs( "NV_NVDLA_RUBIK_wrdma_cmd_wr_limit" ) ) begin
        wr_limit_override = 1;
        $value$plusargs( "NV_NVDLA_RUBIK_wrdma_cmd_wr_limit=%d", wr_limit_override_value);
    end
end

`endif
`endif
`endif








`ifdef PERFMON_HISTOGRAM

`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
perfmon_histogram perfmon (
      .clk ( nvdla_core_clk )
    , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} )
    , .curr ( {29'd0, idata_count} )
    );
`endif
`endif

`endif

`ifdef SPYGLASS
`else
`ifdef FV_ASSERT_ON
`else

`endif
`ifdef ASSERT_ON
`ifdef SPYGLASS
wire disable_assert_plusarg = 1'b0;
`else
`ifdef FV_ASSERT_ON
wire disable_assert_plusarg = 1'b0;
`else
wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS");
`endif
`endif
wire assert_enabled = 1'b1 && !disable_assert_plusarg;
`endif
`ifdef FV_ASSERT_ON
`else

`endif
`ifdef ASSERT_ON

`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
always @(assert_enabled) begin
    if ( assert_enabled === 1'b0 ) begin
        $display("Asserts are disabled for %m");
    end
end
`endif
`endif

`endif
`endif




`ifdef FIFOGEN_MODULE_SEARCH
NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y());
`endif




endmodule
module NV_NVDLA_RUBIK_wrdma_cmd (
      nvdla_core_clk
    , nvdla_core_rstn
    , idata_prdy
    , idata_pvld
    , idata_pd
    , odata_prdy
    , odata_pvld
    , odata_pd
    , pwrbus_ram_pd
    );


input nvdla_core_clk;
input nvdla_core_rstn;
output idata_prdy;
input idata_pvld;
input [72:0] idata_pd;
input odata_prdy;
output odata_pvld;
output [72:0] odata_pd;
input [31:0] pwrbus_ram_pd;











wire nvdla_core_clk_mgated_enable;
wire nvdla_core_clk_mgated;
NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) );



wire wr_reserving;
reg idata_pvld_in;
reg wr_busy_in;
assign idata_prdy = !wr_busy_in;
wire idata_busy_next;

wire wr_busy_in_next_wr_req_eq_1 = idata_busy_next;
wire wr_busy_in_next_wr_req_eq_0 = (idata_pvld_in && idata_busy_next) && !wr_reserving;
wire wr_busy_in_next = (idata_pvld? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0)
                               ;
wire wr_busy_in_int;
always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin
    if ( !nvdla_core_rstn ) begin
        idata_pvld_in <= 1'b0;
        wr_busy_in <= 1'b0;
    end else begin
        wr_busy_in <= wr_busy_in_next;
        if ( !wr_busy_in_int ) begin
            idata_pvld_in <= idata_pvld && !wr_busy_in;
        end

            else if ( wr_busy_in_int ) begin
        end else begin
            idata_pvld_in <= `x_or_0;
        end

    end
end
reg idata_busy_int;
assign wr_reserving = idata_pvld_in && !idata_busy_int;
wire wr_popping;
reg [2:0] idata_count;
wire [2:0] wr_count_next_wr_popping = wr_reserving ? idata_count : (idata_count - 1'd1);
wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (idata_count + 1'd1) : idata_count;
wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping :
                                               wr_count_next_no_wr_popping;
wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 );
wire wr_count_next_is_4 = wr_popping ? 1'b0 :
                                          wr_count_next_no_wr_popping_is_4;
wire [2:0] wr_limit_muxed;
wire [2:0] wr_limit_reg = wr_limit_muxed;

assign idata_busy_next = wr_count_next_is_4 ||
                          (wr_limit_reg != 3'd0 &&
                           wr_count_next >= wr_limit_reg) ;

assign wr_busy_in_int = idata_pvld_in && idata_busy_int;
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
    if ( !nvdla_core_rstn ) begin
        idata_busy_int <= 1'b0;
        idata_count <= 3'd0;
    end else begin
 idata_busy_int <= idata_busy_next;
 if ( wr_reserving ^ wr_popping ) begin
     idata_count <= wr_count_next;
        end

            else if ( !(wr_reserving ^ wr_popping) ) begin
        end else begin
            idata_count <= {3{`x_or_0}};
        end

    end
end
wire wr_pushing = wr_reserving;



reg [1:0] idata_adr;


wire [1:0] wr_adr_next = idata_adr + 1'd1;
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
    if ( !nvdla_core_rstn ) begin
        idata_adr <= 2'd0;
    end else begin
        if ( wr_pushing ) begin
            idata_adr <= wr_adr_next;
        end
    end
end

wire rd_popping;
reg [1:0] odata_adr;
wire ram_we = wr_pushing && (idata_count > 3'd0 || !rd_popping);
wire ram_iwe = !wr_busy_in && idata_pvld;
wire [72:0] odata_pd_p;
wire [31 : 0] pwrbus_ram_pd;


NV_NVDLA_RUBIK_wrdma_cmd_flopram_rwsa_4x73 ram (
      .clk( nvdla_core_clk )
    , .clk_mgated( nvdla_core_clk_mgated )
    , .pwrbus_ram_pd ( pwrbus_ram_pd )
    , .di ( idata_pd )
    , .iwe ( ram_iwe )
    , .we ( ram_we )
    , .wa ( idata_adr )
    , .ra ( (idata_count == 0) ? 3'd4 : {1'b0,odata_adr} )
    , .dout ( odata_pd_p )
    );
wire [1:0] rd_adr_next_popping = odata_adr + 1'd1;
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
    if ( !nvdla_core_rstn ) begin
        odata_adr <= 2'd0;
    end else begin
        if ( rd_popping ) begin
     odata_adr <= rd_adr_next_popping;
        end

            else if ( !rd_popping ) begin
        end else begin
            odata_adr <= {2{`x_or_0}};
        end

    end
end



assign wr_popping = rd_popping;
wire rd_pushing = wr_pushing;



wire odata_pvld_p;
reg odata_pvld_int;
assign odata_pvld = odata_pvld_int;
assign rd_popping = odata_pvld_p && !(odata_pvld_int && !odata_prdy);
reg [2:0] odata_count_p;

wire [2:0] rd_count_p_next_rd_popping = rd_pushing ? odata_count_p :
                                                                (odata_count_p - 1'd1);
wire [2:0] rd_count_p_next_no_rd_popping = rd_pushing ? (odata_count_p + 1'd1) :
                                                                    odata_count_p;

wire [2:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping :
                                                     rd_count_p_next_no_rd_popping;
assign odata_pvld_p = odata_count_p != 0 || rd_pushing;
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
    if ( !nvdla_core_rstn ) begin
        odata_count_p <= 3'd0;
    end else begin
        if ( rd_pushing || rd_popping ) begin
     odata_count_p <= rd_count_p_next;
        end

            else if ( !(rd_pushing || rd_popping ) ) begin
        end else begin
            odata_count_p <= {3{`x_or_0}};
        end

    end
end
reg [72:0] odata_pd;
wire rd_req_next = (odata_pvld_p || (odata_pvld_int && !odata_prdy)) ;
always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin
    if ( !nvdla_core_rstn ) begin
        odata_pvld_int <= 1'b0;
    end else begin
        odata_pvld_int <= rd_req_next;
    end
end
always @( posedge nvdla_core_clk_mgated ) begin
    if ( (rd_popping) ) begin
        odata_pd <= odata_pd_p;
    end

        else if ( !((rd_popping)) ) begin
    end else begin
        odata_pd <= {73{`x_or_0}};
    end

end




`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0;
`endif
`endif

assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (idata_pvld_in && !idata_busy_int) || (idata_busy_int != idata_busy_next)) || (rd_pushing || rd_popping || (odata_pvld_int && odata_prdy)) || (wr_pushing))
                               `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED
                               || 1'b1
                               `endif

          `ifndef SYNTH_LEVEL1_COMPILE
          `ifndef SYNTHESIS
                               || master_clk_gating_disabled
          `endif
          `endif

                               ;


`ifdef EMU
`ifdef EMU_FIFO_CFG


assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_RUBIK_wrdma_cmd_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_RUBIK_wrdma_cmd_wr_limit : 3'd0;
`else


assign wr_limit_muxed = 3'd0;
`endif
`else
`ifdef SYNTH_LEVEL1_COMPILE


assign wr_limit_muxed = 3'd0;
`else
`ifdef SYNTHESIS


assign wr_limit_muxed = 3'd0;
`else


reg wr_limit_override;
reg [2:0] wr_limit_override_value;
assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0;
`ifdef NV_ARCHPRO
event reinit;
initial begin
    $display("fifogen reinit initial block %m");
    -> reinit;
end
`endif
`ifdef NV_ARCHPRO
always @( reinit ) begin
`else
initial begin
`endif
    wr_limit_override = 0;
    wr_limit_override_value = 0;
    if ( $test$plusargs( "NV_NVDLA_RUBIK_wrdma_cmd_wr_limit" ) ) begin
        wr_limit_override = 1;
        $value$plusargs( "NV_NVDLA_RUBIK_wrdma_cmd_wr_limit=%d", wr_limit_override_value);
    end
end

`endif
`endif
`endif








`ifdef PERFMON_HISTOGRAM

`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
perfmon_histogram perfmon (
      .clk ( nvdla_core_clk )
    , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} )
    , .curr ( {29'd0, idata_count} )
    );
`endif
`endif

`endif

`ifdef SPYGLASS
`else
`ifdef FV_ASSERT_ON
`else

`endif
`ifdef ASSERT_ON
`ifdef SPYGLASS
wire disable_assert_plusarg = 1'b0;
`else
`ifdef FV_ASSERT_ON
wire disable_assert_plusarg = 1'b0;
`else
wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS");
`endif
`endif
wire assert_enabled = 1'b1 && !disable_assert_plusarg;
`endif
`ifdef FV_ASSERT_ON
`else

`endif
`ifdef ASSERT_ON

`ifndef SYNTH_LEVEL1_COMPILE
`ifndef SYNTHESIS
always @(assert_enabled) begin
    if ( assert_enabled === 1'b0 ) begin
        $display("Asserts are disabled for %m");
    end
end
`endif
`endif

`endif
`endif




`ifdef FIFOGEN_MODULE_SEARCH
NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y());
`endif




endmodule