data/full_repos/permissive/471242277/VerilogCode/basicProcessor_tb.v
1: b'%Error: data/full_repos/permissive/471242277/VerilogCode/basicProcessor_tb.v:2: Cannot find include file: basicProcessor.v\n`include "basicProcessor.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/471242277/VerilogCode,data/full_repos/permissive/471242277/basicProcessor.v\n             data/full_repos/permissive/471242277/VerilogCode,data/full_repos/permissive/471242277/basicProcessor.v.v\n             data/full_repos/permissive/471242277/VerilogCode,data/full_repos/permissive/471242277/basicProcessor.v.sv\n             basicProcessor.v\n             basicProcessor.v.v\n             basicProcessor.v.sv\n             obj_dir/basicProcessor.v\n             obj_dir/basicProcessor.v.v\n             obj_dir/basicProcessor.v.sv\n%Error: data/full_repos/permissive/471242277/VerilogCode/basicProcessor_tb.v:35: Unsupported or unknown PLI call: $monitor\n      $monitor("Time %t, instruction address = %h", $time, instructionAddress);\n      ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/471242277/VerilogCode/basicProcessor_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n      #20;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/471242277/VerilogCode/basicProcessor_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n      #20;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/471242277/VerilogCode/basicProcessor_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n      #8000;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/471242277/VerilogCode/basicProcessor_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n      #20;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/471242277/VerilogCode/basicProcessor_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n      #20;\n      ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n'
module basicProcessor_tb();
   reg [31:0] memory [31:0];
   reg [31:0] instruction [31:0];
   reg clk;
   reg reset;
   wire [31:0] memOut, memAddress, instructionAddress;
   wire WE;
   reg [31:0]cycleCount;
   localparam [31:0] noOp = 32'h00000000;
   localparam [1:0] Load = 2'b01;
   localparam [1:0] mem = 2'b00;
   localparam [1:0] immediate = 2'b01;
   localparam [1:0] write = 2'b10;
   localparam [1:0] move = 2'b11;
   localparam [1:0] jump = 2'b10;
   localparam [1:0] unconditional = 2'b00;
   localparam [1:0] equal = 2'b01;
   localparam [1:0] notEqual = 2'b10;
   localparam [1:0] negative = 2'b11;
   localparam [1:0] alu = 2'b11;

   always @(posedge clk) begin
      if(WE) begin
         memory[memAddress] <= memOut;
         $display("Memory Written address = %h, value = %d",memAddress,memOut);
      end
   end

   initial
   begin 
      $readmemh("program.hex",instruction);
      $monitor("Time %t, instruction address = %h", $time, instructionAddress);

























      reset = 1'b1;
      #20;
      reset = 1'b0;
      #20;
      cycleCount = 0;
      clk = 0;
      #8000;
      $writememh("memory_out.hex", memory);
      $writememh("register_out.hex", p.reg0.regfile);
      $finish;
   end
   
   always
   begin
      $display("Cycle %d", cycleCount);
      clk = 0;
      #20;
      $display("A = %h, B = %h, nPC = %h, op = %b, isTakenBranch = %b, fZero = %b, fNegative = %b", p.A, p.B, p.nPC, p.op, p.isTakenBranch, p.fZero, p.fNegative);
      $display("isALU = %b, aluOut = %h, nFN = %b", p.isALU, p.aluOut, p.nFN);
      clk = 1;
      #20;
      cycleCount = cycleCount + 1;
   end

   Processor p (.memoryIn(memory[memAddress]), .memoryOut(memOut), .memoryAddress(memAddress), .memoryWE(WE), .instruction(instruction[instructionAddress]), .instructionAddress(instructionAddress), .reset(reset), .clk(clk));


endmodule
module basicProcessor_tb();

   reg [31:0] memory [31:0];
   reg [31:0] instruction [31:0];
   reg clk;
   reg reset;
   wire [31:0] memOut, memAddress, instructionAddress;
   wire WE;
   reg [31:0]cycleCount;
   localparam [31:0] noOp = 32'h00000000;
   localparam [1:0] Load = 2'b01;
   localparam [1:0] mem = 2'b00;
   localparam [1:0] immediate = 2'b01;
   localparam [1:0] write = 2'b10;
   localparam [1:0] move = 2'b11;
   localparam [1:0] jump = 2'b10;
   localparam [1:0] unconditional = 2'b00;
   localparam [1:0] equal = 2'b01;
   localparam [1:0] notEqual = 2'b10;
   localparam [1:0] negative = 2'b11;
   localparam [1:0] alu = 2'b11;

   always @(posedge clk) begin
      if(WE) begin
         memory[memAddress] <= memOut;
         $display("Memory Written address = %h, value = %d",memAddress,memOut);
      end
   end

   initial
   begin 
      $readmemh("program.hex",instruction);
      $monitor("Time %t, instruction address = %h", $time, instructionAddress);

























      reset = 1'b1;
      #20;
      reset = 1'b0;
      #20;
      cycleCount = 0;
      clk = 0;
      #8000;
      $writememh("memory_out.hex", memory);
      $writememh("register_out.hex", p.reg0.regfile);
      $finish;
   end
   
   always
   begin
      $display("Cycle %d", cycleCount);
      clk = 0;
      #20;
      $display("A = %h, B = %h, nPC = %h, op = %b, isTakenBranch = %b, fZero = %b, fNegative = %b", p.A, p.B, p.nPC, p.op, p.isTakenBranch, p.fZero, p.fNegative);
      $display("isALU = %b, aluOut = %h, nFN = %b", p.isALU, p.aluOut, p.nFN);
      clk = 1;
      #20;
      cycleCount = cycleCount + 1;
   end

   Processor p (.memoryIn(memory[memAddress]), .memoryOut(memOut), .memoryAddress(memAddress), .memoryWE(WE), .instruction(instruction[instructionAddress]), .instructionAddress(instructionAddress), .reset(reset), .clk(clk));


endmodule