data/full_repos/permissive/502544928/ra_packetizer_cache.v
1: b'%Warning-WIDTH: data/full_repos/permissive/502544928/ra_packetizer_cache.v:263: Operator COND expects 45 bits on the Conditional False, but Conditional False\'s VARREF \'t_net2cache_iAddr\' generates 32 bits.\n                                                                              : ... In instance ra_packetizer_cache\n  t_net2cache_iAddr   <= iClear? 0 : (i_read_req | i_write_req0)? \n                                                                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/502544928/ra_packetizer_cache.v:263: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 45 bits.\n                                                                              : ... In instance ra_packetizer_cache\n  t_net2cache_iAddr   <= iClear? 0 : (i_read_req | i_write_req0)? \n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/502544928/ra_packetizer_cache.v:266: Operator COND expects 45 bits on the Conditional False, but Conditional False\'s VARREF \'t_net2cache_iData\' generates 32 bits.\n                                                                              : ... In instance ra_packetizer_cache\n                         0 : i_write_req1? flit_received : t_net2cache_iData;\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/502544928/ra_packetizer_cache.v:265: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 45 bits.\n                                                                              : ... In instance ra_packetizer_cache\n  t_net2cache_iData   <= iClear? 0 : (i_read_req | i_write_req0)? \n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/502544928/ra_packetizer_cache.v:270: Operator COND expects 45 bits on the Conditional False, but Conditional False\'s VARREF \'t_net2cache_dAddr\' generates 32 bits.\n                                                                              : ... In instance ra_packetizer_cache\n  t_net2cache_dAddr   <= dClear? 0 : (d_read_req | d_write_req0)? \n                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/502544928/ra_packetizer_cache.v:270: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 45 bits.\n                                                                              : ... In instance ra_packetizer_cache\n  t_net2cache_dAddr   <= dClear? 0 : (d_read_req | d_write_req0)? \n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/502544928/ra_packetizer_cache.v:273: Operator COND expects 45 bits on the Conditional False, but Conditional False\'s VARREF \'t_net2cache_dData\' generates 32 bits.\n                                                                              : ... In instance ra_packetizer_cache\n                         0 : d_write_req1? flit_received : t_net2cache_dData;\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/502544928/ra_packetizer_cache.v:272: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 45 bits.\n                                                                              : ... In instance ra_packetizer_cache\n  t_net2cache_dData   <= dClear? 0 : (d_read_req | d_write_req0)?\n                      ^~\n%Error: Exiting due to 8 warning(s)\n'
module ra_packetizer_cache #(parameter CORE = 0, DATA_WIDTH = 32, ADDRESS_BITS = 32, 
							 VC_BITS = 1, ID_BITS = 4, EXTRA  = 2, TYPE_BITS = 2) ( 
					
				     clock, reset,  
					 

				     net2cache_iRead, net2cache_iWrite, 
					 net2cache_iAddr, net2cache_iData, 
					 
				     cache2net_iAddr, cache2net_iData, 
					 cache2net_iValid, cache2net_iReady,
				     
				     net2cache_dRead, net2cache_dWrite, 
					 net2cache_dAddr, net2cache_dData, 
					 
				     cache2net_dAddr, cache2net_dData, 
					 cache2net_dValid, cache2net_dReady,
					 

				     flit_to_send, v_send_flit, 
					 
  					 flit_received, v_rec_flit, 
					 ready
				     
);
localparam VC_PER_PORTS  = (1 << VC_BITS); 
localparam FLOW_BITS     = (2*ID_BITS) + EXTRA;  
localparam FLIT_WIDTH    = FLOW_BITS + TYPE_BITS + VC_BITS + DATA_WIDTH;
localparam HEAD = 'b10, BODY = 'b00, TAIL = 'b01, ALL= 'b11;
localparam IDLE = 0, SEND = 1, SEND2 = 2, DONE = 3; 

input clock, reset; 

output net2cache_iRead, net2cache_iWrite;
output [ADDRESS_BITS-1:0]net2cache_iAddr; 
output [DATA_WIDTH-1:0]   net2cache_iData;

input cache2net_iValid , cache2net_iReady;
input [ADDRESS_BITS-1:0] cache2net_iAddr;
input [DATA_WIDTH-1:0]   cache2net_iData;

output net2cache_dRead, net2cache_dWrite; 
output [ADDRESS_BITS-1:0] net2cache_dAddr;
output [DATA_WIDTH-1:0]   net2cache_dData;

input cache2net_dValid,  cache2net_dReady;
input [ADDRESS_BITS-1:0] cache2net_dAddr;
input [DATA_WIDTH-1:0]   cache2net_dData;

output [FLIT_WIDTH -1:0] flit_to_send;
output v_send_flit; 
					 
input [FLIT_WIDTH -1:0] flit_received; 
input v_rec_flit; 
input ready;

wire [ID_BITS - 1: 0] core_ID = CORE; 
reg [FLIT_WIDTH -1:0] flit_to_send;
reg v_send_flit; 

reg t_cache2net_iReady, t_cache2net_dReady;

reg [FLIT_WIDTH -1:0] iflit_to_send0, iflit_to_send1; 
reg iv_send_flit0, iv_send_flit1;

reg [FLIT_WIDTH -1:0] iflit_received0, iflit_received1; 
reg iv_rec_flit0, iv_rec_flit1;

reg [FLIT_WIDTH -1:0] dflit_to_send0, dflit_to_send1; 
reg dv_send_flit0, dv_send_flit1;

reg [FLIT_WIDTH -1:0] dflit_received0, dflit_received1; 
reg dv_rec_flit0, dv_rec_flit1;

reg [1:0] iState, dState; 
reg send_turn; 
reg [ID_BITS - 1: 0] i_requester, d_requester; 
reg last_ireq_write, last_dreq_write; 

wire [ID_BITS - 1: 0]   source            = core_ID; 
wire [ID_BITS - 1: 0]   idestination      = i_requester; 
wire [EXTRA - 1: 0]     isub_flow         = 2;
wire [TYPE_BITS - 1:0]  iflit_type0       = last_ireq_write?  ALL : HEAD;
wire [TYPE_BITS - 1:0]  iflit_type1       = TAIL;
wire [VC_BITS - 1:0]    iflit_vc          = 0;
wire [DATA_WIDTH - 1:0] iflit_payload0    = cache2net_iAddr; 

wire [ID_BITS - 1: 0]   ddestination      = d_requester; 
wire [EXTRA - 1: 0]     dsub_flow         = 3;
wire [TYPE_BITS - 1:0]  dflit_type0       = last_dreq_write?  ALL : HEAD;
wire [TYPE_BITS - 1:0]  dflit_type1       = TAIL;
wire [VC_BITS - 1:0]    dflit_vc          = 0;
wire [DATA_WIDTH - 1:0] dflit_payload0    = cache2net_dAddr; 

wire [EXTRA - 1: 0]     rec_sub_flow  = flit_received[(FLIT_WIDTH-(2*ID_BITS)-1) -: EXTRA];
wire [ID_BITS - 1: 0]   rec_source    = flit_received[(FLIT_WIDTH -1) -: ID_BITS];
wire [TYPE_BITS - 1: 0] rec_flit_type = flit_received[((FLIT_WIDTH - FLOW_BITS) -1) -: TYPE_BITS];
wire i_read_req   = ((rec_sub_flow == 0) & (rec_flit_type == ALL) & (v_rec_flit));
wire i_write_req0 = ((rec_sub_flow == 0) & (rec_flit_type == HEAD) & (v_rec_flit));
wire i_write_req1 = ((rec_sub_flow == 0) & (rec_flit_type == TAIL) & (v_rec_flit));

wire d_read_req   = ((rec_sub_flow == 1) & (rec_flit_type == ALL) & (v_rec_flit));
wire d_write_req0 = ((rec_sub_flow == 1) & (rec_flit_type == HEAD) & (v_rec_flit));
wire d_write_req1 = ((rec_sub_flow == 1) & (rec_flit_type == TAIL) & (v_rec_flit));
		
reg t_net2cache_iRead, t_net2cache_iWrite;
reg [ADDRESS_BITS-1:0] t_net2cache_iAddr; 
reg [DATA_WIDTH-1:0]   t_net2cache_iData;

reg t_net2cache_dRead, t_net2cache_dWrite;
reg [ADDRESS_BITS-1:0] t_net2cache_dAddr; 
reg [DATA_WIDTH-1:0]   t_net2cache_dData;

wire iClear = (t_cache2net_iReady & (t_net2cache_iRead | t_net2cache_iWrite)); 
wire dClear = (t_cache2net_dReady & (t_net2cache_dRead | t_net2cache_dWrite)); 

assign net2cache_iRead   = (t_cache2net_iReady)?  t_net2cache_iRead : 0; 
assign net2cache_iWrite  = (t_cache2net_iReady)?  t_net2cache_iWrite: 0;
assign net2cache_iAddr   = (t_cache2net_iReady)?  t_net2cache_iAddr : 0; 
assign net2cache_iData   = (t_cache2net_iReady)?  t_net2cache_iData: 0;

assign net2cache_dRead   = (t_cache2net_dReady)?  t_net2cache_dRead : 0; 
assign net2cache_dWrite  = (t_cache2net_dReady)?  t_net2cache_dWrite: 0;
assign net2cache_dAddr   = (t_cache2net_dReady)?  t_net2cache_dAddr : 0; 
assign net2cache_dData   = (t_cache2net_dReady)?  t_net2cache_dData: 0;

wire change_turn = (((iState == IDLE) & (~cache2net_iValid)) |
				   ((dState == IDLE) & (~cache2net_dValid))  |
				   ((iState == DONE) | (dState == DONE)));


always @ (posedge clock) begin  
	if(reset == 1) begin 
		iflit_to_send0     <= 0;
		iv_send_flit0      <= 0;
		iflit_to_send1     <= 0;
		iv_send_flit1      <= 0;
		iState             <= IDLE; 
	end 
	else begin 
		case (iState)
			IDLE: begin
				iflit_to_send0     <= {source, idestination, isub_flow, iflit_type0, iflit_vc, iflit_payload0};
				iv_send_flit0      <= cache2net_iValid;
				iflit_to_send1     <= last_ireq_write? 0 : 
									 {source, idestination, isub_flow, iflit_type1, iflit_vc, cache2net_iData};
				iv_send_flit1      <= last_ireq_write? 0 : cache2net_iValid;	
				iState             <= cache2net_iValid? SEND : IDLE;
			end
		
		SEND: begin
			if((send_turn == 0) & (ready)) begin
				iflit_to_send0  <= 0; 
				iv_send_flit0   <= 0; 
				iState          <=  iv_send_flit1? SEND2: DONE;
			end
		end
		
		SEND2: begin
			if((send_turn == 0) & (ready)) begin
				iflit_to_send1  <= 0; 
				iv_send_flit1   <= 0; 
				iState          <= DONE;
			end 
		end
		
		DONE: begin
				iState        <=  IDLE;
		end
		
		default: iState <= IDLE;
		endcase   
	end
 end
 

always @ (posedge clock) begin  
	if(reset == 1) begin 
		dflit_to_send0     <= 0;
		dv_send_flit0      <= 0;
		dflit_to_send1     <= 0;
		dv_send_flit1      <= 0;
		dState             <= IDLE; 
	end 
	else begin 
		case (dState)
			IDLE: begin
				dflit_to_send0     <= {source, ddestination, dsub_flow, dflit_type0, dflit_vc, dflit_payload0};
				dv_send_flit0      <= cache2net_dValid;
				dflit_to_send1     <= last_dreq_write? 0 : 
									 {source, ddestination, dsub_flow, dflit_type1, dflit_vc, cache2net_dData};
				dv_send_flit1      <= last_dreq_write? 0 : cache2net_dValid;	
				dState             <= cache2net_dValid? SEND : IDLE;
			end
		
		SEND: begin
			if((send_turn == 1) & (ready)) begin
				dflit_to_send0  <= 0; 
				dv_send_flit0   <= 0; 
				dState          <=  dv_send_flit1? SEND2: DONE;
			end
		end
		
		SEND2: begin
			if((send_turn == 1) & (ready)) begin
				dflit_to_send1  <= 0; 
				dv_send_flit1   <= 0; 	
				dState          <= DONE;
			end 
		end
		
		DONE: begin
				dState        <=  IDLE;
		end
		
		default: dState <= IDLE;
		endcase   
	end
 end


always @ (posedge clock) begin 
	if(reset == 1) begin 
		t_net2cache_iRead   <= 0; 
		t_net2cache_iWrite  <= 0; 
		t_net2cache_iAddr   <= 0; 
		t_net2cache_iData   <= 0;
		
		t_net2cache_dRead   <= 0; 
		t_net2cache_dWrite  <= 0; 
		t_net2cache_dAddr   <= 0; 
		t_net2cache_dData   <= 0;
		
		t_cache2net_iReady  <= 0; 
		t_cache2net_dReady  <= 0; 
	end 
	else begin 
		t_net2cache_iRead   <= iClear? 0 : i_read_req? 1   : t_net2cache_iRead; 
		t_net2cache_iWrite  <= iClear? 0 : i_write_req1? 1 : t_net2cache_iWrite; 
		t_net2cache_iAddr   <= iClear? 0 : (i_read_req | i_write_req0)? 
		                       flit_received : t_net2cache_iAddr;
		t_net2cache_iData   <= iClear? 0 : (i_read_req | i_write_req0)? 
		                       0 : i_write_req1? flit_received : t_net2cache_iData;
		
		t_net2cache_dRead   <= dClear? 0 : d_read_req? 1   : t_net2cache_dRead; 
		t_net2cache_dWrite  <= dClear? 0 : d_write_req1? 1 : t_net2cache_dWrite;  
		t_net2cache_dAddr   <= dClear? 0 : (d_read_req | d_write_req0)? 
		                      flit_received : t_net2cache_dAddr;
		t_net2cache_dData   <= dClear? 0 : (d_read_req | d_write_req0)?
		                       0 : d_write_req1? flit_received : t_net2cache_dData;
							   
		t_cache2net_iReady  <= cache2net_iReady; 
		t_cache2net_dReady  <= cache2net_dReady; 
	end
end
				   

always @ (posedge clock) begin  
	if(reset == 1) begin 
		send_turn        <= 0;

		i_requester      <= 0;
		last_ireq_write  <= 0;
		
		d_requester      <= 0;
		last_dreq_write  <= 0;

		flit_to_send     <= 0; 
		v_send_flit      <= 0; 
	end 
	else begin 

		send_turn        <= ((iState == IDLE) & cache2net_iValid)? 0 : 
							((dState == IDLE) & cache2net_dValid)? 1 : 
							((iState == DONE) | (dState == DONE))? (~send_turn) : send_turn;
		
		i_requester      <= (i_read_req | i_write_req1)? rec_source : cache2net_iValid? 0 : i_requester;
		last_ireq_write  <= i_write_req1? 1 : cache2net_iValid? 0 : last_ireq_write;
		
		d_requester      <= (d_read_req | d_write_req1)? rec_source : cache2net_dValid? 0 : d_requester;
		last_dreq_write  <= d_write_req1? 1 : cache2net_dValid? 0 : last_dreq_write;
		
		flit_to_send     <= (ready & (iState == SEND) & (send_turn == 0))?  iflit_to_send0 : 
							(ready & (iState == SEND2) & (send_turn == 0))? iflit_to_send1 : 
							(ready & (dState == SEND) & (send_turn == 1))?  dflit_to_send0 : 
							(ready & (dState == SEND2) & (send_turn == 1))? dflit_to_send1 : 0; 
						 
		v_send_flit      <= (ready & (iState == SEND) & (send_turn == 0))?  iv_send_flit0  :
							(ready & (iState == SEND2) & (send_turn == 0))? iv_send_flit1 : 
							(ready & (dState == SEND) & (send_turn == 1))?  dv_send_flit0 : 
							(ready & (dState == SEND2) & (send_turn == 1))? dv_send_flit1 : 0;
	end
end


endmodule
module ra_packetizer_cache #(parameter CORE = 0, DATA_WIDTH = 32, ADDRESS_BITS = 32, 
							 VC_BITS = 1, ID_BITS = 4, EXTRA  = 2, TYPE_BITS = 2) ( 
					
				     clock, reset,  
					 

				     net2cache_iRead, net2cache_iWrite, 
					 net2cache_iAddr, net2cache_iData, 
					 
				     cache2net_iAddr, cache2net_iData, 
					 cache2net_iValid, cache2net_iReady,
				     
				     net2cache_dRead, net2cache_dWrite, 
					 net2cache_dAddr, net2cache_dData, 
					 
				     cache2net_dAddr, cache2net_dData, 
					 cache2net_dValid, cache2net_dReady,
					 

				     flit_to_send, v_send_flit, 
					 
  					 flit_received, v_rec_flit, 
					 ready
				     
);

localparam VC_PER_PORTS  = (1 << VC_BITS); 
localparam FLOW_BITS     = (2*ID_BITS) + EXTRA;  
localparam FLIT_WIDTH    = FLOW_BITS + TYPE_BITS + VC_BITS + DATA_WIDTH;
localparam HEAD = 'b10, BODY = 'b00, TAIL = 'b01, ALL= 'b11;
localparam IDLE = 0, SEND = 1, SEND2 = 2, DONE = 3; 

input clock, reset; 

output net2cache_iRead, net2cache_iWrite;
output [ADDRESS_BITS-1:0]net2cache_iAddr; 
output [DATA_WIDTH-1:0]   net2cache_iData;

input cache2net_iValid , cache2net_iReady;
input [ADDRESS_BITS-1:0] cache2net_iAddr;
input [DATA_WIDTH-1:0]   cache2net_iData;

output net2cache_dRead, net2cache_dWrite; 
output [ADDRESS_BITS-1:0] net2cache_dAddr;
output [DATA_WIDTH-1:0]   net2cache_dData;

input cache2net_dValid,  cache2net_dReady;
input [ADDRESS_BITS-1:0] cache2net_dAddr;
input [DATA_WIDTH-1:0]   cache2net_dData;

output [FLIT_WIDTH -1:0] flit_to_send;
output v_send_flit; 
					 
input [FLIT_WIDTH -1:0] flit_received; 
input v_rec_flit; 
input ready;

wire [ID_BITS - 1: 0] core_ID = CORE; 
reg [FLIT_WIDTH -1:0] flit_to_send;
reg v_send_flit; 

reg t_cache2net_iReady, t_cache2net_dReady;

reg [FLIT_WIDTH -1:0] iflit_to_send0, iflit_to_send1; 
reg iv_send_flit0, iv_send_flit1;

reg [FLIT_WIDTH -1:0] iflit_received0, iflit_received1; 
reg iv_rec_flit0, iv_rec_flit1;

reg [FLIT_WIDTH -1:0] dflit_to_send0, dflit_to_send1; 
reg dv_send_flit0, dv_send_flit1;

reg [FLIT_WIDTH -1:0] dflit_received0, dflit_received1; 
reg dv_rec_flit0, dv_rec_flit1;

reg [1:0] iState, dState; 
reg send_turn; 
reg [ID_BITS - 1: 0] i_requester, d_requester; 
reg last_ireq_write, last_dreq_write; 

wire [ID_BITS - 1: 0]   source            = core_ID; 
wire [ID_BITS - 1: 0]   idestination      = i_requester; 
wire [EXTRA - 1: 0]     isub_flow         = 2;
wire [TYPE_BITS - 1:0]  iflit_type0       = last_ireq_write?  ALL : HEAD;
wire [TYPE_BITS - 1:0]  iflit_type1       = TAIL;
wire [VC_BITS - 1:0]    iflit_vc          = 0;
wire [DATA_WIDTH - 1:0] iflit_payload0    = cache2net_iAddr; 

wire [ID_BITS - 1: 0]   ddestination      = d_requester; 
wire [EXTRA - 1: 0]     dsub_flow         = 3;
wire [TYPE_BITS - 1:0]  dflit_type0       = last_dreq_write?  ALL : HEAD;
wire [TYPE_BITS - 1:0]  dflit_type1       = TAIL;
wire [VC_BITS - 1:0]    dflit_vc          = 0;
wire [DATA_WIDTH - 1:0] dflit_payload0    = cache2net_dAddr; 

wire [EXTRA - 1: 0]     rec_sub_flow  = flit_received[(FLIT_WIDTH-(2*ID_BITS)-1) -: EXTRA];
wire [ID_BITS - 1: 0]   rec_source    = flit_received[(FLIT_WIDTH -1) -: ID_BITS];
wire [TYPE_BITS - 1: 0] rec_flit_type = flit_received[((FLIT_WIDTH - FLOW_BITS) -1) -: TYPE_BITS];
wire i_read_req   = ((rec_sub_flow == 0) & (rec_flit_type == ALL) & (v_rec_flit));
wire i_write_req0 = ((rec_sub_flow == 0) & (rec_flit_type == HEAD) & (v_rec_flit));
wire i_write_req1 = ((rec_sub_flow == 0) & (rec_flit_type == TAIL) & (v_rec_flit));

wire d_read_req   = ((rec_sub_flow == 1) & (rec_flit_type == ALL) & (v_rec_flit));
wire d_write_req0 = ((rec_sub_flow == 1) & (rec_flit_type == HEAD) & (v_rec_flit));
wire d_write_req1 = ((rec_sub_flow == 1) & (rec_flit_type == TAIL) & (v_rec_flit));
		
reg t_net2cache_iRead, t_net2cache_iWrite;
reg [ADDRESS_BITS-1:0] t_net2cache_iAddr; 
reg [DATA_WIDTH-1:0]   t_net2cache_iData;

reg t_net2cache_dRead, t_net2cache_dWrite;
reg [ADDRESS_BITS-1:0] t_net2cache_dAddr; 
reg [DATA_WIDTH-1:0]   t_net2cache_dData;

wire iClear = (t_cache2net_iReady & (t_net2cache_iRead | t_net2cache_iWrite)); 
wire dClear = (t_cache2net_dReady & (t_net2cache_dRead | t_net2cache_dWrite)); 

assign net2cache_iRead   = (t_cache2net_iReady)?  t_net2cache_iRead : 0; 
assign net2cache_iWrite  = (t_cache2net_iReady)?  t_net2cache_iWrite: 0;
assign net2cache_iAddr   = (t_cache2net_iReady)?  t_net2cache_iAddr : 0; 
assign net2cache_iData   = (t_cache2net_iReady)?  t_net2cache_iData: 0;

assign net2cache_dRead   = (t_cache2net_dReady)?  t_net2cache_dRead : 0; 
assign net2cache_dWrite  = (t_cache2net_dReady)?  t_net2cache_dWrite: 0;
assign net2cache_dAddr   = (t_cache2net_dReady)?  t_net2cache_dAddr : 0; 
assign net2cache_dData   = (t_cache2net_dReady)?  t_net2cache_dData: 0;

wire change_turn = (((iState == IDLE) & (~cache2net_iValid)) |
				   ((dState == IDLE) & (~cache2net_dValid))  |
				   ((iState == DONE) | (dState == DONE)));


always @ (posedge clock) begin  
	if(reset == 1) begin 
		iflit_to_send0     <= 0;
		iv_send_flit0      <= 0;
		iflit_to_send1     <= 0;
		iv_send_flit1      <= 0;
		iState             <= IDLE; 
	end 
	else begin 
		case (iState)
			IDLE: begin
				iflit_to_send0     <= {source, idestination, isub_flow, iflit_type0, iflit_vc, iflit_payload0};
				iv_send_flit0      <= cache2net_iValid;
				iflit_to_send1     <= last_ireq_write? 0 : 
									 {source, idestination, isub_flow, iflit_type1, iflit_vc, cache2net_iData};
				iv_send_flit1      <= last_ireq_write? 0 : cache2net_iValid;	
				iState             <= cache2net_iValid? SEND : IDLE;
			end
		
		SEND: begin
			if((send_turn == 0) & (ready)) begin
				iflit_to_send0  <= 0; 
				iv_send_flit0   <= 0; 
				iState          <=  iv_send_flit1? SEND2: DONE;
			end
		end
		
		SEND2: begin
			if((send_turn == 0) & (ready)) begin
				iflit_to_send1  <= 0; 
				iv_send_flit1   <= 0; 
				iState          <= DONE;
			end 
		end
		
		DONE: begin
				iState        <=  IDLE;
		end
		
		default: iState <= IDLE;
		endcase   
	end
 end
 

always @ (posedge clock) begin  
	if(reset == 1) begin 
		dflit_to_send0     <= 0;
		dv_send_flit0      <= 0;
		dflit_to_send1     <= 0;
		dv_send_flit1      <= 0;
		dState             <= IDLE; 
	end 
	else begin 
		case (dState)
			IDLE: begin
				dflit_to_send0     <= {source, ddestination, dsub_flow, dflit_type0, dflit_vc, dflit_payload0};
				dv_send_flit0      <= cache2net_dValid;
				dflit_to_send1     <= last_dreq_write? 0 : 
									 {source, ddestination, dsub_flow, dflit_type1, dflit_vc, cache2net_dData};
				dv_send_flit1      <= last_dreq_write? 0 : cache2net_dValid;	
				dState             <= cache2net_dValid? SEND : IDLE;
			end
		
		SEND: begin
			if((send_turn == 1) & (ready)) begin
				dflit_to_send0  <= 0; 
				dv_send_flit0   <= 0; 
				dState          <=  dv_send_flit1? SEND2: DONE;
			end
		end
		
		SEND2: begin
			if((send_turn == 1) & (ready)) begin
				dflit_to_send1  <= 0; 
				dv_send_flit1   <= 0; 	
				dState          <= DONE;
			end 
		end
		
		DONE: begin
				dState        <=  IDLE;
		end
		
		default: dState <= IDLE;
		endcase   
	end
 end


always @ (posedge clock) begin 
	if(reset == 1) begin 
		t_net2cache_iRead   <= 0; 
		t_net2cache_iWrite  <= 0; 
		t_net2cache_iAddr   <= 0; 
		t_net2cache_iData   <= 0;
		
		t_net2cache_dRead   <= 0; 
		t_net2cache_dWrite  <= 0; 
		t_net2cache_dAddr   <= 0; 
		t_net2cache_dData   <= 0;
		
		t_cache2net_iReady  <= 0; 
		t_cache2net_dReady  <= 0; 
	end 
	else begin 
		t_net2cache_iRead   <= iClear? 0 : i_read_req? 1   : t_net2cache_iRead; 
		t_net2cache_iWrite  <= iClear? 0 : i_write_req1? 1 : t_net2cache_iWrite; 
		t_net2cache_iAddr   <= iClear? 0 : (i_read_req | i_write_req0)? 
		                       flit_received : t_net2cache_iAddr;
		t_net2cache_iData   <= iClear? 0 : (i_read_req | i_write_req0)? 
		                       0 : i_write_req1? flit_received : t_net2cache_iData;
		
		t_net2cache_dRead   <= dClear? 0 : d_read_req? 1   : t_net2cache_dRead; 
		t_net2cache_dWrite  <= dClear? 0 : d_write_req1? 1 : t_net2cache_dWrite;  
		t_net2cache_dAddr   <= dClear? 0 : (d_read_req | d_write_req0)? 
		                      flit_received : t_net2cache_dAddr;
		t_net2cache_dData   <= dClear? 0 : (d_read_req | d_write_req0)?
		                       0 : d_write_req1? flit_received : t_net2cache_dData;
							   
		t_cache2net_iReady  <= cache2net_iReady; 
		t_cache2net_dReady  <= cache2net_dReady; 
	end
end
				   

always @ (posedge clock) begin  
	if(reset == 1) begin 
		send_turn        <= 0;

		i_requester      <= 0;
		last_ireq_write  <= 0;
		
		d_requester      <= 0;
		last_dreq_write  <= 0;

		flit_to_send     <= 0; 
		v_send_flit      <= 0; 
	end 
	else begin 

		send_turn        <= ((iState == IDLE) & cache2net_iValid)? 0 : 
							((dState == IDLE) & cache2net_dValid)? 1 : 
							((iState == DONE) | (dState == DONE))? (~send_turn) : send_turn;
		
		i_requester      <= (i_read_req | i_write_req1)? rec_source : cache2net_iValid? 0 : i_requester;
		last_ireq_write  <= i_write_req1? 1 : cache2net_iValid? 0 : last_ireq_write;
		
		d_requester      <= (d_read_req | d_write_req1)? rec_source : cache2net_dValid? 0 : d_requester;
		last_dreq_write  <= d_write_req1? 1 : cache2net_dValid? 0 : last_dreq_write;
		
		flit_to_send     <= (ready & (iState == SEND) & (send_turn == 0))?  iflit_to_send0 : 
							(ready & (iState == SEND2) & (send_turn == 0))? iflit_to_send1 : 
							(ready & (dState == SEND) & (send_turn == 1))?  dflit_to_send0 : 
							(ready & (dState == SEND2) & (send_turn == 1))? dflit_to_send1 : 0; 
						 
		v_send_flit      <= (ready & (iState == SEND) & (send_turn == 0))?  iv_send_flit0  :
							(ready & (iState == SEND2) & (send_turn == 0))? iv_send_flit1 : 
							(ready & (dState == SEND) & (send_turn == 1))?  dv_send_flit0 : 
							(ready & (dState == SEND2) & (send_turn == 1))? dv_send_flit1 : 0;
	end
end


endmodule