data/full_repos/permissive/411457613/Pyverilog/verilogcode/led_main.v
1: b'%Error: data/full_repos/permissive/411457613/Pyverilog/verilogcode/led_main.v:2: Cannot find include file: led.v\n`include "led.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/411457613/Pyverilog/verilogcode,data/full_repos/permissive/411457613/led.v\n             data/full_repos/permissive/411457613/Pyverilog/verilogcode,data/full_repos/permissive/411457613/led.v.v\n             data/full_repos/permissive/411457613/Pyverilog/verilogcode,data/full_repos/permissive/411457613/led.v.sv\n             led.v\n             led.v.v\n             led.v.sv\n             obj_dir/led.v\n             obj_dir/led.v.v\n             obj_dir/led.v.sv\n%Error: data/full_repos/permissive/411457613/Pyverilog/verilogcode/led_main.v:13: Define or directive not defined: \'`STEP\'\n     .STEP(`STEP)\n           ^~~~~\n%Error: Exiting due to 2 error(s)\n'
module main
(
 input CLK,
 input RST,
 output [7:0] LED
 );
  
  led #
    (
     .STEP(`STEP)
     )
  inst_led
    (
     .CLK(CLK),
     .RST(RST),
     .LED(LED)
     );
  
endmodule
module main
(
 input CLK,
 input RST,
 output [7:0] LED
 );

  
  led #
    (
     .STEP(`STEP)
     )
  inst_led
    (
     .CLK(CLK),
     .RST(RST),
     .LED(LED)
     );
  
endmodule