data/full_repos/permissive/441359809/src/yosys/techlibs/nexus/lutrams_map.v
1: b"%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/nexus/lutrams_map.v:23: Cannot find file containing module: 'DPR16X4'\n DPR16X4 #(\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/441359809/src/yosys/techlibs/nexus,data/full_repos/permissive/441359809/DPR16X4\n             data/full_repos/permissive/441359809/src/yosys/techlibs/nexus,data/full_repos/permissive/441359809/DPR16X4.v\n             data/full_repos/permissive/441359809/src/yosys/techlibs/nexus,data/full_repos/permissive/441359809/DPR16X4.sv\n             DPR16X4\n             DPR16X4.v\n             DPR16X4.sv\n             obj_dir/DPR16X4\n             obj_dir/DPR16X4.v\n             obj_dir/DPR16X4.sv\n%Error: Exiting due to 1 error(s)\n"
module \$__NEXUS_DPR16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
	parameter [63:0] INIT = 64'b0;
	parameter CLKPOL2 = 1;
	input CLK1;

	input [3:0] A1ADDR;
	output [3:0] A1DATA;

	input [3:0] B1ADDR;
	input [3:0] B1DATA;
	input B1EN;


	wire wck;

	generate
		if (CLKPOL2)
			assign wck = CLK1;
		else
			INV wck_inv_i (.A(CLK1), .Z(wck));
	endgenerate

	DPR16X4 #(
		.INITVAL($sformatf("0x%08x", INIT))
	) _TECHMAP_REPLACE_ (
		.RAD(A1ADDR),
		.DO(A1DATA),

		.WAD(B1ADDR),
		.DI(B1DATA),
		.WCK(CLK1),
		.WRE(B1EN)
	);
endmodule
module \$__NEXUS_DPR16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);

	parameter [63:0] INIT = 64'b0;
	parameter CLKPOL2 = 1;
	input CLK1;

	input [3:0] A1ADDR;
	output [3:0] A1DATA;

	input [3:0] B1ADDR;
	input [3:0] B1DATA;
	input B1EN;


	wire wck;

	generate
		if (CLKPOL2)
			assign wck = CLK1;
		else
			INV wck_inv_i (.A(CLK1), .Z(wck));
	endgenerate

	DPR16X4 #(
		.INITVAL($sformatf("0x%08x", INIT))
	) _TECHMAP_REPLACE_ (
		.RAD(A1ADDR),
		.DO(A1DATA),

		.WAD(B1ADDR),
		.DI(B1DATA),
		.WCK(CLK1),
		.WRE(B1EN)
	);
endmodule