data/full_repos/permissive/525452387/perips/ram.v
1: b'%Warning-WIDTH: data/full_repos/permissive/525452387/perips/ram.v:16: Bit extraction of array[4095:0] requires 12 bit index, not 30 bits.\n                                                                    : ... In instance ram\n        data[addr_i[31:2]] <= data_i;\n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/525452387/perips/ram.v:24: Bit extraction of array[4095:0] requires 12 bit index, not 30 bits.\n                                                                    : ... In instance ram\n        data_o = data[addr_i[31:2]];\n                     ^\n%Error: Exiting due to 2 warning(s)\n'
module ram(
    input wire clk,
    input wire rst_,

    input wire we_i,
    input wire[31:0] addr_i,
    input wire[31:0] data_i,

    output reg[31:0] data_o
);

reg[31:0] data[0:4096-1];

always @ (posedge clk) begin
    if (we_i == 1'b1) begin
        data[addr_i[31:2]] <= data_i;
    end
end

always @ (*) begin
    if (rst_ == 1'b0) begin
        data_o = 32'b0;
    end else begin
        data_o = data[addr_i[31:2]];
    end
end

endmodule
module ram(
    input wire clk,
    input wire rst_,

    input wire we_i,
    input wire[31:0] addr_i,
    input wire[31:0] data_i,

    output reg[31:0] data_o
);


reg[31:0] data[0:4096-1];

always @ (posedge clk) begin
    if (we_i == 1'b1) begin
        data[addr_i[31:2]] <= data_i;
    end
end

always @ (*) begin
    if (rst_ == 1'b0) begin
        data_o = 32'b0;
    end else begin
        data_o = data[addr_i[31:2]];
    end
end

endmodule