data/full_repos/permissive/493019833/test/testcase/firrtl/GCDTester/sbt/GCDTester.v
data/verilator_xmls/61b9487f-7dc9-4512-9bf9-3efdeb271db3.xml
module DecoupledGCD(
  input         clock,
  input         reset,
  output        io_in_ready,
  input         io_in_valid,
  input  [31:0] io_in_bits_a,
  input  [31:0] io_in_bits_b,
  input         io_out_ready,
  output        io_out_valid,
  output [31:0] io_out_bits
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif
  reg  busy;
  reg  done;
  reg [31:0] x;
  reg [31:0] y;
  wire  T_42 = y == 32'h0;
  wire  T_43 = busy & T_42;
  wire  T_45 = done & io_out_ready;
  wire  _GEN_1 = T_45 ? 1'h0 : busy;
  wire  start = io_in_valid & io_in_ready;
  wire  T_50 = x > y;
  wire [31:0] T_52 = x - y;
  wire  T_54 = ~T_50;
  wire [31:0] T_56 = y - x;
  assign io_in_ready = ~busy;
  assign io_out_valid = done;
  assign io_out_bits = x;
  always @(posedge clock) begin
    if (reset) begin
      busy <= 1'h0;
    end else begin
      busy <= start | _GEN_1;
    end
    if (reset) begin
      done <= 1'h0;
    end else if (start) begin
      done <= 1'h0;
    end else begin
      done <= T_43 | done;
    end
    if (start) begin
      x <= io_in_bits_a;
    end else if (T_50) begin
      x <= T_52;
    end
    if (start) begin
      y <= io_in_bits_b;
    end else if (T_54) begin
      y <= T_56;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  busy = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  done = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  x = _RAND_2[31:0];
  _RAND_3 = {1{`RANDOM}};
  y = _RAND_3[31:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module DecoupledGCD(
  input         clock,
  input         reset,
  output        io_in_ready,
  input         io_in_valid,
  input  [31:0] io_in_bits_a,
  input  [31:0] io_in_bits_b,
  input         io_out_ready,
  output        io_out_valid,
  output [31:0] io_out_bits
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif
  reg  busy;
  reg  done;
  reg [31:0] x;
  reg [31:0] y;
  wire  T_42 = y == 32'h0;
  wire  T_43 = busy & T_42;
  wire  T_45 = done & io_out_ready;
  wire  _GEN_1 = T_45 ? 1'h0 : busy;
  wire  start = io_in_valid & io_in_ready;
  wire  T_50 = x > y;
  wire [31:0] T_52 = x - y;
  wire  T_54 = ~T_50;
  wire [31:0] T_56 = y - x;
  assign io_in_ready = ~busy;
  assign io_out_valid = done;
  assign io_out_bits = x;
  always @(posedge clock) begin
    if (reset) begin
      busy <= 1'h0;
    end else begin
      busy <= start | _GEN_1;
    end
    if (reset) begin
      done <= 1'h0;
    end else if (start) begin
      done <= 1'h0;
    end else begin
      done <= T_43 | done;
    end
    if (start) begin
      x <= io_in_bits_a;
    end else if (T_50) begin
      x <= T_52;
    end
    if (start) begin
      y <= io_in_bits_b;
    end else if (T_54) begin
      y <= T_56;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  busy = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  done = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  x = _RAND_2[31:0];
  _RAND_3 = {1{`RANDOM}};
  y = _RAND_3[31:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule