data/full_repos/permissive/488660558/PUF/TIME.v
data/verilator_xmls/cf3c8ed4-b37a-4a2b-939d-73da784d081c.xml
module Time(clk,reset,CLK);
    input clk,reset;
    output reg CLK;
    reg [4:0]Count;
    
    always @(posedge clk or posedge reset)
    begin
        if (reset) begin
            Count<=5'd0;
            CLK<=1'b1; end
        else if(Count[4]==1'b1) begin
            Count<=5'd0;
            CLK<=~CLK; end
        else begin
            Count<=Count+5'd1; end
    end
endmodule
module Time(clk,reset,CLK);

    input clk,reset;
    output reg CLK;
    reg [4:0]Count;
    
    always @(posedge clk or posedge reset)
    begin
        if (reset) begin
            Count<=5'd0;
            CLK<=1'b1; end
        else if(Count[4]==1'b1) begin
            Count<=5'd0;
            CLK<=~CLK; end
        else begin
            Count<=Count+5'd1; end
    end
endmodule