data/full_repos/permissive/460468583/data/yosys/achronix/speedster22i/cells_sim.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/460468583/data/yosys/achronix/speedster22i/cells_sim.v:30: Multiple top level modules\n                                                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                       : ... Top module \'PADIN\'\nmodule PADIN (output padout, input padin);\n       ^~~~~\n                                                                                                       : ... Top module \'PADOUT\'\nmodule PADOUT (output padout, input padin, input oe);\n       ^~~~~~\n                                                                                                       : ... Top module \'LUT4\'\nmodule LUT4 (output dout,\n       ^~~~\n                                                                                                       : ... Top module \'DFF\'\nmodule DFF (output q,\n       ^~~\n%Error: data/full_repos/permissive/460468583/data/yosys/achronix/speedster22i/cells_sim.v:73: Duplicate declaration of signal: \'q\'\n                                                                                            : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n   reg             q;\n                   ^\n        data/full_repos/permissive/460468583/data/yosys/achronix/speedster22i/cells_sim.v:71: ... Location of original declaration\nmodule DFF (output q,\n                   ^\n%Error-ASSIGNIN: data/full_repos/permissive/460468583/data/yosys/achronix/speedster22i/cells_sim.v:32: Assigning to input/const variable: \'oe\'\n   assign oe = oe;\n          ^~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module DFF (output q,
            input  d, ck);
   reg             q;
   always @(posedge ck)
     q <= d;

endmodule
module DFF (output q,
            input  d, ck);

   reg             q;
   always @(posedge ck)
     q <= d;

endmodule