data/full_repos/permissive/463481430/RTL/core/rib.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/463481430/RTL/core/rib.v:155: Multiple top level modules\n                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                          : ... Top module \'SLAVE_SEL\'\nmodule SLAVE_SEL #(\n       ^~~~~~~~~\n                                                                          : ... Top module \'MASTER_SEL\'\nmodule MASTER_SEL #(\n       ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/463481430/RTL/core/rib.v:267: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'onehot2int\' generates 32 bits.\n                                                                       : ... In instance MASTER_SEL\n                sel_tag_id <= onehot2int(sel_tag);\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/463481430/RTL/core/rib.v:281: Bit extraction of var[2:0] requires 2 bit index, not 3 bits.\n                                                                       : ... In instance MASTER_SEL\n    assign o_ribs_rdy = i_ribm_rdy[sel_tag_id];\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/463481430/RTL/core/rib.v:130: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'onehot2int\' generates 32 bits.\n                                                                       : ... In instance SLAVE_SEL\n                sel_tag_id <= onehot2int(sel_tag);\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/463481430/RTL/core/rib.v:146: Bit extraction of array[2:0] requires 2 bit index, not 8 bits.\n                                                                       : ... In instance SLAVE_SEL\n    assign o_ribm_rdata = default_cs ? i_ribd_rdata : ribs_rdata[sel_tag_id];\n                                                                ^\n%Error: Exiting due to 5 warning(s)\n'
module MASTER_SEL #(
    parameter masters = 3
)(
    input wire i_clk,
    input wire i_rstn,

    input wire[32*masters-1:0]  i_ribm_addr,
    input wire[masters-1:0]     i_ribm_wrcs,
    input wire[4*masters-1:0]   i_ribm_mask,
    input wire[32*masters-1:0]  i_ribm_wdata,
    output wire[32*masters-1:0] o_ribm_rdata,
    input wire[masters-1:0]     i_ribm_req,
    output wire[masters-1:0]    o_ribm_gnt,
    output wire[masters-1:0]    o_ribm_rsp,
    input wire[masters-1:0]     i_ribm_rdy,



    output wire[31:0]           o_ribs_addr,
    output wire                 o_ribs_wrcs,
    output wire[3:0]            o_ribs_mask,
    output wire[31:0]           o_ribs_wdata,
    input wire[31:0]            i_ribs_rdata,
    output wire                 o_ribs_req, 
    input wire                  i_ribs_gnt, 
    input wire                  i_ribs_rsp, 
    output wire                 o_ribs_rdy
);



    function integer onehot2int;
        input[masters-1:0] onehot;
        integer j;
        begin
            onehot2int = 0;
            for(j=0;j<masters;j=j+1)begin
                if(onehot[j])begin
                    onehot2int = j;
                end
            end
        end
    endfunction
    



    wire[31:0] ribm_addr[masters-1:0];
    wire[3:0] ribm_mask[masters-1:0];
    wire[31:0] ribm_wdata[masters-1:0];
    generate
        genvar i0;
        for(i0=0;i0<masters;i0=i0+1)begin:gen_ribm_addr
            assign ribm_addr[i0] = i_ribm_addr[32*i0+31:32*i0];
            assign ribm_mask[i0] = i_ribm_mask[4*i0+3:4*i0];
            assign ribm_wdata[i0] = i_ribm_wdata[32*i0+31:32*i0];
        end
    endgenerate



    wire[masters-1:0] sel_tag;
    generate
        genvar i;
        for(i=0;i<masters;i=i+1)begin:addr_sel
            if(i==0)begin
                assign sel_tag[0] = ~(|i_ribm_req[masters-1:1]);
            end
            else if(i == masters-1)begin
                assign sel_tag[i] = i_ribm_req[i];
            end
            else begin
                assign sel_tag[i] = i_ribm_req[i] & ~(|i_ribm_req[masters-1:i+1]);
            end


            assign o_ribm_gnt[i] = sel_tag[i] & i_ribs_gnt;

            assign o_ribm_rdata[32*i+31:32*i] = i_ribs_rdata;
        end
    endgenerate


    assign o_ribs_addr = ribm_addr[onehot2int(sel_tag)];

    assign o_ribs_wrcs = i_ribm_wrcs[onehot2int(sel_tag)];

    assign o_ribs_mask = ribm_mask[onehot2int(sel_tag)];

    assign o_ribs_wdata = ribm_wdata[onehot2int(sel_tag)];

    assign o_ribs_req = |i_ribm_req;





    reg[$clog2(masters):0] sel_tag_id;
    wire handshake_rdy = o_ribs_req & i_ribs_gnt;

    wire access_rdy = i_ribs_rsp;
    reg handshake_rdy_last;

    wire trans_finish = handshake_rdy_last & access_rdy;
    always @(posedge i_clk or negedge i_rstn) begin
        if(~i_rstn)begin
            handshake_rdy_last <= 0;
        end
        else begin

            if(access_rdy | (~handshake_rdy_last))begin
                handshake_rdy_last <= handshake_rdy;
                sel_tag_id <= onehot2int(sel_tag);
            end
        end
    end


    generate
        genvar j;
        for(j=0;j<masters;j=j+1)begin:data_sel
            assign o_ribm_rsp[j] = (j==sel_tag_id) & i_ribs_rsp;
        end
    endgenerate


    assign o_ribs_rdy = i_ribm_rdy[sel_tag_id];
    
endmodule
module MASTER_SEL #(
    parameter masters = 3
)(
    input wire i_clk,
    input wire i_rstn,

    input wire[32*masters-1:0]  i_ribm_addr,
    input wire[masters-1:0]     i_ribm_wrcs,
    input wire[4*masters-1:0]   i_ribm_mask,
    input wire[32*masters-1:0]  i_ribm_wdata,
    output wire[32*masters-1:0] o_ribm_rdata,
    input wire[masters-1:0]     i_ribm_req,
    output wire[masters-1:0]    o_ribm_gnt,
    output wire[masters-1:0]    o_ribm_rsp,
    input wire[masters-1:0]     i_ribm_rdy,



    output wire[31:0]           o_ribs_addr,
    output wire                 o_ribs_wrcs,
    output wire[3:0]            o_ribs_mask,
    output wire[31:0]           o_ribs_wdata,
    input wire[31:0]            i_ribs_rdata,
    output wire                 o_ribs_req, 
    input wire                  i_ribs_gnt, 
    input wire                  i_ribs_rsp, 
    output wire                 o_ribs_rdy
);




    function integer onehot2int;
        input[masters-1:0] onehot;
        integer j;
        begin
            onehot2int = 0;
            for(j=0;j<masters;j=j+1)begin
                if(onehot[j])begin
                    onehot2int = j;
                end
            end
        end
    endfunction
    



    wire[31:0] ribm_addr[masters-1:0];
    wire[3:0] ribm_mask[masters-1:0];
    wire[31:0] ribm_wdata[masters-1:0];
    generate
        genvar i0;
        for(i0=0;i0<masters;i0=i0+1)begin:gen_ribm_addr
            assign ribm_addr[i0] = i_ribm_addr[32*i0+31:32*i0];
            assign ribm_mask[i0] = i_ribm_mask[4*i0+3:4*i0];
            assign ribm_wdata[i0] = i_ribm_wdata[32*i0+31:32*i0];
        end
    endgenerate



    wire[masters-1:0] sel_tag;
    generate
        genvar i;
        for(i=0;i<masters;i=i+1)begin:addr_sel
            if(i==0)begin
                assign sel_tag[0] = ~(|i_ribm_req[masters-1:1]);
            end
            else if(i == masters-1)begin
                assign sel_tag[i] = i_ribm_req[i];
            end
            else begin
                assign sel_tag[i] = i_ribm_req[i] & ~(|i_ribm_req[masters-1:i+1]);
            end


            assign o_ribm_gnt[i] = sel_tag[i] & i_ribs_gnt;

            assign o_ribm_rdata[32*i+31:32*i] = i_ribs_rdata;
        end
    endgenerate


    assign o_ribs_addr = ribm_addr[onehot2int(sel_tag)];

    assign o_ribs_wrcs = i_ribm_wrcs[onehot2int(sel_tag)];

    assign o_ribs_mask = ribm_mask[onehot2int(sel_tag)];

    assign o_ribs_wdata = ribm_wdata[onehot2int(sel_tag)];

    assign o_ribs_req = |i_ribm_req;





    reg[$clog2(masters):0] sel_tag_id;
    wire handshake_rdy = o_ribs_req & i_ribs_gnt;

    wire access_rdy = i_ribs_rsp;
    reg handshake_rdy_last;

    wire trans_finish = handshake_rdy_last & access_rdy;
    always @(posedge i_clk or negedge i_rstn) begin
        if(~i_rstn)begin
            handshake_rdy_last <= 0;
        end
        else begin

            if(access_rdy | (~handshake_rdy_last))begin
                handshake_rdy_last <= handshake_rdy;
                sel_tag_id <= onehot2int(sel_tag);
            end
        end
    end


    generate
        genvar j;
        for(j=0;j<masters;j=j+1)begin:data_sel
            assign o_ribm_rsp[j] = (j==sel_tag_id) & i_ribs_rsp;
        end
    endgenerate


    assign o_ribs_rdy = i_ribm_rdy[sel_tag_id];
    
endmodule