data/full_repos/permissive/417288846/List_1/Task_1/JK_latch.v
data/verilator_xmls/b67a8e9c-17d2-48b4-a686-700d01dd3610.xml
module mux_4(input i1, i2, i3, i4, s1, s2, output out);
   wire m1, m2, m3, m4;
   wire a1, a2, a3, a4;
   dec_24 dec1(.s1(s1), .s2(s2), .o1(m1), .o2(m2), .o3(m3), .o4(m4));
   and (a1, m1, i1);
   and (a2, m2, i2);
   and (a3, m3, i3);
   and (a4, m4, i4);
   or  (out, a1, a2, a3, a4);
endmodule
module mux_4(input i1, i2, i3, i4, s1, s2, output out);

   wire m1, m2, m3, m4;
   wire a1, a2, a3, a4;
   dec_24 dec1(.s1(s1), .s2(s2), .o1(m1), .o2(m2), .o3(m3), .o4(m4));
   and (a1, m1, i1);
   and (a2, m2, i2);
   and (a3, m3, i3);
   and (a4, m4, i4);
   or  (out, a1, a2, a3, a4);
endmodule