data/full_repos/permissive/503973366/SIM/ACC_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/ACC_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n            #(10/2) clk = ~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/ACC_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n        #(3)\n        ^\n%Error: data/full_repos/permissive/503973366/SIM/ACC_tb.v:79: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/ACC_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n        #(3)\n        ^\n%Error: data/full_repos/permissive/503973366/SIM/ACC_tb.v:86: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/ACC_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n        #(3)\n        ^\n%Error: data/full_repos/permissive/503973366/SIM/ACC_tb.v:90: Too many digits for 32 bit number: \'h00000001_00000002_00000003_00000004\n        psum_row_i = \'h00000001_00000002_00000003_00000004;\n                     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/503973366/SIM/ACC_tb.v:93: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/ACC_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n        #(3)\n        ^\n%Error: data/full_repos/permissive/503973366/SIM/ACC_tb.v:97: Too many digits for 32 bit number: \'h00000002_00000003_00000004_00000005\n        psum_row_i = \'h00000002_00000003_00000004_00000005;\n                     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/503973366/SIM/ACC_tb.v:100: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/ACC_tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n        #(3)\n        ^\n%Error: data/full_repos/permissive/503973366/SIM/ACC_tb.v:104: Too many digits for 32 bit number: \'h00000003_00000004_00000005_00000006\n        psum_row_i = \'h00000003_00000004_00000005_00000006;\n                     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/503973366/SIM/ACC_tb.v:107: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/ACC_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n        #(3)\n        ^\n%Error: data/full_repos/permissive/503973366/SIM/ACC_tb.v:111: Too many digits for 32 bit number: \'h00000004_00000005_00000006_00000007\n        psum_row_i = \'h00000004_00000005_00000006_00000007;\n                     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/503973366/SIM/ACC_tb.v:115: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/ACC_tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n            #(3)\n            ^\n%Error: data/full_repos/permissive/503973366/SIM/ACC_tb.v:119: Too many digits for 32 bit number: \'h00000010_00000010_00000010_00000010\n            psum_row_i = \'h00000010_00000010_00000010_00000010;\n                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/503973366/SIM/ACC_tb.v:120: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/ACC_tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n            #(3)\n            ^\n%Error: data/full_repos/permissive/503973366/SIM/ACC_tb.v:124: Too many digits for 32 bit number: \'h00000100_00000100_00000100_00000100\n            psum_row_i = \'h00000100_00000100_00000100_00000100;\n                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/503973366/SIM/ACC_tb.v:125: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/ACC_tb.v:127: Unsupported: Ignoring delay on this delayed statement.\n            #(3)\n            ^\n%Error: data/full_repos/permissive/503973366/SIM/ACC_tb.v:129: Too many digits for 32 bit number: \'h00001000_00001000_00001000_00001000\n            psum_row_i = \'h00001000_00001000_00001000_00001000;\n                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/503973366/SIM/ACC_tb.v:130: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/ACC_tb.v:132: Unsupported: Ignoring delay on this delayed statement.\n            #(3)\n            ^\n%Error: data/full_repos/permissive/503973366/SIM/ACC_tb.v:134: Too many digits for 32 bit number: \'h00010000_00010000_00010000_00010000\n            psum_row_i = \'h00010000_00010000_00010000_00010000;\n                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/503973366/SIM/ACC_tb.v:139: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/ACC_tb.v:140: Unsupported: Ignoring delay on this delayed statement.\n            #(3)\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/ACC_tb.v:143: Unsupported: Ignoring delay on this delayed statement.\n            #(3)\n            ^\n%Error: data/full_repos/permissive/503973366/SIM/ACC_tb.v:149: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/ACC_tb.v:151: Unsupported: Ignoring delay on this delayed statement.\n            #(3)\n            ^\n%Error: Exiting due to 19 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ACC_TB #(

    parameter PE_SIZE       = 4,
    parameter DATA_WIDTH    = 32,
    parameter FIFO_DEPTH    = 4
    )
    (


    );
    

    reg     clk;
    reg     rst_n;
    

    reg     [PE_SIZE-1:0]   psum_en_i;
    reg     [PE_SIZE-1:0]   rden_i;
    

    reg     [DATA_WIDTH*PE_SIZE-1:0]    psum_row_i;
    wire    [DATA_WIDTH*PE_SIZE-1:0]    psum_row_o;
    
    
    
    
    ACC #(
        .PE_SIZE    ( 4 ),
        .DATA_WIDTH ( 32 ),
        .FIFO_DEPTH ( 4 )
    ) ACC_INST (
        .clk        ( clk        ),
        .rst_n      ( rst_n      ),
        .psum_en_i  ( psum_en_i  ),
        .rden_i     ( rden_i     ),
        .psum_row_i ( psum_row_i ),
        .psum_row_o ( psum_row_o )
    );


    initial begin
        clk = 1'b0;
        forever begin
            #(`CLOCK_PERIOD/2) clk = ~clk;
        end
    end
    
    integer cycle;


    initial begin
        cycle = 0;
        rst_n = 1'b1;
        psum_en_i = {(PE_SIZE){1'b0}};
        rden_i = {(PE_SIZE){1'b0}};
        psum_row_i = {(DATA_WIDTH*PE_SIZE){1'b0}};
    end



    



    initial begin

        #(`DELTA)
        rst_n = 1'b0;
        @(posedge clk);
        cycle = cycle + 1;
        #(`DELTA)
        rst_n = 1'b1;
        


        @(posedge clk);
        cycle = cycle + 1;
        #(`DELTA)
        psum_en_i = 4'b1111;
        psum_row_i = 'h00000001_00000002_00000003_00000004;
        

        @(posedge clk);
        cycle = cycle + 1;
        #(`DELTA)
        psum_en_i = 4'b1111;
        psum_row_i = 'h00000002_00000003_00000004_00000005;
        

        @(posedge clk);
        cycle = cycle + 1;
        #(`DELTA)
        psum_en_i = 4'b1111;
        psum_row_i = 'h00000003_00000004_00000005_00000006;
        

        @(posedge clk);
        cycle = cycle + 1;
        #(`DELTA)
        psum_en_i = 4'b1111;
        psum_row_i = 'h00000004_00000005_00000006_00000007;
        

        repeat (3) begin
            @(posedge clk);
            cycle = cycle + 1;
            #(`DELTA)
            psum_en_i = 4'b1111;
            psum_row_i = 'h00000010_00000010_00000010_00000010;
            @(posedge clk);
            cycle = cycle + 1;
            #(`DELTA)
            psum_en_i = 4'b1111;
            psum_row_i = 'h00000100_00000100_00000100_00000100;
            @(posedge clk);
            cycle = cycle + 1;
            #(`DELTA)
            psum_en_i = 4'b1111;
            psum_row_i = 'h00001000_00001000_00001000_00001000;
            @(posedge clk);
            cycle = cycle + 1;
            #(`DELTA)
            psum_en_i = 4'b1111;
            psum_row_i = 'h00010000_00010000_00010000_00010000;
        end
        

        repeat (4) begin
            @(posedge clk);
            #(`DELTA)
            psum_en_i = 4'b0000;
            cycle = cycle + 1;
            #(`DELTA)
            rden_i = 4'b1111;
        end
        

        repeat (4) begin
            @(posedge clk);
            psum_en_i = 4'b0000;
            #(`DELTA)
            rden_i = 4'b0000;
            cycle = cycle + 1;
        end
    
    end


endmodule
module ACC_TB #(

    parameter PE_SIZE       = 4,
    parameter DATA_WIDTH    = 32,
    parameter FIFO_DEPTH    = 4
    )
    (


    );

    

    reg     clk;
    reg     rst_n;
    

    reg     [PE_SIZE-1:0]   psum_en_i;
    reg     [PE_SIZE-1:0]   rden_i;
    

    reg     [DATA_WIDTH*PE_SIZE-1:0]    psum_row_i;
    wire    [DATA_WIDTH*PE_SIZE-1:0]    psum_row_o;
    
    
    
    
    ACC #(
        .PE_SIZE    ( 4 ),
        .DATA_WIDTH ( 32 ),
        .FIFO_DEPTH ( 4 )
    ) ACC_INST (
        .clk        ( clk        ),
        .rst_n      ( rst_n      ),
        .psum_en_i  ( psum_en_i  ),
        .rden_i     ( rden_i     ),
        .psum_row_i ( psum_row_i ),
        .psum_row_o ( psum_row_o )
    );


    initial begin
        clk = 1'b0;
        forever begin
            #(`CLOCK_PERIOD/2) clk = ~clk;
        end
    end
    
    integer cycle;


    initial begin
        cycle = 0;
        rst_n = 1'b1;
        psum_en_i = {(PE_SIZE){1'b0}};
        rden_i = {(PE_SIZE){1'b0}};
        psum_row_i = {(DATA_WIDTH*PE_SIZE){1'b0}};
    end



    



    initial begin

        #(`DELTA)
        rst_n = 1'b0;
        @(posedge clk);
        cycle = cycle + 1;
        #(`DELTA)
        rst_n = 1'b1;
        


        @(posedge clk);
        cycle = cycle + 1;
        #(`DELTA)
        psum_en_i = 4'b1111;
        psum_row_i = 'h00000001_00000002_00000003_00000004;
        

        @(posedge clk);
        cycle = cycle + 1;
        #(`DELTA)
        psum_en_i = 4'b1111;
        psum_row_i = 'h00000002_00000003_00000004_00000005;
        

        @(posedge clk);
        cycle = cycle + 1;
        #(`DELTA)
        psum_en_i = 4'b1111;
        psum_row_i = 'h00000003_00000004_00000005_00000006;
        

        @(posedge clk);
        cycle = cycle + 1;
        #(`DELTA)
        psum_en_i = 4'b1111;
        psum_row_i = 'h00000004_00000005_00000006_00000007;
        

        repeat (3) begin
            @(posedge clk);
            cycle = cycle + 1;
            #(`DELTA)
            psum_en_i = 4'b1111;
            psum_row_i = 'h00000010_00000010_00000010_00000010;
            @(posedge clk);
            cycle = cycle + 1;
            #(`DELTA)
            psum_en_i = 4'b1111;
            psum_row_i = 'h00000100_00000100_00000100_00000100;
            @(posedge clk);
            cycle = cycle + 1;
            #(`DELTA)
            psum_en_i = 4'b1111;
            psum_row_i = 'h00001000_00001000_00001000_00001000;
            @(posedge clk);
            cycle = cycle + 1;
            #(`DELTA)
            psum_en_i = 4'b1111;
            psum_row_i = 'h00010000_00010000_00010000_00010000;
        end
        

        repeat (4) begin
            @(posedge clk);
            #(`DELTA)
            psum_en_i = 4'b0000;
            cycle = cycle + 1;
            #(`DELTA)
            rden_i = 4'b1111;
        end
        

        repeat (4) begin
            @(posedge clk);
            psum_en_i = 4'b0000;
            #(`DELTA)
            rden_i = 4'b0000;
            cycle = cycle + 1;
        end
    
    end


endmodule