data/full_repos/permissive/439731184/example_case.v
1: b'%Error: data/full_repos/permissive/439731184/example_case.v:33: Unsupported or unknown PLI call: $urandom\n    r = $urandom;\n        ^~~~~~~~\n%Error: data/full_repos/permissive/439731184/example_case.v:43: Unsupported or unknown PLI call: $monitor\n    $monitor("%b\\t%b\\t%b\\t%b\\t%h\\t%b", a, b, c, d, sel, y);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/439731184/example_case.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #7 $finish;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/439731184/example_case.v:47: Unsupported: Ignoring delay on this delayed statement.\nalways #2 sel = sel + 1;\n       ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux(a, b, c, d, sel, y);

input a, b, c, d;
input [1:0] sel;
output y;

wire a, b, d, c;
wire [1:0] sel;
reg y;

always @ (a or b or c or d or sel)
case(sel)
    2'b00 : y = a;
    2'b01 : y = b;
    2'b10 : y = c;
    2'b11 : y = d;
    default : $display("Error in SEL");
endcase

endmodule
module mux(a, b, c, d, sel, y);


input a, b, c, d;
input [1:0] sel;
output y;

wire a, b, d, c;
wire [1:0] sel;
reg y;

always @ (a or b or c or d or sel)
case(sel)
    2'b00 : y = a;
    2'b01 : y = b;
    2'b10 : y = c;
    2'b11 : y = d;
    default : $display("Error in SEL");
endcase

endmodule