data/full_repos/permissive/43858668/final_verilog/src/clib/c_shift_reg.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_shift_reg.v:35: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_constants.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_constants.v.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_constants.v.sv\n             c_constants.v\n             c_constants.v.v\n             c_constants.v.sv\n             obj_dir/c_constants.v\n             obj_dir/c_constants.v.v\n             obj_dir/c_constants.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_shift_reg.v:43: Define or directive not defined: \'`RESET_TYPE_ASYNC\'\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_shift_reg.v:43: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                                           ^\n%Error: Exiting due to 3 error(s)\n'
module c_shift_reg
  (clk, reset, active, data_in, data_out);
   
`include "c_constants.v"
   

   parameter width = 32;
   

   parameter depth = 2;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   input clk;
   input reset;
   input active;
   

   input [0:width-1] data_in;
   

   output [0:width-1] data_out;
   wire [0:width-1] data_out;
   
   genvar 	    level;
   
   wire [0:(depth+1)*width-1] data;
   assign data[0:width-1] = data_in;
   
   generate
      
      for(level = 0; level < depth; level = level + 1)
	begin:levels
	   
	   wire [0:width-1] data_s, data_q;
	   assign data_s = data[level*width:(level+1)*width-1];
	   c_dff
	     #(.width(width),
	       .reset_type(reset_type))
	   dataq
	     (.clk(clk),
	      .reset(reset),
	      .active(active),
	      .d(data_s),
	      .q(data_q));
	   
	   assign data[(level+1)*width:(level+2)*width-1] = data_q;
	   
	end
      
   endgenerate
   
   assign data_out = data[depth*width:(depth+1)*width-1];
   
endmodule
module c_shift_reg
  (clk, reset, active, data_in, data_out);

   
`include "c_constants.v"
   

   parameter width = 32;
   

   parameter depth = 2;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   input clk;
   input reset;
   input active;
   

   input [0:width-1] data_in;
   

   output [0:width-1] data_out;
   wire [0:width-1] data_out;
   
   genvar 	    level;
   
   wire [0:(depth+1)*width-1] data;
   assign data[0:width-1] = data_in;
   
   generate
      
      for(level = 0; level < depth; level = level + 1)
	begin:levels
	   
	   wire [0:width-1] data_s, data_q;
	   assign data_s = data[level*width:(level+1)*width-1];
	   c_dff
	     #(.width(width),
	       .reset_type(reset_type))
	   dataq
	     (.clk(clk),
	      .reset(reset),
	      .active(active),
	      .d(data_s),
	      .q(data_q));
	   
	   assign data[(level+1)*width:(level+2)*width-1] = data_q;
	   
	end
      
   endgenerate
   
   assign data_out = data[depth*width:(depth+1)*width-1];
   
endmodule