data/full_repos/permissive/441359809/src/yosys/tests/arch/common/lutram.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/tests/arch/common/lutram.v:22: Multiple top level modules\n                                                                                               : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                               : ... Top module \'lutram_1w1r\'\nmodule lutram_1w1r\n       ^~~~~~~~~~~\n                                                                                               : ... Top module \'lutram_1w3r\'\nmodule lutram_1w3r\n       ^~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module lutram_1w1r
#(parameter D_WIDTH=8, A_WIDTH=6)
(
	input [D_WIDTH-1:0] data_a,
	input [A_WIDTH:1] addr_a,
	input we_a, clk,
	output reg [D_WIDTH-1:0] q_a
);

	reg [D_WIDTH-1:0] ram[(2**A_WIDTH)-1:0];


	always @ (posedge clk)
	begin
		if (we_a)
			ram[addr_a] <= data_a;
		q_a <= ram[addr_a];
	end
endmodule
module lutram_1w1r
#(parameter D_WIDTH=8, A_WIDTH=6)
(
	input [D_WIDTH-1:0] data_a,
	input [A_WIDTH:1] addr_a,
	input we_a, clk,
	output reg [D_WIDTH-1:0] q_a
);


	reg [D_WIDTH-1:0] ram[(2**A_WIDTH)-1:0];


	always @ (posedge clk)
	begin
		if (we_a)
			ram[addr_a] <= data_a;
		q_a <= ram[addr_a];
	end
endmodule