data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/stream_arbiter.sv
1: b'%Warning-LITENDIAN: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/stream_arbiter.sv:24: Little bit endian vector: MSB < LSB of bit range: -2:0\n    input  DATA_T [N_INP-1:0] inp_data_i,\n                  ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/stream_arbiter.sv:25: Little bit endian vector: MSB < LSB of bit range: -2:0\n    input  logic  [N_INP-1:0] inp_valid_i,\n                  ^\n%Warning-LITENDIAN: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/stream_arbiter.sv:26: Little bit endian vector: MSB < LSB of bit range: -2:0\n    output logic  [N_INP-1:0] inp_ready_o,\n                  ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/stream_arbiter.sv:33: Cannot find file containing module: \'stream_arbiter_flushable\'\n  stream_arbiter_flushable #(\n  ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src,data/full_repos/permissive/473423187/stream_arbiter_flushable\n             data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src,data/full_repos/permissive/473423187/stream_arbiter_flushable.v\n             data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src,data/full_repos/permissive/473423187/stream_arbiter_flushable.sv\n             stream_arbiter_flushable\n             stream_arbiter_flushable.v\n             stream_arbiter_flushable.sv\n             obj_dir/stream_arbiter_flushable\n             obj_dir/stream_arbiter_flushable.v\n             obj_dir/stream_arbiter_flushable.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module stream_arbiter #(
    parameter type      DATA_T = logic,
    parameter integer   N_INP = -1,
    parameter           ARBITER = "rr"
) (
    input  logic              clk_i,
    input  logic              rst_ni,

    input  DATA_T [N_INP-1:0] inp_data_i,
    input  logic  [N_INP-1:0] inp_valid_i,
    output logic  [N_INP-1:0] inp_ready_o,

    output DATA_T             oup_data_o,
    output logic              oup_valid_o,
    input  logic              oup_ready_i
);

  stream_arbiter_flushable #(
    .DATA_T   (DATA_T),
    .N_INP    (N_INP),
    .ARBITER  (ARBITER)
  ) i_arb (
    .clk_i        (clk_i),
    .rst_ni       (rst_ni),
    .flush_i      (1'b0),
    .inp_data_i   (inp_data_i),
    .inp_valid_i  (inp_valid_i),
    .inp_ready_o  (inp_ready_o),
    .oup_data_o   (oup_data_o),
    .oup_valid_o  (oup_valid_o),
    .oup_ready_i  (oup_ready_i)
  );

endmodule
module stream_arbiter #(
    parameter type      DATA_T = logic,
    parameter integer   N_INP = -1,
    parameter           ARBITER = "rr"
) (
    input  logic              clk_i,
    input  logic              rst_ni,

    input  DATA_T [N_INP-1:0] inp_data_i,
    input  logic  [N_INP-1:0] inp_valid_i,
    output logic  [N_INP-1:0] inp_ready_o,

    output DATA_T             oup_data_o,
    output logic              oup_valid_o,
    input  logic              oup_ready_i
);


  stream_arbiter_flushable #(
    .DATA_T   (DATA_T),
    .N_INP    (N_INP),
    .ARBITER  (ARBITER)
  ) i_arb (
    .clk_i        (clk_i),
    .rst_ni       (rst_ni),
    .flush_i      (1'b0),
    .inp_data_i   (inp_data_i),
    .inp_valid_i  (inp_valid_i),
    .inp_ready_o  (inp_ready_o),
    .oup_data_o   (oup_data_o),
    .oup_valid_o  (oup_valid_o),
    .oup_ready_i  (oup_ready_i)
  );

endmodule