data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/tb/PRNG_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/tb/PRNG_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #rng_clk_h_period;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/tb/PRNG_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #rng_clk_h_period;\n  ^\n%Error: data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/tb/PRNG_tb.v:39: Unsupported: $fopen with multichannel descriptor.  Add ,"w" as second argument to open a file descriptor.\n  write_data = $fopen("samp_generation.txt");\n               ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/tb/PRNG_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #rng_clk_h_period;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/tb/PRNG_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #rng_clk_h_period;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/tb/PRNG_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n   #rng_clk_h_period;\n   ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module PRNG_tb;

	localparam rng_samps = 1000000;
	localparam seed_width = 32;
	localparam out_width = 32;
	localparam rng_width = 14;

	localparam rng_clk_h_period = 5;




	reg rng_clk = 1'b0;
	reg rng_rst = 1'b0;

	reg [out_width - 1:0] SIGMA = 32'h0000_3A2E;
	wire [out_width - 1:0] rng_out_0;
	wire [out_width - 1:0] rng_out_1;

	integer write_data;
	integer i;



	PRNG #(.FP_WIDTH(out_width), .RNG_WIDTH(rng_width)) PRNG_0(.SIGMA(SIGMA), .clk(rng_clk), .rst(rng_rst), .PERT_A(rng_out_0), .PERT_B(rng_out_1));



	always
	begin
		rng_clk = 1'b0;
		#rng_clk_h_period;
		rng_clk = 1'b1;
		#rng_clk_h_period;
	end

	initial
	begin
		write_data = $fopen("samp_generation.txt");
		rng_rst = 1'b1;
		#rng_clk_h_period;
		rng_rst = 1'b0;
		#rng_clk_h_period;
		
		repeat(rng_samps)
		begin
			#rng_clk_h_period;
			$fdisplay(write_data, "%x, %x", rng_out_0, rng_out_1);

		end
		$fclose(write_data);
		$finish;
	end
endmodule
module PRNG_tb;


	localparam rng_samps = 1000000;
	localparam seed_width = 32;
	localparam out_width = 32;
	localparam rng_width = 14;

	localparam rng_clk_h_period = 5;




	reg rng_clk = 1'b0;
	reg rng_rst = 1'b0;

	reg [out_width - 1:0] SIGMA = 32'h0000_3A2E;
	wire [out_width - 1:0] rng_out_0;
	wire [out_width - 1:0] rng_out_1;

	integer write_data;
	integer i;



	PRNG #(.FP_WIDTH(out_width), .RNG_WIDTH(rng_width)) PRNG_0(.SIGMA(SIGMA), .clk(rng_clk), .rst(rng_rst), .PERT_A(rng_out_0), .PERT_B(rng_out_1));



	always
	begin
		rng_clk = 1'b0;
		#rng_clk_h_period;
		rng_clk = 1'b1;
		#rng_clk_h_period;
	end

	initial
	begin
		write_data = $fopen("samp_generation.txt");
		rng_rst = 1'b1;
		#rng_clk_h_period;
		rng_rst = 1'b0;
		#rng_clk_h_period;
		
		repeat(rng_samps)
		begin
			#rng_clk_h_period;
			$fdisplay(write_data, "%x, %x", rng_out_0, rng_out_1);

		end
		$fclose(write_data);
		$finish;
	end
endmodule