data/full_repos/permissive/44647742/new_counter.v
data/verilator_xmls/d534f27a-0b4c-4013-86d9-a9ebf0ee2429.xml
module new_counter(
input rst_n,
input inc,
output [9:0]counter
    );

reg [9:0]counter_reg;

assign counter = counter_reg;

always@(posedge inc or negedge rst_n)
begin
	if(~rst_n)
		counter_reg<=10'b0000;
	else
		counter_reg <= counter_reg  + 1;
end

endmodule
module new_counter(
input rst_n,
input inc,
output [9:0]counter
    );


reg [9:0]counter_reg;

assign counter = counter_reg;

always@(posedge inc or negedge rst_n)
begin
	if(~rst_n)
		counter_reg<=10'b0000;
	else
		counter_reg <= counter_reg  + 1;
end

endmodule