data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_async_pad.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_async_pad.v:72: Cannot find file containing module: 'dram_async_edgelogic'\ndram_async_edgelogic async_edgelogic( \n^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/dram_async_edgelogic\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/dram_async_edgelogic.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/dram_async_edgelogic.sv\n             dram_async_edgelogic\n             dram_async_edgelogic.v\n             dram_async_edgelogic.sv\n             obj_dir/dram_async_edgelogic\n             obj_dir/dram_async_edgelogic.v\n             obj_dir/dram_async_edgelogic.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_async_pad.v:88: Cannot find file containing module: 'dram_sstl_pad'\ndram_sstl_pad sstl_pad( \n^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module dram_async_pad(

   bso, 

   pad, 

   vrefcode, vdd_h, update_dr, shift_dr, 
   mode_ctrl, hiz_n, data, clock_dr, cbu, cbd, bsi
   );






input			bsi;
input [8:1]		cbd;
input [8:1]		cbu;
input			clock_dr;
input			data;
input			hiz_n;
input			mode_ctrl;
input			shift_dr;
input			update_dr;
input			vdd_h;
input [7:0]		vrefcode;





inout			pad;






output			bso;







wire			to_pad;




dram_async_edgelogic async_edgelogic(

				 .to_pad(to_pad),

				 .data	(data));





dram_sstl_pad sstl_pad(

		       .bso		(bso),
		       .to_core		(),

		       .pad		(pad),

		       .bsi		(bsi),
		       .cbd		(cbd[8:1]),
		       .cbu		(cbu[8:1]),
		       .clock_dr	(clock_dr),
		       .data_in		(to_pad),
		       .hiz_n		(hiz_n),
		       .mode_ctrl	(mode_ctrl),
		       .odt_enable_mask	(1'b1),
		       .oe		(1'b1),
		       .shift_dr	(shift_dr),
		       .update_dr	(update_dr),
		       .vdd_h		(vdd_h),
		       .vrefcode	(vrefcode[7:0]));
endmodule
module dram_async_pad(

   bso, 

   pad, 

   vrefcode, vdd_h, update_dr, shift_dr, 
   mode_ctrl, hiz_n, data, clock_dr, cbu, cbd, bsi
   );







input			bsi;
input [8:1]		cbd;
input [8:1]		cbu;
input			clock_dr;
input			data;
input			hiz_n;
input			mode_ctrl;
input			shift_dr;
input			update_dr;
input			vdd_h;
input [7:0]		vrefcode;





inout			pad;






output			bso;







wire			to_pad;




dram_async_edgelogic async_edgelogic(

				 .to_pad(to_pad),

				 .data	(data));





dram_sstl_pad sstl_pad(

		       .bso		(bso),
		       .to_core		(),

		       .pad		(pad),

		       .bsi		(bsi),
		       .cbd		(cbd[8:1]),
		       .cbu		(cbu[8:1]),
		       .clock_dr	(clock_dr),
		       .data_in		(to_pad),
		       .hiz_n		(hiz_n),
		       .mode_ctrl	(mode_ctrl),
		       .odt_enable_mask	(1'b1),
		       .oe		(1'b1),
		       .shift_dr	(shift_dr),
		       .update_dr	(update_dr),
		       .vdd_h		(vdd_h),
		       .vrefcode	(vrefcode[7:0]));
endmodule