data/full_repos/permissive/459421171/Pipelined/pc_update_testbench.v
1: b'%Error: data/full_repos/permissive/459421171/Pipelined/pc_update_testbench.v:12: Unsupported or unknown PLI call: $monitor\n        $monitor ($time ," clk=%d,icode=%d,cnd=%d valC=%d valM=%d valP=%d PC_updated=%d",clk,icode,cnd,valC,valM,valP,PC_updated);\n        ^~~~~~~~\n%Error: data/full_repos/permissive/459421171/Pipelined/pc_update_testbench.v:13: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile ("pc_update_test1.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/459421171/Pipelined/pc_update_testbench.v:14: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars (0,pc_update_test);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/pc_update_testbench.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk=1;icode=4\'b1001;valP=12;valM=20;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/pc_update_testbench.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk=1;icode=4\'b1000;valP=15;valC=13;valM=25;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/pc_update_testbench.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk=1;icode=4\'b0111;valP=9;valC=6;valM=19;cnd=0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/pc_update_testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #5 cnd=1;\n        ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pc_update_test;
     pc_update DUT(.clk(clk),.icode(icode),.cnd(cnd),.valC(valC),.valM(valM),.valP(valP),.PC_updated(PC_updated));
reg clk;
reg [3:0] icode;
reg cnd;
reg [63:0] valC;
reg [63:0] valM;
reg [63:0] valP;
wire [63:0] PC_updated;
initial
        begin
        $monitor ($time ," clk=%d,icode=%d,cnd=%d valC=%d valM=%d valP=%d PC_updated=%d",clk,icode,cnd,valC,valM,valP,PC_updated);
        $dumpfile ("pc_update_test1.vcd");
        $dumpvars (0,pc_update_test);
        clk=1;icode=4'b0010;cnd=0;valP=10;
        #5 clk=1;icode=4'b1001;valP=12;valM=20;
        #5 clk=1;icode=4'b1000;valP=15;valC=13;valM=25;
        #5 clk=1;icode=4'b0111;valP=9;valC=6;valM=19;cnd=0;
        #5 cnd=1;
       end
endmodule
module pc_update_test;

     pc_update DUT(.clk(clk),.icode(icode),.cnd(cnd),.valC(valC),.valM(valM),.valP(valP),.PC_updated(PC_updated));
reg clk;
reg [3:0] icode;
reg cnd;
reg [63:0] valC;
reg [63:0] valM;
reg [63:0] valP;
wire [63:0] PC_updated;
initial
        begin
        $monitor ($time ," clk=%d,icode=%d,cnd=%d valC=%d valM=%d valP=%d PC_updated=%d",clk,icode,cnd,valC,valM,valP,PC_updated);
        $dumpfile ("pc_update_test1.vcd");
        $dumpvars (0,pc_update_test);
        clk=1;icode=4'b0010;cnd=0;valP=10;
        #5 clk=1;icode=4'b1001;valP=12;valM=20;
        #5 clk=1;icode=4'b1000;valP=15;valC=13;valM=25;
        #5 clk=1;icode=4'b0111;valP=9;valC=6;valM=19;cnd=0;
        #5 cnd=1;
       end
endmodule