data/full_repos/permissive/463555432/Codes/amsg_kirsch_nw.v
1: b'%Warning-WIDTH: data/full_repos/permissive/463555432/Codes/amsg_kirsch_nw.v:25: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'ys1\' generates 16 bits.\n                                                                              : ... In instance AMSG_kirsch_nw\n      y1 <= ys1;\n         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module AMSG_kirsch_nw(
  input [7:0] p1, p2, p3, p4, p6, p7, p8, p9,
  output reg [7:0] y1
    );
    wire [15:0] ys1;
    wire [8:0] n1, n2, n3, n4, n5, n6;
    wire [15:0] m1, m2;
    
    assign n1 = p1 + p4;
    assign n2 = p7 + p8;
    assign n3 = n1 + n2;
	assign n4 = n3 + p9;
	assign n5 = p2 + p3;
	assign n6 = n5 + p6;
	assign m1 = 5 * n6;
    assign m2 = 3 * n4;
    assign ys1 = m1 - m2;
    always@(ys1)
    begin
    if(ys1 > 255)
      y1 <= 255;
    else
      y1 <= ys1;
    end
endmodule
module AMSG_kirsch_nw(
  input [7:0] p1, p2, p3, p4, p6, p7, p8, p9,
  output reg [7:0] y1
    );

    wire [15:0] ys1;
    wire [8:0] n1, n2, n3, n4, n5, n6;
    wire [15:0] m1, m2;
    
    assign n1 = p1 + p4;
    assign n2 = p7 + p8;
    assign n3 = n1 + n2;
	assign n4 = n3 + p9;
	assign n5 = p2 + p3;
	assign n6 = n5 + p6;
	assign m1 = 5 * n6;
    assign m2 = 3 * n4;
    assign ys1 = m1 - m2;
    always@(ys1)
    begin
    if(ys1 > 255)
      y1 <= 255;
    else
      y1 <= ys1;
    end
endmodule