data/full_repos/permissive/431605717/Code/RV32IM/WB.v
data/verilator_xmls/3b468949-e548-415e-a43d-9e0e0f52a6b7.xml
module risc_v_32_wb(mem_out,alu_out,MemtoReg,data_2_rf);
    input      [31:0] mem_out;
	input      [31:0] alu_out;
	input 	          MemtoReg;
    output 	   [31:0] data_2_rf;

    wire   [31:0] data_2_rf = MemtoReg ? mem_out : alu_out;

	
endmodule
module risc_v_32_wb(mem_out,alu_out,MemtoReg,data_2_rf);

    input      [31:0] mem_out;
	input      [31:0] alu_out;
	input 	          MemtoReg;
    output 	   [31:0] data_2_rf;

    wire   [31:0] data_2_rf = MemtoReg ? mem_out : alu_out;

	
endmodule