data/full_repos/permissive/427221126/src/AdderTree.v
1: b"%Error: data/full_repos/permissive/427221126/src/AdderTree.v:102: Cannot find file containing module: 'Add3'\n      Add3 #(.INWIDTH(INWIDTH), .IN_FRAC(IN_FRAC)) U_add3_l1 (\n      ^~~~\n        ... Looked in:\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/Add3\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/Add3.v\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/Add3.sv\n             Add3\n             Add3.v\n             Add3.sv\n             obj_dir/Add3\n             obj_dir/Add3.v\n             obj_dir/Add3.sv\n%Error: data/full_repos/permissive/427221126/src/AdderTree.v:114: Cannot find file containing module: 'Add3'\n      Add3 #(.INWIDTH(INWIDTH+2), .IN_FRAC(IN_FRAC)) U_add3_l2 (\n      ^~~~\n%Error: data/full_repos/permissive/427221126/src/AdderTree.v:181: Cannot find file containing module: 'Add3'\n      Add3 #(.INWIDTH(INWIDTH), .IN_FRAC(IN_FRAC)) U_add3_L0 (\n      ^~~~\n%Error: Exiting due to 3 error(s)\n"
module AdderTree
  #(
    parameter INWIDTH = 16,
              IN_FRAC = 10,
              NUM_INPUTS = 45
  )
  (
    input                           clk       ,
    input                           reset     ,
    input                           en        ,
    input  [INWIDTH*NUM_INPUTS-1:0] din       ,
    input                           din_valid ,
    output signed [INWIDTH+6:0]     dout      ,
    output                          dout_valid 
  );
  wire signed [INWIDTH+4:0] addertree15_dout;
  wire signed [INWIDTH+6:0] addertree45_dout;

  generate
    if (NUM_INPUTS == 15) begin
      AdderTree15 U_atree (
        .clk       ( clk              ),
        .reset     ( reset            ),
        .en        ( en               ),
        .din       ( din              ),
        .din_valid ( din_valid        ),
        .dout      ( addertree15_dout ),
        .dout_valid( dout_valid       ) 
      );

      assign dout = addertree15_dout;
    end
    else if (NUM_INPUTS == 45) begin
      AdderTree45 U_atree (
        .clk       ( clk              ),
        .reset     ( reset            ),
        .en        ( en               ),
        .din       ( din              ),
        .din_valid ( din_valid        ),
        .dout      ( addertree45_dout ),
        .dout_valid( dout_valid       ) 
      );

      assign dout = addertree45_dout;
    end
  endgenerate
endmodule
module AdderTree
  #(
    parameter INWIDTH = 16,
              IN_FRAC = 10,
              NUM_INPUTS = 45
  )
  (
    input                           clk       ,
    input                           reset     ,
    input                           en        ,
    input  [INWIDTH*NUM_INPUTS-1:0] din       ,
    input                           din_valid ,
    output signed [INWIDTH+6:0]     dout      ,
    output                          dout_valid 
  );

  wire signed [INWIDTH+4:0] addertree15_dout;
  wire signed [INWIDTH+6:0] addertree45_dout;

  generate
    if (NUM_INPUTS == 15) begin
      AdderTree15 U_atree (
        .clk       ( clk              ),
        .reset     ( reset            ),
        .en        ( en               ),
        .din       ( din              ),
        .din_valid ( din_valid        ),
        .dout      ( addertree15_dout ),
        .dout_valid( dout_valid       ) 
      );

      assign dout = addertree15_dout;
    end
    else if (NUM_INPUTS == 45) begin
      AdderTree45 U_atree (
        .clk       ( clk              ),
        .reset     ( reset            ),
        .en        ( en               ),
        .din       ( din              ),
        .din_valid ( din_valid        ),
        .dout      ( addertree45_dout ),
        .dout_valid( dout_valid       ) 
      );

      assign dout = addertree45_dout;
    end
  endgenerate
endmodule