data/full_repos/permissive/525152535/LUT6.v
data/verilator_xmls/abf8581a-799e-45ed-853f-e0c28b80df52.xml
module LUT6
#(
    parameter [63:0] INIT = 64'h0
)
(
    input  I0,
    input  I1,
    input  I2,
    input  I3,
    input  I4,
    input  I5,
    output F
);

    assign F = INIT[{I5, I4, I3, I2, I1, I0}];

endmodule
module LUT6
#(
    parameter [63:0] INIT = 64'h0
)
(
    input  I0,
    input  I1,
    input  I2,
    input  I3,
    input  I4,
    input  I5,
    output F
);


    assign F = INIT[{I5, I4, I3, I2, I1, I0}];

endmodule