data/full_repos/permissive/441359809/src/yosys/techlibs/sf2/cells_sim.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/techlibs/sf2/cells_sim.v:10: Multiple top level modules\n                                                                                             : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                             : ... Top module \'ADD2\'\nmodule ADD2 (\n       ^~~~\n                                                                                             : ... Top module \'ADD3\'\nmodule ADD3 (\n       ^~~~\n                                                                                             : ... Top module \'ADD4\'\nmodule ADD4 (\n       ^~~~\n                                                                                             : ... Top module \'CFG1\'\nmodule CFG1 (\n       ^~~~\n                                                                                             : ... Top module \'CFG2\'\nmodule CFG2 (\n       ^~~~\n                                                                                             : ... Top module \'CFG3\'\nmodule CFG3 (\n       ^~~~\n                                                                                             : ... Top module \'CFG4\'\nmodule CFG4 (\n       ^~~~\n                                                                                             : ... Top module \'BUFF\'\nmodule BUFF (\n       ^~~~\n                                                                                             : ... Top module \'BUFD\'\nmodule BUFD (\n       ^~~~\n                                                                                             : ... Top module \'CLKINT\'\nmodule CLKINT (\n       ^~~~~~\n                                                                                             : ... Top module \'CLKINT_PRESERVE\'\nmodule CLKINT_PRESERVE (\n       ^~~~~~~~~~~~~~~\n                                                                                             : ... Top module \'GCLKINT\'\nmodule GCLKINT (\n       ^~~~~~~\n                                                                                             : ... Top module \'RCLKINT\'\nmodule RCLKINT (\n       ^~~~~~~\n                                                                                             : ... Top module \'RGCLKINT\'\nmodule RGCLKINT (\n       ^~~~~~~~\n                                                                                             : ... Top module \'SLE\'\nmodule SLE (\n       ^~~\n                                                                                             : ... Top module \'GCLKBUF\'\nmodule GCLKBUF (\n       ^~~~~~~\n                                                                                             : ... Top module \'GCLKBUF_DIFF\'\nmodule GCLKBUF_DIFF (\n       ^~~~~~~~~~~~\n                                                                                             : ... Top module \'GCLKBIBUF\'\nmodule GCLKBIBUF (\n       ^~~~~~~~~\n                                                                                             : ... Top module \'INV\'\nmodule INV (\n       ^~~\n                                                                                             : ... Top module \'INVD\'\nmodule INVD (\n       ^~~~\n                                                                                             : ... Top module \'MX2\'\nmodule MX2 (\n       ^~~\n                                                                                             : ... Top module \'MX4\'\nmodule MX4 (\n       ^~~\n                                                                                             : ... Top module \'NAND2\'\nmodule NAND2 (\n       ^~~~~\n                                                                                             : ... Top module \'NAND3\'\nmodule NAND3 (\n       ^~~~~\n                                                                                             : ... Top module \'NAND4\'\nmodule NAND4 (\n       ^~~~~\n                                                                                             : ... Top module \'NOR2\'\nmodule NOR2 (\n       ^~~~\n                                                                                             : ... Top module \'NOR3\'\nmodule NOR3 (\n       ^~~~\n                                                                                             : ... Top module \'NOR4\'\nmodule NOR4 (\n       ^~~~\n                                                                                             : ... Top module \'OR2\'\nmodule OR2 (\n       ^~~\n                                                                                             : ... Top module \'OR3\'\nmodule OR3 (\n       ^~~\n                                                                                             : ... Top module \'OR4\'\nmodule OR4 (\n       ^~~\n                                                                                             : ... Top module \'XOR2\'\nmodule XOR2 (\n       ^~~~\n                                                                                             : ... Top module \'XOR3\'\nmodule XOR3 (\n       ^~~~\n                                                                                             : ... Top module \'XOR4\'\nmodule XOR4 (\n       ^~~~\n                                                                                             : ... Top module \'XOR8\'\nmodule XOR8 (\n       ^~~~\n                                                                                             : ... Top module \'BIBUF\'\nmodule BIBUF (\n       ^~~~~\n                                                                                             : ... Top module \'BIBUF_DIFF\'\nmodule BIBUF_DIFF (\n       ^~~~~~~~~~\n                                                                                             : ... Top module \'CLKBIBUF\'\nmodule CLKBIBUF (\n       ^~~~~~~~\n                                                                                             : ... Top module \'CLKBUF\'\nmodule CLKBUF (\n       ^~~~~~\n                                                                                             : ... Top module \'CLKBUF_DIFF\'\nmodule CLKBUF_DIFF (\n       ^~~~~~~~~~~\n                                                                                             : ... Top module \'INBUF\'\nmodule INBUF (\n       ^~~~~\n                                                                                             : ... Top module \'INBUF_DIFF\'\nmodule INBUF_DIFF (\n       ^~~~~~~~~~\n                                                                                             : ... Top module \'OUTBUF\'\nmodule OUTBUF (\n       ^~~~~~\n                                                                                             : ... Top module \'OUTBUF_DIFF\'\nmodule OUTBUF_DIFF (\n       ^~~~~~~~~~~\n                                                                                             : ... Top module \'TRIBUFF\'\nmodule TRIBUFF (\n       ^~~~~~~\n                                                                                             : ... Top module \'TRIBUFF_DIFF\'\nmodule TRIBUFF_DIFF (\n       ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/techlibs/sf2/cells_sim.v:59: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 16 bits.\n                                                                                          : ... In instance CFG4\n assign Y = INIT >> {D, C, B, A};\n          ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/techlibs/sf2/cells_sim.v:48: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 8 bits.\n                                                                                          : ... In instance CFG3\n assign Y = INIT >> {C, B, A};\n          ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/techlibs/sf2/cells_sim.v:38: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 4 bits.\n                                                                                          : ... In instance CFG2\n assign Y = INIT >> {B, A};\n          ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/techlibs/sf2/cells_sim.v:29: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 2 bits.\n                                                                                          : ... In instance CFG1\n assign Y = INIT >> A;\n          ^\n%Error: Exiting due to 5 warning(s)\n'
module XOR3 (
	input A, B, C,
	output Y
);
	assign Y = A ^ B ^ C;
endmodule
module XOR3 (
	input A, B, C,
	output Y
);

	assign Y = A ^ B ^ C;
endmodule