data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:30: Cannot find include file: sys.h\n`include "sys.h" // system level definition file which contains the  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:32: Cannot find include file: iop.h\n`include        "iop.h" \n                ^~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:79: Define or directive not defined: \'`PCX_RQ_HI\'\n   input [`PCX_RQ_HI-`PCX_RQ_LO:0]    pcx_iob_req;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:79: Define or directive not defined: \'`PCX_RQ_LO\'\n   input [`PCX_RQ_HI-`PCX_RQ_LO:0]    pcx_iob_req;\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:79: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   input [`PCX_RQ_HI-`PCX_RQ_LO:0]    pcx_iob_req;\n                               ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:80: Define or directive not defined: \'`PCX_AD_HI\'\n   input [`PCX_AD_HI-`PCX_AD_LO:0]    pcx_iob_addr;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:80: Define or directive not defined: \'`PCX_AD_LO\'\n   input [`PCX_AD_HI-`PCX_AD_LO:0]    pcx_iob_addr;\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:80: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   input [`PCX_AD_HI-`PCX_AD_LO:0]    pcx_iob_addr;\n                               ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:81: Define or directive not defined: \'`PCX_CP_HI\'\n   input [`PCX_CP_HI-`PCX_TH_LO:0]    pcx_iob_cputhr;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:81: Define or directive not defined: \'`PCX_TH_LO\'\n   input [`PCX_CP_HI-`PCX_TH_LO:0]    pcx_iob_cputhr;\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:81: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   input [`PCX_CP_HI-`PCX_TH_LO:0]    pcx_iob_cputhr;\n                               ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:93: Define or directive not defined: \'`IOB_MONDO_DATA_INDEX\'\n   output [`IOB_MONDO_DATA_INDEX-1:0] mondo_data_addr_p0_d1;\n           ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:97: Define or directive not defined: \'`IOB_CPU_BUF_INDEX\'\n   input [`IOB_CPU_BUF_INDEX:0]       cpu_buf_head_s;\n          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:97: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   input [`IOB_CPU_BUF_INDEX:0]       cpu_buf_head_s;\n                            ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:98: Define or directive not defined: \'`IOB_CPU_BUF_INDEX\'\n   output [`IOB_CPU_BUF_INDEX:0]      cpu_buf_tail_f;\n           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:98: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   output [`IOB_CPU_BUF_INDEX:0]      cpu_buf_tail_f;\n                             ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:113: Define or directive not defined: \'`IOB_MONDO_DATA_INDEX\'\n   input [`IOB_MONDO_DATA_INDEX-1:0]  io_mondo_data_wr_addr_s;\n          ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:117: Define or directive not defined: \'`IOB_ADDR_WIDTH\'\n   input [`IOB_ADDR_WIDTH-1:0]        tap_mondo_acc_addr_s;\n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:125: Define or directive not defined: \'`IOB_MONDO_DATA_INDEX\'\n   output [`IOB_MONDO_DATA_INDEX-1:0] mondo_data_addr_p0;\n           ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:126: Define or directive not defined: \'`IOB_MONDO_DATA_INDEX\'\n   output [`IOB_MONDO_DATA_INDEX-1:0] mondo_data_addr_p1;\n           ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:132: Define or directive not defined: \'`IOB_MONDO_DATA_INDEX\'\n   output [`IOB_MONDO_DATA_INDEX-1:0] mondo_busy_addr_p0;\n           ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:133: Define or directive not defined: \'`IOB_MONDO_DATA_INDEX\'\n   output [`IOB_MONDO_DATA_INDEX-1:0] mondo_busy_addr_p1;\n           ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:134: Define or directive not defined: \'`IOB_MONDO_DATA_INDEX\'\n   output [`IOB_MONDO_DATA_INDEX-1:0] mondo_busy_addr_p2;\n           ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:141: Define or directive not defined: \'`IOB_CPU_BUF_INDEX\'\n   output [`IOB_CPU_BUF_INDEX-1:0]    cpu_buf_tail_ptr;\n           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:153: Define or directive not defined: \'`IOB_MONDO_DATA_INDEX\'\n   wire [`IOB_MONDO_DATA_INDEX-1:0]   cpu_mondo_data_addr;\n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:160: Define or directive not defined: \'`IOB_MONDO_DATA_INDEX\'\n   wire [`IOB_MONDO_DATA_INDEX-1:0]   io_mondo_data_addr;\n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:162: Define or directive not defined: \'`IOB_ADDR_WIDTH\'\n   wire [`IOB_ADDR_WIDTH-1:0]        tap_mondo_acc_addr;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:166: Define or directive not defined: \'`IOB_MONDO_DATA_INDEX\'\n   wire [`IOB_MONDO_DATA_INDEX-1:0]   tap_mondo_data_addr;\n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:188: Define or directive not defined: \'`IOB_MONDO_DATA_INDEX\'\n   wire [`IOB_MONDO_DATA_INDEX-1:0]   mondo_data_addr_p1_d1;\n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:191: Define or directive not defined: \'`IOB_CPU_BUF_INDEX\'\n   wire [`IOB_CPU_BUF_INDEX:0]        cpu_buf_tail_plus;\n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:191: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   wire [`IOB_CPU_BUF_INDEX:0]        cpu_buf_tail_plus;\n                           ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:192: Define or directive not defined: \'`IOB_CPU_BUF_INDEX\'\n   wire [`IOB_CPU_BUF_INDEX:0]        cpu_buf_tail;\n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:192: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   wire [`IOB_CPU_BUF_INDEX:0]        cpu_buf_tail;\n                           ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:193: Define or directive not defined: \'`IOB_CPU_BUF_INDEX\'\n   wire [`IOB_CPU_BUF_INDEX:0]        cpu_buf_head;\n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:193: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   wire [`IOB_CPU_BUF_INDEX:0]        cpu_buf_head;\n                           ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:194: Define or directive not defined: \'`IOB_CPU_BUF_INDEX\'\n   wire [`IOB_CPU_BUF_INDEX:0]        cpu_buf_tail_plus8;\n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:194: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   wire [`IOB_CPU_BUF_INDEX:0]        cpu_buf_tail_plus8;\n                           ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:215: Define or directive not defined: \'`ADDR_MAP_HI\'\n                         (pcx_iob_addr[`ADDR_MAP_HI:`ADDR_MAP_LO] == `IOB_INT_CSR);\n                                       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:215: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n                         (pcx_iob_addr[`ADDR_MAP_HI:`ADDR_MAP_LO] == `IOB_INT_CSR);\n                                                   ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:215: Define or directive not defined: \'`ADDR_MAP_LO\'\n                         (pcx_iob_addr[`ADDR_MAP_HI:`ADDR_MAP_LO] == `IOB_INT_CSR);\n                                                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:215: Define or directive not defined: \'`IOB_INT_CSR\'\n                         (pcx_iob_addr[`ADDR_MAP_HI:`ADDR_MAP_LO] == `IOB_INT_CSR);\n                                                                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:217: Define or directive not defined: \'`LOAD_RQ\'\n   assign  cpu_mondo_rd = cpu_mondo_acc & (pcx_iob_req == `LOAD_RQ);\n                                                          ^~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:217: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   assign  cpu_mondo_rd = cpu_mondo_acc & (pcx_iob_req == `LOAD_RQ);\n                                                                  ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:229: Define or directive not defined: \'`STORE_RQ\'\n   assign  cpu_mondo_wr = cpu_mondo_acc & (pcx_iob_req == `STORE_RQ);\n                                                          ^~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:229: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   assign  cpu_mondo_wr = cpu_mondo_acc & (pcx_iob_req == `STORE_RQ);\n                                                                   ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:288: Define or directive not defined: \'`IOB_MONDO_DATA_INDEX\'\n   dffe_ns #(`IOB_MONDO_DATA_INDEX) io_mondo_data_addr_ff (.din(io_mondo_data_wr_addr_s),\n             ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:298: Define or directive not defined: \'`IOB_ADDR_WIDTH\'\n   dffe_ns #(`IOB_ADDR_WIDTH) tap_mondo_acc_addr_ff (.din(tap_mondo_acc_addr_s),\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:308: Define or directive not defined: \'`IOB_CPUTHR_INDEX\'\n          .thr_id_in(`IOB_CPUTHR_INDEX\'b0),\n                     ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:427: Define or directive not defined: \'`IOB_MONDO_DATA_INDEX\'\n   assign  mondo_data0_wr_lo = mondo_data0_wr & ~mondo_data_addr_p1[`IOB_MONDO_DATA_INDEX-1];\n                                                                    ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_fctrl.v:428: Define or directive not defined: \'`IOB_MONDO_DATA_INDEX\'\n   assign  mondo_data0_wr_hi = mondo_data0_wr & mondo_data_addr_p1[`IOB_MONDO_DATA_INDEX-1];\n                                                                   ^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module c2i_fctrl (

   iob_pcx_stall_pq, io_mondo_data_wr, mondo_data_bypass_d1, 
   mondo_addr_creg_mdata0_dec_d1, mondo_addr_creg_mdata1_dec_d1, 
   mondo_addr_creg_mbusy_dec_d1, cpu_mondo_rd_d1, tap_mondo_rd_d1, 
   cpu_mondo_rd_d2, cpu_mondo_addr_invld_d2, mondo_data_addr_p0_d1, 
   cpu_buf_tail_f, cpu_mondo_wr_d2, tap_mondo_acc_addr_invld_d2_f, 
   tap_mondo_acc_seq_d2_f, mondo_data_addr_p0, mondo_data_addr_p1, 
   mondo_data0_wr_lo_l, mondo_data0_wr_hi_l, mondo_data1_wr_lo_l, 
   mondo_data1_wr_hi_l, mondo_source_wr_l, mondo_busy_addr_p0, 
   mondo_busy_addr_p1, mondo_busy_addr_p2, mondo_busy_wr_p1, 
   mondo_busy_wr_p2, cpu_buf_wr_l, cpu_buf_tail_ptr, 

   cpu_rst_l, cpu_clk, tx_sync, rx_sync, pcx_iob_data_rdy_px2, 
   pcx_iob_vld, pcx_iob_req, pcx_iob_addr, pcx_iob_cputhr, 
   cpu_buf_head_s, int_buf_hit_hwm, io_mondo_data_wr_s, 
   io_mondo_data_wr_addr_s, tap_mondo_acc_addr_s, 
   tap_mondo_acc_seq_s, tap_mondo_wr_s
   );
   




   input                              cpu_rst_l;
   input 			      cpu_clk;
   input 			      tx_sync;
   input 			      rx_sync;

   

   input 			      pcx_iob_data_rdy_px2;
   output 			      iob_pcx_stall_pq;
   
 

   input 			      pcx_iob_vld;
   input [`PCX_RQ_HI-`PCX_RQ_LO:0]    pcx_iob_req;
   input [`PCX_AD_HI-`PCX_AD_LO:0]    pcx_iob_addr;
   input [`PCX_CP_HI-`PCX_TH_LO:0]    pcx_iob_cputhr;
 			      
   output 			      io_mondo_data_wr;
   output 			      mondo_data_bypass_d1;
   output 			      mondo_addr_creg_mdata0_dec_d1;
   output 			      mondo_addr_creg_mdata1_dec_d1;
   output 			      mondo_addr_creg_mbusy_dec_d1;
   output 			      cpu_mondo_rd_d1;
   output 			      tap_mondo_rd_d1;
   output 			      cpu_mondo_rd_d2;
   output 			      cpu_mondo_addr_invld_d2;
   
   output [`IOB_MONDO_DATA_INDEX-1:0] mondo_data_addr_p0_d1;

   

   input [`IOB_CPU_BUF_INDEX:0]       cpu_buf_head_s;
   output [`IOB_CPU_BUF_INDEX:0]      cpu_buf_tail_f;

   


   output 			      cpu_mondo_wr_d2;
   
   input 			      int_buf_hit_hwm;

   

   input 			      io_mondo_data_wr_s;

   

   input [`IOB_MONDO_DATA_INDEX-1:0]  io_mondo_data_wr_addr_s;
   
   

   input [`IOB_ADDR_WIDTH-1:0] 	      tap_mondo_acc_addr_s;
   input 			      tap_mondo_acc_seq_s;
   input 			      tap_mondo_wr_s;
   output 			      tap_mondo_acc_addr_invld_d2_f;
   output 			      tap_mondo_acc_seq_d2_f;
   
   

   output [`IOB_MONDO_DATA_INDEX-1:0] mondo_data_addr_p0;
   output [`IOB_MONDO_DATA_INDEX-1:0] mondo_data_addr_p1;
   output 			      mondo_data0_wr_lo_l;
   output 			      mondo_data0_wr_hi_l;
   output 			      mondo_data1_wr_lo_l;
   output 			      mondo_data1_wr_hi_l;
   output 			      mondo_source_wr_l;
   output [`IOB_MONDO_DATA_INDEX-1:0] mondo_busy_addr_p0;
   output [`IOB_MONDO_DATA_INDEX-1:0] mondo_busy_addr_p1;
   output [`IOB_MONDO_DATA_INDEX-1:0] mondo_busy_addr_p2;
   output 			      mondo_busy_wr_p1;
   output 			      mondo_busy_wr_p2;
   
   

   output 			      cpu_buf_wr_l;
   output [`IOB_CPU_BUF_INDEX-1:0]    cpu_buf_tail_ptr;

   

   wire 			      pcx_iob_data_rdy;
   wire 			      cpu_mondo_acc;
   wire 			      cpu_mondo_rd;
   wire 			      cpu_mondo_wr;
   wire 			      cpu_mondo_wr_d1;
   wire 			      cpu_mondo_addr_creg_mdata0_dec;
   wire 			      cpu_mondo_addr_creg_mdata1_dec;
   wire 			      cpu_mondo_addr_creg_mbusy_dec;
   wire [`IOB_MONDO_DATA_INDEX-1:0]   cpu_mondo_data_addr;
   wire 			      cpu_mondo_addr_invld;
   wire 			      cpu_mondo_addr_creg_mdata0_dec_d1;
   wire 			      cpu_mondo_addr_creg_mdata1_dec_d1;
   wire 			      cpu_mondo_addr_creg_mbusy_dec_d1;
   wire 			      cpu_mondo_addr_invld_d1;

   wire [`IOB_MONDO_DATA_INDEX-1:0]   io_mondo_data_addr;
   
   wire [`IOB_ADDR_WIDTH-1:0] 	      tap_mondo_acc_addr;
   wire 			      tap_mondo_addr_creg_mdata0_dec;
   wire 			      tap_mondo_addr_creg_mdata1_dec;
   wire 			      tap_mondo_addr_creg_mbusy_dec;
   wire [`IOB_MONDO_DATA_INDEX-1:0]   tap_mondo_data_addr;
   wire 			      tap_mondo_addr_invld;
   wire 			      tap_mondo_addr_creg_mdata0_dec_d1;
   wire 			      tap_mondo_addr_creg_mdata1_dec_d1;
   wire 			      tap_mondo_addr_creg_mbusy_dec_d1;
   wire 			      tap_mondo_addr_invld_d1;
   wire 			      tap_mondo_addr_invld_d2;
   wire 			      tap_mondo_acc_seq;
   wire 			      tap_mondo_acc_seq_d1;
   wire 			      tap_mondo_acc_seq_d2;
   wire 			      tap_mondo_wr;
   wire 			      tap_mondo_acc;
   wire 			      tap_mondo_rd;

   wire 			      mondo_data0_wr;
   wire 			      mondo_data0_wr_lo;
   wire 			      mondo_data0_wr_hi;
   wire 			      mondo_data1_wr;
   wire 			      mondo_data1_wr_lo;
   wire 			      mondo_data1_wr_hi;
   wire 			      mondo_source_wr;
   wire 			      mondo_data_wr_d1;
   wire [`IOB_MONDO_DATA_INDEX-1:0]   mondo_data_addr_p1_d1;
   
   wire 			      cpu_buf_wr;
   wire [`IOB_CPU_BUF_INDEX:0] 	      cpu_buf_tail_plus;
   wire [`IOB_CPU_BUF_INDEX:0] 	      cpu_buf_tail;
   wire [`IOB_CPU_BUF_INDEX:0] 	      cpu_buf_head;
   wire [`IOB_CPU_BUF_INDEX:0] 	      cpu_buf_tail_plus8;
   wire 			      cpu_buf_hit_hwm;

   




   dffrl_ns #(1) pcx_iob_data_rdy_ff (.din(pcx_iob_data_rdy_px2),
				      .clk(cpu_clk),
				      .rst_l(cpu_rst_l),
				      .q(pcx_iob_data_rdy));



   assign       cpu_mondo_acc = pcx_iob_data_rdy & pcx_iob_vld &
	                        (pcx_iob_addr[`ADDR_MAP_HI:`ADDR_MAP_LO] == `IOB_INT_CSR);
   
   assign 	cpu_mondo_rd = cpu_mondo_acc & (pcx_iob_req == `LOAD_RQ);
   
   dffrl_ns #(1) cpu_mondo_rd_d1_ff (.din(cpu_mondo_rd),
				     .clk(cpu_clk),
				     .rst_l(cpu_rst_l),
				     .q(cpu_mondo_rd_d1));
   
   dffrl_ns #(1) cpu_mondo_rd_d2_ff (.din(cpu_mondo_rd_d1),
				     .clk(cpu_clk),
				     .rst_l(cpu_rst_l),
				     .q(cpu_mondo_rd_d2));

   assign 	cpu_mondo_wr = cpu_mondo_acc & (pcx_iob_req == `STORE_RQ);

   dffrl_ns #(1) cpu_mondo_wr_d1_ff (.din(cpu_mondo_wr),
				     .clk(cpu_clk),
				     .rst_l(cpu_rst_l),
				     .q(cpu_mondo_wr_d1));
   
   dffrl_ns #(1) cpu_mondo_wr_d2_ff (.din(cpu_mondo_wr_d1),
				     .clk(cpu_clk),
				     .rst_l(cpu_rst_l),
				     .q(cpu_mondo_wr_d2));


   iobdg_int_mondo_addr_dec cpu_mondo_addr_dec (.addr_in(pcx_iob_addr),
					    	.thr_id_in(pcx_iob_cputhr),
					    	.creg_mdata0_dec(cpu_mondo_addr_creg_mdata0_dec),
					    	.creg_mdata1_dec(cpu_mondo_addr_creg_mdata1_dec),
					    	.creg_mbusy_dec(cpu_mondo_addr_creg_mbusy_dec),
					    	.mondo_data_addr(cpu_mondo_data_addr),
					    	.addr_invld(cpu_mondo_addr_invld));

   dffrl_ns #(1) cpu_mondo_addr_creg_mdata0_dec_d1_ff (.din(cpu_mondo_addr_creg_mdata0_dec),
						       .clk(cpu_clk),
						       .rst_l(cpu_rst_l),
						       .q(cpu_mondo_addr_creg_mdata0_dec_d1));

   dffrl_ns #(1) cpu_mondo_addr_creg_mdata1_dec_d1_ff (.din(cpu_mondo_addr_creg_mdata1_dec),
						       .clk(cpu_clk),
						       .rst_l(cpu_rst_l),
						       .q(cpu_mondo_addr_creg_mdata1_dec_d1));

   dffrl_ns #(1) cpu_mondo_addr_creg_mbusy_dec_d1_ff (.din(cpu_mondo_addr_creg_mbusy_dec),
						      .clk(cpu_clk),
						      .rst_l(cpu_rst_l),
						      .q(cpu_mondo_addr_creg_mbusy_dec_d1));
   
   dffrl_ns #(1) cpu_mondo_addr_invld_d1_ff (.din(cpu_mondo_addr_invld),
					     .clk(cpu_clk),
					     .rst_l(cpu_rst_l),
					     .q(cpu_mondo_addr_invld_d1));
   
   dffrl_ns #(1) cpu_mondo_addr_invld_d2_ff (.din(cpu_mondo_addr_invld_d1),
					     .clk(cpu_clk),
					     .rst_l(cpu_rst_l),
					     .q(cpu_mondo_addr_invld_d2));

  



   dffrle_ns #(1) io_mondo_data_wr_ff (.din(io_mondo_data_wr_s),
				       .rst_l(cpu_rst_l),
				       .en(rx_sync),
				       .clk(cpu_clk),
				       .q(io_mondo_data_wr));

   dffe_ns #(`IOB_MONDO_DATA_INDEX) io_mondo_data_addr_ff (.din(io_mondo_data_wr_addr_s),
						      	   .en(rx_sync),
						      	   .clk(cpu_clk),
						      	   .q(io_mondo_data_addr));
   



   dffe_ns #(`IOB_ADDR_WIDTH) tap_mondo_acc_addr_ff (.din(tap_mondo_acc_addr_s),
						     .en(rx_sync),
						     .clk(cpu_clk),
						     .q(tap_mondo_acc_addr));
   




   iobdg_int_mondo_addr_dec tap_mondo_addr_dec (.addr_in(tap_mondo_acc_addr),
					    	.thr_id_in(`IOB_CPUTHR_INDEX'b0),
					    	.creg_mdata0_dec(tap_mondo_addr_creg_mdata0_dec),
					    	.creg_mdata1_dec(tap_mondo_addr_creg_mdata1_dec),
					    	.creg_mbusy_dec(tap_mondo_addr_creg_mbusy_dec),
					    	.mondo_data_addr(tap_mondo_data_addr),
					    	.addr_invld(tap_mondo_addr_invld));
   
   dffrle_ns #(1) tap_mondo_addr_creg_mdata0_dec_d1_ff (.din(tap_mondo_addr_creg_mdata0_dec),
							.rst_l(cpu_rst_l),
							.en(tap_mondo_acc),
							.clk(cpu_clk),
							.q(tap_mondo_addr_creg_mdata0_dec_d1));

   dffrle_ns #(1) tap_mondo_addr_creg_mdata1_dec_d1_ff (.din(tap_mondo_addr_creg_mdata1_dec),
							.rst_l(cpu_rst_l),
							.en(tap_mondo_acc),
							.clk(cpu_clk),
							.q(tap_mondo_addr_creg_mdata1_dec_d1));

   dffrle_ns #(1) tap_mondo_addr_creg_mbusy_dec_d1_ff (.din(tap_mondo_addr_creg_mbusy_dec),
						       .rst_l(cpu_rst_l),
						       .en(tap_mondo_acc),
						       .clk(cpu_clk),
						       .q(tap_mondo_addr_creg_mbusy_dec_d1));

   dffrle_ns #(1) tap_mondo_addr_invld_d1_ff (.din(tap_mondo_addr_invld),
					      .rst_l(cpu_rst_l),
					      .en(tap_mondo_acc),
					      .clk(cpu_clk),
					      .q(tap_mondo_addr_invld_d1));

   dffrl_ns #(1) tap_mondo_addr_invld_d2_ff (.din(tap_mondo_addr_invld_d1),
					     .clk(cpu_clk),
					     .rst_l(cpu_rst_l),
					     .q(tap_mondo_addr_invld_d2));


   dffrle_ns #(1) tap_mondo_acc_addr_invld_d2_f_ff (.din(tap_mondo_addr_invld_d2),
						    .rst_l(cpu_rst_l),
						    .en(tx_sync),
						    .clk(cpu_clk),
						    .q(tap_mondo_acc_addr_invld_d2_f));



   dffrle_ns #(1) tap_mondo_acc_seq_ff (.din(tap_mondo_acc_seq_s),
					.rst_l(cpu_rst_l),
					.en(rx_sync),
					.clk(cpu_clk),
					.q(tap_mondo_acc_seq));


   dffrle_ns #(1) tap_mondo_acc_seq_d1_ff (.din(tap_mondo_acc_seq),
					   .rst_l(cpu_rst_l),
					   .en(tap_mondo_acc),
					   .clk(cpu_clk),
					   .q(tap_mondo_acc_seq_d1));

   dffrl_ns #(1) tap_mondo_acc_seq_d2_ff (.din(tap_mondo_acc_seq_d1),
					  .clk(cpu_clk),
					  .rst_l(cpu_rst_l),
					  .q(tap_mondo_acc_seq_d2));


   dffrle_ns #(1) tap_mondo_acc_seq_d2_f_ff (.din(tap_mondo_acc_seq_d2),
					     .rst_l(cpu_rst_l),
					     .en(tx_sync),
					     .clk(cpu_clk),
					     .q(tap_mondo_acc_seq_d2_f));

   

   dffrle_ns #(1) tap_mondo_wr_ff (.din(tap_mondo_wr_s),
				   .rst_l(cpu_rst_l),
				   .en(rx_sync),
				   .clk(cpu_clk),
				   .q(tap_mondo_wr));



   assign 	tap_mondo_acc = ~cpu_mondo_acc &
		                ~io_mondo_data_wr &
	                        (tap_mondo_acc_seq != tap_mondo_acc_seq_d1);

   assign 	tap_mondo_rd = tap_mondo_acc & ~tap_mondo_wr;
   
   dffrl_ns #(1) tap_mondo_rd_d1_ff (.din(tap_mondo_rd),
				     .clk(cpu_clk),
				     .rst_l(cpu_rst_l),
				     .q(tap_mondo_rd_d1));

   

   assign 	mondo_addr_creg_mdata0_dec_d1 = 
		cpu_mondo_rd_d1 ? cpu_mondo_addr_creg_mdata0_dec_d1 :
		                  tap_mondo_addr_creg_mdata0_dec_d1;
   
   assign 	mondo_addr_creg_mdata1_dec_d1 = 
		cpu_mondo_rd_d1 ? cpu_mondo_addr_creg_mdata1_dec_d1 :
		                  tap_mondo_addr_creg_mdata1_dec_d1;
   
   assign 	mondo_addr_creg_mbusy_dec_d1 = 
		cpu_mondo_rd_d1 ? cpu_mondo_addr_creg_mbusy_dec_d1 :
		                  tap_mondo_addr_creg_mbusy_dec_d1;
   
		

   assign 	mondo_data_addr_p0 = cpu_mondo_acc ? cpu_mondo_data_addr :
	                                             tap_mondo_data_addr;

   assign 	mondo_data_addr_p1 = io_mondo_data_wr ? io_mondo_data_addr :
	                                                tap_mondo_data_addr;

   assign 	mondo_data0_wr = io_mondo_data_wr |
		                 (tap_mondo_acc & tap_mondo_wr & tap_mondo_addr_creg_mdata0_dec);
   assign 	mondo_data0_wr_lo = mondo_data0_wr & ~mondo_data_addr_p1[`IOB_MONDO_DATA_INDEX-1];
   assign 	mondo_data0_wr_hi = mondo_data0_wr & mondo_data_addr_p1[`IOB_MONDO_DATA_INDEX-1];
   
   assign 	mondo_data1_wr = io_mondo_data_wr |
		                 (tap_mondo_acc & tap_mondo_wr & tap_mondo_addr_creg_mdata1_dec);
   assign 	mondo_data1_wr_lo = mondo_data1_wr & ~mondo_data_addr_p1[`IOB_MONDO_DATA_INDEX-1];
   assign 	mondo_data1_wr_hi = mondo_data1_wr & mondo_data_addr_p1[`IOB_MONDO_DATA_INDEX-1];
   
   assign 	mondo_source_wr = io_mondo_data_wr |
		                  (tap_mondo_acc & tap_mondo_wr & tap_mondo_addr_creg_mbusy_dec);

   assign 	mondo_data0_wr_lo_l = ~mondo_data0_wr_lo;
   assign 	mondo_data0_wr_hi_l = ~mondo_data0_wr_hi;
   assign 	mondo_data1_wr_lo_l = ~mondo_data1_wr_lo;
   assign 	mondo_data1_wr_hi_l = ~mondo_data1_wr_hi;
   assign 	mondo_source_wr_l = ~mondo_source_wr;
   







   dffrl_ns #(1) mondo_data_wr_d1_ff (.din(io_mondo_data_wr),
				      .clk(cpu_clk),
				      .rst_l(cpu_rst_l),
				      .q(mondo_data_wr_d1));

   dff_ns #(`IOB_MONDO_DATA_INDEX) mondo_data_addr_p0_d1_ff (.din(mondo_data_addr_p0),
							     .clk(cpu_clk),
							     .q(mondo_data_addr_p0_d1));
   
   dff_ns #(`IOB_MONDO_DATA_INDEX) mondo_data_addr_p1_d1_ff (.din(mondo_data_addr_p1),
							     .clk(cpu_clk),
							     .q(mondo_data_addr_p1_d1));

   assign 	mondo_data_bypass_d1 = mondo_data_wr_d1 &
	                               (mondo_data_addr_p0_d1 == mondo_data_addr_p1_d1);
   
   







   assign 	mondo_busy_addr_p0 = mondo_data_addr_p0;

   assign 	mondo_busy_addr_p1 = mondo_data_addr_p1;

   assign 	mondo_busy_addr_p2 = cpu_mondo_data_addr;
   

   assign 	mondo_busy_wr_p1 = io_mondo_data_wr |
                                   (tap_mondo_acc & tap_mondo_wr & tap_mondo_addr_creg_mbusy_dec);
   
   assign 	mondo_busy_wr_p2 = cpu_mondo_acc & cpu_mondo_wr & cpu_mondo_addr_creg_mbusy_dec;

 

   assign 	cpu_buf_wr = pcx_iob_data_rdy & pcx_iob_vld & ~(cpu_mondo_rd | cpu_mondo_wr);
   assign 	cpu_buf_wr_l = ~cpu_buf_wr;

   

   dffrle_ns #(`IOB_CPU_BUF_INDEX+1) cpu_buf_tail_ff (.din(cpu_buf_tail_plus),
						      .rst_l(cpu_rst_l),
						      .en(cpu_buf_wr),
						      .clk(cpu_clk),
						      .q(cpu_buf_tail));
   
   assign 	cpu_buf_tail_plus = cpu_buf_tail + 5'b1;
   
   assign 	cpu_buf_tail_ptr = cpu_buf_tail[`IOB_CPU_BUF_INDEX-1:0];
   

   dffrle_ns #(`IOB_CPU_BUF_INDEX+1) cpu_buf_tail_f_ff (.din(cpu_buf_tail),
							.rst_l(cpu_rst_l),
							.en(tx_sync),
							.clk(cpu_clk),
							.q(cpu_buf_tail_f));
   


   dffrle_ns #(`IOB_CPU_BUF_INDEX+1) cpu_buf_head_ff (.din(cpu_buf_head_s),
						      .rst_l(cpu_rst_l),
						      .en(rx_sync),
						      .clk(cpu_clk),
						      .q(cpu_buf_head));





   assign 	cpu_buf_tail_plus8 = cpu_buf_tail + 5'b01000;
   
   assign 	cpu_buf_hit_hwm = ((cpu_buf_tail_plus8[`IOB_CPU_BUF_INDEX] != cpu_buf_head[`IOB_CPU_BUF_INDEX]) &
	             		   (cpu_buf_tail_plus8[`IOB_CPU_BUF_INDEX-1:0] >= cpu_buf_head[`IOB_CPU_BUF_INDEX-1:0])) |
				  ((cpu_buf_tail_plus8[`IOB_CPU_BUF_INDEX] == cpu_buf_head[`IOB_CPU_BUF_INDEX]) &
	             		   (cpu_buf_tail_plus8[`IOB_CPU_BUF_INDEX-1:0] <= cpu_buf_head[`IOB_CPU_BUF_INDEX-1:0]));
   
   dffrl_ns #(1) iob_pcx_stall_pq_ff (.din(cpu_buf_hit_hwm | int_buf_hit_hwm),
				      .clk(cpu_clk),
				      .rst_l(cpu_rst_l),
				      .q(iob_pcx_stall_pq));
   

endmodule
module c2i_fctrl (

   iob_pcx_stall_pq, io_mondo_data_wr, mondo_data_bypass_d1, 
   mondo_addr_creg_mdata0_dec_d1, mondo_addr_creg_mdata1_dec_d1, 
   mondo_addr_creg_mbusy_dec_d1, cpu_mondo_rd_d1, tap_mondo_rd_d1, 
   cpu_mondo_rd_d2, cpu_mondo_addr_invld_d2, mondo_data_addr_p0_d1, 
   cpu_buf_tail_f, cpu_mondo_wr_d2, tap_mondo_acc_addr_invld_d2_f, 
   tap_mondo_acc_seq_d2_f, mondo_data_addr_p0, mondo_data_addr_p1, 
   mondo_data0_wr_lo_l, mondo_data0_wr_hi_l, mondo_data1_wr_lo_l, 
   mondo_data1_wr_hi_l, mondo_source_wr_l, mondo_busy_addr_p0, 
   mondo_busy_addr_p1, mondo_busy_addr_p2, mondo_busy_wr_p1, 
   mondo_busy_wr_p2, cpu_buf_wr_l, cpu_buf_tail_ptr, 

   cpu_rst_l, cpu_clk, tx_sync, rx_sync, pcx_iob_data_rdy_px2, 
   pcx_iob_vld, pcx_iob_req, pcx_iob_addr, pcx_iob_cputhr, 
   cpu_buf_head_s, int_buf_hit_hwm, io_mondo_data_wr_s, 
   io_mondo_data_wr_addr_s, tap_mondo_acc_addr_s, 
   tap_mondo_acc_seq_s, tap_mondo_wr_s
   );

   




   input                              cpu_rst_l;
   input 			      cpu_clk;
   input 			      tx_sync;
   input 			      rx_sync;

   

   input 			      pcx_iob_data_rdy_px2;
   output 			      iob_pcx_stall_pq;
   
 

   input 			      pcx_iob_vld;
   input [`PCX_RQ_HI-`PCX_RQ_LO:0]    pcx_iob_req;
   input [`PCX_AD_HI-`PCX_AD_LO:0]    pcx_iob_addr;
   input [`PCX_CP_HI-`PCX_TH_LO:0]    pcx_iob_cputhr;
 			      
   output 			      io_mondo_data_wr;
   output 			      mondo_data_bypass_d1;
   output 			      mondo_addr_creg_mdata0_dec_d1;
   output 			      mondo_addr_creg_mdata1_dec_d1;
   output 			      mondo_addr_creg_mbusy_dec_d1;
   output 			      cpu_mondo_rd_d1;
   output 			      tap_mondo_rd_d1;
   output 			      cpu_mondo_rd_d2;
   output 			      cpu_mondo_addr_invld_d2;
   
   output [`IOB_MONDO_DATA_INDEX-1:0] mondo_data_addr_p0_d1;

   

   input [`IOB_CPU_BUF_INDEX:0]       cpu_buf_head_s;
   output [`IOB_CPU_BUF_INDEX:0]      cpu_buf_tail_f;

   


   output 			      cpu_mondo_wr_d2;
   
   input 			      int_buf_hit_hwm;

   

   input 			      io_mondo_data_wr_s;

   

   input [`IOB_MONDO_DATA_INDEX-1:0]  io_mondo_data_wr_addr_s;
   
   

   input [`IOB_ADDR_WIDTH-1:0] 	      tap_mondo_acc_addr_s;
   input 			      tap_mondo_acc_seq_s;
   input 			      tap_mondo_wr_s;
   output 			      tap_mondo_acc_addr_invld_d2_f;
   output 			      tap_mondo_acc_seq_d2_f;
   
   

   output [`IOB_MONDO_DATA_INDEX-1:0] mondo_data_addr_p0;
   output [`IOB_MONDO_DATA_INDEX-1:0] mondo_data_addr_p1;
   output 			      mondo_data0_wr_lo_l;
   output 			      mondo_data0_wr_hi_l;
   output 			      mondo_data1_wr_lo_l;
   output 			      mondo_data1_wr_hi_l;
   output 			      mondo_source_wr_l;
   output [`IOB_MONDO_DATA_INDEX-1:0] mondo_busy_addr_p0;
   output [`IOB_MONDO_DATA_INDEX-1:0] mondo_busy_addr_p1;
   output [`IOB_MONDO_DATA_INDEX-1:0] mondo_busy_addr_p2;
   output 			      mondo_busy_wr_p1;
   output 			      mondo_busy_wr_p2;
   
   

   output 			      cpu_buf_wr_l;
   output [`IOB_CPU_BUF_INDEX-1:0]    cpu_buf_tail_ptr;

   

   wire 			      pcx_iob_data_rdy;
   wire 			      cpu_mondo_acc;
   wire 			      cpu_mondo_rd;
   wire 			      cpu_mondo_wr;
   wire 			      cpu_mondo_wr_d1;
   wire 			      cpu_mondo_addr_creg_mdata0_dec;
   wire 			      cpu_mondo_addr_creg_mdata1_dec;
   wire 			      cpu_mondo_addr_creg_mbusy_dec;
   wire [`IOB_MONDO_DATA_INDEX-1:0]   cpu_mondo_data_addr;
   wire 			      cpu_mondo_addr_invld;
   wire 			      cpu_mondo_addr_creg_mdata0_dec_d1;
   wire 			      cpu_mondo_addr_creg_mdata1_dec_d1;
   wire 			      cpu_mondo_addr_creg_mbusy_dec_d1;
   wire 			      cpu_mondo_addr_invld_d1;

   wire [`IOB_MONDO_DATA_INDEX-1:0]   io_mondo_data_addr;
   
   wire [`IOB_ADDR_WIDTH-1:0] 	      tap_mondo_acc_addr;
   wire 			      tap_mondo_addr_creg_mdata0_dec;
   wire 			      tap_mondo_addr_creg_mdata1_dec;
   wire 			      tap_mondo_addr_creg_mbusy_dec;
   wire [`IOB_MONDO_DATA_INDEX-1:0]   tap_mondo_data_addr;
   wire 			      tap_mondo_addr_invld;
   wire 			      tap_mondo_addr_creg_mdata0_dec_d1;
   wire 			      tap_mondo_addr_creg_mdata1_dec_d1;
   wire 			      tap_mondo_addr_creg_mbusy_dec_d1;
   wire 			      tap_mondo_addr_invld_d1;
   wire 			      tap_mondo_addr_invld_d2;
   wire 			      tap_mondo_acc_seq;
   wire 			      tap_mondo_acc_seq_d1;
   wire 			      tap_mondo_acc_seq_d2;
   wire 			      tap_mondo_wr;
   wire 			      tap_mondo_acc;
   wire 			      tap_mondo_rd;

   wire 			      mondo_data0_wr;
   wire 			      mondo_data0_wr_lo;
   wire 			      mondo_data0_wr_hi;
   wire 			      mondo_data1_wr;
   wire 			      mondo_data1_wr_lo;
   wire 			      mondo_data1_wr_hi;
   wire 			      mondo_source_wr;
   wire 			      mondo_data_wr_d1;
   wire [`IOB_MONDO_DATA_INDEX-1:0]   mondo_data_addr_p1_d1;
   
   wire 			      cpu_buf_wr;
   wire [`IOB_CPU_BUF_INDEX:0] 	      cpu_buf_tail_plus;
   wire [`IOB_CPU_BUF_INDEX:0] 	      cpu_buf_tail;
   wire [`IOB_CPU_BUF_INDEX:0] 	      cpu_buf_head;
   wire [`IOB_CPU_BUF_INDEX:0] 	      cpu_buf_tail_plus8;
   wire 			      cpu_buf_hit_hwm;

   




   dffrl_ns #(1) pcx_iob_data_rdy_ff (.din(pcx_iob_data_rdy_px2),
				      .clk(cpu_clk),
				      .rst_l(cpu_rst_l),
				      .q(pcx_iob_data_rdy));



   assign       cpu_mondo_acc = pcx_iob_data_rdy & pcx_iob_vld &
	                        (pcx_iob_addr[`ADDR_MAP_HI:`ADDR_MAP_LO] == `IOB_INT_CSR);
   
   assign 	cpu_mondo_rd = cpu_mondo_acc & (pcx_iob_req == `LOAD_RQ);
   
   dffrl_ns #(1) cpu_mondo_rd_d1_ff (.din(cpu_mondo_rd),
				     .clk(cpu_clk),
				     .rst_l(cpu_rst_l),
				     .q(cpu_mondo_rd_d1));
   
   dffrl_ns #(1) cpu_mondo_rd_d2_ff (.din(cpu_mondo_rd_d1),
				     .clk(cpu_clk),
				     .rst_l(cpu_rst_l),
				     .q(cpu_mondo_rd_d2));

   assign 	cpu_mondo_wr = cpu_mondo_acc & (pcx_iob_req == `STORE_RQ);

   dffrl_ns #(1) cpu_mondo_wr_d1_ff (.din(cpu_mondo_wr),
				     .clk(cpu_clk),
				     .rst_l(cpu_rst_l),
				     .q(cpu_mondo_wr_d1));
   
   dffrl_ns #(1) cpu_mondo_wr_d2_ff (.din(cpu_mondo_wr_d1),
				     .clk(cpu_clk),
				     .rst_l(cpu_rst_l),
				     .q(cpu_mondo_wr_d2));


   iobdg_int_mondo_addr_dec cpu_mondo_addr_dec (.addr_in(pcx_iob_addr),
					    	.thr_id_in(pcx_iob_cputhr),
					    	.creg_mdata0_dec(cpu_mondo_addr_creg_mdata0_dec),
					    	.creg_mdata1_dec(cpu_mondo_addr_creg_mdata1_dec),
					    	.creg_mbusy_dec(cpu_mondo_addr_creg_mbusy_dec),
					    	.mondo_data_addr(cpu_mondo_data_addr),
					    	.addr_invld(cpu_mondo_addr_invld));

   dffrl_ns #(1) cpu_mondo_addr_creg_mdata0_dec_d1_ff (.din(cpu_mondo_addr_creg_mdata0_dec),
						       .clk(cpu_clk),
						       .rst_l(cpu_rst_l),
						       .q(cpu_mondo_addr_creg_mdata0_dec_d1));

   dffrl_ns #(1) cpu_mondo_addr_creg_mdata1_dec_d1_ff (.din(cpu_mondo_addr_creg_mdata1_dec),
						       .clk(cpu_clk),
						       .rst_l(cpu_rst_l),
						       .q(cpu_mondo_addr_creg_mdata1_dec_d1));

   dffrl_ns #(1) cpu_mondo_addr_creg_mbusy_dec_d1_ff (.din(cpu_mondo_addr_creg_mbusy_dec),
						      .clk(cpu_clk),
						      .rst_l(cpu_rst_l),
						      .q(cpu_mondo_addr_creg_mbusy_dec_d1));
   
   dffrl_ns #(1) cpu_mondo_addr_invld_d1_ff (.din(cpu_mondo_addr_invld),
					     .clk(cpu_clk),
					     .rst_l(cpu_rst_l),
					     .q(cpu_mondo_addr_invld_d1));
   
   dffrl_ns #(1) cpu_mondo_addr_invld_d2_ff (.din(cpu_mondo_addr_invld_d1),
					     .clk(cpu_clk),
					     .rst_l(cpu_rst_l),
					     .q(cpu_mondo_addr_invld_d2));

  



   dffrle_ns #(1) io_mondo_data_wr_ff (.din(io_mondo_data_wr_s),
				       .rst_l(cpu_rst_l),
				       .en(rx_sync),
				       .clk(cpu_clk),
				       .q(io_mondo_data_wr));

   dffe_ns #(`IOB_MONDO_DATA_INDEX) io_mondo_data_addr_ff (.din(io_mondo_data_wr_addr_s),
						      	   .en(rx_sync),
						      	   .clk(cpu_clk),
						      	   .q(io_mondo_data_addr));
   



   dffe_ns #(`IOB_ADDR_WIDTH) tap_mondo_acc_addr_ff (.din(tap_mondo_acc_addr_s),
						     .en(rx_sync),
						     .clk(cpu_clk),
						     .q(tap_mondo_acc_addr));
   




   iobdg_int_mondo_addr_dec tap_mondo_addr_dec (.addr_in(tap_mondo_acc_addr),
					    	.thr_id_in(`IOB_CPUTHR_INDEX'b0),
					    	.creg_mdata0_dec(tap_mondo_addr_creg_mdata0_dec),
					    	.creg_mdata1_dec(tap_mondo_addr_creg_mdata1_dec),
					    	.creg_mbusy_dec(tap_mondo_addr_creg_mbusy_dec),
					    	.mondo_data_addr(tap_mondo_data_addr),
					    	.addr_invld(tap_mondo_addr_invld));
   
   dffrle_ns #(1) tap_mondo_addr_creg_mdata0_dec_d1_ff (.din(tap_mondo_addr_creg_mdata0_dec),
							.rst_l(cpu_rst_l),
							.en(tap_mondo_acc),
							.clk(cpu_clk),
							.q(tap_mondo_addr_creg_mdata0_dec_d1));

   dffrle_ns #(1) tap_mondo_addr_creg_mdata1_dec_d1_ff (.din(tap_mondo_addr_creg_mdata1_dec),
							.rst_l(cpu_rst_l),
							.en(tap_mondo_acc),
							.clk(cpu_clk),
							.q(tap_mondo_addr_creg_mdata1_dec_d1));

   dffrle_ns #(1) tap_mondo_addr_creg_mbusy_dec_d1_ff (.din(tap_mondo_addr_creg_mbusy_dec),
						       .rst_l(cpu_rst_l),
						       .en(tap_mondo_acc),
						       .clk(cpu_clk),
						       .q(tap_mondo_addr_creg_mbusy_dec_d1));

   dffrle_ns #(1) tap_mondo_addr_invld_d1_ff (.din(tap_mondo_addr_invld),
					      .rst_l(cpu_rst_l),
					      .en(tap_mondo_acc),
					      .clk(cpu_clk),
					      .q(tap_mondo_addr_invld_d1));

   dffrl_ns #(1) tap_mondo_addr_invld_d2_ff (.din(tap_mondo_addr_invld_d1),
					     .clk(cpu_clk),
					     .rst_l(cpu_rst_l),
					     .q(tap_mondo_addr_invld_d2));


   dffrle_ns #(1) tap_mondo_acc_addr_invld_d2_f_ff (.din(tap_mondo_addr_invld_d2),
						    .rst_l(cpu_rst_l),
						    .en(tx_sync),
						    .clk(cpu_clk),
						    .q(tap_mondo_acc_addr_invld_d2_f));



   dffrle_ns #(1) tap_mondo_acc_seq_ff (.din(tap_mondo_acc_seq_s),
					.rst_l(cpu_rst_l),
					.en(rx_sync),
					.clk(cpu_clk),
					.q(tap_mondo_acc_seq));


   dffrle_ns #(1) tap_mondo_acc_seq_d1_ff (.din(tap_mondo_acc_seq),
					   .rst_l(cpu_rst_l),
					   .en(tap_mondo_acc),
					   .clk(cpu_clk),
					   .q(tap_mondo_acc_seq_d1));

   dffrl_ns #(1) tap_mondo_acc_seq_d2_ff (.din(tap_mondo_acc_seq_d1),
					  .clk(cpu_clk),
					  .rst_l(cpu_rst_l),
					  .q(tap_mondo_acc_seq_d2));


   dffrle_ns #(1) tap_mondo_acc_seq_d2_f_ff (.din(tap_mondo_acc_seq_d2),
					     .rst_l(cpu_rst_l),
					     .en(tx_sync),
					     .clk(cpu_clk),
					     .q(tap_mondo_acc_seq_d2_f));

   

   dffrle_ns #(1) tap_mondo_wr_ff (.din(tap_mondo_wr_s),
				   .rst_l(cpu_rst_l),
				   .en(rx_sync),
				   .clk(cpu_clk),
				   .q(tap_mondo_wr));



   assign 	tap_mondo_acc = ~cpu_mondo_acc &
		                ~io_mondo_data_wr &
	                        (tap_mondo_acc_seq != tap_mondo_acc_seq_d1);

   assign 	tap_mondo_rd = tap_mondo_acc & ~tap_mondo_wr;
   
   dffrl_ns #(1) tap_mondo_rd_d1_ff (.din(tap_mondo_rd),
				     .clk(cpu_clk),
				     .rst_l(cpu_rst_l),
				     .q(tap_mondo_rd_d1));

   

   assign 	mondo_addr_creg_mdata0_dec_d1 = 
		cpu_mondo_rd_d1 ? cpu_mondo_addr_creg_mdata0_dec_d1 :
		                  tap_mondo_addr_creg_mdata0_dec_d1;
   
   assign 	mondo_addr_creg_mdata1_dec_d1 = 
		cpu_mondo_rd_d1 ? cpu_mondo_addr_creg_mdata1_dec_d1 :
		                  tap_mondo_addr_creg_mdata1_dec_d1;
   
   assign 	mondo_addr_creg_mbusy_dec_d1 = 
		cpu_mondo_rd_d1 ? cpu_mondo_addr_creg_mbusy_dec_d1 :
		                  tap_mondo_addr_creg_mbusy_dec_d1;
   
		

   assign 	mondo_data_addr_p0 = cpu_mondo_acc ? cpu_mondo_data_addr :
	                                             tap_mondo_data_addr;

   assign 	mondo_data_addr_p1 = io_mondo_data_wr ? io_mondo_data_addr :
	                                                tap_mondo_data_addr;

   assign 	mondo_data0_wr = io_mondo_data_wr |
		                 (tap_mondo_acc & tap_mondo_wr & tap_mondo_addr_creg_mdata0_dec);
   assign 	mondo_data0_wr_lo = mondo_data0_wr & ~mondo_data_addr_p1[`IOB_MONDO_DATA_INDEX-1];
   assign 	mondo_data0_wr_hi = mondo_data0_wr & mondo_data_addr_p1[`IOB_MONDO_DATA_INDEX-1];
   
   assign 	mondo_data1_wr = io_mondo_data_wr |
		                 (tap_mondo_acc & tap_mondo_wr & tap_mondo_addr_creg_mdata1_dec);
   assign 	mondo_data1_wr_lo = mondo_data1_wr & ~mondo_data_addr_p1[`IOB_MONDO_DATA_INDEX-1];
   assign 	mondo_data1_wr_hi = mondo_data1_wr & mondo_data_addr_p1[`IOB_MONDO_DATA_INDEX-1];
   
   assign 	mondo_source_wr = io_mondo_data_wr |
		                  (tap_mondo_acc & tap_mondo_wr & tap_mondo_addr_creg_mbusy_dec);

   assign 	mondo_data0_wr_lo_l = ~mondo_data0_wr_lo;
   assign 	mondo_data0_wr_hi_l = ~mondo_data0_wr_hi;
   assign 	mondo_data1_wr_lo_l = ~mondo_data1_wr_lo;
   assign 	mondo_data1_wr_hi_l = ~mondo_data1_wr_hi;
   assign 	mondo_source_wr_l = ~mondo_source_wr;
   







   dffrl_ns #(1) mondo_data_wr_d1_ff (.din(io_mondo_data_wr),
				      .clk(cpu_clk),
				      .rst_l(cpu_rst_l),
				      .q(mondo_data_wr_d1));

   dff_ns #(`IOB_MONDO_DATA_INDEX) mondo_data_addr_p0_d1_ff (.din(mondo_data_addr_p0),
							     .clk(cpu_clk),
							     .q(mondo_data_addr_p0_d1));
   
   dff_ns #(`IOB_MONDO_DATA_INDEX) mondo_data_addr_p1_d1_ff (.din(mondo_data_addr_p1),
							     .clk(cpu_clk),
							     .q(mondo_data_addr_p1_d1));

   assign 	mondo_data_bypass_d1 = mondo_data_wr_d1 &
	                               (mondo_data_addr_p0_d1 == mondo_data_addr_p1_d1);
   
   







   assign 	mondo_busy_addr_p0 = mondo_data_addr_p0;

   assign 	mondo_busy_addr_p1 = mondo_data_addr_p1;

   assign 	mondo_busy_addr_p2 = cpu_mondo_data_addr;
   

   assign 	mondo_busy_wr_p1 = io_mondo_data_wr |
                                   (tap_mondo_acc & tap_mondo_wr & tap_mondo_addr_creg_mbusy_dec);
   
   assign 	mondo_busy_wr_p2 = cpu_mondo_acc & cpu_mondo_wr & cpu_mondo_addr_creg_mbusy_dec;

 

   assign 	cpu_buf_wr = pcx_iob_data_rdy & pcx_iob_vld & ~(cpu_mondo_rd | cpu_mondo_wr);
   assign 	cpu_buf_wr_l = ~cpu_buf_wr;

   

   dffrle_ns #(`IOB_CPU_BUF_INDEX+1) cpu_buf_tail_ff (.din(cpu_buf_tail_plus),
						      .rst_l(cpu_rst_l),
						      .en(cpu_buf_wr),
						      .clk(cpu_clk),
						      .q(cpu_buf_tail));
   
   assign 	cpu_buf_tail_plus = cpu_buf_tail + 5'b1;
   
   assign 	cpu_buf_tail_ptr = cpu_buf_tail[`IOB_CPU_BUF_INDEX-1:0];
   

   dffrle_ns #(`IOB_CPU_BUF_INDEX+1) cpu_buf_tail_f_ff (.din(cpu_buf_tail),
							.rst_l(cpu_rst_l),
							.en(tx_sync),
							.clk(cpu_clk),
							.q(cpu_buf_tail_f));
   


   dffrle_ns #(`IOB_CPU_BUF_INDEX+1) cpu_buf_head_ff (.din(cpu_buf_head_s),
						      .rst_l(cpu_rst_l),
						      .en(rx_sync),
						      .clk(cpu_clk),
						      .q(cpu_buf_head));





   assign 	cpu_buf_tail_plus8 = cpu_buf_tail + 5'b01000;
   
   assign 	cpu_buf_hit_hwm = ((cpu_buf_tail_plus8[`IOB_CPU_BUF_INDEX] != cpu_buf_head[`IOB_CPU_BUF_INDEX]) &
	             		   (cpu_buf_tail_plus8[`IOB_CPU_BUF_INDEX-1:0] >= cpu_buf_head[`IOB_CPU_BUF_INDEX-1:0])) |
				  ((cpu_buf_tail_plus8[`IOB_CPU_BUF_INDEX] == cpu_buf_head[`IOB_CPU_BUF_INDEX]) &
	             		   (cpu_buf_tail_plus8[`IOB_CPU_BUF_INDEX-1:0] <= cpu_buf_head[`IOB_CPU_BUF_INDEX-1:0]));
   
   dffrl_ns #(1) iob_pcx_stall_pq_ff (.din(cpu_buf_hit_hwm | int_buf_hit_hwm),
				      .clk(cpu_clk),
				      .rst_l(cpu_rst_l),
				      .q(iob_pcx_stall_pq));
   

endmodule