data/full_repos/permissive/504478691/sound/harmony_and_scale/sound_pwm.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/504478691/sound/harmony_and_scale/sound_pwm.v:14: Multiple top level modules\n                                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                              : ... Top module \'square\'\nmodule square(input [31:0] f_dHz, input clk, output reg soundbit = 0);\n       ^~~~~~\n                                                                                              : ... Top module \'harmonic_pwm\'\nmodule harmonic_pwm(input [31:0] f_dHz, input clk, output soundbit);\n       ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/504478691/sound/harmony_and_scale/sound_pwm.v:16: Operator DIV expects 64 bits on the RHS, but RHS\'s VARREF \'f_dHz\' generates 32 bits.\n                                                                                           : ... In instance harmonic_pwm\nassign N_0 = 100_000_000_0 / f_dHz;\n                           ^\n%Error: Exiting due to 2 warning(s)\n'
module harmonic_pwm(input [31:0] f_dHz, input clk, output soundbit);
wire [63:0] N_0;
assign N_0 = 100_000_000_0 / f_dHz;
parameter N = 100;
wire [63:0] N_V;




reg [63:0] n = N;
reg [63:0] n_0 = 0;
parameter pi_10000 = 31416;



assign soundbit = (n < N_V) ? 1 : 0;

reg [63:0] n_0_0 = 0;
reg [63:0] N_V_0 = 0;
reg [63:0] tmp = 0;
assign N_V = (100000 * N_0 / n_0 / N >= 200000) ? (N / 2 + N_V_0 / 2) : (N / 2 - N_V_0 / 2);



always @(posedge clk)
begin
    if (n >= N)
    begin
        n = 1;
        if (n_0 >= N_0 / N)
            n_0 = 1;
        else
            n_0 = n_0 + 1;

        if (100000 * N_0 / n_0 / N >= 400000)
            n_0_0 = n_0;
        else if (200000 * N_0 / n_0 / N >= 400000)
            n_0_0 = N_0 / N / 2 - n_0;
        else if (300000 * N_0 / n_0 / N >= 400000)
            n_0_0 = n_0 - N_0 / N / 2;
        else n_0_0 = N_0 / N - n_0;





        tmp = 2 * pi_10000 * N * N * n_0_0 / N_0 / 10000;
        N_V_0 = tmp;
        tmp = tmp * 2 * pi_10000 * pi_10000 / 3  / (10000 * N_0 / N / n_0_0) / (10000 * N_0 / N / n_0_0);
        N_V_0 = N_V_0 - tmp;
        tmp = tmp * 1 * pi_10000 * pi_10000 / 5  / (10000 * N_0 / N / n_0_0) / (10000 * N_0 / N / n_0_0);
        N_V_0 = N_V_0 + tmp;
        tmp = tmp * 2 * pi_10000 * pi_10000 / 21 / (10000 * N_0 / N / n_0_0) / (10000 * N_0 / N / n_0_0);
        N_V_0 = N_V_0 - tmp;
    end
    else
        n = n + 1;
end
endmodule
module harmonic_pwm(input [31:0] f_dHz, input clk, output soundbit);

wire [63:0] N_0;
assign N_0 = 100_000_000_0 / f_dHz;
parameter N = 100;
wire [63:0] N_V;




reg [63:0] n = N;
reg [63:0] n_0 = 0;
parameter pi_10000 = 31416;



assign soundbit = (n < N_V) ? 1 : 0;

reg [63:0] n_0_0 = 0;
reg [63:0] N_V_0 = 0;
reg [63:0] tmp = 0;
assign N_V = (100000 * N_0 / n_0 / N >= 200000) ? (N / 2 + N_V_0 / 2) : (N / 2 - N_V_0 / 2);



always @(posedge clk)
begin
    if (n >= N)
    begin
        n = 1;
        if (n_0 >= N_0 / N)
            n_0 = 1;
        else
            n_0 = n_0 + 1;

        if (100000 * N_0 / n_0 / N >= 400000)
            n_0_0 = n_0;
        else if (200000 * N_0 / n_0 / N >= 400000)
            n_0_0 = N_0 / N / 2 - n_0;
        else if (300000 * N_0 / n_0 / N >= 400000)
            n_0_0 = n_0 - N_0 / N / 2;
        else n_0_0 = N_0 / N - n_0;





        tmp = 2 * pi_10000 * N * N * n_0_0 / N_0 / 10000;
        N_V_0 = tmp;
        tmp = tmp * 2 * pi_10000 * pi_10000 / 3  / (10000 * N_0 / N / n_0_0) / (10000 * N_0 / N / n_0_0);
        N_V_0 = N_V_0 - tmp;
        tmp = tmp * 1 * pi_10000 * pi_10000 / 5  / (10000 * N_0 / N / n_0_0) / (10000 * N_0 / N / n_0_0);
        N_V_0 = N_V_0 + tmp;
        tmp = tmp * 2 * pi_10000 * pi_10000 / 21 / (10000 * N_0 / N / n_0_0) / (10000 * N_0 / N / n_0_0);
        N_V_0 = N_V_0 - tmp;
    end
    else
        n = n + 1;
end
endmodule