data/full_repos/permissive/431682734/LabL/cpu.v
1: b'%Error: data/full_repos/permissive/431682734/LabL/cpu.v:25: syntax error, unexpected final, expecting IDENTIFIER\n    yMux #(SIZE) final(z, zLo, zHi, c[1]);\n                 ^~~~~\n%Error: Exiting due to 1 error(s)\n'
module yMux1(z, a, b, c);
    output z;
    input a, b, c;
    wire notC, upper, lower;
    not my_not(notC, c);
    and upperAnd(upper, a, notC);
    and lowerAnd(lower, c, b);
    or my_or(z, upper, lower);
endmodule
module yMux1(z, a, b, c);

    output z;
    input a, b, c;
    wire notC, upper, lower;
    not my_not(notC, c);
    and upperAnd(upper, a, notC);
    and lowerAnd(lower, c, b);
    or my_or(z, upper, lower);
endmodule