data/full_repos/permissive/435914753/Display_kbd/kbd_protocol_2prevState.v
1: b'%Warning-WIDTH: data/full_repos/permissive/435914753/Display_kbd/kbd_protocol_2prevState.v:11: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 9 bits.\n                                                                                             : ... In instance kbd_protocol\n      else ps2clksamples <= {ps2clksamples[7:0], ps2clk};\n                         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module kbd_protocol (reset, clk, ps2clk, ps2data, scancode, scanPrev, scanPrev2);
  input        reset, clk, ps2clk, ps2data;
  output [7:0] scancode, scanPrev, scanPrev2;
  reg    [7:0] scancode, scanPrev, scanPrev2;


  reg    [7:0] ps2clksamples;

  always @(posedge clk or posedge reset)
    if (reset) ps2clksamples <= 8'd0;
      else ps2clksamples <= {ps2clksamples[7:0], ps2clk};

  wire fall_edge;
  assign fall_edge = (ps2clksamples[7:4] == 4'hF) & (ps2clksamples[3:0] == 4'h0);

  reg    [9:0] shift;
  reg    [3:0] cnt;
  reg          f0;
  







  always @(posedge clk or posedge reset)
    if (reset) 
      begin
        cnt    <= 4'd0;
		  scanPrev2 <= 8'd0;

		  scanPrev <= 8'd0;
        scancode <= 8'd0;
        shift    <= 10'd0;
        f0       <= 1'b0;
      end  
     else if (fall_edge)
         begin
           if (cnt == 4'd10)
             begin
               cnt <= 0;
               if ((shift[0] == 0) && (ps2data == 1) && (^shift[9:1]==1))
                 begin
                   if (f0)
                     begin
						scanPrev2 <= scanPrev;
						scanPrev <= scancode;
						scancode <= shift[8:1];
						f0 <= 0;						
                     end
                    else if (shift[8:1] == 8'hF0) f0 <= 1'b1;
                 end
             end
            else
             begin
               shift <= {ps2data, shift[9:1]};
               cnt <= cnt+1;
             end
         end
endmodule
module kbd_protocol (reset, clk, ps2clk, ps2data, scancode, scanPrev, scanPrev2);

  input        reset, clk, ps2clk, ps2data;
  output [7:0] scancode, scanPrev, scanPrev2;
  reg    [7:0] scancode, scanPrev, scanPrev2;


  reg    [7:0] ps2clksamples;

  always @(posedge clk or posedge reset)
    if (reset) ps2clksamples <= 8'd0;
      else ps2clksamples <= {ps2clksamples[7:0], ps2clk};

  wire fall_edge;
  assign fall_edge = (ps2clksamples[7:4] == 4'hF) & (ps2clksamples[3:0] == 4'h0);

  reg    [9:0] shift;
  reg    [3:0] cnt;
  reg          f0;
  







  always @(posedge clk or posedge reset)
    if (reset) 
      begin
        cnt    <= 4'd0;
		  scanPrev2 <= 8'd0;

		  scanPrev <= 8'd0;
        scancode <= 8'd0;
        shift    <= 10'd0;
        f0       <= 1'b0;
      end  
     else if (fall_edge)
         begin
           if (cnt == 4'd10)
             begin
               cnt <= 0;
               if ((shift[0] == 0) && (ps2data == 1) && (^shift[9:1]==1))
                 begin
                   if (f0)
                     begin
						scanPrev2 <= scanPrev;
						scanPrev <= scancode;
						scancode <= shift[8:1];
						f0 <= 0;						
                     end
                    else if (shift[8:1] == 8'hF0) f0 <= 1'b1;
                 end
             end
            else
             begin
               shift <= {ps2data, shift[9:1]};
               cnt <= cnt+1;
             end
         end
endmodule