data/full_repos/permissive/43856783/j1_soc/hdl/Position/Integradorv2.v
1: b'%Error: data/full_repos/permissive/43856783/j1_soc/hdl/Position/Integradorv2.v:41: Cannot find file containing module: \'booth_mult\'\n    booth_mult Multi(.clk(clk),.rst(rest), .en(en),.A(dt),.B(varI),.busy(ready),.R(varS));\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43856783/j1_soc/hdl/Position,data/full_repos/permissive/43856783/booth_mult\n             data/full_repos/permissive/43856783/j1_soc/hdl/Position,data/full_repos/permissive/43856783/booth_mult.v\n             data/full_repos/permissive/43856783/j1_soc/hdl/Position,data/full_repos/permissive/43856783/booth_mult.sv\n             booth_mult\n             booth_mult.v\n             booth_mult.sv\n             obj_dir/booth_mult\n             obj_dir/booth_mult.v\n             obj_dir/booth_mult.sv\n%Warning-WIDTH: data/full_repos/permissive/43856783/j1_soc/hdl/Position/Integradorv2.v:89: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                         : ... In instance Integradorv2\n     varI <= 1\'d0;\n          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/43856783/j1_soc/hdl/Position/Integradorv2.v:103: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'a\' generates 16 bits.\n                                                                                          : ... In instance Integradorv2\n     varI <= a;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/43856783/j1_soc/hdl/Position/Integradorv2.v:112: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'a\' generates 16 bits.\n                                                                                          : ... In instance Integradorv2\n     varI <= a;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/43856783/j1_soc/hdl/Position/Integradorv2.v:129: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'a\' generates 16 bits.\n                                                                                          : ... In instance Integradorv2\n   varI <= a;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/43856783/j1_soc/hdl/Position/Integradorv2.v:142: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'a\' generates 16 bits.\n                                                                                          : ... In instance Integradorv2\n     varI <= a;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/43856783/j1_soc/hdl/Position/Integradorv2.v:153: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'a\' generates 16 bits.\n                                                                                          : ... In instance Integradorv2\n     varI <= a;\n          ^~\n%Error: Exiting due to 1 error(s), 6 warning(s)\n'
module Integradorv2(
    input [15:0] a,
    input [15:0] dt,
    input enable,
    input rst,
    input clk,
    output reg [31:0] v,
    output reg busy
    );
	 	
	 wire ready;
	 reg en;
	 reg [31:0] pv;
	 reg [31:0] vd;
	 reg [31:0] pvd;
	 reg [31:0] varI;
	 wire [31:0] varS;
	 reg rest;
	 initial rest <= 1'b1;
	 initial v = 32'h0000;
	 	 booth_mult Multi(.clk(clk),.rst(rest), .en(en),.A(dt),.B(varI),.busy(ready),.R(varS));
	 

	
	 
	 
	 	 localparam 
						reset 	= 5'd0,
						ini	   = 5'd1,
						mulv		= 5'd2,
						check_1  = 5'd3,
						afterv	= 5'd4,
						end_state= 5'd5;
						
						

						

	 reg[4:0] state;
	 reg[4:0] next_state;
	 
	 initial state = 0;
	 initial next_state = 0;
	 
	 
	 
	 always @(posedge clk)begin
	  if(rst) state <= reset;
	  else state <= next_state;  
	 end
	
	always @(*)begin
		case(state)
			reset: begin
				 v  <= 32'd0;
				 pv <= 32'd0;
				 busy <= 1'd1;
				 en <= 1'd0;
				 varI <= 32'd0;
				 rest <= 1'd1;
				 next_state <= ini;
			end
			
			ini: begin
				 busy <= 1'd0;
				 v  <= vd;
				 pv <= pvd;
				 en <= 1'd0;
				 varI <= 1'd0;
				 rest <= 1'd1;
				
				if (!enable) next_state <= ini;
					else 		next_state <= mulv;
			
			end
			
			mulv: begin
				 v  <= vd;
				 pv <= pvd;
			  	 busy <= 1'd1;
				 en <= 1'b1;
				 rest <=1'b0;
				 varI <= a;
				 next_state <= check_1;
			end
			
			check_1: begin
				 v  <= vd;
			  	 busy <= 1'd1;
				 en <= 1'b0;
				 rest <= 1'b0;
				 varI <= a;
			
				if (!ready) begin
				next_state <= afterv;
				pv <= v + varS;
				end
					else begin
					pv <= pvd;
					next_state <= check_1;
					end
					
			end
			
			afterv: begin
			v  <= vd;
			pv <= pvd;
			busy <= 1'd1;
			varI <= a;
			
			rest <= 1'b1;
			en <= 1'd0;
			next_state <= end_state;
				
			end
						
			end_state:begin
				
				 pv <= pvd;
				 en <= 1'd0;
				 rest <=1'b1;
				 varI <= a;
				 v <= pv;
				 busy <= 1'd0;
					if (!enable) next_state <= end_state;
					else 		next_state <= ini;
			end
			
			default: begin
				 pv <= pvd;
				 en <= 1'd0;
				 rest <= 1'b1;
				 varI <= a;
				 v <= vd;
				 busy <= 1'd0;
				 next_state <= ini;
			end
		endcase
	 end
	 
	always @(negedge clk)begin
	pvd <= pv;
	vd <= v;
	end

endmodule
module Integradorv2(
    input [15:0] a,
    input [15:0] dt,
    input enable,
    input rst,
    input clk,
    output reg [31:0] v,
    output reg busy
    );

	 	
	 wire ready;
	 reg en;
	 reg [31:0] pv;
	 reg [31:0] vd;
	 reg [31:0] pvd;
	 reg [31:0] varI;
	 wire [31:0] varS;
	 reg rest;
	 initial rest <= 1'b1;
	 initial v = 32'h0000;
	 	 booth_mult Multi(.clk(clk),.rst(rest), .en(en),.A(dt),.B(varI),.busy(ready),.R(varS));
	 

	
	 
	 
	 	 localparam 
						reset 	= 5'd0,
						ini	   = 5'd1,
						mulv		= 5'd2,
						check_1  = 5'd3,
						afterv	= 5'd4,
						end_state= 5'd5;
						
						

						

	 reg[4:0] state;
	 reg[4:0] next_state;
	 
	 initial state = 0;
	 initial next_state = 0;
	 
	 
	 
	 always @(posedge clk)begin
	  if(rst) state <= reset;
	  else state <= next_state;  
	 end
	
	always @(*)begin
		case(state)
			reset: begin
				 v  <= 32'd0;
				 pv <= 32'd0;
				 busy <= 1'd1;
				 en <= 1'd0;
				 varI <= 32'd0;
				 rest <= 1'd1;
				 next_state <= ini;
			end
			
			ini: begin
				 busy <= 1'd0;
				 v  <= vd;
				 pv <= pvd;
				 en <= 1'd0;
				 varI <= 1'd0;
				 rest <= 1'd1;
				
				if (!enable) next_state <= ini;
					else 		next_state <= mulv;
			
			end
			
			mulv: begin
				 v  <= vd;
				 pv <= pvd;
			  	 busy <= 1'd1;
				 en <= 1'b1;
				 rest <=1'b0;
				 varI <= a;
				 next_state <= check_1;
			end
			
			check_1: begin
				 v  <= vd;
			  	 busy <= 1'd1;
				 en <= 1'b0;
				 rest <= 1'b0;
				 varI <= a;
			
				if (!ready) begin
				next_state <= afterv;
				pv <= v + varS;
				end
					else begin
					pv <= pvd;
					next_state <= check_1;
					end
					
			end
			
			afterv: begin
			v  <= vd;
			pv <= pvd;
			busy <= 1'd1;
			varI <= a;
			
			rest <= 1'b1;
			en <= 1'd0;
			next_state <= end_state;
				
			end
						
			end_state:begin
				
				 pv <= pvd;
				 en <= 1'd0;
				 rest <=1'b1;
				 varI <= a;
				 v <= pv;
				 busy <= 1'd0;
					if (!enable) next_state <= end_state;
					else 		next_state <= ini;
			end
			
			default: begin
				 pv <= pvd;
				 en <= 1'd0;
				 rest <= 1'b1;
				 varI <= a;
				 v <= vd;
				 busy <= 1'd0;
				 next_state <= ini;
			end
		endcase
	 end
	 
	always @(negedge clk)begin
	pvd <= pv;
	vd <= v;
	end

endmodule