data/full_repos/permissive/435012493/CU.v
data/verilator_xmls/efaf1bb8-ed3a-474d-b6a7-1b2d3230883e.xml
module CU(input GO, RST, clk, counterStatus, input [1:0] Pbits,
output reg [1:0] CS, output reg pSel, addSel, addResSel, enC, enA, enS, enP, count, done);
reg [1:0] NS;

always@(CS,GO,counterStatus)
begin
case(CS)
0: NS = GO ? 2'b01:2'b00;
1: NS = 2'd2;
2: NS = (counterStatus) ? (2'd2):(2'd3);
3: NS = 2'b00;
default: NS = 2'b00;
endcase
end

always@(posedge clk, posedge RST)
begin
CS <= RST? 0:NS;
end


always@(CS,Pbits)
begin
  case(CS)
  0: {addSel, addResSel, pSel, enC, enA, enS, enP, done, count} = 9'b000_1000_00;
  1: {addSel, addResSel, pSel, enC, enA, enS, enP, done, count} = 9'b000_0111_00;
  2: begin
    case(Pbits)
    1:{addSel, addResSel, pSel, enC, enA, enS, enP, done, count} = 9'b101_0001_01;
    2:{addSel, addResSel, pSel, enC, enA, enS, enP, done, count} = 9'b001_0001_01;
    default:
    {addSel, addResSel, pSel, enC, enA, enS, enP, done, count}= 9'b011_0001_01;
    endcase
    end
  3: {addSel, addResSel, pSel, enC, enA, enS, enP, done, count}= 9'b000_0000_10;
  default:
  {addSel, addResSel, pSel, enC, enA, enS, enP, done, count} = 9'b000_0000_00;
  endcase
end
endmodule
module CU(input GO, RST, clk, counterStatus, input [1:0] Pbits,
output reg [1:0] CS, output reg pSel, addSel, addResSel, enC, enA, enS, enP, count, done);

reg [1:0] NS;

always@(CS,GO,counterStatus)
begin
case(CS)
0: NS = GO ? 2'b01:2'b00;
1: NS = 2'd2;
2: NS = (counterStatus) ? (2'd2):(2'd3);
3: NS = 2'b00;
default: NS = 2'b00;
endcase
end

always@(posedge clk, posedge RST)
begin
CS <= RST? 0:NS;
end


always@(CS,Pbits)
begin
  case(CS)
  0: {addSel, addResSel, pSel, enC, enA, enS, enP, done, count} = 9'b000_1000_00;
  1: {addSel, addResSel, pSel, enC, enA, enS, enP, done, count} = 9'b000_0111_00;
  2: begin
    case(Pbits)
    1:{addSel, addResSel, pSel, enC, enA, enS, enP, done, count} = 9'b101_0001_01;
    2:{addSel, addResSel, pSel, enC, enA, enS, enP, done, count} = 9'b001_0001_01;
    default:
    {addSel, addResSel, pSel, enC, enA, enS, enP, done, count}= 9'b011_0001_01;
    endcase
    end
  3: {addSel, addResSel, pSel, enC, enA, enS, enP, done, count}= 9'b000_0000_10;
  default:
  {addSel, addResSel, pSel, enC, enA, enS, enP, done, count} = 9'b000_0000_00;
  endcase
end
endmodule