data/full_repos/permissive/423547971/FPGA Projects/PmodENC/debounce.v
1: b'%Error: Cannot find file containing module: Projects/PmodENC,data/full_repos/permissive/423547971\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/PmodENC,data/full_repos/permissive/423547971\n             data/full_repos/permissive/423547971/FPGA/Projects/PmodENC,data/full_repos/permissive/423547971.v\n             data/full_repos/permissive/423547971/FPGA/Projects/PmodENC,data/full_repos/permissive/423547971.sv\n             Projects/PmodENC,data/full_repos/permissive/423547971\n             Projects/PmodENC,data/full_repos/permissive/423547971.v\n             Projects/PmodENC,data/full_repos/permissive/423547971.sv\n             obj_dir/Projects/PmodENC,data/full_repos/permissive/423547971\n             obj_dir/Projects/PmodENC,data/full_repos/permissive/423547971.v\n             obj_dir/Projects/PmodENC,data/full_repos/permissive/423547971.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: Projects/PmodENC/debounce.v\n%Error: Exiting due to 3 error(s)\n'
module debounce(
    input clk,
    input Ain,
    input Bin,
    output Aout,
    output Bout
    );




	 reg r_Aout = 0;
	 reg r_Bout = 0;

	 reg [6:0] sclk = 0;
	 reg sampledA = 0;
	 reg sampledB = 0;
	 



	 always @(posedge clk) begin
			sampledA <= Ain;
			sampledB <= Bin;



			
			if(sclk == 100) begin
					if(sampledA == Ain) begin
							r_Aout <= Ain;
					end
					
					if(sampledB == Bin) begin
							r_Bout <= Bin;
					end
					
					sclk <= 0;
			end
			else begin
					sclk <= sclk + 1;
			end
	 end

    assign Aout = r_Aout;
    assign Bout = r_Bout;

endmodule
module debounce(
    input clk,
    input Ain,
    input Bin,
    output Aout,
    output Bout
    );





	 reg r_Aout = 0;
	 reg r_Bout = 0;

	 reg [6:0] sclk = 0;
	 reg sampledA = 0;
	 reg sampledB = 0;
	 



	 always @(posedge clk) begin
			sampledA <= Ain;
			sampledB <= Bin;



			
			if(sclk == 100) begin
					if(sampledA == Ain) begin
							r_Aout <= Ain;
					end
					
					if(sampledB == Bin) begin
							r_Bout <= Bin;
					end
					
					sclk <= 0;
			end
			else begin
					sclk <= sclk + 1;
			end
	 end

    assign Aout = r_Aout;
    assign Bout = r_Bout;

endmodule