data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:98: Unsupported: Ignoring delay on this delayed statement.\n      #CLK_HALF_PERIOD tb_clk = !tb_clk;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:107: Unsupported: Ignoring delay on this delayed statement.\n      #(CLK_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:170: Unsupported: Ignoring delay on this delayed statement.\n      #(4 * CLK_HALF_PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:229: Unsupported: Ignoring delay on this delayed statement.\n          #(CLK_PERIOD);\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:250: Unsupported: Ignoring delay on this delayed statement.\n     #(CLK_PERIOD);\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:294: Unsupported: Ignoring delay on this delayed statement.\n     #(CLK_PERIOD);\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:303: Unsupported: Ignoring delay on this delayed statement.\n     #(CLK_PERIOD);\n     ^\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:126: Can\'t find definition of \'init\' in dotted variable: \'dut.init\'\n               dut.init, dut.next);\n                   ^~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:126: Can\'t find definition of \'next\' in dotted variable: \'dut.next\'\n               dut.init, dut.next);\n                             ^~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:127: Can\'t find definition of \'block\' in dotted variable: \'dut.block\'\n      $display("block  = 0x%0128x", dut.block);\n                                        ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:130: Can\'t find definition of \'ready\' in dotted variable: \'dut.ready\'\n               dut.ready, dut.digest_valid);\n                   ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:130: Can\'t find definition of \'digest_valid\' in dotted variable: \'dut.digest_valid\'\n               dut.ready, dut.digest_valid);\n                              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:131: Can\'t find definition of \'digest\' in dotted variable: \'dut.digest\'\n      $display("digest = 0x%040x", dut.digest);\n                                       ^~~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:133: Can\'t find definition of \'H0_reg\' in dotted variable: \'dut.H0_reg\'\n               dut.H0_reg, dut.H1_reg, dut.H2_reg, dut.H3_reg, dut.H4_reg);\n                   ^~~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:133: Can\'t find definition of \'H1_reg\' in dotted variable: \'dut.H1_reg\'\n               dut.H0_reg, dut.H1_reg, dut.H2_reg, dut.H3_reg, dut.H4_reg);\n                               ^~~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:133: Can\'t find definition of \'H2_reg\' in dotted variable: \'dut.H2_reg\'\n               dut.H0_reg, dut.H1_reg, dut.H2_reg, dut.H3_reg, dut.H4_reg);\n                                           ^~~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:133: Can\'t find definition of \'H3_reg\' in dotted variable: \'dut.H3_reg\'\n               dut.H0_reg, dut.H1_reg, dut.H2_reg, dut.H3_reg, dut.H4_reg);\n                                                       ^~~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:133: Can\'t find definition of \'H4_reg\' in dotted variable: \'dut.H4_reg\'\n               dut.H0_reg, dut.H1_reg, dut.H2_reg, dut.H3_reg, dut.H4_reg);\n                                                                   ^~~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:137: Can\'t find definition of \'sha1_ctrl_reg\' in dotted variable: \'dut.sha1_ctrl_reg\'\n      $display("sha1_ctrl_reg = 0x%01x", dut.sha1_ctrl_reg);\n                                             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:139: Can\'t find definition of \'digest_init\' in dotted variable: \'dut.digest_init\'\n               dut.digest_init, dut.digest_update);\n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:139: Can\'t find definition of \'digest_update\' in dotted variable: \'dut.digest_update\'\n               dut.digest_init, dut.digest_update);\n                                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:141: Can\'t find definition of \'state_init\' in dotted variable: \'dut.state_init\'\n               dut.state_init, dut.state_update);\n                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:141: Can\'t find definition of \'state_update\' in dotted variable: \'dut.state_update\'\n               dut.state_init, dut.state_update);\n                                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:143: Can\'t find definition of \'first_block\' in dotted variable: \'dut.first_block\'\n               dut.first_block, dut.ready_flag, dut.w_init);\n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:143: Can\'t find definition of \'ready_flag\' in dotted variable: \'dut.ready_flag\'\n               dut.first_block, dut.ready_flag, dut.w_init);\n                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:143: Can\'t find definition of \'w_init\' in dotted variable: \'dut.w_init\'\n               dut.first_block, dut.ready_flag, dut.w_init);\n                                                    ^~~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:145: Can\'t find definition of \'round_ctr_inc\' in dotted variable: \'dut.round_ctr_inc\'\n               dut.round_ctr_inc, dut.round_ctr_rst, dut.round_ctr_reg);\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:145: Can\'t find definition of \'round_ctr_rst\' in dotted variable: \'dut.round_ctr_rst\'\n               dut.round_ctr_inc, dut.round_ctr_rst, dut.round_ctr_reg);\n                                      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:145: Can\'t find definition of \'round_ctr_reg\' in dotted variable: \'dut.round_ctr_reg\'\n               dut.round_ctr_inc, dut.round_ctr_rst, dut.round_ctr_reg);\n                                                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:150: Can\'t find definition of \'a_reg\' in dotted variable: \'dut.a_reg\'\n               dut.a_reg, dut.b_reg, dut.c_reg, dut.d_reg,  dut.e_reg);\n                   ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:150: Can\'t find definition of \'b_reg\' in dotted variable: \'dut.b_reg\'\n               dut.a_reg, dut.b_reg, dut.c_reg, dut.d_reg,  dut.e_reg);\n                              ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:150: Can\'t find definition of \'c_reg\' in dotted variable: \'dut.c_reg\'\n               dut.a_reg, dut.b_reg, dut.c_reg, dut.d_reg,  dut.e_reg);\n                                         ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:150: Can\'t find definition of \'d_reg\' in dotted variable: \'dut.d_reg\'\n               dut.a_reg, dut.b_reg, dut.c_reg, dut.d_reg,  dut.e_reg);\n                                                    ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:150: Can\'t find definition of \'e_reg\' in dotted variable: \'dut.e_reg\'\n               dut.a_reg, dut.b_reg, dut.c_reg, dut.d_reg,  dut.e_reg);\n                                                                ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:152: Can\'t find definition of \'a_new\' in dotted variable: \'dut.a_new\'\n               dut.a_new, dut.b_new, dut.c_new, dut.d_new, dut.e_new);\n                   ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:152: Can\'t find definition of \'b_new\' in dotted variable: \'dut.b_new\'\n               dut.a_new, dut.b_new, dut.c_new, dut.d_new, dut.e_new);\n                              ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:152: Can\'t find definition of \'c_new\' in dotted variable: \'dut.c_new\'\n               dut.a_new, dut.b_new, dut.c_new, dut.d_new, dut.e_new);\n                                         ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:152: Can\'t find definition of \'d_new\' in dotted variable: \'dut.d_new\'\n               dut.a_new, dut.b_new, dut.c_new, dut.d_new, dut.e_new);\n                                                    ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:152: Can\'t find definition of \'e_new\' in dotted variable: \'dut.e_new\'\n               dut.a_new, dut.b_new, dut.c_new, dut.d_new, dut.e_new);\n                                                               ^~~~~\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:157: Can\'t find definition of \'state_logic\' in dotted scope/variable: \'dut.state_logic\'\n               dut.state_logic.f, dut.state_logic.k, dut.state_logic.t, dut.w);\n                   ^~~~~~~~~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:157: Can\'t find definition of \'state_logic\' in dotted scope/variable: \'dut.state_logic\'\n               dut.state_logic.f, dut.state_logic.k, dut.state_logic.t, dut.w);\n                                      ^~~~~~~~~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:157: Can\'t find definition of \'state_logic\' in dotted scope/variable: \'dut.state_logic\'\n               dut.state_logic.f, dut.state_logic.k, dut.state_logic.t, dut.w);\n                                                         ^~~~~~~~~~~\n        ... Known scopes under \'dut\': <no cells found>\n%Error: data/full_repos/permissive/47537295/src/sha1-master/src/tb/tb_sha1_core.v:157: Can\'t find definition of \'w\' in dotted variable: \'dut.w\'\n               dut.state_logic.f, dut.state_logic.k, dut.state_logic.t, dut.w);\n                                                                            ^\n%Error: Exiting due to 36 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_sha1_core();




  parameter DEBUG = 0;

  parameter CLK_HALF_PERIOD = 1;
  parameter CLK_PERIOD = CLK_HALF_PERIOD * 2;





  reg [31 : 0] cycle_ctr;
  reg [31 : 0] error_ctr;
  reg [31 : 0] tc_ctr;

  reg            tb_clk;
  reg            tb_reset_n;
  reg            tb_init;
  reg            tb_next;
  reg [511 : 0]  tb_block;
  wire           tb_ready;
  wire [159 : 0] tb_digest;
  wire           tb_digest_valid;






  sha1_core dut(
                   .clk(tb_clk),
                   .reset_n(tb_reset_n),

                   .init(tb_init),
                   .next(tb_next),

                   .block(tb_block),

                   .ready(tb_ready),

                   .digest(tb_digest),
                   .digest_valid(tb_digest_valid)
                 );







  always
    begin : clk_gen
      #CLK_HALF_PERIOD tb_clk = !tb_clk;
    end





  always
    begin : sys_monitor
      #(CLK_PERIOD);
      if (DEBUG)
        begin
          dump_dut_state();
        end
    end







  task dump_dut_state();
    begin
      $display("State of DUT");
      $display("------------");
      $display("Inputs and outputs:");
      $display("init   = 0x%01x, next  = 0x%01x",
               dut.init, dut.next);
      $display("block  = 0x%0128x", dut.block);

      $display("ready  = 0x%01x, valid = 0x%01x",
               dut.ready, dut.digest_valid);
      $display("digest = 0x%040x", dut.digest);
      $display("H0_reg = 0x%08x, H1_reg = 0x%08x, H2_reg = 0x%08x, H3_reg = 0x%08x, H4_reg = 0x%08x",
               dut.H0_reg, dut.H1_reg, dut.H2_reg, dut.H3_reg, dut.H4_reg);
      $display("");

      $display("Control signals and counter:");
      $display("sha1_ctrl_reg = 0x%01x", dut.sha1_ctrl_reg);
      $display("digest_init   = 0x%01x, digest_update = 0x%01x",
               dut.digest_init, dut.digest_update);
      $display("state_init    = 0x%01x, state_update  = 0x%01x",
               dut.state_init, dut.state_update);
      $display("first_block   = 0x%01x, ready_flag    = 0x%01x, w_init        = 0x%01x",
               dut.first_block, dut.ready_flag, dut.w_init);
      $display("round_ctr_inc = 0x%01x, round_ctr_rst = 0x%01x, round_ctr_reg = 0x%02x",
               dut.round_ctr_inc, dut.round_ctr_rst, dut.round_ctr_reg);
      $display("");

      $display("State registers:");
      $display("a_reg = 0x%08x, b_reg = 0x%08x, c_reg = 0x%08x, d_reg = 0x%08x, e_reg = 0x%08x",
               dut.a_reg, dut.b_reg, dut.c_reg, dut.d_reg,  dut.e_reg);
      $display("a_new = 0x%08x, b_new = 0x%08x, c_new = 0x%08x, d_new = 0x%08x, e_new = 0x%08x",
               dut.a_new, dut.b_new, dut.c_new, dut.d_new, dut.e_new);
      $display("");

      $display("State update values:");
      $display("f = 0x%08x, k = 0x%08x, t = 0x%08x, w = 0x%08x,",
               dut.state_logic.f, dut.state_logic.k, dut.state_logic.t, dut.w);
      $display("");
    end
  endtask





  task reset_dut();
    begin
      $display("*** Toggle reset.");
      tb_reset_n = 0;
      #(4 * CLK_HALF_PERIOD);
      tb_reset_n = 1;
    end
  endtask








  task init_sim();
    begin
      error_ctr = 0;
      tc_ctr = 0;

      tb_clk = 0;
      tb_reset_n = 1;

      tb_init = 0;
      tb_next = 0;
      tb_block = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
    end
  endtask







  task display_test_result();
    begin
      if (error_ctr == 0)
        begin
          $display("*** All %02d test cases completed successfully", tc_ctr);
        end
      else
        begin
          $display("*** %02d test cases did not complete successfully.", error_ctr);
        end
    end
  endtask











  task wait_ready();
    begin
      while (!tb_ready)
        begin
          #(CLK_PERIOD);

        end
    end
  endtask







  task single_block_test(input [7 : 0]   tc_number,
                         input [511 : 0] block,
                         input [159 : 0] expected);
   begin
     $display("*** TC %0d single block test case started.", tc_number);
     tc_ctr = tc_ctr + 1;

     tb_block = block;
     tb_init = 1;
     #(CLK_PERIOD);
     tb_init = 0;
     wait_ready();


     if (tb_digest == expected)
       begin
         $display("*** TC %0d successful.", tc_number);
         $display("");
       end
     else
       begin
         $display("*** ERROR: TC %0d NOT successful.", tc_number);
         $display("Expected: 0x%040x", expected);
         $display("Got:      0x%040x", tb_digest);
         $display("");

         error_ctr = error_ctr + 1;
       end
   end
  endtask







  task double_block_test(input [7 : 0]   tc_number,
                         input [511 : 0] block1,
                         input [159 : 0] expected1,
                         input [511 : 0] block2,
                         input [159 : 0] expected2);

     reg [159 : 0] db_digest1;
     reg           db_error;
   begin
     $display("*** TC %0d double block test case started.", tc_number);
     db_error = 0;
     tc_ctr = tc_ctr + 1;

     $display("*** TC %0d first block started.", tc_number);
     tb_block = block1;
     tb_init = 1;
     #(CLK_PERIOD);
     tb_init = 0;
     wait_ready();
     db_digest1 = tb_digest;
     $display("*** TC %0d first block done.", tc_number);

     $display("*** TC %0d second block started.", tc_number);
     tb_block = block2;
     tb_next = 1;
     #(CLK_PERIOD);
     tb_next = 0;
     wait_ready();
     $display("*** TC %0d second block done.", tc_number);

     if (db_digest1 == expected1)
       begin
         $display("*** TC %0d first block successful", tc_number);
         $display("");
       end
     else
       begin
         $display("*** ERROR: TC %0d first block NOT successful", tc_number);
         $display("Expected: 0x%040x", expected1);
         $display("Got:      0x%040x", db_digest1);
         $display("");
         db_error = 1;
       end

     if (db_digest1 == expected1)
       begin
         $display("*** TC %0d second block successful", tc_number);
         $display("");
       end
     else
       begin
         $display("*** ERROR: TC %0d second block NOT successful", tc_number);
         $display("Expected: 0x%040x", expected2);
         $display("Got:      0x%040x", tb_digest);
         $display("");
         db_error = 1;
       end

     if (db_error)
       begin
         error_ctr = error_ctr + 1;
       end
   end
  endtask









  initial
    begin : sha1_core_test
      reg [511 : 0] tc1;
      reg [159 : 0] res1;

      reg [511 : 0] tc2_1;
      reg [159 : 0] res2_1;
      reg [511 : 0] tc2_2;
      reg [159 : 0] res2_2;

      $display("   -- Testbench for sha1 core started --");

      init_sim();
      dump_dut_state();
      reset_dut();
      dump_dut_state();


      tc1 = 512'h61626380000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018;
      res1 = 160'ha9993e364706816aba3e25717850c26c9cd0d89d;

      single_block_test(1, tc1, res1);



      tc2_1 = 512'h6162636462636465636465666465666765666768666768696768696A68696A6B696A6B6C6A6B6C6D6B6C6D6E6C6D6E6F6D6E6F706E6F70718000000000000000;
      res2_1 = 160'hf4286818c37b27ae0408f581846771484a566572;
		
		

      tc2_2 = 512'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001C0;
      res2_2 = 160'h84983e441c3bd26ebaae4aa1f95129e5e54670f1;
      double_block_test(2, tc2_1, res2_1, tc2_2, res2_2);

      display_test_result();
      $display("*** Simulation done.");
      $finish;
    end
endmodule
module tb_sha1_core();





  parameter DEBUG = 0;

  parameter CLK_HALF_PERIOD = 1;
  parameter CLK_PERIOD = CLK_HALF_PERIOD * 2;





  reg [31 : 0] cycle_ctr;
  reg [31 : 0] error_ctr;
  reg [31 : 0] tc_ctr;

  reg            tb_clk;
  reg            tb_reset_n;
  reg            tb_init;
  reg            tb_next;
  reg [511 : 0]  tb_block;
  wire           tb_ready;
  wire [159 : 0] tb_digest;
  wire           tb_digest_valid;






  sha1_core dut(
                   .clk(tb_clk),
                   .reset_n(tb_reset_n),

                   .init(tb_init),
                   .next(tb_next),

                   .block(tb_block),

                   .ready(tb_ready),

                   .digest(tb_digest),
                   .digest_valid(tb_digest_valid)
                 );







  always
    begin : clk_gen
      #CLK_HALF_PERIOD tb_clk = !tb_clk;
    end





  always
    begin : sys_monitor
      #(CLK_PERIOD);
      if (DEBUG)
        begin
          dump_dut_state();
        end
    end







  task dump_dut_state();
    begin
      $display("State of DUT");
      $display("------------");
      $display("Inputs and outputs:");
      $display("init   = 0x%01x, next  = 0x%01x",
               dut.init, dut.next);
      $display("block  = 0x%0128x", dut.block);

      $display("ready  = 0x%01x, valid = 0x%01x",
               dut.ready, dut.digest_valid);
      $display("digest = 0x%040x", dut.digest);
      $display("H0_reg = 0x%08x, H1_reg = 0x%08x, H2_reg = 0x%08x, H3_reg = 0x%08x, H4_reg = 0x%08x",
               dut.H0_reg, dut.H1_reg, dut.H2_reg, dut.H3_reg, dut.H4_reg);
      $display("");

      $display("Control signals and counter:");
      $display("sha1_ctrl_reg = 0x%01x", dut.sha1_ctrl_reg);
      $display("digest_init   = 0x%01x, digest_update = 0x%01x",
               dut.digest_init, dut.digest_update);
      $display("state_init    = 0x%01x, state_update  = 0x%01x",
               dut.state_init, dut.state_update);
      $display("first_block   = 0x%01x, ready_flag    = 0x%01x, w_init        = 0x%01x",
               dut.first_block, dut.ready_flag, dut.w_init);
      $display("round_ctr_inc = 0x%01x, round_ctr_rst = 0x%01x, round_ctr_reg = 0x%02x",
               dut.round_ctr_inc, dut.round_ctr_rst, dut.round_ctr_reg);
      $display("");

      $display("State registers:");
      $display("a_reg = 0x%08x, b_reg = 0x%08x, c_reg = 0x%08x, d_reg = 0x%08x, e_reg = 0x%08x",
               dut.a_reg, dut.b_reg, dut.c_reg, dut.d_reg,  dut.e_reg);
      $display("a_new = 0x%08x, b_new = 0x%08x, c_new = 0x%08x, d_new = 0x%08x, e_new = 0x%08x",
               dut.a_new, dut.b_new, dut.c_new, dut.d_new, dut.e_new);
      $display("");

      $display("State update values:");
      $display("f = 0x%08x, k = 0x%08x, t = 0x%08x, w = 0x%08x,",
               dut.state_logic.f, dut.state_logic.k, dut.state_logic.t, dut.w);
      $display("");
    end
  endtask





  task reset_dut();
    begin
      $display("*** Toggle reset.");
      tb_reset_n = 0;
      #(4 * CLK_HALF_PERIOD);
      tb_reset_n = 1;
    end
  endtask








  task init_sim();
    begin
      error_ctr = 0;
      tc_ctr = 0;

      tb_clk = 0;
      tb_reset_n = 1;

      tb_init = 0;
      tb_next = 0;
      tb_block = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
    end
  endtask







  task display_test_result();
    begin
      if (error_ctr == 0)
        begin
          $display("*** All %02d test cases completed successfully", tc_ctr);
        end
      else
        begin
          $display("*** %02d test cases did not complete successfully.", error_ctr);
        end
    end
  endtask











  task wait_ready();
    begin
      while (!tb_ready)
        begin
          #(CLK_PERIOD);

        end
    end
  endtask







  task single_block_test(input [7 : 0]   tc_number,
                         input [511 : 0] block,
                         input [159 : 0] expected);
   begin
     $display("*** TC %0d single block test case started.", tc_number);
     tc_ctr = tc_ctr + 1;

     tb_block = block;
     tb_init = 1;
     #(CLK_PERIOD);
     tb_init = 0;
     wait_ready();


     if (tb_digest == expected)
       begin
         $display("*** TC %0d successful.", tc_number);
         $display("");
       end
     else
       begin
         $display("*** ERROR: TC %0d NOT successful.", tc_number);
         $display("Expected: 0x%040x", expected);
         $display("Got:      0x%040x", tb_digest);
         $display("");

         error_ctr = error_ctr + 1;
       end
   end
  endtask







  task double_block_test(input [7 : 0]   tc_number,
                         input [511 : 0] block1,
                         input [159 : 0] expected1,
                         input [511 : 0] block2,
                         input [159 : 0] expected2);

     reg [159 : 0] db_digest1;
     reg           db_error;
   begin
     $display("*** TC %0d double block test case started.", tc_number);
     db_error = 0;
     tc_ctr = tc_ctr + 1;

     $display("*** TC %0d first block started.", tc_number);
     tb_block = block1;
     tb_init = 1;
     #(CLK_PERIOD);
     tb_init = 0;
     wait_ready();
     db_digest1 = tb_digest;
     $display("*** TC %0d first block done.", tc_number);

     $display("*** TC %0d second block started.", tc_number);
     tb_block = block2;
     tb_next = 1;
     #(CLK_PERIOD);
     tb_next = 0;
     wait_ready();
     $display("*** TC %0d second block done.", tc_number);

     if (db_digest1 == expected1)
       begin
         $display("*** TC %0d first block successful", tc_number);
         $display("");
       end
     else
       begin
         $display("*** ERROR: TC %0d first block NOT successful", tc_number);
         $display("Expected: 0x%040x", expected1);
         $display("Got:      0x%040x", db_digest1);
         $display("");
         db_error = 1;
       end

     if (db_digest1 == expected1)
       begin
         $display("*** TC %0d second block successful", tc_number);
         $display("");
       end
     else
       begin
         $display("*** ERROR: TC %0d second block NOT successful", tc_number);
         $display("Expected: 0x%040x", expected2);
         $display("Got:      0x%040x", tb_digest);
         $display("");
         db_error = 1;
       end

     if (db_error)
       begin
         error_ctr = error_ctr + 1;
       end
   end
  endtask









  initial
    begin : sha1_core_test
      reg [511 : 0] tc1;
      reg [159 : 0] res1;

      reg [511 : 0] tc2_1;
      reg [159 : 0] res2_1;
      reg [511 : 0] tc2_2;
      reg [159 : 0] res2_2;

      $display("   -- Testbench for sha1 core started --");

      init_sim();
      dump_dut_state();
      reset_dut();
      dump_dut_state();


      tc1 = 512'h61626380000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018;
      res1 = 160'ha9993e364706816aba3e25717850c26c9cd0d89d;

      single_block_test(1, tc1, res1);



      tc2_1 = 512'h6162636462636465636465666465666765666768666768696768696A68696A6B696A6B6C6A6B6C6D6B6C6D6E6C6D6E6F6D6E6F706E6F70718000000000000000;
      res2_1 = 160'hf4286818c37b27ae0408f581846771484a566572;
		
		

      tc2_2 = 512'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001C0;
      res2_2 = 160'h84983e441c3bd26ebaae4aa1f95129e5e54670f1;
      double_block_test(2, tc2_1, res2_1, tc2_2, res2_2);

      display_test_result();
      $display("*** Simulation done.");
      $finish;
    end
endmodule