data/full_repos/permissive/448627443/Peripherals/APB_UART/RTL/UART.v
data/verilator_xmls/7840526d-fdcf-42be-abd3-2afae07c246c.xml
module UART_RX (
  input               io_tick,
  output reg          io_data_valid,
  input               io_data_ready,
  output reg [7:0]    io_data_payload,
  input               io_rxd,
  output              io_busy,
  input               clk,
  input               resetn
);
  reg        [2:0]    subDiv_counter;
  reg                 subDiv_tick;
  wire                when_UART_RX_l33;
  reg        [2:0]    bitCnt_value;
  reg        [2:0]    keeper_counter;
  reg                 keeper_rxk;
  wire                when_UART_RX_l55;
  wire                when_UART_RX_l57;
  reg        `UartState_1_binary_sequential_type stateMac_state;
  wire                when_UART_RX_l75;
  wire                when_UART_RX_l88;
  wire                when_UART_RX_l102;
  reg                 lState;
  `ifndef SYNTHESIS
  reg [39:0] stateMac_state_string;
  `endif


  `ifndef SYNTHESIS
  always @(*) begin
    case(stateMac_state)
      `UartState_1_binary_sequential_IDLE : stateMac_state_string = "IDLE ";
      `UartState_1_binary_sequential_START : stateMac_state_string = "START";
      `UartState_1_binary_sequential_DATA : stateMac_state_string = "DATA ";
      `UartState_1_binary_sequential_STOP : stateMac_state_string = "STOP ";
      default : stateMac_state_string = "?????";
    endcase
  end
  `endif

  assign when_UART_RX_l33 = (subDiv_counter == 3'b000);
  assign when_UART_RX_l55 = (keeper_rxk != io_rxd);
  assign when_UART_RX_l57 = (3'b001 < keeper_counter);
  assign when_UART_RX_l75 = (keeper_rxk == 1'b0);
  assign when_UART_RX_l88 = (bitCnt_value == 3'b111);
  assign when_UART_RX_l102 = (io_data_valid && io_data_ready);
  assign io_busy = ((stateMac_state != `UartState_1_binary_sequential_IDLE) || lState);
  always @(posedge clk or negedge resetn) begin
    if(!resetn) begin
      io_data_payload <= 8'h0;
      io_data_valid <= 1'b0;
      subDiv_counter <= 3'b000;
      keeper_counter <= 3'b000;
      keeper_rxk <= 1'b1;
      stateMac_state <= `UartState_1_binary_sequential_IDLE;
      lState <= 1'b0;
    end else begin
      if(io_tick) begin
        if(when_UART_RX_l33) begin
          subDiv_counter <= 3'b111;
        end else begin
          subDiv_counter <= (subDiv_counter - 3'b001);
        end
      end
      if(io_tick) begin
        if(when_UART_RX_l55) begin
          keeper_counter <= (keeper_counter + 3'b001);
          if(when_UART_RX_l57) begin
            keeper_counter <= 3'b000;
            keeper_rxk <= (! keeper_rxk);
          end
        end else begin
          keeper_counter <= 3'b000;
        end
      end
      case(stateMac_state)
        `UartState_1_binary_sequential_IDLE : begin
          if(when_UART_RX_l75) begin
            subDiv_counter <= 3'b010;
            stateMac_state <= `UartState_1_binary_sequential_START;
          end
        end
        `UartState_1_binary_sequential_START : begin
          if(subDiv_tick) begin
            stateMac_state <= `UartState_1_binary_sequential_DATA;
          end
        end
        `UartState_1_binary_sequential_DATA : begin
          if(subDiv_tick) begin
            if(when_UART_RX_l88) begin
              stateMac_state <= `UartState_1_binary_sequential_STOP;
              io_data_valid <= 1'b1;
            end
            io_data_payload[bitCnt_value] <= keeper_rxk;
          end
        end
        default : begin
          if(subDiv_tick) begin
            stateMac_state <= `UartState_1_binary_sequential_IDLE;
          end
        end
      endcase
      if(when_UART_RX_l102) begin
        io_data_valid <= 1'b0;
      end
      if(subDiv_tick) begin
        lState <= (stateMac_state != `UartState_1_binary_sequential_IDLE);
      end
    end
  end

  always @(posedge clk) begin
    subDiv_tick <= ((subDiv_counter == 3'b000) && io_tick);
    if(subDiv_tick) begin
      bitCnt_value <= (bitCnt_value + 3'b001);
    end
    case(stateMac_state)
      `UartState_1_binary_sequential_IDLE : begin
        if(when_UART_RX_l75) begin
          subDiv_tick <= 1'b0;
        end
      end
      `UartState_1_binary_sequential_START : begin
        if(subDiv_tick) begin
          bitCnt_value <= 3'b000;
        end
      end
      `UartState_1_binary_sequential_DATA : begin
      end
      default : begin
      end
    endcase
  end


endmodule
module UART_RX (
  input               io_tick,
  output reg          io_data_valid,
  input               io_data_ready,
  output reg [7:0]    io_data_payload,
  input               io_rxd,
  output              io_busy,
  input               clk,
  input               resetn
);

  reg        [2:0]    subDiv_counter;
  reg                 subDiv_tick;
  wire                when_UART_RX_l33;
  reg        [2:0]    bitCnt_value;
  reg        [2:0]    keeper_counter;
  reg                 keeper_rxk;
  wire                when_UART_RX_l55;
  wire                when_UART_RX_l57;
  reg        `UartState_1_binary_sequential_type stateMac_state;
  wire                when_UART_RX_l75;
  wire                when_UART_RX_l88;
  wire                when_UART_RX_l102;
  reg                 lState;
  `ifndef SYNTHESIS
  reg [39:0] stateMac_state_string;
  `endif


  `ifndef SYNTHESIS
  always @(*) begin
    case(stateMac_state)
      `UartState_1_binary_sequential_IDLE : stateMac_state_string = "IDLE ";
      `UartState_1_binary_sequential_START : stateMac_state_string = "START";
      `UartState_1_binary_sequential_DATA : stateMac_state_string = "DATA ";
      `UartState_1_binary_sequential_STOP : stateMac_state_string = "STOP ";
      default : stateMac_state_string = "?????";
    endcase
  end
  `endif

  assign when_UART_RX_l33 = (subDiv_counter == 3'b000);
  assign when_UART_RX_l55 = (keeper_rxk != io_rxd);
  assign when_UART_RX_l57 = (3'b001 < keeper_counter);
  assign when_UART_RX_l75 = (keeper_rxk == 1'b0);
  assign when_UART_RX_l88 = (bitCnt_value == 3'b111);
  assign when_UART_RX_l102 = (io_data_valid && io_data_ready);
  assign io_busy = ((stateMac_state != `UartState_1_binary_sequential_IDLE) || lState);
  always @(posedge clk or negedge resetn) begin
    if(!resetn) begin
      io_data_payload <= 8'h0;
      io_data_valid <= 1'b0;
      subDiv_counter <= 3'b000;
      keeper_counter <= 3'b000;
      keeper_rxk <= 1'b1;
      stateMac_state <= `UartState_1_binary_sequential_IDLE;
      lState <= 1'b0;
    end else begin
      if(io_tick) begin
        if(when_UART_RX_l33) begin
          subDiv_counter <= 3'b111;
        end else begin
          subDiv_counter <= (subDiv_counter - 3'b001);
        end
      end
      if(io_tick) begin
        if(when_UART_RX_l55) begin
          keeper_counter <= (keeper_counter + 3'b001);
          if(when_UART_RX_l57) begin
            keeper_counter <= 3'b000;
            keeper_rxk <= (! keeper_rxk);
          end
        end else begin
          keeper_counter <= 3'b000;
        end
      end
      case(stateMac_state)
        `UartState_1_binary_sequential_IDLE : begin
          if(when_UART_RX_l75) begin
            subDiv_counter <= 3'b010;
            stateMac_state <= `UartState_1_binary_sequential_START;
          end
        end
        `UartState_1_binary_sequential_START : begin
          if(subDiv_tick) begin
            stateMac_state <= `UartState_1_binary_sequential_DATA;
          end
        end
        `UartState_1_binary_sequential_DATA : begin
          if(subDiv_tick) begin
            if(when_UART_RX_l88) begin
              stateMac_state <= `UartState_1_binary_sequential_STOP;
              io_data_valid <= 1'b1;
            end
            io_data_payload[bitCnt_value] <= keeper_rxk;
          end
        end
        default : begin
          if(subDiv_tick) begin
            stateMac_state <= `UartState_1_binary_sequential_IDLE;
          end
        end
      endcase
      if(when_UART_RX_l102) begin
        io_data_valid <= 1'b0;
      end
      if(subDiv_tick) begin
        lState <= (stateMac_state != `UartState_1_binary_sequential_IDLE);
      end
    end
  end

  always @(posedge clk) begin
    subDiv_tick <= ((subDiv_counter == 3'b000) && io_tick);
    if(subDiv_tick) begin
      bitCnt_value <= (bitCnt_value + 3'b001);
    end
    case(stateMac_state)
      `UartState_1_binary_sequential_IDLE : begin
        if(when_UART_RX_l75) begin
          subDiv_tick <= 1'b0;
        end
      end
      `UartState_1_binary_sequential_START : begin
        if(subDiv_tick) begin
          bitCnt_value <= 3'b000;
        end
      end
      `UartState_1_binary_sequential_DATA : begin
      end
      default : begin
      end
    endcase
  end


endmodule