data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_escape_id.v
data/verilator_xmls/ce27baa3-0136-4593-94dd-dc9783e50bf9.xml
module \1dff (
q,
\q~ ,
d,
cl$k,
\reset*
);

input d, cl$k, \reset* ;
output q, \q~ ;  

endmodule
module \1dff (
q,
\q~ ,
d,
cl$k,
\reset*
);


input d, cl$k, \reset* ;
output q, \q~ ;  

endmodule