data/full_repos/permissive/481307378/source_files/register_set/regset.v
data/verilator_xmls/c20e16ac-553b-4bf3-ba65-a5a545e952b6.xml
module regset(
    input [31 : 0] D,
    input [4 : 0] A_D,
    input [4 : 0] A_Q0,
    input [4 : 0] A_Q1,
    input write_enable,
    input RES,
    input CLK,
    output [31 : 0] Q0,
    output [31 : 0]  Q1
);



    reg [31 : 0] regs [31 : 1];  
    integer i;


    always @(posedge CLK)
    begin    

        if(RES == 1'b1) begin
            for (i = 1; i < 32; i = i + 1) begin
                regs[i] <= 32'd0;
            end
        end

        else if((write_enable == 1'b1) && (A_D != 5'd0)) begin
            regs[A_D] <= D;
        end         
    end 


    assign Q0 = (A_Q0 != 5'd0) ? regs[A_Q0] : 32'd0;
    assign Q1 = (A_Q1 != 5'd0) ? regs[A_Q1] : 32'd0;

endmodule
module regset(
    input [31 : 0] D,
    input [4 : 0] A_D,
    input [4 : 0] A_Q0,
    input [4 : 0] A_Q1,
    input write_enable,
    input RES,
    input CLK,
    output [31 : 0] Q0,
    output [31 : 0]  Q1
);




    reg [31 : 0] regs [31 : 1];  
    integer i;


    always @(posedge CLK)
    begin    

        if(RES == 1'b1) begin
            for (i = 1; i < 32; i = i + 1) begin
                regs[i] <= 32'd0;
            end
        end

        else if((write_enable == 1'b1) && (A_D != 5'd0)) begin
            regs[A_D] <= D;
        end         
    end 


    assign Q0 = (A_Q0 != 5'd0) ? regs[A_Q0] : 32'd0;
    assign Q1 = (A_Q1 != 5'd0) ? regs[A_Q1] : 32'd0;

endmodule