data/full_repos/permissive/506562943/HDLBits/Verilog Language/More Verilog Features/bcdadd100.v
1: b'%Error: Cannot find file containing module: Language/More\n        ... Looked in:\n             data/full_repos/permissive/506562943/HDLBits/Verilog/Language/More\n             data/full_repos/permissive/506562943/HDLBits/Verilog/Language/More.v\n             data/full_repos/permissive/506562943/HDLBits/Verilog/Language/More.sv\n             Language/More\n             Language/More.v\n             Language/More.sv\n             obj_dir/Language/More\n             obj_dir/Language/More.v\n             obj_dir/Language/More.sv\n%Error: Cannot find file containing module: Verilog\n%Error: Cannot find file containing module: Features,data/full_repos/permissive/506562943\n%Error: Cannot find file containing module: data/full_repos/permissive/506562943/HDLBits/Verilog\n%Error: Cannot find file containing module: Features/bcdadd100.v\n%Error: Exiting due to 5 error(s)\n'
module top_module( 
    input [399:0] a, b,
    input cin,
    output cout,
    output [399:0] sum );


    wire [98:0] carry;
    

    bcd_fadd u_bcd_fadd_0(a[3:0], b[3:0], cin, carry[0], sum[3:0]);
    bcd_fadd u_bcd_fadd_99(a[399:396], b[399:396], carry[98], cout, sum[399:396]);
    

    generate
        genvar i;
        
        for (i = 1; i < 99; i++) begin : add_100
            bcd_fadd u_bcd_fadd(a[i * 4 + 3: i * 4], b[i * 4 + 3: i * 4], carry[i - 1], carry[i], sum[i * 4 + 3: i * 4])
        end
    endgenerate
    
endmodule
module top_module( 
    input [399:0] a, b,
    input cin,
    output cout,
    output [399:0] sum );



    wire [98:0] carry;
    

    bcd_fadd u_bcd_fadd_0(a[3:0], b[3:0], cin, carry[0], sum[3:0]);
    bcd_fadd u_bcd_fadd_99(a[399:396], b[399:396], carry[98], cout, sum[399:396]);
    

    generate
        genvar i;
        
        for (i = 1; i < 99; i++) begin : add_100
            bcd_fadd u_bcd_fadd(a[i * 4 + 3: i * 4], b[i * 4 + 3: i * 4], carry[i - 1], carry[i], sum[i * 4 + 3: i * 4])
        end
    endgenerate
    
endmodule