data/full_repos/permissive/428611613/cores/port_slicer_v1_0/port_slicer.v
data/verilator_xmls/1e9d56c4-eb32-445d-86b2-0415a6532e1a.xml
module port_slicer #
(
  parameter integer DIN_WIDTH = 32,
  parameter integer DIN_FROM = 31,
  parameter integer DIN_TO = 0
)
(
  input  wire [DIN_WIDTH-1:0]     din,
  output wire [DIN_FROM-DIN_TO:0] dout
);

  assign dout = din[DIN_FROM:DIN_TO];

endmodule
module port_slicer #
(
  parameter integer DIN_WIDTH = 32,
  parameter integer DIN_FROM = 31,
  parameter integer DIN_TO = 0
)
(
  input  wire [DIN_WIDTH-1:0]     din,
  output wire [DIN_FROM-DIN_TO:0] dout
);


  assign dout = din[DIN_FROM:DIN_TO];

endmodule