data/full_repos/permissive/503053625/fpga_projects/SPGD/src/twos_to_ADC_offset.v
1: b'%Warning-WIDTH: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/twos_to_ADC_offset.v:10: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'14\'h0\' generates 14 bits.\n                                                                                                   : ... In instance twos_to_ADC_offset\n    reg [WIRE_WIDTH - 1:0] data_register1 = 14\'h0;\n                                            ^~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/twos_to_ADC_offset.v:15: Operator SUB expects 14 bits on the LHS, but LHS\'s VARREF \'data_in\' generates 12 bits.\n                                                                                                   : ... In instance twos_to_ADC_offset\n            data_register1 = data_in - 14\'h800;\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/twos_to_ADC_offset.v:15: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s SUB generates 14 bits.\n                                                                                                   : ... In instance twos_to_ADC_offset\n            data_register1 = data_in - 14\'h800;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/twos_to_ADC_offset.v:17: Operator ADD expects 14 bits on the LHS, but LHS\'s VARREF \'data_in\' generates 12 bits.\n                                                                                                   : ... In instance twos_to_ADC_offset\n            data_register1 = data_in + 14\'h800;\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/twos_to_ADC_offset.v:17: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s ADD generates 14 bits.\n                                                                                                   : ... In instance twos_to_ADC_offset\n            data_register1 = data_in + 14\'h800;\n                           ^\n%Error: Exiting due to 5 warning(s)\n'
module twos_to_ADC_offset
#(
	parameter WIRE_WIDTH = 12
)
(
    input [WIRE_WIDTH - 1:0] data_in,
	output [WIRE_WIDTH - 1:0] data_out
);

    reg [WIRE_WIDTH - 1:0] data_register1 = 14'h0;
    
    always @(data_in)
    begin
        if(data_in[WIRE_WIDTH - 1])
            data_register1 = data_in - 14'h800;
        else 
            data_register1 = data_in + 14'h800;
    end
    
    assign data_out = data_register1;

endmodule
module twos_to_ADC_offset
#(
	parameter WIRE_WIDTH = 12
)
(
    input [WIRE_WIDTH - 1:0] data_in,
	output [WIRE_WIDTH - 1:0] data_out
);


    reg [WIRE_WIDTH - 1:0] data_register1 = 14'h0;
    
    always @(data_in)
    begin
        if(data_in[WIRE_WIDTH - 1])
            data_register1 = data_in - 14'h800;
        else 
            data_register1 = data_in + 14'h800;
    end
    
    assign data_out = data_register1;

endmodule