data/full_repos/permissive/420819839/Vectors/Vectorr.v
data/verilator_xmls/2c69ca47-06b4-48ad-8dc8-b5f4117a37ca.xml
module top_module( 
    input [7:0] in,
    output [7:0] out
);

    assign out = {in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7]};
    
endmodule
module top_module( 
    input [7:0] in,
    output [7:0] out
);


    assign out = {in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7]};
    
endmodule