data/full_repos/permissive/470571815/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8_wrapper.v
1: b"%Error: data/full_repos/permissive/470571815/verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8_wrapper.v:58: Cannot find file containing module: 'sky130_sram_2kbyte_1rw1r_32x512_8'\n  sky130_sram_2kbyte_1rw1r_32x512_8 inner (\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/470571815/verilog/rtl,data/full_repos/permissive/470571815/sky130_sram_2kbyte_1rw1r_32x512_8\n             data/full_repos/permissive/470571815/verilog/rtl,data/full_repos/permissive/470571815/sky130_sram_2kbyte_1rw1r_32x512_8.v\n             data/full_repos/permissive/470571815/verilog/rtl,data/full_repos/permissive/470571815/sky130_sram_2kbyte_1rw1r_32x512_8.sv\n             sky130_sram_2kbyte_1rw1r_32x512_8\n             sky130_sram_2kbyte_1rw1r_32x512_8.v\n             sky130_sram_2kbyte_1rw1r_32x512_8.sv\n             obj_dir/sky130_sram_2kbyte_1rw1r_32x512_8\n             obj_dir/sky130_sram_2kbyte_1rw1r_32x512_8.v\n             obj_dir/sky130_sram_2kbyte_1rw1r_32x512_8.sv\n%Error: Exiting due to 1 error(s)\n"
module sky130_sram_2kbyte_1rw1r_32x512_8_wrapper(
`ifdef USE_POWER_PINS
    vccd1,
    vssd1,
`endif
    clk0, cs0, web0, wmask0, addr0, din0, dout0, clk1, cs1, addr1, dout1);
`ifdef USE_POWER_PINS
    inout vccd1;
    inout vssd1;
`endif
  (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:156.24-156.28" *)
  wire _0_;
  (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:157.24-157.28" *)
  wire _1_;
  (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:144.27-144.32" *)
  input [8:0] addr0;
  wire [8:0] addr0;
  (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:149.27-149.32" *)
  input [8:0] addr1;
  wire [8:0] addr1;
  (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:140.10-140.14" *)
  input clk0;
  wire clk0;
  (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:147.10-147.14" *)
  input clk1;
  wire clk1;
  (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:141.11-141.14" *)
  input cs0;
  wire cs0;
  (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:148.11-148.14" *)
  input cs1;
  wire cs1;
  (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:145.27-145.31" *)
  input [31:0] din0;
  wire [31:0] din0;
  (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:146.27-146.32" *)
  output [31:0] dout0;
  wire [31:0] dout0;
  (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:150.27-150.32" *)
  output [31:0] dout1;
  wire [31:0] dout1;
  (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:142.10-142.14" *)
  input web0;
  wire web0;
  (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:143.28-143.34" *)
  input [3:0] wmask0;
  wire [3:0] wmask0;
  assign _0_ = ! (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:156.24-156.28" *) cs0;
  assign _1_ = ! (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:157.24-157.28" *) cs1;
  (* module_not_derived = 32'd1 *)
  (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:151.37-158.4" *)
  sky130_sram_2kbyte_1rw1r_32x512_8 inner (
`ifdef USE_POWER_PINS
    .vccd1(vccd1),
    .vssd1(vssd1),
`endif
    .addr0(addr0),
    .addr1(addr1),
    .clk0(clk0),
    .clk1(clk1),
    .csb0(_0_),
    .csb1(_1_),
    .din0(din0),
    .dout0(dout0),
    .dout1(dout1),
    .web0(web0),
    .wmask0(wmask0)
  );
endmodule
module sky130_sram_2kbyte_1rw1r_32x512_8_wrapper(
`ifdef USE_POWER_PINS
    vccd1,
    vssd1,
`endif
    clk0, cs0, web0, wmask0, addr0, din0, dout0, clk1, cs1, addr1, dout1);

`ifdef USE_POWER_PINS
    inout vccd1;
    inout vssd1;
`endif
  (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:156.24-156.28" *)
  wire _0_;
  (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:157.24-157.28" *)
  wire _1_;
  (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:144.27-144.32" *)
  input [8:0] addr0;
  wire [8:0] addr0;
  (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:149.27-149.32" *)
  input [8:0] addr1;
  wire [8:0] addr1;
  (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:140.10-140.14" *)
  input clk0;
  wire clk0;
  (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:147.10-147.14" *)
  input clk1;
  wire clk1;
  (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:141.11-141.14" *)
  input cs0;
  wire cs0;
  (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:148.11-148.14" *)
  input cs1;
  wire cs1;
  (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:145.27-145.31" *)
  input [31:0] din0;
  wire [31:0] din0;
  (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:146.27-146.32" *)
  output [31:0] dout0;
  wire [31:0] dout0;
  (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:150.27-150.32" *)
  output [31:0] dout1;
  wire [31:0] dout1;
  (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:142.10-142.14" *)
  input web0;
  wire web0;
  (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:143.28-143.34" *)
  input [3:0] wmask0;
  wire [3:0] wmask0;
  assign _0_ = ! (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:156.24-156.28" *) cs0;
  assign _1_ = ! (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:157.24-157.28" *) cs1;
  (* module_not_derived = 32'd1 *)
  (* src = "boards/qf100/sky130_sram_2kbyte_1rw1r_32x512_8.v:151.37-158.4" *)
  sky130_sram_2kbyte_1rw1r_32x512_8 inner (
`ifdef USE_POWER_PINS
    .vccd1(vccd1),
    .vssd1(vssd1),
`endif
    .addr0(addr0),
    .addr1(addr1),
    .clk0(clk0),
    .clk1(clk1),
    .csb0(_0_),
    .csb1(_1_),
    .din0(din0),
    .dout0(dout0),
    .dout1(dout1),
    .web0(web0),
    .wmask0(wmask0)
  );
endmodule