data/full_repos/permissive/487568919/generic_systemverilog_designs_library/demultiplexer/demux.sv
data/verilator_xmls/b4013ccd-0abc-46a2-b32f-4267383e1364.xml
module demux #(parameter WIDTH = 1, 
               parameter NUMBER = 2, 
               localparam SELECT_W = $clog2(NUMBER)) 
 (input logic [SELECT_W-1:0] sel, 
  input logic [WIDTH-1:0] demux_in,                   
  output logic [WIDTH-1:0] demux_out [NUMBER-1:0]);
  
  assign demux_out[sel] = demux_in;
    
endmodule
module demux #(parameter WIDTH = 1, 
               parameter NUMBER = 2, 
               localparam SELECT_W = $clog2(NUMBER)) 
 (input logic [SELECT_W-1:0] sel, 
  input logic [WIDTH-1:0] demux_in,                   
  output logic [WIDTH-1:0] demux_out [NUMBER-1:0]);

  
  assign demux_out[sel] = demux_in;
    
endmodule