data/full_repos/permissive/433336136/16bit_risc/Data_Memory.v
1: b'%Error: data/full_repos/permissive/433336136/16bit_risc/Data_Memory.v:1: Cannot find include file: Parameter.v\n`include "Parameter.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/433336136/16bit_risc,data/full_repos/permissive/433336136/Parameter.v\n             data/full_repos/permissive/433336136/16bit_risc,data/full_repos/permissive/433336136/Parameter.v.v\n             data/full_repos/permissive/433336136/16bit_risc,data/full_repos/permissive/433336136/Parameter.v.sv\n             Parameter.v\n             Parameter.v.v\n             Parameter.v.sv\n             obj_dir/Parameter.v\n             obj_dir/Parameter.v.v\n             obj_dir/Parameter.v.sv\n%Error: data/full_repos/permissive/433336136/16bit_risc/Data_Memory.v:19: Define or directive not defined: \'`col\'\nreg [`col - 1:0] memory [`row_d - 1:0];\n     ^~~~\n%Error: data/full_repos/permissive/433336136/16bit_risc/Data_Memory.v:19: Define or directive not defined: \'`row_d\'\nreg [`col - 1:0] memory [`row_d - 1:0];\n                         ^~~~~~\n%Error: data/full_repos/permissive/433336136/16bit_risc/Data_Memory.v:26: Define or directive not defined: \'`filename\'\n    f = $fopen(`filename);\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/433336136/16bit_risc/Data_Memory.v:26: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    f = $fopen(`filename);\n                        ^\n%Error: data/full_repos/permissive/433336136/16bit_risc/Data_Memory.v:37: Define or directive not defined: \'`simulation_time\'\n    `simulation_time;\n    ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n'
module Data_Memory(
           input clk,

           input [15:0]   mem_access_addr,


           input [15:0]   mem_write_data,
           input     mem_write_en,
           input mem_read,

           output [15:0]   mem_read_data
       );

reg [`col - 1:0] memory [`row_d - 1:0];
integer f;
wire [2:0] ram_addr=mem_access_addr[2:0];
initial
begin
    $readmemb("./test/test.data", memory);

    f = $fopen(`filename);

    $display("time = %d\n", $time,
             "\tmemory[0] = %b\n", memory[0],
             "\tmemory[1] = %b\n", memory[1],
             "\tmemory[2] = %b\n", memory[2],
             "\tmemory[3] = %b\n", memory[3],
             "\tmemory[4] = %b\n", memory[4],
             "\tmemory[5] = %b\n", memory[5],
             "\tmemory[6] = %b\n", memory[6],
             "\tmemory[7] = %b\n", memory[7]);
    `simulation_time;
    $fclose(f);
end

always @(posedge clk) begin
    if (mem_write_en)
        memory[ram_addr] <= mem_write_data;
end
assign mem_read_data = (mem_read==1'b1) ? memory[ram_addr]: 16'd0;


endmodule
module Data_Memory(
           input clk,

           input [15:0]   mem_access_addr,


           input [15:0]   mem_write_data,
           input     mem_write_en,
           input mem_read,

           output [15:0]   mem_read_data
       );


reg [`col - 1:0] memory [`row_d - 1:0];
integer f;
wire [2:0] ram_addr=mem_access_addr[2:0];
initial
begin
    $readmemb("./test/test.data", memory);

    f = $fopen(`filename);

    $display("time = %d\n", $time,
             "\tmemory[0] = %b\n", memory[0],
             "\tmemory[1] = %b\n", memory[1],
             "\tmemory[2] = %b\n", memory[2],
             "\tmemory[3] = %b\n", memory[3],
             "\tmemory[4] = %b\n", memory[4],
             "\tmemory[5] = %b\n", memory[5],
             "\tmemory[6] = %b\n", memory[6],
             "\tmemory[7] = %b\n", memory[7]);
    `simulation_time;
    $fclose(f);
end

always @(posedge clk) begin
    if (mem_write_en)
        memory[ram_addr] <= mem_write_data;
end
assign mem_read_data = (mem_read==1'b1) ? memory[ram_addr]: 16'd0;


endmodule