data/full_repos/permissive/492772061/ADPPulse/slow/ADP_Sim_Slow.srcs/sim_1/new/runAdp.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/492772061/ADPPulse/slow/ADP_Sim_Slow.srcs/sim_1/new/runAdp.v:28: Unsupported: Ignoring delay on this delayed statement.\n        clk = 1; #5;\n                 ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/492772061/ADPPulse/slow/ADP_Sim_Slow.srcs/sim_1/new/runAdp.v:29: Unsupported: Ignoring delay on this delayed statement.\n        clk = 0; #5;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/492772061/ADPPulse/slow/ADP_Sim_Slow.srcs/sim_1/new/runAdp.v:33: Unsupported: Ignoring delay on this delayed statement.\n        Adp = 0; #100;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/492772061/ADPPulse/slow/ADP_Sim_Slow.srcs/sim_1/new/runAdp.v:34: Unsupported: Ignoring delay on this delayed statement.\n        Adp = 1; #20;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/492772061/ADPPulse/slow/ADP_Sim_Slow.srcs/sim_1/new/runAdp.v:35: Unsupported: Ignoring delay on this delayed statement.\n        Adp = 0; #100;\n                 ^\n%Error: data/full_repos/permissive/492772061/ADPPulse/slow/ADP_Sim_Slow.srcs/sim_1/new/runAdp.v:38: Cannot find file containing module: \'slowLogic\'\n    slowLogic slowLogic_i(\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/492772061/ADPPulse/slow/ADP_Sim_Slow.srcs/sim_1/new,data/full_repos/permissive/492772061/slowLogic\n             data/full_repos/permissive/492772061/ADPPulse/slow/ADP_Sim_Slow.srcs/sim_1/new,data/full_repos/permissive/492772061/slowLogic.v\n             data/full_repos/permissive/492772061/ADPPulse/slow/ADP_Sim_Slow.srcs/sim_1/new,data/full_repos/permissive/492772061/slowLogic.sv\n             slowLogic\n             slowLogic.v\n             slowLogic.sv\n             obj_dir/slowLogic\n             obj_dir/slowLogic.v\n             obj_dir/slowLogic.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module runAdp;
    reg clk, Adp;
    wire Q, R, apdPE;
    
    always begin
        clk = 1; #5;
        clk = 0; #5;
    end    
    
    always begin
        Adp = 0; #100;
        Adp = 1; #20;
        Adp = 0; #100;
    end
    
    slowLogic slowLogic_i(
        .clk(clk),
        .Adp_pulse(Adp),
        .Quench(Q),
        .Reset(R),
        .AdpPE(apdPE)
        );

endmodule
module runAdp;

    reg clk, Adp;
    wire Q, R, apdPE;
    
    always begin
        clk = 1; #5;
        clk = 0; #5;
    end    
    
    always begin
        Adp = 0; #100;
        Adp = 1; #20;
        Adp = 0; #100;
    end
    
    slowLogic slowLogic_i(
        .clk(clk),
        .Adp_pulse(Adp),
        .Quench(Q),
        .Reset(R),
        .AdpPE(apdPE)
        );

endmodule