data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_impctl_clkgen.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_impctl_clkgen.v:42: Cannot find file containing module: 'bw_io_impctl_sclk'\nbw_io_impctl_sclk I227 (\n^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_io_impctl_sclk\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_io_impctl_sclk.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_io_impctl_sclk.sv\n             bw_io_impctl_sclk\n             bw_io_impctl_sclk.v\n             bw_io_impctl_sclk.sv\n             obj_dir/bw_io_impctl_sclk\n             obj_dir/bw_io_impctl_sclk.v\n             obj_dir/bw_io_impctl_sclk.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_impctl_clkgen.v:50: Cannot find file containing module: 'bw_io_impctl_upclk'\nbw_io_impctl_upclk I208 (\n^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module bw_io_impctl_clkgen(se ,oe_out ,updclk ,so_l ,si_l ,
     synced_upd_imped ,bypass ,global_reset_n ,clk ,hard_reset_n ,sclk ,
     reset_l ,avgcntr_rst );
output		oe_out ;
output		updclk ;
output		so_l ;
output		bypass ;
output		global_reset_n ;
output		sclk ;
output		avgcntr_rst ;
input		se ;
input		si_l ;
input		synced_upd_imped ;
input		clk ;
input		hard_reset_n ;
input		reset_l ;
 
wire		int_sclk ;
wire		net42 ;
 
 
bw_io_impctl_sclk I227 (
     .l2clk           (clk ),
     .int_sclk        (int_sclk ),
     .sclk            (sclk ),
     .ssclk_n         (net42 ),
     .se              (se ),
     .si_l            (si_l ),
     .global_reset_n  (global_reset_n ) );
bw_io_impctl_upclk I208 (
     .int_sclk        (int_sclk ),
     .l2clk           (clk ),
     .synced_upd_imped (synced_upd_imped ),
     .updclk          (updclk ),
     .reset_l         (reset_l ),
     .oe_out          (oe_out ),
     .bypass          (bypass ),
     .avgcntr_rst     (avgcntr_rst ),
     .so_l            (so_l ),
     .hard_reset_n    (hard_reset_n ),
     .si_l            (net42 ),
     .se              (se ),
     .global_reset_n  (global_reset_n ) );
endmodule
module bw_io_impctl_clkgen(se ,oe_out ,updclk ,so_l ,si_l ,
     synced_upd_imped ,bypass ,global_reset_n ,clk ,hard_reset_n ,sclk ,
     reset_l ,avgcntr_rst );

output		oe_out ;
output		updclk ;
output		so_l ;
output		bypass ;
output		global_reset_n ;
output		sclk ;
output		avgcntr_rst ;
input		se ;
input		si_l ;
input		synced_upd_imped ;
input		clk ;
input		hard_reset_n ;
input		reset_l ;
 
wire		int_sclk ;
wire		net42 ;
 
 
bw_io_impctl_sclk I227 (
     .l2clk           (clk ),
     .int_sclk        (int_sclk ),
     .sclk            (sclk ),
     .ssclk_n         (net42 ),
     .se              (se ),
     .si_l            (si_l ),
     .global_reset_n  (global_reset_n ) );
bw_io_impctl_upclk I208 (
     .int_sclk        (int_sclk ),
     .l2clk           (clk ),
     .synced_upd_imped (synced_upd_imped ),
     .updclk          (updclk ),
     .reset_l         (reset_l ),
     .oe_out          (oe_out ),
     .bypass          (bypass ),
     .avgcntr_rst     (avgcntr_rst ),
     .so_l            (so_l ),
     .hard_reset_n    (hard_reset_n ),
     .si_l            (net42 ),
     .se              (se ),
     .global_reset_n  (global_reset_n ) );
endmodule