data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v
1: b'%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:116: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_X_WAIT\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   S_LOAD_X: next = LoadX ? S_LOAD_X_WAIT : S_LOAD_X;\n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:116: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s VARREF \'S_LOAD_X\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   S_LOAD_X: next = LoadX ? S_LOAD_X_WAIT : S_LOAD_X;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:117: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_X_WAIT\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   S_LOAD_X_WAIT: next = LoadX ? S_LOAD_X_WAIT : S_LOAD_Y_COLOUR;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:117: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s VARREF \'S_LOAD_Y_COLOUR\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   S_LOAD_X_WAIT: next = LoadX ? S_LOAD_X_WAIT : S_LOAD_Y_COLOUR;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:118: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_Y_WAIT\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   S_LOAD_Y_COLOUR: next = PlotBox ? S_LOAD_Y_WAIT : S_LOAD_Y_COLOUR;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:118: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s VARREF \'S_LOAD_Y_COLOUR\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   S_LOAD_Y_COLOUR: next = PlotBox ? S_LOAD_Y_WAIT : S_LOAD_Y_COLOUR;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:119: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_Y_WAIT\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   S_LOAD_Y_WAIT: next = PlotBox ? S_LOAD_Y_WAIT : S_DRAW;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:119: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s VARREF \'S_DRAW\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   S_LOAD_Y_WAIT: next = PlotBox ? S_LOAD_Y_WAIT : S_DRAW;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:120: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_X\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   S_DRAW: next = LoadX ? S_LOAD_X : S_DRAW;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:120: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s VARREF \'S_DRAW\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   S_DRAW: next = LoadX ? S_LOAD_X : S_DRAW;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:121: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_LOAD_X\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   default next = S_LOAD_X;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:115: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_X\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n  case(now)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:115: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_X_WAIT\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n  case(now)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:115: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_Y_COLOUR\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n  case(now)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:115: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_Y_WAIT\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n  case(now)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:115: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'S_DRAW\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n  case(now)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:128: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_LOAD_X\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   now <= S_LOAD_X;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:140: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_X_WAIT\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n       case (now)\n       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:140: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_Y_COLOUR\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n       case (now)\n       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:140: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'S_DRAW\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n       case (now)\n       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:90: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                 : ... In instance part2.d0\n    X_Coordinates <= temp_x + Counter[1:0];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:91: Operator ADD expects 7 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                 : ... In instance part2.d0\n    Y_Coordinates <= temp_y + Counter[3:2];\n                            ^\n%Error: Exiting due to 22 warning(s)\n'
module part2(iResetn,iPlotBox,iBlack,iColour,iLoadX,iXY_Coord,iClock,oX,oY,oColour,oPlot);
   
	parameter X_SCREEN_PIXELS = 8'd160;
   parameter Y_SCREEN_PIXELS = 7'd120;
   
   input wire iResetn, iPlotBox, iBlack, iLoadX;
   input wire [2:0] iColour;
   input wire [6:0] iXY_Coord;
   input wire 	    iClock;
   output wire [7:0] oX;
   output wire [6:0] oY;
   
   output wire [2:0] oColour;
   output wire 	     oPlot;
	
	wire X_enable, Y_enable, Color_enable, Counter_enable;

   controlpath C0(iClock,iResetn,iLoadX, iPlotBox, X_enable, Y_enable, Color_enable, Counter_enable, oPlot);	
	datapath d0(iClock, iResetn, iXY_Coord, iColour, oPlot, iBlack, X_enable, Y_enable, oX, oY, Counter_enable, Color_enable, oColour);
   
endmodule
module part2(iResetn,iPlotBox,iBlack,iColour,iLoadX,iXY_Coord,iClock,oX,oY,oColour,oPlot);

   
	parameter X_SCREEN_PIXELS = 8'd160;
   parameter Y_SCREEN_PIXELS = 7'd120;
   
   input wire iResetn, iPlotBox, iBlack, iLoadX;
   input wire [2:0] iColour;
   input wire [6:0] iXY_Coord;
   input wire 	    iClock;
   output wire [7:0] oX;
   output wire [6:0] oY;
   
   output wire [2:0] oColour;
   output wire 	     oPlot;
	
	wire X_enable, Y_enable, Color_enable, Counter_enable;

   controlpath C0(iClock,iResetn,iLoadX, iPlotBox, X_enable, Y_enable, Color_enable, Counter_enable, oPlot);	
	datapath d0(iClock, iResetn, iXY_Coord, iColour, oPlot, iBlack, X_enable, Y_enable, oX, oY, Counter_enable, Color_enable, oColour);
   
endmodule