data/full_repos/permissive/474721296/alu/alu.v
1: b'%Error: data/full_repos/permissive/474721296/alu/alu.v:4: Cannot find include file: ../eight_adder/eight_adder.v\n`include "../eight_adder/eight_adder.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/474721296/alu,data/full_repos/permissive/474721296/../eight_adder/eight_adder.v\n             data/full_repos/permissive/474721296/alu,data/full_repos/permissive/474721296/../eight_adder/eight_adder.v.v\n             data/full_repos/permissive/474721296/alu,data/full_repos/permissive/474721296/../eight_adder/eight_adder.v.sv\n             ../eight_adder/eight_adder.v\n             ../eight_adder/eight_adder.v.v\n             ../eight_adder/eight_adder.v.sv\n             obj_dir/../eight_adder/eight_adder.v\n             obj_dir/../eight_adder/eight_adder.v.v\n             obj_dir/../eight_adder/eight_adder.v.sv\n%Error: data/full_repos/permissive/474721296/alu/alu.v:5: Cannot find include file: ../twos_comp/twos_comp.v\n`include "../twos_comp/twos_comp.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/474721296/alu/alu.v:6: Cannot find include file: ../shift/shift.v\n`include "../shift/shift.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module alu(
		input[7:0] A, B,
		input[2:0] S,
		output[7:0] D,
		output C
	);

	wire Cin;
	wire Cout;
	wire[7:0] adder_out;
	wire[7:0] shift_out;

	wire add_or_sub = ~(S[2] | S[1]);
	wire and_or_xor_not = S[1];
	wire[7:0] B_neg;
	wire[7:0] B_multi = S[0] ? B_neg : B;


	wire[7:0] S2e = {8{S[2]}};
	wire[7:0] S0e = {8{S[0]}};
	wire[7:0] logical_out =
		(S0e & (A ^ B)) | (~S2e & A & B) | (S2e & ~S0e & ~A);


	assign C = add_or_sub ? Cout :
		and_or_xor_not ? 1'b0 :
		1'b0;
	assign D = add_or_sub ? adder_out :
		and_or_xor_not ? logical_out :
		shift_out;
	assign Cin = 0;

	eight_adder adder(A, B_multi, Cin, adder_out, Cout);
	twos_comp comp_calc(B, B_neg);
	shift shifter(A, B[2:0], S[0], shift_out);
endmodule
module alu(
		input[7:0] A, B,
		input[2:0] S,
		output[7:0] D,
		output C
	);


	wire Cin;
	wire Cout;
	wire[7:0] adder_out;
	wire[7:0] shift_out;

	wire add_or_sub = ~(S[2] | S[1]);
	wire and_or_xor_not = S[1];
	wire[7:0] B_neg;
	wire[7:0] B_multi = S[0] ? B_neg : B;


	wire[7:0] S2e = {8{S[2]}};
	wire[7:0] S0e = {8{S[0]}};
	wire[7:0] logical_out =
		(S0e & (A ^ B)) | (~S2e & A & B) | (S2e & ~S0e & ~A);


	assign C = add_or_sub ? Cout :
		and_or_xor_not ? 1'b0 :
		1'b0;
	assign D = add_or_sub ? adder_out :
		and_or_xor_not ? logical_out :
		shift_out;
	assign Cin = 0;

	eight_adder adder(A, B_multi, Cin, adder_out, Cout);
	twos_comp comp_calc(B, B_neg);
	shift shifter(A, B[2:0], S[0], shift_out);
endmodule