data/full_repos/permissive/421663164/univision/mpw3/openlane/sspim/rtl/sspim_if.sv
data/verilator_xmls/c5c6772b-5372-49e5-9a01-d799208b807a.xml
module sspim_if
          (
          input  logic clk,
          input  logic reset_n,
          input  logic sck_pe,
          input  logic sck_int,
          input  logic cs_int_n,
          
          input  logic       load_byte,
          input  logic [1:0] cfg_tgt_sel,

          input  logic [7:0] byte_out,
          input  logic       shift_out,
          input  logic       shift_in,

          output logic  [7:0] byte_in,
          output logic        sck,
          output logic        so,
          output logic  [3:0] cs_n,
          input  logic        si
           );



  logic [7:0]    so_reg;
  logic [7:0]    si_reg;




  always @(posedge clk or negedge reset_n) begin
     if(!reset_n) begin
        so_reg <= 8'h00;
        so <= 1'b0;
     end
     else begin
        if(load_byte) begin
           so_reg <= byte_out;
           if(shift_out) begin 


              so <= so_reg[7];
           end
        end
        else begin
           if(shift_out) begin
              so <= so_reg[7];
              so_reg <= {so_reg[6:0],1'b0};
           end
        end
     end
  end



  always @(posedge clk or negedge reset_n) begin
     if(!reset_n) begin
        si_reg <= 8'h0;
     end
     else begin
        if(sck_pe & shift_in) begin
           si_reg[7:0] <= {si_reg[6:0],si};
        end
     end
  end


  assign byte_in[7:0] = si_reg[7:0];
  assign cs_n[0] = (cfg_tgt_sel[1:0] == 2'b00) ? cs_int_n : 1'b1;
  assign cs_n[1] = (cfg_tgt_sel[1:0] == 2'b01) ? cs_int_n : 1'b1;
  assign cs_n[2] = (cfg_tgt_sel[1:0] == 2'b10) ? cs_int_n : 1'b1;
  assign cs_n[3] = (cfg_tgt_sel[1:0] == 2'b11) ? cs_int_n : 1'b1;
  assign sck = sck_int;

endmodule
module sspim_if
          (
          input  logic clk,
          input  logic reset_n,
          input  logic sck_pe,
          input  logic sck_int,
          input  logic cs_int_n,
          
          input  logic       load_byte,
          input  logic [1:0] cfg_tgt_sel,

          input  logic [7:0] byte_out,
          input  logic       shift_out,
          input  logic       shift_in,

          output logic  [7:0] byte_in,
          output logic        sck,
          output logic        so,
          output logic  [3:0] cs_n,
          input  logic        si
           );




  logic [7:0]    so_reg;
  logic [7:0]    si_reg;




  always @(posedge clk or negedge reset_n) begin
     if(!reset_n) begin
        so_reg <= 8'h00;
        so <= 1'b0;
     end
     else begin
        if(load_byte) begin
           so_reg <= byte_out;
           if(shift_out) begin 


              so <= so_reg[7];
           end
        end
        else begin
           if(shift_out) begin
              so <= so_reg[7];
              so_reg <= {so_reg[6:0],1'b0};
           end
        end
     end
  end



  always @(posedge clk or negedge reset_n) begin
     if(!reset_n) begin
        si_reg <= 8'h0;
     end
     else begin
        if(sck_pe & shift_in) begin
           si_reg[7:0] <= {si_reg[6:0],si};
        end
     end
  end


  assign byte_in[7:0] = si_reg[7:0];
  assign cs_n[0] = (cfg_tgt_sel[1:0] == 2'b00) ? cs_int_n : 1'b1;
  assign cs_n[1] = (cfg_tgt_sel[1:0] == 2'b01) ? cs_int_n : 1'b1;
  assign cs_n[2] = (cfg_tgt_sel[1:0] == 2'b10) ? cs_int_n : 1'b1;
  assign cs_n[3] = (cfg_tgt_sel[1:0] == 2'b11) ? cs_int_n : 1'b1;
  assign sck = sck_int;

endmodule