data/full_repos/permissive/43858668/final_verilog/src/vcr_ovc_ctrl.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ovc_ctrl.v:37: Cannot find include file: c_functions.v\n`include "c_functions.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v.v\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v.sv\n             c_functions.v\n             c_functions.v.v\n             c_functions.v.sv\n             obj_dir/c_functions.v\n             obj_dir/c_functions.v.v\n             obj_dir/c_functions.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ovc_ctrl.v:38: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ovc_ctrl.v:39: Cannot find include file: rtr_constants.v\n`include "rtr_constants.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ovc_ctrl.v:40: Cannot find include file: vcr_constants.v\n`include "vcr_constants.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ovc_ctrl.v:52: Define or directive not defined: \'`ELIG_MASK_NONE\'\n   parameter elig_mask = `ELIG_MASK_NONE;\n                         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ovc_ctrl.v:52: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter elig_mask = `ELIG_MASK_NONE;\n                                        ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ovc_ctrl.v:54: Define or directive not defined: \'`RESET_TYPE_ASYNC\'\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ovc_ctrl.v:54: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                                           ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ovc_ctrl.v:192: Define or directive not defined: \'`ELIG_MASK_NONE\'\n      if(sw_alloc_spec && (elig_mask == `ELIG_MASK_NONE))\n                                        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ovc_ctrl.v:192: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      if(sw_alloc_spec && (elig_mask == `ELIG_MASK_NONE))\n                                                       ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ovc_ctrl.v:208: Define or directive not defined: \'`ELIG_MASK_NONE\'\n `ELIG_MASK_NONE:\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ovc_ctrl.v:208: syntax error, unexpected \':\', expecting endcase\n `ELIG_MASK_NONE:\n                ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ovc_ctrl.v:213: Define or directive not defined: \'`ELIG_MASK_FULL\'\n `ELIG_MASK_FULL:\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_ovc_ctrl.v:218: Define or directive not defined: \'`ELIG_MASK_USED\'\n `ELIG_MASK_USED:\n ^~~~~~~~~~~~~~~\n%Error: Cannot continue\n'
module vcr_ovc_ctrl
  (clk, reset, vc_active, vc_gnt, vc_sel_ip, vc_sel_ivc, sw_active, sw_gnt, 
   sw_sel_ip, sw_sel_ivc, flit_valid, flit_tail, flit_sel, elig, full, 
   full_prev, empty);
   
`include "c_functions.v"
`include "c_constants.v"
`include "rtr_constants.v"
`include "vcr_constants.v"
   

   parameter num_vcs = 4;
   

   parameter num_ports = 5;
   

   parameter sw_alloc_spec = 1;
   

   parameter elig_mask = `ELIG_MASK_NONE;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   input clk;
   input reset;
   

   input vc_active;
   

   input vc_gnt;
   

   input [0:num_ports-1] vc_sel_ip;
   

   input [0:num_vcs-1] 	 vc_sel_ivc;
   

   input 		 sw_active;
   

   input 		 sw_gnt;
   

   input [0:num_ports-1] sw_sel_ip;
   

   input [0:num_vcs-1] 	 sw_sel_ivc;
   

   input 		 flit_valid;
   

   input 		 flit_tail;
   

   output 		 flit_sel;
   wire 		 flit_sel;
   

   output 		 elig;
   wire 		 elig;
   

   input 		 full;
   

   input 		 full_prev;
   

   input 		 empty;
   
   



   
   wire 		 alloc_active;
   assign alloc_active = vc_active | flit_valid;
   
   wire 		 allocated;
   
   wire 		 allocated_s, allocated_q;
   assign allocated_s = vc_gnt | allocated;
   c_dff
     #(.width(1),
       .reset_type(reset_type))
   allocatedq
     (.clk(clk),
      .reset(reset),
      .active(alloc_active),
      .d(allocated_s),
      .q(allocated_q));
   
   assign allocated = allocated_q & ~(flit_valid & flit_sel & flit_tail);
   
   wire [0:num_ports-1]  allocated_ip_s, allocated_ip_q;
   assign allocated_ip_s = allocated ? allocated_ip_q : vc_sel_ip;
   c_dff
     #(.width(num_ports),
       .reset_type(reset_type))
   allocated_ipq
     (.clk(clk),
      .reset(1'b0),
      .active(vc_active),
      .d(allocated_ip_s),
      .q(allocated_ip_q));
   
   wire 		 port_match;
   wire 		 vc_match;
   
   generate
      
      if(sw_alloc_spec)
	assign port_match = |(sw_sel_ip & allocated_ip_s);
      else
	assign port_match = |(sw_sel_ip & allocated_ip_q);
      
      if(num_vcs == 1)
	assign vc_match = 1'b1;
      else if(num_vcs > 1)
	begin
	   
	   wire [0:num_vcs-1] allocated_ivc_s, allocated_ivc_q;
	   assign allocated_ivc_s = allocated ? allocated_ivc_q : vc_sel_ivc;
	   c_dff
	     #(.width(num_vcs),
	       .reset_type(reset_type))
	   allocated_ivcq
	     (.clk(clk),
	      .reset(1'b0),
	      .active(vc_active),
	      .d(allocated_ivc_s),
	      .q(allocated_ivc_q));
	   
	   if(sw_alloc_spec)
	     assign vc_match = |(sw_sel_ivc & allocated_ivc_s);
	   else
	     assign vc_match = |(sw_sel_ivc & allocated_ivc_q);
	   
	end
      
   endgenerate
   
   wire 		      match_s, match_q;
   assign match_s = sw_gnt ? (port_match & vc_match) : match_q;
   c_dff
     #(.width(1),
       .reset_type(reset_type))
   matchq
     (.clk(clk),
      .reset(reset),
      .active(sw_active),
      .d(match_s),
      .q(match_q));
   
   generate
	 
      if(sw_alloc_spec && (elig_mask == `ELIG_MASK_NONE))
	assign flit_sel = allocated_q & match_q & ~full_prev;
      else
	assign flit_sel = allocated_q & match_q;
      
   endgenerate
   
   



   
   generate
      
      case(elig_mask)

	`ELIG_MASK_NONE:
	  begin
	     assign elig = ~allocated;
	  end

	`ELIG_MASK_FULL:
	  begin
	     assign elig = ~allocated & ~full;
	  end

	`ELIG_MASK_USED:
	  begin
	     assign elig = ~allocated & empty;
	  end
	
      endcase
      
   endgenerate
   
endmodule
module vcr_ovc_ctrl
  (clk, reset, vc_active, vc_gnt, vc_sel_ip, vc_sel_ivc, sw_active, sw_gnt, 
   sw_sel_ip, sw_sel_ivc, flit_valid, flit_tail, flit_sel, elig, full, 
   full_prev, empty);

   
`include "c_functions.v"
`include "c_constants.v"
`include "rtr_constants.v"
`include "vcr_constants.v"
   

   parameter num_vcs = 4;
   

   parameter num_ports = 5;
   

   parameter sw_alloc_spec = 1;
   

   parameter elig_mask = `ELIG_MASK_NONE;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   input clk;
   input reset;
   

   input vc_active;
   

   input vc_gnt;
   

   input [0:num_ports-1] vc_sel_ip;
   

   input [0:num_vcs-1] 	 vc_sel_ivc;
   

   input 		 sw_active;
   

   input 		 sw_gnt;
   

   input [0:num_ports-1] sw_sel_ip;
   

   input [0:num_vcs-1] 	 sw_sel_ivc;
   

   input 		 flit_valid;
   

   input 		 flit_tail;
   

   output 		 flit_sel;
   wire 		 flit_sel;
   

   output 		 elig;
   wire 		 elig;
   

   input 		 full;
   

   input 		 full_prev;
   

   input 		 empty;
   
   



   
   wire 		 alloc_active;
   assign alloc_active = vc_active | flit_valid;
   
   wire 		 allocated;
   
   wire 		 allocated_s, allocated_q;
   assign allocated_s = vc_gnt | allocated;
   c_dff
     #(.width(1),
       .reset_type(reset_type))
   allocatedq
     (.clk(clk),
      .reset(reset),
      .active(alloc_active),
      .d(allocated_s),
      .q(allocated_q));
   
   assign allocated = allocated_q & ~(flit_valid & flit_sel & flit_tail);
   
   wire [0:num_ports-1]  allocated_ip_s, allocated_ip_q;
   assign allocated_ip_s = allocated ? allocated_ip_q : vc_sel_ip;
   c_dff
     #(.width(num_ports),
       .reset_type(reset_type))
   allocated_ipq
     (.clk(clk),
      .reset(1'b0),
      .active(vc_active),
      .d(allocated_ip_s),
      .q(allocated_ip_q));
   
   wire 		 port_match;
   wire 		 vc_match;
   
   generate
      
      if(sw_alloc_spec)
	assign port_match = |(sw_sel_ip & allocated_ip_s);
      else
	assign port_match = |(sw_sel_ip & allocated_ip_q);
      
      if(num_vcs == 1)
	assign vc_match = 1'b1;
      else if(num_vcs > 1)
	begin
	   
	   wire [0:num_vcs-1] allocated_ivc_s, allocated_ivc_q;
	   assign allocated_ivc_s = allocated ? allocated_ivc_q : vc_sel_ivc;
	   c_dff
	     #(.width(num_vcs),
	       .reset_type(reset_type))
	   allocated_ivcq
	     (.clk(clk),
	      .reset(1'b0),
	      .active(vc_active),
	      .d(allocated_ivc_s),
	      .q(allocated_ivc_q));
	   
	   if(sw_alloc_spec)
	     assign vc_match = |(sw_sel_ivc & allocated_ivc_s);
	   else
	     assign vc_match = |(sw_sel_ivc & allocated_ivc_q);
	   
	end
      
   endgenerate
   
   wire 		      match_s, match_q;
   assign match_s = sw_gnt ? (port_match & vc_match) : match_q;
   c_dff
     #(.width(1),
       .reset_type(reset_type))
   matchq
     (.clk(clk),
      .reset(reset),
      .active(sw_active),
      .d(match_s),
      .q(match_q));
   
   generate
	 
      if(sw_alloc_spec && (elig_mask == `ELIG_MASK_NONE))
	assign flit_sel = allocated_q & match_q & ~full_prev;
      else
	assign flit_sel = allocated_q & match_q;
      
   endgenerate
   
   



   
   generate
      
      case(elig_mask)

	`ELIG_MASK_NONE:
	  begin
	     assign elig = ~allocated;
	  end

	`ELIG_MASK_FULL:
	  begin
	     assign elig = ~allocated & ~full;
	  end

	`ELIG_MASK_USED:
	  begin
	     assign elig = ~allocated & empty;
	  end
	
      endcase
      
   endgenerate
   
endmodule