data/full_repos/permissive/503137469/verilog/rtl/risc_spm/src/RISC_SPM.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/503137469/verilog/rtl/risc_spm/src/RISC_SPM.v:38: Signal definition not found, creating implicitly: \'write\'\n                              write, instruction, zero, clk, rst);\n                              ^~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/503137469/verilog/rtl/risc_spm/src/RISC_SPM.v:173: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'data_a\' generates 8 bits.\n                                                                                            : ... In instance RISC_SPM.M0_Processor.Mux_2\n  assign  mux_out = (sel == 0) ? data_a: (sel == 1) ? data_b : (sel == 2) ? data_c: \'bx;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/503137469/verilog/rtl/risc_spm/src/RISC_SPM.v:173: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'data_b\' generates 8 bits.\n                                                                                            : ... In instance RISC_SPM.M0_Processor.Mux_2\n  assign  mux_out = (sel == 0) ? data_a: (sel == 1) ? data_b : (sel == 2) ? data_c: \'bx;\n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/503137469/verilog/rtl/risc_spm/src/RISC_SPM.v:173: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'data_c\' generates 8 bits.\n                                                                                            : ... In instance RISC_SPM.M0_Processor.Mux_2\n  assign  mux_out = (sel == 0) ? data_a: (sel == 1) ? data_b : (sel == 2) ? data_c: \'bx;\n                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/503137469/verilog/rtl/risc_spm/src/RISC_SPM.v:173: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                            : ... In instance RISC_SPM.M0_Processor.Mux_2\n  assign  mux_out = (sel == 0) ? data_a: (sel == 1) ? data_b : (sel == 2) ? data_c: \'bx;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/503137469/verilog/rtl/risc_spm/src/RISC_SPM.v:160: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'data_a\' generates 8 bits.\n                                                                                            : ... In instance RISC_SPM.M0_Processor.Mux_1\n  assign  mux_out = (sel == 0) ? data_a: (sel == 1)\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/503137469/verilog/rtl/risc_spm/src/RISC_SPM.v:161: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'data_b\' generates 8 bits.\n                                                                                            : ... In instance RISC_SPM.M0_Processor.Mux_1\n                               ? data_b : (sel == 2)\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/503137469/verilog/rtl/risc_spm/src/RISC_SPM.v:162: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'data_c\' generates 8 bits.\n                                                                                            : ... In instance RISC_SPM.M0_Processor.Mux_1\n                               ? data_c: (sel == 3)\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/503137469/verilog/rtl/risc_spm/src/RISC_SPM.v:163: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'data_d\' generates 8 bits.\n                                                                                            : ... In instance RISC_SPM.M0_Processor.Mux_1\n                               ? data_d : (sel == 4)\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/503137469/verilog/rtl/risc_spm/src/RISC_SPM.v:164: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'data_e\' generates 8 bits.\n                                                                                            : ... In instance RISC_SPM.M0_Processor.Mux_1\n                               ? data_e : \'bx;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/503137469/verilog/rtl/risc_spm/src/RISC_SPM.v:160: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                            : ... In instance RISC_SPM.M0_Processor.Mux_1\n  assign  mux_out = (sel == 0) ? data_a: (sel == 1)\n                  ^\n%Error: Exiting due to 11 warning(s)\n'
module RISC_SPM #(parameter word_size = 8,
                    parameter Sel1_size = 3,
                    parameter Sel2_size = 2)(
    `ifdef USE_POWER_PINS
        inout vccd1,
        inout vssd1,
    `endif
     input clk, rst,
     input ext_write,
     input [word_size-1:0] data_bus, address_bus,
     output [word_size-1:0] memory_bus,
     output [word_size-1:0] io_oeb
     );

  wire [Sel1_size-1: 0] Sel_Bus_1_Mux;
  wire [Sel2_size-1: 0] Sel_Bus_2_Mux;


  wire zero;
  wire [word_size-1: 0] instruction, address, Bus_1, mem_word;

    assign io_oeb = 8'b0;


  assign memory_bus = mem_word;



  wire Load_R0, Load_R1, Load_R2, Load_R3, Load_PC, Inc_PC, Load_IR;   
  wire Load_Add_R, Load_Reg_Y, Load_Reg_Z;

  Processing_Unit M0_Processor (instruction, zero, address, Bus_1, mem_word, Load_R0, Load_R1,
                                Load_R2, Load_R3, Load_PC, Inc_PC, Sel_Bus_1_Mux, Load_IR,
                                Load_Add_R, Load_Reg_Y, Load_Reg_Z,  Sel_Bus_2_Mux, clk, rst);

  Control_Unit M1_Controller (Load_R0, Load_R1, Load_R2, Load_R3, Load_PC, Inc_PC, Sel_Bus_1_Mux, 
                              Sel_Bus_2_Mux , Load_IR, Load_Add_R, Load_Reg_Y, Load_Reg_Z, 
                              write, instruction, zero, clk, rst);

  Memory_Unit M2_MEM (.data_out(mem_word),
                       .data_in(Bus_1), 
                       .address(address), 
                       .clk(clk), 
                       .write(write),
                       .ext_write(ext_write),
                       .data_bus(data_bus),
                       .address_bus(address_bus));
endmodule
module RISC_SPM #(parameter word_size = 8,
                    parameter Sel1_size = 3,
                    parameter Sel2_size = 2)(
    `ifdef USE_POWER_PINS
        inout vccd1,
        inout vssd1,
    `endif
     input clk, rst,
     input ext_write,
     input [word_size-1:0] data_bus, address_bus,
     output [word_size-1:0] memory_bus,
     output [word_size-1:0] io_oeb
     );


  wire [Sel1_size-1: 0] Sel_Bus_1_Mux;
  wire [Sel2_size-1: 0] Sel_Bus_2_Mux;


  wire zero;
  wire [word_size-1: 0] instruction, address, Bus_1, mem_word;

    assign io_oeb = 8'b0;


  assign memory_bus = mem_word;



  wire Load_R0, Load_R1, Load_R2, Load_R3, Load_PC, Inc_PC, Load_IR;   
  wire Load_Add_R, Load_Reg_Y, Load_Reg_Z;

  Processing_Unit M0_Processor (instruction, zero, address, Bus_1, mem_word, Load_R0, Load_R1,
                                Load_R2, Load_R3, Load_PC, Inc_PC, Sel_Bus_1_Mux, Load_IR,
                                Load_Add_R, Load_Reg_Y, Load_Reg_Z,  Sel_Bus_2_Mux, clk, rst);

  Control_Unit M1_Controller (Load_R0, Load_R1, Load_R2, Load_R3, Load_PC, Inc_PC, Sel_Bus_1_Mux, 
                              Sel_Bus_2_Mux , Load_IR, Load_Add_R, Load_Reg_Y, Load_Reg_Z, 
                              write, instruction, zero, clk, rst);

  Memory_Unit M2_MEM (.data_out(mem_word),
                       .data_in(Bus_1), 
                       .address(address), 
                       .clk(clk), 
                       .write(write),
                       .ext_write(ext_write),
                       .data_bus(data_bus),
                       .address_bus(address_bus));
endmodule