data/full_repos/permissive/493847347/tests/s44_soft_test.v
1: b'%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:1: Cannot find include file: vcTest.v\n`include "vcTest.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/493847347/tests,data/full_repos/permissive/493847347/vcTest.v\n             data/full_repos/permissive/493847347/tests,data/full_repos/permissive/493847347/vcTest.v.v\n             data/full_repos/permissive/493847347/tests,data/full_repos/permissive/493847347/vcTest.v.sv\n             vcTest.v\n             vcTest.v.v\n             vcTest.v.sv\n             obj_dir/vcTest.v\n             obj_dir/vcTest.v.v\n             obj_dir/vcTest.v.sv\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:11: Define or directive not defined: \'`CLOCK_PERIOD\'\n  always #`CLOCK_PERIOD clk = ~clk;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:11: syntax error, unexpected \'=\'\n  always #`CLOCK_PERIOD clk = ~clk;\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/493847347/tests/s44_soft_test.v:11: Unsupported: Ignoring delay on this delayed statement.\n  always #`CLOCK_PERIOD clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:36: Define or directive not defined: \'`VC_TEST_SUITE_BEGIN\'\n  `VC_TEST_SUITE_BEGIN( "S44" )\n  ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:36: syntax error, unexpected \'(\'\n  `VC_TEST_SUITE_BEGIN( "S44" )\n                        ^~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:51: Unsupported or unknown PLI call: $vcdpluson\n    $vcdpluson;\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:52: Unsupported or unknown PLI call: $vcdplusoff\n    $vcdplusoff;\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:55: Define or directive not defined: \'`VC_TEST_CASE_BEGIN\'\n  `VC_TEST_CASE_BEGIN(0, "S44 LUT programming")\n  ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:55: syntax error, unexpected \'(\'\n  `VC_TEST_CASE_BEGIN(0, "S44 LUT programming")\n                      ^\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:58: Define or directive not defined: \'`CLOCK_PERIOD\'\n    #`CLOCK_PERIOD reset = 1\'b1;\n     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:59: Define or directive not defined: \'`CLOCK_PERIOD\'\n    #`CLOCK_PERIOD;\n     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:60: Define or directive not defined: \'`CLOCK_PERIOD\'\n    #`CLOCK_PERIOD reset = 1\'b0;\n     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:61: Define or directive not defined: \'`CLOCK_PERIOD\'\n    #`CLOCK_PERIOD;\n     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:64: syntax error, unexpected \'=\', expecting IDENTIFIER\n      sc_clk = 1\'b0;\n             ^\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:66: Define or directive not defined: \'`CLOCK_PERIOD\'\n      #`CLOCK_PERIOD\n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:68: Define or directive not defined: \'`CLOCK_PERIOD\'\n      #`CLOCK_PERIOD;\n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:70: syntax error, unexpected \'=\', expecting IDENTIFIER\n    sc_clk = 1\'b0;\n           ^\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:75: Define or directive not defined: \'`CLOCK_PERIOD\'\n    #`CLOCK_PERIOD;\n     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:77: Define or directive not defined: \'`CLOCK_PERIOD\'\n    #`CLOCK_PERIOD;\n     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:82: syntax error, unexpected $display\n      $display("FAIL: fracturing bit not correctly set");\n      ^~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:84: syntax error, unexpected $display\n      $display("OK  : fracturing bit corretly set");\n      ^~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:88: syntax error, unexpected $display\n      $display("FAIL: \\n\\tinput:\\t%b\\n\\tstored:\\t%b", mem_upper, dut.lut1.data);\n      ^~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:90: syntax error, unexpected $display\n      $display("OK  : input == output");\n      ^~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:94: syntax error, unexpected $display\n      $display("FAIL: \\n\\tinput:\\t%b\\n\\tstored:\\t%b", mem_lower, dut.lut0.data);\n      ^~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:96: syntax error, unexpected $display\n      $display("OK  : input == output");\n      ^~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:99: Define or directive not defined: \'`VC_TEST_CASE_END\'\n  `VC_TEST_CASE_END\n  ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:101: Define or directive not defined: \'`VC_TEST_CASE_BEGIN\'\n  `VC_TEST_CASE_BEGIN(1, "S44 LUT read - Not fractured")\n  ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:104: Define or directive not defined: \'`CLOCK_PERIOD\'\n    #`CLOCK_PERIOD reset = 1\'b1;\n     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:105: Define or directive not defined: \'`CLOCK_PERIOD\'\n    #`CLOCK_PERIOD;\n     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:106: Define or directive not defined: \'`CLOCK_PERIOD\'\n    #`CLOCK_PERIOD reset = 1\'b0;\n     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:107: Define or directive not defined: \'`CLOCK_PERIOD\'\n    #`CLOCK_PERIOD;\n     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:110: syntax error, unexpected \'=\', expecting IDENTIFIER\n      sc_clk = 1\'b0;\n             ^\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:112: Define or directive not defined: \'`CLOCK_PERIOD\'\n      #`CLOCK_PERIOD\n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:114: Define or directive not defined: \'`CLOCK_PERIOD\'\n      #`CLOCK_PERIOD;\n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:117: syntax error, unexpected \'=\', expecting IDENTIFIER\n    sc_clk = 1\'b0;\n           ^\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:122: Define or directive not defined: \'`CLOCK_PERIOD\'\n    #`CLOCK_PERIOD;\n     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:124: Define or directive not defined: \'`CLOCK_PERIOD\'\n    #`CLOCK_PERIOD;\n     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:132: syntax error, unexpected \'=\', expecting IDENTIFIER\n      lut_select0 = i;\n                  ^\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:135: syntax error, unexpected \'=\', expecting IDENTIFIER\n        lut_select1 = j;\n                    ^\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:145: syntax error, unexpected $display\n          $display("FAIL: i: %2d; s0: %2d -> z0: %b (expected %b)",\n          ^~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:148: syntax error, unexpected $display\n          $display("OK  : i: %2d; s0: %2d -> z0: %b (expected %b)",\n          ^~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:153: syntax error, unexpected $display\n          $display("FAIL: j: %2d; s1: %2d -> lut1_s: %b -> z1: %b (expected %b)",\n          ^~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:156: syntax error, unexpected $display\n          $display("OK  : j: %2d; s1: %2d -> lut1_s: %b -> z1: %b (expected %b)",\n          ^~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:161: syntax error, unexpected \'#\'\n    #100;\n    ^\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:164: Define or directive not defined: \'`VC_TEST_CASE_END\'\n  `VC_TEST_CASE_END\n  ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:166: Define or directive not defined: \'`VC_TEST_CASE_BEGIN\'\n  `VC_TEST_CASE_BEGIN(2, "S44 LUT read - Fractured")\n  ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:169: Define or directive not defined: \'`CLOCK_PERIOD\'\n    #`CLOCK_PERIOD reset = 1\'b1;\n     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:170: Define or directive not defined: \'`CLOCK_PERIOD\'\n    #`CLOCK_PERIOD;\n     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:171: Define or directive not defined: \'`CLOCK_PERIOD\'\n    #`CLOCK_PERIOD reset = 1\'b0;\n     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493847347/tests/s44_soft_test.v:172: Define or directive not defined: \'`CLOCK_PERIOD\'\n    #`CLOCK_PERIOD;\n     ^~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module S44Test;
  localparam K = 4;
  localparam N = 32;

  reg reset;


  reg clk = 0;
  always #`CLOCK_PERIOD clk = ~clk;

  reg sc_clk;
  reg [K-1:0] lut_select0 = {K{1'b0}};
  reg [K-1:0] lut_select1 = {K{1'b0}};
  reg sc_data;
  reg sc_data_out;

  wire lut_out0;
  wire lut_out1;

  S44 dut
  (
    .reset(reset),


    .sc_clk(sc_clk),
    .sc_data(sc_data),
    .s0(lut_select0),
    .s1(lut_select1),
    .sc_data_out(),
    .z0(lut_out0),
    .z1(lut_out1)
  );

  `VC_TEST_SUITE_BEGIN( "S44" )

  reg [N-1:0] mem;
  wire [N/2-1:0] mem_upper, mem_lower;
  assign mem_upper = mem[N-1:N/2];
  assign mem_lower = mem[N/2-1:0];
  reg [K-1:0] lut1_s;

  integer i, j;
  initial
  begin

    for (i = 0; i < N; i = i + 1) begin
      mem[i] = $random % 2;
    end
    $vcdpluson;
    $vcdplusoff;
  end

  `VC_TEST_CASE_BEGIN(0, "S44 LUT programming")
  begin

    #`CLOCK_PERIOD reset = 1'b1;
    #`CLOCK_PERIOD;
    #`CLOCK_PERIOD reset = 1'b0;
    #`CLOCK_PERIOD;

    for (i = 0; i < N; i = i + 1) begin
      sc_clk = 1'b0;
      sc_data = mem[i];
      #`CLOCK_PERIOD
      sc_clk = 1'b1;
      #`CLOCK_PERIOD;
    end
    sc_clk = 1'b0;


    sc_clk = 1'b0;
    sc_data = 1'b0;
    #`CLOCK_PERIOD;
    sc_clk = 1'b1;
    #`CLOCK_PERIOD;

    sc_clk = 1'b0;

    if (1'b0 != dut.fractured) begin
      $display("FAIL: fracturing bit not correctly set");
    end else begin
      $display("OK  : fracturing bit corretly set");
    end

    if (mem_upper != dut.lut1.data) begin
      $display("FAIL: \n\tinput:\t%b\n\tstored:\t%b", mem_upper, dut.lut1.data);
    end else begin
      $display("OK  : input == output");
    end

    if (mem_lower != dut.lut0.data) begin
      $display("FAIL: \n\tinput:\t%b\n\tstored:\t%b", mem_lower, dut.lut0.data);
    end else begin
      $display("OK  : input == output");
    end
  end
  `VC_TEST_CASE_END

  `VC_TEST_CASE_BEGIN(1, "S44 LUT read - Not fractured")
  begin

    #`CLOCK_PERIOD reset = 1'b1;
    #`CLOCK_PERIOD;
    #`CLOCK_PERIOD reset = 1'b0;
    #`CLOCK_PERIOD;

    for (i = 0; i < N; i = i + 1) begin
      sc_clk = 1'b0;
      sc_data = mem[i];
      #`CLOCK_PERIOD
      sc_clk = 1'b1;
      #`CLOCK_PERIOD;

    end
    sc_clk = 1'b0;


    sc_clk = 1'b0;
    sc_data = 1'b0;
    #`CLOCK_PERIOD;
    sc_clk = 1'b1;
    #`CLOCK_PERIOD;

    sc_clk = 1'b0;

    $display("Programming: \n\tinput:\t\t%b\n\tstored:\t\t%b %b\n\tfractured:\t%b",
             mem, dut.lut1.data, dut.lut0.data, dut.fractured);

    for (i = 0; i < N/2; i = i + 1) begin
      lut_select0 = i;

      for (j = 0; j < N/2; j = j + 1) begin
        lut_select1 = j;

        lut1_s = {lut_select1[3:1],mem_lower[lut_select0]};




        #1;

        if (lut_out0 != mem_lower[lut_select0]) begin
          $display("FAIL: i: %2d; s0: %2d -> z0: %b (expected %b)",
                   i, lut_select0, lut_out0, mem_lower[lut_select0]);
        end else begin
          $display("OK  : i: %2d; s0: %2d -> z0: %b (expected %b)",
                   i, lut_select0, lut_out0, mem_lower[lut_select0]);
        end

        if (lut_out1 != mem_upper[lut1_s]) begin
          $display("FAIL: j: %2d; s1: %2d -> lut1_s: %b -> z1: %b (expected %b)",
                   j, lut_select1, lut1_s, lut_out1, mem_upper[lut1_s]);
        end else begin
          $display("OK  : j: %2d; s1: %2d -> lut1_s: %b -> z1: %b (expected %b)",
                   j, lut_select1, lut1_s, lut_out1, mem_upper[lut1_s]);
        end
      end
    end
    #100;

  end
  `VC_TEST_CASE_END

  `VC_TEST_CASE_BEGIN(2, "S44 LUT read - Fractured")
  begin

    #`CLOCK_PERIOD reset = 1'b1;
    #`CLOCK_PERIOD;
    #`CLOCK_PERIOD reset = 1'b0;
    #`CLOCK_PERIOD;

    for (i = 0; i < N; i = i + 1) begin
      sc_clk = 1'b0;
      sc_data = mem[i];
      #`CLOCK_PERIOD
      sc_clk = 1'b1;
      #`CLOCK_PERIOD;

    end
    sc_clk = 1'b0;


    sc_clk = 1'b0;
    sc_data = 1'b1;
    #`CLOCK_PERIOD;
    sc_clk = 1'b1;
    #`CLOCK_PERIOD;

    sc_clk = 1'b0;

    $display("Programming: \n\tinput:\t\t%b\n\tstored:\t\t%b %b\n\tfractured:\t%b",
             mem, dut.lut1.data, dut.lut0.data, dut.fractured);

    for (i = 0; i < N/2; i = i + 1) begin
      lut_select0 = i;

      for (j = 0; j < N/2; j = j + 1) begin
        lut_select1 = j;

        lut1_s = {lut_select1[3:1],mem_lower[lut_select0]};




        #1;

        if (lut_out0 != mem_lower[lut_select0]) begin
          $display("FAIL: i: %2d; s0: %2d -> z0: %b (expected %b)",
                   i, lut_select0, lut_out0, mem_lower[lut_select0]);
        end else begin
          $display("OK  : i: %2d; s0: %2d -> z0: %b (expected %b)",
                   i, lut_select0, lut_out0, mem_lower[lut_select0]);
        end

        if (lut_out1 != mem_upper[lut_select1]) begin
          $display("FAIL: j: %2d; s1: %2d -> z1: %b (expected %b)",
                   j, lut_select1, lut_out1, mem_upper[lut_select1]);
        end else begin
          $display("OK  : j: %2d; s1: %2d -> z1: %b (expected %b)",
                   j, lut_select1, lut_out1, mem_upper[lut_select1]);
        end
      end
    end
    #100;

  end
  `VC_TEST_CASE_END

  `VC_TEST_SUITE_END( 3 )

endmodule
module S44Test;

  localparam K = 4;
  localparam N = 32;

  reg reset;


  reg clk = 0;
  always #`CLOCK_PERIOD clk = ~clk;

  reg sc_clk;
  reg [K-1:0] lut_select0 = {K{1'b0}};
  reg [K-1:0] lut_select1 = {K{1'b0}};
  reg sc_data;
  reg sc_data_out;

  wire lut_out0;
  wire lut_out1;

  S44 dut
  (
    .reset(reset),


    .sc_clk(sc_clk),
    .sc_data(sc_data),
    .s0(lut_select0),
    .s1(lut_select1),
    .sc_data_out(),
    .z0(lut_out0),
    .z1(lut_out1)
  );

  `VC_TEST_SUITE_BEGIN( "S44" )

  reg [N-1:0] mem;
  wire [N/2-1:0] mem_upper, mem_lower;
  assign mem_upper = mem[N-1:N/2];
  assign mem_lower = mem[N/2-1:0];
  reg [K-1:0] lut1_s;

  integer i, j;
  initial
  begin

    for (i = 0; i < N; i = i + 1) begin
      mem[i] = $random % 2;
    end
    $vcdpluson;
    $vcdplusoff;
  end

  `VC_TEST_CASE_BEGIN(0, "S44 LUT programming")
  begin

    #`CLOCK_PERIOD reset = 1'b1;
    #`CLOCK_PERIOD;
    #`CLOCK_PERIOD reset = 1'b0;
    #`CLOCK_PERIOD;

    for (i = 0; i < N; i = i + 1) begin
      sc_clk = 1'b0;
      sc_data = mem[i];
      #`CLOCK_PERIOD
      sc_clk = 1'b1;
      #`CLOCK_PERIOD;
    end
    sc_clk = 1'b0;


    sc_clk = 1'b0;
    sc_data = 1'b0;
    #`CLOCK_PERIOD;
    sc_clk = 1'b1;
    #`CLOCK_PERIOD;

    sc_clk = 1'b0;

    if (1'b0 != dut.fractured) begin
      $display("FAIL: fracturing bit not correctly set");
    end else begin
      $display("OK  : fracturing bit corretly set");
    end

    if (mem_upper != dut.lut1.data) begin
      $display("FAIL: \n\tinput:\t%b\n\tstored:\t%b", mem_upper, dut.lut1.data);
    end else begin
      $display("OK  : input == output");
    end

    if (mem_lower != dut.lut0.data) begin
      $display("FAIL: \n\tinput:\t%b\n\tstored:\t%b", mem_lower, dut.lut0.data);
    end else begin
      $display("OK  : input == output");
    end
  end
  `VC_TEST_CASE_END

  `VC_TEST_CASE_BEGIN(1, "S44 LUT read - Not fractured")
  begin

    #`CLOCK_PERIOD reset = 1'b1;
    #`CLOCK_PERIOD;
    #`CLOCK_PERIOD reset = 1'b0;
    #`CLOCK_PERIOD;

    for (i = 0; i < N; i = i + 1) begin
      sc_clk = 1'b0;
      sc_data = mem[i];
      #`CLOCK_PERIOD
      sc_clk = 1'b1;
      #`CLOCK_PERIOD;

    end
    sc_clk = 1'b0;


    sc_clk = 1'b0;
    sc_data = 1'b0;
    #`CLOCK_PERIOD;
    sc_clk = 1'b1;
    #`CLOCK_PERIOD;

    sc_clk = 1'b0;

    $display("Programming: \n\tinput:\t\t%b\n\tstored:\t\t%b %b\n\tfractured:\t%b",
             mem, dut.lut1.data, dut.lut0.data, dut.fractured);

    for (i = 0; i < N/2; i = i + 1) begin
      lut_select0 = i;

      for (j = 0; j < N/2; j = j + 1) begin
        lut_select1 = j;

        lut1_s = {lut_select1[3:1],mem_lower[lut_select0]};




        #1;

        if (lut_out0 != mem_lower[lut_select0]) begin
          $display("FAIL: i: %2d; s0: %2d -> z0: %b (expected %b)",
                   i, lut_select0, lut_out0, mem_lower[lut_select0]);
        end else begin
          $display("OK  : i: %2d; s0: %2d -> z0: %b (expected %b)",
                   i, lut_select0, lut_out0, mem_lower[lut_select0]);
        end

        if (lut_out1 != mem_upper[lut1_s]) begin
          $display("FAIL: j: %2d; s1: %2d -> lut1_s: %b -> z1: %b (expected %b)",
                   j, lut_select1, lut1_s, lut_out1, mem_upper[lut1_s]);
        end else begin
          $display("OK  : j: %2d; s1: %2d -> lut1_s: %b -> z1: %b (expected %b)",
                   j, lut_select1, lut1_s, lut_out1, mem_upper[lut1_s]);
        end
      end
    end
    #100;

  end
  `VC_TEST_CASE_END

  `VC_TEST_CASE_BEGIN(2, "S44 LUT read - Fractured")
  begin

    #`CLOCK_PERIOD reset = 1'b1;
    #`CLOCK_PERIOD;
    #`CLOCK_PERIOD reset = 1'b0;
    #`CLOCK_PERIOD;

    for (i = 0; i < N; i = i + 1) begin
      sc_clk = 1'b0;
      sc_data = mem[i];
      #`CLOCK_PERIOD
      sc_clk = 1'b1;
      #`CLOCK_PERIOD;

    end
    sc_clk = 1'b0;


    sc_clk = 1'b0;
    sc_data = 1'b1;
    #`CLOCK_PERIOD;
    sc_clk = 1'b1;
    #`CLOCK_PERIOD;

    sc_clk = 1'b0;

    $display("Programming: \n\tinput:\t\t%b\n\tstored:\t\t%b %b\n\tfractured:\t%b",
             mem, dut.lut1.data, dut.lut0.data, dut.fractured);

    for (i = 0; i < N/2; i = i + 1) begin
      lut_select0 = i;

      for (j = 0; j < N/2; j = j + 1) begin
        lut_select1 = j;

        lut1_s = {lut_select1[3:1],mem_lower[lut_select0]};




        #1;

        if (lut_out0 != mem_lower[lut_select0]) begin
          $display("FAIL: i: %2d; s0: %2d -> z0: %b (expected %b)",
                   i, lut_select0, lut_out0, mem_lower[lut_select0]);
        end else begin
          $display("OK  : i: %2d; s0: %2d -> z0: %b (expected %b)",
                   i, lut_select0, lut_out0, mem_lower[lut_select0]);
        end

        if (lut_out1 != mem_upper[lut_select1]) begin
          $display("FAIL: j: %2d; s1: %2d -> z1: %b (expected %b)",
                   j, lut_select1, lut_out1, mem_upper[lut_select1]);
        end else begin
          $display("OK  : j: %2d; s1: %2d -> z1: %b (expected %b)",
                   j, lut_select1, lut_out1, mem_upper[lut_select1]);
        end
      end
    end
    #100;

  end
  `VC_TEST_CASE_END

  `VC_TEST_SUITE_END( 3 )

endmodule