data/full_repos/permissive/50192283/mmio.sv
1: b'%Warning-LITENDIAN: data/full_repos/permissive/50192283/mmio.sv:8: Little bit endian vector: MSB < LSB of bit range: 0:23\n  input  [0:23] ha_mmad,        \n         ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/50192283/mmio.sv:10: Little bit endian vector: MSB < LSB of bit range: 0:63\n  input  [0:63] ha_mmdata,      \n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/50192283/mmio.sv:13: Little bit endian vector: MSB < LSB of bit range: 0:63\n  output [0:63] ah_mmdata_out,  \n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/50192283/mmio.sv:17: Little bit endian vector: MSB < LSB of bit range: 0:63\n  reg [0:63] ah_mmdata;\n      ^\n%Error: data/full_repos/permissive/50192283/mmio.sv:19: Cannot find file containing module: \'shift_register\'\n  shift_register mmack_shift(\n  ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/50192283,data/full_repos/permissive/50192283/shift_register\n             data/full_repos/permissive/50192283,data/full_repos/permissive/50192283/shift_register.v\n             data/full_repos/permissive/50192283,data/full_repos/permissive/50192283/shift_register.sv\n             shift_register\n             shift_register.v\n             shift_register.sv\n             obj_dir/shift_register\n             obj_dir/shift_register.v\n             obj_dir/shift_register.sv\n%Error: data/full_repos/permissive/50192283/mmio.sv:24: Cannot find file containing module: \'shift_register\'\n  shift_register #(64) mmdata_shift(\n  ^~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n'
module mmio (
  input         ha_pclock,

  input         ha_mmval,
  input         ha_mmcfg,
  input         ha_mmrnw,
  input         ha_mmdw,
  input  [0:23] ha_mmad,
  input         ha_mmadpar,
  input  [0:63] ha_mmdata,
  input         ha_mmdatapar,
  output        ah_mmack_out,
  output [0:63] ah_mmdata_out,
  output        ah_mmdatapar);

  reg ah_mmack;
  reg [0:63] ah_mmdata;

  shift_register mmack_shift(
    .clock(ha_pclock),
    .in(ah_mmack),
    .out(ah_mmack_out));

  shift_register #(64) mmdata_shift(
    .clock(ha_pclock),
    .in(ah_mmdata),
    .out(ah_mmdata_out));

  assign ah_mmdatapar = ~^ah_mmdata_out;


  always @ (posedge ha_pclock)
  begin
    if(ha_mmval & ha_mmcfg & ha_mmrnw)
    begin
      $display("AFU decriptor request");
      case(ha_mmad)
        'h0: begin
          ah_mmack <= 1;
          ah_mmdata <= 64'h0000000100010010;
        end
        'h8: begin
          ah_mmack <= 1;
          ah_mmdata <= 64'h0000000000000001;
        end
        'hA: begin
          ah_mmack <= 1;
          ah_mmdata <= 64'h0000000000000100;
        end
        'hE: begin
          ah_mmack <= 1;
          ah_mmdata <= 64'h0100000000000000;
        end
        default: begin
          ah_mmack <= 1;
          ah_mmdata <= 64'h0000000000000000;
        end
      endcase
    end else begin
      ah_mmack <= 0;
      ah_mmdata <= 0;
    end
  end

endmodule
module mmio (
  input         ha_pclock,

  input         ha_mmval,
  input         ha_mmcfg,
  input         ha_mmrnw,
  input         ha_mmdw,
  input  [0:23] ha_mmad,
  input         ha_mmadpar,
  input  [0:63] ha_mmdata,
  input         ha_mmdatapar,
  output        ah_mmack_out,
  output [0:63] ah_mmdata_out,
  output        ah_mmdatapar);


  reg ah_mmack;
  reg [0:63] ah_mmdata;

  shift_register mmack_shift(
    .clock(ha_pclock),
    .in(ah_mmack),
    .out(ah_mmack_out));

  shift_register #(64) mmdata_shift(
    .clock(ha_pclock),
    .in(ah_mmdata),
    .out(ah_mmdata_out));

  assign ah_mmdatapar = ~^ah_mmdata_out;


  always @ (posedge ha_pclock)
  begin
    if(ha_mmval & ha_mmcfg & ha_mmrnw)
    begin
      $display("AFU decriptor request");
      case(ha_mmad)
        'h0: begin
          ah_mmack <= 1;
          ah_mmdata <= 64'h0000000100010010;
        end
        'h8: begin
          ah_mmack <= 1;
          ah_mmdata <= 64'h0000000000000001;
        end
        'hA: begin
          ah_mmack <= 1;
          ah_mmdata <= 64'h0000000000000100;
        end
        'hE: begin
          ah_mmack <= 1;
          ah_mmdata <= 64'h0100000000000000;
        end
        default: begin
          ah_mmack <= 1;
          ah_mmdata <= 64'h0000000000000000;
        end
      endcase
    end else begin
      ah_mmack <= 0;
      ah_mmdata <= 0;
    end
  end

endmodule