data/full_repos/permissive/482470447/verilog/adder16_8.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/482470447/verilog/adder16_8.v:6: Signal definition not found, creating implicitly: \'c2\'\n        assign sum[16] = c2;\n                         ^~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/482470447/verilog/adder16_8.v:4: Cannot find file containing module: \'blockSize8\'\n        blockSize8 b0(a[7:0],b[7:0],1\'b0,sum[7:0],c1);\n        ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/482470447/verilog,data/full_repos/permissive/482470447/blockSize8\n             data/full_repos/permissive/482470447/verilog,data/full_repos/permissive/482470447/blockSize8.v\n             data/full_repos/permissive/482470447/verilog,data/full_repos/permissive/482470447/blockSize8.sv\n             blockSize8\n             blockSize8.v\n             blockSize8.sv\n             obj_dir/blockSize8\n             obj_dir/blockSize8.v\n             obj_dir/blockSize8.sv\n%Error: data/full_repos/permissive/482470447/verilog/adder16_8.v:5: Cannot find file containing module: \'blockSize8\'\n blockSize8 b1 (a[15:8],b[15:8],c1,sum[15:8],c2);\n ^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module adder16_8(a,b,sum);
        input[15:0] a,b;
        output[16:0]sum;
        blockSize8 b0(a[7:0],b[7:0],1'b0,sum[7:0],c1);
	blockSize8 b1 (a[15:8],b[15:8],c1,sum[15:8],c2);
        assign sum[16] = c2;
endmodule
module adder16_8(a,b,sum);

        input[15:0] a,b;
        output[16:0]sum;
        blockSize8 b0(a[7:0],b[7:0],1'b0,sum[7:0],c1);
	blockSize8 b1 (a[15:8],b[15:8],c1,sum[15:8],c2);
        assign sum[16] = c2;
endmodule