data/full_repos/permissive/519567026/Simulation File/MIPS_Single_Cycle.srcs/sources_1/new/Register.v
1: b'%Error: Cannot find file containing module: File/MIPS_Single_Cycle.srcs/sources_1/new,data/full_repos/permissive/519567026\n        ... Looked in:\n             data/full_repos/permissive/519567026/Simulation/File/MIPS_Single_Cycle.srcs/sources_1/new,data/full_repos/permissive/519567026\n             data/full_repos/permissive/519567026/Simulation/File/MIPS_Single_Cycle.srcs/sources_1/new,data/full_repos/permissive/519567026.v\n             data/full_repos/permissive/519567026/Simulation/File/MIPS_Single_Cycle.srcs/sources_1/new,data/full_repos/permissive/519567026.sv\n             File/MIPS_Single_Cycle.srcs/sources_1/new,data/full_repos/permissive/519567026\n             File/MIPS_Single_Cycle.srcs/sources_1/new,data/full_repos/permissive/519567026.v\n             File/MIPS_Single_Cycle.srcs/sources_1/new,data/full_repos/permissive/519567026.sv\n             obj_dir/File/MIPS_Single_Cycle.srcs/sources_1/new,data/full_repos/permissive/519567026\n             obj_dir/File/MIPS_Single_Cycle.srcs/sources_1/new,data/full_repos/permissive/519567026.v\n             obj_dir/File/MIPS_Single_Cycle.srcs/sources_1/new,data/full_repos/permissive/519567026.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/519567026/Simulation\n%Error: Cannot find file containing module: File/MIPS_Single_Cycle.srcs/sources_1/new/Register.v\n%Error: Exiting due to 3 error(s)\n'
module Register (
    input clk,
    input [31:0] instruction,
    input RegWrite,
    input RegDst,
    input [31:0] WriteData,
    output [31:0] ReadData1,
    output [31:0] ReadData2
);

  reg [31:0] RegData[31:0];


  integer i;
  initial begin
    for (i = 0; i < 32; i = i + 1) begin
      RegData[i] = 32'b0;
    end
  end

  assign ReadData1 = RegData[instruction[25:21]];
  assign ReadData2 = RegData[instruction[20:16]];

  always @(posedge clk) begin
    if (RegWrite == 1'b1) begin

      if (RegDst == 1'b0) begin
        RegData[instruction[20:16]] = WriteData;
      end else begin
        RegData[instruction[15:11]] = WriteData;
      end
    end
  end

endmodule
module Register (
    input clk,
    input [31:0] instruction,
    input RegWrite,
    input RegDst,
    input [31:0] WriteData,
    output [31:0] ReadData1,
    output [31:0] ReadData2
);


  reg [31:0] RegData[31:0];


  integer i;
  initial begin
    for (i = 0; i < 32; i = i + 1) begin
      RegData[i] = 32'b0;
    end
  end

  assign ReadData1 = RegData[instruction[25:21]];
  assign ReadData2 = RegData[instruction[20:16]];

  always @(posedge clk) begin
    if (RegWrite == 1'b1) begin

      if (RegDst == 1'b0) begin
        RegData[instruction[20:16]] = WriteData;
      end else begin
        RegData[instruction[15:11]] = WriteData;
      end
    end
  end

endmodule