data/full_repos/permissive/503175397/rtl/audio.sv
1: b"%Error: data/full_repos/permissive/503175397/rtl/audio.sv:53: Found definition of 'volume' as a VAR but expected a task/function\n    7'h17: volume;\n           ^~~~~~\n%Error: data/full_repos/permissive/503175397/rtl/audio.sv:55: Can't find definition of variable: 'timer_0_div'\n    7'h20: timer_0_div <= din;\n           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/503175397/rtl/audio.sv:56: Can't find definition of variable: 'timer_int'\n    7'h21: timer_int <= din;\n           ^~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module audio
(
	input clk,
	input [6:0] AB,
	input reset,
	input ce,
	input sys_cs,
	input cpu_rwn,
	input din
);



reg [11:0] sq1_freq, sq2_freq_ps;

reg [7:0] audio_ctl, volume;

wire [3:0] audio_mode = audio_ctl[3:0];
wire [2:0] prescaler = audio_ctl[6:4];






















always_ff @(posedge clk) begin
	if (ce) begin
		if (cpu_rwn && sys_cs) begin
			case (AB)
				7'h10: sq1_freq[7:0] <= din;
				7'h11: sq1_freq[11:8] <= din[3:0];
				7'h12: sq2_freq_ps[7:0] <= din;
				7'h13: sq2_freq_ps[11:8] <= din[3:0];
				7'h14: ;
				7'h15: ;
				7'h16: audio_ctl <= din;
				7'h17: volume;

				7'h20: timer_0_div <= din;
				7'h21: timer_int <= din;
				7'h22: ;
				7'h23: ;
				7'h24: ;
				7'h25: ;
				7'h26: ;
				
			endcase
		end
	end
end

endmodule
module audio
(
	input clk,
	input [6:0] AB,
	input reset,
	input ce,
	input sys_cs,
	input cpu_rwn,
	input din
);




reg [11:0] sq1_freq, sq2_freq_ps;

reg [7:0] audio_ctl, volume;

wire [3:0] audio_mode = audio_ctl[3:0];
wire [2:0] prescaler = audio_ctl[6:4];






















always_ff @(posedge clk) begin
	if (ce) begin
		if (cpu_rwn && sys_cs) begin
			case (AB)
				7'h10: sq1_freq[7:0] <= din;
				7'h11: sq1_freq[11:8] <= din[3:0];
				7'h12: sq2_freq_ps[7:0] <= din;
				7'h13: sq2_freq_ps[11:8] <= din[3:0];
				7'h14: ;
				7'h15: ;
				7'h16: audio_ctl <= din;
				7'h17: volume;

				7'h20: timer_0_div <= din;
				7'h21: timer_int <= din;
				7'h22: ;
				7'h23: ;
				7'h24: ;
				7'h25: ;
				7'h26: ;
				
			endcase
		end
	end
end

endmodule