data/full_repos/permissive/529953906/openlane/pdm/src/pdm_core.v
1: b'%Warning-WIDTH: data/full_repos/permissive/529953906/openlane/pdm/src/pdm_core.v:28: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 7 bits.\n                                                                                   : ... In instance pdm_core\n        input_reg <=    {(BITWIDTH-1){1\'b0}};\n                  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/529953906/openlane/pdm/src/pdm_core.v:29: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 7 bits.\n                                                                                   : ... In instance pdm_core\n        accumulator <=  {(BITWIDTH-1){1\'b0}};\n                    ^~\n%Error: Exiting due to 2 warning(s)\n'
module pdm_core #(
    parameter BITWIDTH=8) (
    input [7:0] pdm_input,
    input       write_en,
    input       clk, reset_n,    
    output      pdm_out
);

`ifdef COCOTB_SIM_WAVEFORMS
initial begin
    $dumpfile("pdm_core.vcd");
    $dumpvars(0, pdm_core);
end
`endif

reg [BITWIDTH-1:0] accumulator;
reg [BITWIDTH-1:0] input_reg;

wire [BITWIDTH:0] sum;

assign sum = input_reg + accumulator;
assign pdm_out = sum[BITWIDTH];

always @(posedge clk or negedge reset_n) begin
    if (~reset_n) begin 
        input_reg <=    {(BITWIDTH-1){1'b0}};
        accumulator <=  {(BITWIDTH-1){1'b0}};
    end else begin
        accumulator <= sum[BITWIDTH-1:0];
        if (write_en) input_reg <= pdm_input ;
    end
end

endmodule
module pdm_core #(
    parameter BITWIDTH=8) (
    input [7:0] pdm_input,
    input       write_en,
    input       clk, reset_n,    
    output      pdm_out
);


`ifdef COCOTB_SIM_WAVEFORMS
initial begin
    $dumpfile("pdm_core.vcd");
    $dumpvars(0, pdm_core);
end
`endif

reg [BITWIDTH-1:0] accumulator;
reg [BITWIDTH-1:0] input_reg;

wire [BITWIDTH:0] sum;

assign sum = input_reg + accumulator;
assign pdm_out = sum[BITWIDTH];

always @(posedge clk or negedge reset_n) begin
    if (~reset_n) begin 
        input_reg <=    {(BITWIDTH-1){1'b0}};
        accumulator <=  {(BITWIDTH-1){1'b0}};
    end else begin
        accumulator <= sum[BITWIDTH-1:0];
        if (write_en) input_reg <= pdm_input ;
    end
end

endmodule