data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Counters/Count_clock_4/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Counters/Count_clock_4,data/full_repos/permissive/500128826\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/Count_clock_4,data/full_repos/permissive/500128826\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/Count_clock_4,data/full_repos/permissive/500128826.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/Count_clock_4,data/full_repos/permissive/500128826.sv\n             Logic/Counters/Count_clock_4,data/full_repos/permissive/500128826\n             Logic/Counters/Count_clock_4,data/full_repos/permissive/500128826.v\n             Logic/Counters/Count_clock_4,data/full_repos/permissive/500128826.sv\n             obj_dir/Logic/Counters/Count_clock_4,data/full_repos/permissive/500128826\n             obj_dir/Logic/Counters/Count_clock_4,data/full_repos/permissive/500128826.v\n             obj_dir/Logic/Counters/Count_clock_4,data/full_repos/permissive/500128826.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Logic/Counters/Count_clock_4/top_module.v\n%Error: Exiting due to 3 error(s)\n'
module bcd24h2complex12h (
    input wire [23:0] bcd24h,
    output reg pm,
    output reg [23:0] bcd12h
);

  always @(*) begin
    if (bcd24h >= 24'h000000 & bcd24h < 24'h010000) begin
      bcd12h = bcd24h + 24'h120000;
    end else if (bcd24h >= 24'h130000 & bcd24h < 24'h200000) begin
      bcd12h = bcd24h - 24'h120000;
    end else if (bcd24h >= 24'h200000 & bcd24h < 24'h220000) begin
      bcd12h = bcd24h - 24'h180000;
    end else if (bcd24h >= 24'h220000) begin
      bcd12h = bcd24h - 24'h120000;
    end else begin
      bcd12h = bcd24h;
    end

    if (bcd24h < 24'h120000) pm = 0;
    else pm = 1;
  end
endmodule
module bcd24h2complex12h (
    input wire [23:0] bcd24h,
    output reg pm,
    output reg [23:0] bcd12h
);


  always @(*) begin
    if (bcd24h >= 24'h000000 & bcd24h < 24'h010000) begin
      bcd12h = bcd24h + 24'h120000;
    end else if (bcd24h >= 24'h130000 & bcd24h < 24'h200000) begin
      bcd12h = bcd24h - 24'h120000;
    end else if (bcd24h >= 24'h200000 & bcd24h < 24'h220000) begin
      bcd12h = bcd24h - 24'h180000;
    end else if (bcd24h >= 24'h220000) begin
      bcd12h = bcd24h - 24'h120000;
    end else begin
      bcd12h = bcd24h;
    end

    if (bcd24h < 24'h120000) pm = 0;
    else pm = 1;
  end
endmodule