data/full_repos/permissive/479923049/alu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/479923049/alu.v:43: Operator XOR expects 16 bits on the LHS, but LHS\'s SEL generates 15 bits.\n                                                             : ... In instance ALU.addsub\n    assign {c1, s[14:0]} = a[14:0] + (b[14:0] ^ {15{sub}}) + sub;\n                                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/479923049/alu.v:43: Operator XOR expects 16 bits on the RHS, but RHS\'s REPLICATE generates 15 bits.\n                                                             : ... In instance ALU.addsub\n    assign {c1, s[14:0]} = a[14:0] + (b[14:0] ^ {15{sub}}) + sub;\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/479923049/alu.v:43: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'sub\' generates 1 bits.\n                                                             : ... In instance ALU.addsub\n    assign {c1, s[14:0]} = a[14:0] + (b[14:0] ^ {15{sub}}) + sub;\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/479923049/alu.v:45: Operator XOR expects 2 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                             : ... In instance ALU.addsub\n    assign {c2, s[15]} = a[15] + (b[15] ^ sub) + c1;\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/479923049/alu.v:45: Operator XOR expects 2 bits on the RHS, but RHS\'s VARREF \'sub\' generates 1 bits.\n                                                             : ... In instance ALU.addsub\n    assign {c2, s[15]} = a[15] + (b[15] ^ sub) + c1;\n                                        ^\n%Error: Exiting due to 5 warning(s)\n'
module AddSub(a, b, sub, s, ovf) ;
    input [15:0] a,b;
    input sub ;
    output [15:0] s;
    output ovf;
    wire c1, c2;
    assign ovf = c1 ^ c2;


    assign {c1, s[14:0]} = a[14:0] + (b[14:0] ^ {15{sub}}) + sub;

    assign {c2, s[15]} = a[15] + (b[15] ^ sub) + c1;
endmodule
module AddSub(a, b, sub, s, ovf) ;

    input [15:0] a,b;
    input sub ;
    output [15:0] s;
    output ovf;
    wire c1, c2;
    assign ovf = c1 ^ c2;


    assign {c1, s[14:0]} = a[14:0] + (b[14:0] ^ {15{sub}}) + sub;

    assign {c2, s[15]} = a[15] + (b[15] ^ sub) + c1;
endmodule