data/full_repos/permissive/429196919/FPGA/latchReg/latchReg_TB.v
1: b'%Error: data/full_repos/permissive/429196919/FPGA/latchReg/latchReg_TB.v:24: Cannot find include file: ../genericIOSateliteEnv.v\n`include "../genericIOSateliteEnv.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/429196919/FPGA/latchReg,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v\n             data/full_repos/permissive/429196919/FPGA/latchReg,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v.v\n             data/full_repos/permissive/429196919/FPGA/latchReg,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v.sv\n             ../genericIOSateliteEnv.v\n             ../genericIOSateliteEnv.v.v\n             ../genericIOSateliteEnv.v.sv\n             obj_dir/../genericIOSateliteEnv.v\n             obj_dir/../genericIOSateliteEnv.v.v\n             obj_dir/../genericIOSateliteEnv.v.sv\n%Error: data/full_repos/permissive/429196919/FPGA/latchReg/latchReg_TB.v:25: Cannot find include file: ../genericIOSateliteEnv_TB.v\n`include "../genericIOSateliteEnv_TB.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/latchReg/latchReg_TB.v:26: Cannot find include file: latchReg.v\n`include "latchReg.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/latchReg/latchReg_TB.v:34: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n reg[31:0] expect;\n           ^~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/latchReg/latchReg_TB.v:34: syntax error, unexpected \';\', expecting IDENTIFIER or \'=\' or do or final\n reg[31:0] expect;\n                 ^\n%Error: data/full_repos/permissive/429196919/FPGA/latchReg/latchReg_TB.v:39: Define or directive not defined: \'`OSCH_FREQ\'\n OSCH #(.NOM_FREQ(`OSCH_FREQ)) internal_oscillator_inst (.STDBY(1\'b0), .OSC(masterClk), .SEDSTDBY ());\n                  ^~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/429196919/FPGA/latchReg/latchReg_TB.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/429196919/FPGA/latchReg/latchReg_TB.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/429196919/FPGA/latchReg/latchReg_TB.v:52: Define or directive not defined: \'`CHECK_WIRE_32\'\n  `CHECK_WIRE_32("latchReg", latchOutput, 8\'h00, 8\'h00, 8\'h00, 8\'h00)\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/latchReg/latchReg_TB.v:52: syntax error, unexpected \',\'\n  `CHECK_WIRE_32("latchReg", latchOutput, 8\'h00, 8\'h00, 8\'h00, 8\'h00)\n                           ^\n%Error: data/full_repos/permissive/429196919/FPGA/latchReg/latchReg_TB.v:57: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n  expect = 32\'h0001;\n  ^~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/latchReg/latchReg_TB.v:57: syntax error, unexpected \'=\'\n  expect = 32\'h0001;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/429196919/FPGA/latchReg/latchReg_TB.v:60: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Error: data/full_repos/permissive/429196919/FPGA/latchReg/latchReg_TB.v:61: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n   if(latchOutput === expect)\n                      ^~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/latchReg/latchReg_TB.v:61: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   if(latchOutput === expect)\n                            ^\n%Error: data/full_repos/permissive/429196919/FPGA/latchReg/latchReg_TB.v:62: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n    $display("latchReg: PASS: latchoutput was as expected, expected: %b, detected: %b", expect, latchOutput);\n                                                                                        ^~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/latchReg/latchReg_TB.v:64: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n    $display("latchReg: ERROR: latchoutput was not as expected, expected: %b, detected: %b", expect, latchOutput);\n                                                                                             ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/429196919/FPGA/latchReg/latchReg_TB.v:68: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Error: data/full_repos/permissive/429196919/FPGA/latchReg/latchReg_TB.v:70: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n   expect = (expect << 1) | 32\'h0001;\n   ^~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/latchReg/latchReg_TB.v:70: syntax error, unexpected \'=\'\n   expect = (expect << 1) | 32\'h0001;\n          ^\n%Error: data/full_repos/permissive/429196919/FPGA/latchReg/latchReg_TB.v:70: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n   expect = (expect << 1) | 32\'h0001;\n             ^~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/latchReg/latchReg_TB.v:74: syntax error, unexpected \'=\', expecting IDENTIFIER\n  latchInput = 32\'h0000;\n             ^\n%Error: data/full_repos/permissive/429196919/FPGA/latchReg/latchReg_TB.v:79: Define or directive not defined: \'`CHECK_WIRE_32\'\n  `CHECK_WIRE_32("latchReg", latchOutput, 8\'h00, 8\'h00, 8\'h00, 8\'h00)\n  ^~~~~~~~~~~~~~\n%Error: Cannot continue\n'
module latchReg_TB ();
	wire masterClk;
	reg[31:0] latchInput;
	reg reset;
	wire[31:0] latchOutput;
	reg[31:0] latchStimuli;
	reg[31:0] expect;

	integer i;

	latchReg #(.WIDTH(32)) DUT(.masterClk(masterClk), .latchInput(latchInput), .reset(reset), .latchOutput(latchOutput));
	OSCH #(.NOM_FREQ(`OSCH_FREQ)) internal_oscillator_inst (.STDBY(1'b0), .OSC(masterClk), .SEDSTDBY ());
	
	initial begin
		$display("latchReg: Running simulation for a 32 bit latch reg");
		$display("latchReg: Initializing simulation for WS2811Decoder");

		reset = 0;
		latchInput = 32'h0000;
		#100;


		reset = 1;
		#100;
		`CHECK_WIRE_32("latchReg", latchOutput, 8'h00, 8'h00, 8'h00, 8'h00)
		#100;


		latchStimuli = 32'h0001;
		expect = 32'h0001;
		for(i=0; i<32; i=i+1) begin
			latchInput = latchStimuli;
			#100;
			if(latchOutput === expect)
				$display("latchReg: PASS: latchoutput was as expected, expected: %b, detected: %b", expect, latchOutput);
			else begin
				$display("latchReg: ERROR: latchoutput was not as expected, expected: %b, detected: %b", expect, latchOutput);
				$display("latchReg: Stoping simulation");
				$stop;
			end
			#100;
			latchStimuli = latchStimuli << 1;
			expect = (expect << 1) | 32'h0001;
		end


		latchInput = 32'h0000;
		reset = 0;
		#100;
		reset = 1;
		#100;
		`CHECK_WIRE_32("latchReg", latchOutput, 8'h00, 8'h00, 8'h00, 8'h00)
		$display("latchReg: Simulation successful");
		$stop;
	end
endmodule
module latchReg_TB ();

	wire masterClk;
	reg[31:0] latchInput;
	reg reset;
	wire[31:0] latchOutput;
	reg[31:0] latchStimuli;
	reg[31:0] expect;

	integer i;

	latchReg #(.WIDTH(32)) DUT(.masterClk(masterClk), .latchInput(latchInput), .reset(reset), .latchOutput(latchOutput));
	OSCH #(.NOM_FREQ(`OSCH_FREQ)) internal_oscillator_inst (.STDBY(1'b0), .OSC(masterClk), .SEDSTDBY ());
	
	initial begin
		$display("latchReg: Running simulation for a 32 bit latch reg");
		$display("latchReg: Initializing simulation for WS2811Decoder");

		reset = 0;
		latchInput = 32'h0000;
		#100;


		reset = 1;
		#100;
		`CHECK_WIRE_32("latchReg", latchOutput, 8'h00, 8'h00, 8'h00, 8'h00)
		#100;


		latchStimuli = 32'h0001;
		expect = 32'h0001;
		for(i=0; i<32; i=i+1) begin
			latchInput = latchStimuli;
			#100;
			if(latchOutput === expect)
				$display("latchReg: PASS: latchoutput was as expected, expected: %b, detected: %b", expect, latchOutput);
			else begin
				$display("latchReg: ERROR: latchoutput was not as expected, expected: %b, detected: %b", expect, latchOutput);
				$display("latchReg: Stoping simulation");
				$stop;
			end
			#100;
			latchStimuli = latchStimuli << 1;
			expect = (expect << 1) | 32'h0001;
		end


		latchInput = 32'h0000;
		reset = 0;
		#100;
		reset = 1;
		#100;
		`CHECK_WIRE_32("latchReg", latchOutput, 8'h00, 8'h00, 8'h00, 8'h00)
		$display("latchReg: Simulation successful");
		$stop;
	end
endmodule