data/full_repos/permissive/471533249/register.sv
data/verilator_xmls/4c77b4e1-07b8-4ab3-a52c-62c61ba5f5ec.xml
module register
	# (parameter width = 16)
	(input logic clk, reset, load_en,
		input logic [width-1:0] D,
		output logic [width-1:0] Q);
		
		always_ff @(posedge clk)
			if (reset) Q = 0;
			else if (load_en) Q = D;
endmodule
module register
	# (parameter width = 16)
	(input logic clk, reset, load_en,
		input logic [width-1:0] D,
		output logic [width-1:0] Q);

		
		always_ff @(posedge clk)
			if (reset) Q = 0;
			else if (load_en) Q = D;
endmodule