data/full_repos/permissive/485721981/sources/synthesis/debounce.v
1: b'%Error: data/full_repos/permissive/485721981/sources/synthesis/debounce.v:59: Expected integral (non-real) input to CLOG2\n                                                                            : ... In instance debounce\n    localparam C_CYCLES_WIDTH = $clog2(C_CYCLES);\n                                       ^~~~~~~~\n%Warning-REALCVT: data/full_repos/permissive/485721981/sources/synthesis/debounce.v:59: Implicit conversion of real to integer\n    localparam C_CYCLES_WIDTH = $clog2(C_CYCLES);\n                                       ^~~~~~~~\n                  ... Use "/* verilator lint_off REALCVT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module  debounce # (
		parameter C_CLK_FRQ = 100_000_000,
		parameter C_INTERVAL = 0.010
	) (
		input rstb,
		input clk,
		input in,
		output reg out
	);









    localparam C_CYCLES = 2 * C_CLK_FRQ * C_INTERVAL / 1000;
    localparam C_CYCLES_WIDTH = $clog2(C_CYCLES);
   






	reg [C_CYCLES_WIDTH - 1 : 0] rCount;
	

	reg DFF1, DFF2;
	

	wire wClear;
	wire wEnable;







	assign wClear = (DFF1  ^ DFF2);
	


	assign wEnable = (rCount[C_CYCLES_WIDTH - 1]);
	






	always @ (posedge clk) begin
		

		if (rstb ==  1'b0) begin
			DFF1 <= 1'b0;
			DFF2 <= 1'b0;
		end else begin
			DFF1 <= in;
			DFF2 <= DFF1;
		end
	end


	always @ (posedge clk) begin
		

		if (rstb ==  1'b0 || wClear == 1'b1) begin
			rCount <= { C_CYCLES_WIDTH {1'b0} };


		end else begin
			rCount <= (wEnable) ? rCount : rCount + 1;
		end
	end








	always @ (posedge clk) begin
		out <= (wEnable) ? DFF2 : out;
	end

endmodule
module  debounce # (
		parameter C_CLK_FRQ = 100_000_000,
		parameter C_INTERVAL = 0.010
	) (
		input rstb,
		input clk,
		input in,
		output reg out
	);










    localparam C_CYCLES = 2 * C_CLK_FRQ * C_INTERVAL / 1000;
    localparam C_CYCLES_WIDTH = $clog2(C_CYCLES);
   






	reg [C_CYCLES_WIDTH - 1 : 0] rCount;
	

	reg DFF1, DFF2;
	

	wire wClear;
	wire wEnable;







	assign wClear = (DFF1  ^ DFF2);
	


	assign wEnable = (rCount[C_CYCLES_WIDTH - 1]);
	






	always @ (posedge clk) begin
		

		if (rstb ==  1'b0) begin
			DFF1 <= 1'b0;
			DFF2 <= 1'b0;
		end else begin
			DFF1 <= in;
			DFF2 <= DFF1;
		end
	end


	always @ (posedge clk) begin
		

		if (rstb ==  1'b0 || wClear == 1'b1) begin
			rCount <= { C_CYCLES_WIDTH {1'b0} };


		end else begin
			rCount <= (wEnable) ? rCount : rCount + 1;
		end
	end








	always @ (posedge clk) begin
		out <= (wEnable) ? DFF2 : out;
	end

endmodule