data/full_repos/permissive/412289941/findv.v
data/verilator_xmls/978d597a-dc6f-4eed-970a-e90edfe66fd9.xml
module findv(rst_n, indata_P, indata_N, outdata,clk);

input rst_n,clk;
input indata_P, indata_N;
output reg [1:0] outdata;
reg [1:0]flag1;
reg [1:0]flag2;

initial begin
    flag1=2'b00;
    flag2=2'b00;
end

always @(posedge clk or negedge rst_n) begin
    if(!rst_n) begin

        flag1=2'b00;
        flag2=2'b00;
        outdata <= 2'b00;
    end
    else begin
        if(indata_P==1'b1 && indata_N==1'b0) begin

            flag2<=2'b00;
            flag1=flag1+2'b01;
            if(flag1==2'b10) begin
                outdata<=2'b11;
                flag1<=2'b00;
            end
            else outdata<=2'b01;
        end
        else if(indata_P==1'b0 && indata_N==1'b1) begin

            flag1<=2'b00;
            flag2=flag2+2'b01;
            if(flag2==2'b10) begin
                outdata<=2'b11;
                flag2<=2'b00;
            end
            else outdata<=2'b01;
        end

        else if(indata_P==1'b0 && indata_N==1'b0) outdata<=2'b00;

    end
end

endmodule
module findv(rst_n, indata_P, indata_N, outdata,clk);


input rst_n,clk;
input indata_P, indata_N;
output reg [1:0] outdata;
reg [1:0]flag1;
reg [1:0]flag2;

initial begin
    flag1=2'b00;
    flag2=2'b00;
end

always @(posedge clk or negedge rst_n) begin
    if(!rst_n) begin

        flag1=2'b00;
        flag2=2'b00;
        outdata <= 2'b00;
    end
    else begin
        if(indata_P==1'b1 && indata_N==1'b0) begin

            flag2<=2'b00;
            flag1=flag1+2'b01;
            if(flag1==2'b10) begin
                outdata<=2'b11;
                flag1<=2'b00;
            end
            else outdata<=2'b01;
        end
        else if(indata_P==1'b0 && indata_N==1'b1) begin

            flag1<=2'b00;
            flag2=flag2+2'b01;
            if(flag2==2'b10) begin
                outdata<=2'b11;
                flag2<=2'b00;
            end
            else outdata<=2'b01;
        end

        else if(indata_P==1'b0 && indata_N==1'b0) outdata<=2'b00;

    end
end

endmodule