data/full_repos/permissive/42149584/Lab4-Part1-40x7bit-RAM/AddressManager.v
data/verilator_xmls/3d2b1625-d6b3-4f62-9c5c-572aa41d4fe3.xml
module AddressManager(Clock, IncrementAddress, Reset, Address);
	input Clock, IncrementAddress, Reset;
	output reg [5:0] Address;

	initial Address = 6'b0;
	always@(posedge Clock)
		if (Reset == 1) Address <= 6'b0;
		else if (IncrementAddress == 1 & Address == 39) Address <= 0;
		else if (IncrementAddress == 1) Address <= Address + 1;
endmodule
module AddressManager(Clock, IncrementAddress, Reset, Address);

	input Clock, IncrementAddress, Reset;
	output reg [5:0] Address;

	initial Address = 6'b0;
	always@(posedge Clock)
		if (Reset == 1) Address <= 6'b0;
		else if (IncrementAddress == 1 & Address == 39) Address <= 0;
		else if (IncrementAddress == 1) Address <= Address + 1;
endmodule