data/full_repos/permissive/472586361/humanmachine/register-4.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/472586361/humanmachine/register-4.v:9: Unsupported: Ignoring delay on this delayed statement.\n    #delaytime data_out[0] <= data_in[0];\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/472586361/humanmachine/register-4.v:10: Unsupported: Ignoring delay on this delayed statement.\n    #delaytime data_out[1] <= data_in[1];\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/472586361/humanmachine/register-4.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #delaytime data_out[2] <= data_in[2];\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/472586361/humanmachine/register-4.v:12: Unsupported: Ignoring delay on this delayed statement.\n    #delaytime data_out[3] <= data_in[3];\n    ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module register4(input clk, input [3:0] data_in, input EI, output reg [3:0] data_out);
wire CLK;
parameter delaytime=5;
assign CLK=(clk & EI);
always @(posedge CLK)
begin
    #delaytime data_out[0] <= data_in[0];
    #delaytime data_out[1] <= data_in[1];
    #delaytime data_out[2] <= data_in[2];
    #delaytime data_out[3] <= data_in[3];
end
endmodule
module register4(input clk, input [3:0] data_in, input EI, output reg [3:0] data_out);

wire CLK;
parameter delaytime=5;
assign CLK=(clk & EI);
always @(posedge CLK)
begin
    #delaytime data_out[0] <= data_in[0];
    #delaytime data_out[1] <= data_in[1];
    #delaytime data_out[2] <= data_in[2];
    #delaytime data_out[3] <= data_in[3];
end
endmodule