data/full_repos/permissive/461000256/new/tb_ALU.v
1: b'%Error: data/full_repos/permissive/461000256/new/tb_ALU.v:2: Cannot find include file: include.v\n`include "include.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/461000256/new,data/full_repos/permissive/461000256/include.v\n             data/full_repos/permissive/461000256/new,data/full_repos/permissive/461000256/include.v.v\n             data/full_repos/permissive/461000256/new,data/full_repos/permissive/461000256/include.v.sv\n             include.v\n             include.v.v\n             include.v.sv\n             obj_dir/include.v\n             obj_dir/include.v.v\n             obj_dir/include.v.sv\n%Error: data/full_repos/permissive/461000256/new/tb_ALU.v:21: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("ALU.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/461000256/new/tb_ALU.v:22: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, tb_ALU);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/461000256/new/tb_ALU.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #10 $finish;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module tb_ALU;
	parameter RFW = 5;
	parameter IMW = 4;
	parameter DW  = 32;
	parameter IW  = 32;
	integer y;
	reg [DW-1:0]a;
	reg [DW-1:0]b;
	reg [IW-1:0]inst;
	wire [IW-1:0]o;
	wire [DW-1:0]out;
		integer i;

	EXE #(.RFW(RFW),.IMW(IMW),.DW(DW),.IW(IW))		alu(.inst(inst),.dataA(a),.dataB(b),.inst_o(o),.data_out(out));

	initial begin
		inst = 32'h8e7425b7;
		$display("\n");
		$dumpfile("ALU.vcd");
		$dumpvars(0, tb_ALU);
		a = 445;
		b = 1;
		#10 $finish;
		
	end

endmodule
module tb_ALU;

	parameter RFW = 5;
	parameter IMW = 4;
	parameter DW  = 32;
	parameter IW  = 32;
	integer y;
	reg [DW-1:0]a;
	reg [DW-1:0]b;
	reg [IW-1:0]inst;
	wire [IW-1:0]o;
	wire [DW-1:0]out;
		integer i;

	EXE #(.RFW(RFW),.IMW(IMW),.DW(DW),.IW(IW))		alu(.inst(inst),.dataA(a),.dataB(b),.inst_o(o),.data_out(out));

	initial begin
		inst = 32'h8e7425b7;
		$display("\n");
		$dumpfile("ALU.vcd");
		$dumpvars(0, tb_ALU);
		a = 445;
		b = 1;
		#10 $finish;
		
	end

endmodule