data/full_repos/permissive/520452389/source_codes/Execution.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/520452389/source_codes/Execution.v:22: Signal definition not found, creating implicitly: \'zero\'\n                                                                                   : ... Suggested alternative: \'zero_s3\'\n        MemtoReg_s3,MemRead_s3,RegWrite_s2,RegWrite_s3,Branch_s3,write_reg,write_reg_s3,pc_out1_ss,pc_out1_s3,zero,zero_s3);\n                                                                                                              ^~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/520452389/source_codes/Execution.v:18: Cannot find file containing module: \'ksa_add\'\nksa_add kkkk(0,pc_out1_s2,add_in2,pc_out1_ss, pc_carry);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/520452389/source_codes,data/full_repos/permissive/520452389/ksa_add\n             data/full_repos/permissive/520452389/source_codes,data/full_repos/permissive/520452389/ksa_add.v\n             data/full_repos/permissive/520452389/source_codes,data/full_repos/permissive/520452389/ksa_add.sv\n             ksa_add\n             ksa_add.v\n             ksa_add.sv\n             obj_dir/ksa_add\n             obj_dir/ksa_add.v\n             obj_dir/ksa_add.sv\n%Error: data/full_repos/permissive/520452389/source_codes/Execution.v:20: Cannot find file containing module: \'ALU\'\nALU alu(alu1,alu_in2,ALUCtrl,ALU_result,zero);\n^~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module ALU_control (input [5:0]a,input ALUOp1,input ALUOp0,output [3:0]ALUCtrl);
assign ALUCtrl = (({ALUOp1,ALUOp0}==2'b10))?((a == 6'b100000)?4'b0010:(a == 6'b100010)?4'b0110:(a == 6'b100100)?4'b0000:(a==6'b100101)?4'b0001:(a == 6'b011011)?4'b0100:4'b0011):({ALUOp1,ALUOp0}==2'b01)?4'b0110:4'b0010;
endmodule
module ALU_control (input [5:0]a,input ALUOp1,input ALUOp0,output [3:0]ALUCtrl);

assign ALUCtrl = (({ALUOp1,ALUOp0}==2'b10))?((a == 6'b100000)?4'b0010:(a == 6'b100010)?4'b0110:(a == 6'b100100)?4'b0000:(a==6'b100101)?4'b0001:(a == 6'b011011)?4'b0100:4'b0011):({ALUOp1,ALUOp0}==2'b01)?4'b0110:4'b0010;
endmodule