data/full_repos/permissive/422178762/verilog/rtl/gpio_ssp.v
1: b'%Warning-WIDTH: data/full_repos/permissive/422178762/verilog/rtl/gpio_ssp.v:73: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s LTE generates 1 bits.\n                                                                              : ... In instance gpio_ssp\n                            default      : begin apb_rdata  <= apb_rdata  <= 32\'h0000_0000; end\n                                                            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module gpio_ssp(
    input              clock,
    input              rst_n,
    input  [31:0]      apb_addr,
    input              apb_sel,
    input              apb_write,
    input              apb_ena,
    input  [31:0]      apb_wdata,
    output reg [31:0]  apb_rdata,
    input  [3:0]       apb_pstb,
    output             apb_rready,
    output             gpio_intr,
    
    input  [19:0]      gpi,
    output [19:0]      gpo,
    output [19:0]      gpd
   
     
    
    );
    
    localparam GPO_ADDR    = 8'h00;
    localparam GPI_ADDR    = 8'h04;
    localparam GPID_ADDR   = 8'h0C;
    
    
    reg [19:0] gpo_r;
    reg [19:0] gpd_r;
    assign apb_rready = 1'b1;
    
    assign gpd   = gpd_r; 
    assign gpo   = gpo_r;
    
assign gpio_intr = 1'b0;
     
    always @(posedge clock or negedge rst_n) begin 
        if(!rst_n) begin
        
            gpo_r      <= 20'h00000;
            apb_rdata  <= 32'h0000_0000;
            gpd_r      <= 20'h00000;
        
        end else begin
        
            if(apb_sel && apb_write) begin 
                case(apb_addr[7:0]) 
                            GPO_ADDR     : begin gpo_r    <= apb_wdata[19:0] ;end
                            GPID_ADDR    : begin gpd_r    <= apb_wdata[19:0] ;end
                            
                 endcase        
              end
              
             if(apb_sel && !apb_write) begin 
                    case(apb_addr[7:0]) 
                            GPO_ADDR     : begin apb_rdata  <= {12'h000,gpo_r}  ;end
                            GPID_ADDR    : begin apb_rdata  <= {12'h000,gpd_r}  ;end
                            GPI_ADDR     : begin apb_rdata  <= {12'h000,gpi}; end
                            default      : begin apb_rdata  <= apb_rdata  <= 32'h0000_0000; end
                    endcase      
                            
            end            
            
              
              
              
              
              
             
        
        end
    
    end
    
    
    
    
    
    
    
    
    
    
endmodule
module gpio_ssp(
    input              clock,
    input              rst_n,
    input  [31:0]      apb_addr,
    input              apb_sel,
    input              apb_write,
    input              apb_ena,
    input  [31:0]      apb_wdata,
    output reg [31:0]  apb_rdata,
    input  [3:0]       apb_pstb,
    output             apb_rready,
    output             gpio_intr,
    
    input  [19:0]      gpi,
    output [19:0]      gpo,
    output [19:0]      gpd
   
     
    
    );

    
    localparam GPO_ADDR    = 8'h00;
    localparam GPI_ADDR    = 8'h04;
    localparam GPID_ADDR   = 8'h0C;
    
    
    reg [19:0] gpo_r;
    reg [19:0] gpd_r;
    assign apb_rready = 1'b1;
    
    assign gpd   = gpd_r; 
    assign gpo   = gpo_r;
    
assign gpio_intr = 1'b0;
     
    always @(posedge clock or negedge rst_n) begin 
        if(!rst_n) begin
        
            gpo_r      <= 20'h00000;
            apb_rdata  <= 32'h0000_0000;
            gpd_r      <= 20'h00000;
        
        end else begin
        
            if(apb_sel && apb_write) begin 
                case(apb_addr[7:0]) 
                            GPO_ADDR     : begin gpo_r    <= apb_wdata[19:0] ;end
                            GPID_ADDR    : begin gpd_r    <= apb_wdata[19:0] ;end
                            
                 endcase        
              end
              
             if(apb_sel && !apb_write) begin 
                    case(apb_addr[7:0]) 
                            GPO_ADDR     : begin apb_rdata  <= {12'h000,gpo_r}  ;end
                            GPID_ADDR    : begin apb_rdata  <= {12'h000,gpd_r}  ;end
                            GPI_ADDR     : begin apb_rdata  <= {12'h000,gpi}; end
                            default      : begin apb_rdata  <= apb_rdata  <= 32'h0000_0000; end
                    endcase      
                            
            end            
            
              
              
              
              
              
             
        
        end
    
    end
    
    
    
    
    
    
    
    
    
    
endmodule