data/full_repos/permissive/486598419/6.9/alu_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #20  a=32\'h7fffffff;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #20  a=32\'h7fffffff;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #20  a=32\'hffffffff;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #20  aluc=4\'b0000;   \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #20  a=32\'h7fffffff;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n    #20  a=32\'hffffffff;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #20  aluc=4\'b0011;        \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n    #20  a=32\'h7fffffff;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #20  a=32\'hf00fffff;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n    #20  a=32\'hffffffff;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #20  a=32\'hf0000000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n    #20  aluc=4\'b0001;        \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n    #20  a=32\'h7fffffff;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n    #20  a=32\'hffffffff;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n    #20  a=32\'hf0000000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n    #20  aluc=4\'b0100;        \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n    #20  a=32\'h7fffffff;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n    #20  aluc=4\'b0101;        \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n    #20  a=32\'h7fffffff;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n    #20  aluc=4\'b0110;        \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n    #20  a=32\'h7fffffff;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n    #20  aluc=4\'b0111;        \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n    #20  a=32\'h7fffffff;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n    #20  aluc=11\'b1011;        \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n    #20  a=32\'h7000000f;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n    #20  a=32\'hf0001231;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n    #20  aluc=4\'b1010;        \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n    #20  a=32\'h7000000f;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n    #20  a=32\'hf0001231;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n    #20  aluc=4\'b111x;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n    #20  aluc=4\'b1101;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:125: Unsupported: Ignoring delay on this delayed statement.\n    #20  aluc=4\'b1100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.9/alu_tb.v:128: Unsupported: Ignoring delay on this delayed statement.\n    #20  b=32\'h0fffffff;\n    ^\n%Error: data/full_repos/permissive/486598419/6.9/alu_tb.v:33: Cannot find file containing module: \'alu\'\nalu uut(a,b,aluc,r,zero,carry,negative,overflow);\n^~~\n        ... Looked in:\n             data/full_repos/permissive/486598419/6.9,data/full_repos/permissive/486598419/alu\n             data/full_repos/permissive/486598419/6.9,data/full_repos/permissive/486598419/alu.v\n             data/full_repos/permissive/486598419/6.9,data/full_repos/permissive/486598419/alu.sv\n             alu\n             alu.v\n             alu.sv\n             obj_dir/alu\n             obj_dir/alu.v\n             obj_dir/alu.sv\n%Warning-WIDTH: data/full_repos/permissive/486598419/6.9/alu_tb.v:101: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'11\'hb\' generates 11 bits.\n                                                                     : ... In instance alu_tb\n    #20  aluc=11\'b1011;        \n             ^\n%Error: Exiting due to 1 error(s), 34 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu_tb();
reg [31:0] a;
reg [31:0] b;
reg [3:0] aluc;
wire [31:0] r;
wire zero;
wire carry;
wire negative;
wire overflow;

alu uut(a,b,aluc,r,zero,carry,negative,overflow);
initial
    begin

         aluc=4'b0010;        
         a=32'hf2340000;
         b=32'h80000000;
    #20  a=32'h7fffffff;
         b=32'h70000001;
    #20  a=32'h7fffffff;
         b=32'hf0000001;
    #20  a=32'hffffffff;
         b=32'h00000001;

    #20  aluc=4'b0000;   
         a=32'hf2340000;
         b=32'h80000000;
    #20  a=32'h7fffffff;
         b=32'h70000001;
    #20  a=32'hffffffff;
         b=32'h00000001;

    #20  aluc=4'b0011;        
         a=32'h72340000;
         b=32'h60000000;
    #20  a=32'h7fffffff;
         b=32'hf0000001;
    #20  a=32'hf00fffff;
         b=32'h7ffffff1;
    #20  a=32'hffffffff;
         b=32'hffffffff;
    #20  a=32'hf0000000;
         b=32'h0fffffff; 

    #20  aluc=4'b0001;        
         a=32'h72340000;
         b=32'h60000000;
    #20  a=32'h7fffffff;
         b=32'hf0000001;
    #20  a=32'hffffffff;
         b=32'hffffffff;
    #20  a=32'hf0000000;
         b=32'h0fffffff; 

    #20  aluc=4'b0100;        
         a=32'h72340000;
         b=32'h60000000;
    #20  a=32'h7fffffff;
         b=32'h00000000; 

    #20  aluc=4'b0101;        
         a=32'h00000000;
         b=32'h00000000;
    #20  a=32'h7fffffff;
         b=32'hf0000001;

    #20  aluc=4'b0110;        
         a=32'ha0000000;
         b=32'h50000000;
    #20  a=32'h7fffffff;
         b=32'hf0000001;

    #20  aluc=4'b0111;        
         a=32'h123451ff;
         b=32'h60000000;
    #20  a=32'h7fffffff;
         b=32'hf0000001;

    #20  aluc=11'b1011;        
         a=32'h72340000;
         b=32'hf0000000;
    #20  a=32'h7000000f;
         b=32'h7f000001;
    #20  a=32'hf0001231;
         b=32'h7ac34545;

    #20  aluc=4'b1010;        
         a=32'h72340000;
         b=32'hf0000000;
    #20  a=32'h7000000f;
         b=32'h7f000001;
    #20  a=32'hf0001231;
         b=32'h7ac34545;

    #20  aluc=4'b111x;
         b=32'hffffffff;
         a=32'd5;

    #20  aluc=4'b1101;
         b=32'hffffffff;
         a=32'd5;

    #20  aluc=4'b1100;
         b=32'hffffffff;
         a=32'd3;
    #20  b=32'h0fffffff;
         a=32'd5;
    end
endmodule
module alu_tb();

reg [31:0] a;
reg [31:0] b;
reg [3:0] aluc;
wire [31:0] r;
wire zero;
wire carry;
wire negative;
wire overflow;

alu uut(a,b,aluc,r,zero,carry,negative,overflow);
initial
    begin

         aluc=4'b0010;        
         a=32'hf2340000;
         b=32'h80000000;
    #20  a=32'h7fffffff;
         b=32'h70000001;
    #20  a=32'h7fffffff;
         b=32'hf0000001;
    #20  a=32'hffffffff;
         b=32'h00000001;

    #20  aluc=4'b0000;   
         a=32'hf2340000;
         b=32'h80000000;
    #20  a=32'h7fffffff;
         b=32'h70000001;
    #20  a=32'hffffffff;
         b=32'h00000001;

    #20  aluc=4'b0011;        
         a=32'h72340000;
         b=32'h60000000;
    #20  a=32'h7fffffff;
         b=32'hf0000001;
    #20  a=32'hf00fffff;
         b=32'h7ffffff1;
    #20  a=32'hffffffff;
         b=32'hffffffff;
    #20  a=32'hf0000000;
         b=32'h0fffffff; 

    #20  aluc=4'b0001;        
         a=32'h72340000;
         b=32'h60000000;
    #20  a=32'h7fffffff;
         b=32'hf0000001;
    #20  a=32'hffffffff;
         b=32'hffffffff;
    #20  a=32'hf0000000;
         b=32'h0fffffff; 

    #20  aluc=4'b0100;        
         a=32'h72340000;
         b=32'h60000000;
    #20  a=32'h7fffffff;
         b=32'h00000000; 

    #20  aluc=4'b0101;        
         a=32'h00000000;
         b=32'h00000000;
    #20  a=32'h7fffffff;
         b=32'hf0000001;

    #20  aluc=4'b0110;        
         a=32'ha0000000;
         b=32'h50000000;
    #20  a=32'h7fffffff;
         b=32'hf0000001;

    #20  aluc=4'b0111;        
         a=32'h123451ff;
         b=32'h60000000;
    #20  a=32'h7fffffff;
         b=32'hf0000001;

    #20  aluc=11'b1011;        
         a=32'h72340000;
         b=32'hf0000000;
    #20  a=32'h7000000f;
         b=32'h7f000001;
    #20  a=32'hf0001231;
         b=32'h7ac34545;

    #20  aluc=4'b1010;        
         a=32'h72340000;
         b=32'hf0000000;
    #20  a=32'h7000000f;
         b=32'h7f000001;
    #20  a=32'hf0001231;
         b=32'h7ac34545;

    #20  aluc=4'b111x;
         b=32'hffffffff;
         a=32'd5;

    #20  aluc=4'b1101;
         b=32'hffffffff;
         a=32'd5;

    #20  aluc=4'b1100;
         b=32'hffffffff;
         a=32'd3;
    #20  b=32'h0fffffff;
         a=32'd5;
    end
endmodule