data/full_repos/permissive/432384243/verilog/rtl/lbist/src/lbist_reg.sv
1: b"%Error: data/full_repos/permissive/432384243/verilog/rtl/lbist/src/lbist_reg.sv:183: Cannot find file containing module: 'generic_register'\ngeneric_register #(8,8'h0  ) u_reg0_be0 (\n^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/432384243/verilog/rtl/lbist/src,data/full_repos/permissive/432384243/generic_register\n             data/full_repos/permissive/432384243/verilog/rtl/lbist/src,data/full_repos/permissive/432384243/generic_register.v\n             data/full_repos/permissive/432384243/verilog/rtl/lbist/src,data/full_repos/permissive/432384243/generic_register.sv\n             generic_register\n             generic_register.v\n             generic_register.sv\n             obj_dir/generic_register\n             obj_dir/generic_register.v\n             obj_dir/generic_register.sv\n%Error: data/full_repos/permissive/432384243/verilog/rtl/lbist/src/lbist_reg.sv:207: Cannot find file containing module: 'gen_32b_reg'\ngen_32b_reg  #(32'h4C66_8354) u_reg_1 (\n^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module lbist_reg (

       input logic             mclk,
       input logic             reset_n,



        input logic             reg_cs,
        input logic             reg_wr,
        input logic [1:0]       reg_addr,
        input logic [31:0]      reg_wdata,
        input logic [3:0]       reg_be,


        output logic [31:0]     reg_rdata,
        output logic            reg_ack,


	output logic            cfg_lbist_rst,
	output logic            cfg_lbist_start,
	output logic            cfg_lbist_rsb,
	output logic [15:0]     cfg_lbist_pat,
	output logic [15:0]     cfg_chain_depth,


	input  logic            lbist_done,
	input  logic [31:0]     lbist_sig


        );







logic           sw_rd_en    ;
logic           sw_wr_en    ;
logic  [1:0]    sw_addr     ;
logic  [3:0]    wr_be       ;
logic  [31:0]   sw_reg_wdata;



logic [31:0]    reg_0;
logic [31:0]    reg_1;

logic [31:0]    reg_out;










assign       sw_addr       = reg_addr [1:0];
assign       sw_rd_en      = reg_cs & !reg_wr;
assign       sw_wr_en      = reg_cs & reg_wr;
assign       wr_be         = reg_be;
assign       sw_reg_wdata  = reg_wdata;


wire   sw_wr_en_0 = sw_wr_en & (sw_addr == 2'h0);
wire   sw_rd_en_0 = sw_rd_en & (sw_addr == 2'h0);
wire   sw_wr_en_1 = sw_wr_en & (sw_addr == 2'h1);
wire   sw_rd_en_1 = sw_rd_en & (sw_addr == 2'h1);
wire   sw_wr_en_2 = sw_wr_en & (sw_addr == 2'h2);
wire   sw_rd_en_2 = sw_rd_en & (sw_addr == 2'h2);
wire   sw_wr_en_3 = sw_wr_en & (sw_addr == 2'h3);
wire   sw_rd_en_3 = sw_rd_en & (sw_addr == 2'h3);

logic wb_req;

always_ff @(negedge reset_n or posedge mclk) begin
    if ( reset_n == 1'b0 ) begin
        wb_req    <= '0;
   end else begin
       wb_req   <= reg_cs && (reg_ack == 0) ;
   end
end


always @ (posedge mclk or negedge reset_n)
begin : preg_out_Seq
   if (reset_n == 1'b0) begin
      reg_rdata  <= 'h0;
      reg_ack    <= 1'b0;
   end else if (reg_cs && !reg_ack) begin
      reg_rdata <= reg_out ;
      reg_ack   <= 1'b1;
   end else begin
      reg_ack   <= 1'b0;
   end
end

always @( *)
begin 
  reg_out [31:0] = 32'h0;

  case (sw_addr [1:0])
    2'b00 :   reg_out [31:0] = reg_0;
    2'b01 :   reg_out [31:0] = reg_1;
    2'b10 :   reg_out [31:0] = lbist_sig;
    default : reg_out [31:0] = 'h0;
  endcase
end








generic_register #(8,8'h0  ) u_reg0_be0 (
	      .we            ({8{sw_wr_en_0 & 
                                 wr_be[0]   }}  ),		 
	      .data_in       (sw_reg_wdata[7:0]    ),
	      .reset_n       (reset_n           ),
	      .clk           (mclk              ),
	      

	      .data_out      (reg_0[7:0]        )
          );


assign cfg_lbist_rst    = reg_0[0];
assign cfg_lbist_start  = reg_0[1];
assign cfg_lbist_rsb  = reg_0[2];
assign reg_0[31:8]     = {lbist_done,23'b0};





assign cfg_chain_depth  = reg_1[15:0];
assign cfg_lbist_pat    = reg_1[31:16];

gen_32b_reg  #(32'h4C66_8354) u_reg_1	(

	      .reset_n    (reset_n       ),
	      .clk        (mclk          ),
	      .cs         (sw_wr_en_1    ),
	      .we         (wr_be         ),		 
	      .data_in    (sw_reg_wdata  ),
	      

	      .data_out   (reg_1       )
	      );
endmodule
module lbist_reg (

       input logic             mclk,
       input logic             reset_n,



        input logic             reg_cs,
        input logic             reg_wr,
        input logic [1:0]       reg_addr,
        input logic [31:0]      reg_wdata,
        input logic [3:0]       reg_be,


        output logic [31:0]     reg_rdata,
        output logic            reg_ack,


	output logic            cfg_lbist_rst,
	output logic            cfg_lbist_start,
	output logic            cfg_lbist_rsb,
	output logic [15:0]     cfg_lbist_pat,
	output logic [15:0]     cfg_chain_depth,


	input  logic            lbist_done,
	input  logic [31:0]     lbist_sig


        );








logic           sw_rd_en    ;
logic           sw_wr_en    ;
logic  [1:0]    sw_addr     ;
logic  [3:0]    wr_be       ;
logic  [31:0]   sw_reg_wdata;



logic [31:0]    reg_0;
logic [31:0]    reg_1;

logic [31:0]    reg_out;










assign       sw_addr       = reg_addr [1:0];
assign       sw_rd_en      = reg_cs & !reg_wr;
assign       sw_wr_en      = reg_cs & reg_wr;
assign       wr_be         = reg_be;
assign       sw_reg_wdata  = reg_wdata;


wire   sw_wr_en_0 = sw_wr_en & (sw_addr == 2'h0);
wire   sw_rd_en_0 = sw_rd_en & (sw_addr == 2'h0);
wire   sw_wr_en_1 = sw_wr_en & (sw_addr == 2'h1);
wire   sw_rd_en_1 = sw_rd_en & (sw_addr == 2'h1);
wire   sw_wr_en_2 = sw_wr_en & (sw_addr == 2'h2);
wire   sw_rd_en_2 = sw_rd_en & (sw_addr == 2'h2);
wire   sw_wr_en_3 = sw_wr_en & (sw_addr == 2'h3);
wire   sw_rd_en_3 = sw_rd_en & (sw_addr == 2'h3);

logic wb_req;

always_ff @(negedge reset_n or posedge mclk) begin
    if ( reset_n == 1'b0 ) begin
        wb_req    <= '0;
   end else begin
       wb_req   <= reg_cs && (reg_ack == 0) ;
   end
end


always @ (posedge mclk or negedge reset_n)
begin : preg_out_Seq
   if (reset_n == 1'b0) begin
      reg_rdata  <= 'h0;
      reg_ack    <= 1'b0;
   end else if (reg_cs && !reg_ack) begin
      reg_rdata <= reg_out ;
      reg_ack   <= 1'b1;
   end else begin
      reg_ack   <= 1'b0;
   end
end

always @( *)
begin 
  reg_out [31:0] = 32'h0;

  case (sw_addr [1:0])
    2'b00 :   reg_out [31:0] = reg_0;
    2'b01 :   reg_out [31:0] = reg_1;
    2'b10 :   reg_out [31:0] = lbist_sig;
    default : reg_out [31:0] = 'h0;
  endcase
end








generic_register #(8,8'h0  ) u_reg0_be0 (
	      .we            ({8{sw_wr_en_0 & 
                                 wr_be[0]   }}  ),		 
	      .data_in       (sw_reg_wdata[7:0]    ),
	      .reset_n       (reset_n           ),
	      .clk           (mclk              ),
	      

	      .data_out      (reg_0[7:0]        )
          );


assign cfg_lbist_rst    = reg_0[0];
assign cfg_lbist_start  = reg_0[1];
assign cfg_lbist_rsb  = reg_0[2];
assign reg_0[31:8]     = {lbist_done,23'b0};





assign cfg_chain_depth  = reg_1[15:0];
assign cfg_lbist_pat    = reg_1[31:16];

gen_32b_reg  #(32'h4C66_8354) u_reg_1	(

	      .reset_n    (reset_n       ),
	      .clk        (mclk          ),
	      .cs         (sw_wr_en_1    ),
	      .we         (wr_be         ),		 
	      .data_in    (sw_reg_wdata  ),
	      

	      .data_out   (reg_1       )
	      );
endmodule