data/full_repos/permissive/496096937/verilog/rtl/user_project_wrapper.v
1: b'%Warning-WIDTH: data/full_repos/permissive/496096937/verilog/rtl/user_project_wrapper.v:253: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 30 bits.\n                                                                                           : ... In instance user_project_wrapper\nassign srdata                = la_data_in[29:0];\n                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-SELRANGE: data/full_repos/permissive/496096937/verilog/rtl/user_project_wrapper.v:287: Selection index out of range: 39:32 outside 37:0\n                                                                                              : ... In instance user_project_wrapper\nassign io_oeb[39:32] = ~8\'b00000000;\n             ^\n%Error: data/full_repos/permissive/496096937/verilog/rtl/user_project_wrapper.v:292: Cannot find file containing module: \'tdc\'\ntdc u_tdc(\n^~~\n        ... Looked in:\n             data/full_repos/permissive/496096937/verilog/rtl,data/full_repos/permissive/496096937/tdc\n             data/full_repos/permissive/496096937/verilog/rtl,data/full_repos/permissive/496096937/tdc.v\n             data/full_repos/permissive/496096937/verilog/rtl,data/full_repos/permissive/496096937/tdc.sv\n             tdc\n             tdc.v\n             tdc.sv\n             obj_dir/tdc\n             obj_dir/tdc.v\n             obj_dir/tdc.sv\n%Error: data/full_repos/permissive/496096937/verilog/rtl/user_project_wrapper.v:304: Cannot find file containing module: \'hp35_core\'\nhp35_core u_hp35_core (\n^~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module user_project_wrapper #(
    parameter BITS = 32
) (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    `ifndef MPRJ_IO_PADS
        `define MPRJ_IO_PADS 38
    `endif
    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,





    inout [`MPRJ_IO_PADS-10:0] analog_io,


    input   user_clock2,


    output [2:0] user_irq
);

wire [4:0]  col_in;
wire        cdiv_rst_in;
wire        dbg_internal_cdiv_in;
wire        external_clock_in;
wire        osc_in = wb_clk_i;
wire        phi1_in;
wire        phi2_in;
wire        phi1_out;
wire        phi2_out;
wire        phi_oen;
wire        pwo_in;
wire [4:0]  dd_out;
wire        start_out;
wire        is_in;
wire        is_bus;
wire        is_oen;
wire        ws_in;
wire        ws_bus;
wire        ws_oen;
wire        bcd_in;
wire        bcd_bus;
wire        bcd_oen;
wire        ia_in;
wire        ia_bus;
wire        ia_oen;
wire        carry_in;
wire        carry_bus;
wire        carry_oen;
wire        sync_in;
wire        sync_bus;
wire        sync_oen;
wire [2:0]  dbg_sram_cksel_in;
wire [1:0]  dbg_sram_wrmode_in;

wire [3:0]  dbg_cksel_in;


wire        dbg_disable_arc_in;
wire        dbg_disable_ctc_in;
wire        dbg_disable_rom_in;
wire        dbg_arc_dummy_in;
wire        dbg_force_data_in;
wire [9:0]  dbg_romdata_in;
wire [4:0]  dbg_dsbf_out;
wire        dbg_arc_t1_out;
wire        dbg_arc_t4_out;
wire        dbg_arc_a1_out;
wire        dbg_arc_b1_out;
wire [2:0]  dbg_rom_roe_out;
wire        dbg_ctc_state1_out;
wire        dbg_ctc_kdn_out;
wire [5:0]  dbg_ctc_q_out;

wire        dbg_oe_xor;
wire        sram_clk0;
wire        sram_csb0;
wire        sram_web0;
wire [7:0]  sram_addr0;
wire [29:0] sram_din0;

wire        sram_clk1;
wire        dbg_sram_csb1_in;
wire [7:0]  sraddr_mux;
wire [31:0] srdata;

wire        dbg_tdc_invstop;
wire        tdc_start;
wire        tdc_stop;
wire [63:0] tdc_dq;
wire        tdc_tail;


assign tdc_start     = io_in[33];
assign tdc_stop      = io_in[32];
assign io_out[31:29] = dbg_ctc_q_out[5:3];

assign io_oeb[31:29] = (~3'b111);
assign col_in[4:0]   = io_in[28:24];

assign io_oeb[28:24] = (~5'b00000);
assign io_out[23:19] = dd_out;

assign io_oeb[23:19] = (~5'b11111);
assign io_out[18]    = start_out;
assign io_oeb[18]    = (~1'b1);
assign pwo_in        = io_in[17];
assign io_oeb[17]    = (~1'b0);
assign io_out[16]    = phi2_out;
assign phi2_in       = io_in[16];
assign io_out[15]    = phi1_out;
assign phi1_in       = io_in[15];
assign io_oeb[16:15] = {2{phi_oen}};
assign io_out[14]    = is_bus;
assign is_in         = io_in[14];
assign io_oeb[14]    = is_oen;
assign io_out[13]    = ws_bus;
assign ws_in         = io_in[13];
assign io_oeb[13]    = ws_oen;
assign io_out[12]    = bcd_bus;
assign bcd_in        = io_in[12];
assign io_oeb[12]    = bcd_oen;
assign io_out[11]    = ia_bus;
assign ia_in         = io_in[11];
assign io_oeb[11]    = ia_oen;
assign io_out[10]    = carry_bus;
assign carry_in      = io_in[10];
assign io_oeb[10]    = carry_oen;
assign io_out[ 9]    = sync_bus;
assign sync_in       = io_in[ 9];
assign io_oeb[ 9]    = sync_oen;
assign external_clock_in = io_in[8];

assign io_oeb[ 8]    = ~1'b0;


assign la_data_out[63:0] = tdc_dq;







assign la_data_out[69]      = tdc_tail;
assign la_data_out[74:70]   = dbg_dsbf_out;
assign la_data_out[75]      = dbg_arc_t1_out;
assign la_data_out[76]      = dbg_arc_t4_out;
assign la_data_out[77]      = dbg_arc_a1_out;
assign la_data_out[78]      = dbg_arc_b1_out;
assign la_data_out[81:79]   = dbg_rom_roe_out;
assign la_data_out[82]      = dbg_ctc_state1_out;
assign la_data_out[83]      = dbg_ctc_kdn_out;

assign la_data_out[86:84]   = dbg_ctc_q_out[2:0];


assign la_data_out[100:93]  = sraddr_mux;

assign srdata                = la_data_in[29:0];




assign sram_addr0            = la_data_in[40:33];
assign dbg_sram_csb1_in      = la_data_in[41];
assign dbg_disable_arc_in    = la_data_in[42];
assign dbg_disable_ctc_in    = la_data_in[43];
assign dbg_disable_rom_in    = la_data_in[44];
assign dbg_arc_dummy_in      = la_data_in[45];
assign dbg_force_data_in     = la_data_in[46];
assign dbg_romdata_in        = la_data_in[56:47];
assign dbg_oe_xor            = la_data_in[57];
assign cdiv_rst_in           = la_data_in[58];
assign dbg_internal_cdiv_in  = la_data_in[59];
assign dbg_cksel_in          = la_data_in[63:60];
wire [3:0] sram_wmask0       = la_data_in[67:64];
assign dbg_sram_cksel_in     = la_data_in[70:68];
assign dbg_sram_wrmode_in    = la_data_in[72:71];
assign dbg_tdc_invstop       = la_data_in[125];
wire   sram_page             = la_data_in[126];
wire   nc                    = la_data_in[127];

assign wbs_ack_o            = 0;
assign wbs_dat_o[31:0]      = 0;
assign user_irq[2:0]        = {2'b0, sram_clk1};
assign la_data_out[127:101] = 0;
assign io_out[37:32] = 0;
assign io_out[28:24] = 0;
assign io_out[17]    = 0;
assign io_out[8:0]   = 0;


assign io_oeb[39:32] = ~8'b00000000;
assign io_oeb[7:0]   = ~8'b00000000;



tdc u_tdc(
`ifdef USE_POWER_PINS
	.vccd1(vccd1),
	.vssd1(vssd1),
`endif
    .start  (tdc_start      ),
    .stop   (tdc_stop       ),
    .invstop(dbg_tdc_invstop),
    .tail   (tdc_tail       ),
    .dq     (tdc_dq         )
);

hp35_core u_hp35_core (
`ifdef USE_POWER_PINS
	.vccd1(vccd1),
	.vssd1(vssd1),
`endif
    .COL               (col_in               ),
    .cdiv_rst          (cdiv_rst_in          ),
    .dbg_internal_cdiv (dbg_internal_cdiv_in ),
    .osc_in            (osc_in               ),
    .phi1_in           (phi1_in              ),
    .phi2_in           (phi2_in              ),
    .phi1_out          (phi1_out             ),
    .phi2_out          (phi2_out             ),
    .phi_oen           (phi_oen              ),
    .PWO               (pwo_in               ),
    .DD                (dd_out               ),
    .START             (start_out            ),
    .is_in             (is_in                ),
    .is_bus            (is_bus               ),
    .is_oen            (is_oen               ),
    .ws_in             (ws_in                ),
    .ws_bus            (ws_bus               ),
    .ws_oen            (ws_oen               ),
    .bcd_in            (bcd_in               ),
    .bcd_bus           (bcd_bus              ),
    .bcd_oen           (bcd_oen              ),
    .ia_in             (ia_in                ),
    .ia_bus            (ia_bus               ),
    .ia_oen            (ia_oen               ),
    .carry_bus         (carry_bus            ),
    .carry_in          (carry_in             ),
    .carry_oen         (carry_oen            ),
    .sync_bus          (sync_bus             ),
    .sync_in           (sync_in              ),
    .sync_oen          (sync_oen             ),
    .dbg_disable_arc   (dbg_disable_arc_in   ),
    .dbg_disable_ctc   (dbg_disable_ctc_in   ),
    .dbg_disable_rom   (dbg_disable_rom_in   ),
    .dbg_arc_dummy     (dbg_arc_dummy_in     ),
    .dbg_force_data    (dbg_force_data_in    ),
    .dbg_romdata       (dbg_romdata_in       ),
    .dbg_sram_csb1     (dbg_sram_csb1_in     ),
    .dbg_dsbf          (dbg_dsbf_out         ),
    .dbg_arc_t1        (dbg_arc_t1_out       ),
    .dbg_arc_t4        (dbg_arc_t4_out       ),
    .dbg_arc_a1        (dbg_arc_a1_out       ),
    .dbg_arc_b1        (dbg_arc_b1_out       ),
    .dbg_rom_roe       (dbg_rom_roe_out      ),
    .dbg_ctc_state1    (dbg_ctc_state1_out   ),
    .dbg_ctc_kdn       (dbg_ctc_kdn_out      ),
    .dbg_ctc_q         (dbg_ctc_q_out        ),
    .dbg_sram_cksel    (dbg_sram_cksel_in    ),
    .sraddr_in         (sram_addr0           ),
    .dbg_sram_wrmode   (dbg_sram_wrmode_in   ),
    .sram_clk1         (sram_clk1            ),
    .sraddr_mux        (sraddr_mux           ),
    .srdata            (srdata[29:0]         )
);

endmodule
module user_project_wrapper #(
    parameter BITS = 32
) (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    `ifndef MPRJ_IO_PADS
        `define MPRJ_IO_PADS 38
    `endif
    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,





    inout [`MPRJ_IO_PADS-10:0] analog_io,


    input   user_clock2,


    output [2:0] user_irq
);


wire [4:0]  col_in;
wire        cdiv_rst_in;
wire        dbg_internal_cdiv_in;
wire        external_clock_in;
wire        osc_in = wb_clk_i;
wire        phi1_in;
wire        phi2_in;
wire        phi1_out;
wire        phi2_out;
wire        phi_oen;
wire        pwo_in;
wire [4:0]  dd_out;
wire        start_out;
wire        is_in;
wire        is_bus;
wire        is_oen;
wire        ws_in;
wire        ws_bus;
wire        ws_oen;
wire        bcd_in;
wire        bcd_bus;
wire        bcd_oen;
wire        ia_in;
wire        ia_bus;
wire        ia_oen;
wire        carry_in;
wire        carry_bus;
wire        carry_oen;
wire        sync_in;
wire        sync_bus;
wire        sync_oen;
wire [2:0]  dbg_sram_cksel_in;
wire [1:0]  dbg_sram_wrmode_in;

wire [3:0]  dbg_cksel_in;


wire        dbg_disable_arc_in;
wire        dbg_disable_ctc_in;
wire        dbg_disable_rom_in;
wire        dbg_arc_dummy_in;
wire        dbg_force_data_in;
wire [9:0]  dbg_romdata_in;
wire [4:0]  dbg_dsbf_out;
wire        dbg_arc_t1_out;
wire        dbg_arc_t4_out;
wire        dbg_arc_a1_out;
wire        dbg_arc_b1_out;
wire [2:0]  dbg_rom_roe_out;
wire        dbg_ctc_state1_out;
wire        dbg_ctc_kdn_out;
wire [5:0]  dbg_ctc_q_out;

wire        dbg_oe_xor;
wire        sram_clk0;
wire        sram_csb0;
wire        sram_web0;
wire [7:0]  sram_addr0;
wire [29:0] sram_din0;

wire        sram_clk1;
wire        dbg_sram_csb1_in;
wire [7:0]  sraddr_mux;
wire [31:0] srdata;

wire        dbg_tdc_invstop;
wire        tdc_start;
wire        tdc_stop;
wire [63:0] tdc_dq;
wire        tdc_tail;


assign tdc_start     = io_in[33];
assign tdc_stop      = io_in[32];
assign io_out[31:29] = dbg_ctc_q_out[5:3];

assign io_oeb[31:29] = (~3'b111);
assign col_in[4:0]   = io_in[28:24];

assign io_oeb[28:24] = (~5'b00000);
assign io_out[23:19] = dd_out;

assign io_oeb[23:19] = (~5'b11111);
assign io_out[18]    = start_out;
assign io_oeb[18]    = (~1'b1);
assign pwo_in        = io_in[17];
assign io_oeb[17]    = (~1'b0);
assign io_out[16]    = phi2_out;
assign phi2_in       = io_in[16];
assign io_out[15]    = phi1_out;
assign phi1_in       = io_in[15];
assign io_oeb[16:15] = {2{phi_oen}};
assign io_out[14]    = is_bus;
assign is_in         = io_in[14];
assign io_oeb[14]    = is_oen;
assign io_out[13]    = ws_bus;
assign ws_in         = io_in[13];
assign io_oeb[13]    = ws_oen;
assign io_out[12]    = bcd_bus;
assign bcd_in        = io_in[12];
assign io_oeb[12]    = bcd_oen;
assign io_out[11]    = ia_bus;
assign ia_in         = io_in[11];
assign io_oeb[11]    = ia_oen;
assign io_out[10]    = carry_bus;
assign carry_in      = io_in[10];
assign io_oeb[10]    = carry_oen;
assign io_out[ 9]    = sync_bus;
assign sync_in       = io_in[ 9];
assign io_oeb[ 9]    = sync_oen;
assign external_clock_in = io_in[8];

assign io_oeb[ 8]    = ~1'b0;


assign la_data_out[63:0] = tdc_dq;







assign la_data_out[69]      = tdc_tail;
assign la_data_out[74:70]   = dbg_dsbf_out;
assign la_data_out[75]      = dbg_arc_t1_out;
assign la_data_out[76]      = dbg_arc_t4_out;
assign la_data_out[77]      = dbg_arc_a1_out;
assign la_data_out[78]      = dbg_arc_b1_out;
assign la_data_out[81:79]   = dbg_rom_roe_out;
assign la_data_out[82]      = dbg_ctc_state1_out;
assign la_data_out[83]      = dbg_ctc_kdn_out;

assign la_data_out[86:84]   = dbg_ctc_q_out[2:0];


assign la_data_out[100:93]  = sraddr_mux;

assign srdata                = la_data_in[29:0];




assign sram_addr0            = la_data_in[40:33];
assign dbg_sram_csb1_in      = la_data_in[41];
assign dbg_disable_arc_in    = la_data_in[42];
assign dbg_disable_ctc_in    = la_data_in[43];
assign dbg_disable_rom_in    = la_data_in[44];
assign dbg_arc_dummy_in      = la_data_in[45];
assign dbg_force_data_in     = la_data_in[46];
assign dbg_romdata_in        = la_data_in[56:47];
assign dbg_oe_xor            = la_data_in[57];
assign cdiv_rst_in           = la_data_in[58];
assign dbg_internal_cdiv_in  = la_data_in[59];
assign dbg_cksel_in          = la_data_in[63:60];
wire [3:0] sram_wmask0       = la_data_in[67:64];
assign dbg_sram_cksel_in     = la_data_in[70:68];
assign dbg_sram_wrmode_in    = la_data_in[72:71];
assign dbg_tdc_invstop       = la_data_in[125];
wire   sram_page             = la_data_in[126];
wire   nc                    = la_data_in[127];

assign wbs_ack_o            = 0;
assign wbs_dat_o[31:0]      = 0;
assign user_irq[2:0]        = {2'b0, sram_clk1};
assign la_data_out[127:101] = 0;
assign io_out[37:32] = 0;
assign io_out[28:24] = 0;
assign io_out[17]    = 0;
assign io_out[8:0]   = 0;


assign io_oeb[39:32] = ~8'b00000000;
assign io_oeb[7:0]   = ~8'b00000000;



tdc u_tdc(
`ifdef USE_POWER_PINS
	.vccd1(vccd1),
	.vssd1(vssd1),
`endif
    .start  (tdc_start      ),
    .stop   (tdc_stop       ),
    .invstop(dbg_tdc_invstop),
    .tail   (tdc_tail       ),
    .dq     (tdc_dq         )
);

hp35_core u_hp35_core (
`ifdef USE_POWER_PINS
	.vccd1(vccd1),
	.vssd1(vssd1),
`endif
    .COL               (col_in               ),
    .cdiv_rst          (cdiv_rst_in          ),
    .dbg_internal_cdiv (dbg_internal_cdiv_in ),
    .osc_in            (osc_in               ),
    .phi1_in           (phi1_in              ),
    .phi2_in           (phi2_in              ),
    .phi1_out          (phi1_out             ),
    .phi2_out          (phi2_out             ),
    .phi_oen           (phi_oen              ),
    .PWO               (pwo_in               ),
    .DD                (dd_out               ),
    .START             (start_out            ),
    .is_in             (is_in                ),
    .is_bus            (is_bus               ),
    .is_oen            (is_oen               ),
    .ws_in             (ws_in                ),
    .ws_bus            (ws_bus               ),
    .ws_oen            (ws_oen               ),
    .bcd_in            (bcd_in               ),
    .bcd_bus           (bcd_bus              ),
    .bcd_oen           (bcd_oen              ),
    .ia_in             (ia_in                ),
    .ia_bus            (ia_bus               ),
    .ia_oen            (ia_oen               ),
    .carry_bus         (carry_bus            ),
    .carry_in          (carry_in             ),
    .carry_oen         (carry_oen            ),
    .sync_bus          (sync_bus             ),
    .sync_in           (sync_in              ),
    .sync_oen          (sync_oen             ),
    .dbg_disable_arc   (dbg_disable_arc_in   ),
    .dbg_disable_ctc   (dbg_disable_ctc_in   ),
    .dbg_disable_rom   (dbg_disable_rom_in   ),
    .dbg_arc_dummy     (dbg_arc_dummy_in     ),
    .dbg_force_data    (dbg_force_data_in    ),
    .dbg_romdata       (dbg_romdata_in       ),
    .dbg_sram_csb1     (dbg_sram_csb1_in     ),
    .dbg_dsbf          (dbg_dsbf_out         ),
    .dbg_arc_t1        (dbg_arc_t1_out       ),
    .dbg_arc_t4        (dbg_arc_t4_out       ),
    .dbg_arc_a1        (dbg_arc_a1_out       ),
    .dbg_arc_b1        (dbg_arc_b1_out       ),
    .dbg_rom_roe       (dbg_rom_roe_out      ),
    .dbg_ctc_state1    (dbg_ctc_state1_out   ),
    .dbg_ctc_kdn       (dbg_ctc_kdn_out      ),
    .dbg_ctc_q         (dbg_ctc_q_out        ),
    .dbg_sram_cksel    (dbg_sram_cksel_in    ),
    .sraddr_in         (sram_addr0           ),
    .dbg_sram_wrmode   (dbg_sram_wrmode_in   ),
    .sram_clk1         (sram_clk1            ),
    .sraddr_mux        (sraddr_mux           ),
    .srdata            (srdata[29:0]         )
);

endmodule