data/full_repos/permissive/485721981/sources/synthesis/UART_Mirror.v
data/verilator_xmls/26b94b45-9c74-42a6-b79b-0e43b5008cf7.xml
module  UART_Mirror # (
	   parameter C_UART_DATA_WIDTH = 8
    ) (
        

        input rstb,
        input clk,
        input enable,
            

        output validRx,
        input ackRx,
        output [C_UART_DATA_WIDTH - 1 : 0] dataRx,
        output errRx,
        

        output busyTx,
        input sendTx,
        input [C_UART_DATA_WIDTH - 1 : 0] dataTx,
        output errTx,
            

        input rxValid,
        output rxAck,
        input [C_UART_DATA_WIDTH - 1 : 0] rxData,
        input rxErr,
        

        input txBusy,
        output txSend,
        output [C_UART_DATA_WIDTH - 1 : 0] txData,
        input txErr
        
    );
    
    





    localparam sIDLE    = 2'b00;
    localparam sACK     = 2'b01;
	localparam sWAIT    = 2'b10;
	





    reg [1:0] rState = sIDLE;
    reg [1:0] rNext;
    

    reg rMirAck;
    reg rMirSend;
    

    





    assign validRx = rxValid;
    assign rxAck = (enable) ? rMirAck : ackRx;
    assign busyTx = (enable) ? 1'b1 : txBusy;
    assign txSend = (enable) ? rMirSend : sendTx;
    assign errTx = (enable) ? 1'b0 : txErr;
    

    assign txData = (enable) ? rxData : dataTx;


    assign dataRx = rxData;
    assign errRx = rxErr;








    always @(posedge clk) begin  
        

        if (rstb == 1'b0) begin
            rState <= sIDLE;
        

        end else begin
            rState <= rNext;
        end
    end


    always @(rState, rxValid) begin


        rNext <= rState;
        

        case (rState)


            sIDLE: begin
                rNext <= (rxValid == 1'b1) ? sACK : sIDLE; 
            end


            sACK: begin
                rNext <= sWAIT;
            end


            sWAIT: begin
                rNext <= (rxValid == 1'b0) ? sIDLE : sWAIT;
            end

        endcase    
    end
    










    always @(posedge clk) begin  
        

        rMirAck <= (rState == sACK) ? 1'b1 : 1'b0;
        

        rMirSend <= (rState == sACK) ? 1'b1 : 1'b0;
        
    end

endmodule
module  UART_Mirror # (
	   parameter C_UART_DATA_WIDTH = 8
    ) (
        

        input rstb,
        input clk,
        input enable,
            

        output validRx,
        input ackRx,
        output [C_UART_DATA_WIDTH - 1 : 0] dataRx,
        output errRx,
        

        output busyTx,
        input sendTx,
        input [C_UART_DATA_WIDTH - 1 : 0] dataTx,
        output errTx,
            

        input rxValid,
        output rxAck,
        input [C_UART_DATA_WIDTH - 1 : 0] rxData,
        input rxErr,
        

        input txBusy,
        output txSend,
        output [C_UART_DATA_WIDTH - 1 : 0] txData,
        input txErr
        
    );

    
    





    localparam sIDLE    = 2'b00;
    localparam sACK     = 2'b01;
	localparam sWAIT    = 2'b10;
	





    reg [1:0] rState = sIDLE;
    reg [1:0] rNext;
    

    reg rMirAck;
    reg rMirSend;
    

    





    assign validRx = rxValid;
    assign rxAck = (enable) ? rMirAck : ackRx;
    assign busyTx = (enable) ? 1'b1 : txBusy;
    assign txSend = (enable) ? rMirSend : sendTx;
    assign errTx = (enable) ? 1'b0 : txErr;
    

    assign txData = (enable) ? rxData : dataTx;


    assign dataRx = rxData;
    assign errRx = rxErr;








    always @(posedge clk) begin  
        

        if (rstb == 1'b0) begin
            rState <= sIDLE;
        

        end else begin
            rState <= rNext;
        end
    end


    always @(rState, rxValid) begin


        rNext <= rState;
        

        case (rState)


            sIDLE: begin
                rNext <= (rxValid == 1'b1) ? sACK : sIDLE; 
            end


            sACK: begin
                rNext <= sWAIT;
            end


            sWAIT: begin
                rNext <= (rxValid == 1'b0) ? sIDLE : sWAIT;
            end

        endcase    
    end
    










    always @(posedge clk) begin  
        

        rMirAck <= (rState == sACK) ? 1'b1 : 1'b0;
        

        rMirSend <= (rState == sACK) ? 1'b1 : 1'b0;
        
    end

endmodule