data/full_repos/permissive/517031174/Template/ad9226.v
data/verilator_xmls/b6bed127-acc4-4886-b0ea-0977785d5568.xml
module ad9226 (
    input clk,
    input rst_n,
    input [11:0] data_in,
    input adc_otr,
    output adc_clk,
    output reg [11:0] data_out
);

assign adc_clk = clk;

always @(posedge clk or negedge rst_n) begin
    if(!rst_n)begin
        data_out <= 12'd0;
    end
    else begin
        data_out <= data_in;
    end
end

endmodule
module ad9226 (
    input clk,
    input rst_n,
    input [11:0] data_in,
    input adc_otr,
    output adc_clk,
    output reg [11:0] data_out
);


assign adc_clk = clk;

always @(posedge clk or negedge rst_n) begin
    if(!rst_n)begin
        data_out <= 12'd0;
    end
    else begin
        data_out <= data_in;
    end
end

endmodule