data/full_repos/permissive/458737381/src/verilog-parser/tests/ccx_iob_rptr.v
data/verilator_xmls/48978306-b0cb-4069-bff7-4776044d76aa.xml
module ccx_iob_rptr (

   sig_buf, 

   sig
   );


output	[135:0]	 sig_buf;
input	[135:0]	 sig;


assign	sig_buf = sig;



endmodule
module ccx_iob_rptr (

   sig_buf, 

   sig
   );



output	[135:0]	 sig_buf;
input	[135:0]	 sig;


assign	sig_buf = sig;



endmodule