data/full_repos/permissive/40989439/AdiHDLLib/library/common/ad_axis_dma_tx.v
1: b'%Warning-WIDTH: data/full_repos/permissive/40989439/AdiHDLLib/library/common/ad_axis_dma_tx.v:190: Operator FUNCREF \'b2g\' expects 8 bits on the Function Argument, but Function Argument\'s VARREF \'dac_raddr\' generates 6 bits.\n                                                                                                 : ... In instance ad_axis_dma_tx\n    dac_raddr_g <= b2g(dac_raddr);\n                   ^~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/40989439/AdiHDLLib/library/common/ad_axis_dma_tx.v:190: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'b2g\' generates 8 bits.\n                                                                                                 : ... In instance ad_axis_dma_tx\n    dac_raddr_g <= b2g(dac_raddr);\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/40989439/AdiHDLLib/library/common/ad_axis_dma_tx.v:201: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                                                 : ... In instance ad_axis_dma_tx\n      dma_clkcnt <= 16\'d0;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/40989439/AdiHDLLib/library/common/ad_axis_dma_tx.v:226: Operator FUNCREF \'g2b\' expects 8 bits on the Function Argument, but Function Argument\'s VARREF \'dma_raddr_g_m2\' generates 6 bits.\n                                                                                                 : ... In instance ad_axis_dma_tx\n    dma_raddr <= g2b(dma_raddr_g_m2);\n                 ^~~\n%Warning-WIDTH: data/full_repos/permissive/40989439/AdiHDLLib/library/common/ad_axis_dma_tx.v:226: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'g2b\' generates 8 bits.\n                                                                                                 : ... In instance ad_axis_dma_tx\n    dma_raddr <= g2b(dma_raddr_g_m2);\n              ^~\n%Error: data/full_repos/permissive/40989439/AdiHDLLib/library/common/ad_axis_dma_tx.v:269: Cannot find file containing module: \'ad_mem\'\n  ad_mem #(.DATA_WIDTH(DATA_WIDTH), .ADDRESS_WIDTH(6)) i_mem (\n  ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/40989439/AdiHDLLib/library/common,data/full_repos/permissive/40989439/ad_mem\n             data/full_repos/permissive/40989439/AdiHDLLib/library/common,data/full_repos/permissive/40989439/ad_mem.v\n             data/full_repos/permissive/40989439/AdiHDLLib/library/common,data/full_repos/permissive/40989439/ad_mem.sv\n             ad_mem\n             ad_mem.v\n             ad_mem.sv\n             obj_dir/ad_mem\n             obj_dir/ad_mem.v\n             obj_dir/ad_mem.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n'
function [7:0] g2b;
    input [7:0] g;
    reg   [7:0] b;
    begin
      b[7] = g[7];
      b[6] = b[7] ^ g[6];
      b[5] = b[6] ^ g[5];
      b[4] = b[5] ^ g[4];
      b[3] = b[4] ^ g[3];
      b[2] = b[3] ^ g[2];
      b[1] = b[2] ^ g[1];
      b[0] = b[1] ^ g[0];
      g2b = b;
    end
  endfunction
function [7:0] g2b;

    input [7:0] g;
    reg   [7:0] b;
    begin
      b[7] = g[7];
      b[6] = b[7] ^ g[6];
      b[5] = b[6] ^ g[5];
      b[4] = b[5] ^ g[4];
      b[3] = b[4] ^ g[3];
      b[2] = b[3] ^ g[2];
      b[1] = b[2] ^ g[1];
      b[0] = b[1] ^ g[0];
      g2b = b;
    end
  endfunction