data/full_repos/permissive/452098851/tutorial/demo_add/bdw_work/modules/dut/BASIC/v_rtl/dut_LessThan_4Ux4U_1U_1.v
data/verilator_xmls/633a252e-db3b-48bd-ab75-292cc943300b.xml
module dut_LessThan_4Ux4U_1U_1 (
	in2,
	in1,
	out1
	);
input [3:0] in2,
	in1;
output  out1;
wire  asc001;

assign asc001 = (in1>in2);

assign out1 = asc001;
endmodule
module dut_LessThan_4Ux4U_1U_1 (
	in2,
	in1,
	out1
	);

input [3:0] in2,
	in1;
output  out1;
wire  asc001;

assign asc001 = (in1>in2);

assign out1 = asc001;
endmodule