data/full_repos/permissive/461069000/spi/src/spi.v
1: b"%Error: data/full_repos/permissive/461069000/spi/src/spi.v:58: Cannot find file containing module: 'spi_clock_generator'\n    spi_clock_generator i_spi_clock_generator(\n    ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/461069000/spi/src,data/full_repos/permissive/461069000/spi_clock_generator\n             data/full_repos/permissive/461069000/spi/src,data/full_repos/permissive/461069000/spi_clock_generator.v\n             data/full_repos/permissive/461069000/spi/src,data/full_repos/permissive/461069000/spi_clock_generator.sv\n             spi_clock_generator\n             spi_clock_generator.v\n             spi_clock_generator.sv\n             obj_dir/spi_clock_generator\n             obj_dir/spi_clock_generator.v\n             obj_dir/spi_clock_generator.sv\n%Error: data/full_repos/permissive/461069000/spi/src/spi.v:66: Cannot find file containing module: 'spi_register'\n    spi_register  i_spi_register(\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/461069000/spi/src/spi.v:90: Cannot find file containing module: 'spi_module'\n    spi_module i_spi_module(\n    ^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module spi (

    input wire clk,
    input wire rst,
    input wire enable,
    input wire write_enable,
    input wire [1:0] address,
    input wire [7:0] write_data,
    output wire [7:0] read_data,


    input sdi, 
    output sdo, 
    
    output wire cs_o,
    input wire cs_i,
    input sclk_i,
    output sclk_o,


    output wire done_int);


    localparam SPI_MASTER = 0;
    localparam SPI_SLAVE = 1;
    

    wire [2:0] prescaler_in;
    wire clock_polarity;
    wire clock_phase;
    

    wire spi_mode;
    wire process;


    wire w_ready;
    wire w_busy;
    wire w_done;


    wire done_int_en;
    assign done_int = done_int_en & w_done;


    wire [7:0] send_data;
    

    wire [7:0] received_data;




    wire modified_clock;

    spi_clock_generator i_spi_clock_generator(
        .clk(clk),
        .prescaler_in(prescaler_in),
        .spi_mode(spi_mode),
        .clk_out(modified_clock)
    );
    

    spi_register  i_spi_register(
        .clk(clk),
        .enable(enable),
        .rst(rst),
        .write_enable(write_enable),
        .address(address),
        .write_data(write_data),
        .read_data(read_data),
        .prescaler_in(prescaler_in),
        .clock_polarity(clock_polarity),
        .clock_phase(clock_phase),
        .process(process),
        .spi_mode(spi_mode),
        .send_data(send_data),
        .received_data(received_data),
        .done_int_en(done_int_en),
        .w_done(w_done),
        .w_busy(w_busy),
        .w_ready(w_ready)
    );

    wire spi_master_mode = spi_mode == 0;
    wire clock_in = spi_master_mode ? modified_clock : sclk_i;

    spi_module i_spi_module(

    .clk(clk),
    .enable(enable),
    .rst(rst),


    .spi_mode(spi_mode),
    .clock_phase(clock_phase),
    .clock_polarity(clock_polarity),

    .process(process),
    .done(w_done),
    .busy(w_busy),
    .ready(w_ready),


    .tx_data(send_data),


    .rx_data(received_data),


    .sclk_o(sclk_o),
    .sclk_i(clock_in),


    .cs_o(cs_o),
    .cs_i(cs_i),

    .sdi(sdi),
    .sdo(sdo)
);

    
    
endmodule
module spi (

    input wire clk,
    input wire rst,
    input wire enable,
    input wire write_enable,
    input wire [1:0] address,
    input wire [7:0] write_data,
    output wire [7:0] read_data,


    input sdi, 
    output sdo, 
    
    output wire cs_o,
    input wire cs_i,
    input sclk_i,
    output sclk_o,


    output wire done_int);



    localparam SPI_MASTER = 0;
    localparam SPI_SLAVE = 1;
    

    wire [2:0] prescaler_in;
    wire clock_polarity;
    wire clock_phase;
    

    wire spi_mode;
    wire process;


    wire w_ready;
    wire w_busy;
    wire w_done;


    wire done_int_en;
    assign done_int = done_int_en & w_done;


    wire [7:0] send_data;
    

    wire [7:0] received_data;




    wire modified_clock;

    spi_clock_generator i_spi_clock_generator(
        .clk(clk),
        .prescaler_in(prescaler_in),
        .spi_mode(spi_mode),
        .clk_out(modified_clock)
    );
    

    spi_register  i_spi_register(
        .clk(clk),
        .enable(enable),
        .rst(rst),
        .write_enable(write_enable),
        .address(address),
        .write_data(write_data),
        .read_data(read_data),
        .prescaler_in(prescaler_in),
        .clock_polarity(clock_polarity),
        .clock_phase(clock_phase),
        .process(process),
        .spi_mode(spi_mode),
        .send_data(send_data),
        .received_data(received_data),
        .done_int_en(done_int_en),
        .w_done(w_done),
        .w_busy(w_busy),
        .w_ready(w_ready)
    );

    wire spi_master_mode = spi_mode == 0;
    wire clock_in = spi_master_mode ? modified_clock : sclk_i;

    spi_module i_spi_module(

    .clk(clk),
    .enable(enable),
    .rst(rst),


    .spi_mode(spi_mode),
    .clock_phase(clock_phase),
    .clock_polarity(clock_polarity),

    .process(process),
    .done(w_done),
    .busy(w_busy),
    .ready(w_ready),


    .tx_data(send_data),


    .rx_data(received_data),


    .sclk_o(sclk_o),
    .sclk_i(clock_in),


    .cs_o(cs_o),
    .cs_i(cs_i),

    .sdi(sdi),
    .sdo(sdo)
);

    
    
endmodule