data/full_repos/permissive/514758517/adder.v
1: b'%Warning-WIDTH: data/full_repos/permissive/514758517/adder.v:8: Operator ADD expects 9 bits on the LHS, but LHS\'s VARREF \'in1\' generates 5 bits.\n                                                              : ... In instance add\n  assign out_add = in1 + in2;\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/514758517/adder.v:8: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'in2\' generates 5 bits.\n                                                              : ... In instance add\n  assign out_add = in1 + in2;\n                       ^\n%Error: Exiting due to 2 warning(s)\n'
module add(in1 , in2 , out_add);
  
  input signed [4:0]in1;
  input signed [4:0]in2;
  output signed [8:0]out_add;
  
  assign out_add = in1 + in2;
  
endmodule
module add(in1 , in2 , out_add);

  
  input signed [4:0]in1;
  input signed [4:0]in2;
  output signed [8:0]out_add;
  
  assign out_add = in1 + in2;
  
endmodule