data/full_repos/permissive/412284801/mux2x1/mux2x1_tb.v
1: b'%Error: data/full_repos/permissive/412284801/mux2x1/mux2x1_tb.v:3: Cannot find include file: mux2x1.v\n`include "mux2x1.v"\n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/412284801/mux2x1,data/full_repos/permissive/412284801/mux2x1.v\n             data/full_repos/permissive/412284801/mux2x1,data/full_repos/permissive/412284801/mux2x1.v.v\n             data/full_repos/permissive/412284801/mux2x1,data/full_repos/permissive/412284801/mux2x1.v.sv\n             mux2x1.v\n             mux2x1.v.v\n             mux2x1.v.sv\n             obj_dir/mux2x1.v\n             obj_dir/mux2x1.v.v\n             obj_dir/mux2x1.v.sv\n%Error: data/full_repos/permissive/412284801/mux2x1/mux2x1_tb.v:20: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("mux2x1_test.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/412284801/mux2x1/mux2x1_tb.v:21: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,mux2x1_test);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/412284801/mux2x1/mux2x1_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #100 $finish;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/412284801/mux2x1/mux2x1_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n always #5 a1=~a1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/412284801/mux2x1/mux2x1_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n always #10 a0=~a0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/412284801/mux2x1/mux2x1_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n  always #20 s=~s;\n         ^\n%Error: data/full_repos/permissive/412284801/mux2x1/mux2x1_tb.v:34: Unsupported or unknown PLI call: $monitor\n    $monitor("time=%0t s=%d a0=%d a1=%d output=%d",$time,s,a0,a1,y);\n    ^~~~~~~~\n%Error: Exiting due to 4 error(s), 4 warning(s)\n'
module mux2x1_test;

	reg a0;
	reg a1;
	reg s;
	wire y;

	mux2x1 uut (
		.a0(a0), 
		.a1(a1), 
		.s(s), 
		.y(y)
	);

	initial begin
		$dumpfile("mux2x1_test.vcd");
    $dumpvars(0,mux2x1_test);
		a0 = 1'b0;
		a1 = 1'b0;
		s = 1'b0;

		#100 $finish;
  end

	always #5 a1=~a1;
	always #10 a0=~a0;
  always #20 s=~s;

	initial
    $monitor("time=%0t s=%d a0=%d a1=%d output=%d",$time,s,a0,a1,y);
      
endmodule
module mux2x1_test;


	reg a0;
	reg a1;
	reg s;
	wire y;

	mux2x1 uut (
		.a0(a0), 
		.a1(a1), 
		.s(s), 
		.y(y)
	);

	initial begin
		$dumpfile("mux2x1_test.vcd");
    $dumpvars(0,mux2x1_test);
		a0 = 1'b0;
		a1 = 1'b0;
		s = 1'b0;

		#100 $finish;
  end

	always #5 a1=~a1;
	always #10 a0=~a0;
  always #20 s=~s;

	initial
    $monitor("time=%0t s=%d a0=%d a1=%d output=%d",$time,s,a0,a1,y);
      
endmodule