data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_simple_function.v
data/verilator_xmls/09fb6bad-7ce8-4f92-a2b4-dee5588d318f.xml
function  myfunction;
input a, b, c, d;
begin
  myfunction = ((a+b) + (c-d));
end
endfunction
function  myfunction;

input a, b, c, d;
begin
  myfunction = ((a+b) + (c-d));
end
endfunction