data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/sha3/sha3_comb.v
1: b'%Warning-WIDTH: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/sha3/sha3_comb.v:40: Operator ASSIGNW expects 1600 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 576 bits.\n                                                                                                     : ... In instance sha3_comb\n  assign round_in[0] = {e_input, g_input};\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/sha3/sha3_comb.v:56: Cannot find file containing module: \'rconst\'\n   rconst rconst_ \n   ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/sha3,data/full_repos/permissive/486954482/rconst\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/sha3,data/full_repos/permissive/486954482/rconst.v\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/sha3,data/full_repos/permissive/486954482/rconst.sv\n             rconst\n             rconst.v\n             rconst.sv\n             obj_dir/rconst\n             obj_dir/rconst.v\n             obj_dir/rconst.sv\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/sha3/sha3_comb.v:68: Cannot find file containing module: \'rconst\'\n   rconst rconst_ \n   ^~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/sha3/sha3_comb.v:62: Cannot find file containing module: \'rconst\'\n   rconst rconst_ \n   ^~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/sha3/sha3_comb.v:80: Cannot find file containing module: \'round\'\n round \n ^~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n'
module sha3_comb
#(
	parameter CC=1
)
(
	clk,
	rst, 
	g_input,
  e_input,
	o
);

  input             clk;
  input 				    rst;
  input	  [287:0]		g_input;
  input   [287:0]   e_input;
  output  [1599:0]	o;
  wire	  [63:0]		rc [24/CC-1:0];
  wire	  [1599:0]	round_in [24/CC-1:0];
  wire 	  [1599:0]	round_out [24/CC-1:0];
    
	
  assign round_in[0] = {e_input, g_input};
	assign o = round_out[24/CC-1];

	genvar q;
	
	generate
	for(q=1;q<24/CC;q=q+1)
	begin:ASSROUND
		assign round_in[q] = round_out[q-1];
	end
	endgenerate
	
	generate
	for(q=0;q<24/CC;q=q+1)
	begin:RCONST
		if(q==0)
			rconst rconst_ 
			(
				.i({{(24/CC-q-1){1'b0}}, 1'b1}),
				.rc(rc[q])
			);
		else if(q==24/CC-1)
			rconst rconst_ 
			(
				.i({1'b1, {(q){1'b0}}}),
				.rc(rc[q])
			);
		else
			rconst rconst_ 
			(
				.i({{(24/CC-q-1){1'b0}}, 1'b1, {(q){1'b0}}}),
				.rc(rc[q])
			);
	end
	endgenerate
	

	generate
	for(q=0;q<24/CC;q=q+1)
	begin:ROUND
	round 
		round_ 
		(
			.in(round_in[q]), 
			.round_const(rc[q]), 
			.out(round_out[q])
		);
	end
	endgenerate
	
endmodule
module sha3_comb
#(
	parameter CC=1
)
(
	clk,
	rst, 
	g_input,
  e_input,
	o
);


  input             clk;
  input 				    rst;
  input	  [287:0]		g_input;
  input   [287:0]   e_input;
  output  [1599:0]	o;
  wire	  [63:0]		rc [24/CC-1:0];
  wire	  [1599:0]	round_in [24/CC-1:0];
  wire 	  [1599:0]	round_out [24/CC-1:0];
    
	
  assign round_in[0] = {e_input, g_input};
	assign o = round_out[24/CC-1];

	genvar q;
	
	generate
	for(q=1;q<24/CC;q=q+1)
	begin:ASSROUND
		assign round_in[q] = round_out[q-1];
	end
	endgenerate
	
	generate
	for(q=0;q<24/CC;q=q+1)
	begin:RCONST
		if(q==0)
			rconst rconst_ 
			(
				.i({{(24/CC-q-1){1'b0}}, 1'b1}),
				.rc(rc[q])
			);
		else if(q==24/CC-1)
			rconst rconst_ 
			(
				.i({1'b1, {(q){1'b0}}}),
				.rc(rc[q])
			);
		else
			rconst rconst_ 
			(
				.i({{(24/CC-q-1){1'b0}}, 1'b1, {(q){1'b0}}}),
				.rc(rc[q])
			);
	end
	endgenerate
	

	generate
	for(q=0;q<24/CC;q=q+1)
	begin:ROUND
	round 
		round_ 
		(
			.in(round_in[q]), 
			.round_const(rc[q]), 
			.out(round_out[q])
		);
	end
	endgenerate
	
endmodule