data/full_repos/permissive/521337848/Hardware/procesor/aluX.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/521337848/Hardware/procesor/aluX.v:111: Cell has missing pin: \'sreg3\'\ncollectsubreg csr(.bank(bank[1]),\n              ^~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/521337848/Hardware/procesor/aluX.v:111: Cell has missing pin: \'sreg4\'\ncollectsubreg csr(.bank(bank[1]),\n              ^~~\n%Error: Exiting due to 2 warning(s)\n'
module registers(
	input clk,
	input rst,
	
	input save,
	input[1:0] bank,
	
	input[15:0] f_sreg1,
	input[15:0] f_sreg2,
	input[15:0] f_sreg3,
	input[15:0] f_sreg4,
	
	output[15:0] sreg1,
	output[15:0] sreg2,
	output[15:0] sreg3,
	output[15:0] sreg4
);



register r1(.bank(bank),
		
				.clk(clk),
				.rst(rst),
				.save(save),
				
				.f_reg(f_sreg1),
	
				.s_reg(sreg1)
);

register r2(.bank(bank),
		
				.clk(clk),
				.rst(rst),
	
				.f_reg(f_sreg2),
				.save(save),
				
				.s_reg(sreg2)
);

register r3(.bank(bank),
		
				.clk(clk),
				.rst(rst),
	
				.f_reg(f_sreg3),
				.save(save),
				
				.s_reg(sreg3)
);

register r4(.bank(bank),
		
				.clk(clk),
				.rst(rst),
	
				.f_reg(f_sreg4),
				.save(save),
				
				.s_reg(sreg4)
);

endmodule
module registers(
	input clk,
	input rst,
	
	input save,
	input[1:0] bank,
	
	input[15:0] f_sreg1,
	input[15:0] f_sreg2,
	input[15:0] f_sreg3,
	input[15:0] f_sreg4,
	
	output[15:0] sreg1,
	output[15:0] sreg2,
	output[15:0] sreg3,
	output[15:0] sreg4
);




register r1(.bank(bank),
		
				.clk(clk),
				.rst(rst),
				.save(save),
				
				.f_reg(f_sreg1),
	
				.s_reg(sreg1)
);

register r2(.bank(bank),
		
				.clk(clk),
				.rst(rst),
	
				.f_reg(f_sreg2),
				.save(save),
				
				.s_reg(sreg2)
);

register r3(.bank(bank),
		
				.clk(clk),
				.rst(rst),
	
				.f_reg(f_sreg3),
				.save(save),
				
				.s_reg(sreg3)
);

register r4(.bank(bank),
		
				.clk(clk),
				.rst(rst),
	
				.f_reg(f_sreg4),
				.save(save),
				
				.s_reg(sreg4)
);

endmodule