data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Multiplexers/64_Mux256to1.v
data/verilator_xmls/ae0638b1-c182-42d8-9db4-90b06b1ca72c.xml
module top_module( 
    input [255:0] in,
    input [7:0] sel,
    output out );

    assign out = in[sel];
endmodule
module top_module( 
    input [255:0] in,
    input [7:0] sel,
    output out );


    assign out = in[sel];
endmodule