data/full_repos/permissive/468755927/verilog/beh/ir_behavioral_driver.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/468755927/verilog/beh/ir_behavioral_driver.v:96: Unsupported: Ignoring delay on this delayed statement.\n    #(p_period*16) ir_signal = ~p_polarity;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/468755927/verilog/beh/ir_behavioral_driver.v:97: Unsupported: Ignoring delay on this delayed statement.\n    #(p_period*8)  ir_signal =  p_polarity;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468755927/verilog/beh/ir_behavioral_driver.v:109: Unsupported: Ignoring delay on this delayed statement.\n    #(p_period)  ir_signal = ~p_polarity;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468755927/verilog/beh/ir_behavioral_driver.v:111: Unsupported: Ignoring delay on this delayed statement.\n      #(p_period*3)  ir_signal = p_polarity;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/468755927/verilog/beh/ir_behavioral_driver.v:113: Unsupported: Ignoring delay on this delayed statement.\n      #(p_period)  ir_signal = p_polarity;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/468755927/verilog/beh/ir_behavioral_driver.v:124: Unsupported: Ignoring delay on this delayed statement.\n    #(p_period) ir_signal = ~p_polarity;\n    ^\n%Error: Exiting due to 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ir_behavioral_driver (
  output reg       ir_signal
);

  reg     p_polarity;
  integer p_period;
  integer i;




  task init(
    input         polarity,
    input integer tick_period_ns
  );
  begin
    $display("simetime = %g : Init IR interface with", $time);
    $display("simetime = %g :  - polarity = %b", $time, polarity);
    $display("simetime = %g :  - period to %d ns", $time, tick_period_ns); 
    

    p_polarity = polarity;
    p_period = tick_period_ns;
    

    ir_signal = ~p_polarity;

  end
  endtask
  



  task send_nec(
    input [7:0] addr,
    input [7:0] data
  );
  begin
    $display("simetime = %g : Send IR NEC trame (0x%h -> 0x%h)", $time, addr, data);

    send_start();
    

    for (i=0 ; i<8 ; i=i+1) begin
      send_bit(addr[i]);
    end
    

    for (i=0 ; i<8 ; i=i+1) begin
      send_bit(~addr[i]);
    end
    

    for (i=0 ; i<8 ; i=i+1) begin
      send_bit(data[i]);
    end
    

    for (i=0 ; i<8 ; i=i+1) begin
      send_bit(~data[i]);
    end
    

    send_stop();
    

  end
  endtask




  task send_start;
  begin
    ir_signal = p_polarity;
    #(p_period*16) ir_signal = ~p_polarity;
    #(p_period*8)  ir_signal =  p_polarity;
  end 
  endtask
  



  task send_bit(
    input reg value
  );
  begin
    ir_signal = p_polarity;
    #(p_period)  ir_signal = ~p_polarity;
    if (value == 1'b1) begin
      #(p_period*3)  ir_signal = p_polarity;
    end else begin
      #(p_period)  ir_signal = p_polarity;
    end
  end 
  endtask
  



  task send_stop;
  begin
    ir_signal = p_polarity;
    #(p_period) ir_signal = ~p_polarity;
  end 
  endtask
  
endmodule
module ir_behavioral_driver (
  output reg       ir_signal
);


  reg     p_polarity;
  integer p_period;
  integer i;




  task init(
    input         polarity,
    input integer tick_period_ns
  );
  begin
    $display("simetime = %g : Init IR interface with", $time);
    $display("simetime = %g :  - polarity = %b", $time, polarity);
    $display("simetime = %g :  - period to %d ns", $time, tick_period_ns); 
    

    p_polarity = polarity;
    p_period = tick_period_ns;
    

    ir_signal = ~p_polarity;

  end
  endtask
  



  task send_nec(
    input [7:0] addr,
    input [7:0] data
  );
  begin
    $display("simetime = %g : Send IR NEC trame (0x%h -> 0x%h)", $time, addr, data);

    send_start();
    

    for (i=0 ; i<8 ; i=i+1) begin
      send_bit(addr[i]);
    end
    

    for (i=0 ; i<8 ; i=i+1) begin
      send_bit(~addr[i]);
    end
    

    for (i=0 ; i<8 ; i=i+1) begin
      send_bit(data[i]);
    end
    

    for (i=0 ; i<8 ; i=i+1) begin
      send_bit(~data[i]);
    end
    

    send_stop();
    

  end
  endtask




  task send_start;
  begin
    ir_signal = p_polarity;
    #(p_period*16) ir_signal = ~p_polarity;
    #(p_period*8)  ir_signal =  p_polarity;
  end 
  endtask
  



  task send_bit(
    input reg value
  );
  begin
    ir_signal = p_polarity;
    #(p_period)  ir_signal = ~p_polarity;
    if (value == 1'b1) begin
      #(p_period*3)  ir_signal = p_polarity;
    end else begin
      #(p_period)  ir_signal = p_polarity;
    end
  end 
  endtask
  



  task send_stop;
  begin
    ir_signal = p_polarity;
    #(p_period) ir_signal = ~p_polarity;
  end 
  endtask
  
endmodule