data/full_repos/permissive/518305690/iiitb_lfsr_tb.v
1: b'%Error: data/full_repos/permissive/518305690/iiitb_lfsr_tb.v:12: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile ("iiitb_lfsr.vcd"); \n  ^~~~~~~~~\n%Error: data/full_repos/permissive/518305690/iiitb_lfsr_tb.v:13: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0,iiitb_lfsr_tb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/518305690/iiitb_lfsr_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n#10 rst = 1;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/518305690/iiitb_lfsr_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n#10 rst = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/518305690/iiitb_lfsr_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n#50 clk = !clk;\n^\n%Warning-STMTDLY: data/full_repos/permissive/518305690/iiitb_lfsr_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n#100 seed = 4\'b0001;\n^\n%Warning-STMTDLY: data/full_repos/permissive/518305690/iiitb_lfsr_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n#100 load = 0;\n^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module iiitb_lfsr_tb;
reg clk;
reg rst;
reg [3:0] seed;
reg load;
wire q;
iiitb_lfsr L(q, clk, rst, seed, load);


initial
begin
  $dumpfile ("iiitb_lfsr.vcd"); 
  $dumpvars(0,iiitb_lfsr_tb);
clk = 0;
load = 0;
seed = 0;
rst = 0;
#10 rst = 1;
#10 rst = 0;
end

always
#50 clk = !clk;

initial begin
#100 seed = 4'b0001;
load = 1;
#100 load = 0;
end
endmodule
module iiitb_lfsr_tb;

reg clk;
reg rst;
reg [3:0] seed;
reg load;
wire q;
iiitb_lfsr L(q, clk, rst, seed, load);


initial
begin
  $dumpfile ("iiitb_lfsr.vcd"); 
  $dumpvars(0,iiitb_lfsr_tb);
clk = 0;
load = 0;
seed = 0;
rst = 0;
#10 rst = 1;
#10 rst = 0;
end

always
#50 clk = !clk;

initial begin
#100 seed = 4'b0001;
load = 1;
#100 load = 0;
end
endmodule