data/full_repos/permissive/43856783/j1_soc/hdl/LCD/Periphera_Test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/LCD/Periphera_Test.v:97: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/LCD/Periphera_Test.v:103: Unsupported: Ignoring delay on this delayed statement.\n  #100;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/LCD/Periphera_Test.v:109: Unsupported: Ignoring delay on this delayed statement.\n  #20;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/LCD/Periphera_Test.v:112: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/LCD/Periphera_Test.v:115: Unsupported: Ignoring delay on this delayed statement.\n  #20;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/LCD/Periphera_Test.v:120: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/LCD/Periphera_Test.v:121: Unsupported: Ignoring delay on this delayed statement.\n  while(d_out == 0) #5;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/LCD/Periphera_Test.v:125: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/LCD/Periphera_Test.v:130: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/LCD/Periphera_Test.v:134: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/LCD/Periphera_Test.v:138: Unsupported: Ignoring delay on this delayed statement.\n  while(d_out != 0) #5;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/LCD/Periphera_Test.v:142: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = !clk;\n        ^\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/LCD/Periphera_Test.v:49: Cannot find file containing module: \'clk_counter\'\n clk_counter count(\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43856783/j1_soc/hdl/LCD,data/full_repos/permissive/43856783/clk_counter\n             data/full_repos/permissive/43856783/j1_soc/hdl/LCD,data/full_repos/permissive/43856783/clk_counter.v\n             data/full_repos/permissive/43856783/j1_soc/hdl/LCD,data/full_repos/permissive/43856783/clk_counter.sv\n             clk_counter\n             clk_counter.v\n             clk_counter.sv\n             obj_dir/clk_counter\n             obj_dir/clk_counter.v\n             obj_dir/clk_counter.sv\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/LCD/Periphera_Test.v:56: Cannot find file containing module: \'clk_interruptor\'\n clk_interruptor intGen(\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/LCD/Periphera_Test.v:65: Cannot find file containing module: \'LCD_Peripheral\'\n LCD_Peripheral uut (\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Periphera_Test;


	reg clk;
	reg rst;
	reg [15:0] d_in;
	reg cs;
	reg [3:0] addr;
	reg rd;
	reg wr;
	wire int_cnt;


	wire e;
	wire rs;
	wire [7:0] data;
	wire [15:0] d_out;
	wire en_cnt;
	wire [15:0] limit_cnt;
	
	wire [31:0] mcount;
	reg mcoun_en;
	reg mcoun_rst;
	
	clk_counter count(
		.clk(clk),
		.en(mcoun_en),
		.rst(mcoun_rst),
		.count(mcount)
	);
	
	clk_interruptor intGen(
		.clk(clk),
		.en(en_cnt),
		.limit({16'h0000,limit_cnt}),
		.count(mcount),
		.int_0(int_cnt)
	);


	LCD_Peripheral uut (
		.clk(clk), 
		.rst(rst), 
		.d_in(d_in), 
		.cs(cs), 
		.addr(addr), 
		.rd(rd), 
		.wr(wr), 
		.e(e), 
		.rs(rs), 
		.data(data), 
		.int_cnt(int_cnt),
		.en_cnt(en_cnt),
		.limit_cnt(limit_cnt),
		.d_out(d_out)
	);
	
	reg putamierda;
	
	initial begin

		clk = 0;
		rst = 1;
		d_in = 0;
		cs = 0;
		addr = 0;
		rd = 0;
		wr = 0;
		mcoun_rst = 1;
		mcoun_en = 0;


		#100;
		rst = 0;
		mcoun_rst = 0;
		mcoun_en = 1;

		
		#100;
		cs = 1;
		wr = 1;
		d_in = 1;
		addr = 1;
		
		#20;
		addr = 0;
		
		#100;
		putamierda = 1;
		
		#20;
		wr = 0;
		rd = 1;
		d_in = 0;
		addr = 10;
		#20;
		while(d_out == 0) #5;
		cs = 0;
		rd = 0;
		wr = 0;
		#20;
		addr = 0;
		cs = 1;
		wr = 1;
		d_in = 0;
		#20
		cs = 0;
		rd = 0;
		wr = 0;
		#20;
		addr = 10;
		cs =1;
		rd = 1;
		while(d_out != 0) #5;
		
	end
	
	always #5 clk = !clk;
	
endmodule
module Periphera_Test;



	reg clk;
	reg rst;
	reg [15:0] d_in;
	reg cs;
	reg [3:0] addr;
	reg rd;
	reg wr;
	wire int_cnt;


	wire e;
	wire rs;
	wire [7:0] data;
	wire [15:0] d_out;
	wire en_cnt;
	wire [15:0] limit_cnt;
	
	wire [31:0] mcount;
	reg mcoun_en;
	reg mcoun_rst;
	
	clk_counter count(
		.clk(clk),
		.en(mcoun_en),
		.rst(mcoun_rst),
		.count(mcount)
	);
	
	clk_interruptor intGen(
		.clk(clk),
		.en(en_cnt),
		.limit({16'h0000,limit_cnt}),
		.count(mcount),
		.int_0(int_cnt)
	);


	LCD_Peripheral uut (
		.clk(clk), 
		.rst(rst), 
		.d_in(d_in), 
		.cs(cs), 
		.addr(addr), 
		.rd(rd), 
		.wr(wr), 
		.e(e), 
		.rs(rs), 
		.data(data), 
		.int_cnt(int_cnt),
		.en_cnt(en_cnt),
		.limit_cnt(limit_cnt),
		.d_out(d_out)
	);
	
	reg putamierda;
	
	initial begin

		clk = 0;
		rst = 1;
		d_in = 0;
		cs = 0;
		addr = 0;
		rd = 0;
		wr = 0;
		mcoun_rst = 1;
		mcoun_en = 0;


		#100;
		rst = 0;
		mcoun_rst = 0;
		mcoun_en = 1;

		
		#100;
		cs = 1;
		wr = 1;
		d_in = 1;
		addr = 1;
		
		#20;
		addr = 0;
		
		#100;
		putamierda = 1;
		
		#20;
		wr = 0;
		rd = 1;
		d_in = 0;
		addr = 10;
		#20;
		while(d_out == 0) #5;
		cs = 0;
		rd = 0;
		wr = 0;
		#20;
		addr = 0;
		cs = 1;
		wr = 1;
		d_in = 0;
		#20
		cs = 0;
		rd = 0;
		wr = 0;
		#20;
		addr = 10;
		cs =1;
		rd = 1;
		while(d_out != 0) #5;
		
	end
	
	always #5 clk = !clk;
	
endmodule