data/full_repos/permissive/463481430/RTL/core/pipe_ctrl.v
1: b'%Error: data/full_repos/permissive/463481430/RTL/core/pipe_ctrl.v:5: Cannot find include file: config.v\n`include "config.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463481430/RTL/core,data/full_repos/permissive/463481430/config.v\n             data/full_repos/permissive/463481430/RTL/core,data/full_repos/permissive/463481430/config.v.v\n             data/full_repos/permissive/463481430/RTL/core,data/full_repos/permissive/463481430/config.v.sv\n             config.v\n             config.v.v\n             config.v.sv\n             obj_dir/config.v\n             obj_dir/config.v.v\n             obj_dir/config.v.sv\n%Error: data/full_repos/permissive/463481430/RTL/core/pipe_ctrl.v:14: Define or directive not defined: \'`rfidxlen_def\'\n    input wire[`rfidxlen_def] i_bpu_rs1idx,\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/pipe_ctrl.v:14: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire[`rfidxlen_def] i_bpu_rs1idx,\n                            ^\n%Error: data/full_repos/permissive/463481430/RTL/core/pipe_ctrl.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[`rfidxlen_def] i_bpu_rs2idx,\n    ^~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/pipe_ctrl.v:16: Define or directive not defined: \'`rfidxlen_def\'\n    input wire[`rfidxlen_def] i_bpu_rs2idx,\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/pipe_ctrl.v:19: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[`rfidxlen_def] i_exu_rdidx0,\n    ^~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/pipe_ctrl.v:19: Define or directive not defined: \'`rfidxlen_def\'\n    input wire[`rfidxlen_def] i_exu_rdidx0,\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/pipe_ctrl.v:21: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[`rfidxlen_def] i_exu_rdidx1,\n    ^~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/pipe_ctrl.v:21: Define or directive not defined: \'`rfidxlen_def\'\n    input wire[`rfidxlen_def] i_exu_rdidx1,\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/pipe_ctrl.v:23: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[`rfidxlen_def] i_exu_rdidx2,\n    ^~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/pipe_ctrl.v:23: Define or directive not defined: \'`rfidxlen_def\'\n    input wire[`rfidxlen_def] i_exu_rdidx2,\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/pipe_ctrl.v:28: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire i_wb_match,\n    ^~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/pipe_ctrl.v:30: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire o_ifu_wait,\n    ^~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/pipe_ctrl.v:31: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire o_bpu_wait,\n    ^~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/pipe_ctrl.v:32: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire o_dis_wait,\n    ^~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/pipe_ctrl.v:34: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire o_dis_flush\n    ^~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/pipe_ctrl.v:58: syntax error, unexpected assign\n    assign o_ifu_wait = i_exu_resource_match | read_after_write | i_wb_match;\n    ^~~~~~\n%Error: Exiting due to 17 error(s)\n'
module PIPE_CTRL (



    input wire i_bpu_rs1ren,
    input wire[`rfidxlen_def] i_bpu_rs1idx,
    input wire i_bpu_rs2ren,
    input wire[`rfidxlen_def] i_bpu_rs2idx,

    input wire i_exu_rdwen0,
    input wire[`rfidxlen_def] i_exu_rdidx0,
    input wire i_exu_rdwen1,
    input wire[`rfidxlen_def] i_exu_rdidx1,
    input wire i_exu_rdwen2,
    input wire[`rfidxlen_def] i_exu_rdidx2,


    input wire i_exu_resource_match,

    input wire i_wb_match,

    output wire o_ifu_wait,
    output wire o_bpu_wait,
    output wire o_dis_wait,

    output wire o_dis_flush

);




    wire rs1_match =    i_bpu_rs1ren ? 
                        (
                        (i_exu_rdwen0 & (i_bpu_rs1idx == i_exu_rdidx0)) |
                        (i_exu_rdwen1 & (i_bpu_rs1idx == i_exu_rdidx1)) |
                        (i_exu_rdwen2 & (i_bpu_rs1idx == i_exu_rdidx2))
                        ) : 0;
    wire rs2_match =   i_bpu_rs2ren ? 
                        (
                        (i_exu_rdwen0 & (i_bpu_rs2idx == i_exu_rdidx0)) |
                        (i_exu_rdwen1 & (i_bpu_rs2idx == i_exu_rdidx1)) |
                        (i_exu_rdwen2 & (i_bpu_rs2idx == i_exu_rdidx2))
                        ) : 0;


    wire read_after_write = rs1_match | rs2_match;


    assign o_ifu_wait = i_exu_resource_match | read_after_write | i_wb_match;
    assign o_bpu_wait = i_exu_resource_match | read_after_write | i_wb_match;

    assign o_dis_wait = i_exu_resource_match | i_wb_match;




    assign o_dis_flush = (i_exu_resource_match | i_wb_match) ? 0 : read_after_write;










    
endmodule
module PIPE_CTRL (



    input wire i_bpu_rs1ren,
    input wire[`rfidxlen_def] i_bpu_rs1idx,
    input wire i_bpu_rs2ren,
    input wire[`rfidxlen_def] i_bpu_rs2idx,

    input wire i_exu_rdwen0,
    input wire[`rfidxlen_def] i_exu_rdidx0,
    input wire i_exu_rdwen1,
    input wire[`rfidxlen_def] i_exu_rdidx1,
    input wire i_exu_rdwen2,
    input wire[`rfidxlen_def] i_exu_rdidx2,


    input wire i_exu_resource_match,

    input wire i_wb_match,

    output wire o_ifu_wait,
    output wire o_bpu_wait,
    output wire o_dis_wait,

    output wire o_dis_flush

);





    wire rs1_match =    i_bpu_rs1ren ? 
                        (
                        (i_exu_rdwen0 & (i_bpu_rs1idx == i_exu_rdidx0)) |
                        (i_exu_rdwen1 & (i_bpu_rs1idx == i_exu_rdidx1)) |
                        (i_exu_rdwen2 & (i_bpu_rs1idx == i_exu_rdidx2))
                        ) : 0;
    wire rs2_match =   i_bpu_rs2ren ? 
                        (
                        (i_exu_rdwen0 & (i_bpu_rs2idx == i_exu_rdidx0)) |
                        (i_exu_rdwen1 & (i_bpu_rs2idx == i_exu_rdidx1)) |
                        (i_exu_rdwen2 & (i_bpu_rs2idx == i_exu_rdidx2))
                        ) : 0;


    wire read_after_write = rs1_match | rs2_match;


    assign o_ifu_wait = i_exu_resource_match | read_after_write | i_wb_match;
    assign o_bpu_wait = i_exu_resource_match | read_after_write | i_wb_match;

    assign o_dis_wait = i_exu_resource_match | i_wb_match;




    assign o_dis_flush = (i_exu_resource_match | i_wb_match) ? 0 : read_after_write;










    
endmodule