data/full_repos/permissive/439345921/Keyboard.v
data/verilator_xmls/dcf2661a-e7ce-4080-8d36-1c15dee26ed4.xml
module Keyboard (
	input wire rst_n,
	input wire sck,
	input wire mosi,
	input wire cs_n,
	output reg [7:0] key
);
	reg [7:0] key_pre;
	
	initial begin
		key = 8'd0;
		key_pre = 8'd0;
	end
	

	always @(posedge cs_n or negedge rst_n) begin
		if (rst_n == 1'b0) key <= 8'd0;
		else key <= key_pre;
	end
	

	always @(posedge sck or negedge rst_n) begin
		if (rst_n == 1'b0) key_pre <= 8'd0;
		else key_pre <= {key_pre[6:0], mosi};
	end
	
endmodule
module Keyboard (
	input wire rst_n,
	input wire sck,
	input wire mosi,
	input wire cs_n,
	output reg [7:0] key
);

	reg [7:0] key_pre;
	
	initial begin
		key = 8'd0;
		key_pre = 8'd0;
	end
	

	always @(posedge cs_n or negedge rst_n) begin
		if (rst_n == 1'b0) key <= 8'd0;
		else key <= key_pre;
	end
	

	always @(posedge sck or negedge rst_n) begin
		if (rst_n == 1'b0) key_pre <= 8'd0;
		else key_pre <= {key_pre[6:0], mosi};
	end
	
endmodule