data/full_repos/permissive/459421171/Pipelined/fetch_decode_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_decode_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;PC=64\'d64;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_decode_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_decode_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;PC=valP;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_decode_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_decode_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;PC=valP;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_decode_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_decode_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;PC=valP;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_decode_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_decode_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;PC=64\'d10;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_decode_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_decode_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;PC=valP;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_decode_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_decode_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;PC=valP;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_decode_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_decode_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;PC=valP;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_decode_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_decode_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;PC=valP;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_decode_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_decode_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;PC=valP;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_decode_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_decode_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;PC=valP;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_decode_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_decode_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;PC=valP;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_decode_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_decode_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;PC=valP;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_decode_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/fetch_decode_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Error: data/full_repos/permissive/459421171/Pipelined/fetch_decode_tb.v:95: Unsupported or unknown PLI call: $monitor\n   $monitor("clk=%d icode=%b ifun=%b rA=%d rB=%d valA=%d valB=%d P=%d\\n ",clk,iCode,iFun,rA,rB,valA,valB,valP);\n   ^~~~~~~~\n%Error: Exiting due to 1 error(s), 27 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fetch_decode_tb;
  reg clk;
  reg [63:0] PC;
  reg [63:0] memreg[0:14];

  wire [3:0] iCode;
  wire [3:0] iFun;
  wire [3:0] rA;
  wire [3:0] rB; 
  wire [63:0] valC;
  wire [63:0] valP;
  wire [63:0] valA;
   wire [63:0] valB;
  integer i,j;

   
    
  initial begin
  memreg[0] = 64'd0;

    
    
       for(i=1;i<15;i = i+1)
    begin
      memreg[i] = memreg[i-1] + 1;
    end
  end
  
  

  fetch fetch(
    .clk(clk),
    .PC(PC),
    
    .rA(rA),
    .rB(rB),
    
    .iCode(iCode),
    .iFun(iFun),
    .valC(valC),
    .valP(valP)
  );

  decode decode(
    .clk(clk),
    .iCode(iCode),
    .rA(rA),
    .rB(rB),
    .reg_stackA(memreg[rA]),
    .reg_stackB(memreg[rB]),
    .reg_stack4(memreg[4]),

    
    .valA(valA),
    .valB(valB)
  );

  initial 
  begin
  
   clk = 1;
  
     

    #10 clk=~clk;PC=64'd64;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=64'd10;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;
  end 
  
  initial
   $monitor("clk=%d icode=%b ifun=%b rA=%d rB=%d valA=%d valB=%d P=%d\n ",clk,iCode,iFun,rA,rB,valA,valB,valP);


endmodule
module fetch_decode_tb;

  reg clk;
  reg [63:0] PC;
  reg [63:0] memreg[0:14];

  wire [3:0] iCode;
  wire [3:0] iFun;
  wire [3:0] rA;
  wire [3:0] rB; 
  wire [63:0] valC;
  wire [63:0] valP;
  wire [63:0] valA;
   wire [63:0] valB;
  integer i,j;

   
    
  initial begin
  memreg[0] = 64'd0;

    
    
       for(i=1;i<15;i = i+1)
    begin
      memreg[i] = memreg[i-1] + 1;
    end
  end
  
  

  fetch fetch(
    .clk(clk),
    .PC(PC),
    
    .rA(rA),
    .rB(rB),
    
    .iCode(iCode),
    .iFun(iFun),
    .valC(valC),
    .valP(valP)
  );

  decode decode(
    .clk(clk),
    .iCode(iCode),
    .rA(rA),
    .rB(rB),
    .reg_stackA(memreg[rA]),
    .reg_stackB(memreg[rB]),
    .reg_stack4(memreg[4]),

    
    .valA(valA),
    .valB(valB)
  );

  initial 
  begin
  
   clk = 1;
  
     

    #10 clk=~clk;PC=64'd64;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=64'd10;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;
    #10 clk=~clk;
  end 
  
  initial
   $monitor("clk=%d icode=%b ifun=%b rA=%d rB=%d valA=%d valB=%d P=%d\n ",clk,iCode,iFun,rA,rB,valA,valB,valP);


endmodule