data/full_repos/permissive/491294671/minutes_seconds_timer/modulos_nivel3/counter_mod10_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/491294671/minutes_seconds_timer/modulos_nivel3/counter_mod10_TB.v:13: Unsupported: Ignoring delay on this delayed statement.\n    always #5000 clock <= !clock;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/491294671/minutes_seconds_timer/modulos_nivel3/counter_mod10_TB.v:16: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("counter_mod10_TB.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/491294671/minutes_seconds_timer/modulos_nivel3/counter_mod10_TB.v:17: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0,counter_mod10_TB);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/491294671/minutes_seconds_timer/modulos_nivel3/counter_mod10_TB.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #50000 loadn = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/491294671/minutes_seconds_timer/modulos_nivel3/counter_mod10_TB.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #50000 loadn = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/491294671/minutes_seconds_timer/modulos_nivel3/counter_mod10_TB.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #50000 en = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/491294671/minutes_seconds_timer/modulos_nivel3/counter_mod10_TB.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #150000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/491294671/minutes_seconds_timer/modulos_nivel3/counter_mod10_TB.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #50000; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/491294671/minutes_seconds_timer/modulos_nivel3/counter_mod10_TB.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #50000; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/491294671/minutes_seconds_timer/modulos_nivel3/counter_mod10_TB.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #50000; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/491294671/minutes_seconds_timer/modulos_nivel3/counter_mod10_TB.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #150000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/491294671/minutes_seconds_timer/modulos_nivel3/counter_mod10_TB.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #50000; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/491294671/minutes_seconds_timer/modulos_nivel3/counter_mod10_TB.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #50000; $finish;\n        ^\n%Error: Exiting due to 2 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module counter_mod10_TB ();

    reg [3:0] data;
    reg loadn, clearn, clock, en;

    wire [3:0] digit;
    wire zero, tc;

    counter_mod10 dut(.loadn(loadn), .clearn(clearn), .clock(clock), .en(en), .data(data), .tc(tc),.zero(zero),.digit(digit));

    always #5000 clock <= !clock;

    initial begin
        $dumpfile("counter_mod10_TB.vcd");
        $dumpvars(0,counter_mod10_TB);
        
    end

    initial begin
        clock = 1'b0; data = 4'b1001; 
        loadn = 1'b1; 
        clearn = 1'b1; 
        en = 1'b0;
        #50000 loadn = 1'b0;
        #50000 loadn = 1'b1;
        #50000 en = 1'b1;
        #150000;
        en = 1'b0;
        #50000; 
        clearn = 1'b0;
        #50000; 
        clearn = 1'b1;
        #50000; 
        en = 1'b1;
        #150000;
        clearn = 1'b0;
        #50000; 
        clearn = 1'b1;
        #50000; $finish;
    end    
endmodule
module counter_mod10_TB ();


    reg [3:0] data;
    reg loadn, clearn, clock, en;

    wire [3:0] digit;
    wire zero, tc;

    counter_mod10 dut(.loadn(loadn), .clearn(clearn), .clock(clock), .en(en), .data(data), .tc(tc),.zero(zero),.digit(digit));

    always #5000 clock <= !clock;

    initial begin
        $dumpfile("counter_mod10_TB.vcd");
        $dumpvars(0,counter_mod10_TB);
        
    end

    initial begin
        clock = 1'b0; data = 4'b1001; 
        loadn = 1'b1; 
        clearn = 1'b1; 
        en = 1'b0;
        #50000 loadn = 1'b0;
        #50000 loadn = 1'b1;
        #50000 en = 1'b1;
        #150000;
        en = 1'b0;
        #50000; 
        clearn = 1'b0;
        #50000; 
        clearn = 1'b1;
        #50000; 
        en = 1'b1;
        #150000;
        clearn = 1'b0;
        #50000; 
        clearn = 1'b1;
        #50000; $finish;
    end    
endmodule