data/full_repos/permissive/524455192/src/user_module_339898704941023827_tb.v
1: b'%Error: data/full_repos/permissive/524455192/src/user_module_339898704941023827_tb.v:12: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("user_module_339898704941023827_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/524455192/src/user_module_339898704941023827_tb.v:13: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, user_module_339898704941023827_tb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/524455192/src/user_module_339898704941023827_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n   #100_000_000;  \n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/524455192/src/user_module_339898704941023827_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_HALF_PERIOD);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/524455192/src/user_module_339898704941023827_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_HALF_PERIOD);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/524455192/src/user_module_339898704941023827_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/524455192/src/user_module_339898704941023827_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n #(CLK_HALF_PERIOD);\n ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module user_module_339898704941023827_tb;

reg [7:0] io_in;
wire [7:0] io_out;

user_module_339898704941023827 UUT (.io_in(io_in), .io_out(io_out));

initial begin
  $dumpfile("user_module_339898704941023827_tb.vcd");
  $dumpvars(0, user_module_339898704941023827_tb);
end

initial begin
   #100_000_000;
   $display("Caught by trap");
   $finish;
 end

parameter CLK_HALF_PERIOD = 5;
always begin
  io_in[0] = 1'b1;
  #(CLK_HALF_PERIOD);
  io_in[0] = 1'b0;
  #(CLK_HALF_PERIOD);
end

initial 
begin
  #20
	io_in[1] = 1;
	#(CLK_HALF_PERIOD);
	io_in[1] = 0;
end

endmodule
module user_module_339898704941023827_tb;


reg [7:0] io_in;
wire [7:0] io_out;

user_module_339898704941023827 UUT (.io_in(io_in), .io_out(io_out));

initial begin
  $dumpfile("user_module_339898704941023827_tb.vcd");
  $dumpvars(0, user_module_339898704941023827_tb);
end

initial begin
   #100_000_000;
   $display("Caught by trap");
   $finish;
 end

parameter CLK_HALF_PERIOD = 5;
always begin
  io_in[0] = 1'b1;
  #(CLK_HALF_PERIOD);
  io_in[0] = 1'b0;
  #(CLK_HALF_PERIOD);
end

initial 
begin
  #20
	io_in[1] = 1;
	#(CLK_HALF_PERIOD);
	io_in[1] = 0;
end

endmodule