data/full_repos/permissive/465671848/Project_files/Top_design.v
1: b"%Error: data/full_repos/permissive/465671848/Project_files/Top_design.v:41: Cannot find file containing module: 'Bin_BCD'\nBin_BCD BCD(data_input , hundreds_out , tens_out, ones_out );\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/465671848/Project_files,data/full_repos/permissive/465671848/Bin_BCD\n             data/full_repos/permissive/465671848/Project_files,data/full_repos/permissive/465671848/Bin_BCD.v\n             data/full_repos/permissive/465671848/Project_files,data/full_repos/permissive/465671848/Bin_BCD.sv\n             Bin_BCD\n             Bin_BCD.v\n             Bin_BCD.sv\n             obj_dir/Bin_BCD\n             obj_dir/Bin_BCD.v\n             obj_dir/Bin_BCD.sv\n%Error: data/full_repos/permissive/465671848/Project_files/Top_design.v:42: Cannot find file containing module: 'slow_clkgen'\nslow_clkgen CLK_GEN(i_clk , clock_out);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/465671848/Project_files/Top_design.v:44: Cannot find file containing module: 'counter_2bit'\ncounter_2bit Counter( clock_out , count_out  );\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/465671848/Project_files/Top_design.v:45: Cannot find file containing module: 'decoder'\ndecoder DEC (count_out  , an);\n^~~~~~~\n%Error: data/full_repos/permissive/465671848/Project_files/Top_design.v:46: Cannot find file containing module: 'seven_seg_converter'\nseven_seg_converter SEV_SEG( mux_OUT , seg_OUT );\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/465671848/Project_files/Top_design.v:47: Cannot find file containing module: 'mux'\nmux MUX ( ones_out , tens_out , hundreds_out ,4'b0000 ,  count_out, mux_OUT);\n^~~\n%Error: Exiting due to 6 error(s)\n"
module Top_design(i_clk , data_input, an , seg_OUT);
input i_clk ;
input [`WIDTH_INPUT-1:0] data_input ;
output [2:0] an ;
output  [7:0] seg_OUT ;

wire [3:0] ones_out ;
wire [3:0] tens_out ;
wire [3:0] hundreds_out ;

wire [1:0] count_out ;


wire [3:0] mux_OUT ;

wire clock_out ;


Bin_BCD BCD(data_input , hundreds_out , tens_out, ones_out );
slow_clkgen CLK_GEN(i_clk , clock_out);

counter_2bit Counter( clock_out , count_out  );
decoder DEC (count_out  , an);
seven_seg_converter SEV_SEG( mux_OUT , seg_OUT );
mux MUX ( ones_out , tens_out , hundreds_out ,4'b0000 ,  count_out, mux_OUT);


endmodule
module Top_design(i_clk , data_input, an , seg_OUT);

input i_clk ;
input [`WIDTH_INPUT-1:0] data_input ;
output [2:0] an ;
output  [7:0] seg_OUT ;

wire [3:0] ones_out ;
wire [3:0] tens_out ;
wire [3:0] hundreds_out ;

wire [1:0] count_out ;


wire [3:0] mux_OUT ;

wire clock_out ;


Bin_BCD BCD(data_input , hundreds_out , tens_out, ones_out );
slow_clkgen CLK_GEN(i_clk , clock_out);

counter_2bit Counter( clock_out , count_out  );
decoder DEC (count_out  , an);
seven_seg_converter SEV_SEG( mux_OUT , seg_OUT );
mux MUX ( ones_out , tens_out , hundreds_out ,4'b0000 ,  count_out, mux_OUT);


endmodule