data/full_repos/permissive/466874195/verilog/rtl/calc_ck.v
data/verilator_xmls/3ce26dfd-d7a3-4bd6-a0f2-5d2a67b51d53.xml
module calc_ck #
(
    parameter SEQ_WIDTH = 8
)
(
    input  wire                     clk,
    input  wire                     rst,

    input  wire [SEQ_WIDTH-1:0]     a,
    input  wire [SEQ_WIDTH-1:0]     b,
    output reg  [7:0]               z
);

initial begin
    z = 0;
end

reg [7:0] temp;
integer i;
always @(posedge clk) begin
    if (rst) begin
        z <= 0;
    end else begin
        temp = 0;
        for (i = 0; i < SEQ_WIDTH; i++) begin
            if (a[i] == b[i]) begin
                temp = temp + 1;
            end else begin
                temp = temp - 1;
            end
        end

        z <= temp;
    end
end

endmodule
module calc_ck #
(
    parameter SEQ_WIDTH = 8
)
(
    input  wire                     clk,
    input  wire                     rst,

    input  wire [SEQ_WIDTH-1:0]     a,
    input  wire [SEQ_WIDTH-1:0]     b,
    output reg  [7:0]               z
);


initial begin
    z = 0;
end

reg [7:0] temp;
integer i;
always @(posedge clk) begin
    if (rst) begin
        z <= 0;
    end else begin
        temp = 0;
        for (i = 0; i < SEQ_WIDTH; i++) begin
            if (a[i] == b[i]) begin
                temp = temp + 1;
            end else begin
                temp = temp - 1;
            end
        end

        z <= temp;
    end
end

endmodule