data/full_repos/permissive/508331744/verilog/rtl/FA.v
1: b"%Error: data/full_repos/permissive/508331744/verilog/rtl/FA.v:12: Cannot find file containing module: 'HA'\n    HA half_adder_1 (x,y,c1,s1);\n    ^~\n        ... Looked in:\n             data/full_repos/permissive/508331744/verilog/rtl,data/full_repos/permissive/508331744/HA\n             data/full_repos/permissive/508331744/verilog/rtl,data/full_repos/permissive/508331744/HA.v\n             data/full_repos/permissive/508331744/verilog/rtl,data/full_repos/permissive/508331744/HA.sv\n             HA\n             HA.v\n             HA.sv\n             obj_dir/HA\n             obj_dir/HA.v\n             obj_dir/HA.sv\n%Error: data/full_repos/permissive/508331744/verilog/rtl/FA.v:13: Cannot find file containing module: 'HA'\n    HA half_adder_2 (ci,s1,c2,sum);\n    ^~\n%Error: Exiting due to 2 error(s)\n"
module FA(
    input x,y,ci,
    output cout, sum
    );
    (* dont_touch="true" *)

    wire c1,s1,c2;

    HA half_adder_1 (x,y,c1,s1);
    HA half_adder_2 (ci,s1,c2,sum);
    assign cout = c1 | c2;

endmodule
module FA(
    input x,y,ci,
    output cout, sum
    );

    (* dont_touch="true" *)

    wire c1,s1,c2;

    HA half_adder_1 (x,y,c1,s1);
    HA half_adder_2 (ci,s1,c2,sum);
    assign cout = c1 | c2;

endmodule