data/full_repos/permissive/494117590/hdl_src/design/load_bram_if.v
1: b"%Error: data/full_repos/permissive/494117590/hdl_src/design/load_bram_if.v:4: syntax error, unexpected ')', expecting '['\n) (\n^\n%Error: data/full_repos/permissive/494117590/hdl_src/design/load_bram_if.v:16: syntax error, unexpected always\n  always @(posedge clk ) begin\n  ^~~~~~\n%Error: data/full_repos/permissive/494117590/hdl_src/design/load_bram_if.v:34: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module load_bram_if #(
  parameter DATA_WIDTH = 18,
  parameter DATA_DEPTH = 1024,
) (
  output [clogb2(DATA_DEPTH-1)-1:0] o_addra,
  input  clka,
  input  rsta,
  input [DATA_WIDTH-1:0] i_bram_out
);




  reg [DATA_WIDTH-1:0] index_lookup [clogb2(DATA_DEPTH-1)-1:0][DATA_DEPTH-1:0];
  
  always @(posedge clk ) begin
    if (!rst_n) begin



    end else begin 


    end
  end


  function integer clogb2;
    input integer depth;
      for (clogb2=0; depth>0; clogb2=clogb2+1)
        depth = depth >> 1;
  endfunction

endmodule
module load_bram_if #(
  parameter DATA_WIDTH = 18,
  parameter DATA_DEPTH = 1024,
) (
  output [clogb2(DATA_DEPTH-1)-1:0] o_addra,
  input  clka,
  input  rsta,
  input [DATA_WIDTH-1:0] i_bram_out
);





  reg [DATA_WIDTH-1:0] index_lookup [clogb2(DATA_DEPTH-1)-1:0][DATA_DEPTH-1:0];
  
  always @(posedge clk ) begin
    if (!rst_n) begin



    end else begin 


    end
  end


  function integer clogb2;
    input integer depth;
      for (clogb2=0; depth>0; clogb2=clogb2+1)
        depth = depth >> 1;
  endfunction

endmodule