data/full_repos/permissive/499137621/CheckPoint4_CPU_Sub-main/clk_div_2.v
data/verilator_xmls/e2afa5af-59ea-4081-9717-9dc6546534e0.xml
module clk_div_2 ( clk ,rst,out_clk );
output reg out_clk;
input clk ;
input rst;
always @(posedge clk)
begin
if (~rst)
     out_clk <= 1'b0;
else
     out_clk <= ~out_clk;	
end
endmodule
module clk_div_2 ( clk ,rst,out_clk );

output reg out_clk;
input clk ;
input rst;
always @(posedge clk)
begin
if (~rst)
     out_clk <= 1'b0;
else
     out_clk <= ~out_clk;	
end
endmodule