data/full_repos/permissive/458134463/Modules/nextPC.v
data/verilator_xmls/b0fe8999-12ed-4cff-abbc-d120eb576178.xml
module nextPC(branch, branchAddress, NextPC, clock);

input branch, clock;
input [31:0] branchAddress;

output reg [31:0] NextPC;

initial begin
	NextPC = 32'h00000000;
end

always @ (posedge clock) begin
	if(branch)
		NextPC = NextPC + 1 + branchAddress;
	else 
		NextPC = NextPC + 1;
end

endmodule
module nextPC(branch, branchAddress, NextPC, clock);


input branch, clock;
input [31:0] branchAddress;

output reg [31:0] NextPC;

initial begin
	NextPC = 32'h00000000;
end

always @ (posedge clock) begin
	if(branch)
		NextPC = NextPC + 1 + branchAddress;
	else 
		NextPC = NextPC + 1;
end

endmodule