data/full_repos/permissive/466366448/verilogfiles/yt_pwm.v
1: b'%Warning-WIDTH: data/full_repos/permissive/466366448/verilogfiles/yt_pwm.v:11: Operator LT expects 32 or 13 bits on the LHS, but LHS\'s VARREF \'counter\' generates 8 bits.\n                                                                             : ... In instance yt_pwm\n if (counter < 5000) counter<= counter +1;  \n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module yt_pwm(
	input clk,
	output led
	);


reg [7:0] counter =0;
always @ (posedge clk) begin
	if (counter < 5000) counter<= counter +1;
	else counter <=0;
end



assign led = (counter<80) ? 1:0;
endmodule
module yt_pwm(
	input clk,
	output led
	);



reg [7:0] counter =0;
always @ (posedge clk) begin
	if (counter < 5000) counter<= counter +1;
	else counter <=0;
end



assign led = (counter<80) ? 1:0;
endmodule