data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/ATCKINV1.v
data/verilator_xmls/12cb902d-b61b-448e-a454-43b84d92bef4.xml
module ATCKINV1
    (
     A,
     Y
     );
input A;
output Y;
assign Y = ~A;

endmodule
module ATCKINV1
    (
     A,
     Y
     );

input A;
output Y;
assign Y = ~A;

endmodule