data/full_repos/permissive/441359809/src/yosys/tests/various/muxpack.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/tests/various/muxpack.v:10: Multiple top level modules\n                                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                            : ... Top module \'mux_if_unbal_4_1\'\nmodule mux_if_unbal_4_1 #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);\n       ^~~~~~~~~~~~~~~~\n                                                                                            : ... Top module \'mux_if_unbal_5_3\'\nmodule mux_if_unbal_5_3 #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);\n       ^~~~~~~~~~~~~~~~\n                                                                                            : ... Top module \'mux_if_unbal_5_3_invert\'\nmodule mux_if_unbal_5_3_invert #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);\n       ^~~~~~~~~~~~~~~~~~~~~~~\n                                                                                            : ... Top module \'mux_if_unbal_5_3_width_mismatch\'\nmodule mux_if_unbal_5_3_width_mismatch #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                            : ... Top module \'mux_if_unbal_4_1_missing\'\nmodule mux_if_unbal_4_1_missing #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);\n       ^~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                            : ... Top module \'mux_if_unbal_5_3_order\'\nmodule mux_if_unbal_5_3_order #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);\n       ^~~~~~~~~~~~~~~~~~~~~~\n                                                                                            : ... Top module \'mux_if_unbal_4_1_nonexcl\'\nmodule mux_if_unbal_4_1_nonexcl #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);\n       ^~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                            : ... Top module \'mux_if_unbal_5_3_nonexcl\'\nmodule mux_if_unbal_5_3_nonexcl #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);\n       ^~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                            : ... Top module \'mux_case_unbal_8_7\'\nmodule mux_case_unbal_8_7#(parameter N=8, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);\n       ^~~~~~~~~~~~~~~~~~\n                                                                                            : ... Top module \'mux_if_bal_8_2\'\nmodule mux_if_bal_8_2 #(parameter N=8, parameter W=2) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);\n       ^~~~~~~~~~~~~~\n                                                                                            : ... Top module \'mux_if_bal_5_1\'\nmodule mux_if_bal_5_1 #(parameter N=5, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);\n       ^~~~~~~~~~~~~~\n                                                                                            : ... Top module \'cliffordwolf_nonexclusive_select\'\nmodule cliffordwolf_nonexclusive_select (\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                            : ... Top module \'cliffordwolf_freduce\'\nmodule cliffordwolf_freduce (\n       ^~~~~~~~~~~~~~~~~~~~\n                                                                                            : ... Top module \'case_nonexclusive_select\'\nmodule case_nonexclusive_select (\n       ^~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                            : ... Top module \'case_nonoverlap\'\nmodule case_nonoverlap (\n       ^~~~~~~~~~~~~~~\n                                                                                            : ... Top module \'case_overlap\'\nmodule case_overlap (\n       ^~~~~~~~~~~~\n                                                                                            : ... Top module \'case_overlap2\'\nmodule case_overlap2 (\n       ^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/muxpack.v:177: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 3 bits.\n                                                                                          : ... In instance cliffordwolf_freduce\n                if (s == 0) o = {3{b}};\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/muxpack.v:178: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n                                                                                          : ... In instance cliffordwolf_freduce\n                if (s == 1) o = {2{c}};\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/muxpack.v:179: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'d\' generates 1 bits.\n                                                                                          : ... In instance cliffordwolf_freduce\n                if (s == 2) o = d;\n                              ^\n%Error: Exiting due to 4 warning(s)\n'
module mux_if_unbal_5_3_nonexcl #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @* begin
    o <= {W{1'bx}};
    if (s == 0) o <= i[0*W+:W];
    if (s == 1) o <= i[1*W+:W];
    if (s == 2) o <= i[2*W+:W];
    if (s == 3) o <= i[3*W+:W];
    if (s == 4) o <= i[4*W+:W];
	if (s == 0) o <= i[2*W+:W];
end
endmodule
module mux_if_unbal_5_3_nonexcl #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);

always @* begin
    o <= {W{1'bx}};
    if (s == 0) o <= i[0*W+:W];
    if (s == 1) o <= i[1*W+:W];
    if (s == 2) o <= i[2*W+:W];
    if (s == 3) o <= i[3*W+:W];
    if (s == 4) o <= i[4*W+:W];
	if (s == 0) o <= i[2*W+:W];
end
endmodule