data/full_repos/permissive/450205124/Assignment3/Q1-sequence-detector/A3Q1_sequence_detector_unit.v
1: b'%Error: data/full_repos/permissive/450205124/Assignment3/Q1-sequence-detector/A3Q1_sequence_detector_unit.v:1: Cannot find include file: A3Q1_d_flip_flop.v\n`include "A3Q1_d_flip_flop.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/450205124/Assignment3/Q1-sequence-detector,data/full_repos/permissive/450205124/A3Q1_d_flip_flop.v\n             data/full_repos/permissive/450205124/Assignment3/Q1-sequence-detector,data/full_repos/permissive/450205124/A3Q1_d_flip_flop.v.v\n             data/full_repos/permissive/450205124/Assignment3/Q1-sequence-detector,data/full_repos/permissive/450205124/A3Q1_d_flip_flop.v.sv\n             A3Q1_d_flip_flop.v\n             A3Q1_d_flip_flop.v.v\n             A3Q1_d_flip_flop.v.sv\n             obj_dir/A3Q1_d_flip_flop.v\n             obj_dir/A3Q1_d_flip_flop.v.v\n             obj_dir/A3Q1_d_flip_flop.v.sv\n%Error: Exiting due to 1 error(s)\n'
module sequence_detector_unit(out,inp,clk,reset);
  output out;
  input inp;
  input clk;
  input reset;

  wire[2:0] k;
  d_flip_flop D1(k[0],inp,clk,reset);
  d_flip_flop D2(k[1],k[0],clk,reset);
  d_flip_flop D3(k[2],k[1],clk,reset);
  assign out = ~inp & k[0] &~k[1]&k[2];
endmodule
module sequence_detector_unit(out,inp,clk,reset);

  output out;
  input inp;
  input clk;
  input reset;

  wire[2:0] k;
  d_flip_flop D1(k[0],inp,clk,reset);
  d_flip_flop D2(k[1],k[0],clk,reset);
  d_flip_flop D3(k[2],k[1],clk,reset);
  assign out = ~inp & k[0] &~k[1]&k[2];
endmodule