data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/register_interface/src/axi_to_reg.sv
1: b'%Warning-MULTITOP: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/register_interface/src/axi_to_reg.sv:26: Multiple top level modules\n                                                                                                                                                : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                                                                : ... Top module \'axi_to_reg\'\nmodule axi_to_reg #(\n       ^~~~~~~~~~\n                                                                                                                                                : ... Top module \'AXI_BUS\'\n  AXI_BUS.in   in        ,\n  ^~~~~~~\n                                                                                                                                                : ... Top module \'REG_BUS\'\n  REG_BUS.out  reg_o\n  ^~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/register_interface/src/axi_to_reg.sv:26: Unsupported: Interfaced port on top level module\n  AXI_BUS.in   in        ,\n               ^~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/register_interface/src/axi_to_reg.sv:27: Unsupported: Interfaced port on top level module\n  REG_BUS.out  reg_o\n               ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/register_interface/src/axi_to_reg.sv:26: Cannot find file containing interface: \'AXI_BUS\'\n  AXI_BUS.in   in        ,\n  ^~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/register_interface/src/axi_to_reg.sv:27: Cannot find file containing interface: \'REG_BUS\'\n  REG_BUS.out  reg_o\n  ^~~~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n'
module axi_to_reg #(

  parameter int ADDR_WIDTH = -1,

  parameter int DATA_WIDTH = -1,


  parameter bit DECOUPLE_W = 1
)(
  input  logic clk_i     ,
  input  logic rst_ni    ,
  input  logic testmode_i,
  AXI_BUS.in   in        ,
  REG_BUS.out  reg_o
);

  AXI_LITE_BUS #(
    .AXI_ADDR_WIDTH ( ADDR_WIDTH ),
    .AXI_DATA_WIDTH ( DATA_WIDTH )
  ) axi_lite (clk_i);


  axi_to_axi_lite #(

    .NUM_PENDING_RD (1),

    .NUM_PENDING_WR (1)
  ) i_axi_to_axi_lite (
    .clk_i,
    .rst_ni,
    .testmode_i,
    .in,
    .out ( axi_lite )
  );

  axi_lite_to_reg #(

    .ADDR_WIDTH ( ADDR_WIDTH ),

    .DATA_WIDTH ( DATA_WIDTH ),


    .DECOUPLE_W ( DECOUPLE_W )
  ) i_axi_lite_to_reg (
    .clk_i,
    .rst_ni,
    .axi_i ( axi_lite ),
    .reg_o
  );

endmodule
module axi_to_reg #(

  parameter int ADDR_WIDTH = -1,

  parameter int DATA_WIDTH = -1,


  parameter bit DECOUPLE_W = 1
)(
  input  logic clk_i     ,
  input  logic rst_ni    ,
  input  logic testmode_i,
  AXI_BUS.in   in        ,
  REG_BUS.out  reg_o
);


  AXI_LITE_BUS #(
    .AXI_ADDR_WIDTH ( ADDR_WIDTH ),
    .AXI_DATA_WIDTH ( DATA_WIDTH )
  ) axi_lite (clk_i);


  axi_to_axi_lite #(

    .NUM_PENDING_RD (1),

    .NUM_PENDING_WR (1)
  ) i_axi_to_axi_lite (
    .clk_i,
    .rst_ni,
    .testmode_i,
    .in,
    .out ( axi_lite )
  );

  axi_lite_to_reg #(

    .ADDR_WIDTH ( ADDR_WIDTH ),

    .DATA_WIDTH ( DATA_WIDTH ),


    .DECOUPLE_W ( DECOUPLE_W )
  ) i_axi_lite_to_reg (
    .clk_i,
    .rst_ni,
    .axi_i ( axi_lite ),
    .reg_o
  );

endmodule