data/full_repos/permissive/519831524/iiitb_cps_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/519831524/iiitb_cps_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n forever #10 clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/519831524/iiitb_cps_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/519831524/iiitb_cps_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/519831524/iiitb_cps_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/519831524/iiitb_cps_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n #2000;\n ^\n%Error: data/full_repos/permissive/519831524/iiitb_cps_tb.v:61: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("dump.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/519831524/iiitb_cps_tb.v:62: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0,iiitb_cps_tb);\n      ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module iiitb_cps_tb;


  reg clk;
  reg reset_n;
  reg sensor_entrance;
  reg sensor_exit;
  reg [1:0] password_1;
  reg [1:0] password_2;


  wire GREEN_LED;
  wire RED_LED;
  wire [6:0] HEX_1;
  wire [6:0] HEX_2;


  iiitb_cps uut (
  .clk(clk), 
  .reset_n(reset_n), 
  .sensor_entrance(sensor_entrance), 
  .sensor_exit(sensor_exit), 
  .password_1(password_1), 
  .password_2(password_2), 
  .GREEN_LED(GREEN_LED), 
  .RED_LED(RED_LED), 
  .HEX_1(HEX_1), 
 .HEX_2(HEX_2)
 );
 initial begin
 clk = 0;
 forever #10 clk = ~clk;
 end
 initial begin

 reset_n = 0;
 sensor_entrance = 0;
 sensor_exit = 0;
 password_1 = 0;
 password_2 = 0;

 #100;
      reset_n = 1;
 #20;
 sensor_entrance = 1;
 #1000;
 sensor_entrance = 0;
 password_1 = 1;
 password_2 = 2;
 #2000;
 sensor_exit =1;
 


 end
  initial
    begin
      $dumpfile("dump.vcd");
      $dumpvars(0,iiitb_cps_tb);
    end
  
      
endmodule
module iiitb_cps_tb;



  reg clk;
  reg reset_n;
  reg sensor_entrance;
  reg sensor_exit;
  reg [1:0] password_1;
  reg [1:0] password_2;


  wire GREEN_LED;
  wire RED_LED;
  wire [6:0] HEX_1;
  wire [6:0] HEX_2;


  iiitb_cps uut (
  .clk(clk), 
  .reset_n(reset_n), 
  .sensor_entrance(sensor_entrance), 
  .sensor_exit(sensor_exit), 
  .password_1(password_1), 
  .password_2(password_2), 
  .GREEN_LED(GREEN_LED), 
  .RED_LED(RED_LED), 
  .HEX_1(HEX_1), 
 .HEX_2(HEX_2)
 );
 initial begin
 clk = 0;
 forever #10 clk = ~clk;
 end
 initial begin

 reset_n = 0;
 sensor_entrance = 0;
 sensor_exit = 0;
 password_1 = 0;
 password_2 = 0;

 #100;
      reset_n = 1;
 #20;
 sensor_entrance = 1;
 #1000;
 sensor_entrance = 0;
 password_1 = 1;
 password_2 = 2;
 #2000;
 sensor_exit =1;
 


 end
  initial
    begin
      $dumpfile("dump.vcd");
      $dumpvars(0,iiitb_cps_tb);
    end
  
      
endmodule