data/full_repos/permissive/504478691/FFT/fft.v
1: b'%Error: data/full_repos/permissive/504478691/FFT/fft.v:1: Cannot find include file: top.vh\n`include "top.vh" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/504478691/FFT,data/full_repos/permissive/504478691/top.vh\n             data/full_repos/permissive/504478691/FFT,data/full_repos/permissive/504478691/top.vh.v\n             data/full_repos/permissive/504478691/FFT,data/full_repos/permissive/504478691/top.vh.sv\n             top.vh\n             top.vh.v\n             top.vh.sv\n             obj_dir/top.vh\n             obj_dir/top.vh.v\n             obj_dir/top.vh.sv\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:5: Define or directive not defined: \'`logN\'\ninput [`logN-1:0] addr;\n       ^~~~~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:6: Define or directive not defined: \'`CW\'\ninput [`CW-1:0] din;\n       ^~~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:7: Define or directive not defined: \'`CW\'\noutput [`CW-1:0] dout;\n        ^~~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:11: Define or directive not defined: \'`logS\'\nreg [`logS-1:0] stage;\n     ^~~~~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:12: Define or directive not defined: \'`logN\'\nwire [`logN-1:0] addr_rev;\n      ^~~~~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:13: Define or directive not defined: \'`logN\'\nwire [`logN-1:0] addr_phy;\n      ^~~~~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:14: Define or directive not defined: \'`logN\'\nreg [`logN-1:0] rnd;  \n     ^~~~~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:15: Define or directive not defined: \'`logNpM\'\nreg [`logNpM-2:0] iter;\n     ^~~~~~~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:16: Define or directive not defined: \'`logCyc\'\nreg [`logCyc-1:0] cycle;\n     ^~~~~~~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:19: Define or directive not defined: \'`logNpM\'\nreg [`logNpM-1:0] addra_calc[0:`M], addrb_calc[0:`M];  \n     ^~~~~~~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:19: Define or directive not defined: \'`M\'\nreg [`logNpM-1:0] addra_calc[0:`M], addrb_calc[0:`M];  \n                               ^~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:19: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg [`logNpM-1:0] addra_calc[0:`M], addrb_calc[0:`M];  \n                                 ^\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:19: Define or directive not defined: \'`M\'\nreg [`logNpM-1:0] addra_calc[0:`M], addrb_calc[0:`M];  \n                                                 ^~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:20: Define or directive not defined: \'`logM\'\nwire [`logM-1:0] grpa[0:`M], grpb[0:`M];  \n      ^~~~~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:20: Define or directive not defined: \'`M\'\nwire [`logM-1:0] grpa[0:`M], grpb[0:`M];  \n                        ^~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:20: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [`logM-1:0] grpa[0:`M], grpb[0:`M];  \n                          ^\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:20: Define or directive not defined: \'`M\'\nwire [`logM-1:0] grpa[0:`M], grpb[0:`M];  \n                                    ^~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:21: Define or directive not defined: \'`logNpM\'\nwire [`logNpM-1:0] idxa[0:`M], idxb[0:`M];  \n      ^~~~~~~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:21: Define or directive not defined: \'`M\'\nwire [`logNpM-1:0] idxa[0:`M], idxb[0:`M];  \n                          ^~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:21: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [`logNpM-1:0] idxa[0:`M], idxb[0:`M];  \n                            ^\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:21: Define or directive not defined: \'`M\'\nwire [`logNpM-1:0] idxa[0:`M], idxb[0:`M];  \n                                      ^~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:22: Define or directive not defined: \'`CW\'\nreg [`CW-1:0] dina_calc[0:`M], dinb_calc[0:`M];  \n     ^~~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:22: Define or directive not defined: \'`M\'\nreg [`CW-1:0] dina_calc[0:`M], dinb_calc[0:`M];  \n                          ^~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:22: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg [`CW-1:0] dina_calc[0:`M], dinb_calc[0:`M];  \n                            ^\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:22: Define or directive not defined: \'`M\'\nreg [`CW-1:0] dina_calc[0:`M], dinb_calc[0:`M];  \n                                           ^~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:23: Define or directive not defined: \'`CW\'\nwire [`CW-1:0] douta_calc[0:`M], doutb_calc[0:`M];  \n      ^~~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:23: Define or directive not defined: \'`M\'\nwire [`CW-1:0] douta_calc[0:`M], doutb_calc[0:`M];  \n                            ^~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:23: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [`CW-1:0] douta_calc[0:`M], doutb_calc[0:`M];  \n                              ^\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:23: Define or directive not defined: \'`M\'\nwire [`CW-1:0] douta_calc[0:`M], doutb_calc[0:`M];  \n                                              ^~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:24: Define or directive not defined: \'`CW\'\nreg [`CW-1:0] opa[0:`M], opb[0:`M];  \n     ^~~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:24: Define or directive not defined: \'`M\'\nreg [`CW-1:0] opa[0:`M], opb[0:`M];  \n                    ^~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:24: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg [`CW-1:0] opa[0:`M], opb[0:`M];  \n                      ^\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:24: Define or directive not defined: \'`M\'\nreg [`CW-1:0] opa[0:`M], opb[0:`M];  \n                               ^~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:25: Define or directive not defined: \'`CW\'\nwire [`CW-1:0] opc[0:`M], opd[0:`M];  \n      ^~~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:25: Define or directive not defined: \'`M\'\nwire [`CW-1:0] opc[0:`M], opd[0:`M];  \n                     ^~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:25: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [`CW-1:0] opc[0:`M], opd[0:`M];  \n                       ^\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:25: Define or directive not defined: \'`M\'\nwire [`CW-1:0] opc[0:`M], opd[0:`M];  \n                                ^~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:26: Define or directive not defined: \'`logM\'\nreg [`logM:0] k;  \n     ^~~~~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:26: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nreg [`logM:0] k;  \n          ^\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:31: Define or directive not defined: \'`logCyc\'\nassign we_calc = cycle == `logCyc\'d4 | cycle == `logCyc\'d5;\n                          ^~~~~~~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:31: Define or directive not defined: \'`logCyc\'\nassign we_calc = cycle == `logCyc\'d4 | cycle == `logCyc\'d5;\n                                                ^~~~~~~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:32: Define or directive not defined: \'`M\'\nfor (igen = 0; igen < `M; igen = igen + 1) begin : mem_units  \n                      ^~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:32: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nfor (igen = 0; igen < `M; igen = igen + 1) begin : mem_units  \n                        ^\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:34: Define or directive not defined: \'`logNpM\'\n    wire [`logNpM-1:0] addra, addrb;  \n          ^~~~~~~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:35: Define or directive not defined: \'`CW\'\n    wire [`CW-1:0] dina, dinb, douta, doutb;  \n          ^~~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:37: Define or directive not defined: \'`logNpM\'\n        .wea(wea), .addra({`logNpM\'d0, addra}), .dina(`r(dina)), .douta(`r(douta)), .clka(clk),\n                           ^~~~~~~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:37: Define or directive not defined: \'`r\'\n        .wea(wea), .addra({`logNpM\'d0, addra}), .dina(`r(dina)), .douta(`r(douta)), .clka(clk),\n                                                      ^~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:37: Define or directive not defined: \'`r\'\n        .wea(wea), .addra({`logNpM\'d0, addra}), .dina(`r(dina)), .douta(`r(douta)), .clka(clk),\n                                                                        ^~\n%Error: data/full_repos/permissive/504478691/FFT/fft.v:38: Define or directive not defined: \'`logNpM\'\n        .web(web), .addrb({`logNpM\'d0, addrb}), .dinb(`r(dinb)), .doutb(`r(doutb)), .clkb(clk));  \n                           ^~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module fft(clk, rst, sig, we, rev, addr, din, dout);
input clk, rst, sig;
input we, rev;
input [`logN-1:0] addr;
input [`CW-1:0] din;
output [`CW-1:0] dout;

reg busy, finish;
wire clk_run;
reg [`logS-1:0] stage;
wire [`logN-1:0] addr_rev;
wire [`logN-1:0] addr_phy;
reg [`logN-1:0] rnd;
reg [`logNpM-2:0] iter;
reg [`logCyc-1:0] cycle;
genvar igen;
wire we_calc;
reg [`logNpM-1:0] addra_calc[0:`M], addrb_calc[0:`M];
wire [`logM-1:0] grpa[0:`M], grpb[0:`M];
wire [`logNpM-1:0] idxa[0:`M], idxb[0:`M];
reg [`CW-1:0] dina_calc[0:`M], dinb_calc[0:`M];
wire [`CW-1:0] douta_calc[0:`M], doutb_calc[0:`M];
reg [`CW-1:0] opa[0:`M], opb[0:`M];
wire [`CW-1:0] opc[0:`M], opd[0:`M];
reg [`logM:0] k;

bit_reverse inst_rev(addr, addr_rev);
assign clk_run = clk & busy;
assign addr_phy = rev ? addr_rev : addr;
assign we_calc = cycle == `logCyc'd4 | cycle == `logCyc'd5;
for (igen = 0; igen < `M; igen = igen + 1) begin : mem_units
    wire wea, web;
    wire [`logNpM-1:0] addra, addrb;
    wire [`CW-1:0] dina, dinb, douta, doutb;
    bram_data inst_data_r(
        .wea(wea), .addra({`logNpM'd0, addra}), .dina(`r(dina)), .douta(`r(douta)), .clka(clk),
        .web(web), .addrb({`logNpM'd0, addrb}), .dinb(`r(dinb)), .doutb(`r(doutb)), .clkb(clk));
    bram_data inst_data_i(
        .wea(wea), .addra({`logNpM'd0, addra}), .dina(`i(dina)), .douta(`i(douta)), .clka(clk),
        .web(web), .addrb({`logNpM'd0, addrb}), .dinb(`i(dinb)), .doutb(`i(doutb)), .clkb(clk));
    assign wea   = busy ? (stage == `logS'd1 ? we_calc : 1'd0) : (igen == addr_phy[`logN-1:`logNpM]) & we;
    assign web   = busy ? (stage == `logS'd1 ? we_calc : 1'd0) : 1'd0;
    assign addra = busy ? (stage == `logS'd1 ? addra_calc[igen] : `logNpM'dz) : addr_phy[`logNpM-1:0];
    assign addrb = busy ? (stage == `logS'd1 ? addrb_calc[igen] : `logNpM'dz) : `logNpM'dz;
    assign dina  = busy ? (stage == `logS'd1 ? dina_calc[igen] : `CW'dz) : din;
    assign dinb  = busy ? (stage == `logS'd1 ? dinb_calc[igen] : `CW'dz) : `CW'dz;
    assign dout  = igen == addr_phy[`logN-1:`logNpM] ? douta : `CW'dz;
    assign douta_calc[igen] = douta;
    assign doutb_calc[igen] = doutb;
end
for (igen = 0; igen < `M; igen = igen + 1) begin : op_units
    wire [`CW-1:0] w;
    wire [`logN-1:0] addra, addrb;
    wire [`logN-2:0] omega;
    wire [`logN-1:0] addr_op;
    fft_op_unit op(`r(opa[igen]), `i(opa[igen]), `r(opb[igen]), `i(opb[igen]),
        `r(opc[igen]), `i(opc[igen]), `r(opd[igen]), `i(opd[igen]), `r(w), `i(w));
    brom_cos4096 inst_cos(.addra({`logNpM'd0, omega}), .clka(clk_run), .douta(`r(w)));
    brom_sin4096 inst_sin(.addra({`logNpM'd0, omega}), .clka(clk_run), .douta(`i(w)));
    assign addr_op = rnd > `logNpM ?
        {igen[`logM-1:0], igen[`logM-1:0] & (`logM'd1 << (rnd - 1 - `logNpM)) ? 1'd1 : 1'd0, iter} :
        {igen[`logM-1:0], iter, 1'd0} & (~`logN'd0 << (rnd - 1)) | iter & ~(~`logN'd0 << (rnd - 1));
    assign addra = addr_op & ~(`logN'd1 << (rnd - 1));
    assign addrb = addr_op | (`logN'd1 << (rnd - 1));
    assign grpa[igen] = addra[`logN-1:`logNpM];
    assign grpb[igen] = addrb[`logN-1:`logNpM];
    assign idxa[igen] = addra[`logNpM-1:0];
    assign idxb[igen] = addrb[`logNpM-1:0];
    assign omega = addra << (`logN - rnd);
end

always @(posedge clk)
begin
    if (rst | ~busy) begin
        stage <= `logS'd0;
        finish <= 1'd0;
    end
    else case (stage)
        `logS'd0: begin
            rnd <= `logN'd1;
            iter <= `logNpM'd0;
            cycle <= 1'd0;
            stage <= `logS'd1;
            finish <= 1'd0;
        end
        `logS'd1: begin
            if (cycle == `logCyc'd0) begin
                for (k = 0; k < `M; k = k + 1) begin
                    if (grpa[k] == k)
                        addra_calc[grpa[k]] <= idxa[k];
                    else addrb_calc[grpa[k]] <= idxa[k];
                    if (grpb[k] == k)
                        addrb_calc[grpb[k]] <= idxb[k];
                    else addra_calc[grpb[k]] <= idxb[k];
                end
                cycle <= 1;
            end else if (cycle == `logCyc'd2) begin
                for (k = 0; k < `M; k = k + 1) begin
                    if (grpa[k] == k)
                        opa[k] <= douta_calc[grpa[k]];
                    else opa[k] <= doutb_calc[grpa[k]];
                    if (grpb[k] == k)
                        opb[k] <= doutb_calc[grpb[k]];
                    else opb[k] <= douta_calc[grpb[k]];
                end
                cycle <= 3;
            end else if (cycle == `logCyc'd3) begin
                for (k = 0; k < `M; k = k + 1) begin
                    if (grpa[k] == k)
                        dina_calc[grpa[k]] <= opc[k];
                    else dinb_calc[grpa[k]] <= opc[k];
                    if (grpb[k] == k)
                        dinb_calc[grpb[k]] <= opd[k];
                    else dina_calc[grpb[k]] <= opd[k];
                end
                cycle <= 4;
            end else if (cycle == `logCyc'd5) begin
                if ({1'd1, iter} == ~`logNpM'd0) begin
                    if (rnd == `logN) begin
                        finish <= 1'd1;
                        stage <= `logS'd0;
                    end
                    rnd <= rnd + 1;
                end
                iter <= iter + 1;
                cycle <= 1'd0;
            end else cycle <= cycle + 1;
        end
        default: begin
            stage <= `logS'd0;
        end
    endcase
end

always @(posedge sig or posedge rst or posedge finish)
    busy <= rst ? 1'd0 : (finish ? 1'd0 : 1'd1);
endmodule
module fft(clk, rst, sig, we, rev, addr, din, dout);

input clk, rst, sig;
input we, rev;
input [`logN-1:0] addr;
input [`CW-1:0] din;
output [`CW-1:0] dout;

reg busy, finish;
wire clk_run;
reg [`logS-1:0] stage;
wire [`logN-1:0] addr_rev;
wire [`logN-1:0] addr_phy;
reg [`logN-1:0] rnd;
reg [`logNpM-2:0] iter;
reg [`logCyc-1:0] cycle;
genvar igen;
wire we_calc;
reg [`logNpM-1:0] addra_calc[0:`M], addrb_calc[0:`M];
wire [`logM-1:0] grpa[0:`M], grpb[0:`M];
wire [`logNpM-1:0] idxa[0:`M], idxb[0:`M];
reg [`CW-1:0] dina_calc[0:`M], dinb_calc[0:`M];
wire [`CW-1:0] douta_calc[0:`M], doutb_calc[0:`M];
reg [`CW-1:0] opa[0:`M], opb[0:`M];
wire [`CW-1:0] opc[0:`M], opd[0:`M];
reg [`logM:0] k;

bit_reverse inst_rev(addr, addr_rev);
assign clk_run = clk & busy;
assign addr_phy = rev ? addr_rev : addr;
assign we_calc = cycle == `logCyc'd4 | cycle == `logCyc'd5;
for (igen = 0; igen < `M; igen = igen + 1) begin : mem_units
    wire wea, web;
    wire [`logNpM-1:0] addra, addrb;
    wire [`CW-1:0] dina, dinb, douta, doutb;
    bram_data inst_data_r(
        .wea(wea), .addra({`logNpM'd0, addra}), .dina(`r(dina)), .douta(`r(douta)), .clka(clk),
        .web(web), .addrb({`logNpM'd0, addrb}), .dinb(`r(dinb)), .doutb(`r(doutb)), .clkb(clk));
    bram_data inst_data_i(
        .wea(wea), .addra({`logNpM'd0, addra}), .dina(`i(dina)), .douta(`i(douta)), .clka(clk),
        .web(web), .addrb({`logNpM'd0, addrb}), .dinb(`i(dinb)), .doutb(`i(doutb)), .clkb(clk));
    assign wea   = busy ? (stage == `logS'd1 ? we_calc : 1'd0) : (igen == addr_phy[`logN-1:`logNpM]) & we;
    assign web   = busy ? (stage == `logS'd1 ? we_calc : 1'd0) : 1'd0;
    assign addra = busy ? (stage == `logS'd1 ? addra_calc[igen] : `logNpM'dz) : addr_phy[`logNpM-1:0];
    assign addrb = busy ? (stage == `logS'd1 ? addrb_calc[igen] : `logNpM'dz) : `logNpM'dz;
    assign dina  = busy ? (stage == `logS'd1 ? dina_calc[igen] : `CW'dz) : din;
    assign dinb  = busy ? (stage == `logS'd1 ? dinb_calc[igen] : `CW'dz) : `CW'dz;
    assign dout  = igen == addr_phy[`logN-1:`logNpM] ? douta : `CW'dz;
    assign douta_calc[igen] = douta;
    assign doutb_calc[igen] = doutb;
end
for (igen = 0; igen < `M; igen = igen + 1) begin : op_units
    wire [`CW-1:0] w;
    wire [`logN-1:0] addra, addrb;
    wire [`logN-2:0] omega;
    wire [`logN-1:0] addr_op;
    fft_op_unit op(`r(opa[igen]), `i(opa[igen]), `r(opb[igen]), `i(opb[igen]),
        `r(opc[igen]), `i(opc[igen]), `r(opd[igen]), `i(opd[igen]), `r(w), `i(w));
    brom_cos4096 inst_cos(.addra({`logNpM'd0, omega}), .clka(clk_run), .douta(`r(w)));
    brom_sin4096 inst_sin(.addra({`logNpM'd0, omega}), .clka(clk_run), .douta(`i(w)));
    assign addr_op = rnd > `logNpM ?
        {igen[`logM-1:0], igen[`logM-1:0] & (`logM'd1 << (rnd - 1 - `logNpM)) ? 1'd1 : 1'd0, iter} :
        {igen[`logM-1:0], iter, 1'd0} & (~`logN'd0 << (rnd - 1)) | iter & ~(~`logN'd0 << (rnd - 1));
    assign addra = addr_op & ~(`logN'd1 << (rnd - 1));
    assign addrb = addr_op | (`logN'd1 << (rnd - 1));
    assign grpa[igen] = addra[`logN-1:`logNpM];
    assign grpb[igen] = addrb[`logN-1:`logNpM];
    assign idxa[igen] = addra[`logNpM-1:0];
    assign idxb[igen] = addrb[`logNpM-1:0];
    assign omega = addra << (`logN - rnd);
end

always @(posedge clk)
begin
    if (rst | ~busy) begin
        stage <= `logS'd0;
        finish <= 1'd0;
    end
    else case (stage)
        `logS'd0: begin
            rnd <= `logN'd1;
            iter <= `logNpM'd0;
            cycle <= 1'd0;
            stage <= `logS'd1;
            finish <= 1'd0;
        end
        `logS'd1: begin
            if (cycle == `logCyc'd0) begin
                for (k = 0; k < `M; k = k + 1) begin
                    if (grpa[k] == k)
                        addra_calc[grpa[k]] <= idxa[k];
                    else addrb_calc[grpa[k]] <= idxa[k];
                    if (grpb[k] == k)
                        addrb_calc[grpb[k]] <= idxb[k];
                    else addra_calc[grpb[k]] <= idxb[k];
                end
                cycle <= 1;
            end else if (cycle == `logCyc'd2) begin
                for (k = 0; k < `M; k = k + 1) begin
                    if (grpa[k] == k)
                        opa[k] <= douta_calc[grpa[k]];
                    else opa[k] <= doutb_calc[grpa[k]];
                    if (grpb[k] == k)
                        opb[k] <= doutb_calc[grpb[k]];
                    else opb[k] <= douta_calc[grpb[k]];
                end
                cycle <= 3;
            end else if (cycle == `logCyc'd3) begin
                for (k = 0; k < `M; k = k + 1) begin
                    if (grpa[k] == k)
                        dina_calc[grpa[k]] <= opc[k];
                    else dinb_calc[grpa[k]] <= opc[k];
                    if (grpb[k] == k)
                        dinb_calc[grpb[k]] <= opd[k];
                    else dina_calc[grpb[k]] <= opd[k];
                end
                cycle <= 4;
            end else if (cycle == `logCyc'd5) begin
                if ({1'd1, iter} == ~`logNpM'd0) begin
                    if (rnd == `logN) begin
                        finish <= 1'd1;
                        stage <= `logS'd0;
                    end
                    rnd <= rnd + 1;
                end
                iter <= iter + 1;
                cycle <= 1'd0;
            end else cycle <= cycle + 1;
        end
        default: begin
            stage <= `logS'd0;
        end
    endcase
end

always @(posedge sig or posedge rst or posedge finish)
    busy <= rst ? 1'd0 : (finish ? 1'd0 : 1'd1);
endmodule