data/full_repos/permissive/455421905/src/hms.v
1: b'%Warning-WIDTH: data/full_repos/permissive/455421905/src/hms.v:490: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'FLOAT\' generates 16 bits.\n                                                                  : ... In instance MERGE_TREE.level[0].nodes[1].merge_node.merge_logic\n      if (FLOAT == "yes" || SIGNED == "yes") begin\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/455421905/src/hms.v:490: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'SIGNED\' generates 16 bits.\n                                                                  : ... In instance MERGE_TREE.level[0].nodes[1].merge_node.merge_logic\n      if (FLOAT == "yes" || SIGNED == "yes") begin\n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/455421905/src/hms.v:342: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'FLOAT\' generates 16 bits.\n                                                                  : ... In instance MERGE_TREE.level[0].nodes[1].merge_node.merge_logic.merge_network\n      if (FLOAT == "yes" || SIGNED == "yes") begin\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/455421905/src/hms.v:342: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'SIGNED\' generates 16 bits.\n                                                                  : ... In instance MERGE_TREE.level[0].nodes[1].merge_node.merge_logic.merge_network\n      if (FLOAT == "yes" || SIGNED == "yes") begin\n                                   ^~\n%Error: data/full_repos/permissive/455421905/src/hms.v:80: Cannot find file containing module: \'COMPARATOR\'\n  COMPARATOR #(FLOAT, SIGNED, KEYW)\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/COMPARATOR\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/COMPARATOR.v\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/COMPARATOR.sv\n             COMPARATOR\n             COMPARATOR.v\n             COMPARATOR.sv\n             obj_dir/COMPARATOR\n             obj_dir/COMPARATOR.v\n             obj_dir/COMPARATOR.sv\n%Error: data/full_repos/permissive/455421905/src/hms.v:564: Cannot find file containing module: \'BS_FIFO\'\n  BS_FIFO #(5, (DATW<<E_LOG), USE_IPCORE)\n  ^~~~~~~\n%Error: data/full_repos/permissive/455421905/src/hms.v:567: Cannot find file containing module: \'BS_FIFO\'\n  BS_FIFO #(5, (DATW<<E_LOG), USE_IPCORE)\n  ^~~~~~~\n%Error: data/full_repos/permissive/455421905/src/hms.v:606: Cannot find file containing module: \'COMPARATOR\'\n      COMPARATOR #(FLOAT, SIGNED, KEYW)\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/455421905/src/hms.v:673: Cannot find file containing module: \'BS_FIFO\'\n  BS_FIFO #(FIFO_SIZE, (DATW<<E_LOG), USE_IPCORE)\n  ^~~~~~~\n%Error: Exiting due to 5 error(s), 4 warning(s)\n'
module COUPLER #(parameter                           E_LOG = 2,
                 parameter                           DATW  = 64)
                (input  wire                         CLK,
                 input  wire                         RST,
                 input  wire                         IN_FULL,
                 input  wire [(DATW<<(E_LOG-1))-1:0] DIN,
                 input  wire                         DINEN,
                 output wire [(DATW<<E_LOG)-1:0]     DOT,
                 output wire                         DOTEN);


  reg stall;
  always @(posedge CLK) stall <= IN_FULL;

  reg [(DATW<<E_LOG)-1:0] record_buf;
  reg                     record_buf_cnt;
  reg                     record_buf_en;

  always @(posedge CLK) begin
    if (DINEN) record_buf <= {DIN, record_buf[(DATW<<E_LOG)-1:(DATW<<(E_LOG-1))]};
  end
  always @(posedge CLK) begin
    if      (RST)   record_buf_cnt <= 0;
    else if (DINEN) record_buf_cnt <= ~record_buf_cnt;
  end
  always @(posedge CLK) begin
    if      (RST)    record_buf_en <= 0;
    else if (!stall) record_buf_en <= &{DINEN, record_buf_cnt};
  end


  assign DOT   = record_buf;
  assign DOTEN = &{record_buf_en, (~stall)};

endmodule
module COUPLER #(parameter                           E_LOG = 2,
                 parameter                           DATW  = 64)
                (input  wire                         CLK,
                 input  wire                         RST,
                 input  wire                         IN_FULL,
                 input  wire [(DATW<<(E_LOG-1))-1:0] DIN,
                 input  wire                         DINEN,
                 output wire [(DATW<<E_LOG)-1:0]     DOT,
                 output wire                         DOTEN);



  reg stall;
  always @(posedge CLK) stall <= IN_FULL;

  reg [(DATW<<E_LOG)-1:0] record_buf;
  reg                     record_buf_cnt;
  reg                     record_buf_en;

  always @(posedge CLK) begin
    if (DINEN) record_buf <= {DIN, record_buf[(DATW<<E_LOG)-1:(DATW<<(E_LOG-1))]};
  end
  always @(posedge CLK) begin
    if      (RST)   record_buf_cnt <= 0;
    else if (DINEN) record_buf_cnt <= ~record_buf_cnt;
  end
  always @(posedge CLK) begin
    if      (RST)    record_buf_en <= 0;
    else if (!stall) record_buf_en <= &{DINEN, record_buf_cnt};
  end


  assign DOT   = record_buf;
  assign DOTEN = &{record_buf_en, (~stall)};

endmodule