data/full_repos/permissive/491135068/regfile.v
1: b"%Error: data/full_repos/permissive/491135068/regfile.v:28: Cannot find file containing module: 'zero_reg'\n    zero_reg reg0(\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/491135068,data/full_repos/permissive/491135068/zero_reg\n             data/full_repos/permissive/491135068,data/full_repos/permissive/491135068/zero_reg.v\n             data/full_repos/permissive/491135068,data/full_repos/permissive/491135068/zero_reg.sv\n             zero_reg\n             zero_reg.v\n             zero_reg.sv\n             obj_dir/zero_reg\n             obj_dir/zero_reg.v\n             obj_dir/zero_reg.sv\n%Error: data/full_repos/permissive/491135068/regfile.v:37: Cannot find file containing module: 'register32'\n    register32 reg1(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/regfile.v:47: Cannot find file containing module: 'register32'\n    register32 reg2(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/regfile.v:58: Cannot find file containing module: 'register32'\n    register32 reg3(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/regfile.v:69: Cannot find file containing module: 'register32'\n    register32 reg4(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/regfile.v:79: Cannot find file containing module: 'register32'\n    register32 reg5(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/regfile.v:89: Cannot find file containing module: 'register32'\n    register32 reg6(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/regfile.v:100: Cannot find file containing module: 'register32'\n    register32 reg7(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/regfile.v:111: Cannot find file containing module: 'register32'\n    register32 reg8(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/regfile.v:121: Cannot find file containing module: 'register32'\n    register32 reg9(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/regfile.v:131: Cannot find file containing module: 'register32'\n    register32 reg10(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/regfile.v:142: Cannot find file containing module: 'register32'\n    register32 reg11(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/regfile.v:153: Cannot find file containing module: 'register32'\n    register32 reg12(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/regfile.v:163: Cannot find file containing module: 'register32'\n    register32 reg13(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/regfile.v:173: Cannot find file containing module: 'register32'\n    register32 reg14(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/regfile.v:184: Cannot find file containing module: 'register32'\n    register32 reg15(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/regfile.v:195: Cannot find file containing module: 'register32'\n    register32 reg16(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/regfile.v:205: Cannot find file containing module: 'register32'\n    register32 reg17(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/regfile.v:215: Cannot find file containing module: 'register32'\n    register32 reg18(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/regfile.v:226: Cannot find file containing module: 'register32'\n    register32 reg19(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/regfile.v:237: Cannot find file containing module: 'register32'\n    register32 reg20(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/regfile.v:247: Cannot find file containing module: 'register32'\n    register32 reg21(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/regfile.v:257: Cannot find file containing module: 'register32'\n    register32 reg22(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/regfile.v:268: Cannot find file containing module: 'register32'\n    register32 reg23(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/regfile.v:279: Cannot find file containing module: 'register32'\n    register32 reg24(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/regfile.v:289: Cannot find file containing module: 'register32'\n    register32 reg25(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/regfile.v:299: Cannot find file containing module: 'register32'\n    register32 reg26(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/regfile.v:310: Cannot find file containing module: 'register32'\n    register32 reg27(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/regfile.v:321: Cannot find file containing module: 'register32'\n    register32 reg28(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/regfile.v:331: Cannot find file containing module: 'register32'\n    register32 reg29(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/regfile.v:341: Cannot find file containing module: 'register32'\n    register32 reg30(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/491135068/regfile.v:352: Cannot find file containing module: 'register32'\n    register32 reg31(\n    ^~~~~~~~~~\n%Error: Exiting due to 32 error(s)\n"
module regfile(Aselect, Dselect, dbus, clk, Bselect, abus, bbus);
    input [31:0] Aselect, Bselect, Dselect, dbus;
    input clk;
    output wire [31:0] abus, bbus;
    
    zero_reg reg0(
        .Dselect(Dselect[0]),
        .Aselect(Aselect[0]),
        .Bselect(Bselect[0]),
        .abus(abus),
        .bbus(bbus),
        .D(32'h00000000)
    );
    
    register32 reg1(
        .clk(clk),
        .Dselect(Dselect[1]),
        .Aselect(Aselect[1]),
        .Bselect(Bselect[1]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
    
    register32 reg2(
        .clk(clk),
        .Dselect(Dselect[2]),
        .Aselect(Aselect[2]),
        .Bselect(Bselect[2]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
        
    
    register32 reg3(
        .clk(clk),
        .Dselect(Dselect[3]),
        .Aselect(Aselect[3]),
        .Bselect(Bselect[3]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
      
    
    register32 reg4(
        .clk(clk),
        .Dselect(Dselect[4]),
        .Aselect(Aselect[4]),
        .Bselect(Bselect[4]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
    
    register32 reg5(
        .clk(clk),
        .Dselect(Dselect[5]),
        .Aselect(Aselect[5]),
        .Bselect(Bselect[5]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
    
    register32 reg6(
        .clk(clk),
        .Dselect(Dselect[6]),
        .Aselect(Aselect[6]),
        .Bselect(Bselect[6]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
        
    
    register32 reg7(
        .clk(clk),
        .Dselect(Dselect[7]),
        .Aselect(Aselect[7]),
        .Bselect(Bselect[7]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
      
    
    register32 reg8(
        .clk(clk),
        .Dselect(Dselect[8]),
        .Aselect(Aselect[8]),
        .Bselect(Bselect[8]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
          
    register32 reg9(
        .clk(clk),
        .Dselect(Dselect[9]),
        .Aselect(Aselect[9]),
        .Bselect(Bselect[9]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
    
    register32 reg10(
        .clk(clk),
        .Dselect(Dselect[10]),
        .Aselect(Aselect[10]),
        .Bselect(Bselect[10]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
        
    
    register32 reg11(
        .clk(clk),
        .Dselect(Dselect[11]),
        .Aselect(Aselect[11]),
        .Bselect(Bselect[11]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
      
    
    register32 reg12(
        .clk(clk),
        .Dselect(Dselect[12]),
        .Aselect(Aselect[12]),
        .Bselect(Bselect[12]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
    
    register32 reg13(
        .clk(clk),
        .Dselect(Dselect[13]),
        .Aselect(Aselect[13]),
        .Bselect(Bselect[13]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
    
    register32 reg14(
        .clk(clk),
        .Dselect(Dselect[14]),
        .Aselect(Aselect[14]),
        .Bselect(Bselect[14]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
        
    
    register32 reg15(
        .clk(clk),
        .Dselect(Dselect[15]),
        .Aselect(Aselect[15]),
        .Bselect(Bselect[15]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
      
    
    register32 reg16(
        .clk(clk),
        .Dselect(Dselect[16]),
        .Aselect(Aselect[16]),
        .Bselect(Bselect[16]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
    
    register32 reg17(
        .clk(clk),
        .Dselect(Dselect[17]),
        .Aselect(Aselect[17]),
        .Bselect(Bselect[17]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
    
    register32 reg18(
        .clk(clk),
        .Dselect(Dselect[18]),
        .Aselect(Aselect[18]),
        .Bselect(Bselect[18]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
        
    
    register32 reg19(
        .clk(clk),
        .Dselect(Dselect[19]),
        .Aselect(Aselect[19]),
        .Bselect(Bselect[19]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
      
    
    register32 reg20(
        .clk(clk),
        .Dselect(Dselect[20]),
        .Aselect(Aselect[20]),
        .Bselect(Bselect[20]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
    
    register32 reg21(
        .clk(clk),
        .Dselect(Dselect[21]),
        .Aselect(Aselect[21]),
        .Bselect(Bselect[21]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
    
    register32 reg22(
        .clk(clk),
        .Dselect(Dselect[22]),
        .Aselect(Aselect[22]),
        .Bselect(Bselect[22]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
        
    
    register32 reg23(
        .clk(clk),
        .Dselect(Dselect[23]),
        .Aselect(Aselect[23]),
        .Bselect(Bselect[23]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
      
    
    register32 reg24(
        .clk(clk),
        .Dselect(Dselect[24]),
        .Aselect(Aselect[24]),
        .Bselect(Bselect[24]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
          
    register32 reg25(
        .clk(clk),
        .Dselect(Dselect[25]),
        .Aselect(Aselect[25]),
        .Bselect(Bselect[25]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
    
    register32 reg26(
        .clk(clk),
        .Dselect(Dselect[26]),
        .Aselect(Aselect[26]),
        .Bselect(Bselect[26]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
        
    
    register32 reg27(
        .clk(clk),
        .Dselect(Dselect[27]),
        .Aselect(Aselect[27]),
        .Bselect(Bselect[27]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
      
    
    register32 reg28(
        .clk(clk),
        .Dselect(Dselect[28]),
        .Aselect(Aselect[28]),
        .Bselect(Bselect[28]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
    
    register32 reg29(
        .clk(clk),
        .Dselect(Dselect[29]),
        .Aselect(Aselect[29]),
        .Bselect(Bselect[29]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
    
    register32 reg30(
        .clk(clk),
        .Dselect(Dselect[30]),
        .Aselect(Aselect[30]),
        .Bselect(Bselect[30]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
        
    
    register32 reg31(
        .clk(clk),
        .Dselect(Dselect[31]),
        .Aselect(Aselect[31]),
        .Bselect(Bselect[31]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
    
endmodule
module regfile(Aselect, Dselect, dbus, clk, Bselect, abus, bbus);

    input [31:0] Aselect, Bselect, Dselect, dbus;
    input clk;
    output wire [31:0] abus, bbus;
    
    zero_reg reg0(
        .Dselect(Dselect[0]),
        .Aselect(Aselect[0]),
        .Bselect(Bselect[0]),
        .abus(abus),
        .bbus(bbus),
        .D(32'h00000000)
    );
    
    register32 reg1(
        .clk(clk),
        .Dselect(Dselect[1]),
        .Aselect(Aselect[1]),
        .Bselect(Bselect[1]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
    
    register32 reg2(
        .clk(clk),
        .Dselect(Dselect[2]),
        .Aselect(Aselect[2]),
        .Bselect(Bselect[2]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
        
    
    register32 reg3(
        .clk(clk),
        .Dselect(Dselect[3]),
        .Aselect(Aselect[3]),
        .Bselect(Bselect[3]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
      
    
    register32 reg4(
        .clk(clk),
        .Dselect(Dselect[4]),
        .Aselect(Aselect[4]),
        .Bselect(Bselect[4]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
    
    register32 reg5(
        .clk(clk),
        .Dselect(Dselect[5]),
        .Aselect(Aselect[5]),
        .Bselect(Bselect[5]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
    
    register32 reg6(
        .clk(clk),
        .Dselect(Dselect[6]),
        .Aselect(Aselect[6]),
        .Bselect(Bselect[6]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
        
    
    register32 reg7(
        .clk(clk),
        .Dselect(Dselect[7]),
        .Aselect(Aselect[7]),
        .Bselect(Bselect[7]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
      
    
    register32 reg8(
        .clk(clk),
        .Dselect(Dselect[8]),
        .Aselect(Aselect[8]),
        .Bselect(Bselect[8]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
          
    register32 reg9(
        .clk(clk),
        .Dselect(Dselect[9]),
        .Aselect(Aselect[9]),
        .Bselect(Bselect[9]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
    
    register32 reg10(
        .clk(clk),
        .Dselect(Dselect[10]),
        .Aselect(Aselect[10]),
        .Bselect(Bselect[10]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
        
    
    register32 reg11(
        .clk(clk),
        .Dselect(Dselect[11]),
        .Aselect(Aselect[11]),
        .Bselect(Bselect[11]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
      
    
    register32 reg12(
        .clk(clk),
        .Dselect(Dselect[12]),
        .Aselect(Aselect[12]),
        .Bselect(Bselect[12]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
    
    register32 reg13(
        .clk(clk),
        .Dselect(Dselect[13]),
        .Aselect(Aselect[13]),
        .Bselect(Bselect[13]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
    
    register32 reg14(
        .clk(clk),
        .Dselect(Dselect[14]),
        .Aselect(Aselect[14]),
        .Bselect(Bselect[14]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
        
    
    register32 reg15(
        .clk(clk),
        .Dselect(Dselect[15]),
        .Aselect(Aselect[15]),
        .Bselect(Bselect[15]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
      
    
    register32 reg16(
        .clk(clk),
        .Dselect(Dselect[16]),
        .Aselect(Aselect[16]),
        .Bselect(Bselect[16]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
    
    register32 reg17(
        .clk(clk),
        .Dselect(Dselect[17]),
        .Aselect(Aselect[17]),
        .Bselect(Bselect[17]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
    
    register32 reg18(
        .clk(clk),
        .Dselect(Dselect[18]),
        .Aselect(Aselect[18]),
        .Bselect(Bselect[18]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
        
    
    register32 reg19(
        .clk(clk),
        .Dselect(Dselect[19]),
        .Aselect(Aselect[19]),
        .Bselect(Bselect[19]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
      
    
    register32 reg20(
        .clk(clk),
        .Dselect(Dselect[20]),
        .Aselect(Aselect[20]),
        .Bselect(Bselect[20]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
    
    register32 reg21(
        .clk(clk),
        .Dselect(Dselect[21]),
        .Aselect(Aselect[21]),
        .Bselect(Bselect[21]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
    
    register32 reg22(
        .clk(clk),
        .Dselect(Dselect[22]),
        .Aselect(Aselect[22]),
        .Bselect(Bselect[22]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
        
    
    register32 reg23(
        .clk(clk),
        .Dselect(Dselect[23]),
        .Aselect(Aselect[23]),
        .Bselect(Bselect[23]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
      
    
    register32 reg24(
        .clk(clk),
        .Dselect(Dselect[24]),
        .Aselect(Aselect[24]),
        .Bselect(Bselect[24]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
          
    register32 reg25(
        .clk(clk),
        .Dselect(Dselect[25]),
        .Aselect(Aselect[25]),
        .Bselect(Bselect[25]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
    
    register32 reg26(
        .clk(clk),
        .Dselect(Dselect[26]),
        .Aselect(Aselect[26]),
        .Bselect(Bselect[26]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
        
    
    register32 reg27(
        .clk(clk),
        .Dselect(Dselect[27]),
        .Aselect(Aselect[27]),
        .Bselect(Bselect[27]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
      
    
    register32 reg28(
        .clk(clk),
        .Dselect(Dselect[28]),
        .Aselect(Aselect[28]),
        .Bselect(Bselect[28]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
    
    register32 reg29(
        .clk(clk),
        .Dselect(Dselect[29]),
        .Aselect(Aselect[29]),
        .Bselect(Bselect[29]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
    
    register32 reg30(
        .clk(clk),
        .Dselect(Dselect[30]),
        .Aselect(Aselect[30]),
        .Bselect(Bselect[30]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
        
    
    register32 reg31(
        .clk(clk),
        .Dselect(Dselect[31]),
        .Aselect(Aselect[31]),
        .Bselect(Bselect[31]),
        .abus(abus),
        .bbus(bbus),
        .D(dbus)
    );
    
endmodule