data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_cclk_scanlasr_2x.v
data/verilator_xmls/6f345335-0c39-4fb5-9564-d5a594aee75d.xml
module bw_clk_cclk_scanlasr_2x (so, sd, ck, r_l);
output so;
input sd, ck, r_l;

reg so_l;

    assign so = ~so_l;
    always @ ( ck or sd or r_l )
       if (~(ck & r_l)) so_l <= ~sd ;

endmodule
module bw_clk_cclk_scanlasr_2x (so, sd, ck, r_l);

output so;
input sd, ck, r_l;

reg so_l;

    assign so = ~so_l;
    always @ ( ck or sd or r_l )
       if (~(ck & r_l)) so_l <= ~sd ;

endmodule