data/full_repos/permissive/458935738/remote_control/rx_wrapper.v
1: b"%Error: data/full_repos/permissive/458935738/remote_control/rx_wrapper.v:18: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/458935738/remote_control/rx_wrapper.v:25: syntax error, unexpected input\n    input wire clk, rst, Rx;\n    ^~~~~\n%Error: data/full_repos/permissive/458935738/remote_control/rx_wrapper.v:26: syntax error, unexpected output\n    output reg [DATA_WIDTH-1:0] Rx_data;\n    ^~~~~~\n%Error: data/full_repos/permissive/458935738/remote_control/rx_wrapper.v:32: syntax error, unexpected IDENTIFIER\n    Rx_core #(DATA_WIDTH, BAUD_RATE) core(clk, rst, Rx, Rx_data_raw, Rx_done);\n    ^~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module Rx_wrapper (
    clk, rst,
    Rx,
    Rx_data,
);

    parameter DATA_WIDTH = 8;
    parameter BAUD_RATE = 32'd1667;

    localparam SLEEP = 32'd48000000;

    input wire clk, rst, Rx;
    output reg [DATA_WIDTH-1:0] Rx_data;

    wire Rx_done;
    wire [DATA_WIDTH-1:0] Rx_data_raw;
    reg [31:0] counter;

    Rx_core #(DATA_WIDTH, BAUD_RATE) core(clk, rst, Rx, Rx_data_raw, Rx_done);

    always @(posedge clk) begin
        if (rst) begin
            Rx_data <= 0;
            counter <= 0;
        end else begin
            if (counter == SLEEP) begin
                Rx_data <= 0;
                counter <= 0; 
            end
            else begin 
                Rx_data <= Rx_done ? Rx_data_raw : Rx_data;
                counter <= Rx_done ? 0 : counter + 1;
            end
        end
    end

endmodule
module Rx_wrapper (
    clk, rst,
    Rx,
    Rx_data,
);


    parameter DATA_WIDTH = 8;
    parameter BAUD_RATE = 32'd1667;

    localparam SLEEP = 32'd48000000;

    input wire clk, rst, Rx;
    output reg [DATA_WIDTH-1:0] Rx_data;

    wire Rx_done;
    wire [DATA_WIDTH-1:0] Rx_data_raw;
    reg [31:0] counter;

    Rx_core #(DATA_WIDTH, BAUD_RATE) core(clk, rst, Rx, Rx_data_raw, Rx_done);

    always @(posedge clk) begin
        if (rst) begin
            Rx_data <= 0;
            counter <= 0;
        end else begin
            if (counter == SLEEP) begin
                Rx_data <= 0;
                counter <= 0; 
            end
            else begin 
                Rx_data <= Rx_done ? Rx_data_raw : Rx_data;
                counter <= Rx_done ? 0 : counter + 1;
            end
        end
    end

endmodule