data/full_repos/permissive/441359809/src/yosys/techlibs/intel/cycloneive/arith_map.v
1: b"%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/intel/cycloneive/arith_map.v:83: Can't resolve module reference: '$pos'\n   \\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));\n                                                                      ^~~~~~\n%Error: Exiting due to 1 error(s)\n"
module _80_cycloneive_alu (A, B, CI, BI, X, Y, CO);
   parameter A_SIGNED = 0;
   parameter B_SIGNED = 0;
   parameter A_WIDTH = 1;
   parameter B_WIDTH = 1;
   parameter Y_WIDTH = 1;

   (* force_downto *)
   input [A_WIDTH-1:0] A;
   (* force_downto *)
   input [B_WIDTH-1:0] B;
   (* force_downto *)
   output [Y_WIDTH-1:0] X, Y;

   input                CI, BI;
   output [Y_WIDTH:0]   CO;

   wire                 _TECHMAP_FAIL_ = Y_WIDTH < 5;

   (* force_downto *)
   wire [Y_WIDTH-1:0]   A_buf, B_buf;
   \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
   \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));

   (* force_downto *)
   wire [Y_WIDTH-1:0]   AA = A_buf;
   (* force_downto *)
   wire [Y_WIDTH-1:0]   BB = BI ? ~B_buf : B_buf;
   wire [Y_WIDTH:0]     C = {CO, CI};

   fa f0 (.a_c(AA[0]),
          .b_c(BB[0]),
          .cin_c(C[0]),
          .cout_t(C0[1]),
          .sum_x(Y[0]));

   genvar i;
   generate for (i = 1; i < Y_WIDTH; i = i + 1) begin:slice
      cycloneive_lcell_comb #(.lut_mask(16'b0101_1010_0101_0000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(CO[i]), .dataa(BB[i]), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[i]));
   end endgenerate

   assign X = AA ^ BB;

endmodule
module _80_cycloneive_alu (A, B, CI, BI, X, Y, CO);

   parameter A_SIGNED = 0;
   parameter B_SIGNED = 0;
   parameter A_WIDTH = 1;
   parameter B_WIDTH = 1;
   parameter Y_WIDTH = 1;

   (* force_downto *)
   input [A_WIDTH-1:0] A;
   (* force_downto *)
   input [B_WIDTH-1:0] B;
   (* force_downto *)
   output [Y_WIDTH-1:0] X, Y;

   input                CI, BI;
   output [Y_WIDTH:0]   CO;

   wire                 _TECHMAP_FAIL_ = Y_WIDTH < 5;

   (* force_downto *)
   wire [Y_WIDTH-1:0]   A_buf, B_buf;
   \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
   \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));

   (* force_downto *)
   wire [Y_WIDTH-1:0]   AA = A_buf;
   (* force_downto *)
   wire [Y_WIDTH-1:0]   BB = BI ? ~B_buf : B_buf;
   wire [Y_WIDTH:0]     C = {CO, CI};

   fa f0 (.a_c(AA[0]),
          .b_c(BB[0]),
          .cin_c(C[0]),
          .cout_t(C0[1]),
          .sum_x(Y[0]));

   genvar i;
   generate for (i = 1; i < Y_WIDTH; i = i + 1) begin:slice
      cycloneive_lcell_comb #(.lut_mask(16'b0101_1010_0101_0000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(CO[i]), .dataa(BB[i]), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[i]));
   end endgenerate

   assign X = AA ^ BB;

endmodule