data/full_repos/permissive/531216051/verilog/rtl/Sha256Ppl.v
data/verilator_xmls/247d94c1-94ea-4c6d-bed9-a520ba0cd4ea.xml
function automatic reg [31:0] right_rotate(input reg [31:0] number, input reg[31:0] n);
    right_rotate = (number >> n) | (number << (32 - n));
  endfunction
function automatic reg [31:0] right_rotate(input reg [31:0] number, input reg[31:0] n);

    right_rotate = (number >> n) | (number << (32 - n));
  endfunction