data/full_repos/permissive/429737743/sources_1/new/MCU.v
1: b'%Error: data/full_repos/permissive/429737743/sources_1/new/MCU.v:21: Cannot find include file: cpu_constant.v\n`include "cpu_constant.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/429737743/sources_1/new,data/full_repos/permissive/429737743/cpu_constant.v\n             data/full_repos/permissive/429737743/sources_1/new,data/full_repos/permissive/429737743/cpu_constant.v.v\n             data/full_repos/permissive/429737743/sources_1/new,data/full_repos/permissive/429737743/cpu_constant.v.sv\n             cpu_constant.v\n             cpu_constant.v.v\n             cpu_constant.v.sv\n             obj_dir/cpu_constant.v\n             obj_dir/cpu_constant.v.v\n             obj_dir/cpu_constant.v.sv\n%Error: data/full_repos/permissive/429737743/sources_1/new/MCU.v:85: Define or directive not defined: \'`LDW\'\n                `LDW : begin\n                ^~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/MCU.v:85: syntax error, unexpected \':\', expecting endcase\n                `LDW : begin\n                     ^\n%Error: data/full_repos/permissive/429737743/sources_1/new/MCU.v:93: Define or directive not defined: \'`LDH\'\n                `LDH : begin\n                ^~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/MCU.v:93: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                `LDH : begin\n                       ^~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/MCU.v:97: Define or directive not defined: \'`LDB\'\n                `LDB : out = {24\'h000000, M[address / 4][address % 4 * 8 + 7 -: 8]};\n                ^~~~\n%Warning-ENDLABEL: data/full_repos/permissive/429737743/sources_1/new/MCU.v:97: End label \'out\' does not match begin label \'\'\n                `LDB : out = {24\'h000000, M[address / 4][address % 4 * 8 + 7 -: 8]};\n                       ^~~\n                   ... Use "/* verilator lint_off ENDLABEL */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/429737743/sources_1/new/MCU.v:97: syntax error, unexpected \'=\'\n                `LDB : out = {24\'h000000, M[address / 4][address % 4 * 8 + 7 -: 8]};\n                           ^\n%Error: data/full_repos/permissive/429737743/sources_1/new/MCU.v:98: Define or directive not defined: \'`STB\'\n                `STB : M[address / 4][address % 4 * 8 + 7 -: 8] = num[7 : 0];\n                ^~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/MCU.v:99: Define or directive not defined: \'`STH\'\n                `STH : begin\n                ^~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/MCU.v:103: Define or directive not defined: \'`STW\'\n                `STW :begin\n                ^~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/MCU.v:103: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n                `STW :begin\n                      ^~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/MCU.v:109: syntax error, unexpected \':\', expecting clocking\n                default : out = {\n                        ^\n%Error: Cannot continue\n'
module MCU(out, address, num, ctl);
    output [31 : 0] out;reg [31 : 0] out;
    input [31 : 0] address, num;
    input [3 : 0] ctl;
    reg [31 : 0] M[0 : 8'hff];



    initial begin

        M[0] = 32'b0000000_00001_00000_000_00010_0110011;
        M[1] = 32'b111111111101_00000_000_00011_0010011;
        M[2] = 0;




        M[15] = 32'b00000000_00000000_00000000_00001011;
        M[17] = 32'b11111111_11111111_11111111_11111001;

        M[3] = 32'b0000000_00001_00001_100_00001_0110011;
        M[4] = 32'b000000111100_00001_010_00010_0000011;
        M[5] = 32'b000001000100_00001_010_00011_0000011;
        M[6] = 32'b0000000_00010_00011_000_00100_0110011;
        M[7] = 32'b0000001_00100_00001_010_11100_0100011;
        M[8] = 0;





        M[25] = 32'b00000000_00000000_00000000_01100101;

        M[9] = 32'b0000000_00011_00011_100_00011_0110011;
        M[10] = 32'b0000000_00000_00000_100_00000_0110011;
        M[11] = 32'b0000000_00001_00001_100_00001_0110011;
        M[12] = 32'b000001100100_00000_010_00010_0000011;
        M[13] = 32'b0000000_00011_00001_000_00011_0110011;
        M[14] = 32'b000000000001_00001_000_00001_0010011;
        M[15] = 32'b1111111_00010_00001_100_11001_1100011;
        M[16] = 32'b0000011_00011_00000_010_01000_0100011;
        M[17] = 0;



        M[18] = 32'b0_0000011000_0_0_00000000_00001_1101111;
        M[19] = 32'b00001111_000000000000_00010_0010111;
        M[20] = 0;
        M[24] = 32'b000000011000_00010_000_00010_0010011;
        M[25] = 32'b000000000000_00001_000_00011_1100111;
        M[26] = 0;


    end


    always@(*) begin
        if (ctl[3 : 3]) begin
            case (ctl[2 : 0])
                `LDW : begin
                    out = {
                        M[(address + 3) / 4][(address + 3) % 4 * 8 + 7 -: 8],
                        M[(address + 2) / 4][(address + 2) % 4 * 8 + 7 -: 8],
                        M[(address + 1) / 4][(address + 1) % 4 * 8 + 7 -: 8],
                        M[address / 4][address % 4 * 8 + 7 -: 8]
                    };
                end
                `LDH : begin
                    out = {16'h0000, M[(address + 1) / 4][(address + 1) % 4 * 8 + 7 -: 8],
                        M[address / 4][address % 4 * 8 + 7 -: 8]};
                end
                `LDB : out = {24'h000000, M[address / 4][address % 4 * 8 + 7 -: 8]};
                `STB : M[address / 4][address % 4 * 8 + 7 -: 8] = num[7 : 0];
                `STH : begin
                    M[(address + 1) / 4][(address + 1) % 4 * 8 + 7 -: 8] = num[15 : 8];
                    M[address / 4][address % 4 * 8 + 7 -: 8] = num[7 : 0];
                end
                `STW :begin
                    M[(address + 3) / 4][(address + 3) % 4 * 8 + 7 -: 8] = num[31 : 24];
                    M[(address + 2) / 4][(address + 2) % 4 * 8 + 7 -: 8] = num[23 : 16];
                    M[(address + 1) / 4][(address + 1) % 4 * 8 + 7 -: 8] = num[15 : 8];
                    M[address / 4][address % 4 * 8 + 7 -: 8] = num[7 : 0];
                end 
                default : out = {
                    M[(address + 3) / 4][(address + 3) % 4 * 8 + 7 -: 8],
                    M[(address + 2) / 4][(address + 2) % 4 * 8 + 7 -: 8],
                    M[(address + 1) / 4][(address + 1) % 4 * 8 + 7 -: 8],
                    M[address / 4][address % 4 * 8 + 7 -: 8]
                };
            endcase
        end
    end
endmodule
module MCU(out, address, num, ctl);

    output [31 : 0] out;reg [31 : 0] out;
    input [31 : 0] address, num;
    input [3 : 0] ctl;
    reg [31 : 0] M[0 : 8'hff];



    initial begin

        M[0] = 32'b0000000_00001_00000_000_00010_0110011;
        M[1] = 32'b111111111101_00000_000_00011_0010011;
        M[2] = 0;




        M[15] = 32'b00000000_00000000_00000000_00001011;
        M[17] = 32'b11111111_11111111_11111111_11111001;

        M[3] = 32'b0000000_00001_00001_100_00001_0110011;
        M[4] = 32'b000000111100_00001_010_00010_0000011;
        M[5] = 32'b000001000100_00001_010_00011_0000011;
        M[6] = 32'b0000000_00010_00011_000_00100_0110011;
        M[7] = 32'b0000001_00100_00001_010_11100_0100011;
        M[8] = 0;





        M[25] = 32'b00000000_00000000_00000000_01100101;

        M[9] = 32'b0000000_00011_00011_100_00011_0110011;
        M[10] = 32'b0000000_00000_00000_100_00000_0110011;
        M[11] = 32'b0000000_00001_00001_100_00001_0110011;
        M[12] = 32'b000001100100_00000_010_00010_0000011;
        M[13] = 32'b0000000_00011_00001_000_00011_0110011;
        M[14] = 32'b000000000001_00001_000_00001_0010011;
        M[15] = 32'b1111111_00010_00001_100_11001_1100011;
        M[16] = 32'b0000011_00011_00000_010_01000_0100011;
        M[17] = 0;



        M[18] = 32'b0_0000011000_0_0_00000000_00001_1101111;
        M[19] = 32'b00001111_000000000000_00010_0010111;
        M[20] = 0;
        M[24] = 32'b000000011000_00010_000_00010_0010011;
        M[25] = 32'b000000000000_00001_000_00011_1100111;
        M[26] = 0;


    end


    always@(*) begin
        if (ctl[3 : 3]) begin
            case (ctl[2 : 0])
                `LDW : begin
                    out = {
                        M[(address + 3) / 4][(address + 3) % 4 * 8 + 7 -: 8],
                        M[(address + 2) / 4][(address + 2) % 4 * 8 + 7 -: 8],
                        M[(address + 1) / 4][(address + 1) % 4 * 8 + 7 -: 8],
                        M[address / 4][address % 4 * 8 + 7 -: 8]
                    };
                end
                `LDH : begin
                    out = {16'h0000, M[(address + 1) / 4][(address + 1) % 4 * 8 + 7 -: 8],
                        M[address / 4][address % 4 * 8 + 7 -: 8]};
                end
                `LDB : out = {24'h000000, M[address / 4][address % 4 * 8 + 7 -: 8]};
                `STB : M[address / 4][address % 4 * 8 + 7 -: 8] = num[7 : 0];
                `STH : begin
                    M[(address + 1) / 4][(address + 1) % 4 * 8 + 7 -: 8] = num[15 : 8];
                    M[address / 4][address % 4 * 8 + 7 -: 8] = num[7 : 0];
                end
                `STW :begin
                    M[(address + 3) / 4][(address + 3) % 4 * 8 + 7 -: 8] = num[31 : 24];
                    M[(address + 2) / 4][(address + 2) % 4 * 8 + 7 -: 8] = num[23 : 16];
                    M[(address + 1) / 4][(address + 1) % 4 * 8 + 7 -: 8] = num[15 : 8];
                    M[address / 4][address % 4 * 8 + 7 -: 8] = num[7 : 0];
                end 
                default : out = {
                    M[(address + 3) / 4][(address + 3) % 4 * 8 + 7 -: 8],
                    M[(address + 2) / 4][(address + 2) % 4 * 8 + 7 -: 8],
                    M[(address + 1) / 4][(address + 1) % 4 * 8 + 7 -: 8],
                    M[address / 4][address % 4 * 8 + 7 -: 8]
                };
            endcase
        end
    end
endmodule