data/full_repos/permissive/511535464/src/BranchForwarding.v
data/verilator_xmls/412d5a67-979e-4f7b-980b-5f413937c1dd.xml
module BranchForwarding(
    input wire [4:0] rs,
    input wire [4:0] rt,
    input wire [4:0] Rw_MEM,
    input wire RegWrite_MEM,
    input wire Load_WB,
    input wire [4:0] Rw_WB,
    output wire [1:0] BrForwardingA,
    output wire [1:0] BrForwardingB
);

    assign BrForwardingA = rs == Rw_WB && Load_WB ? 2 : 
                           rs == Rw_MEM && RegWrite_MEM ? 1 : 0;
    assign BrForwardingB = rt == Rw_WB && Load_WB ? 2 : 
                           rt == Rw_MEM && RegWrite_MEM ? 1 : 0;

endmodule
module BranchForwarding(
    input wire [4:0] rs,
    input wire [4:0] rt,
    input wire [4:0] Rw_MEM,
    input wire RegWrite_MEM,
    input wire Load_WB,
    input wire [4:0] Rw_WB,
    output wire [1:0] BrForwardingA,
    output wire [1:0] BrForwardingB
);


    assign BrForwardingA = rs == Rw_WB && Load_WB ? 2 : 
                           rs == Rw_MEM && RegWrite_MEM ? 1 : 0;
    assign BrForwardingB = rt == Rw_WB && Load_WB ? 2 : 
                           rt == Rw_MEM && RegWrite_MEM ? 1 : 0;

endmodule