data/full_repos/permissive/419538859/lab6/sim/lab6.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/419538859/lab6/sim/lab6.v:110: Multiple top level modules\n                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                           : ... Top module \'lab6\'\nmodule lab6(clk, reset, column, sel, seg7);\n       ^~~~\n                                                                           : ... Top module \'key_led\'\nmodule  key_led(clk_sel, reset, column, sel, key_code);\n        ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/419538859/lab6/sim/lab6.v:122: Signal definition not found, creating implicitly: \'press_valid\'\nkey_buf6 g3(clk_sel, reset, press_valid, scan_code, display_code);\n                            ^~~~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n'
module 		freq_div(clk_in,reset,clk_out);

parameter	exp = 20;   
input		clk_in, reset;
output		clk_out;
reg			[exp-1:0] divider;
integer 	i;

assign 	clk_out= divider[exp-1];

always@ (posedge clk_in or posedge reset)
begin
	if(reset)
		for(i=0; i < exp; i=i+1)
		divider[i] = 1'b0;
	else
		divider = divider+ 1'b1;
end
endmodule
module 		freq_div(clk_in,reset,clk_out);


parameter	exp = 20;   
input		clk_in, reset;
output		clk_out;
reg			[exp-1:0] divider;
integer 	i;

assign 	clk_out= divider[exp-1];

always@ (posedge clk_in or posedge reset)
begin
	if(reset)
		for(i=0; i < exp; i=i+1)
		divider[i] = 1'b0;
	else
		divider = divider+ 1'b1;
end
endmodule