data/full_repos/permissive/41404488/verilog/snes_bus_sync.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:111: Unsupported: Ignoring delay on this delayed statement.\nalways #14.3 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:112: Unsupported: Ignoring delay on this delayed statement.\nalways #139.6 cycle_clk = ~cycle_clk;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:113: Unsupported: Ignoring delay on this delayed statement.\ninitial #1000 rst_n = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:118: Unsupported: Ignoring delay on this delayed statement.\n D  = $random; #2;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:119: Unsupported: Ignoring delay on this delayed statement.\n D  = $random; #2;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:120: Unsupported: Ignoring delay on this delayed statement.\n D  = $random; #2;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:121: Unsupported: Ignoring delay on this delayed statement.\n D  = $random; #2;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:122: Unsupported: Ignoring delay on this delayed statement.\n D  = $random; #2;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:125: Unsupported: Ignoring delay on this delayed statement.\n PA = $random; #2;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:126: Unsupported: Ignoring delay on this delayed statement.\n PA = $random; #2;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:127: Unsupported: Ignoring delay on this delayed statement.\n PA = $random; #2;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:128: Unsupported: Ignoring delay on this delayed statement.\n PA = $random; #2;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:129: Unsupported: Ignoring delay on this delayed statement.\n PA = $random; #2;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:116: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s MODDIVS generates 32 bits.\n                                                                               : ... In instance snes_bus_sync_test\n if (PARD_n) PARD_n = $random % 2;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:118: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                               : ... In instance snes_bus_sync_test\n D  = $random; #2;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:119: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                               : ... In instance snes_bus_sync_test\n D  = $random; #2;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:120: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                               : ... In instance snes_bus_sync_test\n D  = $random; #2;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:121: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                               : ... In instance snes_bus_sync_test\n D  = $random; #2;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:122: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                               : ... In instance snes_bus_sync_test\n D  = $random; #2;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:125: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                               : ... In instance snes_bus_sync_test\n PA = $random; #2;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:126: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                               : ... In instance snes_bus_sync_test\n PA = $random; #2;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:127: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                               : ... In instance snes_bus_sync_test\n PA = $random; #2;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:128: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                               : ... In instance snes_bus_sync_test\n PA = $random; #2;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/41404488/verilog/snes_bus_sync.v:129: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                               : ... In instance snes_bus_sync_test\n PA = $random; #2;\n    ^\n%Error: Exiting due to 24 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module snes_bus_sync_test ();

reg clk = 0;
reg cycle_clk = 0;
reg rst_n = 0;
reg [7:0] PA = 0;
reg [7:0] D = 0;
wire [7:0] PA_sync;
wire [7:0] D_sync;
wire event_latch;
reg PARD_n = 1;

snes_bus_sync bs (
	.clk(clk),
	.rst_n(rst_n),
	.PA(PA),
	.event_latch(event_latch)
);

always #14.3 clk = ~clk;
always #139.6 cycle_clk = ~cycle_clk;
initial #1000 rst_n = 1;

always @(posedge cycle_clk) begin
	if (PARD_n) PARD_n = $random % 2;
	else PARD_n = 1;
	D  = $random; #2;
	D  = $random; #2;
	D  = $random; #2;
	D  = $random; #2;
	D  = $random; #2;
end
always @(posedge cycle_clk) begin
	PA = $random; #2;
	PA = $random; #2;
	PA = $random; #2;
	PA = $random; #2;
	PA = $random; #2;
end



endmodule
module snes_bus_sync_test ();


reg clk = 0;
reg cycle_clk = 0;
reg rst_n = 0;
reg [7:0] PA = 0;
reg [7:0] D = 0;
wire [7:0] PA_sync;
wire [7:0] D_sync;
wire event_latch;
reg PARD_n = 1;

snes_bus_sync bs (
	.clk(clk),
	.rst_n(rst_n),
	.PA(PA),
	.event_latch(event_latch)
);

always #14.3 clk = ~clk;
always #139.6 cycle_clk = ~cycle_clk;
initial #1000 rst_n = 1;

always @(posedge cycle_clk) begin
	if (PARD_n) PARD_n = $random % 2;
	else PARD_n = 1;
	D  = $random; #2;
	D  = $random; #2;
	D  = $random; #2;
	D  = $random; #2;
	D  = $random; #2;
end
always @(posedge cycle_clk) begin
	PA = $random; #2;
	PA = $random; #2;
	PA = $random; #2;
	PA = $random; #2;
	PA = $random; #2;
end



endmodule