data/full_repos/permissive/485721981/sources/simulation/registry_tb.sv
1: b'%Error: data/full_repos/permissive/485721981/sources/simulation/registry_tb.sv:45: Unsupported: Static in this context\n    static int seed = $urandom + 0;\n    ^~~~~~\n%Error: data/full_repos/permissive/485721981/sources/simulation/registry_tb.sv:45: Unsupported or unknown PLI call: $urandom\n    static int seed = $urandom + 0;\n                      ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/485721981/sources/simulation/registry_tb.sv:109: Unsupported: Ignoring delay on this delayed statement.\n        #(2 * C_CLK_PERIOD) rRstb <= 1\'b0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/485721981/sources/simulation/registry_tb.sv:110: Unsupported: Ignoring delay on this delayed statement.\n        #(10 * C_CLK_PERIOD) rRstb <= 1\'b1;\n        ^\n%Error: data/full_repos/permissive/485721981/sources/simulation/registry_tb.sv:117: Unsupported or unknown PLI call: $dist_normal\n        #(0.001 * $dist_normal(seed, 1000.0 * C_CLK_PERIOD / 2, C_CLK_JTR));\n                  ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/485721981/sources/simulation/registry_tb.sv:117: Unsupported: Ignoring delay on this delayed statement.\n        #(0.001 * $dist_normal(seed, 1000.0 * C_CLK_PERIOD / 2, C_CLK_JTR));\n        ^\n%Error: data/full_repos/permissive/485721981/sources/simulation/registry_tb.sv:130: Unsupported or unknown PLI call: $dist_normal\n        #($dist_normal(seed, 10 * C_CLK_PERIOD, 2 * C_CLK_PERIOD));\n          ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/485721981/sources/simulation/registry_tb.sv:130: Unsupported: Ignoring delay on this delayed statement.\n        #($dist_normal(seed, 10 * C_CLK_PERIOD, 2 * C_CLK_PERIOD));\n        ^\n%Error: data/full_repos/permissive/485721981/sources/simulation/registry_tb.sv:133: syntax error, unexpected \'@\'\n        @(posedge rClk);\n        ^\n%Error: data/full_repos/permissive/485721981/sources/simulation/registry_tb.sv:136: Unsupported or unknown PLI call: $urandom_range\n        rData <= $urandom_range(0, 255);\n                 ^~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/485721981/sources/simulation/registry_tb.sv:137: Unsupported: Ignoring delay on this delayed statement.\n        #1 rValid <= 1\'b1;\n        ^\n%Error: data/full_repos/permissive/485721981/sources/simulation/registry_tb.sv:140: Unsupported: wait statements\n        wait(wAck == 1\'b1);\n        ^~~~\n%Error: data/full_repos/permissive/485721981/sources/simulation/registry_tb.sv:143: syntax error, unexpected \'@\'\n        @(posedge rClk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/485721981/sources/simulation/registry_tb.sv:144: Unsupported: Ignoring delay on this delayed statement.\n        #1 rValid <= 1\'b0;\n        ^\n%Error: Exiting due to 8 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module registry_tb();
    



    

    parameter C_CLK_FRQ         = 100000000;
    parameter C_CLK_JTR         = 50;
    localparam real C_CLK_PERIOD = 1E9 / C_CLK_FRQ;
        

    parameter C_UART_DATA_WIDTH = 8;


    parameter C_REG_WIDTH = 5;


    localparam C_REG_COUNT_WIDTH = C_UART_DATA_WIDTH - C_REG_WIDTH; 
    localparam C_REG_COUNT = 2**C_REG_COUNT_WIDTH;
    localparam C_REG_PORT_WIDTH = C_REG_COUNT * C_REG_WIDTH;






        

    static int seed = $urandom + 0;
    
    



    

    reg rRstb;
    reg rClk;
        

    reg [C_UART_DATA_WIDTH - 1 : 0] rData;
    reg rValid;
    wire wAck;
    wire [C_REG_WIDTH - 1 : 0] wRegister [C_REG_COUNT - 1 : 0];
    

    wire [C_REG_PORT_WIDTH - 1 : 0] wRegPort;
    genvar i;
    generate
        for (i = 0; i < C_REG_COUNT; i = i + 1) begin
            assign wRegister[i] = wRegPort[(i + 1) *C_REG_WIDTH - 1 : i * C_REG_WIDTH];    
        end
    endgenerate


    wire [C_UART_DATA_WIDTH - C_REG_WIDTH : 0] wAdd;
    wire [C_REG_WIDTH : 0] wDta;
    assign wAdd = rData[C_UART_DATA_WIDTH - 1 : C_REG_WIDTH];
    assign wDta = rData[C_REG_WIDTH - 1 : 0];
    






    registry #(
        .C_UART_DATA_WIDTH(C_UART_DATA_WIDTH),
        .C_REG_WIDTH(C_REG_WIDTH)
    ) DUT (
        .rstb(rRstb),
        .clk(rClk),
        .data(rData),
        .valid(rValid),
        .ack(wAck),
        .register(wRegPort)
    );
    
        



    

    initial begin 
        

        rRstb = 1'b1;
        rClk = 1'b0; 
        rValid = 1'b0;
                     

        #(2 * C_CLK_PERIOD) rRstb <= 1'b0;
        #(10 * C_CLK_PERIOD) rRstb <= 1'b1;
    end
    



    always begin
        #(0.001 * $dist_normal(seed, 1000.0 * C_CLK_PERIOD / 2, C_CLK_JTR));
        rClk = ! rClk;
    end      
    
   



        

    always begin
        

        #($dist_normal(seed, 10 * C_CLK_PERIOD, 2 * C_CLK_PERIOD));
                

        @(posedge rClk);
            

        rData <= $urandom_range(0, 255);
        #1 rValid <= 1'b1;
        

        wait(wAck == 1'b1);
            

        @(posedge rClk);
        #1 rValid <= 1'b0;

    end

           
endmodule
module registry_tb();

    



    

    parameter C_CLK_FRQ         = 100000000;
    parameter C_CLK_JTR         = 50;
    localparam real C_CLK_PERIOD = 1E9 / C_CLK_FRQ;
        

    parameter C_UART_DATA_WIDTH = 8;


    parameter C_REG_WIDTH = 5;


    localparam C_REG_COUNT_WIDTH = C_UART_DATA_WIDTH - C_REG_WIDTH; 
    localparam C_REG_COUNT = 2**C_REG_COUNT_WIDTH;
    localparam C_REG_PORT_WIDTH = C_REG_COUNT * C_REG_WIDTH;






        

    static int seed = $urandom + 0;
    
    



    

    reg rRstb;
    reg rClk;
        

    reg [C_UART_DATA_WIDTH - 1 : 0] rData;
    reg rValid;
    wire wAck;
    wire [C_REG_WIDTH - 1 : 0] wRegister [C_REG_COUNT - 1 : 0];
    

    wire [C_REG_PORT_WIDTH - 1 : 0] wRegPort;
    genvar i;
    generate
        for (i = 0; i < C_REG_COUNT; i = i + 1) begin
            assign wRegister[i] = wRegPort[(i + 1) *C_REG_WIDTH - 1 : i * C_REG_WIDTH];    
        end
    endgenerate


    wire [C_UART_DATA_WIDTH - C_REG_WIDTH : 0] wAdd;
    wire [C_REG_WIDTH : 0] wDta;
    assign wAdd = rData[C_UART_DATA_WIDTH - 1 : C_REG_WIDTH];
    assign wDta = rData[C_REG_WIDTH - 1 : 0];
    






    registry #(
        .C_UART_DATA_WIDTH(C_UART_DATA_WIDTH),
        .C_REG_WIDTH(C_REG_WIDTH)
    ) DUT (
        .rstb(rRstb),
        .clk(rClk),
        .data(rData),
        .valid(rValid),
        .ack(wAck),
        .register(wRegPort)
    );
    
        



    

    initial begin 
        

        rRstb = 1'b1;
        rClk = 1'b0; 
        rValid = 1'b0;
                     

        #(2 * C_CLK_PERIOD) rRstb <= 1'b0;
        #(10 * C_CLK_PERIOD) rRstb <= 1'b1;
    end
    



    always begin
        #(0.001 * $dist_normal(seed, 1000.0 * C_CLK_PERIOD / 2, C_CLK_JTR));
        rClk = ! rClk;
    end      
    
   



        

    always begin
        

        #($dist_normal(seed, 10 * C_CLK_PERIOD, 2 * C_CLK_PERIOD));
                

        @(posedge rClk);
            

        rData <= $urandom_range(0, 255);
        #1 rValid <= 1'b1;
        

        wait(wAck == 1'b1);
            

        @(posedge rClk);
        #1 rValid <= 1'b0;

    end

           
endmodule