data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic/saturated-adder-tb.v
1: b'%Error: data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic/saturated-adder-tb.v:1: Cannot find include file: saturated-adder.v\n`include "saturated-adder.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic,data/full_repos/permissive/474294847/saturated-adder.v\n             data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic,data/full_repos/permissive/474294847/saturated-adder.v.v\n             data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic,data/full_repos/permissive/474294847/saturated-adder.v.sv\n             saturated-adder.v\n             saturated-adder.v.v\n             saturated-adder.v.sv\n             obj_dir/saturated-adder.v\n             obj_dir/saturated-adder.v.v\n             obj_dir/saturated-adder.v.sv\n%Error: data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic/saturated-adder-tb.v:16: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("./build/rtl-sim/vcd/saturated_adder.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic/saturated-adder-tb.v:17: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic/saturated-adder-tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module saturated_adder_tb;

reg signed [7:0] a, b;
wire signed [7:0] c;

saturated_adder dut
(
    a, b, c
);
defparam dut.WIDTH = 8;

initial
begin
    $dumpfile("./build/rtl-sim/vcd/saturated_adder.vcd");
    $dumpvars;
end

integer i;
initial
begin
    a = 120;
    b = -12;
    #100;
end

endmodule
module saturated_adder_tb;


reg signed [7:0] a, b;
wire signed [7:0] c;

saturated_adder dut
(
    a, b, c
);
defparam dut.WIDTH = 8;

initial
begin
    $dumpfile("./build/rtl-sim/vcd/saturated_adder.vcd");
    $dumpvars;
end

integer i;
initial
begin
    a = 120;
    b = -12;
    #100;
end

endmodule