data/full_repos/permissive/517906272/syn_fifo_test.v
1: b'%Error: data/full_repos/permissive/517906272/syn_fifo_test.v:1: Cannot find include file: syn_fifo.v\n`include "syn_fifo.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/517906272,data/full_repos/permissive/517906272/syn_fifo.v\n             data/full_repos/permissive/517906272,data/full_repos/permissive/517906272/syn_fifo.v.v\n             data/full_repos/permissive/517906272,data/full_repos/permissive/517906272/syn_fifo.v.sv\n             syn_fifo.v\n             syn_fifo.v.v\n             syn_fifo.v.sv\n             obj_dir/syn_fifo.v\n             obj_dir/syn_fifo.v.v\n             obj_dir/syn_fifo.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/517906272/syn_fifo_test.v:19: Unsupported: Ignoring delay on this delayed statement.\nalways #30 clk=~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/517906272/syn_fifo_test.v:22: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("syn_fifo_test.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/517906272/syn_fifo_test.v:23: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,syn_fifo_test);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/517906272/syn_fifo_test.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #60;we=1;data=\'d7;rst=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/517906272/syn_fifo_test.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #60;we=1;data=\'d1;re=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/517906272/syn_fifo_test.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #60;we=1;data=\'d2;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/517906272/syn_fifo_test.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #60;we=1;data=\'d3;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/517906272/syn_fifo_test.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #60;we=1;data=\'d6;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/517906272/syn_fifo_test.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #60;we=1;data=\'d5;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/517906272/syn_fifo_test.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #60;we=1;data=\'d4;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/517906272/syn_fifo_test.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #60;we=1;data=\'d7;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/517906272/syn_fifo_test.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #60;re=1;we=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/517906272/syn_fifo_test.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #60;\n    ^\n%Error: Exiting due to 3 error(s), 11 warning(s)\n'
module syn_fifo_test;


reg clk,rst,we,re;
reg [3:0] data;


wire [3:0] read_data;

syn_fifo uut(
    .clk(clk),
    .rst(rst),
    .we(we),
    .re(re),
    .data(data),
    .read_data(read_data)
);
always #30 clk=~clk;

initial begin
    $dumpfile("syn_fifo_test.vcd");
    $dumpvars(0,syn_fifo_test);

    clk=1;rst=1;we=0;re=0;data=0;

    #60;we=1;data='d7;rst=0;

    

    #60;we=1;data='d1;re=0;
    #60;we=1;data='d2;
    #60;we=1;data='d3;
    #60;we=1;data='d6;
    #60;we=1;data='d5;
    #60;we=1;data='d4;
    #60;we=1;data='d7;

    #60;re=1;we=0;
    #60;
    $finish;
end
endmodule
module syn_fifo_test;



reg clk,rst,we,re;
reg [3:0] data;


wire [3:0] read_data;

syn_fifo uut(
    .clk(clk),
    .rst(rst),
    .we(we),
    .re(re),
    .data(data),
    .read_data(read_data)
);
always #30 clk=~clk;

initial begin
    $dumpfile("syn_fifo_test.vcd");
    $dumpvars(0,syn_fifo_test);

    clk=1;rst=1;we=0;re=0;data=0;

    #60;we=1;data='d7;rst=0;

    

    #60;we=1;data='d1;re=0;
    #60;we=1;data='d2;
    #60;we=1;data='d3;
    #60;we=1;data='d6;
    #60;we=1;data='d5;
    #60;we=1;data='d4;
    #60;we=1;data='d7;

    #60;re=1;we=0;
    #60;
    $finish;
end
endmodule