data/full_repos/permissive/488490114/test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/488490114/test.v:30: Unsupported: Ignoring delay on this delayed statement.\n #5 CLK = ~CLK;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/488490114/test.v:35: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488490114/test.v:39: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488490114/test.v:42: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488490114/test.v:46: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488490114/test.v:49: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488490114/test.v:53: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488490114/test.v:56: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488490114/test.v:60: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488490114/test.v:63: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488490114/test.v:67: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488490114/test.v:70: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488490114/test.v:74: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488490114/test.v:77: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488490114/test.v:80: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488490114/test.v:86: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488490114/test.v:89: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488490114/test.v:93: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488490114/test.v:96: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488490114/test.v:100: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488490114/test.v:103: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488490114/test.v:107: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488490114/test.v:110: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488490114/test.v:114: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488490114/test.v:117: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488490114/test.v:121: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/488490114/test.v:124: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Error: data/full_repos/permissive/488490114/test.v:15: Cannot find file containing module: \'Locker_Top\'\nLocker_Top UUT(\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/488490114,data/full_repos/permissive/488490114/Locker_Top\n             data/full_repos/permissive/488490114,data/full_repos/permissive/488490114/Locker_Top.v\n             data/full_repos/permissive/488490114,data/full_repos/permissive/488490114/Locker_Top.sv\n             Locker_Top\n             Locker_Top.v\n             Locker_Top.sv\n             obj_dir/Locker_Top\n             obj_dir/Locker_Top.v\n             obj_dir/Locker_Top.sv\n%Error: Exiting due to 1 error(s), 27 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;
reg CLK;
reg RST;
reg BTNA;
reg BTNB;
reg BTNC;
reg BTND;
reg BTNE;
reg BTNF;
wire SUCESS_COMB_LED;
wire WRONG_COMB_LED;
wire [5:0]ANODE;
wire [6:0]SEGMENTS;

Locker_Top UUT(
.CLK(CLK),
.RST(RST),
.BTNA(BTNA),
.BTNB(BTNB),
.BTNC(BTNC),
.BTND(BTND),
.BTNE(BTNE),
.BTNF(BTNF),
.SUCESS_COMB_LED(SUCESS_COMB_LED),
.WRONG_COMB_LED(WRONG_COMB_LED),
.ANODE(ANODE),
.SEGMENTS(SEGMENTS)
);
always
	#5 CLK = ~CLK;

initial begin
	CLK = 1'b0;
	RST = 1'b1;
	#20;
	
	RST = 1'b0;
	BTNA = 1'b1;
	#10
	BTNA = 1'b0;
	
	#10
	
	RST = 1'b0;
	BTNB = 1'b1;
	#10
	BTNB = 1'b0;
	
	#10
	
	RST = 1'b0;
	BTNC = 1'b1;
	#10
	BTNC = 1'b0;
	
	#10
	
	RST = 1'b0;
	BTND = 1'b1;
	#10
	BTND = 1'b0;
	
	#10
	
	RST = 1'b0;
	BTNE = 1'b1;
	#10
	BTNE = 1'b0;
	
	#10
	
	RST = 1'b0;
	BTNF = 1'b1;
	#10
	BTNF = 1'b0;
	
	#20
	
	RST = 1'b1;
	#20
	

	
	RST = 1'b0;
	BTNA = 1'b1;
	#10
	BTNA = 1'b0;
	
	#10
	
	RST = 1'b0;
	BTNA = 1'b1;
	#10
	BTNA = 1'b0;
	
	#10
	
	RST = 1'b0;
	BTNC = 1'b1;
	#10
	BTNC = 1'b0;
	
	#10
	
	RST = 1'b0;
	BTND = 1'b1;
	#10
	BTND = 1'b0;
	
	#10
	
	RST = 1'b0;
	BTNE = 1'b1;
	#10
	BTNE = 1'b0;
	
	#10
	
	RST = 1'b0;
	BTNF = 1'b1;
	#10
	BTNF = 1'b0;
	
	#20;

end

endmodule
module test;

reg CLK;
reg RST;
reg BTNA;
reg BTNB;
reg BTNC;
reg BTND;
reg BTNE;
reg BTNF;
wire SUCESS_COMB_LED;
wire WRONG_COMB_LED;
wire [5:0]ANODE;
wire [6:0]SEGMENTS;

Locker_Top UUT(
.CLK(CLK),
.RST(RST),
.BTNA(BTNA),
.BTNB(BTNB),
.BTNC(BTNC),
.BTND(BTND),
.BTNE(BTNE),
.BTNF(BTNF),
.SUCESS_COMB_LED(SUCESS_COMB_LED),
.WRONG_COMB_LED(WRONG_COMB_LED),
.ANODE(ANODE),
.SEGMENTS(SEGMENTS)
);
always
	#5 CLK = ~CLK;

initial begin
	CLK = 1'b0;
	RST = 1'b1;
	#20;
	
	RST = 1'b0;
	BTNA = 1'b1;
	#10
	BTNA = 1'b0;
	
	#10
	
	RST = 1'b0;
	BTNB = 1'b1;
	#10
	BTNB = 1'b0;
	
	#10
	
	RST = 1'b0;
	BTNC = 1'b1;
	#10
	BTNC = 1'b0;
	
	#10
	
	RST = 1'b0;
	BTND = 1'b1;
	#10
	BTND = 1'b0;
	
	#10
	
	RST = 1'b0;
	BTNE = 1'b1;
	#10
	BTNE = 1'b0;
	
	#10
	
	RST = 1'b0;
	BTNF = 1'b1;
	#10
	BTNF = 1'b0;
	
	#20
	
	RST = 1'b1;
	#20
	

	
	RST = 1'b0;
	BTNA = 1'b1;
	#10
	BTNA = 1'b0;
	
	#10
	
	RST = 1'b0;
	BTNA = 1'b1;
	#10
	BTNA = 1'b0;
	
	#10
	
	RST = 1'b0;
	BTNC = 1'b1;
	#10
	BTNC = 1'b0;
	
	#10
	
	RST = 1'b0;
	BTND = 1'b1;
	#10
	BTND = 1'b0;
	
	#10
	
	RST = 1'b0;
	BTNE = 1'b1;
	#10
	BTNE = 1'b0;
	
	#10
	
	RST = 1'b0;
	BTNF = 1'b1;
	#10
	BTNF = 1'b0;
	
	#20;

end

endmodule