data/full_repos/permissive/450205124/Assignment3/Q2-parity-checker/A3Q2_parity_checker.v
1: b'%Error: data/full_repos/permissive/450205124/Assignment3/Q2-parity-checker/A3Q2_parity_checker.v:1: Cannot find include file: A3Q2_t_flip_flop.v\n`include "A3Q2_t_flip_flop.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/450205124/Assignment3/Q2-parity-checker,data/full_repos/permissive/450205124/A3Q2_t_flip_flop.v\n             data/full_repos/permissive/450205124/Assignment3/Q2-parity-checker,data/full_repos/permissive/450205124/A3Q2_t_flip_flop.v.v\n             data/full_repos/permissive/450205124/Assignment3/Q2-parity-checker,data/full_repos/permissive/450205124/A3Q2_t_flip_flop.v.sv\n             A3Q2_t_flip_flop.v\n             A3Q2_t_flip_flop.v.v\n             A3Q2_t_flip_flop.v.sv\n             obj_dir/A3Q2_t_flip_flop.v\n             obj_dir/A3Q2_t_flip_flop.v.v\n             obj_dir/A3Q2_t_flip_flop.v.sv\n%Error: Exiting due to 1 error(s)\n'
module parity_checker(out,seq,reset,clk);
	output reg out;
	input [2:0] seq;
	input reset;
	input clk;
	
	integer count=2;
	reg i;
	wire o;
	t_flip_flop T1(o,i,clk,reset);
	always @(negedge clk) begin
		i=seq[count];
		count=count-1;
		if(count==-1) begin
		  count=2;
		end
	end
	always @(posedge clk) begin
		out=o;
	end
endmodule
module parity_checker(out,seq,reset,clk);

	output reg out;
	input [2:0] seq;
	input reset;
	input clk;
	
	integer count=2;
	reg i;
	wire o;
	t_flip_flop T1(o,i,clk,reset);
	always @(negedge clk) begin
		i=seq[count];
		count=count-1;
		if(count==-1) begin
		  count=2;
		end
	end
	always @(posedge clk) begin
		out=o;
	end
endmodule