data/full_repos/permissive/425063934/custom_layout/sim/predecode_sdr_64.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/425063934/custom_layout/sim/predecode_sdr_64.v:48: Little bit endian vector: MSB < LSB of bit range: 0:5\n   input [0:5] address;\n         ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/425063934/custom_layout/sim/predecode_sdr_64.v:65: Little bit endian vector: MSB < LSB of bit range: 0:5\n   wire [0:5] inv_address;\n        ^\n%Error: Exiting due to 2 warning(s)\n'
module predecode_sdr_64(

    strobe,
    enable,
    address,
    

    c_na0,
    c_a0,
    na1_na2,
    na1_a2,
    a1_na2,
    a1_a2,
    na3,
    a3,
    na4_na5,
    na4_a5,
    a4_na5,
    a4_a5

);
     
   input       strobe;
   input 	enable; 
   input [0:5] address;
   
   output 	c_na0;
   output 	c_a0;
   output 	na1_na2;
   output 	na1_a2;
   output 	a1_na2;
   output 	a1_a2;
   output 	na3;
   output 	a3;
   output 	na4_na5;
   output 	na4_a5;
   output 	a4_na5;
   output 	a4_a5;

   wire clock_enable;
  
   wire [0:5] inv_address;
  
   wire n_c_na0;
   wire n_c_a0;
   wire n_na1_na2;
   wire n_na1_a2;
   wire n_a1_na2;
   wire n_a1_a2;
   wire n_na4_na5;
   wire n_na4_a5;
   wire n_a4_na5;
   wire n_a4_a5;
   



  assign clock_enable = strobe & enable;

   
  assign inv_address[0] = (~(address[0]));
  assign inv_address[1] = (~(address[1]));
  assign inv_address[2] = (~(address[2]));
  assign inv_address[3] = (~(address[3]));
  assign inv_address[4] = (~(address[4]));
  assign inv_address[5] = (~(address[5]));

   


  assign c_na0 = clock_enable & inv_address[0];
    
  assign c_a0 = clock_enable & address[0];
   
   

  
  assign na1_na2 = inv_address[1] & inv_address[2];
   		 
  assign na1_a2 = inv_address[1] & address[2];
  
  assign a1_na2 = address[1] & inv_address[2];
   
  assign a1_a2 = address[1] & address[2];

   


  assign na3 = inv_address[3];
  assign a3  = address[3];
   

  
  assign na4_na5 = inv_address[4] & inv_address[5];

  assign na4_a5 = inv_address[4] & address[5];
   
  assign a4_na5 = address[4] & inv_address[5];
  assign a4_a5 = address[4] & address[5];

endmodule
module predecode_sdr_64(

    strobe,
    enable,
    address,
    

    c_na0,
    c_a0,
    na1_na2,
    na1_a2,
    a1_na2,
    a1_a2,
    na3,
    a3,
    na4_na5,
    na4_a5,
    a4_na5,
    a4_a5

);

     
   input       strobe;
   input 	enable; 
   input [0:5] address;
   
   output 	c_na0;
   output 	c_a0;
   output 	na1_na2;
   output 	na1_a2;
   output 	a1_na2;
   output 	a1_a2;
   output 	na3;
   output 	a3;
   output 	na4_na5;
   output 	na4_a5;
   output 	a4_na5;
   output 	a4_a5;

   wire clock_enable;
  
   wire [0:5] inv_address;
  
   wire n_c_na0;
   wire n_c_a0;
   wire n_na1_na2;
   wire n_na1_a2;
   wire n_a1_na2;
   wire n_a1_a2;
   wire n_na4_na5;
   wire n_na4_a5;
   wire n_a4_na5;
   wire n_a4_a5;
   



  assign clock_enable = strobe & enable;

   
  assign inv_address[0] = (~(address[0]));
  assign inv_address[1] = (~(address[1]));
  assign inv_address[2] = (~(address[2]));
  assign inv_address[3] = (~(address[3]));
  assign inv_address[4] = (~(address[4]));
  assign inv_address[5] = (~(address[5]));

   


  assign c_na0 = clock_enable & inv_address[0];
    
  assign c_a0 = clock_enable & address[0];
   
   

  
  assign na1_na2 = inv_address[1] & inv_address[2];
   		 
  assign na1_a2 = inv_address[1] & address[2];
  
  assign a1_na2 = address[1] & inv_address[2];
   
  assign a1_a2 = address[1] & address[2];

   


  assign na3 = inv_address[3];
  assign a3  = address[3];
   

  
  assign na4_na5 = inv_address[4] & inv_address[5];

  assign na4_a5 = inv_address[4] & address[5];
   
  assign a4_na5 = address[4] & inv_address[5];
  assign a4_a5 = address[4] & address[5];

endmodule