data/full_repos/permissive/447976230/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/one_gige_phy.v
1: b"%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma/one_gige_phy.v:64: Cannot find file containing module: 'one_gig_eth_pcs_pma_support'\n   one_gig_eth_pcs_pma_support core_support_i (\n   ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma,data/full_repos/permissive/447976230/one_gig_eth_pcs_pma_support\n             data/full_repos/permissive/447976230/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma,data/full_repos/permissive/447976230/one_gig_eth_pcs_pma_support.v\n             data/full_repos/permissive/447976230/fpga/usrp3/top/e320/ip/one_gig_eth_pcs_pma,data/full_repos/permissive/447976230/one_gig_eth_pcs_pma_support.sv\n             one_gig_eth_pcs_pma_support\n             one_gig_eth_pcs_pma_support.v\n             one_gig_eth_pcs_pma_support.sv\n             obj_dir/one_gig_eth_pcs_pma_support\n             obj_dir/one_gig_eth_pcs_pma_support.v\n             obj_dir/one_gig_eth_pcs_pma_support.sv\n%Error: Exiting due to 1 error(s)\n"
module one_gige_phy
(
   input            independent_clock,



   input            gtrefclk,
   input            gtrefclk_bufg,
   output           txp,
   output           txn,
   input            rxp,
   input            rxn,



   output           gmii_clk,
   input [7:0]      gmii_txd,
   input            gmii_tx_en,
   input            gmii_tx_er,
   output reg [7:0] gmii_rxd,
   output reg       gmii_rx_dv,
   output reg       gmii_rx_er,



   input            mdc,
   input            mdio_i,
   output           mdio_o,
   output           mdio_t,
   input [4:0]      phyaddr,
   input [4:0]      configuration_vector,
   input            configuration_valid,



   output [15:0]    status_vector,
   input            reset,
   input            signal_detect
);

   wire         resetdone;
   wire         userclk;
   wire         userclk2;
   wire         rxuserclk2;
   wire         gmii_isolate;

   wire [7:0]   gmii_rxd_int;
   wire         gmii_rx_dv_int;
   wire         gmii_rx_er_int;

   always @(posedge gmii_clk) begin
      gmii_rxd    <= gmii_rxd_int;
      gmii_rx_dv  <= gmii_rx_dv_int;
      gmii_rx_er  <= gmii_rx_er_int;
   end




   one_gig_eth_pcs_pma_support core_support_i (
      .gtrefclk              (gtrefclk),
      .gtrefclk_bufg         (gtrefclk_bufg),
      .txp                   (txp),
      .txn                   (txn),
      .rxp                   (rxp),
      .rxn                   (rxn),
      .mmcm_locked_out       (),
      .userclk_out           (userclk),
      .userclk2_out          (userclk2),
      .rxuserclk_out         (),
      .rxuserclk2_out        (rxuserclk2),
      .independent_clock_bufg(independent_clock),
      .pma_reset_out         (),
      .resetdone             (resetdone),
      .gmii_txd              (gmii_txd),
      .gmii_tx_en            (gmii_tx_en),
      .gmii_tx_er            (gmii_tx_er),
      .gmii_rxd              (gmii_rxd_int),
      .gmii_rx_dv            (gmii_rx_dv_int),
      .gmii_rx_er            (gmii_rx_er_int),
      .gmii_isolate          (gmii_isolate),
      .mdc                   (mdc),
      .mdio_i                (mdio_i),
      .mdio_o                (mdio_o),
      .mdio_t                (mdio_t),
      .phyaddr               (phyaddr),
      .configuration_vector  (configuration_vector),
      .configuration_valid   (configuration_valid),
      .status_vector         (status_vector),
      .reset                 (reset),
      .signal_detect         (signal_detect),
      .gt0_qplloutclk_out    (),
      .gt0_qplloutrefclk_out ()
   );

   assign gmii_clk = userclk2;

endmodule
module one_gige_phy
(
   input            independent_clock,



   input            gtrefclk,
   input            gtrefclk_bufg,
   output           txp,
   output           txn,
   input            rxp,
   input            rxn,



   output           gmii_clk,
   input [7:0]      gmii_txd,
   input            gmii_tx_en,
   input            gmii_tx_er,
   output reg [7:0] gmii_rxd,
   output reg       gmii_rx_dv,
   output reg       gmii_rx_er,



   input            mdc,
   input            mdio_i,
   output           mdio_o,
   output           mdio_t,
   input [4:0]      phyaddr,
   input [4:0]      configuration_vector,
   input            configuration_valid,



   output [15:0]    status_vector,
   input            reset,
   input            signal_detect
);


   wire         resetdone;
   wire         userclk;
   wire         userclk2;
   wire         rxuserclk2;
   wire         gmii_isolate;

   wire [7:0]   gmii_rxd_int;
   wire         gmii_rx_dv_int;
   wire         gmii_rx_er_int;

   always @(posedge gmii_clk) begin
      gmii_rxd    <= gmii_rxd_int;
      gmii_rx_dv  <= gmii_rx_dv_int;
      gmii_rx_er  <= gmii_rx_er_int;
   end




   one_gig_eth_pcs_pma_support core_support_i (
      .gtrefclk              (gtrefclk),
      .gtrefclk_bufg         (gtrefclk_bufg),
      .txp                   (txp),
      .txn                   (txn),
      .rxp                   (rxp),
      .rxn                   (rxn),
      .mmcm_locked_out       (),
      .userclk_out           (userclk),
      .userclk2_out          (userclk2),
      .rxuserclk_out         (),
      .rxuserclk2_out        (rxuserclk2),
      .independent_clock_bufg(independent_clock),
      .pma_reset_out         (),
      .resetdone             (resetdone),
      .gmii_txd              (gmii_txd),
      .gmii_tx_en            (gmii_tx_en),
      .gmii_tx_er            (gmii_tx_er),
      .gmii_rxd              (gmii_rxd_int),
      .gmii_rx_dv            (gmii_rx_dv_int),
      .gmii_rx_er            (gmii_rx_er_int),
      .gmii_isolate          (gmii_isolate),
      .mdc                   (mdc),
      .mdio_i                (mdio_i),
      .mdio_o                (mdio_o),
      .mdio_t                (mdio_t),
      .phyaddr               (phyaddr),
      .configuration_vector  (configuration_vector),
      .configuration_valid   (configuration_valid),
      .status_vector         (status_vector),
      .reset                 (reset),
      .signal_detect         (signal_detect),
      .gt0_qplloutclk_out    (),
      .gt0_qplloutrefclk_out ()
   );

   assign gmii_clk = userclk2;

endmodule