data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_hz.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_hz.v:31: Cannot find file containing module: 'bw_clk_gclk_inv_224x'\nbw_clk_gclk_inv_224x x2 (\n^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_clk_gclk_inv_224x\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_clk_gclk_inv_224x.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_clk_gclk_inv_224x.sv\n             bw_clk_gclk_inv_224x\n             bw_clk_gclk_inv_224x.v\n             bw_clk_gclk_inv_224x.sv\n             obj_dir/bw_clk_gclk_inv_224x\n             obj_dir/bw_clk_gclk_inv_224x.v\n             obj_dir/bw_clk_gclk_inv_224x.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_hz.v:34: Cannot find file containing module: 'bw_clk_gclk_inv_224x'\nbw_clk_gclk_inv_224x x3 (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_hz.v:37: Cannot find file containing module: 'bw_clk_gclk_inv_192x'\nbw_clk_gclk_inv_192x x4 (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_hz.v:40: Cannot find file containing module: 'bw_clk_gclk_inv_224x'\nbw_clk_gclk_inv_224x x5 (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_hz.v:43: Cannot find file containing module: 'bw_clk_gclk_inv_288x'\nbw_clk_gclk_inv_288x x6 (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_hz.v:46: Cannot find file containing module: 'bw_clk_gclk_inv_224x'\nbw_clk_gclk_inv_224x x7 (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_hz.v:49: Cannot find file containing module: 'bw_clk_gclk_inv_288x'\nbw_clk_gclk_inv_288x x8 (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_hz.v:52: Cannot find file containing module: 'bw_clk_gclk_inv_224x'\nbw_clk_gclk_inv_224x x0 (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_hz.v:55: Cannot find file containing module: 'bw_clk_gclk_inv_192x'\nbw_clk_gclk_inv_192x x1 (\n^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n"
module bw_clk_gl_hz(ddr_center ,jbus_center ,cmp_center ,cmp_c11 ,
     jbus_c11 ,ddr_c11 );
output [3:0]	cmp_c11 ;
output [3:0]	jbus_c11 ;
output [3:0]	ddr_c11 ;
input		ddr_center ;
input		jbus_center ;
input		cmp_center ;
 
 
 
bw_clk_gl_hz1 xddr (
     .col_clk         ({ddr_c11 } ),
     .center_clk      (ddr_center ) );
bw_clk_gl_hz1 xjbus (
     .col_clk         ({jbus_c11 } ),
     .center_clk      (jbus_center ) );
bw_clk_gl_hz1 xcmp (
     .col_clk         ({cmp_c11 } ),
     .center_clk      (cmp_center ) );
endmodule
module bw_clk_gl_hz(ddr_center ,jbus_center ,cmp_center ,cmp_c11 ,
     jbus_c11 ,ddr_c11 );

output [3:0]	cmp_c11 ;
output [3:0]	jbus_c11 ;
output [3:0]	ddr_c11 ;
input		ddr_center ;
input		jbus_center ;
input		cmp_center ;
 
 
 
bw_clk_gl_hz1 xddr (
     .col_clk         ({ddr_c11 } ),
     .center_clk      (ddr_center ) );
bw_clk_gl_hz1 xjbus (
     .col_clk         ({jbus_c11 } ),
     .center_clk      (jbus_center ) );
bw_clk_gl_hz1 xcmp (
     .col_clk         ({cmp_c11 } ),
     .center_clk      (cmp_center ) );
endmodule