data/full_repos/permissive/418819021/lab-05/test_push.vh
1: b'%Error: data/full_repos/permissive/418819021/lab-05/test_push.vh:5: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418819021/lab-05,data/full_repos/permissive/418819021/defines.vh\n             data/full_repos/permissive/418819021/lab-05,data/full_repos/permissive/418819021/defines.vh.v\n             data/full_repos/permissive/418819021/lab-05,data/full_repos/permissive/418819021/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/418819021/lab-05/test_push.vh:7: Define or directive not defined: \'`STAGE_COUNT\'\n input [`STAGE_COUNT-1:0]       pipeline_stage;\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_push.vh:8: Define or directive not defined: \'`GROUP_COUNT\'\n input [`GROUP_COUNT-1:0]       opcode_group;\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_push.vh:9: Define or directive not defined: \'`OPCODE_COUNT\'\n input [`OPCODE_COUNT-1:0]      opcode_type;\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_push.vh:11: Define or directive not defined: \'`TEST_DATA_WIDTH\'\n input [`TEST_DATA_WIDTH-1:0]   writeback_value;\n        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_push.vh:12: Define or directive not defined: \'`SIGNAL_COUNT\'\n input [`SIGNAL_COUNT-1:0]      signals;\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_push.vh:13: Define or directive not defined: \'`TEST_R_ADDR_WIDTH\'\n input [`TEST_R_ADDR_WIDTH-1:0] rr_addr;\n        ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_push.vh:14: Define or directive not defined: \'`TEST_R_ADDR_WIDTH\'\n input [`TEST_R_ADDR_WIDTH-1:0] rd_addr;\n        ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_push.vh:15: Define or directive not defined: \'`TEST_DATA_WIDTH\'\n input [`TEST_DATA_WIDTH-1:0]   alu_rr;\n        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_push.vh:16: Define or directive not defined: \'`TEST_DATA_WIDTH\'\n input [`TEST_DATA_WIDTH-1:0]   alu_rd;\n        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_push.vh:17: Define or directive not defined: \'`TEST_DATA_WIDTH\'\n input [`TEST_DATA_WIDTH-1:0]   alu_out;\n        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_push.vh:18: Define or directive not defined: \'`TEST_D_ADDR_WIDTH\'\n input [`TEST_D_ADDR_WIDTH-1:0] bus_address;\n        ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_push.vh:25: Define or directive not defined: \'`STAGE_IF\'\n   `STAGE_IF:  TEST_PUSH = 1\'bx;\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_push.vh:25: syntax error, unexpected \':\', expecting endcase\n   `STAGE_IF:  TEST_PUSH = 1\'bx;\n            ^\n%Error: data/full_repos/permissive/418819021/lab-05/test_push.vh:26: Define or directive not defined: \'`STAGE_ID\'\n   `STAGE_ID:\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_push.vh:27: Define or directive not defined: \'`GROUP_STACK\'\n    if(opcode_group[`GROUP_STACK] &&\n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_push.vh:28: Define or directive not defined: \'`TYPE_PUSH\'\n     opcode_type == `TYPE_PUSH &&\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_push.vh:34: syntax error, unexpected else\n    else\n    ^~~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_push.vh:38: syntax error, unexpected end\n     end\n     ^~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_push.vh:39: Define or directive not defined: \'`STAGE_EX\'\n   `STAGE_EX:  TEST_PUSH = 1\'bx;\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_push.vh:40: Define or directive not defined: \'`STAGE_MEM\'\n   `STAGE_MEM: \n   ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_push.vh:45: syntax error, unexpected end\n     end\n     ^~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_push.vh:50: syntax error, unexpected end\n     end\n     ^~~\n%Error: data/full_repos/permissive/418819021/lab-05/test_push.vh:51: Define or directive not defined: \'`STAGE_WB\'\n   `STAGE_WB:  TEST_PUSH = 1\'bx;\n   ^~~~~~~~~\n%Error: Cannot continue\n'
function TEST_PUSH;
	input [`STAGE_COUNT-1:0]       pipeline_stage;
	input [`GROUP_COUNT-1:0]       opcode_group;
	input [`OPCODE_COUNT-1:0]      opcode_type;
	input [11:0]                   opcode_imd;
	input [`TEST_DATA_WIDTH-1:0]   writeback_value;
	input [`SIGNAL_COUNT-1:0]      signals;
	input [`TEST_R_ADDR_WIDTH-1:0] rr_addr;
	input [`TEST_R_ADDR_WIDTH-1:0] rd_addr;
	input [`TEST_DATA_WIDTH-1:0]   alu_rr;
	input [`TEST_DATA_WIDTH-1:0]   alu_rd;
	input [`TEST_DATA_WIDTH-1:0]   alu_out;
	input [`TEST_D_ADDR_WIDTH-1:0] bus_address;
	input integer address;
	input integer register_rr;
	input integer register_rd;
	input integer value;
	begin
		case (pipeline_stage)
			`STAGE_IF:  TEST_PUSH = 1'bx;
			`STAGE_ID:
				if(opcode_group[`GROUP_STACK] &&
					opcode_type == `TYPE_PUSH &&
					rr_addr == register_rr)
					begin
						TEST_PUSH = 1'b1;
						$display("PUSH R%2d - ID: OK", register_rr);
					end
				else
					begin
						TEST_PUSH = 1'bx;
						$display("PUSH R%2d - ID: FAILED", register_rr);
					end
			`STAGE_EX:  TEST_PUSH = 1'bx;
			`STAGE_MEM: 
				if (bus_address == address[7:0] - 8'h40)
					begin
						TEST_PUSH = 1'b1;
						$display("PUSH R%2d - MEM: OK (bus_address = %2H)", register_rr, bus_address);
					end
				else
					begin
						TEST_PUSH = 1'bx;
						$display("PUSH R%2d - MEM: FAILED => bus_address: (%2H) vs (%2H)", register_rr, address[7:0] - 8'h40, bus_address);
					end
			`STAGE_WB:  TEST_PUSH = 1'bx;
		endcase
	end
endfunction
function TEST_PUSH;

	input [`STAGE_COUNT-1:0]       pipeline_stage;
	input [`GROUP_COUNT-1:0]       opcode_group;
	input [`OPCODE_COUNT-1:0]      opcode_type;
	input [11:0]                   opcode_imd;
	input [`TEST_DATA_WIDTH-1:0]   writeback_value;
	input [`SIGNAL_COUNT-1:0]      signals;
	input [`TEST_R_ADDR_WIDTH-1:0] rr_addr;
	input [`TEST_R_ADDR_WIDTH-1:0] rd_addr;
	input [`TEST_DATA_WIDTH-1:0]   alu_rr;
	input [`TEST_DATA_WIDTH-1:0]   alu_rd;
	input [`TEST_DATA_WIDTH-1:0]   alu_out;
	input [`TEST_D_ADDR_WIDTH-1:0] bus_address;
	input integer address;
	input integer register_rr;
	input integer register_rd;
	input integer value;
	begin
		case (pipeline_stage)
			`STAGE_IF:  TEST_PUSH = 1'bx;
			`STAGE_ID:
				if(opcode_group[`GROUP_STACK] &&
					opcode_type == `TYPE_PUSH &&
					rr_addr == register_rr)
					begin
						TEST_PUSH = 1'b1;
						$display("PUSH R%2d - ID: OK", register_rr);
					end
				else
					begin
						TEST_PUSH = 1'bx;
						$display("PUSH R%2d - ID: FAILED", register_rr);
					end
			`STAGE_EX:  TEST_PUSH = 1'bx;
			`STAGE_MEM: 
				if (bus_address == address[7:0] - 8'h40)
					begin
						TEST_PUSH = 1'b1;
						$display("PUSH R%2d - MEM: OK (bus_address = %2H)", register_rr, bus_address);
					end
				else
					begin
						TEST_PUSH = 1'bx;
						$display("PUSH R%2d - MEM: FAILED => bus_address: (%2H) vs (%2H)", register_rr, address[7:0] - 8'h40, bus_address);
					end
			`STAGE_WB:  TEST_PUSH = 1'bx;
		endcase
	end
endfunction