data/full_repos/permissive/472097485/Chu01/G8ter4Bit_03/G8ter2.v
data/verilator_xmls/27f8a9bc-c696-401f-aa79-1fcd0269ff09.xml
module G8ter2( input [1:0] a, input [1:0] b, output g );

	assign g = ( a[0] & ~b[1] & ~b[0] ) | ( a[1] & ~ b[1] ) | ( a[1] & a[0] & ~b[0] );

endmodule
module G8ter2( input [1:0] a, input [1:0] b, output g );


	assign g = ( a[0] & ~b[1] & ~b[0] ) | ( a[1] & ~ b[1] ) | ( a[1] & a[0] & ~b[0] );

endmodule