data/full_repos/permissive/43264243/system.v
1: b'%Warning-WIDTH: data/full_repos/permissive/43264243/system.v:233: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'channel_cur\' generates 2 bits.\n                                                                : ... In instance system.ssc0\n     hexnybble <= channel_cur;\n               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/43264243/system.v:281: Operator EQ expects 4 bits on the LHS, but LHS\'s VARREF \'channel_cur\' generates 2 bits.\n                                                                : ... In instance system.ssc0\n      else if (channel_cur == 4\'b0011)\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/43264243/system.v:279: Operator EQ expects 4 bits on the LHS, but LHS\'s VARREF \'channel_cur\' generates 2 bits.\n                                                                : ... In instance system.ssc0\n      else if (channel_cur == 4\'b0010)\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/43264243/system.v:277: Operator EQ expects 4 bits on the LHS, but LHS\'s VARREF \'channel_cur\' generates 2 bits.\n                                                                : ... In instance system.ssc0\n      else if (channel_cur == 4\'b0001)\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/43264243/system.v:275: Operator EQ expects 4 bits on the LHS, but LHS\'s VARREF \'channel_cur\' generates 2 bits.\n                                                                : ... In instance system.ssc0\n      if(channel_cur == 4\'b0000)\n                     ^~\n%Error: data/full_repos/permissive/43264243/system.v:496: Cannot find file containing module: \'counter\'\n counter ctr63(\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43264243,data/full_repos/permissive/43264243/counter\n             data/full_repos/permissive/43264243,data/full_repos/permissive/43264243/counter.v\n             data/full_repos/permissive/43264243,data/full_repos/permissive/43264243/counter.sv\n             counter\n             counter.v\n             counter.sv\n             obj_dir/counter\n             obj_dir/counter.v\n             obj_dir/counter.sv\n%Error: data/full_repos/permissive/43264243/system.v:506: Cannot find file containing module: \'counter\'\n counter ctr2(\n ^~~~~~~\n%Error: data/full_repos/permissive/43264243/system.v:516: Cannot find file containing module: \'channel\'\n channel ch0(\n ^~~~~~~\n%Error: data/full_repos/permissive/43264243/system.v:533: Cannot find file containing module: \'channel\'\n channel ch1(\n ^~~~~~~\n%Error: data/full_repos/permissive/43264243/system.v:549: Cannot find file containing module: \'channel\'\n channel ch2(\n ^~~~~~~\n%Error: data/full_repos/permissive/43264243/system.v:564: Cannot find file containing module: \'channel\'\n channel ch3(\n ^~~~~~~\n%Error: data/full_repos/permissive/43264243/system.v:588: Cannot find file containing module: \'counter\'\n counter bc0(\n ^~~~~~~\n%Error: data/full_repos/permissive/43264243/system.v:657: Cannot find file containing module: \'utx\'\n utx utx0(\n ^~~\n%Error: Exiting due to 8 error(s), 5 warning(s)\n'
module channel_mux(ch0, ch1, ch2, ch3, channel, dataout);
	input [7:0] ch0;
	input [7:0] ch1;
	input [7:0] ch2;
	input [7:0] ch3;
	input [1:0] channel;
	output reg [7:0] dataout;
	
	always @(*) begin
		case(channel)
			0:
				dataout <= ch0;
				
			1:
				dataout <= ch1;
				
			2:
				dataout <= ch2;
			
			3:
				dataout <= ch3;
				
			default:
				dataout <= 0;
		endcase
	end
endmodule
module channel_mux(ch0, ch1, ch2, ch3, channel, dataout);

	input [7:0] ch0;
	input [7:0] ch1;
	input [7:0] ch2;
	input [7:0] ch3;
	input [1:0] channel;
	output reg [7:0] dataout;
	
	always @(*) begin
		case(channel)
			0:
				dataout <= ch0;
				
			1:
				dataout <= ch1;
				
			2:
				dataout <= ch2;
			
			3:
				dataout <= ch3;
				
			default:
				dataout <= 0;
		endcase
	end
endmodule