data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new/ALUOutR.v
data/verilator_xmls/c431b5a8-03ae-4a2a-b1b8-0068d6efd761.xml
module ALUOutR(
    input clk,
    input [31:0] ALUOutRIn,
    output reg [31:0] ALUOutROut
    );
    
    always@(posedge clk)begin
        ALUOutROut <= ALUOutRIn;
    end
endmodule
module ALUOutR(
    input clk,
    input [31:0] ALUOutRIn,
    output reg [31:0] ALUOutROut
    );

    
    always@(posedge clk)begin
        ALUOutROut <= ALUOutRIn;
    end
endmodule