data/full_repos/permissive/467394306/rtl/tb/pe_lin_tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/467394306/rtl/tb/pe_lin_tb.sv:12: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/467394306/rtl/tb/pe_lin_tb.sv:25: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("lin_tb.vcd");\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/467394306/rtl/tb/pe_lin_tb.sv:38: Unsupported: Ignoring delay on this delayed statement.\n  #25;\n  ^\n%Error: data/full_repos/permissive/467394306/rtl/tb/pe_lin_tb.sv:42: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/467394306/rtl/tb/pe_lin_tb.sv:48: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Error: data/full_repos/permissive/467394306/rtl/tb/pe_lin_tb.sv:53: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/467394306/rtl/tb/pe_lin_tb.sv:57: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, PE_TB);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/467394306/rtl/tb/pe_lin_tb.sv:58: Unsupported or unknown PLI call: $dumpall\n  $dumpall;\n  ^~~~~~~~\n%Error: data/full_repos/permissive/467394306/rtl/tb/pe_lin_tb.sv:59: Unsupported or unknown PLI call: $dumpflush\n  $dumpflush;\n  ^~~~~~~~~~\n%Error: Exiting due to 6 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module PE_TB;
	reg clk, rstn, fire;
	reg [7:0] w1, w2, w3, w4, a;
	wire [11:0] o1, o2, o3, o4;
	reg [7:0] cnt;

	integer i;

	always begin
		#10;
		clk = ~clk;
	end

	always @ (posedge clk) begin
		cnt <= cnt + 1'b1;
	end

	PE_Lin dut(clk, rstn, fire, 
		w1, w2, w3, w4, a,
		o1, o2, o3, o4);

	initial begin
		$dumpfile("lin_tb.vcd");
		clk <= 0;
		rstn <= 0;
		cnt <= 0;
		w1 <= 1;
		w2 <= 2;
		w3 <= 3;
		w4 <= 4;
		a <= 1;
		fire <= 1;

		$display("Initialized");

		#25;
		rstn <= 1;

		for (i=0; i<8; i=i+1) begin
			@(posedge clk);
			$display("i=%d\tout=%d,%d,%d,%d",i,o1,o2,o3,o4);

			a <= a + 1;
		end
		
		#5;
		a <= 0;
		fire <= 0;

		for (i=0; i<8; i=i+1) begin
			@(posedge clk);
			$display("i=%d\tout=%d,%d,%d,%d",i,o1,o2,o3,o4);
		end

		$dumpvars(0, PE_TB);
		$dumpall;
		$dumpflush;
		$finish;
	end
endmodule
module PE_TB;

	reg clk, rstn, fire;
	reg [7:0] w1, w2, w3, w4, a;
	wire [11:0] o1, o2, o3, o4;
	reg [7:0] cnt;

	integer i;

	always begin
		#10;
		clk = ~clk;
	end

	always @ (posedge clk) begin
		cnt <= cnt + 1'b1;
	end

	PE_Lin dut(clk, rstn, fire, 
		w1, w2, w3, w4, a,
		o1, o2, o3, o4);

	initial begin
		$dumpfile("lin_tb.vcd");
		clk <= 0;
		rstn <= 0;
		cnt <= 0;
		w1 <= 1;
		w2 <= 2;
		w3 <= 3;
		w4 <= 4;
		a <= 1;
		fire <= 1;

		$display("Initialized");

		#25;
		rstn <= 1;

		for (i=0; i<8; i=i+1) begin
			@(posedge clk);
			$display("i=%d\tout=%d,%d,%d,%d",i,o1,o2,o3,o4);

			a <= a + 1;
		end
		
		#5;
		a <= 0;
		fire <= 0;

		for (i=0; i<8; i=i+1) begin
			@(posedge clk);
			$display("i=%d\tout=%d,%d,%d,%d",i,o1,o2,o3,o4);
		end

		$dumpvars(0, PE_TB);
		$dumpall;
		$dumpflush;
		$finish;
	end
endmodule