data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:20: Cannot find include file: test_exec.svh\n  `include "test_exec.svh" \n           ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb,data/full_repos/permissive/447976230/test_exec.svh\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb,data/full_repos/permissive/447976230/test_exec.svh.v\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb,data/full_repos/permissive/447976230/test_exec.svh.sv\n             test_exec.svh\n             test_exec.svh.v\n             test_exec.svh.sv\n             obj_dir/test_exec.svh\n             obj_dir/test_exec.svh.v\n             obj_dir/test_exec.svh.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:21: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n  import PkgAxiStreamBfm::*;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:112: syntax error, unexpected \'=\', expecting \',\' or \';\'\n  TestExec test = new();\n                ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:113: syntax error, unexpected \'=\', expecting \',\' or \';\'\n  AxiStreamBfm #(.DATA_WIDTH(DATA_WIDTH),.USER_WIDTH(USER_WIDTH)) axi =\n                                                                      ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:122: syntax error, unexpected TIME NUMBER, expecting \')\'\n    test.start_test({TEST_NAME,"Wait for Reset"}, 10us);\n                                                  ^~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:123: Unsupported: wait statements\n    wait(!rst);\n    ^~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:124: syntax error, unexpected \'@\'\n    repeat (10) @(posedge clk);\n                ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:128: syntax error, unexpected \'#\', expecting \'.\' or \';\'\n  typedef AxiStreamPacket #(DATA_WIDTH,USER_WIDTH) AxisPacket_t;\n                          ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:129: syntax error, unexpected \'#\', expecting \'.\' or \';\'\n  typedef XportStreamPacket #(DATA_WIDTH) XportPacket_t;\n                            ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:142: syntax error, unexpected IDENTIFIER, expecting \')\'\n  task automatic send_lbus(AxisPacket_t packets[$]);\n                                        ^~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:149: syntax error, unexpected foreach\n    foreach(packets[i]) begin\n    ^~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:159: syntax error, unexpected \'[\', expecting IDENTIFIER\n           lbus_in[seg].eop = 1;\n                  ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:163: syntax error, unexpected \'@\'\n           @(posedge clk);\n           ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:168: syntax error, unexpected \'@\'\n             @(posedge clk);\n             ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:172: syntax error, unexpected \'=\', expecting IDENTIFIER\n         b = (b+1) % (SEG_DATA_WIDTH/8);\n           ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:174: syntax error, unexpected \'=\', expecting IDENTIFIER\n           seg = (seg+1) % NUM_SEG;\n               ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:180: syntax error, unexpected \'@\'\n          @(posedge clk);\n          ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:185: syntax error, unexpected \'@\'\n             @(posedge clk);\n             ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:189: syntax error, unexpected \'=\', expecting IDENTIFIER\n        b   = 0;\n            ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:193: Unsupported or unknown PLI call: $urandom_range\n      if ($urandom_range(99) < 25) begin\n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:197: Unsupported or unknown PLI call: $urandom_range\n        if ($urandom_range(99) < 25) begin\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:198: syntax error, unexpected \'@\'\n          @(posedge clk);\n          ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:203: syntax error, unexpected \'=\', expecting IDENTIFIER\n             idle_insert =0;\n                         ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:208: syntax error, unexpected \'@\'\n          @(posedge clk);\n          ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:213: syntax error, unexpected \'=\', expecting IDENTIFIER\n             idle_insert =0;\n                         ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:217: syntax error, unexpected end\n      end\n      ^~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:226: syntax error, unexpected IDENTIFIER, expecting \')\'\n  task automatic compare_packet(AxisPacket_t actual, expected);\n                                             ^~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:230: syntax error, unexpected \'(\', expecting IDENTIFIER\n    actual_copy.import_axis(actual);\n                            ^~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:231: syntax error, unexpected \'(\', expecting IDENTIFIER\n    expected_copy.import_axis(expected);\n                              ^~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:233: syntax error, unexpected \'(\', expecting IDENTIFIER\n    expected_copy.tkeep_to_tuser();\n                                 ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:234: syntax error, unexpected \'(\', expecting IDENTIFIER\n    actual_copy.clear_unused_bytes();\n                                   ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:237: syntax error, unexpected $display\n      $display("Expected");\n      ^~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:238: syntax error, unexpected \'(\', expecting IDENTIFIER\n      expected_copy.print();\n                          ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:240: syntax error, unexpected \'(\', expecting IDENTIFIER\n      actual_copy.print();\n                        ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:246: syntax error, unexpected endtask\n  endtask : compare_packet;\n  ^~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:249: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n    automatic AxisPacket_t send[$];\n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:253: syntax error, unexpected TIME NUMBER, expecting \')\'\n    test.start_test({TEST_NAME,"Test Transfer"}, 200us);\n                                                 ^~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:256: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n      automatic raw_pkt_t    pay;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:270: Unsupported: fork statements\n    fork\n    ^~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:276: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n          automatic AxisPacket_t  actual;\n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:329: Unsupported or unknown PLI call: $urandom_range\n     random_value = $urandom_range(64,512);\n                    ^~~~~~~~~~~~~~\n%Error: Internal Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/ip/eth_100g_bd/lbus_tb/lbus_axi_tb.sv:13: ../V3ParseSym.h:114: Symbols suggest ending TASK \'compare_packet\' but parser thinks ending MODULE \'lbus_axi_tb\'\nmodule lbus_axi_tb #(\n       ^~~~~~~~~~~\n'
module lbus_axi_tb #(
  parameter TEST_NAME  = ""
)(

);

  `define TEST_EXEC_OBJ test
  `include "test_exec.svh"
  import PkgAxiStreamBfm::*;
  import PkgEthernet::*;
  import PkgTestExec::*;
  import PkgEth100gLbus::*;

  localparam DATA_WIDTH      = 512;
  localparam USER_WIDTH      = $clog2(DATA_WIDTH/8)+1;
  localparam NUM_SEG         = 4;
  localparam SEG_DATA_WIDTH  = DATA_WIDTH/NUM_SEG;
  localparam SEG_BYTES      = SEG_DATA_WIDTH/8;




  logic clk;
  logic rst;

  sim_clock_gen #(.PERIOD(5), .AUTOSTART(1))
    clk_gen (.clk(clk), .rst(rst));




  AxiStreamIf #(.DATA_WIDTH(DATA_WIDTH),.USER_WIDTH(USER_WIDTH))
    axis    (clk, rst);

  AxiStreamIf #(.DATA_WIDTH(DATA_WIDTH),.USER_WIDTH(USER_WIDTH))
    axig    (clk, rst);




  lbus_t lbus_in [NUM_SEG-1:0];

  eth_100g_lbus2axi #(.FIFO_DEPTH(5),.NUM_SEG(NUM_SEG)) DUT (
    .axis(axis),
    .lbus_in(lbus_in)
  );













  TestExec test = new();
  AxiStreamBfm #(.DATA_WIDTH(DATA_WIDTH),.USER_WIDTH(USER_WIDTH)) axi =
    new(.slave(axis),.master(null));






  task test_reset();
    test.start_test({TEST_NAME,"Wait for Reset"}, 10us);
    wait(!rst);
    repeat (10) @(posedge clk);
    test.end_test();
  endtask : test_reset

  typedef AxiStreamPacket #(DATA_WIDTH,USER_WIDTH) AxisPacket_t;
  typedef XportStreamPacket #(DATA_WIDTH) XportPacket_t;

  task automatic clear_lbus_in();
    for (int i=0 ; i < NUM_SEG ; ++i) begin
      lbus_in[i].data = 'b0;
      lbus_in[i].mty  = 'b0;
      lbus_in[i].sop  = 1'b0;
      lbus_in[i].eop  = 1'b0;
      lbus_in[i].err  = 1'b0;
      lbus_in[i].ena  = 1'b0;
    end
  endtask : clear_lbus_in;

  task automatic send_lbus(AxisPacket_t packets[$]);

    int seg = 0;
    int b   = 0;
    int idle_insert = 0;


    foreach(packets[i]) begin
      automatic raw_pkt_t pay;
      pay = packets[i].dump_bytes;

      lbus_in[seg].sop = 1;

      while (pay.size() > 0) begin
         lbus_in[seg].ena = 1;
         lbus_in[seg].data |= pay.pop_front()<<(SEG_DATA_WIDTH-b*8-8);
         if (pay.size() == 0) begin
           lbus_in[seg].eop = 1;
           lbus_in[seg].mty = SEG_DATA_WIDTH-1-b;
         end
         if (seg == NUM_SEG-1 &&  b == SEG_DATA_WIDTH/8-1) begin
           @(posedge clk);
           clear_lbus_in();
           idle_insert++;

           if (idle_insert > 2) begin
             @(posedge clk);
             idle_insert =0;
           end
         end
         b = (b+1) % (SEG_DATA_WIDTH/8);
         if (b==0) begin
           seg = (seg+1) % NUM_SEG;
         end
      end
      if (b != 0) begin
        seg = (seg+1) % NUM_SEG;
        if (seg == 0) begin
          @(posedge clk);
          clear_lbus_in();
          idle_insert++;

           if (idle_insert > 2) begin
             @(posedge clk);
             idle_insert =0;
           end
        end
        b   = 0;
      end


      if ($urandom_range(99) < 25) begin
        b   = 0;
        seg = 0;

        if ($urandom_range(99) < 25) begin
          @(posedge clk);
          clear_lbus_in();
          idle_insert++;

           if (idle_insert > 2) begin
             idle_insert =0;
             @(posedge clk);
           end
          @(posedge clk);
        end else begin
          @(posedge clk);
          clear_lbus_in();
          idle_insert++;

           if (idle_insert > 2) begin
             idle_insert =0;
             @(posedge clk);
           end
        end
      end

    end

    @(posedge clk);
    clear_lbus_in();

  endtask : send_lbus;

  task automatic compare_packet(AxisPacket_t actual, expected);

    automatic XportPacket_t actual_copy = new();
    automatic XportPacket_t expected_copy = new();
    actual_copy.import_axis(actual);
    expected_copy.import_axis(expected);

    expected_copy.tkeep_to_tuser();
    actual_copy.clear_unused_bytes();

    if (!expected_copy.equal(actual_copy)) begin
      $display("Expected");
      expected_copy.print();
      $display("Actual");
      actual_copy.print();
      if (!expected_copy.equal(actual_copy))
        $error("ERROR :: packet mismatch");

    end

  endtask : compare_packet;

  task automatic test_transfers(int num_samples[$]);
    automatic AxisPacket_t send[$];
    automatic AxisPacket_t expected[$];
    automatic int sample_sum = 0;

    test.start_test({TEST_NAME,"Test Transfer"}, 200us);

    foreach (num_samples[i]) begin
      automatic raw_pkt_t    pay;

      expected[i] = new;
      send[i] = new;

      get_ramp_raw_pkt(.num_samps(num_samples[i]),.ramp_start((sample_sum)%256),
                       .ramp_inc(1),.pkt(pay),.SWIDTH(8));
      sample_sum += num_samples[i];
      send[i].push_bytes(pay);


      expected[i].push_bytes(pay);
    end

    fork
      begin
        send_lbus(send);
      end
      begin
        foreach(expected[i]) begin
          automatic AxisPacket_t  actual;
          axi.get(actual);
          compare_packet(actual,expected[i]);
        end
      end
    join

    test.end_test();
  endtask : test_transfers




  initial begin : tb_main
   automatic int num_samples[$];
   automatic int random_value;
   clk_gen.reset();



   axi.slave_tready_init = 1'b1;
   axi.set_master_stall_prob(0);
   axi.set_slave_stall_prob(0);
   axi.run();
   clear_lbus_in();
   test_reset();

   $display("Fixed Sequences");
   num_samples = {64,65,66,67,68,69,70,71};
   test_transfers(num_samples);
   num_samples = {64,128,256,512,256,64,64,64};
   test_transfers(num_samples);
   num_samples = {65,64,64,64,64,64,64,64};
   test_transfers(num_samples);
   num_samples = {65,64,80,80,80,80,80,80};
   test_transfers(num_samples);
   num_samples = {64,64,96,80,96,80,96,80};
   test_transfers(num_samples);
   $display("Tons of 64");
   num_samples.delete();
   repeat(1000) begin
     num_samples.push_back(64);
   end
   test_transfers(num_samples);
   $display("Tons of 65");
   num_samples.delete();
   repeat(1000) begin
     num_samples.push_back(65);
   end
   test_transfers(num_samples);
   $display("Tons of Random");
   num_samples.delete();
   repeat(1000) begin
     random_value = $urandom_range(64,512);
     num_samples.push_back(random_value);
   end
   test_transfers(num_samples);




   test.end_tb(0);


   clk_gen.kill();
  end

endmodule
module lbus_axi_tb #(
  parameter TEST_NAME  = ""
)(

);


  `define TEST_EXEC_OBJ test
  `include "test_exec.svh"
  import PkgAxiStreamBfm::*;
  import PkgEthernet::*;
  import PkgTestExec::*;
  import PkgEth100gLbus::*;

  localparam DATA_WIDTH      = 512;
  localparam USER_WIDTH      = $clog2(DATA_WIDTH/8)+1;
  localparam NUM_SEG         = 4;
  localparam SEG_DATA_WIDTH  = DATA_WIDTH/NUM_SEG;
  localparam SEG_BYTES      = SEG_DATA_WIDTH/8;




  logic clk;
  logic rst;

  sim_clock_gen #(.PERIOD(5), .AUTOSTART(1))
    clk_gen (.clk(clk), .rst(rst));




  AxiStreamIf #(.DATA_WIDTH(DATA_WIDTH),.USER_WIDTH(USER_WIDTH))
    axis    (clk, rst);

  AxiStreamIf #(.DATA_WIDTH(DATA_WIDTH),.USER_WIDTH(USER_WIDTH))
    axig    (clk, rst);




  lbus_t lbus_in [NUM_SEG-1:0];

  eth_100g_lbus2axi #(.FIFO_DEPTH(5),.NUM_SEG(NUM_SEG)) DUT (
    .axis(axis),
    .lbus_in(lbus_in)
  );













  TestExec test = new();
  AxiStreamBfm #(.DATA_WIDTH(DATA_WIDTH),.USER_WIDTH(USER_WIDTH)) axi =
    new(.slave(axis),.master(null));






  task test_reset();
    test.start_test({TEST_NAME,"Wait for Reset"}, 10us);
    wait(!rst);
    repeat (10) @(posedge clk);
    test.end_test();
  endtask : test_reset

  typedef AxiStreamPacket #(DATA_WIDTH,USER_WIDTH) AxisPacket_t;
  typedef XportStreamPacket #(DATA_WIDTH) XportPacket_t;

  task automatic clear_lbus_in();
    for (int i=0 ; i < NUM_SEG ; ++i) begin
      lbus_in[i].data = 'b0;
      lbus_in[i].mty  = 'b0;
      lbus_in[i].sop  = 1'b0;
      lbus_in[i].eop  = 1'b0;
      lbus_in[i].err  = 1'b0;
      lbus_in[i].ena  = 1'b0;
    end
  endtask : clear_lbus_in;

  task automatic send_lbus(AxisPacket_t packets[$]);

    int seg = 0;
    int b   = 0;
    int idle_insert = 0;


    foreach(packets[i]) begin
      automatic raw_pkt_t pay;
      pay = packets[i].dump_bytes;

      lbus_in[seg].sop = 1;

      while (pay.size() > 0) begin
         lbus_in[seg].ena = 1;
         lbus_in[seg].data |= pay.pop_front()<<(SEG_DATA_WIDTH-b*8-8);
         if (pay.size() == 0) begin
           lbus_in[seg].eop = 1;
           lbus_in[seg].mty = SEG_DATA_WIDTH-1-b;
         end
         if (seg == NUM_SEG-1 &&  b == SEG_DATA_WIDTH/8-1) begin
           @(posedge clk);
           clear_lbus_in();
           idle_insert++;

           if (idle_insert > 2) begin
             @(posedge clk);
             idle_insert =0;
           end
         end
         b = (b+1) % (SEG_DATA_WIDTH/8);
         if (b==0) begin
           seg = (seg+1) % NUM_SEG;
         end
      end
      if (b != 0) begin
        seg = (seg+1) % NUM_SEG;
        if (seg == 0) begin
          @(posedge clk);
          clear_lbus_in();
          idle_insert++;

           if (idle_insert > 2) begin
             @(posedge clk);
             idle_insert =0;
           end
        end
        b   = 0;
      end


      if ($urandom_range(99) < 25) begin
        b   = 0;
        seg = 0;

        if ($urandom_range(99) < 25) begin
          @(posedge clk);
          clear_lbus_in();
          idle_insert++;

           if (idle_insert > 2) begin
             idle_insert =0;
             @(posedge clk);
           end
          @(posedge clk);
        end else begin
          @(posedge clk);
          clear_lbus_in();
          idle_insert++;

           if (idle_insert > 2) begin
             idle_insert =0;
             @(posedge clk);
           end
        end
      end

    end

    @(posedge clk);
    clear_lbus_in();

  endtask : send_lbus;

  task automatic compare_packet(AxisPacket_t actual, expected);

    automatic XportPacket_t actual_copy = new();
    automatic XportPacket_t expected_copy = new();
    actual_copy.import_axis(actual);
    expected_copy.import_axis(expected);

    expected_copy.tkeep_to_tuser();
    actual_copy.clear_unused_bytes();

    if (!expected_copy.equal(actual_copy)) begin
      $display("Expected");
      expected_copy.print();
      $display("Actual");
      actual_copy.print();
      if (!expected_copy.equal(actual_copy))
        $error("ERROR :: packet mismatch");

    end

  endtask : compare_packet;

  task automatic test_transfers(int num_samples[$]);
    automatic AxisPacket_t send[$];
    automatic AxisPacket_t expected[$];
    automatic int sample_sum = 0;

    test.start_test({TEST_NAME,"Test Transfer"}, 200us);

    foreach (num_samples[i]) begin
      automatic raw_pkt_t    pay;

      expected[i] = new;
      send[i] = new;

      get_ramp_raw_pkt(.num_samps(num_samples[i]),.ramp_start((sample_sum)%256),
                       .ramp_inc(1),.pkt(pay),.SWIDTH(8));
      sample_sum += num_samples[i];
      send[i].push_bytes(pay);


      expected[i].push_bytes(pay);
    end

    fork
      begin
        send_lbus(send);
      end
      begin
        foreach(expected[i]) begin
          automatic AxisPacket_t  actual;
          axi.get(actual);
          compare_packet(actual,expected[i]);
        end
      end
    join

    test.end_test();
  endtask : test_transfers




  initial begin : tb_main
   automatic int num_samples[$];
   automatic int random_value;
   clk_gen.reset();



   axi.slave_tready_init = 1'b1;
   axi.set_master_stall_prob(0);
   axi.set_slave_stall_prob(0);
   axi.run();
   clear_lbus_in();
   test_reset();

   $display("Fixed Sequences");
   num_samples = {64,65,66,67,68,69,70,71};
   test_transfers(num_samples);
   num_samples = {64,128,256,512,256,64,64,64};
   test_transfers(num_samples);
   num_samples = {65,64,64,64,64,64,64,64};
   test_transfers(num_samples);
   num_samples = {65,64,80,80,80,80,80,80};
   test_transfers(num_samples);
   num_samples = {64,64,96,80,96,80,96,80};
   test_transfers(num_samples);
   $display("Tons of 64");
   num_samples.delete();
   repeat(1000) begin
     num_samples.push_back(64);
   end
   test_transfers(num_samples);
   $display("Tons of 65");
   num_samples.delete();
   repeat(1000) begin
     num_samples.push_back(65);
   end
   test_transfers(num_samples);
   $display("Tons of Random");
   num_samples.delete();
   repeat(1000) begin
     random_value = $urandom_range(64,512);
     num_samples.push_back(random_value);
   end
   test_transfers(num_samples);




   test.end_tb(0);


   clk_gen.kill();
  end

endmodule