data/full_repos/permissive/458047849/SevenSegmentDataflow.v
data/verilator_xmls/4ee3bcdf-aea3-4b93-986a-dbc84af46fac.xml
module SevenSegment(W, X, Y, Z, A, B, C, D, E, F, G);
input W, X, Y, Z;
output A, B, C, D, E, F, G;



assign #8 A = ~X & ~Z | W | Y | X & Z;
assign #8 B = ~Y & ~Z | Y & Z | ~X;
assign #8 C = X | Z | ~Y;
assign #8 D = ~W & ~X & ~Z | X & ~Y & Z | Y & ~Z | W;
assign #8 E = ~Z;
assign #8 F = ~Y & ~Z | X & ~Z | X & ~Y | W;
assign #8 G = ~X & Y | X & ~Z | X & ~Y | W;
endmodule
module SevenSegment(W, X, Y, Z, A, B, C, D, E, F, G);

input W, X, Y, Z;
output A, B, C, D, E, F, G;



assign #8 A = ~X & ~Z | W | Y | X & Z;
assign #8 B = ~Y & ~Z | Y & Z | ~X;
assign #8 C = X | Z | ~Y;
assign #8 D = ~W & ~X & ~Z | X & ~Y & Z | Y & ~Z | W;
assign #8 E = ~Z;
assign #8 F = ~Y & ~Z | X & ~Z | X & ~Y | W;
assign #8 G = ~X & Y | X & ~Z | X & ~Y | W;
endmodule