data/full_repos/permissive/455421905/src/even_odd.v
1: b"%Error: data/full_repos/permissive/455421905/src/even_odd.v:80: Cannot find file containing module: 'COMPARATOR'\n  COMPARATOR #(FLOAT, SIGNED, KEYW)\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/COMPARATOR\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/COMPARATOR.v\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/COMPARATOR.sv\n             COMPARATOR\n             COMPARATOR.v\n             COMPARATOR.sv\n             obj_dir/COMPARATOR\n             obj_dir/COMPARATOR.v\n             obj_dir/COMPARATOR.sv\n%Error: Exiting due to 1 error(s)\n"
module EVEN_ODD #(parameter                       P_LOG = 4,
                  parameter                       FLOAT  = "no",
                  parameter                       SIGNED = "no",
                  parameter                       DATW  = 64,
                  parameter                       KEYW  = 32)
                 (input  wire                     CLK,
                  input  wire                     RST,
                  input  wire [(DATW<<P_LOG)-1:0] DIN,
                  input  wire                     DINEN,
                  output wire [(DATW<<P_LOG)-1:0] DOT,
                  output wire                     DOTEN);




  reg [(DATW<<P_LOG)-1:0] din;   always @(posedge CLK) din   <= DIN;
  reg                     dinen; always @(posedge CLK) dinen <= (RST) ? 0 : DINEN;




  reg pc [(P_LOG*(P_LOG+1))-1:0];

  genvar i, j;
  generate
    for (i=0; i<P_LOG; i=i+1) begin: level
      wire [(DATW<<P_LOG)-1:0] box_din;
      wire [(DATW<<P_LOG)-1:0] box_dot;
      for (j=0; j<(1<<(P_LOG-(i+1))); j=j+1) begin: boxes
        BOX #((i+1), FLOAT, SIGNED, DATW, KEYW)
        box(CLK, box_din[DATW*(1<<(i+1))*(j+1)-1:DATW*(1<<(i+1))*j], box_dot[DATW*(1<<(i+1))*(j+1)-1:DATW*(1<<(i+1))*j]);
      end
    end
  endgenerate

  generate
    for (i=0; i<P_LOG; i=i+1) begin: connection
      if (i == 0) assign level[i].box_din = din;
      else        assign level[i].box_din = level[i-1].box_dot;
    end
  endgenerate

  integer p;
  always @(posedge CLK) begin
    if (RST) begin
      for (p=0; p<(P_LOG*(P_LOG+1)); p=p+1) pc[p] <= 0;
    end else begin
      pc[0] <= dinen;
      for (p=1; p<(P_LOG*(P_LOG+1)); p=p+1) pc[p] <= pc[p-1];
    end
  end




  assign DOT   = level[P_LOG-1].box_dot;
  assign DOTEN = pc[(P_LOG*(P_LOG+1))-1];

endmodule
module EVEN_ODD #(parameter                       P_LOG = 4,
                  parameter                       FLOAT  = "no",
                  parameter                       SIGNED = "no",
                  parameter                       DATW  = 64,
                  parameter                       KEYW  = 32)
                 (input  wire                     CLK,
                  input  wire                     RST,
                  input  wire [(DATW<<P_LOG)-1:0] DIN,
                  input  wire                     DINEN,
                  output wire [(DATW<<P_LOG)-1:0] DOT,
                  output wire                     DOTEN);





  reg [(DATW<<P_LOG)-1:0] din;   always @(posedge CLK) din   <= DIN;
  reg                     dinen; always @(posedge CLK) dinen <= (RST) ? 0 : DINEN;




  reg pc [(P_LOG*(P_LOG+1))-1:0];

  genvar i, j;
  generate
    for (i=0; i<P_LOG; i=i+1) begin: level
      wire [(DATW<<P_LOG)-1:0] box_din;
      wire [(DATW<<P_LOG)-1:0] box_dot;
      for (j=0; j<(1<<(P_LOG-(i+1))); j=j+1) begin: boxes
        BOX #((i+1), FLOAT, SIGNED, DATW, KEYW)
        box(CLK, box_din[DATW*(1<<(i+1))*(j+1)-1:DATW*(1<<(i+1))*j], box_dot[DATW*(1<<(i+1))*(j+1)-1:DATW*(1<<(i+1))*j]);
      end
    end
  endgenerate

  generate
    for (i=0; i<P_LOG; i=i+1) begin: connection
      if (i == 0) assign level[i].box_din = din;
      else        assign level[i].box_din = level[i-1].box_dot;
    end
  endgenerate

  integer p;
  always @(posedge CLK) begin
    if (RST) begin
      for (p=0; p<(P_LOG*(P_LOG+1)); p=p+1) pc[p] <= 0;
    end else begin
      pc[0] <= dinen;
      for (p=1; p<(P_LOG*(P_LOG+1)); p=p+1) pc[p] <= pc[p-1];
    end
  end




  assign DOT   = level[P_LOG-1].box_dot;
  assign DOTEN = pc[(P_LOG*(P_LOG+1))-1];

endmodule