data/full_repos/permissive/449807379/CPU_design/memory_control_with_RAM.v
1: b"%Error: data/full_repos/permissive/449807379/CPU_design/memory_control_with_RAM.v:16: Cannot find file containing module: 'memory_control'\nmemory_control mem_c1(source1, source2, alu_result, opcode, str_ldr_address, rw, datain, dataout, en, LDR_sel, address_sel);\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/449807379/CPU_design,data/full_repos/permissive/449807379/memory_control\n             data/full_repos/permissive/449807379/CPU_design,data/full_repos/permissive/449807379/memory_control.v\n             data/full_repos/permissive/449807379/CPU_design,data/full_repos/permissive/449807379/memory_control.sv\n             memory_control\n             memory_control.v\n             memory_control.sv\n             obj_dir/memory_control\n             obj_dir/memory_control.v\n             obj_dir/memory_control.sv\n%Error: data/full_repos/permissive/449807379/CPU_design/memory_control_with_RAM.v:18: Cannot find file containing module: 'mux_2x1_16bit'\nmux_2x1_16bit address_bus_mux( address_sel, address, str_ldr_address, pc_instruction);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/449807379/CPU_design/memory_control_with_RAM.v:22: Cannot find file containing module: 'RAM'\nRAM ram1(en, rw, address, dataout, datain);  \n^~~\n%Error: data/full_repos/permissive/449807379/CPU_design/memory_control_with_RAM.v:25: Cannot find file containing module: 'RAM'\nRAM ram2(en, 1'b1, pc_instruction, dataout, instruction);\n^~~\n%Error: Exiting due to 4 error(s)\n"
module memory_control_with_RAM(source1, source2, alu_result, opcode, register_data, pc_instruction, instruction);

input [31:0] source1, source2, alu_result;
input [3:0] opcode;
input [15:0] pc_instruction;

wire [31:0] dataout, datain;
wire rw;
wire en;
wire [15:0] address, str_ldr_address;
wire LDR_sel, address_sel;

output [31:0] register_data;
output [31:0] instruction;

memory_control mem_c1(source1, source2, alu_result, opcode, str_ldr_address, rw, datain, dataout, en, LDR_sel, address_sel);

mux_2x1_16bit address_bus_mux( address_sel, address, str_ldr_address, pc_instruction);



RAM ram1(en, rw, address, dataout, datain);


RAM ram2(en, 1'b1, pc_instruction, dataout, instruction);




assign register_data = (LDR_sel) ? (datain) : (alu_result);

endmodule
module memory_control_with_RAM(source1, source2, alu_result, opcode, register_data, pc_instruction, instruction);


input [31:0] source1, source2, alu_result;
input [3:0] opcode;
input [15:0] pc_instruction;

wire [31:0] dataout, datain;
wire rw;
wire en;
wire [15:0] address, str_ldr_address;
wire LDR_sel, address_sel;

output [31:0] register_data;
output [31:0] instruction;

memory_control mem_c1(source1, source2, alu_result, opcode, str_ldr_address, rw, datain, dataout, en, LDR_sel, address_sel);

mux_2x1_16bit address_bus_mux( address_sel, address, str_ldr_address, pc_instruction);



RAM ram1(en, rw, address, dataout, datain);


RAM ram2(en, 1'b1, pc_instruction, dataout, instruction);




assign register_data = (LDR_sel) ? (datain) : (alu_result);

endmodule