data/full_repos/permissive/488490114/ANODE_COUNTER.v
data/verilator_xmls/68af1045-23b0-4fbc-9ea5-d06ec0ebde09.xml
module ANODE_COUNTER(
    input CE,
    input CLK,
    input RST,
    output reg [2:0]CNT
);

always @ (posedge CLK)
begin
	if(RST) 
		CNT <= 0;
	else if(CE) 
		CNT <= CNT + 1'b1;
	else if (CNT == 3'b110)
		CNT <= 0;
end

endmodule
module ANODE_COUNTER(
    input CE,
    input CLK,
    input RST,
    output reg [2:0]CNT
);


always @ (posedge CLK)
begin
	if(RST) 
		CNT <= 0;
	else if(CE) 
		CNT <= CNT + 1'b1;
	else if (CNT == 3'b110)
		CNT <= 0;
end

endmodule