data/full_repos/permissive/502135797/Lab8_April_20_2022/Code/BSUPDOWN_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab8_April_20_2022/Code/BSUPDOWN_TB.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk_tb = ~clk_tb;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/502135797/Lab8_April_20_2022/Code/BSUPDOWN_TB.v:7: Cannot find file containing module: \'BSUPDOWN\'\n    BSUPDOWN COMP (\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502135797/Lab8_April_20_2022/Code,data/full_repos/permissive/502135797/BSUPDOWN\n             data/full_repos/permissive/502135797/Lab8_April_20_2022/Code,data/full_repos/permissive/502135797/BSUPDOWN.v\n             data/full_repos/permissive/502135797/Lab8_April_20_2022/Code,data/full_repos/permissive/502135797/BSUPDOWN.sv\n             BSUPDOWN\n             BSUPDOWN.v\n             BSUPDOWN.sv\n             obj_dir/BSUPDOWN\n             obj_dir/BSUPDOWN.v\n             obj_dir/BSUPDOWN.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module BSUPDOWN_TB(
    );
    reg clk_tb;
    wire [1:0] s0_tb; 
    wire [1:0] s1_tb;   
    BSUPDOWN COMP (
    .clk1(clk_tb),
    .s0(s0_tb),
    .s1(sl_tb)
    );    
    initial 
        begin
        clk_tb = 0;
        end        
    always   
        begin
        #5 clk_tb = ~clk_tb;
        end        
  
endmodule
module BSUPDOWN_TB(
    );

    reg clk_tb;
    wire [1:0] s0_tb; 
    wire [1:0] s1_tb;   
    BSUPDOWN COMP (
    .clk1(clk_tb),
    .s0(s0_tb),
    .s1(sl_tb)
    );    
    initial 
        begin
        clk_tb = 0;
        end        
    always   
        begin
        #5 clk_tb = ~clk_tb;
        end        
  
endmodule