data/full_repos/permissive/523038000/lab1/4.Decoer_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/523038000/lab1/4.Decoer_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/523038000/lab1/4.Decoer_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/523038000/lab1/4.Decoer_tb.v:19: Cannot find file containing module: \'Decoder\'\n Decoder uut (\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/523038000/lab1,data/full_repos/permissive/523038000/Decoder\n             data/full_repos/permissive/523038000/lab1,data/full_repos/permissive/523038000/Decoder.v\n             data/full_repos/permissive/523038000/lab1,data/full_repos/permissive/523038000/Decoder.sv\n             Decoder\n             Decoder.v\n             Decoder.sv\n             obj_dir/Decoder\n             obj_dir/Decoder.v\n             obj_dir/Decoder.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TestModule;


	reg a;
	reg b;
	reg c;


	wire d0;
	wire d1;
	wire d2;
	wire d3;
	wire d4;
	wire d5;
	wire d6;
	wire d7;


	Decoder uut (
		.a(a), 
		.b(b), 
		.c(c), 
		.d0(d0), 
		.d1(d1), 
		.d2(d2), 
		.d3(d3), 
		.d4(d4), 
		.d5(d5), 
		.d6(d6), 
		.d7(d7)
	);

	initial begin

		a = 0;
		b = 0;
		c = 0;


		#100;
        
		a = 1;
		b = 0;
		c = 1;


		#100;

	end
      
endmodule
module TestModule;



	reg a;
	reg b;
	reg c;


	wire d0;
	wire d1;
	wire d2;
	wire d3;
	wire d4;
	wire d5;
	wire d6;
	wire d7;


	Decoder uut (
		.a(a), 
		.b(b), 
		.c(c), 
		.d0(d0), 
		.d1(d1), 
		.d2(d2), 
		.d3(d3), 
		.d4(d4), 
		.d5(d5), 
		.d6(d6), 
		.d7(d7)
	);

	initial begin

		a = 0;
		b = 0;
		c = 0;


		#100;
        
		a = 1;
		b = 0;
		c = 1;


		#100;

	end
      
endmodule