data/full_repos/permissive/523236004/vrased/hw-mod/casu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/523236004/vrased/hw-mod/casu.v:53: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'KILL\' generates 2 bits.\n                                                                            : ... In instance casu\n        state = KILL;\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/523236004/vrased/hw-mod/casu.v:77: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'KILL\' generates 2 bits.\n                                                                            : ... In instance casu\n    state <= KILL;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/523236004/vrased/hw-mod/casu.v:79: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'RUN\' generates 2 bits.\n                                                                            : ... In instance casu\n    state <= RUN;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/523236004/vrased/hw-mod/casu.v:78: Operator EQ expects 2 bits on the LHS, but LHS\'s VARREF \'state\' generates 1 bits.\n                                                                            : ... In instance casu\nelse if (state == KILL && pc_reset && !violation)\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/523236004/vrased/hw-mod/casu.v:76: Operator EQ expects 2 bits on the LHS, but LHS\'s VARREF \'state\' generates 1 bits.\n                                                                            : ... In instance casu\nif( state == RUN && violation )\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/523236004/vrased/hw-mod/casu.v:89: Operator EQ expects 2 bits on the LHS, but LHS\'s VARREF \'state\' generates 1 bits.\n                                                                            : ... In instance casu\nelse if (state == RUN)\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/523236004/vrased/hw-mod/casu.v:87: Operator EQ expects 2 bits on the LHS, but LHS\'s VARREF \'state\' generates 1 bits.\n                                                                            : ... In instance casu\nelse if (state == KILL)\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/523236004/vrased/hw-mod/casu.v:85: Operator EQ expects 2 bits on the LHS, but LHS\'s VARREF \'state\' generates 1 bits.\n                                                                            : ... In instance casu\nelse if (state == KILL && pc_reset && !violation)\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/523236004/vrased/hw-mod/casu.v:83: Operator EQ expects 2 bits on the LHS, but LHS\'s VARREF \'state\' generates 1 bits.\n                                                                            : ... In instance casu\nif (state == RUN && violation )\n          ^~\n%Error: Exiting due to 9 warning(s)\n'
module casu (
    clk,
    
    pc,
    
    data_wr,
    data_addr,
    
    dma_addr,
    dma_en,

    ER_min,
    ER_max,
    
    reset
);


input           clk;
input   [15:0]  pc;
input           data_wr;
input   [15:0]  data_addr;
input   [15:0]  dma_addr;
input           dma_en;
input   [15:0]  ER_min;
input   [15:0]  ER_max;
output          reset;



parameter SMEM_BASE = 16'hA000;
parameter SMEM_SIZE = 16'h4000;

parameter SCACHE_BASE  = 16'hFFDF;
parameter SCACHE_SIZE  = 16'h0033;

parameter EP_BASE  = 16'h0140;
parameter EP_SIZE  = 16'h0003;

parameter RESET_HANDLER = 16'h0000;


parameter RUN  = 2'b0, KILL = 2'b1;


reg             state;
reg             casu_reset;



initial
    begin
        state = KILL;
        casu_reset = 0;
    end

wire pc_reset = pc == RESET_HANDLER;
wire pc_in_casu = (pc >= SMEM_BASE && pc <= SMEM_BASE + SMEM_SIZE - 2);
wire pc_in_ER = (pc >= ER_min && pc <= ER_max);
wire invalid_modifications_CPU = data_wr && ((data_addr >= ER_min && data_addr <= ER_max) 
                                     || (data_addr >= SCACHE_BASE && data_addr <= SCACHE_BASE + SCACHE_SIZE - 2) 
                                     || (data_addr >= EP_BASE && data_addr <= EP_BASE + EP_SIZE - 2));
wire invalid_modifications_DMA = dma_en && ((dma_addr >= ER_min && dma_addr <= ER_max) 
                                     || (dma_addr >= SCACHE_BASE && dma_addr <= SCACHE_BASE + SCACHE_SIZE - 2) 
                                     || (dma_addr >= EP_BASE && dma_addr <= EP_BASE + EP_SIZE - 2));


wire violation1 = (!pc_in_casu && invalid_modifications_CPU) || invalid_modifications_DMA;


wire violation2 = !pc_in_casu && !pc_in_ER && !pc_reset;

wire violation = violation1 || violation2;

always @(posedge clk)
if( state == RUN && violation )
    state <= KILL;
else if (state == KILL && pc_reset && !violation)
    state <= RUN;
else state <= state;
    
always @(posedge clk)
if (state == RUN && violation )
    casu_reset <= 1'b1;
else if (state == KILL && pc_reset && !violation)
    casu_reset <= 1'b0;
else if (state == KILL)
    casu_reset <= 1'b1;
else if (state == RUN)
    casu_reset <= 1'b0;
else casu_reset <= 1'b0;
        
assign reset = casu_reset;

endmodule
module casu (
    clk,
    
    pc,
    
    data_wr,
    data_addr,
    
    dma_addr,
    dma_en,

    ER_min,
    ER_max,
    
    reset
);



input           clk;
input   [15:0]  pc;
input           data_wr;
input   [15:0]  data_addr;
input   [15:0]  dma_addr;
input           dma_en;
input   [15:0]  ER_min;
input   [15:0]  ER_max;
output          reset;



parameter SMEM_BASE = 16'hA000;
parameter SMEM_SIZE = 16'h4000;

parameter SCACHE_BASE  = 16'hFFDF;
parameter SCACHE_SIZE  = 16'h0033;

parameter EP_BASE  = 16'h0140;
parameter EP_SIZE  = 16'h0003;

parameter RESET_HANDLER = 16'h0000;


parameter RUN  = 2'b0, KILL = 2'b1;


reg             state;
reg             casu_reset;



initial
    begin
        state = KILL;
        casu_reset = 0;
    end

wire pc_reset = pc == RESET_HANDLER;
wire pc_in_casu = (pc >= SMEM_BASE && pc <= SMEM_BASE + SMEM_SIZE - 2);
wire pc_in_ER = (pc >= ER_min && pc <= ER_max);
wire invalid_modifications_CPU = data_wr && ((data_addr >= ER_min && data_addr <= ER_max) 
                                     || (data_addr >= SCACHE_BASE && data_addr <= SCACHE_BASE + SCACHE_SIZE - 2) 
                                     || (data_addr >= EP_BASE && data_addr <= EP_BASE + EP_SIZE - 2));
wire invalid_modifications_DMA = dma_en && ((dma_addr >= ER_min && dma_addr <= ER_max) 
                                     || (dma_addr >= SCACHE_BASE && dma_addr <= SCACHE_BASE + SCACHE_SIZE - 2) 
                                     || (dma_addr >= EP_BASE && dma_addr <= EP_BASE + EP_SIZE - 2));


wire violation1 = (!pc_in_casu && invalid_modifications_CPU) || invalid_modifications_DMA;


wire violation2 = !pc_in_casu && !pc_in_ER && !pc_reset;

wire violation = violation1 || violation2;

always @(posedge clk)
if( state == RUN && violation )
    state <= KILL;
else if (state == KILL && pc_reset && !violation)
    state <= RUN;
else state <= state;
    
always @(posedge clk)
if (state == RUN && violation )
    casu_reset <= 1'b1;
else if (state == KILL && pc_reset && !violation)
    casu_reset <= 1'b0;
else if (state == KILL)
    casu_reset <= 1'b1;
else if (state == RUN)
    casu_reset <= 1'b0;
else casu_reset <= 1'b0;
        
assign reset = casu_reset;

endmodule