data/full_repos/permissive/456771003/rv_core.v
1: b'%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:372: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 20 bits.\n                                                                  : ... In instance rv_core.decode_inst\n    assign imm_31_12   = op[31:12];\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:390: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                  : ... In instance rv_core.decode_inst\n        fmt = \'bx;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d1:  fmt = 3\'d4; \n                       ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d2:  fmt = 3\'d4; \n                       ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h5\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d3:  fmt = 3\'d5; \n                       ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d4:  fmt = 3\'d1; \n                       ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h3\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d5:  fmt = 3\'d3; \n                       ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h3\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d6:  fmt = 3\'d3; \n                       ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h3\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d7:  fmt = 3\'d3; \n                       ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h3\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d8:  fmt = 3\'d3; \n                       ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h3\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d9:  fmt = 3\'d3; \n                       ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h3\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d10:  fmt = 3\'d3; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d11:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d12:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d13:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d14:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d15:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h2\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d16:  fmt = 3\'d2; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h2\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d17:  fmt = 3\'d2; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h2\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d18:  fmt = 3\'d2; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d19:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d20:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d21:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d22:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d23:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d24:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d25:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d26:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d27:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d28:  fmt = 3\'d0; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d29:  fmt = 3\'d0; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d30:  fmt = 3\'d0; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d31:  fmt = 3\'d0; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d32:  fmt = 3\'d0; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d33:  fmt = 3\'d0; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d34:  fmt = 3\'d0; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d35:  fmt = 3\'d0; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d36:  fmt = 3\'d0; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d37:  fmt = 3\'d0; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d38:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d39:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d40:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d41:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d42:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d43:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d44:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d45:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d46:  fmt = 3\'d1; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:394: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            6\'d47:  fmt = 3\'d1;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:406: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 22 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            3\'d4: imm = {imm_31_12, 12\'b0};\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:407: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 40 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            3\'d5: imm = {{19{imm_20}}, imm_20, imm_19_12, imm_11_a20, imm_10_1, 1\'b0};\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:402: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h1\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n        case (fmt)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:402: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h2\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n        case (fmt)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:402: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h3\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n        case (fmt)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:402: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h4\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n        case (fmt)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:402: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h5\' generates 3 bits.\n                                                                  : ... In instance rv_core.decode_inst\n        case (fmt)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:473: Operator ASSIGN expects 15 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 16 bits.\n                                                                  : ... In instance rv_core.decode_inst\n            default:        decode_out = {5\'bx,     2\'bx,      2\'bx,      1\'b0, 2\'bx,        2\'d0,  1\'b0, 1\'b0};\n                                       ^\n%Error: data/full_repos/permissive/456771003/rv_core.v:196: Cannot find file containing module: \'ff_ar\'\n    ff_ar #(.RESET_VAL(1\'d0)) state_ff(.clk(clk), .rst(rst), .d(state_n), .q(state_q));\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/456771003,data/full_repos/permissive/456771003/ff_ar\n             data/full_repos/permissive/456771003,data/full_repos/permissive/456771003/ff_ar.v\n             data/full_repos/permissive/456771003,data/full_repos/permissive/456771003/ff_ar.sv\n             ff_ar\n             ff_ar.v\n             ff_ar.sv\n             obj_dir/ff_ar\n             obj_dir/ff_ar.v\n             obj_dir/ff_ar.sv\n%Error: data/full_repos/permissive/456771003/rv_core.v:200: Cannot find file containing module: \'ff_ar\'\n    ff_ar #(.W(32)) pc(.clk(clk), .rst(rst), .d(pc_n), .q(pc_q));\n    ^~~~~\n%Error: data/full_repos/permissive/456771003/rv_core.v:203: Cannot find file containing module: \'ff_ar\'\n    ff_ar rf_write_ff(.clk(clk), .rst(rst), .d(rf_write_n && (state_q == 1\'d0)), .q(rf_write_q));\n    ^~~~~\n%Error: data/full_repos/permissive/456771003/rv_core.v:206: Cannot find file containing module: \'ff_ar\'\n    ff_ar #(.W(2)) rf_wdata_sel_ff(.clk(clk), .rst(rst), .d(rf_wdata_sel_n), .q(rf_wdata_sel_q));\n    ^~~~~\n%Error: data/full_repos/permissive/456771003/rv_core.v:210: Cannot find file containing module: \'ff_ar\'\n    ff_ar #(.W(5)) rd_ff(.clk(clk), .rst(rst), .d(rd_n), .q(rd_q));\n    ^~~~~\n%Error: data/full_repos/permissive/456771003/rv_core.v:215: Cannot find file containing module: \'ff_ar\'\n    ff_ar #(.W(32)) alu_reg(.clk(clk), .rst(rst), .d(alu_out), .q(alu_out_q));\n    ^~~~~\n%Error: data/full_repos/permissive/456771003/rv_core.v:218: Cannot find file containing module: \'ff_ar\'\n    ff_ar #(.W(32)) rs2_val_ff(.clk(clk), .rst(rst), .d(rs2_val), .q(rs2_val_q));\n    ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:223: Operator ASSIGNW expects 20 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                  : ... In instance rv_core\n    assign addr_n = (state_n == 1\'d0) ? pc_n : alu_out;\n                  ^\n%Error: data/full_repos/permissive/456771003/rv_core.v:224: Cannot find file containing module: \'ff_ar\'\n    ff_ar #(.W(20)) addr_reg(.clk(clk), .rst(rst), .d(addr_n), .q(addr_q));\n    ^~~~~\n%Error: data/full_repos/permissive/456771003/rv_core.v:227: Cannot find file containing module: \'ff_ar\'\n    ff_ar write_ff(.clk(clk), .rst(rst), .d(write_n), .q(write_q));\n    ^~~~~\n%Error: data/full_repos/permissive/456771003/rv_core.v:230: Cannot find file containing module: \'ff_ar\'\n    ff_ar #(.RESET_VAL(1)) read_ff(.clk(clk), .rst(rst), .d(read_n), .q(read_q));\n    ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:251: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                  : ... In instance rv_core\n    assign shamt = {27\'b0, data[24:20]};\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:279: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'shamt\' generates 5 bits.\n                                                                  : ... In instance rv_core\n            2\'d2:  alu_in2 = shamt;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:291: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s EQ generates 1 bits.\n                                                                  : ... In instance rv_core\n            4\'d3:  alu_out = alu_in1 == alu_in2;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/456771003/rv_core.v:292: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                                  : ... In instance rv_core\n            4\'d5 : alu_out = alu_in1 < alu_in2;\n                           ^\n%Error: Exiting due to 10 error(s), 62 warning(s)\n'
module rv_core(
    inout wire [31:0] data,
    output wire [19:0] addr,
    output wire write,
    output wire read,
    output wire [1:0] size,
    input wire clk,
    input wire rst
);

    wire [1:0] branch;
    wire [4:0] shamt;
    wire [31:0] imm;
    wire [1:0] alu_in1_sel, alu_in2_sel;

    wire state_n, state_q;
    assign state_n = (state_q == `S_FETCH) ? `S_UPDATE : `S_FETCH;
    ff_ar #(.RESET_VAL(`S_FETCH)) state_ff(.clk(clk), .rst(rst), .d(state_n), .q(state_q));

    wire [31:0] pc_q;
    reg [31:0] pc_n;
    ff_ar #(.W(32)) pc(.clk(clk), .rst(rst), .d(pc_n), .q(pc_q));

    wire rf_write_n, rf_write_q;
    ff_ar rf_write_ff(.clk(clk), .rst(rst), .d(rf_write_n && (state_q == `S_FETCH)), .q(rf_write_q));

    wire [1:0] rf_wdata_sel_n, rf_wdata_sel_q;
    ff_ar #(.W(2)) rf_wdata_sel_ff(.clk(clk), .rst(rst), .d(rf_wdata_sel_n), .q(rf_wdata_sel_q));

    wire [4:0] rd_n, rd_q, rs1, rs2;
    wire [31:0] rs1_val, rs2_val;
    ff_ar #(.W(5)) rd_ff(.clk(clk), .rst(rst), .d(rd_n), .q(rd_q));

    wire [3:0] alu_op;
    reg [31:0] alu_in1, alu_in2, alu_out;
    wire [31:0] alu_out_q;
    ff_ar #(.W(32)) alu_reg(.clk(clk), .rst(rst), .d(alu_out), .q(alu_out_q));

    wire [31:0] rs2_val_q;
    ff_ar #(.W(32)) rs2_val_ff(.clk(clk), .rst(rst), .d(rs2_val), .q(rs2_val_q));

    reg [31:0] reg_file [0:31];

    wire [19:0] addr_n, addr_q;
    assign addr_n = (state_n == `S_FETCH) ? pc_n : alu_out;
    ff_ar #(.W(20)) addr_reg(.clk(clk), .rst(rst), .d(addr_n), .q(addr_q));

    wire write_n, write_q;
    ff_ar write_ff(.clk(clk), .rst(rst), .d(write_n), .q(write_q));

    wire read_n, read_q;
    ff_ar #(.RESET_VAL(1)) read_ff(.clk(clk), .rst(rst), .d(read_n), .q(read_q));

    assign write = write_q && (state_q == `S_UPDATE);
    assign read = read_q || (state_q == `S_FETCH);
    assign size = `SZ_4B;
    assign data = write_q ? rs2_val_q : 'bz;
    assign addr = addr_q;

    always @(*) begin
        if (state_q == `S_FETCH) begin
            case (branch)
                `BR_NO:     pc_n = pc_q + 4;
                `BR_YES:    pc_n = alu_out;
                `BR_IF0:    pc_n = alu_out[0] == 1'b0 ? pc_q + imm : pc_q + 4;
                `BR_IF1:    pc_n = alu_out[0] == 1'b1 ? pc_q + imm : pc_q + 4;
            endcase
        end else begin
            pc_n = pc_q;
        end
    end

    assign shamt = {27'b0, data[24:20]};


    decode decode_inst(
        .op(data),
        .alu_op(alu_op),
        .alu_in1_sel(alu_in1_sel),
        .alu_in2_sel(alu_in2_sel),
        .imm(imm),
        .rd(rd_n), .rs1(rs1), .rs2(rs2),
        .rf_write(rf_write_n),
        .rf_wdata_sel(rf_wdata_sel_n),
        .branch(branch),
        .read(read_n),
        .write(write_n)
    );


    always @(*) begin
        alu_in1 = 'bx;
        case (alu_in1_sel)
            `SEL1_RS1: alu_in1 = rs1_val;
            `SEL1_PC:  alu_in1 = pc_q;
        endcase
        alu_in2 = 'bx;
        case (alu_in2_sel)
            `SEL2_IMM: alu_in2 = imm;
            `SEL2_RS2: alu_in2 = rs2_val;
            `SEL2_SH:  alu_in2 = shamt;
        endcase
    end


    always @(*) begin
        alu_out = 'bx;
        case (alu_op)
            `ALU_IN1: alu_out = alu_in1;
            `ALU_IN2: alu_out = alu_in2;
            `ALU_ADD: alu_out = alu_in1 + alu_in2;
            `ALU_SUB: alu_out = alu_in1 - alu_in2;
            `ALU_EQ:  alu_out = alu_in1 == alu_in2;
            `ALU_LT : alu_out = alu_in1 < alu_in2;
            `ALU_XOR: alu_out = alu_in1 ^ alu_in2;
            `ALU_OR : alu_out = alu_in1 | alu_in2;
            `ALU_AND: alu_out = alu_in1 & alu_in2;
            `ALU_SLL: alu_out = alu_in1 << alu_in2;
            `ALU_SRL: alu_out = alu_in1 >> alu_in2;
            `ALU_SRA: alu_out = alu_in1 >> alu_in2;
        endcase
    end


    assign rs1_val = (rs1 == 5'b0) ? 32'b0 : reg_file[rs1];
    assign rs2_val = (rs2 == 5'b0) ? 32'b0 : reg_file[rs2];
    integer i;
    always @(posedge clk, rst) begin
        if (rst) begin
            for (i = 0; i < 32; i = i + 1) begin
                reg_file[i] <= 32'b0;
            end

            reg_file[`REG_A1] <= 32'd5;
            reg_file[`REG_A0] <= 32'h54;
            reg_file[`REG_RA] <= 32'h4c;
        end else begin
            if (rf_write_q) begin
                case (rf_wdata_sel_q)
                    `RF_SEL_ALU: reg_file[rd_q] <= alu_out_q;
                    `RF_SEL_MEM: reg_file[rd_q] <= data;
                    `RF_SEL_PC4: reg_file[rd_q] <= pc_q + 4;
                endcase
            end
        end
    end

endmodule
module rv_core(
    inout wire [31:0] data,
    output wire [19:0] addr,
    output wire write,
    output wire read,
    output wire [1:0] size,
    input wire clk,
    input wire rst
);


    wire [1:0] branch;
    wire [4:0] shamt;
    wire [31:0] imm;
    wire [1:0] alu_in1_sel, alu_in2_sel;

    wire state_n, state_q;
    assign state_n = (state_q == `S_FETCH) ? `S_UPDATE : `S_FETCH;
    ff_ar #(.RESET_VAL(`S_FETCH)) state_ff(.clk(clk), .rst(rst), .d(state_n), .q(state_q));

    wire [31:0] pc_q;
    reg [31:0] pc_n;
    ff_ar #(.W(32)) pc(.clk(clk), .rst(rst), .d(pc_n), .q(pc_q));

    wire rf_write_n, rf_write_q;
    ff_ar rf_write_ff(.clk(clk), .rst(rst), .d(rf_write_n && (state_q == `S_FETCH)), .q(rf_write_q));

    wire [1:0] rf_wdata_sel_n, rf_wdata_sel_q;
    ff_ar #(.W(2)) rf_wdata_sel_ff(.clk(clk), .rst(rst), .d(rf_wdata_sel_n), .q(rf_wdata_sel_q));

    wire [4:0] rd_n, rd_q, rs1, rs2;
    wire [31:0] rs1_val, rs2_val;
    ff_ar #(.W(5)) rd_ff(.clk(clk), .rst(rst), .d(rd_n), .q(rd_q));

    wire [3:0] alu_op;
    reg [31:0] alu_in1, alu_in2, alu_out;
    wire [31:0] alu_out_q;
    ff_ar #(.W(32)) alu_reg(.clk(clk), .rst(rst), .d(alu_out), .q(alu_out_q));

    wire [31:0] rs2_val_q;
    ff_ar #(.W(32)) rs2_val_ff(.clk(clk), .rst(rst), .d(rs2_val), .q(rs2_val_q));

    reg [31:0] reg_file [0:31];

    wire [19:0] addr_n, addr_q;
    assign addr_n = (state_n == `S_FETCH) ? pc_n : alu_out;
    ff_ar #(.W(20)) addr_reg(.clk(clk), .rst(rst), .d(addr_n), .q(addr_q));

    wire write_n, write_q;
    ff_ar write_ff(.clk(clk), .rst(rst), .d(write_n), .q(write_q));

    wire read_n, read_q;
    ff_ar #(.RESET_VAL(1)) read_ff(.clk(clk), .rst(rst), .d(read_n), .q(read_q));

    assign write = write_q && (state_q == `S_UPDATE);
    assign read = read_q || (state_q == `S_FETCH);
    assign size = `SZ_4B;
    assign data = write_q ? rs2_val_q : 'bz;
    assign addr = addr_q;

    always @(*) begin
        if (state_q == `S_FETCH) begin
            case (branch)
                `BR_NO:     pc_n = pc_q + 4;
                `BR_YES:    pc_n = alu_out;
                `BR_IF0:    pc_n = alu_out[0] == 1'b0 ? pc_q + imm : pc_q + 4;
                `BR_IF1:    pc_n = alu_out[0] == 1'b1 ? pc_q + imm : pc_q + 4;
            endcase
        end else begin
            pc_n = pc_q;
        end
    end

    assign shamt = {27'b0, data[24:20]};


    decode decode_inst(
        .op(data),
        .alu_op(alu_op),
        .alu_in1_sel(alu_in1_sel),
        .alu_in2_sel(alu_in2_sel),
        .imm(imm),
        .rd(rd_n), .rs1(rs1), .rs2(rs2),
        .rf_write(rf_write_n),
        .rf_wdata_sel(rf_wdata_sel_n),
        .branch(branch),
        .read(read_n),
        .write(write_n)
    );


    always @(*) begin
        alu_in1 = 'bx;
        case (alu_in1_sel)
            `SEL1_RS1: alu_in1 = rs1_val;
            `SEL1_PC:  alu_in1 = pc_q;
        endcase
        alu_in2 = 'bx;
        case (alu_in2_sel)
            `SEL2_IMM: alu_in2 = imm;
            `SEL2_RS2: alu_in2 = rs2_val;
            `SEL2_SH:  alu_in2 = shamt;
        endcase
    end


    always @(*) begin
        alu_out = 'bx;
        case (alu_op)
            `ALU_IN1: alu_out = alu_in1;
            `ALU_IN2: alu_out = alu_in2;
            `ALU_ADD: alu_out = alu_in1 + alu_in2;
            `ALU_SUB: alu_out = alu_in1 - alu_in2;
            `ALU_EQ:  alu_out = alu_in1 == alu_in2;
            `ALU_LT : alu_out = alu_in1 < alu_in2;
            `ALU_XOR: alu_out = alu_in1 ^ alu_in2;
            `ALU_OR : alu_out = alu_in1 | alu_in2;
            `ALU_AND: alu_out = alu_in1 & alu_in2;
            `ALU_SLL: alu_out = alu_in1 << alu_in2;
            `ALU_SRL: alu_out = alu_in1 >> alu_in2;
            `ALU_SRA: alu_out = alu_in1 >> alu_in2;
        endcase
    end


    assign rs1_val = (rs1 == 5'b0) ? 32'b0 : reg_file[rs1];
    assign rs2_val = (rs2 == 5'b0) ? 32'b0 : reg_file[rs2];
    integer i;
    always @(posedge clk, rst) begin
        if (rst) begin
            for (i = 0; i < 32; i = i + 1) begin
                reg_file[i] <= 32'b0;
            end

            reg_file[`REG_A1] <= 32'd5;
            reg_file[`REG_A0] <= 32'h54;
            reg_file[`REG_RA] <= 32'h4c;
        end else begin
            if (rf_write_q) begin
                case (rf_wdata_sel_q)
                    `RF_SEL_ALU: reg_file[rd_q] <= alu_out_q;
                    `RF_SEL_MEM: reg_file[rd_q] <= data;
                    `RF_SEL_PC4: reg_file[rd_q] <= pc_q + 4;
                endcase
            end
        end
    end

endmodule