data/full_repos/permissive/504478691/MIPS/CPU54/CP0.v
1: b"%Error: data/full_repos/permissive/504478691/MIPS/CPU54/CP0.v:31: Cannot find file containing module: 'Reg32'\n    Reg32 count(clk, rst, 1'd1, din[9], dout[9]);\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/504478691/MIPS/CPU54,data/full_repos/permissive/504478691/Reg32\n             data/full_repos/permissive/504478691/MIPS/CPU54,data/full_repos/permissive/504478691/Reg32.v\n             data/full_repos/permissive/504478691/MIPS/CPU54,data/full_repos/permissive/504478691/Reg32.sv\n             Reg32\n             Reg32.v\n             Reg32.sv\n             obj_dir/Reg32\n             obj_dir/Reg32.v\n             obj_dir/Reg32.sv\n%Error: data/full_repos/permissive/504478691/MIPS/CPU54/CP0.v:32: Cannot find file containing module: 'Reg32'\n    Reg32 compare(clk, rst, ena[11], din[11], dout[11]);\n    ^~~~~\n%Error: data/full_repos/permissive/504478691/MIPS/CPU54/CP0.v:33: Cannot find file containing module: 'Reg32'\n    Reg32 status(clk, rst, ena[12] | exc, din[12], dout[12]);\n    ^~~~~\n%Error: data/full_repos/permissive/504478691/MIPS/CPU54/CP0.v:34: Cannot find file containing module: 'Reg32'\n    Reg32 cause(clk, rst, ena[13] | (exc_type < 8'h20), din[13], dout[13]);\n    ^~~~~\n%Error: data/full_repos/permissive/504478691/MIPS/CPU54/CP0.v:35: Cannot find file containing module: 'Reg32'\n    Reg32 epc(clk, rst, ena[14] | exc & exc_type != 8'h20, din[14], dout[14]);\n    ^~~~~\n%Error: Exiting due to 5 error(s)\n"
module CP0(clk, rst, addr, wea, data_in, data_out, pc, timer_int, exc, exc_type);

    input clk;
    input rst;
    input [4:0] addr;
    input wea;
    input [31:0] data_in;
    output [31:0] data_out;

    input [31:0] pc;
    output timer_int;
    output exc;
    input [7:0] exc_type;


    wire [31:0] din[0:31];
    wire [31:0] dout[0:31];
    wire [31:0] ena;
    reg timer_int_r;
    wire timer_rst;
    wire timer_equ;
    Reg32 count(clk, rst, 1'd1, din[9], dout[9]);
    Reg32 compare(clk, rst, ena[11], din[11], dout[11]);
    Reg32 status(clk, rst, ena[12] | exc, din[12], dout[12]);
    Reg32 cause(clk, rst, ena[13] | (exc_type < 8'h20), din[13], dout[13]);
    Reg32 epc(clk, rst, ena[14] | exc & exc_type != 8'h20, din[14], dout[14]);


    assign ena = {31'd0, wea} << addr;
    assign din[9]  = ena[9]  ? data_in : dout[9] + 32'd1;
    assign din[11] = ena[11] ? data_in : 32'dz;
    assign din[12] = ena[12] ? data_in :
                    (exc_type == 8'h20 ? {dout[12][31:2], 1'b0, dout[12][0]} :
                    (exc ? {dout[12][31:2], 1'b1, dout[12][0]} : 32'hz));
    assign din[13] = ena[13] ? data_in :
                    (exc_type < 8'h20 ?
                        {dout[13][31:10], 2'b00, dout[13][7], exc_type[4:0], dout[13][1:0]} : 32'dz);
    assign din[14] = wea & addr == 5'd14 ? data_in :
                    (exc & exc_type != 8'h20 ? pc : 32'dz);
    assign data_out = exc_type == 8'h20 ? dout[14] : (wea ? 32'dz : dout[addr]);

    assign timer_int = timer_int_r;
    assign timer_rst = rst | wea & addr == 5'd11 | dout[11] == 32'd0;
    assign timer_equ = dout[9] == dout[11];
    assign exc = exc_type != 8'hff;

    always @(posedge timer_equ or posedge timer_rst)
        timer_int_r = timer_rst ? 1'd0 : 1'd1;
endmodule
module CP0(clk, rst, addr, wea, data_in, data_out, pc, timer_int, exc, exc_type);


    input clk;
    input rst;
    input [4:0] addr;
    input wea;
    input [31:0] data_in;
    output [31:0] data_out;

    input [31:0] pc;
    output timer_int;
    output exc;
    input [7:0] exc_type;


    wire [31:0] din[0:31];
    wire [31:0] dout[0:31];
    wire [31:0] ena;
    reg timer_int_r;
    wire timer_rst;
    wire timer_equ;
    Reg32 count(clk, rst, 1'd1, din[9], dout[9]);
    Reg32 compare(clk, rst, ena[11], din[11], dout[11]);
    Reg32 status(clk, rst, ena[12] | exc, din[12], dout[12]);
    Reg32 cause(clk, rst, ena[13] | (exc_type < 8'h20), din[13], dout[13]);
    Reg32 epc(clk, rst, ena[14] | exc & exc_type != 8'h20, din[14], dout[14]);


    assign ena = {31'd0, wea} << addr;
    assign din[9]  = ena[9]  ? data_in : dout[9] + 32'd1;
    assign din[11] = ena[11] ? data_in : 32'dz;
    assign din[12] = ena[12] ? data_in :
                    (exc_type == 8'h20 ? {dout[12][31:2], 1'b0, dout[12][0]} :
                    (exc ? {dout[12][31:2], 1'b1, dout[12][0]} : 32'hz));
    assign din[13] = ena[13] ? data_in :
                    (exc_type < 8'h20 ?
                        {dout[13][31:10], 2'b00, dout[13][7], exc_type[4:0], dout[13][1:0]} : 32'dz);
    assign din[14] = wea & addr == 5'd14 ? data_in :
                    (exc & exc_type != 8'h20 ? pc : 32'dz);
    assign data_out = exc_type == 8'h20 ? dout[14] : (wea ? 32'dz : dout[addr]);

    assign timer_int = timer_int_r;
    assign timer_rst = rst | wea & addr == 5'd11 | dout[11] == 32'd0;
    assign timer_equ = dout[9] == dout[11];
    assign exc = exc_type != 8'hff;

    always @(posedge timer_equ or posedge timer_rst)
        timer_int_r = timer_rst ? 1'd0 : 1'd1;
endmodule