data/full_repos/permissive/486598419/6.6/Synchronous_D_FF.v
data/verilator_xmls/c518c546-8f50-4ec3-8121-5d2733c2b0ae.xml
module Synchronous_D_FF(
    input CLK,
    input D,
    input RST_n,
    output reg Q1,
    output reg Q2
    );
    always @(posedge CLK )
    if(~RST_n)
    begin
        Q1<=1'b0;
        Q2<=1'b1;
    end
    else
    begin
        Q1<=D;
        Q2<=~D;
    end
endmodule
module Synchronous_D_FF(
    input CLK,
    input D,
    input RST_n,
    output reg Q1,
    output reg Q2
    );

    always @(posedge CLK )
    if(~RST_n)
    begin
        Q1<=1'b0;
        Q2<=1'b1;
    end
    else
    begin
        Q1<=D;
        Q2<=~D;
    end
endmodule