data/full_repos/permissive/435516446/MIPS/struMem_TEST.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/struMem_TEST.v:34: Unsupported: Ignoring delay on this delayed statement.\n always #10 clock <= ~clock;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/struMem_TEST.v:35: Unsupported: Ignoring delay on this delayed statement.\n always #10 address <= address + 32\'b00000000000000000000000000000001;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/struMem_TEST.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #100 $finish;\n  ^\n%Error: data/full_repos/permissive/435516446/MIPS/struMem_TEST.v:39: Cannot find file containing module: \'InstructionMemory\'\n InstructionMemory uut (\n ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/InstructionMemory\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/InstructionMemory.v\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/InstructionMemory.sv\n             InstructionMemory\n             InstructionMemory.v\n             InstructionMemory.sv\n             obj_dir/InstructionMemory\n             obj_dir/InstructionMemory.v\n             obj_dir/InstructionMemory.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module struMem_TEST;


	reg [31:0] address;
	reg clock;
	

	wire [31:0] inst;

	always #10 clock <= ~clock;
	always #10 address <= address + 32'b00000000000000000000000000000001;



	InstructionMemory uut (
		.address(address), 
		.clock(clock), 
		.inst(inst)
	);

	initial begin

		address <= 32'h000000;
		clock <= 0;


		#100 $finish;
        


	end
      
endmodule
module struMem_TEST;



	reg [31:0] address;
	reg clock;
	

	wire [31:0] inst;

	always #10 clock <= ~clock;
	always #10 address <= address + 32'b00000000000000000000000000000001;



	InstructionMemory uut (
		.address(address), 
		.clock(clock), 
		.inst(inst)
	);

	initial begin

		address <= 32'h000000;
		clock <= 0;


		#100 $finish;
        


	end
      
endmodule