data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv
1: b'%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv:3: Cannot find include file: bli201v32i_tl_defines.vh\n`include "bli201v32i_tl_defines.vh" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/519458744/BLI201V32ITL/sim,data/full_repos/permissive/519458744/bli201v32i_tl_defines.vh\n             data/full_repos/permissive/519458744/BLI201V32ITL/sim,data/full_repos/permissive/519458744/bli201v32i_tl_defines.vh.v\n             data/full_repos/permissive/519458744/BLI201V32ITL/sim,data/full_repos/permissive/519458744/bli201v32i_tl_defines.vh.sv\n             bli201v32i_tl_defines.vh\n             bli201v32i_tl_defines.vh.v\n             bli201v32i_tl_defines.vh.sv\n             obj_dir/bli201v32i_tl_defines.vh\n             obj_dir/bli201v32i_tl_defines.vh.v\n             obj_dir/bli201v32i_tl_defines.vh.sv\n%Warning-STMTDLY: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv:13: Unsupported: Ignoring delay on this delayed statement.\n    #(CLOCK_PERIOD/2) clk = ~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv:18: Unsupported: Ignoring delay on this delayed statement.\n      #0;\n      ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv:21: syntax error, unexpected \'@\'\n      repeat(2) @(posedge clk);\n                ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv:65: Define or directive not defined: \'`TL_A_MSG_PUTFULLDATA_OPCODE\'\n      tl_a_opcode   <= `TL_A_MSG_PUTFULLDATA_OPCODE;  \n                       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv:65: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      tl_a_opcode   <= `TL_A_MSG_PUTFULLDATA_OPCODE;  \n                                                   ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv:66: Define or directive not defined: \'`TL_A_MSG_PUTFULLDATA_PARAM\'\n      tl_a_param    <= `TL_A_MSG_PUTFULLDATA_PARAM;   \n                       ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv:66: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      tl_a_param    <= `TL_A_MSG_PUTFULLDATA_PARAM;   \n                                                  ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv:74: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv:79: Unsupported: fork statements\n      fork\n      ^~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv:87: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv:104: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv:108: Define or directive not defined: \'`TL_D_MSG_ACCESSACK_OPCODE\'\n          if (tl_d_opcode !== `TL_D_MSG_ACCESSACK_OPCODE)   $display("%d [TL PutFullData]: ERROR: response opcode incorrect!", $time);\n                              ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv:108: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n          if (tl_d_opcode !== `TL_D_MSG_ACCESSACK_OPCODE)   $display("%d [TL PutFullData]: ERROR: response opcode incorrect!", $time);\n                                                        ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv:109: Define or directive not defined: \'`TL_D_MSG_ACCESSACK_PARAM\'\n          if (tl_d_param !== `TL_D_MSG_ACCESSACK_PARAM)    $display("%d [TL PutFullData]: ERROR: response param incorrect!", $time);\n                             ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv:109: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n          if (tl_d_param !== `TL_D_MSG_ACCESSACK_PARAM)    $display("%d [TL PutFullData]: ERROR: response param incorrect!", $time);\n                                                      ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv:116: syntax error, unexpected \'@\'\n          @(posedge clk);\n          ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv:133: Define or directive not defined: \'`TL_A_MSG_GET_OPCODE\'\n      tl_a_opcode   <= `TL_A_MSG_GET_OPCODE;         \n                       ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv:133: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      tl_a_opcode   <= `TL_A_MSG_GET_OPCODE;         \n                                           ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv:134: Define or directive not defined: \'`TL_A_MSG_GET_PARAM\'\n      tl_a_param    <= `TL_A_MSG_GET_PARAM;          \n                       ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv:134: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      tl_a_param    <= `TL_A_MSG_GET_PARAM;          \n                                          ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv:144: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv:146: Unsupported: fork statements\n      fork\n      ^~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv:154: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv:171: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv:178: Define or directive not defined: \'`TL_D_MSG_ACCESSACKDATA_OPCODE\'\n          if (tl_d_opcode !== `TL_D_MSG_ACCESSACKDATA_OPCODE)   $display("%d [TL Get]: ERROR: response opcode incorrect!", $time);\n                              ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv:178: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n          if (tl_d_opcode !== `TL_D_MSG_ACCESSACKDATA_OPCODE)   $display("%d [TL Get]: ERROR: response opcode incorrect!", $time);\n                                                            ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv:179: Define or directive not defined: \'`TL_D_MSG_ACCESSACKDATA_PARAM\'\n          if (tl_d_param !== `TL_D_MSG_ACCESSACKDATA_PARAM)    $display("%d [TL Get]: ERROR: response param incorrect!", $time);\n                             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv:179: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n          if (tl_d_param !== `TL_D_MSG_ACCESSACKDATA_PARAM)    $display("%d [TL Get]: ERROR: response param incorrect!", $time);\n                                                          ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv:239: syntax error, unexpected \'@\'\n    repeat(8) @(posedge clk);\n              ^\n%Error: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv:248: syntax error, unexpected \'@\'\n    repeat(100) @(posedge clk);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/519458744/BLI201V32ITL/sim/tb_gpio.sv:249: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Error: Exiting due to 29 error(s), 3 warning(s)\n'
module tb_gpio();
  parameter CLOCK_FREQ = 100_000_000;
  parameter CLOCK_PERIOD = 1_000_000_000 / CLOCK_FREQ;


  reg clk, rst;
  initial clk = 'b0;
  always
    #(CLOCK_PERIOD/2) clk = ~clk;


  task SYS_reset;
    begin
      #0;
      rst = 0;
      $display("[TEST]\tRESET pulled LOW.");
      repeat(2) @(posedge clk);
      @(negedge clk);
      rst = 1;
      $display("[TEST]\tRESET pulled HIGH.");
    end
  endtask






  reg [2:0]   tl_a_opcode;    initial tl_a_opcode  = 'b0;
  reg [2:0]   tl_a_param;     initial tl_a_param   = 'b0;
  reg [2:0]   tl_a_size;      initial tl_a_size    = 'b0;
  reg [0:0]   tl_a_source;    initial tl_a_source  = 'b0;
  reg [31:0]  tl_a_address;   initial tl_a_address = 'b0;
  reg [3:0]   tl_a_mask;      initial tl_a_mask    = 'b0;
  reg [31:0]  tl_a_data;      initial tl_a_data    = 'b0;
  reg         tl_a_corrupt;   initial tl_a_corrupt = 'b0;
  reg         tl_a_valid;     initial tl_a_valid   = 'b0;
  wire        tl_a_ready;
    
  wire [2:0]  tl_d_opcode;
  wire [1:0]  tl_d_param;
  wire [2:0]  tl_d_size;
  wire [0:0]  tl_d_source;
  wire [0:0]  tl_d_sink;
  wire        tl_d_denied;
  wire [31:0] tl_d_data;
  wire        tl_d_corrupt;
  wire        tl_d_valid;
  reg         tl_d_ready;     initial tl_d_ready   = 'b0;

  parameter tl_log_quiet = 0;

  task TL_PutFullData;
    input  [2:0]  size;
    input  [0:0]  source;
    input  [31:0] address;
    input  [4:0]  mask;
    input  [31:0] data;

    begin
      tl_a_opcode   <= `TL_A_MSG_PUTFULLDATA_OPCODE;
      tl_a_param    <= `TL_A_MSG_PUTFULLDATA_PARAM;
      tl_a_size     <= $clog2(size);
      tl_a_source   <= source;
      tl_a_address  <= address;
      tl_a_mask     <= mask;
      tl_a_corrupt  <= 1'b0;
      tl_a_data     <= data;
      
      @(posedge clk);
      
      $display("%d [TL PutFullData]: <addr: 0x%h (%d), size: %d, mask: %b, data: 0x%h (%d)>", $time, tl_a_address, tl_a_address, size, tl_a_mask, tl_a_data, tl_a_data);


      fork
        begin

          if (!tl_log_quiet) $display("%d [TL PutFullData]:  asserting ch A VALID...", $time);
          tl_a_valid <= 'b1;
          
          if (!tl_log_quiet) $display("%d [TL PutFullData]:  waiting slave ch A READY...", $time);
          while (tl_a_ready !== 'b1) begin
            @(posedge clk);
          end
          

          @(posedge clk);
          
          if (!tl_log_quiet) $display("%d [TL PutFullData]:  finish ch A transaction.", $time);
          tl_a_valid <= 'b0;
        end
        begin
          if (!tl_log_quiet) $display("%d [TL PutFullData]:  asserting ch D READY...", $time);


          tl_d_ready <= 'b1;

          if (!tl_log_quiet) $display("%d [TL PutFullData]:  waiting slave ch D VALID...", $time);
          while (tl_d_valid !== 'b1) begin
            @(posedge clk);
          end


          if (tl_d_opcode !== `TL_D_MSG_ACCESSACK_OPCODE)   $display("%d [TL PutFullData]: ERROR: response opcode incorrect!", $time);
          if (tl_d_param !== `TL_D_MSG_ACCESSACK_PARAM)    $display("%d [TL PutFullData]: ERROR: response param incorrect!", $time);
          if (tl_d_size !== tl_a_size)                      $display("%d [TL PutFullData]: ERROR: response size mismatch!", $time); 
          if (tl_d_source !== tl_a_source)                  $display("%d [TL PutFullData]: ERROR: response source mismatch!", $time); 
          if (tl_d_denied !== 'b0)                          $display("%d [TL PutFullData]: WARNING: response denied!", $time);
          if (tl_d_corrupt !== 'b0)                         $display("%d [TL PutFullData]: WARNING: response corrupted!", $time);
          

          @(posedge clk);
          
          if (!tl_log_quiet) $display("%d [TL PutFullData]: finish ch D transaction.", $time);
        end
      join
    end
  endtask
  
  
  task TL_Get;
    input  [2:0]  size;
    input  [0:0]  source;
    input  [31:0] address;
    input  [4:0]  mask;
    output [31:0] data;

    begin
      tl_a_opcode   <= `TL_A_MSG_GET_OPCODE;
      tl_a_param    <= `TL_A_MSG_GET_PARAM;
      tl_a_size     <= $clog2(size);
      tl_a_source   <= source;
      tl_a_address  <= address;
      tl_a_mask     <= mask;
      tl_a_corrupt  <= 1'b0;
      tl_a_data     <= 'h0;
      
      $display("%d [TL Get]: <addr: 0x%h (%d), size: %d, mask: %b>", $time, tl_a_address, tl_a_address, size, tl_a_mask);

      @(posedge clk);

      fork
        begin

          if (!tl_log_quiet) $display("%d [TL Get]:  asserting ch A VALID...", $time);
          tl_a_valid <= 'b1;
          
          if (!tl_log_quiet) $display("%d [TL Get]:  waiting slave ch A READY...", $time);
          while (tl_a_ready !== 'b1) begin
            @(posedge clk);
          end
          

          @(posedge clk);
          
          if (!tl_log_quiet) $display("%d [TL Get]:  finish ch A transaction.", $time);
          tl_a_valid <= 'b0;
        end
        begin
          if (!tl_log_quiet) $display("%d [TL Get]:  asserting ch D READY...", $time);


          tl_d_ready <= 'b1;

          if (!tl_log_quiet) $display("%d [TL Get]:  waiting slave ch D VALID...", $time);
          while (tl_d_valid !== 'b1) begin
            @(posedge clk);
          end


          @(posedge clk);
          

          if (tl_d_opcode !== `TL_D_MSG_ACCESSACKDATA_OPCODE)   $display("%d [TL Get]: ERROR: response opcode incorrect!", $time);
          if (tl_d_param !== `TL_D_MSG_ACCESSACKDATA_PARAM)    $display("%d [TL Get]: ERROR: response param incorrect!", $time);
          if (tl_d_size !== tl_a_size)                      $display("%d [TL Get]: ERROR: response size mismatch!", $time); 
          if (tl_d_source !== tl_a_source)                  $display("%d [TL Get]: ERROR: response source mismatch!", $time); 
          if (tl_d_denied !== 'b0)                          $display("%d [TL Get]: WARNING: response denied!", $time);
          if (tl_d_corrupt !== 'b0)                         $display("%d [TL Get]: WARNING: response corrupted!", $time);
          
          if (!tl_log_quiet) $display("%d [TL Get]:  finish ch D transaction.", $time);
          
          $display("%d [TL Get]: <Response: data: 0x%h (%d)>", $time, tl_d_data, tl_d_data);
          data <= tl_d_data;
        end
      join
    end
  endtask



  reg [3:0] sw;     initial sw = 'b1111;
  reg [3:0] btn;    initial btn = 'b0000;
  wire [3:0] led;

  gpio #(
  ) DUT (
    .clk(clk),
    .rst(rst),

    .gpio_i_tl_a_opcode(tl_a_opcode),
    .gpio_i_tl_a_param(tl_a_param),
    .gpio_i_tl_a_size(tl_a_size),
    .gpio_i_tl_a_source(tl_a_source),
    .gpio_i_tl_a_address(tl_a_address),
    .gpio_i_tl_a_mask(tl_a_mask),
    .gpio_i_tl_a_data(tl_a_data),
    .gpio_i_tl_a_corrupt(tl_a_corrupt),
    .gpio_i_tl_a_valid(tl_a_valid),
    .gpio_o_tl_a_ready(tl_a_ready),
    
    .gpio_o_tl_d_opcode(tl_d_opcode),
    .gpio_o_tl_d_param(tl_d_param),
    .gpio_o_tl_d_size(tl_d_size),
    .gpio_o_tl_d_source(tl_d_source),
    .gpio_o_tl_d_sink(tl_d_sink),
    .gpio_o_tl_d_denied(tl_d_denied),
    .gpio_o_tl_d_data(tl_d_data),
    .gpio_o_tl_d_corrupt(tl_d_corrupt),
    .gpio_o_tl_d_valid(tl_d_valid),
    .gpio_i_tl_d_ready(tl_d_ready),

    .gpio_i_sw(sw),
    .gpio_i_btn(btn),
    .gpio_o_led(led)
  );



  reg [31:0] tl_data_output;

  initial begin
    SYS_reset();
    
    repeat(8) @(posedge clk);
    
    
      begin
        TL_PutFullData('d4, 'h0, 'h0000_0004, 'b0001, 'h0000_0041);
        
        TL_Get('d4, 'h0, 'h0000_0000, 'b0001, tl_data_output);
      end
    
    repeat(100) @(posedge clk);
    #100;
    $finish();

  end 

endmodule
module tb_gpio();

  parameter CLOCK_FREQ = 100_000_000;
  parameter CLOCK_PERIOD = 1_000_000_000 / CLOCK_FREQ;


  reg clk, rst;
  initial clk = 'b0;
  always
    #(CLOCK_PERIOD/2) clk = ~clk;


  task SYS_reset;
    begin
      #0;
      rst = 0;
      $display("[TEST]\tRESET pulled LOW.");
      repeat(2) @(posedge clk);
      @(negedge clk);
      rst = 1;
      $display("[TEST]\tRESET pulled HIGH.");
    end
  endtask






  reg [2:0]   tl_a_opcode;    initial tl_a_opcode  = 'b0;
  reg [2:0]   tl_a_param;     initial tl_a_param   = 'b0;
  reg [2:0]   tl_a_size;      initial tl_a_size    = 'b0;
  reg [0:0]   tl_a_source;    initial tl_a_source  = 'b0;
  reg [31:0]  tl_a_address;   initial tl_a_address = 'b0;
  reg [3:0]   tl_a_mask;      initial tl_a_mask    = 'b0;
  reg [31:0]  tl_a_data;      initial tl_a_data    = 'b0;
  reg         tl_a_corrupt;   initial tl_a_corrupt = 'b0;
  reg         tl_a_valid;     initial tl_a_valid   = 'b0;
  wire        tl_a_ready;
    
  wire [2:0]  tl_d_opcode;
  wire [1:0]  tl_d_param;
  wire [2:0]  tl_d_size;
  wire [0:0]  tl_d_source;
  wire [0:0]  tl_d_sink;
  wire        tl_d_denied;
  wire [31:0] tl_d_data;
  wire        tl_d_corrupt;
  wire        tl_d_valid;
  reg         tl_d_ready;     initial tl_d_ready   = 'b0;

  parameter tl_log_quiet = 0;

  task TL_PutFullData;
    input  [2:0]  size;
    input  [0:0]  source;
    input  [31:0] address;
    input  [4:0]  mask;
    input  [31:0] data;

    begin
      tl_a_opcode   <= `TL_A_MSG_PUTFULLDATA_OPCODE;
      tl_a_param    <= `TL_A_MSG_PUTFULLDATA_PARAM;
      tl_a_size     <= $clog2(size);
      tl_a_source   <= source;
      tl_a_address  <= address;
      tl_a_mask     <= mask;
      tl_a_corrupt  <= 1'b0;
      tl_a_data     <= data;
      
      @(posedge clk);
      
      $display("%d [TL PutFullData]: <addr: 0x%h (%d), size: %d, mask: %b, data: 0x%h (%d)>", $time, tl_a_address, tl_a_address, size, tl_a_mask, tl_a_data, tl_a_data);


      fork
        begin

          if (!tl_log_quiet) $display("%d [TL PutFullData]:  asserting ch A VALID...", $time);
          tl_a_valid <= 'b1;
          
          if (!tl_log_quiet) $display("%d [TL PutFullData]:  waiting slave ch A READY...", $time);
          while (tl_a_ready !== 'b1) begin
            @(posedge clk);
          end
          

          @(posedge clk);
          
          if (!tl_log_quiet) $display("%d [TL PutFullData]:  finish ch A transaction.", $time);
          tl_a_valid <= 'b0;
        end
        begin
          if (!tl_log_quiet) $display("%d [TL PutFullData]:  asserting ch D READY...", $time);


          tl_d_ready <= 'b1;

          if (!tl_log_quiet) $display("%d [TL PutFullData]:  waiting slave ch D VALID...", $time);
          while (tl_d_valid !== 'b1) begin
            @(posedge clk);
          end


          if (tl_d_opcode !== `TL_D_MSG_ACCESSACK_OPCODE)   $display("%d [TL PutFullData]: ERROR: response opcode incorrect!", $time);
          if (tl_d_param !== `TL_D_MSG_ACCESSACK_PARAM)    $display("%d [TL PutFullData]: ERROR: response param incorrect!", $time);
          if (tl_d_size !== tl_a_size)                      $display("%d [TL PutFullData]: ERROR: response size mismatch!", $time); 
          if (tl_d_source !== tl_a_source)                  $display("%d [TL PutFullData]: ERROR: response source mismatch!", $time); 
          if (tl_d_denied !== 'b0)                          $display("%d [TL PutFullData]: WARNING: response denied!", $time);
          if (tl_d_corrupt !== 'b0)                         $display("%d [TL PutFullData]: WARNING: response corrupted!", $time);
          

          @(posedge clk);
          
          if (!tl_log_quiet) $display("%d [TL PutFullData]: finish ch D transaction.", $time);
        end
      join
    end
  endtask
  
  
  task TL_Get;
    input  [2:0]  size;
    input  [0:0]  source;
    input  [31:0] address;
    input  [4:0]  mask;
    output [31:0] data;

    begin
      tl_a_opcode   <= `TL_A_MSG_GET_OPCODE;
      tl_a_param    <= `TL_A_MSG_GET_PARAM;
      tl_a_size     <= $clog2(size);
      tl_a_source   <= source;
      tl_a_address  <= address;
      tl_a_mask     <= mask;
      tl_a_corrupt  <= 1'b0;
      tl_a_data     <= 'h0;
      
      $display("%d [TL Get]: <addr: 0x%h (%d), size: %d, mask: %b>", $time, tl_a_address, tl_a_address, size, tl_a_mask);

      @(posedge clk);

      fork
        begin

          if (!tl_log_quiet) $display("%d [TL Get]:  asserting ch A VALID...", $time);
          tl_a_valid <= 'b1;
          
          if (!tl_log_quiet) $display("%d [TL Get]:  waiting slave ch A READY...", $time);
          while (tl_a_ready !== 'b1) begin
            @(posedge clk);
          end
          

          @(posedge clk);
          
          if (!tl_log_quiet) $display("%d [TL Get]:  finish ch A transaction.", $time);
          tl_a_valid <= 'b0;
        end
        begin
          if (!tl_log_quiet) $display("%d [TL Get]:  asserting ch D READY...", $time);


          tl_d_ready <= 'b1;

          if (!tl_log_quiet) $display("%d [TL Get]:  waiting slave ch D VALID...", $time);
          while (tl_d_valid !== 'b1) begin
            @(posedge clk);
          end


          @(posedge clk);
          

          if (tl_d_opcode !== `TL_D_MSG_ACCESSACKDATA_OPCODE)   $display("%d [TL Get]: ERROR: response opcode incorrect!", $time);
          if (tl_d_param !== `TL_D_MSG_ACCESSACKDATA_PARAM)    $display("%d [TL Get]: ERROR: response param incorrect!", $time);
          if (tl_d_size !== tl_a_size)                      $display("%d [TL Get]: ERROR: response size mismatch!", $time); 
          if (tl_d_source !== tl_a_source)                  $display("%d [TL Get]: ERROR: response source mismatch!", $time); 
          if (tl_d_denied !== 'b0)                          $display("%d [TL Get]: WARNING: response denied!", $time);
          if (tl_d_corrupt !== 'b0)                         $display("%d [TL Get]: WARNING: response corrupted!", $time);
          
          if (!tl_log_quiet) $display("%d [TL Get]:  finish ch D transaction.", $time);
          
          $display("%d [TL Get]: <Response: data: 0x%h (%d)>", $time, tl_d_data, tl_d_data);
          data <= tl_d_data;
        end
      join
    end
  endtask



  reg [3:0] sw;     initial sw = 'b1111;
  reg [3:0] btn;    initial btn = 'b0000;
  wire [3:0] led;

  gpio #(
  ) DUT (
    .clk(clk),
    .rst(rst),

    .gpio_i_tl_a_opcode(tl_a_opcode),
    .gpio_i_tl_a_param(tl_a_param),
    .gpio_i_tl_a_size(tl_a_size),
    .gpio_i_tl_a_source(tl_a_source),
    .gpio_i_tl_a_address(tl_a_address),
    .gpio_i_tl_a_mask(tl_a_mask),
    .gpio_i_tl_a_data(tl_a_data),
    .gpio_i_tl_a_corrupt(tl_a_corrupt),
    .gpio_i_tl_a_valid(tl_a_valid),
    .gpio_o_tl_a_ready(tl_a_ready),
    
    .gpio_o_tl_d_opcode(tl_d_opcode),
    .gpio_o_tl_d_param(tl_d_param),
    .gpio_o_tl_d_size(tl_d_size),
    .gpio_o_tl_d_source(tl_d_source),
    .gpio_o_tl_d_sink(tl_d_sink),
    .gpio_o_tl_d_denied(tl_d_denied),
    .gpio_o_tl_d_data(tl_d_data),
    .gpio_o_tl_d_corrupt(tl_d_corrupt),
    .gpio_o_tl_d_valid(tl_d_valid),
    .gpio_i_tl_d_ready(tl_d_ready),

    .gpio_i_sw(sw),
    .gpio_i_btn(btn),
    .gpio_o_led(led)
  );



  reg [31:0] tl_data_output;

  initial begin
    SYS_reset();
    
    repeat(8) @(posedge clk);
    
    
      begin
        TL_PutFullData('d4, 'h0, 'h0000_0004, 'b0001, 'h0000_0041);
        
        TL_Get('d4, 'h0, 'h0000_0000, 'b0001, tl_data_output);
      end
    
    repeat(100) @(posedge clk);
    #100;
    $finish();

  end 

endmodule