data/full_repos/permissive/486367830/hdl/comp_mult_4.v
1: b"%Error: data/full_repos/permissive/486367830/hdl/comp_mult_4.v:77: Cannot find file containing module: 'signed_mult'\nsigned_mult #(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/486367830/hdl,data/full_repos/permissive/486367830/signed_mult\n             data/full_repos/permissive/486367830/hdl,data/full_repos/permissive/486367830/signed_mult.v\n             data/full_repos/permissive/486367830/hdl,data/full_repos/permissive/486367830/signed_mult.sv\n             signed_mult\n             signed_mult.v\n             signed_mult.sv\n             obj_dir/signed_mult\n             obj_dir/signed_mult.v\n             obj_dir/signed_mult.sv\n%Error: data/full_repos/permissive/486367830/hdl/comp_mult_4.v:85: Cannot find file containing module: 'signed_mult'\nsigned_mult #(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/486367830/hdl/comp_mult_4.v:93: Cannot find file containing module: 'signed_mult'\nsigned_mult #(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/486367830/hdl/comp_mult_4.v:101: Cannot find file containing module: 'signed_mult'\nsigned_mult #(\n^~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module comp_mult_4 #(
parameter DWIDTH = 8
)(

input                              clk      ,
input                              rst_n    ,
input                              sw_rst   ,
                                  

input                              op_val   ,
output reg                         op_rdy   ,
input      [      2*2*DWIDTH -1:0] op_data  ,


output reg                         res_val  ,
input                              res_rdy  ,
output     [2*2*(DWIDTH + 1) -1:0] res_data
); 



wire op_ld;



wire [  DWIDTH -1:0] x1 ;
wire [  DWIDTH -1:0] x2 ;
wire [  DWIDTH -1:0] y1 ;
wire [  DWIDTH -1:0] y2 ;


wire [2*DWIDTH -1:0] prod1  ;
wire [2*DWIDTH -1:0] prod2  ;
wire [2*DWIDTH -1:0] prod3  ;
wire [2*DWIDTH -1:0] prod4  ;


reg  [2*DWIDTH-1 :0] xr ;
reg  [2*DWIDTH-1 :0] yr ;




always @(posedge clk or negedge rst_n)
if(~rst_n)            op_rdy <= 1'b1 ; else
if(sw_rst)            op_rdy <= 1'b1 ; else
if(op_val & op_rdy)   op_rdy <= 1'b0 ; else 
if(res_rdy)           op_rdy <= 1'b1 ; 
  
assign op_ld = op_val & op_rdy;

always @(posedge clk or negedge rst_n)
if(~rst_n)              res_val <= 1'b0 ; else
if(sw_rst)              res_val <= 1'b0 ; else
if(op_ld)               res_val <= 1'b1 ; else
if(res_rdy)             res_val <= 1'b0 ;

  

  
  

assign x1 = op_data[4*DWIDTH -1 -: DWIDTH]; 
assign y1 = op_data[3*DWIDTH -1 -: DWIDTH]; 
assign x2 = op_data[2*DWIDTH -1 -: DWIDTH]; 
assign y2 = op_data[1*DWIDTH -1 -: DWIDTH]; 

signed_mult #(
.DWIDTH (DWIDTH)
)i_signed_mult_0(
 .op1    (x1     ),
 .op2    (x2     ),
 .result (prod1  )
);  

signed_mult #(
.DWIDTH (DWIDTH)
)i_signed_mult_1(
 .op1    (x1     ),
 .op2    (y2     ),
 .result (prod2  )
);  

signed_mult #(
.DWIDTH (DWIDTH)
)i_signed_mult_2(
 .op1    (x2     ),
 .op2    (y1     ),
 .result (prod3  )
);  

signed_mult #(
.DWIDTH (DWIDTH)
)i_signed_mult_3(
 .op1    (y1     ),
 .op2    (y2     ),
 .result (prod4  )
);  


always @(posedge clk or negedge rst_n)
if(~rst_n)   xr <= 'b0           ; else 
if(sw_rst)   xr <= 'b0           ; else 
if(op_ld)    xr <= prod1 - prod4 ;


always @(posedge clk or negedge rst_n)
if(~rst_n)   yr <= 'b0           ; else 
if(sw_rst)   yr <= 'b0           ; else 
if(op_ld)    yr <= prod2 + prod3 ;


assign res_data = {{{'d2{xr[2*DWIDTH-1]}},xr},
                   {{'d2{yr[2*DWIDTH-1]}},yr}};




endmodule
module comp_mult_4 #(
parameter DWIDTH = 8
)(

input                              clk      ,
input                              rst_n    ,
input                              sw_rst   ,
                                  

input                              op_val   ,
output reg                         op_rdy   ,
input      [      2*2*DWIDTH -1:0] op_data  ,


output reg                         res_val  ,
input                              res_rdy  ,
output     [2*2*(DWIDTH + 1) -1:0] res_data
);
 



wire op_ld;



wire [  DWIDTH -1:0] x1 ;
wire [  DWIDTH -1:0] x2 ;
wire [  DWIDTH -1:0] y1 ;
wire [  DWIDTH -1:0] y2 ;


wire [2*DWIDTH -1:0] prod1  ;
wire [2*DWIDTH -1:0] prod2  ;
wire [2*DWIDTH -1:0] prod3  ;
wire [2*DWIDTH -1:0] prod4  ;


reg  [2*DWIDTH-1 :0] xr ;
reg  [2*DWIDTH-1 :0] yr ;




always @(posedge clk or negedge rst_n)
if(~rst_n)            op_rdy <= 1'b1 ; else
if(sw_rst)            op_rdy <= 1'b1 ; else
if(op_val & op_rdy)   op_rdy <= 1'b0 ; else 
if(res_rdy)           op_rdy <= 1'b1 ; 
  
assign op_ld = op_val & op_rdy;

always @(posedge clk or negedge rst_n)
if(~rst_n)              res_val <= 1'b0 ; else
if(sw_rst)              res_val <= 1'b0 ; else
if(op_ld)               res_val <= 1'b1 ; else
if(res_rdy)             res_val <= 1'b0 ;

  

  
  

assign x1 = op_data[4*DWIDTH -1 -: DWIDTH]; 
assign y1 = op_data[3*DWIDTH -1 -: DWIDTH]; 
assign x2 = op_data[2*DWIDTH -1 -: DWIDTH]; 
assign y2 = op_data[1*DWIDTH -1 -: DWIDTH]; 

signed_mult #(
.DWIDTH (DWIDTH)
)i_signed_mult_0(
 .op1    (x1     ),
 .op2    (x2     ),
 .result (prod1  )
);  

signed_mult #(
.DWIDTH (DWIDTH)
)i_signed_mult_1(
 .op1    (x1     ),
 .op2    (y2     ),
 .result (prod2  )
);  

signed_mult #(
.DWIDTH (DWIDTH)
)i_signed_mult_2(
 .op1    (x2     ),
 .op2    (y1     ),
 .result (prod3  )
);  

signed_mult #(
.DWIDTH (DWIDTH)
)i_signed_mult_3(
 .op1    (y1     ),
 .op2    (y2     ),
 .result (prod4  )
);  


always @(posedge clk or negedge rst_n)
if(~rst_n)   xr <= 'b0           ; else 
if(sw_rst)   xr <= 'b0           ; else 
if(op_ld)    xr <= prod1 - prod4 ;


always @(posedge clk or negedge rst_n)
if(~rst_n)   yr <= 'b0           ; else 
if(sw_rst)   yr <= 'b0           ; else 
if(op_ld)    yr <= prod2 + prod3 ;


assign res_data = {{{'d2{xr[2*DWIDTH-1]}},xr},
                   {{'d2{yr[2*DWIDTH-1]}},yr}};




endmodule