data/full_repos/permissive/494664634/AxiS2MMTest/src/hdl/AxiS2MMTest.v
data/verilator_xmls/8782da5f-17bb-4ce7-b810-c4989e6c3866.xml
module AxiWriteMaster(
  input         clock,
  input         reset,
  input         ctrl_start,
  output        ctrl_done,
  input  [31:0] ctrl_offset,
  input  [31:0] ctrl_length,
  output [31:0] m_axi_awaddr,
  output        m_axi_awvalid,
  input         m_axi_awready,
  output [31:0] m_axi_wdata,
  output        m_axi_wvalid,
  input         m_axi_wready,
  input         m_axi_bvalid,
  output        m_axi_bready,
  output [7:0]  m_axi_awlen,
  output [3:0]  m_axi_wstrb,
  output        m_axi_wlast,
  input  [31:0] s_tdata,
  input         s_tvalid,
  output        s_tready,
  input  [3:0]  s_tkeep
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
`endif
  wire  burst_cntr_clock;
  wire  burst_cntr_reset;
  wire  burst_cntr_load;
  wire  burst_cntr_decr;
  wire [7:0] burst_cntr_load_value;
  wire  burst_cntr_is_zero;
  wire  w_transaction_cntr_clock;
  wire  w_transaction_cntr_reset;
  wire  w_transaction_cntr_load;
  wire  w_transaction_cntr_decr;
  wire [23:0] w_transaction_cntr_load_value;
  wire [23:0] w_transaction_cntr_count;
  wire  w_transaction_cntr_is_zero;
  wire  w_to_aw_cntr_clock;
  wire  w_to_aw_cntr_reset;
  wire  w_to_aw_cntr_incr;
  wire  w_to_aw_cntr_decr;
  wire  w_to_aw_cntr_is_zero;
  wire  aw_transaction_cntr_clock;
  wire  aw_transaction_cntr_reset;
  wire  aw_transaction_cntr_load;
  wire  aw_transaction_cntr_decr;
  wire [23:0] aw_transaction_cntr_load_value;
  wire [23:0] aw_transaction_cntr_count;
  wire  aw_transaction_cntr_is_zero;
  wire  b_transaction_cntr_clock;
  wire  b_transaction_cntr_reset;
  wire  b_transaction_cntr_load;
  wire  b_transaction_cntr_decr;
  wire [23:0] b_transaction_cntr_load_value;
  wire [23:0] b_transaction_cntr_count;
  wire  b_transaction_cntr_is_zero;
  reg  wfirst;
  reg  wfirst_pulse;
  reg  w_almost_final_transaction;
  reg  awvalid_r;
  reg [31:0] addr;
  wire [23:0] num_full_bursts = ctrl_length[31:8];
  wire  num_partial_bursts = ctrl_length[7:0] != 8'h0;
  reg  start;
  wire [23:0] _num_transactions_T_2 = num_full_bursts - 24'h1;
  reg [23:0] num_transactions;
  reg [7:0] final_burst_len;
  wire  bxfer = m_axi_bready & m_axi_bvalid;
  wire  b_final_transaction = b_transaction_cntr_is_zero;
  wire  single_transaction = num_transactions == 24'h0;
  wire  wxfer = s_tvalid & m_axi_wready;
  wire  _wfirst_T = wxfer ? m_axi_wlast : wfirst;
  wire  _load_burst_cntr_T_2 = start & single_transaction;
  wire  load_burst_cntr = wxfer & m_axi_wlast & w_almost_final_transaction | start & single_transaction & ctrl_length
     != 32'h1;
  wire [7:0] _burst_cntr_load_value_T_4 = final_burst_len - 8'h1;
  wire [23:0] w_transactions_to_go = w_transaction_cntr_count;
  wire  awxfer = awvalid_r & m_axi_awready;
  wire  idle_aw = w_to_aw_cntr_is_zero;
  wire  _awvalid_r_T_3 = m_axi_awready ? 1'h0 : awvalid_r;
  wire [31:0] _addr_T_1 = addr + 32'h400;
  wire  aw_final_transaction = aw_transaction_cntr_is_zero;
  wire  _wfirst_dl_T = s_tvalid & wfirst;
  reg  wfirst_dl;
  UpDownLoadCounter burst_cntr (
    .clock(burst_cntr_clock),
    .reset(burst_cntr_reset),
    .load(burst_cntr_load),
    .decr(burst_cntr_decr),
    .load_value(burst_cntr_load_value),
    .is_zero(burst_cntr_is_zero)
  );
  UpDownLoadCounter_1 w_transaction_cntr (
    .clock(w_transaction_cntr_clock),
    .reset(w_transaction_cntr_reset),
    .load(w_transaction_cntr_load),
    .decr(w_transaction_cntr_decr),
    .load_value(w_transaction_cntr_load_value),
    .count(w_transaction_cntr_count),
    .is_zero(w_transaction_cntr_is_zero)
  );
  UpDownLoadCounter_2 w_to_aw_cntr (
    .clock(w_to_aw_cntr_clock),
    .reset(w_to_aw_cntr_reset),
    .incr(w_to_aw_cntr_incr),
    .decr(w_to_aw_cntr_decr),
    .is_zero(w_to_aw_cntr_is_zero)
  );
  UpDownLoadCounter_1 aw_transaction_cntr (
    .clock(aw_transaction_cntr_clock),
    .reset(aw_transaction_cntr_reset),
    .load(aw_transaction_cntr_load),
    .decr(aw_transaction_cntr_decr),
    .load_value(aw_transaction_cntr_load_value),
    .count(aw_transaction_cntr_count),
    .is_zero(aw_transaction_cntr_is_zero)
  );
  UpDownLoadCounter_1 b_transaction_cntr (
    .clock(b_transaction_cntr_clock),
    .reset(b_transaction_cntr_reset),
    .load(b_transaction_cntr_load),
    .decr(b_transaction_cntr_decr),
    .load_value(b_transaction_cntr_load_value),
    .count(b_transaction_cntr_count),
    .is_zero(b_transaction_cntr_is_zero)
  );
  assign ctrl_done = bxfer & b_final_transaction;
  assign m_axi_awaddr = addr;
  assign m_axi_awvalid = awvalid_r;
  assign m_axi_wdata = s_tdata;
  assign m_axi_wvalid = s_tvalid;
  assign m_axi_bready = 1'h1;
  assign m_axi_awlen = aw_final_transaction | _load_burst_cntr_T_2 ? final_burst_len : 8'hff;
  assign m_axi_wstrb = s_tkeep;
  assign m_axi_wlast = ctrl_length == 32'h1 ? wxfer : burst_cntr_is_zero;
  assign s_tready = m_axi_wready;
  assign burst_cntr_clock = clock;
  assign burst_cntr_reset = reset;
  assign burst_cntr_load = wxfer & m_axi_wlast & w_almost_final_transaction | start & single_transaction & ctrl_length
     != 32'h1;
  assign burst_cntr_decr = s_tvalid & m_axi_wready;
  assign burst_cntr_load_value = _load_burst_cntr_T_2 & load_burst_cntr & wxfer ? _burst_cntr_load_value_T_4 :
    final_burst_len;
  assign w_transaction_cntr_clock = clock;
  assign w_transaction_cntr_reset = reset;
  assign w_transaction_cntr_load = start;
  assign w_transaction_cntr_decr = wxfer & m_axi_wlast;
  assign w_transaction_cntr_load_value = num_transactions;
  assign w_to_aw_cntr_clock = clock;
  assign w_to_aw_cntr_reset = reset;
  assign w_to_aw_cntr_incr = wfirst_pulse;
  assign w_to_aw_cntr_decr = awvalid_r & m_axi_awready;
  assign aw_transaction_cntr_clock = clock;
  assign aw_transaction_cntr_reset = reset;
  assign aw_transaction_cntr_load = start;
  assign aw_transaction_cntr_decr = awvalid_r & m_axi_awready;
  assign aw_transaction_cntr_load_value = num_transactions;
  assign b_transaction_cntr_clock = clock;
  assign b_transaction_cntr_reset = reset;
  assign b_transaction_cntr_load = start;
  assign b_transaction_cntr_decr = m_axi_bready & m_axi_bvalid;
  assign b_transaction_cntr_load_value = num_transactions;
  always @(posedge clock) begin
    wfirst <= reset | _wfirst_T;
    if (reset) begin
      wfirst_pulse <= 1'h0;
    end else begin
      wfirst_pulse <= _wfirst_dl_T & ~wfirst_dl;
    end
    if (reset) begin
      w_almost_final_transaction <= 1'h0;
    end else begin
      w_almost_final_transaction <= w_transactions_to_go == 24'h1;
    end
    if (reset) begin
      awvalid_r <= 1'h0;
    end else begin
      awvalid_r <= ~idle_aw & ~awvalid_r | _awvalid_r_T_3;
    end
    if (reset) begin
      addr <= 32'h0;
    end else if (ctrl_start) begin
      addr <= ctrl_offset;
    end else if (awxfer) begin
      addr <= _addr_T_1;
    end
    if (reset) begin
      start <= 1'h0;
    end else begin
      start <= ctrl_start;
    end
    if (~num_partial_bursts) begin
      num_transactions <= _num_transactions_T_2;
    end else begin
      num_transactions <= num_full_bursts;
    end
    final_burst_len <= ctrl_length[7:0] - 8'h1;
    wfirst_dl <= s_tvalid & wfirst;
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  wfirst = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  wfirst_pulse = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  w_almost_final_transaction = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  awvalid_r = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  addr = _RAND_4[31:0];
  _RAND_5 = {1{`RANDOM}};
  start = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  num_transactions = _RAND_6[23:0];
  _RAND_7 = {1{`RANDOM}};
  final_burst_len = _RAND_7[7:0];
  _RAND_8 = {1{`RANDOM}};
  wfirst_dl = _RAND_8[0:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module AxiWriteMaster(
  input         clock,
  input         reset,
  input         ctrl_start,
  output        ctrl_done,
  input  [31:0] ctrl_offset,
  input  [31:0] ctrl_length,
  output [31:0] m_axi_awaddr,
  output        m_axi_awvalid,
  input         m_axi_awready,
  output [31:0] m_axi_wdata,
  output        m_axi_wvalid,
  input         m_axi_wready,
  input         m_axi_bvalid,
  output        m_axi_bready,
  output [7:0]  m_axi_awlen,
  output [3:0]  m_axi_wstrb,
  output        m_axi_wlast,
  input  [31:0] s_tdata,
  input         s_tvalid,
  output        s_tready,
  input  [3:0]  s_tkeep
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
`endif
  wire  burst_cntr_clock;
  wire  burst_cntr_reset;
  wire  burst_cntr_load;
  wire  burst_cntr_decr;
  wire [7:0] burst_cntr_load_value;
  wire  burst_cntr_is_zero;
  wire  w_transaction_cntr_clock;
  wire  w_transaction_cntr_reset;
  wire  w_transaction_cntr_load;
  wire  w_transaction_cntr_decr;
  wire [23:0] w_transaction_cntr_load_value;
  wire [23:0] w_transaction_cntr_count;
  wire  w_transaction_cntr_is_zero;
  wire  w_to_aw_cntr_clock;
  wire  w_to_aw_cntr_reset;
  wire  w_to_aw_cntr_incr;
  wire  w_to_aw_cntr_decr;
  wire  w_to_aw_cntr_is_zero;
  wire  aw_transaction_cntr_clock;
  wire  aw_transaction_cntr_reset;
  wire  aw_transaction_cntr_load;
  wire  aw_transaction_cntr_decr;
  wire [23:0] aw_transaction_cntr_load_value;
  wire [23:0] aw_transaction_cntr_count;
  wire  aw_transaction_cntr_is_zero;
  wire  b_transaction_cntr_clock;
  wire  b_transaction_cntr_reset;
  wire  b_transaction_cntr_load;
  wire  b_transaction_cntr_decr;
  wire [23:0] b_transaction_cntr_load_value;
  wire [23:0] b_transaction_cntr_count;
  wire  b_transaction_cntr_is_zero;
  reg  wfirst;
  reg  wfirst_pulse;
  reg  w_almost_final_transaction;
  reg  awvalid_r;
  reg [31:0] addr;
  wire [23:0] num_full_bursts = ctrl_length[31:8];
  wire  num_partial_bursts = ctrl_length[7:0] != 8'h0;
  reg  start;
  wire [23:0] _num_transactions_T_2 = num_full_bursts - 24'h1;
  reg [23:0] num_transactions;
  reg [7:0] final_burst_len;
  wire  bxfer = m_axi_bready & m_axi_bvalid;
  wire  b_final_transaction = b_transaction_cntr_is_zero;
  wire  single_transaction = num_transactions == 24'h0;
  wire  wxfer = s_tvalid & m_axi_wready;
  wire  _wfirst_T = wxfer ? m_axi_wlast : wfirst;
  wire  _load_burst_cntr_T_2 = start & single_transaction;
  wire  load_burst_cntr = wxfer & m_axi_wlast & w_almost_final_transaction | start & single_transaction & ctrl_length
     != 32'h1;
  wire [7:0] _burst_cntr_load_value_T_4 = final_burst_len - 8'h1;
  wire [23:0] w_transactions_to_go = w_transaction_cntr_count;
  wire  awxfer = awvalid_r & m_axi_awready;
  wire  idle_aw = w_to_aw_cntr_is_zero;
  wire  _awvalid_r_T_3 = m_axi_awready ? 1'h0 : awvalid_r;
  wire [31:0] _addr_T_1 = addr + 32'h400;
  wire  aw_final_transaction = aw_transaction_cntr_is_zero;
  wire  _wfirst_dl_T = s_tvalid & wfirst;
  reg  wfirst_dl;
  UpDownLoadCounter burst_cntr (
    .clock(burst_cntr_clock),
    .reset(burst_cntr_reset),
    .load(burst_cntr_load),
    .decr(burst_cntr_decr),
    .load_value(burst_cntr_load_value),
    .is_zero(burst_cntr_is_zero)
  );
  UpDownLoadCounter_1 w_transaction_cntr (
    .clock(w_transaction_cntr_clock),
    .reset(w_transaction_cntr_reset),
    .load(w_transaction_cntr_load),
    .decr(w_transaction_cntr_decr),
    .load_value(w_transaction_cntr_load_value),
    .count(w_transaction_cntr_count),
    .is_zero(w_transaction_cntr_is_zero)
  );
  UpDownLoadCounter_2 w_to_aw_cntr (
    .clock(w_to_aw_cntr_clock),
    .reset(w_to_aw_cntr_reset),
    .incr(w_to_aw_cntr_incr),
    .decr(w_to_aw_cntr_decr),
    .is_zero(w_to_aw_cntr_is_zero)
  );
  UpDownLoadCounter_1 aw_transaction_cntr (
    .clock(aw_transaction_cntr_clock),
    .reset(aw_transaction_cntr_reset),
    .load(aw_transaction_cntr_load),
    .decr(aw_transaction_cntr_decr),
    .load_value(aw_transaction_cntr_load_value),
    .count(aw_transaction_cntr_count),
    .is_zero(aw_transaction_cntr_is_zero)
  );
  UpDownLoadCounter_1 b_transaction_cntr (
    .clock(b_transaction_cntr_clock),
    .reset(b_transaction_cntr_reset),
    .load(b_transaction_cntr_load),
    .decr(b_transaction_cntr_decr),
    .load_value(b_transaction_cntr_load_value),
    .count(b_transaction_cntr_count),
    .is_zero(b_transaction_cntr_is_zero)
  );
  assign ctrl_done = bxfer & b_final_transaction;
  assign m_axi_awaddr = addr;
  assign m_axi_awvalid = awvalid_r;
  assign m_axi_wdata = s_tdata;
  assign m_axi_wvalid = s_tvalid;
  assign m_axi_bready = 1'h1;
  assign m_axi_awlen = aw_final_transaction | _load_burst_cntr_T_2 ? final_burst_len : 8'hff;
  assign m_axi_wstrb = s_tkeep;
  assign m_axi_wlast = ctrl_length == 32'h1 ? wxfer : burst_cntr_is_zero;
  assign s_tready = m_axi_wready;
  assign burst_cntr_clock = clock;
  assign burst_cntr_reset = reset;
  assign burst_cntr_load = wxfer & m_axi_wlast & w_almost_final_transaction | start & single_transaction & ctrl_length
     != 32'h1;
  assign burst_cntr_decr = s_tvalid & m_axi_wready;
  assign burst_cntr_load_value = _load_burst_cntr_T_2 & load_burst_cntr & wxfer ? _burst_cntr_load_value_T_4 :
    final_burst_len;
  assign w_transaction_cntr_clock = clock;
  assign w_transaction_cntr_reset = reset;
  assign w_transaction_cntr_load = start;
  assign w_transaction_cntr_decr = wxfer & m_axi_wlast;
  assign w_transaction_cntr_load_value = num_transactions;
  assign w_to_aw_cntr_clock = clock;
  assign w_to_aw_cntr_reset = reset;
  assign w_to_aw_cntr_incr = wfirst_pulse;
  assign w_to_aw_cntr_decr = awvalid_r & m_axi_awready;
  assign aw_transaction_cntr_clock = clock;
  assign aw_transaction_cntr_reset = reset;
  assign aw_transaction_cntr_load = start;
  assign aw_transaction_cntr_decr = awvalid_r & m_axi_awready;
  assign aw_transaction_cntr_load_value = num_transactions;
  assign b_transaction_cntr_clock = clock;
  assign b_transaction_cntr_reset = reset;
  assign b_transaction_cntr_load = start;
  assign b_transaction_cntr_decr = m_axi_bready & m_axi_bvalid;
  assign b_transaction_cntr_load_value = num_transactions;
  always @(posedge clock) begin
    wfirst <= reset | _wfirst_T;
    if (reset) begin
      wfirst_pulse <= 1'h0;
    end else begin
      wfirst_pulse <= _wfirst_dl_T & ~wfirst_dl;
    end
    if (reset) begin
      w_almost_final_transaction <= 1'h0;
    end else begin
      w_almost_final_transaction <= w_transactions_to_go == 24'h1;
    end
    if (reset) begin
      awvalid_r <= 1'h0;
    end else begin
      awvalid_r <= ~idle_aw & ~awvalid_r | _awvalid_r_T_3;
    end
    if (reset) begin
      addr <= 32'h0;
    end else if (ctrl_start) begin
      addr <= ctrl_offset;
    end else if (awxfer) begin
      addr <= _addr_T_1;
    end
    if (reset) begin
      start <= 1'h0;
    end else begin
      start <= ctrl_start;
    end
    if (~num_partial_bursts) begin
      num_transactions <= _num_transactions_T_2;
    end else begin
      num_transactions <= num_full_bursts;
    end
    final_burst_len <= ctrl_length[7:0] - 8'h1;
    wfirst_dl <= s_tvalid & wfirst;
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  wfirst = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  wfirst_pulse = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  w_almost_final_transaction = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  awvalid_r = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  addr = _RAND_4[31:0];
  _RAND_5 = {1{`RANDOM}};
  start = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  num_transactions = _RAND_6[23:0];
  _RAND_7 = {1{`RANDOM}};
  final_burst_len = _RAND_7[7:0];
  _RAND_8 = {1{`RANDOM}};
  wfirst_dl = _RAND_8[0:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule