data/full_repos/permissive/479094658/FA_S_testbench.v
1: b'%Error: data/full_repos/permissive/479094658/FA_S_testbench.v:12: Unsupported or unknown PLI call: $monitor\n    $monitor($time, "Cin=%b, A=%b, B=%b, Sum=%b, Cout=%b", Cin, A, B, Sum, Cout);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/479094658/FA_S_testbench.v:17: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(1, FA_S_testbench);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/479094658/FA_S_testbench.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #0  Cin=0; A=0; B=0;  \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/479094658/FA_S_testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #50 Cin=0; A=0; B=1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/479094658/FA_S_testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #50 Cin=0; A=1; B=0;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/479094658/FA_S_testbench.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #50 Cin=0; A=1; B=1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/479094658/FA_S_testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #50 Cin=1; A=0; B=0;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/479094658/FA_S_testbench.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #50 Cin=1; A=0; B=1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/479094658/FA_S_testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #50 Cin=1; A=1; B=0;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/479094658/FA_S_testbench.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #50 Cin=1; A=1; B=1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/479094658/FA_S_testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #50 $finish;\n    ^\n%Error: Exiting due to 2 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module FA_S_testbench();
  
  reg Cin, A, B;
  wire Sum, Cout;
  
  FA_S DUT (.Cin(Cin), .A(A), .B(B), .Sum(Sum), .Cout(Cout));
  
  initial
  begin
    $monitor($time, "Cin=%b, A=%b, B=%b, Sum=%b, Cout=%b", Cin, A, B, Sum, Cout);
  end
  
  initial
  begin
    $dumpvars(1, FA_S_testbench);
    #0  Cin=0; A=0; B=0;
    #50 Cin=0; A=0; B=1;
    #50 Cin=0; A=1; B=0;
    #50 Cin=0; A=1; B=1;
    #50 Cin=1; A=0; B=0;
    #50 Cin=1; A=0; B=1;
    #50 Cin=1; A=1; B=0;
    #50 Cin=1; A=1; B=1;
    #50 $finish;
  end
endmodule
module FA_S_testbench();

  
  reg Cin, A, B;
  wire Sum, Cout;
  
  FA_S DUT (.Cin(Cin), .A(A), .B(B), .Sum(Sum), .Cout(Cout));
  
  initial
  begin
    $monitor($time, "Cin=%b, A=%b, B=%b, Sum=%b, Cout=%b", Cin, A, B, Sum, Cout);
  end
  
  initial
  begin
    $dumpvars(1, FA_S_testbench);
    #0  Cin=0; A=0; B=0;
    #50 Cin=0; A=0; B=1;
    #50 Cin=0; A=1; B=0;
    #50 Cin=0; A=1; B=1;
    #50 Cin=1; A=0; B=0;
    #50 Cin=1; A=0; B=1;
    #50 Cin=1; A=1; B=0;
    #50 Cin=1; A=1; B=1;
    #50 $finish;
  end
endmodule