data/full_repos/permissive/458208177/test/32_bit_add_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/458208177/test/32_bit_add_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    initial #stop_time $finish; \n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458208177/test/32_bit_add_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #10 A[7:0] = 8\'b00000000; B[7:0] = 8\'b00000001; C0 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/458208177/test/32_bit_add_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #10 A[7:0] = 8\'b00000001; B[7:0] = 8\'b00000000; C0 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/458208177/test/32_bit_add_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #10 A[7:0] = 8\'b00000001; B[7:0] = 8\'b00000001; C0 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/458208177/test/32_bit_add_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #10 A[7:0] = 8\'b00000000; B[7:0] = 8\'b00000010; C0 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/458208177/test/32_bit_add_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #10 A[7:0] = 8\'b00000010; B[7:0] = 8\'b00000010; C0 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/458208177/test/32_bit_add_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #10 A[7:0] = 8\'b00010000; B[7:0] = 8\'b00000000; C0 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/458208177/test/32_bit_add_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #10 A[7:0] = 8\'b00000100; B[7:0] = 8\'b00010000; C0 = 0;\n        ^\n%Error: data/full_repos/permissive/458208177/test/32_bit_add_tb.v:33: Unsupported or unknown PLI call: $monitor\n        $monitor ("time = ", $time, ", x = %b y = %b S = %b C = %b",\n        ^~~~~~~~\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module t_8_bit_cla_gp;
    wire [7:0] t_S;
    wire [7:0] t_C;
    wire t_G;
    wire t_P;

    reg C0;
    reg [7:0] A;
    reg [7:0] B;

    parameter stop_time = 50;


    t_8_bit_cla_gp A1(t_ha_S, t_ha_C, G, P, C0, A, B);



    initial #stop_time $finish; 

    initial begin
            A[7:0] = 8'b00000000; B[7:0] = 8'b00000000; C0 = 0;
        #10 A[7:0] = 8'b00000000; B[7:0] = 8'b00000001; C0 = 0;
        #10 A[7:0] = 8'b00000001; B[7:0] = 8'b00000000; C0 = 0;
        #10 A[7:0] = 8'b00000001; B[7:0] = 8'b00000001; C0 = 0;
        #10 A[7:0] = 8'b00000000; B[7:0] = 8'b00000010; C0 = 0;
        #10 A[7:0] = 8'b00000010; B[7:0] = 8'b00000010; C0 = 0;
        #10 A[7:0] = 8'b00010000; B[7:0] = 8'b00000000; C0 = 0;
        #10 A[7:0] = 8'b00000100; B[7:0] = 8'b00010000; C0 = 0;
    end

    initial begin
        $monitor ("time = ", $time, ", x = %b y = %b S = %b C = %b",
            A, B, t_S, t_C);
    end
endmodule
module t_8_bit_cla_gp;

    wire [7:0] t_S;
    wire [7:0] t_C;
    wire t_G;
    wire t_P;

    reg C0;
    reg [7:0] A;
    reg [7:0] B;

    parameter stop_time = 50;


    t_8_bit_cla_gp A1(t_ha_S, t_ha_C, G, P, C0, A, B);



    initial #stop_time $finish; 

    initial begin
            A[7:0] = 8'b00000000; B[7:0] = 8'b00000000; C0 = 0;
        #10 A[7:0] = 8'b00000000; B[7:0] = 8'b00000001; C0 = 0;
        #10 A[7:0] = 8'b00000001; B[7:0] = 8'b00000000; C0 = 0;
        #10 A[7:0] = 8'b00000001; B[7:0] = 8'b00000001; C0 = 0;
        #10 A[7:0] = 8'b00000000; B[7:0] = 8'b00000010; C0 = 0;
        #10 A[7:0] = 8'b00000010; B[7:0] = 8'b00000010; C0 = 0;
        #10 A[7:0] = 8'b00010000; B[7:0] = 8'b00000000; C0 = 0;
        #10 A[7:0] = 8'b00000100; B[7:0] = 8'b00010000; C0 = 0;
    end

    initial begin
        $monitor ("time = ", $time, ", x = %b y = %b S = %b C = %b",
            A, B, t_S, t_C);
    end
endmodule