data/full_repos/permissive/423958267/lab04_3/lab04_3.srcs/sources_1/new/rom.v
data/verilator_xmls/ed0875d3-9759-402b-9d56-9480ea4deb9e.xml
module ROM(
    output reg [12:0] dout,
    input [9:0] addr,
    input clk
);

    reg [12:0] mem [1023:0];
    initial $readmemb("rom.data", mem);

    always @(posedge clk)
    begin
        dout <= mem[addr];
    end
endmodule
module ROM(
    output reg [12:0] dout,
    input [9:0] addr,
    input clk
);


    reg [12:0] mem [1023:0];
    initial $readmemb("rom.data", mem);

    always @(posedge clk)
    begin
        dout <= mem[addr];
    end
endmodule