data/full_repos/permissive/528677531/LAB-4/Q2/qb.v
1: b"%Error: data/full_repos/permissive/528677531/LAB-4/Q2/qb.v:3: Input/output/inout does not appear in port list: 'Y'\ninput [3:0]x,y,Y;\n               ^\n%Error-ASSIGNIN: data/full_repos/permissive/528677531/LAB-4/Q2/qb.v:7: Assigning to input/const variable: 'Y'\nassign Y[0]=y[0]^carryin;\n       ^\n%Error-ASSIGNIN: data/full_repos/permissive/528677531/LAB-4/Q2/qb.v:8: Assigning to input/const variable: 'Y'\nassign Y[1]=y[1]^carryin;\n       ^\n%Error-ASSIGNIN: data/full_repos/permissive/528677531/LAB-4/Q2/qb.v:9: Assigning to input/const variable: 'Y'\nassign Y[2]=y[2]^carryin;\n       ^\n%Error-ASSIGNIN: data/full_repos/permissive/528677531/LAB-4/Q2/qb.v:10: Assigning to input/const variable: 'Y'\nassign Y[3]=y[3]^carryin;\n       ^\n%Error: Exiting due to 5 error(s)\n"
module fulladd (Cin, x1, y1, s1, Cout);
input Cin, x1, y1;
output s1, Cout;
assign s1 = x1 ^ y1 ^ Cin;
assign Cout = (x1 & y1) | (x1 & Cin) | (y1 & Cin);
endmodule
module fulladd (Cin, x1, y1, s1, Cout);

input Cin, x1, y1;
output s1, Cout;
assign s1 = x1 ^ y1 ^ Cin;
assign Cout = (x1 & y1) | (x1 & Cin) | (y1 & Cin);
endmodule