data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/ADDER_STATEMACHINE.v
data/verilator_xmls/bfb3487a-d2cf-4cff-bdc1-711fc0a84ef7.xml
module ADDER_STATEMACHINE (


ADDER_STATEMACHINE_Clk,
ADDER_STATEMACHINE_Start_Routine,
ADDER_STATEMACHINE_Counter_Flag,
ADDER_STATEMACHINE_Routine_Finished_Already_Ok,


ADDER_STATEMACHINE_Mems_Re,
ADDER_STATEMACHINE_Counter_Clr,
ADDER_STATEMACHINE_Counter_En,
ADDER_STATEMACHINE_Routine_Finished_Already
);





localparam State_reset = 0;
localparam State_started = 1;
localparam State_wait_conf = 2;





input ADDER_STATEMACHINE_Clk;
input ADDER_STATEMACHINE_Start_Routine;
input ADDER_STATEMACHINE_Counter_Flag;
input ADDER_STATEMACHINE_Routine_Finished_Already_Ok;
output reg ADDER_STATEMACHINE_Mems_Re;
output reg ADDER_STATEMACHINE_Counter_Clr;
output reg ADDER_STATEMACHINE_Counter_En;
output reg ADDER_STATEMACHINE_Routine_Finished_Already;




reg [2:0] State_Register;
reg [2:0] State_Signal;


always @(*)
begin
	case (State_Register)
	
	State_reset: if (ADDER_STATEMACHINE_Start_Routine)
							State_Signal=State_started;
					 else
							State_Signal=State_reset;
	
	State_started: if (ADDER_STATEMACHINE_Counter_Flag)
							State_Signal=State_wait_conf;
						else
							State_Signal=State_started;
	
	State_wait_conf: if(ADDER_STATEMACHINE_Routine_Finished_Already_Ok)
								State_Signal=State_reset;
						  else
								State_Signal=State_wait_conf;
								
								
	
	default: State_Signal = State_reset;
	
	endcase

end




always @ (posedge ADDER_STATEMACHINE_Clk )
begin
		State_Register <= State_Signal;
end



always @ (*)
begin
	
	case(State_Register)
		
		State_reset:
		begin
			ADDER_STATEMACHINE_Mems_Re =0;
			ADDER_STATEMACHINE_Counter_Clr =0;
			ADDER_STATEMACHINE_Counter_En = 0;
			ADDER_STATEMACHINE_Routine_Finished_Already = 0;
		end
		
		State_started:
		begin
			ADDER_STATEMACHINE_Mems_Re =1;
			ADDER_STATEMACHINE_Counter_Clr =1;
			ADDER_STATEMACHINE_Counter_En = 1;
			ADDER_STATEMACHINE_Routine_Finished_Already = 0;
		end
		
		State_wait_conf:
		begin
			ADDER_STATEMACHINE_Mems_Re =0;
			ADDER_STATEMACHINE_Counter_Clr =0;
			ADDER_STATEMACHINE_Counter_En = 0;
			ADDER_STATEMACHINE_Routine_Finished_Already = 1;
		end
		
	endcase

end



endmodule
module ADDER_STATEMACHINE (


ADDER_STATEMACHINE_Clk,
ADDER_STATEMACHINE_Start_Routine,
ADDER_STATEMACHINE_Counter_Flag,
ADDER_STATEMACHINE_Routine_Finished_Already_Ok,


ADDER_STATEMACHINE_Mems_Re,
ADDER_STATEMACHINE_Counter_Clr,
ADDER_STATEMACHINE_Counter_En,
ADDER_STATEMACHINE_Routine_Finished_Already
);






localparam State_reset = 0;
localparam State_started = 1;
localparam State_wait_conf = 2;





input ADDER_STATEMACHINE_Clk;
input ADDER_STATEMACHINE_Start_Routine;
input ADDER_STATEMACHINE_Counter_Flag;
input ADDER_STATEMACHINE_Routine_Finished_Already_Ok;
output reg ADDER_STATEMACHINE_Mems_Re;
output reg ADDER_STATEMACHINE_Counter_Clr;
output reg ADDER_STATEMACHINE_Counter_En;
output reg ADDER_STATEMACHINE_Routine_Finished_Already;




reg [2:0] State_Register;
reg [2:0] State_Signal;


always @(*)
begin
	case (State_Register)
	
	State_reset: if (ADDER_STATEMACHINE_Start_Routine)
							State_Signal=State_started;
					 else
							State_Signal=State_reset;
	
	State_started: if (ADDER_STATEMACHINE_Counter_Flag)
							State_Signal=State_wait_conf;
						else
							State_Signal=State_started;
	
	State_wait_conf: if(ADDER_STATEMACHINE_Routine_Finished_Already_Ok)
								State_Signal=State_reset;
						  else
								State_Signal=State_wait_conf;
								
								
	
	default: State_Signal = State_reset;
	
	endcase

end




always @ (posedge ADDER_STATEMACHINE_Clk )
begin
		State_Register <= State_Signal;
end



always @ (*)
begin
	
	case(State_Register)
		
		State_reset:
		begin
			ADDER_STATEMACHINE_Mems_Re =0;
			ADDER_STATEMACHINE_Counter_Clr =0;
			ADDER_STATEMACHINE_Counter_En = 0;
			ADDER_STATEMACHINE_Routine_Finished_Already = 0;
		end
		
		State_started:
		begin
			ADDER_STATEMACHINE_Mems_Re =1;
			ADDER_STATEMACHINE_Counter_Clr =1;
			ADDER_STATEMACHINE_Counter_En = 1;
			ADDER_STATEMACHINE_Routine_Finished_Already = 0;
		end
		
		State_wait_conf:
		begin
			ADDER_STATEMACHINE_Mems_Re =0;
			ADDER_STATEMACHINE_Counter_Clr =0;
			ADDER_STATEMACHINE_Counter_En = 0;
			ADDER_STATEMACHINE_Routine_Finished_Already = 1;
		end
		
	endcase

end



endmodule