data/full_repos/permissive/500128826/HDLBits/Modules/Module_fadd/top_module.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/500128826/HDLBits/Modules/Module_fadd/top_module.v:34: Multiple top level modules\n                                                                                                   : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                   : ... Top module \'top_module\'\nmodule top_module (\n       ^~~~~~~~~~\n                                                                                                   : ... Top module \'add1\'\nmodule add1 (\n       ^~~~\n%Error: data/full_repos/permissive/500128826/HDLBits/Modules/Module_fadd/top_module.v:17: Cannot find file containing module: \'add16\'\n  add16 a1 (\n  ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Modules/Module_fadd,data/full_repos/permissive/500128826/add16\n             data/full_repos/permissive/500128826/HDLBits/Modules/Module_fadd,data/full_repos/permissive/500128826/add16.v\n             data/full_repos/permissive/500128826/HDLBits/Modules/Module_fadd,data/full_repos/permissive/500128826/add16.sv\n             add16\n             add16.v\n             add16.sv\n             obj_dir/add16\n             obj_dir/add16.v\n             obj_dir/add16.sv\n%Error: data/full_repos/permissive/500128826/HDLBits/Modules/Module_fadd/top_module.v:24: Cannot find file containing module: \'add16\'\n  add16 a2 (\n  ^~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module top_module (
    input wire [31:0] a,
    input wire [31:0] b,
    output wire [31:0] sum
);

  wire a1c, a2c;
  add16 a1 (
      a[15:0],
      b[15:0],
      1'b0,
      sum[15:0],
      a1c
  );
  add16 a2 (
      a[31:16],
      b[31:16],
      a1c,
      sum[31:16],
      a2c
  );

endmodule
module top_module (
    input wire [31:0] a,
    input wire [31:0] b,
    output wire [31:0] sum
);


  wire a1c, a2c;
  add16 a1 (
      a[15:0],
      b[15:0],
      1'b0,
      sum[15:0],
      a1c
  );
  add16 a2 (
      a[31:16],
      b[31:16],
      a1c,
      sum[31:16],
      a2c
  );

endmodule