data/full_repos/permissive/515624136/rtl/ALU.v
data/verilator_xmls/84450bc7-725b-4183-abac-58b88de4dd0d.xml
module ALU (


Operand_1,
Operand_2,
Opcode,


Out

);























parameter DATAWIDTH=32;

parameter  ADD   = 4'b0000,
			  SUB   = 4'b0001,
			  SLL   = 4'b0010,
			  SLT   = 4'b0011,
			  SLTU  = 4'b0100,
			  XOR   = 4'b0101,
			  SRL   = 4'b0110,
			  SRA   = 4'b0111,
			  OR    = 4'b1000,
			  AND   = 4'b1001,
			  BUFFB = 4'b1010,
			  BUFFA = 4'b1011;





input [DATAWIDTH-1:0] Operand_1;
input [DATAWIDTH-1:0] Operand_2;
input [3:0] Opcode;
output[DATAWIDTH-1:0] Out;





reg [DATAWIDTH-1:0] tmp;





always @(Operand_1,Operand_2,Opcode)
begin

	case(Opcode)
		ADD: tmp = Operand_1+Operand_2;
		SUB: tmp = Operand_1-Operand_2;
		SLL: tmp = Operand_1 << Operand_2[4:0];
		SLT: tmp = ($signed(Operand_1) < $signed(Operand_2)) ? 32'd1 : 32'd0;
	   SLTU: tmp = (Operand_1 < Operand_2) ? 32'd1 : 32'd0;
		XOR: tmp = Operand_1^Operand_2;
		SRL: tmp = Operand_1 >> Operand_2[4:0];
		SRA: tmp = $signed(Operand_1) >> Operand_2[4:0];
		OR:  tmp = Operand_1|Operand_2;
		AND: tmp = Operand_1&Operand_2;	
		BUFFB: tmp= Operand_2;
		BUFFA: tmp= Operand_1;
		
		default tmp= 32'd0;
		
	endcase

end



assign Out=tmp;

endmodule
module ALU (


Operand_1,
Operand_2,
Opcode,


Out

);
























parameter DATAWIDTH=32;

parameter  ADD   = 4'b0000,
			  SUB   = 4'b0001,
			  SLL   = 4'b0010,
			  SLT   = 4'b0011,
			  SLTU  = 4'b0100,
			  XOR   = 4'b0101,
			  SRL   = 4'b0110,
			  SRA   = 4'b0111,
			  OR    = 4'b1000,
			  AND   = 4'b1001,
			  BUFFB = 4'b1010,
			  BUFFA = 4'b1011;





input [DATAWIDTH-1:0] Operand_1;
input [DATAWIDTH-1:0] Operand_2;
input [3:0] Opcode;
output[DATAWIDTH-1:0] Out;





reg [DATAWIDTH-1:0] tmp;





always @(Operand_1,Operand_2,Opcode)
begin

	case(Opcode)
		ADD: tmp = Operand_1+Operand_2;
		SUB: tmp = Operand_1-Operand_2;
		SLL: tmp = Operand_1 << Operand_2[4:0];
		SLT: tmp = ($signed(Operand_1) < $signed(Operand_2)) ? 32'd1 : 32'd0;
	   SLTU: tmp = (Operand_1 < Operand_2) ? 32'd1 : 32'd0;
		XOR: tmp = Operand_1^Operand_2;
		SRL: tmp = Operand_1 >> Operand_2[4:0];
		SRA: tmp = $signed(Operand_1) >> Operand_2[4:0];
		OR:  tmp = Operand_1|Operand_2;
		AND: tmp = Operand_1&Operand_2;	
		BUFFB: tmp= Operand_2;
		BUFFA: tmp= Operand_1;
		
		default tmp= 32'd0;
		
	endcase

end



assign Out=tmp;

endmodule