data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_explicit.v
data/verilator_xmls/f03dde19-de5e-4fc0-924d-ebf22c995b3a.xml
module dff (q, q_bar, clk, d, rst, pre);
input clk, d, rst, pre;
output q, q_bar;
reg q;

assign q_bar = ~q;

always @ (posedge clk)
if (rst == 1'b1) begin
  q <= 0;
end else if (pre == 1'b1) begin
  q <= 1;
end else begin
  q <= d;
end

endmodule
module dff (q, q_bar, clk, d, rst, pre);

input clk, d, rst, pre;
output q, q_bar;
reg q;

assign q_bar = ~q;

always @ (posedge clk)
if (rst == 1'b1) begin
  q <= 0;
end else if (pre == 1'b1) begin
  q <= 1;
end else begin
  q <= d;
end

endmodule