data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/router_output_port_lookup_v1_0_0/hdl/ip_checksum_ttl.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/router_output_port_lookup_v1_0_0/hdl/ip_checksum_ttl.v:198: Unsupported: Ignoring delay on this delayed statement.\n            #100 $stop;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/router_output_port_lookup_v1_0_0/hdl/ip_checksum_ttl.v:78: Cannot find file containing module: \'fallthrough_small_fifo\'\n   fallthrough_small_fifo #(.WIDTH(26), .MAX_DEPTH_BITS(2))\n   ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/router_output_port_lookup_v1_0_0/hdl,data/full_repos/permissive/498471995/fallthrough_small_fifo\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/router_output_port_lookup_v1_0_0/hdl,data/full_repos/permissive/498471995/fallthrough_small_fifo.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/router_output_port_lookup_v1_0_0/hdl,data/full_repos/permissive/498471995/fallthrough_small_fifo.sv\n             fallthrough_small_fifo\n             fallthrough_small_fifo.v\n             fallthrough_small_fifo.sv\n             obj_dir/fallthrough_small_fifo\n             obj_dir/fallthrough_small_fifo.v\n             obj_dir/fallthrough_small_fifo.sv\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/router_output_port_lookup_v1_0_0/hdl/ip_checksum_ttl.v:92: Cannot find file containing module: \'fallthrough_small_fifo\'\n   fallthrough_small_fifo #(.WIDTH(1), .MAX_DEPTH_BITS(2))\n   ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/router_output_port_lookup_v1_0_0/hdl/ip_checksum_ttl.v:119: Operator ADD expects 20 bits on the LHS, but LHS\'s SEL generates 16 bits.\n                                                                                                                                                                    : ... In instance ip_checksum_ttl\n  cksm_sum_0_next = tdata[143:128]+tdata[127:112]+tdata[111:96];\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/router_output_port_lookup_v1_0_0/hdl/ip_checksum_ttl.v:119: Operator ADD expects 20 bits on the RHS, but RHS\'s SEL generates 16 bits.\n                                                                                                                                                                    : ... In instance ip_checksum_ttl\n  cksm_sum_0_next = tdata[143:128]+tdata[127:112]+tdata[111:96];\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/router_output_port_lookup_v1_0_0/hdl/ip_checksum_ttl.v:119: Operator ADD expects 20 bits on the RHS, but RHS\'s SEL generates 16 bits.\n                                                                                                                                                                    : ... In instance ip_checksum_ttl\n  cksm_sum_0_next = tdata[143:128]+tdata[127:112]+tdata[111:96];\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/router_output_port_lookup_v1_0_0/hdl/ip_checksum_ttl.v:120: Operator ADD expects 20 bits on the LHS, but LHS\'s SEL generates 16 bits.\n                                                                                                                                                                    : ... In instance ip_checksum_ttl\n  cksm_sum_1_next = tdata[95:80]+tdata[79:64];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/router_output_port_lookup_v1_0_0/hdl/ip_checksum_ttl.v:120: Operator ADD expects 20 bits on the RHS, but RHS\'s SEL generates 16 bits.\n                                                                                                                                                                    : ... In instance ip_checksum_ttl\n  cksm_sum_1_next = tdata[95:80]+tdata[79:64];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/router_output_port_lookup_v1_0_0/hdl/ip_checksum_ttl.v:121: Operator ADD expects 20 bits on the LHS, but LHS\'s SEL generates 16 bits.\n                                                                                                                                                                    : ... In instance ip_checksum_ttl\n  cksm_sum_2_next = tdata[63:48]+tdata[47:32];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/router_output_port_lookup_v1_0_0/hdl/ip_checksum_ttl.v:121: Operator ADD expects 20 bits on the RHS, but RHS\'s SEL generates 16 bits.\n                                                                                                                                                                    : ... In instance ip_checksum_ttl\n  cksm_sum_2_next = tdata[63:48]+tdata[47:32];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/router_output_port_lookup_v1_0_0/hdl/ip_checksum_ttl.v:122: Operator ADD expects 20 bits on the LHS, but LHS\'s SEL generates 16 bits.\n                                                                                                                                                                    : ... In instance ip_checksum_ttl\n  cksm_sum_3_next = tdata[31:16]+tdata[15:0];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/router_output_port_lookup_v1_0_0/hdl/ip_checksum_ttl.v:122: Operator ADD expects 20 bits on the RHS, but RHS\'s SEL generates 16 bits.\n                                                                                                                                                                    : ... In instance ip_checksum_ttl\n  cksm_sum_3_next = tdata[31:16]+tdata[15:0];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/router_output_port_lookup_v1_0_0/hdl/ip_checksum_ttl.v:125: Operator ADD expects 20 bits on the RHS, but RHS\'s SEL generates 16 bits.\n                                                                                                                                                                    : ... In instance ip_checksum_ttl\n  checksum_next = cksm_temp + cksm_temp2 + tdata[255:240];\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/router_output_port_lookup_v1_0_0/hdl/ip_checksum_ttl.v:128: Operator ADD expects 20 bits on the LHS, but LHS\'s SEL generates 4 bits.\n                                                                                                                                                                    : ... In instance ip_checksum_ttl\n  checksum_next = checksum[19:16] + checksum[15:0];\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/router_output_port_lookup_v1_0_0/hdl/ip_checksum_ttl.v:128: Operator ADD expects 20 bits on the RHS, but RHS\'s SEL generates 16 bits.\n                                                                                                                                                                    : ... In instance ip_checksum_ttl\n  checksum_next = checksum[19:16] + checksum[15:0];\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/router_output_port_lookup_v1_0_0/hdl/ip_checksum_ttl.v:168: Operator ADD expects 17 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                                                                                                    : ... In instance ip_checksum_ttl\n            adjusted_checksum <= {1\'h0, adjusted_checksum[15:0]} + adjusted_checksum[16];\n                                                                 ^\n%Error: Exiting due to 2 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ip_checksum_ttl
  #(parameter C_S_AXIS_DATA_WIDTH=256)
  (

   input  [C_S_AXIS_DATA_WIDTH-1:0]   tdata,
   input                              valid,


   input                              word_IP_DST_HI,
   input                              word_IP_DST_LO,


   output                             ip_checksum_vld,
   output                             ip_checksum_is_good,
   output                             ip_hdr_has_options,
   output                             ip_ttl_is_good,
   output     [7:0]                   ip_new_ttl,
   output     [15:0]                  ip_new_checksum,
   input                              rd_checksum,


   input reset,
   input clk
   );


   reg	[19:0]	checksum, checksum_next;
   reg	[16:0]	adjusted_checksum;
   reg		checksum_done;
   reg		info_ready;
   wire		empty;
   reg	[7:0]	ttl_new;
   reg		ttl_good;
   reg		hdr_has_options;
   reg		add_carry;
   reg	add_carry_d1;

   reg	[19:0]	cksm_sum_0, cksm_sum_1, cksm_sum_0_next, cksm_sum_1_next, cksm_sum_2, cksm_sum_2_next, cksm_sum_3, cksm_sum_3_next;
   wire	[19:0]	cksm_temp,cksm_temp2;



   fallthrough_small_fifo #(.WIDTH(26), .MAX_DEPTH_BITS(2))
      info_fifo
        (.din ({adjusted_checksum[15:0], ttl_good, ttl_new, hdr_has_options}),
         .wr_en (info_ready),
         .rd_en (rd_checksum),
         .dout ({ip_new_checksum, ip_ttl_is_good, ip_new_ttl, ip_hdr_has_options}),
         .full (),
         .nearly_full (),
         .prog_full (),
         .empty (),
         .reset (reset),
         .clk (clk)
         );

   fallthrough_small_fifo #(.WIDTH(1), .MAX_DEPTH_BITS(2))
      cksm_fifo
        (.din (&checksum[15:0]),
         .wr_en (checksum_done),
         .rd_en (rd_checksum),
         .dout (ip_checksum_is_good),
         .full (),
         .nearly_full (),
         .prog_full (),
         .empty (empty),
         .reset (reset),
         .clk (clk)
         );


   assign ip_checksum_vld = !empty;

   assign cksm_temp = cksm_sum_0 + cksm_sum_1;
   assign cksm_temp2 = cksm_sum_2 + cksm_sum_3;

   always @(*) begin
      checksum_next = checksum;
      cksm_sum_0_next = cksm_sum_0;
      cksm_sum_1_next = cksm_sum_1;
      cksm_sum_2_next = cksm_sum_2;
      cksm_sum_3_next = cksm_sum_3;
      if(word_IP_DST_HI) begin
	 cksm_sum_0_next = tdata[143:128]+tdata[127:112]+tdata[111:96];
	 cksm_sum_1_next = tdata[95:80]+tdata[79:64];
	 cksm_sum_2_next = tdata[63:48]+tdata[47:32];
	 cksm_sum_3_next = tdata[31:16]+tdata[15:0];
      end
      if(word_IP_DST_LO) begin
	 checksum_next = cksm_temp + cksm_temp2 + tdata[255:240];
      end
      if(add_carry) begin
	 checksum_next = checksum[19:16] + checksum[15:0];
      end
   end




   always @(posedge clk) begin
      if(reset) begin
         adjusted_checksum	<= 17'h0;
         checksum_done		<= 0;
         ttl_new		<= 0;
         ttl_good		<= 0;
         hdr_has_options	<= 0;
         info_ready		<= 0;
	 checksum		<= 20'h0;
         add_carry		<= 0;
	 add_carry_d1		<= 0;

         cksm_sum_0		<= 0;
         cksm_sum_1		<= 0;
         cksm_sum_2		<= 0;
         cksm_sum_3		<= 0;
      end
      else begin
	 checksum <= checksum_next;
         cksm_sum_0 <= cksm_sum_0_next;
         cksm_sum_1 <= cksm_sum_1_next;
         cksm_sum_2 <= cksm_sum_2_next;
         cksm_sum_3 <= cksm_sum_3_next;


         if(word_IP_DST_HI) begin
	    hdr_has_options	<= (tdata[143:136]!=8'h45);
	    ttl_new		<= (tdata[79:72]==8'h0) ? 8'h0 : tdata[79:72] - 1'b1;
	    ttl_good		<= (tdata[79:72] > 8'h1);
	    adjusted_checksum	<= {1'h0, tdata[63:48]} + 17'h0100;
         end

         if(word_IP_DST_LO) begin
            adjusted_checksum	<= {1'h0, adjusted_checksum[15:0]} + adjusted_checksum[16];
            info_ready		<= 1;
            add_carry		<= 1;
         end
         else begin
            info_ready	<= 0;
            add_carry	<= 0;
         end

         if(add_carry) begin
	    add_carry_d1 <= 1;	
         end
	 else
            add_carry_d1 <= 0;


	 if(add_carry_d1) begin
	    checksum_done <= 1;
	    add_carry <= 0;		
	 end

         else begin
            checksum_done <= 0;
         end



         if (checksum_done && checksum[19:16] != 4'h0) begin
            $display("%t %m ERROR: top 4 bits of checksum_word_0 not zero - algo wrong???",
                     $time);
            #100 $stop;
         end


      end
   end

endmodule
module ip_checksum_ttl
  #(parameter C_S_AXIS_DATA_WIDTH=256)
  (

   input  [C_S_AXIS_DATA_WIDTH-1:0]   tdata,
   input                              valid,


   input                              word_IP_DST_HI,
   input                              word_IP_DST_LO,


   output                             ip_checksum_vld,
   output                             ip_checksum_is_good,
   output                             ip_hdr_has_options,
   output                             ip_ttl_is_good,
   output     [7:0]                   ip_new_ttl,
   output     [15:0]                  ip_new_checksum,
   input                              rd_checksum,


   input reset,
   input clk
   );



   reg	[19:0]	checksum, checksum_next;
   reg	[16:0]	adjusted_checksum;
   reg		checksum_done;
   reg		info_ready;
   wire		empty;
   reg	[7:0]	ttl_new;
   reg		ttl_good;
   reg		hdr_has_options;
   reg		add_carry;
   reg	add_carry_d1;

   reg	[19:0]	cksm_sum_0, cksm_sum_1, cksm_sum_0_next, cksm_sum_1_next, cksm_sum_2, cksm_sum_2_next, cksm_sum_3, cksm_sum_3_next;
   wire	[19:0]	cksm_temp,cksm_temp2;



   fallthrough_small_fifo #(.WIDTH(26), .MAX_DEPTH_BITS(2))
      info_fifo
        (.din ({adjusted_checksum[15:0], ttl_good, ttl_new, hdr_has_options}),
         .wr_en (info_ready),
         .rd_en (rd_checksum),
         .dout ({ip_new_checksum, ip_ttl_is_good, ip_new_ttl, ip_hdr_has_options}),
         .full (),
         .nearly_full (),
         .prog_full (),
         .empty (),
         .reset (reset),
         .clk (clk)
         );

   fallthrough_small_fifo #(.WIDTH(1), .MAX_DEPTH_BITS(2))
      cksm_fifo
        (.din (&checksum[15:0]),
         .wr_en (checksum_done),
         .rd_en (rd_checksum),
         .dout (ip_checksum_is_good),
         .full (),
         .nearly_full (),
         .prog_full (),
         .empty (empty),
         .reset (reset),
         .clk (clk)
         );


   assign ip_checksum_vld = !empty;

   assign cksm_temp = cksm_sum_0 + cksm_sum_1;
   assign cksm_temp2 = cksm_sum_2 + cksm_sum_3;

   always @(*) begin
      checksum_next = checksum;
      cksm_sum_0_next = cksm_sum_0;
      cksm_sum_1_next = cksm_sum_1;
      cksm_sum_2_next = cksm_sum_2;
      cksm_sum_3_next = cksm_sum_3;
      if(word_IP_DST_HI) begin
	 cksm_sum_0_next = tdata[143:128]+tdata[127:112]+tdata[111:96];
	 cksm_sum_1_next = tdata[95:80]+tdata[79:64];
	 cksm_sum_2_next = tdata[63:48]+tdata[47:32];
	 cksm_sum_3_next = tdata[31:16]+tdata[15:0];
      end
      if(word_IP_DST_LO) begin
	 checksum_next = cksm_temp + cksm_temp2 + tdata[255:240];
      end
      if(add_carry) begin
	 checksum_next = checksum[19:16] + checksum[15:0];
      end
   end




   always @(posedge clk) begin
      if(reset) begin
         adjusted_checksum	<= 17'h0;
         checksum_done		<= 0;
         ttl_new		<= 0;
         ttl_good		<= 0;
         hdr_has_options	<= 0;
         info_ready		<= 0;
	 checksum		<= 20'h0;
         add_carry		<= 0;
	 add_carry_d1		<= 0;

         cksm_sum_0		<= 0;
         cksm_sum_1		<= 0;
         cksm_sum_2		<= 0;
         cksm_sum_3		<= 0;
      end
      else begin
	 checksum <= checksum_next;
         cksm_sum_0 <= cksm_sum_0_next;
         cksm_sum_1 <= cksm_sum_1_next;
         cksm_sum_2 <= cksm_sum_2_next;
         cksm_sum_3 <= cksm_sum_3_next;


         if(word_IP_DST_HI) begin
	    hdr_has_options	<= (tdata[143:136]!=8'h45);
	    ttl_new		<= (tdata[79:72]==8'h0) ? 8'h0 : tdata[79:72] - 1'b1;
	    ttl_good		<= (tdata[79:72] > 8'h1);
	    adjusted_checksum	<= {1'h0, tdata[63:48]} + 17'h0100;
         end

         if(word_IP_DST_LO) begin
            adjusted_checksum	<= {1'h0, adjusted_checksum[15:0]} + adjusted_checksum[16];
            info_ready		<= 1;
            add_carry		<= 1;
         end
         else begin
            info_ready	<= 0;
            add_carry	<= 0;
         end

         if(add_carry) begin
	    add_carry_d1 <= 1;	
         end
	 else
            add_carry_d1 <= 0;


	 if(add_carry_d1) begin
	    checksum_done <= 1;
	    add_carry <= 0;		
	 end

         else begin
            checksum_done <= 0;
         end



         if (checksum_done && checksum[19:16] != 4'h0) begin
            $display("%t %m ERROR: top 4 bits of checksum_word_0 not zero - algo wrong???",
                     $time);
            #100 $stop;
         end


      end
   end

endmodule