data/full_repos/permissive/414822257/ip/randsack/rtl/ringosc_macro.v
1: b"%Error: data/full_repos/permissive/414822257/ip/randsack/rtl/ringosc_macro.v:34: Cannot find file containing module: 'ring_osc2x13'\n  ring_osc2x13 ring (\n  ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/414822257/ip/randsack/rtl,data/full_repos/permissive/414822257/ring_osc2x13\n             data/full_repos/permissive/414822257/ip/randsack/rtl,data/full_repos/permissive/414822257/ring_osc2x13.v\n             data/full_repos/permissive/414822257/ip/randsack/rtl,data/full_repos/permissive/414822257/ring_osc2x13.sv\n             ring_osc2x13\n             ring_osc2x13.v\n             ring_osc2x13.sv\n             obj_dir/ring_osc2x13\n             obj_dir/ring_osc2x13.v\n             obj_dir/ring_osc2x13.sv\n%Error: Exiting due to 1 error(s)\n"
module ringosc_macro #(
  parameter TRIM_BITS = 26
) (
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif

  input start,
  input [TRIM_BITS-1:0] trim_a,
  input [2:0] clkmux,

  output clk_out
);

  wire [1:0] clockp;
  wire clk = clockp[0];

  ring_osc2x13 ring (
    .reset(~start),
    .trim(trim_a),
    .clockp(clockp)
  );


  reg s0;
  always @(posedge clk or negedge start) begin
    if (!start) begin
      s0 <= 1'b0;
    end else begin
      s0 <= ~s0;
    end
  end

  reg s1;
  always @(posedge s0 or negedge start) begin
    if (!start) begin
      s1 <= 1'b0;
    end else begin
      s1 <= ~s1;
    end
  end

  reg s2;
  always @(posedge s1 or negedge start) begin
    if (!start) begin
      s2 <= 1'b0;
    end else begin
      s2 <= ~s2;
    end
  end

  assign clk_out = (clkmux == 3'b000) ? clk :
                   (clkmux == 3'b001) ? s0  :
                   (clkmux == 3'b010) ? s1  :
                   (clkmux == 3'b011) ? s2  :
                   clk;

endmodule
module ringosc_macro #(
  parameter TRIM_BITS = 26
) (
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif

  input start,
  input [TRIM_BITS-1:0] trim_a,
  input [2:0] clkmux,

  output clk_out
);


  wire [1:0] clockp;
  wire clk = clockp[0];

  ring_osc2x13 ring (
    .reset(~start),
    .trim(trim_a),
    .clockp(clockp)
  );


  reg s0;
  always @(posedge clk or negedge start) begin
    if (!start) begin
      s0 <= 1'b0;
    end else begin
      s0 <= ~s0;
    end
  end

  reg s1;
  always @(posedge s0 or negedge start) begin
    if (!start) begin
      s1 <= 1'b0;
    end else begin
      s1 <= ~s1;
    end
  end

  reg s2;
  always @(posedge s1 or negedge start) begin
    if (!start) begin
      s2 <= 1'b0;
    end else begin
      s2 <= ~s2;
    end
  end

  assign clk_out = (clkmux == 3'b000) ? clk :
                   (clkmux == 3'b001) ? s0  :
                   (clkmux == 3'b010) ? s1  :
                   (clkmux == 3'b011) ? s2  :
                   clk;

endmodule