data/full_repos/permissive/452305748/L8/UART_RXer/UART_RXer_tb.v
1: b'%Error: data/full_repos/permissive/452305748/L8/UART_RXer/UART_RXer_tb.v:24: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("wave.vcd");         \n        ^~~~~~~~~\n%Error: data/full_repos/permissive/452305748/L8/UART_RXer/UART_RXer_tb.v:25: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, UART_RXer_tb);     \n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/452305748/L8/UART_RXer/UART_RXer_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #17 rstn <= 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/452305748/L8/UART_RXer/UART_RXer_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #4000000 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452305748/L8/UART_RXer/UART_RXer_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk <= ~clk;\n           ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module UART_RXer_tb ();
    
    reg   clk,rstn;
    wire  RX;
    wire [7:0] data_out;
    wire en_data_out;
    

    reg [25:0] RX_send;
    assign RX = RX_send;
    reg [12:0] con;
    
    UART_RXer UART_RXer(
    clk,
    rstn,
    RX,
    en_data_out,
    data_out
    );
    

    initial
    begin
        $dumpfile("wave.vcd");
        $dumpvars(0, UART_RXer_tb);
    end


    initial begin
        clk     <= 0;
        rstn    <= 0;
        RX_send <= {1'b1, 8'haa, 1'b0, 16'hffff};
        con     <= 0;
        #17 rstn <= 1;
        #4000000 $finish;
    end
    
    always #5 clk <= ~clk;
    
    always @(posedge clk) begin
        if (con == 5000 - 1) begin
            con <= 0;
        end
        else begin
            con <= con + 1;
        end
        

        if (con == 0) begin
            RX_send[24:0] <= RX_send[25:1];
            RX_send[25]   <= RX_send[0];
        end
    end
    
endmodule
module UART_RXer_tb ();

    
    reg   clk,rstn;
    wire  RX;
    wire [7:0] data_out;
    wire en_data_out;
    

    reg [25:0] RX_send;
    assign RX = RX_send;
    reg [12:0] con;
    
    UART_RXer UART_RXer(
    clk,
    rstn,
    RX,
    en_data_out,
    data_out
    );
    

    initial
    begin
        $dumpfile("wave.vcd");
        $dumpvars(0, UART_RXer_tb);
    end


    initial begin
        clk     <= 0;
        rstn    <= 0;
        RX_send <= {1'b1, 8'haa, 1'b0, 16'hffff};
        con     <= 0;
        #17 rstn <= 1;
        #4000000 $finish;
    end
    
    always #5 clk <= ~clk;
    
    always @(posedge clk) begin
        if (con == 5000 - 1) begin
            con <= 0;
        end
        else begin
            con <= con + 1;
        end
        

        if (con == 0) begin
            RX_send[24:0] <= RX_send[25:1];
            RX_send[25]   <= RX_send[0];
        end
    end
    
endmodule