data/full_repos/permissive/412284801/adders/fullsubtractor/b_fullsub.v
data/verilator_xmls/b5000b79-532d-453d-93b8-c816b048b71e.xml
module b_fullsub(a,b,bin,bout,d);
    input a,b,bin;
    output reg bout,d;
    reg w,d1,b1,b2;
    always@(*)begin
        d = (a^b)^bin;
        bout = ((~a)&bin)|((~a)&b)|(b&bin);
    end
endmodule
module b_fullsub(a,b,bin,bout,d);

    input a,b,bin;
    output reg bout,d;
    reg w,d1,b1,b2;
    always@(*)begin
        d = (a^b)^bin;
        bout = ((~a)&bin)|((~a)&b)|(b&bin);
    end
endmodule