data/full_repos/permissive/495950911/src/shift_register_line.v
data/verilator_xmls/a865c7db-99be-4611-8853-fec839920cce.xml
module shift_register_line #(
    parameter TOTAL_TAPS = 9,
    parameter BITS_PER_TAP = 8,
    parameter TOTAL_BITS = 9 * 8
) (

    input wire clk,


    input wire rst,


    input wire signed [BITS_PER_TAP - 1:0] i_value,


    input wire i_data_clk,


    output wire o_start_calc,


    output reg [TOTAL_BITS - 1:0] o_taps
);

  reg stb;
  reg start_calc;
  reg data_clk_previous;
  reg data_clk_two_previous;

  initial begin
    o_taps = 0;
    stb = 0;
    start_calc = 0;
    data_clk_previous = 0;
    data_clk_two_previous = 0;
  end

  always @(posedge clk) begin
    if (rst) begin
      o_taps <= 0;
      stb <= 0;
      start_calc <= 0;
      data_clk_previous <= 0;
      data_clk_two_previous <= 0;
    end else begin
      o_taps <= o_taps;
      start_calc <= 0;
      if (i_data_clk & ~data_clk_previous & ~data_clk_two_previous) begin
        o_taps <= {o_taps[((TOTAL_BITS-1)-BITS_PER_TAP):0], i_value};
        start_calc <= 1;
      end
      data_clk_previous <= i_data_clk;
      data_clk_two_previous <= data_clk_previous;

    end
  end

  assign o_start_calc = start_calc;

endmodule
module shift_register_line #(
    parameter TOTAL_TAPS = 9,
    parameter BITS_PER_TAP = 8,
    parameter TOTAL_BITS = 9 * 8
) (

    input wire clk,


    input wire rst,


    input wire signed [BITS_PER_TAP - 1:0] i_value,


    input wire i_data_clk,


    output wire o_start_calc,


    output reg [TOTAL_BITS - 1:0] o_taps
);


  reg stb;
  reg start_calc;
  reg data_clk_previous;
  reg data_clk_two_previous;

  initial begin
    o_taps = 0;
    stb = 0;
    start_calc = 0;
    data_clk_previous = 0;
    data_clk_two_previous = 0;
  end

  always @(posedge clk) begin
    if (rst) begin
      o_taps <= 0;
      stb <= 0;
      start_calc <= 0;
      data_clk_previous <= 0;
      data_clk_two_previous <= 0;
    end else begin
      o_taps <= o_taps;
      start_calc <= 0;
      if (i_data_clk & ~data_clk_previous & ~data_clk_two_previous) begin
        o_taps <= {o_taps[((TOTAL_BITS-1)-BITS_PER_TAP):0], i_value};
        start_calc <= 1;
      end
      data_clk_previous <= i_data_clk;
      data_clk_two_previous <= data_clk_previous;

    end
  end

  assign o_start_calc = start_calc;

endmodule