data/full_repos/permissive/458737381/src/verilog-parser/tests/ccx_global_int_buf.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ccx_global_int_buf.v:23: Cannot find include file: sys.h\n`include "sys.h" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ccx_global_int_buf.v:24: Cannot find include file: iop.h\n`include "iop.h" \n         ^~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module ccx_global_int_buf(

   rst_l_buf, se_buf, adbginit_l_buf, 

   rst_l, se, adbginit_l
   );
   output          rst_l_buf ;
   output          se_buf ;
   output          adbginit_l_buf ;
   

   input 	   rst_l ;	
   input          se ;
   input          adbginit_l ;

   
   assign               rst_l_buf    =  rst_l;
   assign               se_buf    =  se;
   assign               adbginit_l_buf  =  adbginit_l ;


endmodule
module ccx_global_int_buf(

   rst_l_buf, se_buf, adbginit_l_buf, 

   rst_l, se, adbginit_l
   );

   output          rst_l_buf ;
   output          se_buf ;
   output          adbginit_l_buf ;
   

   input 	   rst_l ;	
   input          se ;
   input          adbginit_l ;

   
   assign               rst_l_buf    =  rst_l;
   assign               se_buf    =  se;
   assign               adbginit_l_buf  =  adbginit_l ;


endmodule