data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/MICROBENCHMARKS/bm_add_lpm.v
data/verilator_xmls/bbf22013-50a3-4002-abf2-e18d34890285.xml
module bm_add_lpm(clock,
		reset_n,
		a_in,
		b_in,
		out);


input	clock;
input 	reset_n;

input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;

output [`BITS-1:0] out;

wire [`BITS-1:0]    out;


assign out = a_in + b_in;

endmodule
module bm_add_lpm(clock,
		reset_n,
		a_in,
		b_in,
		out);



input	clock;
input 	reset_n;

input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;

output [`BITS-1:0] out;

wire [`BITS-1:0]    out;


assign out = a_in + b_in;

endmodule