data/full_repos/permissive/43856783/Integrador/adder.v
data/verilator_xmls/d1fff808-f488-4914-94dd-931c8e57b47e.xml
module adder(
    input [32:0] A,
    input [15:0] B,
    output reg [32:0] R
    );
	 
	 always @(*) begin
		R[32:17] <= A[32:17] + B;
		R[16:0]	<= A[16:0];
	 end
	 
endmodule
module adder(
    input [32:0] A,
    input [15:0] B,
    output reg [32:0] R
    );

	 
	 always @(*) begin
		R[32:17] <= A[32:17] + B;
		R[16:0]	<= A[16:0];
	 end
	 
endmodule