data/full_repos/permissive/429462627/mips_pipeline.v
1: b'%Error: data/full_repos/permissive/429462627/mips_pipeline.v:138: Unsupported or unknown PLI call: $monitor\n        $monitor($time, " :A = %b,\\n\\t B = %b,\\n\\t ALU_ctrlerartion = %b,\\n\\t Result = %b,\\n\\t Carry Out = %b,\\n\\t Zero = %b.", A, B, ALU_ctrl, result, carry_out, zero);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:139: Unsupported: Ignoring delay on this delayed statement.\n        #0  A = 32\'ha5a5a5a5; B = 32\'h5a5a5a5a; ALU_ctrl = 4\'b0000;      \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:140: Unsupported: Ignoring delay on this delayed statement.\n        #10  ALU_ctrl = 4\'b0001;                                         \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:141: Unsupported: Ignoring delay on this delayed statement.\n        #10  ALU_ctrl = 4\'b0010;                                         \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:142: Unsupported: Ignoring delay on this delayed statement.\n        #10  ALU_ctrl = 4\'b0110;                                         \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:143: Unsupported: Ignoring delay on this delayed statement.\n        #10  A = 32\'hA5A5A5A5; B = 32\'hA5A5A5A5; ALU_ctrl = 4\'b0110;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:144: Unsupported: Ignoring delay on this delayed statement.\n        #10  B = 32\'hA5A5A5A5; A = 32\'h5A5A5A5A; ALU_ctrl = 4\'b0111;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:145: Unsupported: Ignoring delay on this delayed statement.\n        #10  B = 32\'hA5A5A5A5; A = 32\'h5A5A5A5A; ALU_ctrl = 4\'b1100;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:146: Unsupported: Ignoring delay on this delayed statement.\n        #20  $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:1090: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk = ~clk;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:1096: Unsupported: Ignoring delay on this delayed statement.\n        #5 reset = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:1098: Unsupported: Ignoring delay on this delayed statement.\n        #300 $finish;\n        ^\n%Error: Exiting due to 1 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module instruction_memory (
    input reset,
    input[31:0] read_addr,
    output [31:0] instruction);

    reg [31:0] inst_memory [0:31];
    
    wire [29:0] shifted_read_addr;
    assign shifted_read_addr = read_addr [31:2];
    assign instruction = inst_memory [shifted_read_addr];

    integer i;
    always @(posedge reset)
    begin

        for (i=0; i<32; i=i+1) 
        begin
           inst_memory[i] = 32'b0;
        end
        inst_memory[0] = 32'b00000000000000000000000000000000;
        inst_memory[1] = 32'b100011_00000_10001_0000000000001000;
        inst_memory[2] = 32'b100011_00000_10010_0000000000000100;
        inst_memory[3] = 32'b101011_10011_00000_0000000000001100;
        inst_memory[4] = 32'b000100_10001_10001_0000000000000010;
        inst_memory[5] = 32'b00000000000000000000000000000000;
        inst_memory[6] = 32'b00000000000000000000000000000000;
        inst_memory[7] = 32'b000000_10001_10010_01000_00000_100000;
        inst_memory[8] = 32'b000000_10001_10010_01001_00000_100010;
        inst_memory[9] = 32'b000000_10001_10010_01010_00000_100100;
        inst_memory[10] = 32'b000000_10001_10010_01011_00000_100101;
        inst_memory[11] = 32'b000000_10001_10010_01100_00000_101010;
        inst_memory[12] = 32'b001000_10001_01101_0000000000001111;
        inst_memory[13] = 32'b001100_10001_01110_1010101010101010;
        inst_memory[14] = 32'b001101_10001_01111_1111000011110000;
        inst_memory[15] = 32'b001010_10001_10100_0000000000000000;
        inst_memory[16] = 32'b000100_10001_10010_0000000000000100;
        inst_memory[17] = 32'b00000000000000000000000000000000;
        inst_memory[18] = 32'b00000000000000000000000000000000;
        inst_memory[19] = 32'b00000000000000000000000000000000;
        inst_memory[20] = 32'b00000000000000000000000000000000;
        inst_memory[21] = 32'b00000000000000000000000000000000;
        inst_memory[22] = 32'b00000000000000000000000000000000;
        inst_memory[23] = 32'b00000000000000000000000000000000;
        inst_memory[24] = 32'b00000000000000000000000000000000;
        inst_memory[25] = 32'b00000000000000000000000000000000;
        inst_memory[26] = 32'b00000000000000000000000000000000;
        inst_memory[27] = 32'b00000000000000000000000000000000;
        inst_memory[28] = 32'b00000000000000000000000000000000;
        inst_memory[29] = 32'b00000000000000000000000000000000;
        inst_memory[30] = 32'b00000000000000000000000000000000;
        inst_memory[31] = 32'b00000000000000000000000000000000;
    end
endmodule
module instruction_memory (
    input reset,
    input[31:0] read_addr,
    output [31:0] instruction);


    reg [31:0] inst_memory [0:31];
    
    wire [29:0] shifted_read_addr;
    assign shifted_read_addr = read_addr [31:2];
    assign instruction = inst_memory [shifted_read_addr];

    integer i;
    always @(posedge reset)
    begin

        for (i=0; i<32; i=i+1) 
        begin
           inst_memory[i] = 32'b0;
        end
        inst_memory[0] = 32'b00000000000000000000000000000000;
        inst_memory[1] = 32'b100011_00000_10001_0000000000001000;
        inst_memory[2] = 32'b100011_00000_10010_0000000000000100;
        inst_memory[3] = 32'b101011_10011_00000_0000000000001100;
        inst_memory[4] = 32'b000100_10001_10001_0000000000000010;
        inst_memory[5] = 32'b00000000000000000000000000000000;
        inst_memory[6] = 32'b00000000000000000000000000000000;
        inst_memory[7] = 32'b000000_10001_10010_01000_00000_100000;
        inst_memory[8] = 32'b000000_10001_10010_01001_00000_100010;
        inst_memory[9] = 32'b000000_10001_10010_01010_00000_100100;
        inst_memory[10] = 32'b000000_10001_10010_01011_00000_100101;
        inst_memory[11] = 32'b000000_10001_10010_01100_00000_101010;
        inst_memory[12] = 32'b001000_10001_01101_0000000000001111;
        inst_memory[13] = 32'b001100_10001_01110_1010101010101010;
        inst_memory[14] = 32'b001101_10001_01111_1111000011110000;
        inst_memory[15] = 32'b001010_10001_10100_0000000000000000;
        inst_memory[16] = 32'b000100_10001_10010_0000000000000100;
        inst_memory[17] = 32'b00000000000000000000000000000000;
        inst_memory[18] = 32'b00000000000000000000000000000000;
        inst_memory[19] = 32'b00000000000000000000000000000000;
        inst_memory[20] = 32'b00000000000000000000000000000000;
        inst_memory[21] = 32'b00000000000000000000000000000000;
        inst_memory[22] = 32'b00000000000000000000000000000000;
        inst_memory[23] = 32'b00000000000000000000000000000000;
        inst_memory[24] = 32'b00000000000000000000000000000000;
        inst_memory[25] = 32'b00000000000000000000000000000000;
        inst_memory[26] = 32'b00000000000000000000000000000000;
        inst_memory[27] = 32'b00000000000000000000000000000000;
        inst_memory[28] = 32'b00000000000000000000000000000000;
        inst_memory[29] = 32'b00000000000000000000000000000000;
        inst_memory[30] = 32'b00000000000000000000000000000000;
        inst_memory[31] = 32'b00000000000000000000000000000000;
    end
endmodule