data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v
1: b'%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v:10: Cannot find include file: simulate_x_tick.vh\n`include "simulate_x_tick.vh" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master,data/full_repos/permissive/437632408/simulate_x_tick.vh\n             data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master,data/full_repos/permissive/437632408/simulate_x_tick.vh.v\n             data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master,data/full_repos/permissive/437632408/simulate_x_tick.vh.sv\n             simulate_x_tick.vh\n             simulate_x_tick.vh.v\n             simulate_x_tick.vh.sv\n             obj_dir/simulate_x_tick.vh\n             obj_dir/simulate_x_tick.vh.v\n             obj_dir/simulate_x_tick.vh.sv\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v:96: Define or directive not defined: \'`x_or_0\'\n            wr_req_in <= `x_or_0;\n                         ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v:96: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            wr_req_in <= `x_or_0;\n                                ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v:132: Define or directive not defined: \'`x_or_0\'\n            wr_count <= {2{`x_or_0}};\n                           ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v:132: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n            wr_count <= {2{`x_or_0}};\n                                  ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v:185: Define or directive not defined: \'`x_or_0\'\n            rd_adr <= {1{`x_or_0}};\n                         ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v:185: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n            rd_adr <= {1{`x_or_0}};\n                                ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v:365: Define or directive not defined: \'`x_or_0\'\n            rd_count_p <= {2{`x_or_0}};\n                             ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v:365: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n            rd_count_p <= {2{`x_or_0}};\n                                    ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v:386: Define or directive not defined: \'`x_or_0\'\n        NV_AFIFO_rd_data <= {34{`x_or_0}};\n                                ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v:386: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n        NV_AFIFO_rd_data <= {34{`x_or_0}};\n                                       ^\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v:643: Define or directive not defined: \'`x_or_0\'\n    default: dout = {34{`x_or_0}};\n                        ^~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v:643: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n    default: dout = {34{`x_or_0}};\n                               ^\n%Error: Exiting due to 13 error(s)\n'
module NV_NVDLA_CSB_MASTER_csb2falcon_fifo_gray_cntr (
      clk
    , reset_
    , inc
    , gray
    );
input clk;
input reset_;
input inc;
output [1:0] gray;
reg [1:0] gray;
wire polarity;
assign polarity = gray[0] ^ gray[1];
  always @( posedge clk or negedge reset_ ) begin
    if ( !reset_ ) begin
 gray <= 2'd0;
    end else if ( inc ) begin
        gray <= { gray[1]^(polarity ),
                         gray[0]^(~polarity) };
    end
end
endmodule
module NV_NVDLA_CSB_MASTER_csb2falcon_fifo_gray_cntr (
      clk
    , reset_
    , inc
    , gray
    );

input clk;
input reset_;
input inc;
output [1:0] gray;
reg [1:0] gray;
wire polarity;
assign polarity = gray[0] ^ gray[1];
  always @( posedge clk or negedge reset_ ) begin
    if ( !reset_ ) begin
 gray <= 2'd0;
    end else if ( inc ) begin
        gray <= { gray[1]^(polarity ),
                         gray[0]^(~polarity) };
    end
end
endmodule