data/full_repos/permissive/449071180/tb_move_register.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_move_register.v:29: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_move_register.v:31: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_move_register.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_move_register.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_move_register.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_move_register.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Error: data/full_repos/permissive/449071180/tb_move_register.v:12: Cannot find file containing module: \'move_register\'\nmove_register port_map(\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/move_register\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/move_register.v\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/move_register.sv\n             move_register\n             move_register.v\n             move_register.sv\n             obj_dir/move_register\n             obj_dir/move_register.v\n             obj_dir/move_register.sv\n%Warning-WIDTH: data/full_repos/permissive/449071180/tb_move_register.v:28: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                          : ... In instance tb_move_register\nload_test = 2\'b0;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/449071180/tb_move_register.v:41: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_test1\' generates 32 bits.\n                                                                          : ... In instance tb_move_register\n  load_test = input_test1;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/449071180/tb_move_register.v:52: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'input_test2\' generates 32 bits.\n                                                                          : ... In instance tb_move_register\n  pos_test = input_test2;\n           ^\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_move_register();
reg clk_test,reset_test,shift_test;
reg [2:0] load_test;
reg [5:0] pos_test;
wire [2:0] out_head_test,out_pos_test;

integer input_test0;
integer input_test1;
integer input_test2;


move_register port_map(
.clk(clk_test),
.reset(reset_test),
.load(load_test),
.pos(pos_test),
.out_head(out_head_test),
.out_pos(out_pos_test),
.shift(shift_test)

);

initial begin 
shift_test = 0;
clk_test = 0;
reset_test = 0;
pos_test = 6'b0;
load_test = 2'b0;
#5;
reset_test = 1;
#5;
reset_test = 0;
end

always begin 

	shift_test = 1;
	
	for(input_test0 = 0; input_test0 < 16; input_test0 = input_test0 + 1) begin
		for(input_test1 = 0;input_test1 < 4; input_test1 = input_test1 + 1) begin
		load_test = input_test1;
		#5;
		clk_test = 1;
		#5;
		clk_test = 0;
		end
	end
	
	shift_test = 0;
	
	for(input_test2 = 0; input_test2 < 64; input_test2 = input_test2 + 1) begin
		pos_test = input_test2;
		#5;
		clk_test = 1;
		#5;
		clk_test = 0;
	end
end

endmodule
module tb_move_register();

reg clk_test,reset_test,shift_test;
reg [2:0] load_test;
reg [5:0] pos_test;
wire [2:0] out_head_test,out_pos_test;

integer input_test0;
integer input_test1;
integer input_test2;


move_register port_map(
.clk(clk_test),
.reset(reset_test),
.load(load_test),
.pos(pos_test),
.out_head(out_head_test),
.out_pos(out_pos_test),
.shift(shift_test)

);

initial begin 
shift_test = 0;
clk_test = 0;
reset_test = 0;
pos_test = 6'b0;
load_test = 2'b0;
#5;
reset_test = 1;
#5;
reset_test = 0;
end

always begin 

	shift_test = 1;
	
	for(input_test0 = 0; input_test0 < 16; input_test0 = input_test0 + 1) begin
		for(input_test1 = 0;input_test1 < 4; input_test1 = input_test1 + 1) begin
		load_test = input_test1;
		#5;
		clk_test = 1;
		#5;
		clk_test = 0;
		end
	end
	
	shift_test = 0;
	
	for(input_test2 = 0; input_test2 < 64; input_test2 = input_test2 + 1) begin
		pos_test = input_test2;
		#5;
		clk_test = 1;
		#5;
		clk_test = 0;
	end
end

endmodule