data/full_repos/permissive/475371394/generators/cgra4x3/src/main/resources/memoryPort_4connect_32b.v
1: b"%Error: data/full_repos/permissive/475371394/generators/cgra4x3/src/main/resources/memoryPort_4connect_32b.v:29: Cannot find file containing module: 'ConfigCell'\n    ConfigCell #(2) MuxAddr (\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/475371394/generators/cgra4x3/src/main/resources,data/full_repos/permissive/475371394/ConfigCell\n             data/full_repos/permissive/475371394/generators/cgra4x3/src/main/resources,data/full_repos/permissive/475371394/ConfigCell.v\n             data/full_repos/permissive/475371394/generators/cgra4x3/src/main/resources,data/full_repos/permissive/475371394/ConfigCell.sv\n             ConfigCell\n             ConfigCell.v\n             ConfigCell.sv\n             obj_dir/ConfigCell\n             obj_dir/ConfigCell.v\n             obj_dir/ConfigCell.sv\n%Error: data/full_repos/permissive/475371394/generators/cgra4x3/src/main/resources/memoryPort_4connect_32b.v:35: Cannot find file containing module: 'ConfigCell'\n    ConfigCell #(2) MuxData (\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/475371394/generators/cgra4x3/src/main/resources/memoryPort_4connect_32b.v:41: Cannot find file containing module: 'ConfigCell'\n    ConfigCell #(1) WriteRq (\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/475371394/generators/cgra4x3/src/main/resources/memoryPort_4connect_32b.v:49: Cannot find file containing module: 'mux_4to1_32b'\n    mux_4to1_32b #(32) mux_addr(\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/475371394/generators/cgra4x3/src/main/resources/memoryPort_4connect_32b.v:56: Cannot find file containing module: 'mux_4to1_32b'\n    mux_4to1_32b #(32) mux_data(\n    ^~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module memoryPort_4connect_32b(Config_Clock, Config_Reset, ConfigIn, ConfigOut, in0, in1, in2, in3, out, write_rq, from_mem, to_mem, addr);

    input Config_Clock, Config_Reset, ConfigIn;
    output ConfigOut;
    input [31:0] in0;
    input [31:0] in1;
    input [31:0] in2;
    input [31:0] in3;
    input [31:0] from_mem;
    output [31:0] out;
    output write_rq;
    output [31:0] addr;
    output [31:0] to_mem;


    wire [1:0] MuxAddr_sig;
    wire MuxAddr_config;
    wire [1:0] MuxData_sig;
    wire MuxData_config;
    wire WriteRq_sig;
    wire WriteRq_config;


    wire [31:0] mux_addr_out_sig;
    wire [31:0] mux_data_out_sig;


    ConfigCell #(2) MuxAddr (
        .Config_Clock(Config_Clock),
        .Config_Reset(Config_Reset),
        .ConfigIn(ConfigIn),
        .ConfigOut(MuxAddr_config),
        .select(MuxAddr_sig));
    ConfigCell #(2) MuxData (
        .Config_Clock(Config_Clock),
        .Config_Reset(Config_Reset),
        .ConfigIn(MuxAddr_config),
        .ConfigOut(MuxData_config),
        .select(MuxData_sig));
    ConfigCell #(1) WriteRq (
        .Config_Clock(Config_Clock),
        .Config_Reset(Config_Reset),
        .ConfigIn(MuxData_config),
        .ConfigOut(WriteRq_config),
        .select(WriteRq_sig));


    mux_4to1_32b #(32) mux_addr(
        .in0(in0),
        .in1(in1),
        .in2(in2),
        .in3(in3),
        .out(mux_addr_out_sig),
        .select(MuxAddr_sig));
    mux_4to1_32b #(32) mux_data(
        .in0(in0),
        .in1(in1),
        .in2(in2),
        .in3(in3),
        .out(mux_data_out_sig),
        .select(MuxData_sig));
    assign write_rq     = WriteRq_sig;
    assign to_mem       = mux_data_out_sig;
    assign addr         = mux_addr_out_sig;
    assign out          = from_mem;
    
    assign ConfigOut = WriteRq_config;
endmodule
module memoryPort_4connect_32b(Config_Clock, Config_Reset, ConfigIn, ConfigOut, in0, in1, in2, in3, out, write_rq, from_mem, to_mem, addr);


    input Config_Clock, Config_Reset, ConfigIn;
    output ConfigOut;
    input [31:0] in0;
    input [31:0] in1;
    input [31:0] in2;
    input [31:0] in3;
    input [31:0] from_mem;
    output [31:0] out;
    output write_rq;
    output [31:0] addr;
    output [31:0] to_mem;


    wire [1:0] MuxAddr_sig;
    wire MuxAddr_config;
    wire [1:0] MuxData_sig;
    wire MuxData_config;
    wire WriteRq_sig;
    wire WriteRq_config;


    wire [31:0] mux_addr_out_sig;
    wire [31:0] mux_data_out_sig;


    ConfigCell #(2) MuxAddr (
        .Config_Clock(Config_Clock),
        .Config_Reset(Config_Reset),
        .ConfigIn(ConfigIn),
        .ConfigOut(MuxAddr_config),
        .select(MuxAddr_sig));
    ConfigCell #(2) MuxData (
        .Config_Clock(Config_Clock),
        .Config_Reset(Config_Reset),
        .ConfigIn(MuxAddr_config),
        .ConfigOut(MuxData_config),
        .select(MuxData_sig));
    ConfigCell #(1) WriteRq (
        .Config_Clock(Config_Clock),
        .Config_Reset(Config_Reset),
        .ConfigIn(MuxData_config),
        .ConfigOut(WriteRq_config),
        .select(WriteRq_sig));


    mux_4to1_32b #(32) mux_addr(
        .in0(in0),
        .in1(in1),
        .in2(in2),
        .in3(in3),
        .out(mux_addr_out_sig),
        .select(MuxAddr_sig));
    mux_4to1_32b #(32) mux_data(
        .in0(in0),
        .in1(in1),
        .in2(in2),
        .in3(in3),
        .out(mux_data_out_sig),
        .select(MuxData_sig));
    assign write_rq     = WriteRq_sig;
    assign to_mem       = mux_data_out_sig;
    assign addr         = mux_addr_out_sig;
    assign out          = from_mem;
    
    assign ConfigOut = WriteRq_config;
endmodule