data/full_repos/permissive/487568919/basic_verilog/reverse_dimensions.sv
data/verilator_xmls/c2339ad0-0b17-4653-90cb-384b3dc52c81.xml
module reverse_dimensions #( parameter
  D1_WIDTH = 8,
  D2_WIDTH = 3
)(
  input [D1_WIDTH-1:0][D2_WIDTH-1:0] in,
  output logic [D2_WIDTH-1:0][D1_WIDTH-1:0] out
);


genvar i;
genvar j;
generate
  for (i = 0; i < D1_WIDTH ; i++) begin : gen_i
  for (j = 0; j < D2_WIDTH ; j++) begin : gen_j

    always_comb begin
      out[j][i] = in[i][j];
    end

  end
  end
endgenerate

endmodule
module reverse_dimensions #( parameter
  D1_WIDTH = 8,
  D2_WIDTH = 3
)(
  input [D1_WIDTH-1:0][D2_WIDTH-1:0] in,
  output logic [D2_WIDTH-1:0][D1_WIDTH-1:0] out
);



genvar i;
genvar j;
generate
  for (i = 0; i < D1_WIDTH ; i++) begin : gen_i
  for (j = 0; j < D2_WIDTH ; j++) begin : gen_j

    always_comb begin
      out[j][i] = in[i][j];
    end

  end
  end
endgenerate

endmodule