data/full_repos/permissive/443520440/code/bluetooth_uart_driver.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/443520440/code/bluetooth_uart_driver.v:125: Multiple top level modules\n                                                                                        : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                        : ... Top module \'uart_recv\'\nmodule uart_recv(\n       ^~~~~~~~~\n                                                                                        : ... Top module \'uart_send\'\nmodule uart_send(\n       ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/443520440/code/bluetooth_uart_driver.v:176: Operator EQ expects 32 or 27 bits on the LHS, but LHS\'s VARREF \'clk_cnt\' generates 16 bits.\n                                                                                     : ... In instance uart_send\n        end else if ((tx_cnt == 4\'d9)&&(clk_cnt == BPS_CNT/2)) begin \n                                                ^~\n%Warning-WIDTH: data/full_repos/permissive/443520440/code/bluetooth_uart_driver.v:193: Operator LT expects 32 or 27 bits on the LHS, but LHS\'s VARREF \'clk_cnt\' generates 16 bits.\n                                                                                     : ... In instance uart_send\n            if (clk_cnt < BPS_CNT - 1) begin\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/443520440/code/bluetooth_uart_driver.v:52: Operator EQ expects 32 or 27 bits on the LHS, but LHS\'s VARREF \'clk_cnt\' generates 16 bits.\n                                                                                    : ... In instance uart_recv\n            else if((rx_cnt == 4\'d9)&&(clk_cnt == BPS_CNT/2))\n                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/443520440/code/bluetooth_uart_driver.v:67: Operator LT expects 32 or 27 bits on the LHS, but LHS\'s VARREF \'clk_cnt\' generates 16 bits.\n                                                                                    : ... In instance uart_recv\n                if (clk_cnt < BPS_CNT - 1) begin\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/443520440/code/bluetooth_uart_driver.v:87: Operator EQ expects 32 or 27 bits on the LHS, but LHS\'s VARREF \'clk_cnt\' generates 16 bits.\n                                                                                    : ... In instance uart_recv\n            if (clk_cnt == BPS_CNT/2) begin\n                        ^~\n%Error: Exiting due to 6 warning(s)\n'
module uart_send(
    input               sys_clk     ,
    input               sys_rst_n   ,
    input               uart_en     ,
    input  [7:0]        uart_din    , 
    output  reg         uart_txd
    );


    parameter  CLK_FREQ = 100000000; 
    parameter  UART_BPS = 9600;
    localparam BPS_CNT  = CLK_FREQ/UART_BPS;


 
    reg [15:0]      clk_cnt;
    reg [ 3:0]      tx_cnt;
    reg             tx_flag;
    reg [ 7:0]      tx_data;
    wire            en_flag;


    reg             uart_en_0; 
    reg             uart_en_1; 
    assign en_flag = (~uart_en_1) & uart_en_0;                                         
    always @(posedge sys_clk or negedge sys_rst_n) begin         
        if (!sys_rst_n) begin
            uart_en_0 <= 1'b0;                                  
            uart_en_1 <= 1'b0;
        end else begin                                               
            uart_en_0 <= uart_en;                               
            uart_en_1 <= uart_en_0;                            
        end
    end


    always @(posedge sys_clk or negedge sys_rst_n) begin         
        if (!sys_rst_n) begin                                  
            tx_flag <= 1'b0;
            tx_data <= 8'd0;
        end else if (en_flag) begin                 
            tx_flag <= 1'b1;
            tx_data <= uart_din;
        end else if ((tx_cnt == 4'd9)&&(clk_cnt == BPS_CNT/2)) begin 
            tx_flag <= 1'b0;
            tx_data <= 8'd0;
        end else begin
            tx_flag <= tx_flag;
            tx_data <= tx_data;
        end 
    end


    always @(posedge sys_clk or negedge sys_rst_n) begin         
        if (!sys_rst_n) begin                             
            clk_cnt <= 16'd0;                                  
            tx_cnt  <= 4'd0;
        end  else if (tx_flag) begin
            if (clk_cnt < BPS_CNT - 1) begin
                clk_cnt <= clk_cnt + 1'b1;
                tx_cnt  <= tx_cnt;
            end else begin
                clk_cnt <= 16'd0;
                tx_cnt  <= tx_cnt + 1'b1;
            end
        end else begin
            clk_cnt <= 16'd0;
            tx_cnt  <= 4'd0;
        end
    end


    always @(posedge sys_clk or negedge sys_rst_n) begin        
        if (!sys_rst_n)  
            uart_txd <= 1'b1;        
        else if (tx_flag)
            case(tx_cnt)
                4'd0: uart_txd <= 1'b0;
                4'd1: uart_txd <= tx_data[0];
                4'd2: uart_txd <= tx_data[1];
                4'd3: uart_txd <= tx_data[2];
                4'd4: uart_txd <= tx_data[3];
                4'd5: uart_txd <= tx_data[4];
                4'd6: uart_txd <= tx_data[5];
                4'd7: uart_txd <= tx_data[6];
                4'd8: uart_txd <= tx_data[7];
                4'd9: uart_txd <= 1'b1;
                default: ;
            endcase
        else 
            uart_txd <= 1'b1;
    end
endmodule
module uart_send(
    input               sys_clk     ,
    input               sys_rst_n   ,
    input               uart_en     ,
    input  [7:0]        uart_din    , 
    output  reg         uart_txd
    );



    parameter  CLK_FREQ = 100000000; 
    parameter  UART_BPS = 9600;
    localparam BPS_CNT  = CLK_FREQ/UART_BPS;


 
    reg [15:0]      clk_cnt;
    reg [ 3:0]      tx_cnt;
    reg             tx_flag;
    reg [ 7:0]      tx_data;
    wire            en_flag;


    reg             uart_en_0; 
    reg             uart_en_1; 
    assign en_flag = (~uart_en_1) & uart_en_0;                                         
    always @(posedge sys_clk or negedge sys_rst_n) begin         
        if (!sys_rst_n) begin
            uart_en_0 <= 1'b0;                                  
            uart_en_1 <= 1'b0;
        end else begin                                               
            uart_en_0 <= uart_en;                               
            uart_en_1 <= uart_en_0;                            
        end
    end


    always @(posedge sys_clk or negedge sys_rst_n) begin         
        if (!sys_rst_n) begin                                  
            tx_flag <= 1'b0;
            tx_data <= 8'd0;
        end else if (en_flag) begin                 
            tx_flag <= 1'b1;
            tx_data <= uart_din;
        end else if ((tx_cnt == 4'd9)&&(clk_cnt == BPS_CNT/2)) begin 
            tx_flag <= 1'b0;
            tx_data <= 8'd0;
        end else begin
            tx_flag <= tx_flag;
            tx_data <= tx_data;
        end 
    end


    always @(posedge sys_clk or negedge sys_rst_n) begin         
        if (!sys_rst_n) begin                             
            clk_cnt <= 16'd0;                                  
            tx_cnt  <= 4'd0;
        end  else if (tx_flag) begin
            if (clk_cnt < BPS_CNT - 1) begin
                clk_cnt <= clk_cnt + 1'b1;
                tx_cnt  <= tx_cnt;
            end else begin
                clk_cnt <= 16'd0;
                tx_cnt  <= tx_cnt + 1'b1;
            end
        end else begin
            clk_cnt <= 16'd0;
            tx_cnt  <= 4'd0;
        end
    end


    always @(posedge sys_clk or negedge sys_rst_n) begin        
        if (!sys_rst_n)  
            uart_txd <= 1'b1;        
        else if (tx_flag)
            case(tx_cnt)
                4'd0: uart_txd <= 1'b0;
                4'd1: uart_txd <= tx_data[0];
                4'd2: uart_txd <= tx_data[1];
                4'd3: uart_txd <= tx_data[2];
                4'd4: uart_txd <= tx_data[3];
                4'd5: uart_txd <= tx_data[4];
                4'd6: uart_txd <= tx_data[5];
                4'd7: uart_txd <= tx_data[6];
                4'd8: uart_txd <= tx_data[7];
                4'd9: uart_txd <= 1'b1;
                default: ;
            endcase
        else 
            uart_txd <= 1'b1;
    end
endmodule