data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_explicit_mem/cachelib/v_rtl/dut_Add_7Sx2S_8S_1.v
data/verilator_xmls/af0bcd4d-739a-44fe-bca4-957db9b749d5.xml
module dut_Add_7Sx2S_8S_1 (
	in2,
	in1,
	out1
	);
input [6:0] in2;
input [1:0] in1;
output [7:0] out1;
wire [7:0] asc001;

assign asc001 = 
	+({in2[6], in2})
	+({{6{in1[1]}}, in1});

assign out1 = asc001;
endmodule
module dut_Add_7Sx2S_8S_1 (
	in2,
	in1,
	out1
	);

input [6:0] in2;
input [1:0] in1;
output [7:0] out1;
wire [7:0] asc001;

assign asc001 = 
	+({in2[6], in2})
	+({{6{in1[1]}}, in1});

assign out1 = asc001;
endmodule