data/full_repos/permissive/446312960/Verilog_Simulation/02_mux/mux_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/02_mux/mux_test.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/02_mux/mux_test.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #100;   \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/02_mux/mux_test.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #100;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/02_mux/mux_test.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #100;   \n    ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux_test(t1, t2, t3, p);
output t1, t2, t3;
input p;

reg t1,t2,t3;

initial begin

    t1 <= 1;
    t2 <= 0;
    t3 <= 0;

    #100;
    t3 <= 0;

    #100;   
    t3 <= 1;

    #100;  
    t3 <= 0;
    
    #100;   
    t3 <= 1;

    $finish;
end

endmodule
module mux_test(t1, t2, t3, p);

output t1, t2, t3;
input p;

reg t1,t2,t3;

initial begin

    t1 <= 1;
    t2 <= 0;
    t3 <= 0;

    #100;
    t3 <= 0;

    #100;   
    t3 <= 1;

    #100;  
    t3 <= 0;
    
    #100;   
    t3 <= 1;

    $finish;
end

endmodule