data/full_repos/permissive/421048855/Verilog Language/More Verilog Features/Bcdadd100.v
1: b'%Error: Cannot find file containing module: Language/More\n        ... Looked in:\n             data/full_repos/permissive/421048855/Verilog/Language/More\n             data/full_repos/permissive/421048855/Verilog/Language/More.v\n             data/full_repos/permissive/421048855/Verilog/Language/More.sv\n             Language/More\n             Language/More.v\n             Language/More.sv\n             obj_dir/Language/More\n             obj_dir/Language/More.v\n             obj_dir/Language/More.sv\n%Error: Cannot find file containing module: Verilog\n%Error: Cannot find file containing module: Features,data/full_repos/permissive/421048855\n%Error: Cannot find file containing module: data/full_repos/permissive/421048855/Verilog\n%Error: Cannot find file containing module: Features/Bcdadd100.v\n%Error: Exiting due to 5 error(s)\n'
module top_module( 
    input [399:0] a, b,
    input cin,
    output cout,
    output [399:0] sum );
    wire [99:0] cout_t;
generate
    genvar i;
    for(i=0;i<100;i=i+1) begin:bcdadd
        if(i==0) begin
            bcd_fadd u_bcd_fadd_0(a[3:0],b[3:0],cin,cout_t[0],sum[3:0]);
        end
        else begin
            bcd_fadd u_bcd_fadd_i(a[i*4+3:i*4],b[i*4+3:i*4],cout_t[i-1],cout_t[i],sum[i*4+3:i*4]);
        end
    end
endgenerate
    assign cout = cout_t[99];
endmodule
module top_module( 
    input [399:0] a, b,
    input cin,
    output cout,
    output [399:0] sum );

    wire [99:0] cout_t;
generate
    genvar i;
    for(i=0;i<100;i=i+1) begin:bcdadd
        if(i==0) begin
            bcd_fadd u_bcd_fadd_0(a[3:0],b[3:0],cin,cout_t[0],sum[3:0]);
        end
        else begin
            bcd_fadd u_bcd_fadd_i(a[i*4+3:i*4],b[i*4+3:i*4],cout_t[i-1],cout_t[i],sum[i*4+3:i*4]);
        end
    end
endgenerate
    assign cout = cout_t[99];
endmodule