data/full_repos/permissive/436037353/src/Control.v
data/verilator_xmls/4b3a56ef-f16e-4155-8966-6a9a0a318bba.xml
module Control(
	instructionInput,
	regWrite,
	memWrite,
	useEA,
	ALUOP,
	memRead,
	linkSrc,
	memToReg,
	branchControl);
	
	
	input [3:0]			instructionInput;
	
	output reg			regWrite;
	output reg			memWrite;
	output reg			useEA;
	output reg [3:0]	ALUOP;
	output reg			memRead;
	output reg			linkSrc;
	output reg			memToReg;
	output reg [1:0]	branchControl;
	
	always@(*) begin
	
		ALUOP <= instructionInput;
	
		case(instructionInput)
			
			'b0000:
				begin
					linkSrc <= 0;
					memWrite <= 0;
					memRead <= 0;
					memToReg <= 0;
					regWrite <= 0;
					useEA <= 0;
					branchControl <= 0;
				end
				
			4'b0001:
				begin
					linkSrc <= 0;
					memWrite <= 0;
					memRead <= 0;
					memToReg <= 0;
					regWrite <= 1;
					useEA <= 0;
					branchControl <= 0;
				end	
			4'b0010:
				begin
					linkSrc <= 0;
					memWrite <= 0;
					memRead <= 0;
					memToReg <= 0;
					regWrite <= 1;
					useEA <= 0;
					branchControl <= 0;
				end	
				
			4'b0011:
				begin
					linkSrc <= 0;
					memWrite <= 0;
					memRead <= 0;
					memToReg <= 0;
					regWrite <= 1;
					useEA <= 0;
					branchControl <= 0;
				end
				
			4'b0100:
				begin
					linkSrc <= 0;
					memWrite <= 0;
					memRead <= 0;
					memToReg <= 0;
					regWrite <= 1;
					useEA <= 0;
					branchControl <= 0;
				end
				
			4'b0101:
				begin
					linkSrc <= 0;
					memWrite <= 0;
					memRead <= 0;
					memToReg <= 0;
					regWrite <= 1;
					useEA <= 0;
					branchControl <= 0;
				end
				
			4'b0110:
				begin
					linkSrc <= 0;
					memWrite <= 0;
					memRead <= 0;
					memToReg <= 0;
					regWrite <= 0;
					useEA <= 0;
					branchControl <= 0;
				end
				
			4'b0111:
				begin
					linkSrc <= 0;
					memWrite <= 0;
					memRead <= 0;
					memToReg <= 0;
					regWrite <= 1;
					useEA <= 0;
					branchControl <= 0;
				end	
				
			4'b1000:
				begin
					linkSrc <= 0;
					memWrite <= 0;
					memRead <= 0;
					memToReg <= 0;
					regWrite <= 1;
					useEA <= 0;
					branchControl <= 0;	
				end
				
			4'b1001:
				begin
					linkSrc <= 1;
					memWrite <= 0;
					memRead <= 0;
					memToReg <= 0;
					regWrite <= 0;
					useEA <= 1;
					branchControl <= 0;
				end	
				
			4'b1010:
				begin
					linkSrc <= 1;
					memWrite <= 0;
					memRead <= 0;
					memToReg <= 0;
					regWrite <= 0;
					useEA <= 1;
					branchControl <= 1;
				end
			4'b1011:
				begin
					linkSrc <= 1;
					memWrite <= 0;
					memRead <= 0;
					memToReg <= 0;
					regWrite <= 0;
					useEA <= 1;
					branchControl <= 2;	
				end
				
			4'b1100:
				begin
					linkSrc <= 1;
					memWrite <= 0;
					memRead <= 0;
					memToReg <= 0;
					regWrite <= 0;
					useEA <= 1;
					branchControl <= 3;
				end
				
			4'b1101:
				begin
					linkSrc <= 0;
					memWrite <= 0;
					memRead <= 1;
					memToReg <= 1;
					regWrite <= 1;
					useEA <= 1;
					branchControl <= 0;
				end
				
			4'b1110:
				begin
					linkSrc <= 0;
					memWrite <= 1;
					memRead <= 0;
					memToReg <= 0;
					regWrite <= 0;
					useEA <= 1;
					branchControl <= 0;
				end
			
			4'b1111:
				begin
					linkSrc <= 0;
					memWrite <= 0;
					memRead <= 0;
					memToReg <= 0;
					regWrite <= 1;
					useEA <= 1;
					branchControl <= 0;		
				end
		endcase
	end
endmodule
module Control(
	instructionInput,
	regWrite,
	memWrite,
	useEA,
	ALUOP,
	memRead,
	linkSrc,
	memToReg,
	branchControl);

	
	
	input [3:0]			instructionInput;
	
	output reg			regWrite;
	output reg			memWrite;
	output reg			useEA;
	output reg [3:0]	ALUOP;
	output reg			memRead;
	output reg			linkSrc;
	output reg			memToReg;
	output reg [1:0]	branchControl;
	
	always@(*) begin
	
		ALUOP <= instructionInput;
	
		case(instructionInput)
			
			'b0000:
				begin
					linkSrc <= 0;
					memWrite <= 0;
					memRead <= 0;
					memToReg <= 0;
					regWrite <= 0;
					useEA <= 0;
					branchControl <= 0;
				end
				
			4'b0001:
				begin
					linkSrc <= 0;
					memWrite <= 0;
					memRead <= 0;
					memToReg <= 0;
					regWrite <= 1;
					useEA <= 0;
					branchControl <= 0;
				end	
			4'b0010:
				begin
					linkSrc <= 0;
					memWrite <= 0;
					memRead <= 0;
					memToReg <= 0;
					regWrite <= 1;
					useEA <= 0;
					branchControl <= 0;
				end	
				
			4'b0011:
				begin
					linkSrc <= 0;
					memWrite <= 0;
					memRead <= 0;
					memToReg <= 0;
					regWrite <= 1;
					useEA <= 0;
					branchControl <= 0;
				end
				
			4'b0100:
				begin
					linkSrc <= 0;
					memWrite <= 0;
					memRead <= 0;
					memToReg <= 0;
					regWrite <= 1;
					useEA <= 0;
					branchControl <= 0;
				end
				
			4'b0101:
				begin
					linkSrc <= 0;
					memWrite <= 0;
					memRead <= 0;
					memToReg <= 0;
					regWrite <= 1;
					useEA <= 0;
					branchControl <= 0;
				end
				
			4'b0110:
				begin
					linkSrc <= 0;
					memWrite <= 0;
					memRead <= 0;
					memToReg <= 0;
					regWrite <= 0;
					useEA <= 0;
					branchControl <= 0;
				end
				
			4'b0111:
				begin
					linkSrc <= 0;
					memWrite <= 0;
					memRead <= 0;
					memToReg <= 0;
					regWrite <= 1;
					useEA <= 0;
					branchControl <= 0;
				end	
				
			4'b1000:
				begin
					linkSrc <= 0;
					memWrite <= 0;
					memRead <= 0;
					memToReg <= 0;
					regWrite <= 1;
					useEA <= 0;
					branchControl <= 0;	
				end
				
			4'b1001:
				begin
					linkSrc <= 1;
					memWrite <= 0;
					memRead <= 0;
					memToReg <= 0;
					regWrite <= 0;
					useEA <= 1;
					branchControl <= 0;
				end	
				
			4'b1010:
				begin
					linkSrc <= 1;
					memWrite <= 0;
					memRead <= 0;
					memToReg <= 0;
					regWrite <= 0;
					useEA <= 1;
					branchControl <= 1;
				end
			4'b1011:
				begin
					linkSrc <= 1;
					memWrite <= 0;
					memRead <= 0;
					memToReg <= 0;
					regWrite <= 0;
					useEA <= 1;
					branchControl <= 2;	
				end
				
			4'b1100:
				begin
					linkSrc <= 1;
					memWrite <= 0;
					memRead <= 0;
					memToReg <= 0;
					regWrite <= 0;
					useEA <= 1;
					branchControl <= 3;
				end
				
			4'b1101:
				begin
					linkSrc <= 0;
					memWrite <= 0;
					memRead <= 1;
					memToReg <= 1;
					regWrite <= 1;
					useEA <= 1;
					branchControl <= 0;
				end
				
			4'b1110:
				begin
					linkSrc <= 0;
					memWrite <= 1;
					memRead <= 0;
					memToReg <= 0;
					regWrite <= 0;
					useEA <= 1;
					branchControl <= 0;
				end
			
			4'b1111:
				begin
					linkSrc <= 0;
					memWrite <= 0;
					memRead <= 0;
					memToReg <= 0;
					regWrite <= 1;
					useEA <= 1;
					branchControl <= 0;		
				end
		endcase
	end
endmodule