data/full_repos/permissive/481044442/BDCDrv/led_ctl_by_uart.v
1: b"%Error: data/full_repos/permissive/481044442/BDCDrv/led_ctl_by_uart.v:13: Cannot find file containing module: 'power_on_reset'\npower_on_reset u0 (.clk(clk), \n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/481044442/BDCDrv,data/full_repos/permissive/481044442/power_on_reset\n             data/full_repos/permissive/481044442/BDCDrv,data/full_repos/permissive/481044442/power_on_reset.v\n             data/full_repos/permissive/481044442/BDCDrv,data/full_repos/permissive/481044442/power_on_reset.sv\n             power_on_reset\n             power_on_reset.v\n             power_on_reset.sv\n             obj_dir/power_on_reset\n             obj_dir/power_on_reset.v\n             obj_dir/power_on_reset.sv\n%Error: data/full_repos/permissive/481044442/BDCDrv/led_ctl_by_uart.v:17: Cannot find file containing module: 'clk_prescale'\nclk_prescale inst_clk_prescale(.clk(clk), \n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/481044442/BDCDrv/led_ctl_by_uart.v:27: Cannot find file containing module: 'rx_module'\nrx_module u1(.clk(clk_main), \n^~~~~~~~~\n%Error: data/full_repos/permissive/481044442/BDCDrv/led_ctl_by_uart.v:51: Cannot find file containing module: 'uart_parser'\nuart_parser inst_uart_parser(.clk(clk), \n^~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module led_ctl_by_uart(clk,RXD,led1,led2,bps_clkx4,motor_pwm,parse_done_sig);
input clk;
input RXD;
output led1;
output led2;
output wire bps_clkx4;   

output [3:0] motor_pwm;
output parse_done_sig;
   

wire reset;
power_on_reset u0 (.clk(clk),
					.reset(reset));

wire clk_main;
clk_prescale inst_clk_prescale(.clk(clk),
								.reset(reset),
								.clk_main(clk_main));



reg Rx_En_Sig;   
wire [7:0] RxData;
wire Rx_Done_Sig;

rx_module u1(.clk(clk_main),
			.reset(reset),
			.RXD(RXD),
			.Rx_En_Sig(Rx_En_Sig),
			.RxData(RxData),
			.Rx_Done_Sig(Rx_Done_Sig));


always@(posedge clk or posedge reset)
begin
	if(reset) begin
				Rx_En_Sig<=1'd0;
	          end
	else begin
			if(Rx_Done_Sig) 
					Rx_En_Sig<=1'd0;
			else
					Rx_En_Sig<=1'd1;
		 end
end

reg parse_start_en_sig;
wire parse_done_sig;
wire [1:0] led;
uart_parser inst_uart_parser(.clk(clk),
							.reset(reset),
							.Start_En_Sig(parse_start_en_sig),
							.Rx_Done_Sig(Rx_Done_Sig),
							.Data_In(RxData),
							.led(led),
							.motor_pwm(motor_pwm),
							.Done_Sig(parse_done_sig));
assign led1=led[0];
assign led2=led[1];

always@(posedge clk or posedge reset)
begin
	if(reset) begin
				parse_start_en_sig<=1'd0;
	          end
	else begin
			if(parse_done_sig) 
					parse_start_en_sig<=1'd0;
			else
					parse_start_en_sig<=1'd1;
		 end
end

endmodule
module led_ctl_by_uart(clk,RXD,led1,led2,bps_clkx4,motor_pwm,parse_done_sig);

input clk;
input RXD;
output led1;
output led2;
output wire bps_clkx4;   

output [3:0] motor_pwm;
output parse_done_sig;
   

wire reset;
power_on_reset u0 (.clk(clk),
					.reset(reset));

wire clk_main;
clk_prescale inst_clk_prescale(.clk(clk),
								.reset(reset),
								.clk_main(clk_main));



reg Rx_En_Sig;   
wire [7:0] RxData;
wire Rx_Done_Sig;

rx_module u1(.clk(clk_main),
			.reset(reset),
			.RXD(RXD),
			.Rx_En_Sig(Rx_En_Sig),
			.RxData(RxData),
			.Rx_Done_Sig(Rx_Done_Sig));


always@(posedge clk or posedge reset)
begin
	if(reset) begin
				Rx_En_Sig<=1'd0;
	          end
	else begin
			if(Rx_Done_Sig) 
					Rx_En_Sig<=1'd0;
			else
					Rx_En_Sig<=1'd1;
		 end
end

reg parse_start_en_sig;
wire parse_done_sig;
wire [1:0] led;
uart_parser inst_uart_parser(.clk(clk),
							.reset(reset),
							.Start_En_Sig(parse_start_en_sig),
							.Rx_Done_Sig(Rx_Done_Sig),
							.Data_In(RxData),
							.led(led),
							.motor_pwm(motor_pwm),
							.Done_Sig(parse_done_sig));
assign led1=led[0];
assign led2=led[1];

always@(posedge clk or posedge reset)
begin
	if(reset) begin
				parse_start_en_sig<=1'd0;
	          end
	else begin
			if(parse_done_sig) 
					parse_start_en_sig<=1'd0;
			else
					parse_start_en_sig<=1'd1;
		 end
end

endmodule