data/full_repos/permissive/439037294/ip/sun_tr_sky130nm/design/SUN_TR_SKY130NM.v
1: b"%Error: data/full_repos/permissive/439037294/ip/sun_tr_sky130nm/design/SUN_TR_SKY130NM.v:723: syntax error, unexpected '<', expecting ')' or ','\nmodule SUNTR_RG12TRIX1_CV(D<11>,D<10>,D<9>,D<8>,D<7>,D<6>,D<5>,D<4>,D<3>,D<2>,D<1>,D<0>,CK,C,CN,Y<11>,Y<10>,Y<9>,Y<8>,Y<7>,Y<6>,Y<5>,Y<4>,Y<3>,Y<2>,Y<1>,Y<0>,AVDD,AVSS);\n                           ^\n%Error: data/full_repos/permissive/439037294/ip/sun_tr_sky130nm/design/SUN_TR_SKY130NM.v:725: syntax error, unexpected input\ninput logic AVDD;\n^~~~~\n%Error: data/full_repos/permissive/439037294/ip/sun_tr_sky130nm/design/SUN_TR_SKY130NM.v:726: syntax error, unexpected input\ninput logic CK;\n^~~~~\n%Error: data/full_repos/permissive/439037294/ip/sun_tr_sky130nm/design/SUN_TR_SKY130NM.v:727: syntax error, unexpected input\ninput logic C;\n^~~~~\n%Error: data/full_repos/permissive/439037294/ip/sun_tr_sky130nm/design/SUN_TR_SKY130NM.v:728: syntax error, unexpected input\ninput logic CN;\n^~~~~\n%Error: data/full_repos/permissive/439037294/ip/sun_tr_sky130nm/design/SUN_TR_SKY130NM.v:729: syntax error, unexpected input\ninput logic Y<11>;\n^~~~~\n%Error: Exiting due to 6 error(s)\n"
module SUNTR_SCX1_CV(A,Y,AVDD,AVSS);
input logic A;
input logic Y;
input logic AVDD;
input logic AVSS;
SUNTR_NCHDL XA2 (N1,A,AVSS,AVSS);
SUNTR_NCHDL XA3 (SCO,A,N1,AVSS);
SUNTR_NCHDL XA4a (AVDD,SCO,N1,AVSS);
SUNTR_NCHDL XA4b (AVDD,SCO,N1,AVSS);
SUNTR_NCHDL XA5 (Y,SCO,AVSS,AVSS);
SUNTR_PCHDL XB0 (N2,A,AVDD,AVDD);
SUNTR_PCHDL XB1 (SCO,A,N2,AVDD);
SUNTR_PCHDL XB3a (N2,SCO,AVSS,AVDD);
SUNTR_PCHDL XB3b (N2,SCO,AVSS,AVDD);
SUNTR_PCHDL XB4 (Y,SCO,AVDD,AVDD);
endmodule
module SUNTR_SCX1_CV(A,Y,AVDD,AVSS);

input logic A;
input logic Y;
input logic AVDD;
input logic AVSS;
SUNTR_NCHDL XA2 (N1,A,AVSS,AVSS);
SUNTR_NCHDL XA3 (SCO,A,N1,AVSS);
SUNTR_NCHDL XA4a (AVDD,SCO,N1,AVSS);
SUNTR_NCHDL XA4b (AVDD,SCO,N1,AVSS);
SUNTR_NCHDL XA5 (Y,SCO,AVSS,AVSS);
SUNTR_PCHDL XB0 (N2,A,AVDD,AVDD);
SUNTR_PCHDL XB1 (SCO,A,N2,AVDD);
SUNTR_PCHDL XB3a (N2,SCO,AVSS,AVDD);
SUNTR_PCHDL XB3b (N2,SCO,AVSS,AVDD);
SUNTR_PCHDL XB4 (Y,SCO,AVDD,AVDD);
endmodule