data/full_repos/permissive/423547971/FPGA Projects/Seven Segment Clock Basys 3(segs on basys3)/seconds.v
1: b'%Error: Cannot find file containing module: Projects/Seven\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/Seven\n             data/full_repos/permissive/423547971/FPGA/Projects/Seven.v\n             data/full_repos/permissive/423547971/FPGA/Projects/Seven.sv\n             Projects/Seven\n             Projects/Seven.v\n             Projects/Seven.sv\n             obj_dir/Projects/Seven\n             obj_dir/Projects/Seven.v\n             obj_dir/Projects/Seven.sv\n%Error: Cannot find file containing module: Segment\n%Error: Cannot find file containing module: Clock\n%Error: Cannot find file containing module: Basys\n%Error: Cannot find file containing module: 3(segs\n%Error: Cannot find file containing module: on\n%Error: Cannot find file containing module: basys3),data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: basys3)/seconds.v\n%Error: Exiting due to 9 error(s)\n'
module seconds(
    input clk_1Hz,
    input reset,
    output inc_minutes
    );
    
    reg [5:0] sec_ctr = 0;
    
    always @(posedge clk_1Hz or posedge reset) begin
        if(reset)
            sec_ctr <= 0;
        else
            if(sec_ctr == 59) 
                sec_ctr <= 0;
            else
                sec_ctr <= sec_ctr + 1;
    end
    
    assign inc_minutes = (sec_ctr == 59) ? 1 : 0;
    
endmodule
module seconds(
    input clk_1Hz,
    input reset,
    output inc_minutes
    );

    
    reg [5:0] sec_ctr = 0;
    
    always @(posedge clk_1Hz or posedge reset) begin
        if(reset)
            sec_ctr <= 0;
        else
            if(sec_ctr == 59) 
                sec_ctr <= 0;
            else
                sec_ctr <= sec_ctr + 1;
    end
    
    assign inc_minutes = (sec_ctr == 59) ? 1 : 0;
    
endmodule