data/full_repos/permissive/479308240/demux.v
data/verilator_xmls/fd84bd66-78c0-4ea3-a594-1c3cc232eba8.xml
module demux(output reg [7:0] A,
                 output reg [7:0] B,
                 output reg [7:0] outbuf,
                 input wire [2:0] sel,
                 input wire clk,
                 input wire [7:0] busfin,
                 input wire busin
                 );


always@(posedge clk)
begin 
    if(busin) 
        begin
        case(sel)
                3'h1: 
                A=busfin;
                3'h2: 
                B=busfin;
                3'h4: 
                outbuf=busfin;
           endcase
        end
end

endmodule
module demux(output reg [7:0] A,
                 output reg [7:0] B,
                 output reg [7:0] outbuf,
                 input wire [2:0] sel,
                 input wire clk,
                 input wire [7:0] busfin,
                 input wire busin
                 );



always@(posedge clk)
begin 
    if(busin) 
        begin
        case(sel)
                3'h1: 
                A=busfin;
                3'h2: 
                B=busfin;
                3'h4: 
                outbuf=busfin;
           endcase
        end
end

endmodule