data/full_repos/permissive/464047548/bram_sdp.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/464047548/bram_sdp.v:35: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'data_out'\n                                                                      : ... In instance bram_sdp\n        data_out <= memory[addr_read];\n        ^~~~~~~~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module bram_sdp #(
    parameter WIDTH=8,
    parameter DEPTH=256,
    localparam ADDRW=$clog2(DEPTH)
    ) (
    input wire clk_write,
    input wire clk_read,
    input wire we,
    input wire [ADDRW-1:0] addr_write,
    input wire [ADDRW-1:0] addr_read,
    input wire [WIDTH-1:0] data_in,
    output     [WIDTH-1:0] data_out
    );


    reg [WIDTH-1:0] memory [DEPTH];



    always @(posedge clk_write) begin
        if (we) begin
            memory[addr_write] <= data_in;
        end
    end


    always @(posedge clk_read) begin
        data_out <= memory[addr_read];
    end
endmodule
module bram_sdp #(
    parameter WIDTH=8,
    parameter DEPTH=256,
    localparam ADDRW=$clog2(DEPTH)
    ) (
    input wire clk_write,
    input wire clk_read,
    input wire we,
    input wire [ADDRW-1:0] addr_write,
    input wire [ADDRW-1:0] addr_read,
    input wire [WIDTH-1:0] data_in,
    output     [WIDTH-1:0] data_out
    );



    reg [WIDTH-1:0] memory [DEPTH];



    always @(posedge clk_write) begin
        if (we) begin
            memory[addr_write] <= data_in;
        end
    end


    always @(posedge clk_read) begin
        data_out <= memory[addr_read];
    end
endmodule