data/full_repos/permissive/451048101/src/fpga/zynq7020/buffer_manage_bigFIFO.v
1: b"%Error: data/full_repos/permissive/451048101/src/fpga/zynq7020/buffer_manage_bigFIFO.v:247: Cannot find file containing module: 'blk_134b_4096'\nblk_134b_4096 pkt_ram (\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/451048101/src/fpga/zynq7020,data/full_repos/permissive/451048101/blk_134b_4096\n             data/full_repos/permissive/451048101/src/fpga/zynq7020,data/full_repos/permissive/451048101/blk_134b_4096.v\n             data/full_repos/permissive/451048101/src/fpga/zynq7020,data/full_repos/permissive/451048101/blk_134b_4096.sv\n             blk_134b_4096\n             blk_134b_4096.v\n             blk_134b_4096.sv\n             obj_dir/blk_134b_4096\n             obj_dir/blk_134b_4096.v\n             obj_dir/blk_134b_4096.sv\n%Error: Exiting due to 1 error(s)\n"
module buffer_manage_bigFIFO(
  input                 rst_n,
  input                 clk,
  input         [535:0] pktData_in,
  input         [3:0]   pktData_in_valid,
  output  wire  [63:0]  distr_bufferID,
  input         [3:0]   req_bufferID_en,
  input         [63:0]  req_bufferID,
  output  reg   [3:0]   ready_pkt,
  input         [3:0]   rden_pkt,
  output  wire  [535:0] pktData_out
  


);


wire  [133:0] pktData_in_w[3:0];
assign  {pktData_in_w[3],pktData_in_w[2],pktData_in_w[1],pktData_in_w[0]} = pktData_in;

wire  [15:0]  req_bufferID_w[3:0];
assign  {req_bufferID_w[3],req_bufferID_w[2],req_bufferID_w[1],
              req_bufferID_w[0]} = req_bufferID;


reg   [15:0]  distr_bufferID_r[3:0];
assign  distr_bufferID = {distr_bufferID_r[3],distr_bufferID_r[2],
              distr_bufferID_r[1],distr_bufferID_r[0]};

(* mark_debug = "true"*)reg   [133:0] pktData_out_r[3:0];
assign  pktData_out = {pktData_out_r[3],pktData_out_r[2],
              pktData_out_r[1],pktData_out_r[0]};


reg           wren_wrPkt;
reg   [133:0] din_wrPkt;
wire  [133:0] dout_rdPkt;
reg   [`RAM_DEPTH-1:0]  addr_rdPkt,addr_wrPkt;




integer i;
always @(posedge clk or negedge rst_n) begin
  if(!rst_n) begin
    for(i=0; i<4; i=i+1)
      distr_bufferID_r[i]                   <= 16'b0;
    distr_bufferID_r[0][(`RAM_DEPTH-1)-:2]  <= 2'd0;
    distr_bufferID_r[1][(`RAM_DEPTH-1)-:2]  <= 2'd1;
    distr_bufferID_r[2][(`RAM_DEPTH-1)-:2]  <= 2'd2;
    distr_bufferID_r[3][(`RAM_DEPTH-1)-:2]  <= 2'd3;

  end
  else begin

    for(i=0; i<4; i=i+1) begin
      if(pktData_in_valid[i] == 1'b1) begin
        distr_bufferID_r[i][`RAM_DEPTH-3:0] <= distr_bufferID_r[i][`RAM_DEPTH-3:0] + 
          {{(`RAM_DEPTH-3){1'b0}},1'b1};
      end
    end
  end
end







reg   [133:0] temp_pktIn[3:0];
reg   [3:0]   pktIn_ready[1:0];
wire  [3:0]   tag_pktIn_ready;
assign        tag_pktIn_ready = pktIn_ready[1]^pktIn_ready[0];
(* mark_debug = "true"*)reg   [`RAM_DEPTH-1:0]  temp_addrWr[3:0];
always @(posedge clk or negedge rst_n) begin
  if(!rst_n) begin
    addr_wrPkt                          <= {`RAM_DEPTH{1'b0}};
    wren_wrPkt                          <= 1'b0;
    din_wrPkt                           <= 134'b0;
    for(i=0; i<4; i=i+1) begin
      temp_addrWr[i]                    <= {`RAM_DEPTH{1'b0}};
      temp_pktIn[i]                     <= 134'b0;
    end
    pktIn_ready[0]                      <= 4'b0;
    pktIn_ready[1]                      <= 4'b0;
  end
  else begin
    for(i=0; i<4; i=i+1) begin

      if(pktData_in_valid[i] == 1'b1) begin
        temp_pktIn[i]                   <= pktData_in_w[i];
        pktIn_ready[0][i]               <= ~pktIn_ready[0][i];

        temp_addrWr[i]                  <= distr_bufferID_r[i][`RAM_DEPTH-1:0];
      end
    end

    if(tag_pktIn_ready != 4'h0) begin
      wren_wrPkt                        <= 1'b1;
      (* parallel_case, full_case *)
      casez(tag_pktIn_ready)
        4'b1???: begin 
          din_wrPkt                     <= temp_pktIn[3];
          addr_wrPkt                    <= temp_addrWr[3];
          pktIn_ready[1][3]             <= ~pktIn_ready[1][3];
        end
        4'b01??: begin 
          din_wrPkt                     <= temp_pktIn[2];
          addr_wrPkt                    <= temp_addrWr[2];
          pktIn_ready[1][2]             <= ~pktIn_ready[1][2];
        end
        4'b001?: begin 
          din_wrPkt                     <= temp_pktIn[1];
          addr_wrPkt                    <= temp_addrWr[1];
          pktIn_ready[1][1]             <= ~pktIn_ready[1][1];
        end
        4'b0001: begin 
          din_wrPkt                     <= temp_pktIn[0];
          addr_wrPkt                    <= temp_addrWr[0];
          pktIn_ready[1][0]             <= ~pktIn_ready[1][0];
        end
      endcase
    end
    else  wren_wrPkt                    <= 1'b0;
  end
end






(* mark_debug = "true"*)reg   [`RAM_DEPTH-1:0]  temp_addrRd[3:0];
reg   [3:0] pktOut_ready[1:0];
wire  [3:0] tag_pktOut_ready;
assign  tag_pktOut_ready = pktOut_ready[1]^pktOut_ready[0];

reg   [3:0] tag_alreadyRd[2:0];
    
always @(posedge clk or negedge rst_n) begin
  if(!rst_n) begin
    addr_rdPkt                          <= {`RAM_DEPTH{1'b0}};
    for(i=0; i<4; i=i+1) begin
      pktData_out_r[i]                  <= 134'b0;
      ready_pkt[i]                      <= 1'b0;
      temp_addrRd[i]                    <= {`RAM_DEPTH{1'b0}};
    end
    pktOut_ready[0]                     <= 4'b0;
    pktOut_ready[1]                     <= 4'b0;
    tag_alreadyRd[0]                    <= 4'b0;
    tag_alreadyRd[1]                    <= 4'b0;
    tag_alreadyRd[2]                    <= 4'b0;
  end
  else begin

    for(i=0; i<4; i=i+1) begin



      if(req_bufferID_en[i] == 1'b1) begin
        temp_addrRd[i]                  <= req_bufferID_w[i][`RAM_DEPTH-1:0];
        pktOut_ready[0][i]              <= ~pktOut_ready[0][i];
      end
      else if(rden_pkt[i] == 1'b1) begin
        temp_addrRd[i][`RAM_DEPTH-3:0]  <= temp_addrRd[i][`RAM_DEPTH-3:0] + 
                                            {{(`RAM_DEPTH-3){1'b0}},1'b1};
        pktOut_ready[0][i]              <= ~pktOut_ready[0][i];
      end
    end
    



    tag_alreadyRd[0]                  <= 4'b0;
    if(tag_pktOut_ready != 4'h0) begin
      (* parallel_case, full_case *)
      casez(tag_pktOut_ready)
        4'b1???: begin
          addr_rdPkt                  <= temp_addrRd[3];
          pktOut_ready[1][3]          <= ~pktOut_ready[1][3];
          tag_alreadyRd[0]            <= 4'd8;
        end
        4'b01??: begin
          addr_rdPkt                  <= temp_addrRd[2];
          pktOut_ready[1][2]          <= ~pktOut_ready[1][2];
          tag_alreadyRd[0]            <= 4'd4;
        end
        4'b001?: begin
          addr_rdPkt                  <= temp_addrRd[1];
          pktOut_ready[1][1]          <= ~pktOut_ready[1][1];
          tag_alreadyRd[0]            <= 4'd2;
        end
        4'b0001: begin
          addr_rdPkt                  <= temp_addrRd[0];
          pktOut_ready[1][0]          <= ~pktOut_ready[1][0];
          tag_alreadyRd[0]            <= 4'd1;
        end
      endcase
    end
    

    for(i=0; i<4; i=i+1) begin
      if(tag_alreadyRd[2][i] == 1'b1) begin
        pktData_out_r[i]              <= dout_rdPkt;

        ready_pkt[i]                  <= 1'b1;
      end
      else begin
        pktData_out_r[i]              <= pktData_out_r[i];
        ready_pkt[i]                  <= 1'b0;
      end
    end
    

    {tag_alreadyRd[2],tag_alreadyRd[1]} <= {tag_alreadyRd[1],tag_alreadyRd[0]};
  end
end

blk_134b_4096 pkt_ram (
  .clka(clk),
  .wea(wren_wrPkt),
  .addra(addr_wrPkt),
  .dina(din_wrPkt),
  .douta(),
  .clkb(clk),
  .web(1'b0),
  .addrb(addr_rdPkt),
  .dinb(134'b0),
  .doutb(dout_rdPkt)
);



(* mark_debug = "true"*)reg   tag_almost_full;
(* mark_debug = "true"*)reg   tag_full;
(* mark_debug = "true"*)reg   [10:0] usedw_pktBuf;
reg temp_gmii_valid;
always @(posedge clk or negedge rst_n) begin
  if(!rst_n) begin
    tag_almost_full         <= 1'b0;
    tag_full                <= 1'b0;
    usedw_pktBuf            <= 11'b0;
  end
  else begin
    tag_full                <= 1'b0;
    if(temp_addrWr[0][9:0] == (temp_addrRd[0][9:0] - 10'd1))
      tag_full              <= 1'b1;

    tag_almost_full         <= 1'b0;
    if(temp_addrWr[0][9:0] == (temp_addrRd[0][9:0] - 10'd8))
      tag_almost_full       <= 1'b1;
    if(temp_addrWr[0][9:0] >= temp_addrRd[0][9:0])
      usedw_pktBuf          <= {1'b0,temp_addrWr[0][9:0]-temp_addrRd[0][9:0]};
    else
      usedw_pktBuf          <= {1'b1,temp_addrWr[0][9:0]}-{1'b0,temp_addrRd[0][9:0]};
  end
end


endmodule
module buffer_manage_bigFIFO(
  input                 rst_n,
  input                 clk,
  input         [535:0] pktData_in,
  input         [3:0]   pktData_in_valid,
  output  wire  [63:0]  distr_bufferID,
  input         [3:0]   req_bufferID_en,
  input         [63:0]  req_bufferID,
  output  reg   [3:0]   ready_pkt,
  input         [3:0]   rden_pkt,
  output  wire  [535:0] pktData_out
  


);



wire  [133:0] pktData_in_w[3:0];
assign  {pktData_in_w[3],pktData_in_w[2],pktData_in_w[1],pktData_in_w[0]} = pktData_in;

wire  [15:0]  req_bufferID_w[3:0];
assign  {req_bufferID_w[3],req_bufferID_w[2],req_bufferID_w[1],
              req_bufferID_w[0]} = req_bufferID;


reg   [15:0]  distr_bufferID_r[3:0];
assign  distr_bufferID = {distr_bufferID_r[3],distr_bufferID_r[2],
              distr_bufferID_r[1],distr_bufferID_r[0]};

(* mark_debug = "true"*)reg   [133:0] pktData_out_r[3:0];
assign  pktData_out = {pktData_out_r[3],pktData_out_r[2],
              pktData_out_r[1],pktData_out_r[0]};


reg           wren_wrPkt;
reg   [133:0] din_wrPkt;
wire  [133:0] dout_rdPkt;
reg   [`RAM_DEPTH-1:0]  addr_rdPkt,addr_wrPkt;




integer i;
always @(posedge clk or negedge rst_n) begin
  if(!rst_n) begin
    for(i=0; i<4; i=i+1)
      distr_bufferID_r[i]                   <= 16'b0;
    distr_bufferID_r[0][(`RAM_DEPTH-1)-:2]  <= 2'd0;
    distr_bufferID_r[1][(`RAM_DEPTH-1)-:2]  <= 2'd1;
    distr_bufferID_r[2][(`RAM_DEPTH-1)-:2]  <= 2'd2;
    distr_bufferID_r[3][(`RAM_DEPTH-1)-:2]  <= 2'd3;

  end
  else begin

    for(i=0; i<4; i=i+1) begin
      if(pktData_in_valid[i] == 1'b1) begin
        distr_bufferID_r[i][`RAM_DEPTH-3:0] <= distr_bufferID_r[i][`RAM_DEPTH-3:0] + 
          {{(`RAM_DEPTH-3){1'b0}},1'b1};
      end
    end
  end
end







reg   [133:0] temp_pktIn[3:0];
reg   [3:0]   pktIn_ready[1:0];
wire  [3:0]   tag_pktIn_ready;
assign        tag_pktIn_ready = pktIn_ready[1]^pktIn_ready[0];
(* mark_debug = "true"*)reg   [`RAM_DEPTH-1:0]  temp_addrWr[3:0];
always @(posedge clk or negedge rst_n) begin
  if(!rst_n) begin
    addr_wrPkt                          <= {`RAM_DEPTH{1'b0}};
    wren_wrPkt                          <= 1'b0;
    din_wrPkt                           <= 134'b0;
    for(i=0; i<4; i=i+1) begin
      temp_addrWr[i]                    <= {`RAM_DEPTH{1'b0}};
      temp_pktIn[i]                     <= 134'b0;
    end
    pktIn_ready[0]                      <= 4'b0;
    pktIn_ready[1]                      <= 4'b0;
  end
  else begin
    for(i=0; i<4; i=i+1) begin

      if(pktData_in_valid[i] == 1'b1) begin
        temp_pktIn[i]                   <= pktData_in_w[i];
        pktIn_ready[0][i]               <= ~pktIn_ready[0][i];

        temp_addrWr[i]                  <= distr_bufferID_r[i][`RAM_DEPTH-1:0];
      end
    end

    if(tag_pktIn_ready != 4'h0) begin
      wren_wrPkt                        <= 1'b1;
      (* parallel_case, full_case *)
      casez(tag_pktIn_ready)
        4'b1???: begin 
          din_wrPkt                     <= temp_pktIn[3];
          addr_wrPkt                    <= temp_addrWr[3];
          pktIn_ready[1][3]             <= ~pktIn_ready[1][3];
        end
        4'b01??: begin 
          din_wrPkt                     <= temp_pktIn[2];
          addr_wrPkt                    <= temp_addrWr[2];
          pktIn_ready[1][2]             <= ~pktIn_ready[1][2];
        end
        4'b001?: begin 
          din_wrPkt                     <= temp_pktIn[1];
          addr_wrPkt                    <= temp_addrWr[1];
          pktIn_ready[1][1]             <= ~pktIn_ready[1][1];
        end
        4'b0001: begin 
          din_wrPkt                     <= temp_pktIn[0];
          addr_wrPkt                    <= temp_addrWr[0];
          pktIn_ready[1][0]             <= ~pktIn_ready[1][0];
        end
      endcase
    end
    else  wren_wrPkt                    <= 1'b0;
  end
end






(* mark_debug = "true"*)reg   [`RAM_DEPTH-1:0]  temp_addrRd[3:0];
reg   [3:0] pktOut_ready[1:0];
wire  [3:0] tag_pktOut_ready;
assign  tag_pktOut_ready = pktOut_ready[1]^pktOut_ready[0];

reg   [3:0] tag_alreadyRd[2:0];
    
always @(posedge clk or negedge rst_n) begin
  if(!rst_n) begin
    addr_rdPkt                          <= {`RAM_DEPTH{1'b0}};
    for(i=0; i<4; i=i+1) begin
      pktData_out_r[i]                  <= 134'b0;
      ready_pkt[i]                      <= 1'b0;
      temp_addrRd[i]                    <= {`RAM_DEPTH{1'b0}};
    end
    pktOut_ready[0]                     <= 4'b0;
    pktOut_ready[1]                     <= 4'b0;
    tag_alreadyRd[0]                    <= 4'b0;
    tag_alreadyRd[1]                    <= 4'b0;
    tag_alreadyRd[2]                    <= 4'b0;
  end
  else begin

    for(i=0; i<4; i=i+1) begin



      if(req_bufferID_en[i] == 1'b1) begin
        temp_addrRd[i]                  <= req_bufferID_w[i][`RAM_DEPTH-1:0];
        pktOut_ready[0][i]              <= ~pktOut_ready[0][i];
      end
      else if(rden_pkt[i] == 1'b1) begin
        temp_addrRd[i][`RAM_DEPTH-3:0]  <= temp_addrRd[i][`RAM_DEPTH-3:0] + 
                                            {{(`RAM_DEPTH-3){1'b0}},1'b1};
        pktOut_ready[0][i]              <= ~pktOut_ready[0][i];
      end
    end
    



    tag_alreadyRd[0]                  <= 4'b0;
    if(tag_pktOut_ready != 4'h0) begin
      (* parallel_case, full_case *)
      casez(tag_pktOut_ready)
        4'b1???: begin
          addr_rdPkt                  <= temp_addrRd[3];
          pktOut_ready[1][3]          <= ~pktOut_ready[1][3];
          tag_alreadyRd[0]            <= 4'd8;
        end
        4'b01??: begin
          addr_rdPkt                  <= temp_addrRd[2];
          pktOut_ready[1][2]          <= ~pktOut_ready[1][2];
          tag_alreadyRd[0]            <= 4'd4;
        end
        4'b001?: begin
          addr_rdPkt                  <= temp_addrRd[1];
          pktOut_ready[1][1]          <= ~pktOut_ready[1][1];
          tag_alreadyRd[0]            <= 4'd2;
        end
        4'b0001: begin
          addr_rdPkt                  <= temp_addrRd[0];
          pktOut_ready[1][0]          <= ~pktOut_ready[1][0];
          tag_alreadyRd[0]            <= 4'd1;
        end
      endcase
    end
    

    for(i=0; i<4; i=i+1) begin
      if(tag_alreadyRd[2][i] == 1'b1) begin
        pktData_out_r[i]              <= dout_rdPkt;

        ready_pkt[i]                  <= 1'b1;
      end
      else begin
        pktData_out_r[i]              <= pktData_out_r[i];
        ready_pkt[i]                  <= 1'b0;
      end
    end
    

    {tag_alreadyRd[2],tag_alreadyRd[1]} <= {tag_alreadyRd[1],tag_alreadyRd[0]};
  end
end

blk_134b_4096 pkt_ram (
  .clka(clk),
  .wea(wren_wrPkt),
  .addra(addr_wrPkt),
  .dina(din_wrPkt),
  .douta(),
  .clkb(clk),
  .web(1'b0),
  .addrb(addr_rdPkt),
  .dinb(134'b0),
  .doutb(dout_rdPkt)
);



(* mark_debug = "true"*)reg   tag_almost_full;
(* mark_debug = "true"*)reg   tag_full;
(* mark_debug = "true"*)reg   [10:0] usedw_pktBuf;
reg temp_gmii_valid;
always @(posedge clk or negedge rst_n) begin
  if(!rst_n) begin
    tag_almost_full         <= 1'b0;
    tag_full                <= 1'b0;
    usedw_pktBuf            <= 11'b0;
  end
  else begin
    tag_full                <= 1'b0;
    if(temp_addrWr[0][9:0] == (temp_addrRd[0][9:0] - 10'd1))
      tag_full              <= 1'b1;

    tag_almost_full         <= 1'b0;
    if(temp_addrWr[0][9:0] == (temp_addrRd[0][9:0] - 10'd8))
      tag_almost_full       <= 1'b1;
    if(temp_addrWr[0][9:0] >= temp_addrRd[0][9:0])
      usedw_pktBuf          <= {1'b0,temp_addrWr[0][9:0]-temp_addrRd[0][9:0]};
    else
      usedw_pktBuf          <= {1'b1,temp_addrWr[0][9:0]}-{1'b0,temp_addrRd[0][9:0]};
  end
end


endmodule