data/full_repos/permissive/496508301/Lesson6/sigma_16p.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson6/sigma_16p.v:75: Unsupported: Ignoring delay on this delayed statement.\n    #17     res <= 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson6/sigma_16p.v:76: Unsupported: Ignoring delay on this delayed statement.\n    #25000  $stop;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson6/sigma_16p.v:78: Unsupported: Ignoring delay on this delayed statement.\nalways #5   clk <= ~clk;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson6/sigma_16p.v:79: Unsupported: Ignoring delay on this delayed statement.\nalways #100 syn_in <= ~syn_in;   \n       ^\n%Error: data/full_repos/permissive/496508301/Lesson6/sigma_16p.v:82: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("sigma_16p_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/496508301/Lesson6/sigma_16p.v:83: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sigma_16p_tb;
reg             clk, res;
reg[7:0]        data_in;
reg             syn_in;
wire[11:0]      data_out;
wire            syn_out;
sigma_16p sigma_16p(
    .clk(clk),
    .res(res),
    .data_in(data_in),
    .syn_in(syn_in),
    .data_out(data_out),
    .syn_out(syn_out)
);
initial begin

    clk <= 0; res <= 0; data_in <= 8'b10000001; syn_in <= 0;
    #17     res <= 1;
    #25000  $stop;
end
always #5   clk <= ~clk;
always #100 syn_in <= ~syn_in;

initial begin
    $dumpfile("sigma_16p_tb.vcd");
    $dumpvars;
end
endmodule
module sigma_16p_tb;

reg             clk, res;
reg[7:0]        data_in;
reg             syn_in;
wire[11:0]      data_out;
wire            syn_out;
sigma_16p sigma_16p(
    .clk(clk),
    .res(res),
    .data_in(data_in),
    .syn_in(syn_in),
    .data_out(data_out),
    .syn_out(syn_out)
);
initial begin

    clk <= 0; res <= 0; data_in <= 8'b10000001; syn_in <= 0;
    #17     res <= 1;
    #25000  $stop;
end
always #5   clk <= ~clk;
always #100 syn_in <= ~syn_in;

initial begin
    $dumpfile("sigma_16p_tb.vcd");
    $dumpvars;
end
endmodule