data/full_repos/permissive/447976230/fpga/usrp2/gpif/packet_padder36.v
1: b'%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/gpif/packet_padder36.v:92: Operator COND expects 32 or 2 bits on the Conditional True, but Conditional True\'s LTE generates 1 bits.\n                                                                                         : ... In instance packet_padder36\n                state <= (data_i[15:0] > line_count)? state <= STATE_WRITE_PAD : STATE_WRITE_HDR;\n                                                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module packet_padder36
#(
    parameter RX_IDLE_FLUSH_CYCLES = 65536,
    parameter MAX_LUT_LINES32 = 4096
)
(
    input clk, input reset,
    input [35:0] data_i,
    input src_rdy_i,
    output dst_rdy_o,
    output [35:0] data_o,
    output src_rdy_o,
    input dst_rdy_i,
    input rx_dsp_active
);


    localparam STATE_READ_HDR = 0;
    localparam STATE_WRITE_HDR = 1;
    localparam STATE_FORWARD = 2;
    localparam STATE_WRITE_PAD = 3;
    reg [1:0] state;


    reg [15:0] line_count;
    wire line_count_done = line_count == 1;
    wire lut_is_empty = line_count == MAX_LUT_LINES32;
    always @(posedge clk) begin
        if (reset) begin
            line_count <= MAX_LUT_LINES32;
        end
        else if (src_rdy_o && dst_rdy_i) begin
            line_count <= (line_count_done)? MAX_LUT_LINES32 : line_count - 1;
        end
    end


    reg [17:0] non_rx_cycles;
    wire idle_timeout = (non_rx_cycles == RX_IDLE_FLUSH_CYCLES);
    always @(posedge clk) begin
        if(reset || state != STATE_READ_HDR) begin
            non_rx_cycles <= 0;
        end
        else if (~idle_timeout) begin
            non_rx_cycles <= non_rx_cycles + 1;
        end
    end


    wire force_flush = ~lut_is_empty && (idle_timeout || ~rx_dsp_active);


    reg [31:0] vita_hdr;
    reg has_vita_hdr;
    always @(posedge clk) begin
        if (reset) begin
            state <= STATE_READ_HDR;
        end
        else case(state)

        STATE_READ_HDR: begin
            if (src_rdy_i && dst_rdy_o && data_i[32]) begin
                vita_hdr <= data_i[31:0];
                has_vita_hdr <= 1;
                state <= (data_i[15:0] > line_count)? state <= STATE_WRITE_PAD : STATE_WRITE_HDR;
            end
            else if (force_flush) begin
                has_vita_hdr <= 0;
                state <= STATE_WRITE_PAD;
            end
        end

        STATE_WRITE_HDR: begin
            if (src_rdy_o && dst_rdy_i) begin
                state <= STATE_FORWARD;
            end
        end

        STATE_FORWARD: begin
            if (src_rdy_i && dst_rdy_o && data_i[33]) begin
                state <= STATE_READ_HDR;
            end
        end

        STATE_WRITE_PAD: begin
            if (src_rdy_o && dst_rdy_i && line_count_done) begin
                state <= (has_vita_hdr)? STATE_WRITE_HDR : STATE_READ_HDR;
            end
        end

        endcase
    end


    assign dst_rdy_o = (state == STATE_READ_HDR)? 1 : ((state == STATE_FORWARD)? dst_rdy_i : 0);
    assign src_rdy_o = (state == STATE_WRITE_HDR || state == STATE_WRITE_PAD)? 1 : ((state == STATE_FORWARD )? src_rdy_i : 0);
    assign data_o = (state == STATE_WRITE_HDR)? {4'b0001, vita_hdr} : ((state == STATE_FORWARD)? data_i : 0);

endmodule
module packet_padder36
#(
    parameter RX_IDLE_FLUSH_CYCLES = 65536,
    parameter MAX_LUT_LINES32 = 4096
)
(
    input clk, input reset,
    input [35:0] data_i,
    input src_rdy_i,
    output dst_rdy_o,
    output [35:0] data_o,
    output src_rdy_o,
    input dst_rdy_i,
    input rx_dsp_active
);



    localparam STATE_READ_HDR = 0;
    localparam STATE_WRITE_HDR = 1;
    localparam STATE_FORWARD = 2;
    localparam STATE_WRITE_PAD = 3;
    reg [1:0] state;


    reg [15:0] line_count;
    wire line_count_done = line_count == 1;
    wire lut_is_empty = line_count == MAX_LUT_LINES32;
    always @(posedge clk) begin
        if (reset) begin
            line_count <= MAX_LUT_LINES32;
        end
        else if (src_rdy_o && dst_rdy_i) begin
            line_count <= (line_count_done)? MAX_LUT_LINES32 : line_count - 1;
        end
    end


    reg [17:0] non_rx_cycles;
    wire idle_timeout = (non_rx_cycles == RX_IDLE_FLUSH_CYCLES);
    always @(posedge clk) begin
        if(reset || state != STATE_READ_HDR) begin
            non_rx_cycles <= 0;
        end
        else if (~idle_timeout) begin
            non_rx_cycles <= non_rx_cycles + 1;
        end
    end


    wire force_flush = ~lut_is_empty && (idle_timeout || ~rx_dsp_active);


    reg [31:0] vita_hdr;
    reg has_vita_hdr;
    always @(posedge clk) begin
        if (reset) begin
            state <= STATE_READ_HDR;
        end
        else case(state)

        STATE_READ_HDR: begin
            if (src_rdy_i && dst_rdy_o && data_i[32]) begin
                vita_hdr <= data_i[31:0];
                has_vita_hdr <= 1;
                state <= (data_i[15:0] > line_count)? state <= STATE_WRITE_PAD : STATE_WRITE_HDR;
            end
            else if (force_flush) begin
                has_vita_hdr <= 0;
                state <= STATE_WRITE_PAD;
            end
        end

        STATE_WRITE_HDR: begin
            if (src_rdy_o && dst_rdy_i) begin
                state <= STATE_FORWARD;
            end
        end

        STATE_FORWARD: begin
            if (src_rdy_i && dst_rdy_o && data_i[33]) begin
                state <= STATE_READ_HDR;
            end
        end

        STATE_WRITE_PAD: begin
            if (src_rdy_o && dst_rdy_i && line_count_done) begin
                state <= (has_vita_hdr)? STATE_WRITE_HDR : STATE_READ_HDR;
            end
        end

        endcase
    end


    assign dst_rdy_o = (state == STATE_READ_HDR)? 1 : ((state == STATE_FORWARD)? dst_rdy_i : 0);
    assign src_rdy_o = (state == STATE_WRITE_HDR || state == STATE_WRITE_PAD)? 1 : ((state == STATE_FORWARD )? src_rdy_i : 0);
    assign data_o = (state == STATE_WRITE_HDR)? {4'b0001, vita_hdr} : ((state == STATE_FORWARD)? data_i : 0);

endmodule