data/full_repos/permissive/459497172/verilog/rtl/lib/wb_stagging.sv
data/verilator_xmls/469a5ed3-c7ce-4118-8670-61965dcec964.xml
module wb_stagging (
         input logic		clk_i, 
         input logic            rst_n,

         input   logic	[31:0]	m_wbd_dat_i,
         input   logic  [31:0]	m_wbd_adr_i,
         input   logic  [3:0]	m_wbd_sel_i,
         input   logic  [9:0]	m_wbd_bl_i,
         input   logic  	m_wbd_bry_i,
         input   logic  	m_wbd_we_i,
         input   logic  	m_wbd_cyc_i,
         input   logic  	m_wbd_stb_i,
         input   logic  [3:0]	m_wbd_tid_i,
         output  logic	[31:0]	m_wbd_dat_o,
         output  logic		m_wbd_ack_o,
         output  logic		m_wbd_lack_o,
         output  logic		m_wbd_err_o,


         input	logic [31:0]	s_wbd_dat_i,
         input	logic 	        s_wbd_ack_i,
         input	logic 	        s_wbd_lack_i,
         input	logic 	        s_wbd_err_i,
         output	logic [31:0]	s_wbd_dat_o,
         output	logic [31:0]	s_wbd_adr_o,
         output	logic [3:0]	s_wbd_sel_o,
         output	logic [9:0]	s_wbd_bl_o,
         output	logic    	s_wbd_bry_o,
         output	logic 	        s_wbd_we_o,
         output	logic 	        s_wbd_cyc_o,
         output	logic 	        s_wbd_stb_o,
         output	logic [3:0]	s_wbd_tid_o

);

logic [31:0] m_wbd_dat_i_ff ;
logic [31:0] m_wbd_adr_i_ff ;
logic [3:0]  m_wbd_sel_i_ff ;
logic [9:0]  m_wbd_bl_i_ff ;
logic        m_wbd_bry_i_ff ;
logic        m_wbd_we_i_ff  ;
logic        m_wbd_cyc_i_ff ;
logic        m_wbd_stb_i_ff ;
logic [3:0]  m_wbd_tid_i_ff ;
logic [31:0] s_wbd_dat_i_ff ;
logic        s_wbd_ack_i_ff ;
logic        s_wbd_lack_i_ff ;
logic        s_wbd_err_i_ff ;


assign s_wbd_dat_o = m_wbd_dat_i_ff;
assign s_wbd_adr_o = m_wbd_adr_i_ff;
assign s_wbd_sel_o = m_wbd_sel_i_ff;
assign s_wbd_bl_o  = m_wbd_bl_i_ff;
assign s_wbd_bry_o = m_wbd_bry_i_ff;
assign s_wbd_we_o  = m_wbd_we_i_ff;
assign s_wbd_cyc_o = m_wbd_cyc_i_ff;
assign s_wbd_stb_o = m_wbd_stb_i_ff;
assign s_wbd_tid_o = m_wbd_tid_i_ff;

assign m_wbd_dat_o = s_wbd_dat_i_ff;
assign m_wbd_ack_o = s_wbd_ack_i_ff;
assign m_wbd_lack_o = s_wbd_lack_i_ff;
assign m_wbd_err_o = s_wbd_err_i_ff;

always @(negedge rst_n or posedge clk_i)
begin
   if(rst_n == 1'b0) begin
       m_wbd_dat_i_ff <= 'h0;
       m_wbd_adr_i_ff <= 'h0;
       m_wbd_sel_i_ff <= 'h0;
       m_wbd_bl_i_ff  <= 'h0;
       m_wbd_bry_i_ff <= 'b0;
       m_wbd_we_i_ff  <= 'h0;
       m_wbd_cyc_i_ff <= 'h0;
       m_wbd_stb_i_ff <= 'h0;
       m_wbd_tid_i_ff <= 'h0;
       s_wbd_dat_i_ff <= 'h0;
       s_wbd_ack_i_ff <= 'h0;
       s_wbd_lack_i_ff <= 'h0;
       s_wbd_err_i_ff <= 'h0;
   end else begin
       s_wbd_dat_i_ff  <= s_wbd_dat_i;
       s_wbd_ack_i_ff  <= s_wbd_ack_i;
       s_wbd_lack_i_ff <= s_wbd_lack_i;
       s_wbd_err_i_ff <= s_wbd_err_i;
       if((m_wbd_stb_i && m_wbd_bry_i && s_wbd_ack_i == 0 && m_wbd_lack_o == 0) ||
          (m_wbd_stb_i && m_wbd_bry_i && s_wbd_ack_i == 1 && s_wbd_lack_i == 0)) begin
          m_wbd_dat_i_ff <= m_wbd_dat_i;
          m_wbd_adr_i_ff <= m_wbd_adr_i;
          m_wbd_sel_i_ff <= m_wbd_sel_i;
          m_wbd_we_i_ff  <= m_wbd_we_i;
          m_wbd_cyc_i_ff <= m_wbd_cyc_i;
          m_wbd_stb_i_ff <= m_wbd_stb_i;
          m_wbd_tid_i_ff <= m_wbd_tid_i;
          m_wbd_bl_i_ff  <= m_wbd_bl_i;
          m_wbd_bry_i_ff <= 'b1;
       end else  if ((m_wbd_stb_i && !m_wbd_bry_i && s_wbd_ack_i == 1 && s_wbd_lack_i == 0)) begin
          m_wbd_bry_i_ff <= 'b0;
       end else if (s_wbd_lack_i) begin
          m_wbd_dat_i_ff <= 'h0;
          m_wbd_adr_i_ff <= 'h0;
          m_wbd_sel_i_ff <= 'h0;
          m_wbd_we_i_ff  <= 'h0;
          m_wbd_cyc_i_ff <= 'h0;
          m_wbd_stb_i_ff <= 'h0;
          m_wbd_tid_i_ff <= 'h0;
          m_wbd_bl_i_ff  <= 'h0;
          m_wbd_bry_i_ff <= 'b0;
       end
   end
end


endmodule
module wb_stagging (
         input logic		clk_i, 
         input logic            rst_n,

         input   logic	[31:0]	m_wbd_dat_i,
         input   logic  [31:0]	m_wbd_adr_i,
         input   logic  [3:0]	m_wbd_sel_i,
         input   logic  [9:0]	m_wbd_bl_i,
         input   logic  	m_wbd_bry_i,
         input   logic  	m_wbd_we_i,
         input   logic  	m_wbd_cyc_i,
         input   logic  	m_wbd_stb_i,
         input   logic  [3:0]	m_wbd_tid_i,
         output  logic	[31:0]	m_wbd_dat_o,
         output  logic		m_wbd_ack_o,
         output  logic		m_wbd_lack_o,
         output  logic		m_wbd_err_o,


         input	logic [31:0]	s_wbd_dat_i,
         input	logic 	        s_wbd_ack_i,
         input	logic 	        s_wbd_lack_i,
         input	logic 	        s_wbd_err_i,
         output	logic [31:0]	s_wbd_dat_o,
         output	logic [31:0]	s_wbd_adr_o,
         output	logic [3:0]	s_wbd_sel_o,
         output	logic [9:0]	s_wbd_bl_o,
         output	logic    	s_wbd_bry_o,
         output	logic 	        s_wbd_we_o,
         output	logic 	        s_wbd_cyc_o,
         output	logic 	        s_wbd_stb_o,
         output	logic [3:0]	s_wbd_tid_o

);


logic [31:0] m_wbd_dat_i_ff ;
logic [31:0] m_wbd_adr_i_ff ;
logic [3:0]  m_wbd_sel_i_ff ;
logic [9:0]  m_wbd_bl_i_ff ;
logic        m_wbd_bry_i_ff ;
logic        m_wbd_we_i_ff  ;
logic        m_wbd_cyc_i_ff ;
logic        m_wbd_stb_i_ff ;
logic [3:0]  m_wbd_tid_i_ff ;
logic [31:0] s_wbd_dat_i_ff ;
logic        s_wbd_ack_i_ff ;
logic        s_wbd_lack_i_ff ;
logic        s_wbd_err_i_ff ;


assign s_wbd_dat_o = m_wbd_dat_i_ff;
assign s_wbd_adr_o = m_wbd_adr_i_ff;
assign s_wbd_sel_o = m_wbd_sel_i_ff;
assign s_wbd_bl_o  = m_wbd_bl_i_ff;
assign s_wbd_bry_o = m_wbd_bry_i_ff;
assign s_wbd_we_o  = m_wbd_we_i_ff;
assign s_wbd_cyc_o = m_wbd_cyc_i_ff;
assign s_wbd_stb_o = m_wbd_stb_i_ff;
assign s_wbd_tid_o = m_wbd_tid_i_ff;

assign m_wbd_dat_o = s_wbd_dat_i_ff;
assign m_wbd_ack_o = s_wbd_ack_i_ff;
assign m_wbd_lack_o = s_wbd_lack_i_ff;
assign m_wbd_err_o = s_wbd_err_i_ff;

always @(negedge rst_n or posedge clk_i)
begin
   if(rst_n == 1'b0) begin
       m_wbd_dat_i_ff <= 'h0;
       m_wbd_adr_i_ff <= 'h0;
       m_wbd_sel_i_ff <= 'h0;
       m_wbd_bl_i_ff  <= 'h0;
       m_wbd_bry_i_ff <= 'b0;
       m_wbd_we_i_ff  <= 'h0;
       m_wbd_cyc_i_ff <= 'h0;
       m_wbd_stb_i_ff <= 'h0;
       m_wbd_tid_i_ff <= 'h0;
       s_wbd_dat_i_ff <= 'h0;
       s_wbd_ack_i_ff <= 'h0;
       s_wbd_lack_i_ff <= 'h0;
       s_wbd_err_i_ff <= 'h0;
   end else begin
       s_wbd_dat_i_ff  <= s_wbd_dat_i;
       s_wbd_ack_i_ff  <= s_wbd_ack_i;
       s_wbd_lack_i_ff <= s_wbd_lack_i;
       s_wbd_err_i_ff <= s_wbd_err_i;
       if((m_wbd_stb_i && m_wbd_bry_i && s_wbd_ack_i == 0 && m_wbd_lack_o == 0) ||
          (m_wbd_stb_i && m_wbd_bry_i && s_wbd_ack_i == 1 && s_wbd_lack_i == 0)) begin
          m_wbd_dat_i_ff <= m_wbd_dat_i;
          m_wbd_adr_i_ff <= m_wbd_adr_i;
          m_wbd_sel_i_ff <= m_wbd_sel_i;
          m_wbd_we_i_ff  <= m_wbd_we_i;
          m_wbd_cyc_i_ff <= m_wbd_cyc_i;
          m_wbd_stb_i_ff <= m_wbd_stb_i;
          m_wbd_tid_i_ff <= m_wbd_tid_i;
          m_wbd_bl_i_ff  <= m_wbd_bl_i;
          m_wbd_bry_i_ff <= 'b1;
       end else  if ((m_wbd_stb_i && !m_wbd_bry_i && s_wbd_ack_i == 1 && s_wbd_lack_i == 0)) begin
          m_wbd_bry_i_ff <= 'b0;
       end else if (s_wbd_lack_i) begin
          m_wbd_dat_i_ff <= 'h0;
          m_wbd_adr_i_ff <= 'h0;
          m_wbd_sel_i_ff <= 'h0;
          m_wbd_we_i_ff  <= 'h0;
          m_wbd_cyc_i_ff <= 'h0;
          m_wbd_stb_i_ff <= 'h0;
          m_wbd_tid_i_ff <= 'h0;
          m_wbd_bl_i_ff  <= 'h0;
          m_wbd_bry_i_ff <= 'b0;
       end
   end
end


endmodule