data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv
1: b'%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:14: Cannot find include file: common_cells/registers.svh\n`include "common_cells/registers.svh" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src,data/full_repos/permissive/473423187/common_cells/registers.svh\n             data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src,data/full_repos/permissive/473423187/common_cells/registers.svh.v\n             data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src,data/full_repos/permissive/473423187/common_cells/registers.svh.sv\n             common_cells/registers.svh\n             common_cells/registers.svh.v\n             common_cells/registers.svh.sv\n             obj_dir/common_cells/registers.svh\n             obj_dir/common_cells/registers.svh.v\n             obj_dir/common_cells/registers.svh.sv\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:17: syntax error, unexpected ::, expecting \')\' or \',\'\n  parameter fpnew_pkg::fp_format_e   FpFormat    = fpnew_pkg::fp_format_e\'(0),\n                     ^~\n                                                                                          : ... Perhaps \'fpnew_pkg\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:19: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter fpnew_pkg::pipe_config_t PipeConfig  = fpnew_pkg::BEFORE,\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:21: syntax error, unexpected parameter, expecting IDENTIFIER\n  parameter type                     AuxType     = logic,\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:23: syntax error, unexpected localparam, expecting IDENTIFIER\n  localparam int unsigned WIDTH = fpnew_pkg::fp_width(FpFormat)  \n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:23: syntax error, unexpected ::, expecting \';\'\n  localparam int unsigned WIDTH = fpnew_pkg::fp_width(FpFormat)  \n                                           ^~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:26: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input logic                  rst_ni,\n  ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:28: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input logic [1:0][WIDTH-1:0]     operands_i,  \n  ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:29: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input logic [1:0]                is_boxed_i,  \n  ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:30: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input fpnew_pkg::roundmode_e     rnd_mode_i,\n  ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:33: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input TagType                    tag_i,\n  ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:34: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input AuxType                    aux_i,\n  ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:36: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input  logic                     in_valid_i,\n  ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:37: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output logic                     in_ready_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:38: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input  logic                     flush_i,\n  ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:40: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output logic [WIDTH-1:0]         result_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:41: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output fpnew_pkg::status_t       status_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:43: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output fpnew_pkg::classmask_e    class_mask_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:45: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output TagType                   tag_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:46: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output AuxType                   aux_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:48: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output logic                     out_valid_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:49: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input  logic                     out_ready_i,\n  ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:51: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output logic                     busy_o\n  ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:57: syntax error, unexpected ::, expecting \';\'\n  localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(FpFormat);\n                                              ^~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:58: syntax error, unexpected ::, expecting \';\'\n  localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(FpFormat);\n                                              ^~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:60: syntax error, unexpected ::\n  localparam NUM_INP_REGS = (PipeConfig == fpnew_pkg::BEFORE || PipeConfig == fpnew_pkg::INSIDE)\n                                                    ^~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:65: syntax error, unexpected ::, expecting \';\'\n  localparam NUM_OUT_REGS = PipeConfig == fpnew_pkg::AFTER\n                                                   ^~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:86: syntax error, unexpected IDENTIFIER\n  fpnew_pkg::roundmode_e [0:NUM_INP_REGS]                 inp_pipe_rnd_mode_q;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:96: syntax error, unexpected assign\n  assign inp_pipe_operands_q[0] = operands_i;\n  ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:113: syntax error, unexpected assign\n    assign inp_pipe_ready[i] = inp_pipe_ready[i+1] | ~inp_pipe_valid_q[i+1];\n    ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:115: Define or directive not defined: \'`FFLARNC\'\n    `FFLARNC(inp_pipe_valid_q[i+1], inp_pipe_valid_q[i], inp_pipe_ready[i], flush_i, 1\'b0, clk_i, rst_ni)\n    ^~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:119: Define or directive not defined: \'`FFL\'\n    `FFL(inp_pipe_operands_q[i+1], inp_pipe_operands_q[i], reg_ena, \'0)\n    ^~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:120: Define or directive not defined: \'`FFL\'\n    `FFL(inp_pipe_is_boxed_q[i+1], inp_pipe_is_boxed_q[i], reg_ena, \'0)\n    ^~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:121: Define or directive not defined: \'`FFL\'\n    `FFL(inp_pipe_rnd_mode_q[i+1], inp_pipe_rnd_mode_q[i], reg_ena, fpnew_pkg::RNE)\n    ^~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:122: Define or directive not defined: \'`FFL\'\n    `FFL(inp_pipe_op_q[i+1],       inp_pipe_op_q[i],       reg_ena, fpnew_pkg::FMADD)\n    ^~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:123: Define or directive not defined: \'`FFL\'\n    `FFL(inp_pipe_op_mod_q[i+1],   inp_pipe_op_mod_q[i],   reg_ena, \'0)\n    ^~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:124: Define or directive not defined: \'`FFL\'\n    `FFL(inp_pipe_tag_q[i+1],      inp_pipe_tag_q[i],      reg_ena, TagType\'(\'0))\n    ^~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:125: Define or directive not defined: \'`FFL\'\n    `FFL(inp_pipe_aux_q[i+1],      inp_pipe_aux_q[i],      reg_ena, AuxType\'(\'0))\n    ^~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:144: syntax error, unexpected IDENTIFIER\n  fpnew_pkg::fp_info_t info_a,    info_b;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:157: syntax error, unexpected assign\n  assign any_operand_inf = (| {info_a.is_inf,        info_b.is_inf});\n  ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:164: syntax error, unexpected assign\n  assign operands_equal    = (operand_a == operand_b) || (info_a.is_zero && info_b.is_zero);\n  ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:172: syntax error, unexpected IDENTIFIER\n  fpnew_pkg::status_t sgnj_status;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:177: syntax error, unexpected always_comb\n  always_comb begin : sign_injections\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:180: syntax error, unexpected IDENTIFIER\n    sgnj_result = operand_a;  \n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:208: syntax error, unexpected IDENTIFIER\n  fpnew_pkg::status_t minmax_status;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:213: syntax error, unexpected always_comb\n  always_comb begin : min_max\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:242: syntax error, unexpected IDENTIFIER\n  fpnew_pkg::status_t cmp_status;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:248: syntax error, unexpected always_comb\n  always_comb begin : comparisons\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:282: syntax error, unexpected IDENTIFIER\n  fpnew_pkg::classmask_e class_mask_d;  \n  ^~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/fpnew_noncomp.sv:308: syntax error, unexpected IDENTIFIER\n  fpnew_pkg::status_t    status_d;\n  ^~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module fpnew_noncomp #(
  parameter fpnew_pkg::fp_format_e   FpFormat    = fpnew_pkg::fp_format_e'(0),
  parameter int unsigned             NumPipeRegs = 0,
  parameter fpnew_pkg::pipe_config_t PipeConfig  = fpnew_pkg::BEFORE,
  parameter type                     TagType     = logic,
  parameter type                     AuxType     = logic,

  localparam int unsigned WIDTH = fpnew_pkg::fp_width(FpFormat)
) (
  input logic                  clk_i,
  input logic                  rst_ni,

  input logic [1:0][WIDTH-1:0]     operands_i,
  input logic [1:0]                is_boxed_i,
  input fpnew_pkg::roundmode_e     rnd_mode_i,
  input fpnew_pkg::operation_e     op_i,
  input logic                      op_mod_i,
  input TagType                    tag_i,
  input AuxType                    aux_i,

  input  logic                     in_valid_i,
  output logic                     in_ready_o,
  input  logic                     flush_i,

  output logic [WIDTH-1:0]         result_o,
  output fpnew_pkg::status_t       status_o,
  output logic                     extension_bit_o,
  output fpnew_pkg::classmask_e    class_mask_o,
  output logic                     is_class_o,
  output TagType                   tag_o,
  output AuxType                   aux_o,

  output logic                     out_valid_o,
  input  logic                     out_ready_i,

  output logic                     busy_o
);




  localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(FpFormat);
  localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(FpFormat);

  localparam NUM_INP_REGS = (PipeConfig == fpnew_pkg::BEFORE || PipeConfig == fpnew_pkg::INSIDE)
                            ? NumPipeRegs
                            : (PipeConfig == fpnew_pkg::DISTRIBUTED
                               ? ((NumPipeRegs + 1) / 2)
                               : 0);
  localparam NUM_OUT_REGS = PipeConfig == fpnew_pkg::AFTER
                            ? NumPipeRegs
                            : (PipeConfig == fpnew_pkg::DISTRIBUTED
                               ? (NumPipeRegs / 2)
                               : 0);




  typedef struct packed {
    logic                sign;
    logic [EXP_BITS-1:0] exponent;
    logic [MAN_BITS-1:0] mantissa;
  } fp_t;





  logic                  [0:NUM_INP_REGS][1:0][WIDTH-1:0] inp_pipe_operands_q;
  logic                  [0:NUM_INP_REGS][1:0]            inp_pipe_is_boxed_q;
  fpnew_pkg::roundmode_e [0:NUM_INP_REGS]                 inp_pipe_rnd_mode_q;
  fpnew_pkg::operation_e [0:NUM_INP_REGS]                 inp_pipe_op_q;
  logic                  [0:NUM_INP_REGS]                 inp_pipe_op_mod_q;
  TagType                [0:NUM_INP_REGS]                 inp_pipe_tag_q;
  AuxType                [0:NUM_INP_REGS]                 inp_pipe_aux_q;
  logic                  [0:NUM_INP_REGS]                 inp_pipe_valid_q;

  logic [0:NUM_INP_REGS] inp_pipe_ready;


  assign inp_pipe_operands_q[0] = operands_i;
  assign inp_pipe_is_boxed_q[0] = is_boxed_i;
  assign inp_pipe_rnd_mode_q[0] = rnd_mode_i;
  assign inp_pipe_op_q[0]       = op_i;
  assign inp_pipe_op_mod_q[0]   = op_mod_i;
  assign inp_pipe_tag_q[0]      = tag_i;
  assign inp_pipe_aux_q[0]      = aux_i;
  assign inp_pipe_valid_q[0]    = in_valid_i;

  assign in_ready_o = inp_pipe_ready[0];

  for (genvar i = 0; i < NUM_INP_REGS; i++) begin : gen_input_pipeline

    logic reg_ena;



    assign inp_pipe_ready[i] = inp_pipe_ready[i+1] | ~inp_pipe_valid_q[i+1];

    `FFLARNC(inp_pipe_valid_q[i+1], inp_pipe_valid_q[i], inp_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni)

    assign reg_ena = inp_pipe_ready[i] & inp_pipe_valid_q[i];

    `FFL(inp_pipe_operands_q[i+1], inp_pipe_operands_q[i], reg_ena, '0)
    `FFL(inp_pipe_is_boxed_q[i+1], inp_pipe_is_boxed_q[i], reg_ena, '0)
    `FFL(inp_pipe_rnd_mode_q[i+1], inp_pipe_rnd_mode_q[i], reg_ena, fpnew_pkg::RNE)
    `FFL(inp_pipe_op_q[i+1],       inp_pipe_op_q[i],       reg_ena, fpnew_pkg::FMADD)
    `FFL(inp_pipe_op_mod_q[i+1],   inp_pipe_op_mod_q[i],   reg_ena, '0)
    `FFL(inp_pipe_tag_q[i+1],      inp_pipe_tag_q[i],      reg_ena, TagType'('0))
    `FFL(inp_pipe_aux_q[i+1],      inp_pipe_aux_q[i],      reg_ena, AuxType'('0))
  end




  fpnew_pkg::fp_info_t [1:0] info_q;


  fpnew_classifier #(
    .FpFormat    ( FpFormat ),
    .NumOperands ( 2        )
    ) i_class_a (
    .operands_i ( inp_pipe_operands_q[NUM_INP_REGS] ),
    .is_boxed_i ( inp_pipe_is_boxed_q[NUM_INP_REGS] ),
    .info_o     ( info_q                            )
  );

  fp_t                 operand_a, operand_b;
  fpnew_pkg::fp_info_t info_a,    info_b;


  assign operand_a = inp_pipe_operands_q[NUM_INP_REGS][0];
  assign operand_b = inp_pipe_operands_q[NUM_INP_REGS][1];
  assign info_a    = info_q[0];
  assign info_b    = info_q[1];

  logic any_operand_inf;
  logic any_operand_nan;
  logic signalling_nan;


  assign any_operand_inf = (| {info_a.is_inf,        info_b.is_inf});
  assign any_operand_nan = (| {info_a.is_nan,        info_b.is_nan});
  assign signalling_nan  = (| {info_a.is_signalling, info_b.is_signalling});

  logic operands_equal, operand_a_smaller;


  assign operands_equal    = (operand_a == operand_b) || (info_a.is_zero && info_b.is_zero);

  assign operand_a_smaller = (operand_a < operand_b) ^ (operand_a.sign || operand_b.sign);




  fp_t                sgnj_result;
  fpnew_pkg::status_t sgnj_status;
  logic               sgnj_extension_bit;



  always_comb begin : sign_injections
    logic sign_a, sign_b;

    sgnj_result = operand_a;


    if (!info_a.is_boxed) sgnj_result = '{sign: 1'b0, exponent: '1, mantissa: 2**(MAN_BITS-1)};


    sign_a = operand_a.sign & info_a.is_boxed;
    sign_b = operand_b.sign & info_b.is_boxed;


    unique case (inp_pipe_rnd_mode_q[NUM_INP_REGS])
      fpnew_pkg::RNE: sgnj_result.sign = sign_b;
      fpnew_pkg::RTZ: sgnj_result.sign = ~sign_b;
      fpnew_pkg::RDN: sgnj_result.sign = sign_a ^ sign_b;
      fpnew_pkg::RUP: sgnj_result      = operand_a;
      default: sgnj_result = '{default: fpnew_pkg::DONT_CARE};
    endcase
  end

  assign sgnj_status = '0;


  assign sgnj_extension_bit = inp_pipe_op_mod_q[NUM_INP_REGS] ? sgnj_result.sign : 1'b1;




  fp_t                minmax_result;
  fpnew_pkg::status_t minmax_status;
  logic               minmax_extension_bit;



  always_comb begin : min_max

    minmax_status = '0;


    minmax_status.NV = signalling_nan;


    if (info_a.is_nan && info_b.is_nan)
      minmax_result = '{sign: 1'b0, exponent: '1, mantissa: 2**(MAN_BITS-1)};

    else if (info_a.is_nan) minmax_result = operand_b;
    else if (info_b.is_nan) minmax_result = operand_a;

    else begin
      unique case (inp_pipe_rnd_mode_q[NUM_INP_REGS])
        fpnew_pkg::RNE: minmax_result = operand_a_smaller ? operand_a : operand_b;
        fpnew_pkg::RTZ: minmax_result = operand_a_smaller ? operand_b : operand_a;
        default: minmax_result = '{default: fpnew_pkg::DONT_CARE};
      endcase
    end
  end

  assign minmax_extension_bit = 1'b1;




  fp_t                cmp_result;
  fpnew_pkg::status_t cmp_status;
  logic               cmp_extension_bit;




  always_comb begin : comparisons

    cmp_result = '0;
    cmp_status = '0;


    if (signalling_nan) cmp_status.NV = 1'b1;

    else begin
      unique case (inp_pipe_rnd_mode_q[NUM_INP_REGS])
        fpnew_pkg::RNE: begin
          if (any_operand_nan) cmp_status.NV = 1'b1;
          else cmp_result = (operand_a_smaller | operands_equal) ^ inp_pipe_op_mod_q[NUM_INP_REGS];
        end
        fpnew_pkg::RTZ: begin
          if (any_operand_nan) cmp_status.NV = 1'b1;
          else cmp_result = (operand_a_smaller & ~operands_equal) ^ inp_pipe_op_mod_q[NUM_INP_REGS];
        end
        fpnew_pkg::RDN: begin
          if (any_operand_nan) cmp_result = inp_pipe_op_mod_q[NUM_INP_REGS];
          else cmp_result = operands_equal ^ inp_pipe_op_mod_q[NUM_INP_REGS];
        end
        default: cmp_result = '{default: fpnew_pkg::DONT_CARE};
      endcase
    end
  end

  assign cmp_extension_bit = 1'b0;




  fpnew_pkg::status_t    class_status;
  logic                  class_extension_bit;
  fpnew_pkg::classmask_e class_mask_d;


  always_comb begin : classify
    if (info_a.is_normal) begin
      class_mask_d = operand_a.sign       ? fpnew_pkg::NEGNORM    : fpnew_pkg::POSNORM;
    end else if (info_a.is_subnormal) begin
      class_mask_d = operand_a.sign       ? fpnew_pkg::NEGSUBNORM : fpnew_pkg::POSSUBNORM;
    end else if (info_a.is_zero) begin
      class_mask_d = operand_a.sign       ? fpnew_pkg::NEGZERO    : fpnew_pkg::POSZERO;
    end else if (info_a.is_inf) begin
      class_mask_d = operand_a.sign       ? fpnew_pkg::NEGINF     : fpnew_pkg::POSINF;
    end else if (info_a.is_nan) begin
      class_mask_d = info_a.is_signalling ? fpnew_pkg::SNAN       : fpnew_pkg::QNAN;
    end else begin
      class_mask_d = fpnew_pkg::QNAN;
    end
  end

  assign class_status        = '0;
  assign class_extension_bit = 1'b0;




  fp_t                   result_d;
  fpnew_pkg::status_t    status_d;
  logic                  extension_bit_d;
  logic                  is_class_d;


  always_comb begin : select_result
    unique case (inp_pipe_op_q[NUM_INP_REGS])
      fpnew_pkg::SGNJ: begin
        result_d        = sgnj_result;
        status_d        = sgnj_status;
        extension_bit_d = sgnj_extension_bit;
      end
      fpnew_pkg::MINMAX: begin
        result_d        = minmax_result;
        status_d        = minmax_status;
        extension_bit_d = minmax_extension_bit;
      end
      fpnew_pkg::CMP: begin
        result_d        = cmp_result;
        status_d        = cmp_status;
        extension_bit_d = cmp_extension_bit;
      end
      fpnew_pkg::CLASSIFY: begin
        result_d        = '{default: fpnew_pkg::DONT_CARE};
        status_d        = class_status;
        extension_bit_d = class_extension_bit;
      end
      default: begin
        result_d        = '{default: fpnew_pkg::DONT_CARE};
        status_d        = '{default: fpnew_pkg::DONT_CARE};
        extension_bit_d = fpnew_pkg::DONT_CARE;
      end
    endcase
  end

  assign is_class_d = (inp_pipe_op_q[NUM_INP_REGS] == fpnew_pkg::CLASSIFY);





  fp_t                   [0:NUM_OUT_REGS] out_pipe_result_q;
  fpnew_pkg::status_t    [0:NUM_OUT_REGS] out_pipe_status_q;
  logic                  [0:NUM_OUT_REGS] out_pipe_extension_bit_q;
  fpnew_pkg::classmask_e [0:NUM_OUT_REGS] out_pipe_class_mask_q;
  logic                  [0:NUM_OUT_REGS] out_pipe_is_class_q;
  TagType                [0:NUM_OUT_REGS] out_pipe_tag_q;
  AuxType                [0:NUM_OUT_REGS] out_pipe_aux_q;
  logic                  [0:NUM_OUT_REGS] out_pipe_valid_q;

  logic [0:NUM_OUT_REGS] out_pipe_ready;


  assign out_pipe_result_q[0]        = result_d;
  assign out_pipe_status_q[0]        = status_d;
  assign out_pipe_extension_bit_q[0] = extension_bit_d;
  assign out_pipe_class_mask_q[0]    = class_mask_d;
  assign out_pipe_is_class_q[0]      = is_class_d;
  assign out_pipe_tag_q[0]           = inp_pipe_tag_q[NUM_INP_REGS];
  assign out_pipe_aux_q[0]           = inp_pipe_aux_q[NUM_INP_REGS];
  assign out_pipe_valid_q[0]         = inp_pipe_valid_q[NUM_INP_REGS];

  assign inp_pipe_ready[NUM_INP_REGS] = out_pipe_ready[0];

  for (genvar i = 0; i < NUM_OUT_REGS; i++) begin : gen_output_pipeline

    logic reg_ena;



    assign out_pipe_ready[i] = out_pipe_ready[i+1] | ~out_pipe_valid_q[i+1];

    `FFLARNC(out_pipe_valid_q[i+1], out_pipe_valid_q[i], out_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni)

    assign reg_ena = out_pipe_ready[i] & out_pipe_valid_q[i];

    `FFL(out_pipe_result_q[i+1],        out_pipe_result_q[i],        reg_ena, '0)
    `FFL(out_pipe_status_q[i+1],        out_pipe_status_q[i],        reg_ena, '0)
    `FFL(out_pipe_extension_bit_q[i+1], out_pipe_extension_bit_q[i], reg_ena, '0)
    `FFL(out_pipe_class_mask_q[i+1],    out_pipe_class_mask_q[i],    reg_ena, fpnew_pkg::QNAN)
    `FFL(out_pipe_is_class_q[i+1],      out_pipe_is_class_q[i],      reg_ena, '0)
    `FFL(out_pipe_tag_q[i+1],           out_pipe_tag_q[i],           reg_ena, TagType'('0))
    `FFL(out_pipe_aux_q[i+1],           out_pipe_aux_q[i],           reg_ena, AuxType'('0))
  end

  assign out_pipe_ready[NUM_OUT_REGS] = out_ready_i;

  assign result_o        = out_pipe_result_q[NUM_OUT_REGS];
  assign status_o        = out_pipe_status_q[NUM_OUT_REGS];
  assign extension_bit_o = out_pipe_extension_bit_q[NUM_OUT_REGS];
  assign class_mask_o    = out_pipe_class_mask_q[NUM_OUT_REGS];
  assign is_class_o      = out_pipe_is_class_q[NUM_OUT_REGS];
  assign tag_o           = out_pipe_tag_q[NUM_OUT_REGS];
  assign aux_o           = out_pipe_aux_q[NUM_OUT_REGS];
  assign out_valid_o     = out_pipe_valid_q[NUM_OUT_REGS];
  assign busy_o          = (| {inp_pipe_valid_q, out_pipe_valid_q});
endmodule
module fpnew_noncomp #(
  parameter fpnew_pkg::fp_format_e   FpFormat    = fpnew_pkg::fp_format_e'(0),
  parameter int unsigned             NumPipeRegs = 0,
  parameter fpnew_pkg::pipe_config_t PipeConfig  = fpnew_pkg::BEFORE,
  parameter type                     TagType     = logic,
  parameter type                     AuxType     = logic,

  localparam int unsigned WIDTH = fpnew_pkg::fp_width(FpFormat)
) (
  input logic                  clk_i,
  input logic                  rst_ni,

  input logic [1:0][WIDTH-1:0]     operands_i,
  input logic [1:0]                is_boxed_i,
  input fpnew_pkg::roundmode_e     rnd_mode_i,
  input fpnew_pkg::operation_e     op_i,
  input logic                      op_mod_i,
  input TagType                    tag_i,
  input AuxType                    aux_i,

  input  logic                     in_valid_i,
  output logic                     in_ready_o,
  input  logic                     flush_i,

  output logic [WIDTH-1:0]         result_o,
  output fpnew_pkg::status_t       status_o,
  output logic                     extension_bit_o,
  output fpnew_pkg::classmask_e    class_mask_o,
  output logic                     is_class_o,
  output TagType                   tag_o,
  output AuxType                   aux_o,

  output logic                     out_valid_o,
  input  logic                     out_ready_i,

  output logic                     busy_o
);





  localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(FpFormat);
  localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(FpFormat);

  localparam NUM_INP_REGS = (PipeConfig == fpnew_pkg::BEFORE || PipeConfig == fpnew_pkg::INSIDE)
                            ? NumPipeRegs
                            : (PipeConfig == fpnew_pkg::DISTRIBUTED
                               ? ((NumPipeRegs + 1) / 2)
                               : 0);
  localparam NUM_OUT_REGS = PipeConfig == fpnew_pkg::AFTER
                            ? NumPipeRegs
                            : (PipeConfig == fpnew_pkg::DISTRIBUTED
                               ? (NumPipeRegs / 2)
                               : 0);




  typedef struct packed {
    logic                sign;
    logic [EXP_BITS-1:0] exponent;
    logic [MAN_BITS-1:0] mantissa;
  } fp_t;





  logic                  [0:NUM_INP_REGS][1:0][WIDTH-1:0] inp_pipe_operands_q;
  logic                  [0:NUM_INP_REGS][1:0]            inp_pipe_is_boxed_q;
  fpnew_pkg::roundmode_e [0:NUM_INP_REGS]                 inp_pipe_rnd_mode_q;
  fpnew_pkg::operation_e [0:NUM_INP_REGS]                 inp_pipe_op_q;
  logic                  [0:NUM_INP_REGS]                 inp_pipe_op_mod_q;
  TagType                [0:NUM_INP_REGS]                 inp_pipe_tag_q;
  AuxType                [0:NUM_INP_REGS]                 inp_pipe_aux_q;
  logic                  [0:NUM_INP_REGS]                 inp_pipe_valid_q;

  logic [0:NUM_INP_REGS] inp_pipe_ready;


  assign inp_pipe_operands_q[0] = operands_i;
  assign inp_pipe_is_boxed_q[0] = is_boxed_i;
  assign inp_pipe_rnd_mode_q[0] = rnd_mode_i;
  assign inp_pipe_op_q[0]       = op_i;
  assign inp_pipe_op_mod_q[0]   = op_mod_i;
  assign inp_pipe_tag_q[0]      = tag_i;
  assign inp_pipe_aux_q[0]      = aux_i;
  assign inp_pipe_valid_q[0]    = in_valid_i;

  assign in_ready_o = inp_pipe_ready[0];

  for (genvar i = 0; i < NUM_INP_REGS; i++) begin : gen_input_pipeline

    logic reg_ena;



    assign inp_pipe_ready[i] = inp_pipe_ready[i+1] | ~inp_pipe_valid_q[i+1];

    `FFLARNC(inp_pipe_valid_q[i+1], inp_pipe_valid_q[i], inp_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni)

    assign reg_ena = inp_pipe_ready[i] & inp_pipe_valid_q[i];

    `FFL(inp_pipe_operands_q[i+1], inp_pipe_operands_q[i], reg_ena, '0)
    `FFL(inp_pipe_is_boxed_q[i+1], inp_pipe_is_boxed_q[i], reg_ena, '0)
    `FFL(inp_pipe_rnd_mode_q[i+1], inp_pipe_rnd_mode_q[i], reg_ena, fpnew_pkg::RNE)
    `FFL(inp_pipe_op_q[i+1],       inp_pipe_op_q[i],       reg_ena, fpnew_pkg::FMADD)
    `FFL(inp_pipe_op_mod_q[i+1],   inp_pipe_op_mod_q[i],   reg_ena, '0)
    `FFL(inp_pipe_tag_q[i+1],      inp_pipe_tag_q[i],      reg_ena, TagType'('0))
    `FFL(inp_pipe_aux_q[i+1],      inp_pipe_aux_q[i],      reg_ena, AuxType'('0))
  end




  fpnew_pkg::fp_info_t [1:0] info_q;


  fpnew_classifier #(
    .FpFormat    ( FpFormat ),
    .NumOperands ( 2        )
    ) i_class_a (
    .operands_i ( inp_pipe_operands_q[NUM_INP_REGS] ),
    .is_boxed_i ( inp_pipe_is_boxed_q[NUM_INP_REGS] ),
    .info_o     ( info_q                            )
  );

  fp_t                 operand_a, operand_b;
  fpnew_pkg::fp_info_t info_a,    info_b;


  assign operand_a = inp_pipe_operands_q[NUM_INP_REGS][0];
  assign operand_b = inp_pipe_operands_q[NUM_INP_REGS][1];
  assign info_a    = info_q[0];
  assign info_b    = info_q[1];

  logic any_operand_inf;
  logic any_operand_nan;
  logic signalling_nan;


  assign any_operand_inf = (| {info_a.is_inf,        info_b.is_inf});
  assign any_operand_nan = (| {info_a.is_nan,        info_b.is_nan});
  assign signalling_nan  = (| {info_a.is_signalling, info_b.is_signalling});

  logic operands_equal, operand_a_smaller;


  assign operands_equal    = (operand_a == operand_b) || (info_a.is_zero && info_b.is_zero);

  assign operand_a_smaller = (operand_a < operand_b) ^ (operand_a.sign || operand_b.sign);




  fp_t                sgnj_result;
  fpnew_pkg::status_t sgnj_status;
  logic               sgnj_extension_bit;



  always_comb begin : sign_injections
    logic sign_a, sign_b;

    sgnj_result = operand_a;


    if (!info_a.is_boxed) sgnj_result = '{sign: 1'b0, exponent: '1, mantissa: 2**(MAN_BITS-1)};


    sign_a = operand_a.sign & info_a.is_boxed;
    sign_b = operand_b.sign & info_b.is_boxed;


    unique case (inp_pipe_rnd_mode_q[NUM_INP_REGS])
      fpnew_pkg::RNE: sgnj_result.sign = sign_b;
      fpnew_pkg::RTZ: sgnj_result.sign = ~sign_b;
      fpnew_pkg::RDN: sgnj_result.sign = sign_a ^ sign_b;
      fpnew_pkg::RUP: sgnj_result      = operand_a;
      default: sgnj_result = '{default: fpnew_pkg::DONT_CARE};
    endcase
  end

  assign sgnj_status = '0;


  assign sgnj_extension_bit = inp_pipe_op_mod_q[NUM_INP_REGS] ? sgnj_result.sign : 1'b1;




  fp_t                minmax_result;
  fpnew_pkg::status_t minmax_status;
  logic               minmax_extension_bit;



  always_comb begin : min_max

    minmax_status = '0;


    minmax_status.NV = signalling_nan;


    if (info_a.is_nan && info_b.is_nan)
      minmax_result = '{sign: 1'b0, exponent: '1, mantissa: 2**(MAN_BITS-1)};

    else if (info_a.is_nan) minmax_result = operand_b;
    else if (info_b.is_nan) minmax_result = operand_a;

    else begin
      unique case (inp_pipe_rnd_mode_q[NUM_INP_REGS])
        fpnew_pkg::RNE: minmax_result = operand_a_smaller ? operand_a : operand_b;
        fpnew_pkg::RTZ: minmax_result = operand_a_smaller ? operand_b : operand_a;
        default: minmax_result = '{default: fpnew_pkg::DONT_CARE};
      endcase
    end
  end

  assign minmax_extension_bit = 1'b1;




  fp_t                cmp_result;
  fpnew_pkg::status_t cmp_status;
  logic               cmp_extension_bit;




  always_comb begin : comparisons

    cmp_result = '0;
    cmp_status = '0;


    if (signalling_nan) cmp_status.NV = 1'b1;

    else begin
      unique case (inp_pipe_rnd_mode_q[NUM_INP_REGS])
        fpnew_pkg::RNE: begin
          if (any_operand_nan) cmp_status.NV = 1'b1;
          else cmp_result = (operand_a_smaller | operands_equal) ^ inp_pipe_op_mod_q[NUM_INP_REGS];
        end
        fpnew_pkg::RTZ: begin
          if (any_operand_nan) cmp_status.NV = 1'b1;
          else cmp_result = (operand_a_smaller & ~operands_equal) ^ inp_pipe_op_mod_q[NUM_INP_REGS];
        end
        fpnew_pkg::RDN: begin
          if (any_operand_nan) cmp_result = inp_pipe_op_mod_q[NUM_INP_REGS];
          else cmp_result = operands_equal ^ inp_pipe_op_mod_q[NUM_INP_REGS];
        end
        default: cmp_result = '{default: fpnew_pkg::DONT_CARE};
      endcase
    end
  end

  assign cmp_extension_bit = 1'b0;




  fpnew_pkg::status_t    class_status;
  logic                  class_extension_bit;
  fpnew_pkg::classmask_e class_mask_d;


  always_comb begin : classify
    if (info_a.is_normal) begin
      class_mask_d = operand_a.sign       ? fpnew_pkg::NEGNORM    : fpnew_pkg::POSNORM;
    end else if (info_a.is_subnormal) begin
      class_mask_d = operand_a.sign       ? fpnew_pkg::NEGSUBNORM : fpnew_pkg::POSSUBNORM;
    end else if (info_a.is_zero) begin
      class_mask_d = operand_a.sign       ? fpnew_pkg::NEGZERO    : fpnew_pkg::POSZERO;
    end else if (info_a.is_inf) begin
      class_mask_d = operand_a.sign       ? fpnew_pkg::NEGINF     : fpnew_pkg::POSINF;
    end else if (info_a.is_nan) begin
      class_mask_d = info_a.is_signalling ? fpnew_pkg::SNAN       : fpnew_pkg::QNAN;
    end else begin
      class_mask_d = fpnew_pkg::QNAN;
    end
  end

  assign class_status        = '0;
  assign class_extension_bit = 1'b0;




  fp_t                   result_d;
  fpnew_pkg::status_t    status_d;
  logic                  extension_bit_d;
  logic                  is_class_d;


  always_comb begin : select_result
    unique case (inp_pipe_op_q[NUM_INP_REGS])
      fpnew_pkg::SGNJ: begin
        result_d        = sgnj_result;
        status_d        = sgnj_status;
        extension_bit_d = sgnj_extension_bit;
      end
      fpnew_pkg::MINMAX: begin
        result_d        = minmax_result;
        status_d        = minmax_status;
        extension_bit_d = minmax_extension_bit;
      end
      fpnew_pkg::CMP: begin
        result_d        = cmp_result;
        status_d        = cmp_status;
        extension_bit_d = cmp_extension_bit;
      end
      fpnew_pkg::CLASSIFY: begin
        result_d        = '{default: fpnew_pkg::DONT_CARE};
        status_d        = class_status;
        extension_bit_d = class_extension_bit;
      end
      default: begin
        result_d        = '{default: fpnew_pkg::DONT_CARE};
        status_d        = '{default: fpnew_pkg::DONT_CARE};
        extension_bit_d = fpnew_pkg::DONT_CARE;
      end
    endcase
  end

  assign is_class_d = (inp_pipe_op_q[NUM_INP_REGS] == fpnew_pkg::CLASSIFY);





  fp_t                   [0:NUM_OUT_REGS] out_pipe_result_q;
  fpnew_pkg::status_t    [0:NUM_OUT_REGS] out_pipe_status_q;
  logic                  [0:NUM_OUT_REGS] out_pipe_extension_bit_q;
  fpnew_pkg::classmask_e [0:NUM_OUT_REGS] out_pipe_class_mask_q;
  logic                  [0:NUM_OUT_REGS] out_pipe_is_class_q;
  TagType                [0:NUM_OUT_REGS] out_pipe_tag_q;
  AuxType                [0:NUM_OUT_REGS] out_pipe_aux_q;
  logic                  [0:NUM_OUT_REGS] out_pipe_valid_q;

  logic [0:NUM_OUT_REGS] out_pipe_ready;


  assign out_pipe_result_q[0]        = result_d;
  assign out_pipe_status_q[0]        = status_d;
  assign out_pipe_extension_bit_q[0] = extension_bit_d;
  assign out_pipe_class_mask_q[0]    = class_mask_d;
  assign out_pipe_is_class_q[0]      = is_class_d;
  assign out_pipe_tag_q[0]           = inp_pipe_tag_q[NUM_INP_REGS];
  assign out_pipe_aux_q[0]           = inp_pipe_aux_q[NUM_INP_REGS];
  assign out_pipe_valid_q[0]         = inp_pipe_valid_q[NUM_INP_REGS];

  assign inp_pipe_ready[NUM_INP_REGS] = out_pipe_ready[0];

  for (genvar i = 0; i < NUM_OUT_REGS; i++) begin : gen_output_pipeline

    logic reg_ena;



    assign out_pipe_ready[i] = out_pipe_ready[i+1] | ~out_pipe_valid_q[i+1];

    `FFLARNC(out_pipe_valid_q[i+1], out_pipe_valid_q[i], out_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni)

    assign reg_ena = out_pipe_ready[i] & out_pipe_valid_q[i];

    `FFL(out_pipe_result_q[i+1],        out_pipe_result_q[i],        reg_ena, '0)
    `FFL(out_pipe_status_q[i+1],        out_pipe_status_q[i],        reg_ena, '0)
    `FFL(out_pipe_extension_bit_q[i+1], out_pipe_extension_bit_q[i], reg_ena, '0)
    `FFL(out_pipe_class_mask_q[i+1],    out_pipe_class_mask_q[i],    reg_ena, fpnew_pkg::QNAN)
    `FFL(out_pipe_is_class_q[i+1],      out_pipe_is_class_q[i],      reg_ena, '0)
    `FFL(out_pipe_tag_q[i+1],           out_pipe_tag_q[i],           reg_ena, TagType'('0))
    `FFL(out_pipe_aux_q[i+1],           out_pipe_aux_q[i],           reg_ena, AuxType'('0))
  end

  assign out_pipe_ready[NUM_OUT_REGS] = out_ready_i;

  assign result_o        = out_pipe_result_q[NUM_OUT_REGS];
  assign status_o        = out_pipe_status_q[NUM_OUT_REGS];
  assign extension_bit_o = out_pipe_extension_bit_q[NUM_OUT_REGS];
  assign class_mask_o    = out_pipe_class_mask_q[NUM_OUT_REGS];
  assign is_class_o      = out_pipe_is_class_q[NUM_OUT_REGS];
  assign tag_o           = out_pipe_tag_q[NUM_OUT_REGS];
  assign aux_o           = out_pipe_aux_q[NUM_OUT_REGS];
  assign out_valid_o     = out_pipe_valid_q[NUM_OUT_REGS];
  assign busy_o          = (| {inp_pipe_valid_q, out_pipe_valid_q});
endmodule