data/full_repos/permissive/497870922/rtl/spi module/spi_master_top.v
1: b'%Error: Cannot find file containing module: module,data/full_repos/permissive/497870922\n        ... Looked in:\n             data/full_repos/permissive/497870922/rtl/spi/module,data/full_repos/permissive/497870922\n             data/full_repos/permissive/497870922/rtl/spi/module,data/full_repos/permissive/497870922.v\n             data/full_repos/permissive/497870922/rtl/spi/module,data/full_repos/permissive/497870922.sv\n             module,data/full_repos/permissive/497870922\n             module,data/full_repos/permissive/497870922.v\n             module,data/full_repos/permissive/497870922.sv\n             obj_dir/module,data/full_repos/permissive/497870922\n             obj_dir/module,data/full_repos/permissive/497870922.v\n             obj_dir/module,data/full_repos/permissive/497870922.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/497870922/rtl/spi\n%Error: Cannot find file containing module: module/spi_master_top.v\n%Error: Exiting due to 3 error(s)\n'
module spi_master_top(
   Clk
  ,Rst_n
  ,Wr
  ,Rd
  ,Addr
  ,DataIn
  ,DataOut
  ,SCLK
  ,MOSI
  ,MISO
  ,SS
  ,Int
  ,spi_cpol_debug
  ,spi_cpha_debug
);
parameter SIZE = 8;

input             Clk;
input             Rst_n;


input             Wr;
input             Rd;
input  [SIZE-1:0] Addr;
input  [SIZE-1:0] DataIn;
output [SIZE-1:0] DataOut;


output            SCLK;
output            MOSI;
input             MISO;
output [SIZE-1:0] SS;


output            Int;
output            spi_cpol_debug;
output            spi_cpha_debug;


wire              cPol;
wire              cPha;
wire              spr1,spr0;
wire   [SIZE-1:0] cPre;

wire              busy;
wire   [SIZE-1:0] spiSRRx;
wire   [SIZE-1:0] spiBuf;
wire              wrBuf;
wire              spie;
wire              spse;
wire              loadMaster;

assign spi_cpol_debug = cPol;
assign spi_cpha_debug = cPha;

spi_master_registers SPI_REG(
   .Clk               (Clk)
  ,.Rst_n             (Rst_n)

  ,.Wr                (Wr)
  ,.Rd                (Rd)
  ,.Addr              (Addr)
  ,.DataIn            (DataIn)
  ,.DataOut           (DataOut)

  ,.CPol              (cPol)
  ,.CPha              (cPha)
  ,.Spr1              (spr1)
  ,.Spr0              (spr0)
  ,.CPre              (cPre)

  ,.SS                (SS)

  ,.Busy              (busy)
  ,.SpiSRRx           (spiSRRx)
  ,.SpiBuf            (spiBuf)
  ,.WrBuf             (wrBuf)
  ,.Spie              (spie)
  ,.Spse              (spse)
  ,.LoadMaster        (loadMaster)
);

spi_master_controller MSTR_CTRL(
   .Clk               (Clk)
  ,.Rst_n             (Rst_n)

  ,.MI                (MISO)
  ,.MO                (MOSI)
  ,.SCLK              (SCLK)

  ,.CPre              (cPre)
  ,.CPol              (cPol)
  ,.CPha              (cPha)
  ,.Spr1              (spr1)
  ,.Spr0              (spr0)

  ,.Spie              (spie)
  ,.Spse              (spse)
  ,.LoadMaster        (loadMaster)
  ,.SpiBuf            (spiBuf)
  ,.Busy              (busy)
  ,.WrBuf             (wrBuf)
  ,.Int               (Int)
  ,.SpiSRRx           (spiSRRx)
);

endmodule
module spi_master_top(
   Clk
  ,Rst_n
  ,Wr
  ,Rd
  ,Addr
  ,DataIn
  ,DataOut
  ,SCLK
  ,MOSI
  ,MISO
  ,SS
  ,Int
  ,spi_cpol_debug
  ,spi_cpha_debug
);

parameter SIZE = 8;

input             Clk;
input             Rst_n;


input             Wr;
input             Rd;
input  [SIZE-1:0] Addr;
input  [SIZE-1:0] DataIn;
output [SIZE-1:0] DataOut;


output            SCLK;
output            MOSI;
input             MISO;
output [SIZE-1:0] SS;


output            Int;
output            spi_cpol_debug;
output            spi_cpha_debug;


wire              cPol;
wire              cPha;
wire              spr1,spr0;
wire   [SIZE-1:0] cPre;

wire              busy;
wire   [SIZE-1:0] spiSRRx;
wire   [SIZE-1:0] spiBuf;
wire              wrBuf;
wire              spie;
wire              spse;
wire              loadMaster;

assign spi_cpol_debug = cPol;
assign spi_cpha_debug = cPha;

spi_master_registers SPI_REG(
   .Clk               (Clk)
  ,.Rst_n             (Rst_n)

  ,.Wr                (Wr)
  ,.Rd                (Rd)
  ,.Addr              (Addr)
  ,.DataIn            (DataIn)
  ,.DataOut           (DataOut)

  ,.CPol              (cPol)
  ,.CPha              (cPha)
  ,.Spr1              (spr1)
  ,.Spr0              (spr0)
  ,.CPre              (cPre)

  ,.SS                (SS)

  ,.Busy              (busy)
  ,.SpiSRRx           (spiSRRx)
  ,.SpiBuf            (spiBuf)
  ,.WrBuf             (wrBuf)
  ,.Spie              (spie)
  ,.Spse              (spse)
  ,.LoadMaster        (loadMaster)
);

spi_master_controller MSTR_CTRL(
   .Clk               (Clk)
  ,.Rst_n             (Rst_n)

  ,.MI                (MISO)
  ,.MO                (MOSI)
  ,.SCLK              (SCLK)

  ,.CPre              (cPre)
  ,.CPol              (cPol)
  ,.CPha              (cPha)
  ,.Spr1              (spr1)
  ,.Spr0              (spr0)

  ,.Spie              (spie)
  ,.Spse              (spse)
  ,.LoadMaster        (loadMaster)
  ,.SpiBuf            (spiBuf)
  ,.Busy              (busy)
  ,.WrBuf             (wrBuf)
  ,.Int               (Int)
  ,.SpiSRRx           (spiSRRx)
);

endmodule