data/full_repos/permissive/458737381/src/verilog-parser/tests/aurora_201_pcore.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/458737381/src/verilog-parser/tests/aurora_201_pcore.v:289: Multiple top level modules\n                                                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                       : ... Top module \'aurora_201_pcore\'\nmodule aurora_201_pcore #\n       ^~~~~~~~~~~~~~~~\n                                                                                                       : ... Top module \'icon\'\nmodule icon \n       ^~~~\n                                                                                                       : ... Top module \'ila\'\nmodule ila\n       ^~~\n%Warning-LITENDIAN: data/full_repos/permissive/458737381/src/verilog-parser/tests/aurora_201_pcore.v:53: Little bit endian vector: MSB < LSB of bit range: 0:15\n    input   [0:15]     TX_D;\n            ^\n%Warning-LITENDIAN: data/full_repos/permissive/458737381/src/verilog-parser/tests/aurora_201_pcore.v:58: Little bit endian vector: MSB < LSB of bit range: 0:15\n    output  [0:15]     RX_D;\n            ^\n%Warning-LITENDIAN: data/full_repos/permissive/458737381/src/verilog-parser/tests/aurora_201_pcore.v:76: Little bit endian vector: MSB < LSB of bit range: 0:3\n    reg     [0:3]      reset_debounce_r;\n            ^\n%Warning-LITENDIAN: data/full_repos/permissive/458737381/src/verilog-parser/tests/aurora_201_pcore.v:77: Little bit endian vector: MSB < LSB of bit range: 0:3\n    reg     [0:3]      debounce_pma_init_r;\n            ^\n%Warning-LITENDIAN: data/full_repos/permissive/458737381/src/verilog-parser/tests/aurora_201_pcore.v:83: Little bit endian vector: MSB < LSB of bit range: 0:15\n    wire    [0:15]     tx_d_i;\n            ^\n%Warning-LITENDIAN: data/full_repos/permissive/458737381/src/verilog-parser/tests/aurora_201_pcore.v:87: Little bit endian vector: MSB < LSB of bit range: 0:15\n    wire    [0:15]     rx_d_i;\n            ^\n%Warning-LITENDIAN: data/full_repos/permissive/458737381/src/verilog-parser/tests/aurora_201_pcore.v:106: Little bit endian vector: MSB < LSB of bit range: 0:2\n    wire    [0:2]      loopback_i;\n            ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/aurora_201_pcore.v:115: Cannot find file containing module: \'IBUFDS\'\n IBUFDS IBUFDS\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/IBUFDS\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/IBUFDS.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/IBUFDS.sv\n             IBUFDS\n             IBUFDS.v\n             IBUFDS.sv\n             obj_dir/IBUFDS\n             obj_dir/IBUFDS.v\n             obj_dir/IBUFDS.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/aurora_201_pcore.v:121: Cannot find file containing module: \'BUFG\'\n BUFG BUFG\n ^~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/aurora_201_pcore.v:130: Cannot find file containing module: \'aurora_201_CLOCK_MODULE\'\n    aurora_201_CLOCK_MODULE clock_module_i\n    ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/aurora_201_pcore.v:191: Cannot find file containing module: \'aurora_201\'\n    aurora_201 #\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/aurora_201_pcore.v:231: Cannot find file containing module: \'aurora_201_STANDARD_CC_MODULE\'\n    aurora_201_STANDARD_CC_MODULE standard_cc_module_i\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s), 8 warning(s)\n'
module aurora_201_pcore #
(

     parameter   SIM_GTPRESET_SPEEDUP=   0,
     parameter   C_EXT_RESET_HIGH = 0
)
(

    RESET,
    USER_CLK,
    HARD_ERROR,
    SOFT_ERROR,
    LANE_UP,
    CHANNEL_UP,
    INIT_CLK,
    PMA_INIT,

    TX_D,
    TX_SRC_RDY,
    TX_DST_RDY,

    RX_D,
    RX_SRC_RDY,

    GTPD4_P,
    GTPD4_N,

    RXP,
    RXN,
    TXP,
    TXN
);
/

    aurora_201_CLOCK_MODULE clock_module_i
    (
        .GTP_CLK(buf_tx_out_clk_i),
        .GTP_CLK_LOCKED(tx_lock_i),
        .USER_CLK(user_clk_i),
        .SYNC_CLK(sync_clk_i),
        .DCM_NOT_LOCKED(dcm_not_locked_i)
    );




    always @(posedge user_clk_i)
    begin
        HARD_ERROR      <=  hard_error_i;
        SOFT_ERROR      <=  soft_error_i;
        LANE_UP         <=  lane_up_i;
        CHANNEL_UP      <=  channel_up_i;
    end


    assign tx_src_rdy_n_i = ~TX_SRC_RDY;
    assign TX_DST_RDY = ~tx_dst_rdy_n_i;
    assign RX_SRC_RDY = ~rx_src_rdy_n_i;
    assign tx_d_i = TX_D;
    assign RX_D = rx_d_i;
    assign USER_CLK = user_clk_i;



    assign  power_down_i        =   1'b0;
    assign  loopback_i          =   3'b000;






    always @(posedge user_clk_i or posedge pma_init_r)
        if(pma_init_r)
            reset_debounce_r    <=  4'b1111;    
        else
            reset_debounce_r    <=  {RESET,reset_debounce_r[0:2]};
    assign  reset_i =   &reset_debounce_r;



   assign init_clk_i = INIT_CLK;


    always @(posedge init_clk_i)
        debounce_pma_init_r <=  {PMA_INIT,debounce_pma_init_r[0:2]};
    assign  pma_init_r  =   &debounce_pma_init_r;


    aurora_201 #
    (
        .SIM_GTPRESET_SPEEDUP(SIM_GTPRESET_SPEEDUP)
    )
    aurora_module_i
    (

        .TX_D(tx_d_i),
        .TX_SRC_RDY_N(tx_src_rdy_n_i),
        .TX_DST_RDY_N(tx_dst_rdy_n_i),

        .RX_D(rx_d_i),
        .RX_SRC_RDY_N(rx_src_rdy_n_i),

        .RXP(RXP),
        .RXN(RXN),
        .TXP(TXP),
        .TXN(TXN),

        .GTPD4(GTPD4_left_i),

        .HARD_ERROR(hard_error_i),
        .SOFT_ERROR(soft_error_i),

        .CHANNEL_UP(channel_up_i),
        .LANE_UP(lane_up_i),

        .WARN_CC(warn_cc_i),
        .DO_CC(do_cc_i),

        .DCM_NOT_LOCKED(dcm_not_locked_i),
        .USER_CLK(user_clk_i),
        .SYNC_CLK(sync_clk_i),
        .RESET(reset_i),
        .POWER_DOWN(power_down_i),
        .LOOPBACK(loopback_i),
        .PMA_INIT(pma_init_r),
        .TX_LOCK(tx_lock_i),
        .TX_OUT_CLK(tx_out_clk_i)
    );
    aurora_201_STANDARD_CC_MODULE standard_cc_module_i
    (

        .WARN_CC(warn_cc_i),
        .DO_CC(do_cc_i),

        .DCM_NOT_LOCKED(dcm_not_locked_i),
        .USER_CLK(user_clk_i),
        .CHANNEL_UP(channel_up_i)
    );






  wire [35:0] control0;


































endmodule
module aurora_201_pcore #
(

     parameter   SIM_GTPRESET_SPEEDUP=   0,
     parameter   C_EXT_RESET_HIGH = 0
)
(

    RESET,
    USER_CLK,
    HARD_ERROR,
    SOFT_ERROR,
    LANE_UP,
    CHANNEL_UP,
    INIT_CLK,
    PMA_INIT,

    TX_D,
    TX_SRC_RDY,
    TX_DST_RDY,

    RX_D,
    RX_SRC_RDY,

    GTPD4_P,
    GTPD4_N,

    RXP,
    RXN,
    TXP,
    TXN
);

/

    aurora_201_CLOCK_MODULE clock_module_i
    (
        .GTP_CLK(buf_tx_out_clk_i),
        .GTP_CLK_LOCKED(tx_lock_i),
        .USER_CLK(user_clk_i),
        .SYNC_CLK(sync_clk_i),
        .DCM_NOT_LOCKED(dcm_not_locked_i)
    );




    always @(posedge user_clk_i)
    begin
        HARD_ERROR      <=  hard_error_i;
        SOFT_ERROR      <=  soft_error_i;
        LANE_UP         <=  lane_up_i;
        CHANNEL_UP      <=  channel_up_i;
    end


    assign tx_src_rdy_n_i = ~TX_SRC_RDY;
    assign TX_DST_RDY = ~tx_dst_rdy_n_i;
    assign RX_SRC_RDY = ~rx_src_rdy_n_i;
    assign tx_d_i = TX_D;
    assign RX_D = rx_d_i;
    assign USER_CLK = user_clk_i;



    assign  power_down_i        =   1'b0;
    assign  loopback_i          =   3'b000;






    always @(posedge user_clk_i or posedge pma_init_r)
        if(pma_init_r)
            reset_debounce_r    <=  4'b1111;    
        else
            reset_debounce_r    <=  {RESET,reset_debounce_r[0:2]};
    assign  reset_i =   &reset_debounce_r;



   assign init_clk_i = INIT_CLK;


    always @(posedge init_clk_i)
        debounce_pma_init_r <=  {PMA_INIT,debounce_pma_init_r[0:2]};
    assign  pma_init_r  =   &debounce_pma_init_r;


    aurora_201 #
    (
        .SIM_GTPRESET_SPEEDUP(SIM_GTPRESET_SPEEDUP)
    )
    aurora_module_i
    (

        .TX_D(tx_d_i),
        .TX_SRC_RDY_N(tx_src_rdy_n_i),
        .TX_DST_RDY_N(tx_dst_rdy_n_i),

        .RX_D(rx_d_i),
        .RX_SRC_RDY_N(rx_src_rdy_n_i),

        .RXP(RXP),
        .RXN(RXN),
        .TXP(TXP),
        .TXN(TXN),

        .GTPD4(GTPD4_left_i),

        .HARD_ERROR(hard_error_i),
        .SOFT_ERROR(soft_error_i),

        .CHANNEL_UP(channel_up_i),
        .LANE_UP(lane_up_i),

        .WARN_CC(warn_cc_i),
        .DO_CC(do_cc_i),

        .DCM_NOT_LOCKED(dcm_not_locked_i),
        .USER_CLK(user_clk_i),
        .SYNC_CLK(sync_clk_i),
        .RESET(reset_i),
        .POWER_DOWN(power_down_i),
        .LOOPBACK(loopback_i),
        .PMA_INIT(pma_init_r),
        .TX_LOCK(tx_lock_i),
        .TX_OUT_CLK(tx_out_clk_i)
    );
    aurora_201_STANDARD_CC_MODULE standard_cc_module_i
    (

        .WARN_CC(warn_cc_i),
        .DO_CC(do_cc_i),

        .DCM_NOT_LOCKED(dcm_not_locked_i),
        .USER_CLK(user_clk_i),
        .CHANNEL_UP(channel_up_i)
    );






  wire [35:0] control0;


































endmodule