data/full_repos/permissive/521337848/Hardware/SPISD/receiver.v
data/verilator_xmls/6b2e6e31-5c02-48da-a77c-065d76c7f3f2.xml
module receiverbuffer(
	input clk,
	input dclk,
	input rst,
	
	input[7:0] in,
	input readed,
	
	output reg[7:0] n_in,
	output reg n_readed
);

reg f_started = 0;
reg n_started = 0;

reg[7:0] nn_in;
reg nn_readed;

reg nreaded;
reg[7:0] nin;
always@(posedge clk or posedge rst)
	if(rst) begin
		nreaded <= 0;
		nin <= 0;
		end
	else begin
		nreaded <= readed;
		nin <= in;
		end
		
always@(posedge clk or posedge rst)
	if(rst) f_started <= 0;
	else f_started <= n_started;
	
always@(*)begin
	n_started = nreaded;
	
	nn_in = 0;
	nn_readed = 0;
	
	if(~f_started && nreaded)begin
		nn_in = nin;
		nn_readed = nreaded;
	end
	
end

always@(posedge clk or posedge rst)
	begin
		if(rst) begin
			n_in <= 0;
			n_readed <= 0;
		end
		else begin
			n_in <= nn_in;
			n_readed <= nn_readed;
		end
	end

endmodule
module receiverbuffer(
	input clk,
	input dclk,
	input rst,
	
	input[7:0] in,
	input readed,
	
	output reg[7:0] n_in,
	output reg n_readed
);


reg f_started = 0;
reg n_started = 0;

reg[7:0] nn_in;
reg nn_readed;

reg nreaded;
reg[7:0] nin;
always@(posedge clk or posedge rst)
	if(rst) begin
		nreaded <= 0;
		nin <= 0;
		end
	else begin
		nreaded <= readed;
		nin <= in;
		end
		
always@(posedge clk or posedge rst)
	if(rst) f_started <= 0;
	else f_started <= n_started;
	
always@(*)begin
	n_started = nreaded;
	
	nn_in = 0;
	nn_readed = 0;
	
	if(~f_started && nreaded)begin
		nn_in = nin;
		nn_readed = nreaded;
	end
	
end

always@(posedge clk or posedge rst)
	begin
		if(rst) begin
			n_in <= 0;
			n_readed <= 0;
		end
		else begin
			n_in <= nn_in;
			n_readed <= nn_readed;
		end
	end

endmodule