data/full_repos/permissive/469080355/me.v
data/verilator_xmls/eaab81a6-3f1c-4087-ba41-df986b099b6a.xml
module me (
        input wire clk_i,
        input wire rst_i,

        input wire [183:0] ref_data,
        input wire [63:0] cur_data,

        output wire clk_o,
        output wire rst_o,
        output wire [4095:0] me_result
    );

    reg [511:0] cur_block;

endmodule
module me (
        input wire clk_i,
        input wire rst_i,

        input wire [183:0] ref_data,
        input wire [63:0] cur_data,

        output wire clk_o,
        output wire rst_o,
        output wire [4095:0] me_result
    );


    reg [511:0] cur_block;

endmodule