data/full_repos/permissive/487368624/Lab M/cpu.v
1: b'%Error: Cannot find file containing module: M,data/full_repos/permissive/487368624\n        ... Looked in:\n             data/full_repos/permissive/487368624/Lab/M,data/full_repos/permissive/487368624\n             data/full_repos/permissive/487368624/Lab/M,data/full_repos/permissive/487368624.v\n             data/full_repos/permissive/487368624/Lab/M,data/full_repos/permissive/487368624.sv\n             M,data/full_repos/permissive/487368624\n             M,data/full_repos/permissive/487368624.v\n             M,data/full_repos/permissive/487368624.sv\n             obj_dir/M,data/full_repos/permissive/487368624\n             obj_dir/M,data/full_repos/permissive/487368624.v\n             obj_dir/M,data/full_repos/permissive/487368624.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/487368624/Lab\n%Error: Cannot find file containing module: M/cpu.v\n%Error: Exiting due to 3 error(s)\n'
module yIF(ins, PC, PCp4, PCin, clk);
output [31:0] ins, PC, PCp4;
input [31:0] PCin;
input clk;

wire zero;
wire read, write, enable;
wire [31:0] a, memIn;
wire [2:0] op;
 
register #(32) pc_reg(PC, PCin, clk, enable);
mem insMem(ins, PC, memIn, clk, read, write);
yAlu myAlu(PCp4, zero, a, PC, op);

assign enable = 1'b1;
assign a = 32'h0004;
assign op = 3'b010;
assign read = 1'b1;
assign write = 1'b0;

endmodule
module yIF(ins, PC, PCp4, PCin, clk);

output [31:0] ins, PC, PCp4;
input [31:0] PCin;
input clk;

wire zero;
wire read, write, enable;
wire [31:0] a, memIn;
wire [2:0] op;
 
register #(32) pc_reg(PC, PCin, clk, enable);
mem insMem(ins, PC, memIn, clk, read, write);
yAlu myAlu(PCp4, zero, a, PC, op);

assign enable = 1'b1;
assign a = 32'h0004;
assign op = 3'b010;
assign read = 1'b1;
assign write = 1'b0;

endmodule