data/full_repos/permissive/491294671/magnetron_control/tests/latch_sr_tb.v
1: b'%Error: data/full_repos/permissive/491294671/magnetron_control/tests/latch_sr_tb.v:4: Cannot find include file: ../hdl/latch_sr.v\n`include "../hdl/latch_sr.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/491294671/magnetron_control/tests,data/full_repos/permissive/491294671/../hdl/latch_sr.v\n             data/full_repos/permissive/491294671/magnetron_control/tests,data/full_repos/permissive/491294671/../hdl/latch_sr.v.v\n             data/full_repos/permissive/491294671/magnetron_control/tests,data/full_repos/permissive/491294671/../hdl/latch_sr.v.sv\n             ../hdl/latch_sr.v\n             ../hdl/latch_sr.v.v\n             ../hdl/latch_sr.v.sv\n             obj_dir/../hdl/latch_sr.v\n             obj_dir/../hdl/latch_sr.v.v\n             obj_dir/../hdl/latch_sr.v.sv\n%Error: data/full_repos/permissive/491294671/magnetron_control/tests/latch_sr_tb.v:15: Unsupported or unknown PLI call: $dumpfile\n            $dumpfile("latch_sr_tb.vcd");\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/491294671/magnetron_control/tests/latch_sr_tb.v:16: Unsupported or unknown PLI call: $dumpvars\n            $dumpvars(0, latch_sr_tb);\n            ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/491294671/magnetron_control/tests/latch_sr_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n            #10  r_tb=0; s_tb=1; \n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/491294671/magnetron_control/tests/latch_sr_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n            #10  r_tb=1; s_tb=0; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/491294671/magnetron_control/tests/latch_sr_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n            #10  r_tb=1; s_tb=1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/491294671/magnetron_control/tests/latch_sr_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n            #10  r_tb=0; s_tb=0;  \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/491294671/magnetron_control/tests/latch_sr_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n            #10  r_tb=0; s_tb=1; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/491294671/magnetron_control/tests/latch_sr_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n            #10  r_tb=1; s_tb=0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/491294671/magnetron_control/tests/latch_sr_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n            #10  r_tb=1; s_tb=1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/491294671/magnetron_control/tests/latch_sr_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n            #10  r_tb=0; s_tb=0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/491294671/magnetron_control/tests/latch_sr_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n            #10  r_tb=0; s_tb=1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/491294671/magnetron_control/tests/latch_sr_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n            #10  r_tb=1; s_tb=0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/491294671/magnetron_control/tests/latch_sr_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n            #10  r_tb=1; s_tb=1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/491294671/magnetron_control/tests/latch_sr_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Error: Exiting due to 3 error(s), 12 warning(s)\n'
module latch_sr_tb();

    reg s_tb,r_tb;
    wire q_tb;
    
    latch_sr UUT(.s(s_tb), .r(r_tb), .q(q_tb));
    
    initial 
        begin
            $dumpfile("latch_sr_tb.vcd");
            $dumpvars(0, latch_sr_tb);

                 r_tb=0; s_tb=0; 
            #10  r_tb=0; s_tb=1; 
            #10  r_tb=1; s_tb=0; 
            #10  r_tb=1; s_tb=1;
            #10  r_tb=0; s_tb=0;  
            #10  r_tb=0; s_tb=1; 
            #10  r_tb=1; s_tb=0;
            #10  r_tb=1; s_tb=1;
            #10  r_tb=0; s_tb=0;
            #10  r_tb=0; s_tb=1;
            #10  r_tb=1; s_tb=0;
            #10  r_tb=1; s_tb=1;
        
            #10;
        end
endmodule
module latch_sr_tb();


    reg s_tb,r_tb;
    wire q_tb;
    
    latch_sr UUT(.s(s_tb), .r(r_tb), .q(q_tb));
    
    initial 
        begin
            $dumpfile("latch_sr_tb.vcd");
            $dumpvars(0, latch_sr_tb);

                 r_tb=0; s_tb=0; 
            #10  r_tb=0; s_tb=1; 
            #10  r_tb=1; s_tb=0; 
            #10  r_tb=1; s_tb=1;
            #10  r_tb=0; s_tb=0;  
            #10  r_tb=0; s_tb=1; 
            #10  r_tb=1; s_tb=0;
            #10  r_tb=1; s_tb=1;
            #10  r_tb=0; s_tb=0;
            #10  r_tb=0; s_tb=1;
            #10  r_tb=1; s_tb=0;
            #10  r_tb=1; s_tb=1;
        
            #10;
        end
endmodule