data/full_repos/permissive/423958267/lab02/lab02.srcs/sources_1/new/DFlipFlop.v
data/verilator_xmls/14098395-1493-43d5-9d90-5afbe735ae5a.xml
module DFlipFlop(output reg q, input d, input clk, input nreset);
    always @(posedge clk or negedge nreset)
    begin
        if(!nreset) q<=0;
        else q<=d;
    end
endmodule
module DFlipFlop(output reg q, input d, input clk, input nreset);

    always @(posedge clk or negedge nreset)
    begin
        if(!nreset) q<=0;
        else q<=d;
    end
endmodule