data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco/RequestBlock1CH.sv
1: b'%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco/RequestBlock1CH.sv:48: Cannot find include file: parameters.v\n`include "parameters.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco,data/full_repos/permissive/489147019/parameters.v\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco,data/full_repos/permissive/489147019/parameters.v.v\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco,data/full_repos/permissive/489147019/parameters.v.sv\n             parameters.v\n             parameters.v.v\n             parameters.v.sv\n             obj_dir/parameters.v\n             obj_dir/parameters.v.v\n             obj_dir/parameters.v.sv\n%Error: Exiting due to 1 error(s)\n'
module RequestBlock1CH
#(
    parameter ADDR_MEM_WIDTH = 12,
    parameter N_CH0          = 16,
    parameter ID_WIDTH       = N_CH0,
    parameter DATA_WIDTH     = 32,
    parameter BE_WIDTH       = DATA_WIDTH/8
)
(

    input  logic [N_CH0-1:0]                     data_req_CH0_i,
    input  logic [N_CH0-1:0][ADDR_MEM_WIDTH:0]   data_add_CH0_i,
    input  logic [N_CH0-1:0]                     data_wen_CH0_i,
    input  logic [N_CH0-1:0][DATA_WIDTH-1:0]     data_wdata_CH0_i,
    input  logic [N_CH0-1:0][BE_WIDTH-1:0]       data_be_CH0_i,
    input  logic [N_CH0-1:0][ID_WIDTH-1:0]       data_ID_CH0_i,
`ifdef GNT_BASED_FC
    output logic [N_CH0-1:0]                     data_gnt_CH0_o,
`else
    output logic [N_CH0-1:0]                     data_stall_CH0_o,
`endif



    output logic                                 data_req_o,
    output logic                                 data_ts_set_o,
    output logic [ADDR_MEM_WIDTH-1:0]            data_add_o,
    output logic                                 data_wen_o,
    output logic [DATA_WIDTH-1:0]                data_wdata_o,
    output logic [BE_WIDTH-1:0]                  data_be_o,
    output logic [ID_WIDTH-1:0]                  data_ID_o,
`ifdef GNT_BASED_FC
    input  logic                                 data_gnt_i,
`else
    input  logic                                 data_stall_i,
`endif

    input logic [ID_WIDTH-1:0]                   data_r_ID_i,
    input logic                                  data_r_valid_i,
    output logic [N_CH0-1:0]                     data_r_valid_CH0_o,

    input  logic                                 TCDM_arb_policy_i,

    input  logic                                 clk,
    input  logic                                 rst_n
);




    logic [2**$clog2(N_CH0)-1:0]                                data_req_CH0_int;
    logic [2**$clog2(N_CH0)-1:0][ADDR_MEM_WIDTH:0]              data_add_CH0_int;
    logic [2**$clog2(N_CH0)-1:0]                                data_wen_CH0_int;
    logic [2**$clog2(N_CH0)-1:0][DATA_WIDTH-1:0]                data_wdata_CH0_int;
    logic [2**$clog2(N_CH0)-1:0][BE_WIDTH-1:0]                  data_be_CH0_int;
    logic [2**$clog2(N_CH0)-1:0][ID_WIDTH-1:0]                  data_ID_CH0_int;
`ifdef GNT_BASED_FC
    logic [2**$clog2(N_CH0)-1:0]                                data_gnt_CH0_int;
`else
    logic [2**$clog2(N_CH0)-1:0]                                data_stall_CH0_int;
`endif


generate

    if(2**$clog2(N_CH0) != N_CH0)
    begin : _DUMMY_CH0_PORTS_
      
      logic [2**$clog2(N_CH0)-N_CH0 -1 :0]                                data_req_CH0_dummy;
      logic [2**$clog2(N_CH0)-N_CH0 -1 :0][ADDR_MEM_WIDTH:0]              data_add_CH0_dummy;
      logic [2**$clog2(N_CH0)-N_CH0 -1 :0]                                data_wen_CH0_dummy;
      logic [2**$clog2(N_CH0)-N_CH0 -1 :0][DATA_WIDTH-1:0]                data_wdata_CH0_dummy;
      logic [2**$clog2(N_CH0)-N_CH0 -1 :0][BE_WIDTH-1:0]                  data_be_CH0_dummy;
      logic [2**$clog2(N_CH0)-N_CH0 -1 :0][ID_WIDTH-1:0]                  data_ID_CH0_dummy;
  `ifdef GNT_BASED_FC
      logic [2**$clog2(N_CH0)-N_CH0 -1 :0]                                data_gnt_CH0_dummy;
  `else
      logic [2**$clog2(N_CH0)-N_CH0 -1 :0]                                data_stall_CH0_dummy;
  `endif

      assign data_req_CH0_dummy    = '0 ;  
      assign data_add_CH0_dummy    = '0 ;   
      assign data_wen_CH0_dummy    = '0 ;  
      assign data_wdata_CH0_dummy  = '0 ;
      assign data_be_CH0_dummy     = '0 ;   
      assign data_ID_CH0_dummy     = '0 ;

      assign data_req_CH0_int      = {  data_req_CH0_dummy  ,     data_req_CH0_i     };
      assign data_add_CH0_int      = {  data_add_CH0_dummy  ,     data_add_CH0_i     };
      assign data_wen_CH0_int      = {  data_wen_CH0_dummy  ,     data_wen_CH0_i     };
      assign data_wdata_CH0_int    = {  data_wdata_CH0_dummy  ,   data_wdata_CH0_i   };
      assign data_be_CH0_int       = {  data_be_CH0_dummy  ,      data_be_CH0_i      };
      assign data_ID_CH0_int       = {  data_ID_CH0_dummy  ,      data_ID_CH0_i      };        


      for(genvar j=0; j<N_CH0; j++)
      begin : _MERGING_CH0_DUMMY_PORTS_OUT_
`ifdef GNT_BASED_FC           
        assign data_gnt_CH0_o[j]     = data_gnt_CH0_int[j];
`else
        assign data_stall_CH0_o[j]   = data_stall_CH0_int[j];
`endif        
      end


  end
  else
  begin
        assign data_req_CH0_int   = data_req_CH0_i;
        assign data_add_CH0_int   = data_add_CH0_i;
        assign data_wen_CH0_int   = data_wen_CH0_i;
        assign data_wdata_CH0_int = data_wdata_CH0_i;
        assign data_be_CH0_int    = data_be_CH0_i;
        assign data_ID_CH0_int    = data_ID_CH0_i;
    `ifdef GNT_BASED_FC    
        assign data_gnt_CH0_o     = data_gnt_CH0_int;
    `else 
        assign data_stall_CH0_o   = data_stall_CH0_int;
    `endif
  end







    if(N_CH0 != 1)
    begin : POLY_CH0



        logic                                           data_req_MEM;
        logic [ADDR_MEM_WIDTH:0]                        data_add_MEM;
        logic                                           data_wen_MEM;
        logic [DATA_WIDTH-1:0]                          data_wdata_MEM;
        logic [BE_WIDTH-1:0]                            data_be_MEM;
        logic [ID_WIDTH-1:0]                            data_ID_MEM;

    `ifdef GNT_BASED_FC
        logic                                           data_gnt_MEM;      
    `else
        logic                                           data_stall_MEM;      
    `endif

        ArbitrationTree 
        #(
            .ADDR_WIDTH     ( ADDR_MEM_WIDTH+1   ),
            .ID_WIDTH       ( ID_WIDTH           ),
            .N_MASTER       ( 2**$clog2(N_CH0)   ),
            .DATA_WIDTH     ( DATA_WIDTH         ),
            .BE_WIDTH       ( BE_WIDTH           ),
            .MAX_COUNT      ( N_CH0-1            )
        )
        i_ArbitrationTree 
        (
            .clk               ( clk                ),
            .rst_n             ( rst_n              ),
            .TCDM_arb_policy_i ( TCDM_arb_policy_i  ),

            .data_req_i        ( data_req_CH0_int   ),
            .data_add_i        ( data_add_CH0_int   ),
            .data_wen_i        ( data_wen_CH0_int   ),
            .data_wdata_i      ( data_wdata_CH0_int ),
            .data_be_i         ( data_be_CH0_int    ),
            .data_ID_i         ( data_ID_CH0_int    ),
         `ifdef GNT_BASED_FC
            .data_gnt_o        ( data_gnt_CH0_int   ),
         `else
            .data_stall_o      ( data_stall_CH0_int ),
         `endif

            .data_req_o        ( data_req_MEM       ),
            .data_add_o        ( data_add_MEM       ),
            .data_wen_o        ( data_wen_MEM       ),
            .data_wdata_o      ( data_wdata_MEM     ),
            .data_be_o         ( data_be_MEM        ),
            .data_ID_o         ( data_ID_MEM        ),
         `ifdef GNT_BASED_FC
            .data_gnt_i        ( data_gnt_MEM       )
         `else
            .data_stall_i      ( data_stall_MEM     )
         `endif
        );

        TestAndSet 
        #( 
            .ADDR_MEM_WIDTH ( ADDR_MEM_WIDTH+1  ), 
            .ID_WIDTH       ( ID_WIDTH          ),
            .DATA_WIDTH     ( DATA_WIDTH        ),
            .BE_WIDTH       ( BE_WIDTH          )
        ) 
        i_TestAndSet
        (
            .clk            ( clk               ),
            .rst_n          ( rst_n             ),

            .data_req_i     ( data_req_MEM      ),
            .data_add_i     ( data_add_MEM      ),
            .data_wen_i     ( data_wen_MEM      ),
            .data_wdata_i   ( data_wdata_MEM    ),
            .data_be_i      ( data_be_MEM       ),
            .data_ID_i      ( data_ID_MEM       ),
          `ifdef GNT_BASED_FC
            .data_gnt_o     ( data_gnt_MEM      ),
          `else
            .data_stall_o   ( data_stall_MEM    ),
          `endif



            .data_req_o     ( data_req_o        ),
            .data_ts_set_o  ( data_ts_set_o     ),
            .data_add_o     ( data_add_o        ),
            .data_wen_o     ( data_wen_o        ),
            .data_wdata_o   ( data_wdata_o      ),
            .data_be_o      ( data_be_o         ),
            .data_ID_o      ( data_ID_o         ),
          `ifdef GNT_BASED_FC
            .data_gnt_i     ( data_gnt_i        )
          `else
            .data_stall_i   ( data_stall_i      )
          `endif
        );
        
    end 
    else 
    begin : MONO_CH0
        TestAndSet 
        #(  
            .ADDR_MEM_WIDTH ( ADDR_MEM_WIDTH+1  ),
            .ID_WIDTH       ( ID_WIDTH          ),
            .DATA_WIDTH     ( DATA_WIDTH        ),
            .BE_WIDTH       ( BE_WIDTH          )
        ) 
        i_TestAndSet
        (
            .clk            ( clk                ),
            .rst_n          ( rst_n              ),

            .data_req_i     ( data_req_CH0_int   ),
            .data_add_i     ( data_add_CH0_int   ),
            .data_wen_i     ( data_wen_CH0_int   ),
            .data_wdata_i   ( data_wdata_CH0_int ),
            .data_be_i      ( data_be_CH0_int    ),
            .data_ID_i      ( data_ID_CH0_int    ),
        `ifdef GNT_BASED_FC
            .data_gnt_o     ( data_gnt_CH0_int   ),
        `else
            .data_stall_o   ( data_stall_CH0_int ),
        `endif


            .data_req_o     ( data_req_o         ),
            .data_ts_set_o  ( data_ts_set_o      ),
            .data_add_o     ( data_add_o         ),
            .data_wen_o     ( data_wen_o         ),
            .data_wdata_o   ( data_wdata_o       ),
            .data_be_o      ( data_be_o          ),
            .data_ID_o      ( data_ID_o          ),
        `ifdef GNT_BASED_FC
            .data_gnt_i     ( data_gnt_i         )
        `else
              .data_stall_i ( data_stall_i       )
        `endif
        );
    end
  endgenerate


  AddressDecoder_Resp 
  #( 
      .ID_WIDTH(ID_WIDTH), 
      .N_MASTER(N_CH0) 
  )
  i_AddressDecoder_Resp
  (

    .data_r_valid_i(data_r_valid_i),
    .data_ID_i(data_r_ID_i),

    .data_r_valid_o(data_r_valid_CH0_o)
  );





endmodule
module RequestBlock1CH
#(
    parameter ADDR_MEM_WIDTH = 12,
    parameter N_CH0          = 16,
    parameter ID_WIDTH       = N_CH0,
    parameter DATA_WIDTH     = 32,
    parameter BE_WIDTH       = DATA_WIDTH/8
)
(

    input  logic [N_CH0-1:0]                     data_req_CH0_i,
    input  logic [N_CH0-1:0][ADDR_MEM_WIDTH:0]   data_add_CH0_i,
    input  logic [N_CH0-1:0]                     data_wen_CH0_i,
    input  logic [N_CH0-1:0][DATA_WIDTH-1:0]     data_wdata_CH0_i,
    input  logic [N_CH0-1:0][BE_WIDTH-1:0]       data_be_CH0_i,
    input  logic [N_CH0-1:0][ID_WIDTH-1:0]       data_ID_CH0_i,
`ifdef GNT_BASED_FC
    output logic [N_CH0-1:0]                     data_gnt_CH0_o,
`else
    output logic [N_CH0-1:0]                     data_stall_CH0_o,
`endif



    output logic                                 data_req_o,
    output logic                                 data_ts_set_o,
    output logic [ADDR_MEM_WIDTH-1:0]            data_add_o,
    output logic                                 data_wen_o,
    output logic [DATA_WIDTH-1:0]                data_wdata_o,
    output logic [BE_WIDTH-1:0]                  data_be_o,
    output logic [ID_WIDTH-1:0]                  data_ID_o,
`ifdef GNT_BASED_FC
    input  logic                                 data_gnt_i,
`else
    input  logic                                 data_stall_i,
`endif

    input logic [ID_WIDTH-1:0]                   data_r_ID_i,
    input logic                                  data_r_valid_i,
    output logic [N_CH0-1:0]                     data_r_valid_CH0_o,

    input  logic                                 TCDM_arb_policy_i,

    input  logic                                 clk,
    input  logic                                 rst_n
);





    logic [2**$clog2(N_CH0)-1:0]                                data_req_CH0_int;
    logic [2**$clog2(N_CH0)-1:0][ADDR_MEM_WIDTH:0]              data_add_CH0_int;
    logic [2**$clog2(N_CH0)-1:0]                                data_wen_CH0_int;
    logic [2**$clog2(N_CH0)-1:0][DATA_WIDTH-1:0]                data_wdata_CH0_int;
    logic [2**$clog2(N_CH0)-1:0][BE_WIDTH-1:0]                  data_be_CH0_int;
    logic [2**$clog2(N_CH0)-1:0][ID_WIDTH-1:0]                  data_ID_CH0_int;
`ifdef GNT_BASED_FC
    logic [2**$clog2(N_CH0)-1:0]                                data_gnt_CH0_int;
`else
    logic [2**$clog2(N_CH0)-1:0]                                data_stall_CH0_int;
`endif


generate

    if(2**$clog2(N_CH0) != N_CH0)
    begin : _DUMMY_CH0_PORTS_
      
      logic [2**$clog2(N_CH0)-N_CH0 -1 :0]                                data_req_CH0_dummy;
      logic [2**$clog2(N_CH0)-N_CH0 -1 :0][ADDR_MEM_WIDTH:0]              data_add_CH0_dummy;
      logic [2**$clog2(N_CH0)-N_CH0 -1 :0]                                data_wen_CH0_dummy;
      logic [2**$clog2(N_CH0)-N_CH0 -1 :0][DATA_WIDTH-1:0]                data_wdata_CH0_dummy;
      logic [2**$clog2(N_CH0)-N_CH0 -1 :0][BE_WIDTH-1:0]                  data_be_CH0_dummy;
      logic [2**$clog2(N_CH0)-N_CH0 -1 :0][ID_WIDTH-1:0]                  data_ID_CH0_dummy;
  `ifdef GNT_BASED_FC
      logic [2**$clog2(N_CH0)-N_CH0 -1 :0]                                data_gnt_CH0_dummy;
  `else
      logic [2**$clog2(N_CH0)-N_CH0 -1 :0]                                data_stall_CH0_dummy;
  `endif

      assign data_req_CH0_dummy    = '0 ;  
      assign data_add_CH0_dummy    = '0 ;   
      assign data_wen_CH0_dummy    = '0 ;  
      assign data_wdata_CH0_dummy  = '0 ;
      assign data_be_CH0_dummy     = '0 ;   
      assign data_ID_CH0_dummy     = '0 ;

      assign data_req_CH0_int      = {  data_req_CH0_dummy  ,     data_req_CH0_i     };
      assign data_add_CH0_int      = {  data_add_CH0_dummy  ,     data_add_CH0_i     };
      assign data_wen_CH0_int      = {  data_wen_CH0_dummy  ,     data_wen_CH0_i     };
      assign data_wdata_CH0_int    = {  data_wdata_CH0_dummy  ,   data_wdata_CH0_i   };
      assign data_be_CH0_int       = {  data_be_CH0_dummy  ,      data_be_CH0_i      };
      assign data_ID_CH0_int       = {  data_ID_CH0_dummy  ,      data_ID_CH0_i      };        


      for(genvar j=0; j<N_CH0; j++)
      begin : _MERGING_CH0_DUMMY_PORTS_OUT_
`ifdef GNT_BASED_FC           
        assign data_gnt_CH0_o[j]     = data_gnt_CH0_int[j];
`else
        assign data_stall_CH0_o[j]   = data_stall_CH0_int[j];
`endif        
      end


  end
  else
  begin
        assign data_req_CH0_int   = data_req_CH0_i;
        assign data_add_CH0_int   = data_add_CH0_i;
        assign data_wen_CH0_int   = data_wen_CH0_i;
        assign data_wdata_CH0_int = data_wdata_CH0_i;
        assign data_be_CH0_int    = data_be_CH0_i;
        assign data_ID_CH0_int    = data_ID_CH0_i;
    `ifdef GNT_BASED_FC    
        assign data_gnt_CH0_o     = data_gnt_CH0_int;
    `else 
        assign data_stall_CH0_o   = data_stall_CH0_int;
    `endif
  end







    if(N_CH0 != 1)
    begin : POLY_CH0



        logic                                           data_req_MEM;
        logic [ADDR_MEM_WIDTH:0]                        data_add_MEM;
        logic                                           data_wen_MEM;
        logic [DATA_WIDTH-1:0]                          data_wdata_MEM;
        logic [BE_WIDTH-1:0]                            data_be_MEM;
        logic [ID_WIDTH-1:0]                            data_ID_MEM;

    `ifdef GNT_BASED_FC
        logic                                           data_gnt_MEM;      
    `else
        logic                                           data_stall_MEM;      
    `endif

        ArbitrationTree 
        #(
            .ADDR_WIDTH     ( ADDR_MEM_WIDTH+1   ),
            .ID_WIDTH       ( ID_WIDTH           ),
            .N_MASTER       ( 2**$clog2(N_CH0)   ),
            .DATA_WIDTH     ( DATA_WIDTH         ),
            .BE_WIDTH       ( BE_WIDTH           ),
            .MAX_COUNT      ( N_CH0-1            )
        )
        i_ArbitrationTree 
        (
            .clk               ( clk                ),
            .rst_n             ( rst_n              ),
            .TCDM_arb_policy_i ( TCDM_arb_policy_i  ),

            .data_req_i        ( data_req_CH0_int   ),
            .data_add_i        ( data_add_CH0_int   ),
            .data_wen_i        ( data_wen_CH0_int   ),
            .data_wdata_i      ( data_wdata_CH0_int ),
            .data_be_i         ( data_be_CH0_int    ),
            .data_ID_i         ( data_ID_CH0_int    ),
         `ifdef GNT_BASED_FC
            .data_gnt_o        ( data_gnt_CH0_int   ),
         `else
            .data_stall_o      ( data_stall_CH0_int ),
         `endif

            .data_req_o        ( data_req_MEM       ),
            .data_add_o        ( data_add_MEM       ),
            .data_wen_o        ( data_wen_MEM       ),
            .data_wdata_o      ( data_wdata_MEM     ),
            .data_be_o         ( data_be_MEM        ),
            .data_ID_o         ( data_ID_MEM        ),
         `ifdef GNT_BASED_FC
            .data_gnt_i        ( data_gnt_MEM       )
         `else
            .data_stall_i      ( data_stall_MEM     )
         `endif
        );

        TestAndSet 
        #( 
            .ADDR_MEM_WIDTH ( ADDR_MEM_WIDTH+1  ), 
            .ID_WIDTH       ( ID_WIDTH          ),
            .DATA_WIDTH     ( DATA_WIDTH        ),
            .BE_WIDTH       ( BE_WIDTH          )
        ) 
        i_TestAndSet
        (
            .clk            ( clk               ),
            .rst_n          ( rst_n             ),

            .data_req_i     ( data_req_MEM      ),
            .data_add_i     ( data_add_MEM      ),
            .data_wen_i     ( data_wen_MEM      ),
            .data_wdata_i   ( data_wdata_MEM    ),
            .data_be_i      ( data_be_MEM       ),
            .data_ID_i      ( data_ID_MEM       ),
          `ifdef GNT_BASED_FC
            .data_gnt_o     ( data_gnt_MEM      ),
          `else
            .data_stall_o   ( data_stall_MEM    ),
          `endif



            .data_req_o     ( data_req_o        ),
            .data_ts_set_o  ( data_ts_set_o     ),
            .data_add_o     ( data_add_o        ),
            .data_wen_o     ( data_wen_o        ),
            .data_wdata_o   ( data_wdata_o      ),
            .data_be_o      ( data_be_o         ),
            .data_ID_o      ( data_ID_o         ),
          `ifdef GNT_BASED_FC
            .data_gnt_i     ( data_gnt_i        )
          `else
            .data_stall_i   ( data_stall_i      )
          `endif
        );
        
    end 
    else 
    begin : MONO_CH0
        TestAndSet 
        #(  
            .ADDR_MEM_WIDTH ( ADDR_MEM_WIDTH+1  ),
            .ID_WIDTH       ( ID_WIDTH          ),
            .DATA_WIDTH     ( DATA_WIDTH        ),
            .BE_WIDTH       ( BE_WIDTH          )
        ) 
        i_TestAndSet
        (
            .clk            ( clk                ),
            .rst_n          ( rst_n              ),

            .data_req_i     ( data_req_CH0_int   ),
            .data_add_i     ( data_add_CH0_int   ),
            .data_wen_i     ( data_wen_CH0_int   ),
            .data_wdata_i   ( data_wdata_CH0_int ),
            .data_be_i      ( data_be_CH0_int    ),
            .data_ID_i      ( data_ID_CH0_int    ),
        `ifdef GNT_BASED_FC
            .data_gnt_o     ( data_gnt_CH0_int   ),
        `else
            .data_stall_o   ( data_stall_CH0_int ),
        `endif


            .data_req_o     ( data_req_o         ),
            .data_ts_set_o  ( data_ts_set_o      ),
            .data_add_o     ( data_add_o         ),
            .data_wen_o     ( data_wen_o         ),
            .data_wdata_o   ( data_wdata_o       ),
            .data_be_o      ( data_be_o          ),
            .data_ID_o      ( data_ID_o          ),
        `ifdef GNT_BASED_FC
            .data_gnt_i     ( data_gnt_i         )
        `else
              .data_stall_i ( data_stall_i       )
        `endif
        );
    end
  endgenerate


  AddressDecoder_Resp 
  #( 
      .ID_WIDTH(ID_WIDTH), 
      .N_MASTER(N_CH0) 
  )
  i_AddressDecoder_Resp
  (

    .data_r_valid_i(data_r_valid_i),
    .data_ID_i(data_r_ID_i),

    .data_r_valid_o(data_r_valid_CH0_o)
  );





endmodule