data/full_repos/permissive/465580112/GRU/mac.v
1: b'%Warning-WIDTH: data/full_repos/permissive/465580112/GRU/mac.v:43: Operator ADD expects 6 bits on the LHS, but LHS\'s REPLICATE generates 4 bits.\n                                                                 : ... In instance mac2.mul.m13.m12.m8\n q[7:2]=({2\'b00,q0[3:2]}+q1[3:0])+({2\'b00,q2[3:0]}+{q3[3:0],2\'b00});\n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/465580112/GRU/mac.v:43: Operator ADD expects 6 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                 : ... In instance mac2.mul.m13.m12.m8\n q[7:2]=({2\'b00,q0[3:2]}+q1[3:0])+({2\'b00,q2[3:0]}+{q3[3:0],2\'b00});\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/465580112/GRU/mac.v:72: Operator ADD expects 12 bits on the LHS, but LHS\'s REPLICATE generates 8 bits.\n                                                                 : ... In instance mac2.mul.m13.m12\nq[15:4]=({4\'b0000,q0[7:4]}+q1[7:0])+({4\'b0000,q2[7:0]}+{q3[7:0],4\'b0000});\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/465580112/GRU/mac.v:72: Operator ADD expects 12 bits on the RHS, but RHS\'s SEL generates 8 bits.\n                                                                 : ... In instance mac2.mul.m13.m12\nq[15:4]=({4\'b0000,q0[7:4]}+q1[7:0])+({4\'b0000,q2[7:0]}+{q3[7:0],4\'b0000});\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/465580112/GRU/mac.v:101: Operator ADD expects 24 bits on the LHS, but LHS\'s REPLICATE generates 16 bits.\n                                                                  : ... In instance mac2.mul.m13\n q[31:8]=({8\'b00000000,q0[15:8]}+q1[15:0])+({8\'b00000000,q2[15:0]}+{q3[15:0],8\'b00000000});\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/465580112/GRU/mac.v:101: Operator ADD expects 24 bits on the RHS, but RHS\'s SEL generates 16 bits.\n                                                                  : ... In instance mac2.mul.m13\n q[31:8]=({8\'b00000000,q0[15:8]}+q1[15:0])+({8\'b00000000,q2[15:0]}+{q3[15:0],8\'b00000000});\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/465580112/GRU/mac.v:118: Input port connection \'a\' expects 16 bits on the pin connection, but pin connection\'s VARREF \'p0\' generates 15 bits.\n                                                                  : ... In instance mac2.mul\n  mul16 m13(cs,p0,p1,q[31:0]);\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/465580112/GRU/mac.v:118: Input port connection \'b\' expects 16 bits on the pin connection, but pin connection\'s VARREF \'p1\' generates 15 bits.\n                                                                  : ... In instance mac2.mul\n  mul16 m13(cs,p0,p1,q[31:0]);\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/465580112/GRU/mac.v:126: Operator ASSIGN expects 28 bits on the Assign RHS, but Assign RHS\'s SEL generates 32 bits.\n                                                                  : ... In instance mac2.mul\nresult[27:0] = q[31:0];\n             ^\n%Error: Exiting due to 9 warning(s)\n'
module mac2(a,b,clk,out,cs_mac,rdy,sync);
input[15:0]a,b;
input clk;
output reg rdy;
output reg sync;
input cs_mac;
output reg [15:0]out;
wire [15:0] fprod, fadd;
reg [15:0] data_a, data_b,fprod1;
reg cs_mult,cs_add,done;
reg [1:0] size;
reg [1:0] i;
reg [2:0] state;

initial state = 0;
initial i = 0;
initial sync=0;

multi mul(cs_mult,data_a,data_b,fprod);
addq add(cs_add,fprod1,out,fadd);

always@(posedge clk)
begin
case(state)
0:begin
	if(cs_mac)
	state=1;
	else
	state=0;
  end
1:state=2;
2:state=3;
3:state=4;
4:state=5;
5:state=6;
6:begin
	if(i==size)
	state=7;
	else
	state=2;
end
7:begin
if(rdy)
state=0;
else
state=7;
end

endcase
end

always@(state)
begin
case(state)
0:rdy=1;
1:begin
	rdy = 1'b0;
 	data_a = 16'b0;
        data_b = 16'b0;
        fprod1 = 16'b0;
        out = 16'b0;
	size = 2'b11;
  end
2:begin
	sync =1'b1;
	data_a = a;
        data_b  = b;	
end
3:begin
  cs_mult = 1'b1;
  sync = 1'b0;
  end
4:fprod1 = fprod;


5:cs_add = 1'b1;
6:  begin     
	out = fadd;
	cs_add=1'b0;
	i = i+1;

  end

7:begin
	done = 1'b1;
	rdy = 1'b1;
	sync=1'b0;
  end
  default:begin 
	state = 0;
        end
endcase
end
endmodule
module mac2(a,b,clk,out,cs_mac,rdy,sync);

input[15:0]a,b;
input clk;
output reg rdy;
output reg sync;
input cs_mac;
output reg [15:0]out;
wire [15:0] fprod, fadd;
reg [15:0] data_a, data_b,fprod1;
reg cs_mult,cs_add,done;
reg [1:0] size;
reg [1:0] i;
reg [2:0] state;

initial state = 0;
initial i = 0;
initial sync=0;

multi mul(cs_mult,data_a,data_b,fprod);
addq add(cs_add,fprod1,out,fadd);

always@(posedge clk)
begin
case(state)
0:begin
	if(cs_mac)
	state=1;
	else
	state=0;
  end
1:state=2;
2:state=3;
3:state=4;
4:state=5;
5:state=6;
6:begin
	if(i==size)
	state=7;
	else
	state=2;
end
7:begin
if(rdy)
state=0;
else
state=7;
end

endcase
end

always@(state)
begin
case(state)
0:rdy=1;
1:begin
	rdy = 1'b0;
 	data_a = 16'b0;
        data_b = 16'b0;
        fprod1 = 16'b0;
        out = 16'b0;
	size = 2'b11;
  end
2:begin
	sync =1'b1;
	data_a = a;
        data_b  = b;	
end
3:begin
  cs_mult = 1'b1;
  sync = 1'b0;
  end
4:fprod1 = fprod;


5:cs_add = 1'b1;
6:  begin     
	out = fadd;
	cs_add=1'b0;
	i = i+1;

  end

7:begin
	done = 1'b1;
	rdy = 1'b1;
	sync=1'b0;
  end
  default:begin 
	state = 0;
        end
endcase
end
endmodule