data/full_repos/permissive/441359809/src/yosys/tests/simple/memory.v
1: b"%Error: data/full_repos/permissive/441359809/src/yosys/tests/simple/memory.v:39: syntax error, unexpected ',', expecting IDENTIFIER or do or final\nmodule memtest02(clk, setA, setB, addr, bit, y1, y2, y3, y4);\n                                           ^\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/simple/memory.v:45: syntax error, unexpected output\noutput y3, y4;\n^~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/simple/memory.v:52: syntax error, unexpected always\nalways @(posedge clk) begin\n^~~~~~\n%Error: Exiting due to 3 error(s)\n"
module memtest03(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data);

input clk, wr_enable;
input [3:0] wr_addr, wr_data, rd_addr;
output reg [3:0] rd_data;

reg [3:0] memory [0:15];

always @(posedge clk) begin
	if (wr_enable)
		memory[wr_addr] <= wr_data;
	rd_data <= memory[rd_addr];
end

endmodule
module memtest03(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data);


input clk, wr_enable;
input [3:0] wr_addr, wr_data, rd_addr;
output reg [3:0] rd_data;

reg [3:0] memory [0:15];

always @(posedge clk) begin
	if (wr_enable)
		memory[wr_addr] <= wr_data;
	rd_data <= memory[rd_addr];
end

endmodule