data/full_repos/permissive/462608388/RTL/or1200_rf.v
1: b'%Error: data/full_repos/permissive/462608388/RTL/or1200_rf.v:51: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/462608388/RTL,data/full_repos/permissive/462608388/timescale.v\n             data/full_repos/permissive/462608388/RTL,data/full_repos/permissive/462608388/timescale.v.v\n             data/full_repos/permissive/462608388/RTL,data/full_repos/permissive/462608388/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/462608388/RTL/or1200_rf.v:53: Cannot find include file: or1200_defines.v\n`include "or1200_defines.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/462608388/RTL/or1200_rf.v:69: Define or directive not defined: \'`OR1200_OPERAND_WIDTH\'\nparameter dw = `OR1200_OPERAND_WIDTH;\n               ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/462608388/RTL/or1200_rf.v:69: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter dw = `OR1200_OPERAND_WIDTH;\n                                    ^\n%Error: data/full_repos/permissive/462608388/RTL/or1200_rf.v:70: Define or directive not defined: \'`OR1200_REGFILE_ADDR_WIDTH\'\nparameter aw = `OR1200_REGFILE_ADDR_WIDTH;\n               ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/462608388/RTL/or1200_rf.v:70: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nparameter aw = `OR1200_REGFILE_ADDR_WIDTH;\n                                         ^\n%Error: data/full_repos/permissive/462608388/RTL/or1200_rf.v:158: Define or directive not defined: \'`OR1200_SPR_RF\'\nassign spr_valid = spr_cs & (spr_addr[10:5] == `OR1200_SPR_RF);\n                                               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/462608388/RTL/or1200_rf.v:158: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign spr_valid = spr_cs & (spr_addr[10:5] == `OR1200_SPR_RF);\n                                                             ^\n%Error: data/full_repos/permissive/462608388/RTL/or1200_rf.v:194: Define or directive not defined: \'`OR1200_RST_EVENT\'\nalways @(`OR1200_RST_EVENT rst or posedge clk)\n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/462608388/RTL/or1200_rf.v:195: Define or directive not defined: \'`OR1200_RST_VALUE\'\n if (rst == `OR1200_RST_VALUE)\n            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/462608388/RTL/or1200_rf.v:195: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (rst == `OR1200_RST_VALUE)\n                             ^\n%Error: Exiting due to 11 error(s)\n'
module or1200_rf(

	clk, rst,


	cy_we_i, cy_we_o, supv, wb_freeze, addrw, dataw, we, flushpipe,


	id_freeze, addra, addrb, dataa, datab, rda, rdb,


	spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o, du_read
);

parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;








input				clk;
input				rst;




input				cy_we_i;
output				cy_we_o;
input				supv;
input				wb_freeze;
input	[aw-1:0]		addrw;
input	[dw-1:0]		dataw;
input				we;
input				flushpipe;




input				id_freeze;
input	[aw-1:0]		addra;
input	[aw-1:0]		addrb;
output	[dw-1:0]		dataa;
output	[dw-1:0]		datab;
input				rda;
input				rdb;




input				spr_cs;
input				spr_write;
input	[31:0]			spr_addr;
input	[31:0]			spr_dat_i;
output	[31:0]			spr_dat_o;
input    			du_read;
   



wire	[dw-1:0]		from_rfa;
wire	[dw-1:0]		from_rfb;
wire	[aw-1:0]		rf_addra;
wire	[aw-1:0]		rf_addrw;
wire	[dw-1:0]		rf_dataw;
wire				rf_we;
wire				spr_valid;
wire				rf_ena;
wire				rf_enb;
reg				rf_we_allow;








   

   reg 				spr_du_cs;
   wire 			spr_cs_fe;

   reg	[aw-1:0]		addra_last;


   always @(posedge clk)
     if (rf_ena & !(spr_cs_fe | (du_read & spr_cs)))
       addra_last <= addra;

   always @(posedge clk)
     spr_du_cs <= spr_cs & du_read;

   assign spr_cs_fe = spr_du_cs & !(spr_cs & du_read);

   




assign spr_valid = spr_cs & (spr_addr[10:5] == `OR1200_SPR_RF);




assign spr_dat_o = from_rfa;




assign dataa = from_rfa;




assign datab = from_rfb;




assign rf_addra = (spr_valid & !spr_write) ? spr_addr[4:0] : 
		  spr_cs_fe ? addra_last : addra;




assign rf_addrw = (spr_valid & spr_write) ? spr_addr[4:0] : addrw;




assign rf_dataw = (spr_valid & spr_write) ? spr_dat_i : dataw;




always @(`OR1200_RST_EVENT rst or posedge clk)
	if (rst == `OR1200_RST_VALUE)
		rf_we_allow <=  1'b1;
	else if (~wb_freeze)
		rf_we_allow <=  ~flushpipe;

assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow;

assign cy_we_o = cy_we_i && ~wb_freeze && rf_we_allow;
   




assign rf_ena = (rda & ~id_freeze) | (spr_valid & !spr_write) | spr_cs_fe;





assign rf_enb = rdb & ~id_freeze;

`ifdef OR1200_RFRAM_TWOPORT




or1200_tpram_32x32 rf_a(

	.clk_a(clk),
	.rst_a(rst),
	.ce_a(rf_ena),
	.we_a(1'b0),
	.oe_a(1'b1),
	.addr_a(rf_addra),
	.di_a(32'h0000_0000),
	.do_a(from_rfa),


	.clk_b(clk),
	.rst_b(rst),
	.ce_b(rf_we),
	.we_b(rf_we),
	.oe_b(1'b0),
	.addr_b(rf_addrw),
	.di_b(rf_dataw),
	.do_b()
);




or1200_tpram_32x32 rf_b(

	.clk_a(clk),
	.rst_a(rst),
	.ce_a(rf_enb),
	.we_a(1'b0),
	.oe_a(1'b1),
	.addr_a(addrb),
	.di_a(32'h0000_0000),
	.do_a(from_rfb),


	.clk_b(clk),
	.rst_b(rst),
	.ce_b(rf_we),
	.we_b(rf_we),
	.oe_b(1'b0),
	.addr_b(rf_addrw),
	.di_b(rf_dataw),
	.do_b()
);

`else

`ifdef OR1200_RFRAM_DUALPORT




   or1200_dpram #
     (
      .aw(5),
      .dw(32)
      )
   rf_a
     (

      .clk_a(clk),
      .ce_a(rf_ena),
      .addr_a(rf_addra),
      .do_a(from_rfa),
      

      .clk_b(clk),
      .ce_b(rf_we),
      .we_b(rf_we),
      .addr_b(rf_addrw),
      .di_b(rf_dataw)
      );




   or1200_dpram #
     (
      .aw(5),
      .dw(32)
      )
   rf_b
     (

      .clk_a(clk),
      .ce_a(rf_enb),
      .addr_a(addrb),
      .do_a(from_rfb),
      

      .clk_b(clk),
      .ce_b(rf_we),
      .we_b(rf_we),
      .addr_b(rf_addrw),
      .di_b(rf_dataw)
      );
   
`else

`ifdef OR1200_RFRAM_GENERIC




or1200_rfram_generic rf_a(

	.clk(clk),
	.rst(rst),


	.ce_a(rf_ena),
	.addr_a(rf_addra),
	.do_a(from_rfa),


	.ce_b(rf_enb),
	.addr_b(addrb),
	.do_b(from_rfb),


	.ce_w(rf_we),
	.we_w(rf_we),
	.addr_w(rf_addrw),
	.di_w(rf_dataw)
);

`else




initial begin
	$display("Define RFRAM type.");
	$finish;
end

`endif
`endif
`endif

endmodule
module or1200_rf(

	clk, rst,


	cy_we_i, cy_we_o, supv, wb_freeze, addrw, dataw, we, flushpipe,


	id_freeze, addra, addrb, dataa, datab, rda, rdb,


	spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o, du_read
);


parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;








input				clk;
input				rst;




input				cy_we_i;
output				cy_we_o;
input				supv;
input				wb_freeze;
input	[aw-1:0]		addrw;
input	[dw-1:0]		dataw;
input				we;
input				flushpipe;




input				id_freeze;
input	[aw-1:0]		addra;
input	[aw-1:0]		addrb;
output	[dw-1:0]		dataa;
output	[dw-1:0]		datab;
input				rda;
input				rdb;




input				spr_cs;
input				spr_write;
input	[31:0]			spr_addr;
input	[31:0]			spr_dat_i;
output	[31:0]			spr_dat_o;
input    			du_read;
   



wire	[dw-1:0]		from_rfa;
wire	[dw-1:0]		from_rfb;
wire	[aw-1:0]		rf_addra;
wire	[aw-1:0]		rf_addrw;
wire	[dw-1:0]		rf_dataw;
wire				rf_we;
wire				spr_valid;
wire				rf_ena;
wire				rf_enb;
reg				rf_we_allow;








   

   reg 				spr_du_cs;
   wire 			spr_cs_fe;

   reg	[aw-1:0]		addra_last;


   always @(posedge clk)
     if (rf_ena & !(spr_cs_fe | (du_read & spr_cs)))
       addra_last <= addra;

   always @(posedge clk)
     spr_du_cs <= spr_cs & du_read;

   assign spr_cs_fe = spr_du_cs & !(spr_cs & du_read);

   




assign spr_valid = spr_cs & (spr_addr[10:5] == `OR1200_SPR_RF);




assign spr_dat_o = from_rfa;




assign dataa = from_rfa;




assign datab = from_rfb;




assign rf_addra = (spr_valid & !spr_write) ? spr_addr[4:0] : 
		  spr_cs_fe ? addra_last : addra;




assign rf_addrw = (spr_valid & spr_write) ? spr_addr[4:0] : addrw;




assign rf_dataw = (spr_valid & spr_write) ? spr_dat_i : dataw;




always @(`OR1200_RST_EVENT rst or posedge clk)
	if (rst == `OR1200_RST_VALUE)
		rf_we_allow <=  1'b1;
	else if (~wb_freeze)
		rf_we_allow <=  ~flushpipe;

assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow;

assign cy_we_o = cy_we_i && ~wb_freeze && rf_we_allow;
   




assign rf_ena = (rda & ~id_freeze) | (spr_valid & !spr_write) | spr_cs_fe;





assign rf_enb = rdb & ~id_freeze;

`ifdef OR1200_RFRAM_TWOPORT




or1200_tpram_32x32 rf_a(

	.clk_a(clk),
	.rst_a(rst),
	.ce_a(rf_ena),
	.we_a(1'b0),
	.oe_a(1'b1),
	.addr_a(rf_addra),
	.di_a(32'h0000_0000),
	.do_a(from_rfa),


	.clk_b(clk),
	.rst_b(rst),
	.ce_b(rf_we),
	.we_b(rf_we),
	.oe_b(1'b0),
	.addr_b(rf_addrw),
	.di_b(rf_dataw),
	.do_b()
);




or1200_tpram_32x32 rf_b(

	.clk_a(clk),
	.rst_a(rst),
	.ce_a(rf_enb),
	.we_a(1'b0),
	.oe_a(1'b1),
	.addr_a(addrb),
	.di_a(32'h0000_0000),
	.do_a(from_rfb),


	.clk_b(clk),
	.rst_b(rst),
	.ce_b(rf_we),
	.we_b(rf_we),
	.oe_b(1'b0),
	.addr_b(rf_addrw),
	.di_b(rf_dataw),
	.do_b()
);

`else

`ifdef OR1200_RFRAM_DUALPORT




   or1200_dpram #
     (
      .aw(5),
      .dw(32)
      )
   rf_a
     (

      .clk_a(clk),
      .ce_a(rf_ena),
      .addr_a(rf_addra),
      .do_a(from_rfa),
      

      .clk_b(clk),
      .ce_b(rf_we),
      .we_b(rf_we),
      .addr_b(rf_addrw),
      .di_b(rf_dataw)
      );




   or1200_dpram #
     (
      .aw(5),
      .dw(32)
      )
   rf_b
     (

      .clk_a(clk),
      .ce_a(rf_enb),
      .addr_a(addrb),
      .do_a(from_rfb),
      

      .clk_b(clk),
      .ce_b(rf_we),
      .we_b(rf_we),
      .addr_b(rf_addrw),
      .di_b(rf_dataw)
      );
   
`else

`ifdef OR1200_RFRAM_GENERIC




or1200_rfram_generic rf_a(

	.clk(clk),
	.rst(rst),


	.ce_a(rf_ena),
	.addr_a(rf_addra),
	.do_a(from_rfa),


	.ce_b(rf_enb),
	.addr_b(addrb),
	.do_b(from_rfb),


	.ce_w(rf_we),
	.we_w(rf_we),
	.addr_w(rf_addrw),
	.di_w(rf_dataw)
);

`else




initial begin
	$display("Define RFRAM type.");
	$finish;
end

`endif
`endif
`endif

endmodule