data/full_repos/permissive/429641629/sources_1/new/ss1.v
1: b'%Warning-WIDTH: data/full_repos/permissive/429641629/sources_1/new/ss1.v:34: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                           : ... In instance Transform_Amp\n        thousand = 4\'d0;\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/429641629/sources_1/new/ss1.v:41: Operator GTE expects 4 bits on the LHS, but LHS\'s VARREF \'thousand\' generates 3 bits.\n                                                                           : ... In instance Transform_Amp\n            if(thousand >= 4\'d5)\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/429641629/sources_1/new/ss1.v:44: Operator ADD expects 4 bits on the RHS, but RHS\'s CONST \'2\'h3\' generates 2 bits.\n                                                                           : ... In instance Transform_Amp\n                hundred = hundred + 2\'d3;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/429641629/sources_1/new/ss1.v:46: Operator ADD expects 4 bits on the RHS, but RHS\'s CONST \'2\'h3\' generates 2 bits.\n                                                                           : ... In instance Transform_Amp\n                ten = ten + 2\'d3;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/429641629/sources_1/new/ss1.v:48: Operator ADD expects 4 bits on the RHS, but RHS\'s CONST \'2\'h3\' generates 2 bits.\n                                                                           : ... In instance Transform_Amp\n                one = one + 2\'d3;\n                          ^\n%Error: Exiting due to 5 warning(s)\n'
module Transform_Amp(
    input [11:0] data_receive,
    output reg [3:0] one,
    output reg [3:0] ten,
    output reg [3:0] hundred,
    output reg [2:0] thousand
    );
    
    integer i;
    always @ (data_receive)
    begin
        thousand = 4'd0;
        hundred = 4'd0;
        ten = 4'd0;
        one = 4'd0;
        
        for(i = 11; i >= 0; i = i - 1)
        begin
            if(thousand >= 4'd5)
                thousand = thousand + 2'd3;
            if(hundred >= 4'd5)
                hundred = hundred + 2'd3;
            if(ten >= 4'd5)
                ten = ten + 2'd3;
            if(one >= 4'd5)
                one = one + 2'd3;
            
            thousand = thousand << 1'b1;
            thousand[0] = hundred[3];
            hundred = hundred << 1'b1;
            hundred[0] = ten[3];
            ten = ten << 1'b1;
            ten[0] = one[3];
            one = one << 1'b1;
            one[0] = data_receive[i];
        end
    end
endmodule
module Transform_Amp(
    input [11:0] data_receive,
    output reg [3:0] one,
    output reg [3:0] ten,
    output reg [3:0] hundred,
    output reg [2:0] thousand
    );

    
    integer i;
    always @ (data_receive)
    begin
        thousand = 4'd0;
        hundred = 4'd0;
        ten = 4'd0;
        one = 4'd0;
        
        for(i = 11; i >= 0; i = i - 1)
        begin
            if(thousand >= 4'd5)
                thousand = thousand + 2'd3;
            if(hundred >= 4'd5)
                hundred = hundred + 2'd3;
            if(ten >= 4'd5)
                ten = ten + 2'd3;
            if(one >= 4'd5)
                one = one + 2'd3;
            
            thousand = thousand << 1'b1;
            thousand[0] = hundred[3];
            hundred = hundred << 1'b1;
            hundred[0] = ten[3];
            ten = ten << 1'b1;
            ten[0] = one[3];
            one = one << 1'b1;
            one[0] = data_receive[i];
        end
    end
endmodule