data/full_repos/permissive/520428138/verilog/rtl/user_module_341628725785264722.v
data/verilator_xmls/b1d0eaad-6e68-4f61-9830-6af8b630f206.xml
module div4_341628725785264722 ( clk ,rst, out_clk );
    output out_clk;
    input clk ;
    input rst;

    reg [1:0] data;
    assign out_clk = data[1];

    always @(posedge clk)
    begin
    if (rst)
         data <= 2'b0;
    else
         data <= data+1;	
    end
endmodule
module div4_341628725785264722 ( clk ,rst, out_clk );

    output out_clk;
    input clk ;
    input rst;

    reg [1:0] data;
    assign out_clk = data[1];

    always @(posedge clk)
    begin
    if (rst)
         data <= 2'b0;
    else
         data <= data+1;	
    end
endmodule