data/full_repos/permissive/528252229/mem_wb.v
1: b'%Error: data/full_repos/permissive/528252229/mem_wb.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/528252229,data/full_repos/permissive/528252229/defines.v\n             data/full_repos/permissive/528252229,data/full_repos/permissive/528252229/defines.v.v\n             data/full_repos/permissive/528252229,data/full_repos/permissive/528252229/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/528252229/mem_wb.v:9: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus]        mem_wd,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem_wb.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`RegAddrBus]        mem_wd,\n                       ^\n%Error: data/full_repos/permissive/528252229/mem_wb.v:10: Define or directive not defined: \'`WriteBus\'\n input wire[`WriteBus]           mem_wreg,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem_wb.v:11: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus]    mem_wdata,\n            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/mem_wb.v:12: Define or directive not defined: \'`InstAddrBus\'\n input wire[`InstAddrBus]  mem_pc,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem_wb.v:13: Define or directive not defined: \'`AluOpBus\'\n input wire[`AluOpBus]   mem_aluop,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem_wb.v:14: Define or directive not defined: \'`StopBus\'\n input wire[`StopBus]            stall,\n            ^~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem_wb.v:17: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus]       wb_wd,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem_wb.v:18: Define or directive not defined: \'`WriteBus\'\n output reg[`WriteBus]           wb_wreg,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem_wb.v:19: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus]    wb_wdata,\n            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/mem_wb.v:20: Define or directive not defined: \'`InstAddrBus\'\n output reg[`InstAddrBus]  wb_pc,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem_wb.v:21: Define or directive not defined: \'`AluOpBus\'\n output reg[`AluOpBus]   wb_aluop    \n            ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem_wb.v:28: Define or directive not defined: \'`RstDisable\'\n        if(rst == `RstDisable) begin\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem_wb.v:29: Define or directive not defined: \'`ZeroRegAddr\'\n            wb_wd       <= `ZeroRegAddr;\n                           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem_wb.v:30: Define or directive not defined: \'`WriteDisable\'\n            wb_wreg     <= `WriteDisable;\n                           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem_wb.v:31: Define or directive not defined: \'`ZeroWord\'\n            wb_wdata    <= `ZeroWord;\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem_wb.v:32: Define or directive not defined: \'`InitialPc\'\n            wb_pc       <= `InitialPc;\n                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem_wb.v:33: Define or directive not defined: \'`ALU_OP_NOP\'\n            wb_aluop    <= `ALU_OP_NOP;\n                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem_wb.v:35: Define or directive not defined: \'`Stop\'\n        else if(stall[4] == `Stop && stall[5] == `NoStop) begin\n                            ^~~~~\n%Error: data/full_repos/permissive/528252229/mem_wb.v:35: Define or directive not defined: \'`NoStop\'\n        else if(stall[4] == `Stop && stall[5] == `NoStop) begin\n                                                 ^~~~~~~\n%Error: data/full_repos/permissive/528252229/mem_wb.v:36: Define or directive not defined: \'`ZeroRegAddr\'\n            wb_wd       <= `ZeroRegAddr;\n                           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem_wb.v:37: Define or directive not defined: \'`WriteDisable\'\n            wb_wreg     <= `WriteDisable;\n                           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem_wb.v:38: Define or directive not defined: \'`ZeroWord\'\n            wb_wdata    <= `ZeroWord;\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem_wb.v:39: Define or directive not defined: \'`InitialPc\'\n            wb_pc       <= `InitialPc;\n                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem_wb.v:40: Define or directive not defined: \'`ALU_OP_NOP\'\n            wb_aluop    <= `ALU_OP_NOP;\n                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/mem_wb.v:42: Define or directive not defined: \'`NoStop\'\n        else if(stall[4] == `NoStop) begin\n                            ^~~~~~~\n%Error: Exiting due to 27 error(s)\n'
module mem_wb(

	input wire						clk,
	input wire						rst,
	
	
	input wire[`RegAddrBus]       	mem_wd,
	input wire[`WriteBus]           mem_wreg,
	input wire[`RegBus]				mem_wdata,
	input wire[`InstAddrBus]		mem_pc,
	input wire[`AluOpBus]			mem_aluop,
	input wire[`StopBus]            stall,


	output reg[`RegAddrBus]      	wb_wd,
	output reg[`WriteBus]           wb_wreg,
	output reg[`RegBus]				wb_wdata,
	output reg[`InstAddrBus]		wb_pc,
	output reg[`AluOpBus]			wb_aluop    
	
);
    


    always @(posedge clk) begin
        if(rst == `RstDisable) begin
            wb_wd       <= `ZeroRegAddr;
            wb_wreg     <= `WriteDisable;
            wb_wdata    <= `ZeroWord;
            wb_pc       <= `InitialPc;
            wb_aluop    <= `ALU_OP_NOP;
        end 
        else if(stall[4] == `Stop && stall[5] == `NoStop) begin
            wb_wd       <= `ZeroRegAddr;
            wb_wreg     <= `WriteDisable;
            wb_wdata    <= `ZeroWord;
            wb_pc       <= `InitialPc;
            wb_aluop    <= `ALU_OP_NOP;
        end 
        else if(stall[4] == `NoStop) begin
            wb_wd       <= mem_wd;
            wb_wreg     <= mem_wreg;
            wb_wdata    <= mem_wdata;
            wb_pc       <= mem_pc;
            wb_aluop    <= mem_aluop;
        end
    end

endmodule
module mem_wb(

	input wire						clk,
	input wire						rst,
	
	
	input wire[`RegAddrBus]       	mem_wd,
	input wire[`WriteBus]           mem_wreg,
	input wire[`RegBus]				mem_wdata,
	input wire[`InstAddrBus]		mem_pc,
	input wire[`AluOpBus]			mem_aluop,
	input wire[`StopBus]            stall,


	output reg[`RegAddrBus]      	wb_wd,
	output reg[`WriteBus]           wb_wreg,
	output reg[`RegBus]				wb_wdata,
	output reg[`InstAddrBus]		wb_pc,
	output reg[`AluOpBus]			wb_aluop    
	
);

    


    always @(posedge clk) begin
        if(rst == `RstDisable) begin
            wb_wd       <= `ZeroRegAddr;
            wb_wreg     <= `WriteDisable;
            wb_wdata    <= `ZeroWord;
            wb_pc       <= `InitialPc;
            wb_aluop    <= `ALU_OP_NOP;
        end 
        else if(stall[4] == `Stop && stall[5] == `NoStop) begin
            wb_wd       <= `ZeroRegAddr;
            wb_wreg     <= `WriteDisable;
            wb_wdata    <= `ZeroWord;
            wb_pc       <= `InitialPc;
            wb_aluop    <= `ALU_OP_NOP;
        end 
        else if(stall[4] == `NoStop) begin
            wb_wd       <= mem_wd;
            wb_wreg     <= mem_wreg;
            wb_wdata    <= mem_wdata;
            wb_pc       <= mem_pc;
            wb_aluop    <= mem_aluop;
        end
    end

endmodule