data/full_repos/permissive/42434302/ivltests/ca_time.v
1: b'%Error: data/full_repos/permissive/42434302/ivltests/ca_time.v:11: Unsupported or unknown PLI call: $simtime\n  assign smtm = itrig * $simtime;\n                        ^~~~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/ca_time.v:14: Unsupported or unknown PLI call: $monitor\n    $monitor(rtm,, tm,, stm,, smtm);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/ca_time.v:14: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    $monitor(rtm,, tm,, stm,, smtm);\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/ca_time.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #1 itrig = 1\'b1; rtrig = 1.0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/ca_time.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #1 itrig = 1\'b0; rtrig = 0.0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/ca_time.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #1 itrig = 1\'b1; rtrig = 1.0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/ca_time.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #1 itrig = 1\'b0; rtrig = 0.0;\n    ^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  real rtrig = 0.0;
  reg itrig = 1'b0;
  wire real rtm;
  wire [31:0] tm, stm, smtm;

  assign rtm = rtrig * $realtime;
  assign tm = itrig * $time;
  assign stm = itrig * $stime;
  assign smtm = itrig * $simtime;

  initial begin
    $monitor(rtm,, tm,, stm,, smtm);
    #1 itrig = 1'b1; rtrig = 1.0;
    #1 itrig = 1'b0; rtrig = 0.0;
    #1 itrig = 1'b1; rtrig = 1.0;
    #1 itrig = 1'b0; rtrig = 0.0;
  end

endmodule
module top;

  real rtrig = 0.0;
  reg itrig = 1'b0;
  wire real rtm;
  wire [31:0] tm, stm, smtm;

  assign rtm = rtrig * $realtime;
  assign tm = itrig * $time;
  assign stm = itrig * $stime;
  assign smtm = itrig * $simtime;

  initial begin
    $monitor(rtm,, tm,, stm,, smtm);
    #1 itrig = 1'b1; rtrig = 1.0;
    #1 itrig = 1'b0; rtrig = 0.0;
    #1 itrig = 1'b1; rtrig = 1.0;
    #1 itrig = 1'b0; rtrig = 0.0;
  end

endmodule