data/full_repos/permissive/498662723/Verilog Language/Basics/7458.v
1: b'%Error: Cannot find file containing module: Language/Basics,data/full_repos/permissive/498662723\n        ... Looked in:\n             data/full_repos/permissive/498662723/Verilog/Language/Basics,data/full_repos/permissive/498662723\n             data/full_repos/permissive/498662723/Verilog/Language/Basics,data/full_repos/permissive/498662723.v\n             data/full_repos/permissive/498662723/Verilog/Language/Basics,data/full_repos/permissive/498662723.sv\n             Language/Basics,data/full_repos/permissive/498662723\n             Language/Basics,data/full_repos/permissive/498662723.v\n             Language/Basics,data/full_repos/permissive/498662723.sv\n             obj_dir/Language/Basics,data/full_repos/permissive/498662723\n             obj_dir/Language/Basics,data/full_repos/permissive/498662723.v\n             obj_dir/Language/Basics,data/full_repos/permissive/498662723.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/498662723/Verilog\n%Error: Cannot find file containing module: Language/Basics/7458.v\n%Error: Exiting due to 3 error(s)\n'
module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
    
    wire out1, out2, out3, out4;
	
    assign out1 = p2a & p2b;
    assign out2 = p2c & p2d;
    assign p2y = out1 | out2;
    
    assign out3 = p1a & p1b & p1c;
    assign out4 = p1d & p1e & p1f;
    assign p1y = out3 | out4;

endmodule
module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );

    
    wire out1, out2, out3, out4;
	
    assign out1 = p2a & p2b;
    assign out2 = p2c & p2d;
    assign p2y = out1 | out2;
    
    assign out3 = p1a & p1b & p1c;
    assign out4 = p1d & p1e & p1f;
    assign p1y = out3 | out4;

endmodule