data/full_repos/permissive/464128338/SD-card-SPI-to-speaker-verilog-program/src/BCH_to_7_segment_LED_Decoder.v
1: b'%Warning-CMPCONST: data/full_repos/permissive/464128338/SD-card-SPI-to-speaker-verilog-program/src/BCH_to_7_segment_LED_Decoder.v:133: Comparison is constant due to limited range\n                                                                                                                                     : ... In instance BCH_to_7_segment_LED_Decoder\n   else if((In >= 32\'h10000000) && (In <= 32\'hFFFFFFFF)) \n                                       ^~\n                   ... Use "/* verilator lint_off CMPCONST */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module BCH_to_7_segment_LED_Decoder( 
         output reg DP,
         output reg [6:0] Cathodes,
         output reg [7:0] Anodes,
         input  Enable, Clock_100MHz, Clear_n,
         input  [31:0] In); 
         
        






    
    reg [12:0] count_6250; 
    reg clock_8KHz;  
  
    always@(posedge Clock_100MHz, negedge Clear_n)
       if(!Clear_n)
          begin
            count_6250  <= 0;
            clock_8KHz  <= 0;
          end          
       else if(count_6250 == 6249)
            begin
              count_6250  <= 0;
              clock_8KHz <= ~clock_8KHz;                                
            end 
        else if(Enable)
             count_6250 <= count_6250 + 1;
          
          


     reg [2:0] Digit;
     
     always@(posedge clock_8KHz, negedge Clear_n)
        if(!Clear_n)
           Digit <= 3'b000;          
        else if(Digit == 7) 
           Digit <= 3'b000;                    
        else if(Enable)
           Digit <= Digit + 1;  
           
          

  always@(negedge clock_8KHz, negedge Clear_n)
    if(!Clear_n)
       begin 
         DP <= 1;
         Anodes   <= 8'b11111110;
         Decoder(4'd0);
       end   
    else if(In <= 4'hF)  
       case(Digit)
               0 : Digit_0;
         default : Digit_disable;          
       endcase         
    else if((In >= 8'h10) && (In <= 8'hFF)) 
       case(Digit)
               0 : Digit_0;
               1 : Digit_1;
         default : Digit_disable;  
       endcase         
    else if((In >= 12'h100) && (In <= 12'hFFF))       
       case(Digit)
               0 : Digit_0;
               1 : Digit_1;
               2 : Digit_2;
         default : Digit_disable; 
       endcase        
    else if((In >= 16'h1000) && (In <= 16'hFFFF)) 
        case(Digit)
                0 : Digit_0;
                1 : Digit_1;
                2 : Digit_2;
                3 : Digit_3;
          default : Digit_disable;       
        endcase         
    else if((In >= 20'h10000) && (In <= 20'hFFFFF))
        case(Digit)
                0 : Digit_0;
                1 : Digit_1;
                2 : Digit_2;
                3 : Digit_3;
                4 : Digit_4;
          default : Digit_disable;      
        endcase         
    else if((In >= 24'h100000) && (In <= 24'hFFFFFF))
        case(Digit)
                0 : Digit_0;
                1 : Digit_1;
                2 : Digit_2;
                3 : Digit_3;
                4 : Digit_4;
                5 : Digit_5;
          default : Digit_disable;      
        endcase  
   else if((In >= 28'h1000000) && (In <= 28'hFFFFFFF))
        case(Digit)
                0 : Digit_0;
                1 : Digit_1;
                2 : Digit_2;
                3 : Digit_3;
                4 : Digit_4;
                5 : Digit_5;
                6 : Digit_6;
          default : Digit_disable;      
        endcase
   else if((In >= 32'h10000000) && (In <= 32'hFFFFFFFF)) 
        case(Digit)
                0 : Digit_0;
                1 : Digit_1;
                2 : Digit_2;
                3 : Digit_3;
                4 : Digit_4;
                5 : Digit_5;
                6 : Digit_6;
                7 : Digit_7;
        endcase    
   else
       Digit_disable;  
       
      
 task Digit_disable;
   begin  
     DP <= 1;
     Anodes   <= 8'b11111111;
     Cathodes <= 7'b1111111;
   end  
 endtask        
                     
 task Digit_0;
   begin
     DP <= 1;
     Anodes <= 8'b11111110;
     Decoder(In[3:0]);
   end  
 endtask  
          
 task Digit_1;
   begin
     DP <= 1;
     Anodes <= 8'b11111101;
     Decoder(In[7:4]);
   end  
 endtask     
          
 task Digit_2;
   begin          
     DP <= 1;
     Anodes <= 8'b11111011;
     Decoder(In[11:8]);
   end  
 endtask 
          
 task Digit_3;
   begin
    DP <= 1;
    Anodes <= 8'b11110111;
    Decoder(In[15:12]);
   end  
 endtask  
          
 task Digit_4;
   begin
     DP <= 1;
     Anodes <= 8'b11101111;
     Decoder(In[19:16]);
   end  
 endtask 
          
 task Digit_5;
   begin
     DP <= 1;
     Anodes <= 8'b11011111;
     Decoder(In[23:20]);
   end  
 endtask 
      
 task Digit_6;
   begin
     DP <= 1;
     Anodes <= 8'b10111111;
     Decoder(In[27:24]);
   end  
 endtask 
          
 task Digit_7;
   begin
     DP <= 1;
     Anodes <= 8'b01111111;
     Decoder(In[31:28]);
   end  
 endtask  
         
  

    task Decoder;
     input [3:0] BCH_Number;
      case(BCH_Number)
           0:  Cathodes <= 7'b0000001;
           1:  Cathodes <= 7'b1001111;
           2:  Cathodes <= 7'b0010010;
           3:  Cathodes <= 7'b0000110;
           4:  Cathodes <= 7'b1001100;
           5:  Cathodes <= 7'b0100100;
           6:  Cathodes <= 7'b0100000;
           7:  Cathodes <= 7'b0001111;
           8:  Cathodes <= 7'b0000000;
           9:  Cathodes <= 7'b0000100;
           10: Cathodes <= 7'b0001000;
           11: Cathodes <= 7'b1100000;
           12: Cathodes <= 7'b0110001;
           13: Cathodes <= 7'b1000010;
           14: Cathodes <= 7'b0110000;
           15: Cathodes <= 7'b0111000;
       endcase                 
     endtask   
   
 endmodule
module BCH_to_7_segment_LED_Decoder( 
         output reg DP,
         output reg [6:0] Cathodes,
         output reg [7:0] Anodes,
         input  Enable, Clock_100MHz, Clear_n,
         input  [31:0] In);
 
         
        






    
    reg [12:0] count_6250; 
    reg clock_8KHz;  
  
    always@(posedge Clock_100MHz, negedge Clear_n)
       if(!Clear_n)
          begin
            count_6250  <= 0;
            clock_8KHz  <= 0;
          end          
       else if(count_6250 == 6249)
            begin
              count_6250  <= 0;
              clock_8KHz <= ~clock_8KHz;                                
            end 
        else if(Enable)
             count_6250 <= count_6250 + 1;
          
          


     reg [2:0] Digit;
     
     always@(posedge clock_8KHz, negedge Clear_n)
        if(!Clear_n)
           Digit <= 3'b000;          
        else if(Digit == 7) 
           Digit <= 3'b000;                    
        else if(Enable)
           Digit <= Digit + 1;  
           
          

  always@(negedge clock_8KHz, negedge Clear_n)
    if(!Clear_n)
       begin 
         DP <= 1;
         Anodes   <= 8'b11111110;
         Decoder(4'd0);
       end   
    else if(In <= 4'hF)  
       case(Digit)
               0 : Digit_0;
         default : Digit_disable;          
       endcase         
    else if((In >= 8'h10) && (In <= 8'hFF)) 
       case(Digit)
               0 : Digit_0;
               1 : Digit_1;
         default : Digit_disable;  
       endcase         
    else if((In >= 12'h100) && (In <= 12'hFFF))       
       case(Digit)
               0 : Digit_0;
               1 : Digit_1;
               2 : Digit_2;
         default : Digit_disable; 
       endcase        
    else if((In >= 16'h1000) && (In <= 16'hFFFF)) 
        case(Digit)
                0 : Digit_0;
                1 : Digit_1;
                2 : Digit_2;
                3 : Digit_3;
          default : Digit_disable;       
        endcase         
    else if((In >= 20'h10000) && (In <= 20'hFFFFF))
        case(Digit)
                0 : Digit_0;
                1 : Digit_1;
                2 : Digit_2;
                3 : Digit_3;
                4 : Digit_4;
          default : Digit_disable;      
        endcase         
    else if((In >= 24'h100000) && (In <= 24'hFFFFFF))
        case(Digit)
                0 : Digit_0;
                1 : Digit_1;
                2 : Digit_2;
                3 : Digit_3;
                4 : Digit_4;
                5 : Digit_5;
          default : Digit_disable;      
        endcase  
   else if((In >= 28'h1000000) && (In <= 28'hFFFFFFF))
        case(Digit)
                0 : Digit_0;
                1 : Digit_1;
                2 : Digit_2;
                3 : Digit_3;
                4 : Digit_4;
                5 : Digit_5;
                6 : Digit_6;
          default : Digit_disable;      
        endcase
   else if((In >= 32'h10000000) && (In <= 32'hFFFFFFFF)) 
        case(Digit)
                0 : Digit_0;
                1 : Digit_1;
                2 : Digit_2;
                3 : Digit_3;
                4 : Digit_4;
                5 : Digit_5;
                6 : Digit_6;
                7 : Digit_7;
        endcase    
   else
       Digit_disable;  
       
      
 task Digit_disable;
   begin  
     DP <= 1;
     Anodes   <= 8'b11111111;
     Cathodes <= 7'b1111111;
   end  
 endtask        
                     
 task Digit_0;
   begin
     DP <= 1;
     Anodes <= 8'b11111110;
     Decoder(In[3:0]);
   end  
 endtask  
          
 task Digit_1;
   begin
     DP <= 1;
     Anodes <= 8'b11111101;
     Decoder(In[7:4]);
   end  
 endtask     
          
 task Digit_2;
   begin          
     DP <= 1;
     Anodes <= 8'b11111011;
     Decoder(In[11:8]);
   end  
 endtask 
          
 task Digit_3;
   begin
    DP <= 1;
    Anodes <= 8'b11110111;
    Decoder(In[15:12]);
   end  
 endtask  
          
 task Digit_4;
   begin
     DP <= 1;
     Anodes <= 8'b11101111;
     Decoder(In[19:16]);
   end  
 endtask 
          
 task Digit_5;
   begin
     DP <= 1;
     Anodes <= 8'b11011111;
     Decoder(In[23:20]);
   end  
 endtask 
      
 task Digit_6;
   begin
     DP <= 1;
     Anodes <= 8'b10111111;
     Decoder(In[27:24]);
   end  
 endtask 
          
 task Digit_7;
   begin
     DP <= 1;
     Anodes <= 8'b01111111;
     Decoder(In[31:28]);
   end  
 endtask  
         
  

    task Decoder;
     input [3:0] BCH_Number;
      case(BCH_Number)
           0:  Cathodes <= 7'b0000001;
           1:  Cathodes <= 7'b1001111;
           2:  Cathodes <= 7'b0010010;
           3:  Cathodes <= 7'b0000110;
           4:  Cathodes <= 7'b1001100;
           5:  Cathodes <= 7'b0100100;
           6:  Cathodes <= 7'b0100000;
           7:  Cathodes <= 7'b0001111;
           8:  Cathodes <= 7'b0000000;
           9:  Cathodes <= 7'b0000100;
           10: Cathodes <= 7'b0001000;
           11: Cathodes <= 7'b1100000;
           12: Cathodes <= 7'b0110001;
           13: Cathodes <= 7'b1000010;
           14: Cathodes <= 7'b0110000;
           15: Cathodes <= 7'b0111000;
       endcase                 
     endtask   
   
 endmodule