data/full_repos/permissive/463481430/project/al_ip/sdram_sim.v
1: b"%Error: data/full_repos/permissive/463481430/project/al_ip/sdram_sim.v:37: Cannot find file containing module: 'EG_PHY_CONFIG'\n  EG_PHY_CONFIG #(\n  ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463481430/project/al_ip,data/full_repos/permissive/463481430/EG_PHY_CONFIG\n             data/full_repos/permissive/463481430/project/al_ip,data/full_repos/permissive/463481430/EG_PHY_CONFIG.v\n             data/full_repos/permissive/463481430/project/al_ip,data/full_repos/permissive/463481430/EG_PHY_CONFIG.sv\n             EG_PHY_CONFIG\n             EG_PHY_CONFIG.v\n             EG_PHY_CONFIG.sv\n             obj_dir/EG_PHY_CONFIG\n             obj_dir/EG_PHY_CONFIG.v\n             obj_dir/EG_PHY_CONFIG.sv\n%Error: data/full_repos/permissive/463481430/project/al_ip/sdram_sim.v:43: Cannot find file containing module: 'EG_PHY_SDRAM_2M_32'\n  EG_PHY_SDRAM_2M_32 sdram (\n  ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module SDRAM
  (
  addr,
  ba,
  cas_n,
  cke,
  clk,
  cs_n,
  dm0,
  dm1,
  dm2,
  dm3,
  ras_n,
  we_n,
  dq
  );

  input [10:0] addr;
  input [1:0] ba;
  input cas_n;
  input cke;
  input clk;
  input cs_n;
  input dm0;
  input dm1;
  input dm2;
  input dm3;
  input ras_n;
  input we_n;
  inout [31:0] dq;


  EG_PHY_CONFIG #(
    .DONE_PERSISTN("ENABLE"),
    .INIT_PERSISTN("ENABLE"),
    .JTAG_PERSISTN("DISABLE"),
    .PROGRAMN_PERSISTN("DISABLE"))
    config_inst ();
  EG_PHY_SDRAM_2M_32 sdram (
    .addr(addr),
    .ba(ba),
    .cas_n(cas_n),
    .cke(cke),
    .clk(clk),
    .cs_n(cs_n),
    .dm0(dm0),
    .dm1(dm1),
    .dm2(dm2),
    .dm3(dm3),
    .ras_n(ras_n),
    .we_n(we_n),
    .dq(dq));

endmodule
module SDRAM
  (
  addr,
  ba,
  cas_n,
  cke,
  clk,
  cs_n,
  dm0,
  dm1,
  dm2,
  dm3,
  ras_n,
  we_n,
  dq
  );


  input [10:0] addr;
  input [1:0] ba;
  input cas_n;
  input cke;
  input clk;
  input cs_n;
  input dm0;
  input dm1;
  input dm2;
  input dm3;
  input ras_n;
  input we_n;
  inout [31:0] dq;


  EG_PHY_CONFIG #(
    .DONE_PERSISTN("ENABLE"),
    .INIT_PERSISTN("ENABLE"),
    .JTAG_PERSISTN("DISABLE"),
    .PROGRAMN_PERSISTN("DISABLE"))
    config_inst ();
  EG_PHY_SDRAM_2M_32 sdram (
    .addr(addr),
    .ba(ba),
    .cas_n(cas_n),
    .cke(cke),
    .clk(clk),
    .cs_n(cs_n),
    .dm0(dm0),
    .dm1(dm1),
    .dm2(dm2),
    .dm3(dm3),
    .ras_n(ras_n),
    .we_n(we_n),
    .dq(dq));

endmodule