data/full_repos/permissive/494148647/src/util/async_handshake_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/494148647/src/util/async_handshake_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n        forever #SRC_CLK_DELAY clk_src = ~clk_src;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/494148647/src/util/async_handshake_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n        forever #DST_CLK_DELAY clk_dst = ~clk_dst;\n                ^\n%Error: data/full_repos/permissive/494148647/src/util/async_handshake_tb.v:52: syntax error, unexpected \'@\'\n        repeat(4) @(negedge clk_dst);\n                  ^\n%Error: data/full_repos/permissive/494148647/src/util/async_handshake_tb.v:58: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("async_handshake_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/494148647/src/util/async_handshake_tb.v:59: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, async_handshake_tb);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/494148647/src/util/async_handshake_tb.v:66: syntax error, unexpected \'@\'\n        @(negedge rst);\n        ^\n%Error: data/full_repos/permissive/494148647/src/util/async_handshake_tb.v:79: syntax error, unexpected \'@\'\n        @(posedge clk_src) valid_src <= #1 1\'b1;\n        ^\n%Error: data/full_repos/permissive/494148647/src/util/async_handshake_tb.v:84: syntax error, unexpected \'@\'\n            @(posedge clk_dst) #1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/494148647/src/util/async_handshake_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/494148647/src/util/async_handshake_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n        #1 ready_dst = 1\'b1;\n        ^\n%Error: data/full_repos/permissive/494148647/src/util/async_handshake_tb.v:95: syntax error, unexpected \'@\'\n        @(posedge clk_dst) ready_dst <= #1 1\'b0;\n        ^\n%Error: data/full_repos/permissive/494148647/src/util/async_handshake_tb.v:99: syntax error, unexpected \'@\'\n            @(posedge clk_src) #1;\n            ^\n%Error: data/full_repos/permissive/494148647/src/util/async_handshake_tb.v:111: syntax error, unexpected \'@\'\n        @(posedge clk_src);\n        ^\n%Error: Exiting due to 9 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module async_handshake_tb #(
    parameter SRC_CLK_DELAY = 3.75,
    parameter DST_CLK_DELAY = 10,
    parameter DATA_W = 8
    ) ();

    reg rst, clk_src, clk_dst, valid_src, ready_dst;
    wire valid_dst, ready_src;

    reg  [DATA_W-1:0] data_src;
    wire [DATA_W-1:0] data_dst;

    async_handshake #(
        .DATA_W(DATA_W)
    ) DUT (
        .rst_src(rst),
        .clk_src(clk_src),
        .data_src(data_src),
        .valid_src(valid_src),
        .ready_src(ready_src),
        .rst_dst(rst),
        .clk_dst(clk_dst),
        .data_dst(data_dst),
        .valid_dst(valid_dst),
        .ready_dst(ready_dst)
    );


    initial begin
        clk_src = 0;
        forever #SRC_CLK_DELAY clk_src = ~clk_src;
    end


    initial begin
        clk_dst = 0;
        forever #DST_CLK_DELAY clk_dst = ~clk_dst;
    end


    initial begin
        rst = 1'b1;
        repeat(4) @(negedge clk_dst);
        rst = 1'b0;
    end


    initial begin
        $dumpfile("async_handshake_tb.vcd");
        $dumpvars(0, async_handshake_tb);

        valid_src = 1'b0;
        ready_dst = 1'b0;
        data_src = {DATA_W{1'b0}};


        @(negedge rst);
        @(posedge clk_src) #1;


        if (data_dst != {DATA_W{1'b0}} || valid_dst == 1'b1 || ready_src == 1'b1)
            $display("%t: ERROR: invalid initial state", $time);
        else
            $display("%t: INFO: initial state valid", $time);


        data_src = 8'hA5;


        @(posedge clk_src) valid_src <= #1 1'b1;
        @(posedge clk_src) valid_src <= #1 1'b0;


        while (~valid_dst)
            @(posedge clk_dst) #1;


        #1;
        if (data_dst != 8'hA5 || ready_src == 1'b1)
            $display("%t: ERROR: invalid src->dest state", $time);
        else
            $display("%t: INFO: src->dest state valid", $time);


        #1 ready_dst = 1'b1;
        @(posedge clk_dst) ready_dst <= #1 1'b0;


        while (~ready_src)
            @(posedge clk_src) #1;


        data_src = 8'h5A;


        if (data_dst != 8'hA5 || valid_src == 1'b1)
            $display("%t: ERROR: invalid final state", $time);
        else
            $display("%t: INFO: final state valid", $time);


        @(posedge clk_src);
        @(posedge clk_dst);
        $finish;
    end

endmodule
module async_handshake_tb #(
    parameter SRC_CLK_DELAY = 3.75,
    parameter DST_CLK_DELAY = 10,
    parameter DATA_W = 8
    ) ();


    reg rst, clk_src, clk_dst, valid_src, ready_dst;
    wire valid_dst, ready_src;

    reg  [DATA_W-1:0] data_src;
    wire [DATA_W-1:0] data_dst;

    async_handshake #(
        .DATA_W(DATA_W)
    ) DUT (
        .rst_src(rst),
        .clk_src(clk_src),
        .data_src(data_src),
        .valid_src(valid_src),
        .ready_src(ready_src),
        .rst_dst(rst),
        .clk_dst(clk_dst),
        .data_dst(data_dst),
        .valid_dst(valid_dst),
        .ready_dst(ready_dst)
    );


    initial begin
        clk_src = 0;
        forever #SRC_CLK_DELAY clk_src = ~clk_src;
    end


    initial begin
        clk_dst = 0;
        forever #DST_CLK_DELAY clk_dst = ~clk_dst;
    end


    initial begin
        rst = 1'b1;
        repeat(4) @(negedge clk_dst);
        rst = 1'b0;
    end


    initial begin
        $dumpfile("async_handshake_tb.vcd");
        $dumpvars(0, async_handshake_tb);

        valid_src = 1'b0;
        ready_dst = 1'b0;
        data_src = {DATA_W{1'b0}};


        @(negedge rst);
        @(posedge clk_src) #1;


        if (data_dst != {DATA_W{1'b0}} || valid_dst == 1'b1 || ready_src == 1'b1)
            $display("%t: ERROR: invalid initial state", $time);
        else
            $display("%t: INFO: initial state valid", $time);


        data_src = 8'hA5;


        @(posedge clk_src) valid_src <= #1 1'b1;
        @(posedge clk_src) valid_src <= #1 1'b0;


        while (~valid_dst)
            @(posedge clk_dst) #1;


        #1;
        if (data_dst != 8'hA5 || ready_src == 1'b1)
            $display("%t: ERROR: invalid src->dest state", $time);
        else
            $display("%t: INFO: src->dest state valid", $time);


        #1 ready_dst = 1'b1;
        @(posedge clk_dst) ready_dst <= #1 1'b0;


        while (~ready_src)
            @(posedge clk_src) #1;


        data_src = 8'h5A;


        if (data_dst != 8'hA5 || valid_src == 1'b1)
            $display("%t: ERROR: invalid final state", $time);
        else
            $display("%t: INFO: final state valid", $time);


        @(posedge clk_src);
        @(posedge clk_dst);
        $finish;
    end

endmodule