data/full_repos/permissive/515613199/divider.v
1: b'%Error: data/full_repos/permissive/515613199/divider.v:1: Cannot find include file: reg_size.v\n`include "reg_size.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/515613199,data/full_repos/permissive/515613199/reg_size.v\n             data/full_repos/permissive/515613199,data/full_repos/permissive/515613199/reg_size.v.v\n             data/full_repos/permissive/515613199,data/full_repos/permissive/515613199/reg_size.v.sv\n             reg_size.v\n             reg_size.v.v\n             reg_size.v.sv\n             obj_dir/reg_size.v\n             obj_dir/reg_size.v.v\n             obj_dir/reg_size.v.sv\n%Error: data/full_repos/permissive/515613199/divider.v:6: Define or directive not defined: \'`SIZE\'\n input [`SIZE-1:0] N,  \n        ^~~~~\n%Error: data/full_repos/permissive/515613199/divider.v:21: Define or directive not defined: \'`SIZE\'\n assign exception = ~| N[`SIZE-1:1]; \n                         ^~~~~\n%Error: Exiting due to 3 error(s)\n'
module N_divider(
    input ref_clk,
	input enable,
	input [`SIZE-1:0] N,
	input reset,
	output div_clk
    );
	
	wire clk;
	wire out_odd;
	wire out_even;
	wire exception;
	wire enable_even;
	wire enable_odd;
	reg q_en;

	assign clk = ref_clk & q_en;

	assign exception = ~| N[`SIZE-1:1];	

	assign div_clk = (enable)? ( (exception)? ref_clk : ( N[0] ? out_odd : out_even ) ) : 1'hz;

	assign enable_odd  =  N[0] & !exception;
	assign enable_even = ~N[0] & !exception;

	even_divider E(clk, N, reset, enable_even, out_even);
	odd_divider  O(clk, N, reset, enable_odd, out_odd);

	always@(negedge ref_clk or posedge reset)
	begin
	   q_en <= (reset)? 1'b0 : enable ;
	end
	
endmodule
module N_divider(
    input ref_clk,
	input enable,
	input [`SIZE-1:0] N,
	input reset,
	output div_clk
    );

	
	wire clk;
	wire out_odd;
	wire out_even;
	wire exception;
	wire enable_even;
	wire enable_odd;
	reg q_en;

	assign clk = ref_clk & q_en;

	assign exception = ~| N[`SIZE-1:1];	

	assign div_clk = (enable)? ( (exception)? ref_clk : ( N[0] ? out_odd : out_even ) ) : 1'hz;

	assign enable_odd  =  N[0] & !exception;
	assign enable_even = ~N[0] & !exception;

	even_divider E(clk, N, reset, enable_even, out_even);
	odd_divider  O(clk, N, reset, enable_odd, out_odd);

	always@(negedge ref_clk or posedge reset)
	begin
	   q_en <= (reset)? 1'b0 : enable ;
	end
	
endmodule