data/full_repos/permissive/451853158/MIPS_Pipeline_Processor/instrMem.v
data/verilator_xmls/989ca133-add1-48c4-aea7-2bc3c3d18ca0.xml
module instrMem (
  input [5:0] a,
  output wire [31:0] instr
);

reg [31:0] imem [63:0];

assign instr = imem[a];

initial $readmemh("memfile.dat", imem);

endmodule
module instrMem (
  input [5:0] a,
  output wire [31:0] instr
);


reg [31:0] imem [63:0];

assign instr = imem[a];

initial $readmemh("memfile.dat", imem);

endmodule