data/full_repos/permissive/502744275/vga_text_avl_interface.sv
1: b"%Error: data/full_repos/permissive/502744275/vga_text_avl_interface.sv:77: Cannot find file containing module: 'vga_controller'\n vga_controller vc0 (\n ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502744275,data/full_repos/permissive/502744275/vga_controller\n             data/full_repos/permissive/502744275,data/full_repos/permissive/502744275/vga_controller.v\n             data/full_repos/permissive/502744275,data/full_repos/permissive/502744275/vga_controller.sv\n             vga_controller\n             vga_controller.v\n             vga_controller.sv\n             obj_dir/vga_controller\n             obj_dir/vga_controller.v\n             obj_dir/vga_controller.sv\n%Error: data/full_repos/permissive/502744275/vga_text_avl_interface.sv:89: Cannot find file containing module: 'font_rom'\n font_rom fr0 (\n ^~~~~~~~\n%Error: data/full_repos/permissive/502744275/vga_text_avl_interface.sv:94: Cannot find file containing module: 'ram'\n ram ram0 (\n ^~~\n%Error: Exiting due to 3 error(s)\n"
module vga_text_avl_interface (


	input logic CLK,
	

	input logic RESET,
	

	input  logic AVL_READ,
	input  logic AVL_WRITE,
	input  logic AVL_CS,
	input  logic [3:0] AVL_BYTE_EN,
	input  logic [11:0] AVL_ADDR,
	input  logic [31:0] AVL_WRITEDATA,
	output logic [31:0] AVL_READDATA,
	

	output logic [3:0]  red, green, blue,
	output logic hs, vs
);



logic [9:0] drawX, drawY;
logic [10:0] index;
logic [7:0] charData;
logic [11:0] address;
logic currentBit;
logic inverse;
logic pixel_clk;
logic blank, sync;


logic [31:0] ram_output;
logic [11:0] ram_read_address;


logic [31:0] PALETTE_REG [8];

always_ff @(posedge CLK) begin
	if(AVL_WRITE & AVL_ADDR[11])
		PALETTE_REG[AVL_ADDR[2:0]] <= AVL_WRITEDATA;
		
	if(AVL_READ & AVL_ADDR[11])
		AVL_READDATA <= PALETTE_REG[AVL_ADDR[2:0]];
end


	vga_controller vc0 (
		.Clk(CLK),
		.Reset(RESET),
		.hs(hs),
		.vs(vs),
		.pixel_clk(pixel_clk),
		.blank(blank),
		.sync(sync),
		.DrawX(drawX),
		.DrawY(drawY)
	);
	
	font_rom fr0 (
		.addr(index),
		.data(charData)
	);
	
	ram ram0 (
		.address_a(AVL_ADDR),
		.address_b(ram_read_address),
		.byteena_a(AVL_BYTE_EN),
		.byteena_b(),
		.clock(CLK),
		.data_a(AVL_WRITEDATA),
		.data_b(),
		.rden_a(1'b1),
		.rden_b(1'b1),
		.wren_a(AVL_CS & AVL_WRITE & ~AVL_ADDR[11]),
		.wren_b(1'b0),
		.q_a(),
		.q_b(ram_output)
	);
  

always_comb begin




















end

always_ff @(posedge pixel_clk) begin
	if (!blank) begin
		red <= 4'h0;
		green <= 4'h0;
		blue <= 4'h0;
	end
	else begin
		if (drawY < 320) begin
			red <= 4'h8;
			green <= 4'ha;
			blue <= 4'hf;
		end
		else begin
			red <= 4'h4;
			green <= 4'hf;
			blue <= 4'h4;
		end
	end
end

endmodule
module vga_text_avl_interface (


	input logic CLK,
	

	input logic RESET,
	

	input  logic AVL_READ,
	input  logic AVL_WRITE,
	input  logic AVL_CS,
	input  logic [3:0] AVL_BYTE_EN,
	input  logic [11:0] AVL_ADDR,
	input  logic [31:0] AVL_WRITEDATA,
	output logic [31:0] AVL_READDATA,
	

	output logic [3:0]  red, green, blue,
	output logic hs, vs
);




logic [9:0] drawX, drawY;
logic [10:0] index;
logic [7:0] charData;
logic [11:0] address;
logic currentBit;
logic inverse;
logic pixel_clk;
logic blank, sync;


logic [31:0] ram_output;
logic [11:0] ram_read_address;


logic [31:0] PALETTE_REG [8];

always_ff @(posedge CLK) begin
	if(AVL_WRITE & AVL_ADDR[11])
		PALETTE_REG[AVL_ADDR[2:0]] <= AVL_WRITEDATA;
		
	if(AVL_READ & AVL_ADDR[11])
		AVL_READDATA <= PALETTE_REG[AVL_ADDR[2:0]];
end


	vga_controller vc0 (
		.Clk(CLK),
		.Reset(RESET),
		.hs(hs),
		.vs(vs),
		.pixel_clk(pixel_clk),
		.blank(blank),
		.sync(sync),
		.DrawX(drawX),
		.DrawY(drawY)
	);
	
	font_rom fr0 (
		.addr(index),
		.data(charData)
	);
	
	ram ram0 (
		.address_a(AVL_ADDR),
		.address_b(ram_read_address),
		.byteena_a(AVL_BYTE_EN),
		.byteena_b(),
		.clock(CLK),
		.data_a(AVL_WRITEDATA),
		.data_b(),
		.rden_a(1'b1),
		.rden_b(1'b1),
		.wren_a(AVL_CS & AVL_WRITE & ~AVL_ADDR[11]),
		.wren_b(1'b0),
		.q_a(),
		.q_b(ram_output)
	);
  

always_comb begin




















end

always_ff @(posedge pixel_clk) begin
	if (!blank) begin
		red <= 4'h0;
		green <= 4'h0;
		blue <= 4'h0;
	end
	else begin
		if (drawY < 320) begin
			red <= 4'h8;
			green <= 4'ha;
			blue <= 4'hf;
		end
		else begin
			red <= 4'h4;
			green <= 4'hf;
			blue <= 4'h4;
		end
	end
end

endmodule