data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_loop_unrolling/bdw_work/modules/dut/UNROLL_FILL/v_rtl/dut_LessThan_5Sx5S_1U_4.v
data/verilator_xmls/3a2cf57b-b9ab-4a4d-901a-45fc6ca294f0.xml
module dut_LessThan_5Sx5S_1U_4 (
	in2,
	in1,
	out1
	);
input [4:0] in2,
	in1;
output  out1;
wire  asc001;

assign asc001 = ((10'B1000000000 ^ {{5{in1[4]}}, in1})>(10'B1000000000 ^ {{5{in2[4]}}, in2}));

assign out1 = asc001;
endmodule
module dut_LessThan_5Sx5S_1U_4 (
	in2,
	in1,
	out1
	);

input [4:0] in2,
	in1;
output  out1;
wire  asc001;

assign asc001 = ((10'B1000000000 ^ {{5{in1[4]}}, in1})>(10'B1000000000 ^ {{5{in2[4]}}, in2}));

assign out1 = asc001;
endmodule