data/full_repos/permissive/528677531/LAB-4/Q1/qb_tb.v
1: b'%Error: data/full_repos/permissive/528677531/LAB-4/Q1/qb_tb.v:2: Cannot find include file: qb.v\n`include "qb.v" \n         ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/528677531/LAB-4/Q1,data/full_repos/permissive/528677531/qb.v\n             data/full_repos/permissive/528677531/LAB-4/Q1,data/full_repos/permissive/528677531/qb.v.v\n             data/full_repos/permissive/528677531/LAB-4/Q1,data/full_repos/permissive/528677531/qb.v.sv\n             qb.v\n             qb.v.v\n             qb.v.sv\n             obj_dir/qb.v\n             obj_dir/qb.v.v\n             obj_dir/qb.v.sv\n%Error: data/full_repos/permissive/528677531/LAB-4/Q1/qb_tb.v:9: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("qb_tb.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/528677531/LAB-4/Q1/qb_tb.v:10: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0,qb_tb);\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-4/Q1/qb_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\nx=1\'b0; y=1\'b0; #20;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-4/Q1/qb_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\nx=1\'b0; y=1\'b1; #20;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-4/Q1/qb_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\nx=1\'b1; y=1\'b0; #20;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-4/Q1/qb_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\nx=1\'b1; y=1\'b1; #20; \n                ^\n%Error: data/full_repos/permissive/528677531/LAB-4/Q1/qb_tb.v:25: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("qb_tb.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/528677531/LAB-4/Q1/qb_tb.v:26: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0,qb_tb);\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-4/Q1/qb_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b0; y1=1\'b0; Cin=1\'b0; #20;\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-4/Q1/qb_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b0; y1=1\'b0; Cin=1\'b1; #20;\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-4/Q1/qb_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b0; y1=1\'b1; Cin=1\'b0; #20;\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-4/Q1/qb_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b0; y1=1\'b1; Cin=1\'b1; #20;\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-4/Q1/qb_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b1; y1=1\'b0; Cin=1\'b0; #20;\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-4/Q1/qb_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b1; y1=1\'b0; Cin=1\'b1; #20;\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-4/Q1/qb_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b1; y1=1\'b1; Cin=1\'b0; #20;\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-4/Q1/qb_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\nx1=1\'b1; y1=1\'b1; Cin=1\'b1; #20;\n                            ^\n%Error: data/full_repos/permissive/528677531/LAB-4/Q1/qb_tb.v:45: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("qb_tb.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/528677531/LAB-4/Q1/qb_tb.v:46: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0,qb_tb);\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-4/Q1/qb_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\nx2=1\'b0; y2=1\'b0; CIn=1\'b0; #20;\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-4/Q1/qb_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\nx2=1\'b0; y2=1\'b0; CIn=1\'b1; #20;\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-4/Q1/qb_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\nx2=1\'b0; y2=1\'b1; CIn=1\'b0; #20;\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-4/Q1/qb_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\nx2=1\'b0; y2=1\'b1; CIn=1\'b1; #20;\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-4/Q1/qb_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\nx2=1\'b1; y2=1\'b0; CIn=1\'b0; #20;\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-4/Q1/qb_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\nx2=1\'b1; y2=1\'b0; CIn=1\'b1; #20;\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-4/Q1/qb_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\nx2=1\'b1; y2=1\'b1; CIn=1\'b0; #20;\n                            ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-4/Q1/qb_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\nx2=1\'b1; y2=1\'b1; CIn=1\'b1; #20;\n                            ^\n%Error: Exiting due to 7 error(s), 20 warning(s)\n'
module qb_tb();
reg x,y;
wire sum,cout;
halfadder ha(x,y,sum,cout);
initial
begin
$dumpfile("qb_tb.vcd");
$dumpvars(0,qb_tb);

x=1'b0; y=1'b0; #20;
x=1'b0; y=1'b1; #20;
x=1'b1; y=1'b0; #20;
x=1'b1; y=1'b1; #20; 

$display("Test Complete");
end

reg x1,y1,Cin;
wire Sum,Cout;
fulladder fa(x1,y1,Cin,Sum,Cout);
initial
begin
$dumpfile("qb_tb.vcd");
$dumpvars(0,qb_tb);

x1=1'b0; y1=1'b0; Cin=1'b0; #20;
x1=1'b0; y1=1'b0; Cin=1'b1; #20;
x1=1'b0; y1=1'b1; Cin=1'b0; #20;
x1=1'b0; y1=1'b1; Cin=1'b1; #20;
x1=1'b1; y1=1'b0; Cin=1'b0; #20;
x1=1'b1; y1=1'b0; Cin=1'b1; #20;
x1=1'b1; y1=1'b1; Cin=1'b0; #20;
x1=1'b1; y1=1'b1; Cin=1'b1; #20;

$display("Test Complete");
end

reg x2,y2,CIn;
wire Sum1,Cout1;
decomposedfulladder dfa(x2,y2,CIn,Sum1,Cout1);
initial
begin
$dumpfile("qb_tb.vcd");
$dumpvars(0,qb_tb);

x2=1'b0; y2=1'b0; CIn=1'b0; #20;
x2=1'b0; y2=1'b0; CIn=1'b1; #20;
x2=1'b0; y2=1'b1; CIn=1'b0; #20;
x2=1'b0; y2=1'b1; CIn=1'b1; #20;
x2=1'b1; y2=1'b0; CIn=1'b0; #20;
x2=1'b1; y2=1'b0; CIn=1'b1; #20;
x2=1'b1; y2=1'b1; CIn=1'b0; #20;
x2=1'b1; y2=1'b1; CIn=1'b1; #20;

$display("Test Complete");
end
endmodule
module qb_tb();

reg x,y;
wire sum,cout;
halfadder ha(x,y,sum,cout);
initial
begin
$dumpfile("qb_tb.vcd");
$dumpvars(0,qb_tb);

x=1'b0; y=1'b0; #20;
x=1'b0; y=1'b1; #20;
x=1'b1; y=1'b0; #20;
x=1'b1; y=1'b1; #20; 

$display("Test Complete");
end

reg x1,y1,Cin;
wire Sum,Cout;
fulladder fa(x1,y1,Cin,Sum,Cout);
initial
begin
$dumpfile("qb_tb.vcd");
$dumpvars(0,qb_tb);

x1=1'b0; y1=1'b0; Cin=1'b0; #20;
x1=1'b0; y1=1'b0; Cin=1'b1; #20;
x1=1'b0; y1=1'b1; Cin=1'b0; #20;
x1=1'b0; y1=1'b1; Cin=1'b1; #20;
x1=1'b1; y1=1'b0; Cin=1'b0; #20;
x1=1'b1; y1=1'b0; Cin=1'b1; #20;
x1=1'b1; y1=1'b1; Cin=1'b0; #20;
x1=1'b1; y1=1'b1; Cin=1'b1; #20;

$display("Test Complete");
end

reg x2,y2,CIn;
wire Sum1,Cout1;
decomposedfulladder dfa(x2,y2,CIn,Sum1,Cout1);
initial
begin
$dumpfile("qb_tb.vcd");
$dumpvars(0,qb_tb);

x2=1'b0; y2=1'b0; CIn=1'b0; #20;
x2=1'b0; y2=1'b0; CIn=1'b1; #20;
x2=1'b0; y2=1'b1; CIn=1'b0; #20;
x2=1'b0; y2=1'b1; CIn=1'b1; #20;
x2=1'b1; y2=1'b0; CIn=1'b0; #20;
x2=1'b1; y2=1'b0; CIn=1'b1; #20;
x2=1'b1; y2=1'b1; CIn=1'b0; #20;
x2=1'b1; y2=1'b1; CIn=1'b1; #20;

$display("Test Complete");
end
endmodule