data/full_repos/permissive/50192283/parity_generator.sv
1: b'%Warning-LITENDIAN: data/full_repos/permissive/50192283/parity_generator.sv:5: Little bit endian vector: MSB < LSB of bit range: 0:63\n  input [0:63] wed,\n        ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/50192283/parity_generator.sv:8: Little bit endian vector: MSB < LSB of bit range: 0:7\n  output reg [0:7]  ah_ctag,         \n             ^\n%Warning-LITENDIAN: data/full_repos/permissive/50192283/parity_generator.sv:10: Little bit endian vector: MSB < LSB of bit range: 0:12\n  output reg [0:12] ah_com,          \n             ^\n%Warning-LITENDIAN: data/full_repos/permissive/50192283/parity_generator.sv:12: Little bit endian vector: MSB < LSB of bit range: 0:2\n  output [0:2]      ah_cabt,         \n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/50192283/parity_generator.sv:13: Little bit endian vector: MSB < LSB of bit range: 0:63\n  output reg [0:63] ah_cea,          \n             ^\n%Warning-LITENDIAN: data/full_repos/permissive/50192283/parity_generator.sv:15: Little bit endian vector: MSB < LSB of bit range: 0:15\n  output [0:15]     ah_cch,          \n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/50192283/parity_generator.sv:16: Little bit endian vector: MSB < LSB of bit range: 0:11\n  output reg [0:11] ah_csize,        \n             ^\n%Warning-LITENDIAN: data/full_repos/permissive/50192283/parity_generator.sv:17: Little bit endian vector: MSB < LSB of bit range: 0:7\n  input  [0:7]      ha_croom,        \n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/50192283/parity_generator.sv:20: Little bit endian vector: MSB < LSB of bit range: 0:7\n  input  [0:7]      ha_brtag,        \n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/50192283/parity_generator.sv:22: Little bit endian vector: MSB < LSB of bit range: 0:5\n  input  [0:5]      ha_brad,         \n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/50192283/parity_generator.sv:23: Little bit endian vector: MSB < LSB of bit range: 0:3\n  output [0:3]      ah_brlat,        \n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/50192283/parity_generator.sv:24: Little bit endian vector: MSB < LSB of bit range: 0:511\n  output [0:511]    ah_brdata,       \n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/50192283/parity_generator.sv:25: Little bit endian vector: MSB < LSB of bit range: 0:7\n  output [0:7]      ah_brpar,        \n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/50192283/parity_generator.sv:27: Little bit endian vector: MSB < LSB of bit range: 0:7\n  input  [0:7]      ha_bwtag,        \n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/50192283/parity_generator.sv:29: Little bit endian vector: MSB < LSB of bit range: 0:5\n  input  [0:5]      ha_bwad,         \n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/50192283/parity_generator.sv:30: Little bit endian vector: MSB < LSB of bit range: 0:511\n  input  [0:511]    ha_bwdata,       \n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/50192283/parity_generator.sv:31: Little bit endian vector: MSB < LSB of bit range: 0:7\n  input  [0:7]      ha_bwpar,        \n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/50192283/parity_generator.sv:34: Little bit endian vector: MSB < LSB of bit range: 0:7\n  input  [0:7]      ha_rtag,         \n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/50192283/parity_generator.sv:36: Little bit endian vector: MSB < LSB of bit range: 0:7\n  input  [0:7]      ha_response,     \n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/50192283/parity_generator.sv:37: Little bit endian vector: MSB < LSB of bit range: 0:8\n  input  [0:8]      ha_rcredits,     \n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/50192283/parity_generator.sv:38: Little bit endian vector: MSB < LSB of bit range: 0:1\n  input  [0:1]      ha_rcachestate,  \n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/50192283/parity_generator.sv:39: Little bit endian vector: MSB < LSB of bit range: 0:12\n  input  [0:12]     ha_rcachepos     \n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/50192283/parity_generator.sv:44: Little bit endian vector: MSB < LSB of bit range: 0:63\n  reg [0:63] buffer_size;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/50192283/parity_generator.sv:45: Little bit endian vector: MSB < LSB of bit range: 0:63\n  reg [0:63] stripe1_addr;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/50192283/parity_generator.sv:46: Little bit endian vector: MSB < LSB of bit range: 0:63\n  reg [0:63] stripe2_addr;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/50192283/parity_generator.sv:47: Little bit endian vector: MSB < LSB of bit range: 0:63\n  reg [0:63] parity_addr;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/50192283/parity_generator.sv:69: Operator ASSIGNDLY expects 13 bits on the Assign RHS, but Assign RHS\'s CONST \'12\'ha00\' generates 12 bits.\n                                                                          : ... In instance parity_generator\n        ah_com <= 12\'h0A00;\n               ^~\n%Error: Exiting due to 27 warning(s)\n'
module parity_generator (
  input clock,
  input enable,
  input reset,
  input [0:63] wed,

  output reg        ah_cvalid,
  output reg [0:7]  ah_ctag,
  output            ah_ctagpar,
  output reg [0:12] ah_com,
  output            ah_compar,
  output [0:2]      ah_cabt,
  output reg [0:63] ah_cea,
  output            ah_ceapar,
  output [0:15]     ah_cch,
  output reg [0:11] ah_csize,
  input  [0:7]      ha_croom,

  input             ha_brvalid,
  input  [0:7]      ha_brtag,
  input             ha_brtagpar,
  input  [0:5]      ha_brad,
  output [0:3]      ah_brlat,
  output [0:511]    ah_brdata,
  output [0:7]      ah_brpar,
  input             ha_bwvalid,
  input  [0:7]      ha_bwtag,
  input             ha_bwtagpar,
  input  [0:5]      ha_bwad,
  input  [0:511]    ha_bwdata,
  input  [0:7]      ha_bwpar,

  input             ha_rvalid,
  input  [0:7]      ha_rtag,
  input             ha_rtagpar,
  input  [0:7]      ha_response,
  input  [0:8]      ha_rcredits,
  input  [0:1]      ha_rcachestate,
  input  [0:12]     ha_rcachepos
  );

  reg wed_requested;
  reg wed_received;
  reg [0:63] buffer_size;
  reg [0:63] stripe1_addr;
  reg [0:63] stripe2_addr;
  reg [0:63] parity_addr;

  assign ah_cabt = 3'b000,
         ah_cch = 0,
         ah_brlat = 1,

         ah_compar = ~^ah_com,
         ah_ceapar = ~^ah_cea,
         ah_ctagpar = ~^ah_ctag;


  always @ (posedge clock)
  begin

    if (reset) begin
      ah_cvalid <= 0;
      wed_requested <= 0;
      wed_received <= 0;
      ah_csize <= 32;

    end else if(enable) begin
      if(!wed_requested) begin
        ah_com <= 12'h0A00;
        ah_ctag <= 8'b11111111;
        ah_cea <= wed;
        ah_cvalid <= 1;
        wed_requested <= 1;
      end else if (wed_requested & !wed_received & ha_bwvalid) begin
        $display("Got WED buffer");

        buffer_size <= {ha_bwdata[48:55], ha_bwdata[56:63],
                        ha_bwdata[32:39], ha_bwdata[40:47],
                        ha_bwdata[16:23], ha_bwdata[24:31],
                        ha_bwdata[8:15], ha_bwdata[0:7]};
        stripe1_addr <= {ha_bwdata[120:127], ha_bwdata[112:119],
                         ha_bwdata[104:111], ha_bwdata[96:103],
                         ha_bwdata[88:95], ha_bwdata[80:87],
                         ha_bwdata[72:79], ha_bwdata[64:71]};
        stripe2_addr <= {ha_bwdata[184:191], ha_bwdata[176:183],
                         ha_bwdata[168:175], ha_bwdata[160:167],
                         ha_bwdata[152:159], ha_bwdata[144:151],
                         ha_bwdata[136:143], ha_bwdata[128:135]};
        parity_addr <= {ha_bwdata[248:255], ha_bwdata[240:247],
                        ha_bwdata[232:239], ha_bwdata[224:231],
                        ha_bwdata[216:223], ha_bwdata[208:215],
                        ha_bwdata[200:207], ha_bwdata[192:199]};
        wed_received <= 1;
        ah_cea <= stripe1_addr;
        ah_cvalid <= 0;
      end else begin
        ah_cvalid <= 0;
      end
    end
  end

endmodule
module parity_generator (
  input clock,
  input enable,
  input reset,
  input [0:63] wed,

  output reg        ah_cvalid,
  output reg [0:7]  ah_ctag,
  output            ah_ctagpar,
  output reg [0:12] ah_com,
  output            ah_compar,
  output [0:2]      ah_cabt,
  output reg [0:63] ah_cea,
  output            ah_ceapar,
  output [0:15]     ah_cch,
  output reg [0:11] ah_csize,
  input  [0:7]      ha_croom,

  input             ha_brvalid,
  input  [0:7]      ha_brtag,
  input             ha_brtagpar,
  input  [0:5]      ha_brad,
  output [0:3]      ah_brlat,
  output [0:511]    ah_brdata,
  output [0:7]      ah_brpar,
  input             ha_bwvalid,
  input  [0:7]      ha_bwtag,
  input             ha_bwtagpar,
  input  [0:5]      ha_bwad,
  input  [0:511]    ha_bwdata,
  input  [0:7]      ha_bwpar,

  input             ha_rvalid,
  input  [0:7]      ha_rtag,
  input             ha_rtagpar,
  input  [0:7]      ha_response,
  input  [0:8]      ha_rcredits,
  input  [0:1]      ha_rcachestate,
  input  [0:12]     ha_rcachepos
  );


  reg wed_requested;
  reg wed_received;
  reg [0:63] buffer_size;
  reg [0:63] stripe1_addr;
  reg [0:63] stripe2_addr;
  reg [0:63] parity_addr;

  assign ah_cabt = 3'b000,
         ah_cch = 0,
         ah_brlat = 1,

         ah_compar = ~^ah_com,
         ah_ceapar = ~^ah_cea,
         ah_ctagpar = ~^ah_ctag;


  always @ (posedge clock)
  begin

    if (reset) begin
      ah_cvalid <= 0;
      wed_requested <= 0;
      wed_received <= 0;
      ah_csize <= 32;

    end else if(enable) begin
      if(!wed_requested) begin
        ah_com <= 12'h0A00;
        ah_ctag <= 8'b11111111;
        ah_cea <= wed;
        ah_cvalid <= 1;
        wed_requested <= 1;
      end else if (wed_requested & !wed_received & ha_bwvalid) begin
        $display("Got WED buffer");

        buffer_size <= {ha_bwdata[48:55], ha_bwdata[56:63],
                        ha_bwdata[32:39], ha_bwdata[40:47],
                        ha_bwdata[16:23], ha_bwdata[24:31],
                        ha_bwdata[8:15], ha_bwdata[0:7]};
        stripe1_addr <= {ha_bwdata[120:127], ha_bwdata[112:119],
                         ha_bwdata[104:111], ha_bwdata[96:103],
                         ha_bwdata[88:95], ha_bwdata[80:87],
                         ha_bwdata[72:79], ha_bwdata[64:71]};
        stripe2_addr <= {ha_bwdata[184:191], ha_bwdata[176:183],
                         ha_bwdata[168:175], ha_bwdata[160:167],
                         ha_bwdata[152:159], ha_bwdata[144:151],
                         ha_bwdata[136:143], ha_bwdata[128:135]};
        parity_addr <= {ha_bwdata[248:255], ha_bwdata[240:247],
                        ha_bwdata[232:239], ha_bwdata[224:231],
                        ha_bwdata[216:223], ha_bwdata[208:215],
                        ha_bwdata[200:207], ha_bwdata[192:199]};
        wed_received <= 1;
        ah_cea <= stripe1_addr;
        ah_cvalid <= 0;
      end else begin
        ah_cvalid <= 0;
      end
    end
  end

endmodule