data/full_repos/permissive/502135797/Lab1_Feb_11_2022/Code/DECO.v
data/verilator_xmls/83367128-0f0d-4dcb-b5cd-a7d37c13b3fe.xml
module DECO(
    input [1:0]in,
    input en,
 
    output [3:0]out
    );
 
 wire in0_neg, in1_neg;

 
 not(in0_neg, in[0]);
 not(in1_neg, in[1]);
 
 
 and(out[0],in1_neg,in0_neg,en);
 and(out[1],in1_neg,in[0],en);  
 and(out[2],in[1],in0_neg,en);  
 and(out[3],in[1],in[0],en); 
   
   
endmodule
module DECO(
    input [1:0]in,
    input en,
 
    output [3:0]out
    );

 
 wire in0_neg, in1_neg;

 
 not(in0_neg, in[0]);
 not(in1_neg, in[1]);
 
 
 and(out[0],in1_neg,in0_neg,en);
 and(out[1],in1_neg,in[0],en);  
 and(out[2],in[1],in0_neg,en);  
 and(out[3],in[1],in[0],en); 
   
   
endmodule