data/full_repos/permissive/50724111/vga/rtl/verilog/img_data.v
data/verilator_xmls/dc3315c4-70d3-4893-84d4-0c153358e808.xml
module img_data (
    output reg [7:0] q,
    input [7:0] d,
    input [18:0] write_address, read_address,
    input we, clk
);
    
    (* ramstyle = "M10K" *)

    reg [7:0] mem [383999:0];
    
    always @ (posedge clk) begin
        if (we)
            mem[write_address] <= d;
        q <= mem[read_address];
    end
    
endmodule
module img_data (
    output reg [7:0] q,
    input [7:0] d,
    input [18:0] write_address, read_address,
    input we, clk
);

    
    (* ramstyle = "M10K" *)

    reg [7:0] mem [383999:0];
    
    always @ (posedge clk) begin
        if (we)
            mem[write_address] <= d;
        q <= mem[read_address];
    end
    
endmodule