data/full_repos/permissive/515133384/Verilog Code for Design part.v
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/515133384/Verilog\n        ... Looked in:\n             data/full_repos/permissive/515133384,data/full_repos/permissive/515133384/data/full_repos/permissive/515133384/Verilog\n             data/full_repos/permissive/515133384,data/full_repos/permissive/515133384/data/full_repos/permissive/515133384/Verilog.v\n             data/full_repos/permissive/515133384,data/full_repos/permissive/515133384/data/full_repos/permissive/515133384/Verilog.sv\n             data/full_repos/permissive/515133384/Verilog\n             data/full_repos/permissive/515133384/Verilog.v\n             data/full_repos/permissive/515133384/Verilog.sv\n             obj_dir/data/full_repos/permissive/515133384/Verilog\n             obj_dir/data/full_repos/permissive/515133384/Verilog.v\n             obj_dir/data/full_repos/permissive/515133384/Verilog.sv\n%Error: Cannot find file containing module: Code\n%Error: Cannot find file containing module: for\n%Error: Cannot find file containing module: Design\n%Error: Cannot find file containing module: part.v\n%Error: Exiting due to 5 error(s)\n'
module mux4x1(I0,I1,I2,I3,S0,S1,out);
  inout [8:0]I0,I1,I2,I3;
  input S0,S1;
  output reg[9:0]out;

    always @ (I0 or I1 or I2 or I3 or S0 or S1)
    begin
      case ({S1,S0})
        2'b00: out<={I0[8],I0};
        2'b01: out<={I1[8],I1};
        2'b10: out<={I2[8],I2};
        2'b11: out<={I3[8],I3};
	endcase
    end
endmodule
module mux4x1(I0,I1,I2,I3,S0,S1,out);

  inout [8:0]I0,I1,I2,I3;
  input S0,S1;
  output reg[9:0]out;

    always @ (I0 or I1 or I2 or I3 or S0 or S1)
    begin
      case ({S1,S0})
        2'b00: out<={I0[8],I0};
        2'b01: out<={I1[8],I1};
        2'b10: out<={I2[8],I2};
        2'b11: out<={I3[8],I3};
	endcase
    end
endmodule