data/full_repos/permissive/448204225/src/accelerator/xcel_naive.v
1: b'%Error: data/full_repos/permissive/448204225/src/accelerator/xcel_naive.v:1: Cannot find include file: axi_consts.vh\n`include "axi_consts.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/448204225/src/accelerator,data/full_repos/permissive/448204225/axi_consts.vh\n             data/full_repos/permissive/448204225/src/accelerator,data/full_repos/permissive/448204225/axi_consts.vh.v\n             data/full_repos/permissive/448204225/src/accelerator,data/full_repos/permissive/448204225/axi_consts.vh.sv\n             axi_consts.vh\n             axi_consts.vh.v\n             axi_consts.vh.sv\n             obj_dir/axi_consts.vh\n             obj_dir/axi_consts.vh.v\n             obj_dir/axi_consts.vh.sv\n%Error: data/full_repos/permissive/448204225/src/accelerator/xcel_naive.v:2: Cannot find include file: lenet_consts.vh\n`include "lenet_consts.vh" \n         ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module xcel_naive #(
  parameter AXI_AWIDTH = 32,
  parameter AXI_DWIDTH = 32,
  parameter WT_DIM     = 5
) (
  input clk,
  input rst,



  output                  xcel_read_request_valid,
  input                   xcel_read_request_ready,
  output [AXI_AWIDTH-1:0] xcel_read_addr,
  output [31:0]           xcel_read_len,
  output [2:0]            xcel_read_size,
  output [1:0]            xcel_read_burst,
  input  [AXI_DWIDTH-1:0] xcel_read_data,
  input                   xcel_read_data_valid,
  output                  xcel_read_data_ready,



  output                  xcel_write_request_valid,
  input                   xcel_write_request_ready,
  output [AXI_AWIDTH-1:0] xcel_write_addr,
  output [31:0]           xcel_write_len,
  output [2:0]            xcel_write_size,
  output [1:0]            xcel_write_burst,
  output [AXI_DWIDTH-1:0] xcel_write_data,
  output                  xcel_write_data_valid,
  input                   xcel_write_data_ready,


  input  xcel_start,
  output xcel_done,
  output xcel_idle,

  input [31:0] ifm_ddr_addr,
  input [31:0] wt_ddr_addr,
  input [31:0] ofm_ddr_addr,

  input [31:0] ifm_dim,
  input [31:0] ifm_depth,
  input [31:0] ofm_dim,
  input [31:0] ofm_depth
);

  localparam integer WT_SIZE = WT_DIM * WT_DIM;
  localparam DWIDTH = 8;

  wire [31:0] ifm_size;
  wire [31:0] ifm_len;

  wire [31:0] wt_volume;
  wire [31:0] wt_len;

  wire [31:0] ofm_size;
  wire [31:0] ofm_len;


  REGISTER #(.N(32)) ifm_size_reg (
    .clk(clk),
    .d(ifm_dim * ifm_dim),
    .q(ifm_size)
  );

  REGISTER #(.N(32)) ifm_len_reg (
    .clk(clk),
    .d(ifm_size * ifm_depth),
    .q(ifm_len)
  );

  REGISTER #(.N(32)) wt_volume_reg (
    .clk(clk),
    .d(WT_SIZE * ifm_depth),
    .q(wt_volume)
  );

  REGISTER #(.N(32)) wt_len_reg (
    .clk(clk),
    .d(wt_volume * ofm_depth),
    .q(wt_len)
  );

  REGISTER #(.N(32)) ofm_size_reg (
    .clk(clk),
    .d(ofm_dim * ofm_dim),
    .q(ofm_size)
  );

  REGISTER #(.N(32)) ofm_len_reg (
    .clk(clk),
    .d(ofm_size * ofm_depth),
    .q(ofm_len)
  );

  wire [31:0]       wt_addr;
  wire [DWIDTH-1:0] wt_dout;
  wire wt_dout_valid;
  wire wt_dout_ready;

  wire [31:0]       ifm_addr;
  wire [DWIDTH-1:0] ifm_dout;
  wire ifm_dout_valid;
  wire ifm_dout_ready;

  wire [31:0] ofm_addr0;
  wire [31:0] ofm_dout0;
  wire ofm_dout0_valid;
  wire ofm_dout0_ready;

  wire [31:0] ofm_addr1;
  wire [31:0] ofm_din1;
  wire ofm_din1_valid;
  wire ofm_din1_ready;
  wire ofm_we1;

  wire compute_start, compute_done, compute_idle;


  xcel_naive_compute #(
    .DWIDTH(DWIDTH),
    .WT_DIM(WT_DIM)
  ) compute_unit (
    .clk(clk),
    .rst(rst),


    .ifm_addr(ifm_addr),
    .ifm_dout(ifm_dout),
    .ifm_dout_valid(ifm_dout_valid),
    .ifm_dout_ready(ifm_dout_ready),


    .wt_addr(wt_addr),
    .wt_dout(wt_dout),
    .wt_dout_valid(wt_dout_valid),
    .wt_dout_ready(wt_dout_ready),


    .ofm_addr0(ofm_addr0),
    .ofm_dout0(ofm_dout0),
    .ofm_dout0_valid(ofm_dout0_valid),
    .ofm_dout0_ready(ofm_dout0_ready),


    .ofm_addr1(ofm_addr1),
    .ofm_din1(ofm_din1),
    .ofm_din1_valid(ofm_din1_valid),
    .ofm_din1_ready(ofm_din1_ready),
    .ofm_we1(ofm_we1),


    .compute_start(compute_start),
    .compute_idle(compute_idle),
    .compute_done(compute_done),


    .ifm_dim(ifm_dim),
    .ifm_size(ifm_size),
    .ifm_depth(ifm_depth),
    .ifm_len(ifm_len),

    .wt_volume(wt_volume),
    .wt_len(wt_len),

    .ofm_dim(ofm_dim),
    .ofm_size(ofm_size),
    .ofm_depth(ofm_depth),
    .ofm_len(ofm_len)
  );


  xcel_naive_memif #(
    .AXI_AWIDTH(AXI_AWIDTH),
    .AXI_DWIDTH(AXI_DWIDTH),
    .WT_DIM(WT_DIM)
  ) memif_unit (
    .clk(clk),
    .rst(rst),


    .xcel_read_request_valid(xcel_read_request_valid),
    .xcel_read_request_ready(xcel_read_request_ready),
    .xcel_read_addr(xcel_read_addr),
    .xcel_read_len(xcel_read_len),
    .xcel_read_size(xcel_read_size),
    .xcel_read_burst(xcel_read_burst),
    .xcel_read_data(xcel_read_data),
    .xcel_read_data_valid(xcel_read_data_valid),
    .xcel_read_data_ready(xcel_read_data_ready),


    .xcel_write_request_valid(xcel_write_request_valid),
    .xcel_write_request_ready(xcel_write_request_ready),
    .xcel_write_addr(xcel_write_addr),
    .xcel_write_len(xcel_write_len),
    .xcel_write_size(xcel_write_size),
    .xcel_write_burst(xcel_write_burst),
    .xcel_write_data(xcel_write_data),
    .xcel_write_data_valid(xcel_write_data_valid),
    .xcel_write_data_ready(xcel_write_data_ready),


    .ifm_ddr_addr(ifm_ddr_addr),
    .wt_ddr_addr(wt_ddr_addr),
    .ofm_ddr_addr(ofm_ddr_addr),


    .ifm_addr(ifm_addr),
    .ifm_dout(ifm_dout),
    .ifm_dout_valid(ifm_dout_valid),
    .ifm_dout_ready(ifm_dout_ready),


    .wt_addr(wt_addr),
    .wt_dout(wt_dout),
    .wt_dout_valid(wt_dout_valid),
    .wt_dout_ready(wt_dout_ready),


    .ofm_addr0(ofm_addr0),
    .ofm_dout0(ofm_dout0),
    .ofm_dout0_valid(ofm_dout0_valid),
    .ofm_dout0_ready(ofm_dout0_ready),


    .ofm_addr1(ofm_addr1),
    .ofm_din1(ofm_din1),
    .ofm_din1_valid(ofm_din1_valid),
    .ofm_din1_ready(ofm_din1_ready),
    .ofm_we1(ofm_we1)
  );

  assign compute_start = xcel_start;
  assign xcel_done     = compute_done;
  assign xcel_idle     = compute_idle;

endmodule
module xcel_naive #(
  parameter AXI_AWIDTH = 32,
  parameter AXI_DWIDTH = 32,
  parameter WT_DIM     = 5
) (
  input clk,
  input rst,



  output                  xcel_read_request_valid,
  input                   xcel_read_request_ready,
  output [AXI_AWIDTH-1:0] xcel_read_addr,
  output [31:0]           xcel_read_len,
  output [2:0]            xcel_read_size,
  output [1:0]            xcel_read_burst,
  input  [AXI_DWIDTH-1:0] xcel_read_data,
  input                   xcel_read_data_valid,
  output                  xcel_read_data_ready,



  output                  xcel_write_request_valid,
  input                   xcel_write_request_ready,
  output [AXI_AWIDTH-1:0] xcel_write_addr,
  output [31:0]           xcel_write_len,
  output [2:0]            xcel_write_size,
  output [1:0]            xcel_write_burst,
  output [AXI_DWIDTH-1:0] xcel_write_data,
  output                  xcel_write_data_valid,
  input                   xcel_write_data_ready,


  input  xcel_start,
  output xcel_done,
  output xcel_idle,

  input [31:0] ifm_ddr_addr,
  input [31:0] wt_ddr_addr,
  input [31:0] ofm_ddr_addr,

  input [31:0] ifm_dim,
  input [31:0] ifm_depth,
  input [31:0] ofm_dim,
  input [31:0] ofm_depth
);


  localparam integer WT_SIZE = WT_DIM * WT_DIM;
  localparam DWIDTH = 8;

  wire [31:0] ifm_size;
  wire [31:0] ifm_len;

  wire [31:0] wt_volume;
  wire [31:0] wt_len;

  wire [31:0] ofm_size;
  wire [31:0] ofm_len;


  REGISTER #(.N(32)) ifm_size_reg (
    .clk(clk),
    .d(ifm_dim * ifm_dim),
    .q(ifm_size)
  );

  REGISTER #(.N(32)) ifm_len_reg (
    .clk(clk),
    .d(ifm_size * ifm_depth),
    .q(ifm_len)
  );

  REGISTER #(.N(32)) wt_volume_reg (
    .clk(clk),
    .d(WT_SIZE * ifm_depth),
    .q(wt_volume)
  );

  REGISTER #(.N(32)) wt_len_reg (
    .clk(clk),
    .d(wt_volume * ofm_depth),
    .q(wt_len)
  );

  REGISTER #(.N(32)) ofm_size_reg (
    .clk(clk),
    .d(ofm_dim * ofm_dim),
    .q(ofm_size)
  );

  REGISTER #(.N(32)) ofm_len_reg (
    .clk(clk),
    .d(ofm_size * ofm_depth),
    .q(ofm_len)
  );

  wire [31:0]       wt_addr;
  wire [DWIDTH-1:0] wt_dout;
  wire wt_dout_valid;
  wire wt_dout_ready;

  wire [31:0]       ifm_addr;
  wire [DWIDTH-1:0] ifm_dout;
  wire ifm_dout_valid;
  wire ifm_dout_ready;

  wire [31:0] ofm_addr0;
  wire [31:0] ofm_dout0;
  wire ofm_dout0_valid;
  wire ofm_dout0_ready;

  wire [31:0] ofm_addr1;
  wire [31:0] ofm_din1;
  wire ofm_din1_valid;
  wire ofm_din1_ready;
  wire ofm_we1;

  wire compute_start, compute_done, compute_idle;


  xcel_naive_compute #(
    .DWIDTH(DWIDTH),
    .WT_DIM(WT_DIM)
  ) compute_unit (
    .clk(clk),
    .rst(rst),


    .ifm_addr(ifm_addr),
    .ifm_dout(ifm_dout),
    .ifm_dout_valid(ifm_dout_valid),
    .ifm_dout_ready(ifm_dout_ready),


    .wt_addr(wt_addr),
    .wt_dout(wt_dout),
    .wt_dout_valid(wt_dout_valid),
    .wt_dout_ready(wt_dout_ready),


    .ofm_addr0(ofm_addr0),
    .ofm_dout0(ofm_dout0),
    .ofm_dout0_valid(ofm_dout0_valid),
    .ofm_dout0_ready(ofm_dout0_ready),


    .ofm_addr1(ofm_addr1),
    .ofm_din1(ofm_din1),
    .ofm_din1_valid(ofm_din1_valid),
    .ofm_din1_ready(ofm_din1_ready),
    .ofm_we1(ofm_we1),


    .compute_start(compute_start),
    .compute_idle(compute_idle),
    .compute_done(compute_done),


    .ifm_dim(ifm_dim),
    .ifm_size(ifm_size),
    .ifm_depth(ifm_depth),
    .ifm_len(ifm_len),

    .wt_volume(wt_volume),
    .wt_len(wt_len),

    .ofm_dim(ofm_dim),
    .ofm_size(ofm_size),
    .ofm_depth(ofm_depth),
    .ofm_len(ofm_len)
  );


  xcel_naive_memif #(
    .AXI_AWIDTH(AXI_AWIDTH),
    .AXI_DWIDTH(AXI_DWIDTH),
    .WT_DIM(WT_DIM)
  ) memif_unit (
    .clk(clk),
    .rst(rst),


    .xcel_read_request_valid(xcel_read_request_valid),
    .xcel_read_request_ready(xcel_read_request_ready),
    .xcel_read_addr(xcel_read_addr),
    .xcel_read_len(xcel_read_len),
    .xcel_read_size(xcel_read_size),
    .xcel_read_burst(xcel_read_burst),
    .xcel_read_data(xcel_read_data),
    .xcel_read_data_valid(xcel_read_data_valid),
    .xcel_read_data_ready(xcel_read_data_ready),


    .xcel_write_request_valid(xcel_write_request_valid),
    .xcel_write_request_ready(xcel_write_request_ready),
    .xcel_write_addr(xcel_write_addr),
    .xcel_write_len(xcel_write_len),
    .xcel_write_size(xcel_write_size),
    .xcel_write_burst(xcel_write_burst),
    .xcel_write_data(xcel_write_data),
    .xcel_write_data_valid(xcel_write_data_valid),
    .xcel_write_data_ready(xcel_write_data_ready),


    .ifm_ddr_addr(ifm_ddr_addr),
    .wt_ddr_addr(wt_ddr_addr),
    .ofm_ddr_addr(ofm_ddr_addr),


    .ifm_addr(ifm_addr),
    .ifm_dout(ifm_dout),
    .ifm_dout_valid(ifm_dout_valid),
    .ifm_dout_ready(ifm_dout_ready),


    .wt_addr(wt_addr),
    .wt_dout(wt_dout),
    .wt_dout_valid(wt_dout_valid),
    .wt_dout_ready(wt_dout_ready),


    .ofm_addr0(ofm_addr0),
    .ofm_dout0(ofm_dout0),
    .ofm_dout0_valid(ofm_dout0_valid),
    .ofm_dout0_ready(ofm_dout0_ready),


    .ofm_addr1(ofm_addr1),
    .ofm_din1(ofm_din1),
    .ofm_din1_valid(ofm_din1_valid),
    .ofm_din1_ready(ofm_din1_ready),
    .ofm_we1(ofm_we1)
  );

  assign compute_start = xcel_start;
  assign xcel_done     = compute_done;
  assign xcel_idle     = compute_idle;

endmodule