data/full_repos/permissive/478063538/OR2_v1.v
data/verilator_xmls/6888b2b1-3d12-4638-82fb-6702c7d76d7b.xml
module OR2_v1 (x, y, z);

	input x, y;
	output z ;
	reg z;
	
	always @ (x or y)
	begin
		if ((x == 0) && (y == 0)) 
			z = 0;
		else 
			z = 1;
	end

endmodule
module OR2_v1 (x, y, z);


	input x, y;
	output z ;
	reg z;
	
	always @ (x or y)
	begin
		if ((x == 0) && (y == 0)) 
			z = 0;
		else 
			z = 1;
	end

endmodule