data/full_repos/permissive/418752214/smart_run/impl/mem_icg_test/cpu_ifupred_mem_test_tb.v
1: b'%Error: data/full_repos/permissive/418752214/smart_run/impl/mem_icg_test/cpu_ifupred_mem_test_tb.v:88: syntax error, unexpected \'@\'\n           @(posedge temp_data_CLK)\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/418752214/smart_run/impl/mem_icg_test/cpu_ifupred_mem_test_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n           #20\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/418752214/smart_run/impl/mem_icg_test/cpu_ifupred_mem_test_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n           #0.1 temp_data_cen_internal  = 1\'b0 ;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/418752214/smart_run/impl/mem_icg_test/cpu_ifupred_mem_test_tb.v:96: Unsupported: Ignoring delay on this delayed statement.\n           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1\'b0}};\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/418752214/smart_run/impl/mem_icg_test/cpu_ifupred_mem_test_tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n           #0.1 temp_data_cen_internal  = 1\'b0;\n           ^\n%Error: data/full_repos/permissive/418752214/smart_run/impl/mem_icg_test/cpu_ifupred_mem_test_tb.v:98: syntax error, unexpected \'@\'\n               @(posedge temp_data_CLK)\n               ^\n%Error: data/full_repos/permissive/418752214/smart_run/impl/mem_icg_test/cpu_ifupred_mem_test_tb.v:102: syntax error, unexpected \'@\'\n               @(posedge temp_data_CLK)\n               ^\n%Error: data/full_repos/permissive/418752214/smart_run/impl/mem_icg_test/cpu_ifupred_mem_test_tb.v:105: syntax error, unexpected \'@\'\n               @(posedge temp_data_CLK)\n               ^\n%Error: data/full_repos/permissive/418752214/smart_run/impl/mem_icg_test/cpu_ifupred_mem_test_tb.v:119: syntax error, unexpected \'#\'\n           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1\'b0}};\n           ^\n%Error: data/full_repos/permissive/418752214/smart_run/impl/mem_icg_test/cpu_ifupred_mem_test_tb.v:124: syntax error, unexpected \'@\'\n               @(posedge temp_data_CLK)\n               ^\n%Error: data/full_repos/permissive/418752214/smart_run/impl/mem_icg_test/cpu_ifupred_mem_test_tb.v:147: syntax error, unexpected \'@\'\n                 @(posedge temp_data_CLK)\n                 ^\n%Error: data/full_repos/permissive/418752214/smart_run/impl/mem_icg_test/cpu_ifupred_mem_test_tb.v:161: syntax error, unexpected $display\n                      $display("$  Sorry, temp_data_q_internal = %h , golden_data =%h, wen=%h \\n",temp_data_q_internal,golden_data,temp_data_wen_internal);    \n                      ^~~~~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/impl/mem_icg_test/cpu_ifupred_mem_test_tb.v:171: syntax error, unexpected \'@\'\n           @(posedge temp_data_CLK)  \n           ^\n%Error: data/full_repos/permissive/418752214/smart_run/impl/mem_icg_test/cpu_ifupred_mem_test_tb.v:176: syntax error, unexpected \'#\'\n           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1\'b0}};\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/418752214/smart_run/impl/mem_icg_test/cpu_ifupred_mem_test_tb.v:295: Unsupported: Ignoring delay on this delayed statement.\n#(10/2)  temp_forever_cpuclk = ~temp_forever_cpuclk;\n^\n%Error: Exiting due to 10 error(s), 5 warning(s)\n'
module cpu_ifupred_mem_test_tb(
ifupred_mem_passed
);
output ifupred_mem_passed;
reg ifupred_mem_passed;





parameter LOCAL_DATA_ADDR_WIDTH  = 16;














`ifdef L1_CACHE_ECC
parameter LOCAL_DATA_DATA_WIDTH = 33;
`else
parameter LOCAL_DATA_DATA_WIDTH = 32;
`endif

parameter LOCAL_DATA_WE_WIDTH   = 1;



reg [ LOCAL_DATA_ADDR_WIDTH-1 : 0 ] temp_data_addr_internal;
reg [ LOCAL_DATA_DATA_WIDTH-1 : 0 ] temp_data_din_internal ;
reg [ LOCAL_DATA_WE_WIDTH  -1 : 0 ] temp_data_wen_internal ;
reg                                 temp_data_CLK          ;
reg                                 temp_data_cen_internal ;
wire [ LOCAL_DATA_DATA_WIDTH-1 : 0] temp_data_q_internal   ;
reg  [ LOCAL_DATA_DATA_WIDTH-1 : 0] golden_data      ;
reg  [ LOCAL_DATA_DATA_WIDTH-1 : 0] data_mask   ;
reg  [ LOCAL_DATA_DATA_WIDTH-1 : 0] data_mask_ff   ;




reg temp_forever_cpuclk      ;
reg temp_external_en         ;
reg temp_pad_yy_test_mode    ;
wire temp_xor_clk            ;
wire [151:0] temp_cmp            ;


integer i;

initial 
begin
ifupred_mem_passed =1'b0;


           temp_data_CLK               = 1'b0; 
           temp_data_cen_internal      = 1'b0; 
           temp_data_wen_internal      = {LOCAL_DATA_WE_WIDTH{1'b1}};
           temp_data_addr_internal     = {LOCAL_DATA_ADDR_WIDTH{1'b0}};
           temp_data_din_internal      = {LOCAL_DATA_DATA_WIDTH{1'b0}};
           golden_data                 = {LOCAL_DATA_DATA_WIDTH{1'b0}};
           data_mask                   = {LOCAL_DATA_DATA_WIDTH{1'b0}};
           #20
           @(posedge temp_data_CLK)



           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b0}};
           #0.1 temp_data_cen_internal  = 1'b0 ;
           for(i=1;i<10;i=i+1)
           begin
           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b0}};
           #0.1 temp_data_cen_internal  = 1'b0;
               @(posedge temp_data_CLK)
                temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
                temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;

               @(posedge temp_data_CLK)
               #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b1}};
                    golden_data             <= temp_data_din_internal ;
               @(posedge temp_data_CLK)
               #0.1   

               if(temp_data_q_internal !== golden_data)
               begin

                   $finish;
               end
           end





           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b0}};
           #0.1 temp_data_cen_internal  = 1'b1;

           for(i=10;i<15;i=i+1)
           begin
               @(posedge temp_data_CLK)
                temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
                temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
                golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
               @(posedge temp_data_CLK)
               #0.1   

               if(temp_data_q_internal === golden_data)
               begin

                   $finish;
               end
           end






           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b0}};
           #0.1 temp_data_cen_internal  = 1'b0;
          for(i=0;i<LOCAL_DATA_WE_WIDTH ;i=i+1)
          begin
                 @(posedge temp_data_CLK)
                  temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} ;
                  temp_data_wen_internal  <= {LOCAL_DATA_WE_WIDTH{1'b0}} ; 
                  temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b1}} + i;

                  @(posedge temp_data_CLK)
                  #0.1 temp_data_wen_internal  <= {LOCAL_DATA_WE_WIDTH{1'b1}};
                       golden_data             <= temp_data_din_internal ;
                       data_mask_ff            <= data_mask;
                @(posedge temp_data_CLK)
                  #0.3 
                      $display("$  address = %h temp_data_q_internal = %h , golden_data =%h,wen=%h \n",temp_data_addr_internal,temp_data_q_internal,(golden_data &(~data_mask)),temp_data_wen_internal);    
                 if(temp_data_q_internal !==   (golden_data & data_mask_ff))
                 begin
                      $display("$  Sorry, temp_data_q_internal = %h , golden_data =%h, wen=%h \n",temp_data_q_internal,golden_data,temp_data_wen_internal);    
                      $finish;
                 end
           end
            
                      




           @(posedge temp_data_CLK)
           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b0}};
           #0.1 temp_data_cen_internal  = 1'b0;
           for(i=10;i<15;i = i+1)
           begin
           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b0}};
           #0.1 temp_data_cen_internal  = 1'b0;
               @(posedge temp_data_CLK)
                temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i<<3;
                temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
                golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
               @(posedge temp_data_CLK)
               #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b1}};
                    golden_data             <= temp_data_din_internal ;
               @(posedge temp_data_CLK)
               #0.1   

               if(temp_data_q_internal !== golden_data)
               begin

                   $finish;
               end
           end





           @(posedge temp_data_CLK)
           #0.1 temp_data_cen_internal  = 1'b0;
           @(posedge temp_data_CLK)
           temp_data_wen_internal  <= {LOCAL_DATA_WE_WIDTH{1'b0}};
           temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} ;
           temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hbb;
           golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hbb;
           @(posedge temp_data_CLK)
           temp_data_wen_internal  <= {LOCAL_DATA_WE_WIDTH{1'b0}};
           temp_data_addr_internal <= { {7'b1},{(LOCAL_DATA_ADDR_WIDTH-7){1'b0}} } ;
           temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'haa;
           golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'haa;


           @(posedge temp_data_CLK)
           temp_data_wen_internal  <= {LOCAL_DATA_WE_WIDTH{1'b1}};
           temp_data_addr_internal <= { {20'b1},{LOCAL_DATA_ADDR_WIDTH-7{1'b0}} } ;
           temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hff;
           golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'haa;
           @(posedge temp_data_CLK)
           #0.1   
           if(temp_data_q_internal !== golden_data)
           begin

               $finish;
           end


           @(posedge temp_data_CLK)
           temp_data_wen_internal  <= {LOCAL_DATA_WE_WIDTH{1'b1}};
           temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} ;
           temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hff;
           golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hbb;
           @(posedge temp_data_CLK)
           #0.1   
           if(temp_data_q_internal !== golden_data)
           begin

               $finish;
           end



     
           @(posedge temp_data_CLK)
           #0.1 temp_data_cen_internal  = 1'b0;
           @(posedge temp_data_CLK)
           temp_data_wen_internal  <= {LOCAL_DATA_WE_WIDTH{1'b0}};
           temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b1}} ;
           temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b1}} ;
           golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b1}} ;
           @(posedge temp_data_CLK)
           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b1}};
                 golden_data             <= temp_data_din_internal ;
           @(posedge temp_data_CLK)
           #0.1   

           if(temp_data_q_internal !== golden_data)
           begin

               $finish;
           end










           $display("$$$$$$$$  icache  predecd mem Congratuations PASS!!!!!!!!!                     $");   
             #10
             ifupred_mem_passed = 1'b1;


end













always 
#(`CLK_PERIOD/2)  temp_data_CLK = ~temp_data_CLK;


always 
#(`CLK_PERIOD/2)  temp_forever_cpuclk = ~temp_forever_cpuclk;

always @(posedge temp_data_CLK)
begin


data_mask <= {LOCAL_DATA_DATA_WIDTH{!temp_data_wen_internal[0]}};




end 



ct_ifu_icache_predecd_array0 x_way0_smbist_wrap (
  .ifu_icache_index                (  temp_data_addr_internal   ),
  .ifu_icache_predecd_array0_cen_b    (  temp_data_cen_internal    ),
  .ifu_icache_predecd_array0_clk_en   (  1'b1),
  .forever_cpuclk                  (  temp_data_CLK             ),
  .ifu_icache_data_array0_wen_b     ( temp_data_wen_internal),
  .ifu_icache_predecd_array0_din      (  temp_data_din_internal    ),
  .icache_ifu_predecd_array0_dout     (  temp_data_q_internal      ),
  .ifu_icache_predecd_array0_wen_b    (  temp_data_wen_internal    ),
  .cp0_ifu_icg_en              (  1'b0                      ),

  .pad_yy_icg_scan_en                 (   1'b0                     ),
  .cp0_yy_clk_en                       (1'b1)
);


endmodule
module cpu_ifupred_mem_test_tb(
ifupred_mem_passed
);

output ifupred_mem_passed;
reg ifupred_mem_passed;





parameter LOCAL_DATA_ADDR_WIDTH  = 16;














`ifdef L1_CACHE_ECC
parameter LOCAL_DATA_DATA_WIDTH = 33;
`else
parameter LOCAL_DATA_DATA_WIDTH = 32;
`endif

parameter LOCAL_DATA_WE_WIDTH   = 1;



reg [ LOCAL_DATA_ADDR_WIDTH-1 : 0 ] temp_data_addr_internal;
reg [ LOCAL_DATA_DATA_WIDTH-1 : 0 ] temp_data_din_internal ;
reg [ LOCAL_DATA_WE_WIDTH  -1 : 0 ] temp_data_wen_internal ;
reg                                 temp_data_CLK          ;
reg                                 temp_data_cen_internal ;
wire [ LOCAL_DATA_DATA_WIDTH-1 : 0] temp_data_q_internal   ;
reg  [ LOCAL_DATA_DATA_WIDTH-1 : 0] golden_data      ;
reg  [ LOCAL_DATA_DATA_WIDTH-1 : 0] data_mask   ;
reg  [ LOCAL_DATA_DATA_WIDTH-1 : 0] data_mask_ff   ;




reg temp_forever_cpuclk      ;
reg temp_external_en         ;
reg temp_pad_yy_test_mode    ;
wire temp_xor_clk            ;
wire [151:0] temp_cmp            ;


integer i;

initial 
begin
ifupred_mem_passed =1'b0;


           temp_data_CLK               = 1'b0; 
           temp_data_cen_internal      = 1'b0; 
           temp_data_wen_internal      = {LOCAL_DATA_WE_WIDTH{1'b1}};
           temp_data_addr_internal     = {LOCAL_DATA_ADDR_WIDTH{1'b0}};
           temp_data_din_internal      = {LOCAL_DATA_DATA_WIDTH{1'b0}};
           golden_data                 = {LOCAL_DATA_DATA_WIDTH{1'b0}};
           data_mask                   = {LOCAL_DATA_DATA_WIDTH{1'b0}};
           #20
           @(posedge temp_data_CLK)



           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b0}};
           #0.1 temp_data_cen_internal  = 1'b0 ;
           for(i=1;i<10;i=i+1)
           begin
           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b0}};
           #0.1 temp_data_cen_internal  = 1'b0;
               @(posedge temp_data_CLK)
                temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
                temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;

               @(posedge temp_data_CLK)
               #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b1}};
                    golden_data             <= temp_data_din_internal ;
               @(posedge temp_data_CLK)
               #0.1   

               if(temp_data_q_internal !== golden_data)
               begin

                   $finish;
               end
           end





           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b0}};
           #0.1 temp_data_cen_internal  = 1'b1;

           for(i=10;i<15;i=i+1)
           begin
               @(posedge temp_data_CLK)
                temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
                temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
                golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
               @(posedge temp_data_CLK)
               #0.1   

               if(temp_data_q_internal === golden_data)
               begin

                   $finish;
               end
           end






           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b0}};
           #0.1 temp_data_cen_internal  = 1'b0;
          for(i=0;i<LOCAL_DATA_WE_WIDTH ;i=i+1)
          begin
                 @(posedge temp_data_CLK)
                  temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} ;
                  temp_data_wen_internal  <= {LOCAL_DATA_WE_WIDTH{1'b0}} ; 
                  temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b1}} + i;

                  @(posedge temp_data_CLK)
                  #0.1 temp_data_wen_internal  <= {LOCAL_DATA_WE_WIDTH{1'b1}};
                       golden_data             <= temp_data_din_internal ;
                       data_mask_ff            <= data_mask;
                @(posedge temp_data_CLK)
                  #0.3 
                      $display("$  address = %h temp_data_q_internal = %h , golden_data =%h,wen=%h \n",temp_data_addr_internal,temp_data_q_internal,(golden_data &(~data_mask)),temp_data_wen_internal);    
                 if(temp_data_q_internal !==   (golden_data & data_mask_ff))
                 begin
                      $display("$  Sorry, temp_data_q_internal = %h , golden_data =%h, wen=%h \n",temp_data_q_internal,golden_data,temp_data_wen_internal);    
                      $finish;
                 end
           end
            
                      




           @(posedge temp_data_CLK)
           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b0}};
           #0.1 temp_data_cen_internal  = 1'b0;
           for(i=10;i<15;i = i+1)
           begin
           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b0}};
           #0.1 temp_data_cen_internal  = 1'b0;
               @(posedge temp_data_CLK)
                temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i<<3;
                temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
                golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
               @(posedge temp_data_CLK)
               #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b1}};
                    golden_data             <= temp_data_din_internal ;
               @(posedge temp_data_CLK)
               #0.1   

               if(temp_data_q_internal !== golden_data)
               begin

                   $finish;
               end
           end





           @(posedge temp_data_CLK)
           #0.1 temp_data_cen_internal  = 1'b0;
           @(posedge temp_data_CLK)
           temp_data_wen_internal  <= {LOCAL_DATA_WE_WIDTH{1'b0}};
           temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} ;
           temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hbb;
           golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hbb;
           @(posedge temp_data_CLK)
           temp_data_wen_internal  <= {LOCAL_DATA_WE_WIDTH{1'b0}};
           temp_data_addr_internal <= { {7'b1},{(LOCAL_DATA_ADDR_WIDTH-7){1'b0}} } ;
           temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'haa;
           golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'haa;


           @(posedge temp_data_CLK)
           temp_data_wen_internal  <= {LOCAL_DATA_WE_WIDTH{1'b1}};
           temp_data_addr_internal <= { {20'b1},{LOCAL_DATA_ADDR_WIDTH-7{1'b0}} } ;
           temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hff;
           golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'haa;
           @(posedge temp_data_CLK)
           #0.1   
           if(temp_data_q_internal !== golden_data)
           begin

               $finish;
           end


           @(posedge temp_data_CLK)
           temp_data_wen_internal  <= {LOCAL_DATA_WE_WIDTH{1'b1}};
           temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} ;
           temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hff;
           golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hbb;
           @(posedge temp_data_CLK)
           #0.1   
           if(temp_data_q_internal !== golden_data)
           begin

               $finish;
           end



     
           @(posedge temp_data_CLK)
           #0.1 temp_data_cen_internal  = 1'b0;
           @(posedge temp_data_CLK)
           temp_data_wen_internal  <= {LOCAL_DATA_WE_WIDTH{1'b0}};
           temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b1}} ;
           temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b1}} ;
           golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b1}} ;
           @(posedge temp_data_CLK)
           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b1}};
                 golden_data             <= temp_data_din_internal ;
           @(posedge temp_data_CLK)
           #0.1   

           if(temp_data_q_internal !== golden_data)
           begin

               $finish;
           end










           $display("$$$$$$$$  icache  predecd mem Congratuations PASS!!!!!!!!!                     $");   
             #10
             ifupred_mem_passed = 1'b1;


end













always 
#(`CLK_PERIOD/2)  temp_data_CLK = ~temp_data_CLK;


always 
#(`CLK_PERIOD/2)  temp_forever_cpuclk = ~temp_forever_cpuclk;

always @(posedge temp_data_CLK)
begin


data_mask <= {LOCAL_DATA_DATA_WIDTH{!temp_data_wen_internal[0]}};




end 



ct_ifu_icache_predecd_array0 x_way0_smbist_wrap (
  .ifu_icache_index                (  temp_data_addr_internal   ),
  .ifu_icache_predecd_array0_cen_b    (  temp_data_cen_internal    ),
  .ifu_icache_predecd_array0_clk_en   (  1'b1),
  .forever_cpuclk                  (  temp_data_CLK             ),
  .ifu_icache_data_array0_wen_b     ( temp_data_wen_internal),
  .ifu_icache_predecd_array0_din      (  temp_data_din_internal    ),
  .icache_ifu_predecd_array0_dout     (  temp_data_q_internal      ),
  .ifu_icache_predecd_array0_wen_b    (  temp_data_wen_internal    ),
  .cp0_ifu_icg_en              (  1'b0                      ),

  .pad_yy_icg_scan_en                 (   1'b0                     ),
  .cp0_yy_clk_en                       (1'b1)
);


endmodule