data/full_repos/permissive/471766415/src/top.v
1: b'%Error: data/full_repos/permissive/471766415/src/top.v:20: Cannot find file containing module: \'sphere_renderer\'\n    sphere_renderer spb(\n    ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/471766415/src,data/full_repos/permissive/471766415/sphere_renderer\n             data/full_repos/permissive/471766415/src,data/full_repos/permissive/471766415/sphere_renderer.v\n             data/full_repos/permissive/471766415/src,data/full_repos/permissive/471766415/sphere_renderer.sv\n             sphere_renderer\n             sphere_renderer.v\n             sphere_renderer.sv\n             obj_dir/sphere_renderer\n             obj_dir/sphere_renderer.v\n             obj_dir/sphere_renderer.sv\n%Error: data/full_repos/permissive/471766415/src/top.v:31: Cannot find file containing module: \'sphere_renderer\'\n    sphere_renderer spg(\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/471766415/src/top.v:42: Cannot find file containing module: \'sphere_renderer\'\n    sphere_renderer spr(\n    ^~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:62: Operator COND expects 32 or 6 bits on the Conditional True, but Conditional True\'s CONST \'4\'hf\' generates 4 bits.\n                                                                 : ... In instance vga_demo\n    assign sumr = fvalue ? 4\'b1111 : rcol + background[3:0] > 15 ? 15 : rcol + background[3:0];\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:62: Operator ADD expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'rcol\' generates 4 bits.\n                                                                 : ... In instance vga_demo\n    assign sumr = fvalue ? 4\'b1111 : rcol + background[3:0] > 15 ? 15 : rcol + background[3:0];\n                                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:62: Operator ADD expects 32 or 6 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                 : ... In instance vga_demo\n    assign sumr = fvalue ? 4\'b1111 : rcol + background[3:0] > 15 ? 15 : rcol + background[3:0];\n                                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:63: Operator COND expects 32 or 6 bits on the Conditional True, but Conditional True\'s CONST \'4\'hf\' generates 4 bits.\n                                                                 : ... In instance vga_demo\n    assign sumg = fvalue ? 4\'b1111 : gcol + background[7:4] > 15 ? 15 : gcol + background[7:4];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:63: Operator ADD expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'gcol\' generates 4 bits.\n                                                                 : ... In instance vga_demo\n    assign sumg = fvalue ? 4\'b1111 : gcol + background[7:4] > 15 ? 15 : gcol + background[7:4];\n                                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:63: Operator ADD expects 32 or 6 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                 : ... In instance vga_demo\n    assign sumg = fvalue ? 4\'b1111 : gcol + background[7:4] > 15 ? 15 : gcol + background[7:4];\n                                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:64: Operator COND expects 32 or 6 bits on the Conditional True, but Conditional True\'s CONST \'4\'hf\' generates 4 bits.\n                                                                 : ... In instance vga_demo\n    assign sumb = fvalue ? 4\'b1111 : bcol + background[11:8] > 15 ? 15 : bcol + background[11:8];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:64: Operator ADD expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'bcol\' generates 4 bits.\n                                                                 : ... In instance vga_demo\n    assign sumb = fvalue ? 4\'b1111 : bcol + background[11:8] > 15 ? 15 : bcol + background[11:8];\n                                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:64: Operator ADD expects 32 or 6 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                 : ... In instance vga_demo\n    assign sumb = fvalue ? 4\'b1111 : bcol + background[11:8] > 15 ? 15 : bcol + background[11:8];\n                                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:68: Bit extraction of array[80:0] requires 7 bit index, not 10 bits.\n                                                                 : ... In instance vga_demo\n    assign fvalue = (drawing_pixels & fbit) ? !imbus[v_readwire - 10\'d410][10\'d635 - h_readwire] : 1\'b0;\n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:68: Bit extraction of var[161:0] requires 8 bit index, not 10 bits.\n                                                                 : ... In instance vga_demo\n    assign fvalue = (drawing_pixels & fbit) ? !imbus[v_readwire - 10\'d410][10\'d635 - h_readwire] : 1\'b0;\n                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:72: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffffffffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                 : ... In instance vga_demo\n    assign imbus[0] = 160\'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:73: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffffffffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                 : ... In instance vga_demo\n    assign imbus[1] = 160\'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:74: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffffffffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                 : ... In instance vga_demo\n    assign imbus[2] = 160\'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:75: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffffffffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                 : ... In instance vga_demo\n    assign imbus[3] = 160\'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:76: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffffffffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                 : ... In instance vga_demo\n    assign imbus[4] = 160\'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:77: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffffffffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                 : ... In instance vga_demo\n    assign imbus[5] = 160\'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:78: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffffffffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                 : ... In instance vga_demo\n    assign imbus[6] = 160\'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:79: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffffffffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                 : ... In instance vga_demo\n    assign imbus[7] = 160\'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:80: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffffffffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                 : ... In instance vga_demo\n    assign imbus[8] = 160\'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:81: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffffffffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                 : ... In instance vga_demo\n    assign imbus[9] = 160\'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:82: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffffffffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                 : ... In instance vga_demo\n    assign imbus[10] = 160\'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:83: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffffffffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                 : ... In instance vga_demo\n    assign imbus[11] = 160\'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:84: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffffffffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                 : ... In instance vga_demo\n    assign imbus[12] = 160\'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:85: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffffffffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                 : ... In instance vga_demo\n    assign imbus[13] = 160\'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:86: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffffffffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                 : ... In instance vga_demo\n    assign imbus[14] = 160\'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:87: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffffffffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                 : ... In instance vga_demo\n    assign imbus[15] = 160\'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:88: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffffffffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                 : ... In instance vga_demo\n    assign imbus[16] = 160\'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:89: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffffffffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                 : ... In instance vga_demo\n    assign imbus[17] = 160\'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:90: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffffffffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                 : ... In instance vga_demo\n    assign imbus[18] = 160\'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:91: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffffffffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                 : ... In instance vga_demo\n    assign imbus[19] = 160\'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:92: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffffffffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                 : ... In instance vga_demo\n    assign imbus[20] = 160\'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:93: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffffffffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                 : ... In instance vga_demo\n    assign imbus[21] = 160\'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:94: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffc00fffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                 : ... In instance vga_demo\n    assign imbus[22] = 160\'b1111111111111111111111111100000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:95: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hfffffe0001ffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                 : ... In instance vga_demo\n    assign imbus[23] = 160\'b1111111111111111111111100000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:96: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hfffff000003fffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                 : ... In instance vga_demo\n    assign imbus[24] = 160\'b1111111111111111111100000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:97: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffc000000fffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                 : ... In instance vga_demo\n    assign imbus[25] = 160\'b1111111111111111110000000000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:98: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffff80000007ffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                 : ... In instance vga_demo\n    assign imbus[26] = 160\'b1111111111111111100000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:99: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffff00000003fffffffffc0039ffcfffffffffff\' generates 160 bits.\n                                                                 : ... In instance vga_demo\n    assign imbus[27] = 160\'b1111111111111111000000000000000000000000000000111111111111111111111111111111111111111100000000000011100111111111110011111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:100: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hfffc00000000ffffff01fc0039ffcfffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[28] = 160\'b1111111111111100000000000000000000000000000000001111111111111111111111110000000111111100000000000011100111111111110011111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:101: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hfff8007ff0007ffffc007ffc79ffffffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[29] = 160\'b1111111111111000000000000111111111110000000000000111111111111111111111000000000001111111111111000111100111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:102: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hfff801fffe007ffff8783ffcf9ffffffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[30] = 160\'b1111111111111000000000011111111111111110000000000111111111111111111110000111100000111111111111001111100111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:103: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hfff007ffff803ffff1ff1ff9f907cf827c0f81ff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[31] = 160\'b1111111111110000000001111111111111111111100000000011111111111111111100011111111100011111111110011111100100000111110011111000001001111100000011111000000111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:104: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffe00fffffc01fffe3ff9ff1f803cf00780700ff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[32] = 160\'b1111111111100000000011111111111111111111110000000001111111111111111000111111111110011111111100011111100000000011110011110000000001111000000001110000000011111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:105: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffc000007fe00fffe7018fe3f863ce1870c31cff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[33] = 160\'b1111111111000000000000000000000001111111111000000000111111111111111001110000000110001111111000111111100001100011110011100001100001110000110000110001110011111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:106: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffc000007e700fffc601cfc7f9f1ce3c71e33fff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[34] = 160\'b1111111111000000000000000000000001111110011100000000111111111111110001100000000111001111110001111111100111110001110011100011110001110001111000110011111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:107: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hff800000fe7807ffce31cfcff9f1ce7e73f30fff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[35] = 160\'b1111111110000000000000000000000011111110011110000000011111111111110011100011000111001111110011111111100111110001110011100111111001110011111100110000111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:108: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hff800000fc7c07ffce79cf9ff9f1ce7e73f381ff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[36] = 160\'b1111111110000000000000000000000011111100011111000000011111111111110011100111100111001111100111111111100111110001110011100111111001110011111100111000000111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:109: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hff80ffc1fc7c07ffce798f1ff9f1ce7e73f3f0ff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[37] = 160\'b1111111110000000111111111100000111111100011111000000011111111111110011100111100110001111000111111111100111110001110011100111111001110011111100111111000011111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:110: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hff01ffc1f87e03ffce301e3ff9f1ce3c71e3fc7f\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[38] = 160\'b1111111100000001111111111100000111111000011111100000001111111111110011100011000000011110001111111111100111110001110011100011110001110001111000111111110001111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:111: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hff01ffc3f83e03ffce003c7ff863ce1870c3387f\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[39] = 160\'b1111111100000001111111111100001111111000001111100000001111111111110011100000000000111100011111111111100001100011110011100001100001110000110000110011100001111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:112: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hff03ff83f03f03ffe7007c003803cf00780700ff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[40] = 160\'b1111111100000011111111111000001111110000001111110000001111111111111001110000000001111100000000000011100000000011110011110000000001111000000001110000000011111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:113: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hfe03ff87f03f01ffe3fffc003907cf827c0f81ff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[41] = 160\'b1111111000000011111111111000011111110000001111110000000111111111111000111111111111111100000000000011100100000111110011111000001001111100000011111000000111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:114: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hfe03ff07e03f01fff1fe7ffffffffffc7fffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[42] = 160\'b1111111000000011111111110000011111100000001111110000000111111111111100011111111001111111111111111111111111111111111111111111110001111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:115: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hfe07ff0fe03f01fff8787fffffffff387fffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[43] = 160\'b1111111000000111111111110000111111100000001111110000000111111111111110000111100001111111111111111111111111111111111111110011100001111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:116: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hfe07fe0fc01f81fffc00ffffffffff00ffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[44] = 160\'b1111111000000111111111100000111111000000000111111000000111111111111111000000000011111111111111111111111111111111111111110000000011111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:117: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hfe07fe1fc21f81fffe03ffffffffff81ffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[45] = 160\'b1111111000000111111111100001111111000010000111111000000111111111111111100000001111111111111111111111111111111111111111111000000111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:118: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hfe07fc1f821f81ffffffffffffffffffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[46] = 160\'b1111111000000111111111000001111110000010000111111000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:119: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hfe07fc3f861f81ffffffffffffffffffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[47] = 160\'b1111111000000111111111000011111110000110000111111000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:120: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hfe07f83f070f81ffffffffffffffffffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[48] = 160\'b1111111000000111111110000011111100000111000011111000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:121: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hfe03f87f0f0f01ffffffffffffffffffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[49] = 160\'b1111111000000011111110000111111100001111000011110000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:122: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hfe03f0720f0f01ffffffffffffffffffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[50] = 160\'b1111111000000011111100000111001000001111000011110000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:123: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hff03f0001f0f03ffe03fc1f80fc07fffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[51] = 160\'b1111111100000011111100000000000000011111000011110000001111111111111000000011111111000001111110000000111111000000011111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:124: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hff03e0000f0f03ffc01f80f007803fffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[52] = 160\'b1111111100000011111000000000000000001111000011110000001111111111110000000001111110000000111100000000011110000000001111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:125: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hff01e000018603ffc70f1871c38e1fffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[53] = 160\'b1111111100000001111000000000000000000001100001100000001111111111110001110000111100011000011100011100001110001110000111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:126: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hff01c000078607ffff8f3c7fe3ff1fffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[54] = 160\'b1111111100000001110000000000000000000111100001100000011111111111111111111000111100111100011111111110001111111111000111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:127: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hff80c0007f8407ffff8e3e7fe3ff1fffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[55] = 160\'b1111111110000000110000000000000001111111100001000000011111111111111111111000111000111110011111111110001111111111000111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:128: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hff80ff86ff8007ffff8e3e3fe3ff1fffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[56] = 160\'b1111111110000000111111111000011011111111100000000000011111111111111111111000111000111110001111111110001111111111000111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:129: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffc07ff8ffc00fffff9e3e3fe7ff3fffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[57] = 160\'b1111111111000000011111111111100011111111110000000000111111111111111111111001111000111110001111111110011111111111001111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:130: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffc03fe0ffc00fffff3e3e3fcffe7fffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[58] = 160\'b1111111111000000001111111110000011111111110000000000111111111111111111110011111000111110001111111100111111111110011111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:131: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffe01fe1ffc01ffffe3e3e3f8ffc7fffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[59] = 160\'b1111111111100000000111111110000111111111110000000001111111111111111111100011111000111110001111111000111111111100011111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:132: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hfff00fc1ffc03ffffc7e3e3f1ff8ffffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[60] = 160\'b1111111111110000000011111100000111111111110000000011111111111111111111000111111000111110001111110001111111111000111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:133: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hfff803c3ff007ffff8fe3e7e3ff1ffffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[61] = 160\'b1111111111111000000000111100001111111111000000000111111111111111111110001111111000111110011111100011111111110001111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:134: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hfffc0083fc00fffff1ff3c7c7fe3ffffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[62] = 160\'b1111111111111100000000001000001111111100000000001111111111111111111100011111111100111100011111000111111111100011111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:135: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hfffe0007e001ffffe3ff1878ffc7ffffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[63] = 160\'b1111111111111110000000000000011111100000000000011111111111111111111000111111111100011000011110001111111111000111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:136: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffff00000003ffffc00f80f003801fffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[64] = 160\'b1111111111111111000000000000000000000000000000111111111111111111110000000000111110000000111100000000001110000000000111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:137: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffff80000007ffffc00fc1f003801fffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[65] = 160\'b1111111111111111100000000000000000000000000001111111111111111111110000000000111111000001111100000000001110000000000111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:138: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffc000000fffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[66] = 160\'b1111111111111111110000000000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:139: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hfffff000003fffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[67] = 160\'b1111111111111111111100000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:140: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hfffffe0001ffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[68] = 160\'b1111111111111111111111100000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:141: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffc00fffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[69] = 160\'b1111111111111111111111111100000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:142: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffffffffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[70] = 160\'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:143: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffffffffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[71] = 160\'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:144: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffffffffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[72] = 160\'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:145: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffffffffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[73] = 160\'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:146: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffffffffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[74] = 160\'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:147: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffffffffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[75] = 160\'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:148: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffffffffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[76] = 160\'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:149: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffffffffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[77] = 160\'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:150: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffffffffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[78] = 160\'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top.v:151: Operator ASSIGNW expects 162 bits on the Assign RHS, but Assign RHS\'s CONST \'160\'hffffffffffffffffffffffffffffffffffffffff\' generates 160 bits.\n                                                                  : ... In instance vga_demo\n    assign imbus[79] = 160\'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;\n                     ^\n%Error: data/full_repos/permissive/471766415/src/top.v:153: Cannot find file containing module: \'VGAcore\'\n    VGAcore core(\n    ^~~~~~~\n%Error: Exiting due to 4 error(s), 91 warning(s)\n'
module vga_demo(
    input clk,
    input reset,
    output vga_h_sync,
    output vga_v_sync,
    output wire[3:0] vga_r,
    output wire[3:0] vga_g,
    output wire[3:0] vga_b
);

    wire [9:0] h_readwire, v_readwire;
    wire drawing_pixels;
    wire [3:0] rcol;
    wire [3:0] gcol;
    wire [3:0] bcol;
    
    sphere_renderer spb(
        .clk(clk),
        .reset(reset),
        .compr_hrw(h_readwire[9:3]),
        .compr_vrw(v_readwire[9:3]),
        .colorv(rcol),
        .startv(1'b1),
        .starth(1'b1),
        .top(21'd1398100)
    );

    sphere_renderer spg(
        .clk(clk),
        .reset(reset),
        .compr_hrw(h_readwire[9:3]),
        .compr_vrw(v_readwire[9:3]),
        .colorv(gcol),
        .startv(1'b1),
        .starth(1'b0),
        .top(21'd838860)
    );

    sphere_renderer spr(
        .clk(clk),
        .reset(reset),
        .compr_hrw(h_readwire[9:3]),
        .compr_vrw(v_readwire[9:3]),
        .colorv(bcol),
        .startv(1'b0),
        .starth(1'b1),
        .top(21'd1048576)
    );

    wire [11:0] bstream;
    wire [11:0] background;
    wire [11:0] foreground;

    wire [11:0] final_stream;
    wire [5:0] sumr, sumg, sumb;
    wire fbit;
    wire fvalue;
    assign background = 12'b000000000000;
    assign sumr = fvalue ? 4'b1111 : rcol + background[3:0] > 15 ? 15 : rcol + background[3:0];
    assign sumg = fvalue ? 4'b1111 : gcol + background[7:4] > 15 ? 15 : gcol + background[7:4];
    assign sumb = fvalue ? 4'b1111 : bcol + background[11:8] > 15 ? 15 : bcol + background[11:8];
    
    assign fbit = (h_readwire > 10'd475) & (h_readwire < 10'd635) & (v_readwire > 10'd420) &  (v_readwire < 10'd480);
    wire [9:0] imtar;
    assign fvalue = (drawing_pixels & fbit) ? !imbus[v_readwire - 10'd410][10'd635 - h_readwire] : 1'b0;
    
    wire [161:0] imbus [80:0]; 

    assign imbus[0] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[1] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[2] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[3] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[4] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[5] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[6] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[7] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[8] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[9] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[10] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[11] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[12] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[13] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[14] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[15] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[16] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[17] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[18] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[19] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[20] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[21] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[22] = 160'b1111111111111111111111111100000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[23] = 160'b1111111111111111111111100000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[24] = 160'b1111111111111111111100000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[25] = 160'b1111111111111111110000000000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[26] = 160'b1111111111111111100000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[27] = 160'b1111111111111111000000000000000000000000000000111111111111111111111111111111111111111100000000000011100111111111110011111111111111111111111111111111111111111111;
    assign imbus[28] = 160'b1111111111111100000000000000000000000000000000001111111111111111111111110000000111111100000000000011100111111111110011111111111111111111111111111111111111111111;
    assign imbus[29] = 160'b1111111111111000000000000111111111110000000000000111111111111111111111000000000001111111111111000111100111111111111111111111111111111111111111111111111111111111;
    assign imbus[30] = 160'b1111111111111000000000011111111111111110000000000111111111111111111110000111100000111111111111001111100111111111111111111111111111111111111111111111111111111111;
    assign imbus[31] = 160'b1111111111110000000001111111111111111111100000000011111111111111111100011111111100011111111110011111100100000111110011111000001001111100000011111000000111111111;
    assign imbus[32] = 160'b1111111111100000000011111111111111111111110000000001111111111111111000111111111110011111111100011111100000000011110011110000000001111000000001110000000011111111;
    assign imbus[33] = 160'b1111111111000000000000000000000001111111111000000000111111111111111001110000000110001111111000111111100001100011110011100001100001110000110000110001110011111111;
    assign imbus[34] = 160'b1111111111000000000000000000000001111110011100000000111111111111110001100000000111001111110001111111100111110001110011100011110001110001111000110011111111111111;
    assign imbus[35] = 160'b1111111110000000000000000000000011111110011110000000011111111111110011100011000111001111110011111111100111110001110011100111111001110011111100110000111111111111;
    assign imbus[36] = 160'b1111111110000000000000000000000011111100011111000000011111111111110011100111100111001111100111111111100111110001110011100111111001110011111100111000000111111111;
    assign imbus[37] = 160'b1111111110000000111111111100000111111100011111000000011111111111110011100111100110001111000111111111100111110001110011100111111001110011111100111111000011111111;
    assign imbus[38] = 160'b1111111100000001111111111100000111111000011111100000001111111111110011100011000000011110001111111111100111110001110011100011110001110001111000111111110001111111;
    assign imbus[39] = 160'b1111111100000001111111111100001111111000001111100000001111111111110011100000000000111100011111111111100001100011110011100001100001110000110000110011100001111111;
    assign imbus[40] = 160'b1111111100000011111111111000001111110000001111110000001111111111111001110000000001111100000000000011100000000011110011110000000001111000000001110000000011111111;
    assign imbus[41] = 160'b1111111000000011111111111000011111110000001111110000000111111111111000111111111111111100000000000011100100000111110011111000001001111100000011111000000111111111;
    assign imbus[42] = 160'b1111111000000011111111110000011111100000001111110000000111111111111100011111111001111111111111111111111111111111111111111111110001111111111111111111111111111111;
    assign imbus[43] = 160'b1111111000000111111111110000111111100000001111110000000111111111111110000111100001111111111111111111111111111111111111110011100001111111111111111111111111111111;
    assign imbus[44] = 160'b1111111000000111111111100000111111000000000111111000000111111111111111000000000011111111111111111111111111111111111111110000000011111111111111111111111111111111;
    assign imbus[45] = 160'b1111111000000111111111100001111111000010000111111000000111111111111111100000001111111111111111111111111111111111111111111000000111111111111111111111111111111111;
    assign imbus[46] = 160'b1111111000000111111111000001111110000010000111111000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[47] = 160'b1111111000000111111111000011111110000110000111111000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[48] = 160'b1111111000000111111110000011111100000111000011111000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[49] = 160'b1111111000000011111110000111111100001111000011110000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[50] = 160'b1111111000000011111100000111001000001111000011110000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[51] = 160'b1111111100000011111100000000000000011111000011110000001111111111111000000011111111000001111110000000111111000000011111111111111111111111111111111111111111111111;
    assign imbus[52] = 160'b1111111100000011111000000000000000001111000011110000001111111111110000000001111110000000111100000000011110000000001111111111111111111111111111111111111111111111;
    assign imbus[53] = 160'b1111111100000001111000000000000000000001100001100000001111111111110001110000111100011000011100011100001110001110000111111111111111111111111111111111111111111111;
    assign imbus[54] = 160'b1111111100000001110000000000000000000111100001100000011111111111111111111000111100111100011111111110001111111111000111111111111111111111111111111111111111111111;
    assign imbus[55] = 160'b1111111110000000110000000000000001111111100001000000011111111111111111111000111000111110011111111110001111111111000111111111111111111111111111111111111111111111;
    assign imbus[56] = 160'b1111111110000000111111111000011011111111100000000000011111111111111111111000111000111110001111111110001111111111000111111111111111111111111111111111111111111111;
    assign imbus[57] = 160'b1111111111000000011111111111100011111111110000000000111111111111111111111001111000111110001111111110011111111111001111111111111111111111111111111111111111111111;
    assign imbus[58] = 160'b1111111111000000001111111110000011111111110000000000111111111111111111110011111000111110001111111100111111111110011111111111111111111111111111111111111111111111;
    assign imbus[59] = 160'b1111111111100000000111111110000111111111110000000001111111111111111111100011111000111110001111111000111111111100011111111111111111111111111111111111111111111111;
    assign imbus[60] = 160'b1111111111110000000011111100000111111111110000000011111111111111111111000111111000111110001111110001111111111000111111111111111111111111111111111111111111111111;
    assign imbus[61] = 160'b1111111111111000000000111100001111111111000000000111111111111111111110001111111000111110011111100011111111110001111111111111111111111111111111111111111111111111;
    assign imbus[62] = 160'b1111111111111100000000001000001111111100000000001111111111111111111100011111111100111100011111000111111111100011111111111111111111111111111111111111111111111111;
    assign imbus[63] = 160'b1111111111111110000000000000011111100000000000011111111111111111111000111111111100011000011110001111111111000111111111111111111111111111111111111111111111111111;
    assign imbus[64] = 160'b1111111111111111000000000000000000000000000000111111111111111111110000000000111110000000111100000000001110000000000111111111111111111111111111111111111111111111;
    assign imbus[65] = 160'b1111111111111111100000000000000000000000000001111111111111111111110000000000111111000001111100000000001110000000000111111111111111111111111111111111111111111111;
    assign imbus[66] = 160'b1111111111111111110000000000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[67] = 160'b1111111111111111111100000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[68] = 160'b1111111111111111111111100000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[69] = 160'b1111111111111111111111111100000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[70] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[71] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[72] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[73] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[74] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[75] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[76] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[77] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[78] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[79] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;

    VGAcore core(
        .clk_25_175(clk),
        .reset(reset),
        .h_sync(vga_h_sync),
        .v_sync(vga_v_sync),
        .pixstream({sumr[3:0], sumg[3:0], sumb[3:0]}),
        .hreadwire(h_readwire),
        .vreadwire(v_readwire),
        .drawing_pixels(drawing_pixels),
        .r(vga_r),
        .g(vga_g),
        .b(vga_b)
    );
endmodule
module vga_demo(
    input clk,
    input reset,
    output vga_h_sync,
    output vga_v_sync,
    output wire[3:0] vga_r,
    output wire[3:0] vga_g,
    output wire[3:0] vga_b
);


    wire [9:0] h_readwire, v_readwire;
    wire drawing_pixels;
    wire [3:0] rcol;
    wire [3:0] gcol;
    wire [3:0] bcol;
    
    sphere_renderer spb(
        .clk(clk),
        .reset(reset),
        .compr_hrw(h_readwire[9:3]),
        .compr_vrw(v_readwire[9:3]),
        .colorv(rcol),
        .startv(1'b1),
        .starth(1'b1),
        .top(21'd1398100)
    );

    sphere_renderer spg(
        .clk(clk),
        .reset(reset),
        .compr_hrw(h_readwire[9:3]),
        .compr_vrw(v_readwire[9:3]),
        .colorv(gcol),
        .startv(1'b1),
        .starth(1'b0),
        .top(21'd838860)
    );

    sphere_renderer spr(
        .clk(clk),
        .reset(reset),
        .compr_hrw(h_readwire[9:3]),
        .compr_vrw(v_readwire[9:3]),
        .colorv(bcol),
        .startv(1'b0),
        .starth(1'b1),
        .top(21'd1048576)
    );

    wire [11:0] bstream;
    wire [11:0] background;
    wire [11:0] foreground;

    wire [11:0] final_stream;
    wire [5:0] sumr, sumg, sumb;
    wire fbit;
    wire fvalue;
    assign background = 12'b000000000000;
    assign sumr = fvalue ? 4'b1111 : rcol + background[3:0] > 15 ? 15 : rcol + background[3:0];
    assign sumg = fvalue ? 4'b1111 : gcol + background[7:4] > 15 ? 15 : gcol + background[7:4];
    assign sumb = fvalue ? 4'b1111 : bcol + background[11:8] > 15 ? 15 : bcol + background[11:8];
    
    assign fbit = (h_readwire > 10'd475) & (h_readwire < 10'd635) & (v_readwire > 10'd420) &  (v_readwire < 10'd480);
    wire [9:0] imtar;
    assign fvalue = (drawing_pixels & fbit) ? !imbus[v_readwire - 10'd410][10'd635 - h_readwire] : 1'b0;
    
    wire [161:0] imbus [80:0]; 

    assign imbus[0] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[1] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[2] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[3] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[4] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[5] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[6] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[7] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[8] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[9] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[10] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[11] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[12] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[13] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[14] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[15] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[16] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[17] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[18] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[19] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[20] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[21] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[22] = 160'b1111111111111111111111111100000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[23] = 160'b1111111111111111111111100000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[24] = 160'b1111111111111111111100000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[25] = 160'b1111111111111111110000000000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[26] = 160'b1111111111111111100000000000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[27] = 160'b1111111111111111000000000000000000000000000000111111111111111111111111111111111111111100000000000011100111111111110011111111111111111111111111111111111111111111;
    assign imbus[28] = 160'b1111111111111100000000000000000000000000000000001111111111111111111111110000000111111100000000000011100111111111110011111111111111111111111111111111111111111111;
    assign imbus[29] = 160'b1111111111111000000000000111111111110000000000000111111111111111111111000000000001111111111111000111100111111111111111111111111111111111111111111111111111111111;
    assign imbus[30] = 160'b1111111111111000000000011111111111111110000000000111111111111111111110000111100000111111111111001111100111111111111111111111111111111111111111111111111111111111;
    assign imbus[31] = 160'b1111111111110000000001111111111111111111100000000011111111111111111100011111111100011111111110011111100100000111110011111000001001111100000011111000000111111111;
    assign imbus[32] = 160'b1111111111100000000011111111111111111111110000000001111111111111111000111111111110011111111100011111100000000011110011110000000001111000000001110000000011111111;
    assign imbus[33] = 160'b1111111111000000000000000000000001111111111000000000111111111111111001110000000110001111111000111111100001100011110011100001100001110000110000110001110011111111;
    assign imbus[34] = 160'b1111111111000000000000000000000001111110011100000000111111111111110001100000000111001111110001111111100111110001110011100011110001110001111000110011111111111111;
    assign imbus[35] = 160'b1111111110000000000000000000000011111110011110000000011111111111110011100011000111001111110011111111100111110001110011100111111001110011111100110000111111111111;
    assign imbus[36] = 160'b1111111110000000000000000000000011111100011111000000011111111111110011100111100111001111100111111111100111110001110011100111111001110011111100111000000111111111;
    assign imbus[37] = 160'b1111111110000000111111111100000111111100011111000000011111111111110011100111100110001111000111111111100111110001110011100111111001110011111100111111000011111111;
    assign imbus[38] = 160'b1111111100000001111111111100000111111000011111100000001111111111110011100011000000011110001111111111100111110001110011100011110001110001111000111111110001111111;
    assign imbus[39] = 160'b1111111100000001111111111100001111111000001111100000001111111111110011100000000000111100011111111111100001100011110011100001100001110000110000110011100001111111;
    assign imbus[40] = 160'b1111111100000011111111111000001111110000001111110000001111111111111001110000000001111100000000000011100000000011110011110000000001111000000001110000000011111111;
    assign imbus[41] = 160'b1111111000000011111111111000011111110000001111110000000111111111111000111111111111111100000000000011100100000111110011111000001001111100000011111000000111111111;
    assign imbus[42] = 160'b1111111000000011111111110000011111100000001111110000000111111111111100011111111001111111111111111111111111111111111111111111110001111111111111111111111111111111;
    assign imbus[43] = 160'b1111111000000111111111110000111111100000001111110000000111111111111110000111100001111111111111111111111111111111111111110011100001111111111111111111111111111111;
    assign imbus[44] = 160'b1111111000000111111111100000111111000000000111111000000111111111111111000000000011111111111111111111111111111111111111110000000011111111111111111111111111111111;
    assign imbus[45] = 160'b1111111000000111111111100001111111000010000111111000000111111111111111100000001111111111111111111111111111111111111111111000000111111111111111111111111111111111;
    assign imbus[46] = 160'b1111111000000111111111000001111110000010000111111000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[47] = 160'b1111111000000111111111000011111110000110000111111000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[48] = 160'b1111111000000111111110000011111100000111000011111000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[49] = 160'b1111111000000011111110000111111100001111000011110000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[50] = 160'b1111111000000011111100000111001000001111000011110000000111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[51] = 160'b1111111100000011111100000000000000011111000011110000001111111111111000000011111111000001111110000000111111000000011111111111111111111111111111111111111111111111;
    assign imbus[52] = 160'b1111111100000011111000000000000000001111000011110000001111111111110000000001111110000000111100000000011110000000001111111111111111111111111111111111111111111111;
    assign imbus[53] = 160'b1111111100000001111000000000000000000001100001100000001111111111110001110000111100011000011100011100001110001110000111111111111111111111111111111111111111111111;
    assign imbus[54] = 160'b1111111100000001110000000000000000000111100001100000011111111111111111111000111100111100011111111110001111111111000111111111111111111111111111111111111111111111;
    assign imbus[55] = 160'b1111111110000000110000000000000001111111100001000000011111111111111111111000111000111110011111111110001111111111000111111111111111111111111111111111111111111111;
    assign imbus[56] = 160'b1111111110000000111111111000011011111111100000000000011111111111111111111000111000111110001111111110001111111111000111111111111111111111111111111111111111111111;
    assign imbus[57] = 160'b1111111111000000011111111111100011111111110000000000111111111111111111111001111000111110001111111110011111111111001111111111111111111111111111111111111111111111;
    assign imbus[58] = 160'b1111111111000000001111111110000011111111110000000000111111111111111111110011111000111110001111111100111111111110011111111111111111111111111111111111111111111111;
    assign imbus[59] = 160'b1111111111100000000111111110000111111111110000000001111111111111111111100011111000111110001111111000111111111100011111111111111111111111111111111111111111111111;
    assign imbus[60] = 160'b1111111111110000000011111100000111111111110000000011111111111111111111000111111000111110001111110001111111111000111111111111111111111111111111111111111111111111;
    assign imbus[61] = 160'b1111111111111000000000111100001111111111000000000111111111111111111110001111111000111110011111100011111111110001111111111111111111111111111111111111111111111111;
    assign imbus[62] = 160'b1111111111111100000000001000001111111100000000001111111111111111111100011111111100111100011111000111111111100011111111111111111111111111111111111111111111111111;
    assign imbus[63] = 160'b1111111111111110000000000000011111100000000000011111111111111111111000111111111100011000011110001111111111000111111111111111111111111111111111111111111111111111;
    assign imbus[64] = 160'b1111111111111111000000000000000000000000000000111111111111111111110000000000111110000000111100000000001110000000000111111111111111111111111111111111111111111111;
    assign imbus[65] = 160'b1111111111111111100000000000000000000000000001111111111111111111110000000000111111000001111100000000001110000000000111111111111111111111111111111111111111111111;
    assign imbus[66] = 160'b1111111111111111110000000000000000000000000011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[67] = 160'b1111111111111111111100000000000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[68] = 160'b1111111111111111111111100000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[69] = 160'b1111111111111111111111111100000000001111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[70] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[71] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[72] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[73] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[74] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[75] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[76] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[77] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[78] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;
    assign imbus[79] = 160'b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111;

    VGAcore core(
        .clk_25_175(clk),
        .reset(reset),
        .h_sync(vga_h_sync),
        .v_sync(vga_v_sync),
        .pixstream({sumr[3:0], sumg[3:0], sumb[3:0]}),
        .hreadwire(h_readwire),
        .vreadwire(v_readwire),
        .drawing_pixels(drawing_pixels),
        .r(vga_r),
        .g(vga_g),
        .b(vga_b)
    );
endmodule