data/full_repos/permissive/458134463/Modules/mux2x1.v
data/verilator_xmls/cd6feaba-3f59-41c0-ab65-59196e3e3f8c.xml
module mux2x1(input1, input2, select, result);

input input1;
input input2;
input select;

output result;

wire inverse_select;
wire and1_result;
wire and2_result;


not not1(inverse_select, select);
and and1(and1_result, input2, select);
and and2(and2_result, input1, inverse_select);


or or1(result, and1_result, and2_result);

endmodule
module mux2x1(input1, input2, select, result);


input input1;
input input2;
input select;

output result;

wire inverse_select;
wire and1_result;
wire and2_result;


not not1(inverse_select, select);
and and1(and1_result, input2, select);
and and2(and2_result, input1, inverse_select);


or or1(result, and1_result, and2_result);

endmodule