data/full_repos/permissive/42147529/sn74194version1.v
data/verilator_xmls/1cc31e03-8950-48c3-ac49-dfee4c84477c.xml
module SN74194v1(P,Q,DSR,DSL,S1,S0,_MR,CLOCK) ;
parameter	LENGTH = 4;
input			DSR, DSL, S1, S0, _MR, CLOCK;
input	[LENGTH-1:0]	P;
output 	reg [LENGTH-1:0]	Q;
reg	[LENGTH-1:0]	NextQ;




always @ (posedge CLOCK or negedge _MR)
	if(_MR==0)	Q <= 0;
	else	Q<=NextQ;

always@(Q or S1 or S0 or DSR or DSL or P)
	case ({S1,S0})
	0:	NextQ <= Q;
	1:	NextQ <= {Q[LENGTH-2:0],DSR};
	2:	NextQ <= {DSL, Q[LENGTH-1:1]};
	3:	NextQ <= P;
	endcase
endmodule
module SN74194v1(P,Q,DSR,DSL,S1,S0,_MR,CLOCK) ;

parameter	LENGTH = 4;
input			DSR, DSL, S1, S0, _MR, CLOCK;
input	[LENGTH-1:0]	P;
output 	reg [LENGTH-1:0]	Q;
reg	[LENGTH-1:0]	NextQ;




always @ (posedge CLOCK or negedge _MR)
	if(_MR==0)	Q <= 0;
	else	Q<=NextQ;

always@(Q or S1 or S0 or DSR or DSL or P)
	case ({S1,S0})
	0:	NextQ <= Q;
	1:	NextQ <= {Q[LENGTH-2:0],DSR};
	2:	NextQ <= {DSL, Q[LENGTH-1:1]};
	3:	NextQ <= P;
	endcase
endmodule