data/full_repos/permissive/436253691/hardware/testbench/ONEDCONV_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/436253691/hardware/testbench/ONEDCONV_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD/2);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/436253691/hardware/testbench/ONEDCONV_tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD/2);\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/ONEDCONV_tb.v:117: syntax error, unexpected \'@\'\n @(posedge tb_clk)\n ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/ONEDCONV_tb.v:120: syntax error, unexpected \'@\'\n @(posedge tb_clk)\n ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/ONEDCONV_tb.v:124: syntax error, unexpected \'@\'\n @(posedge tb_clk);\n ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/ONEDCONV_tb.v:130: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/ONEDCONV_tb.v:133: syntax error, unexpected \'@\'\n  @(negedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/ONEDCONV_tb.v:136: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/ONEDCONV_tb.v:138: syntax error, unexpected \'@\'\n  @(negedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/ONEDCONV_tb.v:141: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/ONEDCONV_tb.v:143: syntax error, unexpected \'@\'\n  @(negedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/ONEDCONV_tb.v:146: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/ONEDCONV_tb.v:148: syntax error, unexpected \'@\'\n  @(negedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/ONEDCONV_tb.v:151: syntax error, unexpected \'@\'\n  @(posedge tb_clk);\n  ^\n%Error: data/full_repos/permissive/436253691/hardware/testbench/ONEDCONV_tb.v:153: syntax error, unexpected \'@\'\n  @(negedge tb_clk);\n  ^\n%Error: Exiting due to 13 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ONEDCONV_tb();




parameter BITWIDTH_OF_COLUMS=11;
parameter BITWIDTH_IF_ROWS=10;
parameter BITWIDTH_W_ROWS=4;
parameter BITWIDTH_ROW=4;
parameter BITWIDTH_STRIDE=4;
parameter OF_COLUMS=5;
parameter IF_ROWS=6;
parameter W_ROWS=2;
parameter STRIDE=1;
parameter [BITWIDTH_ROW-1:0] ROW=1;
parameter CLK_PERIOD=20;
integer i;


reg tb_clk;
reg tb_reset;
reg tb_flag_Eqcw;
reg tb_flag_Eqst;
reg tb_flag_Eqcif;
reg [BITWIDTH_IF_ROWS-1:0] tb_current_row;
reg [BITWIDTH_OF_COLUMS-1:0] tb_of_colums;
reg [BITWIDTH_IF_ROWS-1:0] tb_if_rows;
reg [BITWIDTH_W_ROWS-1:0] tb_w_rows;
reg [BITWIDTH_STRIDE-1:0] tb_stride;
reg tb_enable;
reg tb_start;


wire tb_set_en;
wire tb_o_en;
wire tb_wptclr;
wire tb_rptclr;



ONEDCONV OneDConv(


.ONEDCONV_Clk(tb_clk),
.ONEDCONV_Reset(tb_reset),
.ONEDCONV_Row(ROW),
.ONEDCONV_Flag_Eqcw(tb_flag_Eqcw),
.ONEDCONV_Flag_Eqst(tb_flag_Eqst),
.ONEDCONV_Flag_Eqcif(tb_flag_Eqcif),
.ONEDCONV_Current_Row(tb_current_row),
.ONEDCONV_Of_Colums(tb_of_colums),
.ONEDCONV_If_Rows(tb_if_rows),
.ONEDCONV_W_Rows(tb_w_rows),
.ONEDCONV_Conv_Stride(tb_stride),
.ONEDCONV_Enable(tb_enable),
.ONEDCONV_Start(tb_start),



.ONEDCONV_Set_En(tb_set_en),
.ONEDCONV_O_En(tb_o_en),
.ONEDCONV_Wptclr(tb_wptclr),
.ONEDCONV_Rptclr(tb_rptclr)


);


always
begin
		tb_clk=1'b1;
		#(CLK_PERIOD/2);
		tb_clk=1'b0;
		#(CLK_PERIOD/2);
end



initial
begin
	
	tb_reset<=0;
	tb_flag_Eqcw<=0;
	tb_flag_Eqst<=0;
	tb_flag_Eqcif<=0;
	tb_current_row<=1;
	tb_of_colums<=OF_COLUMS;
	tb_if_rows<=IF_ROWS;
	tb_w_rows<=W_ROWS;
	tb_stride<=STRIDE;
	tb_enable<=0;
	tb_start<=0;
	
	@(posedge tb_clk)
	tb_enable<=1;
	tb_reset<=1;
	@(posedge tb_clk)
	tb_enable<=0;
	@(posedge tb_clk);
	tb_start<=1;
	@(posedge tb_clk);
	tb_start<=0;
	
	
	for(i=0;i<3;i=i+1) begin
		
		@(posedge tb_clk);
		@(posedge tb_clk);
		tb_flag_Eqcw<=1;
		@(negedge tb_clk);
		tb_flag_Eqcw<=0;
	
		@(posedge tb_clk);
		tb_flag_Eqst<=1;
		@(negedge tb_clk);
		tb_flag_Eqst<=0;
	
		@(posedge tb_clk);
		tb_flag_Eqst<=1;
		@(negedge tb_clk);
		tb_flag_Eqst<=0;
	
		@(posedge tb_clk);
		tb_flag_Eqst<=1;
		@(negedge tb_clk);
		tb_flag_Eqst<=0;
	
		@(posedge tb_clk);
		tb_flag_Eqst<=1;
		@(negedge tb_clk);
		tb_flag_Eqst<=0;
	
	end


	$stop;

end


endmodule
module ONEDCONV_tb();





parameter BITWIDTH_OF_COLUMS=11;
parameter BITWIDTH_IF_ROWS=10;
parameter BITWIDTH_W_ROWS=4;
parameter BITWIDTH_ROW=4;
parameter BITWIDTH_STRIDE=4;
parameter OF_COLUMS=5;
parameter IF_ROWS=6;
parameter W_ROWS=2;
parameter STRIDE=1;
parameter [BITWIDTH_ROW-1:0] ROW=1;
parameter CLK_PERIOD=20;
integer i;


reg tb_clk;
reg tb_reset;
reg tb_flag_Eqcw;
reg tb_flag_Eqst;
reg tb_flag_Eqcif;
reg [BITWIDTH_IF_ROWS-1:0] tb_current_row;
reg [BITWIDTH_OF_COLUMS-1:0] tb_of_colums;
reg [BITWIDTH_IF_ROWS-1:0] tb_if_rows;
reg [BITWIDTH_W_ROWS-1:0] tb_w_rows;
reg [BITWIDTH_STRIDE-1:0] tb_stride;
reg tb_enable;
reg tb_start;


wire tb_set_en;
wire tb_o_en;
wire tb_wptclr;
wire tb_rptclr;



ONEDCONV OneDConv(


.ONEDCONV_Clk(tb_clk),
.ONEDCONV_Reset(tb_reset),
.ONEDCONV_Row(ROW),
.ONEDCONV_Flag_Eqcw(tb_flag_Eqcw),
.ONEDCONV_Flag_Eqst(tb_flag_Eqst),
.ONEDCONV_Flag_Eqcif(tb_flag_Eqcif),
.ONEDCONV_Current_Row(tb_current_row),
.ONEDCONV_Of_Colums(tb_of_colums),
.ONEDCONV_If_Rows(tb_if_rows),
.ONEDCONV_W_Rows(tb_w_rows),
.ONEDCONV_Conv_Stride(tb_stride),
.ONEDCONV_Enable(tb_enable),
.ONEDCONV_Start(tb_start),



.ONEDCONV_Set_En(tb_set_en),
.ONEDCONV_O_En(tb_o_en),
.ONEDCONV_Wptclr(tb_wptclr),
.ONEDCONV_Rptclr(tb_rptclr)


);


always
begin
		tb_clk=1'b1;
		#(CLK_PERIOD/2);
		tb_clk=1'b0;
		#(CLK_PERIOD/2);
end



initial
begin
	
	tb_reset<=0;
	tb_flag_Eqcw<=0;
	tb_flag_Eqst<=0;
	tb_flag_Eqcif<=0;
	tb_current_row<=1;
	tb_of_colums<=OF_COLUMS;
	tb_if_rows<=IF_ROWS;
	tb_w_rows<=W_ROWS;
	tb_stride<=STRIDE;
	tb_enable<=0;
	tb_start<=0;
	
	@(posedge tb_clk)
	tb_enable<=1;
	tb_reset<=1;
	@(posedge tb_clk)
	tb_enable<=0;
	@(posedge tb_clk);
	tb_start<=1;
	@(posedge tb_clk);
	tb_start<=0;
	
	
	for(i=0;i<3;i=i+1) begin
		
		@(posedge tb_clk);
		@(posedge tb_clk);
		tb_flag_Eqcw<=1;
		@(negedge tb_clk);
		tb_flag_Eqcw<=0;
	
		@(posedge tb_clk);
		tb_flag_Eqst<=1;
		@(negedge tb_clk);
		tb_flag_Eqst<=0;
	
		@(posedge tb_clk);
		tb_flag_Eqst<=1;
		@(negedge tb_clk);
		tb_flag_Eqst<=0;
	
		@(posedge tb_clk);
		tb_flag_Eqst<=1;
		@(negedge tb_clk);
		tb_flag_Eqst<=0;
	
		@(posedge tb_clk);
		tb_flag_Eqst<=1;
		@(negedge tb_clk);
		tb_flag_Eqst<=0;
	
	end


	$stop;

end


endmodule