data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv
1: b'%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:22: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n  time tck_src = 10ns;\n                 ^~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:23: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n  time tck_dst = 10ns;\n                 ^~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:46: syntax error, unexpected TIME NUMBER, expecting \')\'\n    cdc_2phase_tb_delay_injector #(0.8ns) i_dut (.*);\n                                   ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:52: syntax error, unexpected \'=\', expecting \',\' or \';\'\n  mailbox #(int) dst_mbox = new();\n                          ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:59: Unsupported: Static in this context\n    static int num_items, num_clks;\n    ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:62: Unsupported: Ignoring delay on this delayed statement.\n    #10ns;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:64: Unsupported: Ignoring delay on this delayed statement.\n    #10ns;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:66: Unsupported: Ignoring delay on this delayed statement.\n    #10ns;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:69: Unsupported: Ignoring delay on this delayed statement.\n      #(tck_src/2);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:71: Unsupported: Ignoring delay on this delayed statement.\n      #(tck_src/2);\n      ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:78: Unsupported or unknown PLI call: $urandom_range\n        tck_src = $urandom_range(1000, 10000) * 1ps;\n                  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:78: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n        tck_src = $urandom_range(1000, 10000) * 1ps;\n                                                ^~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:85: Unsupported: Static in this context\n    static int num_items, num_clks;\n    ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:88: Unsupported: Ignoring delay on this delayed statement.\n    #10ns;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:90: Unsupported: Ignoring delay on this delayed statement.\n    #10ns;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:92: Unsupported: Ignoring delay on this delayed statement.\n    #10ns;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:95: Unsupported: Ignoring delay on this delayed statement.\n      #(tck_dst/2);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:97: Unsupported: Ignoring delay on this delayed statement.\n      #(tck_dst/2);\n      ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:104: Unsupported or unknown PLI call: $urandom_range\n        tck_dst = $urandom_range(1000, 10000) * 1ps;\n                  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:104: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n        tck_dst = $urandom_range(1000, 10000) * 1ps;\n                                                ^~~\n%Warning-STMTDLY: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:112: Unsupported: Ignoring delay on this delayed statement.\n    #(tck_src*0.8);\n    ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:116: syntax error, unexpected \'@\'\n    @(posedge src_clk_i);\n    ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:120: syntax error, unexpected \'@\'\n    @(negedge src_rst_ni);\n    ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:122: syntax error, unexpected \'@\'\n    repeat(3) @(posedge src_clk_i);\n              ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:124: Unsupported: Static in this context\n      static integer stimulus;\n      ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:143: Unsupported: Ignoring delay on this delayed statement.\n    #(tck_dst*0.8);\n    ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:147: syntax error, unexpected \'@\'\n    @(posedge dst_clk_i);\n    ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:151: syntax error, unexpected \'@\'\n    @(negedge dst_rst_ni);\n    ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:153: syntax error, unexpected \'@\'\n    repeat(3) @(posedge dst_clk_i);\n              ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:155: Unsupported: Static in this context\n      static integer expected, actual;\n      ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:156: Unsupported: Static in this context\n      static int cooldown;\n      ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:179: Unsupported or unknown PLI call: $urandom_range\n      cooldown = $urandom_range(0, 40);\n                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:180: syntax error, unexpected \'@\'\n      if (cooldown < 20) repeat(cooldown) @(posedge dst_clk_i);\n                                          ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:199: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n  parameter time MAX_DELAY = 0ns\n                             ^~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:202: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input  logic        src_clk_i,\n  ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:203: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input  logic [31:0] src_data_i,\n  ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:204: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input  logic        src_valid_i,\n  ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:205: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output logic        src_ready_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:207: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input  logic        dst_rst_ni,\n  ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:208: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input  logic        dst_clk_i,\n  ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:209: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output logic [31:0] dst_data_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:210: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n  output logic        dst_valid_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:211: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n  input  logic        dst_ready_i\n  ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:218: syntax error, unexpected always\n  always @(async_req_o) begin\n  ^~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:219: Unsupported or unknown PLI call: $urandom_range\n    automatic time d = $urandom_range(0, MAX_DELAY);\n                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:220: syntax error, unexpected IDENTIFIER\n    async_req_i <= #d async_req_o;\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:224: Unsupported or unknown PLI call: $urandom_range\n    automatic time d = $urandom_range(0, MAX_DELAY);\n                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:225: syntax error, unexpected IDENTIFIER\n    async_ack_i <= #d async_ack_o;\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:230: Unsupported or unknown PLI call: $urandom_range\n      automatic time d = $urandom_range(0, MAX_DELAY);\n                         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:231: syntax error, unexpected IDENTIFIER\n      async_data_i[i] <= #d async_data_o[i];\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:235: syntax error, unexpected \')\', expecting IDENTIFIER or \'=\' or do or final\n  cdc_2phase_src #(logic [31:0]) i_src (\n                               ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/cdc_2phase_tb.sv:246: syntax error, unexpected \')\', expecting IDENTIFIER or \'=\' or do or final\n  cdc_2phase_dst #(logic [31:0]) i_dst (\n                               ^\n%Error: Exiting due to 40 error(s), 12 warning(s)\n'
module cdc_2phase_tb;

  parameter int UNTIL = 100000;
  parameter bit INJECT_DELAYS = 1;
  parameter bit POST_SYNTHESIS = 0;

  time tck_src = 10ns;
  time tck_dst = 10ns;
  bit src_done = 0;
  bit dst_done = 0;
  bit done;
  assign done = src_done & dst_done;


  logic        src_rst_ni  = 1;
  logic        src_clk_i   = 0;
  logic [31:0] src_data_i  = 0;
  logic        src_valid_i = 0;
  logic        src_ready_o;

  logic        dst_rst_ni  = 1;
  logic        dst_clk_i   = 0;
  logic [31:0] dst_data_o;
  logic        dst_valid_o;
  logic        dst_ready_i = 0;


  if (POST_SYNTHESIS) begin : g_dut
    cdc_2phase_synth i_dut (.*);
  end else if (INJECT_DELAYS) begin : g_dut
    cdc_2phase_tb_delay_injector #(0.8ns) i_dut (.*);
  end else begin : g_dut
    cdc_2phase #(logic [31:0]) i_dut (.*);
  end


  mailbox #(int) dst_mbox = new();
  int num_sent = 0;
  int num_received = 0;
  int num_failed = 0;


  initial begin
    static int num_items, num_clks;
    num_items = 10;
    num_clks = 0;
    #10ns;
    src_rst_ni = 0;
    #10ns;
    src_rst_ni = 1;
    #10ns;
    while (!done) begin
      src_clk_i = 1;
      #(tck_src/2);
      src_clk_i = 0;
      #(tck_src/2);


      num_clks++;
      if (num_sent >= num_items && num_clks > 10) begin
        num_items = num_sent + 10;
        num_clks = 0;
        tck_src = $urandom_range(1000, 10000) * 1ps;
        assert(tck_src > 0);
      end
    end
  end

  initial begin
    static int num_items, num_clks;
    num_items = 10;
    num_clks = 0;
    #10ns;
    dst_rst_ni = 0;
    #10ns;
    dst_rst_ni = 1;
    #10ns;
    while (!done) begin
      dst_clk_i = 1;
      #(tck_dst/2);
      dst_clk_i = 0;
      #(tck_dst/2);


      num_clks++;
      if (num_received >= num_items && num_clks > 10) begin
        num_items = num_received + 10;
        num_clks = 0;
        tck_dst = $urandom_range(1000, 10000) * 1ps;
        assert(tck_dst > 0);
      end
    end
  end


  task src_cycle_start;
    #(tck_src*0.8);
  endtask

  task src_cycle_end;
    @(posedge src_clk_i);
  endtask

  initial begin
    @(negedge src_rst_ni);
    @(posedge src_rst_ni);
    repeat(3) @(posedge src_clk_i);
    for (int i = 0; i < UNTIL; i++) begin
      static integer stimulus;
      stimulus = $random();
      src_data_i  <= #(tck_src*0.2) stimulus;
      src_valid_i <= #(tck_src*0.2) 1;
      dst_mbox.put(stimulus);
      num_sent++;
      src_cycle_start();
      while (!src_ready_o) begin
        src_cycle_end();
        src_cycle_start();
      end
      src_cycle_end();
      src_valid_i <= #(tck_src*0.2) 0;
    end
    src_done = 1;
  end


  task dst_cycle_start;
    #(tck_dst*0.8);
  endtask

  task dst_cycle_end;
    @(posedge dst_clk_i);
  endtask

  initial begin
    @(negedge dst_rst_ni);
    @(posedge dst_rst_ni);
    repeat(3) @(posedge dst_clk_i);
    while (!src_done || dst_mbox.num() > 0) begin
      static integer expected, actual;
      static int cooldown;
      dst_ready_i <= #(tck_dst*0.2) 1;
      dst_cycle_start();
      while (!dst_valid_o) begin
        dst_cycle_end();
        dst_cycle_start();
      end
      actual = dst_data_o;
      num_received++;
      if (dst_mbox.num() == 0) begin
        $error("unexpected transaction: data=%0h", actual);
        num_failed++;
      end else begin
        dst_mbox.get(expected);
        if (actual != expected) begin
          $error("transaction mismatch: exp=%0h, act=%0h", expected, actual);
          num_failed++;
        end
      end
      dst_cycle_end();
      dst_ready_i <= #(tck_dst*0.2) 0;


      cooldown = $urandom_range(0, 40);
      if (cooldown < 20) repeat(cooldown) @(posedge dst_clk_i);
    end

    if (num_sent != num_received) begin
      $error("%0d items sent, but %0d items received", num_sent, num_received);
    end
    if (num_failed > 0) begin
      $error("%0d/%0d items mismatched", num_failed, num_sent);
    end else begin
      $info("%0d items passed", num_sent);
    end

    dst_done = 1;
  end

endmodule
module cdc_2phase_tb;


  parameter int UNTIL = 100000;
  parameter bit INJECT_DELAYS = 1;
  parameter bit POST_SYNTHESIS = 0;

  time tck_src = 10ns;
  time tck_dst = 10ns;
  bit src_done = 0;
  bit dst_done = 0;
  bit done;
  assign done = src_done & dst_done;


  logic        src_rst_ni  = 1;
  logic        src_clk_i   = 0;
  logic [31:0] src_data_i  = 0;
  logic        src_valid_i = 0;
  logic        src_ready_o;

  logic        dst_rst_ni  = 1;
  logic        dst_clk_i   = 0;
  logic [31:0] dst_data_o;
  logic        dst_valid_o;
  logic        dst_ready_i = 0;


  if (POST_SYNTHESIS) begin : g_dut
    cdc_2phase_synth i_dut (.*);
  end else if (INJECT_DELAYS) begin : g_dut
    cdc_2phase_tb_delay_injector #(0.8ns) i_dut (.*);
  end else begin : g_dut
    cdc_2phase #(logic [31:0]) i_dut (.*);
  end


  mailbox #(int) dst_mbox = new();
  int num_sent = 0;
  int num_received = 0;
  int num_failed = 0;


  initial begin
    static int num_items, num_clks;
    num_items = 10;
    num_clks = 0;
    #10ns;
    src_rst_ni = 0;
    #10ns;
    src_rst_ni = 1;
    #10ns;
    while (!done) begin
      src_clk_i = 1;
      #(tck_src/2);
      src_clk_i = 0;
      #(tck_src/2);


      num_clks++;
      if (num_sent >= num_items && num_clks > 10) begin
        num_items = num_sent + 10;
        num_clks = 0;
        tck_src = $urandom_range(1000, 10000) * 1ps;
        assert(tck_src > 0);
      end
    end
  end

  initial begin
    static int num_items, num_clks;
    num_items = 10;
    num_clks = 0;
    #10ns;
    dst_rst_ni = 0;
    #10ns;
    dst_rst_ni = 1;
    #10ns;
    while (!done) begin
      dst_clk_i = 1;
      #(tck_dst/2);
      dst_clk_i = 0;
      #(tck_dst/2);


      num_clks++;
      if (num_received >= num_items && num_clks > 10) begin
        num_items = num_received + 10;
        num_clks = 0;
        tck_dst = $urandom_range(1000, 10000) * 1ps;
        assert(tck_dst > 0);
      end
    end
  end


  task src_cycle_start;
    #(tck_src*0.8);
  endtask

  task src_cycle_end;
    @(posedge src_clk_i);
  endtask

  initial begin
    @(negedge src_rst_ni);
    @(posedge src_rst_ni);
    repeat(3) @(posedge src_clk_i);
    for (int i = 0; i < UNTIL; i++) begin
      static integer stimulus;
      stimulus = $random();
      src_data_i  <= #(tck_src*0.2) stimulus;
      src_valid_i <= #(tck_src*0.2) 1;
      dst_mbox.put(stimulus);
      num_sent++;
      src_cycle_start();
      while (!src_ready_o) begin
        src_cycle_end();
        src_cycle_start();
      end
      src_cycle_end();
      src_valid_i <= #(tck_src*0.2) 0;
    end
    src_done = 1;
  end


  task dst_cycle_start;
    #(tck_dst*0.8);
  endtask

  task dst_cycle_end;
    @(posedge dst_clk_i);
  endtask

  initial begin
    @(negedge dst_rst_ni);
    @(posedge dst_rst_ni);
    repeat(3) @(posedge dst_clk_i);
    while (!src_done || dst_mbox.num() > 0) begin
      static integer expected, actual;
      static int cooldown;
      dst_ready_i <= #(tck_dst*0.2) 1;
      dst_cycle_start();
      while (!dst_valid_o) begin
        dst_cycle_end();
        dst_cycle_start();
      end
      actual = dst_data_o;
      num_received++;
      if (dst_mbox.num() == 0) begin
        $error("unexpected transaction: data=%0h", actual);
        num_failed++;
      end else begin
        dst_mbox.get(expected);
        if (actual != expected) begin
          $error("transaction mismatch: exp=%0h, act=%0h", expected, actual);
          num_failed++;
        end
      end
      dst_cycle_end();
      dst_ready_i <= #(tck_dst*0.2) 0;


      cooldown = $urandom_range(0, 40);
      if (cooldown < 20) repeat(cooldown) @(posedge dst_clk_i);
    end

    if (num_sent != num_received) begin
      $error("%0d items sent, but %0d items received", num_sent, num_received);
    end
    if (num_failed > 0) begin
      $error("%0d/%0d items mismatched", num_failed, num_sent);
    end else begin
      $info("%0d items passed", num_sent);
    end

    dst_done = 1;
  end

endmodule