data/full_repos/permissive/441359809/src/yosys/tests/simple/dynslice.v
1: b'%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/dynslice.v:10: Bit extraction of var[127:0] requires 7 bit index, not 10 bits.\n                                                                                         : ... In instance dynslice\n    dout[ctrl*sel+:16] <= din ;\n        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module dynslice (
    input clk ,
    input [9:0] ctrl ,
    input [15:0] din ,
    input [3:0] sel ,
    output reg [127:0] dout
);
always @(posedge clk)
begin
    dout[ctrl*sel+:16] <= din ;
end
endmodule
module dynslice (
    input clk ,
    input [9:0] ctrl ,
    input [15:0] din ,
    input [3:0] sel ,
    output reg [127:0] dout
);

always @(posedge clk)
begin
    dout[ctrl*sel+:16] <= din ;
end
endmodule