data/full_repos/permissive/515471991/UpCounterTB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/515471991/UpCounterTB.v:10: Unsupported: Ignoring delay on this delayed statement.\n          #5 clk=~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/515471991/UpCounterTB.v:14: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Error: data/full_repos/permissive/515471991/UpCounterTB.v:5: Cannot find file containing module: \'up_counter\'\n    up_counter up(clk, reset, counter1);\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/515471991,data/full_repos/permissive/515471991/up_counter\n             data/full_repos/permissive/515471991,data/full_repos/permissive/515471991/up_counter.v\n             data/full_repos/permissive/515471991,data/full_repos/permissive/515471991/up_counter.sv\n             up_counter\n             up_counter.v\n             up_counter.sv\n             obj_dir/up_counter\n             obj_dir/up_counter.v\n             obj_dir/up_counter.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module counter_testbench();
    reg clk, reset;
    wire [3:0] counter1;

    up_counter up(clk, reset, counter1);
      
    initial begin 
        clk=0;
        repeat(96) 
          #5 clk=~clk;
    end
    initial begin
        reset = 1;
        #10
        reset = 0;
    end
endmodule
module counter_testbench();

    reg clk, reset;
    wire [3:0] counter1;

    up_counter up(clk, reset, counter1);
      
    initial begin 
        clk=0;
        repeat(96) 
          #5 clk=~clk;
    end
    initial begin
        reset = 1;
        #10
        reset = 0;
    end
endmodule