data/full_repos/permissive/493019833/test/testcase/firrtl/EqModule/reference/EqModule.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/EqModule/reference/EqModule.v:37: Operator COND expects 10 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                          : ... In instance EqModule.s_pad_1\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/EqModule/reference/EqModule.v:37: Operator COND expects 10 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 2 bits.\n                                                                                                          : ... In instance EqModule.s_pad_3\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Error: Exiting due to 2 warning(s)\n'
module EqModule(
    input clock,
    input reset,
    input [9:0] io_in,
    output [9:0] io_out
);
    wire _T_5;
    wire [9:0] _WTEMP_0;
    PAD_SIGNED #(.width(1), .n(10)) s_pad_1 (
        .y(_WTEMP_0),
        .in(1'sh0)
    );
    EQ_SIGNED #(.width(10)) s_eq_2 (
        .y(_T_5),
        .a(io_in),
        .b(_WTEMP_0)
    );
    wire [9:0] _T_7;
    wire [9:0] _WTEMP_1;
    PAD_SIGNED #(.width(2), .n(10)) s_pad_3 (
        .y(_WTEMP_1),
        .in(2'sh1)
    );
    MUX_SIGNED #(.width(10)) s_mux_4 (
        .y(_T_7),
        .sel(_T_5),
        .a(_WTEMP_1),
        .b(io_in)
    );
    assign io_out = _T_7;
endmodule
module EqModule(
    input clock,
    input reset,
    input [9:0] io_in,
    output [9:0] io_out
);

    wire _T_5;
    wire [9:0] _WTEMP_0;
    PAD_SIGNED #(.width(1), .n(10)) s_pad_1 (
        .y(_WTEMP_0),
        .in(1'sh0)
    );
    EQ_SIGNED #(.width(10)) s_eq_2 (
        .y(_T_5),
        .a(io_in),
        .b(_WTEMP_0)
    );
    wire [9:0] _T_7;
    wire [9:0] _WTEMP_1;
    PAD_SIGNED #(.width(2), .n(10)) s_pad_3 (
        .y(_WTEMP_1),
        .in(2'sh1)
    );
    MUX_SIGNED #(.width(10)) s_mux_4 (
        .y(_T_7),
        .sel(_T_5),
        .a(_WTEMP_1),
        .b(io_in)
    );
    assign io_out = _T_7;
endmodule