data/full_repos/permissive/441359809/src/yosys/tests/various/async.v
data/verilator_xmls/a5bf65b5-92c1-47b0-91a6-3a90bb45edd6.xml
module \$ff #(
	parameter integer WIDTH = 1
) (
	input [WIDTH-1:0] D,
	output reg [WIDTH-1:0] Q
);
	wire sysclk = testbench.sysclk;
	always @(posedge sysclk)
		Q <= D;
endmodule
module \$ff #(
	parameter integer WIDTH = 1
) (
	input [WIDTH-1:0] D,
	output reg [WIDTH-1:0] Q
);

	wire sysclk = testbench.sysclk;
	always @(posedge sysclk)
		Q <= D;
endmodule