data/full_repos/permissive/521565546/src/hex_to_7seg_tb.v
1: b'%Error: data/full_repos/permissive/521565546/src/hex_to_7seg_tb.v:41: Unsupported or unknown PLI call: $monitor\n  $monitor("t=%d a=%h d=%b", $time, a, d);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/521565546/src/hex_to_7seg_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/521565546/src/hex_to_7seg_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n  for(a = 0; a < 16; a=a+1) #100;\n                            ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module hex_to_7seg_tb;


	reg [3:0] a;


	wire [0:7] d;


	hex_to_7seg uut (
		.a(a), 
		.d(d)
	);

	initial begin

		$monitor("t=%d a=%h d=%b", $time, a, d);
		a = 0;


		#100;
        

		for(a = 0; a < 16; a=a+1) #100;
	end
endmodule
module hex_to_7seg_tb;



	reg [3:0] a;


	wire [0:7] d;


	hex_to_7seg uut (
		.a(a), 
		.d(d)
	);

	initial begin

		$monitor("t=%d a=%h d=%b", $time, a, d);
		a = 0;


		#100;
        

		for(a = 0; a < 16; a=a+1) #100;
	end
endmodule