data/full_repos/permissive/439345921/CPU_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #20 rst_n = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:96: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:111: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:129: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:132: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:135: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:138: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:141: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:144: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:147: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:153: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:156: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:159: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:162: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:166: Unsupported: Ignoring delay on this delayed statement.\n  #10 inM     = 16\'d11111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439345921/CPU_tb.v:172: Unsupported: Ignoring delay on this delayed statement.\n always #5 begin\n        ^\n%Error: data/full_repos/permissive/439345921/CPU_tb.v:12: Cannot find file containing module: \'CPU\'\n CPU CPU_inst(\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/439345921,data/full_repos/permissive/439345921/CPU\n             data/full_repos/permissive/439345921,data/full_repos/permissive/439345921/CPU.v\n             data/full_repos/permissive/439345921,data/full_repos/permissive/439345921/CPU.sv\n             CPU\n             CPU.v\n             CPU.sv\n             obj_dir/CPU\n             obj_dir/CPU.v\n             obj_dir/CPU.sv\n%Error: Exiting due to 1 error(s), 47 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module CPU_tb();
	reg clk_cpu;
	reg [15:0] inM;
	reg [15:0] instruction;
	reg rst_n;
	wire [15:0] outM;
	wire writeM;
	wire [14:0] addressM;
	wire [14:0] pc;
	
	CPU CPU_inst(
		.clk_cpu(clk_cpu),
		.inM(inM),
		.instruction(instruction),
		.rst_n(rst_n),
		.outM(outM),
		.writeM(writeM),
		.addressM(addressM),
		.pc(pc)
	);
	
	initial begin
		clk_cpu = 0;
		rst_n = 0;
		inM = 16'd0;
		instruction = 16'd0;
		
		#20 rst_n = 1;
		inM         = 16'd0;
		instruction = 16'b0011000000111001;

		#10 inM     = 16'd0;
		instruction = 16'b1110110000010000;

		#10 inM     = 16'd0;
		instruction = 16'b0101101110100000;

		#10 inM     = 16'd0;
		instruction = 16'b1110000111010000;

		#10 inM     = 16'd0;
		instruction = 16'b0000001111101000;

		#10 inM     = 16'd0;
		instruction = 16'b1110001100001000;

		#10 inM     = 16'd0;
		instruction = 16'b0000001111101001;

		#10 inM     = 16'd0;
		instruction = 16'b1110001110011000;

		#10 inM     = 16'd0;
		instruction = 16'b0000001111101000;

		#10 inM     = 16'd11111;
		instruction = 16'b1111010011010000;

		#10 inM     = 16'd11111;
		instruction = 16'b0000000000001110;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000100;

		#10 inM     = 16'd11111;
		instruction = 16'b0000001111100111;

		#10 inM     = 16'd11111;
		instruction = 16'b1110110111100000;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100001000;

		#10 inM     = 16'd11111;
		instruction = 16'b0000000000010101;

		#10 inM     = 16'd11111;
		instruction = 16'b1110011111000010;

		#10 inM     = 16'd11111;
		instruction = 16'b0000000000000010;

		#10 inM     = 16'd11111;
		instruction = 16'b1110000010010000;

		#10 inM     = 16'd11111;
		instruction = 16'b0000001111101000;

		#10 inM     = 16'd11111;
		instruction = 16'b1110111010010000;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000001;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000010;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000011;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000100;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000101;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000110;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000111;

		#10 inM     = 16'd11111;
		instruction = 16'b1110101010010000;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000001;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000010;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000011;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000100;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000101;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000110;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000111;

		#10 inM     = 16'd11111;
		instruction = 16'b1110111111010000;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000001;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000010;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000011;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000100;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000101;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000110;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000111;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000111;
		rst_n       = 0;

		#10 inM     = 16'd11111;
		instruction = 16'b0111111111111111;
		rst_n       = 1;
		
	end
	
	always #5 begin
		clk_cpu = !clk_cpu;
	end
endmodule
module CPU_tb();

	reg clk_cpu;
	reg [15:0] inM;
	reg [15:0] instruction;
	reg rst_n;
	wire [15:0] outM;
	wire writeM;
	wire [14:0] addressM;
	wire [14:0] pc;
	
	CPU CPU_inst(
		.clk_cpu(clk_cpu),
		.inM(inM),
		.instruction(instruction),
		.rst_n(rst_n),
		.outM(outM),
		.writeM(writeM),
		.addressM(addressM),
		.pc(pc)
	);
	
	initial begin
		clk_cpu = 0;
		rst_n = 0;
		inM = 16'd0;
		instruction = 16'd0;
		
		#20 rst_n = 1;
		inM         = 16'd0;
		instruction = 16'b0011000000111001;

		#10 inM     = 16'd0;
		instruction = 16'b1110110000010000;

		#10 inM     = 16'd0;
		instruction = 16'b0101101110100000;

		#10 inM     = 16'd0;
		instruction = 16'b1110000111010000;

		#10 inM     = 16'd0;
		instruction = 16'b0000001111101000;

		#10 inM     = 16'd0;
		instruction = 16'b1110001100001000;

		#10 inM     = 16'd0;
		instruction = 16'b0000001111101001;

		#10 inM     = 16'd0;
		instruction = 16'b1110001110011000;

		#10 inM     = 16'd0;
		instruction = 16'b0000001111101000;

		#10 inM     = 16'd11111;
		instruction = 16'b1111010011010000;

		#10 inM     = 16'd11111;
		instruction = 16'b0000000000001110;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000100;

		#10 inM     = 16'd11111;
		instruction = 16'b0000001111100111;

		#10 inM     = 16'd11111;
		instruction = 16'b1110110111100000;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100001000;

		#10 inM     = 16'd11111;
		instruction = 16'b0000000000010101;

		#10 inM     = 16'd11111;
		instruction = 16'b1110011111000010;

		#10 inM     = 16'd11111;
		instruction = 16'b0000000000000010;

		#10 inM     = 16'd11111;
		instruction = 16'b1110000010010000;

		#10 inM     = 16'd11111;
		instruction = 16'b0000001111101000;

		#10 inM     = 16'd11111;
		instruction = 16'b1110111010010000;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000001;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000010;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000011;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000100;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000101;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000110;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000111;

		#10 inM     = 16'd11111;
		instruction = 16'b1110101010010000;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000001;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000010;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000011;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000100;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000101;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000110;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000111;

		#10 inM     = 16'd11111;
		instruction = 16'b1110111111010000;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000001;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000010;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000011;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000100;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000101;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000110;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000111;

		#10 inM     = 16'd11111;
		instruction = 16'b1110001100000111;
		rst_n       = 0;

		#10 inM     = 16'd11111;
		instruction = 16'b0111111111111111;
		rst_n       = 1;
		
	end
	
	always #5 begin
		clk_cpu = !clk_cpu;
	end
endmodule