data/full_repos/permissive/452305748/L3/comp_conv/comp_conv_tb.v
1: b'%Error: data/full_repos/permissive/452305748/L3/comp_conv/comp_conv_tb.v:13: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("wave.vcd");         \n        ^~~~~~~~~\n%Error: data/full_repos/permissive/452305748/L3/comp_conv/comp_conv_tb.v:14: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, comp_conv_tb);     \n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/452305748/L3/comp_conv/comp_conv_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #2560   $finish;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/452305748/L3/comp_conv/comp_conv_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\nalways #10 a_in=a_in+1;\n       ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module comp_conv_tb;
reg[7:0] a_in;
wire[7:0] y_out;
comp_conv comp_conv(
    .a(a_in),
    .a_comp(y_out)
);


    initial
    begin
        $dumpfile("wave.vcd");
        $dumpvars(0, comp_conv_tb);
    end


initial begin
            a_in<=0;
    #2560   $finish;
end

always #10 a_in=a_in+1;

endmodule
module comp_conv_tb;

reg[7:0] a_in;
wire[7:0] y_out;
comp_conv comp_conv(
    .a(a_in),
    .a_comp(y_out)
);


    initial
    begin
        $dumpfile("wave.vcd");
        $dumpvars(0, comp_conv_tb);
    end


initial begin
            a_in<=0;
    #2560   $finish;
end

always #10 a_in=a_in+1;

endmodule