data/full_repos/permissive/431682734/LabL/LabL1.v
1: b'%Error: data/full_repos/permissive/431682734/LabL/LabL1.v:2: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n    reg a, b, c, expect;\n                 ^~~~~~\n%Error: data/full_repos/permissive/431682734/LabL/LabL1.v:2: syntax error, unexpected \';\', expecting IDENTIFIER or \'=\' or do or final\n    reg a, b, c, expect;\n                       ^\n%Error: data/full_repos/permissive/431682734/LabL/LabL1.v:18: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n                    expect = (a & ~c) + (b & c);  \n                    ^~~~~~\n%Error: data/full_repos/permissive/431682734/LabL/LabL1.v:18: syntax error, unexpected \'=\'\n                    expect = (a & ~c) + (b & c);  \n                           ^\n%Warning-STMTDLY: data/full_repos/permissive/431682734/LabL/LabL1.v:19: Unsupported: Ignoring delay on this delayed statement.\n                    #1;  \n                    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/431682734/LabL/LabL1.v:22: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n                    if (expect === z)\n                        ^~~~~~\n%Error: data/full_repos/permissive/431682734/LabL/LabL1.v:22: syntax error, unexpected ===, expecting TYPE-IDENTIFIER\n                    if (expect === z)\n                               ^~~\n%Error: Exiting due to 6 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module labL;
    reg a, b, c, expect;
    wire z;
    integer i, j, k;


    yMux1 mine(z, a, b, c);


    initial begin
        for (i = 0; i < 2; i = i + 1)
        begin
            for (j = 0; j < 2; j = j + 1)
            begin
                for (k = 0; k < 2; k = k + 1)
                begin
                    a = i; b = j; c = k;
                    expect = (a & ~c) + (b & c);
                    #1;


                    if (expect === z)
                        $display("PASS: a=%b b=%b c=%b z=%b", a, b, c, z);
                    else
                        $display("FAIL: a=%b b=%b c=%b z=%b", a, b, c, z);
                end
            end
        end
    $finish;
    end
endmodule
module labL;

    reg a, b, c, expect;
    wire z;
    integer i, j, k;


    yMux1 mine(z, a, b, c);


    initial begin
        for (i = 0; i < 2; i = i + 1)
        begin
            for (j = 0; j < 2; j = j + 1)
            begin
                for (k = 0; k < 2; k = k + 1)
                begin
                    a = i; b = j; c = k;
                    expect = (a & ~c) + (b & c);
                    #1;


                    if (expect === z)
                        $display("PASS: a=%b b=%b c=%b z=%b", a, b, c, z);
                    else
                        $display("FAIL: a=%b b=%b c=%b z=%b", a, b, c, z);
                end
            end
        end
    $finish;
    end
endmodule