data/full_repos/permissive/509809169/Circuits/Sequential Logic/Finite State Machines/Simple FSM1(synchronous reset).v
1: b'%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines,data/full_repos/permissive/509809169\n%Error: Cannot find file containing module: data/full_repos/permissive/509809169/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/Simple\n%Error: Cannot find file containing module: FSM1(synchronous\n%Error: Cannot find file containing module: reset).v\n%Error: Exiting due to 7 error(s)\n'
module top_module(clk, reset, in, out);
    input clk;
    input reset;
    input in;
    output out;
    reg out;


    parameter A = 0, B = 1;
    reg present_state, next_state;

    always @(posedge clk) begin
        if (reset) begin  

            present_state <= B;
            out <= 1;
        end else begin
            case (present_state)

                A: next_state = in ? A : B;
                B: next_state = in ? B : A;
            endcase


            present_state = next_state;   

            case (present_state)

                A: out = 0;
                B: out = 1;
            endcase
        end
    end

endmodule
module top_module(clk, reset, in, out);

    input clk;
    input reset;
    input in;
    output out;
    reg out;


    parameter A = 0, B = 1;
    reg present_state, next_state;

    always @(posedge clk) begin
        if (reset) begin  

            present_state <= B;
            out <= 1;
        end else begin
            case (present_state)

                A: next_state = in ? A : B;
                B: next_state = in ? B : A;
            endcase


            present_state = next_state;   

            case (present_state)

                A: out = 0;
                B: out = 1;
            endcase
        end
    end

endmodule