data/full_repos/permissive/506562943/HDLBits/Verilog Language/Modules/module_shift.v
1: b'%Error: Cannot find file containing module: Language/Modules,data/full_repos/permissive/506562943\n        ... Looked in:\n             data/full_repos/permissive/506562943/HDLBits/Verilog/Language/Modules,data/full_repos/permissive/506562943\n             data/full_repos/permissive/506562943/HDLBits/Verilog/Language/Modules,data/full_repos/permissive/506562943.v\n             data/full_repos/permissive/506562943/HDLBits/Verilog/Language/Modules,data/full_repos/permissive/506562943.sv\n             Language/Modules,data/full_repos/permissive/506562943\n             Language/Modules,data/full_repos/permissive/506562943.v\n             Language/Modules,data/full_repos/permissive/506562943.sv\n             obj_dir/Language/Modules,data/full_repos/permissive/506562943\n             obj_dir/Language/Modules,data/full_repos/permissive/506562943.v\n             obj_dir/Language/Modules,data/full_repos/permissive/506562943.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/506562943/HDLBits/Verilog\n%Error: Cannot find file containing module: Language/Modules/module_shift.v\n%Error: Exiting due to 3 error(s)\n'
module top_module ( input clk, input d, output q );


    wire q1, q2;
    

    my_dff u_my_dff_1 (clk, d, q1);
    my_dff u_my_dff_2 (clk, q1, q2);
    my_dff u_my_dff_3 (clk, q2, q);
    
endmodule
module top_module ( input clk, input d, output q );



    wire q1, q2;
    

    my_dff u_my_dff_1 (clk, d, q1);
    my_dff u_my_dff_2 (clk, q1, q2);
    my_dff u_my_dff_3 (clk, q2, q);
    
endmodule