data/full_repos/permissive/406635962/src/tb/tb_gnrl_dffs.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/406635962/src/tb/tb_gnrl_dffs.v:60: Unsupported: Ignoring delay on this delayed statement.\n        #5 rst_n = 0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/406635962/src/tb/tb_gnrl_dffs.v:61: Unsupported: Ignoring delay on this delayed statement.\n     #6 rst_n = 1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/406635962/src/tb/tb_gnrl_dffs.v:62: Unsupported: Ignoring delay on this delayed statement.\n        #5 load_enable = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/406635962/src/tb/tb_gnrl_dffs.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #100 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/406635962/src/tb/tb_gnrl_dffs.v:73: Unsupported: Ignoring delay on this delayed statement.\n            #5 clk = ~clk;\n            ^\n%Error: data/full_repos/permissive/406635962/src/tb/tb_gnrl_dffs.v:19: Cannot find file containing module: \'gnrl_dfflrs\'\n    gnrl_dfflrs#(.DW(32))u_gnrl_dfflrs(\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/406635962/src/tb,data/full_repos/permissive/406635962/gnrl_dfflrs\n             data/full_repos/permissive/406635962/src/tb,data/full_repos/permissive/406635962/gnrl_dfflrs.v\n             data/full_repos/permissive/406635962/src/tb,data/full_repos/permissive/406635962/gnrl_dfflrs.sv\n             gnrl_dfflrs\n             gnrl_dfflrs.v\n             gnrl_dfflrs.sv\n             obj_dir/gnrl_dfflrs\n             obj_dir/gnrl_dfflrs.v\n             obj_dir/gnrl_dfflrs.sv\n%Error: data/full_repos/permissive/406635962/src/tb/tb_gnrl_dffs.v:27: Cannot find file containing module: \'gnrl_dfflr\'\n    gnrl_dfflr#(.DW(32))u_gnrl_dfflr(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/tb/tb_gnrl_dffs.v:35: Cannot find file containing module: \'gnrl_dffl\'\n    gnrl_dffl #(.DW(32))u_gnrl_dffl(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/tb/tb_gnrl_dffs.v:42: Cannot find file containing module: \'gnrl_dffrs\'\n    gnrl_dffrs#(.DW(32))u_gnrl_dffrs(\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/tb/tb_gnrl_dffs.v:49: Cannot find file containing module: \'gnrl_dffr\'\n    gnrl_dffr#(.DW(32))u_gnrl_dffr(\n    ^~~~~~~~~\n%Error: Exiting due to 5 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_gnrl_dffs #(
    parameter DW = 32
);
    reg clk;
    reg rst_n;
    reg[DW-1:0] Q;
    reg load_enable;
    wire[DW-1:0] qout_gnrl_dfflrs;
    wire[DW-1:0] qout_gnrl_dfflr;
    wire[DW-1:0] qout_gnrl_dffl;
    wire[DW-1:0] qout_gnrl_dffrs;
    wire[DW-1:0] qout_gnrl_dffr;
    
    gnrl_dfflrs#(.DW(32))u_gnrl_dfflrs(
        .lden(load_enable),
        .dnxt(Q),
        .qout(qout_gnrl_dfflrs),
        .clk(clk),
        .rst_n(rst_n)
    );

    gnrl_dfflr#(.DW(32))u_gnrl_dfflr(
        .lden(load_enable),
        .dnxt(Q),
        .qout(qout_gnrl_dfflr),
        .clk(clk),
        .rst_n(rst_n)
    );

    gnrl_dffl #(.DW(32))u_gnrl_dffl(
        .lden(load_enable),
        .dnxt(Q),
        .qout(qout_gnrl_dffl),
        .clk(clk)
    );

    gnrl_dffrs#(.DW(32))u_gnrl_dffrs(
        .dnxt(Q),
        .qout(qout_gnrl_dffrs),
        .clk(clk),
        .rst_n(rst_n)
    );

    gnrl_dffr#(.DW(32))u_gnrl_dffr(
        .dnxt(Q),
        .qout(qout_gnrl_dffr),
        .clk(clk),
        .rst_n(rst_n)
    );
    
    initial begin
        load_enable = 0;
	    Q = 0;
	    rst_n = 1;
        #5 rst_n = 0;
	    #6 rst_n = 1;
        #5 load_enable = 1;
        #100 $finish;
    end

    always @(posedge clk ) begin
        Q <= Q +1;
    end

    initial begin
        clk = 1;
        forever begin
            #5 clk = ~clk;
        end
    end

endmodule
module tb_gnrl_dffs #(
    parameter DW = 32
);

    reg clk;
    reg rst_n;
    reg[DW-1:0] Q;
    reg load_enable;
    wire[DW-1:0] qout_gnrl_dfflrs;
    wire[DW-1:0] qout_gnrl_dfflr;
    wire[DW-1:0] qout_gnrl_dffl;
    wire[DW-1:0] qout_gnrl_dffrs;
    wire[DW-1:0] qout_gnrl_dffr;
    
    gnrl_dfflrs#(.DW(32))u_gnrl_dfflrs(
        .lden(load_enable),
        .dnxt(Q),
        .qout(qout_gnrl_dfflrs),
        .clk(clk),
        .rst_n(rst_n)
    );

    gnrl_dfflr#(.DW(32))u_gnrl_dfflr(
        .lden(load_enable),
        .dnxt(Q),
        .qout(qout_gnrl_dfflr),
        .clk(clk),
        .rst_n(rst_n)
    );

    gnrl_dffl #(.DW(32))u_gnrl_dffl(
        .lden(load_enable),
        .dnxt(Q),
        .qout(qout_gnrl_dffl),
        .clk(clk)
    );

    gnrl_dffrs#(.DW(32))u_gnrl_dffrs(
        .dnxt(Q),
        .qout(qout_gnrl_dffrs),
        .clk(clk),
        .rst_n(rst_n)
    );

    gnrl_dffr#(.DW(32))u_gnrl_dffr(
        .dnxt(Q),
        .qout(qout_gnrl_dffr),
        .clk(clk),
        .rst_n(rst_n)
    );
    
    initial begin
        load_enable = 0;
	    Q = 0;
	    rst_n = 1;
        #5 rst_n = 0;
	    #6 rst_n = 1;
        #5 load_enable = 1;
        #100 $finish;
    end

    always @(posedge clk ) begin
        Q <= Q +1;
    end

    initial begin
        clk = 1;
        forever begin
            #5 clk = ~clk;
        end
    end

endmodule