data/full_repos/permissive/463481430/RTL/core/bpu_ap.v
1: b'%Error: data/full_repos/permissive/463481430/RTL/core/bpu_ap.v:27: Cannot find include file: config.v\n`include "config.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463481430/RTL/core,data/full_repos/permissive/463481430/config.v\n             data/full_repos/permissive/463481430/RTL/core,data/full_repos/permissive/463481430/config.v.v\n             data/full_repos/permissive/463481430/RTL/core,data/full_repos/permissive/463481430/config.v.sv\n             config.v\n             config.v.v\n             config.v.sv\n             obj_dir/config.v\n             obj_dir/config.v.v\n             obj_dir/config.v.sv\n%Error: data/full_repos/permissive/463481430/RTL/core/bpu_ap.v:40: Define or directive not defined: \'`xlen_def\'\n    input wire[`xlen_def] i_iaddr, \n               ^~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/bpu_ap.v:40: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire[`xlen_def] i_iaddr, \n                        ^\n%Error: data/full_repos/permissive/463481430/RTL/core/bpu_ap.v:41: Define or directive not defined: \'`ilen_def\'\n                                                                 : ... Suggested alternative: \'`ifndef\'\n    input wire[`ilen_def] i_data, \n               ^~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/bpu_ap.v:44: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire[`xlen_def] o_inst_pc, \n    ^~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/bpu_ap.v:44: Define or directive not defined: \'`xlen_def\'\n    output wire[`xlen_def] o_inst_pc, \n                ^~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/bpu_ap.v:45: Define or directive not defined: \'`ilen_def\'\n                                                                 : ... Suggested alternative: \'`ifndef\'\n    output wire[`ilen_def] o_inst \n                ^~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/bpu_ap.v:52: Define or directive not defined: \'`xlen_def\'\n    reg[`xlen_def] last_iaddr; \n        ^~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/bpu_ap.v:52: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    reg[`xlen_def] last_iaddr; \n                 ^\n%Error: data/full_repos/permissive/463481430/RTL/core/bpu_ap.v:58: syntax error, unexpected always\n    always @(posedge i_clk or negedge i_rstn) begin\n    ^~~~~~\n%Error: Exiting due to 10 error(s)\n'
module BPU_AP (
    input wire i_clk,
    input wire i_rstn,

    input wire i_stop,
    input wire i_flush,

    input wire i_data_vld,
    input wire[`xlen_def] i_iaddr,
    input wire[`ilen_def] i_data,

    output wire o_inst_vld,
    output wire[`xlen_def] o_inst_pc,
    output wire[`ilen_def] o_inst
);


    
    reg[15:0] leftover_buffer;
    reg leftover_ok;
    reg[`xlen_def] last_iaddr;

    wire align16_mode = i_iaddr[1] | leftover_ok;
    


    always @(posedge i_clk or negedge i_rstn) begin
        if(~i_rstn) begin
            leftover_ok <= 0;
        end 
        else if(i_flush)begin
            leftover_ok<=0;
        end
        else if(i_data_vld & (~i_stop)) begin
            last_iaddr<=i_iaddr;
            if(align16_mode)begin
                leftover_ok <= 1;
                leftover_buffer <= i_data[31:16];
            end
            else begin
                leftover_ok<=0;
            end
        end
    end

    assign o_inst_vld = align16_mode ? leftover_ok&i_data_vld : i_data_vld;
    assign o_inst_pc = align16_mode ? last_iaddr : i_iaddr;
    assign o_inst = align16_mode ? {i_data[15:0],leftover_buffer} : i_data;
    
endmodule
module BPU_AP (
    input wire i_clk,
    input wire i_rstn,

    input wire i_stop,
    input wire i_flush,

    input wire i_data_vld,
    input wire[`xlen_def] i_iaddr,
    input wire[`ilen_def] i_data,

    output wire o_inst_vld,
    output wire[`xlen_def] o_inst_pc,
    output wire[`ilen_def] o_inst
);



    
    reg[15:0] leftover_buffer;
    reg leftover_ok;
    reg[`xlen_def] last_iaddr;

    wire align16_mode = i_iaddr[1] | leftover_ok;
    


    always @(posedge i_clk or negedge i_rstn) begin
        if(~i_rstn) begin
            leftover_ok <= 0;
        end 
        else if(i_flush)begin
            leftover_ok<=0;
        end
        else if(i_data_vld & (~i_stop)) begin
            last_iaddr<=i_iaddr;
            if(align16_mode)begin
                leftover_ok <= 1;
                leftover_buffer <= i_data[31:16];
            end
            else begin
                leftover_ok<=0;
            end
        end
    end

    assign o_inst_vld = align16_mode ? leftover_ok&i_data_vld : i_data_vld;
    assign o_inst_pc = align16_mode ? last_iaddr : i_iaddr;
    assign o_inst = align16_mode ? {i_data[15:0],leftover_buffer} : i_data;
    
endmodule