data/full_repos/permissive/423539813/source_files/Data_Memory.v
data/verilator_xmls/bb422564-1789-4bbc-9193-4b7182525201.xml
module Data_Memory(output [31:0] Data_Out, 
input [31:0] Data_In, input [31:0] D_Addr, 
input wr, rst, input clk);
 reg [31:0] Mem [255:0]; 
 integer i;
assign Data_Out=Mem[D_Addr]; 
 always @(posedge clk) begin
 if(rst) begin
 for(i=0;i<256;i=i+1)
 Mem[i]=32'h0;
 end else if (wr) begin
 Mem[D_Addr]<=Data_In;
 end
 end
endmodule
module Data_Memory(output [31:0] Data_Out, 
input [31:0] Data_In, input [31:0] D_Addr, 
input wr, rst, input clk);

 reg [31:0] Mem [255:0]; 
 integer i;
assign Data_Out=Mem[D_Addr]; 
 always @(posedge clk) begin
 if(rst) begin
 for(i=0;i<256;i=i+1)
 Mem[i]=32'h0;
 end else if (wr) begin
 Mem[D_Addr]<=Data_In;
 end
 end
endmodule