data/full_repos/permissive/489576714/rtl/back1/AlphaMissionCore_Back1_sync.sv
1: b"%Error: data/full_repos/permissive/489576714/rtl/back1/AlphaMissionCore_Back1_sync.sv:76: Cannot find file containing module: 'ttl_74273_sync'\n    ttl_74273_sync g2(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(B1SY), .D(vdin_r), .Q(B1Y));  \n    ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489576714/rtl/back1,data/full_repos/permissive/489576714/ttl_74273_sync\n             data/full_repos/permissive/489576714/rtl/back1,data/full_repos/permissive/489576714/ttl_74273_sync.v\n             data/full_repos/permissive/489576714/rtl/back1,data/full_repos/permissive/489576714/ttl_74273_sync.sv\n             ttl_74273_sync\n             ttl_74273_sync.v\n             ttl_74273_sync.sv\n             obj_dir/ttl_74273_sync\n             obj_dir/ttl_74273_sync.v\n             obj_dir/ttl_74273_sync.sv\n%Error: data/full_repos/permissive/489576714/rtl/back1/AlphaMissionCore_Back1_sync.sv:83: Cannot find file containing module: 'ttl_74283_nodly'\n    ttl_74283_nodly c14 (.A({1'b1, B1Y[2:0]}),    .B({1'b1, H2,H1,H0}), .C_in(1'b0),     .Sum({c14_dum3,B1H[2:0]}),           .C_out()        );\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489576714/rtl/back1/AlphaMissionCore_Back1_sync.sv:85: Cannot find file containing module: 'ttl_74283_nodly'\n    ttl_74283_nodly c13 (.A(B1Y[6:3]),            .B(Y[3:0]),           .C_in(1'b0),     .Sum(B1H[6:3]),                      .C_out(c13_cout));\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489576714/rtl/back1/AlphaMissionCore_Back1_sync.sv:86: Cannot find file containing module: 'ttl_74283_nodly'\n    ttl_74283_nodly c12 (.A({2'b11,B1Y8,B1Y[7]}), .B({2'b11, H8,Y[4]}), .C_in(c13_cout), .Sum({c12_dum,B1H[8:7]}),            .C_out()        );\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489576714/rtl/back1/AlphaMissionCore_Back1_sync.sv:95: Cannot find file containing module: 'ttl_74174_sync'\n    ttl_74174_sync d13\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489576714/rtl/back1/AlphaMissionCore_Back1_sync.sv:107: Cannot find file containing module: 'ttl_74174_sync'\n    ttl_74174_sync d12\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489576714/rtl/back1/AlphaMissionCore_Back1_sync.sv:125: Cannot find file containing module: 'ttl_74273_sync'\n    ttl_74273_sync b12(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(B1SX), .D(vdinX_r), .Q(B1X));  \n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489576714/rtl/back1/AlphaMissionCore_Back1_sync.sv:128: Cannot find file containing module: 'ttl_74283_nodly'\n    ttl_74283_nodly a12 (.A(B1X[3:0]),    .B(X[3:0]), .C_in(1'b0),         .Sum(B1V[3:0]), .C_out(a12_cout));\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489576714/rtl/back1/AlphaMissionCore_Back1_sync.sv:130: Cannot find file containing module: 'ttl_74283_nodly'\n    ttl_74283_nodly a11 (.A(B1X[7:4]),    .B(X[7:4]), .C_in(a12_cout),     .Sum(B1V[7:4]), .C_out(a11_cout));\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489576714/rtl/back1/AlphaMissionCore_Back1_sync.sv:139: Cannot find file containing module: 'ttl_74157'\n    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) e12 (.Enable_bar(1'b0), .Select(V_C),\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/489576714/rtl/back1/AlphaMissionCore_Back1_sync.sv:142: Cannot find file containing module: 'ttl_74157'\n    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) e13 (.Enable_bar(1'b0), .Select(V_C),\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/489576714/rtl/back1/AlphaMissionCore_Back1_sync.sv:145: Cannot find file containing module: 'ttl_74157'\n    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) e14 (.Enable_bar(1'b0), .Select(V_C),\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/489576714/rtl/back1/AlphaMissionCore_Back1_sync.sv:148: Cannot find file containing module: 'ttl_74157'\n    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) d2 (.Enable_bar(1'b0), .Select(V_C),\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/489576714/rtl/back1/AlphaMissionCore_Back1_sync.sv:168: Cannot find file containing module: 'SRAM_dual_sync'\n    SRAM_dual_sync #(.ADDR_WIDTH(13)) h12\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489576714/rtl/back1/AlphaMissionCore_Back1_sync.sv:192: Cannot find file containing module: 'ttl_74273_sync'\n    ttl_74273_sync f12(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(VLK), .D(Dreg), .Q(F12_Q));\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489576714/rtl/back1/AlphaMissionCore_Back1_sync.sv:195: Cannot find file containing module: 'ttl_74273_sync'\n    ttl_74273_sync f13(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(LA), .D(F12_Q), .Q(F13_Q));\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489576714/rtl/back1/AlphaMissionCore_Back1_sync.sv:198: Cannot find file containing module: 'ttl_74273_sync'\n    ttl_74273_sync f14(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(B1HQ[2]), .D(F13_Q), .Q(F14_Q));\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489576714/rtl/back1/AlphaMissionCore_Back1_sync.sv:210: Cannot find file containing module: 'eprom_32K'\n    eprom_32K P10_H14\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/489576714/rtl/back1/AlphaMissionCore_Back1_sync.sv:223: Cannot find file containing module: 'ttl_74273_sync'\n    ttl_74273_sync g14(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(B1HQ[0]), .D(H14_D), .Q(G14_Q));\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489576714/rtl/back1/AlphaMissionCore_Back1_sync.sv:227: Cannot find file containing module: 'ttl_74157'\n    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) a2 (.Enable_bar(1'b0), .Select(G14_S),\n    ^~~~~~~~~\n%Error: Exiting due to 20 error(s)\n"
module AlphaMissionCore_Back1_sync(
    input  wire VIDEO_RSTn,
    input wire clk,
    input wire CK1,
    input wire RESET,

    input wire INV,
    input wire INVn,

    input wire [7:0] VD_in,
    output logic [7:0] VD_out,

	input wire         [24:0] ioctl_addr,
	input wire         [7:0] ioctl_data,
	input wire               ioctl_wr,

    input wire B1SY,
    input wire B1SX,


    input wire B1Y8,
    input wire B1X8,


    input wire V_C,


    input wire H8,
    input wire [4:0] Y,
    input wire H2,
    input wire H1,
    input wire H0,
    input wire [7:0] X, 

    input wire [11:0] VA,
    input wire BACK1_VRAM_CSn,
    input wire [1:0] B1_TILEBANK,
    

    input wire VFLGn,


    input wire VRD,
    input wire VDG,
    input wire VOE,
    input wire VWE,


    input wire CK1n,
    input wire LA,
    input wire VLK,



    output logic [3:0] B1D
);

    logic [2:0] XOR_YSR;
    logic [7:0] B1Y;
    assign XOR_YSR[2] = VD_in[2] ^ INVn;
    assign XOR_YSR[1] = VD_in[1] ^ INVn;
    assign XOR_YSR[0] = VD_in[0] ^ INVn;


    reg [7:0] vdin_r;
    always @(posedge clk) begin
        vdin_r <= {VD_in[7:3],XOR_YSR};
    end

    ttl_74273_sync g2(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(B1SY), .D(vdin_r), .Q(B1Y));

    logic [8:0] B1H;
    logic [2:0] B1Hn;
    logic c14_dum3;
    logic [1:0] c12_dum;

    ttl_74283_nodly c14 (.A({1'b1, B1Y[2:0]}),    .B({1'b1, H2,H1,H0}), .C_in(1'b0),     .Sum({c14_dum3,B1H[2:0]}),           .C_out()        );
    logic c13_cout;
    ttl_74283_nodly c13 (.A(B1Y[6:3]),            .B(Y[3:0]),           .C_in(1'b0),     .Sum(B1H[6:3]),                      .C_out(c13_cout));
    ttl_74283_nodly c12 (.A({2'b11,B1Y8,B1Y[7]}), .B({2'b11, H8,Y[4]}), .C_in(c13_cout), .Sum({c12_dum,B1H[8:7]}),            .C_out()        );

    assign B1Hn[0] = ~B1H[0];
    assign B1Hn[1] = ~B1H[1];
    assign B1Hn[2] = ~B1H[2];

    logic [8:0] B1HQ;

    logic [5:0] d13_q;
    ttl_74174_sync d13
    (
        .Reset_n(VIDEO_RSTn),
        .Clk(clk),
        .Cen(CK1n),
        .Clr_n(1'b1),
        .D({3'b111,B1Hn}),
        .Q(d13_q)
    );
    assign B1HQ[2:0] = d13_q[2:0];

    logic [5:0] d12_q;
    ttl_74174_sync d12
    (
        .Reset_n(VIDEO_RSTn),
        .Clk(clk),
        .Cen(CK1n),
        .Clr_n(1'b1),
        .D(B1H[8:3]),
        .Q(d12_q)
    );
    assign B1HQ[8:3] = d12_q[5:0];


    reg [7:0] vdinX_r;
     always @(posedge clk) begin
        vdinX_r <= VD_in;
    end

    logic [7:0] B1X;
    ttl_74273_sync b12(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(B1SX), .D(vdinX_r), .Q(B1X));
    logic [8:0] B1V;
    logic a12_cout;
    ttl_74283_nodly a12 (.A(B1X[3:0]),    .B(X[3:0]), .C_in(1'b0),         .Sum(B1V[3:0]), .C_out(a12_cout));
    logic a11_cout;
    ttl_74283_nodly a11 (.A(B1X[7:4]),    .B(X[7:4]), .C_in(a12_cout),     .Sum(B1V[7:4]), .C_out(a11_cout));
    assign B1V[8] = B1X8 ^ a11_cout;



    logic h12_CSn;
    logic [11:0] A;
    logic dum3,dum2,dum1;

    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) e12 (.Enable_bar(1'b0), .Select(V_C),
                .A_2D({VA[11],B1HQ[8],VA[10],B1HQ[7],VA[9],B1HQ[6],VA[8],B1HQ[5]}), .Y(A[11:8]));

    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) e13 (.Enable_bar(1'b0), .Select(V_C),
                .A_2D({VA[7],B1HQ[4],VA[6],B1HQ[3],VA[5],B1V[8],VA[4],B1V[7]}), .Y(A[7:4]));

    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) e14 (.Enable_bar(1'b0), .Select(V_C),
                .A_2D({VA[3],B1V[6],VA[2],B1V[5],VA[1],B1V[4],VA[0],B1V[3]}), .Y(A[3:0]));

    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) d2 (.Enable_bar(1'b0), .Select(V_C),
                .A_2D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,BACK1_VRAM_CSn,VFLGn}), .Y({dum3,dum2,dum1,h12_CSn}));

    logic BACK1_SEL;
    assign BACK1_SEL = ~(BACK1_VRAM_CSn | VDG);


    logic [7:0] D, Din;
    assign Din = (BACK1_SEL && VRD) ?  VD_in : 8'hFF;


    logic [7:0] back1_Q;
    logic [7:0] Dreg;
    logic h12_CS;

    assign h12_CS = ~h12_CSn;

    logic [12:0] h12_addr1;
    assign h12_addr1 = {1'b0,B1HQ[8:3],B1V[8:3]};

    SRAM_dual_sync #(.ADDR_WIDTH(13)) h12
    (
        .ADDR0({1'b0,VA[11:0]}), 
        .clk0(clk), 
        .cen0(~BACK1_VRAM_CSn), 
        .we0(~VWE), 
        .DATA0(Din), 
        .Q0(back1_Q),
        .ADDR1(h12_addr1), 
        .clk1(clk), 
        .cen1(~VFLGn), 
        .we1(1'b0), 
        .DATA1(8'hff),
        .Q1(Dreg)
    );

    assign D = (!VOE) ? back1_Q : 8'hff;
    assign VD_out = (BACK1_SEL && !VRD) ? D : 8'hff;





    logic [7:0] F12_Q;
    ttl_74273_sync f12(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(VLK), .D(Dreg), .Q(F12_Q));

    logic [7:0] F13_Q;
    ttl_74273_sync f13(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(LA), .D(F12_Q), .Q(F13_Q));

    logic [7:0] F14_Q;
    ttl_74273_sync f14(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(B1HQ[2]), .D(F13_Q), .Q(F14_Q));

    logic H14_A0;
    logic H14_A1;
    assign H14_A0 = B1HQ[1] ^ INV;
    assign H14_A1 = B1HQ[2] ^ INV;



    wire H14_D_cs = (ioctl_addr >= 25'h40_000) & (ioctl_addr < 25'h48_000);
    
    logic [7:0] H14_D;
    eprom_32K P10_H14
    (
        .ADDR({B1_TILEBANK, F14_Q[7:0], B1V[2:0], H14_A1, H14_A0}),
        .CLK(clk),
        .DATA(H14_D),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data),
        .CS_DL(H14_D_cs),
        .WR(ioctl_wr)
    );

    logic [7:0] G14_Q;
    ttl_74273_sync g14(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(B1HQ[0]), .D(H14_D), .Q(G14_Q));

    logic G14_S;
    assign G14_S = B1HQ[0] ^ INV;
    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) a2 (.Enable_bar(1'b0), .Select(G14_S),
                .A_2D({G14_Q[7],G14_Q[3],G14_Q[6],G14_Q[2],G14_Q[5],G14_Q[1],G14_Q[4],G14_Q[0]}), .Y(B1D));
endmodule
module AlphaMissionCore_Back1_sync(
    input  wire VIDEO_RSTn,
    input wire clk,
    input wire CK1,
    input wire RESET,

    input wire INV,
    input wire INVn,

    input wire [7:0] VD_in,
    output logic [7:0] VD_out,

	input wire         [24:0] ioctl_addr,
	input wire         [7:0] ioctl_data,
	input wire               ioctl_wr,

    input wire B1SY,
    input wire B1SX,


    input wire B1Y8,
    input wire B1X8,


    input wire V_C,


    input wire H8,
    input wire [4:0] Y,
    input wire H2,
    input wire H1,
    input wire H0,
    input wire [7:0] X, 

    input wire [11:0] VA,
    input wire BACK1_VRAM_CSn,
    input wire [1:0] B1_TILEBANK,
    

    input wire VFLGn,


    input wire VRD,
    input wire VDG,
    input wire VOE,
    input wire VWE,


    input wire CK1n,
    input wire LA,
    input wire VLK,



    output logic [3:0] B1D
);


    logic [2:0] XOR_YSR;
    logic [7:0] B1Y;
    assign XOR_YSR[2] = VD_in[2] ^ INVn;
    assign XOR_YSR[1] = VD_in[1] ^ INVn;
    assign XOR_YSR[0] = VD_in[0] ^ INVn;


    reg [7:0] vdin_r;
    always @(posedge clk) begin
        vdin_r <= {VD_in[7:3],XOR_YSR};
    end

    ttl_74273_sync g2(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(B1SY), .D(vdin_r), .Q(B1Y));

    logic [8:0] B1H;
    logic [2:0] B1Hn;
    logic c14_dum3;
    logic [1:0] c12_dum;

    ttl_74283_nodly c14 (.A({1'b1, B1Y[2:0]}),    .B({1'b1, H2,H1,H0}), .C_in(1'b0),     .Sum({c14_dum3,B1H[2:0]}),           .C_out()        );
    logic c13_cout;
    ttl_74283_nodly c13 (.A(B1Y[6:3]),            .B(Y[3:0]),           .C_in(1'b0),     .Sum(B1H[6:3]),                      .C_out(c13_cout));
    ttl_74283_nodly c12 (.A({2'b11,B1Y8,B1Y[7]}), .B({2'b11, H8,Y[4]}), .C_in(c13_cout), .Sum({c12_dum,B1H[8:7]}),            .C_out()        );

    assign B1Hn[0] = ~B1H[0];
    assign B1Hn[1] = ~B1H[1];
    assign B1Hn[2] = ~B1H[2];

    logic [8:0] B1HQ;

    logic [5:0] d13_q;
    ttl_74174_sync d13
    (
        .Reset_n(VIDEO_RSTn),
        .Clk(clk),
        .Cen(CK1n),
        .Clr_n(1'b1),
        .D({3'b111,B1Hn}),
        .Q(d13_q)
    );
    assign B1HQ[2:0] = d13_q[2:0];

    logic [5:0] d12_q;
    ttl_74174_sync d12
    (
        .Reset_n(VIDEO_RSTn),
        .Clk(clk),
        .Cen(CK1n),
        .Clr_n(1'b1),
        .D(B1H[8:3]),
        .Q(d12_q)
    );
    assign B1HQ[8:3] = d12_q[5:0];


    reg [7:0] vdinX_r;
     always @(posedge clk) begin
        vdinX_r <= VD_in;
    end

    logic [7:0] B1X;
    ttl_74273_sync b12(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(B1SX), .D(vdinX_r), .Q(B1X));
    logic [8:0] B1V;
    logic a12_cout;
    ttl_74283_nodly a12 (.A(B1X[3:0]),    .B(X[3:0]), .C_in(1'b0),         .Sum(B1V[3:0]), .C_out(a12_cout));
    logic a11_cout;
    ttl_74283_nodly a11 (.A(B1X[7:4]),    .B(X[7:4]), .C_in(a12_cout),     .Sum(B1V[7:4]), .C_out(a11_cout));
    assign B1V[8] = B1X8 ^ a11_cout;



    logic h12_CSn;
    logic [11:0] A;
    logic dum3,dum2,dum1;

    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) e12 (.Enable_bar(1'b0), .Select(V_C),
                .A_2D({VA[11],B1HQ[8],VA[10],B1HQ[7],VA[9],B1HQ[6],VA[8],B1HQ[5]}), .Y(A[11:8]));

    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) e13 (.Enable_bar(1'b0), .Select(V_C),
                .A_2D({VA[7],B1HQ[4],VA[6],B1HQ[3],VA[5],B1V[8],VA[4],B1V[7]}), .Y(A[7:4]));

    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) e14 (.Enable_bar(1'b0), .Select(V_C),
                .A_2D({VA[3],B1V[6],VA[2],B1V[5],VA[1],B1V[4],VA[0],B1V[3]}), .Y(A[3:0]));

    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) d2 (.Enable_bar(1'b0), .Select(V_C),
                .A_2D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,BACK1_VRAM_CSn,VFLGn}), .Y({dum3,dum2,dum1,h12_CSn}));

    logic BACK1_SEL;
    assign BACK1_SEL = ~(BACK1_VRAM_CSn | VDG);


    logic [7:0] D, Din;
    assign Din = (BACK1_SEL && VRD) ?  VD_in : 8'hFF;


    logic [7:0] back1_Q;
    logic [7:0] Dreg;
    logic h12_CS;

    assign h12_CS = ~h12_CSn;

    logic [12:0] h12_addr1;
    assign h12_addr1 = {1'b0,B1HQ[8:3],B1V[8:3]};

    SRAM_dual_sync #(.ADDR_WIDTH(13)) h12
    (
        .ADDR0({1'b0,VA[11:0]}), 
        .clk0(clk), 
        .cen0(~BACK1_VRAM_CSn), 
        .we0(~VWE), 
        .DATA0(Din), 
        .Q0(back1_Q),
        .ADDR1(h12_addr1), 
        .clk1(clk), 
        .cen1(~VFLGn), 
        .we1(1'b0), 
        .DATA1(8'hff),
        .Q1(Dreg)
    );

    assign D = (!VOE) ? back1_Q : 8'hff;
    assign VD_out = (BACK1_SEL && !VRD) ? D : 8'hff;





    logic [7:0] F12_Q;
    ttl_74273_sync f12(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(VLK), .D(Dreg), .Q(F12_Q));

    logic [7:0] F13_Q;
    ttl_74273_sync f13(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(LA), .D(F12_Q), .Q(F13_Q));

    logic [7:0] F14_Q;
    ttl_74273_sync f14(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(B1HQ[2]), .D(F13_Q), .Q(F14_Q));

    logic H14_A0;
    logic H14_A1;
    assign H14_A0 = B1HQ[1] ^ INV;
    assign H14_A1 = B1HQ[2] ^ INV;



    wire H14_D_cs = (ioctl_addr >= 25'h40_000) & (ioctl_addr < 25'h48_000);
    
    logic [7:0] H14_D;
    eprom_32K P10_H14
    (
        .ADDR({B1_TILEBANK, F14_Q[7:0], B1V[2:0], H14_A1, H14_A0}),
        .CLK(clk),
        .DATA(H14_D),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data),
        .CS_DL(H14_D_cs),
        .WR(ioctl_wr)
    );

    logic [7:0] G14_Q;
    ttl_74273_sync g14(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(B1HQ[0]), .D(H14_D), .Q(G14_Q));

    logic G14_S;
    assign G14_S = B1HQ[0] ^ INV;
    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) a2 (.Enable_bar(1'b0), .Select(G14_S),
                .A_2D({G14_Q[7],G14_Q[3],G14_Q[6],G14_Q[2],G14_Q[5],G14_Q[1],G14_Q[4],G14_Q[0]}), .Y(B1D));
endmodule