data/full_repos/permissive/485312426/sim/Rotator_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/485312426/sim/Rotator_TB.v:8: Unsupported: Ignoring delay on this delayed statement.\n        clk = 0 ; #5 ;\n                  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/485312426/sim/Rotator_TB.v:9: Unsupported: Ignoring delay on this delayed statement.\n        clk = 1 ; #5 ;\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/485312426/sim/Rotator_TB.v:15: Unsupported: Ignoring delay on this delayed statement.\n        #8 ;      rstn      = 1\'b1 ;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/485312426/sim/Rotator_TB.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #55 ;\n        ^\n%Error: data/full_repos/permissive/485312426/sim/Rotator_TB.v:32: syntax error, unexpected \'@\'\n        repeat(30) @(negedge clk );\n                   ^\n%Error: data/full_repos/permissive/485312426/sim/Rotator_TB.v:36: syntax error, unexpected \'@\'\n        repeat(30) @(negedge clk);\n                   ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Rotator_TB;
    reg  clk, rstn;
    wire rst = ~rstn;


    always begin
        clk = 0 ; #5 ;
        clk = 1 ; #5 ;
    end


    initial begin
        rstn      = 1'b0 ;
        #8 ;      rstn      = 1'b1 ;
    end

    reg [15:0] io_in_x;
    reg [15:0] io_in_y;
    reg [15:0] io_in_a;
    wire [15:0] io_out_x;
    wire [15:0] io_out_y;
    wire [15:0] io_out_a;

    reg [15:0] test_out_x;
    reg [15:0] test_out_y;
    reg [15:0] test_out_a;


    initial begin
        #55 ;
        repeat(30) @(negedge clk );
        io_in_a = 16'sd1;
        io_in_x = 16'shff;
        io_in_y = 16'shaa;
        repeat(30) @(negedge clk);
        io_in_a = -16'sd1;
        io_in_x = 16'shff;
        io_in_y = 16'shaa;
    end


    Rotator uut (
      .clock            (clk),
      .reset            (rst),
      .io_in_x          (io_in_x),
      .io_in_y          (io_in_y),
      .io_in_a          (io_in_a),
      .io_out_x         (io_out_x),
      .io_out_y         (io_out_y),
      .io_out_a         (io_out_a)
     );
endmodule
module Rotator_TB;

    reg  clk, rstn;
    wire rst = ~rstn;


    always begin
        clk = 0 ; #5 ;
        clk = 1 ; #5 ;
    end


    initial begin
        rstn      = 1'b0 ;
        #8 ;      rstn      = 1'b1 ;
    end

    reg [15:0] io_in_x;
    reg [15:0] io_in_y;
    reg [15:0] io_in_a;
    wire [15:0] io_out_x;
    wire [15:0] io_out_y;
    wire [15:0] io_out_a;

    reg [15:0] test_out_x;
    reg [15:0] test_out_y;
    reg [15:0] test_out_a;


    initial begin
        #55 ;
        repeat(30) @(negedge clk );
        io_in_a = 16'sd1;
        io_in_x = 16'shff;
        io_in_y = 16'shaa;
        repeat(30) @(negedge clk);
        io_in_a = -16'sd1;
        io_in_x = 16'shff;
        io_in_y = 16'shaa;
    end


    Rotator uut (
      .clock            (clk),
      .reset            (rst),
      .io_in_x          (io_in_x),
      .io_in_y          (io_in_y),
      .io_in_a          (io_in_a),
      .io_out_x         (io_out_x),
      .io_out_y         (io_out_y),
      .io_out_a         (io_out_a)
     );
endmodule