data/full_repos/permissive/52703097/full_adder.v
data/verilator_xmls/4a172b97-e580-43ed-8d3b-6db1ac33a7b2.xml
module full_adder(
    input i_a,
    input i_b,
    input i_cin,
    output o_result,
    output o_cout);

    assign o_result = i_a ^ i_b ^ i_cin;
    assign o_cout = (i_a & i_b) | (i_a & i_cin) | (i_b & i_cin);
endmodule
module full_adder(
    input i_a,
    input i_b,
    input i_cin,
    output o_result,
    output o_cout);


    assign o_result = i_a ^ i_b ^ i_cin;
    assign o_cout = (i_a & i_b) | (i_a & i_cin) | (i_b & i_cin);
endmodule