data/full_repos/permissive/415491487/design_src/main.v
1: b'%Error: data/full_repos/permissive/415491487/design_src/main.v:83: syntax error, unexpected type\n    cmp c0(.clk(clk), .opa(inwirefile[c0opa]), .opb(inwirefile[c0opb]), .type(inwirefile[c0type]), .result(outwirefile[c0result]));\n                                                                         ^~~~\n%Error: Exiting due to 1 error(s)\n'
module proc(
    input clk,
    input rst,
    
    output reg [23:0] iaddr,
    input [23:0] idata,
    
    output [23:0] dwaddr,
    output [23:0] dwdata,
    
    output [23:0] draddr,
    input [23:0] drdata
);
    parameter num_units = 11;
    
    parameter ua0opa = 0;
    parameter ua0opb = 1;
    
    parameter us0opa = 2;
    parameter us0opb = 3;
    
    parameter c0opa = 4;
    parameter c0opb = 5;
    parameter c0type = 6;
    
    parameter dw0addr = 7;
    parameter dw0data = 8;
    
    parameter dr0addr = 9;
    
    parameter statwrite = num_units - 1;
    
    parameter ua0result = 0;
    
    parameter us0result = 1;
    
    parameter c0result = 2;
    
    parameter dr0data = 3;
    
    parameter statread = num_units - 1;
    
    parameter pc = 31;
    
    parameter fetch = 2'b00;
    parameter execute = 2'b01;
    parameter writeback = 2'b11;
    
    reg [23:0] unitfile [(num_units * 2) + 31:0];
    wire [23:0] inwirefile [num_units - 1:0];
    wire [23:0] outwirefile [num_units - 1:0];
    
    generate
        genvar i;
        for (i = 0; i < num_units; i = i + 1) begin
            assign inwirefile[i] = unitfile[i + 32];
        end
    endgenerate
    
    wire valid_instr, lit_mv, hl, cond;
    wire [6:0] src, dest;
    wire [11:0] lit;
    
    reg [1:0] statecounter;
    
    decodeunit d0(.clk(clk), .rst(rst), .instr(idata), .conditional(cond), .valid(valid_instr), .lit_mv(lit_mv), .hl(hl), .src(src), .dest(dest), .lit(lit));
    
    u24add ua0(.clk(clk), .opa(inwirefile[ua0opa]), .opb(inwirefile[ua0opb]), .result(outwirefile[ua0result]));
    u24sub us0(.clk(clk), .opa(inwirefile[us0opa]), .opb(inwirefile[us0opb]), .result(outwirefile[us0result]));
    
    cmp c0(.clk(clk), .opa(inwirefile[c0opa]), .opb(inwirefile[c0opb]), .type(inwirefile[c0type]), .result(outwirefile[c0result]));
    
    assign dwaddr = inwirefile[dw0addr];
    assign dwdata = inwirefile[dw0data];
    
    assign draddr = inwirefile[dr0addr];
    assign outwirefile[dr0data] = drdata;
    
    integer wb;
    
    always @(posedge clk) begin
        if (rst) begin
            statecounter <= fetch;
            unitfile[pc] <= 24'h0;
            unitfile[0] <= 24'h0;
            unitfile[32 + statread] <= 24'h0;
        end else begin
            case (statecounter)
                fetch: begin
                    iaddr <= unitfile[pc];
                    unitfile[pc] <= unitfile[pc] + 1;
                    statecounter <= execute;
                end

                execute: begin
                    $display("got instr 0x%0h back, addr = 0x%0h.", idata, iaddr);
                    $write("executed ");
                    if (cond == 1'b1) begin $write("conditional "); end
                    if (valid_instr) begin
                        if (!cond || (cond && outwirefile[c0result])) begin
                            if (lit_mv) begin
                                $display("load %d -> %d.", lit, dest);
                                unitfile[dest] <= hl ? { lit, unitfile[dest][11:0] } : { unitfile[dest][23:12], lit };
                            end else begin
                                $display("move %d -> %d.", src, dest);
                                unitfile[dest] <= unitfile[src];
                            end
                        end
                    end
                    else begin
                       $display("nop. (invalid instruction)");
                    end
                    statecounter <= writeback;
                end
                writeback: begin
                    for (wb = 0; wb < num_units; wb = wb + 1) begin
                        unitfile[wb + num_units + 32] <= outwirefile[wb];
                    end
                    statecounter <= fetch;
                end
                default: begin
                    $display("ERROR: invalid state counter %d.", statecounter);
                end
            endcase
        end
    end
endmodule
module proc(
    input clk,
    input rst,
    
    output reg [23:0] iaddr,
    input [23:0] idata,
    
    output [23:0] dwaddr,
    output [23:0] dwdata,
    
    output [23:0] draddr,
    input [23:0] drdata
);

    parameter num_units = 11;
    
    parameter ua0opa = 0;
    parameter ua0opb = 1;
    
    parameter us0opa = 2;
    parameter us0opb = 3;
    
    parameter c0opa = 4;
    parameter c0opb = 5;
    parameter c0type = 6;
    
    parameter dw0addr = 7;
    parameter dw0data = 8;
    
    parameter dr0addr = 9;
    
    parameter statwrite = num_units - 1;
    
    parameter ua0result = 0;
    
    parameter us0result = 1;
    
    parameter c0result = 2;
    
    parameter dr0data = 3;
    
    parameter statread = num_units - 1;
    
    parameter pc = 31;
    
    parameter fetch = 2'b00;
    parameter execute = 2'b01;
    parameter writeback = 2'b11;
    
    reg [23:0] unitfile [(num_units * 2) + 31:0];
    wire [23:0] inwirefile [num_units - 1:0];
    wire [23:0] outwirefile [num_units - 1:0];
    
    generate
        genvar i;
        for (i = 0; i < num_units; i = i + 1) begin
            assign inwirefile[i] = unitfile[i + 32];
        end
    endgenerate
    
    wire valid_instr, lit_mv, hl, cond;
    wire [6:0] src, dest;
    wire [11:0] lit;
    
    reg [1:0] statecounter;
    
    decodeunit d0(.clk(clk), .rst(rst), .instr(idata), .conditional(cond), .valid(valid_instr), .lit_mv(lit_mv), .hl(hl), .src(src), .dest(dest), .lit(lit));
    
    u24add ua0(.clk(clk), .opa(inwirefile[ua0opa]), .opb(inwirefile[ua0opb]), .result(outwirefile[ua0result]));
    u24sub us0(.clk(clk), .opa(inwirefile[us0opa]), .opb(inwirefile[us0opb]), .result(outwirefile[us0result]));
    
    cmp c0(.clk(clk), .opa(inwirefile[c0opa]), .opb(inwirefile[c0opb]), .type(inwirefile[c0type]), .result(outwirefile[c0result]));
    
    assign dwaddr = inwirefile[dw0addr];
    assign dwdata = inwirefile[dw0data];
    
    assign draddr = inwirefile[dr0addr];
    assign outwirefile[dr0data] = drdata;
    
    integer wb;
    
    always @(posedge clk) begin
        if (rst) begin
            statecounter <= fetch;
            unitfile[pc] <= 24'h0;
            unitfile[0] <= 24'h0;
            unitfile[32 + statread] <= 24'h0;
        end else begin
            case (statecounter)
                fetch: begin
                    iaddr <= unitfile[pc];
                    unitfile[pc] <= unitfile[pc] + 1;
                    statecounter <= execute;
                end

                execute: begin
                    $display("got instr 0x%0h back, addr = 0x%0h.", idata, iaddr);
                    $write("executed ");
                    if (cond == 1'b1) begin $write("conditional "); end
                    if (valid_instr) begin
                        if (!cond || (cond && outwirefile[c0result])) begin
                            if (lit_mv) begin
                                $display("load %d -> %d.", lit, dest);
                                unitfile[dest] <= hl ? { lit, unitfile[dest][11:0] } : { unitfile[dest][23:12], lit };
                            end else begin
                                $display("move %d -> %d.", src, dest);
                                unitfile[dest] <= unitfile[src];
                            end
                        end
                    end
                    else begin
                       $display("nop. (invalid instruction)");
                    end
                    statecounter <= writeback;
                end
                writeback: begin
                    for (wb = 0; wb < num_units; wb = wb + 1) begin
                        unitfile[wb + num_units + 32] <= outwirefile[wb];
                    end
                    statecounter <= fetch;
                end
                default: begin
                    $display("ERROR: invalid state counter %d.", statecounter);
                end
            endcase
        end
    end
endmodule