data/full_repos/permissive/517127224/fpga/hdl/NES_KV260.v
1: b"%Error: data/full_repos/permissive/517127224/fpga/hdl/NES_KV260.v:325: Can't find definition of 'slv_reg_wren' in dotted variable: 'axi.slv_reg_wren'\n  wire       loader_clk   = (axi_state == 2) && s00_axi_aresetn == 1'b1 && axi.slv_reg_wren && s00_axi_awaddr == 4'b0;\n                                                                               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/517127224/fpga/hdl/NES_KV260.v:392: Can't find definition of 'slv_reg_wren' in dotted variable: 'axi.slv_reg_wren'\n    if (s00_axi_aresetn == 1'b1 && axi.slv_reg_wren && s00_axi_awaddr == 4'b0) begin\n                                       ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module NES_KV260(

    input clk,
    input reset,

    output clk_ppu,
    output [5:0] color,
    output [8:0] scanline,
    output [8:0] cycle,
    
    output [15:0] sample,


    input wire  s00_axi_aclk,
    input wire  s00_axi_aresetn,
    input wire [3:0] s00_axi_awaddr,
    input wire [2:0] s00_axi_awprot,
    input wire  s00_axi_awvalid,
    output wire  s00_axi_awready,
    input wire [31:0] s00_axi_wdata,
    input wire [(32/8)-1 : 0] s00_axi_wstrb,
    input wire  s00_axi_wvalid,
    output wire  s00_axi_wready,
    output wire [1 : 0] s00_axi_bresp,
    output wire  s00_axi_bvalid,
    input wire  s00_axi_bready,
    input wire [3:0] s00_axi_araddr,
    input wire [2:0] s00_axi_arprot,
    input wire  s00_axi_arvalid,
    output wire  s00_axi_arready,
    output wire [31:0] s00_axi_rdata,
    output wire [1:0] s00_axi_rresp,
    output wire  s00_axi_rvalid,
    input wire  s00_axi_rready
);


  wire joypad_strobe;
  wire [1:0] joypad_clock;
  wire [21:0] memory_addr;
  wire memory_read_cpu, memory_read_ppu;
  wire memory_write;
  wire [7:0] memory_din_cpu, memory_din_ppu;
  wire [7:0] memory_dout;
  reg [7:0] joypad_bits, joypad_bits2;
  reg [1:0] last_joypad_clock;
  wire [31:0] dbgadr;
  wire [1:0] dbgctr;
  reg [1:0] nes_ce = 0;
  wire [15:0] SW = 16'b1111_1111_1111_1111;


  nes_axi # ( 
    .C_S_AXI_DATA_WIDTH(32),
    .C_S_AXI_ADDR_WIDTH(4)
  ) axi (
    .value(axi_cmd),
    .result(axi_status),
    .S_AXI_ACLK(s00_axi_aclk),.S_AXI_ARESETN(s00_axi_aresetn),
    .S_AXI_AWADDR(s00_axi_awaddr),.S_AXI_AWPROT(s00_axi_awprot),.S_AXI_AWVALID(s00_axi_awvalid),.S_AXI_AWREADY(s00_axi_awready),
    .S_AXI_WDATA(s00_axi_wdata),.S_AXI_WSTRB(s00_axi_wstrb),.S_AXI_WVALID(s00_axi_wvalid),.S_AXI_WREADY(s00_axi_wready),
    .S_AXI_BRESP(s00_axi_bresp),.S_AXI_BVALID(s00_axi_bvalid),.S_AXI_BREADY(s00_axi_bready),
    .S_AXI_ARADDR(s00_axi_araddr),.S_AXI_ARPROT(s00_axi_arprot),.S_AXI_ARVALID(s00_axi_arvalid),.S_AXI_ARREADY(s00_axi_arready),
    .S_AXI_RDATA(s00_axi_rdata),.S_AXI_RRESP(s00_axi_rresp),.S_AXI_RVALID(s00_axi_rvalid),.S_AXI_RREADY(s00_axi_rready)
  );

  wire [31:0] axi_cmd;
  wire [31:0] axi_status;
  assign axi_status[0] = loader_done;
  assign axi_status[1] = loader_fail;
  assign axi_status[3:2] = axi_state;


  reg [1:0] axi_state = 0;
  wire [7:0] wbyte = s00_axi_wdata[7:0];
  wire [31:0] wdata = s00_axi_wdata;

  reg  [7:0] loader_conf;
  reg [7:0] loader_btn, loader_btn_2;

`ifdef EMBED_GAME

  wire [7:0] loader_input;
  wire loader_clk;
  wire loader_reset = reset;
  GameData ines(clk, reset, loader_input, loader_clk);
`else

  wire [7:0] loader_input = wbyte;
  wire       loader_clk   = (axi_state == 2) && s00_axi_aresetn == 1'b1 && axi.slv_reg_wren && s00_axi_awaddr == 4'b0;
  wire loader_reset = loader_conf[0];
`endif

  always @(posedge clk) begin
    if (joypad_strobe) begin
      joypad_bits <= loader_btn;
      joypad_bits2 <= loader_btn_2;
    end
    if (!joypad_clock[0] && last_joypad_clock[0])
      joypad_bits <= {1'b0, joypad_bits[7:1]};
    if (!joypad_clock[1] && last_joypad_clock[1])
      joypad_bits2 <= {1'b0, joypad_bits2[7:1]};
    last_joypad_clock <= joypad_clock;
  end


  wire [21:0] loader_addr;
  wire [7:0] loader_write_data;
  wire loader_write;
  wire [31:0] mapper_flags;
  wire loader_done, loader_fail;
  

  GameLoader loader(clk, loader_reset, loader_input, loader_clk,
                    loader_addr, loader_write_data, loader_write,
                    mapper_flags, loader_done, loader_fail);


  wire reset_nes = !loader_done;
  wire run_mem = (nes_ce == 0) && !reset_nes;
  wire run_nes = (nes_ce == 3) && !reset_nes;
  assign clk_ppu = (nes_ce == 3 || nes_ce == 0);


  always @(posedge clk)
    nes_ce <= nes_ce + 1;


  NES nes(clk, reset_nes, run_nes,
          mapper_flags,
          sample, color,
          joypad_strobe, joypad_clock, {joypad_bits2[0], joypad_bits[0]},
          SW[4:0],
          memory_addr,
          memory_read_cpu, memory_din_cpu,
          memory_read_ppu, memory_din_ppu,
          memory_write, memory_dout,
          cycle, scanline,
          dbgadr,
          dbgctr);


  wire ram_busy;
  MemoryController memory(clk,
        memory_read_cpu && run_mem, 
        memory_read_ppu && run_mem,
        memory_write && run_mem || loader_write,
        loader_write ? loader_addr : memory_addr,
        loader_write ? loader_write_data : memory_dout,
        memory_din_cpu,
        memory_din_ppu,
        ram_busy);

  reg [31:0] loader_len = 0;
  reg [31:0] loader_count = 0;
  always @(posedge s00_axi_aclk) begin
    if (s00_axi_aresetn == 1'b1 && axi.slv_reg_wren && s00_axi_awaddr == 4'b0) begin
        case (axi_state)
            2'd0: if (wdata == 1) begin

                    axi_state <= 1;
                    loader_conf <= 0;
                end else if (wdata == 2) begin

                    loader_conf <= 1;
                end else if (wbyte == 3) begin



                    loader_btn <= wdata[15:8];
                    loader_btn_2 <= wdata[23:16];
                end
            2'd1: begin
                loader_len <= wdata;
                loader_count <= 0;
                axi_state <= 2;
            end
            2'd2: begin

                if (loader_count == loader_len - 1) begin
                    axi_state <= 0;
                end
                loader_count <= loader_count + 1;
            end
            default: begin end

        endcase
    end
  end

endmodule
module NES_KV260(

    input clk,
    input reset,

    output clk_ppu,
    output [5:0] color,
    output [8:0] scanline,
    output [8:0] cycle,
    
    output [15:0] sample,


    input wire  s00_axi_aclk,
    input wire  s00_axi_aresetn,
    input wire [3:0] s00_axi_awaddr,
    input wire [2:0] s00_axi_awprot,
    input wire  s00_axi_awvalid,
    output wire  s00_axi_awready,
    input wire [31:0] s00_axi_wdata,
    input wire [(32/8)-1 : 0] s00_axi_wstrb,
    input wire  s00_axi_wvalid,
    output wire  s00_axi_wready,
    output wire [1 : 0] s00_axi_bresp,
    output wire  s00_axi_bvalid,
    input wire  s00_axi_bready,
    input wire [3:0] s00_axi_araddr,
    input wire [2:0] s00_axi_arprot,
    input wire  s00_axi_arvalid,
    output wire  s00_axi_arready,
    output wire [31:0] s00_axi_rdata,
    output wire [1:0] s00_axi_rresp,
    output wire  s00_axi_rvalid,
    input wire  s00_axi_rready
);



  wire joypad_strobe;
  wire [1:0] joypad_clock;
  wire [21:0] memory_addr;
  wire memory_read_cpu, memory_read_ppu;
  wire memory_write;
  wire [7:0] memory_din_cpu, memory_din_ppu;
  wire [7:0] memory_dout;
  reg [7:0] joypad_bits, joypad_bits2;
  reg [1:0] last_joypad_clock;
  wire [31:0] dbgadr;
  wire [1:0] dbgctr;
  reg [1:0] nes_ce = 0;
  wire [15:0] SW = 16'b1111_1111_1111_1111;


  nes_axi # ( 
    .C_S_AXI_DATA_WIDTH(32),
    .C_S_AXI_ADDR_WIDTH(4)
  ) axi (
    .value(axi_cmd),
    .result(axi_status),
    .S_AXI_ACLK(s00_axi_aclk),.S_AXI_ARESETN(s00_axi_aresetn),
    .S_AXI_AWADDR(s00_axi_awaddr),.S_AXI_AWPROT(s00_axi_awprot),.S_AXI_AWVALID(s00_axi_awvalid),.S_AXI_AWREADY(s00_axi_awready),
    .S_AXI_WDATA(s00_axi_wdata),.S_AXI_WSTRB(s00_axi_wstrb),.S_AXI_WVALID(s00_axi_wvalid),.S_AXI_WREADY(s00_axi_wready),
    .S_AXI_BRESP(s00_axi_bresp),.S_AXI_BVALID(s00_axi_bvalid),.S_AXI_BREADY(s00_axi_bready),
    .S_AXI_ARADDR(s00_axi_araddr),.S_AXI_ARPROT(s00_axi_arprot),.S_AXI_ARVALID(s00_axi_arvalid),.S_AXI_ARREADY(s00_axi_arready),
    .S_AXI_RDATA(s00_axi_rdata),.S_AXI_RRESP(s00_axi_rresp),.S_AXI_RVALID(s00_axi_rvalid),.S_AXI_RREADY(s00_axi_rready)
  );

  wire [31:0] axi_cmd;
  wire [31:0] axi_status;
  assign axi_status[0] = loader_done;
  assign axi_status[1] = loader_fail;
  assign axi_status[3:2] = axi_state;


  reg [1:0] axi_state = 0;
  wire [7:0] wbyte = s00_axi_wdata[7:0];
  wire [31:0] wdata = s00_axi_wdata;

  reg  [7:0] loader_conf;
  reg [7:0] loader_btn, loader_btn_2;

`ifdef EMBED_GAME

  wire [7:0] loader_input;
  wire loader_clk;
  wire loader_reset = reset;
  GameData ines(clk, reset, loader_input, loader_clk);
`else

  wire [7:0] loader_input = wbyte;
  wire       loader_clk   = (axi_state == 2) && s00_axi_aresetn == 1'b1 && axi.slv_reg_wren && s00_axi_awaddr == 4'b0;
  wire loader_reset = loader_conf[0];
`endif

  always @(posedge clk) begin
    if (joypad_strobe) begin
      joypad_bits <= loader_btn;
      joypad_bits2 <= loader_btn_2;
    end
    if (!joypad_clock[0] && last_joypad_clock[0])
      joypad_bits <= {1'b0, joypad_bits[7:1]};
    if (!joypad_clock[1] && last_joypad_clock[1])
      joypad_bits2 <= {1'b0, joypad_bits2[7:1]};
    last_joypad_clock <= joypad_clock;
  end


  wire [21:0] loader_addr;
  wire [7:0] loader_write_data;
  wire loader_write;
  wire [31:0] mapper_flags;
  wire loader_done, loader_fail;
  

  GameLoader loader(clk, loader_reset, loader_input, loader_clk,
                    loader_addr, loader_write_data, loader_write,
                    mapper_flags, loader_done, loader_fail);


  wire reset_nes = !loader_done;
  wire run_mem = (nes_ce == 0) && !reset_nes;
  wire run_nes = (nes_ce == 3) && !reset_nes;
  assign clk_ppu = (nes_ce == 3 || nes_ce == 0);


  always @(posedge clk)
    nes_ce <= nes_ce + 1;


  NES nes(clk, reset_nes, run_nes,
          mapper_flags,
          sample, color,
          joypad_strobe, joypad_clock, {joypad_bits2[0], joypad_bits[0]},
          SW[4:0],
          memory_addr,
          memory_read_cpu, memory_din_cpu,
          memory_read_ppu, memory_din_ppu,
          memory_write, memory_dout,
          cycle, scanline,
          dbgadr,
          dbgctr);


  wire ram_busy;
  MemoryController memory(clk,
        memory_read_cpu && run_mem, 
        memory_read_ppu && run_mem,
        memory_write && run_mem || loader_write,
        loader_write ? loader_addr : memory_addr,
        loader_write ? loader_write_data : memory_dout,
        memory_din_cpu,
        memory_din_ppu,
        ram_busy);

  reg [31:0] loader_len = 0;
  reg [31:0] loader_count = 0;
  always @(posedge s00_axi_aclk) begin
    if (s00_axi_aresetn == 1'b1 && axi.slv_reg_wren && s00_axi_awaddr == 4'b0) begin
        case (axi_state)
            2'd0: if (wdata == 1) begin

                    axi_state <= 1;
                    loader_conf <= 0;
                end else if (wdata == 2) begin

                    loader_conf <= 1;
                end else if (wbyte == 3) begin



                    loader_btn <= wdata[15:8];
                    loader_btn_2 <= wdata[23:16];
                end
            2'd1: begin
                loader_len <= wdata;
                loader_count <= 0;
                axi_state <= 2;
            end
            2'd2: begin

                if (loader_count == loader_len - 1) begin
                    axi_state <= 0;
                end
                loader_count <= loader_count + 1;
            end
            default: begin end

        endcase
    end
  end

endmodule