data/full_repos/permissive/473722449/PIPO_bidirectional.v
1: b"%Error: data/full_repos/permissive/473722449/PIPO_bidirectional.v:27: Cannot find file containing module: 'mux4x1'\n    mux4x1 m0 (ctrl[1],ctrl[0],q[0],xl,q[1],d[0],s[0]);\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/473722449,data/full_repos/permissive/473722449/mux4x1\n             data/full_repos/permissive/473722449,data/full_repos/permissive/473722449/mux4x1.v\n             data/full_repos/permissive/473722449,data/full_repos/permissive/473722449/mux4x1.sv\n             mux4x1\n             mux4x1.v\n             mux4x1.sv\n             obj_dir/mux4x1\n             obj_dir/mux4x1.v\n             obj_dir/mux4x1.sv\n%Error: data/full_repos/permissive/473722449/PIPO_bidirectional.v:28: Cannot find file containing module: 'mux4x1'\n    mux4x1 m1 (ctrl[1],ctrl[0],q[1],q[0],q[2],d[1],s[1]);\n    ^~~~~~\n%Error: data/full_repos/permissive/473722449/PIPO_bidirectional.v:29: Cannot find file containing module: 'mux4x1'\n    mux4x1 m2 (ctrl[1],ctrl[0],q[2],q[1],q[3],d[2],s[2]);\n    ^~~~~~\n%Error: data/full_repos/permissive/473722449/PIPO_bidirectional.v:30: Cannot find file containing module: 'mux4x1'\n    mux4x1 m3 (ctrl[1],ctrl[0],q[3],q[2],xr,d[3],s[3]);\n    ^~~~~~\n%Error: data/full_repos/permissive/473722449/PIPO_bidirectional.v:32: Cannot find file containing module: 'DFF_clr'\n    DFF_clr d0 (s[0],clk,clear,q[0]);\n    ^~~~~~~\n%Error: data/full_repos/permissive/473722449/PIPO_bidirectional.v:33: Cannot find file containing module: 'DFF_clr'\n    DFF_clr d1 (s[1],clk,clear,q[1]);\n    ^~~~~~~\n%Error: data/full_repos/permissive/473722449/PIPO_bidirectional.v:34: Cannot find file containing module: 'DFF_clr'\n    DFF_clr d2 (s[2],clk,clear,q[2]);\n    ^~~~~~~\n%Error: data/full_repos/permissive/473722449/PIPO_bidirectional.v:35: Cannot find file containing module: 'DFF_clr'\n    DFF_clr d3 (s[3],clk,clear,q[3]);\n    ^~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module PIPO_bidirectional(
    input [3:0] d,
    input [1:0] ctrl,
    input clear,
    input clk,
    input xl,
    input xr,
    output [3:0] q
    );
    wire [3:0] s;
    mux4x1 m0 (ctrl[1],ctrl[0],q[0],xl,q[1],d[0],s[0]);
    mux4x1 m1 (ctrl[1],ctrl[0],q[1],q[0],q[2],d[1],s[1]);
    mux4x1 m2 (ctrl[1],ctrl[0],q[2],q[1],q[3],d[2],s[2]);
    mux4x1 m3 (ctrl[1],ctrl[0],q[3],q[2],xr,d[3],s[3]);
    
    DFF_clr d0 (s[0],clk,clear,q[0]);
    DFF_clr d1 (s[1],clk,clear,q[1]);
    DFF_clr d2 (s[2],clk,clear,q[2]);
    DFF_clr d3 (s[3],clk,clear,q[3]);
    
endmodule
module PIPO_bidirectional(
    input [3:0] d,
    input [1:0] ctrl,
    input clear,
    input clk,
    input xl,
    input xr,
    output [3:0] q
    );

    wire [3:0] s;
    mux4x1 m0 (ctrl[1],ctrl[0],q[0],xl,q[1],d[0],s[0]);
    mux4x1 m1 (ctrl[1],ctrl[0],q[1],q[0],q[2],d[1],s[1]);
    mux4x1 m2 (ctrl[1],ctrl[0],q[2],q[1],q[3],d[2],s[2]);
    mux4x1 m3 (ctrl[1],ctrl[0],q[3],q[2],xr,d[3],s[3]);
    
    DFF_clr d0 (s[0],clk,clear,q[0]);
    DFF_clr d1 (s[1],clk,clear,q[1]);
    DFF_clr d2 (s[2],clk,clear,q[2]);
    DFF_clr d3 (s[3],clk,clear,q[3]);
    
endmodule