data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:28: Cannot find include file: ifu.h\n`include "ifu.h" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/ifu.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/ifu.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/ifu.h.sv\n             ifu.h\n             ifu.h.v\n             ifu.h.sv\n             obj_dir/ifu.h\n             obj_dir/ifu.h.v\n             obj_dir/ifu.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:78: Define or directive not defined: \'`THRFSM_IDLE\'\n          `THRFSM_IDLE:   \n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:78: syntax error, unexpected \':\', expecting endcase\n          `THRFSM_IDLE:   \n                      ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:81: Define or directive not defined: \'`THRFSM_WAIT\'\n               next_state = `THRFSM_WAIT;\n                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:83: Define or directive not defined: \'`THRFSM_RDY\'\n               next_state = `THRFSM_RDY;\n                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:88: Define or directive not defined: \'`THRFSM_HALT\'\n         `THRFSM_HALT:   \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:89: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n           begin\n           ^~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:91: Define or directive not defined: \'`THRFSM_IDLE\'\n               next_state = `THRFSM_IDLE;\n                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:93: Define or directive not defined: \'`THRFSM_WAIT\'\n               next_state = `THRFSM_WAIT;\n                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:95: Define or directive not defined: \'`THRFSM_RDY\'\n               next_state = `THRFSM_RDY;\n                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:100: Define or directive not defined: \'`THRFSM_RDY\'\n         `THRFSM_RDY:        \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:101: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n           begin\n           ^~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:105: Define or directive not defined: \'`THRFSM_WAIT\'\n               next_state = `THRFSM_WAIT;\n                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:107: Define or directive not defined: \'`THRFSM_RUN\'\n               next_state = `THRFSM_RUN;\n                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:112: Define or directive not defined: \'`THRFSM_RUN\'\n         `THRFSM_RUN:        \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:113: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n           begin\n           ^~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:117: Define or directive not defined: \'`THRFSM_WAIT\'\n               next_state = `THRFSM_WAIT;\n                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:121: Define or directive not defined: \'`THRFSM_RDY\'\n               next_state = `THRFSM_RDY;\n                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:126: Define or directive not defined: \'`THRFSM_WAIT\'\n         `THRFSM_WAIT:        \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:127: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n           begin\n           ^~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:129: Define or directive not defined: \'`THRFSM_IDLE\'\n               next_state = `THRFSM_IDLE;\n                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:131: Define or directive not defined: \'`THRFSM_HALT\'\n               next_state = `THRFSM_HALT;\n                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:133: Define or directive not defined: \'`THRFSM_WAIT\'\n               next_state = `THRFSM_WAIT;\n                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:135: Define or directive not defined: \'`THRFSM_SPEC_RDY\'\n               next_state = `THRFSM_SPEC_RDY;\n                            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:137: Define or directive not defined: \'`THRFSM_RDY\'\n               next_state = `THRFSM_RDY;\n                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:142: Define or directive not defined: \'`THRFSM_SPEC_RDY\'\n         `THRFSM_SPEC_RDY:        \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:143: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n           begin\n           ^~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:145: Define or directive not defined: \'`THRFSM_WAIT\'\n               next_state = `THRFSM_WAIT;\n                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:147: Define or directive not defined: \'`THRFSM_SPEC_RUN\'\n               next_state = `THRFSM_SPEC_RUN;\n                            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:149: Define or directive not defined: \'`THRFSM_RUN\'\n               next_state = `THRFSM_RUN;\n                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:151: Define or directive not defined: \'`THRFSM_RDY\'\n               next_state = `THRFSM_RDY;\n                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:156: Define or directive not defined: \'`THRFSM_SPEC_RUN\'\n         `THRFSM_SPEC_RUN:        \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:157: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n           begin\n           ^~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:159: Define or directive not defined: \'`THRFSM_WAIT\'\n               next_state = `THRFSM_WAIT;\n                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:161: Define or directive not defined: \'`THRFSM_RDY\'\n               next_state = `THRFSM_RDY;\n                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:163: Define or directive not defined: \'`THRFSM_RUN\'\n               next_state = `THRFSM_RUN;\n                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:165: Define or directive not defined: \'`THRFSM_SPEC_RDY\'\n               next_state = `THRFSM_SPEC_RDY;\n                            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:173: syntax error, unexpected \':\', expecting clocking\n         default:\n                ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:187: syntax error, unexpected \'=\', expecting IDENTIFIER\n               next_state = `THRFSM_WAIT;\n                          ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:187: Define or directive not defined: \'`THRFSM_WAIT\'\n               next_state = `THRFSM_WAIT;\n                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:189: syntax error, unexpected \'=\', expecting IDENTIFIER\n               next_state = `THRFSM_IDLE;   \n                          ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:189: Define or directive not defined: \'`THRFSM_IDLE\'\n               next_state = `THRFSM_IDLE;   \n                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_thrfsm.v:191: syntax error, unexpected \'=\', expecting IDENTIFIER\n               next_state = thr_state[4:0];\n                          ^\n%Error: Exiting due to 43 error(s)\n'
module sparc_ifu_thrfsm(

   so, thr_state, 

   completion, schedule, spec_ld, ldhit, stall, int_activate, 
   start_thread, thaw_thread, nuke_thread, rst_thread, switch_out, 
   halt_thread, sw_cond, clk, se, si, reset
   );


   input  completion,
	        schedule,
	        spec_ld,
	        ldhit,
	        stall,
	        int_activate,
          halt_thread,
	        start_thread,
	        nuke_thread,
          thaw_thread,
	        rst_thread;


   input  switch_out,
	        sw_cond;

   input       clk, se, si, reset;

   output      so;

   output [4:0] thr_state;


   reg [4:0]    next_state;
   



   


   always @ (completion
             or halt_thread or int_activate or ldhit or nuke_thread
             or rst_thread or schedule or spec_ld or stall
             or start_thread or sw_cond or switch_out or thaw_thread 
             or thr_state)
     begin
	      case (thr_state[4:0])
          `THRFSM_IDLE:
	          begin
	             if (rst_thread | thaw_thread)
		             next_state = `THRFSM_WAIT;
	             else if (start_thread)    
		             next_state = `THRFSM_RDY;
	             else
		             next_state = thr_state[4:0];
	          end

	        `THRFSM_HALT:
	          begin
	             if (nuke_thread)
		             next_state = `THRFSM_IDLE;
	             else if (rst_thread | thaw_thread)
		             next_state = `THRFSM_WAIT;
	             else if (int_activate | start_thread) 
		             next_state = `THRFSM_RDY;
	             else
		             next_state = thr_state[4:0];
	          end
	        
	        `THRFSM_RDY:
	          begin
	             if (stall)     


		             next_state = `THRFSM_WAIT;
	             else if (schedule)
		             next_state = `THRFSM_RUN;
	             else
		             next_state = thr_state[4:0];
	          end

	        `THRFSM_RUN:
	          begin
	             if (stall | sw_cond)


		             next_state = `THRFSM_WAIT;
	             else if (switch_out)


		             next_state = `THRFSM_RDY;
	             else
		             next_state = thr_state[4:0];
	          end

	        `THRFSM_WAIT:
	          begin
	             if (nuke_thread) 
		             next_state = `THRFSM_IDLE;
	             else if (halt_thread)
		             next_state = `THRFSM_HALT;
	             else if (stall)
		             next_state = `THRFSM_WAIT;
	             else if (spec_ld)
		             next_state = `THRFSM_SPEC_RDY;
	             else if (completion & ~halt_thread)
		             next_state = `THRFSM_RDY;
	             else
		             next_state = thr_state[4:0];
	          end
	        
	        `THRFSM_SPEC_RDY:
	          begin
	             if (stall)
		             next_state = `THRFSM_WAIT;
	             else if (schedule & ~ldhit)
		             next_state = `THRFSM_SPEC_RUN;
	             else if (schedule & ldhit)
		             next_state = `THRFSM_RUN;
	             else if (ldhit)
		             next_state = `THRFSM_RDY;
	             else
		             next_state = thr_state[4:0];
	          end

	        `THRFSM_SPEC_RUN:
	          begin
	             if (stall | sw_cond)
		             next_state = `THRFSM_WAIT;
	             else if ((ldhit) & switch_out)
		             next_state = `THRFSM_RDY;
	             else if ((ldhit) & ~switch_out)
		             next_state = `THRFSM_RUN;
	             else if (~(ldhit) & switch_out)
		             next_state = `THRFSM_SPEC_RDY;


	             else
		             next_state = thr_state[4:0];
	          end


	        default:
	          begin


`ifdef DEFINE_0IN
`else           
		`ifdef MODELSIM
	             $display("ILLEGAL_THR_STATE", "thrfsm.v: Error! Invalid State %b\n", thr_state);
		`else
	             $error("ILLEGAL_THR_STATE", "thrfsm.v: Error! Invalid State %b\n", thr_state);
		`endif		 
`endif		     

	             if (rst_thread)
		             next_state = `THRFSM_WAIT;
	             else if (nuke_thread)
		             next_state = `THRFSM_IDLE;		 
	             else 
		             next_state = thr_state[4:0];
	          end

	      endcase
     end


   dffr_s #(5) tcr(.din  (next_state),
	             .clk  (clk),
	             .q    (thr_state),
	             .rst  (reset),
	             .se   (se), .so(), .si());


endmodule
module sparc_ifu_thrfsm(

   so, thr_state, 

   completion, schedule, spec_ld, ldhit, stall, int_activate, 
   start_thread, thaw_thread, nuke_thread, rst_thread, switch_out, 
   halt_thread, sw_cond, clk, se, si, reset
   );



   input  completion,
	        schedule,
	        spec_ld,
	        ldhit,
	        stall,
	        int_activate,
          halt_thread,
	        start_thread,
	        nuke_thread,
          thaw_thread,
	        rst_thread;


   input  switch_out,
	        sw_cond;

   input       clk, se, si, reset;

   output      so;

   output [4:0] thr_state;


   reg [4:0]    next_state;
   



   


   always @ (completion
             or halt_thread or int_activate or ldhit or nuke_thread
             or rst_thread or schedule or spec_ld or stall
             or start_thread or sw_cond or switch_out or thaw_thread 
             or thr_state)
     begin
	      case (thr_state[4:0])
          `THRFSM_IDLE:
	          begin
	             if (rst_thread | thaw_thread)
		             next_state = `THRFSM_WAIT;
	             else if (start_thread)    
		             next_state = `THRFSM_RDY;
	             else
		             next_state = thr_state[4:0];
	          end

	        `THRFSM_HALT:
	          begin
	             if (nuke_thread)
		             next_state = `THRFSM_IDLE;
	             else if (rst_thread | thaw_thread)
		             next_state = `THRFSM_WAIT;
	             else if (int_activate | start_thread) 
		             next_state = `THRFSM_RDY;
	             else
		             next_state = thr_state[4:0];
	          end
	        
	        `THRFSM_RDY:
	          begin
	             if (stall)     


		             next_state = `THRFSM_WAIT;
	             else if (schedule)
		             next_state = `THRFSM_RUN;
	             else
		             next_state = thr_state[4:0];
	          end

	        `THRFSM_RUN:
	          begin
	             if (stall | sw_cond)


		             next_state = `THRFSM_WAIT;
	             else if (switch_out)


		             next_state = `THRFSM_RDY;
	             else
		             next_state = thr_state[4:0];
	          end

	        `THRFSM_WAIT:
	          begin
	             if (nuke_thread) 
		             next_state = `THRFSM_IDLE;
	             else if (halt_thread)
		             next_state = `THRFSM_HALT;
	             else if (stall)
		             next_state = `THRFSM_WAIT;
	             else if (spec_ld)
		             next_state = `THRFSM_SPEC_RDY;
	             else if (completion & ~halt_thread)
		             next_state = `THRFSM_RDY;
	             else
		             next_state = thr_state[4:0];
	          end
	        
	        `THRFSM_SPEC_RDY:
	          begin
	             if (stall)
		             next_state = `THRFSM_WAIT;
	             else if (schedule & ~ldhit)
		             next_state = `THRFSM_SPEC_RUN;
	             else if (schedule & ldhit)
		             next_state = `THRFSM_RUN;
	             else if (ldhit)
		             next_state = `THRFSM_RDY;
	             else
		             next_state = thr_state[4:0];
	          end

	        `THRFSM_SPEC_RUN:
	          begin
	             if (stall | sw_cond)
		             next_state = `THRFSM_WAIT;
	             else if ((ldhit) & switch_out)
		             next_state = `THRFSM_RDY;
	             else if ((ldhit) & ~switch_out)
		             next_state = `THRFSM_RUN;
	             else if (~(ldhit) & switch_out)
		             next_state = `THRFSM_SPEC_RDY;


	             else
		             next_state = thr_state[4:0];
	          end


	        default:
	          begin


`ifdef DEFINE_0IN
`else           
		`ifdef MODELSIM
	             $display("ILLEGAL_THR_STATE", "thrfsm.v: Error! Invalid State %b\n", thr_state);
		`else
	             $error("ILLEGAL_THR_STATE", "thrfsm.v: Error! Invalid State %b\n", thr_state);
		`endif		 
`endif		     

	             if (rst_thread)
		             next_state = `THRFSM_WAIT;
	             else if (nuke_thread)
		             next_state = `THRFSM_IDLE;		 
	             else 
		             next_state = thr_state[4:0];
	          end

	      endcase
     end


   dffr_s #(5) tcr(.din  (next_state),
	             .clk  (clk),
	             .q    (thr_state),
	             .rst  (reset),
	             .se   (se), .so(), .si());


endmodule