data/full_repos/permissive/515613199/divider_tb.v
1: b'%Error: data/full_repos/permissive/515613199/divider_tb.v:2: Cannot find include file: reg_size.v\n`include "reg_size.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/515613199,data/full_repos/permissive/515613199/reg_size.v\n             data/full_repos/permissive/515613199,data/full_repos/permissive/515613199/reg_size.v.v\n             data/full_repos/permissive/515613199,data/full_repos/permissive/515613199/reg_size.v.sv\n             reg_size.v\n             reg_size.v.v\n             reg_size.v.sv\n             obj_dir/reg_size.v\n             obj_dir/reg_size.v.v\n             obj_dir/reg_size.v.sv\n%Error: data/full_repos/permissive/515613199/divider_tb.v:9: Define or directive not defined: \'`SIZE\'\nreg[`SIZE-1:0] N;\n    ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/515613199/divider_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #2 rst=1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/515613199/divider_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #2 rst=0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/515613199/divider_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n  forever #5 clk=~clk;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/515613199/divider_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #1  en=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/515613199/divider_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #50 N=2; rst=1; en=0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/515613199/divider_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #2  rst=0; en=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/515613199/divider_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #100 N=3; rst=1; en=0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/515613199/divider_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #2  rst=0; en=1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/515613199/divider_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #150 $finish;\n  ^\n%Error: data/full_repos/permissive/515613199/divider_tb.v:71: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("graph.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/515613199/divider_tb.v:72: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0,divider_testbench);\n  ^~~~~~~~~\n%Error: Exiting due to 4 error(s), 9 warning(s)\n'
module divider_testbench;

reg clk,rst,en;
wire div_clk;

reg[`SIZE-1:0] N;

N_divider DIV(.ref_clk(clk), .enable(en), .N(N), .reset(rst), .div_clk(div_clk));

initial 
begin
  rst=0;
  #2 rst=1;
  #2 rst=0;
end

initial
begin
  clk=0;
  forever #5 clk=~clk;
end  

initial
begin

 
      N=1;
  #1  en=1;
  #50 N=2; rst=1; en=0;
  #2  rst=0; en=1;
  #100 N=3; rst=1; en=0;
  #2  rst=0; en=1;
  #150 $finish;
end

initial
begin
  $dumpfile("graph.vcd");
  $dumpvars(0,divider_testbench);
end
endmodule
module divider_testbench;


reg clk,rst,en;
wire div_clk;

reg[`SIZE-1:0] N;

N_divider DIV(.ref_clk(clk), .enable(en), .N(N), .reset(rst), .div_clk(div_clk));

initial 
begin
  rst=0;
  #2 rst=1;
  #2 rst=0;
end

initial
begin
  clk=0;
  forever #5 clk=~clk;
end  

initial
begin

 
      N=1;
  #1  en=1;
  #50 N=2; rst=1; en=0;
  #2  rst=0; en=1;
  #100 N=3; rst=1; en=0;
  #2  rst=0; en=1;
  #150 $finish;
end

initial
begin
  $dumpfile("graph.vcd");
  $dumpvars(0,divider_testbench);
end
endmodule