data/full_repos/permissive/434840709/lab3/3.2/CatchPress.v
data/verilator_xmls/0237e4bd-37aa-4176-af09-8c39e2c56f45.xml
module CatchPress(input clk190hz, input press, output signal);
    reg[5:0] delay;
    
    always @(posedge clk190hz)
    begin
        delay[5] <= delay[4];
        delay[4] <= delay[3];
        delay[3] <= delay[2];
        delay[2] <= delay[1]; 
        delay[1] <= delay[0];  
        delay[0] <= press;
    end
    
    assign signal = delay[0] & delay[1] & delay[2] & delay[3] & delay[4] & delay[5];
endmodule
module CatchPress(input clk190hz, input press, output signal);

    reg[5:0] delay;
    
    always @(posedge clk190hz)
    begin
        delay[5] <= delay[4];
        delay[4] <= delay[3];
        delay[3] <= delay[2];
        delay[2] <= delay[1]; 
        delay[1] <= delay[0];  
        delay[0] <= press;
    end
    
    assign signal = delay[0] & delay[1] & delay[2] & delay[3] & delay[4] & delay[5];
endmodule