data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_dbus.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_dbus.sv:21: Unsupported: Ignoring delay on this delayed statement.\n forever #(0.5) clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_dbus.sv:33: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_dbus.sv:35: Unsupported: Ignoring delay on this delayed statement.\n #2;\n ^\n%Error: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_dbus.sv:47: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_dbus.sv:57: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_dbus.sv:58: Unsupported: Ignoring delay on this delayed statement.\n  #0.1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_dbus.sv:65: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_dbus.sv:67: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_dbus.sv:74: Unsupported: Ignoring delay on this delayed statement.\n #4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_dbus.sv:87: Unsupported: Ignoring delay on this delayed statement.\n #200;\n ^\n%Error: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_dbus.sv:111: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tb.lxt");   \n ^~~~~~~~~\n%Error: data/full_repos/permissive/456528918/RTL/tb_iverilog/tb_dbus.sv:112: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, test);    \n ^~~~~~~~~\n%Error: Exiting due to 4 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_dbus();
parameter DW=16;
parameter AW=16;

logic clk,rst;
logic [DW-1:0]din;
logic [DW-1:0]dout;
logic [AW-1:0]addr;
logic we;
logic [DW-1:0]gpio_in;
logic [DW-1:0]gpio_out;
logic T0_PWM_N;
logic T0_PWM_P;
logic T1_PWM_N;
logic T1_PWM_P;


initial begin
	clk = '0;
	forever #(0.5) clk = ~clk;
end


task sysrst;
	input rstb;
begin
	rst <= rstb;
	din <= 0;
	addr <= 0;
	we <= 0;
	gpio_in <= 0;
	#2;
	rst <= ~rstb;
	#2;
end
endtask : sysrst


task write_d;
	input [AW-1:0]w_addr;
	input [DW-1:0]w_data;
	begin
		we=1;
		addr=w_addr;
		din=w_data;
		@(posedge clk)
		#0.1;
	end
endtask : write_d

task read_d;
	input [AW-1:0]r_addr;
	begin
		we=0;
		addr=r_addr;
		@(posedge clk);
		#0.1;
	end
endtask : read_d


initial begin
	sysrst(1);
	#1;
	gpio_in<=16'h1A;
	#1;
	write_d(16'h0,16'h30);
	write_d(16'h1,16'h31);
	read_d(16'h1);
	read_d(16'h0);
	write_d(16'h2,16'h32);
	read_d(16'h2);
	#4;
	read_d(16'h1000);
	write_d(16'h1001,16'h3C);
	read_d(16'h1);

	write_d(16'h2001,16'h1);
	write_d(16'h2002,16'h6);
	write_d(16'h2003,16'h4);
	write_d(16'h2005,16'h7);
	write_d(16'h2006,16'h2);
	write_d(16'h2000,16'h0301);
	$display("|--------Yduck dbus pass---------|");

	#200;
	$finish;
end


dbus #(
		.RAM_AW(7)
	) test (
		.clk      (clk),
		.rst      (rst),
		.din      (din),
		.addr     (addr),
		.we       (we),
		.dout     (dout),
		.gpio_in  (gpio_in),
		.gpio_out (gpio_out),
		.T0_PWM_P (T0_PWM_P),
		.T0_PWM_N (T0_PWM_N),
		.T1_PWM_P (T1_PWM_P),
		.T1_PWM_N (T1_PWM_N)
	);


initial begin
	$dumpfile("tb.lxt");
	$dumpvars(0, test);
end

endmodule
module tb_dbus();

parameter DW=16;
parameter AW=16;

logic clk,rst;
logic [DW-1:0]din;
logic [DW-1:0]dout;
logic [AW-1:0]addr;
logic we;
logic [DW-1:0]gpio_in;
logic [DW-1:0]gpio_out;
logic T0_PWM_N;
logic T0_PWM_P;
logic T1_PWM_N;
logic T1_PWM_P;


initial begin
	clk = '0;
	forever #(0.5) clk = ~clk;
end


task sysrst;
	input rstb;
begin
	rst <= rstb;
	din <= 0;
	addr <= 0;
	we <= 0;
	gpio_in <= 0;
	#2;
	rst <= ~rstb;
	#2;
end
endtask : sysrst


task write_d;
	input [AW-1:0]w_addr;
	input [DW-1:0]w_data;
	begin
		we=1;
		addr=w_addr;
		din=w_data;
		@(posedge clk)
		#0.1;
	end
endtask : write_d

task read_d;
	input [AW-1:0]r_addr;
	begin
		we=0;
		addr=r_addr;
		@(posedge clk);
		#0.1;
	end
endtask : read_d


initial begin
	sysrst(1);
	#1;
	gpio_in<=16'h1A;
	#1;
	write_d(16'h0,16'h30);
	write_d(16'h1,16'h31);
	read_d(16'h1);
	read_d(16'h0);
	write_d(16'h2,16'h32);
	read_d(16'h2);
	#4;
	read_d(16'h1000);
	write_d(16'h1001,16'h3C);
	read_d(16'h1);

	write_d(16'h2001,16'h1);
	write_d(16'h2002,16'h6);
	write_d(16'h2003,16'h4);
	write_d(16'h2005,16'h7);
	write_d(16'h2006,16'h2);
	write_d(16'h2000,16'h0301);
	$display("|--------Yduck dbus pass---------|");

	#200;
	$finish;
end


dbus #(
		.RAM_AW(7)
	) test (
		.clk      (clk),
		.rst      (rst),
		.din      (din),
		.addr     (addr),
		.we       (we),
		.dout     (dout),
		.gpio_in  (gpio_in),
		.gpio_out (gpio_out),
		.T0_PWM_P (T0_PWM_P),
		.T0_PWM_N (T0_PWM_N),
		.T1_PWM_P (T1_PWM_P),
		.T1_PWM_N (T1_PWM_N)
	);


initial begin
	$dumpfile("tb.lxt");
	$dumpvars(0, test);
end

endmodule