data/full_repos/permissive/468612001/Week02/multiplexer1/multiplexer1.v
data/verilator_xmls/edca8fd3-51d5-461b-b367-a8178a07845f.xml
module multiplexer1(a, b, sel, out);
	input a, b, sel;
	output out;
	
	assign out = sel ? b : a;
	
endmodule
module multiplexer1(a, b, sel, out);

	input a, b, sel;
	output out;
	
	assign out = sel ? b : a;
	
endmodule