data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_buf_pt.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_buf_pt.v:35: Cannot find include file: sys.h\n`include "sys.h" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_buf_pt.v:36: Cannot find include file: iop.h\n`include "iop.h" \n         ^~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module pcx_buf_pt(

   out0_l, out1_l, pcx_spc_grant_px, so, 

   in0, in1, pcx_spc_grant_buf_pa, rclk, si, se
   );
   

   output [4:0]		out0_l;	
   output 		out1_l;	
   output [4:0]		pcx_spc_grant_px;	
   output 		so;
   

   input [4:0] 		in0;
   input            	in1;
   input [4:0]		pcx_spc_grant_buf_pa;	

   input 		rclk;
   input 		si, se;
   
   dff_s #(5) dff_ccx_com_spc(
            .din           (pcx_spc_grant_buf_pa[4:0]),
	    .q             (pcx_spc_grant_px[4:0]),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (5'd0),
	    .so            ());

   
   assign out0_l[4:0] = ~in0[4:0];
   assign out1_l = ~in1;
   




endmodule
module pcx_buf_pt(

   out0_l, out1_l, pcx_spc_grant_px, so, 

   in0, in1, pcx_spc_grant_buf_pa, rclk, si, se
   );

   

   output [4:0]		out0_l;	
   output 		out1_l;	
   output [4:0]		pcx_spc_grant_px;	
   output 		so;
   

   input [4:0] 		in0;
   input            	in1;
   input [4:0]		pcx_spc_grant_buf_pa;	

   input 		rclk;
   input 		si, se;
   
   dff_s #(5) dff_ccx_com_spc(
            .din           (pcx_spc_grant_buf_pa[4:0]),
	    .q             (pcx_spc_grant_px[4:0]),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (5'd0),
	    .so            ());

   
   assign out0_l[4:0] = ~in0[4:0];
   assign out1_l = ~in1;
   




endmodule