data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/GeneralPurpose/Gp2to1Mux.v
data/verilator_xmls/75a2be25-e81f-4a7f-aaa5-8939d3900317.xml
module Gp2to1Mux #(
    parameter WIDTH = 64
) (
    input [WIDTH - 1:0] a,
    input [WIDTH - 1:0] b,
    input select,

    output reg [WIDTH - 1:0] out
);

    always @(*) begin
        case(select)
            1'b0: out = a;
            1'b1: out = b;
            default: out = {WIDTH{1'bX}}; 
        endcase
    end

endmodule
module Gp2to1Mux #(
    parameter WIDTH = 64
) (
    input [WIDTH - 1:0] a,
    input [WIDTH - 1:0] b,
    input select,

    output reg [WIDTH - 1:0] out
);


    always @(*) begin
        case(select)
            1'b0: out = a;
            1'b1: out = b;
            default: out = {WIDTH{1'bX}}; 
        endcase
    end

endmodule