data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v
1: b'%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:14: Operator SHIFTL expects 8 bits on the LHS, but LHS\'s VARREF \'u1\' generates 4 bits.\n                                                                                          : ... In instance optest\n   0: y <= u1 << u2;\n              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:15: Operator SHIFTL expects 8 bits on the LHS, but LHS\'s VARREF \'u1\' generates 4 bits.\n                                                                                          : ... In instance optest\n   1: y <= u1 << s2;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:16: Operator SHIFTL expects 8 bits on the LHS, but LHS\'s VARREF \'s1\' generates 4 bits.\n                                                                                          : ... In instance optest\n   2: y <= s1 << u2;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:17: Operator SHIFTL expects 8 bits on the LHS, but LHS\'s VARREF \'s1\' generates 4 bits.\n                                                                                          : ... In instance optest\n   3: y <= s1 << s2;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:19: Operator SHIFTR expects 8 bits on the LHS, but LHS\'s VARREF \'u1\' generates 4 bits.\n                                                                                          : ... In instance optest\n   4: y <= u1 >> u2;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:20: Operator SHIFTR expects 8 bits on the LHS, but LHS\'s VARREF \'u1\' generates 4 bits.\n                                                                                          : ... In instance optest\n   5: y <= u1 >> s2;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:21: Operator SHIFTR expects 8 bits on the LHS, but LHS\'s VARREF \'s1\' generates 4 bits.\n                                                                                          : ... In instance optest\n   6: y <= s1 >> u2;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:22: Operator SHIFTR expects 8 bits on the LHS, but LHS\'s VARREF \'s1\' generates 4 bits.\n                                                                                          : ... In instance optest\n   7: y <= s1 >> s2;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:24: Operator SHIFTL expects 8 bits on the LHS, but LHS\'s VARREF \'u1\' generates 4 bits.\n                                                                                          : ... In instance optest\n   8: y <= u1 <<< u2;\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:25: Operator SHIFTL expects 8 bits on the LHS, but LHS\'s VARREF \'u1\' generates 4 bits.\n                                                                                          : ... In instance optest\n   9: y <= u1 <<< s2;\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:26: Operator SHIFTL expects 8 bits on the LHS, but LHS\'s VARREF \'s1\' generates 4 bits.\n                                                                                          : ... In instance optest\n  10: y <= s1 <<< u2;\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:27: Operator SHIFTL expects 8 bits on the LHS, but LHS\'s VARREF \'s1\' generates 4 bits.\n                                                                                          : ... In instance optest\n  11: y <= s1 <<< s2;\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:29: Operator SHIFTR expects 8 bits on the LHS, but LHS\'s VARREF \'u1\' generates 4 bits.\n                                                                                          : ... In instance optest\n  12: y <= u1 >>> u2;\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:30: Operator SHIFTR expects 8 bits on the LHS, but LHS\'s VARREF \'u1\' generates 4 bits.\n                                                                                          : ... In instance optest\n  13: y <= u1 >>> s2;\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:31: Operator SHIFTRS expects 8 bits on the LHS, but LHS\'s VARREF \'s1\' generates 4 bits.\n                                                                                          : ... In instance optest\n  14: y <= s1 >>> u2;\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:32: Operator SHIFTRS expects 8 bits on the LHS, but LHS\'s VARREF \'s1\' generates 4 bits.\n                                                                                          : ... In instance optest\n  15: y <= s1 >>> s2;\n              ^~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:34: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                                                          : ... In instance optest\n  16: y <= u1 < u2;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:35: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                                                          : ... In instance optest\n  17: y <= u1 < s2;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:36: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                                                          : ... In instance optest\n  18: y <= s1 < u2;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:37: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s LTS generates 1 bits.\n                                                                                          : ... In instance optest\n  19: y <= s1 < s2;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:39: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s LTE generates 1 bits.\n                                                                                          : ... In instance optest\n  20: y <= u1 <= u2;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:40: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s LTE generates 1 bits.\n                                                                                          : ... In instance optest\n  21: y <= u1 <= s2;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:41: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s LTE generates 1 bits.\n                                                                                          : ... In instance optest\n  22: y <= s1 <= u2;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:42: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s LTES generates 1 bits.\n                                                                                          : ... In instance optest\n  23: y <= s1 <= s2;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:44: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s EQ generates 1 bits.\n                                                                                          : ... In instance optest\n  24: y <= u1 == u2;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:45: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s EQ generates 1 bits.\n                                                                                          : ... In instance optest\n  25: y <= u1 == s2;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:46: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s EQ generates 1 bits.\n                                                                                          : ... In instance optest\n  26: y <= s1 == u2;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:47: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s EQ generates 1 bits.\n                                                                                          : ... In instance optest\n  27: y <= s1 == s2;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:49: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s NEQ generates 1 bits.\n                                                                                          : ... In instance optest\n  28: y <= u1 != u2;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:50: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s NEQ generates 1 bits.\n                                                                                          : ... In instance optest\n  29: y <= u1 != s2;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:51: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s NEQ generates 1 bits.\n                                                                                          : ... In instance optest\n  30: y <= s1 != u2;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:52: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s NEQ generates 1 bits.\n                                                                                          : ... In instance optest\n  31: y <= s1 != s2;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:54: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s GTE generates 1 bits.\n                                                                                          : ... In instance optest\n  32: y <= u1 >= u2;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:55: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s GTE generates 1 bits.\n                                                                                          : ... In instance optest\n  33: y <= u1 >= s2;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:56: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s GTE generates 1 bits.\n                                                                                          : ... In instance optest\n  34: y <= s1 >= u2;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:57: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s GTES generates 1 bits.\n                                                                                          : ... In instance optest\n  35: y <= s1 >= s2;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:59: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s GT generates 1 bits.\n                                                                                          : ... In instance optest\n  36: y <= u1 > u2;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:60: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s GT generates 1 bits.\n                                                                                          : ... In instance optest\n  37: y <= u1 > s2;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:61: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s GT generates 1 bits.\n                                                                                          : ... In instance optest\n  38: y <= s1 > u2;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:62: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s GTS generates 1 bits.\n                                                                                          : ... In instance optest\n  39: y <= s1 > s2;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:64: Operator ADD expects 8 bits on the LHS, but LHS\'s VARREF \'u1\' generates 4 bits.\n                                                                                          : ... In instance optest\n  40: y <= u1 + u2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:64: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'u2\' generates 4 bits.\n                                                                                          : ... In instance optest\n  40: y <= u1 + u2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:65: Operator ADD expects 8 bits on the LHS, but LHS\'s VARREF \'u1\' generates 4 bits.\n                                                                                          : ... In instance optest\n  41: y <= u1 + s2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:65: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'s2\' generates 4 bits.\n                                                                                          : ... In instance optest\n  41: y <= u1 + s2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:66: Operator ADD expects 8 bits on the LHS, but LHS\'s VARREF \'s1\' generates 4 bits.\n                                                                                          : ... In instance optest\n  42: y <= s1 + u2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:66: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'u2\' generates 4 bits.\n                                                                                          : ... In instance optest\n  42: y <= s1 + u2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:67: Operator ADD expects 8 bits on the LHS, but LHS\'s VARREF \'s1\' generates 4 bits.\n                                                                                          : ... In instance optest\n  43: y <= s1 + s2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:67: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'s2\' generates 4 bits.\n                                                                                          : ... In instance optest\n  43: y <= s1 + s2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:69: Operator SUB expects 8 bits on the LHS, but LHS\'s VARREF \'u1\' generates 4 bits.\n                                                                                          : ... In instance optest\n  44: y <= u1 - u2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:69: Operator SUB expects 8 bits on the RHS, but RHS\'s VARREF \'u2\' generates 4 bits.\n                                                                                          : ... In instance optest\n  44: y <= u1 - u2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:70: Operator SUB expects 8 bits on the LHS, but LHS\'s VARREF \'u1\' generates 4 bits.\n                                                                                          : ... In instance optest\n  45: y <= u1 - s2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:70: Operator SUB expects 8 bits on the RHS, but RHS\'s VARREF \'s2\' generates 4 bits.\n                                                                                          : ... In instance optest\n  45: y <= u1 - s2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:71: Operator SUB expects 8 bits on the LHS, but LHS\'s VARREF \'s1\' generates 4 bits.\n                                                                                          : ... In instance optest\n  46: y <= s1 - u2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:71: Operator SUB expects 8 bits on the RHS, but RHS\'s VARREF \'u2\' generates 4 bits.\n                                                                                          : ... In instance optest\n  46: y <= s1 - u2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:72: Operator SUB expects 8 bits on the LHS, but LHS\'s VARREF \'s1\' generates 4 bits.\n                                                                                          : ... In instance optest\n  47: y <= s1 - s2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:72: Operator SUB expects 8 bits on the RHS, but RHS\'s VARREF \'s2\' generates 4 bits.\n                                                                                          : ... In instance optest\n  47: y <= s1 - s2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:79: Operator DIV expects 8 bits on the LHS, but LHS\'s VARREF \'u1\' generates 4 bits.\n                                                                                          : ... In instance optest\n  52: y <= u1 / u2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:79: Operator DIV expects 8 bits on the RHS, but RHS\'s VARREF \'u2\' generates 4 bits.\n                                                                                          : ... In instance optest\n  52: y <= u1 / u2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:80: Operator DIV expects 8 bits on the LHS, but LHS\'s VARREF \'u1\' generates 4 bits.\n                                                                                          : ... In instance optest\n  53: y <= u1 / s2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:80: Operator DIV expects 8 bits on the RHS, but RHS\'s VARREF \'s2\' generates 4 bits.\n                                                                                          : ... In instance optest\n  53: y <= u1 / s2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:81: Operator DIV expects 8 bits on the LHS, but LHS\'s VARREF \'s1\' generates 4 bits.\n                                                                                          : ... In instance optest\n  54: y <= s1 / u2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:81: Operator DIV expects 8 bits on the RHS, but RHS\'s VARREF \'u2\' generates 4 bits.\n                                                                                          : ... In instance optest\n  54: y <= s1 / u2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:82: Operator DIVS expects 8 bits on the LHS, but LHS\'s VARREF \'s1\' generates 4 bits.\n                                                                                          : ... In instance optest\n  55: y <= s1 / s2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:82: Operator DIVS expects 8 bits on the RHS, but RHS\'s VARREF \'s2\' generates 4 bits.\n                                                                                          : ... In instance optest\n  55: y <= s1 / s2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:84: Operator MODDIV expects 8 bits on the LHS, but LHS\'s VARREF \'u1\' generates 4 bits.\n                                                                                          : ... In instance optest\n  56: y <= u1 % u2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:84: Operator MODDIV expects 8 bits on the RHS, but RHS\'s VARREF \'u2\' generates 4 bits.\n                                                                                          : ... In instance optest\n  56: y <= u1 % u2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:85: Operator MODDIV expects 8 bits on the LHS, but LHS\'s VARREF \'u1\' generates 4 bits.\n                                                                                          : ... In instance optest\n  57: y <= u1 % s2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:85: Operator MODDIV expects 8 bits on the RHS, but RHS\'s VARREF \'s2\' generates 4 bits.\n                                                                                          : ... In instance optest\n  57: y <= u1 % s2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:86: Operator MODDIV expects 8 bits on the LHS, but LHS\'s VARREF \'s1\' generates 4 bits.\n                                                                                          : ... In instance optest\n  58: y <= s1 % u2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:86: Operator MODDIV expects 8 bits on the RHS, but RHS\'s VARREF \'u2\' generates 4 bits.\n                                                                                          : ... In instance optest\n  58: y <= s1 % u2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:87: Operator MODDIVS expects 8 bits on the LHS, but LHS\'s VARREF \'s1\' generates 4 bits.\n                                                                                          : ... In instance optest\n  59: y <= s1 % s2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:87: Operator MODDIVS expects 8 bits on the RHS, but RHS\'s VARREF \'s2\' generates 4 bits.\n                                                                                          : ... In instance optest\n  59: y <= s1 % s2;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:89: Operator POW expects 8 bits on the LHS, but LHS\'s CONST \'4\'h2\' generates 4 bits.\n                                                                                          : ... In instance optest\n  60: y <= 4\'d2 ** u1;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:90: Operator POW expects 8 bits on the LHS, but LHS\'s CONST \'4\'h2\' generates 4 bits.\n                                                                                          : ... In instance optest\n  61: y <= 4\'d2 ** s1;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:91: Operator POW expects 8 bits on the LHS, but LHS\'s CONST \'4\'sh2\' generates 4 bits.\n                                                                                          : ... In instance optest\n  62: y <= 4\'sd2 ** u1;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:92: Operator POW expects 8 bits on the LHS, but LHS\'s CONST \'4\'sh2\' generates 4 bits.\n                                                                                          : ... In instance optest\n  63: y <= 4\'sd2 ** s1;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:94: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'u1\' generates 4 bits.\n                                                                                          : ... In instance optest\n  64: y <= +u1;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:95: Operator NEGATE expects 8 bits on the LHS, but LHS\'s VARREF \'u1\' generates 4 bits.\n                                                                                          : ... In instance optest\n  65: y <= -u1;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:96: Operator NOT expects 8 bits on the LHS, but LHS\'s VARREF \'u1\' generates 4 bits.\n                                                                                          : ... In instance optest\n  66: y <= ~u1;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:97: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'u1\' generates 4 bits.\n                                                                                          : ... In instance optest\n  67: y <= !u1;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:97: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s LOGNOT generates 1 bits.\n                                                                                          : ... In instance optest\n  67: y <= !u1;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:99: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'s1\' generates 4 bits.\n                                                                                          : ... In instance optest\n  68: y <= +s1;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:100: Operator NEGATE expects 8 bits on the LHS, but LHS\'s VARREF \'s1\' generates 4 bits.\n                                                                                           : ... In instance optest\n  69: y <= -s1;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:101: Operator NOT expects 8 bits on the LHS, but LHS\'s VARREF \'s1\' generates 4 bits.\n                                                                                           : ... In instance optest\n  70: y <= ~s1;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:102: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'s1\' generates 4 bits.\n                                                                                           : ... In instance optest\n  71: y <= !s1;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:102: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s LOGNOT generates 1 bits.\n                                                                                           : ... In instance optest\n  71: y <= !s1;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:104: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 7 bits.\n                                                                                           : ... In instance optest\n  72: y <= { &u1, ~&u1, |u1, ~|u1, ^u1, ~^u1, ^~u1 };\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:105: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 7 bits.\n                                                                                           : ... In instance optest\n  73: y <= { &s1, ~&s1, |s1, ~|s1, ^s1, ~^s1, ^~s1 };\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:106: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 7 bits.\n                                                                                           : ... In instance optest\n  74: y <= { &u1[1:0], ~&u1[1:0], |u1[1:0], ~|u1[1:0], ^u1[1:0], ~^u1[1:0], ^~u1[1:0] };\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:107: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 7 bits.\n                                                                                           : ... In instance optest\n  75: y <= { &s1[1:0], ~&s1[1:0], |s1[1:0], ~|s1[1:0], ^s1[1:0], ~^s1[1:0], ^~s1[1:0] };\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:109: Logical Operator LOGAND expects 1 bit on the LHS, but LHS\'s SEL generates 2 bits.\n                                                                                           : ... In instance optest\n  76: y <= { u1[1:0] && u2[1:0], u1[1:0] && u2[1:0], !u1[1:0] };\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:109: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                           : ... In instance optest\n  76: y <= { u1[1:0] && u2[1:0], u1[1:0] && u2[1:0], !u1[1:0] };\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:109: Logical Operator LOGAND expects 1 bit on the LHS, but LHS\'s SEL generates 2 bits.\n                                                                                           : ... In instance optest\n  76: y <= { u1[1:0] && u2[1:0], u1[1:0] && u2[1:0], !u1[1:0] };\n                                         ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:109: Logical Operator LOGAND expects 1 bit on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                           : ... In instance optest\n  76: y <= { u1[1:0] && u2[1:0], u1[1:0] && u2[1:0], !u1[1:0] };\n                                         ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:109: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s SEL generates 2 bits.\n                                                                                           : ... In instance optest\n  76: y <= { u1[1:0] && u2[1:0], u1[1:0] && u2[1:0], !u1[1:0] };\n                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:109: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 3 bits.\n                                                                                           : ... In instance optest\n  76: y <= { u1[1:0] && u2[1:0], u1[1:0] && u2[1:0], !u1[1:0] };\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:114: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s VARREF \'u1\' generates 4 bits.\n                                                                                           : ... In instance optest\n  80: y <= u1[0] ? u1 : u2;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:114: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s VARREF \'u2\' generates 4 bits.\n                                                                                           : ... In instance optest\n  80: y <= u1[0] ? u1 : u2;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:115: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s VARREF \'u1\' generates 4 bits.\n                                                                                           : ... In instance optest\n  81: y <= u1[0] ? u1 : s2;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:115: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s VARREF \'s2\' generates 4 bits.\n                                                                                           : ... In instance optest\n  81: y <= u1[0] ? u1 : s2;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:116: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s VARREF \'s1\' generates 4 bits.\n                                                                                           : ... In instance optest\n  82: y <= u1[0] ? s1 : u2;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:116: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s VARREF \'u2\' generates 4 bits.\n                                                                                           : ... In instance optest\n  82: y <= u1[0] ? s1 : u2;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:117: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s VARREF \'s1\' generates 4 bits.\n                                                                                           : ... In instance optest\n  83: y <= u1[0] ? s1 : s2;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/operators.v:117: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s VARREF \'s2\' generates 4 bits.\n                                                                                           : ... In instance optest\n  83: y <= u1[0] ? s1 : s2;\n                 ^\n%Error: Exiting due to 104 warning(s)\n'
module optest(clk, mode, u1, s1, u2, s2, y);

input clk;
input [6:0] mode;

input [3:0] u1, u2;
input signed [3:0] s1, s2;

output reg [7:0] y;

always @(posedge clk) begin
	y <= 8'h42;
	case (mode)
		 0: y <= u1 << u2;
		 1: y <= u1 << s2;
		 2: y <= s1 << u2;
		 3: y <= s1 << s2;

		 4: y <= u1 >> u2;
		 5: y <= u1 >> s2;
		 6: y <= s1 >> u2;
		 7: y <= s1 >> s2;

		 8: y <= u1 <<< u2;
		 9: y <= u1 <<< s2;
		10: y <= s1 <<< u2;
		11: y <= s1 <<< s2;

		12: y <= u1 >>> u2;
		13: y <= u1 >>> s2;
		14: y <= s1 >>> u2;
		15: y <= s1 >>> s2;

		16: y <= u1 < u2;
		17: y <= u1 < s2;
		18: y <= s1 < u2;
		19: y <= s1 < s2;

		20: y <= u1 <= u2;
		21: y <= u1 <= s2;
		22: y <= s1 <= u2;
		23: y <= s1 <= s2;

		24: y <= u1 == u2;
		25: y <= u1 == s2;
		26: y <= s1 == u2;
		27: y <= s1 == s2;

		28: y <= u1 != u2;
		29: y <= u1 != s2;
		30: y <= s1 != u2;
		31: y <= s1 != s2;

		32: y <= u1 >= u2;
		33: y <= u1 >= s2;
		34: y <= s1 >= u2;
		35: y <= s1 >= s2;

		36: y <= u1 > u2;
		37: y <= u1 > s2;
		38: y <= s1 > u2;
		39: y <= s1 > s2;

		40: y <= u1 + u2;
		41: y <= u1 + s2;
		42: y <= s1 + u2;
		43: y <= s1 + s2;

		44: y <= u1 - u2;
		45: y <= u1 - s2;
		46: y <= s1 - u2;
		47: y <= s1 - s2;

		48: y <= u1 * u2;
		49: y <= u1 * s2;
		50: y <= s1 * u2;
		51: y <= s1 * s2;

		52: y <= u1 / u2;
		53: y <= u1 / s2;
		54: y <= s1 / u2;
		55: y <= s1 / s2;

		56: y <= u1 % u2;
		57: y <= u1 % s2;
		58: y <= s1 % u2;
		59: y <= s1 % s2;

		60: y <= 4'd2 ** u1;
		61: y <= 4'd2 ** s1;
		62: y <= 4'sd2 ** u1;
		63: y <= 4'sd2 ** s1;

		64: y <= +u1;
		65: y <= -u1;
		66: y <= ~u1;
		67: y <= !u1;

		68: y <= +s1;
		69: y <= -s1;
		70: y <= ~s1;
		71: y <= !s1;

		72: y <= { &u1, ~&u1, |u1, ~|u1, ^u1, ~^u1, ^~u1 };
		73: y <= { &s1, ~&s1, |s1, ~|s1, ^s1, ~^s1, ^~s1 };
		74: y <= { &u1[1:0], ~&u1[1:0], |u1[1:0], ~|u1[1:0], ^u1[1:0], ~^u1[1:0], ^~u1[1:0] };
		75: y <= { &s1[1:0], ~&s1[1:0], |s1[1:0], ~|s1[1:0], ^s1[1:0], ~^s1[1:0], ^~s1[1:0] };

		76: y <= { u1[1:0] && u2[1:0], u1[1:0] && u2[1:0], !u1[1:0] };
		77: y <= {4{u1[1:0]}};
		78: y <= {u1, u2} ^ {s1, s2};
		79: y <= {u1, u2} & {s1, s2};

		80: y <= u1[0] ? u1 : u2;
		81: y <= u1[0] ? u1 : s2;
		82: y <= u1[0] ? s1 : u2;
		83: y <= u1[0] ? s1 : s2;
	endcase
end

endmodule
module optest(clk, mode, u1, s1, u2, s2, y);


input clk;
input [6:0] mode;

input [3:0] u1, u2;
input signed [3:0] s1, s2;

output reg [7:0] y;

always @(posedge clk) begin
	y <= 8'h42;
	case (mode)
		 0: y <= u1 << u2;
		 1: y <= u1 << s2;
		 2: y <= s1 << u2;
		 3: y <= s1 << s2;

		 4: y <= u1 >> u2;
		 5: y <= u1 >> s2;
		 6: y <= s1 >> u2;
		 7: y <= s1 >> s2;

		 8: y <= u1 <<< u2;
		 9: y <= u1 <<< s2;
		10: y <= s1 <<< u2;
		11: y <= s1 <<< s2;

		12: y <= u1 >>> u2;
		13: y <= u1 >>> s2;
		14: y <= s1 >>> u2;
		15: y <= s1 >>> s2;

		16: y <= u1 < u2;
		17: y <= u1 < s2;
		18: y <= s1 < u2;
		19: y <= s1 < s2;

		20: y <= u1 <= u2;
		21: y <= u1 <= s2;
		22: y <= s1 <= u2;
		23: y <= s1 <= s2;

		24: y <= u1 == u2;
		25: y <= u1 == s2;
		26: y <= s1 == u2;
		27: y <= s1 == s2;

		28: y <= u1 != u2;
		29: y <= u1 != s2;
		30: y <= s1 != u2;
		31: y <= s1 != s2;

		32: y <= u1 >= u2;
		33: y <= u1 >= s2;
		34: y <= s1 >= u2;
		35: y <= s1 >= s2;

		36: y <= u1 > u2;
		37: y <= u1 > s2;
		38: y <= s1 > u2;
		39: y <= s1 > s2;

		40: y <= u1 + u2;
		41: y <= u1 + s2;
		42: y <= s1 + u2;
		43: y <= s1 + s2;

		44: y <= u1 - u2;
		45: y <= u1 - s2;
		46: y <= s1 - u2;
		47: y <= s1 - s2;

		48: y <= u1 * u2;
		49: y <= u1 * s2;
		50: y <= s1 * u2;
		51: y <= s1 * s2;

		52: y <= u1 / u2;
		53: y <= u1 / s2;
		54: y <= s1 / u2;
		55: y <= s1 / s2;

		56: y <= u1 % u2;
		57: y <= u1 % s2;
		58: y <= s1 % u2;
		59: y <= s1 % s2;

		60: y <= 4'd2 ** u1;
		61: y <= 4'd2 ** s1;
		62: y <= 4'sd2 ** u1;
		63: y <= 4'sd2 ** s1;

		64: y <= +u1;
		65: y <= -u1;
		66: y <= ~u1;
		67: y <= !u1;

		68: y <= +s1;
		69: y <= -s1;
		70: y <= ~s1;
		71: y <= !s1;

		72: y <= { &u1, ~&u1, |u1, ~|u1, ^u1, ~^u1, ^~u1 };
		73: y <= { &s1, ~&s1, |s1, ~|s1, ^s1, ~^s1, ^~s1 };
		74: y <= { &u1[1:0], ~&u1[1:0], |u1[1:0], ~|u1[1:0], ^u1[1:0], ~^u1[1:0], ^~u1[1:0] };
		75: y <= { &s1[1:0], ~&s1[1:0], |s1[1:0], ~|s1[1:0], ^s1[1:0], ~^s1[1:0], ^~s1[1:0] };

		76: y <= { u1[1:0] && u2[1:0], u1[1:0] && u2[1:0], !u1[1:0] };
		77: y <= {4{u1[1:0]}};
		78: y <= {u1, u2} ^ {s1, s2};
		79: y <= {u1, u2} & {s1, s2};

		80: y <= u1[0] ? u1 : u2;
		81: y <= u1[0] ? u1 : s2;
		82: y <= u1[0] ? s1 : u2;
		83: y <= u1[0] ? s1 : s2;
	endcase
end

endmodule