data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/always01.v
data/verilator_xmls/433212d4-680e-4257-abb8-6a1f5ae42eba.xml
module uut_always01(clock, reset, c3, c2, c1, c0);

input clock, reset;
output c3, c2, c1, c0;
reg [3:0] count;

assign {c3, c2, c1, c0} = count;

always @(posedge clock)
	count <= reset ? 0 : count + 1;

endmodule
module uut_always01(clock, reset, c3, c2, c1, c0);


input clock, reset;
output c3, c2, c1, c0;
reg [3:0] count;

assign {c3, c2, c1, c0} = count;

always @(posedge clock)
	count <= reset ? 0 : count + 1;

endmodule