data/full_repos/permissive/494664634/AxisPriorityArbiter/src/hdl/AxisPriorityArbiter.v
data/verilator_xmls/2683b94a-bf1b-4896-8735-7a8a9cd58e2b.xml
module PacketPriorityArbiter(
  input        clock,
  input        reset,
  input  [3:0] req,
  input  [3:0] fin,
  output [3:0] grant,
  input        ready
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
`endif
  reg  pending_0;
  reg  pending_1;
  reg  pending_2;
  reg  pending_3;
  reg  state;
  reg [3:0] granted;
  wire [3:0] _T_1 = {pending_3,pending_2,pending_1,pending_0};
  wire [3:0] _GEN_0 = _T_1 != 4'h0 ? _T_1 : req;
  wire [3:0] valid_req = ~state ? _GEN_0 : 4'h0;
  wire [3:0] granted_tmp = valid_req & 4'h8;
  wire  _GEN_1 = granted_tmp != 4'h0 & granted_tmp[0];
  wire  _GEN_2 = granted_tmp != 4'h0 & granted_tmp[1];
  wire  _GEN_3 = granted_tmp != 4'h0 & granted_tmp[2];
  wire  _GEN_4 = granted_tmp != 4'h0 & granted_tmp[3];
  wire [3:0] granted_tmp_1 = valid_req & 4'h4;
  wire  _GEN_5 = granted_tmp_1 != 4'h0 ? granted_tmp_1[0] : _GEN_1;
  wire  _GEN_6 = granted_tmp_1 != 4'h0 ? granted_tmp_1[1] : _GEN_2;
  wire  _GEN_7 = granted_tmp_1 != 4'h0 ? granted_tmp_1[2] : _GEN_3;
  wire  _GEN_8 = granted_tmp_1 != 4'h0 ? granted_tmp_1[3] : _GEN_4;
  wire [3:0] granted_tmp_2 = valid_req & 4'h2;
  wire  _GEN_9 = granted_tmp_2 != 4'h0 ? granted_tmp_2[0] : _GEN_5;
  wire  _GEN_10 = granted_tmp_2 != 4'h0 ? granted_tmp_2[1] : _GEN_6;
  wire  _GEN_11 = granted_tmp_2 != 4'h0 ? granted_tmp_2[2] : _GEN_7;
  wire  _GEN_12 = granted_tmp_2 != 4'h0 ? granted_tmp_2[3] : _GEN_8;
  wire [3:0] granted_tmp_3 = valid_req & 4'h1;
  wire  _GEN_13 = granted_tmp_3 != 4'h0 ? granted_tmp_3[0] : _GEN_9;
  wire  _GEN_14 = granted_tmp_3 != 4'h0 ? granted_tmp_3[1] : _GEN_10;
  wire  _GEN_15 = granted_tmp_3 != 4'h0 ? granted_tmp_3[2] : _GEN_11;
  wire  _GEN_16 = granted_tmp_3 != 4'h0 ? granted_tmp_3[3] : _GEN_12;
  wire  next_granted_0 = ~state & _GEN_13;
  wire  _grant_T = ready & next_granted_0;
  wire  next_granted_1 = ~state & _GEN_14;
  wire  _grant_T_1 = ready & next_granted_1;
  wire  next_granted_2 = ~state & _GEN_15;
  wire  _grant_T_2 = ready & next_granted_2;
  wire  next_granted_3 = ~state & _GEN_16;
  wire  _grant_T_3 = ready & next_granted_3;
  wire [3:0] _grant_T_4 = {_grant_T_3,_grant_T_2,_grant_T_1,_grant_T};
  wire [3:0] _granted_T = {next_granted_3,next_granted_2,next_granted_1,next_granted_0};
  wire [3:0] _T_9 = fin & grant;
  wire  _GEN_17 = _T_9 == 4'h0 | state;
  wire  _grant_T_6 = granted[0] & ready;
  wire  _grant_T_8 = granted[1] & ready;
  wire  _grant_T_10 = granted[2] & ready;
  wire  _grant_T_12 = granted[3] & ready;
  wire [3:0] _grant_T_13 = {_grant_T_12,_grant_T_10,_grant_T_8,_grant_T_6};
  wire [3:0] _GEN_29 = state ? _grant_T_13 : 4'h0;
  assign grant = ~state ? _grant_T_4 : _GEN_29;
  always @(posedge clock) begin
    if (reset) begin
      pending_0 <= 1'h0;
    end else if (~state) begin
      if (_granted_T != 4'h0) begin
        if (_T_9 == 4'h0) begin
          pending_0 <= 1'h0;
        end else begin
          pending_0 <= valid_req[0] ^ fin[0];
        end
      end
    end
    if (reset) begin
      pending_1 <= 1'h0;
    end else if (~state) begin
      if (_granted_T != 4'h0) begin
        if (_T_9 == 4'h0) begin
          pending_1 <= 1'h0;
        end else begin
          pending_1 <= valid_req[1] ^ fin[1];
        end
      end
    end
    if (reset) begin
      pending_2 <= 1'h0;
    end else if (~state) begin
      if (_granted_T != 4'h0) begin
        if (_T_9 == 4'h0) begin
          pending_2 <= 1'h0;
        end else begin
          pending_2 <= valid_req[2] ^ fin[2];
        end
      end
    end
    if (reset) begin
      pending_3 <= 1'h0;
    end else if (~state) begin
      if (_granted_T != 4'h0) begin
        if (_T_9 == 4'h0) begin
          pending_3 <= 1'h0;
        end else begin
          pending_3 <= valid_req[3] ^ fin[3];
        end
      end
    end
    if (reset) begin
      state <= 1'h0;
    end else if (~state) begin
      if (_granted_T != 4'h0) begin
        state <= _GEN_17;
      end
    end else if (state) begin
      if (_T_9 != 4'h0) begin
        state <= 1'h0;
      end
    end
    if (reset) begin
      granted <= 4'h0;
    end else if (~state) begin
      granted <= _granted_T;
    end else if (state) begin
      if (_T_9 != 4'h0) begin
        granted <= 4'h0;
      end
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  pending_0 = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  pending_1 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  pending_2 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  pending_3 = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  state = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  granted = _RAND_5[3:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module PacketPriorityArbiter(
  input        clock,
  input        reset,
  input  [3:0] req,
  input  [3:0] fin,
  output [3:0] grant,
  input        ready
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
`endif
  reg  pending_0;
  reg  pending_1;
  reg  pending_2;
  reg  pending_3;
  reg  state;
  reg [3:0] granted;
  wire [3:0] _T_1 = {pending_3,pending_2,pending_1,pending_0};
  wire [3:0] _GEN_0 = _T_1 != 4'h0 ? _T_1 : req;
  wire [3:0] valid_req = ~state ? _GEN_0 : 4'h0;
  wire [3:0] granted_tmp = valid_req & 4'h8;
  wire  _GEN_1 = granted_tmp != 4'h0 & granted_tmp[0];
  wire  _GEN_2 = granted_tmp != 4'h0 & granted_tmp[1];
  wire  _GEN_3 = granted_tmp != 4'h0 & granted_tmp[2];
  wire  _GEN_4 = granted_tmp != 4'h0 & granted_tmp[3];
  wire [3:0] granted_tmp_1 = valid_req & 4'h4;
  wire  _GEN_5 = granted_tmp_1 != 4'h0 ? granted_tmp_1[0] : _GEN_1;
  wire  _GEN_6 = granted_tmp_1 != 4'h0 ? granted_tmp_1[1] : _GEN_2;
  wire  _GEN_7 = granted_tmp_1 != 4'h0 ? granted_tmp_1[2] : _GEN_3;
  wire  _GEN_8 = granted_tmp_1 != 4'h0 ? granted_tmp_1[3] : _GEN_4;
  wire [3:0] granted_tmp_2 = valid_req & 4'h2;
  wire  _GEN_9 = granted_tmp_2 != 4'h0 ? granted_tmp_2[0] : _GEN_5;
  wire  _GEN_10 = granted_tmp_2 != 4'h0 ? granted_tmp_2[1] : _GEN_6;
  wire  _GEN_11 = granted_tmp_2 != 4'h0 ? granted_tmp_2[2] : _GEN_7;
  wire  _GEN_12 = granted_tmp_2 != 4'h0 ? granted_tmp_2[3] : _GEN_8;
  wire [3:0] granted_tmp_3 = valid_req & 4'h1;
  wire  _GEN_13 = granted_tmp_3 != 4'h0 ? granted_tmp_3[0] : _GEN_9;
  wire  _GEN_14 = granted_tmp_3 != 4'h0 ? granted_tmp_3[1] : _GEN_10;
  wire  _GEN_15 = granted_tmp_3 != 4'h0 ? granted_tmp_3[2] : _GEN_11;
  wire  _GEN_16 = granted_tmp_3 != 4'h0 ? granted_tmp_3[3] : _GEN_12;
  wire  next_granted_0 = ~state & _GEN_13;
  wire  _grant_T = ready & next_granted_0;
  wire  next_granted_1 = ~state & _GEN_14;
  wire  _grant_T_1 = ready & next_granted_1;
  wire  next_granted_2 = ~state & _GEN_15;
  wire  _grant_T_2 = ready & next_granted_2;
  wire  next_granted_3 = ~state & _GEN_16;
  wire  _grant_T_3 = ready & next_granted_3;
  wire [3:0] _grant_T_4 = {_grant_T_3,_grant_T_2,_grant_T_1,_grant_T};
  wire [3:0] _granted_T = {next_granted_3,next_granted_2,next_granted_1,next_granted_0};
  wire [3:0] _T_9 = fin & grant;
  wire  _GEN_17 = _T_9 == 4'h0 | state;
  wire  _grant_T_6 = granted[0] & ready;
  wire  _grant_T_8 = granted[1] & ready;
  wire  _grant_T_10 = granted[2] & ready;
  wire  _grant_T_12 = granted[3] & ready;
  wire [3:0] _grant_T_13 = {_grant_T_12,_grant_T_10,_grant_T_8,_grant_T_6};
  wire [3:0] _GEN_29 = state ? _grant_T_13 : 4'h0;
  assign grant = ~state ? _grant_T_4 : _GEN_29;
  always @(posedge clock) begin
    if (reset) begin
      pending_0 <= 1'h0;
    end else if (~state) begin
      if (_granted_T != 4'h0) begin
        if (_T_9 == 4'h0) begin
          pending_0 <= 1'h0;
        end else begin
          pending_0 <= valid_req[0] ^ fin[0];
        end
      end
    end
    if (reset) begin
      pending_1 <= 1'h0;
    end else if (~state) begin
      if (_granted_T != 4'h0) begin
        if (_T_9 == 4'h0) begin
          pending_1 <= 1'h0;
        end else begin
          pending_1 <= valid_req[1] ^ fin[1];
        end
      end
    end
    if (reset) begin
      pending_2 <= 1'h0;
    end else if (~state) begin
      if (_granted_T != 4'h0) begin
        if (_T_9 == 4'h0) begin
          pending_2 <= 1'h0;
        end else begin
          pending_2 <= valid_req[2] ^ fin[2];
        end
      end
    end
    if (reset) begin
      pending_3 <= 1'h0;
    end else if (~state) begin
      if (_granted_T != 4'h0) begin
        if (_T_9 == 4'h0) begin
          pending_3 <= 1'h0;
        end else begin
          pending_3 <= valid_req[3] ^ fin[3];
        end
      end
    end
    if (reset) begin
      state <= 1'h0;
    end else if (~state) begin
      if (_granted_T != 4'h0) begin
        state <= _GEN_17;
      end
    end else if (state) begin
      if (_T_9 != 4'h0) begin
        state <= 1'h0;
      end
    end
    if (reset) begin
      granted <= 4'h0;
    end else if (~state) begin
      granted <= _granted_T;
    end else if (state) begin
      if (_T_9 != 4'h0) begin
        granted <= 4'h0;
      end
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  pending_0 = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  pending_1 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  pending_2 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  pending_3 = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  state = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  granted = _RAND_5[3:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule