data/full_repos/permissive/477877520/coma_flotante/coma_flotante.srcs/sources_1/new/memoria.v
data/verilator_xmls/61de176f-41eb-459a-8afd-dfa3d9d2e552.xml
module memoria(
    input [31:0]a,b,
    input clk,
    output y

    );
    
    parameter S_inicial = 2'b00;  
    parameter S_guardar_numeros = 2'b01;  
    parameter S_revisar_si_cambiaron = 2'b10;  
    
    reg [1:0]state,nextstate;

    reg [31:0]aux_a;
    reg [31:0]aux_b;


    always@(posedge clk)begin
        state <= nextstate;
    end
   

    always@* begin
        case(state)
            S_inicial: 
                nextstate = S_guardar_numeros;
                
            S_guardar_numeros:
                nextstate = S_revisar_si_cambiaron;
                
            S_revisar_si_cambiaron:
                if( a == aux_a && b == aux_b ) nextstate = S_revisar_si_cambiaron;
                else nextstate = S_inicial;
 
        endcase        
    end
    

    always @* begin: HOLA     
        if(state == S_guardar_numeros) begin
            aux_a = a;
            aux_b = b;
        end             
    end
    
    assign y = (state == S_inicial) ? 1 : 0;
    
endmodule
module memoria(
    input [31:0]a,b,
    input clk,
    output y

    );

    
    parameter S_inicial = 2'b00;  
    parameter S_guardar_numeros = 2'b01;  
    parameter S_revisar_si_cambiaron = 2'b10;  
    
    reg [1:0]state,nextstate;

    reg [31:0]aux_a;
    reg [31:0]aux_b;


    always@(posedge clk)begin
        state <= nextstate;
    end
   

    always@* begin
        case(state)
            S_inicial: 
                nextstate = S_guardar_numeros;
                
            S_guardar_numeros:
                nextstate = S_revisar_si_cambiaron;
                
            S_revisar_si_cambiaron:
                if( a == aux_a && b == aux_b ) nextstate = S_revisar_si_cambiaron;
                else nextstate = S_inicial;
 
        endcase        
    end
    

    always @* begin: HOLA     
        if(state == S_guardar_numeros) begin
            aux_a = a;
            aux_b = b;
        end             
    end
    
    assign y = (state == S_inicial) ? 1 : 0;
    
endmodule