data/full_repos/permissive/527249789/src/mem.v
1: b'%Error: data/full_repos/permissive/527249789/src/mem.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/defines.v\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/defines.v.v\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/527249789/src/mem.v:6: Define or directive not defined: \'`InstAddrBus\'\n    input   [`InstAddrBus]                  pc_i,\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:6: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input   [`InstAddrBus]                  pc_i,\n                         ^\n%Error: data/full_repos/permissive/527249789/src/mem.v:7: Define or directive not defined: \'`InstAddrBus\'\n    output  [`InstAddrBus]                  pc_o,\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:10: Define or directive not defined: \'`RegAddrBus\'\n    input   [`RegAddrBus]                   waddr_i,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:11: Define or directive not defined: \'`RegBus\'\n    input   [`RegBus]                       wdata_i,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:12: Define or directive not defined: \'`AluOpBus\'\n    input   [`AluOpBus]                     aluop_i,\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:13: Define or directive not defined: \'`DataAddrBus\'\n    input   [`DataAddrBus]                  data_addr_i,\n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:14: Define or directive not defined: \'`DataBus\'\n    input   [`DataBus]                      data_rdata_i,\n             ^~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:16: Define or directive not defined: \'`RegBus\'\n    input   [`RegBus]                       exception_type_i,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:19: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output  reg[`RegBus]                    wdata_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:19: Define or directive not defined: \'`RegBus\'\n    output  reg[`RegBus]                    wdata_o,\n                ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:20: Define or directive not defined: \'`RegAddrBus\'\n    output  [`RegAddrBus]                   waddr_o,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:24: Define or directive not defined: \'`RegBus\'\n    input   [`RegBus]                       hi_i,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:25: Define or directive not defined: \'`RegBus\'\n    input   [`RegBus]                       lo_i,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:27: Define or directive not defined: \'`RegBus\'\n    output  [`RegBus]                       hi_o,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:28: Define or directive not defined: \'`RegBus\'\n    output  [`RegBus]                       lo_o,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:32: Define or directive not defined: \'`RegBus\'\n    input   [`RegBus]                       cp0_reg_wdata_i,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:33: Define or directive not defined: \'`RegAddrBus\'\n    input   [`RegAddrBus]                   cp0_reg_waddr_i,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:35: Define or directive not defined: \'`RegBus\'\n    output  [`RegBus]                       cp0_reg_wdata_o,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:36: Define or directive not defined: \'`RegAddrBus\'\n    output  [`RegAddrBus]                   cp0_reg_waddr_o,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:38: Define or directive not defined: \'`RegBus\'\n    input   [`RegBus]                       commit_cp0_reg_wdata,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:39: Define or directive not defined: \'`RegAddrBus\'\n    input   [`RegAddrBus]                   commit_cp0_reg_waddr,\n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:40: Define or directive not defined: \'`RegBus\'\n    input   [`RegBus]                       cp0_reg_status,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:41: Define or directive not defined: \'`RegBus\'\n    input   [`RegBus]                       cp0_reg_epc,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:42: Define or directive not defined: \'`RegBus\'\n    input   [`RegBus]                       cp0_reg_cause,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:43: Define or directive not defined: \'`RegBus\'\n    input   [`RegBus]                       cp0_reg_ebase,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:44: Define or directive not defined: \'`RegBus\'\n    output  reg[`RegBus]                    latest_cp0_reg_epc,\n                ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:45: Define or directive not defined: \'`RegBus\'\n    output  reg[`RegBus]                    latest_cp0_reg_ebase,\n                ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:48: Define or directive not defined: \'`RegBus\'\n    output  reg[`RegBus]                    exception_type_o\n                ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:51: Define or directive not defined: \'`RegBus\'\nreg [`RegBus] latest_cp0_reg_status;\n     ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:51: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg [`RegBus] latest_cp0_reg_status;\n            ^\n%Error: data/full_repos/permissive/527249789/src/mem.v:52: Define or directive not defined: \'`RegBus\'\nreg [`RegBus] latest_cp0_reg_cause;\n     ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:52: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg [`RegBus] latest_cp0_reg_cause;\n            ^\n%Error: data/full_repos/permissive/527249789/src/mem.v:65: Define or directive not defined: \'`RstEnable\'\n    if (resetn == `RstEnable) begin\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:66: Define or directive not defined: \'`ZeroWord\'\n        wen_o = `ZeroWord;\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:67: Define or directive not defined: \'`ZeroWord\'\n        wdata_o = `ZeroWord;\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:68: Define or directive not defined: \'`ZeroWord\'\n    end else if (exception_type_i == `ZeroWord) begin\n                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:72: Define or directive not defined: \'`EXE_LW_OP\'\n            `EXE_LW_OP: begin\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:75: Define or directive not defined: \'`EXE_LB_OP\'\n            `EXE_LB_OP: begin\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:90: Define or directive not defined: \'`ZeroWord\'\n                        wdata_o = `ZeroWord;\n                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:94: Define or directive not defined: \'`EXE_LBU_OP\'\n            `EXE_LBU_OP: begin\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:109: Define or directive not defined: \'`ZeroWord\'\n                        wdata_o = `ZeroWord;\n                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:113: Define or directive not defined: \'`EXE_LH_OP\'\n            `EXE_LH_OP: begin\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:122: Define or directive not defined: \'`ZeroWord\'\n                        wdata_o = `ZeroWord;\n                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:126: Define or directive not defined: \'`EXE_LHU_OP\'\n            `EXE_LHU_OP: begin\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:135: Define or directive not defined: \'`ZeroWord\'\n                        wdata_o = `ZeroWord;\n                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:143: Define or directive not defined: \'`WriteDisable\'\n        wen_o = `WriteDisable;\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:144: Define or directive not defined: \'`ZeroWord\'\n        wdata_o = `ZeroWord;\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/mem.v:149: Define or directive not defined: \'`RstEnable\'\n    if (resetn == `RstEnable) begin\n                  ^~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module mem(
    input                                   resetn,

    input   [`InstAddrBus]                  pc_i,
    output  [`InstAddrBus]                  pc_o,

    input                                   wen_i,
    input   [`RegAddrBus]                   waddr_i,
    input   [`RegBus]                       wdata_i,
    input   [`AluOpBus]                     aluop_i,
    input   [`DataAddrBus]                  data_addr_i,
    input   [`DataBus]                      data_rdata_i,
    input                                   is_in_delayslot_i,
    input   [`RegBus]                       exception_type_i,

    output  reg                             wen_o,
    output  reg[`RegBus]                    wdata_o,
    output  [`RegAddrBus]                   waddr_o,


    input                                   hilo_wen_i,
    input   [`RegBus]                       hi_i,
    input   [`RegBus]                       lo_i,
    output                                  hilo_wen_o,
    output  [`RegBus]                       hi_o,
    output  [`RegBus]                       lo_o,


    input                                   cp0_reg_wen_i,
    input   [`RegBus]                       cp0_reg_wdata_i,
    input   [`RegAddrBus]                   cp0_reg_waddr_i,
    output                                  cp0_reg_wen_o,
    output  [`RegBus]                       cp0_reg_wdata_o,
    output  [`RegAddrBus]                   cp0_reg_waddr_o,
    input                                   commit_cp0_reg_wen,
    input   [`RegBus]                       commit_cp0_reg_wdata,
    input   [`RegAddrBus]                   commit_cp0_reg_waddr,
    input   [`RegBus]                       cp0_reg_status,
    input   [`RegBus]                       cp0_reg_epc,
    input   [`RegBus]                       cp0_reg_cause,
    input   [`RegBus]                       cp0_reg_ebase,
    output  reg[`RegBus]                    latest_cp0_reg_epc,
    output  reg[`RegBus]                    latest_cp0_reg_ebase,

    output                                  is_in_delayslot_o,
    output  reg[`RegBus]                    exception_type_o
);

reg [`RegBus] latest_cp0_reg_status;
reg [`RegBus] latest_cp0_reg_cause;

assign pc_o = pc_i;
assign waddr_o = waddr_i;
assign is_in_delayslot_o = is_in_delayslot_i;
assign hilo_wen_o = hilo_wen_i;
assign hi_o = hi_i;
assign lo_o = lo_i;
assign cp0_reg_wen_o = cp0_reg_wen_i;
assign cp0_reg_wdata_o = cp0_reg_wdata_i;
assign cp0_reg_waddr_o = cp0_reg_waddr_i;

always @(*) begin
    if (resetn == `RstEnable) begin
        wen_o = `ZeroWord;
        wdata_o = `ZeroWord;
    end else if (exception_type_i == `ZeroWord) begin
        wen_o = wen_i;
        wdata_o = wdata_i;
        case (aluop_i)
            `EXE_LW_OP: begin
                wdata_o = data_rdata_i;
            end
            `EXE_LB_OP: begin
                case (data_addr_i[1:0])
                    2'b00: begin
                        wdata_o = {{24{data_rdata_i[7]}}, data_rdata_i[7:0]};
                    end
                    2'b01: begin
                        wdata_o = {{24{data_rdata_i[15]}}, data_rdata_i[15:8]};
                    end
                    2'b10: begin
                        wdata_o = {{24{data_rdata_i[23]}}, data_rdata_i[23:16]};
                    end
                    2'b11: begin
                        wdata_o = {{24{data_rdata_i[31]}}, data_rdata_i[31:24]};
                    end
                    default: begin
                        wdata_o = `ZeroWord;
                    end
                endcase
            end
            `EXE_LBU_OP: begin
                case (data_addr_i[1:0])
                    2'b00: begin
                        wdata_o = {{24'd0}, data_rdata_i[7:0]};
                    end
                    2'b01: begin
                        wdata_o = {{24'd0}, data_rdata_i[15:8]};
                    end
                    2'b10: begin
                        wdata_o = {{24'd0}, data_rdata_i[23:16]};
                    end
                    2'b11: begin
                        wdata_o = {{24'd0}, data_rdata_i[31:24]};
                    end
                    default: begin
                        wdata_o = `ZeroWord;
                    end
                endcase
            end
            `EXE_LH_OP: begin
                case (data_addr_i[1:0])
                    2'b00: begin
                        wdata_o = {{16{data_rdata_i[15]}}, data_rdata_i[15:0]};
                    end
                    2'b10: begin
                        wdata_o = {{16{data_rdata_i[31]}}, data_rdata_i[31:16]};
                    end
                    default: begin
                        wdata_o = `ZeroWord;
                    end
                endcase
            end
            `EXE_LHU_OP: begin
                case (data_addr_i[1:0])
                    2'b00: begin
                        wdata_o = {{16'd0}, data_rdata_i[15:0]};
                    end
                    2'b10: begin
                        wdata_o = {{16'd0}, data_rdata_i[31:16]};
                    end
                    default: begin
                        wdata_o = `ZeroWord;
                    end
                endcase
            end
            default: begin
            end
        endcase
    end else begin
        wen_o = `WriteDisable;
        wdata_o = `ZeroWord;
    end
end

always @(*) begin
    if (resetn == `RstEnable) begin
        exception_type_o = `ZeroWord;
    end else begin
        exception_type_o = `ZeroWord;
        if (pc_i != `ZeroWord) begin
            if (exception_type_i[8] == 1'b1) begin

                exception_type_o = `EXECEPTION_SYS;
            end else if (exception_type_i[9] == 1'b1) begin

                exception_type_o = `EXECEPTION_INSTVALID;
            end else if (exception_type_i[10] == 1'b1) begin

                exception_type_o = `EXECEPTION_OV;
            end else if (exception_type_i[11] == 1'b1) begin

                exception_type_o = `EXECEPTION_BREAK;
            end else if (exception_type_i[12] == 1'b1) begin

                exception_type_o = `EXECEPTION_ERET;
            end else if (exception_type_i[13] == 1'b1) begin

                exception_type_o = `EXECEPTION_ADES;
            end else if (exception_type_i[14] == 1'b1) begin

                exception_type_o = `EXECEPTION_ADEL;
            end else if (((latest_cp0_reg_cause[15:8] & latest_cp0_reg_status[15:8]) != 8'd0) &&
                         ((latest_cp0_reg_status[1] == 1'b0) && (latest_cp0_reg_status[0] == 1'b1))) begin

                exception_type_o = `EXECEPTION_INT;
            end else begin
            end
        end else begin
        end
    end
end






always @(*) begin
    if (resetn == `RstEnable) begin
        latest_cp0_reg_status = `ZeroWord;
    end else if ((commit_cp0_reg_wen == `WriteEnable) && (commit_cp0_reg_waddr == `CP0_REG_STATUS)) begin
        latest_cp0_reg_status = commit_cp0_reg_wdata;
    end else begin
        latest_cp0_reg_status = cp0_reg_status;
    end
end

always @(*) begin
    if (resetn == `RstEnable) begin
        latest_cp0_reg_epc = `ZeroWord;
    end else if ((commit_cp0_reg_wen == `WriteEnable) && (commit_cp0_reg_waddr == `CP0_REG_EPC)) begin
        latest_cp0_reg_epc = commit_cp0_reg_wdata;
    end else begin
        latest_cp0_reg_epc = cp0_reg_epc;
    end
end

always @(*) begin
    if (resetn == `RstEnable) begin
        latest_cp0_reg_cause = `ZeroWord;
    end else if ((commit_cp0_reg_wen == `WriteEnable) && (commit_cp0_reg_waddr == `CP0_REG_CAUSE)) begin
        latest_cp0_reg_cause[9:8] = commit_cp0_reg_wdata[9:8];
        latest_cp0_reg_cause[22] = commit_cp0_reg_wdata[22];
        latest_cp0_reg_cause[23] = commit_cp0_reg_wdata[23];
    end else begin
        latest_cp0_reg_cause = cp0_reg_cause;
    end
end

always @(*) begin
    if (resetn == `RstEnable) begin
        latest_cp0_reg_ebase = `ZeroWord;
    end else if ((commit_cp0_reg_wen == `WriteEnable) && (commit_cp0_reg_waddr == `CP0_REG_EBASE)) begin
        latest_cp0_reg_ebase = commit_cp0_reg_wdata;
    end else begin
        latest_cp0_reg_ebase = cp0_reg_ebase;
    end
end





endmodule
module mem(
    input                                   resetn,

    input   [`InstAddrBus]                  pc_i,
    output  [`InstAddrBus]                  pc_o,

    input                                   wen_i,
    input   [`RegAddrBus]                   waddr_i,
    input   [`RegBus]                       wdata_i,
    input   [`AluOpBus]                     aluop_i,
    input   [`DataAddrBus]                  data_addr_i,
    input   [`DataBus]                      data_rdata_i,
    input                                   is_in_delayslot_i,
    input   [`RegBus]                       exception_type_i,

    output  reg                             wen_o,
    output  reg[`RegBus]                    wdata_o,
    output  [`RegAddrBus]                   waddr_o,


    input                                   hilo_wen_i,
    input   [`RegBus]                       hi_i,
    input   [`RegBus]                       lo_i,
    output                                  hilo_wen_o,
    output  [`RegBus]                       hi_o,
    output  [`RegBus]                       lo_o,


    input                                   cp0_reg_wen_i,
    input   [`RegBus]                       cp0_reg_wdata_i,
    input   [`RegAddrBus]                   cp0_reg_waddr_i,
    output                                  cp0_reg_wen_o,
    output  [`RegBus]                       cp0_reg_wdata_o,
    output  [`RegAddrBus]                   cp0_reg_waddr_o,
    input                                   commit_cp0_reg_wen,
    input   [`RegBus]                       commit_cp0_reg_wdata,
    input   [`RegAddrBus]                   commit_cp0_reg_waddr,
    input   [`RegBus]                       cp0_reg_status,
    input   [`RegBus]                       cp0_reg_epc,
    input   [`RegBus]                       cp0_reg_cause,
    input   [`RegBus]                       cp0_reg_ebase,
    output  reg[`RegBus]                    latest_cp0_reg_epc,
    output  reg[`RegBus]                    latest_cp0_reg_ebase,

    output                                  is_in_delayslot_o,
    output  reg[`RegBus]                    exception_type_o
);


reg [`RegBus] latest_cp0_reg_status;
reg [`RegBus] latest_cp0_reg_cause;

assign pc_o = pc_i;
assign waddr_o = waddr_i;
assign is_in_delayslot_o = is_in_delayslot_i;
assign hilo_wen_o = hilo_wen_i;
assign hi_o = hi_i;
assign lo_o = lo_i;
assign cp0_reg_wen_o = cp0_reg_wen_i;
assign cp0_reg_wdata_o = cp0_reg_wdata_i;
assign cp0_reg_waddr_o = cp0_reg_waddr_i;

always @(*) begin
    if (resetn == `RstEnable) begin
        wen_o = `ZeroWord;
        wdata_o = `ZeroWord;
    end else if (exception_type_i == `ZeroWord) begin
        wen_o = wen_i;
        wdata_o = wdata_i;
        case (aluop_i)
            `EXE_LW_OP: begin
                wdata_o = data_rdata_i;
            end
            `EXE_LB_OP: begin
                case (data_addr_i[1:0])
                    2'b00: begin
                        wdata_o = {{24{data_rdata_i[7]}}, data_rdata_i[7:0]};
                    end
                    2'b01: begin
                        wdata_o = {{24{data_rdata_i[15]}}, data_rdata_i[15:8]};
                    end
                    2'b10: begin
                        wdata_o = {{24{data_rdata_i[23]}}, data_rdata_i[23:16]};
                    end
                    2'b11: begin
                        wdata_o = {{24{data_rdata_i[31]}}, data_rdata_i[31:24]};
                    end
                    default: begin
                        wdata_o = `ZeroWord;
                    end
                endcase
            end
            `EXE_LBU_OP: begin
                case (data_addr_i[1:0])
                    2'b00: begin
                        wdata_o = {{24'd0}, data_rdata_i[7:0]};
                    end
                    2'b01: begin
                        wdata_o = {{24'd0}, data_rdata_i[15:8]};
                    end
                    2'b10: begin
                        wdata_o = {{24'd0}, data_rdata_i[23:16]};
                    end
                    2'b11: begin
                        wdata_o = {{24'd0}, data_rdata_i[31:24]};
                    end
                    default: begin
                        wdata_o = `ZeroWord;
                    end
                endcase
            end
            `EXE_LH_OP: begin
                case (data_addr_i[1:0])
                    2'b00: begin
                        wdata_o = {{16{data_rdata_i[15]}}, data_rdata_i[15:0]};
                    end
                    2'b10: begin
                        wdata_o = {{16{data_rdata_i[31]}}, data_rdata_i[31:16]};
                    end
                    default: begin
                        wdata_o = `ZeroWord;
                    end
                endcase
            end
            `EXE_LHU_OP: begin
                case (data_addr_i[1:0])
                    2'b00: begin
                        wdata_o = {{16'd0}, data_rdata_i[15:0]};
                    end
                    2'b10: begin
                        wdata_o = {{16'd0}, data_rdata_i[31:16]};
                    end
                    default: begin
                        wdata_o = `ZeroWord;
                    end
                endcase
            end
            default: begin
            end
        endcase
    end else begin
        wen_o = `WriteDisable;
        wdata_o = `ZeroWord;
    end
end

always @(*) begin
    if (resetn == `RstEnable) begin
        exception_type_o = `ZeroWord;
    end else begin
        exception_type_o = `ZeroWord;
        if (pc_i != `ZeroWord) begin
            if (exception_type_i[8] == 1'b1) begin

                exception_type_o = `EXECEPTION_SYS;
            end else if (exception_type_i[9] == 1'b1) begin

                exception_type_o = `EXECEPTION_INSTVALID;
            end else if (exception_type_i[10] == 1'b1) begin

                exception_type_o = `EXECEPTION_OV;
            end else if (exception_type_i[11] == 1'b1) begin

                exception_type_o = `EXECEPTION_BREAK;
            end else if (exception_type_i[12] == 1'b1) begin

                exception_type_o = `EXECEPTION_ERET;
            end else if (exception_type_i[13] == 1'b1) begin

                exception_type_o = `EXECEPTION_ADES;
            end else if (exception_type_i[14] == 1'b1) begin

                exception_type_o = `EXECEPTION_ADEL;
            end else if (((latest_cp0_reg_cause[15:8] & latest_cp0_reg_status[15:8]) != 8'd0) &&
                         ((latest_cp0_reg_status[1] == 1'b0) && (latest_cp0_reg_status[0] == 1'b1))) begin

                exception_type_o = `EXECEPTION_INT;
            end else begin
            end
        end else begin
        end
    end
end






always @(*) begin
    if (resetn == `RstEnable) begin
        latest_cp0_reg_status = `ZeroWord;
    end else if ((commit_cp0_reg_wen == `WriteEnable) && (commit_cp0_reg_waddr == `CP0_REG_STATUS)) begin
        latest_cp0_reg_status = commit_cp0_reg_wdata;
    end else begin
        latest_cp0_reg_status = cp0_reg_status;
    end
end

always @(*) begin
    if (resetn == `RstEnable) begin
        latest_cp0_reg_epc = `ZeroWord;
    end else if ((commit_cp0_reg_wen == `WriteEnable) && (commit_cp0_reg_waddr == `CP0_REG_EPC)) begin
        latest_cp0_reg_epc = commit_cp0_reg_wdata;
    end else begin
        latest_cp0_reg_epc = cp0_reg_epc;
    end
end

always @(*) begin
    if (resetn == `RstEnable) begin
        latest_cp0_reg_cause = `ZeroWord;
    end else if ((commit_cp0_reg_wen == `WriteEnable) && (commit_cp0_reg_waddr == `CP0_REG_CAUSE)) begin
        latest_cp0_reg_cause[9:8] = commit_cp0_reg_wdata[9:8];
        latest_cp0_reg_cause[22] = commit_cp0_reg_wdata[22];
        latest_cp0_reg_cause[23] = commit_cp0_reg_wdata[23];
    end else begin
        latest_cp0_reg_cause = cp0_reg_cause;
    end
end

always @(*) begin
    if (resetn == `RstEnable) begin
        latest_cp0_reg_ebase = `ZeroWord;
    end else if ((commit_cp0_reg_wen == `WriteEnable) && (commit_cp0_reg_waddr == `CP0_REG_EBASE)) begin
        latest_cp0_reg_ebase = commit_cp0_reg_wdata;
    end else begin
        latest_cp0_reg_ebase = cp0_reg_ebase;
    end
end





endmodule