data/full_repos/permissive/478063538/REGFILE1.v
data/verilator_xmls/977d9fd2-6721-4e77-abba-0cae48e8e071.xml
module REGFILE1 (
	input clk, we,
	input [7:0] Ddata,
	input [1:0] Daddr, Aaddr, Baddr,
	output [7:0] Adata, Bdata
);

	reg[7:0] RF[3:0];
	

	always @ (posedge clk)
	begin
		if(we) RF[Daddr] <= Ddata;
	end
	

	assign Adata = RF[Aaddr];
	assign Bdata = RF[Baddr];

endmodule
module REGFILE1 (
	input clk, we,
	input [7:0] Ddata,
	input [1:0] Daddr, Aaddr, Baddr,
	output [7:0] Adata, Bdata
);


	reg[7:0] RF[3:0];
	

	always @ (posedge clk)
	begin
		if(we) RF[Daddr] <= Ddata;
	end
	

	assign Adata = RF[Aaddr];
	assign Bdata = RF[Baddr];

endmodule