data/full_repos/permissive/433225833/Testbench/delay_reg_tb.v
1: b'%Error: data/full_repos/permissive/433225833/Testbench/delay_reg_tb.v:14: syntax error, unexpected \'@\'\n    @(negedge clk)\n    ^\n%Error: data/full_repos/permissive/433225833/Testbench/delay_reg_tb.v:17: syntax error, unexpected \'@\'\n    @(negedge clk)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/433225833/Testbench/delay_reg_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #6;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/433225833/Testbench/delay_reg_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #1 clk = ~clk;\n    ^\n%Error: data/full_repos/permissive/433225833/Testbench/delay_reg_tb.v:36: Unsupported or unknown PLI call: $monitor\n    $monitor("%3d\\t%h\\t%h\\t%h\\t%h", $time, data_in, clk, reset, data_out);\n    ^~~~~~~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module delay_reg_tb();
	parameter DEPTH=4;
  parameter WIDTH=32;

  reg [WIDTH-1:0] data_in;
  reg [7:0] in_pos;
  reg clk, reset;
  wire [WIDTH-1:0] data_out;
  
  initial begin
    clk = 0;
    in_pos = 4;
    reset = 1;
    @(negedge clk)
    reset = 0;
    data_in = 1;
    @(negedge clk)
    data_in = 2;
    @(negedge clk)
    data_in = 3;
    @(negedge clk)
    data_in = 4;
    @(negedge clk)
    data_in = 5;
    @(negedge clk)
    data_in = 6;
    #6;
    $finish;
  end
  
  always
    #1 clk = ~clk;
  
  initial begin
    $display("  T\tdin\t\tclk\trst\tdout");
    $monitor("%3d\t%h\t%h\t%h\t%h", $time, data_in, clk, reset, data_out);

  end
  
  delay_reg #(.DEPTH(DEPTH), .WIDTH(WIDTH)) dut 
  (.data_in(data_in), .in_pos(in_pos), .data_out(data_out), .clk(clk), .reset(reset));
  
endmodule
module delay_reg_tb();

	parameter DEPTH=4;
  parameter WIDTH=32;

  reg [WIDTH-1:0] data_in;
  reg [7:0] in_pos;
  reg clk, reset;
  wire [WIDTH-1:0] data_out;
  
  initial begin
    clk = 0;
    in_pos = 4;
    reset = 1;
    @(negedge clk)
    reset = 0;
    data_in = 1;
    @(negedge clk)
    data_in = 2;
    @(negedge clk)
    data_in = 3;
    @(negedge clk)
    data_in = 4;
    @(negedge clk)
    data_in = 5;
    @(negedge clk)
    data_in = 6;
    #6;
    $finish;
  end
  
  always
    #1 clk = ~clk;
  
  initial begin
    $display("  T\tdin\t\tclk\trst\tdout");
    $monitor("%3d\t%h\t%h\t%h\t%h", $time, data_in, clk, reset, data_out);

  end
  
  delay_reg #(.DEPTH(DEPTH), .WIDTH(WIDTH)) dut 
  (.data_in(data_in), .in_pos(in_pos), .data_out(data_out), .clk(clk), .reset(reset));
  
endmodule