data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:111: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_in;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:112: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_out;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:113: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_oeb;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:125: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_out = {user_gpio_out, pwmA_q0, pwmB_q0, pwmC_q0, pwmA_n0, pwmB_n0, pwmC_n0, user_halt, {(`MPRJ_IO_PADS-1-8-6-1){1'b0}}};\n                                                                                                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:126: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_oeb = {user_gpio_en,  {(`MPRJ_IO_PADS-1-8){rst}}};\n                                      ^~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module cla_adder_parm #(parameter D = 16) (
  input          carry_i,
  input  [D-1:0] A,
  input  [D-1:0] B,
  output [D-1:0] result_o, 
  output         carry_o
);
  
  wire [D-0:0] w_C;
  wire [D-1:0] w_G, w_P; 

  assign w_C[0]  = carry_i;
  assign carry_o = w_C[D-0];

  genvar ii;
  generate
    for (ii=0; ii<D; ii=ii+1) 
      begin
        assign result_o[ii] = A[ii]   ^  B[ii] ^ w_C[ii];
        assign w_G[ii]      = A[ii]   &  B[ii];
        assign w_P[ii]      = A[ii]   |  B[ii];
        assign w_C[ii+1]    = w_G[ii] | (w_P[ii] & w_C[ii]);
      end
  endgenerate
 
endmodule
module cla_adder_parm #(parameter D = 16) (
  input          carry_i,
  input  [D-1:0] A,
  input  [D-1:0] B,
  output [D-1:0] result_o, 
  output         carry_o
);

  
  wire [D-0:0] w_C;
  wire [D-1:0] w_G, w_P; 

  assign w_C[0]  = carry_i;
  assign carry_o = w_C[D-0];

  genvar ii;
  generate
    for (ii=0; ii<D; ii=ii+1) 
      begin
        assign result_o[ii] = A[ii]   ^  B[ii] ^ w_C[ii];
        assign w_G[ii]      = A[ii]   &  B[ii];
        assign w_P[ii]      = A[ii]   |  B[ii];
        assign w_C[ii+1]    = w_G[ii] | (w_P[ii] & w_C[ii]);
      end
  endgenerate
 
endmodule