data/full_repos/permissive/444277419/Verilog/com_32.v
data/verilator_xmls/f236d59c-7b1b-47ae-8576-36f947522bed.xml
module com_32(a,b,c,co,sum);
input a,b,c;
output co,sum;
assign co = (a&b)|(c&(a|b));
assign sum = a^b^c;
endmodule
module com_32(a,b,c,co,sum);

input a,b,c;
output co,sum;
assign co = (a&b)|(c&(a|b));
assign sum = a^b^c;
endmodule