data/full_repos/permissive/421048855/Circuits/Sequential Logic/Counters/Count clock.v
1: b'%Error: Cannot find file containing module: Logic/Counters,data/full_repos/permissive/421048855\n        ... Looked in:\n             data/full_repos/permissive/421048855/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/421048855\n             data/full_repos/permissive/421048855/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/421048855.v\n             data/full_repos/permissive/421048855/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/421048855.sv\n             Logic/Counters,data/full_repos/permissive/421048855\n             Logic/Counters,data/full_repos/permissive/421048855.v\n             Logic/Counters,data/full_repos/permissive/421048855.sv\n             obj_dir/Logic/Counters,data/full_repos/permissive/421048855\n             obj_dir/Logic/Counters,data/full_repos/permissive/421048855.v\n             obj_dir/Logic/Counters,data/full_repos/permissive/421048855.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/421048855/Circuits/Sequential\n%Error: Cannot find file containing module: Logic/Counters/Count\n%Error: Cannot find file containing module: clock.v\n%Error: Exiting due to 4 error(s)\n'
module cnt(
input clk,
input reset,
input ena,
input [3:0] upper,
output reg [3:0] num,
output reg over
);
always @(posedge clk) begin
	if(reset) begin
		num <= 'd0;
	end
	else if(ena) begin
		if(num >= upper) begin
			num <= 'd0;
		end
		else begin
			num <= num + 'd1;
		end
	end
end
assign over = ((num == upper) && ena) ? 1'b1 : 1'b0;
endmodule
module cnt(
input clk,
input reset,
input ena,
input [3:0] upper,
output reg [3:0] num,
output reg over
);

always @(posedge clk) begin
	if(reset) begin
		num <= 'd0;
	end
	else if(ena) begin
		if(num >= upper) begin
			num <= 'd0;
		end
		else begin
			num <= num + 'd1;
		end
	end
end
assign over = ((num == upper) && ena) ? 1'b1 : 1'b0;
endmodule