data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:7: Multiple top level modules\n                                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                          : ... Top module \'partsel_test001\'\nmodule partsel_test001(input [2:0] idx, input [31:0] data, output [3:0] slice_up, slice_down);\n       ^~~~~~~~~~~~~~~\n                                                                                          : ... Top module \'partsel_test002\'\nmodule partsel_test002 (\n       ^~~~~~~~~~~~~~~\n                                                                                          : ... Top module \'partsel_test003\'\nmodule partsel_test003(input [2:0] a, b, input [31:0] din, output [3:0] dout);\n       ^~~~~~~~~~~~~~~\n                                                                                          : ... Top module \'partsel_test004\'\nmodule partsel_test004 (\n       ^~~~~~~~~~~~~~~\n                                                                                          : ... Top module \'partsel_test005\'\nmodule partsel_test005 (\n       ^~~~~~~~~~~~~~~\n                                                                                          : ... Top module \'partsel_test006\'\nmodule partsel_test006 (\n       ^~~~~~~~~~~~~~~\n                                                                                          : ... Top module \'partsel_test007\'\nmodule partsel_test007 (\n       ^~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:65: Bit extraction of var[31:0] requires 5 bit index, not 3 bits.\n                                                                                        : ... In instance partsel_test003\nassign dout = din[a*b +: 2];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:65: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                        : ... In instance partsel_test003\nassign dout = din[a*b +: 2];\n            ^\n%Warning-LITENDIAN: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:10: Little bit endian vector: MSB < LSB of bit range: 0:7\n input [0:7] b,\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:13: Little bit endian vector: MSB < LSB of bit range: 0:7\n output [0:7] x4, x5, x6,\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:15: Little bit endian vector: MSB < LSB of bit range: 0:7\n output [0:7] y4, y5, y6,\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:17: Little bit endian vector: MSB < LSB of bit range: 0:7\n output [0:7] z4, z5, z6,\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:19: Little bit endian vector: MSB < LSB of bit range: 0:7\n output [0:7] w4, w5, w6,\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:21: Little bit endian vector: MSB < LSB of bit range: 0:7\n output [0:7] q1, q2, q3, q4, q5, q6,\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:23: Little bit endian vector: MSB < LSB of bit range: 0:7\n output reg [0:7] r2\n            ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:28: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 3 bits.\n                                                                                        : ... In instance partsel_test002\nassign y1 = a[4 +: 3], y2 = a[4 +: 3] + b[4 +: 3], y3 = b[4 +: 3];\n          ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:28: Operator ADD expects 8 bits on the LHS, but LHS\'s SEL generates 3 bits.\n                                                                                        : ... In instance partsel_test002\nassign y1 = a[4 +: 3], y2 = a[4 +: 3] + b[4 +: 3], y3 = b[4 +: 3];\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:28: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 3 bits.\n                                                                                        : ... In instance partsel_test002\nassign y1 = a[4 +: 3], y2 = a[4 +: 3] + b[4 +: 3], y3 = b[4 +: 3];\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:28: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 3 bits.\n                                                                                        : ... In instance partsel_test002\nassign y1 = a[4 +: 3], y2 = a[4 +: 3] + b[4 +: 3], y3 = b[4 +: 3];\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:29: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 3 bits.\n                                                                                        : ... In instance partsel_test002\nassign y4 = a[4 +: 3], y5 = a[4 +: 3] + b[4 +: 3], y6 = b[4 +: 3];\n          ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:29: Operator ADD expects 8 bits on the LHS, but LHS\'s SEL generates 3 bits.\n                                                                                        : ... In instance partsel_test002\nassign y4 = a[4 +: 3], y5 = a[4 +: 3] + b[4 +: 3], y6 = b[4 +: 3];\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:29: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 3 bits.\n                                                                                        : ... In instance partsel_test002\nassign y4 = a[4 +: 3], y5 = a[4 +: 3] + b[4 +: 3], y6 = b[4 +: 3];\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:29: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 3 bits.\n                                                                                        : ... In instance partsel_test002\nassign y4 = a[4 +: 3], y5 = a[4 +: 3] + b[4 +: 3], y6 = b[4 +: 3];\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:30: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 3 bits.\n                                                                                        : ... In instance partsel_test002\nassign z1 = a[4 -: 3], z2 = a[4 -: 3] + b[4 -: 3], z3 = b[4 -: 3];\n          ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:30: Operator ADD expects 8 bits on the LHS, but LHS\'s SEL generates 3 bits.\n                                                                                        : ... In instance partsel_test002\nassign z1 = a[4 -: 3], z2 = a[4 -: 3] + b[4 -: 3], z3 = b[4 -: 3];\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:30: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 3 bits.\n                                                                                        : ... In instance partsel_test002\nassign z1 = a[4 -: 3], z2 = a[4 -: 3] + b[4 -: 3], z3 = b[4 -: 3];\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:30: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 3 bits.\n                                                                                        : ... In instance partsel_test002\nassign z1 = a[4 -: 3], z2 = a[4 -: 3] + b[4 -: 3], z3 = b[4 -: 3];\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:31: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 3 bits.\n                                                                                        : ... In instance partsel_test002\nassign z4 = a[4 -: 3], z5 = a[4 -: 3] + b[4 -: 3], z6 = b[4 -: 3];\n          ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:31: Operator ADD expects 8 bits on the LHS, but LHS\'s SEL generates 3 bits.\n                                                                                        : ... In instance partsel_test002\nassign z4 = a[4 -: 3], z5 = a[4 -: 3] + b[4 -: 3], z6 = b[4 -: 3];\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:31: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 3 bits.\n                                                                                        : ... In instance partsel_test002\nassign z4 = a[4 -: 3], z5 = a[4 -: 3] + b[4 -: 3], z6 = b[4 -: 3];\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:31: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 3 bits.\n                                                                                        : ... In instance partsel_test002\nassign z4 = a[4 -: 3], z5 = a[4 -: 3] + b[4 -: 3], z6 = b[4 -: 3];\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:32: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                        : ... In instance partsel_test002\nassign w1 = a[6:3], w2 = a[6:3] + b[3:6], w3 = b[3:6];\n          ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:32: Operator ADD expects 8 bits on the LHS, but LHS\'s SEL generates 4 bits.\n                                                                                        : ... In instance partsel_test002\nassign w1 = a[6:3], w2 = a[6:3] + b[3:6], w3 = b[3:6];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:32: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                                        : ... In instance partsel_test002\nassign w1 = a[6:3], w2 = a[6:3] + b[3:6], w3 = b[3:6];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:32: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                        : ... In instance partsel_test002\nassign w1 = a[6:3], w2 = a[6:3] + b[3:6], w3 = b[3:6];\n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:33: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                        : ... In instance partsel_test002\nassign w4 = a[6:3], w5 = a[6:3] + b[3:6], w6 = b[3:6];\n          ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:33: Operator ADD expects 8 bits on the LHS, but LHS\'s SEL generates 4 bits.\n                                                                                        : ... In instance partsel_test002\nassign w4 = a[6:3], w5 = a[6:3] + b[3:6], w6 = b[3:6];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:33: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                                        : ... In instance partsel_test002\nassign w4 = a[6:3], w5 = a[6:3] + b[3:6], w6 = b[3:6];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:33: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 4 bits.\n                                                                                        : ... In instance partsel_test002\nassign w4 = a[6:3], w5 = a[6:3] + b[3:6], w6 = b[3:6];\n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:34: Bit extraction of var[7:0] requires 3 bit index, not 2 bits.\n                                                                                        : ... In instance partsel_test002\nassign p1 = a[s], p2 = b[s], p3 = a[s+2 +: 2], p4 = b[s+2 +: 2], p5 = a[s+2 -: 2], p6 = b[s+2 -: 2];\n             ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:34: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n                                                                                        : ... In instance partsel_test002\nassign p1 = a[s], p2 = b[s], p3 = a[s+2 +: 2], p4 = b[s+2 +: 2], p5 = a[s+2 -: 2], p6 = b[s+2 -: 2];\n          ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:34: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n                                                                                        : ... In instance partsel_test002\nassign p1 = a[s], p2 = b[s], p3 = a[s+2 +: 2], p4 = b[s+2 +: 2], p5 = a[s+2 -: 2], p6 = b[s+2 -: 2];\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:34: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                        : ... In instance partsel_test002\nassign p1 = a[s], p2 = b[s], p3 = a[s+2 +: 2], p4 = b[s+2 +: 2], p5 = a[s+2 -: 2], p6 = b[s+2 -: 2];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:34: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                        : ... In instance partsel_test002\nassign p1 = a[s], p2 = b[s], p3 = a[s+2 +: 2], p4 = b[s+2 +: 2], p5 = a[s+2 -: 2], p6 = b[s+2 -: 2];\n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:34: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                        : ... In instance partsel_test002\nassign p1 = a[s], p2 = b[s], p3 = a[s+2 +: 2], p4 = b[s+2 +: 2], p5 = a[s+2 -: 2], p6 = b[s+2 -: 2];\n                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:34: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                        : ... In instance partsel_test002\nassign p1 = a[s], p2 = b[s], p3 = a[s+2 +: 2], p4 = b[s+2 +: 2], p5 = a[s+2 -: 2], p6 = b[s+2 -: 2];\n                                                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:35: Bit extraction of var[7:0] requires 3 bit index, not 2 bits.\n                                                                                        : ... In instance partsel_test002\nassign q1 = a[s], q2 = b[s], q3 = a[s+2 +: 2], q4 = b[s+2 +: 2], q5 = a[s+2 -: 2], q6 = b[s+2 -: 2];\n             ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:35: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n                                                                                        : ... In instance partsel_test002\nassign q1 = a[s], q2 = b[s], q3 = a[s+2 +: 2], q4 = b[s+2 +: 2], q5 = a[s+2 -: 2], q6 = b[s+2 -: 2];\n          ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:35: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n                                                                                        : ... In instance partsel_test002\nassign q1 = a[s], q2 = b[s], q3 = a[s+2 +: 2], q4 = b[s+2 +: 2], q5 = a[s+2 -: 2], q6 = b[s+2 -: 2];\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:35: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                        : ... In instance partsel_test002\nassign q1 = a[s], q2 = b[s], q3 = a[s+2 +: 2], q4 = b[s+2 +: 2], q5 = a[s+2 -: 2], q6 = b[s+2 -: 2];\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:35: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                        : ... In instance partsel_test002\nassign q1 = a[s], q2 = b[s], q3 = a[s+2 +: 2], q4 = b[s+2 +: 2], q5 = a[s+2 -: 2], q6 = b[s+2 -: 2];\n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:35: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                        : ... In instance partsel_test002\nassign q1 = a[s], q2 = b[s], q3 = a[s+2 +: 2], q4 = b[s+2 +: 2], q5 = a[s+2 -: 2], q6 = b[s+2 -: 2];\n                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:35: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n                                                                                        : ... In instance partsel_test002\nassign q1 = a[s], q2 = b[s], q3 = a[s+2 +: 2], q4 = b[s+2 +: 2], q5 = a[s+2 -: 2], q6 = b[s+2 -: 2];\n                                                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:43: Operator XOR expects 8 bits on the LHS, but LHS\'s SEL generates 4 bits.\n                                                                                        : ... In instance partsel_test002\n    r1[3:0] <= r2[0:3] ^ x1;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:43: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s XOR generates 8 bits.\n                                                                                        : ... In instance partsel_test002\n    r1[3:0] <= r2[0:3] ^ x1;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:44: Operator XOR expects 8 bits on the LHS, but LHS\'s SEL generates 4 bits.\n                                                                                        : ... In instance partsel_test002\n    r2[4:7] <= r1[7:4] ^ x4;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:44: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s XOR generates 8 bits.\n                                                                                        : ... In instance partsel_test002\n    r2[4:7] <= r1[7:4] ^ x4;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:47: Operator ADD expects 8 bits on the LHS, but LHS\'s SEL generates 3 bits.\n                                                                                        : ... In instance partsel_test002\n    r1[2 +: 3] <= r2[5 -: 3] + x1;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:47: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s ADD generates 8 bits.\n                                                                                        : ... In instance partsel_test002\n    r1[2 +: 3] <= r2[5 -: 3] + x1;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:48: Operator ADD expects 8 bits on the LHS, but LHS\'s SEL generates 3 bits.\n                                                                                        : ... In instance partsel_test002\n    r2[3 +: 3] <= r1[6 -: 3] + x4;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:48: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s ADD generates 8 bits.\n                                                                                        : ... In instance partsel_test002\n    r2[3 +: 3] <= r1[6 -: 3] + x4;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:51: Operator SUB expects 8 bits on the LHS, but LHS\'s SEL generates 3 bits.\n                                                                                        : ... In instance partsel_test002\n    r1[6 -: 3] <= r2[3 +: 3] - x1;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:51: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                                        : ... In instance partsel_test002\n    r1[6 -: 3] <= r2[3 +: 3] - x1;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:52: Operator SUB expects 8 bits on the LHS, but LHS\'s SEL generates 3 bits.\n                                                                                        : ... In instance partsel_test002\n    r2[7 -: 3] <= r1[4 +: 3] - x4;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:52: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s SUB generates 8 bits.\n                                                                                        : ... In instance partsel_test002\n    r2[7 -: 3] <= r1[4 +: 3] - x4;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:2: Operator SHIFTL expects 6 bits on the LHS, but LHS\'s VARREF \'idx\' generates 3 bits.\n                                                                                       : ... In instance partsel_test001\nwire [5:0] offset = idx << 2;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/partsel.v:3: Bit extraction of var[31:0] requires 5 bit index, not 6 bits.\n                                                                                       : ... In instance partsel_test001\nassign slice_up = data[offset +: 4];\n                      ^\n%Error: Exiting due to 62 warning(s)\n'
module partsel_test001(input [2:0] idx, input [31:0] data, output [3:0] slice_up, slice_down);
wire [5:0] offset = idx << 2;
assign slice_up = data[offset +: 4];
assign slice_down = data[offset + 3 -: 4];
endmodule
module partsel_test001(input [2:0] idx, input [31:0] data, output [3:0] slice_up, slice_down);

wire [5:0] offset = idx << 2;
assign slice_up = data[offset +: 4];
assign slice_down = data[offset + 3 -: 4];
endmodule