data/full_repos/permissive/451853158/MIPS_Pipeline_Processor/mainDecoder.v
data/verilator_xmls/d1894f90-d177-4074-b584-86aec786672d.xml
module mainDecoder (
  input      [5:0] OPCode,
  output reg       MemtoReg, MemWrite, Branch, ALUSrc, RegDst, RegWrite,
  output reg [1:0] ALUOp
);

always @(*)
  case (OPCode)
    6'b000000:
      {RegWrite, RegDst, ALUSrc, Branch, MemWrite, MemtoReg, ALUOp} = 8'b1_1_0_0_0_0_10;
	 
	  6'b100011:
	    {RegWrite, RegDst, ALUSrc, Branch, MemWrite, MemtoReg, ALUOp} = 8'b1_0_1_0_0_1_00;
	 
	  6'b101011:
	    {RegWrite, RegDst, ALUSrc, Branch, MemWrite, MemtoReg, ALUOp} = 8'b0_x_1_0_1_x_00;
	 
	  6'b000100:
	    {RegWrite, RegDst, ALUSrc, Branch, MemWrite, MemtoReg, ALUOp} = 8'b0_x_0_1_0_x_01;
	 
	  6'b001000:
	    {RegWrite, RegDst, ALUSrc, Branch, MemWrite, MemtoReg, ALUOp} = 8'b1_0_1_0_0_0_00;
	 
	  6'b000010:
	    {RegWrite, RegDst, ALUSrc, Branch, MemWrite, MemtoReg, ALUOp} = 8'b0_x_x_x_0_x_xx;
	 
	 default: 
	   {RegWrite, RegDst, ALUSrc, Branch, MemWrite, MemtoReg, ALUOp} = 8'bx_x_x_x_x_x_xx;
  endcase

endmodule
module mainDecoder (
  input      [5:0] OPCode,
  output reg       MemtoReg, MemWrite, Branch, ALUSrc, RegDst, RegWrite,
  output reg [1:0] ALUOp
);


always @(*)
  case (OPCode)
    6'b000000:
      {RegWrite, RegDst, ALUSrc, Branch, MemWrite, MemtoReg, ALUOp} = 8'b1_1_0_0_0_0_10;
	 
	  6'b100011:
	    {RegWrite, RegDst, ALUSrc, Branch, MemWrite, MemtoReg, ALUOp} = 8'b1_0_1_0_0_1_00;
	 
	  6'b101011:
	    {RegWrite, RegDst, ALUSrc, Branch, MemWrite, MemtoReg, ALUOp} = 8'b0_x_1_0_1_x_00;
	 
	  6'b000100:
	    {RegWrite, RegDst, ALUSrc, Branch, MemWrite, MemtoReg, ALUOp} = 8'b0_x_0_1_0_x_01;
	 
	  6'b001000:
	    {RegWrite, RegDst, ALUSrc, Branch, MemWrite, MemtoReg, ALUOp} = 8'b1_0_1_0_0_0_00;
	 
	  6'b000010:
	    {RegWrite, RegDst, ALUSrc, Branch, MemWrite, MemtoReg, ALUOp} = 8'b0_x_x_x_0_x_xx;
	 
	 default: 
	   {RegWrite, RegDst, ALUSrc, Branch, MemWrite, MemtoReg, ALUOp} = 8'bx_x_x_x_x_x_xx;
  endcase

endmodule