data/full_repos/permissive/477054115/iitb-risc/dataMem.v
1: b'%Warning-WIDTH: data/full_repos/permissive/477054115/iitb-risc/dataMem.v:26: Bit extraction of array[4096:0] requires 13 bit index, not 12 bits.\n                                                                           : ... In instance data_memory\n            ram[ram_addr] <= mem_write_data;\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/477054115/iitb-risc/dataMem.v:36: Bit extraction of array[4096:0] requires 13 bit index, not 12 bits.\n                                                                           : ... In instance data_memory\n    assign mem_read_data = (mem_read == 1\'b1) ? ram[ram_addr]: 16\'d0;\n                                                   ^\n%Error: Exiting due to 2 warning(s)\n'
module data_memory
 (
    input           clk,
    input           rst,
    input   [15:0]  mem_access_addr,
    input   [15:0]  mem_write_data,
    input           mem_write_en,

    output  [15:0]  mem_read_data
 );

    integer i;
    reg     [15:0] ram [4096:0];
    wire    [11:0] ram_addr = mem_access_addr [11:0];
    reg mem_read;
    initial begin
        for(i=0; i<4096; i=i+1) begin
            ram[i] <= 16'd0;
        end
        mem_read = 1'b1;
    end

    always @(posedge clk) begin
        if (mem_write_en && ~rst) begin
            ram[ram_addr] <= mem_write_data;
        end

        if (rst) begin
            for(i=0; i<4096; i=i+1) begin
                ram[i] <= 16'd0;
            end
        end
    end
      
    assign mem_read_data = (mem_read == 1'b1) ? ram[ram_addr]: 16'd0;

endmodule
module data_memory
 (
    input           clk,
    input           rst,
    input   [15:0]  mem_access_addr,
    input   [15:0]  mem_write_data,
    input           mem_write_en,

    output  [15:0]  mem_read_data
 );


    integer i;
    reg     [15:0] ram [4096:0];
    wire    [11:0] ram_addr = mem_access_addr [11:0];
    reg mem_read;
    initial begin
        for(i=0; i<4096; i=i+1) begin
            ram[i] <= 16'd0;
        end
        mem_read = 1'b1;
    end

    always @(posedge clk) begin
        if (mem_write_en && ~rst) begin
            ram[ram_addr] <= mem_write_data;
        end

        if (rst) begin
            for(i=0; i<4096; i=i+1) begin
                ram[i] <= 16'd0;
            end
        end
    end
      
    assign mem_read_data = (mem_read == 1'b1) ? ram[ram_addr]: 16'd0;

endmodule