data/full_repos/permissive/496903659/150 exams#2013_q2afsm.v
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/496903659/150\n        ... Looked in:\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/150\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/150.v\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/150.sv\n             data/full_repos/permissive/496903659/150\n             data/full_repos/permissive/496903659/150.v\n             data/full_repos/permissive/496903659/150.sv\n             obj_dir/data/full_repos/permissive/496903659/150\n             obj_dir/data/full_repos/permissive/496903659/150.v\n             obj_dir/data/full_repos/permissive/496903659/150.sv\n%Error: Cannot find file containing module: exams#2013_q2afsm.v\n%Error: Exiting due to 2 error(s)\n'
module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output [3:1] g
); 
    reg [3:0] state, next_state;
    always @(*) begin
        case (state)
            'b0001: next_state <= (r[1] ? 'b0010: (r[2] ? 'b0100: (r[3] ? 'b1000: 'b0001)));
            'b0010: next_state <= r[1] ? 'b0010: 'b0001;
            'b0100: next_state <= r[2] ? 'b0100: 'b0001;
            'b1000: next_state <= r[3] ? 'b1000: 'b0001;
            default: next_state <= state;
        endcase
    end
    
    always @(posedge clk) begin
        if (~resetn)
            state <= 'b0001;
        else
            state <= next_state;
    end

    assign g = state[3:1];
endmodule
module top_module (
    input clk,
    input resetn,
    input [3:1] r,
    output [3:1] g
);
 
    reg [3:0] state, next_state;
    always @(*) begin
        case (state)
            'b0001: next_state <= (r[1] ? 'b0010: (r[2] ? 'b0100: (r[3] ? 'b1000: 'b0001)));
            'b0010: next_state <= r[1] ? 'b0010: 'b0001;
            'b0100: next_state <= r[2] ? 'b0100: 'b0001;
            'b1000: next_state <= r[3] ? 'b1000: 'b0001;
            default: next_state <= state;
        endcase
    end
    
    always @(posedge clk) begin
        if (~resetn)
            state <= 'b0001;
        else
            state <= next_state;
    end

    assign g = state[3:1];
endmodule