data/full_repos/permissive/42434302/ivltests/undef_lval_select4a.v
1: b"%Error: data/full_repos/permissive/42434302/ivltests/undef_lval_select4a.v:10: Unsupported: Verilog 1995 force\n    force vec[1'bx] = 1'b1;\n    ^~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/undef_lval_select4a.v:15: Unsupported: Verilog 1995 release\n    release vec[1'bx];\n    ^~~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/undef_lval_select4a.v:17: Unsupported: Verilog 1995 force\n    force vec[1'bx:0] = 1'b1;\n    ^~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/undef_lval_select4a.v:22: Unsupported: Verilog 1995 release\n    release vec[1'bx:0];\n    ^~~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/undef_lval_select4a.v:24: Unsupported: Verilog 1995 force\n    force vec[0:1'bx] = 1'b1;\n    ^~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/undef_lval_select4a.v:29: Unsupported: Verilog 1995 release\n    release vec[0:1'bx];\n    ^~~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/undef_lval_select4a.v:31: Unsupported: Verilog 1995 force\n    force vec[1'bx:1'bx] = 1'b1;\n    ^~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/undef_lval_select4a.v:36: Unsupported: Verilog 1995 release\n    release vec[1'bx:1'bx];\n    ^~~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/undef_lval_select4a.v:38: Unsupported: Verilog 1995 force\n    force vec[1'bx+:1] = 1'b1;\n    ^~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/undef_lval_select4a.v:43: Unsupported: Verilog 1995 release\n    release vec[1'bx+:1];\n    ^~~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/undef_lval_select4a.v:45: Unsupported: Verilog 1995 force\n    force vec[1'bx+:2] = 2'b01;\n    ^~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/undef_lval_select4a.v:50: Unsupported: Verilog 1995 release\n    release vec[1'bx+:2];\n    ^~~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/undef_lval_select4a.v:52: Unsupported: Verilog 1995 force\n    force vec[1'bx-:1] = 1'b1;\n    ^~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/undef_lval_select4a.v:57: Unsupported: Verilog 1995 release\n    release vec[1'bx-:1];\n    ^~~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/undef_lval_select4a.v:59: Unsupported: Verilog 1995 force\n    force vec[1'bx-:2] = 2'b01;\n    ^~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/undef_lval_select4a.v:64: Unsupported: Verilog 1995 release\n    release vec[1'bx-:2];\n    ^~~~~~~\n%Error: Exiting due to 16 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module top;
  reg pass;
  wire [2:-1] vec;

  assign vec = 4'bxxxx;

  initial begin
    pass = 1'b1;

    force vec[1'bx] = 1'b1;
    if (vec !== 4'bxxx) begin
      $display("Failed vec[1'bx], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end
    release vec[1'bx];

    force vec[1'bx:0] = 1'b1;
    if (vec !== 4'bxxxx) begin
      $display("Failed vec[1'bx:0], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end
    release vec[1'bx:0];

    force vec[0:1'bx] = 1'b1;
    if (vec !== 4'bxxxx) begin
      $display("Failed vec[0:1'bx], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end
    release vec[0:1'bx];

    force vec[1'bx:1'bx] = 1'b1;
    if (vec !== 4'bxxxx) begin
      $display("Failed vec[1'bx:1'bx], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end
    release vec[1'bx:1'bx];

    force vec[1'bx+:1] = 1'b1;
    if (vec !== 4'bxxxx) begin
      $display("Failed vec[1'bx+:1], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end
    release vec[1'bx+:1];

    force vec[1'bx+:2] = 2'b01;
    if (vec !== 4'bxxxx) begin
      $display("Failed vec[1'bx+:2], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end
    release vec[1'bx+:2];

    force vec[1'bx-:1] = 1'b1;
    if (vec !== 4'bxxxx) begin
      $display("Failed vec[1'bx-:1], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end
    release vec[1'bx-:1];

    force vec[1'bx-:2] = 2'b01;
    if (vec !== 4'bxxxx) begin
      $display("Failed vec[1'bx-:2], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end
    release vec[1'bx-:2];

    if (pass) $display("PASSED");
  end
endmodule
module top;

  reg pass;
  wire [2:-1] vec;

  assign vec = 4'bxxxx;

  initial begin
    pass = 1'b1;

    force vec[1'bx] = 1'b1;
    if (vec !== 4'bxxx) begin
      $display("Failed vec[1'bx], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end
    release vec[1'bx];

    force vec[1'bx:0] = 1'b1;
    if (vec !== 4'bxxxx) begin
      $display("Failed vec[1'bx:0], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end
    release vec[1'bx:0];

    force vec[0:1'bx] = 1'b1;
    if (vec !== 4'bxxxx) begin
      $display("Failed vec[0:1'bx], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end
    release vec[0:1'bx];

    force vec[1'bx:1'bx] = 1'b1;
    if (vec !== 4'bxxxx) begin
      $display("Failed vec[1'bx:1'bx], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end
    release vec[1'bx:1'bx];

    force vec[1'bx+:1] = 1'b1;
    if (vec !== 4'bxxxx) begin
      $display("Failed vec[1'bx+:1], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end
    release vec[1'bx+:1];

    force vec[1'bx+:2] = 2'b01;
    if (vec !== 4'bxxxx) begin
      $display("Failed vec[1'bx+:2], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end
    release vec[1'bx+:2];

    force vec[1'bx-:1] = 1'b1;
    if (vec !== 4'bxxxx) begin
      $display("Failed vec[1'bx-:1], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end
    release vec[1'bx-:1];

    force vec[1'bx-:2] = 2'b01;
    if (vec !== 4'bxxxx) begin
      $display("Failed vec[1'bx-:2], expected 4'bxxxx, got %b", vec);
      pass = 1'b0;
    end
    release vec[1'bx-:2];

    if (pass) $display("PASSED");
  end
endmodule