data/full_repos/permissive/443741085/src/rv_top.v
1: b"%Error: data/full_repos/permissive/443741085/src/rv_top.v:47: Cannot find file containing module: 'rv_dp'\n rv_dp\n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/443741085/src,data/full_repos/permissive/443741085/rv_dp\n             data/full_repos/permissive/443741085/src,data/full_repos/permissive/443741085/rv_dp.v\n             data/full_repos/permissive/443741085/src,data/full_repos/permissive/443741085/rv_dp.sv\n             rv_dp\n             rv_dp.v\n             rv_dp.sv\n             obj_dir/rv_dp\n             obj_dir/rv_dp.v\n             obj_dir/rv_dp.sv\n%Error: data/full_repos/permissive/443741085/src/rv_top.v:83: Cannot find file containing module: 'rv_ctl'\n rv_ctl ctl\n ^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module rv_top
    #(parameter
        DPWIDTH = 32,
        RFSIZE  = 32
    )
 (


     output wire [DPWIDTH-1:0] imem_addr,
     output wire [DPWIDTH-1:0] dmem_addr,
     output wire [DPWIDTH-1:0] dmem_dataout,
     output wire memrw,
     input wire [DPWIDTH-1:0] dmem_datain,
     input wire [DPWIDTH-1:0] imem_datain,


     input wire clk,
     input wire rst
 );




 wire [DPWIDTH-1:0] instr;
 wire zero;
 wire pcsourse;
 wire pcwrite;
 wire pccen;
 wire irwrite;
 wire [1:0] wbsel;
 wire regwen;
 wire [1:0] immsel;
 wire asel;
 wire bsel;
 wire [3:0] alusel;
 wire mdrwrite;
     


 rv_dp
    #(
        .DPWIDTH(DPWIDTH),
        .RFSIZE(RFSIZE)
    ) dp
 (


     .imem_addr(imem_addr),
     .dmem_addr(dmem_addr),
     .dmem_dataout(dmem_dataout),
     .dmem_datain(dmem_datain),
     .imem_datain(imem_datain),


     .instr(instr),
     .zero(zero),
     .pcsourse(pcsourse),
     .pcwrite(pcwrite),
     .pccen(pccen),
     .irwrite(irwrite),
     .wbsel(wbsel),
     .regwen(regwen),
     .immsel(immsel),
     .asel(asel),
     .bsel(bsel),
     .alusel(alusel),
     .mdrwrite(mdrwrite),
     

     .clk(clk),
     .rst(rst)
 );



 rv_ctl ctl
 (


     .memrw(memrw),


     .instr(instr),
     .zero(zero),
     .pcsourse(pcsourse),
     .pcwrite(pcwrite),
     .pccen(pccen),
     .irwrite(irwrite),
     .wbsel(wbsel),
     .regwen(regwen),
     .immsel(immsel),
     .asel(asel),
     .bsel(bsel),
     .alusel(alusel),
     .mdrwrite(mdrwrite),
     

     .clk(clk),
     .rst(rst)
 );
 
 endmodule
module rv_top
    #(parameter
        DPWIDTH = 32,
        RFSIZE  = 32
    )
 (


     output wire [DPWIDTH-1:0] imem_addr,
     output wire [DPWIDTH-1:0] dmem_addr,
     output wire [DPWIDTH-1:0] dmem_dataout,
     output wire memrw,
     input wire [DPWIDTH-1:0] dmem_datain,
     input wire [DPWIDTH-1:0] imem_datain,


     input wire clk,
     input wire rst
 );





 wire [DPWIDTH-1:0] instr;
 wire zero;
 wire pcsourse;
 wire pcwrite;
 wire pccen;
 wire irwrite;
 wire [1:0] wbsel;
 wire regwen;
 wire [1:0] immsel;
 wire asel;
 wire bsel;
 wire [3:0] alusel;
 wire mdrwrite;
     


 rv_dp
    #(
        .DPWIDTH(DPWIDTH),
        .RFSIZE(RFSIZE)
    ) dp
 (


     .imem_addr(imem_addr),
     .dmem_addr(dmem_addr),
     .dmem_dataout(dmem_dataout),
     .dmem_datain(dmem_datain),
     .imem_datain(imem_datain),


     .instr(instr),
     .zero(zero),
     .pcsourse(pcsourse),
     .pcwrite(pcwrite),
     .pccen(pccen),
     .irwrite(irwrite),
     .wbsel(wbsel),
     .regwen(regwen),
     .immsel(immsel),
     .asel(asel),
     .bsel(bsel),
     .alusel(alusel),
     .mdrwrite(mdrwrite),
     

     .clk(clk),
     .rst(rst)
 );



 rv_ctl ctl
 (


     .memrw(memrw),


     .instr(instr),
     .zero(zero),
     .pcsourse(pcsourse),
     .pcwrite(pcwrite),
     .pccen(pccen),
     .irwrite(irwrite),
     .wbsel(wbsel),
     .regwen(regwen),
     .immsel(immsel),
     .asel(asel),
     .bsel(bsel),
     .alusel(alusel),
     .mdrwrite(mdrwrite),
     

     .clk(clk),
     .rst(rst)
 );
 
 endmodule