data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/barrier_gluelogic_v1_0_0/hdl/barrier_gluelogic.v
data/verilator_xmls/3c154d1d-0b7f-47f2-8e57-701a8c3e8680.xml
module barrier_gluelogic
(
   input wire                                  in_pin4,
   input wire                                  in_pin3,
   input wire                                  in_pin2,
   input wire                                  in_pin1,
   input wire                                  in_pin0,

   output wire  [4:0]                          out_bus
);

assign out_bus = {in_pin4, in_pin3, in_pin2, in_pin1, in_pin0};

endmodule
module barrier_gluelogic
(
   input wire                                  in_pin4,
   input wire                                  in_pin3,
   input wire                                  in_pin2,
   input wire                                  in_pin1,
   input wire                                  in_pin0,

   output wire  [4:0]                          out_bus
);


assign out_bus = {in_pin4, in_pin3, in_pin2, in_pin1, in_pin0};

endmodule