data/full_repos/permissive/418331750/priRV32_SoC.v
1: b'%Error: data/full_repos/permissive/418331750/priRV32_SoC.v:1: Cannot find include file: ./core/priRV32_top.v\n`include "./core/priRV32_top.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418331750,data/full_repos/permissive/418331750/./core/priRV32_top.v\n             data/full_repos/permissive/418331750,data/full_repos/permissive/418331750/./core/priRV32_top.v.v\n             data/full_repos/permissive/418331750,data/full_repos/permissive/418331750/./core/priRV32_top.v.sv\n             ./core/priRV32_top.v\n             ./core/priRV32_top.v.v\n             ./core/priRV32_top.v.sv\n             obj_dir/./core/priRV32_top.v\n             obj_dir/./core/priRV32_top.v.v\n             obj_dir/./core/priRV32_top.v.sv\n%Error: data/full_repos/permissive/418331750/priRV32_SoC.v:2: Cannot find include file: ./periph/uart/uart_top.v\n`include "./periph/uart/uart_top.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418331750/priRV32_SoC.v:3: Cannot find include file: ./fpga/itcm_ram.v\n`include "./fpga/itcm_ram.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418331750/priRV32_SoC.v:4: Cannot find include file: ./periph/flash/spi_flash\n`include "./periph/flash/spi_flash" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module priRV32_SoC (
    input clk_in,
    input rst_in,
    input rx_pin,
    output tx_pin,
    output spi_cs_pin,
    output spi_clk_pin,
    output spi_mosi_pin,
    input spi_miso_pin
);
    wire rst_n;
    wire [31:0]readwrite_address, mem_read_data, itcm_address, itcm_data;

    PowerOn_RST po_rst(
		.clk_in(clk_in),
		.rst_in(rst_in),
		.rst_n(rst_n)
	);

    itcm_ram itcm_ram1(
	    .address(itcm_address),
		.clock(clk_in),
		.data(itcm_data),
		.wren(),
		.q(mem_read_data)
    );
	
    priRV32 rv32_core(
        .clk_in(clk_in),
		.rst_n(rst_n),
        .itcm_address(itcm_address),
        .itcm_data(itcm_data),
        .mem_readwrite_address(readwrite_address),
        .mem_read_data(mem_read_data),
        .mem_write_data()
    );

    uart_top #(
        .CLK_FREQUENCY(50_000_000),
		.BAUD_RATE(115200)
    )uart1(
        .clk_in(clk_in),
		.rst_n(rst_n),
        .tx_pin(tx_pin),
		.rx_pin(rx_pin),
        .write_valid(1'b1),
        .read_valid(1'b1),
        .write_data(),
        .read_data(),
        .write_address(readwrite_address),
        .read_address(readwrite_address)
    );

    spi_flash_xip flash_xip(
        .clk(clk_in),
		.rst_n(rst_n),
		.ncs(spi_cs_pin),
		.dclk(spi_clk_pin),
		.mosi(spi_mosi_pin),
		.miso(spi_miso_pin)
    );

endmodule
module priRV32_SoC (
    input clk_in,
    input rst_in,
    input rx_pin,
    output tx_pin,
    output spi_cs_pin,
    output spi_clk_pin,
    output spi_mosi_pin,
    input spi_miso_pin
);

    wire rst_n;
    wire [31:0]readwrite_address, mem_read_data, itcm_address, itcm_data;

    PowerOn_RST po_rst(
		.clk_in(clk_in),
		.rst_in(rst_in),
		.rst_n(rst_n)
	);

    itcm_ram itcm_ram1(
	    .address(itcm_address),
		.clock(clk_in),
		.data(itcm_data),
		.wren(),
		.q(mem_read_data)
    );
	
    priRV32 rv32_core(
        .clk_in(clk_in),
		.rst_n(rst_n),
        .itcm_address(itcm_address),
        .itcm_data(itcm_data),
        .mem_readwrite_address(readwrite_address),
        .mem_read_data(mem_read_data),
        .mem_write_data()
    );

    uart_top #(
        .CLK_FREQUENCY(50_000_000),
		.BAUD_RATE(115200)
    )uart1(
        .clk_in(clk_in),
		.rst_n(rst_n),
        .tx_pin(tx_pin),
		.rx_pin(rx_pin),
        .write_valid(1'b1),
        .read_valid(1'b1),
        .write_data(),
        .read_data(),
        .write_address(readwrite_address),
        .read_address(readwrite_address)
    );

    spi_flash_xip flash_xip(
        .clk(clk_in),
		.rst_n(rst_n),
		.ncs(spi_cs_pin),
		.dclk(spi_clk_pin),
		.mosi(spi_mosi_pin),
		.miso(spi_miso_pin)
    );

endmodule