data/full_repos/permissive/493441306/Verilog Language/vectors/02_vector2.v
1: b'%Error: Cannot find file containing module: Language/vectors,data/full_repos/permissive/493441306\n        ... Looked in:\n             data/full_repos/permissive/493441306/Verilog/Language/vectors,data/full_repos/permissive/493441306\n             data/full_repos/permissive/493441306/Verilog/Language/vectors,data/full_repos/permissive/493441306.v\n             data/full_repos/permissive/493441306/Verilog/Language/vectors,data/full_repos/permissive/493441306.sv\n             Language/vectors,data/full_repos/permissive/493441306\n             Language/vectors,data/full_repos/permissive/493441306.v\n             Language/vectors,data/full_repos/permissive/493441306.sv\n             obj_dir/Language/vectors,data/full_repos/permissive/493441306\n             obj_dir/Language/vectors,data/full_repos/permissive/493441306.v\n             obj_dir/Language/vectors,data/full_repos/permissive/493441306.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/493441306/Verilog\n%Error: Cannot find file containing module: Language/vectors/02_vector2.v\n%Error: Exiting due to 3 error(s)\n'
module top_module( 
    input [31:0] in,
    output [31:0] out );

    assign out[31:24] = in[7:0],
           out[23:16] = in[15:8],
            out[15:8] = in[23:16],
             out[7:0] = in[31:24];

endmodule
module top_module( 
    input [31:0] in,
    output [31:0] out );


    assign out[31:24] = in[7:0],
           out[23:16] = in[15:8],
            out[15:8] = in[23:16],
             out[7:0] = in[31:24];

endmodule