data/full_repos/permissive/42434302/ivltests/pr1077.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1077.v:18: Unsupported: Ignoring delay on this delayed statement.\nalways #2.5 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1077.v:22: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr1077.v:29: Logical Operator LOGOR expects 1 bit on the RHS, but RHS\'s NOT generates 3 bits.\n                                                                        : ... In instance bool\n y <= count[10] || ~count[5:3];\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr1077.v:32: Logical Operator LOGOR expects 1 bit on the RHS, but RHS\'s NOT generates 3 bits.\n                                                                        : ... In instance bool\n if(count[10] || ~(count[5:3]))\n              ^~\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bool;

reg clk,y;
reg [31:0] count;

initial clk=0;
always #2.5 clk = ~clk;

initial begin
	count = 'h8;
	#20
	$finish;
end

always @(posedge clk)
begin

	y <= count[10] || ~count[5:3];


	if(count[10] || ~(count[5:3]))
		$display("one");
	else
		$display("zero");
	$display("y = %b",y);

end

endmodule
module bool;


reg clk,y;
reg [31:0] count;

initial clk=0;
always #2.5 clk = ~clk;

initial begin
	count = 'h8;
	#20
	$finish;
end

always @(posedge clk)
begin

	y <= count[10] || ~count[5:3];


	if(count[10] || ~(count[5:3]))
		$display("one");
	else
		$display("zero");
	$display("y = %b",y);

end

endmodule