data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Basic_Gates/54_Mt2015_q4b.v
data/verilator_xmls/a8cbd78f-19f9-49d9-a66a-1e4a6f9175ef.xml
module top_module ( input x, input y, output z );
    assign z = (~x & ~y)|
               (x & y);
endmodule
module top_module ( input x, input y, output z );

    assign z = (~x & ~y)|
               (x & y);
endmodule