data/full_repos/permissive/405799749/amg_new/mult/Unsigned/9/5/Simple_PPG/Wallace_tree/Han-Carlson_adder/module.v
data/verilator_xmls/72e5ceb7-1230-456d-98d4-39e8ca0391a6.xml
module MultUB_STD_WAL_HC000 (P, IN1, IN2);
  output [13:0] P;
  input [8:0] IN1;
  input [4:0] IN2;
  wire [8:0] PP0;
  wire [9:1] PP1;
  wire [10:2] PP2;
  wire [11:3] PP3;
  wire [12:4] PP4;
  wire [12:4] S1;
  wire [12:0] S2;
  UBPPG_8_0_4_0 U0 (PP0, PP1, PP2, PP3, PP4, IN1, IN2);
  WLCTR_8_0_9_1_10_000 U1 (S1, S2, PP0, PP1, PP2, PP3, PP4);
  UBHCA_12_4_12_0 U2 (P, S1, S2);
endmodule
module MultUB_STD_WAL_HC000 (P, IN1, IN2);

  output [13:0] P;
  input [8:0] IN1;
  input [4:0] IN2;
  wire [8:0] PP0;
  wire [9:1] PP1;
  wire [10:2] PP2;
  wire [11:3] PP3;
  wire [12:4] PP4;
  wire [12:4] S1;
  wire [12:0] S2;
  UBPPG_8_0_4_0 U0 (PP0, PP1, PP2, PP3, PP4, IN1, IN2);
  WLCTR_8_0_9_1_10_000 U1 (S1, S2, PP0, PP1, PP2, PP3, PP4);
  UBHCA_12_4_12_0 U2 (P, S1, S2);
endmodule