data/full_repos/permissive/434840709/作业/进位选择加法器/cg.v
1: b"%Error: data/full_repos/permissive/434840709/\xe4\xbd\x9c\xe4\xb8\x9a/\xe8\xbf\x9b\xe4\xbd\x8d\xe9\x80\x89\xe6\x8b\xa9\xe5\x8a\xa0\xe6\xb3\x95\xe5\x99\xa8/cg.v:13: Cannot find file containing module: 'add16'\nadd16 A16_1(a[15:0],b[15:0],0,sum[15:0],out1);\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/434840709/\xe4\xbd\x9c\xe4\xb8\x9a/\xe8\xbf\x9b\xe4\xbd\x8d\xe9\x80\x89\xe6\x8b\xa9\xe5\x8a\xa0\xe6\xb3\x95\xe5\x99\xa8,data/full_repos/permissive/434840709/add16\n             data/full_repos/permissive/434840709/\xe4\xbd\x9c\xe4\xb8\x9a/\xe8\xbf\x9b\xe4\xbd\x8d\xe9\x80\x89\xe6\x8b\xa9\xe5\x8a\xa0\xe6\xb3\x95\xe5\x99\xa8,data/full_repos/permissive/434840709/add16.v\n             data/full_repos/permissive/434840709/\xe4\xbd\x9c\xe4\xb8\x9a/\xe8\xbf\x9b\xe4\xbd\x8d\xe9\x80\x89\xe6\x8b\xa9\xe5\x8a\xa0\xe6\xb3\x95\xe5\x99\xa8,data/full_repos/permissive/434840709/add16.sv\n             add16\n             add16.v\n             add16.sv\n             obj_dir/add16\n             obj_dir/add16.v\n             obj_dir/add16.sv\n%Error: data/full_repos/permissive/434840709/\xe4\xbd\x9c\xe4\xb8\x9a/\xe8\xbf\x9b\xe4\xbd\x8d\xe9\x80\x89\xe6\x8b\xa9\xe5\x8a\xa0\xe6\xb3\x95\xe5\x99\xa8/cg.v:14: Cannot find file containing module: 'add16'\nadd16 A16_2(a[31:16],b[31:16],0,tout1[15:0],out2);\n^~~~~\n%Error: data/full_repos/permissive/434840709/\xe4\xbd\x9c\xe4\xb8\x9a/\xe8\xbf\x9b\xe4\xbd\x8d\xe9\x80\x89\xe6\x8b\xa9\xe5\x8a\xa0\xe6\xb3\x95\xe5\x99\xa8/cg.v:15: Cannot find file containing module: 'add16'\nadd16 A16_3(a[31:16],b[31:16],1,tout2[15:0],out3);\n^~~~~\n%Error: Exiting due to 3 error(s)\n"
module top_module(

                input [31:0] a,

                input [31:0] b,

                output [31:0] sum

        );

wire out1,out2,out3;
wire[15:0] tout1,tout2;
add16 A16_1(a[15:0],b[15:0],0,sum[15:0],out1);
add16 A16_2(a[31:16],b[31:16],0,tout1[15:0],out2);
add16 A16_3(a[31:16],b[31:16],1,tout2[15:0],out3);
assign sum[31:16] = (out1<1)?(tout1):(tout2);


endmodule
module top_module(

                input [31:0] a,

                input [31:0] b,

                output [31:0] sum

        );


wire out1,out2,out3;
wire[15:0] tout1,tout2;
add16 A16_1(a[15:0],b[15:0],0,sum[15:0],out1);
add16 A16_2(a[31:16],b[31:16],0,tout1[15:0],out2);
add16 A16_3(a[31:16],b[31:16],1,tout2[15:0],out3);
assign sum[31:16] = (out1<1)?(tout1):(tout2);


endmodule