data/full_repos/permissive/507307707/generated/CellProcessing.v
data/verilator_xmls/ab97e684-dfea-49c9-88b0-d7fe90873c62.xml
module FU(
  input         clock,
  input         reset,
  input  [31:0] io_din_1,
  input  [31:0] io_din_2,
  input         io_din_v,
  input         io_dout_r,
  input  [1:0]  io_loop_source,
  input  [15:0] io_iterations_reset,
  input  [3:0]  io_op_config,
  output        io_din_r,
  output [31:0] io_dout,
  output        io_dout_v
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
`endif
  wire [31:0] ALU_io_din_1;
  wire [31:0] ALU_io_din_2;
  wire [3:0] ALU_io_op_config;
  wire [31:0] ALU_io_dout;
  reg [31:0] alu_din_1;
  reg [31:0] alu_din_2;
  reg [31:0] alu_dout;
  reg [31:0] dout_Reg;
  reg [15:0] count;
  reg  loaded;
  reg  valid;
  wire  _T = io_loop_source == 2'h0;
  wire  _T_1 = io_loop_source == 2'h1;
  wire  _T_2 = ~loaded;
  wire  _T_3 = io_loop_source == 2'h2;
  wire [31:0] _GEN_3 = _T_2 ? io_din_2 : dout_Reg;
  wire  _GEN_10 = io_dout_r ? 1'h0 : valid;
  wire  _T_13 = _T_1 | _T_3;
  wire  _T_14 = io_din_v & io_dout_r & _T_13;
  wire [15:0] _count_T_1 = count + 16'h1;
  wire  _T_19 = count == io_iterations_reset & _T_13;
  wire  _T_21 = _T_19 & io_dout_r;
  wire  _T_26 = _T_13 & io_din_v;
  wire  _T_28 = _T_26 & io_dout_r;
  wire  _GEN_16 = _T_21 | _GEN_10;
  ALU ALU (
    .io_din_1(ALU_io_din_1),
    .io_din_2(ALU_io_din_2),
    .io_op_config(ALU_io_op_config),
    .io_dout(ALU_io_dout)
  );
  assign io_din_r = io_dout_r;
  assign io_dout = _T ? alu_dout : dout_Reg;
  assign io_dout_v = _T ? io_din_v : valid;
  assign ALU_io_din_1 = alu_din_1;
  assign ALU_io_din_2 = alu_din_2;
  assign ALU_io_op_config = io_op_config;
  always @(posedge clock) begin
    if (reset) begin
      alu_din_1 <= 32'h0;
    end else if (io_loop_source == 2'h0) begin
      alu_din_1 <= io_din_1;
    end else if (io_loop_source == 2'h1) begin
      if (~loaded) begin
        alu_din_1 <= io_din_1;
      end else begin
        alu_din_1 <= dout_Reg;
      end
    end else if (io_loop_source == 2'h2) begin
      alu_din_1 <= io_din_1;
    end else begin
      alu_din_1 <= 32'h1f;
    end
    if (reset) begin
      alu_din_2 <= 32'h0;
    end else if (io_loop_source == 2'h0) begin
      alu_din_2 <= io_din_2;
    end else if (io_loop_source == 2'h1) begin
      alu_din_2 <= io_din_2;
    end else if (io_loop_source == 2'h2) begin
      alu_din_2 <= _GEN_3;
    end else begin
      alu_din_2 <= 32'h1f;
    end
    if (reset) begin
      alu_dout <= 32'h0;
    end else begin
      alu_dout <= ALU_io_dout;
    end
    if (reset) begin
      dout_Reg <= 32'h0;
    end else if (_T_21) begin
      dout_Reg <= alu_dout;
    end else if (_T_28) begin
      dout_Reg <= alu_dout;
    end else begin
      dout_Reg <= 32'h0;
    end
    if (reset) begin
      count <= 16'hffff;
    end else if (_T_21) begin
      count <= 16'h0;
    end else if (_T_14) begin
      count <= _count_T_1;
    end else begin
      count <= 16'h0;
    end
    if (reset) begin
      loaded <= 1'h0;
    end else if (_T_21) begin
      loaded <= 1'h0;
    end else begin
      loaded <= _T_14;
    end
    if (reset) begin
      valid <= 1'h0;
    end else begin
      valid <= _GEN_16;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  alu_din_1 = _RAND_0[31:0];
  _RAND_1 = {1{`RANDOM}};
  alu_din_2 = _RAND_1[31:0];
  _RAND_2 = {1{`RANDOM}};
  alu_dout = _RAND_2[31:0];
  _RAND_3 = {1{`RANDOM}};
  dout_Reg = _RAND_3[31:0];
  _RAND_4 = {1{`RANDOM}};
  count = _RAND_4[15:0];
  _RAND_5 = {1{`RANDOM}};
  loaded = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  valid = _RAND_6[0:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module FU(
  input         clock,
  input         reset,
  input  [31:0] io_din_1,
  input  [31:0] io_din_2,
  input         io_din_v,
  input         io_dout_r,
  input  [1:0]  io_loop_source,
  input  [15:0] io_iterations_reset,
  input  [3:0]  io_op_config,
  output        io_din_r,
  output [31:0] io_dout,
  output        io_dout_v
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
`endif
  wire [31:0] ALU_io_din_1;
  wire [31:0] ALU_io_din_2;
  wire [3:0] ALU_io_op_config;
  wire [31:0] ALU_io_dout;
  reg [31:0] alu_din_1;
  reg [31:0] alu_din_2;
  reg [31:0] alu_dout;
  reg [31:0] dout_Reg;
  reg [15:0] count;
  reg  loaded;
  reg  valid;
  wire  _T = io_loop_source == 2'h0;
  wire  _T_1 = io_loop_source == 2'h1;
  wire  _T_2 = ~loaded;
  wire  _T_3 = io_loop_source == 2'h2;
  wire [31:0] _GEN_3 = _T_2 ? io_din_2 : dout_Reg;
  wire  _GEN_10 = io_dout_r ? 1'h0 : valid;
  wire  _T_13 = _T_1 | _T_3;
  wire  _T_14 = io_din_v & io_dout_r & _T_13;
  wire [15:0] _count_T_1 = count + 16'h1;
  wire  _T_19 = count == io_iterations_reset & _T_13;
  wire  _T_21 = _T_19 & io_dout_r;
  wire  _T_26 = _T_13 & io_din_v;
  wire  _T_28 = _T_26 & io_dout_r;
  wire  _GEN_16 = _T_21 | _GEN_10;
  ALU ALU (
    .io_din_1(ALU_io_din_1),
    .io_din_2(ALU_io_din_2),
    .io_op_config(ALU_io_op_config),
    .io_dout(ALU_io_dout)
  );
  assign io_din_r = io_dout_r;
  assign io_dout = _T ? alu_dout : dout_Reg;
  assign io_dout_v = _T ? io_din_v : valid;
  assign ALU_io_din_1 = alu_din_1;
  assign ALU_io_din_2 = alu_din_2;
  assign ALU_io_op_config = io_op_config;
  always @(posedge clock) begin
    if (reset) begin
      alu_din_1 <= 32'h0;
    end else if (io_loop_source == 2'h0) begin
      alu_din_1 <= io_din_1;
    end else if (io_loop_source == 2'h1) begin
      if (~loaded) begin
        alu_din_1 <= io_din_1;
      end else begin
        alu_din_1 <= dout_Reg;
      end
    end else if (io_loop_source == 2'h2) begin
      alu_din_1 <= io_din_1;
    end else begin
      alu_din_1 <= 32'h1f;
    end
    if (reset) begin
      alu_din_2 <= 32'h0;
    end else if (io_loop_source == 2'h0) begin
      alu_din_2 <= io_din_2;
    end else if (io_loop_source == 2'h1) begin
      alu_din_2 <= io_din_2;
    end else if (io_loop_source == 2'h2) begin
      alu_din_2 <= _GEN_3;
    end else begin
      alu_din_2 <= 32'h1f;
    end
    if (reset) begin
      alu_dout <= 32'h0;
    end else begin
      alu_dout <= ALU_io_dout;
    end
    if (reset) begin
      dout_Reg <= 32'h0;
    end else if (_T_21) begin
      dout_Reg <= alu_dout;
    end else if (_T_28) begin
      dout_Reg <= alu_dout;
    end else begin
      dout_Reg <= 32'h0;
    end
    if (reset) begin
      count <= 16'hffff;
    end else if (_T_21) begin
      count <= 16'h0;
    end else if (_T_14) begin
      count <= _count_T_1;
    end else begin
      count <= 16'h0;
    end
    if (reset) begin
      loaded <= 1'h0;
    end else if (_T_21) begin
      loaded <= 1'h0;
    end else begin
      loaded <= _T_14;
    end
    if (reset) begin
      valid <= 1'h0;
    end else begin
      valid <= _GEN_16;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  alu_din_1 = _RAND_0[31:0];
  _RAND_1 = {1{`RANDOM}};
  alu_din_2 = _RAND_1[31:0];
  _RAND_2 = {1{`RANDOM}};
  alu_dout = _RAND_2[31:0];
  _RAND_3 = {1{`RANDOM}};
  dout_Reg = _RAND_3[31:0];
  _RAND_4 = {1{`RANDOM}};
  count = _RAND_4[15:0];
  _RAND_5 = {1{`RANDOM}};
  loaded = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  valid = _RAND_6[0:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule