data/full_repos/permissive/433624543/generic_n_x_n_mult.v
data/verilator_xmls/77bc6db2-608d-4a2f-a0fe-edfaf76a4baf.xml
module two_in_and_gate(input a, b, output reg z);
    always @(a or b)
    begin
        z = a & b;
    end
endmodule
module two_in_and_gate(input a, b, output reg z);

    always @(a or b)
    begin
        z = a & b;
    end
endmodule