data/full_repos/permissive/411457613/Pyverilog/verilogcode/supply.v
data/verilator_xmls/5291c942-bd4e-4b61-8fb4-082821c07666.xml
module TOP(CLK, RST);
  input CLK, RST;
  parameter AAA = 1;
  supply0 VSS;
  supply1 VDD;
endmodule
module TOP(CLK, RST);

  input CLK, RST;
  parameter AAA = 1;
  supply0 VSS;
  supply1 VDD;
endmodule