data/full_repos/permissive/439731184/udp_flip_flop.v
1: b'%Error: data/full_repos/permissive/439731184/udp_flip_flop.v:27: syntax error, unexpected \'(\', expecting IDENTIFIER\nflip_flop(out, in);\n          ^~~\n%Error: data/full_repos/permissive/439731184/udp_flip_flop.v:31: Unsupported or unknown PLI call: $monitor\n    $monitor("%b\\t%b", in, out);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/439731184/udp_flip_flop.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #1 in = 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/439731184/udp_flip_flop.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #2 in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/udp_flip_flop.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #2 in = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/udp_flip_flop.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #10 in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/udp_flip_flop.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #3 in = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/udp_flip_flop.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #4 in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/udp_flip_flop.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #5 in = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/udp_flip_flop.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #6 in = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/udp_flip_flop.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #1 $finish;\n    ^\n%Error: Exiting due to 2 error(s), 9 warning(s)\n'
module test();

wire out;
reg in;

flip_flop(out, in);

initial begin
    $display("in\tout");
    $monitor("%b\t%b", in, out);
    in = 0;
    #1 in = 1;
    #2 in = 0;
    #2 in = 1;
    #10 in = 0;
    #3 in = 1;
    #4 in = 0;
    #5 in = 1;
    #6 in = 0;
    #1 $finish;
end

endmodule
module test();


wire out;
reg in;

flip_flop(out, in);

initial begin
    $display("in\tout");
    $monitor("%b\t%b", in, out);
    in = 0;
    #1 in = 1;
    #2 in = 0;
    #2 in = 1;
    #10 in = 0;
    #3 in = 1;
    #4 in = 0;
    #5 in = 1;
    #6 in = 0;
    #1 $finish;
end

endmodule