data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/DMem_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/DMem_TB.v:20: Unsupported: Ignoring delay on this delayed statement.\n            #5; \n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/DMem_TB.v:22: Unsupported: Ignoring delay on this delayed statement.\n            #5;  \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/DMem_TB.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/DMem_TB.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/DMem_TB.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #9;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/DMem_TB.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/DMem_TB.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/DMem_TB.v:60: Unsupported: Ignoring delay on this delayed statement.\n        #9;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/DMem_TB.v:67: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/DMem_TB.v:74: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/DMem_TB.v:76: Unsupported: Ignoring delay on this delayed statement.\n        #9;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/DMem_TB.v:82: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/DMem_TB.v:90: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/DMem_TB.v:92: Unsupported: Ignoring delay on this delayed statement.\n        #9;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/DMem_TB.v:98: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/DMem_TB.v:106: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/DMem_TB.v:108: Unsupported: Ignoring delay on this delayed statement.\n        #9;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/DMem_TB.v:114: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/DMem_TB.v:116: Unsupported: Ignoring delay on this delayed statement.\n        #9;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/DMem_TB.v:122: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/DMem_TB.v:124: Unsupported: Ignoring delay on this delayed statement.\n        #9;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/DMem_TB.v:129: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/DMem_TB.v:131: Unsupported: Ignoring delay on this delayed statement.\n        #9;\n        ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/DMem_TB.v:15: Cannot find file containing module: \'DMem\'\n    DMem DUT(.addr_in(addr), .data_in(data_in), .we(we), .clk(clk), .rd(rd), .data_out(data));\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new,data/full_repos/permissive/433174928/DMem\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new,data/full_repos/permissive/433174928/DMem.v\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new,data/full_repos/permissive/433174928/DMem.sv\n             DMem\n             DMem.v\n             DMem.sv\n             obj_dir/DMem\n             obj_dir/DMem.v\n             obj_dir/DMem.sv\n%Error: Exiting due to 1 error(s), 23 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module DMem_TB(

    );
    
    reg [31:0] addr;
    reg [31:0] data_in;
    reg [3:0]we;
    reg clk;
    reg rd;
    reg rst;
    wire  [31:0] data;
    
    DMem DUT(.addr_in(addr), .data_in(data_in), .we(we), .clk(clk), .rd(rd), .data_out(data));
    
    initial begin : CLK_GEN
        forever begin
            clk = 1; 
            #5; 
            clk = 0; 
            #5;
        end
    end

    initial begin
       data_in=32'h01010101;

        rd=1'b0;
        rst=1'b1;
        we=4'b0001;
        addr=32'h80000000;
        #10;

        
        rd=1'b1;
        rst=1'b1;
        we=4'b0000;
        addr=32'h80000000;

        #1;
        if(data!=32'h00000001) $fatal("The Data memory or RAM is not reading properly");
        #9;
        
        
        
        rd=1'b0;
        rst=1'b1;
        we=4'b0010;
         addr=32'h80000004;
        #10;
        
        rd=1'b1;
        rst=1'b1;
        we=4'b0000;
        addr=32'h80000004;

        #1;
        if(data!=32'h00000100) $fatal("The Data memory or RAM is not reading properly");
        #9;
        
        
        rd=1'b0;
        rst=1'b1;
        we=4'b0100;
        addr=32'h80000008;
        #10;

        rd=1'b1;
        rst=1'b1;
        we=4'b0000;
        addr=32'h80000008;

        #1;
        if(data!=32'h00010000) $fatal("The Data memory or RAM is not reading properly");
        #9;
        
        rd=1'b0;
        rst=1'b1;
        we=4'b1000;
         addr=32'h8000000c;
        #10;


        rd=1'b1;
        rst=1'b1;
        we=4'b0000;
        addr=32'h8000000c;

        #1;
        if(data!=32'h01000000) $fatal("The Data memory or RAM is not reading properly");
        #9;
        
        rd=1'b0;
        rst=1'b1;
        we=4'b1111;
        addr=32'h80000010;
        #10;
       
        
        rd=1'b1;
        rst=1'b1;
        we=4'b0000;
        addr=32'h80000010;

        #1;
        if(data!=32'h01010101) $fatal("The Data memory or RAM is not reading properly");
        #9;
        
        
        addr=32'h00100000;
        we=4'b0000;
        rd=1'b1;
        #1;
        if(data!=32'h13391993) $fatal("The Data memory or RAM is not reading properly");
        #9;
        
        
        addr=32'h00100004;
        we=4'b0000;
        rd=1'b1;
        #1;
        if(data!=32'h13643732) $fatal("The Data memory or RAM is not reading properly");
        #9;
        
        addr=32'h00100008;
        we=4'b0000;
        rd=1'b1;
        #1;
        if(data!=32'h17456399) $fatal("The Data memory or RAM is not reading properly");
        #9;
        






        






        
        $display("All tests passed");
        $finish;
    end
endmodule
module DMem_TB(

    );

    
    reg [31:0] addr;
    reg [31:0] data_in;
    reg [3:0]we;
    reg clk;
    reg rd;
    reg rst;
    wire  [31:0] data;
    
    DMem DUT(.addr_in(addr), .data_in(data_in), .we(we), .clk(clk), .rd(rd), .data_out(data));
    
    initial begin : CLK_GEN
        forever begin
            clk = 1; 
            #5; 
            clk = 0; 
            #5;
        end
    end

    initial begin
       data_in=32'h01010101;

        rd=1'b0;
        rst=1'b1;
        we=4'b0001;
        addr=32'h80000000;
        #10;

        
        rd=1'b1;
        rst=1'b1;
        we=4'b0000;
        addr=32'h80000000;

        #1;
        if(data!=32'h00000001) $fatal("The Data memory or RAM is not reading properly");
        #9;
        
        
        
        rd=1'b0;
        rst=1'b1;
        we=4'b0010;
         addr=32'h80000004;
        #10;
        
        rd=1'b1;
        rst=1'b1;
        we=4'b0000;
        addr=32'h80000004;

        #1;
        if(data!=32'h00000100) $fatal("The Data memory or RAM is not reading properly");
        #9;
        
        
        rd=1'b0;
        rst=1'b1;
        we=4'b0100;
        addr=32'h80000008;
        #10;

        rd=1'b1;
        rst=1'b1;
        we=4'b0000;
        addr=32'h80000008;

        #1;
        if(data!=32'h00010000) $fatal("The Data memory or RAM is not reading properly");
        #9;
        
        rd=1'b0;
        rst=1'b1;
        we=4'b1000;
         addr=32'h8000000c;
        #10;


        rd=1'b1;
        rst=1'b1;
        we=4'b0000;
        addr=32'h8000000c;

        #1;
        if(data!=32'h01000000) $fatal("The Data memory or RAM is not reading properly");
        #9;
        
        rd=1'b0;
        rst=1'b1;
        we=4'b1111;
        addr=32'h80000010;
        #10;
       
        
        rd=1'b1;
        rst=1'b1;
        we=4'b0000;
        addr=32'h80000010;

        #1;
        if(data!=32'h01010101) $fatal("The Data memory or RAM is not reading properly");
        #9;
        
        
        addr=32'h00100000;
        we=4'b0000;
        rd=1'b1;
        #1;
        if(data!=32'h13391993) $fatal("The Data memory or RAM is not reading properly");
        #9;
        
        
        addr=32'h00100004;
        we=4'b0000;
        rd=1'b1;
        #1;
        if(data!=32'h13643732) $fatal("The Data memory or RAM is not reading properly");
        #9;
        
        addr=32'h00100008;
        we=4'b0000;
        rd=1'b1;
        #1;
        if(data!=32'h17456399) $fatal("The Data memory or RAM is not reading properly");
        #9;
        






        






        
        $display("All tests passed");
        $finish;
    end
endmodule