data/full_repos/permissive/418284997/src/rv32im/rv32im_div.v
data/verilator_xmls/f3554ef8-3940-40b2-a1a4-d0ad62338180.xml
module rv32im_div #(parameter WIDTH=4) (
    input wire clk_i,
    input wire clear_i,
    input wire start,
    output reg busy,
    output reg valid,
    output reg dbz,
    input wire [WIDTH-1:0] x,
    input wire [WIDTH-1:0] y,
    output reg [WIDTH-1:0] q,
    output reg [WIDTH-1:0] r
    );

    localparam WIDTH_M1 = WIDTH-1;

    reg [WIDTH-1:0] y1;
    initial y1 = 0;
    reg [WIDTH-1:0] q1, q1_next;
    initial q1 = 0;
    initial q1_next = 0;
    reg [WIDTH:0] ac, ac_next;
    initial ac = 0;
    initial ac_next = 0;
    reg [$clog2(WIDTH)-1:0] i;
    initial i = 0;

    always @(*) begin
        if (ac >= {1'b0,y1}) begin
            ac_next = ac - y1;
            {ac_next, q1_next} = {ac_next[WIDTH-1:0], q1, 1'b1};
        end else begin
            {ac_next, q1_next} = {ac, q1} << 1;
        end
    end

    always @(posedge clk_i) begin
        if (clear_i) begin
            valid <= 0;
            busy <= 0;
        end else if (start) begin
            valid <= 0;
            i <= 0;
            if (y == 0) begin
                busy <= 0;
                dbz <= 1;
            end else begin
                busy <= 1;
                dbz <= 0;
                y1 <= y;
                {ac, q1} <= {{WIDTH{1'b0}}, x, 1'b0};
            end
        end else if (busy) begin
            if (i == WIDTH_M1[$clog2(WIDTH)-1:0]) begin
                busy <= 0;
                valid <= 1;
                q <= q1_next;
                r <= ac_next[WIDTH:1];
            end else begin
                i <= i + 1;
                ac <= ac_next;
                q1 <= q1_next;
            end
        end else begin
            valid <= 1'b0;
        end
    end
endmodule
module rv32im_div #(parameter WIDTH=4) (
    input wire clk_i,
    input wire clear_i,
    input wire start,
    output reg busy,
    output reg valid,
    output reg dbz,
    input wire [WIDTH-1:0] x,
    input wire [WIDTH-1:0] y,
    output reg [WIDTH-1:0] q,
    output reg [WIDTH-1:0] r
    );


    localparam WIDTH_M1 = WIDTH-1;

    reg [WIDTH-1:0] y1;
    initial y1 = 0;
    reg [WIDTH-1:0] q1, q1_next;
    initial q1 = 0;
    initial q1_next = 0;
    reg [WIDTH:0] ac, ac_next;
    initial ac = 0;
    initial ac_next = 0;
    reg [$clog2(WIDTH)-1:0] i;
    initial i = 0;

    always @(*) begin
        if (ac >= {1'b0,y1}) begin
            ac_next = ac - y1;
            {ac_next, q1_next} = {ac_next[WIDTH-1:0], q1, 1'b1};
        end else begin
            {ac_next, q1_next} = {ac, q1} << 1;
        end
    end

    always @(posedge clk_i) begin
        if (clear_i) begin
            valid <= 0;
            busy <= 0;
        end else if (start) begin
            valid <= 0;
            i <= 0;
            if (y == 0) begin
                busy <= 0;
                dbz <= 1;
            end else begin
                busy <= 1;
                dbz <= 0;
                y1 <= y;
                {ac, q1} <= {{WIDTH{1'b0}}, x, 1'b0};
            end
        end else if (busy) begin
            if (i == WIDTH_M1[$clog2(WIDTH)-1:0]) begin
                busy <= 0;
                valid <= 1;
                q <= q1_next;
                r <= ac_next[WIDTH:1];
            end else begin
                i <= i + 1;
                ac <= ac_next;
                q1 <= q1_next;
            end
        end else begin
            valid <= 1'b0;
        end
    end
endmodule