data/full_repos/permissive/475371394/generators/cgra2x2/src/main/resources/mux_7to1_32b.v
data/verilator_xmls/f46aeae9-39b3-4288-a1c5-45892f67bba9.xml
module mux_7to1_32b(in0, in1, in2, in3, in4, in5, in6, out, select);
    parameter size = 32;

    input [size-1:0] in0;
    input [size-1:0] in1;
    input [size-1:0] in2;
    input [size-1:0] in3;
    input [size-1:0] in4;
    input [size-1:0] in5;
    input [size-1:0] in6;
    output reg [size-1:0] out;
    input [2:0] select;
    always @(*)
        case (select)
            0: out = in0;
            1: out = in1;
            2: out = in2;
            3: out = in3;
            4: out = in4;
            5: out = in5;
            6: out = in6;
            default: out = {size{1'bx}};
        endcase
endmodule
module mux_7to1_32b(in0, in1, in2, in3, in4, in5, in6, out, select);

    parameter size = 32;

    input [size-1:0] in0;
    input [size-1:0] in1;
    input [size-1:0] in2;
    input [size-1:0] in3;
    input [size-1:0] in4;
    input [size-1:0] in5;
    input [size-1:0] in6;
    output reg [size-1:0] out;
    input [2:0] select;
    always @(*)
        case (select)
            0: out = in0;
            1: out = in1;
            2: out = in2;
            3: out = in3;
            4: out = in4;
            5: out = in5;
            6: out = in6;
            default: out = {size{1'bx}};
        endcase
endmodule