data/full_repos/permissive/501402725/mbs_1a/src/LFSRmod.v
data/verilator_xmls/22f8029e-a6cb-4ae8-b8a8-cba30dd94f62.xml
module LFSRmod (CLOCK, RESET, ENABLE, OUTDATA);
	input wire CLOCK, RESET, ENABLE;
	output reg [18:0] OUTDATA;

	reg value;
	reg [18:0] out;

	always @(*) begin
		value = ~(out[18] ^ out[5] ^ out[1] ^ out[0]);
		OUTDATA = out;
	end

	always @(posedge CLOCK) begin
		if (RESET) begin
			out <= 19'b1;
		end

		else begin
			if(ENABLE)
			begin
				out[18:0] <= { value , out[18:1] };
			end
		end
	end
endmodule
module LFSRmod (CLOCK, RESET, ENABLE, OUTDATA);

	input wire CLOCK, RESET, ENABLE;
	output reg [18:0] OUTDATA;

	reg value;
	reg [18:0] out;

	always @(*) begin
		value = ~(out[18] ^ out[5] ^ out[1] ^ out[0]);
		OUTDATA = out;
	end

	always @(posedge CLOCK) begin
		if (RESET) begin
			out <= 19'b1;
		end

		else begin
			if(ENABLE)
			begin
				out[18:0] <= { value , out[18:1] };
			end
		end
	end
endmodule