data/full_repos/permissive/473722449/counter_4bit_asyn.v
data/verilator_xmls/8c1a67f5-323c-4a16-a51a-e972bd30c473.xml
module counter_4bit_asyn(
    input wire clk,
    output reg [3:0] count
    );
    initial count= 4'b0;
    
    always@(negedge clk)
    count[0]<=~count[0];
    
    
    always@(negedge count[0])
    count[1]<=~count[1];
    
    
    always@(negedge count[1])
    count[2]<=~count[2];
    
    
    always@(negedge count[2])
    count[3]<=~count[3];
    
endmodule
module counter_4bit_asyn(
    input wire clk,
    output reg [3:0] count
    );

    initial count= 4'b0;
    
    always@(negedge clk)
    count[0]<=~count[0];
    
    
    always@(negedge count[0])
    count[1]<=~count[1];
    
    
    always@(negedge count[1])
    count[2]<=~count[2];
    
    
    always@(negedge count[2])
    count[3]<=~count[3];
    
endmodule