data/full_repos/permissive/468066752/rtl/RS232.sv
1: b'%Error: data/full_repos/permissive/468066752/rtl/RS232.sv:60: Cannot find file containing module: \'UART_RX\'\n  UART_RX rx (\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/468066752/rtl,data/full_repos/permissive/468066752/UART_RX\n             data/full_repos/permissive/468066752/rtl,data/full_repos/permissive/468066752/UART_RX.v\n             data/full_repos/permissive/468066752/rtl,data/full_repos/permissive/468066752/UART_RX.sv\n             UART_RX\n             UART_RX.v\n             UART_RX.sv\n             obj_dir/UART_RX\n             obj_dir/UART_RX.v\n             obj_dir/UART_RX.sv\n%Error: data/full_repos/permissive/468066752/rtl/RS232.sv:69: Cannot find file containing module: \'UART_TX\'\n  UART_TX tx (\n  ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/468066752/rtl/RS232.sv:93: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 8 bits.\n                                                                    : ... In instance RS232\n          DATA_O                       <= fifo_rx[fifo_rx_read_addr];\n                                       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/468066752/rtl/RS232.sv:99: Operator LTE expects 32 bits on the LHS, but LHS\'s VARREF \'fifo_rx_len\' generates 7 bits.\n                                                                    : ... In instance RS232\n        if (RX_DATA_VALID == 1\'b1 && fifo_rx_len <= FIFO_WIDTH) begin\n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/468066752/rtl/RS232.sv:121: Operator LTE expects 32 bits on the LHS, but LHS\'s VARREF \'fifo_tx_len\' generates 7 bits.\n                                                                     : ... In instance RS232\n      if (WRSTB && (ADDR >= BASEADDRESS) && (ADDR[0] == 1\'b0) && fifo_tx_len <= FIFO_WIDTH) begin\n                                                                             ^~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module RS232 #(
  parameter int BASEADDRESS = 32'h6000_0000,


  parameter int CLOCK_FREQ  = 50_000_000,
  parameter int BAUD_RATE   = 115200,
  parameter int FIFO_WIDTH  = 64
) (
  input       logic         ACLK,
  input       logic         RESET,
  input       logic [31:00] DATA_I,
  output      logic [31:00] DATA_O,
  input       logic [31:00] ADDR,
  input       logic         WRSTB,
  input       logic         RDSTB,

  input 		  logic     		UART_CTS,
  output		  logic     		UART_RTS,
  input 		  logic     		UART_RXD,
  output		  logic     		UART_TXD
);

  logic [07:00] fifo_rx [0:FIFO_WIDTH-1];


  logic [$clog2(FIFO_WIDTH)-1:00] fifo_rx_read_addr;
  logic [$clog2(FIFO_WIDTH)-1:00] fifo_rx_write_addr;


  logic [$clog2(FIFO_WIDTH)  :00] fifo_rx_len;


  logic [07:00] fifo_tx [0:FIFO_WIDTH-1];


  logic [$clog2(FIFO_WIDTH)-1:00] fifo_tx_read_addr;
  logic [$clog2(FIFO_WIDTH)-1:00] fifo_tx_write_addr;


  logic [$clog2(FIFO_WIDTH)  :00] fifo_tx_len;


  logic [07:00] RX_DATA;

  logic         RX_DATA_VALID;

  logic         RX_DATA_READ;


  logic [07:00] TX_DATA;

  logic         TX_DATA_VALID;

  logic         TX_DATA_READ;

  logic         TX_IDLE;



  UART_RX rx (
    .ACLK(ACLK),
    .RESET(RESET),
    .RXD(UART_RXD),
    .RX_DATA_READ(RX_DATA_READ),
    .RX_DATA(RX_DATA),
    .RX_DATA_VALID(RX_DATA_VALID)
  );

  UART_TX tx (
    .ACLK(ACLK),
    .RESET(RESET),
    .TXD(UART_TXD),
    .TX_DATA_READ(TX_DATA_READ),
    .TX_DATA(TX_DATA),
    .TX_DATA_VALID(TX_DATA_VALID),
    .UART_CTS(UART_CTS),
    .UART_RTS(UART_RTS),
    .TX_IDLE(TX_IDLE)
  );





  always_ff @(posedge ACLK or posedge RESET) begin : readRXData
    if (RESET == 1) begin
      fifo_rx_write_addr  <= 'd0;
      fifo_rx_read_addr   <= 'd0;
      RX_DATA_READ        <= 1'd0;
      fifo_rx_len         <= 'd0;
    end else begin
      if (RDSTB && (ADDR >= BASEADDRESS) && (ADDR[0] == 1'b1) && fifo_rx_len > 0) begin
          DATA_O                       <= fifo_rx[fifo_rx_read_addr];
          fifo_rx_read_addr            <= fifo_rx_read_addr + 6'd1;
          fifo_rx_len                  <= fifo_rx_len - 7'd1;
      end
      else begin
        DATA_O                         <= 32'dz;
        if (RX_DATA_VALID == 1'b1 && fifo_rx_len <= FIFO_WIDTH) begin
          fifo_rx[fifo_rx_write_addr]  <= RX_DATA;
          fifo_rx_write_addr           <= fifo_rx_write_addr + 6'd1;
          RX_DATA_READ                 <= 1'd1;
          fifo_rx_len                  <= fifo_rx_len + 7'd1;
        end
        else begin
          RX_DATA_READ                  <= 1'd0;
        end
      end
    end
  end : readRXData




  always_ff @(posedge ACLK or posedge RESET) begin : writeTXFIFO
    if (RESET == 1) begin
      fifo_tx_write_addr  <= 'd0;
      fifo_tx_read_addr   <= 'd0;
      fifo_tx_len         <= 'd0;
    end else begin
      if (WRSTB && (ADDR >= BASEADDRESS) && (ADDR[0] == 1'b0) && fifo_tx_len <= FIFO_WIDTH) begin
        fifo_tx[fifo_rx_write_addr]    <= DATA_I[07:00];
        fifo_tx_write_addr             <= fifo_tx_write_addr + 6'd1;
        fifo_tx_len                    <= fifo_tx_len + 7'd1;
      end
      else if (TX_IDLE == 1'b1) begin
        TX_DATA                        <= fifo_tx[fifo_tx_read_addr];
        TX_DATA_VALID                  <= 1'b1;
        fifo_tx_read_addr              <= fifo_tx_read_addr + 6'd1;
        fifo_tx_len                    <= fifo_tx_len - 7'd1;
      end
    end
  end : writeTXFIFO

endmodule
module RS232 #(
  parameter int BASEADDRESS = 32'h6000_0000,


  parameter int CLOCK_FREQ  = 50_000_000,
  parameter int BAUD_RATE   = 115200,
  parameter int FIFO_WIDTH  = 64
) (
  input       logic         ACLK,
  input       logic         RESET,
  input       logic [31:00] DATA_I,
  output      logic [31:00] DATA_O,
  input       logic [31:00] ADDR,
  input       logic         WRSTB,
  input       logic         RDSTB,

  input 		  logic     		UART_CTS,
  output		  logic     		UART_RTS,
  input 		  logic     		UART_RXD,
  output		  logic     		UART_TXD
);


  logic [07:00] fifo_rx [0:FIFO_WIDTH-1];


  logic [$clog2(FIFO_WIDTH)-1:00] fifo_rx_read_addr;
  logic [$clog2(FIFO_WIDTH)-1:00] fifo_rx_write_addr;


  logic [$clog2(FIFO_WIDTH)  :00] fifo_rx_len;


  logic [07:00] fifo_tx [0:FIFO_WIDTH-1];


  logic [$clog2(FIFO_WIDTH)-1:00] fifo_tx_read_addr;
  logic [$clog2(FIFO_WIDTH)-1:00] fifo_tx_write_addr;


  logic [$clog2(FIFO_WIDTH)  :00] fifo_tx_len;


  logic [07:00] RX_DATA;

  logic         RX_DATA_VALID;

  logic         RX_DATA_READ;


  logic [07:00] TX_DATA;

  logic         TX_DATA_VALID;

  logic         TX_DATA_READ;

  logic         TX_IDLE;



  UART_RX rx (
    .ACLK(ACLK),
    .RESET(RESET),
    .RXD(UART_RXD),
    .RX_DATA_READ(RX_DATA_READ),
    .RX_DATA(RX_DATA),
    .RX_DATA_VALID(RX_DATA_VALID)
  );

  UART_TX tx (
    .ACLK(ACLK),
    .RESET(RESET),
    .TXD(UART_TXD),
    .TX_DATA_READ(TX_DATA_READ),
    .TX_DATA(TX_DATA),
    .TX_DATA_VALID(TX_DATA_VALID),
    .UART_CTS(UART_CTS),
    .UART_RTS(UART_RTS),
    .TX_IDLE(TX_IDLE)
  );





  always_ff @(posedge ACLK or posedge RESET) begin : readRXData
    if (RESET == 1) begin
      fifo_rx_write_addr  <= 'd0;
      fifo_rx_read_addr   <= 'd0;
      RX_DATA_READ        <= 1'd0;
      fifo_rx_len         <= 'd0;
    end else begin
      if (RDSTB && (ADDR >= BASEADDRESS) && (ADDR[0] == 1'b1) && fifo_rx_len > 0) begin
          DATA_O                       <= fifo_rx[fifo_rx_read_addr];
          fifo_rx_read_addr            <= fifo_rx_read_addr + 6'd1;
          fifo_rx_len                  <= fifo_rx_len - 7'd1;
      end
      else begin
        DATA_O                         <= 32'dz;
        if (RX_DATA_VALID == 1'b1 && fifo_rx_len <= FIFO_WIDTH) begin
          fifo_rx[fifo_rx_write_addr]  <= RX_DATA;
          fifo_rx_write_addr           <= fifo_rx_write_addr + 6'd1;
          RX_DATA_READ                 <= 1'd1;
          fifo_rx_len                  <= fifo_rx_len + 7'd1;
        end
        else begin
          RX_DATA_READ                  <= 1'd0;
        end
      end
    end
  end : readRXData




  always_ff @(posedge ACLK or posedge RESET) begin : writeTXFIFO
    if (RESET == 1) begin
      fifo_tx_write_addr  <= 'd0;
      fifo_tx_read_addr   <= 'd0;
      fifo_tx_len         <= 'd0;
    end else begin
      if (WRSTB && (ADDR >= BASEADDRESS) && (ADDR[0] == 1'b0) && fifo_tx_len <= FIFO_WIDTH) begin
        fifo_tx[fifo_rx_write_addr]    <= DATA_I[07:00];
        fifo_tx_write_addr             <= fifo_tx_write_addr + 6'd1;
        fifo_tx_len                    <= fifo_tx_len + 7'd1;
      end
      else if (TX_IDLE == 1'b1) begin
        TX_DATA                        <= fifo_tx[fifo_tx_read_addr];
        TX_DATA_VALID                  <= 1'b1;
        fifo_tx_read_addr              <= fifo_tx_read_addr + 6'd1;
        fifo_tx_len                    <= fifo_tx_len - 7'd1;
      end
    end
  end : writeTXFIFO

endmodule