data/full_repos/permissive/514313792/prj_qsys/avalon_lcd_rgb_controller/rtl/burst_read_master.v
1: b'%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_lcd_rgb_controller/rtl/burst_read_master.v:188: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s AND generates 32 bits.\n                                                                                                                   : ... In instance burst_read_master\n assign burst_boundary_word_address = ((address / BYTEENABLEWIDTH) & (MAXBURSTCOUNT - 1));\n                                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_lcd_rgb_controller/rtl/burst_read_master.v:192: Operator AND expects 3 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                                                   : ... In instance burst_read_master\n assign first_short_burst_count = ((burst_boundary_word_address & 1\'b1) == 1\'b1)? 1 :   \n                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_lcd_rgb_controller/rtl/burst_read_master.v:192: Operator EQ expects 3 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                                                   : ... In instance burst_read_master\n assign first_short_burst_count = ((burst_boundary_word_address & 1\'b1) == 1\'b1)? 1 :   \n                                                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_lcd_rgb_controller/rtl/burst_read_master.v:193: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'burst_boundary_word_address\' generates 3 bits.\n                                                                                                                   : ... In instance burst_read_master\n           (((MAXBURSTCOUNT - burst_boundary_word_address) < (length / BYTEENABLEWIDTH))?\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_lcd_rgb_controller/rtl/burst_read_master.v:194: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'burst_boundary_word_address\' generates 3 bits.\n                                                                                                                   : ... In instance burst_read_master\n           (MAXBURSTCOUNT - burst_boundary_word_address) : (length / BYTEENABLEWIDTH));\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_lcd_rgb_controller/rtl/burst_read_master.v:192: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                                                   : ... In instance burst_read_master\n assign first_short_burst_count = ((burst_boundary_word_address & 1\'b1) == 1\'b1)? 1 :   \n                                ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_lcd_rgb_controller/rtl/burst_read_master.v:195: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s DIV generates 32 bits.\n                                                                                                                   : ... In instance burst_read_master\n assign final_short_burst_count = (length / BYTEENABLEWIDTH);\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_lcd_rgb_controller/rtl/burst_read_master.v:216: Operator ADD expects 5 bits on the RHS, but RHS\'s VARREF \'burst_count\' generates 3 bits.\n                                                                                                                   : ... In instance burst_read_master\n     reads_pending <= reads_pending + burst_count;\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/514313792/prj_qsys/avalon_lcd_rgb_controller/rtl/burst_read_master.v:220: Operator ADD expects 32 or 5 bits on the RHS, but RHS\'s VARREF \'burst_count\' generates 3 bits.\n                                                                                                                   : ... In instance burst_read_master\n     reads_pending <= reads_pending + burst_count - 1;   \n                                    ^\n%Error: data/full_repos/permissive/514313792/prj_qsys/avalon_lcd_rgb_controller/rtl/burst_read_master.v:240: Cannot find file containing module: \'dcfifo_mixed_widths\'\n dcfifo_mixed_widths the_master_to_user_fifo (\n ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514313792/prj_qsys/avalon_lcd_rgb_controller/rtl,data/full_repos/permissive/514313792/dcfifo_mixed_widths\n             data/full_repos/permissive/514313792/prj_qsys/avalon_lcd_rgb_controller/rtl,data/full_repos/permissive/514313792/dcfifo_mixed_widths.v\n             data/full_repos/permissive/514313792/prj_qsys/avalon_lcd_rgb_controller/rtl,data/full_repos/permissive/514313792/dcfifo_mixed_widths.sv\n             dcfifo_mixed_widths\n             dcfifo_mixed_widths.v\n             dcfifo_mixed_widths.sv\n             obj_dir/dcfifo_mixed_widths\n             obj_dir/dcfifo_mixed_widths.v\n             obj_dir/dcfifo_mixed_widths.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n'
module burst_read_master (
	clk,
	reset,


	control_fixed_location,
	control_read_base,
	control_read_length,
	control_go,
	control_done,
	control_early_done,
	

	user_read_clock,
	user_read_buffer,
	user_buffer_data,
	user_data_available,
	

	master_address,
	master_read,
	master_byteenable,
	master_readdata,
	master_readdatavalid,
	master_burstcount,
	master_waitrequest
);

	parameter DATAWIDTH = 32;
	parameter MAXBURSTCOUNT = 4;
	parameter BURSTCOUNTWIDTH = 3;
	parameter BYTEENABLEWIDTH = 4;
	parameter ADDRESSWIDTH = 32;
	parameter FIFODEPTH = 32;
	parameter FIFODEPTH_LOG2 = 5;
	parameter FIFOUSEMEMORY = 1;
	
	input clk;
	input reset;



	input control_fixed_location;
	input [ADDRESSWIDTH-1:0] control_read_base;
	input [ADDRESSWIDTH-1:0] control_read_length;
	input control_go;
	output wire control_done;
	output wire control_early_done;
	

	input user_read_clock;
	input user_read_buffer;
	output wire [DATAWIDTH-1:0] user_buffer_data;
	output wire user_data_available;
	

	input master_waitrequest;
	input master_readdatavalid;
    input [DATAWIDTH-1:0] master_readdata;
	output wire [ADDRESSWIDTH-1:0] master_address;
	output wire master_read;
	output wire [BYTEENABLEWIDTH-1:0] master_byteenable;
	output wire [BURSTCOUNTWIDTH-1:0] master_burstcount;
	

	reg control_fixed_location_d1;
	wire fifo_empty;
	reg [ADDRESSWIDTH-1:0] address;
	reg [ADDRESSWIDTH-1:0] length;
	reg [FIFODEPTH_LOG2-1:0] reads_pending;
	wire increment_address;
	wire [BURSTCOUNTWIDTH-1:0] burst_count;
	wire [BURSTCOUNTWIDTH-1:0] first_short_burst_count;
	wire first_short_burst_enable;
	wire [BURSTCOUNTWIDTH-1:0] final_short_burst_count;
	wire final_short_burst_enable;
	wire [BURSTCOUNTWIDTH-1:0] burst_boundary_word_address;
	reg burst_begin;
	wire too_many_reads_pending;
	wire [FIFODEPTH_LOG2-1:0] fifo_used;




	always @ (posedge clk or posedge reset)
	begin
		if (reset == 1)
		begin
			control_fixed_location_d1 <= 0;
		end
		else
		begin
			if (control_go == 1)
			begin
				control_fixed_location_d1 <= control_fixed_location;
			end
		end
	end




	always @ (posedge clk or posedge reset)
	begin
		if (reset == 1)
		begin
			address <= 0;
		end
		else
		begin
			if(control_go == 1)
			begin
				address <= control_read_base;
			end
			else if((increment_address == 1) & (control_fixed_location_d1 == 0))
			begin
				address <= address + (burst_count * BYTEENABLEWIDTH);
			end
		end
	end




	always @ (posedge clk or posedge reset)
	begin
		if (reset == 1)
		begin
			length <= 0;
		end
		else
		begin
			if(control_go == 1)
			begin
				length <= control_read_length;
			end
			else if(increment_address == 1)
			begin
				length <= length - (burst_count * BYTEENABLEWIDTH);
			end
		end
	end	
	



	assign master_address = address;
	assign master_byteenable = -1;
	assign master_burstcount = burst_count;
	assign control_done = (length == 0) & (reads_pending == 0);
	assign control_early_done = (length == 0);
	assign master_read = (too_many_reads_pending == 0) & (length != 0);
	assign burst_boundary_word_address = ((address / BYTEENABLEWIDTH) & (MAXBURSTCOUNT - 1));
	assign first_short_burst_enable = (burst_boundary_word_address != 0);
	assign final_short_burst_enable = (length < (MAXBURSTCOUNT * BYTEENABLEWIDTH));
	
	assign first_short_burst_count = ((burst_boundary_word_address & 1'b1) == 1'b1)? 1 :
									  (((MAXBURSTCOUNT - burst_boundary_word_address) < (length / BYTEENABLEWIDTH))?
									  (MAXBURSTCOUNT - burst_boundary_word_address) : (length / BYTEENABLEWIDTH));
	assign final_short_burst_count = (length / BYTEENABLEWIDTH);
	
	assign burst_count = (first_short_burst_enable == 1)? first_short_burst_count :
						 (final_short_burst_enable == 1)? final_short_burst_count : MAXBURSTCOUNT;
	assign increment_address = (too_many_reads_pending == 0) & (master_waitrequest == 0) & (length != 0);
	assign too_many_reads_pending = (reads_pending + fifo_used) >= (FIFODEPTH - MAXBURSTCOUNT - 4);



	always @ (posedge clk or posedge reset)
	begin
		if (reset == 1)
		begin
			reads_pending <= 0;
		end
		else
		begin
			if(increment_address == 1)
			begin
				if(master_readdatavalid == 0)
				begin
					reads_pending <= reads_pending + burst_count;
				end
				else
				begin
					reads_pending <= reads_pending + burst_count - 1;
				end			
			end
			else
			begin
				if(master_readdatavalid == 0)
				begin
					reads_pending <= reads_pending;
				end
				else
				begin
					reads_pending <= reads_pending - 1;
				end				
			end
		end
	end



	assign user_data_available = !fifo_empty;
	dcfifo_mixed_widths the_master_to_user_fifo (
		.aclr (reset),
		.wrclk (clk),
		.wrreq (master_readdatavalid),
		.data (master_readdata),
		.rdclk (user_read_clock),
		.rdreq (user_read_buffer),
		.q (user_buffer_data),
		.rdempty (fifo_empty),
		.wrusedw (fifo_used),
		.rdfull (),
		.rdusedw (),
		.wrempty (),
		.wrfull ()
	);
	defparam
		the_master_to_user_fifo.intended_device_family = "Cyclone IV E",
		the_master_to_user_fifo.lpm_numwords = FIFODEPTH,
		the_master_to_user_fifo.lpm_showahead = "ON",
		the_master_to_user_fifo.lpm_type = "dcfifo_mixed_widths",
		the_master_to_user_fifo.lpm_width = 16,
		the_master_to_user_fifo.lpm_widthu = FIFODEPTH_LOG2,
		the_master_to_user_fifo.lpm_widthu_r = FIFODEPTH_LOG2 - (DATAWIDTH/16) + 1,
		the_master_to_user_fifo.lpm_width_r = DATAWIDTH,
		the_master_to_user_fifo.overflow_checking = "OFF",
		the_master_to_user_fifo.rdsync_delaypipe = 4,
		the_master_to_user_fifo.read_aclr_synch = "ON",
		the_master_to_user_fifo.underflow_checking = "OFF",
		the_master_to_user_fifo.use_eab = (FIFOUSEMEMORY == 1)? "ON" : "OFF",
		the_master_to_user_fifo.write_aclr_synch = "ON",
		the_master_to_user_fifo.wrsync_delaypipe = 4;

endmodule
module burst_read_master (
	clk,
	reset,


	control_fixed_location,
	control_read_base,
	control_read_length,
	control_go,
	control_done,
	control_early_done,
	

	user_read_clock,
	user_read_buffer,
	user_buffer_data,
	user_data_available,
	

	master_address,
	master_read,
	master_byteenable,
	master_readdata,
	master_readdatavalid,
	master_burstcount,
	master_waitrequest
);


	parameter DATAWIDTH = 32;
	parameter MAXBURSTCOUNT = 4;
	parameter BURSTCOUNTWIDTH = 3;
	parameter BYTEENABLEWIDTH = 4;
	parameter ADDRESSWIDTH = 32;
	parameter FIFODEPTH = 32;
	parameter FIFODEPTH_LOG2 = 5;
	parameter FIFOUSEMEMORY = 1;
	
	input clk;
	input reset;



	input control_fixed_location;
	input [ADDRESSWIDTH-1:0] control_read_base;
	input [ADDRESSWIDTH-1:0] control_read_length;
	input control_go;
	output wire control_done;
	output wire control_early_done;
	

	input user_read_clock;
	input user_read_buffer;
	output wire [DATAWIDTH-1:0] user_buffer_data;
	output wire user_data_available;
	

	input master_waitrequest;
	input master_readdatavalid;
    input [DATAWIDTH-1:0] master_readdata;
	output wire [ADDRESSWIDTH-1:0] master_address;
	output wire master_read;
	output wire [BYTEENABLEWIDTH-1:0] master_byteenable;
	output wire [BURSTCOUNTWIDTH-1:0] master_burstcount;
	

	reg control_fixed_location_d1;
	wire fifo_empty;
	reg [ADDRESSWIDTH-1:0] address;
	reg [ADDRESSWIDTH-1:0] length;
	reg [FIFODEPTH_LOG2-1:0] reads_pending;
	wire increment_address;
	wire [BURSTCOUNTWIDTH-1:0] burst_count;
	wire [BURSTCOUNTWIDTH-1:0] first_short_burst_count;
	wire first_short_burst_enable;
	wire [BURSTCOUNTWIDTH-1:0] final_short_burst_count;
	wire final_short_burst_enable;
	wire [BURSTCOUNTWIDTH-1:0] burst_boundary_word_address;
	reg burst_begin;
	wire too_many_reads_pending;
	wire [FIFODEPTH_LOG2-1:0] fifo_used;




	always @ (posedge clk or posedge reset)
	begin
		if (reset == 1)
		begin
			control_fixed_location_d1 <= 0;
		end
		else
		begin
			if (control_go == 1)
			begin
				control_fixed_location_d1 <= control_fixed_location;
			end
		end
	end




	always @ (posedge clk or posedge reset)
	begin
		if (reset == 1)
		begin
			address <= 0;
		end
		else
		begin
			if(control_go == 1)
			begin
				address <= control_read_base;
			end
			else if((increment_address == 1) & (control_fixed_location_d1 == 0))
			begin
				address <= address + (burst_count * BYTEENABLEWIDTH);
			end
		end
	end




	always @ (posedge clk or posedge reset)
	begin
		if (reset == 1)
		begin
			length <= 0;
		end
		else
		begin
			if(control_go == 1)
			begin
				length <= control_read_length;
			end
			else if(increment_address == 1)
			begin
				length <= length - (burst_count * BYTEENABLEWIDTH);
			end
		end
	end	
	



	assign master_address = address;
	assign master_byteenable = -1;
	assign master_burstcount = burst_count;
	assign control_done = (length == 0) & (reads_pending == 0);
	assign control_early_done = (length == 0);
	assign master_read = (too_many_reads_pending == 0) & (length != 0);
	assign burst_boundary_word_address = ((address / BYTEENABLEWIDTH) & (MAXBURSTCOUNT - 1));
	assign first_short_burst_enable = (burst_boundary_word_address != 0);
	assign final_short_burst_enable = (length < (MAXBURSTCOUNT * BYTEENABLEWIDTH));
	
	assign first_short_burst_count = ((burst_boundary_word_address & 1'b1) == 1'b1)? 1 :
									  (((MAXBURSTCOUNT - burst_boundary_word_address) < (length / BYTEENABLEWIDTH))?
									  (MAXBURSTCOUNT - burst_boundary_word_address) : (length / BYTEENABLEWIDTH));
	assign final_short_burst_count = (length / BYTEENABLEWIDTH);
	
	assign burst_count = (first_short_burst_enable == 1)? first_short_burst_count :
						 (final_short_burst_enable == 1)? final_short_burst_count : MAXBURSTCOUNT;
	assign increment_address = (too_many_reads_pending == 0) & (master_waitrequest == 0) & (length != 0);
	assign too_many_reads_pending = (reads_pending + fifo_used) >= (FIFODEPTH - MAXBURSTCOUNT - 4);



	always @ (posedge clk or posedge reset)
	begin
		if (reset == 1)
		begin
			reads_pending <= 0;
		end
		else
		begin
			if(increment_address == 1)
			begin
				if(master_readdatavalid == 0)
				begin
					reads_pending <= reads_pending + burst_count;
				end
				else
				begin
					reads_pending <= reads_pending + burst_count - 1;
				end			
			end
			else
			begin
				if(master_readdatavalid == 0)
				begin
					reads_pending <= reads_pending;
				end
				else
				begin
					reads_pending <= reads_pending - 1;
				end				
			end
		end
	end



	assign user_data_available = !fifo_empty;
	dcfifo_mixed_widths the_master_to_user_fifo (
		.aclr (reset),
		.wrclk (clk),
		.wrreq (master_readdatavalid),
		.data (master_readdata),
		.rdclk (user_read_clock),
		.rdreq (user_read_buffer),
		.q (user_buffer_data),
		.rdempty (fifo_empty),
		.wrusedw (fifo_used),
		.rdfull (),
		.rdusedw (),
		.wrempty (),
		.wrfull ()
	);
	defparam
		the_master_to_user_fifo.intended_device_family = "Cyclone IV E",
		the_master_to_user_fifo.lpm_numwords = FIFODEPTH,
		the_master_to_user_fifo.lpm_showahead = "ON",
		the_master_to_user_fifo.lpm_type = "dcfifo_mixed_widths",
		the_master_to_user_fifo.lpm_width = 16,
		the_master_to_user_fifo.lpm_widthu = FIFODEPTH_LOG2,
		the_master_to_user_fifo.lpm_widthu_r = FIFODEPTH_LOG2 - (DATAWIDTH/16) + 1,
		the_master_to_user_fifo.lpm_width_r = DATAWIDTH,
		the_master_to_user_fifo.overflow_checking = "OFF",
		the_master_to_user_fifo.rdsync_delaypipe = 4,
		the_master_to_user_fifo.read_aclr_synch = "ON",
		the_master_to_user_fifo.underflow_checking = "OFF",
		the_master_to_user_fifo.use_eab = (FIFOUSEMEMORY == 1)? "ON" : "OFF",
		the_master_to_user_fifo.write_aclr_synch = "ON",
		the_master_to_user_fifo.wrsync_delaypipe = 4;

endmodule