data/full_repos/permissive/461620575/Simple DACs/PWM/PWM_tb.v
1: b'%Error: Cannot find file containing module: DACs/PWM,data/full_repos/permissive/461620575\n        ... Looked in:\n             data/full_repos/permissive/461620575/Simple/DACs/PWM,data/full_repos/permissive/461620575\n             data/full_repos/permissive/461620575/Simple/DACs/PWM,data/full_repos/permissive/461620575.v\n             data/full_repos/permissive/461620575/Simple/DACs/PWM,data/full_repos/permissive/461620575.sv\n             DACs/PWM,data/full_repos/permissive/461620575\n             DACs/PWM,data/full_repos/permissive/461620575.v\n             DACs/PWM,data/full_repos/permissive/461620575.sv\n             obj_dir/DACs/PWM,data/full_repos/permissive/461620575\n             obj_dir/DACs/PWM,data/full_repos/permissive/461620575.v\n             obj_dir/DACs/PWM,data/full_repos/permissive/461620575.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/461620575/Simple\n%Error: Cannot find file containing module: DACs/PWM/PWM_tb.v\n%Error: Exiting due to 3 error(s)\n'
module PWM_tb;
	reg clk;
	reg rst;
	reg [9:0] PWM_in;
	
	wire PWM_out_up;
	wire PWM_out_down;
	
	PWM #(.COUNT_UP(1)) uut1 (.clk(clk), .rst(rst), .PWM_in(PWM_in), .PWM_out(PWM_out_up));
	PWM #(.COUNT_UP(0)) uut2 (.clk(clk), .rst(rst), .PWM_in(PWM_in), .PWM_out(PWM_out_down));
	
	integer i;
	
	initial begin
		clk = 1'b0;
		rst = 1'b1;
		PWM_in = 10'b0;
		
		#10;		
		rst = 1'b0;		
		#10;
		
		for(i = 0; i < 10; i = i + 1) begin
			PWM_in = 10'h3FF >> i;
			#10000;
		end
		
		$stop;
	
	end
	
	always
		#5 clk = ~clk;

endmodule
module PWM_tb;

	reg clk;
	reg rst;
	reg [9:0] PWM_in;
	
	wire PWM_out_up;
	wire PWM_out_down;
	
	PWM #(.COUNT_UP(1)) uut1 (.clk(clk), .rst(rst), .PWM_in(PWM_in), .PWM_out(PWM_out_up));
	PWM #(.COUNT_UP(0)) uut2 (.clk(clk), .rst(rst), .PWM_in(PWM_in), .PWM_out(PWM_out_down));
	
	integer i;
	
	initial begin
		clk = 1'b0;
		rst = 1'b1;
		PWM_in = 10'b0;
		
		#10;		
		rst = 1'b0;		
		#10;
		
		for(i = 0; i < 10; i = i + 1) begin
			PWM_in = 10'h3FF >> i;
			#10000;
		end
		
		$stop;
	
	end
	
	always
		#5 clk = ~clk;

endmodule