data/full_repos/permissive/503578084/pipeline/rD1_mux.v
1: b'%Error: data/full_repos/permissive/503578084/pipeline/rD1_mux.v:21: Cannot find include file: param.v\n`include    "param.v" \n            ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/503578084/pipeline,data/full_repos/permissive/503578084/param.v\n             data/full_repos/permissive/503578084/pipeline,data/full_repos/permissive/503578084/param.v.v\n             data/full_repos/permissive/503578084/pipeline,data/full_repos/permissive/503578084/param.v.sv\n             param.v\n             param.v.v\n             param.v.sv\n             obj_dir/param.v\n             obj_dir/param.v.v\n             obj_dir/param.v.sv\n%Error: data/full_repos/permissive/503578084/pipeline/rD1_mux.v:38: Define or directive not defined: \'`NO_HAZARD\'\n            `NO_HAZARD:real_rD1=rD1;\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/503578084/pipeline/rD1_mux.v:38: syntax error, unexpected \':\', expecting endcase\n            `NO_HAZARD:real_rD1=rD1;\n                      ^\n%Error: data/full_repos/permissive/503578084/pipeline/rD1_mux.v:39: Define or directive not defined: \'`HAZARD_1\'\n            `HAZARD_1:real_rD1=wD_from_ex;\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/503578084/pipeline/rD1_mux.v:40: Define or directive not defined: \'`HAZARD_2\'\n            `HAZARD_2:real_rD1=wD_from_mem;\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/503578084/pipeline/rD1_mux.v:41: Define or directive not defined: \'`LOAD_USE_HAZARD\'\n            `LOAD_USE_HAZARD:real_rD1=wD_from_mem;\n            ^~~~~~~~~~~~~~~~\n%Error: Cannot continue\n'
module rD1_mux(
    input   rst_n,
    input   [1:0]   rD1_sel,
    input   [31:0]  rD1,
    input   [31:0]  wD_from_ex,
    input   [31:0]  wD_from_mem,
    output  reg [31:0]  real_rD1
    );
    
always @ (*) begin
    if(rst_n=='b0) begin
        real_rD1=rD1;
    end
    else begin
        case(rD1_sel)
            `NO_HAZARD:real_rD1=rD1;
            `HAZARD_1:real_rD1=wD_from_ex;
            `HAZARD_2:real_rD1=wD_from_mem;
            `LOAD_USE_HAZARD:real_rD1=wD_from_mem;
            default:real_rD1=rD1;
        endcase
    end
end
    
endmodule
module rD1_mux(
    input   rst_n,
    input   [1:0]   rD1_sel,
    input   [31:0]  rD1,
    input   [31:0]  wD_from_ex,
    input   [31:0]  wD_from_mem,
    output  reg [31:0]  real_rD1
    );

    
always @ (*) begin
    if(rst_n=='b0) begin
        real_rD1=rD1;
    end
    else begin
        case(rD1_sel)
            `NO_HAZARD:real_rD1=rD1;
            `HAZARD_1:real_rD1=wD_from_ex;
            `HAZARD_2:real_rD1=wD_from_mem;
            `LOAD_USE_HAZARD:real_rD1=wD_from_mem;
            default:real_rD1=rD1;
        endcase
    end
end
    
endmodule