data/full_repos/permissive/441359809/test/main_test/common/lut_def.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/test/main_test/common/lut_def.v:5: Multiple top level modules\n                                                                                         : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                         : ... Top module \'LUT1\'\nmodule LUT1 #( parameter INIT = 2\'h0 ) (input i0, output out );\n       ^~~~\n                                                                                         : ... Top module \'LUT2\'\nmodule LUT2 #( parameter INIT = 4\'h0 ) ( input i0, i1, output out );\n       ^~~~\n                                                                                         : ... Top module \'LUT3\'\nmodule LUT3 #( parameter INIT = 8\'h0 ) ( input i0, i1, i2, output out );\n       ^~~~\n                                                                                         : ... Top module \'LUT4\'\nmodule LUT4 #( parameter INIT = 16\'h0 ) ( input i0, i1, i2, i3, output out );\n       ^~~~\n                                                                                         : ... Top module \'LUT5\'\nmodule LUT5 #( parameter INIT = 32\'h0 ) ( input i0, i1, i2, i3, i4, output out );\n       ^~~~\n                                                                                         : ... Top module \'LUT6\'\nmodule LUT6 #( parameter INIT = 64\'h0 ) ( input i0, i1, i2, i3, i4, i5, output out );\n       ^~~~\n                                                                                         : ... Top module \'LUT7\'\nmodule LUT7 #( parameter INIT = 128\'h0 ) ( input i0, i1, i2, i3, i4, i5, i6, output out );\n       ^~~~\n%Error: Exiting due to 1 warning(s)\n'
module LUT7 #( parameter INIT = 128'h0 ) ( input i0, i1, i2, i3, i4, i5, i6, output out );
 assign out = INIT[{i6, i5, i4, i3, i2, i1, i0}];
endmodule
module LUT7 #( parameter INIT = 128'h0 ) ( input i0, i1, i2, i3, i4, i5, i6, output out );

 assign out = INIT[{i6, i5, i4, i3, i2, i1, i0}];
endmodule