data/full_repos/permissive/484215530/verilog/rtl/user_proj_example.v
1: b'%Error: data/full_repos/permissive/484215530/verilog/rtl/user_proj_example.v:5: Unknown verilator comment: /*verilator -xinit: zeros*/\n/*verilator -xinit: zeros*/ \n^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/484215530/verilog/rtl/user_proj_example.v:105: Unknown verilator comment: /*verilator -xinit: zeros*/\n/*verilator -xinit: zeros*/ \n^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/484215530/verilog/rtl/user_proj_example.v:331: Unknown verilator comment: /*verilator -xinit: zeros*/\n/*verilator -xinit: zeros*/ \n^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/484215530/verilog/rtl/user_proj_example.v:373: Unknown verilator comment: /*verilator -xinit: zeros*/\n/*verilator -xinit: zeros*/ \n^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/484215530/verilog/rtl/user_proj_example.v:558: Unknown verilator comment: /*verilator -xinit: zeros*/\n/*verilator -xinit: zeros*/ \n^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/484215530/verilog/rtl/user_proj_example.v:596: Unknown verilator comment: /*verilator -xinit: zeros*/\n/*verilator -xinit: zeros*/ \n^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/484215530/verilog/rtl/user_proj_example.v:629: Unknown verilator comment: /*verilator -xinit: zeros*/\n/*verilator -xinit: zeros*/ \n^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/484215530/verilog/rtl/user_proj_example.v:662: Unknown verilator comment: /*verilator -xinit: zeros*/\n/*verilator -xinit: zeros*/ \n^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/484215530/verilog/rtl/user_proj_example.v:707: Unknown verilator comment: /*verilator -xinit: zeros*/\n/*verilator -xinit: zeros*/ \n^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/484215530/verilog/rtl/user_proj_example.v:749: Unknown verilator comment: /*verilator -xinit: zeros*/\n/*verilator -xinit: zeros*/ \n^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 10 error(s)\n'
module RegRst_0x9f365fdf6c8998a
(
  input  wire [   0:0] clk,
  input  wire [   1:0] in_,
  output reg  [   1:0] out,
  input  wire [   0:0] reset
);


  localparam reset_value = 0;













  always @ (posedge clk) begin
    if (reset) begin
      out <= reset_value;
    end
    else begin
      out <= in_;
    end
  end


endmodule
module RegRst_0x9f365fdf6c8998a
(
  input  wire [   0:0] clk,
  input  wire [   1:0] in_,
  output reg  [   1:0] out,
  input  wire [   0:0] reset
);



  localparam reset_value = 0;













  always @ (posedge clk) begin
    if (reset) begin
      out <= reset_value;
    end
    else begin
      out <= in_;
    end
  end


endmodule