data/full_repos/permissive/524208019/simple_gate/simple_gate.v
data/verilator_xmls/276a9df7-8310-47b7-85b0-15985c82f2f3.xml
module simple_gate(
  inout clk,
  input a,
  input b,
  output out
);

  assign out = a^b;

endmodule
module simple_gate(
  inout clk,
  input a,
  input b,
  output out
);


  assign out = a^b;

endmodule