data/full_repos/permissive/439731184/one_bit_adder_assign.v
1: b'%Error: data/full_repos/permissive/439731184/one_bit_adder_assign.v:11: Unsupported or unknown PLI call: $monitor\n    $monitor("%h\\t%b\\t%b\\t%b\\t%b", $time, a, b, sum, carry);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/439731184/one_bit_adder_assign.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #10 a = 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/439731184/one_bit_adder_assign.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #10 b = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/one_bit_adder_assign.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #10 a = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/one_bit_adder_assign.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #10 $finish;\n    ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module adder_assign(); 

reg a, b;
wire sum, carry;


assign #5 {carry, sum} = a + b;

initial begin 
    $display("time\ta\tb\tsum\tcarry");
    $monitor("%h\t%b\t%b\t%b\t%b", $time, a, b, sum, carry);
    a = 0;
    b = 0;
    #10 a = 1;
    #10 b = 1;
    #10 a = 0;
    #10 $finish;
end

endmodule
module adder_assign();
 

reg a, b;
wire sum, carry;


assign #5 {carry, sum} = a + b;

initial begin 
    $display("time\ta\tb\tsum\tcarry");
    $monitor("%h\t%b\t%b\t%b\t%b", $time, a, b, sum, carry);
    a = 0;
    b = 0;
    #10 a = 1;
    #10 b = 1;
    #10 a = 0;
    #10 $finish;
end

endmodule