data/full_repos/permissive/505761772/code/ModemCore.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/505761772/code/ModemCore.v:204: Multiple top level modules\n                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                            : ... Top module \'DEMODULATOR\'\nmodule DEMODULATOR  ( input             CLK,\n       ^~~~~~~~~~~\n                                                                            : ... Top module \'NCO\'\nmodule NCO( input CLK,\n       ^~~\n                                                                            : ... Top module \'DESERIALIZER\'\nmodule DESERIALIZER(  input CLK,\n       ^~~~~~~~~~~~\n                                                                            : ... Top module \'SERIALIZER\'\nmodule SERIALIZER(  input       CLK,\n       ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/505761772/code/ModemCore.v:34: Operator ASSIGNW expects 18 bits on the Assign RHS, but Assign RHS\'s SHIFTRS generates 36 bits.\n                                                                        : ... In instance DEMODULATOR.MULT8\nassign P = (P36>>>17);\n         ^\n%Error: data/full_repos/permissive/505761772/code/ModemCore.v:35: Cannot find file containing module: \'MULT18X18\'\nMULT18X18 mult ( .P(P36),\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/505761772/code,data/full_repos/permissive/505761772/MULT18X18\n             data/full_repos/permissive/505761772/code,data/full_repos/permissive/505761772/MULT18X18.v\n             data/full_repos/permissive/505761772/code,data/full_repos/permissive/505761772/MULT18X18.sv\n             MULT18X18\n             MULT18X18.v\n             MULT18X18.sv\n             obj_dir/MULT18X18\n             obj_dir/MULT18X18.v\n             obj_dir/MULT18X18.sv\n%Warning-WIDTH: data/full_repos/permissive/505761772/code/ModemCore.v:10: Operator ASSIGN expects 18 bits on the Assign RHS, but Assign RHS\'s CONST \'17\'h1d000\' generates 17 bits.\n                                                                        : ... In instance DEMODULATOR.Osc2\nreg signed [17:0] X = 17\'h1D000;\n                      ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/505761772/code/ModemCore.v:11: Operator ASSIGN expects 18 bits on the Assign RHS, but Assign RHS\'s CONST \'17\'h0\' generates 17 bits.\n                                                                        : ... In instance DEMODULATOR.Osc2\nreg signed [17:0] Y = 17\'h00000;\n                      ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/505761772/code/ModemCore.v:192: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                         : ... In instance DEMODULATOR\n    if(cnt == 4\'h1)\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/505761772/code/ModemCore.v:240: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s CONST \'17\'he800\' generates 17 bits.\n                                                                         : ... In instance NCO\n      X <= 17\'h0E800;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/505761772/code/ModemCore.v:241: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s CONST \'17\'h0\' generates 17 bits.\n                                                                         : ... In instance NCO\n      Y <= 17\'h00000;\n        ^~\n%Error: Exiting due to 1 error(s), 7 warning(s)\n'
module SERIALIZER(  input       CLK,
                    input [7:0] DATA,
                    output reg  DET,
                    input       EN,
                    output reg  DATA_out);

reg [4:0]  stateReg;
reg [7:0]  cnt;
reg [15:0] dataReg;
reg [3:0]  stuffedBit;
reg EN_old;

initial begin
  stateReg = 0;
  DET = 0;
  stuffedBit = 0;
end

always @(posedge CLK) begin
  if(stateReg == 0) begin
    if(EN & !EN_old) begin
      stateReg <= 5'h11;
      cnt <= 8'd102;
      stuffedBit <= 0;
      DET <= 1;

      dataReg <= {DATA[7:0], 8'h7E};
    end else begin
      DET <= 0;
    end
  end else begin
    if(cnt > 0) cnt <= cnt - 1;
    else begin
      cnt <= 8'd102;
      if((stuffedBit < 5) || (stateReg > 5'h8)) begin
        if(!dataReg[0]) begin
          DATA_out <= !DATA_out;
          stuffedBit <= 0;
        end else begin
          stuffedBit <= stuffedBit + 1;
        end

        dataReg <= {1'bX, dataReg[15:1]};
        stateReg <= stateReg - 1;
      end else begin
        DATA_out <= !DATA_out;
        stuffedBit <= 0;
      end
    end
  end

  EN_old <= EN;
end

endmodule
module SERIALIZER(  input       CLK,
                    input [7:0] DATA,
                    output reg  DET,
                    input       EN,
                    output reg  DATA_out);


reg [4:0]  stateReg;
reg [7:0]  cnt;
reg [15:0] dataReg;
reg [3:0]  stuffedBit;
reg EN_old;

initial begin
  stateReg = 0;
  DET = 0;
  stuffedBit = 0;
end

always @(posedge CLK) begin
  if(stateReg == 0) begin
    if(EN & !EN_old) begin
      stateReg <= 5'h11;
      cnt <= 8'd102;
      stuffedBit <= 0;
      DET <= 1;

      dataReg <= {DATA[7:0], 8'h7E};
    end else begin
      DET <= 0;
    end
  end else begin
    if(cnt > 0) cnt <= cnt - 1;
    else begin
      cnt <= 8'd102;
      if((stuffedBit < 5) || (stateReg > 5'h8)) begin
        if(!dataReg[0]) begin
          DATA_out <= !DATA_out;
          stuffedBit <= 0;
        end else begin
          stuffedBit <= stuffedBit + 1;
        end

        dataReg <= {1'bX, dataReg[15:1]};
        stateReg <= stateReg - 1;
      end else begin
        DATA_out <= !DATA_out;
        stuffedBit <= 0;
      end
    end
  end

  EN_old <= EN;
end

endmodule