data/full_repos/permissive/51854321/irig_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/51854321/irig_testbench.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #120 rst = 1\'b0;        \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/51854321/irig_testbench.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/51854321/irig_testbench.v:64: Unsupported: Ignoring delay on this delayed statement.\n      #50 clk_10mhz = ~clk_10mhz;\n      ^\n%Error: data/full_repos/permissive/51854321/irig_testbench.v:135: syntax error, unexpected \'@\'\n            @(posedge clk_10mhz);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/51854321/irig_testbench.v:140: Unsupported: Ignoring delay on this delayed statement.\n                    #2000500 irigb = 1\'b0;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/51854321/irig_testbench.v:141: Unsupported: Ignoring delay on this delayed statement.\n                    #7999500;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/51854321/irig_testbench.v:145: Unsupported: Ignoring delay on this delayed statement.\n                    #5000500 irigb = 1\'b0;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/51854321/irig_testbench.v:146: Unsupported: Ignoring delay on this delayed statement.\n                    #4999500;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/51854321/irig_testbench.v:150: Unsupported: Ignoring delay on this delayed statement.\n                    #8000500 irigb = 1\'b0;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/51854321/irig_testbench.v:151: Unsupported: Ignoring delay on this delayed statement.\n                    #2999500;\n                    ^\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module irig_testbench();
    
    localparam MARK = 3'b100;
    localparam D1 = 3'b010;
    localparam D0 = 3'b001;


    reg clk_10mhz;
    reg rst;
    reg irigb;
 

    wire pps;    
    wire [5:0] ts_second;
    wire [5:0] ts_minute;
    wire [4:0] ts_hour;
    wire [8:0] ts_day;
    wire [6:0] ts_year;
    wire [16:0] ts_sec_day;
    

    irig i1(.clk_10mhz(clk_10mhz),
            .rst(rst),
            .irigb(irigb),
            .pps(pps),
            .ts_second(ts_second),
            .ts_minute(ts_minute),
            .ts_hour(ts_hour),
            .ts_day(ts_day),
            .ts_year(ts_year),
            .ts_sec_day(ts_sec_day));
            

    initial begin
        clk_10mhz = 1'b0;
        irigb = 1'b0;
        rst = 1'b1;
        

        #120 rst = 1'b0;        
        #100;


        irig_bit(D0);
        irig_bit(MARK);
        irig_bit(D1);
        irig_bit(D0);


        irig_bit(MARK);


        irig_timestamp();


        irig_bit(MARK);

        $stop;
    end

    always
      #50 clk_10mhz = ~clk_10mhz;


    task irig_timestamp;        
        begin

            irig_bit(MARK);



            irig_bitstream(9'bx10000010);


            irig_bit(MARK);
            irig_bitstream(9'b010101001);
            

            irig_bit(MARK);
            irig_bitstream(9'b000100111);


            irig_bit(MARK);
            irig_bitstream(9'b100100011);



            irig_bit(MARK);
            irig_bitstream(9'b000000010);


            irig_bit(MARK);
            irig_bitstream(9'b000100110);


            irig_bit(MARK);
            irig_bitstream(9'b0);
            irig_bit(MARK);
            irig_bitstream(9'b0);



            irig_bit(MARK);
            irig_bitstream(9'b100001110);
            irig_bit(MARK);
            irig_bitstream(9'b001111110);
            irig_bit(MARK);
          end
    endtask



    task irig_bitstream;
        input [8:0] s;
        begin
        repeat (9) 
          begin
            case (s[0])
              1'b1:
                irig_bit(D0);
              1'b0:
                irig_bit(D1);
            endcase
            s = s >> 1'b1;
          end 
        end
    endtask
              

    task irig_bit;
        input [2:0] ib;
        begin
            @(posedge clk_10mhz);
            irigb = 1'b1;
            case (ib)
              D0: 
                begin
                    #2000500 irigb = 1'b0;
                    #7999500;
                end
              D1:
                begin
                    #5000500 irigb = 1'b0;
                    #4999500;
                end
              MARK:
                begin 
                    #8000500 irigb = 1'b0;
                    #2999500;
                end
            endcase            
        end
    endtask

endmodule
module irig_testbench();

    
    localparam MARK = 3'b100;
    localparam D1 = 3'b010;
    localparam D0 = 3'b001;


    reg clk_10mhz;
    reg rst;
    reg irigb;
 

    wire pps;    
    wire [5:0] ts_second;
    wire [5:0] ts_minute;
    wire [4:0] ts_hour;
    wire [8:0] ts_day;
    wire [6:0] ts_year;
    wire [16:0] ts_sec_day;
    

    irig i1(.clk_10mhz(clk_10mhz),
            .rst(rst),
            .irigb(irigb),
            .pps(pps),
            .ts_second(ts_second),
            .ts_minute(ts_minute),
            .ts_hour(ts_hour),
            .ts_day(ts_day),
            .ts_year(ts_year),
            .ts_sec_day(ts_sec_day));
            

    initial begin
        clk_10mhz = 1'b0;
        irigb = 1'b0;
        rst = 1'b1;
        

        #120 rst = 1'b0;        
        #100;


        irig_bit(D0);
        irig_bit(MARK);
        irig_bit(D1);
        irig_bit(D0);


        irig_bit(MARK);


        irig_timestamp();


        irig_bit(MARK);

        $stop;
    end

    always
      #50 clk_10mhz = ~clk_10mhz;


    task irig_timestamp;        
        begin

            irig_bit(MARK);



            irig_bitstream(9'bx10000010);


            irig_bit(MARK);
            irig_bitstream(9'b010101001);
            

            irig_bit(MARK);
            irig_bitstream(9'b000100111);


            irig_bit(MARK);
            irig_bitstream(9'b100100011);



            irig_bit(MARK);
            irig_bitstream(9'b000000010);


            irig_bit(MARK);
            irig_bitstream(9'b000100110);


            irig_bit(MARK);
            irig_bitstream(9'b0);
            irig_bit(MARK);
            irig_bitstream(9'b0);



            irig_bit(MARK);
            irig_bitstream(9'b100001110);
            irig_bit(MARK);
            irig_bitstream(9'b001111110);
            irig_bit(MARK);
          end
    endtask



    task irig_bitstream;
        input [8:0] s;
        begin
        repeat (9) 
          begin
            case (s[0])
              1'b1:
                irig_bit(D0);
              1'b0:
                irig_bit(D1);
            endcase
            s = s >> 1'b1;
          end 
        end
    endtask
              

    task irig_bit;
        input [2:0] ib;
        begin
            @(posedge clk_10mhz);
            irigb = 1'b1;
            case (ib)
              D0: 
                begin
                    #2000500 irigb = 1'b0;
                    #7999500;
                end
              D1:
                begin
                    #5000500 irigb = 1'b0;
                    #4999500;
                end
              MARK:
                begin 
                    #8000500 irigb = 1'b0;
                    #2999500;
                end
            endcase            
        end
    endtask

endmodule