data/full_repos/permissive/458737381/src/verilog-parser/tests/efc_saed.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/efc_saed.v:28: Cannot find include file: sys.h\n`include "sys.h" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/efc_saed.v:29: Cannot find include file: iop.h\n`include "iop.h" \n         ^~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module efc_saed (

   rise_det, fall_det, 

   async_in, clk
   );





output   rise_det;
output   fall_det;
input   async_in;
input   clk;







wire		snc1_ff;
wire		snc2_ff;
wire		hist_ff;




bw_u1_syncff_4x snc1_reg(
					.so(),
					.q (snc1_ff),
					.ck (clk),
					.d (async_in),
					.sd(),
					.se(1'b0));
dff_ns #(1) snc2_reg (.din(snc1_ff), .q(snc2_ff), .clk(clk));

dff_ns #(1) hist_reg (.din(snc2_ff), .q(hist_ff), .clk(clk));

assign rise_det = !hist_ff && snc2_ff;
assign fall_det = hist_ff && !snc2_ff;

endmodule
module efc_saed (

   rise_det, fall_det, 

   async_in, clk
   );






output   rise_det;
output   fall_det;
input   async_in;
input   clk;







wire		snc1_ff;
wire		snc2_ff;
wire		hist_ff;




bw_u1_syncff_4x snc1_reg(
					.so(),
					.q (snc1_ff),
					.ck (clk),
					.d (async_in),
					.sd(),
					.se(1'b0));
dff_ns #(1) snc2_reg (.din(snc1_ff), .q(snc2_ff), .clk(clk));

dff_ns #(1) hist_reg (.din(snc2_ff), .q(hist_ff), .clk(clk));

assign rise_det = !hist_ff && snc2_ff;
assign fall_det = hist_ff && !snc2_ff;

endmodule