data/full_repos/permissive/472499258/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/472499258/verilog/rtl/user_proj_example.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472499258/verilog/rtl/user_proj_example.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472499258/verilog/rtl/user_proj_example.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472499258/verilog/rtl/user_proj_example.v:74: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_in;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472499258/verilog/rtl/user_proj_example.v:75: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_out;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472499258/verilog/rtl/user_proj_example.v:76: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_oeb;\n          ^~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n"
module user_proj_example #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,


    output [2:0] irq
);
    wire clk;
    wire rst;

    wire [`MPRJ_IO_PADS-1:0] io_in;
    wire [`MPRJ_IO_PADS-1:0] io_out;
    wire [`MPRJ_IO_PADS-1:0] io_oeb;

    


    assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
    assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;




    wire [31:0] data_out;
    wire select;

    assign select = la_data_in[112];
    assign data_out = select ? la_data_in[63:32] : prng_out;

    hyperram hyperram(
        .clk(clk),
        .rst(rst),


	.address(la_data_in[31:0]),

	.data_out(data_out),
	.data_in(la_data_out[31:0]),
	.write_enable(la_data_in[66]),
	.write_mask(la_data_in[70:67]),
	.transaction_begin(la_data_in[71]),
	.transaction_end(la_data_out[32]),


	.dq_in(io_in[15:8]),
	.dq_out(io_out[15:8]),
	.dq_oeb(io_oeb[15:8]),
	.ck(io_out[16]),
	.ck_bar(io_out[17]),
	.cs_bar(io_out[18]),
	.rwds_in(io_in[19]),
	.rwds_out(io_out[19]),
	.rwds_oeb(io_oeb[19]),


	.timed_read(la_data_in[72]),
	.WAIT_LATENCY(la_data_in[78:73]),
	.DONE_LATENCY(la_data_in[84:79]),


	.control_state(la_data_out[102:96])
    );


    wire [31:0] prng_out;
    assign prng_out[31:12] = 0;

    acorn_prng acorn_prng(
	.clk(clk),
        .reset(rst),
         
        .load(la_data_in[85]),
        .select(la_data_in[87:86]),
        .gpio_seed(la_data_in[99:88]),
        .LA1_seed(la_data_in[111:100]),
        .out(prng_out[11:0]),
        .io_oeb(la_data_out[115:103]),
        .reset_out(la_data_out[116])
    );
endmodule
module user_proj_example #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,


    output [2:0] irq
);

    wire clk;
    wire rst;

    wire [`MPRJ_IO_PADS-1:0] io_in;
    wire [`MPRJ_IO_PADS-1:0] io_out;
    wire [`MPRJ_IO_PADS-1:0] io_oeb;

    


    assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
    assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;




    wire [31:0] data_out;
    wire select;

    assign select = la_data_in[112];
    assign data_out = select ? la_data_in[63:32] : prng_out;

    hyperram hyperram(
        .clk(clk),
        .rst(rst),


	.address(la_data_in[31:0]),

	.data_out(data_out),
	.data_in(la_data_out[31:0]),
	.write_enable(la_data_in[66]),
	.write_mask(la_data_in[70:67]),
	.transaction_begin(la_data_in[71]),
	.transaction_end(la_data_out[32]),


	.dq_in(io_in[15:8]),
	.dq_out(io_out[15:8]),
	.dq_oeb(io_oeb[15:8]),
	.ck(io_out[16]),
	.ck_bar(io_out[17]),
	.cs_bar(io_out[18]),
	.rwds_in(io_in[19]),
	.rwds_out(io_out[19]),
	.rwds_oeb(io_oeb[19]),


	.timed_read(la_data_in[72]),
	.WAIT_LATENCY(la_data_in[78:73]),
	.DONE_LATENCY(la_data_in[84:79]),


	.control_state(la_data_out[102:96])
    );


    wire [31:0] prng_out;
    assign prng_out[31:12] = 0;

    acorn_prng acorn_prng(
	.clk(clk),
        .reset(rst),
         
        .load(la_data_in[85]),
        .select(la_data_in[87:86]),
        .gpio_seed(la_data_in[99:88]),
        .LA1_seed(la_data_in[111:100]),
        .out(prng_out[11:0]),
        .io_oeb(la_data_out[115:103]),
        .reset_out(la_data_out[116])
    );
endmodule