data/full_repos/permissive/463395574/regfile.v
1: b'%Error: data/full_repos/permissive/463395574/regfile.v:6: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v.v\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/463395574/regfile.v:10: Define or directive not defined: \'`REG_IDX_WIDTH\'\n    input  [`REG_IDX_WIDTH-1:0] readAddr1, readAddr2,\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/regfile.v:11: Define or directive not defined: \'`WORD_LEN\'\n    output [`WORD_LEN-1:0]      readData1, readData2,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/regfile.v:14: Define or directive not defined: \'`REG_IDX_WIDTH\'\n    input  [`REG_IDX_WIDTH-1:0] writeAddr,\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/regfile.v:15: Define or directive not defined: \'`WORD_LEN\'\n    input  [`WORD_LEN-1:0]      writeData\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/regfile.v:22: Define or directive not defined: \'`WORD_LEN\'\n    reg [`WORD_LEN-1:0] registerFile[`REG_COUNT-1:0];\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/regfile.v:22: Define or directive not defined: \'`REG_COUNT\'\n    reg [`WORD_LEN-1:0] registerFile[`REG_COUNT-1:0];\n                                     ^~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n'
module RegFile(
    input                      	clk,
    input  [`REG_IDX_WIDTH-1:0] readAddr1, readAddr2,
    output [`WORD_LEN-1:0]      readData1, readData2,

    input                      	writeEnable,
    input  [`REG_IDX_WIDTH-1:0] writeAddr,
    input  [`WORD_LEN-1:0]      writeData
`ifdef FPGA
    ,input [`REG_IDX_WIDTH-1:0] readAddr3,
    output [`WORD_LEN-1:0]      readData3
`endif
);

    reg [`WORD_LEN-1:0] registerFile[`REG_COUNT-1:0];

    always @(negedge clk)
        if (writeEnable && writeAddr != 0)
        begin
            registerFile[writeAddr] <= writeData;
            `ifdef DEBUG
            $display("x%d = %h", writeAddr, writeData);
            `endif
        end

    assign readData1 = (readAddr1 != 0) ? registerFile[readAddr1] : 0;
    assign readData2 = (readAddr2 != 0) ? registerFile[readAddr2] : 0;
`ifdef FPGA
    assign readData3 = (readAddr3 != 0) ? registerFile[readAddr3] : 0;
`endif
endmodule
module RegFile(
    input                      	clk,
    input  [`REG_IDX_WIDTH-1:0] readAddr1, readAddr2,
    output [`WORD_LEN-1:0]      readData1, readData2,

    input                      	writeEnable,
    input  [`REG_IDX_WIDTH-1:0] writeAddr,
    input  [`WORD_LEN-1:0]      writeData
`ifdef FPGA
    ,input [`REG_IDX_WIDTH-1:0] readAddr3,
    output [`WORD_LEN-1:0]      readData3
`endif
);


    reg [`WORD_LEN-1:0] registerFile[`REG_COUNT-1:0];

    always @(negedge clk)
        if (writeEnable && writeAddr != 0)
        begin
            registerFile[writeAddr] <= writeData;
            `ifdef DEBUG
            $display("x%d = %h", writeAddr, writeData);
            `endif
        end

    assign readData1 = (readAddr1 != 0) ? registerFile[readAddr1] : 0;
    assign readData2 = (readAddr2 != 0) ? registerFile[readAddr2] : 0;
`ifdef FPGA
    assign readData3 = (readAddr3 != 0) ? registerFile[readAddr3] : 0;
`endif
endmodule