data/full_repos/permissive/40581558/fpga_sim/model_rec/transmit_test_entity.v
1: b"%Error: data/full_repos/permissive/40581558/fpga_sim/model_rec/transmit_test_entity.v:62: Cannot find file containing module: 'transmit_test_model'\n transmit_test_model    transmit_test_model  (\n ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/40581558/fpga_sim/model_rec,data/full_repos/permissive/40581558/transmit_test_model\n             data/full_repos/permissive/40581558/fpga_sim/model_rec,data/full_repos/permissive/40581558/transmit_test_model.v\n             data/full_repos/permissive/40581558/fpga_sim/model_rec,data/full_repos/permissive/40581558/transmit_test_model.sv\n             transmit_test_model\n             transmit_test_model.v\n             transmit_test_model.sv\n             obj_dir/transmit_test_model\n             obj_dir/transmit_test_model.v\n             obj_dir/transmit_test_model.sv\n%Error: data/full_repos/permissive/40581558/fpga_sim/model_rec/transmit_test_entity.v:86: Cannot find file containing module: 'Transmit'\n    Transmit     Transmit_module  (\n    ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module  transmit_test_entity   (

             input        clk_in  ,

             input        reset_n ,

              
         
	output            Sample_Gate,
	output    [15:0]  P,
	output    [15:0]  N,
	
	output            HV_SW_CLR,
	output            HV_SW_LE,
	output            HV_SW_CLK,
	output            HV_SW_DOUT,
	
	output     [3:0]  AX,
	output     [2:0]  AY,
	output            MT_CS,
	output            MT_Strobe,
	output            MT_Data   

      ) ;






  wire        [7:0]      Line_Num  ;

  wire        [1:0]      Focus_Num ;

  wire                   Pr_Gate  ;

  wire                   RX_Gate  ;

  wire                   End_Gate ;

  wire                   Envelop  ;

  
















 transmit_test_model    transmit_test_model  (

              .clk_100M  (clk_in) ,
      
              .reset_n   (reset_n)  ,

              .Line_Num  (Line_Num) ,

              .Focus_Num (Focus_Num),
       
              .Pr_Gate   (Pr_Gate)  ,
     
              .RX_Gate   (RX_Gate) ,
      
              .End_Gate  (End_Gate),
      
              .Envelop   (Envelop) 

  );





    Transmit     Transmit_module  (
    

           .Transmit_CLK  (clk_in) ,
	   .Line_Num      (Line_Num) ,
	   .Focus_Num     (Focus_Num),
	   .Pr_Gate       (Pr_Gate)  ,
	   .RX_Gate       (RX_Gate) ,

           .Sample_Gate   (Sample_Gate),
	   .P             (P),
	   .N             (N),
	   .HV_SW_CLR     (HV_SW_CLR),
	   .HV_SW_LE      (HV_SW_LE),
	   .HV_SW_CLK     (HV_SW_CLK),
	   .HV_SW_DOUT    (HV_SW_DOUT),
	
	   .AX            (AX),
	   .AY            (AY),
	   .MT_CS         (MT_CS),
	   .MT_Strobe     (MT_Strobe),
	   .MT_Data       (MT_Data)
    );









   endmodule
module  transmit_test_entity   (

             input        clk_in  ,

             input        reset_n ,

              
         
	output            Sample_Gate,
	output    [15:0]  P,
	output    [15:0]  N,
	
	output            HV_SW_CLR,
	output            HV_SW_LE,
	output            HV_SW_CLK,
	output            HV_SW_DOUT,
	
	output     [3:0]  AX,
	output     [2:0]  AY,
	output            MT_CS,
	output            MT_Strobe,
	output            MT_Data   

      ) ;







  wire        [7:0]      Line_Num  ;

  wire        [1:0]      Focus_Num ;

  wire                   Pr_Gate  ;

  wire                   RX_Gate  ;

  wire                   End_Gate ;

  wire                   Envelop  ;

  
















 transmit_test_model    transmit_test_model  (

              .clk_100M  (clk_in) ,
      
              .reset_n   (reset_n)  ,

              .Line_Num  (Line_Num) ,

              .Focus_Num (Focus_Num),
       
              .Pr_Gate   (Pr_Gate)  ,
     
              .RX_Gate   (RX_Gate) ,
      
              .End_Gate  (End_Gate),
      
              .Envelop   (Envelop) 

  );





    Transmit     Transmit_module  (
    

           .Transmit_CLK  (clk_in) ,
	   .Line_Num      (Line_Num) ,
	   .Focus_Num     (Focus_Num),
	   .Pr_Gate       (Pr_Gate)  ,
	   .RX_Gate       (RX_Gate) ,

           .Sample_Gate   (Sample_Gate),
	   .P             (P),
	   .N             (N),
	   .HV_SW_CLR     (HV_SW_CLR),
	   .HV_SW_LE      (HV_SW_LE),
	   .HV_SW_CLK     (HV_SW_CLK),
	   .HV_SW_DOUT    (HV_SW_DOUT),
	
	   .AX            (AX),
	   .AY            (AY),
	   .MT_CS         (MT_CS),
	   .MT_Strobe     (MT_Strobe),
	   .MT_Data       (MT_Data)
    );









   endmodule