data/full_repos/permissive/451853158/MIPS_Pipeline_Processor/mips_pipeline_processor_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/451853158/MIPS_Pipeline_Processor/mips_pipeline_processor_tb.v:8: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = !clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/451853158/MIPS_Pipeline_Processor/mips_pipeline_processor_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n #2 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/451853158/MIPS_Pipeline_Processor/mips_pipeline_processor_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #6 reset = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451853158/MIPS_Pipeline_Processor/mips_pipeline_processor_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n #3000 $stop;\n ^\n%Error: data/full_repos/permissive/451853158/MIPS_Pipeline_Processor/mips_pipeline_processor_tb.v:6: Cannot find file containing module: \'mips_pipeline_processor\'\nmips_pipeline_processor mips (.clk(clk), .reset(reset));\n^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/451853158/MIPS_Pipeline_Processor,data/full_repos/permissive/451853158/mips_pipeline_processor\n             data/full_repos/permissive/451853158/MIPS_Pipeline_Processor,data/full_repos/permissive/451853158/mips_pipeline_processor.v\n             data/full_repos/permissive/451853158/MIPS_Pipeline_Processor,data/full_repos/permissive/451853158/mips_pipeline_processor.sv\n             mips_pipeline_processor\n             mips_pipeline_processor.v\n             mips_pipeline_processor.sv\n             obj_dir/mips_pipeline_processor\n             obj_dir/mips_pipeline_processor.v\n             obj_dir/mips_pipeline_processor.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mips_pipeline_processor_tb ();


reg clk, reset;

mips_pipeline_processor mips (.clk(clk), .reset(reset));

always #5 clk = !clk;

initial begin
	clk = 0;
	reset = 1;
	
	#2 reset = 0;
  #6 reset = 1;

	#3000 $stop;

end

endmodule
module mips_pipeline_processor_tb ();



reg clk, reset;

mips_pipeline_processor mips (.clk(clk), .reset(reset));

always #5 clk = !clk;

initial begin
	clk = 0;
	reset = 1;
	
	#2 reset = 0;
  #6 reset = 1;

	#3000 $stop;

end

endmodule