data/full_repos/permissive/423539813/source_files/address_gen.v
data/verilator_xmls/a12517b8-982e-4335-b6e6-43557e97a9f6.xml
module address_gen (output reg [31:0] pc, input [31:0] PCNext,input clk,rst); 

 

 
 always@(posedge clk)
    begin
	if (rst)
		pc =0;
	else
	   pc = PCNext;
	
    end
endmodule
module address_gen (output reg [31:0] pc, input [31:0] PCNext,input clk,rst);
 

 

 
 always@(posedge clk)
    begin
	if (rst)
		pc =0;
	else
	   pc = PCNext;
	
    end
endmodule