data/full_repos/permissive/461141714/src/Single Cycle CPU/RF.v
1: b'%Error: Cannot find file containing module: Cycle\n        ... Looked in:\n             data/full_repos/permissive/461141714/src/Single/Cycle\n             data/full_repos/permissive/461141714/src/Single/Cycle.v\n             data/full_repos/permissive/461141714/src/Single/Cycle.sv\n             Cycle\n             Cycle.v\n             Cycle.sv\n             obj_dir/Cycle\n             obj_dir/Cycle.v\n             obj_dir/Cycle.sv\n%Error: Cannot find file containing module: CPU,data/full_repos/permissive/461141714\n%Error: Cannot find file containing module: data/full_repos/permissive/461141714/src/Single\n%Error: Cannot find file containing module: CPU/RF.v\n%Error: Exiting due to 4 error(s)\n'
module RF(
    input write,
    input clk,
    input reset_n,
    input [1:0] addr1,
    input [1:0] addr2,
    input [1:0] addr3,
    output reg [15:0] data1,
    output reg [15:0] data2,
    input [15:0] data3
    );
    
    integer i;

    reg [15:0] memory [3:0];
    
    initial begin
        for(i=0; i<4; i=i+1) begin
            memory[i] = 16'b0;
        end
    end
    
    always @(reset_n) begin
        if(reset_n == 0) begin
            for(i=0; i<4; i=i+1) begin
                memory[i] = i;
            end
        end
    end
    
    always @(*) begin
        data1 = memory[addr1];
        data2 = memory[addr2];
    end
    
    always @(posedge clk) begin
        if(write == 1) begin
            memory[addr3] = data3;
        end
    end
endmodule
module RF(
    input write,
    input clk,
    input reset_n,
    input [1:0] addr1,
    input [1:0] addr2,
    input [1:0] addr3,
    output reg [15:0] data1,
    output reg [15:0] data2,
    input [15:0] data3
    );

    
    integer i;

    reg [15:0] memory [3:0];
    
    initial begin
        for(i=0; i<4; i=i+1) begin
            memory[i] = 16'b0;
        end
    end
    
    always @(reset_n) begin
        if(reset_n == 0) begin
            for(i=0; i<4; i=i+1) begin
                memory[i] = i;
            end
        end
    end
    
    always @(*) begin
        data1 = memory[addr1];
        data2 = memory[addr2];
    end
    
    always @(posedge clk) begin
        if(write == 1) begin
            memory[addr3] = data3;
        end
    end
endmodule