data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_serial_host.v
1: b'%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_serial_host.v:32: Cannot find include file: sd_defines.h\n`include "sd_defines.h" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc,data/full_repos/permissive/489980666/sd_defines.h\n             data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc,data/full_repos/permissive/489980666/sd_defines.h.v\n             data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc,data/full_repos/permissive/489980666/sd_defines.h.sv\n             sd_defines.h\n             sd_defines.h.v\n             sd_defines.h.sv\n             obj_dir/sd_defines.h\n             obj_dir/sd_defines.h.v\n             obj_dir/sd_defines.h.sv\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_serial_host.v:50: Define or directive not defined: \'`BLKSIZE_W\'\n    input [`BLKSIZE_W-1:0] blksize,\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_serial_host.v:52: Define or directive not defined: \'`BLKCNT_W\'\n    input [`BLKCNT_W-1:0] blkcnt,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_serial_host.v:65: Define or directive not defined: \'`BLKSIZE_W\'\nreg [`BLKSIZE_W+4-1:0] data_cycles;\n     ^~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_serial_host.v:66: Define or directive not defined: \'`BLKSIZE_W\'\nreg [`BLKSIZE_W+4-1:0] transf_cnt;\n     ^~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_data_serial_host.v:69: Define or directive not defined: \'`BLKCNT_W\'\nreg [`BLKCNT_W-1:0] blkcnt_reg;\n     ^~~~~~~~~\n%Error: Exiting due to 6 error(s)\n'
module sd_crc_16(
    input        BITVAL,
    input        ENABLE,
    input        BITSTRB,
    input        CLEAR,
    output reg [15:0] CRC
);

assign inv = BITVAL ^ CRC[15];

always @(posedge BITSTRB) begin
    if (CLEAR) begin
        CRC <= 0;
    end else if (ENABLE == 1) begin
        CRC[15] <= CRC[14];
        CRC[14] <= CRC[13];
        CRC[13] <= CRC[12];
        CRC[12] <= CRC[11] ^ inv;
        CRC[11] <= CRC[10];
        CRC[10] <= CRC[9];
        CRC[9] <= CRC[8];
        CRC[8] <= CRC[7];
        CRC[7] <= CRC[6];
        CRC[6] <= CRC[5];
        CRC[5] <= CRC[4] ^ inv;
        CRC[4] <= CRC[3];
        CRC[3] <= CRC[2];
        CRC[2] <= CRC[1];
        CRC[1] <= CRC[0];
        CRC[0] <= inv;
    end
end

endmodule
module sd_crc_16(
    input        BITVAL,
    input        ENABLE,
    input        BITSTRB,
    input        CLEAR,
    output reg [15:0] CRC
);


assign inv = BITVAL ^ CRC[15];

always @(posedge BITSTRB) begin
    if (CLEAR) begin
        CRC <= 0;
    end else if (ENABLE == 1) begin
        CRC[15] <= CRC[14];
        CRC[14] <= CRC[13];
        CRC[13] <= CRC[12];
        CRC[12] <= CRC[11] ^ inv;
        CRC[11] <= CRC[10];
        CRC[10] <= CRC[9];
        CRC[9] <= CRC[8];
        CRC[8] <= CRC[7];
        CRC[7] <= CRC[6];
        CRC[6] <= CRC[5];
        CRC[5] <= CRC[4] ^ inv;
        CRC[4] <= CRC[3];
        CRC[3] <= CRC[2];
        CRC[2] <= CRC[1];
        CRC[1] <= CRC[0];
        CRC[0] <= inv;
    end
end

endmodule