data/full_repos/permissive/465389471/TLC_topModule_labsland.v
1: b'%Warning-WIDTH: data/full_repos/permissive/465389471/TLC_topModule_labsland.v:60: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'an\' generates 4 bits.\n                                                                                : ... In instance TLC_topModule_labsland\n    assign LEDG[0] = an;\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/465389471/TLC_topModule_labsland.v:67: Cannot find file containing module: \'TwelveHourBCDclock\'\nTwelveHourBCDclock BCD_clk(\n^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/465389471,data/full_repos/permissive/465389471/TwelveHourBCDclock\n             data/full_repos/permissive/465389471,data/full_repos/permissive/465389471/TwelveHourBCDclock.v\n             data/full_repos/permissive/465389471,data/full_repos/permissive/465389471/TwelveHourBCDclock.sv\n             TwelveHourBCDclock\n             TwelveHourBCDclock.v\n             TwelveHourBCDclock.sv\n             obj_dir/TwelveHourBCDclock\n             obj_dir/TwelveHourBCDclock.v\n             obj_dir/TwelveHourBCDclock.sv\n%Error: data/full_repos/permissive/465389471/TLC_topModule_labsland.v:77: Cannot find file containing module: \'peak_offpeak\'\npeak_offpeak BCD_peak(\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/465389471/TLC_topModule_labsland.v:83: Cannot find file containing module: \'TLC_main\'\nTLC_main Tlc_1(\n^~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module sevenseg_driver1(clk,clr,in5,in6,seg7,seg8);
  input clk;
  input clr;
  input [3:0] in5, in6;
wire [7:0] timer;

  output [6:0] seg7;
  output [6:0] seg8;

  decoder_7seg disp7(in5,seg7);
  decoder_7seg disp8(in6,seg8);
  

  
  
endmodule
module sevenseg_driver1(clk,clr,in5,in6,seg7,seg8);

  input clk;
  input clr;
  input [3:0] in5, in6;
wire [7:0] timer;

  output [6:0] seg7;
  output [6:0] seg8;

  decoder_7seg disp7(in5,seg7);
  decoder_7seg disp8(in6,seg8);
  

  
  
endmodule