data/full_repos/permissive/481885440/verification/digital_filter/decimator_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/481885440/verification/digital_filter/decimator_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n    always #10 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/481885440/verification/digital_filter/decimator_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/481885440/verification/digital_filter/decimator_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #20 data_in <= data_in + 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/481885440/verification/digital_filter/decimator_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n            #20 count <= count + 1; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/481885440/verification/digital_filter/decimator_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n            #20 count <= count + 1;\n            ^\n%Error: data/full_repos/permissive/481885440/verification/digital_filter/decimator_tb.v:46: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("dump.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/481885440/verification/digital_filter/decimator_tb.v:47: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, decimator_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/481885440/verification/digital_filter/decimator_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #800000\n        ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module decimator_tb;

    reg clk;
    reg rst_n;
    reg unsigned [11:0] data_in;
    wire unsigned [11:0] data_out;
    wire new_data;

    decimator dut (
        .clk(clk),
        .rst_n(rst_n),
        .data_in(data_in),
        .data_out(data_out),
        .new_data(new_data)
    );

    always #10 clk = ~clk;

    initial begin
        clk <= 0;
        rst_n <= 0;
        data_in <= 12'd0;

        #20

        rst_n <= 1;
    end

    always begin
        #20 data_in <= data_in + 1;
    end
    
    integer count = 0;
    initial begin
        while(count < 512) begin
            #20 count <= count + 1; 
        end
        $display("Expected: %d, Actual: %d", count, data_out);
        while(count < 2*512) begin
            #20 count <= count + 1;
        end
        $display("Expected: %d, Actual: %d", count, data_out);
    end

    initial begin
        $dumpfile("dump.vcd");
        $dumpvars(0, decimator_tb);
        #800000
        $finish(2);
    end

endmodule
module decimator_tb;


    reg clk;
    reg rst_n;
    reg unsigned [11:0] data_in;
    wire unsigned [11:0] data_out;
    wire new_data;

    decimator dut (
        .clk(clk),
        .rst_n(rst_n),
        .data_in(data_in),
        .data_out(data_out),
        .new_data(new_data)
    );

    always #10 clk = ~clk;

    initial begin
        clk <= 0;
        rst_n <= 0;
        data_in <= 12'd0;

        #20

        rst_n <= 1;
    end

    always begin
        #20 data_in <= data_in + 1;
    end
    
    integer count = 0;
    initial begin
        while(count < 512) begin
            #20 count <= count + 1; 
        end
        $display("Expected: %d, Actual: %d", count, data_out);
        while(count < 2*512) begin
            #20 count <= count + 1;
        end
        $display("Expected: %d, Actual: %d", count, data_out);
    end

    initial begin
        $dumpfile("dump.vcd");
        $dumpvars(0, decimator_tb);
        #800000
        $finish(2);
    end

endmodule