data/full_repos/permissive/406635962/src/rtl/exu_wbck.v
1: b'%Error: data/full_repos/permissive/406635962/src/rtl/exu_wbck.v:7: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_wbck.v:13: Define or directive not defined: \'`XLEN\'\n    input [`XLEN-1:0] alu_wbck_i_data,\n           ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_wbck.v:14: Define or directive not defined: \'`RFIDX_WIDTH\'\n    input [`RFIDX_WIDTH-1:0] alu_wbck_i_rdidx,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_wbck.v:19: Define or directive not defined: \'`XLEN\'\n    input [`XLEN-1:0] longp_wbck_i_data,\n           ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_wbck.v:20: Define or directive not defined: \'`RFIDX_WIDTH\'\n    input [`RFIDX_WIDTH-1:0] longp_wbck_i_rdidx,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_wbck.v:23: Define or directive not defined: \'`XLEN\'\n    output [`XLEN-1:0] rf_wbck_o_data,\n            ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_wbck.v:24: Define or directive not defined: \'`RFIDX_WIDTH\'\n    output [`RFIDX_WIDTH-1:0] rf_wbck_o_rdidx\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_wbck.v:36: Define or directive not defined: \'`XLEN\'\n    wire [`XLEN-1:0] wbck_i_data;\n          ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_wbck.v:37: Define or directive not defined: \'`RFIDX_WIDTH\'\n    wire [`RFIDX_WIDTH-1:0] wbck_i_rdidx;\n          ^~~~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n'
module exu_wbck (

    input alu_wbck_i_valid, 
    output alu_wbck_i_ready,
    input [`XLEN-1:0] alu_wbck_i_data,
    input [`RFIDX_WIDTH-1:0] alu_wbck_i_rdidx,


    input longp_wbck_i_valid,
    output longp_wbck_i_ready,
    input [`XLEN-1:0] longp_wbck_i_data,
    input [`RFIDX_WIDTH-1:0] longp_wbck_i_rdidx,

    output rf_wbck_o_ena,
    output [`XLEN-1:0] rf_wbck_o_data,
    output [`RFIDX_WIDTH-1:0] rf_wbck_o_rdidx
);

    wire wbck_ready4alu = (~longp_wbck_i_valid);
    wire wbck_sel_alu = alu_wbck_i_valid & wbck_ready4alu;

    wire wbck_ready4longp = 1'b1;
    wire wbck_sel_longp = longp_wbck_i_valid & wbck_ready4longp;


    wire wbck_i_ready;
    wire wbck_i_valid;
    wire [`XLEN-1:0] wbck_i_data;
    wire [`RFIDX_WIDTH-1:0] wbck_i_rdidx;

    assign alu_wbck_i_ready = wbck_i_ready & wbck_ready4alu;
    assign longp_wbck_i_ready = wbck_i_ready & wbck_ready4longp;

    assign wbck_i_valid = wbck_sel_alu? alu_wbck_i_valid : longp_wbck_i_valid;
    assign wbck_i_data = wbck_sel_alu? alu_wbck_i_data : longp_wbck_i_data;
    assign wbck_i_rdidx = wbck_sel_alu? alu_wbck_i_rdidx : longp_wbck_i_rdidx;

    wire rf_wbck_o_ready;
    assign rf_wbck_o_ready = 1'b1;
    assign wbck_i_ready = rf_wbck_o_ready;
    wire rf_wbck_o_valid = wbck_i_valid;
    assign rf_wbck_o_ena = rf_wbck_o_valid & rf_wbck_o_ready;
    assign rf_wbck_o_rdidx = wbck_i_rdidx;
    assign rf_wbck_o_data = wbck_i_data;
    
endmodule
module exu_wbck (

    input alu_wbck_i_valid, 
    output alu_wbck_i_ready,
    input [`XLEN-1:0] alu_wbck_i_data,
    input [`RFIDX_WIDTH-1:0] alu_wbck_i_rdidx,


    input longp_wbck_i_valid,
    output longp_wbck_i_ready,
    input [`XLEN-1:0] longp_wbck_i_data,
    input [`RFIDX_WIDTH-1:0] longp_wbck_i_rdidx,

    output rf_wbck_o_ena,
    output [`XLEN-1:0] rf_wbck_o_data,
    output [`RFIDX_WIDTH-1:0] rf_wbck_o_rdidx
);


    wire wbck_ready4alu = (~longp_wbck_i_valid);
    wire wbck_sel_alu = alu_wbck_i_valid & wbck_ready4alu;

    wire wbck_ready4longp = 1'b1;
    wire wbck_sel_longp = longp_wbck_i_valid & wbck_ready4longp;


    wire wbck_i_ready;
    wire wbck_i_valid;
    wire [`XLEN-1:0] wbck_i_data;
    wire [`RFIDX_WIDTH-1:0] wbck_i_rdidx;

    assign alu_wbck_i_ready = wbck_i_ready & wbck_ready4alu;
    assign longp_wbck_i_ready = wbck_i_ready & wbck_ready4longp;

    assign wbck_i_valid = wbck_sel_alu? alu_wbck_i_valid : longp_wbck_i_valid;
    assign wbck_i_data = wbck_sel_alu? alu_wbck_i_data : longp_wbck_i_data;
    assign wbck_i_rdidx = wbck_sel_alu? alu_wbck_i_rdidx : longp_wbck_i_rdidx;

    wire rf_wbck_o_ready;
    assign rf_wbck_o_ready = 1'b1;
    assign wbck_i_ready = rf_wbck_o_ready;
    wire rf_wbck_o_valid = wbck_i_valid;
    assign rf_wbck_o_ena = rf_wbck_o_valid & rf_wbck_o_ready;
    assign rf_wbck_o_rdidx = wbck_i_rdidx;
    assign rf_wbck_o_data = wbck_i_data;
    
endmodule