data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv
1: b"%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:1: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport rv32i_types::*;\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:21: syntax error, unexpected ::, expecting ')'\nfunction void loadRegfile(regfilemux::regfilemux_sel_t sel);\n                                    ^~\n                                                                      : ... Perhaps 'regfilemux' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:22: syntax error, unexpected '=', expecting IDENTIFIER\n    ctrl_word.load_regfile = 1'b1; \n                           ^\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:23: syntax error, unexpected '=', expecting IDENTIFIER\n    ctrl_word.regfilemux_sel = sel;\n                             ^\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:28: syntax error, unexpected '=', expecting IDENTIFIER\n        ctrl_word.aluop = op;\n                        ^\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:29: syntax error, unexpected '=', expecting IDENTIFIER\n        ctrl_word.alumux1_sel = sel1; \n                              ^\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:35: syntax error, unexpected '=', expecting IDENTIFIER\n        ctrl_word.cmpop = op; \n                        ^\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:36: syntax error, unexpected '=', expecting IDENTIFIER\n        ctrl_word.cmpmux_sel = sel; \n                             ^\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:44: syntax error, unexpected '=', expecting IDENTIFIER\n    ctrl_word.regfilemux_sel = regfilemux::alu_out; \n                             ^\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:45: syntax error, unexpected '=', expecting IDENTIFIER\n    ctrl_word.cmpmux_sel = cmpmux::rs2_out; \n                         ^\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:46: syntax error, unexpected '=', expecting IDENTIFIER\n    ctrl_word.alumux1_sel = alumux::rs1_out; \n                          ^\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:47: syntax error, unexpected '=', expecting IDENTIFIER\n    ctrl_word.cmpop = beq; \n                    ^\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:48: syntax error, unexpected '=', expecting IDENTIFIER\n    ctrl_word.aluop = alu_add;  \n                    ^\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:49: syntax error, unexpected '=', expecting IDENTIFIER\n    ctrl_word.dmem_read = 1'b0;\n                        ^\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:50: syntax error, unexpected '=', expecting IDENTIFIER\n    ctrl_word.dmem_write = 1'b0; \n                         ^\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:51: syntax error, unexpected '=', expecting IDENTIFIER\n    ctrl_word.mem_byte_enable = 4'b1111; \n                              ^\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:52: syntax error, unexpected '=', expecting IDENTIFIER\n    ctrl_word.opcode = opcode; \n                     ^\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:53: syntax error, unexpected '=', expecting IDENTIFIER\n    ctrl_word.funct3 = funct3; \n                     ^\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:54: syntax error, unexpected '=', expecting IDENTIFIER\n    ctrl_word.funct7 = funct7;\n                     ^\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:55: syntax error, unexpected '=', expecting IDENTIFIER\n    ctrl_word.br_en = 1'b0; \n                    ^\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:59: syntax error, unexpected '(', expecting IDENTIFIER\n            loadRegfile(regfilemux::u_imm);\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:62: syntax error, unexpected '(', expecting IDENTIFIER\n            setALU(alumux::pc_out, 1'b1, alu_add);\n                   ^~~~~~\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:66: syntax error, unexpected '(', expecting IDENTIFIER\n            loadRegfile(regfilemux::pc_plus4);\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:70: syntax error, unexpected '(', expecting IDENTIFIER\n            loadRegfile(regfilemux::pc_plus4);\n                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:74: syntax error, unexpected '(', expecting IDENTIFIER\n            setALU(alumux::pc_out, 1'b1, alu_add); \n                   ^~~~~~\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:78: syntax error, unexpected '=', expecting IDENTIFIER\n            ctrl_word.dmem_read = 1'b1; \n                                ^\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:81: syntax error, unexpected '(', expecting IDENTIFIER\n                lb: loadRegfile(regfilemux::lb);\n                                ^~~~~~~~~~\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:82: syntax error, unexpected '(', expecting IDENTIFIER\n                lh: loadRegfile(regfilemux::lh);\n                                ^~~~~~~~~~\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:83: syntax error, unexpected '(', expecting IDENTIFIER\n                lw: loadRegfile(regfilemux::lw);\n                                ^~~~~~~~~~\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:84: syntax error, unexpected '(', expecting IDENTIFIER\n                lbu: loadRegfile(regfilemux::lbu);\n                                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:85: syntax error, unexpected '(', expecting IDENTIFIER\n                lhu: loadRegfile(regfilemux::lhu);\n                                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:90: syntax error, unexpected '(', expecting IDENTIFIER\n            setALU(alumux::rs1_out, 1'b1, alu_add);\n                   ^~~~~~\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:91: syntax error, unexpected '=', expecting IDENTIFIER\n            ctrl_word.dmem_write = 1'b1; \n                                 ^\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:96: syntax error, unexpected '(', expecting IDENTIFIER\n                    setCMP(cmpmux::i_imm, 1'b1, blt);\n                           ^~~~~~\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:100: syntax error, unexpected '(', expecting IDENTIFIER\n                    setCMP(cmpmux::i_imm, 1'b1, bltu);   \n                           ^~~~~~\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:104: syntax error, unexpected '(', expecting IDENTIFIER\n                    loadRegfile(regfilemux::alu_out);\n                                ^~~~~~~~~~\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:106: syntax error, unexpected '(', expecting IDENTIFIER\n                        setALU(alumux::rs1_out, 1'b1, alu_sra);\n                               ^~~~~~\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:108: syntax error, unexpected '(', expecting IDENTIFIER\n                        setALU(alumux::rs1_out, 1'b1, alu_srl);\n                               ^~~~~~\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:111: syntax error, unexpected '(', expecting IDENTIFIER\n                    loadRegfile(regfilemux::alu_out);\n                                ^~~~~~~~~~\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:118: syntax error, unexpected '(', expecting IDENTIFIER\n                loadRegfile(regfilemux::alu_out);\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:123: syntax error, unexpected '(', expecting IDENTIFIER\n                        loadRegfile(regfilemux::alu_out); \n                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:125: syntax error, unexpected '(', expecting IDENTIFIER\n                            setALU(alumux::rs1_out, 1'b1, alu_sub);\n                                   ^~~~~~\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:127: syntax error, unexpected '(', expecting IDENTIFIER\n                            setALU(alumux::rs1_out, 1'b1, alu_add);\n                                   ^~~~~~\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:130: syntax error, unexpected '(', expecting IDENTIFIER\n                        setCMP(cmpmux::rs2_out, 1'b1, blt);\n                               ^~~~~~\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:134: syntax error, unexpected '(', expecting IDENTIFIER\n                        setCMP(cmpmux::rs2_out, 1'b1, bltu);\n                               ^~~~~~\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:138: syntax error, unexpected '(', expecting IDENTIFIER\n                        loadRegfile(regfilemux::alu_out);\n                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:140: syntax error, unexpected '(', expecting IDENTIFIER\n                            setALU(alumux::rs1_out, 1'b1, alu_sra);\n                                   ^~~~~~\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:142: syntax error, unexpected '(', expecting IDENTIFIER\n                            setALU(alumux::rs1_out, 1'b1, alu_srl);                    \n                                   ^~~~~~\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:145: syntax error, unexpected '(', expecting IDENTIFIER\n                        loadRegfile(regfilemux::alu_out);\n                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/444555755/mp4/hdl/control_rom.sv:152: syntax error, unexpected '=', expecting IDENTIFIER\n            ctrl_word.load_regfile = 1'b0;\n                                   ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n"
module control_rom
(
    input rv32i_opcode opcode,
    input logic [2:0] funct3,
    input logic [6:0] funct7, 
    output rv32i_control_word ctrl_word
);
branch_funct3_t branch_funct3;

load_funct3_t load_funct3;
arith_funct3_t arith_funct3;

assign arith_funct3 = arith_funct3_t'(funct3);
assign branch_funct3 = branch_funct3_t'(funct3);
assign load_funct3 = load_funct3_t'(funct3);



function void loadRegfile(regfilemux::regfilemux_sel_t sel);
    ctrl_word.load_regfile = 1'b1; 
    ctrl_word.regfilemux_sel = sel;
endfunction
function void setALU(alumux::alumux1_sel_t sel1,
                     logic setop = 1'b0, alu_ops op = alu_add);
    if (setop) begin 
        ctrl_word.aluop = op;
        ctrl_word.alumux1_sel = sel1; 
    end 
endfunction
function automatic void setCMP(cmpmux::cmpmux_sel_t sel, 
                               logic setop = 1'b0, branch_funct3_t op = beq);
    if (setop) begin 
        ctrl_word.cmpop = op; 
        ctrl_word.cmpmux_sel = sel; 
    end 
endfunction

always_comb
begin

    ctrl_word.load_regfile = 1'b0;
    ctrl_word.regfilemux_sel = regfilemux::alu_out; 
    ctrl_word.cmpmux_sel = cmpmux::rs2_out; 
    ctrl_word.alumux1_sel = alumux::rs1_out; 
    ctrl_word.cmpop = beq; 
    ctrl_word.aluop = alu_add;
    ctrl_word.dmem_read = 1'b0;
    ctrl_word.dmem_write = 1'b0; 
    ctrl_word.mem_byte_enable = 4'b1111; 
    ctrl_word.opcode = opcode; 
    ctrl_word.funct3 = funct3; 
    ctrl_word.funct7 = funct7;
    ctrl_word.br_en = 1'b0; 

    case(opcode)
        op_lui: begin 
            loadRegfile(regfilemux::u_imm);
        end 
        op_auipc: begin
            setALU(alumux::pc_out, 1'b1, alu_add);
            loadRegfile(regfilemux::alu_out);            
        end
        op_jal: begin 
            loadRegfile(regfilemux::pc_plus4);
            setALU(alumux::pc_out, 1'b1, alu_add);
        end 
        op_jalr: begin 
            loadRegfile(regfilemux::pc_plus4);
            setALU(alumux::rs1_out, 1'b1, alu_add);
        end 
        op_br: begin 
            setALU(alumux::pc_out, 1'b1, alu_add); 
            setCMP(cmpmux::rs2_out, 1'b1, branch_funct3);
        end 
        op_load: begin 
            ctrl_word.dmem_read = 1'b1; 
            setALU(alumux::rs1_out, 1'b1, alu_add);
            case(load_funct3)
                lb: loadRegfile(regfilemux::lb);
                lh: loadRegfile(regfilemux::lh);
                lw: loadRegfile(regfilemux::lw);
                lbu: loadRegfile(regfilemux::lbu);
                lhu: loadRegfile(regfilemux::lhu);
                default:;
            endcase
        end 
        op_store: begin 
            setALU(alumux::rs1_out, 1'b1, alu_add);
            ctrl_word.dmem_write = 1'b1; 
        end 
        op_imm: begin 
            case(arith_funct3)
                slt: begin 
                    setCMP(cmpmux::i_imm, 1'b1, blt);
                    loadRegfile(regfilemux::br_en);
                end 
                sltu: begin 
                    setCMP(cmpmux::i_imm, 1'b1, bltu);   
                    loadRegfile(regfilemux::br_en);
                end 
                sr: begin 
                    loadRegfile(regfilemux::alu_out);
                    if(funct7[5])
                        setALU(alumux::rs1_out, 1'b1, alu_sra);
                    else
                        setALU(alumux::rs1_out, 1'b1, alu_srl);
                end
                default: begin 
                    loadRegfile(regfilemux::alu_out);
                    setALU(alumux::rs1_out, 1'b1, alu_ops'(arith_funct3));
                end 
            endcase 
        end 
        op_reg: begin
            if(funct7 == 7'd1) begin
                loadRegfile(regfilemux::alu_out);
            end 
            else begin
                case(arith_funct3)
                    add: begin
                        loadRegfile(regfilemux::alu_out); 
                        if(funct7[5])
                            setALU(alumux::rs1_out, 1'b1, alu_sub);
                        else
                            setALU(alumux::rs1_out, 1'b1, alu_add);
                    end 
                    slt: begin 
                        setCMP(cmpmux::rs2_out, 1'b1, blt);
                        loadRegfile(regfilemux::br_en);
                    end 
                    sltu: begin 
                        setCMP(cmpmux::rs2_out, 1'b1, bltu);
                        loadRegfile(regfilemux::br_en);                    
                    end 
                    sr: begin 
                        loadRegfile(regfilemux::alu_out);
                        if(funct7[5])
                            setALU(alumux::rs1_out, 1'b1, alu_sra);
                        else
                            setALU(alumux::rs1_out, 1'b1, alu_srl);                    
                    end 
                    default: begin 
                        loadRegfile(regfilemux::alu_out);
                        setALU(alumux::rs1_out, 1'b1, alu_ops'(arith_funct3));
                    end    
                endcase 
            end
        end
        default: begin
            ctrl_word.load_regfile = 1'b0;
            ctrl_word.regfilemux_sel = regfilemux::alu_out; 
            ctrl_word.cmpmux_sel = cmpmux::rs2_out; 
            ctrl_word.alumux1_sel = alumux::rs1_out; 
            ctrl_word.cmpop = beq; 
            ctrl_word.aluop = alu_add;
            ctrl_word.dmem_read = 1'b0;
            ctrl_word.dmem_write = 1'b0; 
            ctrl_word.mem_byte_enable = 4'b1111; 
            ctrl_word.opcode = opcode; 
            ctrl_word.funct3 = funct3; 
            ctrl_word.funct7 = funct7;
            ctrl_word.br_en = 1'b0;
        end
    endcase
end
endmodule
module control_rom
(
    input rv32i_opcode opcode,
    input logic [2:0] funct3,
    input logic [6:0] funct7, 
    output rv32i_control_word ctrl_word
);

branch_funct3_t branch_funct3;

load_funct3_t load_funct3;
arith_funct3_t arith_funct3;

assign arith_funct3 = arith_funct3_t'(funct3);
assign branch_funct3 = branch_funct3_t'(funct3);
assign load_funct3 = load_funct3_t'(funct3);



function void loadRegfile(regfilemux::regfilemux_sel_t sel);
    ctrl_word.load_regfile = 1'b1; 
    ctrl_word.regfilemux_sel = sel;
endfunction
function void setALU(alumux::alumux1_sel_t sel1,
                     logic setop = 1'b0, alu_ops op = alu_add);
    if (setop) begin 
        ctrl_word.aluop = op;
        ctrl_word.alumux1_sel = sel1; 
    end 
endfunction
function automatic void setCMP(cmpmux::cmpmux_sel_t sel, 
                               logic setop = 1'b0, branch_funct3_t op = beq);
    if (setop) begin 
        ctrl_word.cmpop = op; 
        ctrl_word.cmpmux_sel = sel; 
    end 
endfunction

always_comb
begin

    ctrl_word.load_regfile = 1'b0;
    ctrl_word.regfilemux_sel = regfilemux::alu_out; 
    ctrl_word.cmpmux_sel = cmpmux::rs2_out; 
    ctrl_word.alumux1_sel = alumux::rs1_out; 
    ctrl_word.cmpop = beq; 
    ctrl_word.aluop = alu_add;
    ctrl_word.dmem_read = 1'b0;
    ctrl_word.dmem_write = 1'b0; 
    ctrl_word.mem_byte_enable = 4'b1111; 
    ctrl_word.opcode = opcode; 
    ctrl_word.funct3 = funct3; 
    ctrl_word.funct7 = funct7;
    ctrl_word.br_en = 1'b0; 

    case(opcode)
        op_lui: begin 
            loadRegfile(regfilemux::u_imm);
        end 
        op_auipc: begin
            setALU(alumux::pc_out, 1'b1, alu_add);
            loadRegfile(regfilemux::alu_out);            
        end
        op_jal: begin 
            loadRegfile(regfilemux::pc_plus4);
            setALU(alumux::pc_out, 1'b1, alu_add);
        end 
        op_jalr: begin 
            loadRegfile(regfilemux::pc_plus4);
            setALU(alumux::rs1_out, 1'b1, alu_add);
        end 
        op_br: begin 
            setALU(alumux::pc_out, 1'b1, alu_add); 
            setCMP(cmpmux::rs2_out, 1'b1, branch_funct3);
        end 
        op_load: begin 
            ctrl_word.dmem_read = 1'b1; 
            setALU(alumux::rs1_out, 1'b1, alu_add);
            case(load_funct3)
                lb: loadRegfile(regfilemux::lb);
                lh: loadRegfile(regfilemux::lh);
                lw: loadRegfile(regfilemux::lw);
                lbu: loadRegfile(regfilemux::lbu);
                lhu: loadRegfile(regfilemux::lhu);
                default:;
            endcase
        end 
        op_store: begin 
            setALU(alumux::rs1_out, 1'b1, alu_add);
            ctrl_word.dmem_write = 1'b1; 
        end 
        op_imm: begin 
            case(arith_funct3)
                slt: begin 
                    setCMP(cmpmux::i_imm, 1'b1, blt);
                    loadRegfile(regfilemux::br_en);
                end 
                sltu: begin 
                    setCMP(cmpmux::i_imm, 1'b1, bltu);   
                    loadRegfile(regfilemux::br_en);
                end 
                sr: begin 
                    loadRegfile(regfilemux::alu_out);
                    if(funct7[5])
                        setALU(alumux::rs1_out, 1'b1, alu_sra);
                    else
                        setALU(alumux::rs1_out, 1'b1, alu_srl);
                end
                default: begin 
                    loadRegfile(regfilemux::alu_out);
                    setALU(alumux::rs1_out, 1'b1, alu_ops'(arith_funct3));
                end 
            endcase 
        end 
        op_reg: begin
            if(funct7 == 7'd1) begin
                loadRegfile(regfilemux::alu_out);
            end 
            else begin
                case(arith_funct3)
                    add: begin
                        loadRegfile(regfilemux::alu_out); 
                        if(funct7[5])
                            setALU(alumux::rs1_out, 1'b1, alu_sub);
                        else
                            setALU(alumux::rs1_out, 1'b1, alu_add);
                    end 
                    slt: begin 
                        setCMP(cmpmux::rs2_out, 1'b1, blt);
                        loadRegfile(regfilemux::br_en);
                    end 
                    sltu: begin 
                        setCMP(cmpmux::rs2_out, 1'b1, bltu);
                        loadRegfile(regfilemux::br_en);                    
                    end 
                    sr: begin 
                        loadRegfile(regfilemux::alu_out);
                        if(funct7[5])
                            setALU(alumux::rs1_out, 1'b1, alu_sra);
                        else
                            setALU(alumux::rs1_out, 1'b1, alu_srl);                    
                    end 
                    default: begin 
                        loadRegfile(regfilemux::alu_out);
                        setALU(alumux::rs1_out, 1'b1, alu_ops'(arith_funct3));
                    end    
                endcase 
            end
        end
        default: begin
            ctrl_word.load_regfile = 1'b0;
            ctrl_word.regfilemux_sel = regfilemux::alu_out; 
            ctrl_word.cmpmux_sel = cmpmux::rs2_out; 
            ctrl_word.alumux1_sel = alumux::rs1_out; 
            ctrl_word.cmpop = beq; 
            ctrl_word.aluop = alu_add;
            ctrl_word.dmem_read = 1'b0;
            ctrl_word.dmem_write = 1'b0; 
            ctrl_word.mem_byte_enable = 4'b1111; 
            ctrl_word.opcode = opcode; 
            ctrl_word.funct3 = funct3; 
            ctrl_word.funct7 = funct7;
            ctrl_word.br_en = 1'b0;
        end
    endcase
end
endmodule