data/full_repos/permissive/514835397/tb/fifo_buffer_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/514835397/tb/fifo_buffer_TB.v:25: Unsupported: Ignoring delay on this delayed statement.\nforever #2\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/514835397/tb/fifo_buffer_TB.v:32: Unsupported: Ignoring delay on this delayed statement.\n#4\n^\n%Warning-STMTDLY: data/full_repos/permissive/514835397/tb/fifo_buffer_TB.v:37: Unsupported: Ignoring delay on this delayed statement.\n#200\n^\n%Warning-STMTDLY: data/full_repos/permissive/514835397/tb/fifo_buffer_TB.v:40: Unsupported: Ignoring delay on this delayed statement.\n#200\n^\n%Error: data/full_repos/permissive/514835397/tb/fifo_buffer_TB.v:10: Cannot find file containing module: \'fifo_buffer\'\nfifo_buffer dut\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514835397/tb,data/full_repos/permissive/514835397/fifo_buffer\n             data/full_repos/permissive/514835397/tb,data/full_repos/permissive/514835397/fifo_buffer.v\n             data/full_repos/permissive/514835397/tb,data/full_repos/permissive/514835397/fifo_buffer.sv\n             fifo_buffer\n             fifo_buffer.v\n             fifo_buffer.sv\n             obj_dir/fifo_buffer\n             obj_dir/fifo_buffer.v\n             obj_dir/fifo_buffer.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fifo_buffer_TB();

reg sclock, sreset_n;
reg swrite_enable, sread_enable;
reg [7:0] sdata_in;
reg [5:0] sfull_thres;
wire [7:0] sdata_out;
wire sempty, sfull;

fifo_buffer dut
(
	.clock(sclock),
	.reset_n(sreset_n),
	.write_enable(swrite_enable),
	.read_enable(sread_enable),
	.data_in(sdata_in),
	.full_thres(sfull_thres),
	.data_out(sdata_out),
	.empty(sempty),
	.full(sfull)
);

initial begin
	sclock = 0;
forever #2
	sclock = ~sclock;
end

initial begin
	sreset_n = 0;
	sfull_thres = 32;
#4
	sreset_n = 1;
	sdata_in = 120;
	swrite_enable = 1;
	sread_enable = 0;
#200
	swrite_enable = 0;
	sread_enable = 1;
#200
	$stop;
end

endmodule
module fifo_buffer_TB();


reg sclock, sreset_n;
reg swrite_enable, sread_enable;
reg [7:0] sdata_in;
reg [5:0] sfull_thres;
wire [7:0] sdata_out;
wire sempty, sfull;

fifo_buffer dut
(
	.clock(sclock),
	.reset_n(sreset_n),
	.write_enable(swrite_enable),
	.read_enable(sread_enable),
	.data_in(sdata_in),
	.full_thres(sfull_thres),
	.data_out(sdata_out),
	.empty(sempty),
	.full(sfull)
);

initial begin
	sclock = 0;
forever #2
	sclock = ~sclock;
end

initial begin
	sreset_n = 0;
	sfull_thres = 32;
#4
	sreset_n = 1;
	sdata_in = 120;
	swrite_enable = 1;
	sread_enable = 0;
#200
	swrite_enable = 0;
	sread_enable = 1;
#200
	$stop;
end

endmodule