data/full_repos/permissive/507312280/rtl/perips/sysio/spi.v
1: b'%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/spi.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507312280/rtl/perips/sysio,data/full_repos/permissive/507312280/defines.v\n             data/full_repos/permissive/507312280/rtl/perips/sysio,data/full_repos/permissive/507312280/defines.v.v\n             data/full_repos/permissive/507312280/rtl/perips/sysio,data/full_repos/permissive/507312280/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/spi.v:8: Define or directive not defined: \'`MemBus\'\n    input wire[`MemBus] data_i,\n               ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/spi.v:8: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire[`MemBus] data_i,\n                      ^\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/spi.v:10: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire we_i,\n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/spi.v:11: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[7:0] raddr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/spi.v:12: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire rd_i,\n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/spi.v:13: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg[`MemBus] data_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/spi.v:13: Define or directive not defined: \'`MemBus\'\n    output reg[`MemBus] data_o,\n               ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/spi.v:17: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input wire spi_miso,              \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/spi.v:18: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire spi_cs,               \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/spi.v:19: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg spi_clk                \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/perips/sysio/spi.v:54: syntax error, unexpected assign\nassign spi_cs = ~spi_ctrl[3];    \n^~~~~~\n%Error: Exiting due to 12 error(s)\n'
module spi(

    input wire clk,
    input wire rst_n,

    input wire[7:0] waddr_i,
    input wire[`MemBus] data_i,
    input wire[3:0] sel_i,
    input wire we_i,
    input wire[7:0] raddr_i,
    input wire rd_i,
    output reg[`MemBus] data_o,


    output reg spi_mosi,
    input wire spi_miso,
    output wire spi_cs,
    output reg spi_clk

);

localparam SPI_CTRL   = 4'h0;
localparam SPI_DATA   = 4'h4;
localparam SPI_STATUS = 4'h8;








reg[15:0] spi_ctrl;



reg[15:0] spi_data;



reg spi_status;

reg[8:0] clk_cnt;
reg en;
reg[4:0] spi_clk_edge_cnt;
reg spi_clk_edge_level;
reg[7:0] rdata;
reg done;
reg[3:0] bit_index;
wire[8:0] div_cnt;


assign spi_cs = ~spi_ctrl[3];

assign div_cnt = spi_ctrl[15:8];


always @ (posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        spi_ctrl <= 16'h0;
        spi_data <= 16'h0;
        spi_status <= 1'b0;
    end else begin
        spi_status <= en;
        if (we_i == 1'b1) begin
            case (waddr_i[3:0])
                SPI_CTRL: begin
                    if(sel_i[0])
                        spi_ctrl[7:0] <= data_i[7:0];
                    if(sel_i[1])
                        spi_ctrl[15:8] <= data_i[15:8];
                end
                SPI_DATA: begin
                    spi_data <= data_i[15:0];
                end
                default: begin

                end
            endcase
        end else begin
            spi_ctrl[0] <= 1'b0;

            if (done == 1'b1) begin
                if(rdata===8'hXX)
                    spi_data <= {8'h0, 8'h0};
                else
                    spi_data <= {8'h0, rdata};
            end
        end
    end
end


always @ (posedge clk) begin
    if (rd_i == 1'b1) begin
        case (raddr_i[3:0])
            SPI_CTRL: begin
                data_o <= {16'h0, spi_ctrl};
            end
            SPI_DATA: begin
                data_o <= {24'h0, spi_data[7:0]};
            end
            SPI_STATUS: begin
                data_o <= {31'h0, spi_status};
            end
            default: begin
                data_o <= 32'h0;
            end
        endcase
    end
    else begin
        data_o <= data_o;
    end
end



always @ (posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        en <= 1'b0;
    end else begin
        if (spi_ctrl[0] == 1'b1) begin
            en <= 1'b1;
        end else if (done == 1'b1) begin
            en <= 1'b0;
        end else begin
            en <= en;
        end
    end
end


always @ (posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        clk_cnt <= 9'h0;
    end else if (en == 1'b1) begin
        if (clk_cnt == div_cnt) begin
            clk_cnt <= 9'h0;
        end else begin
            clk_cnt <= clk_cnt + 1'b1;
        end
    end else begin
        clk_cnt <= 9'h0;
    end
end



always @ (posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        spi_clk_edge_cnt <= 5'h0;
        spi_clk_edge_level <= 1'b0;
    end else if (en == 1'b1) begin

        if (clk_cnt == div_cnt) begin
            if (spi_clk_edge_cnt == 5'd17) begin
                spi_clk_edge_cnt <= 5'h0;
                spi_clk_edge_level <= 1'b0;
            end else begin
                spi_clk_edge_cnt <= spi_clk_edge_cnt + 1'b1;
                spi_clk_edge_level <= 1'b1;
            end
        end else begin
            spi_clk_edge_level <= 1'b0;
        end
    end else begin
        spi_clk_edge_cnt <= 5'h0;
        spi_clk_edge_level <= 1'b0;
    end
end


always @ (posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        spi_clk <= 1'b0;
        rdata <= 8'h0;
        spi_mosi <= 1'b0;
        bit_index <= 4'h0;
    end else begin
        if (en) begin
            if (spi_clk_edge_level == 1'b1) begin
                case (spi_clk_edge_cnt)

                    1, 3, 5, 7, 9, 11, 13, 15: begin
                        spi_clk <= ~spi_clk;
                        if (spi_ctrl[2] == 1'b1) begin
                            spi_mosi <= spi_data[bit_index];
                            bit_index <= bit_index - 1'b1;
                        end else begin
                            rdata <= {rdata[6:0], spi_miso};
                        end
                    end

                    2, 4, 6, 8, 10, 12, 14, 16: begin
                        spi_clk <= ~spi_clk;
                        if (spi_ctrl[2] == 1'b1) begin
                            rdata <= {rdata[6:0], spi_miso};
                        end else begin
                            spi_mosi <= spi_data[bit_index];
                            bit_index <= bit_index - 1'b1;
                        end
                    end
                    17: begin
                        spi_clk <= spi_ctrl[1];
                    end
                endcase
            end
        end else begin

            spi_clk <= spi_ctrl[1];
            if (spi_ctrl[2] == 1'b0) begin
                spi_mosi <= spi_data[7];
                bit_index <= 4'h6;
            end else begin
                bit_index <= 4'h7;
            end
        end
    end
end


always @ (posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        done <= 1'b0;
    end else begin
        if (en && spi_clk_edge_cnt == 5'd17) begin
            done <= 1'b1;
        end else begin
            done <= 1'b0;
        end
    end
end



endmodule
module spi(

    input wire clk,
    input wire rst_n,

    input wire[7:0] waddr_i,
    input wire[`MemBus] data_i,
    input wire[3:0] sel_i,
    input wire we_i,
    input wire[7:0] raddr_i,
    input wire rd_i,
    output reg[`MemBus] data_o,


    output reg spi_mosi,
    input wire spi_miso,
    output wire spi_cs,
    output reg spi_clk

);


localparam SPI_CTRL   = 4'h0;
localparam SPI_DATA   = 4'h4;
localparam SPI_STATUS = 4'h8;








reg[15:0] spi_ctrl;



reg[15:0] spi_data;



reg spi_status;

reg[8:0] clk_cnt;
reg en;
reg[4:0] spi_clk_edge_cnt;
reg spi_clk_edge_level;
reg[7:0] rdata;
reg done;
reg[3:0] bit_index;
wire[8:0] div_cnt;


assign spi_cs = ~spi_ctrl[3];

assign div_cnt = spi_ctrl[15:8];


always @ (posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        spi_ctrl <= 16'h0;
        spi_data <= 16'h0;
        spi_status <= 1'b0;
    end else begin
        spi_status <= en;
        if (we_i == 1'b1) begin
            case (waddr_i[3:0])
                SPI_CTRL: begin
                    if(sel_i[0])
                        spi_ctrl[7:0] <= data_i[7:0];
                    if(sel_i[1])
                        spi_ctrl[15:8] <= data_i[15:8];
                end
                SPI_DATA: begin
                    spi_data <= data_i[15:0];
                end
                default: begin

                end
            endcase
        end else begin
            spi_ctrl[0] <= 1'b0;

            if (done == 1'b1) begin
                if(rdata===8'hXX)
                    spi_data <= {8'h0, 8'h0};
                else
                    spi_data <= {8'h0, rdata};
            end
        end
    end
end


always @ (posedge clk) begin
    if (rd_i == 1'b1) begin
        case (raddr_i[3:0])
            SPI_CTRL: begin
                data_o <= {16'h0, spi_ctrl};
            end
            SPI_DATA: begin
                data_o <= {24'h0, spi_data[7:0]};
            end
            SPI_STATUS: begin
                data_o <= {31'h0, spi_status};
            end
            default: begin
                data_o <= 32'h0;
            end
        endcase
    end
    else begin
        data_o <= data_o;
    end
end



always @ (posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        en <= 1'b0;
    end else begin
        if (spi_ctrl[0] == 1'b1) begin
            en <= 1'b1;
        end else if (done == 1'b1) begin
            en <= 1'b0;
        end else begin
            en <= en;
        end
    end
end


always @ (posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        clk_cnt <= 9'h0;
    end else if (en == 1'b1) begin
        if (clk_cnt == div_cnt) begin
            clk_cnt <= 9'h0;
        end else begin
            clk_cnt <= clk_cnt + 1'b1;
        end
    end else begin
        clk_cnt <= 9'h0;
    end
end



always @ (posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        spi_clk_edge_cnt <= 5'h0;
        spi_clk_edge_level <= 1'b0;
    end else if (en == 1'b1) begin

        if (clk_cnt == div_cnt) begin
            if (spi_clk_edge_cnt == 5'd17) begin
                spi_clk_edge_cnt <= 5'h0;
                spi_clk_edge_level <= 1'b0;
            end else begin
                spi_clk_edge_cnt <= spi_clk_edge_cnt + 1'b1;
                spi_clk_edge_level <= 1'b1;
            end
        end else begin
            spi_clk_edge_level <= 1'b0;
        end
    end else begin
        spi_clk_edge_cnt <= 5'h0;
        spi_clk_edge_level <= 1'b0;
    end
end


always @ (posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        spi_clk <= 1'b0;
        rdata <= 8'h0;
        spi_mosi <= 1'b0;
        bit_index <= 4'h0;
    end else begin
        if (en) begin
            if (spi_clk_edge_level == 1'b1) begin
                case (spi_clk_edge_cnt)

                    1, 3, 5, 7, 9, 11, 13, 15: begin
                        spi_clk <= ~spi_clk;
                        if (spi_ctrl[2] == 1'b1) begin
                            spi_mosi <= spi_data[bit_index];
                            bit_index <= bit_index - 1'b1;
                        end else begin
                            rdata <= {rdata[6:0], spi_miso};
                        end
                    end

                    2, 4, 6, 8, 10, 12, 14, 16: begin
                        spi_clk <= ~spi_clk;
                        if (spi_ctrl[2] == 1'b1) begin
                            rdata <= {rdata[6:0], spi_miso};
                        end else begin
                            spi_mosi <= spi_data[bit_index];
                            bit_index <= bit_index - 1'b1;
                        end
                    end
                    17: begin
                        spi_clk <= spi_ctrl[1];
                    end
                endcase
            end
        end else begin

            spi_clk <= spi_ctrl[1];
            if (spi_ctrl[2] == 1'b0) begin
                spi_mosi <= spi_data[7];
                bit_index <= 4'h6;
            end else begin
                bit_index <= 4'h7;
            end
        end
    end
end


always @ (posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        done <= 1'b0;
    end else begin
        if (en && spi_clk_edge_cnt == 5'd17) begin
            done <= 1'b1;
        end else begin
            done <= 1'b0;
        end
    end
end



endmodule