data/full_repos/permissive/525152535/DFFC.v
data/verilator_xmls/b157c506-2f54-45df-93fb-621892f8a264.xml
module DFFC
#(
    parameter INIT = 1'b0
)
(
    input  CLEAR,
    input  CLK,
    input  D,
    output Q
);

    reg _r_Q;

    initial begin
        _r_Q = INIT;
    end

    always @(posedge CLEAR or posedge CLK) begin
    
        if (CLEAR) begin
            _r_Q <= 1'b0;
        end
        else begin
            _r_Q <= D;
        end
    end

    assign Q = _r_Q;

endmodule
module DFFC
#(
    parameter INIT = 1'b0
)
(
    input  CLEAR,
    input  CLK,
    input  D,
    output Q
);


    reg _r_Q;

    initial begin
        _r_Q = INIT;
    end

    always @(posedge CLEAR or posedge CLK) begin
    
        if (CLEAR) begin
            _r_Q <= 1'b0;
        end
        else begin
            _r_Q <= D;
        end
    end

    assign Q = _r_Q;

endmodule