data/full_repos/permissive/493019833/test/testcase/firrtl/IntegerModule/reference/IntegerModule.v
data/verilator_xmls/dce721cb-4346-4a5d-93f5-76e57ed6147f.xml
module ASSINT(y, in);
    parameter width = 4;
    output [width-1:0] y;
    input [width-1:0] in;
    assign y = $signed(in);
endmodule
module ASSINT(y, in);

    parameter width = 4;
    output [width-1:0] y;
    input [width-1:0] in;
    assign y = $signed(in);
endmodule