data/full_repos/permissive/496903659/133 fsm_ps2.v
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/496903659/133\n        ... Looked in:\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/133\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/133.v\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/133.sv\n             data/full_repos/permissive/496903659/133\n             data/full_repos/permissive/496903659/133.v\n             data/full_repos/permissive/496903659/133.sv\n             obj_dir/data/full_repos/permissive/496903659/133\n             obj_dir/data/full_repos/permissive/496903659/133.v\n             obj_dir/data/full_repos/permissive/496903659/133.sv\n%Error: Cannot find file containing module: fsm_ps2.v\n%Error: Exiting due to 2 error(s)\n'
module top_module(
    input clk,
    input [7:0] in,
    input reset,
    output done);

    reg [4:0] state, next_state;
    

    assign next_state = reset ? 1 : (in[3] ? (state[2:0] << 1) | (state[4:3] > 0) << 1 : (state[2:1] << 2) | ({state[4:3], state[0]} > 0) << 4);
    

    always @(posedge clk) begin
        state <= next_state;
    end
 

    assign done = (state == 'b1000);

endmodule
module top_module(
    input clk,
    input [7:0] in,
    input reset,
    output done);


    reg [4:0] state, next_state;
    

    assign next_state = reset ? 1 : (in[3] ? (state[2:0] << 1) | (state[4:3] > 0) << 1 : (state[2:1] << 2) | ({state[4:3], state[0]} > 0) << 4);
    

    always @(posedge clk) begin
        state <= next_state;
    end
 

    assign done = (state == 'b1000);

endmodule