data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU_TestBench.v
1: b'%Error: data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU_TestBench.v:27: Unsupported: fork statements\ninitial fork\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU_TestBench.v:29: Unsupported: Ignoring delay on this delayed statement.\n #1 MFC = 1;#1 Reset=0 ;#1 A=1; #1 B=0; #1 FLAGS=FLAGS_OUT;#1 S=1; \n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU_TestBench.v:29: Unsupported: Ignoring delay on this delayed statement.\n #1 MFC = 1;#1 Reset=0 ;#1 A=1; #1 B=0; #1 FLAGS=FLAGS_OUT;#1 S=1; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU_TestBench.v:29: Unsupported: Ignoring delay on this delayed statement.\n #1 MFC = 1;#1 Reset=0 ;#1 A=1; #1 B=0; #1 FLAGS=FLAGS_OUT;#1 S=1; \n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU_TestBench.v:29: Unsupported: Ignoring delay on this delayed statement.\n #1 MFC = 1;#1 Reset=0 ;#1 A=1; #1 B=0; #1 FLAGS=FLAGS_OUT;#1 S=1; \n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU_TestBench.v:29: Unsupported: Ignoring delay on this delayed statement.\n #1 MFC = 1;#1 Reset=0 ;#1 A=1; #1 B=0; #1 FLAGS=FLAGS_OUT;#1 S=1; \n                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU_TestBench.v:29: Unsupported: Ignoring delay on this delayed statement.\n #1 MFC = 1;#1 Reset=0 ;#1 A=1; #1 B=0; #1 FLAGS=FLAGS_OUT;#1 S=1; \n                                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU_TestBench.v:34: Unsupported: Ignoring delay on this delayed statement.\n #1 Clk = ~Clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU_TestBench.v:36: Unsupported: Ignoring delay on this delayed statement.\ninitial #sim_time $finish; \n        ^\n%Error: data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU_TestBench.v:39: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("ARM_CU_ALU_TestBench.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU_TestBench.v:40: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,ARM_CU_ALU_TestBench);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU_TestBench.v:42: Unsupported or unknown PLI call: $monitor\n $monitor("A=%4h,B=%4h,opcode=%3d,Out=%3h,FLAGS_OUT=%3d,FLAGS=%3d,S=%3d,ALUSTORE=%3d",A,B,opcode,Out,FLAGS_OUT,FLAGS,S,ALUSTORE);\n ^~~~~~~~\n%Error: Exiting due to 4 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ARM_CU_ALU_TestBench;

parameter sim_time = 750*2;
wire [17:0] signals;
wire IR_CU,  RFLOAD,  PCLOAD,  SRLOAD,  SRENABLED,  ALUSTORE,  MFA,  WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD;
wire [4:0] opcode; 
wire [3:0] CU; 
reg [31:0] IR;
reg [3:0] SR;
reg MFC , Reset , Clk ;

ControlUnit cu(IR_CU,  RFLOAD,  PCLOAD,  SRLOAD,  SRENABLED,  ALUSTORE,  MFA,  WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD,opcode,CU,MFC,Reset,Clk,IR,SR);

reg  [31:0] A,B;
reg [3:0] FLAGS;
reg S,ALU_OUT;
wire [31:0] Out;
wire [3:0] FLAGS_OUT;

ARM_ALU alu(A,B, opcode, FLAGS, Out,FLAGS_OUT,S,ALUSTORE);

reg [19:0] RSLCT;
wire [31:0] Rn,Rm,Rs,PCout;

RegisterFile RF(Out,Out,RSLCT,Clk, Reset, PCLOAD, RFLOAD,IR_CU, Rn,Rm,Rs,PCout);

initial fork
	MFC = 0; Reset=1 ; Clk=0 ; FLAGS =0;
	#1 MFC = 1;#1 Reset=0 ;#1 A=1; #1 B=0; #1 FLAGS=FLAGS_OUT;#1 S=1; 
join
	
	
always 
	#1 Clk = ~Clk;
	
initial #sim_time $finish; 

initial begin
	$dumpfile("ARM_CU_ALU_TestBench.vcd");
	$dumpvars(0,ARM_CU_ALU_TestBench);
	$display(" Test Results" );
	$monitor("A=%4h,B=%4h,opcode=%3d,Out=%3h,FLAGS_OUT=%3d,FLAGS=%3d,S=%3d,ALUSTORE=%3d",A,B,opcode,Out,FLAGS_OUT,FLAGS,S,ALUSTORE);
end

endmodule
module ARM_CU_ALU_TestBench;


parameter sim_time = 750*2;
wire [17:0] signals;
wire IR_CU,  RFLOAD,  PCLOAD,  SRLOAD,  SRENABLED,  ALUSTORE,  MFA,  WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD;
wire [4:0] opcode; 
wire [3:0] CU; 
reg [31:0] IR;
reg [3:0] SR;
reg MFC , Reset , Clk ;

ControlUnit cu(IR_CU,  RFLOAD,  PCLOAD,  SRLOAD,  SRENABLED,  ALUSTORE,  MFA,  WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD,opcode,CU,MFC,Reset,Clk,IR,SR);

reg  [31:0] A,B;
reg [3:0] FLAGS;
reg S,ALU_OUT;
wire [31:0] Out;
wire [3:0] FLAGS_OUT;

ARM_ALU alu(A,B, opcode, FLAGS, Out,FLAGS_OUT,S,ALUSTORE);

reg [19:0] RSLCT;
wire [31:0] Rn,Rm,Rs,PCout;

RegisterFile RF(Out,Out,RSLCT,Clk, Reset, PCLOAD, RFLOAD,IR_CU, Rn,Rm,Rs,PCout);

initial fork
	MFC = 0; Reset=1 ; Clk=0 ; FLAGS =0;
	#1 MFC = 1;#1 Reset=0 ;#1 A=1; #1 B=0; #1 FLAGS=FLAGS_OUT;#1 S=1; 
join
	
	
always 
	#1 Clk = ~Clk;
	
initial #sim_time $finish; 

initial begin
	$dumpfile("ARM_CU_ALU_TestBench.vcd");
	$dumpvars(0,ARM_CU_ALU_TestBench);
	$display(" Test Results" );
	$monitor("A=%4h,B=%4h,opcode=%3d,Out=%3h,FLAGS_OUT=%3d,FLAGS=%3d,S=%3d,ALUSTORE=%3d",A,B,opcode,Out,FLAGS_OUT,FLAGS,S,ALUSTORE);
end

endmodule