data/full_repos/permissive/489994352/Image-Part/conv1buffer.v
1: b'%Warning-WIDTH: data/full_repos/permissive/489994352/Image-Part/conv1buffer.v:52: Bit extraction of var[15:0] requires 4 bit index, not 14 bits.\n                                                                                : ... In instance conv1buffer\n    data_out={  data_ram[rd_pointer],data_ram[rd_pointer+1],data_ram[rd_pointer+2],\n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/489994352/Image-Part/conv1buffer.v:52: Operator ASSIGN expects 144 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 9 bits.\n                                                                                : ... In instance conv1buffer\n    data_out={  data_ram[rd_pointer],data_ram[rd_pointer+1],data_ram[rd_pointer+2],\n            ^\n%Error: Exiting due to 2 warning(s)\n'
module conv1buffer(data_out,full,empty,data_in,clk,rst_a,wr_en,rd_en);
 

   parameter data_width    = 16;
   parameter ram_depth     = 111*111;
   parameter address_width = $clog2(ram_depth);



   output reg [9*data_width-1:0] data_out;
   output      full;
   output      empty;
   input [data_width-1:0]  data_in;
   input      clk;
   input      rst_a;
   input      wr_en;
   input      rd_en;


   reg [address_width-1:0]    wr_pointer;
   reg [address_width-1:0]    rd_pointer;
   reg [address_width :0]     status_count;
   wire [data_width-1:0]      data_ram ;
   reg [data_width-1:0] mem [0:ram_depth-1];

 

   always @ (posedge clk,posedge rst_a)
     begin
  if(rst_a)
   wr_pointer = -2;
  else
   if(wr_en)
    wr_pointer = wr_pointer+1;
 end

   always @ (posedge clk,posedge rst_a)
     begin
  if(rst_a)
   rd_pointer = 0;
  else
   if(rd_en)
    rd_pointer = rd_pointer+1;
 end

   always @ (posedge clk,posedge rst_a)
    begin
  if(rst_a)
   data_out=0;
  else
   if(rd_en)
    data_out={  data_ram[rd_pointer],data_ram[rd_pointer+1],data_ram[rd_pointer+2],
                data_ram[rd_pointer+224],data_ram[rd_pointer+1+224],data_ram[rd_pointer+2+224],
                data_ram[rd_pointer+448],data_ram[rd_pointer+1+448],data_ram[rd_pointer+2+448]};
    end


   always @ (posedge clk,posedge rst_a)
    begin
  if(rst_a)
   status_count = 0;
  else
   if(wr_en && !rd_en && (status_count != ram_depth))
    status_count = status_count + 1;
  else
   if(rd_en && !wr_en && (status_count != 0))
    status_count = status_count - 1;
    end


   assign full = (status_count == (ram_depth));
   assign empty = (status_count == 0);

 always @(posedge clk)
 begin
     if(wr_en)
        mem[wr_pointer] <= data_in;
 end




endmodule
module conv1buffer(data_out,full,empty,data_in,clk,rst_a,wr_en,rd_en);

 

   parameter data_width    = 16;
   parameter ram_depth     = 111*111;
   parameter address_width = $clog2(ram_depth);



   output reg [9*data_width-1:0] data_out;
   output      full;
   output      empty;
   input [data_width-1:0]  data_in;
   input      clk;
   input      rst_a;
   input      wr_en;
   input      rd_en;


   reg [address_width-1:0]    wr_pointer;
   reg [address_width-1:0]    rd_pointer;
   reg [address_width :0]     status_count;
   wire [data_width-1:0]      data_ram ;
   reg [data_width-1:0] mem [0:ram_depth-1];

 

   always @ (posedge clk,posedge rst_a)
     begin
  if(rst_a)
   wr_pointer = -2;
  else
   if(wr_en)
    wr_pointer = wr_pointer+1;
 end

   always @ (posedge clk,posedge rst_a)
     begin
  if(rst_a)
   rd_pointer = 0;
  else
   if(rd_en)
    rd_pointer = rd_pointer+1;
 end

   always @ (posedge clk,posedge rst_a)
    begin
  if(rst_a)
   data_out=0;
  else
   if(rd_en)
    data_out={  data_ram[rd_pointer],data_ram[rd_pointer+1],data_ram[rd_pointer+2],
                data_ram[rd_pointer+224],data_ram[rd_pointer+1+224],data_ram[rd_pointer+2+224],
                data_ram[rd_pointer+448],data_ram[rd_pointer+1+448],data_ram[rd_pointer+2+448]};
    end


   always @ (posedge clk,posedge rst_a)
    begin
  if(rst_a)
   status_count = 0;
  else
   if(wr_en && !rd_en && (status_count != ram_depth))
    status_count = status_count + 1;
  else
   if(rd_en && !wr_en && (status_count != 0))
    status_count = status_count - 1;
    end


   assign full = (status_count == (ram_depth));
   assign empty = (status_count == 0);

 always @(posedge clk)
 begin
     if(wr_en)
        mem[wr_pointer] <= data_in;
 end




endmodule