data/full_repos/permissive/501791642/sim/shift_reg_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/shift_reg_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\nalways #1 CLK = ~CLK;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/shift_reg_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #6 CE = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/shift_reg_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #6 RST = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/shift_reg_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #4 CE = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/shift_reg_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #2 CE = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/shift_reg_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #10 D = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/shift_reg_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #16 D = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/shift_reg_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #50 $stop;\n    ^\n%Error: data/full_repos/permissive/501791642/sim/shift_reg_tb.v:18: Cannot find file containing module: \'shift_reg\'\nshift_reg #(\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/501791642/sim,data/full_repos/permissive/501791642/shift_reg\n             data/full_repos/permissive/501791642/sim,data/full_repos/permissive/501791642/shift_reg.v\n             data/full_repos/permissive/501791642/sim,data/full_repos/permissive/501791642/shift_reg.sv\n             shift_reg\n             shift_reg.v\n             shift_reg.sv\n             obj_dir/shift_reg\n             obj_dir/shift_reg.v\n             obj_dir/shift_reg.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module shift_reg_tb;

reg CLK, CE, RST, D, DIR;
wire [7:0] Q;

initial begin
    CLK = 0;
    RST = 1;
    CE = 0;
    D = 1;
    DIR = 1;
end

always #1 CLK = ~CLK;

shift_reg #(
    .W(8)
)
shift_reg
(
    .CLK(CLK),
    .CE(CE),
    .CLR(RST),
    .DIR(DIR),
    .D(D),
    .Q(Q)
);


initial begin
    #6 CE = 1;
    #6 RST = 0;
    #4 CE = 0;
    D = 0;
    #2 CE = 1;
    #10 D = 1;
    DIR = 0;
    #16 D = 0;
    DIR = 1;
    #50 $stop;
end

endmodule
module shift_reg_tb;


reg CLK, CE, RST, D, DIR;
wire [7:0] Q;

initial begin
    CLK = 0;
    RST = 1;
    CE = 0;
    D = 1;
    DIR = 1;
end

always #1 CLK = ~CLK;

shift_reg #(
    .W(8)
)
shift_reg
(
    .CLK(CLK),
    .CE(CE),
    .CLR(RST),
    .DIR(DIR),
    .D(D),
    .Q(Q)
);


initial begin
    #6 CE = 1;
    #6 RST = 0;
    #4 CE = 0;
    D = 0;
    #2 CE = 1;
    #10 D = 1;
    DIR = 0;
    #16 D = 0;
    DIR = 1;
    #50 $stop;
end

endmodule