data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v
1: b"%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:540: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\breaker.loop_breaker  (\n  ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block,data/full_repos/permissive/496906136/fpga_tech_buffer\n             data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block,data/full_repos/permissive/496906136/fpga_tech_buffer.v\n             data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block,data/full_repos/permissive/496906136/fpga_tech_buffer.sv\n             fpga_tech_buffer\n             fpga_tech_buffer.v\n             fpga_tech_buffer.sv\n             obj_dir/fpga_tech_buffer\n             obj_dir/fpga_tech_buffer.v\n             obj_dir/fpga_tech_buffer.sv\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:544: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\breaker.lut_tfinish  (\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:548: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\breaker.lut_tstart  (\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:347: Cannot find file containing module: 'fpga_tech_register'\n  fpga_tech_register cell_reg (\n  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:355: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\in_bufs:1.cell_tstart  (\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:359: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\in_bufs:2.cell_tstart  (\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:363: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\in_bufs:3.cell_tstart  (\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:367: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\in_bufs:4.cell_tstart  (\n  ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module fpga_logic_cell(\config_i.lut_config , \config_i.mux_config , clk_i, glb_rstn_i, logic_i, logic_o);
  wire _0_;
  wire _1_;
  wire _2_;
  wire _3_;
  wire _4_;
  wire _5_;
  wire _6_;
  wire _7_;
  input clk_i;
  input [15:0] \config_i.lut_config ;
  input \config_i.mux_config ;
  input glb_rstn_i;
  input [3:0] logic_i;
  wire [3:0] logic_in_buf;
  output logic_o;
  wire lut_out;
  wire register_out;
  assign _6_ = ~ \config_i.mux_config ;
  assign _7_ = _6_ ? lut_out : register_out;
  fpga_tech_register cell_reg (
    .clk_i(clk_i),
    .config_i_rst_polarity(1'h0),
    .config_i_rst_value(1'h0),
    .data_i(lut_out),
    .data_o(_5_),
    .rstn_i(glb_rstn_i)
  );
  fpga_tech_buffer \in_bufs:1.cell_tstart  (
    .i(logic_i[0]),
    .z(_0_)
  );
  fpga_tech_buffer \in_bufs:2.cell_tstart  (
    .i(logic_i[1]),
    .z(_1_)
  );
  fpga_tech_buffer \in_bufs:3.cell_tstart  (
    .i(logic_i[2]),
    .z(_2_)
  );
  fpga_tech_buffer \in_bufs:4.cell_tstart  (
    .i(logic_i[3]),
    .z(_3_)
  );
  fpga_lut_4 lut (
    .config_i(\config_i.lut_config ),
    .glb_rstn_i(glb_rstn_i),
    .logic_i(logic_in_buf),
    .logic_o(_4_)
  );
  assign lut_out = _4_;
  assign register_out = _5_;
  assign logic_in_buf = { _3_, _2_, _1_, _0_ };
  assign logic_o = _7_;
endmodule
module fpga_logic_cell(\config_i.lut_config , \config_i.mux_config , clk_i, glb_rstn_i, logic_i, logic_o);

  wire _0_;
  wire _1_;
  wire _2_;
  wire _3_;
  wire _4_;
  wire _5_;
  wire _6_;
  wire _7_;
  input clk_i;
  input [15:0] \config_i.lut_config ;
  input \config_i.mux_config ;
  input glb_rstn_i;
  input [3:0] logic_i;
  wire [3:0] logic_in_buf;
  output logic_o;
  wire lut_out;
  wire register_out;
  assign _6_ = ~ \config_i.mux_config ;
  assign _7_ = _6_ ? lut_out : register_out;
  fpga_tech_register cell_reg (
    .clk_i(clk_i),
    .config_i_rst_polarity(1'h0),
    .config_i_rst_value(1'h0),
    .data_i(lut_out),
    .data_o(_5_),
    .rstn_i(glb_rstn_i)
  );
  fpga_tech_buffer \in_bufs:1.cell_tstart  (
    .i(logic_i[0]),
    .z(_0_)
  );
  fpga_tech_buffer \in_bufs:2.cell_tstart  (
    .i(logic_i[1]),
    .z(_1_)
  );
  fpga_tech_buffer \in_bufs:3.cell_tstart  (
    .i(logic_i[2]),
    .z(_2_)
  );
  fpga_tech_buffer \in_bufs:4.cell_tstart  (
    .i(logic_i[3]),
    .z(_3_)
  );
  fpga_lut_4 lut (
    .config_i(\config_i.lut_config ),
    .glb_rstn_i(glb_rstn_i),
    .logic_i(logic_in_buf),
    .logic_o(_4_)
  );
  assign lut_out = _4_;
  assign register_out = _5_;
  assign logic_in_buf = { _3_, _2_, _1_, _0_ };
  assign logic_o = _7_;
endmodule