data/full_repos/permissive/406805302/verilog/pwm/pwm.v
1: b'%Warning-WIDTH: data/full_repos/permissive/406805302/verilog/pwm/pwm.v:23: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                         : ... In instance pwm\n            up_counter <= 1\'b0;\n                       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module pwm 
#(
    parameter pwm_bits = 8   
)(
    input i_clk,
    input i_reset,
    input [pwm_bits -1 : 0] duty_cycle,
    output reg o_pwm
);


    reg [pwm_bits -1 : 0] up_counter;


    always @(posedge i_clk or posedge i_reset) begin
        if (i_reset == 1'b1) begin
            up_counter <= 1'b0;
        end else begin
            up_counter <= up_counter + 1'b1;
        end
    end

    always @(posedge i_clk) begin

        o_pwm = up_counter < (duty_cycle + 1);
    end
endmodule
module pwm 
#(
    parameter pwm_bits = 8   
)(
    input i_clk,
    input i_reset,
    input [pwm_bits -1 : 0] duty_cycle,
    output reg o_pwm
);



    reg [pwm_bits -1 : 0] up_counter;


    always @(posedge i_clk or posedge i_reset) begin
        if (i_reset == 1'b1) begin
            up_counter <= 1'b0;
        end else begin
            up_counter <= up_counter + 1'b1;
        end
    end

    always @(posedge i_clk) begin

        o_pwm = up_counter < (duty_cycle + 1);
    end
endmodule