data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v
1: b'%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:77: Cannot find include file: sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v\n`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/504248338/verilog/dv/user_risc_boot,data/full_repos/permissive/504248338/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v\n             data/full_repos/permissive/504248338/verilog/dv/user_risc_boot,data/full_repos/permissive/504248338/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v.v\n             data/full_repos/permissive/504248338/verilog/dv/user_risc_boot,data/full_repos/permissive/504248338/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v.sv\n             sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v\n             sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v.v\n             sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v.sv\n             obj_dir/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v\n             obj_dir/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v.v\n             obj_dir/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v.sv\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:413: Cannot find include file: s25fl256s.sv\n`include "s25fl256s.sv" \n         ^~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n always #12.5 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:133: Unsupported: Ignoring delay on this delayed statement.\n  #200;  \n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:134: syntax error, unexpected \'@\'\n         repeat (10) @(posedge clock);\n                     ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:138: Define or directive not defined: \'`ADDR_SPACE_WBHOST\'\n  wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,\'h1);\n                     ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:138: Define or directive not defined: \'`WBHOST_GLBL_CFG\'\n  wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,\'h1);\n                                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:138: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,\'h1);\n                                                        ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:140: syntax error, unexpected \'@\'\n         repeat (2) @(posedge clock);\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:141: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:143: Define or directive not defined: \'`ADDR_SPACE_PINMUX\'\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h11F);\n                                   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:143: Define or directive not defined: \'`PINMUX_GBL_CFG0\'\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h11F);\n                                                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:143: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h11F);\n                                                                      ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:148: syntax error, unexpected \'@\'\n   repeat (1000) @(posedge clock);\n                 ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:164: Define or directive not defined: \'`ADDR_SPACE_PINMUX\'\n  wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32\'h11223344);\n                          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:164: Define or directive not defined: \'`PINMUX_SOFT_REG_1\'\n  wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32\'h11223344);\n                                             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:164: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32\'h11223344);\n                                                               ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:165: Define or directive not defined: \'`ADDR_SPACE_PINMUX\'\n  wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32\'h22334455);\n                          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:165: Define or directive not defined: \'`PINMUX_SOFT_REG_2\'\n  wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32\'h22334455);\n                                             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:165: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32\'h22334455);\n                                                               ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:166: Define or directive not defined: \'`ADDR_SPACE_PINMUX\'\n  wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32\'h33445566);\n                          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:166: Define or directive not defined: \'`PINMUX_SOFT_REG_3\'\n  wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32\'h33445566);\n                                             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:166: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32\'h33445566);\n                                                               ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:167: Define or directive not defined: \'`ADDR_SPACE_PINMUX\'\n  wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32\'h44556677);\n                          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:167: Define or directive not defined: \'`PINMUX_SOFT_REG_4\'\n  wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32\'h44556677);\n                                             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:167: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32\'h44556677);\n                                                               ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:168: Define or directive not defined: \'`ADDR_SPACE_PINMUX\'\n  wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32\'h55667788);\n                          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:168: Define or directive not defined: \'`PINMUX_SOFT_REG_5\'\n  wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32\'h55667788);\n                                             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:168: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32\'h55667788);\n                                                               ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:169: Define or directive not defined: \'`ADDR_SPACE_PINMUX\'\n  wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32\'h66778899);\n                          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:169: Define or directive not defined: \'`PINMUX_SOFT_REG_6\'\n  wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32\'h66778899);\n                                             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:169: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32\'h66778899);\n                                                               ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:193: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:287: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:288: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:295: Unsupported: wait statements\n  wait(wbd_ext_ack_o == 1);\n  ^~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:296: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:297: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:305: syntax error, unexpected \'@\'\n  repeat (2) @(posedge clock);\n             ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:314: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:315: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:322: Unsupported: wait statements\n  wait(wbd_ext_ack_o == 1);\n  ^~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:323: syntax error, unexpected \'@\'\n  repeat (1) @(negedge clock);\n             ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:325: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:326: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:334: syntax error, unexpected \'@\'\n  repeat (2) @(posedge clock);\n             ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:344: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:345: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:352: Unsupported: wait statements\n  wait(wbd_ext_ack_o == 1);\n  ^~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:353: syntax error, unexpected \'@\'\n  repeat (1) @(negedge clock);\n             ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:355: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:356: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_risc_boot/user_risc_boot_tb.v:369: syntax error, unexpected \'@\'\n  repeat (2) @(posedge clock);\n             ^\n%Error: Exiting due to 43 error(s), 10 warning(s)\n'
module user_risc_boot_tb;
	reg clock;
	reg wb_rst_i;
	reg power1, power2;
	reg power3, power4;

        reg        wbd_ext_cyc_i;
        reg        wbd_ext_stb_i;
        reg [31:0] wbd_ext_adr_i;
        reg        wbd_ext_we_i;
        reg [31:0] wbd_ext_dat_i;
        reg [3:0]  wbd_ext_sel_i;

        wire [31:0] wbd_ext_dat_o;
        wire        wbd_ext_ack_o;
        wire        wbd_ext_err_o;


	wire [37:0] io_oeb;
	wire [37:0] io_out;
	wire [37:0] io_in;

	wire gpio;
	wire [37:0] mprj_io;
	wire [7:0] mprj_io_0;
	reg         test_fail;
	reg [31:0] read_data;







	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
                wbd_ext_cyc_i ='h0;
                wbd_ext_stb_i ='h0;
                wbd_ext_adr_i ='h0;
                wbd_ext_we_i  ='h0;
                wbd_ext_dat_i ='h0;
                wbd_ext_sel_i ='h0;
	end

	`ifdef WFDUMP
	   initial begin
	   	$dumpfile("simx.vcd");
	   	$dumpvars(3, user_risc_boot_tb);
	   end
       `endif

	initial begin

		#200;
	        repeat (10) @(posedge clock);
		$display("Monitor: Standalone User Risc Boot Test Started");


		wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);

	        repeat (2) @(posedge clock);
		#1;

                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);



		repeat (30) begin
			repeat (1000) @(posedge clock);

		end


		$display("Monitor: Reading Back the expected value");









                test_fail = 0;
		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344);
		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455);
		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566);
		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677);
		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788);
		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899);


	   
	    	$display("###################################################");
          	if(test_fail == 0) begin
		   `ifdef GL
	    	       $display("Monitor: Standalone User Risc Boot (GL) Passed");
		   `else
		       $display("Monitor: Standalone User Risc Boot (RTL) Passed");
		   `endif
	        end else begin
		    `ifdef GL
	    	        $display("Monitor: Standalone User Risc Boot (GL) Failed");
		    `else
		        $display("Monitor: Standalone User Risc Boot (RTL) Failed");
		    `endif
		 end
	    	$display("###################################################");
	    $finish;
	end

	initial begin
		wb_rst_i <= 1'b1;
		#100;
		wb_rst_i <= 1'b0;
	end
wire USER_VDD1V8 = 1'b1;
wire VSS = 1'b0;

user_project_wrapper u_top(
`ifdef USE_POWER_PINS
    .vccd1(USER_VDD1V8),
    .vssd1(VSS),
`endif
    .wb_clk_i        (clock),
    .user_clock2     (1'b1),
    .wb_rst_i        (wb_rst_i),

    .wbs_cyc_i   (wbd_ext_cyc_i),
    .wbs_stb_i   (wbd_ext_stb_i),
    .wbs_adr_i   (wbd_ext_adr_i),
    .wbs_we_i    (wbd_ext_we_i),
    .wbs_dat_i   (wbd_ext_dat_i),
    .wbs_sel_i   (wbd_ext_sel_i),

    .wbs_dat_o   (wbd_ext_dat_o),
    .wbs_ack_o   (wbd_ext_ack_o),

 

    .la_data_in      ('1) ,
    .la_data_out     (),
    .la_oenb         ('0),
 


    .io_in          (io_in)  ,
    .io_out         (io_out) ,
    .io_oeb         (io_oeb) ,

    .user_irq       () 

);

`ifndef GL

    initial begin

    end
`endif    






   wire flash_clk = io_out[24];
   wire flash_csb = io_out[25];

   wire #1 io_oeb_29 = io_oeb[29];
   wire #1 io_oeb_30 = io_oeb[30];
   wire #1 io_oeb_31 = io_oeb[31];
   wire #1 io_oeb_32 = io_oeb[32];
   tri  #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz;
   tri  #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz;
   tri  #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz;
   tri  #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz;

   assign io_in[29] = flash_io0;
   assign io_in[30] = flash_io1;
   assign io_in[31] = flash_io2;
   assign io_in[32] = flash_io3;


     s25fl256s #(.mem_file_name("user_risc_boot.hex"),
	         .otp_file_name("none"),
                 .TimingModel("S25FL512SAGMFI010_F_30pF")) 
		 u_spi_flash_256mb (

       .SI      (flash_io0),
       .SO      (flash_io1),

       .SCK     (flash_clk),
       .CSNeg   (flash_csb),
       .WPNeg   (flash_io2),
       .HOLDNeg (flash_io3),
       .RSTNeg  (!wb_rst_i)

       );




task wb_user_core_write;
input [31:0] address;
input [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h1;
  wbd_ext_dat_i =data;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read;
input [31:0] address;
output [31:0] data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(negedge clock);
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read_check;
input [31:0] address;
output [31:0] data;
input [31:0] cmp_data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(negedge clock);
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  if(data !== cmp_data) begin
     $display("ERROR : WB USER ACCESS READ  Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
     test_fail = 1;
  end else begin
     $display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,data);
  end
  repeat (2) @(posedge clock);
end
endtask

`ifdef GL

wire        wbd_spi_stb_i   = u_top.u_qspi_master.wbd_stb_i;
wire        wbd_spi_ack_o   = u_top.u_qspi_master.wbd_ack_o;
wire        wbd_spi_we_i    = u_top.u_qspi_master.wbd_we_i;
wire [31:0] wbd_spi_adr_i   = u_top.u_qspi_master.wbd_adr_i;
wire [31:0] wbd_spi_dat_i   = u_top.u_qspi_master.wbd_dat_i;
wire [31:0] wbd_spi_dat_o   = u_top.u_qspi_master.wbd_dat_o;
wire [3:0]  wbd_spi_sel_i   = u_top.u_qspi_master.wbd_sel_i;

wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb_spi.reg_cs;
wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb_spi.reg_ack;
wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb_spi.reg_wr;
wire [8:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb_spi.reg_addr;
wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb_spi.reg_wdata;
wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb_spi.reg_rdata;
wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb_spi.reg_be;

`endif


endmodule
module user_risc_boot_tb;

	reg clock;
	reg wb_rst_i;
	reg power1, power2;
	reg power3, power4;

        reg        wbd_ext_cyc_i;
        reg        wbd_ext_stb_i;
        reg [31:0] wbd_ext_adr_i;
        reg        wbd_ext_we_i;
        reg [31:0] wbd_ext_dat_i;
        reg [3:0]  wbd_ext_sel_i;

        wire [31:0] wbd_ext_dat_o;
        wire        wbd_ext_ack_o;
        wire        wbd_ext_err_o;


	wire [37:0] io_oeb;
	wire [37:0] io_out;
	wire [37:0] io_in;

	wire gpio;
	wire [37:0] mprj_io;
	wire [7:0] mprj_io_0;
	reg         test_fail;
	reg [31:0] read_data;







	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
                wbd_ext_cyc_i ='h0;
                wbd_ext_stb_i ='h0;
                wbd_ext_adr_i ='h0;
                wbd_ext_we_i  ='h0;
                wbd_ext_dat_i ='h0;
                wbd_ext_sel_i ='h0;
	end

	`ifdef WFDUMP
	   initial begin
	   	$dumpfile("simx.vcd");
	   	$dumpvars(3, user_risc_boot_tb);
	   end
       `endif

	initial begin

		#200;
	        repeat (10) @(posedge clock);
		$display("Monitor: Standalone User Risc Boot Test Started");


		wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);

	        repeat (2) @(posedge clock);
		#1;

                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);



		repeat (30) begin
			repeat (1000) @(posedge clock);

		end


		$display("Monitor: Reading Back the expected value");









                test_fail = 0;
		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344);
		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455);
		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566);
		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677);
		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788);
		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899);


	   
	    	$display("###################################################");
          	if(test_fail == 0) begin
		   `ifdef GL
	    	       $display("Monitor: Standalone User Risc Boot (GL) Passed");
		   `else
		       $display("Monitor: Standalone User Risc Boot (RTL) Passed");
		   `endif
	        end else begin
		    `ifdef GL
	    	        $display("Monitor: Standalone User Risc Boot (GL) Failed");
		    `else
		        $display("Monitor: Standalone User Risc Boot (RTL) Failed");
		    `endif
		 end
	    	$display("###################################################");
	    $finish;
	end

	initial begin
		wb_rst_i <= 1'b1;
		#100;
		wb_rst_i <= 1'b0;
	end
wire USER_VDD1V8 = 1'b1;
wire VSS = 1'b0;

user_project_wrapper u_top(
`ifdef USE_POWER_PINS
    .vccd1(USER_VDD1V8),
    .vssd1(VSS),
`endif
    .wb_clk_i        (clock),
    .user_clock2     (1'b1),
    .wb_rst_i        (wb_rst_i),

    .wbs_cyc_i   (wbd_ext_cyc_i),
    .wbs_stb_i   (wbd_ext_stb_i),
    .wbs_adr_i   (wbd_ext_adr_i),
    .wbs_we_i    (wbd_ext_we_i),
    .wbs_dat_i   (wbd_ext_dat_i),
    .wbs_sel_i   (wbd_ext_sel_i),

    .wbs_dat_o   (wbd_ext_dat_o),
    .wbs_ack_o   (wbd_ext_ack_o),

 

    .la_data_in      ('1) ,
    .la_data_out     (),
    .la_oenb         ('0),
 


    .io_in          (io_in)  ,
    .io_out         (io_out) ,
    .io_oeb         (io_oeb) ,

    .user_irq       () 

);

`ifndef GL

    initial begin

    end
`endif    






   wire flash_clk = io_out[24];
   wire flash_csb = io_out[25];

   wire #1 io_oeb_29 = io_oeb[29];
   wire #1 io_oeb_30 = io_oeb[30];
   wire #1 io_oeb_31 = io_oeb[31];
   wire #1 io_oeb_32 = io_oeb[32];
   tri  #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz;
   tri  #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz;
   tri  #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz;
   tri  #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz;

   assign io_in[29] = flash_io0;
   assign io_in[30] = flash_io1;
   assign io_in[31] = flash_io2;
   assign io_in[32] = flash_io3;


     s25fl256s #(.mem_file_name("user_risc_boot.hex"),
	         .otp_file_name("none"),
                 .TimingModel("S25FL512SAGMFI010_F_30pF")) 
		 u_spi_flash_256mb (

       .SI      (flash_io0),
       .SO      (flash_io1),

       .SCK     (flash_clk),
       .CSNeg   (flash_csb),
       .WPNeg   (flash_io2),
       .HOLDNeg (flash_io3),
       .RSTNeg  (!wb_rst_i)

       );




task wb_user_core_write;
input [31:0] address;
input [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h1;
  wbd_ext_dat_i =data;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read;
input [31:0] address;
output [31:0] data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(negedge clock);
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read_check;
input [31:0] address;
output [31:0] data;
input [31:0] cmp_data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(negedge clock);
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  if(data !== cmp_data) begin
     $display("ERROR : WB USER ACCESS READ  Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
     test_fail = 1;
  end else begin
     $display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,data);
  end
  repeat (2) @(posedge clock);
end
endtask

`ifdef GL

wire        wbd_spi_stb_i   = u_top.u_qspi_master.wbd_stb_i;
wire        wbd_spi_ack_o   = u_top.u_qspi_master.wbd_ack_o;
wire        wbd_spi_we_i    = u_top.u_qspi_master.wbd_we_i;
wire [31:0] wbd_spi_adr_i   = u_top.u_qspi_master.wbd_adr_i;
wire [31:0] wbd_spi_dat_i   = u_top.u_qspi_master.wbd_dat_i;
wire [31:0] wbd_spi_dat_o   = u_top.u_qspi_master.wbd_dat_o;
wire [3:0]  wbd_spi_sel_i   = u_top.u_qspi_master.wbd_sel_i;

wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb_spi.reg_cs;
wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb_spi.reg_ack;
wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb_spi.reg_wr;
wire [8:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb_spi.reg_addr;
wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb_spi.reg_wdata;
wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb_spi.reg_rdata;
wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb_spi.reg_be;

`endif


endmodule