data/full_repos/permissive/518006745/src/btRAM.v
data/verilator_xmls/ace7f26d-2d0a-40e9-b8e7-6cda2bc251f8.xml
module btRAM #(
		parameter DATA_WIDTH = 32,
		parameter DATA_DEPTH = 512
	) (
		input wire [$clog2(DATA_DEPTH)-1:0] address,
		input wire [3:0] byteena,
		input wire clock,
		input wire [DATA_WIDTH-1:0] data,
		input wire wren,
		output reg [DATA_WIDTH-1:0] q
	);


	reg [DATA_WIDTH-1:0] MEM [DATA_DEPTH-1:0];


	genvar bytelane;
	generate
		for (bytelane = 0; bytelane < (DATA_WIDTH / 8); bytelane = bytelane + 1) begin : whatever
			always @(posedge clock) begin
				if (wren && byteena[bytelane]) MEM[address][7+bytelane*8:bytelane*8] <= data[7+bytelane*8:bytelane*8];
			end
		end
	endgenerate
	

	always @(posedge clock) q <= MEM[address];
		
endmodule
module btRAM #(
		parameter DATA_WIDTH = 32,
		parameter DATA_DEPTH = 512
	) (
		input wire [$clog2(DATA_DEPTH)-1:0] address,
		input wire [3:0] byteena,
		input wire clock,
		input wire [DATA_WIDTH-1:0] data,
		input wire wren,
		output reg [DATA_WIDTH-1:0] q
	);



	reg [DATA_WIDTH-1:0] MEM [DATA_DEPTH-1:0];


	genvar bytelane;
	generate
		for (bytelane = 0; bytelane < (DATA_WIDTH / 8); bytelane = bytelane + 1) begin : whatever
			always @(posedge clock) begin
				if (wren && byteena[bytelane]) MEM[address][7+bytelane*8:bytelane*8] <= data[7+bytelane*8:bytelane*8];
			end
		end
	endgenerate
	

	always @(posedge clock) q <= MEM[address];
		
endmodule