data/full_repos/permissive/458737381/src/verilog-parser/tests/comma_example.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/comma_example.v:19: Unsupported or unknown PLI call: $monitor\n  $monitor ("%g a=%b b=%b c=%b d=%b e=%b sum=%b sum95=%b", \n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/comma_example.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #1 a = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/comma_example.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #1 b = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/comma_example.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #1 c = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/comma_example.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #1 d = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/comma_example.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #1 e = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/comma_example.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #1 $finish;\n  ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module comma_example();

reg a, b, c, d, e;
reg [2:0] sum, sum95;


always @ (a, b, c, d, e)
begin : SUM_V2K
  sum = a + b + c + d + e; 
end


always @ (a or b or c or d or e)
begin : SUM_V95
  sum95 = a + b + c + d + e; 
end

initial begin
  $monitor ("%g a=%b b=%b c=%b d=%b e=%b sum=%b sum95=%b", 
    $time, a, b, c, d, e, sum, sum95);
  #1 a = 1;
  #1 b = 1;
  #1 c = 1;
  #1 d = 1;
  #1 e = 1;
  #1 $finish;
end

endmodule
module comma_example();


reg a, b, c, d, e;
reg [2:0] sum, sum95;


always @ (a, b, c, d, e)
begin : SUM_V2K
  sum = a + b + c + d + e; 
end


always @ (a or b or c or d or e)
begin : SUM_V95
  sum95 = a + b + c + d + e; 
end

initial begin
  $monitor ("%g a=%b b=%b c=%b d=%b e=%b sum=%b sum95=%b", 
    $time, a, b, c, d, e, sum, sum95);
  #1 a = 1;
  #1 b = 1;
  #1 c = 1;
  #1 d = 1;
  #1 e = 1;
  #1 $finish;
end

endmodule