data/full_repos/permissive/505898990/verilog/dv/distance_display/distance_display_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/505898990/verilog/dv/distance_display/distance_display_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n always #12.5 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/505898990/verilog/dv/distance_display/distance_display_tb.v:54: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("distance_display.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/505898990/verilog/dv/distance_display/distance_display_tb.v:55: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, distance_display_tb);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/505898990/verilog/dv/distance_display/distance_display_tb.v:59: syntax error, unexpected \'@\'\n   repeat (2000) @(posedge clock);\n                 ^\n%Error: data/full_repos/permissive/505898990/verilog/dv/distance_display/distance_display_tb.v:92: Unsupported: wait statements\n  wait(display_anode == 4\'b0001);\n  ^~~~\n%Error: data/full_repos/permissive/505898990/verilog/dv/distance_display/distance_display_tb.v:93: Unsupported: wait statements\n  wait(display_anode == 4\'b0010);\n  ^~~~\n%Error: data/full_repos/permissive/505898990/verilog/dv/distance_display/distance_display_tb.v:94: Unsupported: wait statements\n  wait(display_anode == 4\'b0100);\n  ^~~~\n%Error: data/full_repos/permissive/505898990/verilog/dv/distance_display/distance_display_tb.v:95: Unsupported: wait statements\n  wait(display_anode == 4\'b1000);\n  ^~~~\n%Error: data/full_repos/permissive/505898990/verilog/dv/distance_display/distance_display_tb.v:98: Unsupported: wait statements\n  wait(display_cathode == 8\'b11000000);\n  ^~~~\n%Error: data/full_repos/permissive/505898990/verilog/dv/distance_display/distance_display_tb.v:101: Unsupported: wait statements\n  wait(sensor_trigger == 1\'b1);\n  ^~~~\n%Error: data/full_repos/permissive/505898990/verilog/dv/distance_display/distance_display_tb.v:102: Unsupported: wait statements\n  wait(sensor_trigger == 1\'b0);\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/505898990/verilog/dv/distance_display/distance_display_tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n  #2000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/505898990/verilog/dv/distance_display/distance_display_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n  #300000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/505898990/verilog/dv/distance_display/distance_display_tb.v:128: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/505898990/verilog/dv/distance_display/distance_display_tb.v:130: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/505898990/verilog/dv/distance_display/distance_display_tb.v:132: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/505898990/verilog/dv/distance_display/distance_display_tb.v:134: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/505898990/verilog/dv/distance_display/distance_display_tb.v:139: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);\n  ^\n%Error: Exiting due to 10 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module distance_display_tb;
	reg clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

	wire gpio;
	wire [37:0] mprj_io;
	wire [11:0] mprj_io_0;
	wire	    sensor_trigger;
	wire [3:0]  display_anode;
	wire [7:0]  display_cathode;

	assign sensor_trigger = mprj_io[9];
	assign display_anode = mprj_io[13:10];
	assign display_cathode = mprj_io[21:14];


	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;






	always #12.5 clock <= (clock === 1'b0);


	initial begin
		clock = 0;
	end

	initial begin
		$dumpfile("distance_display.vcd");
		$dumpvars(0, distance_display_tb);


		repeat (25) begin
			repeat (2000) @(posedge clock);

		end
		$display("%c[1;31m",27);
		`ifdef GL
			$display ("Monitor: Timeout, Test Mega-Project IO Ports (GL) Failed");
		`else
			$display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed");
		`endif
		$display("%c[0m",27);
		$finish;
	end

	initial begin







		wait(display_anode == 4'b0001);
		wait(display_anode == 4'b0010);
		wait(display_anode == 4'b0100);
		wait(display_anode == 4'b1000);


		wait(display_cathode == 8'b11000000);


		wait(sensor_trigger == 1'b1);
		wait(sensor_trigger == 1'b0);


		
		`ifdef GL
	    	$display("Monitor: Test 1 Mega-Project IO (GL) Passed");
		`else
		    $display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
		`endif
	    $finish;
	end

	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#300000;
		CSB = 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end

	always @(mprj_io) begin
		#1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
	end

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3;
	wire VDD1V8;
	wire VSS;
	
	assign VDD3V3 = power1;
	assign VDD1V8 = power2;
	assign VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda1_2  (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock    (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("distance_display.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule
module distance_display_tb;

	reg clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

	wire gpio;
	wire [37:0] mprj_io;
	wire [11:0] mprj_io_0;
	wire	    sensor_trigger;
	wire [3:0]  display_anode;
	wire [7:0]  display_cathode;

	assign sensor_trigger = mprj_io[9];
	assign display_anode = mprj_io[13:10];
	assign display_cathode = mprj_io[21:14];


	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;






	always #12.5 clock <= (clock === 1'b0);


	initial begin
		clock = 0;
	end

	initial begin
		$dumpfile("distance_display.vcd");
		$dumpvars(0, distance_display_tb);


		repeat (25) begin
			repeat (2000) @(posedge clock);

		end
		$display("%c[1;31m",27);
		`ifdef GL
			$display ("Monitor: Timeout, Test Mega-Project IO Ports (GL) Failed");
		`else
			$display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed");
		`endif
		$display("%c[0m",27);
		$finish;
	end

	initial begin







		wait(display_anode == 4'b0001);
		wait(display_anode == 4'b0010);
		wait(display_anode == 4'b0100);
		wait(display_anode == 4'b1000);


		wait(display_cathode == 8'b11000000);


		wait(sensor_trigger == 1'b1);
		wait(sensor_trigger == 1'b0);


		
		`ifdef GL
	    	$display("Monitor: Test 1 Mega-Project IO (GL) Passed");
		`else
		    $display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
		`endif
	    $finish;
	end

	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#300000;
		CSB = 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end

	always @(mprj_io) begin
		#1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
	end

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3;
	wire VDD1V8;
	wire VSS;
	
	assign VDD3V3 = power1;
	assign VDD1V8 = power2;
	assign VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda1_2  (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock    (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("distance_display.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule