data/full_repos/permissive/413003984/fpga/c10lp025-dk/VRV1_264_test/OpenHBMC/hbmc_elastic_buf.v
1: b"%Error: data/full_repos/permissive/413003984/fpga/c10lp025-dk/VRV1_264_test/OpenHBMC/hbmc_elastic_buf.v:47: Cannot find file containing module: 'hbmc_arst_sync'\n    hbmc_arst_sync #\n    ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/413003984/fpga/c10lp025-dk/VRV1_264_test/OpenHBMC,data/full_repos/permissive/413003984/hbmc_arst_sync\n             data/full_repos/permissive/413003984/fpga/c10lp025-dk/VRV1_264_test/OpenHBMC,data/full_repos/permissive/413003984/hbmc_arst_sync.v\n             data/full_repos/permissive/413003984/fpga/c10lp025-dk/VRV1_264_test/OpenHBMC,data/full_repos/permissive/413003984/hbmc_arst_sync.sv\n             hbmc_arst_sync\n             hbmc_arst_sync.v\n             hbmc_arst_sync.sv\n             obj_dir/hbmc_arst_sync\n             obj_dir/hbmc_arst_sync.v\n             obj_dir/hbmc_arst_sync.sv\n%Error: data/full_repos/permissive/413003984/fpga/c10lp025-dk/VRV1_264_test/OpenHBMC/hbmc_elastic_buf.v:59: Cannot find file containing module: 'hbmc_arst_sync'\n    hbmc_arst_sync #\n    ^~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module hbmc_elastic_buf #
(
    parameter   DATA_WIDTH = 8
)
(
    input   wire                        arst,
    input   wire                        clk_din,
    input   wire                        clk_dout,
    input   wire    [DATA_WIDTH - 1:0]  din,
    output  reg     [DATA_WIDTH - 1:0]  dout
);



    wire    rst_0;
    wire    rst_1;


    hbmc_arst_sync #
    (
        .C_SYNC_STAGES ( 3 )
    )
    hbmc_arst_sync_inst_0
    (
        .clk   ( clk_din ),
        .arst  ( arst    ),
        .rst   ( rst_0   )
    );


    hbmc_arst_sync #
    (
        .C_SYNC_STAGES ( 3 )
    )
    hbmc_arst_sync_inst_1
    (
        .clk   ( clk_dout ),
        .arst  ( arst     ),
        .rst   ( rst_1    )
    );



    reg     [4:0]               wr_addr;
    reg     [4:0]               rd_addr;
    wire    [DATA_WIDTH - 1:0]  dout_ram;


    always @(posedge clk_din or posedge rst_0) begin
        if (rst_0) begin
            wr_addr <= 5'd2;
        end else begin
            wr_addr <= wr_addr + 1'b1;
        end
    end



    always @(posedge clk_dout or posedge rst_1) begin
        if (rst_1) begin
            rd_addr <= 5'd0;
            dout    <= {DATA_WIDTH{1'b0}};
        end else begin
            rd_addr <= rd_addr + 1'b1;
            dout    <= dout_ram;
        end
    end

































endmodule
module hbmc_elastic_buf #
(
    parameter   DATA_WIDTH = 8
)
(
    input   wire                        arst,
    input   wire                        clk_din,
    input   wire                        clk_dout,
    input   wire    [DATA_WIDTH - 1:0]  din,
    output  reg     [DATA_WIDTH - 1:0]  dout
);




    wire    rst_0;
    wire    rst_1;


    hbmc_arst_sync #
    (
        .C_SYNC_STAGES ( 3 )
    )
    hbmc_arst_sync_inst_0
    (
        .clk   ( clk_din ),
        .arst  ( arst    ),
        .rst   ( rst_0   )
    );


    hbmc_arst_sync #
    (
        .C_SYNC_STAGES ( 3 )
    )
    hbmc_arst_sync_inst_1
    (
        .clk   ( clk_dout ),
        .arst  ( arst     ),
        .rst   ( rst_1    )
    );



    reg     [4:0]               wr_addr;
    reg     [4:0]               rd_addr;
    wire    [DATA_WIDTH - 1:0]  dout_ram;


    always @(posedge clk_din or posedge rst_0) begin
        if (rst_0) begin
            wr_addr <= 5'd2;
        end else begin
            wr_addr <= wr_addr + 1'b1;
        end
    end



    always @(posedge clk_dout or posedge rst_1) begin
        if (rst_1) begin
            rd_addr <= 5'd0;
            dout    <= {DATA_WIDTH{1'b0}};
        end else begin
            rd_addr <= rd_addr + 1'b1;
            dout    <= dout_ram;
        end
    end

































endmodule