data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa/modmult.v
1: b"%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa/modmult.v:174: Cannot find file containing module: 'MUX'\n MUX \n ^~~\n        ... Looked in:\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa,data/full_repos/permissive/486954482/MUX\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa,data/full_repos/permissive/486954482/MUX.v\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa,data/full_repos/permissive/486954482/MUX.sv\n             MUX\n             MUX.v\n             MUX.sv\n             obj_dir/MUX\n             obj_dir/MUX.v\n             obj_dir/MUX.sv\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa/modmult.v:186: Cannot find file containing module: 'MUX'\n MUX \n ^~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa/modmult.v:199: Cannot find file containing module: 'MUX'\n MUX \n ^~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa/modmult.v:214: Cannot find file containing module: 'ADD'\n ADD \n ^~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa/modmult.v:228: Cannot find file containing module: 'COMP'\n COMP\n ^~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa/modmult.v:239: Cannot find file containing module: 'SUB'\n SUB \n ^~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa/modmult.v:251: Cannot find file containing module: 'COMP'\n COMP\n ^~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/rsa/modmult.v:264: Cannot find file containing module: 'SUB'\n SUB \n ^~~\n%Error: Exiting due to 8 error(s)\n"
module modmult
#(
	parameter N 	= 8,
	parameter CC	= N
)
(
	clk,
	rst,
	start,
	x,
	y,
	n,
	o
);

	input			clk;
	input			rst;
	input 			start;
	input 	[N-1:0]	x;
	input 	[N-1:0]	y;
	input 	[N-1:0]	n;

	output 	[N-1:0]	o;

	reg 	[N-1:0]	xreg;


	wire 	[N-1:0]	xin;
	reg 	[N+1:0]	zreg;
	wire 	[N+1:0]	zin[N/CC-1:0];
	wire 	[N+1:0]	zout[N/CC-1:0];


	assign o = zout[N/CC-1][N-1:0];







	assign zin[0] 	= zreg;
	assign xin 		= xreg;


	genvar g;

	generate
	for(g=1;g<N/CC;g=g+1)
	begin:ASSZIN
		assign zin[g] = zout[g-1];
	end
	endgenerate

	generate
	for(g=0;g<N/CC;g=g+1)
	begin:MODMULT_STEP
		modmult_step 
		#(
			.N(N)
		)
		modmult_step_
		(
			.xregN_1(xin[N-1-g]),
			.y(y),
			.n(n),
			.zin(zin[g]),
			.zout(zout[g])
		);
	end
	endgenerate

	generate
	if(CC>1)
		always@(posedge clk or posedge rst)
		begin
			if(rst)
			begin
				zreg <= 0;
				xreg <= 0;
			end
			else if(start)
			begin
				zreg <= 0;
				xreg <= x;
			end
			else
			begin
				zreg <= zout[N/CC-1];
				xreg <= {xin[N-1-N/CC:0], {N/CC{1'b0}}};
			end
		end
	else
		always@(*)
		begin
			zreg <= 0;
			xreg <= x;	
		end
	endgenerate

endmodule
module modmult
#(
	parameter N 	= 8,
	parameter CC	= N
)
(
	clk,
	rst,
	start,
	x,
	y,
	n,
	o
);


	input			clk;
	input			rst;
	input 			start;
	input 	[N-1:0]	x;
	input 	[N-1:0]	y;
	input 	[N-1:0]	n;

	output 	[N-1:0]	o;

	reg 	[N-1:0]	xreg;


	wire 	[N-1:0]	xin;
	reg 	[N+1:0]	zreg;
	wire 	[N+1:0]	zin[N/CC-1:0];
	wire 	[N+1:0]	zout[N/CC-1:0];


	assign o = zout[N/CC-1][N-1:0];







	assign zin[0] 	= zreg;
	assign xin 		= xreg;


	genvar g;

	generate
	for(g=1;g<N/CC;g=g+1)
	begin:ASSZIN
		assign zin[g] = zout[g-1];
	end
	endgenerate

	generate
	for(g=0;g<N/CC;g=g+1)
	begin:MODMULT_STEP
		modmult_step 
		#(
			.N(N)
		)
		modmult_step_
		(
			.xregN_1(xin[N-1-g]),
			.y(y),
			.n(n),
			.zin(zin[g]),
			.zout(zout[g])
		);
	end
	endgenerate

	generate
	if(CC>1)
		always@(posedge clk or posedge rst)
		begin
			if(rst)
			begin
				zreg <= 0;
				xreg <= 0;
			end
			else if(start)
			begin
				zreg <= 0;
				xreg <= x;
			end
			else
			begin
				zreg <= zout[N/CC-1];
				xreg <= {xin[N-1-N/CC:0], {N/CC{1'b0}}};
			end
		end
	else
		always@(*)
		begin
			zreg <= 0;
			xreg <= x;	
		end
	endgenerate

endmodule