data/full_repos/permissive/411838135/rv/boot1.sv
data/verilator_xmls/0749ac82-259c-40a2-af72-7b53dd5e2f68.xml
module bootrom1(input [8:0]addr, output [127:0]data);
	reg [127:0]rdata;assign data=rdata;
	always @(*)
	case (addr)
	9'h0: rdata = 128'h00000000000000000001000195024501;

	endcase
endmodule
module bootrom1(input [8:0]addr, output [127:0]data);

	reg [127:0]rdata;assign data=rdata;
	always @(*)
	case (addr)
	9'h0: rdata = 128'h00000000000000000001000195024501;

	endcase
endmodule