data/full_repos/permissive/485085993/verilog/rtl/memories.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/485085993/verilog/rtl/memories.v:91: Multiple top level modules\n                                                                                 : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                 : ... Top module \'mux_2level_tapbuf_size6_mem\'\nmodule mux_2level_tapbuf_size6_mem(bl,\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                 : ... Top module \'mux_2level_tapbuf_size4_mem\'\nmodule mux_2level_tapbuf_size4_mem(bl,\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                 : ... Top module \'mux_2level_tapbuf_size3_mem\'\nmodule mux_2level_tapbuf_size3_mem(bl,\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                 : ... Top module \'mux_2level_tapbuf_size2_mem\'\nmodule mux_2level_tapbuf_size2_mem(bl,\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                 : ... Top module \'mux_2level_size14_mem\'\nmodule mux_2level_size14_mem(bl,\n       ^~~~~~~~~~~~~~~~~~~~~\n                                                                                 : ... Top module \'mux_1level_tapbuf_size2_mem\'\nmodule mux_1level_tapbuf_size2_mem(bl,\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                 : ... Top module \'lut4_SRAM_mem\'\nmodule lut4_SRAM_mem(bl,\n       ^~~~~~~~~~~~~\n                                                                                 : ... Top module \'GPIO_SRAM_mem\'\nmodule GPIO_SRAM_mem(bl,\n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:580: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_0_ (\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/SRAM\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/SRAM.v\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/SRAM.sv\n             SRAM\n             SRAM.v\n             SRAM.sv\n             obj_dir/SRAM\n             obj_dir/SRAM.v\n             obj_dir/SRAM.sv\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/memories.v:422: Little bit endian vector: MSB < LSB of bit range: 0:15\ninput [0:15] bl;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/memories.v:424: Little bit endian vector: MSB < LSB of bit range: 0:15\ninput [0:15] wl;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/memories.v:426: Little bit endian vector: MSB < LSB of bit range: 0:15\noutput [0:15] mem_out;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/memories.v:428: Little bit endian vector: MSB < LSB of bit range: 0:15\noutput [0:15] mem_outb;\n       ^\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:444: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_0_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:450: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_1_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:456: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_2_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:462: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_3_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:468: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_4_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:474: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_5_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:480: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_6_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:486: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_7_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:492: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_8_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:498: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_9_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:504: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_10_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:510: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_11_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:516: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_12_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:522: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_13_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:528: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_14_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:534: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_15_ (\n ^~~~\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/memories.v:364: Little bit endian vector: MSB < LSB of bit range: 0:2\ninput [0:2] bl;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/memories.v:366: Little bit endian vector: MSB < LSB of bit range: 0:2\ninput [0:2] wl;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/memories.v:368: Little bit endian vector: MSB < LSB of bit range: 0:2\noutput [0:2] mem_out;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/memories.v:370: Little bit endian vector: MSB < LSB of bit range: 0:2\noutput [0:2] mem_outb;\n       ^\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:386: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_0_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:392: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_1_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:398: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_2_ (\n ^~~~\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/memories.v:276: Little bit endian vector: MSB < LSB of bit range: 0:7\ninput [0:7] bl;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/memories.v:278: Little bit endian vector: MSB < LSB of bit range: 0:7\ninput [0:7] wl;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/memories.v:280: Little bit endian vector: MSB < LSB of bit range: 0:7\noutput [0:7] mem_out;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/memories.v:282: Little bit endian vector: MSB < LSB of bit range: 0:7\noutput [0:7] mem_outb;\n       ^\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:298: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_0_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:304: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_1_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:310: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_2_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:316: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_3_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:322: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_4_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:328: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_5_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:334: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_6_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:340: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_7_ (\n ^~~~\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/memories.v:224: Little bit endian vector: MSB < LSB of bit range: 0:1\ninput [0:1] bl;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/memories.v:226: Little bit endian vector: MSB < LSB of bit range: 0:1\ninput [0:1] wl;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/memories.v:228: Little bit endian vector: MSB < LSB of bit range: 0:1\noutput [0:1] mem_out;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/memories.v:230: Little bit endian vector: MSB < LSB of bit range: 0:1\noutput [0:1] mem_outb;\n       ^\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:246: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_0_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:252: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_1_ (\n ^~~~\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/memories.v:172: Little bit endian vector: MSB < LSB of bit range: 0:1\ninput [0:1] bl;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/memories.v:174: Little bit endian vector: MSB < LSB of bit range: 0:1\ninput [0:1] wl;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/memories.v:176: Little bit endian vector: MSB < LSB of bit range: 0:1\noutput [0:1] mem_out;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/memories.v:178: Little bit endian vector: MSB < LSB of bit range: 0:1\noutput [0:1] mem_outb;\n       ^\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:194: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_0_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:200: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_1_ (\n ^~~~\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/memories.v:96: Little bit endian vector: MSB < LSB of bit range: 0:5\ninput [0:5] bl;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/memories.v:98: Little bit endian vector: MSB < LSB of bit range: 0:5\ninput [0:5] wl;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/memories.v:100: Little bit endian vector: MSB < LSB of bit range: 0:5\noutput [0:5] mem_out;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/memories.v:102: Little bit endian vector: MSB < LSB of bit range: 0:5\noutput [0:5] mem_outb;\n       ^\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:118: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_0_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:124: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_1_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:130: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_2_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:136: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_3_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:142: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_4_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:148: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_5_ (\n ^~~~\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/memories.v:20: Little bit endian vector: MSB < LSB of bit range: 0:5\ninput [0:5] bl;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/memories.v:22: Little bit endian vector: MSB < LSB of bit range: 0:5\ninput [0:5] wl;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/memories.v:24: Little bit endian vector: MSB < LSB of bit range: 0:5\noutput [0:5] mem_out;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/memories.v:26: Little bit endian vector: MSB < LSB of bit range: 0:5\noutput [0:5] mem_outb;\n       ^\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:42: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_0_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:48: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_1_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:54: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_2_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:60: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_3_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:66: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_4_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/memories.v:72: Cannot find file containing module: \'SRAM\'\n SRAM SRAM_5_ (\n ^~~~\n%Error: Exiting due to 44 error(s), 29 warning(s)\n'
module mux_2level_tapbuf_size2_mem(bl,
                                   wl,
                                   mem_out,
                                   mem_outb);

input [0:1] bl;

input [0:1] wl;

output [0:1] mem_out;

output [0:1] mem_outb;















	SRAM SRAM_0_ (
		.D(bl[0]),
		.WE(wl[0]),
		.Q(mem_out[0]),
		.QN(mem_outb[0]));

	SRAM SRAM_1_ (
		.D(bl[1]),
		.WE(wl[1]),
		.Q(mem_out[1]),
		.QN(mem_outb[1]));

endmodule
module mux_2level_tapbuf_size2_mem(bl,
                                   wl,
                                   mem_out,
                                   mem_outb);


input [0:1] bl;

input [0:1] wl;

output [0:1] mem_out;

output [0:1] mem_outb;















	SRAM SRAM_0_ (
		.D(bl[0]),
		.WE(wl[0]),
		.Q(mem_out[0]),
		.QN(mem_outb[0]));

	SRAM SRAM_1_ (
		.D(bl[1]),
		.WE(wl[1]),
		.Q(mem_out[1]),
		.QN(mem_outb[1]));

endmodule