data/full_repos/permissive/43858668/final_verilog/src/vcr_vc_alloc_wf.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_vc_alloc_wf.v:37: Cannot find include file: c_functions.v\n`include "c_functions.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v.v\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v.sv\n             c_functions.v\n             c_functions.v.v\n             c_functions.v.sv\n             obj_dir/c_functions.v\n             obj_dir/c_functions.v.v\n             obj_dir/c_functions.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_vc_alloc_wf.v:38: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_vc_alloc_wf.v:39: Cannot find include file: rtr_constants.v\n`include "rtr_constants.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_vc_alloc_wf.v:40: Cannot find include file: vcr_constants.v\n`include "vcr_constants.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_vc_alloc_wf.v:61: Define or directive not defined: \'`WF_ALLOC_TYPE_REP\'\n   parameter wf_alloc_type = `WF_ALLOC_TYPE_REP;\n                             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_vc_alloc_wf.v:61: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter wf_alloc_type = `WF_ALLOC_TYPE_REP;\n                                               ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_vc_alloc_wf.v:63: Define or directive not defined: \'`RESET_TYPE_ASYNC\'\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_vc_alloc_wf.v:63: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                                           ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_vc_alloc_wf.v:224: Define or directive not defined: \'`BINARY_OP_AND\'\n       .prod_op(`BINARY_OP_AND),\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_vc_alloc_wf.v:225: Define or directive not defined: \'`BINARY_OP_OR\'\n       .sum_op(`BINARY_OP_OR))\n               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_vc_alloc_wf.v:295: Define or directive not defined: \'`BINARY_OP_OR\'\n         .op(`BINARY_OP_OR))\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_vc_alloc_wf.v:380: Define or directive not defined: \'`BINARY_OP_OR\'\n         .op(`BINARY_OP_OR))\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_vc_alloc_wf.v:405: Define or directive not defined: \'`BINARY_OP_OR\'\n         .op(`BINARY_OP_OR))\n             ^~~~~~~~~~~~~\n%Error: Exiting due to 13 error(s)\n'
module vcr_vc_alloc_wf
  (clk, reset, active, route_ip_ivc_op, route_ip_ivc_orc, elig_op_ovc, 
   req_ip_ivc, gnt_ip_ivc, sel_ip_ivc_ovc, gnt_op_ovc, sel_op_ovc_ip, 
   sel_op_ovc_ivc);
   
`include "c_functions.v"
`include "c_constants.v"
`include "rtr_constants.v"
`include "vcr_constants.v"
   

   parameter num_message_classes = 2;
   

   parameter num_resource_classes = 2;
   

   localparam num_packet_classes = num_message_classes * num_resource_classes;
   

   parameter num_vcs_per_class = 1;
   

   localparam num_vcs = num_packet_classes * num_vcs_per_class;
   

   parameter num_ports = 5;
   

   parameter wf_alloc_type = `WF_ALLOC_TYPE_REP;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   input clk;
   input reset;
   

   input active;
   

   input [0:num_ports*num_vcs*num_ports-1] route_ip_ivc_op;
   

   input [0:num_ports*num_vcs*num_resource_classes-1] route_ip_ivc_orc;
   

   input [0:num_ports*num_vcs-1] 		      elig_op_ovc;
   

   input [0:num_ports*num_vcs-1] 		      req_ip_ivc;
   

   output [0:num_ports*num_vcs-1] 		      gnt_ip_ivc;
   wire [0:num_ports*num_vcs-1] 		      gnt_ip_ivc;
   

   output [0:num_ports*num_vcs*num_vcs-1] 	      sel_ip_ivc_ovc;
   wire [0:num_ports*num_vcs*num_vcs-1] 	      sel_ip_ivc_ovc;
   

   output [0:num_ports*num_vcs-1] 		      gnt_op_ovc;
   wire [0:num_ports*num_vcs-1] 		      gnt_op_ovc;
   

   output [0:num_ports*num_vcs*num_ports-1] 	      sel_op_ovc_ip;
   wire [0:num_ports*num_vcs*num_ports-1] 	      sel_op_ovc_ip;
   

   output [0:num_ports*num_vcs*num_vcs-1] 	      sel_op_ovc_ivc;
   wire [0:num_ports*num_vcs*num_vcs-1] 	      sel_op_ovc_ivc;
   
   
   generate
      
      genvar 					      mc;
      
      for(mc = 0; mc < num_message_classes; mc = mc + 1)
	begin:mcs
	   



	   
	   wire [0:num_ports*num_resource_classes*
		 num_vcs_per_class-1] req_ip_irc_icvc;
	   
	   wire [0:num_ports*num_resource_classes*num_vcs_per_class*num_ports*
		 num_resource_classes*
		 num_vcs_per_class-1] req_wf_ip_irc_icvc_op_orc_ocvc;
	   
	   wire 		      update_alloc;
	   assign update_alloc = |req_wf_ip_irc_icvc_op_orc_ocvc;
	   
	   wire [0:num_ports*num_resource_classes*num_vcs_per_class*num_ports*
		 num_resource_classes*
		 num_vcs_per_class-1] gnt_wf_ip_irc_icvc_op_orc_ocvc;
	   c_wf_alloc
	     #(.num_ports(num_ports*num_resource_classes*num_vcs_per_class),
	       .num_priorities(1),
	       .skip_empty_diags(1),
	       .wf_alloc_type(wf_alloc_type),
	       .reset_type(reset_type))
	   gnt_wf_ip_irc_icvc_op_orc_ocvc_alloc
	     (.clk(clk),
	      .reset(reset),
	      .active(active),
	      .update(update_alloc),
	      .req_pr(req_wf_ip_irc_icvc_op_orc_ocvc),
	      .gnt_pr(gnt_wf_ip_irc_icvc_op_orc_ocvc),
	      .gnt());
	   
	   



	   
	   genvar 		      ip;
	   
	   for(ip = 0; ip < num_ports; ip = ip + 1)
	     begin:ips
		
		assign req_ip_irc_icvc[ip*num_resource_classes*
				       num_vcs_per_class:
				       (ip+1)*num_resource_classes*
				       num_vcs_per_class-1]
		  = req_ip_ivc[(ip*num_message_classes+mc)*
			       num_resource_classes*num_vcs_per_class:
			       (ip*num_message_classes+mc+1)*
			       num_resource_classes*num_vcs_per_class-1];
		
		genvar irc;
		
		for(irc = 0; irc < num_resource_classes; irc = irc + 1)
		  begin:ircs
		     
		     genvar icvc;
		     
		     for(icvc = 0; icvc < num_vcs_per_class; icvc = icvc + 1)
		       begin:icvcs
			  
			  wire req;
			  assign req = req_ip_ivc[ip*num_vcs+
						  (mc*num_resource_classes+irc)*
						  num_vcs_per_class+icvc];
			  
			  wire [0:num_ports-1] route_op;
			  assign route_op
			    = route_ip_ivc_op[(ip*num_vcs+
					       (mc*num_resource_classes+irc)*
					       num_vcs_per_class+icvc)*
					      num_ports:
					      (ip*num_vcs+
					       (mc*num_resource_classes+irc)*
					       num_vcs_per_class+icvc+1)*
					      num_ports-1];
			  
			  wire [0:num_resource_classes-1] route_orc;
			  if(irc == (num_resource_classes - 1))
			    assign route_orc = 'd1;
			  else
			    assign route_orc
			      = route_ip_ivc_orc[(((ip*num_message_classes+mc)*
						   num_resource_classes+irc)*
						  num_vcs_per_class+icvc)*
						 num_resource_classes:
						 (((ip*num_message_classes+mc)*
						   num_resource_classes+irc)*
						  num_vcs_per_class+icvc+1)*
						 num_resource_classes-1];
			  
			  wire [0:num_ports*num_resource_classes*
				num_vcs_per_class-1] 	  req_wf_op_orc_ocvc;
			  
			  genvar 			  op;
			  
			  for(op = 0; op < num_ports; op = op + 1)
			    begin:ops
			       
			       wire route;
			       assign route = route_op[op];
			       
			       wire [0:num_resource_classes-1] sel_orc;
			       assign sel_orc
				 = {num_resource_classes{req & route}} &
				   route_orc;
			       
			       wire [0:num_resource_classes*
				     num_vcs_per_class-1]      sel_orc_ocvc;
			       c_mat_mult
				 #(.dim1_width(num_resource_classes),
				   .dim2_width(1),
				   .dim3_width(num_vcs_per_class),
				   .prod_op(`BINARY_OP_AND),
				   .sum_op(`BINARY_OP_OR))
			       sel_orc_ocvc_mmult
				 (.input_a(sel_orc),
				  .input_b({num_vcs_per_class{1'b1}}),
				  .result(sel_orc_ocvc));
			       
			       wire [0:num_vcs-1] 	       sel_ovc;
			       c_align
				 #(.in_width(num_resource_classes*
					     num_vcs_per_class),
				   .out_width(num_vcs),
				   .offset(mc*num_resource_classes*
					   num_vcs_per_class))
			       sel_ovc_agn
				 (.data_in(sel_orc_ocvc),
				  .dest_in({num_vcs{1'b0}}),
				  .data_out(sel_ovc));
			       
			       wire [0:num_resource_classes*
				     num_vcs_per_class-1]      elig_orc_ocvc;
			       assign elig_orc_ocvc
				 = elig_op_ovc[(op*num_message_classes+mc)*
					       num_resource_classes*
					       num_vcs_per_class:
					       (op*num_message_classes+mc+1)*
					       num_resource_classes*
					       num_vcs_per_class-1];
			       
			       wire [0:num_resource_classes*
				     num_vcs_per_class-1]      req_wf_orc_ocvc;
			       assign req_wf_orc_ocvc
				 = sel_orc_ocvc & elig_orc_ocvc;
			       
			       assign req_wf_op_orc_ocvc[op*
							 num_resource_classes*
							 num_vcs_per_class:
							 (op+1)*
							 num_resource_classes*
							 num_vcs_per_class-1]
				 = req_wf_orc_ocvc;
			       
			    end
			  
			  assign req_wf_ip_irc_icvc_op_orc_ocvc
			    [((ip*num_resource_classes+irc)*
			      num_vcs_per_class+icvc)*
			     num_ports*num_resource_classes*num_vcs_per_class:
			     ((ip*num_resource_classes+irc)*
			      num_vcs_per_class+icvc+1)*
			     num_ports*num_resource_classes*num_vcs_per_class-1]
			    = req_wf_op_orc_ocvc;
			  
			  wire [0:num_ports*num_resource_classes*
				num_vcs_per_class-1] gnt_wf_op_orc_ocvc;
			  assign gnt_wf_op_orc_ocvc
			    = gnt_wf_ip_irc_icvc_op_orc_ocvc
			      [((ip*num_resource_classes+irc)*
				num_vcs_per_class+icvc)*
			       num_ports*num_resource_classes*
			       num_vcs_per_class:
			       ((ip*num_resource_classes+irc)*
				num_vcs_per_class+icvc+1)*
			       num_ports*num_resource_classes*
			       num_vcs_per_class-1];
			  
			  wire [0:num_resource_classes*
				num_vcs_per_class-1] gnt_wf_orc_ocvc;
			  c_binary_op
			    #(.num_ports(num_ports),
			      .width(num_resource_classes*num_vcs_per_class),
			      .op(`BINARY_OP_OR))
			  gnt_wf_orc_ocvc_or
			    (.data_in(gnt_wf_op_orc_ocvc),
			     .data_out(gnt_wf_orc_ocvc));
			  
			  wire [0:num_vcs-1] 	     gnt_wf_ovc;
			  c_align
			    #(.in_width(num_resource_classes*num_vcs_per_class),
			      .out_width(num_vcs),
			      .offset(mc*num_resource_classes*
				      num_vcs_per_class))
			  gnt_wf_ovc_agn
			    (.data_in(gnt_wf_orc_ocvc),
			     .dest_in({num_vcs{1'b0}}),
			     .data_out(gnt_wf_ovc));
			  
			  assign sel_ip_ivc_ovc[(ip*num_vcs+
						 (mc*num_resource_classes+irc)*
						 num_vcs_per_class+icvc)*
						num_vcs:
						(ip*num_vcs+
						 (mc*num_resource_classes+irc)*
						 num_vcs_per_class+icvc+1)*
						num_vcs-1]
			    = gnt_wf_ovc;
			  
			  assign gnt_ip_ivc[ip*num_vcs+
					    (mc*num_resource_classes+irc)*
					    num_vcs_per_class+icvc]
			    = |gnt_wf_ovc;
			  
		       end
		     
		  end
		
	     end
	   
	   



	   
	   wire [0:num_ports*num_resource_classes*num_vcs_per_class*num_ports*
		 num_resource_classes*
		 num_vcs_per_class-1] gnt_wf_op_orc_ocvc_ip_irc_icvc;
	   c_interleave
	     #(.width(num_ports*num_resource_classes*num_vcs_per_class*
		      num_ports*num_resource_classes*num_vcs_per_class),
	       .num_blocks(num_ports*num_resource_classes*num_vcs_per_class))
	   gnt_wf_op_orc_ocvc_ip_irc_icvc_intl
	     (.data_in(gnt_wf_ip_irc_icvc_op_orc_ocvc),
	      .data_out(gnt_wf_op_orc_ocvc_ip_irc_icvc));
	   
	   genvar 		      op;
	   
	   for(op = 0; op < num_ports; op = op + 1)
	     begin:ops
		
		genvar orc;
		
		for(orc = 0; orc < num_resource_classes; orc = orc + 1)
		  begin:orcs
		     
		     genvar ocvc;
		     
		     for(ocvc = 0; ocvc < num_vcs_per_class; ocvc = ocvc + 1)
		       begin:ocvcs
			  
			  wire [0:num_ports*num_resource_classes*
				num_vcs_per_class-1] gnt_wf_ip_irc_icvc;
			  assign gnt_wf_ip_irc_icvc
			    = gnt_wf_op_orc_ocvc_ip_irc_icvc
			      [((op*num_resource_classes+orc)*
				num_vcs_per_class+ocvc)*
			       num_ports*num_resource_classes*
			       num_vcs_per_class:
			       ((op*num_resource_classes+orc)*
				num_vcs_per_class+ocvc+1)*
			       num_ports*num_resource_classes*
			       num_vcs_per_class-1];
			  
			  wire [0:num_ports-1] 	     gnt_wf_ip;
			  c_reduce_bits
			    #(.num_ports(num_ports),
			      .width(num_resource_classes*num_vcs_per_class),
			      .op(`BINARY_OP_OR))
			  gnt_wf_ip_rb
			    (.data_in(gnt_wf_ip_irc_icvc),
			     .data_out(gnt_wf_ip));
			  
			  assign sel_op_ovc_ip[(op*num_vcs+
						(mc*num_resource_classes+orc)*
						num_vcs_per_class+ocvc)*
					       num_ports:
					       (op*num_vcs+
						(mc*num_resource_classes+orc)*
						num_vcs_per_class+ocvc+1)*
					       num_ports-1]
			    = gnt_wf_ip;
			  
			  assign gnt_op_ovc[op*num_vcs+
					    (mc*num_resource_classes+orc)*
					    num_vcs_per_class+ocvc]
			    = |gnt_wf_ip;
			  
			  wire [0:num_resource_classes*
				num_vcs_per_class-1] gnt_wf_irc_icvc;
			  c_binary_op
			    #(.num_ports(num_ports),
			      .width(num_resource_classes*num_vcs_per_class),
			      .op(`BINARY_OP_OR))
			  gnt_wf_irc_icvc_or
			    (.data_in(gnt_wf_ip_irc_icvc),
			     .data_out(gnt_wf_irc_icvc));
			  
			  wire [0:num_vcs-1] 	     gnt_wf_ivc;
			  c_align
			    #(.in_width(num_resource_classes*num_vcs_per_class),
			      .out_width(num_vcs),
			      .offset(mc*num_resource_classes*
				      num_vcs_per_class))
			  gnt_wf_ivc_alg
			    (.data_in(gnt_wf_irc_icvc),
			     .dest_in({num_vcs{1'b0}}),
			     .data_out(gnt_wf_ivc));
			  
			  assign sel_op_ovc_ivc[(op*num_vcs+
						 (mc*num_resource_classes+orc)*
						num_vcs_per_class+ocvc)*
						num_vcs:
						(op*num_vcs+
						 (mc*num_resource_classes+orc)*
						 num_vcs_per_class+ocvc+1)*
						num_vcs-1]
			    = gnt_wf_ivc;
			  
		       end
		     
		  end
		
	     end
	   
	end
      
   endgenerate
   
endmodule
module vcr_vc_alloc_wf
  (clk, reset, active, route_ip_ivc_op, route_ip_ivc_orc, elig_op_ovc, 
   req_ip_ivc, gnt_ip_ivc, sel_ip_ivc_ovc, gnt_op_ovc, sel_op_ovc_ip, 
   sel_op_ovc_ivc);

   
`include "c_functions.v"
`include "c_constants.v"
`include "rtr_constants.v"
`include "vcr_constants.v"
   

   parameter num_message_classes = 2;
   

   parameter num_resource_classes = 2;
   

   localparam num_packet_classes = num_message_classes * num_resource_classes;
   

   parameter num_vcs_per_class = 1;
   

   localparam num_vcs = num_packet_classes * num_vcs_per_class;
   

   parameter num_ports = 5;
   

   parameter wf_alloc_type = `WF_ALLOC_TYPE_REP;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   input clk;
   input reset;
   

   input active;
   

   input [0:num_ports*num_vcs*num_ports-1] route_ip_ivc_op;
   

   input [0:num_ports*num_vcs*num_resource_classes-1] route_ip_ivc_orc;
   

   input [0:num_ports*num_vcs-1] 		      elig_op_ovc;
   

   input [0:num_ports*num_vcs-1] 		      req_ip_ivc;
   

   output [0:num_ports*num_vcs-1] 		      gnt_ip_ivc;
   wire [0:num_ports*num_vcs-1] 		      gnt_ip_ivc;
   

   output [0:num_ports*num_vcs*num_vcs-1] 	      sel_ip_ivc_ovc;
   wire [0:num_ports*num_vcs*num_vcs-1] 	      sel_ip_ivc_ovc;
   

   output [0:num_ports*num_vcs-1] 		      gnt_op_ovc;
   wire [0:num_ports*num_vcs-1] 		      gnt_op_ovc;
   

   output [0:num_ports*num_vcs*num_ports-1] 	      sel_op_ovc_ip;
   wire [0:num_ports*num_vcs*num_ports-1] 	      sel_op_ovc_ip;
   

   output [0:num_ports*num_vcs*num_vcs-1] 	      sel_op_ovc_ivc;
   wire [0:num_ports*num_vcs*num_vcs-1] 	      sel_op_ovc_ivc;
   
   
   generate
      
      genvar 					      mc;
      
      for(mc = 0; mc < num_message_classes; mc = mc + 1)
	begin:mcs
	   



	   
	   wire [0:num_ports*num_resource_classes*
		 num_vcs_per_class-1] req_ip_irc_icvc;
	   
	   wire [0:num_ports*num_resource_classes*num_vcs_per_class*num_ports*
		 num_resource_classes*
		 num_vcs_per_class-1] req_wf_ip_irc_icvc_op_orc_ocvc;
	   
	   wire 		      update_alloc;
	   assign update_alloc = |req_wf_ip_irc_icvc_op_orc_ocvc;
	   
	   wire [0:num_ports*num_resource_classes*num_vcs_per_class*num_ports*
		 num_resource_classes*
		 num_vcs_per_class-1] gnt_wf_ip_irc_icvc_op_orc_ocvc;
	   c_wf_alloc
	     #(.num_ports(num_ports*num_resource_classes*num_vcs_per_class),
	       .num_priorities(1),
	       .skip_empty_diags(1),
	       .wf_alloc_type(wf_alloc_type),
	       .reset_type(reset_type))
	   gnt_wf_ip_irc_icvc_op_orc_ocvc_alloc
	     (.clk(clk),
	      .reset(reset),
	      .active(active),
	      .update(update_alloc),
	      .req_pr(req_wf_ip_irc_icvc_op_orc_ocvc),
	      .gnt_pr(gnt_wf_ip_irc_icvc_op_orc_ocvc),
	      .gnt());
	   
	   



	   
	   genvar 		      ip;
	   
	   for(ip = 0; ip < num_ports; ip = ip + 1)
	     begin:ips
		
		assign req_ip_irc_icvc[ip*num_resource_classes*
				       num_vcs_per_class:
				       (ip+1)*num_resource_classes*
				       num_vcs_per_class-1]
		  = req_ip_ivc[(ip*num_message_classes+mc)*
			       num_resource_classes*num_vcs_per_class:
			       (ip*num_message_classes+mc+1)*
			       num_resource_classes*num_vcs_per_class-1];
		
		genvar irc;
		
		for(irc = 0; irc < num_resource_classes; irc = irc + 1)
		  begin:ircs
		     
		     genvar icvc;
		     
		     for(icvc = 0; icvc < num_vcs_per_class; icvc = icvc + 1)
		       begin:icvcs
			  
			  wire req;
			  assign req = req_ip_ivc[ip*num_vcs+
						  (mc*num_resource_classes+irc)*
						  num_vcs_per_class+icvc];
			  
			  wire [0:num_ports-1] route_op;
			  assign route_op
			    = route_ip_ivc_op[(ip*num_vcs+
					       (mc*num_resource_classes+irc)*
					       num_vcs_per_class+icvc)*
					      num_ports:
					      (ip*num_vcs+
					       (mc*num_resource_classes+irc)*
					       num_vcs_per_class+icvc+1)*
					      num_ports-1];
			  
			  wire [0:num_resource_classes-1] route_orc;
			  if(irc == (num_resource_classes - 1))
			    assign route_orc = 'd1;
			  else
			    assign route_orc
			      = route_ip_ivc_orc[(((ip*num_message_classes+mc)*
						   num_resource_classes+irc)*
						  num_vcs_per_class+icvc)*
						 num_resource_classes:
						 (((ip*num_message_classes+mc)*
						   num_resource_classes+irc)*
						  num_vcs_per_class+icvc+1)*
						 num_resource_classes-1];
			  
			  wire [0:num_ports*num_resource_classes*
				num_vcs_per_class-1] 	  req_wf_op_orc_ocvc;
			  
			  genvar 			  op;
			  
			  for(op = 0; op < num_ports; op = op + 1)
			    begin:ops
			       
			       wire route;
			       assign route = route_op[op];
			       
			       wire [0:num_resource_classes-1] sel_orc;
			       assign sel_orc
				 = {num_resource_classes{req & route}} &
				   route_orc;
			       
			       wire [0:num_resource_classes*
				     num_vcs_per_class-1]      sel_orc_ocvc;
			       c_mat_mult
				 #(.dim1_width(num_resource_classes),
				   .dim2_width(1),
				   .dim3_width(num_vcs_per_class),
				   .prod_op(`BINARY_OP_AND),
				   .sum_op(`BINARY_OP_OR))
			       sel_orc_ocvc_mmult
				 (.input_a(sel_orc),
				  .input_b({num_vcs_per_class{1'b1}}),
				  .result(sel_orc_ocvc));
			       
			       wire [0:num_vcs-1] 	       sel_ovc;
			       c_align
				 #(.in_width(num_resource_classes*
					     num_vcs_per_class),
				   .out_width(num_vcs),
				   .offset(mc*num_resource_classes*
					   num_vcs_per_class))
			       sel_ovc_agn
				 (.data_in(sel_orc_ocvc),
				  .dest_in({num_vcs{1'b0}}),
				  .data_out(sel_ovc));
			       
			       wire [0:num_resource_classes*
				     num_vcs_per_class-1]      elig_orc_ocvc;
			       assign elig_orc_ocvc
				 = elig_op_ovc[(op*num_message_classes+mc)*
					       num_resource_classes*
					       num_vcs_per_class:
					       (op*num_message_classes+mc+1)*
					       num_resource_classes*
					       num_vcs_per_class-1];
			       
			       wire [0:num_resource_classes*
				     num_vcs_per_class-1]      req_wf_orc_ocvc;
			       assign req_wf_orc_ocvc
				 = sel_orc_ocvc & elig_orc_ocvc;
			       
			       assign req_wf_op_orc_ocvc[op*
							 num_resource_classes*
							 num_vcs_per_class:
							 (op+1)*
							 num_resource_classes*
							 num_vcs_per_class-1]
				 = req_wf_orc_ocvc;
			       
			    end
			  
			  assign req_wf_ip_irc_icvc_op_orc_ocvc
			    [((ip*num_resource_classes+irc)*
			      num_vcs_per_class+icvc)*
			     num_ports*num_resource_classes*num_vcs_per_class:
			     ((ip*num_resource_classes+irc)*
			      num_vcs_per_class+icvc+1)*
			     num_ports*num_resource_classes*num_vcs_per_class-1]
			    = req_wf_op_orc_ocvc;
			  
			  wire [0:num_ports*num_resource_classes*
				num_vcs_per_class-1] gnt_wf_op_orc_ocvc;
			  assign gnt_wf_op_orc_ocvc
			    = gnt_wf_ip_irc_icvc_op_orc_ocvc
			      [((ip*num_resource_classes+irc)*
				num_vcs_per_class+icvc)*
			       num_ports*num_resource_classes*
			       num_vcs_per_class:
			       ((ip*num_resource_classes+irc)*
				num_vcs_per_class+icvc+1)*
			       num_ports*num_resource_classes*
			       num_vcs_per_class-1];
			  
			  wire [0:num_resource_classes*
				num_vcs_per_class-1] gnt_wf_orc_ocvc;
			  c_binary_op
			    #(.num_ports(num_ports),
			      .width(num_resource_classes*num_vcs_per_class),
			      .op(`BINARY_OP_OR))
			  gnt_wf_orc_ocvc_or
			    (.data_in(gnt_wf_op_orc_ocvc),
			     .data_out(gnt_wf_orc_ocvc));
			  
			  wire [0:num_vcs-1] 	     gnt_wf_ovc;
			  c_align
			    #(.in_width(num_resource_classes*num_vcs_per_class),
			      .out_width(num_vcs),
			      .offset(mc*num_resource_classes*
				      num_vcs_per_class))
			  gnt_wf_ovc_agn
			    (.data_in(gnt_wf_orc_ocvc),
			     .dest_in({num_vcs{1'b0}}),
			     .data_out(gnt_wf_ovc));
			  
			  assign sel_ip_ivc_ovc[(ip*num_vcs+
						 (mc*num_resource_classes+irc)*
						 num_vcs_per_class+icvc)*
						num_vcs:
						(ip*num_vcs+
						 (mc*num_resource_classes+irc)*
						 num_vcs_per_class+icvc+1)*
						num_vcs-1]
			    = gnt_wf_ovc;
			  
			  assign gnt_ip_ivc[ip*num_vcs+
					    (mc*num_resource_classes+irc)*
					    num_vcs_per_class+icvc]
			    = |gnt_wf_ovc;
			  
		       end
		     
		  end
		
	     end
	   
	   



	   
	   wire [0:num_ports*num_resource_classes*num_vcs_per_class*num_ports*
		 num_resource_classes*
		 num_vcs_per_class-1] gnt_wf_op_orc_ocvc_ip_irc_icvc;
	   c_interleave
	     #(.width(num_ports*num_resource_classes*num_vcs_per_class*
		      num_ports*num_resource_classes*num_vcs_per_class),
	       .num_blocks(num_ports*num_resource_classes*num_vcs_per_class))
	   gnt_wf_op_orc_ocvc_ip_irc_icvc_intl
	     (.data_in(gnt_wf_ip_irc_icvc_op_orc_ocvc),
	      .data_out(gnt_wf_op_orc_ocvc_ip_irc_icvc));
	   
	   genvar 		      op;
	   
	   for(op = 0; op < num_ports; op = op + 1)
	     begin:ops
		
		genvar orc;
		
		for(orc = 0; orc < num_resource_classes; orc = orc + 1)
		  begin:orcs
		     
		     genvar ocvc;
		     
		     for(ocvc = 0; ocvc < num_vcs_per_class; ocvc = ocvc + 1)
		       begin:ocvcs
			  
			  wire [0:num_ports*num_resource_classes*
				num_vcs_per_class-1] gnt_wf_ip_irc_icvc;
			  assign gnt_wf_ip_irc_icvc
			    = gnt_wf_op_orc_ocvc_ip_irc_icvc
			      [((op*num_resource_classes+orc)*
				num_vcs_per_class+ocvc)*
			       num_ports*num_resource_classes*
			       num_vcs_per_class:
			       ((op*num_resource_classes+orc)*
				num_vcs_per_class+ocvc+1)*
			       num_ports*num_resource_classes*
			       num_vcs_per_class-1];
			  
			  wire [0:num_ports-1] 	     gnt_wf_ip;
			  c_reduce_bits
			    #(.num_ports(num_ports),
			      .width(num_resource_classes*num_vcs_per_class),
			      .op(`BINARY_OP_OR))
			  gnt_wf_ip_rb
			    (.data_in(gnt_wf_ip_irc_icvc),
			     .data_out(gnt_wf_ip));
			  
			  assign sel_op_ovc_ip[(op*num_vcs+
						(mc*num_resource_classes+orc)*
						num_vcs_per_class+ocvc)*
					       num_ports:
					       (op*num_vcs+
						(mc*num_resource_classes+orc)*
						num_vcs_per_class+ocvc+1)*
					       num_ports-1]
			    = gnt_wf_ip;
			  
			  assign gnt_op_ovc[op*num_vcs+
					    (mc*num_resource_classes+orc)*
					    num_vcs_per_class+ocvc]
			    = |gnt_wf_ip;
			  
			  wire [0:num_resource_classes*
				num_vcs_per_class-1] gnt_wf_irc_icvc;
			  c_binary_op
			    #(.num_ports(num_ports),
			      .width(num_resource_classes*num_vcs_per_class),
			      .op(`BINARY_OP_OR))
			  gnt_wf_irc_icvc_or
			    (.data_in(gnt_wf_ip_irc_icvc),
			     .data_out(gnt_wf_irc_icvc));
			  
			  wire [0:num_vcs-1] 	     gnt_wf_ivc;
			  c_align
			    #(.in_width(num_resource_classes*num_vcs_per_class),
			      .out_width(num_vcs),
			      .offset(mc*num_resource_classes*
				      num_vcs_per_class))
			  gnt_wf_ivc_alg
			    (.data_in(gnt_wf_irc_icvc),
			     .dest_in({num_vcs{1'b0}}),
			     .data_out(gnt_wf_ivc));
			  
			  assign sel_op_ovc_ivc[(op*num_vcs+
						 (mc*num_resource_classes+orc)*
						num_vcs_per_class+ocvc)*
						num_vcs:
						(op*num_vcs+
						 (mc*num_resource_classes+orc)*
						 num_vcs_per_class+ocvc+1)*
						num_vcs-1]
			    = gnt_wf_ivc;
			  
		       end
		     
		  end
		
	     end
	   
	end
      
   endgenerate
   
endmodule