data/full_repos/permissive/470045893/SupplementaryMaterials/false_path.v
data/verilator_xmls/03eda097-6894-4ba3-bbbe-a3adf51da9cd.xml
module falsepath (A,B,G);

input A,B;

output G;

wire F;

and AND2_1 (F, A, B);
nor OR2_1 (G, F, B);

endmodule
module falsepath (A,B,G);


input A,B;

output G;

wire F;

and AND2_1 (F, A, B);
nor OR2_1 (G, F, B);

endmodule