data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Basic_Gates/47_Another_gate_q4f.v
data/verilator_xmls/28c10bef-ca15-4c1d-ba69-e01a1d18e182.xml
module top_module (
    input in1,
    input in2,
    output out);

    assign out = in1 & (~in2);
endmodule
module top_module (
    input in1,
    input in2,
    output out);


    assign out = in1 & (~in2);
endmodule