data/full_repos/permissive/513306128/ECEN248/up_counter.v
1: b"%Error: data/full_repos/permissive/513306128/ECEN248/up_counter.v:32: Cannot find file containing module: 'half_adder'\n    half_adder add0(Sum[0],Carry[0],En, Count[0]);\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/513306128/ECEN248,data/full_repos/permissive/513306128/half_adder\n             data/full_repos/permissive/513306128/ECEN248,data/full_repos/permissive/513306128/half_adder.v\n             data/full_repos/permissive/513306128/ECEN248,data/full_repos/permissive/513306128/half_adder.sv\n             half_adder\n             half_adder.v\n             half_adder.sv\n             obj_dir/half_adder\n             obj_dir/half_adder.v\n             obj_dir/half_adder.sv\n%Error: data/full_repos/permissive/513306128/ECEN248/up_counter.v:33: Cannot find file containing module: 'half_adder'\n    half_adder add1(Sum[1],Carry[1],Carry[0], Count[1]);\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/513306128/ECEN248/up_counter.v:34: Cannot find file containing module: 'half_adder'\n    half_adder add2(Sum[2],Carry[2],Carry[1],Count[2]);\n    ^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module up_counter(Count, Carry2, En, Clk, Rst);

    output reg [2:0] Count;
    output wire Carry2;
    

    input wire En, Clk, Rst;
    
    wire [2:0] Carry, Sum;
    Threebit_counter UC1(Sum,Carry2,Count,En);

    always@(posedge Clk or posedge Rst)
        if(Rst)
            Count <= 0;
        else
            Count <= Sum;
endmodule
module up_counter(Count, Carry2, En, Clk, Rst);


    output reg [2:0] Count;
    output wire Carry2;
    

    input wire En, Clk, Rst;
    
    wire [2:0] Carry, Sum;
    Threebit_counter UC1(Sum,Carry2,Count,En);

    always@(posedge Clk or posedge Rst)
        if(Rst)
            Count <= 0;
        else
            Count <= Sum;
endmodule