data/full_repos/permissive/506562943/DigitalCircuits/4-1-bit-full-adder/rtl/full_adder.v
data/verilator_xmls/96f84394-7e97-42a1-b760-db1e7f99aecf.xml
module full_adder (
	input a, b, ci,
	output so, co
 );
 

 assign so = a ^ b ^ ci;
 assign co = (a & b) | ((a ^ b) & ci);
 
 endmodule
module full_adder (
	input a, b, ci,
	output so, co
 );

 

 assign so = a ^ b ^ ci;
 assign co = (a & b) | ((a ^ b) & ci);
 
 endmodule