data/full_repos/permissive/529618104/sim/testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/529618104/sim/testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #50;  \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/529618104/sim/testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #10_000_000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/529618104/sim/testbench.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #5 clk = !clk;  \n    ^\n%Error: data/full_repos/permissive/529618104/sim/testbench.v:40: Cannot find file containing module: \'neorv32_verilog_wrapper\'\n  neorv32_verilog_wrapper uut(\n  ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/529618104/sim,data/full_repos/permissive/529618104/neorv32_verilog_wrapper\n             data/full_repos/permissive/529618104/sim,data/full_repos/permissive/529618104/neorv32_verilog_wrapper.v\n             data/full_repos/permissive/529618104/sim,data/full_repos/permissive/529618104/neorv32_verilog_wrapper.sv\n             neorv32_verilog_wrapper\n             neorv32_verilog_wrapper.v\n             neorv32_verilog_wrapper.sv\n             obj_dir/neorv32_verilog_wrapper\n             obj_dir/neorv32_verilog_wrapper.v\n             obj_dir/neorv32_verilog_wrapper.sv\n%Error: data/full_repos/permissive/529618104/sim/testbench.v:49: Cannot find file containing module: \'uart_sim_receiver\'\n  uart_sim_receiver #(\n  ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module neorv32_verilog_tb;

  reg clk, nrst;
  wire uart_txd;
  wire [7:0] char_data;
  wire char_valid;



  initial begin
    $display ("neorv32-verilog testbench\n");
    clk = 0;
    nrst = 0;
    #50;
    nrst = 1;
    #10_000_000;

    $display("Simulation terminated!");
    $finish;
  end



  always begin
    #5 clk = !clk;
  end





  neorv32_verilog_wrapper uut(
  .clk_i(clk),
  .rstn_i(nrst),
  .uart0_rxd_i(1'b0),
  .uart0_txd_o(uart_txd)
  );



  uart_sim_receiver #(
    .BAUD_RATE(19200),
    .CLOCK_FREQ(100000000)
  )
  uart_receiver(
    .clk_i(clk),
    .txd_i(uart_txd),
    .data_o(char_data),
    .valid_o(char_valid)
  );



  reg [7:0] char_buffer [0:6];
  integer i;

  always @(posedge clk) begin

    if (char_valid == 1'b1) begin

      for (i=6; i>0; i=i-1) begin
        char_buffer[i-1] <= char_buffer[i];
      end
      char_buffer[6] <= char_data;
    end


    if ((char_buffer[0] == "N") &&
        (char_buffer[1] == "E") &&
        (char_buffer[2] == "O") &&
        (char_buffer[3] == "R") &&
        (char_buffer[4] == "V") &&
        (char_buffer[5] == "3") &&
        (char_buffer[6] == "2")) begin

      $display ("");
      $display("Simulation successful!");
      $finish;
    end
  end

endmodule
module neorv32_verilog_tb;


  reg clk, nrst;
  wire uart_txd;
  wire [7:0] char_data;
  wire char_valid;



  initial begin
    $display ("neorv32-verilog testbench\n");
    clk = 0;
    nrst = 0;
    #50;
    nrst = 1;
    #10_000_000;

    $display("Simulation terminated!");
    $finish;
  end



  always begin
    #5 clk = !clk;
  end





  neorv32_verilog_wrapper uut(
  .clk_i(clk),
  .rstn_i(nrst),
  .uart0_rxd_i(1'b0),
  .uart0_txd_o(uart_txd)
  );



  uart_sim_receiver #(
    .BAUD_RATE(19200),
    .CLOCK_FREQ(100000000)
  )
  uart_receiver(
    .clk_i(clk),
    .txd_i(uart_txd),
    .data_o(char_data),
    .valid_o(char_valid)
  );



  reg [7:0] char_buffer [0:6];
  integer i;

  always @(posedge clk) begin

    if (char_valid == 1'b1) begin

      for (i=6; i>0; i=i-1) begin
        char_buffer[i-1] <= char_buffer[i];
      end
      char_buffer[6] <= char_data;
    end


    if ((char_buffer[0] == "N") &&
        (char_buffer[1] == "E") &&
        (char_buffer[2] == "O") &&
        (char_buffer[3] == "R") &&
        (char_buffer[4] == "V") &&
        (char_buffer[5] == "3") &&
        (char_buffer[6] == "2")) begin

      $display ("");
      $display("Simulation successful!");
      $finish;
    end
  end

endmodule