data/full_repos/permissive/499137621/CheckPoint3_regfile-main/regfile.v
1: b"%Error: data/full_repos/permissive/499137621/CheckPoint3_regfile-main/regfile.v:20: Cannot find file containing module: 'write_port'\n write_port write_p(.ctrl_writeReg(ctrl_writeReg), .ctrl_writeEN(ctrl_writeEnable), .out(write_in));\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/499137621/CheckPoint3_regfile-main,data/full_repos/permissive/499137621/write_port\n             data/full_repos/permissive/499137621/CheckPoint3_regfile-main,data/full_repos/permissive/499137621/write_port.v\n             data/full_repos/permissive/499137621/CheckPoint3_regfile-main,data/full_repos/permissive/499137621/write_port.sv\n             write_port\n             write_port.v\n             write_port.sv\n             obj_dir/write_port\n             obj_dir/write_port.v\n             obj_dir/write_port.sv\n%Error: data/full_repos/permissive/499137621/CheckPoint3_regfile-main/regfile.v:30: Cannot find file containing module: 'reg_32'\n reg_32 reg0(.in(32'b0), .out(Q[0]), .clk(clock), .en(1'b0), .clr(ctrl_reset));\n ^~~~~~\n%Error: data/full_repos/permissive/499137621/CheckPoint3_regfile-main/regfile.v:36: Cannot find file containing module: 'reg_32'\n  reg_32 reg_(.in(data_writeReg), .out(Q[i]), .clk(clock), .en(write_in[i]), .clr(ctrl_reset));\n  ^~~~~~\n%Error: data/full_repos/permissive/499137621/CheckPoint3_regfile-main/regfile.v:42: Cannot find file containing module: '_5to32decoder'\n _5to32decoder _5to32_read_A(decoder_out_A, ctrl_readRegA, 1'b1);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499137621/CheckPoint3_regfile-main/regfile.v:49: Cannot find file containing module: 'tristate_32'\n   tristate_32 tA(data_readRegA, Q[j], decoder_out_A[j]);\n   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/499137621/CheckPoint3_regfile-main/regfile.v:55: Cannot find file containing module: '_5to32decoder'\n _5to32decoder _5to32_read_B(decoder_out_B, ctrl_readRegB, 1'b1);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499137621/CheckPoint3_regfile-main/regfile.v:62: Cannot find file containing module: 'tristate_32'\n   tristate_32 tB(data_readRegB, Q[k], decoder_out_B[k]);\n   ^~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module regfile (
    clock,
    ctrl_writeEnable,
    ctrl_reset, ctrl_writeReg,
    ctrl_readRegA, ctrl_readRegB, data_writeReg,
    data_readRegA, data_readRegB
);

   input clock, ctrl_writeEnable, ctrl_reset;
   input [4:0] ctrl_writeReg, ctrl_readRegA, ctrl_readRegB;
   input [31:0] data_writeReg;

   output [31:0] data_readRegA, data_readRegB;



	wire [31:0] write_in;
	

	write_port write_p(.ctrl_writeReg(ctrl_writeReg), .ctrl_writeEN(ctrl_writeEnable), .out(write_in));
	

	wire [31:0] Q [31:0];
	wire [31:0] decoder_out_A;
	wire [31:0] decoder_out_B;	

	

	
	reg_32 reg0(.in(32'b0), .out(Q[0]), .clk(clock), .en(1'b0), .clr(ctrl_reset));
	
	genvar i;
	
	generate
	for (i=1; i < 32; i = i+1)  begin : generate_block_identifier3
		reg_32 reg_(.in(data_writeReg), .out(Q[i]), .clk(clock), .en(write_in[i]), .clr(ctrl_reset));
	end
	endgenerate
	
	

	_5to32decoder _5to32_read_A(decoder_out_A, ctrl_readRegA, 1'b1);
	
	
	genvar j;
	
	generate
	for (j=0; j < 32; j = j+1)  begin : readA
			tristate_32 tA(data_readRegA, Q[j], decoder_out_A[j]);
	end
	endgenerate
	


	_5to32decoder _5to32_read_B(decoder_out_B, ctrl_readRegB, 1'b1);
	
	
	genvar k;
	
	generate
	for (k=0; k < 32; k = k+1)  begin : readB
			tristate_32 tB(data_readRegB, Q[k], decoder_out_B[k]);
	end
	endgenerate
	
	
	

endmodule
module regfile (
    clock,
    ctrl_writeEnable,
    ctrl_reset, ctrl_writeReg,
    ctrl_readRegA, ctrl_readRegB, data_writeReg,
    data_readRegA, data_readRegB
);


   input clock, ctrl_writeEnable, ctrl_reset;
   input [4:0] ctrl_writeReg, ctrl_readRegA, ctrl_readRegB;
   input [31:0] data_writeReg;

   output [31:0] data_readRegA, data_readRegB;



	wire [31:0] write_in;
	

	write_port write_p(.ctrl_writeReg(ctrl_writeReg), .ctrl_writeEN(ctrl_writeEnable), .out(write_in));
	

	wire [31:0] Q [31:0];
	wire [31:0] decoder_out_A;
	wire [31:0] decoder_out_B;	

	

	
	reg_32 reg0(.in(32'b0), .out(Q[0]), .clk(clock), .en(1'b0), .clr(ctrl_reset));
	
	genvar i;
	
	generate
	for (i=1; i < 32; i = i+1)  begin : generate_block_identifier3
		reg_32 reg_(.in(data_writeReg), .out(Q[i]), .clk(clock), .en(write_in[i]), .clr(ctrl_reset));
	end
	endgenerate
	
	

	_5to32decoder _5to32_read_A(decoder_out_A, ctrl_readRegA, 1'b1);
	
	
	genvar j;
	
	generate
	for (j=0; j < 32; j = j+1)  begin : readA
			tristate_32 tA(data_readRegA, Q[j], decoder_out_A[j]);
	end
	endgenerate
	


	_5to32decoder _5to32_read_B(decoder_out_B, ctrl_readRegB, 1'b1);
	
	
	genvar k;
	
	generate
	for (k=0; k < 32; k = k+1)  begin : readB
			tristate_32 tB(data_readRegB, Q[k], decoder_out_B[k]);
	end
	endgenerate
	
	
	

endmodule