data/full_repos/permissive/455874613/Projects/Module03/FanSpeed.v
1: b'%Warning-WIDTH: data/full_repos/permissive/455874613/Projects/Module03/FanSpeed.v:37: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'speed\' generates 8 bits.\n                                                                                    : ... In instance FanSpeed\n  cycle = speed;\n        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module FanSpeed (
	input        arst     ,
	input        clk      ,
	input  [7:0] speed    ,
	output reg   pwm_data
);

	integer cycle, i = 1, period = 256;
	
	always @(posedge clk or negedge arst)
	begin
		if(~arst) begin
			pwm_data = 0;
			i = 1;
		end
		else begin
		cycle = speed;
		
		if(i%period <= cycle)
			pwm_data = 1;
		else
			pwm_data = 0;
		
		i = i+1;
		end
	end
	
endmodule
module FanSpeed (
	input        arst     ,
	input        clk      ,
	input  [7:0] speed    ,
	output reg   pwm_data
);


	integer cycle, i = 1, period = 256;
	
	always @(posedge clk or negedge arst)
	begin
		if(~arst) begin
			pwm_data = 0;
			i = 1;
		end
		else begin
		cycle = speed;
		
		if(i%period <= cycle)
			pwm_data = 1;
		else
			pwm_data = 0;
		
		i = i+1;
		end
	end
	
endmodule