data/full_repos/permissive/451270484/simple_gates/adder/adder_4/adder_4.v
1: b'%Warning-WIDTH: data/full_repos/permissive/451270484/simple_gates/adder/adder_4/adder_4.v:9: Operator ADD expects 5 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                                           : ... In instance adder_4\nassign {cout, sum} = a + b + cin;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module adder_4(cout, sum, a, b, cin);
output cout;
output [3:0] sum;
input cin;
input [3:0] a, b;

assign {cout, sum} = a + b + cin;

endmodule
module adder_4(cout, sum, a, b, cin);

output cout;
output [3:0] sum;
input cin;
input [3:0] a, b;

assign {cout, sum} = a + b + cin;

endmodule