data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/lib/stdcells_S.v
1: b"%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/lib/stdcells_S.v:418: Can't resolve module reference: '$_XOR_'\n\\$_XOR_ gate1 ( .A(A), .B(C), .Y(t1) );\n        ^~~~~\n%Error: Exiting due to 1 error(s)\n"
module \$__fulladd (A, B, C, X, Y);


input A, B, C;
output X, Y;


wire t1, t2, t3;






\$_XOR_ gate1 ( .A(A), .B(C), .Y(t1) );
\$_XOR_ gate2 ( .A(B), .B(C), .Y(t2) );
\$_AND_ gate3 ( .A(t1), .B(t2), .Y(t3) );
\$_XOR_ gate4 ( .A(t1), .B(B), .Y(Y) );
\$_XOR_ gate5 ( .A(t3), .B(C), .Y(X) );

endmodule
module \$__fulladd (A, B, C, X, Y);



input A, B, C;
output X, Y;


wire t1, t2, t3;






\$_XOR_ gate1 ( .A(A), .B(C), .Y(t1) );
\$_XOR_ gate2 ( .A(B), .B(C), .Y(t2) );
\$_AND_ gate3 ( .A(t1), .B(t2), .Y(t3) );
\$_XOR_ gate4 ( .A(t1), .B(B), .Y(Y) );
\$_XOR_ gate5 ( .A(t3), .B(C), .Y(X) );

endmodule