data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v
1: b'%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:246: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n      case (core_l15_rqtype)\n      ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:246: Operator CASE expects 5 bits on the Case Item, but Case Item\'s CONST \'4\'h1\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n      case (core_l15_rqtype)\n      ^~~~\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:265: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n     core_l15_rqtype = 4\'b0001;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:274: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n     core_l15_rqtype = 4\'b0000;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:278: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n     core_l15_rqtype = 4\'b0000;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:264: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'bw\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n    if (bw) begin\n    ^~\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:290: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n     core_l15_rqtype = 4\'b0001;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:299: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n     core_l15_rqtype = 4\'b0000;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:303: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n     core_l15_rqtype = 4\'b0000;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:289: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'bw\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n    if (bw) begin\n    ^~\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:322: Operator FUNCREF \'sv2v_cast_32_signed\' expects 32 bits on the Function Argument, but Function Argument\'s SIGNED generates 8 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n    3\'b101: mem_out6 = sv2v_cast_32_signed($signed(piton_out[baddr * 8+:8]));\n                       ^~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:323: Operator ADD expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'baddr\' generates 2 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n    3\'b011: mem_out6 = sv2v_cast_32_signed($signed({piton_out[(baddr + 1) * 8+:8], piton_out[baddr * 8+:8]}));\n                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:323: Operator FUNCREF \'sv2v_cast_32_signed\' expects 32 bits on the Function Argument, but Function Argument\'s SIGNED generates 16 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n    3\'b011: mem_out6 = sv2v_cast_32_signed($signed({piton_out[(baddr + 1) * 8+:8], piton_out[baddr * 8+:8]}));\n                       ^~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:326: Operator ADD expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'baddr\' generates 2 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n    3\'b010: mem_out6 = {16\'b0000000000000000, piton_out[(baddr + 1) * 8+:8], piton_out[baddr * 8+:8]};\n                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/mem_wrap.v:313: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                    : ... In instance mem_wrap.piton_fsm\n  if ((core_l15_rqtype == 4\'b0000) & (l15_core_val == 1)) begin\n                       ^~\n%Error: Exiting due to 15 warning(s)\n'
module mem_wrap (
	clk,
	nrst,
	mem_op4,
	op_a4,
	op_b4,
	S_imm4,
	stall_mem,
	dmem_finished,
	mem_l15_rqtype,
	mem_l15_size,
	mem_l15_address,
	mem_l15_data,
	mem_l15_val,
	l15_mem_data_0,
	l15_mem_data_1,
	l15_mem_returntype,
	l15_mem_val,
	l15_mem_ack,
	l15_mem_header_ack,
	mem_l15_req_ack,
	mem_out6,
	memOp_done,
	m_op6,
	ld_addr_misaligned6,
	samo_addr_misaligned6
);
	input wire clk;
	input wire nrst;
	input wire [3:0] mem_op4;
	input wire [31:0] op_a4;
	input wire [31:0] op_b4;
	input wire [31:0] S_imm4;
	input wire stall_mem;
	input wire dmem_finished;
	output wire [4:0] mem_l15_rqtype;
	output wire [2:0] mem_l15_size;
	output wire [31:0] mem_l15_address;
	output wire [63:0] mem_l15_data;
	output wire mem_l15_val;
	input wire [63:0] l15_mem_data_0;
	input wire [63:0] l15_mem_data_1;
	input wire [3:0] l15_mem_returntype;
	input wire l15_mem_val;
	input wire l15_mem_ack;
	input wire l15_mem_header_ack;
	output wire mem_l15_req_ack;
	output wire [31:0] mem_out6;
	output wire memOp_done;
	output wire m_op6;
	output wire ld_addr_misaligned6;
	output wire samo_addr_misaligned6;
	wire [31:0] addr6;
	wire [31:0] data_in6;
	wire [1:0] baddr6;
	wire gwe6;
	wire rd6;
	wire bw06;
	wire bw16;
	wire bw26;
	wire bw36;
	wire addr_misaligned6;
	wire [3:0] mem_op6;
	wire m_rd6;
	mem_decode mem_decode(
		.clk(clk),
		.nrst(nrst),
		.mem_op4(mem_op4),
		.op_a4(op_a4),
		.op_b4(op_b4),
		.S_imm4(S_imm4),
		.stall_mem(stall_mem),
		.dmem_finished(dmem_finished),
		.addr6(addr6),
		.data_in6(data_in6),
		.baddr6(baddr6),
		.gwe6(gwe6),
		.rd6(m_rd6),
		.bw06(bw06),
		.bw16(bw16),
		.bw26(bw26),
		.bw36(bw36),
		.m_op6(m_op6),
		.addr_misaligned6(addr_misaligned6),
		.ld_addr_misaligned6(ld_addr_misaligned6),
		.samo_addr_misaligned6(samo_addr_misaligned6),
		.mem_op6(mem_op6)
	);
	piton_fsm piton_fsm(
		.clk(clk),
		.nrst(nrst),
		.addr6(addr6),
		.data_in6(data_in6),
		.m_rd6(m_rd6),
		.bw06(bw06),
		.bw16(bw16),
		.bw26(bw26),
		.bw36(bw36),
		.m_op6(m_op6),
		.mem_op6(mem_op6),
		.core_l15_rqtype(mem_l15_rqtype),
		.core_l15_size(mem_l15_size),
		.core_l15_address(mem_l15_address),
		.core_l15_data(mem_l15_data),
		.core_l15_val(mem_l15_val),
		.l15_core_data_0(l15_mem_data_0),
		.l15_core_data_1(l15_mem_data_1),
		.l15_core_returntype(l15_mem_returntype),
		.l15_core_val(l15_mem_val),
		.l15_core_ack(l15_mem_ack),
		.l15_core_header_ack(l15_mem_header_ack),
		.core_l15_req_ack(mem_l15_req_ack),
		.mem_out6(mem_out6),
		.memOp_done(memOp_done)
	);
endmodule
module mem_wrap (
	clk,
	nrst,
	mem_op4,
	op_a4,
	op_b4,
	S_imm4,
	stall_mem,
	dmem_finished,
	mem_l15_rqtype,
	mem_l15_size,
	mem_l15_address,
	mem_l15_data,
	mem_l15_val,
	l15_mem_data_0,
	l15_mem_data_1,
	l15_mem_returntype,
	l15_mem_val,
	l15_mem_ack,
	l15_mem_header_ack,
	mem_l15_req_ack,
	mem_out6,
	memOp_done,
	m_op6,
	ld_addr_misaligned6,
	samo_addr_misaligned6
);

	input wire clk;
	input wire nrst;
	input wire [3:0] mem_op4;
	input wire [31:0] op_a4;
	input wire [31:0] op_b4;
	input wire [31:0] S_imm4;
	input wire stall_mem;
	input wire dmem_finished;
	output wire [4:0] mem_l15_rqtype;
	output wire [2:0] mem_l15_size;
	output wire [31:0] mem_l15_address;
	output wire [63:0] mem_l15_data;
	output wire mem_l15_val;
	input wire [63:0] l15_mem_data_0;
	input wire [63:0] l15_mem_data_1;
	input wire [3:0] l15_mem_returntype;
	input wire l15_mem_val;
	input wire l15_mem_ack;
	input wire l15_mem_header_ack;
	output wire mem_l15_req_ack;
	output wire [31:0] mem_out6;
	output wire memOp_done;
	output wire m_op6;
	output wire ld_addr_misaligned6;
	output wire samo_addr_misaligned6;
	wire [31:0] addr6;
	wire [31:0] data_in6;
	wire [1:0] baddr6;
	wire gwe6;
	wire rd6;
	wire bw06;
	wire bw16;
	wire bw26;
	wire bw36;
	wire addr_misaligned6;
	wire [3:0] mem_op6;
	wire m_rd6;
	mem_decode mem_decode(
		.clk(clk),
		.nrst(nrst),
		.mem_op4(mem_op4),
		.op_a4(op_a4),
		.op_b4(op_b4),
		.S_imm4(S_imm4),
		.stall_mem(stall_mem),
		.dmem_finished(dmem_finished),
		.addr6(addr6),
		.data_in6(data_in6),
		.baddr6(baddr6),
		.gwe6(gwe6),
		.rd6(m_rd6),
		.bw06(bw06),
		.bw16(bw16),
		.bw26(bw26),
		.bw36(bw36),
		.m_op6(m_op6),
		.addr_misaligned6(addr_misaligned6),
		.ld_addr_misaligned6(ld_addr_misaligned6),
		.samo_addr_misaligned6(samo_addr_misaligned6),
		.mem_op6(mem_op6)
	);
	piton_fsm piton_fsm(
		.clk(clk),
		.nrst(nrst),
		.addr6(addr6),
		.data_in6(data_in6),
		.m_rd6(m_rd6),
		.bw06(bw06),
		.bw16(bw16),
		.bw26(bw26),
		.bw36(bw36),
		.m_op6(m_op6),
		.mem_op6(mem_op6),
		.core_l15_rqtype(mem_l15_rqtype),
		.core_l15_size(mem_l15_size),
		.core_l15_address(mem_l15_address),
		.core_l15_data(mem_l15_data),
		.core_l15_val(mem_l15_val),
		.l15_core_data_0(l15_mem_data_0),
		.l15_core_data_1(l15_mem_data_1),
		.l15_core_returntype(l15_mem_returntype),
		.l15_core_val(l15_mem_val),
		.l15_core_ack(l15_mem_ack),
		.l15_core_header_ack(l15_mem_header_ack),
		.core_l15_req_ack(mem_l15_req_ack),
		.mem_out6(mem_out6),
		.memOp_done(memOp_done)
	);
endmodule