data/full_repos/permissive/434840709/week14/1/1.v
data/verilator_xmls/10ae271e-934c-4923-982c-d1465bc5ff6a.xml
module top_module(
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    output walk_left,
    output walk_right
);

    reg walk_left_reg=1, walk_right_reg=0;
    always @(posedge clk) begin
        if (areset) begin
            walk_left_reg  <= 1'b1;
            walk_right_reg <= 1'b0;
        end else begin
            if (bump_left + bump_right == 1)begin
                    if (bump_left == 1) begin
                        walk_left_reg  = 0;
                        walk_right_reg = 1;
                    end
                    else begin
                        walk_left_reg  = 1;
                        walk_right_reg = 0;
                    end
            end
            else if (bump_left+bump_right == 2)begin
                    if (walk_left_reg == 1) begin
                        walk_left_reg = 0;
                        walk_right_reg = 1;
                    end
                    else begin
                        walk_left_reg = 1;
                        walk_right_reg = 0;
                    end
            end
        end
    end

    assign walk_left  = walk_left_reg;
    assign walk_right = walk_right_reg;

endmodule
module top_module(
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    output walk_left,
    output walk_right
);


    reg walk_left_reg=1, walk_right_reg=0;
    always @(posedge clk) begin
        if (areset) begin
            walk_left_reg  <= 1'b1;
            walk_right_reg <= 1'b0;
        end else begin
            if (bump_left + bump_right == 1)begin
                    if (bump_left == 1) begin
                        walk_left_reg  = 0;
                        walk_right_reg = 1;
                    end
                    else begin
                        walk_left_reg  = 1;
                        walk_right_reg = 0;
                    end
            end
            else if (bump_left+bump_right == 2)begin
                    if (walk_left_reg == 1) begin
                        walk_left_reg = 0;
                        walk_right_reg = 1;
                    end
                    else begin
                        walk_left_reg = 1;
                        walk_right_reg = 0;
                    end
            end
        end
    end

    assign walk_left  = walk_left_reg;
    assign walk_right = walk_right_reg;

endmodule