data/full_repos/permissive/515100461/sequential/decode_tb.v
1: b'%Error: data/full_repos/permissive/515100461/sequential/decode_tb.v:1: Cannot find include file: fetch.v\n`include "fetch.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/515100461/sequential,data/full_repos/permissive/515100461/fetch.v\n             data/full_repos/permissive/515100461/sequential,data/full_repos/permissive/515100461/fetch.v.v\n             data/full_repos/permissive/515100461/sequential,data/full_repos/permissive/515100461/fetch.v.sv\n             fetch.v\n             fetch.v.v\n             fetch.v.sv\n             obj_dir/fetch.v\n             obj_dir/fetch.v.v\n             obj_dir/fetch.v.sv\n%Error: data/full_repos/permissive/515100461/sequential/decode_tb.v:2: Cannot find include file: execute.v\n`include "execute.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/515100461/sequential/decode_tb.v:3: Cannot find include file: decode.v\n`include "decode.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/515100461/sequential/decode_tb.v:4: Cannot find include file: memory.v\n`include "memory.v" \n         ^~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/decode_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #20 clk=~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/decode_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #20 clk=~clk;PC=valP;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/decode_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #20 clk=~clk;\n    ^\n%Error: data/full_repos/permissive/515100461/sequential/decode_tb.v:41: Unsupported or unknown PLI call: $monitor\n  $monitor("clk=%d PC=%d icode=%b ifun=%b \\nrA=%b rB=%b valA=%d valB=%d valE=%d\\nr4=%d r2=%d\\n",clk,PC,icode,ifun,rA,rB,valA,valB,valE,regmem4,regmem2);\n  ^~~~~~~~\n%Error: Exiting due to 5 error(s), 3 warning(s)\n'
module fdecode_tb;

reg clk;

reg [63:0] reg_mem[0:14];
reg [63:0] PC;
wire [3:0] rA,rB,icode,ifun;
wire signed [63:0] valA,valB,valC,valP,valM,valE;
wire signed [63:0] regmem0,regmem1,regmem2,regmem3,regmem4,regmem5,regmem6,regmem7,regmem8,regmem9,regmem10,regmem11;
wire signed [63:0] regmem12,regmem13,regmem14,regmem15;
wire cnd,hlt;
fetch uut1(clk,PC,icode,ifun,rA,rB,valP,valC,hlt);
execute uut3(icode,ifun,clk,valA,valB,valC,valE,cnd);
decode uut2(icode,clk,rA,rB,cnd,valE,valM,regmem0,regmem1,regmem2,regmem3,regmem4,regmem5,regmem6,regmem7,regmem8,regmem9,regmem10,regmem11,regmem12,regmem13,regmem14,regmem15,valA,valB);
memory uut4(clk,icode,valE,valP,valA,valM);

initial begin



     clk=1;PC=64'd1;
    #20 clk=~clk;
    #20 clk=~clk;PC=valP;
    #20 clk=~clk;








end

initial 

  $monitor("clk=%d PC=%d icode=%b ifun=%b \nrA=%b rB=%b valA=%d valB=%d valE=%d\nr4=%d r2=%d\n",clk,PC,icode,ifun,rA,rB,valA,valB,valE,regmem4,regmem2);

endmodule
module fdecode_tb;


reg clk;

reg [63:0] reg_mem[0:14];
reg [63:0] PC;
wire [3:0] rA,rB,icode,ifun;
wire signed [63:0] valA,valB,valC,valP,valM,valE;
wire signed [63:0] regmem0,regmem1,regmem2,regmem3,regmem4,regmem5,regmem6,regmem7,regmem8,regmem9,regmem10,regmem11;
wire signed [63:0] regmem12,regmem13,regmem14,regmem15;
wire cnd,hlt;
fetch uut1(clk,PC,icode,ifun,rA,rB,valP,valC,hlt);
execute uut3(icode,ifun,clk,valA,valB,valC,valE,cnd);
decode uut2(icode,clk,rA,rB,cnd,valE,valM,regmem0,regmem1,regmem2,regmem3,regmem4,regmem5,regmem6,regmem7,regmem8,regmem9,regmem10,regmem11,regmem12,regmem13,regmem14,regmem15,valA,valB);
memory uut4(clk,icode,valE,valP,valA,valM);

initial begin



     clk=1;PC=64'd1;
    #20 clk=~clk;
    #20 clk=~clk;PC=valP;
    #20 clk=~clk;








end

initial 

  $monitor("clk=%d PC=%d icode=%b ifun=%b \nrA=%b rB=%b valA=%d valB=%d valE=%d\nr4=%d r2=%d\n",clk,PC,icode,ifun,rA,rB,valA,valB,valE,regmem4,regmem2);

endmodule