data/full_repos/permissive/508266496/simulation/CPUTest.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/508266496/simulation/CPUTest.v:29: Unsupported: Ignoring delay on this delayed statement.\n#0 Clock = 1\'b0;  \n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/508266496/simulation/CPUTest.v:30: Unsupported: Ignoring delay on this delayed statement.\n#100 Clock = 1\'b0;  \n^\n%Warning-STMTDLY: data/full_repos/permissive/508266496/simulation/CPUTest.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #5 Clock = ~Clock;\n    ^\n%Error: data/full_repos/permissive/508266496/simulation/CPUTest.v:38: Cannot find file containing module: \'CPU\'\nCPU cpu(Clock);\n^~~\n        ... Looked in:\n             data/full_repos/permissive/508266496/simulation,data/full_repos/permissive/508266496/CPU\n             data/full_repos/permissive/508266496/simulation,data/full_repos/permissive/508266496/CPU.v\n             data/full_repos/permissive/508266496/simulation,data/full_repos/permissive/508266496/CPU.sv\n             CPU\n             CPU.v\n             CPU.sv\n             obj_dir/CPU\n             obj_dir/CPU.v\n             obj_dir/CPU.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module CPUTest();

reg Clock;

initial 
begin
#0 Clock = 1'b0;
#100 Clock = 1'b0;
end

always
begin
    #5 Clock = ~Clock;
end

CPU cpu(Clock);
endmodule
module CPUTest();


reg Clock;

initial 
begin
#0 Clock = 1'b0;
#100 Clock = 1'b0;
end

always
begin
    #5 Clock = ~Clock;
end

CPU cpu(Clock);
endmodule