data/full_repos/permissive/482132588/design/code/pipeline_regs.v
data/verilator_xmls/c781eeae-7b3f-41eb-af9f-26f93cd62767.xml
module pipeline_regs(

    input  wire clock,
    input  wire reset,
    input  wire nop,

    input  wire PCSel_f,
    input  wire PCSel,
    input  wire [1:0] BrUn,
    input  wire RegWEn,
    input  wire BSel,
    input  wire ASel,
    input  wire MemRW,
    input  wire [1:0]WBSel,
    input  wire [3:0]ALUSel,
    input  wire [31:0]IMM,
    input  wire [2:0] func3,
   
    input  wire [31:0] pcDi,
    input  wire [31:0] instDi,
    input  wire [31:0] rs1Xi,
    input  wire [31:0] rs2Xi,
    input  wire [4:0]  addr_Xi,
    input  wire [31:0] aluMi,
    input  wire [31:0] rs2Mi,
    input  wire [31:0] dmemWi,


    
    output reg BSelX,
    output reg ASelX,
    output reg MemRWM,
    output reg PCSelX,
    output reg [1:0]BrUnX,
    output reg PCSelM,
    output reg RegWEnW,
    output reg [1:0]WBSelW,
    output reg [3:0]ALUSelX,
    output reg [2:0] func3_Xo,
    output reg [2:0]func3_Mo,

    output reg [31:0] pcDo,
    output reg [31:0] instDo,
    output reg [31:0] pcXo,
    output reg [31:0] rs1Xo,
    output reg [31:0] rs2Xo,
    output reg [31:0] immXo,
    output reg [31:0] pcMo,
    output reg [31:0] aluMo,
    output reg [31:0] rs2Mo,
    output reg [31:0] dmemWo,
    output reg [4:0]  addr_Wo,
    output reg [31:0] pcWo



);


    
    reg [4:0]  addr_Xo;
    reg [4:0]  addr_Mo;
    
  

   
    reg RegWEnX;
    reg MemRWX;

    

    reg RegWEnM;
    reg [1:0]WBSelM;





  always @(posedge clock or posedge reset) begin

    if(reset) begin

        BSelX <= 0;
        ASelX <= 0;
        MemRWM <= 0;

        RegWEnW <= 0;
        WBSelW <= 0;
        ALUSelX <= 0;
        func3_Xo <= 0;

        PCSelX <= 0;
        BrUnX <= 0;
        RegWEnX <= 0;
        MemRWX <= 0;

        PCSelM <= 0;
        RegWEnM <= 0;
        WBSelM <= 0;
        func3_Mo <= 0;

        instDo <= 0;
        pcXo <= 0;
        rs1Xo <= 0;
        rs2Xo <= 0;
        immXo <= 0;
        pcMo <= 0;
        aluMo <= 0;
        rs2Mo <= 0;
        dmemWo <= 0;
        addr_Wo <= 0;

        pcDo <= 0;
        addr_Xo <= 0;
        addr_Mo <= 0;
        pcWo <= 0;
    




    end
    else if (nop) begin
        

        RegWEnW  <= RegWEnM;
        WBSelW  <= WBSelM;
        pcWo <= pcMo;
    
        MemRWM  <= MemRWX;
        PCSelM  <= PCSelX;
        RegWEnM  <= RegWEnX;
        WBSelM  <= WBSel;
        func3_Mo  <= func3_Xo;     
        
        BSelX  <= 0;
        ASelX  <= 0;
        ALUSelX  <= 0;
        PCSelX  <= 0;
        BrUnX <= 0;
        RegWEnX  <= 0;
        MemRWX  <= 0;


        dmemWo  <= dmemWi;
        addr_Wo  <= addr_Mo;

        pcMo  <= pcXo;
        aluMo  <= aluMi;
        rs2Mo  <= rs2Mi;

        pcXo  <= 0;
        rs1Xo  <= 0;
        rs2Xo  <= 0;
        immXo  <= 0;

 
        addr_Mo  <= addr_Xo;
        addr_Xo  <= 0;
        func3_Xo  <= 0;






    end
    else if (PCSel_f) begin
        

        RegWEnW  <= RegWEnM;
        WBSelW  <= WBSelM;
        pcWo <= pcMo;
    
        MemRWM  <= MemRWX;
        PCSelM  <= PCSelX;
        RegWEnM  <= RegWEnX;
        WBSelM  <= WBSel;
        func3_Mo  <= func3_Xo;     
        
        BSelX  <= 0;
        ASelX  <= 0;
        ALUSelX  <= 0;
        PCSelX  <= 0;
        BrUnX <= 0;
        RegWEnX  <= 0;;
        MemRWX  <= 0;


        dmemWo  <= dmemWi;
        addr_Wo  <= addr_Mo;

        pcMo  <= pcXo;
        aluMo  <= aluMi;
        rs2Mo  <= rs2Mi;

        pcXo  <= 0;
        rs1Xo  <= 0;
        rs2Xo  <= 0;
        immXo  <= 0;

        instDo  <= 0;
        pcDo  <= 0; 
        
        addr_Mo  <= addr_Xo;
        addr_Xo  <= 0;
        func3_Xo  <= 0;
    end

    else begin
    

        RegWEnW  <= RegWEnM;
        WBSelW  <= WBSelM;
        pcWo <= pcMo;
    
        MemRWM  <= MemRWX;
        PCSelM  <= PCSelX;
        RegWEnM  <= RegWEnX;
        WBSelM  <= WBSel;
        func3_Mo  <= func3_Xo;     
        
        BSelX  <= BSel;
        ASelX  <= ASel;
        ALUSelX  <= ALUSel;
        PCSelX  <= PCSel;
        BrUnX <= BrUn;
        RegWEnX  <= RegWEn;
        MemRWX  <= MemRW;


        dmemWo  <= dmemWi;
        addr_Wo  <= addr_Mo;

        pcMo  <= pcXo;
        aluMo  <= aluMi;
        rs2Mo  <= rs2Mi;

        pcXo  <= pcDo;
        rs1Xo  <= rs1Xi;
        rs2Xo  <= rs2Xi;
        immXo  <= IMM;

        instDo  <= instDi;

        pcDo  <= pcDi; 
        addr_Mo  <= addr_Xo;
        addr_Xo  <= addr_Xi;
        func3_Xo  <= func3;

    end


   
   


 end
  

endmodule
module pipeline_regs(

    input  wire clock,
    input  wire reset,
    input  wire nop,

    input  wire PCSel_f,
    input  wire PCSel,
    input  wire [1:0] BrUn,
    input  wire RegWEn,
    input  wire BSel,
    input  wire ASel,
    input  wire MemRW,
    input  wire [1:0]WBSel,
    input  wire [3:0]ALUSel,
    input  wire [31:0]IMM,
    input  wire [2:0] func3,
   
    input  wire [31:0] pcDi,
    input  wire [31:0] instDi,
    input  wire [31:0] rs1Xi,
    input  wire [31:0] rs2Xi,
    input  wire [4:0]  addr_Xi,
    input  wire [31:0] aluMi,
    input  wire [31:0] rs2Mi,
    input  wire [31:0] dmemWi,


    
    output reg BSelX,
    output reg ASelX,
    output reg MemRWM,
    output reg PCSelX,
    output reg [1:0]BrUnX,
    output reg PCSelM,
    output reg RegWEnW,
    output reg [1:0]WBSelW,
    output reg [3:0]ALUSelX,
    output reg [2:0] func3_Xo,
    output reg [2:0]func3_Mo,

    output reg [31:0] pcDo,
    output reg [31:0] instDo,
    output reg [31:0] pcXo,
    output reg [31:0] rs1Xo,
    output reg [31:0] rs2Xo,
    output reg [31:0] immXo,
    output reg [31:0] pcMo,
    output reg [31:0] aluMo,
    output reg [31:0] rs2Mo,
    output reg [31:0] dmemWo,
    output reg [4:0]  addr_Wo,
    output reg [31:0] pcWo



);



    
    reg [4:0]  addr_Xo;
    reg [4:0]  addr_Mo;
    
  

   
    reg RegWEnX;
    reg MemRWX;

    

    reg RegWEnM;
    reg [1:0]WBSelM;





  always @(posedge clock or posedge reset) begin

    if(reset) begin

        BSelX <= 0;
        ASelX <= 0;
        MemRWM <= 0;

        RegWEnW <= 0;
        WBSelW <= 0;
        ALUSelX <= 0;
        func3_Xo <= 0;

        PCSelX <= 0;
        BrUnX <= 0;
        RegWEnX <= 0;
        MemRWX <= 0;

        PCSelM <= 0;
        RegWEnM <= 0;
        WBSelM <= 0;
        func3_Mo <= 0;

        instDo <= 0;
        pcXo <= 0;
        rs1Xo <= 0;
        rs2Xo <= 0;
        immXo <= 0;
        pcMo <= 0;
        aluMo <= 0;
        rs2Mo <= 0;
        dmemWo <= 0;
        addr_Wo <= 0;

        pcDo <= 0;
        addr_Xo <= 0;
        addr_Mo <= 0;
        pcWo <= 0;
    




    end
    else if (nop) begin
        

        RegWEnW  <= RegWEnM;
        WBSelW  <= WBSelM;
        pcWo <= pcMo;
    
        MemRWM  <= MemRWX;
        PCSelM  <= PCSelX;
        RegWEnM  <= RegWEnX;
        WBSelM  <= WBSel;
        func3_Mo  <= func3_Xo;     
        
        BSelX  <= 0;
        ASelX  <= 0;
        ALUSelX  <= 0;
        PCSelX  <= 0;
        BrUnX <= 0;
        RegWEnX  <= 0;
        MemRWX  <= 0;


        dmemWo  <= dmemWi;
        addr_Wo  <= addr_Mo;

        pcMo  <= pcXo;
        aluMo  <= aluMi;
        rs2Mo  <= rs2Mi;

        pcXo  <= 0;
        rs1Xo  <= 0;
        rs2Xo  <= 0;
        immXo  <= 0;

 
        addr_Mo  <= addr_Xo;
        addr_Xo  <= 0;
        func3_Xo  <= 0;






    end
    else if (PCSel_f) begin
        

        RegWEnW  <= RegWEnM;
        WBSelW  <= WBSelM;
        pcWo <= pcMo;
    
        MemRWM  <= MemRWX;
        PCSelM  <= PCSelX;
        RegWEnM  <= RegWEnX;
        WBSelM  <= WBSel;
        func3_Mo  <= func3_Xo;     
        
        BSelX  <= 0;
        ASelX  <= 0;
        ALUSelX  <= 0;
        PCSelX  <= 0;
        BrUnX <= 0;
        RegWEnX  <= 0;;
        MemRWX  <= 0;


        dmemWo  <= dmemWi;
        addr_Wo  <= addr_Mo;

        pcMo  <= pcXo;
        aluMo  <= aluMi;
        rs2Mo  <= rs2Mi;

        pcXo  <= 0;
        rs1Xo  <= 0;
        rs2Xo  <= 0;
        immXo  <= 0;

        instDo  <= 0;
        pcDo  <= 0; 
        
        addr_Mo  <= addr_Xo;
        addr_Xo  <= 0;
        func3_Xo  <= 0;
    end

    else begin
    

        RegWEnW  <= RegWEnM;
        WBSelW  <= WBSelM;
        pcWo <= pcMo;
    
        MemRWM  <= MemRWX;
        PCSelM  <= PCSelX;
        RegWEnM  <= RegWEnX;
        WBSelM  <= WBSel;
        func3_Mo  <= func3_Xo;     
        
        BSelX  <= BSel;
        ASelX  <= ASel;
        ALUSelX  <= ALUSel;
        PCSelX  <= PCSel;
        BrUnX <= BrUn;
        RegWEnX  <= RegWEn;
        MemRWX  <= MemRW;


        dmemWo  <= dmemWi;
        addr_Wo  <= addr_Mo;

        pcMo  <= pcXo;
        aluMo  <= aluMi;
        rs2Mo  <= rs2Mi;

        pcXo  <= pcDo;
        rs1Xo  <= rs1Xi;
        rs2Xo  <= rs2Xi;
        immXo  <= IMM;

        instDo  <= instDi;

        pcDo  <= pcDi; 
        addr_Mo  <= addr_Xo;
        addr_Xo  <= addr_Xi;
        func3_Xo  <= func3;

    end


   
   


 end
  

endmodule