data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:40: Little bit endian vector: MSB < LSB of bit range: 0:12\ninput [0:12] chany_bottom_in;\n      ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:60: Little bit endian vector: MSB < LSB of bit range: 0:12\ninput [0:12] chanx_left_in;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:80: Little bit endian vector: MSB < LSB of bit range: 0:67\ninput [0:67] bl;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:82: Little bit endian vector: MSB < LSB of bit range: 0:67\ninput [0:67] wl;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:84: Little bit endian vector: MSB < LSB of bit range: 0:12\noutput [0:12] chany_bottom_out;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:86: Little bit endian vector: MSB < LSB of bit range: 0:12\noutput [0:12] chanx_left_out;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:96: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size2_0_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:97: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size2_0_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:98: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size2_1_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:99: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size2_1_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:100: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size2_2_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:101: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size2_2_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:102: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size2_3_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:103: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size2_3_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:104: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size2_4_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:105: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size2_4_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:106: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size2_5_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:107: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size2_5_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:108: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size3_0_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:109: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size3_0_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:110: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size3_10_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:111: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size3_10_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:112: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size3_11_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:113: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size3_11_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:114: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size3_12_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:115: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size3_12_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:116: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size3_13_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:117: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size3_13_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:118: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size3_14_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:119: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size3_14_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:120: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size3_15_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:121: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size3_15_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:122: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size3_1_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:123: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size3_1_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:124: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size3_2_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:125: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size3_2_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:126: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size3_3_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:127: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size3_3_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:128: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size3_4_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:129: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size3_4_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:130: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size3_5_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:131: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size3_5_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:132: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size3_6_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:133: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size3_6_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:134: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size3_7_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:135: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size3_7_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:136: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size3_8_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:137: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size3_8_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:138: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size3_9_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:139: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:1] mux_2level_tapbuf_size3_9_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:140: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size4_0_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:141: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size4_0_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:142: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size4_1_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:143: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size4_1_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:144: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size4_2_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:145: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size4_2_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:146: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size4_3_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:147: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size4_3_sram_inv;\n     ^\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:154: Cannot find file containing module: \'mux_2level_tapbuf_size4\'\n mux_2level_tapbuf_size4 mux_bottom_track_1 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/mux_2level_tapbuf_size4\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/mux_2level_tapbuf_size4.v\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/mux_2level_tapbuf_size4.sv\n             mux_2level_tapbuf_size4\n             mux_2level_tapbuf_size4.v\n             mux_2level_tapbuf_size4.sv\n             obj_dir/mux_2level_tapbuf_size4\n             obj_dir/mux_2level_tapbuf_size4.v\n             obj_dir/mux_2level_tapbuf_size4.sv\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:160: Cannot find file containing module: \'mux_2level_tapbuf_size4\'\n mux_2level_tapbuf_size4 mux_bottom_track_13 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:166: Cannot find file containing module: \'mux_2level_tapbuf_size4\'\n mux_2level_tapbuf_size4 mux_left_track_1 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:172: Cannot find file containing module: \'mux_2level_tapbuf_size4\'\n mux_2level_tapbuf_size4 mux_left_track_13 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:178: Cannot find file containing module: \'mux_2level_tapbuf_size4_mem\'\n mux_2level_tapbuf_size4_mem mem_bottom_track_1 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:184: Cannot find file containing module: \'mux_2level_tapbuf_size4_mem\'\n mux_2level_tapbuf_size4_mem mem_bottom_track_13 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:190: Cannot find file containing module: \'mux_2level_tapbuf_size4_mem\'\n mux_2level_tapbuf_size4_mem mem_left_track_1 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:196: Cannot find file containing module: \'mux_2level_tapbuf_size4_mem\'\n mux_2level_tapbuf_size4_mem mem_left_track_13 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:202: Cannot find file containing module: \'mux_2level_tapbuf_size3\'\n mux_2level_tapbuf_size3 mux_bottom_track_3 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:208: Cannot find file containing module: \'mux_2level_tapbuf_size3\'\n mux_2level_tapbuf_size3 mux_bottom_track_5 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:214: Cannot find file containing module: \'mux_2level_tapbuf_size3\'\n mux_2level_tapbuf_size3 mux_bottom_track_7 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:220: Cannot find file containing module: \'mux_2level_tapbuf_size3\'\n mux_2level_tapbuf_size3 mux_bottom_track_9 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:226: Cannot find file containing module: \'mux_2level_tapbuf_size3\'\n mux_2level_tapbuf_size3 mux_bottom_track_11 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:232: Cannot find file containing module: \'mux_2level_tapbuf_size3\'\n mux_2level_tapbuf_size3 mux_bottom_track_15 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:238: Cannot find file containing module: \'mux_2level_tapbuf_size3\'\n mux_2level_tapbuf_size3 mux_bottom_track_17 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:244: Cannot find file containing module: \'mux_2level_tapbuf_size3\'\n mux_2level_tapbuf_size3 mux_bottom_track_25 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:250: Cannot find file containing module: \'mux_2level_tapbuf_size3\'\n mux_2level_tapbuf_size3 mux_left_track_3 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:256: Cannot find file containing module: \'mux_2level_tapbuf_size3\'\n mux_2level_tapbuf_size3 mux_left_track_5 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:262: Cannot find file containing module: \'mux_2level_tapbuf_size3\'\n mux_2level_tapbuf_size3 mux_left_track_7 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:268: Cannot find file containing module: \'mux_2level_tapbuf_size3\'\n mux_2level_tapbuf_size3 mux_left_track_9 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:274: Cannot find file containing module: \'mux_2level_tapbuf_size3\'\n mux_2level_tapbuf_size3 mux_left_track_11 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:280: Cannot find file containing module: \'mux_2level_tapbuf_size3\'\n mux_2level_tapbuf_size3 mux_left_track_15 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:286: Cannot find file containing module: \'mux_2level_tapbuf_size3\'\n mux_2level_tapbuf_size3 mux_left_track_17 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:292: Cannot find file containing module: \'mux_2level_tapbuf_size3\'\n mux_2level_tapbuf_size3 mux_left_track_25 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:298: Cannot find file containing module: \'mux_2level_tapbuf_size3_mem\'\n mux_2level_tapbuf_size3_mem mem_bottom_track_3 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:304: Cannot find file containing module: \'mux_2level_tapbuf_size3_mem\'\n mux_2level_tapbuf_size3_mem mem_bottom_track_5 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:310: Cannot find file containing module: \'mux_2level_tapbuf_size3_mem\'\n mux_2level_tapbuf_size3_mem mem_bottom_track_7 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:316: Cannot find file containing module: \'mux_2level_tapbuf_size3_mem\'\n mux_2level_tapbuf_size3_mem mem_bottom_track_9 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:322: Cannot find file containing module: \'mux_2level_tapbuf_size3_mem\'\n mux_2level_tapbuf_size3_mem mem_bottom_track_11 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:328: Cannot find file containing module: \'mux_2level_tapbuf_size3_mem\'\n mux_2level_tapbuf_size3_mem mem_bottom_track_15 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:334: Cannot find file containing module: \'mux_2level_tapbuf_size3_mem\'\n mux_2level_tapbuf_size3_mem mem_bottom_track_17 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:340: Cannot find file containing module: \'mux_2level_tapbuf_size3_mem\'\n mux_2level_tapbuf_size3_mem mem_bottom_track_25 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:346: Cannot find file containing module: \'mux_2level_tapbuf_size3_mem\'\n mux_2level_tapbuf_size3_mem mem_left_track_3 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:352: Cannot find file containing module: \'mux_2level_tapbuf_size3_mem\'\n mux_2level_tapbuf_size3_mem mem_left_track_5 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:358: Cannot find file containing module: \'mux_2level_tapbuf_size3_mem\'\n mux_2level_tapbuf_size3_mem mem_left_track_7 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:364: Cannot find file containing module: \'mux_2level_tapbuf_size3_mem\'\n mux_2level_tapbuf_size3_mem mem_left_track_9 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:370: Cannot find file containing module: \'mux_2level_tapbuf_size3_mem\'\n mux_2level_tapbuf_size3_mem mem_left_track_11 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:376: Cannot find file containing module: \'mux_2level_tapbuf_size3_mem\'\n mux_2level_tapbuf_size3_mem mem_left_track_15 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:382: Cannot find file containing module: \'mux_2level_tapbuf_size3_mem\'\n mux_2level_tapbuf_size3_mem mem_left_track_17 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:388: Cannot find file containing module: \'mux_2level_tapbuf_size3_mem\'\n mux_2level_tapbuf_size3_mem mem_left_track_25 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:394: Cannot find file containing module: \'mux_2level_tapbuf_size2\'\n mux_2level_tapbuf_size2 mux_bottom_track_19 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:400: Cannot find file containing module: \'mux_2level_tapbuf_size2\'\n mux_2level_tapbuf_size2 mux_bottom_track_21 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:406: Cannot find file containing module: \'mux_2level_tapbuf_size2\'\n mux_2level_tapbuf_size2 mux_bottom_track_23 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:412: Cannot find file containing module: \'mux_2level_tapbuf_size2\'\n mux_2level_tapbuf_size2 mux_left_track_19 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:418: Cannot find file containing module: \'mux_2level_tapbuf_size2\'\n mux_2level_tapbuf_size2 mux_left_track_21 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:424: Cannot find file containing module: \'mux_2level_tapbuf_size2\'\n mux_2level_tapbuf_size2 mux_left_track_23 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:430: Cannot find file containing module: \'mux_2level_tapbuf_size2_mem\'\n mux_2level_tapbuf_size2_mem mem_bottom_track_19 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:436: Cannot find file containing module: \'mux_2level_tapbuf_size2_mem\'\n mux_2level_tapbuf_size2_mem mem_bottom_track_21 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:442: Cannot find file containing module: \'mux_2level_tapbuf_size2_mem\'\n mux_2level_tapbuf_size2_mem mem_bottom_track_23 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/sb_1__1_.v:448: Cannot find file containing module: \'mux_2level_tapbuf_size2_mem\'\n mux_2level_tapbuf_size2_mem mem_left_track_19 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module sb_1__1_(chany_bottom_in,
                bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_,
                bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_,
                bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_,
                bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_,
                bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_,
                bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_,
                bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_,
                bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_,
                bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_,
                chanx_left_in,
                left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_,
                left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_,
                left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_,
                left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_,
                left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_,
                left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_,
                left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_,
                left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_,
                left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
                bl,
                wl,
                chany_bottom_out,
                chanx_left_out);

input [0:12] chany_bottom_in;

input [0:0] bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_;

input [0:0] bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_;

input [0:0] bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_;

input [0:0] bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_;

input [0:0] bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_;

input [0:0] bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_;

input [0:0] bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_;

input [0:0] bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_;

input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_;

input [0:12] chanx_left_in;

input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;

input [0:0] left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_;

input [0:0] left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_;

input [0:0] left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_;

input [0:0] left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_;

input [0:0] left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_;

input [0:0] left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_;

input [0:0] left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_;

input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;

input [0:67] bl;

input [0:67] wl;

output [0:12] chany_bottom_out;

output [0:12] chanx_left_out;









wire [0:1] mux_2level_tapbuf_size2_0_sram;
wire [0:1] mux_2level_tapbuf_size2_0_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_1_sram;
wire [0:1] mux_2level_tapbuf_size2_1_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_2_sram;
wire [0:1] mux_2level_tapbuf_size2_2_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_3_sram;
wire [0:1] mux_2level_tapbuf_size2_3_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_4_sram;
wire [0:1] mux_2level_tapbuf_size2_4_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_5_sram;
wire [0:1] mux_2level_tapbuf_size2_5_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_0_sram;
wire [0:1] mux_2level_tapbuf_size3_0_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_10_sram;
wire [0:1] mux_2level_tapbuf_size3_10_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_11_sram;
wire [0:1] mux_2level_tapbuf_size3_11_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_12_sram;
wire [0:1] mux_2level_tapbuf_size3_12_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_13_sram;
wire [0:1] mux_2level_tapbuf_size3_13_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_14_sram;
wire [0:1] mux_2level_tapbuf_size3_14_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_15_sram;
wire [0:1] mux_2level_tapbuf_size3_15_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_1_sram;
wire [0:1] mux_2level_tapbuf_size3_1_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_2_sram;
wire [0:1] mux_2level_tapbuf_size3_2_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_3_sram;
wire [0:1] mux_2level_tapbuf_size3_3_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_4_sram;
wire [0:1] mux_2level_tapbuf_size3_4_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_5_sram;
wire [0:1] mux_2level_tapbuf_size3_5_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_6_sram;
wire [0:1] mux_2level_tapbuf_size3_6_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_7_sram;
wire [0:1] mux_2level_tapbuf_size3_7_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_8_sram;
wire [0:1] mux_2level_tapbuf_size3_8_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_9_sram;
wire [0:1] mux_2level_tapbuf_size3_9_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_0_sram;
wire [0:5] mux_2level_tapbuf_size4_0_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_1_sram;
wire [0:5] mux_2level_tapbuf_size4_1_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_2_sram;
wire [0:5] mux_2level_tapbuf_size4_2_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_3_sram;
wire [0:5] mux_2level_tapbuf_size4_3_sram_inv;






	mux_2level_tapbuf_size4 mux_bottom_track_1 (
		.in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[1]}),
		.sram(mux_2level_tapbuf_size4_0_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size4_0_sram_inv[0:5]),
		.out(chany_bottom_out[0]));

	mux_2level_tapbuf_size4 mux_bottom_track_13 (
		.in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[7]}),
		.sram(mux_2level_tapbuf_size4_1_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size4_1_sram_inv[0:5]),
		.out(chany_bottom_out[6]));

	mux_2level_tapbuf_size4 mux_left_track_1 (
		.in({chany_bottom_in[12], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_}),
		.sram(mux_2level_tapbuf_size4_2_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size4_2_sram_inv[0:5]),
		.out(chanx_left_out[0]));

	mux_2level_tapbuf_size4 mux_left_track_13 (
		.in({chany_bottom_in[5], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_}),
		.sram(mux_2level_tapbuf_size4_3_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size4_3_sram_inv[0:5]),
		.out(chanx_left_out[6]));

	mux_2level_tapbuf_size4_mem mem_bottom_track_1 (
		.bl(bl[0:5]),
		.wl(wl[0:5]),
		.mem_out(mux_2level_tapbuf_size4_0_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size4_0_sram_inv[0:5]));

	mux_2level_tapbuf_size4_mem mem_bottom_track_13 (
		.bl(bl[16:21]),
		.wl(wl[16:21]),
		.mem_out(mux_2level_tapbuf_size4_1_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size4_1_sram_inv[0:5]));

	mux_2level_tapbuf_size4_mem mem_left_track_1 (
		.bl(bl[34:39]),
		.wl(wl[34:39]),
		.mem_out(mux_2level_tapbuf_size4_2_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size4_2_sram_inv[0:5]));

	mux_2level_tapbuf_size4_mem mem_left_track_13 (
		.bl(bl[50:55]),
		.wl(wl[50:55]),
		.mem_out(mux_2level_tapbuf_size4_3_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size4_3_sram_inv[0:5]));

	mux_2level_tapbuf_size3 mux_bottom_track_3 (
		.in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[2]}),
		.sram(mux_2level_tapbuf_size3_0_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size3_0_sram_inv[0:1]),
		.out(chany_bottom_out[1]));

	mux_2level_tapbuf_size3 mux_bottom_track_5 (
		.in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[3]}),
		.sram(mux_2level_tapbuf_size3_1_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size3_1_sram_inv[0:1]),
		.out(chany_bottom_out[2]));

	mux_2level_tapbuf_size3 mux_bottom_track_7 (
		.in({bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, chanx_left_in[4]}),
		.sram(mux_2level_tapbuf_size3_2_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size3_2_sram_inv[0:1]),
		.out(chany_bottom_out[3]));

	mux_2level_tapbuf_size3 mux_bottom_track_9 (
		.in({bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, chanx_left_in[5]}),
		.sram(mux_2level_tapbuf_size3_3_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size3_3_sram_inv[0:1]),
		.out(chany_bottom_out[4]));

	mux_2level_tapbuf_size3 mux_bottom_track_11 (
		.in({bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, chanx_left_in[6]}),
		.sram(mux_2level_tapbuf_size3_4_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size3_4_sram_inv[0:1]),
		.out(chany_bottom_out[5]));

	mux_2level_tapbuf_size3 mux_bottom_track_15 (
		.in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[8]}),
		.sram(mux_2level_tapbuf_size3_5_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size3_5_sram_inv[0:1]),
		.out(chany_bottom_out[7]));

	mux_2level_tapbuf_size3 mux_bottom_track_17 (
		.in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_, chanx_left_in[9]}),
		.sram(mux_2level_tapbuf_size3_6_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size3_6_sram_inv[0:1]),
		.out(chany_bottom_out[8]));

	mux_2level_tapbuf_size3 mux_bottom_track_25 (
		.in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, chanx_left_in[0]}),
		.sram(mux_2level_tapbuf_size3_7_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size3_7_sram_inv[0:1]),
		.out(chany_bottom_out[12]));

	mux_2level_tapbuf_size3 mux_left_track_3 (
		.in({chany_bottom_in[0], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_}),
		.sram(mux_2level_tapbuf_size3_8_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size3_8_sram_inv[0:1]),
		.out(chanx_left_out[1]));

	mux_2level_tapbuf_size3 mux_left_track_5 (
		.in({chany_bottom_in[1], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_}),
		.sram(mux_2level_tapbuf_size3_9_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size3_9_sram_inv[0:1]),
		.out(chanx_left_out[2]));

	mux_2level_tapbuf_size3 mux_left_track_7 (
		.in({chany_bottom_in[2], left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_}),
		.sram(mux_2level_tapbuf_size3_10_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size3_10_sram_inv[0:1]),
		.out(chanx_left_out[3]));

	mux_2level_tapbuf_size3 mux_left_track_9 (
		.in({chany_bottom_in[3], left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_}),
		.sram(mux_2level_tapbuf_size3_11_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size3_11_sram_inv[0:1]),
		.out(chanx_left_out[4]));

	mux_2level_tapbuf_size3 mux_left_track_11 (
		.in({chany_bottom_in[4], left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_}),
		.sram(mux_2level_tapbuf_size3_12_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size3_12_sram_inv[0:1]),
		.out(chanx_left_out[5]));

	mux_2level_tapbuf_size3 mux_left_track_15 (
		.in({chany_bottom_in[6], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_}),
		.sram(mux_2level_tapbuf_size3_13_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size3_13_sram_inv[0:1]),
		.out(chanx_left_out[7]));

	mux_2level_tapbuf_size3 mux_left_track_17 (
		.in({chany_bottom_in[7], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}),
		.sram(mux_2level_tapbuf_size3_14_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size3_14_sram_inv[0:1]),
		.out(chanx_left_out[8]));

	mux_2level_tapbuf_size3 mux_left_track_25 (
		.in({chany_bottom_in[11], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_}),
		.sram(mux_2level_tapbuf_size3_15_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size3_15_sram_inv[0:1]),
		.out(chanx_left_out[12]));

	mux_2level_tapbuf_size3_mem mem_bottom_track_3 (
		.bl(bl[6:7]),
		.wl(wl[6:7]),
		.mem_out(mux_2level_tapbuf_size3_0_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size3_0_sram_inv[0:1]));

	mux_2level_tapbuf_size3_mem mem_bottom_track_5 (
		.bl(bl[8:9]),
		.wl(wl[8:9]),
		.mem_out(mux_2level_tapbuf_size3_1_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size3_1_sram_inv[0:1]));

	mux_2level_tapbuf_size3_mem mem_bottom_track_7 (
		.bl(bl[10:11]),
		.wl(wl[10:11]),
		.mem_out(mux_2level_tapbuf_size3_2_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size3_2_sram_inv[0:1]));

	mux_2level_tapbuf_size3_mem mem_bottom_track_9 (
		.bl(bl[12:13]),
		.wl(wl[12:13]),
		.mem_out(mux_2level_tapbuf_size3_3_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size3_3_sram_inv[0:1]));

	mux_2level_tapbuf_size3_mem mem_bottom_track_11 (
		.bl(bl[14:15]),
		.wl(wl[14:15]),
		.mem_out(mux_2level_tapbuf_size3_4_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size3_4_sram_inv[0:1]));

	mux_2level_tapbuf_size3_mem mem_bottom_track_15 (
		.bl(bl[22:23]),
		.wl(wl[22:23]),
		.mem_out(mux_2level_tapbuf_size3_5_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size3_5_sram_inv[0:1]));

	mux_2level_tapbuf_size3_mem mem_bottom_track_17 (
		.bl(bl[24:25]),
		.wl(wl[24:25]),
		.mem_out(mux_2level_tapbuf_size3_6_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size3_6_sram_inv[0:1]));

	mux_2level_tapbuf_size3_mem mem_bottom_track_25 (
		.bl(bl[32:33]),
		.wl(wl[32:33]),
		.mem_out(mux_2level_tapbuf_size3_7_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size3_7_sram_inv[0:1]));

	mux_2level_tapbuf_size3_mem mem_left_track_3 (
		.bl(bl[40:41]),
		.wl(wl[40:41]),
		.mem_out(mux_2level_tapbuf_size3_8_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size3_8_sram_inv[0:1]));

	mux_2level_tapbuf_size3_mem mem_left_track_5 (
		.bl(bl[42:43]),
		.wl(wl[42:43]),
		.mem_out(mux_2level_tapbuf_size3_9_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size3_9_sram_inv[0:1]));

	mux_2level_tapbuf_size3_mem mem_left_track_7 (
		.bl(bl[44:45]),
		.wl(wl[44:45]),
		.mem_out(mux_2level_tapbuf_size3_10_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size3_10_sram_inv[0:1]));

	mux_2level_tapbuf_size3_mem mem_left_track_9 (
		.bl(bl[46:47]),
		.wl(wl[46:47]),
		.mem_out(mux_2level_tapbuf_size3_11_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size3_11_sram_inv[0:1]));

	mux_2level_tapbuf_size3_mem mem_left_track_11 (
		.bl(bl[48:49]),
		.wl(wl[48:49]),
		.mem_out(mux_2level_tapbuf_size3_12_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size3_12_sram_inv[0:1]));

	mux_2level_tapbuf_size3_mem mem_left_track_15 (
		.bl(bl[56:57]),
		.wl(wl[56:57]),
		.mem_out(mux_2level_tapbuf_size3_13_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size3_13_sram_inv[0:1]));

	mux_2level_tapbuf_size3_mem mem_left_track_17 (
		.bl(bl[58:59]),
		.wl(wl[58:59]),
		.mem_out(mux_2level_tapbuf_size3_14_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size3_14_sram_inv[0:1]));

	mux_2level_tapbuf_size3_mem mem_left_track_25 (
		.bl(bl[66:67]),
		.wl(wl[66:67]),
		.mem_out(mux_2level_tapbuf_size3_15_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size3_15_sram_inv[0:1]));

	mux_2level_tapbuf_size2 mux_bottom_track_19 (
		.in({bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[10]}),
		.sram(mux_2level_tapbuf_size2_0_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size2_0_sram_inv[0:1]),
		.out(chany_bottom_out[9]));

	mux_2level_tapbuf_size2 mux_bottom_track_21 (
		.in({bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, chanx_left_in[11]}),
		.sram(mux_2level_tapbuf_size2_1_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size2_1_sram_inv[0:1]),
		.out(chany_bottom_out[10]));

	mux_2level_tapbuf_size2 mux_bottom_track_23 (
		.in({bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, chanx_left_in[12]}),
		.sram(mux_2level_tapbuf_size2_2_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size2_2_sram_inv[0:1]),
		.out(chany_bottom_out[11]));

	mux_2level_tapbuf_size2 mux_left_track_19 (
		.in({chany_bottom_in[8], left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_}),
		.sram(mux_2level_tapbuf_size2_3_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size2_3_sram_inv[0:1]),
		.out(chanx_left_out[9]));

	mux_2level_tapbuf_size2 mux_left_track_21 (
		.in({chany_bottom_in[9], left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_}),
		.sram(mux_2level_tapbuf_size2_4_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size2_4_sram_inv[0:1]),
		.out(chanx_left_out[10]));

	mux_2level_tapbuf_size2 mux_left_track_23 (
		.in({chany_bottom_in[10], left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_}),
		.sram(mux_2level_tapbuf_size2_5_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size2_5_sram_inv[0:1]),
		.out(chanx_left_out[11]));

	mux_2level_tapbuf_size2_mem mem_bottom_track_19 (
		.bl(bl[26:27]),
		.wl(wl[26:27]),
		.mem_out(mux_2level_tapbuf_size2_0_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size2_0_sram_inv[0:1]));

	mux_2level_tapbuf_size2_mem mem_bottom_track_21 (
		.bl(bl[28:29]),
		.wl(wl[28:29]),
		.mem_out(mux_2level_tapbuf_size2_1_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size2_1_sram_inv[0:1]));

	mux_2level_tapbuf_size2_mem mem_bottom_track_23 (
		.bl(bl[30:31]),
		.wl(wl[30:31]),
		.mem_out(mux_2level_tapbuf_size2_2_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size2_2_sram_inv[0:1]));

	mux_2level_tapbuf_size2_mem mem_left_track_19 (
		.bl(bl[60:61]),
		.wl(wl[60:61]),
		.mem_out(mux_2level_tapbuf_size2_3_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size2_3_sram_inv[0:1]));

	mux_2level_tapbuf_size2_mem mem_left_track_21 (
		.bl(bl[62:63]),
		.wl(wl[62:63]),
		.mem_out(mux_2level_tapbuf_size2_4_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size2_4_sram_inv[0:1]));

	mux_2level_tapbuf_size2_mem mem_left_track_23 (
		.bl(bl[64:65]),
		.wl(wl[64:65]),
		.mem_out(mux_2level_tapbuf_size2_5_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size2_5_sram_inv[0:1]));

endmodule
module sb_1__1_(chany_bottom_in,
                bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_,
                bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_,
                bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_,
                bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_,
                bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_,
                bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_,
                bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_,
                bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_,
                bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_,
                chanx_left_in,
                left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_,
                left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_,
                left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_,
                left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_,
                left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_,
                left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_,
                left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_,
                left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_,
                left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_,
                bl,
                wl,
                chany_bottom_out,
                chanx_left_out);


input [0:12] chany_bottom_in;

input [0:0] bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_;

input [0:0] bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_;

input [0:0] bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_;

input [0:0] bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_;

input [0:0] bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_;

input [0:0] bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_;

input [0:0] bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_;

input [0:0] bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_;

input [0:0] bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_;

input [0:12] chanx_left_in;

input [0:0] left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_;

input [0:0] left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_;

input [0:0] left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_;

input [0:0] left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_;

input [0:0] left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_;

input [0:0] left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_;

input [0:0] left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_;

input [0:0] left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_;

input [0:0] left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_;

input [0:67] bl;

input [0:67] wl;

output [0:12] chany_bottom_out;

output [0:12] chanx_left_out;









wire [0:1] mux_2level_tapbuf_size2_0_sram;
wire [0:1] mux_2level_tapbuf_size2_0_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_1_sram;
wire [0:1] mux_2level_tapbuf_size2_1_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_2_sram;
wire [0:1] mux_2level_tapbuf_size2_2_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_3_sram;
wire [0:1] mux_2level_tapbuf_size2_3_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_4_sram;
wire [0:1] mux_2level_tapbuf_size2_4_sram_inv;
wire [0:1] mux_2level_tapbuf_size2_5_sram;
wire [0:1] mux_2level_tapbuf_size2_5_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_0_sram;
wire [0:1] mux_2level_tapbuf_size3_0_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_10_sram;
wire [0:1] mux_2level_tapbuf_size3_10_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_11_sram;
wire [0:1] mux_2level_tapbuf_size3_11_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_12_sram;
wire [0:1] mux_2level_tapbuf_size3_12_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_13_sram;
wire [0:1] mux_2level_tapbuf_size3_13_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_14_sram;
wire [0:1] mux_2level_tapbuf_size3_14_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_15_sram;
wire [0:1] mux_2level_tapbuf_size3_15_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_1_sram;
wire [0:1] mux_2level_tapbuf_size3_1_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_2_sram;
wire [0:1] mux_2level_tapbuf_size3_2_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_3_sram;
wire [0:1] mux_2level_tapbuf_size3_3_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_4_sram;
wire [0:1] mux_2level_tapbuf_size3_4_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_5_sram;
wire [0:1] mux_2level_tapbuf_size3_5_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_6_sram;
wire [0:1] mux_2level_tapbuf_size3_6_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_7_sram;
wire [0:1] mux_2level_tapbuf_size3_7_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_8_sram;
wire [0:1] mux_2level_tapbuf_size3_8_sram_inv;
wire [0:1] mux_2level_tapbuf_size3_9_sram;
wire [0:1] mux_2level_tapbuf_size3_9_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_0_sram;
wire [0:5] mux_2level_tapbuf_size4_0_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_1_sram;
wire [0:5] mux_2level_tapbuf_size4_1_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_2_sram;
wire [0:5] mux_2level_tapbuf_size4_2_sram_inv;
wire [0:5] mux_2level_tapbuf_size4_3_sram;
wire [0:5] mux_2level_tapbuf_size4_3_sram_inv;






	mux_2level_tapbuf_size4 mux_bottom_track_1 (
		.in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[1]}),
		.sram(mux_2level_tapbuf_size4_0_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size4_0_sram_inv[0:5]),
		.out(chany_bottom_out[0]));

	mux_2level_tapbuf_size4 mux_bottom_track_13 (
		.in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[7]}),
		.sram(mux_2level_tapbuf_size4_1_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size4_1_sram_inv[0:5]),
		.out(chany_bottom_out[6]));

	mux_2level_tapbuf_size4 mux_left_track_1 (
		.in({chany_bottom_in[12], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_}),
		.sram(mux_2level_tapbuf_size4_2_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size4_2_sram_inv[0:5]),
		.out(chanx_left_out[0]));

	mux_2level_tapbuf_size4 mux_left_track_13 (
		.in({chany_bottom_in[5], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_}),
		.sram(mux_2level_tapbuf_size4_3_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size4_3_sram_inv[0:5]),
		.out(chanx_left_out[6]));

	mux_2level_tapbuf_size4_mem mem_bottom_track_1 (
		.bl(bl[0:5]),
		.wl(wl[0:5]),
		.mem_out(mux_2level_tapbuf_size4_0_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size4_0_sram_inv[0:5]));

	mux_2level_tapbuf_size4_mem mem_bottom_track_13 (
		.bl(bl[16:21]),
		.wl(wl[16:21]),
		.mem_out(mux_2level_tapbuf_size4_1_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size4_1_sram_inv[0:5]));

	mux_2level_tapbuf_size4_mem mem_left_track_1 (
		.bl(bl[34:39]),
		.wl(wl[34:39]),
		.mem_out(mux_2level_tapbuf_size4_2_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size4_2_sram_inv[0:5]));

	mux_2level_tapbuf_size4_mem mem_left_track_13 (
		.bl(bl[50:55]),
		.wl(wl[50:55]),
		.mem_out(mux_2level_tapbuf_size4_3_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size4_3_sram_inv[0:5]));

	mux_2level_tapbuf_size3 mux_bottom_track_3 (
		.in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, chanx_left_in[2]}),
		.sram(mux_2level_tapbuf_size3_0_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size3_0_sram_inv[0:1]),
		.out(chany_bottom_out[1]));

	mux_2level_tapbuf_size3 mux_bottom_track_5 (
		.in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[3]}),
		.sram(mux_2level_tapbuf_size3_1_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size3_1_sram_inv[0:1]),
		.out(chany_bottom_out[2]));

	mux_2level_tapbuf_size3 mux_bottom_track_7 (
		.in({bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, chanx_left_in[4]}),
		.sram(mux_2level_tapbuf_size3_2_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size3_2_sram_inv[0:1]),
		.out(chany_bottom_out[3]));

	mux_2level_tapbuf_size3 mux_bottom_track_9 (
		.in({bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, chanx_left_in[5]}),
		.sram(mux_2level_tapbuf_size3_3_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size3_3_sram_inv[0:1]),
		.out(chany_bottom_out[4]));

	mux_2level_tapbuf_size3 mux_bottom_track_11 (
		.in({bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, chanx_left_in[6]}),
		.sram(mux_2level_tapbuf_size3_4_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size3_4_sram_inv[0:1]),
		.out(chany_bottom_out[5]));

	mux_2level_tapbuf_size3 mux_bottom_track_15 (
		.in({bottom_right_grid_left_width_0_height_0_subtile_1__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_, chanx_left_in[8]}),
		.sram(mux_2level_tapbuf_size3_5_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size3_5_sram_inv[0:1]),
		.out(chany_bottom_out[7]));

	mux_2level_tapbuf_size3 mux_bottom_track_17 (
		.in({bottom_right_grid_left_width_0_height_0_subtile_2__pin_inpad_0_, bottom_left_grid_right_width_0_height_0_subtile_0__pin_O_3_, chanx_left_in[9]}),
		.sram(mux_2level_tapbuf_size3_6_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size3_6_sram_inv[0:1]),
		.out(chany_bottom_out[8]));

	mux_2level_tapbuf_size3 mux_bottom_track_25 (
		.in({bottom_right_grid_left_width_0_height_0_subtile_0__pin_inpad_0_, bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_, chanx_left_in[0]}),
		.sram(mux_2level_tapbuf_size3_7_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size3_7_sram_inv[0:1]),
		.out(chany_bottom_out[12]));

	mux_2level_tapbuf_size3 mux_left_track_3 (
		.in({chany_bottom_in[0], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_}),
		.sram(mux_2level_tapbuf_size3_8_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size3_8_sram_inv[0:1]),
		.out(chanx_left_out[1]));

	mux_2level_tapbuf_size3 mux_left_track_5 (
		.in({chany_bottom_in[1], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_}),
		.sram(mux_2level_tapbuf_size3_9_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size3_9_sram_inv[0:1]),
		.out(chanx_left_out[2]));

	mux_2level_tapbuf_size3 mux_left_track_7 (
		.in({chany_bottom_in[2], left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_}),
		.sram(mux_2level_tapbuf_size3_10_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size3_10_sram_inv[0:1]),
		.out(chanx_left_out[3]));

	mux_2level_tapbuf_size3 mux_left_track_9 (
		.in({chany_bottom_in[3], left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_}),
		.sram(mux_2level_tapbuf_size3_11_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size3_11_sram_inv[0:1]),
		.out(chanx_left_out[4]));

	mux_2level_tapbuf_size3 mux_left_track_11 (
		.in({chany_bottom_in[4], left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_}),
		.sram(mux_2level_tapbuf_size3_12_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size3_12_sram_inv[0:1]),
		.out(chanx_left_out[5]));

	mux_2level_tapbuf_size3 mux_left_track_15 (
		.in({chany_bottom_in[6], left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_}),
		.sram(mux_2level_tapbuf_size3_13_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size3_13_sram_inv[0:1]),
		.out(chanx_left_out[7]));

	mux_2level_tapbuf_size3 mux_left_track_17 (
		.in({chany_bottom_in[7], left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_, left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_}),
		.sram(mux_2level_tapbuf_size3_14_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size3_14_sram_inv[0:1]),
		.out(chanx_left_out[8]));

	mux_2level_tapbuf_size3 mux_left_track_25 (
		.in({chany_bottom_in[11], left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_, left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_}),
		.sram(mux_2level_tapbuf_size3_15_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size3_15_sram_inv[0:1]),
		.out(chanx_left_out[12]));

	mux_2level_tapbuf_size3_mem mem_bottom_track_3 (
		.bl(bl[6:7]),
		.wl(wl[6:7]),
		.mem_out(mux_2level_tapbuf_size3_0_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size3_0_sram_inv[0:1]));

	mux_2level_tapbuf_size3_mem mem_bottom_track_5 (
		.bl(bl[8:9]),
		.wl(wl[8:9]),
		.mem_out(mux_2level_tapbuf_size3_1_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size3_1_sram_inv[0:1]));

	mux_2level_tapbuf_size3_mem mem_bottom_track_7 (
		.bl(bl[10:11]),
		.wl(wl[10:11]),
		.mem_out(mux_2level_tapbuf_size3_2_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size3_2_sram_inv[0:1]));

	mux_2level_tapbuf_size3_mem mem_bottom_track_9 (
		.bl(bl[12:13]),
		.wl(wl[12:13]),
		.mem_out(mux_2level_tapbuf_size3_3_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size3_3_sram_inv[0:1]));

	mux_2level_tapbuf_size3_mem mem_bottom_track_11 (
		.bl(bl[14:15]),
		.wl(wl[14:15]),
		.mem_out(mux_2level_tapbuf_size3_4_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size3_4_sram_inv[0:1]));

	mux_2level_tapbuf_size3_mem mem_bottom_track_15 (
		.bl(bl[22:23]),
		.wl(wl[22:23]),
		.mem_out(mux_2level_tapbuf_size3_5_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size3_5_sram_inv[0:1]));

	mux_2level_tapbuf_size3_mem mem_bottom_track_17 (
		.bl(bl[24:25]),
		.wl(wl[24:25]),
		.mem_out(mux_2level_tapbuf_size3_6_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size3_6_sram_inv[0:1]));

	mux_2level_tapbuf_size3_mem mem_bottom_track_25 (
		.bl(bl[32:33]),
		.wl(wl[32:33]),
		.mem_out(mux_2level_tapbuf_size3_7_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size3_7_sram_inv[0:1]));

	mux_2level_tapbuf_size3_mem mem_left_track_3 (
		.bl(bl[40:41]),
		.wl(wl[40:41]),
		.mem_out(mux_2level_tapbuf_size3_8_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size3_8_sram_inv[0:1]));

	mux_2level_tapbuf_size3_mem mem_left_track_5 (
		.bl(bl[42:43]),
		.wl(wl[42:43]),
		.mem_out(mux_2level_tapbuf_size3_9_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size3_9_sram_inv[0:1]));

	mux_2level_tapbuf_size3_mem mem_left_track_7 (
		.bl(bl[44:45]),
		.wl(wl[44:45]),
		.mem_out(mux_2level_tapbuf_size3_10_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size3_10_sram_inv[0:1]));

	mux_2level_tapbuf_size3_mem mem_left_track_9 (
		.bl(bl[46:47]),
		.wl(wl[46:47]),
		.mem_out(mux_2level_tapbuf_size3_11_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size3_11_sram_inv[0:1]));

	mux_2level_tapbuf_size3_mem mem_left_track_11 (
		.bl(bl[48:49]),
		.wl(wl[48:49]),
		.mem_out(mux_2level_tapbuf_size3_12_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size3_12_sram_inv[0:1]));

	mux_2level_tapbuf_size3_mem mem_left_track_15 (
		.bl(bl[56:57]),
		.wl(wl[56:57]),
		.mem_out(mux_2level_tapbuf_size3_13_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size3_13_sram_inv[0:1]));

	mux_2level_tapbuf_size3_mem mem_left_track_17 (
		.bl(bl[58:59]),
		.wl(wl[58:59]),
		.mem_out(mux_2level_tapbuf_size3_14_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size3_14_sram_inv[0:1]));

	mux_2level_tapbuf_size3_mem mem_left_track_25 (
		.bl(bl[66:67]),
		.wl(wl[66:67]),
		.mem_out(mux_2level_tapbuf_size3_15_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size3_15_sram_inv[0:1]));

	mux_2level_tapbuf_size2 mux_bottom_track_19 (
		.in({bottom_right_grid_left_width_0_height_0_subtile_3__pin_inpad_0_, chanx_left_in[10]}),
		.sram(mux_2level_tapbuf_size2_0_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size2_0_sram_inv[0:1]),
		.out(chany_bottom_out[9]));

	mux_2level_tapbuf_size2 mux_bottom_track_21 (
		.in({bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_, chanx_left_in[11]}),
		.sram(mux_2level_tapbuf_size2_1_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size2_1_sram_inv[0:1]),
		.out(chany_bottom_out[10]));

	mux_2level_tapbuf_size2 mux_bottom_track_23 (
		.in({bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_, chanx_left_in[12]}),
		.sram(mux_2level_tapbuf_size2_2_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size2_2_sram_inv[0:1]),
		.out(chany_bottom_out[11]));

	mux_2level_tapbuf_size2 mux_left_track_19 (
		.in({chany_bottom_in[8], left_top_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_}),
		.sram(mux_2level_tapbuf_size2_3_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size2_3_sram_inv[0:1]),
		.out(chanx_left_out[9]));

	mux_2level_tapbuf_size2 mux_left_track_21 (
		.in({chany_bottom_in[9], left_top_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_}),
		.sram(mux_2level_tapbuf_size2_4_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size2_4_sram_inv[0:1]),
		.out(chanx_left_out[10]));

	mux_2level_tapbuf_size2 mux_left_track_23 (
		.in({chany_bottom_in[10], left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_}),
		.sram(mux_2level_tapbuf_size2_5_sram[0:1]),
		.sram_inv(mux_2level_tapbuf_size2_5_sram_inv[0:1]),
		.out(chanx_left_out[11]));

	mux_2level_tapbuf_size2_mem mem_bottom_track_19 (
		.bl(bl[26:27]),
		.wl(wl[26:27]),
		.mem_out(mux_2level_tapbuf_size2_0_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size2_0_sram_inv[0:1]));

	mux_2level_tapbuf_size2_mem mem_bottom_track_21 (
		.bl(bl[28:29]),
		.wl(wl[28:29]),
		.mem_out(mux_2level_tapbuf_size2_1_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size2_1_sram_inv[0:1]));

	mux_2level_tapbuf_size2_mem mem_bottom_track_23 (
		.bl(bl[30:31]),
		.wl(wl[30:31]),
		.mem_out(mux_2level_tapbuf_size2_2_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size2_2_sram_inv[0:1]));

	mux_2level_tapbuf_size2_mem mem_left_track_19 (
		.bl(bl[60:61]),
		.wl(wl[60:61]),
		.mem_out(mux_2level_tapbuf_size2_3_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size2_3_sram_inv[0:1]));

	mux_2level_tapbuf_size2_mem mem_left_track_21 (
		.bl(bl[62:63]),
		.wl(wl[62:63]),
		.mem_out(mux_2level_tapbuf_size2_4_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size2_4_sram_inv[0:1]));

	mux_2level_tapbuf_size2_mem mem_left_track_23 (
		.bl(bl[64:65]),
		.wl(wl[64:65]),
		.mem_out(mux_2level_tapbuf_size2_5_sram[0:1]),
		.mem_outb(mux_2level_tapbuf_size2_5_sram_inv[0:1]));

endmodule