data/full_repos/permissive/458737381/src/verilog-parser/tests/iob_jbi_rptr_0.v
data/verilator_xmls/76d6ed2c-ee1e-4ac6-b890-87b9db761ab2.xml
module iob_jbi_rptr_0 (

   sig_buf, 

   sig
   );



output  [163:0] sig_buf;
input   [163:0] sig;


assign  sig_buf  = sig;




endmodule
module iob_jbi_rptr_0 (

   sig_buf, 

   sig
   );




output  [163:0] sig_buf;
input   [163:0] sig;


assign  sig_buf  = sig;




endmodule