data/full_repos/permissive/510160664/Adders/tb/ripple_carry_tb.v
1: b'%Error: data/full_repos/permissive/510160664/Adders/tb/ripple_carry_tb.v:2: Cannot find include file: ../src/ripple_carry.v\n`include "../src/ripple_carry.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/510160664/Adders/tb,data/full_repos/permissive/510160664/../src/ripple_carry.v\n             data/full_repos/permissive/510160664/Adders/tb,data/full_repos/permissive/510160664/../src/ripple_carry.v.v\n             data/full_repos/permissive/510160664/Adders/tb,data/full_repos/permissive/510160664/../src/ripple_carry.v.sv\n             ../src/ripple_carry.v\n             ../src/ripple_carry.v.v\n             ../src/ripple_carry.v.sv\n             obj_dir/../src/ripple_carry.v\n             obj_dir/../src/ripple_carry.v.v\n             obj_dir/../src/ripple_carry.v.sv\n%Error: data/full_repos/permissive/510160664/Adders/tb/ripple_carry_tb.v:27: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("ripple_carry.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/510160664/Adders/tb/ripple_carry_tb.v:28: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, ripple_carry_tb);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/510160664/Adders/tb/ripple_carry_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #100 $finish;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/510160664/Adders/tb/ripple_carry_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #10;                                               \n ^\n%Warning-STMTDLY: data/full_repos/permissive/510160664/Adders/tb/ripple_carry_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #10;                                               \n ^\n%Warning-STMTDLY: data/full_repos/permissive/510160664/Adders/tb/ripple_carry_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n #10;                                               \n ^\n%Warning-STMTDLY: data/full_repos/permissive/510160664/Adders/tb/ripple_carry_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n #10;                                               \n ^\n%Warning-STMTDLY: data/full_repos/permissive/510160664/Adders/tb/ripple_carry_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n #10;                                               \n ^\n%Warning-STMTDLY: data/full_repos/permissive/510160664/Adders/tb/ripple_carry_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n #10;                                               \n ^\n%Warning-STMTDLY: data/full_repos/permissive/510160664/Adders/tb/ripple_carry_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n #10;                                               \n ^\n%Warning-STMTDLY: data/full_repos/permissive/510160664/Adders/tb/ripple_carry_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: Exiting due to 3 error(s), 9 warning(s)\n'
module ripple_carry_tb();

parameter WIDTH_PARAM = 32;

reg 	[WIDTH_PARAM-1:0] a, b;
reg 		  					c_i;
wire 		  					c_o;
wire 	[WIDTH_PARAM-1:0] s;

ripple_carry
#(
				.WIDTH(WIDTH_PARAM)
)
ripple_carry1
(
				.Number1_i(	a),
				.Number2_i(	b),
				.Carry_i(	c_i),

				.Result_o(	s),
				.Carry_o(	c_o)
);
initial begin
	$dumpfile("ripple_carry.vcd");
	$dumpvars(0, ripple_carry_tb);
	
	#100 $finish;
end

initial begin
	a <= 32'h9805_0EAA;	b <= 32'hE8E7_F6EA;	c_i <= 1'b0;
	#10;                                               
	a <= 32'h0DAB_5C93;	b <= 32'hCD41_F8D6;	c_i <= 1'b1;
	#10;                                               
	a <= 32'h1C86_CC9A;	b <= 32'hC926_4861;	c_i <= 1'b0;
	#10;                                               
	a <= 32'h9D6B_27C9;	b <= 32'hEE5_86C70;	c_i <= 1'b0;
	#10;                                               
	a <= 32'h515D_B61C;	b <= 32'hA7A5_38C1;	c_i <= 1'b1;
	#10;                                               
	a <= 32'h2CB8_5EE3;	b <= 32'hF4EE_199D;	c_i <= 1'b1;
	#10;                                               
	a <= 32'hFFFF_FFFF;	b <= 32'h0000_0000;	c_i <= 1'b1;
	#10;                                               
	a <= 32'hFFFF_FFFF;	b <= 32'h0000_0001;	c_i <= 1'b1;
	#10;
end

endmodule
module ripple_carry_tb();


parameter WIDTH_PARAM = 32;

reg 	[WIDTH_PARAM-1:0] a, b;
reg 		  					c_i;
wire 		  					c_o;
wire 	[WIDTH_PARAM-1:0] s;

ripple_carry
#(
				.WIDTH(WIDTH_PARAM)
)
ripple_carry1
(
				.Number1_i(	a),
				.Number2_i(	b),
				.Carry_i(	c_i),

				.Result_o(	s),
				.Carry_o(	c_o)
);
initial begin
	$dumpfile("ripple_carry.vcd");
	$dumpvars(0, ripple_carry_tb);
	
	#100 $finish;
end

initial begin
	a <= 32'h9805_0EAA;	b <= 32'hE8E7_F6EA;	c_i <= 1'b0;
	#10;                                               
	a <= 32'h0DAB_5C93;	b <= 32'hCD41_F8D6;	c_i <= 1'b1;
	#10;                                               
	a <= 32'h1C86_CC9A;	b <= 32'hC926_4861;	c_i <= 1'b0;
	#10;                                               
	a <= 32'h9D6B_27C9;	b <= 32'hEE5_86C70;	c_i <= 1'b0;
	#10;                                               
	a <= 32'h515D_B61C;	b <= 32'hA7A5_38C1;	c_i <= 1'b1;
	#10;                                               
	a <= 32'h2CB8_5EE3;	b <= 32'hF4EE_199D;	c_i <= 1'b1;
	#10;                                               
	a <= 32'hFFFF_FFFF;	b <= 32'h0000_0000;	c_i <= 1'b1;
	#10;                                               
	a <= 32'hFFFF_FFFF;	b <= 32'h0000_0001;	c_i <= 1'b1;
	#10;
end

endmodule