data/full_repos/permissive/520695407/src/buffer.sv
data/verilator_xmls/a8537430-6c85-4e55-84ee-8069c6ad348c.xml
module bram_sp_rf (
  input		      clk,
  input		      en,
  input		      w_en,
  input        [9:0]  addr,
  input        [11:0] din,
  output logic [11:0] dout
);
  logic [11:0] bram [1023:0];

  always_ff @ (posedge clk) begin
    if (en) begin
      if (w_en) bram[addr] <= din;
      dout <= bram[addr];
    end
  end
endmodule
module bram_sp_rf (
  input		      clk,
  input		      en,
  input		      w_en,
  input        [9:0]  addr,
  input        [11:0] din,
  output logic [11:0] dout
);

  logic [11:0] bram [1023:0];

  always_ff @ (posedge clk) begin
    if (en) begin
      if (w_en) bram[addr] <= din;
      dout <= bram[addr];
    end
  end
endmodule