data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_in_1 = 1; data_in_2 = 1; data_in_3 = 1; sign_in_1 = 1; sign_in_2 = 1; sign_in_3 = 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_in_1 = 1; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 1; sign_in_2 = 0; sign_in_3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_in_1 = 1; data_in_2 = 1; data_in_3 = 0; sign_in_1 = 1; sign_in_2 = 1; sign_in_3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_in_1 = 1; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 1; sign_in_2 = 0; sign_in_3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_in_1 = 0; data_in_2 = 1; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 1; sign_in_3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_in_1 = 0; data_in_2 = 0; data_in_3 = 1; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_in_1 = 0; data_in_2 = 1; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 1; sign_in_3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_in_1 = 1; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 1; sign_in_2 = 0; sign_in_3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_in_1 = 0; data_in_2 = 1; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 1; sign_in_3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_in_1 = 1; data_in_2 = 0; data_in_3 = 1; sign_in_1 = 1; sign_in_2 = 0; sign_in_3 = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_in_1 = 0; data_in_2 = 1; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 1; sign_in_3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:96: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_in_1 = 1; data_in_2 = 0; data_in_3 = 1; sign_in_1 = 1; sign_in_2 = 0; sign_in_3 = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_in_1 = 0; data_in_2 = 1; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 1; sign_in_3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_in_1 = 1; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 1; sign_in_2 = 0; sign_in_3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_in_1 = 0; data_in_2 = 1; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 1; sign_in_3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_in_1 = 1; data_in_2 = 0; data_in_3 = 1; sign_in_1 = 1; sign_in_2 = 0; sign_in_3 = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n    #5 clk = !clk;\n    ^\n%Error: data/full_repos/permissive/515513819/network_3_2/network_3_2_tb.v:14: Cannot find file containing module: \'network_3_2\'\n  network_3_2 U0(\n  ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/515513819/network_3_2,data/full_repos/permissive/515513819/network_3_2\n             data/full_repos/permissive/515513819/network_3_2,data/full_repos/permissive/515513819/network_3_2.v\n             data/full_repos/permissive/515513819/network_3_2,data/full_repos/permissive/515513819/network_3_2.sv\n             network_3_2\n             network_3_2.v\n             network_3_2.sv\n             obj_dir/network_3_2\n             obj_dir/network_3_2.v\n             obj_dir/network_3_2.sv\n%Error: Exiting due to 1 error(s), 38 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module network_3_2_tb ;

  reg clk;
  reg data_in_1, data_in_2, data_in_3;
  reg sign_in_1, sign_in_2, sign_in_3;
  reg weight_1, weight_2, weight_3, weight_4, weight_5;

  wire data_out_4, data_out_5;
  wire sign_out_4, sign_out_5;
  wire o1,o2,o3;

  network_3_2 U0(
    .clk         (clk),
    .data_in_1   (data_in_1),
    .sign_in_1   (sign_in_1),
    .data_in_2   (data_in_2),
    .sign_in_2   (sign_in_2),
    .data_in_3   (data_in_3),
    .sign_in_3   (sign_in_3),
    .weight_1    (weight_1),
    .weight_2    (weight_2),
    .weight_3    (weight_3),
    .weight_4    (weight_4),
    .weight_5    (weight_5),
    .data_out_4  (data_out_4),
    .sign_out_4  (sign_out_4),
    .data_out_5  (data_out_5),
    .sign_out_5  (sign_out_5),
    .o1 (o1), .o2 (o2), .o3(o3)
    );

  initial begin
    clk = 0;
    weight_1 = 1;
    weight_2 = 1;
    weight_3 = 0;
    weight_4 = 0;
    weight_5 = 1;

    data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 1; data_in_2 = 1; data_in_3 = 1; sign_in_1 = 1; sign_in_2 = 1; sign_in_3 = 1;

    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 1; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 1; sign_in_2 = 0; sign_in_3 = 0;

    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 1; data_in_2 = 1; data_in_3 = 0; sign_in_1 = 1; sign_in_2 = 1; sign_in_3 = 0;

    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 1; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 1; sign_in_2 = 0; sign_in_3 = 0;

    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 0; data_in_2 = 1; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 1; sign_in_3 = 0;

    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 0; data_in_2 = 0; data_in_3 = 1; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 1;

    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 0; data_in_2 = 1; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 1; sign_in_3 = 0;

    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 1; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 1; sign_in_2 = 0; sign_in_3 = 0;

    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 0; data_in_2 = 1; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 1; sign_in_3 = 0;

    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 1; data_in_2 = 0; data_in_3 = 1; sign_in_1 = 1; sign_in_2 = 0; sign_in_3 = 1;

    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 0; data_in_2 = 1; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 1; sign_in_3 = 0;

    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 1; data_in_2 = 0; data_in_3 = 1; sign_in_1 = 1; sign_in_2 = 0; sign_in_3 = 1;

    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 0; data_in_2 = 1; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 1; sign_in_3 = 0;

    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 1; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 1; sign_in_2 = 0; sign_in_3 = 0;

    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 0; data_in_2 = 1; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 1; sign_in_3 = 0;

    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 1; data_in_2 = 0; data_in_3 = 1; sign_in_1 = 1; sign_in_2 = 0; sign_in_3 = 1;

    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;
  end


  always
    #5 clk = !clk;

endmodule
module network_3_2_tb ;


  reg clk;
  reg data_in_1, data_in_2, data_in_3;
  reg sign_in_1, sign_in_2, sign_in_3;
  reg weight_1, weight_2, weight_3, weight_4, weight_5;

  wire data_out_4, data_out_5;
  wire sign_out_4, sign_out_5;
  wire o1,o2,o3;

  network_3_2 U0(
    .clk         (clk),
    .data_in_1   (data_in_1),
    .sign_in_1   (sign_in_1),
    .data_in_2   (data_in_2),
    .sign_in_2   (sign_in_2),
    .data_in_3   (data_in_3),
    .sign_in_3   (sign_in_3),
    .weight_1    (weight_1),
    .weight_2    (weight_2),
    .weight_3    (weight_3),
    .weight_4    (weight_4),
    .weight_5    (weight_5),
    .data_out_4  (data_out_4),
    .sign_out_4  (sign_out_4),
    .data_out_5  (data_out_5),
    .sign_out_5  (sign_out_5),
    .o1 (o1), .o2 (o2), .o3(o3)
    );

  initial begin
    clk = 0;
    weight_1 = 1;
    weight_2 = 1;
    weight_3 = 0;
    weight_4 = 0;
    weight_5 = 1;

    data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 1; data_in_2 = 1; data_in_3 = 1; sign_in_1 = 1; sign_in_2 = 1; sign_in_3 = 1;

    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 1; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 1; sign_in_2 = 0; sign_in_3 = 0;

    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 1; data_in_2 = 1; data_in_3 = 0; sign_in_1 = 1; sign_in_2 = 1; sign_in_3 = 0;

    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 1; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 1; sign_in_2 = 0; sign_in_3 = 0;

    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 0; data_in_2 = 1; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 1; sign_in_3 = 0;

    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 0; data_in_2 = 0; data_in_3 = 1; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 1;

    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 0; data_in_2 = 1; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 1; sign_in_3 = 0;

    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 1; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 1; sign_in_2 = 0; sign_in_3 = 0;

    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 0; data_in_2 = 1; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 1; sign_in_3 = 0;

    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 1; data_in_2 = 0; data_in_3 = 1; sign_in_1 = 1; sign_in_2 = 0; sign_in_3 = 1;

    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 0; data_in_2 = 1; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 1; sign_in_3 = 0;

    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 1; data_in_2 = 0; data_in_3 = 1; sign_in_1 = 1; sign_in_2 = 0; sign_in_3 = 1;

    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 0; data_in_2 = 1; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 1; sign_in_3 = 0;

    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 1; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 1; sign_in_2 = 0; sign_in_3 = 0;

    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 0; data_in_2 = 1; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 1; sign_in_3 = 0;

    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;

    #10 data_in_1 = 1; data_in_2 = 0; data_in_3 = 1; sign_in_1 = 1; sign_in_2 = 0; sign_in_3 = 1;

    #1 data_in_1 = 0; data_in_2 = 0; data_in_3 = 0; sign_in_1 = 0; sign_in_2 = 0; sign_in_3 = 0;
  end


  always
    #5 clk = !clk;

endmodule