data/full_repos/permissive/493019833/test/testcase/firrtl/TestMem/reference/TestMem.v
data/verilator_xmls/353b198e-02b3-4119-9aea-3ffe3a112987.xml
module TestMem(
    input clock,
    input reset
);
endmodule
module TestMem(
    input clock,
    input reset
);

endmodule