data/full_repos/permissive/413582930/instruction_memory.v
data/verilator_xmls/ebfd4a15-22de-40ec-a453-6b04dc2dbc76.xml
module instruction_memory (
    clk,
    pc,
    instruction
);

    parameter SIZE_OF_MEMORY = 64;

    input wire clk;
    input wire [31:0] pc;
    output reg [31:0] instruction = 32'h00000000;

    reg [31:0] ROM [SIZE_OF_MEMORY-1 : 0];

    integer i;
    initial begin
        for (i=0; i<SIZE_OF_MEMORY; i=i+1)
            ROM[i] = 0;
    end

    always @(posedge clk)
        instruction <= ROM[pc >> 2];

endmodule
module instruction_memory (
    clk,
    pc,
    instruction
);


    parameter SIZE_OF_MEMORY = 64;

    input wire clk;
    input wire [31:0] pc;
    output reg [31:0] instruction = 32'h00000000;

    reg [31:0] ROM [SIZE_OF_MEMORY-1 : 0];

    integer i;
    initial begin
        for (i=0; i<SIZE_OF_MEMORY; i=i+1)
            ROM[i] = 0;
    end

    always @(posedge clk)
        instruction <= ROM[pc >> 2];

endmodule