data/full_repos/permissive/425529933/Proyecto1Digitales2/phy-tx/phy_tx_e.v
data/verilator_xmls/40164a93-5aed-4490-afb3-993d0348201a.xml
module byte_striping_e(clk_2f_e, reset, valid_in, Data_in, valid_0_c, lane_0_c, valid_1_c, lane_1_c);
  (* src = "byte_striping_e.v:13" *)
  reg _00_;
  (* src = "byte_striping_e.v:13" *)
  reg [31:0] _01_;
  (* src = "byte_striping_e.v:13" *)
  reg [31:0] _02_;
  (* src = "byte_striping_e.v:13" *)
  reg _03_;
  (* src = "byte_striping_e.v:13" *)
  reg _04_;
  (* src = "byte_striping_e.v:23" *)
  reg _05_;
  (* src = "byte_striping_e.v:23" *)
  reg [31:0] _06_;
  (* src = "byte_striping_e.v:23" *)
  reg [31:0] _07_;
  (* src = "byte_striping_e.v:23" *)
  reg _08_;
  (* src = "byte_striping_e.v:23" *)
  reg _09_;
  (* src = "byte_striping_e.v:14" *)
  wire _10_;
  (* src = "byte_striping_e.v:43" *)
  wire _11_;
  (* src = "byte_striping_e.v:5" *)
  input [31:0] Data_in;
  (* src = "byte_striping_e.v:2" *)
  input clk_2f_e;
  (* src = "byte_striping_e.v:11" *)
  reg contador;
  (* src = "byte_striping_e.v:7" *)
  output [31:0] lane_0_c;
  reg [31:0] lane_0_c;
  (* src = "byte_striping_e.v:9" *)
  output [31:0] lane_1_c;
  reg [31:0] lane_1_c;
  (* src = "byte_striping_e.v:3" *)
  input reset;
  (* src = "byte_striping_e.v:6" *)
  output valid_0_c;
  reg valid_0_c;
  (* src = "byte_striping_e.v:8" *)
  output valid_1_c;
  reg valid_1_c;
  (* src = "byte_striping_e.v:4" *)
  input valid_in;
  assign _10_ = ~(* src = "byte_striping_e.v:14" *) reset;
  assign _11_ = ~(* src = "byte_striping_e.v:43" *) valid_0_c;
  always @* begin
    _04_ = valid_1_c;
    _02_ = lane_1_c;
    _00_ = contador;
    _03_ = valid_0_c;
    _01_ = lane_0_c;
    (* src = "byte_striping_e.v:14" *)
    casez (_10_)

      1'h1:
        begin
          _03_ = 1'h0;
          _01_ = 32'd0;
          _04_ = 1'h0;
          _02_ = 32'd0;
          _00_ = 1'h0;
        end
      default:
;
    endcase
  end
  always @* begin
      valid_1_c <= _04_;
      lane_1_c <= _02_;
      contador <= _00_;
      valid_0_c <= _03_;
      lane_0_c <= _01_;
  end
  always @* begin
    _09_ = valid_1_c;
    _07_ = lane_1_c;
    _05_ = contador;
    _08_ = valid_0_c;
    _06_ = lane_0_c;
    (* src = "byte_striping_e.v:24" *)
    casez (valid_in)

      1'h1:
          (* src = "byte_striping_e.v:25" *)
          casez (contador)

            1'h0:
              begin
                _05_ = 1'h1;
                _06_ = Data_in;
                _08_ = 1'h1;
              end

            1'h1:
              begin
                _05_ = 1'h0;
                _07_ = Data_in;
                _09_ = 1'h1;
              end
            default:
;
          endcase

      default:
        begin
          _08_ = 1'h0;
          _06_ = 32'd0;
          (* src = "byte_striping_e.v:43" *)
          casez (_11_)

            1'h1:
              begin
                _07_ = 32'd0;
                _09_ = 1'h0;
              end
            default:
;
          endcase
        end
    endcase
  end
  always @(posedge clk_2f_e) begin
      valid_1_c <= _09_;
      lane_1_c <= _07_;
      contador <= _05_;
      valid_0_c <= _08_;
      lane_0_c <= _06_;
  end
endmodule
module byte_striping_e(clk_2f_e, reset, valid_in, Data_in, valid_0_c, lane_0_c, valid_1_c, lane_1_c);

  (* src = "byte_striping_e.v:13" *)
  reg _00_;
  (* src = "byte_striping_e.v:13" *)
  reg [31:0] _01_;
  (* src = "byte_striping_e.v:13" *)
  reg [31:0] _02_;
  (* src = "byte_striping_e.v:13" *)
  reg _03_;
  (* src = "byte_striping_e.v:13" *)
  reg _04_;
  (* src = "byte_striping_e.v:23" *)
  reg _05_;
  (* src = "byte_striping_e.v:23" *)
  reg [31:0] _06_;
  (* src = "byte_striping_e.v:23" *)
  reg [31:0] _07_;
  (* src = "byte_striping_e.v:23" *)
  reg _08_;
  (* src = "byte_striping_e.v:23" *)
  reg _09_;
  (* src = "byte_striping_e.v:14" *)
  wire _10_;
  (* src = "byte_striping_e.v:43" *)
  wire _11_;
  (* src = "byte_striping_e.v:5" *)
  input [31:0] Data_in;
  (* src = "byte_striping_e.v:2" *)
  input clk_2f_e;
  (* src = "byte_striping_e.v:11" *)
  reg contador;
  (* src = "byte_striping_e.v:7" *)
  output [31:0] lane_0_c;
  reg [31:0] lane_0_c;
  (* src = "byte_striping_e.v:9" *)
  output [31:0] lane_1_c;
  reg [31:0] lane_1_c;
  (* src = "byte_striping_e.v:3" *)
  input reset;
  (* src = "byte_striping_e.v:6" *)
  output valid_0_c;
  reg valid_0_c;
  (* src = "byte_striping_e.v:8" *)
  output valid_1_c;
  reg valid_1_c;
  (* src = "byte_striping_e.v:4" *)
  input valid_in;
  assign _10_ = ~(* src = "byte_striping_e.v:14" *) reset;
  assign _11_ = ~(* src = "byte_striping_e.v:43" *) valid_0_c;
  always @* begin
    _04_ = valid_1_c;
    _02_ = lane_1_c;
    _00_ = contador;
    _03_ = valid_0_c;
    _01_ = lane_0_c;
    (* src = "byte_striping_e.v:14" *)
    casez (_10_)

      1'h1:
        begin
          _03_ = 1'h0;
          _01_ = 32'd0;
          _04_ = 1'h0;
          _02_ = 32'd0;
          _00_ = 1'h0;
        end
      default:
;
    endcase
  end
  always @* begin
      valid_1_c <= _04_;
      lane_1_c <= _02_;
      contador <= _00_;
      valid_0_c <= _03_;
      lane_0_c <= _01_;
  end
  always @* begin
    _09_ = valid_1_c;
    _07_ = lane_1_c;
    _05_ = contador;
    _08_ = valid_0_c;
    _06_ = lane_0_c;
    (* src = "byte_striping_e.v:24" *)
    casez (valid_in)

      1'h1:
          (* src = "byte_striping_e.v:25" *)
          casez (contador)

            1'h0:
              begin
                _05_ = 1'h1;
                _06_ = Data_in;
                _08_ = 1'h1;
              end

            1'h1:
              begin
                _05_ = 1'h0;
                _07_ = Data_in;
                _09_ = 1'h1;
              end
            default:
;
          endcase

      default:
        begin
          _08_ = 1'h0;
          _06_ = 32'd0;
          (* src = "byte_striping_e.v:43" *)
          casez (_11_)

            1'h1:
              begin
                _07_ = 32'd0;
                _09_ = 1'h0;
              end
            default:
;
          endcase
        end
    endcase
  end
  always @(posedge clk_2f_e) begin
      valid_1_c <= _09_;
      lane_1_c <= _07_;
      contador <= _05_;
      valid_0_c <= _08_;
      lane_0_c <= _06_;
  end
endmodule