data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:170: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc7_1_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_clk_gclk_inv_r90_224x\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_clk_gclk_inv_r90_224x.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_clk_gclk_inv_r90_224x.sv\n             bw_clk_gclk_inv_r90_224x\n             bw_clk_gclk_inv_r90_224x.v\n             bw_clk_gclk_inv_r90_224x.sv\n             obj_dir/bw_clk_gclk_inv_r90_224x\n             obj_dir/bw_clk_gclk_inv_r90_224x.v\n             obj_dir/bw_clk_gclk_inv_r90_224x.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:173: Cannot find file containing module: 'bw_clk_gclk_inv_r90_256x'\nbw_clk_gclk_inv_r90_256x xc10a_0_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:176: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc7_2_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:179: Cannot find file containing module: 'bw_clk_gclk_inv_r90_192x'\nbw_clk_gclk_inv_r90_192x xc8_0_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:182: Cannot find file containing module: 'bw_clk_gclk_inv_r90_256x'\nbw_clk_gclk_inv_r90_256x xc10a_1_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:185: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc7_3_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:188: Cannot find file containing module: 'bw_clk_gclk_inv_r90_192x'\nbw_clk_gclk_inv_r90_192x xc10b_0_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:191: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc9_0_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:194: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc7_4_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:197: Cannot find file containing module: 'bw_clk_gclk_inv_r90_192x'\nbw_clk_gclk_inv_r90_192x xc10b_1_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:200: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc9_1_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:203: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc7_5_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:206: Cannot find file containing module: 'bw_clk_gclk_inv_r90_192x'\nbw_clk_gclk_inv_r90_192x xc8_3_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:209: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc7_6_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:212: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc7_7_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:215: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc7_0_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:104: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc7_1_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:107: Cannot find file containing module: 'bw_clk_gclk_inv_r90_256x'\nbw_clk_gclk_inv_r90_256x xc10a_0_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:110: Cannot find file containing module: 'bw_clk_gclk_inv_r90_192x'\nbw_clk_gclk_inv_r90_192x xc8_0_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:113: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc7_2_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:116: Cannot find file containing module: 'bw_clk_gclk_inv_r90_256x'\nbw_clk_gclk_inv_r90_256x xc10a_1_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:119: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc7_3_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:122: Cannot find file containing module: 'bw_clk_gclk_inv_r90_192x'\nbw_clk_gclk_inv_r90_192x xc10b_0_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:125: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc7_4_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:128: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc9_0_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:131: Cannot find file containing module: 'bw_clk_gclk_inv_r90_192x'\nbw_clk_gclk_inv_r90_192x xc10b_1_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:134: Cannot find file containing module: 'bw_clk_gclk_inv_r90_192x'\nbw_clk_gclk_inv_r90_192x xc8_3_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:137: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc7_5_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:140: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc9_1_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:143: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc7_6_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:146: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc7_7_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:149: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc7_0_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:38: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc7_1_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:41: Cannot find file containing module: 'bw_clk_gclk_inv_r90_256x'\nbw_clk_gclk_inv_r90_256x xc10a_0_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:44: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc7_2_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:47: Cannot find file containing module: 'bw_clk_gclk_inv_r90_192x'\nbw_clk_gclk_inv_r90_192x xc8_0_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:50: Cannot find file containing module: 'bw_clk_gclk_inv_r90_256x'\nbw_clk_gclk_inv_r90_256x xc10a_1_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:53: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc7_3_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:56: Cannot find file containing module: 'bw_clk_gclk_inv_r90_192x'\nbw_clk_gclk_inv_r90_192x xc10b_0_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:59: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc7_4_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:62: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc9_0_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:65: Cannot find file containing module: 'bw_clk_gclk_inv_r90_192x'\nbw_clk_gclk_inv_r90_192x xc10b_1_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:68: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc7_5_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:71: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc9_1_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:74: Cannot find file containing module: 'bw_clk_gclk_inv_r90_192x'\nbw_clk_gclk_inv_r90_192x xc8_3_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:77: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc7_6_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:80: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc7_7_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gl_vrt_all.v:83: Cannot find file containing module: 'bw_clk_gclk_inv_r90_224x'\nbw_clk_gclk_inv_r90_224x xc7_0_ (\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 48 error(s)\n"
module bw_clk_gl_vrt1(c12 ,sctag_in ,sctag_out ,c7 );
output [1:0]	sctag_out ;
output [7:0]	c7 ;
input [1:0]	sctag_in ;
input		c12 ;
 
wire [1:0]	c11 ;
wire [3:0]	c8 ;
wire [1:0]	c10 ;
wire [1:0]	c9 ;
 
assign	c8[2] = sctag_in[1] ;
assign	c8[1] = sctag_in[0] ;
assign	sctag_out[1] = c9[1] ;
assign	sctag_out[0] = c9[0] ;
 
bw_clk_gclk_inv_r90_224x xc7_1_ (
     .clkout          (c7[1] ),
     .clkin           (c8[0] ) );
bw_clk_gclk_inv_r90_256x xc10a_0_ (
     .clkout          (c11[0] ),
     .clkin           (c12 ) );
bw_clk_gclk_inv_r90_224x xc7_2_ (
     .clkout          (c7[2] ),
     .clkin           (c8[1] ) );
bw_clk_gclk_inv_r90_192x xc8_0_ (
     .clkout          (c8[0] ),
     .clkin           (c9[0] ) );
bw_clk_gclk_inv_r90_256x xc10a_1_ (
     .clkout          (c11[1] ),
     .clkin           (c12 ) );
bw_clk_gclk_inv_r90_224x xc7_3_ (
     .clkout          (c7[3] ),
     .clkin           (c8[1] ) );
bw_clk_gclk_inv_r90_192x xc10b_0_ (
     .clkout          (c10[0] ),
     .clkin           (c11[0] ) );
bw_clk_gclk_inv_r90_224x xc7_4_ (
     .clkout          (c7[4] ),
     .clkin           (c8[2] ) );
bw_clk_gclk_inv_r90_224x xc9_0_ (
     .clkout          (c9[0] ),
     .clkin           (c10[0] ) );
bw_clk_gclk_inv_r90_192x xc10b_1_ (
     .clkout          (c10[1] ),
     .clkin           (c11[1] ) );
bw_clk_gclk_inv_r90_224x xc7_5_ (
     .clkout          (c7[5] ),
     .clkin           (c8[2] ) );
bw_clk_gclk_inv_r90_224x xc9_1_ (
     .clkout          (c9[1] ),
     .clkin           (c10[1] ) );
bw_clk_gclk_inv_r90_192x xc8_3_ (
     .clkout          (c8[3] ),
     .clkin           (c9[1] ) );
bw_clk_gclk_inv_r90_224x xc7_6_ (
     .clkout          (c7[6] ),
     .clkin           (c8[3] ) );
bw_clk_gclk_inv_r90_224x xc7_7_ (
     .clkout          (c7[7] ),
     .clkin           (c8[3] ) );
bw_clk_gclk_inv_r90_224x xc7_0_ (
     .clkout          (c7[0] ),
     .clkin           (c8[0] ) );
endmodule
module bw_clk_gl_vrt1(c12 ,sctag_in ,sctag_out ,c7 );

output [1:0]	sctag_out ;
output [7:0]	c7 ;
input [1:0]	sctag_in ;
input		c12 ;
 
wire [1:0]	c11 ;
wire [3:0]	c8 ;
wire [1:0]	c10 ;
wire [1:0]	c9 ;
 
assign	c8[2] = sctag_in[1] ;
assign	c8[1] = sctag_in[0] ;
assign	sctag_out[1] = c9[1] ;
assign	sctag_out[0] = c9[0] ;
 
bw_clk_gclk_inv_r90_224x xc7_1_ (
     .clkout          (c7[1] ),
     .clkin           (c8[0] ) );
bw_clk_gclk_inv_r90_256x xc10a_0_ (
     .clkout          (c11[0] ),
     .clkin           (c12 ) );
bw_clk_gclk_inv_r90_224x xc7_2_ (
     .clkout          (c7[2] ),
     .clkin           (c8[1] ) );
bw_clk_gclk_inv_r90_192x xc8_0_ (
     .clkout          (c8[0] ),
     .clkin           (c9[0] ) );
bw_clk_gclk_inv_r90_256x xc10a_1_ (
     .clkout          (c11[1] ),
     .clkin           (c12 ) );
bw_clk_gclk_inv_r90_224x xc7_3_ (
     .clkout          (c7[3] ),
     .clkin           (c8[1] ) );
bw_clk_gclk_inv_r90_192x xc10b_0_ (
     .clkout          (c10[0] ),
     .clkin           (c11[0] ) );
bw_clk_gclk_inv_r90_224x xc7_4_ (
     .clkout          (c7[4] ),
     .clkin           (c8[2] ) );
bw_clk_gclk_inv_r90_224x xc9_0_ (
     .clkout          (c9[0] ),
     .clkin           (c10[0] ) );
bw_clk_gclk_inv_r90_192x xc10b_1_ (
     .clkout          (c10[1] ),
     .clkin           (c11[1] ) );
bw_clk_gclk_inv_r90_224x xc7_5_ (
     .clkout          (c7[5] ),
     .clkin           (c8[2] ) );
bw_clk_gclk_inv_r90_224x xc9_1_ (
     .clkout          (c9[1] ),
     .clkin           (c10[1] ) );
bw_clk_gclk_inv_r90_192x xc8_3_ (
     .clkout          (c8[3] ),
     .clkin           (c9[1] ) );
bw_clk_gclk_inv_r90_224x xc7_6_ (
     .clkout          (c7[6] ),
     .clkin           (c8[3] ) );
bw_clk_gclk_inv_r90_224x xc7_7_ (
     .clkout          (c7[7] ),
     .clkin           (c8[3] ) );
bw_clk_gclk_inv_r90_224x xc7_0_ (
     .clkout          (c7[0] ),
     .clkin           (c8[0] ) );
endmodule