data/full_repos/permissive/437204475/common/id/regfile.v
1: b'%Error: data/full_repos/permissive/437204475/common/id/regfile.v:3: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/437204475/common/id,data/full_repos/permissive/437204475/defines.v\n             data/full_repos/permissive/437204475/common/id,data/full_repos/permissive/437204475/defines.v.v\n             data/full_repos/permissive/437204475/common/id,data/full_repos/permissive/437204475/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/437204475/common/id/regfile.v:6: Define or directive not defined: \'`REG_ADDR_W\'\n    parameter RW = `REG_ADDR_W,\n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/common/id/regfile.v:6: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    parameter RW = `REG_ADDR_W,\n                              ^\n%Error: data/full_repos/permissive/437204475/common/id/regfile.v:7: Define or directive not defined: \'`WORD_WIDTH\'\n    parameter W = `WORD_WIDTH\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/common/id/regfile.v:8: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n) (\n^\n%Error: data/full_repos/permissive/437204475/common/id/regfile.v:11: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire rs_en,\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/common/id/regfile.v:12: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[RW-1:0] rs_addr,\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/common/id/regfile.v:13: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg[W-1:0] rs_data,\n    ^~~~~~\n%Error: data/full_repos/permissive/437204475/common/id/regfile.v:14: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input wire rt_en,\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/common/id/regfile.v:15: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[RW-1:0] rt_addr,\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/common/id/regfile.v:16: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg[W-1:0] rt_data,\n    ^~~~~~\n%Error: data/full_repos/permissive/437204475/common/id/regfile.v:18: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input wire write_en,\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/common/id/regfile.v:19: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[RW-1:0] write_addr,\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/common/id/regfile.v:20: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[W-1:0] write_data\n    ^~~~~\n%Error: data/full_repos/permissive/437204475/common/id/regfile.v:21: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/437204475/common/id/regfile.v:26: syntax error, unexpected always\n    always @(posedge clk) begin\n    ^~~~~~\n%Error: data/full_repos/permissive/437204475/common/id/regfile.v:27: Define or directive not defined: \'`REG_ZERO\'\n        if (!rst && write_en && write_addr != `REG_ZERO) begin\n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/437204475/common/id/regfile.v:33: Define or directive not defined: \'`REG_ZERO\'\n        if (rst || rs_addr == `REG_ZERO) begin\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/437204475/common/id/regfile.v:34: Define or directive not defined: \'`ZERO_WORD\'\n            rs_data <= `ZERO_WORD;\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/common/id/regfile.v:40: Define or directive not defined: \'`ZERO_WORD\'\n            rs_data <= `ZERO_WORD;\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/common/id/regfile.v:45: Define or directive not defined: \'`REG_ZERO\'\n        if (rst || rt_addr == `REG_ZERO) begin\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/437204475/common/id/regfile.v:46: Define or directive not defined: \'`ZERO_WORD\'\n            rt_data <= `ZERO_WORD;\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/common/id/regfile.v:52: Define or directive not defined: \'`ZERO_WORD\'\n            rt_data <= `ZERO_WORD;\n                       ^~~~~~~~~~\n%Error: Exiting due to 23 error(s)\n'
module regfile #(
    parameter RW = `REG_ADDR_W,
    parameter W = `WORD_WIDTH
) (
    input wire clk, rst,

    input wire rs_en,
    input wire[RW-1:0] rs_addr,
    output reg[W-1:0] rs_data,
    input wire rt_en,
    input wire[RW-1:0] rt_addr,
    output reg[W-1:0] rt_data,

    input wire write_en,
    input wire[RW-1:0] write_addr,
    input wire[W-1:0] write_data
);

    reg[W-1:0] regs[W-1:0];


    always @(posedge clk) begin
        if (!rst && write_en && write_addr != `REG_ZERO) begin
            regs[write_addr] <= write_data;
        end
    end

    always @(*) begin
        if (rst || rs_addr == `REG_ZERO) begin
            rs_data <= `ZERO_WORD;
        end
        else if (rs_en) begin
            rs_data <= regs[rs_addr];
        end
        else begin
            rs_data <= `ZERO_WORD;
        end
    end

    always @(*) begin
        if (rst || rt_addr == `REG_ZERO) begin
            rt_data <= `ZERO_WORD;
        end
        else if (rt_en) begin
            rt_data <= regs[rt_addr];
        end
        else begin
            rt_data <= `ZERO_WORD;
        end
    end
endmodule
module regfile #(
    parameter RW = `REG_ADDR_W,
    parameter W = `WORD_WIDTH
) (
    input wire clk, rst,

    input wire rs_en,
    input wire[RW-1:0] rs_addr,
    output reg[W-1:0] rs_data,
    input wire rt_en,
    input wire[RW-1:0] rt_addr,
    output reg[W-1:0] rt_data,

    input wire write_en,
    input wire[RW-1:0] write_addr,
    input wire[W-1:0] write_data
);


    reg[W-1:0] regs[W-1:0];


    always @(posedge clk) begin
        if (!rst && write_en && write_addr != `REG_ZERO) begin
            regs[write_addr] <= write_data;
        end
    end

    always @(*) begin
        if (rst || rs_addr == `REG_ZERO) begin
            rs_data <= `ZERO_WORD;
        end
        else if (rs_en) begin
            rs_data <= regs[rs_addr];
        end
        else begin
            rs_data <= `ZERO_WORD;
        end
    end

    always @(*) begin
        if (rst || rt_addr == `REG_ZERO) begin
            rt_data <= `ZERO_WORD;
        end
        else if (rt_en) begin
            rt_data <= regs[rt_addr];
        end
        else begin
            rt_data <= `ZERO_WORD;
        end
    end
endmodule