data/full_repos/permissive/411838135/rv/synth/vsram.v
1: b'%Error: No top level module found\n%Error: Exiting due to 1 error(s)\n'
module dc1_data(input [5:0]addra,
                input [5:0]addrb,
                input clka,
                input clkb,
                input [511:0]dina,
                input [511:0]dinb,
                output [511:0]douta,
                output [511:0]doutb,
		input [63:0]wea,
		input [63:0]web);



        reg [6-1:0]r_addra;
        reg [6-1:0]r_addrb;
	always @(posedge clka)
		r_addra <= addra;
	always @(posedge clkb)
		r_addrb <= addrb;

	reg 	[512-1:0]mem[0:63];
	generate

		genvar I;
		for (I =0; I <64; I=I+1) begin
			always @(posedge clka)
			if (wea[I])
				mem[addra][I*8+7:I*8] <= dina[I*8+7:I*8];

			always @(posedge clkb)
			if (web[I])
				mem[addrb][I*8+7:I*8] <= dinb[I*8+7:I*8];
		end

	endgenerate


	reg [512-1:0]outa;
	assign douta = outa;
	always @(*)
	if (clka)
		outa = mem[r_addra];

	reg [512-1:0]outb;
	assign doutb = outb;
	always @(*)
	if (clkb)
		outb = mem[r_addrb];

endmodule
module dc1_data(input [5:0]addra,
                input [5:0]addrb,
                input clka,
                input clkb,
                input [511:0]dina,
                input [511:0]dinb,
                output [511:0]douta,
                output [511:0]doutb,
		input [63:0]wea,
		input [63:0]web);




        reg [6-1:0]r_addra;
        reg [6-1:0]r_addrb;
	always @(posedge clka)
		r_addra <= addra;
	always @(posedge clkb)
		r_addrb <= addrb;

	reg 	[512-1:0]mem[0:63];
	generate

		genvar I;
		for (I =0; I <64; I=I+1) begin
			always @(posedge clka)
			if (wea[I])
				mem[addra][I*8+7:I*8] <= dina[I*8+7:I*8];

			always @(posedge clkb)
			if (web[I])
				mem[addrb][I*8+7:I*8] <= dinb[I*8+7:I*8];
		end

	endgenerate


	reg [512-1:0]outa;
	assign douta = outa;
	always @(*)
	if (clka)
		outa = mem[r_addra];

	reg [512-1:0]outb;
	assign doutb = outb;
	always @(*)
	if (clkb)
		outb = mem[r_addrb];

endmodule