data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_schmitt.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_schmitt.v:27: Cannot find include file: sys.h\n`include "sys.h"  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: Exiting due to 1 error(s)\n'
module bw_io_schmitt(


    out,

   in, 

   vddo );

output	out;
input	in;
inout	vddo;

wire out = in;

endmodule
module bw_io_schmitt(


    out,

   in, 

   vddo );


output	out;
input	in;
inout	vddo;

wire out = in;

endmodule