data/full_repos/permissive/423547971/FPGA Projects/Traffic_Controller_Basys3/sw_debounce.v
1: b'%Error: Cannot find file containing module: Projects/Traffic_Controller_Basys3,data/full_repos/permissive/423547971\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/Traffic_Controller_Basys3,data/full_repos/permissive/423547971\n             data/full_repos/permissive/423547971/FPGA/Projects/Traffic_Controller_Basys3,data/full_repos/permissive/423547971.v\n             data/full_repos/permissive/423547971/FPGA/Projects/Traffic_Controller_Basys3,data/full_repos/permissive/423547971.sv\n             Projects/Traffic_Controller_Basys3,data/full_repos/permissive/423547971\n             Projects/Traffic_Controller_Basys3,data/full_repos/permissive/423547971.v\n             Projects/Traffic_Controller_Basys3,data/full_repos/permissive/423547971.sv\n             obj_dir/Projects/Traffic_Controller_Basys3,data/full_repos/permissive/423547971\n             obj_dir/Projects/Traffic_Controller_Basys3,data/full_repos/permissive/423547971.v\n             obj_dir/Projects/Traffic_Controller_Basys3,data/full_repos/permissive/423547971.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: Projects/Traffic_Controller_Basys3/sw_debounce.v\n%Error: Exiting due to 3 error(s)\n'
module sw_debounce(
    input clk,      
    input btn_in,
    output btn_out
    );
    
    reg t0, t1, t2;
    
    always @(posedge clk) begin
        t0 <= btn_in;
        t1 <= t0;
        t2 <= t1;
    end
    
    assign btn_out = t2;
    
endmodule
module sw_debounce(
    input clk,      
    input btn_in,
    output btn_out
    );

    
    reg t0, t1, t2;
    
    always @(posedge clk) begin
        t0 <= btn_in;
        t1 <= t0;
        t2 <= t1;
    end
    
    assign btn_out = t2;
    
endmodule