data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/tx_port_buffer_32.v
1: b'%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa/tx_port_buffer_32.v:65: Cannot find include file: functions.vh\n`include "functions.vh" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa,data/full_repos/permissive/498471995/functions.vh\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa,data/full_repos/permissive/498471995/functions.vh.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_riffa_dma_v1_0_0/hdl/riffa,data/full_repos/permissive/498471995/functions.vh.sv\n             functions.vh\n             functions.vh.v\n             functions.vh.sv\n             obj_dir/functions.vh\n             obj_dir/functions.vh.v\n             obj_dir/functions.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module tx_port_buffer_32 #(
	parameter C_FIFO_DATA_WIDTH = 9'd32,
	parameter C_FIFO_DEPTH = 512,

	parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1)
)
(
	input RST,
	input CLK,

	input [C_FIFO_DATA_WIDTH-1:0] WR_DATA,
	input WR_EN,
	output [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT,

	output [C_FIFO_DATA_WIDTH-1:0] RD_DATA,
	input RD_EN
);

`include "functions.vh"

reg 								rFifoRdEn=0, _rFifoRdEn=0;
reg		[C_FIFO_DATA_WIDTH-1:0]		rFifoData={C_FIFO_DATA_WIDTH{1'd0}}, _rFifoData={C_FIFO_DATA_WIDTH{1'd0}};
wire	[C_FIFO_DATA_WIDTH-1:0]		wFifoData;

assign RD_DATA = rFifoData;



always @ (posedge CLK) begin
	rFifoRdEn <= #1 (RST ? 1'd0 : _rFifoRdEn);
end

always @ (*) begin
	_rFifoRdEn = RD_EN;
end



(* RAM_STYLE="BLOCK" *)
sync_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) fifo (
	.CLK(CLK),
	.RST(RST),
	.WR_EN(WR_EN),
	.WR_DATA(WR_DATA),
	.FULL(),
	.COUNT(WR_COUNT),
	.RD_EN(rFifoRdEn),
	.RD_DATA(wFifoData),
	.EMPTY()
);



always @ (posedge CLK) begin
	rFifoData <= #1 _rFifoData;
end

always @ (*) begin
	_rFifoData = wFifoData;
end


endmodule
module tx_port_buffer_32 #(
	parameter C_FIFO_DATA_WIDTH = 9'd32,
	parameter C_FIFO_DEPTH = 512,

	parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1)
)
(
	input RST,
	input CLK,

	input [C_FIFO_DATA_WIDTH-1:0] WR_DATA,
	input WR_EN,
	output [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT,

	output [C_FIFO_DATA_WIDTH-1:0] RD_DATA,
	input RD_EN
);


`include "functions.vh"

reg 								rFifoRdEn=0, _rFifoRdEn=0;
reg		[C_FIFO_DATA_WIDTH-1:0]		rFifoData={C_FIFO_DATA_WIDTH{1'd0}}, _rFifoData={C_FIFO_DATA_WIDTH{1'd0}};
wire	[C_FIFO_DATA_WIDTH-1:0]		wFifoData;

assign RD_DATA = rFifoData;



always @ (posedge CLK) begin
	rFifoRdEn <= #1 (RST ? 1'd0 : _rFifoRdEn);
end

always @ (*) begin
	_rFifoRdEn = RD_EN;
end



(* RAM_STYLE="BLOCK" *)
sync_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) fifo (
	.CLK(CLK),
	.RST(RST),
	.WR_EN(WR_EN),
	.WR_DATA(WR_DATA),
	.FULL(),
	.COUNT(WR_COUNT),
	.RD_EN(rFifoRdEn),
	.RD_DATA(wFifoData),
	.EMPTY()
);



always @ (posedge CLK) begin
	rFifoData <= #1 _rFifoData;
end

always @ (*) begin
	_rFifoData = wFifoData;
end


endmodule