data/full_repos/permissive/458737381/src/verilog-parser/tests/sctag_cpx_rptr_3.v
data/verilator_xmls/f6e34cdd-c3d1-4968-9162-93432c8c0fa2.xml
module sctag_cpx_rptr_3 (

   sig_buf, 

   sig
   );



output	[163:0]	sig_buf;
input	[163:0]	sig;


assign	sig_buf  = sig;

















endmodule
module sctag_cpx_rptr_3 (

   sig_buf, 

   sig
   );




output	[163:0]	sig_buf;
input	[163:0]	sig;


assign	sig_buf  = sig;

















endmodule