data/full_repos/permissive/435890256/test_operator/test.sv
data/verilator_xmls/33cc43f0-c6a7-41e1-a3f8-74491489b7b7.xml
module test(
  input logic [31:0] a,
  input logic [4:0] shamt,
  output logic [31:0] b
);

logic signed [31:0] a_s;

assign a_s = a;

always_comb begin : test
  b   <= a_s >>> shamt;
end

endmodule
module test(
  input logic [31:0] a,
  input logic [4:0] shamt,
  output logic [31:0] b
);


logic signed [31:0] a_s;

assign a_s = a;

always_comb begin : test
  b   <= a_s >>> shamt;
end

endmodule