data/full_repos/permissive/521337848/Hardware/procesor/aluX.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/521337848/Hardware/procesor/aluX.v:111: Cell has missing pin: \'sreg3\'\ncollectsubreg csr(.bank(bank[1]),\n              ^~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/521337848/Hardware/procesor/aluX.v:111: Cell has missing pin: \'sreg4\'\ncollectsubreg csr(.bank(bank[1]),\n              ^~~\n%Error: Exiting due to 2 warning(s)\n'
module selector(
	input[15:0] ireg1,
	input[15:0] ireg2,
	input[15:0] ireg3,
	input[15:0] ireg4,
	
	input[1:0] reg1,
	input[1:0] reg2,
	
	output reg[15:0] num1,
	output reg[15:0] num2
);

always@(*)begin
	case(reg1) 
		0: num1 = ireg1;
		1: num1 = ireg2;
		2: num1 = ireg3;
		3: num1 = ireg4;
		default:;
	endcase
end

always@(*)begin
	case(reg2) 
		0: num2 = ireg1;
		1: num2 = ireg2;
		2: num2 = ireg3;
		3: num2 = ireg4;
		default:;
	endcase
	
end

endmodule
module selector(
	input[15:0] ireg1,
	input[15:0] ireg2,
	input[15:0] ireg3,
	input[15:0] ireg4,
	
	input[1:0] reg1,
	input[1:0] reg2,
	
	output reg[15:0] num1,
	output reg[15:0] num2
);


always@(*)begin
	case(reg1) 
		0: num1 = ireg1;
		1: num1 = ireg2;
		2: num1 = ireg3;
		3: num1 = ireg4;
		default:;
	endcase
end

always@(*)begin
	case(reg2) 
		0: num2 = ireg1;
		1: num2 = ireg2;
		2: num2 = ireg3;
		3: num2 = ireg4;
		default:;
	endcase
	
end

endmodule