data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/dv/uvm/icache/dv/ibex_icache_mem_agent/ibex_icache_mem_model.sv
1: b'%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/dv/uvm/icache/dv/ibex_icache_mem_agent/ibex_icache_mem_model.sv:24: Unsupported: classes\nclass ibex_icache_mem_model #(parameter int unsigned BusWidth = 32) extends uvm_object;\n^~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/dv/uvm/icache/dv/ibex_icache_mem_agent/ibex_icache_mem_model.sv:24: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass ibex_icache_mem_model #(parameter int unsigned BusWidth = 32) extends uvm_object;\n                                                                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/dv/uvm/icache/dv/ibex_icache_mem_agent/ibex_icache_mem_model.sv:30: syntax error, unexpected protected\n  protected bit no_mem_errs;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/dv/uvm/icache/dv/ibex_icache_mem_agent/ibex_icache_mem_model.sv:32: Unsupported: new constructor\n  function new(string       name="",\n           ^~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/dv/uvm/icache/dv/ibex_icache_mem_agent/ibex_icache_mem_model.sv:39: Define or directive not defined: \'`uvm_object_utils_begin\'\n  `uvm_object_utils_begin(ibex_icache_mem_model)\n  ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/dv/uvm/icache/dv/ibex_icache_mem_agent/ibex_icache_mem_model.sv:39: syntax error, unexpected \'(\'\n  `uvm_object_utils_begin(ibex_icache_mem_model)\n                          ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/dv/uvm/icache/dv/ibex_icache_mem_agent/ibex_icache_mem_model.sv:40: Define or directive not defined: \'`uvm_field_int\'\n    `uvm_field_int (no_pmp_errs, UVM_DEFAULT)\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/dv/uvm/icache/dv/ibex_icache_mem_agent/ibex_icache_mem_model.sv:41: Define or directive not defined: \'`uvm_field_int\'\n    `uvm_field_int (no_mem_errs, UVM_DEFAULT)\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/dv/uvm/icache/dv/ibex_icache_mem_agent/ibex_icache_mem_model.sv:42: Define or directive not defined: \'`uvm_object_utils_end\'\n  `uvm_object_utils_end\n  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/dv/uvm/icache/dv/ibex_icache_mem_agent/ibex_icache_mem_model.sv:130: syntax error, unexpected endclass\nendclass\n^~~~~~~~\n%Error: Exiting due to 10 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
function automatic logic [BusWidth-1:0] read_data(bit [31:0] seed, logic [31:0] address);
    logic [BusWidth-1:0] acc, word_data;
    int                  word_count, lo_idx, lo_bit;
    logic [29:0]         word_addr;



    word_count = ((BusWidth + 31) / 32) + ((address & 32'd3) ? 1 : 0);


    word_addr = address >> 2;


    acc = 0;


    lo_bit = 0;

    for (int i = 0; i < word_count; i++) begin


      word_data = 0;
      word_data[31:0] = read_word(seed, word_addr + i[29:0]);



      lo_idx = (i > 0) ? 0 : (i & 3);



      acc = acc | (((word_data >> lo_idx) << lo_idx) << lo_bit);

      lo_bit = lo_bit + 32;
    end

    return acc;
  endfunction
function automatic logic [BusWidth-1:0] read_data(bit [31:0] seed, logic [31:0] address);

    logic [BusWidth-1:0] acc, word_data;
    int                  word_count, lo_idx, lo_bit;
    logic [29:0]         word_addr;



    word_count = ((BusWidth + 31) / 32) + ((address & 32'd3) ? 1 : 0);


    word_addr = address >> 2;


    acc = 0;


    lo_bit = 0;

    for (int i = 0; i < word_count; i++) begin


      word_data = 0;
      word_data[31:0] = read_word(seed, word_addr + i[29:0]);



      lo_idx = (i > 0) ? 0 : (i & 3);



      acc = acc | (((word_data >> lo_idx) << lo_idx) << lo_bit);

      lo_bit = lo_bit + 32;
    end

    return acc;
  endfunction