data/full_repos/permissive/515133384/Verilog Code for Design part.v
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/515133384/Verilog\n        ... Looked in:\n             data/full_repos/permissive/515133384,data/full_repos/permissive/515133384/data/full_repos/permissive/515133384/Verilog\n             data/full_repos/permissive/515133384,data/full_repos/permissive/515133384/data/full_repos/permissive/515133384/Verilog.v\n             data/full_repos/permissive/515133384,data/full_repos/permissive/515133384/data/full_repos/permissive/515133384/Verilog.sv\n             data/full_repos/permissive/515133384/Verilog\n             data/full_repos/permissive/515133384/Verilog.v\n             data/full_repos/permissive/515133384/Verilog.sv\n             obj_dir/data/full_repos/permissive/515133384/Verilog\n             obj_dir/data/full_repos/permissive/515133384/Verilog.v\n             obj_dir/data/full_repos/permissive/515133384/Verilog.sv\n%Error: Cannot find file containing module: Code\n%Error: Cannot find file containing module: for\n%Error: Cannot find file containing module: Design\n%Error: Cannot find file containing module: part.v\n%Error: Exiting due to 5 error(s)\n'
module mux2x1 #(parameter N=1) (I0,I1,S0,out);
 
  input [N:0]I0;
  input [N:0]I1;
  input S0;
  output reg[N:0]out;


always @ (I0 or I1 or S0 )
begin
case (S0)
0:out<=I0;
1:out<=I1;
endcase


end
endmodule
module mux2x1 #(parameter N=1) (I0,I1,S0,out);

 
  input [N:0]I0;
  input [N:0]I1;
  input S0;
  output reg[N:0]out;


always @ (I0 or I1 or S0 )
begin
case (S0)
0:out<=I0;
1:out<=I1;
endcase


end
endmodule