data/full_repos/permissive/452098851/tutorial/demo_add/bdw_work/wrappers/dut_cosim.v
1: b'%Error: data/full_repos/permissive/452098851/tutorial/demo_add/bdw_work/wrappers/dut_cosim.v:31: Cannot find include file: hub.v\n `include "hub.v" \n          ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/452098851/tutorial/demo_add/bdw_work/wrappers,data/full_repos/permissive/452098851/hub.v\n             data/full_repos/permissive/452098851/tutorial/demo_add/bdw_work/wrappers,data/full_repos/permissive/452098851/hub.v.v\n             data/full_repos/permissive/452098851/tutorial/demo_add/bdw_work/wrappers,data/full_repos/permissive/452098851/hub.v.sv\n             hub.v\n             hub.v.v\n             hub.v.sv\n             obj_dir/hub.v\n             obj_dir/hub.v.v\n             obj_dir/hub.v.sv\n%Error: data/full_repos/permissive/452098851/tutorial/demo_add/bdw_work/wrappers/dut_cosim.v:69: syntax error, unexpected \'@\'\n         @( clk_initialized );\n         ^\n%Error: data/full_repos/permissive/452098851/tutorial/demo_add/bdw_work/wrappers/dut_cosim.v:93: syntax error, unexpected \'@\'\n         @( clk_started );\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/452098851/tutorial/demo_add/bdw_work/wrappers/dut_cosim.v:97: Unsupported: Ignoring delay on this delayed statement.\n         #clk_firstHalf;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/452098851/tutorial/demo_add/bdw_work/wrappers/dut_cosim.v:109: Unsupported: Ignoring delay on this delayed statement.\n         #clk_secondHalf;\n         ^\n%Error: data/full_repos/permissive/452098851/tutorial/demo_add/bdw_work/wrappers/dut_cosim.v:140: syntax error, unexpected \'@\'\n         @( rst_initialized );\n         ^\n%Error: data/full_repos/permissive/452098851/tutorial/demo_add/bdw_work/wrappers/dut_cosim.v:164: syntax error, unexpected \'@\'\n         @( rst_started );\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/452098851/tutorial/demo_add/bdw_work/wrappers/dut_cosim.v:168: Unsupported: Ignoring delay on this delayed statement.\n         #rst_firstHalf;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/452098851/tutorial/demo_add/bdw_work/wrappers/dut_cosim.v:180: Unsupported: Ignoring delay on this delayed statement.\n         #rst_secondHalf;\n         ^\n%Error: data/full_repos/permissive/452098851/tutorial/demo_add/bdw_work/wrappers/dut_cosim.v:211: syntax error, unexpected \'@\'\n         @( din_1_vld_initialized );\n         ^\n%Error: data/full_repos/permissive/452098851/tutorial/demo_add/bdw_work/wrappers/dut_cosim.v:235: syntax error, unexpected \'@\'\n         @( din_1_vld_started );\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/452098851/tutorial/demo_add/bdw_work/wrappers/dut_cosim.v:239: Unsupported: Ignoring delay on this delayed statement.\n         #din_1_vld_firstHalf;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/452098851/tutorial/demo_add/bdw_work/wrappers/dut_cosim.v:251: Unsupported: Ignoring delay on this delayed statement.\n         #din_1_vld_secondHalf;\n         ^\n%Error: data/full_repos/permissive/452098851/tutorial/demo_add/bdw_work/wrappers/dut_cosim.v:282: syntax error, unexpected \'@\'\n         @( din_2_vld_initialized );\n         ^\n%Error: data/full_repos/permissive/452098851/tutorial/demo_add/bdw_work/wrappers/dut_cosim.v:306: syntax error, unexpected \'@\'\n         @( din_2_vld_started );\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/452098851/tutorial/demo_add/bdw_work/wrappers/dut_cosim.v:310: Unsupported: Ignoring delay on this delayed statement.\n         #din_2_vld_firstHalf;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/452098851/tutorial/demo_add/bdw_work/wrappers/dut_cosim.v:322: Unsupported: Ignoring delay on this delayed statement.\n         #din_2_vld_secondHalf;\n         ^\n%Error: data/full_repos/permissive/452098851/tutorial/demo_add/bdw_work/wrappers/dut_cosim.v:353: syntax error, unexpected \'@\'\n         @( dout_busy_initialized );\n         ^\n%Error: data/full_repos/permissive/452098851/tutorial/demo_add/bdw_work/wrappers/dut_cosim.v:377: syntax error, unexpected \'@\'\n         @( dout_busy_started );\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/452098851/tutorial/demo_add/bdw_work/wrappers/dut_cosim.v:381: Unsupported: Ignoring delay on this delayed statement.\n         #dout_busy_firstHalf;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/452098851/tutorial/demo_add/bdw_work/wrappers/dut_cosim.v:393: Unsupported: Ignoring delay on this delayed statement.\n         #dout_busy_secondHalf;\n         ^\n%Error: Exiting due to 11 error(s), 10 warning(s)\n'
module dut_cosim;

	reg clk;
	reg rst;
	wire din_1_busy;
	reg din_1_vld;
	reg[7:0] din_1_data;
	wire din_2_busy;
	reg din_2_vld;
	reg[7:0] din_2_data;
	reg dout_busy;
	wire dout_vld;
	wire[8:0] dout_data;


	`include "hub.v"

	dut dut0( .clk(clk),
	 .rst(rst),
	 .din_1_busy(din_1_busy),
	 .din_1_vld(din_1_vld),
	 .din_1_data(din_1_data),
	 .din_2_busy(din_2_busy),
	 .din_2_vld(din_2_vld),
	 .din_2_data(din_2_data),
	 .dout_busy(dout_busy),
	 .dout_vld(dout_vld),
	 .dout_data(dout_data) );



	reg clk_firstEdge;
	reg clk_initialized;
	reg clk_started;
	real clk_startTime;
	real clk_firstHalf;
	real clk_secondHalf;
	
	initial begin
	

	    hubSetOption("cycleOnly=1");
	

	    clk_firstEdge = 1'b1;
	    clk_startTime = 0.000;
	    clk_firstHalf = 5.000;
	    clk_secondHalf = 5.000;
	

	    hubScheduleDelayedAssignments;
	
	    while ( clk_initialized !== 1'b1 )
	        @( clk_initialized );
	
	    if ( clk_startTime > 0.0 ) begin
	        clk_started = #clk_startTime 1;
	    end
	    else begin
	        clk_started = 1;
	    end
	end
	

	always @( dut0.clk ) begin
	    if ( clk_started === 1'b1 ) begin
	        if ($time == top.cur_time) top.n_cur_time=top.n_cur_time-1;
	        else top.n_cur_time=0;
	        if (top.n_cur_time==0) begin
	            hubScheduleDelayedAssignments;
	        end
	    end
	end
	
	always begin

	    while ( clk_started !== 1'b1 )
	        @( clk_started );
	
	    clk <= clk_firstEdge;
	    if ( clk_firstHalf > 0.0 ) begin
	        #clk_firstHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	        clk = ~clk_firstEdge;
	    end
	    else begin
	        clk = ~clk_firstEdge;
	    end
	    if ( clk_secondHalf > 0.0 ) begin
	        #clk_secondHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	    end
	end

	reg rst_firstEdge;
	reg rst_initialized;
	reg rst_started;
	real rst_startTime;
	real rst_firstHalf;
	real rst_secondHalf;
	
	initial begin
	

	    hubSetOption("cycleOnly=1");
	

	    rst_firstEdge = 1'b1;
	    rst_startTime = 0.000;
	    rst_firstHalf = 5.000;
	    rst_secondHalf = 5.000;
	

	    hubScheduleDelayedAssignments;
	
	    while ( rst_initialized !== 1'b1 )
	        @( rst_initialized );
	
	    if ( rst_startTime > 0.0 ) begin
	        rst_started = #rst_startTime 1;
	    end
	    else begin
	        rst_started = 1;
	    end
	end
	

	always @( dut0.rst ) begin
	    if ( rst_started === 1'b1 ) begin
	        if ($time == top.cur_time) top.n_cur_time=top.n_cur_time-1;
	        else top.n_cur_time=0;
	        if (top.n_cur_time==0) begin
	            hubScheduleDelayedAssignments;
	        end
	    end
	end
	
	always begin

	    while ( rst_started !== 1'b1 )
	        @( rst_started );
	
	    rst <= rst_firstEdge;
	    if ( rst_firstHalf > 0.0 ) begin
	        #rst_firstHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	        rst = ~rst_firstEdge;
	    end
	    else begin
	        rst = ~rst_firstEdge;
	    end
	    if ( rst_secondHalf > 0.0 ) begin
	        #rst_secondHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	    end
	end

	reg din_1_vld_firstEdge;
	reg din_1_vld_initialized;
	reg din_1_vld_started;
	real din_1_vld_startTime;
	real din_1_vld_firstHalf;
	real din_1_vld_secondHalf;
	
	initial begin
	

	    hubSetOption("cycleOnly=1");
	

	    din_1_vld_firstEdge = 1'b1;
	    din_1_vld_startTime = 0.000;
	    din_1_vld_firstHalf = 5.000;
	    din_1_vld_secondHalf = 5.000;
	

	    hubScheduleDelayedAssignments;
	
	    while ( din_1_vld_initialized !== 1'b1 )
	        @( din_1_vld_initialized );
	
	    if ( din_1_vld_startTime > 0.0 ) begin
	        din_1_vld_started = #din_1_vld_startTime 1;
	    end
	    else begin
	        din_1_vld_started = 1;
	    end
	end
	

	always @( dut0.din_1_vld ) begin
	    if ( din_1_vld_started === 1'b1 ) begin
	        if ($time == top.cur_time) top.n_cur_time=top.n_cur_time-1;
	        else top.n_cur_time=0;
	        if (top.n_cur_time==0) begin
	            hubScheduleDelayedAssignments;
	        end
	    end
	end
	
	always begin

	    while ( din_1_vld_started !== 1'b1 )
	        @( din_1_vld_started );
	
	    din_1_vld <= din_1_vld_firstEdge;
	    if ( din_1_vld_firstHalf > 0.0 ) begin
	        #din_1_vld_firstHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	        din_1_vld = ~din_1_vld_firstEdge;
	    end
	    else begin
	        din_1_vld = ~din_1_vld_firstEdge;
	    end
	    if ( din_1_vld_secondHalf > 0.0 ) begin
	        #din_1_vld_secondHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	    end
	end

	reg din_2_vld_firstEdge;
	reg din_2_vld_initialized;
	reg din_2_vld_started;
	real din_2_vld_startTime;
	real din_2_vld_firstHalf;
	real din_2_vld_secondHalf;
	
	initial begin
	

	    hubSetOption("cycleOnly=1");
	

	    din_2_vld_firstEdge = 1'b1;
	    din_2_vld_startTime = 0.000;
	    din_2_vld_firstHalf = 5.000;
	    din_2_vld_secondHalf = 5.000;
	

	    hubScheduleDelayedAssignments;
	
	    while ( din_2_vld_initialized !== 1'b1 )
	        @( din_2_vld_initialized );
	
	    if ( din_2_vld_startTime > 0.0 ) begin
	        din_2_vld_started = #din_2_vld_startTime 1;
	    end
	    else begin
	        din_2_vld_started = 1;
	    end
	end
	

	always @( dut0.din_2_vld ) begin
	    if ( din_2_vld_started === 1'b1 ) begin
	        if ($time == top.cur_time) top.n_cur_time=top.n_cur_time-1;
	        else top.n_cur_time=0;
	        if (top.n_cur_time==0) begin
	            hubScheduleDelayedAssignments;
	        end
	    end
	end
	
	always begin

	    while ( din_2_vld_started !== 1'b1 )
	        @( din_2_vld_started );
	
	    din_2_vld <= din_2_vld_firstEdge;
	    if ( din_2_vld_firstHalf > 0.0 ) begin
	        #din_2_vld_firstHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	        din_2_vld = ~din_2_vld_firstEdge;
	    end
	    else begin
	        din_2_vld = ~din_2_vld_firstEdge;
	    end
	    if ( din_2_vld_secondHalf > 0.0 ) begin
	        #din_2_vld_secondHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	    end
	end

	reg dout_busy_firstEdge;
	reg dout_busy_initialized;
	reg dout_busy_started;
	real dout_busy_startTime;
	real dout_busy_firstHalf;
	real dout_busy_secondHalf;
	
	initial begin
	

	    hubSetOption("cycleOnly=1");
	

	    dout_busy_firstEdge = 1'b1;
	    dout_busy_startTime = 0.000;
	    dout_busy_firstHalf = 5.000;
	    dout_busy_secondHalf = 5.000;
	

	    hubScheduleDelayedAssignments;
	
	    while ( dout_busy_initialized !== 1'b1 )
	        @( dout_busy_initialized );
	
	    if ( dout_busy_startTime > 0.0 ) begin
	        dout_busy_started = #dout_busy_startTime 1;
	    end
	    else begin
	        dout_busy_started = 1;
	    end
	end
	

	always @( dut0.dout_busy ) begin
	    if ( dout_busy_started === 1'b1 ) begin
	        if ($time == top.cur_time) top.n_cur_time=top.n_cur_time-1;
	        else top.n_cur_time=0;
	        if (top.n_cur_time==0) begin
	            hubScheduleDelayedAssignments;
	        end
	    end
	end
	
	always begin

	    while ( dout_busy_started !== 1'b1 )
	        @( dout_busy_started );
	
	    dout_busy <= dout_busy_firstEdge;
	    if ( dout_busy_firstHalf > 0.0 ) begin
	        #dout_busy_firstHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	        dout_busy = ~dout_busy_firstEdge;
	    end
	    else begin
	        dout_busy = ~dout_busy_firstEdge;
	    end
	    if ( dout_busy_secondHalf > 0.0 ) begin
	        #dout_busy_secondHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	    end
	end


endmodule
module dut_cosim;


	reg clk;
	reg rst;
	wire din_1_busy;
	reg din_1_vld;
	reg[7:0] din_1_data;
	wire din_2_busy;
	reg din_2_vld;
	reg[7:0] din_2_data;
	reg dout_busy;
	wire dout_vld;
	wire[8:0] dout_data;


	`include "hub.v"

	dut dut0( .clk(clk),
	 .rst(rst),
	 .din_1_busy(din_1_busy),
	 .din_1_vld(din_1_vld),
	 .din_1_data(din_1_data),
	 .din_2_busy(din_2_busy),
	 .din_2_vld(din_2_vld),
	 .din_2_data(din_2_data),
	 .dout_busy(dout_busy),
	 .dout_vld(dout_vld),
	 .dout_data(dout_data) );



	reg clk_firstEdge;
	reg clk_initialized;
	reg clk_started;
	real clk_startTime;
	real clk_firstHalf;
	real clk_secondHalf;
	
	initial begin
	

	    hubSetOption("cycleOnly=1");
	

	    clk_firstEdge = 1'b1;
	    clk_startTime = 0.000;
	    clk_firstHalf = 5.000;
	    clk_secondHalf = 5.000;
	

	    hubScheduleDelayedAssignments;
	
	    while ( clk_initialized !== 1'b1 )
	        @( clk_initialized );
	
	    if ( clk_startTime > 0.0 ) begin
	        clk_started = #clk_startTime 1;
	    end
	    else begin
	        clk_started = 1;
	    end
	end
	

	always @( dut0.clk ) begin
	    if ( clk_started === 1'b1 ) begin
	        if ($time == top.cur_time) top.n_cur_time=top.n_cur_time-1;
	        else top.n_cur_time=0;
	        if (top.n_cur_time==0) begin
	            hubScheduleDelayedAssignments;
	        end
	    end
	end
	
	always begin

	    while ( clk_started !== 1'b1 )
	        @( clk_started );
	
	    clk <= clk_firstEdge;
	    if ( clk_firstHalf > 0.0 ) begin
	        #clk_firstHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	        clk = ~clk_firstEdge;
	    end
	    else begin
	        clk = ~clk_firstEdge;
	    end
	    if ( clk_secondHalf > 0.0 ) begin
	        #clk_secondHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	    end
	end

	reg rst_firstEdge;
	reg rst_initialized;
	reg rst_started;
	real rst_startTime;
	real rst_firstHalf;
	real rst_secondHalf;
	
	initial begin
	

	    hubSetOption("cycleOnly=1");
	

	    rst_firstEdge = 1'b1;
	    rst_startTime = 0.000;
	    rst_firstHalf = 5.000;
	    rst_secondHalf = 5.000;
	

	    hubScheduleDelayedAssignments;
	
	    while ( rst_initialized !== 1'b1 )
	        @( rst_initialized );
	
	    if ( rst_startTime > 0.0 ) begin
	        rst_started = #rst_startTime 1;
	    end
	    else begin
	        rst_started = 1;
	    end
	end
	

	always @( dut0.rst ) begin
	    if ( rst_started === 1'b1 ) begin
	        if ($time == top.cur_time) top.n_cur_time=top.n_cur_time-1;
	        else top.n_cur_time=0;
	        if (top.n_cur_time==0) begin
	            hubScheduleDelayedAssignments;
	        end
	    end
	end
	
	always begin

	    while ( rst_started !== 1'b1 )
	        @( rst_started );
	
	    rst <= rst_firstEdge;
	    if ( rst_firstHalf > 0.0 ) begin
	        #rst_firstHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	        rst = ~rst_firstEdge;
	    end
	    else begin
	        rst = ~rst_firstEdge;
	    end
	    if ( rst_secondHalf > 0.0 ) begin
	        #rst_secondHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	    end
	end

	reg din_1_vld_firstEdge;
	reg din_1_vld_initialized;
	reg din_1_vld_started;
	real din_1_vld_startTime;
	real din_1_vld_firstHalf;
	real din_1_vld_secondHalf;
	
	initial begin
	

	    hubSetOption("cycleOnly=1");
	

	    din_1_vld_firstEdge = 1'b1;
	    din_1_vld_startTime = 0.000;
	    din_1_vld_firstHalf = 5.000;
	    din_1_vld_secondHalf = 5.000;
	

	    hubScheduleDelayedAssignments;
	
	    while ( din_1_vld_initialized !== 1'b1 )
	        @( din_1_vld_initialized );
	
	    if ( din_1_vld_startTime > 0.0 ) begin
	        din_1_vld_started = #din_1_vld_startTime 1;
	    end
	    else begin
	        din_1_vld_started = 1;
	    end
	end
	

	always @( dut0.din_1_vld ) begin
	    if ( din_1_vld_started === 1'b1 ) begin
	        if ($time == top.cur_time) top.n_cur_time=top.n_cur_time-1;
	        else top.n_cur_time=0;
	        if (top.n_cur_time==0) begin
	            hubScheduleDelayedAssignments;
	        end
	    end
	end
	
	always begin

	    while ( din_1_vld_started !== 1'b1 )
	        @( din_1_vld_started );
	
	    din_1_vld <= din_1_vld_firstEdge;
	    if ( din_1_vld_firstHalf > 0.0 ) begin
	        #din_1_vld_firstHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	        din_1_vld = ~din_1_vld_firstEdge;
	    end
	    else begin
	        din_1_vld = ~din_1_vld_firstEdge;
	    end
	    if ( din_1_vld_secondHalf > 0.0 ) begin
	        #din_1_vld_secondHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	    end
	end

	reg din_2_vld_firstEdge;
	reg din_2_vld_initialized;
	reg din_2_vld_started;
	real din_2_vld_startTime;
	real din_2_vld_firstHalf;
	real din_2_vld_secondHalf;
	
	initial begin
	

	    hubSetOption("cycleOnly=1");
	

	    din_2_vld_firstEdge = 1'b1;
	    din_2_vld_startTime = 0.000;
	    din_2_vld_firstHalf = 5.000;
	    din_2_vld_secondHalf = 5.000;
	

	    hubScheduleDelayedAssignments;
	
	    while ( din_2_vld_initialized !== 1'b1 )
	        @( din_2_vld_initialized );
	
	    if ( din_2_vld_startTime > 0.0 ) begin
	        din_2_vld_started = #din_2_vld_startTime 1;
	    end
	    else begin
	        din_2_vld_started = 1;
	    end
	end
	

	always @( dut0.din_2_vld ) begin
	    if ( din_2_vld_started === 1'b1 ) begin
	        if ($time == top.cur_time) top.n_cur_time=top.n_cur_time-1;
	        else top.n_cur_time=0;
	        if (top.n_cur_time==0) begin
	            hubScheduleDelayedAssignments;
	        end
	    end
	end
	
	always begin

	    while ( din_2_vld_started !== 1'b1 )
	        @( din_2_vld_started );
	
	    din_2_vld <= din_2_vld_firstEdge;
	    if ( din_2_vld_firstHalf > 0.0 ) begin
	        #din_2_vld_firstHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	        din_2_vld = ~din_2_vld_firstEdge;
	    end
	    else begin
	        din_2_vld = ~din_2_vld_firstEdge;
	    end
	    if ( din_2_vld_secondHalf > 0.0 ) begin
	        #din_2_vld_secondHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	    end
	end

	reg dout_busy_firstEdge;
	reg dout_busy_initialized;
	reg dout_busy_started;
	real dout_busy_startTime;
	real dout_busy_firstHalf;
	real dout_busy_secondHalf;
	
	initial begin
	

	    hubSetOption("cycleOnly=1");
	

	    dout_busy_firstEdge = 1'b1;
	    dout_busy_startTime = 0.000;
	    dout_busy_firstHalf = 5.000;
	    dout_busy_secondHalf = 5.000;
	

	    hubScheduleDelayedAssignments;
	
	    while ( dout_busy_initialized !== 1'b1 )
	        @( dout_busy_initialized );
	
	    if ( dout_busy_startTime > 0.0 ) begin
	        dout_busy_started = #dout_busy_startTime 1;
	    end
	    else begin
	        dout_busy_started = 1;
	    end
	end
	

	always @( dut0.dout_busy ) begin
	    if ( dout_busy_started === 1'b1 ) begin
	        if ($time == top.cur_time) top.n_cur_time=top.n_cur_time-1;
	        else top.n_cur_time=0;
	        if (top.n_cur_time==0) begin
	            hubScheduleDelayedAssignments;
	        end
	    end
	end
	
	always begin

	    while ( dout_busy_started !== 1'b1 )
	        @( dout_busy_started );
	
	    dout_busy <= dout_busy_firstEdge;
	    if ( dout_busy_firstHalf > 0.0 ) begin
	        #dout_busy_firstHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	        dout_busy = ~dout_busy_firstEdge;
	    end
	    else begin
	        dout_busy = ~dout_busy_firstEdge;
	    end
	    if ( dout_busy_secondHalf > 0.0 ) begin
	        #dout_busy_secondHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	    end
	end


endmodule