data/full_repos/permissive/475937410/Ass3/test_ALU.v
1: b'%Error: data/full_repos/permissive/475937410/Ass3/test_ALU.v:15: Unsupported or unknown PLI call: $monitor\n$monitor("   %h:%h: %h :%h:%h:%h:  %b   :    %b     :    %b     :%b:%b:  %b",\n^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:24: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00011_00000_100000;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:30: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00011_00000_100000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:34: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_100000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:38: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_100000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:42: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_100000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:47: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b001000_00000_00001_1000000000100000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:52: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b001000_00000_00001_0000000000100010;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:56: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b001000_00000_00001_0000000000100000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:60: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b001000_00000_00001_1111111111111111;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:65: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_100001;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:70: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_100001;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:74: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_100001;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:78: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_100001;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:82: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_100001;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:86: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_100001;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:91: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b001001_00000_00001_1000000000100000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:96: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b001001_00000_00001_1000000000100000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:100: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b001001_00000_00001_0000000000000000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:105: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_100010;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:110: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_100010;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:114: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_100010;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:118: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_100010;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:123: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_100011;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:128: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_100011;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:132: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_100011;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:136: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_100011;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:140: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_100011;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:145: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_100100;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:150: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_100100;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:154: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_100100;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:158: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_100100;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:163: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b001100_00000_00001_1000000000100000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:168: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b001100_00000_00001_1000000000100000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:172: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b001100_00000_00001_1000000000100000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:177: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_100111;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:182: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_100111;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:186: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_100111;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:190: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_100111;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:195: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_11000_100101;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:200: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_11000_100101;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:204: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_11000_100101;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:209: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b001101_00000_00001_1000000000100000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:214: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b001101_00000_00001_1000000000100000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:218: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b001101_00000_00001_0000000000000000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:223: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_100110;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:228: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_100110;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:232: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_100110;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:236: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_100110;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:241: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b001110_00000_00001_1000000000100000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:246: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b001110_00000_00001_1000000000100000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:250: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b001110_00000_00001_1000000000100000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:255: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000101_00000_00001_1000000000100000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:260: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000100_00000_00001_1000000000100000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:264: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000100_00000_00001_1000000000100000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:269: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_101010;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:274: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_101010;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:278: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_101010;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:282: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_101010;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:287: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b001010_00000_00001_1000000000100000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:292: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b001010_00000_00001_1000000000100000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:296: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b001010_00000_00001_1000000000100000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:301: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_101011;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:306: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_101011;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:310: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_101011;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:314: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00000_101011;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:319: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b001011_00000_00001_0000000000100000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:324: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b001011_00000_00001_0000000000010000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:328: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b001011_00000_00001_1000000000100000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:332: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b001011_00000_00001_1000000000100000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:337: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b101011_00000_00001_1000000000100000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:342: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b101011_00000_00001_1000000000100000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:346: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b101011_00000_00001_1000000000100000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:351: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b100011_00000_00001_1000000000100000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:356: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b100011_00000_00001_1000000000100000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:360: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b100011_00000_00001_1000000000100000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:365: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00010_000000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:371: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_11000_000000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:376: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_11000_000100;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:381: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_11000_000100;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:386: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00010_000010;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:391: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_11000_000010;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:396: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_11000_000110;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:401: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_11000_000110;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:406: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_00010_000011;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:411: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_11000_000011;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:416: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_11000_000111;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:421: Unsupported: Ignoring delay on this delayed statement.\n#10 instruction<=32\'b000000_00000_00001_00001_11000_000111;\n^\n%Warning-STMTDLY: data/full_repos/permissive/475937410/Ass3/test_ALU.v:426: Unsupported: Ignoring delay on this delayed statement.\n#10 $finish;\n^\n%Error: Exiting due to 1 error(s), 88 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu_test;
reg[31:0] instruction,regA, regB;

wire[31:0] result;
wire[2:0] flags;

alu testalu(instruction,regA,regB, result, flags);

initial
begin

$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
$monitor("   %h:%h: %h :%h:%h:%h:  %b   :    %b     :    %b     :%b:%b:  %b",
instruction, testalu.opcode, testalu.func, regA ,regB, result, flags[2],flags[1],flags[0], testalu.rs_reg, testalu.rt_reg, testalu.reg_C);







#10 instruction<=32'b000000_00000_00001_00011_00000_100000;
regA<=32'b0000_0000_0000_0000_0000_0000_0000_0011;
regB<=32'b0000_0000_0000_0000_0000_0000_0000_1001;
$display("add");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");

#10 instruction<=32'b000000_00000_00001_00011_00000_100000;
regA<=32'b1000_0000_0000_0000_0000_0000_0000_0001;
regB<=32'b1000_0000_0000_0000_0000_0000_0000_0001;

#10 instruction<=32'b000000_00000_00001_00001_00000_100000;
regA<=32'b0100_0000_0000_0000_0000_0000_0000_0001;
regB<=32'b0100_0000_0000_0000_0000_0000_0000_0001;

#10 instruction<=32'b000000_00000_00001_00001_00000_100000;
regA<=32'b0000_0000_0000_0000_0000_0000_1101_1101;
regB<=32'b1111_1111_1111_1111_1111_1111_0010_0011;

#10 instruction<=32'b000000_00000_00001_00001_00000_100000;
regA<=32'b0000_0010_0010_0000_1000_1111_0101_1101;
regB<=32'b1111_1101_1101_1111_0111_0000_0010_0011;


#10 instruction<=32'b001000_00000_00001_1000000000100000;
regA<=32'b1000_0000_0000_0000_0101_1100_0000_0001;
regB<=32'b1000_0000_0000_0101_1100_0101_1100_0001;
$display("addi");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b001000_00000_00001_0000000000100010;
regA<=32'b1000_0000_0000_0000_0000_0000_0000_0001;
regB<=32'b1000_0000_0101_1100_0000_0000_0000_0001;

#10 instruction<=32'b001000_00000_00001_0000000000100000;
regA<=32'b1000_0000_0101_1100_0000_0000_0000_0001;
regB<=32'b1000_0000_0000_0000_0000_0000_0000_0001;

#10 instruction<=32'b001000_00000_00001_1111111111111111;
regA<=32'b0111_1111_1111_1111_0000_0000_0000_0001;
regB<=32'b1000_0000_0000_0000_0000_0000_0000_0001;


#10 instruction<=32'b000000_00000_00001_00001_00000_100001;
regA<=32'b0000_0000_0000_0000_0000_0000_0000_0001;
regB<=32'b0000_0000_0000_0101_1100_0000_0000_1001;
$display("addu");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b000000_00000_00001_00001_00000_100001;
regA<=32'b1000_0000_0101_1100_0000_0000_0000_0001;
regB<=32'b1000_0000_0000_0101_1100_0000_0000_0001;

#10 instruction<=32'b000000_00000_00001_00001_00000_100001;
regA<=32'b0100_0000_0101_1100_0000_0000_0000_0001;
regB<=32'b0100_0000_0000_0101_1100_0000_0000_0001;

#10 instruction<=32'b000000_00000_00001_00001_00000_100001;
regA<=32'b0000_0000_0000_0000_0000_0000_1101_1101;
regB<=32'b1111_0101_1100_1111_1111_1111_0010_0011;

#10 instruction<=32'b000000_00000_00001_00001_00000_100001;
regA<=32'b0000_0000_0000_0101_1100_0000_0101_1101;
regB<=32'b1111_1111_0101_1100_1111_1111_0010_0011;

#10 instruction<=32'b000000_00000_00001_00001_00000_100001;
regA<=32'b0000_0000_0000_0000_0000_0000_0000_0000;
regB<=32'b0000_0101_1100_0000_0000_0000_0000_0000;


#10 instruction<=32'b001001_00000_00001_1000000000100000;
regA<=32'b1000_0000_0000_0000_0000_0000_0000_0001;
regB<=32'b1000_0000_0000_0000_0000_0000_0000_0001;
$display("addiu");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b001001_00000_00001_1000000000100000;
regA<=32'b0000_0000_0000_0000_0000_0000_0000_0001;
regB<=32'b0000_0101_1100_0000_0000_0000_0000_0011;

#10 instruction<=32'b001001_00000_00001_0000000000000000;
regA<=32'b0000_0101_1100_0000_0000_0000_0000_0000;
regB<=32'b0000_0000_0000_0000_0000_0000_0000_0000;


#10 instruction<=32'b000000_00000_00001_00001_00000_100010;
regA<=32'b1111_0000_0000_0000_0000_0000_0101_1101;
regB<=32'b0000_0101_1100_0000_0000_0000_0000_0001;
$display("sub");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b000000_00000_00001_00001_00000_100010;
regA<=32'b1000_0000_0000_0000_0000_0000_0000_0001;
regB<=32'b0111_0000_0000_0000_0000_0000_0101_1101;

#10 instruction<=32'b000000_00000_00001_00001_00000_100010;
regA<=32'b0000_0000_0000_0000_0000_0000_0000_0001;
regB<=32'b1111_0000_0101_1100_0000_0101_1100_1101;

#10 instruction<=32'b000000_00000_00001_00001_00000_100010;
regA<=32'b0000_0000_0101_1100_0000_0000_0000_0000;
regB<=32'b0000_0000_0000_0000_0101_0101_1100_0000;


#10 instruction<=32'b000000_00000_00001_00001_00000_100011;
regA<=32'b0111_0101_1100_0000_0101_1100_0101_1101;
regB<=32'b1000_0000_0000_1111_0000_0000_0000_0001;
$display("subu");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b000000_00000_00001_00001_00000_100011;
regA<=32'b1000_0000_0000_1111_0000_0000_0000_0001;
regB<=32'b0111_0000_1111_0000_0000_0000_0101_1111;

#10 instruction<=32'b000000_00000_00001_00001_00000_100011;
regA<=32'b0000_0000_1111_0000_0000_0000_0000_0001;
regB<=32'b1111_0000_0000_0000_0000_0000_0101_0001;

#10 instruction<=32'b000000_00000_00001_00001_00000_100011;
regA<=32'b0000_0000_0000_0000_0000_1000_0000_1101;
regB<=32'b0000_0000_1111_0000_0000_0000_0101_1101;

#10 instruction<=32'b000000_00000_00001_00001_00000_100011;
regA<=32'b0000_0000_0000_0000_1111_0000_0000_0000;
regB<=32'b0000_1111_0000_1111_0000_0000_0000_0000;


#10 instruction<=32'b000000_00000_00001_00001_00000_100100;
regA<=32'b1000_0000_0000_0000_0000_0000_0000_0000;
regB<=32'b1111_1111_1111_1111_1111_1111_1111_1111;
$display("and");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b000000_00000_00001_00001_00000_100100;
regA<=32'b1000_0000_1001_0000_0000_0000_0000_0000;
regB<=32'b0000_0000_1001_0000_0000_0000_0011_0010;

#10 instruction<=32'b000000_00000_00001_00001_00000_100100;
regA<=32'b1000_1100_0010_0000_0000_0000_0000_0000;
regB<=32'b0100_0001_0000_0001_0110_0000_0011_1110;

#10 instruction<=32'b000000_00000_00001_00001_00000_100100;
regA<=32'b1000_0100_0100_1100_0000_0110_1100_0100;
regB<=32'b1111_1111_1100_0011_1101_1111_1111_1111;


#10 instruction<=32'b001100_00000_00001_1000000000100000;
regA<=32'b1000_0110_0000_0000_0000_0000_0000_0001;
regB<=32'b1000_0000_0110_0000_0000_0000_0000_0001;
$display("andi");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b001100_00000_00001_1000000000100000;
regA<=32'b1000_0000_0000_0110_0000_0000_0010_0000;
regB<=32'b1000_0000_0000_0000_0000_0000_0000_0001;

#10 instruction<=32'b001100_00000_00001_1000000000100000;
regA<=32'b0000_0000_0000_0000_0110_0000_0000_0001;
regB<=32'b0000_0000_0000_0000_0000_0000_0000_0011;


#10 instruction<=32'b000000_00000_00001_00001_00000_100111;
regA<=32'b1000_0000_0010_0000_0000_0000_0000_0000;
regB<=32'b1111_1111_1101_1111_1111_1111_1111_1111;
$display("nor");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b000000_00000_00001_00001_00000_100111;
regA<=32'b1000_0110_0000_0000_0000_0000_0000_0000;
regB<=32'b0000_0000_0000_1100_0000_0000_0011_0010;

#10 instruction<=32'b000000_00000_00001_00001_00000_100111;
regA<=32'b1000_0000_0000_0000_0000_0000_0000_0000;
regB<=32'b1111_1111_1111_1111_1111_1111_1111_1111;

#10 instruction<=32'b000000_00000_00001_00001_00000_100111;
regA<=32'b1000_1100_1110_0000_1100_0000_0000_0000;
regB<=32'b0000_0010_0000_0000_0000_0000_0011_0010;


#10 instruction<=32'b000000_00000_00001_00001_11000_100101;
regA<=32'b1111_1100_0010_1100_0010_0100_0100_0000;
regB<=32'b0000_0000_0000_1100_0100_0010_0001_0010;
$display("or");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b000000_00000_00001_00001_11000_100101;
regA<=32'b0100_0000_1111_1111_0000_0000_0010_0000;
regB<=32'b1111_1111_1111_1111_1111_1111_1111_1111;

#10 instruction<=32'b000000_00000_00001_00001_11000_100101;
regA<=32'b0000_0000_0010_0100_0000_0000_0010_0000;
regB<=32'b0000_0000_1000_0100_0000_0000_0010_0000;


#10 instruction<=32'b001101_00000_00001_1000000000100000;
regA<=32'b1000_0000_1000_0010_0000_0000_0000_0001;
regB<=32'b1100_0000_0000_0010_0000_0000_0000_0001;
$display("ori");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b001101_00000_00001_1000000000100000;
regA<=32'b1000_0000_0000_0100_0010_0001_0010_0000;
regB<=32'b1000_0000_0000_0100_0010_0001_1000_0001;

#10 instruction<=32'b001101_00000_00001_0000000000000000;
regA<=32'b0000_0000_0100_0000_0000_0000_0000_0000;
regB<=32'b0000_0000_1111_1111_0000_0000_0000_0011;


#10 instruction<=32'b000000_00000_00001_00001_00000_100110;
regA<=32'b1000_0000_0000_0000_0000_0000_0000_0000;
regB<=32'b1111_1111_1111_1111_1111_1111_1111_1111;
$display("xor");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b000000_00000_00001_00001_00000_100110;
regA<=32'b1000_0000_0000_0010_0000_0000_0000_0000;
regB<=32'b0000_0000_1111_1111_0000_0000_0011_0010;

#10 instruction<=32'b000000_00000_00001_00001_00000_100110;
regA<=32'b1000_1100_0010_0010_0000_0010_0000_0000;
regB<=32'b0000_1111_1111_1000_0000_0000_0011_0010;

#10 instruction<=32'b000000_00000_00001_00001_00000_100110;
regA<=32'b1000_0000_0000_0000_0000_0010_0000_0000;
regB<=32'b1111_1111_1000_1011_1111_1111_1111_1111;


#10 instruction<=32'b001110_00000_00001_1000000000100000;
regA<=32'b1000_0000_0000_0000_0000_1000_1011_0001;
regB<=32'b1000_0000_1000_1011_0000_0000_1000_1011;
$display("xori");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b001110_00000_00001_1000000000100000;
regA<=32'b1000_0000_0000_0100_0000_0000_0010_0000;
regB<=32'b1000_0000_0000_0100_0000_0010_0000_0001;

#10 instruction<=32'b001110_00000_00001_1000000000100000;
regA<=32'b0000_0000_0010_0000_0000_0111_0000_0001;
regB<=32'b0000_0000_1000_0000_0000_0010_0000_0011;


#10 instruction<=32'b000101_00000_00001_1000000000100000;
regA<=32'b1000_0000_0100_0000_0000_0000_0000_0001;
regB<=32'b1000_0000_0100_0000_0000_0000_0000_0001;
$display("beq/bne");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b000100_00000_00001_1000000000100000;
regA<=32'b1000_0000_0000_1000_0000_0000_0010_0000;
regB<=32'b1000_0000_0000_1000_0000_0000_0010_0000;

#10 instruction<=32'b000100_00000_00001_1000000000100000;
regA<=32'b0000_0000_0000_0010_0000_0000_0000_0001;
regB<=32'b0000_0000_0000_0010_0000_0000_0000_0001;


#10 instruction<=32'b000000_00000_00001_00001_00000_101010;
regA<=32'b1000_0000_0000_1000_1011_0000_0000_0000;
regB<=32'b1111_1000_1011_1111_1111_1111_1111_1111;
$display("slt");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b000000_00000_00001_00001_00000_101010;
regA<=32'b1000_0000_1000_1011_0000_0000_0000_0000;
regB<=32'b0000_0000_0000_0000_0000_0000_0000_0010;

#10 instruction<=32'b000000_00000_00001_00001_00000_101010;
regA<=32'b0100_1100_0010_0000_0000_0000_0000_0000;
regB<=32'b0000_0000_0000_1000_1011_0000_0000_0010;

#10 instruction<=32'b000000_00000_00001_00001_00000_101010;
regA<=32'b1010_0000_0100_0000_0000_0000_0000_0000;
regB<=32'b1111_1111_1111_1011_1100_1000_1011_1111;


#10 instruction<=32'b001010_00000_00001_1000000000100000;
regA<=32'b1010_0000_0000_0000_0000_0000_0000_0001;
regB<=32'b1000_0000_0100_0000_0000_0000_1100_0001;
$display("slti");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b001010_00000_00001_1000000000100000;
regA<=32'b1100_0000_1000_0000_0000_0000_0010_0000;
regB<=32'b1010_1000_0100_0000_0000_0110_0000_0001;

#10 instruction<=32'b001010_00000_00001_1000000000100000;
regA<=32'b0000_0000_1100_0100_0000_0000_0000_0001;
regB<=32'b0000_0110_0110_0010_0000_0110_0000_0011;


#10 instruction<=32'b000000_00000_00001_00001_00000_101011;
regA<=32'b1111_1111_1111_1111_1111_1111_1111_1111;
regB<=32'b1111_1111_1111_1111_1111_1111_1111_1111;
$display("sltu");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b000000_00000_00001_00001_00000_101011;
regA<=32'b1000_0000_0010_0000_0000_0000_1000_0000;
regB<=32'b0000_0000_0000_1111_1111_1111_1111_1111;

#10 instruction<=32'b000000_00000_00001_00001_00000_101011;
regA<=32'b1000_1100_0010_1100_0000_0000_0000_0000;
regB<=32'b0000_0110_1000_0000_0000_1100_0011_0010;

#10 instruction<=32'b000000_00000_00001_00001_00000_101011;
regA<=32'b1000_0000_1100_0000_0000_0000_0000_0000;
regB<=32'b1111_1111_1111_0011_1111_1111_1111_1111;


#10 instruction<=32'b001011_00000_00001_0000000000100000;
regA<=32'b0000_0000_0000_0000_0100_0000_0000_0000;
regB<=32'b0000_0000_0000_0000_0000_0000_1000_0001;
$display("stliu");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b001011_00000_00001_0000000000010000;
regA<=32'b0000_0100_0000_0000_0100_0000_0010_0000;
regB<=32'b0000_0000_0100_0000_0000_0100_0000_0001;

#10 instruction<=32'b001011_00000_00001_1000000000100000;
regA<=32'b1000_0110_0000_0000_0000_0000_0000_0000;
regB<=32'b1000_0000_0000_0110_0000_0000_0000_1001;

#10 instruction<=32'b001011_00000_00001_1000000000100000;
regA<=32'b0100_0010_0000_0100_0000_0000_0000_0000;
regB<=32'b1000_0000_0100_0100_0110_0000_0000_0011;


#10 instruction<=32'b101011_00000_00001_1000000000100000;
regA<=32'b1100_0100_0000_0000_1100_0000_0000_0001;
regB<=32'b1010_0110_0000_0000_0000_1100_0000_0001;
$display("sw");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b101011_00000_00001_1000000000100000;
regA<=32'b1000_0000_0000_1100_0000_0000_0010_0000;
regB<=32'b1000_0000_0100_0000_0000_1111_0000_0001;

#10 instruction<=32'b101011_00000_00001_1000000000100000;
regA<=32'b0000_0000_0100_0000_1110_0000_0110_0001;
regB<=32'b0000_0110_0000_1100_0000_0000_0000_0011;


#10 instruction<=32'b100011_00000_00001_1000000000100000;
regA<=32'b1000_0000_0100_0000_0010_1100_0011_0001;
regB<=32'b1000_0110_0000_1100_0010_1100_1100_1101;
$display("lw");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b100011_00000_00001_1000000000100000;
regA<=32'b1000_0000_0010_0000_0010_0000_0010_0000;
regB<=32'b1000_0110_0000_0000_0000_0100_0000_0001;

#10 instruction<=32'b100011_00000_00001_1000000000100000;
regA<=32'b0000_0010_0010_0100_0000_0100_0000_0001;
regB<=32'b0000_0110_0000_1100_0000_0001_0000_0011;


#10 instruction<=32'b000000_00000_00001_00001_00010_000000;
regA<=32'b1111_1100_0010_0000_0000_0001_0000_0000;
regB<=32'b0000_0000_0000_0100_1010_0010_0000_0010;
$display("sll");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");

#10 instruction<=32'b000000_00000_00001_00001_11000_000000;
regA<=32'b0000_0000_0000_0000_0000_0000_0000_0100;
regB<=32'b1111_0000_1111_0000_0000_1111_1111_1111;


#10 instruction<=32'b000000_00000_00001_00001_11000_000100;
regA<=32'b0000_0000_0000_0000_0000_0000_0000_0010;
regB<=32'b0000_0000_0000_0010_0100_0100_0010_0010;
$display("sllv");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b000000_00000_00001_00001_11000_000100;
regA<=32'b0000_0000_0000_0000_0000_0000_0000_0110;
regB<=32'b0000_0000_1000_0101_0100_0000_0001_0000;


#10 instruction<=32'b000000_00000_00001_00001_00010_000010;
regA<=32'b1111_1100_0010_0000_0000_0000_0000_0000;
regB<=32'b1000_0010_0110_0110_1010_0110_0000_0010;
$display("srl");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b000000_00000_00001_00001_11000_000010;
regA<=32'b0100_0000_0000_0000_0000_0000_0000_0000;
regB<=32'b1111_0000_0000_0000_0000_0000_0000_0000;


#10 instruction<=32'b000000_00000_00001_00001_11000_000110;
regA<=32'b0000_0000_0000_0000_0000_0000_0000_0010;
regB<=32'b1000_1010_0010_0100_1000_0100_0000_0010;
$display("srlv");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b000000_00000_00001_00001_11000_000110;
regA<=32'b1000_0000_0000_0000_0000_0000_0000_0010;
regB<=32'b0110_0010_0010_0000_0100_1101_0010_1000;


#10 instruction<=32'b000000_00000_00001_00001_00010_000011;
regA<=32'b1111_1100_0010_0000_0000_0000_0000_0000;
regB<=32'b1000_0000_0000_0100_0010_0100_0100_0010;
$display("sra");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b000000_00000_00001_00001_11000_000011;
regA<=32'b0100_0000_0010_0000_0000_0000_0000_0000;
regB<=32'b1111_1001_1001_1111_0011_1111_0011_0000;


#10 instruction<=32'b000000_00000_00001_00001_11000_000111;
regA<=32'b0000_0000_0000_0000_0000_0000_0000_0010;
regB<=32'b1000_0100_0100_1101_1100_0010_0010_0010;
$display("srav");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b000000_00000_00001_00001_11000_000111;
regA<=32'b0000_0000_0100_0010_0001_0000_0000_0110;
regB<=32'b0100_0100_1100_1100_0000_0000_0101_0000;


#10 $finish;
end
endmodule
module alu_test;

reg[31:0] instruction,regA, regB;

wire[31:0] result;
wire[2:0] flags;

alu testalu(instruction,regA,regB, result, flags);

initial
begin

$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
$monitor("   %h:%h: %h :%h:%h:%h:  %b   :    %b     :    %b     :%b:%b:  %b",
instruction, testalu.opcode, testalu.func, regA ,regB, result, flags[2],flags[1],flags[0], testalu.rs_reg, testalu.rt_reg, testalu.reg_C);







#10 instruction<=32'b000000_00000_00001_00011_00000_100000;
regA<=32'b0000_0000_0000_0000_0000_0000_0000_0011;
regB<=32'b0000_0000_0000_0000_0000_0000_0000_1001;
$display("add");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");

#10 instruction<=32'b000000_00000_00001_00011_00000_100000;
regA<=32'b1000_0000_0000_0000_0000_0000_0000_0001;
regB<=32'b1000_0000_0000_0000_0000_0000_0000_0001;

#10 instruction<=32'b000000_00000_00001_00001_00000_100000;
regA<=32'b0100_0000_0000_0000_0000_0000_0000_0001;
regB<=32'b0100_0000_0000_0000_0000_0000_0000_0001;

#10 instruction<=32'b000000_00000_00001_00001_00000_100000;
regA<=32'b0000_0000_0000_0000_0000_0000_1101_1101;
regB<=32'b1111_1111_1111_1111_1111_1111_0010_0011;

#10 instruction<=32'b000000_00000_00001_00001_00000_100000;
regA<=32'b0000_0010_0010_0000_1000_1111_0101_1101;
regB<=32'b1111_1101_1101_1111_0111_0000_0010_0011;


#10 instruction<=32'b001000_00000_00001_1000000000100000;
regA<=32'b1000_0000_0000_0000_0101_1100_0000_0001;
regB<=32'b1000_0000_0000_0101_1100_0101_1100_0001;
$display("addi");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b001000_00000_00001_0000000000100010;
regA<=32'b1000_0000_0000_0000_0000_0000_0000_0001;
regB<=32'b1000_0000_0101_1100_0000_0000_0000_0001;

#10 instruction<=32'b001000_00000_00001_0000000000100000;
regA<=32'b1000_0000_0101_1100_0000_0000_0000_0001;
regB<=32'b1000_0000_0000_0000_0000_0000_0000_0001;

#10 instruction<=32'b001000_00000_00001_1111111111111111;
regA<=32'b0111_1111_1111_1111_0000_0000_0000_0001;
regB<=32'b1000_0000_0000_0000_0000_0000_0000_0001;


#10 instruction<=32'b000000_00000_00001_00001_00000_100001;
regA<=32'b0000_0000_0000_0000_0000_0000_0000_0001;
regB<=32'b0000_0000_0000_0101_1100_0000_0000_1001;
$display("addu");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b000000_00000_00001_00001_00000_100001;
regA<=32'b1000_0000_0101_1100_0000_0000_0000_0001;
regB<=32'b1000_0000_0000_0101_1100_0000_0000_0001;

#10 instruction<=32'b000000_00000_00001_00001_00000_100001;
regA<=32'b0100_0000_0101_1100_0000_0000_0000_0001;
regB<=32'b0100_0000_0000_0101_1100_0000_0000_0001;

#10 instruction<=32'b000000_00000_00001_00001_00000_100001;
regA<=32'b0000_0000_0000_0000_0000_0000_1101_1101;
regB<=32'b1111_0101_1100_1111_1111_1111_0010_0011;

#10 instruction<=32'b000000_00000_00001_00001_00000_100001;
regA<=32'b0000_0000_0000_0101_1100_0000_0101_1101;
regB<=32'b1111_1111_0101_1100_1111_1111_0010_0011;

#10 instruction<=32'b000000_00000_00001_00001_00000_100001;
regA<=32'b0000_0000_0000_0000_0000_0000_0000_0000;
regB<=32'b0000_0101_1100_0000_0000_0000_0000_0000;


#10 instruction<=32'b001001_00000_00001_1000000000100000;
regA<=32'b1000_0000_0000_0000_0000_0000_0000_0001;
regB<=32'b1000_0000_0000_0000_0000_0000_0000_0001;
$display("addiu");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b001001_00000_00001_1000000000100000;
regA<=32'b0000_0000_0000_0000_0000_0000_0000_0001;
regB<=32'b0000_0101_1100_0000_0000_0000_0000_0011;

#10 instruction<=32'b001001_00000_00001_0000000000000000;
regA<=32'b0000_0101_1100_0000_0000_0000_0000_0000;
regB<=32'b0000_0000_0000_0000_0000_0000_0000_0000;


#10 instruction<=32'b000000_00000_00001_00001_00000_100010;
regA<=32'b1111_0000_0000_0000_0000_0000_0101_1101;
regB<=32'b0000_0101_1100_0000_0000_0000_0000_0001;
$display("sub");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b000000_00000_00001_00001_00000_100010;
regA<=32'b1000_0000_0000_0000_0000_0000_0000_0001;
regB<=32'b0111_0000_0000_0000_0000_0000_0101_1101;

#10 instruction<=32'b000000_00000_00001_00001_00000_100010;
regA<=32'b0000_0000_0000_0000_0000_0000_0000_0001;
regB<=32'b1111_0000_0101_1100_0000_0101_1100_1101;

#10 instruction<=32'b000000_00000_00001_00001_00000_100010;
regA<=32'b0000_0000_0101_1100_0000_0000_0000_0000;
regB<=32'b0000_0000_0000_0000_0101_0101_1100_0000;


#10 instruction<=32'b000000_00000_00001_00001_00000_100011;
regA<=32'b0111_0101_1100_0000_0101_1100_0101_1101;
regB<=32'b1000_0000_0000_1111_0000_0000_0000_0001;
$display("subu");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b000000_00000_00001_00001_00000_100011;
regA<=32'b1000_0000_0000_1111_0000_0000_0000_0001;
regB<=32'b0111_0000_1111_0000_0000_0000_0101_1111;

#10 instruction<=32'b000000_00000_00001_00001_00000_100011;
regA<=32'b0000_0000_1111_0000_0000_0000_0000_0001;
regB<=32'b1111_0000_0000_0000_0000_0000_0101_0001;

#10 instruction<=32'b000000_00000_00001_00001_00000_100011;
regA<=32'b0000_0000_0000_0000_0000_1000_0000_1101;
regB<=32'b0000_0000_1111_0000_0000_0000_0101_1101;

#10 instruction<=32'b000000_00000_00001_00001_00000_100011;
regA<=32'b0000_0000_0000_0000_1111_0000_0000_0000;
regB<=32'b0000_1111_0000_1111_0000_0000_0000_0000;


#10 instruction<=32'b000000_00000_00001_00001_00000_100100;
regA<=32'b1000_0000_0000_0000_0000_0000_0000_0000;
regB<=32'b1111_1111_1111_1111_1111_1111_1111_1111;
$display("and");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b000000_00000_00001_00001_00000_100100;
regA<=32'b1000_0000_1001_0000_0000_0000_0000_0000;
regB<=32'b0000_0000_1001_0000_0000_0000_0011_0010;

#10 instruction<=32'b000000_00000_00001_00001_00000_100100;
regA<=32'b1000_1100_0010_0000_0000_0000_0000_0000;
regB<=32'b0100_0001_0000_0001_0110_0000_0011_1110;

#10 instruction<=32'b000000_00000_00001_00001_00000_100100;
regA<=32'b1000_0100_0100_1100_0000_0110_1100_0100;
regB<=32'b1111_1111_1100_0011_1101_1111_1111_1111;


#10 instruction<=32'b001100_00000_00001_1000000000100000;
regA<=32'b1000_0110_0000_0000_0000_0000_0000_0001;
regB<=32'b1000_0000_0110_0000_0000_0000_0000_0001;
$display("andi");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b001100_00000_00001_1000000000100000;
regA<=32'b1000_0000_0000_0110_0000_0000_0010_0000;
regB<=32'b1000_0000_0000_0000_0000_0000_0000_0001;

#10 instruction<=32'b001100_00000_00001_1000000000100000;
regA<=32'b0000_0000_0000_0000_0110_0000_0000_0001;
regB<=32'b0000_0000_0000_0000_0000_0000_0000_0011;


#10 instruction<=32'b000000_00000_00001_00001_00000_100111;
regA<=32'b1000_0000_0010_0000_0000_0000_0000_0000;
regB<=32'b1111_1111_1101_1111_1111_1111_1111_1111;
$display("nor");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b000000_00000_00001_00001_00000_100111;
regA<=32'b1000_0110_0000_0000_0000_0000_0000_0000;
regB<=32'b0000_0000_0000_1100_0000_0000_0011_0010;

#10 instruction<=32'b000000_00000_00001_00001_00000_100111;
regA<=32'b1000_0000_0000_0000_0000_0000_0000_0000;
regB<=32'b1111_1111_1111_1111_1111_1111_1111_1111;

#10 instruction<=32'b000000_00000_00001_00001_00000_100111;
regA<=32'b1000_1100_1110_0000_1100_0000_0000_0000;
regB<=32'b0000_0010_0000_0000_0000_0000_0011_0010;


#10 instruction<=32'b000000_00000_00001_00001_11000_100101;
regA<=32'b1111_1100_0010_1100_0010_0100_0100_0000;
regB<=32'b0000_0000_0000_1100_0100_0010_0001_0010;
$display("or");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b000000_00000_00001_00001_11000_100101;
regA<=32'b0100_0000_1111_1111_0000_0000_0010_0000;
regB<=32'b1111_1111_1111_1111_1111_1111_1111_1111;

#10 instruction<=32'b000000_00000_00001_00001_11000_100101;
regA<=32'b0000_0000_0010_0100_0000_0000_0010_0000;
regB<=32'b0000_0000_1000_0100_0000_0000_0010_0000;


#10 instruction<=32'b001101_00000_00001_1000000000100000;
regA<=32'b1000_0000_1000_0010_0000_0000_0000_0001;
regB<=32'b1100_0000_0000_0010_0000_0000_0000_0001;
$display("ori");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b001101_00000_00001_1000000000100000;
regA<=32'b1000_0000_0000_0100_0010_0001_0010_0000;
regB<=32'b1000_0000_0000_0100_0010_0001_1000_0001;

#10 instruction<=32'b001101_00000_00001_0000000000000000;
regA<=32'b0000_0000_0100_0000_0000_0000_0000_0000;
regB<=32'b0000_0000_1111_1111_0000_0000_0000_0011;


#10 instruction<=32'b000000_00000_00001_00001_00000_100110;
regA<=32'b1000_0000_0000_0000_0000_0000_0000_0000;
regB<=32'b1111_1111_1111_1111_1111_1111_1111_1111;
$display("xor");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b000000_00000_00001_00001_00000_100110;
regA<=32'b1000_0000_0000_0010_0000_0000_0000_0000;
regB<=32'b0000_0000_1111_1111_0000_0000_0011_0010;

#10 instruction<=32'b000000_00000_00001_00001_00000_100110;
regA<=32'b1000_1100_0010_0010_0000_0010_0000_0000;
regB<=32'b0000_1111_1111_1000_0000_0000_0011_0010;

#10 instruction<=32'b000000_00000_00001_00001_00000_100110;
regA<=32'b1000_0000_0000_0000_0000_0010_0000_0000;
regB<=32'b1111_1111_1000_1011_1111_1111_1111_1111;


#10 instruction<=32'b001110_00000_00001_1000000000100000;
regA<=32'b1000_0000_0000_0000_0000_1000_1011_0001;
regB<=32'b1000_0000_1000_1011_0000_0000_1000_1011;
$display("xori");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b001110_00000_00001_1000000000100000;
regA<=32'b1000_0000_0000_0100_0000_0000_0010_0000;
regB<=32'b1000_0000_0000_0100_0000_0010_0000_0001;

#10 instruction<=32'b001110_00000_00001_1000000000100000;
regA<=32'b0000_0000_0010_0000_0000_0111_0000_0001;
regB<=32'b0000_0000_1000_0000_0000_0010_0000_0011;


#10 instruction<=32'b000101_00000_00001_1000000000100000;
regA<=32'b1000_0000_0100_0000_0000_0000_0000_0001;
regB<=32'b1000_0000_0100_0000_0000_0000_0000_0001;
$display("beq/bne");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b000100_00000_00001_1000000000100000;
regA<=32'b1000_0000_0000_1000_0000_0000_0010_0000;
regB<=32'b1000_0000_0000_1000_0000_0000_0010_0000;

#10 instruction<=32'b000100_00000_00001_1000000000100000;
regA<=32'b0000_0000_0000_0010_0000_0000_0000_0001;
regB<=32'b0000_0000_0000_0010_0000_0000_0000_0001;


#10 instruction<=32'b000000_00000_00001_00001_00000_101010;
regA<=32'b1000_0000_0000_1000_1011_0000_0000_0000;
regB<=32'b1111_1000_1011_1111_1111_1111_1111_1111;
$display("slt");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b000000_00000_00001_00001_00000_101010;
regA<=32'b1000_0000_1000_1011_0000_0000_0000_0000;
regB<=32'b0000_0000_0000_0000_0000_0000_0000_0010;

#10 instruction<=32'b000000_00000_00001_00001_00000_101010;
regA<=32'b0100_1100_0010_0000_0000_0000_0000_0000;
regB<=32'b0000_0000_0000_1000_1011_0000_0000_0010;

#10 instruction<=32'b000000_00000_00001_00001_00000_101010;
regA<=32'b1010_0000_0100_0000_0000_0000_0000_0000;
regB<=32'b1111_1111_1111_1011_1100_1000_1011_1111;


#10 instruction<=32'b001010_00000_00001_1000000000100000;
regA<=32'b1010_0000_0000_0000_0000_0000_0000_0001;
regB<=32'b1000_0000_0100_0000_0000_0000_1100_0001;
$display("slti");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b001010_00000_00001_1000000000100000;
regA<=32'b1100_0000_1000_0000_0000_0000_0010_0000;
regB<=32'b1010_1000_0100_0000_0000_0110_0000_0001;

#10 instruction<=32'b001010_00000_00001_1000000000100000;
regA<=32'b0000_0000_1100_0100_0000_0000_0000_0001;
regB<=32'b0000_0110_0110_0010_0000_0110_0000_0011;


#10 instruction<=32'b000000_00000_00001_00001_00000_101011;
regA<=32'b1111_1111_1111_1111_1111_1111_1111_1111;
regB<=32'b1111_1111_1111_1111_1111_1111_1111_1111;
$display("sltu");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b000000_00000_00001_00001_00000_101011;
regA<=32'b1000_0000_0010_0000_0000_0000_1000_0000;
regB<=32'b0000_0000_0000_1111_1111_1111_1111_1111;

#10 instruction<=32'b000000_00000_00001_00001_00000_101011;
regA<=32'b1000_1100_0010_1100_0000_0000_0000_0000;
regB<=32'b0000_0110_1000_0000_0000_1100_0011_0010;

#10 instruction<=32'b000000_00000_00001_00001_00000_101011;
regA<=32'b1000_0000_1100_0000_0000_0000_0000_0000;
regB<=32'b1111_1111_1111_0011_1111_1111_1111_1111;


#10 instruction<=32'b001011_00000_00001_0000000000100000;
regA<=32'b0000_0000_0000_0000_0100_0000_0000_0000;
regB<=32'b0000_0000_0000_0000_0000_0000_1000_0001;
$display("stliu");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b001011_00000_00001_0000000000010000;
regA<=32'b0000_0100_0000_0000_0100_0000_0010_0000;
regB<=32'b0000_0000_0100_0000_0000_0100_0000_0001;

#10 instruction<=32'b001011_00000_00001_1000000000100000;
regA<=32'b1000_0110_0000_0000_0000_0000_0000_0000;
regB<=32'b1000_0000_0000_0110_0000_0000_0000_1001;

#10 instruction<=32'b001011_00000_00001_1000000000100000;
regA<=32'b0100_0010_0000_0100_0000_0000_0000_0000;
regB<=32'b1000_0000_0100_0100_0110_0000_0000_0011;


#10 instruction<=32'b101011_00000_00001_1000000000100000;
regA<=32'b1100_0100_0000_0000_1100_0000_0000_0001;
regB<=32'b1010_0110_0000_0000_0000_1100_0000_0001;
$display("sw");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b101011_00000_00001_1000000000100000;
regA<=32'b1000_0000_0000_1100_0000_0000_0010_0000;
regB<=32'b1000_0000_0100_0000_0000_1111_0000_0001;

#10 instruction<=32'b101011_00000_00001_1000000000100000;
regA<=32'b0000_0000_0100_0000_1110_0000_0110_0001;
regB<=32'b0000_0110_0000_1100_0000_0000_0000_0011;


#10 instruction<=32'b100011_00000_00001_1000000000100000;
regA<=32'b1000_0000_0100_0000_0010_1100_0011_0001;
regB<=32'b1000_0110_0000_1100_0010_1100_1100_1101;
$display("lw");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b100011_00000_00001_1000000000100000;
regA<=32'b1000_0000_0010_0000_0010_0000_0010_0000;
regB<=32'b1000_0110_0000_0000_0000_0100_0000_0001;

#10 instruction<=32'b100011_00000_00001_1000000000100000;
regA<=32'b0000_0010_0010_0100_0000_0100_0000_0001;
regB<=32'b0000_0110_0000_1100_0000_0001_0000_0011;


#10 instruction<=32'b000000_00000_00001_00001_00010_000000;
regA<=32'b1111_1100_0010_0000_0000_0001_0000_0000;
regB<=32'b0000_0000_0000_0100_1010_0010_0000_0010;
$display("sll");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");

#10 instruction<=32'b000000_00000_00001_00001_11000_000000;
regA<=32'b0000_0000_0000_0000_0000_0000_0000_0100;
regB<=32'b1111_0000_1111_0000_0000_1111_1111_1111;


#10 instruction<=32'b000000_00000_00001_00001_11000_000100;
regA<=32'b0000_0000_0000_0000_0000_0000_0000_0010;
regB<=32'b0000_0000_0000_0010_0100_0100_0010_0010;
$display("sllv");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b000000_00000_00001_00001_11000_000100;
regA<=32'b0000_0000_0000_0000_0000_0000_0000_0110;
regB<=32'b0000_0000_1000_0101_0100_0000_0001_0000;


#10 instruction<=32'b000000_00000_00001_00001_00010_000010;
regA<=32'b1111_1100_0010_0000_0000_0000_0000_0000;
regB<=32'b1000_0010_0110_0110_1010_0110_0000_0010;
$display("srl");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b000000_00000_00001_00001_11000_000010;
regA<=32'b0100_0000_0000_0000_0000_0000_0000_0000;
regB<=32'b1111_0000_0000_0000_0000_0000_0000_0000;


#10 instruction<=32'b000000_00000_00001_00001_11000_000110;
regA<=32'b0000_0000_0000_0000_0000_0000_0000_0010;
regB<=32'b1000_1010_0010_0100_1000_0100_0000_0010;
$display("srlv");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b000000_00000_00001_00001_11000_000110;
regA<=32'b1000_0000_0000_0000_0000_0000_0000_0010;
regB<=32'b0110_0010_0010_0000_0100_1101_0010_1000;


#10 instruction<=32'b000000_00000_00001_00001_00010_000011;
regA<=32'b1111_1100_0010_0000_0000_0000_0000_0000;
regB<=32'b1000_0000_0000_0100_0010_0100_0100_0010;
$display("sra");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b000000_00000_00001_00001_11000_000011;
regA<=32'b0100_0000_0010_0000_0000_0000_0000_0000;
regB<=32'b1111_1001_1001_1111_0011_1111_0011_0000;


#10 instruction<=32'b000000_00000_00001_00001_11000_000111;
regA<=32'b0000_0000_0000_0000_0000_0000_0000_0010;
regB<=32'b1000_0100_0100_1101_1100_0010_0010_0010;
$display("srav");
$display("instruction:op:func:  regA  :  regB  : result : zero : negative : overflow :               rs               :               rt               :            result_buffer");
#10 instruction<=32'b000000_00000_00001_00001_11000_000111;
regA<=32'b0000_0000_0100_0010_0001_0000_0000_0110;
regB<=32'b0100_0100_1100_1100_0000_0000_0101_0000;


#10 $finish;
end
endmodule