data/full_repos/permissive/509335294/regdestmux.v
data/verilator_xmls/038bcdf9-b5fd-4263-866d-62bd8e266625.xml
module regdestmux(		input[2:0] rt,
													rd,
									input[1:0] sel,
									output reg[2:0] regdestmux_out
									);
					
always@(*)begin
	case(sel)
	2'b00 : regdestmux_out <= rt;
	2'b01 : regdestmux_out <= rd;	
	2'b10 : regdestmux_out <= 3'b111;
	endcase
end

endmodule
module regdestmux(		input[2:0] rt,
													rd,
									input[1:0] sel,
									output reg[2:0] regdestmux_out
									);

					
always@(*)begin
	case(sel)
	2'b00 : regdestmux_out <= rt;
	2'b01 : regdestmux_out <= rd;	
	2'b10 : regdestmux_out <= 3'b111;
	endcase
end

endmodule