data/full_repos/permissive/482132588/design/code/cu.v
data/verilator_xmls/844b5241-e682-411d-8bba-f307016b05e9.xml
module cu(
    input  wire clock,
    input  wire reset,
      
    input wire [6:0] OPC,
    input wire [2:0] func3,
    input wire [6:0] func7,


    input wire BrEQ,
    input wire BrLT,
    

    output reg PCSel,
    output reg RegWEn,
    output reg [1:0] BrUn,
    output reg BSel,
    output reg ASel,
    output reg MemRW,
    output reg [1:0]WBSel,
    output reg [3:0]ALUSel

); 








always @( * ) begin

    BrUn[0] = func3[1];
    ALUSel[3] = (func7 == 0)? 0 : 1;

    case(OPC)

        7'b0110011: begin


            PCSel = 0;
            RegWEn = 1;
            BSel = 0;
            ASel = 0;
            MemRW = 0;
            WBSel = 2'b01;

            ALUSel[2:0] = func3;
            BrUn[1] = 0;

       
  
        end 

        7'b0010011: begin

            PCSel = 0;
            RegWEn = 1;
            BSel = 1;
            ASel = 0;
            MemRW = 0;
            WBSel = 2'b01;

            ALUSel[2:0] = func3;
            BrUn[1] = 0;



            
        end 
        7'b1100111: begin

            PCSel = 1;
            RegWEn = 1;
            BSel = 1;
            ASel = 0;
            MemRW = 0;
            WBSel = 2'b10;

            ALUSel[2:0] = 3'b000;
            BrUn[1] = 0;

            
        end 


        7'b0100011: begin


            PCSel = 0;
            RegWEn = 0;
            BSel = 1;
            ASel = 0;
            MemRW = 1;
            WBSel = 2'b01;

            ALUSel[2:0] = 3'b000;
            BrUn[1] = 0;

            
        end


        7'b1100011: begin




            PCSel = 0;
            RegWEn = 0;
            BSel = 1;
            ASel = 1;
            MemRW = 0;
            WBSel = 2'b01;

            ALUSel[2:0] = 3'b000;
            BrUn[1] = 1'b1;


            
        end 


        7'b0110111: begin

            PCSel = 0;
            RegWEn = 1;
            BSel = 1;
            ASel = 0;
            MemRW = 0;
            WBSel = 2'b01;

            ALUSel[2:0] = 3'b000;
            BrUn[1] = 0;
            
        end 

        7'b0010111: begin

            PCSel = 0;
            RegWEn = 1;
            BSel = 1;
            ASel = 1;
            MemRW = 0;
            WBSel = 2'b01;

            ALUSel[2:0] = 3'b000;
            BrUn[1] = 0;

            
        end 
        


        7'b1101111: begin

            PCSel = 0;
            RegWEn = 1;
            BSel = 1;
            ASel = 1;
            MemRW = 0;
            WBSel = 2'b10;

            ALUSel[2:0] = 3'b000;
            BrUn[1] = 0;

            
        end 


        7'b0000011: begin 

            PCSel = 0;
            RegWEn = 1;
            BSel = 1;
            ASel = 0;
            MemRW = 0;
            WBSel = 2'b00;

            ALUSel[2:0] = 3'b000;
            BrUn[1] = 0;

        end


        7'b1110011: begin

            PCSel = 0;
            RegWEn = 0;
            BSel = 0;
            ASel = 0;
            MemRW = 0;
            WBSel = 2'b01;

            ALUSel[2:0] = 3'b000;
            BrUn[1] = 0;


            
        end 

        default: begin


            PCSel = 0;
            RegWEn = 0;
            BSel = 0;
            ASel = 0;
            MemRW = 0;
            WBSel = 2'b01;

            ALUSel[2:0] = 3'b000;
            BrUn[1] = 0;

            
        end

    endcase
    

end









endmodule
module cu(
    input  wire clock,
    input  wire reset,
      
    input wire [6:0] OPC,
    input wire [2:0] func3,
    input wire [6:0] func7,


    input wire BrEQ,
    input wire BrLT,
    

    output reg PCSel,
    output reg RegWEn,
    output reg [1:0] BrUn,
    output reg BSel,
    output reg ASel,
    output reg MemRW,
    output reg [1:0]WBSel,
    output reg [3:0]ALUSel

);
 








always @( * ) begin

    BrUn[0] = func3[1];
    ALUSel[3] = (func7 == 0)? 0 : 1;

    case(OPC)

        7'b0110011: begin


            PCSel = 0;
            RegWEn = 1;
            BSel = 0;
            ASel = 0;
            MemRW = 0;
            WBSel = 2'b01;

            ALUSel[2:0] = func3;
            BrUn[1] = 0;

       
  
        end 

        7'b0010011: begin

            PCSel = 0;
            RegWEn = 1;
            BSel = 1;
            ASel = 0;
            MemRW = 0;
            WBSel = 2'b01;

            ALUSel[2:0] = func3;
            BrUn[1] = 0;



            
        end 
        7'b1100111: begin

            PCSel = 1;
            RegWEn = 1;
            BSel = 1;
            ASel = 0;
            MemRW = 0;
            WBSel = 2'b10;

            ALUSel[2:0] = 3'b000;
            BrUn[1] = 0;

            
        end 


        7'b0100011: begin


            PCSel = 0;
            RegWEn = 0;
            BSel = 1;
            ASel = 0;
            MemRW = 1;
            WBSel = 2'b01;

            ALUSel[2:0] = 3'b000;
            BrUn[1] = 0;

            
        end


        7'b1100011: begin




            PCSel = 0;
            RegWEn = 0;
            BSel = 1;
            ASel = 1;
            MemRW = 0;
            WBSel = 2'b01;

            ALUSel[2:0] = 3'b000;
            BrUn[1] = 1'b1;


            
        end 


        7'b0110111: begin

            PCSel = 0;
            RegWEn = 1;
            BSel = 1;
            ASel = 0;
            MemRW = 0;
            WBSel = 2'b01;

            ALUSel[2:0] = 3'b000;
            BrUn[1] = 0;
            
        end 

        7'b0010111: begin

            PCSel = 0;
            RegWEn = 1;
            BSel = 1;
            ASel = 1;
            MemRW = 0;
            WBSel = 2'b01;

            ALUSel[2:0] = 3'b000;
            BrUn[1] = 0;

            
        end 
        


        7'b1101111: begin

            PCSel = 0;
            RegWEn = 1;
            BSel = 1;
            ASel = 1;
            MemRW = 0;
            WBSel = 2'b10;

            ALUSel[2:0] = 3'b000;
            BrUn[1] = 0;

            
        end 


        7'b0000011: begin 

            PCSel = 0;
            RegWEn = 1;
            BSel = 1;
            ASel = 0;
            MemRW = 0;
            WBSel = 2'b00;

            ALUSel[2:0] = 3'b000;
            BrUn[1] = 0;

        end


        7'b1110011: begin

            PCSel = 0;
            RegWEn = 0;
            BSel = 0;
            ASel = 0;
            MemRW = 0;
            WBSel = 2'b01;

            ALUSel[2:0] = 3'b000;
            BrUn[1] = 0;


            
        end 

        default: begin


            PCSel = 0;
            RegWEn = 0;
            BSel = 0;
            ASel = 0;
            MemRW = 0;
            WBSel = 2'b01;

            ALUSel[2:0] = 3'b000;
            BrUn[1] = 0;

            
        end

    endcase
    

end









endmodule