data/full_repos/permissive/522534105/RTL_files/Test_Top_design.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/522534105/RTL_files/Test_Top_design.v:57: Unsupported: Ignoring delay on this delayed statement.\n       always #5 i_clk = ~i_clk ; \n              ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/522534105/RTL_files/Test_Top_design.v:62: Unsupported: Ignoring delay on this delayed statement.\n            #3 i_rst_n = 1\'b1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/522534105/RTL_files/Test_Top_design.v:63: Unsupported: Ignoring delay on this delayed statement.\n            #2 start = 1\'b1 ;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/522534105/RTL_files/Test_Top_design.v:65: Unsupported: Ignoring delay on this delayed statement.\n            #100 $stop ;\n            ^\n%Error: data/full_repos/permissive/522534105/RTL_files/Test_Top_design.v:72: syntax error, unexpected \'@\'\n           @(posedge i_clk)\n           ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Test_Top_design();
reg i_clk ;
reg start ;
reg i_rst_n ;
reg [4:0] op_1 ;
reg [3:0] op_2 ;
wire [4:0] o_Q_out , o_ACC_out ;
reg [7:0] o_result=0  ;
wire C_o ;



 Top_design DUT(
i_clk , 
start , 
i_rst_n , 
op_1 , 
op_2 , 
o_Q_out , 
o_ACC_out ,
o_assert_done  
,C_o );
   
 initial
   begin
    i_clk = 1'b0; 
     i_rst_n = 1'b0;
      start = 1'b0; 
      op_1 = 5'b11000;
      op_2 = 4'b1011;
    
        end
        
        
       always #5 i_clk = ~i_clk ; 
        
        
        initial
           begin
            #3 i_rst_n = 1'b1;
            #2 start = 1'b1 ;

            #100 $stop ;
            end 
      integer i ;      
    initial
       begin
         for (i = 0; i<40; i= i+1)
           begin
           @(posedge i_clk)
          #5 o_result = { o_ACC_out[3:0] , o_Q_out[4:1]} ;
         end 
       end 
endmodule
module Test_Top_design();

reg i_clk ;
reg start ;
reg i_rst_n ;
reg [4:0] op_1 ;
reg [3:0] op_2 ;
wire [4:0] o_Q_out , o_ACC_out ;
reg [7:0] o_result=0  ;
wire C_o ;



 Top_design DUT(
i_clk , 
start , 
i_rst_n , 
op_1 , 
op_2 , 
o_Q_out , 
o_ACC_out ,
o_assert_done  
,C_o );
   
 initial
   begin
    i_clk = 1'b0; 
     i_rst_n = 1'b0;
      start = 1'b0; 
      op_1 = 5'b11000;
      op_2 = 4'b1011;
    
        end
        
        
       always #5 i_clk = ~i_clk ; 
        
        
        initial
           begin
            #3 i_rst_n = 1'b1;
            #2 start = 1'b1 ;

            #100 $stop ;
            end 
      integer i ;      
    initial
       begin
         for (i = 0; i<40; i= i+1)
           begin
           @(posedge i_clk)
          #5 o_result = { o_ACC_out[3:0] , o_Q_out[4:1]} ;
         end 
       end 
endmodule