data/full_repos/permissive/521337848/Hardware/procesor/coprocesor.v
data/verilator_xmls/d0425821-0650-4ec0-ad61-76caf8fccdfc.xml
module coprocesor(
	input clk,
	input rst,
	

	
	input[1:0] devaddrin,
	input[1:0] devaddrout,

	input[31:0] in,
	output reg[31:0] out,
	

	
	input mrdy,
	input[23:0] mout,
	
	output reg[23:0] min,
	output reg mstart,
	
	
	output reg irq
	
);

reg[31:0] n_out;
reg n_irq;

always@(posedge clk or posedge rst)begin
	if(rst)begin
		out <= 0;
	end
	else begin
		out <= n_out;
	end
end

always@(posedge clk)begin
	irq <= n_irq;
end

always@(*)begin
	min = 0;
	n_out = out;
	mstart = 0;
	n_irq = 0;
	
	if(in[31:30] == devaddrin) begin
	
		if(in[29:24] ==6'b111111)begin

			n_out = 0;
		end else
		begin

			mstart = 1;
			min = in[23:0];
		end
		
		
	end 
	
	if(mrdy) begin

		n_out = {1'b1 , devaddrout, 5'b0,mout};
		n_irq = 1;
	end
	
end

endmodule
module coprocesor(
	input clk,
	input rst,
	

	
	input[1:0] devaddrin,
	input[1:0] devaddrout,

	input[31:0] in,
	output reg[31:0] out,
	

	
	input mrdy,
	input[23:0] mout,
	
	output reg[23:0] min,
	output reg mstart,
	
	
	output reg irq
	
);


reg[31:0] n_out;
reg n_irq;

always@(posedge clk or posedge rst)begin
	if(rst)begin
		out <= 0;
	end
	else begin
		out <= n_out;
	end
end

always@(posedge clk)begin
	irq <= n_irq;
end

always@(*)begin
	min = 0;
	n_out = out;
	mstart = 0;
	n_irq = 0;
	
	if(in[31:30] == devaddrin) begin
	
		if(in[29:24] ==6'b111111)begin

			n_out = 0;
		end else
		begin

			mstart = 1;
			min = in[23:0];
		end
		
		
	end 
	
	if(mrdy) begin

		n_out = {1'b1 , devaddrout, 5'b0,mout};
		n_irq = 1;
	end
	
end

endmodule