data/full_repos/permissive/469195529/sources/hdl/clk_div.v
data/verilator_xmls/30352c39-d17b-45d2-9946-c2a4e2c79f58.xml
module clk_div(
    input clk_in,
    output reg clk_out
    );
    
integer counter;
parameter HALF_PERIOD = 100;
always@(posedge clk_in)
    if(counter < HALF_PERIOD - 1) counter = counter + 1;
    else begin
    clk_out = ~clk_out;
    counter = 0;
    end
endmodule
module clk_div(
    input clk_in,
    output reg clk_out
    );

    
integer counter;
parameter HALF_PERIOD = 100;
always@(posedge clk_in)
    if(counter < HALF_PERIOD - 1) counter = counter + 1;
    else begin
    clk_out = ~clk_out;
    counter = 0;
    end
endmodule