data/full_repos/permissive/427281804/FPU/verilog/icgc.v
data/verilator_xmls/3a3721b6-e39e-49a0-9d1c-99055011dc50.xml
module icgc (

	input		CK,
	input 		E,
	output		ECK
);

reg   clkg_en;
always @* if(CK) clkg_en = E;
assign ECK = CK & clkg_en;

endmodule
module icgc (

	input		CK,
	input 		E,
	output		ECK
);


reg   clkg_en;
always @* if(CK) clkg_en = E;
assign ECK = CK & clkg_en;

endmodule