data/full_repos/permissive/515557004/traffic_tb.v
1: b'%Error: data/full_repos/permissive/515557004/traffic_tb.v:26: Unterminated string\n%Error: data/full_repos/permissive/515557004/traffic_tb.v:27: Unterminated string\n%Warning-STMTDLY: data/full_repos/permissive/515557004/traffic_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk=~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/515557004/traffic_tb.v:25: Unsupported or unknown PLI call: $monitor\n    $monitor($time,    MG=%d,SR=%d, SY=%d, SG=%d\n    ^~~~~~~~\n%Error: data/full_repos/permissive/515557004/traffic_tb.v:25: syntax error, unexpected \'=\', expecting \')\' or \',\'\n    $monitor($time,    MG=%d,SR=%d, SY=%d, SG=%d\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/515557004/traffic_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #13 SideVehicles =0; ped=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515557004/traffic_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #18 SideVehicles =1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515557004/traffic_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #33 ped=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515557004/traffic_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #13 em=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515557004/traffic_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #14 em=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515557004/traffic_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #3 rst =1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515557004/traffic_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #12 rst =0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515557004/traffic_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #103 es=1;#13 es=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515557004/traffic_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #103 es=1;#13 es=0;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/515557004/traffic_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #1000 $finish;\n    ^\n%Error: Exiting due to 4 error(s), 11 warning(s)\n'
module traffic_tb(
    );
    reg rst;
    reg clk;
    reg SideVehicles;
    reg ped;
    reg em;
    reg es;
    wire MR,MY,MG,SR,SY,SG;
 
    trafficSignalController tl(rst,SideVehicles,clk,ped,em,es,MG,MY,MR,SG,SY,SR);
    initial rst = 0;
    initial clk =0;
    initial SideVehicles = 0;
    initial ped=0;
    initial em=0;
    initial es=0;

    always #5 clk=~clk;

    initial
    begin
    $monitor($time,"rst = %b, em=%b, es=%b, ped=%b, sideVehicles = %b, MR=%d, MY=%d, 
    MG=%d,SR=%d, SY=%d, SG=%d",rst,em,es,ped,SideVehicles,MR,MY,MG,SR,SY,SG);

    #3 SideVehicles = 1;
    #13 SideVehicles =0; ped=1;
    #18 SideVehicles =1;
    #33 ped=0;
    #13 em=1;
    #14 em=0;
    #3 rst =1;
    #12 rst =0;
    #103 es=1;#13 es=0;
    #1000 $finish;
    end 
    
endmodule
module traffic_tb(
    );

    reg rst;
    reg clk;
    reg SideVehicles;
    reg ped;
    reg em;
    reg es;
    wire MR,MY,MG,SR,SY,SG;
 
    trafficSignalController tl(rst,SideVehicles,clk,ped,em,es,MG,MY,MR,SG,SY,SR);
    initial rst = 0;
    initial clk =0;
    initial SideVehicles = 0;
    initial ped=0;
    initial em=0;
    initial es=0;

    always #5 clk=~clk;

    initial
    begin
    $monitor($time,"rst = %b, em=%b, es=%b, ped=%b, sideVehicles = %b, MR=%d, MY=%d, 
    MG=%d,SR=%d, SY=%d, SG=%d",rst,em,es,ped,SideVehicles,MR,MY,MG,SR,SY,SG);

    #3 SideVehicles = 1;
    #13 SideVehicles =0; ped=1;
    #18 SideVehicles =1;
    #33 ped=0;
    #13 em=1;
    #14 em=0;
    #3 rst =1;
    #12 rst =0;
    #103 es=1;#13 es=0;
    #1000 $finish;
    end 
    
endmodule