data/full_repos/permissive/493851698/verilog/dv/my_alu_xor_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/493851698/verilog/dv/my_alu_xor_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/493851698/verilog/dv/my_alu_xor_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/493851698/verilog/dv/my_alu_xor_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/493851698/verilog/dv/my_alu_xor_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/493851698/verilog/dv/my_alu_xor_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/493851698/verilog/dv/my_alu_xor_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/493851698/verilog/dv/my_alu_xor_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/493851698/verilog/dv/my_alu_xor_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/493851698/verilog/dv/my_alu_xor_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/493851698/verilog/dv/my_alu_xor_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/493851698/verilog/dv/my_alu_xor_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/493851698/verilog/dv/my_alu_xor_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/493851698/verilog/dv/my_alu_xor_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/493851698/verilog/dv/my_alu_xor_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/493851698/verilog/dv/my_alu_xor_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/493851698/verilog/dv/my_alu_xor_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/493851698/verilog/dv/my_alu_xor_tb.v:124: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/493851698/verilog/dv/my_alu_xor_tb.v:129: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/493851698/verilog/dv/my_alu_xor_tb.v:138: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/493851698/verilog/dv/my_alu_xor_tb.v:143: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/493851698/verilog/dv/my_alu_xor_tb.v:148: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/493851698/verilog/dv/my_alu_xor_tb.v:157: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/493851698/verilog/dv/my_alu_xor_tb.v:162: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/493851698/verilog/dv/my_alu_xor_tb.v:167: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Error: data/full_repos/permissive/493851698/verilog/dv/my_alu_xor_tb.v:12: Cannot find file containing module: \'my_alu_xor\'\nmy_alu_xor UUT (.clk(clk), .A0(A0), .B0(B0), .A1(A1), .B1(B1), .ALU_Sel1(ALU_Sel1), .ALU_Sel2(ALU_Sel2), .ALU_Out1(ALU_Out1), .ALU_Out2(ALU_Out2), .CarryOut1(CarryOut1), .CarryOut2(CarryOut2), .x(x), .y(y));\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/493851698/verilog/dv,data/full_repos/permissive/493851698/my_alu_xor\n             data/full_repos/permissive/493851698/verilog/dv,data/full_repos/permissive/493851698/my_alu_xor.v\n             data/full_repos/permissive/493851698/verilog/dv,data/full_repos/permissive/493851698/my_alu_xor.sv\n             my_alu_xor\n             my_alu_xor.v\n             my_alu_xor.sv\n             obj_dir/my_alu_xor\n             obj_dir/my_alu_xor.v\n             obj_dir/my_alu_xor.sv\n%Error: Exiting due to 1 error(s), 24 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module my_alu_xor_tb;
		   reg clk;
           reg [7:0] A0,B0,A1,B1;
           reg [1:0] ALU_Sel1,ALU_Sel2;
           wire [7:0] ALU_Out1,ALU_Out2;
           wire CarryOut1,CarryOut2;
		   wire [7:0] x;
		   wire y;

integer i;

my_alu_xor UUT (.clk(clk), .A0(A0), .B0(B0), .A1(A1), .B1(B1), .ALU_Sel1(ALU_Sel1), .ALU_Sel2(ALU_Sel2), .ALU_Out1(ALU_Out1), .ALU_Out2(ALU_Out2), .CarryOut1(CarryOut1), .CarryOut2(CarryOut2), .x(x), .y(y));



initial
begin

clk = 1'b1;
ALU_Sel1 = 2'b00;
ALU_Sel2 = 2'b00;
A0=8'b00000000;
B0=8'b00000000;
A1=8'b00000000;
B1=8'b00000000;
#10;
if(ALU_Out1 != ALU_Out2)
$display("Add - ALU1 != ALU2");
else
$display("Add - ALU1 = ALU2");
#10;
if(CarryOut1 != CarryOut2)
$display("Add - Carry1 != Carry2");
else
$display("Add - Carry1 = Carry2");
#10;

ALU_Sel1 =  2'b01;
ALU_Sel2 =  2'b01;
A0=8'b10000000;
B0=8'b00000000;
A1=8'b00000000;
B1=8'b00000000;
#10;
if(ALU_Out1 != ALU_Out2)
$display("Sub - ALU1 != ALU2");
else
$display("Sub - ALU1 = ALU2");
#10;
if(CarryOut1 != CarryOut2)
$display("Sub - Carry1 != Carry2");
else
$display("Sub - Carry1 = Carry2");
#10;

ALU_Sel1 =  2'b10;
ALU_Sel2 =  2'b10;
A0=8'b00000000;
B0=8'b00000000;
A1=8'b00000000;
B1=8'b00000000;
#10;
if(ALU_Out1 != ALU_Out2)
$display("And - ALU1 != ALU2");
else
$display("And - ALU1 = ALU2");
#10;
if(CarryOut1 != CarryOut2)
$display("And - Carry1 != Carry2");
else
$display("And - Carry1 = Carry2");
#10;

ALU_Sel1 =  2'b11;
ALU_Sel2 =  2'b11;
A0=8'b00000000;
B0=8'b00000000;
A1=8'b00000000;
B1=8'b00000000;
#10;
if(ALU_Out1 != ALU_Out2)
$display("Or - ALU1 != ALU2");
else
$display("Or - ALU1 = ALU2");
#10;
if(CarryOut1 != CarryOut2)
$display("Or - Carry1 != Carry2");
else
$display("Or - Carry1 = Carry2");
#10;



ALU_Sel1 = 2'b00;
ALU_Sel2 = 2'b00;
A0=8'b10000001;
B0=8'b10000001;
A1=8'b00000000;
B1=8'b00000000;
#10;
if(ALU_Out1 != ALU_Out2)
$display("Add - ALU1 != ALU2");
else
$display("Add - ALU1 = ALU2");
#10;
if(CarryOut1 != CarryOut2)
$display("Add - Carry1 != Carry2");
else
$display("Add - Carry1 = Carry2");
#10;


ALU_Sel1 = 2'b01;
ALU_Sel2 = 2'b01;
A0=8'b10000001;
B0=8'b10000001;
A1=8'b00000000;
B1=8'b00000000;
#10;
if(ALU_Out1 != ALU_Out2)
$display("Sub - ALU1 != ALU2");
else
$display("Sub - ALU1 = ALU2");
#10;
if(CarryOut1 != CarryOut2)
$display("Sub - Carry1 != Carry2");
else
$display("Sub - Carry1 = Carry2");
#10;


ALU_Sel1 = 2'b10;
ALU_Sel2 = 2'b10;
A0=8'b10000001;
B0=8'b10000001;
A1=8'b00000000;
B1=8'b00000000;
#10;
if(ALU_Out1 != ALU_Out2)
$display("And - ALU1 != ALU2");
else
$display("And - ALU1 = ALU2");
#10;
if(CarryOut1 != CarryOut2)
$display("And - Carry1 != Carry2");
else
$display("And - Carry1 = Carry2");
#10;
 
 
ALU_Sel1 = 2'b11;
ALU_Sel2 = 2'b11;
A0=8'b10000001;
B0=8'b10000001;
A1=8'b00000000;
B1=8'b00000000;
#10;
if(ALU_Out1 != ALU_Out2)
$display("Or - ALU1 != ALU2");
else
$display("Or - ALU1 = ALU2");
#10;
if(CarryOut1 != CarryOut2)
$display("Or - Carry1 != Carry2");
else
$display("Or - Carry1 = Carry2");
#10;
end
endmodule
module my_alu_xor_tb;

		   reg clk;
           reg [7:0] A0,B0,A1,B1;
           reg [1:0] ALU_Sel1,ALU_Sel2;
           wire [7:0] ALU_Out1,ALU_Out2;
           wire CarryOut1,CarryOut2;
		   wire [7:0] x;
		   wire y;

integer i;

my_alu_xor UUT (.clk(clk), .A0(A0), .B0(B0), .A1(A1), .B1(B1), .ALU_Sel1(ALU_Sel1), .ALU_Sel2(ALU_Sel2), .ALU_Out1(ALU_Out1), .ALU_Out2(ALU_Out2), .CarryOut1(CarryOut1), .CarryOut2(CarryOut2), .x(x), .y(y));



initial
begin

clk = 1'b1;
ALU_Sel1 = 2'b00;
ALU_Sel2 = 2'b00;
A0=8'b00000000;
B0=8'b00000000;
A1=8'b00000000;
B1=8'b00000000;
#10;
if(ALU_Out1 != ALU_Out2)
$display("Add - ALU1 != ALU2");
else
$display("Add - ALU1 = ALU2");
#10;
if(CarryOut1 != CarryOut2)
$display("Add - Carry1 != Carry2");
else
$display("Add - Carry1 = Carry2");
#10;

ALU_Sel1 =  2'b01;
ALU_Sel2 =  2'b01;
A0=8'b10000000;
B0=8'b00000000;
A1=8'b00000000;
B1=8'b00000000;
#10;
if(ALU_Out1 != ALU_Out2)
$display("Sub - ALU1 != ALU2");
else
$display("Sub - ALU1 = ALU2");
#10;
if(CarryOut1 != CarryOut2)
$display("Sub - Carry1 != Carry2");
else
$display("Sub - Carry1 = Carry2");
#10;

ALU_Sel1 =  2'b10;
ALU_Sel2 =  2'b10;
A0=8'b00000000;
B0=8'b00000000;
A1=8'b00000000;
B1=8'b00000000;
#10;
if(ALU_Out1 != ALU_Out2)
$display("And - ALU1 != ALU2");
else
$display("And - ALU1 = ALU2");
#10;
if(CarryOut1 != CarryOut2)
$display("And - Carry1 != Carry2");
else
$display("And - Carry1 = Carry2");
#10;

ALU_Sel1 =  2'b11;
ALU_Sel2 =  2'b11;
A0=8'b00000000;
B0=8'b00000000;
A1=8'b00000000;
B1=8'b00000000;
#10;
if(ALU_Out1 != ALU_Out2)
$display("Or - ALU1 != ALU2");
else
$display("Or - ALU1 = ALU2");
#10;
if(CarryOut1 != CarryOut2)
$display("Or - Carry1 != Carry2");
else
$display("Or - Carry1 = Carry2");
#10;



ALU_Sel1 = 2'b00;
ALU_Sel2 = 2'b00;
A0=8'b10000001;
B0=8'b10000001;
A1=8'b00000000;
B1=8'b00000000;
#10;
if(ALU_Out1 != ALU_Out2)
$display("Add - ALU1 != ALU2");
else
$display("Add - ALU1 = ALU2");
#10;
if(CarryOut1 != CarryOut2)
$display("Add - Carry1 != Carry2");
else
$display("Add - Carry1 = Carry2");
#10;


ALU_Sel1 = 2'b01;
ALU_Sel2 = 2'b01;
A0=8'b10000001;
B0=8'b10000001;
A1=8'b00000000;
B1=8'b00000000;
#10;
if(ALU_Out1 != ALU_Out2)
$display("Sub - ALU1 != ALU2");
else
$display("Sub - ALU1 = ALU2");
#10;
if(CarryOut1 != CarryOut2)
$display("Sub - Carry1 != Carry2");
else
$display("Sub - Carry1 = Carry2");
#10;


ALU_Sel1 = 2'b10;
ALU_Sel2 = 2'b10;
A0=8'b10000001;
B0=8'b10000001;
A1=8'b00000000;
B1=8'b00000000;
#10;
if(ALU_Out1 != ALU_Out2)
$display("And - ALU1 != ALU2");
else
$display("And - ALU1 = ALU2");
#10;
if(CarryOut1 != CarryOut2)
$display("And - Carry1 != Carry2");
else
$display("And - Carry1 = Carry2");
#10;
 
 
ALU_Sel1 = 2'b11;
ALU_Sel2 = 2'b11;
A0=8'b10000001;
B0=8'b10000001;
A1=8'b00000000;
B1=8'b00000000;
#10;
if(ALU_Out1 != ALU_Out2)
$display("Or - ALU1 != ALU2");
else
$display("Or - ALU1 = ALU2");
#10;
if(CarryOut1 != CarryOut2)
$display("Or - Carry1 != Carry2");
else
$display("Or - Carry1 = Carry2");
#10;
end
endmodule