data/full_repos/permissive/523043017/Verilog microcontroller/control_unit.v
1: b'%Error: Cannot find file containing module: microcontroller,data/full_repos/permissive/523043017\n        ... Looked in:\n             data/full_repos/permissive/523043017/Verilog/microcontroller,data/full_repos/permissive/523043017\n             data/full_repos/permissive/523043017/Verilog/microcontroller,data/full_repos/permissive/523043017.v\n             data/full_repos/permissive/523043017/Verilog/microcontroller,data/full_repos/permissive/523043017.sv\n             microcontroller,data/full_repos/permissive/523043017\n             microcontroller,data/full_repos/permissive/523043017.v\n             microcontroller,data/full_repos/permissive/523043017.sv\n             obj_dir/microcontroller,data/full_repos/permissive/523043017\n             obj_dir/microcontroller,data/full_repos/permissive/523043017.v\n             obj_dir/microcontroller,data/full_repos/permissive/523043017.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/523043017/Verilog\n%Error: Cannot find file containing module: microcontroller/control_unit.v\n%Error: Exiting due to 3 error(s)\n'
module control_unit(
	input wire clock,
	input wire [3:0] command,
	input wire [7:0] data,
	input wire [3:0] FR,
	input wire [7:0] PC_in,
	output reg [7:0] PC_out,
	output reg [3:0] FR_rev,
	output reg RAM_w, PC_w
);
	reg [7:0] int_adr;
	reg [3:0] st_adress;
	reg [7:0] stack[3:0];
	reg IE;
	initial begin
		st_adress = 4'h0;
		IE = 0;
	end
	always @(negedge clock) begin
		RAM_w <= 1'h0;
		PC_w <= 1'h0;
		FR_rev <= 4'h0;
	end
	always @(posedge clock) begin
		if (FR[2]) begin
			if (IE) begin
				stack[st_adress] <= PC_in;
				st_adress <= st_adress + 1;
				PC_out <= data;
				PC_w <= 1;
			end
		end
		else case (command)

				4'h7: RAM_w <= 1;

				4'h8: begin
					PC_out <= data;
					PC_w <= 1;
				end

				4'h9: if (FR[1]) begin
						PC_out <= data;
						PC_w <= 1;
					end

				4'hA: if (FR[0]) begin
						PC_out <= data;
						PC_w <= 1;
					end

				4'hC: begin
					IE <= 1;
					st_adress <= data;
				end

				4'hD: FR_rev <= (4'h1 << data);

				4'hE: begin
					stack[st_adress] <= PC_in;
					st_adress <= st_adress + 1;
					PC_out <= data;
					PC_w <= 1;
				end

				4'hF: begin
					st_adress <= st_adress - 1;
					PC_out <= stack[st_adress];
					PC_w <= 1;
				end
			endcase
	end
endmodule
module control_unit(
	input wire clock,
	input wire [3:0] command,
	input wire [7:0] data,
	input wire [3:0] FR,
	input wire [7:0] PC_in,
	output reg [7:0] PC_out,
	output reg [3:0] FR_rev,
	output reg RAM_w, PC_w
);

	reg [7:0] int_adr;
	reg [3:0] st_adress;
	reg [7:0] stack[3:0];
	reg IE;
	initial begin
		st_adress = 4'h0;
		IE = 0;
	end
	always @(negedge clock) begin
		RAM_w <= 1'h0;
		PC_w <= 1'h0;
		FR_rev <= 4'h0;
	end
	always @(posedge clock) begin
		if (FR[2]) begin
			if (IE) begin
				stack[st_adress] <= PC_in;
				st_adress <= st_adress + 1;
				PC_out <= data;
				PC_w <= 1;
			end
		end
		else case (command)

				4'h7: RAM_w <= 1;

				4'h8: begin
					PC_out <= data;
					PC_w <= 1;
				end

				4'h9: if (FR[1]) begin
						PC_out <= data;
						PC_w <= 1;
					end

				4'hA: if (FR[0]) begin
						PC_out <= data;
						PC_w <= 1;
					end

				4'hC: begin
					IE <= 1;
					st_adress <= data;
				end

				4'hD: FR_rev <= (4'h1 << data);

				4'hE: begin
					stack[st_adress] <= PC_in;
					st_adress <= st_adress + 1;
					PC_out <= data;
					PC_w <= 1;
				end

				4'hF: begin
					st_adress <= st_adress - 1;
					PC_out <= stack[st_adress];
					PC_w <= 1;
				end
			endcase
	end
endmodule