data/full_repos/permissive/447283927/Data_Memory.v
1: b'%Warning-WIDTH: data/full_repos/permissive/447283927/Data_Memory.v:19: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'buttons_in\' generates 16 bits.\n                                                                     : ... In instance Data_Memory\n            Data_Out <= buttons_in;\n                     ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Data_Memory(output reg [31:0] Data_Out, input [31:0] Data_In, input [7:0] D_Addr, input wr, input clk
    ,output [31:0] seg_out, output [31:0] seg_en, input [15:0] buttons_in);
    reg [31:0] Mem [255:0];
    always @(negedge clk)
    begin
        if (wr)
        begin
           if (D_Addr != 2)
           begin
             Mem[D_Addr] <= Data_In;
           end
        end
    end
    always @(*)
    begin
        if (D_Addr == 2)
        begin
            Data_Out <= buttons_in;
        end
        else begin
            Data_Out <= Mem[D_Addr];
        end
    end
    assign seg_out = Mem[0];
    assign seg_en = Mem[1];
endmodule
module Data_Memory(output reg [31:0] Data_Out, input [31:0] Data_In, input [7:0] D_Addr, input wr, input clk
    ,output [31:0] seg_out, output [31:0] seg_en, input [15:0] buttons_in);

    reg [31:0] Mem [255:0];
    always @(negedge clk)
    begin
        if (wr)
        begin
           if (D_Addr != 2)
           begin
             Mem[D_Addr] <= Data_In;
           end
        end
    end
    always @(*)
    begin
        if (D_Addr == 2)
        begin
            Data_Out <= buttons_in;
        end
        else begin
            Data_Out <= Mem[D_Addr];
        end
    end
    assign seg_out = Mem[0];
    assign seg_en = Mem[1];
endmodule