data/full_repos/permissive/482470447/verilog/adder16_4.v
1: b"%Error: data/full_repos/permissive/482470447/verilog/adder16_4.v:5: Cannot find file containing module: 'blockSize4'\n blockSize4 b0(a[3:0],b[3:0],1'b0,sum[3:0],c1);\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/482470447/verilog,data/full_repos/permissive/482470447/blockSize4\n             data/full_repos/permissive/482470447/verilog,data/full_repos/permissive/482470447/blockSize4.v\n             data/full_repos/permissive/482470447/verilog,data/full_repos/permissive/482470447/blockSize4.sv\n             blockSize4\n             blockSize4.v\n             blockSize4.sv\n             obj_dir/blockSize4\n             obj_dir/blockSize4.v\n             obj_dir/blockSize4.sv\n%Error: data/full_repos/permissive/482470447/verilog/adder16_4.v:6: Cannot find file containing module: 'blockSize4'\n blockSize4 b1(a[7:4],b[7:4],c1,sum[7:4],c2);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/482470447/verilog/adder16_4.v:7: Cannot find file containing module: 'blockSize4'\n blockSize4 b2(a[11:8],b[11:8],c2,sum[11:8],c3);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/482470447/verilog/adder16_4.v:8: Cannot find file containing module: 'blockSize4'\n blockSize4 b3(a[15:12],b[15:12],c3,sum[15:12],c4);\n ^~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module adder16_4(a,b,sum);
	input[15:0] a,b;
	output[16:0]sum;
	wire c1,c2,c3,c4;
	blockSize4 b0(a[3:0],b[3:0],1'b0,sum[3:0],c1);
	blockSize4 b1(a[7:4],b[7:4],c1,sum[7:4],c2);
	blockSize4 b2(a[11:8],b[11:8],c2,sum[11:8],c3);
	blockSize4 b3(a[15:12],b[15:12],c3,sum[15:12],c4);
	assign sum[16] = c4;
endmodule
module adder16_4(a,b,sum);

	input[15:0] a,b;
	output[16:0]sum;
	wire c1,c2,c3,c4;
	blockSize4 b0(a[3:0],b[3:0],1'b0,sum[3:0],c1);
	blockSize4 b1(a[7:4],b[7:4],c1,sum[7:4],c2);
	blockSize4 b2(a[11:8],b[11:8],c2,sum[11:8],c3);
	blockSize4 b3(a[15:12],b[15:12],c3,sum[15:12],c4);
	assign sum[16] = c4;
endmodule