data/full_repos/permissive/460468583/data/yosys/gatemate/lut_map.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/460468583/data/yosys/gatemate/lut_map.v:25: Little bit endian vector: MSB < LSB of bit range: -1:0\n input [WIDTH-1:0] A;\n       ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module \$lut (A, Y);
	parameter WIDTH = 0;
	parameter LUT = 0;

	(* force_downto *)
	input [WIDTH-1:0] A;
	output Y;

	generate
		if (WIDTH == 1) begin
			CC_LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]));
		end
		else if (WIDTH == 2) begin
			CC_LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]));
		end
		else if (WIDTH == 3) begin
			CC_LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]));
		end
		else if (WIDTH == 4) begin
			CC_LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
		end
		else begin
			wire _TECHMAP_FAIL_ = 1;
		end
	endgenerate
endmodule
module \$lut (A, Y);

	parameter WIDTH = 0;
	parameter LUT = 0;

	(* force_downto *)
	input [WIDTH-1:0] A;
	output Y;

	generate
		if (WIDTH == 1) begin
			CC_LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]));
		end
		else if (WIDTH == 2) begin
			CC_LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]));
		end
		else if (WIDTH == 3) begin
			CC_LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]));
		end
		else if (WIDTH == 4) begin
			CC_LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
		end
		else begin
			wire _TECHMAP_FAIL_ = 1;
		end
	endgenerate
endmodule