data/full_repos/permissive/421450529/XALU.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/421450529/XALU.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #0; \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module XALU(
     input clk,
	  input reset,
	  input[31:0] Instr,
     input[31:0] D1,
	  input[31:0] D2,
	  input Start,
	  output reg[31:0] HI,
	  output reg[31:0] LO,
	  output reg Busy
    );
    initial begin
	    HI=32'b0;
		 LO=32'b0;
		 Busy=0;
	 end








	  
	  integer state=0;
		reg[31:0] hi=0;     
		reg[31:0] lo=0;
		reg[31:0] instr;
	 
	 always@(posedge clk)begin
	 #0;
	   if(reset)begin
		   HI=32'b0;
		   LO=32'b0;
		   Busy=0;
			state=0;
			hi=0;
			lo=0;
			instr=0;
		end
		else begin
	    case(state)
		   0:begin
			    if(Start)begin
				   case(Instr[5:0])
					  6'b011000:begin
					     instr=Instr;
					     {hi,lo}=$signed(D1)*$signed(D2);
						  Busy=1;
						  state=1;
					  end
					  6'b011001:begin
					     instr=Instr;
					     {hi,lo}=D1*D2;
						  Busy=1;
						  state=1;
					  end
					  6'b011010:begin
					      instr=Instr;
					      hi=$signed(D1)%$signed(D2);
							lo=$signed(D1)/$signed(D2);
							Busy=1;
							state=1;
					  end
					  6'b011011:begin
					      instr=Instr;
					      hi=D1%D2;
							lo=D1/D2;
							Busy=1;
							state=1;
					  end
					  6'b010000:begin
					      HI=hi;
							Busy=0;
							state=0;
					  end
					  6'b010010:begin
					      LO=lo;
							Busy=0;
							state=0;
					  end
					  6'b010001:begin
					      hi=D1;
							Busy=0;
							state=0;
					  end
					  6'b010011:begin
					      lo=D1;
							Busy=0;
							state=0;
					  end
					endcase
				 end
				 else begin
				   state=0;
					Busy=0;
					instr=0;
				 end
			  end
			1,2,3,4:begin
			     state=state+1;
				  Busy=1;
			  end
			5:begin
			     if(instr[5:0]==6'b011000||instr[5:0]==6'b011001)begin
				     HI=hi;
					  LO=lo;
					  state=0;
					  Busy=0;
					  instr=0;
				  end
				  else begin
				     state=state+1;
					  Busy=1;
				  end
			  end
			6,7,8,9:begin
			     state=state+1;
				  Busy=1;
			  end
			10:begin
			    if(instr[5:0]==6'b011010||instr[5:0]==6'b011011)begin
				     HI=hi;
					  LO=lo;
					  state=0;
					  Busy=0;
					  instr=0;
				  end
				  else begin
				     state=0;
					  Busy=0;
					  instr=0;
				  end
			  end
		endcase
	  end
	 end

endmodule
module XALU(
     input clk,
	  input reset,
	  input[31:0] Instr,
     input[31:0] D1,
	  input[31:0] D2,
	  input Start,
	  output reg[31:0] HI,
	  output reg[31:0] LO,
	  output reg Busy
    );

    initial begin
	    HI=32'b0;
		 LO=32'b0;
		 Busy=0;
	 end








	  
	  integer state=0;
		reg[31:0] hi=0;     
		reg[31:0] lo=0;
		reg[31:0] instr;
	 
	 always@(posedge clk)begin
	 #0;
	   if(reset)begin
		   HI=32'b0;
		   LO=32'b0;
		   Busy=0;
			state=0;
			hi=0;
			lo=0;
			instr=0;
		end
		else begin
	    case(state)
		   0:begin
			    if(Start)begin
				   case(Instr[5:0])
					  6'b011000:begin
					     instr=Instr;
					     {hi,lo}=$signed(D1)*$signed(D2);
						  Busy=1;
						  state=1;
					  end
					  6'b011001:begin
					     instr=Instr;
					     {hi,lo}=D1*D2;
						  Busy=1;
						  state=1;
					  end
					  6'b011010:begin
					      instr=Instr;
					      hi=$signed(D1)%$signed(D2);
							lo=$signed(D1)/$signed(D2);
							Busy=1;
							state=1;
					  end
					  6'b011011:begin
					      instr=Instr;
					      hi=D1%D2;
							lo=D1/D2;
							Busy=1;
							state=1;
					  end
					  6'b010000:begin
					      HI=hi;
							Busy=0;
							state=0;
					  end
					  6'b010010:begin
					      LO=lo;
							Busy=0;
							state=0;
					  end
					  6'b010001:begin
					      hi=D1;
							Busy=0;
							state=0;
					  end
					  6'b010011:begin
					      lo=D1;
							Busy=0;
							state=0;
					  end
					endcase
				 end
				 else begin
				   state=0;
					Busy=0;
					instr=0;
				 end
			  end
			1,2,3,4:begin
			     state=state+1;
				  Busy=1;
			  end
			5:begin
			     if(instr[5:0]==6'b011000||instr[5:0]==6'b011001)begin
				     HI=hi;
					  LO=lo;
					  state=0;
					  Busy=0;
					  instr=0;
				  end
				  else begin
				     state=state+1;
					  Busy=1;
				  end
			  end
			6,7,8,9:begin
			     state=state+1;
				  Busy=1;
			  end
			10:begin
			    if(instr[5:0]==6'b011010||instr[5:0]==6'b011011)begin
				     HI=hi;
					  LO=lo;
					  state=0;
					  Busy=0;
					  instr=0;
				  end
				  else begin
				     state=0;
					  Busy=0;
					  instr=0;
				  end
			  end
		endcase
	  end
	 end

endmodule