data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_incr46.v
data/verilator_xmls/de7040a3-beb5-416c-86aa-3e2727df5af7.xml
module sparc_ifu_incr46(a, a_inc, ofl);
   input  [45:0]  a;
   output [45:0]  a_inc;
   output 	  ofl;
   
   reg [45:0] 	  a_inc;
   reg 		  ofl;
   
   always @ (a)
     begin
	      a_inc = a + (46'b1);
	      ofl = (~a[45]) & a_inc[45];
     end
   
   
   
endmodule
module sparc_ifu_incr46(a, a_inc, ofl);

   input  [45:0]  a;
   output [45:0]  a_inc;
   output 	  ofl;
   
   reg [45:0] 	  a_inc;
   reg 		  ofl;
   
   always @ (a)
     begin
	      a_inc = a + (46'b1);
	      ofl = (~a[45]) & a_inc[45];
     end
   
   
   
endmodule