data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/alu.v
1: b'%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/alu.v:4: Cannot find include file: instruction_defs.vh\n`include "instruction_defs.vh" \n         ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new,data/full_repos/permissive/464120924/instruction_defs.vh\n             data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new,data/full_repos/permissive/464120924/instruction_defs.vh.v\n             data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new,data/full_repos/permissive/464120924/instruction_defs.vh.sv\n             instruction_defs.vh\n             instruction_defs.vh.v\n             instruction_defs.vh.sv\n             obj_dir/instruction_defs.vh\n             obj_dir/instruction_defs.vh.v\n             obj_dir/instruction_defs.vh.sv\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/alu.v:42: Define or directive not defined: \'`ADD\'\n            `ADD: res1 <= a + b;\n            ^~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/alu.v:42: syntax error, unexpected \':\', expecting endcase\n            `ADD: res1 <= a + b;\n                ^\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/alu.v:43: Define or directive not defined: \'`SUB\'\n            `SUB: res1 <= a - b;\n            ^~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/alu.v:45: Define or directive not defined: \'`AND\'\n            `AND: res1 <= a & b;\n            ^~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/alu.v:46: Define or directive not defined: \'`OR\'\n            `OR:  res1 <= a | b;\n            ^~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/alu.v:47: Define or directive not defined: \'`XOR\'\n            `XOR: res1 <= a ^ b;\n            ^~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/alu.v:49: Define or directive not defined: \'`NOT\'\n            `NOT: res1 <= ~a;\n            ^~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/alu.v:51: Define or directive not defined: \'`SHL\'\n            `SHL: res1 <= a << shift_amount;\n            ^~~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/alu.v:52: Define or directive not defined: \'`SHR\'\n            `SHR: res1 <= a >> shift_amount;\n            ^~~~\n%Error: Cannot continue\n'
module alu#(parameter bits=15)(input clk, 
                            input enabled,
                            input multiplier_enabled,
                            input divider_enabled,
                            input[7:0] instr, 
                            input[bits:0] a, 
                            input[bits:0] b, 
                            output[bits:0] out1, 
                            output[bits:0] out2, 
                            output done);
                            
                        
    reg[bits:0] res1 = 0;

    wire[31:0] multiplier_result;
    wire[15:0] divider_result, divider_remainder;
    wire multiplier_done, divider_done;
    
    
    multiplier#(bits) mult1(clk, multiplier_enabled & enabled, a, b, multiplier_result, multiplier_done);
    divider#(bits) div1(clk, divider_enabled & enabled, a, b, divider_result, divider_remainder, divider_done);

    assign out1 = multiplier_enabled ? multiplier_result[15:0] : 
                    divider_enabled ? divider_result : res1;
                    
    assign out2 = multiplier_enabled ? multiplier_result[31:16] : divider_remainder;
    assign done = multiplier_done & divider_done;


    wire[3:0] shift_amount = b[3:0];

    always@(posedge clk) begin
        
        if (enabled) case (instr)
        
            `ADD: res1 <= a + b;
            `SUB: res1 <= a - b;
        
            `AND: res1 <= a & b;
            `OR:  res1 <= a | b;
            `XOR: res1 <= a ^ b;
            
            `NOT: res1 <= ~a;
                  
            `SHL: res1 <= a << shift_amount;
            `SHR: res1 <= a >> shift_amount;

        endcase
    
    end

endmodule
module alu#(parameter bits=15)(input clk, 
                            input enabled,
                            input multiplier_enabled,
                            input divider_enabled,
                            input[7:0] instr, 
                            input[bits:0] a, 
                            input[bits:0] b, 
                            output[bits:0] out1, 
                            output[bits:0] out2, 
                            output done);

                            
                        
    reg[bits:0] res1 = 0;

    wire[31:0] multiplier_result;
    wire[15:0] divider_result, divider_remainder;
    wire multiplier_done, divider_done;
    
    
    multiplier#(bits) mult1(clk, multiplier_enabled & enabled, a, b, multiplier_result, multiplier_done);
    divider#(bits) div1(clk, divider_enabled & enabled, a, b, divider_result, divider_remainder, divider_done);

    assign out1 = multiplier_enabled ? multiplier_result[15:0] : 
                    divider_enabled ? divider_result : res1;
                    
    assign out2 = multiplier_enabled ? multiplier_result[31:16] : divider_remainder;
    assign done = multiplier_done & divider_done;


    wire[3:0] shift_amount = b[3:0];

    always@(posedge clk) begin
        
        if (enabled) case (instr)
        
            `ADD: res1 <= a + b;
            `SUB: res1 <= a - b;
        
            `AND: res1 <= a & b;
            `OR:  res1 <= a | b;
            `XOR: res1 <= a ^ b;
            
            `NOT: res1 <= ~a;
                  
            `SHL: res1 <= a << shift_amount;
            `SHR: res1 <= a >> shift_amount;

        endcase
    
    end

endmodule