data/full_repos/permissive/506081587/quartus/src/vgaHdmi.v
1: b"%Error: data/full_repos/permissive/506081587/quartus/src/vgaHdmi.v:140: Cannot find file containing module: 'lane'\nlane lane(\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/506081587/quartus/src,data/full_repos/permissive/506081587/lane\n             data/full_repos/permissive/506081587/quartus/src,data/full_repos/permissive/506081587/lane.v\n             data/full_repos/permissive/506081587/quartus/src,data/full_repos/permissive/506081587/lane.sv\n             lane\n             lane.v\n             lane.sv\n             obj_dir/lane\n             obj_dir/lane.v\n             obj_dir/lane.sv\n%Error: Exiting due to 1 error(s)\n"
module vgaHdmi(

  input clock, clock50, reset,
  input switchSobel,
  input button0,


  output reg hsync, vsync,
  output reg dataEnable,
  output reg vgaClock,
  output [23:0] RGBchannel
);

reg [9:0]pixelH, pixelV;
reg [23:0]RGBchannel_reg;
reg [1:0] resContador;
reg [23:0]RGBchannel_reg_sobel;


initial begin
  hsync      = 1;
  vsync      = 1;
  pixelH     = 0;
  pixelV     = 0;
  dataEnable = 0;
  vgaClock   = 0;
  resContador= 0;
  
end



always @(posedge clock or posedge reset) begin
  if(reset) begin
    hsync  <= 1;
    vsync  <= 1;
    pixelH <= 0;
    pixelV <= 0;
  end
  else begin

    if(pixelH==0 && pixelV!=524) begin
      pixelH<=pixelH+1'b1;
      pixelV<=pixelV+1'b1;
    end
    else if(pixelH==0 && pixelV==524) begin
      pixelH <= pixelH + 1'b1;
      pixelV <= 0;
    end
    else if(pixelH<=640) pixelH <= pixelH + 1'b1;

    else if(pixelH<=656) pixelH <= pixelH + 1'b1;

    else if(pixelH<=752) begin
      pixelH <= pixelH + 1'b1;
      hsync  <= 0;
    end

    else if(pixelH<799) begin
      pixelH <= pixelH+1'b1;
      hsync  <= 1;
    end
    else pixelH<=0;



    if(pixelV == 491 || pixelV == 492)
      vsync <= 0;
    else
      vsync <= 1;
  end
end


always @(posedge clock or posedge reset) begin
  if(reset) dataEnable<= 0;

  else begin
    if(pixelH >= 0 && pixelH <640 && pixelV >= 0 && pixelV < 480)
      dataEnable <= 1;
    else
      dataEnable <= 0;
  end
end



initial vgaClock = 0;

always @(posedge clock50 or posedge reset) begin
  if(reset) vgaClock <= 0;
  else      vgaClock <= ~vgaClock;
end






always @(posedge clock50 or negedge button0) begin
  if (!button0) begin
    resContador <= resContador+1'b1;
  end else begin
    if(resContador == 0)begin
      if(pixelH <320 && pixelV<240) begin
        RGBchannel_reg <= 24'b111111110000000000000000;
      end else if (pixelH >=320 && pixelV<240) begin
        RGBchannel_reg <= 24'b000000001111111100000000;
      end else if (pixelH <320 && pixelV>=240) begin
        RGBchannel_reg <= 24'b000000000000000011111111;
      end else begin
        RGBchannel_reg <= 24'b111111110000000011111111;
      end
    end else begin
      if (pixelH <200 && pixelV<240) begin
        RGBchannel_reg <=24'b111111111111111100000000;
      end else if (pixelH <420 && pixelV<240) begin
        RGBchannel_reg <=24'b000000001111111111111111;
      end else if(pixelH >=420 && pixelV<240) begin
        RGBchannel_reg <=24'b111111111111111111111111;
      end else if (pixelH <200 && pixelV>=240) begin
        RGBchannel_reg <=24'b000000001111111100000000;
      end else if (pixelH <400 && pixelV>=240) begin
        RGBchannel_reg <=24'b000000000000000000000000;
      end else begin
        RGBchannel_reg <=24'b111111110000000011111111;
      end



    end
  end

end





lane lane(
  .clk(clock50), 
  .reset_n(!reset),
  .enable_in(3'b111),
  
  .vs_in(vsync),
  .hs_in(hsync),
  .de_in(dataEnable),
  .r_in(RGBchannel_reg[23:16]),
  .g_in(RGBchannel_reg[15:8]),
  .b_in(RGBchannel_reg[7:0]),




  .r_out(RGBchannel_reg_sobel[23:16]),
  .g_out(RGBchannel_reg_sobel[15:8]),
  .b_out(RGBchannel_reg_sobel[7:0]),
  


);



assign RGBchannel = (switchSobel)? RGBchannel_reg_sobel : RGBchannel_reg;










endmodule
module vgaHdmi(

  input clock, clock50, reset,
  input switchSobel,
  input button0,


  output reg hsync, vsync,
  output reg dataEnable,
  output reg vgaClock,
  output [23:0] RGBchannel
);


reg [9:0]pixelH, pixelV;
reg [23:0]RGBchannel_reg;
reg [1:0] resContador;
reg [23:0]RGBchannel_reg_sobel;


initial begin
  hsync      = 1;
  vsync      = 1;
  pixelH     = 0;
  pixelV     = 0;
  dataEnable = 0;
  vgaClock   = 0;
  resContador= 0;
  
end



always @(posedge clock or posedge reset) begin
  if(reset) begin
    hsync  <= 1;
    vsync  <= 1;
    pixelH <= 0;
    pixelV <= 0;
  end
  else begin

    if(pixelH==0 && pixelV!=524) begin
      pixelH<=pixelH+1'b1;
      pixelV<=pixelV+1'b1;
    end
    else if(pixelH==0 && pixelV==524) begin
      pixelH <= pixelH + 1'b1;
      pixelV <= 0;
    end
    else if(pixelH<=640) pixelH <= pixelH + 1'b1;

    else if(pixelH<=656) pixelH <= pixelH + 1'b1;

    else if(pixelH<=752) begin
      pixelH <= pixelH + 1'b1;
      hsync  <= 0;
    end

    else if(pixelH<799) begin
      pixelH <= pixelH+1'b1;
      hsync  <= 1;
    end
    else pixelH<=0;



    if(pixelV == 491 || pixelV == 492)
      vsync <= 0;
    else
      vsync <= 1;
  end
end


always @(posedge clock or posedge reset) begin
  if(reset) dataEnable<= 0;

  else begin
    if(pixelH >= 0 && pixelH <640 && pixelV >= 0 && pixelV < 480)
      dataEnable <= 1;
    else
      dataEnable <= 0;
  end
end



initial vgaClock = 0;

always @(posedge clock50 or posedge reset) begin
  if(reset) vgaClock <= 0;
  else      vgaClock <= ~vgaClock;
end






always @(posedge clock50 or negedge button0) begin
  if (!button0) begin
    resContador <= resContador+1'b1;
  end else begin
    if(resContador == 0)begin
      if(pixelH <320 && pixelV<240) begin
        RGBchannel_reg <= 24'b111111110000000000000000;
      end else if (pixelH >=320 && pixelV<240) begin
        RGBchannel_reg <= 24'b000000001111111100000000;
      end else if (pixelH <320 && pixelV>=240) begin
        RGBchannel_reg <= 24'b000000000000000011111111;
      end else begin
        RGBchannel_reg <= 24'b111111110000000011111111;
      end
    end else begin
      if (pixelH <200 && pixelV<240) begin
        RGBchannel_reg <=24'b111111111111111100000000;
      end else if (pixelH <420 && pixelV<240) begin
        RGBchannel_reg <=24'b000000001111111111111111;
      end else if(pixelH >=420 && pixelV<240) begin
        RGBchannel_reg <=24'b111111111111111111111111;
      end else if (pixelH <200 && pixelV>=240) begin
        RGBchannel_reg <=24'b000000001111111100000000;
      end else if (pixelH <400 && pixelV>=240) begin
        RGBchannel_reg <=24'b000000000000000000000000;
      end else begin
        RGBchannel_reg <=24'b111111110000000011111111;
      end



    end
  end

end





lane lane(
  .clk(clock50), 
  .reset_n(!reset),
  .enable_in(3'b111),
  
  .vs_in(vsync),
  .hs_in(hsync),
  .de_in(dataEnable),
  .r_in(RGBchannel_reg[23:16]),
  .g_in(RGBchannel_reg[15:8]),
  .b_in(RGBchannel_reg[7:0]),




  .r_out(RGBchannel_reg_sobel[23:16]),
  .g_out(RGBchannel_reg_sobel[15:8]),
  .b_out(RGBchannel_reg_sobel[7:0]),
  


);



assign RGBchannel = (switchSobel)? RGBchannel_reg_sobel : RGBchannel_reg;










endmodule