data/full_repos/permissive/485721981/sources/synthesis/pwm.v
data/verilator_xmls/be9eb65a-dd6b-4b1c-8adf-b0e2802652db.xml
module  pwm # (
		parameter C_CLK_FRQ = 100000000,
        parameter C_LEVEL_WIDTH = 8
	) (
		input rstb,
		input clk,
		input [C_LEVEL_WIDTH-1 : 0] level,
		output reg out
	);  







	reg [C_LEVEL_WIDTH - 1 : 0] rCount;
	






	always @ (posedge clk) begin
		

    	rCount <= (rstb ==  1'b0) ? { C_LEVEL_WIDTH {1'b0} } : rCount + 1;
    end







	always @ (posedge clk) begin
		out <= (rCount <= level) ? 1'b1 : 1'b0;
	end

endmodule
module  pwm # (
		parameter C_CLK_FRQ = 100000000,
        parameter C_LEVEL_WIDTH = 8
	) (
		input rstb,
		input clk,
		input [C_LEVEL_WIDTH-1 : 0] level,
		output reg out
	);
  







	reg [C_LEVEL_WIDTH - 1 : 0] rCount;
	






	always @ (posedge clk) begin
		

    	rCount <= (rstb ==  1'b0) ? { C_LEVEL_WIDTH {1'b0} } : rCount + 1;
    end







	always @ (posedge clk) begin
		out <= (rCount <= level) ? 1'b1 : 1'b0;
	end

endmodule