data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/macro/stickyx.v
data/verilator_xmls/e25ef703-2dc0-4e02-b0c8-8e9c058ed6aa.xml
module stickyx
    (
     clk,
     rst,
     upactive,
     alarm,
     upen,
     upws,
     updi,
     updo,
     lalarm
     );

parameter           WIDTH = 8;
input               clk;
input               rst;
input               upactive;
input               upen;
input               upws;
input   [WIDTH-1:0] alarm;
input   [WIDTH-1:0] updi;

output  [WIDTH-1:0] updo;
output  [WIDTH-1:0] lalarm;

wire                we;
assign we = upen & upws;

reg     [WIDTH-1:0] lalarm;

assign updo = upen ? lalarm : {WIDTH{1'b0}};

always @(posedge clk)
    begin
    if (rst) 
        lalarm <= {WIDTH{1'b0}};
    else if (~upactive)
        begin
        if(we) lalarm <= updi;
        end
    else if (we)
        lalarm <= alarm | (lalarm & ~updi);
    else 
        lalarm <= alarm | lalarm;
    end

endmodule
module stickyx
    (
     clk,
     rst,
     upactive,
     alarm,
     upen,
     upws,
     updi,
     updo,
     lalarm
     );


parameter           WIDTH = 8;
input               clk;
input               rst;
input               upactive;
input               upen;
input               upws;
input   [WIDTH-1:0] alarm;
input   [WIDTH-1:0] updi;

output  [WIDTH-1:0] updo;
output  [WIDTH-1:0] lalarm;

wire                we;
assign we = upen & upws;

reg     [WIDTH-1:0] lalarm;

assign updo = upen ? lalarm : {WIDTH{1'b0}};

always @(posedge clk)
    begin
    if (rst) 
        lalarm <= {WIDTH{1'b0}};
    else if (~upactive)
        begin
        if(we) lalarm <= updi;
        end
    else if (we)
        lalarm <= alarm | (lalarm & ~updi);
    else 
        lalarm <= alarm | lalarm;
    end

endmodule