data/full_repos/permissive/491294671/magnetron_control/hdl/latch_sr.v
data/verilator_xmls/ca18717f-47e4-41ce-8683-6135e5ce35ee.xml
module latch_sr(
	input wire s, r,
	output reg q
);


	always @ (s, r) 
	begin
	
		if(s == 0 && r == 0)
			q <= q;
		
		else if(s == 0 && r == 1)
			q <= 0;
		
		else if(s == 1 && r == 0)
			q <= 1;
		
		else if(s == 1 && r == 1)
			q <= 1'bX;

	end

endmodule
module latch_sr(
	input wire s, r,
	output reg q
);



	always @ (s, r) 
	begin
	
		if(s == 0 && r == 0)
			q <= q;
		
		else if(s == 0 && r == 1)
			q <= 0;
		
		else if(s == 1 && r == 0)
			q <= 1;
		
		else if(s == 1 && r == 1)
			q <= 1'bX;

	end

endmodule