data/full_repos/permissive/411457613/Pyverilog/verilogcode/delay.v
data/verilator_xmls/d05631fc-81ad-4082-93b4-41ea42ff06b8.xml
module main #
(
 parameter STEP = 10
)
(
 input CLK,
 input RST,
 output reg [7:0] LED
 );

  localparam DELAY = 10;
  
  always @(posedge CLK) begin
    if(RST) begin
      LED <= 0;
    end else begin
      LED <= #DELAY LED + 1;
    end
  end
endmodule
module main #
(
 parameter STEP = 10
)
(
 input CLK,
 input RST,
 output reg [7:0] LED
 );


  localparam DELAY = 10;
  
  always @(posedge CLK) begin
    if(RST) begin
      LED <= 0;
    end else begin
      LED <= #DELAY LED + 1;
    end
  end
endmodule