data/full_repos/permissive/451853158/MIPS_Single_Cycle_Processor/dataMem.v
data/verilator_xmls/1f4b39ea-8853-49a1-a21b-29f81a6058bb.xml
module dataMem(
  input clk, wrEn,
  input [31:0] addr, wrData,
  output wire [31:0] rdData
);

reg [31:0] dmem [63:0];

assign rdData = dmem[addr[7:2]];

always @(posedge clk)
  if (wrEn)
    dmem[addr[7:2]] <= wrData;

endmodule
module dataMem(
  input clk, wrEn,
  input [31:0] addr, wrData,
  output wire [31:0] rdData
);


reg [31:0] dmem [63:0];

assign rdData = dmem[addr[7:2]];

always @(posedge clk)
  if (wrEn)
    dmem[addr[7:2]] <= wrData;

endmodule