data/full_repos/permissive/466926510/Project_files/mux_B.v
data/verilator_xmls/72099645-09f6-4dc3-8cd9-01a90642c4df.xml
module mux_B(
i_1 , i_2 , o_B  , sel_B 
    );
  
 input sel_B ;
 input [`MUX_WIDTH1-1:0] i_1 , i_2 ; 
 output[`MUX_WIDTH1-1:0] o_B ;  
 
 assign o_B = sel_B ? i_2 :i_1 ;
 
endmodule
module mux_B(
i_1 , i_2 , o_B  , sel_B 
    );

  
 input sel_B ;
 input [`MUX_WIDTH1-1:0] i_1 , i_2 ; 
 output[`MUX_WIDTH1-1:0] o_B ;  
 
 assign o_B = sel_B ? i_2 :i_1 ;
 
endmodule