data/full_repos/permissive/459233267/sram.v
1: b'%Warning-WIDTH: data/full_repos/permissive/459233267/sram.v:10: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'buff\' generates 8 bits.\n                                                              : ... In instance sram\nassign dr = (cs & rd & !wr) ? buff : \'hz;\n                            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/459233267/sram.v:10: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                              : ... In instance sram\nassign dr = (cs & rd & !wr) ? buff : \'hz;\n          ^\n%Error: Exiting due to 2 warning(s)\n'
module sram(
    input clk,cs,rd,wr,
    input [3:0] ar,
    inout [7:0] dr
);

reg [7:0] memory[2**4 - 1 : 0];
reg [7:0] buff;

assign dr = (cs & rd & !wr) ? buff : 'hz;

always @(posedge clk) begin
    if(rd)
        buff <= memory[ar];
    else if(wr)
        memory[ar] <= dr;
end

endmodule
module sram(
    input clk,cs,rd,wr,
    input [3:0] ar,
    inout [7:0] dr
);


reg [7:0] memory[2**4 - 1 : 0];
reg [7:0] buff;

assign dr = (cs & rd & !wr) ? buff : 'hz;

always @(posedge clk) begin
    if(rd)
        buff <= memory[ar];
    else if(wr)
        memory[ar] <= dr;
end

endmodule