data/full_repos/permissive/451853158/MIPS_Single_Cycle_Processor/mainDecoder.v
data/verilator_xmls/8229a5ab-12b3-4606-8ec7-e13a41d12f23.xml
module mainDecoder (
  input      [5:0] OPCode,
  output reg       MemtoReg, MemWrite, Branch, ALUSrc, RegDst, RegWrite, Jump,
  output reg [1:0] ALUOp
);



always @(*)
  case (OPCode)
    6'b000000:
      {RegWrite, RegDst, ALUSrc, Branch, MemWrite, MemtoReg, ALUOp, Jump} = 9'b110000100;
	 
	  6'b100011:
	    {RegWrite, RegDst, ALUSrc, Branch, MemWrite, MemtoReg, ALUOp, Jump} = 9'b101001000;
	 
	  6'b101011:
	    {RegWrite, RegDst, ALUSrc, Branch, MemWrite, MemtoReg, ALUOp, Jump} = 9'b0x101x000;
	 
	  6'b000100:
	    {RegWrite, RegDst, ALUSrc, Branch, MemWrite, MemtoReg, ALUOp, Jump} = 9'b0x010x010;
	 
	  6'b001000:
	    {RegWrite, RegDst, ALUSrc, Branch, MemWrite, MemtoReg, ALUOp, Jump} = 9'b101000000;
	 
	  6'b000010:
	    {RegWrite, RegDst, ALUSrc, Branch, MemWrite, MemtoReg, ALUOp, Jump} = 9'b0xxx0xxx1;
	 
	 default: 
	   {RegWrite, RegDst, ALUSrc, Branch, MemWrite, MemtoReg, ALUOp, Jump} = 9'bxxxxxxxxx;
  endcase

endmodule
module mainDecoder (
  input      [5:0] OPCode,
  output reg       MemtoReg, MemWrite, Branch, ALUSrc, RegDst, RegWrite, Jump,
  output reg [1:0] ALUOp
);




always @(*)
  case (OPCode)
    6'b000000:
      {RegWrite, RegDst, ALUSrc, Branch, MemWrite, MemtoReg, ALUOp, Jump} = 9'b110000100;
	 
	  6'b100011:
	    {RegWrite, RegDst, ALUSrc, Branch, MemWrite, MemtoReg, ALUOp, Jump} = 9'b101001000;
	 
	  6'b101011:
	    {RegWrite, RegDst, ALUSrc, Branch, MemWrite, MemtoReg, ALUOp, Jump} = 9'b0x101x000;
	 
	  6'b000100:
	    {RegWrite, RegDst, ALUSrc, Branch, MemWrite, MemtoReg, ALUOp, Jump} = 9'b0x010x010;
	 
	  6'b001000:
	    {RegWrite, RegDst, ALUSrc, Branch, MemWrite, MemtoReg, ALUOp, Jump} = 9'b101000000;
	 
	  6'b000010:
	    {RegWrite, RegDst, ALUSrc, Branch, MemWrite, MemtoReg, ALUOp, Jump} = 9'b0xxx0xxx1;
	 
	 default: 
	   {RegWrite, RegDst, ALUSrc, Branch, MemWrite, MemtoReg, ALUOp, Jump} = 9'bxxxxxxxxx;
  endcase

endmodule