data/full_repos/permissive/513806017/generated/Hello.v
data/verilator_xmls/8cd341e1-d444-46ce-b0bf-2288791e475a.xml
module Hello(
  input   clock,
  input   reset,
  output  io_led1,
  output  io_led2,
  output  io_txd
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
`endif
  wire  tx_clock;
  wire  tx_reset;
  wire  tx_io_in_ready;
  wire  tx_io_in_valid;
  wire [7:0] tx_io_in_bits;
  wire  tx_io_txd;
  reg [31:0] cntReg;
  reg  blkReg1;
  reg  blkReg2;
  reg [7:0] txCntReg;
  reg [7:0] txLenReg;
  reg  startTxReg;
  reg  runningTxReg;
  wire [31:0] _cntReg_T_1 = cntReg + 32'h1;
  wire  _GEN_2 = cntReg == 32'hb71b00 ? blkReg1 : blkReg2;
  wire  _GEN_3 = cntReg == 32'hb71b00 | startTxReg;
  wire  _GEN_5 = startTxReg | runningTxReg;
  wire [6:0] _GEN_8 = txCntReg[0] ? 7'h4e : 7'h4f;
  wire [6:0] _GEN_10 = 2'h1 == txCntReg[1:0] ? 7'h46 : 7'h4f;
  wire [6:0] _GEN_11 = 2'h2 == txCntReg[1:0] ? 7'h46 : _GEN_10;
  wire [1:0] _GEN_12 = blkReg1 ? 2'h2 : 2'h3;
  wire [6:0] _GEN_13 = blkReg1 ? _GEN_8 : _GEN_11;
  wire  _T_3 = txCntReg != txLenReg;
  wire [7:0] _txCntReg_T_1 = txCntReg + 8'h1;
  wire  _GEN_16 = _T_3 & _GEN_5;
  BufferedTx tx (
    .clock(tx_clock),
    .reset(tx_reset),
    .io_in_ready(tx_io_in_ready),
    .io_in_valid(tx_io_in_valid),
    .io_in_bits(tx_io_in_bits),
    .io_txd(tx_io_txd)
  );
  assign io_led1 = blkReg1;
  assign io_led2 = blkReg2;
  assign io_txd = tx_io_txd;
  assign tx_clock = clock;
  assign tx_reset = reset;
  assign tx_io_in_valid = runningTxReg & _T_3;
  assign tx_io_in_bits = {{1'd0}, _GEN_13};
  always @(posedge clock) begin
    if (reset) begin
      cntReg <= 32'h0;
    end else if (cntReg == 32'hb71b00) begin
      cntReg <= 32'h0;
    end else begin
      cntReg <= _cntReg_T_1;
    end
    if (reset) begin
      blkReg1 <= 1'h0;
    end else if (cntReg == 32'hb71b00) begin
      blkReg1 <= ~blkReg1;
    end
    blkReg2 <= reset | _GEN_2;
    if (reset) begin
      txCntReg <= 8'h0;
    end else if (tx_io_in_ready & txCntReg != txLenReg) begin
      txCntReg <= _txCntReg_T_1;
    end else if (startTxReg) begin
      txCntReg <= 8'h0;
    end
    if (reset) begin
      txLenReg <= 8'h0;
    end else begin
      txLenReg <= {{6'd0}, _GEN_12};
    end
    if (reset) begin
      startTxReg <= 1'h0;
    end else if (startTxReg) begin
      startTxReg <= 1'h0;
    end else begin
      startTxReg <= _GEN_3;
    end
    if (reset) begin
      runningTxReg <= 1'h0;
    end else if (runningTxReg) begin
      runningTxReg <= _GEN_16;
    end else begin
      runningTxReg <= _GEN_5;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  cntReg = _RAND_0[31:0];
  _RAND_1 = {1{`RANDOM}};
  blkReg1 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  blkReg2 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  txCntReg = _RAND_3[7:0];
  _RAND_4 = {1{`RANDOM}};
  txLenReg = _RAND_4[7:0];
  _RAND_5 = {1{`RANDOM}};
  startTxReg = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  runningTxReg = _RAND_6[0:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module Hello(
  input   clock,
  input   reset,
  output  io_led1,
  output  io_led2,
  output  io_txd
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
`endif
  wire  tx_clock;
  wire  tx_reset;
  wire  tx_io_in_ready;
  wire  tx_io_in_valid;
  wire [7:0] tx_io_in_bits;
  wire  tx_io_txd;
  reg [31:0] cntReg;
  reg  blkReg1;
  reg  blkReg2;
  reg [7:0] txCntReg;
  reg [7:0] txLenReg;
  reg  startTxReg;
  reg  runningTxReg;
  wire [31:0] _cntReg_T_1 = cntReg + 32'h1;
  wire  _GEN_2 = cntReg == 32'hb71b00 ? blkReg1 : blkReg2;
  wire  _GEN_3 = cntReg == 32'hb71b00 | startTxReg;
  wire  _GEN_5 = startTxReg | runningTxReg;
  wire [6:0] _GEN_8 = txCntReg[0] ? 7'h4e : 7'h4f;
  wire [6:0] _GEN_10 = 2'h1 == txCntReg[1:0] ? 7'h46 : 7'h4f;
  wire [6:0] _GEN_11 = 2'h2 == txCntReg[1:0] ? 7'h46 : _GEN_10;
  wire [1:0] _GEN_12 = blkReg1 ? 2'h2 : 2'h3;
  wire [6:0] _GEN_13 = blkReg1 ? _GEN_8 : _GEN_11;
  wire  _T_3 = txCntReg != txLenReg;
  wire [7:0] _txCntReg_T_1 = txCntReg + 8'h1;
  wire  _GEN_16 = _T_3 & _GEN_5;
  BufferedTx tx (
    .clock(tx_clock),
    .reset(tx_reset),
    .io_in_ready(tx_io_in_ready),
    .io_in_valid(tx_io_in_valid),
    .io_in_bits(tx_io_in_bits),
    .io_txd(tx_io_txd)
  );
  assign io_led1 = blkReg1;
  assign io_led2 = blkReg2;
  assign io_txd = tx_io_txd;
  assign tx_clock = clock;
  assign tx_reset = reset;
  assign tx_io_in_valid = runningTxReg & _T_3;
  assign tx_io_in_bits = {{1'd0}, _GEN_13};
  always @(posedge clock) begin
    if (reset) begin
      cntReg <= 32'h0;
    end else if (cntReg == 32'hb71b00) begin
      cntReg <= 32'h0;
    end else begin
      cntReg <= _cntReg_T_1;
    end
    if (reset) begin
      blkReg1 <= 1'h0;
    end else if (cntReg == 32'hb71b00) begin
      blkReg1 <= ~blkReg1;
    end
    blkReg2 <= reset | _GEN_2;
    if (reset) begin
      txCntReg <= 8'h0;
    end else if (tx_io_in_ready & txCntReg != txLenReg) begin
      txCntReg <= _txCntReg_T_1;
    end else if (startTxReg) begin
      txCntReg <= 8'h0;
    end
    if (reset) begin
      txLenReg <= 8'h0;
    end else begin
      txLenReg <= {{6'd0}, _GEN_12};
    end
    if (reset) begin
      startTxReg <= 1'h0;
    end else if (startTxReg) begin
      startTxReg <= 1'h0;
    end else begin
      startTxReg <= _GEN_3;
    end
    if (reset) begin
      runningTxReg <= 1'h0;
    end else if (runningTxReg) begin
      runningTxReg <= _GEN_16;
    end else begin
      runningTxReg <= _GEN_5;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  cntReg = _RAND_0[31:0];
  _RAND_1 = {1{`RANDOM}};
  blkReg1 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  blkReg2 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  txCntReg = _RAND_3[7:0];
  _RAND_4 = {1{`RANDOM}};
  txLenReg = _RAND_4[7:0];
  _RAND_5 = {1{`RANDOM}};
  startTxReg = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  runningTxReg = _RAND_6[0:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule