data/full_repos/permissive/428125225/divider_module.v
1: b'%Warning-WIDTH: data/full_repos/permissive/428125225/divider_module.v:29: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 12 bits.\n                                                                        : ... In instance divider_module\nt={4\'b0000,divisor};\n ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module divider_module
(dividend,divisor,clk,rst,quotient,reminder);

input [7:0]dividend;
input [7:0]divisor;
input clk;
input rst;
output [7:0]quotient;
output [7:0]reminder;

reg [7:0]q;
reg [7:0]r;
reg [7:0]t;
wire [7:0]quotient;
wire [7:0]reminder;
integer i;
parameter j=8;

always@(posedge clk or negedge rst)
begin
if(!rst)
begin
q=0;
r=0;
end
else
begin
q=dividend;
t={4'b0000,divisor};
r=8'b00000000;
{r,q}={r,q}<<1;


for(i=0;i<j;i=i+1)
if(r>=t)
begin
r=r-t;
{r,q}={r,q}<<1;
q[0]=1;
end
else
begin
r=r;
{r,q}={r,q}<<1;
q[0]=0;
end
end
end
assign quotient=q;
assign reminder=r>>1;
endmodule
module divider_module
(dividend,divisor,clk,rst,quotient,reminder);


input [7:0]dividend;
input [7:0]divisor;
input clk;
input rst;
output [7:0]quotient;
output [7:0]reminder;

reg [7:0]q;
reg [7:0]r;
reg [7:0]t;
wire [7:0]quotient;
wire [7:0]reminder;
integer i;
parameter j=8;

always@(posedge clk or negedge rst)
begin
if(!rst)
begin
q=0;
r=0;
end
else
begin
q=dividend;
t={4'b0000,divisor};
r=8'b00000000;
{r,q}={r,q}<<1;


for(i=0;i<j;i=i+1)
if(r>=t)
begin
r=r-t;
{r,q}={r,q}<<1;
q[0]=1;
end
else
begin
r=r;
{r,q}={r,q}<<1;
q[0]=0;
end
end
end
assign quotient=q;
assign reminder=r>>1;
endmodule