data/full_repos/permissive/437204475/sim/testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/437204475/sim/testbench.v:17: Unsupported: Ignoring delay on this delayed statement.\n         #10 clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/437204475/sim/testbench.v:23: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("sim.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/437204475/sim/testbench.v:24: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, tb_top);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/437204475/sim/testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n      #25 rst = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/437204475/sim/testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n      #5000;\n      ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_top;

   reg clk;
   reg rst;

   top top_inst(
      .rst(rst),
      .clk(clk)
   );


   initial begin
      clk = 0;
      forever begin
         #10 clk = ~clk;
      end
   end


   initial begin
      $dumpfile("sim.vcd");
      $dumpvars(0, tb_top);
   end


   initial begin
      rst = 1;
      #25 rst = 0;
      #5000;
      $finish;
   end

endmodule
module tb_top;


   reg clk;
   reg rst;

   top top_inst(
      .rst(rst),
      .clk(clk)
   );


   initial begin
      clk = 0;
      forever begin
         #10 clk = ~clk;
      end
   end


   initial begin
      $dumpfile("sim.vcd");
      $dumpvars(0, tb_top);
   end


   initial begin
      rst = 1;
      #25 rst = 0;
      #5000;
      $finish;
   end

endmodule