data/full_repos/permissive/471533249/comp_unit.sv
1: b"%Error: data/full_repos/permissive/471533249/comp_unit.sv:24: Cannot find file containing module: 'FP_Mult'\n FP_Mult mult(mult_en, clk, Ain, Bin, m_overflow, multout);\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/471533249,data/full_repos/permissive/471533249/FP_Mult\n             data/full_repos/permissive/471533249,data/full_repos/permissive/471533249/FP_Mult.v\n             data/full_repos/permissive/471533249,data/full_repos/permissive/471533249/FP_Mult.sv\n             FP_Mult\n             FP_Mult.v\n             FP_Mult.sv\n             obj_dir/FP_Mult\n             obj_dir/FP_Mult.v\n             obj_dir/FP_Mult.sv\n%Error: data/full_repos/permissive/471533249/comp_unit.sv:27: Cannot find file containing module: 'FP_Adder'\n FP_Adder adder(add_en, clk, multout, Cout, a_overflow, Cin);\n ^~~~~~~~\n%Error: data/full_repos/permissive/471533249/comp_unit.sv:30: Cannot find file containing module: 'register'\n register #(32) A(clk, reset, out_en, Ain, Aout);\n ^~~~~~~~\n%Error: data/full_repos/permissive/471533249/comp_unit.sv:31: Cannot find file containing module: 'register'\n register #(32) B(clk, reset, out_en, Bin, Bout);\n ^~~~~~~~\n%Error: data/full_repos/permissive/471533249/comp_unit.sv:32: Cannot find file containing module: 'register'\n register #(32) C(clk, reset, out_en, Cin, Cout);\n ^~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module comp_unit(clk, reset,  mult_en, add_en, out_en, Ain, Bin, Cout, Aout, Bout, overflow);
	

	input logic clk, reset, mult_en, add_en, out_en;
	input logic [31:0] Ain, Bin;
	

	output logic overflow;
	output logic [31:0] Cout, Aout, Bout;
	

	logic  m_overflow, a_overflow;
	logic [31:0] multout,  Cin;
	

	FP_Mult mult(mult_en, clk, Ain, Bin, m_overflow, multout);
	

	FP_Adder adder(add_en, clk, multout, Cout, a_overflow, Cin);
	

	register #(32) A(clk, reset, out_en, Ain, Aout);
	register #(32) B(clk, reset, out_en, Bin, Bout);
	register #(32) C(clk, reset, out_en, Cin, Cout);
	

	assign overflow = m_overflow | a_overflow;

endmodule
module comp_unit(clk, reset,  mult_en, add_en, out_en, Ain, Bin, Cout, Aout, Bout, overflow);

	

	input logic clk, reset, mult_en, add_en, out_en;
	input logic [31:0] Ain, Bin;
	

	output logic overflow;
	output logic [31:0] Cout, Aout, Bout;
	

	logic  m_overflow, a_overflow;
	logic [31:0] multout,  Cin;
	

	FP_Mult mult(mult_en, clk, Ain, Bin, m_overflow, multout);
	

	FP_Adder adder(add_en, clk, multout, Cout, a_overflow, Cin);
	

	register #(32) A(clk, reset, out_en, Ain, Aout);
	register #(32) B(clk, reset, out_en, Bin, Bout);
	register #(32) C(clk, reset, out_en, Cin, Cout);
	

	assign overflow = m_overflow | a_overflow;

endmodule