data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v
1: b'%Error: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:32: Unsupported: fork statements\ninitial fork\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:36: Unsupported: Ignoring delay on this delayed statement.\n #1 OP = 0  ; #1 IR[27:25] = 0  ; #1 IR[11:7] = 0  ; #1 IR[6:5] = 0  ; #1 IR[4]=1   ; #1 IR[19:16] = 0   ; #1 IR[3:0] = 0  ; #1 IR[11:8] = 0  ; #1 IR[15:12] = 0  ; #1 RSLCT[19:16] = 0   ;#1 RESET = 0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ;#1 S=0;#1 ALU_OUT=0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:36: Unsupported: Ignoring delay on this delayed statement.\n #1 OP = 0  ; #1 IR[27:25] = 0  ; #1 IR[11:7] = 0  ; #1 IR[6:5] = 0  ; #1 IR[4]=1   ; #1 IR[19:16] = 0   ; #1 IR[3:0] = 0  ; #1 IR[11:8] = 0  ; #1 IR[15:12] = 0  ; #1 RSLCT[19:16] = 0   ;#1 RESET = 0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ;#1 S=0;#1 ALU_OUT=0;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:36: Unsupported: Ignoring delay on this delayed statement.\n #1 OP = 0  ; #1 IR[27:25] = 0  ; #1 IR[11:7] = 0  ; #1 IR[6:5] = 0  ; #1 IR[4]=1   ; #1 IR[19:16] = 0   ; #1 IR[3:0] = 0  ; #1 IR[11:8] = 0  ; #1 IR[15:12] = 0  ; #1 RSLCT[19:16] = 0   ;#1 RESET = 0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ;#1 S=0;#1 ALU_OUT=0;\n                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:36: Unsupported: Ignoring delay on this delayed statement.\n #1 OP = 0  ; #1 IR[27:25] = 0  ; #1 IR[11:7] = 0  ; #1 IR[6:5] = 0  ; #1 IR[4]=1   ; #1 IR[19:16] = 0   ; #1 IR[3:0] = 0  ; #1 IR[11:8] = 0  ; #1 IR[15:12] = 0  ; #1 RSLCT[19:16] = 0   ;#1 RESET = 0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ;#1 S=0;#1 ALU_OUT=0;\n                                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:36: Unsupported: Ignoring delay on this delayed statement.\n #1 OP = 0  ; #1 IR[27:25] = 0  ; #1 IR[11:7] = 0  ; #1 IR[6:5] = 0  ; #1 IR[4]=1   ; #1 IR[19:16] = 0   ; #1 IR[3:0] = 0  ; #1 IR[11:8] = 0  ; #1 IR[15:12] = 0  ; #1 RSLCT[19:16] = 0   ;#1 RESET = 0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ;#1 S=0;#1 ALU_OUT=0;\n                                                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:36: Unsupported: Ignoring delay on this delayed statement.\n #1 OP = 0  ; #1 IR[27:25] = 0  ; #1 IR[11:7] = 0  ; #1 IR[6:5] = 0  ; #1 IR[4]=1   ; #1 IR[19:16] = 0   ; #1 IR[3:0] = 0  ; #1 IR[11:8] = 0  ; #1 IR[15:12] = 0  ; #1 RSLCT[19:16] = 0   ;#1 RESET = 0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ;#1 S=0;#1 ALU_OUT=0;\n                                                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:36: Unsupported: Ignoring delay on this delayed statement.\n #1 OP = 0  ; #1 IR[27:25] = 0  ; #1 IR[11:7] = 0  ; #1 IR[6:5] = 0  ; #1 IR[4]=1   ; #1 IR[19:16] = 0   ; #1 IR[3:0] = 0  ; #1 IR[11:8] = 0  ; #1 IR[15:12] = 0  ; #1 RSLCT[19:16] = 0   ;#1 RESET = 0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ;#1 S=0;#1 ALU_OUT=0;\n                                                                                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:36: Unsupported: Ignoring delay on this delayed statement.\n #1 OP = 0  ; #1 IR[27:25] = 0  ; #1 IR[11:7] = 0  ; #1 IR[6:5] = 0  ; #1 IR[4]=1   ; #1 IR[19:16] = 0   ; #1 IR[3:0] = 0  ; #1 IR[11:8] = 0  ; #1 IR[15:12] = 0  ; #1 RSLCT[19:16] = 0   ;#1 RESET = 0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ;#1 S=0;#1 ALU_OUT=0;\n                                                                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:36: Unsupported: Ignoring delay on this delayed statement.\n #1 OP = 0  ; #1 IR[27:25] = 0  ; #1 IR[11:7] = 0  ; #1 IR[6:5] = 0  ; #1 IR[4]=1   ; #1 IR[19:16] = 0   ; #1 IR[3:0] = 0  ; #1 IR[11:8] = 0  ; #1 IR[15:12] = 0  ; #1 RSLCT[19:16] = 0   ;#1 RESET = 0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ;#1 S=0;#1 ALU_OUT=0;\n                                                                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:36: Unsupported: Ignoring delay on this delayed statement.\n #1 OP = 0  ; #1 IR[27:25] = 0  ; #1 IR[11:7] = 0  ; #1 IR[6:5] = 0  ; #1 IR[4]=1   ; #1 IR[19:16] = 0   ; #1 IR[3:0] = 0  ; #1 IR[11:8] = 0  ; #1 IR[15:12] = 0  ; #1 RSLCT[19:16] = 0   ;#1 RESET = 0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ;#1 S=0;#1 ALU_OUT=0;\n                                                                                                                                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:36: Unsupported: Ignoring delay on this delayed statement.\n #1 OP = 0  ; #1 IR[27:25] = 0  ; #1 IR[11:7] = 0  ; #1 IR[6:5] = 0  ; #1 IR[4]=1   ; #1 IR[19:16] = 0   ; #1 IR[3:0] = 0  ; #1 IR[11:8] = 0  ; #1 IR[15:12] = 0  ; #1 RSLCT[19:16] = 0   ;#1 RESET = 0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ;#1 S=0;#1 ALU_OUT=0;\n                                                                                                                                                                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:36: Unsupported: Ignoring delay on this delayed statement.\n #1 OP = 0  ; #1 IR[27:25] = 0  ; #1 IR[11:7] = 0  ; #1 IR[6:5] = 0  ; #1 IR[4]=1   ; #1 IR[19:16] = 0   ; #1 IR[3:0] = 0  ; #1 IR[11:8] = 0  ; #1 IR[15:12] = 0  ; #1 RSLCT[19:16] = 0   ;#1 RESET = 0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ;#1 S=0;#1 ALU_OUT=0;\n                                                                                                                                                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:36: Unsupported: Ignoring delay on this delayed statement.\n #1 OP = 0  ; #1 IR[27:25] = 0  ; #1 IR[11:7] = 0  ; #1 IR[6:5] = 0  ; #1 IR[4]=1   ; #1 IR[19:16] = 0   ; #1 IR[3:0] = 0  ; #1 IR[11:8] = 0  ; #1 IR[15:12] = 0  ; #1 RSLCT[19:16] = 0   ;#1 RESET = 0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ;#1 S=0;#1 ALU_OUT=0;\n                                                                                                                                                                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:36: Unsupported: Ignoring delay on this delayed statement.\n #1 OP = 0  ; #1 IR[27:25] = 0  ; #1 IR[11:7] = 0  ; #1 IR[6:5] = 0  ; #1 IR[4]=1   ; #1 IR[19:16] = 0   ; #1 IR[3:0] = 0  ; #1 IR[11:8] = 0  ; #1 IR[15:12] = 0  ; #1 RSLCT[19:16] = 0   ;#1 RESET = 0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ;#1 S=0;#1 ALU_OUT=0;\n                                                                                                                                                                                                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:36: Unsupported: Ignoring delay on this delayed statement.\n #1 OP = 0  ; #1 IR[27:25] = 0  ; #1 IR[11:7] = 0  ; #1 IR[6:5] = 0  ; #1 IR[4]=1   ; #1 IR[19:16] = 0   ; #1 IR[3:0] = 0  ; #1 IR[11:8] = 0  ; #1 IR[15:12] = 0  ; #1 RSLCT[19:16] = 0   ;#1 RESET = 0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ;#1 S=0;#1 ALU_OUT=0;\n                                                                                                                                                                                                                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:36: Unsupported: Ignoring delay on this delayed statement.\n #1 OP = 0  ; #1 IR[27:25] = 0  ; #1 IR[11:7] = 0  ; #1 IR[6:5] = 0  ; #1 IR[4]=1   ; #1 IR[19:16] = 0   ; #1 IR[3:0] = 0  ; #1 IR[11:8] = 0  ; #1 IR[15:12] = 0  ; #1 RSLCT[19:16] = 0   ;#1 RESET = 0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ;#1 S=0;#1 ALU_OUT=0;\n                                                                                                                                                                                                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:38: Unsupported: Ignoring delay on this delayed statement.\n #2 OP = 17; #2 IR[27:25] = 0  ; #2 IR[11:7] = 0  ; #2 IR[6:5] = 1  ; #2 IR[4]=0   ; #2 IR[19:16] = 0   ; #2 IR[3:0] = 0  ; #2 IR[11:8] = 0  ; #2 IR[15:12] = 0  ; #2 RSLCT[19:16] = 0   ;#2 RESET = 0 ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ;#2 S=1;#2 ALU_OUT=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:38: Unsupported: Ignoring delay on this delayed statement.\n #2 OP = 17; #2 IR[27:25] = 0  ; #2 IR[11:7] = 0  ; #2 IR[6:5] = 1  ; #2 IR[4]=0   ; #2 IR[19:16] = 0   ; #2 IR[3:0] = 0  ; #2 IR[11:8] = 0  ; #2 IR[15:12] = 0  ; #2 RSLCT[19:16] = 0   ;#2 RESET = 0 ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ;#2 S=1;#2 ALU_OUT=1;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:38: Unsupported: Ignoring delay on this delayed statement.\n #2 OP = 17; #2 IR[27:25] = 0  ; #2 IR[11:7] = 0  ; #2 IR[6:5] = 1  ; #2 IR[4]=0   ; #2 IR[19:16] = 0   ; #2 IR[3:0] = 0  ; #2 IR[11:8] = 0  ; #2 IR[15:12] = 0  ; #2 RSLCT[19:16] = 0   ;#2 RESET = 0 ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ;#2 S=1;#2 ALU_OUT=1;\n                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:38: Unsupported: Ignoring delay on this delayed statement.\n #2 OP = 17; #2 IR[27:25] = 0  ; #2 IR[11:7] = 0  ; #2 IR[6:5] = 1  ; #2 IR[4]=0   ; #2 IR[19:16] = 0   ; #2 IR[3:0] = 0  ; #2 IR[11:8] = 0  ; #2 IR[15:12] = 0  ; #2 RSLCT[19:16] = 0   ;#2 RESET = 0 ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ;#2 S=1;#2 ALU_OUT=1;\n                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:38: Unsupported: Ignoring delay on this delayed statement.\n #2 OP = 17; #2 IR[27:25] = 0  ; #2 IR[11:7] = 0  ; #2 IR[6:5] = 1  ; #2 IR[4]=0   ; #2 IR[19:16] = 0   ; #2 IR[3:0] = 0  ; #2 IR[11:8] = 0  ; #2 IR[15:12] = 0  ; #2 RSLCT[19:16] = 0   ;#2 RESET = 0 ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ;#2 S=1;#2 ALU_OUT=1;\n                                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:38: Unsupported: Ignoring delay on this delayed statement.\n #2 OP = 17; #2 IR[27:25] = 0  ; #2 IR[11:7] = 0  ; #2 IR[6:5] = 1  ; #2 IR[4]=0   ; #2 IR[19:16] = 0   ; #2 IR[3:0] = 0  ; #2 IR[11:8] = 0  ; #2 IR[15:12] = 0  ; #2 RSLCT[19:16] = 0   ;#2 RESET = 0 ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ;#2 S=1;#2 ALU_OUT=1;\n                                                                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:38: Unsupported: Ignoring delay on this delayed statement.\n #2 OP = 17; #2 IR[27:25] = 0  ; #2 IR[11:7] = 0  ; #2 IR[6:5] = 1  ; #2 IR[4]=0   ; #2 IR[19:16] = 0   ; #2 IR[3:0] = 0  ; #2 IR[11:8] = 0  ; #2 IR[15:12] = 0  ; #2 RSLCT[19:16] = 0   ;#2 RESET = 0 ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ;#2 S=1;#2 ALU_OUT=1;\n                                                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:38: Unsupported: Ignoring delay on this delayed statement.\n #2 OP = 17; #2 IR[27:25] = 0  ; #2 IR[11:7] = 0  ; #2 IR[6:5] = 1  ; #2 IR[4]=0   ; #2 IR[19:16] = 0   ; #2 IR[3:0] = 0  ; #2 IR[11:8] = 0  ; #2 IR[15:12] = 0  ; #2 RSLCT[19:16] = 0   ;#2 RESET = 0 ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ;#2 S=1;#2 ALU_OUT=1;\n                                                                                                                            ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:38: Unsupported: Ignoring delay on this delayed statement.\n #2 OP = 17; #2 IR[27:25] = 0  ; #2 IR[11:7] = 0  ; #2 IR[6:5] = 1  ; #2 IR[4]=0   ; #2 IR[19:16] = 0   ; #2 IR[3:0] = 0  ; #2 IR[11:8] = 0  ; #2 IR[15:12] = 0  ; #2 RSLCT[19:16] = 0   ;#2 RESET = 0 ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ;#2 S=1;#2 ALU_OUT=1;\n                                                                                                                                               ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:38: Unsupported: Ignoring delay on this delayed statement.\n #2 OP = 17; #2 IR[27:25] = 0  ; #2 IR[11:7] = 0  ; #2 IR[6:5] = 1  ; #2 IR[4]=0   ; #2 IR[19:16] = 0   ; #2 IR[3:0] = 0  ; #2 IR[11:8] = 0  ; #2 IR[15:12] = 0  ; #2 RSLCT[19:16] = 0   ;#2 RESET = 0 ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ;#2 S=1;#2 ALU_OUT=1;\n                                                                                                                                                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:38: Unsupported: Ignoring delay on this delayed statement.\n #2 OP = 17; #2 IR[27:25] = 0  ; #2 IR[11:7] = 0  ; #2 IR[6:5] = 1  ; #2 IR[4]=0   ; #2 IR[19:16] = 0   ; #2 IR[3:0] = 0  ; #2 IR[11:8] = 0  ; #2 IR[15:12] = 0  ; #2 RSLCT[19:16] = 0   ;#2 RESET = 0 ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ;#2 S=1;#2 ALU_OUT=1;\n                                                                                                                                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:38: Unsupported: Ignoring delay on this delayed statement.\n #2 OP = 17; #2 IR[27:25] = 0  ; #2 IR[11:7] = 0  ; #2 IR[6:5] = 1  ; #2 IR[4]=0   ; #2 IR[19:16] = 0   ; #2 IR[3:0] = 0  ; #2 IR[11:8] = 0  ; #2 IR[15:12] = 0  ; #2 RSLCT[19:16] = 0   ;#2 RESET = 0 ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ;#2 S=1;#2 ALU_OUT=1;\n                                                                                                                                                                                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:38: Unsupported: Ignoring delay on this delayed statement.\n #2 OP = 17; #2 IR[27:25] = 0  ; #2 IR[11:7] = 0  ; #2 IR[6:5] = 1  ; #2 IR[4]=0   ; #2 IR[19:16] = 0   ; #2 IR[3:0] = 0  ; #2 IR[11:8] = 0  ; #2 IR[15:12] = 0  ; #2 RSLCT[19:16] = 0   ;#2 RESET = 0 ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ;#2 S=1;#2 ALU_OUT=1;\n                                                                                                                                                                                                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:38: Unsupported: Ignoring delay on this delayed statement.\n #2 OP = 17; #2 IR[27:25] = 0  ; #2 IR[11:7] = 0  ; #2 IR[6:5] = 1  ; #2 IR[4]=0   ; #2 IR[19:16] = 0   ; #2 IR[3:0] = 0  ; #2 IR[11:8] = 0  ; #2 IR[15:12] = 0  ; #2 RSLCT[19:16] = 0   ;#2 RESET = 0 ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ;#2 S=1;#2 ALU_OUT=1;\n                                                                                                                                                                                                                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:38: Unsupported: Ignoring delay on this delayed statement.\n #2 OP = 17; #2 IR[27:25] = 0  ; #2 IR[11:7] = 0  ; #2 IR[6:5] = 1  ; #2 IR[4]=0   ; #2 IR[19:16] = 0   ; #2 IR[3:0] = 0  ; #2 IR[11:8] = 0  ; #2 IR[15:12] = 0  ; #2 RSLCT[19:16] = 0   ;#2 RESET = 0 ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ;#2 S=1;#2 ALU_OUT=1;\n                                                                                                                                                                                                                                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:38: Unsupported: Ignoring delay on this delayed statement.\n #2 OP = 17; #2 IR[27:25] = 0  ; #2 IR[11:7] = 0  ; #2 IR[6:5] = 1  ; #2 IR[4]=0   ; #2 IR[19:16] = 0   ; #2 IR[3:0] = 0  ; #2 IR[11:8] = 0  ; #2 IR[15:12] = 0  ; #2 RSLCT[19:16] = 0   ;#2 RESET = 0 ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ;#2 S=1;#2 ALU_OUT=1;\n                                                                                                                                                                                                                                                            ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:40: Unsupported: Ignoring delay on this delayed statement.\n #3 OP = 17 ; #3 IR[27:25] = 0  ; #3 IR[11:7] = 0  ; #3 IR[6:5] = 1  ; #3 IR[4]=0   ; #3 IR[19:16] = 0   ; #3 IR[3:0] = 0  ; #3 IR[11:8] = 0  ; #3 IR[15:12] = 0  ; #3 RSLCT[19:16] = 0   ;#3 RESET = 0 ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ;#3 S=1;#3 ALU_OUT=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:40: Unsupported: Ignoring delay on this delayed statement.\n #3 OP = 17 ; #3 IR[27:25] = 0  ; #3 IR[11:7] = 0  ; #3 IR[6:5] = 1  ; #3 IR[4]=0   ; #3 IR[19:16] = 0   ; #3 IR[3:0] = 0  ; #3 IR[11:8] = 0  ; #3 IR[15:12] = 0  ; #3 RSLCT[19:16] = 0   ;#3 RESET = 0 ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ;#3 S=1;#3 ALU_OUT=1;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:40: Unsupported: Ignoring delay on this delayed statement.\n #3 OP = 17 ; #3 IR[27:25] = 0  ; #3 IR[11:7] = 0  ; #3 IR[6:5] = 1  ; #3 IR[4]=0   ; #3 IR[19:16] = 0   ; #3 IR[3:0] = 0  ; #3 IR[11:8] = 0  ; #3 IR[15:12] = 0  ; #3 RSLCT[19:16] = 0   ;#3 RESET = 0 ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ;#3 S=1;#3 ALU_OUT=1;\n                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:40: Unsupported: Ignoring delay on this delayed statement.\n #3 OP = 17 ; #3 IR[27:25] = 0  ; #3 IR[11:7] = 0  ; #3 IR[6:5] = 1  ; #3 IR[4]=0   ; #3 IR[19:16] = 0   ; #3 IR[3:0] = 0  ; #3 IR[11:8] = 0  ; #3 IR[15:12] = 0  ; #3 RSLCT[19:16] = 0   ;#3 RESET = 0 ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ;#3 S=1;#3 ALU_OUT=1;\n                                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:40: Unsupported: Ignoring delay on this delayed statement.\n #3 OP = 17 ; #3 IR[27:25] = 0  ; #3 IR[11:7] = 0  ; #3 IR[6:5] = 1  ; #3 IR[4]=0   ; #3 IR[19:16] = 0   ; #3 IR[3:0] = 0  ; #3 IR[11:8] = 0  ; #3 IR[15:12] = 0  ; #3 RSLCT[19:16] = 0   ;#3 RESET = 0 ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ;#3 S=1;#3 ALU_OUT=1;\n                                                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:40: Unsupported: Ignoring delay on this delayed statement.\n #3 OP = 17 ; #3 IR[27:25] = 0  ; #3 IR[11:7] = 0  ; #3 IR[6:5] = 1  ; #3 IR[4]=0   ; #3 IR[19:16] = 0   ; #3 IR[3:0] = 0  ; #3 IR[11:8] = 0  ; #3 IR[15:12] = 0  ; #3 RSLCT[19:16] = 0   ;#3 RESET = 0 ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ;#3 S=1;#3 ALU_OUT=1;\n                                                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:40: Unsupported: Ignoring delay on this delayed statement.\n #3 OP = 17 ; #3 IR[27:25] = 0  ; #3 IR[11:7] = 0  ; #3 IR[6:5] = 1  ; #3 IR[4]=0   ; #3 IR[19:16] = 0   ; #3 IR[3:0] = 0  ; #3 IR[11:8] = 0  ; #3 IR[15:12] = 0  ; #3 RSLCT[19:16] = 0   ;#3 RESET = 0 ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ;#3 S=1;#3 ALU_OUT=1;\n                                                                                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:40: Unsupported: Ignoring delay on this delayed statement.\n #3 OP = 17 ; #3 IR[27:25] = 0  ; #3 IR[11:7] = 0  ; #3 IR[6:5] = 1  ; #3 IR[4]=0   ; #3 IR[19:16] = 0   ; #3 IR[3:0] = 0  ; #3 IR[11:8] = 0  ; #3 IR[15:12] = 0  ; #3 RSLCT[19:16] = 0   ;#3 RESET = 0 ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ;#3 S=1;#3 ALU_OUT=1;\n                                                                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:40: Unsupported: Ignoring delay on this delayed statement.\n #3 OP = 17 ; #3 IR[27:25] = 0  ; #3 IR[11:7] = 0  ; #3 IR[6:5] = 1  ; #3 IR[4]=0   ; #3 IR[19:16] = 0   ; #3 IR[3:0] = 0  ; #3 IR[11:8] = 0  ; #3 IR[15:12] = 0  ; #3 RSLCT[19:16] = 0   ;#3 RESET = 0 ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ;#3 S=1;#3 ALU_OUT=1;\n                                                                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:40: Unsupported: Ignoring delay on this delayed statement.\n #3 OP = 17 ; #3 IR[27:25] = 0  ; #3 IR[11:7] = 0  ; #3 IR[6:5] = 1  ; #3 IR[4]=0   ; #3 IR[19:16] = 0   ; #3 IR[3:0] = 0  ; #3 IR[11:8] = 0  ; #3 IR[15:12] = 0  ; #3 RSLCT[19:16] = 0   ;#3 RESET = 0 ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ;#3 S=1;#3 ALU_OUT=1;\n                                                                                                                                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:40: Unsupported: Ignoring delay on this delayed statement.\n #3 OP = 17 ; #3 IR[27:25] = 0  ; #3 IR[11:7] = 0  ; #3 IR[6:5] = 1  ; #3 IR[4]=0   ; #3 IR[19:16] = 0   ; #3 IR[3:0] = 0  ; #3 IR[11:8] = 0  ; #3 IR[15:12] = 0  ; #3 RSLCT[19:16] = 0   ;#3 RESET = 0 ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ;#3 S=1;#3 ALU_OUT=1;\n                                                                                                                                                                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:40: Unsupported: Ignoring delay on this delayed statement.\n #3 OP = 17 ; #3 IR[27:25] = 0  ; #3 IR[11:7] = 0  ; #3 IR[6:5] = 1  ; #3 IR[4]=0   ; #3 IR[19:16] = 0   ; #3 IR[3:0] = 0  ; #3 IR[11:8] = 0  ; #3 IR[15:12] = 0  ; #3 RSLCT[19:16] = 0   ;#3 RESET = 0 ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ;#3 S=1;#3 ALU_OUT=1;\n                                                                                                                                                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:40: Unsupported: Ignoring delay on this delayed statement.\n #3 OP = 17 ; #3 IR[27:25] = 0  ; #3 IR[11:7] = 0  ; #3 IR[6:5] = 1  ; #3 IR[4]=0   ; #3 IR[19:16] = 0   ; #3 IR[3:0] = 0  ; #3 IR[11:8] = 0  ; #3 IR[15:12] = 0  ; #3 RSLCT[19:16] = 0   ;#3 RESET = 0 ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ;#3 S=1;#3 ALU_OUT=1;\n                                                                                                                                                                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:40: Unsupported: Ignoring delay on this delayed statement.\n #3 OP = 17 ; #3 IR[27:25] = 0  ; #3 IR[11:7] = 0  ; #3 IR[6:5] = 1  ; #3 IR[4]=0   ; #3 IR[19:16] = 0   ; #3 IR[3:0] = 0  ; #3 IR[11:8] = 0  ; #3 IR[15:12] = 0  ; #3 RSLCT[19:16] = 0   ;#3 RESET = 0 ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ;#3 S=1;#3 ALU_OUT=1;\n                                                                                                                                                                                                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:40: Unsupported: Ignoring delay on this delayed statement.\n #3 OP = 17 ; #3 IR[27:25] = 0  ; #3 IR[11:7] = 0  ; #3 IR[6:5] = 1  ; #3 IR[4]=0   ; #3 IR[19:16] = 0   ; #3 IR[3:0] = 0  ; #3 IR[11:8] = 0  ; #3 IR[15:12] = 0  ; #3 RSLCT[19:16] = 0   ;#3 RESET = 0 ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ;#3 S=1;#3 ALU_OUT=1;\n                                                                                                                                                                                                                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:40: Unsupported: Ignoring delay on this delayed statement.\n #3 OP = 17 ; #3 IR[27:25] = 0  ; #3 IR[11:7] = 0  ; #3 IR[6:5] = 1  ; #3 IR[4]=0   ; #3 IR[19:16] = 0   ; #3 IR[3:0] = 0  ; #3 IR[11:8] = 0  ; #3 IR[15:12] = 0  ; #3 RSLCT[19:16] = 0   ;#3 RESET = 0 ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ;#3 S=1;#3 ALU_OUT=1;\n                                                                                                                                                                                                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:42: Unsupported: Ignoring delay on this delayed statement.\n #4 OP = 17; #4 IR[27:25] = 0  ; #4 IR[11:7] = 0  ; #4 IR[6:5] = 1  ; #4 IR[4]=0   ; #4 IR[19:16] = 0   ; #4 IR[3:0] = 0  ; #4 IR[11:8] = 0  ; #4 IR[15:12] = 0  ; #4 RSLCT[19:16] = 0   ;#4 RESET = 0 ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ;#4 S=1;#4 ALU_OUT=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:42: Unsupported: Ignoring delay on this delayed statement.\n #4 OP = 17; #4 IR[27:25] = 0  ; #4 IR[11:7] = 0  ; #4 IR[6:5] = 1  ; #4 IR[4]=0   ; #4 IR[19:16] = 0   ; #4 IR[3:0] = 0  ; #4 IR[11:8] = 0  ; #4 IR[15:12] = 0  ; #4 RSLCT[19:16] = 0   ;#4 RESET = 0 ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ;#4 S=1;#4 ALU_OUT=1;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:42: Unsupported: Ignoring delay on this delayed statement.\n #4 OP = 17; #4 IR[27:25] = 0  ; #4 IR[11:7] = 0  ; #4 IR[6:5] = 1  ; #4 IR[4]=0   ; #4 IR[19:16] = 0   ; #4 IR[3:0] = 0  ; #4 IR[11:8] = 0  ; #4 IR[15:12] = 0  ; #4 RSLCT[19:16] = 0   ;#4 RESET = 0 ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ;#4 S=1;#4 ALU_OUT=1;\n                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:42: Unsupported: Ignoring delay on this delayed statement.\n #4 OP = 17; #4 IR[27:25] = 0  ; #4 IR[11:7] = 0  ; #4 IR[6:5] = 1  ; #4 IR[4]=0   ; #4 IR[19:16] = 0   ; #4 IR[3:0] = 0  ; #4 IR[11:8] = 0  ; #4 IR[15:12] = 0  ; #4 RSLCT[19:16] = 0   ;#4 RESET = 0 ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ;#4 S=1;#4 ALU_OUT=1;\n                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:42: Unsupported: Ignoring delay on this delayed statement.\n #4 OP = 17; #4 IR[27:25] = 0  ; #4 IR[11:7] = 0  ; #4 IR[6:5] = 1  ; #4 IR[4]=0   ; #4 IR[19:16] = 0   ; #4 IR[3:0] = 0  ; #4 IR[11:8] = 0  ; #4 IR[15:12] = 0  ; #4 RSLCT[19:16] = 0   ;#4 RESET = 0 ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ;#4 S=1;#4 ALU_OUT=1;\n                                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:42: Unsupported: Ignoring delay on this delayed statement.\n #4 OP = 17; #4 IR[27:25] = 0  ; #4 IR[11:7] = 0  ; #4 IR[6:5] = 1  ; #4 IR[4]=0   ; #4 IR[19:16] = 0   ; #4 IR[3:0] = 0  ; #4 IR[11:8] = 0  ; #4 IR[15:12] = 0  ; #4 RSLCT[19:16] = 0   ;#4 RESET = 0 ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ;#4 S=1;#4 ALU_OUT=1;\n                                                                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:42: Unsupported: Ignoring delay on this delayed statement.\n #4 OP = 17; #4 IR[27:25] = 0  ; #4 IR[11:7] = 0  ; #4 IR[6:5] = 1  ; #4 IR[4]=0   ; #4 IR[19:16] = 0   ; #4 IR[3:0] = 0  ; #4 IR[11:8] = 0  ; #4 IR[15:12] = 0  ; #4 RSLCT[19:16] = 0   ;#4 RESET = 0 ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ;#4 S=1;#4 ALU_OUT=1;\n                                                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:42: Unsupported: Ignoring delay on this delayed statement.\n #4 OP = 17; #4 IR[27:25] = 0  ; #4 IR[11:7] = 0  ; #4 IR[6:5] = 1  ; #4 IR[4]=0   ; #4 IR[19:16] = 0   ; #4 IR[3:0] = 0  ; #4 IR[11:8] = 0  ; #4 IR[15:12] = 0  ; #4 RSLCT[19:16] = 0   ;#4 RESET = 0 ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ;#4 S=1;#4 ALU_OUT=1;\n                                                                                                                            ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:42: Unsupported: Ignoring delay on this delayed statement.\n #4 OP = 17; #4 IR[27:25] = 0  ; #4 IR[11:7] = 0  ; #4 IR[6:5] = 1  ; #4 IR[4]=0   ; #4 IR[19:16] = 0   ; #4 IR[3:0] = 0  ; #4 IR[11:8] = 0  ; #4 IR[15:12] = 0  ; #4 RSLCT[19:16] = 0   ;#4 RESET = 0 ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ;#4 S=1;#4 ALU_OUT=1;\n                                                                                                                                               ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:42: Unsupported: Ignoring delay on this delayed statement.\n #4 OP = 17; #4 IR[27:25] = 0  ; #4 IR[11:7] = 0  ; #4 IR[6:5] = 1  ; #4 IR[4]=0   ; #4 IR[19:16] = 0   ; #4 IR[3:0] = 0  ; #4 IR[11:8] = 0  ; #4 IR[15:12] = 0  ; #4 RSLCT[19:16] = 0   ;#4 RESET = 0 ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ;#4 S=1;#4 ALU_OUT=1;\n                                                                                                                                                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:42: Unsupported: Ignoring delay on this delayed statement.\n #4 OP = 17; #4 IR[27:25] = 0  ; #4 IR[11:7] = 0  ; #4 IR[6:5] = 1  ; #4 IR[4]=0   ; #4 IR[19:16] = 0   ; #4 IR[3:0] = 0  ; #4 IR[11:8] = 0  ; #4 IR[15:12] = 0  ; #4 RSLCT[19:16] = 0   ;#4 RESET = 0 ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ;#4 S=1;#4 ALU_OUT=1;\n                                                                                                                                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:42: Unsupported: Ignoring delay on this delayed statement.\n #4 OP = 17; #4 IR[27:25] = 0  ; #4 IR[11:7] = 0  ; #4 IR[6:5] = 1  ; #4 IR[4]=0   ; #4 IR[19:16] = 0   ; #4 IR[3:0] = 0  ; #4 IR[11:8] = 0  ; #4 IR[15:12] = 0  ; #4 RSLCT[19:16] = 0   ;#4 RESET = 0 ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ;#4 S=1;#4 ALU_OUT=1;\n                                                                                                                                                                                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:42: Unsupported: Ignoring delay on this delayed statement.\n #4 OP = 17; #4 IR[27:25] = 0  ; #4 IR[11:7] = 0  ; #4 IR[6:5] = 1  ; #4 IR[4]=0   ; #4 IR[19:16] = 0   ; #4 IR[3:0] = 0  ; #4 IR[11:8] = 0  ; #4 IR[15:12] = 0  ; #4 RSLCT[19:16] = 0   ;#4 RESET = 0 ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ;#4 S=1;#4 ALU_OUT=1;\n                                                                                                                                                                                                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:42: Unsupported: Ignoring delay on this delayed statement.\n #4 OP = 17; #4 IR[27:25] = 0  ; #4 IR[11:7] = 0  ; #4 IR[6:5] = 1  ; #4 IR[4]=0   ; #4 IR[19:16] = 0   ; #4 IR[3:0] = 0  ; #4 IR[11:8] = 0  ; #4 IR[15:12] = 0  ; #4 RSLCT[19:16] = 0   ;#4 RESET = 0 ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ;#4 S=1;#4 ALU_OUT=1;\n                                                                                                                                                                                                                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:42: Unsupported: Ignoring delay on this delayed statement.\n #4 OP = 17; #4 IR[27:25] = 0  ; #4 IR[11:7] = 0  ; #4 IR[6:5] = 1  ; #4 IR[4]=0   ; #4 IR[19:16] = 0   ; #4 IR[3:0] = 0  ; #4 IR[11:8] = 0  ; #4 IR[15:12] = 0  ; #4 RSLCT[19:16] = 0   ;#4 RESET = 0 ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ;#4 S=1;#4 ALU_OUT=1;\n                                                                                                                                                                                                                                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:42: Unsupported: Ignoring delay on this delayed statement.\n #4 OP = 17; #4 IR[27:25] = 0  ; #4 IR[11:7] = 0  ; #4 IR[6:5] = 1  ; #4 IR[4]=0   ; #4 IR[19:16] = 0   ; #4 IR[3:0] = 0  ; #4 IR[11:8] = 0  ; #4 IR[15:12] = 0  ; #4 RSLCT[19:16] = 0   ;#4 RESET = 0 ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ;#4 S=1;#4 ALU_OUT=1;\n                                                                                                                                                                                                                                                            ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:44: Unsupported: Ignoring delay on this delayed statement.\n #5 OP = 17 ; #5 IR[27:25] = 0  ; #5 IR[11:7] = 0  ; #5 IR[6:5] = 1  ; #5 IR[4]=0   ; #5 IR[19:16] = 0   ; #5 IR[3:0] = 0  ; #5 IR[11:8] = 0  ; #5 IR[15:12] = 0  ; #5 RSLCT[19:16] = 0   ;#5 RESET = 0 ; #5 LOADPC = 0 ; #5 LOAD = 1 ; #5 IR_CU = 1 ;#5 S=1;#5 ALU_OUT=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:44: Unsupported: Ignoring delay on this delayed statement.\n #5 OP = 17 ; #5 IR[27:25] = 0  ; #5 IR[11:7] = 0  ; #5 IR[6:5] = 1  ; #5 IR[4]=0   ; #5 IR[19:16] = 0   ; #5 IR[3:0] = 0  ; #5 IR[11:8] = 0  ; #5 IR[15:12] = 0  ; #5 RSLCT[19:16] = 0   ;#5 RESET = 0 ; #5 LOADPC = 0 ; #5 LOAD = 1 ; #5 IR_CU = 1 ;#5 S=1;#5 ALU_OUT=1;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:44: Unsupported: Ignoring delay on this delayed statement.\n #5 OP = 17 ; #5 IR[27:25] = 0  ; #5 IR[11:7] = 0  ; #5 IR[6:5] = 1  ; #5 IR[4]=0   ; #5 IR[19:16] = 0   ; #5 IR[3:0] = 0  ; #5 IR[11:8] = 0  ; #5 IR[15:12] = 0  ; #5 RSLCT[19:16] = 0   ;#5 RESET = 0 ; #5 LOADPC = 0 ; #5 LOAD = 1 ; #5 IR_CU = 1 ;#5 S=1;#5 ALU_OUT=1;\n                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:44: Unsupported: Ignoring delay on this delayed statement.\n #5 OP = 17 ; #5 IR[27:25] = 0  ; #5 IR[11:7] = 0  ; #5 IR[6:5] = 1  ; #5 IR[4]=0   ; #5 IR[19:16] = 0   ; #5 IR[3:0] = 0  ; #5 IR[11:8] = 0  ; #5 IR[15:12] = 0  ; #5 RSLCT[19:16] = 0   ;#5 RESET = 0 ; #5 LOADPC = 0 ; #5 LOAD = 1 ; #5 IR_CU = 1 ;#5 S=1;#5 ALU_OUT=1;\n                                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:44: Unsupported: Ignoring delay on this delayed statement.\n #5 OP = 17 ; #5 IR[27:25] = 0  ; #5 IR[11:7] = 0  ; #5 IR[6:5] = 1  ; #5 IR[4]=0   ; #5 IR[19:16] = 0   ; #5 IR[3:0] = 0  ; #5 IR[11:8] = 0  ; #5 IR[15:12] = 0  ; #5 RSLCT[19:16] = 0   ;#5 RESET = 0 ; #5 LOADPC = 0 ; #5 LOAD = 1 ; #5 IR_CU = 1 ;#5 S=1;#5 ALU_OUT=1;\n                                                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:44: Unsupported: Ignoring delay on this delayed statement.\n #5 OP = 17 ; #5 IR[27:25] = 0  ; #5 IR[11:7] = 0  ; #5 IR[6:5] = 1  ; #5 IR[4]=0   ; #5 IR[19:16] = 0   ; #5 IR[3:0] = 0  ; #5 IR[11:8] = 0  ; #5 IR[15:12] = 0  ; #5 RSLCT[19:16] = 0   ;#5 RESET = 0 ; #5 LOADPC = 0 ; #5 LOAD = 1 ; #5 IR_CU = 1 ;#5 S=1;#5 ALU_OUT=1;\n                                                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:44: Unsupported: Ignoring delay on this delayed statement.\n #5 OP = 17 ; #5 IR[27:25] = 0  ; #5 IR[11:7] = 0  ; #5 IR[6:5] = 1  ; #5 IR[4]=0   ; #5 IR[19:16] = 0   ; #5 IR[3:0] = 0  ; #5 IR[11:8] = 0  ; #5 IR[15:12] = 0  ; #5 RSLCT[19:16] = 0   ;#5 RESET = 0 ; #5 LOADPC = 0 ; #5 LOAD = 1 ; #5 IR_CU = 1 ;#5 S=1;#5 ALU_OUT=1;\n                                                                                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:44: Unsupported: Ignoring delay on this delayed statement.\n #5 OP = 17 ; #5 IR[27:25] = 0  ; #5 IR[11:7] = 0  ; #5 IR[6:5] = 1  ; #5 IR[4]=0   ; #5 IR[19:16] = 0   ; #5 IR[3:0] = 0  ; #5 IR[11:8] = 0  ; #5 IR[15:12] = 0  ; #5 RSLCT[19:16] = 0   ;#5 RESET = 0 ; #5 LOADPC = 0 ; #5 LOAD = 1 ; #5 IR_CU = 1 ;#5 S=1;#5 ALU_OUT=1;\n                                                                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:44: Unsupported: Ignoring delay on this delayed statement.\n #5 OP = 17 ; #5 IR[27:25] = 0  ; #5 IR[11:7] = 0  ; #5 IR[6:5] = 1  ; #5 IR[4]=0   ; #5 IR[19:16] = 0   ; #5 IR[3:0] = 0  ; #5 IR[11:8] = 0  ; #5 IR[15:12] = 0  ; #5 RSLCT[19:16] = 0   ;#5 RESET = 0 ; #5 LOADPC = 0 ; #5 LOAD = 1 ; #5 IR_CU = 1 ;#5 S=1;#5 ALU_OUT=1;\n                                                                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:44: Unsupported: Ignoring delay on this delayed statement.\n #5 OP = 17 ; #5 IR[27:25] = 0  ; #5 IR[11:7] = 0  ; #5 IR[6:5] = 1  ; #5 IR[4]=0   ; #5 IR[19:16] = 0   ; #5 IR[3:0] = 0  ; #5 IR[11:8] = 0  ; #5 IR[15:12] = 0  ; #5 RSLCT[19:16] = 0   ;#5 RESET = 0 ; #5 LOADPC = 0 ; #5 LOAD = 1 ; #5 IR_CU = 1 ;#5 S=1;#5 ALU_OUT=1;\n                                                                                                                                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:44: Unsupported: Ignoring delay on this delayed statement.\n #5 OP = 17 ; #5 IR[27:25] = 0  ; #5 IR[11:7] = 0  ; #5 IR[6:5] = 1  ; #5 IR[4]=0   ; #5 IR[19:16] = 0   ; #5 IR[3:0] = 0  ; #5 IR[11:8] = 0  ; #5 IR[15:12] = 0  ; #5 RSLCT[19:16] = 0   ;#5 RESET = 0 ; #5 LOADPC = 0 ; #5 LOAD = 1 ; #5 IR_CU = 1 ;#5 S=1;#5 ALU_OUT=1;\n                                                                                                                                                                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:44: Unsupported: Ignoring delay on this delayed statement.\n #5 OP = 17 ; #5 IR[27:25] = 0  ; #5 IR[11:7] = 0  ; #5 IR[6:5] = 1  ; #5 IR[4]=0   ; #5 IR[19:16] = 0   ; #5 IR[3:0] = 0  ; #5 IR[11:8] = 0  ; #5 IR[15:12] = 0  ; #5 RSLCT[19:16] = 0   ;#5 RESET = 0 ; #5 LOADPC = 0 ; #5 LOAD = 1 ; #5 IR_CU = 1 ;#5 S=1;#5 ALU_OUT=1;\n                                                                                                                                                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:44: Unsupported: Ignoring delay on this delayed statement.\n #5 OP = 17 ; #5 IR[27:25] = 0  ; #5 IR[11:7] = 0  ; #5 IR[6:5] = 1  ; #5 IR[4]=0   ; #5 IR[19:16] = 0   ; #5 IR[3:0] = 0  ; #5 IR[11:8] = 0  ; #5 IR[15:12] = 0  ; #5 RSLCT[19:16] = 0   ;#5 RESET = 0 ; #5 LOADPC = 0 ; #5 LOAD = 1 ; #5 IR_CU = 1 ;#5 S=1;#5 ALU_OUT=1;\n                                                                                                                                                                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:44: Unsupported: Ignoring delay on this delayed statement.\n #5 OP = 17 ; #5 IR[27:25] = 0  ; #5 IR[11:7] = 0  ; #5 IR[6:5] = 1  ; #5 IR[4]=0   ; #5 IR[19:16] = 0   ; #5 IR[3:0] = 0  ; #5 IR[11:8] = 0  ; #5 IR[15:12] = 0  ; #5 RSLCT[19:16] = 0   ;#5 RESET = 0 ; #5 LOADPC = 0 ; #5 LOAD = 1 ; #5 IR_CU = 1 ;#5 S=1;#5 ALU_OUT=1;\n                                                                                                                                                                                                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:44: Unsupported: Ignoring delay on this delayed statement.\n #5 OP = 17 ; #5 IR[27:25] = 0  ; #5 IR[11:7] = 0  ; #5 IR[6:5] = 1  ; #5 IR[4]=0   ; #5 IR[19:16] = 0   ; #5 IR[3:0] = 0  ; #5 IR[11:8] = 0  ; #5 IR[15:12] = 0  ; #5 RSLCT[19:16] = 0   ;#5 RESET = 0 ; #5 LOADPC = 0 ; #5 LOAD = 1 ; #5 IR_CU = 1 ;#5 S=1;#5 ALU_OUT=1;\n                                                                                                                                                                                                                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:44: Unsupported: Ignoring delay on this delayed statement.\n #5 OP = 17 ; #5 IR[27:25] = 0  ; #5 IR[11:7] = 0  ; #5 IR[6:5] = 1  ; #5 IR[4]=0   ; #5 IR[19:16] = 0   ; #5 IR[3:0] = 0  ; #5 IR[11:8] = 0  ; #5 IR[15:12] = 0  ; #5 RSLCT[19:16] = 0   ;#5 RESET = 0 ; #5 LOADPC = 0 ; #5 LOAD = 1 ; #5 IR_CU = 1 ;#5 S=1;#5 ALU_OUT=1;\n                                                                                                                                                                                                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:46: Unsupported: Ignoring delay on this delayed statement.\n #6 OP = 0  ; #6 IR[27:25] = 0  ; #6 IR[11:7] = 0  ; #6 IR[6:5] = 0  ; #6 IR[4]=1   ; #6 IR[19:16] = 0   ; #6 IR[3:0] = 0  ; #6 IR[11:8] = 0  ; #6 IR[15:12] = 0  ; #6 RSLCT[19:16] = 0   ;#6 RESET = 0 ; #6 LOADPC = 0 ; #6 LOAD = 0 ; #6 IR_CU = 1 ;#6 S=0;#6 ALU_OUT=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:46: Unsupported: Ignoring delay on this delayed statement.\n #6 OP = 0  ; #6 IR[27:25] = 0  ; #6 IR[11:7] = 0  ; #6 IR[6:5] = 0  ; #6 IR[4]=1   ; #6 IR[19:16] = 0   ; #6 IR[3:0] = 0  ; #6 IR[11:8] = 0  ; #6 IR[15:12] = 0  ; #6 RSLCT[19:16] = 0   ;#6 RESET = 0 ; #6 LOADPC = 0 ; #6 LOAD = 0 ; #6 IR_CU = 1 ;#6 S=0;#6 ALU_OUT=0;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:46: Unsupported: Ignoring delay on this delayed statement.\n #6 OP = 0  ; #6 IR[27:25] = 0  ; #6 IR[11:7] = 0  ; #6 IR[6:5] = 0  ; #6 IR[4]=1   ; #6 IR[19:16] = 0   ; #6 IR[3:0] = 0  ; #6 IR[11:8] = 0  ; #6 IR[15:12] = 0  ; #6 RSLCT[19:16] = 0   ;#6 RESET = 0 ; #6 LOADPC = 0 ; #6 LOAD = 0 ; #6 IR_CU = 1 ;#6 S=0;#6 ALU_OUT=0;\n                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:46: Unsupported: Ignoring delay on this delayed statement.\n #6 OP = 0  ; #6 IR[27:25] = 0  ; #6 IR[11:7] = 0  ; #6 IR[6:5] = 0  ; #6 IR[4]=1   ; #6 IR[19:16] = 0   ; #6 IR[3:0] = 0  ; #6 IR[11:8] = 0  ; #6 IR[15:12] = 0  ; #6 RSLCT[19:16] = 0   ;#6 RESET = 0 ; #6 LOADPC = 0 ; #6 LOAD = 0 ; #6 IR_CU = 1 ;#6 S=0;#6 ALU_OUT=0;\n                                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:46: Unsupported: Ignoring delay on this delayed statement.\n #6 OP = 0  ; #6 IR[27:25] = 0  ; #6 IR[11:7] = 0  ; #6 IR[6:5] = 0  ; #6 IR[4]=1   ; #6 IR[19:16] = 0   ; #6 IR[3:0] = 0  ; #6 IR[11:8] = 0  ; #6 IR[15:12] = 0  ; #6 RSLCT[19:16] = 0   ;#6 RESET = 0 ; #6 LOADPC = 0 ; #6 LOAD = 0 ; #6 IR_CU = 1 ;#6 S=0;#6 ALU_OUT=0;\n                                                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:46: Unsupported: Ignoring delay on this delayed statement.\n #6 OP = 0  ; #6 IR[27:25] = 0  ; #6 IR[11:7] = 0  ; #6 IR[6:5] = 0  ; #6 IR[4]=1   ; #6 IR[19:16] = 0   ; #6 IR[3:0] = 0  ; #6 IR[11:8] = 0  ; #6 IR[15:12] = 0  ; #6 RSLCT[19:16] = 0   ;#6 RESET = 0 ; #6 LOADPC = 0 ; #6 LOAD = 0 ; #6 IR_CU = 1 ;#6 S=0;#6 ALU_OUT=0;\n                                                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:46: Unsupported: Ignoring delay on this delayed statement.\n #6 OP = 0  ; #6 IR[27:25] = 0  ; #6 IR[11:7] = 0  ; #6 IR[6:5] = 0  ; #6 IR[4]=1   ; #6 IR[19:16] = 0   ; #6 IR[3:0] = 0  ; #6 IR[11:8] = 0  ; #6 IR[15:12] = 0  ; #6 RSLCT[19:16] = 0   ;#6 RESET = 0 ; #6 LOADPC = 0 ; #6 LOAD = 0 ; #6 IR_CU = 1 ;#6 S=0;#6 ALU_OUT=0;\n                                                                                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:46: Unsupported: Ignoring delay on this delayed statement.\n #6 OP = 0  ; #6 IR[27:25] = 0  ; #6 IR[11:7] = 0  ; #6 IR[6:5] = 0  ; #6 IR[4]=1   ; #6 IR[19:16] = 0   ; #6 IR[3:0] = 0  ; #6 IR[11:8] = 0  ; #6 IR[15:12] = 0  ; #6 RSLCT[19:16] = 0   ;#6 RESET = 0 ; #6 LOADPC = 0 ; #6 LOAD = 0 ; #6 IR_CU = 1 ;#6 S=0;#6 ALU_OUT=0;\n                                                                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:46: Unsupported: Ignoring delay on this delayed statement.\n #6 OP = 0  ; #6 IR[27:25] = 0  ; #6 IR[11:7] = 0  ; #6 IR[6:5] = 0  ; #6 IR[4]=1   ; #6 IR[19:16] = 0   ; #6 IR[3:0] = 0  ; #6 IR[11:8] = 0  ; #6 IR[15:12] = 0  ; #6 RSLCT[19:16] = 0   ;#6 RESET = 0 ; #6 LOADPC = 0 ; #6 LOAD = 0 ; #6 IR_CU = 1 ;#6 S=0;#6 ALU_OUT=0;\n                                                                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:46: Unsupported: Ignoring delay on this delayed statement.\n #6 OP = 0  ; #6 IR[27:25] = 0  ; #6 IR[11:7] = 0  ; #6 IR[6:5] = 0  ; #6 IR[4]=1   ; #6 IR[19:16] = 0   ; #6 IR[3:0] = 0  ; #6 IR[11:8] = 0  ; #6 IR[15:12] = 0  ; #6 RSLCT[19:16] = 0   ;#6 RESET = 0 ; #6 LOADPC = 0 ; #6 LOAD = 0 ; #6 IR_CU = 1 ;#6 S=0;#6 ALU_OUT=0;\n                                                                                                                                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:46: Unsupported: Ignoring delay on this delayed statement.\n #6 OP = 0  ; #6 IR[27:25] = 0  ; #6 IR[11:7] = 0  ; #6 IR[6:5] = 0  ; #6 IR[4]=1   ; #6 IR[19:16] = 0   ; #6 IR[3:0] = 0  ; #6 IR[11:8] = 0  ; #6 IR[15:12] = 0  ; #6 RSLCT[19:16] = 0   ;#6 RESET = 0 ; #6 LOADPC = 0 ; #6 LOAD = 0 ; #6 IR_CU = 1 ;#6 S=0;#6 ALU_OUT=0;\n                                                                                                                                                                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:46: Unsupported: Ignoring delay on this delayed statement.\n #6 OP = 0  ; #6 IR[27:25] = 0  ; #6 IR[11:7] = 0  ; #6 IR[6:5] = 0  ; #6 IR[4]=1   ; #6 IR[19:16] = 0   ; #6 IR[3:0] = 0  ; #6 IR[11:8] = 0  ; #6 IR[15:12] = 0  ; #6 RSLCT[19:16] = 0   ;#6 RESET = 0 ; #6 LOADPC = 0 ; #6 LOAD = 0 ; #6 IR_CU = 1 ;#6 S=0;#6 ALU_OUT=0;\n                                                                                                                                                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:46: Unsupported: Ignoring delay on this delayed statement.\n #6 OP = 0  ; #6 IR[27:25] = 0  ; #6 IR[11:7] = 0  ; #6 IR[6:5] = 0  ; #6 IR[4]=1   ; #6 IR[19:16] = 0   ; #6 IR[3:0] = 0  ; #6 IR[11:8] = 0  ; #6 IR[15:12] = 0  ; #6 RSLCT[19:16] = 0   ;#6 RESET = 0 ; #6 LOADPC = 0 ; #6 LOAD = 0 ; #6 IR_CU = 1 ;#6 S=0;#6 ALU_OUT=0;\n                                                                                                                                                                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:46: Unsupported: Ignoring delay on this delayed statement.\n #6 OP = 0  ; #6 IR[27:25] = 0  ; #6 IR[11:7] = 0  ; #6 IR[6:5] = 0  ; #6 IR[4]=1   ; #6 IR[19:16] = 0   ; #6 IR[3:0] = 0  ; #6 IR[11:8] = 0  ; #6 IR[15:12] = 0  ; #6 RSLCT[19:16] = 0   ;#6 RESET = 0 ; #6 LOADPC = 0 ; #6 LOAD = 0 ; #6 IR_CU = 1 ;#6 S=0;#6 ALU_OUT=0;\n                                                                                                                                                                                                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:46: Unsupported: Ignoring delay on this delayed statement.\n #6 OP = 0  ; #6 IR[27:25] = 0  ; #6 IR[11:7] = 0  ; #6 IR[6:5] = 0  ; #6 IR[4]=1   ; #6 IR[19:16] = 0   ; #6 IR[3:0] = 0  ; #6 IR[11:8] = 0  ; #6 IR[15:12] = 0  ; #6 RSLCT[19:16] = 0   ;#6 RESET = 0 ; #6 LOADPC = 0 ; #6 LOAD = 0 ; #6 IR_CU = 1 ;#6 S=0;#6 ALU_OUT=0;\n                                                                                                                                                                                                                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:46: Unsupported: Ignoring delay on this delayed statement.\n #6 OP = 0  ; #6 IR[27:25] = 0  ; #6 IR[11:7] = 0  ; #6 IR[6:5] = 0  ; #6 IR[4]=1   ; #6 IR[19:16] = 0   ; #6 IR[3:0] = 0  ; #6 IR[11:8] = 0  ; #6 IR[15:12] = 0  ; #6 RSLCT[19:16] = 0   ;#6 RESET = 0 ; #6 LOADPC = 0 ; #6 LOAD = 0 ; #6 IR_CU = 1 ;#6 S=0;#6 ALU_OUT=0;\n                                                                                                                                                                                                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:48: Unsupported: Ignoring delay on this delayed statement.\n #7 OP = 0  ; #7 IR[27:25] = 0  ; #7 IR[11:7] = 0  ; #7 IR[6:5] = 0  ; #7 IR[4]=1   ; #7 IR[19:16] = 0   ; #7 IR[3:0] = 0  ; #7 IR[11:8] = 0  ; #7 IR[15:12] = 0  ; #7 RSLCT[19:16] = 0   ;#7 RESET = 0 ; #7 LOADPC = 0 ; #7 LOAD = 0 ; #7 IR_CU = 1 ;#7 S=0;#7 ALU_OUT=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:48: Unsupported: Ignoring delay on this delayed statement.\n #7 OP = 0  ; #7 IR[27:25] = 0  ; #7 IR[11:7] = 0  ; #7 IR[6:5] = 0  ; #7 IR[4]=1   ; #7 IR[19:16] = 0   ; #7 IR[3:0] = 0  ; #7 IR[11:8] = 0  ; #7 IR[15:12] = 0  ; #7 RSLCT[19:16] = 0   ;#7 RESET = 0 ; #7 LOADPC = 0 ; #7 LOAD = 0 ; #7 IR_CU = 1 ;#7 S=0;#7 ALU_OUT=0;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:48: Unsupported: Ignoring delay on this delayed statement.\n #7 OP = 0  ; #7 IR[27:25] = 0  ; #7 IR[11:7] = 0  ; #7 IR[6:5] = 0  ; #7 IR[4]=1   ; #7 IR[19:16] = 0   ; #7 IR[3:0] = 0  ; #7 IR[11:8] = 0  ; #7 IR[15:12] = 0  ; #7 RSLCT[19:16] = 0   ;#7 RESET = 0 ; #7 LOADPC = 0 ; #7 LOAD = 0 ; #7 IR_CU = 1 ;#7 S=0;#7 ALU_OUT=0;\n                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:48: Unsupported: Ignoring delay on this delayed statement.\n #7 OP = 0  ; #7 IR[27:25] = 0  ; #7 IR[11:7] = 0  ; #7 IR[6:5] = 0  ; #7 IR[4]=1   ; #7 IR[19:16] = 0   ; #7 IR[3:0] = 0  ; #7 IR[11:8] = 0  ; #7 IR[15:12] = 0  ; #7 RSLCT[19:16] = 0   ;#7 RESET = 0 ; #7 LOADPC = 0 ; #7 LOAD = 0 ; #7 IR_CU = 1 ;#7 S=0;#7 ALU_OUT=0;\n                                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:48: Unsupported: Ignoring delay on this delayed statement.\n #7 OP = 0  ; #7 IR[27:25] = 0  ; #7 IR[11:7] = 0  ; #7 IR[6:5] = 0  ; #7 IR[4]=1   ; #7 IR[19:16] = 0   ; #7 IR[3:0] = 0  ; #7 IR[11:8] = 0  ; #7 IR[15:12] = 0  ; #7 RSLCT[19:16] = 0   ;#7 RESET = 0 ; #7 LOADPC = 0 ; #7 LOAD = 0 ; #7 IR_CU = 1 ;#7 S=0;#7 ALU_OUT=0;\n                                                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:48: Unsupported: Ignoring delay on this delayed statement.\n #7 OP = 0  ; #7 IR[27:25] = 0  ; #7 IR[11:7] = 0  ; #7 IR[6:5] = 0  ; #7 IR[4]=1   ; #7 IR[19:16] = 0   ; #7 IR[3:0] = 0  ; #7 IR[11:8] = 0  ; #7 IR[15:12] = 0  ; #7 RSLCT[19:16] = 0   ;#7 RESET = 0 ; #7 LOADPC = 0 ; #7 LOAD = 0 ; #7 IR_CU = 1 ;#7 S=0;#7 ALU_OUT=0;\n                                                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:48: Unsupported: Ignoring delay on this delayed statement.\n #7 OP = 0  ; #7 IR[27:25] = 0  ; #7 IR[11:7] = 0  ; #7 IR[6:5] = 0  ; #7 IR[4]=1   ; #7 IR[19:16] = 0   ; #7 IR[3:0] = 0  ; #7 IR[11:8] = 0  ; #7 IR[15:12] = 0  ; #7 RSLCT[19:16] = 0   ;#7 RESET = 0 ; #7 LOADPC = 0 ; #7 LOAD = 0 ; #7 IR_CU = 1 ;#7 S=0;#7 ALU_OUT=0;\n                                                                                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:48: Unsupported: Ignoring delay on this delayed statement.\n #7 OP = 0  ; #7 IR[27:25] = 0  ; #7 IR[11:7] = 0  ; #7 IR[6:5] = 0  ; #7 IR[4]=1   ; #7 IR[19:16] = 0   ; #7 IR[3:0] = 0  ; #7 IR[11:8] = 0  ; #7 IR[15:12] = 0  ; #7 RSLCT[19:16] = 0   ;#7 RESET = 0 ; #7 LOADPC = 0 ; #7 LOAD = 0 ; #7 IR_CU = 1 ;#7 S=0;#7 ALU_OUT=0;\n                                                                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:48: Unsupported: Ignoring delay on this delayed statement.\n #7 OP = 0  ; #7 IR[27:25] = 0  ; #7 IR[11:7] = 0  ; #7 IR[6:5] = 0  ; #7 IR[4]=1   ; #7 IR[19:16] = 0   ; #7 IR[3:0] = 0  ; #7 IR[11:8] = 0  ; #7 IR[15:12] = 0  ; #7 RSLCT[19:16] = 0   ;#7 RESET = 0 ; #7 LOADPC = 0 ; #7 LOAD = 0 ; #7 IR_CU = 1 ;#7 S=0;#7 ALU_OUT=0;\n                                                                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:48: Unsupported: Ignoring delay on this delayed statement.\n #7 OP = 0  ; #7 IR[27:25] = 0  ; #7 IR[11:7] = 0  ; #7 IR[6:5] = 0  ; #7 IR[4]=1   ; #7 IR[19:16] = 0   ; #7 IR[3:0] = 0  ; #7 IR[11:8] = 0  ; #7 IR[15:12] = 0  ; #7 RSLCT[19:16] = 0   ;#7 RESET = 0 ; #7 LOADPC = 0 ; #7 LOAD = 0 ; #7 IR_CU = 1 ;#7 S=0;#7 ALU_OUT=0;\n                                                                                                                                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:48: Unsupported: Ignoring delay on this delayed statement.\n #7 OP = 0  ; #7 IR[27:25] = 0  ; #7 IR[11:7] = 0  ; #7 IR[6:5] = 0  ; #7 IR[4]=1   ; #7 IR[19:16] = 0   ; #7 IR[3:0] = 0  ; #7 IR[11:8] = 0  ; #7 IR[15:12] = 0  ; #7 RSLCT[19:16] = 0   ;#7 RESET = 0 ; #7 LOADPC = 0 ; #7 LOAD = 0 ; #7 IR_CU = 1 ;#7 S=0;#7 ALU_OUT=0;\n                                                                                                                                                                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:48: Unsupported: Ignoring delay on this delayed statement.\n #7 OP = 0  ; #7 IR[27:25] = 0  ; #7 IR[11:7] = 0  ; #7 IR[6:5] = 0  ; #7 IR[4]=1   ; #7 IR[19:16] = 0   ; #7 IR[3:0] = 0  ; #7 IR[11:8] = 0  ; #7 IR[15:12] = 0  ; #7 RSLCT[19:16] = 0   ;#7 RESET = 0 ; #7 LOADPC = 0 ; #7 LOAD = 0 ; #7 IR_CU = 1 ;#7 S=0;#7 ALU_OUT=0;\n                                                                                                                                                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:48: Unsupported: Ignoring delay on this delayed statement.\n #7 OP = 0  ; #7 IR[27:25] = 0  ; #7 IR[11:7] = 0  ; #7 IR[6:5] = 0  ; #7 IR[4]=1   ; #7 IR[19:16] = 0   ; #7 IR[3:0] = 0  ; #7 IR[11:8] = 0  ; #7 IR[15:12] = 0  ; #7 RSLCT[19:16] = 0   ;#7 RESET = 0 ; #7 LOADPC = 0 ; #7 LOAD = 0 ; #7 IR_CU = 1 ;#7 S=0;#7 ALU_OUT=0;\n                                                                                                                                                                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:48: Unsupported: Ignoring delay on this delayed statement.\n #7 OP = 0  ; #7 IR[27:25] = 0  ; #7 IR[11:7] = 0  ; #7 IR[6:5] = 0  ; #7 IR[4]=1   ; #7 IR[19:16] = 0   ; #7 IR[3:0] = 0  ; #7 IR[11:8] = 0  ; #7 IR[15:12] = 0  ; #7 RSLCT[19:16] = 0   ;#7 RESET = 0 ; #7 LOADPC = 0 ; #7 LOAD = 0 ; #7 IR_CU = 1 ;#7 S=0;#7 ALU_OUT=0;\n                                                                                                                                                                                                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:48: Unsupported: Ignoring delay on this delayed statement.\n #7 OP = 0  ; #7 IR[27:25] = 0  ; #7 IR[11:7] = 0  ; #7 IR[6:5] = 0  ; #7 IR[4]=1   ; #7 IR[19:16] = 0   ; #7 IR[3:0] = 0  ; #7 IR[11:8] = 0  ; #7 IR[15:12] = 0  ; #7 RSLCT[19:16] = 0   ;#7 RESET = 0 ; #7 LOADPC = 0 ; #7 LOAD = 0 ; #7 IR_CU = 1 ;#7 S=0;#7 ALU_OUT=0;\n                                                                                                                                                                                                                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:48: Unsupported: Ignoring delay on this delayed statement.\n #7 OP = 0  ; #7 IR[27:25] = 0  ; #7 IR[11:7] = 0  ; #7 IR[6:5] = 0  ; #7 IR[4]=1   ; #7 IR[19:16] = 0   ; #7 IR[3:0] = 0  ; #7 IR[11:8] = 0  ; #7 IR[15:12] = 0  ; #7 RSLCT[19:16] = 0   ;#7 RESET = 0 ; #7 LOADPC = 0 ; #7 LOAD = 0 ; #7 IR_CU = 1 ;#7 S=0;#7 ALU_OUT=0;\n                                                                                                                                                                                                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:50: Unsupported: Ignoring delay on this delayed statement.\n #8 OP = 16; #8 IR[27:25] = 0  ; #8 IR[11:7] = 1  ; #8 IR[6:5] = 0  ; #8 IR[4]=0   ; #8 IR[19:16] = 0   ; #8 IR[3:0] = 0  ; #8 IR[11:8] = 0  ; #8 IR[15:12] = 0  ; #8 RSLCT[19:16] = 0   ;#8 RESET = 0 ; #8 LOADPC = 0 ; #8 LOAD = 0 ; #8 IR_CU = 1 ;#8 S=1;#8 ALU_OUT=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:50: Unsupported: Ignoring delay on this delayed statement.\n #8 OP = 16; #8 IR[27:25] = 0  ; #8 IR[11:7] = 1  ; #8 IR[6:5] = 0  ; #8 IR[4]=0   ; #8 IR[19:16] = 0   ; #8 IR[3:0] = 0  ; #8 IR[11:8] = 0  ; #8 IR[15:12] = 0  ; #8 RSLCT[19:16] = 0   ;#8 RESET = 0 ; #8 LOADPC = 0 ; #8 LOAD = 0 ; #8 IR_CU = 1 ;#8 S=1;#8 ALU_OUT=1;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:50: Unsupported: Ignoring delay on this delayed statement.\n #8 OP = 16; #8 IR[27:25] = 0  ; #8 IR[11:7] = 1  ; #8 IR[6:5] = 0  ; #8 IR[4]=0   ; #8 IR[19:16] = 0   ; #8 IR[3:0] = 0  ; #8 IR[11:8] = 0  ; #8 IR[15:12] = 0  ; #8 RSLCT[19:16] = 0   ;#8 RESET = 0 ; #8 LOADPC = 0 ; #8 LOAD = 0 ; #8 IR_CU = 1 ;#8 S=1;#8 ALU_OUT=1;\n                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:50: Unsupported: Ignoring delay on this delayed statement.\n #8 OP = 16; #8 IR[27:25] = 0  ; #8 IR[11:7] = 1  ; #8 IR[6:5] = 0  ; #8 IR[4]=0   ; #8 IR[19:16] = 0   ; #8 IR[3:0] = 0  ; #8 IR[11:8] = 0  ; #8 IR[15:12] = 0  ; #8 RSLCT[19:16] = 0   ;#8 RESET = 0 ; #8 LOADPC = 0 ; #8 LOAD = 0 ; #8 IR_CU = 1 ;#8 S=1;#8 ALU_OUT=1;\n                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:50: Unsupported: Ignoring delay on this delayed statement.\n #8 OP = 16; #8 IR[27:25] = 0  ; #8 IR[11:7] = 1  ; #8 IR[6:5] = 0  ; #8 IR[4]=0   ; #8 IR[19:16] = 0   ; #8 IR[3:0] = 0  ; #8 IR[11:8] = 0  ; #8 IR[15:12] = 0  ; #8 RSLCT[19:16] = 0   ;#8 RESET = 0 ; #8 LOADPC = 0 ; #8 LOAD = 0 ; #8 IR_CU = 1 ;#8 S=1;#8 ALU_OUT=1;\n                                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:50: Unsupported: Ignoring delay on this delayed statement.\n #8 OP = 16; #8 IR[27:25] = 0  ; #8 IR[11:7] = 1  ; #8 IR[6:5] = 0  ; #8 IR[4]=0   ; #8 IR[19:16] = 0   ; #8 IR[3:0] = 0  ; #8 IR[11:8] = 0  ; #8 IR[15:12] = 0  ; #8 RSLCT[19:16] = 0   ;#8 RESET = 0 ; #8 LOADPC = 0 ; #8 LOAD = 0 ; #8 IR_CU = 1 ;#8 S=1;#8 ALU_OUT=1;\n                                                                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:50: Unsupported: Ignoring delay on this delayed statement.\n #8 OP = 16; #8 IR[27:25] = 0  ; #8 IR[11:7] = 1  ; #8 IR[6:5] = 0  ; #8 IR[4]=0   ; #8 IR[19:16] = 0   ; #8 IR[3:0] = 0  ; #8 IR[11:8] = 0  ; #8 IR[15:12] = 0  ; #8 RSLCT[19:16] = 0   ;#8 RESET = 0 ; #8 LOADPC = 0 ; #8 LOAD = 0 ; #8 IR_CU = 1 ;#8 S=1;#8 ALU_OUT=1;\n                                                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:50: Unsupported: Ignoring delay on this delayed statement.\n #8 OP = 16; #8 IR[27:25] = 0  ; #8 IR[11:7] = 1  ; #8 IR[6:5] = 0  ; #8 IR[4]=0   ; #8 IR[19:16] = 0   ; #8 IR[3:0] = 0  ; #8 IR[11:8] = 0  ; #8 IR[15:12] = 0  ; #8 RSLCT[19:16] = 0   ;#8 RESET = 0 ; #8 LOADPC = 0 ; #8 LOAD = 0 ; #8 IR_CU = 1 ;#8 S=1;#8 ALU_OUT=1;\n                                                                                                                            ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:50: Unsupported: Ignoring delay on this delayed statement.\n #8 OP = 16; #8 IR[27:25] = 0  ; #8 IR[11:7] = 1  ; #8 IR[6:5] = 0  ; #8 IR[4]=0   ; #8 IR[19:16] = 0   ; #8 IR[3:0] = 0  ; #8 IR[11:8] = 0  ; #8 IR[15:12] = 0  ; #8 RSLCT[19:16] = 0   ;#8 RESET = 0 ; #8 LOADPC = 0 ; #8 LOAD = 0 ; #8 IR_CU = 1 ;#8 S=1;#8 ALU_OUT=1;\n                                                                                                                                               ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:50: Unsupported: Ignoring delay on this delayed statement.\n #8 OP = 16; #8 IR[27:25] = 0  ; #8 IR[11:7] = 1  ; #8 IR[6:5] = 0  ; #8 IR[4]=0   ; #8 IR[19:16] = 0   ; #8 IR[3:0] = 0  ; #8 IR[11:8] = 0  ; #8 IR[15:12] = 0  ; #8 RSLCT[19:16] = 0   ;#8 RESET = 0 ; #8 LOADPC = 0 ; #8 LOAD = 0 ; #8 IR_CU = 1 ;#8 S=1;#8 ALU_OUT=1;\n                                                                                                                                                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:50: Unsupported: Ignoring delay on this delayed statement.\n #8 OP = 16; #8 IR[27:25] = 0  ; #8 IR[11:7] = 1  ; #8 IR[6:5] = 0  ; #8 IR[4]=0   ; #8 IR[19:16] = 0   ; #8 IR[3:0] = 0  ; #8 IR[11:8] = 0  ; #8 IR[15:12] = 0  ; #8 RSLCT[19:16] = 0   ;#8 RESET = 0 ; #8 LOADPC = 0 ; #8 LOAD = 0 ; #8 IR_CU = 1 ;#8 S=1;#8 ALU_OUT=1;\n                                                                                                                                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:50: Unsupported: Ignoring delay on this delayed statement.\n #8 OP = 16; #8 IR[27:25] = 0  ; #8 IR[11:7] = 1  ; #8 IR[6:5] = 0  ; #8 IR[4]=0   ; #8 IR[19:16] = 0   ; #8 IR[3:0] = 0  ; #8 IR[11:8] = 0  ; #8 IR[15:12] = 0  ; #8 RSLCT[19:16] = 0   ;#8 RESET = 0 ; #8 LOADPC = 0 ; #8 LOAD = 0 ; #8 IR_CU = 1 ;#8 S=1;#8 ALU_OUT=1;\n                                                                                                                                                                                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:50: Unsupported: Ignoring delay on this delayed statement.\n #8 OP = 16; #8 IR[27:25] = 0  ; #8 IR[11:7] = 1  ; #8 IR[6:5] = 0  ; #8 IR[4]=0   ; #8 IR[19:16] = 0   ; #8 IR[3:0] = 0  ; #8 IR[11:8] = 0  ; #8 IR[15:12] = 0  ; #8 RSLCT[19:16] = 0   ;#8 RESET = 0 ; #8 LOADPC = 0 ; #8 LOAD = 0 ; #8 IR_CU = 1 ;#8 S=1;#8 ALU_OUT=1;\n                                                                                                                                                                                                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:50: Unsupported: Ignoring delay on this delayed statement.\n #8 OP = 16; #8 IR[27:25] = 0  ; #8 IR[11:7] = 1  ; #8 IR[6:5] = 0  ; #8 IR[4]=0   ; #8 IR[19:16] = 0   ; #8 IR[3:0] = 0  ; #8 IR[11:8] = 0  ; #8 IR[15:12] = 0  ; #8 RSLCT[19:16] = 0   ;#8 RESET = 0 ; #8 LOADPC = 0 ; #8 LOAD = 0 ; #8 IR_CU = 1 ;#8 S=1;#8 ALU_OUT=1;\n                                                                                                                                                                                                                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:50: Unsupported: Ignoring delay on this delayed statement.\n #8 OP = 16; #8 IR[27:25] = 0  ; #8 IR[11:7] = 1  ; #8 IR[6:5] = 0  ; #8 IR[4]=0   ; #8 IR[19:16] = 0   ; #8 IR[3:0] = 0  ; #8 IR[11:8] = 0  ; #8 IR[15:12] = 0  ; #8 RSLCT[19:16] = 0   ;#8 RESET = 0 ; #8 LOADPC = 0 ; #8 LOAD = 0 ; #8 IR_CU = 1 ;#8 S=1;#8 ALU_OUT=1;\n                                                                                                                                                                                                                                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:50: Unsupported: Ignoring delay on this delayed statement.\n #8 OP = 16; #8 IR[27:25] = 0  ; #8 IR[11:7] = 1  ; #8 IR[6:5] = 0  ; #8 IR[4]=0   ; #8 IR[19:16] = 0   ; #8 IR[3:0] = 0  ; #8 IR[11:8] = 0  ; #8 IR[15:12] = 0  ; #8 RSLCT[19:16] = 0   ;#8 RESET = 0 ; #8 LOADPC = 0 ; #8 LOAD = 0 ; #8 IR_CU = 1 ;#8 S=1;#8 ALU_OUT=1;\n                                                                                                                                                                                                                                                            ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:52: Unsupported: Ignoring delay on this delayed statement.\n #9 OP = 16 ; #9 IR[27:25] = 0  ; #9 IR[11:7] = 1  ; #9 IR[6:5] = 0  ; #9 IR[4]=0   ; #9 IR[19:16] = 0   ; #9 IR[3:0] = 0  ; #9 IR[11:8] = 0  ; #9 IR[15:12] = 0  ; #9 RSLCT[19:16] = 0   ;#9 RESET = 0 ; #9 LOADPC = 0 ; #9 LOAD = 0 ; #9 IR_CU = 1 ;#9 S=1;#9 ALU_OUT=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:52: Unsupported: Ignoring delay on this delayed statement.\n #9 OP = 16 ; #9 IR[27:25] = 0  ; #9 IR[11:7] = 1  ; #9 IR[6:5] = 0  ; #9 IR[4]=0   ; #9 IR[19:16] = 0   ; #9 IR[3:0] = 0  ; #9 IR[11:8] = 0  ; #9 IR[15:12] = 0  ; #9 RSLCT[19:16] = 0   ;#9 RESET = 0 ; #9 LOADPC = 0 ; #9 LOAD = 0 ; #9 IR_CU = 1 ;#9 S=1;#9 ALU_OUT=1;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:52: Unsupported: Ignoring delay on this delayed statement.\n #9 OP = 16 ; #9 IR[27:25] = 0  ; #9 IR[11:7] = 1  ; #9 IR[6:5] = 0  ; #9 IR[4]=0   ; #9 IR[19:16] = 0   ; #9 IR[3:0] = 0  ; #9 IR[11:8] = 0  ; #9 IR[15:12] = 0  ; #9 RSLCT[19:16] = 0   ;#9 RESET = 0 ; #9 LOADPC = 0 ; #9 LOAD = 0 ; #9 IR_CU = 1 ;#9 S=1;#9 ALU_OUT=1;\n                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:52: Unsupported: Ignoring delay on this delayed statement.\n #9 OP = 16 ; #9 IR[27:25] = 0  ; #9 IR[11:7] = 1  ; #9 IR[6:5] = 0  ; #9 IR[4]=0   ; #9 IR[19:16] = 0   ; #9 IR[3:0] = 0  ; #9 IR[11:8] = 0  ; #9 IR[15:12] = 0  ; #9 RSLCT[19:16] = 0   ;#9 RESET = 0 ; #9 LOADPC = 0 ; #9 LOAD = 0 ; #9 IR_CU = 1 ;#9 S=1;#9 ALU_OUT=1;\n                                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:52: Unsupported: Ignoring delay on this delayed statement.\n #9 OP = 16 ; #9 IR[27:25] = 0  ; #9 IR[11:7] = 1  ; #9 IR[6:5] = 0  ; #9 IR[4]=0   ; #9 IR[19:16] = 0   ; #9 IR[3:0] = 0  ; #9 IR[11:8] = 0  ; #9 IR[15:12] = 0  ; #9 RSLCT[19:16] = 0   ;#9 RESET = 0 ; #9 LOADPC = 0 ; #9 LOAD = 0 ; #9 IR_CU = 1 ;#9 S=1;#9 ALU_OUT=1;\n                                                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:52: Unsupported: Ignoring delay on this delayed statement.\n #9 OP = 16 ; #9 IR[27:25] = 0  ; #9 IR[11:7] = 1  ; #9 IR[6:5] = 0  ; #9 IR[4]=0   ; #9 IR[19:16] = 0   ; #9 IR[3:0] = 0  ; #9 IR[11:8] = 0  ; #9 IR[15:12] = 0  ; #9 RSLCT[19:16] = 0   ;#9 RESET = 0 ; #9 LOADPC = 0 ; #9 LOAD = 0 ; #9 IR_CU = 1 ;#9 S=1;#9 ALU_OUT=1;\n                                                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:52: Unsupported: Ignoring delay on this delayed statement.\n #9 OP = 16 ; #9 IR[27:25] = 0  ; #9 IR[11:7] = 1  ; #9 IR[6:5] = 0  ; #9 IR[4]=0   ; #9 IR[19:16] = 0   ; #9 IR[3:0] = 0  ; #9 IR[11:8] = 0  ; #9 IR[15:12] = 0  ; #9 RSLCT[19:16] = 0   ;#9 RESET = 0 ; #9 LOADPC = 0 ; #9 LOAD = 0 ; #9 IR_CU = 1 ;#9 S=1;#9 ALU_OUT=1;\n                                                                                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:52: Unsupported: Ignoring delay on this delayed statement.\n #9 OP = 16 ; #9 IR[27:25] = 0  ; #9 IR[11:7] = 1  ; #9 IR[6:5] = 0  ; #9 IR[4]=0   ; #9 IR[19:16] = 0   ; #9 IR[3:0] = 0  ; #9 IR[11:8] = 0  ; #9 IR[15:12] = 0  ; #9 RSLCT[19:16] = 0   ;#9 RESET = 0 ; #9 LOADPC = 0 ; #9 LOAD = 0 ; #9 IR_CU = 1 ;#9 S=1;#9 ALU_OUT=1;\n                                                                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:52: Unsupported: Ignoring delay on this delayed statement.\n #9 OP = 16 ; #9 IR[27:25] = 0  ; #9 IR[11:7] = 1  ; #9 IR[6:5] = 0  ; #9 IR[4]=0   ; #9 IR[19:16] = 0   ; #9 IR[3:0] = 0  ; #9 IR[11:8] = 0  ; #9 IR[15:12] = 0  ; #9 RSLCT[19:16] = 0   ;#9 RESET = 0 ; #9 LOADPC = 0 ; #9 LOAD = 0 ; #9 IR_CU = 1 ;#9 S=1;#9 ALU_OUT=1;\n                                                                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:52: Unsupported: Ignoring delay on this delayed statement.\n #9 OP = 16 ; #9 IR[27:25] = 0  ; #9 IR[11:7] = 1  ; #9 IR[6:5] = 0  ; #9 IR[4]=0   ; #9 IR[19:16] = 0   ; #9 IR[3:0] = 0  ; #9 IR[11:8] = 0  ; #9 IR[15:12] = 0  ; #9 RSLCT[19:16] = 0   ;#9 RESET = 0 ; #9 LOADPC = 0 ; #9 LOAD = 0 ; #9 IR_CU = 1 ;#9 S=1;#9 ALU_OUT=1;\n                                                                                                                                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:52: Unsupported: Ignoring delay on this delayed statement.\n #9 OP = 16 ; #9 IR[27:25] = 0  ; #9 IR[11:7] = 1  ; #9 IR[6:5] = 0  ; #9 IR[4]=0   ; #9 IR[19:16] = 0   ; #9 IR[3:0] = 0  ; #9 IR[11:8] = 0  ; #9 IR[15:12] = 0  ; #9 RSLCT[19:16] = 0   ;#9 RESET = 0 ; #9 LOADPC = 0 ; #9 LOAD = 0 ; #9 IR_CU = 1 ;#9 S=1;#9 ALU_OUT=1;\n                                                                                                                                                                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:52: Unsupported: Ignoring delay on this delayed statement.\n #9 OP = 16 ; #9 IR[27:25] = 0  ; #9 IR[11:7] = 1  ; #9 IR[6:5] = 0  ; #9 IR[4]=0   ; #9 IR[19:16] = 0   ; #9 IR[3:0] = 0  ; #9 IR[11:8] = 0  ; #9 IR[15:12] = 0  ; #9 RSLCT[19:16] = 0   ;#9 RESET = 0 ; #9 LOADPC = 0 ; #9 LOAD = 0 ; #9 IR_CU = 1 ;#9 S=1;#9 ALU_OUT=1;\n                                                                                                                                                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:52: Unsupported: Ignoring delay on this delayed statement.\n #9 OP = 16 ; #9 IR[27:25] = 0  ; #9 IR[11:7] = 1  ; #9 IR[6:5] = 0  ; #9 IR[4]=0   ; #9 IR[19:16] = 0   ; #9 IR[3:0] = 0  ; #9 IR[11:8] = 0  ; #9 IR[15:12] = 0  ; #9 RSLCT[19:16] = 0   ;#9 RESET = 0 ; #9 LOADPC = 0 ; #9 LOAD = 0 ; #9 IR_CU = 1 ;#9 S=1;#9 ALU_OUT=1;\n                                                                                                                                                                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:52: Unsupported: Ignoring delay on this delayed statement.\n #9 OP = 16 ; #9 IR[27:25] = 0  ; #9 IR[11:7] = 1  ; #9 IR[6:5] = 0  ; #9 IR[4]=0   ; #9 IR[19:16] = 0   ; #9 IR[3:0] = 0  ; #9 IR[11:8] = 0  ; #9 IR[15:12] = 0  ; #9 RSLCT[19:16] = 0   ;#9 RESET = 0 ; #9 LOADPC = 0 ; #9 LOAD = 0 ; #9 IR_CU = 1 ;#9 S=1;#9 ALU_OUT=1;\n                                                                                                                                                                                                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:52: Unsupported: Ignoring delay on this delayed statement.\n #9 OP = 16 ; #9 IR[27:25] = 0  ; #9 IR[11:7] = 1  ; #9 IR[6:5] = 0  ; #9 IR[4]=0   ; #9 IR[19:16] = 0   ; #9 IR[3:0] = 0  ; #9 IR[11:8] = 0  ; #9 IR[15:12] = 0  ; #9 RSLCT[19:16] = 0   ;#9 RESET = 0 ; #9 LOADPC = 0 ; #9 LOAD = 0 ; #9 IR_CU = 1 ;#9 S=1;#9 ALU_OUT=1;\n                                                                                                                                                                                                                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:52: Unsupported: Ignoring delay on this delayed statement.\n #9 OP = 16 ; #9 IR[27:25] = 0  ; #9 IR[11:7] = 1  ; #9 IR[6:5] = 0  ; #9 IR[4]=0   ; #9 IR[19:16] = 0   ; #9 IR[3:0] = 0  ; #9 IR[11:8] = 0  ; #9 IR[15:12] = 0  ; #9 RSLCT[19:16] = 0   ;#9 RESET = 0 ; #9 LOADPC = 0 ; #9 LOAD = 0 ; #9 IR_CU = 1 ;#9 S=1;#9 ALU_OUT=1;\n                                                                                                                                                                                                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:54: Unsupported: Ignoring delay on this delayed statement.\n #10 OP = 16 ; #10 IR[27:25] = 0  ; #10 IR[11:7] = 1  ; #10 IR[6:5] = 0  ; #10 IR[4]=0   ; #10 IR[19:16] = 0   ; #10 IR[3:0] = 0  ; #10 IR[11:8] = 0  ; #10 IR[15:12] = 0  ; #10 RSLCT[19:16] = 0   ;#10 RESET = 0 ; #10 LOADPC = 0 ; #10 LOAD = 1 ; #10 IR_CU = 1 ;#10 S=1;#10 ALU_OUT=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:54: Unsupported: Ignoring delay on this delayed statement.\n #10 OP = 16 ; #10 IR[27:25] = 0  ; #10 IR[11:7] = 1  ; #10 IR[6:5] = 0  ; #10 IR[4]=0   ; #10 IR[19:16] = 0   ; #10 IR[3:0] = 0  ; #10 IR[11:8] = 0  ; #10 IR[15:12] = 0  ; #10 RSLCT[19:16] = 0   ;#10 RESET = 0 ; #10 LOADPC = 0 ; #10 LOAD = 1 ; #10 IR_CU = 1 ;#10 S=1;#10 ALU_OUT=1;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:54: Unsupported: Ignoring delay on this delayed statement.\n #10 OP = 16 ; #10 IR[27:25] = 0  ; #10 IR[11:7] = 1  ; #10 IR[6:5] = 0  ; #10 IR[4]=0   ; #10 IR[19:16] = 0   ; #10 IR[3:0] = 0  ; #10 IR[11:8] = 0  ; #10 IR[15:12] = 0  ; #10 RSLCT[19:16] = 0   ;#10 RESET = 0 ; #10 LOADPC = 0 ; #10 LOAD = 1 ; #10 IR_CU = 1 ;#10 S=1;#10 ALU_OUT=1;\n                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:54: Unsupported: Ignoring delay on this delayed statement.\n #10 OP = 16 ; #10 IR[27:25] = 0  ; #10 IR[11:7] = 1  ; #10 IR[6:5] = 0  ; #10 IR[4]=0   ; #10 IR[19:16] = 0   ; #10 IR[3:0] = 0  ; #10 IR[11:8] = 0  ; #10 IR[15:12] = 0  ; #10 RSLCT[19:16] = 0   ;#10 RESET = 0 ; #10 LOADPC = 0 ; #10 LOAD = 1 ; #10 IR_CU = 1 ;#10 S=1;#10 ALU_OUT=1;\n                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:54: Unsupported: Ignoring delay on this delayed statement.\n #10 OP = 16 ; #10 IR[27:25] = 0  ; #10 IR[11:7] = 1  ; #10 IR[6:5] = 0  ; #10 IR[4]=0   ; #10 IR[19:16] = 0   ; #10 IR[3:0] = 0  ; #10 IR[11:8] = 0  ; #10 IR[15:12] = 0  ; #10 RSLCT[19:16] = 0   ;#10 RESET = 0 ; #10 LOADPC = 0 ; #10 LOAD = 1 ; #10 IR_CU = 1 ;#10 S=1;#10 ALU_OUT=1;\n                                                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:54: Unsupported: Ignoring delay on this delayed statement.\n #10 OP = 16 ; #10 IR[27:25] = 0  ; #10 IR[11:7] = 1  ; #10 IR[6:5] = 0  ; #10 IR[4]=0   ; #10 IR[19:16] = 0   ; #10 IR[3:0] = 0  ; #10 IR[11:8] = 0  ; #10 IR[15:12] = 0  ; #10 RSLCT[19:16] = 0   ;#10 RESET = 0 ; #10 LOADPC = 0 ; #10 LOAD = 1 ; #10 IR_CU = 1 ;#10 S=1;#10 ALU_OUT=1;\n                                                                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:54: Unsupported: Ignoring delay on this delayed statement.\n #10 OP = 16 ; #10 IR[27:25] = 0  ; #10 IR[11:7] = 1  ; #10 IR[6:5] = 0  ; #10 IR[4]=0   ; #10 IR[19:16] = 0   ; #10 IR[3:0] = 0  ; #10 IR[11:8] = 0  ; #10 IR[15:12] = 0  ; #10 RSLCT[19:16] = 0   ;#10 RESET = 0 ; #10 LOADPC = 0 ; #10 LOAD = 1 ; #10 IR_CU = 1 ;#10 S=1;#10 ALU_OUT=1;\n                                                                                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:54: Unsupported: Ignoring delay on this delayed statement.\n #10 OP = 16 ; #10 IR[27:25] = 0  ; #10 IR[11:7] = 1  ; #10 IR[6:5] = 0  ; #10 IR[4]=0   ; #10 IR[19:16] = 0   ; #10 IR[3:0] = 0  ; #10 IR[11:8] = 0  ; #10 IR[15:12] = 0  ; #10 RSLCT[19:16] = 0   ;#10 RESET = 0 ; #10 LOADPC = 0 ; #10 LOAD = 1 ; #10 IR_CU = 1 ;#10 S=1;#10 ALU_OUT=1;\n                                                                                                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:54: Unsupported: Ignoring delay on this delayed statement.\n #10 OP = 16 ; #10 IR[27:25] = 0  ; #10 IR[11:7] = 1  ; #10 IR[6:5] = 0  ; #10 IR[4]=0   ; #10 IR[19:16] = 0   ; #10 IR[3:0] = 0  ; #10 IR[11:8] = 0  ; #10 IR[15:12] = 0  ; #10 RSLCT[19:16] = 0   ;#10 RESET = 0 ; #10 LOADPC = 0 ; #10 LOAD = 1 ; #10 IR_CU = 1 ;#10 S=1;#10 ALU_OUT=1;\n                                                                                                                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:54: Unsupported: Ignoring delay on this delayed statement.\n #10 OP = 16 ; #10 IR[27:25] = 0  ; #10 IR[11:7] = 1  ; #10 IR[6:5] = 0  ; #10 IR[4]=0   ; #10 IR[19:16] = 0   ; #10 IR[3:0] = 0  ; #10 IR[11:8] = 0  ; #10 IR[15:12] = 0  ; #10 RSLCT[19:16] = 0   ;#10 RESET = 0 ; #10 LOADPC = 0 ; #10 LOAD = 1 ; #10 IR_CU = 1 ;#10 S=1;#10 ALU_OUT=1;\n                                                                                                                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:54: Unsupported: Ignoring delay on this delayed statement.\n #10 OP = 16 ; #10 IR[27:25] = 0  ; #10 IR[11:7] = 1  ; #10 IR[6:5] = 0  ; #10 IR[4]=0   ; #10 IR[19:16] = 0   ; #10 IR[3:0] = 0  ; #10 IR[11:8] = 0  ; #10 IR[15:12] = 0  ; #10 RSLCT[19:16] = 0   ;#10 RESET = 0 ; #10 LOADPC = 0 ; #10 LOAD = 1 ; #10 IR_CU = 1 ;#10 S=1;#10 ALU_OUT=1;\n                                                                                                                                                                                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:54: Unsupported: Ignoring delay on this delayed statement.\n #10 OP = 16 ; #10 IR[27:25] = 0  ; #10 IR[11:7] = 1  ; #10 IR[6:5] = 0  ; #10 IR[4]=0   ; #10 IR[19:16] = 0   ; #10 IR[3:0] = 0  ; #10 IR[11:8] = 0  ; #10 IR[15:12] = 0  ; #10 RSLCT[19:16] = 0   ;#10 RESET = 0 ; #10 LOADPC = 0 ; #10 LOAD = 1 ; #10 IR_CU = 1 ;#10 S=1;#10 ALU_OUT=1;\n                                                                                                                                                                                                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:54: Unsupported: Ignoring delay on this delayed statement.\n #10 OP = 16 ; #10 IR[27:25] = 0  ; #10 IR[11:7] = 1  ; #10 IR[6:5] = 0  ; #10 IR[4]=0   ; #10 IR[19:16] = 0   ; #10 IR[3:0] = 0  ; #10 IR[11:8] = 0  ; #10 IR[15:12] = 0  ; #10 RSLCT[19:16] = 0   ;#10 RESET = 0 ; #10 LOADPC = 0 ; #10 LOAD = 1 ; #10 IR_CU = 1 ;#10 S=1;#10 ALU_OUT=1;\n                                                                                                                                                                                                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:54: Unsupported: Ignoring delay on this delayed statement.\n #10 OP = 16 ; #10 IR[27:25] = 0  ; #10 IR[11:7] = 1  ; #10 IR[6:5] = 0  ; #10 IR[4]=0   ; #10 IR[19:16] = 0   ; #10 IR[3:0] = 0  ; #10 IR[11:8] = 0  ; #10 IR[15:12] = 0  ; #10 RSLCT[19:16] = 0   ;#10 RESET = 0 ; #10 LOADPC = 0 ; #10 LOAD = 1 ; #10 IR_CU = 1 ;#10 S=1;#10 ALU_OUT=1;\n                                                                                                                                                                                                                                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:54: Unsupported: Ignoring delay on this delayed statement.\n #10 OP = 16 ; #10 IR[27:25] = 0  ; #10 IR[11:7] = 1  ; #10 IR[6:5] = 0  ; #10 IR[4]=0   ; #10 IR[19:16] = 0   ; #10 IR[3:0] = 0  ; #10 IR[11:8] = 0  ; #10 IR[15:12] = 0  ; #10 RSLCT[19:16] = 0   ;#10 RESET = 0 ; #10 LOADPC = 0 ; #10 LOAD = 1 ; #10 IR_CU = 1 ;#10 S=1;#10 ALU_OUT=1;\n                                                                                                                                                                                                                                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:54: Unsupported: Ignoring delay on this delayed statement.\n #10 OP = 16 ; #10 IR[27:25] = 0  ; #10 IR[11:7] = 1  ; #10 IR[6:5] = 0  ; #10 IR[4]=0   ; #10 IR[19:16] = 0   ; #10 IR[3:0] = 0  ; #10 IR[11:8] = 0  ; #10 IR[15:12] = 0  ; #10 RSLCT[19:16] = 0   ;#10 RESET = 0 ; #10 LOADPC = 0 ; #10 LOAD = 1 ; #10 IR_CU = 1 ;#10 S=1;#10 ALU_OUT=1;\n                                                                                                                                                                                                                                                                            ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:59: Unsupported: Ignoring delay on this delayed statement.\n #1 Clk = ~Clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:61: Unsupported: Ignoring delay on this delayed statement.\ninitial #sim_time $finish; \n        ^\n%Error: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:64: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("prefab_alu_rf_bs2.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:65: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,prefab_alu_rf_bs2);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/PreFabALU+RF+BS/prefab_alu_rf_bs2.v:67: Unsupported or unknown PLI call: $monitor\n $monitor("time = %3d , in = %3d , LOADPC = %3d , LOAD = %3d , IR_CU = %3d , RSLCT = %3h, Rn = %3d ,Rm = %3d ,Rs = %3d ,PCout = %3d,OP=%3d;FLAGS=0; S=%1b;ALU_OUT=%1b;",$time, in, LOADPC, LOAD, IR_CU, RSLCT,Rn,Rm,Rs,PCout,OP,FLAGS,S,ALU_OUT);\n ^~~~~~~~\n%Error: Exiting due to 4 error(s), 162 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module prefab_alu_rf_bs2;

parameter sim_time = 750*2;

reg [19:0] RSLCT;
reg Clk, RESET, LOADPC, LOAD,IR_CU;
wire [31:0] Rn,Rm,Rs,PCout,in;

RegisterFile RF(in,in,RSLCT,Clk, RESET, LOADPC, LOAD,IR_CU, Rn,Rm,Rs,PCout);

reg [31:0] IR;
wire SR29_OUT;
wire [31:0] Out;
wire [3:0] FLAGS;
wire [3:0] FLAGS_OUT;


BarrelShifter bs(Rs,Rm,IR,FLAGS[1],FLAGS_OUT[1], Out);


reg [4:0] OP;
reg S,ALU_OUT;


ARM_ALU alu(Rn,Out, OP, FLAGS_OUT, in,FLAGS,S,ALU_OUT);

always@(IR)
begin
	RSLCT = {IR[15:8],IR[3:1], IR[19:16]};
end

initial fork

	IR = 0 ; Clk = 0 ; RESET = 1 ;   LOADPC = 0 ; LOAD = 0 ;IR_CU = 1 ; RSLCT[3:0] = 0 ; RSLCT[7:4] = 0 ; RSLCT[11:8] = 0 ; RSLCT[15:12] = 0 ; RSLCT[19:16] = 0 ; OP=17;  S=1;ALU_OUT=1;

	#1 OP = 0  ; #1 IR[27:25] = 0; #1 IR[11:7] = 0; #1 IR[6:5] = 0; #1 IR[4]=1; #1 IR[19:16] = 0; #1 IR[3:0] = 0; #1 IR[11:8] = 0; #1 IR[15:12] = 0; #1 RSLCT[19:16] = 0;#1 RESET = 0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ;#1 S=0;#1 ALU_OUT=0;

	#2 OP = 17; #2 IR[27:25] = 0; #2 IR[11:7] = 0; #2 IR[6:5] = 1; #2 IR[4]=0; #2 IR[19:16] = 0; #2 IR[3:0] = 0; #2 IR[11:8] = 0; #2 IR[15:12] = 0; #2 RSLCT[19:16] = 0;#2 RESET = 0 ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ;#2 S=1;#2 ALU_OUT=1;

	#3 OP = 17 ; #3 IR[27:25] = 0; #3 IR[11:7] = 0; #3 IR[6:5] = 1; #3 IR[4]=0; #3 IR[19:16] = 0; #3 IR[3:0] = 0; #3 IR[11:8] = 0; #3 IR[15:12] = 0; #3 RSLCT[19:16] = 0;#3 RESET = 0 ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ;#3 S=1;#3 ALU_OUT=1;

	#4 OP = 17; #4 IR[27:25] = 0; #4 IR[11:7] = 0; #4 IR[6:5] = 1; #4 IR[4]=0; #4 IR[19:16] = 0; #4 IR[3:0] = 0; #4 IR[11:8] = 0; #4 IR[15:12] = 0; #4 RSLCT[19:16] = 0;#4 RESET = 0 ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ;#4 S=1;#4 ALU_OUT=1;

	#5 OP = 17 ; #5 IR[27:25] = 0; #5 IR[11:7] = 0; #5 IR[6:5] = 1; #5 IR[4]=0; #5 IR[19:16] = 0; #5 IR[3:0] = 0; #5 IR[11:8] = 0; #5 IR[15:12] = 0; #5 RSLCT[19:16] = 0;#5 RESET = 0 ; #5 LOADPC = 0 ; #5 LOAD = 1 ; #5 IR_CU = 1 ;#5 S=1;#5 ALU_OUT=1;

	#6 OP = 0  ; #6 IR[27:25] = 0; #6 IR[11:7] = 0; #6 IR[6:5] = 0; #6 IR[4]=1; #6 IR[19:16] = 0; #6 IR[3:0] = 0; #6 IR[11:8] = 0; #6 IR[15:12] = 0; #6 RSLCT[19:16] = 0;#6 RESET = 0 ; #6 LOADPC = 0 ; #6 LOAD = 0 ; #6 IR_CU = 1 ;#6 S=0;#6 ALU_OUT=0;

	#7 OP = 0  ; #7 IR[27:25] = 0; #7 IR[11:7] = 0; #7 IR[6:5] = 0; #7 IR[4]=1; #7 IR[19:16] = 0; #7 IR[3:0] = 0; #7 IR[11:8] = 0; #7 IR[15:12] = 0; #7 RSLCT[19:16] = 0;#7 RESET = 0 ; #7 LOADPC = 0 ; #7 LOAD = 0 ; #7 IR_CU = 1 ;#7 S=0;#7 ALU_OUT=0;

	#8 OP = 16; #8 IR[27:25] = 0; #8 IR[11:7] = 1; #8 IR[6:5] = 0; #8 IR[4]=0; #8 IR[19:16] = 0; #8 IR[3:0] = 0; #8 IR[11:8] = 0; #8 IR[15:12] = 0; #8 RSLCT[19:16] = 0;#8 RESET = 0 ; #8 LOADPC = 0 ; #8 LOAD = 0 ; #8 IR_CU = 1 ;#8 S=1;#8 ALU_OUT=1;

	#9 OP = 16 ; #9 IR[27:25] = 0; #9 IR[11:7] = 1; #9 IR[6:5] = 0; #9 IR[4]=0; #9 IR[19:16] = 0; #9 IR[3:0] = 0; #9 IR[11:8] = 0; #9 IR[15:12] = 0; #9 RSLCT[19:16] = 0;#9 RESET = 0 ; #9 LOADPC = 0 ; #9 LOAD = 0 ; #9 IR_CU = 1 ;#9 S=1;#9 ALU_OUT=1;

	#10 OP = 16 ; #10 IR[27:25] = 0; #10 IR[11:7] = 1; #10 IR[6:5] = 0; #10 IR[4]=0; #10 IR[19:16] = 0; #10 IR[3:0] = 0; #10 IR[11:8] = 0; #10 IR[15:12] = 0; #10 RSLCT[19:16] = 0;#10 RESET = 0 ; #10 LOADPC = 0 ; #10 LOAD = 1 ; #10 IR_CU = 1 ;#10 S=1;#10 ALU_OUT=1;

join

always 
	#1 Clk = ~Clk;
	
initial #sim_time $finish; 

initial begin
	$dumpfile("prefab_alu_rf_bs2.vcd");
	$dumpvars(0,prefab_alu_rf_bs2);
	$display(" Test Results" );
	$monitor("time = %3d , in = %3d , LOADPC = %3d , LOAD = %3d , IR_CU = %3d , RSLCT = %3h, Rn = %3d ,Rm = %3d ,Rs = %3d ,PCout = %3d,OP=%3d;FLAGS=0; S=%1b;ALU_OUT=%1b;",$time, in, LOADPC, LOAD, IR_CU, RSLCT,Rn,Rm,Rs,PCout,OP,FLAGS,S,ALU_OUT);
end

endmodule
module prefab_alu_rf_bs2;


parameter sim_time = 750*2;

reg [19:0] RSLCT;
reg Clk, RESET, LOADPC, LOAD,IR_CU;
wire [31:0] Rn,Rm,Rs,PCout,in;

RegisterFile RF(in,in,RSLCT,Clk, RESET, LOADPC, LOAD,IR_CU, Rn,Rm,Rs,PCout);

reg [31:0] IR;
wire SR29_OUT;
wire [31:0] Out;
wire [3:0] FLAGS;
wire [3:0] FLAGS_OUT;


BarrelShifter bs(Rs,Rm,IR,FLAGS[1],FLAGS_OUT[1], Out);


reg [4:0] OP;
reg S,ALU_OUT;


ARM_ALU alu(Rn,Out, OP, FLAGS_OUT, in,FLAGS,S,ALU_OUT);

always@(IR)
begin
	RSLCT = {IR[15:8],IR[3:1], IR[19:16]};
end

initial fork

	IR = 0 ; Clk = 0 ; RESET = 1 ;   LOADPC = 0 ; LOAD = 0 ;IR_CU = 1 ; RSLCT[3:0] = 0 ; RSLCT[7:4] = 0 ; RSLCT[11:8] = 0 ; RSLCT[15:12] = 0 ; RSLCT[19:16] = 0 ; OP=17;  S=1;ALU_OUT=1;

	#1 OP = 0  ; #1 IR[27:25] = 0; #1 IR[11:7] = 0; #1 IR[6:5] = 0; #1 IR[4]=1; #1 IR[19:16] = 0; #1 IR[3:0] = 0; #1 IR[11:8] = 0; #1 IR[15:12] = 0; #1 RSLCT[19:16] = 0;#1 RESET = 0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ;#1 S=0;#1 ALU_OUT=0;

	#2 OP = 17; #2 IR[27:25] = 0; #2 IR[11:7] = 0; #2 IR[6:5] = 1; #2 IR[4]=0; #2 IR[19:16] = 0; #2 IR[3:0] = 0; #2 IR[11:8] = 0; #2 IR[15:12] = 0; #2 RSLCT[19:16] = 0;#2 RESET = 0 ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ;#2 S=1;#2 ALU_OUT=1;

	#3 OP = 17 ; #3 IR[27:25] = 0; #3 IR[11:7] = 0; #3 IR[6:5] = 1; #3 IR[4]=0; #3 IR[19:16] = 0; #3 IR[3:0] = 0; #3 IR[11:8] = 0; #3 IR[15:12] = 0; #3 RSLCT[19:16] = 0;#3 RESET = 0 ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ;#3 S=1;#3 ALU_OUT=1;

	#4 OP = 17; #4 IR[27:25] = 0; #4 IR[11:7] = 0; #4 IR[6:5] = 1; #4 IR[4]=0; #4 IR[19:16] = 0; #4 IR[3:0] = 0; #4 IR[11:8] = 0; #4 IR[15:12] = 0; #4 RSLCT[19:16] = 0;#4 RESET = 0 ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ;#4 S=1;#4 ALU_OUT=1;

	#5 OP = 17 ; #5 IR[27:25] = 0; #5 IR[11:7] = 0; #5 IR[6:5] = 1; #5 IR[4]=0; #5 IR[19:16] = 0; #5 IR[3:0] = 0; #5 IR[11:8] = 0; #5 IR[15:12] = 0; #5 RSLCT[19:16] = 0;#5 RESET = 0 ; #5 LOADPC = 0 ; #5 LOAD = 1 ; #5 IR_CU = 1 ;#5 S=1;#5 ALU_OUT=1;

	#6 OP = 0  ; #6 IR[27:25] = 0; #6 IR[11:7] = 0; #6 IR[6:5] = 0; #6 IR[4]=1; #6 IR[19:16] = 0; #6 IR[3:0] = 0; #6 IR[11:8] = 0; #6 IR[15:12] = 0; #6 RSLCT[19:16] = 0;#6 RESET = 0 ; #6 LOADPC = 0 ; #6 LOAD = 0 ; #6 IR_CU = 1 ;#6 S=0;#6 ALU_OUT=0;

	#7 OP = 0  ; #7 IR[27:25] = 0; #7 IR[11:7] = 0; #7 IR[6:5] = 0; #7 IR[4]=1; #7 IR[19:16] = 0; #7 IR[3:0] = 0; #7 IR[11:8] = 0; #7 IR[15:12] = 0; #7 RSLCT[19:16] = 0;#7 RESET = 0 ; #7 LOADPC = 0 ; #7 LOAD = 0 ; #7 IR_CU = 1 ;#7 S=0;#7 ALU_OUT=0;

	#8 OP = 16; #8 IR[27:25] = 0; #8 IR[11:7] = 1; #8 IR[6:5] = 0; #8 IR[4]=0; #8 IR[19:16] = 0; #8 IR[3:0] = 0; #8 IR[11:8] = 0; #8 IR[15:12] = 0; #8 RSLCT[19:16] = 0;#8 RESET = 0 ; #8 LOADPC = 0 ; #8 LOAD = 0 ; #8 IR_CU = 1 ;#8 S=1;#8 ALU_OUT=1;

	#9 OP = 16 ; #9 IR[27:25] = 0; #9 IR[11:7] = 1; #9 IR[6:5] = 0; #9 IR[4]=0; #9 IR[19:16] = 0; #9 IR[3:0] = 0; #9 IR[11:8] = 0; #9 IR[15:12] = 0; #9 RSLCT[19:16] = 0;#9 RESET = 0 ; #9 LOADPC = 0 ; #9 LOAD = 0 ; #9 IR_CU = 1 ;#9 S=1;#9 ALU_OUT=1;

	#10 OP = 16 ; #10 IR[27:25] = 0; #10 IR[11:7] = 1; #10 IR[6:5] = 0; #10 IR[4]=0; #10 IR[19:16] = 0; #10 IR[3:0] = 0; #10 IR[11:8] = 0; #10 IR[15:12] = 0; #10 RSLCT[19:16] = 0;#10 RESET = 0 ; #10 LOADPC = 0 ; #10 LOAD = 1 ; #10 IR_CU = 1 ;#10 S=1;#10 ALU_OUT=1;

join

always 
	#1 Clk = ~Clk;
	
initial #sim_time $finish; 

initial begin
	$dumpfile("prefab_alu_rf_bs2.vcd");
	$dumpvars(0,prefab_alu_rf_bs2);
	$display(" Test Results" );
	$monitor("time = %3d , in = %3d , LOADPC = %3d , LOAD = %3d , IR_CU = %3d , RSLCT = %3h, Rn = %3d ,Rm = %3d ,Rs = %3d ,PCout = %3d,OP=%3d;FLAGS=0; S=%1b;ALU_OUT=%1b;",$time, in, LOADPC, LOAD, IR_CU, RSLCT,Rn,Rm,Rs,PCout,OP,FLAGS,S,ALU_OUT);
end

endmodule