data/full_repos/permissive/451577625/system/bit_pair_recoder_32.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/451577625/system/bit_pair_recoder_32.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) bit_pair = 3\'b101;   \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/bit_pair_recoder_32.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) bit_pair = 3\'b111;   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/bit_pair_recoder_32.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) bit_pair = 3\'b010;   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/bit_pair_recoder_32.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) bit_pair = 3\'b011;   \n  ^\n%Error: data/full_repos/permissive/451577625/system/bit_pair_recoder_32.v:7: Cannot find file containing module: \'adder_32\'\n adder_32 adder(.in_x (~in_multiplier),\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/adder_32\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/adder_32.v\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/adder_32.sv\n             adder_32\n             adder_32.v\n             adder_32.sv\n             obj_dir/adder_32\n             obj_dir/adder_32.v\n             obj_dir/adder_32.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bit_pair_recoder_32(input [31:0] in_multiplier, input [2:0] in_bit_pair, output reg [63:0] out_recode);

	wire [31:0] w_neg_multiplier;
	wire [32:0] w_pos_shift;
	wire [32:0] w_neg_shift;
	
	adder_32 adder(.in_x (~in_multiplier),
		.in_y (32'b0),
		.in_carry (1'b1),
		.out_sum (w_neg_multiplier),
		.out_carry ());
	
	assign w_pos_shift = {in_multiplier, 1'b0};
	assign w_neg_shift = {w_neg_multiplier, 1'b0};

	always @(*) begin
		case(in_bit_pair)
			3'b000,
			3'b111:  out_recode = 64'b0;
			3'b001,
			3'b010:  out_recode = {{32{in_multiplier[31]}}, in_multiplier};
			3'b011:  out_recode = {{31{w_pos_shift[32]}}, w_pos_shift};
			3'b100:  out_recode = {{31{w_neg_shift[32]}}, w_neg_shift};
			3'b101,
			3'b110:  out_recode = {{32{w_neg_multiplier[31]}}, w_neg_multiplier};
			default: out_recode = 64'b0;
		endcase
	end
endmodule
module bit_pair_recoder_32(input [31:0] in_multiplier, input [2:0] in_bit_pair, output reg [63:0] out_recode);


	wire [31:0] w_neg_multiplier;
	wire [32:0] w_pos_shift;
	wire [32:0] w_neg_shift;
	
	adder_32 adder(.in_x (~in_multiplier),
		.in_y (32'b0),
		.in_carry (1'b1),
		.out_sum (w_neg_multiplier),
		.out_carry ());
	
	assign w_pos_shift = {in_multiplier, 1'b0};
	assign w_neg_shift = {w_neg_multiplier, 1'b0};

	always @(*) begin
		case(in_bit_pair)
			3'b000,
			3'b111:  out_recode = 64'b0;
			3'b001,
			3'b010:  out_recode = {{32{in_multiplier[31]}}, in_multiplier};
			3'b011:  out_recode = {{31{w_pos_shift[32]}}, w_pos_shift};
			3'b100:  out_recode = {{31{w_neg_shift[32]}}, w_neg_shift};
			3'b101,
			3'b110:  out_recode = {{32{w_neg_multiplier[31]}}, w_neg_multiplier};
			default: out_recode = 64'b0;
		endcase
	end
endmodule