data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_cl_jbusr_jbus.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_cl_jbusr_jbus.v:42: Cannot find file containing module: 'bw_clk_cclk_inv_64x'\nbw_clk_cclk_inv_64x xc3a (\n^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_clk_cclk_inv_64x\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_clk_cclk_inv_64x.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_clk_cclk_inv_64x.sv\n             bw_clk_cclk_inv_64x\n             bw_clk_cclk_inv_64x.v\n             bw_clk_cclk_inv_64x.sv\n             obj_dir/bw_clk_cclk_inv_64x\n             obj_dir/bw_clk_cclk_inv_64x.v\n             obj_dir/bw_clk_cclk_inv_64x.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_cl_jbusr_jbus.v:45: Cannot find file containing module: 'bw_clk_cclk_inv_128x'\nbw_clk_cclk_inv_128x xgriddrv_3_ (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_cl_jbusr_jbus.v:48: Cannot find file containing module: 'bw_clk_cclk_inv_64x'\nbw_clk_cclk_inv_64x xc3b (\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_cl_jbusr_jbus.v:51: Cannot find file containing module: 'bw_clk_cclk_inv_64x'\nbw_clk_cclk_inv_64x xc3c (\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_cl_jbusr_jbus.v:54: Cannot find file containing module: 'bw_clk_cclk_inv_64x'\nbw_clk_cclk_inv_64x xc3d (\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_cl_jbusr_jbus.v:57: Cannot find file containing module: 'bw_clk_cclk_inv_128x'\nbw_clk_cclk_inv_128x xgriddrv_11_ (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_cl_jbusr_jbus.v:60: Cannot find file containing module: 'bw_clk_cclk_inv_64x'\nbw_clk_cclk_inv_64x xc4a (\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_cl_jbusr_jbus.v:63: Cannot find file containing module: 'bw_clk_cclk_inv_128x'\nbw_clk_cclk_inv_128x xgriddrv_2_ (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_cl_jbusr_jbus.v:66: Cannot find file containing module: 'bw_clk_cclk_inv_64x'\nbw_clk_cclk_inv_64x xc4b (\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_cl_jbusr_jbus.v:69: Cannot find file containing module: 'bw_clk_cclk_hdr_48x'\nbw_clk_cclk_hdr_48x xCCHdr (\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_cl_jbusr_jbus.v:83: Cannot find file containing module: 'bw_clk_cclk_inv_128x'\nbw_clk_cclk_inv_128x xgriddrv_9_ (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_cl_jbusr_jbus.v:86: Cannot find file containing module: 'bw_clk_cclk_inv_128x'\nbw_clk_cclk_inv_128x xgriddrv_1_ (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_cl_jbusr_jbus.v:89: Cannot find file containing module: 'bw_clk_cclk_inv_128x'\nbw_clk_cclk_inv_128x xgriddrv_8_ (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_cl_jbusr_jbus.v:92: Cannot find file containing module: 'bw_clk_cclk_inv_128x'\nbw_clk_cclk_inv_128x xgriddrv_0_ (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_cl_jbusr_jbus.v:95: Cannot find file containing module: 'bw_clk_cclk_inv_128x'\nbw_clk_cclk_inv_128x xgriddrv_10_ (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_cl_jbusr_jbus.v:98: Cannot find file containing module: 'bw_clk_cclk_inv_48x'\nbw_clk_cclk_inv_48x xc5 (\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_cl_jbusr_jbus.v:101: Cannot find file containing module: 'bw_clk_cclk_inv_128x'\nbw_clk_cclk_inv_128x xgriddrv_7_ (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_cl_jbusr_jbus.v:104: Cannot find file containing module: 'terminator'\nterminator I22 (\n^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_cl_jbusr_jbus.v:106: Cannot find file containing module: 'bw_clk_cclk_inv_128x'\nbw_clk_cclk_inv_128x xgriddrv_6_ (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_cl_jbusr_jbus.v:109: Cannot find file containing module: 'bw_clk_cclk_inv_128x'\nbw_clk_cclk_inv_128x xgriddrv_5_ (\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_cl_jbusr_jbus.v:112: Cannot find file containing module: 'bw_clk_cclk_inv_128x'\nbw_clk_cclk_inv_128x xgriddrv_4_ (\n^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 21 error(s)\n"
module bw_clk_cl_jbusr_jbus(cluster_grst_l ,so ,dbginit_l ,rclk ,si ,se
      ,adbginit_l ,gdbginit_l ,arst_l ,grst_l ,cluster_cken ,gclk );
output		cluster_grst_l ;
output		so ;
output		dbginit_l ;
output		rclk ;
input		si ;
input		se ;
input		adbginit_l ;
input		gdbginit_l ;
input		arst_l ;
input		grst_l ;
input		cluster_cken ;
input		gclk ;
 
wire [3:0]	clk3 ;
wire [1:0]	clk4 ;
wire		clk5 ;
wire		cclk ;
 
 
bw_clk_cclk_inv_64x xc3a (
     .clkout          (clk3[0] ),
     .clkin           (clk4[0] ) );
bw_clk_cclk_inv_128x xgriddrv_3_ (
     .clkout          (rclk ),
     .clkin           (clk3[0] ) );
bw_clk_cclk_inv_64x xc3b (
     .clkout          (clk3[1] ),
     .clkin           (clk4[0] ) );
bw_clk_cclk_inv_64x xc3c (
     .clkout          (clk3[2] ),
     .clkin           (clk4[1] ) );
bw_clk_cclk_inv_64x xc3d (
     .clkout          (clk3[3] ),
     .clkin           (clk4[1] ) );
bw_clk_cclk_inv_128x xgriddrv_11_ (
     .clkout          (rclk ),
     .clkin           (clk3[2] ) );
bw_clk_cclk_inv_64x xc4a (
     .clkout          (clk4[0] ),
     .clkin           (clk5 ) );
bw_clk_cclk_inv_128x xgriddrv_2_ (
     .clkout          (rclk ),
     .clkin           (clk3[0] ) );
bw_clk_cclk_inv_64x xc4b (
     .clkout          (clk4[1] ),
     .clkin           (clk5 ) );
bw_clk_cclk_hdr_48x xCCHdr (
     .rst_l           (cluster_grst_l ),
     .dbginit_l       (dbginit_l ),
     .clk             (cclk ),
     .so              (so ),
     .gclk            (gclk ),
     .cluster_cken    (cluster_cken ),
     .arst_l          (arst_l ),
     .grst_l          (grst_l ),
     .adbginit_l      (adbginit_l ),
     .gdbginit_l      (gdbginit_l ),
     .si              (si ),
     .se              (se ),
     .rclk            (rclk ) );
bw_clk_cclk_inv_128x xgriddrv_9_ (
     .clkout          (rclk ),
     .clkin           (clk3[2] ) );
bw_clk_cclk_inv_128x xgriddrv_1_ (
     .clkout          (rclk ),
     .clkin           (clk3[0] ) );
bw_clk_cclk_inv_128x xgriddrv_8_ (
     .clkout          (rclk ),
     .clkin           (clk3[2] ) );
bw_clk_cclk_inv_128x xgriddrv_0_ (
     .clkout          (rclk ),
     .clkin           (clk3[0] ) );
bw_clk_cclk_inv_128x xgriddrv_10_ (
     .clkout          (rclk ),
     .clkin           (clk3[2] ) );
bw_clk_cclk_inv_48x xc5 (
     .clkout          (clk5 ),
     .clkin           (cclk ) );
bw_clk_cclk_inv_128x xgriddrv_7_ (
     .clkout          (rclk ),
     .clkin           (clk3[1] ) );
terminator I22 (
     .TERM            (clk3[3] ) );
bw_clk_cclk_inv_128x xgriddrv_6_ (
     .clkout          (rclk ),
     .clkin           (clk3[1] ) );
bw_clk_cclk_inv_128x xgriddrv_5_ (
     .clkout          (rclk ),
     .clkin           (clk3[1] ) );
bw_clk_cclk_inv_128x xgriddrv_4_ (
     .clkout          (rclk ),
     .clkin           (clk3[1] ) );
endmodule
module bw_clk_cl_jbusr_jbus(cluster_grst_l ,so ,dbginit_l ,rclk ,si ,se
      ,adbginit_l ,gdbginit_l ,arst_l ,grst_l ,cluster_cken ,gclk );

output		cluster_grst_l ;
output		so ;
output		dbginit_l ;
output		rclk ;
input		si ;
input		se ;
input		adbginit_l ;
input		gdbginit_l ;
input		arst_l ;
input		grst_l ;
input		cluster_cken ;
input		gclk ;
 
wire [3:0]	clk3 ;
wire [1:0]	clk4 ;
wire		clk5 ;
wire		cclk ;
 
 
bw_clk_cclk_inv_64x xc3a (
     .clkout          (clk3[0] ),
     .clkin           (clk4[0] ) );
bw_clk_cclk_inv_128x xgriddrv_3_ (
     .clkout          (rclk ),
     .clkin           (clk3[0] ) );
bw_clk_cclk_inv_64x xc3b (
     .clkout          (clk3[1] ),
     .clkin           (clk4[0] ) );
bw_clk_cclk_inv_64x xc3c (
     .clkout          (clk3[2] ),
     .clkin           (clk4[1] ) );
bw_clk_cclk_inv_64x xc3d (
     .clkout          (clk3[3] ),
     .clkin           (clk4[1] ) );
bw_clk_cclk_inv_128x xgriddrv_11_ (
     .clkout          (rclk ),
     .clkin           (clk3[2] ) );
bw_clk_cclk_inv_64x xc4a (
     .clkout          (clk4[0] ),
     .clkin           (clk5 ) );
bw_clk_cclk_inv_128x xgriddrv_2_ (
     .clkout          (rclk ),
     .clkin           (clk3[0] ) );
bw_clk_cclk_inv_64x xc4b (
     .clkout          (clk4[1] ),
     .clkin           (clk5 ) );
bw_clk_cclk_hdr_48x xCCHdr (
     .rst_l           (cluster_grst_l ),
     .dbginit_l       (dbginit_l ),
     .clk             (cclk ),
     .so              (so ),
     .gclk            (gclk ),
     .cluster_cken    (cluster_cken ),
     .arst_l          (arst_l ),
     .grst_l          (grst_l ),
     .adbginit_l      (adbginit_l ),
     .gdbginit_l      (gdbginit_l ),
     .si              (si ),
     .se              (se ),
     .rclk            (rclk ) );
bw_clk_cclk_inv_128x xgriddrv_9_ (
     .clkout          (rclk ),
     .clkin           (clk3[2] ) );
bw_clk_cclk_inv_128x xgriddrv_1_ (
     .clkout          (rclk ),
     .clkin           (clk3[0] ) );
bw_clk_cclk_inv_128x xgriddrv_8_ (
     .clkout          (rclk ),
     .clkin           (clk3[2] ) );
bw_clk_cclk_inv_128x xgriddrv_0_ (
     .clkout          (rclk ),
     .clkin           (clk3[0] ) );
bw_clk_cclk_inv_128x xgriddrv_10_ (
     .clkout          (rclk ),
     .clkin           (clk3[2] ) );
bw_clk_cclk_inv_48x xc5 (
     .clkout          (clk5 ),
     .clkin           (cclk ) );
bw_clk_cclk_inv_128x xgriddrv_7_ (
     .clkout          (rclk ),
     .clkin           (clk3[1] ) );
terminator I22 (
     .TERM            (clk3[3] ) );
bw_clk_cclk_inv_128x xgriddrv_6_ (
     .clkout          (rclk ),
     .clkin           (clk3[1] ) );
bw_clk_cclk_inv_128x xgriddrv_5_ (
     .clkout          (rclk ),
     .clkin           (clk3[1] ) );
bw_clk_cclk_inv_128x xgriddrv_4_ (
     .clkout          (rclk ),
     .clkin           (clk3[1] ) );
endmodule