data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/clk_divider.v
1: b'%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/clk_divider.v:32: Operator AND expects 8 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                                        : ... In instance clk_divider\n       counter <= #1 ratio[7:1] + (ratio[0] & out_clk) - 8\'b1;\n                                            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/clk_divider.v:32: Operator AND expects 8 bits on the RHS, but RHS\'s VARREF \'out_clk\' generates 1 bits.\n                                                                                        : ... In instance clk_divider\n       counter <= #1 ratio[7:1] + (ratio[0] & out_clk) - 8\'b1;\n                                            ^\n%Error: Exiting due to 2 warning(s)\n'
module clk_divider(input reset, input wire in_clk,output reg out_clk, input [7:0] ratio);
   reg [7:0] counter;
   

	
   always @(posedge in_clk or posedge reset)
     if(reset)
       counter <= #1 8'd0;
     else if(counter == 0)
       counter <= #1 ratio[7:1] + (ratio[0] & out_clk) - 8'b1;
     else
       counter <= #1 counter-8'd1;
   
   always @(posedge in_clk or posedge reset)
     if(reset)
       out_clk <= #1 1'b0;
     else if(counter == 0)
       out_clk <= #1 ~out_clk;
   
endmodule
module clk_divider(input reset, input wire in_clk,output reg out_clk, input [7:0] ratio);

   reg [7:0] counter;
   

	
   always @(posedge in_clk or posedge reset)
     if(reset)
       counter <= #1 8'd0;
     else if(counter == 0)
       counter <= #1 ratio[7:1] + (ratio[0] & out_clk) - 8'b1;
     else
       counter <= #1 counter-8'd1;
   
   always @(posedge in_clk or posedge reset)
     if(reset)
       out_clk <= #1 1'b0;
     else if(counter == 0)
       out_clk <= #1 ~out_clk;
   
endmodule