data/full_repos/permissive/471766415/src/top_fpga.v
1: b'%Error: data/full_repos/permissive/471766415/src/top_fpga.v:19: Cannot find file containing module: \'vga_pll\'\n    vga_pll pll(\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/471766415/src,data/full_repos/permissive/471766415/vga_pll\n             data/full_repos/permissive/471766415/src,data/full_repos/permissive/471766415/vga_pll.v\n             data/full_repos/permissive/471766415/src,data/full_repos/permissive/471766415/vga_pll.sv\n             vga_pll\n             vga_pll.v\n             vga_pll.sv\n             obj_dir/vga_pll\n             obj_dir/vga_pll.v\n             obj_dir/vga_pll.sv\n%Warning-WIDTH: data/full_repos/permissive/471766415/src/top_fpga.v:27: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n                                                                      : ... In instance top\n  resetn_gen <= {resetn_gen, pll_locked};\n             ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/471766415/src/top_fpga.v:30: Cannot find file containing module: \'vga_demo\'\n    vga_demo topi(\n    ^~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module top(
    input clk,
    input btn,
    output vga_h_sync,
    output vga_v_sync,
    output reg[3:0] vga_r,
    output reg[3:0] vga_g,
    output reg[3:0] vga_b
);

    reg [3:0] resetn_gen = 0;
	reg reset;
    wire pll_locked;
    wire clk_25_175;

    vga_pll pll(
        .clock_in(clk),
        .pll_locked(pll_locked),
        .clock_out(clk_25_175),
    );

	always @(posedge clk_25_175) begin
		reset <= &resetn_gen;
		resetn_gen <= {resetn_gen, pll_locked};
	end

    vga_demo topi(
        .clk(clk_25_175),
        .reset(reset),
        .vga_h_sync(vga_h_sync),
        .vga_v_sync(vga_v_sync),
        .vga_r(vga_r),
        .vga_g(vga_g),
        .vga_b(vga_b)
    );

endmodule
module top(
    input clk,
    input btn,
    output vga_h_sync,
    output vga_v_sync,
    output reg[3:0] vga_r,
    output reg[3:0] vga_g,
    output reg[3:0] vga_b
);


    reg [3:0] resetn_gen = 0;
	reg reset;
    wire pll_locked;
    wire clk_25_175;

    vga_pll pll(
        .clock_in(clk),
        .pll_locked(pll_locked),
        .clock_out(clk_25_175),
    );

	always @(posedge clk_25_175) begin
		reset <= &resetn_gen;
		resetn_gen <= {resetn_gen, pll_locked};
	end

    vga_demo topi(
        .clk(clk_25_175),
        .reset(reset),
        .vga_h_sync(vga_h_sync),
        .vga_v_sync(vga_v_sync),
        .vga_r(vga_r),
        .vga_g(vga_g),
        .vga_b(vga_b)
    );

endmodule