data/full_repos/permissive/452215364/rtl/opl3/operator/envelope_generator.v
1: b'%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/envelope_generator.v:51: Cannot find include file: ../opl3.vh\n`include "../opl3.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/452215364/rtl/opl3/operator,data/full_repos/permissive/452215364/../opl3.vh\n             data/full_repos/permissive/452215364/rtl/opl3/operator,data/full_repos/permissive/452215364/../opl3.vh.v\n             data/full_repos/permissive/452215364/rtl/opl3/operator,data/full_repos/permissive/452215364/../opl3.vh.sv\n             ../opl3.vh\n             ../opl3.vh.v\n             ../opl3.vh.sv\n             obj_dir/../opl3.vh\n             obj_dir/../opl3.vh.v\n             obj_dir/../opl3.vh.sv\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/envelope_generator.v:58: Define or directive not defined: \'`BANK_NUM_WIDTH\'\n    input wire [`BANK_NUM_WIDTH-1:0] bank_num,\n                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/envelope_generator.v:59: Define or directive not defined: \'`OP_NUM_WIDTH\'\n    input wire [`OP_NUM_WIDTH-1:0] op_num,        \n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/envelope_generator.v:60: Define or directive not defined: \'`REG_ENV_WIDTH\'\n    input wire [`REG_ENV_WIDTH-1:0] ar,  \n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/envelope_generator.v:61: Define or directive not defined: \'`REG_ENV_WIDTH\'\n    input wire [`REG_ENV_WIDTH-1:0] dr,  \n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/envelope_generator.v:62: Define or directive not defined: \'`REG_ENV_WIDTH\'\n    input wire [`REG_ENV_WIDTH-1:0] sl,  \n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/envelope_generator.v:63: Define or directive not defined: \'`REG_ENV_WIDTH\'\n    input wire [`REG_ENV_WIDTH-1:0] rr,  \n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/envelope_generator.v:64: Define or directive not defined: \'`REG_TL_WIDTH\'\n    input wire [`REG_TL_WIDTH-1:0] tl,   \n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/envelope_generator.v:66: Define or directive not defined: \'`REG_KSL_WIDTH\'\n    input wire [`REG_KSL_WIDTH-1:0] ksl,  \n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/envelope_generator.v:71: Define or directive not defined: \'`REG_FNUM_WIDTH\'\n    input wire [`REG_FNUM_WIDTH-1:0] fnum,\n                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/envelope_generator.v:72: Define or directive not defined: \'`REG_BLOCK_WIDTH\'\n    input wire [`REG_BLOCK_WIDTH-1:0] block,\n                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/envelope_generator.v:75: Define or directive not defined: \'`ENV_WIDTH\'\n    output reg [`ENV_WIDTH-1:0] env = SILENCE\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/envelope_generator.v:91: Define or directive not defined: \'`NUM_BANKS\'\n    reg [3:0] state [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/envelope_generator.v:91: Define or directive not defined: \'`NUM_OPERATORS_PER_BANK\'\n    reg [3:0] state [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];\n                                     ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/envelope_generator.v:95: Define or directive not defined: \'`ENV_WIDTH\'\n    reg [`ENV_WIDTH-1:0] env_int [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];  \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/envelope_generator.v:95: Define or directive not defined: \'`NUM_BANKS\'\n    reg [`ENV_WIDTH-1:0] env_int [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];  \n                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/envelope_generator.v:95: Define or directive not defined: \'`NUM_OPERATORS_PER_BANK\'\n    reg [`ENV_WIDTH-1:0] env_int [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];  \n                                                  ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/envelope_generator.v:96: Define or directive not defined: \'`AM_VAL_WIDTH\'\n    wire [`AM_VAL_WIDTH-1:0] am_val;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/envelope_generator.v:97: Define or directive not defined: \'`REG_ENV_WIDTH\'\n    reg [`REG_ENV_WIDTH-1:0] requested_rate;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/envelope_generator.v:98: Define or directive not defined: \'`ENV_RATE_COUNTER_OVERFLOW_WIDTH\'\n    wire [`ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] rate_counter_overflow;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl3/operator/envelope_generator.v:99: Define or directive not defined: \'`ENV_WIDTH\'\n    reg signed [`ENV_WIDTH+1:0] env_tmp;  \n                ^~~~~~~~~~\n%Error: Exiting due to 21 error(s)\n'
module envelope_generator #(
    parameter SILENCE = 511
)(
    input wire clk,
    input wire sample_clk_en,
    input wire [`BANK_NUM_WIDTH-1:0] bank_num,
    input wire [`OP_NUM_WIDTH-1:0] op_num,        
    input wire [`REG_ENV_WIDTH-1:0] ar,
    input wire [`REG_ENV_WIDTH-1:0] dr,
    input wire [`REG_ENV_WIDTH-1:0] sl,
    input wire [`REG_ENV_WIDTH-1:0] rr,
    input wire [`REG_TL_WIDTH-1:0] tl,
    input wire ksr,
    input wire [`REG_KSL_WIDTH-1:0] ksl,
    input wire egt,
    input wire am,
    input wire dam,
    input wire nts,
    input wire [`REG_FNUM_WIDTH-1:0] fnum,
    input wire [`REG_BLOCK_WIDTH-1:0] block,
    input wire key_on_pulse,
    input wire key_off_pulse,
    output reg [`ENV_WIDTH-1:0] env = SILENCE
);
    localparam KSL_ADD_WIDTH = 8;
    localparam PIPELINE_DELAY = 2;
    

    parameter [3:0]
        ATTACK    = 4'b0001,
        DECAY     = 4'b0010,
        SUSTAIN   = 4'b0100,
        RELEASE   = 4'b1000;
    
    reg [3:0] state [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];
    reg [3:0] next_state;    
    
    wire [KSL_ADD_WIDTH-1:0] ksl_add;
    reg [`ENV_WIDTH-1:0] env_int [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];
    wire [`AM_VAL_WIDTH-1:0] am_val;
    reg [`REG_ENV_WIDTH-1:0] requested_rate;
    wire [`ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] rate_counter_overflow;
    reg signed [`ENV_WIDTH+1:0] env_tmp;
    reg [PIPELINE_DELAY-1:0] sample_clk_en_delayed = 0;
    
    ksl_add_rom ksl_add_rom (
        .clk(clk),
        .fnum(fnum),
        .block(block),
        .ksl(ksl),
        .ksl_add(ksl_add)
    );
    
    always @(posedge clk)
        if (key_on_pulse)
            state[bank_num][op_num] <= ATTACK;
        else if (key_off_pulse)
            state[bank_num][op_num] <= RELEASE;
        else if (sample_clk_en)
            state[bank_num][op_num] <= next_state;
        
    always @ *
        case (state[bank_num][op_num])
        ATTACK: next_state = env_int[bank_num][op_num] == 0 ? DECAY : ATTACK;
        DECAY: next_state = (env_int[bank_num][op_num] >> 4) >= sl ? SUSTAIN : DECAY;
        SUSTAIN: next_state = !egt ? RELEASE : SUSTAIN;
        RELEASE: next_state = RELEASE;
        default: next_state = RELEASE;
        endcase
            
    always @ *
        case (state[bank_num][op_num])
        ATTACK: requested_rate = ar;
        DECAY: requested_rate = dr;
        SUSTAIN: requested_rate = 0;
        RELEASE: requested_rate = rr;
        default: requested_rate = rr;
        endcase
            

    env_rate_counter env_rate_counter (
        .clk(clk),
        .sample_clk_en(sample_clk_en),
        .bank_num(bank_num),
        .op_num(op_num),      
        .ksr(ksr),
        .nts(nts),
        .fnum(fnum),
        .block(block),
        .requested_rate(requested_rate),
        .rate_counter_overflow(rate_counter_overflow)
    );
    
    always @(posedge clk) begin
        sample_clk_en_delayed <= sample_clk_en_delayed << 1;
        sample_clk_en_delayed[0] <= sample_clk_en;
    end        
    
    always @(posedge clk)
        if (sample_clk_en_delayed[PIPELINE_DELAY-1])
            if (state[bank_num][op_num] == ATTACK && rate_counter_overflow != 0 && env_int[bank_num][op_num] != 0)
                env_int[bank_num][op_num] <= env_int[bank_num][op_num] - (((env_int[bank_num][op_num]*rate_counter_overflow) >> 3) + 1);
            else if (state[bank_num][op_num] == DECAY || state[bank_num][op_num] == RELEASE)
                if (env_int[bank_num][op_num] + rate_counter_overflow > SILENCE)

                    env_int[bank_num][op_num] <= SILENCE;
                else
                    env_int[bank_num][op_num] <= env_int[bank_num][op_num] + rate_counter_overflow;     
    

    tremolo tremolo (
        .clk(clk),
        .sample_clk_en(sample_clk_en),
        .bank_num(bank_num),
        .op_num(op_num),      
        .dam(dam),
        .am_val(am_val)
    );
    
    always @ *
        if (am)
            env_tmp = env_int[bank_num][op_num] + (tl << 2) + ksl_add + am_val;
        else
            env_tmp = env_int[bank_num][op_num] + (tl << 2) + ksl_add;
            
    always @(posedge clk)
        if (env_tmp < 0)
            env <= 0;
        else if (env_tmp > SILENCE) 
            env <= SILENCE;
        else
            env <= env_tmp;
    
endmodule
module envelope_generator #(
    parameter SILENCE = 511
)(
    input wire clk,
    input wire sample_clk_en,
    input wire [`BANK_NUM_WIDTH-1:0] bank_num,
    input wire [`OP_NUM_WIDTH-1:0] op_num,        
    input wire [`REG_ENV_WIDTH-1:0] ar,
    input wire [`REG_ENV_WIDTH-1:0] dr,
    input wire [`REG_ENV_WIDTH-1:0] sl,
    input wire [`REG_ENV_WIDTH-1:0] rr,
    input wire [`REG_TL_WIDTH-1:0] tl,
    input wire ksr,
    input wire [`REG_KSL_WIDTH-1:0] ksl,
    input wire egt,
    input wire am,
    input wire dam,
    input wire nts,
    input wire [`REG_FNUM_WIDTH-1:0] fnum,
    input wire [`REG_BLOCK_WIDTH-1:0] block,
    input wire key_on_pulse,
    input wire key_off_pulse,
    output reg [`ENV_WIDTH-1:0] env = SILENCE
);

    localparam KSL_ADD_WIDTH = 8;
    localparam PIPELINE_DELAY = 2;
    

    parameter [3:0]
        ATTACK    = 4'b0001,
        DECAY     = 4'b0010,
        SUSTAIN   = 4'b0100,
        RELEASE   = 4'b1000;
    
    reg [3:0] state [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];
    reg [3:0] next_state;    
    
    wire [KSL_ADD_WIDTH-1:0] ksl_add;
    reg [`ENV_WIDTH-1:0] env_int [`NUM_BANKS-1:0][`NUM_OPERATORS_PER_BANK-1:0];
    wire [`AM_VAL_WIDTH-1:0] am_val;
    reg [`REG_ENV_WIDTH-1:0] requested_rate;
    wire [`ENV_RATE_COUNTER_OVERFLOW_WIDTH-1:0] rate_counter_overflow;
    reg signed [`ENV_WIDTH+1:0] env_tmp;
    reg [PIPELINE_DELAY-1:0] sample_clk_en_delayed = 0;
    
    ksl_add_rom ksl_add_rom (
        .clk(clk),
        .fnum(fnum),
        .block(block),
        .ksl(ksl),
        .ksl_add(ksl_add)
    );
    
    always @(posedge clk)
        if (key_on_pulse)
            state[bank_num][op_num] <= ATTACK;
        else if (key_off_pulse)
            state[bank_num][op_num] <= RELEASE;
        else if (sample_clk_en)
            state[bank_num][op_num] <= next_state;
        
    always @ *
        case (state[bank_num][op_num])
        ATTACK: next_state = env_int[bank_num][op_num] == 0 ? DECAY : ATTACK;
        DECAY: next_state = (env_int[bank_num][op_num] >> 4) >= sl ? SUSTAIN : DECAY;
        SUSTAIN: next_state = !egt ? RELEASE : SUSTAIN;
        RELEASE: next_state = RELEASE;
        default: next_state = RELEASE;
        endcase
            
    always @ *
        case (state[bank_num][op_num])
        ATTACK: requested_rate = ar;
        DECAY: requested_rate = dr;
        SUSTAIN: requested_rate = 0;
        RELEASE: requested_rate = rr;
        default: requested_rate = rr;
        endcase
            

    env_rate_counter env_rate_counter (
        .clk(clk),
        .sample_clk_en(sample_clk_en),
        .bank_num(bank_num),
        .op_num(op_num),      
        .ksr(ksr),
        .nts(nts),
        .fnum(fnum),
        .block(block),
        .requested_rate(requested_rate),
        .rate_counter_overflow(rate_counter_overflow)
    );
    
    always @(posedge clk) begin
        sample_clk_en_delayed <= sample_clk_en_delayed << 1;
        sample_clk_en_delayed[0] <= sample_clk_en;
    end        
    
    always @(posedge clk)
        if (sample_clk_en_delayed[PIPELINE_DELAY-1])
            if (state[bank_num][op_num] == ATTACK && rate_counter_overflow != 0 && env_int[bank_num][op_num] != 0)
                env_int[bank_num][op_num] <= env_int[bank_num][op_num] - (((env_int[bank_num][op_num]*rate_counter_overflow) >> 3) + 1);
            else if (state[bank_num][op_num] == DECAY || state[bank_num][op_num] == RELEASE)
                if (env_int[bank_num][op_num] + rate_counter_overflow > SILENCE)

                    env_int[bank_num][op_num] <= SILENCE;
                else
                    env_int[bank_num][op_num] <= env_int[bank_num][op_num] + rate_counter_overflow;     
    

    tremolo tremolo (
        .clk(clk),
        .sample_clk_en(sample_clk_en),
        .bank_num(bank_num),
        .op_num(op_num),      
        .dam(dam),
        .am_val(am_val)
    );
    
    always @ *
        if (am)
            env_tmp = env_int[bank_num][op_num] + (tl << 2) + ksl_add + am_val;
        else
            env_tmp = env_int[bank_num][op_num] + (tl << 2) + ksl_add;
            
    always @(posedge clk)
        if (env_tmp < 0)
            env <= 0;
        else if (env_tmp > SILENCE) 
            env <= SILENCE;
        else
            env <= env_tmp;
    
endmodule