data/full_repos/permissive/488835089/level-1/level-2/level-3/mux_2to1_tb.v
1: b'%Error: data/full_repos/permissive/488835089/level-1/level-2/level-3/mux_2to1_tb.v:1: Cannot find include file: mux_2to1.v\n`include "mux_2to1.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/488835089/level-1/level-2/level-3,data/full_repos/permissive/488835089/mux_2to1.v\n             data/full_repos/permissive/488835089/level-1/level-2/level-3,data/full_repos/permissive/488835089/mux_2to1.v.v\n             data/full_repos/permissive/488835089/level-1/level-2/level-3,data/full_repos/permissive/488835089/mux_2to1.v.sv\n             mux_2to1.v\n             mux_2to1.v.v\n             mux_2to1.v.sv\n             obj_dir/mux_2to1.v\n             obj_dir/mux_2to1.v.v\n             obj_dir/mux_2to1.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/488835089/level-1/level-2/level-3/mux_2to1_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n        SEL = 1\'b0; #10;\n                    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/488835089/level-1/level-2/level-3/mux_2to1_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n        D0 = 1\'b0; D1 = 1\'b0; #10;\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/488835089/level-1/level-2/level-3/mux_2to1_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n        D0 = 1\'b0; D1 = 1\'b1; #10;\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/488835089/level-1/level-2/level-3/mux_2to1_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n        D0 = 1\'b1; D1 = 1\'b0; #10;\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/488835089/level-1/level-2/level-3/mux_2to1_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n        D0 = 1\'b1; D1 = 1\'b1; #10;\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/488835089/level-1/level-2/level-3/mux_2to1_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n        D0 = 1\'b0; D1 = 1\'b0; #10;\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/488835089/level-1/level-2/level-3/mux_2to1_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n        SEL = 1\'b1; #10;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/488835089/level-1/level-2/level-3/mux_2to1_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n        D0 = 1\'b0; D1 = 1\'b0; #10;\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/488835089/level-1/level-2/level-3/mux_2to1_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n        D0 = 1\'b0; D1 = 1\'b1; #10;\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/488835089/level-1/level-2/level-3/mux_2to1_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n        D0 = 1\'b1; D1 = 1\'b0; #10;\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/488835089/level-1/level-2/level-3/mux_2to1_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        D0 = 1\'b1; D1 = 1\'b1; #10;\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/488835089/level-1/level-2/level-3/mux_2to1_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n        D0 = 1\'b0; D1 = 1\'b0; #10;\n                              ^\n%Error: data/full_repos/permissive/488835089/level-1/level-2/level-3/mux_2to1_tb.v:30: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("mux_2to1_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/488835089/level-1/level-2/level-3/mux_2to1_tb.v:31: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, mux_2to1_tb);\n        ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 12 warning(s)\n'
module mux_2to1_tb();
    wire OUT;
    reg SEL;
    reg D0;
    reg D1;

    mux_2to1 dut(SEL, D0, D1, OUT);

    initial begin

        SEL = 1'b0; #10;
        D0 = 1'b0; D1 = 1'b0; #10;
        D0 = 1'b0; D1 = 1'b1; #10;
        D0 = 1'b1; D1 = 1'b0; #10;
        D0 = 1'b1; D1 = 1'b1; #10;
        D0 = 1'b0; D1 = 1'b0; #10;

        SEL = 1'b1; #10;
        D0 = 1'b0; D1 = 1'b0; #10;
        D0 = 1'b0; D1 = 1'b1; #10;
        D0 = 1'b1; D1 = 1'b0; #10;
        D0 = 1'b1; D1 = 1'b1; #10;
        D0 = 1'b0; D1 = 1'b0; #10;

    end

    initial begin
        $dumpfile("mux_2to1_tb.vcd");
        $dumpvars(0, mux_2to1_tb);
    end

endmodule
module mux_2to1_tb();

    wire OUT;
    reg SEL;
    reg D0;
    reg D1;

    mux_2to1 dut(SEL, D0, D1, OUT);

    initial begin

        SEL = 1'b0; #10;
        D0 = 1'b0; D1 = 1'b0; #10;
        D0 = 1'b0; D1 = 1'b1; #10;
        D0 = 1'b1; D1 = 1'b0; #10;
        D0 = 1'b1; D1 = 1'b1; #10;
        D0 = 1'b0; D1 = 1'b0; #10;

        SEL = 1'b1; #10;
        D0 = 1'b0; D1 = 1'b0; #10;
        D0 = 1'b0; D1 = 1'b1; #10;
        D0 = 1'b1; D1 = 1'b0; #10;
        D0 = 1'b1; D1 = 1'b1; #10;
        D0 = 1'b0; D1 = 1'b0; #10;

    end

    initial begin
        $dumpfile("mux_2to1_tb.vcd");
        $dumpvars(0, mux_2to1_tb);
    end

endmodule