data/full_repos/permissive/470803657/modules/testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/470803657/modules/testbench.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #12 reset <= 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/470803657/modules/testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #5 clock <= !clock;\n  ^\n%Error: data/full_repos/permissive/470803657/modules/testbench.v:12: Cannot find file containing module: \'top\'\ntop dut (.clock (clock),\n^~~\n        ... Looked in:\n             data/full_repos/permissive/470803657/modules,data/full_repos/permissive/470803657/top\n             data/full_repos/permissive/470803657/modules,data/full_repos/permissive/470803657/top.v\n             data/full_repos/permissive/470803657/modules,data/full_repos/permissive/470803657/top.sv\n             top\n             top.v\n             top.sv\n             obj_dir/top\n             obj_dir/top.v\n             obj_dir/top.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;

reg        clock;
reg        reset;
wire [7:0] out;

top dut (.clock (clock),
         .reset (reset),
         .out   (out));

initial 
  begin
    reset <= 0;
    clock <= 0;
  end

initial
  #12 reset <= 1;

always
  #5 clock <= !clock;

endmodule
module testbench;


reg        clock;
reg        reset;
wire [7:0] out;

top dut (.clock (clock),
         .reset (reset),
         .out   (out));

initial 
  begin
    reset <= 0;
    clock <= 0;
  end

initial
  #12 reset <= 1;

always
  #5 clock <= !clock;

endmodule