data/full_repos/permissive/484316383/rtl/Next186/Next186_ALU.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/484316383/rtl/Next186/Next186_ALU.v:297: Multiple top level modules\n                                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                     : ... Top module \'Next186_ALU\'\nmodule Next186_ALU(\n       ^~~~~~~~~~~\n                                                                                     : ... Top module \'Next186_EA\'\nmodule Next186_EA(\n       ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/484316383/rtl/Next186/Next186_ALU.v:119: Operator ADD expects 5 bits on the RHS, but RHS\'s VARREF \'SCIN\' generates 1 bits.\n                                                                                  : ... In instance Next186_ALU\n assign {AF, SUMOUT[3:0]} = SUMOP1[3:0] + SUMOP2[3:0] + SCIN;\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/484316383/rtl/Next186/Next186_ALU.v:120: Operator ADD expects 5 bits on the RHS, but RHS\'s VARREF \'AF\' generates 1 bits.\n                                                                                  : ... In instance Next186_ALU\n assign {SC8OUT, SUMOUT[7:4]} = SUMOP1[7:4] + SUMOP2[7:4] + AF;\n                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/484316383/rtl/Next186/Next186_ALU.v:121: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'SC8OUT\' generates 1 bits.\n                                                                                  : ... In instance Next186_ALU\n assign {SC16OUT, SUMOUT[15:8]} = SUMOP1[15:8] + SUMOP2[15:8] + SC8OUT;\n                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/484316383/rtl/Next186/Next186_ALU.v:132: Operator ASSIGNW expects 18 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 25 bits.\n                                                                                  : ... In instance Next186_ALU\n wire [17:0]SHBAR = (EXOP[0] ? {1\'bx, SHEX, WORD ? RA[15:8]: SHEX, RA[7:0]} : {RA, SHEX, 1\'bx}) >> SCOUNT;\n                  ^\n%Error: Exiting due to 5 warning(s)\n'
module Next186_ALU(
    input [15:0] RA,
    input [15:0] RB,
	 input [15:0] TMP16,
	 input [15:0] FETCH23,
	 input [15:0]FIN,
	 input [4:0]ALUOP,
	 input [2:0]EXOP,
	 input [3:0]FLAGOP,
	 input WORD,
	 input INC2,
	 output reg [15:0]FOUT,
    output reg [15:0]ALUOUT,
    output [15:0]ALUOUTA,
	 output reg ALUCONT,
	 output NULLSHIFT,
	 output COUT,
	 input [2:0]STAGE,
	 input CLK
    );

	reg CPLOP2;	
	wire [15:0]SUMOP1 = ALUOP[3:1] == 3'b101 ? 16'h0000 : RA;
	reg [15:0]SUMOP21;
	wire [15:0]SUMOP2 = CPLOP2 ? ~SUMOP21 : SUMOP21;
	wire SCIN1 = ALUOP[3:1] == 3'b001 ? FIN[0] : ALUOP[3:0] == 4'b1010 ? 1'b1 : 1'b0;
	wire SCIN = CPLOP2 ? ~SCIN1 : SCIN1;
	wire SC16OUT;
	wire SC8OUT;
	wire AF;
	wire [15:0]SUMOUT;
	wire parity = ~^ALUOUT[7:0];
	wire zero8 = ~|ALUOUT[7:0];
	wire zero = ~|ALUOUT[15:0];
	wire overflow8 = (SUMOP1[7] & SUMOP2[7] & !SUMOUT[7]) | (!SUMOP1[7] & !SUMOP2[7] & SUMOUT[7]);
	wire overflow = (SUMOP1[15] & SUMOP2[15] & !SUMOUT[15]) | (!SUMOP1[15] & !SUMOP2[15] & SUMOUT[15]);
	wire LONIBBLE = (RA[3:0] > 4'h9)  || FIN[4];
	wire HINIBBLE = (RA[7:0] > 8'h99) || FIN[0];


	assign {AF, SUMOUT[3:0]} = SUMOP1[3:0] + SUMOP2[3:0] + SCIN;
	assign {SC8OUT, SUMOUT[7:4]} = SUMOP1[7:4] + SUMOP2[7:4] + AF;
	assign {SC16OUT, SUMOUT[15:8]} = SUMOP1[15:8] + SUMOP2[15:8] + SC8OUT;
	assign COUT = (WORD ? SC16OUT : SC8OUT) ^ CPLOP2;
	assign ALUOUTA = ALUOP == 5'b11111 ? RB : SUMOUT;


	reg [4:0]SHNOPT;
	wire [4:0]SHN = {STAGE[2:1] ^ SHNOPT[4:3], SHNOPT[2:0]};
	assign NULLSHIFT = ~|SHNOPT;
	wire [2:0]COUNT = |SHN[4:3] ? 0 : SHN[2:0];
	wire [2:0]SCOUNT = (EXOP[0] ? COUNT[2:0] : 3'b000) - (EXOP[0] ? 3'b001 : COUNT[2:0]);
	reg [7:0]SHEX;
	wire [17:0]SHBAR = (EXOP[0] ? {1'bx, SHEX, WORD ? RA[15:8]: SHEX, RA[7:0]} : {RA, SHEX, 1'bx}) >> SCOUNT;


	wire signed [16:0]MULOP1 = WORD ? {ALUOP[0] & TMP16[15], TMP16} : {ALUOP[0] ? {9{TMP16[7]}} : 9'b000000000, TMP16[7:0]};
	wire signed [16:0]MULOP2 = WORD ? {ALUOP[0] & FETCH23[15], FETCH23} : {ALUOP[0] ? {9{FETCH23[7]}} : 9'b000000000, FETCH23[7:0]};
	wire signed [31:0]MUL = MULOP1 * MULOP2;
	
	always @* begin
		FOUT[15:8] = {4'bxxxx, WORD ? overflow : overflow8, FIN[10:8]};
		FOUT[7] = WORD ? ALUOUT[15] : ALUOUT[7];
		FOUT[6] = WORD ? zero : zero8;
		FOUT[5] = 1'bx;
		FOUT[4] = AF ^ CPLOP2;
		FOUT[3] = 1'bx;
		FOUT[2] = parity;
		FOUT[1] = 1'bx;
		FOUT[0] = COUT;
		ALUOUT = 16'hxxxx;
		ALUCONT = 1'bx;

		case(ALUOP[3:0])
			4'b0000, 4'b0010, 4'b1000, 4'b1100, 4'b1110: CPLOP2 = 1'b0;
			default: CPLOP2 = 1'b1;
		endcase

		case(ALUOP[3:0])
			4'b1000, 4'b1001:	SUMOP21 = INC2 && WORD ? 2 : 1;
			4'b1100, 4'b1101:	SUMOP21 = {9'b000000000, HINIBBLE, HINIBBLE, 2'b00, LONIBBLE, LONIBBLE, 1'b0};
			4'b1110, 4'b1111:	SUMOP21 = {7'b0000000, LONIBBLE, 5'b00000, LONIBBLE, LONIBBLE, 1'b0};
			default: SUMOP21 = RB;
		endcase
	
		if(ALUOP[0]) 
			case({WORD, EXOP[2:1]})
				3'b000:	SHNOPT = {2'b00, RB[2:0]};
				3'b001, 3'b101:  SHNOPT = RB[4:0];
				3'b010, 3'b011: SHNOPT = |RB[4:3] ? 5'b01000 : RB[4:0];
				3'b100:	SHNOPT = {1'b0, RB[3:0]};
				3'b110, 3'b111: SHNOPT = RB[4] ? 5'b10000 : RB[4:0];	
			endcase
		else SHNOPT = 5'b00001;
		
		case({WORD, EXOP})
			4'b1000:	SHEX = RA[15:8];
			4'b0010: SHEX = {FIN[0], RA[7:1]};
			4'b0011, 4'b1011:	SHEX = {RA[6:0], FIN[0]};
			4'b0111:	SHEX = {8{RA[7]}};
			4'b0000, 4'b0001, 4'b1001:	SHEX = RA[7:0];
			4'b1010: SHEX = {FIN[0], RA[15:9]};
			4'b1111:	SHEX = {8{RA[15]}};
			default: SHEX = 8'h00;
		endcase

		case(ALUOP)
			5'b00000, 5'b00010, 5'b00011, 5'b00101, 5'b00111, 5'b01010, 5'b01011: ALUOUT = SUMOUT;
			5'b00001: begin
				ALUOUT = RA | RB;
				FOUT[0] = 1'b0;
				FOUT[11] = 1'b0;
				FOUT[4] = FIN[4];
			end
			5'b00100: begin
				ALUOUT = RA & RB;
				FOUT[0] = 1'b0;
				FOUT[11] = 1'b0;
				FOUT[4] = FIN[4];
			end
			5'b00110: begin
				ALUOUT = RA ^ RB;
				FOUT[0] = 1'b0;
				FOUT[11] = 1'b0;
				FOUT[4] = FIN[4];
			end
			5'b01000, 5'b01001: begin
				ALUOUT = SUMOUT;
				FOUT[0] = FIN[0];
			end
			5'b01100, 5'b01101: begin
				ALUOUT = SUMOUT;
				FOUT[0] = HINIBBLE;
				FOUT[4] = LONIBBLE;
			end
			5'b01110, 5'b01111: begin
				ALUOUT = {SUMOUT[15:8], 4'b0000, SUMOUT[3:0]};
				FOUT[0] = LONIBBLE;
				FOUT[4] = LONIBBLE;
			end
			5'b10000, 5'b10001 : begin
				ALUOUT = STAGE[1] ? MUL[31:16] : MUL[15:0];

				FOUT[0] = WORD ? MUL[31:16] != {16{MUL[15] & ALUOP[0]}} : MUL[15:8] != {8{MUL[7] & ALUOP[0]}}; 
				FOUT[11] = FOUT[0];
			end
			5'b11001: begin
				FOUT[11:8] = FIN[11:8];
				FOUT[7] = FIN[7];
				FOUT[6] = FIN[6];
				FOUT[4] = FIN[4];
				FOUT[2] = FIN[2];
				FOUT[0] = FIN[0];
				case(FLAGOP)
					4'b1000: FOUT[0] = 1'b0;
					4'b0101: FOUT[0] = !FIN[0];
					4'b1001: FOUT[0] = 1'b1;
					4'b1100: FOUT[10] = 1'b0;
					4'b1101: FOUT[10] = 1'b1;
					4'b1010:	FOUT[9] = 1'b0;
					default: FOUT[9] = 1'b1;
				endcase
			end
			5'b11010: ALUOUT[7:0] = {8{RB[7]}};
			5'b11011: ALUOUT[15:0] = {16{RB[15]}};
			5'b11100, 5'b11101: begin
				ALUOUT = SHBAR[16:1];
				FOUT[0] = EXOP[0] ? SHBAR[0] : WORD ? SHBAR[17] : SHBAR[9];
				FOUT[11] = WORD ? RA[15] ^ ALUOUT[15] : RA[7] ^ ALUOUT[7];
				if(!EXOP[2]) begin
					FOUT[7] = FIN[7];
					FOUT[6] = FIN[6];
					FOUT[4] = FIN[4];
					FOUT[2] = FIN[2];
				end
				case({SHN[4:3], STAGE[2:1]})
					4'b0100, 4'b1101, 4'b0110: ALUCONT = |SHN[2:0];
					4'b1000, 4'b1100, 4'b1001: ALUCONT = 1'b1;
					default: ALUCONT = 1'b0;
				endcase
			end

			5'b11110:	begin
				ALUOUT = FIN;
				FOUT[11] = FIN[11];
				FOUT[9] = 1'b0;
				FOUT[8] = 1'b0;
				FOUT[7] = FIN[7];
				FOUT[6] = FIN[6];
				FOUT[4] = FIN[4];
				FOUT[2] = FIN[2];
				FOUT[0] = FIN[0];
			end
			5'b11111:	begin
				ALUOUT = RB;
				FOUT = {WORD ? RA[15:8] : FIN[15:8], RA[7:0]};
			end
		endcase
	end

endmodule
module Next186_ALU(
    input [15:0] RA,
    input [15:0] RB,
	 input [15:0] TMP16,
	 input [15:0] FETCH23,
	 input [15:0]FIN,
	 input [4:0]ALUOP,
	 input [2:0]EXOP,
	 input [3:0]FLAGOP,
	 input WORD,
	 input INC2,
	 output reg [15:0]FOUT,
    output reg [15:0]ALUOUT,
    output [15:0]ALUOUTA,
	 output reg ALUCONT,
	 output NULLSHIFT,
	 output COUT,
	 input [2:0]STAGE,
	 input CLK
    );


	reg CPLOP2;	
	wire [15:0]SUMOP1 = ALUOP[3:1] == 3'b101 ? 16'h0000 : RA;
	reg [15:0]SUMOP21;
	wire [15:0]SUMOP2 = CPLOP2 ? ~SUMOP21 : SUMOP21;
	wire SCIN1 = ALUOP[3:1] == 3'b001 ? FIN[0] : ALUOP[3:0] == 4'b1010 ? 1'b1 : 1'b0;
	wire SCIN = CPLOP2 ? ~SCIN1 : SCIN1;
	wire SC16OUT;
	wire SC8OUT;
	wire AF;
	wire [15:0]SUMOUT;
	wire parity = ~^ALUOUT[7:0];
	wire zero8 = ~|ALUOUT[7:0];
	wire zero = ~|ALUOUT[15:0];
	wire overflow8 = (SUMOP1[7] & SUMOP2[7] & !SUMOUT[7]) | (!SUMOP1[7] & !SUMOP2[7] & SUMOUT[7]);
	wire overflow = (SUMOP1[15] & SUMOP2[15] & !SUMOUT[15]) | (!SUMOP1[15] & !SUMOP2[15] & SUMOUT[15]);
	wire LONIBBLE = (RA[3:0] > 4'h9)  || FIN[4];
	wire HINIBBLE = (RA[7:0] > 8'h99) || FIN[0];


	assign {AF, SUMOUT[3:0]} = SUMOP1[3:0] + SUMOP2[3:0] + SCIN;
	assign {SC8OUT, SUMOUT[7:4]} = SUMOP1[7:4] + SUMOP2[7:4] + AF;
	assign {SC16OUT, SUMOUT[15:8]} = SUMOP1[15:8] + SUMOP2[15:8] + SC8OUT;
	assign COUT = (WORD ? SC16OUT : SC8OUT) ^ CPLOP2;
	assign ALUOUTA = ALUOP == 5'b11111 ? RB : SUMOUT;


	reg [4:0]SHNOPT;
	wire [4:0]SHN = {STAGE[2:1] ^ SHNOPT[4:3], SHNOPT[2:0]};
	assign NULLSHIFT = ~|SHNOPT;
	wire [2:0]COUNT = |SHN[4:3] ? 0 : SHN[2:0];
	wire [2:0]SCOUNT = (EXOP[0] ? COUNT[2:0] : 3'b000) - (EXOP[0] ? 3'b001 : COUNT[2:0]);
	reg [7:0]SHEX;
	wire [17:0]SHBAR = (EXOP[0] ? {1'bx, SHEX, WORD ? RA[15:8]: SHEX, RA[7:0]} : {RA, SHEX, 1'bx}) >> SCOUNT;


	wire signed [16:0]MULOP1 = WORD ? {ALUOP[0] & TMP16[15], TMP16} : {ALUOP[0] ? {9{TMP16[7]}} : 9'b000000000, TMP16[7:0]};
	wire signed [16:0]MULOP2 = WORD ? {ALUOP[0] & FETCH23[15], FETCH23} : {ALUOP[0] ? {9{FETCH23[7]}} : 9'b000000000, FETCH23[7:0]};
	wire signed [31:0]MUL = MULOP1 * MULOP2;
	
	always @* begin
		FOUT[15:8] = {4'bxxxx, WORD ? overflow : overflow8, FIN[10:8]};
		FOUT[7] = WORD ? ALUOUT[15] : ALUOUT[7];
		FOUT[6] = WORD ? zero : zero8;
		FOUT[5] = 1'bx;
		FOUT[4] = AF ^ CPLOP2;
		FOUT[3] = 1'bx;
		FOUT[2] = parity;
		FOUT[1] = 1'bx;
		FOUT[0] = COUT;
		ALUOUT = 16'hxxxx;
		ALUCONT = 1'bx;

		case(ALUOP[3:0])
			4'b0000, 4'b0010, 4'b1000, 4'b1100, 4'b1110: CPLOP2 = 1'b0;
			default: CPLOP2 = 1'b1;
		endcase

		case(ALUOP[3:0])
			4'b1000, 4'b1001:	SUMOP21 = INC2 && WORD ? 2 : 1;
			4'b1100, 4'b1101:	SUMOP21 = {9'b000000000, HINIBBLE, HINIBBLE, 2'b00, LONIBBLE, LONIBBLE, 1'b0};
			4'b1110, 4'b1111:	SUMOP21 = {7'b0000000, LONIBBLE, 5'b00000, LONIBBLE, LONIBBLE, 1'b0};
			default: SUMOP21 = RB;
		endcase
	
		if(ALUOP[0]) 
			case({WORD, EXOP[2:1]})
				3'b000:	SHNOPT = {2'b00, RB[2:0]};
				3'b001, 3'b101:  SHNOPT = RB[4:0];
				3'b010, 3'b011: SHNOPT = |RB[4:3] ? 5'b01000 : RB[4:0];
				3'b100:	SHNOPT = {1'b0, RB[3:0]};
				3'b110, 3'b111: SHNOPT = RB[4] ? 5'b10000 : RB[4:0];	
			endcase
		else SHNOPT = 5'b00001;
		
		case({WORD, EXOP})
			4'b1000:	SHEX = RA[15:8];
			4'b0010: SHEX = {FIN[0], RA[7:1]};
			4'b0011, 4'b1011:	SHEX = {RA[6:0], FIN[0]};
			4'b0111:	SHEX = {8{RA[7]}};
			4'b0000, 4'b0001, 4'b1001:	SHEX = RA[7:0];
			4'b1010: SHEX = {FIN[0], RA[15:9]};
			4'b1111:	SHEX = {8{RA[15]}};
			default: SHEX = 8'h00;
		endcase

		case(ALUOP)
			5'b00000, 5'b00010, 5'b00011, 5'b00101, 5'b00111, 5'b01010, 5'b01011: ALUOUT = SUMOUT;
			5'b00001: begin
				ALUOUT = RA | RB;
				FOUT[0] = 1'b0;
				FOUT[11] = 1'b0;
				FOUT[4] = FIN[4];
			end
			5'b00100: begin
				ALUOUT = RA & RB;
				FOUT[0] = 1'b0;
				FOUT[11] = 1'b0;
				FOUT[4] = FIN[4];
			end
			5'b00110: begin
				ALUOUT = RA ^ RB;
				FOUT[0] = 1'b0;
				FOUT[11] = 1'b0;
				FOUT[4] = FIN[4];
			end
			5'b01000, 5'b01001: begin
				ALUOUT = SUMOUT;
				FOUT[0] = FIN[0];
			end
			5'b01100, 5'b01101: begin
				ALUOUT = SUMOUT;
				FOUT[0] = HINIBBLE;
				FOUT[4] = LONIBBLE;
			end
			5'b01110, 5'b01111: begin
				ALUOUT = {SUMOUT[15:8], 4'b0000, SUMOUT[3:0]};
				FOUT[0] = LONIBBLE;
				FOUT[4] = LONIBBLE;
			end
			5'b10000, 5'b10001 : begin
				ALUOUT = STAGE[1] ? MUL[31:16] : MUL[15:0];

				FOUT[0] = WORD ? MUL[31:16] != {16{MUL[15] & ALUOP[0]}} : MUL[15:8] != {8{MUL[7] & ALUOP[0]}}; 
				FOUT[11] = FOUT[0];
			end
			5'b11001: begin
				FOUT[11:8] = FIN[11:8];
				FOUT[7] = FIN[7];
				FOUT[6] = FIN[6];
				FOUT[4] = FIN[4];
				FOUT[2] = FIN[2];
				FOUT[0] = FIN[0];
				case(FLAGOP)
					4'b1000: FOUT[0] = 1'b0;
					4'b0101: FOUT[0] = !FIN[0];
					4'b1001: FOUT[0] = 1'b1;
					4'b1100: FOUT[10] = 1'b0;
					4'b1101: FOUT[10] = 1'b1;
					4'b1010:	FOUT[9] = 1'b0;
					default: FOUT[9] = 1'b1;
				endcase
			end
			5'b11010: ALUOUT[7:0] = {8{RB[7]}};
			5'b11011: ALUOUT[15:0] = {16{RB[15]}};
			5'b11100, 5'b11101: begin
				ALUOUT = SHBAR[16:1];
				FOUT[0] = EXOP[0] ? SHBAR[0] : WORD ? SHBAR[17] : SHBAR[9];
				FOUT[11] = WORD ? RA[15] ^ ALUOUT[15] : RA[7] ^ ALUOUT[7];
				if(!EXOP[2]) begin
					FOUT[7] = FIN[7];
					FOUT[6] = FIN[6];
					FOUT[4] = FIN[4];
					FOUT[2] = FIN[2];
				end
				case({SHN[4:3], STAGE[2:1]})
					4'b0100, 4'b1101, 4'b0110: ALUCONT = |SHN[2:0];
					4'b1000, 4'b1100, 4'b1001: ALUCONT = 1'b1;
					default: ALUCONT = 1'b0;
				endcase
			end

			5'b11110:	begin
				ALUOUT = FIN;
				FOUT[11] = FIN[11];
				FOUT[9] = 1'b0;
				FOUT[8] = 1'b0;
				FOUT[7] = FIN[7];
				FOUT[6] = FIN[6];
				FOUT[4] = FIN[4];
				FOUT[2] = FIN[2];
				FOUT[0] = FIN[0];
			end
			5'b11111:	begin
				ALUOUT = RB;
				FOUT = {WORD ? RA[15:8] : FIN[15:8], RA[7:0]};
			end
		endcase
	end

endmodule