data/full_repos/permissive/469312749/FINAL1/work/verilog/bool_16_13.v
data/verilator_xmls/0f36cb6d-2840-4033-9e66-5ad89a8fbc0a.xml
module bool_16_13 (
    input [15:0] x,
    input [15:0] y,
    input [3:0] boolAlufn,
    output reg [15:0] boolOut
  );
  
  
  
  reg [15:0] temp;
  
  always @* begin
    
    case (boolAlufn)
      4'h0: begin
        temp = x | y;
      end
      4'h1: begin
        temp = x & y;
      end
      4'h2: begin
        temp = x ^ y;
      end
      4'h3: begin
        temp = x;
      end
      4'h4: begin
        temp = y;
      end
      4'h8: begin
        temp = ~(x | y);
      end
      4'h9: begin
        temp = ~(x & y);
      end
      4'hb: begin
        temp = ~x;
      end
      4'hc: begin
        temp = ~y;
      end
      default: begin
        temp = 16'h0000;
      end
    endcase
    boolOut = temp;
  end
endmodule
module bool_16_13 (
    input [15:0] x,
    input [15:0] y,
    input [3:0] boolAlufn,
    output reg [15:0] boolOut
  );

  
  
  
  reg [15:0] temp;
  
  always @* begin
    
    case (boolAlufn)
      4'h0: begin
        temp = x | y;
      end
      4'h1: begin
        temp = x & y;
      end
      4'h2: begin
        temp = x ^ y;
      end
      4'h3: begin
        temp = x;
      end
      4'h4: begin
        temp = y;
      end
      4'h8: begin
        temp = ~(x | y);
      end
      4'h9: begin
        temp = ~(x & y);
      end
      4'hb: begin
        temp = ~x;
      end
      4'hc: begin
        temp = ~y;
      end
      default: begin
        temp = 16'h0000;
      end
    endcase
    boolOut = temp;
  end
endmodule