data/full_repos/permissive/459497172/verilog/rtl/sar_adc/adc_reg.sv
1: b"%Error: data/full_repos/permissive/459497172/verilog/rtl/sar_adc/adc_reg.sv:211: Cannot find file containing module: 'gen_32b_reg'\ngen_32b_reg  #(32'h0) u_reg_0 (\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/459497172/verilog/rtl/sar_adc,data/full_repos/permissive/459497172/gen_32b_reg\n             data/full_repos/permissive/459497172/verilog/rtl/sar_adc,data/full_repos/permissive/459497172/gen_32b_reg.v\n             data/full_repos/permissive/459497172/verilog/rtl/sar_adc,data/full_repos/permissive/459497172/gen_32b_reg.sv\n             gen_32b_reg\n             gen_32b_reg.v\n             gen_32b_reg.sv\n             obj_dir/gen_32b_reg\n             obj_dir/gen_32b_reg.v\n             obj_dir/gen_32b_reg.sv\n%Error: Exiting due to 1 error(s)\n"
module adc_reg (

        input logic             mclk,
        input logic             reset_n,


        input logic             reg_cs,
        input logic             reg_wr,
        input logic [7:0]       reg_addr,
        input logic [31:0]      reg_wdata,
        input logic [3:0]       reg_be,


        output logic [31:0]     reg_rdata,
        output logic            reg_ack,

	input  logic            pulse1m_mclk,

       output logic            start_conv,
       output logic [2:0]      adc_ch_no,           
       input  logic            conv_done,
       input  logic [7:0]      adc_result


        );







logic           sw_rd_en;
logic           sw_wr_en;
logic  [3:0]    sw_addr ;
logic  [3:0]    wr_be   ;
logic  [31:0]   sw_reg_wdata;

logic           reg_cs_l    ;
logic           reg_cs_2l    ;


logic [31:0]    reg_0;
logic [31:0]    reg_1;
logic [31:0]    reg_2;
logic [31:0]    reg_3;
logic [31:0]    reg_4;
logic [31:0]    reg_5;
logic [31:0]    reg_6;
logic [31:0]    reg_7;
logic [31:0]    reg_out;








always @ (posedge mclk or negedge reset_n)
begin 
   if (reset_n == 1'b0)
   begin
    sw_addr       <= '0;
    sw_rd_en      <= '0;
    sw_wr_en      <= '0;
    sw_reg_wdata  <= '0;
    wr_be         <= '0;
    reg_cs_l      <= '0;
    reg_cs_2l     <= '0;
  end else begin
    sw_addr       <= reg_addr [5:2];
    sw_rd_en      <= reg_cs & !reg_wr;
    sw_wr_en      <= reg_cs & reg_wr;
    sw_reg_wdata  <= reg_wdata;
    wr_be         <= reg_be;
    reg_cs_l      <= reg_cs;
    reg_cs_2l     <= reg_cs_l;
  end
end






always @ (posedge mclk or negedge reset_n)
begin : preg_out_Seq
   if (reset_n == 1'b0) begin
      reg_rdata [31:0]  <= 32'h0000_0000;
      reg_ack           <= 1'b0;
   end else if (sw_rd_en && !reg_ack && !reg_cs_2l) begin
      reg_rdata [31:0]  <= reg_out [31:0];
      reg_ack           <= 1'b1;
   end else if (sw_wr_en && !reg_ack && !reg_cs_2l) begin 
      reg_ack           <= 1'b1;
   end else begin
      reg_ack        <= 1'b0;
   end
end





wire   sw_wr_en_0 = sw_wr_en & (sw_addr == 4'h0);
wire   sw_rd_en_0 = sw_rd_en & (sw_addr == 4'h0);
wire   sw_wr_en_1 = sw_wr_en & (sw_addr == 4'h1);
wire   sw_rd_en_1 = sw_rd_en & (sw_addr == 4'h1);
wire   sw_wr_en_2 = sw_wr_en & (sw_addr == 4'h2);
wire   sw_rd_en_2 = sw_rd_en & (sw_addr == 4'h2);
wire   sw_wr_en_3 = sw_wr_en & (sw_addr == 4'h3);
wire   sw_rd_en_3 = sw_rd_en & (sw_addr == 4'h3);
wire   sw_wr_en_4 = sw_wr_en & (sw_addr == 4'h4);
wire   sw_rd_en_4 = sw_rd_en & (sw_addr == 4'h4);
wire   sw_wr_en_5 = sw_wr_en & (sw_addr == 4'h5);
wire   sw_rd_en_5 = sw_rd_en & (sw_addr == 4'h5);
wire   sw_wr_en_6 = sw_wr_en & (sw_addr == 4'h6);
wire   sw_rd_en_6 = sw_rd_en & (sw_addr == 4'h6);
wire   sw_wr_en_7 = sw_wr_en & (sw_addr == 4'h7);
wire   sw_rd_en_7 = sw_rd_en & (sw_addr == 4'h7);

always @( *)
begin : preg_sel_Com

  reg_out [31:0] = 32'd0;

  case (sw_addr [3:0])
    4'b0000 : reg_out [31:0] = reg_0 [31:0];     
    4'b0001 : reg_out [31:0] = {24'h0,reg_1 [7:0]};    
    4'b0010 : reg_out [31:0] = {24'h0,reg_2 [7:0]};     
    4'b0011 : reg_out [31:0] = {24'h0,reg_3 [7:0]};    
    4'b0100 : reg_out [31:0] = {24'h0,reg_4 [7:0]};    
    4'b0101 : reg_out [31:0] = {24'h0,reg_5 [7:0]};    
    4'b0110 : reg_out [31:0] = {24'h0,reg_6 [7:0]};    
    default : reg_out [31:0] = 'h0;
  endcase
end






logic [5:0] cfg_adc_enb = reg_0[5:0];

gen_32b_reg  #(32'h0) u_reg_0	(

	      .reset_n    (reset_n     ),
	      .clk        (mclk          ),
	      .cs         (sw_wr_en_0    ),
	      .we         (wr_be         ),		 
	      .data_in    (sw_reg_wdata  ),
	      

	      .data_out   (reg_0        )
	      );


always @(posedge mclk or negedge reset_n)
begin
   if(~reset_n) begin
      reg_1[7:0]   <= 8'h0;
      reg_2[7:0]   <= 8'h0;
      reg_3[7:0]   <= 8'h0;
      reg_4[7:0]   <= 8'h0;
      reg_5[7:0]   <= 8'h0;
      reg_6[7:0]   <= 8'h0;
      start_conv   <= '0;
      adc_ch_no    <= '0;
   end else begin
      if(cfg_adc_enb[0] && pulse1m_mclk) begin
	 if(start_conv && conv_done) begin
            start_conv <= 0;
	    case(adc_ch_no)
	    3'b000: reg_1[7:0] <= adc_result;
	    3'b001: reg_2[7:0] <= adc_result;
	    3'b010: reg_3[7:0] <= adc_result;
	    3'b011: reg_4[7:0] <= adc_result;
	    3'b100: reg_5[7:0] <= adc_result;
	    3'b101: reg_6[7:0] <= adc_result;
	    endcase
         end
      end else begin
	 start_conv <= 1;
	 if(adc_ch_no == 5) begin
	    adc_ch_no <= 0;
         end else begin
	    adc_ch_no    <= adc_ch_no+1;
	 end
      end
   end
end




endmodule
module adc_reg (

        input logic             mclk,
        input logic             reset_n,


        input logic             reg_cs,
        input logic             reg_wr,
        input logic [7:0]       reg_addr,
        input logic [31:0]      reg_wdata,
        input logic [3:0]       reg_be,


        output logic [31:0]     reg_rdata,
        output logic            reg_ack,

	input  logic            pulse1m_mclk,

       output logic            start_conv,
       output logic [2:0]      adc_ch_no,           
       input  logic            conv_done,
       input  logic [7:0]      adc_result


        );








logic           sw_rd_en;
logic           sw_wr_en;
logic  [3:0]    sw_addr ;
logic  [3:0]    wr_be   ;
logic  [31:0]   sw_reg_wdata;

logic           reg_cs_l    ;
logic           reg_cs_2l    ;


logic [31:0]    reg_0;
logic [31:0]    reg_1;
logic [31:0]    reg_2;
logic [31:0]    reg_3;
logic [31:0]    reg_4;
logic [31:0]    reg_5;
logic [31:0]    reg_6;
logic [31:0]    reg_7;
logic [31:0]    reg_out;








always @ (posedge mclk or negedge reset_n)
begin 
   if (reset_n == 1'b0)
   begin
    sw_addr       <= '0;
    sw_rd_en      <= '0;
    sw_wr_en      <= '0;
    sw_reg_wdata  <= '0;
    wr_be         <= '0;
    reg_cs_l      <= '0;
    reg_cs_2l     <= '0;
  end else begin
    sw_addr       <= reg_addr [5:2];
    sw_rd_en      <= reg_cs & !reg_wr;
    sw_wr_en      <= reg_cs & reg_wr;
    sw_reg_wdata  <= reg_wdata;
    wr_be         <= reg_be;
    reg_cs_l      <= reg_cs;
    reg_cs_2l     <= reg_cs_l;
  end
end






always @ (posedge mclk or negedge reset_n)
begin : preg_out_Seq
   if (reset_n == 1'b0) begin
      reg_rdata [31:0]  <= 32'h0000_0000;
      reg_ack           <= 1'b0;
   end else if (sw_rd_en && !reg_ack && !reg_cs_2l) begin
      reg_rdata [31:0]  <= reg_out [31:0];
      reg_ack           <= 1'b1;
   end else if (sw_wr_en && !reg_ack && !reg_cs_2l) begin 
      reg_ack           <= 1'b1;
   end else begin
      reg_ack        <= 1'b0;
   end
end





wire   sw_wr_en_0 = sw_wr_en & (sw_addr == 4'h0);
wire   sw_rd_en_0 = sw_rd_en & (sw_addr == 4'h0);
wire   sw_wr_en_1 = sw_wr_en & (sw_addr == 4'h1);
wire   sw_rd_en_1 = sw_rd_en & (sw_addr == 4'h1);
wire   sw_wr_en_2 = sw_wr_en & (sw_addr == 4'h2);
wire   sw_rd_en_2 = sw_rd_en & (sw_addr == 4'h2);
wire   sw_wr_en_3 = sw_wr_en & (sw_addr == 4'h3);
wire   sw_rd_en_3 = sw_rd_en & (sw_addr == 4'h3);
wire   sw_wr_en_4 = sw_wr_en & (sw_addr == 4'h4);
wire   sw_rd_en_4 = sw_rd_en & (sw_addr == 4'h4);
wire   sw_wr_en_5 = sw_wr_en & (sw_addr == 4'h5);
wire   sw_rd_en_5 = sw_rd_en & (sw_addr == 4'h5);
wire   sw_wr_en_6 = sw_wr_en & (sw_addr == 4'h6);
wire   sw_rd_en_6 = sw_rd_en & (sw_addr == 4'h6);
wire   sw_wr_en_7 = sw_wr_en & (sw_addr == 4'h7);
wire   sw_rd_en_7 = sw_rd_en & (sw_addr == 4'h7);

always @( *)
begin : preg_sel_Com

  reg_out [31:0] = 32'd0;

  case (sw_addr [3:0])
    4'b0000 : reg_out [31:0] = reg_0 [31:0];     
    4'b0001 : reg_out [31:0] = {24'h0,reg_1 [7:0]};    
    4'b0010 : reg_out [31:0] = {24'h0,reg_2 [7:0]};     
    4'b0011 : reg_out [31:0] = {24'h0,reg_3 [7:0]};    
    4'b0100 : reg_out [31:0] = {24'h0,reg_4 [7:0]};    
    4'b0101 : reg_out [31:0] = {24'h0,reg_5 [7:0]};    
    4'b0110 : reg_out [31:0] = {24'h0,reg_6 [7:0]};    
    default : reg_out [31:0] = 'h0;
  endcase
end






logic [5:0] cfg_adc_enb = reg_0[5:0];

gen_32b_reg  #(32'h0) u_reg_0	(

	      .reset_n    (reset_n     ),
	      .clk        (mclk          ),
	      .cs         (sw_wr_en_0    ),
	      .we         (wr_be         ),		 
	      .data_in    (sw_reg_wdata  ),
	      

	      .data_out   (reg_0        )
	      );


always @(posedge mclk or negedge reset_n)
begin
   if(~reset_n) begin
      reg_1[7:0]   <= 8'h0;
      reg_2[7:0]   <= 8'h0;
      reg_3[7:0]   <= 8'h0;
      reg_4[7:0]   <= 8'h0;
      reg_5[7:0]   <= 8'h0;
      reg_6[7:0]   <= 8'h0;
      start_conv   <= '0;
      adc_ch_no    <= '0;
   end else begin
      if(cfg_adc_enb[0] && pulse1m_mclk) begin
	 if(start_conv && conv_done) begin
            start_conv <= 0;
	    case(adc_ch_no)
	    3'b000: reg_1[7:0] <= adc_result;
	    3'b001: reg_2[7:0] <= adc_result;
	    3'b010: reg_3[7:0] <= adc_result;
	    3'b011: reg_4[7:0] <= adc_result;
	    3'b100: reg_5[7:0] <= adc_result;
	    3'b101: reg_6[7:0] <= adc_result;
	    endcase
         end
      end else begin
	 start_conv <= 1;
	 if(adc_ch_no == 5) begin
	    adc_ch_no <= 0;
         end else begin
	    adc_ch_no    <= adc_ch_no+1;
	 end
      end
   end
end




endmodule