data/full_repos/permissive/421030651/mdl/spi_mdl.sv
1: b'%Error: data/full_repos/permissive/421030651/mdl/spi_mdl.sv:43: Unsupported: wait statements\n    wait (rstn === 1\'b1);\n    ^~~~\n%Error: data/full_repos/permissive/421030651/mdl/spi_mdl.sv:49: Unsupported: wait statements\n        wait (NSS === 1\'b0);\n        ^~~~\n%Error: data/full_repos/permissive/421030651/mdl/spi_mdl.sv:55: syntax error, unexpected \'@\'\n            @(posedge SCLK or negedge SCLK or posedge NSS);\n            ^\n%Error: data/full_repos/permissive/421030651/mdl/spi_mdl.sv:64: syntax error, unexpected \'@\'\n                @(posedge SCLK or negedge SCLK or posedge NSS);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/421030651/mdl/spi_mdl.sv:65: Unsupported: Ignoring delay on this delayed statement.\n                #1;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/421030651/mdl/spi_mdl.sv:72: syntax error, unexpected \'@\'\n                @(posedge SCLK or negedge SCLK or posedge NSS);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/421030651/mdl/spi_mdl.sv:158: Unsupported: Ignoring delay on this delayed statement.\n    #1000000;\n    ^\n%Error: Exiting due to 5 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
function [7:0] txfifo_rdata;
logic [7:0] rdata;

if (txfifo_wptr != txfifo_rptr) begin
    rdata = txfifo[txfifo_rptr[9:0]];
    txfifo_rptr = txfifo_rptr + 11'b1;
end
else begin
    rdata = 8'hff;
end
return rdata;
endfunction
function [7:0] txfifo_rdata;

logic [7:0] rdata;

if (txfifo_wptr != txfifo_rptr) begin
    rdata = txfifo[txfifo_rptr[9:0]];
    txfifo_rptr = txfifo_rptr + 11'b1;
end
else begin
    rdata = 8'hff;
end
return rdata;
endfunction