data/full_repos/permissive/445455582/single/RiSC16_alu.v
1: b'%Error: data/full_repos/permissive/445455582/single/RiSC16_alu.v:21: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/445455582/single,data/full_repos/permissive/445455582/defines.v\n             data/full_repos/permissive/445455582/single,data/full_repos/permissive/445455582/defines.v.v\n             data/full_repos/permissive/445455582/single,data/full_repos/permissive/445455582/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/445455582/single/RiSC16_alu.v:47: Define or directive not defined: \'`ALU_FUNCT_LEN\'\n    input [`ALU_FUNCT_LEN - 1 : 0] funct;\n           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_alu.v:53: Define or directive not defined: \'`ALU_ADD\'\n            `ALU_ADD:   result <= src1 + src2;\n            ^~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_alu.v:53: syntax error, unexpected \':\', expecting endcase\n            `ALU_ADD:   result <= src1 + src2;\n                    ^\n%Error: data/full_repos/permissive/445455582/single/RiSC16_alu.v:54: Define or directive not defined: \'`ALU_NAND\'\n            `ALU_NAND:  result <= ~(src1 & src2);\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_alu.v:55: Define or directive not defined: \'`ALU_PASSA\'\n            `ALU_PASSA: result <= src1;\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_alu.v:56: Define or directive not defined: \'`ALU_SUB\'\n            `ALU_SUB:   result <= src1 - src2;\n            ^~~~~~~~\n%Error: Exiting due to 7 error(s)\n'
module RiSC16_alu #(
    parameter WORD_LENGTH = 16
) (
    src1, src2, result, state, funct
);

    output reg [WORD_LENGTH - 1 : 0] result = 0;
    output reg state = 0;

    input [WORD_LENGTH - 1 : 0] src1;
    input [WORD_LENGTH - 1 : 0] src2;
    input [`ALU_FUNCT_LEN - 1 : 0] funct;

    always @(*) begin
        
        case(funct)

            `ALU_ADD:   result <= src1 + src2;
            `ALU_NAND:  result <= ~(src1 & src2);
            `ALU_PASSA: result <= src1;
            `ALU_SUB:   result <= src1 - src2;
            default:    result <= 0;

        endcase

        state = &(~result);

    end
    
endmodule
module RiSC16_alu #(
    parameter WORD_LENGTH = 16
) (
    src1, src2, result, state, funct
);


    output reg [WORD_LENGTH - 1 : 0] result = 0;
    output reg state = 0;

    input [WORD_LENGTH - 1 : 0] src1;
    input [WORD_LENGTH - 1 : 0] src2;
    input [`ALU_FUNCT_LEN - 1 : 0] funct;

    always @(*) begin
        
        case(funct)

            `ALU_ADD:   result <= src1 + src2;
            `ALU_NAND:  result <= ~(src1 & src2);
            `ALU_PASSA: result <= src1;
            `ALU_SUB:   result <= src1 - src2;
            default:    result <= 0;

        endcase

        state = &(~result);

    end
    
endmodule