data/full_repos/permissive/445929378/mult_128.v
1: b'%Warning-WIDTH: data/full_repos/permissive/445929378/mult_128.v:39: Operator ADD expects 34 bits on the LHS, but LHS\'s VARREF \'input_a_high\' generates 32 bits.\n                                                                  : ... In instance mult_128\n   assign e_high_tdata = input_a_high + input_a_low;\n                                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/445929378/mult_128.v:39: Operator ADD expects 34 bits on the RHS, but RHS\'s VARREF \'input_a_low\' generates 32 bits.\n                                                                  : ... In instance mult_128\n   assign e_high_tdata = input_a_high + input_a_low;\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/445929378/mult_128.v:40: Operator ADD expects 34 bits on the LHS, but LHS\'s VARREF \'input_b_high\' generates 32 bits.\n                                                                  : ... In instance mult_128\n   assign e_low_tdata = input_b_high + input_b_low;\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/445929378/mult_128.v:40: Operator ADD expects 34 bits on the RHS, but RHS\'s VARREF \'input_b_low\' generates 32 bits.\n                                                                  : ... In instance mult_128\n   assign e_low_tdata = input_b_high + input_b_low;\n                                     ^\n%Error: data/full_repos/permissive/445929378/mult_128.v:52: Cannot find file containing module: \'mult_64_pipeline_2\'\n   mult_64_pipeline_2 mult_a(\n   ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/mult_64_pipeline_2\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/mult_64_pipeline_2.v\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/mult_64_pipeline_2.sv\n             mult_64_pipeline_2\n             mult_64_pipeline_2.v\n             mult_64_pipeline_2.sv\n             obj_dir/mult_64_pipeline_2\n             obj_dir/mult_64_pipeline_2.v\n             obj_dir/mult_64_pipeline_2.sv\n%Error: data/full_repos/permissive/445929378/mult_128.v:66: Cannot find file containing module: \'mult_64_pipeline_2\'\n   mult_64_pipeline_2 mult_d(\n   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/445929378/mult_128.v:80: Cannot find file containing module: \'mult_66_pipeline_2\'\n   mult_66_pipeline_2 mult_e(\n   ^~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/445929378/mult_128.v:111: Operator SHIFTL expects 128 bits on the LHS, but LHS\'s VARREF \'a_reg\' generates 64 bits.\n                                                                   : ... In instance mult_128\n        output_reg <= a_reg << (64);\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/445929378/mult_128.v:112: Operator SUB expects 66 bits on the RHS, but RHS\'s VARREF \'d_reg\' generates 64 bits.\n                                                                   : ... In instance mult_128\n        e_reg <= e_reg - d_reg - a_reg;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/445929378/mult_128.v:112: Operator SUB expects 66 bits on the RHS, but RHS\'s VARREF \'a_reg\' generates 64 bits.\n                                                                   : ... In instance mult_128\n        e_reg <= e_reg - d_reg - a_reg;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/445929378/mult_128.v:116: Operator SHIFTL expects 128 bits on the LHS, but LHS\'s VARREF \'e_reg\' generates 66 bits.\n                                                                   : ... In instance mult_128\n        bufer_reg <= e_reg << (32);\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/445929378/mult_128.v:120: Operator ADD expects 128 bits on the RHS, but RHS\'s VARREF \'d_reg\' generates 64 bits.\n                                                                   : ... In instance mult_128\n        output_reg <= output_reg + bufer_reg + d_reg;     \n                                             ^\n%Error: Exiting due to 3 error(s), 9 warning(s)\n'
module mult_128(
		input wire 	    clk, rst,
		input wire [63:0]   input_a_tdata, input_b_tdata,
		input wire 	    input_a_tvalid, input_b_tvalid,
		output wire 	    input_a_tready, input_b_tready,
		output wire [127:0] output_tdata,
		output wire 	    output_tvalid,
		input wire 	    output_tready
		);

   wire 			    karatsuba_rdy;
   
   wire [31:0] 			    input_a_high;
   wire [31:0] 			    input_a_low;
   
   wire [31:0] 			    input_b_high;
   wire [31:0] 			    input_b_low;

   wire [33:0] 			    e_high_tdata, e_low_tdata;

   reg [127:0] 			    output_reg;
   reg [127:0] 			    bufer_reg = 0;

   reg [2:0] 			    rdy_flg = 0;
   
   wire 			    data_tready;
   wire 			    a_output_tvalid, d_output_tvalid, e_output_tvalid;
   
   wire [63:0] 			    a, d;
   wire [65:0] 			    e;
   reg [63:0] 			    a_reg, d_reg;
   reg [65:0] 			    e_reg;
   
   assign {input_a_high, input_a_low} = input_a_tdata;
   assign {input_b_high, input_b_low} = input_b_tdata;

   assign e_high_tdata = input_a_high + input_a_low;
   assign e_low_tdata = input_b_high + input_b_low;
   
   assign input_a_tready = input_b_tvalid & output_tready;
   assign input_b_tready = input_a_tvalid & output_tready;
   
   assign data_tready = input_a_tready & input_b_tready & output_tready;
   assign karatsuba_rdy = a_output_tvalid & d_output_tvalid & e_output_tvalid;

   assign output_tvalid = rdy_flg[2];
   
   assign output_tdata = output_reg;
   
   mult_64_pipeline_2 mult_a(
			     .clk(clk),
			     .rst(rst),
			     .input_a_tdata(input_a_high),
			     .input_b_tdata(input_b_high),
			     .input_a_tvalid(input_a_tvalid),
			     .input_b_tvalid(input_b_tvalid),


			     .output_tdata(a),
			     .output_tvalid(a_output_tvalid),
			     .output_tready(data_tready)
			     );
   
   mult_64_pipeline_2 mult_d(
			     .clk(clk),
			     .rst(rst),
			     .input_a_tdata(input_a_low),
			     .input_b_tdata(input_b_low),
			     .input_a_tvalid(input_a_tvalid),
			     .input_b_tvalid(input_b_tvalid),


			     .output_tdata(d),
			     .output_tvalid(d_output_tvalid),
			     .output_tready(data_tready)
			     );
   
   mult_66_pipeline_2 mult_e(
			     .clk(clk),
			     .rst(rst),
			     .input_a_tdata(e_high_tdata),
			     .input_b_tdata(e_low_tdata),
			     .input_a_tvalid(input_a_tvalid),
			     .input_b_tvalid(input_b_tvalid),


			     .output_tdata(e),
			     .output_tvalid(e_output_tvalid),
			     .output_tready(data_tready)
			     );


   always @(posedge clk) begin
      if(rst) begin
	 rdy_flg <= 3'b000;
	 a_reg <= 0;
	 e_reg <= 0;
	 d_reg <= 0;
	 output_reg <= 0;
      end else begin
	 if(karatsuba_rdy) begin
	    if(rdy_flg[1:0] == 2'b00) begin
	       a_reg <= a;
	       e_reg <= e;
	       d_reg <= d;
	       rdy_flg <= 3'b001;
	    end	 
	    if(rdy_flg == 3'b001) begin
	       output_reg <= a_reg << (64);
	       e_reg <= e_reg - d_reg - a_reg;
	       rdy_flg <= 3'b10;
	    end
	    else if (rdy_flg == 3'b010) begin
	       bufer_reg <= e_reg << (32);
	       rdy_flg <= 3'b011;
	    end
	    else if (rdy_flg == 3'b011) begin
	       output_reg <= output_reg + bufer_reg + d_reg;	    
	       rdy_flg <= 3'b100;
	    end
	 end
      end
   end
endmodule
module mult_128(
		input wire 	    clk, rst,
		input wire [63:0]   input_a_tdata, input_b_tdata,
		input wire 	    input_a_tvalid, input_b_tvalid,
		output wire 	    input_a_tready, input_b_tready,
		output wire [127:0] output_tdata,
		output wire 	    output_tvalid,
		input wire 	    output_tready
		);


   wire 			    karatsuba_rdy;
   
   wire [31:0] 			    input_a_high;
   wire [31:0] 			    input_a_low;
   
   wire [31:0] 			    input_b_high;
   wire [31:0] 			    input_b_low;

   wire [33:0] 			    e_high_tdata, e_low_tdata;

   reg [127:0] 			    output_reg;
   reg [127:0] 			    bufer_reg = 0;

   reg [2:0] 			    rdy_flg = 0;
   
   wire 			    data_tready;
   wire 			    a_output_tvalid, d_output_tvalid, e_output_tvalid;
   
   wire [63:0] 			    a, d;
   wire [65:0] 			    e;
   reg [63:0] 			    a_reg, d_reg;
   reg [65:0] 			    e_reg;
   
   assign {input_a_high, input_a_low} = input_a_tdata;
   assign {input_b_high, input_b_low} = input_b_tdata;

   assign e_high_tdata = input_a_high + input_a_low;
   assign e_low_tdata = input_b_high + input_b_low;
   
   assign input_a_tready = input_b_tvalid & output_tready;
   assign input_b_tready = input_a_tvalid & output_tready;
   
   assign data_tready = input_a_tready & input_b_tready & output_tready;
   assign karatsuba_rdy = a_output_tvalid & d_output_tvalid & e_output_tvalid;

   assign output_tvalid = rdy_flg[2];
   
   assign output_tdata = output_reg;
   
   mult_64_pipeline_2 mult_a(
			     .clk(clk),
			     .rst(rst),
			     .input_a_tdata(input_a_high),
			     .input_b_tdata(input_b_high),
			     .input_a_tvalid(input_a_tvalid),
			     .input_b_tvalid(input_b_tvalid),


			     .output_tdata(a),
			     .output_tvalid(a_output_tvalid),
			     .output_tready(data_tready)
			     );
   
   mult_64_pipeline_2 mult_d(
			     .clk(clk),
			     .rst(rst),
			     .input_a_tdata(input_a_low),
			     .input_b_tdata(input_b_low),
			     .input_a_tvalid(input_a_tvalid),
			     .input_b_tvalid(input_b_tvalid),


			     .output_tdata(d),
			     .output_tvalid(d_output_tvalid),
			     .output_tready(data_tready)
			     );
   
   mult_66_pipeline_2 mult_e(
			     .clk(clk),
			     .rst(rst),
			     .input_a_tdata(e_high_tdata),
			     .input_b_tdata(e_low_tdata),
			     .input_a_tvalid(input_a_tvalid),
			     .input_b_tvalid(input_b_tvalid),


			     .output_tdata(e),
			     .output_tvalid(e_output_tvalid),
			     .output_tready(data_tready)
			     );


   always @(posedge clk) begin
      if(rst) begin
	 rdy_flg <= 3'b000;
	 a_reg <= 0;
	 e_reg <= 0;
	 d_reg <= 0;
	 output_reg <= 0;
      end else begin
	 if(karatsuba_rdy) begin
	    if(rdy_flg[1:0] == 2'b00) begin
	       a_reg <= a;
	       e_reg <= e;
	       d_reg <= d;
	       rdy_flg <= 3'b001;
	    end	 
	    if(rdy_flg == 3'b001) begin
	       output_reg <= a_reg << (64);
	       e_reg <= e_reg - d_reg - a_reg;
	       rdy_flg <= 3'b10;
	    end
	    else if (rdy_flg == 3'b010) begin
	       bufer_reg <= e_reg << (32);
	       rdy_flg <= 3'b011;
	    end
	    else if (rdy_flg == 3'b011) begin
	       output_reg <= output_reg + bufer_reg + d_reg;	    
	       rdy_flg <= 3'b100;
	    end
	 end
      end
   end
endmodule