data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v
1: b'%Error: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:13: Unsupported: fork statements\ninitial fork\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:15: Unsupported: Ignoring delay on this delayed statement.\n #1 Reset = 0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11100010_00000001_00000000_00000000 ; #1 MEMLOAD = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11100010_00000001_00000000_00000000 ; #1 MEMLOAD = 1; \n                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #5 MEMLOAD=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11100011_10000000_00010000_00101000 ; #1 MEMLOAD = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11100011_10000000_00010000_00101000 ; #1 MEMLOAD = 1; \n                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #5 MEMLOAD=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11100111_11010001_00100000_00000000 ; #1 MEMLOAD = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11100111_11010001_00100000_00000000 ; #1 MEMLOAD = 1; \n                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #5 MEMLOAD=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11100101_11010001_00110000_00000010 ; #1 MEMLOAD = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11100101_11010001_00110000_00000010 ; #1 MEMLOAD = 1; \n                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #5 MEMLOAD=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11100000_10000000_01010000_00000000 ; #1 MEMLOAD = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11100000_10000000_01010000_00000000 ; #1 MEMLOAD = 1; \n                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #5 MEMLOAD=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11100000_10000010_01010000_00000101; #1 MEMLOAD = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11100000_10000010_01010000_00000101; #1 MEMLOAD = 1; \n                                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #5 MEMLOAD=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11100010_01010011_00110000_00000001 ; #1 MEMLOAD = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11100010_01010011_00110000_00000001 ; #1 MEMLOAD = 1; \n                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #5 MEMLOAD=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:52: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b00011010_11111111_11111111_11111101 ; #1 MEMLOAD = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:52: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b00011010_11111111_11111111_11111101 ; #1 MEMLOAD = 1; \n                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #5 MEMLOAD=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11100101_11000001_01010000_00000011 ; #1 MEMLOAD = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11100101_11000001_01010000_00000011 ; #1 MEMLOAD = 1; \n                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #5 MEMLOAD=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11101010_00000000_00000000_00000001 ; #1 MEMLOAD = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11101010_00000000_00000000_00000001 ; #1 MEMLOAD = 1; \n                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:61: Unsupported: Ignoring delay on this delayed statement.\n    #5 MEMLOAD=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b00001011_00000101_00000111_00000100 ; #1 MEMLOAD = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b00001011_00000101_00000111_00000100 ; #1 MEMLOAD = 1; \n                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #5 MEMLOAD=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:68: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11101010_11111111_11111111_11111111 ; #1 MEMLOAD = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:68: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'b11101010_11111111_11111111_11111111 ; #1 MEMLOAD = 1; \n                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:69: Unsupported: Ignoring delay on this delayed statement.\n    #5 MEMLOAD=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:72: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'h00000000 ; #1 MEMLOAD = 1; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:72: Unsupported: Ignoring delay on this delayed statement.\n    #1 MEMDAT = 32\'h00000000 ; #1 MEMLOAD = 1; \n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:73: Unsupported: Ignoring delay on this delayed statement.\n    #5 MEMLOAD=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:76: Unsupported: Ignoring delay on this delayed statement.\n  #5 MFC = 1 ;#7 MFC = 0 ;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:76: Unsupported: Ignoring delay on this delayed statement.\n  #5 MFC = 1 ;#7 MFC = 0 ;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:81: Unsupported: Ignoring delay on this delayed statement.\n #1 Clk = ~Clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:83: Unsupported: Ignoring delay on this delayed statement.\ninitial #sim_time $finish; \n        ^\n%Error: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:86: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("ARM_CU_ALU_TestBench5.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/CPU/ARM_CU_ALU_TestBench5.v:87: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,ARM_CU_ALU_TestBench5);\n ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 44 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ARM_CU_ALU_TestBench5;

parameter sim_time = 750*2;

reg MFC , Reset , Clk , MEMSTORE,MEMLOAD;
reg [31:0] MEMDAT;
wire MFA,READ_WRITE,WORD_BYTE;
wire [7:0] MEMADD;


ARM_CU_ALU CPU( MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT,MEMADD, MFA,READ_WRITE,WORD_BYTE);

initial fork
	Reset =1; Clk = 0; MEMSTORE=0;MEMLOAD=0;MEMDAT=0;MFC=0;
	#1 Reset = 0;
join

always@(posedge MFA)begin
	$display("MEMADD = %d", MEMADD);
	if(READ_WRITE == 1) begin
		case(MEMADD) 
			8'h00:begin
				#1 MEMDAT = 32'b11100010_00000001_00000000_00000000 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
				
			end
			8'h04:begin
				#1 MEMDAT = 32'b11100011_10000000_00010000_00101000 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h08:begin
				#1 MEMDAT = 32'b11100111_11010001_00100000_00000000 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h0C:begin
				#1 MEMDAT = 32'b11100101_11010001_00110000_00000010 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h10:begin
				#1 MEMDAT = 32'b11100000_10000000_01010000_00000000 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h14:begin
				#1 MEMDAT = 32'b11100000_10000010_01010000_00000101; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h18:begin
				#1 MEMDAT = 32'b11100010_01010011_00110000_00000001 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h1C:begin
				#1 MEMDAT = 32'b00011010_11111111_11111111_11111101 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h20:begin
				#1 MEMDAT = 32'b11100101_11000001_01010000_00000011 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h24:begin
				#1 MEMDAT = 32'b11101010_00000000_00000000_00000001 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h28:begin
				#1 MEMDAT = 32'b00001011_00000101_00000111_00000100 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h2C:begin
				#1 MEMDAT = 32'b11101010_11111111_11111111_11111111 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			default:begin
				#1 MEMDAT = 32'h00000000 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
		endcase
		#5 MFC = 1 ;#7 MFC = 0 ;
		end
end
	
always 
	#1 Clk = ~Clk;
	
initial #sim_time $finish; 

initial begin
	$dumpfile("ARM_CU_ALU_TestBench5.vcd");
	$dumpvars(0,ARM_CU_ALU_TestBench5);


end

endmodule
module ARM_CU_ALU_TestBench5;


parameter sim_time = 750*2;

reg MFC , Reset , Clk , MEMSTORE,MEMLOAD;
reg [31:0] MEMDAT;
wire MFA,READ_WRITE,WORD_BYTE;
wire [7:0] MEMADD;


ARM_CU_ALU CPU( MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT,MEMADD, MFA,READ_WRITE,WORD_BYTE);

initial fork
	Reset =1; Clk = 0; MEMSTORE=0;MEMLOAD=0;MEMDAT=0;MFC=0;
	#1 Reset = 0;
join

always@(posedge MFA)begin
	$display("MEMADD = %d", MEMADD);
	if(READ_WRITE == 1) begin
		case(MEMADD) 
			8'h00:begin
				#1 MEMDAT = 32'b11100010_00000001_00000000_00000000 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
				
			end
			8'h04:begin
				#1 MEMDAT = 32'b11100011_10000000_00010000_00101000 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h08:begin
				#1 MEMDAT = 32'b11100111_11010001_00100000_00000000 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h0C:begin
				#1 MEMDAT = 32'b11100101_11010001_00110000_00000010 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h10:begin
				#1 MEMDAT = 32'b11100000_10000000_01010000_00000000 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h14:begin
				#1 MEMDAT = 32'b11100000_10000010_01010000_00000101; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h18:begin
				#1 MEMDAT = 32'b11100010_01010011_00110000_00000001 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h1C:begin
				#1 MEMDAT = 32'b00011010_11111111_11111111_11111101 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h20:begin
				#1 MEMDAT = 32'b11100101_11000001_01010000_00000011 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h24:begin
				#1 MEMDAT = 32'b11101010_00000000_00000000_00000001 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h28:begin
				#1 MEMDAT = 32'b00001011_00000101_00000111_00000100 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			8'h2C:begin
				#1 MEMDAT = 32'b11101010_11111111_11111111_11111111 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
			default:begin
				#1 MEMDAT = 32'h00000000 ; #1 MEMLOAD = 1; 
				#5 MEMLOAD=0;
			end
		endcase
		#5 MFC = 1 ;#7 MFC = 0 ;
		end
end
	
always 
	#1 Clk = ~Clk;
	
initial #sim_time $finish; 

initial begin
	$dumpfile("ARM_CU_ALU_TestBench5.vcd");
	$dumpvars(0,ARM_CU_ALU_TestBench5);


end

endmodule