data/full_repos/permissive/531341619/rtl/fp32_adder_dual_add_stage.v
data/verilator_xmls/c9e9ca4f-8917-4dec-9e63-548e68b17eb1.xml
module fp32_adder_dual_add_stage
#(
  parameter EXPONENT_WIDTH = 8,
  parameter MANTISA_WIDTH = 24
) (
  input  wire clk,
  input  wire signed [EXPONENT_WIDTH-1:0] exponent_big_0_in, exponent_big_1_in,
  input  wire signed [MANTISA_WIDTH-1:0] mantissa_big_0_in, mantissa_aligned_0,
  input  wire signed [MANTISA_WIDTH-1:0] mantissa_big_1_in, mantissa_aligned_1,
  
  output reg  signed [EXPONENT_WIDTH-1:0] exponent_big_0_out, exponent_big_1_out,
  output reg  signed [MANTISA_WIDTH:0] add_0_out, add_1_out
);

  always @(posedge clk) 
  begin

    add_0_out <= mantissa_big_0_in + mantissa_aligned_0; 
    add_1_out <= mantissa_big_1_in + mantissa_aligned_1;
    exponent_big_0_out <= exponent_big_0_in;
    exponent_big_1_out <= exponent_big_1_in;
  end
endmodule
module fp32_adder_dual_add_stage
#(
  parameter EXPONENT_WIDTH = 8,
  parameter MANTISA_WIDTH = 24
) (
  input  wire clk,
  input  wire signed [EXPONENT_WIDTH-1:0] exponent_big_0_in, exponent_big_1_in,
  input  wire signed [MANTISA_WIDTH-1:0] mantissa_big_0_in, mantissa_aligned_0,
  input  wire signed [MANTISA_WIDTH-1:0] mantissa_big_1_in, mantissa_aligned_1,
  
  output reg  signed [EXPONENT_WIDTH-1:0] exponent_big_0_out, exponent_big_1_out,
  output reg  signed [MANTISA_WIDTH:0] add_0_out, add_1_out
);


  always @(posedge clk) 
  begin

    add_0_out <= mantissa_big_0_in + mantissa_aligned_0; 
    add_1_out <= mantissa_big_1_in + mantissa_aligned_1;
    exponent_big_0_out <= exponent_big_0_in;
    exponent_big_1_out <= exponent_big_1_in;
  end
endmodule