data/full_repos/permissive/473722449/reg_4bit_clr.v
data/verilator_xmls/708b2dfe-71e7-4209-868a-9ee4261afe56.xml
module reg_4bit_clr(
    input [3:0] d,
    input clk,
    input load,
    input clear,
    output reg [3:0] q
    );
    always@(posedge clk)
    begin
        if (clear == 1)
            assign q= 4'b0000;
         else
            begin
                if (load == 0)
                    assign q = q;
                else
                    assign q=d;    
            end   
    end
    
endmodule
module reg_4bit_clr(
    input [3:0] d,
    input clk,
    input load,
    input clear,
    output reg [3:0] q
    );

    always@(posedge clk)
    begin
        if (clear == 1)
            assign q= 4'b0000;
         else
            begin
                if (load == 0)
                    assign q = q;
                else
                    assign q=d;    
            end   
    end
    
endmodule