data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/MICROBENCHMARKS/bm_dag3_lpm_log_mod.v
1: b'%Warning-WIDTH: data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/MICROBENCHMARKS/bm_dag3_lpm_log_mod.v:84: Operator XOR expects 2 bits on the RHS, but RHS\'s VARREF \'temp3\' generates 1 bits.\n                                                                                                                                    : ... In instance bm_dag3_lpm_log_mod.top_b\n temp2 <= seventh | eight ^ temp3;\n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module 	bm_dag3_lpm_log_mod(clock, 
		reset_n, 
		first, 
		sceond,
		third, 
		fourth, 
		out0,
		out1);


input	clock;
input 	reset_n;

input [`BITS-1:0] first;
input [`BITS-1:0] sceond;
input third;
input fourth;

output [`BITS-1:0] out0;
output  out1;

wire [`BITS-1:0]    out0;
wire     out1;

wire [`BITS-1:0] temp_a;
wire [`BITS-1:0] temp_b;
wire temp_c;
wire temp_d;

a top_a(clock, first, sceond, temp_a);
b top_b(clock, first, sceond, temp_b);
c top_c(clock, third, fourth, temp_c);
d top_d(clock, third, fourth, temp_d);

assign out0 = temp_a & temp_b;
assign out1 = temp_c + temp_d;

endmodule
module 	bm_dag3_lpm_log_mod(clock, 
		reset_n, 
		first, 
		sceond,
		third, 
		fourth, 
		out0,
		out1);



input	clock;
input 	reset_n;

input [`BITS-1:0] first;
input [`BITS-1:0] sceond;
input third;
input fourth;

output [`BITS-1:0] out0;
output  out1;

wire [`BITS-1:0]    out0;
wire     out1;

wire [`BITS-1:0] temp_a;
wire [`BITS-1:0] temp_b;
wire temp_c;
wire temp_d;

a top_a(clock, first, sceond, temp_a);
b top_b(clock, first, sceond, temp_b);
c top_c(clock, third, fourth, temp_c);
d top_d(clock, third, fourth, temp_d);

assign out0 = temp_a & temp_b;
assign out1 = temp_c + temp_d;

endmodule