data/full_repos/permissive/487568919/basic_verilog/lifo_tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/lifo_tb.sv:16: Unsupported: Ignoring delay on this delayed statement.\n  #0 clk200 = 1\'b0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/lifo_tb.sv:18: Unsupported: Ignoring delay on this delayed statement.\n    #2.5 clk200 = ~clk200;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/lifo_tb.sv:24: Unsupported: Ignoring delay on this delayed statement.\n  #0 clk33 = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/lifo_tb.sv:26: Unsupported: Ignoring delay on this delayed statement.\n    #15.151 clk33 = ~clk33;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/lifo_tb.sv:31: Unsupported: Ignoring delay on this delayed statement.\n  #0 rst = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/lifo_tb.sv:32: Unsupported: Ignoring delay on this delayed statement.\n  #10.2 rst = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/lifo_tb.sv:33: Unsupported: Ignoring delay on this delayed statement.\n  #5 rst = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/lifo_tb.sv:36: Unsupported: Ignoring delay on this delayed statement.\n    #9985 rst = ~rst;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/lifo_tb.sv:37: Unsupported: Ignoring delay on this delayed statement.\n    #5 rst = ~rst;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/lifo_tb.sv:46: Unsupported: Ignoring delay on this delayed statement.\n  #0 rst_once = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/lifo_tb.sv:47: Unsupported: Ignoring delay on this delayed statement.\n  #10.2 rst_once = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/lifo_tb.sv:48: Unsupported: Ignoring delay on this delayed statement.\n  #5 rst_once = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/lifo_tb.sv:85: Unsupported: Ignoring delay on this delayed statement.\n  #0 start = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/lifo_tb.sv:86: Unsupported: Ignoring delay on this delayed statement.\n  #100 start = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/lifo_tb.sv:87: Unsupported: Ignoring delay on this delayed statement.\n  #20 start = 1\'b0;\n  ^\n%Error: data/full_repos/permissive/487568919/basic_verilog/lifo_tb.sv:55: Cannot find file containing module: \'clk_divider\'\nclk_divider #(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/487568919/basic_verilog,data/full_repos/permissive/487568919/clk_divider\n             data/full_repos/permissive/487568919/basic_verilog,data/full_repos/permissive/487568919/clk_divider.v\n             data/full_repos/permissive/487568919/basic_verilog,data/full_repos/permissive/487568919/clk_divider.sv\n             clk_divider\n             clk_divider.v\n             clk_divider.sv\n             obj_dir/clk_divider\n             obj_dir/clk_divider.v\n             obj_dir/clk_divider.sv\n%Error: data/full_repos/permissive/487568919/basic_verilog/lifo_tb.sv:65: Cannot find file containing module: \'edge_detect\'\nedge_detect ed1[31:0] (\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/lifo_tb.sv:75: Cannot find file containing module: \'c_rand\'\nc_rand rng1 (\n^~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/lifo_tb.sv:124: Cannot find file containing module: \'lifo\'\nlifo #(\n^~~~\n%Error: Exiting due to 4 error(s), 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module lifo_tb();

logic clk200;
initial begin
  #0 clk200 = 1'b0;
  forever
    #2.5 clk200 = ~clk200;
end


logic clk33;
initial begin
  #0 clk33 = 1'b0;
  forever
    #15.151 clk33 = ~clk33;
end

logic rst;
initial begin
  #0 rst = 1'b0;
  #10.2 rst = 1'b1;
  #5 rst = 1'b0;

  forever begin
    #9985 rst = ~rst;
    #5 rst = ~rst;
  end
end

logic nrst;
assign nrst = ~rst;

logic rst_once;
initial begin
  #0 rst_once = 1'b0;
  #10.2 rst_once = 1'b1;
  #5 rst_once = 1'b0;
end

logic nrst_once;
assign nrst_once = ~rst_once;

logic [31:0] DerivedClocks;
clk_divider #(
  .WIDTH( 32 )
) cd1 (
  .clk( clk200 ),
  .nrst( nrst_once ),
  .ena( 1'b1 ),
  .out( DerivedClocks[31:0] )
);

logic [31:0] E_DerivedClocks;
edge_detect ed1[31:0] (
  .clk( {32{clk200}} ),
  .nrst( {32{nrst_once}} ),
  .in( DerivedClocks[31:0] ),
  .rising( E_DerivedClocks[31:0] ),
  .falling(  ),
  .both(  )
);

logic [15:0] RandomNumber1;
c_rand rng1 (
  .clk(clk200),
  .rst(rst_once),
  .reseed(1'b0),
  .seed_val(DerivedClocks[31:0]),
  .out( RandomNumber1[15:0] )
);

logic start;
initial begin
  #0 start = 1'b0;
  #100 start = 1'b1;
  #20 start = 1'b0;
end








`define TEST_SWEEP yes

logic full1, empty1;
logic full1_d1, empty1_d1;

logic direction1 = 1'b0;
always_ff @(posedge clk200) begin
  if( ~nrst ) begin
    direction1 <= 1'b0;
  end else begin

    if( full1_d1 ) begin
      direction1 <= 1'b1;
    end else if( empty1_d1 ) begin
     direction1 <= 1'b0;
end




    full1_d1 <= full1;
    empty1_d1 <= empty1;
  end
end

logic [3:0] cnt1;
logic [15:0] data_out1;
lifo #(
`ifdef TEST_FWFT
  .FWFT_MODE( "TRUE" ),
`else
  .FWFT_MODE( "FALSE" ),
`endif
  .DEPTH( 8 ),
  .DATA_W( 16 )
) LF1 (
  .clk( clk200 ),
  .nrst( nrst_once ),

`ifdef TEST_SWEEP
  .w_req( ~direction1 && &RandomNumber1[10] ),
  .w_data( RandomNumber1[15:0] ),

  .r_req( direction1 && &RandomNumber1[10] ),
  .r_data( data_out1[15:0] ),
`else
  .w_req( &RandomNumber1[10:9] ),
  .w_data( RandomNumber1[15:0] ),

  .r_req( &RandomNumber1[8:7] ),
  .r_data( data_out1[15:0] ),
`endif

  .cnt( cnt1[3:0] ),
  .empty( empty1 ),
  .full( full1 )
);


endmodule
module lifo_tb();


logic clk200;
initial begin
  #0 clk200 = 1'b0;
  forever
    #2.5 clk200 = ~clk200;
end


logic clk33;
initial begin
  #0 clk33 = 1'b0;
  forever
    #15.151 clk33 = ~clk33;
end

logic rst;
initial begin
  #0 rst = 1'b0;
  #10.2 rst = 1'b1;
  #5 rst = 1'b0;

  forever begin
    #9985 rst = ~rst;
    #5 rst = ~rst;
  end
end

logic nrst;
assign nrst = ~rst;

logic rst_once;
initial begin
  #0 rst_once = 1'b0;
  #10.2 rst_once = 1'b1;
  #5 rst_once = 1'b0;
end

logic nrst_once;
assign nrst_once = ~rst_once;

logic [31:0] DerivedClocks;
clk_divider #(
  .WIDTH( 32 )
) cd1 (
  .clk( clk200 ),
  .nrst( nrst_once ),
  .ena( 1'b1 ),
  .out( DerivedClocks[31:0] )
);

logic [31:0] E_DerivedClocks;
edge_detect ed1[31:0] (
  .clk( {32{clk200}} ),
  .nrst( {32{nrst_once}} ),
  .in( DerivedClocks[31:0] ),
  .rising( E_DerivedClocks[31:0] ),
  .falling(  ),
  .both(  )
);

logic [15:0] RandomNumber1;
c_rand rng1 (
  .clk(clk200),
  .rst(rst_once),
  .reseed(1'b0),
  .seed_val(DerivedClocks[31:0]),
  .out( RandomNumber1[15:0] )
);

logic start;
initial begin
  #0 start = 1'b0;
  #100 start = 1'b1;
  #20 start = 1'b0;
end








`define TEST_SWEEP yes

logic full1, empty1;
logic full1_d1, empty1_d1;

logic direction1 = 1'b0;
always_ff @(posedge clk200) begin
  if( ~nrst ) begin
    direction1 <= 1'b0;
  end else begin

    if( full1_d1 ) begin
      direction1 <= 1'b1;
    end else if( empty1_d1 ) begin
     direction1 <= 1'b0;
end




    full1_d1 <= full1;
    empty1_d1 <= empty1;
  end
end

logic [3:0] cnt1;
logic [15:0] data_out1;
lifo #(
`ifdef TEST_FWFT
  .FWFT_MODE( "TRUE" ),
`else
  .FWFT_MODE( "FALSE" ),
`endif
  .DEPTH( 8 ),
  .DATA_W( 16 )
) LF1 (
  .clk( clk200 ),
  .nrst( nrst_once ),

`ifdef TEST_SWEEP
  .w_req( ~direction1 && &RandomNumber1[10] ),
  .w_data( RandomNumber1[15:0] ),

  .r_req( direction1 && &RandomNumber1[10] ),
  .r_data( data_out1[15:0] ),
`else
  .w_req( &RandomNumber1[10:9] ),
  .w_data( RandomNumber1[15:0] ),

  .r_req( &RandomNumber1[8:7] ),
  .r_data( data_out1[15:0] ),
`endif

  .cnt( cnt1[3:0] ),
  .empty( empty1 ),
  .full( full1 )
);


endmodule