data/full_repos/permissive/43264243/testbench.v
1: b'%Error: data/full_repos/permissive/43264243/testbench.v:62: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, testbench);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/43264243/testbench.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/43264243/testbench.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #5000000\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43264243/testbench.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #1090\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43264243/testbench.v:77: Unsupported: Ignoring delay on this delayed statement.\n  #610\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43264243/testbench.v:79: Unsupported: Ignoring delay on this delayed statement.\n  #8300\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43264243/testbench.v:89: Unsupported: Ignoring delay on this delayed statement.\n  #10000000 $finish; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43264243/testbench.v:92: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = ~clk;\n        ^\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
  

	reg clk; 
	reg rstn;
	reg datain_ch0;
	reg datain_ch1;
	reg datain_ch2;
	reg datain_ch3;
	integer i;
	wire serialout;
	wire testout0;
	wire testout1;
	wire testout2;
	wire testout3;
  
	
	root test_root(
		.clk(clk),
		.rstn(rstn),
		.datain_ch0(datain_ch0),
		.datain_ch1(datain_ch1),
		.datain_ch2(datain_ch2),
		.datain_ch3(datain_ch3),
		
		.serialout(serialout),
		.testout0(testout0),
		.testout1(testout1),
		.testout2(testout2),
		.testout3(testout3)
	);


	initial begin
		$dumpvars(0, testbench);
	
		clk = 0;
	
		rstn = 0;
		datain_ch0 = 0;
		datain_ch1 = 0;
		datain_ch2 = 0;
		datain_ch3 = 0;
		#10
		rstn = 1;
		#5000000
		datain_ch1 = 1;
		#1090
		datain_ch0 = 1;
		#610
		datain_ch0 = 0;
		#8300
		datain_ch1 = 0;
	
		



		


		#10000000 $finish; 
	end
 
	always #5 clk = ~clk;


endmodule
module testbench;

  

	reg clk; 
	reg rstn;
	reg datain_ch0;
	reg datain_ch1;
	reg datain_ch2;
	reg datain_ch3;
	integer i;
	wire serialout;
	wire testout0;
	wire testout1;
	wire testout2;
	wire testout3;
  
	
	root test_root(
		.clk(clk),
		.rstn(rstn),
		.datain_ch0(datain_ch0),
		.datain_ch1(datain_ch1),
		.datain_ch2(datain_ch2),
		.datain_ch3(datain_ch3),
		
		.serialout(serialout),
		.testout0(testout0),
		.testout1(testout1),
		.testout2(testout2),
		.testout3(testout3)
	);


	initial begin
		$dumpvars(0, testbench);
	
		clk = 0;
	
		rstn = 0;
		datain_ch0 = 0;
		datain_ch1 = 0;
		datain_ch2 = 0;
		datain_ch3 = 0;
		#10
		rstn = 1;
		#5000000
		datain_ch1 = 1;
		#1090
		datain_ch0 = 1;
		#610
		datain_ch0 = 0;
		#8300
		datain_ch1 = 0;
	
		



		


		#10000000 $finish; 
	end
 
	always #5 clk = ~clk;


endmodule