data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/watermarkx.v
data/verilator_xmls/91b05601-3fd4-42e1-b35d-30d01c8ee82e.xml
module watermarkx
    (
     clk,
     rst,
     dtvl,
     alarm,
     upact,
     upen,
     upws,
     updi,
     updo,
     lalarm
     );

parameter           WIDTH = 8;
parameter           MODE  = 0;

input               clk;
input               rst;
input               dtvl;
input   [WIDTH-1:0] alarm;
input               upact;
input               upen;
input               upws;
input   [WIDTH-1:0] updi;

output  [WIDTH-1:0] updo;
output  [WIDTH-1:0] lalarm;

wire                we;
assign              we = upen & upws;

reg [WIDTH-1:0]     lalarm;

assign              updo = upen ? lalarm : {WIDTH{1'b0}};

always @(posedge clk)
    begin
    if (rst) 
        lalarm <= MODE ? {WIDTH{1'b1}} : {WIDTH{1'b0}};
    else if (!upact) 
        lalarm <= MODE ? {WIDTH{1'b1}} : {WIDTH{1'b0}};
    else if (we) 
        lalarm <= updi;
    else if (dtvl)
        begin
        if (MODE)
            begin
            if(alarm < lalarm) lalarm <= alarm;
            end
        else
            begin
            if(alarm > lalarm) lalarm <= alarm;
            end
        end
    end

endmodule
module watermarkx
    (
     clk,
     rst,
     dtvl,
     alarm,
     upact,
     upen,
     upws,
     updi,
     updo,
     lalarm
     );


parameter           WIDTH = 8;
parameter           MODE  = 0;

input               clk;
input               rst;
input               dtvl;
input   [WIDTH-1:0] alarm;
input               upact;
input               upen;
input               upws;
input   [WIDTH-1:0] updi;

output  [WIDTH-1:0] updo;
output  [WIDTH-1:0] lalarm;

wire                we;
assign              we = upen & upws;

reg [WIDTH-1:0]     lalarm;

assign              updo = upen ? lalarm : {WIDTH{1'b0}};

always @(posedge clk)
    begin
    if (rst) 
        lalarm <= MODE ? {WIDTH{1'b1}} : {WIDTH{1'b0}};
    else if (!upact) 
        lalarm <= MODE ? {WIDTH{1'b1}} : {WIDTH{1'b0}};
    else if (we) 
        lalarm <= updi;
    else if (dtvl)
        begin
        if (MODE)
            begin
            if(alarm < lalarm) lalarm <= alarm;
            end
        else
            begin
            if(alarm > lalarm) lalarm <= alarm;
            end
        end
    end

endmodule