data/full_repos/permissive/488739248/rtl/clocks/AlphaMissionCore_Clocks_Cen.v
data/verilator_xmls/7b289808-9db5-46e4-9af5-55d6216a660d.xml
module AlphaMissionCoreClocks_Cen (
    input wire  i_clk,
    output wire clk_13p4_cen,
    output wire clk_13p4,
    output wire clk_13p4b_cen,
    output wire clk_13p4b,
    output wire clk_6p7_cen,
    output wire clk_6p7b_cen,
    output wire clk_3p35_cen,
    output wire clk_3p35b_cen,
    output wire clk_4_cen,
    output wire clk_4b_cen
);
    reg ck_stb1=1'b0;
    reg ck_stb2=1'b0;
    reg ck_stb3=1'b0;
    reg ck_stb4=1'b0;
    reg ck_stb5=1'b0;
    reg ck_stb6=1'b0;
    reg ck_stb7=1'b0;
    reg ck_stb8=1'b0;


    reg	[3:0] counter1=4'h4;
    reg clk_13p4_r = 0;
    reg [3:0] counter2=4'hC;
    reg clk_13p4b_r = 0;


    reg	[3:0] counter3=4'hE;
    reg [3:0] counter4=4'h6;

    reg	[3:0] counter5=4'hF;
    reg [3:0] counter6=4'h7;

    reg	[15:0] counter7=16'd63583;
    reg [15:0] counter8=16'd30815;


    always @(negedge i_clk) begin
            { ck_stb1, counter1 } <= counter1 + 4'h4;
    end

    assign clk_13p4_cen = ck_stb1;

    always @(posedge i_clk)
        if (clk_13p4_cen || clk_13p4b_cen) begin
            clk_13p4_r <= ~clk_13p4_r;
            clk_13p4b_r <= ~clk_13p4b_r;
        end 
    assign clk_13p4 = clk_13p4_r;
    assign clk_13p4b = clk_13p4b_r;

    always @(negedge i_clk) begin
            { ck_stb2, counter2 } <= counter2 + 4'h4    ;
    end

    assign clk_13p4b_cen = ck_stb2;


    always @(negedge i_clk) begin
            { ck_stb3, counter3 } <= counter3 + 4'h2;
    end

    always @(negedge i_clk) begin
            { ck_stb4, counter4 } <= counter4 + 4'h2;
    end
    
    assign clk_6p7_cen = ck_stb3;
    assign clk_6p7b_cen = ck_stb4;


    always @(negedge i_clk) begin
            { ck_stb5, counter5 } <= counter5 + 4'h1;
    end

    always @(negedge i_clk) begin
            { ck_stb6, counter6 } <= counter6 + 4'h1;
    end

    assign clk_3p35_cen = ck_stb5;
    assign clk_3p35b_cen = ck_stb6;

    always @(negedge i_clk) begin
            { ck_stb7, counter7 } <= counter7 + 16'd4891;
    end

    always @(negedge i_clk) begin
            { ck_stb8, counter8 } <= counter8 + 16'd4891;
    end

    assign clk_4_cen = ck_stb7;
    assign clk_4b_cen = ck_stb8;
endmodule
module AlphaMissionCoreClocks_Cen (
    input wire  i_clk,
    output wire clk_13p4_cen,
    output wire clk_13p4,
    output wire clk_13p4b_cen,
    output wire clk_13p4b,
    output wire clk_6p7_cen,
    output wire clk_6p7b_cen,
    output wire clk_3p35_cen,
    output wire clk_3p35b_cen,
    output wire clk_4_cen,
    output wire clk_4b_cen
);

    reg ck_stb1=1'b0;
    reg ck_stb2=1'b0;
    reg ck_stb3=1'b0;
    reg ck_stb4=1'b0;
    reg ck_stb5=1'b0;
    reg ck_stb6=1'b0;
    reg ck_stb7=1'b0;
    reg ck_stb8=1'b0;


    reg	[3:0] counter1=4'h4;
    reg clk_13p4_r = 0;
    reg [3:0] counter2=4'hC;
    reg clk_13p4b_r = 0;


    reg	[3:0] counter3=4'hE;
    reg [3:0] counter4=4'h6;

    reg	[3:0] counter5=4'hF;
    reg [3:0] counter6=4'h7;

    reg	[15:0] counter7=16'd63583;
    reg [15:0] counter8=16'd30815;


    always @(negedge i_clk) begin
            { ck_stb1, counter1 } <= counter1 + 4'h4;
    end

    assign clk_13p4_cen = ck_stb1;

    always @(posedge i_clk)
        if (clk_13p4_cen || clk_13p4b_cen) begin
            clk_13p4_r <= ~clk_13p4_r;
            clk_13p4b_r <= ~clk_13p4b_r;
        end 
    assign clk_13p4 = clk_13p4_r;
    assign clk_13p4b = clk_13p4b_r;

    always @(negedge i_clk) begin
            { ck_stb2, counter2 } <= counter2 + 4'h4    ;
    end

    assign clk_13p4b_cen = ck_stb2;


    always @(negedge i_clk) begin
            { ck_stb3, counter3 } <= counter3 + 4'h2;
    end

    always @(negedge i_clk) begin
            { ck_stb4, counter4 } <= counter4 + 4'h2;
    end
    
    assign clk_6p7_cen = ck_stb3;
    assign clk_6p7b_cen = ck_stb4;


    always @(negedge i_clk) begin
            { ck_stb5, counter5 } <= counter5 + 4'h1;
    end

    always @(negedge i_clk) begin
            { ck_stb6, counter6 } <= counter6 + 4'h1;
    end

    assign clk_3p35_cen = ck_stb5;
    assign clk_3p35b_cen = ck_stb6;

    always @(negedge i_clk) begin
            { ck_stb7, counter7 } <= counter7 + 16'd4891;
    end

    always @(negedge i_clk) begin
            { ck_stb8, counter8 } <= counter8 + 16'd4891;
    end

    assign clk_4_cen = ck_stb7;
    assign clk_4b_cen = ck_stb8;
endmodule