data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:40: Cannot find include file: c_functions.v\n`include "c_functions.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v.v\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v.sv\n             c_functions.v\n             c_functions.v.v\n             c_functions.v.sv\n             obj_dir/c_functions.v\n             obj_dir/c_functions.v.v\n             obj_dir/c_functions.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:41: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:42: Cannot find include file: vcr_constants.v\n`include "vcr_constants.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:66: Define or directive not defined: \'`SW_ALLOC_TYPE_SEP_IF\'\n   parameter vc_allocator_type = `SW_ALLOC_TYPE_SEP_IF;\n                                 ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:66: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter vc_allocator_type = `SW_ALLOC_TYPE_SEP_IF;\n                                                      ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:69: Define or directive not defined: \'`ARBITER_TYPE_ROUND_ROBIN_BINARY\'\n   parameter vc_arbiter_type = `ARBITER_TYPE_ROUND_ROBIN_BINARY;\n                               ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:69: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter vc_arbiter_type = `ARBITER_TYPE_ROUND_ROBIN_BINARY;\n                                                               ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:72: Define or directive not defined: \'`VC_ALLOC_TYPE_SEP_IF\'\n   parameter sw_allocator_type = `VC_ALLOC_TYPE_SEP_IF;\n                                 ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:72: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter sw_allocator_type = `VC_ALLOC_TYPE_SEP_IF;\n                                                      ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:75: Define or directive not defined: \'`ARBITER_TYPE_ROUND_ROBIN_BINARY\'\n   parameter sw_arbiter_type = `ARBITER_TYPE_ROUND_ROBIN_BINARY;\n                               ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:75: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter sw_arbiter_type = `ARBITER_TYPE_ROUND_ROBIN_BINARY;\n                                                               ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:78: Define or directive not defined: \'`SW_ALLOC_SPEC_TYPE_REQ\'\n   parameter spec_type = `SW_ALLOC_SPEC_TYPE_REQ;\n                         ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:78: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter spec_type = `SW_ALLOC_SPEC_TYPE_REQ;\n                                                ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:80: Define or directive not defined: \'`RESET_TYPE_ASYNC\'\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:80: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                                           ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:176: Define or directive not defined: \'`BINARY_OP_OR\'\n       .op(`BINARY_OP_OR))\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:191: Define or directive not defined: \'`VC_ALLOC_TYPE_SEP_IF\'\n      if(vc_allocator_type == `VC_ALLOC_TYPE_SEP_IF)\n                              ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:191: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      if(vc_allocator_type == `VC_ALLOC_TYPE_SEP_IF)\n                                                   ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:217: Define or directive not defined: \'`VC_ALLOC_TYPE_SEP_OF\'\n      else if(vc_allocator_type == `VC_ALLOC_TYPE_SEP_OF)\n                                   ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:243: Define or directive not defined: \'`VC_ALLOC_TYPE_WF_BASE\'\n      else if((vc_allocator_type >= `VC_ALLOC_TYPE_WF_BASE) &&\n                                    ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:244: Define or directive not defined: \'`VC_ALLOC_TYPE_WF_LIMIT\'\n       (vc_allocator_type <= `VC_ALLOC_TYPE_WF_LIMIT))\n                             ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:255: Define or directive not defined: \'`VC_ALLOC_TYPE_WF_BASE\'\n        .wf_alloc_type(vc_allocator_type - `VC_ALLOC_TYPE_WF_BASE),\n                                           ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:255: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        .wf_alloc_type(vc_allocator_type - `VC_ALLOC_TYPE_WF_BASE),\n                                                                 ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:286: Define or directive not defined: \'`BINARY_OP_OR\'\n       .op(`BINARY_OP_OR))\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:299: syntax error, unexpected generate\n   generate\n   ^~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:301: Define or directive not defined: \'`SW_ALLOC_TYPE_SEP_IF\'\n      if(sw_allocator_type == `SW_ALLOC_TYPE_SEP_IF)\n                              ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:325: Define or directive not defined: \'`SW_ALLOC_TYPE_SEP_OF\'\n      else if(sw_allocator_type == `SW_ALLOC_TYPE_SEP_OF)\n                                   ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:349: Define or directive not defined: \'`SW_ALLOC_TYPE_WF_BASE\'\n      else if((sw_allocator_type >= `SW_ALLOC_TYPE_WF_BASE) &&\n                                    ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:350: Define or directive not defined: \'`SW_ALLOC_TYPE_WF_LIMIT\'\n       (sw_allocator_type <= `SW_ALLOC_TYPE_WF_LIMIT))\n                             ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:356: Define or directive not defined: \'`SW_ALLOC_TYPE_WF_BASE\'\n        .wf_alloc_type(sw_allocator_type - `SW_ALLOC_TYPE_WF_BASE),\n                                           ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:382: syntax error, unexpected generate\n   generate\n   ^~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:418: syntax error, unexpected end\n end\n ^~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/vcr_alloc_mac.v:478: syntax error, unexpected end\n end\n ^~~\n%Error: Cannot continue\n'
module vcr_alloc_mac
  (clk, reset, route_ip_ivc_op, route_ip_ivc_orc, allocated_ip_ivc, 
   flit_valid_ip_ivc, flit_head_ip_ivc, flit_tail_ip_ivc, elig_op_ovc, 
   free_nonspec_ip_ivc, vc_active_op, vc_gnt_ip_ivc, vc_sel_ip_ivc_ovc, 
   vc_gnt_op_ovc, vc_sel_op_ovc_ip, vc_sel_op_ovc_ivc, sw_active_op, 
   sw_gnt_ip, sw_sel_ip_ivc, sw_gnt_op, sw_sel_op_ip, sw_sel_op_ivc, 
   flit_head_op, flit_tail_op, xbr_ctrl_op_ip);
   
`include "c_functions.v"
`include "c_constants.v"
`include "vcr_constants.v"
   

   parameter num_message_classes = 2;
   

   parameter num_resource_classes = 2;
   

   localparam num_packet_classes = num_message_classes * num_resource_classes;
   

   parameter num_vcs_per_class = 1;
   

   localparam num_vcs = num_packet_classes * num_vcs_per_class;
   

   parameter num_ports = 5;
   

   localparam port_idx_width = clogb(num_ports);
   

   parameter vc_allocator_type = `SW_ALLOC_TYPE_SEP_IF;
   

   parameter vc_arbiter_type = `ARBITER_TYPE_ROUND_ROBIN_BINARY;
   

   parameter sw_allocator_type = `VC_ALLOC_TYPE_SEP_IF;
   

   parameter sw_arbiter_type = `ARBITER_TYPE_ROUND_ROBIN_BINARY;
   

   parameter spec_type = `SW_ALLOC_SPEC_TYPE_REQ;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   input clk;
   input reset;
   

   input [0:num_ports*num_vcs*num_ports-1] route_ip_ivc_op;
   

   input [0:num_ports*num_vcs*num_resource_classes-1] route_ip_ivc_orc;
   

   input [0:num_ports*num_vcs-1] 		      allocated_ip_ivc;
   

   input [0:num_ports*num_vcs-1] 		      flit_valid_ip_ivc;
   

   input [0:num_ports*num_vcs-1] 		      flit_head_ip_ivc;
   

   input [0:num_ports*num_vcs-1] 		      flit_tail_ip_ivc;
   

   input [0:num_ports*num_vcs-1] 		      elig_op_ovc;
   

   input [0:num_ports*num_vcs-1] 		      free_nonspec_ip_ivc;
   

   output [0:num_ports-1] 			      vc_active_op;
   wire [0:num_ports-1] 			      vc_active_op;
   

   output [0:num_ports*num_vcs-1] 		      vc_gnt_ip_ivc;
   wire [0:num_ports*num_vcs-1] 		      vc_gnt_ip_ivc;
   

   output [0:num_ports*num_vcs*num_vcs-1] 	      vc_sel_ip_ivc_ovc;
   wire [0:num_ports*num_vcs*num_vcs-1] 	      vc_sel_ip_ivc_ovc;
   

   output [0:num_ports*num_vcs-1] 		      vc_gnt_op_ovc;
   wire [0:num_ports*num_vcs-1] 		      vc_gnt_op_ovc;
   

   output [0:num_ports*num_vcs*num_ports-1] 	      vc_sel_op_ovc_ip;
   wire [0:num_ports*num_vcs*num_ports-1] 	      vc_sel_op_ovc_ip;
   

   output [0:num_ports*num_vcs*num_vcs-1] 	      vc_sel_op_ovc_ivc;
   wire [0:num_ports*num_vcs*num_vcs-1] 	      vc_sel_op_ovc_ivc;
   

   output [0:num_ports-1] 			      sw_active_op;
   wire [0:num_ports-1] 			      sw_active_op;
   

   output [0:num_ports-1] 			      sw_gnt_ip;
   wire [0:num_ports-1] 			      sw_gnt_ip;
   

   output [0:num_ports*num_vcs-1] 		      sw_sel_ip_ivc;
   wire [0:num_ports*num_vcs-1] 		      sw_sel_ip_ivc;
   

   output [0:num_ports-1] 			      sw_gnt_op;
   wire [0:num_ports-1] 			      sw_gnt_op;
   

   output [0:num_ports*num_ports-1] 		      sw_sel_op_ip;
   wire [0:num_ports*num_ports-1] 		      sw_sel_op_ip;
   

   output [0:num_ports*num_vcs-1] 		      sw_sel_op_ivc;
   wire [0:num_ports*num_vcs-1] 		      sw_sel_op_ivc;
   

   output [0:num_ports-1] 			      flit_head_op;
   wire [0:num_ports-1] 			      flit_head_op;
   

   output [0:num_ports-1] 			      flit_tail_op;
   wire [0:num_ports-1] 			      flit_tail_op;
   

   output [0:num_ports*num_ports-1] 		      xbr_ctrl_op_ip;
   wire [0:num_ports*num_ports-1] 		      xbr_ctrl_op_ip;
   
   wire [0:num_ports*num_vcs-1] 		      vc_req_ip_ivc;
   assign vc_req_ip_ivc = flit_valid_ip_ivc & ~allocated_ip_ivc;
   
   wire [0:num_ports-1] 			      vc_active_ip;
   c_reduce_bits
     #(.num_ports(num_ports),
       .width(num_vcs),
       .op(`BINARY_OP_OR))
   vc_active_ip_rb
     (.data_in(vc_req_ip_ivc),
      .data_out(vc_active_ip));
   
   c_select_mofn
     #(.num_ports(num_ports*num_vcs),
       .width(num_ports))
   vc_active_op_sel
     (.select(vc_req_ip_ivc),
      .data_in(route_ip_ivc_op),
      .data_out(vc_active_op));
   
   generate
      
      if(vc_allocator_type == `VC_ALLOC_TYPE_SEP_IF)
	begin
	   
	   vcr_vc_alloc_sep_if
	     #(.num_message_classes(num_message_classes),
	       .num_resource_classes(num_resource_classes),
	       .num_vcs_per_class(num_vcs_per_class),
	       .num_ports(num_ports),
	       .arbiter_type(vc_arbiter_type),
	       .reset_type(reset_type))
	   vc_core_sep_if
	     (.clk(clk),
	      .reset(reset),
	      .active_ip(vc_active_ip),
	      .active_op(vc_active_op),
	      .route_ip_ivc_op(route_ip_ivc_op),
	      .route_ip_ivc_orc(route_ip_ivc_orc),
	      .elig_op_ovc(elig_op_ovc),
	      .req_ip_ivc(vc_req_ip_ivc),
	      .gnt_ip_ivc(vc_gnt_ip_ivc),
	      .sel_ip_ivc_ovc(vc_sel_ip_ivc_ovc),
	      .gnt_op_ovc(vc_gnt_op_ovc),
	      .sel_op_ovc_ip(vc_sel_op_ovc_ip),
	      .sel_op_ovc_ivc(vc_sel_op_ovc_ivc));
	   
	end
      else if(vc_allocator_type == `VC_ALLOC_TYPE_SEP_OF)
	begin
	   
	   vcr_vc_alloc_sep_of
	     #(.num_message_classes(num_message_classes),
	       .num_resource_classes(num_resource_classes),
	       .num_vcs_per_class(num_vcs_per_class),
	       .num_ports(num_ports),
	       .arbiter_type(vc_arbiter_type),
	       .reset_type(reset_type))
	   vc_core_sep_of
	     (.clk(clk),
	      .reset(reset),
	      .active_ip(vc_active_ip),
	      .active_op(vc_active_op),
	      .route_ip_ivc_op(route_ip_ivc_op),
	      .route_ip_ivc_orc(route_ip_ivc_orc),
	      .elig_op_ovc(elig_op_ovc),
	      .req_ip_ivc(vc_req_ip_ivc),
	      .gnt_ip_ivc(vc_gnt_ip_ivc),
	      .sel_ip_ivc_ovc(vc_sel_ip_ivc_ovc),
	      .gnt_op_ovc(vc_gnt_op_ovc),
	      .sel_op_ovc_ip(vc_sel_op_ovc_ip),
	      .sel_op_ovc_ivc(vc_sel_op_ovc_ivc));
	   
	end
      else if((vc_allocator_type >= `VC_ALLOC_TYPE_WF_BASE) &&
	      (vc_allocator_type <= `VC_ALLOC_TYPE_WF_LIMIT))
	begin
	   
	   wire vc_active;
	   assign vc_active = |vc_active_ip;
	   
	   vcr_vc_alloc_wf
	     #(.num_message_classes(num_message_classes),
	       .num_resource_classes(num_resource_classes),
	       .num_vcs_per_class(num_vcs_per_class),
	       .num_ports(num_ports),
	       .wf_alloc_type(vc_allocator_type - `VC_ALLOC_TYPE_WF_BASE),
	       .reset_type(reset_type))
	   vc_core_wf
	     (.clk(clk),
	      .reset(reset),
	      .active(vc_active),
	      .route_ip_ivc_op(route_ip_ivc_op),
	      .route_ip_ivc_orc(route_ip_ivc_orc),
	      .elig_op_ovc(elig_op_ovc),
	      .req_ip_ivc(vc_req_ip_ivc),
	      .gnt_ip_ivc(vc_gnt_ip_ivc),
	      .sel_ip_ivc_ovc(vc_sel_ip_ivc_ovc),
	      .gnt_op_ovc(vc_gnt_op_ovc),
	      .sel_op_ovc_ip(vc_sel_op_ovc_ip),
	      .sel_op_ovc_ivc(vc_sel_op_ovc_ivc));
	   
	end
      
   endgenerate
   
   wire [0:num_ports*num_vcs-1] sw_req_nonspec_ip_ivc;
   assign sw_req_nonspec_ip_ivc
     = allocated_ip_ivc & flit_valid_ip_ivc & free_nonspec_ip_ivc;
   
   wire [0:num_ports*num_vcs-1] sw_req_spec_ip_ivc;
   assign sw_req_spec_ip_ivc = ~allocated_ip_ivc & flit_valid_ip_ivc;
   
   wire [0:num_ports-1] 	sw_active_ip;
   c_reduce_bits
     #(.num_ports(num_ports),
       .width(num_vcs),
       .op(`BINARY_OP_OR))
   sw_active_ip_rb
     (.data_in(flit_valid_ip_ivc),
      .data_out(sw_active_ip));
   
   c_select_mofn
     #(.num_ports(num_ports*num_vcs),
       .width(num_ports))
   sw_active_op_sel
     (.select(flit_valid_ip_ivc),
      .data_in(route_ip_ivc_op),
      .data_out(sw_active_op));
   
   generate
      
      if(sw_allocator_type == `SW_ALLOC_TYPE_SEP_IF)
	begin
	   
	   vcr_sw_alloc_sep_if
	     #(.num_vcs(num_vcs),
	       .num_ports(num_ports),
	       .arbiter_type(sw_arbiter_type),
	       .spec_type(spec_type),
	       .reset_type(reset_type))
	   sw_core_sep_if
	     (.clk(clk),
	      .reset(reset),
	      .active_ip(sw_active_ip),
	      .active_op(sw_active_op),
	      .route_ip_ivc_op(route_ip_ivc_op),
	      .req_nonspec_ip_ivc(sw_req_nonspec_ip_ivc),
	      .req_spec_ip_ivc(sw_req_spec_ip_ivc),
	      .sel_ip_ivc(sw_sel_ip_ivc),
	      .gnt_ip(sw_gnt_ip),
	      .gnt_op(sw_gnt_op),
	      .sel_op_ip(sw_sel_op_ip),
	      .sel_op_ivc(sw_sel_op_ivc));
	   
	end
      else if(sw_allocator_type == `SW_ALLOC_TYPE_SEP_OF)
	begin
	   
	   vcr_sw_alloc_sep_of
	     #(.num_vcs(num_vcs),
	       .num_ports(num_ports),
	       .arbiter_type(sw_arbiter_type),
	       .spec_type(spec_type),
	       .reset_type(reset_type))
	   sw_core_sep_of
	     (.clk(clk),
	      .reset(reset),
	      .active_ip(sw_active_ip),
	      .active_op(sw_active_op),
	      .route_ip_ivc_op(route_ip_ivc_op),
	      .req_nonspec_ip_ivc(sw_req_nonspec_ip_ivc),
	      .req_spec_ip_ivc(sw_req_spec_ip_ivc),
	      .sel_ip_ivc(sw_sel_ip_ivc),
	      .gnt_ip(sw_gnt_ip),
	      .gnt_op(sw_gnt_op),
	      .sel_op_ip(sw_sel_op_ip),
	      .sel_op_ivc(sw_sel_op_ivc));
	   
	end
      else if((sw_allocator_type >= `SW_ALLOC_TYPE_WF_BASE) &&
	      (sw_allocator_type <= `SW_ALLOC_TYPE_WF_LIMIT))
	begin
	   
	   vcr_sw_alloc_wf
	     #(.num_vcs(num_vcs),
	       .num_ports(num_ports),
	       .wf_alloc_type(sw_allocator_type - `SW_ALLOC_TYPE_WF_BASE),
	       .arbiter_type(sw_arbiter_type),
	       .spec_type(spec_type),
	       .reset_type(reset_type))
	   sw_core_wf
	     (.clk(clk),
	      .reset(reset),
	      .active_ip(sw_active_ip),
	      .route_ip_ivc_op(route_ip_ivc_op),
	      .req_nonspec_ip_ivc(sw_req_nonspec_ip_ivc),
	      .req_spec_ip_ivc(sw_req_spec_ip_ivc),
	      .sel_ip_ivc(sw_sel_ip_ivc),
	      .gnt_ip(sw_gnt_ip),
	      .gnt_op(sw_gnt_op),
	      .sel_op_ip(sw_sel_op_ip),
	      .sel_op_ivc(sw_sel_op_ivc));
	   
	end
      
   endgenerate
   
   wire [0:num_ports-1] flit_head_ip;
   wire [0:num_ports-1] flit_tail_ip;
   
   genvar ip;
   
   generate
      
      for(ip = 0; ip < num_ports; ip = ip + 1)
	begin:ips
	   
	   wire [0:num_vcs-1] sw_sel_ivc;
	   assign sw_sel_ivc = sw_sel_ip_ivc[ip*num_vcs:(ip+1)*num_vcs-1];
	   
	   wire [0:num_vcs-1] flit_head_ivc;
	   assign flit_head_ivc = flit_head_ip_ivc[ip*num_vcs:(ip+1)*num_vcs-1];
	   
	   wire 	      flit_head;
	   c_select_1ofn
	     #(.num_ports(num_vcs),
	       .width(1))
	   flit_head_sel
	     (.select(sw_sel_ivc),
	      .data_in(flit_head_ivc),
	      .data_out(flit_head));
	   
	   assign flit_head_ip[ip] = flit_head;
	   
	   wire [0:num_vcs-1] flit_tail_ivc;
	   assign flit_tail_ivc = flit_tail_ip_ivc[ip*num_vcs:(ip+1)*num_vcs-1];
	   
	   wire 	      flit_tail;
	   c_select_1ofn
	     #(.num_ports(num_vcs),
	       .width(1))
	   flit_tail_sel
	     (.select(sw_sel_ivc),
	      .data_in(flit_tail_ivc),
	      .data_out(flit_tail));
	   
	   assign flit_tail_ip[ip] = flit_tail;
	   
	end
      
   endgenerate
   
   genvar op;
   
   generate
      
      for(op = 0; op < num_ports; op = op + 1)
	begin:ops
	   
	   wire [0:num_ports-1] sw_sel_ip;
	   assign sw_sel_ip = sw_sel_op_ip[op*num_ports:(op+1)*num_ports-1];
	   
	   wire 		flit_head;
	   c_select_1ofn
	     #(.num_ports(num_ports),
	       .width(1))
	   flit_head_sel
	     (.select(sw_sel_ip),
	      .data_in(flit_head_ip),
	      .data_out(flit_head));
	   
	   assign flit_head_op[op] = flit_head;
	   
	   wire 		flit_tail;
	   c_select_1ofn
	     #(.num_ports(num_ports),
	       .width(1))
	   flit_tail_sel
	     (.select(sw_sel_ip),
	      .data_in(flit_tail_ip),
	      .data_out(flit_tail));
	   
	   assign flit_tail_op[op] = flit_tail;
	   
	   wire [0:num_ports-1] xbr_ctrl_ip;
	   
	   wire 		sw_active;
	   assign sw_active = sw_active_op[op];
	   
	   wire 		active;
	   assign active = sw_active | (|xbr_ctrl_ip);
	   
	   wire [0:num_ports-1] xbr_ctrl_ip_s, xbr_ctrl_ip_q;
	   assign xbr_ctrl_ip_s = sw_sel_ip;
	   c_dff
	     #(.width(num_ports),
	       .reset_type(reset_type))
	   xbr_ctrl_ipq
	     (.clk(clk),
	      .reset(reset),
	      .active(active),
	      .d(xbr_ctrl_ip_s),
	      .q(xbr_ctrl_ip_q));
	   
	   assign xbr_ctrl_ip = xbr_ctrl_ip_q;
	   
	   assign xbr_ctrl_op_ip[op*num_ports:(op+1)*num_ports-1] = xbr_ctrl_ip;
	   
	end
      
   endgenerate
   
endmodule
module vcr_alloc_mac
  (clk, reset, route_ip_ivc_op, route_ip_ivc_orc, allocated_ip_ivc, 
   flit_valid_ip_ivc, flit_head_ip_ivc, flit_tail_ip_ivc, elig_op_ovc, 
   free_nonspec_ip_ivc, vc_active_op, vc_gnt_ip_ivc, vc_sel_ip_ivc_ovc, 
   vc_gnt_op_ovc, vc_sel_op_ovc_ip, vc_sel_op_ovc_ivc, sw_active_op, 
   sw_gnt_ip, sw_sel_ip_ivc, sw_gnt_op, sw_sel_op_ip, sw_sel_op_ivc, 
   flit_head_op, flit_tail_op, xbr_ctrl_op_ip);

   
`include "c_functions.v"
`include "c_constants.v"
`include "vcr_constants.v"
   

   parameter num_message_classes = 2;
   

   parameter num_resource_classes = 2;
   

   localparam num_packet_classes = num_message_classes * num_resource_classes;
   

   parameter num_vcs_per_class = 1;
   

   localparam num_vcs = num_packet_classes * num_vcs_per_class;
   

   parameter num_ports = 5;
   

   localparam port_idx_width = clogb(num_ports);
   

   parameter vc_allocator_type = `SW_ALLOC_TYPE_SEP_IF;
   

   parameter vc_arbiter_type = `ARBITER_TYPE_ROUND_ROBIN_BINARY;
   

   parameter sw_allocator_type = `VC_ALLOC_TYPE_SEP_IF;
   

   parameter sw_arbiter_type = `ARBITER_TYPE_ROUND_ROBIN_BINARY;
   

   parameter spec_type = `SW_ALLOC_SPEC_TYPE_REQ;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   input clk;
   input reset;
   

   input [0:num_ports*num_vcs*num_ports-1] route_ip_ivc_op;
   

   input [0:num_ports*num_vcs*num_resource_classes-1] route_ip_ivc_orc;
   

   input [0:num_ports*num_vcs-1] 		      allocated_ip_ivc;
   

   input [0:num_ports*num_vcs-1] 		      flit_valid_ip_ivc;
   

   input [0:num_ports*num_vcs-1] 		      flit_head_ip_ivc;
   

   input [0:num_ports*num_vcs-1] 		      flit_tail_ip_ivc;
   

   input [0:num_ports*num_vcs-1] 		      elig_op_ovc;
   

   input [0:num_ports*num_vcs-1] 		      free_nonspec_ip_ivc;
   

   output [0:num_ports-1] 			      vc_active_op;
   wire [0:num_ports-1] 			      vc_active_op;
   

   output [0:num_ports*num_vcs-1] 		      vc_gnt_ip_ivc;
   wire [0:num_ports*num_vcs-1] 		      vc_gnt_ip_ivc;
   

   output [0:num_ports*num_vcs*num_vcs-1] 	      vc_sel_ip_ivc_ovc;
   wire [0:num_ports*num_vcs*num_vcs-1] 	      vc_sel_ip_ivc_ovc;
   

   output [0:num_ports*num_vcs-1] 		      vc_gnt_op_ovc;
   wire [0:num_ports*num_vcs-1] 		      vc_gnt_op_ovc;
   

   output [0:num_ports*num_vcs*num_ports-1] 	      vc_sel_op_ovc_ip;
   wire [0:num_ports*num_vcs*num_ports-1] 	      vc_sel_op_ovc_ip;
   

   output [0:num_ports*num_vcs*num_vcs-1] 	      vc_sel_op_ovc_ivc;
   wire [0:num_ports*num_vcs*num_vcs-1] 	      vc_sel_op_ovc_ivc;
   

   output [0:num_ports-1] 			      sw_active_op;
   wire [0:num_ports-1] 			      sw_active_op;
   

   output [0:num_ports-1] 			      sw_gnt_ip;
   wire [0:num_ports-1] 			      sw_gnt_ip;
   

   output [0:num_ports*num_vcs-1] 		      sw_sel_ip_ivc;
   wire [0:num_ports*num_vcs-1] 		      sw_sel_ip_ivc;
   

   output [0:num_ports-1] 			      sw_gnt_op;
   wire [0:num_ports-1] 			      sw_gnt_op;
   

   output [0:num_ports*num_ports-1] 		      sw_sel_op_ip;
   wire [0:num_ports*num_ports-1] 		      sw_sel_op_ip;
   

   output [0:num_ports*num_vcs-1] 		      sw_sel_op_ivc;
   wire [0:num_ports*num_vcs-1] 		      sw_sel_op_ivc;
   

   output [0:num_ports-1] 			      flit_head_op;
   wire [0:num_ports-1] 			      flit_head_op;
   

   output [0:num_ports-1] 			      flit_tail_op;
   wire [0:num_ports-1] 			      flit_tail_op;
   

   output [0:num_ports*num_ports-1] 		      xbr_ctrl_op_ip;
   wire [0:num_ports*num_ports-1] 		      xbr_ctrl_op_ip;
   
   wire [0:num_ports*num_vcs-1] 		      vc_req_ip_ivc;
   assign vc_req_ip_ivc = flit_valid_ip_ivc & ~allocated_ip_ivc;
   
   wire [0:num_ports-1] 			      vc_active_ip;
   c_reduce_bits
     #(.num_ports(num_ports),
       .width(num_vcs),
       .op(`BINARY_OP_OR))
   vc_active_ip_rb
     (.data_in(vc_req_ip_ivc),
      .data_out(vc_active_ip));
   
   c_select_mofn
     #(.num_ports(num_ports*num_vcs),
       .width(num_ports))
   vc_active_op_sel
     (.select(vc_req_ip_ivc),
      .data_in(route_ip_ivc_op),
      .data_out(vc_active_op));
   
   generate
      
      if(vc_allocator_type == `VC_ALLOC_TYPE_SEP_IF)
	begin
	   
	   vcr_vc_alloc_sep_if
	     #(.num_message_classes(num_message_classes),
	       .num_resource_classes(num_resource_classes),
	       .num_vcs_per_class(num_vcs_per_class),
	       .num_ports(num_ports),
	       .arbiter_type(vc_arbiter_type),
	       .reset_type(reset_type))
	   vc_core_sep_if
	     (.clk(clk),
	      .reset(reset),
	      .active_ip(vc_active_ip),
	      .active_op(vc_active_op),
	      .route_ip_ivc_op(route_ip_ivc_op),
	      .route_ip_ivc_orc(route_ip_ivc_orc),
	      .elig_op_ovc(elig_op_ovc),
	      .req_ip_ivc(vc_req_ip_ivc),
	      .gnt_ip_ivc(vc_gnt_ip_ivc),
	      .sel_ip_ivc_ovc(vc_sel_ip_ivc_ovc),
	      .gnt_op_ovc(vc_gnt_op_ovc),
	      .sel_op_ovc_ip(vc_sel_op_ovc_ip),
	      .sel_op_ovc_ivc(vc_sel_op_ovc_ivc));
	   
	end
      else if(vc_allocator_type == `VC_ALLOC_TYPE_SEP_OF)
	begin
	   
	   vcr_vc_alloc_sep_of
	     #(.num_message_classes(num_message_classes),
	       .num_resource_classes(num_resource_classes),
	       .num_vcs_per_class(num_vcs_per_class),
	       .num_ports(num_ports),
	       .arbiter_type(vc_arbiter_type),
	       .reset_type(reset_type))
	   vc_core_sep_of
	     (.clk(clk),
	      .reset(reset),
	      .active_ip(vc_active_ip),
	      .active_op(vc_active_op),
	      .route_ip_ivc_op(route_ip_ivc_op),
	      .route_ip_ivc_orc(route_ip_ivc_orc),
	      .elig_op_ovc(elig_op_ovc),
	      .req_ip_ivc(vc_req_ip_ivc),
	      .gnt_ip_ivc(vc_gnt_ip_ivc),
	      .sel_ip_ivc_ovc(vc_sel_ip_ivc_ovc),
	      .gnt_op_ovc(vc_gnt_op_ovc),
	      .sel_op_ovc_ip(vc_sel_op_ovc_ip),
	      .sel_op_ovc_ivc(vc_sel_op_ovc_ivc));
	   
	end
      else if((vc_allocator_type >= `VC_ALLOC_TYPE_WF_BASE) &&
	      (vc_allocator_type <= `VC_ALLOC_TYPE_WF_LIMIT))
	begin
	   
	   wire vc_active;
	   assign vc_active = |vc_active_ip;
	   
	   vcr_vc_alloc_wf
	     #(.num_message_classes(num_message_classes),
	       .num_resource_classes(num_resource_classes),
	       .num_vcs_per_class(num_vcs_per_class),
	       .num_ports(num_ports),
	       .wf_alloc_type(vc_allocator_type - `VC_ALLOC_TYPE_WF_BASE),
	       .reset_type(reset_type))
	   vc_core_wf
	     (.clk(clk),
	      .reset(reset),
	      .active(vc_active),
	      .route_ip_ivc_op(route_ip_ivc_op),
	      .route_ip_ivc_orc(route_ip_ivc_orc),
	      .elig_op_ovc(elig_op_ovc),
	      .req_ip_ivc(vc_req_ip_ivc),
	      .gnt_ip_ivc(vc_gnt_ip_ivc),
	      .sel_ip_ivc_ovc(vc_sel_ip_ivc_ovc),
	      .gnt_op_ovc(vc_gnt_op_ovc),
	      .sel_op_ovc_ip(vc_sel_op_ovc_ip),
	      .sel_op_ovc_ivc(vc_sel_op_ovc_ivc));
	   
	end
      
   endgenerate
   
   wire [0:num_ports*num_vcs-1] sw_req_nonspec_ip_ivc;
   assign sw_req_nonspec_ip_ivc
     = allocated_ip_ivc & flit_valid_ip_ivc & free_nonspec_ip_ivc;
   
   wire [0:num_ports*num_vcs-1] sw_req_spec_ip_ivc;
   assign sw_req_spec_ip_ivc = ~allocated_ip_ivc & flit_valid_ip_ivc;
   
   wire [0:num_ports-1] 	sw_active_ip;
   c_reduce_bits
     #(.num_ports(num_ports),
       .width(num_vcs),
       .op(`BINARY_OP_OR))
   sw_active_ip_rb
     (.data_in(flit_valid_ip_ivc),
      .data_out(sw_active_ip));
   
   c_select_mofn
     #(.num_ports(num_ports*num_vcs),
       .width(num_ports))
   sw_active_op_sel
     (.select(flit_valid_ip_ivc),
      .data_in(route_ip_ivc_op),
      .data_out(sw_active_op));
   
   generate
      
      if(sw_allocator_type == `SW_ALLOC_TYPE_SEP_IF)
	begin
	   
	   vcr_sw_alloc_sep_if
	     #(.num_vcs(num_vcs),
	       .num_ports(num_ports),
	       .arbiter_type(sw_arbiter_type),
	       .spec_type(spec_type),
	       .reset_type(reset_type))
	   sw_core_sep_if
	     (.clk(clk),
	      .reset(reset),
	      .active_ip(sw_active_ip),
	      .active_op(sw_active_op),
	      .route_ip_ivc_op(route_ip_ivc_op),
	      .req_nonspec_ip_ivc(sw_req_nonspec_ip_ivc),
	      .req_spec_ip_ivc(sw_req_spec_ip_ivc),
	      .sel_ip_ivc(sw_sel_ip_ivc),
	      .gnt_ip(sw_gnt_ip),
	      .gnt_op(sw_gnt_op),
	      .sel_op_ip(sw_sel_op_ip),
	      .sel_op_ivc(sw_sel_op_ivc));
	   
	end
      else if(sw_allocator_type == `SW_ALLOC_TYPE_SEP_OF)
	begin
	   
	   vcr_sw_alloc_sep_of
	     #(.num_vcs(num_vcs),
	       .num_ports(num_ports),
	       .arbiter_type(sw_arbiter_type),
	       .spec_type(spec_type),
	       .reset_type(reset_type))
	   sw_core_sep_of
	     (.clk(clk),
	      .reset(reset),
	      .active_ip(sw_active_ip),
	      .active_op(sw_active_op),
	      .route_ip_ivc_op(route_ip_ivc_op),
	      .req_nonspec_ip_ivc(sw_req_nonspec_ip_ivc),
	      .req_spec_ip_ivc(sw_req_spec_ip_ivc),
	      .sel_ip_ivc(sw_sel_ip_ivc),
	      .gnt_ip(sw_gnt_ip),
	      .gnt_op(sw_gnt_op),
	      .sel_op_ip(sw_sel_op_ip),
	      .sel_op_ivc(sw_sel_op_ivc));
	   
	end
      else if((sw_allocator_type >= `SW_ALLOC_TYPE_WF_BASE) &&
	      (sw_allocator_type <= `SW_ALLOC_TYPE_WF_LIMIT))
	begin
	   
	   vcr_sw_alloc_wf
	     #(.num_vcs(num_vcs),
	       .num_ports(num_ports),
	       .wf_alloc_type(sw_allocator_type - `SW_ALLOC_TYPE_WF_BASE),
	       .arbiter_type(sw_arbiter_type),
	       .spec_type(spec_type),
	       .reset_type(reset_type))
	   sw_core_wf
	     (.clk(clk),
	      .reset(reset),
	      .active_ip(sw_active_ip),
	      .route_ip_ivc_op(route_ip_ivc_op),
	      .req_nonspec_ip_ivc(sw_req_nonspec_ip_ivc),
	      .req_spec_ip_ivc(sw_req_spec_ip_ivc),
	      .sel_ip_ivc(sw_sel_ip_ivc),
	      .gnt_ip(sw_gnt_ip),
	      .gnt_op(sw_gnt_op),
	      .sel_op_ip(sw_sel_op_ip),
	      .sel_op_ivc(sw_sel_op_ivc));
	   
	end
      
   endgenerate
   
   wire [0:num_ports-1] flit_head_ip;
   wire [0:num_ports-1] flit_tail_ip;
   
   genvar ip;
   
   generate
      
      for(ip = 0; ip < num_ports; ip = ip + 1)
	begin:ips
	   
	   wire [0:num_vcs-1] sw_sel_ivc;
	   assign sw_sel_ivc = sw_sel_ip_ivc[ip*num_vcs:(ip+1)*num_vcs-1];
	   
	   wire [0:num_vcs-1] flit_head_ivc;
	   assign flit_head_ivc = flit_head_ip_ivc[ip*num_vcs:(ip+1)*num_vcs-1];
	   
	   wire 	      flit_head;
	   c_select_1ofn
	     #(.num_ports(num_vcs),
	       .width(1))
	   flit_head_sel
	     (.select(sw_sel_ivc),
	      .data_in(flit_head_ivc),
	      .data_out(flit_head));
	   
	   assign flit_head_ip[ip] = flit_head;
	   
	   wire [0:num_vcs-1] flit_tail_ivc;
	   assign flit_tail_ivc = flit_tail_ip_ivc[ip*num_vcs:(ip+1)*num_vcs-1];
	   
	   wire 	      flit_tail;
	   c_select_1ofn
	     #(.num_ports(num_vcs),
	       .width(1))
	   flit_tail_sel
	     (.select(sw_sel_ivc),
	      .data_in(flit_tail_ivc),
	      .data_out(flit_tail));
	   
	   assign flit_tail_ip[ip] = flit_tail;
	   
	end
      
   endgenerate
   
   genvar op;
   
   generate
      
      for(op = 0; op < num_ports; op = op + 1)
	begin:ops
	   
	   wire [0:num_ports-1] sw_sel_ip;
	   assign sw_sel_ip = sw_sel_op_ip[op*num_ports:(op+1)*num_ports-1];
	   
	   wire 		flit_head;
	   c_select_1ofn
	     #(.num_ports(num_ports),
	       .width(1))
	   flit_head_sel
	     (.select(sw_sel_ip),
	      .data_in(flit_head_ip),
	      .data_out(flit_head));
	   
	   assign flit_head_op[op] = flit_head;
	   
	   wire 		flit_tail;
	   c_select_1ofn
	     #(.num_ports(num_ports),
	       .width(1))
	   flit_tail_sel
	     (.select(sw_sel_ip),
	      .data_in(flit_tail_ip),
	      .data_out(flit_tail));
	   
	   assign flit_tail_op[op] = flit_tail;
	   
	   wire [0:num_ports-1] xbr_ctrl_ip;
	   
	   wire 		sw_active;
	   assign sw_active = sw_active_op[op];
	   
	   wire 		active;
	   assign active = sw_active | (|xbr_ctrl_ip);
	   
	   wire [0:num_ports-1] xbr_ctrl_ip_s, xbr_ctrl_ip_q;
	   assign xbr_ctrl_ip_s = sw_sel_ip;
	   c_dff
	     #(.width(num_ports),
	       .reset_type(reset_type))
	   xbr_ctrl_ipq
	     (.clk(clk),
	      .reset(reset),
	      .active(active),
	      .d(xbr_ctrl_ip_s),
	      .q(xbr_ctrl_ip_q));
	   
	   assign xbr_ctrl_ip = xbr_ctrl_ip_q;
	   
	   assign xbr_ctrl_op_ip[op*num_ports:(op+1)*num_ports-1] = xbr_ctrl_ip;
	   
	end
      
   endgenerate
   
endmodule