data/full_repos/permissive/488093047/Verilog Codes/D_Flipflop.v
1: b'%Error: Cannot find file containing module: Codes,data/full_repos/permissive/488093047\n        ... Looked in:\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.v\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.sv\n             Codes,data/full_repos/permissive/488093047\n             Codes,data/full_repos/permissive/488093047.v\n             Codes,data/full_repos/permissive/488093047.sv\n             obj_dir/Codes,data/full_repos/permissive/488093047\n             obj_dir/Codes,data/full_repos/permissive/488093047.v\n             obj_dir/Codes,data/full_repos/permissive/488093047.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/488093047/Verilog\n%Error: Cannot find file containing module: Codes/D_Flipflop.v\n%Error: Exiting due to 3 error(s)\n'
module D_Flipflop (D,clk,reset,Q);
input D,clk,reset;
output reg Q;

always@(posedge clk)
begin
	if(reset==1'b1)
	begin
		Q<=1'b0;
	end
	else
	begin
		Q<=D;
	end
end

endmodule
module D_Flipflop (D,clk,reset,Q);

input D,clk,reset;
output reg Q;

always@(posedge clk)
begin
	if(reset==1'b1)
	begin
		Q<=1'b0;
	end
	else
	begin
		Q<=D;
	end
end

endmodule