data/full_repos/permissive/418819021/lab-02/decode_unit.v
1: b'%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:5: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418819021/lab-02,data/full_repos/permissive/418819021/defines.vh\n             data/full_repos/permissive/418819021/lab-02,data/full_repos/permissive/418819021/defines.vh.v\n             data/full_repos/permissive/418819021/lab-02,data/full_repos/permissive/418819021/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:13: Define or directive not defined: \'`OPCODE_COUNT\'\n        output reg  [`OPCODE_COUNT-1:0] opcode_type,\n                     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:16: Define or directive not defined: \'`GROUP_COUNT\'\n        output wire [`GROUP_COUNT-1:0]  opcode_group,\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:28: Define or directive not defined: \'`TYPE_ADC\'\n                opcode_type = `TYPE_ADC;\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:28: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                opcode_type = `TYPE_ADC;\n                                       ^\n%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:35: Define or directive not defined: \'`TYPE_NOP\'\n                opcode_type = `TYPE_NOP;\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:35: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                opcode_type = `TYPE_NOP;\n                                       ^\n%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:42: Define or directive not defined: \'`TYPE_NEG\'\n                opcode_type = `TYPE_NEG;\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:42: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                opcode_type = `TYPE_NEG;\n                                       ^\n%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:49: Define or directive not defined: \'`TYPE_ADD\'\n                opcode_type = `TYPE_ADD;\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:49: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                opcode_type = `TYPE_ADD;\n                                       ^\n%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:56: Define or directive not defined: \'`TYPE_SUB\'\n                opcode_type = `TYPE_SUB;\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:56: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                opcode_type = `TYPE_SUB;\n                                       ^\n%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:63: Define or directive not defined: \'`TYPE_AND\'\n                opcode_type = `TYPE_AND;\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:63: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                opcode_type = `TYPE_AND;\n                                       ^\n%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:70: Define or directive not defined: \'`TYPE_OR\'\n                opcode_type = `TYPE_OR;\n                              ^~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:70: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                opcode_type = `TYPE_OR;\n                                      ^\n%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:76: Define or directive not defined: \'`TYPE_UNKNOWN\'\n                opcode_type = `TYPE_UNKNOWN;\n                              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:76: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                opcode_type = `TYPE_UNKNOWN;\n                                           ^\n%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:84: Define or directive not defined: \'`GROUP_ALU_ONE_OP\'\n   assign opcode_group[`GROUP_ALU_ONE_OP] =\n                       ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:84: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   assign opcode_group[`GROUP_ALU_ONE_OP] =\n                                        ^\n%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:85: Define or directive not defined: \'`TYPE_NEG\'\n       (opcode_type == `TYPE_NEG);\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:88: Define or directive not defined: \'`GROUP_ALU_TWO_OP\'\n   assign opcode_group[`GROUP_ALU_TWO_OP] =\n                       ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:88: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   assign opcode_group[`GROUP_ALU_TWO_OP] =\n                                        ^\n%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:89: Define or directive not defined: \'`TYPE_ADC\'\n       (opcode_type == `TYPE_ADC) ||\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:90: Define or directive not defined: \'`TYPE_ADD\'\n       (opcode_type == `TYPE_ADD) ||\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:91: Define or directive not defined: \'`TYPE_SUB\'\n       (opcode_type == `TYPE_SUB) ||\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:92: Define or directive not defined: \'`TYPE_AND\'\n       (opcode_type == `TYPE_AND) ||\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:93: Define or directive not defined: \'`TYPE_OR\'\n       (opcode_type == `TYPE_OR);\n                       ^~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:95: Define or directive not defined: \'`GROUP_ALU\'\n   assign opcode_group[`GROUP_ALU] =\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:95: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   assign opcode_group[`GROUP_ALU] =\n                                 ^\n%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:96: Define or directive not defined: \'`GROUP_ALU_ONE_OP\'\n       opcode_group[`GROUP_ALU_ONE_OP] ||\n                    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-02/decode_unit.v:97: Define or directive not defined: \'`GROUP_ALU_TWO_OP\'\n       opcode_group[`GROUP_ALU_TWO_OP];\n                    ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 33 error(s)\n'
module decode_unit #(
        parameter  INSTR_WIDTH  = 16,
        parameter  R_ADDR_WIDTH = 5

    )(
        input  wire [INSTR_WIDTH-1:0]   instruction,
        output reg  [`OPCODE_COUNT-1:0] opcode_type,


        output wire [`GROUP_COUNT-1:0]  opcode_group,


        output reg  [R_ADDR_WIDTH-1:0]  opcode_rd,
        output reg  [R_ADDR_WIDTH-1:0]  opcode_rr
    );


    always @* begin
        casez (instruction)

	    16'b0001_11??_????_????: begin
                opcode_type = `TYPE_ADC;
                opcode_rd   = instruction[8:4];
                opcode_rr   = {instruction[9], instruction[3:0]};
            end


            16'b0000_0000_0000_0000: begin
                opcode_type = `TYPE_NOP;
                opcode_rd   = {R_ADDR_WIDTH{1'bx}};
                opcode_rr   = {R_ADDR_WIDTH{1'bx}};
            end


            16'b1001_010?_????_0001: begin
                opcode_type = `TYPE_NEG;
                opcode_rd   = instruction[8:4];
                opcode_rr   = {R_ADDR_WIDTH{1'bx}};
            end


            16'b0000_11??_????_????: begin
                opcode_type = `TYPE_ADD;
                opcode_rd   = instruction[8:4];
                opcode_rr   = {instruction[9], instruction[3:0]};
            end
            

            16'b0001_10??_????_????: begin
                opcode_type = `TYPE_SUB;
                opcode_rd   = instruction[8:4];
                opcode_rr   = {instruction[9], instruction[3:0]};
            end


            16'b0010_00??_????_????: begin
                opcode_type = `TYPE_AND;
                opcode_rd   = instruction[8:4];
                opcode_rr   = {instruction[9], instruction[3:0]};
            end
        

            16'b0010_10??_????_????: begin
                opcode_type = `TYPE_OR;
                opcode_rd   = instruction[8:4];
                opcode_rr   = {instruction[9], instruction[3:0]};
            end

            default: begin
                opcode_type = `TYPE_UNKNOWN;
                opcode_rd   = {R_ADDR_WIDTH{1'bx}};
                opcode_rr   = {R_ADDR_WIDTH{1'bx}};
            end
       endcase
   end


   assign opcode_group[`GROUP_ALU_ONE_OP] =
       (opcode_type == `TYPE_NEG);


   assign opcode_group[`GROUP_ALU_TWO_OP] =
       (opcode_type == `TYPE_ADC) ||
       (opcode_type == `TYPE_ADD) ||
       (opcode_type == `TYPE_SUB) ||
       (opcode_type == `TYPE_AND) ||
       (opcode_type == `TYPE_OR);

   assign opcode_group[`GROUP_ALU] =
       opcode_group[`GROUP_ALU_ONE_OP] ||
       opcode_group[`GROUP_ALU_TWO_OP];
endmodule
module decode_unit #(
        parameter  INSTR_WIDTH  = 16,
        parameter  R_ADDR_WIDTH = 5

    )(
        input  wire [INSTR_WIDTH-1:0]   instruction,
        output reg  [`OPCODE_COUNT-1:0] opcode_type,


        output wire [`GROUP_COUNT-1:0]  opcode_group,


        output reg  [R_ADDR_WIDTH-1:0]  opcode_rd,
        output reg  [R_ADDR_WIDTH-1:0]  opcode_rr
    );



    always @* begin
        casez (instruction)

	    16'b0001_11??_????_????: begin
                opcode_type = `TYPE_ADC;
                opcode_rd   = instruction[8:4];
                opcode_rr   = {instruction[9], instruction[3:0]};
            end


            16'b0000_0000_0000_0000: begin
                opcode_type = `TYPE_NOP;
                opcode_rd   = {R_ADDR_WIDTH{1'bx}};
                opcode_rr   = {R_ADDR_WIDTH{1'bx}};
            end


            16'b1001_010?_????_0001: begin
                opcode_type = `TYPE_NEG;
                opcode_rd   = instruction[8:4];
                opcode_rr   = {R_ADDR_WIDTH{1'bx}};
            end


            16'b0000_11??_????_????: begin
                opcode_type = `TYPE_ADD;
                opcode_rd   = instruction[8:4];
                opcode_rr   = {instruction[9], instruction[3:0]};
            end
            

            16'b0001_10??_????_????: begin
                opcode_type = `TYPE_SUB;
                opcode_rd   = instruction[8:4];
                opcode_rr   = {instruction[9], instruction[3:0]};
            end


            16'b0010_00??_????_????: begin
                opcode_type = `TYPE_AND;
                opcode_rd   = instruction[8:4];
                opcode_rr   = {instruction[9], instruction[3:0]};
            end
        

            16'b0010_10??_????_????: begin
                opcode_type = `TYPE_OR;
                opcode_rd   = instruction[8:4];
                opcode_rr   = {instruction[9], instruction[3:0]};
            end

            default: begin
                opcode_type = `TYPE_UNKNOWN;
                opcode_rd   = {R_ADDR_WIDTH{1'bx}};
                opcode_rr   = {R_ADDR_WIDTH{1'bx}};
            end
       endcase
   end


   assign opcode_group[`GROUP_ALU_ONE_OP] =
       (opcode_type == `TYPE_NEG);


   assign opcode_group[`GROUP_ALU_TWO_OP] =
       (opcode_type == `TYPE_ADC) ||
       (opcode_type == `TYPE_ADD) ||
       (opcode_type == `TYPE_SUB) ||
       (opcode_type == `TYPE_AND) ||
       (opcode_type == `TYPE_OR);

   assign opcode_group[`GROUP_ALU] =
       opcode_group[`GROUP_ALU_ONE_OP] ||
       opcode_group[`GROUP_ALU_TWO_OP];
endmodule