data/full_repos/permissive/505451992/Pendulum_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/505451992/Pendulum_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n            reset = 1;#125 \n                      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/505451992/Pendulum_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n            reset = 0;#125;\n                      ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/Pendulum_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n            reset = 0;#125;\n                      ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/Pendulum_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n           forever #125 clk=~clk;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/Pendulum_tb.v:197: Unsupported: Ignoring delay on this delayed statement.\n        forever #125000 B=~B;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/Pendulum_tb.v:196: Unsupported: Ignoring delay on this delayed statement.\n        #125000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/Pendulum_tb.v:203: Unsupported: Ignoring delay on this delayed statement.\n        forever #125000 A=~A;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/Pendulum_tb.v:202: Unsupported: Ignoring delay on this delayed statement.\n        #185000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/Pendulum_tb.v:207: Unsupported: Ignoring delay on this delayed statement.\n             #250000000\n             ^\n%Error: data/full_repos/permissive/505451992/Pendulum_tb.v:44: Cannot find file containing module: \'EE_TOP\'\n     EE_TOP  uat(\n     ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/505451992,data/full_repos/permissive/505451992/EE_TOP\n             data/full_repos/permissive/505451992,data/full_repos/permissive/505451992/EE_TOP.v\n             data/full_repos/permissive/505451992,data/full_repos/permissive/505451992/EE_TOP.sv\n             EE_TOP\n             EE_TOP.v\n             EE_TOP.sv\n             obj_dir/EE_TOP\n             obj_dir/EE_TOP.v\n             obj_dir/EE_TOP.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Pendulum_tb(

    );
    reg reset;
    reg clk;
    reg [3:0]PR;
    reg [2:0] R;
    reg A;
    reg B;


    reg PWM_Input;
    
    wire PWM_AB;
    wire Drive;
    wire Load;
    wire Drive_Led;
    wire Load_Led;
    
    
    
     EE_TOP  uat(
     .reset(reset),
    .clk(clk),
    .PR(PR),
    .R(R),
    .A(A),
    .B(B),


    .PWM_Input(PWM_Input),
    
    .PWM_AB(PWM_AB),
    .Drive(Drive),
    .Load(Load),
    .Drive_Led(Drive_Led),
    .Load_Led(Load_Led)
        );
    
    
        initial begin

             PR = 4'b0000;
            R=3'b000;
            reset = 1;#125 
            reset = 0;#125;
            reset = 0;#125;
            end
            
           initial begin
           clk=0;
           forever #125 clk=~clk;
           end
        
        
        



		        initial begin
        B=0;
        #125000
        forever #125000 B=~B;
        end
        
        initial begin
        A=0;
        #185000
        forever #125000 A=~A;
        end
             initial begin
             PWM_Input = 1;
             #250000000
             PWM_Input = 0;
             end
    
    
    
    
endmodule
module Pendulum_tb(

    );

    reg reset;
    reg clk;
    reg [3:0]PR;
    reg [2:0] R;
    reg A;
    reg B;


    reg PWM_Input;
    
    wire PWM_AB;
    wire Drive;
    wire Load;
    wire Drive_Led;
    wire Load_Led;
    
    
    
     EE_TOP  uat(
     .reset(reset),
    .clk(clk),
    .PR(PR),
    .R(R),
    .A(A),
    .B(B),


    .PWM_Input(PWM_Input),
    
    .PWM_AB(PWM_AB),
    .Drive(Drive),
    .Load(Load),
    .Drive_Led(Drive_Led),
    .Load_Led(Load_Led)
        );
    
    
        initial begin

             PR = 4'b0000;
            R=3'b000;
            reset = 1;#125 
            reset = 0;#125;
            reset = 0;#125;
            end
            
           initial begin
           clk=0;
           forever #125 clk=~clk;
           end
        
        
        



		        initial begin
        B=0;
        #125000
        forever #125000 B=~B;
        end
        
        initial begin
        A=0;
        #185000
        forever #125000 A=~A;
        end
             initial begin
             PWM_Input = 1;
             #250000000
             PWM_Input = 0;
             end
    
    
    
    
endmodule