data/full_repos/permissive/52900389/Comp_16bits.v
1: b"%Error: data/full_repos/permissive/52900389/Comp_16bits.v:21: syntax error, unexpected ',', expecting '['\nmodule Comp_16bits(in,out,rst,ref,clk);\n                                 ^\n%Error: data/full_repos/permissive/52900389/Comp_16bits.v:22: syntax error, unexpected ref, expecting IDENTIFIER or do or final\ninput wire [3:0] in, ref;\n                     ^~~\n%Error: data/full_repos/permissive/52900389/Comp_16bits.v:24: syntax error, unexpected output\noutput reg out;\n^~~~~~\n%Error: data/full_repos/permissive/52900389/Comp_16bits.v:26: syntax error, unexpected always\nalways@(posedge clk,posedge rst)\n^~~~~~\n%Error: Exiting due to 4 error(s)\n"
module Comp_16bits(in,out,rst,ref,clk);
input wire [3:0] in, ref;
input wire rst,clk;
output reg out;
 
always@(posedge clk,posedge rst)
if (rst) out = 1'b0;
else if (in >= ref) out = 1'b1;
else out = 1'b0;
endmodule
module Comp_16bits(in,out,rst,ref,clk);

input wire [3:0] in, ref;
input wire rst,clk;
output reg out;
 
always@(posedge clk,posedge rst)
if (rst) out = 1'b0;
else if (in >= ref) out = 1'b1;
else out = 1'b0;
endmodule