data/full_repos/permissive/485721981/sources/synthesis/registry.v
data/verilator_xmls/bf0569fd-6db8-4a37-b4a6-d046489af343.xml
module registry # (
        parameter C_UART_DATA_WIDTH = 8,
        parameter C_REG_WIDTH = 4,
        

        localparam C_REG_COUNT_WIDTH = C_UART_DATA_WIDTH - C_REG_WIDTH, 
        localparam C_REG_COUNT = 2**C_REG_COUNT_WIDTH,
        localparam C_REG_PORT_WIDTH = C_REG_COUNT * C_REG_WIDTH
    ) (
        

        input rstb,
        input clk,
        input valid,
        input [C_UART_DATA_WIDTH - 1 : 0] data,
        output reg ack,

        output [C_REG_PORT_WIDTH - 1 : 0] register,
        output reg [C_UART_DATA_WIDTH - 1 : 0] dataRaw
    );
    
    





    localparam sIDLE = 2'b00;
	localparam sGET  = 2'b01;
    localparam sACK  = 2'b10;







    reg [1:0] rState = sIDLE;
    reg [1:0] rNext;
   

    reg [C_REG_WIDTH - 1 : 0] rRegister [C_REG_COUNT - 1 : 0];











    genvar i;
    generate
        for (i = 0; i < C_REG_COUNT; i = i + 1) begin
            assign register[(i + 1) * C_REG_WIDTH - 1: i * C_REG_WIDTH] = rRegister[i];
        end
    endgenerate
    






    always @(posedge clk) begin  
        

        if (rstb == 1'b0) begin
            rState <= sIDLE;
        

        end else begin
            rState <= rNext;
        end
    end


    always @(rState, valid) begin


        rNext <= rState;
        

        case (rState)


            sIDLE: begin
                rNext <= (valid == 1'b1) ? sGET : sIDLE; 
            end


            sGET: begin
                rNext <= sACK;
            end


            sACK: begin
                rNext <= sIDLE;
            end
        endcase    
    end







    always @(posedge clk) begin  
        if (rState == sGET) begin
            rRegister [data[C_UART_DATA_WIDTH - 1 : C_REG_WIDTH]] <= data[C_REG_WIDTH - 1 : 0];
            dataRaw <= data[C_UART_DATA_WIDTH - 1 : 0];
        end
    end







    always @(posedge clk) begin  
        ack <= (rState == sGET) ? 1'b1 : 1'b0;
    end
    
endmodule
module registry # (
        parameter C_UART_DATA_WIDTH = 8,
        parameter C_REG_WIDTH = 4,
        

        localparam C_REG_COUNT_WIDTH = C_UART_DATA_WIDTH - C_REG_WIDTH, 
        localparam C_REG_COUNT = 2**C_REG_COUNT_WIDTH,
        localparam C_REG_PORT_WIDTH = C_REG_COUNT * C_REG_WIDTH
    ) (
        

        input rstb,
        input clk,
        input valid,
        input [C_UART_DATA_WIDTH - 1 : 0] data,
        output reg ack,

        output [C_REG_PORT_WIDTH - 1 : 0] register,
        output reg [C_UART_DATA_WIDTH - 1 : 0] dataRaw
    );

    
    





    localparam sIDLE = 2'b00;
	localparam sGET  = 2'b01;
    localparam sACK  = 2'b10;







    reg [1:0] rState = sIDLE;
    reg [1:0] rNext;
   

    reg [C_REG_WIDTH - 1 : 0] rRegister [C_REG_COUNT - 1 : 0];











    genvar i;
    generate
        for (i = 0; i < C_REG_COUNT; i = i + 1) begin
            assign register[(i + 1) * C_REG_WIDTH - 1: i * C_REG_WIDTH] = rRegister[i];
        end
    endgenerate
    






    always @(posedge clk) begin  
        

        if (rstb == 1'b0) begin
            rState <= sIDLE;
        

        end else begin
            rState <= rNext;
        end
    end


    always @(rState, valid) begin


        rNext <= rState;
        

        case (rState)


            sIDLE: begin
                rNext <= (valid == 1'b1) ? sGET : sIDLE; 
            end


            sGET: begin
                rNext <= sACK;
            end


            sACK: begin
                rNext <= sIDLE;
            end
        endcase    
    end







    always @(posedge clk) begin  
        if (rState == sGET) begin
            rRegister [data[C_UART_DATA_WIDTH - 1 : C_REG_WIDTH]] <= data[C_REG_WIDTH - 1 : 0];
            dataRaw <= data[C_UART_DATA_WIDTH - 1 : 0];
        end
    end







    always @(posedge clk) begin  
        ack <= (rState == sGET) ? 1'b1 : 1'b0;
    end
    
endmodule