data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new/IR.v
data/verilator_xmls/a0f84f48-172d-4c00-968b-0ee2ddb8af28.xml
module IR(
    input clk,
    input IRWE,
    input [31:0] IRIn,
    output reg [31:0] IROut
    );
    
    always@(posedge clk) begin
        if (IRWE) begin
            IROut <= IRIn;
        end
    end
endmodule
module IR(
    input clk,
    input IRWE,
    input [31:0] IRIn,
    output reg [31:0] IROut
    );

    
    always@(posedge clk) begin
        if (IRWE) begin
            IROut <= IRIn;
        end
    end
endmodule