data/full_repos/permissive/446939020/risc-v/mux22.v
data/verilator_xmls/7469d730-4a2b-41d5-bad9-e3ce3531006b.xml
module mux22
  (input [31:0] d0, d1,d2,
   input [1:0]s,
   output reg [31:0] y);
  always@(*) begin
  	case(s)
   	 	2'b00: y=d0;
    	2'b01: y=d1;
    	2'b10: y=d2;
  	endcase
  end

endmodule
module mux22
  (input [31:0] d0, d1,d2,
   input [1:0]s,
   output reg [31:0] y);

  always@(*) begin
  	case(s)
   	 	2'b00: y=d0;
    	2'b01: y=d1;
    	2'b10: y=d2;
  	endcase
  end

endmodule