data/full_repos/permissive/503053625/resources/verilog_source/top_level_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/top_level_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #ADC_CLK_HPERIOD;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/top_level_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #ADC_CLK_HPERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/top_level_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #TRIG_CLK_HPERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/top_level_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #TRIG_CLK_HPERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/top_level_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #ADC_CLK_HPERIOD\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/top_level_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #ADC_CLK_HPERIOD\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/top_level_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #ADC_CLK_HPERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/top_level_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #ADC_CLK_HPERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/top_level_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #ADC_CLK_HPERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/top_level_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #TRIG_CLK_HPERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/top_level_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #ADC_CLK_HPERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/top_level_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #ADC_CLK_HPERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/top_level_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #ADC_CLK_HPERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/top_level_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #ADC_CLK_HPERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/top_level_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #ADC_CLK_HPERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/top_level_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #ADC_CLK_HPERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/top_level_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #ADC_CLK_HPERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/top_level_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #TRIG_CLK_HPERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/top_level_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #T_OFFSET;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/top_level_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #TRIG_CLK_HPERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/top_level_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #TRIG_CLK_HPERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/top_level_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n  #TRIG_CLK_HPERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/top_level_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #TRIG_CLK_HPERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/top_level_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #TRIG_CLK_HPERIOD;\n  ^\n%Error: data/full_repos/permissive/503053625/resources/verilog_source/top_level_tb.v:23: Cannot find file containing module: \'newer_top\'\n newer_top TL(.TRIG_IN(trig_clk), .ADC_CLK(adc_clk), .ADC_IN(ADC_data),  .GPIO_IN(GPIO_IN), .DAC_SPI_SDIO(), .DAC_SPI_CLK(), .DAC_SPI_CSB(), .DAC_SPI_RST(),\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/503053625/resources/verilog_source,data/full_repos/permissive/503053625/newer_top\n             data/full_repos/permissive/503053625/resources/verilog_source,data/full_repos/permissive/503053625/newer_top.v\n             data/full_repos/permissive/503053625/resources/verilog_source,data/full_repos/permissive/503053625/newer_top.sv\n             newer_top\n             newer_top.v\n             newer_top.sv\n             obj_dir/newer_top\n             obj_dir/newer_top.v\n             obj_dir/newer_top.sv\n%Error: Exiting due to 1 error(s), 24 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_level_tb;

	reg trig_clk;
	reg adc_clk;

	reg [11:0] ADC_data = 12'h7FF;
	reg [31:0] GPIO_IN = 32'h00000002;
	wire [31:0] GPIO_OUT;

	wire [7:0] leds;

	wire [13:0] DAC_A;
	wire [13:0] DAC_B;

	localparam ADC_CLK_HPERIOD = 2;
	localparam T_OFFSET = 150;
	localparam TRIG_CLK_HPERIOD = 250;

	newer_top TL(.TRIG_IN(trig_clk), .ADC_CLK(adc_clk), .ADC_IN(ADC_data),  .GPIO_IN(GPIO_IN), .DAC_SPI_SDIO(), .DAC_SPI_CLK(), .DAC_SPI_CSB(), .DAC_SPI_RST(),
	.DAC_A_OUT(DAC_A), .DAC_B_OUT(DAC_B), .GPIO_OUT(GPIO_OUT), .LED_OUT(leds));

	always 
	begin
		adc_clk = 1'b0; 
		#ADC_CLK_HPERIOD;
		adc_clk = 1'b1;
		#ADC_CLK_HPERIOD;
	end

	always 
	begin
		trig_clk = 1'b0; 
		#TRIG_CLK_HPERIOD;
		trig_clk = 1'b1;
		#TRIG_CLK_HPERIOD;
	end

	initial
	begin
		#ADC_CLK_HPERIOD
		#ADC_CLK_HPERIOD
		GPIO_IN = 32'h00000002;
		#ADC_CLK_HPERIOD;
		#ADC_CLK_HPERIOD;
		GPIO_IN = 32'h00000000;
		#ADC_CLK_HPERIOD;

		#TRIG_CLK_HPERIOD;
		#ADC_CLK_HPERIOD;
		#ADC_CLK_HPERIOD;
		#ADC_CLK_HPERIOD;
		#ADC_CLK_HPERIOD;
		#ADC_CLK_HPERIOD;
		#ADC_CLK_HPERIOD;
		#ADC_CLK_HPERIOD;
		GPIO_IN = 32'h00000001;
		ADC_data = 12'h523;
		#TRIG_CLK_HPERIOD;
		#T_OFFSET;
		ADC_data = 12'h520;
		#TRIG_CLK_HPERIOD;
		ADC_data = 12'h4FA;
		#TRIG_CLK_HPERIOD;
		ADC_data = 12'h4EA;
		#TRIG_CLK_HPERIOD;
		ADC_data = 12'h4FC;
		#TRIG_CLK_HPERIOD;
		ADC_data = 12'h4DA;
		#TRIG_CLK_HPERIOD;
		ADC_data = 12'h50A;
	end

endmodule
module top_level_tb;


	reg trig_clk;
	reg adc_clk;

	reg [11:0] ADC_data = 12'h7FF;
	reg [31:0] GPIO_IN = 32'h00000002;
	wire [31:0] GPIO_OUT;

	wire [7:0] leds;

	wire [13:0] DAC_A;
	wire [13:0] DAC_B;

	localparam ADC_CLK_HPERIOD = 2;
	localparam T_OFFSET = 150;
	localparam TRIG_CLK_HPERIOD = 250;

	newer_top TL(.TRIG_IN(trig_clk), .ADC_CLK(adc_clk), .ADC_IN(ADC_data),  .GPIO_IN(GPIO_IN), .DAC_SPI_SDIO(), .DAC_SPI_CLK(), .DAC_SPI_CSB(), .DAC_SPI_RST(),
	.DAC_A_OUT(DAC_A), .DAC_B_OUT(DAC_B), .GPIO_OUT(GPIO_OUT), .LED_OUT(leds));

	always 
	begin
		adc_clk = 1'b0; 
		#ADC_CLK_HPERIOD;
		adc_clk = 1'b1;
		#ADC_CLK_HPERIOD;
	end

	always 
	begin
		trig_clk = 1'b0; 
		#TRIG_CLK_HPERIOD;
		trig_clk = 1'b1;
		#TRIG_CLK_HPERIOD;
	end

	initial
	begin
		#ADC_CLK_HPERIOD
		#ADC_CLK_HPERIOD
		GPIO_IN = 32'h00000002;
		#ADC_CLK_HPERIOD;
		#ADC_CLK_HPERIOD;
		GPIO_IN = 32'h00000000;
		#ADC_CLK_HPERIOD;

		#TRIG_CLK_HPERIOD;
		#ADC_CLK_HPERIOD;
		#ADC_CLK_HPERIOD;
		#ADC_CLK_HPERIOD;
		#ADC_CLK_HPERIOD;
		#ADC_CLK_HPERIOD;
		#ADC_CLK_HPERIOD;
		#ADC_CLK_HPERIOD;
		GPIO_IN = 32'h00000001;
		ADC_data = 12'h523;
		#TRIG_CLK_HPERIOD;
		#T_OFFSET;
		ADC_data = 12'h520;
		#TRIG_CLK_HPERIOD;
		ADC_data = 12'h4FA;
		#TRIG_CLK_HPERIOD;
		ADC_data = 12'h4EA;
		#TRIG_CLK_HPERIOD;
		ADC_data = 12'h4FC;
		#TRIG_CLK_HPERIOD;
		ADC_data = 12'h4DA;
		#TRIG_CLK_HPERIOD;
		ADC_data = 12'h50A;
	end

endmodule