data/full_repos/permissive/491169855/LimeSDR-Mini_lms7_trx/mico32_patform/MSBComponents/Reg_Comp/rtl/verilog/wb_reg_dev.v
data/verilator_xmls/a08eca61-ddb5-4f71-ad9b-80dad3eaacfe.xml
function integer i_clk_mhz;
      input integer clk_mhz;
      begin
         i_clk_mhz = clk_mhz;
      end
   endfunction
function integer i_clk_mhz;

      input integer clk_mhz;
      begin
         i_clk_mhz = clk_mhz;
      end
   endfunction