data/full_repos/permissive/506186384/project-files/lab5/ALUCtr.v
data/verilator_xmls/a49f8395-74c4-4b8b-9493-1df633425b3a.xml
module ALUCtr(
    input [2:0] ALUOp,
    input [5:0] Funct,
    output [3:0] ALUCtr,
    output jr,
    output shift
    );
    reg [3:0] aluCtr;
    reg JR;
    reg SHIFT;
    always @ (ALUOp or Funct)
    begin
        casex ({ALUOp, Funct})
            9'b000xxxxxx: begin
                aluCtr = 4'b0010;
                JR = 0;
                SHIFT = 0;
            end
            9'b001xxxxxx: begin
                aluCtr = 4'b0110;
                JR = 0;
                SHIFT = 0;
            end
            9'b011xxxxxx: begin
                aluCtr = 4'b0000;
                JR = 0;
                SHIFT = 0;
            end
            9'b100xxxxxx: begin
                aluCtr = 4'b0001;
                JR = 0;
                SHIFT = 0;
            end

            9'b010100000: begin
                aluCtr = 4'b0010;
                JR = 0;
                SHIFT = 0;
            end
            9'b010100010: begin
                aluCtr = 4'b0110;
                JR = 0;
                SHIFT = 0;
            end
            9'b010100100: begin
                aluCtr = 4'b0000;
                JR = 0;
                SHIFT = 0;
            end
            9'b010100101: begin
                aluCtr = 4'b0001;
                JR = 0;
                SHIFT = 0;
            end
            9'b010101010: begin
                aluCtr = 4'b0111;
                JR = 0;
                SHIFT = 0;
            end
            9'b010100111: begin
                aluCtr = 4'b1100;
                JR = 0;
                SHIFT = 0;
            end
            9'b010000000: begin
                aluCtr = 4'b0011;
                JR = 0;
                SHIFT = 1;
            end
            9'b010000010: begin
                aluCtr = 4'b0100;
                JR = 0;
                SHIFT = 1;
            end
            9'b010001000: begin 
                aluCtr = 4'b1000;
                JR = 1;
                SHIFT = 0;
            end
            default: aluCtr = 4'b0000;
        endcase
    end
    assign ALUCtr = aluCtr;
    assign jr = JR;
    assign shift = SHIFT;
endmodule
module ALUCtr(
    input [2:0] ALUOp,
    input [5:0] Funct,
    output [3:0] ALUCtr,
    output jr,
    output shift
    );

    reg [3:0] aluCtr;
    reg JR;
    reg SHIFT;
    always @ (ALUOp or Funct)
    begin
        casex ({ALUOp, Funct})
            9'b000xxxxxx: begin
                aluCtr = 4'b0010;
                JR = 0;
                SHIFT = 0;
            end
            9'b001xxxxxx: begin
                aluCtr = 4'b0110;
                JR = 0;
                SHIFT = 0;
            end
            9'b011xxxxxx: begin
                aluCtr = 4'b0000;
                JR = 0;
                SHIFT = 0;
            end
            9'b100xxxxxx: begin
                aluCtr = 4'b0001;
                JR = 0;
                SHIFT = 0;
            end

            9'b010100000: begin
                aluCtr = 4'b0010;
                JR = 0;
                SHIFT = 0;
            end
            9'b010100010: begin
                aluCtr = 4'b0110;
                JR = 0;
                SHIFT = 0;
            end
            9'b010100100: begin
                aluCtr = 4'b0000;
                JR = 0;
                SHIFT = 0;
            end
            9'b010100101: begin
                aluCtr = 4'b0001;
                JR = 0;
                SHIFT = 0;
            end
            9'b010101010: begin
                aluCtr = 4'b0111;
                JR = 0;
                SHIFT = 0;
            end
            9'b010100111: begin
                aluCtr = 4'b1100;
                JR = 0;
                SHIFT = 0;
            end
            9'b010000000: begin
                aluCtr = 4'b0011;
                JR = 0;
                SHIFT = 1;
            end
            9'b010000010: begin
                aluCtr = 4'b0100;
                JR = 0;
                SHIFT = 1;
            end
            9'b010001000: begin 
                aluCtr = 4'b1000;
                JR = 1;
                SHIFT = 0;
            end
            default: aluCtr = 4'b0000;
        endcase
    end
    assign ALUCtr = aluCtr;
    assign jr = JR;
    assign shift = SHIFT;
endmodule