data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Keccak_Core/tb_SHA_SHAKE_wrapper.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Keccak_Core/tb_SHA_SHAKE_wrapper.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Keccak_Core/tb_SHA_SHAKE_wrapper.v:66: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Keccak_Core/tb_SHA_SHAKE_wrapper.v:71: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Keccak_Core/tb_SHA_SHAKE_wrapper.v:73: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Keccak_Core/tb_SHA_SHAKE_wrapper.v:75: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Keccak_Core/tb_SHA_SHAKE_wrapper.v:77: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Keccak_Core/tb_SHA_SHAKE_wrapper.v:79: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Keccak_Core/tb_SHA_SHAKE_wrapper.v:83: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Keccak_Core/tb_SHA_SHAKE_wrapper.v:88: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Keccak_Core/tb_SHA_SHAKE_wrapper.v:92: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Keccak_Core/tb_SHA_SHAKE_wrapper.v:97: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Keccak_Core/tb_SHA_SHAKE_wrapper.v:101: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Keccak_Core/tb_SHA_SHAKE_wrapper.v:106: Unsupported: wait statements\n  wait(done_shake);\n  ^~~~\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Keccak_Core/tb_SHA_SHAKE_wrapper.v:107: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Keccak_Core/tb_SHA_SHAKE_wrapper.v:113: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Keccak_Core/tb_SHA_SHAKE_wrapper.v:118: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Keccak_Core/tb_SHA_SHAKE_wrapper.v:122: syntax error, unexpected \'@\'\n  @(posedge clk)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Keccak_Core/tb_SHA_SHAKE_wrapper.v:127: Unsupported: Ignoring delay on this delayed statement.\n   always #5 clk = ~clk;\n          ^\n%Error: Exiting due to 16 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_sha_shake_wrapper;


	reg clk;
	reg [8:0] address_ext;
	reg [63:0] dina_ext;
	reg wea_ext;
	reg [31:0] command_in;
	reg command_we0, command_we1, command_enable;


	wire done_shake;


	SHA_SHAKE_wrapper_test uut (
		.clk(clk), 
		.address_ext(address_ext), 
		.dina_ext(dina_ext), 
		.wea_ext(wea_ext), 
		.command_in(command_in), 
		.command_we0(command_we0),
		.command_we1(command_we1),	
		.command_enable(command_enable),
		.done_shake(done_shake)
	);

	initial begin

		clk = 0;
		address_ext = 0;
		dina_ext = 0;
		wea_ext = 0;
		command_in = 0;
		command_we0 = 0;
		command_we1 = 0;		
		command_enable = 0;
		

		#100;
        

		@(posedge clk)
		command_in = 32'd0;
		command_we0 = 1; command_we1 = 0;
		command_enable = 0;

		@(posedge clk);
		address_ext = 9'd0; dina_ext = 64'h38520EBAD808EE98; wea_ext = 1;
		@(posedge clk);
		address_ext = 9'd1; dina_ext = 64'h15A05FE0A84F7D23; wea_ext = 1;
		@(posedge clk);
		address_ext = 9'd2; dina_ext = 64'hE8528969C871AABA; wea_ext = 1;
		@(posedge clk);
		address_ext = 9'd3; dina_ext = 64'h430DD8BC41420304; wea_ext = 1;
		@(posedge clk);
		wea_ext = 0;
		

		@(posedge clk)

		command_in = {16'd336,16'd32};
		command_we0 = 0; command_we1 = 1;
		command_enable = 0;
		@(posedge clk)
		command_in = {9'd16,9'd0,9'd0,5'd0};
		command_we0 = 1; command_we1 = 0;
		command_enable = 0;
		@(posedge clk)
		command_in = {9'd16,9'd0,9'd0,5'd0};
		command_we0 = 0; command_we1 = 0;
		command_enable = 1;

		@(posedge clk)
		command_in = {9'd16,9'd0,9'd0,5'd3};
		command_we0 = 1; command_we1 = 0;
		command_enable = 0;
		@(posedge clk)
		command_in = 32'd0;
		command_we0 = 0; command_we1 = 0;
		command_enable = 1;

		wait(done_shake);
			@(posedge clk);
			
		@(posedge clk)
		command_in = {9'd16,9'd0,9'd0,5'd4};
		command_we0 = 1; command_we1 = 0;
		command_enable = 0;
		@(posedge clk)
		command_in = 32'd0;
		command_we0 = 0; command_we1 = 0;
		command_enable = 1;

		@(posedge clk)
		command_in = {9'd16,9'd0,9'd0,5'd5};
		command_we0 = 1; command_we1 = 0;
		command_enable = 0;
		@(posedge clk)
		command_in = 32'd0;
		command_we0 = 0; command_we1 = 0;
		command_enable = 1;		
	end
   always #5 clk = ~clk;
   
endmodule
module tb_sha_shake_wrapper;



	reg clk;
	reg [8:0] address_ext;
	reg [63:0] dina_ext;
	reg wea_ext;
	reg [31:0] command_in;
	reg command_we0, command_we1, command_enable;


	wire done_shake;


	SHA_SHAKE_wrapper_test uut (
		.clk(clk), 
		.address_ext(address_ext), 
		.dina_ext(dina_ext), 
		.wea_ext(wea_ext), 
		.command_in(command_in), 
		.command_we0(command_we0),
		.command_we1(command_we1),	
		.command_enable(command_enable),
		.done_shake(done_shake)
	);

	initial begin

		clk = 0;
		address_ext = 0;
		dina_ext = 0;
		wea_ext = 0;
		command_in = 0;
		command_we0 = 0;
		command_we1 = 0;		
		command_enable = 0;
		

		#100;
        

		@(posedge clk)
		command_in = 32'd0;
		command_we0 = 1; command_we1 = 0;
		command_enable = 0;

		@(posedge clk);
		address_ext = 9'd0; dina_ext = 64'h38520EBAD808EE98; wea_ext = 1;
		@(posedge clk);
		address_ext = 9'd1; dina_ext = 64'h15A05FE0A84F7D23; wea_ext = 1;
		@(posedge clk);
		address_ext = 9'd2; dina_ext = 64'hE8528969C871AABA; wea_ext = 1;
		@(posedge clk);
		address_ext = 9'd3; dina_ext = 64'h430DD8BC41420304; wea_ext = 1;
		@(posedge clk);
		wea_ext = 0;
		

		@(posedge clk)

		command_in = {16'd336,16'd32};
		command_we0 = 0; command_we1 = 1;
		command_enable = 0;
		@(posedge clk)
		command_in = {9'd16,9'd0,9'd0,5'd0};
		command_we0 = 1; command_we1 = 0;
		command_enable = 0;
		@(posedge clk)
		command_in = {9'd16,9'd0,9'd0,5'd0};
		command_we0 = 0; command_we1 = 0;
		command_enable = 1;

		@(posedge clk)
		command_in = {9'd16,9'd0,9'd0,5'd3};
		command_we0 = 1; command_we1 = 0;
		command_enable = 0;
		@(posedge clk)
		command_in = 32'd0;
		command_we0 = 0; command_we1 = 0;
		command_enable = 1;

		wait(done_shake);
			@(posedge clk);
			
		@(posedge clk)
		command_in = {9'd16,9'd0,9'd0,5'd4};
		command_we0 = 1; command_we1 = 0;
		command_enable = 0;
		@(posedge clk)
		command_in = 32'd0;
		command_we0 = 0; command_we1 = 0;
		command_enable = 1;

		@(posedge clk)
		command_in = {9'd16,9'd0,9'd0,5'd5};
		command_we0 = 1; command_we1 = 0;
		command_enable = 0;
		@(posedge clk)
		command_in = 32'd0;
		command_we0 = 0; command_we1 = 0;
		command_enable = 1;		
	end
   always #5 clk = ~clk;
   
endmodule