data/full_repos/permissive/497044171/verilog/rtl/prog_uart_top.v
1: b"%Error: data/full_repos/permissive/497044171/verilog/rtl/prog_uart_top.v:20: Cannot find file containing module: 'Top'\nTop u_top(\n^~~\n        ... Looked in:\n             data/full_repos/permissive/497044171/verilog/rtl,data/full_repos/permissive/497044171/Top\n             data/full_repos/permissive/497044171/verilog/rtl,data/full_repos/permissive/497044171/Top.v\n             data/full_repos/permissive/497044171/verilog/rtl,data/full_repos/permissive/497044171/Top.sv\n             Top\n             Top.v\n             Top.sv\n             obj_dir/Top\n             obj_dir/Top.v\n             obj_dir/Top.sv\n%Error: data/full_repos/permissive/497044171/verilog/rtl/prog_uart_top.v:32: Cannot find file containing module: 'programmer'\nprogrammer u_programmer(\n^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module prog_uart_top(  
  input           clock,
  input           reset,
  output [31:0]   io_gpio_o,
  output [31:0]   io_gpio_en_o,
  input  [31:0]   io_gpio_i,
  input           io_rx_i,
  input  [15:0]   io_CLK_PER_BIT,
  output          boot,
  input           prog_i);

wire        io_rx_we;
wire [31:0] io_rx_wdata;
wire        rst;
wire [31:0] io_rx_addr;
wire        a_clk;

assign boot = rst;

Top u_top(
  .clock(clock),
  .reset(reset | ~rst),
  .io_gpio_o(io_gpio_o),
  .io_gpio_en_o(io_gpio_en_o),
  .io_gpio_i(io_gpio_i),
  .io_rx_we_i(~io_rx_we),
  .io_rx_addr_i(io_rx_addr),
  .io_rx_wdata_i(io_rx_wdata),
  .io_rx_reset_i(rst)
);

programmer u_programmer(
  .clk_i(clock),
  .rst_ni(~reset),
  .prog_i(prog_i),
  .rx_i(io_rx_i),
  .clks_per_bit(io_CLK_PER_BIT),
  .we_o(io_rx_we),
  .addr_o(io_rx_addr),
  .wdata_o(io_rx_wdata),
  .reset_o(rst));




endmodule
module prog_uart_top(  
  input           clock,
  input           reset,
  output [31:0]   io_gpio_o,
  output [31:0]   io_gpio_en_o,
  input  [31:0]   io_gpio_i,
  input           io_rx_i,
  input  [15:0]   io_CLK_PER_BIT,
  output          boot,
  input           prog_i);


wire        io_rx_we;
wire [31:0] io_rx_wdata;
wire        rst;
wire [31:0] io_rx_addr;
wire        a_clk;

assign boot = rst;

Top u_top(
  .clock(clock),
  .reset(reset | ~rst),
  .io_gpio_o(io_gpio_o),
  .io_gpio_en_o(io_gpio_en_o),
  .io_gpio_i(io_gpio_i),
  .io_rx_we_i(~io_rx_we),
  .io_rx_addr_i(io_rx_addr),
  .io_rx_wdata_i(io_rx_wdata),
  .io_rx_reset_i(rst)
);

programmer u_programmer(
  .clk_i(clock),
  .rst_ni(~reset),
  .prog_i(prog_i),
  .rx_i(io_rx_i),
  .clks_per_bit(io_CLK_PER_BIT),
  .we_o(io_rx_we),
  .addr_o(io_rx_addr),
  .wdata_o(io_rx_wdata),
  .reset_o(rst));




endmodule