data/full_repos/permissive/417033152/fft_main.v
1: b'%Warning-WIDTH: data/full_repos/permissive/417033152/fft_main.v:79: Operator ASSIGNW expects 9 bits on the Assign RHS, but Assign RHS\'s SUB generates 10 bits.\n                                                                  : ... In instance dit_fft_8.s34\nassign in0r=inr+p1[17:8]-p2[17:8];\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/417033152/fft_main.v:80: Operator ASSIGNW expects 9 bits on the Assign RHS, but Assign RHS\'s ADD generates 10 bits.\n                                                                  : ... In instance dit_fft_8.s34\nassign in0i=ini+p3[17:8]+p4[17:8];\n           ^\n%Warning-WIDTH: data/full_repos/permissive/417033152/fft_main.v:81: Operator ASSIGNW expects 9 bits on the Assign RHS, but Assign RHS\'s ADD generates 10 bits.\n                                                                  : ... In instance dit_fft_8.s34\nassign in1r=inr-p1[17:8]+p2[17:8];\n           ^\n%Warning-WIDTH: data/full_repos/permissive/417033152/fft_main.v:82: Operator ASSIGNW expects 9 bits on the Assign RHS, but Assign RHS\'s SUB generates 10 bits.\n                                                                  : ... In instance dit_fft_8.s34\nassign in1i=ini-p3[17:8]-p4[17:8];\n           ^\n%Error: Exiting due to 4 warning(s)\n'
module bfly4_4(inr,ini,yr,yi,wr,wi,in0r,in0i,in1r,in1i);
input signed [8:0]inr,ini,yr,yi;
input signed [8:0]wr,wi;
output [8:0]in0r,in0i,in1r,in1i;
wire [17:0]p1,p2,p3,p4;
assign p1=wr*yr;
assign p2=wi*yi;
assign p3=wr*yi;
assign p4=wi*yr;
assign in0r=inr+p1[17:8]-p2[17:8];
assign in0i=ini+p3[17:8]+p4[17:8];
assign in1r=inr-p1[17:8]+p2[17:8];
assign in1i=ini-p3[17:8]-p4[17:8];
endmodule
module bfly4_4(inr,ini,yr,yi,wr,wi,in0r,in0i,in1r,in1i);

input signed [8:0]inr,ini,yr,yi;
input signed [8:0]wr,wi;
output [8:0]in0r,in0i,in1r,in1i;
wire [17:0]p1,p2,p3,p4;
assign p1=wr*yr;
assign p2=wi*yi;
assign p3=wr*yi;
assign p4=wi*yr;
assign in0r=inr+p1[17:8]-p2[17:8];
assign in0i=ini+p3[17:8]+p4[17:8];
assign in1r=inr-p1[17:8]+p2[17:8];
assign in1i=ini-p3[17:8]-p4[17:8];
endmodule