data/full_repos/permissive/423547971/College Coursework/Digital Design II Final Project/counter2_TB.v
1: b'%Error: Cannot find file containing module: Coursework/Digital\n        ... Looked in:\n             data/full_repos/permissive/423547971/College/Coursework/Digital\n             data/full_repos/permissive/423547971/College/Coursework/Digital.v\n             data/full_repos/permissive/423547971/College/Coursework/Digital.sv\n             Coursework/Digital\n             Coursework/Digital.v\n             Coursework/Digital.sv\n             obj_dir/Coursework/Digital\n             obj_dir/Coursework/Digital.v\n             obj_dir/Coursework/Digital.sv\n%Error: Cannot find file containing module: Design\n%Error: Cannot find file containing module: II\n%Error: Cannot find file containing module: Final\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/College\n%Error: Cannot find file containing module: Project/counter2_TB.v\n%Error: Exiting due to 7 error(s)\n'
module counter2_TB;

reg CLOCK;
reg RESET;
reg ENABLE;

wire counter3_RST;
wire control_signal;
wire W;
wire X;
wire Y;
wire Z;


counter2 CTR(
	.CLOCK(CLOCK),
	.RESET(RESET),
	.ENABLE(ENABLE),
	.counter3_RST(counter3_RST),
	.control_signal(control_signal),
	.W(W),
	.X(X),
	.Y(Y),
	.Z(Z)
);


always
  #20 CLOCK = ~CLOCK ;
  

initial
begin
  $dumpfile("counter2_TB.vcd") ;
  $dumpvars(0, counter2_TB) ;
end


initial
begin
		CLOCK  = 0 ;
		RESET  = 0 ;
		ENABLE = 0 ;
  #10	RESET  = 1 ;
  #31 	RESET  = 0 ;
  #200	ENABLE = 1 ;
  #250	RESET  = 1 ;
  #50	RESET  = 0 ;
  #950	ENABLE = 0 ;
  
  #2000 $finish ;  
end
 
endmodule
module counter2_TB;


reg CLOCK;
reg RESET;
reg ENABLE;

wire counter3_RST;
wire control_signal;
wire W;
wire X;
wire Y;
wire Z;


counter2 CTR(
	.CLOCK(CLOCK),
	.RESET(RESET),
	.ENABLE(ENABLE),
	.counter3_RST(counter3_RST),
	.control_signal(control_signal),
	.W(W),
	.X(X),
	.Y(Y),
	.Z(Z)
);


always
  #20 CLOCK = ~CLOCK ;
  

initial
begin
  $dumpfile("counter2_TB.vcd") ;
  $dumpvars(0, counter2_TB) ;
end


initial
begin
		CLOCK  = 0 ;
		RESET  = 0 ;
		ENABLE = 0 ;
  #10	RESET  = 1 ;
  #31 	RESET  = 0 ;
  #200	ENABLE = 1 ;
  #250	RESET  = 1 ;
  #50	RESET  = 0 ;
  #950	ENABLE = 0 ;
  
  #2000 $finish ;  
end
 
endmodule