data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/top_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/top_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n            #100\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/top_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n            #100    \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/top_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n            #100    \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/top_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n            #1000\n            ^\n%Error: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/top_tb.v:14: Cannot find file containing module: \'top\'\n    top top_t(\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/502135797/Lab7_April_6_2022/Code,data/full_repos/permissive/502135797/top\n             data/full_repos/permissive/502135797/Lab7_April_6_2022/Code,data/full_repos/permissive/502135797/top.v\n             data/full_repos/permissive/502135797/Lab7_April_6_2022/Code,data/full_repos/permissive/502135797/top.sv\n             top\n             top.v\n             top.sv\n             obj_dir/top\n             obj_dir/top.v\n             obj_dir/top.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_tb();
    reg [3:0] opatb;
    reg [3:0] opbtb;
    reg signatb;
    reg signbtb;
    reg [1:0] asmtb;
    
    wire [6:0] Cnode_tb;
    wire dp_tb;
    wire [7:0] AN_tb;

    
    top top_t(
        .opa(opatb),
        .opb(opbtb),
        .signa(signatb),
        .signb(signbtb),
        .asm(asmtb),

         .Cnode1(Cnode_tb),
         .seg(dp_tb),
         .AN1(AN_tb)

    );
    initial
        begin: TEST
            asmtb = 3;      
            opatb = 4;
            opbtb = 2;
            signatb = 0;
            signbtb = 0; 
            
            #100

            asmtb = 2;      
            opatb = 4;
            opbtb = 4;
            signatb = 0;
            signbtb = 1; 

            #100    
            
            asmtb = 1;      
            opatb = 9;
            opbtb = 1;
            signatb = 0;
            signbtb = 0; 
            
            #100    
            asmtb = 3;      
            opatb = 1;
            opbtb = 9;
            signatb = 1;
            signbtb = 0; 
            #1000
            $finish;
        end
endmodule
module top_tb();

    reg [3:0] opatb;
    reg [3:0] opbtb;
    reg signatb;
    reg signbtb;
    reg [1:0] asmtb;
    
    wire [6:0] Cnode_tb;
    wire dp_tb;
    wire [7:0] AN_tb;

    
    top top_t(
        .opa(opatb),
        .opb(opbtb),
        .signa(signatb),
        .signb(signbtb),
        .asm(asmtb),

         .Cnode1(Cnode_tb),
         .seg(dp_tb),
         .AN1(AN_tb)

    );
    initial
        begin: TEST
            asmtb = 3;      
            opatb = 4;
            opbtb = 2;
            signatb = 0;
            signbtb = 0; 
            
            #100

            asmtb = 2;      
            opatb = 4;
            opbtb = 4;
            signatb = 0;
            signbtb = 1; 

            #100    
            
            asmtb = 1;      
            opatb = 9;
            opbtb = 1;
            signatb = 0;
            signbtb = 0; 
            
            #100    
            asmtb = 3;      
            opatb = 1;
            opbtb = 9;
            signatb = 1;
            signbtb = 0; 
            #1000
            $finish;
        end
endmodule