data/full_repos/permissive/497530416/sequential/decode.v
data/verilator_xmls/654e1eb6-40db-4421-8f93-fc61348e96c9.xml
module decode_seq(clk, icode, rA, rB, valA, valB, reg_file0, reg_file1, reg_file2, reg_file3, reg_file4, reg_file5, reg_file6, reg_file7, reg_file8, reg_file9, reg_file10, reg_file11, reg_file12, reg_file13, reg_file14);

input clk;
input [3:0] icode;
input [3:0] rA;
input [3:0] rB;


output reg [63:0] valA;
output reg [63:0] valB;

input [63:0] reg_file0;
input [63:0] reg_file1;
input [63:0] reg_file2;
input [63:0] reg_file3;
input [63:0] reg_file4;
input [63:0] reg_file5;
input [63:0] reg_file6;
input [63:0] reg_file7;
input [63:0] reg_file8;
input [63:0] reg_file9;
input [63:0] reg_file10;
input [63:0] reg_file11;
input [63:0] reg_file12;
input [63:0] reg_file13;
input [63:0] reg_file14;

reg [63:0] reg_memory [0:14];

always @ (*)  
    begin
        reg_memory[0] = reg_file0;
        reg_memory[1] = reg_file1;
        reg_memory[2] = reg_file2;
        reg_memory[3] = reg_file3;
        reg_memory[4] = reg_file4;
        reg_memory[5] = reg_file5;
        reg_memory[6] = reg_file6;
        reg_memory[7] = reg_file7;
        reg_memory[8] = reg_file8;
        reg_memory[9] = reg_file9;
        reg_memory[10] = reg_file10;
        reg_memory[11] = reg_file11;
        reg_memory[12] = reg_file12;
        reg_memory[13] = reg_file13;
        reg_memory[14] = reg_file14;

        case(icode)

        4'b0000: begin end


        4'b0001: begin end


        4'b0010: 
        begin 
            valA = reg_memory[rA];
        end


        4'b0011: begin end


        4'b0100: 
        begin 
            valA = reg_memory[rA];
            valB = reg_memory[rB];
        end
            

        4'b0101: 
        begin 
            valB = reg_memory[rB];
        end


        4'b0110: 
        begin 
            valA = reg_memory[rA];
            valB = reg_memory[rB];
        end


        4'b0111: begin end


        4'b1000: 
        begin 
            valB = reg_memory[4'b0100];
        end


        4'b1001: 
        begin 
            valA = reg_memory[4'b0100];
            valB = reg_memory[4'b0100];
        end


        4'b1010: 
        begin 
            valA = reg_memory[rA];
            valB = reg_memory[4'b0100];
        end


        4'b1011: 
        begin 
            valA = reg_memory[4'b0100];
            valB = reg_memory[4'b0100];
        end
        endcase
    end
endmodule
module decode_seq(clk, icode, rA, rB, valA, valB, reg_file0, reg_file1, reg_file2, reg_file3, reg_file4, reg_file5, reg_file6, reg_file7, reg_file8, reg_file9, reg_file10, reg_file11, reg_file12, reg_file13, reg_file14);


input clk;
input [3:0] icode;
input [3:0] rA;
input [3:0] rB;


output reg [63:0] valA;
output reg [63:0] valB;

input [63:0] reg_file0;
input [63:0] reg_file1;
input [63:0] reg_file2;
input [63:0] reg_file3;
input [63:0] reg_file4;
input [63:0] reg_file5;
input [63:0] reg_file6;
input [63:0] reg_file7;
input [63:0] reg_file8;
input [63:0] reg_file9;
input [63:0] reg_file10;
input [63:0] reg_file11;
input [63:0] reg_file12;
input [63:0] reg_file13;
input [63:0] reg_file14;

reg [63:0] reg_memory [0:14];

always @ (*)  
    begin
        reg_memory[0] = reg_file0;
        reg_memory[1] = reg_file1;
        reg_memory[2] = reg_file2;
        reg_memory[3] = reg_file3;
        reg_memory[4] = reg_file4;
        reg_memory[5] = reg_file5;
        reg_memory[6] = reg_file6;
        reg_memory[7] = reg_file7;
        reg_memory[8] = reg_file8;
        reg_memory[9] = reg_file9;
        reg_memory[10] = reg_file10;
        reg_memory[11] = reg_file11;
        reg_memory[12] = reg_file12;
        reg_memory[13] = reg_file13;
        reg_memory[14] = reg_file14;

        case(icode)

        4'b0000: begin end


        4'b0001: begin end


        4'b0010: 
        begin 
            valA = reg_memory[rA];
        end


        4'b0011: begin end


        4'b0100: 
        begin 
            valA = reg_memory[rA];
            valB = reg_memory[rB];
        end
            

        4'b0101: 
        begin 
            valB = reg_memory[rB];
        end


        4'b0110: 
        begin 
            valA = reg_memory[rA];
            valB = reg_memory[rB];
        end


        4'b0111: begin end


        4'b1000: 
        begin 
            valB = reg_memory[4'b0100];
        end


        4'b1001: 
        begin 
            valA = reg_memory[4'b0100];
            valB = reg_memory[4'b0100];
        end


        4'b1010: 
        begin 
            valA = reg_memory[rA];
            valB = reg_memory[4'b0100];
        end


        4'b1011: 
        begin 
            valA = reg_memory[4'b0100];
            valB = reg_memory[4'b0100];
        end
        endcase
    end
endmodule