data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/fpga-support/synth/BramDwc/src/Top.sv
1: b"%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/fpga-support/synth/BramDwc/src/Top.sv:33: Can't find definition of 'Clk_C' in dotted variable: 'fromMaster.Clk_C'\n  assign fromMaster.Clk_C   = '0;\n                    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/fpga-support/synth/BramDwc/src/Top.sv:34: Can't find definition of 'Rst_R' in dotted variable: 'fromMaster.Rst_R'\n  assign fromMaster.Rst_R   = '0;\n                    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/fpga-support/synth/BramDwc/src/Top.sv:35: Can't find definition of 'En_S' in dotted variable: 'fromMaster.En_S'\n  assign fromMaster.En_S    = '0;\n                    ^~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/fpga-support/synth/BramDwc/src/Top.sv:36: Can't find definition of 'Addr_S' in dotted variable: 'fromMaster.Addr_S'\n  assign fromMaster.Addr_S  = '0;\n                    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/fpga-support/synth/BramDwc/src/Top.sv:37: Can't find definition of 'Wr_D' in dotted variable: 'fromMaster.Wr_D'\n  assign fromMaster.Wr_D    = '0;\n                    ^~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/fpga-support/synth/BramDwc/src/Top.sv:38: Can't find definition of 'WrEn_S' in dotted variable: 'fromMaster.WrEn_S'\n  assign fromMaster.WrEn_S  = '0;\n                    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/fpga-support/synth/BramDwc/src/Top.sv:40: Can't find definition of 'Rd_D' in dotted variable: 'toSlave.Rd_D'\n  assign toSlave.Rd_D       = '0;\n                 ^~~~\n%Error: Exiting due to 7 error(s)\n"
module Top;

  localparam integer ADDR_BITW      = 32;
  localparam integer MST_DATA_BITW  = 32;
  localparam integer SLV_DATA_BITW  = 96;

  BramPort
    #(
      .DATA_BITW(MST_DATA_BITW),
      .ADDR_BITW(ADDR_BITW)
    )
    fromMaster ();

  BramPort
    #(
      .DATA_BITW(SLV_DATA_BITW),
      .ADDR_BITW(ADDR_BITW)
    )
    toSlave ();

  BramDwc
    #(
      .ADDR_BITW      (ADDR_BITW),
      .MST_DATA_BITW  (MST_DATA_BITW),
      .SLV_DATA_BITW  (SLV_DATA_BITW)
    ) dwc (
      .FromMaster_PS  (fromMaster),
      .ToSlave_PM     (toSlave)
    );

  assign fromMaster.Clk_C   = '0;
  assign fromMaster.Rst_R   = '0;
  assign fromMaster.En_S    = '0;
  assign fromMaster.Addr_S  = '0;
  assign fromMaster.Wr_D    = '0;
  assign fromMaster.WrEn_S  = '0;

  assign toSlave.Rd_D       = '0;

endmodule
module Top;


  localparam integer ADDR_BITW      = 32;
  localparam integer MST_DATA_BITW  = 32;
  localparam integer SLV_DATA_BITW  = 96;

  BramPort
    #(
      .DATA_BITW(MST_DATA_BITW),
      .ADDR_BITW(ADDR_BITW)
    )
    fromMaster ();

  BramPort
    #(
      .DATA_BITW(SLV_DATA_BITW),
      .ADDR_BITW(ADDR_BITW)
    )
    toSlave ();

  BramDwc
    #(
      .ADDR_BITW      (ADDR_BITW),
      .MST_DATA_BITW  (MST_DATA_BITW),
      .SLV_DATA_BITW  (SLV_DATA_BITW)
    ) dwc (
      .FromMaster_PS  (fromMaster),
      .ToSlave_PM     (toSlave)
    );

  assign fromMaster.Clk_C   = '0;
  assign fromMaster.Rst_R   = '0;
  assign fromMaster.En_S    = '0;
  assign fromMaster.Addr_S  = '0;
  assign fromMaster.Wr_D    = '0;
  assign fromMaster.WrEn_S  = '0;

  assign toSlave.Rd_D       = '0;

endmodule