data/full_repos/permissive/492581806/alumod.v
data/verilator_xmls/1b5d26a6-2f6f-42bc-ae7c-abcd2c58b0fe.xml
module ADD(DATA1,DATA2,Result);

input [7:0] DATA1,DATA2;
output [7:0] Result;



  assign #2 Result= DATA1 + DATA2;


endmodule
module ADD(DATA1,DATA2,Result);


input [7:0] DATA1,DATA2;
output [7:0] Result;



  assign #2 Result= DATA1 + DATA2;


endmodule