data/full_repos/permissive/496903659/135 fsm_serial.v
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/496903659/135\n        ... Looked in:\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/135\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/135.v\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/135.sv\n             data/full_repos/permissive/496903659/135\n             data/full_repos/permissive/496903659/135.v\n             data/full_repos/permissive/496903659/135.sv\n             obj_dir/data/full_repos/permissive/496903659/135\n             obj_dir/data/full_repos/permissive/496903659/135.v\n             obj_dir/data/full_repos/permissive/496903659/135.sv\n%Error: Cannot find file containing module: fsm_serial.v\n%Error: Exiting due to 2 error(s)\n'
module top_module(
    input clk,
    input in,
    input reset,
    output done
); 

    reg is_reset;
    reg [11:0] state;
    always @(posedge clk) begin
        is_reset <= reset;
        if (reset) begin
            ;
        end
        else if (is_reset & ~reset) begin
            if (in)
                state <= 1 << 10;
            else
                state <= 1 << 0;
        end
        else begin
            if (in)
                state <= state[8:0] << 1 | state[9] << 10 | state[10] << 10 | state[11] << 10;
            else
                state <= state[7:0] << 1 | state[8] << 11 | state[9] | state[10] | state[11] << 11;
        end
    end
    assign done = (state == 1 << 9);
endmodule
module top_module(
    input clk,
    input in,
    input reset,
    output done
);
 

    reg is_reset;
    reg [11:0] state;
    always @(posedge clk) begin
        is_reset <= reset;
        if (reset) begin
            ;
        end
        else if (is_reset & ~reset) begin
            if (in)
                state <= 1 << 10;
            else
                state <= 1 << 0;
        end
        else begin
            if (in)
                state <= state[8:0] << 1 | state[9] << 10 | state[10] << 10 | state[11] << 10;
            else
                state <= state[7:0] << 1 | state[8] << 11 | state[9] | state[10] | state[11] << 11;
        end
    end
    assign done = (state == 1 << 9);
endmodule