data/full_repos/permissive/434840709/week11/4.v
data/verilator_xmls/564c87d1-22e8-4d47-88a3-3724f4a110d9.xml
module top_module (
    input [7:0] a, b, c, d,
    output [7:0] min
);
    wire [7:0] result1,result2;
	assign result1 = a < b ? a : b;
    assign result2 = c < d ? c : d;
    assign min     = result1 < result2 ? result1 : result2;
endmodule
module top_module (
    input [7:0] a, b, c, d,
    output [7:0] min
);

    wire [7:0] result1,result2;
	assign result1 = a < b ? a : b;
    assign result2 = c < d ? c : d;
    assign min     = result1 < result2 ? result1 : result2;
endmodule