data/full_repos/permissive/511902453/main_control.v
1: b"%Error: data/full_repos/permissive/511902453/main_control.v:52: Define or directive not defined: '`b_type'\n assign branch=(opcode==`b_type)?1'b1:1'b0;\n                        ^~~~~~~\n%Error: data/full_repos/permissive/511902453/main_control.v:52: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n assign branch=(opcode==`b_type)?1'b1:1'b0;\n                               ^\n%Error: data/full_repos/permissive/511902453/main_control.v:53: Define or directive not defined: '`r_type'\n assign r_type=(opcode==`r_type)?1'b1:1'b0;\n                        ^~~~~~~\n%Error: data/full_repos/permissive/511902453/main_control.v:53: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n assign r_type=(opcode==`r_type)?1'b1:1'b0;\n                               ^\n%Error: data/full_repos/permissive/511902453/main_control.v:54: Define or directive not defined: '`i_type'\n assign i_type=(opcode==`i_type)?1'b1:1'b0;\n                        ^~~~~~~\n%Error: data/full_repos/permissive/511902453/main_control.v:54: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n assign i_type=(opcode==`i_type)?1'b1:1'b0;\n                               ^\n%Error: data/full_repos/permissive/511902453/main_control.v:56: Define or directive not defined: '`load'\n assign load=(opcode==`load)?1'b1:1'b0;\n                      ^~~~~\n%Error: data/full_repos/permissive/511902453/main_control.v:56: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n assign load=(opcode==`load)?1'b1:1'b0;\n                           ^\n%Error: data/full_repos/permissive/511902453/main_control.v:57: Define or directive not defined: '`store'\n assign store=(opcode==`store)?1'b1:1'b0;\n                       ^~~~~~\n%Error: data/full_repos/permissive/511902453/main_control.v:57: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n assign store=(opcode==`store)?1'b1:1'b0;\n                             ^\n%Error: data/full_repos/permissive/511902453/main_control.v:59: Define or directive not defined: '`jal'\n assign jal=(opcode==`jal)?1'b1:1'b0;\n                     ^~~~\n%Error: data/full_repos/permissive/511902453/main_control.v:59: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n assign jal=(opcode==`jal)?1'b1:1'b0;\n                         ^\n%Error: data/full_repos/permissive/511902453/main_control.v:60: Define or directive not defined: '`jalr'\n assign jalr=(opcode==`jalr)?1'b1:1'b0;\n                      ^~~~~\n%Error: data/full_repos/permissive/511902453/main_control.v:60: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n assign jalr=(opcode==`jalr)?1'b1:1'b0;\n                           ^\n%Error: data/full_repos/permissive/511902453/main_control.v:61: Define or directive not defined: '`lui'\n assign lui=(opcode==`lui)?1'b1:1'b0;\n                     ^~~~\n%Error: data/full_repos/permissive/511902453/main_control.v:61: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n assign lui=(opcode==`lui)?1'b1:1'b0;\n                         ^\n%Error: data/full_repos/permissive/511902453/main_control.v:62: Define or directive not defined: '`auipc'\n assign auipc=(opcode==`auipc)?1'b1:1'b0;\n                       ^~~~~~\n%Error: data/full_repos/permissive/511902453/main_control.v:62: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\n assign auipc=(opcode==`auipc)?1'b1:1'b0;\n                             ^\n%Error: data/full_repos/permissive/511902453/main_control.v:73: syntax error, unexpected assign, expecting IDENTIFIER\n assign memread= load;\n ^~~~~~\n%Error: data/full_repos/permissive/511902453/main_control.v:78: syntax error, unexpected assign, expecting IDENTIFIER\n assign alusrc=load | store |i_type | jalr;   \n ^~~~~~\n%Error: data/full_repos/permissive/511902453/main_control.v:82: syntax error, unexpected assign, expecting IDENTIFIER\n assign aluop[1]= r_type|branch;  \n ^~~~~~\n%Error: Exiting due to 21 error(s)\n"
module main_control(
	opcode,
	func3,
	memread,
	memtoreg,
	aluop,
	memwrite,
	alusrc,
	regwrite,
	lui,
	u_type,
	jal,
	jalr,
	beq,
	bne,
	blt,
	bge,
	bltu,
	bgeu,
	rw_type
    );
	input [6:0]opcode;
	input [2:0]func3;
	
	output   memread;
	output   memtoreg;
	output   [1:0]aluop;
	output   memwrite;
	output   alusrc;
	output   regwrite;
	output   lui;
	output   u_type;
	output   jal;
	output   jalr;
	output   beq;
	output   bne;
	output   blt;
	output   bge;
	output   bltu;
	output   bgeu;
	output   [2:0]rw_type;
	
	wire branch;
	wire r_type;
	wire i_type;
	wire load;
	wire store;
	wire lui;
	wire auipc;

	
	assign branch=(opcode==`b_type)?1'b1:1'b0;
	assign r_type=(opcode==`r_type)?1'b1:1'b0;
	assign i_type=(opcode==`i_type)?1'b1:1'b0;
	assign u_type=(lui | auipc)? 1'b1:1'b0;
	assign load=(opcode==`load)?1'b1:1'b0;
	assign store=(opcode==`store)?1'b1:1'b0;
	
	assign jal=(opcode==`jal)?1'b1:1'b0;
	assign jalr=(opcode==`jalr)?1'b1:1'b0;
	assign lui=(opcode==`lui)?1'b1:1'b0;
	assign auipc=(opcode==`auipc)?1'b1:1'b0;
	assign beq= branch & (func3==3'b000);
	assign bne= branch & (func3==3'b001);
	assign blt= branch & (func3==3'b100);
	assign bge= branch & (func3==3'b101);
	assign bltu= branch & (func3==3'b110);
	assign bgeu= branch & (func3==3'b111);
	assign rw_type=func3;
	
	
	enable
	assign memread= load;
	assign memwrite= store;
	assign regwrite= jal| jalr | load | i_type |r_type | u_type;
	
	mux
	assign alusrc=load | store |i_type | jalr;
	assign memtoreg= load;
	
	aluop
	assign aluop[1]= r_type|branch;
	assign aluop[0]= i_type|branch;
	
	
endmodule
module main_control(
	opcode,
	func3,
	memread,
	memtoreg,
	aluop,
	memwrite,
	alusrc,
	regwrite,
	lui,
	u_type,
	jal,
	jalr,
	beq,
	bne,
	blt,
	bge,
	bltu,
	bgeu,
	rw_type
    );

	input [6:0]opcode;
	input [2:0]func3;
	
	output   memread;
	output   memtoreg;
	output   [1:0]aluop;
	output   memwrite;
	output   alusrc;
	output   regwrite;
	output   lui;
	output   u_type;
	output   jal;
	output   jalr;
	output   beq;
	output   bne;
	output   blt;
	output   bge;
	output   bltu;
	output   bgeu;
	output   [2:0]rw_type;
	
	wire branch;
	wire r_type;
	wire i_type;
	wire load;
	wire store;
	wire lui;
	wire auipc;

	
	assign branch=(opcode==`b_type)?1'b1:1'b0;
	assign r_type=(opcode==`r_type)?1'b1:1'b0;
	assign i_type=(opcode==`i_type)?1'b1:1'b0;
	assign u_type=(lui | auipc)? 1'b1:1'b0;
	assign load=(opcode==`load)?1'b1:1'b0;
	assign store=(opcode==`store)?1'b1:1'b0;
	
	assign jal=(opcode==`jal)?1'b1:1'b0;
	assign jalr=(opcode==`jalr)?1'b1:1'b0;
	assign lui=(opcode==`lui)?1'b1:1'b0;
	assign auipc=(opcode==`auipc)?1'b1:1'b0;
	assign beq= branch & (func3==3'b000);
	assign bne= branch & (func3==3'b001);
	assign blt= branch & (func3==3'b100);
	assign bge= branch & (func3==3'b101);
	assign bltu= branch & (func3==3'b110);
	assign bgeu= branch & (func3==3'b111);
	assign rw_type=func3;
	
	
	enable
	assign memread= load;
	assign memwrite= store;
	assign regwrite= jal| jalr | load | i_type |r_type | u_type;
	
	mux
	assign alusrc=load | store |i_type | jalr;
	assign memtoreg= load;
	
	aluop
	assign aluop[1]= r_type|branch;
	assign aluop[0]= i_type|branch;
	
	
endmodule