data/full_repos/permissive/427281804/FPU/verilog/FPALU_dummy.v
1: b'%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/FPALU_dummy.v:84: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s ADD generates 7 bits.\n                                                                                 : ... In instance FPALU_dummy\nassign dout_uni_y_exp = {1\'b0, ae_s5_r} + {1\'b0, be_s5_r};\n                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module FPALU_dummy (

	input           clk,
	input [1:0]		opcode,

	input           din_uni_a_sgn,
	input [5:0]     din_uni_a_exp,
	input [21:0]    din_uni_a_man_dn,

	input           din_uni_b_sgn,
	input [5:0]     din_uni_b_exp,
	input [21:0]    din_uni_b_man_dn,


	output          dout_uni_y_sgn,
	output [5:0]    dout_uni_y_exp, 
	output [21:0]   dout_uni_y_man_dn
);

reg        as_s2_r;
reg [5:0]  ae_s2_r;
reg [21:0] am_s2_r;

reg        bs_s2_r;
reg [5:0]  be_s2_r;
reg [21:0] bm_s2_r;

reg        as_s3_r;
reg [5:0]  ae_s3_r;
reg [21:0] am_s3_r;

reg        bs_s3_r;
reg [5:0]  be_s3_r;
reg [21:0] bm_s3_r;

reg        as_s4_r;
reg [5:0]  ae_s4_r;
reg [21:0] am_s4_r;

reg        bs_s4_r;
reg [5:0]  be_s4_r;
reg [21:0] bm_s4_r;

reg        as_s5_r;
reg [5:0]  ae_s5_r;
reg [21:0] am_s5_r;

reg        bs_s5_r;
reg [5:0]  be_s5_r;
reg [21:0] bm_s5_r;

always @(posedge clk) begin
	as_s2_r <= din_uni_a_sgn;
	ae_s2_r <= din_uni_a_exp;
	am_s2_r <= din_uni_a_man_dn;
	bs_s2_r <= din_uni_b_sgn;
	be_s2_r <= din_uni_b_exp;
	bm_s2_r <= din_uni_b_man_dn;

	as_s3_r <= as_s2_r;
	ae_s3_r <= ae_s2_r;
	am_s3_r <= am_s2_r;
	bs_s3_r <= bs_s2_r;
	be_s3_r <= be_s2_r;
	bm_s3_r <= bm_s2_r;
	
	as_s4_r <= as_s3_r;
	ae_s4_r <= ae_s3_r;
	am_s4_r <= am_s3_r;
	bs_s4_r <= bs_s3_r;
	be_s4_r <= be_s3_r;
	bm_s4_r <= bm_s3_r;
	
	as_s5_r <= as_s4_r;
	ae_s5_r <= ae_s4_r;
	am_s5_r <= am_s4_r;
	bs_s5_r <= bs_s4_r;
	be_s5_r <= be_s4_r;
	bm_s5_r <= bm_s4_r;	
end

assign dout_uni_y_sgn = as_s5_r ^ bs_s5_r;
assign dout_uni_y_exp = {1'b0, ae_s5_r} + {1'b0, be_s5_r};
assign dout_uni_y_man_dn = {6'b0, am_s5_r[7:0], bm_s5_r[7:0]};

endmodule
module FPALU_dummy (

	input           clk,
	input [1:0]		opcode,

	input           din_uni_a_sgn,
	input [5:0]     din_uni_a_exp,
	input [21:0]    din_uni_a_man_dn,

	input           din_uni_b_sgn,
	input [5:0]     din_uni_b_exp,
	input [21:0]    din_uni_b_man_dn,


	output          dout_uni_y_sgn,
	output [5:0]    dout_uni_y_exp, 
	output [21:0]   dout_uni_y_man_dn
);


reg        as_s2_r;
reg [5:0]  ae_s2_r;
reg [21:0] am_s2_r;

reg        bs_s2_r;
reg [5:0]  be_s2_r;
reg [21:0] bm_s2_r;

reg        as_s3_r;
reg [5:0]  ae_s3_r;
reg [21:0] am_s3_r;

reg        bs_s3_r;
reg [5:0]  be_s3_r;
reg [21:0] bm_s3_r;

reg        as_s4_r;
reg [5:0]  ae_s4_r;
reg [21:0] am_s4_r;

reg        bs_s4_r;
reg [5:0]  be_s4_r;
reg [21:0] bm_s4_r;

reg        as_s5_r;
reg [5:0]  ae_s5_r;
reg [21:0] am_s5_r;

reg        bs_s5_r;
reg [5:0]  be_s5_r;
reg [21:0] bm_s5_r;

always @(posedge clk) begin
	as_s2_r <= din_uni_a_sgn;
	ae_s2_r <= din_uni_a_exp;
	am_s2_r <= din_uni_a_man_dn;
	bs_s2_r <= din_uni_b_sgn;
	be_s2_r <= din_uni_b_exp;
	bm_s2_r <= din_uni_b_man_dn;

	as_s3_r <= as_s2_r;
	ae_s3_r <= ae_s2_r;
	am_s3_r <= am_s2_r;
	bs_s3_r <= bs_s2_r;
	be_s3_r <= be_s2_r;
	bm_s3_r <= bm_s2_r;
	
	as_s4_r <= as_s3_r;
	ae_s4_r <= ae_s3_r;
	am_s4_r <= am_s3_r;
	bs_s4_r <= bs_s3_r;
	be_s4_r <= be_s3_r;
	bm_s4_r <= bm_s3_r;
	
	as_s5_r <= as_s4_r;
	ae_s5_r <= ae_s4_r;
	am_s5_r <= am_s4_r;
	bs_s5_r <= bs_s4_r;
	be_s5_r <= be_s4_r;
	bm_s5_r <= bm_s4_r;	
end

assign dout_uni_y_sgn = as_s5_r ^ bs_s5_r;
assign dout_uni_y_exp = {1'b0, ae_s5_r} + {1'b0, be_s5_r};
assign dout_uni_y_man_dn = {6'b0, am_s5_r[7:0], bm_s5_r[7:0]};

endmodule