data/full_repos/permissive/447976230/fpga/usrp2/models/MULT18X18S.v
data/verilator_xmls/2b715d5b-4e80-458b-be1f-c7c9a75a4902.xml
module MULT18X18S
  (output reg signed [35:0] P,
   input signed [17:0] A,
   input signed [17:0] B,
   input C,
   input CE,
   input R
   );
   
   always @(posedge C)
     if(R)
       P <= 36'sd0;
     else if(CE)
       P <= A * B;

endmodule
module MULT18X18S
  (output reg signed [35:0] P,
   input signed [17:0] A,
   input signed [17:0] B,
   input C,
   input CE,
   input R
   );

   
   always @(posedge C)
     if(R)
       P <= 36'sd0;
     else if(CE)
       P <= A * B;

endmodule