data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Finite State Machines/Fsm_serial/top_module_tb.v
1: b'%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines/Fsm_serial,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/Fsm_serial/top_module_tb.v\n%Error: Exiting due to 5 error(s)\n'
module top_module_tb ();
  reg clk = 1'd1;
  reg reset = 1'd1;
  reg in = 1'd1;
  wire done;

  localparam ITERATIONS = 1000;

  always begin
    #5 clk = clk + 1;
  end

  always begin
    #10 in = 1'b0;
    #90 in = 1'b1;
    #10 in = 1'b0;
    #90 in = 1'b1;
    #10 in = 1'b0;
    #100;

    #10 in = 1'b1;
    #30 in = 1'b0;
    #10 in = 1'b0;
    #10 in = 1'b0;
    #10 in = 1'b0;
    #10 in = 1'b0;
    #10 in = 1'b0;
    #10 in = 1'b0;
    #10 in = 1'b0;
    #10 in = 1'b0;
    #10 in = 1'b1;

    #10 in = 1'b1;
    #30 in = 1'b0;
    #10 in = $random;
    #10 in = $random;
    #10 in = $random;
    #10 in = $random;
    #10 in = $random;
    #10 in = $random;
    #10 in = $random;
    #10 in = $random;
    #10 in = 1'b0;

  end

  initial begin
    #10 reset = 1'b0;
  end

  top_module uut (
      .clk(clk),
      .reset(reset),
      .in(in),
      .done(done)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule
module top_module_tb ();

  reg clk = 1'd1;
  reg reset = 1'd1;
  reg in = 1'd1;
  wire done;

  localparam ITERATIONS = 1000;

  always begin
    #5 clk = clk + 1;
  end

  always begin
    #10 in = 1'b0;
    #90 in = 1'b1;
    #10 in = 1'b0;
    #90 in = 1'b1;
    #10 in = 1'b0;
    #100;

    #10 in = 1'b1;
    #30 in = 1'b0;
    #10 in = 1'b0;
    #10 in = 1'b0;
    #10 in = 1'b0;
    #10 in = 1'b0;
    #10 in = 1'b0;
    #10 in = 1'b0;
    #10 in = 1'b0;
    #10 in = 1'b0;
    #10 in = 1'b1;

    #10 in = 1'b1;
    #30 in = 1'b0;
    #10 in = $random;
    #10 in = $random;
    #10 in = $random;
    #10 in = $random;
    #10 in = $random;
    #10 in = $random;
    #10 in = $random;
    #10 in = $random;
    #10 in = 1'b0;

  end

  initial begin
    #10 reset = 1'b0;
  end

  top_module uut (
      .clk(clk),
      .reset(reset),
      .in(in),
      .done(done)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule