data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/ffxkclk.v
data/verilator_xmls/01113211-40a0-4d42-b890-65d6e144c86a.xml
module ffxkclk
    (
     clk,
     rst,
     idat,
     odat
     );



parameter           K = 3;



input               clk,
                    rst;
input               idat;
output              odat;
  


wire                odat;



reg [K-1:0]         shift_dat = {K{1'b0}};
wire [K:0]          shift_in;
assign              shift_in = {shift_dat,idat};

always @ (posedge clk)
    begin
    shift_dat <= shift_in[K-1:0];
    end
assign odat = shift_dat[K-1];

endmodule
module ffxkclk
    (
     clk,
     rst,
     idat,
     odat
     );




parameter           K = 3;



input               clk,
                    rst;
input               idat;
output              odat;
  


wire                odat;



reg [K-1:0]         shift_dat = {K{1'b0}};
wire [K:0]          shift_in;
assign              shift_in = {shift_dat,idat};

always @ (posedge clk)
    begin
    shift_dat <= shift_in[K-1:0];
    end
assign odat = shift_dat[K-1];

endmodule