data/full_repos/permissive/486598419/6.1/logic_gates_3.v
data/verilator_xmls/8d372246-5aad-4510-ac09-832d7de7819d.xml
module logic_gates_3( iA, iB,oAnd,oOr,oNot );
   input iA,iB;
   output reg oAnd,oOr,oNot;
   always @ (*)
   begin
      oAnd = iA & iB;
      oOr = iA | iB;
      oNot = ~iA;
   end
endmodule
module logic_gates_3( iA, iB,oAnd,oOr,oNot );

   input iA,iB;
   output reg oAnd,oOr,oNot;
   always @ (*)
   begin
      oAnd = iA & iB;
      oOr = iA | iB;
      oNot = ~iA;
   end
endmodule