data/full_repos/permissive/482848318/ALU_testbench.v
1: b'%Error: data/full_repos/permissive/482848318/ALU_testbench.v:17: Unsupported or unknown PLI call: $monitor\n    $monitor($time, " Ain=%d, Bin=%d, ALUop=%b,  ALUout=%d ",Ain, Bin, ALUop,  ALUout);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/482848318/ALU_testbench.v:22: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("ALU.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/482848318/ALU_testbench.v:23: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(1, ALU_testbench);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/482848318/ALU_testbench.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #0  Ain = 15; Bin = 0; ALUop = 0;  \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/482848318/ALU_testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #50 Ain <= Ain -1; Bin <= Bin + 1;\n        ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ALU_testbench();
  
  reg [3:0] Ain, Bin;
  reg [2:0] ALUop;
  wire [3:0] ALUout;
  
  ALU DUT ( .Ain(Ain), .Bin(Bin), .ALUop(ALUop), .ALUout(ALUout));
  
  initial
  begin
    $monitor($time, " Ain=%d, Bin=%d, ALUop=%b,  ALUout=%d ",Ain, Bin, ALUop,  ALUout);
  end
  
  initial
  begin
    $dumpfile("ALU.vcd");
    $dumpvars(1, ALU_testbench);
    
    #0  Ain = 15; Bin = 0; ALUop = 0;
    repeat (6)
    begin
      repeat (15)
      begin
        #50 Ain <= Ain -1; Bin <= Bin + 1;
      end
      ALUop <= ALUop + 1;
    end
    
  end
  
endmodule
module ALU_testbench();

  
  reg [3:0] Ain, Bin;
  reg [2:0] ALUop;
  wire [3:0] ALUout;
  
  ALU DUT ( .Ain(Ain), .Bin(Bin), .ALUop(ALUop), .ALUout(ALUout));
  
  initial
  begin
    $monitor($time, " Ain=%d, Bin=%d, ALUop=%b,  ALUout=%d ",Ain, Bin, ALUop,  ALUout);
  end
  
  initial
  begin
    $dumpfile("ALU.vcd");
    $dumpvars(1, ALU_testbench);
    
    #0  Ain = 15; Bin = 0; ALUop = 0;
    repeat (6)
    begin
      repeat (15)
      begin
        #50 Ain <= Ain -1; Bin <= Bin + 1;
      end
      ALUop <= ALUop + 1;
    end
    
  end
  
endmodule