data/full_repos/permissive/529469310/RSA/Smult_Func_tb.v
1: b'%Error: data/full_repos/permissive/529469310/RSA/Smult_Func_tb.v:31: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("dump.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/529469310/RSA/Smult_Func_tb.v:32: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/529469310/RSA/Smult_Func_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #10000 \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/529469310/RSA/Smult_Func_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\nalways #50  clk = ~clk;\n       ^\n%Error: data/full_repos/permissive/529469310/RSA/Smult_Func_tb.v:50: syntax error, unexpected \'@\'\n        @(posedge clk)  #10;\n        ^\n%Error: data/full_repos/permissive/529469310/RSA/Smult_Func_tb.v:52: syntax error, unexpected \'@\'\n        @(posedge clk)  #10;\n        ^\n%Error: data/full_repos/permissive/529469310/RSA/Smult_Func_tb.v:53: syntax error, unexpected \'@\'\n    while (busy==1) @(posedge clk);\n                    ^\n%Error: Exiting due to 5 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Smulti_test;

reg [`Bit*2:0] mem [0:9];
reg [`Bit*2-1:0] Expect;

reg clk, start;
reg [`Bit-1:0] A,B;
wire busy;
wire [`Bit:0] Hreg;
wire [`Bit-1:0] Lreg;

integer i;

S_multi mult(clk, start, busy, A, B, Hreg, Lreg);

initial begin
  $dumpfile("dump.vcd");
  $dumpvars;
  #10000 
  $finish;
end

always #50  clk = ~clk;

initial begin
    mem[0] = {`Bit'h1,`Bit'h1};
    mem[1] = {`Bit'h1,`Bit'h0};
    mem[2] = {`Bit'h0,`Bit'h1};
    mem[3] = {`Bit'h11,`Bit'h2};  
    clk=1;

    for(i=0;i<10;i=i+1)begin
        start = 0;
        {A,B} = mem[i];
        Expect = A * B;
        @(posedge clk)  #`delay;
        start = 1;
        @(posedge clk)  #`delay;
    while (busy==1) @(posedge clk);

    if(Expect=={Hreg[`Bit-1:0],Lreg}) begin
        $display("Match M=%h Expect=%h",{Hreg[`Bit-1:0],Lreg},Expect);
    end else begin
        $display("Error M=%h Expect=%h",{Hreg[`Bit-1:0],Lreg},Expect);
    end
        
    end
$finish;
end

endmodule
module Smulti_test;


reg [`Bit*2:0] mem [0:9];
reg [`Bit*2-1:0] Expect;

reg clk, start;
reg [`Bit-1:0] A,B;
wire busy;
wire [`Bit:0] Hreg;
wire [`Bit-1:0] Lreg;

integer i;

S_multi mult(clk, start, busy, A, B, Hreg, Lreg);

initial begin
  $dumpfile("dump.vcd");
  $dumpvars;
  #10000 
  $finish;
end

always #50  clk = ~clk;

initial begin
    mem[0] = {`Bit'h1,`Bit'h1};
    mem[1] = {`Bit'h1,`Bit'h0};
    mem[2] = {`Bit'h0,`Bit'h1};
    mem[3] = {`Bit'h11,`Bit'h2};  
    clk=1;

    for(i=0;i<10;i=i+1)begin
        start = 0;
        {A,B} = mem[i];
        Expect = A * B;
        @(posedge clk)  #`delay;
        start = 1;
        @(posedge clk)  #`delay;
    while (busy==1) @(posedge clk);

    if(Expect=={Hreg[`Bit-1:0],Lreg}) begin
        $display("Match M=%h Expect=%h",{Hreg[`Bit-1:0],Lreg},Expect);
    end else begin
        $display("Error M=%h Expect=%h",{Hreg[`Bit-1:0],Lreg},Expect);
    end
        
    end
$finish;
end

endmodule