data/full_repos/permissive/472097485/Chu01/G8ter4Bit_03/Test_G8ter2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu01/G8ter4Bit_03/Test_G8ter2.v:19: Unsupported: Ignoring delay on this delayed statement.\n #1 a[0] = !a[0];\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu01/G8ter4Bit_03/Test_G8ter2.v:22: Unsupported: Ignoring delay on this delayed statement.\n #2 a[1] = !a[1];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu01/G8ter4Bit_03/Test_G8ter2.v:25: Unsupported: Ignoring delay on this delayed statement.\n #4 b[0] = !b[0];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu01/G8ter4Bit_03/Test_G8ter2.v:28: Unsupported: Ignoring delay on this delayed statement.\n #8 b[1] = !b[1];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu01/G8ter4Bit_03/Test_G8ter2.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Error: data/full_repos/permissive/472097485/Chu01/G8ter4Bit_03/Test_G8ter2.v:16: Cannot find file containing module: \'G8ter2\'\n G8ter2 uut ( .a(a), .b(b), .g(g) );\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/472097485/Chu01/G8ter4Bit_03,data/full_repos/permissive/472097485/G8ter2\n             data/full_repos/permissive/472097485/Chu01/G8ter4Bit_03,data/full_repos/permissive/472097485/G8ter2.v\n             data/full_repos/permissive/472097485/Chu01/G8ter4Bit_03,data/full_repos/permissive/472097485/G8ter2.sv\n             G8ter2\n             G8ter2.v\n             G8ter2.sv\n             obj_dir/G8ter2\n             obj_dir/G8ter2.v\n             obj_dir/G8ter2.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Test_G8ter2;


	reg [1:0] a;
	reg [1:0] b;


	wire g;


	G8ter2 uut ( .a(a), .b(b), .g(g) );

	always begin
	#1 a[0] = !a[0];
	end
	always begin
	#2 a[1] = !a[1];
	end
	always begin
	#4 b[0] = !b[0];
	end
	always begin
	#8 b[1] = !b[1];
	end

	initial begin

		a = 0;
		b = 0;


		#20;
        

		$stop;
	end
      
endmodule
module Test_G8ter2;



	reg [1:0] a;
	reg [1:0] b;


	wire g;


	G8ter2 uut ( .a(a), .b(b), .g(g) );

	always begin
	#1 a[0] = !a[0];
	end
	always begin
	#2 a[1] = !a[1];
	end
	always begin
	#4 b[0] = !b[0];
	end
	always begin
	#8 b[1] = !b[1];
	end

	initial begin

		a = 0;
		b = 0;


		#20;
        

		$stop;
	end
      
endmodule