data/full_repos/permissive/459838989/rtl/fpga_wrapper/syn_harness.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/459838989/rtl/fpga_wrapper/syn_harness.v:205: Multiple top level modules\n                                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                          : ... Top module \'Synthesis_Harness_Input\'\nmodule Synthesis_Harness_Input #(\n       ^~~~~~~~~~~~~~~~~~~~~~~\n                                                                                          : ... Top module \'Synthesis_Harness_Output\'\nmodule Synthesis_Harness_Output #(\n       ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/459838989/rtl/fpga_wrapper/syn_harness.v:177: Replication value of 0 is only legal under a concatenation (IEEE 1800-2017 11.4.12.1)\n                                                                               : ... In instance Synthesis_Harness_Input\nlocalparam WORD_ZERO = {WORD_WIDTH{1\'b0}};\n                                  ^\n%Warning-LITENDIAN: data/full_repos/permissive/459838989/rtl/fpga_wrapper/syn_harness.v:75: Little bit endian vector: MSB < LSB of bit range: -1:0\n    parameter [TOTAL_WIDTH-1:0] RESET_VALUES = 0\n              ^\n%Warning-WIDTH: data/full_repos/permissive/459838989/rtl/fpga_wrapper/syn_harness.v:75: Operator VAR \'RESET_VALUES\' expects 2 bits on the Initial value, but Initial value\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                      : ... In instance Synthesis_Harness_Input.shift_bit_into_word\n    parameter [TOTAL_WIDTH-1:0] RESET_VALUES = 0\n                                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/459838989/rtl/fpga_wrapper/syn_harness.v:216: Replication value of 0 is only legal under a concatenation (IEEE 1800-2017 11.4.12.1)\n                                                                               : ... In instance Synthesis_Harness_Output\nlocalparam WORD_ZERO = {WORD_WIDTH{1\'b0}};\n                                  ^\n%Error: data/full_repos/permissive/459838989/rtl/fpga_wrapper/syn_harness.v:88: Replication value of 0 is only legal under a concatenation (IEEE 1800-2017 11.4.12.1)\n                                                                              : ... In instance Synthesis_Harness_Output.word_register\nlocalparam WORD_ZERO = {WORD_WIDTH{1\'b0}};\n                                  ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n'
module Register_Pipeline #(
    parameter WORD_WIDTH = 0,
    parameter PIPE_DEPTH = 0,

    parameter TOTAL_WIDTH = WORD_WIDTH * PIPE_DEPTH,

    parameter [TOTAL_WIDTH-1:0] RESET_VALUES = 0
)
(
    input clock,
    input clock_enable,
    input clear,
    input parallel_load,
    input [TOTAL_WIDTH-1:0] parallel_in,
    output reg [TOTAL_WIDTH-1:0] parallel_out,
    input [WORD_WIDTH-1:0] pipe_in,
    output reg [WORD_WIDTH-1:0] pipe_out
);

localparam WORD_ZERO = {WORD_WIDTH{1'b0}};

initial begin
    pipe_out = WORD_ZERO;
end

wire [WORD_WIDTH-1:0] pipe_stage_in [PIPE_DEPTH-1:0];
wire [WORD_WIDTH-1:0] pipe_stage_out [PIPE_DEPTH-1:0];

(* multstyle = "logic" *)
(* use_dsp   = "no" *)

Multiplexer_Binary_Behavioural #(
    .WORD_WIDTH     (WORD_WIDTH),
    .ADDR_WIDTH     (1),
    .INPUT_COUNT    (2)
) pipe_input_select (
    .selector       (parallel_load),
    .words_in       ({parallel_in[0 +: WORD_WIDTH], pipe_in}),
    .word_out       (pipe_stage_in[0])
);

Register #(
    .WORD_WIDTH     (WORD_WIDTH),
    .RESET_VALUE    (RESET_VALUES[0 +: WORD_WIDTH])
) pipe_stage (
    .clock          (clock),
    .clock_enable   (clock_enable),
    .clear          (clear),
    .data_in        (pipe_stage_in[0]),
    .data_out       (pipe_stage_out[0])
);

always @ (*) begin
    parallel_out[0 +: WORD_WIDTH] = pipe_stage_out[0];
end

generate
    genvar i;

    for (i = 1; i < PIPE_DEPTH; i = i + 1) begin : pipe_stages
        (* multstyle = "logic" *)
        (* use_dsp   = "no" *)

        Multiplexer_Binary_Behavioural #(
            .WORD_WIDTH     (WORD_WIDTH),
            .ADDR_WIDTH     (1),
            .INPUT_COUNT    (2)
        ) pipe_input_select (
            .selector       (parallel_load),
            .words_in       ({parallel_in[WORD_WIDTH*i +: WORD_WIDTH], pipe_stage_out[i-1]}),
            .word_out       (pipe_stage_in[i])
        );

        Register #(
            .WORD_WIDTH     (WORD_WIDTH),
            .RESET_VALUE    (RESET_VALUES[WORD_WIDTH*i +: WORD_WIDTH])
        ) pipe_stage (
            .clock          (clock),
            .clock_enable   (clock_enable),
            .clear          (clear),
            .data_in        (pipe_stage_in[i]),
            .data_out       (pipe_stage_out[i])
        );

        always @ (*) begin
            parallel_out[WORD_WIDTH*i +: WORD_WIDTH] = pipe_stage_out[i];
        end
    end
endgenerate

always @ (*) begin
    pipe_out = pipe_stage_out[PIPE_DEPTH-1];
end

endmodule
module Register_Pipeline #(
    parameter WORD_WIDTH = 0,
    parameter PIPE_DEPTH = 0,

    parameter TOTAL_WIDTH = WORD_WIDTH * PIPE_DEPTH,

    parameter [TOTAL_WIDTH-1:0] RESET_VALUES = 0
)
(
    input clock,
    input clock_enable,
    input clear,
    input parallel_load,
    input [TOTAL_WIDTH-1:0] parallel_in,
    output reg [TOTAL_WIDTH-1:0] parallel_out,
    input [WORD_WIDTH-1:0] pipe_in,
    output reg [WORD_WIDTH-1:0] pipe_out
);


localparam WORD_ZERO = {WORD_WIDTH{1'b0}};

initial begin
    pipe_out = WORD_ZERO;
end

wire [WORD_WIDTH-1:0] pipe_stage_in [PIPE_DEPTH-1:0];
wire [WORD_WIDTH-1:0] pipe_stage_out [PIPE_DEPTH-1:0];

(* multstyle = "logic" *)
(* use_dsp   = "no" *)

Multiplexer_Binary_Behavioural #(
    .WORD_WIDTH     (WORD_WIDTH),
    .ADDR_WIDTH     (1),
    .INPUT_COUNT    (2)
) pipe_input_select (
    .selector       (parallel_load),
    .words_in       ({parallel_in[0 +: WORD_WIDTH], pipe_in}),
    .word_out       (pipe_stage_in[0])
);

Register #(
    .WORD_WIDTH     (WORD_WIDTH),
    .RESET_VALUE    (RESET_VALUES[0 +: WORD_WIDTH])
) pipe_stage (
    .clock          (clock),
    .clock_enable   (clock_enable),
    .clear          (clear),
    .data_in        (pipe_stage_in[0]),
    .data_out       (pipe_stage_out[0])
);

always @ (*) begin
    parallel_out[0 +: WORD_WIDTH] = pipe_stage_out[0];
end

generate
    genvar i;

    for (i = 1; i < PIPE_DEPTH; i = i + 1) begin : pipe_stages
        (* multstyle = "logic" *)
        (* use_dsp   = "no" *)

        Multiplexer_Binary_Behavioural #(
            .WORD_WIDTH     (WORD_WIDTH),
            .ADDR_WIDTH     (1),
            .INPUT_COUNT    (2)
        ) pipe_input_select (
            .selector       (parallel_load),
            .words_in       ({parallel_in[WORD_WIDTH*i +: WORD_WIDTH], pipe_stage_out[i-1]}),
            .word_out       (pipe_stage_in[i])
        );

        Register #(
            .WORD_WIDTH     (WORD_WIDTH),
            .RESET_VALUE    (RESET_VALUES[WORD_WIDTH*i +: WORD_WIDTH])
        ) pipe_stage (
            .clock          (clock),
            .clock_enable   (clock_enable),
            .clear          (clear),
            .data_in        (pipe_stage_in[i]),
            .data_out       (pipe_stage_out[i])
        );

        always @ (*) begin
            parallel_out[WORD_WIDTH*i +: WORD_WIDTH] = pipe_stage_out[i];
        end
    end
endgenerate

always @ (*) begin
    pipe_out = pipe_stage_out[PIPE_DEPTH-1];
end

endmodule