data/full_repos/permissive/49670587/vtr/quick_test/depth_split.v
1: b"%Error: data/full_repos/permissive/49670587/vtr/quick_test/depth_split.v:13: Cannot find file containing module: 'single_port_ram'\nsingle_port_ram new_ram(\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/49670587/vtr/quick_test,data/full_repos/permissive/49670587/single_port_ram\n             data/full_repos/permissive/49670587/vtr/quick_test,data/full_repos/permissive/49670587/single_port_ram.v\n             data/full_repos/permissive/49670587/vtr/quick_test,data/full_repos/permissive/49670587/single_port_ram.sv\n             single_port_ram\n             single_port_ram.v\n             single_port_ram.sv\n             obj_dir/single_port_ram\n             obj_dir/single_port_ram.v\n             obj_dir/single_port_ram.sv\n%Error: Exiting due to 1 error(s)\n"
module depth_split (we, addr, datain, dataout, clk);

    input we; 
    input[11 - 1:0] addr; 
    input[2 - 1:0] datain; 
    output[2 - 1:0] dataout; 
    wire[2 - 1:0] dataout;
    input clk; 




single_port_ram new_ram(
  .clk (clk),
  .we(we),
  .data(datain),
  .out(dataout),
  .addr(addr)
  );
  
  
endmodule
module depth_split (we, addr, datain, dataout, clk);


    input we; 
    input[11 - 1:0] addr; 
    input[2 - 1:0] datain; 
    output[2 - 1:0] dataout; 
    wire[2 - 1:0] dataout;
    input clk; 




single_port_ram new_ram(
  .clk (clk),
  .we(we),
  .data(datain),
  .out(dataout),
  .addr(addr)
  );
  
  
endmodule