data/full_repos/permissive/423006272/verilog/dv/io_ports/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v
1: b"%Error: data/full_repos/permissive/423006272/verilog/dv/io_ports/pdk/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v:34: Can't resolve module reference: 'sky130_fd_io__top_power_hvc_wpadv2'\n  sky130_fd_io__top_power_hvc_wpadv2 sky130_fd_io__top_power_hvc_base ( \n                                     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module sky130_ef_io__corner_pad (AMUXBUS_A, AMUXBUS_B, 
	VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD,
	VSSIO, VSSD, VSSIO_Q
);
  inout AMUXBUS_A;
  inout AMUXBUS_B;

  inout VDDIO;	
  inout VDDIO_Q;	
  inout VDDA;
  inout VCCD;
  inout VSWITCH;
  inout VCCHIB;
  inout VSSA;
  inout VSSD;
  inout VSSIO_Q;
  inout VSSIO;

endmodule
module sky130_ef_io__corner_pad (AMUXBUS_A, AMUXBUS_B, 
	VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD,
	VSSIO, VSSD, VSSIO_Q
);

  inout AMUXBUS_A;
  inout AMUXBUS_B;

  inout VDDIO;	
  inout VDDIO_Q;	
  inout VDDA;
  inout VCCD;
  inout VSWITCH;
  inout VCCHIB;
  inout VSSA;
  inout VSSD;
  inout VSSIO_Q;
  inout VSSIO;

endmodule