data/full_repos/permissive/462122681/select_encode.v
1: b"%Error: data/full_repos/permissive/462122681/select_encode.v:32: Cannot find file containing module: 'decoder_4_16'\n decoder_4_16 decoder(\n ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/462122681,data/full_repos/permissive/462122681/decoder_4_16\n             data/full_repos/permissive/462122681,data/full_repos/permissive/462122681/decoder_4_16.v\n             data/full_repos/permissive/462122681,data/full_repos/permissive/462122681/decoder_4_16.sv\n             decoder_4_16\n             decoder_4_16.v\n             decoder_4_16.sv\n             obj_dir/decoder_4_16\n             obj_dir/decoder_4_16.v\n             obj_dir/decoder_4_16.sv\n%Error: Exiting due to 1 error(s)\n"
module select_encode(
	input wire [31:0] IR,
	input wire Gra,
	input wire Grb,
	input wire Grc,
	input wire Rin,
	input wire Rout,
	input wire BAout,
	
	output [15:0] Renable,
	output [15:0] R_out,
	output [31:0] Csign, 
	output [4:0] opcode
);





	wire [3:0] decoder_in;
	wire [15:0] decoder_out;
	
	




	
	assign decoder_in = (IR[26:23] & {4{Gra}}) |  (IR[22:19] & {4{Grb}})	| (IR[18:15] & {4{Grc}});


	decoder_4_16 decoder(
		.d_in (decoder_in),
		.d_out (decoder_out)
	);

	assign opcode = IR[31:27];
	
	assign Renable = {16{Rin}} & decoder_out;

	assign R_out = ({16{Rout}} | {16{BAout}}) & decoder_out;

	assign Csign = {{13{IR[18]}}, IR[18:0]};

endmodule
module select_encode(
	input wire [31:0] IR,
	input wire Gra,
	input wire Grb,
	input wire Grc,
	input wire Rin,
	input wire Rout,
	input wire BAout,
	
	output [15:0] Renable,
	output [15:0] R_out,
	output [31:0] Csign, 
	output [4:0] opcode
);






	wire [3:0] decoder_in;
	wire [15:0] decoder_out;
	
	




	
	assign decoder_in = (IR[26:23] & {4{Gra}}) |  (IR[22:19] & {4{Grb}})	| (IR[18:15] & {4{Grc}});


	decoder_4_16 decoder(
		.d_in (decoder_in),
		.d_out (decoder_out)
	);

	assign opcode = IR[31:27];
	
	assign Renable = {16{Rin}} & decoder_out;

	assign R_out = ({16{Rout}} | {16{BAout}}) & decoder_out;

	assign Csign = {{13{IR[18]}}, IR[18:0]};

endmodule