data/full_repos/permissive/446312960/Verilog_Simulation/04_demux/tb_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/04_demux/tb_testbench.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/446312960/Verilog_Simulation/04_demux/tb_testbench.v:22: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("tb_test_out.vcd");    \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/446312960/Verilog_Simulation/04_demux/tb_testbench.v:23: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,dut);                \n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_testbench; 

wire F,A,B,C,D;
wire [1:0] sel;

demux_test tester (.t1(F), .t2(sel), .p1(A), .p2(B), .p3(C), .p4(D));


demux         dut   (.F(F), .sel(sel), .A(A), .B(B), .C(C), .D(D));

always @( F, sel, A,B,C,D )
begin
    #1;
    $display("%b %2b %b %b %b %b",F,sel,A,B,C,D);
end

initial begin
    $dumpfile("tb_test_out.vcd");
    $dumpvars(0,dut);
end

endmodule
module tb_testbench;
 

wire F,A,B,C,D;
wire [1:0] sel;

demux_test tester (.t1(F), .t2(sel), .p1(A), .p2(B), .p3(C), .p4(D));


demux         dut   (.F(F), .sel(sel), .A(A), .B(B), .C(C), .D(D));

always @( F, sel, A,B,C,D )
begin
    #1;
    $display("%b %2b %b %b %b %b",F,sel,A,B,C,D);
end

initial begin
    $dumpfile("tb_test_out.vcd");
    $dumpvars(0,dut);
end

endmodule