data/full_repos/permissive/509809169/Circuits/Building Larger Circuits/4-bit shift-register and down counter.v
1: b'%Error: Cannot find file containing module: Larger\n        ... Looked in:\n             data/full_repos/permissive/509809169/Circuits/Building/Larger\n             data/full_repos/permissive/509809169/Circuits/Building/Larger.v\n             data/full_repos/permissive/509809169/Circuits/Building/Larger.sv\n             Larger\n             Larger.v\n             Larger.sv\n             obj_dir/Larger\n             obj_dir/Larger.v\n             obj_dir/Larger.sv\n%Error: Cannot find file containing module: Circuits,data/full_repos/permissive/509809169\n%Error: Cannot find file containing module: data/full_repos/permissive/509809169/Circuits/Building\n%Error: Cannot find file containing module: Circuits/4-bit\n%Error: Cannot find file containing module: shift-register\n%Error: Cannot find file containing module: and\n%Error: Cannot find file containing module: down\n%Error: Cannot find file containing module: counter.v\n%Error: Exiting due to 8 error(s)\n'
module top_module (
    input clk,
    input shift_ena,
    input count_ena,
    input data,
    output [3:0] q);

    wire [3:0]w;
    assign w=q-1;
    always @(posedge clk) begin
        if(shift_ena)begin
            q[3]<=q[2];
            q[2]<=q[1];
            q[1]<=q[0];
            q[0]<=data;
        end
        else if(count_ena) begin
            q<=w;
        end
    end
endmodule
module top_module (
    input clk,
    input shift_ena,
    input count_ena,
    input data,
    output [3:0] q);


    wire [3:0]w;
    assign w=q-1;
    always @(posedge clk) begin
        if(shift_ena)begin
            q[3]<=q[2];
            q[2]<=q[1];
            q[1]<=q[0];
            q[0]<=data;
        end
        else if(count_ena) begin
            q<=w;
        end
    end
endmodule