data/full_repos/permissive/524445468/ram_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/524445468/ram_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/524445468/ram_tb.v:21: syntax error, unexpected \'@\'\nrepeat(10) @(posedge clk);\n           ^\n%Error: data/full_repos/permissive/524445468/ram_tb.v:27: syntax error, unexpected \'@\'\n@(posedge clk);\n^\n%Error: data/full_repos/permissive/524445468/ram_tb.v:32: Unsupported or unknown PLI call: $urandom\naddr   = $urandom;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/524445468/ram_tb.v:33: Unsupported or unknown PLI call: $urandom\ndatain = $urandom();\n         ^~~~~~~~\n%Error: data/full_repos/permissive/524445468/ram_tb.v:34: syntax error, unexpected \'@\'\n@(posedge clk);\n^\n%Error: data/full_repos/permissive/524445468/ram_tb.v:43: syntax error, unexpected \'@\'\n@(posedge clk);\n^\n%Error: data/full_repos/permissive/524445468/ram_tb.v:48: Unsupported or unknown PLI call: $urandom\naddr   = $urandom;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/524445468/ram_tb.v:50: syntax error, unexpected \'@\'\nrepeat(2) @(posedge clk);\n          ^\n%Error: Exiting due to 8 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;
 
reg clk =0, rst = 0, we = 0;
reg [3:0] addr = 0;
reg [7:0] datain = 0;
wire [7:0] dataout;
integer i = 0;
 
ram dut (clk, rst, we, addr, datain, dataout);
 
always #5 clk = ~clk;
 
task reset;
begin
rst = 1;
we = 0;
addr = 0;
datain = 0;
repeat(10) @(posedge clk);
end
endtask
 
task write();
begin
@(posedge clk);
rst = 1'b0;
we = 1'b1;
for(i = 0; i < 20; i = i+1)
begin
addr   = $urandom;
datain = $urandom();
@(posedge clk);
end
end
endtask
 
 
 
task read();
begin
@(posedge clk);
rst = 1'b0;
we = 1'b0;
for(i = 0; i < 20; i = i+1)
begin
addr   = $urandom;
datain = 0;
repeat(2) @(posedge clk);
end
end
endtask
 
 
 
 
initial begin
reset();
write();
read();
end
 
 
 
 
 
endmodule
module tb;

 
reg clk =0, rst = 0, we = 0;
reg [3:0] addr = 0;
reg [7:0] datain = 0;
wire [7:0] dataout;
integer i = 0;
 
ram dut (clk, rst, we, addr, datain, dataout);
 
always #5 clk = ~clk;
 
task reset;
begin
rst = 1;
we = 0;
addr = 0;
datain = 0;
repeat(10) @(posedge clk);
end
endtask
 
task write();
begin
@(posedge clk);
rst = 1'b0;
we = 1'b1;
for(i = 0; i < 20; i = i+1)
begin
addr   = $urandom;
datain = $urandom();
@(posedge clk);
end
end
endtask
 
 
 
task read();
begin
@(posedge clk);
rst = 1'b0;
we = 1'b0;
for(i = 0; i < 20; i = i+1)
begin
addr   = $urandom;
datain = 0;
repeat(2) @(posedge clk);
end
end
endtask
 
 
 
 
initial begin
reset();
write();
read();
end
 
 
 
 
 
endmodule