data/full_repos/permissive/492462267/id_ex.v
1: b'%Error: data/full_repos/permissive/492462267/id_ex.v:1: Cannot find include file: define.vh\n`include "define.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh.v\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh.sv\n             define.vh\n             define.vh.v\n             define.vh.sv\n             obj_dir/define.vh\n             obj_dir/define.vh.v\n             obj_dir/define.vh.sv\n%Error: data/full_repos/permissive/492462267/id_ex.v:15: Define or directive not defined: \'`AluOpBus\'\n   input  wire[`AluOpBus]      id_aluop,    \n               ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id_ex.v:15: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   input  wire[`AluOpBus]      id_aluop,    \n                        ^\n%Error: data/full_repos/permissive/492462267/id_ex.v:16: Define or directive not defined: \'`AluSelBus\'\n   input  wire[`AluSelBus]     id_alusel,   \n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id_ex.v:17: Define or directive not defined: \'`RegDataBus\'\n   input  wire[`RegDataBus]    id_data1,    \n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id_ex.v:18: Define or directive not defined: \'`RegDataBus\'\n   input  wire[`RegDataBus]    id_data2,    \n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id_ex.v:19: Define or directive not defined: \'`RegAddrBus\'\n   input  wire[`RegAddrBus]    id_waddr,    \n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id_ex.v:21: syntax error, unexpected input, expecting IDENTIFIER or do or final\n   input  wire[5:0]            stall,       \n   ^~~~~\n%Error: data/full_repos/permissive/492462267/id_ex.v:24: syntax error, unexpected output, expecting IDENTIFIER or do or final\n   output  reg[`AluOpBus]      ex_aluop,    \n   ^~~~~~\n%Error: data/full_repos/permissive/492462267/id_ex.v:24: Define or directive not defined: \'`AluOpBus\'\n   output  reg[`AluOpBus]      ex_aluop,    \n               ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id_ex.v:25: Define or directive not defined: \'`AluSelBus\'\n   output  reg[`AluSelBus]     ex_alusel,   \n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id_ex.v:26: Define or directive not defined: \'`RegDataBus\'\n   output  reg[`RegDataBus]    ex_data1,    \n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id_ex.v:27: Define or directive not defined: \'`RegDataBus\'\n   output  reg[`RegDataBus]    ex_data2,    \n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id_ex.v:28: Define or directive not defined: \'`RegAddrBus\'\n   output  reg[`RegAddrBus]    ex_waddr,    \n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id_ex.v:35: Define or directive not defined: \'`EXE_NOP_OP\'\n        ex_aluop  <= `EXE_NOP_OP;\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id_ex.v:36: Define or directive not defined: \'`EXE_RES_NOP\'\n        ex_alusel <= `EXE_RES_NOP;\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id_ex.v:37: Define or directive not defined: \'`ZeroWord\'\n        ex_data1  <= `ZeroWord;\n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id_ex.v:38: Define or directive not defined: \'`ZeroWord\'\n        ex_data2  <= `ZeroWord;\n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id_ex.v:39: Define or directive not defined: \'`RegAddr_0\'\n        ex_waddr  <= `RegAddr_0;\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id_ex.v:40: Define or directive not defined: \'`Disable\'\n        ex_we     <= `Disable;\n                     ^~~~~~~~\n%Error: data/full_repos/permissive/492462267/id_ex.v:46: Define or directive not defined: \'`EXE_NOP_OP\'\n        ex_aluop  <= `EXE_NOP_OP;\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id_ex.v:47: Define or directive not defined: \'`EXE_RES_NOP\'\n        ex_alusel <= `EXE_RES_NOP;\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id_ex.v:48: Define or directive not defined: \'`ZeroWord\'\n        ex_data1  <= `ZeroWord;\n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id_ex.v:49: Define or directive not defined: \'`ZeroWord\'\n        ex_data2  <= `ZeroWord;\n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id_ex.v:50: Define or directive not defined: \'`RegAddr_0\'\n        ex_waddr  <= `RegAddr_0;\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id_ex.v:51: Define or directive not defined: \'`Disable\'\n        ex_we     <= `Disable;\n                     ^~~~~~~~\n%Error: Exiting due to 26 error(s)\n'
module id_ex (
   input  wire     clk,
   input  wire     rst,


   input  wire[`AluOpBus]      id_aluop,
   input  wire[`AluSelBus]     id_alusel,
   input  wire[`RegDataBus]    id_data1,
   input  wire[`RegDataBus]    id_data2,
   input  wire[`RegAddrBus]    id_waddr,
   input  wire                 id_we,
   input  wire[5:0]            stall,


   output  reg[`AluOpBus]      ex_aluop,
   output  reg[`AluSelBus]     ex_alusel,
   output  reg[`RegDataBus]    ex_data1,
   output  reg[`RegDataBus]    ex_data2,
   output  reg[`RegAddrBus]    ex_waddr,
   output  reg                 ex_we
 );


 always @(posedge clk ) begin
      if(rst) begin
        ex_aluop  <= `EXE_NOP_OP;
        ex_alusel <= `EXE_RES_NOP;
        ex_data1  <= `ZeroWord;
        ex_data2  <= `ZeroWord;
        ex_waddr  <= `RegAddr_0;
        ex_we     <= `Disable;
      end 

      else if(stall[2] && !stall[3])begin
        ex_aluop  <= `EXE_NOP_OP;
        ex_alusel <= `EXE_RES_NOP;
        ex_data1  <= `ZeroWord;
        ex_data2  <= `ZeroWord;
        ex_waddr  <= `RegAddr_0;
        ex_we     <= `Disable;
      end

      else if(!stall[2]) begin
        ex_aluop  <= id_aluop;
        ex_alusel <= id_alusel;
        ex_data1  <= id_data1;
        ex_data2  <= id_data2;
        ex_waddr  <= id_waddr;
        ex_we     <= id_we;
      end 
      
      else begin
        ex_aluop  <= ex_aluop;
        ex_alusel <= ex_alusel;
        ex_data1  <= ex_data1;
        ex_data2  <= ex_data2;
        ex_waddr  <= ex_waddr;
        ex_we     <= ex_we;
      end
 end
 
 endmodule
module id_ex (
   input  wire     clk,
   input  wire     rst,


   input  wire[`AluOpBus]      id_aluop,
   input  wire[`AluSelBus]     id_alusel,
   input  wire[`RegDataBus]    id_data1,
   input  wire[`RegDataBus]    id_data2,
   input  wire[`RegAddrBus]    id_waddr,
   input  wire                 id_we,
   input  wire[5:0]            stall,


   output  reg[`AluOpBus]      ex_aluop,
   output  reg[`AluSelBus]     ex_alusel,
   output  reg[`RegDataBus]    ex_data1,
   output  reg[`RegDataBus]    ex_data2,
   output  reg[`RegAddrBus]    ex_waddr,
   output  reg                 ex_we
 );



 always @(posedge clk ) begin
      if(rst) begin
        ex_aluop  <= `EXE_NOP_OP;
        ex_alusel <= `EXE_RES_NOP;
        ex_data1  <= `ZeroWord;
        ex_data2  <= `ZeroWord;
        ex_waddr  <= `RegAddr_0;
        ex_we     <= `Disable;
      end 

      else if(stall[2] && !stall[3])begin
        ex_aluop  <= `EXE_NOP_OP;
        ex_alusel <= `EXE_RES_NOP;
        ex_data1  <= `ZeroWord;
        ex_data2  <= `ZeroWord;
        ex_waddr  <= `RegAddr_0;
        ex_we     <= `Disable;
      end

      else if(!stall[2]) begin
        ex_aluop  <= id_aluop;
        ex_alusel <= id_alusel;
        ex_data1  <= id_data1;
        ex_data2  <= id_data2;
        ex_waddr  <= id_waddr;
        ex_we     <= id_we;
      end 
      
      else begin
        ex_aluop  <= ex_aluop;
        ex_alusel <= ex_alusel;
        ex_data1  <= ex_data1;
        ex_data2  <= ex_data2;
        ex_waddr  <= ex_waddr;
        ex_we     <= ex_we;
      end
 end
 
 endmodule