data/full_repos/permissive/505451992/rate_switch.v
data/verilator_xmls/b6932833-e8e0-401d-a2fb-b399a782e20f.xml
module Rate_switch(
input reset,
input clk,
input[2:0] R,
output [23:0] Rate_1
    );
    
 reg [23:0] Rate;
    
    always@(*)begin
        case(R)
        3'b000: Rate = 24'd4;
        3'b001: Rate = 24'd9;
        3'b010: Rate = 24'd24;
        3'b011: Rate = 24'd49;
        3'b100: Rate = 24'd99;
        3'b101: Rate = 24'd249;
        3'b110: Rate = 24'd499;
        3'b111: Rate = 24'd999;
        default: Rate = 24'd4;
        
        endcase
    
    end
   
   assign Rate_1 = Rate; 
    
endmodule
module Rate_switch(
input reset,
input clk,
input[2:0] R,
output [23:0] Rate_1
    );

    
 reg [23:0] Rate;
    
    always@(*)begin
        case(R)
        3'b000: Rate = 24'd4;
        3'b001: Rate = 24'd9;
        3'b010: Rate = 24'd24;
        3'b011: Rate = 24'd49;
        3'b100: Rate = 24'd99;
        3'b101: Rate = 24'd249;
        3'b110: Rate = 24'd499;
        3'b111: Rate = 24'd999;
        default: Rate = 24'd4;
        
        endcase
    
    end
   
   assign Rate_1 = Rate; 
    
endmodule