data/full_repos/permissive/422139337/src/tmds_encoder.v
1: b'%Warning-WIDTH: data/full_repos/permissive/422139337/src/tmds_encoder.v:38: Operator ADD expects 4 bits on the RHS, but RHS\'s LOGNOT generates 1 bits.\n                                                                          : ... In instance tmds_encoder\n            N0 = N0 + !d[i];\n                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/422139337/src/tmds_encoder.v:48: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                          : ... In instance tmds_encoder\n            N1 = N1 + d[i];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/422139337/src/tmds_encoder.v:98: Operator SUB expects 8 bits on the LHS, but LHS\'s FUNCREF \'N0\' generates 4 bits.\n                                                                          : ... In instance tmds_encoder\n                cnt = cnt_prev + (N0(q_m[7:0]) - N1(q_m[7:0]));\n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/422139337/src/tmds_encoder.v:98: Operator SUB expects 8 bits on the RHS, but RHS\'s FUNCREF \'N1\' generates 4 bits.\n                                                                          : ... In instance tmds_encoder\n                cnt = cnt_prev + (N0(q_m[7:0]) - N1(q_m[7:0]));\n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/422139337/src/tmds_encoder.v:100: Operator SUB expects 8 bits on the LHS, but LHS\'s FUNCREF \'N1\' generates 4 bits.\n                                                                           : ... In instance tmds_encoder\n                cnt = cnt_prev + (N1(q_m[7:0]) - N0(q_m[7:0]));\n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/422139337/src/tmds_encoder.v:100: Operator SUB expects 8 bits on the RHS, but RHS\'s FUNCREF \'N0\' generates 4 bits.\n                                                                           : ... In instance tmds_encoder\n                cnt = cnt_prev + (N1(q_m[7:0]) - N0(q_m[7:0]));\n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/422139337/src/tmds_encoder.v:110: Operator SUB expects 32 or 8 bits on the LHS, but LHS\'s FUNCREF \'N0\' generates 4 bits.\n                                                                           : ... In instance tmds_encoder\n                cnt = cnt_prev + 2*q_m[8] + (N0(q_m[7:0]) - N1(q_m[7:0]));\n                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/422139337/src/tmds_encoder.v:110: Operator SUB expects 32 or 8 bits on the RHS, but RHS\'s FUNCREF \'N1\' generates 4 bits.\n                                                                           : ... In instance tmds_encoder\n                cnt = cnt_prev + 2*q_m[8] + (N0(q_m[7:0]) - N1(q_m[7:0]));\n                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/422139337/src/tmds_encoder.v:115: Operator NOT expects 32 or 8 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                           : ... In instance tmds_encoder\n                cnt = cnt_prev + 2*(~q_m[8]) + (N1(q_m[7:0]) - N0(q_m[7:0]));\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/422139337/src/tmds_encoder.v:115: Operator SUB expects 32 or 8 bits on the LHS, but LHS\'s FUNCREF \'N1\' generates 4 bits.\n                                                                           : ... In instance tmds_encoder\n                cnt = cnt_prev + 2*(~q_m[8]) + (N1(q_m[7:0]) - N0(q_m[7:0]));\n                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/422139337/src/tmds_encoder.v:115: Operator SUB expects 32 or 8 bits on the RHS, but RHS\'s FUNCREF \'N0\' generates 4 bits.\n                                                                           : ... In instance tmds_encoder\n                cnt = cnt_prev + 2*(~q_m[8]) + (N1(q_m[7:0]) - N0(q_m[7:0]));\n                                                             ^\n%Error: Exiting due to 11 warning(s)\n'
module tmds_encoder(
           input clk,
           input DE, 
           input [7:0]D,
           input C1,
           input C0,
           output reg[9:0] q_out = 0
       );
parameter LEGACY_DVI_CONTROL_LUT = 0;

function [3:0] N0;
    input [7:0] d;
    integer i;
    begin
        N0 = 0;
        for (i = 0; i < 8; i=i+1)
            N0 = N0 + !d[i];
    end
endfunction

function [3:0] N1;
    input [7:0] d;
    integer i;
    begin
        N1 = 0;
        for (i = 0; i < 8; i=i+1)
            N1 = N1 + d[i];
    end
endfunction

reg signed [7:0] cnt_prev = 0;
reg signed [7:0] cnt = 0;

reg [8:0] q_m;

always @(*) begin

    if ( (N1(D) > 4) | (N1(D) == 4) & (D[0] == 0) ) begin

        q_m[0] =           D[0];
        q_m[1] = q_m[0] ~^ D[1];
        q_m[2] = q_m[1] ~^ D[2];
        q_m[3] = q_m[2] ~^ D[3];
        q_m[4] = q_m[3] ~^ D[4];
        q_m[5] = q_m[4] ~^ D[5];
        q_m[6] = q_m[5] ~^ D[6];
        q_m[7] = q_m[6] ~^ D[7];
        q_m[8] = 1'b0;

    end else begin

        q_m[0] =          D[0];
        q_m[1] = q_m[0] ^ D[1];
        q_m[2] = q_m[1] ^ D[2];
        q_m[3] = q_m[2] ^ D[3];
        q_m[4] = q_m[3] ^ D[4];
        q_m[5] = q_m[4] ^ D[5];
        q_m[6] = q_m[5] ^ D[6];
        q_m[7] = q_m[6] ^ D[7];
        q_m[8] = 1'b1;

    end

end

always @(posedge clk) begin

    if (DE) begin

        if ((cnt_prev == 0) | (N1(q_m[7:0]) == N0(q_m[7:0]))) begin

            q_out[9]   <= ~q_m[8];
            q_out[8]   <=  q_m[8];
            q_out[7:0] <= q_m[8] ? q_m[7:0] : ~q_m[7:0];

            if (q_m[8] == 0) begin
                cnt = cnt_prev + (N0(q_m[7:0]) - N1(q_m[7:0]));
            end else begin
                cnt = cnt_prev + (N1(q_m[7:0]) - N0(q_m[7:0]));
            end

        end else begin

            if ( (cnt_prev > 0 & (N1(q_m[7:0]) > N0(q_m[7:0]))) |
                    (cnt_prev < 0 & (N0(q_m[7:0]) > N1(q_m[7:0]))) ) begin
                q_out[9] <= 1;
                q_out[8] <= q_m[8];
                q_out[7:0] <= ~q_m[7:0];
                cnt = cnt_prev + 2*q_m[8] + (N0(q_m[7:0]) - N1(q_m[7:0]));
            end else begin
                q_out[9] <= 0;
                q_out[8] <= q_m[8];
                q_out[7:0] <= q_m[7:0];
                cnt = cnt_prev + 2*(~q_m[8]) + (N1(q_m[7:0]) - N0(q_m[7:0]));
            end

        end

    end else begin

        cnt = 0;

        case ({C1, C0})
`ifdef LEGACY_DVI_CONTROL_LUT

            2'b00: q_out <= 10'b00101_01011;
            2'b01: q_out <= 10'b11010_10100;
            2'b10: q_out <= 10'b00101_01010;
            2'b11: q_out <= 10'b11010_10101;
`else

            2'b00: q_out <= 10'b1101010100;
            2'b01: q_out <= 10'b0010101011;
            2'b10: q_out <= 10'b0101010100;
            2'b11: q_out <= 10'b1010101011;
`endif
        endcase

    end

    cnt_prev <= cnt;

end

endmodule
module tmds_encoder(
           input clk,
           input DE, 
           input [7:0]D,
           input C1,
           input C0,
           output reg[9:0] q_out = 0
       );

parameter LEGACY_DVI_CONTROL_LUT = 0;

function [3:0] N0;
    input [7:0] d;
    integer i;
    begin
        N0 = 0;
        for (i = 0; i < 8; i=i+1)
            N0 = N0 + !d[i];
    end
endfunction

function [3:0] N1;
    input [7:0] d;
    integer i;
    begin
        N1 = 0;
        for (i = 0; i < 8; i=i+1)
            N1 = N1 + d[i];
    end
endfunction

reg signed [7:0] cnt_prev = 0;
reg signed [7:0] cnt = 0;

reg [8:0] q_m;

always @(*) begin

    if ( (N1(D) > 4) | (N1(D) == 4) & (D[0] == 0) ) begin

        q_m[0] =           D[0];
        q_m[1] = q_m[0] ~^ D[1];
        q_m[2] = q_m[1] ~^ D[2];
        q_m[3] = q_m[2] ~^ D[3];
        q_m[4] = q_m[3] ~^ D[4];
        q_m[5] = q_m[4] ~^ D[5];
        q_m[6] = q_m[5] ~^ D[6];
        q_m[7] = q_m[6] ~^ D[7];
        q_m[8] = 1'b0;

    end else begin

        q_m[0] =          D[0];
        q_m[1] = q_m[0] ^ D[1];
        q_m[2] = q_m[1] ^ D[2];
        q_m[3] = q_m[2] ^ D[3];
        q_m[4] = q_m[3] ^ D[4];
        q_m[5] = q_m[4] ^ D[5];
        q_m[6] = q_m[5] ^ D[6];
        q_m[7] = q_m[6] ^ D[7];
        q_m[8] = 1'b1;

    end

end

always @(posedge clk) begin

    if (DE) begin

        if ((cnt_prev == 0) | (N1(q_m[7:0]) == N0(q_m[7:0]))) begin

            q_out[9]   <= ~q_m[8];
            q_out[8]   <=  q_m[8];
            q_out[7:0] <= q_m[8] ? q_m[7:0] : ~q_m[7:0];

            if (q_m[8] == 0) begin
                cnt = cnt_prev + (N0(q_m[7:0]) - N1(q_m[7:0]));
            end else begin
                cnt = cnt_prev + (N1(q_m[7:0]) - N0(q_m[7:0]));
            end

        end else begin

            if ( (cnt_prev > 0 & (N1(q_m[7:0]) > N0(q_m[7:0]))) |
                    (cnt_prev < 0 & (N0(q_m[7:0]) > N1(q_m[7:0]))) ) begin
                q_out[9] <= 1;
                q_out[8] <= q_m[8];
                q_out[7:0] <= ~q_m[7:0];
                cnt = cnt_prev + 2*q_m[8] + (N0(q_m[7:0]) - N1(q_m[7:0]));
            end else begin
                q_out[9] <= 0;
                q_out[8] <= q_m[8];
                q_out[7:0] <= q_m[7:0];
                cnt = cnt_prev + 2*(~q_m[8]) + (N1(q_m[7:0]) - N0(q_m[7:0]));
            end

        end

    end else begin

        cnt = 0;

        case ({C1, C0})
`ifdef LEGACY_DVI_CONTROL_LUT

            2'b00: q_out <= 10'b00101_01011;
            2'b01: q_out <= 10'b11010_10100;
            2'b10: q_out <= 10'b00101_01010;
            2'b11: q_out <= 10'b11010_10101;
`else

            2'b00: q_out <= 10'b1101010100;
            2'b01: q_out <= 10'b0010101011;
            2'b10: q_out <= 10'b0101010100;
            2'b11: q_out <= 10'b1010101011;
`endif
        endcase

    end

    cnt_prev <= cnt;

end

endmodule