data/full_repos/permissive/451577625/system/clock_divider.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/451577625/system/clock_divider.v:39: Unsupported: Ignoring delay on this delayed statement.\n  forever #10 in = ~in;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-INFINITELOOP: data/full_repos/permissive/451577625/system/clock_divider.v:39: Infinite loop (condition always true)\n                                                                                     : ... In instance clock_divider_tb\n  forever #10 in = ~in;\n  ^~~~~~~\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module clock_divider(input in_clock, output reg out_clock);

	initial begin
		out_clock = 0;
	end

	reg [27:0] counter= 28'd0;
	
	parameter DIVISOR = 28'd3;
	
	always @(posedge in_clock) begin
		counter <= counter + 28'd1;
		if(counter == (DIVISOR - 1)) begin
			counter <= 28'd0;
		end
		
		out_clock <= (counter<DIVISOR/2)?1'b1:1'b0;
	end
endmodule
module clock_divider(input in_clock, output reg out_clock);


	initial begin
		out_clock = 0;
	end

	reg [27:0] counter= 28'd0;
	
	parameter DIVISOR = 28'd3;
	
	always @(posedge in_clock) begin
		counter <= counter + 28'd1;
		if(counter == (DIVISOR - 1)) begin
			counter <= 28'd0;
		end
		
		out_clock <= (counter<DIVISOR/2)?1'b1:1'b0;
	end
endmodule