data/full_repos/permissive/4847981/mem.v
data/verilator_xmls/91674d05-f4ce-42ca-9318-6c21f34c6b90.xml
module mem(
    input [3:0] ADDR,
    output [7:0] DATA
    );

	reg [7:0] inst [0:15];
	
	initial begin
		$readmemb("prog.txt", inst,  0,  15);
	end

	assign DATA = inst[ADDR];

endmodule
module mem(
    input [3:0] ADDR,
    output [7:0] DATA
    );


	reg [7:0] inst [0:15];
	
	initial begin
		$readmemb("prog.txt", inst,  0,  15);
	end

	assign DATA = inst[ADDR];

endmodule