data/full_repos/permissive/455223995/src/slzw_lib.v
1: b'%Error: data/full_repos/permissive/455223995/src/slzw_lib.v:50: syntax error, unexpected byte, expecting IDENTIFIER or \'[\' or do or final\n  input   [7:0] byte,\n                ^~~~\n%Error: data/full_repos/permissive/455223995/src/slzw_lib.v:56: syntax error, unexpected \'[\', expecting "\'{"\nwire [13:0] num1 = {1\'b0, byte[4:0], byte[7:0]};\n                              ^\n%Error: data/full_repos/permissive/455223995/src/slzw_lib.v:62: syntax error, unexpected assign\nassign haddr      = num1 + num2;\n^~~~~~\n%Error: Exiting due to 3 error(s)\n'
module slzw_dictmem
#(parameter
   MEMSIZE                     = 10240,
   WIDTH                       = 8
)
(
  input                        clk,

  input           [13:0]       waddr,
  input                        write,
  input      [WIDTH-1:0]       wdata,

  input           [13:0]       raddr,
  output reg [WIDTH-1:0]       rdata

);

reg [WIDTH-1:0] mem[0:MEMSIZE];

always @ (posedge clk)
begin
  rdata                        <= mem[raddr];

  if (write)
  begin
    mem[waddr]                 <= wdata;
  end
end

endmodule
module slzw_dictmem
#(parameter
   MEMSIZE                     = 10240,
   WIDTH                       = 8
)
(
  input                        clk,

  input           [13:0]       waddr,
  input                        write,
  input      [WIDTH-1:0]       wdata,

  input           [13:0]       raddr,
  output reg [WIDTH-1:0]       rdata

);


reg [WIDTH-1:0] mem[0:MEMSIZE];

always @ (posedge clk)
begin
  rdata                        <= mem[raddr];

  if (write)
  begin
    mem[waddr]                 <= wdata;
  end
end

endmodule