data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/run/tb_rsinv.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/run/tb_rsinv.v:12: Unsupported: Ignoring delay on this delayed statement.\nalways #PERIOD clk=~clk;  \n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/run/tb_rsinv.v:59: Unsupported: Ignoring delay on this delayed statement.\n#10 rst = 1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/run/tb_rsinv.v:60: Unsupported: Ignoring delay on this delayed statement.\n#20 rst = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/run/tb_rsinv.v:62: Unsupported: Ignoring delay on this delayed statement.\n#20 acen_i = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/run/tb_rsinv.v:63: Unsupported: Ignoring delay on this delayed statement.\n#100.1 adivld = 1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/run/tb_rsinv.v:65: Unsupported: Ignoring delay on this delayed statement.\n#20 adivld = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/run/tb_rsinv.v:67: Unsupported: Ignoring delay on this delayed statement.\n#20 acen_s = 1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/run/tb_rsinv.v:68: Unsupported: Ignoring delay on this delayed statement.\n#20 acen_s = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/run/tb_rsinv.v:69: Unsupported: Ignoring delay on this delayed statement.\n#100.1 adivld = 1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/run/tb_rsinv.v:71: Unsupported: Ignoring delay on this delayed statement.\n#20 adivld = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/run/tb_rsinv.v:72: Unsupported: Ignoring delay on this delayed statement.\n#100.1 adivld = 1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/run/tb_rsinv.v:74: Unsupported: Ignoring delay on this delayed statement.\n#20 adivld = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/run/tb_rsinv.v:75: Unsupported: Ignoring delay on this delayed statement.\n#100.1 adivld = 1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/run/tb_rsinv.v:77: Unsupported: Ignoring delay on this delayed statement.\n#20 adivld = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/run/tb_rsinv.v:78: Unsupported: Ignoring delay on this delayed statement.\n#20 acen_r = 1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/run/tb_rsinv.v:79: Unsupported: Ignoring delay on this delayed statement.\n#20 acen_r = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/run/tb_rsinv.v:80: Unsupported: Ignoring delay on this delayed statement.\n#100.1 adivld = 1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/run/tb_rsinv.v:82: Unsupported: Ignoring delay on this delayed statement.\n#20 adivld = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/run/tb_rsinv.v:83: Unsupported: Ignoring delay on this delayed statement.\n#10000;\n^\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/run/tb_rsinv.v:88: Unsupported or unknown PLI call: $shm_open\n$shm_open ("my_waves");\n^~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/run/tb_rsinv.v:89: Unsupported or unknown PLI call: $shm_probe\n$shm_probe (tb_rsinv,"AC");\n^~~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/run/tb_rsinv.v:90: Unsupported or unknown PLI call: $recordfile\n$recordfile("testsample.trn");\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/run/tb_rsinv.v:91: Unsupported or unknown PLI call: $recordvars\n$recordvars();\n^~~~~~~~~~~\n%Error: Exiting due to 4 error(s), 19 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_rsinv;

parameter WID = 256;
parameter AWID = 5;
parameter PERIOD = 10;

reg clk=0;
reg rst=0;

always #PERIOD clk=~clk;

wire [AWID-1:0] ramra;
wire [WID-1:0]  ramwd;
wire [AWID-1:0] ramwa;
wire            ramwe;

reg             acen_i;
reg             acen_r;
reg             acen_s;
wire            rsidone;

wire            aen;
wire [1:0]      aop;
reg [WID-1:0]   adi;
reg             adivld;

rsinv irsinv
    (
     .clk(clk),
     .rst(rst),

     .ramra(ramra),
     .ramwd(ramwd),
     .ramwa(ramwa),
     .ramwe(ramwe),
     

     .acen_i(acen_i),
     .acen_r(acen_r),
     .acen_s(acen_s),
     .rsidone(rsidone),

     .aen(aen),
     .aop(aop),
     .adi(adi),
     .adivld(adivld)
     );

initial begin
acen_i = 0;
acen_r = 0;
acen_s = 0;
adivld = 0;
adi = 0;
clk = 0;
rst = 0;
#10 rst = 1;
#20 rst = 0;
acen_i = 1;
#20 acen_i = 0;
#100.1 adivld = 1;
adi = 256'd3251231251234;
#20 adivld = 0;
adi = 256'd1;
#20 acen_s = 1;
#20 acen_s = 0;
#100.1 adivld = 1;
adi = 256'd3;
#20 adivld = 0;
#100.1 adivld = 1;
adi = 256'd4;
#20 adivld = 0;
#100.1 adivld = 1;
adi = 256'd6;
#20 adivld = 0;
#20 acen_r = 1;
#20 acen_r = 0;
#100.1 adivld = 1;
adi = 256'd7;
#20 adivld = 0;
#10000;
$finish;
end

initial begin
$shm_open ("my_waves");
$shm_probe (tb_rsinv,"AC");
$recordfile("testsample.trn");
$recordvars();
end

endmodule
module tb_rsinv;


parameter WID = 256;
parameter AWID = 5;
parameter PERIOD = 10;

reg clk=0;
reg rst=0;

always #PERIOD clk=~clk;

wire [AWID-1:0] ramra;
wire [WID-1:0]  ramwd;
wire [AWID-1:0] ramwa;
wire            ramwe;

reg             acen_i;
reg             acen_r;
reg             acen_s;
wire            rsidone;

wire            aen;
wire [1:0]      aop;
reg [WID-1:0]   adi;
reg             adivld;

rsinv irsinv
    (
     .clk(clk),
     .rst(rst),

     .ramra(ramra),
     .ramwd(ramwd),
     .ramwa(ramwa),
     .ramwe(ramwe),
     

     .acen_i(acen_i),
     .acen_r(acen_r),
     .acen_s(acen_s),
     .rsidone(rsidone),

     .aen(aen),
     .aop(aop),
     .adi(adi),
     .adivld(adivld)
     );

initial begin
acen_i = 0;
acen_r = 0;
acen_s = 0;
adivld = 0;
adi = 0;
clk = 0;
rst = 0;
#10 rst = 1;
#20 rst = 0;
acen_i = 1;
#20 acen_i = 0;
#100.1 adivld = 1;
adi = 256'd3251231251234;
#20 adivld = 0;
adi = 256'd1;
#20 acen_s = 1;
#20 acen_s = 0;
#100.1 adivld = 1;
adi = 256'd3;
#20 adivld = 0;
#100.1 adivld = 1;
adi = 256'd4;
#20 adivld = 0;
#100.1 adivld = 1;
adi = 256'd6;
#20 adivld = 0;
#20 acen_r = 1;
#20 acen_r = 0;
#100.1 adivld = 1;
adi = 256'd7;
#20 adivld = 0;
#10000;
$finish;
end

initial begin
$shm_open ("my_waves");
$shm_probe (tb_rsinv,"AC");
$recordfile("testsample.trn");
$recordvars();
end

endmodule