data/full_repos/permissive/463395574/testbench.v
1: b'%Error: data/full_repos/permissive/463395574/testbench.v:3: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v.v\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/463395574/testbench.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/463395574/testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #(50) clk = ~clk;\n        ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module testbench();
    reg clk, rstn;


    CPU cpu(clk, rstn);

    integer counter = 0;

    initial begin
        $readmemh("riscv32_sim1.dat", cpu.imem.RAM);
        clk = 1;
        rstn = 1;
        #5;
        rstn = 0;
    end

    always begin
        #(50) clk = ~clk;

        if (clk == 1'b1)
        begin
`ifdef DEBUG
            counter = counter + 1;
            $display("clock: %d", counter);
`ifdef PIPELINING
            $display("stage: IF      ID      EX      MEM      WB");
            $display("PC:\t %h %h %h %h %h", cpu.cpuCore.pc_IF, cpu.cpuCore.pc_ID, cpu.cpuCore.pc_EX, cpu.cpuCore.pc_MEM, cpu.cpuCore.pc_WB);
            $display("instr: %h %h", cpu.cpuCore.instr_IF, cpu.cpuCore.instr_ID);
`else
            $display("PC:\t\t%h", cpu.pc);
            $display("instr:\t%h", cpu.instr);
`endif
`endif
`ifdef PIPELINING
            if (cpu.cpuCore.pc_WB == 32'h00000078)
            begin
                $display("pc_WB:\t%h", cpu.cpuCore.pc_WB);

                $stop;
            end
`else
            if (cpu.pc == 32'h00000078)
            begin
                $display("pc:\t%h", cpu.pc);

                $stop;
            end
`endif
        end
    end
endmodule
module testbench();

    reg clk, rstn;


    CPU cpu(clk, rstn);

    integer counter = 0;

    initial begin
        $readmemh("riscv32_sim1.dat", cpu.imem.RAM);
        clk = 1;
        rstn = 1;
        #5;
        rstn = 0;
    end

    always begin
        #(50) clk = ~clk;

        if (clk == 1'b1)
        begin
`ifdef DEBUG
            counter = counter + 1;
            $display("clock: %d", counter);
`ifdef PIPELINING
            $display("stage: IF      ID      EX      MEM      WB");
            $display("PC:\t %h %h %h %h %h", cpu.cpuCore.pc_IF, cpu.cpuCore.pc_ID, cpu.cpuCore.pc_EX, cpu.cpuCore.pc_MEM, cpu.cpuCore.pc_WB);
            $display("instr: %h %h", cpu.cpuCore.instr_IF, cpu.cpuCore.instr_ID);
`else
            $display("PC:\t\t%h", cpu.pc);
            $display("instr:\t%h", cpu.instr);
`endif
`endif
`ifdef PIPELINING
            if (cpu.cpuCore.pc_WB == 32'h00000078)
            begin
                $display("pc_WB:\t%h", cpu.cpuCore.pc_WB);

                $stop;
            end
`else
            if (cpu.pc == 32'h00000078)
            begin
                $display("pc:\t%h", cpu.pc);

                $stop;
            end
`endif
        end
    end
endmodule