data/full_repos/permissive/414867793/Logic_Circuits/Four_Bit_C_Adder/Fo_B_ADD.v
1: b'%Error: data/full_repos/permissive/414867793/Logic_Circuits/Four_Bit_C_Adder/Fo_B_ADD.v:1: Cannot find include file: F_ADD.v\n`include "F_ADD.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/414867793/Logic_Circuits/Four_Bit_C_Adder,data/full_repos/permissive/414867793/F_ADD.v\n             data/full_repos/permissive/414867793/Logic_Circuits/Four_Bit_C_Adder,data/full_repos/permissive/414867793/F_ADD.v.v\n             data/full_repos/permissive/414867793/Logic_Circuits/Four_Bit_C_Adder,data/full_repos/permissive/414867793/F_ADD.v.sv\n             F_ADD.v\n             F_ADD.v.v\n             F_ADD.v.sv\n             obj_dir/F_ADD.v\n             obj_dir/F_ADD.v.v\n             obj_dir/F_ADD.v.sv\n%Error: Exiting due to 1 error(s)\n'
module Fo_B_ADD(A,B,C,S,D);
input [3:0] A,B;
input C;
output [3:0] S;
output D;
wire [3:1] Y;


F_ADD uut0(A[0],B[0],C,S[0],Y[1]);
F_ADD uut1(A[1],B[1],Y[1],S[1],Y[2]);
F_ADD uut2(A[2],B[2],Y[2],S[2],Y[3]);
F_ADD uut3(A[3],B[3],Y[3],S[3],D);

endmodule
module Fo_B_ADD(A,B,C,S,D);

input [3:0] A,B;
input C;
output [3:0] S;
output D;
wire [3:1] Y;


F_ADD uut0(A[0],B[0],C,S[0],Y[1]);
F_ADD uut1(A[1],B[1],Y[1],S[1],Y[2]);
F_ADD uut2(A[2],B[2],Y[2],S[2],Y[3]);
F_ADD uut3(A[3],B[3],Y[3],S[3],D);

endmodule