data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_hdl_models_up_counter_load.v
data/verilator_xmls/1b633c38-88ec-4321-a86c-5848dad17ed1.xml
module up_counter_load    (
out      ,
data     ,
load     ,
enable   ,
clk      ,
reset
);

output [7:0] out;

input [7:0] data;
input load, enable, clk, reset;

reg [7:0] out;

always @(posedge clk)
if (reset) begin
  out <= 8'b0 ;
end else if (load) begin
  out <= data;
end else if (enable) begin
  out <= out + 1;
end
    
endmodule
module up_counter_load    (
out      ,
data     ,
load     ,
enable   ,
clk      ,
reset
);


output [7:0] out;

input [7:0] data;
input load, enable, clk, reset;

reg [7:0] out;

always @(posedge clk)
if (reset) begin
  out <= 8'b0 ;
end else if (load) begin
  out <= data;
end else if (enable) begin
  out <= out + 1;
end
    
endmodule