data/full_repos/permissive/48330045/rtl/shift_register.v
data/verilator_xmls/7a1c945f-58e1-47ed-b1dd-3fb570a52a0f.xml
module shift_register
#(
  parameter DEPTH = 16,
  parameter WIDTH = 8
) (
  input  wire             rst_n,
  input  wire             clk,
  input  wire             en,
  input  wire [WIDTH-1:0] d,
  output wire [WIDTH-1:0] q
);

reg [WIDTH-1:0] core [0:DEPTH-1];
assign q = core[DEPTH-1];

always @(posedge clk or negedge rst_n) begin
  if (~rst_n)
    core[0] <= 0;
  else if(en)
    core[0] <= d;
end

genvar i;
generate
for (i = 1; i < DEPTH; i = i + 1) begin :SHIFT_REG
  always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
      core[i] <= 0;
    else if (en)
      core[i] <= core[i-1];
  end
end
endgenerate

endmodule
module shift_register
#(
  parameter DEPTH = 16,
  parameter WIDTH = 8
) (
  input  wire             rst_n,
  input  wire             clk,
  input  wire             en,
  input  wire [WIDTH-1:0] d,
  output wire [WIDTH-1:0] q
);


reg [WIDTH-1:0] core [0:DEPTH-1];
assign q = core[DEPTH-1];

always @(posedge clk or negedge rst_n) begin
  if (~rst_n)
    core[0] <= 0;
  else if(en)
    core[0] <= d;
end

genvar i;
generate
for (i = 1; i < DEPTH; i = i + 1) begin :SHIFT_REG
  always @(posedge clk or negedge rst_n) begin
    if(~rst_n)
      core[i] <= 0;
    else if (en)
      core[i] <= core[i-1];
  end
end
endgenerate

endmodule