data/full_repos/permissive/493019833/test/testcase/firrtl/Switch/sbt/Switch.v
data/verilator_xmls/f158ea02-c82c-43a9-8b73-f0290ee6de54.xml
module Switch(
  input        clock,
  input        reset,
  input  [1:0] io_i0,
  input        io_i1,
  output       io_out
);
  assign io_out = io_i1;
endmodule
module Switch(
  input        clock,
  input        reset,
  input  [1:0] io_i0,
  input        io_i1,
  output       io_out
);

  assign io_out = io_i1;
endmodule