data/full_repos/permissive/491340191/top.v
1: b'%Error: data/full_repos/permissive/491340191/top.v:6: Cannot find include file: print.v\n`include "print.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/491340191,data/full_repos/permissive/491340191/print.v\n             data/full_repos/permissive/491340191,data/full_repos/permissive/491340191/print.v.v\n             data/full_repos/permissive/491340191,data/full_repos/permissive/491340191/print.v.sv\n             print.v\n             print.v.v\n             print.v.sv\n             obj_dir/print.v\n             obj_dir/print.v.v\n             obj_dir/print.v.sv\n%Error: data/full_repos/permissive/491340191/top.v:22: Define or directive not defined: \'`print\'\n        `print("Hello World!\\n",STR);\n        ^~~~~~\n%Error: data/full_repos/permissive/491340191/top.v:22: syntax error, unexpected \',\'\n        `print("Hello World!\\n",STR);\n                               ^\n%Error: data/full_repos/permissive/491340191/top.v:25: Define or directive not defined: \'`print\'\n        `print(128\'h0123456789abcdeffedcba9876543210,16); \n        ^~~~~~\n%Error: data/full_repos/permissive/491340191/top.v:25: syntax error, unexpected \',\'\n        `print(128\'h0123456789abcdeffedcba9876543210,16); \n                                                    ^\n%Error: Exiting due to 5 error(s)\n'
module top(
    input clk,
    output txp
);

`include "print.v"

defparam tx.uart_freq=115200;
defparam tx.clk_freq=27000000;

assign txp=uart_txp;
assign print_clk = clk;

reg[31:0] cnt;

always@(posedge clk) begin
    cnt<=cnt+32'd1;
    if(cnt==32'd54_000_000)
        cnt<=32'd0;

    if(cnt==32'd0)
        `print("Hello World!\n",STR);
    
    if(cnt==32'd27_000_000)
        `print(128'h0123456789abcdeffedcba9876543210,16);
end

endmodule
module top(
    input clk,
    output txp
);


`include "print.v"

defparam tx.uart_freq=115200;
defparam tx.clk_freq=27000000;

assign txp=uart_txp;
assign print_clk = clk;

reg[31:0] cnt;

always@(posedge clk) begin
    cnt<=cnt+32'd1;
    if(cnt==32'd54_000_000)
        cnt<=32'd0;

    if(cnt==32'd0)
        `print("Hello World!\n",STR);
    
    if(cnt==32'd27_000_000)
        `print(128'h0123456789abcdeffedcba9876543210,16);
end

endmodule