data/full_repos/permissive/434837003/test/instantiation.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/434837003/test/instantiation.v:17: Unsupported: Ignoring delay on this delayed statement.\nelse #(test3) b(some);\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/434837003/test/instantiation.v:28: Duplicate declaration of cell: \'modinst\'\n)modinst (\n ^~~~~~~\n        data/full_repos/permissive/434837003/test/instantiation.v:20: ... Location of original declaration\nmymod modinst (\n      ^~~~~~~\n%Error: data/full_repos/permissive/434837003/test/instantiation.v:36: Duplicate declaration of cell: \'modinst\'\n)modinst (\n ^~~~~~~\n        data/full_repos/permissive/434837003/test/instantiation.v:28: ... Location of original declaration\n)modinst (\n ^~~~~~~\n%Error: data/full_repos/permissive/434837003/test/instantiation.v:5: Can\'t find definition of variable: \'d\'\nassign #(test) c = d;\n                   ^\n%Warning-IMPLICIT: data/full_repos/permissive/434837003/test/instantiation.v:5: Signal definition not found, creating implicitly: \'c\'\nassign #(test) c = d;\n               ^\n%Error: data/full_repos/permissive/434837003/test/instantiation.v:8: Can\'t find definition of variable: \'lvalue\'\n    lvalue = #(test) c;\n    ^~~~~~\n%Error: data/full_repos/permissive/434837003/test/instantiation.v:12: Can\'t find definition of variable: \'lvalue2\'\n                                                                    : ... Suggested alternative: \'lvalue\'\nlvalue2 = #(test3) d;\n^~~~~~~\n%Error: data/full_repos/permissive/434837003/test/instantiation.v:15: Can\'t find definition of variable: \'a\'\nif (a)\n    ^\n%Error: data/full_repos/permissive/434837003/test/instantiation.v:17: Can\'t find definition of task/function: \'b\'\nelse #(test3) b(some);\n              ^\n%Error: data/full_repos/permissive/434837003/test/instantiation.v:17: Can\'t find definition of variable: \'some\'\nelse #(test3) b(some);\n                ^~~~\n%Error: Exiting due to 8 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

assign #(test) c = d;

initial begin
    lvalue = #(test) c;
end

initial
lvalue2 = #(test3) d;

initial
if (a)
    ;
else #(test3) b(some);


mymod modinst (
  .a (str.aa),
  .b (str.aa==PARAM0),
  .c (str.aa==PARAM1)
);

mymod #(
  .PARAM ()
)modinst (
  .a (str.aa),
  .b (str.aa==PARAM0),
  .c (str.aa==PARAM1)
);

mymod #(
  .PARAM ()
)modinst (
  .a (str.aa),
  .b (str.aa==PARAM0),
  .b (str.aa==PARAM0),
  .b (str.aa==PARAM0),
  .c (str.aa==PARAM1)
);

FL1P3AZ oe_next[NUM_ATC-1:0] (oe_int, zero, state[0] | state[1], ~master_clk, state[1], OE);



module_def module_instance (
    .clk(clk),
    .data(data)
);


Delay #(.width(12), .delay(8)) delay_2r(.clk(clk), .data_in(delay_in_r_2), .data_out(delay_out_r_2));
Delay #(.width(12), .delay(8)) delay_2i(.clk(clk), .data_in(delay_in_i_2), .data_out(delay_out_i_2));
Butterfly #(.width (10)) butterfly_2(
    .mode             (stage_2_mode        ),
    .data_in_a_r      (delay_out_r_2[10:0] ),
    .data_in_a_i      (delay_out_i_2[10:0] ),
    .data_in_b_r      (butterfly_in_r_2    ),
    .data_in_b_i      (butterfly_in_i_2    ),
    .data_out_r       (din_r_3             ),
    .data_out_i       (din_i_3             ),
    .data_out_delay_r (butterfly_out_r_2   ),
    .data_out_delay_i (butterfly_out_i_2   )
);
Multiply #(.in_width(11), .const_width(8), .out_width(12)) multiply_2 (
    .data_in_r    (butterfly_out_r_2 ),
    .data_in_i    (butterfly_out_i_2 ),
    .data_const_r (const_r_2         ),
    .data_const_i (const_i_2         ),
    .data_out_r   (mult_out_r_2      ),
    .data_out_i   (mult_out_i_2      )
);

endmodule
module test;


assign #(test) c = d;

initial begin
    lvalue = #(test) c;
end

initial
lvalue2 = #(test3) d;

initial
if (a)
    ;
else #(test3) b(some);


mymod modinst (
  .a (str.aa),
  .b (str.aa==PARAM0),
  .c (str.aa==PARAM1)
);

mymod #(
  .PARAM ()
)modinst (
  .a (str.aa),
  .b (str.aa==PARAM0),
  .c (str.aa==PARAM1)
);

mymod #(
  .PARAM ()
)modinst (
  .a (str.aa),
  .b (str.aa==PARAM0),
  .b (str.aa==PARAM0),
  .b (str.aa==PARAM0),
  .c (str.aa==PARAM1)
);

FL1P3AZ oe_next[NUM_ATC-1:0] (oe_int, zero, state[0] | state[1], ~master_clk, state[1], OE);



module_def module_instance (
    .clk(clk),
    .data(data)
);


Delay #(.width(12), .delay(8)) delay_2r(.clk(clk), .data_in(delay_in_r_2), .data_out(delay_out_r_2));
Delay #(.width(12), .delay(8)) delay_2i(.clk(clk), .data_in(delay_in_i_2), .data_out(delay_out_i_2));
Butterfly #(.width (10)) butterfly_2(
    .mode             (stage_2_mode        ),
    .data_in_a_r      (delay_out_r_2[10:0] ),
    .data_in_a_i      (delay_out_i_2[10:0] ),
    .data_in_b_r      (butterfly_in_r_2    ),
    .data_in_b_i      (butterfly_in_i_2    ),
    .data_out_r       (din_r_3             ),
    .data_out_i       (din_i_3             ),
    .data_out_delay_r (butterfly_out_r_2   ),
    .data_out_delay_i (butterfly_out_i_2   )
);
Multiply #(.in_width(11), .const_width(8), .out_width(12)) multiply_2 (
    .data_in_r    (butterfly_out_r_2 ),
    .data_in_i    (butterfly_out_i_2 ),
    .data_const_r (const_r_2         ),
    .data_const_i (const_i_2         ),
    .data_out_r   (mult_out_r_2      ),
    .data_out_i   (mult_out_i_2      )
);

endmodule