data/full_repos/permissive/419677538/Exercise_1/verilog_code/FAStruct.v
data/verilator_xmls/9426bd6d-924e-493d-a9eb-89e87670a997.xml
module FAStruct(input a,b,cin,output sum,cout);
    wire an_1,an_2,an_3;
    and(an_1,a,b);
    and(an_3,a,cin);
    and(an_2,b,cin);
    or(cout,an_1,an_2,an_3);
    xor(sum,a,b,cin);
endmodule
module FAStruct(input a,b,cin,output sum,cout);

    wire an_1,an_2,an_3;
    and(an_1,a,b);
    and(an_3,a,cin);
    and(an_2,b,cin);
    or(cout,an_1,an_2,an_3);
    xor(sum,a,b,cin);
endmodule