data/full_repos/permissive/498662723/Verilog Language/More Verilog Features/conditional.v
1: b'%Error: Cannot find file containing module: Language/More\n        ... Looked in:\n             data/full_repos/permissive/498662723/Verilog/Language/More\n             data/full_repos/permissive/498662723/Verilog/Language/More.v\n             data/full_repos/permissive/498662723/Verilog/Language/More.sv\n             Language/More\n             Language/More.v\n             Language/More.sv\n             obj_dir/Language/More\n             obj_dir/Language/More.v\n             obj_dir/Language/More.sv\n%Error: Cannot find file containing module: Verilog\n%Error: Cannot find file containing module: Features,data/full_repos/permissive/498662723\n%Error: Cannot find file containing module: data/full_repos/permissive/498662723/Verilog\n%Error: Cannot find file containing module: Features/conditional.v\n%Error: Exiting due to 5 error(s)\n'
module top_module (
    input [7:0] a, b, c, d,
    output [7:0] min);

    wire [7:0] less1, less2;
    assign less1 = (a < b)? a: b;
    assign less2 = (c < d)? c: d;
    assign min = (less1 < less2)? less1 : less2;
    

endmodule
module top_module (
    input [7:0] a, b, c, d,
    output [7:0] min);


    wire [7:0] less1, less2;
    assign less1 = (a < b)? a: b;
    assign less2 = (c < d)? c: d;
    assign min = (less1 < less2)? less1 : less2;
    

endmodule