data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code/MAJORITY.v
data/verilator_xmls/e1f3be85-d402-48de-ae5f-6801e79cf199.xml
module MAJORITY(
    input x,
    input y,
    input z,
    output p
    );
    
  assign p = (y&z)|(x&z)|(x&y);
  
endmodule
module MAJORITY(
    input x,
    input y,
    input z,
    output p
    );

    
  assign p = (y&z)|(x&z)|(x&y);
  
endmodule