data/full_repos/permissive/435997396/asic/e-class-aardonyx/bfms/issiwrapper.v
1: b'%Error: data/full_repos/permissive/435997396/asic/e-class-aardonyx/bfms/issiwrapper.v:26: Cannot find file containing module: \'IS42s32160\'\nIS42s32160#(.FILENAME("code.mem")) issi (\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/435997396/asic/e-class-aardonyx/bfms,data/full_repos/permissive/435997396/IS42s32160\n             data/full_repos/permissive/435997396/asic/e-class-aardonyx/bfms,data/full_repos/permissive/435997396/IS42s32160.v\n             data/full_repos/permissive/435997396/asic/e-class-aardonyx/bfms,data/full_repos/permissive/435997396/IS42s32160.sv\n             IS42s32160\n             IS42s32160.v\n             IS42s32160.sv\n             obj_dir/IS42s32160\n             obj_dir/IS42s32160.v\n             obj_dir/IS42s32160.sv\n%Error: Exiting due to 1 error(s)\n'
module issiwrapper (dq, addr, ba, old_Clk, cke, cs_n, ras_n, cas_n, we_n, dqm);


    parameter ADDR_BITS        =      13;
    parameter ROW_BITS         =      13;
    parameter DQ_BITS          =      32;
    parameter DM_BITS          =       4;
    parameter COL_BITS         =       9;
    parameter BA_BITS          =       2;


    input                      old_Clk ;
    input                      cke  ;
    input  [ADDR_BITS - 1 : 0] addr ;
    input  [BA_BITS - 1 : 0]   ba   ;
    input                      cs_n ;
    input                      ras_n;
    input                      cas_n;
    input                      we_n ;
    input  [DM_BITS - 1 : 0]   dqm  ;
    inout  [DQ_BITS - 1 : 0]   dq   ;

wire clk = ~old_Clk;


IS42s32160#(.FILENAME("code.mem")) issi	(
			.Dq(dq),
			.Addr(addr),
			.Ba(ba),
			.Clk(clk),
			.Cke(cke),
			.Cs_n(cs_n),
			.Ras_n(ras_n),
			.Cas_n(cas_n),
			.We_n(we_n),
			.Dqm(dqm) );

endmodule
module issiwrapper (dq, addr, ba, old_Clk, cke, cs_n, ras_n, cas_n, we_n, dqm);



    parameter ADDR_BITS        =      13;
    parameter ROW_BITS         =      13;
    parameter DQ_BITS          =      32;
    parameter DM_BITS          =       4;
    parameter COL_BITS         =       9;
    parameter BA_BITS          =       2;


    input                      old_Clk ;
    input                      cke  ;
    input  [ADDR_BITS - 1 : 0] addr ;
    input  [BA_BITS - 1 : 0]   ba   ;
    input                      cs_n ;
    input                      ras_n;
    input                      cas_n;
    input                      we_n ;
    input  [DM_BITS - 1 : 0]   dqm  ;
    inout  [DQ_BITS - 1 : 0]   dq   ;

wire clk = ~old_Clk;


IS42s32160#(.FILENAME("code.mem")) issi	(
			.Dq(dq),
			.Addr(addr),
			.Ba(ba),
			.Clk(clk),
			.Cke(cke),
			.Cs_n(cs_n),
			.Ras_n(ras_n),
			.Cas_n(cas_n),
			.We_n(we_n),
			.Dqm(dqm) );

endmodule