data/full_repos/permissive/43856783/j1_soc/hdl/j1.v
1: b'%Warning-WIDTH: data/full_repos/permissive/43856783/j1_soc/hdl/j1.v:41: Operator ADD expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'pc\' generates 13 bits.\n                                                                      : ... In instance j1\n  assign pc_plus_1 = pc + 1;\n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/j1.v:45: Cannot find file containing module: \'dp_ram\'\ndp_ram #(13, 16, bootram_file)\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43856783/j1_soc/hdl,data/full_repos/permissive/43856783/dp_ram\n             data/full_repos/permissive/43856783/j1_soc/hdl,data/full_repos/permissive/43856783/dp_ram.v\n             data/full_repos/permissive/43856783/j1_soc/hdl,data/full_repos/permissive/43856783/dp_ram.sv\n             dp_ram\n             dp_ram.v\n             dp_ram.sv\n             obj_dir/dp_ram\n             obj_dir/dp_ram.v\n             obj_dir/dp_ram.sv\n%Warning-WIDTH: data/full_repos/permissive/43856783/j1_soc/hdl/j1.v:94: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 13 bits.\n                                                                      : ... In instance j1\n        4\'b1110: _st0 = {rsp, 3\'b000, dsp};\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/43856783/j1_soc/hdl/j1.v:120: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'_pc\' generates 13 bits.\n                                                                       : ... In instance j1\n      _rstkD = _pc;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/43856783/j1_soc/hdl/j1.v:140: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'_pc\' generates 13 bits.\n                                                                       : ... In instance j1\n        _rstkD = _pc;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/43856783/j1_soc/hdl/j1.v:155: Operator ASSIGN expects 13 bits on the Assign RHS, but Assign RHS\'s SEL generates 15 bits.\n                                                                       : ... In instance j1\n        _pc = rst0[15:1];\n            ^\n%Warning-WIDTH: data/full_repos/permissive/43856783/j1_soc/hdl/j1.v:157: Operator ASSIGN expects 13 bits on the Assign RHS, but Assign RHS\'s VARREF \'pc_plus_1\' generates 16 bits.\n                                                                       : ... In instance j1\n        _pc = pc_plus_1;\n            ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n'
module j1#(

              parameter   bootram_file     = "./image.ram"
  )
  (

   sys_clk_i, sys_rst_i, io_din,

   io_rd, io_wr, io_addr, io_dout);

  input sys_clk_i;
  input sys_rst_i;
  input  [15:0] io_din;
  output io_rd;
  output io_wr;
  output [15:0] io_addr;
  output [15:0] io_dout;

  wire [15:0] insn;
  wire [15:0] immediate = { 1'b0, insn[14:0] };

  wire [15:0] ramrd;

  reg [4:0] dsp;
  reg [4:0] _dsp;
  reg [15:0] st0;
  reg [15:0] _st0;
  wire [15:0] st1;
  wire _dstkW;

  reg [12:0] pc;
  reg [12:0] _pc;
  reg [4:0] rsp;
  reg [4:0] _rsp;
  wire [15:0] rst0;
  reg _rstkW;
  reg [15:0] _rstkD;
  wire _ramWE;

  wire [15:0] pc_plus_1;
  assign pc_plus_1 = pc + 1;



dp_ram #(13, 16, bootram_file)
ram0 ( .clk_b(sys_clk_i), .en_b(1), .dat_b(insn), .adr_b({_pc}),
       .clk_a(sys_clk_i), .en_a(|_st0[15:14] == 0), .dat_a_out(ramrd), .dat_a(st1), .we_a(_ramWE & (_st0[15:14] == 0)), .adr_a(st0[15:1])
);

  reg [15:0] dstack[0:31];
  reg [15:0] rstack[0:31];
  always @(posedge sys_clk_i)
  begin
    if (_dstkW)
      dstack[_dsp] = st0;
    if (_rstkW)
      rstack[_rsp] = _rstkD;
  end
  assign st1 = dstack[dsp];
  assign rst0 = rstack[rsp];
  
  reg [3:0] st0sel;
  always @*
  begin
    case (insn[14:13])
      2'b00: st0sel = 0;
      2'b01: st0sel = 1;
      2'b10: st0sel = 0;
      2'b11: st0sel = insn[11:8];
      default: st0sel = 4'bxxxx;
    endcase
  end

  always @*
  begin
    if (insn[15])
      _st0 = immediate;
    else
      case (st0sel)
        4'b0000: _st0 = st0;
        4'b0001: _st0 = st1;
        4'b0010: _st0 = st0 + st1;
        4'b0011: _st0 = st0 & st1;
        4'b0100: _st0 = st0 | st1;
        4'b0101: _st0 = st0 ^ st1;
        4'b0110: _st0 = ~st0;
        4'b0111: _st0 = {16{(st1 == st0)}};
        4'b1000: _st0 = {16{($signed(st1) < $signed(st0))}};
        4'b1001: _st0 = st1 >> st0[3:0];
        4'b1010: _st0 = st0 - 1;
        4'b1011: _st0 = rst0;
        4'b1100: _st0 = |st0[15:14] ? io_din : ramrd;
        4'b1101: _st0 = st1 << st0[3:0];
        4'b1110: _st0 = {rsp, 3'b000, dsp};
        4'b1111: _st0 = {16{(st1 < st0)}};
        default: _st0 = 16'hxxxx;
      endcase
  end

  wire is_alu = (insn[15:13] == 3'b011);
  wire is_lit = (insn[15]);

  assign io_rd = (is_alu & (insn[11:8] == 4'hc) & (|st0[15:14]));
  assign io_wr = _ramWE;
  assign io_addr = st0;
  assign io_dout = st1;

  assign _ramWE = is_alu & insn[5];
  assign _dstkW = is_lit | (is_alu & insn[7]);

  wire [1:0] dd = insn[1:0];
  wire [1:0] rd = insn[3:2];

  always @*
  begin
    if (is_lit) begin
      _dsp = dsp + 1;
      _rsp = rsp;
      _rstkW = 0;
      _rstkD = _pc;
    end else if (is_alu) begin
      _dsp = dsp + {dd[1], dd[1], dd[1], dd};
      _rsp = rsp + {rd[1], rd[1], rd[1], rd};
      _rstkW = insn[6];
      _rstkD = st0;
    end else begin

      if (insn[15:13] == 3'b001) begin
        _dsp = dsp - 1;
      end else begin
        _dsp = dsp;
      end
      if (insn[15:13] == 3'b010) begin
        _rsp = rsp + 1;
        _rstkW = 1;
        _rstkD = {pc_plus_1[14:0], 1'b0};
      end else begin
        _rsp = rsp;
        _rstkW = 0;
        _rstkD = _pc;
      end
    end
  end

  always @*
  begin
    if (sys_rst_i)
      _pc = pc;
    else
      if ((insn[15:13] == 3'b000) |
          ((insn[15:13] == 3'b001) & (|st0 == 0)) |
          (insn[15:13] == 3'b010))
        _pc = insn[12:0];
      else if (is_alu & insn[12])
        _pc = rst0[15:1];
      else
        _pc = pc_plus_1;
  end

  always @(posedge sys_clk_i)
  begin
    if (sys_rst_i) begin
      pc <= 0;
      dsp <= 0;
      st0 <= 0;
      rsp <= 0;
    end else begin
      dsp <= _dsp;
      pc <= _pc;
      st0 <= _st0;
      rsp <= _rsp;
    end
  end

endmodule
module j1#(

              parameter   bootram_file     = "./image.ram"
  )
  (

   sys_clk_i, sys_rst_i, io_din,

   io_rd, io_wr, io_addr, io_dout);


  input sys_clk_i;
  input sys_rst_i;
  input  [15:0] io_din;
  output io_rd;
  output io_wr;
  output [15:0] io_addr;
  output [15:0] io_dout;

  wire [15:0] insn;
  wire [15:0] immediate = { 1'b0, insn[14:0] };

  wire [15:0] ramrd;

  reg [4:0] dsp;
  reg [4:0] _dsp;
  reg [15:0] st0;
  reg [15:0] _st0;
  wire [15:0] st1;
  wire _dstkW;

  reg [12:0] pc;
  reg [12:0] _pc;
  reg [4:0] rsp;
  reg [4:0] _rsp;
  wire [15:0] rst0;
  reg _rstkW;
  reg [15:0] _rstkD;
  wire _ramWE;

  wire [15:0] pc_plus_1;
  assign pc_plus_1 = pc + 1;



dp_ram #(13, 16, bootram_file)
ram0 ( .clk_b(sys_clk_i), .en_b(1), .dat_b(insn), .adr_b({_pc}),
       .clk_a(sys_clk_i), .en_a(|_st0[15:14] == 0), .dat_a_out(ramrd), .dat_a(st1), .we_a(_ramWE & (_st0[15:14] == 0)), .adr_a(st0[15:1])
);

  reg [15:0] dstack[0:31];
  reg [15:0] rstack[0:31];
  always @(posedge sys_clk_i)
  begin
    if (_dstkW)
      dstack[_dsp] = st0;
    if (_rstkW)
      rstack[_rsp] = _rstkD;
  end
  assign st1 = dstack[dsp];
  assign rst0 = rstack[rsp];
  
  reg [3:0] st0sel;
  always @*
  begin
    case (insn[14:13])
      2'b00: st0sel = 0;
      2'b01: st0sel = 1;
      2'b10: st0sel = 0;
      2'b11: st0sel = insn[11:8];
      default: st0sel = 4'bxxxx;
    endcase
  end

  always @*
  begin
    if (insn[15])
      _st0 = immediate;
    else
      case (st0sel)
        4'b0000: _st0 = st0;
        4'b0001: _st0 = st1;
        4'b0010: _st0 = st0 + st1;
        4'b0011: _st0 = st0 & st1;
        4'b0100: _st0 = st0 | st1;
        4'b0101: _st0 = st0 ^ st1;
        4'b0110: _st0 = ~st0;
        4'b0111: _st0 = {16{(st1 == st0)}};
        4'b1000: _st0 = {16{($signed(st1) < $signed(st0))}};
        4'b1001: _st0 = st1 >> st0[3:0];
        4'b1010: _st0 = st0 - 1;
        4'b1011: _st0 = rst0;
        4'b1100: _st0 = |st0[15:14] ? io_din : ramrd;
        4'b1101: _st0 = st1 << st0[3:0];
        4'b1110: _st0 = {rsp, 3'b000, dsp};
        4'b1111: _st0 = {16{(st1 < st0)}};
        default: _st0 = 16'hxxxx;
      endcase
  end

  wire is_alu = (insn[15:13] == 3'b011);
  wire is_lit = (insn[15]);

  assign io_rd = (is_alu & (insn[11:8] == 4'hc) & (|st0[15:14]));
  assign io_wr = _ramWE;
  assign io_addr = st0;
  assign io_dout = st1;

  assign _ramWE = is_alu & insn[5];
  assign _dstkW = is_lit | (is_alu & insn[7]);

  wire [1:0] dd = insn[1:0];
  wire [1:0] rd = insn[3:2];

  always @*
  begin
    if (is_lit) begin
      _dsp = dsp + 1;
      _rsp = rsp;
      _rstkW = 0;
      _rstkD = _pc;
    end else if (is_alu) begin
      _dsp = dsp + {dd[1], dd[1], dd[1], dd};
      _rsp = rsp + {rd[1], rd[1], rd[1], rd};
      _rstkW = insn[6];
      _rstkD = st0;
    end else begin

      if (insn[15:13] == 3'b001) begin
        _dsp = dsp - 1;
      end else begin
        _dsp = dsp;
      end
      if (insn[15:13] == 3'b010) begin
        _rsp = rsp + 1;
        _rstkW = 1;
        _rstkD = {pc_plus_1[14:0], 1'b0};
      end else begin
        _rsp = rsp;
        _rstkW = 0;
        _rstkD = _pc;
      end
    end
  end

  always @*
  begin
    if (sys_rst_i)
      _pc = pc;
    else
      if ((insn[15:13] == 3'b000) |
          ((insn[15:13] == 3'b001) & (|st0 == 0)) |
          (insn[15:13] == 3'b010))
        _pc = insn[12:0];
      else if (is_alu & insn[12])
        _pc = rst0[15:1];
      else
        _pc = pc_plus_1;
  end

  always @(posedge sys_clk_i)
  begin
    if (sys_rst_i) begin
      pc <= 0;
      dsp <= 0;
      st0 <= 0;
      rsp <= 0;
    end else begin
      dsp <= _dsp;
      pc <= _pc;
      st0 <= _st0;
      rsp <= _rsp;
    end
  end

endmodule