data/full_repos/permissive/497604366/cpu/cpu.srcs/sources_1/new/fwd_b_mux.v
data/verilator_xmls/f94b5095-1e8d-498c-a605-0efebf52b353.xml
module fwd_b_mux(
    input [1:0] fwdb,
    input [31:0] qb,
    input [31:0] r,
    input [31:0] mr,
    input [31:0] mdo,
    output reg [31:0] fwdb_output
    );
    
    always@(*) begin
        if (fwdb == 2'b00) begin
            fwdb_output <= qb;
        end
        else if (fwdb == 2'b01) begin
            fwdb_output <= r;
        end
        else if (fwdb == 2'b10) begin
            fwdb_output <= mr;
        end
        else if (fwdb == 2'b11) begin
            fwdb_output <= mdo;
        end
    end
endmodule
module fwd_b_mux(
    input [1:0] fwdb,
    input [31:0] qb,
    input [31:0] r,
    input [31:0] mr,
    input [31:0] mdo,
    output reg [31:0] fwdb_output
    );

    
    always@(*) begin
        if (fwdb == 2'b00) begin
            fwdb_output <= qb;
        end
        else if (fwdb == 2'b01) begin
            fwdb_output <= r;
        end
        else if (fwdb == 2'b10) begin
            fwdb_output <= mr;
        end
        else if (fwdb == 2'b11) begin
            fwdb_output <= mdo;
        end
    end
endmodule