data/full_repos/permissive/455421905/src/hms.v
1: b'%Warning-WIDTH: data/full_repos/permissive/455421905/src/hms.v:490: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'FLOAT\' generates 16 bits.\n                                                                  : ... In instance MERGE_TREE.level[0].nodes[1].merge_node.merge_logic\n      if (FLOAT == "yes" || SIGNED == "yes") begin\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/455421905/src/hms.v:490: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'SIGNED\' generates 16 bits.\n                                                                  : ... In instance MERGE_TREE.level[0].nodes[1].merge_node.merge_logic\n      if (FLOAT == "yes" || SIGNED == "yes") begin\n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/455421905/src/hms.v:342: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'FLOAT\' generates 16 bits.\n                                                                  : ... In instance MERGE_TREE.level[0].nodes[1].merge_node.merge_logic.merge_network\n      if (FLOAT == "yes" || SIGNED == "yes") begin\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/455421905/src/hms.v:342: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'SIGNED\' generates 16 bits.\n                                                                  : ... In instance MERGE_TREE.level[0].nodes[1].merge_node.merge_logic.merge_network\n      if (FLOAT == "yes" || SIGNED == "yes") begin\n                                   ^~\n%Error: data/full_repos/permissive/455421905/src/hms.v:80: Cannot find file containing module: \'COMPARATOR\'\n  COMPARATOR #(FLOAT, SIGNED, KEYW)\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/COMPARATOR\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/COMPARATOR.v\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/COMPARATOR.sv\n             COMPARATOR\n             COMPARATOR.v\n             COMPARATOR.sv\n             obj_dir/COMPARATOR\n             obj_dir/COMPARATOR.v\n             obj_dir/COMPARATOR.sv\n%Error: data/full_repos/permissive/455421905/src/hms.v:564: Cannot find file containing module: \'BS_FIFO\'\n  BS_FIFO #(5, (DATW<<E_LOG), USE_IPCORE)\n  ^~~~~~~\n%Error: data/full_repos/permissive/455421905/src/hms.v:567: Cannot find file containing module: \'BS_FIFO\'\n  BS_FIFO #(5, (DATW<<E_LOG), USE_IPCORE)\n  ^~~~~~~\n%Error: data/full_repos/permissive/455421905/src/hms.v:606: Cannot find file containing module: \'COMPARATOR\'\n      COMPARATOR #(FLOAT, SIGNED, KEYW)\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/455421905/src/hms.v:673: Cannot find file containing module: \'BS_FIFO\'\n  BS_FIFO #(FIFO_SIZE, (DATW<<E_LOG), USE_IPCORE)\n  ^~~~~~~\n%Error: Exiting due to 5 error(s), 4 warning(s)\n'
module MERGE_TREE #(parameter                       E_LOG      = 2,
                    parameter                       USE_IPCORE = "INTEL",
                    parameter                       FLOAT      = "no",
                    parameter                       SIGNED     = "no",
                    parameter                       DATW       = 64,
                    parameter                       KEYW       = 32)
                   (input  wire                     CLK,
                    input  wire                     RST,
                    input  wire                     IN_FULL,
                    input  wire [(DATW<<E_LOG)-1:0] DIN,
                    input  wire [(1<<E_LOG)-1:0]    DINEN,
                    output wire [(1<<E_LOG)-1:0]    FULL,
                    output wire [(DATW<<E_LOG)-1:0] DOT,
                    output wire                     DOTEN);

  genvar i, j;
  generate
    for (i=0; i<E_LOG; i=i+1) begin: level
      wire [(1<<(E_LOG-(i+1)))-1:0] node_in_full;
      wire [(DATW<<E_LOG)-1:0]      node_din;
      wire [(1<<(E_LOG-i))-1:0]     node_dinen;
      wire [(1<<(E_LOG-i))-1:0]     node_full;
      wire [(DATW<<E_LOG)-1:0]      node_dot;
      wire [(1<<(E_LOG-(i+1)))-1:0] node_doten;
      for (j=0; j<(1<<(E_LOG-(i+1))); j=j+1) begin: nodes
        MERGE_NODE #((i+1), USE_IPCORE, FLOAT, SIGNED, DATW, KEYW)
        merge_node(CLK, RST, node_in_full[j], node_din[(DATW<<(i))*(2*j+1)-1:(DATW<<(i))*(2*j)], node_dinen[2*j], node_din[(DATW<<(i))*(2*j+2)-1:(DATW<<(i))*(2*j+1)], node_dinen[2*j+1],
                   node_full[2*j], node_full[2*j+1], node_dot[(DATW<<(i+1))*(j+1)-1:(DATW<<(i+1))*j], node_doten[j]);
      end
    end
  endgenerate

  generate
    for (i=0; i<E_LOG; i=i+1) begin: connection
      if (i == 0) begin
        assign level[0].node_din   = DIN;
        assign level[0].node_dinen = DINEN;
        assign FULL                = level[0].node_full;
      end else begin
        assign level[i].node_din       = level[i-1].node_dot;
        assign level[i].node_dinen     = level[i-1].node_doten;
        assign level[i-1].node_in_full = level[i].node_full;
      end
    end
  endgenerate

  assign level[E_LOG-1].node_in_full = IN_FULL;
  assign DOT                         = level[E_LOG-1].node_dot;
  assign DOTEN                       = level[E_LOG-1].node_doten;

endmodule
module MERGE_TREE #(parameter                       E_LOG      = 2,
                    parameter                       USE_IPCORE = "INTEL",
                    parameter                       FLOAT      = "no",
                    parameter                       SIGNED     = "no",
                    parameter                       DATW       = 64,
                    parameter                       KEYW       = 32)
                   (input  wire                     CLK,
                    input  wire                     RST,
                    input  wire                     IN_FULL,
                    input  wire [(DATW<<E_LOG)-1:0] DIN,
                    input  wire [(1<<E_LOG)-1:0]    DINEN,
                    output wire [(1<<E_LOG)-1:0]    FULL,
                    output wire [(DATW<<E_LOG)-1:0] DOT,
                    output wire                     DOTEN);


  genvar i, j;
  generate
    for (i=0; i<E_LOG; i=i+1) begin: level
      wire [(1<<(E_LOG-(i+1)))-1:0] node_in_full;
      wire [(DATW<<E_LOG)-1:0]      node_din;
      wire [(1<<(E_LOG-i))-1:0]     node_dinen;
      wire [(1<<(E_LOG-i))-1:0]     node_full;
      wire [(DATW<<E_LOG)-1:0]      node_dot;
      wire [(1<<(E_LOG-(i+1)))-1:0] node_doten;
      for (j=0; j<(1<<(E_LOG-(i+1))); j=j+1) begin: nodes
        MERGE_NODE #((i+1), USE_IPCORE, FLOAT, SIGNED, DATW, KEYW)
        merge_node(CLK, RST, node_in_full[j], node_din[(DATW<<(i))*(2*j+1)-1:(DATW<<(i))*(2*j)], node_dinen[2*j], node_din[(DATW<<(i))*(2*j+2)-1:(DATW<<(i))*(2*j+1)], node_dinen[2*j+1],
                   node_full[2*j], node_full[2*j+1], node_dot[(DATW<<(i+1))*(j+1)-1:(DATW<<(i+1))*j], node_doten[j]);
      end
    end
  endgenerate

  generate
    for (i=0; i<E_LOG; i=i+1) begin: connection
      if (i == 0) begin
        assign level[0].node_din   = DIN;
        assign level[0].node_dinen = DINEN;
        assign FULL                = level[0].node_full;
      end else begin
        assign level[i].node_din       = level[i-1].node_dot;
        assign level[i].node_dinen     = level[i-1].node_doten;
        assign level[i-1].node_in_full = level[i].node_full;
      end
    end
  endgenerate

  assign level[E_LOG-1].node_in_full = IN_FULL;
  assign DOT                         = level[E_LOG-1].node_dot;
  assign DOTEN                       = level[E_LOG-1].node_doten;

endmodule