data/full_repos/permissive/518669498/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/518669498/verilog/rtl/user_proj_example.v:868: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/518669498/verilog/rtl/user_proj_example.v:869: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/518669498/verilog/rtl/user_proj_example.v:870: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/518669498/verilog/rtl/user_proj_example.v:878: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_in;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/518669498/verilog/rtl/user_proj_example.v:879: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_out;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/518669498/verilog/rtl/user_proj_example.v:880: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_oeb;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/518669498/verilog/rtl/user_proj_example.v:898: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};\n                      ^~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module PE #(

  parameter W = 16
) (
  input  wire                 i_clk,
  input  wire                 i_rst,
  input  wire                 i_en,
  input  wire                 i_mode,
  input  wire [    W - 1 : 0] i_A,
  input  wire [    W - 1 : 0] i_B,
  output wire [    W - 1 : 0] o_A,
  output wire [    W - 1 : 0] o_B,

  output reg  [    W - 1 : 0] o_C
);




  wire sync_load;
  assign o_A = i_A_buffered;
  assign o_B = i_B_buffered;
  assign sync_load = i_rst | ~i_en;

  wire [W - 1 : 0] i_A_buffered;
  wire [W - 1 : 0] i_B_buffered;

  reg  [15 : 0] accu;
  wire [15 : 0] mac_out;


  delay2 #(.WIDTH(W), .DEPTH(1)) delayA(.clk(i_clk), .reset(i_rst), .data_in(i_A), .data_out(i_A_buffered));
  delay2 #(.WIDTH(W), .DEPTH(1)) delayB(.clk(i_clk), .reset(i_rst), .data_in(i_B), .data_out(i_B_buffered));

  always @(posedge i_clk) begin
    if (sync_load) begin
      accu <= 0;
      o_C  <= 0;
    end
    else begin
      accu <= mac_out;
      o_C  <= mac_out;
    end
  end


  mac_unit u0_mac(
    .in_a    (i_A_buffered),
    .in_b    (i_B_buffered),
    .in_c    (accu),
    .mode    (i_mode),
    .mac_out (mac_out)
  );

endmodule
module PE #(

  parameter W = 16
) (
  input  wire                 i_clk,
  input  wire                 i_rst,
  input  wire                 i_en,
  input  wire                 i_mode,
  input  wire [    W - 1 : 0] i_A,
  input  wire [    W - 1 : 0] i_B,
  output wire [    W - 1 : 0] o_A,
  output wire [    W - 1 : 0] o_B,

  output reg  [    W - 1 : 0] o_C
);





  wire sync_load;
  assign o_A = i_A_buffered;
  assign o_B = i_B_buffered;
  assign sync_load = i_rst | ~i_en;

  wire [W - 1 : 0] i_A_buffered;
  wire [W - 1 : 0] i_B_buffered;

  reg  [15 : 0] accu;
  wire [15 : 0] mac_out;


  delay2 #(.WIDTH(W), .DEPTH(1)) delayA(.clk(i_clk), .reset(i_rst), .data_in(i_A), .data_out(i_A_buffered));
  delay2 #(.WIDTH(W), .DEPTH(1)) delayB(.clk(i_clk), .reset(i_rst), .data_in(i_B), .data_out(i_B_buffered));

  always @(posedge i_clk) begin
    if (sync_load) begin
      accu <= 0;
      o_C  <= 0;
    end
    else begin
      accu <= mac_out;
      o_C  <= mac_out;
    end
  end


  mac_unit u0_mac(
    .in_a    (i_A_buffered),
    .in_b    (i_B_buffered),
    .in_c    (accu),
    .mode    (i_mode),
    .mac_out (mac_out)
  );

endmodule