data/full_repos/permissive/488093047/Verilog Codes/Demux1x2.v
1: b'%Error: Cannot find file containing module: Codes,data/full_repos/permissive/488093047\n        ... Looked in:\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.v\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.sv\n             Codes,data/full_repos/permissive/488093047\n             Codes,data/full_repos/permissive/488093047.v\n             Codes,data/full_repos/permissive/488093047.sv\n             obj_dir/Codes,data/full_repos/permissive/488093047\n             obj_dir/Codes,data/full_repos/permissive/488093047.v\n             obj_dir/Codes,data/full_repos/permissive/488093047.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/488093047/Verilog\n%Error: Cannot find file containing module: Codes/Demux1x2.v\n%Error: Exiting due to 3 error(s)\n'
module Demux1x2 #(parameter N=32)(S0,I,Y0,Y1);
input S0;
input [N-1:0]I;
output [N-1:0]Y0,Y1;
wire [N-1:0]S0n;
wire [N-1:0]SS0;
assign SS0={(N){S0}};

NOT #(.N(N)) DUT1(.A(SS0),.NOT(S0n));

AND #(.N(N)) DUT2(.A(S0n),.B(I),.AND(Y0));

AND #(.N(N)) DUT3(.A(SS0),.B(I),.AND(Y1));
endmodule
module Demux1x2 #(parameter N=32)(S0,I,Y0,Y1);

input S0;
input [N-1:0]I;
output [N-1:0]Y0,Y1;
wire [N-1:0]S0n;
wire [N-1:0]SS0;
assign SS0={(N){S0}};

NOT #(.N(N)) DUT1(.A(SS0),.NOT(S0n));

AND #(.N(N)) DUT2(.A(S0n),.B(I),.AND(Y0));

AND #(.N(N)) DUT3(.A(SS0),.B(I),.AND(Y1));
endmodule