data/full_repos/permissive/421481661/wrapper.v
1: b"%Error: data/full_repos/permissive/421481661/wrapper.v:41: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  wire [`MPRJ_IO_PADS-1:0] io_in,   \n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421481661/wrapper.v:42: Define or directive not defined: '`MPRJ_IO_PADS'\n    output wire [`MPRJ_IO_PADS-1:0] io_out,  \n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421481661/wrapper.v:43: Define or directive not defined: '`MPRJ_IO_PADS'\n    output wire [`MPRJ_IO_PADS-1:0] io_oeb,  \n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421481661/wrapper.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] buf_io_out;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421481661/wrapper.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] buf_io_oeb;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421481661/wrapper.v:96: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_out       = active ? buf_io_out       : {`MPRJ_IO_PADS{1'bz}};\n                                                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421481661/wrapper.v:97: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_oeb       = active ? buf_io_oeb       : {`MPRJ_IO_PADS{1'bz}};\n                                                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421481661/wrapper.v:105: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign buf_io_oeb = {`MPRJ_IO_PADS{1'b0}};\n                         ^~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module wrapped_ws2812(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif
    input wire wb_clk_i,

`ifdef USE_WB
    input wire wb_rst_i,
    input wire wbs_stb_i,
    input wire wbs_cyc_i,
    input wire wbs_we_i,
    input wire [3:0] wbs_sel_i,
    input wire [31:0] wbs_dat_i,
    input wire [31:0] wbs_adr_i,
    output wire wbs_ack_o,
    output wire [31:0] wbs_dat_o,
`endif


`ifdef USE_LA
    input  wire [31:0] la1_data_in,
    output wire [31:0] la1_data_out,
    input  wire [31:0] la1_oenb,
`endif


`ifdef USE_IO
    input  wire [`MPRJ_IO_PADS-1:0] io_in,
    output wire [`MPRJ_IO_PADS-1:0] io_out,
    output wire [`MPRJ_IO_PADS-1:0] io_oeb,
`endif


`ifdef USE_IRQ
    output wire [2:0] user_irq,
`endif

`ifdef USE_CLK2

    input wire user_clock2,
`endif
    

    input wire active
);


    wire buf_wbs_ack_o;
    wire [31:0] buf_wbs_dat_o;
    wire [31:0] buf_la1_data_out;
    wire [`MPRJ_IO_PADS-1:0] buf_io_out;
    wire [`MPRJ_IO_PADS-1:0] buf_io_oeb;
    wire [2:0] buf_user_irq;

    `ifdef FORMAL

    `ifdef USE_WB
    assign wbs_ack_o    = active ? buf_wbs_ack_o    : 1'b0;
    assign wbs_dat_o    = active ? buf_wbs_dat_o    : 32'b0;
    `endif
    `ifdef USE_LA
    assign la1_data_out = active ? buf_la1_data_out  : 32'b0;
    `endif
    `ifdef USE_IO
    assign io_out       = active ? buf_io_out       : {`MPRJ_IO_PADS{1'b0}};
    assign io_oeb       = active ? buf_io_oeb       : {`MPRJ_IO_PADS{1'b0}};
    `endif
    `ifdef USE_IRQ
    assign user_irq     = active ? buf_user_irq          : 3'b0;
    `endif
    `include "properties.v"
    `else

    
    `ifdef USE_WB
    assign wbs_ack_o    = active ? buf_wbs_ack_o    : 1'bz;
    assign wbs_dat_o    = active ? buf_wbs_dat_o    : 32'bz;
    `endif
    `ifdef USE_LA
    assign la1_data_out  = active ? buf_la1_data_out  : 32'bz;
    `endif
    `ifdef USE_IO
    assign io_out       = active ? buf_io_out       : {`MPRJ_IO_PADS{1'bz}};
    assign io_oeb       = active ? buf_io_oeb       : {`MPRJ_IO_PADS{1'bz}};
    `endif
    `ifdef USE_IRQ
    assign user_irq     = active ? buf_user_irq          : 3'bz;
    `endif
    `endif


    assign buf_io_oeb = {`MPRJ_IO_PADS{1'b0}};







    ws2812 ws2812(
        .clk(wb_clk_i),
        .reset(la1_data_in[0]),
        .led_num({5'b0, la1_data_in[3:1]}),
        .rgb_data(la1_data_in[27:4]),
        .write(la1_data_in[28]),
        .data(buf_io_out[8])
    );

endmodule
module wrapped_ws2812(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif
    input wire wb_clk_i,

`ifdef USE_WB
    input wire wb_rst_i,
    input wire wbs_stb_i,
    input wire wbs_cyc_i,
    input wire wbs_we_i,
    input wire [3:0] wbs_sel_i,
    input wire [31:0] wbs_dat_i,
    input wire [31:0] wbs_adr_i,
    output wire wbs_ack_o,
    output wire [31:0] wbs_dat_o,
`endif


`ifdef USE_LA
    input  wire [31:0] la1_data_in,
    output wire [31:0] la1_data_out,
    input  wire [31:0] la1_oenb,
`endif


`ifdef USE_IO
    input  wire [`MPRJ_IO_PADS-1:0] io_in,
    output wire [`MPRJ_IO_PADS-1:0] io_out,
    output wire [`MPRJ_IO_PADS-1:0] io_oeb,
`endif


`ifdef USE_IRQ
    output wire [2:0] user_irq,
`endif

`ifdef USE_CLK2

    input wire user_clock2,
`endif
    

    input wire active
);



    wire buf_wbs_ack_o;
    wire [31:0] buf_wbs_dat_o;
    wire [31:0] buf_la1_data_out;
    wire [`MPRJ_IO_PADS-1:0] buf_io_out;
    wire [`MPRJ_IO_PADS-1:0] buf_io_oeb;
    wire [2:0] buf_user_irq;

    `ifdef FORMAL

    `ifdef USE_WB
    assign wbs_ack_o    = active ? buf_wbs_ack_o    : 1'b0;
    assign wbs_dat_o    = active ? buf_wbs_dat_o    : 32'b0;
    `endif
    `ifdef USE_LA
    assign la1_data_out = active ? buf_la1_data_out  : 32'b0;
    `endif
    `ifdef USE_IO
    assign io_out       = active ? buf_io_out       : {`MPRJ_IO_PADS{1'b0}};
    assign io_oeb       = active ? buf_io_oeb       : {`MPRJ_IO_PADS{1'b0}};
    `endif
    `ifdef USE_IRQ
    assign user_irq     = active ? buf_user_irq          : 3'b0;
    `endif
    `include "properties.v"
    `else

    
    `ifdef USE_WB
    assign wbs_ack_o    = active ? buf_wbs_ack_o    : 1'bz;
    assign wbs_dat_o    = active ? buf_wbs_dat_o    : 32'bz;
    `endif
    `ifdef USE_LA
    assign la1_data_out  = active ? buf_la1_data_out  : 32'bz;
    `endif
    `ifdef USE_IO
    assign io_out       = active ? buf_io_out       : {`MPRJ_IO_PADS{1'bz}};
    assign io_oeb       = active ? buf_io_oeb       : {`MPRJ_IO_PADS{1'bz}};
    `endif
    `ifdef USE_IRQ
    assign user_irq     = active ? buf_user_irq          : 3'bz;
    `endif
    `endif


    assign buf_io_oeb = {`MPRJ_IO_PADS{1'b0}};







    ws2812 ws2812(
        .clk(wb_clk_i),
        .reset(la1_data_in[0]),
        .led_num({5'b0, la1_data_in[3:1]}),
        .rgb_data(la1_data_in[27:4]),
        .write(la1_data_in[28]),
        .data(buf_io_out[8])
    );

endmodule