data/full_repos/permissive/515100461/ALU/ALU.v
1: b'%Error: data/full_repos/permissive/515100461/ALU/ALU.v:1: Cannot find include file: Add.v\n`include "Add.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/515100461/ALU,data/full_repos/permissive/515100461/Add.v\n             data/full_repos/permissive/515100461/ALU,data/full_repos/permissive/515100461/Add.v.v\n             data/full_repos/permissive/515100461/ALU,data/full_repos/permissive/515100461/Add.v.sv\n             Add.v\n             Add.v.v\n             Add.v.sv\n             obj_dir/Add.v\n             obj_dir/Add.v.v\n             obj_dir/Add.v.sv\n%Error: data/full_repos/permissive/515100461/ALU/ALU.v:2: Cannot find include file: sub.v\n`include "sub.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/515100461/ALU/ALU.v:3: Cannot find include file: Xor.v\n`include "Xor.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/515100461/ALU/ALU.v:4: Cannot find include file: And.v\n`include "And.v" \n         ^~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module alu(control,a,b,end_result,carry_overflow);

input [1:0]control;
input signed [63:0]a,b;
output reg signed [63:0] end_result;
output reg carry_overflow;


wire signed [63:0]add_result,sub_result,xor_result,and_result;


Xor s3(a,b,xor_result);
And s4(a,b,and_result);
Sub s2(a,b,sub_result,carry_overflow_sub);
Add s1(a,b,add_result,carry_overflow_add);

always @(*) begin
    case(control)
    2'b00:begin
        end_result = add_result;
        carry_overflow = carry_overflow_add; 
    end
    2'b01:begin
        end_result = sub_result;
        carry_overflow = carry_overflow_sub;
    end
    2'b10:begin
        end_result = and_result;
        carry_overflow = 0;
    end
    2'b11:begin
        end_result = xor_result;
        carry_overflow = 0;
    end
    endcase
end
endmodule
module alu(control,a,b,end_result,carry_overflow);


input [1:0]control;
input signed [63:0]a,b;
output reg signed [63:0] end_result;
output reg carry_overflow;


wire signed [63:0]add_result,sub_result,xor_result,and_result;


Xor s3(a,b,xor_result);
And s4(a,b,and_result);
Sub s2(a,b,sub_result,carry_overflow_sub);
Add s1(a,b,add_result,carry_overflow_add);

always @(*) begin
    case(control)
    2'b00:begin
        end_result = add_result;
        carry_overflow = carry_overflow_add; 
    end
    2'b01:begin
        end_result = sub_result;
        carry_overflow = carry_overflow_sub;
    end
    2'b10:begin
        end_result = and_result;
        carry_overflow = 0;
    end
    2'b11:begin
        end_result = xor_result;
        carry_overflow = 0;
    end
    endcase
end
endmodule