data/full_repos/permissive/500396778/Microprocessor-Control-Logic-using/mproc_mem.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/500396778/Microprocessor-Control-Logic-using/mproc_mem.v:2: Little bit endian vector: MSB < LSB of bit range: 0:127\n  reg [0:127] ram [15:0];\n      ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/500396778/Microprocessor-Control-Logic-using/mproc_mem.v:5: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'b10xxxxx000xxxxxx\' generates 16 bits.\n                                                                                                     : ... In instance mproc_mem.ram_128_16_0\n    ram[0]=16\'b10xxxxx000xxxxxx;  \n          ^\n%Warning-WIDTH: data/full_repos/permissive/500396778/Microprocessor-Control-Logic-using/mproc_mem.v:6: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h1\' generates 16 bits.\n                                                                                                     : ... In instance mproc_mem.ram_128_16_0\n    ram[1]=16\'h01;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/500396778/Microprocessor-Control-Logic-using/mproc_mem.v:7: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'b10xxxxx001xxxxxx\' generates 16 bits.\n                                                                                                     : ... In instance mproc_mem.ram_128_16_0\n    ram[2]=16\'b10xxxxx001xxxxxx;  \n          ^\n%Warning-WIDTH: data/full_repos/permissive/500396778/Microprocessor-Control-Logic-using/mproc_mem.v:8: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h15\' generates 16 bits.\n                                                                                                     : ... In instance mproc_mem.ram_128_16_0\n    ram[3]=16\'h15;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/500396778/Microprocessor-Control-Logic-using/mproc_mem.v:9: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'b10xxxxx010xxxxxx\' generates 16 bits.\n                                                                                                     : ... In instance mproc_mem.ram_128_16_0\n    ram[4]=16\'b10xxxxx010xxxxxx;  \n          ^\n%Warning-WIDTH: data/full_repos/permissive/500396778/Microprocessor-Control-Logic-using/mproc_mem.v:10: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h1\' generates 16 bits.\n                                                                                                      : ... In instance mproc_mem.ram_128_16_0\n    ram[5]=16\'h01;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/500396778/Microprocessor-Control-Logic-using/mproc_mem.v:11: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'b10xxxxx011xxxxxx\' generates 16 bits.\n                                                                                                      : ... In instance mproc_mem.ram_128_16_0\n    ram[6]=16\'b10xxxxx011xxxxxx;  \n          ^\n%Warning-WIDTH: data/full_repos/permissive/500396778/Microprocessor-Control-Logic-using/mproc_mem.v:12: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h1\' generates 16 bits.\n                                                                                                      : ... In instance mproc_mem.ram_128_16_0\n    ram[7]=16\'h01;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/500396778/Microprocessor-Control-Logic-using/mproc_mem.v:13: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h113\' generates 16 bits.\n                                                                                                      : ... In instance mproc_mem.ram_128_16_0\n    ram[8]=16\'b0000000100010011;  \n          ^\n%Warning-WIDTH: data/full_repos/permissive/500396778/Microprocessor-Control-Logic-using/mproc_mem.v:14: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h49b\' generates 16 bits.\n                                                                                                      : ... In instance mproc_mem.ram_128_16_0\n    ram[9]=16\'b0000010010011011;  \n          ^\n%Warning-WIDTH: data/full_repos/permissive/500396778/Microprocessor-Control-Logic-using/mproc_mem.v:15: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h4e4\' generates 16 bits.\n                                                                                                      : ... In instance mproc_mem.ram_128_16_0\n    ram[10]=16\'b0000010011100100;  \n           ^\n%Warning-WIDTH: data/full_repos/permissive/500396778/Microprocessor-Control-Logic-using/mproc_mem.v:16: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h241\' generates 16 bits.\n                                                                                                      : ... In instance mproc_mem.ram_128_16_0\n    ram[11]=16\'b0000001001000001;  \n           ^\n%Warning-WIDTH: data/full_repos/permissive/500396778/Microprocessor-Control-Logic-using/mproc_mem.v:17: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'b1xxxxxx00000101\' generates 16 bits.\n                                                                                                      : ... In instance mproc_mem.ram_128_16_0\n    ram[12]=16\'b01xxxxxx00000101;  \n           ^\n%Warning-WIDTH: data/full_repos/permissive/500396778/Microprocessor-Control-Logic-using/mproc_mem.v:18: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h424\' generates 16 bits.\n                                                                                                      : ... In instance mproc_mem.ram_128_16_0\n    ram[13]=16\'b0000010000100100;  \n           ^\n%Warning-WIDTH: data/full_repos/permissive/500396778/Microprocessor-Control-Logic-using/mproc_mem.v:20: Bit extraction of array[15:0] requires 4 bit index, not 7 bits.\n                                                                                                      : ... In instance mproc_mem.ram_128_16_0\n  always @(wr) ram[addr]=din;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/500396778/Microprocessor-Control-Logic-using/mproc_mem.v:20: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                      : ... In instance mproc_mem.ram_128_16_0\n  always @(wr) ram[addr]=din;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/500396778/Microprocessor-Control-Logic-using/mproc_mem.v:21: Bit extraction of array[15:0] requires 4 bit index, not 7 bits.\n                                                                                                      : ... In instance mproc_mem.ram_128_16_0\n  assign dout=ram[addr];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/500396778/Microprocessor-Control-Logic-using/mproc_mem.v:21: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 128 bits.\n                                                                                                      : ... In instance mproc_mem.ram_128_16_0\n  assign dout=ram[addr];\n             ^\n%Error: data/full_repos/permissive/500396778/Microprocessor-Control-Logic-using/mproc_mem.v:28: Cannot find file containing module: \'mproc\'\n  mproc mproc_0 (clk, reset, d_in, addr, d_out);\n  ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/500396778/Microprocessor-Control-Logic-using,data/full_repos/permissive/500396778/mproc\n             data/full_repos/permissive/500396778/Microprocessor-Control-Logic-using,data/full_repos/permissive/500396778/mproc.v\n             data/full_repos/permissive/500396778/Microprocessor-Control-Logic-using,data/full_repos/permissive/500396778/mproc.sv\n             mproc\n             mproc.v\n             mproc.sv\n             obj_dir/mproc\n             obj_dir/mproc.v\n             obj_dir/mproc.sv\n%Error: Exiting due to 1 error(s), 19 warning(s)\n'
module ram_128_16 (input wire clk, reset, wr, input wire [6:0] addr, input wire [15:0] din, output wire [15:0] dout);
  reg [0:127] ram [15:0];

  initial begin
    ram[0]=16'b10xxxxx000xxxxxx;
    ram[1]=16'h01;
    ram[2]=16'b10xxxxx001xxxxxx;
    ram[3]=16'h15;
    ram[4]=16'b10xxxxx010xxxxxx;
    ram[5]=16'h01;
    ram[6]=16'b10xxxxx011xxxxxx;
    ram[7]=16'h01;
    ram[8]=16'b0000000100010011;
    ram[9]=16'b0000010010011011;
    ram[10]=16'b0000010011100100;
    ram[11]=16'b0000001001000001;
    ram[12]=16'b01xxxxxx00000101;
    ram[13]=16'b0000010000100100;
  end
  always @(wr) ram[addr]=din;
  assign dout=ram[addr];
endmodule
module ram_128_16 (input wire clk, reset, wr, input wire [6:0] addr, input wire [15:0] din, output wire [15:0] dout);

  reg [0:127] ram [15:0];

  initial begin
    ram[0]=16'b10xxxxx000xxxxxx;
    ram[1]=16'h01;
    ram[2]=16'b10xxxxx001xxxxxx;
    ram[3]=16'h15;
    ram[4]=16'b10xxxxx010xxxxxx;
    ram[5]=16'h01;
    ram[6]=16'b10xxxxx011xxxxxx;
    ram[7]=16'h01;
    ram[8]=16'b0000000100010011;
    ram[9]=16'b0000010010011011;
    ram[10]=16'b0000010011100100;
    ram[11]=16'b0000001001000001;
    ram[12]=16'b01xxxxxx00000101;
    ram[13]=16'b0000010000100100;
  end
  always @(wr) ram[addr]=din;
  assign dout=ram[addr];
endmodule