data/full_repos/permissive/513628330/Gateware/src/sndgen.v
1: b"%Error: data/full_repos/permissive/513628330/Gateware/src/sndgen.v:191: Cannot find file containing module: 'sat'\n sat #(.isz(32-4), .osz(16))\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/513628330/Gateware/src,data/full_repos/permissive/513628330/sat\n             data/full_repos/permissive/513628330/Gateware/src,data/full_repos/permissive/513628330/sat.v\n             data/full_repos/permissive/513628330/Gateware/src,data/full_repos/permissive/513628330/sat.sv\n             sat\n             sat.v\n             sat.sv\n             obj_dir/sat\n             obj_dir/sat.v\n             obj_dir/sat.sv\n%Error: data/full_repos/permissive/513628330/Gateware/src/sndgen.v:193: Cannot find file containing module: 'sat'\n sat #(.isz(32-4), .osz(16))\n ^~~\n%Error: Exiting due to 2 error(s)\n"
module pdm_enc #(
	parameter integer DSZ = 16
)(
	input clk,
	input reset,
	input clk_en,
	input signed [DSZ-1:0] data,
	output pdm
);
	wire [DSZ-1:0] ob = data ^ {1'b1,{DSZ-1{1'b0}}};
	reg  [DSZ:0] sd_acc;

	always @(posedge clk)
	begin
		if(reset)
			sd_acc <= 0;
		else if(clk_en)
			sd_acc <= {1'b0,sd_acc[DSZ-1:0]} + {1'b0,ob};
	end

	assign pdm = sd_acc[DSZ];
endmodule
module pdm_enc #(
	parameter integer DSZ = 16
)(
	input clk,
	input reset,
	input clk_en,
	input signed [DSZ-1:0] data,
	output pdm
);

	wire [DSZ-1:0] ob = data ^ {1'b1,{DSZ-1{1'b0}}};
	reg  [DSZ:0] sd_acc;

	always @(posedge clk)
	begin
		if(reset)
			sd_acc <= 0;
		else if(clk_en)
			sd_acc <= {1'b0,sd_acc[DSZ-1:0]} + {1'b0,ob};
	end

	assign pdm = sd_acc[DSZ];
endmodule