data/full_repos/permissive/502544928/arbiter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/502544928/arbiter.v:74: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                 : ... In instance arbiter\n                        port_priority[p_req_ports [i]] = i;  \n                                                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/502544928/arbiter.v:67: Operator EQ expects 32 bits on the LHS, but LHS\'s ARRAYSEL generates 3 bits.\n                                                                 : ... In instance arbiter\n               if (port_priority[p_req_ports [i]] == i) begin\n                                                  ^~\n%Error: Exiting due to 2 warning(s)\n'
module arbiter #(parameter IN_PORTS = 5, OUT_PORT_BITS = 3) (
    input  clk,
    input  reset,
 	input  [IN_PORTS - 1:0]                   requests, 
	input  [(IN_PORTS * OUT_PORT_BITS) - 1:0] req_ports, 
	output [IN_PORTS - 1:0]                   grants
);


reg   [OUT_PORT_BITS - 1: 0]   port_priority [IN_PORTS - 1:0];
reg   [IN_PORTS - 1: 0]        temp_grants; 
wire  [OUT_PORT_BITS - 1: 0]   p_req_ports [IN_PORTS - 1:0];
reg   [OUT_PORT_BITS - 1: 0] turn; 

integer i; 
genvar j;
generate
	   for (j = 0; j < IN_PORTS; j = j + 1) begin : ARB_PORTS
      		assign p_req_ports[j] = req_ports [(((j + 1) *OUT_PORT_BITS)-1) -: OUT_PORT_BITS]; 
  	   end
endgenerate 


always @ (posedge clk)
	if (reset) begin
		for (i = 0; i < IN_PORTS; i = i + 1) begin
  			port_priority  [i]  = 0;
  			temp_grants [i]     = 0;
  		end 
	end 
    else begin  
        temp_grants = 0;
    
  		for (i = 0; i < IN_PORTS; i = i + 1) begin
  			port_priority[i] = turn; 
  		end 

 	    for (i = 0; i < IN_PORTS; i = i + 1) begin


  			if (requests [i]) begin
    	          if (port_priority[p_req_ports [i]] == i) begin
    	              temp_grants[i] = 1;  
    	          end
	             else begin 
    	                 if ((p_req_ports[i] != p_req_ports[port_priority[p_req_ports [i]]]) 
  	                       | (~requests[port_priority[p_req_ports [i]]]))begin
    	                   temp_grants[i] = 1; 
    	                   port_priority[p_req_ports [i]] = i;  
    	                 end    
	             end 
	       end
 	  end 


	end




always @ (posedge clk)
     turn <= ((turn >= IN_PORTS - 1)| reset)? 0: turn + 1;




	assign grants   = temp_grants;
	 
endmodule
module arbiter #(parameter IN_PORTS = 5, OUT_PORT_BITS = 3) (
    input  clk,
    input  reset,
 	input  [IN_PORTS - 1:0]                   requests, 
	input  [(IN_PORTS * OUT_PORT_BITS) - 1:0] req_ports, 
	output [IN_PORTS - 1:0]                   grants
);



reg   [OUT_PORT_BITS - 1: 0]   port_priority [IN_PORTS - 1:0];
reg   [IN_PORTS - 1: 0]        temp_grants; 
wire  [OUT_PORT_BITS - 1: 0]   p_req_ports [IN_PORTS - 1:0];
reg   [OUT_PORT_BITS - 1: 0] turn; 

integer i; 
genvar j;
generate
	   for (j = 0; j < IN_PORTS; j = j + 1) begin : ARB_PORTS
      		assign p_req_ports[j] = req_ports [(((j + 1) *OUT_PORT_BITS)-1) -: OUT_PORT_BITS]; 
  	   end
endgenerate 


always @ (posedge clk)
	if (reset) begin
		for (i = 0; i < IN_PORTS; i = i + 1) begin
  			port_priority  [i]  = 0;
  			temp_grants [i]     = 0;
  		end 
	end 
    else begin  
        temp_grants = 0;
    
  		for (i = 0; i < IN_PORTS; i = i + 1) begin
  			port_priority[i] = turn; 
  		end 

 	    for (i = 0; i < IN_PORTS; i = i + 1) begin


  			if (requests [i]) begin
    	          if (port_priority[p_req_ports [i]] == i) begin
    	              temp_grants[i] = 1;  
    	          end
	             else begin 
    	                 if ((p_req_ports[i] != p_req_ports[port_priority[p_req_ports [i]]]) 
  	                       | (~requests[port_priority[p_req_ports [i]]]))begin
    	                   temp_grants[i] = 1; 
    	                   port_priority[p_req_ports [i]] = i;  
    	                 end    
	             end 
	       end
 	  end 


	end




always @ (posedge clk)
     turn <= ((turn >= IN_PORTS - 1)| reset)? 0: turn + 1;




	assign grants   = temp_grants;
	 
endmodule