data/full_repos/permissive/439514885/testbench/clk_generator.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/439514885/testbench/clk_generator.v:13: Unsupported: Ignoring delay on this delayed statement.\n     #5 clk = ~clk;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-INFINITELOOP: data/full_repos/permissive/439514885/testbench/clk_generator.v:12: Infinite loop (condition always true)\n                                                                                        : ... In instance clk_generator\n  forever begin\n  ^~~~~~~\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module clk_generator (
   clk
);

output clk;

reg clk;


initial begin
  clk = 0;
  forever begin
     #5 clk = ~clk;
  end
end

endmodule
module clk_generator (
   clk
);


output clk;

reg clk;


initial begin
  clk = 0;
  forever begin
     #5 clk = ~clk;
  end
end

endmodule