data/full_repos/permissive/458737381/src/verilog-parser/tests/std-7.1.6-primitives.v
data/verilator_xmls/7f97c35a-6cd4-423c-8631-4e687f564efe.xml
module driver (in, out, en);
input [3:0] in;
output [3:0] out;
input en;
bufif0 ar[3:0] (out, in, en);
endmodule
module driver (in, out, en);

input [3:0] in;
output [3:0] out;
input en;
bufif0 ar[3:0] (out, in, en);
endmodule