data/full_repos/permissive/423547971/FPGA Projects/Gray Code Counter/gray_counter.v
1: b'%Error: Cannot find file containing module: Projects/Gray\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/Gray\n             data/full_repos/permissive/423547971/FPGA/Projects/Gray.v\n             data/full_repos/permissive/423547971/FPGA/Projects/Gray.sv\n             Projects/Gray\n             Projects/Gray.v\n             Projects/Gray.sv\n             obj_dir/Projects/Gray\n             obj_dir/Projects/Gray.v\n             obj_dir/Projects/Gray.sv\n%Error: Cannot find file containing module: Code\n%Error: Cannot find file containing module: Counter,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: Counter/gray_counter.v\n%Error: Exiting due to 5 error(s)\n'
module gray_counter(
    input clk,
    input reset,
    output [2:0] o_bin,
    output [2:0] o_gray_code
    );
    

    reg [2:0] bin_counter = 0;
    
    always @(posedge clk or posedge reset)
        if(reset)
            bin_counter <= 0;
        else
            bin_counter <= bin_counter + 1;
        
    assign o_bin = bin_counter;
        


    











       


        

    assign o_gray_code[2] = bin_counter[2];
    assign o_gray_code[1] = bin_counter[2] ^ bin_counter[1];
    assign o_gray_code[0] = bin_counter[1] ^ bin_counter[0];

        
endmodule
module gray_counter(
    input clk,
    input reset,
    output [2:0] o_bin,
    output [2:0] o_gray_code
    );

    

    reg [2:0] bin_counter = 0;
    
    always @(posedge clk or posedge reset)
        if(reset)
            bin_counter <= 0;
        else
            bin_counter <= bin_counter + 1;
        
    assign o_bin = bin_counter;
        


    











       


        

    assign o_gray_code[2] = bin_counter[2];
    assign o_gray_code[1] = bin_counter[2] ^ bin_counter[1];
    assign o_gray_code[0] = bin_counter[1] ^ bin_counter[0];

        
endmodule