data/full_repos/permissive/505451992/divclk_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/505451992/divclk_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n       reset = 1;#5\n                 ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/505451992/divclk_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n       reset = 0;#5;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/divclk_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n       reset = 0;#5;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/divclk_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n      forever #5 clk=~clk;\n              ^\n%Error: data/full_repos/permissive/505451992/divclk_tb.v:33: Cannot find file containing module: \'Clock\'\n     Clock utt(.reset(reset),\n     ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/505451992,data/full_repos/permissive/505451992/Clock\n             data/full_repos/permissive/505451992,data/full_repos/permissive/505451992/Clock.v\n             data/full_repos/permissive/505451992,data/full_repos/permissive/505451992/Clock.sv\n             Clock\n             Clock.v\n             Clock.sv\n             obj_dir/Clock\n             obj_dir/Clock.v\n             obj_dir/Clock.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module divclk_tb(

    );
    
    
    reg reset;
    reg clk;
    reg[7:0] Rate;
    wire CLK_PWM;
    
     Clock utt(.reset(reset),
     .clk(clk),.Rate(Rate),.CLK_PWM(CLK_PWM));
    
      initial begin

       Rate = 10;
       reset = 1;#5
       reset = 0;#5;
       reset = 0;#5;
       end
       
      initial begin
      clk=0;
      forever #5 clk=~clk;
      end
   
    
endmodule
module divclk_tb(

    );

    
    
    reg reset;
    reg clk;
    reg[7:0] Rate;
    wire CLK_PWM;
    
     Clock utt(.reset(reset),
     .clk(clk),.Rate(Rate),.CLK_PWM(CLK_PWM));
    
      initial begin

       Rate = 10;
       reset = 1;#5
       reset = 0;#5;
       reset = 0;#5;
       end
       
      initial begin
      clk=0;
      forever #5 clk=~clk;
      end
   
    
endmodule