data/full_repos/permissive/420518472/testbenches/test_top.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_top.v:13: Unsupported: Ignoring delay on this delayed statement.\n initial while(1) #5 comm_clk = ~comm_clk;\n                  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_top.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_top.v:95: Unsupported: Ignoring delay on this delayed statement.\n  #10000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_top.v:108: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_top.v:182: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("uart_comm_tb.vcd");\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_top.v:188: Unsupported: Ignoring delay on this delayed statement.\n  #1600;\n  ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_top.v:194: syntax error, unexpected byte, expecting IDENTIFIER\n input [7:0] byte;\n             ^~~~\n%Error: data/full_repos/permissive/420518472/testbenches/test_top.v:197: syntax error, unexpected \'[\', expecting "\'{"\n  uut_rx = byte[0]; #160\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_top.v:196: Unsupported: Ignoring delay on this delayed statement.\n  uut_rx = 0;       #160\n                    ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_top.v:198: syntax error, unexpected \'[\', expecting "\'{"\n  uut_rx = byte[1]; #160;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_top.v:197: Unsupported: Ignoring delay on this delayed statement.\n  uut_rx = byte[0]; #160\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_top.v:198: Unsupported: Ignoring delay on this delayed statement.\n  uut_rx = byte[1]; #160;\n                    ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_top.v:199: syntax error, unexpected \'[\', expecting "\'{"\n  uut_rx = byte[2]; #160;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_top.v:199: Unsupported: Ignoring delay on this delayed statement.\n  uut_rx = byte[2]; #160;\n                    ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_top.v:200: syntax error, unexpected \'[\', expecting "\'{"\n  uut_rx = byte[3]; #160;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_top.v:200: Unsupported: Ignoring delay on this delayed statement.\n  uut_rx = byte[3]; #160;\n                    ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_top.v:201: syntax error, unexpected \'[\', expecting "\'{"\n  uut_rx = byte[4]; #160;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_top.v:201: Unsupported: Ignoring delay on this delayed statement.\n  uut_rx = byte[4]; #160;\n                    ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_top.v:202: syntax error, unexpected \'[\', expecting "\'{"\n  uut_rx = byte[5]; #160;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_top.v:202: Unsupported: Ignoring delay on this delayed statement.\n  uut_rx = byte[5]; #160;\n                    ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_top.v:203: syntax error, unexpected \'[\', expecting "\'{"\n  uut_rx = byte[6]; #160;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_top.v:203: Unsupported: Ignoring delay on this delayed statement.\n  uut_rx = byte[6]; #160;\n                    ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_top.v:204: syntax error, unexpected \'[\', expecting "\'{"\n  uut_rx = byte[7]; #160;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_top.v:204: Unsupported: Ignoring delay on this delayed statement.\n  uut_rx = byte[7]; #160;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_top.v:205: Unsupported: Ignoring delay on this delayed statement.\n  uut_rx = 1; #160;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_top.v:207: Unsupported: Ignoring delay on this delayed statement.\n  while (($random & 3) != 0) #10;\n                             ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_top.v:223: syntax error, unexpected byte, expecting IDENTIFIER\n output [7:0] byte;\n              ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_top.v:226: Unsupported: Ignoring delay on this delayed statement.\n  #80;\n  ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_top.v:232: syntax error, unexpected \'[\', expecting "\'{"\n  #160 byte[0] = uut_tx;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_top.v:232: Unsupported: Ignoring delay on this delayed statement.\n  #160 byte[0] = uut_tx;\n  ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_top.v:233: syntax error, unexpected \'[\', expecting "\'{"\n  #160 byte[1] = uut_tx;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_top.v:233: Unsupported: Ignoring delay on this delayed statement.\n  #160 byte[1] = uut_tx;\n  ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_top.v:234: syntax error, unexpected \'[\', expecting "\'{"\n  #160 byte[2] = uut_tx;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_top.v:234: Unsupported: Ignoring delay on this delayed statement.\n  #160 byte[2] = uut_tx;\n  ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_top.v:235: syntax error, unexpected \'[\', expecting "\'{"\n  #160 byte[3] = uut_tx;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_top.v:235: Unsupported: Ignoring delay on this delayed statement.\n  #160 byte[3] = uut_tx;\n  ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_top.v:236: syntax error, unexpected \'[\', expecting "\'{"\n  #160 byte[4] = uut_tx;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_top.v:236: Unsupported: Ignoring delay on this delayed statement.\n  #160 byte[4] = uut_tx;\n  ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_top.v:237: syntax error, unexpected \'[\', expecting "\'{"\n  #160 byte[5] = uut_tx;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_top.v:237: Unsupported: Ignoring delay on this delayed statement.\n  #160 byte[5] = uut_tx;\n  ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_top.v:238: syntax error, unexpected \'[\', expecting "\'{"\n  #160 byte[6] = uut_tx;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_top.v:238: Unsupported: Ignoring delay on this delayed statement.\n  #160 byte[6] = uut_tx;\n  ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_top.v:239: syntax error, unexpected \'[\', expecting "\'{"\n  #160 byte[7] = uut_tx;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_top.v:239: Unsupported: Ignoring delay on this delayed statement.\n  #160 byte[7] = uut_tx;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/420518472/testbenches/test_top.v:240: Unsupported: Ignoring delay on this delayed statement.\n  #160;\n  ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_top.v:251: syntax error, unexpected byte, expecting IDENTIFIER\n input [7:0] byte;\n             ^~~~\n%Error: data/full_repos/permissive/420518472/testbenches/test_top.v:252: syntax error, unexpected IDENTIFIER, expecting "\'{"\n reg [7:0] tmp;\n           ^~~\n%Error: data/full_repos/permissive/420518472/testbenches/test_top.v:256: syntax error, unexpected \')\', expecting "\'{"\n  if (tmp != byte)\n                 ^\n%Error: data/full_repos/permissive/420518472/testbenches/test_top.v:261: syntax error, unexpected end\n end\n ^~~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_top ();
	`define SIM 1


	reg comm_clk = 0;
	initial while(1) #5 comm_clk = ~comm_clk;

	reg test_passed = 0;


	reg uut_rx = 1'b1;
	wire uut_tx;
	wire [255:0] uut_midstate;
	wire [95:0] uut_data;
	wire [31:0] uut_noncemin, uut_noncemax;

	localparam baud_rate = 1;
	localparam sys_clk_freq = 16;

    top #(
		.baud_rate(baud_rate),
		.sys_clk_freq(sys_clk_freq),
        .LOOP_LOG2(5)
	) miner (
        .CLK(comm_clk),
        .RX(uut_rx),
        .TX(uut_tx)
    );


	initial
	begin
		#100;
		uart_delay;


		uart_send_byte (8'h00);
		uart_delay;


		uart_send_byte (8'h08);
		uart_send_byte (8'h00);
		uart_send_byte (8'h00);
		uart_send_byte (8'h00);
		uart_send_byte (8'hf9);
		uart_send_byte (8'hea);
		uart_send_byte (8'h98);
		uart_send_byte (8'h0a);
		uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay;
		uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay;


		uart_send_byte (8'h6);
		uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay;
		uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay;


		uart_send_byte (8'h08);
		uart_send_byte (8'h00);
		uart_send_byte (8'h00);
		uart_send_byte (8'h00);
		uart_send_byte (8'hf9);
		uart_send_byte (8'hea);
		uart_send_byte (8'h98);
		uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay;
		uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay;



		uart_send_word (32'h0200003C);
		uart_send_word (32'hFFFFFFFF);
		uart_send_word (32'h1DAC2B7B);
		uart_send_word (32'h4B1E5E4A);
		uart_send_word (32'h29AB5F49);
		uart_send_word (32'hFFFF001D);
		uart_send_word (32'hBC909A33);
		uart_send_word (32'h6358BFF0);
		uart_send_word (32'h90CCAC7D);
		uart_send_word (32'h1E59CAA8);
		uart_send_word (32'hC3C8D8E9);
		uart_send_word (32'h4F0103C8);
		uart_send_word (32'h96B18736);
		uart_send_word (32'h4719F91B);
        uart_send_word (32'h814f1577);

		uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay;
		
		#10000;
		if (test_passed)
			$display ("\n*** TEST PASSED ***\n");
		else
			$display ("TEST FAILED: Not enough output data.\n");
		$finish;
	end


	reg tmp;

	initial
	begin
		#100;


		$display ("\nExpecting PONG...");
		uart_expect_byte (8'h01);
		$display ("PASSED: PONG\n");


		$display ("Expecting INFO...");
		uart_expect_byte (8'd16);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'hde);
		uart_expect_byte (8'had);
		uart_expect_byte (8'hbe);
		uart_expect_byte (8'hef);
		uart_expect_byte (8'h13);
		uart_expect_byte (8'h37);
		uart_expect_byte (8'h0d);
		uart_expect_byte (8'h13);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		$display ("PASSED: INFO\n");


		$display ("Expecting INVALID because the length we sent is too short for any known packet...");
		uart_expect_byte (8'd08);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd01);
		uart_delay;
		uart_delay;
		uart_delay;
		uart_delay;
		$display ("PASSED: INVALID\n");


		$display ("Expecting INVALID because of not enough packets...");
		uart_expect_byte (8'd08);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd01);
		uart_delay;
		uart_delay;
		uart_delay;
		uart_delay;
		$display ("PASSED: INVALID\n");


		$display ("Expecting ACK for push job...");
        uart_expect_byte (8'h01);
		$display ("PASSED: ACK\n");

		$display ("Expecting MSG_NONCE...");

		uart_expect_byte (8'd8);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd03);
		uart_expect_byte (8'h1d);
		uart_expect_byte (8'hac);
		uart_expect_byte (8'h2b);
		uart_expect_byte (8'h7c);
		$display ("PASSED: MSG_NONCE\n");

		test_passed = 1;
	end


	initial
	begin
		$dumpfile("uart_comm_tb.vcd");
	end


	task uart_delay;
	begin
		#1600;
	end
	endtask


	task uart_send_byte;
	input [7:0] byte;
	begin
		uut_rx = 0;       #160
		uut_rx = byte[0]; #160
		uut_rx = byte[1]; #160;
		uut_rx = byte[2]; #160;
		uut_rx = byte[3]; #160;
		uut_rx = byte[4]; #160;
		uut_rx = byte[5]; #160;
		uut_rx = byte[6]; #160;
		uut_rx = byte[7]; #160;
		uut_rx = 1; #160;

		while (($random & 3) != 0) #10;
	end
	endtask


	task uart_send_word;
	input [31:0] word;
	begin
		uart_send_byte (word[7:0]);
		uart_send_byte (word[15:8]);
		uart_send_byte (word[23:16]);
		uart_send_byte (word[31:24]);
	end
	endtask

	task uart_recv_byte;
	output [7:0] byte;
	begin
		@ (negedge uut_tx);
		#80;
		if (uut_tx)
		begin
			$display ("TEST FAILED: Floating start bit on uut_tx.\n");
			$finish;
		end
		#160 byte[0] = uut_tx;
		#160 byte[1] = uut_tx;
		#160 byte[2] = uut_tx;
		#160 byte[3] = uut_tx;
		#160 byte[4] = uut_tx;
		#160 byte[5] = uut_tx;
		#160 byte[6] = uut_tx;
		#160 byte[7] = uut_tx;
		#160;
		if (~uut_tx)
		begin
			$display ("TEST FAILED: Floating stop bit on uut_tx.\n");
			$finish;
		end
	end
	endtask


	task uart_expect_byte;
	input [7:0] byte;
	reg [7:0] tmp;
	begin
		uart_recv_byte (tmp);

		if (tmp != byte)
		begin
			$display ("TEST FAILED: Expected 0x%02X got 0x%02X.", byte, tmp);
			$finish;
		end
	end
	endtask
endmodule
module test_top ();

	`define SIM 1


	reg comm_clk = 0;
	initial while(1) #5 comm_clk = ~comm_clk;

	reg test_passed = 0;


	reg uut_rx = 1'b1;
	wire uut_tx;
	wire [255:0] uut_midstate;
	wire [95:0] uut_data;
	wire [31:0] uut_noncemin, uut_noncemax;

	localparam baud_rate = 1;
	localparam sys_clk_freq = 16;

    top #(
		.baud_rate(baud_rate),
		.sys_clk_freq(sys_clk_freq),
        .LOOP_LOG2(5)
	) miner (
        .CLK(comm_clk),
        .RX(uut_rx),
        .TX(uut_tx)
    );


	initial
	begin
		#100;
		uart_delay;


		uart_send_byte (8'h00);
		uart_delay;


		uart_send_byte (8'h08);
		uart_send_byte (8'h00);
		uart_send_byte (8'h00);
		uart_send_byte (8'h00);
		uart_send_byte (8'hf9);
		uart_send_byte (8'hea);
		uart_send_byte (8'h98);
		uart_send_byte (8'h0a);
		uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay;
		uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay;


		uart_send_byte (8'h6);
		uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay;
		uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay;


		uart_send_byte (8'h08);
		uart_send_byte (8'h00);
		uart_send_byte (8'h00);
		uart_send_byte (8'h00);
		uart_send_byte (8'hf9);
		uart_send_byte (8'hea);
		uart_send_byte (8'h98);
		uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay;
		uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay;



		uart_send_word (32'h0200003C);
		uart_send_word (32'hFFFFFFFF);
		uart_send_word (32'h1DAC2B7B);
		uart_send_word (32'h4B1E5E4A);
		uart_send_word (32'h29AB5F49);
		uart_send_word (32'hFFFF001D);
		uart_send_word (32'hBC909A33);
		uart_send_word (32'h6358BFF0);
		uart_send_word (32'h90CCAC7D);
		uart_send_word (32'h1E59CAA8);
		uart_send_word (32'hC3C8D8E9);
		uart_send_word (32'h4F0103C8);
		uart_send_word (32'h96B18736);
		uart_send_word (32'h4719F91B);
        uart_send_word (32'h814f1577);

		uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay; uart_delay;
		
		#10000;
		if (test_passed)
			$display ("\n*** TEST PASSED ***\n");
		else
			$display ("TEST FAILED: Not enough output data.\n");
		$finish;
	end


	reg tmp;

	initial
	begin
		#100;


		$display ("\nExpecting PONG...");
		uart_expect_byte (8'h01);
		$display ("PASSED: PONG\n");


		$display ("Expecting INFO...");
		uart_expect_byte (8'd16);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'hde);
		uart_expect_byte (8'had);
		uart_expect_byte (8'hbe);
		uart_expect_byte (8'hef);
		uart_expect_byte (8'h13);
		uart_expect_byte (8'h37);
		uart_expect_byte (8'h0d);
		uart_expect_byte (8'h13);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		$display ("PASSED: INFO\n");


		$display ("Expecting INVALID because the length we sent is too short for any known packet...");
		uart_expect_byte (8'd08);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd01);
		uart_delay;
		uart_delay;
		uart_delay;
		uart_delay;
		$display ("PASSED: INVALID\n");


		$display ("Expecting INVALID because of not enough packets...");
		uart_expect_byte (8'd08);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd01);
		uart_delay;
		uart_delay;
		uart_delay;
		uart_delay;
		$display ("PASSED: INVALID\n");


		$display ("Expecting ACK for push job...");
        uart_expect_byte (8'h01);
		$display ("PASSED: ACK\n");

		$display ("Expecting MSG_NONCE...");

		uart_expect_byte (8'd8);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd00);
		uart_expect_byte (8'd03);
		uart_expect_byte (8'h1d);
		uart_expect_byte (8'hac);
		uart_expect_byte (8'h2b);
		uart_expect_byte (8'h7c);
		$display ("PASSED: MSG_NONCE\n");

		test_passed = 1;
	end


	initial
	begin
		$dumpfile("uart_comm_tb.vcd");
	end


	task uart_delay;
	begin
		#1600;
	end
	endtask


	task uart_send_byte;
	input [7:0] byte;
	begin
		uut_rx = 0;       #160
		uut_rx = byte[0]; #160
		uut_rx = byte[1]; #160;
		uut_rx = byte[2]; #160;
		uut_rx = byte[3]; #160;
		uut_rx = byte[4]; #160;
		uut_rx = byte[5]; #160;
		uut_rx = byte[6]; #160;
		uut_rx = byte[7]; #160;
		uut_rx = 1; #160;

		while (($random & 3) != 0) #10;
	end
	endtask


	task uart_send_word;
	input [31:0] word;
	begin
		uart_send_byte (word[7:0]);
		uart_send_byte (word[15:8]);
		uart_send_byte (word[23:16]);
		uart_send_byte (word[31:24]);
	end
	endtask

	task uart_recv_byte;
	output [7:0] byte;
	begin
		@ (negedge uut_tx);
		#80;
		if (uut_tx)
		begin
			$display ("TEST FAILED: Floating start bit on uut_tx.\n");
			$finish;
		end
		#160 byte[0] = uut_tx;
		#160 byte[1] = uut_tx;
		#160 byte[2] = uut_tx;
		#160 byte[3] = uut_tx;
		#160 byte[4] = uut_tx;
		#160 byte[5] = uut_tx;
		#160 byte[6] = uut_tx;
		#160 byte[7] = uut_tx;
		#160;
		if (~uut_tx)
		begin
			$display ("TEST FAILED: Floating stop bit on uut_tx.\n");
			$finish;
		end
	end
	endtask


	task uart_expect_byte;
	input [7:0] byte;
	reg [7:0] tmp;
	begin
		uart_recv_byte (tmp);

		if (tmp != byte)
		begin
			$display ("TEST FAILED: Expected 0x%02X got 0x%02X.", byte, tmp);
			$finish;
		end
	end
	endtask
endmodule