data/full_repos/permissive/531257706/src/LFSRmod.v
data/verilator_xmls/38266ae0-d40e-440f-b742-f3d7729d93d1.xml
module LFSRmod (CLOCK, RESET, ENABLE, OUTDATA);
	input wire CLOCK, RESET, ENABLE;
	output reg [4:0] OUTDATA;

	reg value;
	reg [18:0] out;

	always @(*) begin
		value = ~(out[18] ^ out[5] ^ out[1] ^ out[0]);
		OUTDATA = out[18:14];
	end

	always @(posedge CLOCK) begin
		if (RESET) begin
			out <= 19'h1;
		end

		else begin
			if(ENABLE)
			begin
				out[18:0] <= { value , out[18:1] };
			end
		end
	end
endmodule
module LFSRmod (CLOCK, RESET, ENABLE, OUTDATA);

	input wire CLOCK, RESET, ENABLE;
	output reg [4:0] OUTDATA;

	reg value;
	reg [18:0] out;

	always @(*) begin
		value = ~(out[18] ^ out[5] ^ out[1] ^ out[0]);
		OUTDATA = out[18:14];
	end

	always @(posedge CLOCK) begin
		if (RESET) begin
			out <= 19'h1;
		end

		else begin
			if(ENABLE)
			begin
				out[18:0] <= { value , out[18:1] };
			end
		end
	end
endmodule