data/full_repos/permissive/406831108/CRC_16_Generator.v
1: b'%Error: data/full_repos/permissive/406831108/CRC_16_Generator.v:38: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("dump.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/406831108/CRC_16_Generator.v:39: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(1);\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/406831108/CRC_16_Generator.v:41: Unsupported: Ignoring delay on this delayed statement.\nforever #5 clk=~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/406831108/CRC_16_Generator.v:43: Unsupported: fork statements\ninitial fork\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/406831108/CRC_16_Generator.v:45: Unsupported: Ignoring delay on this delayed statement.\n#10 start=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/406831108/CRC_16_Generator.v:46: Unsupported: Ignoring delay on this delayed statement.\n#20 start=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/406831108/CRC_16_Generator.v:47: Unsupported: Ignoring delay on this delayed statement.\n#20 x=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/406831108/CRC_16_Generator.v:48: Unsupported: Ignoring delay on this delayed statement.\n#80 x=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/406831108/CRC_16_Generator.v:49: Unsupported: Ignoring delay on this delayed statement.\n#100 x=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/406831108/CRC_16_Generator.v:50: Unsupported: Ignoring delay on this delayed statement.\n#170 x=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/406831108/CRC_16_Generator.v:51: Unsupported: Ignoring delay on this delayed statement.\n#180 x=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/406831108/CRC_16_Generator.v:52: Unsupported: Ignoring delay on this delayed statement.\n#240 x=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/406831108/CRC_16_Generator.v:53: Unsupported: Ignoring delay on this delayed statement.\n#250 x=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/406831108/CRC_16_Generator.v:54: Unsupported: Ignoring delay on this delayed statement.\n#320 x=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/406831108/CRC_16_Generator.v:55: Unsupported: Ignoring delay on this delayed statement.\n#340 $finish;\n^\n%Error: Exiting due to 3 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;
reg x;
reg clk,start;
wire [15:0]r;
wire done;
crc_16 uut(x,clk,start,r,done);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
clk=0;
forever #5 clk=~clk;
end
initial fork
start=0;
#10 start=1;
#20 start=0;
#20 x=0;
#80 x=1;
#100 x=0;
#170 x=1;
#180 x=0;
#240 x=1;
#250 x=0;
#320 x=1;
#340 $finish;
join
endmodule
module test;

reg x;
reg clk,start;
wire [15:0]r;
wire done;
crc_16 uut(x,clk,start,r,done);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
clk=0;
forever #5 clk=~clk;
end
initial fork
start=0;
#10 start=1;
#20 start=0;
#20 x=0;
#80 x=1;
#100 x=0;
#170 x=1;
#180 x=0;
#240 x=1;
#250 x=0;
#320 x=1;
#340 $finish;
join
endmodule