data/full_repos/permissive/498662723/Verilog Language/Modules Hierarchy/module cseladd.v
1: b'%Error: Cannot find file containing module: Language/Modules\n        ... Looked in:\n             data/full_repos/permissive/498662723/Verilog/Language/Modules\n             data/full_repos/permissive/498662723/Verilog/Language/Modules.v\n             data/full_repos/permissive/498662723/Verilog/Language/Modules.sv\n             Language/Modules\n             Language/Modules.v\n             Language/Modules.sv\n             obj_dir/Language/Modules\n             obj_dir/Language/Modules.v\n             obj_dir/Language/Modules.sv\n%Error: Cannot find file containing module: Hierarchy,data/full_repos/permissive/498662723\n%Error: Cannot find file containing module: data/full_repos/permissive/498662723/Verilog\n%Error: Cannot find file containing module: Hierarchy/module\n%Error: Cannot find file containing module: cseladd.v\n%Error: Exiting due to 5 error(s)\n'
module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    wire [15:0] sumh1, sumh2;
    wire c1,c2, c3;
    add16 adder1 (a[15:0], b[15:0], 1'b0, sum[15:0], c3);
    add16 adder2 (a[31:16], b[31:16], 1'b0, sumh1, c1);
    add16 adder3 (a[31:16], b[31:16], 1'b1, sumh2, c2);
    
    always @ (*)
        begin
            case(c3)
                1'b0: sum[31:16] = sumh1;
                1'b1: sum[31:16] = sumh2;
            endcase
        end 
    

endmodule
module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);

    wire [15:0] sumh1, sumh2;
    wire c1,c2, c3;
    add16 adder1 (a[15:0], b[15:0], 1'b0, sum[15:0], c3);
    add16 adder2 (a[31:16], b[31:16], 1'b0, sumh1, c1);
    add16 adder3 (a[31:16], b[31:16], 1'b1, sumh2, c2);
    
    always @ (*)
        begin
            case(c3)
                1'b0: sum[31:16] = sumh1;
                1'b1: sum[31:16] = sumh2;
            endcase
        end 
    

endmodule