data/full_repos/permissive/473363095/display_and_drop.v
data/verilator_xmls/446f444f-23c3-4f11-973f-648a9eb729d3.xml
module display_and_drop(
	output [6:0] seven_seg1, 
   output [6:0] seven_seg2,
   output [6:0] seven_seg3,
   output [6:0] seven_seg4,
   output [0:0] drop_activated,
   input [15:0] t_act,
   input [15:0] t_lim,
   input drop_en
   );
	
	reg [6:0] seven_seg1_aux;
	reg [6:0] seven_seg2_aux;
	reg [6:0] seven_seg3_aux;
	reg [6:0] seven_seg4_aux;
	reg drop_aux;
	
	always@(*) begin
			

		if(t_act < t_lim && drop_en == 0) begin
			seven_seg1_aux = 7'b011_1001;
			seven_seg2_aux = 7'b101_1100;
			seven_seg3_aux = 7'b011_1000;
			seven_seg4_aux = 7'b101_1110;
			drop_aux = 0;
		end
		

		if(t_act < t_lim && drop_en == 1) begin
			seven_seg1_aux = 7'b101_1110;
			seven_seg2_aux = 7'b101_0000;
			seven_seg3_aux = 7'b101_1100;
			seven_seg4_aux = 7'b111_0011;
			drop_aux = 1;
		end
				

		if(t_act > t_lim && drop_en == 1) begin
			seven_seg1_aux = 7'b000_0000;
			seven_seg2_aux = 7'b111_0110;
			seven_seg3_aux = 7'b101_1100;
			seven_seg4_aux = 7'b111_1000;
			drop_aux = 0;
		end
		
    end
	

    assign seven_seg1 = seven_seg1_aux;
	 assign seven_seg2 = seven_seg2_aux;
	 assign seven_seg3 = seven_seg3_aux;
	 assign seven_seg4 = seven_seg4_aux;
	 assign drop_activated = drop_aux;

endmodule
module display_and_drop(
	output [6:0] seven_seg1, 
   output [6:0] seven_seg2,
   output [6:0] seven_seg3,
   output [6:0] seven_seg4,
   output [0:0] drop_activated,
   input [15:0] t_act,
   input [15:0] t_lim,
   input drop_en
   );

	
	reg [6:0] seven_seg1_aux;
	reg [6:0] seven_seg2_aux;
	reg [6:0] seven_seg3_aux;
	reg [6:0] seven_seg4_aux;
	reg drop_aux;
	
	always@(*) begin
			

		if(t_act < t_lim && drop_en == 0) begin
			seven_seg1_aux = 7'b011_1001;
			seven_seg2_aux = 7'b101_1100;
			seven_seg3_aux = 7'b011_1000;
			seven_seg4_aux = 7'b101_1110;
			drop_aux = 0;
		end
		

		if(t_act < t_lim && drop_en == 1) begin
			seven_seg1_aux = 7'b101_1110;
			seven_seg2_aux = 7'b101_0000;
			seven_seg3_aux = 7'b101_1100;
			seven_seg4_aux = 7'b111_0011;
			drop_aux = 1;
		end
				

		if(t_act > t_lim && drop_en == 1) begin
			seven_seg1_aux = 7'b000_0000;
			seven_seg2_aux = 7'b111_0110;
			seven_seg3_aux = 7'b101_1100;
			seven_seg4_aux = 7'b111_1000;
			drop_aux = 0;
		end
		
    end
	

    assign seven_seg1 = seven_seg1_aux;
	 assign seven_seg2 = seven_seg2_aux;
	 assign seven_seg3 = seven_seg3_aux;
	 assign seven_seg4 = seven_seg4_aux;
	 assign drop_activated = drop_aux;

endmodule