data/full_repos/permissive/457911422/Master.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/457911422/Master.v:7: Little bit endian vector: MSB < LSB of bit range: 0:2\noutput reg [0:2] CS,\n           ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Master (
input wire clk, reset, start,
input wire[1:0] slaveSelect,
input wire [7:0] masterDataToSend,
output reg [7:0] masterDataReceived,
output wire sclk,
output reg [0:2] CS,
output reg MOSI,
input wire MISO
);

reg [7:0] Register;

assign sclk = clk;

reg transmit = 0;

integer maxCount = 0;

always @(posedge start or posedge reset) begin
if (!transmit && start) begin
	Register <= masterDataToSend;
	masterDataReceived <= 8'bxxxxxxxx;
	maxCount <= 0;
	transmit <= 1;
	if (slaveSelect == 0) begin
		CS <= 3'b011;
	end
	else if (slaveSelect == 1) begin
		CS <= 3'b101;
	end
	else if (slaveSelect == 2) begin
		CS <= 3'b110;
	end
	else begin
		CS <= 3'b111;
	end
end
if (reset) begin
	Register <= 0;
end
end

always @(posedge clk)
begin
if (transmit) begin
	Register <= Register >> 1;
	MOSI <= Register[0];
end
end

always @(negedge clk)
begin
if (maxCount >= 7) begin
	transmit <= 0;
	CS <= 3'b111;
end
if (transmit) begin
	Register[7] <= MISO;
	masterDataReceived <= {MISO, masterDataReceived[7:1]};
	maxCount <= maxCount + 1;
end
end
endmodule
module Master (
input wire clk, reset, start,
input wire[1:0] slaveSelect,
input wire [7:0] masterDataToSend,
output reg [7:0] masterDataReceived,
output wire sclk,
output reg [0:2] CS,
output reg MOSI,
input wire MISO
);


reg [7:0] Register;

assign sclk = clk;

reg transmit = 0;

integer maxCount = 0;

always @(posedge start or posedge reset) begin
if (!transmit && start) begin
	Register <= masterDataToSend;
	masterDataReceived <= 8'bxxxxxxxx;
	maxCount <= 0;
	transmit <= 1;
	if (slaveSelect == 0) begin
		CS <= 3'b011;
	end
	else if (slaveSelect == 1) begin
		CS <= 3'b101;
	end
	else if (slaveSelect == 2) begin
		CS <= 3'b110;
	end
	else begin
		CS <= 3'b111;
	end
end
if (reset) begin
	Register <= 0;
end
end

always @(posedge clk)
begin
if (transmit) begin
	Register <= Register >> 1;
	MOSI <= Register[0];
end
end

always @(negedge clk)
begin
if (maxCount >= 7) begin
	transmit <= 0;
	CS <= 3'b111;
end
if (transmit) begin
	Register[7] <= MISO;
	masterDataReceived <= {MISO, masterDataReceived[7:1]};
	maxCount <= maxCount + 1;
end
end
endmodule