data/full_repos/permissive/491990249/verilog/rtl/user_project_wrapper.v
1: b"%Error: data/full_repos/permissive/491990249/verilog/rtl/user_project_wrapper.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/491990249/verilog/rtl/user_project_wrapper.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/491990249/verilog/rtl/user_project_wrapper.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/491990249/verilog/rtl/user_project_wrapper.v:72: Define or directive not defined: '`MPRJ_IO_PADS'\n    inout [`MPRJ_IO_PADS-10:0] analog_io,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/491990249/verilog/rtl/user_project_wrapper.v:95: Define or directive not defined: '`MPRJ_IO_PADS'\nassign io_out = {{(`MPRJ_IO_PADS-2){1'b0}}, tx, 1'b0};\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/491990249/verilog/rtl/user_project_wrapper.v:96: Define or directive not defined: '`MPRJ_IO_PADS'\nassign io_oeb = {(`MPRJ_IO_PADS){wb_rst_i}};\n                  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/491990249/verilog/rtl/user_project_wrapper.v:96: syntax error, unexpected ')', expecting TYPE-IDENTIFIER\nassign io_oeb = {(`MPRJ_IO_PADS){wb_rst_i}};\n                               ^\n%Error: Exiting due to 7 error(s)\n"
module user_project_wrapper #(
    parameter BITS = 32
) (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,





    inout [`MPRJ_IO_PADS-10:0] analog_io,


    input   user_clock2,


    output [2:0] user_irq
);




wire rx;
wire tx;


assign wbs_ack_o = wbs_stb_i;

assign wbs_dat_o = {(32){1'b0}};

assign la_data_out = {(128){1'b0}};

assign rx = io_in[0];
assign io_out = {{(`MPRJ_IO_PADS-2){1'b0}}, tx, 1'b0};
assign io_oeb = {(`MPRJ_IO_PADS){wb_rst_i}};

assign user_irq = 3'b000;

leaf_chip mprj (
    .clk(wb_clk_i),
    .reset(wb_rst_i),
    .rx(rx),
    .tx(tx)
);

endmodule
module user_project_wrapper #(
    parameter BITS = 32
) (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,





    inout [`MPRJ_IO_PADS-10:0] analog_io,


    input   user_clock2,


    output [2:0] user_irq
);





wire rx;
wire tx;


assign wbs_ack_o = wbs_stb_i;

assign wbs_dat_o = {(32){1'b0}};

assign la_data_out = {(128){1'b0}};

assign rx = io_in[0];
assign io_out = {{(`MPRJ_IO_PADS-2){1'b0}}, tx, 1'b0};
assign io_oeb = {(`MPRJ_IO_PADS){wb_rst_i}};

assign user_irq = 3'b000;

leaf_chip mprj (
    .clk(wb_clk_i),
    .reset(wb_rst_i),
    .rx(rx),
    .tx(tx)
);

endmodule