data/full_repos/permissive/476728999/Final/cheatsuccess_tb.v
1: b'%Error: data/full_repos/permissive/476728999/Final/cheatsuccess_tb.v:3: Cannot find include file: scp_079.v\n`include "scp_079.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/476728999/Final,data/full_repos/permissive/476728999/scp_079.v\n             data/full_repos/permissive/476728999/Final,data/full_repos/permissive/476728999/scp_079.v.v\n             data/full_repos/permissive/476728999/Final,data/full_repos/permissive/476728999/scp_079.v.sv\n             scp_079.v\n             scp_079.v.v\n             scp_079.v.sv\n             obj_dir/scp_079.v\n             obj_dir/scp_079.v.v\n             obj_dir/scp_079.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Final/cheatsuccess_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #500 clock = 0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Final/cheatsuccess_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #500 clock = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Final/cheatsuccess_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #40000 green = 0; red = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/476728999/Final/cheatsuccess_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #12000 green = 1; red = 0;\n        ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n'
module allok_tb();

    reg green, yellow, red, clock;
    wire a1, a2, a3, cheat_out;
    wire [2:0] state;
    wire [5:0] timer;
    

    scp_079 UUT(.clock(clock), .green(green), .yellow(yellow), .red(red), .state(state), .timer(timer), .a1(a1), .a2(a2), .a3(a3), .cheat_out(cheat_out));
    

    always begin
        #500 clock = 0;
        #500 clock = 1;
    end
    
    initial begin

        clock = 1; green = 1; yellow = 0; red = 0;

        #40000 green = 0; red = 1;

        #12000 green = 1; red = 0;
        $finish;
    end
        
endmodule
module allok_tb();


    reg green, yellow, red, clock;
    wire a1, a2, a3, cheat_out;
    wire [2:0] state;
    wire [5:0] timer;
    

    scp_079 UUT(.clock(clock), .green(green), .yellow(yellow), .red(red), .state(state), .timer(timer), .a1(a1), .a2(a2), .a3(a3), .cheat_out(cheat_out));
    

    always begin
        #500 clock = 0;
        #500 clock = 1;
    end
    
    initial begin

        clock = 1; green = 1; yellow = 0; red = 0;

        #40000 green = 0; red = 1;

        #12000 green = 1; red = 0;
        $finish;
    end
        
endmodule