data/full_repos/permissive/455421905/src/fifo.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/455421905/src/fifo.v:57: Multiple top level modules\n                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                     : ... Top module \'ONE_ENTRY_FIFO\'\nmodule ONE_ENTRY_FIFO #(parameter                    FIFO_WIDTH = 64)   \n       ^~~~~~~~~~~~~~\n                                                                     : ... Top module \'TWO_ENTRY_FIFO\'\nmodule TWO_ENTRY_FIFO #(parameter                    FIFO_WIDTH = 64)   \n       ^~~~~~~~~~~~~~\n                                                                     : ... Top module \'DFIFO\'\nmodule DFIFO #(parameter                    FIFO_SIZE  =  4,   \n       ^~~~~\n                                                                     : ... Top module \'BS_FIFO\'\nmodule BS_FIFO #(parameter                    FIFO_SIZE  =  4,   \n       ^~~~~~~\n                                                                     : ... Top module \'RAM_LAYER_FIFO\'\nmodule RAM_LAYER_FIFO #(parameter                    C_LOG      = 2,   \n       ^~~~~~~~~~~~~~\n                                                                     : ... Top module \'MULTI_CHANNEL_TWOENTRY_FIFO\'\nmodule MULTI_CHANNEL_TWOENTRY_FIFO #(parameter                    C_LOG      = 2,   \n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/455421905/src/fifo.v:375: Cannot find file containing module: \'BRAM\'\n  BRAM #(C_LOG, FIFO_WIDTH, USE_IPCORE)\n  ^~~~\n        ... Looked in:\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/BRAM\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/BRAM.v\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/BRAM.sv\n             BRAM\n             BRAM.v\n             BRAM.sv\n             obj_dir/BRAM\n             obj_dir/BRAM.v\n             obj_dir/BRAM.sv\n%Error: data/full_repos/permissive/455421905/src/fifo.v:127: Cannot find file containing module: \'BRAM\'\n  BRAM #(FIFO_SIZE, FIFO_WIDTH, USE_IPCORE)\n  ^~~~\n%Error: data/full_repos/permissive/455421905/src/fifo.v:332: Cannot find file containing module: \'BRAM\'\n  BRAM #(C_LOG, FIFO_WIDTH, USE_IPCORE)\n  ^~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module MULTI_CHANNEL_ONEENTRY_FIFO #(parameter                    C_LOG      = 2,
                                     parameter                    FIFO_WIDTH = 32,
                                     parameter                    USE_IPCORE = "INTEL")
                                    (input  wire                  CLK,
                                     input  wire                  RST,
                                     input  wire                  enq,
                                     input  wire [C_LOG-1:0]      enq_idx,
                                     input  wire                  deq,
                                     input  wire [C_LOG-1:0]      deq_idx,
                                     input  wire [FIFO_WIDTH-1:0] din,
                                     output wire [FIFO_WIDTH-1:0] dot,
                                     output wire [(1<<C_LOG)-1:0] emp,
                                     output wire [(1<<C_LOG)-1:0] full);

  wire [C_LOG-1:0] raddr = deq_idx;
  wire [C_LOG-1:0] waddr = enq_idx;

  BRAM #(C_LOG, FIFO_WIDTH, USE_IPCORE)
  bram(CLK, enq, raddr, waddr, din, dot);

  reg [(1<<C_LOG)-1:0] v;

  always @(posedge CLK) begin
    if (RST) begin
      v <= 0;
    end else begin
      case ({enq, deq})
        2'b01: begin v[deq_idx] <= 0;                  end
        2'b10: begin                  v[enq_idx] <= 1; end
        2'b11: begin v[deq_idx] <= 0; v[enq_idx] <= 1; end
      endcase
    end
  end


  assign emp  = ~v;
  assign full =  v;

endmodule
module MULTI_CHANNEL_ONEENTRY_FIFO #(parameter                    C_LOG      = 2,
                                     parameter                    FIFO_WIDTH = 32,
                                     parameter                    USE_IPCORE = "INTEL")
                                    (input  wire                  CLK,
                                     input  wire                  RST,
                                     input  wire                  enq,
                                     input  wire [C_LOG-1:0]      enq_idx,
                                     input  wire                  deq,
                                     input  wire [C_LOG-1:0]      deq_idx,
                                     input  wire [FIFO_WIDTH-1:0] din,
                                     output wire [FIFO_WIDTH-1:0] dot,
                                     output wire [(1<<C_LOG)-1:0] emp,
                                     output wire [(1<<C_LOG)-1:0] full);


  wire [C_LOG-1:0] raddr = deq_idx;
  wire [C_LOG-1:0] waddr = enq_idx;

  BRAM #(C_LOG, FIFO_WIDTH, USE_IPCORE)
  bram(CLK, enq, raddr, waddr, din, dot);

  reg [(1<<C_LOG)-1:0] v;

  always @(posedge CLK) begin
    if (RST) begin
      v <= 0;
    end else begin
      case ({enq, deq})
        2'b01: begin v[deq_idx] <= 0;                  end
        2'b10: begin                  v[enq_idx] <= 1; end
        2'b11: begin v[deq_idx] <= 0; v[enq_idx] <= 1; end
      endcase
    end
  end


  assign emp  = ~v;
  assign full =  v;

endmodule