data/full_repos/permissive/434840709/USTB_digital_logic_homework/task3/GPU.v
data/verilator_xmls/b0ea9336-dc23-4d6a-aff0-79447df74a5b.xml
module GPU(
input clk3hz,
input clr,
input	disp_data_en,
input	[31:0]	datain,
output [15:0]dataBus
    );
	reg	disp_data_en_ff1=0;

    reg[31:0]msgArray;



    assign dataBus =msgArray[31:16];
	always @ (posedge clk3hz)disp_data_en_ff1<=disp_data_en;
    always @ (posedge clk3hz or negedge clr)
        if(!clr)	
			msgArray<=0;
		else if(disp_data_en_ff1&&disp_data_en==0)
            msgArray<=datain;
        else begin



			
			msgArray[31:28]<=msgArray[3:0];
            msgArray[27:0]<=msgArray[31:4];
        end
endmodule
module GPU(
input clk3hz,
input clr,
input	disp_data_en,
input	[31:0]	datain,
output [15:0]dataBus
    );

	reg	disp_data_en_ff1=0;

    reg[31:0]msgArray;



    assign dataBus =msgArray[31:16];
	always @ (posedge clk3hz)disp_data_en_ff1<=disp_data_en;
    always @ (posedge clk3hz or negedge clr)
        if(!clr)	
			msgArray<=0;
		else if(disp_data_en_ff1&&disp_data_en==0)
            msgArray<=datain;
        else begin



			
			msgArray[31:28]<=msgArray[3:0];
            msgArray[27:0]<=msgArray[31:4];
        end
endmodule