data/full_repos/permissive/416231581/sylap.srcs/sources_1/new/uart/uart.v
1: b"%Error: data/full_repos/permissive/416231581/sylap.srcs/sources_1/new/uart/uart.v:15: Cannot find file containing module: 'baud_rate_gen'\nbaud_rate_gen uart_baud(.clk_50m(clk_50m),\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/416231581/sylap.srcs/sources_1/new/uart,data/full_repos/permissive/416231581/baud_rate_gen\n             data/full_repos/permissive/416231581/sylap.srcs/sources_1/new/uart,data/full_repos/permissive/416231581/baud_rate_gen.v\n             data/full_repos/permissive/416231581/sylap.srcs/sources_1/new/uart,data/full_repos/permissive/416231581/baud_rate_gen.sv\n             baud_rate_gen\n             baud_rate_gen.v\n             baud_rate_gen.sv\n             obj_dir/baud_rate_gen\n             obj_dir/baud_rate_gen.v\n             obj_dir/baud_rate_gen.sv\n%Error: data/full_repos/permissive/416231581/sylap.srcs/sources_1/new/uart/uart.v:18: Cannot find file containing module: 'transmitter'\ntransmitter uart_tx(.din(din),\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/416231581/sylap.srcs/sources_1/new/uart/uart.v:24: Cannot find file containing module: 'receiver'\nreceiver uart_rx(.rx(rx),\n^~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module uart(input wire [7:0] din,
	    input wire wr_en,
	    input wire clk_50m,
	    output wire tx,
	    output wire tx_busy,
	    input wire rx,
	    output wire rdy,
	    input wire rdy_clr,
	    output wire [7:0] dout);

wire rxclk_en, txclk_en;

baud_rate_gen uart_baud(.clk_50m(clk_50m),
			.rxclk_en(rxclk_en),
			.txclk_en(txclk_en));
transmitter uart_tx(.din(din),
		    .wr_en(wr_en),
		    .clk_50m(clk_50m),
		    .clken(txclk_en),
		    .tx(tx),
		    .tx_busy(tx_busy));
receiver uart_rx(.rx(rx),
		 .rdy(rdy),
		 .rdy_clr(rdy_clr),
		 .clk_50m(clk_50m),
		 .clken(rxclk_en),
		 .data(dout));

endmodule
module uart(input wire [7:0] din,
	    input wire wr_en,
	    input wire clk_50m,
	    output wire tx,
	    output wire tx_busy,
	    input wire rx,
	    output wire rdy,
	    input wire rdy_clr,
	    output wire [7:0] dout);


wire rxclk_en, txclk_en;

baud_rate_gen uart_baud(.clk_50m(clk_50m),
			.rxclk_en(rxclk_en),
			.txclk_en(txclk_en));
transmitter uart_tx(.din(din),
		    .wr_en(wr_en),
		    .clk_50m(clk_50m),
		    .clken(txclk_en),
		    .tx(tx),
		    .tx_busy(tx_busy));
receiver uart_rx(.rx(rx),
		 .rdy(rdy),
		 .rdy_clr(rdy_clr),
		 .clk_50m(clk_50m),
		 .clken(rxclk_en),
		 .data(dout));

endmodule