data/full_repos/permissive/493019833/test/testcase/firrtl/FixedPointAdder/reference/FixedPointAdder.v
data/verilator_xmls/5c6ff056-7d93-46d7-901e-d87983cffb37.xml
module FixedPointAdder(
    input clock,
    input reset,
    input [15:0] io_in0,
    input [15:0] io_in1,
    output [15:0] io_out
);
    wire [16:0] _T_5;
    ADD_SIGNED #(.width(16)) s_add_1 (
        .y(_T_5),
        .a(io_in0),
        .b(io_in1)
    );
    wire [15:0] _T_6;
    TAIL #(.width(17), .n(1)) tail_2 (
        .y(_T_6),
        .in(_T_5)
    );
    wire [15:0] _T_7;
    ASSINT #(.width(16)) assint_3 (
        .y(_T_7),
        .in(_T_6)
    );
    assign io_out = _T_7;
endmodule
module FixedPointAdder(
    input clock,
    input reset,
    input [15:0] io_in0,
    input [15:0] io_in1,
    output [15:0] io_out
);

    wire [16:0] _T_5;
    ADD_SIGNED #(.width(16)) s_add_1 (
        .y(_T_5),
        .a(io_in0),
        .b(io_in1)
    );
    wire [15:0] _T_6;
    TAIL #(.width(17), .n(1)) tail_2 (
        .y(_T_6),
        .in(_T_5)
    );
    wire [15:0] _T_7;
    ASSINT #(.width(16)) assint_3 (
        .y(_T_7),
        .in(_T_6)
    );
    assign io_out = _T_7;
endmodule