data/full_repos/permissive/46224382/src/SimpleCPU/SimpleCPU_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/46224382/src/SimpleCPU/SimpleCPU_test.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #5 rst = 0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/46224382/src/SimpleCPU/SimpleCPU_test.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #50;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/46224382/src/SimpleCPU/SimpleCPU_test.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk = ~clk;\n        ^\n%Error: data/full_repos/permissive/46224382/src/SimpleCPU/SimpleCPU_test.v:9: Cannot find file containing module: \'SimpleCPU\'\n    SimpleCPU cpu(clk, rst, cur_ins);\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/46224382/src/SimpleCPU,data/full_repos/permissive/46224382/SimpleCPU\n             data/full_repos/permissive/46224382/src/SimpleCPU,data/full_repos/permissive/46224382/SimpleCPU.v\n             data/full_repos/permissive/46224382/src/SimpleCPU,data/full_repos/permissive/46224382/SimpleCPU.sv\n             SimpleCPU\n             SimpleCPU.v\n             SimpleCPU.sv\n             obj_dir/SimpleCPU\n             obj_dir/SimpleCPU.v\n             obj_dir/SimpleCPU.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module SimpleCPU_test ();
    reg clk, rst;
    reg [31:0] cur_ins;
    

    SimpleCPU cpu(clk, rst, cur_ins);
    

    initial
    begin
        clk = 0;
        rst = 1;
        cur_ins = 1;
        

        #5 rst = 0;


        #50;
        $finish;
    end


    always 
    begin 
        #5 clk = ~clk;
    end
    
endmodule
module SimpleCPU_test ();

    reg clk, rst;
    reg [31:0] cur_ins;
    

    SimpleCPU cpu(clk, rst, cur_ins);
    

    initial
    begin
        clk = 0;
        rst = 1;
        cur_ins = 1;
        

        #5 rst = 0;


        #50;
        $finish;
    end


    always 
    begin 
        #5 clk = ~clk;
    end
    
endmodule