data/full_repos/permissive/503053625/resources/verilog_source/fsm_mux_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/fsm_mux_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #ADC_CLK_HPERIOD;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/fsm_mux_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #ADC_CLK_HPERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/fsm_mux_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #TRIG_CLK_HPERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/fsm_mux_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #TRIG_CLK_HPERIOD;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/fsm_mux_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #TRIG_CLK_HPERIOD;\n  ^\n%Error: data/full_repos/permissive/503053625/resources/verilog_source/fsm_mux_tb.v:23: Cannot find file containing module: \'DAC_MUX\'\nDAC_MUX #(.DATA_WIDTH(14)) DAC_CON(.adc_clk(ADC_CLK), .DAC_SEL(DAC_SEL), .U0(U0), .U1(U1), .U0_p(U0_p), .U0_m(U0_m), .U1_p(U1_p), .U1_m(U1_m), .DAC_A_OUT(DAC_A), .DAC_B_OUT(DAC_B));\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/503053625/resources/verilog_source,data/full_repos/permissive/503053625/DAC_MUX\n             data/full_repos/permissive/503053625/resources/verilog_source,data/full_repos/permissive/503053625/DAC_MUX.v\n             data/full_repos/permissive/503053625/resources/verilog_source,data/full_repos/permissive/503053625/DAC_MUX.sv\n             DAC_MUX\n             DAC_MUX.v\n             DAC_MUX.sv\n             obj_dir/DAC_MUX\n             obj_dir/DAC_MUX.v\n             obj_dir/DAC_MUX.sv\n%Error: data/full_repos/permissive/503053625/resources/verilog_source/fsm_mux_tb.v:25: Cannot find file containing module: \'FSM\'\nFSM CON_BOX(.TRIG_IN(TRIG_IN), .adc_clk(ADC_CLK), .start(start), .FSM_ADC_COUNTER_TRIG(FSM_ADC_COUNTER_TRIG), .FSM_DAC_COUNTER_TRIG(FSM_DAC_COUNTER_TRIG), .FSM_JP_WRT(), \n^~~\n%Error: data/full_repos/permissive/503053625/resources/verilog_source/fsm_mux_tb.v:29: Cannot find file containing module: \'gen_counter\'\ngen_counter #(.COUNT_DATA_WIDTH(4), .COUNTER_TRIG_VAL(10)) ADC_SAMP_COUNTER(.clk(ADC_CLK), .rst(FSM_ADC_COUNTER_RST), .en(FSM_ADC_COUNTER_START), .f(FSM_ADC_COUNTER_TRIG));\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/503053625/resources/verilog_source/fsm_mux_tb.v:30: Cannot find file containing module: \'gen_counter\'\ngen_counter #(.COUNT_DATA_WIDTH(4), .COUNTER_TRIG_VAL(7)) DAC_SAMP_COUNTER(.clk(ADC_CLK), .rst(FSM_DAC_COUNTER_RST), .en(FSM_DAC_COUNTER_START), .f(FSM_DAC_COUNTER_TRIG));\n^~~~~~~~~~~\n%Error: Exiting due to 4 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fsm_mux_tb;

reg [13:0] U0 = 14'b00101001110110;
reg [13:0] U1 = 14'b00011101010100;
reg [13:0] U0_p = 14'b00000000000111;
reg [13:0] U0_m = 14'b11111111111001;
reg [13:0] U1_p = 14'b11111111111000;
reg [13:0] U1_m = 14'b00000000000101;

wire [13:0] DAC_A;
wire [13:0] DAC_B;

reg ADC_CLK;
wire [1:0] DAC_SEL;
reg TRIG_IN;
reg start = 1;

localparam ADC_CLK_HPERIOD = 2;
localparam TRIG_CLK_HPERIOD = 40;

DAC_MUX #(.DATA_WIDTH(14)) DAC_CON(.adc_clk(ADC_CLK), .DAC_SEL(DAC_SEL), .U0(U0), .U1(U1), .U0_p(U0_p), .U0_m(U0_m), .U1_p(U1_p), .U1_m(U1_m), .DAC_A_OUT(DAC_A), .DAC_B_OUT(DAC_B));

FSM CON_BOX(.TRIG_IN(TRIG_IN), .adc_clk(ADC_CLK), .start(start), .FSM_ADC_COUNTER_TRIG(FSM_ADC_COUNTER_TRIG), .FSM_DAC_COUNTER_TRIG(FSM_DAC_COUNTER_TRIG), .FSM_JP_WRT(), 
.FSM_JM_WRT(), .FSM_REG_RST(), .FSM_U_WRT(), .FSM_DAC_SEL(DAC_SEL), .FSM_ADC_COUNTER_START(FSM_ADC_COUNTER_START), .FSM_ADC_COUNTER_RST(FSM_ADC_COUNTER_RST),
.FSM_DAC_COUNTER_START(FSM_DAC_COUNTER_START), .FSM_DAC_COUNTER_RST(FSM_DAC_COUNTER_RST));

gen_counter #(.COUNT_DATA_WIDTH(4), .COUNTER_TRIG_VAL(10)) ADC_SAMP_COUNTER(.clk(ADC_CLK), .rst(FSM_ADC_COUNTER_RST), .en(FSM_ADC_COUNTER_START), .f(FSM_ADC_COUNTER_TRIG));
gen_counter #(.COUNT_DATA_WIDTH(4), .COUNTER_TRIG_VAL(7)) DAC_SAMP_COUNTER(.clk(ADC_CLK), .rst(FSM_DAC_COUNTER_RST), .en(FSM_DAC_COUNTER_START), .f(FSM_DAC_COUNTER_TRIG));

	always 
	begin
		ADC_CLK = 1'b0; 
		#ADC_CLK_HPERIOD;
		ADC_CLK = 1'b1;
		#ADC_CLK_HPERIOD;
	end
	always 
	begin
		TRIG_IN = 1'b0; 
		#TRIG_CLK_HPERIOD;
		TRIG_IN = 1'b1;
		#TRIG_CLK_HPERIOD;
	end

	initial
	begin
		#TRIG_CLK_HPERIOD;
		
	end
endmodule
module fsm_mux_tb;


reg [13:0] U0 = 14'b00101001110110;
reg [13:0] U1 = 14'b00011101010100;
reg [13:0] U0_p = 14'b00000000000111;
reg [13:0] U0_m = 14'b11111111111001;
reg [13:0] U1_p = 14'b11111111111000;
reg [13:0] U1_m = 14'b00000000000101;

wire [13:0] DAC_A;
wire [13:0] DAC_B;

reg ADC_CLK;
wire [1:0] DAC_SEL;
reg TRIG_IN;
reg start = 1;

localparam ADC_CLK_HPERIOD = 2;
localparam TRIG_CLK_HPERIOD = 40;

DAC_MUX #(.DATA_WIDTH(14)) DAC_CON(.adc_clk(ADC_CLK), .DAC_SEL(DAC_SEL), .U0(U0), .U1(U1), .U0_p(U0_p), .U0_m(U0_m), .U1_p(U1_p), .U1_m(U1_m), .DAC_A_OUT(DAC_A), .DAC_B_OUT(DAC_B));

FSM CON_BOX(.TRIG_IN(TRIG_IN), .adc_clk(ADC_CLK), .start(start), .FSM_ADC_COUNTER_TRIG(FSM_ADC_COUNTER_TRIG), .FSM_DAC_COUNTER_TRIG(FSM_DAC_COUNTER_TRIG), .FSM_JP_WRT(), 
.FSM_JM_WRT(), .FSM_REG_RST(), .FSM_U_WRT(), .FSM_DAC_SEL(DAC_SEL), .FSM_ADC_COUNTER_START(FSM_ADC_COUNTER_START), .FSM_ADC_COUNTER_RST(FSM_ADC_COUNTER_RST),
.FSM_DAC_COUNTER_START(FSM_DAC_COUNTER_START), .FSM_DAC_COUNTER_RST(FSM_DAC_COUNTER_RST));

gen_counter #(.COUNT_DATA_WIDTH(4), .COUNTER_TRIG_VAL(10)) ADC_SAMP_COUNTER(.clk(ADC_CLK), .rst(FSM_ADC_COUNTER_RST), .en(FSM_ADC_COUNTER_START), .f(FSM_ADC_COUNTER_TRIG));
gen_counter #(.COUNT_DATA_WIDTH(4), .COUNTER_TRIG_VAL(7)) DAC_SAMP_COUNTER(.clk(ADC_CLK), .rst(FSM_DAC_COUNTER_RST), .en(FSM_DAC_COUNTER_START), .f(FSM_DAC_COUNTER_TRIG));

	always 
	begin
		ADC_CLK = 1'b0; 
		#ADC_CLK_HPERIOD;
		ADC_CLK = 1'b1;
		#ADC_CLK_HPERIOD;
	end
	always 
	begin
		TRIG_IN = 1'b0; 
		#TRIG_CLK_HPERIOD;
		TRIG_IN = 1'b1;
		#TRIG_CLK_HPERIOD;
	end

	initial
	begin
		#TRIG_CLK_HPERIOD;
		
	end
endmodule