data/full_repos/permissive/482975152/PipelinedProcessor.srcs/sources_1/new/RF.v
data/verilator_xmls/291f804d-8948-4188-ac00-a93168936f55.xml
module RF(
    input clk,
    input RFWE,
    input [4:0] RFRA1,
    input [4:0] RFRA2,
    input [4:0] RFWA,
    input [31:0] RFWD,
    output [31:0] RFRD1,
    output [31:0] RFRD2
    );
    
    reg [31:0] Registers [31:0];
    

    initial begin 

        Registers[0] <= 32'h00000000;
    end
    

    assign RFRD1 = Registers[RFRA1];
    assign RFRD2 = Registers[RFRA2];
    
    always@(posedge clk) begin
        if (RFWE) begin
            Registers[RFWA] = RFWD;
        end




    end
endmodule
module RF(
    input clk,
    input RFWE,
    input [4:0] RFRA1,
    input [4:0] RFRA2,
    input [4:0] RFWA,
    input [31:0] RFWD,
    output [31:0] RFRD1,
    output [31:0] RFRD2
    );

    
    reg [31:0] Registers [31:0];
    

    initial begin 

        Registers[0] <= 32'h00000000;
    end
    

    assign RFRD1 = Registers[RFRA1];
    assign RFRD2 = Registers[RFRA2];
    
    always@(posedge clk) begin
        if (RFWE) begin
            Registers[RFWA] = RFWD;
        end




    end
endmodule