data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/plic/rtl/plic_arb_ctrl.v
1: b'%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/plic/rtl/plic_arb_ctrl.v:143: Cannot find file containing module: \'gated_clk_cell\'\ngated_clk_cell  x_arb_ctrl_ready_gateclk (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/plic/rtl,data/full_repos/permissive/418752214/gated_clk_cell\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/plic/rtl,data/full_repos/permissive/418752214/gated_clk_cell.v\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/plic/rtl,data/full_repos/permissive/418752214/gated_clk_cell.sv\n             gated_clk_cell\n             gated_clk_cell.v\n             gated_clk_cell.sv\n             obj_dir/gated_clk_cell\n             obj_dir/gated_clk_cell.v\n             obj_dir/gated_clk_cell.sv\n%Warning-WIDTH: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/plic/rtl/plic_arb_ctrl.v:195: Operator EQ expects 32 or 11 bits on the LHS, but LHS\'s SEL generates 5 bits.\n                                                                                                          : ... In instance plic_arb_ctrl\nassign arb_end   = arb_round[RD_BIT-1:0] == (RD_NUM-1);\n                                         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
function automatic integer clog2(input integer a);
begin
  for(clog2=32'd0;a>0;clog2=clog2+32'd1)
  begin
    a = a>>>1;
  end
end
endfunction
function automatic integer clog2(input integer a);

begin
  for(clog2=32'd0;a>0;clog2=clog2+32'd1)
  begin
    a = a>>>1;
  end
end
endfunction