data/full_repos/permissive/513398397/verilog/inst_mem.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/513398397/verilog/inst_mem.v:150: Multiple top level modules\n                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                              : ... Top module \'inst_mem\'\nmodule inst_mem(\n       ^~~~~~~~\n                                                                              : ... Top module \'dff_1b\'\nmodule dff_1b(\n       ^~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module dff_1b(
    output reg [31:0] Q, 
    input  [31:0] D, 
    input  clk, rst, wen, select
);

always @ (posedge clk) begin
    if (rst) begin
        Q <= 32'b0;
    end
    else if (select) begin
        if (wen) begin
            Q <= D;
        end
    end
end

endmodule
module dff_1b(
    output reg [31:0] Q, 
    input  [31:0] D, 
    input  clk, rst, wen, select
);


always @ (posedge clk) begin
    if (rst) begin
        Q <= 32'b0;
    end
    else if (select) begin
        if (wen) begin
            Q <= D;
        end
    end
end

endmodule