data/full_repos/permissive/452215364/rtl/opl2/operator/calc_phase_inc.v
1: b'%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/calc_phase_inc.v:52: Cannot find include file: opl3.vh\n`include "opl3.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/452215364/rtl/opl2/operator,data/full_repos/permissive/452215364/opl3.vh\n             data/full_repos/permissive/452215364/rtl/opl2/operator,data/full_repos/permissive/452215364/opl3.vh.v\n             data/full_repos/permissive/452215364/rtl/opl2/operator,data/full_repos/permissive/452215364/opl3.vh.sv\n             opl3.vh\n             opl3.vh.v\n             opl3.vh.sv\n             obj_dir/opl3.vh\n             obj_dir/opl3.vh.v\n             obj_dir/opl3.vh.sv\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/calc_phase_inc.v:58: Define or directive not defined: \'`REG_FNUM_WIDTH\'\n    input wire [`REG_FNUM_WIDTH-1:0] fnum,\n                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/calc_phase_inc.v:59: Define or directive not defined: \'`REG_MULT_WIDTH\'\n    input wire [`REG_MULT_WIDTH-1:0] mult,\n                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/calc_phase_inc.v:60: Define or directive not defined: \'`REG_BLOCK_WIDTH\'\n    input wire [`REG_BLOCK_WIDTH-1:0] block,\n                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/calc_phase_inc.v:63: Define or directive not defined: \'`PHASE_ACC_WIDTH\'\n    output reg signed [`PHASE_ACC_WIDTH-1:0] phase_inc\n                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/calc_phase_inc.v:65: Define or directive not defined: \'`PHASE_ACC_WIDTH\'\n    wire signed [`PHASE_ACC_WIDTH-1:0] pre_mult;\n                 ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/calc_phase_inc.v:66: Define or directive not defined: \'`PHASE_ACC_WIDTH\'\n    reg signed [`PHASE_ACC_WIDTH-1:0] post_mult;\n                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/calc_phase_inc.v:68: Define or directive not defined: \'`REG_FNUM_WIDTH\'\n    wire signed [`REG_FNUM_WIDTH-1:0] vib_val;\n                 ^~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n'
module calc_phase_inc (
    input wire clk,
    input wire reset,
    input wire sample_clk_en,     
    input wire [`REG_FNUM_WIDTH-1:0] fnum,
    input wire [`REG_MULT_WIDTH-1:0] mult,
    input wire [`REG_BLOCK_WIDTH-1:0] block,
    input wire vib,
    input wire dvb,
    output reg signed [`PHASE_ACC_WIDTH-1:0] phase_inc
);   
    wire signed [`PHASE_ACC_WIDTH-1:0] pre_mult;
    reg signed [`PHASE_ACC_WIDTH-1:0] post_mult;
    
    wire signed [`REG_FNUM_WIDTH-1:0] vib_val;
    
    assign pre_mult = fnum << block;

    reg signed [4:0] pre_mult_adj;
    always @(*) begin
        case (mult)
        'h0: pre_mult_adj <= 1;
        'h1: pre_mult_adj <= 1;
        'h2: pre_mult_adj <= 2;
        'h3: pre_mult_adj <= 3;
        'h4: pre_mult_adj <= 4;
        'h5: pre_mult_adj <= 5;
        'h6: pre_mult_adj <= 6;
        'h7: pre_mult_adj <= 7;
        'h8: pre_mult_adj <= 8;
        'h9: pre_mult_adj <= 9;
        'hA: pre_mult_adj <= 10;
        'hB: pre_mult_adj <= 10;
        'hC: pre_mult_adj <= 12;
        'hD: pre_mult_adj <= 12;
        'hE: pre_mult_adj <= 15;
        'hF: pre_mult_adj <= 15;
        default: pre_mult_adj <= 1;
        endcase
    end

    always @(posedge clk)
        if (reset)
            post_mult <= 0;
        else
            case (mult)
            'h0: post_mult <= pre_mult >> 1;
            default: post_mult <= pre_mult * pre_mult_adj;
            endcase
    
    always @ *
        if (vib)
            phase_inc = post_mult + vib_val;
        else
            phase_inc = post_mult;
    

    vibrato vibrato (
        .clk(clk),
        .reset(reset),
        .sample_clk_en(sample_clk_en),
        .fnum(fnum),
        .dvb(dvb),
        .vib_val(vib_val)
    );
endmodule
module calc_phase_inc (
    input wire clk,
    input wire reset,
    input wire sample_clk_en,     
    input wire [`REG_FNUM_WIDTH-1:0] fnum,
    input wire [`REG_MULT_WIDTH-1:0] mult,
    input wire [`REG_BLOCK_WIDTH-1:0] block,
    input wire vib,
    input wire dvb,
    output reg signed [`PHASE_ACC_WIDTH-1:0] phase_inc
);
   
    wire signed [`PHASE_ACC_WIDTH-1:0] pre_mult;
    reg signed [`PHASE_ACC_WIDTH-1:0] post_mult;
    
    wire signed [`REG_FNUM_WIDTH-1:0] vib_val;
    
    assign pre_mult = fnum << block;

    reg signed [4:0] pre_mult_adj;
    always @(*) begin
        case (mult)
        'h0: pre_mult_adj <= 1;
        'h1: pre_mult_adj <= 1;
        'h2: pre_mult_adj <= 2;
        'h3: pre_mult_adj <= 3;
        'h4: pre_mult_adj <= 4;
        'h5: pre_mult_adj <= 5;
        'h6: pre_mult_adj <= 6;
        'h7: pre_mult_adj <= 7;
        'h8: pre_mult_adj <= 8;
        'h9: pre_mult_adj <= 9;
        'hA: pre_mult_adj <= 10;
        'hB: pre_mult_adj <= 10;
        'hC: pre_mult_adj <= 12;
        'hD: pre_mult_adj <= 12;
        'hE: pre_mult_adj <= 15;
        'hF: pre_mult_adj <= 15;
        default: pre_mult_adj <= 1;
        endcase
    end

    always @(posedge clk)
        if (reset)
            post_mult <= 0;
        else
            case (mult)
            'h0: post_mult <= pre_mult >> 1;
            default: post_mult <= pre_mult * pre_mult_adj;
            endcase
    
    always @ *
        if (vib)
            phase_inc = post_mult + vib_val;
        else
            phase_inc = post_mult;
    

    vibrato vibrato (
        .clk(clk),
        .reset(reset),
        .sample_clk_en(sample_clk_en),
        .fnum(fnum),
        .dvb(dvb),
        .vib_val(vib_val)
    );
endmodule