data/full_repos/permissive/515256171/code_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/515256171/code_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n    forever #(1000000000/2) clk=~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/515256171/code_tb.v:39: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile(" Controller.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/515256171/code_tb.v:40: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, Controller);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/515256171/code_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #1000000000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515256171/code_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #1000000000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515256171/code_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #(1000000000*200);\n    ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Controller;

reg clk,rst;
wire [2:0]light_M1;
wire [2:0]light_S;
wire [2:0]light_MT;
wire [2:0]light_M2;
Traffic_Light_Controller dut(.clk(clk) , .rst(rst) , .light_M1(light_M1) , .light_S(light_S)  ,.light_M2(light_M2),.light_MT(light_MT)   );
initial
begin
    clk=1'b0;
    forever #(1000000000/2) clk=~clk;
end


initial
begin
    $dumpfile(" Controller.vcd");
    $dumpvars(0, Controller);
    rst=0;
    #1000000000;
    rst=1;
    #1000000000;
    rst=0;
    #(1000000000*200);
    $finish;
    end




endmodule
module Controller;


reg clk,rst;
wire [2:0]light_M1;
wire [2:0]light_S;
wire [2:0]light_MT;
wire [2:0]light_M2;
Traffic_Light_Controller dut(.clk(clk) , .rst(rst) , .light_M1(light_M1) , .light_S(light_S)  ,.light_M2(light_M2),.light_MT(light_MT)   );
initial
begin
    clk=1'b0;
    forever #(1000000000/2) clk=~clk;
end


initial
begin
    $dumpfile(" Controller.vcd");
    $dumpvars(0, Controller);
    rst=0;
    #1000000000;
    rst=1;
    #1000000000;
    rst=0;
    #(1000000000*200);
    $finish;
    end




endmodule