data/full_repos/permissive/508935683/Verilog/dct_top.v
1: b"%Error: data/full_repos/permissive/508935683/Verilog/dct_top.v:17: Cannot find file containing module: 'dct_1d'\ndct_1d DCT1D(dct_1d_out, tp_1d_enb, dct_data_in_reg, clk, rst, enb);\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/508935683/Verilog,data/full_repos/permissive/508935683/dct_1d\n             data/full_repos/permissive/508935683/Verilog,data/full_repos/permissive/508935683/dct_1d.v\n             data/full_repos/permissive/508935683/Verilog,data/full_repos/permissive/508935683/dct_1d.sv\n             dct_1d\n             dct_1d.v\n             dct_1d.sv\n             obj_dir/dct_1d\n             obj_dir/dct_1d.v\n             obj_dir/dct_1d.sv\n%Error: data/full_repos/permissive/508935683/Verilog/dct_top.v:18: Cannot find file containing module: 'tp_mem'\ntp_mem #(.BW(10)) TP1D(tp_1d_out, dct_2d_enb, dct_1d_out, clk, rst, tp_1d_enb);\n^~~~~~\n%Error: data/full_repos/permissive/508935683/Verilog/dct_top.v:20: Cannot find file containing module: 'dct_2d'\ndct_2d DCT2D(dct_2d_out, tp_2d_enb, tp_1d_out, clk, rst, dct_2d_enb);\n^~~~~~\n%Error: data/full_repos/permissive/508935683/Verilog/dct_top.v:21: Cannot find file containing module: 'tp_mem'\ntp_mem #(.BW(12)) TP2D(tp_2d_out, dct_fin_enb, dct_2d_out, clk, rst, tp_2d_enb);\n^~~~~~\n%Error: Exiting due to 4 error(s)\n"
module dct_top(
    output [11:0] dct_data_out,
    input  [7:0]  dct_data_in,
    input  clk, rst, enb
);

parameter BWo1d = 10;
parameter BWo2d = 12;

reg [7:0] dct_data_in_reg;

wire [BWo1d-1:0] dct_1d_out, tp_1d_out;
wire [BWo2d-1:0] dct_2d_out, tp_2d_out;
wire tp_1d_enb, tp_2d_enb;
wire dct_2d_enb, dct_fin_enb;

dct_1d DCT1D(dct_1d_out, tp_1d_enb, dct_data_in_reg, clk, rst, enb);
tp_mem #(.BW(10)) TP1D(tp_1d_out, dct_2d_enb, dct_1d_out, clk, rst, tp_1d_enb);

dct_2d DCT2D(dct_2d_out, tp_2d_enb, tp_1d_out, clk, rst, dct_2d_enb);
tp_mem #(.BW(12)) TP2D(tp_2d_out, dct_fin_enb, dct_2d_out, clk, rst, tp_2d_enb);

assign dct_data_out = tp_2d_out;

always @ (posedge clk) begin
    if (rst) begin
        dct_data_in_reg <= 8'b0;
    end
    else begin
        dct_data_in_reg <= dct_data_in;
    end
end

endmodule
module dct_top(
    output [11:0] dct_data_out,
    input  [7:0]  dct_data_in,
    input  clk, rst, enb
);


parameter BWo1d = 10;
parameter BWo2d = 12;

reg [7:0] dct_data_in_reg;

wire [BWo1d-1:0] dct_1d_out, tp_1d_out;
wire [BWo2d-1:0] dct_2d_out, tp_2d_out;
wire tp_1d_enb, tp_2d_enb;
wire dct_2d_enb, dct_fin_enb;

dct_1d DCT1D(dct_1d_out, tp_1d_enb, dct_data_in_reg, clk, rst, enb);
tp_mem #(.BW(10)) TP1D(tp_1d_out, dct_2d_enb, dct_1d_out, clk, rst, tp_1d_enb);

dct_2d DCT2D(dct_2d_out, tp_2d_enb, tp_1d_out, clk, rst, dct_2d_enb);
tp_mem #(.BW(12)) TP2D(tp_2d_out, dct_fin_enb, dct_2d_out, clk, rst, tp_2d_enb);

assign dct_data_out = tp_2d_out;

always @ (posedge clk) begin
    if (rst) begin
        dct_data_in_reg <= 8'b0;
    end
    else begin
        dct_data_in_reg <= dct_data_in;
    end
end

endmodule