data/full_repos/permissive/441359809/src/yosys/tests/simple/attrib04_net_var.v
data/verilator_xmls/597f6bb1-2721-412c-9312-ab3f1b40fb9b.xml
module foo(clk, rst, inp, out);
  input  wire clk;
  input  wire rst;
  input  wire inp;
  output wire out;

  bar bar_instance (clk, rst, inp, out);
endmodule
module foo(clk, rst, inp, out);

  input  wire clk;
  input  wire rst;
  input  wire inp;
  output wire out;

  bar bar_instance (clk, rst, inp, out);
endmodule