data/full_repos/permissive/441359809/src/yosys/manual/PRESENTATION_ExOth/scrambler.v
data/verilator_xmls/3500db7c-302f-4792-a1f2-8b3c00f9d681.xml
module scrambler(
        input clk, rst, in_bit,
        output reg out_bit
);
    reg [31:0] xs;
    always @(posedge clk) begin
    	if (rst)
	    xs = 1;
        xs = xs ^ (xs << 13);
        xs = xs ^ (xs >> 17);
        xs = xs ^ (xs << 5);
        out_bit <= in_bit ^ xs[0];
    end
endmodule
module scrambler(
        input clk, rst, in_bit,
        output reg out_bit
);

    reg [31:0] xs;
    always @(posedge clk) begin
    	if (rst)
	    xs = 1;
        xs = xs ^ (xs << 13);
        xs = xs ^ (xs >> 17);
        xs = xs ^ (xs << 5);
        out_bit <= in_bit ^ xs[0];
    end
endmodule