data/full_repos/permissive/52714256/INTERFACES/src/sandbox.v
1: b"%Error: data/full_repos/permissive/52714256/INTERFACES/src/sandbox.v:58: Cannot find file containing module: 'SPI'\n    SPI #(.m(15), .Tbit(100)) spi\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/52714256/INTERFACES/src,data/full_repos/permissive/52714256/SPI\n             data/full_repos/permissive/52714256/INTERFACES/src,data/full_repos/permissive/52714256/SPI.v\n             data/full_repos/permissive/52714256/INTERFACES/src,data/full_repos/permissive/52714256/SPI.sv\n             SPI\n             SPI.v\n             SPI.sv\n             obj_dir/SPI\n             obj_dir/SPI.v\n             obj_dir/SPI.sv\n%Error: Exiting due to 1 error(s)\n"
module sandbox
    (
    output wire [127:0] OLED_S0,
    output wire [127:0] OLED_S1,
    output wire [127:0] OLED_S2,
    output wire [127:0] OLED_S3,
    input wire GCLK,
    output wire [7:0] LD,
    input wire [7:0] SW,
    output wire [7:0] JA,
    input wire [7:0] JB,
    input wire BTNC,
    input wire BTND,
    input wire BTNL,
    input wire BTNR,
    input wire BTNU
    );
    
    wire MISO;
    wire MOSI;
    wire SS;
    wire SCLK;
    
    reg SS_REG = 1'b0;
    reg SCLK_REG = 1'b0;
    assign JA[2] = SS_REG;
    assign JA[3] = SCLK_REG;
    
    always @(posedge GCLK) begin
        SS_REG <= SS;
        SCLK_REG <= SCLK;
    end
    

   
    SPI #(.m(15), .Tbit(100)) spi
        (

        .str0(OLED_S0),
        .str1(OLED_S1),
        .str2(OLED_S2),
        .str3(OLED_S3),
        .GCLK(GCLK),
        .RST(BTND),
        .SW(SW),

        .st(BTNC),



        .MASTER_SS(SS),
        .MASTER_SCLK(SCLK),
        .MASTER_MISO(JB[0]),
        .MASTER_MOSI(JA[1]),





        .SLAVE_SS(SS),
        .SLAVE_SCLK(SCLK),
        .SLAVE_MOSI(JB[1]),
        .SLAVE_MISO(JA[0])


        );

endmodule
module sandbox
    (
    output wire [127:0] OLED_S0,
    output wire [127:0] OLED_S1,
    output wire [127:0] OLED_S2,
    output wire [127:0] OLED_S3,
    input wire GCLK,
    output wire [7:0] LD,
    input wire [7:0] SW,
    output wire [7:0] JA,
    input wire [7:0] JB,
    input wire BTNC,
    input wire BTND,
    input wire BTNL,
    input wire BTNR,
    input wire BTNU
    );

    
    wire MISO;
    wire MOSI;
    wire SS;
    wire SCLK;
    
    reg SS_REG = 1'b0;
    reg SCLK_REG = 1'b0;
    assign JA[2] = SS_REG;
    assign JA[3] = SCLK_REG;
    
    always @(posedge GCLK) begin
        SS_REG <= SS;
        SCLK_REG <= SCLK;
    end
    

   
    SPI #(.m(15), .Tbit(100)) spi
        (

        .str0(OLED_S0),
        .str1(OLED_S1),
        .str2(OLED_S2),
        .str3(OLED_S3),
        .GCLK(GCLK),
        .RST(BTND),
        .SW(SW),

        .st(BTNC),



        .MASTER_SS(SS),
        .MASTER_SCLK(SCLK),
        .MASTER_MISO(JB[0]),
        .MASTER_MOSI(JA[1]),





        .SLAVE_SS(SS),
        .SLAVE_SCLK(SCLK),
        .SLAVE_MOSI(JB[1]),
        .SLAVE_MISO(JA[0])


        );

endmodule