data/full_repos/permissive/47765321/divider.v
data/verilator_xmls/812fadfa-7dfa-4243-9816-f51066bdb158.xml
module divider
(
	input  wire rst_n,
	input  wire clk,
	output wire en100hz
);

reg [16:0] r_cnt;

always @(posedge clk or negedge rst_n) begin
	if(~rst_n)
		r_cnt <= 17'd0;
	else begin
		if(en100hz)
			r_cnt <= 17'd0;
		else
			r_cnt <= r_cnt + 17'd1;
	end
end

assign en100hz = (r_cnt == 17'd99_999);

endmodule
module divider
(
	input  wire rst_n,
	input  wire clk,
	output wire en100hz
);


reg [16:0] r_cnt;

always @(posedge clk or negedge rst_n) begin
	if(~rst_n)
		r_cnt <= 17'd0;
	else begin
		if(en100hz)
			r_cnt <= 17'd0;
		else
			r_cnt <= r_cnt + 17'd1;
	end
end

assign en100hz = (r_cnt == 17'd99_999);

endmodule