data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/gen/gen_adder_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/gen/gen_adder_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #H_period;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/gen/gen_adder_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #H_period;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/gen/gen_adder_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #F_period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/gen/gen_adder_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #F_period;\n        ^\n%Error: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/gen/gen_adder_tb.v:18: Cannot find file containing module: \'gen_adder\'\ngen_adder #(\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/gen,data/full_repos/permissive/503053625/gen_adder\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/gen,data/full_repos/permissive/503053625/gen_adder.v\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/gen,data/full_repos/permissive/503053625/gen_adder.sv\n             gen_adder\n             gen_adder.v\n             gen_adder.sv\n             obj_dir/gen_adder\n             obj_dir/gen_adder.v\n             obj_dir/gen_adder.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module gen_adder_tb;
localparam NUM_SAMPS = 10;
localparam F_period=4;
localparam H_period=F_period/2;
localparam IN_WIDTH = 32;
localparam  ON = 1'b1;
localparam  OFF = 1'b0;

reg  ADC_CLK = OFF;
reg	 [IN_WIDTH - 1	: 0] A = {IN_WIDTH{1'b0}};
reg  [IN_WIDTH - 1	: 0] B = {IN_WIDTH{1'b0}};
wire [IN_WIDTH  	: 0] SUM;

gen_adder #(
	.IN_WIDTH(IN_WIDTH)
) ADD0 (
	.a(A),
	.b(B),
	.s(SUM)
);

always begin
    ADC_CLK = OFF;
    #H_period;
    ADC_CLK = ON;
    #H_period;
end
initial
begin
    repeat(NUM_SAMPS) begin
        #F_period;
        A = $random;
        #F_period;
        B = $random;
    end
    $finish;
end

endmodule
module gen_adder_tb;

localparam NUM_SAMPS = 10;
localparam F_period=4;
localparam H_period=F_period/2;
localparam IN_WIDTH = 32;
localparam  ON = 1'b1;
localparam  OFF = 1'b0;

reg  ADC_CLK = OFF;
reg	 [IN_WIDTH - 1	: 0] A = {IN_WIDTH{1'b0}};
reg  [IN_WIDTH - 1	: 0] B = {IN_WIDTH{1'b0}};
wire [IN_WIDTH  	: 0] SUM;

gen_adder #(
	.IN_WIDTH(IN_WIDTH)
) ADD0 (
	.a(A),
	.b(B),
	.s(SUM)
);

always begin
    ADC_CLK = OFF;
    #H_period;
    ADC_CLK = ON;
    #H_period;
end
initial
begin
    repeat(NUM_SAMPS) begin
        #F_period;
        A = $random;
        #F_period;
        B = $random;
    end
    $finish;
end

endmodule