data/full_repos/permissive/422421961/lib/tb/write_enable_signal.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/422421961/lib/tb/write_enable_signal.v:43: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/422421961/lib/tb/write_enable_signal.v:78: Unsupported: Ignoring delay on this delayed statement.\n          #delay $display("Write %s[%d] is %d",signal_NAME,index,signal_out);\n          ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module write_enable_signal
#(
parameter signal_WIDTH=10,
parameter FILENAME="./pat/dfai.dat",
parameter signal_NAME="DATA",
parameter repeat_time=1,
parameter delay=2,
parameter display_OK=0
)
(
input clk,
input enable,
input signed [signal_WIDTH-1:0] signal_out
);

integer signal_FILE,signal_FILE1; 
integer index=0;
reg signal_isNotFirstRise = 0;
reg signal_isSimulationEnd= 0;
reg signed [signal_WIDTH-1:0] tmp_sig_I;
	
	initial
	begin
  $display("writing: %s....",FILENAME);
	#`DLY_1;
  signal_FILE = $fopen(FILENAME,"wb");
  signal_FILE1 = $fopen(signal_NAME,"wb");
  if (signal_FILE ==0||signal_FILE1==0)
    begin
      $display("Error at opening file: %s or  %s",FILENAME,signal_NAME);
      $stop;
    end
  else
  	$display("writing %s .........",FILENAME);
  end

  always @(posedge clk) begin
    signal_isNotFirstRise <=  #`DLY_1 1;
  end

reg [9:0] cnt=0;  
always @(posedge clk)
  if(enable) begin
    if(cnt==repeat_time-1)
      cnt<=0;
    else 
      cnt<=cnt+1;
  end



  always@(posedge clk) 
  begin 
    if(signal_isNotFirstRise) begin
      if(enable&&cnt==repeat_time-1)
      begin
          $fwrite(signal_FILE, "%s[%d] is %d\n",signal_NAME,index,signal_out);
          $fwrite(signal_FILE1, "%d\n",signal_out);
      	  if(display_OK)begin
	         #delay	$display("Write %s[%d] is %d",signal_NAME,index,signal_out);
          end
          index<=index+1;
 	    end
    end
  end


endmodule
module write_enable_signal
#(
parameter signal_WIDTH=10,
parameter FILENAME="./pat/dfai.dat",
parameter signal_NAME="DATA",
parameter repeat_time=1,
parameter delay=2,
parameter display_OK=0
)
(
input clk,
input enable,
input signed [signal_WIDTH-1:0] signal_out
);


integer signal_FILE,signal_FILE1; 
integer index=0;
reg signal_isNotFirstRise = 0;
reg signal_isSimulationEnd= 0;
reg signed [signal_WIDTH-1:0] tmp_sig_I;
	
	initial
	begin
  $display("writing: %s....",FILENAME);
	#`DLY_1;
  signal_FILE = $fopen(FILENAME,"wb");
  signal_FILE1 = $fopen(signal_NAME,"wb");
  if (signal_FILE ==0||signal_FILE1==0)
    begin
      $display("Error at opening file: %s or  %s",FILENAME,signal_NAME);
      $stop;
    end
  else
  	$display("writing %s .........",FILENAME);
  end

  always @(posedge clk) begin
    signal_isNotFirstRise <=  #`DLY_1 1;
  end

reg [9:0] cnt=0;  
always @(posedge clk)
  if(enable) begin
    if(cnt==repeat_time-1)
      cnt<=0;
    else 
      cnt<=cnt+1;
  end



  always@(posedge clk) 
  begin 
    if(signal_isNotFirstRise) begin
      if(enable&&cnt==repeat_time-1)
      begin
          $fwrite(signal_FILE, "%s[%d] is %d\n",signal_NAME,index,signal_out);
          $fwrite(signal_FILE1, "%d\n",signal_out);
      	  if(display_OK)begin
	         #delay	$display("Write %s[%d] is %d",signal_NAME,index,signal_out);
          end
          index<=index+1;
 	    end
    end
  end


endmodule