data/full_repos/permissive/449807379/CPU_design/programCounter.v
data/verilator_xmls/1bdf2910-d235-4420-af68-5bb035469e82.xml
module programCounter( cycle, rst, out);
input cycle;
input rst;
output reg [7:0] out;


always@(cycle)
begin
if (!rst)
	out = 8'b0;

else
	out = out+8'b1;

end

endmodule
module programCounter( cycle, rst, out);

input cycle;
input rst;
output reg [7:0] out;


always@(cycle)
begin
if (!rst)
	out = 8'b0;

else
	out = out+8'b1;

end

endmodule