data/full_repos/permissive/421663164/foss/frontend/exp1/pgate/wb_host.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/421663164/foss/frontend/exp1/pgate/wb_host.sv:152: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                            : ... In instance wb_host\n  reg_out [31:0] = 8\'d0;\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module wb_host (

`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


       input   logic               wbm_rst_i        ,
       input   logic               wbm_clk_i        ,
       input   logic               wbm_cyc_i        ,
       input   logic               wbm_stb_i        ,
       input   logic [31:0]        wbm_adr_i        ,
       input   logic               wbm_we_i         ,
       input   logic [31:0]        wbm_dat_i        ,
       input   logic [3:0]         wbm_sel_i        ,
       output  logic [31:0]        wbm_dat_o        ,
       output  logic               wbm_ack_o        ,
       output  logic               wbm_err_o


    );






logic               wbm_rst_n;
logic [2:0]         sw_addr    ;
logic               sw_wr_en   ;
logic [31:0]        reg_rdata  ;
logic [31:0]        reg_out    ;
logic               reg_ack    ;
logic               sw_wr_en_0;
logic               sw_wr_en_1;
logic [31:0]        reg_0;
logic [31:0]        reg_1;



assign wbm_rst_n = !wbm_rst_i;



logic wb_req;
logic wb_req_d;
always_ff @(negedge wbm_rst_n or posedge wbm_clk_i) begin
    if ( wbm_rst_n == 1'b0 ) begin
        wb_req     <= '0;
        wb_req_d   <= '0;
   end else begin
       wb_req   <= wbm_stb_i && (wbm_ack_o == 0) ;
       wb_req_d <= wb_req;
   end
end


assign  wbm_dat_o   = (wb_req) ? reg_rdata  : 'h0;
assign  wbm_ack_o   = (wb_req) ? reg_ack   : 'h0;
assign  wbm_err_o   = (wb_req) ? 1'b0      : 'h0;

assign sw_addr       = wbm_adr_i [4:2];
assign sw_wr_en      = wb_req & wbm_we_i;

assign  sw_wr_en_0 = sw_wr_en && (sw_addr=='h0);
assign  sw_wr_en_1 = sw_wr_en && (sw_addr=='h1);



always @ (posedge wbm_clk_i or negedge wbm_rst_n)
begin 
   if (wbm_rst_n == 1'b0) begin
      reg_rdata  <= 'h0;
      reg_ack    <= 1'b0;
   end else if (wb_req && !reg_ack) begin
      reg_rdata <= reg_out ;
      reg_ack   <= 1'b1;
   end else begin
      reg_ack        <= 1'b0;
   end
end



always @( *)
begin 
  reg_out [31:0] = 8'd0;

  case (sw_addr [2:0])
    3'b000 :   reg_out [31:0] = reg_0;
    3'b001 :   reg_out [31:0] = reg_1;
    default : reg_out [31:0] = 'h0;
  endcase
end

always @ (posedge wbm_clk_i or negedge wbm_rst_n)
begin 
   if (wbm_rst_n == 1'b0) begin
      reg_0      <= 'h0;
      reg_1      <= 'h0;
   end else begin
     if(sw_wr_en_0)
       reg_0    <= wbm_dat_i;
     if(sw_wr_en_1)
       reg_1    <= wbm_dat_i;
   end
end




endmodule
module wb_host (

`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


       input   logic               wbm_rst_i        ,
       input   logic               wbm_clk_i        ,
       input   logic               wbm_cyc_i        ,
       input   logic               wbm_stb_i        ,
       input   logic [31:0]        wbm_adr_i        ,
       input   logic               wbm_we_i         ,
       input   logic [31:0]        wbm_dat_i        ,
       input   logic [3:0]         wbm_sel_i        ,
       output  logic [31:0]        wbm_dat_o        ,
       output  logic               wbm_ack_o        ,
       output  logic               wbm_err_o


    );







logic               wbm_rst_n;
logic [2:0]         sw_addr    ;
logic               sw_wr_en   ;
logic [31:0]        reg_rdata  ;
logic [31:0]        reg_out    ;
logic               reg_ack    ;
logic               sw_wr_en_0;
logic               sw_wr_en_1;
logic [31:0]        reg_0;
logic [31:0]        reg_1;



assign wbm_rst_n = !wbm_rst_i;



logic wb_req;
logic wb_req_d;
always_ff @(negedge wbm_rst_n or posedge wbm_clk_i) begin
    if ( wbm_rst_n == 1'b0 ) begin
        wb_req     <= '0;
        wb_req_d   <= '0;
   end else begin
       wb_req   <= wbm_stb_i && (wbm_ack_o == 0) ;
       wb_req_d <= wb_req;
   end
end


assign  wbm_dat_o   = (wb_req) ? reg_rdata  : 'h0;
assign  wbm_ack_o   = (wb_req) ? reg_ack   : 'h0;
assign  wbm_err_o   = (wb_req) ? 1'b0      : 'h0;

assign sw_addr       = wbm_adr_i [4:2];
assign sw_wr_en      = wb_req & wbm_we_i;

assign  sw_wr_en_0 = sw_wr_en && (sw_addr=='h0);
assign  sw_wr_en_1 = sw_wr_en && (sw_addr=='h1);



always @ (posedge wbm_clk_i or negedge wbm_rst_n)
begin 
   if (wbm_rst_n == 1'b0) begin
      reg_rdata  <= 'h0;
      reg_ack    <= 1'b0;
   end else if (wb_req && !reg_ack) begin
      reg_rdata <= reg_out ;
      reg_ack   <= 1'b1;
   end else begin
      reg_ack        <= 1'b0;
   end
end



always @( *)
begin 
  reg_out [31:0] = 8'd0;

  case (sw_addr [2:0])
    3'b000 :   reg_out [31:0] = reg_0;
    3'b001 :   reg_out [31:0] = reg_1;
    default : reg_out [31:0] = 'h0;
  endcase
end

always @ (posedge wbm_clk_i or negedge wbm_rst_n)
begin 
   if (wbm_rst_n == 1'b0) begin
      reg_0      <= 'h0;
      reg_1      <= 'h0;
   end else begin
     if(sw_wr_en_0)
       reg_0    <= wbm_dat_i;
     if(sw_wr_en_1)
       reg_1    <= wbm_dat_i;
   end
end




endmodule