data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/flit_counter.v
data/verilator_xmls/c17be698-a194-4e09-9053-a1d7ea4553e1.xml
module flit_counter #(
    parameter   CNT_SIZE    = 48
)
(
    input   wire                    clk_i,
    input   wire                    reset_q_i,

    input   wire                    cnt_en_i,
    input   wire                    cnt_rst_i,
    output  wire    [CNT_SIZE-1:0]  cnt_data_o
);



    reg     [CNT_SIZE-1:0]  r_cnt;
    reg     [CNT_SIZE-1:0]  rin_cnt;





    always @(posedge clk_i, negedge reset_q_i) begin: cnt_low_reg
        if (reset_q_i == 1'b0) begin
            r_cnt   <= {CNT_SIZE{1'b0}};
        end else begin
            r_cnt   <= rin_cnt;
        end
    end
    always @* begin: cnt_low_logic
        if (cnt_rst_i == 1'b1) begin
            rin_cnt = {CNT_SIZE{1'b0}};
        end else if (cnt_en_i == 1'b1) begin
            rin_cnt = r_cnt + 1;
        end else begin
            rin_cnt = r_cnt;
        end
    end


    assign cnt_data_o       = r_cnt;


endmodule
module flit_counter #(
    parameter   CNT_SIZE    = 48
)
(
    input   wire                    clk_i,
    input   wire                    reset_q_i,

    input   wire                    cnt_en_i,
    input   wire                    cnt_rst_i,
    output  wire    [CNT_SIZE-1:0]  cnt_data_o
);




    reg     [CNT_SIZE-1:0]  r_cnt;
    reg     [CNT_SIZE-1:0]  rin_cnt;





    always @(posedge clk_i, negedge reset_q_i) begin: cnt_low_reg
        if (reset_q_i == 1'b0) begin
            r_cnt   <= {CNT_SIZE{1'b0}};
        end else begin
            r_cnt   <= rin_cnt;
        end
    end
    always @* begin: cnt_low_logic
        if (cnt_rst_i == 1'b1) begin
            rin_cnt = {CNT_SIZE{1'b0}};
        end else if (cnt_en_i == 1'b1) begin
            rin_cnt = r_cnt + 1;
        end else begin
            rin_cnt = r_cnt;
        end
    end


    assign cnt_data_o       = r_cnt;


endmodule