data/full_repos/permissive/509150045/src/adder.sv
data/verilator_xmls/f85728d1-0655-4771-a8cc-bf023e7fd4a2.xml
module adder(   input logic [31:0] A, B, 
                output logic [31:0] OUT );

    assign OUT = A + B;

endmodule
module adder(   input logic [31:0] A, B, 
                output logic [31:0] OUT );


    assign OUT = A + B;

endmodule