data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_zzctu_sync.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_zzctu_sync.v:61: Cannot find file containing module: 'bw_u1_soffi_4x'\n     bw_u1_soffi_4x u_I0( \n     ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_soffi_4x\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_soffi_4x.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_soffi_4x.sv\n             bw_u1_soffi_4x\n             bw_u1_soffi_4x.v\n             bw_u1_soffi_4x.sv\n             obj_dir/bw_u1_soffi_4x\n             obj_dir/bw_u1_soffi_4x.v\n             obj_dir/bw_u1_soffi_4x.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_zzctu_sync.v:80: Cannot find file containing module: 'bw_u1_soffi_4x'\n     bw_u1_soffi_4x u_I1( \n     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_zzctu_sync.v:100: Cannot find file containing module: 'bw_u1_soff_8x'\n     bw_u1_soff_8x u_I2( \n     ^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module bw_zzctu_sync (

so, out, sob,

d, si, sib, pll_out, pll_out_l, se
);


input d;
input si;
input sib;
input pll_out;
input pll_out_l;
input se;
output so;
output sob;
output out;

wire ql1, ql2;
wire so1, so2;
wire pll_out_inv;


    assign pll_out_inv = ~pll_out;


     bw_u1_soffi_4x u_I0(

			 .q_l		(ql1),
			 .so		(so),

			 .ck		(pll_out),
			 .d		(d),
			 .se		(se),
			 .sd		(si));


     bw_u1_soffi_4x u_I1(

			 .q_l		(ql2),
			 .so		(sob1),

			 .ck		(pll_out_inv),
			 .d		(ql1),
			 .se		(se),
			 .sd		(sib));



     bw_u1_soff_8x u_I2(

			.q		(out),
			.so		(sob ),

			.ck		(pll_out_l),
			.d		(ql2),
			.se		(se),
			.sd		(sob1));


endmodule
module bw_zzctu_sync (

so, out, sob,

d, si, sib, pll_out, pll_out_l, se
);



input d;
input si;
input sib;
input pll_out;
input pll_out_l;
input se;
output so;
output sob;
output out;

wire ql1, ql2;
wire so1, so2;
wire pll_out_inv;


    assign pll_out_inv = ~pll_out;


     bw_u1_soffi_4x u_I0(

			 .q_l		(ql1),
			 .so		(so),

			 .ck		(pll_out),
			 .d		(d),
			 .se		(se),
			 .sd		(si));


     bw_u1_soffi_4x u_I1(

			 .q_l		(ql2),
			 .so		(sob1),

			 .ck		(pll_out_inv),
			 .d		(ql1),
			 .se		(se),
			 .sd		(sib));



     bw_u1_soff_8x u_I2(

			.q		(out),
			.so		(sob ),

			.ck		(pll_out_l),
			.d		(ql2),
			.se		(se),
			.sd		(sob1));


endmodule