data/full_repos/permissive/458737381/src/verilog-parser/tests/fpu_cnt_lead0_lvl1.v
data/verilator_xmls/84ca0f05-e60f-48f2-b96f-9d349683f1da.xml
module fpu_cnt_lead0_lvl1 (
	din,

	din_3_0_eq_0,
	din_3_2_eq_0,
	lead0_4b_0
);


input [3:0]	din;

output		din_3_0_eq_0;
output		din_3_2_eq_0;
output		lead0_4b_0;


wire		din_3_0_eq_0;
wire		din_3_2_eq_0;
wire		lead0_4b_0;


assign din_3_0_eq_0= (!(|din[3:0]));

assign din_3_2_eq_0= (!(|din[3:2]));

assign lead0_4b_0= ((!din_3_2_eq_0) && (!din[3]))
		|| (din_3_2_eq_0 && (!din[1]));

endmodule
module fpu_cnt_lead0_lvl1 (
	din,

	din_3_0_eq_0,
	din_3_2_eq_0,
	lead0_4b_0
);



input [3:0]	din;

output		din_3_0_eq_0;
output		din_3_2_eq_0;
output		lead0_4b_0;


wire		din_3_0_eq_0;
wire		din_3_2_eq_0;
wire		lead0_4b_0;


assign din_3_0_eq_0= (!(|din[3:0]));

assign din_3_2_eq_0= (!(|din[3:2]));

assign lead0_4b_0= ((!din_3_2_eq_0) && (!din[3]))
		|| (din_3_2_eq_0 && (!din[1]));

endmodule