data/full_repos/permissive/486598419/6.5/FA.v
data/verilator_xmls/eb6f95af-49cc-4328-bddb-eb5c18b719aa.xml
module FA(
    input iA,
    input iB,
    input iC,
    output oS,
    output oC
    );
    wire tmp1;
    xor n1(tmp1,iA,iB);
    xor n2(oS,iC,tmp1);
    wire tmp2;
    wire tmp3;
    and a1(tmp2,iA,iB);
    and a2(tmp3,tmp1,iC);
    or o1(oC,tmp2,tmp3);
    
endmodule
module FA(
    input iA,
    input iB,
    input iC,
    output oS,
    output oC
    );

    wire tmp1;
    xor n1(tmp1,iA,iB);
    xor n2(oS,iC,tmp1);
    wire tmp2;
    wire tmp3;
    and a1(tmp2,iA,iB);
    and a2(tmp3,tmp1,iC);
    or o1(oC,tmp2,tmp3);
    
endmodule