data/full_repos/permissive/453280569/testbench_iverilog+gtk/tb/tb_fifo_async.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/453280569/testbench_iverilog+gtk/tb/tb_fifo_async.sv:21: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/453280569/testbench_iverilog+gtk/tb/tb_fifo_async.sv:22: Unsupported: Ignoring delay on this delayed statement.\n  forever #(5) wclk = ~wclk;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/453280569/testbench_iverilog+gtk/tb/tb_fifo_async.sv:26: Unsupported: Ignoring delay on this delayed statement.\n  #2;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/453280569/testbench_iverilog+gtk/tb/tb_fifo_async.sv:27: Unsupported: Ignoring delay on this delayed statement.\n  forever #(3) rclk = ~rclk;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/453280569/testbench_iverilog+gtk/tb/tb_fifo_async.sv:33: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/453280569/testbench_iverilog+gtk/tb/tb_fifo_async.sv:37: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/453280569/testbench_iverilog+gtk/tb/tb_fifo_async.sv:38: Unsupported: Ignoring delay on this delayed statement.\n  rst_n =\'1;#20;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/453280569/testbench_iverilog+gtk/tb/tb_fifo_async.sv:41: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/453280569/testbench_iverilog+gtk/tb/tb_fifo_async.sv:43: Unsupported: Ignoring delay on this delayed statement.\n  #400;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/453280569/testbench_iverilog+gtk/tb/tb_fifo_async.sv:46: Unsupported: Ignoring delay on this delayed statement.\n  #400;\n  ^\n%Error: data/full_repos/permissive/453280569/testbench_iverilog+gtk/tb/tb_fifo_async.sv:99: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("tb.lxt");   \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/453280569/testbench_iverilog+gtk/tb/tb_fifo_async.sv:100: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, tb_fifo_async);    \n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_fifo_async ();
	parameter DSIZE = 8;
	parameter ASIZE = 5;
	logic             rst_n;
	logic [DSIZE-1:0] wdata;
	logic             w_en;
	logic             w_full;
	logic [ASIZE-1:0] wuse;
	logic [DSIZE-1:0] rdata;
	logic             r_empty;
	logic             r_en;
	logic             r_ok;
	logic [ASIZE-1:0] ruse;

	logic wclk,rclk;
	initial begin
		wclk = '0;
		rclk = '0;
		#1;
		forever #(5) wclk = ~wclk;
	end
	initial
	begin
		#2;
		forever #(3) rclk = ~rclk;
	end


	initial
	begin
		#20;
		rst_n='0;
		w_en='0;
		r_en='0;
		#20;
		rst_n ='1;#20;
		w_en='1;
		r_en='1;
		#100;
		r_en='0;
		#400;
		w_en='0;
		r_en='1;
		#400;
		$finish;
	end
	logic [ASIZE-1:0]i;
	always @(posedge wclk) begin
		if(~rst_n) 
			i <= 0;
		else 
		begin
			i <= i+1;
			wdata <= i;
		end
	end




	fifo_async #(
			.DSIZE(DSIZE),
			.ASIZE(ASIZE)
		) inst_fifo_async (
			.rst_n   (rst_n),
			.wclk    (wclk),
			.wdata   (wdata),
			.w_en    (w_en),
			.w_full  (w_full),
			.wuse    (wuse),
			.rclk    (rclk),
			.rdata   (rdata),
			.r_empty (r_empty),
			.r_en    (r_en),
			.r_ok    (r_ok),
			.ruse    (ruse)
		);




initial	begin
    $dumpfile("tb.lxt");
    $dumpvars(0, tb_fifo_async);
end
endmodule
module tb_fifo_async ();

	parameter DSIZE = 8;
	parameter ASIZE = 5;
	logic             rst_n;
	logic [DSIZE-1:0] wdata;
	logic             w_en;
	logic             w_full;
	logic [ASIZE-1:0] wuse;
	logic [DSIZE-1:0] rdata;
	logic             r_empty;
	logic             r_en;
	logic             r_ok;
	logic [ASIZE-1:0] ruse;

	logic wclk,rclk;
	initial begin
		wclk = '0;
		rclk = '0;
		#1;
		forever #(5) wclk = ~wclk;
	end
	initial
	begin
		#2;
		forever #(3) rclk = ~rclk;
	end


	initial
	begin
		#20;
		rst_n='0;
		w_en='0;
		r_en='0;
		#20;
		rst_n ='1;#20;
		w_en='1;
		r_en='1;
		#100;
		r_en='0;
		#400;
		w_en='0;
		r_en='1;
		#400;
		$finish;
	end
	logic [ASIZE-1:0]i;
	always @(posedge wclk) begin
		if(~rst_n) 
			i <= 0;
		else 
		begin
			i <= i+1;
			wdata <= i;
		end
	end




	fifo_async #(
			.DSIZE(DSIZE),
			.ASIZE(ASIZE)
		) inst_fifo_async (
			.rst_n   (rst_n),
			.wclk    (wclk),
			.wdata   (wdata),
			.w_en    (w_en),
			.w_full  (w_full),
			.wuse    (wuse),
			.rclk    (rclk),
			.rdata   (rdata),
			.r_empty (r_empty),
			.r_en    (r_en),
			.r_ok    (r_ok),
			.ruse    (ruse)
		);




initial	begin
    $dumpfile("tb.lxt");
    $dumpvars(0, tb_fifo_async);
end
endmodule