data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/blockram.v
1: b'%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/blockram.v:47: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                                        : ... In instance blockram\n if (rst) dout <= \'hx;  \n               ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module blockram(
	clk, rst,
	enb, wen, addr, din, dout
);
parameter width = 8, depth = 10, size = 1<<depth;

input clk, rst, enb, wen;
input [depth-1:0] addr;
input [width-1:0] din;
output reg [width-1:0] dout;

reg [width-1:0] ram[0:size-1];

always @(posedge clk)
	if (rst) dout <= 'hx;
	else if (enb)
		if (wen) ram[addr] <= din;
		else dout <= ram[addr];

endmodule
module blockram(
	clk, rst,
	enb, wen, addr, din, dout
);

parameter width = 8, depth = 10, size = 1<<depth;

input clk, rst, enb, wen;
input [depth-1:0] addr;
input [width-1:0] din;
output reg [width-1:0] dout;

reg [width-1:0] ram[0:size-1];

always @(posedge clk)
	if (rst) dout <= 'hx;
	else if (enb)
		if (wen) ram[addr] <= din;
		else dout <= ram[addr];

endmodule