data/full_repos/permissive/496903659/128 lemmings1.v
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/496903659/128\n        ... Looked in:\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/128\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/128.v\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/128.sv\n             data/full_repos/permissive/496903659/128\n             data/full_repos/permissive/496903659/128.v\n             data/full_repos/permissive/496903659/128.sv\n             obj_dir/data/full_repos/permissive/496903659/128\n             obj_dir/data/full_repos/permissive/496903659/128.v\n             obj_dir/data/full_repos/permissive/496903659/128.sv\n%Error: Cannot find file containing module: lemmings1.v\n%Error: Exiting due to 2 error(s)\n'
module top_module(
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    output walk_left,
    output walk_right);


    reg state, next_state;

    always @(*) begin

        if (state)
	        if (bump_right)
		        next_state <= ~ state;
       		else
                next_state <= state;
        else
            if (bump_left)
		        next_state <= ~ state;
       		else
                next_state <= state;
    end

    always @(posedge clk, posedge areset) begin

        if (areset)
            state <= 1'b0;
        else
            state <= next_state;
    end


    assign walk_left = (state == 1'b0);
    assign walk_right = (state == 1'b1);

endmodule
module top_module(
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    output walk_left,
    output walk_right);



    reg state, next_state;

    always @(*) begin

        if (state)
	        if (bump_right)
		        next_state <= ~ state;
       		else
                next_state <= state;
        else
            if (bump_left)
		        next_state <= ~ state;
       		else
                next_state <= state;
    end

    always @(posedge clk, posedge areset) begin

        if (areset)
            state <= 1'b0;
        else
            state <= next_state;
    end


    assign walk_left = (state == 1'b0);
    assign walk_right = (state == 1'b1);

endmodule