data/full_repos/permissive/484543204/verilog/rtl/fourbit_adder.v
1: b"%Error: data/full_repos/permissive/484543204/verilog/rtl/fourbit_adder.v:14: Duplicate declaration of signal: 'y'\n                                                                           : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n    reg y;\n        ^\n        data/full_repos/permissive/484543204/verilog/rtl/fourbit_adder.v:9: ... Location of original declaration\n    output [3:0] y,\n                 ^\n%Error: Exiting due to 1 error(s)\n"
module fourbit_adder (
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif
    input  [3:0] a,
    input  [3:0] b,
    output [3:0] y,
    output [7:0] input_en,
    output [3:0] output_en,
    input clk
);
    reg y;
    always @(posedge clk) begin
        y <= a + b;
    end
    assign input_en = 8'hff;
    assign output_en = 4'b0;
endmodule
module fourbit_adder (
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif
    input  [3:0] a,
    input  [3:0] b,
    output [3:0] y,
    output [7:0] input_en,
    output [3:0] output_en,
    input clk
);

    reg y;
    always @(posedge clk) begin
        y <= a + b;
    end
    assign input_en = 8'hff;
    assign output_en = 4'b0;
endmodule