data/full_repos/permissive/525452387/core/pcreg.v
1: b'%Warning-WIDTH: data/full_repos/permissive/525452387/core/pcreg.v:17: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'4\'h4\' generates 4 bits.\n                                                                    : ... In instance pcreg\n        pc_o <= pc_o + 4\'h4;\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module pcreg(
    input wire clk,
    input wire rst_,

    input wire jump_flag_i,
    input wire[31:0] jump_addr_i,

    output reg[31:0] pc_o
);

always @ (posedge clk) begin
    if (rst_ == 1'b0) begin
        pc_o <= 32'h0;
    end else if (jump_flag_i == 1'b1) begin
        pc_o <= jump_addr_i;
    end else begin
        pc_o <= pc_o + 4'h4;
    end
end

endmodule
module pcreg(
    input wire clk,
    input wire rst_,

    input wire jump_flag_i,
    input wire[31:0] jump_addr_i,

    output reg[31:0] pc_o
);


always @ (posedge clk) begin
    if (rst_ == 1'b0) begin
        pc_o <= 32'h0;
    end else if (jump_flag_i == 1'b1) begin
        pc_o <= jump_addr_i;
    end else begin
        pc_o <= pc_o + 4'h4;
    end
end

endmodule