data/full_repos/permissive/449071180/tb_move_input.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_move_input.v:27: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_move_input.v:29: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_move_input.v:36: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_move_input.v:38: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_move_input.v:40: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_move_input.v:42: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_move_input.v:44: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_move_input.v:46: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_move_input.v:48: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_move_input.v:50: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_move_input.v:52: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_move_input.v:54: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_move_input.v:56: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_move_input.v:58: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_move_input.v:60: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_move_input.v:62: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Error: data/full_repos/permissive/449071180/tb_move_input.v:7: Cannot find file containing module: \'move_input\'\nmove_input port_map(\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/move_input\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/move_input.v\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/move_input.sv\n             move_input\n             move_input.v\n             move_input.sv\n             obj_dir/move_input\n             obj_dir/move_input.v\n             obj_dir/move_input.sv\n%Error: Exiting due to 1 error(s), 16 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_move_input();

reg left_test,right_test,up_test,down_test,reset_test,clk_test;

wire [2:0] out_test;

move_input port_map(

.left(left_test),
.right(right_test),
.up(up_test),
.down(down_test),
.reset(reset_test),
.out(out_test),
.clk(clk_test)

);


initial begin
clk_test = 0;
left_test = 0;
right_test = 0;
up_test = 0;
down_test = 0;
reset_test = 0;
#5;
reset_test = 1;
#5;
reset_test = 0;
end

always begin

left_test = 1;
#5;
clk_test = 1;
#5;
clk_test = 0;
#5;
left_test = 0;
#5;
right_test = 1;
#5;
clk_test = 1;
#5;
clk_test = 0;
#5;
right_test = 0;
#5;
up_test = 1;
#5;
clk_test = 1;
#5;
clk_test = 0;
#5;
up_test = 0;
#5;
down_test = 1;
#5;
down_test = 0;
#5;
end



endmodule
module tb_move_input();


reg left_test,right_test,up_test,down_test,reset_test,clk_test;

wire [2:0] out_test;

move_input port_map(

.left(left_test),
.right(right_test),
.up(up_test),
.down(down_test),
.reset(reset_test),
.out(out_test),
.clk(clk_test)

);


initial begin
clk_test = 0;
left_test = 0;
right_test = 0;
up_test = 0;
down_test = 0;
reset_test = 0;
#5;
reset_test = 1;
#5;
reset_test = 0;
end

always begin

left_test = 1;
#5;
clk_test = 1;
#5;
clk_test = 0;
#5;
left_test = 0;
#5;
right_test = 1;
#5;
clk_test = 1;
#5;
clk_test = 0;
#5;
right_test = 0;
#5;
up_test = 1;
#5;
clk_test = 1;
#5;
clk_test = 0;
#5;
up_test = 0;
#5;
down_test = 1;
#5;
down_test = 0;
#5;
end



endmodule