data/full_repos/permissive/503053625/resources/verilog_source/GPIO_BOX_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/GPIO_BOX_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #gap_time;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/GPIO_BOX_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #gap_time;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/GPIO_BOX_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #gap_time;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/GPIO_BOX_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #gap_time;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/GPIO_BOX_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #gap_time;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/GPIO_BOX_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #gap_time;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/GPIO_BOX_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #gap_time;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/GPIO_BOX_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #gap_time;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/GPIO_BOX_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n  #gap_time;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/resources/verilog_source/GPIO_BOX_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #gap_time;\n  ^\n%Error: data/full_repos/permissive/503053625/resources/verilog_source/GPIO_BOX_tb.v:23: Cannot find file containing module: \'GPIO_BOX\'\nGPIO_BOX #(.DAC_WIDTH(), .ADC_WIDTH(), .GPIO_WIDTH()) gp_con(.GPIO_IN(GPIO_IN), .ADC_A(ADC_A), .ADC_B(ADC_B), .JP(JP), .JM(JM), .DAC_A(DAC_A), .DAC_B(DAC_B), .U0(U0), .U1(U1), .DELTA_U0(DELTA_U0), .DELTA_U1(DELTA_U1), \n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/503053625/resources/verilog_source,data/full_repos/permissive/503053625/GPIO_BOX\n             data/full_repos/permissive/503053625/resources/verilog_source,data/full_repos/permissive/503053625/GPIO_BOX.v\n             data/full_repos/permissive/503053625/resources/verilog_source,data/full_repos/permissive/503053625/GPIO_BOX.sv\n             GPIO_BOX\n             GPIO_BOX.v\n             GPIO_BOX.sv\n             obj_dir/GPIO_BOX\n             obj_dir/GPIO_BOX.v\n             obj_dir/GPIO_BOX.sv\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module GPIO_BOX_tb;

	reg [31:0] GPIO_IN = 32'h00000000;
	reg [11:0] ADC_A = 12'h666;
	reg [11:0] ADC_B = 12'h777;
	reg [11:0] JP = 12'h222;
	reg [11:0] JM = 12'h420;
	reg [13:0] DAC_A = 14'b00_1011_1101_1011;
	reg [13:0] DAC_B = 14'b01_0101_1101_0101;
	reg [13:0] U0 = 14'b00_1110_1010_1001;
	reg [13:0] U1 = 14'b11_0101_1111_1010;
	reg [13:0] DELTA_U0 = 14'b01_1111_1010_1011;
	reg [13:0] DELTA_U1 = 14'b00_1100_1010_1011;
	reg [13:0] UP_0 = 14'b10_1010_1000_0110;
	reg [13:0] UP_1 = 14'b10_1010_1010_0001;
	reg [13:0] UM_0 = 14'b01_0110_0110_1110;
	reg [13:0] UM_1 = 14'b01_0111_0111_1101;
	reg [13:0] NEW_U0 = 14'b00_1011_1100_0011;
	reg [13:0] NEW_U1 = 14'b00_1101_1110_1011;
	wire [31:0] GPIO_OUT;

	localparam gap_time = 2;
GPIO_BOX #(.DAC_WIDTH(), .ADC_WIDTH(), .GPIO_WIDTH()) gp_con(.GPIO_IN(GPIO_IN), .ADC_A(ADC_A), .ADC_B(ADC_B), .JP(JP), .JM(JM), .DAC_A(DAC_A), .DAC_B(DAC_B), .U0(U0), .U1(U1), .DELTA_U0(DELTA_U0), .DELTA_U1(DELTA_U1), 
	.UP_0(UP_0), .UP_1(UP_1), .UM_0(UM_0), .UM_1(UM_1), .NEW_U0(NEW_U0), .NEW_U1(NEW_U1), .GPIO_OUT(GPIO_OUT));

	initial
	begin
		GPIO_IN = 32'h00000000;
		#gap_time;
		GPIO_IN = 32'h0AFAFAFA;
		#gap_time;

		GPIO_IN = 32'h14389418;
		#gap_time;
		ADC_A = 12'h320;
		ADC_B = 12'h671;
		GPIO_IN = 32'h1A5A5A5A;
		#gap_time;
		ADC_A = 12'h320;
		ADC_B = 12'h671;
		#gap_time;
		ADC_A = 12'h555;
		ADC_B = 12'h671;
		GPIO_IN = 32'h12621231;
		#gap_time;
		ADC_A = 12'h555;
		ADC_B = 12'h666;
		#gap_time;
		ADC_A = 12'h420;
		ADC_B = 12'h386;
		#gap_time;

		GPIO_IN = 32'h27776666;
		#gap_time;
		GPIO_IN = 32'h2A5A5A5A;
		DAC_A = 14'b10_0110_0110_0110;
		DAC_B = 14'b01_1101_1101_1101;
		#gap_time;

	end
endmodule
module GPIO_BOX_tb;


	reg [31:0] GPIO_IN = 32'h00000000;
	reg [11:0] ADC_A = 12'h666;
	reg [11:0] ADC_B = 12'h777;
	reg [11:0] JP = 12'h222;
	reg [11:0] JM = 12'h420;
	reg [13:0] DAC_A = 14'b00_1011_1101_1011;
	reg [13:0] DAC_B = 14'b01_0101_1101_0101;
	reg [13:0] U0 = 14'b00_1110_1010_1001;
	reg [13:0] U1 = 14'b11_0101_1111_1010;
	reg [13:0] DELTA_U0 = 14'b01_1111_1010_1011;
	reg [13:0] DELTA_U1 = 14'b00_1100_1010_1011;
	reg [13:0] UP_0 = 14'b10_1010_1000_0110;
	reg [13:0] UP_1 = 14'b10_1010_1010_0001;
	reg [13:0] UM_0 = 14'b01_0110_0110_1110;
	reg [13:0] UM_1 = 14'b01_0111_0111_1101;
	reg [13:0] NEW_U0 = 14'b00_1011_1100_0011;
	reg [13:0] NEW_U1 = 14'b00_1101_1110_1011;
	wire [31:0] GPIO_OUT;

	localparam gap_time = 2;
GPIO_BOX #(.DAC_WIDTH(), .ADC_WIDTH(), .GPIO_WIDTH()) gp_con(.GPIO_IN(GPIO_IN), .ADC_A(ADC_A), .ADC_B(ADC_B), .JP(JP), .JM(JM), .DAC_A(DAC_A), .DAC_B(DAC_B), .U0(U0), .U1(U1), .DELTA_U0(DELTA_U0), .DELTA_U1(DELTA_U1), 
	.UP_0(UP_0), .UP_1(UP_1), .UM_0(UM_0), .UM_1(UM_1), .NEW_U0(NEW_U0), .NEW_U1(NEW_U1), .GPIO_OUT(GPIO_OUT));

	initial
	begin
		GPIO_IN = 32'h00000000;
		#gap_time;
		GPIO_IN = 32'h0AFAFAFA;
		#gap_time;

		GPIO_IN = 32'h14389418;
		#gap_time;
		ADC_A = 12'h320;
		ADC_B = 12'h671;
		GPIO_IN = 32'h1A5A5A5A;
		#gap_time;
		ADC_A = 12'h320;
		ADC_B = 12'h671;
		#gap_time;
		ADC_A = 12'h555;
		ADC_B = 12'h671;
		GPIO_IN = 32'h12621231;
		#gap_time;
		ADC_A = 12'h555;
		ADC_B = 12'h666;
		#gap_time;
		ADC_A = 12'h420;
		ADC_B = 12'h386;
		#gap_time;

		GPIO_IN = 32'h27776666;
		#gap_time;
		GPIO_IN = 32'h2A5A5A5A;
		DAC_A = 14'b10_0110_0110_0110;
		DAC_B = 14'b01_1101_1101_1101;
		#gap_time;

	end
endmodule