data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v
1: b'%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:190: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h1 )? 8\'h02 : 8\'h00\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:190: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h1 )? 8\'h02 : 8\'h00\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:191: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h2 )? 8\'h04 : 8\'h00\n              ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:191: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h2 )? 8\'h04 : 8\'h00\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:192: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h3 )? 8\'h08 : 8\'h00\n              ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:192: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h3 )? 8\'h08 : 8\'h00\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:193: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h4 )? 8\'h10 : 8\'h00\n              ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:193: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h4 )? 8\'h10 : 8\'h00\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:194: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h5 )? 8\'h20 : 8\'h00\n              ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:194: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h5 )? 8\'h20 : 8\'h00\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:195: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h6 )? 8\'h40 : 8\'h00\n              ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:195: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h6 )? 8\'h40 : 8\'h00\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:196: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h7 )? 8\'h80 : 8\'h00\n              ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:196: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h7 )? 8\'h80 : 8\'h00\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:197: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h8 )? 8\'h1b : 8\'h00\n              ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:197: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h8 )? 8\'h1b : 8\'h00\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:198: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h9 )? 8\'h36 : 8\'h00;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:198: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h9 )? 8\'h36 : 8\'h00;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:232: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h8 )? 8\'h02 : 8\'h00\n               ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:232: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h8 )? 8\'h02 : 8\'h00\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:233: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h7 )? 8\'h04 : 8\'h00\n               ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:233: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h7 )? 8\'h04 : 8\'h00\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:234: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h6 )? 8\'h08 : 8\'h00\n               ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:234: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h6 )? 8\'h08 : 8\'h00\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:235: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h5 )? 8\'h10 : 8\'h00\n               ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:235: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h5 )? 8\'h10 : 8\'h00\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:236: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h4 )? 8\'h20 : 8\'h00\n               ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:236: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h4 )? 8\'h20 : 8\'h00\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:237: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h3 )? 8\'h40 : 8\'h00\n               ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:237: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h3 )? 8\'h40 : 8\'h00\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:238: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h2 )? 8\'h80 : 8\'h00\n               ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:238: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h2 )? 8\'h80 : 8\'h00\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:239: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h1 )? 8\'h1b : 8\'h00\n               ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:239: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h1 )? 8\'h1b : 8\'h00\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:240: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h0 )? 8\'h36 : 8\'h00;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:240: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h0 )? 8\'h36 : 8\'h00;\n                                    ^\n%Error: Exiting due to 36 warning(s)\n'
module aes128_table_ecb (
  input               resetn,
  input               clock,

  input               enc_dec,
  input               key_exp,
  input               start,
  output reg          key_val,
  output reg          text_val,
  input      [127:0]  key_in,
  input      [127:0]  text_in,
  output     [127:0]  text_out,
  output reg          busy
);


`define  IDLE        3'h0
`define  KEY_EXP     3'h1
`define  ROUND_LOOP  3'h2




  reg       [2:0]  now_state;
  reg       [2:0]  next_state;
  reg              start_flag;
  reg       [3:0]  round_n;


  reg      [31:0]  w[0:3];
  wire     [31:0]  rotword;
  wire      [7:0]  rcon;
  wire     [31:0]  temp;
  wire    [127:0]  next_key;
  reg     [127:0]  round10_key;


  reg      [31:0]  iw[0:3];
  wire      [7:0]  ircon;
  wire     [31:0]  itemp;
  wire     [31:0]  sword;
  wire     [31:0]  irotword;
  wire    [127:0]  next_ikey;


  reg      [31:0]  state[0:3];
  wire      [7:0]  s_box[0:3][0:3];
  wire      [7:0]  s_row[0:3][0:3];
  wire      [7:0]  m_col[0:3][0:3];
  wire    [127:0]  add_roundkey0;
  wire    [127:0]  add_roundkey;
  wire    [127:0]  cipher_text;


  reg      [31:0]  istate[0:3];
  wire      [7:0]  is_row_in[0:3][0:3];
  wire      [7:0]  is_row[0:3][0:3];
  wire      [7:0]  is_box[0:3][0:3];
  wire     [31:0]  im_col[0:3];
  wire    [127:0]  add_iroundkey0;
  wire    [127:0]  add_iroundkey;
  wire    [127:0]  plainte_text;







  always @( now_state or enc_dec or key_exp or start or start_flag or round_n or key_val ) begin
    case ( now_state )
      `IDLE       : if ( key_exp == 1'b1 ) next_state = `KEY_EXP;
                    else if ( start == 1'b1 )
                      if ( key_val == 1'b0 ) next_state = `KEY_EXP;
                      else next_state = `ROUND_LOOP;
                    else if ( start_flag == 1'b1 ) next_state = `ROUND_LOOP;
                    else next_state = `IDLE;
      `KEY_EXP    : if ( round_n == 4'd10 ) next_state = `IDLE;
                    else next_state = `KEY_EXP;
      `ROUND_LOOP : if ( round_n == 4'd10 ) next_state = `IDLE;
                    else next_state = `ROUND_LOOP;
       default    : next_state = `IDLE;
    endcase
  end

  always @(posedge clock or negedge resetn) begin
    if ( resetn == 1'b0 ) now_state <= `IDLE;
    else now_state <= next_state;
  end





  always @(posedge clock or negedge resetn) begin
    if ( resetn == 1'b0 ) begin
      busy <= 1'b0;
      start_flag <= 1'b0;
      key_val <= 1'b0;
      round_n <= 4'h0;
      key_val <= 1'b0;
      text_val <= 1'b0;
    end
    else begin

      if (( key_exp == 1'b1 ) || ( start == 1'b1 )) busy <= 1'b1;
      else if (( now_state == `KEY_EXP ) && ( round_n == 4'd10 ) && ( start_flag != 1'b1 )) busy <= 1'b0;
      else if (( now_state == `ROUND_LOOP ) && ( round_n == 4'd10 )) busy <= 1'b0;
      else busy <= busy;


      if ( start == 1'b1 ) start_flag <= 1'b1;
      else if ( now_state == `ROUND_LOOP ) start_flag <= 1'b0;
      else start_flag <= start_flag;


      if ( next_state == `IDLE ) round_n <= 4'h0;
      else round_n <= round_n + 1'b1;


      if ( key_exp == 1'b1 ) key_val <= 1'b0;
      else if (( now_state == `KEY_EXP ) && ( round_n == 4'd10 )) key_val <= 1'b1;
      else key_val <= key_val;


      if (( now_state == `ROUND_LOOP ) && ( round_n == 4'd10 )) text_val <= 1'b1;
      else text_val <= 1'b0;
    end
  end


  assign text_out = ( enc_dec == 1'b0 )? { state[0], state[1], state[2], state[3] } : { istate[0], istate[1], istate[2], istate[3] };





  always @(posedge clock or negedge resetn) begin
    if ( resetn == 1'b0 ) begin
      { w[0], w[1], w[2], w[3] } <= {128{1'b0}};
      round10_key <= {128{1'b0}};
    end
    else begin

      if ( next_state == `IDLE ) { w[0], w[1], w[2], w[3] } <= key_in;
      else if (( next_state == `KEY_EXP ) || ( next_state == `ROUND_LOOP )) { w[0], w[1], w[2], w[3] } <= next_key;
      else { w[0], w[1], w[2], w[3] } <= { w[0], w[1], w[2], w[3] };


      if (( now_state == `KEY_EXP ) && ( round_n == 4'd10 )) round10_key <= { w[0], w[1], w[2], w[3] };
      else round10_key <= round10_key;
    end
  end


  assign rotword = {w[3][23:0], w[3][31:24]};

  subword SubWord ( .a( rotword ), .b( temp ));


  assign next_key[127:96] = w[0] ^ {( temp[31:24] ^ rcon ), temp[23:0] };
  assign next_key[ 95:64] = w[1] ^ next_key[127:96];
  assign next_key[ 63:32] = w[2] ^ next_key[ 95:64];
  assign next_key[ 31: 0] = w[3] ^ next_key[ 63:32];


  assign rcon = ( round_n == 4'h0 )? 8'h01 : 8'h00
              | ( round_n == 4'h1 )? 8'h02 : 8'h00
              | ( round_n == 4'h2 )? 8'h04 : 8'h00
              | ( round_n == 4'h3 )? 8'h08 : 8'h00
              | ( round_n == 4'h4 )? 8'h10 : 8'h00
              | ( round_n == 4'h5 )? 8'h20 : 8'h00
              | ( round_n == 4'h6 )? 8'h40 : 8'h00
              | ( round_n == 4'h7 )? 8'h80 : 8'h00
              | ( round_n == 4'h8 )? 8'h1b : 8'h00
              | ( round_n == 4'h9 )? 8'h36 : 8'h00;






  always @(posedge clock or negedge resetn) begin
    if ( resetn == 1'b0 ) begin
      { iw[0], iw[1], iw[2], iw[3] } <= {128{1'b0}};
    end
    else begin
      if (( now_state == `KEY_EXP ) && ( round_n == 4'd10 )) { iw[0], iw[1], iw[2], iw[3] } <= { w[0], w[1], w[2], w[3] };
      else if ( next_state == `IDLE ) { iw[0], iw[1], iw[2], iw[3] } <= round10_key;
      else if (( start == 1'b1 ) || ( start_flag == 1'b1 ) || ( now_state == `ROUND_LOOP )) { iw[0], iw[1], iw[2], iw[3] } <= next_ikey;
      else { iw[0], iw[1], iw[2], iw[3] } <= { iw[0], iw[1], iw[2], iw[3] };
    end
  end

  assign itemp = iw[3] ^ iw[2];


  subword iSubWord ( .a( itemp ), .b( sword ));


  assign irotword = {sword[23:0], sword[31:24]};


  assign next_ikey[127:96] = {( iw[0][31:24] ^ irotword[31:24] ^ ircon ), ( iw[0][23:0] ^ irotword[23:0] )};
  assign next_ikey[ 95:64] = iw[1] ^ iw[0];
  assign next_ikey[ 63:32] = iw[2] ^ iw[1];
  assign next_ikey[ 31: 0] = iw[3] ^ iw[2];

  assign ircon = ( round_n == 4'h9 )? 8'h01 : 8'h00
               | ( round_n == 4'h8 )? 8'h02 : 8'h00
               | ( round_n == 4'h7 )? 8'h04 : 8'h00
               | ( round_n == 4'h6 )? 8'h08 : 8'h00
               | ( round_n == 4'h5 )? 8'h10 : 8'h00
               | ( round_n == 4'h4 )? 8'h20 : 8'h00
               | ( round_n == 4'h3 )? 8'h40 : 8'h00
               | ( round_n == 4'h2 )? 8'h80 : 8'h00
               | ( round_n == 4'h1 )? 8'h1b : 8'h00
               | ( round_n == 4'h0 )? 8'h36 : 8'h00;







  always @(posedge clock or negedge resetn) begin
    if ( resetn == 1'b0 ) begin
      { state[0], state[1], state[2], state[3]} <= {128{1'b0}};
    end
    else begin
      if ( enc_dec == 1'b0 ) begin
        if ((( start == 1'b1 ) || ( start_flag == 1'b1 )) && ( round_n == 4'h0 )) begin
          { state[0], state[1], state[2], state[3]} <= add_roundkey0;
        end
        else if (( now_state == `ROUND_LOOP ) && ( round_n >= 4'd1 ) && ( round_n <= 4'h9 )) begin
          { state[0], state[1], state[2], state[3]} <= add_roundkey;
        end
        else if (( now_state == `ROUND_LOOP ) && ( round_n == 4'd10 )) begin
          { state[0], state[1], state[2], state[3]} <= cipher_text;
        end
        else { state[0], state[1], state[2], state[3]} <= { state[0], state[1], state[2], state[3]};
      end
      else { state[0], state[1], state[2], state[3]} <= { state[0], state[1], state[2], state[3]};
    end
  end




  assign add_roundkey0 = text_in ^ { w[0], w[1], w[2], w[3] };




  subbytes SubBytes (
    .a00( state[0][31:24] ), .a10( state[0][23:16] ), .a20( state[0][15:8] ), .a30( state[0][7:0] ),
    .a01( state[1][31:24] ), .a11( state[1][23:16] ), .a21( state[1][15:8] ), .a31( state[1][7:0] ),
    .a02( state[2][31:24] ), .a12( state[2][23:16] ), .a22( state[2][15:8] ), .a32( state[2][7:0] ),
    .a03( state[3][31:24] ), .a13( state[3][23:16] ), .a23( state[3][15:8] ), .a33( state[3][7:0] ),

    .b00( s_box[0][0] ), .b10( s_box[1][0] ), .b20( s_box[2][0] ), .b30( s_box[3][0] ),
    .b01( s_box[0][1] ), .b11( s_box[1][1] ), .b21( s_box[2][1] ), .b31( s_box[3][1] ),
    .b02( s_box[0][2] ), .b12( s_box[1][2] ), .b22( s_box[2][2] ), .b32( s_box[3][2] ),
    .b03( s_box[0][3] ), .b13( s_box[1][3] ), .b23( s_box[2][3] ), .b33( s_box[3][3] )
  );




  assign { s_row[0][0], s_row[0][1], s_row[0][2], s_row[0][3] } = { s_box[0][0], s_box[0][1], s_box[0][2], s_box[0][3] };
  assign { s_row[1][0], s_row[1][1], s_row[1][2], s_row[1][3] } = { s_box[1][1], s_box[1][2], s_box[1][3], s_box[1][0] };
  assign { s_row[2][0], s_row[2][1], s_row[2][2], s_row[2][3] } = { s_box[2][2], s_box[2][3], s_box[2][0], s_box[2][1] };
  assign { s_row[3][0], s_row[3][1], s_row[3][2], s_row[3][3] } = { s_box[3][3], s_box[3][0], s_box[3][1], s_box[3][2] };




  mixcolumns MixColumns0 (
    .s0c( s_row[0][0] ), .s1c( s_row[1][0] ), .s2c( s_row[2][0] ), .s3c( s_row[3][0] ),
    .m0c( m_col[0][0] ), .m1c( m_col[1][0] ), .m2c( m_col[2][0] ), .m3c( m_col[3][0] )
  );
  mixcolumns MixColumns1 (
    .s0c( s_row[0][1] ), .s1c( s_row[1][1] ), .s2c( s_row[2][1] ), .s3c( s_row[3][1] ),
    .m0c( m_col[0][1] ), .m1c( m_col[1][1] ), .m2c( m_col[2][1] ), .m3c( m_col[3][1] )
  );
  mixcolumns MixColumns2 (
    .s0c( s_row[0][2] ), .s1c( s_row[1][2] ), .s2c( s_row[2][2] ), .s3c( s_row[3][2] ),
    .m0c( m_col[0][2] ), .m1c( m_col[1][2] ), .m2c( m_col[2][2] ), .m3c( m_col[3][2] )
  );
  mixcolumns MixColumns3 (
    .s0c( s_row[0][3] ), .s1c( s_row[1][3] ), .s2c( s_row[2][3] ), .s3c( s_row[3][3] ),
    .m0c( m_col[0][3] ), .m1c( m_col[1][3] ), .m2c( m_col[2][3] ), .m3c( m_col[3][3] )
  );





  assign add_roundkey[127:96] = { m_col[0][0], m_col[1][0], m_col[2][0], m_col[3][0] } ^ w[0];
  assign add_roundkey[ 95:64] = { m_col[0][1], m_col[1][1], m_col[2][1], m_col[3][1] } ^ w[1];
  assign add_roundkey[ 63:32] = { m_col[0][2], m_col[1][2], m_col[2][2], m_col[3][2] } ^ w[2];
  assign add_roundkey[ 31: 0] = { m_col[0][3], m_col[1][3], m_col[2][3], m_col[3][3] } ^ w[3];



  assign cipher_text[127:96] = { s_row[0][0], s_row[1][0], s_row[2][0], s_row[3][0] } ^ w[0];
  assign cipher_text[ 95:64] = { s_row[0][1], s_row[1][1], s_row[2][1], s_row[3][1] } ^ w[1];
  assign cipher_text[ 63:32] = { s_row[0][2], s_row[1][2], s_row[2][2], s_row[3][2] } ^ w[2];
  assign cipher_text[ 31: 0] = { s_row[0][3], s_row[1][3], s_row[2][3], s_row[3][3] } ^ w[3];








  always @(posedge clock or negedge resetn) begin
    if ( resetn == 1'b0 ) begin
      { istate[0], istate[1], istate[2], istate[3]} <= {128{1'b0}};
    end
    else begin
      if ( enc_dec == 1'b1 ) begin
        if ((( start == 1'b1 ) || ( start_flag == 1'b1 )) && ( round_n == 4'h0 )) begin
          { istate[0], istate[1], istate[2], istate[3]} <= add_iroundkey0;
        end
        else if (( now_state == `ROUND_LOOP ) && ( round_n >= 4'd1 ) && ( round_n <= 4'd9 )) begin
          { istate[0], istate[1], istate[2], istate[3]} <= { im_col[0], im_col[1], im_col[2], im_col[3] };
        end
        else if (( now_state == `ROUND_LOOP ) && ( round_n == 4'd10 )) begin
          { istate[0], istate[1], istate[2], istate[3]} <= add_iroundkey;
        end
        else { istate[0], istate[1], istate[2], istate[3]} <= { istate[0], istate[1], istate[2], istate[3]};
      end
      else { istate[0], istate[1], istate[2], istate[3]} <= { istate[0], istate[1], istate[2], istate[3]};
    end
  end




  assign add_iroundkey0 = text_in ^ { iw[0], iw[1], iw[2], iw[3] };





  assign { is_row_in[0][0], is_row_in[1][0], is_row_in[2][0], is_row_in[3][0] } = istate[0];
  assign { is_row_in[0][1], is_row_in[1][1], is_row_in[2][1], is_row_in[3][1] } = istate[1];
  assign { is_row_in[0][2], is_row_in[1][2], is_row_in[2][2], is_row_in[3][2] } = istate[2];
  assign { is_row_in[0][3], is_row_in[1][3], is_row_in[2][3], is_row_in[3][3] } = istate[3];

  assign { is_row[0][0], is_row[0][1], is_row[0][2], is_row[0][3] } = { is_row_in[0][0], is_row_in[0][1], is_row_in[0][2], is_row_in[0][3] };
  assign { is_row[1][1], is_row[1][2], is_row[1][3], is_row[1][0] } = { is_row_in[1][0], is_row_in[1][1], is_row_in[1][2], is_row_in[1][3] };
  assign { is_row[2][2], is_row[2][3], is_row[2][0], is_row[2][1] } = { is_row_in[2][0], is_row_in[2][1], is_row_in[2][2], is_row_in[2][3] };
  assign { is_row[3][3], is_row[3][0], is_row[3][1], is_row[3][2] } = { is_row_in[3][0], is_row_in[3][1], is_row_in[3][2], is_row_in[3][3] };





  invsubbytes InvSubBytes (
    .a00( is_row[0][0] ), .a10( is_row[1][0] ), .a20( is_row[2][0] ), .a30( is_row[3][0] ),
    .a01( is_row[0][1] ), .a11( is_row[1][1] ), .a21( is_row[2][1] ), .a31( is_row[3][1] ),
    .a02( is_row[0][2] ), .a12( is_row[1][2] ), .a22( is_row[2][2] ), .a32( is_row[3][2] ),
    .a03( is_row[0][3] ), .a13( is_row[1][3] ), .a23( is_row[2][3] ), .a33( is_row[3][3] ),

    .b00( is_box[0][0] ), .b10( is_box[1][0] ), .b20( is_box[2][0] ), .b30( is_box[3][0] ),
    .b01( is_box[0][1] ), .b11( is_box[1][1] ), .b21( is_box[2][1] ), .b31( is_box[3][1] ),
    .b02( is_box[0][2] ), .b12( is_box[1][2] ), .b22( is_box[2][2] ), .b32( is_box[3][2] ),
    .b03( is_box[0][3] ), .b13( is_box[1][3] ), .b23( is_box[2][3] ), .b33( is_box[3][3] )
  );





  assign add_iroundkey[127:96] = { is_box[0][0], is_box[1][0], is_box[2][0], is_box[3][0] } ^ iw[0];
  assign add_iroundkey[ 95:64] = { is_box[0][1], is_box[1][1], is_box[2][1], is_box[3][1] } ^ iw[1];
  assign add_iroundkey[ 63:32] = { is_box[0][2], is_box[1][2], is_box[2][2], is_box[3][2] } ^ iw[2];
  assign add_iroundkey[ 31: 0] = { is_box[0][3], is_box[1][3], is_box[2][3], is_box[3][3] } ^ iw[3];




  inv_mixcolumn InvMixColumn0 (
    .s0c( add_iroundkey[127:120] ), .s1c( add_iroundkey[119:112] ), .s2c( add_iroundkey[111:104] ), .s3c( add_iroundkey[103:96] ),
    .m0c( im_col[0][31:24] ),       .m1c( im_col[0][23:16] ),       .m2c( im_col[0][15:8] ),        .m3c( im_col[0][7:0] )
  );
  inv_mixcolumn InvMixColumn1 (
    .s0c( add_iroundkey[95:88] ), .s1c( add_iroundkey[87:80] ), .s2c( add_iroundkey[79:72] ), .s3c( add_iroundkey[71:64] ),
    .m0c( im_col[1][31:24] ),     .m1c( im_col[1][23:16] ),     .m2c( im_col[1][15:8] ),      .m3c( im_col[1][7:0] )
  );
  inv_mixcolumn InvMixColumn2(
    .s0c( add_iroundkey[63:56] ), .s1c( add_iroundkey[55:48] ), .s2c( add_iroundkey[47:40] ), .s3c( add_iroundkey[39:32] ),
    .m0c( im_col[2][31:24] ),     .m1c( im_col[2][23:16] ),     .m2c( im_col[2][15:8] ),      .m3c( im_col[2][7:0] )
  );
  inv_mixcolumn InvMixColumn3 (
    .s0c( add_iroundkey[31:24] ), .s1c( add_iroundkey[23:16] ), .s2c( add_iroundkey[15:8] ), .s3c( add_iroundkey[7:0] ),
    .m0c( im_col[3][31:24] ),     .m1c( im_col[3][23:16] ),     .m2c( im_col[3][15:8] ),     .m3c( im_col[3][7:0] )
  );

endmodule
module aes128_table_ecb (
  input               resetn,
  input               clock,

  input               enc_dec,
  input               key_exp,
  input               start,
  output reg          key_val,
  output reg          text_val,
  input      [127:0]  key_in,
  input      [127:0]  text_in,
  output     [127:0]  text_out,
  output reg          busy
);



`define  IDLE        3'h0
`define  KEY_EXP     3'h1
`define  ROUND_LOOP  3'h2




  reg       [2:0]  now_state;
  reg       [2:0]  next_state;
  reg              start_flag;
  reg       [3:0]  round_n;


  reg      [31:0]  w[0:3];
  wire     [31:0]  rotword;
  wire      [7:0]  rcon;
  wire     [31:0]  temp;
  wire    [127:0]  next_key;
  reg     [127:0]  round10_key;


  reg      [31:0]  iw[0:3];
  wire      [7:0]  ircon;
  wire     [31:0]  itemp;
  wire     [31:0]  sword;
  wire     [31:0]  irotword;
  wire    [127:0]  next_ikey;


  reg      [31:0]  state[0:3];
  wire      [7:0]  s_box[0:3][0:3];
  wire      [7:0]  s_row[0:3][0:3];
  wire      [7:0]  m_col[0:3][0:3];
  wire    [127:0]  add_roundkey0;
  wire    [127:0]  add_roundkey;
  wire    [127:0]  cipher_text;


  reg      [31:0]  istate[0:3];
  wire      [7:0]  is_row_in[0:3][0:3];
  wire      [7:0]  is_row[0:3][0:3];
  wire      [7:0]  is_box[0:3][0:3];
  wire     [31:0]  im_col[0:3];
  wire    [127:0]  add_iroundkey0;
  wire    [127:0]  add_iroundkey;
  wire    [127:0]  plainte_text;







  always @( now_state or enc_dec or key_exp or start or start_flag or round_n or key_val ) begin
    case ( now_state )
      `IDLE       : if ( key_exp == 1'b1 ) next_state = `KEY_EXP;
                    else if ( start == 1'b1 )
                      if ( key_val == 1'b0 ) next_state = `KEY_EXP;
                      else next_state = `ROUND_LOOP;
                    else if ( start_flag == 1'b1 ) next_state = `ROUND_LOOP;
                    else next_state = `IDLE;
      `KEY_EXP    : if ( round_n == 4'd10 ) next_state = `IDLE;
                    else next_state = `KEY_EXP;
      `ROUND_LOOP : if ( round_n == 4'd10 ) next_state = `IDLE;
                    else next_state = `ROUND_LOOP;
       default    : next_state = `IDLE;
    endcase
  end

  always @(posedge clock or negedge resetn) begin
    if ( resetn == 1'b0 ) now_state <= `IDLE;
    else now_state <= next_state;
  end





  always @(posedge clock or negedge resetn) begin
    if ( resetn == 1'b0 ) begin
      busy <= 1'b0;
      start_flag <= 1'b0;
      key_val <= 1'b0;
      round_n <= 4'h0;
      key_val <= 1'b0;
      text_val <= 1'b0;
    end
    else begin

      if (( key_exp == 1'b1 ) || ( start == 1'b1 )) busy <= 1'b1;
      else if (( now_state == `KEY_EXP ) && ( round_n == 4'd10 ) && ( start_flag != 1'b1 )) busy <= 1'b0;
      else if (( now_state == `ROUND_LOOP ) && ( round_n == 4'd10 )) busy <= 1'b0;
      else busy <= busy;


      if ( start == 1'b1 ) start_flag <= 1'b1;
      else if ( now_state == `ROUND_LOOP ) start_flag <= 1'b0;
      else start_flag <= start_flag;


      if ( next_state == `IDLE ) round_n <= 4'h0;
      else round_n <= round_n + 1'b1;


      if ( key_exp == 1'b1 ) key_val <= 1'b0;
      else if (( now_state == `KEY_EXP ) && ( round_n == 4'd10 )) key_val <= 1'b1;
      else key_val <= key_val;


      if (( now_state == `ROUND_LOOP ) && ( round_n == 4'd10 )) text_val <= 1'b1;
      else text_val <= 1'b0;
    end
  end


  assign text_out = ( enc_dec == 1'b0 )? { state[0], state[1], state[2], state[3] } : { istate[0], istate[1], istate[2], istate[3] };





  always @(posedge clock or negedge resetn) begin
    if ( resetn == 1'b0 ) begin
      { w[0], w[1], w[2], w[3] } <= {128{1'b0}};
      round10_key <= {128{1'b0}};
    end
    else begin

      if ( next_state == `IDLE ) { w[0], w[1], w[2], w[3] } <= key_in;
      else if (( next_state == `KEY_EXP ) || ( next_state == `ROUND_LOOP )) { w[0], w[1], w[2], w[3] } <= next_key;
      else { w[0], w[1], w[2], w[3] } <= { w[0], w[1], w[2], w[3] };


      if (( now_state == `KEY_EXP ) && ( round_n == 4'd10 )) round10_key <= { w[0], w[1], w[2], w[3] };
      else round10_key <= round10_key;
    end
  end


  assign rotword = {w[3][23:0], w[3][31:24]};

  subword SubWord ( .a( rotword ), .b( temp ));


  assign next_key[127:96] = w[0] ^ {( temp[31:24] ^ rcon ), temp[23:0] };
  assign next_key[ 95:64] = w[1] ^ next_key[127:96];
  assign next_key[ 63:32] = w[2] ^ next_key[ 95:64];
  assign next_key[ 31: 0] = w[3] ^ next_key[ 63:32];


  assign rcon = ( round_n == 4'h0 )? 8'h01 : 8'h00
              | ( round_n == 4'h1 )? 8'h02 : 8'h00
              | ( round_n == 4'h2 )? 8'h04 : 8'h00
              | ( round_n == 4'h3 )? 8'h08 : 8'h00
              | ( round_n == 4'h4 )? 8'h10 : 8'h00
              | ( round_n == 4'h5 )? 8'h20 : 8'h00
              | ( round_n == 4'h6 )? 8'h40 : 8'h00
              | ( round_n == 4'h7 )? 8'h80 : 8'h00
              | ( round_n == 4'h8 )? 8'h1b : 8'h00
              | ( round_n == 4'h9 )? 8'h36 : 8'h00;






  always @(posedge clock or negedge resetn) begin
    if ( resetn == 1'b0 ) begin
      { iw[0], iw[1], iw[2], iw[3] } <= {128{1'b0}};
    end
    else begin
      if (( now_state == `KEY_EXP ) && ( round_n == 4'd10 )) { iw[0], iw[1], iw[2], iw[3] } <= { w[0], w[1], w[2], w[3] };
      else if ( next_state == `IDLE ) { iw[0], iw[1], iw[2], iw[3] } <= round10_key;
      else if (( start == 1'b1 ) || ( start_flag == 1'b1 ) || ( now_state == `ROUND_LOOP )) { iw[0], iw[1], iw[2], iw[3] } <= next_ikey;
      else { iw[0], iw[1], iw[2], iw[3] } <= { iw[0], iw[1], iw[2], iw[3] };
    end
  end

  assign itemp = iw[3] ^ iw[2];


  subword iSubWord ( .a( itemp ), .b( sword ));


  assign irotword = {sword[23:0], sword[31:24]};


  assign next_ikey[127:96] = {( iw[0][31:24] ^ irotword[31:24] ^ ircon ), ( iw[0][23:0] ^ irotword[23:0] )};
  assign next_ikey[ 95:64] = iw[1] ^ iw[0];
  assign next_ikey[ 63:32] = iw[2] ^ iw[1];
  assign next_ikey[ 31: 0] = iw[3] ^ iw[2];

  assign ircon = ( round_n == 4'h9 )? 8'h01 : 8'h00
               | ( round_n == 4'h8 )? 8'h02 : 8'h00
               | ( round_n == 4'h7 )? 8'h04 : 8'h00
               | ( round_n == 4'h6 )? 8'h08 : 8'h00
               | ( round_n == 4'h5 )? 8'h10 : 8'h00
               | ( round_n == 4'h4 )? 8'h20 : 8'h00
               | ( round_n == 4'h3 )? 8'h40 : 8'h00
               | ( round_n == 4'h2 )? 8'h80 : 8'h00
               | ( round_n == 4'h1 )? 8'h1b : 8'h00
               | ( round_n == 4'h0 )? 8'h36 : 8'h00;







  always @(posedge clock or negedge resetn) begin
    if ( resetn == 1'b0 ) begin
      { state[0], state[1], state[2], state[3]} <= {128{1'b0}};
    end
    else begin
      if ( enc_dec == 1'b0 ) begin
        if ((( start == 1'b1 ) || ( start_flag == 1'b1 )) && ( round_n == 4'h0 )) begin
          { state[0], state[1], state[2], state[3]} <= add_roundkey0;
        end
        else if (( now_state == `ROUND_LOOP ) && ( round_n >= 4'd1 ) && ( round_n <= 4'h9 )) begin
          { state[0], state[1], state[2], state[3]} <= add_roundkey;
        end
        else if (( now_state == `ROUND_LOOP ) && ( round_n == 4'd10 )) begin
          { state[0], state[1], state[2], state[3]} <= cipher_text;
        end
        else { state[0], state[1], state[2], state[3]} <= { state[0], state[1], state[2], state[3]};
      end
      else { state[0], state[1], state[2], state[3]} <= { state[0], state[1], state[2], state[3]};
    end
  end




  assign add_roundkey0 = text_in ^ { w[0], w[1], w[2], w[3] };




  subbytes SubBytes (
    .a00( state[0][31:24] ), .a10( state[0][23:16] ), .a20( state[0][15:8] ), .a30( state[0][7:0] ),
    .a01( state[1][31:24] ), .a11( state[1][23:16] ), .a21( state[1][15:8] ), .a31( state[1][7:0] ),
    .a02( state[2][31:24] ), .a12( state[2][23:16] ), .a22( state[2][15:8] ), .a32( state[2][7:0] ),
    .a03( state[3][31:24] ), .a13( state[3][23:16] ), .a23( state[3][15:8] ), .a33( state[3][7:0] ),

    .b00( s_box[0][0] ), .b10( s_box[1][0] ), .b20( s_box[2][0] ), .b30( s_box[3][0] ),
    .b01( s_box[0][1] ), .b11( s_box[1][1] ), .b21( s_box[2][1] ), .b31( s_box[3][1] ),
    .b02( s_box[0][2] ), .b12( s_box[1][2] ), .b22( s_box[2][2] ), .b32( s_box[3][2] ),
    .b03( s_box[0][3] ), .b13( s_box[1][3] ), .b23( s_box[2][3] ), .b33( s_box[3][3] )
  );




  assign { s_row[0][0], s_row[0][1], s_row[0][2], s_row[0][3] } = { s_box[0][0], s_box[0][1], s_box[0][2], s_box[0][3] };
  assign { s_row[1][0], s_row[1][1], s_row[1][2], s_row[1][3] } = { s_box[1][1], s_box[1][2], s_box[1][3], s_box[1][0] };
  assign { s_row[2][0], s_row[2][1], s_row[2][2], s_row[2][3] } = { s_box[2][2], s_box[2][3], s_box[2][0], s_box[2][1] };
  assign { s_row[3][0], s_row[3][1], s_row[3][2], s_row[3][3] } = { s_box[3][3], s_box[3][0], s_box[3][1], s_box[3][2] };




  mixcolumns MixColumns0 (
    .s0c( s_row[0][0] ), .s1c( s_row[1][0] ), .s2c( s_row[2][0] ), .s3c( s_row[3][0] ),
    .m0c( m_col[0][0] ), .m1c( m_col[1][0] ), .m2c( m_col[2][0] ), .m3c( m_col[3][0] )
  );
  mixcolumns MixColumns1 (
    .s0c( s_row[0][1] ), .s1c( s_row[1][1] ), .s2c( s_row[2][1] ), .s3c( s_row[3][1] ),
    .m0c( m_col[0][1] ), .m1c( m_col[1][1] ), .m2c( m_col[2][1] ), .m3c( m_col[3][1] )
  );
  mixcolumns MixColumns2 (
    .s0c( s_row[0][2] ), .s1c( s_row[1][2] ), .s2c( s_row[2][2] ), .s3c( s_row[3][2] ),
    .m0c( m_col[0][2] ), .m1c( m_col[1][2] ), .m2c( m_col[2][2] ), .m3c( m_col[3][2] )
  );
  mixcolumns MixColumns3 (
    .s0c( s_row[0][3] ), .s1c( s_row[1][3] ), .s2c( s_row[2][3] ), .s3c( s_row[3][3] ),
    .m0c( m_col[0][3] ), .m1c( m_col[1][3] ), .m2c( m_col[2][3] ), .m3c( m_col[3][3] )
  );





  assign add_roundkey[127:96] = { m_col[0][0], m_col[1][0], m_col[2][0], m_col[3][0] } ^ w[0];
  assign add_roundkey[ 95:64] = { m_col[0][1], m_col[1][1], m_col[2][1], m_col[3][1] } ^ w[1];
  assign add_roundkey[ 63:32] = { m_col[0][2], m_col[1][2], m_col[2][2], m_col[3][2] } ^ w[2];
  assign add_roundkey[ 31: 0] = { m_col[0][3], m_col[1][3], m_col[2][3], m_col[3][3] } ^ w[3];



  assign cipher_text[127:96] = { s_row[0][0], s_row[1][0], s_row[2][0], s_row[3][0] } ^ w[0];
  assign cipher_text[ 95:64] = { s_row[0][1], s_row[1][1], s_row[2][1], s_row[3][1] } ^ w[1];
  assign cipher_text[ 63:32] = { s_row[0][2], s_row[1][2], s_row[2][2], s_row[3][2] } ^ w[2];
  assign cipher_text[ 31: 0] = { s_row[0][3], s_row[1][3], s_row[2][3], s_row[3][3] } ^ w[3];








  always @(posedge clock or negedge resetn) begin
    if ( resetn == 1'b0 ) begin
      { istate[0], istate[1], istate[2], istate[3]} <= {128{1'b0}};
    end
    else begin
      if ( enc_dec == 1'b1 ) begin
        if ((( start == 1'b1 ) || ( start_flag == 1'b1 )) && ( round_n == 4'h0 )) begin
          { istate[0], istate[1], istate[2], istate[3]} <= add_iroundkey0;
        end
        else if (( now_state == `ROUND_LOOP ) && ( round_n >= 4'd1 ) && ( round_n <= 4'd9 )) begin
          { istate[0], istate[1], istate[2], istate[3]} <= { im_col[0], im_col[1], im_col[2], im_col[3] };
        end
        else if (( now_state == `ROUND_LOOP ) && ( round_n == 4'd10 )) begin
          { istate[0], istate[1], istate[2], istate[3]} <= add_iroundkey;
        end
        else { istate[0], istate[1], istate[2], istate[3]} <= { istate[0], istate[1], istate[2], istate[3]};
      end
      else { istate[0], istate[1], istate[2], istate[3]} <= { istate[0], istate[1], istate[2], istate[3]};
    end
  end




  assign add_iroundkey0 = text_in ^ { iw[0], iw[1], iw[2], iw[3] };





  assign { is_row_in[0][0], is_row_in[1][0], is_row_in[2][0], is_row_in[3][0] } = istate[0];
  assign { is_row_in[0][1], is_row_in[1][1], is_row_in[2][1], is_row_in[3][1] } = istate[1];
  assign { is_row_in[0][2], is_row_in[1][2], is_row_in[2][2], is_row_in[3][2] } = istate[2];
  assign { is_row_in[0][3], is_row_in[1][3], is_row_in[2][3], is_row_in[3][3] } = istate[3];

  assign { is_row[0][0], is_row[0][1], is_row[0][2], is_row[0][3] } = { is_row_in[0][0], is_row_in[0][1], is_row_in[0][2], is_row_in[0][3] };
  assign { is_row[1][1], is_row[1][2], is_row[1][3], is_row[1][0] } = { is_row_in[1][0], is_row_in[1][1], is_row_in[1][2], is_row_in[1][3] };
  assign { is_row[2][2], is_row[2][3], is_row[2][0], is_row[2][1] } = { is_row_in[2][0], is_row_in[2][1], is_row_in[2][2], is_row_in[2][3] };
  assign { is_row[3][3], is_row[3][0], is_row[3][1], is_row[3][2] } = { is_row_in[3][0], is_row_in[3][1], is_row_in[3][2], is_row_in[3][3] };





  invsubbytes InvSubBytes (
    .a00( is_row[0][0] ), .a10( is_row[1][0] ), .a20( is_row[2][0] ), .a30( is_row[3][0] ),
    .a01( is_row[0][1] ), .a11( is_row[1][1] ), .a21( is_row[2][1] ), .a31( is_row[3][1] ),
    .a02( is_row[0][2] ), .a12( is_row[1][2] ), .a22( is_row[2][2] ), .a32( is_row[3][2] ),
    .a03( is_row[0][3] ), .a13( is_row[1][3] ), .a23( is_row[2][3] ), .a33( is_row[3][3] ),

    .b00( is_box[0][0] ), .b10( is_box[1][0] ), .b20( is_box[2][0] ), .b30( is_box[3][0] ),
    .b01( is_box[0][1] ), .b11( is_box[1][1] ), .b21( is_box[2][1] ), .b31( is_box[3][1] ),
    .b02( is_box[0][2] ), .b12( is_box[1][2] ), .b22( is_box[2][2] ), .b32( is_box[3][2] ),
    .b03( is_box[0][3] ), .b13( is_box[1][3] ), .b23( is_box[2][3] ), .b33( is_box[3][3] )
  );





  assign add_iroundkey[127:96] = { is_box[0][0], is_box[1][0], is_box[2][0], is_box[3][0] } ^ iw[0];
  assign add_iroundkey[ 95:64] = { is_box[0][1], is_box[1][1], is_box[2][1], is_box[3][1] } ^ iw[1];
  assign add_iroundkey[ 63:32] = { is_box[0][2], is_box[1][2], is_box[2][2], is_box[3][2] } ^ iw[2];
  assign add_iroundkey[ 31: 0] = { is_box[0][3], is_box[1][3], is_box[2][3], is_box[3][3] } ^ iw[3];




  inv_mixcolumn InvMixColumn0 (
    .s0c( add_iroundkey[127:120] ), .s1c( add_iroundkey[119:112] ), .s2c( add_iroundkey[111:104] ), .s3c( add_iroundkey[103:96] ),
    .m0c( im_col[0][31:24] ),       .m1c( im_col[0][23:16] ),       .m2c( im_col[0][15:8] ),        .m3c( im_col[0][7:0] )
  );
  inv_mixcolumn InvMixColumn1 (
    .s0c( add_iroundkey[95:88] ), .s1c( add_iroundkey[87:80] ), .s2c( add_iroundkey[79:72] ), .s3c( add_iroundkey[71:64] ),
    .m0c( im_col[1][31:24] ),     .m1c( im_col[1][23:16] ),     .m2c( im_col[1][15:8] ),      .m3c( im_col[1][7:0] )
  );
  inv_mixcolumn InvMixColumn2(
    .s0c( add_iroundkey[63:56] ), .s1c( add_iroundkey[55:48] ), .s2c( add_iroundkey[47:40] ), .s3c( add_iroundkey[39:32] ),
    .m0c( im_col[2][31:24] ),     .m1c( im_col[2][23:16] ),     .m2c( im_col[2][15:8] ),      .m3c( im_col[2][7:0] )
  );
  inv_mixcolumn InvMixColumn3 (
    .s0c( add_iroundkey[31:24] ), .s1c( add_iroundkey[23:16] ), .s2c( add_iroundkey[15:8] ), .s3c( add_iroundkey[7:0] ),
    .m0c( im_col[3][31:24] ),     .m1c( im_col[3][23:16] ),     .m2c( im_col[3][15:8] ),     .m3c( im_col[3][7:0] )
  );

endmodule