data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:111: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_in;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:112: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_out;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:113: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_oeb;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:125: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_out = {user_gpio_out, pwmA_q0, pwmB_q0, pwmC_q0, pwmA_n0, pwmB_n0, pwmC_n0, user_halt, {(`MPRJ_IO_PADS-1-8-6-1){1'b0}}};\n                                                                                                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:126: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_oeb = {user_gpio_en,  {(`MPRJ_IO_PADS-1-8){rst}}};\n                                      ^~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module MinxTop (
  input clk
, input clr 

, output wire [2:0] pstate
, output wire [7:0] regR0
, output wire [7:0] regR1
, output wire [7:0] regR2
, output wire [7:0] regR3

, output wire [7:0] abus
, output wire [7:0] dbuso
, input  wire [7:0] dbusi
, output wire       rd
, output wire       wr
, output wire       sig_halt
);


  wire [7:0] instruction;
  

  wire [2:0] sel_dbus_mux;
  wire [1:0] sel_bus2_mux;
  wire ld_r0, ld_r1, ld_r2, ld_r3, ld_pc, inc_pc, ld_ir;
  wire ld_address_reg, ld_reg_y, ld_reg_z, carry, zero;
    
  processing_unit processor(
    .clk(clk)
,   .clr(clr)
,   .instruction(instruction)
,   .zero_flag(zero)
,   .carry_flag(carry)
,   .address(abus)
,   .dbuso(dbuso)
,   .dbusi(dbusi)
,   .ld_r0(ld_r0)
,   .regR0(regR0)
,   .ld_r1(ld_r1)
,   .regR1(regR1)
,   .ld_r2(ld_r2)
,   .regR2(regR2)
,   .ld_r3(ld_r3)
,   .regR3(regR3)
,   .ld_pc(ld_pc)
,   .inc_pc(inc_pc)
,   .ld_ir(ld_ir)
,   .ld_address_reg(ld_address_reg)
,   .ld_reg_y(ld_reg_y)
,   .ld_reg_z(ld_reg_z)
,   .sel_dbus_mux(sel_dbus_mux)
,   .sel_bus2_mux(sel_bus2_mux)
);

  control_unit controller(
    .clk(clk)
,   .clr(clr)

,   .pstate(pstate)
,   .ld_r0(ld_r0)
,   .ld_r1(ld_r1)
,   .ld_r2(ld_r2)
,   .ld_r3(ld_r3)
,   .ld_pc(ld_pc)
,   .inc_pc(inc_pc)
,   .sel_dbus_mux(sel_dbus_mux)
,   .sel_bus2_mux(sel_bus2_mux)
,   .ld_ir(ld_ir)
,   .ld_address_reg(ld_address_reg)
,   .ld_reg_y(ld_reg_y)
,   .ld_reg_z(ld_reg_z)
,   .read(rd)
,   .write(wr)
,   .instruction(instruction)
,   .regR0(regR0)
,   .zero(zero)
,   .carry(carry)
,   .sig_halt(sig_halt)
);

endmodule
module MinxTop (
  input clk
, input clr 

, output wire [2:0] pstate
, output wire [7:0] regR0
, output wire [7:0] regR1
, output wire [7:0] regR2
, output wire [7:0] regR3

, output wire [7:0] abus
, output wire [7:0] dbuso
, input  wire [7:0] dbusi
, output wire       rd
, output wire       wr
, output wire       sig_halt
);



  wire [7:0] instruction;
  

  wire [2:0] sel_dbus_mux;
  wire [1:0] sel_bus2_mux;
  wire ld_r0, ld_r1, ld_r2, ld_r3, ld_pc, inc_pc, ld_ir;
  wire ld_address_reg, ld_reg_y, ld_reg_z, carry, zero;
    
  processing_unit processor(
    .clk(clk)
,   .clr(clr)
,   .instruction(instruction)
,   .zero_flag(zero)
,   .carry_flag(carry)
,   .address(abus)
,   .dbuso(dbuso)
,   .dbusi(dbusi)
,   .ld_r0(ld_r0)
,   .regR0(regR0)
,   .ld_r1(ld_r1)
,   .regR1(regR1)
,   .ld_r2(ld_r2)
,   .regR2(regR2)
,   .ld_r3(ld_r3)
,   .regR3(regR3)
,   .ld_pc(ld_pc)
,   .inc_pc(inc_pc)
,   .ld_ir(ld_ir)
,   .ld_address_reg(ld_address_reg)
,   .ld_reg_y(ld_reg_y)
,   .ld_reg_z(ld_reg_z)
,   .sel_dbus_mux(sel_dbus_mux)
,   .sel_bus2_mux(sel_bus2_mux)
);

  control_unit controller(
    .clk(clk)
,   .clr(clr)

,   .pstate(pstate)
,   .ld_r0(ld_r0)
,   .ld_r1(ld_r1)
,   .ld_r2(ld_r2)
,   .ld_r3(ld_r3)
,   .ld_pc(ld_pc)
,   .inc_pc(inc_pc)
,   .sel_dbus_mux(sel_dbus_mux)
,   .sel_bus2_mux(sel_bus2_mux)
,   .ld_ir(ld_ir)
,   .ld_address_reg(ld_address_reg)
,   .ld_reg_y(ld_reg_y)
,   .ld_reg_z(ld_reg_z)
,   .read(rd)
,   .write(wr)
,   .instruction(instruction)
,   .regR0(regR0)
,   .zero(zero)
,   .carry(carry)
,   .sig_halt(sig_halt)
);

endmodule