data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/vfmau/rtl/ct_vfmau_ff1_10bit.v
data/verilator_xmls/e3b9ec34-9cc3-4b28-8643-498a9d5e48e8.xml
module ct_vfmau_ff1_10bit(
  ff1_data,
  ff1_result
);


input   [9:0]  ff1_data;  
output  [3:0]  ff1_result; 


reg     [3:0]  ff1_result; 


wire    [9:0]  ff1_data;  



always @( ff1_data[9:0])
begin
casez(ff1_data[9:0])
  10'b1?????????: ff1_result[3:0] = 4'd1;
  10'b01????????: ff1_result[3:0] = 4'd2;
  10'b001???????: ff1_result[3:0] = 4'd3;
  10'b0001??????: ff1_result[3:0] = 4'd4;
  10'b00001?????: ff1_result[3:0] = 4'd5;
  10'b000001????: ff1_result[3:0] = 4'd6;
  10'b0000001???: ff1_result[3:0] = 4'd7;
  10'b00000001??: ff1_result[3:0] = 4'd8;
  10'b000000001?: ff1_result[3:0] = 4'd9;
  10'b0000000001: ff1_result[3:0] = 4'd10;
  default       : ff1_result[3:0] = {4{1'bx}};
endcase

end


endmodule
module ct_vfmau_ff1_10bit(
  ff1_data,
  ff1_result
);



input   [9:0]  ff1_data;  
output  [3:0]  ff1_result; 


reg     [3:0]  ff1_result; 


wire    [9:0]  ff1_data;  



always @( ff1_data[9:0])
begin
casez(ff1_data[9:0])
  10'b1?????????: ff1_result[3:0] = 4'd1;
  10'b01????????: ff1_result[3:0] = 4'd2;
  10'b001???????: ff1_result[3:0] = 4'd3;
  10'b0001??????: ff1_result[3:0] = 4'd4;
  10'b00001?????: ff1_result[3:0] = 4'd5;
  10'b000001????: ff1_result[3:0] = 4'd6;
  10'b0000001???: ff1_result[3:0] = 4'd7;
  10'b00000001??: ff1_result[3:0] = 4'd8;
  10'b000000001?: ff1_result[3:0] = 4'd9;
  10'b0000000001: ff1_result[3:0] = 4'd10;
  default       : ff1_result[3:0] = {4{1'bx}};
endcase

end


endmodule