data/full_repos/permissive/422421961/lib/tb/read_array_signal.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/422421961/lib/tb/read_array_signal.v:31: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module read_array_signal#(
parameter BIT_W=10,
parameter len=256,
parameter FILENAME="../../pat/dsss/i.dat",
parameter offset=0
)(
	output [BIT_W*len-1:0] sig_out
);
integer signal_FILE; 
integer i,cnt;
reg signed [BIT_W-1:0]  mem[len-1:0];
initial	begin
  $display("reading: %s....",FILENAME);
	#`DLY_1;
  signal_FILE = $fopen(FILENAME,"rb");
  if (signal_FILE ==0) begin
      $display("Error at opening file: %s",FILENAME);
      $stop;
  end

	for(i=0;i<offset;i=i+1)begin
  	if(!$feof(signal_FILE))
  	 cnt=$fscanf(signal_FILE, "%d\n", mem[0]);
	end	
	for(i=0;i<len;i=i+1)begin
  	if(!$feof(signal_FILE))
  	 cnt=$fscanf(signal_FILE, "%d\n", mem[i]);
	end	
end

genvar n;
generate
	for(n=0;n<256;n=n+1)begin
		assign sig_out[(n+1)*BIT_W-1:n*BIT_W]=mem[n];
	end
endgenerate

endmodule
module read_array_signal#(
parameter BIT_W=10,
parameter len=256,
parameter FILENAME="../../pat/dsss/i.dat",
parameter offset=0
)(
	output [BIT_W*len-1:0] sig_out
);

integer signal_FILE; 
integer i,cnt;
reg signed [BIT_W-1:0]  mem[len-1:0];
initial	begin
  $display("reading: %s....",FILENAME);
	#`DLY_1;
  signal_FILE = $fopen(FILENAME,"rb");
  if (signal_FILE ==0) begin
      $display("Error at opening file: %s",FILENAME);
      $stop;
  end

	for(i=0;i<offset;i=i+1)begin
  	if(!$feof(signal_FILE))
  	 cnt=$fscanf(signal_FILE, "%d\n", mem[0]);
	end	
	for(i=0;i<len;i=i+1)begin
  	if(!$feof(signal_FILE))
  	 cnt=$fscanf(signal_FILE, "%d\n", mem[i]);
	end	
end

genvar n;
generate
	for(n=0;n<256;n=n+1)begin
		assign sig_out[(n+1)*BIT_W-1:n*BIT_W]=mem[n];
	end
endgenerate

endmodule