data/full_repos/permissive/506562943/HDLBits/Verilog Language/Modules/module_fadd.v
1: b'%Error: Cannot find file containing module: Language/Modules,data/full_repos/permissive/506562943\n        ... Looked in:\n             data/full_repos/permissive/506562943/HDLBits/Verilog/Language/Modules,data/full_repos/permissive/506562943\n             data/full_repos/permissive/506562943/HDLBits/Verilog/Language/Modules,data/full_repos/permissive/506562943.v\n             data/full_repos/permissive/506562943/HDLBits/Verilog/Language/Modules,data/full_repos/permissive/506562943.sv\n             Language/Modules,data/full_repos/permissive/506562943\n             Language/Modules,data/full_repos/permissive/506562943.v\n             Language/Modules,data/full_repos/permissive/506562943.sv\n             obj_dir/Language/Modules,data/full_repos/permissive/506562943\n             obj_dir/Language/Modules,data/full_repos/permissive/506562943.v\n             obj_dir/Language/Modules,data/full_repos/permissive/506562943.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/506562943/HDLBits/Verilog\n%Error: Cannot find file containing module: Language/Modules/module_fadd.v\n%Error: Exiting due to 3 error(s)\n'
module top_module (
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);

    wire [15:0] lo_result, hi_result;
    wire lo_cout;
    
    assign sum = {hi_result, lo_result};
    
    add16 u_add16_lo(a[15:0], b[15:0], 0, lo_result, lo_cout);
    add16 u_add16_hi(a[31:16], b[31:16], lo_cout, hi_result);

endmodule
module top_module (
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);


    wire [15:0] lo_result, hi_result;
    wire lo_cout;
    
    assign sum = {hi_result, lo_result};
    
    add16 u_add16_lo(a[15:0], b[15:0], 0, lo_result, lo_cout);
    add16 u_add16_hi(a[31:16], b[31:16], lo_cout, hi_result);

endmodule