data/full_repos/permissive/445357518/alu_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/445357518/alu_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n  Ain=16\'d3; Bin=16\'d2;  ALUop=2\'b00; #10;\n                                      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/445357518/alu_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n  Ain=16\'d5; Bin=16\'d9; #10; \n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/alu_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n  Ain= -16\'d1; Bin=16\'d2; #10; \n                          ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/alu_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n  Ain=16\'d0; Bin=16\'d0; #10;\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/alu_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n  Ain=16\'d20; Bin=16\'d19;  ALUop=2\'b01; #10;\n                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/alu_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n  Ain=16\'d15; Bin=16\'d5;  #10;\n                          ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/alu_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n  Ain=16\'d1; Bin=16\'d2;  #10;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/alu_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n  Ain=16\'d3; Bin=16\'d3;  #10;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/alu_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n  Ain=16\'b1000101001011111; Bin=16\'b1000101001011111;  ALUop=2\'b10; #10;\n                                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/alu_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n  Ain=16\'b1111010101100110; Bin=16\'b0110111111110110;  #10;\n                                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/alu_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n  Ain={16{1\'b1}}; Bin={16{1\'b0}};  #10;\n                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/alu_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n  Ain=16\'d5; Bin=16\'b1101010111010011;  ALUop=2\'b11; #10;\n                                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/alu_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n  Ain=16\'d24; Bin=16\'b1100111010110110;  #10;\n                                         ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/alu_tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n  Ain={16\'d38}; Bin={16{1\'b1}};  #10;\n                                 ^\n%Error: data/full_repos/permissive/445357518/alu_tb.v:8: Cannot find file containing module: \'ALU\'\nALU DUT(Ain,Bin,ALUop,out,Z);\n^~~\n        ... Looked in:\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/ALU\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/ALU.v\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/ALU.sv\n             ALU\n             ALU.v\n             ALU.sv\n             obj_dir/ALU\n             obj_dir/ALU.v\n             obj_dir/ALU.sv\n%Error: Exiting due to 1 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ALU_tb;
 reg err = 1'b0;
 reg [15:0] Ain, Bin;
 reg [1:0] ALUop;
 wire [15:0] out;
 wire Z;

ALU DUT(Ain,Bin,ALUop,out,Z);


task check;
 input expect_z;
 input [15:0] expect_out;
begin

if(Z !== expect_z) begin
  $display ("Expected: %b but: %b", expect_z,Z);
  err=1;
end

if(out !== expect_out) begin
  $display ("Expected: %b but: %b", expect_out,out);
  err=1;
end

end
endtask

initial begin
  err=1'b0;


  $display("Check the '+' operation (1)");
  Ain=16'd3; Bin=16'd2;  ALUop=2'b00; #10;
  check(1'b0, 16'd5);

  $display("Check the '+' operation (2)");
  Ain=16'd5; Bin=16'd9; #10; 
  check(1'b0, 16'd14);

  $display("Check the '+' operation (3)");
  Ain= -16'd1; Bin=16'd2; #10; 
  check(1'b0, 16'd1);


  $display("Check Z ");
  Ain=16'd0; Bin=16'd0; #10;
  check(1'b1, 16'd0);


  $display("Check the '-' operation (1)");
  Ain=16'd20; Bin=16'd19;  ALUop=2'b01; #10;
  check(1'b0, 16'd1);
  
  
  $display("Check the '-' operation (2)");
  Ain=16'd15; Bin=16'd5;  #10;
  check(1'b0, 16'd10);
  
  $display("Check the '-' operation (3)");
  Ain=16'd1; Bin=16'd2;  #10;
  check(1'b0, {16{1'b1}});


  $display("Check Z ");
  Ain=16'd3; Bin=16'd3;  #10;
  check(1'b1, 16'd0);


  $display("Check the '&' operation (1)");
  Ain=16'b1000101001011111; Bin=16'b1000101001011111;  ALUop=2'b10; #10;
  check(1'b0, 16'b1000101001011111);


  $display("Check the '&' operation (2)");
  Ain=16'b1111010101100110; Bin=16'b0110111111110110;  #10;
  check(1'b0, 16'b0110010101100110);


  $display("Check Z ");
  Ain={16{1'b1}}; Bin={16{1'b0}};  #10;
  check(1'b1, 16'd0);



  $display("Check the '~B' operation (1)");
  Ain=16'd5; Bin=16'b1101010111010011;  ALUop=2'b11; #10;
  check(1'b0, 16'b0010101000101100);


  $display("Check the '~B' operation (2)");
  Ain=16'd24; Bin=16'b1100111010110110;  #10;
  check(1'b0, 16'b0011000101001001);


  $display("Check Z ");
  Ain={16'd38}; Bin={16{1'b1}};  #10;
  check(1'b1, 16'd0);

   
  if(~err) $display("Passed");
  else $display("Failed");

end

endmodule
module ALU_tb;

 reg err = 1'b0;
 reg [15:0] Ain, Bin;
 reg [1:0] ALUop;
 wire [15:0] out;
 wire Z;

ALU DUT(Ain,Bin,ALUop,out,Z);


task check;
 input expect_z;
 input [15:0] expect_out;
begin

if(Z !== expect_z) begin
  $display ("Expected: %b but: %b", expect_z,Z);
  err=1;
end

if(out !== expect_out) begin
  $display ("Expected: %b but: %b", expect_out,out);
  err=1;
end

end
endtask

initial begin
  err=1'b0;


  $display("Check the '+' operation (1)");
  Ain=16'd3; Bin=16'd2;  ALUop=2'b00; #10;
  check(1'b0, 16'd5);

  $display("Check the '+' operation (2)");
  Ain=16'd5; Bin=16'd9; #10; 
  check(1'b0, 16'd14);

  $display("Check the '+' operation (3)");
  Ain= -16'd1; Bin=16'd2; #10; 
  check(1'b0, 16'd1);


  $display("Check Z ");
  Ain=16'd0; Bin=16'd0; #10;
  check(1'b1, 16'd0);


  $display("Check the '-' operation (1)");
  Ain=16'd20; Bin=16'd19;  ALUop=2'b01; #10;
  check(1'b0, 16'd1);
  
  
  $display("Check the '-' operation (2)");
  Ain=16'd15; Bin=16'd5;  #10;
  check(1'b0, 16'd10);
  
  $display("Check the '-' operation (3)");
  Ain=16'd1; Bin=16'd2;  #10;
  check(1'b0, {16{1'b1}});


  $display("Check Z ");
  Ain=16'd3; Bin=16'd3;  #10;
  check(1'b1, 16'd0);


  $display("Check the '&' operation (1)");
  Ain=16'b1000101001011111; Bin=16'b1000101001011111;  ALUop=2'b10; #10;
  check(1'b0, 16'b1000101001011111);


  $display("Check the '&' operation (2)");
  Ain=16'b1111010101100110; Bin=16'b0110111111110110;  #10;
  check(1'b0, 16'b0110010101100110);


  $display("Check Z ");
  Ain={16{1'b1}}; Bin={16{1'b0}};  #10;
  check(1'b1, 16'd0);



  $display("Check the '~B' operation (1)");
  Ain=16'd5; Bin=16'b1101010111010011;  ALUop=2'b11; #10;
  check(1'b0, 16'b0010101000101100);


  $display("Check the '~B' operation (2)");
  Ain=16'd24; Bin=16'b1100111010110110;  #10;
  check(1'b0, 16'b0011000101001001);


  $display("Check Z ");
  Ain={16'd38}; Bin={16{1'b1}};  #10;
  check(1'b1, 16'd0);

   
  if(~err) $display("Passed");
  else $display("Failed");

end

endmodule