data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/cmprnd3_tb.v
1: b'%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/cmprnd3_tb.v:19: Cannot find include file: timescale_inc.v\n`include "timescale_inc.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze,data/full_repos/permissive/487568919/timescale_inc.v\n             data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze,data/full_repos/permissive/487568919/timescale_inc.v.v\n             data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze,data/full_repos/permissive/487568919/timescale_inc.v.sv\n             timescale_inc.v\n             timescale_inc.v.v\n             timescale_inc.v.sv\n             obj_dir/timescale_inc.v\n             obj_dir/timescale_inc.v.v\n             obj_dir/timescale_inc.v.sv\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/cmprnd3_tb.v:20: Cannot find include file: pacoblaze_inc.v\n`include "pacoblaze_inc.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/cmprnd3_tb.v:29: Define or directive not defined: \'`code_depth\'\nwire [`code_depth-1:0] addr_0, addr_1;  \n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/cmprnd3_tb.v:30: Define or directive not defined: \'`operand_width\'\nreg [`operand_width-1:0] port_0[0:`port_size-1], port_1[0:`port_size-1];\n     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/cmprnd3_tb.v:30: Define or directive not defined: \'`port_size\'\nreg [`operand_width-1:0] port_0[0:`port_size-1], port_1[0:`port_size-1];\n                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/cmprnd3_tb.v:30: Define or directive not defined: \'`port_size\'\nreg [`operand_width-1:0] port_0[0:`port_size-1], port_1[0:`port_size-1];\n                                                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/cmprnd3_tb.v:31: Define or directive not defined: \'`operand_width\'\nwire [`operand_width-1:0] pid_0, pid_1, pout_0, pout_1;  \n      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/cmprnd3_tb.v:34: Define or directive not defined: \'`code_width\'\nwire [`code_width-1:0] din_0, din_1;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/cmprnd3_tb.v:35: Define or directive not defined: \'`operand_width\'\nwire [`operand_width-1:0] pin_0 = port_0[pid_0], pin_1 = port_1[pid_1];  \n      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/cmprnd3_tb.v:38: Define or directive not defined: \'`code_width\'\nblockram #(.width(`code_width),.depth(`code_depth)) rom_0(\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/cmprnd3_tb.v:38: Define or directive not defined: \'`code_depth\'\nblockram #(.width(`code_width),.depth(`code_depth)) rom_0(\n                                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/cmprnd3_tb.v:64: Define or directive not defined: \'`code_width\'\nblockram #(.width(`code_width),.depth(`code_depth)) rom_1(\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/cmprnd3_tb.v:64: Define or directive not defined: \'`code_depth\'\nblockram #(.width(`code_width),.depth(`code_depth)) rom_1(\n                                      ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/cmprnd3_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\nalways #(tck/2) clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/cmprnd3_tb.v:109: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(-1, cmprnd3_tb);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/cmprnd3_tb.v:110: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("cmprnd3_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/cmprnd3_tb.v:118: Define or directive not defined: \'`code_size\'\n for (i=0; i<`code_size; i=i+1) begin\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/cmprnd3_tb.v:118: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n for (i=0; i<`code_size; i=i+1) begin\n                       ^\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/cmprnd3_tb.v:118: syntax error, unexpected \')\', expecting \';\'\n for (i=0; i<`code_size; i=i+1) begin\n                              ^\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/cmprnd3_tb.v:119: Define or directive not defined: \'`code_width\'\n  rom_0.ram[i] = {$random} % (1<<`code_width);\n                                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/cmprnd3_tb.v:124: Define or directive not defined: \'`port_size\'\n for (i=0; i<`port_size; i=i+1) begin\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/cmprnd3_tb.v:124: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n for (i=0; i<`port_size; i=i+1) begin\n                       ^\n%Error: Cannot continue\n'
module cmprnd3_tb;

parameter tck = 10, program_cycles = `TEST_CYCLES;

defparam glbl.ROC_WIDTH = 0;

reg clk, rst, irq;
wire [`code_depth-1:0] addr_0, addr_1;
reg [`operand_width-1:0] port_0[0:`port_size-1], port_1[0:`port_size-1];
wire [`operand_width-1:0] pid_0, pid_1, pout_0, pout_1;
wire ren_0, ren_1, wen_0, wen_1, iak_0, iak_1;

wire [`code_width-1:0] din_0, din_1;
wire [`operand_width-1:0] pin_0 = port_0[pid_0], pin_1 = port_1[pid_1];


blockram #(.width(`code_width),.depth(`code_depth)) rom_0(
	.clk(clk),
	.rst(rst),
	.enb(1),
	.wen(0),
	.addr(addr_0),
	.din(0),
	.dout(din_0)
);


pacoblaze3 dut_0(
	.clk(clk),
	.reset(rst),
	.address(addr_0),
	.instruction(din_0),
	.port_id(pid_0),
	.read_strobe(ren_0),
	.write_strobe(wen_0),
	.in_port(pin_0),
	.out_port(pout_0),
	.interrupt(irq),
	.interrupt_ack(iak_0)
);


blockram #(.width(`code_width),.depth(`code_depth)) rom_1(
	.clk(clk),
	.rst(rst),
	.enb(1),
	.wen(0),
	.addr(addr_1),
	.din(0),
	.dout(din_1)
);


kcpsm3 dut_1(
	.clk(clk),
	.reset(rst),
	.address(addr_1),
	.instruction(din_1),
	.port_id(pid_1),
	.read_strobe(ren_1),
	.write_strobe(wen_1),
	.in_port(pin_1),
	.out_port(pout_1),
	.interrupt(irq),
	.interrupt_ack(iak_1)
);


always #(tck/2) clk = ~clk;


always @(posedge clk)	begin
	if (wen_0) port_0[pid_0] <= pout_0;
	if (wen_1) port_1[pid_1] <= pout_1;
end

always @(negedge clk) begin



	$display("%h:%h %h:%h", addr_0, din_0, addr_1, din_1);

	if (addr_0 != addr_1) $display("***address mismatch***");
end


initial begin
	$dumpvars(-1, cmprnd3_tb);
	$dumpfile("cmprnd3_tb.vcd");
end


integer i;
initial begin


	for (i=0; i<`code_size; i=i+1) begin
		rom_0.ram[i] = {$random} % (1<<`code_width);
		rom_1.ram[i] = rom_0.ram[i];
	end


	for (i=0; i<`port_size; i=i+1) begin
		port_0[i] = i;
		port_1[i] = i;
	end

	clk = 0; rst = 1; irq = 0;
	#(tck*3);
	@(negedge clk) rst = 0;


	#(tck*`TEST_IRQ);
	@(negedge clk) irq = 1;
	@(negedge clk) ;
	@(negedge clk) irq = 0;

	#(program_cycles*tck) $finish;
end

endmodule
module cmprnd3_tb;


parameter tck = 10, program_cycles = `TEST_CYCLES;

defparam glbl.ROC_WIDTH = 0;

reg clk, rst, irq;
wire [`code_depth-1:0] addr_0, addr_1;
reg [`operand_width-1:0] port_0[0:`port_size-1], port_1[0:`port_size-1];
wire [`operand_width-1:0] pid_0, pid_1, pout_0, pout_1;
wire ren_0, ren_1, wen_0, wen_1, iak_0, iak_1;

wire [`code_width-1:0] din_0, din_1;
wire [`operand_width-1:0] pin_0 = port_0[pid_0], pin_1 = port_1[pid_1];


blockram #(.width(`code_width),.depth(`code_depth)) rom_0(
	.clk(clk),
	.rst(rst),
	.enb(1),
	.wen(0),
	.addr(addr_0),
	.din(0),
	.dout(din_0)
);


pacoblaze3 dut_0(
	.clk(clk),
	.reset(rst),
	.address(addr_0),
	.instruction(din_0),
	.port_id(pid_0),
	.read_strobe(ren_0),
	.write_strobe(wen_0),
	.in_port(pin_0),
	.out_port(pout_0),
	.interrupt(irq),
	.interrupt_ack(iak_0)
);


blockram #(.width(`code_width),.depth(`code_depth)) rom_1(
	.clk(clk),
	.rst(rst),
	.enb(1),
	.wen(0),
	.addr(addr_1),
	.din(0),
	.dout(din_1)
);


kcpsm3 dut_1(
	.clk(clk),
	.reset(rst),
	.address(addr_1),
	.instruction(din_1),
	.port_id(pid_1),
	.read_strobe(ren_1),
	.write_strobe(wen_1),
	.in_port(pin_1),
	.out_port(pout_1),
	.interrupt(irq),
	.interrupt_ack(iak_1)
);


always #(tck/2) clk = ~clk;


always @(posedge clk)	begin
	if (wen_0) port_0[pid_0] <= pout_0;
	if (wen_1) port_1[pid_1] <= pout_1;
end

always @(negedge clk) begin



	$display("%h:%h %h:%h", addr_0, din_0, addr_1, din_1);

	if (addr_0 != addr_1) $display("***address mismatch***");
end


initial begin
	$dumpvars(-1, cmprnd3_tb);
	$dumpfile("cmprnd3_tb.vcd");
end


integer i;
initial begin


	for (i=0; i<`code_size; i=i+1) begin
		rom_0.ram[i] = {$random} % (1<<`code_width);
		rom_1.ram[i] = rom_0.ram[i];
	end


	for (i=0; i<`port_size; i=i+1) begin
		port_0[i] = i;
		port_1[i] = i;
	end

	clk = 0; rst = 1; irq = 0;
	#(tck*3);
	@(negedge clk) rst = 0;


	#(tck*`TEST_IRQ);
	@(negedge clk) irq = 1;
	@(negedge clk) ;
	@(negedge clk) irq = 0;

	#(program_cycles*tck) $finish;
end

endmodule