data/full_repos/permissive/472097099/verilog/dv/4ft4_fib/4ft4_fib_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/472097099/verilog/dv/4ft4_fib/4ft4_fib_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n    always #12.5 clock <= (clock === 1\'b0);\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/472097099/verilog/dv/4ft4_fib/4ft4_fib_tb.v:50: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("4ft4_fib.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/472097099/verilog/dv/4ft4_fib/4ft4_fib_tb.v:51: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, tb_4ft4_fib);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/472097099/verilog/dv/4ft4_fib/4ft4_fib_tb.v:55: Unsupported or unknown PLI call: $dumpvars\n            $dumpvars(0, uut.mprj.mprj.sys.cpu.pc_stack.program_counters[i]);\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/472097099/verilog/dv/4ft4_fib/4ft4_fib_tb.v:58: Unsupported or unknown PLI call: $dumpvars\n            $dumpvars(0, uut.mprj.mprj.sys.cpu.datapath.registers[i]);\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/472097099/verilog/dv/4ft4_fib/4ft4_fib_tb.v:64: syntax error, unexpected \'@\'\n            repeat (1000) @(posedge clock);\n                          ^\n%Error: data/full_repos/permissive/472097099/verilog/dv/4ft4_fib/4ft4_fib_tb.v:66: Unsupported: $fflush of all handles does not map to C++.\n            $fflush();\n            ^~~~~~~\n%Error: data/full_repos/permissive/472097099/verilog/dv/4ft4_fib/4ft4_fib_tb.v:79: Unsupported: wait statements\n       wait(checkbits == 16\'hAB60);\n       ^~~~\n%Error: data/full_repos/permissive/472097099/verilog/dv/4ft4_fib/4ft4_fib_tb.v:81: Unsupported: wait statements\n        wait(checkbits == 16\'h1337);\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/472097099/verilog/dv/4ft4_fib/4ft4_fib_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n        #2000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/472097099/verilog/dv/4ft4_fib/4ft4_fib_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n        #100000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/472097099/verilog/dv/4ft4_fib/4ft4_fib_tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n        #200;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/472097099/verilog/dv/4ft4_fib/4ft4_fib_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n        #200;\n        ^\n%Error: Exiting due to 8 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_4ft4_fib;
    reg clock;
    reg RSTB;
    reg CSB;
    reg power1, power2;
    reg power3, power4;

    wire gpio;
    wire [37:0] mprj_io;
    wire [7:0] mprj_io_0;
    wire [15:0] checkbits;

    assign checkbits = mprj_io[31:16];

    assign mprj_io[3] = 1'b1;





    always #12.5 clock <= (clock === 1'b0);

    initial begin
        clock = 0;
    end

    integer i;

    initial begin
        $dumpfile("4ft4_fib.vcd");
        $dumpvars(0, tb_4ft4_fib);

        `ifndef GL
        for (i = 0; i < 3; i++) begin
            $dumpvars(0, uut.mprj.mprj.sys.cpu.pc_stack.program_counters[i]);
        end
        for (i = 0; i < 16; i++) begin
            $dumpvars(0, uut.mprj.mprj.sys.cpu.datapath.registers[i]);
        end
        `endif


        repeat (60) begin
            repeat (1000) @(posedge clock);
            $display("+1000 cycles");
            $fflush();
        end
        $display("%c[1;31m",27);
        `ifdef GL
            $display ("Monitor: Timeout, 4ft4 fibonacci test failed (GL)");
        `else
            $display ("Monitor: Timeout, 4ft4 fibonacci test failed (RTL)");
        `endif
        $display("%c[0m",27);
        $finish;
    end

    initial begin
       wait(checkbits == 16'hAB60);
        $display("Monitor: 4ft4 fibonacci test started");
        wait(checkbits == 16'h1337);
        `ifdef GL
            $display("Monitor: 4ft4 fibonacci test passed (GL)");
        `else
            $display("Monitor: 4ft4 fibonacci test passed (RTL)");
        `endif
        $finish;
    end

    initial begin
        RSTB <= 1'b0;
        CSB  <= 1'b1;
        #2000;
        RSTB <= 1'b1;
        #100000;
        CSB = 1'b0;
    end

    initial begin
        power1 <= 1'b0;
        power2 <= 1'b0;
        #200;
        power1 <= 1'b1;
        #200;
        power2 <= 1'b1;
    end

    wire flash_csb;
    wire flash_clk;
    wire flash_io0;
    wire flash_io1;

    wire VDD3V3 = power1;
    wire VDD1V8 = power2;
    wire USER_VDD3V3 = power3;
    wire USER_VDD1V8 = power4;
    wire VSS = 1'b0;

    caravel uut (
        .vddio      (VDD3V3),
        .vddio_2  (VDD3V3),
        .vssio      (VSS),
        .vssio_2  (VSS),
        .vdda      (VDD3V3),
        .vssa      (VSS),
        .vccd      (VDD1V8),
        .vssd      (VSS),
        .vdda1    (VDD3V3),
        .vdda1_2  (VDD3V3),
        .vdda2    (VDD3V3),
        .vssa1      (VSS),
        .vssa1_2  (VSS),
        .vssa2      (VSS),
        .vccd1      (VDD1V8),
        .vccd2      (VDD1V8),
        .vssd1      (VSS),
        .vssd2      (VSS),
        .clock    (clock),
        .gpio     (gpio),
        .mprj_io  (mprj_io),
        .flash_csb(flash_csb),
        .flash_clk(flash_clk),
        .flash_io0(flash_io0),
        .flash_io1(flash_io1),
        .resetb      (RSTB)
    );

    spiflash #(
        .FILENAME("4ft4_fib.hex")
    ) spiflash (
        .csb(flash_csb),
        .clk(flash_clk),
        .io0(flash_io0),
        .io1(flash_io1),
        .io2(),
        .io3()
    );

endmodule
module tb_4ft4_fib;

    reg clock;
    reg RSTB;
    reg CSB;
    reg power1, power2;
    reg power3, power4;

    wire gpio;
    wire [37:0] mprj_io;
    wire [7:0] mprj_io_0;
    wire [15:0] checkbits;

    assign checkbits = mprj_io[31:16];

    assign mprj_io[3] = 1'b1;





    always #12.5 clock <= (clock === 1'b0);

    initial begin
        clock = 0;
    end

    integer i;

    initial begin
        $dumpfile("4ft4_fib.vcd");
        $dumpvars(0, tb_4ft4_fib);

        `ifndef GL
        for (i = 0; i < 3; i++) begin
            $dumpvars(0, uut.mprj.mprj.sys.cpu.pc_stack.program_counters[i]);
        end
        for (i = 0; i < 16; i++) begin
            $dumpvars(0, uut.mprj.mprj.sys.cpu.datapath.registers[i]);
        end
        `endif


        repeat (60) begin
            repeat (1000) @(posedge clock);
            $display("+1000 cycles");
            $fflush();
        end
        $display("%c[1;31m",27);
        `ifdef GL
            $display ("Monitor: Timeout, 4ft4 fibonacci test failed (GL)");
        `else
            $display ("Monitor: Timeout, 4ft4 fibonacci test failed (RTL)");
        `endif
        $display("%c[0m",27);
        $finish;
    end

    initial begin
       wait(checkbits == 16'hAB60);
        $display("Monitor: 4ft4 fibonacci test started");
        wait(checkbits == 16'h1337);
        `ifdef GL
            $display("Monitor: 4ft4 fibonacci test passed (GL)");
        `else
            $display("Monitor: 4ft4 fibonacci test passed (RTL)");
        `endif
        $finish;
    end

    initial begin
        RSTB <= 1'b0;
        CSB  <= 1'b1;
        #2000;
        RSTB <= 1'b1;
        #100000;
        CSB = 1'b0;
    end

    initial begin
        power1 <= 1'b0;
        power2 <= 1'b0;
        #200;
        power1 <= 1'b1;
        #200;
        power2 <= 1'b1;
    end

    wire flash_csb;
    wire flash_clk;
    wire flash_io0;
    wire flash_io1;

    wire VDD3V3 = power1;
    wire VDD1V8 = power2;
    wire USER_VDD3V3 = power3;
    wire USER_VDD1V8 = power4;
    wire VSS = 1'b0;

    caravel uut (
        .vddio      (VDD3V3),
        .vddio_2  (VDD3V3),
        .vssio      (VSS),
        .vssio_2  (VSS),
        .vdda      (VDD3V3),
        .vssa      (VSS),
        .vccd      (VDD1V8),
        .vssd      (VSS),
        .vdda1    (VDD3V3),
        .vdda1_2  (VDD3V3),
        .vdda2    (VDD3V3),
        .vssa1      (VSS),
        .vssa1_2  (VSS),
        .vssa2      (VSS),
        .vccd1      (VDD1V8),
        .vccd2      (VDD1V8),
        .vssd1      (VSS),
        .vssd2      (VSS),
        .clock    (clock),
        .gpio     (gpio),
        .mprj_io  (mprj_io),
        .flash_csb(flash_csb),
        .flash_clk(flash_clk),
        .flash_io0(flash_io0),
        .flash_io1(flash_io1),
        .resetb      (RSTB)
    );

    spiflash #(
        .FILENAME("4ft4_fib.hex")
    ) spiflash (
        .csb(flash_csb),
        .clk(flash_clk),
        .io0(flash_io0),
        .io1(flash_io1),
        .io2(),
        .io3()
    );

endmodule