data/full_repos/permissive/527249789/src/div.v
1: b'%Error: data/full_repos/permissive/527249789/src/div.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/defines.v\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/defines.v.v\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/527249789/src/div.v:8: Define or directive not defined: \'`RegBus\'\n    input   [`RegBus]                   operand1_i,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/div.v:8: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input   [`RegBus]                   operand1_i,\n                    ^\n%Error: data/full_repos/permissive/527249789/src/div.v:9: Define or directive not defined: \'`RegBus\'\n    input   [`RegBus]                   operand2_i,\n             ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/div.v:13: Define or directive not defined: \'`DoubleRegBus\'\n    output  reg[`DoubleRegBus]          result_o,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/div.v:23: syntax error, unexpected assign\nassign div_temp = {1\'b0, dividend[63:32]} - {1\'b0, divisor};\n^~~~~~\n%Error: data/full_repos/permissive/527249789/src/div.v:26: Define or directive not defined: \'`RstEnable\'\n    if (resetn == `RstEnable) begin\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/div.v:27: Define or directive not defined: \'`DivFree\'\n        state <= `DivFree;\n                 ^~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/div.v:28: Define or directive not defined: \'`DivResultNotReady\'\n        ready_o <= `DivResultNotReady;\n                   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/div.v:29: Define or directive not defined: \'`ZeroWord\'\n        result_o <= {`ZeroWord, `ZeroWord};\n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/div.v:29: Define or directive not defined: \'`ZeroWord\'\n        result_o <= {`ZeroWord, `ZeroWord};\n                                ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/div.v:32: Define or directive not defined: \'`DivFree\'\n            `DivFree: begin\n            ^~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/div.v:33: Define or directive not defined: \'`DivStart\'\n                if ((start_i == `DivStart) && (annul_i == `FlushDisable)) begin\n                                ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/div.v:33: Define or directive not defined: \'`FlushDisable\'\n                if ((start_i == `DivStart) && (annul_i == `FlushDisable)) begin\n                                                          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/div.v:34: Define or directive not defined: \'`ZeroWord\'\n                    if (operand2_i == `ZeroWord) begin\n                                      ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/div.v:35: Define or directive not defined: \'`DivByZero\'\n                        state <= `DivByZero;\n                                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/div.v:37: Define or directive not defined: \'`DivOn\'\n                        state <= `DivOn;\n                                 ^~~~~~\n%Error: data/full_repos/permissive/527249789/src/div.v:53: Define or directive not defined: \'`DivResultNotReady\'\n                    ready_o <= `DivResultNotReady;\n                               ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/div.v:54: Define or directive not defined: \'`ZeroWord\'\n                    result_o <= {`ZeroWord, `ZeroWord};\n                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/div.v:54: Define or directive not defined: \'`ZeroWord\'\n                    result_o <= {`ZeroWord, `ZeroWord};\n                                            ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/div.v:57: Define or directive not defined: \'`DivByZero\'\n            `DivByZero: begin\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/div.v:58: Define or directive not defined: \'`ZeroWord\'\n                dividend <= {`ZeroWord, `ZeroWord};\n                             ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/div.v:58: Define or directive not defined: \'`ZeroWord\'\n                dividend <= {`ZeroWord, `ZeroWord};\n                                        ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/div.v:59: Define or directive not defined: \'`DivEnd\'\n                state <= `DivEnd;\n                         ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/div.v:61: Define or directive not defined: \'`DivOn\'\n            `DivOn: begin\n            ^~~~~~\n%Error: data/full_repos/permissive/527249789/src/div.v:62: Define or directive not defined: \'`FlushDisable\'\n                if (annul_i == `FlushDisable) begin\n                               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/div.v:77: Define or directive not defined: \'`DivEnd\'\n                        state <= `DivEnd;\n                                 ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/div.v:81: Define or directive not defined: \'`DivFree\'\n                    state <= `DivFree;\n                             ^~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/div.v:84: Define or directive not defined: \'`DivEnd\'\n            `DivEnd: begin\n            ^~~~~~~\n%Error: data/full_repos/permissive/527249789/src/div.v:86: Define or directive not defined: \'`DivResultReady\'\n                ready_o <= `DivResultReady;\n                           ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/div.v:87: Define or directive not defined: \'`DivStop\'\n                if (start_i == `DivStop) begin\n                               ^~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/div.v:88: Define or directive not defined: \'`DivFree\'\n                    state <= `DivFree;\n                             ^~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/div.v:89: Define or directive not defined: \'`DivResultNotReady\'\n                    ready_o <= `DivResultNotReady;\n                               ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/div.v:90: Define or directive not defined: \'`ZeroWord\'\n                    result_o <= {`ZeroWord, `ZeroWord};\n                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/527249789/src/div.v:90: Define or directive not defined: \'`ZeroWord\'\n                    result_o <= {`ZeroWord, `ZeroWord};\n                                            ^~~~~~~~~\n%Error: Exiting due to 35 error(s)\n'
module div(
    input                               clk,
    input                               resetn,

    input                               signed_div_i,
    input   [`RegBus]                   operand1_i,
    input   [`RegBus]                   operand2_i,
    input                               start_i,
    input                               annul_i,

    output  reg[`DoubleRegBus]          result_o,
    output  reg                         ready_o
);

wire[32:0] div_temp;
reg[64:0] dividend;
reg[5:0] cnt;
reg[1:0] state;
reg[31:0] divisor;

assign div_temp = {1'b0, dividend[63:32]} - {1'b0, divisor};

always @(posedge clk) begin
    if (resetn == `RstEnable) begin
        state <= `DivFree;
        ready_o <= `DivResultNotReady;
        result_o <= {`ZeroWord, `ZeroWord};
    end else begin
        case (state)
            `DivFree: begin
                if ((start_i == `DivStart) && (annul_i == `FlushDisable)) begin
                    if (operand2_i == `ZeroWord) begin
                        state <= `DivByZero;
                    end else begin
                        state <= `DivOn;
                        cnt <= 6'b000000;
                        dividend[63:33] <= 31'b0;
                        dividend[0] <= 1'b0;
                        if ((signed_div_i == 1'b1) && (operand1_i[31] == 1'b1)) begin
                            dividend[32:1] <= ~operand1_i + 1;
                        end else begin
                            dividend[32:1] <= operand1_i;
                        end
                        if ((signed_div_i == 1'b1) && (operand2_i[31] == 1'b1)) begin
                            divisor <= ~operand2_i + 1;
                        end else begin
                            divisor <= operand2_i;
                        end
                    end
                end else begin
                    ready_o <= `DivResultNotReady;
                    result_o <= {`ZeroWord, `ZeroWord};
                end
            end
            `DivByZero: begin
                dividend <= {`ZeroWord, `ZeroWord};
                state <= `DivEnd;
            end
            `DivOn: begin
                if (annul_i == `FlushDisable) begin
                    if (cnt != 6'b100000) begin
                        if (div_temp[32] == 1'b1) begin
                            dividend <= {dividend[63:0], 1'b0};
                        end else begin
                            dividend <= {div_temp[31:0], dividend[31:0], 1'b1};
                        end
                        cnt <= cnt + 1;
                    end else begin
                        if ((signed_div_i == 1'b1) && ((operand1_i[31] ^ operand2_i[31]) == 1'b1)) begin
                            dividend[31:0] <= (~dividend[31:0] + 1);
                        end
                        if ((signed_div_i == 1'b1) && ((operand1_i[31] ^ dividend[64]) == 1'b1)) begin
                            dividend[64:33] <= (~dividend[64:33] + 1);
                        end
                        state <= `DivEnd;
                        cnt <= 6'b000000;
                    end
                end else begin
                    state <= `DivFree;
                end
            end
            `DivEnd: begin
                result_o <= {dividend[64:33], dividend[31:0]};
                ready_o <= `DivResultReady;
                if (start_i == `DivStop) begin
                    state <= `DivFree;
                    ready_o <= `DivResultNotReady;
                    result_o <= {`ZeroWord, `ZeroWord};
                end
            end
        endcase
    end
end

endmodule
module div(
    input                               clk,
    input                               resetn,

    input                               signed_div_i,
    input   [`RegBus]                   operand1_i,
    input   [`RegBus]                   operand2_i,
    input                               start_i,
    input                               annul_i,

    output  reg[`DoubleRegBus]          result_o,
    output  reg                         ready_o
);


wire[32:0] div_temp;
reg[64:0] dividend;
reg[5:0] cnt;
reg[1:0] state;
reg[31:0] divisor;

assign div_temp = {1'b0, dividend[63:32]} - {1'b0, divisor};

always @(posedge clk) begin
    if (resetn == `RstEnable) begin
        state <= `DivFree;
        ready_o <= `DivResultNotReady;
        result_o <= {`ZeroWord, `ZeroWord};
    end else begin
        case (state)
            `DivFree: begin
                if ((start_i == `DivStart) && (annul_i == `FlushDisable)) begin
                    if (operand2_i == `ZeroWord) begin
                        state <= `DivByZero;
                    end else begin
                        state <= `DivOn;
                        cnt <= 6'b000000;
                        dividend[63:33] <= 31'b0;
                        dividend[0] <= 1'b0;
                        if ((signed_div_i == 1'b1) && (operand1_i[31] == 1'b1)) begin
                            dividend[32:1] <= ~operand1_i + 1;
                        end else begin
                            dividend[32:1] <= operand1_i;
                        end
                        if ((signed_div_i == 1'b1) && (operand2_i[31] == 1'b1)) begin
                            divisor <= ~operand2_i + 1;
                        end else begin
                            divisor <= operand2_i;
                        end
                    end
                end else begin
                    ready_o <= `DivResultNotReady;
                    result_o <= {`ZeroWord, `ZeroWord};
                end
            end
            `DivByZero: begin
                dividend <= {`ZeroWord, `ZeroWord};
                state <= `DivEnd;
            end
            `DivOn: begin
                if (annul_i == `FlushDisable) begin
                    if (cnt != 6'b100000) begin
                        if (div_temp[32] == 1'b1) begin
                            dividend <= {dividend[63:0], 1'b0};
                        end else begin
                            dividend <= {div_temp[31:0], dividend[31:0], 1'b1};
                        end
                        cnt <= cnt + 1;
                    end else begin
                        if ((signed_div_i == 1'b1) && ((operand1_i[31] ^ operand2_i[31]) == 1'b1)) begin
                            dividend[31:0] <= (~dividend[31:0] + 1);
                        end
                        if ((signed_div_i == 1'b1) && ((operand1_i[31] ^ dividend[64]) == 1'b1)) begin
                            dividend[64:33] <= (~dividend[64:33] + 1);
                        end
                        state <= `DivEnd;
                        cnt <= 6'b000000;
                    end
                end else begin
                    state <= `DivFree;
                end
            end
            `DivEnd: begin
                result_o <= {dividend[64:33], dividend[31:0]};
                ready_o <= `DivResultReady;
                if (start_i == `DivStop) begin
                    state <= `DivFree;
                    ready_o <= `DivResultNotReady;
                    result_o <= {`ZeroWord, `ZeroWord};
                end
            end
        endcase
    end
end

endmodule