data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_dpopt/bdw_work/wrappers/dut_vlwrapper.v
data/verilator_xmls/d177eba9-38a0-4cdc-80cc-15dec18c8af5.xml
module dut_vlwrapper(
      clk,
       rst,
       din_busy,
       din_vld,
       din_data_a,
       din_data_b,
       din_data_c,
       din_data_d,
       din_data_e,
       din_data_f,
       din_data_g,
       din_data_h,
       dout_busy,
       dout_vld,
       dout_data

    );

	input clk;
	input rst;
	output din_busy;
	reg din_busy;
	wire m_din_busy;
	input din_vld;
	input [7:0] din_data_a;
	input [7:0] din_data_b;
	input [7:0] din_data_c;
	input [7:0] din_data_d;
	input [7:0] din_data_e;
	input [7:0] din_data_f;
	input [7:0] din_data_g;
	input [7:0] din_data_h;
	input dout_busy;
	output dout_vld;
	reg dout_vld;
	wire m_dout_vld;
	output [31:0] dout_data;
	reg[31:0] dout_data;
	wire [31:0] m_dout_data;



    dut_type_wrapper dut_sc(
        .clk(clk),
         .rst(rst),
         .din_busy(m_din_busy),
         .din_vld(din_vld),
         .din_data_a(din_data_a),
         .din_data_b(din_data_b),
         .din_data_c(din_data_c),
         .din_data_d(din_data_d),
         .din_data_e(din_data_e),
         .din_data_f(din_data_f),
         .din_data_g(din_data_g),
         .din_data_h(din_data_h),
         .dout_busy(dout_busy),
         .dout_vld(m_dout_vld),
         .dout_data(m_dout_data)

    );




    always @(m_din_busy)
     begin
      din_busy <= m_din_busy;
     end
    always @(m_dout_vld)
     begin
      dout_vld <= m_dout_vld;
     end
    always @(m_dout_data)
     begin
      dout_data <= m_dout_data;
     end


endmodule
module dut_vlwrapper(
      clk,
       rst,
       din_busy,
       din_vld,
       din_data_a,
       din_data_b,
       din_data_c,
       din_data_d,
       din_data_e,
       din_data_f,
       din_data_g,
       din_data_h,
       dout_busy,
       dout_vld,
       dout_data

    );


	input clk;
	input rst;
	output din_busy;
	reg din_busy;
	wire m_din_busy;
	input din_vld;
	input [7:0] din_data_a;
	input [7:0] din_data_b;
	input [7:0] din_data_c;
	input [7:0] din_data_d;
	input [7:0] din_data_e;
	input [7:0] din_data_f;
	input [7:0] din_data_g;
	input [7:0] din_data_h;
	input dout_busy;
	output dout_vld;
	reg dout_vld;
	wire m_dout_vld;
	output [31:0] dout_data;
	reg[31:0] dout_data;
	wire [31:0] m_dout_data;



    dut_type_wrapper dut_sc(
        .clk(clk),
         .rst(rst),
         .din_busy(m_din_busy),
         .din_vld(din_vld),
         .din_data_a(din_data_a),
         .din_data_b(din_data_b),
         .din_data_c(din_data_c),
         .din_data_d(din_data_d),
         .din_data_e(din_data_e),
         .din_data_f(din_data_f),
         .din_data_g(din_data_g),
         .din_data_h(din_data_h),
         .dout_busy(dout_busy),
         .dout_vld(m_dout_vld),
         .dout_data(m_dout_data)

    );




    always @(m_din_busy)
     begin
      din_busy <= m_din_busy;
     end
    always @(m_dout_vld)
     begin
      dout_vld <= m_dout_vld;
     end
    always @(m_dout_data)
     begin
      dout_data <= m_dout_data;
     end


endmodule