data/full_repos/permissive/489462235/final_projSrc.v
1: b'%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:170: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                        : ... In instance datapath.control_unit\n        fwda = 2\'b00;\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:171: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                        : ... In instance datapath.control_unit\n        fwdb = 2\'b00;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:174: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h1\' generates 2 bits.\n                                                                        : ... In instance datapath.control_unit\n            fwda = 2\'b01;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:173: Operator EQ expects 5 bits on the LHS, but LHS\'s VARREF \'edestReg\' generates 1 bits.\n                                                                        : ... In instance datapath.control_unit\n        if (edestReg == rs) begin\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:178: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h1\' generates 2 bits.\n                                                                        : ... In instance datapath.control_unit\n            fwdb = 2\'b01;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:177: Operator EQ expects 5 bits on the LHS, but LHS\'s VARREF \'edestReg\' generates 1 bits.\n                                                                        : ... In instance datapath.control_unit\n        if (edestReg == rt) begin\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:183: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h3\' generates 2 bits.\n                                                                        : ... In instance datapath.control_unit\n                fwda = 2\'b11;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:186: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                        : ... In instance datapath.control_unit\n                fwda = 2\'b10;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:192: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h3\' generates 2 bits.\n                                                                        : ... In instance datapath.control_unit\n                fwdb = 2\'b11;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:195: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                        : ... In instance datapath.control_unit\n                fwdb = 2\'b10;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:69: Input port connection \'edestReg\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'edestReg\' generates 5 bits.\n                                                                       : ... In instance datapath\n    control_unit control_unit (dinstOut[31:26], dinstOut[5:0], dinstOut[25:21], rt, mdestReg, mm2reg, mwreg, edestReg, em2reg, ewreg, regrt, wreg, m2reg, wmem, aluimm, aluc, fwda, fwdb);\n                                                                                                             ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:69: Output port connection \'fwda\' expects 32 bits on the pin connection, but pin connection\'s VARREF \'fwda\' generates 2 bits.\n                                                                       : ... In instance datapath\n    control_unit control_unit (dinstOut[31:26], dinstOut[5:0], dinstOut[25:21], rt, mdestReg, mm2reg, mwreg, edestReg, em2reg, ewreg, regrt, wreg, m2reg, wmem, aluimm, aluc, fwda, fwdb);\n                                                                                                                                                                              ^~~~\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:69: Output port connection \'fwdb\' expects 32 bits on the pin connection, but pin connection\'s VARREF \'fwdb\' generates 2 bits.\n                                                                       : ... In instance datapath\n    control_unit control_unit (dinstOut[31:26], dinstOut[5:0], dinstOut[25:21], rt, mdestReg, mm2reg, mwreg, edestReg, em2reg, ewreg, regrt, wreg, m2reg, wmem, aluimm, aluc, fwda, fwdb);\n                                                                                                                                                                                    ^~~~\n%Error: Exiting due to 13 warning(s)\n'
module mux5 (qb, r, mr, mdo, fwdb, fqb);
    input [31:0] qb;
    input [31:0] r;
    input [31:0] mr;
    input [31:0] mdo;
    input [1:0] fwdb;
    output reg [31:0] fqb;
    
    always@(*) begin
        if (fwdb == 2'b00) begin
            fqb <= qb;
        end
        else if (fwdb == 2'b01) begin
            fqb <= r;
        end
        else if (fwdb == 2'b10) begin
            fqb <= mr;
        end
        else if (fwdb == 2'b11) begin
            fqb <= mdo;
        end
    end
endmodule
module mux5 (qb, r, mr, mdo, fwdb, fqb);

    input [31:0] qb;
    input [31:0] r;
    input [31:0] mr;
    input [31:0] mdo;
    input [1:0] fwdb;
    output reg [31:0] fqb;
    
    always@(*) begin
        if (fwdb == 2'b00) begin
            fqb <= qb;
        end
        else if (fwdb == 2'b01) begin
            fqb <= r;
        end
        else if (fwdb == 2'b10) begin
            fqb <= mr;
        end
        else if (fwdb == 2'b11) begin
            fqb <= mdo;
        end
    end
endmodule