data/full_repos/permissive/502764644/mpeg_audio_video/AC97/ac97_soc.v
data/verilator_xmls/a79ad040-df83-4387-84b7-a46607006911.xml
module ac97_soc(
		clk, rst, sample_frequency, sync, out_le, ld, pause_cnt
		);

input		clk;
input		rst;
input		[15:0] sample_frequency;
output		sync;
output	[4:0]	out_le;
output		ld;
output pause_cnt;





reg	[7:0]	cnt;
reg		sync_beat;
reg	[4:0]	out_le;
reg		ld;
reg [10:0] void_count;
reg pause_cnt;

assign sync = sync_beat ;





always @(posedge clk)
	if (!rst) cnt <= 8'hff;
	else 
		if (pause_cnt == 0) cnt <= cnt + 8'h1;

always @(posedge clk)
	ld <= #1 (cnt == 8'h00);

always @(posedge clk) begin
	sync_beat <= #1 (cnt == 8'h00) | ((cnt > 8'h00) & (cnt < 8'h10));
end

always @ (posedge clk) begin
	if (!rst) void_count <= 11'h0;
	else if (cnt == 'hff) void_count <= void_count + 11'h1;
	else void_count <= 0;
end

always @ (cnt or void_count or sample_frequency) begin
	if (cnt < 'hff) pause_cnt <= 0;
	else begin
		case (sample_frequency)
		16'h1F40:
			if (void_count < 'd1280) pause_cnt <= 1;
			else pause_cnt <= 0;
		16'h3E80:
			if (void_count < 'd512) pause_cnt <= 1;
			else pause_cnt <= 0;
		16'h5622:
			if (void_count < 'd301) pause_cnt <= 1;
			else pause_cnt <= 0;
		16'hAC44:
			if (void_count < 'd23) pause_cnt <= 1;
			else pause_cnt <= 0;
		default:
			pause_cnt <= 0;
		endcase
	end
end

always @(posedge clk)
	out_le[0] <= #1 (cnt == 8'h11);

always @(posedge clk)
	out_le[1] <= #1 (cnt == 8'h25);

always @(posedge clk)
	out_le[2] <= #1 (cnt == 8'h39);

always @(posedge clk)
	out_le[3] <= #1 (cnt == 8'h4d);

always @(posedge clk)
	out_le[4] <= #1 (cnt == 8'h61);


endmodule
module ac97_soc(
		clk, rst, sample_frequency, sync, out_le, ld, pause_cnt
		);


input		clk;
input		rst;
input		[15:0] sample_frequency;
output		sync;
output	[4:0]	out_le;
output		ld;
output pause_cnt;





reg	[7:0]	cnt;
reg		sync_beat;
reg	[4:0]	out_le;
reg		ld;
reg [10:0] void_count;
reg pause_cnt;

assign sync = sync_beat ;





always @(posedge clk)
	if (!rst) cnt <= 8'hff;
	else 
		if (pause_cnt == 0) cnt <= cnt + 8'h1;

always @(posedge clk)
	ld <= #1 (cnt == 8'h00);

always @(posedge clk) begin
	sync_beat <= #1 (cnt == 8'h00) | ((cnt > 8'h00) & (cnt < 8'h10));
end

always @ (posedge clk) begin
	if (!rst) void_count <= 11'h0;
	else if (cnt == 'hff) void_count <= void_count + 11'h1;
	else void_count <= 0;
end

always @ (cnt or void_count or sample_frequency) begin
	if (cnt < 'hff) pause_cnt <= 0;
	else begin
		case (sample_frequency)
		16'h1F40:
			if (void_count < 'd1280) pause_cnt <= 1;
			else pause_cnt <= 0;
		16'h3E80:
			if (void_count < 'd512) pause_cnt <= 1;
			else pause_cnt <= 0;
		16'h5622:
			if (void_count < 'd301) pause_cnt <= 1;
			else pause_cnt <= 0;
		16'hAC44:
			if (void_count < 'd23) pause_cnt <= 1;
			else pause_cnt <= 0;
		default:
			pause_cnt <= 0;
		endcase
	end
end

always @(posedge clk)
	out_le[0] <= #1 (cnt == 8'h11);

always @(posedge clk)
	out_le[1] <= #1 (cnt == 8'h25);

always @(posedge clk)
	out_le[2] <= #1 (cnt == 8'h39);

always @(posedge clk)
	out_le[3] <= #1 (cnt == 8'h4d);

always @(posedge clk)
	out_le[4] <= #1 (cnt == 8'h61);


endmodule