data/full_repos/permissive/496508301/Lesson5/sec_counter.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson5/sec_counter.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #17     res <= 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson5/sec_counter.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #1000   $stop;    \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson5/sec_counter.v:57: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk=~clk;\n       ^\n%Error: data/full_repos/permissive/496508301/Lesson5/sec_counter.v:60: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("sec_counter_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/496508301/Lesson5/sec_counter.v:61: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module s_counter (clk, res, s_num);
input       clk;
input       res;
output[3:0] s_num;
parameter freq = 24000000;

reg[24:0]   con_t;
reg         s_pulse;
reg[3:0]    s_num;
always @(posedge clk or negedge res) begin
    if (~res)begin
        con_t <= 0; s_pulse <= 0; s_num <= 0;
    end
    else begin
        if (con_t == freq-1)begin
            con_t <= 0; 
        end
        else begin
            con_t <= con_t+1;
        end
    end

    if (con_t==0)begin
        s_pulse <= 1;
    end
    else begin
        s_pulse <= 0;
    end

    if (s_pulse)begin
        if (s_num == 9)begin
            s_num <= 0;
        end
        else begin
        s_num <= s_num + 1;
        end
    end
end
endmodule
module s_counter (clk, res, s_num);

input       clk;
input       res;
output[3:0] s_num;
parameter freq = 24000000;

reg[24:0]   con_t;
reg         s_pulse;
reg[3:0]    s_num;
always @(posedge clk or negedge res) begin
    if (~res)begin
        con_t <= 0; s_pulse <= 0; s_num <= 0;
    end
    else begin
        if (con_t == freq-1)begin
            con_t <= 0; 
        end
        else begin
            con_t <= con_t+1;
        end
    end

    if (con_t==0)begin
        s_pulse <= 1;
    end
    else begin
        s_pulse <= 0;
    end

    if (s_pulse)begin
        if (s_num == 9)begin
            s_num <= 0;
        end
        else begin
        s_num <= s_num + 1;
        end
    end
end
endmodule