data/full_repos/permissive/479253203/verilog/rtl_cgra/ckmux.v
data/verilator_xmls/4d63120a-9919-4d2a-a7f7-9489510b108d.xml
module CW_ff(CLK,D,Q);
parameter wD=1;
input CLK;
input [wD-1:0] D;
output [wD-1:0] Q;
reg [wD-1:0] Q;
wire [wD-1:0] D2 = D;
always @(posedge CLK) Q <= D2;
endmodule
module CW_ff(CLK,D,Q);

parameter wD=1;
input CLK;
input [wD-1:0] D;
output [wD-1:0] Q;
reg [wD-1:0] Q;
wire [wD-1:0] D2 = D;
always @(posedge CLK) Q <= D2;
endmodule