data/full_repos/permissive/459421171/Pipelined/alu_updated.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/459421171/Pipelined/alu_updated.v:91: Little bit endian vector: MSB < LSB of bit range: 0:63\ninput[0:63] x,y;\n     ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/459421171/Pipelined/alu_updated.v:92: Little bit endian vector: MSB < LSB of bit range: 0:63\noutput[0:63]z;\n      ^\n%Error: Exiting due to 2 warning(s)\n'
module  SUB(x,y,z,OF);
input signed[63:0] x,y;
output signed[63:0] z;
output OF;

wire signed[63:0] u,v,w;
wire signed[63:0] k;


twocomp comp(y , u);



ADD sub_add(x , u , w , OF);

assign z=w;

endmodule
module  SUB(x,y,z,OF);

input signed[63:0] x,y;
output signed[63:0] z;
output OF;

wire signed[63:0] u,v,w;
wire signed[63:0] k;


twocomp comp(y , u);



ADD sub_add(x , u , w , OF);

assign z=w;

endmodule