data/full_repos/permissive/500711628/branch_predictor/branch_predictor.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/500711628/branch_predictor/branch_predictor.v:40: Signal definition not found, creating implicitly: \'is_predict_miss1\'\n                                                                                              : ... Suggested alternative: \'is_predict_miss\'\n assign is_predict_miss1 = (_is_predict_miss1 && is_two_instr_branch1);\n        ^~~~~~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/500711628/branch_predictor/branch_predictor.v:41: Signal definition not found, creating implicitly: \'is_predict_miss2\'\n                                                                                              : ... Suggested alternative: \'is_predict_miss\'\n assign is_predict_miss2 = (_is_predict_miss2 && is_one_instr_branch1);\n        ^~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/500711628/branch_predictor/branch_predictor.v:45: Operator COND expects 16 bits on the Conditional True, but Conditional True\'s VARREF \'branch_dst2\' generates 12 bits.\n                                                                                           : ... In instance branch_predictor\n assign branch_dst = (is_predict_miss2 ? branch_dst2 : ( is_predict_miss1 ? branch_dst1 : (branch_src0 + 12\'h001) ));\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/500711628/branch_predictor/branch_predictor.v:45: Operator COND expects 16 bits on the Conditional True, but Conditional True\'s VARREF \'branch_dst1\' generates 12 bits.\n                                                                                           : ... In instance branch_predictor\n assign branch_dst = (is_predict_miss2 ? branch_dst2 : ( is_predict_miss1 ? branch_dst1 : (branch_src0 + 12\'h001) ));\n                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/500711628/branch_predictor/branch_predictor.v:45: Operator ADD expects 16 bits on the RHS, but RHS\'s CONST \'12\'h1\' generates 12 bits.\n                                                                                           : ... In instance branch_predictor\n assign branch_dst = (is_predict_miss2 ? branch_dst2 : ( is_predict_miss1 ? branch_dst1 : (branch_src0 + 12\'h001) ));\n                                                                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/500711628/branch_predictor/branch_predictor.v:45: Operator ASSIGNW expects 12 bits on the Assign RHS, but Assign RHS\'s COND generates 16 bits.\n                                                                                           : ... In instance branch_predictor\n assign branch_dst = (is_predict_miss2 ? branch_dst2 : ( is_predict_miss1 ? branch_dst1 : (branch_src0 + 12\'h001) ));\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/500711628/branch_predictor/branch_predictor.v:52: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                           : ... In instance branch_predictor\n   for(i = 4\'b0000; i <= 4\'b1111; i = i + 4\'b0001) begin\n         ^\n%Warning-WIDTH: data/full_repos/permissive/500711628/branch_predictor/branch_predictor.v:52: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                                           : ... In instance branch_predictor\n   for(i = 4\'b0000; i <= 4\'b1111; i = i + 4\'b0001) begin\n                                        ^\n%Error: Exiting due to 8 warning(s)\n'
function [1:0] is_branch(
		input [15:0] instr
	); 
		begin
			reg [1:0] op1 = instr[15:14];
			reg [2:0] op2 = instr[13:11];
			reg [2:0] cond = instr[10:8];
			
			reg is_one_instr_branch, is_two_instr_branch;
			is_one_instr_branch 
			= 	(	op1 == 2'b10 
					&& (op2 == 3'b010 || op2 == 3'b011 || op2 == 3'b101 || op2 == 3'b110)
				);	
			is_two_instr_branch 
			= 	(	op1 == 2'b10 
					&& op2 == 3'b111
					&& (cond == 3'b000 || cond == 3'b001 || cond == 3'b010 || cond == 3'b011)
				);
			is_branch = {is_one_instr_branch,is_two_instr_branch};
		end
	endfunction
function [1:0] is_branch(
		input [15:0] instr
	);
 
		begin
			reg [1:0] op1 = instr[15:14];
			reg [2:0] op2 = instr[13:11];
			reg [2:0] cond = instr[10:8];
			
			reg is_one_instr_branch, is_two_instr_branch;
			is_one_instr_branch 
			= 	(	op1 == 2'b10 
					&& (op2 == 3'b010 || op2 == 3'b011 || op2 == 3'b101 || op2 == 3'b110)
				);	
			is_two_instr_branch 
			= 	(	op1 == 2'b10 
					&& op2 == 3'b111
					&& (cond == 3'b000 || cond == 3'b001 || cond == 3'b010 || cond == 3'b011)
				);
			is_branch = {is_one_instr_branch,is_two_instr_branch};
		end
	endfunction