data/full_repos/permissive/420070038/examples/bootloader/fusesoc/rtl/pulse_button.v
data/verilator_xmls/73a8f735-4471-4ae9-a313-727534f83501.xml
module and_gate(
	input a,
	input b,
	output c);

assign c = a & b;

endmodule
module and_gate(
	input a,
	input b,
	output c);


assign c = a & b;

endmodule