data/full_repos/permissive/427221126/src/AdderTree.v
1: b"%Error: data/full_repos/permissive/427221126/src/AdderTree.v:102: Cannot find file containing module: 'Add3'\n      Add3 #(.INWIDTH(INWIDTH), .IN_FRAC(IN_FRAC)) U_add3_l1 (\n      ^~~~\n        ... Looked in:\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/Add3\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/Add3.v\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/Add3.sv\n             Add3\n             Add3.v\n             Add3.sv\n             obj_dir/Add3\n             obj_dir/Add3.v\n             obj_dir/Add3.sv\n%Error: data/full_repos/permissive/427221126/src/AdderTree.v:114: Cannot find file containing module: 'Add3'\n      Add3 #(.INWIDTH(INWIDTH+2), .IN_FRAC(IN_FRAC)) U_add3_l2 (\n      ^~~~\n%Error: data/full_repos/permissive/427221126/src/AdderTree.v:181: Cannot find file containing module: 'Add3'\n      Add3 #(.INWIDTH(INWIDTH), .IN_FRAC(IN_FRAC)) U_add3_L0 (\n      ^~~~\n%Error: Exiting due to 3 error(s)\n"
module AdderTree45
  #(
    parameter INWIDTH = 16, 
              IN_FRAC = 10
  )
  (
    input                       clk       ,
    input                       reset     ,
    input                       en        ,
    input      [45*INWIDTH-1:0] din       ,
    input                       din_valid ,
    output signed [INWIDTH+6:0] dout      ,
    output                      dout_valid 
  );
  localparam NUM_INPUTS = 45;
  reg   [2:1] din_valid_d;
  wire        add_en;
  genvar      g;
  genvar      i;
  
  wire signed [INWIDTH-1:0] din_buf       [0:44];
  wire signed [INWIDTH+1:0] add_l0_y      [0:14];
  wire [(INWIDTH+2)*15-1:0] addtree15_din       ;
  wire signed [INWIDTH+6:0] addtree15_dout      ;
  wire                      addtree15_ovld      ;
   
  generate
    for (g = 0; g < NUM_INPUTS; g = g + 1) begin : inputs
      assign din_buf[g] = $signed(din[(g+1)*INWIDTH-1:g*INWIDTH]);
    end

    for (g = 0; g < 15; g = g + 1) begin : L0
      Add3 #(.INWIDTH(INWIDTH), .IN_FRAC(IN_FRAC)) U_add3_L0 (
        .clk  ( clk             ),
        .reset( reset           ),
        .en   ( en && add_en    ),
        .a    ( din_buf[g*3]    ),
        .d    ( din_buf[g*3+1]  ),
        .c    ( din_buf[g*3+2]  ),
        .y    ( add_l0_y[g]     ) 
      );
      
      assign addtree15_din[(g+1)*(INWIDTH+2)-1:(INWIDTH+2)*g] = add_l0_y[g];
    end
  endgenerate

  assign add_en = |{din_valid, din_valid_d};

  always @(posedge clk) begin
    if (reset)
      din_valid_d <= 0;
    else if (en)
      din_valid_d <= {din_valid_d[1:1], din_valid};
  end

  AdderTree15 #(.INWIDTH(INWIDTH+2), .IN_FRAC(IN_FRAC)) U_atree (
    .clk       ( clk              ),
    .reset     ( reset            ),
    .en        ( en               ),
    .din       ( addtree15_din    ),
    .din_valid ( din_valid_d[2]   ),
    .dout      ( addtree15_dout   ),
    .dout_valid( addtree15_ovld   ) 
  );

  assign dout_valid = addtree15_ovld;
  assign dout = addtree15_dout;
endmodule
module AdderTree45
  #(
    parameter INWIDTH = 16, 
              IN_FRAC = 10
  )
  (
    input                       clk       ,
    input                       reset     ,
    input                       en        ,
    input      [45*INWIDTH-1:0] din       ,
    input                       din_valid ,
    output signed [INWIDTH+6:0] dout      ,
    output                      dout_valid 
  );

  localparam NUM_INPUTS = 45;
  reg   [2:1] din_valid_d;
  wire        add_en;
  genvar      g;
  genvar      i;
  
  wire signed [INWIDTH-1:0] din_buf       [0:44];
  wire signed [INWIDTH+1:0] add_l0_y      [0:14];
  wire [(INWIDTH+2)*15-1:0] addtree15_din       ;
  wire signed [INWIDTH+6:0] addtree15_dout      ;
  wire                      addtree15_ovld      ;
   
  generate
    for (g = 0; g < NUM_INPUTS; g = g + 1) begin : inputs
      assign din_buf[g] = $signed(din[(g+1)*INWIDTH-1:g*INWIDTH]);
    end

    for (g = 0; g < 15; g = g + 1) begin : L0
      Add3 #(.INWIDTH(INWIDTH), .IN_FRAC(IN_FRAC)) U_add3_L0 (
        .clk  ( clk             ),
        .reset( reset           ),
        .en   ( en && add_en    ),
        .a    ( din_buf[g*3]    ),
        .d    ( din_buf[g*3+1]  ),
        .c    ( din_buf[g*3+2]  ),
        .y    ( add_l0_y[g]     ) 
      );
      
      assign addtree15_din[(g+1)*(INWIDTH+2)-1:(INWIDTH+2)*g] = add_l0_y[g];
    end
  endgenerate

  assign add_en = |{din_valid, din_valid_d};

  always @(posedge clk) begin
    if (reset)
      din_valid_d <= 0;
    else if (en)
      din_valid_d <= {din_valid_d[1:1], din_valid};
  end

  AdderTree15 #(.INWIDTH(INWIDTH+2), .IN_FRAC(IN_FRAC)) U_atree (
    .clk       ( clk              ),
    .reset     ( reset            ),
    .en        ( en               ),
    .din       ( addtree15_din    ),
    .din_valid ( din_valid_d[2]   ),
    .dout      ( addtree15_dout   ),
    .dout_valid( addtree15_ovld   ) 
  );

  assign dout_valid = addtree15_ovld;
  assign dout = addtree15_dout;
endmodule