data/full_repos/permissive/462122681/shr.v
data/verilator_xmls/52500a16-fcf7-42ec-9351-5ef4446359dd.xml
module shr_logic(
	input wire [31:0] in,
	input wire [31:0] shift,
	output wire [31:0] out
);
	assign out[31:0] = in >> shift;

endmodule
module shr_logic(
	input wire [31:0] in,
	input wire [31:0] shift,
	output wire [31:0] out
);

	assign out[31:0] = in >> shift;

endmodule