data/full_repos/permissive/472671476/verilog/rtl/simpleUART/simple_uart.v
1: b"%Error: data/full_repos/permissive/472671476/verilog/rtl/simpleUART/simple_uart.v:123: Duplicate declaration of signal: 'enabled'\n                                                                                     : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n    reg        enabled;\n               ^~~~~~~\n        data/full_repos/permissive/472671476/verilog/rtl/simpleUART/simple_uart.v:104: ... Location of original declaration\n    output enabled,\n           ^~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module simpleuartA_wb(
    `ifdef USE_POWER_PINS
    input  wire        vccd1      ,
    input  wire        vssd1      ,
    `endif
    input wb_clk_i,
    input wb_rst_i,

    input [1:0] wb_adr_i,
    input [31:0] wb_dat_i,
    input [3:0]  wb_sel_i,
    input wb_we_i,
    input wb_cyc_i,
    input wb_stb_i,

    output wb_ack_o,
    output [31:0] wb_dat_o,

    output uart_enabled,
    output ser_tx,
    input  ser_rx

);

    localparam CLK_DIV = 0;
    localparam DATA = 1;
    localparam CONFIG = 2;
    wire [31:0] simpleuartA_reg_div_do;
    wire [31:0] simpleuartA_reg_dat_do;
    wire [31:0] simpleuartA_reg_cfg_do;
    wire reg_dat_wait;

    wire resetn = ~wb_rst_i;
    wire valid = wb_stb_i && wb_cyc_i; 
    wire simpleuartA_reg_div_sel = valid && (wb_adr_i == CLK_DIV);
    wire simpleuartA_reg_dat_sel = valid && (wb_adr_i == DATA);
    wire simpleuartA_reg_cfg_sel = valid && (wb_adr_i == CONFIG);

    wire [3:0] reg_div_we = simpleuartA_reg_div_sel ? (wb_sel_i & {4{wb_we_i}}): 4'b 0000; 
    wire reg_dat_we = simpleuartA_reg_dat_sel ? (wb_sel_i[0] & wb_we_i): 1'b 0;
    wire reg_cfg_we = simpleuartA_reg_cfg_sel ? (wb_sel_i[0] & wb_we_i): 1'b 0; 

    wire [31:0] mem_wdata = wb_dat_i;

    wire reg_dat_re = simpleuartA_reg_dat_sel && ~wb_we_i;

    assign wb_dat_o = simpleuartA_reg_div_sel ? simpleuartA_reg_div_do:
		      simpleuartA_reg_cfg_sel ? simpleuartA_reg_cfg_do:
					       simpleuartA_reg_dat_do;
    assign wb_ack_o = (simpleuartA_reg_div_sel || simpleuartA_reg_dat_sel
			|| simpleuartA_reg_cfg_sel) && (!reg_dat_wait);
    
    simpleuartA simpleuartA (
        .clk    (wb_clk_i),
        .resetn (resetn),

        .ser_tx      (ser_tx),
        .ser_rx      (ser_rx),
        .enabled     (uart_enabled),

        .reg_div_we  (reg_div_we), 
        .reg_div_di  (mem_wdata),
        .reg_div_do  (simpleuartA_reg_div_do),

        .reg_cfg_we  (reg_cfg_we), 
        .reg_cfg_di  (mem_wdata),
        .reg_cfg_do  (simpleuartA_reg_cfg_do),

        .reg_dat_we  (reg_dat_we),
        .reg_dat_re  (reg_dat_re),
        .reg_dat_di  (mem_wdata),
        .reg_dat_do  (simpleuartA_reg_dat_do),
        .reg_dat_wait(reg_dat_wait)
    );

endmodule
module simpleuartA_wb(
    `ifdef USE_POWER_PINS
    input  wire        vccd1      ,
    input  wire        vssd1      ,
    `endif
    input wb_clk_i,
    input wb_rst_i,

    input [1:0] wb_adr_i,
    input [31:0] wb_dat_i,
    input [3:0]  wb_sel_i,
    input wb_we_i,
    input wb_cyc_i,
    input wb_stb_i,

    output wb_ack_o,
    output [31:0] wb_dat_o,

    output uart_enabled,
    output ser_tx,
    input  ser_rx

);


    localparam CLK_DIV = 0;
    localparam DATA = 1;
    localparam CONFIG = 2;
    wire [31:0] simpleuartA_reg_div_do;
    wire [31:0] simpleuartA_reg_dat_do;
    wire [31:0] simpleuartA_reg_cfg_do;
    wire reg_dat_wait;

    wire resetn = ~wb_rst_i;
    wire valid = wb_stb_i && wb_cyc_i; 
    wire simpleuartA_reg_div_sel = valid && (wb_adr_i == CLK_DIV);
    wire simpleuartA_reg_dat_sel = valid && (wb_adr_i == DATA);
    wire simpleuartA_reg_cfg_sel = valid && (wb_adr_i == CONFIG);

    wire [3:0] reg_div_we = simpleuartA_reg_div_sel ? (wb_sel_i & {4{wb_we_i}}): 4'b 0000; 
    wire reg_dat_we = simpleuartA_reg_dat_sel ? (wb_sel_i[0] & wb_we_i): 1'b 0;
    wire reg_cfg_we = simpleuartA_reg_cfg_sel ? (wb_sel_i[0] & wb_we_i): 1'b 0; 

    wire [31:0] mem_wdata = wb_dat_i;

    wire reg_dat_re = simpleuartA_reg_dat_sel && ~wb_we_i;

    assign wb_dat_o = simpleuartA_reg_div_sel ? simpleuartA_reg_div_do:
		      simpleuartA_reg_cfg_sel ? simpleuartA_reg_cfg_do:
					       simpleuartA_reg_dat_do;
    assign wb_ack_o = (simpleuartA_reg_div_sel || simpleuartA_reg_dat_sel
			|| simpleuartA_reg_cfg_sel) && (!reg_dat_wait);
    
    simpleuartA simpleuartA (
        .clk    (wb_clk_i),
        .resetn (resetn),

        .ser_tx      (ser_tx),
        .ser_rx      (ser_rx),
        .enabled     (uart_enabled),

        .reg_div_we  (reg_div_we), 
        .reg_div_di  (mem_wdata),
        .reg_div_do  (simpleuartA_reg_div_do),

        .reg_cfg_we  (reg_cfg_we), 
        .reg_cfg_di  (mem_wdata),
        .reg_cfg_do  (simpleuartA_reg_cfg_do),

        .reg_dat_we  (reg_dat_we),
        .reg_dat_re  (reg_dat_re),
        .reg_dat_di  (mem_wdata),
        .reg_dat_do  (simpleuartA_reg_dat_do),
        .reg_dat_wait(reg_dat_wait)
    );

endmodule