data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new/Timer_sim.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new/Timer_sim.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #OFFSET\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new/Timer_sim.v:40: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = ~clk;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new/Timer_sim.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Error: data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new/Timer_sim.v:28: Cannot find file containing module: \'Timer\'\nTimer UUT(.clk(clk), .frame(frame), .reset(reset), .CE(CE), .Q(Q));\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new,data/full_repos/permissive/469509877/Timer\n             data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new,data/full_repos/permissive/469509877/Timer.v\n             data/full_repos/permissive/469509877/source/slug-cross.srcs/sim_1/new,data/full_repos/permissive/469509877/Timer.sv\n             Timer\n             Timer.v\n             Timer.sv\n             obj_dir/Timer\n             obj_dir/Timer.v\n             obj_dir/Timer.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Timer_sim();

reg clk, frame, reset, CE;
wire [15:0] Q;

Timer UUT(.clk(clk), .frame(frame), .reset(reset), .CE(CE), .Q(Q));

parameter PERIOD = 10;
    parameter real DUTY_CYCLE = 0.5;
    parameter OFFSET = 2;

    initial
    begin
        #OFFSET
		  clk = 1'b1;
        forever
        begin
            #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = ~clk;
        end
	end
	
   initial
   begin
    frame = 1'b1;
    reset = 1'b0;
    CE = 1'b1;
    #100;
	end
endmodule
module Timer_sim();


reg clk, frame, reset, CE;
wire [15:0] Q;

Timer UUT(.clk(clk), .frame(frame), .reset(reset), .CE(CE), .Q(Q));

parameter PERIOD = 10;
    parameter real DUTY_CYCLE = 0.5;
    parameter OFFSET = 2;

    initial
    begin
        #OFFSET
		  clk = 1'b1;
        forever
        begin
            #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = ~clk;
        end
	end
	
   initial
   begin
    frame = 1'b1;
    reset = 1'b0;
    CE = 1'b1;
    #100;
	end
endmodule