data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Reg_Bank.v
1: b'%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/Reg_Bank.v:1: Cannot find include file: ../defined.vh\n`include "../defined.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips,data/full_repos/permissive/486954482/../defined.vh\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips,data/full_repos/permissive/486954482/../defined.vh.v\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips,data/full_repos/permissive/486954482/../defined.vh.sv\n             ../defined.vh\n             ../defined.vh.v\n             ../defined.vh.sv\n             obj_dir/../defined.vh\n             obj_dir/../defined.vh.v\n             obj_dir/../defined.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module Reg_Bank
(
	clk,
	rst,
	rs_index,
	rt_index,
	rd_index,
	reg_source_out,
	reg_target_out,
	reg_dest_new
);

	input			clk;
	input        	rst;
	input 	[4:0]	rs_index;
	input 	[4:0]	rt_index;
	input 	[4:0]	rd_index;
	output 	[31:0]	reg_source_out;
	output 	[31:0]	reg_target_out;
	input  	[31:0]	reg_dest_new;
	
	
	reg		[31:0]	registers[31:0];
		
	
	integer i;
	

	assign reg_source_out = registers[rs_index];
	assign reg_target_out = registers[rt_index];

	
	always@(posedge clk or posedge rst)
	begin
		if(rst)
		begin
			for(i=0;i<32;i=i+1)
			begin
				registers[i] <= 32'b0;				
			end
		end
		else if(rd_index != 5'b0)
		begin
			registers[rd_index[4:0]] <= reg_dest_new;
		end
	end

endmodule
module Reg_Bank
(
	clk,
	rst,
	rs_index,
	rt_index,
	rd_index,
	reg_source_out,
	reg_target_out,
	reg_dest_new
);


	input			clk;
	input        	rst;
	input 	[4:0]	rs_index;
	input 	[4:0]	rt_index;
	input 	[4:0]	rd_index;
	output 	[31:0]	reg_source_out;
	output 	[31:0]	reg_target_out;
	input  	[31:0]	reg_dest_new;
	
	
	reg		[31:0]	registers[31:0];
		
	
	integer i;
	

	assign reg_source_out = registers[rs_index];
	assign reg_target_out = registers[rt_index];

	
	always@(posedge clk or posedge rst)
	begin
		if(rst)
		begin
			for(i=0;i<32;i=i+1)
			begin
				registers[i] <= 32'b0;				
			end
		end
		else if(rd_index != 5'b0)
		begin
			registers[rd_index[4:0]] <= reg_dest_new;
		end
	end

endmodule