data/full_repos/permissive/425529933/Proyecto1Digitales2/phy/phy_c.v
1: b'%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/phy/phy_c.v:1: Cannot find include file: phy_tx_c.v\n`include "phy_tx_c.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/425529933/Proyecto1Digitales2/phy,data/full_repos/permissive/425529933/phy_tx_c.v\n             data/full_repos/permissive/425529933/Proyecto1Digitales2/phy,data/full_repos/permissive/425529933/phy_tx_c.v.v\n             data/full_repos/permissive/425529933/Proyecto1Digitales2/phy,data/full_repos/permissive/425529933/phy_tx_c.v.sv\n             phy_tx_c.v\n             phy_tx_c.v.v\n             phy_tx_c.v.sv\n             obj_dir/phy_tx_c.v\n             obj_dir/phy_tx_c.v.v\n             obj_dir/phy_tx_c.v.sv\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/phy/phy_c.v:2: Cannot find include file: phy_rx_c.v\n`include "phy_rx_c.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/phy/phy_c.v:3: Cannot find include file: clk_generator_c.v\n`include "clk_generator_c.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module phy_c (
	input clk_32f,
	input reset, 
	input valid_in,
	input [31:0] Data_in,
	output reg valid_out_c,
	output reg [31:0] Data_out_c
);

	wire Data_out_1bit_0_c;
	wire Data_out_1bit_1_c;
	wire [31:0] Data;
	wire valid;

phy_tx_c phy_tx_c00 (


		     .Data_out_1bit_0_c	(Data_out_1bit_0_c),
		     .Data_out_1bit_1_c	(Data_out_1bit_1_c),

		     .clk_32f		(clk_32f),
		     .clk_2f_c		(clk_2f_c),
		     .clk_4f_c		(clk_4f_c),
		     .reset		(reset),
		     .valid_in		(valid_in),
		     .Data_in		(Data_in[31:0]));

clk_generator_c clk_generador(

			      .clk_4f_c		(clk_4f_c),
			      .clk_2f_c		(clk_2f_c),
			      .clk_f_c		(clk_f_c),

			      .clk_32f		(clk_32f),
			      .reset		(reset));

phy_rx_c phy_rx_c00 (

		     .valid_out_c	(valid),
		     .Data_out_c	(Data[31:0]),

		     .clk_32f		(clk_32f),
		     .clk_2f_c		(clk_2f_c),
		     .clk_4f_c		(clk_4f_c),
		     .reset		(reset),
		     .Data_in_0		(Data_out_1bit_0_c),
		     .Data_in_1		(Data_out_1bit_1_c));
	
	always @(*) begin
		valid_out_c <= valid;
		Data_out_c <= Data;
	end
endmodule
module phy_c (
	input clk_32f,
	input reset, 
	input valid_in,
	input [31:0] Data_in,
	output reg valid_out_c,
	output reg [31:0] Data_out_c
);


	wire Data_out_1bit_0_c;
	wire Data_out_1bit_1_c;
	wire [31:0] Data;
	wire valid;

phy_tx_c phy_tx_c00 (


		     .Data_out_1bit_0_c	(Data_out_1bit_0_c),
		     .Data_out_1bit_1_c	(Data_out_1bit_1_c),

		     .clk_32f		(clk_32f),
		     .clk_2f_c		(clk_2f_c),
		     .clk_4f_c		(clk_4f_c),
		     .reset		(reset),
		     .valid_in		(valid_in),
		     .Data_in		(Data_in[31:0]));

clk_generator_c clk_generador(

			      .clk_4f_c		(clk_4f_c),
			      .clk_2f_c		(clk_2f_c),
			      .clk_f_c		(clk_f_c),

			      .clk_32f		(clk_32f),
			      .reset		(reset));

phy_rx_c phy_rx_c00 (

		     .valid_out_c	(valid),
		     .Data_out_c	(Data[31:0]),

		     .clk_32f		(clk_32f),
		     .clk_2f_c		(clk_2f_c),
		     .clk_4f_c		(clk_4f_c),
		     .reset		(reset),
		     .Data_in_0		(Data_out_1bit_0_c),
		     .Data_in_1		(Data_out_1bit_1_c));
	
	always @(*) begin
		valid_out_c <= valid;
		Data_out_c <= Data;
	end
endmodule