data/full_repos/permissive/42098404/bemicro/rom.v
1: b"%Error: data/full_repos/permissive/42098404/bemicro/rom.v:26: Cannot find file containing module: 'alt_rom'\n   alt_rom mem(.clock(clk),\n   ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/42098404/bemicro,data/full_repos/permissive/42098404/alt_rom\n             data/full_repos/permissive/42098404/bemicro,data/full_repos/permissive/42098404/alt_rom.v\n             data/full_repos/permissive/42098404/bemicro,data/full_repos/permissive/42098404/alt_rom.sv\n             alt_rom\n             alt_rom.v\n             alt_rom.sv\n             obj_dir/alt_rom\n             obj_dir/alt_rom.v\n             obj_dir/alt_rom.sv\n%Error: Exiting due to 1 error(s)\n"
module ROM (
            input wire         clk,
            input wire         reset,
            input wire [31:0]  haddr,
            input wire         hwrite,
            input wire [2:0]   hsize,
            input wire [2:0]   hburst,
            input wire [3:0]   hprot,
            input wire [1:0]   htrans,
            input wire         hmastlock,
            input wire [31:0]  hwdata,
            output wire [31:0] hrdata,
            input wire         hsel,
            input wire         hreadyin,
            output wire        hreadyout,
            output wire        hresp
            );

   wire [11:0] addr;

   assign hreadyout = 1'b1;
   assign hresp = 1'b0;

   assign addr = {12 {!reset}} & haddr[11:0];

   alt_rom mem(.clock(clk),
               .address(addr),
               .q(hrdata));

endmodule
module ROM (
            input wire         clk,
            input wire         reset,
            input wire [31:0]  haddr,
            input wire         hwrite,
            input wire [2:0]   hsize,
            input wire [2:0]   hburst,
            input wire [3:0]   hprot,
            input wire [1:0]   htrans,
            input wire         hmastlock,
            input wire [31:0]  hwdata,
            output wire [31:0] hrdata,
            input wire         hsel,
            input wire         hreadyin,
            output wire        hreadyout,
            output wire        hresp
            );


   wire [11:0] addr;

   assign hreadyout = 1'b1;
   assign hresp = 1'b0;

   assign addr = {12 {!reset}} & haddr[11:0];

   alt_rom mem(.clock(clk),
               .address(addr),
               .q(hrdata));

endmodule