data/full_repos/permissive/531012469/verilog/rtl/main.v
1: b'%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:368: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                                           : ... In instance rvcorep.p.alu0\n            1 : r_result =  in1 <  in2;\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:369: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LTS generates 1 bits.\n                                                                           : ... In instance rvcorep.p.alu0\n            2 : r_result = sin1 < sin2;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:256: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'cnt_start\' generates 12 bits.\n                                                                           : ... In instance rvcorep.ploader.serc\n          stage <= (cnt_start == (waitcnt >> 1)) ? \'d1 : stage;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:484: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'ExMa_b_rslt\' generates 7 bits.\n                                                                           : ... In instance rvcorep.p\n    wire w_bmis = ExMa_b & (ExMa_b_rslt ? ExMa_b_rslt_t1 : ExMa_b_rslt_t2);\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:485: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'ExMa_b_rslt\' generates 7 bits.\n                                                                           : ... In instance rvcorep.p\n    wire [17:0] w_pc_true = {((ExMa_b_rslt) ? ExMa_tkn_pc[17:2]: ExMa_npc[17:2]), 2\'b00};\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:491: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 18 bits.\n                                                                           : ... In instance rvcorep.p\n    assign I_ADDR = {w_npc, 2\'b00};\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:623: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'IfId_pc\' generates 18 bits.\n                                                                           : ... In instance rvcorep.p\n                             (IfId_im_s[1]) ? IfId_pc + {IfId_ir[31:12], 12\'b0} :   \n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:624: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'IfId_pc\' generates 18 bits.\n                                                                           : ... In instance rvcorep.p\n                             (IfId_im_s[2]) ? IfId_pc + 4                       : 0;\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:638: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'IdEx_pc\' generates 18 bits.\n                                                                           : ... In instance rvcorep.p\n    assign w_tkn_pc = (IdEx_JALR) ? Ex_rrs1+IdEx_imm : IdEx_pc+IdEx_imm;  \n                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:638: Operator ASSIGNW expects 18 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                           : ... In instance rvcorep.p\n    assign w_tkn_pc = (IdEx_JALR) ? Ex_rrs1+IdEx_imm : IdEx_pc+IdEx_imm;  \n                    ^\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:711: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 bits.\n                                                                           : ... In instance rvcorep.p\n    wire [7:0]  w_lb_t = D_IN >> ({w_adr, 3\'d0});\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:760: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'MaWb_pc\' generates 18 bits.\n                                                                           : ... In instance rvcorep.p\n        else r_rout <= (MaWb_v) ? MaWb_pc : r_rout;  \n                                ^\n%Warning-WIDTH: data/full_repos/permissive/531012469/verilog/rtl/main.v:58: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'initwe\' generates 4 bits.\n                                                                          : ... In instance rvcorep\n        initaddr <= (r_rst) ? 0 : (initwe)   ? initaddr + 4 : initaddr;\n                                             ^\n%Error: Exiting due to 13 warning(s)\n'
module UartTx(CLK, RST_X, DATA, WE, TXD, READY);
    input wire       CLK, RST_X, WE;
    input wire [7:0] DATA;
    output reg       TXD, READY;

    reg [8:0]   cmd;
    reg [11:0]  waitnum;
    reg [3:0]   cnt;

    always @(posedge CLK) begin
        if(!RST_X) begin
            TXD       <= 1'b1;
            READY     <= 1'b1;
            cmd       <= 9'h1ff;
            waitnum   <= 0;
            cnt       <= 0;
        end else if( READY ) begin
            TXD       <= 1'b1;
            waitnum   <= 0;
            if( WE )begin
                READY <= 1'b0;
                cmd   <= {DATA, 1'b0};
                cnt   <= 10;
            end
        end else if( waitnum >= `SERIAL_WCNT ) begin
            TXD       <= cmd[0];
            READY     <= (cnt == 1);
            cmd       <= {1'b1, cmd[8:1]};
            waitnum   <= 1;
            cnt       <= cnt - 1;
        end else begin
            waitnum   <= waitnum + 1;
        end
    end
endmodule
module UartTx(CLK, RST_X, DATA, WE, TXD, READY);

    input wire       CLK, RST_X, WE;
    input wire [7:0] DATA;
    output reg       TXD, READY;

    reg [8:0]   cmd;
    reg [11:0]  waitnum;
    reg [3:0]   cnt;

    always @(posedge CLK) begin
        if(!RST_X) begin
            TXD       <= 1'b1;
            READY     <= 1'b1;
            cmd       <= 9'h1ff;
            waitnum   <= 0;
            cnt       <= 0;
        end else if( READY ) begin
            TXD       <= 1'b1;
            waitnum   <= 0;
            if( WE )begin
                READY <= 1'b0;
                cmd   <= {DATA, 1'b0};
                cnt   <= 10;
            end
        end else if( waitnum >= `SERIAL_WCNT ) begin
            TXD       <= cmd[0];
            READY     <= (cnt == 1);
            cmd       <= {1'b1, cmd[8:1]};
            waitnum   <= 1;
            cnt       <= cnt - 1;
        end else begin
            waitnum   <= waitnum + 1;
        end
    end
endmodule