data/full_repos/permissive/463395574/pipeline_reg.v
1: b'%Error: data/full_repos/permissive/463395574/pipeline_reg.v:3: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v.v\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:51: Define or directive not defined: \'`ADDR_SIZE\'\n    input [`ADDR_SIZE-1:0] PCIn,\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:52: Define or directive not defined: \'`INSTR_SIZE\'\n    input [`INSTR_SIZE-1:0] instrIn,\n           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:54: Define or directive not defined: \'`ADDR_SIZE\'\n    output [`ADDR_SIZE-1:0] PCOut,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:55: Define or directive not defined: \'`INSTR_SIZE\'\n    output [`INSTR_SIZE-1:0] instrOut\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:57: Define or directive not defined: \'`ADDR_SIZE\'\n    FlushableEnPipeReg #(`ADDR_SIZE) PCPipeReg (clk, reset, en, IFIDFlush, PCIn, PCOut);\n                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:58: Define or directive not defined: \'`INSTR_SIZE\'\n    FlushableEnPipeReg #(`INSTR_SIZE) instrPipeReg (clk, reset, en, IFIDFlush, instrIn, instrOut);\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:67: Define or directive not defined: \'`REG_IDX_WIDTH\'\n    input [`REG_IDX_WIDTH-1:0] readAddr1In, readAddr2In,\n           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:72: Define or directive not defined: \'`REG_IDX_WIDTH\'\n    input [`REG_IDX_WIDTH-1:0] writeAddrIn,\n           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:77: Define or directive not defined: \'`WORD_LEN\'\n    input [`WORD_LEN-1:0] readData1In, readData2In, PCIn, immdiateIn,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:81: Define or directive not defined: \'`REG_IDX_WIDTH\'\n    output [`REG_IDX_WIDTH-1:0] readAddr1Out, readAddr2Out,\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:84: Define or directive not defined: \'`REG_IDX_WIDTH\'\n    output [`REG_IDX_WIDTH-1:0] writeAddrOut,\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:89: Define or directive not defined: \'`WORD_LEN\'\n    output [`WORD_LEN-1:0] readData1Out, readData2Out, PCOut, immdiateOut\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:92: Define or directive not defined: \'`REG_IDX_WIDTH\'\n    FlushablePipeReg #(`REG_IDX_WIDTH) readAddr1PipeReg (clk, reset, IDEXFlush, readAddr1In, readAddr1Out);\n                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:93: Define or directive not defined: \'`REG_IDX_WIDTH\'\n    FlushablePipeReg #(`REG_IDX_WIDTH) readAddr2PipeReg (clk, reset, IDEXFlush, readAddr2In, readAddr2Out);\n                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:102: Define or directive not defined: \'`WORD_LEN\'\n    FlushablePipeReg #(`WORD_LEN) readData1PipeReg (clk, reset, IDEXFlush, readData1In, readData1Out);\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:103: Define or directive not defined: \'`WORD_LEN\'\n    FlushablePipeReg #(`WORD_LEN) readData2PipeReg (clk, reset, IDEXFlush, readData2In, readData2Out);\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:104: Define or directive not defined: \'`ADDR_SIZE\'\n    FlushablePipeReg #(`ADDR_SIZE) PCPipeReg (clk, reset, IDEXFlush, PCIn, PCOut);\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:105: Define or directive not defined: \'`WORD_LEN\'\n    FlushablePipeReg #(`WORD_LEN) immdiatePipeReg (clk, reset, IDEXFlush, immdiateIn, immdiateOut);\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:107: Define or directive not defined: \'`REG_IDX_WIDTH\'\n    FlushablePipeReg #(`REG_IDX_WIDTH) writeAddrPipeReg (clk, reset, IDEXFlush, writeAddrIn, writeAddrOut);\n                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:116: Define or directive not defined: \'`REG_IDX_WIDTH\'\n    input [`REG_IDX_WIDTH-1:0] readAddr2In, writeAddrIn,\n           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:121: Define or directive not defined: \'`WORD_LEN\'\n    input [`WORD_LEN-1:0] ALUResultIn,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:122: Define or directive not defined: \'`WORD_LEN\'\n    input [`WORD_LEN-1:0] readData2In,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:123: Define or directive not defined: \'`ADDR_SIZE\'\n    input [`ADDR_SIZE-1:0] PCIn,\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:128: Define or directive not defined: \'`REG_IDX_WIDTH\'\n    output [`REG_IDX_WIDTH-1:0] readAddr2Out, writeAddrOut,\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:132: Define or directive not defined: \'`WORD_LEN\'\n    output [`WORD_LEN-1:0] ALUResultOut,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:133: Define or directive not defined: \'`WORD_LEN\'\n    output [`WORD_LEN-1:0] readData2Out,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:134: Define or directive not defined: \'`ADDR_SIZE\'\n    output [`ADDR_SIZE-1:0] PCOut\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:139: Define or directive not defined: \'`REG_IDX_WIDTH\'\n    PipelineReg #(`REG_IDX_WIDTH) writeAddrPipeReg (clk, reset, writeAddrIn, writeAddrOut);\n                  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:140: Define or directive not defined: \'`REG_IDX_WIDTH\'\n    PipelineReg #(`REG_IDX_WIDTH) readAddr2PipeReg (clk, reset, readAddr2In, readAddr2Out);\n                  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:144: Define or directive not defined: \'`WORD_LEN\'\n    PipelineReg #(`WORD_LEN) ALUResultPipeReg (clk, reset, ALUResultIn, ALUResultOut);\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:145: Define or directive not defined: \'`WORD_LEN\'\n    PipelineReg #(`WORD_LEN) readData2PipeReg (clk, reset, readData2In, readData2Out);\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:146: Define or directive not defined: \'`ADDR_SIZE\'\n    PipelineReg #(`ADDR_SIZE) pcPipeReg (clk, reset, PCIn, PCOut);\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:153: Define or directive not defined: \'`REG_IDX_WIDTH\'\n    input [`REG_IDX_WIDTH-1:0] writeAddrIn,\n           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:156: Define or directive not defined: \'`ADDR_SIZE\'\n    input [`ADDR_SIZE-1:0] PCIn,\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:157: Define or directive not defined: \'`WORD_LEN\'\n    input [`WORD_LEN-1:0] regWriteDataIn,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:160: Define or directive not defined: \'`REG_IDX_WIDTH\'\n    output [`REG_IDX_WIDTH-1:0] writeAddrOut,\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:163: Define or directive not defined: \'`ADDR_SIZE\'\n    output [`ADDR_SIZE-1:0] PCOut,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:164: Define or directive not defined: \'`WORD_LEN\'\n    output [`WORD_LEN-1:0] regWriteDataOut\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:166: Define or directive not defined: \'`REG_IDX_WIDTH\'\n    PipelineReg #(`REG_IDX_WIDTH) writeAddrPipeReg (clk, reset, writeAddrIn, writeAddrOut);\n                  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:169: Define or directive not defined: \'`ADDR_SIZE\'\n    PipelineReg #(`ADDR_SIZE) pcPipeReg (clk, reset, PCIn, PCOut);\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/pipeline_reg.v:170: Define or directive not defined: \'`WORD_LEN\'\n    PipelineReg #(`WORD_LEN) regWriteDataPipeReg (clk, reset, regWriteDataIn, regWriteDataOut);\n                  ^~~~~~~~~\n%Error: Exiting due to 42 error(s)\n'
module FlushableEnPipeReg #(
    parameter WIDTH = 1
) (
    input clk, reset, en, flush,
    input [WIDTH-1:0] in,
    output reg [WIDTH-1:0] out
);
    always @(posedge clk, posedge reset)
        if (reset)
            out <= {{WIDTH}{1'b0}};
        else if
            (en && flush) out <= {{WIDTH}{1'b0}};
        else if (en)
            out <= in;
endmodule
module FlushableEnPipeReg #(
    parameter WIDTH = 1
) (
    input clk, reset, en, flush,
    input [WIDTH-1:0] in,
    output reg [WIDTH-1:0] out
);

    always @(posedge clk, posedge reset)
        if (reset)
            out <= {{WIDTH}{1'b0}};
        else if
            (en && flush) out <= {{WIDTH}{1'b0}};
        else if (en)
            out <= in;
endmodule