data/full_repos/permissive/475231219/vectors/vector4.v
data/verilator_xmls/a86e002a-7701-425e-a5f0-0f1d1c05856a.xml
module top_module (
    input [7:0] in,
    output [31:0] out );
    assign out = { {24{in[7]}}, in };


endmodule
module top_module (
    input [7:0] in,
    output [31:0] out );

    assign out = { {24{in[7]}}, in };


endmodule