data/full_repos/permissive/507307707/generated/CellProcessing.v
data/verilator_xmls/ab97e684-dfea-49c9-88b0-d7fe90873c62.xml
module FS(
  input  [4:0] io_ready_out,
  input  [4:0] io_fork_mask,
  output       io_ready_in
);
  wire  aux_0 = ~io_fork_mask[0] | io_ready_out[0];
  wire  aux_1 = ~io_fork_mask[1] | io_ready_out[1];
  wire  aux_2 = ~io_fork_mask[2] | io_ready_out[2];
  wire  aux_3 = ~io_fork_mask[3] | io_ready_out[3];
  wire  aux_4 = ~io_fork_mask[4] | io_ready_out[4];
  wire  temp_1 = aux_0 & aux_1;
  wire  temp_2 = temp_1 & aux_2;
  wire  temp_3 = temp_2 & aux_3;
  assign io_ready_in = temp_3 & aux_4;
endmodule
module FS(
  input  [4:0] io_ready_out,
  input  [4:0] io_fork_mask,
  output       io_ready_in
);

  wire  aux_0 = ~io_fork_mask[0] | io_ready_out[0];
  wire  aux_1 = ~io_fork_mask[1] | io_ready_out[1];
  wire  aux_2 = ~io_fork_mask[2] | io_ready_out[2];
  wire  aux_3 = ~io_fork_mask[3] | io_ready_out[3];
  wire  aux_4 = ~io_fork_mask[4] | io_ready_out[4];
  wire  temp_1 = aux_0 & aux_1;
  wire  temp_2 = temp_1 & aux_2;
  wire  temp_3 = temp_2 & aux_3;
  assign io_ready_in = temp_3 & aux_4;
endmodule