data/full_repos/permissive/405799749/arithmetic_netlists/muliplier/16-bit signed multiplier using wallace tree/reco_unit.v
1: b'%Error: Cannot find file containing module: signed\n        ... Looked in:\n             data/full_repos/permissive/405799749/arithmetic_netlists/muliplier/16-bit/signed\n             data/full_repos/permissive/405799749/arithmetic_netlists/muliplier/16-bit/signed.v\n             data/full_repos/permissive/405799749/arithmetic_netlists/muliplier/16-bit/signed.sv\n             signed\n             signed.v\n             signed.sv\n             obj_dir/signed\n             obj_dir/signed.v\n             obj_dir/signed.sv\n%Error: Cannot find file containing module: multiplier\n%Error: Cannot find file containing module: using\n%Error: Cannot find file containing module: wallace\n%Error: Cannot find file containing module: tree,data/full_repos/permissive/405799749\n%Error: Cannot find file containing module: data/full_repos/permissive/405799749/arithmetic_netlists/muliplier/16-bit\n%Error: Cannot find file containing module: tree/reco_unit.v\n%Error: Exiting due to 7 error(s)\n'
module reco_unit(op,sign,xi);
	output reg [1:0] op;
	output reg sign;
	input [2:0] xi;
	always @(*)
	begin
		case(xi)
		3'b000: begin op <= 2'd0; sign <= 1'd0; end
		3'b010: begin op <= 2'd1; sign <= 1'd0; end
		3'b100: begin op <= 2'd2; sign <= 1'd1; end
		3'b110: begin op <= 2'd1; sign <= 1'd1; end
		3'b001: begin op <= 2'd1; sign <= 1'd0; end
		3'b011: begin op <= 2'd2; sign <= 1'd0; end
		3'b101: begin op <= 2'd1; sign <= 1'd1; end
		3'b111: begin op <= 2'd0; sign <= 1'd0; end
		default: begin op <= 2'dz; sign <= 1'dz; end 
		endcase
	end

endmodule
module reco_unit(op,sign,xi);

	output reg [1:0] op;
	output reg sign;
	input [2:0] xi;
	always @(*)
	begin
		case(xi)
		3'b000: begin op <= 2'd0; sign <= 1'd0; end
		3'b010: begin op <= 2'd1; sign <= 1'd0; end
		3'b100: begin op <= 2'd2; sign <= 1'd1; end
		3'b110: begin op <= 2'd1; sign <= 1'd1; end
		3'b001: begin op <= 2'd1; sign <= 1'd0; end
		3'b011: begin op <= 2'd2; sign <= 1'd0; end
		3'b101: begin op <= 2'd1; sign <= 1'd1; end
		3'b111: begin op <= 2'd0; sign <= 1'd0; end
		default: begin op <= 2'dz; sign <= 1'dz; end 
		endcase
	end

endmodule