data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv:6: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv:14: syntax error, unexpected \'@\', expecting \';\'\ndefault clocking cb @(posedge clk);\n                    ^\n%Error: data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv:17: syntax error, unexpected endclocking\nendclocking\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv:24: syntax error, unexpected int, expecting IDENTIFIER or genvar\n    for (int i = 1; i < 32; i++) begin\n         ^~~\n%Error: data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv:30: syntax error, unexpected <=, expecting IDENTIFIER\n    cb.rst <= 1\'b1;\n           ^~\n%Error: data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv:31: syntax error, unexpected <=, expecting IDENTIFIER\n    cb.load <= 1\'b0;\n            ^~\n%Error: data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv:32: syntax error, unexpected <=, expecting IDENTIFIER\n    cb.in <= 32\'b0;\n          ^~\n%Error: data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv:33: syntax error, unexpected <=, expecting IDENTIFIER\n    cb.src_a <= 5\'b0;\n             ^~\n%Error: data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv:34: syntax error, unexpected <=, expecting IDENTIFIER\n    cb.src_b <= 5\'b0;\n             ^~\n%Error: data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv:35: syntax error, unexpected <=, expecting IDENTIFIER\n    cb.dest <= 5\'b0;\n            ^~\n%Error: data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv:37: syntax error, unexpected <=, expecting IDENTIFIER\n    cb.rst <= 1\'b0;\n           ^~\n%Error: data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv:42: syntax error, unexpected <=, expecting IDENTIFIER\n    cb.load <= 1\'b1;\n            ^~\n%Error: data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv:43: syntax error, unexpected <=, expecting IDENTIFIER\n    cb.in <= data;\n          ^~\n%Error: data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv:44: syntax error, unexpected <=, expecting IDENTIFIER\n    cb.dest <= dest;\n            ^~\n%Error: data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv:46: syntax error, unexpected <=, expecting IDENTIFIER\n    cb.load <= 1\'b0;\n            ^~\n%Error: data/full_repos/permissive/444559342/mp1/setup/hvl/mp1_tb.sv:50: syntax error, unexpected int, expecting IDENTIFIER or genvar\n    for (int i = 1; i < 32; i++) begin\n         ^~~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
function void print_reg(int i);
    $display("reg %2x: %x", i, mp1.rf.data[i]);
endfunction
function void print_reg(int i);

    $display("reg %2x: %x", i, mp1.rf.data[i]);
endfunction