data/full_repos/permissive/489994352/Image-Part/conv2d1x1_tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/489994352/Image-Part/conv2d1x1_tb.sv:29: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/489994352/Image-Part/conv2d1x1_tb.sv:36: Unsupported: Ignoring delay on this delayed statement.\nalways #5 i_clk=~i_clk;\n       ^\n%Warning-IMPLICIT: data/full_repos/permissive/489994352/Image-Part/conv2d1x1_tb.sv:21: Signal definition not found, creating implicitly: \'imgdata1\'\n                                                                                     : ... Suggested alternative: \'imgdata\'\n    $readmemh("input.txt",imgdata1);\n                          ^~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/conv2d1x1_tb.sv:22: Can\'t find definition of variable: \'imgdata2\'\n                                                                          : ... Suggested alternative: \'imgdata\'\n    $readmemh("input1.txt",imgdata2);\n                           ^~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/conv2d1x1_tb.sv:23: Can\'t find definition of variable: \'imgdata3\'\n                                                                          : ... Suggested alternative: \'imgdata\'\n    $readmemh("input2.txt",imgdata3);\n                           ^~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/conv2d1x1_tb.sv:26: Can\'t find definition of variable: \'kernel1_1\'\n                                                                          : ... Suggested alternative: \'kernel\'\n    kernel1_1 =  -1;\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/conv2d1x1_tb.sv:27: Can\'t find definition of variable: \'kernel1_2\'\n                                                                          : ... Suggested alternative: \'kernel1_1\'\n    kernel1_2 =  -1;    \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/conv2d1x1_tb.sv:28: Can\'t find definition of variable: \'kernel1_3\'\n                                                                          : ... Suggested alternative: \'kernel1_1\'\n    kernel1_3 =  -1;\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/conv2d1x1_tb.sv:40: Can\'t find definition of variable: \'clk\'\n                                                                          : ... Suggested alternative: \'i_clk\'\nalways @(posedge clk)\n                 ^~~\n%Error: data/full_repos/permissive/489994352/Image-Part/conv2d1x1_tb.sv:42: Can\'t find definition of variable: \'rst\'\n                                                                          : ... Suggested alternative: \'i_rst\'\n    if(rst)\n       ^~~\n%Error: data/full_repos/permissive/489994352/Image-Part/conv2d1x1_tb.sv:64: Can\'t find definition of variable: \'stride\'\n            if(rdCounter == (outputsize-1)-(stride-1))\n                                            ^~~~~~\n%Error: data/full_repos/permissive/489994352/Image-Part/conv2d1x1_tb.sv:111: Can\'t find definition of variable: \'bias\'\n            channelsum <= bias+multData;\n                          ^~~~\n%Error: Exiting due to 9 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module conv2d1x1#(parameter datwidth=16, input_channel=64, inputsize=55, outputsize=55,inpfile="inpf.txt",weightfile="conv1wf1.txt",outputfile="opf.txt")
                ();
reg [datwidth-1:0] imgdata [224*224-1:0];
reg [15:0] kernel;
reg i_clk, i_rst, i_data_valid;
integer f,f1,f1_1,f1_2,f2,file,file_1,file_2,file1,i,j;
initial
begin
    i_clk = 0;
    i_rst = 1;
    f1 = $fopen("input.txt","r");
    f1_1 = $fopen("input1.txt","r");
    f1_2 = $fopen("input2.txt","r");







    $readmemh("input.txt",imgdata1);
    $readmemh("input1.txt",imgdata2);
    $readmemh("input2.txt",imgdata3);


    kernel1_1 =  -1;
    kernel1_2 =  -1;    
    kernel1_3 =  -1;
    #10;
    i_rst = 0;
    i_data_valid = 1;

    file = $fopen("output2.txt","w");

end
always #5 i_clk=~i_clk;

reg [1:0] currentRdChBuffer;

always @(posedge clk)
begin
    if(rst)
    begin
        currentRdChBuffer <= 0;
    end
    else
    begin
        if(currentRdChBuffer == 2'b10)
            currentRdChBuffer <= 2'b00;
        else
            currentRdChBuffer <= currentRdChBuffer + 2'b01;
    end
end

reg [7:0] rdCounter;

always @(posedge clk)
begin
    if(rst)
        rdCounter <= 0;
    else 
    begin
        if (currentRdChBuffer == 2'b10)
            if(rdCounter == (outputsize-1)-(stride-1))
                rdCounter <= 0;
            else
                rdCounter <= rdCounter + stride;
    end
end

reg [7:0] currentRdLineBuffer;

always @(posedge clk)
begin
    if(rst)
    begin
        currentRdLineBuffer <= 0;
    end
    else
    begin
        if(rdCounter == (outputsize-1)-(stride-1) && currentRdChBuffer==2'b10)
            if (currentRdLineBuffer==8'd223)
                currentRdLineBuffer <= 8'd0;
            else
                currentRdLineBuffer <= currentRdLineBuffer + stride;
    end
end




reg multDataValid;
reg [31:0] multData;
wire [31:0] multDataw;
mul_signed mul1 (kernel[currentRdChBuffer],imgdata1,multDataw);
always @(posedge i_clk)
begin

    multData <= multDataw;
    multDataValid <= i_data_valid;
end


reg [15:0] channelsum;
always @(posedge clk)
begin
    if (rst)
        channelsum <= 0;
    else begin
        if (multDataValid && currentRdChBuffer==2'b01)
            channelsum <= bias+multData;
        else if(multDataValid)
            channelsum <= channelsum + multData;
    end
end

reg [15:0] sumData;
reg sumDataValid;
always @(posedge i_clk)
begin
    sumData <= {channelsum[23:16],channelsum[15:8]};
    sumDataValid <= multDataValid;
end

reg [15:0] o_convolved_data;
reg o_convolved_data_valid;
always @(posedge i_clk)
begin
    o_convolved_data <= sumData;

    o_convolved_data_valid <= sumDataValid;
end
integer sentsize = 0;
always@(posedge i_clk)
begin
    if(o_convolved_data_valid)
        $fwrite(file,"%d\n",$signed(o_convolved_data));
        sentsize = sentsize+1;
        if(sentsize==224*224+4)
            $stop;
end

endmodule
module conv2d1x1#(parameter datwidth=16, input_channel=64, inputsize=55, outputsize=55,inpfile="inpf.txt",weightfile="conv1wf1.txt",outputfile="opf.txt")
                ();

reg [datwidth-1:0] imgdata [224*224-1:0];
reg [15:0] kernel;
reg i_clk, i_rst, i_data_valid;
integer f,f1,f1_1,f1_2,f2,file,file_1,file_2,file1,i,j;
initial
begin
    i_clk = 0;
    i_rst = 1;
    f1 = $fopen("input.txt","r");
    f1_1 = $fopen("input1.txt","r");
    f1_2 = $fopen("input2.txt","r");







    $readmemh("input.txt",imgdata1);
    $readmemh("input1.txt",imgdata2);
    $readmemh("input2.txt",imgdata3);


    kernel1_1 =  -1;
    kernel1_2 =  -1;    
    kernel1_3 =  -1;
    #10;
    i_rst = 0;
    i_data_valid = 1;

    file = $fopen("output2.txt","w");

end
always #5 i_clk=~i_clk;

reg [1:0] currentRdChBuffer;

always @(posedge clk)
begin
    if(rst)
    begin
        currentRdChBuffer <= 0;
    end
    else
    begin
        if(currentRdChBuffer == 2'b10)
            currentRdChBuffer <= 2'b00;
        else
            currentRdChBuffer <= currentRdChBuffer + 2'b01;
    end
end

reg [7:0] rdCounter;

always @(posedge clk)
begin
    if(rst)
        rdCounter <= 0;
    else 
    begin
        if (currentRdChBuffer == 2'b10)
            if(rdCounter == (outputsize-1)-(stride-1))
                rdCounter <= 0;
            else
                rdCounter <= rdCounter + stride;
    end
end

reg [7:0] currentRdLineBuffer;

always @(posedge clk)
begin
    if(rst)
    begin
        currentRdLineBuffer <= 0;
    end
    else
    begin
        if(rdCounter == (outputsize-1)-(stride-1) && currentRdChBuffer==2'b10)
            if (currentRdLineBuffer==8'd223)
                currentRdLineBuffer <= 8'd0;
            else
                currentRdLineBuffer <= currentRdLineBuffer + stride;
    end
end




reg multDataValid;
reg [31:0] multData;
wire [31:0] multDataw;
mul_signed mul1 (kernel[currentRdChBuffer],imgdata1,multDataw);
always @(posedge i_clk)
begin

    multData <= multDataw;
    multDataValid <= i_data_valid;
end


reg [15:0] channelsum;
always @(posedge clk)
begin
    if (rst)
        channelsum <= 0;
    else begin
        if (multDataValid && currentRdChBuffer==2'b01)
            channelsum <= bias+multData;
        else if(multDataValid)
            channelsum <= channelsum + multData;
    end
end

reg [15:0] sumData;
reg sumDataValid;
always @(posedge i_clk)
begin
    sumData <= {channelsum[23:16],channelsum[15:8]};
    sumDataValid <= multDataValid;
end

reg [15:0] o_convolved_data;
reg o_convolved_data_valid;
always @(posedge i_clk)
begin
    o_convolved_data <= sumData;

    o_convolved_data_valid <= sumDataValid;
end
integer sentsize = 0;
always@(posedge i_clk)
begin
    if(o_convolved_data_valid)
        $fwrite(file,"%d\n",$signed(o_convolved_data));
        sentsize = sentsize+1;
        if(sentsize==224*224+4)
            $stop;
end

endmodule