data/full_repos/permissive/475642691/sources/new/Flip_Flop_TypeD.v
data/verilator_xmls/cc09539c-72b8-4d61-83d6-bba57599858d.xml
module Flip_Flop_TypeD(

    input NS,CLK,RST,
    output CS
    );
    

    wire s, sbar, r, rbar,cbar, outbar;

    assign cbar = ~RST;

    assign  sbar = ~(rbar & s),
            s = ~(sbar & cbar & CLK),
            r = ~(rbar & CLK & s),
            rbar = ~(r & cbar & NS);

    assign CS = ~(s & outbar ),
           outbar = ~(CS & r & cbar);

endmodule
module Flip_Flop_TypeD(

    input NS,CLK,RST,
    output CS
    );

    

    wire s, sbar, r, rbar,cbar, outbar;

    assign cbar = ~RST;

    assign  sbar = ~(rbar & s),
            s = ~(sbar & cbar & CLK),
            r = ~(rbar & CLK & s),
            rbar = ~(r & cbar & NS);

    assign CS = ~(s & outbar ),
           outbar = ~(CS & r & cbar);

endmodule