data/full_repos/permissive/504762811/test.v
1: b'%Error: data/full_repos/permissive/504762811/test.v:3: Cannot find include file: minicpu.h\n`include "minicpu.h" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/504762811,data/full_repos/permissive/504762811/minicpu.h\n             data/full_repos/permissive/504762811,data/full_repos/permissive/504762811/minicpu.h.v\n             data/full_repos/permissive/504762811,data/full_repos/permissive/504762811/minicpu.h.sv\n             minicpu.h\n             minicpu.h.v\n             minicpu.h.sv\n             obj_dir/minicpu.h\n             obj_dir/minicpu.h.v\n             obj_dir/minicpu.h.sv\n%Error: data/full_repos/permissive/504762811/test.v:6: Define or directive not defined: \'`AddrBus\'\n wire [`AddrBus] ram_addr;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/504762811/test.v:6: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`AddrBus] ram_addr;\n               ^\n%Error: data/full_repos/permissive/504762811/test.v:7: Define or directive not defined: \'`DataBus\'\n wire [`DataBus] ram_d_in;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/504762811/test.v:7: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`DataBus] ram_d_in;\n               ^\n%Error: data/full_repos/permissive/504762811/test.v:8: Define or directive not defined: \'`DataBus\'\n wire [`DataBus] ram_d_out;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/504762811/test.v:8: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`DataBus] ram_d_out;\n               ^\n%Error: data/full_repos/permissive/504762811/test.v:10: Define or directive not defined: \'`AddrBus\'\n wire [`AddrBus] rom_addr;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/504762811/test.v:10: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`AddrBus] rom_addr;\n               ^\n%Error: data/full_repos/permissive/504762811/test.v:11: Define or directive not defined: \'`Rom_Bus\'\n wire [`Rom_Bus] rom_data;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/504762811/test.v:11: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [`Rom_Bus] rom_data;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/504762811/test.v:45: Unsupported: Ignoring delay on this delayed statement.\n always #(CYCLE/2) clk <= ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/504762811/test.v:50: Define or directive not defined: \'`ENABLE_\'\n  rst_ = `ENABLE_;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/504762811/test.v:50: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  rst_ = `ENABLE_;\n                 ^\n%Error: data/full_repos/permissive/504762811/test.v:53: Define or directive not defined: \'`DISABLE_\'\n  rst_ = `DISABLE_;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/504762811/test.v:53: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  rst_ = `DISABLE_;\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/504762811/test.v:52: Unsupported: Ignoring delay on this delayed statement.\n #(CYCLE+CYCLE/2)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/504762811/test.v:58: Unsupported: Ignoring delay on this delayed statement.\n  if(rst_&&rom_data[23:20]==4\'hf) #(CYCLE+0.1) begin \n                                  ^\n%Error: data/full_repos/permissive/504762811/test.v:64: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("test.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/504762811/test.v:65: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, rom);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/504762811/test.v:66: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, ram);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/504762811/test.v:67: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, minicpu);\n  ^~~~~~~~~\n%Error: Exiting due to 19 error(s), 3 warning(s)\n'
module test;
	wire [`AddrBus] ram_addr;
	wire [`DataBus] ram_d_in;
	wire [`DataBus] ram_d_out;
	wire ram_rd_, ram_wr_;
	wire [`AddrBus] rom_addr;
	wire [`Rom_Bus] rom_data;
	reg clk, rst_;
	integer i;
	
	parameter CYCLE = 1.0;
	

	ram ram (
	.addr	(ram_addr),
	.d_out	(ram_d_out),
	.d_in	(ram_d_in),
	.rd_	(ram_rd_),
	.wr_	(ram_wr_),
	.clk	(clk)
	);

	rom rom (
	.addr	(rom_addr),
	.data	(rom_data)
	);
	
	minicpu minicpu (
	.ram_addr	(ram_addr),
	.ram_d_in	(ram_d_in),
	.ram_d_out	(ram_d_out),
	.ram_rd_	(ram_rd_),
	.ram_wr_	(ram_wr_),
	.rom_addr	(rom_addr),
	.rom_data	(rom_data),
	.clk		(clk),
	.rst_		(rst_)
	);


	always #(CYCLE/2) clk <= ~clk;
	

	initial begin
		clk = 1'b1;
		rst_ = `ENABLE_;

	#(CYCLE+CYCLE/2)
		rst_ = `DISABLE_;
	end

	
	always @(negedge clk)
		if(rst_&&rom_data[23:20]==4'hf) #(CYCLE+0.1) begin 
			$write("%-5d, !!!!!!Program done!!!\n", $time);
			$finish;
		end
	
	initial begin
		$dumpfile("test.vcd");
		$dumpvars(0, rom);
		$dumpvars(0, ram);
		$dumpvars(0, minicpu);
		end
endmodule
module test;

	wire [`AddrBus] ram_addr;
	wire [`DataBus] ram_d_in;
	wire [`DataBus] ram_d_out;
	wire ram_rd_, ram_wr_;
	wire [`AddrBus] rom_addr;
	wire [`Rom_Bus] rom_data;
	reg clk, rst_;
	integer i;
	
	parameter CYCLE = 1.0;
	

	ram ram (
	.addr	(ram_addr),
	.d_out	(ram_d_out),
	.d_in	(ram_d_in),
	.rd_	(ram_rd_),
	.wr_	(ram_wr_),
	.clk	(clk)
	);

	rom rom (
	.addr	(rom_addr),
	.data	(rom_data)
	);
	
	minicpu minicpu (
	.ram_addr	(ram_addr),
	.ram_d_in	(ram_d_in),
	.ram_d_out	(ram_d_out),
	.ram_rd_	(ram_rd_),
	.ram_wr_	(ram_wr_),
	.rom_addr	(rom_addr),
	.rom_data	(rom_data),
	.clk		(clk),
	.rst_		(rst_)
	);


	always #(CYCLE/2) clk <= ~clk;
	

	initial begin
		clk = 1'b1;
		rst_ = `ENABLE_;

	#(CYCLE+CYCLE/2)
		rst_ = `DISABLE_;
	end

	
	always @(negedge clk)
		if(rst_&&rom_data[23:20]==4'hf) #(CYCLE+0.1) begin 
			$write("%-5d, !!!!!!Program done!!!\n", $time);
			$finish;
		end
	
	initial begin
		$dumpfile("test.vcd");
		$dumpvars(0, rom);
		$dumpvars(0, ram);
		$dumpvars(0, minicpu);
		end
endmodule