data/full_repos/permissive/456528918/RTL/timer.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/timer.v:111: Unsupported: Ignoring delay on this delayed statement.\n   TCTR_A: #0.1 TCTR <= din;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/timer.v:112: Unsupported: Ignoring delay on this delayed statement.\n   TDIV_A: #0.1 TDIV <= din;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/timer.v:113: Unsupported: Ignoring delay on this delayed statement.\n   TATS0_A: #0.1 TATS0 <= din;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/timer.v:114: Unsupported: Ignoring delay on this delayed statement.\n   TCMP0_A: #0.1 TCMP0 <= din;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/timer.v:115: Unsupported: Ignoring delay on this delayed statement.\n   TATS1_A: #0.1 TATS1 <= din;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/timer.v:116: Unsupported: Ignoring delay on this delayed statement.\n   TCMP1_A: #0.1 TCMP1 <= din;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/timer.v:121: Unsupported: Ignoring delay on this delayed statement.\n   TCTR_A: #0.1 dout <= TCTR;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/timer.v:122: Unsupported: Ignoring delay on this delayed statement.\n   TCNT0_A: #0.1 dout <= TCNT0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/456528918/RTL/timer.v:123: Unsupported: Ignoring delay on this delayed statement.\n   TCNT1_A: #0.1 dout <= TCNT1;\n            ^\n%Error: Exiting due to 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module timer
#(
	parameter DW = 16,
	parameter AW = 12 
)(
	input			clk,
	input			 rst,
	input [DW-1:0]	din,
	input [AW-1:0]	addr,
	input			we,
	output reg[DW-1:0] dout,
	output reg T0_PWM_P,
	output reg T0_PWM_N,
	output reg T1_PWM_P,
	output reg T1_PWM_N,
	output reg intp_T0,
	output reg intp_T1
);



localparam TCTR_A = 12'h00;
localparam TDIV_A = 12'h01;
localparam TATS0_A = 12'h02;
localparam TCMP0_A = 12'h03;
localparam TCNT0_A = 12'h04;
localparam TATS1_A = 12'h05;
localparam TCMP1_A = 12'h06;
localparam TCNT1_A = 12'h07;

reg[15:0]TCTR;
reg[15:0]TDIV;
reg[15:0]TDIV_r;
reg[15:0]TATS0;
reg[15:0]TATS0_r;
reg[15:0]TCMP0;
reg[15:0]TCMP0_r;
reg[15:0]TCNT0;
reg[15:0]TATS1;
reg[15:0]TATS1_r;
reg[15:0]TCMP1;
reg[15:0]TCMP1_r;
reg[15:0]TCNT1;
reg DIV_EN;
reg [15:0]DIV_CNT;


always @(posedge clk) begin
	if(rst) begin
		DIV_CNT<=16'h0;
		TDIV_r<=16'h0;
		end
	else begin
		if(DIV_CNT==TDIV_r) begin
			DIV_EN<=1'b1;
			DIV_CNT<=16'h0;
			if(TDIV_r!=TDIV)
				TDIV_r<=TDIV;
			end
		else begin
			DIV_CNT<=DIV_CNT+1;
			DIV_EN<=1'b0;
			end
		end
end

always @(posedge clk) begin
if(rst) begin
	TCTR <= 16'h0;
	TDIV <= 16'h0;
	TATS0 <= 16'h0;
	TATS1 <= 16'h0;
	TCMP0 <= 16'h0;
	TCMP1 <= 16'h0;
	dout <= 16'h0;
end	
else
	if(we)
		case (addr)
			TCTR_A: #0.1 TCTR <= din;
			TDIV_A: #0.1 TDIV <= din;
			TATS0_A: #0.1 TATS0 <= din;
			TCMP0_A: #0.1 TCMP0 <= din;
			TATS1_A: #0.1 TATS1 <= din;
			TCMP1_A: #0.1 TCMP1 <= din;
			default: ;
		endcase
	else begin
		case (addr)
			TCTR_A: #0.1 dout <= TCTR;
			TCNT0_A: #0.1 dout <= TCNT0;
			TCNT1_A: #0.1 dout <= TCNT1;
			default: dout <= 16'h0;
		endcase
		end
end


always @(posedge clk) begin
if(rst) begin
	TCNT0 <= 16'h0;
	TCNT1 <= 16'h0;
	intp_T0 <= 1'b0;
	intp_T1 <= 1'b0;
	end	
else begin
	if(TCTR[0]) begin
		if(TCNT0==TATS0_r) begin
			TCNT0 <= 16'h0;
			intp_T0 <= 1'b1;
			TATS0_r <= TATS0;
			TCMP0_r <= TCMP0;
			end
		else begin
			TCNT0 <= TCNT0+1;
			intp_T0 <= 1'b0;
			end
		end
	else begin
		TCNT0 <= 16'h0;
		intp_T0 <= 1'b0;
		TATS0_r <= TATS0;
		TCMP0_r <= TCMP0;
		end
	if(TCTR[8]) begin
		if(TCNT1==TATS1_r) begin
			TCNT1 <= 16'h0;
			intp_T1 <= 1'b1;
			TATS1_r <= TATS1;
			TCMP1_r <= TCMP1;
			end
		else begin
			TCNT1 <= TCNT1+1;
			intp_T0 <= 1'b0;
			end
		end
	else begin
		TCNT1 <= 16'h0;
		intp_T0 <= 1'b0;
		TATS1_r <= TATS1;
		TCMP1_r <= TCMP1;
		end
	end
end


always @(*) begin
if(TCNT0<=TCMP0_r) begin
	T0_PWM_P = TCTR[1];
	T0_PWM_N = ~TCTR[1];
	end
else begin
	T0_PWM_P = ~TCTR[1];
	T0_PWM_N = TCTR[1];
	end
if(TCNT1<=TCMP1_r) begin
	T1_PWM_P = TCTR[9];
	T1_PWM_N = ~TCTR[9];
	end
else begin
	T1_PWM_P = ~TCTR[9];
	T1_PWM_N = TCTR[9];
	end
end
endmodule
module timer
#(
	parameter DW = 16,
	parameter AW = 12 
)(
	input			clk,
	input			 rst,
	input [DW-1:0]	din,
	input [AW-1:0]	addr,
	input			we,
	output reg[DW-1:0] dout,
	output reg T0_PWM_P,
	output reg T0_PWM_N,
	output reg T1_PWM_P,
	output reg T1_PWM_N,
	output reg intp_T0,
	output reg intp_T1
);




localparam TCTR_A = 12'h00;
localparam TDIV_A = 12'h01;
localparam TATS0_A = 12'h02;
localparam TCMP0_A = 12'h03;
localparam TCNT0_A = 12'h04;
localparam TATS1_A = 12'h05;
localparam TCMP1_A = 12'h06;
localparam TCNT1_A = 12'h07;

reg[15:0]TCTR;
reg[15:0]TDIV;
reg[15:0]TDIV_r;
reg[15:0]TATS0;
reg[15:0]TATS0_r;
reg[15:0]TCMP0;
reg[15:0]TCMP0_r;
reg[15:0]TCNT0;
reg[15:0]TATS1;
reg[15:0]TATS1_r;
reg[15:0]TCMP1;
reg[15:0]TCMP1_r;
reg[15:0]TCNT1;
reg DIV_EN;
reg [15:0]DIV_CNT;


always @(posedge clk) begin
	if(rst) begin
		DIV_CNT<=16'h0;
		TDIV_r<=16'h0;
		end
	else begin
		if(DIV_CNT==TDIV_r) begin
			DIV_EN<=1'b1;
			DIV_CNT<=16'h0;
			if(TDIV_r!=TDIV)
				TDIV_r<=TDIV;
			end
		else begin
			DIV_CNT<=DIV_CNT+1;
			DIV_EN<=1'b0;
			end
		end
end

always @(posedge clk) begin
if(rst) begin
	TCTR <= 16'h0;
	TDIV <= 16'h0;
	TATS0 <= 16'h0;
	TATS1 <= 16'h0;
	TCMP0 <= 16'h0;
	TCMP1 <= 16'h0;
	dout <= 16'h0;
end	
else
	if(we)
		case (addr)
			TCTR_A: #0.1 TCTR <= din;
			TDIV_A: #0.1 TDIV <= din;
			TATS0_A: #0.1 TATS0 <= din;
			TCMP0_A: #0.1 TCMP0 <= din;
			TATS1_A: #0.1 TATS1 <= din;
			TCMP1_A: #0.1 TCMP1 <= din;
			default: ;
		endcase
	else begin
		case (addr)
			TCTR_A: #0.1 dout <= TCTR;
			TCNT0_A: #0.1 dout <= TCNT0;
			TCNT1_A: #0.1 dout <= TCNT1;
			default: dout <= 16'h0;
		endcase
		end
end


always @(posedge clk) begin
if(rst) begin
	TCNT0 <= 16'h0;
	TCNT1 <= 16'h0;
	intp_T0 <= 1'b0;
	intp_T1 <= 1'b0;
	end	
else begin
	if(TCTR[0]) begin
		if(TCNT0==TATS0_r) begin
			TCNT0 <= 16'h0;
			intp_T0 <= 1'b1;
			TATS0_r <= TATS0;
			TCMP0_r <= TCMP0;
			end
		else begin
			TCNT0 <= TCNT0+1;
			intp_T0 <= 1'b0;
			end
		end
	else begin
		TCNT0 <= 16'h0;
		intp_T0 <= 1'b0;
		TATS0_r <= TATS0;
		TCMP0_r <= TCMP0;
		end
	if(TCTR[8]) begin
		if(TCNT1==TATS1_r) begin
			TCNT1 <= 16'h0;
			intp_T1 <= 1'b1;
			TATS1_r <= TATS1;
			TCMP1_r <= TCMP1;
			end
		else begin
			TCNT1 <= TCNT1+1;
			intp_T0 <= 1'b0;
			end
		end
	else begin
		TCNT1 <= 16'h0;
		intp_T0 <= 1'b0;
		TATS1_r <= TATS1;
		TCMP1_r <= TCMP1;
		end
	end
end


always @(*) begin
if(TCNT0<=TCMP0_r) begin
	T0_PWM_P = TCTR[1];
	T0_PWM_N = ~TCTR[1];
	end
else begin
	T0_PWM_P = ~TCTR[1];
	T0_PWM_N = TCTR[1];
	end
if(TCNT1<=TCMP1_r) begin
	T1_PWM_P = TCTR[9];
	T1_PWM_N = ~TCTR[9];
	end
else begin
	T1_PWM_P = ~TCTR[9];
	T1_PWM_N = TCTR[9];
	end
end
endmodule