data/full_repos/permissive/500326609/a6/regfile.v
data/verilator_xmls/80fd98a5-25e8-4338-b605-26f2b44492df.xml
module regfile(
    input [4:0] rs1,
    input [4:0] rs2,
    input [4:0] rd,
    input we,
    input [31:0] wdata,
    output [31:0] rv1,
    output [31:0] rv2,
    input clk
);
    integer i;
    reg [31:0] register[31:0];



    initial begin
      for  (i=0; i<32; i=i+1) begin
          register[i] = 0;
      end
    end

    assign rv1 = register[rs1];
    assign rv2 = register[rs2];

    always@(posedge clk)
      if(we)
        begin
          register[rd] <= wdata;
          register[0] <= 0;
        end

endmodule
module regfile(
    input [4:0] rs1,
    input [4:0] rs2,
    input [4:0] rd,
    input we,
    input [31:0] wdata,
    output [31:0] rv1,
    output [31:0] rv2,
    input clk
);

    integer i;
    reg [31:0] register[31:0];



    initial begin
      for  (i=0; i<32; i=i+1) begin
          register[i] = 0;
      end
    end

    assign rv1 = register[rs1];
    assign rv2 = register[rs2];

    always@(posedge clk)
      if(we)
        begin
          register[rd] <= wdata;
          register[0] <= 0;
        end

endmodule