data/full_repos/permissive/43858668/final_verilog/src/rtr_fc_state.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_fc_state.v:37: Cannot find include file: c_functions.v\n`include "c_functions.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v.v\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v.sv\n             c_functions.v\n             c_functions.v.v\n             c_functions.v.sv\n             obj_dir/c_functions.v\n             obj_dir/c_functions.v.v\n             obj_dir/c_functions.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_fc_state.v:38: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_fc_state.v:39: Cannot find include file: rtr_constants.v\n`include "rtr_constants.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_fc_state.v:53: Define or directive not defined: \'`FLOW_CTRL_TYPE_CREDIT\'\n   parameter flow_ctrl_type = `FLOW_CTRL_TYPE_CREDIT;\n                              ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_fc_state.v:53: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter flow_ctrl_type = `FLOW_CTRL_TYPE_CREDIT;\n                                                    ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_fc_state.v:60: Define or directive not defined: \'`FB_MGMT_TYPE_STATIC\'\n   parameter mgmt_type = `FB_MGMT_TYPE_STATIC;\n                         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_fc_state.v:60: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter mgmt_type = `FB_MGMT_TYPE_STATIC;\n                                             ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_fc_state.v:71: Define or directive not defined: \'`RESET_TYPE_ASYNC\'\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_fc_state.v:71: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                                           ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_fc_state.v:143: Define or directive not defined: \'`FLOW_CTRL_TYPE_CREDIT\'\n `FLOW_CTRL_TYPE_CREDIT:\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_fc_state.v:143: syntax error, unexpected \':\', expecting endcase\n `FLOW_CTRL_TYPE_CREDIT:\n                       ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_fc_state.v:166: Define or directive not defined: \'`FB_MGMT_TYPE_STATIC\'\n        `FB_MGMT_TYPE_STATIC:\n        ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_fc_state.v:166: syntax error, unexpected \':\', expecting endcase\n        `FB_MGMT_TYPE_STATIC:\n                            ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_fc_state.v:194: syntax error, unexpected end\n   end\n   ^~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_fc_state.v:196: Define or directive not defined: \'`FB_MGMT_TYPE_DYNAMIC\'\n        `FB_MGMT_TYPE_DYNAMIC:\n        ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_fc_state.v:247: syntax error, unexpected end\n   end\n   ^~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_fc_state.v:267: syntax error, unexpected end\n        end\n        ^~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_fc_state.v:277: syntax error, unexpected end\n        end\n        ^~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_fc_state.v:282: syntax error, unexpected end\n   end\n   ^~~\n%Error: Cannot continue\n'
module rtr_fc_state
  (clk, reset, active, flit_valid, flit_head, flit_tail, flit_sel_ovc, 
   fc_event_valid, fc_event_sel_ovc, fc_active, empty_ovc, almost_full_ovc, 
   full_ovc, full_prev_ovc, errors_ovc);
   
`include "c_functions.v"
`include "c_constants.v"
`include "rtr_constants.v"
   
   



   

   parameter num_vcs = 4;
   

   parameter buffer_size = 16;
   

   parameter flow_ctrl_type = `FLOW_CTRL_TYPE_CREDIT;
   


   parameter flow_ctrl_bypass = 1;
   

   parameter mgmt_type = `FB_MGMT_TYPE_STATIC;
   

   parameter fast_almost_empty = 0;
   




   parameter disable_static_reservations = 0;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   



   

   localparam buffer_size_per_vc = buffer_size / num_vcs;
   
   



   
   input clk;
   input reset;
   

   input active;
   

   input flit_valid;
   

   input flit_head;
   

   input flit_tail;
   

   input [0:num_vcs-1] flit_sel_ovc;
   

   input 	       fc_event_valid;


   input [0:num_vcs-1] fc_event_sel_ovc;
   

   output fc_active;
   wire   fc_active;
   

   output [0:num_vcs-1] empty_ovc;
   wire [0:num_vcs-1] 	empty_ovc;


   output [0:num_vcs-1] almost_full_ovc;
   wire [0:num_vcs-1] 	almost_full_ovc;
   

   output [0:num_vcs-1] full_ovc;
   wire [0:num_vcs-1] 	full_ovc;
   

   output [0:num_vcs-1] full_prev_ovc;
   wire [0:num_vcs-1] 	full_prev_ovc;
   

   output [0:num_vcs*2-1] errors_ovc;
   wire [0:num_vcs*2-1]   errors_ovc;
   
   



   
   generate
      
      case(flow_ctrl_type)
	
	`FLOW_CTRL_TYPE_CREDIT:
	  begin
	     
	     wire [0:num_vcs-1] flit_valid_sel_ovc;
	     assign flit_valid_sel_ovc
	       = {num_vcs{flit_valid}} & flit_sel_ovc;
	     
	     wire [0:num_vcs-1] fc_event_valid_sel_ovc;
	     assign fc_event_valid_sel_ovc
	       = {num_vcs{fc_event_valid}} & fc_event_sel_ovc;
	     
	     wire [0:num_vcs-1] debit_ovc;
	     wire [0:num_vcs-1] credit_ovc;
	     
	     wire [0:num_vcs-1] ft_almost_empty_ovc;
	     wire [0:num_vcs-1] ft_empty_ovc;
	     wire [0:num_vcs-1] ft_almost_full_ovc;
	     wire [0:num_vcs-1] ft_full_ovc;
	     wire [0:num_vcs-1] ft_two_free_ovc;
	     wire [0:num_vcs*2-1] ft_errors_ovc;
	     
	     case(mgmt_type)
	       
	       `FB_MGMT_TYPE_STATIC:
		 begin
		    
		    c_samq_tracker
		      #(.num_queues(num_vcs),
			.num_slots_per_queue(buffer_size_per_vc),
			.fast_almost_empty(fast_almost_empty),
			.fast_two_free(1),
			.enable_bypass(0),
			.reset_type(reset_type))
		    samqt
		      (.clk(clk),
		       .reset(reset),
		       .active(active),
		       .push_valid(flit_valid),
		       .push_sel_qu(flit_sel_ovc),
		       .pop_valid(fc_event_valid),
		       .pop_sel_qu(fc_event_sel_ovc),
		       .almost_empty_qu(ft_almost_empty_ovc),
		       .empty_qu(ft_empty_ovc),
		       .almost_full_qu(ft_almost_full_ovc),
		       .full_qu(ft_full_ovc),
		       .two_free_qu(ft_two_free_ovc),
		       .errors_qu(ft_errors_ovc));
		    
		    assign debit_ovc = flit_valid_sel_ovc;
		    assign credit_ovc = fc_event_valid_sel_ovc;
		    
		 end
	       
	       `FB_MGMT_TYPE_DYNAMIC:
		 begin
		    
		    c_damq_tracker
		      #(.num_queues(num_vcs),
			.num_slots(buffer_size),
			.fast_almost_empty(fast_almost_empty),
			.fast_two_free(1),
			.enable_bypass(0),
			.enable_reservations(!disable_static_reservations),
			.reset_type(reset_type))
		    damqt
		      (.clk(clk),
		       .reset(reset),
		       .active(active),
		       .push_valid(flit_valid),
		       .push_sel_qu(flit_sel_ovc),
		       .pop_valid(fc_event_valid),
		       .pop_sel_qu(fc_event_sel_ovc),
		       .almost_empty_qu(ft_almost_empty_ovc),
		       .empty_qu(ft_empty_ovc),
		       .almost_full_qu(ft_almost_full_ovc),
		       .full_qu(ft_full_ovc),
		       .two_free_qu(ft_two_free_ovc),
		       .errors_qu(ft_errors_ovc));
		    
		    wire debit_empty;
		    c_select_1ofn
		      #(.num_ports(num_vcs),
			.width(1))
		    debit_empty_sel
		      (.select(flit_sel_ovc),
		       .data_in(ft_empty_ovc),
		       .data_out(debit_empty));
		    
		    assign debit_ovc = flit_valid_sel_ovc | 
				       {num_vcs{flit_valid & ~debit_empty}};
		    
		    wire 	       credit_almost_empty;
		    c_select_1ofn
		      #(.num_ports(num_vcs),
			.width(1))
		    debit_almost_empty_sel
		      (.select(fc_event_sel_ovc),
		       .data_in(ft_almost_empty_ovc),
		       .data_out(credit_almost_empty));
		    
		    assign credit_ovc
		      = fc_event_valid_sel_ovc | 
			{num_vcs{fc_event_valid & ~credit_almost_empty}};
		    
		 end
	       
	     endcase
	     
	     if(flow_ctrl_bypass)
	       begin
		  assign almost_full_ovc
		    = (credit_ovc & ft_full_ovc) | 
		      ((debit_ovc ~^ credit_ovc) & ft_almost_full_ovc) |
		      ((debit_ovc & ~credit_ovc) & ft_two_free_ovc);
		  assign full_ovc
		    = (ft_full_ovc | 
		       (ft_almost_full_ovc & flit_valid_sel_ovc)) &
		      ~fc_event_valid_sel_ovc;
		  assign full_prev_ovc
		    = ft_full_ovc & ~fc_event_valid_sel_ovc;
		  assign empty_ovc
		    = (ft_empty_ovc | 
		       (ft_almost_empty_ovc & fc_event_valid_sel_ovc)) &
		      ~flit_valid_sel_ovc;
	       end
	     else
	       begin
		  assign almost_full_ovc
		    = (debit_ovc & ft_two_free_ovc) |
		      (~debit_ovc & ft_almost_full_ovc);
		  assign full_ovc
		    = ft_full_ovc | (debit_ovc & ft_almost_full_ovc);
		  assign full_prev_ovc = ft_full_ovc;
		  assign empty_ovc = ft_empty_ovc & ~flit_valid_sel_ovc;
	       end
	     
	     assign fc_active = ~&ft_empty_ovc;
	     assign errors_ovc = ft_errors_ovc;
	     
	  end
	
      endcase
      
   endgenerate
   
endmodule
module rtr_fc_state
  (clk, reset, active, flit_valid, flit_head, flit_tail, flit_sel_ovc, 
   fc_event_valid, fc_event_sel_ovc, fc_active, empty_ovc, almost_full_ovc, 
   full_ovc, full_prev_ovc, errors_ovc);

   
`include "c_functions.v"
`include "c_constants.v"
`include "rtr_constants.v"
   
   



   

   parameter num_vcs = 4;
   

   parameter buffer_size = 16;
   

   parameter flow_ctrl_type = `FLOW_CTRL_TYPE_CREDIT;
   


   parameter flow_ctrl_bypass = 1;
   

   parameter mgmt_type = `FB_MGMT_TYPE_STATIC;
   

   parameter fast_almost_empty = 0;
   




   parameter disable_static_reservations = 0;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   



   

   localparam buffer_size_per_vc = buffer_size / num_vcs;
   
   



   
   input clk;
   input reset;
   

   input active;
   

   input flit_valid;
   

   input flit_head;
   

   input flit_tail;
   

   input [0:num_vcs-1] flit_sel_ovc;
   

   input 	       fc_event_valid;


   input [0:num_vcs-1] fc_event_sel_ovc;
   

   output fc_active;
   wire   fc_active;
   

   output [0:num_vcs-1] empty_ovc;
   wire [0:num_vcs-1] 	empty_ovc;


   output [0:num_vcs-1] almost_full_ovc;
   wire [0:num_vcs-1] 	almost_full_ovc;
   

   output [0:num_vcs-1] full_ovc;
   wire [0:num_vcs-1] 	full_ovc;
   

   output [0:num_vcs-1] full_prev_ovc;
   wire [0:num_vcs-1] 	full_prev_ovc;
   

   output [0:num_vcs*2-1] errors_ovc;
   wire [0:num_vcs*2-1]   errors_ovc;
   
   



   
   generate
      
      case(flow_ctrl_type)
	
	`FLOW_CTRL_TYPE_CREDIT:
	  begin
	     
	     wire [0:num_vcs-1] flit_valid_sel_ovc;
	     assign flit_valid_sel_ovc
	       = {num_vcs{flit_valid}} & flit_sel_ovc;
	     
	     wire [0:num_vcs-1] fc_event_valid_sel_ovc;
	     assign fc_event_valid_sel_ovc
	       = {num_vcs{fc_event_valid}} & fc_event_sel_ovc;
	     
	     wire [0:num_vcs-1] debit_ovc;
	     wire [0:num_vcs-1] credit_ovc;
	     
	     wire [0:num_vcs-1] ft_almost_empty_ovc;
	     wire [0:num_vcs-1] ft_empty_ovc;
	     wire [0:num_vcs-1] ft_almost_full_ovc;
	     wire [0:num_vcs-1] ft_full_ovc;
	     wire [0:num_vcs-1] ft_two_free_ovc;
	     wire [0:num_vcs*2-1] ft_errors_ovc;
	     
	     case(mgmt_type)
	       
	       `FB_MGMT_TYPE_STATIC:
		 begin
		    
		    c_samq_tracker
		      #(.num_queues(num_vcs),
			.num_slots_per_queue(buffer_size_per_vc),
			.fast_almost_empty(fast_almost_empty),
			.fast_two_free(1),
			.enable_bypass(0),
			.reset_type(reset_type))
		    samqt
		      (.clk(clk),
		       .reset(reset),
		       .active(active),
		       .push_valid(flit_valid),
		       .push_sel_qu(flit_sel_ovc),
		       .pop_valid(fc_event_valid),
		       .pop_sel_qu(fc_event_sel_ovc),
		       .almost_empty_qu(ft_almost_empty_ovc),
		       .empty_qu(ft_empty_ovc),
		       .almost_full_qu(ft_almost_full_ovc),
		       .full_qu(ft_full_ovc),
		       .two_free_qu(ft_two_free_ovc),
		       .errors_qu(ft_errors_ovc));
		    
		    assign debit_ovc = flit_valid_sel_ovc;
		    assign credit_ovc = fc_event_valid_sel_ovc;
		    
		 end
	       
	       `FB_MGMT_TYPE_DYNAMIC:
		 begin
		    
		    c_damq_tracker
		      #(.num_queues(num_vcs),
			.num_slots(buffer_size),
			.fast_almost_empty(fast_almost_empty),
			.fast_two_free(1),
			.enable_bypass(0),
			.enable_reservations(!disable_static_reservations),
			.reset_type(reset_type))
		    damqt
		      (.clk(clk),
		       .reset(reset),
		       .active(active),
		       .push_valid(flit_valid),
		       .push_sel_qu(flit_sel_ovc),
		       .pop_valid(fc_event_valid),
		       .pop_sel_qu(fc_event_sel_ovc),
		       .almost_empty_qu(ft_almost_empty_ovc),
		       .empty_qu(ft_empty_ovc),
		       .almost_full_qu(ft_almost_full_ovc),
		       .full_qu(ft_full_ovc),
		       .two_free_qu(ft_two_free_ovc),
		       .errors_qu(ft_errors_ovc));
		    
		    wire debit_empty;
		    c_select_1ofn
		      #(.num_ports(num_vcs),
			.width(1))
		    debit_empty_sel
		      (.select(flit_sel_ovc),
		       .data_in(ft_empty_ovc),
		       .data_out(debit_empty));
		    
		    assign debit_ovc = flit_valid_sel_ovc | 
				       {num_vcs{flit_valid & ~debit_empty}};
		    
		    wire 	       credit_almost_empty;
		    c_select_1ofn
		      #(.num_ports(num_vcs),
			.width(1))
		    debit_almost_empty_sel
		      (.select(fc_event_sel_ovc),
		       .data_in(ft_almost_empty_ovc),
		       .data_out(credit_almost_empty));
		    
		    assign credit_ovc
		      = fc_event_valid_sel_ovc | 
			{num_vcs{fc_event_valid & ~credit_almost_empty}};
		    
		 end
	       
	     endcase
	     
	     if(flow_ctrl_bypass)
	       begin
		  assign almost_full_ovc
		    = (credit_ovc & ft_full_ovc) | 
		      ((debit_ovc ~^ credit_ovc) & ft_almost_full_ovc) |
		      ((debit_ovc & ~credit_ovc) & ft_two_free_ovc);
		  assign full_ovc
		    = (ft_full_ovc | 
		       (ft_almost_full_ovc & flit_valid_sel_ovc)) &
		      ~fc_event_valid_sel_ovc;
		  assign full_prev_ovc
		    = ft_full_ovc & ~fc_event_valid_sel_ovc;
		  assign empty_ovc
		    = (ft_empty_ovc | 
		       (ft_almost_empty_ovc & fc_event_valid_sel_ovc)) &
		      ~flit_valid_sel_ovc;
	       end
	     else
	       begin
		  assign almost_full_ovc
		    = (debit_ovc & ft_two_free_ovc) |
		      (~debit_ovc & ft_almost_full_ovc);
		  assign full_ovc
		    = ft_full_ovc | (debit_ovc & ft_almost_full_ovc);
		  assign full_prev_ovc = ft_full_ovc;
		  assign empty_ovc = ft_empty_ovc & ~flit_valid_sel_ovc;
	       end
	     
	     assign fc_active = ~&ft_empty_ovc;
	     assign errors_ovc = ft_errors_ovc;
	     
	  end
	
      endcase
      
   endgenerate
   
endmodule