data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Latches and Flip-Flops/ece241_2014_q4/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Latches\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Latches\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Latches.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Latches.sv\n             Logic/Latches\n             Logic/Latches.v\n             Logic/Latches.sv\n             obj_dir/Logic/Latches\n             obj_dir/Logic/Latches.v\n             obj_dir/Logic/Latches.sv\n%Error: Cannot find file containing module: and\n%Error: Cannot find file containing module: Flip-Flops/ece241_2014_q4,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Flip-Flops/ece241_2014_q4/top_module.v\n%Error: Exiting due to 5 error(s)\n'
module my_dff (
    input  wire clk,
    input  wire d,
    output reg  q,
    output wire qn
);

  initial begin
    q = 0;
  end

  assign qn = ~q;

  always @(posedge clk) begin
    q <= d;
  end

endmodule
module my_dff (
    input  wire clk,
    input  wire d,
    output reg  q,
    output wire qn
);


  initial begin
    q = 0;
  end

  assign qn = ~q;

  always @(posedge clk) begin
    q <= d;
  end

endmodule