data/full_repos/permissive/441359809/src/yosys/tests/arch/xilinx/xilinx_srl.v
1: b'%Error: data/full_repos/permissive/441359809/src/yosys/tests/arch/xilinx/xilinx_srl.v:29: Unsupported or unknown PLI call: $__XILINX_SHREG_\nmodule $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q);\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/arch/xilinx/xilinx_srl.v:29: syntax error, unexpected ${ignored-bbox-sys}, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q);\n                       ^\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/arch/xilinx/xilinx_srl.v:36: syntax error, unexpected always\nalways @(posedge C)\n^~~~~~\n%Error: Exiting due to 3 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q);
parameter CLKPOL = 1;
parameter ENPOL = 1;
parameter DEPTH = 2;
parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
reg [DEPTH-1:0] r = INIT;
wire clk = C ^ CLKPOL;
always @(posedge C)
    if (E) 
        r <= { r[DEPTH-2:0], D };
assign Q = r[L];
endmodule
module $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q);

parameter CLKPOL = 1;
parameter ENPOL = 1;
parameter DEPTH = 2;
parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
reg [DEPTH-1:0] r = INIT;
wire clk = C ^ CLKPOL;
always @(posedge C)
    if (E) 
        r <= { r[DEPTH-2:0], D };
assign Q = r[L];
endmodule