data/full_repos/permissive/517390617/modules/jtframe/hdl/sound/jtframe_dcrm.v
data/verilator_xmls/4cebc13b-4c64-4ba6-bcb4-85cf7d2aa2d3.xml
module jtframe_dcrm #(parameter SW=8) (
    input                   rst,
    input                   clk,
    input                   sample,
    input         [SW-1:0]  din,
    output signed [SW-1:0]  dout
);

localparam DW=10;

reg  signed [SW+DW:0] integ, exact, error;


reg  signed [SW:0] pre_dout;

reg signed [SW:0] q;

always @(*) begin
    exact = integ+error;
    q = exact[SW+DW:DW];
    pre_dout  = { 1'b0, din } - q;


end

assign dout = pre_dout[SW-1:0];

always @(posedge clk)
    if( rst ) begin
        integ <= {SW+DW+1{1'b0}};
        error <= {SW+DW+1{1'b0}};
    end else if( sample    ) begin

        integ <= integ + pre_dout;

        error <= exact-{q, {DW{1'b0}}};
    end

endmodule
module jtframe_dcrm #(parameter SW=8) (
    input                   rst,
    input                   clk,
    input                   sample,
    input         [SW-1:0]  din,
    output signed [SW-1:0]  dout
);


localparam DW=10;

reg  signed [SW+DW:0] integ, exact, error;


reg  signed [SW:0] pre_dout;

reg signed [SW:0] q;

always @(*) begin
    exact = integ+error;
    q = exact[SW+DW:DW];
    pre_dout  = { 1'b0, din } - q;


end

assign dout = pre_dout[SW-1:0];

always @(posedge clk)
    if( rst ) begin
        integ <= {SW+DW+1{1'b0}};
        error <= {SW+DW+1{1'b0}};
    end else if( sample    ) begin

        integ <= integ + pre_dout;

        error <= exact-{q, {DW{1'b0}}};
    end

endmodule