data/full_repos/permissive/458313092/Debouncer/Debouncer.v
data/verilator_xmls/9c09443e-0e1b-4290-8ab8-5465d1831741.xml
module Debouncer (input CLK,CEI,PUSH,CLR,
                output  PE);

reg [2:0] DELAY;

always @(posedge CLK, posedge CLR) begin
    if ( CLR == 1'b1) DELAY <= 0;
    else if (CLK == 1'b1) 
        if(CEI == 1'b1)  DELAY <= {DELAY[1:0],PUSH};
    
end

assign  PE = (DELAY == 3'b011 && CEI == 1'b1)? 1'b1 : 1'b0;

endmodule
module Debouncer (input CLK,CEI,PUSH,CLR,
                output  PE);


reg [2:0] DELAY;

always @(posedge CLK, posedge CLR) begin
    if ( CLR == 1'b1) DELAY <= 0;
    else if (CLK == 1'b1) 
        if(CEI == 1'b1)  DELAY <= {DELAY[1:0],PUSH};
    
end

assign  PE = (DELAY == 3'b011 && CEI == 1'b1)? 1'b1 : 1'b0;

endmodule