data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/Processor/adder_internal.v
1: b'%Warning-WIDTH: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/Processor/adder_internal.v:26: Operator ADD expects 13 bits on the LHS, but LHS\'s VARREF \'a\' generates 8 bits.\n                                                                                                                           : ... In instance adder_internal\nassign y=a+({{5{2\'b0}},b});\n          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/Processor/adder_internal.v:26: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 13 bits.\n                                                                                                                           : ... In instance adder_internal\nassign y=a+({{5{2\'b0}},b});\n        ^\n%Error: Exiting due to 2 warning(s)\n'
module adder_internal(
input [7:0]a,
input [2:0]b,
output [7:0]y
    );
assign y=a+({{5{2'b0}},b});

endmodule
module adder_internal(
input [7:0]a,
input [2:0]b,
output [7:0]y
    );

assign y=a+({{5{2'b0}},b});

endmodule