data/full_repos/permissive/420518472/src/top.v
1: b"%Error: data/full_repos/permissive/420518472/src/top.v:24: Cannot find file containing module: 'pll'\n    pll myPLL (\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/420518472/src,data/full_repos/permissive/420518472/pll\n             data/full_repos/permissive/420518472/src,data/full_repos/permissive/420518472/pll.v\n             data/full_repos/permissive/420518472/src,data/full_repos/permissive/420518472/pll.sv\n             pll\n             pll.v\n             pll.sv\n             obj_dir/pll\n             obj_dir/pll.v\n             obj_dir/pll.sv\n%Error: data/full_repos/permissive/420518472/src/top.v:30: Cannot find file containing module: 'fpgaminer_top'\n    fpgaminer_top #(\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/420518472/src/top.v:44: Cannot find file containing module: 'uart_comm'\n uart_comm #(\n ^~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module top (
	input wire CLK,
	input wire RX,
	output wire TX,
    output [7:0] led
);

    parameter baud_rate = 9600;
    parameter sys_clk_freq = 12000000;
    parameter LOOP_LOG2 = 5;


    wire [95:0] work_data;
	wire [31:0] nonce_min;
	wire [31:0] nonce_max;
	wire [255:0] midstate;
    wire rx_new_work;
    wire new_golden_nonce;
    wire [31:0] golden_nonce;


	wire hash_clk;
    wire locked;							
    pll myPLL (
        .clock_in(CLK), 
        .clock_out(hash_clk), 
        .locked(locked)
    );	

    fpgaminer_top #(
        .LOOP_LOG2(LOOP_LOG2)
    ) miner (
        .hash_clk (hash_clk),
        .midstate(midstate),
	    .work_data(work_data),
        .reset(rx_new_work),
        .golden_nonce(golden_nonce),
	    .new_golden_nonce(new_golden_nonce),
        .nonce_min(nonce_min),
	    .nonce_max(nonce_max),
        .leds(led)
    );

	uart_comm #(
        .baud_rate(baud_rate),
        .sys_clk_freq(sys_clk_freq)
    ) comm (
		.comm_clk (CLK),
        .golden_nonce(golden_nonce),
	    .new_golden_nonce(new_golden_nonce),
        .hash_clk (hash_clk),
		.rx_serial (RX),
		.tx_serial (TX),
        .work_data(work_data),
	    .nonce_min(nonce_min),
	    .nonce_max(nonce_max),
	    .midstate(midstate),
	    .new_work(rx_new_work)
	);
endmodule
module top (
	input wire CLK,
	input wire RX,
	output wire TX,
    output [7:0] led
);


    parameter baud_rate = 9600;
    parameter sys_clk_freq = 12000000;
    parameter LOOP_LOG2 = 5;


    wire [95:0] work_data;
	wire [31:0] nonce_min;
	wire [31:0] nonce_max;
	wire [255:0] midstate;
    wire rx_new_work;
    wire new_golden_nonce;
    wire [31:0] golden_nonce;


	wire hash_clk;
    wire locked;							
    pll myPLL (
        .clock_in(CLK), 
        .clock_out(hash_clk), 
        .locked(locked)
    );	

    fpgaminer_top #(
        .LOOP_LOG2(LOOP_LOG2)
    ) miner (
        .hash_clk (hash_clk),
        .midstate(midstate),
	    .work_data(work_data),
        .reset(rx_new_work),
        .golden_nonce(golden_nonce),
	    .new_golden_nonce(new_golden_nonce),
        .nonce_min(nonce_min),
	    .nonce_max(nonce_max),
        .leds(led)
    );

	uart_comm #(
        .baud_rate(baud_rate),
        .sys_clk_freq(sys_clk_freq)
    ) comm (
		.comm_clk (CLK),
        .golden_nonce(golden_nonce),
	    .new_golden_nonce(new_golden_nonce),
        .hash_clk (hash_clk),
		.rx_serial (RX),
		.tx_serial (TX),
        .work_data(work_data),
	    .nonce_min(nonce_min),
	    .nonce_max(nonce_max),
	    .midstate(midstate),
	    .new_work(rx_new_work)
	);
endmodule