data/full_repos/permissive/416058412/hw/rtl/top_level_loopback.sv
1: b'%Error: data/full_repos/permissive/416058412/hw/rtl/top_level_loopback.sv:10: Cannot find include file: platform_if.vh\n`include "platform_if.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/416058412/hw/rtl,data/full_repos/permissive/416058412/platform_if.vh\n             data/full_repos/permissive/416058412/hw/rtl,data/full_repos/permissive/416058412/platform_if.vh.v\n             data/full_repos/permissive/416058412/hw/rtl,data/full_repos/permissive/416058412/platform_if.vh.sv\n             platform_if.vh\n             platform_if.vh.v\n             platform_if.vh.sv\n             obj_dir/platform_if.vh\n             obj_dir/platform_if.vh.v\n             obj_dir/platform_if.vh.sv\n%Error: data/full_repos/permissive/416058412/hw/rtl/top_level_loopback.sv:12: Cannot find include file: nic.sv\n`include "nic.sv" \n         ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module top_level_loopback_module (

    input           logic             pClk,
    input           logic             pClkDiv2,
    input           logic             pReset,


    input           t_if_ccip_Rx      pck_cp2af_sRx,
    output          t_if_ccip_Tx      pck_af2cp_sTx
    );




    localparam NUM_SUB_AFUS    = 2;
    localparam NUM_PIPE_STAGES = 2;






    logic clk;
    assign clk = pClk;

    logic clk_div_2;
    assign clk_div_2 = pClkDiv2;

    logic reset;
    assign reset = pReset;


    t_if_ccip_Rx sRx;
    always_ff @(posedge clk)
    begin
        sRx <= pck_cp2af_sRx;
    end

    t_if_ccip_Tx sTx;
    assign pck_af2cp_sTx = sTx;





    t_if_ccip_Rx    pck_afu_RxPort        [NUM_SUB_AFUS-1:0];
    t_if_ccip_Tx    pck_afu_TxPort        [NUM_SUB_AFUS-1:0];
    logic           ccip_mux2pe_reset     [NUM_SUB_AFUS-1:0];

    ccip_mux #(NUM_SUB_AFUS, NUM_PIPE_STAGES) ccip_mux_U0 (
                        .pClk(clk),
                        .pClkDiv2(clk_div_2),
                        .SoftReset(reset),
                        .up_Error(),
                        .up_PwrState(),
                        .up_RxPort(sRx),
                        .up_TxPort(sTx),
                        .afu_SoftReset(ccip_mux2pe_reset),
                        .afu_PwrState(),
                        .afu_Error(),
                        .afu_RxPort(pck_afu_RxPort), 
                        .afu_TxPort(pck_afu_TxPort)
        );





    NetworkIf network_Tx_line,   network_Tx_line_1;
    NetworkIf network_Rx_line,   network_Rx_line_1;






    logic nic_0_reset;
    t_if_ccip_Rx nic_0_rx;
    t_if_ccip_Tx nic_0_tx;

    nic #(
            .NIC_ID(8'h00),
            .SRF_BASE_MMIO_ADDRESS(32'h00000),
            .SRF_BASE_MMIO_ADDRESS_AFU_ID(32'h00000),
            .NUM_SUB_AFUS(NUM_SUB_AFUS)
          ) nic_0 (
            .clk(clk),
            .clk_div_2(clk_div_2),
            .reset(ccip_mux2pe_reset[0]),

            .sRx(pck_afu_RxPort[0]),
            .sTx(pck_afu_TxPort[0]),

            .network_tx_out(network_Tx_line),
            .network_rx_in(network_Rx_line)
        );








    localparam NIC_1_MMIO_SW_ADDR = 32'h20000;
    localparam NIC_1_MMIO_ADDR_SW_2_HW = NIC_1_MMIO_SW_ADDR/4;

    logic nic_1_reset;
    t_if_ccip_Rx nic_1_rx;
    t_if_ccip_Tx nic_1_tx;

    nic #(
            .NIC_ID(8'h01),
            .SRF_BASE_MMIO_ADDRESS(NIC_1_MMIO_ADDR_SW_2_HW),
            .SRF_BASE_MMIO_ADDRESS_AFU_ID(NIC_1_MMIO_ADDR_SW_2_HW),
            .NUM_SUB_AFUS(NUM_SUB_AFUS)
          ) nic_1 (
            .clk(clk),
            .clk_div_2(clk_div_2),
            .reset(ccip_mux2pe_reset[1]),

            .sRx(pck_afu_RxPort[1]),
            .sTx(pck_afu_TxPort[1]),

            .network_tx_out(network_Tx_line_1),
            .network_rx_in(network_Rx_line_1)
        );







    logic network_clk;
    assign network_clk = clk_div_2;

    logic network_rst;
    assign network_rst = ccip_mux2pe_reset[0];

    always @(posedge network_clk) begin
        network_Rx_line   <= network_Tx_line_1;
        network_Rx_line_1 <= network_Tx_line;

        if (network_rst) begin
            network_Rx_line.valid <= 1'b0;
            network_Rx_line_1.valid <= 1'b0;
        end
    end


endmodule
module top_level_loopback_module (

    input           logic             pClk,
    input           logic             pClkDiv2,
    input           logic             pReset,


    input           t_if_ccip_Rx      pck_cp2af_sRx,
    output          t_if_ccip_Tx      pck_af2cp_sTx
    );





    localparam NUM_SUB_AFUS    = 2;
    localparam NUM_PIPE_STAGES = 2;






    logic clk;
    assign clk = pClk;

    logic clk_div_2;
    assign clk_div_2 = pClkDiv2;

    logic reset;
    assign reset = pReset;


    t_if_ccip_Rx sRx;
    always_ff @(posedge clk)
    begin
        sRx <= pck_cp2af_sRx;
    end

    t_if_ccip_Tx sTx;
    assign pck_af2cp_sTx = sTx;





    t_if_ccip_Rx    pck_afu_RxPort        [NUM_SUB_AFUS-1:0];
    t_if_ccip_Tx    pck_afu_TxPort        [NUM_SUB_AFUS-1:0];
    logic           ccip_mux2pe_reset     [NUM_SUB_AFUS-1:0];

    ccip_mux #(NUM_SUB_AFUS, NUM_PIPE_STAGES) ccip_mux_U0 (
                        .pClk(clk),
                        .pClkDiv2(clk_div_2),
                        .SoftReset(reset),
                        .up_Error(),
                        .up_PwrState(),
                        .up_RxPort(sRx),
                        .up_TxPort(sTx),
                        .afu_SoftReset(ccip_mux2pe_reset),
                        .afu_PwrState(),
                        .afu_Error(),
                        .afu_RxPort(pck_afu_RxPort), 
                        .afu_TxPort(pck_afu_TxPort)
        );





    NetworkIf network_Tx_line,   network_Tx_line_1;
    NetworkIf network_Rx_line,   network_Rx_line_1;






    logic nic_0_reset;
    t_if_ccip_Rx nic_0_rx;
    t_if_ccip_Tx nic_0_tx;

    nic #(
            .NIC_ID(8'h00),
            .SRF_BASE_MMIO_ADDRESS(32'h00000),
            .SRF_BASE_MMIO_ADDRESS_AFU_ID(32'h00000),
            .NUM_SUB_AFUS(NUM_SUB_AFUS)
          ) nic_0 (
            .clk(clk),
            .clk_div_2(clk_div_2),
            .reset(ccip_mux2pe_reset[0]),

            .sRx(pck_afu_RxPort[0]),
            .sTx(pck_afu_TxPort[0]),

            .network_tx_out(network_Tx_line),
            .network_rx_in(network_Rx_line)
        );








    localparam NIC_1_MMIO_SW_ADDR = 32'h20000;
    localparam NIC_1_MMIO_ADDR_SW_2_HW = NIC_1_MMIO_SW_ADDR/4;

    logic nic_1_reset;
    t_if_ccip_Rx nic_1_rx;
    t_if_ccip_Tx nic_1_tx;

    nic #(
            .NIC_ID(8'h01),
            .SRF_BASE_MMIO_ADDRESS(NIC_1_MMIO_ADDR_SW_2_HW),
            .SRF_BASE_MMIO_ADDRESS_AFU_ID(NIC_1_MMIO_ADDR_SW_2_HW),
            .NUM_SUB_AFUS(NUM_SUB_AFUS)
          ) nic_1 (
            .clk(clk),
            .clk_div_2(clk_div_2),
            .reset(ccip_mux2pe_reset[1]),

            .sRx(pck_afu_RxPort[1]),
            .sTx(pck_afu_TxPort[1]),

            .network_tx_out(network_Tx_line_1),
            .network_rx_in(network_Rx_line_1)
        );







    logic network_clk;
    assign network_clk = clk_div_2;

    logic network_rst;
    assign network_rst = ccip_mux2pe_reset[0];

    always @(posedge network_clk) begin
        network_Rx_line   <= network_Tx_line_1;
        network_Rx_line_1 <= network_Tx_line;

        if (network_rst) begin
            network_Rx_line.valid <= 1'b0;
            network_Rx_line_1.valid <= 1'b0;
        end
    end


endmodule