data/full_repos/permissive/497530416/pipe/execute.v
1: b'%Error: data/full_repos/permissive/497530416/pipe/execute.v:1: Cannot find include file: ./ALU/alu_64bit.v\n`include "./ALU/alu_64bit.v" // correct this before testing \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/497530416/pipe,data/full_repos/permissive/497530416/./ALU/alu_64bit.v\n             data/full_repos/permissive/497530416/pipe,data/full_repos/permissive/497530416/./ALU/alu_64bit.v.v\n             data/full_repos/permissive/497530416/pipe,data/full_repos/permissive/497530416/./ALU/alu_64bit.v.sv\n             ./ALU/alu_64bit.v\n             ./ALU/alu_64bit.v.v\n             ./ALU/alu_64bit.v.sv\n             obj_dir/./ALU/alu_64bit.v\n             obj_dir/./ALU/alu_64bit.v.v\n             obj_dir/./ALU/alu_64bit.v.sv\n%Error: Exiting due to 1 error(s)\n'
module exec_pipe(clk, E_icode, E_ifun, E_valA, E_valB, E_valC, e_valE, e_dstE, E_dstE, e_cnd, ZF, SF, OF, e_icode, e_valA, e_dstM);

input clk;
input [3:0] E_icode, E_ifun, E_dstE, E_dstM;
input [63:0] E_valA, E_valB, E_valC;

output reg [63:0] e_valE;
output reg [3:0] e_dstE;
output reg [3:0] e_icode, e_dstM;
output reg [63:0] e_valA;
output reg e_cnd, ZF, SF, OF;

reg [1:0] control;
reg signed [63:0] aluA;
reg signed [63:0] aluB;
reg signed [63:0] ans;

wire signed [63:0] out;
wire overflow;

ALU_64bit alu(control, aluA, aluB, out, overflow);

always @(*)
    begin
        e_cnd = 0;


        case(E_icode)

        4'b0000: begin end


        4'b0001: begin end


        4'b0010:
        begin            
            case(E_ifun)

            4'b0000: 
            begin 
                e_cnd = 1;
            end
                

            4'b0001: 
            begin
                cndA = SF; cndB = OF;
                cndA = xor_out; cndB = ZF;
                if(or_out)
                    e_cnd = 1;
            end


            4'b0010: 
            begin 
                cndA = SF; cndB = OF;
                if(xor_out)
                    e_cnd = 1;
            end


            4'b0011: 
            begin 
                if(ZF)
                    e_cnd = 1;
            end


            4'b0100: 
            begin 
                cndA = ZF;
                if(not_out)
                    e_cnd = 1;
            end


            4'b0101: 
            begin 
                cndA = SF;
                cndB = OF;
                cndA = xor_out;
                if(not_out)
                    e_cnd = 1;
            end


            4'b0110: 
            begin 
                cndA = SF; cndB = OF;
                cndA = xor_out;
                if(not_out)
                    begin
                        cndA = ZF;
                        if(not_out)
                            e_cnd = 1;
                    end
            end
            endcase
            aluA = E_valA;
            aluB = 64'd0;
            control = 2'b00;
        end


        4'b0011: 
        begin 

            aluA = E_valC;
            aluB = 64'd0;
            control = 2'b00;
        end


        4'b0100: 
        begin 

            aluA = E_valC;
            aluB = E_valB;
            control = 2'b00;
        end


        4'b0101: 
        begin 

            aluA = E_valC;
            aluB = E_valB;
            control = 2'b00;
        end


        4'b0110: 
        begin
            aluA = E_valA;
            aluB = E_valB;

            case(E_ifun)

            4'b0000: 
            begin 
                control = 2'b00;
            end


            4'b0001: 
            begin 
                control = 2'b01;
            end


            4'b0010: 
            begin 
                control = 2'b10;
            end


            4'b0011: 
            begin 
                control = 2'b11;
            end
            endcase
        end


        4'b0111:
        begin
            case(E_ifun)

            4'b0000: 
            begin 
                e_cnd = 1;
            end


            4'b0001: 
            begin 
                cndA = SF; cndB = OF;
                cndA = xor_out; cndB = ZF;
                if(or_out)
                    e_cnd = 1;
            end


            4'b0010: 
            begin 
                cndA = SF; cndB = OF;
                if(xor_out)
                    e_cnd = 1;
            end


            4'b0011:
            begin 
                if(ZF)
                    e_cnd = 1;
            end


            4'b0100: 
            begin 
                cndA = ZF;
                if(not_out)
                    e_cnd = 1;
            end


            4'b0101: 
            begin 
                cndA = SF;
                cndB = OF;
                cndA = xor_out;
                if(not_out)
                    e_cnd = 1;
            end


            4'b0110: 
            begin 
                cndA = SF; cndB = OF;
                cndA = xor_out;
                cndA = not_out;
                if(not_out)
                    begin
                        cndA = ZF;
                        if(not_out)
                            e_cnd = 1;
                    end
            end
            endcase
        end 


        4'b1000: 
        begin 

            aluA = -64'd8;
            aluB = E_valB;
            control = 2'b00;
        end


        4'b1001: 
        begin 

            aluA = 64'd8;
            aluB = E_valB;
            control = 2'b00;
        end


        4'b1010: 
        begin 

            aluA = -64'd8;
            aluB = E_valB;
            control = 2'b00;
        end


        4'b1011: 
        begin 

            aluA = 64'd8;
            aluB = E_valB;
            control = 2'b00;
        end
        endcase
        ans = out;
        e_valE = ans;
    end

always @(out or aluA or aluB)
    begin
        ZF = (out == 64'b0);
        SF = (out < 64'b0);
        OF = (aluA < 1'b0 == aluB < 1'b0) && (out < 64'b0 != aluA < 1'b0);
    end

reg cndA;
reg cndB;
reg xor_out;
reg and_out;
reg or_out;
reg not_out;

always @(cndA or cndB)
    begin




        and_out = cndA & cndB;
        or_out = cndA | cndB;
        xor_out = cndA ^ cndB;
        not_out = ~cndA;
    end

always@(*)
    begin
        if((E_icode == 2) && (!e_cnd))
            e_dstE = 4'b1111;
        else
            e_dstE = E_dstE;
    end

always@(*)
    begin
       e_icode = E_icode;
       e_dstM = E_dstM;
       e_valA = E_valA;
    end

endmodule
module exec_pipe(clk, E_icode, E_ifun, E_valA, E_valB, E_valC, e_valE, e_dstE, E_dstE, e_cnd, ZF, SF, OF, e_icode, e_valA, e_dstM);


input clk;
input [3:0] E_icode, E_ifun, E_dstE, E_dstM;
input [63:0] E_valA, E_valB, E_valC;

output reg [63:0] e_valE;
output reg [3:0] e_dstE;
output reg [3:0] e_icode, e_dstM;
output reg [63:0] e_valA;
output reg e_cnd, ZF, SF, OF;

reg [1:0] control;
reg signed [63:0] aluA;
reg signed [63:0] aluB;
reg signed [63:0] ans;

wire signed [63:0] out;
wire overflow;

ALU_64bit alu(control, aluA, aluB, out, overflow);

always @(*)
    begin
        e_cnd = 0;


        case(E_icode)

        4'b0000: begin end


        4'b0001: begin end


        4'b0010:
        begin            
            case(E_ifun)

            4'b0000: 
            begin 
                e_cnd = 1;
            end
                

            4'b0001: 
            begin
                cndA = SF; cndB = OF;
                cndA = xor_out; cndB = ZF;
                if(or_out)
                    e_cnd = 1;
            end


            4'b0010: 
            begin 
                cndA = SF; cndB = OF;
                if(xor_out)
                    e_cnd = 1;
            end


            4'b0011: 
            begin 
                if(ZF)
                    e_cnd = 1;
            end


            4'b0100: 
            begin 
                cndA = ZF;
                if(not_out)
                    e_cnd = 1;
            end


            4'b0101: 
            begin 
                cndA = SF;
                cndB = OF;
                cndA = xor_out;
                if(not_out)
                    e_cnd = 1;
            end


            4'b0110: 
            begin 
                cndA = SF; cndB = OF;
                cndA = xor_out;
                if(not_out)
                    begin
                        cndA = ZF;
                        if(not_out)
                            e_cnd = 1;
                    end
            end
            endcase
            aluA = E_valA;
            aluB = 64'd0;
            control = 2'b00;
        end


        4'b0011: 
        begin 

            aluA = E_valC;
            aluB = 64'd0;
            control = 2'b00;
        end


        4'b0100: 
        begin 

            aluA = E_valC;
            aluB = E_valB;
            control = 2'b00;
        end


        4'b0101: 
        begin 

            aluA = E_valC;
            aluB = E_valB;
            control = 2'b00;
        end


        4'b0110: 
        begin
            aluA = E_valA;
            aluB = E_valB;

            case(E_ifun)

            4'b0000: 
            begin 
                control = 2'b00;
            end


            4'b0001: 
            begin 
                control = 2'b01;
            end


            4'b0010: 
            begin 
                control = 2'b10;
            end


            4'b0011: 
            begin 
                control = 2'b11;
            end
            endcase
        end


        4'b0111:
        begin
            case(E_ifun)

            4'b0000: 
            begin 
                e_cnd = 1;
            end


            4'b0001: 
            begin 
                cndA = SF; cndB = OF;
                cndA = xor_out; cndB = ZF;
                if(or_out)
                    e_cnd = 1;
            end


            4'b0010: 
            begin 
                cndA = SF; cndB = OF;
                if(xor_out)
                    e_cnd = 1;
            end


            4'b0011:
            begin 
                if(ZF)
                    e_cnd = 1;
            end


            4'b0100: 
            begin 
                cndA = ZF;
                if(not_out)
                    e_cnd = 1;
            end


            4'b0101: 
            begin 
                cndA = SF;
                cndB = OF;
                cndA = xor_out;
                if(not_out)
                    e_cnd = 1;
            end


            4'b0110: 
            begin 
                cndA = SF; cndB = OF;
                cndA = xor_out;
                cndA = not_out;
                if(not_out)
                    begin
                        cndA = ZF;
                        if(not_out)
                            e_cnd = 1;
                    end
            end
            endcase
        end 


        4'b1000: 
        begin 

            aluA = -64'd8;
            aluB = E_valB;
            control = 2'b00;
        end


        4'b1001: 
        begin 

            aluA = 64'd8;
            aluB = E_valB;
            control = 2'b00;
        end


        4'b1010: 
        begin 

            aluA = -64'd8;
            aluB = E_valB;
            control = 2'b00;
        end


        4'b1011: 
        begin 

            aluA = 64'd8;
            aluB = E_valB;
            control = 2'b00;
        end
        endcase
        ans = out;
        e_valE = ans;
    end

always @(out or aluA or aluB)
    begin
        ZF = (out == 64'b0);
        SF = (out < 64'b0);
        OF = (aluA < 1'b0 == aluB < 1'b0) && (out < 64'b0 != aluA < 1'b0);
    end

reg cndA;
reg cndB;
reg xor_out;
reg and_out;
reg or_out;
reg not_out;

always @(cndA or cndB)
    begin




        and_out = cndA & cndB;
        or_out = cndA | cndB;
        xor_out = cndA ^ cndB;
        not_out = ~cndA;
    end

always@(*)
    begin
        if((E_icode == 2) && (!e_cnd))
            e_dstE = 4'b1111;
        else
            e_dstE = E_dstE;
    end

always@(*)
    begin
       e_icode = E_icode;
       e_dstM = E_dstM;
       e_valA = E_valA;
    end

endmodule