data/full_repos/permissive/419538859/lab3/lab3_1self/sim/lab3_1self_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/419538859/lab3/lab3_1self/sim/lab3_1self_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n #(clkper / 2)  clk = ~clk;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab3/lab3_1self/sim/lab3_1self_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n #20;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab3/lab3_1self/sim/lab3_1self_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #80;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab3/lab3_1self/sim/lab3_1self_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #13870000;   \n ^\n%Error: data/full_repos/permissive/419538859/lab3/lab3_1self/sim/lab3_1self_tb.v:12: Cannot find file containing module: \'lab3_1self\'\nlab3_1self lab3_1self_instance(.clk(clk),.reset(reset),.enable(enable),.seg7_sel(seg7_sel),\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/419538859/lab3/lab3_1self/sim,data/full_repos/permissive/419538859/lab3_1self\n             data/full_repos/permissive/419538859/lab3/lab3_1self/sim,data/full_repos/permissive/419538859/lab3_1self.v\n             data/full_repos/permissive/419538859/lab3/lab3_1self/sim,data/full_repos/permissive/419538859/lab3_1self.sv\n             lab3_1self\n             lab3_1self.v\n             lab3_1self.sv\n             obj_dir/lab3_1self\n             obj_dir/lab3_1self.v\n             obj_dir/lab3_1self.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module 	testbench;

reg		clk,reset,enable;
wire	[2:0]seg7_sel;
wire	[6:0]seg7_out;
wire 	dpt,carry,led_com;
wire	clk_count,clk_sel;
wire	[3:0]count_out,count5,count4,count3,count2,count1,count0;

lab3_1self lab3_1self_instance(.clk(clk),.reset(reset),.enable(enable),.seg7_sel(seg7_sel),
						.seg7_out(seg7_out),.dpt(dpt),.carry(carry),.led_com(led_com));


parameter	clkper = 5;
parameter	exp = 1;
parameter	num_use= 6;

initial
begin
	clk = 1;
end

always 
begin
	#(clkper / 2)  clk = ~clk;
end

initial
begin
 reset	=1'b1;
 enable =1'b0;
 #20;		
 reset  =1'b0;
 #80;
 enable =1'b1; 
 #13870000;			
end
endmodule
module 	testbench;


reg		clk,reset,enable;
wire	[2:0]seg7_sel;
wire	[6:0]seg7_out;
wire 	dpt,carry,led_com;
wire	clk_count,clk_sel;
wire	[3:0]count_out,count5,count4,count3,count2,count1,count0;

lab3_1self lab3_1self_instance(.clk(clk),.reset(reset),.enable(enable),.seg7_sel(seg7_sel),
						.seg7_out(seg7_out),.dpt(dpt),.carry(carry),.led_com(led_com));


parameter	clkper = 5;
parameter	exp = 1;
parameter	num_use= 6;

initial
begin
	clk = 1;
end

always 
begin
	#(clkper / 2)  clk = ~clk;
end

initial
begin
 reset	=1'b1;
 enable =1'b0;
 #20;		
 reset  =1'b0;
 #80;
 enable =1'b1; 
 #13870000;			
end
endmodule