data/full_repos/permissive/407433468/2010-PRJ0_BASE_1/rtl/CC_OR.v
data/verilator_xmls/66a299e6-c3d4-4d43-914d-d2fb063da680.xml
module CC_OR (



	CC_OR_OutBUS,
	


	CC_OR_fila7_InBUS,
	CC_OR_fila6_InBUS,
	CC_OR_fila5_InBUS,
	CC_OR_fila4_InBUS,
	CC_OR_fila3_InBUS,
	CC_OR_fila2_InBUS,
	CC_OR_fila1_InBUS,
	CC_OR_fila0_InBUS
);



parameter NUMBER_DATAWIDTH = 8;




output 	[NUMBER_DATAWIDTH-1:0] CC_OR_OutBUS;

input 	[NUMBER_DATAWIDTH-1:0] CC_OR_fila7_InBUS;
input 	[NUMBER_DATAWIDTH-1:0] CC_OR_fila6_InBUS;
input 	[NUMBER_DATAWIDTH-1:0] CC_OR_fila5_InBUS;
input 	[NUMBER_DATAWIDTH-1:0] CC_OR_fila4_InBUS;
input 	[NUMBER_DATAWIDTH-1:0] CC_OR_fila3_InBUS;
input 	[NUMBER_DATAWIDTH-1:0] CC_OR_fila2_InBUS;
input 	[NUMBER_DATAWIDTH-1:0] CC_OR_fila1_InBUS;
input 	[NUMBER_DATAWIDTH-1:0] CC_OR_fila0_InBUS;







	
or(CC_OR_OutBUS, CC_OR_fila7_InBUS, CC_OR_fila6_InBUS, CC_OR_fila5_InBUS, CC_OR_fila4_InBUS, CC_OR_fila3_InBUS, CC_OR_fila2_InBUS, CC_OR_fila1_InBUS, CC_OR_fila0_InBUS);

endmodule
module CC_OR (



	CC_OR_OutBUS,
	


	CC_OR_fila7_InBUS,
	CC_OR_fila6_InBUS,
	CC_OR_fila5_InBUS,
	CC_OR_fila4_InBUS,
	CC_OR_fila3_InBUS,
	CC_OR_fila2_InBUS,
	CC_OR_fila1_InBUS,
	CC_OR_fila0_InBUS
);




parameter NUMBER_DATAWIDTH = 8;




output 	[NUMBER_DATAWIDTH-1:0] CC_OR_OutBUS;

input 	[NUMBER_DATAWIDTH-1:0] CC_OR_fila7_InBUS;
input 	[NUMBER_DATAWIDTH-1:0] CC_OR_fila6_InBUS;
input 	[NUMBER_DATAWIDTH-1:0] CC_OR_fila5_InBUS;
input 	[NUMBER_DATAWIDTH-1:0] CC_OR_fila4_InBUS;
input 	[NUMBER_DATAWIDTH-1:0] CC_OR_fila3_InBUS;
input 	[NUMBER_DATAWIDTH-1:0] CC_OR_fila2_InBUS;
input 	[NUMBER_DATAWIDTH-1:0] CC_OR_fila1_InBUS;
input 	[NUMBER_DATAWIDTH-1:0] CC_OR_fila0_InBUS;







	
or(CC_OR_OutBUS, CC_OR_fila7_InBUS, CC_OR_fila6_InBUS, CC_OR_fila5_InBUS, CC_OR_fila4_InBUS, CC_OR_fila3_InBUS, CC_OR_fila2_InBUS, CC_OR_fila1_InBUS, CC_OR_fila0_InBUS);

endmodule