data/full_repos/permissive/472025725/assignment_2/assignment_2tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/472025725/assignment_2/assignment_2tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n#5 clk1 = 1; #5 clk1 =0;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/472025725/assignment_2/assignment_2tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n#5 clk1 = 1; #5 clk1 =0;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/472025725/assignment_2/assignment_2tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n#5 clk2 = 1; #5 clk2 =0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/472025725/assignment_2/assignment_2tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n#5 clk2 = 1; #5 clk2 =0;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/472025725/assignment_2/assignment_2tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #5 rs1 =3; rs2 =5; rd =10 ; func =0; addr =125;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/472025725/assignment_2/assignment_2tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n #20 rs1 =3; rs2 =8; rd =12 ; func =2; addr =126;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/472025725/assignment_2/assignment_2tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n #20 rs1 =10; rs2 =5; rd =14 ; func =1; addr =128;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/472025725/assignment_2/assignment_2tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n #20 rs1 =7; rs2 =3; rd =13 ; func =11; addr =127;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/472025725/assignment_2/assignment_2tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n #20 rs1 =10; rs2 =5; rd =15 ; func =1; addr =129;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/472025725/assignment_2/assignment_2tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n #20 rs1 =12; rs2 =13; rd =16 ; func =0; addr =130;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/472025725/assignment_2/assignment_2tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n #60 for(k= 215; k<131; k =k+1)\n ^\n%Error: data/full_repos/permissive/472025725/assignment_2/assignment_2tb.v:51: Unsupported or unknown PLI call: $dumpfile\n   $dumpfile ("pipe_a.vcd");\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/472025725/assignment_2/assignment_2tb.v:52: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0 , pipe_a_tb);\n^~~~~~~~~\n%Error: data/full_repos/permissive/472025725/assignment_2/assignment_2tb.v:53: Unsupported or unknown PLI call: $monitor\n$monitor("Time : %3d , F = %3d ", $time ,Z);\n^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/472025725/assignment_2/assignment_2tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n#300;\n^\n%Error: Exiting due to 3 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pipe_a_tb;


reg [3:0] rs1;
reg [3:0] rs2;
reg [3:0] rd;
reg [3:0] func;
reg [7:0] addr;
reg clk1;
reg clk2;
integer k;


wire [15:0] Z;

pipe_a PIPE(Z ,rs1,rs2,rd,func,addr,clk1,clk2);

initial begin

clk1 = 0;
clk2 = 0;
repeat(20)
begin
#5 clk1 = 1; #5 clk1 =0;
#5 clk2 = 1; #5 clk2 =0;
      end

end

initial
for(k=0;k<16;k=k+1)
PIPE.regbank[k]= k;
     
initial
 begin
 #5 rs1 =3; rs2 =5; rd =10 ; func =0; addr =125;
 #20 rs1 =3; rs2 =8; rd =12 ; func =2; addr =126;
 #20 rs1 =10; rs2 =5; rd =14 ; func =1; addr =128;
 #20 rs1 =7; rs2 =3; rd =13 ; func =11; addr =127;
 #20 rs1 =10; rs2 =5; rd =15 ; func =1; addr =129;
 #20 rs1 =12; rs2 =13; rd =16 ; func =0; addr =130;
 #60 for(k= 215; k<131; k =k+1)
   $display("Mem[%3d] = %3d", k, PIPE.mem[k]);
 end
 
 
 initial
 begin
   $dumpfile ("pipe_a.vcd");
$dumpvars(0 , pipe_a_tb);
$monitor("Time : %3d , F = %3d ", $time ,Z);
#300;
 end

endmodule
module pipe_a_tb;



reg [3:0] rs1;
reg [3:0] rs2;
reg [3:0] rd;
reg [3:0] func;
reg [7:0] addr;
reg clk1;
reg clk2;
integer k;


wire [15:0] Z;

pipe_a PIPE(Z ,rs1,rs2,rd,func,addr,clk1,clk2);

initial begin

clk1 = 0;
clk2 = 0;
repeat(20)
begin
#5 clk1 = 1; #5 clk1 =0;
#5 clk2 = 1; #5 clk2 =0;
      end

end

initial
for(k=0;k<16;k=k+1)
PIPE.regbank[k]= k;
     
initial
 begin
 #5 rs1 =3; rs2 =5; rd =10 ; func =0; addr =125;
 #20 rs1 =3; rs2 =8; rd =12 ; func =2; addr =126;
 #20 rs1 =10; rs2 =5; rd =14 ; func =1; addr =128;
 #20 rs1 =7; rs2 =3; rd =13 ; func =11; addr =127;
 #20 rs1 =10; rs2 =5; rd =15 ; func =1; addr =129;
 #20 rs1 =12; rs2 =13; rd =16 ; func =0; addr =130;
 #60 for(k= 215; k<131; k =k+1)
   $display("Mem[%3d] = %3d", k, PIPE.mem[k]);
 end
 
 
 initial
 begin
   $dumpfile ("pipe_a.vcd");
$dumpvars(0 , pipe_a_tb);
$monitor("Time : %3d , F = %3d ", $time ,Z);
#300;
 end

endmodule