data/full_repos/permissive/432564927/Lab4 (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new/CPU.v
1: b'%Error: Cannot find file containing module: (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927\n        ... Looked in:\n             data/full_repos/permissive/432564927/Lab4/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927\n             data/full_repos/permissive/432564927/Lab4/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             data/full_repos/permissive/432564927/Lab4/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927\n             (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             obj_dir/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927\n             obj_dir/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             obj_dir/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/432564927/Lab4\n%Error: Cannot find file containing module: (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new/CPU.v\n%Error: Exiting due to 3 error(s)\n'
module IDEXE(clk, wreg, m2reg, wmem, aluc, aluimm, mux, qa, qb, extend,
            ewreg, em2reg, ewmem, ealuc, ealuimm, emux, eqa, eqb, eextend);
    input clk; 
    input wreg, m2reg, wmem, aluimm;
    input [4:0] mux;
    input [3:0] aluc;
    input [31:0] extend, qa, qb;
    

    reg wreg2, m2reg2, wmem2, aluimm2;
    reg [4:0] mux2;
    reg [3:0] aluc2;
    reg [31:0] qa2, qb2;
    reg [31:0] extend2;
    
    output reg ewreg, em2reg, ewmem, ealuimm;
    output reg [3:0] ealuc;
    output reg [4:0] emux;
    output reg [31:0] eqa, eqb;
    output reg [31:0] eextend;

    always@(posedge clk) begin
        wreg2 <= wreg;
        m2reg2 <= m2reg;
        wmem2 <= wmem;
        aluimm2 <= aluimm;
        mux2 <= mux;
        aluc2 <= aluc;
        qa2 <= qa;
        qb2 <= qb;
        extend2 <= extend;
    end
    
    always@(negedge clk) begin
        ewreg <= wreg2;
        em2reg <= m2reg2;
        ewmem <= wmem2;
        ealuimm <= aluimm2;
        emux <= mux2;
        ealuc <= aluc2;
        eqa <= qa2;
        eqb <= qb2;
        eextend <= extend2;
    end
endmodule
module IDEXE(clk, wreg, m2reg, wmem, aluc, aluimm, mux, qa, qb, extend,
            ewreg, em2reg, ewmem, ealuc, ealuimm, emux, eqa, eqb, eextend);

    input clk; 
    input wreg, m2reg, wmem, aluimm;
    input [4:0] mux;
    input [3:0] aluc;
    input [31:0] extend, qa, qb;
    

    reg wreg2, m2reg2, wmem2, aluimm2;
    reg [4:0] mux2;
    reg [3:0] aluc2;
    reg [31:0] qa2, qb2;
    reg [31:0] extend2;
    
    output reg ewreg, em2reg, ewmem, ealuimm;
    output reg [3:0] ealuc;
    output reg [4:0] emux;
    output reg [31:0] eqa, eqb;
    output reg [31:0] eextend;

    always@(posedge clk) begin
        wreg2 <= wreg;
        m2reg2 <= m2reg;
        wmem2 <= wmem;
        aluimm2 <= aluimm;
        mux2 <= mux;
        aluc2 <= aluc;
        qa2 <= qa;
        qb2 <= qb;
        extend2 <= extend;
    end
    
    always@(negedge clk) begin
        ewreg <= wreg2;
        em2reg <= m2reg2;
        ewmem <= wmem2;
        ealuimm <= aluimm2;
        emux <= mux2;
        ealuc <= aluc2;
        eqa <= qa2;
        eqb <= qb2;
        eextend <= extend2;
    end
endmodule