data/full_repos/permissive/418753455/smart_run/logical/ahb/ahb_fifo_entry.v
1: b'%Warning-WIDTH: data/full_repos/permissive/418753455/smart_run/logical/ahb/ahb_fifo_entry.v:43: Operator ASSIGNDLY expects 55 bits on the Assign RHS, but Assign RHS\'s CONST \'54\'h0\' generates 54 bits.\n                                                                                              : ... In instance ahb_fifo_entry\n    data_out[54:0] <= 54\'b0;\n                   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module ahb_fifo_entry(
  create_en,
  data_in,
  data_out,
  entry_clk,
  entry_rst_b
);


input           create_en;  
input   [54:0]  data_in;    
input           entry_clk;  
input           entry_rst_b; 
output  [54:0]  data_out;   


reg     [54:0]  data_out;   


wire            create_en;  
wire    [54:0]  data_in;    
wire            entry_clk;  
wire            entry_rst_b; 


always @(posedge entry_clk or negedge entry_rst_b)
begin
  if (!entry_rst_b)
    data_out[54:0] <= 54'b0;
  else if (create_en)
    data_out[54:0] <= data_in[54:0];
  else
    data_out[54:0] <= data_out[54:0];
end







endmodule
module ahb_fifo_entry(
  create_en,
  data_in,
  data_out,
  entry_clk,
  entry_rst_b
);



input           create_en;  
input   [54:0]  data_in;    
input           entry_clk;  
input           entry_rst_b; 
output  [54:0]  data_out;   


reg     [54:0]  data_out;   


wire            create_en;  
wire    [54:0]  data_in;    
wire            entry_clk;  
wire            entry_rst_b; 


always @(posedge entry_clk or negedge entry_rst_b)
begin
  if (!entry_rst_b)
    data_out[54:0] <= 54'b0;
  else if (create_en)
    data_out[54:0] <= data_in[54:0];
  else
    data_out[54:0] <= data_out[54:0];
end







endmodule