data/full_repos/permissive/420259327/IP/testPatternGen.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/420259327/IP/testPatternGen.v:67: Cell has missing pin: \'rst\'\n  Sync_To_Count sync (.i_Clk      (i_Clk),\n                ^~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/420259327/IP/testPatternGen.v:67: Cell has missing pin: \'o_HSync\'\n  Sync_To_Count sync (.i_Clk      (i_Clk),\n                ^~~~\n%Warning-PINMISSING: data/full_repos/permissive/420259327/IP/testPatternGen.v:67: Cell has missing pin: \'o_VSync\'\n  Sync_To_Count sync (.i_Clk      (i_Clk),\n                ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/420259327/IP/testPatternGen.v:306: Signal definition not found, creating implicitly: \'h_Frame_Start\'\n                                                                               : ... Suggested alternative: \'w_Frame_Start\'\n        if(h_Frame_Start) begin\n           ^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/420259327/IP/testPatternGen.v:93: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                           : ... In instance testPatternGen\n  assign Pattern_Red[2] = 1\'b1;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/420259327/IP/testPatternGen.v:94: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                           : ... In instance testPatternGen\n  assign Pattern_Grn[2] = 1\'b1;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/420259327/IP/testPatternGen.v:95: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                           : ... In instance testPatternGen\n  assign Pattern_Blu[2] = 1\'b1;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/420259327/IP/testPatternGen.v:168: Operator OR expects 3 bits on the LHS, but LHS\'s EQ generates 1 bits.\n                                                                            : ... In instance testPatternGen\n  assign Pattern_Red[11] = ((w_Col_Count&60)==0) | ((w_Row_Count&60)==0);\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/420259327/IP/testPatternGen.v:168: Operator OR expects 3 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                            : ... In instance testPatternGen\n  assign Pattern_Red[11] = ((w_Col_Count&60)==0) | ((w_Row_Count&60)==0);\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/420259327/IP/testPatternGen.v:169: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n                                                                            : ... In instance testPatternGen\n  assign Pattern_Grn[11] = w_Row_Count[7];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/420259327/IP/testPatternGen.v:170: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n                                                                            : ... In instance testPatternGen\n  assign Pattern_Blu[11] = w_Col_Count[7];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/420259327/IP/testPatternGen.v:175: Operator OR expects 3 bits on the LHS, but LHS\'s EQ generates 1 bits.\n                                                                            : ... In instance testPatternGen\n  assign Pattern_Red[12] = ((w_Col_Count&60)==0) | ((w_Row_Count&60)==0);\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/420259327/IP/testPatternGen.v:175: Operator OR expects 3 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                            : ... In instance testPatternGen\n  assign Pattern_Red[12] = ((w_Col_Count&60)==0) | ((w_Row_Count&60)==0);\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/420259327/IP/testPatternGen.v:176: Operator AND expects 3 bits on the LHS, but LHS\'s EQ generates 1 bits.\n                                                                            : ... In instance testPatternGen\n  assign Pattern_Grn[12] = ((w_Col_Count&32)==0) & ((w_Row_Count&32)==0);\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/420259327/IP/testPatternGen.v:176: Operator AND expects 3 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                            : ... In instance testPatternGen\n  assign Pattern_Grn[12] = ((w_Col_Count&32)==0) & ((w_Row_Count&32)==0);\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/420259327/IP/testPatternGen.v:177: Operator XOR expects 3 bits on the LHS, but LHS\'s EQ generates 1 bits.\n                                                                            : ... In instance testPatternGen\n  assign Pattern_Blu[12] = ((w_Col_Count&40)==0) ^ ((w_Row_Count&40)==0);\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/420259327/IP/testPatternGen.v:177: Operator XOR expects 3 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                            : ... In instance testPatternGen\n  assign Pattern_Blu[12] = ((w_Col_Count&40)==0) ^ ((w_Row_Count&40)==0);\n                                                 ^\n%Error: Exiting due to 17 warning(s)\n'
module Sync_To_Count 
  (input            i_Clk,
  input             rst,
   input            i_HSync,
   input            i_VSync,
   output reg       o_HSync = 0, 
   output reg       o_VSync = 0,
   output reg [10:0] o_Col_Count = 0,
   output reg [10:0] o_Row_Count = 0);
   
   wire w_Frame_Start;
   

  always @(posedge i_Clk)
  begin
    o_VSync <= i_VSync;
    o_HSync <= i_HSync;
  end
  

   


  always @(posedge i_Clk)
    begin
    
        
        
        if(w_Frame_Start) begin
            o_Row_Count <= 0;
        end else begin
        
        if(h_Frame_Start) begin
            o_Col_Count <= 0;
            o_Row_Count <= o_Row_Count + 1;
        end else begin
            o_Col_Count <= o_Col_Count + 1;
        end
        
            
            
            
            
        end
    
    end
  

  

  assign w_Frame_Start = (~o_VSync & i_VSync);
  assign h_Frame_Start = (~o_HSync & i_HSync);
  


  
endmodule
module Sync_To_Count 
  (input            i_Clk,
  input             rst,
   input            i_HSync,
   input            i_VSync,
   output reg       o_HSync = 0, 
   output reg       o_VSync = 0,
   output reg [10:0] o_Col_Count = 0,
   output reg [10:0] o_Row_Count = 0);

   
   wire w_Frame_Start;
   

  always @(posedge i_Clk)
  begin
    o_VSync <= i_VSync;
    o_HSync <= i_HSync;
  end
  

   


  always @(posedge i_Clk)
    begin
    
        
        
        if(w_Frame_Start) begin
            o_Row_Count <= 0;
        end else begin
        
        if(h_Frame_Start) begin
            o_Col_Count <= 0;
            o_Row_Count <= o_Row_Count + 1;
        end else begin
            o_Col_Count <= o_Col_Count + 1;
        end
        
            
            
            
            
        end
    
    end
  

  

  assign w_Frame_Start = (~o_VSync & i_VSync);
  assign h_Frame_Start = (~o_HSync & i_HSync);
  


  
endmodule