data/full_repos/permissive/470590146/core/wb_stage.v
1: b'%Warning-WIDTH: data/full_repos/permissive/470590146/core/wb_stage.v:36: Operator ASSIGNW expects 39 bits on the Assign RHS, but Assign RHS\'s VARREF \'ms2ws_bus\' generates 38 bits.\n                                                                       : ... In instance wb_stage\n} = ms2ws_bus;\n  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module wb_stage (
	 input clk
	,input rst_n

	,input  [31:0] 	ms_mem_out
    ,input  [37:0]  ms2ws_bus

	,output [ 4:0]  ws_rd
	,output 		ws_reg_wen
	,output [31:0]  ws_reg_wdata
    ,output         ws_ready
);


wire [31:0] ms_alu_result;
wire [ 4:0] ms_rd;
wire [ 1:0] ms_ctrl;
assign {
    ms_alu_result,
    ms_rd,
    ms_ctrl
} = ms2ws_bus;

wire   mem2reg      = ms_ctrl[1];
assign ws_reg_wen   = ms_ctrl[0];

assign ws_reg_wdata = mem2reg == 1'b1 ? ms_mem_out : ms_alu_result;
assign ws_rd        = ms_rd;

assign ws_ready     = 1'b1;

endmodule
module wb_stage (
	 input clk
	,input rst_n

	,input  [31:0] 	ms_mem_out
    ,input  [37:0]  ms2ws_bus

	,output [ 4:0]  ws_rd
	,output 		ws_reg_wen
	,output [31:0]  ws_reg_wdata
    ,output         ws_ready
);



wire [31:0] ms_alu_result;
wire [ 4:0] ms_rd;
wire [ 1:0] ms_ctrl;
assign {
    ms_alu_result,
    ms_rd,
    ms_ctrl
} = ms2ws_bus;

wire   mem2reg      = ms_ctrl[1];
assign ws_reg_wen   = ms_ctrl[0];

assign ws_reg_wdata = mem2reg == 1'b1 ? ms_mem_out : ms_alu_result;
assign ws_rd        = ms_rd;

assign ws_ready     = 1'b1;

endmodule