data/full_repos/permissive/444555755/mp4/hdl/m_extension/muldiv.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/444555755/mp4/hdl/m_extension/muldiv.sv:36: Operator EQ expects 7 bits on the LHS, but LHS\'s VARREF \'muldivop\' generates 3 bits.\n                                                                                     : ... In instance muldiv\nassign mul_start = (start && muldivop == 7\'d0) ? 1\'b1 : 1\'b0;\n                                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/444555755/mp4/hdl/m_extension/muldiv.sv:37: Operator EQ expects 7 bits on the LHS, but LHS\'s VARREF \'muldivop\' generates 3 bits.\n                                                                                     : ... In instance muldiv\nassign mulh_start = (start && muldivop == 7\'d1) ? 1\'b1 : 1\'b0;\n                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/444555755/mp4/hdl/m_extension/muldiv.sv:38: Operator EQ expects 7 bits on the LHS, but LHS\'s VARREF \'muldivop\' generates 3 bits.\n                                                                                     : ... In instance muldiv\nassign mulsu_start = (start && muldivop == 7\'d2) ? 1\'b1 : 1\'b0;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/444555755/mp4/hdl/m_extension/muldiv.sv:39: Operator EQ expects 7 bits on the LHS, but LHS\'s VARREF \'muldivop\' generates 3 bits.\n                                                                                     : ... In instance muldiv\nassign mulhu_start = (start && muldivop == 7\'d3) ? 1\'b1 : 1\'b0;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/444555755/mp4/hdl/m_extension/muldiv.sv:40: Operator EQ expects 7 bits on the LHS, but LHS\'s VARREF \'muldivop\' generates 3 bits.\n                                                                                     : ... In instance muldiv\nassign div_start = (start && muldivop == 7\'d4) ? 1\'b1 : 1\'b0;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/444555755/mp4/hdl/m_extension/muldiv.sv:41: Operator EQ expects 7 bits on the LHS, but LHS\'s VARREF \'muldivop\' generates 3 bits.\n                                                                                     : ... In instance muldiv\nassign divu_start = (start && muldivop == 7\'d5) ? 1\'b1 : 1\'b0;\n                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/444555755/mp4/hdl/m_extension/muldiv.sv:42: Operator EQ expects 7 bits on the LHS, but LHS\'s VARREF \'muldivop\' generates 3 bits.\n                                                                                     : ... In instance muldiv\nassign rem_start = (start && muldivop == 7\'d6) ? 1\'b1 : 1\'b0;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/444555755/mp4/hdl/m_extension/muldiv.sv:43: Operator EQ expects 7 bits on the LHS, but LHS\'s VARREF \'muldivop\' generates 3 bits.\n                                                                                     : ... In instance muldiv\nassign remu_start = (start && muldivop == 7\'d7) ? 1\'b1 : 1\'b0;\n                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/444555755/mp4/hdl/m_extension/muldiv.sv:60: Operator CASE expects 7 bits on the Case expression, but Case expression\'s VARREF \'muldivop\' generates 3 bits.\n                                                                                     : ... In instance muldiv\n    case(muldivop)\n    ^~~~\n%Error: data/full_repos/permissive/444555755/mp4/hdl/m_extension/muldiv.sv:130: Cannot find file containing module: \'multiplier\'\nmultiplier mul(\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/444555755/mp4/hdl/m_extension,data/full_repos/permissive/444555755/multiplier\n             data/full_repos/permissive/444555755/mp4/hdl/m_extension,data/full_repos/permissive/444555755/multiplier.v\n             data/full_repos/permissive/444555755/mp4/hdl/m_extension,data/full_repos/permissive/444555755/multiplier.sv\n             multiplier\n             multiplier.v\n             multiplier.sv\n             obj_dir/multiplier\n             obj_dir/multiplier.v\n             obj_dir/multiplier.sv\n%Error: data/full_repos/permissive/444555755/mp4/hdl/m_extension/muldiv.sv:141: Cannot find file containing module: \'divider\'\ndivider div(\n^~~~~~~\n%Error: Exiting due to 2 error(s), 9 warning(s)\n'
module muldiv
(
    input logic clk,
    input logic rst,
    input logic start,
    input logic [2:0] muldivop,
    input logic [31:0] a,
    input logic [31:0] b,
    output logic muldiv_resp,
    output logic [31:0] result
);


logic [31:0] numerator;
logic [31:0] denominator;
logic [31:0] quotient;
logic [31:0] remainder;
logic [31:0] multiplicand;
logic [31:0] multiplier;
logic [63:0] product;
logic neg_bit;
logic mul_start;
logic mulh_start;
logic mulsu_start;
logic mulhu_start;
logic div_start;
logic divu_start;
logic rem_start;
logic remu_start;
logic mul_resp;
logic div_resp;




assign mul_start = (start && muldivop == 7'd0) ? 1'b1 : 1'b0;
assign mulh_start = (start && muldivop == 7'd1) ? 1'b1 : 1'b0;
assign mulsu_start = (start && muldivop == 7'd2) ? 1'b1 : 1'b0;
assign mulhu_start = (start && muldivop == 7'd3) ? 1'b1 : 1'b0;
assign div_start = (start && muldivop == 7'd4) ? 1'b1 : 1'b0;
assign divu_start = (start && muldivop == 7'd5) ? 1'b1 : 1'b0;
assign rem_start = (start && muldivop == 7'd6) ? 1'b1 : 1'b0;
assign remu_start = (start && muldivop == 7'd7) ? 1'b1 : 1'b0;


function void set_defaults();
    multiplicand = 0;
    multiplier = 0;
    numerator = 0;
    denominator = 0;
    neg_bit = 0;
    result = 0;
    muldiv_resp = 0;
endfunction

always_comb 
begin : result_logic

    set_defaults();
    case(muldivop)

        7'd0: begin
            multiplicand = (a[31] == 1'b1) ? (~a) + 32'd1 : a;
            multiplier = (b[31] == 1'b1) ? (~b) + 32'd1 : b;
            neg_bit = (a[31] ^ b[31]);
            result = (neg_bit) ? (~product[31:0]) + 32'd1 : product[31:0];
            muldiv_resp = mul_resp;
        end

        7'd1: begin
            multiplicand = (a[31] == 1'b1) ? (~a) + 32'd1 : a;
            multiplier = (b[31] == 1'b1) ? (~b) + 32'd1 : b;
            neg_bit = (a[31] ^ b[31]);
            result = (neg_bit) ? (~product[63:32]) + 32'd1 : product[63:32];
            muldiv_resp = mul_resp;            
        end

        7'd2: begin
            multiplicand = (a[31] == 1'b1) ? (~a) + 32'd1 : a;
            multiplier = b;
            neg_bit = a[31];
            result = (neg_bit) ? (~product[63:32]) + 32'd1 : product[63:32];
            muldiv_resp = mul_resp;          
        end

        7'd3: begin
            multiplicand = a;
            multiplier = b;
            neg_bit = 1'b0;
            result = product[63:32];
            muldiv_resp = mul_resp;              
        end

        7'd4: begin
            numerator = (a[31] == 1'b1) ? (~a) + 32'd1 : a;
            denominator = (b[31] == 1'b1) ? (~b) + 32'd1 : b;
            neg_bit = (a[31] ^ b[31]);
            result = (neg_bit) ? (~quotient) + 32'd1 : quotient;
            muldiv_resp = div_resp;
        end

        7'd5: begin
            numerator = a;
            denominator = b;
            neg_bit = 1'b0;
            result = quotient;
            muldiv_resp = div_resp;
        end

        7'd6: begin
            numerator = (a[31] == 1'b1) ? (~a) + 32'd1 : a;
            denominator = (b[31] == 1'b1) ? (~b) + 32'd1 : b;
            neg_bit = a[31];
            result = (neg_bit) ? (~remainder) + 32'd1 : remainder;
            muldiv_resp = div_resp;
        end

        7'd7: begin
            numerator = a;
            denominator = b;
            neg_bit = 1'b0;
            result = remainder;
            muldiv_resp = div_resp;
        end
        default:;
    endcase
end


multiplier mul(
    .clk(clk),
    .rst(rst),
    .start(mul_start || mulh_start || mulsu_start || mulhu_start),
    .multiplicand(multiplicand),
    .multiplier(multiplier),
    .product(product),
    .mul_resp(mul_resp)
);


divider div(
    .clk(clk),
    .rst(rst),
    .start(div_start || divu_start || rem_start || remu_start),
    .numerator(numerator),
    .denominator(denominator),
    .quotient(quotient),
    .remainder(remainder),
    .div_resp(div_resp)
);

endmodule
module muldiv
(
    input logic clk,
    input logic rst,
    input logic start,
    input logic [2:0] muldivop,
    input logic [31:0] a,
    input logic [31:0] b,
    output logic muldiv_resp,
    output logic [31:0] result
);



logic [31:0] numerator;
logic [31:0] denominator;
logic [31:0] quotient;
logic [31:0] remainder;
logic [31:0] multiplicand;
logic [31:0] multiplier;
logic [63:0] product;
logic neg_bit;
logic mul_start;
logic mulh_start;
logic mulsu_start;
logic mulhu_start;
logic div_start;
logic divu_start;
logic rem_start;
logic remu_start;
logic mul_resp;
logic div_resp;




assign mul_start = (start && muldivop == 7'd0) ? 1'b1 : 1'b0;
assign mulh_start = (start && muldivop == 7'd1) ? 1'b1 : 1'b0;
assign mulsu_start = (start && muldivop == 7'd2) ? 1'b1 : 1'b0;
assign mulhu_start = (start && muldivop == 7'd3) ? 1'b1 : 1'b0;
assign div_start = (start && muldivop == 7'd4) ? 1'b1 : 1'b0;
assign divu_start = (start && muldivop == 7'd5) ? 1'b1 : 1'b0;
assign rem_start = (start && muldivop == 7'd6) ? 1'b1 : 1'b0;
assign remu_start = (start && muldivop == 7'd7) ? 1'b1 : 1'b0;


function void set_defaults();
    multiplicand = 0;
    multiplier = 0;
    numerator = 0;
    denominator = 0;
    neg_bit = 0;
    result = 0;
    muldiv_resp = 0;
endfunction

always_comb 
begin : result_logic

    set_defaults();
    case(muldivop)

        7'd0: begin
            multiplicand = (a[31] == 1'b1) ? (~a) + 32'd1 : a;
            multiplier = (b[31] == 1'b1) ? (~b) + 32'd1 : b;
            neg_bit = (a[31] ^ b[31]);
            result = (neg_bit) ? (~product[31:0]) + 32'd1 : product[31:0];
            muldiv_resp = mul_resp;
        end

        7'd1: begin
            multiplicand = (a[31] == 1'b1) ? (~a) + 32'd1 : a;
            multiplier = (b[31] == 1'b1) ? (~b) + 32'd1 : b;
            neg_bit = (a[31] ^ b[31]);
            result = (neg_bit) ? (~product[63:32]) + 32'd1 : product[63:32];
            muldiv_resp = mul_resp;            
        end

        7'd2: begin
            multiplicand = (a[31] == 1'b1) ? (~a) + 32'd1 : a;
            multiplier = b;
            neg_bit = a[31];
            result = (neg_bit) ? (~product[63:32]) + 32'd1 : product[63:32];
            muldiv_resp = mul_resp;          
        end

        7'd3: begin
            multiplicand = a;
            multiplier = b;
            neg_bit = 1'b0;
            result = product[63:32];
            muldiv_resp = mul_resp;              
        end

        7'd4: begin
            numerator = (a[31] == 1'b1) ? (~a) + 32'd1 : a;
            denominator = (b[31] == 1'b1) ? (~b) + 32'd1 : b;
            neg_bit = (a[31] ^ b[31]);
            result = (neg_bit) ? (~quotient) + 32'd1 : quotient;
            muldiv_resp = div_resp;
        end

        7'd5: begin
            numerator = a;
            denominator = b;
            neg_bit = 1'b0;
            result = quotient;
            muldiv_resp = div_resp;
        end

        7'd6: begin
            numerator = (a[31] == 1'b1) ? (~a) + 32'd1 : a;
            denominator = (b[31] == 1'b1) ? (~b) + 32'd1 : b;
            neg_bit = a[31];
            result = (neg_bit) ? (~remainder) + 32'd1 : remainder;
            muldiv_resp = div_resp;
        end

        7'd7: begin
            numerator = a;
            denominator = b;
            neg_bit = 1'b0;
            result = remainder;
            muldiv_resp = div_resp;
        end
        default:;
    endcase
end


multiplier mul(
    .clk(clk),
    .rst(rst),
    .start(mul_start || mulh_start || mulsu_start || mulhu_start),
    .multiplicand(multiplicand),
    .multiplier(multiplier),
    .product(product),
    .mul_resp(mul_resp)
);


divider div(
    .clk(clk),
    .rst(rst),
    .start(div_start || divu_start || rem_start || remu_start),
    .numerator(numerator),
    .denominator(denominator),
    .quotient(quotient),
    .remainder(remainder),
    .div_resp(div_resp)
);

endmodule