data/full_repos/permissive/495609183/memLCDdriver/src/fifomem.v
data/verilator_xmls/66f57f0c-9a2f-43d2-86fe-e4c0a071e6c3.xml
module fifomem #(
	parameter DATA_WIDTH = 8,
	parameter ADDR_WIDTH = 4,
	parameter FIFO_DEPTH = (1 << ADDR_WIDTH)
)(
	output 	[DATA_WIDTH-1:0] 	o_rdata,
	input 	[DATA_WIDTH-1:0] 	i_wdata,
	input 	[ADDR_WIDTH-1:0] 	i_waddr, 
	input 	[ADDR_WIDTH-1:0] 	i_raddr,
	input 						i_wclken,
	input						i_wclk
);

	reg [DATA_WIDTH-1:0] MEM [0:FIFO_DEPTH-1];

	assign o_rdata = MEM[i_raddr];

	always @(posedge i_wclk) begin
		if (i_wclken) begin 
			MEM[i_waddr] <= i_wdata;
		end
	end

endmodule
module fifomem #(
	parameter DATA_WIDTH = 8,
	parameter ADDR_WIDTH = 4,
	parameter FIFO_DEPTH = (1 << ADDR_WIDTH)
)(
	output 	[DATA_WIDTH-1:0] 	o_rdata,
	input 	[DATA_WIDTH-1:0] 	i_wdata,
	input 	[ADDR_WIDTH-1:0] 	i_waddr, 
	input 	[ADDR_WIDTH-1:0] 	i_raddr,
	input 						i_wclken,
	input						i_wclk
);


	reg [DATA_WIDTH-1:0] MEM [0:FIFO_DEPTH-1];

	assign o_rdata = MEM[i_raddr];

	always @(posedge i_wclk) begin
		if (i_wclken) begin 
			MEM[i_waddr] <= i_wdata;
		end
	end

endmodule