data/full_repos/permissive/461099925/salemachine/salem.v
1: b'%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:118: Value too large for 5 bit number: 40\n                        end  else if(residue < 5\'d40)begin \n                                               ^~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:121: Value too large for 5 bit number: 50\n                        end  else if(residue < 5\'d50)begin \n                                               ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:122: Value too large for 5 bit number: 40\n                            res_c[3:0]      <=  residue - 5\'d40 ;\n                                                          ^~~~~\n%Warning-MULTITOP: data/full_repos/permissive/461099925/salemachine/salem.v:158: Multiple top level modules\n                                                                               : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                               : ... Top module \'salem\'\nmodule salem(\n       ^~~~~\n                                                                               : ... Top module \'bcd2seg\'\nmodule bcd2seg(SW,SEG);\n       ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:63: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 5 bits.\n                                                                           : ... In instance salem\n            gm_c[3:0]      <=  swb - 5\'d10 ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:91: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                           : ... In instance salem\n            residue     <= 8\'h00;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:106: Operator SUB expects 6 bits on the LHS, but LHS\'s SEL generates 4 bits.\n                                                                            : ... In instance salem\n                                residue <=  (im_c[7:4] -item[swb][7:4])*4\'ha + im_c[3:0] - item[swb][3:0];\n                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:106: Operator SUB expects 6 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                            : ... In instance salem\n                                residue <=  (im_c[7:4] -item[swb][7:4])*4\'ha + im_c[3:0] - item[swb][3:0];\n                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:106: Operator ADD expects 6 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                            : ... In instance salem\n                                residue <=  (im_c[7:4] -item[swb][7:4])*4\'ha + im_c[3:0] - item[swb][3:0];\n                                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:106: Operator SUB expects 6 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                            : ... In instance salem\n                                residue <=  (im_c[7:4] -item[swb][7:4])*4\'ha + im_c[3:0] - item[swb][3:0];\n                                                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:111: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'residue\' generates 6 bits.\n                                                                            : ... In instance salem\n                            res_c      <=  residue     ;\n                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:113: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 6 bits.\n                                                                            : ... In instance salem\n                            res_c[3:0]      <=  residue - 5\'d10 ;\n                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:116: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 6 bits.\n                                                                            : ... In instance salem\n                            res_c[3:0]      <=  residue - 5\'d20 ;\n                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:119: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 6 bits.\n                                                                            : ... In instance salem\n                            res_c[3:0]      <=  residue - 5\'d30 ;\n                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:122: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 6 bits.\n                                                                            : ... In instance salem\n                            res_c[3:0]      <=  residue - 5\'d40 ;\n                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:121: Operator LT expects 6 bits on the RHS, but RHS\'s CONST \'5\'h12\' generates 5 bits.\n                                                                            : ... In instance salem\n                        end  else if(residue < 5\'d50)begin \n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:118: Operator LT expects 6 bits on the RHS, but RHS\'s CONST \'5\'h8\' generates 5 bits.\n                                                                            : ... In instance salem\n                        end  else if(residue < 5\'d40)begin \n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:115: Operator LT expects 6 bits on the RHS, but RHS\'s CONST \'5\'h1e\' generates 5 bits.\n                                                                            : ... In instance salem\n                        end  else if(residue < 5\'d30)begin \n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:112: Operator LT expects 6 bits on the RHS, but RHS\'s CONST \'5\'h14\' generates 5 bits.\n                                                                            : ... In instance salem\n                        else if(residue < 5\'d20) begin \n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:110: Operator LT expects 6 bits on the RHS, but RHS\'s CONST \'5\'ha\' generates 5 bits.\n                                                                            : ... In instance salem\n                        if(residue < 5\'d10)\n                                   ^\n%Error: Exiting due to 20 warning(s)\n'
module bcd2seg(SW,SEG);
  input [3:0]               SW;
  output reg[6:0]           SEG;
  parameter	cd0	= 7'b1000000,
            cd1	= 7'b1111001,
            cd2	= 7'b0100100,
            cd3	= 7'b0110000,
            cd4	= 7'b0011001,
            cd5	= 7'b0010010,
            cd6	= 7'b0000010,
            cd7	= 7'b1111000,
            cd8	= 7'b0000000,
            cd9	= 7'b0010000,
            cda	= 7'b0001000,
            cdb	= 7'b0000011,
            cdc	= 7'b1000110,
            cdd	= 7'b0100001,
            cde	= 7'b0000110,
            cdf	= 7'b0001110;
  always @(*)
  case(SW[3:0])
    4'h0: SEG[6:0] = cd0;
    4'h1: SEG[6:0] = cd1;
    4'h2: SEG[6:0] = cd2;
    4'h3: SEG[6:0] = cd3;
    4'h4: SEG[6:0] = cd4;
    4'h5: SEG[6:0] = cd5;
    4'h6: SEG[6:0] = cd6;
    4'h7: SEG[6:0] = cd7;
    4'h8: SEG[6:0] = cd8;
    4'h9: SEG[6:0] = cd9;
    4'ha: SEG[6:0] = cda;
    4'hb: SEG[6:0] = cdb;
    4'hc: SEG[6:0] = cdc;
    4'hd: SEG[6:0] = cdd;
    4'he: SEG[6:0] = cde;
    4'hf: SEG[6:0] = cdf;
    default:SEG[6:0] = cd0;
  endcase
endmodule
module bcd2seg(SW,SEG);

  input [3:0]               SW;
  output reg[6:0]           SEG;
  parameter	cd0	= 7'b1000000,
            cd1	= 7'b1111001,
            cd2	= 7'b0100100,
            cd3	= 7'b0110000,
            cd4	= 7'b0011001,
            cd5	= 7'b0010010,
            cd6	= 7'b0000010,
            cd7	= 7'b1111000,
            cd8	= 7'b0000000,
            cd9	= 7'b0010000,
            cda	= 7'b0001000,
            cdb	= 7'b0000011,
            cdc	= 7'b1000110,
            cdd	= 7'b0100001,
            cde	= 7'b0000110,
            cdf	= 7'b0001110;
  always @(*)
  case(SW[3:0])
    4'h0: SEG[6:0] = cd0;
    4'h1: SEG[6:0] = cd1;
    4'h2: SEG[6:0] = cd2;
    4'h3: SEG[6:0] = cd3;
    4'h4: SEG[6:0] = cd4;
    4'h5: SEG[6:0] = cd5;
    4'h6: SEG[6:0] = cd6;
    4'h7: SEG[6:0] = cd7;
    4'h8: SEG[6:0] = cd8;
    4'h9: SEG[6:0] = cd9;
    4'ha: SEG[6:0] = cda;
    4'hb: SEG[6:0] = cdb;
    4'hc: SEG[6:0] = cdc;
    4'hd: SEG[6:0] = cdd;
    4'he: SEG[6:0] = cde;
    4'hf: SEG[6:0] = cdf;
    default:SEG[6:0] = cd0;
  endcase
endmodule