data/full_repos/permissive/489075769/write_response_ms.v
1: b'%Warning-WIDTH: data/full_repos/permissive/489075769/write_response_ms.v:56: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                           : ... In instance write_response_ms.resp_s\no_BRESP <= 1\'b0;\n        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module write_response_master(ACLK,ARESETn, BVALID, i_BREADY, o_BREADY, i_BRESP, o_BRESP);
input ACLK, ARESETn;
input i_BREADY, BVALID;
input [1:0] i_BRESP;

output reg [1:0] o_BRESP;
output reg o_BREADY;
	
 
always @(posedge ACLK) begin
 o_BREADY <= i_BREADY; 
 o_BRESP <= i_BRESP; 
if (ARESETn) begin
o_BREADY <= 0;	
o_BRESP <= 0;
end
end

endmodule
module write_response_master(ACLK,ARESETn, BVALID, i_BREADY, o_BREADY, i_BRESP, o_BRESP);

input ACLK, ARESETn;
input i_BREADY, BVALID;
input [1:0] i_BRESP;

output reg [1:0] o_BRESP;
output reg o_BREADY;
	
 
always @(posedge ACLK) begin
 o_BREADY <= i_BREADY; 
 o_BRESP <= i_BRESP; 
if (ARESETn) begin
o_BREADY <= 0;	
o_BRESP <= 0;
end
end

endmodule