data/full_repos/permissive/516340086/level1_design2_corrected/seq_detect_1011.v
data/verilator_xmls/673ee88a-fed8-4da6-811e-2b775f2b517a.xml
module seq_detect_1011(seq_seen, inp_bit, reset, clk);

  output seq_seen;
  input inp_bit;
  input reset;
  input clk;

  parameter IDLE = 0,
            SEQ_1 = 1, 
            SEQ_11 = 2,
            SEQ_10  = 3,
            SEQ_101 = 4,
            SEQ_1011 = 5;

  reg [2:0] current_state, next_state;



  assign seq_seen = current_state == SEQ_1011 ? 1 : 0;


  always @(posedge clk)
  begin
    if(reset)
    begin
      current_state <= IDLE;
    end
    else
    begin
      current_state <= next_state;
    end
  end


  always @(inp_bit or current_state)
  begin
    case(current_state)
      IDLE:
      begin
        if(inp_bit == 1)
          next_state = SEQ_1;
        else
          next_state = IDLE;
      end
      SEQ_1:
      begin
        if(inp_bit == 1)
          next_state = SEQ_11;
        else
          next_state = SEQ_10;
      end

      SEQ_11:
      begin
        if(inp_bit == 1)
          next_state = IDLE;
        else
          next_state = SEQ_10;
      end
      
      SEQ_10:
      begin
        if(inp_bit == 1)
          next_state = SEQ_101;
        else
          next_state = IDLE;
      end
      
      SEQ_101:
      begin
        if(inp_bit == 1)
          next_state = SEQ_1011;
        else
          next_state = IDLE;
      end
      SEQ_1011:
      begin
        if(inp_bit == 0)
          next_state = SEQ_10;
        else
          next_state = IDLE;
      end
      default: next_state = IDLE;
     
    endcase
  end
endmodule
module seq_detect_1011(seq_seen, inp_bit, reset, clk);


  output seq_seen;
  input inp_bit;
  input reset;
  input clk;

  parameter IDLE = 0,
            SEQ_1 = 1, 
            SEQ_11 = 2,
            SEQ_10  = 3,
            SEQ_101 = 4,
            SEQ_1011 = 5;

  reg [2:0] current_state, next_state;



  assign seq_seen = current_state == SEQ_1011 ? 1 : 0;


  always @(posedge clk)
  begin
    if(reset)
    begin
      current_state <= IDLE;
    end
    else
    begin
      current_state <= next_state;
    end
  end


  always @(inp_bit or current_state)
  begin
    case(current_state)
      IDLE:
      begin
        if(inp_bit == 1)
          next_state = SEQ_1;
        else
          next_state = IDLE;
      end
      SEQ_1:
      begin
        if(inp_bit == 1)
          next_state = SEQ_11;
        else
          next_state = SEQ_10;
      end

      SEQ_11:
      begin
        if(inp_bit == 1)
          next_state = IDLE;
        else
          next_state = SEQ_10;
      end
      
      SEQ_10:
      begin
        if(inp_bit == 1)
          next_state = SEQ_101;
        else
          next_state = IDLE;
      end
      
      SEQ_101:
      begin
        if(inp_bit == 1)
          next_state = SEQ_1011;
        else
          next_state = IDLE;
      end
      SEQ_1011:
      begin
        if(inp_bit == 0)
          next_state = SEQ_10;
        else
          next_state = IDLE;
      end
      default: next_state = IDLE;
     
    endcase
  end
endmodule