data/full_repos/permissive/453449880/XILINX ISE 14.7 PROJECT FILE/clock_divider.v
1: b'%Error: Cannot find file containing module: ISE\n        ... Looked in:\n             data/full_repos/permissive/453449880/XILINX/ISE\n             data/full_repos/permissive/453449880/XILINX/ISE.v\n             data/full_repos/permissive/453449880/XILINX/ISE.sv\n             ISE\n             ISE.v\n             ISE.sv\n             obj_dir/ISE\n             obj_dir/ISE.v\n             obj_dir/ISE.sv\n%Error: Cannot find file containing module: 14.7\n%Error: Cannot find file containing module: PROJECT\n%Error: Cannot find file containing module: FILE,data/full_repos/permissive/453449880\n%Error: Cannot find file containing module: data/full_repos/permissive/453449880/XILINX\n%Error: Cannot find file containing module: FILE/clock_divider.v\n%Error: Exiting due to 6 error(s)\n'
module clock_divider(

i_clk , div_clk
    );
	 input i_clk ;
	 output reg div_clk ;
reg [26:0] cNT_REG ;
parameter count = 50_000_000;


always @ (posedge i_clk)
 begin
 if (cNT_REG == count-1 )
  begin
  div_clk = ~div_clk ;
  cNT_REG = 0 ;
  end
  else
  begin
  cNT_REG = cNT_REG + 1'b1 ;
  end
  end
endmodule
module clock_divider(

i_clk , div_clk
    );

	 input i_clk ;
	 output reg div_clk ;
reg [26:0] cNT_REG ;
parameter count = 50_000_000;


always @ (posedge i_clk)
 begin
 if (cNT_REG == count-1 )
  begin
  div_clk = ~div_clk ;
  cNT_REG = 0 ;
  end
  else
  begin
  cNT_REG = cNT_REG + 1'b1 ;
  end
  end
endmodule