data/full_repos/permissive/445379100/a4_synthesis/cpu.v
1: b"%Error: data/full_repos/permissive/445379100/a4_synthesis/cpu.v:13: Duplicate declaration of signal: 'iaddr'\n                                                                  : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n    reg [31:0] iaddr;   \n               ^~~~~\n        data/full_repos/permissive/445379100/a4_synthesis/cpu.v:8: ... Location of original declaration\n    output [31:0] iaddr,  \n                  ^~~~~\n%Error: data/full_repos/permissive/445379100/a4_synthesis/cpu.v:14: Duplicate declaration of signal: 'daddr'\n    reg [31:0] daddr;\n               ^~~~~\n        data/full_repos/permissive/445379100/a4_synthesis/cpu.v:9: ... Location of original declaration\n    output [31:0] daddr,  \n                  ^~~~~\n%Error: data/full_repos/permissive/445379100/a4_synthesis/cpu.v:15: Duplicate declaration of signal: 'dwdata'\n    reg [31:0] dwdata;\n               ^~~~~~\n        data/full_repos/permissive/445379100/a4_synthesis/cpu.v:10: ... Location of original declaration\n    output [31:0] dwdata,  \n                  ^~~~~~\n%Error: data/full_repos/permissive/445379100/a4_synthesis/cpu.v:16: Duplicate declaration of signal: 'dwe'\n    reg [3:0]  dwe;\n               ^~~\n        data/full_repos/permissive/445379100/a4_synthesis/cpu.v:11: ... Location of original declaration\n    output [3:0] dwe\n                 ^~~\n%Error: Exiting due to 4 error(s)\n"
module cpu (
    input clk, 
    input reset,
    input [31:0] idata,
    input [31:0] drdata,
    output [31:0] iaddr,
    output [31:0] daddr,
    output [31:0] dwdata,
    output [3:0] dwe
);
    reg [31:0] iaddr;
    reg [31:0] daddr;
    reg [31:0] dwdata;
    reg [3:0]  dwe;
    

    

    wire [3:0] alu_op_wire;
    wire mux1_sel_wire ;
    wire [1:0] mux2_sel_wire ;
    wire auipc_wire ;
    wire jal_wire ;
    wire [4:0] rs1_wire ;
    wire [4:0] rs2_wire ;
    wire [4:0] rd_wire ;
    wire [31:0] imm12_ext_wire ;
    wire l_unsign_flag_wire ;
    wire [3:0] dwe_wire ;
    wire [3:0] rf_we_wire ;
    wire is_branch_type_wire ;
    wire is_conditional_branch_type_wire ;
    wire [31:0] branch_condition_wire ;


    wire [31:0] rf_op1_wire ;
    wire [31:0] rf_op2_wire ;
    wire [31:0] rf_op3_wire ;


    wire [31:0] alu_out_wire ;


    wire [31:0] mux1_output_wire ;


    wire [31:0] mux2_output_wire ;


    wire [3:0] dwe_checked_wire;
    wire [3:0] rf_we_checked_wire ;
    wire [31:0] drdata_checked_wire ;
    wire [31:0] dwdata_checked_wire ;


    wire [31:0] pc_plus_4_wire ;


    wire [31:0] next_addr_branch_wire ;
    wire take_branch_wire ;


    wire [31:0] next_address_wire ;
    

    reg clkreset_flag ; 



    control CONT (
                   .reset(reset) ,
                   .idata(idata) ,
                   .clkreset_flag(clkreset_flag) ,
                   

                   .alu_op(alu_op_wire) ,
                   .mux1_sel(mux1_sel_wire) ,
                   .mux2_sel(mux2_sel_wire) ,
                   .auipc(auipc_wire) ,
                   .jal(jal_wire) ,
                   .rs1(rs1_wire) ,
                   .rs2(rs2_wire) ,
                   .rd(rd_wire) ,
                   .imm12_ext(imm12_ext_wire) ,
                   .dwe(dwe_wire) ,
                   .rf_we(rf_we_wire) ,
                   .l_unsign_flag(l_unsign_flag_wire) ,
                   .is_branch_type(is_branch_type_wire) ,
                   .is_conditional_branch_type(is_conditional_branch_type_wire) ,
                   .branch_condition(branch_condition_wire) );
    

    
    reg_file RF (
                  .reset(reset) ,
                  .clk(clk) ,
                  .clkreset_flag(clkreset_flag) ,
                  .rf_we(rf_we_checked_wire) ,
                  .rf_wdata(mux2_output_wire) , 
                  .rs1 (rs1_wire) ,
                  .rs2(rs2_wire) ,
                  .rd(rd_wire) ,
                  .imm12_ext(imm12_ext_wire) ,
                  .l_unsign_flag(l_unsign_flag_wire) ,
                  


                  .rf_op1(rf_op1_wire) , 
                  .rf_op2(rf_op2_wire) , 
                  .rf_op3(rf_op3_wire)  );



    alu ALU (
              .alu_op(alu_op_wire) ,
              .operand1(rf_op1_wire) , 
              .operand2(mux1_output_wire) , 
              

              .alu_out(alu_out_wire) ) ;



    mux MUX_ALU_input_select (
                               .mux_sel(mux1_sel_wire) ,
                               .input0(rf_op2_wire) ,
                               .input1(rf_op3_wire) ,
               

                               .mux_output(mux1_output_wire) );



    mux4input MUX_RFwrite (
                            .mux_sel(mux2_sel_wire) ,
                            .input0(alu_out_wire) ,
                            .input1(drdata_checked_wire) ,
                            .input2(pc_plus_4_wire) ,
                            .input3(next_addr_branch_wire) ,
               

                            .mux_out(mux2_output_wire) );



    check_misalign Dcheck (
                            .opcode(idata[6:0]) ,
                            .dwe(dwe_wire) ,
                            .daddr(alu_out_wire) ,
                            .rf_we(rf_we_wire) ,
                            .dwdata(rf_op2_wire) ,
                            .drdata(drdata) ,


                            .dwe_checked(dwe_checked_wire) ,
                            .rf_we_checked(rf_we_checked_wire) ,
                            .dwdata_checked(dwdata_checked_wire) ,
                            .drdata_checked(drdata_checked_wire) );






    pc_plus4 PC4 (
                   .input_iaddr(iaddr) ,
                   

                   .out_pc_plus4(pc_plus_4_wire) );




    branch_controller_ALU Bcontrol (
                                     .is_branch_type(is_branch_type_wire) ,
                                     .is_conditional_branch_type(is_conditional_branch_type_wire) ,
                                     .input_iaddr(iaddr) ,
                                     .alu_out(alu_out_wire) ,
                                     .branch_condition(branch_condition_wire) ,
                                     .input_imm12_ext(imm12_ext_wire) ,
                                     .auipc(auipc_wire) ,
                                     .jal(jal_wire) ,


                                     .next_addr_branch(next_addr_branch_wire) ,
                                     .take_branch(take_branch_wire) ) ;
    
    


    mux mux_branch (
                     .input0(pc_plus_4_wire) ,
                     .input1(next_addr_branch_wire) ,
                     .mux_sel(take_branch_wire) ,
                     

                     .mux_output(next_address_wire) );




    always @(*) begin
        daddr = alu_out_wire ;
        dwdata = {32{~reset}} & dwdata_checked_wire ;
        dwe = {4{~reset}} & dwe_checked_wire ; 
    end

    always @(posedge clk) begin
        if (reset) begin
            iaddr <= 0;
            clkreset_flag <= 1'b1 ;
        end 
        
        else if ( clkreset_flag ) begin
            clkreset_flag <= 1'b0 ;
            iaddr <= 0 ;
        end
         
        else begin 
            iaddr <= next_address_wire;
        end

    end
endmodule
module cpu (
    input clk, 
    input reset,
    input [31:0] idata,
    input [31:0] drdata,
    output [31:0] iaddr,
    output [31:0] daddr,
    output [31:0] dwdata,
    output [3:0] dwe
);

    reg [31:0] iaddr;
    reg [31:0] daddr;
    reg [31:0] dwdata;
    reg [3:0]  dwe;
    

    

    wire [3:0] alu_op_wire;
    wire mux1_sel_wire ;
    wire [1:0] mux2_sel_wire ;
    wire auipc_wire ;
    wire jal_wire ;
    wire [4:0] rs1_wire ;
    wire [4:0] rs2_wire ;
    wire [4:0] rd_wire ;
    wire [31:0] imm12_ext_wire ;
    wire l_unsign_flag_wire ;
    wire [3:0] dwe_wire ;
    wire [3:0] rf_we_wire ;
    wire is_branch_type_wire ;
    wire is_conditional_branch_type_wire ;
    wire [31:0] branch_condition_wire ;


    wire [31:0] rf_op1_wire ;
    wire [31:0] rf_op2_wire ;
    wire [31:0] rf_op3_wire ;


    wire [31:0] alu_out_wire ;


    wire [31:0] mux1_output_wire ;


    wire [31:0] mux2_output_wire ;


    wire [3:0] dwe_checked_wire;
    wire [3:0] rf_we_checked_wire ;
    wire [31:0] drdata_checked_wire ;
    wire [31:0] dwdata_checked_wire ;


    wire [31:0] pc_plus_4_wire ;


    wire [31:0] next_addr_branch_wire ;
    wire take_branch_wire ;


    wire [31:0] next_address_wire ;
    

    reg clkreset_flag ; 



    control CONT (
                   .reset(reset) ,
                   .idata(idata) ,
                   .clkreset_flag(clkreset_flag) ,
                   

                   .alu_op(alu_op_wire) ,
                   .mux1_sel(mux1_sel_wire) ,
                   .mux2_sel(mux2_sel_wire) ,
                   .auipc(auipc_wire) ,
                   .jal(jal_wire) ,
                   .rs1(rs1_wire) ,
                   .rs2(rs2_wire) ,
                   .rd(rd_wire) ,
                   .imm12_ext(imm12_ext_wire) ,
                   .dwe(dwe_wire) ,
                   .rf_we(rf_we_wire) ,
                   .l_unsign_flag(l_unsign_flag_wire) ,
                   .is_branch_type(is_branch_type_wire) ,
                   .is_conditional_branch_type(is_conditional_branch_type_wire) ,
                   .branch_condition(branch_condition_wire) );
    

    
    reg_file RF (
                  .reset(reset) ,
                  .clk(clk) ,
                  .clkreset_flag(clkreset_flag) ,
                  .rf_we(rf_we_checked_wire) ,
                  .rf_wdata(mux2_output_wire) , 
                  .rs1 (rs1_wire) ,
                  .rs2(rs2_wire) ,
                  .rd(rd_wire) ,
                  .imm12_ext(imm12_ext_wire) ,
                  .l_unsign_flag(l_unsign_flag_wire) ,
                  


                  .rf_op1(rf_op1_wire) , 
                  .rf_op2(rf_op2_wire) , 
                  .rf_op3(rf_op3_wire)  );



    alu ALU (
              .alu_op(alu_op_wire) ,
              .operand1(rf_op1_wire) , 
              .operand2(mux1_output_wire) , 
              

              .alu_out(alu_out_wire) ) ;



    mux MUX_ALU_input_select (
                               .mux_sel(mux1_sel_wire) ,
                               .input0(rf_op2_wire) ,
                               .input1(rf_op3_wire) ,
               

                               .mux_output(mux1_output_wire) );



    mux4input MUX_RFwrite (
                            .mux_sel(mux2_sel_wire) ,
                            .input0(alu_out_wire) ,
                            .input1(drdata_checked_wire) ,
                            .input2(pc_plus_4_wire) ,
                            .input3(next_addr_branch_wire) ,
               

                            .mux_out(mux2_output_wire) );



    check_misalign Dcheck (
                            .opcode(idata[6:0]) ,
                            .dwe(dwe_wire) ,
                            .daddr(alu_out_wire) ,
                            .rf_we(rf_we_wire) ,
                            .dwdata(rf_op2_wire) ,
                            .drdata(drdata) ,


                            .dwe_checked(dwe_checked_wire) ,
                            .rf_we_checked(rf_we_checked_wire) ,
                            .dwdata_checked(dwdata_checked_wire) ,
                            .drdata_checked(drdata_checked_wire) );






    pc_plus4 PC4 (
                   .input_iaddr(iaddr) ,
                   

                   .out_pc_plus4(pc_plus_4_wire) );




    branch_controller_ALU Bcontrol (
                                     .is_branch_type(is_branch_type_wire) ,
                                     .is_conditional_branch_type(is_conditional_branch_type_wire) ,
                                     .input_iaddr(iaddr) ,
                                     .alu_out(alu_out_wire) ,
                                     .branch_condition(branch_condition_wire) ,
                                     .input_imm12_ext(imm12_ext_wire) ,
                                     .auipc(auipc_wire) ,
                                     .jal(jal_wire) ,


                                     .next_addr_branch(next_addr_branch_wire) ,
                                     .take_branch(take_branch_wire) ) ;
    
    


    mux mux_branch (
                     .input0(pc_plus_4_wire) ,
                     .input1(next_addr_branch_wire) ,
                     .mux_sel(take_branch_wire) ,
                     

                     .mux_output(next_address_wire) );




    always @(*) begin
        daddr = alu_out_wire ;
        dwdata = {32{~reset}} & dwdata_checked_wire ;
        dwe = {4{~reset}} & dwe_checked_wire ; 
    end

    always @(posedge clk) begin
        if (reset) begin
            iaddr <= 0;
            clkreset_flag <= 1'b1 ;
        end 
        
        else if ( clkreset_flag ) begin
            clkreset_flag <= 1'b0 ;
            iaddr <= 0 ;
        end
         
        else begin 
            iaddr <= next_address_wire;
        end

    end
endmodule