data/full_repos/permissive/479997390/src/FullAdder32Bits.v
data/verilator_xmls/2371e7e6-6257-4ed9-bbf6-096a2072327e.xml
module FullAdder32Bits (
    a, b, Operation, Anegate, Bnegate, Signed, Carry, Result, Zero, Overflow
);
    input [31:0] a, b;
    input [1:0] Operation;
    input Anegate, Bnegate, Signed;
    input Carry;

    output [31:0] Result;
    output Overflow, Zero;

    wire [31:0] conn;
    wire set, realSet;

    assign Zero = ~(|Result);
    assign realSet = Signed ? (set ^ Overflow) : (((a[31]) & ~b[31]) | (~(a[31] ^ b[31]) & set));

    generate
        genvar i;
        for (i = 0; i < 32; i = i + 1) begin:loop_gen_block
            if (i == 0) begin
                oneBitALU obALU(
                    .a(a[i]),
                    .b(b[i]),
                    .carryIn(Anegate | Bnegate),
                    .carryOut(conn[i]),
                    .Operation(Operation),
                    .Ainvert(Anegate),
                    .Binvert(Bnegate),
                    .Less(realSet),
                    .Result(Result[i])
                );
            end else if (i < 31) begin
                oneBitALU obALU(
                    .a(a[i]),
                    .b(b[i]),
                    .carryIn(Carry ? conn[i - 1] : 1'b0),
                    .carryOut(conn[i]),
                    .Operation(Operation),
                    .Ainvert(Anegate),
                    .Binvert(Bnegate),
                    .Less(1'b0),
                    .Result(Result[i])
                );
            end else begin
                oneBitALUForMSB obALUForMSB(
                    .a(a[i]),
                    .b(b[i]),
                    .carryIn(Carry ? conn[i - 1] : 1'b0),
                    .Operation(Operation),
                    .Ainvert(Anegate),
                    .Binvert(Bnegate),
                    .Less(1'b0),
                    .Result(Result[i]),
                    .Set(set),
                    .Overflow(Overflow)
                );
            end
        end
    endgenerate
endmodule
module FullAdder32Bits (
    a, b, Operation, Anegate, Bnegate, Signed, Carry, Result, Zero, Overflow
);

    input [31:0] a, b;
    input [1:0] Operation;
    input Anegate, Bnegate, Signed;
    input Carry;

    output [31:0] Result;
    output Overflow, Zero;

    wire [31:0] conn;
    wire set, realSet;

    assign Zero = ~(|Result);
    assign realSet = Signed ? (set ^ Overflow) : (((a[31]) & ~b[31]) | (~(a[31] ^ b[31]) & set));

    generate
        genvar i;
        for (i = 0; i < 32; i = i + 1) begin:loop_gen_block
            if (i == 0) begin
                oneBitALU obALU(
                    .a(a[i]),
                    .b(b[i]),
                    .carryIn(Anegate | Bnegate),
                    .carryOut(conn[i]),
                    .Operation(Operation),
                    .Ainvert(Anegate),
                    .Binvert(Bnegate),
                    .Less(realSet),
                    .Result(Result[i])
                );
            end else if (i < 31) begin
                oneBitALU obALU(
                    .a(a[i]),
                    .b(b[i]),
                    .carryIn(Carry ? conn[i - 1] : 1'b0),
                    .carryOut(conn[i]),
                    .Operation(Operation),
                    .Ainvert(Anegate),
                    .Binvert(Bnegate),
                    .Less(1'b0),
                    .Result(Result[i])
                );
            end else begin
                oneBitALUForMSB obALUForMSB(
                    .a(a[i]),
                    .b(b[i]),
                    .carryIn(Carry ? conn[i - 1] : 1'b0),
                    .Operation(Operation),
                    .Ainvert(Anegate),
                    .Binvert(Bnegate),
                    .Less(1'b0),
                    .Result(Result[i]),
                    .Set(set),
                    .Overflow(Overflow)
                );
            end
        end
    endgenerate
endmodule