data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/ARCH_BENCHMARKS/spram_big.v
1: b'%Error: data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/ARCH_BENCHMARKS/spram_big.v:21: Cannot find file containing module: \'single_port_ram\'\nsingle_port_ram inst1(\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/ARCH_BENCHMARKS,data/full_repos/permissive/49670587/single_port_ram\n             data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/ARCH_BENCHMARKS,data/full_repos/permissive/49670587/single_port_ram.v\n             data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/ARCH_BENCHMARKS,data/full_repos/permissive/49670587/single_port_ram.sv\n             single_port_ram\n             single_port_ram.v\n             single_port_ram.sv\n             obj_dir/single_port_ram\n             obj_dir/single_port_ram.v\n             obj_dir/single_port_ram.sv\n%Warning-WIDTH: data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/ARCH_BENCHMARKS/spram_big.v:30: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                                                          : ... In instance spram_big\n  address_counter <= 4\'b00000000;\n                  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module  spram_big(clock,
                reset_n,
                value_out,
                value_in
                );


input   clock;
input   reset_n;
input [`WIDTH-1:0] value_in;
output [`WIDTH-1:0] value_out;
wire [`WIDTH-1:0] value_out;

reg [`DEPTH-1:0] address_counter;
reg [`WIDTH-1:0] temp;

single_port_ram inst1(
  .we(clock),
  .data(value_in),
  .out(value_out),
  .addr(address_counter));

always @(posedge clock)
begin
	if (reset_n == 1'b1) begin
		address_counter <= 4'b00000000;
	end
	else
	begin
		address_counter <= address_counter + 1;
	end
end

endmodule
module  spram_big(clock,
                reset_n,
                value_out,
                value_in
                );



input   clock;
input   reset_n;
input [`WIDTH-1:0] value_in;
output [`WIDTH-1:0] value_out;
wire [`WIDTH-1:0] value_out;

reg [`DEPTH-1:0] address_counter;
reg [`WIDTH-1:0] temp;

single_port_ram inst1(
  .we(clock),
  .data(value_in),
  .out(value_out),
  .addr(address_counter));

always @(posedge clock)
begin
	if (reset_n == 1'b1) begin
		address_counter <= 4'b00000000;
	end
	else
	begin
		address_counter <= address_counter + 1;
	end
end

endmodule