data/full_repos/permissive/489790801/src/compdata.v
data/verilator_xmls/5702ed27-8e63-4f8f-af36-5366ed04231c.xml
module compdata
    #(parameter P_WIDTH=32) (
        input   [P_WIDTH-1:0] a,b,
        output reg [P_WIDTH-1:0] dres,
        input [2-1:0] op);

    always @(op, a, b) begin
        case(op)
            2'b00: dres = (a >> 1);
            2'b01: dres = (a - b);
            default: dres = {P_WIDTH{1'bx}};
        endcase
    end
endmodule
module compdata
    #(parameter P_WIDTH=32) (
        input   [P_WIDTH-1:0] a,b,
        output reg [P_WIDTH-1:0] dres,
        input [2-1:0] op);


    always @(op, a, b) begin
        case(op)
            2'b00: dres = (a >> 1);
            2'b01: dres = (a - b);
            default: dres = {P_WIDTH{1'bx}};
        endcase
    end
endmodule