data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v
1: b'%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:89: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_A_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_A: next_state = go ? S_LOAD_A_WAIT : S_LOAD_A;  \n                                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:89: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'S_LOAD_A\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_A: next_state = go ? S_LOAD_A_WAIT : S_LOAD_A;  \n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:90: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_A_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_A_WAIT: next_state = go ? S_LOAD_A_WAIT : S_LOAD_B;  \n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:90: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'S_LOAD_B\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_A_WAIT: next_state = go ? S_LOAD_A_WAIT : S_LOAD_B;  \n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:91: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_B_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_B: next_state = go ? S_LOAD_B_WAIT : S_LOAD_B;  \n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:91: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'S_LOAD_B\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_B: next_state = go ? S_LOAD_B_WAIT : S_LOAD_B;  \n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:92: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_B_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_B_WAIT: next_state = go ? S_LOAD_B_WAIT : S_LOAD_C;  \n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:92: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'S_LOAD_C\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_B_WAIT: next_state = go ? S_LOAD_B_WAIT : S_LOAD_C;  \n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:93: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_C_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_C: next_state = go ? S_LOAD_C_WAIT : S_LOAD_C;  \n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:93: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'S_LOAD_C\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_C: next_state = go ? S_LOAD_C_WAIT : S_LOAD_C;  \n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:94: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_C_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_C_WAIT: next_state = go ? S_LOAD_C_WAIT : S_LOAD_X;  \n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:94: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'S_LOAD_X\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_C_WAIT: next_state = go ? S_LOAD_C_WAIT : S_LOAD_X;  \n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:95: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_X_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_X: next_state = go ? S_LOAD_X_WAIT : S_LOAD_X;  \n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:95: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'S_LOAD_X\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_X: next_state = go ? S_LOAD_X_WAIT : S_LOAD_X;  \n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:96: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_X_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_X_WAIT: next_state = go ? S_LOAD_X_WAIT : S_CYCLE_0;  \n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:96: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'S_CYCLE_0\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_X_WAIT: next_state = go ? S_LOAD_X_WAIT : S_CYCLE_0;  \n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:97: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_CYCLE_1\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_CYCLE_0: next_state = S_CYCLE_1;\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:98: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_CYCLE_2\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_CYCLE_1: next_state = S_CYCLE_2;  \n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:99: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_CYCLE_3\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n      S_CYCLE_2: next_state = S_CYCLE_3;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:100: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_LOAD_A\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n      S_CYCLE_3: next_state = S_LOAD_A;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:101: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_LOAD_A\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n            default:     next_state = S_LOAD_A;\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_A\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_A_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_B\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_B_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_C\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_C_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_X\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_X_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_CYCLE_0\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_CYCLE_1\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_CYCLE_2\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_CYCLE_3\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:120: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_A\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n        case (current_state)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:120: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_B\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n        case (current_state)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:120: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_C\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n        case (current_state)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:120: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_X\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n        case (current_state)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:120: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_CYCLE_0\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n        case (current_state)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:120: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_CYCLE_1\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n        case (current_state)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:120: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_CYCLE_2\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n        case (current_state)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:120: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_CYCLE_3\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n        case (current_state)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:168: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_LOAD_A\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n            current_state <= S_LOAD_A;\n                          ^~\n%Error: Exiting due to 42 warning(s)\n'
module datapath(
    input clk,
    input resetn,
    input [7:0] data_in,
    input ld_alu_out, 
    input ld_x, ld_a, ld_b, ld_c,
    input ld_r,
    input alu_op, 
    input [1:0] alu_select_a, alu_select_b,
    output reg [7:0] data_result
    );
    

    reg [7:0] a, b, c, x;


    reg [7:0] alu_out;

    reg [7:0] alu_a, alu_b;
    

    always@(posedge clk) begin
        if(!resetn) begin
            a <= 8'b0; 
            b <= 8'b0; 
            c <= 8'b0; 
            x <= 8'b0; 
        end
        else begin
            if(ld_a)
                a <= ld_alu_out ? alu_out : data_in;
            if(ld_b)
                b <= ld_alu_out ? alu_out : data_in;
            if(ld_x)
                x <= data_in;

            if(ld_c)
                c <= data_in;
        end
    end
 

    always@(posedge clk) begin
        if(!resetn) begin
            data_result <= 8'b0; 
        end
        else 
            if(ld_r)
                data_result <= alu_out;
    end


    always @(*)
    begin
        case (alu_select_a)
            2'd0:
                alu_a = a;
            2'd1:
                alu_a = b;
            2'd2:
                alu_a = c;
            2'd3:
                alu_a = x;
            default: alu_a = 8'b0;
        endcase

        case (alu_select_b)
            2'd0:
                alu_b = a;
            2'd1:
                alu_b = b;
            2'd2:
                alu_b = c;
            2'd3:
                alu_b = x;
            default: alu_b = 8'b0;
        endcase
    end


    always @(*)
    begin : ALU

        case (alu_op)
            0: begin
                   alu_out = alu_a + alu_b;
               end
            1: begin
                   alu_out = alu_a * alu_b;
               end
            default: alu_out = 8'b0;
        endcase
    end
    
endmodule
module datapath(
    input clk,
    input resetn,
    input [7:0] data_in,
    input ld_alu_out, 
    input ld_x, ld_a, ld_b, ld_c,
    input ld_r,
    input alu_op, 
    input [1:0] alu_select_a, alu_select_b,
    output reg [7:0] data_result
    );

    

    reg [7:0] a, b, c, x;


    reg [7:0] alu_out;

    reg [7:0] alu_a, alu_b;
    

    always@(posedge clk) begin
        if(!resetn) begin
            a <= 8'b0; 
            b <= 8'b0; 
            c <= 8'b0; 
            x <= 8'b0; 
        end
        else begin
            if(ld_a)
                a <= ld_alu_out ? alu_out : data_in;
            if(ld_b)
                b <= ld_alu_out ? alu_out : data_in;
            if(ld_x)
                x <= data_in;

            if(ld_c)
                c <= data_in;
        end
    end
 

    always@(posedge clk) begin
        if(!resetn) begin
            data_result <= 8'b0; 
        end
        else 
            if(ld_r)
                data_result <= alu_out;
    end


    always @(*)
    begin
        case (alu_select_a)
            2'd0:
                alu_a = a;
            2'd1:
                alu_a = b;
            2'd2:
                alu_a = c;
            2'd3:
                alu_a = x;
            default: alu_a = 8'b0;
        endcase

        case (alu_select_b)
            2'd0:
                alu_b = a;
            2'd1:
                alu_b = b;
            2'd2:
                alu_b = c;
            2'd3:
                alu_b = x;
            default: alu_b = 8'b0;
        endcase
    end


    always @(*)
    begin : ALU

        case (alu_op)
            0: begin
                   alu_out = alu_a + alu_b;
               end
            1: begin
                   alu_out = alu_a * alu_b;
               end
            default: alu_out = 8'b0;
        endcase
    end
    
endmodule