data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v
1: b'%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:5: Cannot find include file: fixedpt.vh\n`include "fixedpt.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/472196771/verilog/rtl/src,data/full_repos/permissive/472196771/fixedpt.vh\n             data/full_repos/permissive/472196771/verilog/rtl/src,data/full_repos/permissive/472196771/fixedpt.vh.v\n             data/full_repos/permissive/472196771/verilog/rtl/src,data/full_repos/permissive/472196771/fixedpt.vh.sv\n             fixedpt.vh\n             fixedpt.vh.v\n             fixedpt.vh.sv\n             obj_dir/fixedpt.vh\n             obj_dir/fixedpt.vh.v\n             obj_dir/fixedpt.vh.sv\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:13: Define or directive not defined: \'`FIXPT\'\n  input `FIXPT            i_w1,\n        ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:14: Define or directive not defined: \'`FIXPT\'\n  input `FIXPT            i_w2,\n        ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:15: Define or directive not defined: \'`FIXPT\'\n  input `FIXPT            i_w3,\n        ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:52: Define or directive not defined: \'`FIXPT\'\n  wire `FIXPT r_v1_value_fixpt;\n       ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:53: Define or directive not defined: \'`FIXPT\'\n  wire `FIXPT r_v2_value_fixpt;\n       ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:54: Define or directive not defined: \'`FIXPT\'\n  wire `FIXPT r_v3_value_fixpt;\n       ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:55: Define or directive not defined: \'`FIXPT\'\n  wire `FIXPT g_v1_value_fixpt;\n       ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:56: Define or directive not defined: \'`FIXPT\'\n  wire `FIXPT g_v2_value_fixpt;\n       ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:57: Define or directive not defined: \'`FIXPT\'\n  wire `FIXPT g_v3_value_fixpt;\n       ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:58: Define or directive not defined: \'`FIXPT\'\n  wire `FIXPT b_v1_value_fixpt;\n       ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:59: Define or directive not defined: \'`FIXPT\'\n  wire `FIXPT b_v2_value_fixpt;\n       ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:60: Define or directive not defined: \'`FIXPT\'\n  wire `FIXPT b_v3_value_fixpt;\n       ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:62: Define or directive not defined: \'`FIXPT_INT\'\n  Interpolator r_interp_v1(.i_a(`FIXPT_INT({ 14\'b0, i_v1_r })), .i_w(i_w1), .o_res(r_v1_value_fixpt));\n                                ^~~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:63: Define or directive not defined: \'`FIXPT_INT\'\n  Interpolator r_interp_v2(.i_a(`FIXPT_INT({ 14\'b0, i_v2_r })), .i_w(i_w2), .o_res(r_v2_value_fixpt));\n                                ^~~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:64: Define or directive not defined: \'`FIXPT_INT\'\n  Interpolator r_interp_v3(.i_a(`FIXPT_INT({ 14\'b0, i_v3_r })), .i_w(i_w3), .o_res(r_v3_value_fixpt));\n                                ^~~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:65: Define or directive not defined: \'`FIXPT_INT\'\n  Interpolator g_interp_v1(.i_a(`FIXPT_INT({ 14\'b0, i_v1_g })), .i_w(i_w1), .o_res(g_v1_value_fixpt));\n                                ^~~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:66: Define or directive not defined: \'`FIXPT_INT\'\n  Interpolator g_interp_v2(.i_a(`FIXPT_INT({ 14\'b0, i_v2_g })), .i_w(i_w2), .o_res(g_v2_value_fixpt));\n                                ^~~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:67: Define or directive not defined: \'`FIXPT_INT\'\n  Interpolator g_interp_v3(.i_a(`FIXPT_INT({ 14\'b0, i_v3_g })), .i_w(i_w3), .o_res(g_v3_value_fixpt));\n                                ^~~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:68: Define or directive not defined: \'`FIXPT_INT\'\n  Interpolator b_interp_v1(.i_a(`FIXPT_INT({ 14\'b0, i_v1_b })), .i_w(i_w1), .o_res(b_v1_value_fixpt));\n                                ^~~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:69: Define or directive not defined: \'`FIXPT_INT\'\n  Interpolator b_interp_v2(.i_a(`FIXPT_INT({ 14\'b0, i_v2_b })), .i_w(i_w2), .o_res(b_v2_value_fixpt));\n                                ^~~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:70: Define or directive not defined: \'`FIXPT_INT\'\n  Interpolator b_interp_v3(.i_a(`FIXPT_INT({ 14\'b0, i_v3_b })), .i_w(i_w3), .o_res(b_v3_value_fixpt));\n                                ^~~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:72: Define or directive not defined: \'`FIXPT\'\n  wire `FIXPT r_interp_fp = r_v1_value_fixpt + r_v2_value_fixpt + r_v3_value_fixpt;\n       ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:73: Define or directive not defined: \'`FIXPT\'\n  wire `FIXPT g_interp_fp = g_v1_value_fixpt + g_v2_value_fixpt + g_v3_value_fixpt;\n       ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:74: Define or directive not defined: \'`FIXPT\'\n  wire `FIXPT b_interp_fp = b_v1_value_fixpt + b_v2_value_fixpt + b_v3_value_fixpt;\n       ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:83: Define or directive not defined: \'`SATURATE\'\n      o_r           <= `SATURATE(8\'d0, 8\'d255, `FIXPT_TO_INT(r_interp_fp));\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:83: syntax error, unexpected \',\'\n      o_r           <= `SATURATE(8\'d0, 8\'d255, `FIXPT_TO_INT(r_interp_fp));\n                                     ^\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:83: Define or directive not defined: \'`FIXPT_TO_INT\'\n      o_r           <= `SATURATE(8\'d0, 8\'d255, `FIXPT_TO_INT(r_interp_fp));\n                                               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:84: Define or directive not defined: \'`SATURATE\'\n      o_g           <= `SATURATE(8\'d0, 8\'d255, `FIXPT_TO_INT(g_interp_fp));\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:84: syntax error, unexpected \',\'\n      o_g           <= `SATURATE(8\'d0, 8\'d255, `FIXPT_TO_INT(g_interp_fp));\n                                     ^\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:84: Define or directive not defined: \'`FIXPT_TO_INT\'\n      o_g           <= `SATURATE(8\'d0, 8\'d255, `FIXPT_TO_INT(g_interp_fp));\n                                               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:85: Define or directive not defined: \'`SATURATE\'\n      o_b           <= `SATURATE(8\'d0, 8\'d255, `FIXPT_TO_INT(b_interp_fp));\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:85: syntax error, unexpected \',\'\n      o_b           <= `SATURATE(8\'d0, 8\'d255, `FIXPT_TO_INT(b_interp_fp));\n                                     ^\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:85: Define or directive not defined: \'`FIXPT_TO_INT\'\n      o_b           <= `SATURATE(8\'d0, 8\'d255, `FIXPT_TO_INT(b_interp_fp));\n                                               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:119: Define or directive not defined: \'`FIXPT\'\n  input  `FIXPT   i_a,\n         ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:120: Define or directive not defined: \'`FIXPT\'\n  input  `FIXPT   i_w,\n         ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:121: Define or directive not defined: \'`FIXPT\'\n  output `FIXPT   o_res\n         ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:123: Define or directive not defined: \'`FIXPT_MUL\'\n  assign o_res = `FIXPT_MUL(i_a, i_w);\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex2.v:123: syntax error, unexpected \',\'\n  assign o_res = `FIXPT_MUL(i_a, i_w);\n                               ^\n%Error: Exiting due to 39 error(s)\n'
module RasterPipelineEX2(
  input                   i_clk,
  input                   i_write_enable,
  input signed [15:0]     i_x_pos,
  input signed [15:0]     i_y_pos,
  input `FIXPT            i_w1,
  input `FIXPT            i_w2,
  input `FIXPT            i_w3,








  input [7:0]             i_v1_r,
  input [7:0]             i_v1_g,
  input [7:0]             i_v1_b,
  input [7:0]             i_v2_r,
  input [7:0]             i_v2_g,
  input [7:0]             i_v2_b,
  input [7:0]             i_v3_r,
  input [7:0]             i_v3_g,
  input [7:0]             i_v3_b,

  output reg              o_write_pixel,
  output reg signed[15:0] o_x,
  output reg signed[15:0] o_y,
  output reg [7:0]        o_r,
  output reg [7:0]        o_g,
  output reg [7:0]        o_b










);

  wire `FIXPT r_v1_value_fixpt;
  wire `FIXPT r_v2_value_fixpt;
  wire `FIXPT r_v3_value_fixpt;
  wire `FIXPT g_v1_value_fixpt;
  wire `FIXPT g_v2_value_fixpt;
  wire `FIXPT g_v3_value_fixpt;
  wire `FIXPT b_v1_value_fixpt;
  wire `FIXPT b_v2_value_fixpt;
  wire `FIXPT b_v3_value_fixpt;

  Interpolator r_interp_v1(.i_a(`FIXPT_INT({ 14'b0, i_v1_r })), .i_w(i_w1), .o_res(r_v1_value_fixpt));
  Interpolator r_interp_v2(.i_a(`FIXPT_INT({ 14'b0, i_v2_r })), .i_w(i_w2), .o_res(r_v2_value_fixpt));
  Interpolator r_interp_v3(.i_a(`FIXPT_INT({ 14'b0, i_v3_r })), .i_w(i_w3), .o_res(r_v3_value_fixpt));
  Interpolator g_interp_v1(.i_a(`FIXPT_INT({ 14'b0, i_v1_g })), .i_w(i_w1), .o_res(g_v1_value_fixpt));
  Interpolator g_interp_v2(.i_a(`FIXPT_INT({ 14'b0, i_v2_g })), .i_w(i_w2), .o_res(g_v2_value_fixpt));
  Interpolator g_interp_v3(.i_a(`FIXPT_INT({ 14'b0, i_v3_g })), .i_w(i_w3), .o_res(g_v3_value_fixpt));
  Interpolator b_interp_v1(.i_a(`FIXPT_INT({ 14'b0, i_v1_b })), .i_w(i_w1), .o_res(b_v1_value_fixpt));
  Interpolator b_interp_v2(.i_a(`FIXPT_INT({ 14'b0, i_v2_b })), .i_w(i_w2), .o_res(b_v2_value_fixpt));
  Interpolator b_interp_v3(.i_a(`FIXPT_INT({ 14'b0, i_v3_b })), .i_w(i_w3), .o_res(b_v3_value_fixpt));

  wire `FIXPT r_interp_fp = r_v1_value_fixpt + r_v2_value_fixpt + r_v3_value_fixpt;
  wire `FIXPT g_interp_fp = g_v1_value_fixpt + g_v2_value_fixpt + g_v3_value_fixpt;
  wire `FIXPT b_interp_fp = b_v1_value_fixpt + b_v2_value_fixpt + b_v3_value_fixpt;

  always @(posedge i_clk)
  begin
    if (i_write_enable)
    begin
      o_write_pixel <= 1;
      o_x           <= i_x_pos;
      o_y           <= i_y_pos;
      o_r           <= `SATURATE(8'd0, 8'd255, `FIXPT_TO_INT(r_interp_fp));
      o_g           <= `SATURATE(8'd0, 8'd255, `FIXPT_TO_INT(g_interp_fp));
      o_b           <= `SATURATE(8'd0, 8'd255, `FIXPT_TO_INT(b_interp_fp));









    end
    else begin
      o_write_pixel <= 0;
      o_x <= 32'bx;   
      o_y <= 32'bx;   
      o_r <= 32'bx;   
      o_g <= 32'bx;   
      o_b <= 32'bx;   









    end
  end

endmodule
module RasterPipelineEX2(
  input                   i_clk,
  input                   i_write_enable,
  input signed [15:0]     i_x_pos,
  input signed [15:0]     i_y_pos,
  input `FIXPT            i_w1,
  input `FIXPT            i_w2,
  input `FIXPT            i_w3,








  input [7:0]             i_v1_r,
  input [7:0]             i_v1_g,
  input [7:0]             i_v1_b,
  input [7:0]             i_v2_r,
  input [7:0]             i_v2_g,
  input [7:0]             i_v2_b,
  input [7:0]             i_v3_r,
  input [7:0]             i_v3_g,
  input [7:0]             i_v3_b,

  output reg              o_write_pixel,
  output reg signed[15:0] o_x,
  output reg signed[15:0] o_y,
  output reg [7:0]        o_r,
  output reg [7:0]        o_g,
  output reg [7:0]        o_b










);


  wire `FIXPT r_v1_value_fixpt;
  wire `FIXPT r_v2_value_fixpt;
  wire `FIXPT r_v3_value_fixpt;
  wire `FIXPT g_v1_value_fixpt;
  wire `FIXPT g_v2_value_fixpt;
  wire `FIXPT g_v3_value_fixpt;
  wire `FIXPT b_v1_value_fixpt;
  wire `FIXPT b_v2_value_fixpt;
  wire `FIXPT b_v3_value_fixpt;

  Interpolator r_interp_v1(.i_a(`FIXPT_INT({ 14'b0, i_v1_r })), .i_w(i_w1), .o_res(r_v1_value_fixpt));
  Interpolator r_interp_v2(.i_a(`FIXPT_INT({ 14'b0, i_v2_r })), .i_w(i_w2), .o_res(r_v2_value_fixpt));
  Interpolator r_interp_v3(.i_a(`FIXPT_INT({ 14'b0, i_v3_r })), .i_w(i_w3), .o_res(r_v3_value_fixpt));
  Interpolator g_interp_v1(.i_a(`FIXPT_INT({ 14'b0, i_v1_g })), .i_w(i_w1), .o_res(g_v1_value_fixpt));
  Interpolator g_interp_v2(.i_a(`FIXPT_INT({ 14'b0, i_v2_g })), .i_w(i_w2), .o_res(g_v2_value_fixpt));
  Interpolator g_interp_v3(.i_a(`FIXPT_INT({ 14'b0, i_v3_g })), .i_w(i_w3), .o_res(g_v3_value_fixpt));
  Interpolator b_interp_v1(.i_a(`FIXPT_INT({ 14'b0, i_v1_b })), .i_w(i_w1), .o_res(b_v1_value_fixpt));
  Interpolator b_interp_v2(.i_a(`FIXPT_INT({ 14'b0, i_v2_b })), .i_w(i_w2), .o_res(b_v2_value_fixpt));
  Interpolator b_interp_v3(.i_a(`FIXPT_INT({ 14'b0, i_v3_b })), .i_w(i_w3), .o_res(b_v3_value_fixpt));

  wire `FIXPT r_interp_fp = r_v1_value_fixpt + r_v2_value_fixpt + r_v3_value_fixpt;
  wire `FIXPT g_interp_fp = g_v1_value_fixpt + g_v2_value_fixpt + g_v3_value_fixpt;
  wire `FIXPT b_interp_fp = b_v1_value_fixpt + b_v2_value_fixpt + b_v3_value_fixpt;

  always @(posedge i_clk)
  begin
    if (i_write_enable)
    begin
      o_write_pixel <= 1;
      o_x           <= i_x_pos;
      o_y           <= i_y_pos;
      o_r           <= `SATURATE(8'd0, 8'd255, `FIXPT_TO_INT(r_interp_fp));
      o_g           <= `SATURATE(8'd0, 8'd255, `FIXPT_TO_INT(g_interp_fp));
      o_b           <= `SATURATE(8'd0, 8'd255, `FIXPT_TO_INT(b_interp_fp));









    end
    else begin
      o_write_pixel <= 0;
      o_x <= 32'bx;   
      o_y <= 32'bx;   
      o_r <= 32'bx;   
      o_g <= 32'bx;   
      o_b <= 32'bx;   









    end
  end

endmodule