data/full_repos/permissive/484553918/rtl/CPU_Rom.sv
data/verilator_xmls/8ac3c19b-3a3c-4fdd-96b0-c2cc16848a62.xml
module CPU_Rom(
    input clk_i,
    input [(addr_width-1):0] addr_i,

    output reg [(data_width-1):0] q_o
);

    parameter data_width = 32;
    parameter addr_width = 10;

    reg [data_width-1:0] rom[2**addr_width-1:0];
    initial
    begin
        `ifdef SYNTHESIS
        $readmemh("build/boot_syn.vh", rom);

        `else
        $readmemh("firmware/build/boot.vh", rom);
        `endif
    end

    always @ (posedge clk_i)
    begin
        q_o <= rom[addr_i];
    end
endmodule
module CPU_Rom(
    input clk_i,
    input [(addr_width-1):0] addr_i,

    output reg [(data_width-1):0] q_o
);


    parameter data_width = 32;
    parameter addr_width = 10;

    reg [data_width-1:0] rom[2**addr_width-1:0];
    initial
    begin
        `ifdef SYNTHESIS
        $readmemh("build/boot_syn.vh", rom);

        `else
        $readmemh("firmware/build/boot.vh", rom);
        `endif
    end

    always @ (posedge clk_i)
    begin
        q_o <= rom[addr_i];
    end
endmodule