data/full_repos/permissive/491934675/ECE251/instruction/ram.v
data/verilator_xmls/0a76d23b-9a49-4970-9e62-c743e5c6974e.xml
module ram(
    input [7:0] addr, datain,
    input we, clk,
    output wire [7:0] data
);

reg [7:0] ram [255:0];
reg [7:0] test;
initial begin
    ram[0] = 0;
    test = ram[addr];
end

always @(posedge clk ) begin
    if(we) begin
        ram[addr] = datain;
    end
end

assign data = ram[addr];


endmodule
module ram(
    input [7:0] addr, datain,
    input we, clk,
    output wire [7:0] data
);


reg [7:0] ram [255:0];
reg [7:0] test;
initial begin
    ram[0] = 0;
    test = ram[addr];
end

always @(posedge clk ) begin
    if(we) begin
        ram[addr] = datain;
    end
end

assign data = ram[addr];


endmodule