data/full_repos/permissive/494148647/src/util/reset_synchronizer.v
data/verilator_xmls/7491443d-ca70-48c4-a78e-58a9516addf7.xml
module reset_synchronizer #(
    parameter DELAY = 4
    ) (
    input clk,
    input rst_in,
    output rst_out
    );

    wire [DELAY-1:0] d;
    reg  [DELAY-1:0] q = {DELAY{1'b1}};

    assign rst_out = q[DELAY-1];

    assign d = {q[DELAY-2:0], 1'b0};

    always @(posedge clk)
        if (rst_in)
            q <= #1 {DELAY{1'b1}};
        else
            q <= #1 d;

endmodule
module reset_synchronizer #(
    parameter DELAY = 4
    ) (
    input clk,
    input rst_in,
    output rst_out
    );


    wire [DELAY-1:0] d;
    reg  [DELAY-1:0] q = {DELAY{1'b1}};

    assign rst_out = q[DELAY-1];

    assign d = {q[DELAY-2:0], 1'b0};

    always @(posedge clk)
        if (rst_in)
            q <= #1 {DELAY{1'b1}};
        else
            q <= #1 d;

endmodule