data/full_repos/permissive/509335294/processor_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/509335294/processor_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/509335294/processor_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n #2 rst = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/509335294/processor_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = ~clk;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/509335294/processor_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n%Error: data/full_repos/permissive/509335294/processor_tb.v:37: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("output.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/509335294/processor_tb.v:38: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0);\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module processor_tb;
	reg clk, rst;
	wire[12:0] current_instr;
	integer i; 
	
processor processor(clk,rst,current_instr);

initial begin
	clk 	= 0;
	rst 	= 0;
	
	#20
	$display("The final result of $s3 in memory is: %d", processor.regmem.registry[4]); 
	$finish;
end

initial begin
	#2 rst = 1;
end

always begin
	#1 clk = ~clk;
end

always begin
	#2
	$write("ID:8107 at time: %tns PC= %d RF[0 1 2 3 4 7] is: ", $time, current_instr);
	$display("");
	for(i=0;i<7;i=i+1)
		$write("%d=%b, ",i,processor.regmem.registry[i]);
	$display("");
end


initial begin
    $dumpfile("output.vcd");
	$dumpvars(0);
end

endmodule
module processor_tb;

	reg clk, rst;
	wire[12:0] current_instr;
	integer i; 
	
processor processor(clk,rst,current_instr);

initial begin
	clk 	= 0;
	rst 	= 0;
	
	#20
	$display("The final result of $s3 in memory is: %d", processor.regmem.registry[4]); 
	$finish;
end

initial begin
	#2 rst = 1;
end

always begin
	#1 clk = ~clk;
end

always begin
	#2
	$write("ID:8107 at time: %tns PC= %d RF[0 1 2 3 4 7] is: ", $time, current_instr);
	$display("");
	for(i=0;i<7;i=i+1)
		$write("%d=%b, ",i,processor.regmem.registry[i]);
	$display("");
end


initial begin
    $dumpfile("output.vcd");
	$dumpvars(0);
end

endmodule