data/full_repos/permissive/492007370/YODA_MinMax/YODA_MinMax.srcs/sim_1/new/testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/492007370/YODA_MinMax/YODA_MinMax.srcs/sim_1/new/testbench.v:53: Unsupported: Ignoring delay on this delayed statement.\nalways #clockRate clk = ~clk;  \n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/492007370/YODA_MinMax/YODA_MinMax.srcs/sim_1/new/testbench.v:34: Cannot find file containing module: \'sine_gen\'\n    sine_gen baseSineGen(.clk (clk), .sineOutput (sine));\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/492007370/YODA_MinMax/YODA_MinMax.srcs/sim_1/new,data/full_repos/permissive/492007370/sine_gen\n             data/full_repos/permissive/492007370/YODA_MinMax/YODA_MinMax.srcs/sim_1/new,data/full_repos/permissive/492007370/sine_gen.v\n             data/full_repos/permissive/492007370/YODA_MinMax/YODA_MinMax.srcs/sim_1/new,data/full_repos/permissive/492007370/sine_gen.sv\n             sine_gen\n             sine_gen.v\n             sine_gen.sv\n             obj_dir/sine_gen\n             obj_dir/sine_gen.v\n             obj_dir/sine_gen.sv\n%Error: data/full_repos/permissive/492007370/YODA_MinMax/YODA_MinMax.srcs/sim_1/new/testbench.v:36: Cannot find file containing module: \'Section2\'\n    Section2 section2 (.clk(clk), .interval(interval), .sample(sine), .min(Min_Output), .max(Max_Output));\n    ^~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
    reg clk;
    reg Enable;
    wire [15:0] sine;
    wire [15:0] Min_Output;
    wire [15:0] Max_Output;
    wire [15:0] N;
    reg [15:0] interval;
    
    

    sine_gen baseSineGen(.clk (clk), .sineOutput (sine));

    Section2 section2 (.clk(clk), .interval(interval), .sample(sine), .min(Min_Output), .max(Max_Output));


    

    parameter frequency = 48000;
    parameter SIZE = 1024; 
    parameter clockRate = 0.2;
    

initial
begin 
    Enable = 1;
    clk = 1'b0;
    interval = 2;
end

always #clockRate clk = ~clk;

endmodule
module testbench;

    reg clk;
    reg Enable;
    wire [15:0] sine;
    wire [15:0] Min_Output;
    wire [15:0] Max_Output;
    wire [15:0] N;
    reg [15:0] interval;
    
    

    sine_gen baseSineGen(.clk (clk), .sineOutput (sine));

    Section2 section2 (.clk(clk), .interval(interval), .sample(sine), .min(Min_Output), .max(Max_Output));


    

    parameter frequency = 48000;
    parameter SIZE = 1024; 
    parameter clockRate = 0.2;
    

initial
begin 
    Enable = 1;
    clk = 1'b0;
    interval = 2;
end

always #clockRate clk = ~clk;

endmodule