data/full_repos/permissive/411457613/Pyverilog/verilogcode/case_in_func.v
1: b"%Error: data/full_repos/permissive/411457613/Pyverilog/verilogcode/case_in_func.v:3: syntax error, unexpected bit, expecting IDENTIFIER or '=' or do or final\n  reg bit;\n      ^~~\n%Error: data/full_repos/permissive/411457613/Pyverilog/verilogcode/case_in_func.v:7: syntax error, unexpected <=, expecting IDENTIFIER or '=' or do or final\n      bit <= func1(IN1,SEL);\n          ^~\n%Error: Exiting due to 2 error(s)\n"
module TOP(IN1,SEL);
  input IN1,SEL;
  reg bit;


  always @* begin
      bit <= func1(IN1,SEL);
  end

  function func1;
    input in1;
    input sel;
    case(sel)
        'h0:
          func1 = in1;
        default:
          func1 = 1'b0;
    endcase
  endfunction



endmodule
module TOP(IN1,SEL);

  input IN1,SEL;
  reg bit;


  always @* begin
      bit <= func1(IN1,SEL);
  end

  function func1;
    input in1;
    input sel;
    case(sel)
        'h0:
          func1 = in1;
        default:
          func1 = 1'b0;
    endcase
  endfunction



endmodule