data/full_repos/permissive/419677538/Exercise_2/verilog_code/DigSysExe2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/419677538/Exercise_2/verilog_code/DigSysExe2.v:34: Unsupported: Ignoring delay on this delayed statement.\n      #10 x<=x+1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Exercise_2/verilog_code/DigSysExe2.v:78: Unsupported: Ignoring delay on this delayed statement.\n      #10 x<=x+1;\n      ^\n%Warning-MULTITOP: data/full_repos/permissive/419677538/Exercise_2/verilog_code/DigSysExe2.v:71: Multiple top level modules\n                                                                                               : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                               : ... Top module \'testbenchDecoder4to16\'\nmodule testbenchDecoder4to16;\n       ^~~~~~~~~~~~~~~~~~~~~\n                                                                                               : ... Top module \'testbenchSqr\'\nmodule testbenchSqr;\n       ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/419677538/Exercise_2/verilog_code/DigSysExe2.v:32: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                            : ... In instance testbenchDecoder4to16\n      x=1\'b0;\n       ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sqr(in,d);
   input [3:0] in;
   output [7:0] d;
   wire notx,noty,notz,notw,v1,v2,v3,v4,v5,v6,v7,v8;
   not(notx,in[3]);
   not(noty,in[2]);
   not(notz,in[1]);
   not(notw,in[0]);

   and(d[7],in[3],in[2]);

   or(v1,noty,in[1]);
   and(d[6],in[3],v1);

   and(v2,notx,in[2],in[1]);
   and(v3,in[3],in[2],in[0]);
   and(v4,in[3],noty,in[1]);
   or(d[5],v2,v3,v4);

   and(v5,notx,in[2],in[0]);
   and(v6,in[2],notz,notw);
   and(v7,in[3],noty,in[0]);
   or(d[4],v5,v6,v7);

   xor(v8,in[1],in[2]);
   and(d[3],in[0],v8);

   and(d[2],notw,in[1]);

   buf(d[1],1'b0);

   buf(d[0],in[0]);
endmodule
module sqr(in,d);

   input [3:0] in;
   output [7:0] d;
   wire notx,noty,notz,notw,v1,v2,v3,v4,v5,v6,v7,v8;
   not(notx,in[3]);
   not(noty,in[2]);
   not(notz,in[1]);
   not(notw,in[0]);

   and(d[7],in[3],in[2]);

   or(v1,noty,in[1]);
   and(d[6],in[3],v1);

   and(v2,notx,in[2],in[1]);
   and(v3,in[3],in[2],in[0]);
   and(v4,in[3],noty,in[1]);
   or(d[5],v2,v3,v4);

   and(v5,notx,in[2],in[0]);
   and(v6,in[2],notz,notw);
   and(v7,in[3],noty,in[0]);
   or(d[4],v5,v6,v7);

   xor(v8,in[1],in[2]);
   and(d[3],in[0],v8);

   and(d[2],notw,in[1]);

   buf(d[1],1'b0);

   buf(d[0],in[0]);
endmodule