data/full_repos/permissive/415103295/verilog/dv/fwvexrisc_rv32im_i4k_d4k_wb/fwvexrisc_rv32im_i4k_d4k_wb_tb.sv
1: b'%Error: data/full_repos/permissive/415103295/verilog/dv/fwvexrisc_rv32im_i4k_d4k_wb/fwvexrisc_rv32im_i4k_d4k_wb_tb.sv:8: Cannot find include file: wishbone_macros.svh\n`include "wishbone_macros.svh" \n         ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/415103295/verilog/dv/fwvexrisc_rv32im_i4k_d4k_wb,data/full_repos/permissive/415103295/wishbone_macros.svh\n             data/full_repos/permissive/415103295/verilog/dv/fwvexrisc_rv32im_i4k_d4k_wb,data/full_repos/permissive/415103295/wishbone_macros.svh.v\n             data/full_repos/permissive/415103295/verilog/dv/fwvexrisc_rv32im_i4k_d4k_wb,data/full_repos/permissive/415103295/wishbone_macros.svh.sv\n             wishbone_macros.svh\n             wishbone_macros.svh.v\n             wishbone_macros.svh.sv\n             obj_dir/wishbone_macros.svh\n             obj_dir/wishbone_macros.svh.v\n             obj_dir/wishbone_macros.svh.sv\n%Error: data/full_repos/permissive/415103295/verilog/dv/fwvexrisc_rv32im_i4k_d4k_wb/fwvexrisc_rv32im_i4k_d4k_wb_tb.sv:9: Cannot find include file: generic_sram_byte_en_macros.svh\n`include "generic_sram_byte_en_macros.svh" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/415103295/verilog/dv/fwvexrisc_rv32im_i4k_d4k_wb/fwvexrisc_rv32im_i4k_d4k_wb_tb.sv:53: Define or directive not defined: \'`WB_WIRES\'\n `WB_WIRES(c2i_, 32, 32);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/415103295/verilog/dv/fwvexrisc_rv32im_i4k_d4k_wb/fwvexrisc_rv32im_i4k_d4k_wb_tb.sv:53: syntax error, unexpected \'(\'\n `WB_WIRES(c2i_, 32, 32);\n           ^~~~\n%Error: data/full_repos/permissive/415103295/verilog/dv/fwvexrisc_rv32im_i4k_d4k_wb/fwvexrisc_rv32im_i4k_d4k_wb_tb.sv:60: Define or directive not defined: \'`WB_CONNECT\'\n  `WB_CONNECT(i_, c2i_),\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/415103295/verilog/dv/fwvexrisc_rv32im_i4k_d4k_wb/fwvexrisc_rv32im_i4k_d4k_wb_tb.sv:60: syntax error, unexpected \',\'\n  `WB_CONNECT(i_, c2i_),\n                ^\n%Error: data/full_repos/permissive/415103295/verilog/dv/fwvexrisc_rv32im_i4k_d4k_wb/fwvexrisc_rv32im_i4k_d4k_wb_tb.sv:63: Define or directive not defined: \'`GENERIC_SRAM_BYTE_EN_WIRES\'\n `GENERIC_SRAM_BYTE_EN_WIRES(sram_, 20, 32);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/415103295/verilog/dv/fwvexrisc_rv32im_i4k_d4k_wb/fwvexrisc_rv32im_i4k_d4k_wb_tb.sv:71: Define or directive not defined: \'`WB_CONNECT\'\n  `WB_CONNECT(t_, c2i_),\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/415103295/verilog/dv/fwvexrisc_rv32im_i4k_d4k_wb/fwvexrisc_rv32im_i4k_d4k_wb_tb.sv:71: syntax error, unexpected \',\'\n  `WB_CONNECT(t_, c2i_),\n                ^\n%Error: data/full_repos/permissive/415103295/verilog/dv/fwvexrisc_rv32im_i4k_d4k_wb/fwvexrisc_rv32im_i4k_d4k_wb_tb.sv:72: Define or directive not defined: \'`GENERIC_SRAM_BYTE_EN_CONNECT\'\n  `GENERIC_SRAM_BYTE_EN_CONNECT(i_, sram_)\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 10 error(s)\n'
module fwvexrisc_rv32im_i4k_d4k_wb_tb(input clock);
	
`ifdef HAVE_HDL_CLOCKGEN
	reg clock_r = 0;
	
	initial begin
		forever begin
`ifdef NEED_TIMESCALE
			#10;
`else
			#10ns;
`endif
			clock_r <= ~clock_r;
		end
	end
	assign clock = clock_r;
`endif
	
`ifdef IVERILOG
	`include "iverilog_control.svh"
`endif
	
	reg 		reset = 0;
	reg[5:0]	reset_cnt = 6'b0;
	
	always @(posedge clock) begin
		if (reset_cnt == 16) begin
			reset <= 1'b0;
		end else begin
			if (reset_cnt == 2) begin
				reset <= 1'b1;
			end
			reset_cnt <= reset_cnt + 1;
		end
	end

	`WB_WIRES(c2i_, 32, 32);

	wire irq;
	
	fwvexrisc_rv32im_i4k_d4k_wb u_dut (
		.clock    (clock   ), 
		.reset    (reset   ), 
		`WB_CONNECT(i_, c2i_),
		.irq      (irq     ));
	
	`GENERIC_SRAM_BYTE_EN_WIRES(sram_, 20, 32);
	
	fw_wishbone_sram_ctrl_single #(
		.ADR_WIDTH     (20    ), 
		.DAT_WIDTH     (32    )
		) fw_wishbone_sram_ctrl_single (
		.clock         (clock        ), 
		.reset         (reset        ), 
		`WB_CONNECT(t_, c2i_),
		`GENERIC_SRAM_BYTE_EN_CONNECT(i_, sram_)
		);
	
	generic_sram_byte_en_target_bfm #(
		.DAT_WIDTH  (32 ), 
		.ADR_WIDTH  (20 )
		) u_sram (
		.clock      (clock               ), 
		.adr        (sram_addr           ), 
		.we         (sram_write_en       ), 
		.sel        (sram_byte_en        ), 
		.dat_r      (sram_read_data      ), 
		.dat_w      (sram_write_data     ));

endmodule
module fwvexrisc_rv32im_i4k_d4k_wb_tb(input clock);

	
`ifdef HAVE_HDL_CLOCKGEN
	reg clock_r = 0;
	
	initial begin
		forever begin
`ifdef NEED_TIMESCALE
			#10;
`else
			#10ns;
`endif
			clock_r <= ~clock_r;
		end
	end
	assign clock = clock_r;
`endif
	
`ifdef IVERILOG
	`include "iverilog_control.svh"
`endif
	
	reg 		reset = 0;
	reg[5:0]	reset_cnt = 6'b0;
	
	always @(posedge clock) begin
		if (reset_cnt == 16) begin
			reset <= 1'b0;
		end else begin
			if (reset_cnt == 2) begin
				reset <= 1'b1;
			end
			reset_cnt <= reset_cnt + 1;
		end
	end

	`WB_WIRES(c2i_, 32, 32);

	wire irq;
	
	fwvexrisc_rv32im_i4k_d4k_wb u_dut (
		.clock    (clock   ), 
		.reset    (reset   ), 
		`WB_CONNECT(i_, c2i_),
		.irq      (irq     ));
	
	`GENERIC_SRAM_BYTE_EN_WIRES(sram_, 20, 32);
	
	fw_wishbone_sram_ctrl_single #(
		.ADR_WIDTH     (20    ), 
		.DAT_WIDTH     (32    )
		) fw_wishbone_sram_ctrl_single (
		.clock         (clock        ), 
		.reset         (reset        ), 
		`WB_CONNECT(t_, c2i_),
		`GENERIC_SRAM_BYTE_EN_CONNECT(i_, sram_)
		);
	
	generic_sram_byte_en_target_bfm #(
		.DAT_WIDTH  (32 ), 
		.ADR_WIDTH  (20 )
		) u_sram (
		.clock      (clock               ), 
		.adr        (sram_addr           ), 
		.we         (sram_write_en       ), 
		.sel        (sram_byte_en        ), 
		.dat_r      (sram_read_data      ), 
		.dat_w      (sram_write_data     ));

endmodule