data/full_repos/permissive/431682734/LabL/LabL11.v
1: b'%Error: data/full_repos/permissive/431682734/LabL/LabL11.v:3: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n    reg [31:0] expect;\n               ^~~~~~\n%Error: data/full_repos/permissive/431682734/LabL/LabL11.v:3: syntax error, unexpected \';\', expecting IDENTIFIER or \'=\' or do or final\n    reg [31:0] expect;\n                     ^\n%Error: data/full_repos/permissive/431682734/LabL/LabL11.v:32: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n                    expect[i] = a[i] & b[i];\n                    ^~~~~~\n%Error: data/full_repos/permissive/431682734/LabL/LabL11.v:32: syntax error, unexpected \'[\'\n                    expect[i] = a[i] & b[i];\n                          ^\n%Error: data/full_repos/permissive/431682734/LabL/LabL11.v:40: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n                    expect[i] = a[i] | b[i];\n                    ^~~~~~\n%Error: data/full_repos/permissive/431682734/LabL/LabL11.v:40: syntax error, unexpected \'[\'\n                    expect[i] = a[i] | b[i];\n                          ^\n%Error: data/full_repos/permissive/431682734/LabL/LabL11.v:46: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n                expect = a + b;\n                ^~~~~~\n%Error: data/full_repos/permissive/431682734/LabL/LabL11.v:46: syntax error, unexpected \'=\'\n                expect = a + b;\n                       ^\n%Error: data/full_repos/permissive/431682734/LabL/LabL11.v:51: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n                expect = a + ~b + 1;\n                ^~~~~~\n%Error: data/full_repos/permissive/431682734/LabL/LabL11.v:51: syntax error, unexpected \'=\'\n                expect = a + ~b + 1;\n                       ^\n%Error: data/full_repos/permissive/431682734/LabL/LabL11.v:54: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n                expect = (a < b) ? 1 : 0;\n                ^~~~~~\n%Error: data/full_repos/permissive/431682734/LabL/LabL11.v:54: syntax error, unexpected \'=\'\n                expect = (a < b) ? 1 : 0;\n                       ^\n%Error: data/full_repos/permissive/431682734/LabL/LabL11.v:58: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n                expect = 0;  \n                ^~~~~~\n%Error: data/full_repos/permissive/431682734/LabL/LabL11.v:58: syntax error, unexpected \'=\'\n                expect = 0;  \n                       ^\n%Error: data/full_repos/permissive/431682734/LabL/LabL11.v:60: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n            zero = (expect == 0) ? 1 : 0;\n                    ^~~~~~\n%Error: data/full_repos/permissive/431682734/LabL/LabL11.v:60: syntax error, unexpected ==, expecting TYPE-IDENTIFIER\n            zero = (expect == 0) ? 1 : 0;\n                           ^~\n%Warning-STMTDLY: data/full_repos/permissive/431682734/LabL/LabL11.v:61: Unsupported: Ignoring delay on this delayed statement.\n            #1;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/431682734/LabL/LabL11.v:65: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n            $display("expected=%b", expect);\n                                    ^~~~~~\n%Error: data/full_repos/permissive/431682734/LabL/LabL11.v:65: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n            $display("expected=%b", expect);\n                                          ^\n%Error: data/full_repos/permissive/431682734/LabL/LabL11.v:68: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n            if (expect === z)\n                ^~~~~~\n%Error: data/full_repos/permissive/431682734/LabL/LabL11.v:68: syntax error, unexpected ===, expecting TYPE-IDENTIFIER\n            if (expect === z)\n                       ^~~\n%Error: Exiting due to 20 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module labL;
    reg signed [31:0] a, b;
    reg [31:0] expect;
    reg [2:0] op, tmp;
    wire ex;
    wire [31:0] z, zAnd;
    reg ok, flag, zero;
    integer i;

    and ab_and[31:0](zAnd, a, b);
    yAlu mine(z, ex, a, b, op);

    initial
    begin
        repeat (10)
        begin
            a = $random;
            b = $random;
            tmp = $random % 2;
            if (tmp == 0)
            begin
                $display("b will now equal a");
                b = a;
            end
            flag = $value$plusargs("op=%d", op);

            if (op == 3'b000)
            begin
                $display("and detected");
                for (i = 0; i < 32; i++)
                begin
                    expect[i] = a[i] & b[i];
                end
            end
            else if (op == 3'b001)
            begin
                $display("or detected");
                for (i = 0; i < 32; i++)
                begin
                    expect[i] = a[i] | b[i];
                end
            end
            else if (op == 3'b010)
            begin
                $display("add detected");
                expect = a + b;
            end
            else if (op == 3'b110)
            begin
                $display("subtract detected");
                expect = a + ~b + 1;
            end
            else if (op == 3'b111)
                expect = (a < b) ? 1 : 0;
            else
            begin
                $display("unsupported operation detected");
                expect = 0;
            end
            zero = (expect == 0) ? 1 : 0;
            #1;



            $display("expected=%b", expect);
            
            ok = 0;
            if (expect === z)
                ok = 1;


            if (ok)
            begin
                $display("PASS: a=%b b=%b op=%b z=%b", a, b, op, z);
                $display("expected zero flag value=%b", zero);
                if (zero && zero === ex)
                    $display("PASS: zero flag exception correctly raised. zero=%b", ex);
                else if (zero && zero !== ex)
                    $display("FAIL: zero flag exception was not raised when it should've been. zero=%b", ex);
                else if (!(zero) && zero !== ex)
                    $display("FAIL: zero flag exception raised incorrectly. zero=%b", ex);
                else if (!(zero) && zero === ex)
                    $display("PASS: zero flag exception not raised, and it shouldn't be!. zero=%b", ex);
            end
            else
                $display("FAIL: a=%b b=%b op=%b z=%b", a, b, op, z);
        end
    $finish;
    end
endmodule
module labL;

    reg signed [31:0] a, b;
    reg [31:0] expect;
    reg [2:0] op, tmp;
    wire ex;
    wire [31:0] z, zAnd;
    reg ok, flag, zero;
    integer i;

    and ab_and[31:0](zAnd, a, b);
    yAlu mine(z, ex, a, b, op);

    initial
    begin
        repeat (10)
        begin
            a = $random;
            b = $random;
            tmp = $random % 2;
            if (tmp == 0)
            begin
                $display("b will now equal a");
                b = a;
            end
            flag = $value$plusargs("op=%d", op);

            if (op == 3'b000)
            begin
                $display("and detected");
                for (i = 0; i < 32; i++)
                begin
                    expect[i] = a[i] & b[i];
                end
            end
            else if (op == 3'b001)
            begin
                $display("or detected");
                for (i = 0; i < 32; i++)
                begin
                    expect[i] = a[i] | b[i];
                end
            end
            else if (op == 3'b010)
            begin
                $display("add detected");
                expect = a + b;
            end
            else if (op == 3'b110)
            begin
                $display("subtract detected");
                expect = a + ~b + 1;
            end
            else if (op == 3'b111)
                expect = (a < b) ? 1 : 0;
            else
            begin
                $display("unsupported operation detected");
                expect = 0;
            end
            zero = (expect == 0) ? 1 : 0;
            #1;



            $display("expected=%b", expect);
            
            ok = 0;
            if (expect === z)
                ok = 1;


            if (ok)
            begin
                $display("PASS: a=%b b=%b op=%b z=%b", a, b, op, z);
                $display("expected zero flag value=%b", zero);
                if (zero && zero === ex)
                    $display("PASS: zero flag exception correctly raised. zero=%b", ex);
                else if (zero && zero !== ex)
                    $display("FAIL: zero flag exception was not raised when it should've been. zero=%b", ex);
                else if (!(zero) && zero !== ex)
                    $display("FAIL: zero flag exception raised incorrectly. zero=%b", ex);
                else if (!(zero) && zero === ex)
                    $display("PASS: zero flag exception not raised, and it shouldn't be!. zero=%b", ex);
            end
            else
                $display("FAIL: a=%b b=%b op=%b z=%b", a, b, op, z);
        end
    $finish;
    end
endmodule