data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_input.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_input.v:37: Cannot find include file: c_functions.v\n`include "c_functions.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v.v\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v.sv\n             c_functions.v\n             c_functions.v.v\n             c_functions.v.sv\n             obj_dir/c_functions.v\n             obj_dir/c_functions.v.v\n             obj_dir/c_functions.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_input.v:38: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_input.v:39: Cannot find include file: rtr_constants.v\n`include "rtr_constants.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_input.v:50: Define or directive not defined: \'`PACKET_FORMAT_EXPLICIT_LENGTH\'\n   parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;\n                             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_input.v:50: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;\n                                                           ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_input.v:69: Define or directive not defined: \'`RESET_TYPE_ASYNC\'\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_input.v:69: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                                           ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_input.v:88: Define or directive not defined: \'`PACKET_FORMAT_HEAD_TAIL\'\n     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_input.v:88: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? \n                                                 ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_input.v:90: Define or directive not defined: \'`PACKET_FORMAT_TAIL_ONLY\'\n       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_input.v:92: Define or directive not defined: \'`PACKET_FORMAT_EXPLICIT_LENGTH\'\n       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_input.v:101: Define or directive not defined: \'`PACKET_FORMAT_HEAD_TAIL\'\n     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_input.v:101: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? \n                                                 ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_input.v:103: Define or directive not defined: \'`PACKET_FORMAT_TAIL_ONLY\'\n       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_input.v:105: Define or directive not defined: \'`PACKET_FORMAT_EXPLICIT_LENGTH\'\n       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_input.v:211: Define or directive not defined: \'`PACKET_FORMAT_HEAD_TAIL\'\n `PACKET_FORMAT_HEAD_TAIL, \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_input.v:211: syntax error, unexpected \',\', expecting endcase\n `PACKET_FORMAT_HEAD_TAIL, \n                         ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_input.v:212: Define or directive not defined: \'`PACKET_FORMAT_TAIL_ONLY\'\n `PACKET_FORMAT_TAIL_ONLY, \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_input.v:213: Define or directive not defined: \'`PACKET_FORMAT_EXPLICIT_LENGTH\'\n `PACKET_FORMAT_EXPLICIT_LENGTH:\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_input.v:268: Define or directive not defined: \'`PACKET_FORMAT_HEAD_TAIL\'\n        `PACKET_FORMAT_HEAD_TAIL:\n        ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_input.v:268: syntax error, unexpected \':\', expecting endcase\n        `PACKET_FORMAT_HEAD_TAIL:\n                                ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_input.v:276: syntax error, unexpected end\n   end\n   ^~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_input.v:278: Define or directive not defined: \'`PACKET_FORMAT_TAIL_ONLY\'\n        `PACKET_FORMAT_TAIL_ONLY:\n        ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_input.v:317: syntax error, unexpected end\n   end\n   ^~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_input.v:319: Define or directive not defined: \'`PACKET_FORMAT_EXPLICIT_LENGTH\'\n        `PACKET_FORMAT_EXPLICIT_LENGTH:\n        ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_input.v:476: syntax error, unexpected end\n   end\n   ^~~\n%Error: Cannot continue\n'
module rtr_channel_input
  (clk, reset, active, channel_in, flit_valid_out, flit_head_out, 
   flit_head_out_ivc, flit_tail_out, flit_tail_out_ivc, flit_data_out, 
   flit_sel_out_ivc);
   
`include "c_functions.v"
`include "c_constants.v"
`include "rtr_constants.v"
   
   



   

   parameter num_vcs = 4;
   

   parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;
   


   parameter max_payload_length = 4;
   


   parameter min_payload_length = 1;
   

   parameter route_info_width = 14;
   

   parameter enable_link_pm = 1;
   

   parameter flit_data_width = 64;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   



   

   localparam vc_idx_width = clogb(num_vcs);
   

   localparam payload_length_width
     = clogb(max_payload_length-min_payload_length+1);
   

   localparam flit_ctr_width = clogb(max_payload_length);
   

   localparam header_info_width
     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? 
       route_info_width : 
       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? 
       route_info_width : 
       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? 
       (route_info_width + payload_length_width) : 
       -1;
   

   localparam link_ctrl_width = enable_link_pm ? 1 : 0;
   

   localparam flit_ctrl_width
     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? 
       (1 + vc_idx_width + 1 + 1) : 
       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? 
       (1 + vc_idx_width + 1) : 
       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? 
       (1 + vc_idx_width + 1) : 
       -1;
   

   localparam channel_width
     = link_ctrl_width + flit_ctrl_width + flit_data_width;
   
   



   
   input clk;
   input reset;
   input active;
   

   input [0:channel_width-1] channel_in;
   

   output 		     flit_valid_out;
   wire 		     flit_valid_out;
   

   output 		     flit_head_out;
   wire 		     flit_head_out;
   output [0:num_vcs-1]      flit_head_out_ivc;
   wire [0:num_vcs-1] 	     flit_head_out_ivc;
   

   output 		     flit_tail_out;
   wire 		     flit_tail_out;
   output [0:num_vcs-1]      flit_tail_out_ivc;
   wire [0:num_vcs-1] 	     flit_tail_out_ivc;
   

   output [0:flit_data_width-1] flit_data_out;
   wire [0:flit_data_width-1] 	flit_data_out;
   

   output [0:num_vcs-1] 	  flit_sel_out_ivc;
   wire [0:num_vcs-1] 		  flit_sel_out_ivc;
   
   



   
   wire 			  regs_active;
   
   generate
      
      if(enable_link_pm)
	begin
	   
	   wire link_active_s, link_active_q;
	   assign link_active_s = channel_in[0];
	   c_dff
	     #(.width(1),
	       .reset_type(reset_type))
	   link_activeq
	     (.clk(clk),
	      .reset(reset),
	      .active(active),
	      .d(link_active_s),
	      .q(link_active_q));
	   
	   assign regs_active = link_active_q;
	   
	end
      else
	assign regs_active = active;
      
   endgenerate
   
   wire [0:flit_ctrl_width-1] 	  flit_ctrl_in;
   assign flit_ctrl_in = channel_in[link_ctrl_width:
				    link_ctrl_width+flit_ctrl_width-1];
   
   wire [0:flit_data_width-1] 	  flit_data_in;
   assign flit_data_in
     = channel_in[link_ctrl_width+flit_ctrl_width:
		  link_ctrl_width+flit_ctrl_width+flit_data_width-1];
   
   wire [0:flit_data_width-1] 	  flit_data_s, flit_data_q;
   assign flit_data_s = flit_data_in;
   c_dff
     #(.width(flit_data_width),
       .reset_type(reset_type))
   flit_dataq
     (.clk(clk),
      .reset(1'b0),
      .active(regs_active),
      .d(flit_data_s),
      .q(flit_data_q));
   
   assign flit_data_out = flit_data_q;
   
   wire [0:header_info_width-1]   header_info_q;
   assign header_info_q = flit_data_q[0:header_info_width-1];
   
   generate
      
      case(packet_format)
	
	`PACKET_FORMAT_HEAD_TAIL, 
	`PACKET_FORMAT_TAIL_ONLY, 
	`PACKET_FORMAT_EXPLICIT_LENGTH:
	  begin
	     
	     wire [0:flit_ctrl_width-1] flit_ctrl_s, flit_ctrl_q;
	     assign flit_ctrl_s = flit_ctrl_in;
	     
	     wire 			flit_valid_s, flit_valid_q;
	     assign flit_valid_s = flit_ctrl_s[0];
	     c_dff
	       #(.width(1),
		 .reset_type(reset_type))
	     flit_validq
	       (.clk(clk),
		.reset(reset),
		.active(regs_active),
		.d(flit_valid_s),
		.q(flit_valid_q));
	     
	     assign flit_ctrl_q[0] = flit_valid_q;
	     
	     assign flit_valid_out = flit_valid_q;
	     
	     if(flit_ctrl_width > 1)
	       begin
		  
		  c_dff
		  #(.width(flit_ctrl_width - 1),
		    .reset_type(reset_type))
		  flit_ctrlq
		    (.clk(clk),
		     .reset(1'b0),
		     .active(regs_active),
		     .d(flit_ctrl_s[1:flit_ctrl_width-1]),
		     .q(flit_ctrl_q[1:flit_ctrl_width-1]));
		  
	       end
	     
	     if(num_vcs > 1)
	       begin
		  
		  wire [0:vc_idx_width-1] flit_vc_q;
		  assign flit_vc_q = flit_ctrl_q[1:1+vc_idx_width-1];
		  
		  c_decode
		    #(.num_ports(num_vcs))
		  flit_sel_out_ivc_dec
		    (.data_in(flit_vc_q),
		     .data_out(flit_sel_out_ivc));
		  
	       end
	     else
	       assign flit_sel_out_ivc = 1'b1;
	     
	     case(packet_format)
	       
	       `PACKET_FORMAT_HEAD_TAIL:
		 begin
		    
		    assign flit_head_out = flit_ctrl_q[1+vc_idx_width+0];
		    assign flit_head_out_ivc = {num_vcs{flit_head_out}};
		    assign flit_tail_out = flit_ctrl_q[1+vc_idx_width+1];
		    assign flit_tail_out_ivc = {num_vcs{flit_tail_out}};
		    		    
		 end
	       
	       `PACKET_FORMAT_TAIL_ONLY:
		 begin
		    
		    assign flit_tail_out = flit_ctrl_q[1+vc_idx_width+0];
		    assign flit_tail_out_ivc = {num_vcs{flit_tail_out}};
		    
		    genvar ivc;
		    
		    for(ivc = 0; ivc < num_vcs; ivc = ivc + 1)
		      begin:ivcs
			 
			 wire [0:num_vcs-1] flit_head_s, flit_head_q;
			 assign flit_head_s
			   = (flit_valid_out & flit_sel_out_ivc[ivc]) ? 
			     flit_tail_out : 
			     flit_head_q;
			 c_dff
			   #(.width(1),
			     .reset_type(reset_type),
			     .reset_value(1'b1))
			 flit_headq
			   (.clk(clk),
			    .reset(reset),
			    .active(regs_active),
			    .d(flit_head_s),
			    .q(flit_head_q));
			 
			 assign flit_head_out_ivc[ivc] = flit_head_q;
			 
		      end
		    
		    c_select_1ofn
		      #(.num_ports(num_vcs),
			.width(1))
		    flit_head_out_sel
		      (.select(flit_sel_out_ivc),
		       .data_in(flit_head_out_ivc),
		       .data_out(flit_head_out));
		    
		 end
	       
	       `PACKET_FORMAT_EXPLICIT_LENGTH:
		 begin
		    
		    assign flit_head_out = flit_ctrl_q[1+vc_idx_width+0];
		    assign flit_head_out_ivc = {num_vcs{flit_head_out}};
		    
		    if(max_payload_length == 0)
		      begin
			 
			 if(max_payload_length == min_payload_length)
			   begin
			      assign flit_tail_out = flit_head_out;
			      assign flit_tail_out_ivc = flit_head_out_ivc;
			   end
			 

			 else
			   begin
			      initial
			      begin
				 $display({"ERROR: The value of the ", 
					   "max_payload_length parameter ", 
					   "(%d) in module %m cannot be ",
					   "smaller than that of the ",
					   "min_payload_length parameter ",
					   "(%d)."},
					  max_payload_length, 
					  min_payload_length);
				 $stop;
			      end
			   end

			 
		      end
		    else if(max_payload_length == 1)
		      begin
			 
			 wire has_payload;
			 
			 if(max_payload_length > min_payload_length)
			   assign has_payload = header_info_q[route_info_width];
			 else if(max_payload_length == min_payload_length)
			   assign has_payload = 1'b1;
			 

			 else
			   begin
			      initial
			      begin
				 $display({"ERROR: The value of the ", 
					   "max_payload_length parameter ",
					   "(%d) in module %m cannot be ",
					   "smaller than that of the ",
					   "min_payload_length parameter ",
					   "(%d)."},
					  max_payload_length,
					  min_payload_length);
				 $stop;
			      end
			   end

			 
			 assign flit_tail_out = ~flit_head_out | ~has_payload;
			 assign flit_tail_out_ivc = {num_vcs{flit_tail_out}};
			 			 
		      end
		    else
		      begin
			 
			 genvar ivc;
			 
			 for(ivc = 0; ivc < num_vcs; ivc = ivc + 1)
			   begin:ivcs
			      
			      wire [0:flit_ctr_width-1] flit_ctr_next;
			      wire [0:flit_ctr_width-1] flit_ctr_s, flit_ctr_q;
			      assign flit_ctr_s
				= (flit_valid_out & flit_sel_out_ivc[ivc]) ? 
				  (flit_head_out ? 
				   flit_ctr_next : 
				   (flit_ctr_q - 1'b1)) : 
				  flit_ctr_q;
			      c_dff
				#(.width(flit_ctr_width),
				  .reset_type(reset_type))
			      flit_ctrq
				(.clk(clk),
				 .reset(reset),
				 .active(active),
				 .d(flit_ctr_s),
				 .q(flit_ctr_q));
			      
			      wire 			flit_tail_out;
			      
			      if(max_payload_length > min_payload_length)
				begin
				   
				   wire [0:payload_length_width-1] 
				     payload_length;
				   assign payload_length
				     = header_info_q[route_info_width:
						     route_info_width+
						     payload_length_width-1];
				   
				   assign flit_ctr_next
				     = (min_payload_length - 1) + 
				       payload_length;
				   
				   if(min_payload_length == 0)
				     assign flit_tail_out = flit_head_out ? 
							    ~|payload_length : 
							    ~|flit_ctr_q;
				   else
				     assign flit_tail_out = ~flit_head_out & 
							    ~|flit_ctr_q;
				   
				end
			      else if(max_payload_length == min_payload_length)
				begin
				   assign flit_ctr_next
				     = max_payload_length - 1;
				   assign flit_tail_out
				     = ~flit_head_out & ~|flit_ctr_q;
				end
			      

			      else
				begin
				   initial
				   begin
				      $display({"ERROR: The value of the ", 
						"max_payload_length parameter ",
						"(%d) in module %m cannot be ",
						"smaller than that of the ",
						"min_payload_length ", 
						"parameter (%d)."},
					       max_payload_length,
					       min_payload_length);
				      $stop;
				   end
				end

			      
			      assign flit_tail_out_ivc[ivc] = flit_tail_out;
			      
			   end
			 
			 c_select_1ofn
			   #(.num_ports(num_vcs),
			     .width(1))
			 flit_tail_out_sel
			   (.select(flit_sel_out_ivc),
			    .data_in(flit_tail_out_ivc),
			    .data_out(flit_tail_out));
			 
		      end
		    
		 end
	       
	     endcase
	     
	  end
	
      endcase
      
   endgenerate
   
endmodule
module rtr_channel_input
  (clk, reset, active, channel_in, flit_valid_out, flit_head_out, 
   flit_head_out_ivc, flit_tail_out, flit_tail_out_ivc, flit_data_out, 
   flit_sel_out_ivc);

   
`include "c_functions.v"
`include "c_constants.v"
`include "rtr_constants.v"
   
   



   

   parameter num_vcs = 4;
   

   parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;
   


   parameter max_payload_length = 4;
   


   parameter min_payload_length = 1;
   

   parameter route_info_width = 14;
   

   parameter enable_link_pm = 1;
   

   parameter flit_data_width = 64;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   



   

   localparam vc_idx_width = clogb(num_vcs);
   

   localparam payload_length_width
     = clogb(max_payload_length-min_payload_length+1);
   

   localparam flit_ctr_width = clogb(max_payload_length);
   

   localparam header_info_width
     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? 
       route_info_width : 
       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? 
       route_info_width : 
       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? 
       (route_info_width + payload_length_width) : 
       -1;
   

   localparam link_ctrl_width = enable_link_pm ? 1 : 0;
   

   localparam flit_ctrl_width
     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? 
       (1 + vc_idx_width + 1 + 1) : 
       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? 
       (1 + vc_idx_width + 1) : 
       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? 
       (1 + vc_idx_width + 1) : 
       -1;
   

   localparam channel_width
     = link_ctrl_width + flit_ctrl_width + flit_data_width;
   
   



   
   input clk;
   input reset;
   input active;
   

   input [0:channel_width-1] channel_in;
   

   output 		     flit_valid_out;
   wire 		     flit_valid_out;
   

   output 		     flit_head_out;
   wire 		     flit_head_out;
   output [0:num_vcs-1]      flit_head_out_ivc;
   wire [0:num_vcs-1] 	     flit_head_out_ivc;
   

   output 		     flit_tail_out;
   wire 		     flit_tail_out;
   output [0:num_vcs-1]      flit_tail_out_ivc;
   wire [0:num_vcs-1] 	     flit_tail_out_ivc;
   

   output [0:flit_data_width-1] flit_data_out;
   wire [0:flit_data_width-1] 	flit_data_out;
   

   output [0:num_vcs-1] 	  flit_sel_out_ivc;
   wire [0:num_vcs-1] 		  flit_sel_out_ivc;
   
   



   
   wire 			  regs_active;
   
   generate
      
      if(enable_link_pm)
	begin
	   
	   wire link_active_s, link_active_q;
	   assign link_active_s = channel_in[0];
	   c_dff
	     #(.width(1),
	       .reset_type(reset_type))
	   link_activeq
	     (.clk(clk),
	      .reset(reset),
	      .active(active),
	      .d(link_active_s),
	      .q(link_active_q));
	   
	   assign regs_active = link_active_q;
	   
	end
      else
	assign regs_active = active;
      
   endgenerate
   
   wire [0:flit_ctrl_width-1] 	  flit_ctrl_in;
   assign flit_ctrl_in = channel_in[link_ctrl_width:
				    link_ctrl_width+flit_ctrl_width-1];
   
   wire [0:flit_data_width-1] 	  flit_data_in;
   assign flit_data_in
     = channel_in[link_ctrl_width+flit_ctrl_width:
		  link_ctrl_width+flit_ctrl_width+flit_data_width-1];
   
   wire [0:flit_data_width-1] 	  flit_data_s, flit_data_q;
   assign flit_data_s = flit_data_in;
   c_dff
     #(.width(flit_data_width),
       .reset_type(reset_type))
   flit_dataq
     (.clk(clk),
      .reset(1'b0),
      .active(regs_active),
      .d(flit_data_s),
      .q(flit_data_q));
   
   assign flit_data_out = flit_data_q;
   
   wire [0:header_info_width-1]   header_info_q;
   assign header_info_q = flit_data_q[0:header_info_width-1];
   
   generate
      
      case(packet_format)
	
	`PACKET_FORMAT_HEAD_TAIL, 
	`PACKET_FORMAT_TAIL_ONLY, 
	`PACKET_FORMAT_EXPLICIT_LENGTH:
	  begin
	     
	     wire [0:flit_ctrl_width-1] flit_ctrl_s, flit_ctrl_q;
	     assign flit_ctrl_s = flit_ctrl_in;
	     
	     wire 			flit_valid_s, flit_valid_q;
	     assign flit_valid_s = flit_ctrl_s[0];
	     c_dff
	       #(.width(1),
		 .reset_type(reset_type))
	     flit_validq
	       (.clk(clk),
		.reset(reset),
		.active(regs_active),
		.d(flit_valid_s),
		.q(flit_valid_q));
	     
	     assign flit_ctrl_q[0] = flit_valid_q;
	     
	     assign flit_valid_out = flit_valid_q;
	     
	     if(flit_ctrl_width > 1)
	       begin
		  
		  c_dff
		  #(.width(flit_ctrl_width - 1),
		    .reset_type(reset_type))
		  flit_ctrlq
		    (.clk(clk),
		     .reset(1'b0),
		     .active(regs_active),
		     .d(flit_ctrl_s[1:flit_ctrl_width-1]),
		     .q(flit_ctrl_q[1:flit_ctrl_width-1]));
		  
	       end
	     
	     if(num_vcs > 1)
	       begin
		  
		  wire [0:vc_idx_width-1] flit_vc_q;
		  assign flit_vc_q = flit_ctrl_q[1:1+vc_idx_width-1];
		  
		  c_decode
		    #(.num_ports(num_vcs))
		  flit_sel_out_ivc_dec
		    (.data_in(flit_vc_q),
		     .data_out(flit_sel_out_ivc));
		  
	       end
	     else
	       assign flit_sel_out_ivc = 1'b1;
	     
	     case(packet_format)
	       
	       `PACKET_FORMAT_HEAD_TAIL:
		 begin
		    
		    assign flit_head_out = flit_ctrl_q[1+vc_idx_width+0];
		    assign flit_head_out_ivc = {num_vcs{flit_head_out}};
		    assign flit_tail_out = flit_ctrl_q[1+vc_idx_width+1];
		    assign flit_tail_out_ivc = {num_vcs{flit_tail_out}};
		    		    
		 end
	       
	       `PACKET_FORMAT_TAIL_ONLY:
		 begin
		    
		    assign flit_tail_out = flit_ctrl_q[1+vc_idx_width+0];
		    assign flit_tail_out_ivc = {num_vcs{flit_tail_out}};
		    
		    genvar ivc;
		    
		    for(ivc = 0; ivc < num_vcs; ivc = ivc + 1)
		      begin:ivcs
			 
			 wire [0:num_vcs-1] flit_head_s, flit_head_q;
			 assign flit_head_s
			   = (flit_valid_out & flit_sel_out_ivc[ivc]) ? 
			     flit_tail_out : 
			     flit_head_q;
			 c_dff
			   #(.width(1),
			     .reset_type(reset_type),
			     .reset_value(1'b1))
			 flit_headq
			   (.clk(clk),
			    .reset(reset),
			    .active(regs_active),
			    .d(flit_head_s),
			    .q(flit_head_q));
			 
			 assign flit_head_out_ivc[ivc] = flit_head_q;
			 
		      end
		    
		    c_select_1ofn
		      #(.num_ports(num_vcs),
			.width(1))
		    flit_head_out_sel
		      (.select(flit_sel_out_ivc),
		       .data_in(flit_head_out_ivc),
		       .data_out(flit_head_out));
		    
		 end
	       
	       `PACKET_FORMAT_EXPLICIT_LENGTH:
		 begin
		    
		    assign flit_head_out = flit_ctrl_q[1+vc_idx_width+0];
		    assign flit_head_out_ivc = {num_vcs{flit_head_out}};
		    
		    if(max_payload_length == 0)
		      begin
			 
			 if(max_payload_length == min_payload_length)
			   begin
			      assign flit_tail_out = flit_head_out;
			      assign flit_tail_out_ivc = flit_head_out_ivc;
			   end
			 

			 else
			   begin
			      initial
			      begin
				 $display({"ERROR: The value of the ", 
					   "max_payload_length parameter ", 
					   "(%d) in module %m cannot be ",
					   "smaller than that of the ",
					   "min_payload_length parameter ",
					   "(%d)."},
					  max_payload_length, 
					  min_payload_length);
				 $stop;
			      end
			   end

			 
		      end
		    else if(max_payload_length == 1)
		      begin
			 
			 wire has_payload;
			 
			 if(max_payload_length > min_payload_length)
			   assign has_payload = header_info_q[route_info_width];
			 else if(max_payload_length == min_payload_length)
			   assign has_payload = 1'b1;
			 

			 else
			   begin
			      initial
			      begin
				 $display({"ERROR: The value of the ", 
					   "max_payload_length parameter ",
					   "(%d) in module %m cannot be ",
					   "smaller than that of the ",
					   "min_payload_length parameter ",
					   "(%d)."},
					  max_payload_length,
					  min_payload_length);
				 $stop;
			      end
			   end

			 
			 assign flit_tail_out = ~flit_head_out | ~has_payload;
			 assign flit_tail_out_ivc = {num_vcs{flit_tail_out}};
			 			 
		      end
		    else
		      begin
			 
			 genvar ivc;
			 
			 for(ivc = 0; ivc < num_vcs; ivc = ivc + 1)
			   begin:ivcs
			      
			      wire [0:flit_ctr_width-1] flit_ctr_next;
			      wire [0:flit_ctr_width-1] flit_ctr_s, flit_ctr_q;
			      assign flit_ctr_s
				= (flit_valid_out & flit_sel_out_ivc[ivc]) ? 
				  (flit_head_out ? 
				   flit_ctr_next : 
				   (flit_ctr_q - 1'b1)) : 
				  flit_ctr_q;
			      c_dff
				#(.width(flit_ctr_width),
				  .reset_type(reset_type))
			      flit_ctrq
				(.clk(clk),
				 .reset(reset),
				 .active(active),
				 .d(flit_ctr_s),
				 .q(flit_ctr_q));
			      
			      wire 			flit_tail_out;
			      
			      if(max_payload_length > min_payload_length)
				begin
				   
				   wire [0:payload_length_width-1] 
				     payload_length;
				   assign payload_length
				     = header_info_q[route_info_width:
						     route_info_width+
						     payload_length_width-1];
				   
				   assign flit_ctr_next
				     = (min_payload_length - 1) + 
				       payload_length;
				   
				   if(min_payload_length == 0)
				     assign flit_tail_out = flit_head_out ? 
							    ~|payload_length : 
							    ~|flit_ctr_q;
				   else
				     assign flit_tail_out = ~flit_head_out & 
							    ~|flit_ctr_q;
				   
				end
			      else if(max_payload_length == min_payload_length)
				begin
				   assign flit_ctr_next
				     = max_payload_length - 1;
				   assign flit_tail_out
				     = ~flit_head_out & ~|flit_ctr_q;
				end
			      

			      else
				begin
				   initial
				   begin
				      $display({"ERROR: The value of the ", 
						"max_payload_length parameter ",
						"(%d) in module %m cannot be ",
						"smaller than that of the ",
						"min_payload_length ", 
						"parameter (%d)."},
					       max_payload_length,
					       min_payload_length);
				      $stop;
				   end
				end

			      
			      assign flit_tail_out_ivc[ivc] = flit_tail_out;
			      
			   end
			 
			 c_select_1ofn
			   #(.num_ports(num_vcs),
			     .width(1))
			 flit_tail_out_sel
			   (.select(flit_sel_out_ivc),
			    .data_in(flit_tail_out_ivc),
			    .data_out(flit_tail_out));
			 
		      end
		    
		 end
	       
	     endcase
	     
	  end
	
      endcase
      
   endgenerate
   
endmodule