data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/macro/rwsgen_cc.v
data/verilator_xmls/5d0d62cb-e2a2-4e15-8085-e4b5a5ee5bf7.xml
module rwsgen_cc
    (
     clk,
     pce_,
     prnw,
     pws,
     prs,
     pcesyn_
     );




input   clk,
        pce_,
        prnw;
output  pws,
        prs,
        pcesyn_;




wire    cerst;
assign  cerst = pce_;

reg [4:0]   rin = {5{1'b1}};
always @(posedge clk)
    begin
    if(cerst) rin <= {5{1'b1}};
    else rin <= {rin[3:0],pce_};
    end

reg pul = 1'b0;
always @(posedge clk)
    begin
    pul <= (rin[4:1] == 4'b1100);
    end

reg [1:0] rprnw = 2'd0;
always @(posedge clk)
    begin
    rprnw <= {rprnw[0],prnw};
    end

reg     pws = 1'b0;
reg     prs = 1'b0;
always @(posedge clk)
    begin
    pws <= ~rprnw[1] & pul;
    prs <= rprnw[1] & pul;
    end

assign  pcesyn_ = rin[1];
    
endmodule
module rwsgen_cc
    (
     clk,
     pce_,
     prnw,
     pws,
     prs,
     pcesyn_
     );





input   clk,
        pce_,
        prnw;
output  pws,
        prs,
        pcesyn_;




wire    cerst;
assign  cerst = pce_;

reg [4:0]   rin = {5{1'b1}};
always @(posedge clk)
    begin
    if(cerst) rin <= {5{1'b1}};
    else rin <= {rin[3:0],pce_};
    end

reg pul = 1'b0;
always @(posedge clk)
    begin
    pul <= (rin[4:1] == 4'b1100);
    end

reg [1:0] rprnw = 2'd0;
always @(posedge clk)
    begin
    rprnw <= {rprnw[0],prnw};
    end

reg     pws = 1'b0;
reg     prs = 1'b0;
always @(posedge clk)
    begin
    pws <= ~rprnw[1] & pul;
    prs <= rprnw[1] & pul;
    end

assign  pcesyn_ = rin[1];
    
endmodule