data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/nocif/NV_NVDLA_CVIF_read.v
1: b'%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/nocif/NV_NVDLA_CVIF_read.v:11: Cannot find include file: simulate_x_tick.vh\n`include "simulate_x_tick.vh" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/nocif,data/full_repos/permissive/509468557/simulate_x_tick.vh\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/nocif,data/full_repos/permissive/509468557/simulate_x_tick.vh.v\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/nocif,data/full_repos/permissive/509468557/simulate_x_tick.vh.sv\n             simulate_x_tick.vh\n             simulate_x_tick.vh.v\n             simulate_x_tick.vh.sv\n             obj_dir/simulate_x_tick.vh\n             obj_dir/simulate_x_tick.vh.v\n             obj_dir/simulate_x_tick.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module NV_NVDLA_CVIF_read (
   bdma2cvif_rd_cdt_lat_fifo_pop
  ,bdma2cvif_rd_req_pd
  ,bdma2cvif_rd_req_valid
  ,cdma_dat2cvif_rd_req_pd
  ,cdma_dat2cvif_rd_req_valid
  ,cdma_wt2cvif_rd_req_pd
  ,cdma_wt2cvif_rd_req_valid
  ,cdp2cvif_rd_cdt_lat_fifo_pop
  ,cdp2cvif_rd_req_pd
  ,cdp2cvif_rd_req_valid
  ,cvif2bdma_rd_rsp_ready
  ,cvif2cdma_dat_rd_rsp_ready
  ,cvif2cdma_wt_rd_rsp_ready
  ,cvif2cdp_rd_rsp_ready
  ,cvif2noc_axi_ar_arready
  ,cvif2pdp_rd_rsp_ready
  ,cvif2rbk_rd_rsp_ready
  ,cvif2sdp_b_rd_rsp_ready
  ,cvif2sdp_e_rd_rsp_ready
  ,cvif2sdp_n_rd_rsp_ready
  ,cvif2sdp_rd_rsp_ready
  ,noc2cvif_axi_r_rdata
  ,noc2cvif_axi_r_rid
  ,noc2cvif_axi_r_rlast
  ,noc2cvif_axi_r_rvalid
  ,nvdla_core_clk
  ,nvdla_core_rstn
  ,pdp2cvif_rd_cdt_lat_fifo_pop
  ,pdp2cvif_rd_req_pd
  ,pdp2cvif_rd_req_valid
  ,pwrbus_ram_pd
  ,rbk2cvif_rd_cdt_lat_fifo_pop
  ,rbk2cvif_rd_req_pd
  ,rbk2cvif_rd_req_valid
  ,reg2dp_rd_os_cnt
  ,reg2dp_rd_weight_bdma
  ,reg2dp_rd_weight_cdma_dat
  ,reg2dp_rd_weight_cdma_wt
  ,reg2dp_rd_weight_cdp
  ,reg2dp_rd_weight_pdp
  ,reg2dp_rd_weight_rbk
  ,reg2dp_rd_weight_sdp
  ,reg2dp_rd_weight_sdp_b
  ,reg2dp_rd_weight_sdp_e
  ,reg2dp_rd_weight_sdp_n
  ,sdp2cvif_rd_cdt_lat_fifo_pop
  ,sdp2cvif_rd_req_pd
  ,sdp2cvif_rd_req_valid
  ,sdp_b2cvif_rd_cdt_lat_fifo_pop
  ,sdp_b2cvif_rd_req_pd
  ,sdp_b2cvif_rd_req_valid
  ,sdp_e2cvif_rd_cdt_lat_fifo_pop
  ,sdp_e2cvif_rd_req_pd
  ,sdp_e2cvif_rd_req_valid
  ,sdp_n2cvif_rd_cdt_lat_fifo_pop
  ,sdp_n2cvif_rd_req_pd
  ,sdp_n2cvif_rd_req_valid
  ,bdma2cvif_rd_req_ready
  ,cdma_dat2cvif_rd_req_ready
  ,cdma_wt2cvif_rd_req_ready
  ,cdp2cvif_rd_req_ready
  ,cvif2bdma_rd_rsp_pd
  ,cvif2bdma_rd_rsp_valid
  ,cvif2cdma_dat_rd_rsp_pd
  ,cvif2cdma_dat_rd_rsp_valid
  ,cvif2cdma_wt_rd_rsp_pd
  ,cvif2cdma_wt_rd_rsp_valid
  ,cvif2cdp_rd_rsp_pd
  ,cvif2cdp_rd_rsp_valid
  ,cvif2noc_axi_ar_araddr
  ,cvif2noc_axi_ar_arid
  ,cvif2noc_axi_ar_arlen
  ,cvif2noc_axi_ar_arvalid
  ,cvif2pdp_rd_rsp_pd
  ,cvif2pdp_rd_rsp_valid
  ,cvif2rbk_rd_rsp_pd
  ,cvif2rbk_rd_rsp_valid
  ,cvif2sdp_b_rd_rsp_pd
  ,cvif2sdp_b_rd_rsp_valid
  ,cvif2sdp_e_rd_rsp_pd
  ,cvif2sdp_e_rd_rsp_valid
  ,cvif2sdp_n_rd_rsp_pd
  ,cvif2sdp_n_rd_rsp_valid
  ,cvif2sdp_rd_rsp_pd
  ,cvif2sdp_rd_rsp_valid
  ,noc2cvif_axi_r_rready
  ,pdp2cvif_rd_req_ready
  ,rbk2cvif_rd_req_ready
  ,sdp2cvif_rd_req_ready
  ,sdp_b2cvif_rd_req_ready
  ,sdp_e2cvif_rd_req_ready
  ,sdp_n2cvif_rd_req_ready
  );
















input [7:0] reg2dp_rd_os_cnt;
input [7:0] reg2dp_rd_weight_bdma;
input [7:0] reg2dp_rd_weight_cdma_dat;
input [7:0] reg2dp_rd_weight_cdma_wt;
input [7:0] reg2dp_rd_weight_cdp;
input [7:0] reg2dp_rd_weight_pdp;
input [7:0] reg2dp_rd_weight_rbk;
input [7:0] reg2dp_rd_weight_sdp;
input [7:0] reg2dp_rd_weight_sdp_b;
input [7:0] reg2dp_rd_weight_sdp_e;
input [7:0] reg2dp_rd_weight_sdp_n;




input  nvdla_core_clk;
input  nvdla_core_rstn;

input  bdma2cvif_rd_cdt_lat_fifo_pop;

input         bdma2cvif_rd_req_valid;
output        bdma2cvif_rd_req_ready;
input  [78:0] bdma2cvif_rd_req_pd;

input         cdma_dat2cvif_rd_req_valid;
output        cdma_dat2cvif_rd_req_ready;
input  [78:0] cdma_dat2cvif_rd_req_pd;

input         cdma_wt2cvif_rd_req_valid;
output        cdma_wt2cvif_rd_req_ready;
input  [78:0] cdma_wt2cvif_rd_req_pd;

input  cdp2cvif_rd_cdt_lat_fifo_pop;

input         cdp2cvif_rd_req_valid;
output        cdp2cvif_rd_req_ready;
input  [78:0] cdp2cvif_rd_req_pd;

output         cvif2bdma_rd_rsp_valid;
input          cvif2bdma_rd_rsp_ready;
output [513:0] cvif2bdma_rd_rsp_pd;

output         cvif2cdma_dat_rd_rsp_valid;
input          cvif2cdma_dat_rd_rsp_ready;
output [513:0] cvif2cdma_dat_rd_rsp_pd;

output         cvif2cdma_wt_rd_rsp_valid;
input          cvif2cdma_wt_rd_rsp_ready;
output [513:0] cvif2cdma_wt_rd_rsp_pd;

output         cvif2cdp_rd_rsp_valid;
input          cvif2cdp_rd_rsp_ready;
output [513:0] cvif2cdp_rd_rsp_pd;

output        cvif2noc_axi_ar_arvalid;
input         cvif2noc_axi_ar_arready;
output  [7:0] cvif2noc_axi_ar_arid;
output  [3:0] cvif2noc_axi_ar_arlen;
output [63:0] cvif2noc_axi_ar_araddr;

output         cvif2pdp_rd_rsp_valid;
input          cvif2pdp_rd_rsp_ready;
output [513:0] cvif2pdp_rd_rsp_pd;

output         cvif2rbk_rd_rsp_valid;
input          cvif2rbk_rd_rsp_ready;
output [513:0] cvif2rbk_rd_rsp_pd;

output         cvif2sdp_b_rd_rsp_valid;
input          cvif2sdp_b_rd_rsp_ready;
output [513:0] cvif2sdp_b_rd_rsp_pd;

output         cvif2sdp_e_rd_rsp_valid;
input          cvif2sdp_e_rd_rsp_ready;
output [513:0] cvif2sdp_e_rd_rsp_pd;

output         cvif2sdp_n_rd_rsp_valid;
input          cvif2sdp_n_rd_rsp_ready;
output [513:0] cvif2sdp_n_rd_rsp_pd;

output         cvif2sdp_rd_rsp_valid;
input          cvif2sdp_rd_rsp_ready;
output [513:0] cvif2sdp_rd_rsp_pd;

input          noc2cvif_axi_r_rvalid;
output         noc2cvif_axi_r_rready;
input    [7:0] noc2cvif_axi_r_rid;
input          noc2cvif_axi_r_rlast;
input  [511:0] noc2cvif_axi_r_rdata;

input  pdp2cvif_rd_cdt_lat_fifo_pop;

input         pdp2cvif_rd_req_valid;
output        pdp2cvif_rd_req_ready;
input  [78:0] pdp2cvif_rd_req_pd;

input [31:0] pwrbus_ram_pd;

input  rbk2cvif_rd_cdt_lat_fifo_pop;

input         rbk2cvif_rd_req_valid;
output        rbk2cvif_rd_req_ready;
input  [78:0] rbk2cvif_rd_req_pd;

input  sdp2cvif_rd_cdt_lat_fifo_pop;

input         sdp2cvif_rd_req_valid;
output        sdp2cvif_rd_req_ready;
input  [78:0] sdp2cvif_rd_req_pd;

input  sdp_b2cvif_rd_cdt_lat_fifo_pop;

input         sdp_b2cvif_rd_req_valid;
output        sdp_b2cvif_rd_req_ready;
input  [78:0] sdp_b2cvif_rd_req_pd;

input  sdp_e2cvif_rd_cdt_lat_fifo_pop;

input         sdp_e2cvif_rd_req_valid;
output        sdp_e2cvif_rd_req_ready;
input  [78:0] sdp_e2cvif_rd_req_pd;

input  sdp_n2cvif_rd_cdt_lat_fifo_pop;

input         sdp_n2cvif_rd_req_valid;
output        sdp_n2cvif_rd_req_ready;
input  [78:0] sdp_n2cvif_rd_req_pd;

wire  [6:0] cq_rd0_pd;
wire        cq_rd0_prdy;
wire        cq_rd0_pvld;
wire  [6:0] cq_rd1_pd;
wire        cq_rd1_prdy;
wire        cq_rd1_pvld;
wire  [6:0] cq_rd2_pd;
wire        cq_rd2_prdy;
wire        cq_rd2_pvld;
wire  [6:0] cq_rd3_pd;
wire        cq_rd3_prdy;
wire        cq_rd3_pvld;
wire  [6:0] cq_rd4_pd;
wire        cq_rd4_prdy;
wire        cq_rd4_pvld;
wire  [6:0] cq_rd5_pd;
wire        cq_rd5_prdy;
wire        cq_rd5_pvld;
wire  [6:0] cq_rd6_pd;
wire        cq_rd6_prdy;
wire        cq_rd6_pvld;
wire  [6:0] cq_rd7_pd;
wire        cq_rd7_prdy;
wire        cq_rd7_pvld;
wire  [6:0] cq_rd8_pd;
wire        cq_rd8_prdy;
wire        cq_rd8_pvld;
wire  [6:0] cq_rd9_pd;
wire        cq_rd9_prdy;
wire        cq_rd9_pvld;
wire  [6:0] cq_wr_pd;
wire        cq_wr_prdy;
wire        cq_wr_pvld;
wire  [3:0] cq_wr_thread_id;
wire        eg2ig_axi_vld;

NV_NVDLA_CVIF_READ_ig u_ig (
   .nvdla_core_clk                 (nvdla_core_clk)
  ,.nvdla_core_rstn                (nvdla_core_rstn)
  ,.bdma2cvif_rd_cdt_lat_fifo_pop  (bdma2cvif_rd_cdt_lat_fifo_pop)
  ,.bdma2cvif_rd_req_valid         (bdma2cvif_rd_req_valid)
  ,.bdma2cvif_rd_req_ready         (bdma2cvif_rd_req_ready)
  ,.bdma2cvif_rd_req_pd            (bdma2cvif_rd_req_pd[78:0])
  ,.cdma_dat2cvif_rd_req_valid     (cdma_dat2cvif_rd_req_valid)
  ,.cdma_dat2cvif_rd_req_ready     (cdma_dat2cvif_rd_req_ready)
  ,.cdma_dat2cvif_rd_req_pd        (cdma_dat2cvif_rd_req_pd[78:0])
  ,.cdma_wt2cvif_rd_req_valid      (cdma_wt2cvif_rd_req_valid)
  ,.cdma_wt2cvif_rd_req_ready      (cdma_wt2cvif_rd_req_ready)
  ,.cdma_wt2cvif_rd_req_pd         (cdma_wt2cvif_rd_req_pd[78:0])
  ,.cdp2cvif_rd_cdt_lat_fifo_pop   (cdp2cvif_rd_cdt_lat_fifo_pop)
  ,.cdp2cvif_rd_req_valid          (cdp2cvif_rd_req_valid)
  ,.cdp2cvif_rd_req_ready          (cdp2cvif_rd_req_ready)
  ,.cdp2cvif_rd_req_pd             (cdp2cvif_rd_req_pd[78:0])
  ,.cq_wr_pvld                     (cq_wr_pvld)
  ,.cq_wr_prdy                     (cq_wr_prdy)
  ,.cq_wr_thread_id                (cq_wr_thread_id[3:0])
  ,.cq_wr_pd                       (cq_wr_pd[6:0])
  ,.cvif2noc_axi_ar_arvalid        (cvif2noc_axi_ar_arvalid)
  ,.cvif2noc_axi_ar_arready        (cvif2noc_axi_ar_arready)
  ,.cvif2noc_axi_ar_arid           (cvif2noc_axi_ar_arid[7:0])
  ,.cvif2noc_axi_ar_arlen          (cvif2noc_axi_ar_arlen[3:0])
  ,.cvif2noc_axi_ar_araddr         (cvif2noc_axi_ar_araddr[63:0])
  ,.pdp2cvif_rd_cdt_lat_fifo_pop   (pdp2cvif_rd_cdt_lat_fifo_pop)
  ,.pdp2cvif_rd_req_valid          (pdp2cvif_rd_req_valid)
  ,.pdp2cvif_rd_req_ready          (pdp2cvif_rd_req_ready)
  ,.pdp2cvif_rd_req_pd             (pdp2cvif_rd_req_pd[78:0])
  ,.rbk2cvif_rd_cdt_lat_fifo_pop   (rbk2cvif_rd_cdt_lat_fifo_pop)
  ,.rbk2cvif_rd_req_valid          (rbk2cvif_rd_req_valid)
  ,.rbk2cvif_rd_req_ready          (rbk2cvif_rd_req_ready)
  ,.rbk2cvif_rd_req_pd             (rbk2cvif_rd_req_pd[78:0])
  ,.sdp2cvif_rd_cdt_lat_fifo_pop   (sdp2cvif_rd_cdt_lat_fifo_pop)
  ,.sdp2cvif_rd_req_valid          (sdp2cvif_rd_req_valid)
  ,.sdp2cvif_rd_req_ready          (sdp2cvif_rd_req_ready)
  ,.sdp2cvif_rd_req_pd             (sdp2cvif_rd_req_pd[78:0])
  ,.sdp_b2cvif_rd_cdt_lat_fifo_pop (sdp_b2cvif_rd_cdt_lat_fifo_pop)
  ,.sdp_b2cvif_rd_req_valid        (sdp_b2cvif_rd_req_valid)
  ,.sdp_b2cvif_rd_req_ready        (sdp_b2cvif_rd_req_ready)
  ,.sdp_b2cvif_rd_req_pd           (sdp_b2cvif_rd_req_pd[78:0])
  ,.sdp_e2cvif_rd_cdt_lat_fifo_pop (sdp_e2cvif_rd_cdt_lat_fifo_pop)
  ,.sdp_e2cvif_rd_req_valid        (sdp_e2cvif_rd_req_valid)
  ,.sdp_e2cvif_rd_req_ready        (sdp_e2cvif_rd_req_ready)
  ,.sdp_e2cvif_rd_req_pd           (sdp_e2cvif_rd_req_pd[78:0])
  ,.sdp_n2cvif_rd_cdt_lat_fifo_pop (sdp_n2cvif_rd_cdt_lat_fifo_pop)
  ,.sdp_n2cvif_rd_req_valid        (sdp_n2cvif_rd_req_valid)
  ,.sdp_n2cvif_rd_req_ready        (sdp_n2cvif_rd_req_ready)
  ,.sdp_n2cvif_rd_req_pd           (sdp_n2cvif_rd_req_pd[78:0])
  ,.eg2ig_axi_vld                  (eg2ig_axi_vld)
  ,.reg2dp_rd_os_cnt               (reg2dp_rd_os_cnt[7:0])
  ,.reg2dp_rd_weight_bdma          (reg2dp_rd_weight_bdma[7:0])
  ,.reg2dp_rd_weight_cdma_dat      (reg2dp_rd_weight_cdma_dat[7:0])
  ,.reg2dp_rd_weight_cdma_wt       (reg2dp_rd_weight_cdma_wt[7:0])
  ,.reg2dp_rd_weight_cdp           (reg2dp_rd_weight_cdp[7:0])
  ,.reg2dp_rd_weight_pdp           (reg2dp_rd_weight_pdp[7:0])
  ,.reg2dp_rd_weight_rbk           (reg2dp_rd_weight_rbk[7:0])
  ,.reg2dp_rd_weight_sdp           (reg2dp_rd_weight_sdp[7:0])
  ,.reg2dp_rd_weight_sdp_b         (reg2dp_rd_weight_sdp_b[7:0])
  ,.reg2dp_rd_weight_sdp_e         (reg2dp_rd_weight_sdp_e[7:0])
  ,.reg2dp_rd_weight_sdp_n         (reg2dp_rd_weight_sdp_n[7:0])
  );
NV_NVDLA_CVIF_READ_cq u_cq (
   .nvdla_core_clk                 (nvdla_core_clk)
  ,.nvdla_core_rstn                (nvdla_core_rstn)
  ,.cq_wr_prdy                     (cq_wr_prdy)
  ,.cq_wr_pvld                     (cq_wr_pvld)
  ,.cq_wr_thread_id                (cq_wr_thread_id[3:0])
  ,.cq_wr_pd                       (cq_wr_pd[6:0])
  ,.cq_rd0_prdy                    (cq_rd0_prdy)
  ,.cq_rd0_pvld                    (cq_rd0_pvld)
  ,.cq_rd0_pd                      (cq_rd0_pd[6:0])
  ,.cq_rd1_prdy                    (cq_rd1_prdy)
  ,.cq_rd1_pvld                    (cq_rd1_pvld)
  ,.cq_rd1_pd                      (cq_rd1_pd[6:0])
  ,.cq_rd2_prdy                    (cq_rd2_prdy)
  ,.cq_rd2_pvld                    (cq_rd2_pvld)
  ,.cq_rd2_pd                      (cq_rd2_pd[6:0])
  ,.cq_rd3_prdy                    (cq_rd3_prdy)
  ,.cq_rd3_pvld                    (cq_rd3_pvld)
  ,.cq_rd3_pd                      (cq_rd3_pd[6:0])
  ,.cq_rd4_prdy                    (cq_rd4_prdy)
  ,.cq_rd4_pvld                    (cq_rd4_pvld)
  ,.cq_rd4_pd                      (cq_rd4_pd[6:0])
  ,.cq_rd5_prdy                    (cq_rd5_prdy)
  ,.cq_rd5_pvld                    (cq_rd5_pvld)
  ,.cq_rd5_pd                      (cq_rd5_pd[6:0])
  ,.cq_rd6_prdy                    (cq_rd6_prdy)
  ,.cq_rd6_pvld                    (cq_rd6_pvld)
  ,.cq_rd6_pd                      (cq_rd6_pd[6:0])
  ,.cq_rd7_prdy                    (cq_rd7_prdy)
  ,.cq_rd7_pvld                    (cq_rd7_pvld)
  ,.cq_rd7_pd                      (cq_rd7_pd[6:0])
  ,.cq_rd8_prdy                    (cq_rd8_prdy)
  ,.cq_rd8_pvld                    (cq_rd8_pvld)
  ,.cq_rd8_pd                      (cq_rd8_pd[6:0])
  ,.cq_rd9_prdy                    (cq_rd9_prdy)
  ,.cq_rd9_pvld                    (cq_rd9_pvld)
  ,.cq_rd9_pd                      (cq_rd9_pd[6:0])
  ,.pwrbus_ram_pd                  (pwrbus_ram_pd[31:0])
  );
NV_NVDLA_CVIF_READ_eg u_eg (
   .nvdla_core_clk                 (nvdla_core_clk)
  ,.nvdla_core_rstn                (nvdla_core_rstn)
  ,.cvif2sdp_rd_rsp_valid          (cvif2sdp_rd_rsp_valid)
  ,.cvif2sdp_rd_rsp_ready          (cvif2sdp_rd_rsp_ready)
  ,.cvif2sdp_rd_rsp_pd             (cvif2sdp_rd_rsp_pd[513:0])
  ,.cvif2sdp_b_rd_rsp_valid        (cvif2sdp_b_rd_rsp_valid)
  ,.cvif2sdp_b_rd_rsp_ready        (cvif2sdp_b_rd_rsp_ready)
  ,.cvif2sdp_b_rd_rsp_pd           (cvif2sdp_b_rd_rsp_pd[513:0])
  ,.cvif2sdp_n_rd_rsp_valid        (cvif2sdp_n_rd_rsp_valid)
  ,.cvif2sdp_n_rd_rsp_ready        (cvif2sdp_n_rd_rsp_ready)
  ,.cvif2sdp_n_rd_rsp_pd           (cvif2sdp_n_rd_rsp_pd[513:0])
  ,.cvif2sdp_e_rd_rsp_valid        (cvif2sdp_e_rd_rsp_valid)
  ,.cvif2sdp_e_rd_rsp_ready        (cvif2sdp_e_rd_rsp_ready)
  ,.cvif2sdp_e_rd_rsp_pd           (cvif2sdp_e_rd_rsp_pd[513:0])
  ,.cvif2cdp_rd_rsp_valid          (cvif2cdp_rd_rsp_valid)
  ,.cvif2cdp_rd_rsp_ready          (cvif2cdp_rd_rsp_ready)
  ,.cvif2cdp_rd_rsp_pd             (cvif2cdp_rd_rsp_pd[513:0])
  ,.cvif2pdp_rd_rsp_valid          (cvif2pdp_rd_rsp_valid)
  ,.cvif2pdp_rd_rsp_ready          (cvif2pdp_rd_rsp_ready)
  ,.cvif2pdp_rd_rsp_pd             (cvif2pdp_rd_rsp_pd[513:0])
  ,.cvif2bdma_rd_rsp_valid         (cvif2bdma_rd_rsp_valid)
  ,.cvif2bdma_rd_rsp_ready         (cvif2bdma_rd_rsp_ready)
  ,.cvif2bdma_rd_rsp_pd            (cvif2bdma_rd_rsp_pd[513:0])
  ,.cvif2rbk_rd_rsp_valid          (cvif2rbk_rd_rsp_valid)
  ,.cvif2rbk_rd_rsp_ready          (cvif2rbk_rd_rsp_ready)
  ,.cvif2rbk_rd_rsp_pd             (cvif2rbk_rd_rsp_pd[513:0])
  ,.cvif2cdma_wt_rd_rsp_valid      (cvif2cdma_wt_rd_rsp_valid)
  ,.cvif2cdma_wt_rd_rsp_ready      (cvif2cdma_wt_rd_rsp_ready)
  ,.cvif2cdma_wt_rd_rsp_pd         (cvif2cdma_wt_rd_rsp_pd[513:0])
  ,.cvif2cdma_dat_rd_rsp_valid     (cvif2cdma_dat_rd_rsp_valid)
  ,.cvif2cdma_dat_rd_rsp_ready     (cvif2cdma_dat_rd_rsp_ready)
  ,.cvif2cdma_dat_rd_rsp_pd        (cvif2cdma_dat_rd_rsp_pd[513:0])
  ,.cq_rd0_pvld                    (cq_rd0_pvld)
  ,.cq_rd0_prdy                    (cq_rd0_prdy)
  ,.cq_rd0_pd                      (cq_rd0_pd[6:0])
  ,.cq_rd1_pvld                    (cq_rd1_pvld)
  ,.cq_rd1_prdy                    (cq_rd1_prdy)
  ,.cq_rd1_pd                      (cq_rd1_pd[6:0])
  ,.cq_rd2_pvld                    (cq_rd2_pvld)
  ,.cq_rd2_prdy                    (cq_rd2_prdy)
  ,.cq_rd2_pd                      (cq_rd2_pd[6:0])
  ,.cq_rd3_pvld                    (cq_rd3_pvld)
  ,.cq_rd3_prdy                    (cq_rd3_prdy)
  ,.cq_rd3_pd                      (cq_rd3_pd[6:0])
  ,.cq_rd4_pvld                    (cq_rd4_pvld)
  ,.cq_rd4_prdy                    (cq_rd4_prdy)
  ,.cq_rd4_pd                      (cq_rd4_pd[6:0])
  ,.cq_rd5_pvld                    (cq_rd5_pvld)
  ,.cq_rd5_prdy                    (cq_rd5_prdy)
  ,.cq_rd5_pd                      (cq_rd5_pd[6:0])
  ,.cq_rd6_pvld                    (cq_rd6_pvld)
  ,.cq_rd6_prdy                    (cq_rd6_prdy)
  ,.cq_rd6_pd                      (cq_rd6_pd[6:0])
  ,.cq_rd7_pvld                    (cq_rd7_pvld)
  ,.cq_rd7_prdy                    (cq_rd7_prdy)
  ,.cq_rd7_pd                      (cq_rd7_pd[6:0])
  ,.cq_rd8_pvld                    (cq_rd8_pvld)
  ,.cq_rd8_prdy                    (cq_rd8_prdy)
  ,.cq_rd8_pd                      (cq_rd8_pd[6:0])
  ,.cq_rd9_pvld                    (cq_rd9_pvld)
  ,.cq_rd9_prdy                    (cq_rd9_prdy)
  ,.cq_rd9_pd                      (cq_rd9_pd[6:0])
  ,.noc2cvif_axi_r_rvalid          (noc2cvif_axi_r_rvalid)
  ,.noc2cvif_axi_r_rready          (noc2cvif_axi_r_rready)
  ,.noc2cvif_axi_r_rid             (noc2cvif_axi_r_rid[7:0])
  ,.noc2cvif_axi_r_rlast           (noc2cvif_axi_r_rlast)
  ,.noc2cvif_axi_r_rdata           (noc2cvif_axi_r_rdata[511:0])
  ,.pwrbus_ram_pd                  (pwrbus_ram_pd[31:0])
  ,.eg2ig_axi_vld                  (eg2ig_axi_vld)
  );

endmodule
module NV_NVDLA_CVIF_read (
   bdma2cvif_rd_cdt_lat_fifo_pop
  ,bdma2cvif_rd_req_pd
  ,bdma2cvif_rd_req_valid
  ,cdma_dat2cvif_rd_req_pd
  ,cdma_dat2cvif_rd_req_valid
  ,cdma_wt2cvif_rd_req_pd
  ,cdma_wt2cvif_rd_req_valid
  ,cdp2cvif_rd_cdt_lat_fifo_pop
  ,cdp2cvif_rd_req_pd
  ,cdp2cvif_rd_req_valid
  ,cvif2bdma_rd_rsp_ready
  ,cvif2cdma_dat_rd_rsp_ready
  ,cvif2cdma_wt_rd_rsp_ready
  ,cvif2cdp_rd_rsp_ready
  ,cvif2noc_axi_ar_arready
  ,cvif2pdp_rd_rsp_ready
  ,cvif2rbk_rd_rsp_ready
  ,cvif2sdp_b_rd_rsp_ready
  ,cvif2sdp_e_rd_rsp_ready
  ,cvif2sdp_n_rd_rsp_ready
  ,cvif2sdp_rd_rsp_ready
  ,noc2cvif_axi_r_rdata
  ,noc2cvif_axi_r_rid
  ,noc2cvif_axi_r_rlast
  ,noc2cvif_axi_r_rvalid
  ,nvdla_core_clk
  ,nvdla_core_rstn
  ,pdp2cvif_rd_cdt_lat_fifo_pop
  ,pdp2cvif_rd_req_pd
  ,pdp2cvif_rd_req_valid
  ,pwrbus_ram_pd
  ,rbk2cvif_rd_cdt_lat_fifo_pop
  ,rbk2cvif_rd_req_pd
  ,rbk2cvif_rd_req_valid
  ,reg2dp_rd_os_cnt
  ,reg2dp_rd_weight_bdma
  ,reg2dp_rd_weight_cdma_dat
  ,reg2dp_rd_weight_cdma_wt
  ,reg2dp_rd_weight_cdp
  ,reg2dp_rd_weight_pdp
  ,reg2dp_rd_weight_rbk
  ,reg2dp_rd_weight_sdp
  ,reg2dp_rd_weight_sdp_b
  ,reg2dp_rd_weight_sdp_e
  ,reg2dp_rd_weight_sdp_n
  ,sdp2cvif_rd_cdt_lat_fifo_pop
  ,sdp2cvif_rd_req_pd
  ,sdp2cvif_rd_req_valid
  ,sdp_b2cvif_rd_cdt_lat_fifo_pop
  ,sdp_b2cvif_rd_req_pd
  ,sdp_b2cvif_rd_req_valid
  ,sdp_e2cvif_rd_cdt_lat_fifo_pop
  ,sdp_e2cvif_rd_req_pd
  ,sdp_e2cvif_rd_req_valid
  ,sdp_n2cvif_rd_cdt_lat_fifo_pop
  ,sdp_n2cvif_rd_req_pd
  ,sdp_n2cvif_rd_req_valid
  ,bdma2cvif_rd_req_ready
  ,cdma_dat2cvif_rd_req_ready
  ,cdma_wt2cvif_rd_req_ready
  ,cdp2cvif_rd_req_ready
  ,cvif2bdma_rd_rsp_pd
  ,cvif2bdma_rd_rsp_valid
  ,cvif2cdma_dat_rd_rsp_pd
  ,cvif2cdma_dat_rd_rsp_valid
  ,cvif2cdma_wt_rd_rsp_pd
  ,cvif2cdma_wt_rd_rsp_valid
  ,cvif2cdp_rd_rsp_pd
  ,cvif2cdp_rd_rsp_valid
  ,cvif2noc_axi_ar_araddr
  ,cvif2noc_axi_ar_arid
  ,cvif2noc_axi_ar_arlen
  ,cvif2noc_axi_ar_arvalid
  ,cvif2pdp_rd_rsp_pd
  ,cvif2pdp_rd_rsp_valid
  ,cvif2rbk_rd_rsp_pd
  ,cvif2rbk_rd_rsp_valid
  ,cvif2sdp_b_rd_rsp_pd
  ,cvif2sdp_b_rd_rsp_valid
  ,cvif2sdp_e_rd_rsp_pd
  ,cvif2sdp_e_rd_rsp_valid
  ,cvif2sdp_n_rd_rsp_pd
  ,cvif2sdp_n_rd_rsp_valid
  ,cvif2sdp_rd_rsp_pd
  ,cvif2sdp_rd_rsp_valid
  ,noc2cvif_axi_r_rready
  ,pdp2cvif_rd_req_ready
  ,rbk2cvif_rd_req_ready
  ,sdp2cvif_rd_req_ready
  ,sdp_b2cvif_rd_req_ready
  ,sdp_e2cvif_rd_req_ready
  ,sdp_n2cvif_rd_req_ready
  );

















input [7:0] reg2dp_rd_os_cnt;
input [7:0] reg2dp_rd_weight_bdma;
input [7:0] reg2dp_rd_weight_cdma_dat;
input [7:0] reg2dp_rd_weight_cdma_wt;
input [7:0] reg2dp_rd_weight_cdp;
input [7:0] reg2dp_rd_weight_pdp;
input [7:0] reg2dp_rd_weight_rbk;
input [7:0] reg2dp_rd_weight_sdp;
input [7:0] reg2dp_rd_weight_sdp_b;
input [7:0] reg2dp_rd_weight_sdp_e;
input [7:0] reg2dp_rd_weight_sdp_n;




input  nvdla_core_clk;
input  nvdla_core_rstn;

input  bdma2cvif_rd_cdt_lat_fifo_pop;

input         bdma2cvif_rd_req_valid;
output        bdma2cvif_rd_req_ready;
input  [78:0] bdma2cvif_rd_req_pd;

input         cdma_dat2cvif_rd_req_valid;
output        cdma_dat2cvif_rd_req_ready;
input  [78:0] cdma_dat2cvif_rd_req_pd;

input         cdma_wt2cvif_rd_req_valid;
output        cdma_wt2cvif_rd_req_ready;
input  [78:0] cdma_wt2cvif_rd_req_pd;

input  cdp2cvif_rd_cdt_lat_fifo_pop;

input         cdp2cvif_rd_req_valid;
output        cdp2cvif_rd_req_ready;
input  [78:0] cdp2cvif_rd_req_pd;

output         cvif2bdma_rd_rsp_valid;
input          cvif2bdma_rd_rsp_ready;
output [513:0] cvif2bdma_rd_rsp_pd;

output         cvif2cdma_dat_rd_rsp_valid;
input          cvif2cdma_dat_rd_rsp_ready;
output [513:0] cvif2cdma_dat_rd_rsp_pd;

output         cvif2cdma_wt_rd_rsp_valid;
input          cvif2cdma_wt_rd_rsp_ready;
output [513:0] cvif2cdma_wt_rd_rsp_pd;

output         cvif2cdp_rd_rsp_valid;
input          cvif2cdp_rd_rsp_ready;
output [513:0] cvif2cdp_rd_rsp_pd;

output        cvif2noc_axi_ar_arvalid;
input         cvif2noc_axi_ar_arready;
output  [7:0] cvif2noc_axi_ar_arid;
output  [3:0] cvif2noc_axi_ar_arlen;
output [63:0] cvif2noc_axi_ar_araddr;

output         cvif2pdp_rd_rsp_valid;
input          cvif2pdp_rd_rsp_ready;
output [513:0] cvif2pdp_rd_rsp_pd;

output         cvif2rbk_rd_rsp_valid;
input          cvif2rbk_rd_rsp_ready;
output [513:0] cvif2rbk_rd_rsp_pd;

output         cvif2sdp_b_rd_rsp_valid;
input          cvif2sdp_b_rd_rsp_ready;
output [513:0] cvif2sdp_b_rd_rsp_pd;

output         cvif2sdp_e_rd_rsp_valid;
input          cvif2sdp_e_rd_rsp_ready;
output [513:0] cvif2sdp_e_rd_rsp_pd;

output         cvif2sdp_n_rd_rsp_valid;
input          cvif2sdp_n_rd_rsp_ready;
output [513:0] cvif2sdp_n_rd_rsp_pd;

output         cvif2sdp_rd_rsp_valid;
input          cvif2sdp_rd_rsp_ready;
output [513:0] cvif2sdp_rd_rsp_pd;

input          noc2cvif_axi_r_rvalid;
output         noc2cvif_axi_r_rready;
input    [7:0] noc2cvif_axi_r_rid;
input          noc2cvif_axi_r_rlast;
input  [511:0] noc2cvif_axi_r_rdata;

input  pdp2cvif_rd_cdt_lat_fifo_pop;

input         pdp2cvif_rd_req_valid;
output        pdp2cvif_rd_req_ready;
input  [78:0] pdp2cvif_rd_req_pd;

input [31:0] pwrbus_ram_pd;

input  rbk2cvif_rd_cdt_lat_fifo_pop;

input         rbk2cvif_rd_req_valid;
output        rbk2cvif_rd_req_ready;
input  [78:0] rbk2cvif_rd_req_pd;

input  sdp2cvif_rd_cdt_lat_fifo_pop;

input         sdp2cvif_rd_req_valid;
output        sdp2cvif_rd_req_ready;
input  [78:0] sdp2cvif_rd_req_pd;

input  sdp_b2cvif_rd_cdt_lat_fifo_pop;

input         sdp_b2cvif_rd_req_valid;
output        sdp_b2cvif_rd_req_ready;
input  [78:0] sdp_b2cvif_rd_req_pd;

input  sdp_e2cvif_rd_cdt_lat_fifo_pop;

input         sdp_e2cvif_rd_req_valid;
output        sdp_e2cvif_rd_req_ready;
input  [78:0] sdp_e2cvif_rd_req_pd;

input  sdp_n2cvif_rd_cdt_lat_fifo_pop;

input         sdp_n2cvif_rd_req_valid;
output        sdp_n2cvif_rd_req_ready;
input  [78:0] sdp_n2cvif_rd_req_pd;

wire  [6:0] cq_rd0_pd;
wire        cq_rd0_prdy;
wire        cq_rd0_pvld;
wire  [6:0] cq_rd1_pd;
wire        cq_rd1_prdy;
wire        cq_rd1_pvld;
wire  [6:0] cq_rd2_pd;
wire        cq_rd2_prdy;
wire        cq_rd2_pvld;
wire  [6:0] cq_rd3_pd;
wire        cq_rd3_prdy;
wire        cq_rd3_pvld;
wire  [6:0] cq_rd4_pd;
wire        cq_rd4_prdy;
wire        cq_rd4_pvld;
wire  [6:0] cq_rd5_pd;
wire        cq_rd5_prdy;
wire        cq_rd5_pvld;
wire  [6:0] cq_rd6_pd;
wire        cq_rd6_prdy;
wire        cq_rd6_pvld;
wire  [6:0] cq_rd7_pd;
wire        cq_rd7_prdy;
wire        cq_rd7_pvld;
wire  [6:0] cq_rd8_pd;
wire        cq_rd8_prdy;
wire        cq_rd8_pvld;
wire  [6:0] cq_rd9_pd;
wire        cq_rd9_prdy;
wire        cq_rd9_pvld;
wire  [6:0] cq_wr_pd;
wire        cq_wr_prdy;
wire        cq_wr_pvld;
wire  [3:0] cq_wr_thread_id;
wire        eg2ig_axi_vld;

NV_NVDLA_CVIF_READ_ig u_ig (
   .nvdla_core_clk                 (nvdla_core_clk)
  ,.nvdla_core_rstn                (nvdla_core_rstn)
  ,.bdma2cvif_rd_cdt_lat_fifo_pop  (bdma2cvif_rd_cdt_lat_fifo_pop)
  ,.bdma2cvif_rd_req_valid         (bdma2cvif_rd_req_valid)
  ,.bdma2cvif_rd_req_ready         (bdma2cvif_rd_req_ready)
  ,.bdma2cvif_rd_req_pd            (bdma2cvif_rd_req_pd[78:0])
  ,.cdma_dat2cvif_rd_req_valid     (cdma_dat2cvif_rd_req_valid)
  ,.cdma_dat2cvif_rd_req_ready     (cdma_dat2cvif_rd_req_ready)
  ,.cdma_dat2cvif_rd_req_pd        (cdma_dat2cvif_rd_req_pd[78:0])
  ,.cdma_wt2cvif_rd_req_valid      (cdma_wt2cvif_rd_req_valid)
  ,.cdma_wt2cvif_rd_req_ready      (cdma_wt2cvif_rd_req_ready)
  ,.cdma_wt2cvif_rd_req_pd         (cdma_wt2cvif_rd_req_pd[78:0])
  ,.cdp2cvif_rd_cdt_lat_fifo_pop   (cdp2cvif_rd_cdt_lat_fifo_pop)
  ,.cdp2cvif_rd_req_valid          (cdp2cvif_rd_req_valid)
  ,.cdp2cvif_rd_req_ready          (cdp2cvif_rd_req_ready)
  ,.cdp2cvif_rd_req_pd             (cdp2cvif_rd_req_pd[78:0])
  ,.cq_wr_pvld                     (cq_wr_pvld)
  ,.cq_wr_prdy                     (cq_wr_prdy)
  ,.cq_wr_thread_id                (cq_wr_thread_id[3:0])
  ,.cq_wr_pd                       (cq_wr_pd[6:0])
  ,.cvif2noc_axi_ar_arvalid        (cvif2noc_axi_ar_arvalid)
  ,.cvif2noc_axi_ar_arready        (cvif2noc_axi_ar_arready)
  ,.cvif2noc_axi_ar_arid           (cvif2noc_axi_ar_arid[7:0])
  ,.cvif2noc_axi_ar_arlen          (cvif2noc_axi_ar_arlen[3:0])
  ,.cvif2noc_axi_ar_araddr         (cvif2noc_axi_ar_araddr[63:0])
  ,.pdp2cvif_rd_cdt_lat_fifo_pop   (pdp2cvif_rd_cdt_lat_fifo_pop)
  ,.pdp2cvif_rd_req_valid          (pdp2cvif_rd_req_valid)
  ,.pdp2cvif_rd_req_ready          (pdp2cvif_rd_req_ready)
  ,.pdp2cvif_rd_req_pd             (pdp2cvif_rd_req_pd[78:0])
  ,.rbk2cvif_rd_cdt_lat_fifo_pop   (rbk2cvif_rd_cdt_lat_fifo_pop)
  ,.rbk2cvif_rd_req_valid          (rbk2cvif_rd_req_valid)
  ,.rbk2cvif_rd_req_ready          (rbk2cvif_rd_req_ready)
  ,.rbk2cvif_rd_req_pd             (rbk2cvif_rd_req_pd[78:0])
  ,.sdp2cvif_rd_cdt_lat_fifo_pop   (sdp2cvif_rd_cdt_lat_fifo_pop)
  ,.sdp2cvif_rd_req_valid          (sdp2cvif_rd_req_valid)
  ,.sdp2cvif_rd_req_ready          (sdp2cvif_rd_req_ready)
  ,.sdp2cvif_rd_req_pd             (sdp2cvif_rd_req_pd[78:0])
  ,.sdp_b2cvif_rd_cdt_lat_fifo_pop (sdp_b2cvif_rd_cdt_lat_fifo_pop)
  ,.sdp_b2cvif_rd_req_valid        (sdp_b2cvif_rd_req_valid)
  ,.sdp_b2cvif_rd_req_ready        (sdp_b2cvif_rd_req_ready)
  ,.sdp_b2cvif_rd_req_pd           (sdp_b2cvif_rd_req_pd[78:0])
  ,.sdp_e2cvif_rd_cdt_lat_fifo_pop (sdp_e2cvif_rd_cdt_lat_fifo_pop)
  ,.sdp_e2cvif_rd_req_valid        (sdp_e2cvif_rd_req_valid)
  ,.sdp_e2cvif_rd_req_ready        (sdp_e2cvif_rd_req_ready)
  ,.sdp_e2cvif_rd_req_pd           (sdp_e2cvif_rd_req_pd[78:0])
  ,.sdp_n2cvif_rd_cdt_lat_fifo_pop (sdp_n2cvif_rd_cdt_lat_fifo_pop)
  ,.sdp_n2cvif_rd_req_valid        (sdp_n2cvif_rd_req_valid)
  ,.sdp_n2cvif_rd_req_ready        (sdp_n2cvif_rd_req_ready)
  ,.sdp_n2cvif_rd_req_pd           (sdp_n2cvif_rd_req_pd[78:0])
  ,.eg2ig_axi_vld                  (eg2ig_axi_vld)
  ,.reg2dp_rd_os_cnt               (reg2dp_rd_os_cnt[7:0])
  ,.reg2dp_rd_weight_bdma          (reg2dp_rd_weight_bdma[7:0])
  ,.reg2dp_rd_weight_cdma_dat      (reg2dp_rd_weight_cdma_dat[7:0])
  ,.reg2dp_rd_weight_cdma_wt       (reg2dp_rd_weight_cdma_wt[7:0])
  ,.reg2dp_rd_weight_cdp           (reg2dp_rd_weight_cdp[7:0])
  ,.reg2dp_rd_weight_pdp           (reg2dp_rd_weight_pdp[7:0])
  ,.reg2dp_rd_weight_rbk           (reg2dp_rd_weight_rbk[7:0])
  ,.reg2dp_rd_weight_sdp           (reg2dp_rd_weight_sdp[7:0])
  ,.reg2dp_rd_weight_sdp_b         (reg2dp_rd_weight_sdp_b[7:0])
  ,.reg2dp_rd_weight_sdp_e         (reg2dp_rd_weight_sdp_e[7:0])
  ,.reg2dp_rd_weight_sdp_n         (reg2dp_rd_weight_sdp_n[7:0])
  );
NV_NVDLA_CVIF_READ_cq u_cq (
   .nvdla_core_clk                 (nvdla_core_clk)
  ,.nvdla_core_rstn                (nvdla_core_rstn)
  ,.cq_wr_prdy                     (cq_wr_prdy)
  ,.cq_wr_pvld                     (cq_wr_pvld)
  ,.cq_wr_thread_id                (cq_wr_thread_id[3:0])
  ,.cq_wr_pd                       (cq_wr_pd[6:0])
  ,.cq_rd0_prdy                    (cq_rd0_prdy)
  ,.cq_rd0_pvld                    (cq_rd0_pvld)
  ,.cq_rd0_pd                      (cq_rd0_pd[6:0])
  ,.cq_rd1_prdy                    (cq_rd1_prdy)
  ,.cq_rd1_pvld                    (cq_rd1_pvld)
  ,.cq_rd1_pd                      (cq_rd1_pd[6:0])
  ,.cq_rd2_prdy                    (cq_rd2_prdy)
  ,.cq_rd2_pvld                    (cq_rd2_pvld)
  ,.cq_rd2_pd                      (cq_rd2_pd[6:0])
  ,.cq_rd3_prdy                    (cq_rd3_prdy)
  ,.cq_rd3_pvld                    (cq_rd3_pvld)
  ,.cq_rd3_pd                      (cq_rd3_pd[6:0])
  ,.cq_rd4_prdy                    (cq_rd4_prdy)
  ,.cq_rd4_pvld                    (cq_rd4_pvld)
  ,.cq_rd4_pd                      (cq_rd4_pd[6:0])
  ,.cq_rd5_prdy                    (cq_rd5_prdy)
  ,.cq_rd5_pvld                    (cq_rd5_pvld)
  ,.cq_rd5_pd                      (cq_rd5_pd[6:0])
  ,.cq_rd6_prdy                    (cq_rd6_prdy)
  ,.cq_rd6_pvld                    (cq_rd6_pvld)
  ,.cq_rd6_pd                      (cq_rd6_pd[6:0])
  ,.cq_rd7_prdy                    (cq_rd7_prdy)
  ,.cq_rd7_pvld                    (cq_rd7_pvld)
  ,.cq_rd7_pd                      (cq_rd7_pd[6:0])
  ,.cq_rd8_prdy                    (cq_rd8_prdy)
  ,.cq_rd8_pvld                    (cq_rd8_pvld)
  ,.cq_rd8_pd                      (cq_rd8_pd[6:0])
  ,.cq_rd9_prdy                    (cq_rd9_prdy)
  ,.cq_rd9_pvld                    (cq_rd9_pvld)
  ,.cq_rd9_pd                      (cq_rd9_pd[6:0])
  ,.pwrbus_ram_pd                  (pwrbus_ram_pd[31:0])
  );
NV_NVDLA_CVIF_READ_eg u_eg (
   .nvdla_core_clk                 (nvdla_core_clk)
  ,.nvdla_core_rstn                (nvdla_core_rstn)
  ,.cvif2sdp_rd_rsp_valid          (cvif2sdp_rd_rsp_valid)
  ,.cvif2sdp_rd_rsp_ready          (cvif2sdp_rd_rsp_ready)
  ,.cvif2sdp_rd_rsp_pd             (cvif2sdp_rd_rsp_pd[513:0])
  ,.cvif2sdp_b_rd_rsp_valid        (cvif2sdp_b_rd_rsp_valid)
  ,.cvif2sdp_b_rd_rsp_ready        (cvif2sdp_b_rd_rsp_ready)
  ,.cvif2sdp_b_rd_rsp_pd           (cvif2sdp_b_rd_rsp_pd[513:0])
  ,.cvif2sdp_n_rd_rsp_valid        (cvif2sdp_n_rd_rsp_valid)
  ,.cvif2sdp_n_rd_rsp_ready        (cvif2sdp_n_rd_rsp_ready)
  ,.cvif2sdp_n_rd_rsp_pd           (cvif2sdp_n_rd_rsp_pd[513:0])
  ,.cvif2sdp_e_rd_rsp_valid        (cvif2sdp_e_rd_rsp_valid)
  ,.cvif2sdp_e_rd_rsp_ready        (cvif2sdp_e_rd_rsp_ready)
  ,.cvif2sdp_e_rd_rsp_pd           (cvif2sdp_e_rd_rsp_pd[513:0])
  ,.cvif2cdp_rd_rsp_valid          (cvif2cdp_rd_rsp_valid)
  ,.cvif2cdp_rd_rsp_ready          (cvif2cdp_rd_rsp_ready)
  ,.cvif2cdp_rd_rsp_pd             (cvif2cdp_rd_rsp_pd[513:0])
  ,.cvif2pdp_rd_rsp_valid          (cvif2pdp_rd_rsp_valid)
  ,.cvif2pdp_rd_rsp_ready          (cvif2pdp_rd_rsp_ready)
  ,.cvif2pdp_rd_rsp_pd             (cvif2pdp_rd_rsp_pd[513:0])
  ,.cvif2bdma_rd_rsp_valid         (cvif2bdma_rd_rsp_valid)
  ,.cvif2bdma_rd_rsp_ready         (cvif2bdma_rd_rsp_ready)
  ,.cvif2bdma_rd_rsp_pd            (cvif2bdma_rd_rsp_pd[513:0])
  ,.cvif2rbk_rd_rsp_valid          (cvif2rbk_rd_rsp_valid)
  ,.cvif2rbk_rd_rsp_ready          (cvif2rbk_rd_rsp_ready)
  ,.cvif2rbk_rd_rsp_pd             (cvif2rbk_rd_rsp_pd[513:0])
  ,.cvif2cdma_wt_rd_rsp_valid      (cvif2cdma_wt_rd_rsp_valid)
  ,.cvif2cdma_wt_rd_rsp_ready      (cvif2cdma_wt_rd_rsp_ready)
  ,.cvif2cdma_wt_rd_rsp_pd         (cvif2cdma_wt_rd_rsp_pd[513:0])
  ,.cvif2cdma_dat_rd_rsp_valid     (cvif2cdma_dat_rd_rsp_valid)
  ,.cvif2cdma_dat_rd_rsp_ready     (cvif2cdma_dat_rd_rsp_ready)
  ,.cvif2cdma_dat_rd_rsp_pd        (cvif2cdma_dat_rd_rsp_pd[513:0])
  ,.cq_rd0_pvld                    (cq_rd0_pvld)
  ,.cq_rd0_prdy                    (cq_rd0_prdy)
  ,.cq_rd0_pd                      (cq_rd0_pd[6:0])
  ,.cq_rd1_pvld                    (cq_rd1_pvld)
  ,.cq_rd1_prdy                    (cq_rd1_prdy)
  ,.cq_rd1_pd                      (cq_rd1_pd[6:0])
  ,.cq_rd2_pvld                    (cq_rd2_pvld)
  ,.cq_rd2_prdy                    (cq_rd2_prdy)
  ,.cq_rd2_pd                      (cq_rd2_pd[6:0])
  ,.cq_rd3_pvld                    (cq_rd3_pvld)
  ,.cq_rd3_prdy                    (cq_rd3_prdy)
  ,.cq_rd3_pd                      (cq_rd3_pd[6:0])
  ,.cq_rd4_pvld                    (cq_rd4_pvld)
  ,.cq_rd4_prdy                    (cq_rd4_prdy)
  ,.cq_rd4_pd                      (cq_rd4_pd[6:0])
  ,.cq_rd5_pvld                    (cq_rd5_pvld)
  ,.cq_rd5_prdy                    (cq_rd5_prdy)
  ,.cq_rd5_pd                      (cq_rd5_pd[6:0])
  ,.cq_rd6_pvld                    (cq_rd6_pvld)
  ,.cq_rd6_prdy                    (cq_rd6_prdy)
  ,.cq_rd6_pd                      (cq_rd6_pd[6:0])
  ,.cq_rd7_pvld                    (cq_rd7_pvld)
  ,.cq_rd7_prdy                    (cq_rd7_prdy)
  ,.cq_rd7_pd                      (cq_rd7_pd[6:0])
  ,.cq_rd8_pvld                    (cq_rd8_pvld)
  ,.cq_rd8_prdy                    (cq_rd8_prdy)
  ,.cq_rd8_pd                      (cq_rd8_pd[6:0])
  ,.cq_rd9_pvld                    (cq_rd9_pvld)
  ,.cq_rd9_prdy                    (cq_rd9_prdy)
  ,.cq_rd9_pd                      (cq_rd9_pd[6:0])
  ,.noc2cvif_axi_r_rvalid          (noc2cvif_axi_r_rvalid)
  ,.noc2cvif_axi_r_rready          (noc2cvif_axi_r_rready)
  ,.noc2cvif_axi_r_rid             (noc2cvif_axi_r_rid[7:0])
  ,.noc2cvif_axi_r_rlast           (noc2cvif_axi_r_rlast)
  ,.noc2cvif_axi_r_rdata           (noc2cvif_axi_r_rdata[511:0])
  ,.pwrbus_ram_pd                  (pwrbus_ram_pd[31:0])
  ,.eg2ig_axi_vld                  (eg2ig_axi_vld)
  );

endmodule