data/full_repos/permissive/425157602/src/darkriscv/rtl/darkuart.v
1: b'%Error: data/full_repos/permissive/425157602/src/darkriscv/rtl/darkuart.v:32: Cannot find include file: ../rtl/config.vh\n`include "../rtl/config.vh" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/425157602/src/darkriscv/rtl,data/full_repos/permissive/425157602/../rtl/config.vh\n             data/full_repos/permissive/425157602/src/darkriscv/rtl,data/full_repos/permissive/425157602/../rtl/config.vh.v\n             data/full_repos/permissive/425157602/src/darkriscv/rtl,data/full_repos/permissive/425157602/../rtl/config.vh.sv\n             ../rtl/config.vh\n             ../rtl/config.vh.v\n             ../rtl/config.vh.sv\n             obj_dir/../rtl/config.vh\n             obj_dir/../rtl/config.vh.v\n             obj_dir/../rtl/config.vh.sv\n%Error: data/full_repos/permissive/425157602/src/darkriscv/rtl/darkuart.v:99: Define or directive not defined: \'`__BAUD__\'\n    reg [15:0]  UART_TIMER = `__BAUD__;   \n                             ^~~~~~~~~\n%Error: data/full_repos/permissive/425157602/src/darkriscv/rtl/darkuart.v:99: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    reg [15:0]  UART_TIMER = `__BAUD__;   \n                                      ^\n%Error: Exiting due to 3 error(s)\n'
module darkuart



(
    input           CLK,
    input           RES,
        
    input           RD,
    input           WR,
    input  [ 3:0]   BE,
    input  [31:0]   DATAI,
    output [31:0]   DATAO,
    output          IRQ,

    input           RXD,
    output          TXD,

`ifdef SIMULATION
    output reg	    FINISH_REQ = 0,
`endif
    
    output [3:0]    DEBUG
);

    reg [15:0]  UART_TIMER = `__BAUD__;
    reg         UART_IREQ  = 0;
    reg         UART_IACK  = 0;

`ifdef __UARTQUEUE__
    reg [ 7:0]  UART_XFIFO [0:255];
    wire [7:0]  UART_XTMP;
    reg [ 8:0]  UART_XREQ  = 0;
    reg [ 8:0]  UART_XACK  = 0;
`else
    reg [ 7:0]  UART_XFIFO = 0;
    reg         UART_XREQ  = 0;
    reg         UART_XACK  = 0;
`endif
    reg [15:0]  UART_XBAUD = 0;
    reg [ 3:0]  UART_XSTATE= 0;

`ifdef __UARTQUEUE__
    reg [ 7:0]  UART_RFIFO [0:255];
    reg [ 7:0]  UART_RTMP  = 0;
    reg [ 8:0]  UART_RREQ  = 0;
    reg [ 8:0]  UART_RACK  = 0;
`else
    reg [ 7:0]  UART_RFIFO = 0;
    reg         UART_RREQ  = 0;
    reg         UART_RACK  = 0;
`endif
    reg [15:0]  UART_RBAUD = 0;
    reg [ 3:0]  UART_RSTATE= 0;

    reg [2:0]   UART_RXDFF = -1;

`ifdef __UARTQUEUE__
    wire [7:0]  UART_STATE = { 6'd0, UART_RREQ!=UART_RACK, UART_XREQ==(UART_XACK^9'h100) };

    integer i;
    
    initial
    for(i=0;i!=256;i=i+1)
    begin
        UART_RFIFO[i] = 0;
        UART_XFIFO[i] = 0;
    end
`else
    wire [7:0]  UART_STATE = { 6'd0, UART_RREQ!=UART_RACK, UART_XREQ!=UART_XACK };    
`endif
    reg [7:0]   UART_STATEFF = 0;



    reg [31:0] DATAOFF = 0;

    always@(posedge CLK)
    begin
        if(WR)
        begin
            if(BE[1])
            begin

`ifdef SIMULATION

                if(DATAI[15:8]!=13)
                begin
                    $write("%c",DATAI[15:8]);
                end
                
                if(DATAI[15:8]=="#")
                begin
                    $display("[checkpoint #]");
                    $stop();
                end
                
                if(DATAI[15:8]==">")
                begin
                    $display(" no UART input, end simulation request...");
                    FINISH_REQ <= 1;
                end
`else
    `ifdef __UARTQUEUE__
                if(UART_XREQ!=(UART_XACK^9'h100))
                begin
                    UART_XFIFO[UART_XREQ[7:0]] <= DATAI[15:8];
                    UART_XREQ <= UART_XREQ+1;
                end
    `else            
                UART_XFIFO <= DATAI[15:8];
                UART_XREQ <= !UART_XACK;
    `endif
`endif
            end


        end
    
        if(RES)
        begin
            UART_RACK <= UART_RREQ;
            UART_STATEFF <= UART_STATE;
        end
        else
        if(RD)
        begin
`ifdef __UARTQUEUE__
            if(BE[1]) UART_RACK     <= UART_RACK!=UART_RREQ?UART_RACK+1:UART_RACK;
`else
            if(BE[1]) UART_RACK     <= UART_RREQ;
`endif
            if(BE[0]) UART_STATEFF <= UART_STATE;
        end
    end
    
    assign IRQ   = |(UART_STATE^UART_STATEFF);
`ifdef __UARTQUEUE__
    assign DATAO = { UART_TIMER, UART_RFIFO[UART_RACK[7:0]], UART_STATE };
`else
    assign DATAO = { UART_TIMER, UART_RFIFO, UART_STATE };
`endif


    
    always@(posedge CLK)
    begin    
        UART_XBAUD <= UART_XSTATE==`UART_STATE_IDLE ? UART_TIMER :
                      UART_XBAUD ? UART_XBAUD-1 : UART_TIMER;

        UART_XSTATE <= RES||UART_XSTATE==`UART_STATE_ACK  ? `UART_STATE_IDLE :
                            UART_XSTATE==`UART_STATE_IDLE ? UART_XSTATE+(UART_XREQ!=UART_XACK) :
                                                            UART_XSTATE+(UART_XBAUD==0);
`ifdef __UARTQUEUE__
        UART_XACK   <= RES ? UART_XREQ : UART_XSTATE==`UART_STATE_ACK && UART_XACK!=UART_XREQ  ? UART_XACK+1 : UART_XACK;
`else                                                           
        UART_XACK   <= RES||UART_XSTATE==`UART_STATE_ACK  ? UART_XREQ : UART_XACK;
`endif        
    end

`ifdef __UARTQUEUE__
    assign UART_XTMP = UART_XFIFO[UART_XACK[7:0]];
    
    assign TXD = UART_XSTATE[3] ? UART_XTMP[UART_XSTATE[2:0]] : UART_XSTATE==`UART_STATE_START ? 0 : 1;
`else
    assign TXD = UART_XSTATE[3] ? UART_XFIFO[UART_XSTATE[2:0]] : UART_XSTATE==`UART_STATE_START ? 0 : 1;
`endif



    always@(posedge CLK)
    begin
        UART_RXDFF <= (UART_RXDFF<<1)|RXD;

        UART_RBAUD <= UART_RSTATE==`UART_STATE_IDLE ? { 1'b0, UART_TIMER[15:1] } :
                      UART_RBAUD ? UART_RBAUD-1 : UART_TIMER;

        
        UART_RSTATE <= RES||UART_RSTATE==`UART_STATE_ACK  ? `UART_STATE_IDLE :
                            UART_RSTATE==`UART_STATE_IDLE ? UART_RSTATE+(UART_RXDFF[2:1]==2'b10) :
                                                            UART_RSTATE+(UART_RBAUD==0);
                                                            
`ifdef __UARTQUEUE__
        if(UART_RSTATE==`UART_STATE_ACK&&(UART_RREQ!=(UART_RACK^9'h100)))
        begin
            UART_RREQ <= UART_RREQ+1;
            UART_RFIFO[UART_RREQ[7:0]] <= UART_RTMP;
        end
`else
        UART_RREQ <= UART_RSTATE==`UART_STATE_ACK ? !UART_RACK : UART_RREQ;
`endif
        if(UART_RSTATE[3]) 
        begin
`ifdef __UARTQUEUE__  
            UART_RTMP[UART_RSTATE[2:0]] <= UART_RXDFF[2];
`else
            UART_RFIFO[UART_RSTATE[2:0]] <= UART_RXDFF[2];
`endif
        end
    end


    
    assign DEBUG = { RXD, TXD, UART_XSTATE!=`UART_STATE_IDLE, UART_RSTATE!=`UART_STATE_IDLE };
    
endmodule
module darkuart



(
    input           CLK,
    input           RES,
        
    input           RD,
    input           WR,
    input  [ 3:0]   BE,
    input  [31:0]   DATAI,
    output [31:0]   DATAO,
    output          IRQ,

    input           RXD,
    output          TXD,

`ifdef SIMULATION
    output reg	    FINISH_REQ = 0,
`endif
    
    output [3:0]    DEBUG
);


    reg [15:0]  UART_TIMER = `__BAUD__;
    reg         UART_IREQ  = 0;
    reg         UART_IACK  = 0;

`ifdef __UARTQUEUE__
    reg [ 7:0]  UART_XFIFO [0:255];
    wire [7:0]  UART_XTMP;
    reg [ 8:0]  UART_XREQ  = 0;
    reg [ 8:0]  UART_XACK  = 0;
`else
    reg [ 7:0]  UART_XFIFO = 0;
    reg         UART_XREQ  = 0;
    reg         UART_XACK  = 0;
`endif
    reg [15:0]  UART_XBAUD = 0;
    reg [ 3:0]  UART_XSTATE= 0;

`ifdef __UARTQUEUE__
    reg [ 7:0]  UART_RFIFO [0:255];
    reg [ 7:0]  UART_RTMP  = 0;
    reg [ 8:0]  UART_RREQ  = 0;
    reg [ 8:0]  UART_RACK  = 0;
`else
    reg [ 7:0]  UART_RFIFO = 0;
    reg         UART_RREQ  = 0;
    reg         UART_RACK  = 0;
`endif
    reg [15:0]  UART_RBAUD = 0;
    reg [ 3:0]  UART_RSTATE= 0;

    reg [2:0]   UART_RXDFF = -1;

`ifdef __UARTQUEUE__
    wire [7:0]  UART_STATE = { 6'd0, UART_RREQ!=UART_RACK, UART_XREQ==(UART_XACK^9'h100) };

    integer i;
    
    initial
    for(i=0;i!=256;i=i+1)
    begin
        UART_RFIFO[i] = 0;
        UART_XFIFO[i] = 0;
    end
`else
    wire [7:0]  UART_STATE = { 6'd0, UART_RREQ!=UART_RACK, UART_XREQ!=UART_XACK };    
`endif
    reg [7:0]   UART_STATEFF = 0;



    reg [31:0] DATAOFF = 0;

    always@(posedge CLK)
    begin
        if(WR)
        begin
            if(BE[1])
            begin

`ifdef SIMULATION

                if(DATAI[15:8]!=13)
                begin
                    $write("%c",DATAI[15:8]);
                end
                
                if(DATAI[15:8]=="#")
                begin
                    $display("[checkpoint #]");
                    $stop();
                end
                
                if(DATAI[15:8]==">")
                begin
                    $display(" no UART input, end simulation request...");
                    FINISH_REQ <= 1;
                end
`else
    `ifdef __UARTQUEUE__
                if(UART_XREQ!=(UART_XACK^9'h100))
                begin
                    UART_XFIFO[UART_XREQ[7:0]] <= DATAI[15:8];
                    UART_XREQ <= UART_XREQ+1;
                end
    `else            
                UART_XFIFO <= DATAI[15:8];
                UART_XREQ <= !UART_XACK;
    `endif
`endif
            end


        end
    
        if(RES)
        begin
            UART_RACK <= UART_RREQ;
            UART_STATEFF <= UART_STATE;
        end
        else
        if(RD)
        begin
`ifdef __UARTQUEUE__
            if(BE[1]) UART_RACK     <= UART_RACK!=UART_RREQ?UART_RACK+1:UART_RACK;
`else
            if(BE[1]) UART_RACK     <= UART_RREQ;
`endif
            if(BE[0]) UART_STATEFF <= UART_STATE;
        end
    end
    
    assign IRQ   = |(UART_STATE^UART_STATEFF);
`ifdef __UARTQUEUE__
    assign DATAO = { UART_TIMER, UART_RFIFO[UART_RACK[7:0]], UART_STATE };
`else
    assign DATAO = { UART_TIMER, UART_RFIFO, UART_STATE };
`endif


    
    always@(posedge CLK)
    begin    
        UART_XBAUD <= UART_XSTATE==`UART_STATE_IDLE ? UART_TIMER :
                      UART_XBAUD ? UART_XBAUD-1 : UART_TIMER;

        UART_XSTATE <= RES||UART_XSTATE==`UART_STATE_ACK  ? `UART_STATE_IDLE :
                            UART_XSTATE==`UART_STATE_IDLE ? UART_XSTATE+(UART_XREQ!=UART_XACK) :
                                                            UART_XSTATE+(UART_XBAUD==0);
`ifdef __UARTQUEUE__
        UART_XACK   <= RES ? UART_XREQ : UART_XSTATE==`UART_STATE_ACK && UART_XACK!=UART_XREQ  ? UART_XACK+1 : UART_XACK;
`else                                                           
        UART_XACK   <= RES||UART_XSTATE==`UART_STATE_ACK  ? UART_XREQ : UART_XACK;
`endif        
    end

`ifdef __UARTQUEUE__
    assign UART_XTMP = UART_XFIFO[UART_XACK[7:0]];
    
    assign TXD = UART_XSTATE[3] ? UART_XTMP[UART_XSTATE[2:0]] : UART_XSTATE==`UART_STATE_START ? 0 : 1;
`else
    assign TXD = UART_XSTATE[3] ? UART_XFIFO[UART_XSTATE[2:0]] : UART_XSTATE==`UART_STATE_START ? 0 : 1;
`endif



    always@(posedge CLK)
    begin
        UART_RXDFF <= (UART_RXDFF<<1)|RXD;

        UART_RBAUD <= UART_RSTATE==`UART_STATE_IDLE ? { 1'b0, UART_TIMER[15:1] } :
                      UART_RBAUD ? UART_RBAUD-1 : UART_TIMER;

        
        UART_RSTATE <= RES||UART_RSTATE==`UART_STATE_ACK  ? `UART_STATE_IDLE :
                            UART_RSTATE==`UART_STATE_IDLE ? UART_RSTATE+(UART_RXDFF[2:1]==2'b10) :
                                                            UART_RSTATE+(UART_RBAUD==0);
                                                            
`ifdef __UARTQUEUE__
        if(UART_RSTATE==`UART_STATE_ACK&&(UART_RREQ!=(UART_RACK^9'h100)))
        begin
            UART_RREQ <= UART_RREQ+1;
            UART_RFIFO[UART_RREQ[7:0]] <= UART_RTMP;
        end
`else
        UART_RREQ <= UART_RSTATE==`UART_STATE_ACK ? !UART_RACK : UART_RREQ;
`endif
        if(UART_RSTATE[3]) 
        begin
`ifdef __UARTQUEUE__  
            UART_RTMP[UART_RSTATE[2:0]] <= UART_RXDFF[2];
`else
            UART_RFIFO[UART_RSTATE[2:0]] <= UART_RXDFF[2];
`endif
        end
    end


    
    assign DEBUG = { RXD, TXD, UART_XSTATE!=`UART_STATE_IDLE, UART_RSTATE!=`UART_STATE_IDLE };
    
endmodule