data/full_repos/permissive/440575220/testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/440575220/testbench.v:8: Unsupported: Ignoring delay on this delayed statement.\n        #1 clock = ~clock;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/440575220/testbench.v:13: Unsupported or unknown PLI call: $monitor\n       $monitor("PC=%d :: Instr=%8h :: x11 = %d",\n       ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/440575220/testbench.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n%Error: data/full_repos/permissive/440575220/testbench.v:21: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("test.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/440575220/testbench.v:22: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, testbench);\n      ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
    reg  clock;

    cpu processor(.clk(clock));

    always begin
        #1 clock = ~clock;
    end

    initial begin
        clock = 0;
       $monitor("PC=%d :: Instr=%8h :: x11 = %d",
                 testbench.processor.PC,
                 testbench.processor.inst,
                testbench.processor.rf.RAM[11]);
        #100
        $finish;
    end
   initial begin
      $dumpfile("test.vcd");
      $dumpvars(0, testbench);
   end

endmodule
module testbench;

    reg  clock;

    cpu processor(.clk(clock));

    always begin
        #1 clock = ~clock;
    end

    initial begin
        clock = 0;
       $monitor("PC=%d :: Instr=%8h :: x11 = %d",
                 testbench.processor.PC,
                 testbench.processor.inst,
                testbench.processor.rf.RAM[11]);
        #100
        $finish;
    end
   initial begin
      $dumpfile("test.vcd");
      $dumpvars(0, testbench);
   end

endmodule