data/full_repos/permissive/423958267/lab02/lab02.srcs/sources_1/new/Mux4-1.v
data/verilator_xmls/a8ad0416-ec8f-4ffe-b21e-7bdee7499108.xml
module Mux4to1 #(parameter N=4) (output reg [N-1:0] M,input [1:0] sel,input[N-1:0] D0,input[N-1:0] D1,input[N-1:0] D2,input[N-1:0] D3);
    always @(sel)
    case (sel)
        2'd0 : M = D0;
        2'd1 : M = D1;
        2'd2 : M = D2;
        2'd3 : M = D3;
    endcase
endmodule
module Mux4to1 #(parameter N=4) (output reg [N-1:0] M,input [1:0] sel,input[N-1:0] D0,input[N-1:0] D1,input[N-1:0] D2,input[N-1:0] D3);

    always @(sel)
    case (sel)
        2'd0 : M = D0;
        2'd1 : M = D1;
        2'd2 : M = D2;
        2'd3 : M = D3;
    endcase
endmodule