data/full_repos/permissive/521337848/Hardware/SPISD/transmitter.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/521337848/Hardware/SPISD/transmitter.v:197: Signal definition not found, creating implicitly: \'f_startsave\'\n .f_startsave(f_startsave),\n              ^~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/SPISD/transmitter.v:376: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'arg\' generates 32 bits.\n                                                                                     : ... In instance managerx.sa\n  in3 = arg;\n      ^\n%Error: Exiting due to 2 warning(s)\n'
module saverx(
	input clk,
	input rst,
	
	input[31:0] arg,
	input sta,
	input sta40,
	input ready,
	
	output reg start3= 0,
	output reg[7:0] in3 = 0,
	output reg rdy3 = 0

);




reg f_startsave;
reg n_startsave;

always@(posedge clk or posedge rst)
	if(rst) begin
		f_startsave <= 0;
		end
	else begin
		f_startsave <= n_startsave;
		end
always@(*) begin

	n_startsave = f_startsave;
	
	start3= 0;
	in3 = 0;
	rdy3 = 0;
	
	if((sta && sta40))begin
		n_startsave = 1;
		start3 = 1;
		in3 = arg;
	end
	
	
	if(f_startsave && ready)begin
		rdy3 = 1;
		n_startsave = 0;
	end
end

endmodule
module saverx(
	input clk,
	input rst,
	
	input[31:0] arg,
	input sta,
	input sta40,
	input ready,
	
	output reg start3= 0,
	output reg[7:0] in3 = 0,
	output reg rdy3 = 0

);





reg f_startsave;
reg n_startsave;

always@(posedge clk or posedge rst)
	if(rst) begin
		f_startsave <= 0;
		end
	else begin
		f_startsave <= n_startsave;
		end
always@(*) begin

	n_startsave = f_startsave;
	
	start3= 0;
	in3 = 0;
	rdy3 = 0;
	
	if((sta && sta40))begin
		n_startsave = 1;
		start3 = 1;
		in3 = arg;
	end
	
	
	if(f_startsave && ready)begin
		rdy3 = 1;
		n_startsave = 0;
	end
end

endmodule