data/full_repos/permissive/441359809/src/yosys/tests/sat/expose_dff.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/tests/sat/expose_dff.v:7: Multiple top level modules\n                                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                          : ... Top module \'test1\'\nmodule test1(input clk, input [3:0] a, output reg [3:0] y);\n       ^~~~~\n                                                                                          : ... Top module \'test2\'\nmodule test2(input clk, input [3:0] a, output reg [3:0] y);\n       ^~~~~\n                                                                                          : ... Top module \'test3\'\nmodule test3(input clk, rst, input [3:0] a, output reg [3:0] y);\n       ^~~~~\n                                                                                          : ... Top module \'test4\'\nmodule test4(input clk, rst, input [3:0] a, output reg [3:0] y);\n       ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/sat/expose_dff.v:31: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s NEQ generates 1 bits.\n                                                                                        : ... In instance test4\n  y <= a != 0;\n    ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/sat/expose_dff.v:22: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s REDOR generates 1 bits.\n                                                                                        : ... In instance test3\n  y <= |a;\n    ^~\n%Error: Exiting due to 3 warning(s)\n'
module test4(input clk, rst, input [3:0] a, output reg [3:0] y);
wire rst_n = !rst;
always @(posedge clk, negedge rst_n)
	if (!rst_n)
		y <= 12;
	else
		y <= a != 0;
endmodule
module test4(input clk, rst, input [3:0] a, output reg [3:0] y);

wire rst_n = !rst;
always @(posedge clk, negedge rst_n)
	if (!rst_n)
		y <= 12;
	else
		y <= a != 0;
endmodule