data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/rtlackstage.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/rtlackstage.v:59: Cannot find file containing module: 'fflopxe'\nfflopxe #(INF) latreqinf (clk,rst,ack,reqinf,oreqinf);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/fflopxe\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/fflopxe.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/fflopxe.sv\n             fflopxe\n             fflopxe.v\n             fflopxe.sv\n             obj_dir/fflopxe\n             obj_dir/fflopxe.v\n             obj_dir/fflopxe.sv\n%Error: Exiting due to 1 error(s)\n"
module rtlackstage
    (clk,
     rst,
     
     req,
     reqinf,
     ack,

     oreq,
     oreqinf,
     iack
     );



parameter   INF = 32;
parameter   FANOUT = 100;



input               clk,
                    rst;

input               req;
input [INF-1:0]     reqinf;
output              ack;

output              oreq;
output [INF-1:0]    oreqinf;
input               iack;






reg                 oreq = 1'b0;
always @ (posedge clk)
    begin
    if (rst)    oreq <= 1'b0;
    else        oreq <= !iack & (oreq | req);
    end

wire ack;
assign              ack = !oreq & req;
fflopxe #(INF) latreqinf (clk,rst,ack,reqinf,oreqinf);

endmodule
module rtlackstage
    (clk,
     rst,
     
     req,
     reqinf,
     ack,

     oreq,
     oreqinf,
     iack
     );




parameter   INF = 32;
parameter   FANOUT = 100;



input               clk,
                    rst;

input               req;
input [INF-1:0]     reqinf;
output              ack;

output              oreq;
output [INF-1:0]    oreqinf;
input               iack;






reg                 oreq = 1'b0;
always @ (posedge clk)
    begin
    if (rst)    oreq <= 1'b0;
    else        oreq <= !iack & (oreq | req);
    end

wire ack;
assign              ack = !oreq & req;
fflopxe #(INF) latreqinf (clk,rst,ack,reqinf,oreqinf);

endmodule