data/full_repos/permissive/439514885/testbench/number_test.v
1: b'%Error: data/full_repos/permissive/439514885/testbench/number_test.v:13: Unsupported or unknown PLI call: $dumpfile\n   $dumpfile("number.vcd");\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/439514885/testbench/number_test.v:14: Unsupported or unknown PLI call: $dumpvars\n   $dumpvars(0,number_test);\n   ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/439514885/testbench/number_test.v:26: Unsupported: Ignoring delay on this delayed statement.\n      #5 clk = ~clk;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/439514885/testbench/number_test.v:31: Unsupported: Ignoring delay on this delayed statement.\n   #3 resetB = 1\'b1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/439514885/testbench/number_test.v:32: Unsupported: Ignoring delay on this delayed statement.\n   #12 resetB = 1\'b0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/439514885/testbench/number_test.v:33: Unsupported: Ignoring delay on this delayed statement.\n   #100 resetB = 1\'b1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/439514885/testbench/number_test.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #150\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439514885/testbench/number_test.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #10 enable = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439514885/testbench/number_test.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #2 enable = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439514885/testbench/number_test.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439514885/testbench/number_test.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #10 enable = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439514885/testbench/number_test.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #2 enable = 1\'b0;\n  ^\n%Error: Exiting due to 2 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module number_test();

wire[63:0] number;
reg clk;
reg resetB;
reg enable;
reg[79:0] numberFromBits;

reg failed = 1'b0;


initial begin
   $dumpfile("number.vcd");
   $dumpvars(0,number_test);
end

initial begin
   clk = 1'b0;
   failed = 1'b0;
end



always
   begin
      #5 clk = ~clk;
   end


initial begin
   #3 resetB = 1'b1;
   #12 resetB = 1'b0;
   #100 resetB = 1'b1;
end


initial begin
  numberFromBits = 80'h0;
  enable = 1'b0;
  #150
  numberFromBits = 80'h7800_0000_0000_0000_0000;
  enable = 1'b1;
  #10 enable = 1'b0;
  numberFromBits = 80'h87ff_ffff_ffff_ffff_ffff;
  #2 enable = 1'b0;
  if (number != 64'h0000_0000_0000_000f) begin
      failed = 1'b1;
  end
  #20
  numberFromBits = 80'h8fff_ffff_ffff_ffff_ffff;
  enable = 1'b1;
  #10 enable = 1'b0;
  #2 enable = 1'b0;
  if (number != 64'h1fff_ffff_ffff_ffff) begin
     failed = 1'b1;
  end
  $finish;
end

number_top number_top(

     .number (number),


     .clk (clk),
     .resetB (resetB),
     .enable (enable),
     .numberFromBits (numberFromBits)
);

endmodule
module number_test();


wire[63:0] number;
reg clk;
reg resetB;
reg enable;
reg[79:0] numberFromBits;

reg failed = 1'b0;


initial begin
   $dumpfile("number.vcd");
   $dumpvars(0,number_test);
end

initial begin
   clk = 1'b0;
   failed = 1'b0;
end



always
   begin
      #5 clk = ~clk;
   end


initial begin
   #3 resetB = 1'b1;
   #12 resetB = 1'b0;
   #100 resetB = 1'b1;
end


initial begin
  numberFromBits = 80'h0;
  enable = 1'b0;
  #150
  numberFromBits = 80'h7800_0000_0000_0000_0000;
  enable = 1'b1;
  #10 enable = 1'b0;
  numberFromBits = 80'h87ff_ffff_ffff_ffff_ffff;
  #2 enable = 1'b0;
  if (number != 64'h0000_0000_0000_000f) begin
      failed = 1'b1;
  end
  #20
  numberFromBits = 80'h8fff_ffff_ffff_ffff_ffff;
  enable = 1'b1;
  #10 enable = 1'b0;
  #2 enable = 1'b0;
  if (number != 64'h1fff_ffff_ffff_ffff) begin
     failed = 1'b1;
  end
  $finish;
end

number_top number_top(

     .number (number),


     .clk (clk),
     .resetB (resetB),
     .enable (enable),
     .numberFromBits (numberFromBits)
);

endmodule