data/full_repos/permissive/476477303/verilog/rtl/ExperiarCore/RV32ICore.v
1: b'%Warning-WIDTH: data/full_repos/permissive/476477303/verilog/rtl/ExperiarCore/RV32ICore.v:103: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'management_registerIndex\' generates 5 bits.\n                                                                                             : ... In instance RV32ICore\n   management_readRegister: management_dataOut <= !management_registerIndex ? registers[management_registerIndex] : 32\'b0;\n                                                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/476477303/verilog/rtl/ExperiarCore/RV32ICore.v:124: Operator COND expects 33 bits on the Conditional True, but Conditional True\'s VARREF \'management_writeData\' generates 32 bits.\n                                                                                             : ... In instance RV32ICore\n wire[31:0] csrWriteData = !management_run ? management_writeData : coreCSRWriteData;\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/476477303/verilog/rtl/ExperiarCore/RV32ICore.v:124: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 33 bits.\n                                                                                             : ... In instance RV32ICore\n wire[31:0] csrWriteData = !management_run ? management_writeData : coreCSRWriteData;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/476477303/verilog/rtl/ExperiarCore/RV32ICore.v:292: Operator ASSIGNDLY expects 33 bits on the Assign RHS, but Assign RHS\'s VARREF \'csrRS1Data\' generates 32 bits.\n                                                                                             : ... In instance RV32ICore\n   if (isCSRRW) coreCSRWriteData <= csrRS1Data;\n                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/476477303/verilog/rtl/ExperiarCore/RV32ICore.v:293: Operator OR expects 33 bits on the LHS, but LHS\'s VARREF \'csrReadData\' generates 32 bits.\n                                                                                             : ... In instance RV32ICore\n   else if (isCSRRS) coreCSRWriteData <= csrReadData | csrRS1Data;\n                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/476477303/verilog/rtl/ExperiarCore/RV32ICore.v:293: Operator OR expects 33 bits on the RHS, but RHS\'s VARREF \'csrRS1Data\' generates 32 bits.\n                                                                                             : ... In instance RV32ICore\n   else if (isCSRRS) coreCSRWriteData <= csrReadData | csrRS1Data;\n                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/476477303/verilog/rtl/ExperiarCore/RV32ICore.v:294: Operator AND expects 33 bits on the LHS, but LHS\'s VARREF \'csrReadData\' generates 32 bits.\n                                                                                             : ... In instance RV32ICore\n   else if (isCSRRC) coreCSRWriteData <= csrReadData & ~csrRS1Data;\n                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/476477303/verilog/rtl/ExperiarCore/RV32ICore.v:294: Operator NOT expects 33 bits on the LHS, but LHS\'s VARREF \'csrRS1Data\' generates 32 bits.\n                                                                                             : ... In instance RV32ICore\n   else if (isCSRRC) coreCSRWriteData <= csrReadData & ~csrRS1Data;\n                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/476477303/verilog/rtl/ExperiarCore/RV32ICore.v:295: Operator ASSIGNDLY expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                                             : ... In instance RV32ICore\n   else coreCSRWriteData <= 32\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/476477303/verilog/rtl/ExperiarCore/RV32ICore.v:297: Operator ASSIGNDLY expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                                             : ... In instance RV32ICore\n   coreCSRWriteData <= 32\'b0;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/476477303/verilog/rtl/ExperiarCore/RV32ICore.v:453: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                             : ... In instance RV32ICore\n   currentError <= 4\'b0;\n                ^~\n%Error: data/full_repos/permissive/476477303/verilog/rtl/ExperiarCore/RV32ICore.v:518: Cannot find file containing module: \'CSR\'\n CSR csr(\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/476477303/verilog/rtl/ExperiarCore,data/full_repos/permissive/476477303/CSR\n             data/full_repos/permissive/476477303/verilog/rtl/ExperiarCore,data/full_repos/permissive/476477303/CSR.v\n             data/full_repos/permissive/476477303/verilog/rtl/ExperiarCore,data/full_repos/permissive/476477303/CSR.sv\n             CSR\n             CSR.v\n             CSR.sv\n             obj_dir/CSR\n             obj_dir/CSR.v\n             obj_dir/CSR.sv\n%Error: Exiting due to 1 error(s), 11 warning(s)\n'
function [31:0] flipBits32 (input [31:0] x);
		flipBits32 = { x[ 0], x[ 1], x[ 2], x[ 3], x[ 4], x[ 5], x[ 6], x[ 7], 
					   x[ 8], x[ 9], x[10], x[11], x[12], x[13], x[14], x[15], 
					   x[16], x[17], x[18], x[19], x[20], x[21], x[22], x[23],
					   x[24], x[25], x[26], x[27], x[28], x[29], x[30], x[31] };
	endfunction
function [31:0] flipBits32 (input [31:0] x);

		flipBits32 = { x[ 0], x[ 1], x[ 2], x[ 3], x[ 4], x[ 5], x[ 6], x[ 7], 
					   x[ 8], x[ 9], x[10], x[11], x[12], x[13], x[14], x[15], 
					   x[16], x[17], x[18], x[19], x[20], x[21], x[22], x[23],
					   x[24], x[25], x[26], x[27], x[28], x[29], x[30], x[31] };
	endfunction