data/full_repos/permissive/430026064/register_file.v
data/verilator_xmls/7db112ba-086e-4bb3-ab45-31e63df52f75.xml
module register_file (
    input wire clk,
	input wire reg_write_en,
    input wire [4:0] read_reg_1,
	input wire [4:0] read_reg_2,
	input wire [4:0] write_reg,
    input wire [31:0] write_data,
    output [31:0] read_data_1,
    output [31:0] read_data_2
);

    reg [31 : 0] mem [31 : 0];
	reg PC;

	integer i;
	initial begin
      for (i=0; i<32; i=i+1) begin
        mem[i] = i * 10;
		end
	end




  	always @(*) begin
       	if ((reg_write_en == 1) && (write_reg != 5'b00000)) begin 
          $display("Register %0d is written with value: %0d", write_reg, write_data);
          mem[write_reg] = write_data;
		end 
      	else if ((reg_write_en == 1) && (write_reg == 5'b00000)) begin
          $display("NOP instruction");
	  	end 
    end
	





  
	assign read_data_1 = mem[read_reg_1];
	assign read_data_2 = mem[read_reg_2];
	
endmodule
module register_file (
    input wire clk,
	input wire reg_write_en,
    input wire [4:0] read_reg_1,
	input wire [4:0] read_reg_2,
	input wire [4:0] write_reg,
    input wire [31:0] write_data,
    output [31:0] read_data_1,
    output [31:0] read_data_2
);


    reg [31 : 0] mem [31 : 0];
	reg PC;

	integer i;
	initial begin
      for (i=0; i<32; i=i+1) begin
        mem[i] = i * 10;
		end
	end




  	always @(*) begin
       	if ((reg_write_en == 1) && (write_reg != 5'b00000)) begin 
          $display("Register %0d is written with value: %0d", write_reg, write_data);
          mem[write_reg] = write_data;
		end 
      	else if ((reg_write_en == 1) && (write_reg == 5'b00000)) begin
          $display("NOP instruction");
	  	end 
    end
	





  
	assign read_data_1 = mem[read_reg_1];
	assign read_data_2 = mem[read_reg_2];
	
endmodule