data/full_repos/permissive/524307278/datapath/ifu.v
1: b'%Error: data/full_repos/permissive/524307278/datapath/ifu.v:12: syntax error, unexpected reg, expecting IDENTIFIER or do or final\n    reg [31:0] extout;\n    ^~~\n%Error: Exiting due to 1 error(s)\n'
module ifu(nPC_sel, zero, clk, rst, instruction);
    input clk, rst;
    input [1:0] nPC_sel;
    input [31:0] zero;
    output [31:0] instruction;

    reg [31:0] pc;
    reg [31:0] pcnew;
    reg [7:0]im[1023:0];
    wire [31:0] temp, t0, t1;
    wire [15:0]
    reg [31:0] extout;


    assign instruction = {im[pc[9:0]], im[pc[9:0]+1], im[pc[9:0]+2], im[pc[9:0]+3]};


    assign temp = {{16{imm16[15]}}, imm16};
    always@(*) begin
        extout = temp[31:0]<<2;
    end



    assign t0 = pc + 4;
    assign t1 = to + extout;

    always@(*)
    begin
        if (nPC_sel == 2'b00) begin
            pcnew = t0;
        end
        else if (nPC_sel == 2'b01) begin
            pcnew = t1;
        end
    end



    always@(posedge clk, posedge rst) 
    begin
        if(rst) pc = 32'h0000_3000;
        else pc = pcnew;
    end

endmodule
module ifu(nPC_sel, zero, clk, rst, instruction);

    input clk, rst;
    input [1:0] nPC_sel;
    input [31:0] zero;
    output [31:0] instruction;

    reg [31:0] pc;
    reg [31:0] pcnew;
    reg [7:0]im[1023:0];
    wire [31:0] temp, t0, t1;
    wire [15:0]
    reg [31:0] extout;


    assign instruction = {im[pc[9:0]], im[pc[9:0]+1], im[pc[9:0]+2], im[pc[9:0]+3]};


    assign temp = {{16{imm16[15]}}, imm16};
    always@(*) begin
        extout = temp[31:0]<<2;
    end



    assign t0 = pc + 4;
    assign t1 = to + extout;

    always@(*)
    begin
        if (nPC_sel == 2'b00) begin
            pcnew = t0;
        end
        else if (nPC_sel == 2'b01) begin
            pcnew = t1;
        end
    end



    always@(posedge clk, posedge rst) 
    begin
        if(rst) pc = 32'h0000_3000;
        else pc = pcnew;
    end

endmodule