data/full_repos/permissive/521337848/Hardware/GRAPHICS/Background.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/521337848/Hardware/GRAPHICS/Background.v:145: Multiple top level modules\n                                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                          : ... Top module \'bcgman\'\nmodule bcgman(\n       ^~~~~~\n                                                                                          : ... Top module \'paletteBcg\'\nmodule paletteBcg(\n       ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/GRAPHICS/Background.v:57: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'palette\' generates 4 bits.\n                                                                                      : ... In instance bcgman\n  f_palette <= palette;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/GRAPHICS/Background.v:72: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'f_palette\' generates 2 bits.\n                                                                                      : ... In instance bcgman\n palette = f_palette;\n         ^\n%Error: Exiting due to 3 warning(s)\n'
module paletteBcg(
	input clk,
	input rst,
	
	input[9:0] CounterX,
	input[8:0] CounterY,
	
	input[4:0] b1col1,
	input[4:0] b1col2,
	input[4:0] b1col3,
	input[4:0] b1col4,
	
	input[4:0] b2col1,
	input[4:0] b2col2,
	input[4:0] b2col3,
	input[4:0] b2col4,
	
	input[4:0] b3col1,
	input[4:0] b3col2,
	input[4:0] b3col3,
	input[4:0] b3col4,
	
	input[4:0] b4col1,
	input[4:0] b4col2,
	input[4:0] b4col3,
	input[4:0] b4col4,
	
	input[4:0] b5col1,
	input[4:0] b5col2,
	input[4:0] b5col3,
	input[4:0] b5col4,
	
	input[4:0] b6col1,
	input[4:0] b6col2,
	input[4:0] b6col3,
	input[4:0] b6col4,
	
	input[4:0] b7col1,
	input[4:0] b7col2,
	input[4:0] b7col3,
	input[4:0] b7col4,
	
	input[4:0] b8col1,
	input[4:0] b8col2,
	input[4:0] b8col3,
	input[4:0] b8col4,
	
	input[3:0] palette,
	
	input[1:0] col,
	
	output reg[4:0] pcol
	
);

always@(posedge clk)begin
	case(palette)
		0:	case(col)
				0: pcol <= b1col1;
				1: pcol <= b1col2;
				2: pcol <= b1col3;
				3: pcol <= b1col4;
			endcase
		1:	case(col)
				0: pcol <= b2col1;
				1: pcol <= b2col2;
				2: pcol <= b2col3;
				3: pcol <= b2col4;
			endcase
		2:	case(col)
				0: pcol <= b3col1;
				1: pcol <= b3col2;
				2: pcol <= b3col3;
				3: pcol <= b3col4;
			endcase
		3:	case(col)
				0: pcol <= b4col1;
				1: pcol <= b4col2;
				2: pcol <= b4col3;
				3: pcol <= b4col4;
			endcase
		4:	case(col)
				0: pcol <= b5col1;
				1: pcol <= b5col2;
				2: pcol <= b5col3;
				3: pcol <= b5col4;
			endcase
		5:	case(col)
				0: pcol <= b6col1;
				1: pcol <= b6col2;
				2: pcol <= b6col3;
				3: pcol <= b6col4;
			endcase
		6:	case(col)
				0: pcol <= b7col1;
				1: pcol <= b7col2;
				2: pcol <= b7col3;
				3: pcol <= b7col4;
			endcase
		7:	case(col)
				0: pcol <= b8col1;
				1: pcol <= b8col2;
				2: pcol <= b8col3;
				3: pcol <= b8col4;
			endcase
		default:;
		endcase
end

endmodule
module paletteBcg(
	input clk,
	input rst,
	
	input[9:0] CounterX,
	input[8:0] CounterY,
	
	input[4:0] b1col1,
	input[4:0] b1col2,
	input[4:0] b1col3,
	input[4:0] b1col4,
	
	input[4:0] b2col1,
	input[4:0] b2col2,
	input[4:0] b2col3,
	input[4:0] b2col4,
	
	input[4:0] b3col1,
	input[4:0] b3col2,
	input[4:0] b3col3,
	input[4:0] b3col4,
	
	input[4:0] b4col1,
	input[4:0] b4col2,
	input[4:0] b4col3,
	input[4:0] b4col4,
	
	input[4:0] b5col1,
	input[4:0] b5col2,
	input[4:0] b5col3,
	input[4:0] b5col4,
	
	input[4:0] b6col1,
	input[4:0] b6col2,
	input[4:0] b6col3,
	input[4:0] b6col4,
	
	input[4:0] b7col1,
	input[4:0] b7col2,
	input[4:0] b7col3,
	input[4:0] b7col4,
	
	input[4:0] b8col1,
	input[4:0] b8col2,
	input[4:0] b8col3,
	input[4:0] b8col4,
	
	input[3:0] palette,
	
	input[1:0] col,
	
	output reg[4:0] pcol
	
);


always@(posedge clk)begin
	case(palette)
		0:	case(col)
				0: pcol <= b1col1;
				1: pcol <= b1col2;
				2: pcol <= b1col3;
				3: pcol <= b1col4;
			endcase
		1:	case(col)
				0: pcol <= b2col1;
				1: pcol <= b2col2;
				2: pcol <= b2col3;
				3: pcol <= b2col4;
			endcase
		2:	case(col)
				0: pcol <= b3col1;
				1: pcol <= b3col2;
				2: pcol <= b3col3;
				3: pcol <= b3col4;
			endcase
		3:	case(col)
				0: pcol <= b4col1;
				1: pcol <= b4col2;
				2: pcol <= b4col3;
				3: pcol <= b4col4;
			endcase
		4:	case(col)
				0: pcol <= b5col1;
				1: pcol <= b5col2;
				2: pcol <= b5col3;
				3: pcol <= b5col4;
			endcase
		5:	case(col)
				0: pcol <= b6col1;
				1: pcol <= b6col2;
				2: pcol <= b6col3;
				3: pcol <= b6col4;
			endcase
		6:	case(col)
				0: pcol <= b7col1;
				1: pcol <= b7col2;
				2: pcol <= b7col3;
				3: pcol <= b7col4;
			endcase
		7:	case(col)
				0: pcol <= b8col1;
				1: pcol <= b8col2;
				2: pcol <= b8col3;
				3: pcol <= b8col4;
			endcase
		default:;
		endcase
end

endmodule