data/full_repos/permissive/460468583/data/yosys/nexus/cells_sim.v
1: b'%Error: data/full_repos/permissive/460468583/data/yosys/nexus/cells_sim.v:4: Cannot find include file: parse_init.vh\n`include "parse_init.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/460468583/data/yosys/nexus,data/full_repos/permissive/460468583/parse_init.vh\n             data/full_repos/permissive/460468583/data/yosys/nexus,data/full_repos/permissive/460468583/parse_init.vh.v\n             data/full_repos/permissive/460468583/data/yosys/nexus,data/full_repos/permissive/460468583/parse_init.vh.sv\n             parse_init.vh\n             parse_init.vh.v\n             parse_init.vh.sv\n             obj_dir/parse_init.vh\n             obj_dir/parse_init.vh.v\n             obj_dir/parse_init.vh.sv\n%Error: data/full_repos/permissive/460468583/data/yosys/nexus/cells_sim.v:182: Cannot find include file: parse_init.vh\n`include "parse_init.vh" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/nexus/cells_sim.v:365: Cannot find include file: parse_init.vh\n`include "parse_init.vh" \n         ^~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module DPR16X4(
	input [3:0] RAD, DI, WAD,
	input WRE, WCK,
	output [3:0] DO
);
	parameter INITVAL = "0x0000000000000000";
`include "parse_init.vh"
	localparam [63:0] parsed_init = parse_init_64(INITVAL);

	reg [3:0] mem[0:15];
	integer i;
	initial begin
		for (i = 0; i < 15; i++)
			mem[i] = parsed_init[i * 4 +: 4];
	end

	always @(posedge WCK)
		if (WRE)
			mem[WAD] <= DI;
	assign DO = mem[RAD];
endmodule
module DPR16X4(
	input [3:0] RAD, DI, WAD,
	input WRE, WCK,
	output [3:0] DO
);

	parameter INITVAL = "0x0000000000000000";
`include "parse_init.vh"
	localparam [63:0] parsed_init = parse_init_64(INITVAL);

	reg [3:0] mem[0:15];
	integer i;
	initial begin
		for (i = 0; i < 15; i++)
			mem[i] = parsed_init[i * 4 +: 4];
	end

	always @(posedge WCK)
		if (WRE)
			mem[WAD] <= DI;
	assign DO = mem[RAD];
endmodule