data/full_repos/permissive/491135068/DFF32.v
data/verilator_xmls/18b806b6-e3bf-4137-bded-56307f6b7cf1.xml
module DFF32(DFFIN32, DFFOUT32, clk);
    input [31:0] DFFIN32;
    input clk;
    output reg [31:0] DFFOUT32;
     
    always @(posedge clk) begin
        DFFOUT32 = DFFIN32;
    end
endmodule
module DFF32(DFFIN32, DFFOUT32, clk);

    input [31:0] DFFIN32;
    input clk;
    output reg [31:0] DFFOUT32;
     
    always @(posedge clk) begin
        DFFOUT32 = DFFIN32;
    end
endmodule