data/full_repos/permissive/491135068/PC_pipe.v
data/verilator_xmls/b3e36d25-696f-48e7-8597-f18edefeed8b.xml
module PC_pipe(
    input [31:0] branchIn,
    output reg [31:0] val,
    input clk, rst
    );
    
    always@(posedge clk) begin
        if(rst)
            val = 32'b0;
        else
            val = branchIn;
    end
    
endmodule
module PC_pipe(
    input [31:0] branchIn,
    output reg [31:0] val,
    input clk, rst
    );

    
    always@(posedge clk) begin
        if(rst)
            val = 32'b0;
        else
            val = branchIn;
    end
    
endmodule