data/full_repos/permissive/514217463/d_flip_flop.v
data/verilator_xmls/a35c0b66-2a83-4f91-b516-74c4895b77ed.xml
module d_flip_flop (
  input clk, 
  input reset,
  input [DATA_WIDTH-1:0] d, 
  output reg [DATA_WIDTH-1:0] q);
  
  parameter DATA_WIDTH = 1;
  

  always @(posedge clk or posedge reset)
  begin
    if (reset) begin
      q = 0;
    end else begin
      q = d;
    end
  end
endmodule
module d_flip_flop (
  input clk, 
  input reset,
  input [DATA_WIDTH-1:0] d, 
  output reg [DATA_WIDTH-1:0] q);

  
  parameter DATA_WIDTH = 1;
  

  always @(posedge clk or posedge reset)
  begin
    if (reset) begin
      q = 0;
    end else begin
      q = d;
    end
  end
endmodule