data/full_repos/permissive/468066752/rtl/VGA.sv
1: b'%Error: data/full_repos/permissive/468066752/rtl/VGA.sv:67: Cannot find file containing module: \'pll\'\n  pll vga_pll_u0 (\n  ^~~\n        ... Looked in:\n             data/full_repos/permissive/468066752/rtl,data/full_repos/permissive/468066752/pll\n             data/full_repos/permissive/468066752/rtl,data/full_repos/permissive/468066752/pll.v\n             data/full_repos/permissive/468066752/rtl,data/full_repos/permissive/468066752/pll.sv\n             pll\n             pll.v\n             pll.sv\n             obj_dir/pll\n             obj_dir/pll.v\n             obj_dir/pll.sv\n%Error: data/full_repos/permissive/468066752/rtl/VGA.sv:73: Cannot find file containing module: \'sram\'\n  sram vga_sram  (\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/468066752/rtl/VGA.sv:103: Operator ASSIGNDLY expects 20 bits on the Assign RHS, but Assign RHS\'s SEL generates 16 bits.\n                                                                   : ... In instance VGA\n        sram_local_address <= ADDR[15:00];\n                           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/468066752/rtl/VGA.sv:120: Operator GTE expects 32 bits on the LHS, but LHS\'s VARREF \'h_pixel_counter\' generates 10 bits.\n                                                                   : ... In instance VGA\n      VGA_HS      <= ~((h_pixel_counter >= (WidthPixels + HFrontPorch)) &&\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/468066752/rtl/VGA.sv:121: Operator LT expects 32 bits on the LHS, but LHS\'s VARREF \'h_pixel_counter\' generates 10 bits.\n                                                                   : ... In instance VGA\n                         (h_pixel_counter < (WidthPixels + HFrontPorch + HSyncPulse)));\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/468066752/rtl/VGA.sv:122: Operator GTE expects 32 bits on the LHS, but LHS\'s VARREF \'v_pixel_counter\' generates 10 bits.\n                                                                   : ... In instance VGA\n      VGA_VS      <= ~((v_pixel_counter >= (HeightPixels + VFrontPorch)) &&\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/468066752/rtl/VGA.sv:123: Operator LT expects 32 bits on the LHS, but LHS\'s VARREF \'v_pixel_counter\' generates 10 bits.\n                                                                   : ... In instance VGA\n                         (v_pixel_counter < (HeightPixels + VFrontPorch + VSyncPulse)));\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/468066752/rtl/VGA.sv:124: Operator LT expects 32 bits on the LHS, but LHS\'s VARREF \'h_pixel_counter\' generates 10 bits.\n                                                                   : ... In instance VGA\n      displayTime <= (h_pixel_counter < WidthPixels) && (v_pixel_counter < HeightPixels);\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/468066752/rtl/VGA.sv:124: Operator LT expects 32 bits on the LHS, but LHS\'s VARREF \'v_pixel_counter\' generates 10 bits.\n                                                                   : ... In instance VGA\n      displayTime <= (h_pixel_counter < WidthPixels) && (v_pixel_counter < HeightPixels);\n                                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/468066752/rtl/VGA.sv:138: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'v_pixel_counter\' generates 10 bits.\n                                                                   : ... In instance VGA\n        if (v_pixel_counter == WholeFrame) begin\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/468066752/rtl/VGA.sv:135: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'h_pixel_counter\' generates 10 bits.\n                                                                   : ... In instance VGA\n      if (h_pixel_counter == WholeLine) begin\n                          ^~\n%Warning-WIDTH: data/full_repos/permissive/468066752/rtl/VGA.sv:155: Operator ADD expects 20 bits on the RHS, but RHS\'s CONST \'16\'h1\' generates 16 bits.\n                                                                   : ... In instance VGA\n        lADDR <= lADDR + 16\'d1;\n                       ^\n%Error: Exiting due to 2 error(s), 10 warning(s)\n'
module VGA #(
  parameter int WidthPixels  = 640,
  parameter int HFrontPorch  = 16,
  parameter int HSyncPulse   = 96,
  parameter int HBackPorch   = 48,
  parameter int HeightPixels = 480,
  parameter int VFrontPorch  = 10,
  parameter int VSyncPulse   = 2,
  parameter int VBackPorch   = 33,
  parameter int BASEADDRESS  = 32'h4000_0000

)(
  input       logic         ACLK,
  input       logic         RESET,
  input       logic [31:00] DATA_I,
  input       logic [31:00] ADDR,
  input       logic         WRSTB,
  output      logic         VGA_HS,
  output      logic         VGA_VS,
  output      logic         VGA_CLK,
  output      logic         VGA_BLANK_N,
  output      logic         VGA_SYNC_N,
  output      logic [07:00] RED,
  output      logic [07:00] GREEN,
  output      logic [07:00] BLUE,

  output      logic [19:00] SRAM_ADDR,
  output      logic         SRAM_CE_N,
  inout  wire logic [15:00] SRAM_DQ,
  output      logic         SRAM_LB_N,
  output      logic         SRAM_OE_N,
  output      logic         SRAM_UB_N,
  output      logic         SRAM_WE_N
);

  localparam int WholeLine = WidthPixels + HFrontPorch + HSyncPulse + HBackPorch;
  localparam int WholeFrame = HeightPixels + VFrontPorch + VSyncPulse + VBackPorch;
  logic [19:00] lADDR;


  logic [19:00] sram_local_address;
  logic [15:00] sram_din;
  logic [15:00] sram_dout;
  logic [01:00] sram_byteenable;
  logic         sram_read;
  logic 			 sram_write;
  logic         sram_dout_valid;

  logic pixel_clk;
  logic displayTime;
  logic [$clog2(WholeLine)-1:0] h_pixel_counter;
  logic [$clog2(WholeFrame)-1:0] v_pixel_counter;
 
  assign sram_byteenable    = 2'd3;

  assign VGA_CLK     = pixel_clk;
  assign VGA_SYNC_N  = displayTime;
  assign VGA_BLANK_N = displayTime;

  assign RED         = (sram_dout_valid) ? {sram_dout[04:00], 3'd0} : 8'd0;
  assign GREEN       = (sram_dout_valid) ? {sram_dout[09:05], 3'd0} : 8'd0;
  assign BLUE        = (sram_dout_valid) ? {sram_dout[14:10], 3'd0} : 8'd0;

  pll vga_pll_u0 (
    .reset_reset(RESET),
    .clk_clk(ACLK),
    .c0_clk(pixel_clk)
  );

  sram vga_sram  (
    .clk_clk               (ACLK),
    .reset_reset           (RESET),
    .sram_DQ               (SRAM_DQ),
    .sram_ADDR             (SRAM_ADDR),
    .sram_LB_N             (SRAM_LB_N),
    .sram_UB_N             (SRAM_UB_N),
    .sram_CE_N             (SRAM_CE_N),
    .sram_OE_N             (SRAM_OE_N),
    .sram_WE_N             (SRAM_WE_N),
    .sram_io_address       (sram_local_address),
    .sram_io_byteenable    (sram_byteenable),
    .sram_io_read          (sram_read),
    .sram_io_write         (sram_write),
    .sram_io_writedata     (sram_din),
    .sram_io_readdata      (sram_dout),
    .sram_io_readdatavalid (sram_dout_valid)
  );


  always_ff @(posedge ACLK or posedge RESET) begin : driveSRAM
    if (RESET == 1'b1) begin
      sram_write         <= 'd0;
      sram_din           <= 'd0;
      sram_local_address <= 'd0;
      sram_read          <= 'd0;
    end
    else begin
      if (WRSTB && (ADDR >= BASEADDRESS) && (ADDR <= BASEADDRESS + (WidthPixels + HeightPixels))) begin
        sram_write         <= 1'b1;
        sram_local_address <= ADDR[15:00];
      end
      else begin
        sram_local_address <= lADDR;
        sram_read          <= displayTime;
      end    
      sram_din    <= DATA_I[15:00];
    end
  end: driveSRAM

  always_ff @(posedge pixel_clk or posedge RESET) begin : driveSyncs
    if (RESET == 1'b1) begin
      VGA_HS       <= 'd0;
      VGA_VS       <= 'd0;
      displayTime  <= 'd0;
    end
    else begin
      VGA_HS      <= ~((h_pixel_counter >= (WidthPixels + HFrontPorch)) &&
                         (h_pixel_counter < (WidthPixels + HFrontPorch + HSyncPulse)));
      VGA_VS      <= ~((v_pixel_counter >= (HeightPixels + VFrontPorch)) &&
                         (v_pixel_counter < (HeightPixels + VFrontPorch + VSyncPulse)));
      displayTime <= (h_pixel_counter < WidthPixels) && (v_pixel_counter < HeightPixels);
    end
  end : driveSyncs


  always_ff @(posedge pixel_clk or posedge RESET) begin : updateCounters
    if (RESET == 1'b1) begin
      h_pixel_counter <= 'd0;
      v_pixel_counter <= 'd0;
    end
    else begin
      if (h_pixel_counter == WholeLine) begin
        h_pixel_counter <= 'd0;
        v_pixel_counter <= v_pixel_counter + 9'd1;
        if (v_pixel_counter == WholeFrame) begin
          v_pixel_counter <= 'd0;
        end
      end
      else begin
        h_pixel_counter <= h_pixel_counter + 10'd1;
      end
    end
  end : updateCounters


  always_ff @(posedge pixel_clk or posedge RESET) begin : updateReadAddress
    if (RESET == 1'b1) begin
     lADDR <= 'd0;
   end
   else begin
     if (displayTime == 1'b1) begin
        lADDR <= lADDR + 16'd1;
      end
   end
  end : updateReadAddress

endmodule
module VGA #(
  parameter int WidthPixels  = 640,
  parameter int HFrontPorch  = 16,
  parameter int HSyncPulse   = 96,
  parameter int HBackPorch   = 48,
  parameter int HeightPixels = 480,
  parameter int VFrontPorch  = 10,
  parameter int VSyncPulse   = 2,
  parameter int VBackPorch   = 33,
  parameter int BASEADDRESS  = 32'h4000_0000

)(
  input       logic         ACLK,
  input       logic         RESET,
  input       logic [31:00] DATA_I,
  input       logic [31:00] ADDR,
  input       logic         WRSTB,
  output      logic         VGA_HS,
  output      logic         VGA_VS,
  output      logic         VGA_CLK,
  output      logic         VGA_BLANK_N,
  output      logic         VGA_SYNC_N,
  output      logic [07:00] RED,
  output      logic [07:00] GREEN,
  output      logic [07:00] BLUE,

  output      logic [19:00] SRAM_ADDR,
  output      logic         SRAM_CE_N,
  inout  wire logic [15:00] SRAM_DQ,
  output      logic         SRAM_LB_N,
  output      logic         SRAM_OE_N,
  output      logic         SRAM_UB_N,
  output      logic         SRAM_WE_N
);


  localparam int WholeLine = WidthPixels + HFrontPorch + HSyncPulse + HBackPorch;
  localparam int WholeFrame = HeightPixels + VFrontPorch + VSyncPulse + VBackPorch;
  logic [19:00] lADDR;


  logic [19:00] sram_local_address;
  logic [15:00] sram_din;
  logic [15:00] sram_dout;
  logic [01:00] sram_byteenable;
  logic         sram_read;
  logic 			 sram_write;
  logic         sram_dout_valid;

  logic pixel_clk;
  logic displayTime;
  logic [$clog2(WholeLine)-1:0] h_pixel_counter;
  logic [$clog2(WholeFrame)-1:0] v_pixel_counter;
 
  assign sram_byteenable    = 2'd3;

  assign VGA_CLK     = pixel_clk;
  assign VGA_SYNC_N  = displayTime;
  assign VGA_BLANK_N = displayTime;

  assign RED         = (sram_dout_valid) ? {sram_dout[04:00], 3'd0} : 8'd0;
  assign GREEN       = (sram_dout_valid) ? {sram_dout[09:05], 3'd0} : 8'd0;
  assign BLUE        = (sram_dout_valid) ? {sram_dout[14:10], 3'd0} : 8'd0;

  pll vga_pll_u0 (
    .reset_reset(RESET),
    .clk_clk(ACLK),
    .c0_clk(pixel_clk)
  );

  sram vga_sram  (
    .clk_clk               (ACLK),
    .reset_reset           (RESET),
    .sram_DQ               (SRAM_DQ),
    .sram_ADDR             (SRAM_ADDR),
    .sram_LB_N             (SRAM_LB_N),
    .sram_UB_N             (SRAM_UB_N),
    .sram_CE_N             (SRAM_CE_N),
    .sram_OE_N             (SRAM_OE_N),
    .sram_WE_N             (SRAM_WE_N),
    .sram_io_address       (sram_local_address),
    .sram_io_byteenable    (sram_byteenable),
    .sram_io_read          (sram_read),
    .sram_io_write         (sram_write),
    .sram_io_writedata     (sram_din),
    .sram_io_readdata      (sram_dout),
    .sram_io_readdatavalid (sram_dout_valid)
  );


  always_ff @(posedge ACLK or posedge RESET) begin : driveSRAM
    if (RESET == 1'b1) begin
      sram_write         <= 'd0;
      sram_din           <= 'd0;
      sram_local_address <= 'd0;
      sram_read          <= 'd0;
    end
    else begin
      if (WRSTB && (ADDR >= BASEADDRESS) && (ADDR <= BASEADDRESS + (WidthPixels + HeightPixels))) begin
        sram_write         <= 1'b1;
        sram_local_address <= ADDR[15:00];
      end
      else begin
        sram_local_address <= lADDR;
        sram_read          <= displayTime;
      end    
      sram_din    <= DATA_I[15:00];
    end
  end: driveSRAM

  always_ff @(posedge pixel_clk or posedge RESET) begin : driveSyncs
    if (RESET == 1'b1) begin
      VGA_HS       <= 'd0;
      VGA_VS       <= 'd0;
      displayTime  <= 'd0;
    end
    else begin
      VGA_HS      <= ~((h_pixel_counter >= (WidthPixels + HFrontPorch)) &&
                         (h_pixel_counter < (WidthPixels + HFrontPorch + HSyncPulse)));
      VGA_VS      <= ~((v_pixel_counter >= (HeightPixels + VFrontPorch)) &&
                         (v_pixel_counter < (HeightPixels + VFrontPorch + VSyncPulse)));
      displayTime <= (h_pixel_counter < WidthPixels) && (v_pixel_counter < HeightPixels);
    end
  end : driveSyncs


  always_ff @(posedge pixel_clk or posedge RESET) begin : updateCounters
    if (RESET == 1'b1) begin
      h_pixel_counter <= 'd0;
      v_pixel_counter <= 'd0;
    end
    else begin
      if (h_pixel_counter == WholeLine) begin
        h_pixel_counter <= 'd0;
        v_pixel_counter <= v_pixel_counter + 9'd1;
        if (v_pixel_counter == WholeFrame) begin
          v_pixel_counter <= 'd0;
        end
      end
      else begin
        h_pixel_counter <= h_pixel_counter + 10'd1;
      end
    end
  end : updateCounters


  always_ff @(posedge pixel_clk or posedge RESET) begin : updateReadAddress
    if (RESET == 1'b1) begin
     lADDR <= 'd0;
   end
   else begin
     if (displayTime == 1'b1) begin
        lADDR <= lADDR + 16'd1;
      end
   end
  end : updateReadAddress

endmodule