data/full_repos/permissive/450962776/processor/src/test_bench_Instruction_memory.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/450962776/processor/src/test_bench_Instruction_memory.v:10: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/450962776/processor/src/test_bench_Instruction_memory.v:12: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Error: data/full_repos/permissive/450962776/processor/src/test_bench_Instruction_memory.v:15: Unsupported or unknown PLI call: $monitor\n$monitor(",pc=%5b,instruction=%16b",pc,instruction);\n^~~~~~~~\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_bench_Instruction_memory();

reg [4:0]pc;
wire [15:0]instruction;
Instruction_Memory ahmet(pc,instruction);
initial begin
	$readmemb("instruction.txt",ahmet.memory);
	pc=5'b00001;
	#`DELAY;
	pc=5'b00011;
	#`DELAY;
end
initial begin
$monitor(",pc=%5b,instruction=%16b",pc,instruction);
end
endmodule
module test_bench_Instruction_memory();


reg [4:0]pc;
wire [15:0]instruction;
Instruction_Memory ahmet(pc,instruction);
initial begin
	$readmemb("instruction.txt",ahmet.memory);
	pc=5'b00001;
	#`DELAY;
	pc=5'b00011;
	#`DELAY;
end
initial begin
$monitor(",pc=%5b,instruction=%16b",pc,instruction);
end
endmodule