data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_jp_bs_baseblk.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_jp_bs_baseblk.v:38: Cannot find file containing module: 'bw_u1_soff_2x'\nbw_u1_soff_2x bsff (\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_soff_2x\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_soff_2x.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_soff_2x.sv\n             bw_u1_soff_2x\n             bw_u1_soff_2x.v\n             bw_u1_soff_2x.sv\n             obj_dir/bw_u1_soff_2x\n             obj_dir/bw_u1_soff_2x.v\n             obj_dir/bw_u1_soff_2x.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_jp_bs_baseblk.v:45: Cannot find file containing module: 'bw_u1_inv_1x'\nbw_u1_inv_1x ud_inv1x (\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_jp_bs_baseblk.v:48: Cannot find file containing module: 'bw_u1_inv_4x'\nbw_u1_inv_4x so_inv4x (\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_jp_bs_baseblk.v:51: Cannot find file containing module: 'bw_u1_inv_1x'\nbw_u1_inv_1x so_inv2x (\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_jp_bs_baseblk.v:54: Cannot find file containing module: 'bw_u1_scanlg_2x'\nbw_u1_scanlg_2x latch_bsrc (\n^~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module bw_io_jp_bs_baseblk(upd_q ,bsr_si ,update_dr ,clock_dr ,shift_dr
      ,bsr_so ,in );
output		upd_q ;
output		bsr_so ;
input		bsr_si ;
input		update_dr ;
input		clock_dr ;
input		shift_dr ;
input		in ;
supply1		vdd ;
 
wire		net73 ;
wire		qn ;
wire		net032 ;
wire		net037 ;
 
 
bw_u1_soff_2x bsff (
     .q               (qn ),
     .so              (net73 ),
     .ck              (clock_dr ),
     .d               (in ),
     .se              (shift_dr ),
     .sd              (bsr_si ) );
bw_u1_inv_1x ud_inv1x (
     .z               (net032 ),
     .a               (update_dr ) );
bw_u1_inv_4x so_inv4x (
     .z               (bsr_so ),
     .a               (net037 ) );
bw_u1_inv_1x so_inv2x (
     .z               (net037 ),
     .a               (qn ) );
bw_u1_scanlg_2x latch_bsrc (
     .so              (upd_q ),
     .sd              (qn ),
     .ck              (net032 ),
     .se              (vdd ) );
endmodule
module bw_io_jp_bs_baseblk(upd_q ,bsr_si ,update_dr ,clock_dr ,shift_dr
      ,bsr_so ,in );

output		upd_q ;
output		bsr_so ;
input		bsr_si ;
input		update_dr ;
input		clock_dr ;
input		shift_dr ;
input		in ;
supply1		vdd ;
 
wire		net73 ;
wire		qn ;
wire		net032 ;
wire		net037 ;
 
 
bw_u1_soff_2x bsff (
     .q               (qn ),
     .so              (net73 ),
     .ck              (clock_dr ),
     .d               (in ),
     .se              (shift_dr ),
     .sd              (bsr_si ) );
bw_u1_inv_1x ud_inv1x (
     .z               (net032 ),
     .a               (update_dr ) );
bw_u1_inv_4x so_inv4x (
     .z               (bsr_so ),
     .a               (net037 ) );
bw_u1_inv_1x so_inv2x (
     .z               (net037 ),
     .a               (qn ) );
bw_u1_scanlg_2x latch_bsrc (
     .so              (upd_q ),
     .sd              (qn ),
     .ck              (net032 ),
     .se              (vdd ) );
endmodule