data/full_repos/permissive/489980666/old_ip/axi4_dv/axi4/uvm/axi4_subscriber.sv
1: b'%Error: data/full_repos/permissive/489980666/old_ip/axi4_dv/axi4/uvm/axi4_subscriber.sv:1: Unsupported: classes\nclass axi4_subscriber extends uvm_subscriber#(axi4_transaction);\n^~~~~\n%Error: data/full_repos/permissive/489980666/old_ip/axi4_dv/axi4/uvm/axi4_subscriber.sv:1: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass axi4_subscriber extends uvm_subscriber#(axi4_transaction);\n                              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/old_ip/axi4_dv/axi4/uvm/axi4_subscriber.sv:2: Define or directive not defined: \'`uvm_component_utils\'\n  `uvm_component_utils(axi4_subscriber)\n  ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/old_ip/axi4_dv/axi4/uvm/axi4_subscriber.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: \'covergroup\'\n  covergroup cover_bus;\n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/old_ip/axi4_dv/axi4/uvm/axi4_subscriber.sv:7: syntax error, unexpected IDENTIFIER\n  covergroup cover_bus;\n             ^~~~~~~~~\n%Error: data/full_repos/permissive/489980666/old_ip/axi4_dv/axi4/uvm/axi4_subscriber.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: \'coverpoint\'\n    coverpoint addr {\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/old_ip/axi4_dv/axi4/uvm/axi4_subscriber.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n      bins a[16] = {[0:255]};\n      ^~~~\n%Error: data/full_repos/permissive/489980666/old_ip/axi4_dv/axi4/uvm/axi4_subscriber.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: \'coverpoint\'\n    coverpoint data {\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/489980666/old_ip/axi4_dv/axi4/uvm/axi4_subscriber.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n      bins d[16] = {[0:255]};\n      ^~~~\n%Error: data/full_repos/permissive/489980666/old_ip/axi4_dv/axi4/uvm/axi4_subscriber.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: \'endgroup\'\n  endgroup\n  ^~~~~~~~\n%Error: data/full_repos/permissive/489980666/old_ip/axi4_dv/axi4/uvm/axi4_subscriber.sv:16: Unsupported: new constructor\n  function new(string name, uvm_component parent);\n           ^~~\n%Error: data/full_repos/permissive/489980666/old_ip/axi4_dv/axi4/uvm/axi4_subscriber.sv:16: syntax error, unexpected IDENTIFIER, expecting \')\'\n  function new(string name, uvm_component parent);\n                                          ^~~~~~\n%Error: data/full_repos/permissive/489980666/old_ip/axi4_dv/axi4/uvm/axi4_subscriber.sv:21: syntax error, unexpected IDENTIFIER, expecting \')\'\n  function void write(axi4_transaction t);\n                                       ^\n%Error: data/full_repos/permissive/489980666/old_ip/axi4_dv/axi4/uvm/axi4_subscriber.sv:22: Define or directive not defined: \'`uvm_info\'\n    `uvm_info("[axi4_subscriber]", $sformatf("Subscriber received tx %s", t.convert2string()), UVM_NONE);\n    ^~~~~~~~~\n%Error: Exiting due to 14 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
function new(string name, uvm_component parent);
    super.new(name,parent);
    cover_bus=new;
  endfunction
function new(string name, uvm_component parent);

    super.new(name,parent);
    cover_bus=new;
  endfunction