data/full_repos/permissive/405799749/amg_new2/adder/FSA_16_64_Carry_select_adder.v
data/verilator_xmls/a1e22f4f-1bee-4d86-a007-eae88622d5c2.xml
module UBRCB_55_46 (Co, S, X, Y, Ci);
  output Co;
  output [55:46] S;
  input Ci;
  input [55:46] X;
  input [55:46] Y;
  wire C47;
  wire C48;
  wire C49;
  wire C50;
  wire C51;
  wire C52;
  wire C53;
  wire C54;
  wire C55;
  UBFA_46 U0 (C47, S[46], X[46], Y[46], Ci);
  UBFA_47 U1 (C48, S[47], X[47], Y[47], C47);
  UBFA_48 U2 (C49, S[48], X[48], Y[48], C48);
  UBFA_49 U3 (C50, S[49], X[49], Y[49], C49);
  UBFA_50 U4 (C51, S[50], X[50], Y[50], C50);
  UBFA_51 U5 (C52, S[51], X[51], Y[51], C51);
  UBFA_52 U6 (C53, S[52], X[52], Y[52], C52);
  UBFA_53 U7 (C54, S[53], X[53], Y[53], C53);
  UBFA_54 U8 (C55, S[54], X[54], Y[54], C54);
  UBFA_55 U9 (Co, S[55], X[55], Y[55], C55);
endmodule
module UBRCB_55_46 (Co, S, X, Y, Ci);

  output Co;
  output [55:46] S;
  input Ci;
  input [55:46] X;
  input [55:46] Y;
  wire C47;
  wire C48;
  wire C49;
  wire C50;
  wire C51;
  wire C52;
  wire C53;
  wire C54;
  wire C55;
  UBFA_46 U0 (C47, S[46], X[46], Y[46], Ci);
  UBFA_47 U1 (C48, S[47], X[47], Y[47], C47);
  UBFA_48 U2 (C49, S[48], X[48], Y[48], C48);
  UBFA_49 U3 (C50, S[49], X[49], Y[49], C49);
  UBFA_50 U4 (C51, S[50], X[50], Y[50], C50);
  UBFA_51 U5 (C52, S[51], X[51], Y[51], C51);
  UBFA_52 U6 (C53, S[52], X[52], Y[52], C52);
  UBFA_53 U7 (C54, S[53], X[53], Y[53], C53);
  UBFA_54 U8 (C55, S[54], X[54], Y[54], C54);
  UBFA_55 U9 (Co, S[55], X[55], Y[55], C55);
endmodule