data/full_repos/permissive/530250155/verilog/rtl/toysram/wrapper/10T_32x32_magic_flattened.v
data/verilator_xmls/1463d0c4-4f59-422c-ab1c-56610473f839.xml
module \10T_32x32_magic_flattened (
   input VDD, GND,












   input clk,
   output [31:0] rd_dat_0
);
endmodule
module \10T_32x32_magic_flattened (
   input VDD, GND,












   input clk,
   output [31:0] rd_dat_0
);

endmodule