data/full_repos/permissive/488739248/rtl/ttl/ttl_74138_nodly.v
1: b'%Warning-WIDTH: data/full_repos/permissive/488739248/rtl/ttl/ttl_74138_nodly.v:22: Operator EQ expects 32 bits on the RHS, but RHS\'s VARREF \'A\' generates 3 bits.\n                                                                                 : ... In instance ttl_74138_nodly\n    if (!Enable1_bar && !Enable2_bar && Enable3 && i == A)\n                                                     ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module ttl_74138_nodly #(parameter WIDTH_OUT = 8, WIDTH_IN = $clog2(WIDTH_OUT))
(
  input wire Enable1_bar,
  input wire Enable2_bar,
  input wire Enable3,
  input wire [WIDTH_IN-1:0] A,
  output wire [WIDTH_OUT-1:0] Y
);


reg [WIDTH_OUT-1:0] computed;
integer i;

always @(*)
begin
  for (i = 0; i < WIDTH_OUT; i=i+1)
  begin
    if (!Enable1_bar && !Enable2_bar && Enable3 && i == A)
      computed[i] = 1'b0;
    else
      computed[i] = 1'b1;
  end
end


assign Y = computed;

endmodule
module ttl_74138_nodly #(parameter WIDTH_OUT = 8, WIDTH_IN = $clog2(WIDTH_OUT))
(
  input wire Enable1_bar,
  input wire Enable2_bar,
  input wire Enable3,
  input wire [WIDTH_IN-1:0] A,
  output wire [WIDTH_OUT-1:0] Y
);



reg [WIDTH_OUT-1:0] computed;
integer i;

always @(*)
begin
  for (i = 0; i < WIDTH_OUT; i=i+1)
  begin
    if (!Enable1_bar && !Enable2_bar && Enable3 && i == A)
      computed[i] = 1'b0;
    else
      computed[i] = 1'b1;
  end
end


assign Y = computed;

endmodule