data/full_repos/permissive/412289941/add_b.v
1: b'%Warning-WIDTH: data/full_repos/permissive/412289941/add_b.v:46: Operator MODDIV expects 32 or 2 bits on the LHS, but LHS\'s VARREF \'counter1\' generates 1 bits.\n                                                               : ... In instance add_b\nassign data_out = (counter1%2 == 0) && (counterv == 1)? 2\'b10 : buffer[3];\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module add_b(rst,data_in,data_out,clk);

input clk,rst;
input [1:0]data_in;
output [1:0]data_out;
reg counter1;
reg counterv;
reg [1:0]buffer[3:0];

always@(posedge clk or negedge rst) begin

    if(!rst) begin
        buffer[3]<=0;
        buffer[2]<=0;
        buffer[1]<=0;
        buffer[0]<=0;
    end
    else begin
        buffer[3]<=buffer[2];
        buffer[2]<=buffer[1];
        buffer[1]<=buffer[0];
        buffer[0]<=data_in;
    end
end

always@(posedge clk or negedge rst) begin

    if(!rst) begin
        counter1 = 0;
        counterv = 0;
    end
else if(data_in == 2'b11)
        counterv <= counterv + 1'b1;
    else if(data_in == 2'b01) begin
        counter1 <= counter1 + 1'b1 + counterv;
        counterv <= 1'b0;
    end
    else begin
        counter1 <= counter1 + counterv;
        counterv <= 1'b0;
    end
end



assign data_out = (counter1%2 == 0) && (counterv == 1)? 2'b10 : buffer[3];

endmodule
module add_b(rst,data_in,data_out,clk);


input clk,rst;
input [1:0]data_in;
output [1:0]data_out;
reg counter1;
reg counterv;
reg [1:0]buffer[3:0];

always@(posedge clk or negedge rst) begin

    if(!rst) begin
        buffer[3]<=0;
        buffer[2]<=0;
        buffer[1]<=0;
        buffer[0]<=0;
    end
    else begin
        buffer[3]<=buffer[2];
        buffer[2]<=buffer[1];
        buffer[1]<=buffer[0];
        buffer[0]<=data_in;
    end
end

always@(posedge clk or negedge rst) begin

    if(!rst) begin
        counter1 = 0;
        counterv = 0;
    end
else if(data_in == 2'b11)
        counterv <= counterv + 1'b1;
    else if(data_in == 2'b01) begin
        counter1 <= counter1 + 1'b1 + counterv;
        counterv <= 1'b0;
    end
    else begin
        counter1 <= counter1 + counterv;
        counterv <= 1'b0;
    end
end



assign data_out = (counter1%2 == 0) && (counterv == 1)? 2'b10 : buffer[3];

endmodule