data/full_repos/permissive/439731184/example_case.v
1: b'%Error: data/full_repos/permissive/439731184/example_case.v:33: Unsupported or unknown PLI call: $urandom\n    r = $urandom;\n        ^~~~~~~~\n%Error: data/full_repos/permissive/439731184/example_case.v:43: Unsupported or unknown PLI call: $monitor\n    $monitor("%b\\t%b\\t%b\\t%b\\t%h\\t%b", a, b, c, d, sel, y);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/439731184/example_case.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #7 $finish;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/439731184/example_case.v:47: Unsupported: Ignoring delay on this delayed statement.\nalways #2 sel = sel + 1;\n       ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux_tb();

reg a, b, c, d;
reg [3:0] r;
reg [1:0] sel;
wire y;

mux M (a, b, c, d, sel, y);

initial begin
    r = $urandom;
    a = r%2;
    r = r / 2;
    b = r%2;
    r = r / 2;
    c = r%2;
    r = r / 2;
    d = r%2;
    sel = 1'b00;
    $display("a\tb\tc\td\tsel\ty");
    $monitor("%b\t%b\t%b\t%b\t%h\t%b", a, b, c, d, sel, y);
    #7 $finish;
end

always #2 sel = sel + 1;

endmodule
module mux_tb();


reg a, b, c, d;
reg [3:0] r;
reg [1:0] sel;
wire y;

mux M (a, b, c, d, sel, y);

initial begin
    r = $urandom;
    a = r%2;
    r = r / 2;
    b = r%2;
    r = r / 2;
    c = r%2;
    r = r / 2;
    d = r%2;
    sel = 1'b00;
    $display("a\tb\tc\td\tsel\ty");
    $monitor("%b\t%b\t%b\t%b\t%h\t%b", a, b, c, d, sel, y);
    #7 $finish;
end

always #2 sel = sel + 1;

endmodule