data/full_repos/permissive/48250786/test_subbytes.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/48250786/test_subbytes.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #20 add = add + 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/48250786/test_subbytes.v:35: Cannot find file containing module: \'subBytes\'\n subBytes uut (\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/48250786,data/full_repos/permissive/48250786/subBytes\n             data/full_repos/permissive/48250786,data/full_repos/permissive/48250786/subBytes.v\n             data/full_repos/permissive/48250786,data/full_repos/permissive/48250786/subBytes.sv\n             subBytes\n             subBytes.v\n             subBytes.sv\n             obj_dir/subBytes\n             obj_dir/subBytes.v\n             obj_dir/subBytes.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_subbytes;


	reg [7:0] add;
	reg invbytes;


	wire [7:0] dout;


	subBytes uut (
		.dout(dout), 
		.add(add), 
		.invbytes(invbytes)
	);

	always begin
		#20 add = add + 1;
	end

	initial begin

		add = 0;
		invbytes = 0;


		
        


	end
      
endmodule
module test_subbytes;



	reg [7:0] add;
	reg invbytes;


	wire [7:0] dout;


	subBytes uut (
		.dout(dout), 
		.add(add), 
		.invbytes(invbytes)
	);

	always begin
		#20 add = add + 1;
	end

	initial begin

		add = 0;
		invbytes = 0;


		
        


	end
      
endmodule