data/full_repos/permissive/504478691/sound/harmony_and_scale/stabilization.v
data/verilator_xmls/68a01e53-05ab-417d-bb9b-1bdcaa14f41f.xml
module stabilization(input clk, input origin, output reg stabilized_signal);
reg [31:0] down = 0;
integer times = 100_000_000 / 100;
always @(posedge clk)
begin
    if (origin == 1)
    begin
        stabilized_signal = 1;
        down = 0;
    end
    else
        down = down + 1;
    if (down == times - 1)
    begin
        stabilized_signal = 0;
        down = 0;
    end
end
endmodule
module stabilization(input clk, input origin, output reg stabilized_signal);

reg [31:0] down = 0;
integer times = 100_000_000 / 100;
always @(posedge clk)
begin
    if (origin == 1)
    begin
        stabilized_signal = 1;
        down = 0;
    end
    else
        down = down + 1;
    if (down == times - 1)
    begin
        stabilized_signal = 0;
        down = 0;
    end
end
endmodule