data/full_repos/permissive/482974522/TimeMultiplexed_FIR.srcs/sources_1/new/FixedMult.v
139: b'%Warning-WIDTH: data/full_repos/permissive/482974522/TimeMultiplexed_FIR.srcs/sources_1/new/FixedMult.v:71: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s REPLICATE generates 3 bits.\n                                                                                                          : ... In instance FixedPointMult\n        tempI = (WIO>multWI) ? {{(WIO-multWI){multAI[multWI-1]}},multAI[multWI-2:0]} : \n                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/482974522/TimeMultiplexed_FIR.srcs/sources_1/new/FixedMult.v:73: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s REPLICATE generates 4 bits.\n                                                                                                          : ... In instance FixedPointMult\n        : (WIO<multWI) ? {multAI[multWI-1], multAI[WIO-2:0]} : multAI[multWI-1:0];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/482974522/TimeMultiplexed_FIR.srcs/sources_1/new/FixedMult.v:71: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n                                                                                                          : ... In instance FixedPointMult\n        tempI = (WIO>multWI) ? {{(WIO-multWI){multAI[multWI-1]}},multAI[multWI-2:0]} : \n              ^\n%Warning-WIDTH: data/full_repos/permissive/482974522/TimeMultiplexed_FIR.srcs/sources_1/new/FixedMult.v:75: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s REPLICATE generates 4 bits.\n                                                                                                          : ... In instance FixedPointMult\n        tempF = (WFO>multWF) ? {multAF[multWF-1:0],{(WFO-multWF){1\'b0}}} : \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/482974522/TimeMultiplexed_FIR.srcs/sources_1/new/FixedMult.v:77: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s SEL generates 4 bits.\n                                                                                                          : ... In instance FixedPointMult\n        (WFO<multWF) ? multAF[multWF-1:multWF-WFO] : multAF[multWF-1:0];\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/482974522/TimeMultiplexed_FIR.srcs/sources_1/new/FixedMult.v:75: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s COND generates 8 bits.\n                                                                                                          : ... In instance FixedPointMult\n        tempF = (WFO>multWF) ? {multAF[multWF-1:0],{(WFO-multWF){1\'b0}}} : \n              ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/482974522/TimeMultiplexed_FIR.srcs/sources_1/new/FixedMult.v:75: More than a 8k bit replication is probably wrong: 4294967292\n                                                                                                                : ... In instance FixedPointMult\n        tempF = (WFO>multWF) ? {multAF[multWF-1:0],{(WFO-multWF){1\'b0}}} : \n                                                                ^\nSegmentation fault\n%Error: Command Failed /usr/bin/verilator_bin --xml-output data/verilator_xmls/83ea83d5-549e-4a79-9c56-faa26e2d08ea.xml --y data/full_repos/permissive/482974522/TimeMultiplexed_FIR.srcs/sources_1/new\\,data/full_repos/permissive/482974522 data/full_repos/permissive/482974522/TimeMultiplexed_FIR.srcs/sources_1/new/FixedMult.v\n'
module FixedPointMult 
    #(parameter WI1 = 4, WF1 = 4,
    WI2 = 4, WF2 = 4,
    WIO = 4, WFO = 4,
    W1 = WI1+WF1,
    W2 = WI2+WF2,
    WO=WIO+WFO)
    (input RST,
    input signed [W1-1:0] in1,
    input signed [W2-1:0] in2,
    output reg signed [WO-1:0] out,
    output reg OVF
);
    parameter maxW = `maxWI + `maxWF;
    localparam multW = 2 * maxW;
    localparam multWI = 2 * `maxWI;
    localparam multWF = 2 * `maxWF;
    
    reg signed [`maxWI-1:0] in1I;
    reg signed [`maxWF-1:0] in1F;
    reg signed [`maxWI+`maxWF-1:0] in1A;
    
    reg signed [`maxWI-1:0] in2I;
    reg signed [`maxWF-1:0] in2F;
    reg signed [`maxWI+`maxWF-1:0] in2A;
    
    reg signed [(2*(maxW))-1:0] multA;

    reg signed [(2*`maxWI)-1:0] multAI;
    reg signed [(2*`maxWF)-1:0] multAF;

    reg signed [WIO-1:0] tempI;
    reg signed [WFO-1:0] tempF;

    always@(*) begin
        in1I = WI1==WI2 ? in1[W1-1:WF1] : WI1 > WI2 ? in1[W1-1:WF1] : WI1 < WI2  ? {{(WI2-WI1){in1[W1-1]}},in1[W1-1:WF1]} : in1[W1-1:WF1];
        in2I = WI1==WI2 ? in2[W2-1:WF2] : WI1 > WI2 ? {{(WI1-WI2){in2[W2-1]}},in2[W2-1:WF2]} : WI1 < WI2  ? in2[W2-1:WF2] : in2[W2-1:WF2];
        in1F = WF1==WF2 ? in1[WF1-1:0] : WF1 > WF2 ? in1[WF1-1:0] : WF1 <WF2 ? {in1[WF1-1:0],{(WF2-WF1){1'b0}}}  : in1[WF1-1:0];
        in2F = WF1==WF2 ? in2[WF2-1:0] : WF1 > WF2 ? {in2[WF2-1:0], {(WF1-WF2){1'b0}}} : WF1 <WF2 ? in2[WF2-1:0]  : in2[WF2-1:0];
        
        in1A = {in1I,in1F};
        in2A = {in2I,in2F};
        
        multA = in1A * in2A;
        
        {multAI,multAF} = multA;
        
        tempI = (WIO>multWI) ? {{(WIO-multWI){multAI[multWI-1]}},multAI[multWI-2:0]} : 
        (WIO==multWI) ? multAI[multWI-1:0] 
        : (WIO<multWI) ? {multAI[multWI-1], multAI[WIO-2:0]} : multAI[multWI-1:0];
        
        tempF = (WFO>multWF) ? {multAF[multWF-1:0],{(WFO-multWF){1'b0}}} : 
        (WFO==multWF) ? multAF[multWF-1:0] : 
        (WFO<multWF) ? multAF[multWF-1:multWF-WFO] : multAF[multWF-1:0];
        
        out = {tempI, tempF};

        OVF = (WIO>multWI) ? 0 
        : (WIO==multWI) ? (in1A[`maxWI+`maxWF-1] & in2A[`maxWI+`maxWF-1] & ~out[WO-1]) | (~in1A[`maxWI+`maxWF-1] &  ~in2A[`maxWI+`maxWF-1] & out[WO-1]) 

        : (WIO<multWI) ? ~((multAI[multWI-1] & (&multAI[multWI-2:WIO-1])) | (~multAI[multWI-1] & ~(|multAI[multWI-2:WIO-1])))
        : 0;
    end
endmodule
module FixedPointMult 
    #(parameter WI1 = 4, WF1 = 4,
    WI2 = 4, WF2 = 4,
    WIO = 4, WFO = 4,
    W1 = WI1+WF1,
    W2 = WI2+WF2,
    WO=WIO+WFO)
    (input RST,
    input signed [W1-1:0] in1,
    input signed [W2-1:0] in2,
    output reg signed [WO-1:0] out,
    output reg OVF
);

    parameter maxW = `maxWI + `maxWF;
    localparam multW = 2 * maxW;
    localparam multWI = 2 * `maxWI;
    localparam multWF = 2 * `maxWF;
    
    reg signed [`maxWI-1:0] in1I;
    reg signed [`maxWF-1:0] in1F;
    reg signed [`maxWI+`maxWF-1:0] in1A;
    
    reg signed [`maxWI-1:0] in2I;
    reg signed [`maxWF-1:0] in2F;
    reg signed [`maxWI+`maxWF-1:0] in2A;
    
    reg signed [(2*(maxW))-1:0] multA;

    reg signed [(2*`maxWI)-1:0] multAI;
    reg signed [(2*`maxWF)-1:0] multAF;

    reg signed [WIO-1:0] tempI;
    reg signed [WFO-1:0] tempF;

    always@(*) begin
        in1I = WI1==WI2 ? in1[W1-1:WF1] : WI1 > WI2 ? in1[W1-1:WF1] : WI1 < WI2  ? {{(WI2-WI1){in1[W1-1]}},in1[W1-1:WF1]} : in1[W1-1:WF1];
        in2I = WI1==WI2 ? in2[W2-1:WF2] : WI1 > WI2 ? {{(WI1-WI2){in2[W2-1]}},in2[W2-1:WF2]} : WI1 < WI2  ? in2[W2-1:WF2] : in2[W2-1:WF2];
        in1F = WF1==WF2 ? in1[WF1-1:0] : WF1 > WF2 ? in1[WF1-1:0] : WF1 <WF2 ? {in1[WF1-1:0],{(WF2-WF1){1'b0}}}  : in1[WF1-1:0];
        in2F = WF1==WF2 ? in2[WF2-1:0] : WF1 > WF2 ? {in2[WF2-1:0], {(WF1-WF2){1'b0}}} : WF1 <WF2 ? in2[WF2-1:0]  : in2[WF2-1:0];
        
        in1A = {in1I,in1F};
        in2A = {in2I,in2F};
        
        multA = in1A * in2A;
        
        {multAI,multAF} = multA;
        
        tempI = (WIO>multWI) ? {{(WIO-multWI){multAI[multWI-1]}},multAI[multWI-2:0]} : 
        (WIO==multWI) ? multAI[multWI-1:0] 
        : (WIO<multWI) ? {multAI[multWI-1], multAI[WIO-2:0]} : multAI[multWI-1:0];
        
        tempF = (WFO>multWF) ? {multAF[multWF-1:0],{(WFO-multWF){1'b0}}} : 
        (WFO==multWF) ? multAF[multWF-1:0] : 
        (WFO<multWF) ? multAF[multWF-1:multWF-WFO] : multAF[multWF-1:0];
        
        out = {tempI, tempF};

        OVF = (WIO>multWI) ? 0 
        : (WIO==multWI) ? (in1A[`maxWI+`maxWF-1] & in2A[`maxWI+`maxWF-1] & ~out[WO-1]) | (~in1A[`maxWI+`maxWF-1] &  ~in2A[`maxWI+`maxWF-1] & out[WO-1]) 

        : (WIO<multWI) ? ~((multAI[multWI-1] & (&multAI[multWI-2:WIO-1])) | (~multAI[multWI-1] & ~(|multAI[multWI-2:WIO-1])))
        : 0;
    end
endmodule