data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/reorddrvld.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/reorddrvld.v:86: Cannot find file containing module: 'fflopx'\nfflopx #(1) ppivld (clk,rst,ivld,ivldp);\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/fflopx\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/fflopx.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/fflopx.sv\n             fflopx\n             fflopx.v\n             fflopx.sv\n             obj_dir/fflopx\n             obj_dir/fflopx.v\n             obj_dir/fflopx.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/reorddrvld.v:87: Cannot find file containing module: 'fflopx'\nfflopx #(1) ppivld1 (clk,rst,ivld1,ivld1p);\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/reorddrvld.v:88: Cannot find file containing module: 'fflopx'\nfflopx #(ADDSEQ) ppivldseqid (clk,rst,ivldseqid,ivldseqidp);\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/reorddrvld.v:89: Cannot find file containing module: 'fflopx'\nfflopx #(ADDSEQ) ppivldseqid1 (clk,rst,ivldseqid1,ivldseqid1p);\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/reorddrvld.v:95: Cannot find file containing module: 'fflopx'\nfflopx #(ADDSEQ) ppvldseq (clk,rst,vldseq,vldseq1);\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/reorddrvld.v:96: Cannot find file containing module: 'fflopx'\nfflopx #(1) ppvldget (clk,rst,vldget,vldget1);\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/reorddrvld.v:102: Cannot find file containing module: 'af6cesrtl_gapbuf'\naf6cesrtl_gapbuf #(ADDSEQ,ADDINFO+ADDSEQ,TYPE) fiforeq\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/reorddrvld.v:169: Cannot find file containing module: 'fflopx'\nfflopx #(ADDSEQ+ADDINFO) ppovldinfo (clk,rst,{vldinfo,vldseq},{ovldinfo,ovldseq});\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/reorddrvld.v:180: Cannot find file containing module: 'fflopx'\nfflopx #(1) pp1error (clk,rst,error,oerror);\n^~~~~~\n%Error: Exiting due to 9 error(s)\n"
module reorddrvld
    (clk,
     rst,


     iack,    
     iackseqid,
     iackinfo,
     ivld,
     ivldseqid,
     ivld1,
     ivldseqid1,
     onumreq,
     

     ovld,
     ovldinfo,
     ovldseq,
     

     iflush,


     oerror
     );



parameter   ADDSEQ = 4;
parameter   NUMSEQ = 16;

parameter   ADDINFO = 40;
parameter   TYPE = "MLAB";
parameter   GAPMOD = 1'b1;



input   clk,
        rst;

input [ADDSEQ-1:0]          iackseqid;
input [ADDINFO-1:0]         iackinfo;
input                       iack;
input                       ivld,
                            ivld1;
input [ADDSEQ-1:0]          ivldseqid,
                            ivldseqid1;

output                      ovld;
output [ADDINFO-1:0]        ovldinfo;
output [ADDSEQ-1:0]         ovldseq;
output [ADDSEQ:0]           onumreq;

input                       iflush;
output                      oerror;






reg                         flush = 1'b1;
always @ (posedge clk)
    begin
    if (rst)    flush <= 1'b1;
    else        flush <= iflush;
    end

wire                        ivldp,
                            ivld1p;
wire  [ADDSEQ-1:0]          ivldseqidp,
                            ivldseqid1p;
fflopx #(1) ppivld (clk,rst,ivld,ivldp);
fflopx #(1) ppivld1 (clk,rst,ivld1,ivld1p);
fflopx #(ADDSEQ) ppivldseqid (clk,rst,ivldseqid,ivldseqidp);
fflopx #(ADDSEQ) ppivldseqid1 (clk,rst,ivldseqid1,ivldseqid1p);


wire [ADDSEQ-1:0]   vldseq,vldseq1;
wire [ADDINFO-1:0]  vldinfo;
wire                fifofull,vldget,vldget1,vldreq;
fflopx #(ADDSEQ) ppvldseq (clk,rst,vldseq,vldseq1);
fflopx #(1) ppvldget (clk,rst,vldget,vldget1);

generate
    begin
    if (GAPMOD == 1'b1)
        begin
af6cesrtl_gapbuf #(ADDSEQ,ADDINFO+ADDSEQ,TYPE) fiforeq
    (.clk(clk),
     .rst(rst),


     .ivld(iack),
     .ivldinfo({iackinfo,iackseqid}),
     .ovldfull(fifofull),
     .ovldlen(onumreq),
     

     .flush(flush),
     

     .oreq(vldreq),
     .oreqinfo({vldinfo,vldseq}),
     .iget(vldget)   
     );
        end
    else
        begin
af6cesrtl_reqbuf #(ADDSEQ,ADDINFO+ADDSEQ,TYPE) fiforeq
    (.clk(clk),
     .rst(rst),


     .ivld(iack),
     .ivldinfo({iackinfo,iackseqid}),
     .ovldfull(fifofull),
     .ovldlen(onumreq),
     

     .flush(flush),
     

     .oreq(vldreq),
     .oreqinfo({vldinfo,vldseq}),
     .iget(vldget)   
     );
        end 
    end
endgenerate




reg [NUMSEQ-1:0]    ivldlat = {NUMSEQ{1'b0}};
wire                ivld1same;
assign              ivld1same = ivldp & (ivldseqidp == ivldseqid1p);

wire                ivld1ok;
assign              ivld1ok = ivld1p & (!ivld1same);

always @ (posedge clk)
    begin
    if (flush)    ivldlat <= {NUMSEQ{1'b0}};    
    else
        begin
        if (ivldp)              ivldlat[ivldseqidp] <= 1'b1;
        if (ivld1ok)            ivldlat[ivldseqid1p] <= 1'b1;
        if (vldget1)            ivldlat[vldseq1] <= 1'b0;
        end
    end


assign          vldget = vldreq & ivldlat[vldseq];
assign          ovld = vldget1;
fflopx #(ADDSEQ+ADDINFO) ppovldinfo (clk,rst,{vldinfo,vldseq},{ovldinfo,ovldseq});


wire        iackerr,ivld1err,ivld1errsame,ivlderrsame;
assign      iackerr = fifofull & iack;
assign      ivld1err = ivld1p & ivld1same;
assign      ivlderrsame = ivldp & ivldlat[ivldseqidp];
assign      ivld1errsame = ivld1p & ivldlat[ivldseqid1p];

wire        oerror,error;
assign      error = iackerr | ivld1err | ivld1errsame | ivlderrsame;
fflopx #(1) pp1error (clk,rst,error,oerror);
    
endmodule
module reorddrvld
    (clk,
     rst,


     iack,    
     iackseqid,
     iackinfo,
     ivld,
     ivldseqid,
     ivld1,
     ivldseqid1,
     onumreq,
     

     ovld,
     ovldinfo,
     ovldseq,
     

     iflush,


     oerror
     );




parameter   ADDSEQ = 4;
parameter   NUMSEQ = 16;

parameter   ADDINFO = 40;
parameter   TYPE = "MLAB";
parameter   GAPMOD = 1'b1;



input   clk,
        rst;

input [ADDSEQ-1:0]          iackseqid;
input [ADDINFO-1:0]         iackinfo;
input                       iack;
input                       ivld,
                            ivld1;
input [ADDSEQ-1:0]          ivldseqid,
                            ivldseqid1;

output                      ovld;
output [ADDINFO-1:0]        ovldinfo;
output [ADDSEQ-1:0]         ovldseq;
output [ADDSEQ:0]           onumreq;

input                       iflush;
output                      oerror;






reg                         flush = 1'b1;
always @ (posedge clk)
    begin
    if (rst)    flush <= 1'b1;
    else        flush <= iflush;
    end

wire                        ivldp,
                            ivld1p;
wire  [ADDSEQ-1:0]          ivldseqidp,
                            ivldseqid1p;
fflopx #(1) ppivld (clk,rst,ivld,ivldp);
fflopx #(1) ppivld1 (clk,rst,ivld1,ivld1p);
fflopx #(ADDSEQ) ppivldseqid (clk,rst,ivldseqid,ivldseqidp);
fflopx #(ADDSEQ) ppivldseqid1 (clk,rst,ivldseqid1,ivldseqid1p);


wire [ADDSEQ-1:0]   vldseq,vldseq1;
wire [ADDINFO-1:0]  vldinfo;
wire                fifofull,vldget,vldget1,vldreq;
fflopx #(ADDSEQ) ppvldseq (clk,rst,vldseq,vldseq1);
fflopx #(1) ppvldget (clk,rst,vldget,vldget1);

generate
    begin
    if (GAPMOD == 1'b1)
        begin
af6cesrtl_gapbuf #(ADDSEQ,ADDINFO+ADDSEQ,TYPE) fiforeq
    (.clk(clk),
     .rst(rst),


     .ivld(iack),
     .ivldinfo({iackinfo,iackseqid}),
     .ovldfull(fifofull),
     .ovldlen(onumreq),
     

     .flush(flush),
     

     .oreq(vldreq),
     .oreqinfo({vldinfo,vldseq}),
     .iget(vldget)   
     );
        end
    else
        begin
af6cesrtl_reqbuf #(ADDSEQ,ADDINFO+ADDSEQ,TYPE) fiforeq
    (.clk(clk),
     .rst(rst),


     .ivld(iack),
     .ivldinfo({iackinfo,iackseqid}),
     .ovldfull(fifofull),
     .ovldlen(onumreq),
     

     .flush(flush),
     

     .oreq(vldreq),
     .oreqinfo({vldinfo,vldseq}),
     .iget(vldget)   
     );
        end 
    end
endgenerate




reg [NUMSEQ-1:0]    ivldlat = {NUMSEQ{1'b0}};
wire                ivld1same;
assign              ivld1same = ivldp & (ivldseqidp == ivldseqid1p);

wire                ivld1ok;
assign              ivld1ok = ivld1p & (!ivld1same);

always @ (posedge clk)
    begin
    if (flush)    ivldlat <= {NUMSEQ{1'b0}};    
    else
        begin
        if (ivldp)              ivldlat[ivldseqidp] <= 1'b1;
        if (ivld1ok)            ivldlat[ivldseqid1p] <= 1'b1;
        if (vldget1)            ivldlat[vldseq1] <= 1'b0;
        end
    end


assign          vldget = vldreq & ivldlat[vldseq];
assign          ovld = vldget1;
fflopx #(ADDSEQ+ADDINFO) ppovldinfo (clk,rst,{vldinfo,vldseq},{ovldinfo,ovldseq});


wire        iackerr,ivld1err,ivld1errsame,ivlderrsame;
assign      iackerr = fifofull & iack;
assign      ivld1err = ivld1p & ivld1same;
assign      ivlderrsame = ivldp & ivldlat[ivldseqidp];
assign      ivld1errsame = ivld1p & ivldlat[ivldseqid1p];

wire        oerror,error;
assign      error = iackerr | ivld1err | ivld1errsame | ivlderrsame;
fflopx #(1) pp1error (clk,rst,error,oerror);
    
endmodule