data/full_repos/permissive/481320526/Arbtb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/481320526/Arbtb.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/481320526/Arbtb.v:66: Unsupported: Ignoring delay on this delayed statement.\n always begin #5 clk = ~clk; end\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/481320526/Arbtb.v:70: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/481320526/Arbtb.v:73: Unsupported: Ignoring delay on this delayed statement.\n #1000;\n ^\n%Error: data/full_repos/permissive/481320526/Arbtb.v:42: Cannot find file containing module: \'Arbiter\'\n Arbiter uut (\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/481320526,data/full_repos/permissive/481320526/Arbiter\n             data/full_repos/permissive/481320526,data/full_repos/permissive/481320526/Arbiter.v\n             data/full_repos/permissive/481320526,data/full_repos/permissive/481320526/Arbiter.sv\n             Arbiter\n             Arbiter.v\n             Arbiter.sv\n             obj_dir/Arbiter\n             obj_dir/Arbiter.v\n             obj_dir/Arbiter.sv\n%Warning-WIDTH: data/full_repos/permissive/481320526/Arbtb.v:72: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIVS generates 32 bits.\n                                                               : ... In instance Arbtb\n {Rqst3,Rqst2,Rqst1,Rqst0} = $random % 16;\n                           ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Arbtb;


	reg Rqst0;
	reg Rqst1;
	reg Rqst2;
	reg Rqst3;
	reg clk;
	reg resetn;


	wire Grant0;
	wire Grant1;
	wire Grant2;
	wire Grant3;


	Arbiter uut (
		.Rqst0(Rqst0), 
		.Rqst1(Rqst1), 
		.Rqst2(Rqst2), 
		.Rqst3(Rqst3), 
		.clk(clk), 
		.resetn(resetn), 
		.Grant0(Grant0), 
		.Grant1(Grant1), 
		.Grant2(Grant2), 
		.Grant3(Grant3)
	);

	initial begin

		clk = 0;


		#100;
        


	end
	
	always begin #5 clk = ~clk; end
	
	always begin
	resetn = 0;
	#10
	resetn = 1;
	{Rqst3,Rqst2,Rqst1,Rqst0} = $random % 16;
	#1000;
	end
      
endmodule
module Arbtb;



	reg Rqst0;
	reg Rqst1;
	reg Rqst2;
	reg Rqst3;
	reg clk;
	reg resetn;


	wire Grant0;
	wire Grant1;
	wire Grant2;
	wire Grant3;


	Arbiter uut (
		.Rqst0(Rqst0), 
		.Rqst1(Rqst1), 
		.Rqst2(Rqst2), 
		.Rqst3(Rqst3), 
		.clk(clk), 
		.resetn(resetn), 
		.Grant0(Grant0), 
		.Grant1(Grant1), 
		.Grant2(Grant2), 
		.Grant3(Grant3)
	);

	initial begin

		clk = 0;


		#100;
        


	end
	
	always begin #5 clk = ~clk; end
	
	always begin
	resetn = 0;
	#10
	resetn = 1;
	{Rqst3,Rqst2,Rqst1,Rqst0} = $random % 16;
	#1000;
	end
      
endmodule