data/full_repos/permissive/42434302/ivltests/scope5.v
1: b"%Error: data/full_repos/permissive/42434302/ivltests/scope5.v:16: syntax error, unexpected bit, expecting IDENTIFIER or '=' or do or final\n   reg bit;\n       ^~~\n%Error: data/full_repos/permissive/42434302/ivltests/scope5.v:17: syntax error, unexpected var, expecting IDENTIFIER or '=' or do or final\n   reg [31:0] var;\n              ^~~\n%Error: data/full_repos/permissive/42434302/ivltests/scope5.v:20: syntax error, unexpected var\n      var = 1;\n      ^~~\n%Error: Exiting due to 3 error(s)\n"
module test;

   real tmp;

   function fun1;
      input [31:0] parm;
      real tmp;

      begin
	 tmp = 0.0;
	 fun1 = parm[0];
      end

   endfunction

   reg bit;
   reg [31:0] var;
   initial begin
      tmp = 1.0;
      var = 1;
      bit = fun1(var);

      if (tmp != 1.0) begin
	 $display("FAILED -- tmp=%f, fun1.tmp=%f", tmp, fun1.tmp);
	 $finish;
      end

      $display("PASSED");
   end

endmodule
module test;


   real tmp;

   function fun1;
      input [31:0] parm;
      real tmp;

      begin
	 tmp = 0.0;
	 fun1 = parm[0];
      end

   endfunction

   reg bit;
   reg [31:0] var;
   initial begin
      tmp = 1.0;
      var = 1;
      bit = fun1(var);

      if (tmp != 1.0) begin
	 $display("FAILED -- tmp=%f, fun1.tmp=%f", tmp, fun1.tmp);
	 $finish;
      end

      $display("PASSED");
   end

endmodule