data/full_repos/permissive/524341347/verilog/rtl/tagMem_ext.v
1: b'%Warning-WIDTH: data/full_repos/permissive/524341347/verilog/rtl/tagMem_ext.v:16: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 24 bits.\n                                                                                : ... In instance tagMem_ext\n  assign wdata = {4\'b0,W0_data};\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/524341347/verilog/rtl/tagMem_ext.v:19: Cannot find file containing module: \'sky130_sram_1kbyte_1rw1r_32x256_8\'\n  sky130_sram_1kbyte_1rw1r_32x256_8 i_sky130_sram_1kbyte_1rw1r_32x256_8(\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/524341347/verilog/rtl,data/full_repos/permissive/524341347/sky130_sram_1kbyte_1rw1r_32x256_8\n             data/full_repos/permissive/524341347/verilog/rtl,data/full_repos/permissive/524341347/sky130_sram_1kbyte_1rw1r_32x256_8.v\n             data/full_repos/permissive/524341347/verilog/rtl,data/full_repos/permissive/524341347/sky130_sram_1kbyte_1rw1r_32x256_8.sv\n             sky130_sram_1kbyte_1rw1r_32x256_8\n             sky130_sram_1kbyte_1rw1r_32x256_8.v\n             sky130_sram_1kbyte_1rw1r_32x256_8.sv\n             obj_dir/sky130_sram_1kbyte_1rw1r_32x256_8\n             obj_dir/sky130_sram_1kbyte_1rw1r_32x256_8.v\n             obj_dir/sky130_sram_1kbyte_1rw1r_32x256_8.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module tagMem_ext(
  input R0_clk,
  input [7:0] R0_addr,
  input R0_en,
  output [19:0] R0_data,
  input W0_clk,
  input [7:0] W0_addr,
  input W0_en,
  input [19:0] W0_data
);

  wire [31:0] wdata;
  wire [31:0] rdata;

  assign wdata = {4'b0,W0_data};
  assign R0_data = rdata[19:0];

  sky130_sram_1kbyte_1rw1r_32x256_8 i_sky130_sram_1kbyte_1rw1r_32x256_8(
    .clk0(W0_clk),.csb0(~W0_en),.web0(~W0_en),.wmask0({4{1'b1}}),.addr0(W0_addr),.din0(wdata),.dout0(),
    .clk1(R0_clk),.csb1(~R0_en),.addr1(R0_addr),.dout1(rdata)
  );


endmodule
module tagMem_ext(
  input R0_clk,
  input [7:0] R0_addr,
  input R0_en,
  output [19:0] R0_data,
  input W0_clk,
  input [7:0] W0_addr,
  input W0_en,
  input [19:0] W0_data
);


  wire [31:0] wdata;
  wire [31:0] rdata;

  assign wdata = {4'b0,W0_data};
  assign R0_data = rdata[19:0];

  sky130_sram_1kbyte_1rw1r_32x256_8 i_sky130_sram_1kbyte_1rw1r_32x256_8(
    .clk0(W0_clk),.csb0(~W0_en),.web0(~W0_en),.wmask0({4{1'b1}}),.addr0(W0_addr),.din0(wdata),.dout0(),
    .clk1(R0_clk),.csb1(~R0_en),.addr1(R0_addr),.dout1(rdata)
  );


endmodule