data/full_repos/permissive/462122681/mul.v
1: b'%Warning-WIDTH: data/full_repos/permissive/462122681/mul.v:17: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n                                                             : ... In instance mul\n   dig = A[i];\n       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module mul(A, B, mul_out);
	input signed [31:0] A, B; 
	output signed [63:0]mul_out;
	reg signed [63:0] mul_out;
	reg[1:0] dig;
	integer i;
	
	reg[31:0] twos;

	always @ (A,B) begin
		mul_out = 64'd0;
		twos = -B;
		mul_out[63:32] = A;
		
		for(i = 0; i < 32; i = i + 1)begin
			dig = A[i];
				case(dig)
					2'd2: mul_out[63:31] = mul_out[63:31] + twos;
					2'd1: mul_out[63:31] = mul_out[63:31] + B;
					default: begin end
				endcase
				
				mul_out = mul_out >> 1;
				mul_out[63] = mul_out[62];
				
		end
	end
endmodule
module mul(A, B, mul_out);

	input signed [31:0] A, B; 
	output signed [63:0]mul_out;
	reg signed [63:0] mul_out;
	reg[1:0] dig;
	integer i;
	
	reg[31:0] twos;

	always @ (A,B) begin
		mul_out = 64'd0;
		twos = -B;
		mul_out[63:32] = A;
		
		for(i = 0; i < 32; i = i + 1)begin
			dig = A[i];
				case(dig)
					2'd2: mul_out[63:31] = mul_out[63:31] + twos;
					2'd1: mul_out[63:31] = mul_out[63:31] + B;
					default: begin end
				endcase
				
				mul_out = mul_out >> 1;
				mul_out[63] = mul_out[62];
				
		end
	end
endmodule