data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/ecc_core.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/ecc_core.v:70: Cannot find file containing module: 'mainctrl'\nmainctrl\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl,data/full_repos/permissive/530013823/mainctrl\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl,data/full_repos/permissive/530013823/mainctrl.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl,data/full_repos/permissive/530013823/mainctrl.sv\n             mainctrl\n             mainctrl.v\n             mainctrl.sv\n             obj_dir/mainctrl\n             obj_dir/mainctrl.v\n             obj_dir/mainctrl.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/ecc_core.v:104: Cannot find file containing module: 'auc_wrap'\nauc_wrap\n^~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/ecc_core.v:138: Cannot find file containing module: 'aluwrap'\naluwrap\n^~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module ecc_core
    (
     clk,
     rst,

     din,
     mode,
     start,
     dout,
     status,

     test_num
     );




`define             RTL_SIMULATION
`define             RWSAMECLK

parameter           WIDTH   = 256;
parameter           ADDR    = 5;
parameter           WINDOW  = 4;
parameter           CBIT    = 8;
parameter           DEPTH   = 1<<ADDR;
parameter           CURWID  = 255;
parameter           OPWID   = 4;





input               clk;
input               rst;


input [3*WIDTH-1:0] din;
input [2:0]         mode;
input               start;
output [WIDTH-1:0]  dout;
output [1:0]        status;

input [WIDTH-1:0]   test_num;







wire [WIDTH-1:0]    auc_dat;
wire [OPWID-1:0]    auc_mode;
wire                auc_start;
wire [WIDTH-1:0]    auc_rslt;
wire [1:0]          auc_status;

mainctrl
    #(
      .WIDTH(WIDTH)
      ) imainctrl
    (
     .clk(clk),
     .rst(rst),

     .din(din),
     .mode(mode),
     .start(start),
     .dout(dout),
     .status(status),

     .auc_dat(auc_dat),
     .auc_start(auc_start),
     .auc_mode(auc_mode),
     .auc_rslt(auc_rslt),
     .auc_status(auc_status)
     );



wire [WIDTH-1:0]    au_dat1;
wire [WIDTH-1:0]    au_dat2;
wire                au_carry;
wire                au_start;
wire [OPWID-1:0]    au_opcode;
wire                au_swapop;
wire                au_swapvl;
wire [WIDTH-1:0]    au_rswap;
wire [WIDTH-1:0]    au_rslt;
wire                au_vld;

auc_wrap
    #(
      .WIDTH(WIDTH),
      .ADDR(ADDR),
      .WINDOW(WINDOW),
      .CBIT(CBIT),
      .DEPTH(DEPTH)
      ) iauc_wrap
    (
     .clk(clk),
     .rst(rst),

     .auc_dat(auc_dat),
     .auc_start(auc_start),
     .auc_mode(auc_mode),
     .auc_rslt(auc_rslt),
     .auc_status(auc_status),

     .au_dat1(au_dat1),
     .au_dat2(au_dat2),
     .au_carry(au_carry),
     .au_start(au_start),
     .au_opcode(au_opcode),
     .au_swapop(au_swapop),
     .au_swapvl(au_swapvl),
     .au_rslt(au_rslt),
     .au_rswap(au_rswap),
     .au_vld(au_vld),

     .test_num(test_num)
     );



aluwrap
    #(
    .WID(WIDTH)
      ) ialuwrap        
    (   
     .clk(clk),
     .rst(rst),
     .status(),

     .a(au_dat1),
     .b(au_dat2),
     .c(au_carry),
     .en(au_start),
     .swapop(au_swapop),
     .swapvl(au_swapvl),
     .opcode(au_opcode),


     
     .r(au_rslt),
     .rswap(au_rswap),
     .vld(au_vld)
     );

endmodule
module ecc_core
    (
     clk,
     rst,

     din,
     mode,
     start,
     dout,
     status,

     test_num
     );





`define             RTL_SIMULATION
`define             RWSAMECLK

parameter           WIDTH   = 256;
parameter           ADDR    = 5;
parameter           WINDOW  = 4;
parameter           CBIT    = 8;
parameter           DEPTH   = 1<<ADDR;
parameter           CURWID  = 255;
parameter           OPWID   = 4;





input               clk;
input               rst;


input [3*WIDTH-1:0] din;
input [2:0]         mode;
input               start;
output [WIDTH-1:0]  dout;
output [1:0]        status;

input [WIDTH-1:0]   test_num;







wire [WIDTH-1:0]    auc_dat;
wire [OPWID-1:0]    auc_mode;
wire                auc_start;
wire [WIDTH-1:0]    auc_rslt;
wire [1:0]          auc_status;

mainctrl
    #(
      .WIDTH(WIDTH)
      ) imainctrl
    (
     .clk(clk),
     .rst(rst),

     .din(din),
     .mode(mode),
     .start(start),
     .dout(dout),
     .status(status),

     .auc_dat(auc_dat),
     .auc_start(auc_start),
     .auc_mode(auc_mode),
     .auc_rslt(auc_rslt),
     .auc_status(auc_status)
     );



wire [WIDTH-1:0]    au_dat1;
wire [WIDTH-1:0]    au_dat2;
wire                au_carry;
wire                au_start;
wire [OPWID-1:0]    au_opcode;
wire                au_swapop;
wire                au_swapvl;
wire [WIDTH-1:0]    au_rswap;
wire [WIDTH-1:0]    au_rslt;
wire                au_vld;

auc_wrap
    #(
      .WIDTH(WIDTH),
      .ADDR(ADDR),
      .WINDOW(WINDOW),
      .CBIT(CBIT),
      .DEPTH(DEPTH)
      ) iauc_wrap
    (
     .clk(clk),
     .rst(rst),

     .auc_dat(auc_dat),
     .auc_start(auc_start),
     .auc_mode(auc_mode),
     .auc_rslt(auc_rslt),
     .auc_status(auc_status),

     .au_dat1(au_dat1),
     .au_dat2(au_dat2),
     .au_carry(au_carry),
     .au_start(au_start),
     .au_opcode(au_opcode),
     .au_swapop(au_swapop),
     .au_swapvl(au_swapvl),
     .au_rslt(au_rslt),
     .au_rswap(au_rswap),
     .au_vld(au_vld),

     .test_num(test_num)
     );



aluwrap
    #(
    .WID(WIDTH)
      ) ialuwrap        
    (   
     .clk(clk),
     .rst(rst),
     .status(),

     .a(au_dat1),
     .b(au_dat2),
     .c(au_carry),
     .en(au_start),
     .swapop(au_swapop),
     .swapvl(au_swapvl),
     .opcode(au_opcode),


     
     .r(au_rslt),
     .rswap(au_rswap),
     .vld(au_vld)
     );

endmodule