data/full_repos/permissive/424292861/guia8/ALU.v
1: b"%Error: data/full_repos/permissive/424292861/guia8/ALU.v:60: syntax error, unexpected '=', expecting IDENTIFIER\n s1 = and1;\n    ^\n%Error: data/full_repos/permissive/424292861/guia8/ALU.v:106: syntax error, unexpected '=', expecting IDENTIFIER\n soma = 5'b0001;\n      ^\n%Error: Exiting due to 2 error(s)\n"
module fullsub5bits(a,b,s0,s1);
	input[5:0] a,b;
	output[5:0] s0;
	output s1;
	reg[5:0] s0;
	reg s1;
	wire sub1,sub2,sub3,sub4;
	halfsub SUB1(a[0],b[0],s0[0],sub1);
	halfsub SUB2(a[1],b[1],sub1,s0[1],sub2);
	halfsub SUB3(a[2],b[2],sub2,s0[2],sub3);
	halfsub SUB4(a[3],b[3],sub3,s0[3],sub4);
	halfsub SUB5(a[4],b[4],sub4,s0[4],s1);
endmodule
module fullsub5bits(a,b,s0,s1);

	input[5:0] a,b;
	output[5:0] s0;
	output s1;
	reg[5:0] s0;
	reg s1;
	wire sub1,sub2,sub3,sub4;
	halfsub SUB1(a[0],b[0],s0[0],sub1);
	halfsub SUB2(a[1],b[1],sub1,s0[1],sub2);
	halfsub SUB3(a[2],b[2],sub2,s0[2],sub3);
	halfsub SUB4(a[3],b[3],sub3,s0[3],sub4);
	halfsub SUB5(a[4],b[4],sub4,s0[4],s1);
endmodule