data/full_repos/permissive/488739248/rtl/ttl/ttl_74283_nodly.v
1: b'%Warning-WIDTH: data/full_repos/permissive/488739248/rtl/ttl/ttl_74283_nodly.v:21: Operator ADD expects 5 bits on the RHS, but RHS\'s VARREF \'C_in\' generates 1 bits.\n                                                                                 : ... In instance ttl_74283_nodly\n  {C_computed, Sum_computed} = {1\'b0, A} + {1\'b0, B} + C_in;\n                                                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module ttl_74283_nodly #(parameter WIDTH = 4)
(
  input wire [WIDTH-1:0] A,
  input wire [WIDTH-1:0] B,
  input wire C_in,
  output wire [WIDTH-1:0] Sum,
  output wire C_out
);


reg [WIDTH-1:0] Sum_computed;
reg C_computed;

always @(*)
begin
  {C_computed, Sum_computed} = {1'b0, A} + {1'b0, B} + C_in;
end



assign Sum = Sum_computed;
assign C_out = C_computed;

endmodule
module ttl_74283_nodly #(parameter WIDTH = 4)
(
  input wire [WIDTH-1:0] A,
  input wire [WIDTH-1:0] B,
  input wire C_in,
  output wire [WIDTH-1:0] Sum,
  output wire C_out
);



reg [WIDTH-1:0] Sum_computed;
reg C_computed;

always @(*)
begin
  {C_computed, Sum_computed} = {1'b0, A} + {1'b0, B} + C_in;
end



assign Sum = Sum_computed;
assign C_out = C_computed;

endmodule