data/full_repos/permissive/447976230/fpga/usrp3/top/x400/rf/400m/dac_gearbox_4x2.v
1: b'%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/rf/400m/dac_gearbox_4x2.v:35: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                                                     : ... In instance dac_gearbox_4x2\n  reg [127:0] data_in_2x_dly0 = 128\'b0, data_in_2x_dly1 = 32\'b0;\n                                                          ^~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module dac_gearbox_4x2 (
  input  wire         clk1x,
  input  wire         reset_n_1x,

  input  wire [127:0] data_in_1x,
  input  wire         valid_in_1x,
  output wire         ready_out_1x,

  input  wire         clk2x,

  output wire [ 63:0] data_out_2x,
  output wire         valid_out_2x
);



  reg toggle_1x, toggle_2x = 1'b0, toggle_2x_dly = 1'b0, valid_2x = 1'b0, valid_dly_2x = 1'b0;
  reg [127:0] data_in_2x_dly0 = 128'b0, data_in_2x_dly1 = 32'b0;
  reg [63 :0] data_2x_dly = 64'b0;


  always @(posedge clk1x or negedge reset_n_1x) begin
    if ( ! reset_n_1x) begin
      toggle_1x <= 1'b0;
    end else begin
      toggle_1x <= ! toggle_1x;
    end
  end









  always @(posedge clk2x) begin
    toggle_2x     <= toggle_1x;
    toggle_2x_dly <= toggle_2x;
    data_in_2x_dly0 <= data_in_1x;
    data_in_2x_dly1 <= data_in_2x_dly0 ;
    data_2x_dly <= 64'b0;

    if (valid_2x) begin
      data_2x_dly <= data_in_2x_dly1[127:64];
      if (toggle_2x != toggle_2x_dly) begin
        data_2x_dly <= data_in_2x_dly0[63:0];
      end
    end


    valid_2x     <= valid_in_1x;
    valid_dly_2x <= valid_2x;
  end

  assign valid_out_2x = valid_dly_2x;
  assign data_out_2x = data_2x_dly;
  assign ready_out_1x = 1'b1;

endmodule
module dac_gearbox_4x2 (
  input  wire         clk1x,
  input  wire         reset_n_1x,

  input  wire [127:0] data_in_1x,
  input  wire         valid_in_1x,
  output wire         ready_out_1x,

  input  wire         clk2x,

  output wire [ 63:0] data_out_2x,
  output wire         valid_out_2x
);




  reg toggle_1x, toggle_2x = 1'b0, toggle_2x_dly = 1'b0, valid_2x = 1'b0, valid_dly_2x = 1'b0;
  reg [127:0] data_in_2x_dly0 = 128'b0, data_in_2x_dly1 = 32'b0;
  reg [63 :0] data_2x_dly = 64'b0;


  always @(posedge clk1x or negedge reset_n_1x) begin
    if ( ! reset_n_1x) begin
      toggle_1x <= 1'b0;
    end else begin
      toggle_1x <= ! toggle_1x;
    end
  end









  always @(posedge clk2x) begin
    toggle_2x     <= toggle_1x;
    toggle_2x_dly <= toggle_2x;
    data_in_2x_dly0 <= data_in_1x;
    data_in_2x_dly1 <= data_in_2x_dly0 ;
    data_2x_dly <= 64'b0;

    if (valid_2x) begin
      data_2x_dly <= data_in_2x_dly1[127:64];
      if (toggle_2x != toggle_2x_dly) begin
        data_2x_dly <= data_in_2x_dly0[63:0];
      end
    end


    valid_2x     <= valid_in_1x;
    valid_dly_2x <= valid_2x;
  end

  assign valid_out_2x = valid_dly_2x;
  assign data_out_2x = data_2x_dly;
  assign ready_out_1x = 1'b1;

endmodule