data/full_repos/permissive/493265923/03_INTEGRATOR_BACK/INTEGRATOR_BACK.v
data/verilator_xmls/0e5092f6-af55-402a-b23b-2938bfa5c53f.xml
function [DATA_Bit_Length+1:0] assign_out;
        input [DATA_Bit_Length:0] SUM_DATA;
    begin
        case(SUM_DATA[DATA_Bit_Length:DATA_Bit_Length-1])
            2'b01:
                begin


                    assign_out = {1'b0, 1'b1, 1'b0, {(DATA_Bit_Length-1){1'b1}}};
                end

            2'b10:
                begin


                    assign_out = {1'b1, 1'b0, 1'b1, {(DATA_Bit_Length-1){1'b0}}};
                end

            default:
                begin

                    assign_out = {1'b0, 1'b0, SUM_DATA[DATA_Bit_Length], SUM_DATA[DATA_Bit_Length-2:0]};
                end
        endcase
    end
    endfunction
function [DATA_Bit_Length+1:0] assign_out;

        input [DATA_Bit_Length:0] SUM_DATA;
    begin
        case(SUM_DATA[DATA_Bit_Length:DATA_Bit_Length-1])
            2'b01:
                begin


                    assign_out = {1'b0, 1'b1, 1'b0, {(DATA_Bit_Length-1){1'b1}}};
                end

            2'b10:
                begin


                    assign_out = {1'b1, 1'b0, 1'b1, {(DATA_Bit_Length-1){1'b0}}};
                end

            default:
                begin

                    assign_out = {1'b0, 1'b0, SUM_DATA[DATA_Bit_Length], SUM_DATA[DATA_Bit_Length-2:0]};
                end
        endcase
    end
    endfunction