data/full_repos/permissive/489075769/write_address.v
data/verilator_xmls/23e8f24f-4590-4405-96e7-70d1935d31c6.xml
module write_address(ACLK,ARESETn,AWVALID, AWREADY, i_AWADDR, o_AWADDR, AWPROT);
	input ACLK;
	input ARESETn;
	input AWVALID;
	input AWREADY;
	input [31:0] i_AWADDR;
	output reg [31:0] o_AWADDR;
	input [2:0] AWPROT;
	
	always @(posedge ARESETn) begin
		o_AWADDR <= 0;
	end
	
	always @(posedge ACLK) begin
		if (AWVALID && AWREADY) 
		o_AWADDR <= i_AWADDR;
		
		else 
		o_AWADDR <= 0;
	
	end
endmodule
module write_address(ACLK,ARESETn,AWVALID, AWREADY, i_AWADDR, o_AWADDR, AWPROT);

	input ACLK;
	input ARESETn;
	input AWVALID;
	input AWREADY;
	input [31:0] i_AWADDR;
	output reg [31:0] o_AWADDR;
	input [2:0] AWPROT;
	
	always @(posedge ARESETn) begin
		o_AWADDR <= 0;
	end
	
	always @(posedge ACLK) begin
		if (AWVALID && AWREADY) 
		o_AWADDR <= i_AWADDR;
		
		else 
		o_AWADDR <= 0;
	
	end
endmodule