data/full_repos/permissive/515589800/mealy_tb.v
1: b'%Error: data/full_repos/permissive/515589800/mealy_tb.v:7: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("test2.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/515589800/mealy_tb.v:8: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0,t_Mealy_Zero_Detector);\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/515589800/mealy_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\ninitial begin t_clock = 0; forever #5 t_clock = ~t_clock; end\n                                   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/515589800/mealy_tb.v:11: Unsupported: fork statements\ninitial fork\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/515589800/mealy_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n#2 t_reset = 1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/515589800/mealy_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n#87 t_reset = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/515589800/mealy_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n#89 t_reset = 1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/515589800/mealy_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n#10 t_x_in = 1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/515589800/mealy_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n#30 t_x_in = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/515589800/mealy_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n#40 t_x_in = 1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/515589800/mealy_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n#50 t_x_in = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/515589800/mealy_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n#52 t_x_in = 1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/515589800/mealy_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n#54 t_x_in = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/515589800/mealy_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n#70 t_x_in = 1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/515589800/mealy_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n#80 t_x_in = 1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/515589800/mealy_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n#70 t_x_in = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/515589800/mealy_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n#90 t_x_in = 1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/515589800/mealy_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n#100 t_x_in = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/515589800/mealy_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n#120 t_x_in = 1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/515589800/mealy_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n#160 t_x_in = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/515589800/mealy_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n#170 t_x_in = 1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/515589800/mealy_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\ninitial #200 $finish ;\n        ^\n%Error: Exiting due to 3 error(s), 19 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module t_Mealy_Zero_Detector;
wire t_y_out;
reg t_x_in, t_clock, t_reset;
Mealy_Zero_Detector M0 (t_y_out, t_x_in, t_clock, t_reset);
initial 
begin
$dumpfile("test2.vcd");
$dumpvars(0,t_Mealy_Zero_Detector);
end
initial begin t_clock = 0; forever #5 t_clock = ~t_clock; end
initial fork
t_reset = 0;
#2 t_reset = 1;
#87 t_reset = 0;
#89 t_reset = 1;
#10 t_x_in = 1;
#30 t_x_in = 0;
#40 t_x_in = 1;
#50 t_x_in = 0;
#52 t_x_in = 1;
#54 t_x_in = 0;
#70 t_x_in = 1;
#80 t_x_in = 1;
#70 t_x_in = 0;
#90 t_x_in = 1;
#100 t_x_in = 0;
#120 t_x_in = 1;
#160 t_x_in = 0;
#170 t_x_in = 1;
join
initial #200 $finish ;
endmodule
module t_Mealy_Zero_Detector;

wire t_y_out;
reg t_x_in, t_clock, t_reset;
Mealy_Zero_Detector M0 (t_y_out, t_x_in, t_clock, t_reset);
initial 
begin
$dumpfile("test2.vcd");
$dumpvars(0,t_Mealy_Zero_Detector);
end
initial begin t_clock = 0; forever #5 t_clock = ~t_clock; end
initial fork
t_reset = 0;
#2 t_reset = 1;
#87 t_reset = 0;
#89 t_reset = 1;
#10 t_x_in = 1;
#30 t_x_in = 0;
#40 t_x_in = 1;
#50 t_x_in = 0;
#52 t_x_in = 1;
#54 t_x_in = 0;
#70 t_x_in = 1;
#80 t_x_in = 1;
#70 t_x_in = 0;
#90 t_x_in = 1;
#100 t_x_in = 0;
#120 t_x_in = 1;
#160 t_x_in = 0;
#170 t_x_in = 1;
join
initial #200 $finish ;
endmodule