data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/src/fpga/tc_sram_xilinx.sv
1: b"%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/src/fpga/tc_sram_xilinx.sv:110: Cannot find file containing module: 'xpm_memory_tdpram'\n    xpm_memory_tdpram#(\n    ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/src/fpga,data/full_repos/permissive/489147019/xpm_memory_tdpram\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/src/fpga,data/full_repos/permissive/489147019/xpm_memory_tdpram.v\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/src/fpga,data/full_repos/permissive/489147019/xpm_memory_tdpram.sv\n             xpm_memory_tdpram\n             xpm_memory_tdpram.v\n             xpm_memory_tdpram.sv\n             obj_dir/xpm_memory_tdpram\n             obj_dir/xpm_memory_tdpram.v\n             obj_dir/xpm_memory_tdpram.sv\n%Error: Exiting due to 1 error(s)\n"
module tc_sram #(
  parameter int unsigned NumWords     = 32'd1024,
  parameter int unsigned DataWidth    = 32'd128,
  parameter int unsigned ByteWidth    = 32'd8,
  parameter int unsigned NumPorts     = 32'd2,
  parameter int unsigned Latency      = 32'd1,
  parameter              SimInit      = "zeros",
  parameter bit          PrintSimCfg  = 1'b0,

  parameter int unsigned AddrWidth = (NumWords > 32'd1) ? $clog2(NumWords) : 32'd1,
  parameter int unsigned BeWidth   = (DataWidth + ByteWidth - 32'd1) / ByteWidth,
  parameter type         addr_t    = logic [AddrWidth-1:0],
  parameter type         data_t    = logic [DataWidth-1:0],
  parameter type         be_t      = logic [BeWidth-1:0]
) (
  input  logic                clk_i,
  input  logic                rst_ni,

  input  logic  [NumPorts-1:0] req_i,
  input  logic  [NumPorts-1:0] we_i,
  input  addr_t [NumPorts-1:0] addr_i,
  input  data_t [NumPorts-1:0] wdata_i,
  input  be_t   [NumPorts-1:0] be_i,

  output data_t [NumPorts-1:0] rdata_o
);

  localparam int unsigned DataWidthAligned = ByteWidth * BeWidth;
  localparam int unsigned Size             = NumWords * DataWidthAligned;

  typedef logic [DataWidthAligned-1:0] data_aligned_t;

  data_aligned_t [NumPorts-1:0] wdata_al;
  data_aligned_t [NumPorts-1:0] rdata_al;
  be_t           [NumPorts-1:0] we;



  always_comb begin : p_align
    wdata_al = '0;
    for (int unsigned i = 0; i < NumPorts; i++) begin
      wdata_al[i][DataWidth-1:0] = wdata_i[i];
    end
  end

  for (genvar i = 0; i < NumPorts; i++) begin : gen_port_assign
    for (genvar j = 0; j < BeWidth; j++) begin : gen_we_assign
      assign we[i][j] = be_i[i][j] & we_i[i];
    end
    assign rdata_o[i] = data_t'(rdata_al[i]);
  end

  if (NumPorts == 32'd1) begin : gen_1_ports


    xpm_memory_spram#(
      .ADDR_WIDTH_A        ( AddrWidth        ),
      .AUTO_SLEEP_TIME     ( 0                ),
      .BYTE_WRITE_WIDTH_A  ( ByteWidth        ),
      .ECC_MODE            ( "no_ecc"         ),
      .MEMORY_INIT_FILE    ( "none"           ),
      .MEMORY_INIT_PARAM   ( "0"              ),
      .MEMORY_OPTIMIZATION ( "true"           ),
      .MEMORY_PRIMITIVE    ( "auto"           ),
      .MEMORY_SIZE         ( Size             ),
      .MESSAGE_CONTROL     ( 0                ),
      .READ_DATA_WIDTH_A   ( DataWidthAligned ),
      .READ_LATENCY_A      ( Latency          ),
      .READ_RESET_VALUE_A  ( "0"              ),
      .USE_MEM_INIT        ( 1                ),
      .WAKEUP_TIME         ( "disable_sleep"  ),
      .WRITE_DATA_WIDTH_A  ( DataWidthAligned ),
      .WRITE_MODE_A        ( "no_change"      )
    ) i_xpm_memory_spram (
      .dbiterra (),
      .douta    ( rdata_al[0]  ),
      .sbiterra (),
      .addra    ( addr_i[0]    ),
      .clka     ( clk_i        ),
      .dina     ( wdata_al[0]  ),
      .ena      ( req_i[0]     ),
      .injectdbiterra ( 1'b0   ),
      .injectsbiterra ( 1'b0   ),
      .regcea   ( 1'b1         ),
      .rsta     ( ~rst_ni      ),
      .sleep    ( 1'b0         ),
      .wea      ( we[0]        )
    );
  end else if (NumPorts == 32'd2) begin : gen_2_ports


    xpm_memory_tdpram#(
      .ADDR_WIDTH_A            ( AddrWidth        ),
      .ADDR_WIDTH_B            ( AddrWidth        ),
      .AUTO_SLEEP_TIME         ( 0                ),
      .BYTE_WRITE_WIDTH_A      ( ByteWidth        ),
      .BYTE_WRITE_WIDTH_B      ( ByteWidth        ),
      .CLOCKING_MODE           ( "common_clock"   ),
      .ECC_MODE                ( "no_ecc"         ),
      .MEMORY_INIT_FILE        ( "none"           ),
      .MEMORY_INIT_PARAM       ( "0"              ),
      .MEMORY_OPTIMIZATION     ( "true"           ),
      .MEMORY_PRIMITIVE        ( "auto"           ),
      .MEMORY_SIZE             ( Size             ),
      .MESSAGE_CONTROL         ( 0                ),
      .READ_DATA_WIDTH_A       ( DataWidthAligned ),
      .READ_DATA_WIDTH_B       ( DataWidthAligned ),
      .READ_LATENCY_A          ( Latency          ),
      .READ_LATENCY_B          ( Latency          ),
      .READ_RESET_VALUE_A      ( "0"              ),
      .READ_RESET_VALUE_B      ( "0"              ),
      .USE_EMBEDDED_CONSTRAINT ( 0                ),
      .USE_MEM_INIT            ( 1                ),
      .WAKEUP_TIME             ( "disable_sleep"  ),
      .WRITE_DATA_WIDTH_A      ( DataWidthAligned ),
      .WRITE_DATA_WIDTH_B      ( DataWidthAligned ),
      .WRITE_MODE_A            ( "no_change"      ),
      .WRITE_MODE_B            ( "no_change"      )
    ) i_xpm_memory_tdpram (
      .dbiterra (),
      .dbiterrb (),
      .sbiterra (),
      .sbiterrb (),
      .addra    ( addr_i[0]    ),
      .addrb    ( addr_i[1]    ),
      .clka     ( clk_i        ),
      .clkb     ( clk_i        ),
      .dina     ( wdata_al[0]  ),
      .dinb     ( wdata_al[1]  ),
      .douta    ( rdata_al[0]  ),
      .doutb    ( rdata_al[1]  ),
      .ena      ( req_i[0]     ),
      .enb      ( req_i[1]     ),
      .injectdbiterra ( 1'b0   ),
      .injectdbiterrb ( 1'b0   ),
      .injectsbiterra ( 1'b0   ),
      .injectsbiterrb ( 1'b0   ),
      .regcea   ( 1'b1         ),
      .regceb   ( 1'b1         ),
      .rsta     ( ~rst_ni      ),
      .rstb     ( ~rst_ni      ),
      .sleep    ( 1'b0         ),
      .wea      ( we[0]        ),
      .web      ( we[1]        )
    );
  end else begin : gen_err_ports
    $fatal(1, "Not supported port parametrization for NumPorts: %0d", NumPorts);
  end



`ifndef VERILATOR
`ifndef TARGET_SYNTHESYS
  initial begin: p_assertions
    assert (SimInit == "zeros") else $fatal(1, "The Xilinx `tc_sram` has fixed SimInit: zeros");
    assert ($bits(addr_i)  == NumPorts * AddrWidth) else $fatal(1, "AddrWidth problem on `addr_i`");
    assert ($bits(wdata_i) == NumPorts * DataWidth) else $fatal(1, "DataWidth problem on `wdata_i`");
    assert ($bits(be_i)    == NumPorts * BeWidth)   else $fatal(1, "BeWidth   problem on `be_i`"   );
    assert ($bits(rdata_o) == NumPorts * DataWidth) else $fatal(1, "DataWidth problem on `rdata_o`");
    assert (NumWords  >= 32'd1) else $fatal(1, "NumWords has to be > 0");
    assert (DataWidth >= 32'd1) else $fatal(1, "DataWidth has to be > 0");
    assert (ByteWidth >= 32'd1) else $fatal(1, "ByteWidth has to be > 0");
    assert (NumPorts  >= 32'd1) else $fatal(1, "The number of ports must be at least 1!");
  end
  initial begin: p_sim_hello
    if (PrintSimCfg) begin
      $display("#################################################################################");
      $display("tc_sram functional instantiated with the configuration:"                          );
      $display("Instance: %m"                                                                     );
      $display("Number of ports   (dec): %0d", NumPorts                                           );
      $display("Number of words   (dec): %0d", NumWords                                           );
      $display("Address width     (dec): %0d", AddrWidth                                          );
      $display("Data width        (dec): %0d", DataWidth                                          );
      $display("Byte width        (dec): %0d", ByteWidth                                          );
      $display("Byte enable width (dec): %0d", BeWidth                                            );
      $display("Latency Cycles    (dec): %0d", Latency                                            );
      $display("Simulation init   (str): %0s", SimInit                                            );
      $display("#################################################################################");
    end
  end
  for (genvar i = 0; i < NumPorts; i++) begin : gen_assertions
    assert property ( @(posedge clk_i) disable iff (!rst_ni)
        (req_i[i] |-> (addr_i[i] < NumWords))) else
      $warning("Request address %0h not mapped, port %0d, expect random write or read behavior!",
          addr_i[i], i);
  end

`endif
`endif


endmodule
module tc_sram #(
  parameter int unsigned NumWords     = 32'd1024,
  parameter int unsigned DataWidth    = 32'd128,
  parameter int unsigned ByteWidth    = 32'd8,
  parameter int unsigned NumPorts     = 32'd2,
  parameter int unsigned Latency      = 32'd1,
  parameter              SimInit      = "zeros",
  parameter bit          PrintSimCfg  = 1'b0,

  parameter int unsigned AddrWidth = (NumWords > 32'd1) ? $clog2(NumWords) : 32'd1,
  parameter int unsigned BeWidth   = (DataWidth + ByteWidth - 32'd1) / ByteWidth,
  parameter type         addr_t    = logic [AddrWidth-1:0],
  parameter type         data_t    = logic [DataWidth-1:0],
  parameter type         be_t      = logic [BeWidth-1:0]
) (
  input  logic                clk_i,
  input  logic                rst_ni,

  input  logic  [NumPorts-1:0] req_i,
  input  logic  [NumPorts-1:0] we_i,
  input  addr_t [NumPorts-1:0] addr_i,
  input  data_t [NumPorts-1:0] wdata_i,
  input  be_t   [NumPorts-1:0] be_i,

  output data_t [NumPorts-1:0] rdata_o
);


  localparam int unsigned DataWidthAligned = ByteWidth * BeWidth;
  localparam int unsigned Size             = NumWords * DataWidthAligned;

  typedef logic [DataWidthAligned-1:0] data_aligned_t;

  data_aligned_t [NumPorts-1:0] wdata_al;
  data_aligned_t [NumPorts-1:0] rdata_al;
  be_t           [NumPorts-1:0] we;



  always_comb begin : p_align
    wdata_al = '0;
    for (int unsigned i = 0; i < NumPorts; i++) begin
      wdata_al[i][DataWidth-1:0] = wdata_i[i];
    end
  end

  for (genvar i = 0; i < NumPorts; i++) begin : gen_port_assign
    for (genvar j = 0; j < BeWidth; j++) begin : gen_we_assign
      assign we[i][j] = be_i[i][j] & we_i[i];
    end
    assign rdata_o[i] = data_t'(rdata_al[i]);
  end

  if (NumPorts == 32'd1) begin : gen_1_ports


    xpm_memory_spram#(
      .ADDR_WIDTH_A        ( AddrWidth        ),
      .AUTO_SLEEP_TIME     ( 0                ),
      .BYTE_WRITE_WIDTH_A  ( ByteWidth        ),
      .ECC_MODE            ( "no_ecc"         ),
      .MEMORY_INIT_FILE    ( "none"           ),
      .MEMORY_INIT_PARAM   ( "0"              ),
      .MEMORY_OPTIMIZATION ( "true"           ),
      .MEMORY_PRIMITIVE    ( "auto"           ),
      .MEMORY_SIZE         ( Size             ),
      .MESSAGE_CONTROL     ( 0                ),
      .READ_DATA_WIDTH_A   ( DataWidthAligned ),
      .READ_LATENCY_A      ( Latency          ),
      .READ_RESET_VALUE_A  ( "0"              ),
      .USE_MEM_INIT        ( 1                ),
      .WAKEUP_TIME         ( "disable_sleep"  ),
      .WRITE_DATA_WIDTH_A  ( DataWidthAligned ),
      .WRITE_MODE_A        ( "no_change"      )
    ) i_xpm_memory_spram (
      .dbiterra (),
      .douta    ( rdata_al[0]  ),
      .sbiterra (),
      .addra    ( addr_i[0]    ),
      .clka     ( clk_i        ),
      .dina     ( wdata_al[0]  ),
      .ena      ( req_i[0]     ),
      .injectdbiterra ( 1'b0   ),
      .injectsbiterra ( 1'b0   ),
      .regcea   ( 1'b1         ),
      .rsta     ( ~rst_ni      ),
      .sleep    ( 1'b0         ),
      .wea      ( we[0]        )
    );
  end else if (NumPorts == 32'd2) begin : gen_2_ports


    xpm_memory_tdpram#(
      .ADDR_WIDTH_A            ( AddrWidth        ),
      .ADDR_WIDTH_B            ( AddrWidth        ),
      .AUTO_SLEEP_TIME         ( 0                ),
      .BYTE_WRITE_WIDTH_A      ( ByteWidth        ),
      .BYTE_WRITE_WIDTH_B      ( ByteWidth        ),
      .CLOCKING_MODE           ( "common_clock"   ),
      .ECC_MODE                ( "no_ecc"         ),
      .MEMORY_INIT_FILE        ( "none"           ),
      .MEMORY_INIT_PARAM       ( "0"              ),
      .MEMORY_OPTIMIZATION     ( "true"           ),
      .MEMORY_PRIMITIVE        ( "auto"           ),
      .MEMORY_SIZE             ( Size             ),
      .MESSAGE_CONTROL         ( 0                ),
      .READ_DATA_WIDTH_A       ( DataWidthAligned ),
      .READ_DATA_WIDTH_B       ( DataWidthAligned ),
      .READ_LATENCY_A          ( Latency          ),
      .READ_LATENCY_B          ( Latency          ),
      .READ_RESET_VALUE_A      ( "0"              ),
      .READ_RESET_VALUE_B      ( "0"              ),
      .USE_EMBEDDED_CONSTRAINT ( 0                ),
      .USE_MEM_INIT            ( 1                ),
      .WAKEUP_TIME             ( "disable_sleep"  ),
      .WRITE_DATA_WIDTH_A      ( DataWidthAligned ),
      .WRITE_DATA_WIDTH_B      ( DataWidthAligned ),
      .WRITE_MODE_A            ( "no_change"      ),
      .WRITE_MODE_B            ( "no_change"      )
    ) i_xpm_memory_tdpram (
      .dbiterra (),
      .dbiterrb (),
      .sbiterra (),
      .sbiterrb (),
      .addra    ( addr_i[0]    ),
      .addrb    ( addr_i[1]    ),
      .clka     ( clk_i        ),
      .clkb     ( clk_i        ),
      .dina     ( wdata_al[0]  ),
      .dinb     ( wdata_al[1]  ),
      .douta    ( rdata_al[0]  ),
      .doutb    ( rdata_al[1]  ),
      .ena      ( req_i[0]     ),
      .enb      ( req_i[1]     ),
      .injectdbiterra ( 1'b0   ),
      .injectdbiterrb ( 1'b0   ),
      .injectsbiterra ( 1'b0   ),
      .injectsbiterrb ( 1'b0   ),
      .regcea   ( 1'b1         ),
      .regceb   ( 1'b1         ),
      .rsta     ( ~rst_ni      ),
      .rstb     ( ~rst_ni      ),
      .sleep    ( 1'b0         ),
      .wea      ( we[0]        ),
      .web      ( we[1]        )
    );
  end else begin : gen_err_ports
    $fatal(1, "Not supported port parametrization for NumPorts: %0d", NumPorts);
  end



`ifndef VERILATOR
`ifndef TARGET_SYNTHESYS
  initial begin: p_assertions
    assert (SimInit == "zeros") else $fatal(1, "The Xilinx `tc_sram` has fixed SimInit: zeros");
    assert ($bits(addr_i)  == NumPorts * AddrWidth) else $fatal(1, "AddrWidth problem on `addr_i`");
    assert ($bits(wdata_i) == NumPorts * DataWidth) else $fatal(1, "DataWidth problem on `wdata_i`");
    assert ($bits(be_i)    == NumPorts * BeWidth)   else $fatal(1, "BeWidth   problem on `be_i`"   );
    assert ($bits(rdata_o) == NumPorts * DataWidth) else $fatal(1, "DataWidth problem on `rdata_o`");
    assert (NumWords  >= 32'd1) else $fatal(1, "NumWords has to be > 0");
    assert (DataWidth >= 32'd1) else $fatal(1, "DataWidth has to be > 0");
    assert (ByteWidth >= 32'd1) else $fatal(1, "ByteWidth has to be > 0");
    assert (NumPorts  >= 32'd1) else $fatal(1, "The number of ports must be at least 1!");
  end
  initial begin: p_sim_hello
    if (PrintSimCfg) begin
      $display("#################################################################################");
      $display("tc_sram functional instantiated with the configuration:"                          );
      $display("Instance: %m"                                                                     );
      $display("Number of ports   (dec): %0d", NumPorts                                           );
      $display("Number of words   (dec): %0d", NumWords                                           );
      $display("Address width     (dec): %0d", AddrWidth                                          );
      $display("Data width        (dec): %0d", DataWidth                                          );
      $display("Byte width        (dec): %0d", ByteWidth                                          );
      $display("Byte enable width (dec): %0d", BeWidth                                            );
      $display("Latency Cycles    (dec): %0d", Latency                                            );
      $display("Simulation init   (str): %0s", SimInit                                            );
      $display("#################################################################################");
    end
  end
  for (genvar i = 0; i < NumPorts; i++) begin : gen_assertions
    assert property ( @(posedge clk_i) disable iff (!rst_ni)
        (req_i[i] |-> (addr_i[i] < NumWords))) else
      $warning("Request address %0h not mapped, port %0d, expect random write or read behavior!",
          addr_i[i], i);
  end

`endif
`endif


endmodule