data/full_repos/permissive/52900389/FSM_Testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/52900389/FSM_Testbench.v:52: Unsupported: Ignoring delay on this delayed statement.\n forever #5 clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/52900389/FSM_Testbench.v:76: Unsupported: Ignoring delay on this delayed statement.\n  #200\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52900389/FSM_Testbench.v:81: Unsupported: Ignoring delay on this delayed statement.\n  #800\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52900389/FSM_Testbench.v:86: Unsupported: Ignoring delay on this delayed statement.\n  #800\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52900389/FSM_Testbench.v:91: Unsupported: Ignoring delay on this delayed statement.\n  #800\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/52900389/FSM_Testbench.v:96: Unsupported: Ignoring delay on this delayed statement.\n  #1000 $stop;\n  ^\n%Error: data/full_repos/permissive/52900389/FSM_Testbench.v:39: Cannot find file containing module: \'FSM\'\n FSM uut (\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/52900389,data/full_repos/permissive/52900389/FSM\n             data/full_repos/permissive/52900389,data/full_repos/permissive/52900389/FSM.v\n             data/full_repos/permissive/52900389,data/full_repos/permissive/52900389/FSM.sv\n             FSM\n             FSM.v\n             FSM.sv\n             obj_dir/FSM\n             obj_dir/FSM.v\n             obj_dir/FSM.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module FSM_Testbench;


	reg clk;
	reg rst;
	reg Funct_Select;
	reg [3:0] Count_CT;
	reg [3:0] Count_F;


	wire [3:0] C_Digit;
	wire [3:0] C_7Seg;


	FSM uut (
		.clk(clk), 
		.rst(rst), 
		.Funct_Select(Funct_Select), 
		.Count_CT(Count_CT), 
		.Count_F(Count_F), 
		.C_Digit(C_Digit), 
		.C_7Seg(C_7Seg)
	);
	

	initial begin
	clk = 0;
	forever #5 clk = ~clk;
	end

	initial begin

		clk = 0;
		rst = 0;
		Funct_Select = 0;
		Count_CT = 0;
		Count_F = 0;
	
		end



        

		
	initial begin
	
		rst = 1;
		Funct_Select = 1'b0;
		Count_CT = 4'b0000;
		Count_F = 4'b0000;
		#200
		rst = 0;
		Funct_Select = 1'b0;
		Count_CT = 4'b0000;
		Count_F = 4'b0000;
		#800
		rst = 0;
		Funct_Select = 1'b1;
		Count_CT = 4'b0000;
		Count_F = 4'b0000;
		#800
		rst = 0;
		Funct_Select = 1'b0;
		Count_CT = 4'b0001;
		Count_F = 4'b0001;
		#800
		rst = 0;
		Funct_Select = 1'b1;
		Count_CT = 4'b0001;
		Count_F = 4'b0001;
		#1000 $stop;
		
	end
	

	
endmodule
module FSM_Testbench;



	reg clk;
	reg rst;
	reg Funct_Select;
	reg [3:0] Count_CT;
	reg [3:0] Count_F;


	wire [3:0] C_Digit;
	wire [3:0] C_7Seg;


	FSM uut (
		.clk(clk), 
		.rst(rst), 
		.Funct_Select(Funct_Select), 
		.Count_CT(Count_CT), 
		.Count_F(Count_F), 
		.C_Digit(C_Digit), 
		.C_7Seg(C_7Seg)
	);
	

	initial begin
	clk = 0;
	forever #5 clk = ~clk;
	end

	initial begin

		clk = 0;
		rst = 0;
		Funct_Select = 0;
		Count_CT = 0;
		Count_F = 0;
	
		end



        

		
	initial begin
	
		rst = 1;
		Funct_Select = 1'b0;
		Count_CT = 4'b0000;
		Count_F = 4'b0000;
		#200
		rst = 0;
		Funct_Select = 1'b0;
		Count_CT = 4'b0000;
		Count_F = 4'b0000;
		#800
		rst = 0;
		Funct_Select = 1'b1;
		Count_CT = 4'b0000;
		Count_F = 4'b0000;
		#800
		rst = 0;
		Funct_Select = 1'b0;
		Count_CT = 4'b0001;
		Count_F = 4'b0001;
		#800
		rst = 0;
		Funct_Select = 1'b1;
		Count_CT = 4'b0001;
		Count_F = 4'b0001;
		#1000 $stop;
		
	end
	

	
endmodule