data/full_repos/permissive/441359809/src/yosys/tests/simple/vloghammer.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/tests/simple/vloghammer.v:11: Multiple top level modules\n                                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                              : ... Top module \'test01\'\nmodule test01(a, y);\n       ^~~~~~\n                                                                                              : ... Top module \'test02\'\nmodule test02(a, y);\n       ^~~~~~\n                                                                                              : ... Top module \'test03\'\nmodule test03(a, b, y);\n       ^~~~~~\n                                                                                              : ... Top module \'test04\'\nmodule test04(a, y);\n       ^~~~~~\n                                                                                              : ... Top module \'test07\'\nmodule test07(a, b, y);\n       ^~~~~~\n                                                                                              : ... Top module \'test08\'\nmodule test08(a, b, y);\n       ^~~~~~\n                                                                                              : ... Top module \'test09\'\nmodule test09(a, b, c, y);\n       ^~~~~~\n                                                                                              : ... Top module \'test10\'\nmodule test10(a, b, c, y);\n       ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/vloghammer.v:73: Operator COND expects 3 bits on the Conditional True, but Conditional True\'s VARREF \'b\' generates 2 bits.\n                                                                                           : ... In instance test10\n  assign y = ^(a ? b : c);\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/vloghammer.v:65: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s VARREF \'b\' generates 2 bits.\n                                                                                           : ... In instance test09\n  assign y = a ? b : c;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/vloghammer.v:65: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s VARREF \'c\' generates 3 bits.\n                                                                                           : ... In instance test09\n  assign y = a ? b : c;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/vloghammer.v:50: Operator NEQ expects 3 bits on the LHS, but LHS\'s CONST \'2\'h3\' generates 2 bits.\n                                                                                           : ... In instance test07\n  assign y = 2\'b11 != a+b;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/vloghammer.v:21: Operator EQ expects 3 bits on the RHS, but RHS\'s VARREF \'b\' generates 2 bits.\n                                                                                           : ... In instance test03\n  assign y = ~(a >>> 1) == b;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/vloghammer.v:14: Operator NOT expects 5 bits on the LHS, but LHS\'s VARREF \'a\' generates 4 bits.\n                                                                                           : ... In instance test02\n  assign y = (~a) >> 1;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/vloghammer.v:8: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 8 bits.\n                                                                                          : ... In instance test01\n  assign y = ~a >> 4;\n           ^\n%Error: Exiting due to 8 warning(s)\n'
module test02(a, y);
  input signed [3:0] a;
  output signed [4:0] y;
  assign y = (~a) >> 1;
endmodule
module test02(a, y);

  input signed [3:0] a;
  output signed [4:0] y;
  assign y = (~a) >> 1;
endmodule