data/full_repos/permissive/515598112/3_Circuits/01_Combinational_Logic/04_Karnaugh_Map_to_Circuits/04_4-variable.v
data/verilator_xmls/f3c6504d-9683-4f8e-b0de-d321e374b486.xml
module top_module(
    input a,
    input b,
    input c,
    input d,
    output out
);
    
    assign out = (a ~^ b) ^ (c ~^ d);

endmodule
module top_module(
    input a,
    input b,
    input c,
    input d,
    output out
);

    
    assign out = (a ~^ b) ^ (c ~^ d);

endmodule