data/full_repos/permissive/43974493/src/sdcard_reader.v
1: b'%Error: data/full_repos/permissive/43974493/src/sdcard_reader.v:16: Cannot find include file: definitions.vh\n`include "definitions.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43974493/src,data/full_repos/permissive/43974493/definitions.vh\n             data/full_repos/permissive/43974493/src,data/full_repos/permissive/43974493/definitions.vh.v\n             data/full_repos/permissive/43974493/src,data/full_repos/permissive/43974493/definitions.vh.sv\n             definitions.vh\n             definitions.vh.v\n             definitions.vh.sv\n             obj_dir/definitions.vh\n             obj_dir/definitions.vh.v\n             obj_dir/definitions.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module sdcard_reader
  (
   input             clk,
   input             calib_done,
   input             disabled,
   input [7:0]       program_index,
   output reg        started,
   output reg        done,
   output reg [7:0]  progress,
   output reg        error,

   output reg        sdcard_cs,
   output reg        sdcard_sclk,
   output            sdcard_mosi,
   input             sdcard_miso,

   output            mem_cmd_en,
   output [2:0]      mem_cmd_instr,
   output [5:0]      mem_cmd_bl,
   output     [29:0] mem_cmd_byte_addr,
   input             mem_cmd_empty,
   input             mem_cmd_full,
   output            mem_wr_en,
   output [3:0]      mem_wr_mask,
   output     [31:0] mem_wr_data,
   input             mem_wr_full,
   input             mem_wr_empty,
   input [6:0]       mem_wr_count,
   input             mem_wr_underrun,
   input             mem_wr_error
   );


   initial begin
      started = 0;
      done = 0;
      progress = 0;
      error = 0;
      sdcard_cs = 1;
      sdcard_sclk = 1;
   end


   reg [8:0] sclk_counter = 0;
   reg [8:0] sclk_div = 250;
   reg       sclk_reset = 0;
   reg       sclk_posedge = 0;
   reg       sclk_negedge = 0;
   always @ (posedge clk) begin
      sclk_posedge <= 0;
      sclk_negedge <= 0;
      if (sclk_reset || sclk_div - 1 == sclk_counter) begin
         sclk_counter <= 0;
         if (sdcard_sclk) begin
            sclk_negedge <= 1;
         end
         sdcard_sclk <= 0;
      end else begin
         sclk_counter <= sclk_counter + 1;

         if ((sclk_div >> 1) - 1 == sclk_counter) begin
            sclk_posedge <= 1;
            sdcard_sclk <= 1;
         end
      end
   end



   localparam                          POWER_COUNTER_MAX = 150000;
   reg                                 power_on_done = 0;
   reg [$clog2(POWER_COUNTER_MAX)-1:0] power_on_counter = 0;
   always @ (posedge clk) begin
      if (power_on_counter == POWER_COUNTER_MAX - 1) begin
         power_on_done <= 1;
      end else begin
         power_on_counter <= power_on_counter + 1;
      end
   end


   localparam          CMD_BITS = 48;
   reg                 spi_cmd_send_reset = 0;
   reg                 spi_cmd_send_en = 0;
   reg [5:0]           spi_cmd_send_index = 0;
   reg [31:0]          spi_cmd_send_arg = 0;
   reg [6:0]           spi_cmd_send_crc = 0;
   wire [CMD_BITS-1:0] spi_cmd_send_data = {
      2'b01, spi_cmd_send_index,
      spi_cmd_send_arg, spi_cmd_send_crc, 1'b1
   };
   wire                spi_cmd_send_done;
   spi_sender #(.DATA_BITS(CMD_BITS)) spi_cmd_sender_
     (
      .clk(clk),
      .sclk_posedge(sclk_posedge),
      .sclk_negedge(sclk_negedge),
      .reset(spi_cmd_send_reset),
      .en(spi_cmd_send_en),
      .data(spi_cmd_send_data),
      .out(sdcard_mosi),
      .done(spi_cmd_send_done)
      );


   localparam         R1_BITS = 8;
   reg                spi_r1_recv_reset = 0;
   reg                spi_r1_recv_en = 0;
   wire [R1_BITS-1:0] spi_r1_recv_out;
   wire               spi_r1_recv_done;
   spi_receiver #(.DATA_BITS(R1_BITS)) spi_r1_receiver_
     (
      .clk(clk),
      .sclk_posedge(sclk_posedge),
      .sclk_negedge(sclk_negedge),
      .reset(spi_r1_recv_reset),
      .en(spi_r1_recv_en),
      .in(sdcard_miso),
      .out(spi_r1_recv_out),
      .done(spi_r1_recv_done)
      );



   localparam            R3_R7_BITS = 40;
   reg                   spi_r3_r7_recv_reset = 0;
   reg                   spi_r3_r7_recv_en = 0;
   wire [R3_R7_BITS-1:0] spi_r3_r7_recv_out;
   wire                  spi_r3_r7_recv_done;
   spi_receiver #(.DATA_BITS(R3_R7_BITS)) spi_r3_r7_receiver_
     (
      .clk(clk),
      .sclk_posedge(sclk_posedge),
      .sclk_negedge(sclk_negedge),
      .reset(spi_r3_r7_recv_reset),
      .en(spi_r3_r7_recv_en),
      .in(sdcard_miso),
      .out(spi_r3_r7_recv_out),
      .done(spi_r3_r7_recv_done)
      );


   reg [6:0]             block_addr = 0;
   reg                   spi_data_read_en = 0;
   wire                  spi_data_read_error;
   wire                  spi_data_read_done;
   spi_data_reader spi_data_reader_
     (
      .clk(clk),
      .calib_done(calib_done),
      .sclk_posedge(sclk_posedge),
      .sclk_negedge(sclk_negedge),
      .block_addr(block_addr),
      .en(spi_data_read_en),
      .in(sdcard_miso),
      .error(spi_data_read_error),
      .done(spi_data_read_done),
      .mem_cmd_en(mem_cmd_en),
      .mem_cmd_instr(mem_cmd_instr),
      .mem_cmd_bl(mem_cmd_bl),
      .mem_cmd_byte_addr(mem_cmd_byte_addr),
      .mem_cmd_empty(mem_cmd_empty),
      .mem_cmd_full(mem_cmd_full),
      .mem_wr_en(mem_wr_en),
      .mem_wr_mask(mem_wr_mask),
      .mem_wr_data(mem_wr_data),
      .mem_wr_full(mem_wr_full),
      .mem_wr_empty(mem_wr_empty),
      .mem_wr_count(mem_wr_count),
      .mem_wr_underrun(mem_wr_underrun),
      .mem_wr_error(mem_wr_error)
      );


   localparam STATE_POWER_ON    = 0;
   localparam STATE_DUMMY_CLK   = 1;
   localparam STATE_0xFF_WAIT   = 2;
   localparam STATE_R1_SEND     = 3;
   localparam STATE_R3_R7_SEND  = 4;
   localparam STATE_CMD0_SEND   = 5;
   localparam STATE_CMD0_RECV   = 6;
   localparam STATE_CMD8_SEND   = 7;
   localparam STATE_CMD8_RECV   = 8;
   localparam STATE_CMD55_SEND  = 9;
   localparam STATE_CMD55_RECV  = 10;
   localparam STATE_ACMD41_SEND = 11;
   localparam STATE_ACMD41_RECV = 12;
   localparam STATE_CMD58_SEND  = 13;
   localparam STATE_CMD58_RECV  = 14;
   localparam STATE_CALIB_WAIT  = 15;
   localparam STATE_CMD17_SEND  = 16;
   localparam STATE_CMD17_RECV  = 17;
   localparam STATE_DATA_RECV   = 18;
   localparam STATE_DONE        = 254;
   localparam STATE_ERROR       = 255;
   reg [7:0] state = STATE_POWER_ON;
   reg [7:0] next_state;
   reg [7:0] dummy_clk_counter = 0;
   reg [7:0] miso_ready_counter = 0;
   always @ (posedge clk) begin
      sclk_reset <= 0;
      spi_cmd_send_en <= 0;
      spi_cmd_send_reset <= 0;
      spi_r1_recv_en <= 0;
      spi_r1_recv_reset <= 0;
      spi_r3_r7_recv_en <= 0;
      spi_r3_r7_recv_reset <= 0;
      spi_data_read_en <= 0;
      case (state)

         STATE_POWER_ON: begin
            sclk_reset <= 1;
            sdcard_cs <= 1;
            if (power_on_done) begin
               state <= STATE_DUMMY_CLK;
            end
         end


         STATE_DUMMY_CLK: begin
            sdcard_cs <= 1;
            if (sdcard_miso && sclk_negedge && 74 <= dummy_clk_counter) begin
               state <= STATE_CMD0_SEND;
            end else if (sclk_posedge) begin
               dummy_clk_counter <= dummy_clk_counter + 1;
            end
         end

         STATE_0xFF_WAIT: begin
            if (sclk_posedge) begin
               if (sdcard_miso) begin
                  if (7 == miso_ready_counter) begin
                     miso_ready_counter <= 0;
                     state <= next_state;
                  end else begin
                     miso_ready_counter <= miso_ready_counter + 1;
                  end
               end else begin
                  miso_ready_counter <= 0;
               end
            end
         end

         STATE_R1_SEND: begin
            if (spi_cmd_send_done) begin
               spi_r1_recv_en <= 1;
               state <= next_state;
            end
         end

         STATE_R3_R7_SEND: begin
            if (spi_cmd_send_done) begin
               spi_r3_r7_recv_en <= 1;
               state <= next_state;
            end
         end

         STATE_CMD0_SEND: begin

            sclk_div <= 10;

            sdcard_cs <= 0;

            spi_cmd_send_index <= 6'd0;
            spi_cmd_send_arg <= 32'h00000000;
            spi_cmd_send_crc <= 7'b1001010;

            spi_cmd_send_en <= 1;
            state <= STATE_R1_SEND;
            next_state <= STATE_CMD0_RECV;
         end

         STATE_CMD0_RECV: begin
            if (spi_r1_recv_done && !disabled) begin
               started <= 1;

               if (8'b1 == spi_r1_recv_out) begin
                  state <= STATE_0xFF_WAIT;
                  next_state <= STATE_CMD8_SEND;
               end else begin
                  state <= STATE_ERROR;
               end
            end
         end

         STATE_CMD8_SEND: begin

            spi_cmd_send_index <= 6'd8;
            spi_cmd_send_arg <= 32'h000001AA;
            spi_cmd_send_crc <= 7'b1000011;

            spi_cmd_send_en <= 1;
            state <= STATE_R3_R7_SEND;
            next_state <= STATE_CMD8_RECV;
         end



         STATE_CMD8_RECV: begin
            if (spi_r3_r7_recv_done) begin
               if (40'h01000001AA == spi_r3_r7_recv_out) begin
                  state <= STATE_0xFF_WAIT;
                  next_state <= STATE_CMD55_SEND;
               end else begin
                  state <= STATE_ERROR;
               end
            end
         end

         STATE_CMD55_SEND: begin
            spi_cmd_send_index <= 6'd55;
            spi_cmd_send_arg <= 32'h00000000;
            spi_cmd_send_crc <= 7'b0000000;
            spi_cmd_send_en <= 1;
            state <= STATE_R1_SEND;
            next_state <= STATE_CMD55_RECV;
         end

         STATE_CMD55_RECV: begin
            if (spi_r1_recv_done) begin
               if (8'b1 == spi_r1_recv_out) begin
                  state <= STATE_0xFF_WAIT;
                  next_state <= STATE_ACMD41_SEND;
               end else begin
                  state <= STATE_ERROR;
               end
            end
         end

         STATE_ACMD41_SEND: begin
            spi_cmd_send_index <= 6'd41;
            spi_cmd_send_arg <= 32'h40000000;
            spi_cmd_send_crc <= 7'b0000000;
            spi_cmd_send_en <= 1;
            state <= STATE_R1_SEND;
            next_state <= STATE_ACMD41_RECV;
         end


         STATE_ACMD41_RECV: begin
            if (spi_r1_recv_done) begin
               if (8'b1 == spi_r1_recv_out) begin
                  state <= STATE_0xFF_WAIT;
                  next_state <= STATE_CMD55_SEND;
               end else if (8'b0 == spi_r1_recv_out) begin
                  state <= STATE_0xFF_WAIT;
                  next_state <= STATE_CMD58_SEND;
               end else begin
                  state <= STATE_ERROR;
               end
            end
         end

         STATE_CMD58_SEND: begin
            spi_cmd_send_index <= 6'd58;
            spi_cmd_send_arg <= 32'h00000000;
            spi_cmd_send_crc <= 7'b0000000;
            spi_cmd_send_en <= 1;
            state <= STATE_R3_R7_SEND;
            next_state <= STATE_CMD58_RECV;
         end



         STATE_CMD58_RECV: begin
            if (spi_r3_r7_recv_done) begin
               if (8'b0 == spi_r3_r7_recv_out[39:32] &&
                   spi_r3_r7_recv_out[30]) begin
                  state <= STATE_CALIB_WAIT;
               end else begin
                  state <= STATE_ERROR;
               end
            end
         end


         STATE_CALIB_WAIT: begin
            if (calib_done) begin
               state <= STATE_0xFF_WAIT;
               next_state <= STATE_CMD17_SEND;
            end
         end

         STATE_CMD17_SEND: begin
            spi_cmd_send_index <= 6'd17;
            spi_cmd_send_arg <= { 17'b0, program_index, block_addr };
            spi_cmd_send_crc <= 7'b0000000;
            spi_cmd_send_en <= 1;
            state <= STATE_R1_SEND;
            next_state <= STATE_CMD17_RECV;
         end


         STATE_CMD17_RECV: begin
            if (spi_r1_recv_done) begin
               if (8'b0 == spi_r1_recv_out) begin
                  spi_data_read_en <= 1;
                  state <= STATE_DATA_RECV;
               end else begin
                  state <= STATE_ERROR;
               end
            end
         end

         STATE_DATA_RECV: begin
            if (spi_data_read_error) begin
               state <= STATE_ERROR;
            end else if (spi_data_read_done) begin
               progress <= progress + 2;
               if (127 == block_addr) begin
                  state <= STATE_DONE;
               end else begin
                  block_addr <= block_addr + 1;
                  state <= STATE_0xFF_WAIT;
                  next_state <= STATE_CMD17_SEND;
               end
            end
         end

         STATE_DONE: begin
            sclk_reset <= 1;
            sdcard_cs <= 1;
            done <= 1;
         end

         STATE_ERROR: begin
            sclk_reset <= 1;
            sdcard_cs <= 1;
            error <= 1;
         end
      endcase
   end

endmodule
module sdcard_reader
  (
   input             clk,
   input             calib_done,
   input             disabled,
   input [7:0]       program_index,
   output reg        started,
   output reg        done,
   output reg [7:0]  progress,
   output reg        error,

   output reg        sdcard_cs,
   output reg        sdcard_sclk,
   output            sdcard_mosi,
   input             sdcard_miso,

   output            mem_cmd_en,
   output [2:0]      mem_cmd_instr,
   output [5:0]      mem_cmd_bl,
   output     [29:0] mem_cmd_byte_addr,
   input             mem_cmd_empty,
   input             mem_cmd_full,
   output            mem_wr_en,
   output [3:0]      mem_wr_mask,
   output     [31:0] mem_wr_data,
   input             mem_wr_full,
   input             mem_wr_empty,
   input [6:0]       mem_wr_count,
   input             mem_wr_underrun,
   input             mem_wr_error
   );



   initial begin
      started = 0;
      done = 0;
      progress = 0;
      error = 0;
      sdcard_cs = 1;
      sdcard_sclk = 1;
   end


   reg [8:0] sclk_counter = 0;
   reg [8:0] sclk_div = 250;
   reg       sclk_reset = 0;
   reg       sclk_posedge = 0;
   reg       sclk_negedge = 0;
   always @ (posedge clk) begin
      sclk_posedge <= 0;
      sclk_negedge <= 0;
      if (sclk_reset || sclk_div - 1 == sclk_counter) begin
         sclk_counter <= 0;
         if (sdcard_sclk) begin
            sclk_negedge <= 1;
         end
         sdcard_sclk <= 0;
      end else begin
         sclk_counter <= sclk_counter + 1;

         if ((sclk_div >> 1) - 1 == sclk_counter) begin
            sclk_posedge <= 1;
            sdcard_sclk <= 1;
         end
      end
   end



   localparam                          POWER_COUNTER_MAX = 150000;
   reg                                 power_on_done = 0;
   reg [$clog2(POWER_COUNTER_MAX)-1:0] power_on_counter = 0;
   always @ (posedge clk) begin
      if (power_on_counter == POWER_COUNTER_MAX - 1) begin
         power_on_done <= 1;
      end else begin
         power_on_counter <= power_on_counter + 1;
      end
   end


   localparam          CMD_BITS = 48;
   reg                 spi_cmd_send_reset = 0;
   reg                 spi_cmd_send_en = 0;
   reg [5:0]           spi_cmd_send_index = 0;
   reg [31:0]          spi_cmd_send_arg = 0;
   reg [6:0]           spi_cmd_send_crc = 0;
   wire [CMD_BITS-1:0] spi_cmd_send_data = {
      2'b01, spi_cmd_send_index,
      spi_cmd_send_arg, spi_cmd_send_crc, 1'b1
   };
   wire                spi_cmd_send_done;
   spi_sender #(.DATA_BITS(CMD_BITS)) spi_cmd_sender_
     (
      .clk(clk),
      .sclk_posedge(sclk_posedge),
      .sclk_negedge(sclk_negedge),
      .reset(spi_cmd_send_reset),
      .en(spi_cmd_send_en),
      .data(spi_cmd_send_data),
      .out(sdcard_mosi),
      .done(spi_cmd_send_done)
      );


   localparam         R1_BITS = 8;
   reg                spi_r1_recv_reset = 0;
   reg                spi_r1_recv_en = 0;
   wire [R1_BITS-1:0] spi_r1_recv_out;
   wire               spi_r1_recv_done;
   spi_receiver #(.DATA_BITS(R1_BITS)) spi_r1_receiver_
     (
      .clk(clk),
      .sclk_posedge(sclk_posedge),
      .sclk_negedge(sclk_negedge),
      .reset(spi_r1_recv_reset),
      .en(spi_r1_recv_en),
      .in(sdcard_miso),
      .out(spi_r1_recv_out),
      .done(spi_r1_recv_done)
      );



   localparam            R3_R7_BITS = 40;
   reg                   spi_r3_r7_recv_reset = 0;
   reg                   spi_r3_r7_recv_en = 0;
   wire [R3_R7_BITS-1:0] spi_r3_r7_recv_out;
   wire                  spi_r3_r7_recv_done;
   spi_receiver #(.DATA_BITS(R3_R7_BITS)) spi_r3_r7_receiver_
     (
      .clk(clk),
      .sclk_posedge(sclk_posedge),
      .sclk_negedge(sclk_negedge),
      .reset(spi_r3_r7_recv_reset),
      .en(spi_r3_r7_recv_en),
      .in(sdcard_miso),
      .out(spi_r3_r7_recv_out),
      .done(spi_r3_r7_recv_done)
      );


   reg [6:0]             block_addr = 0;
   reg                   spi_data_read_en = 0;
   wire                  spi_data_read_error;
   wire                  spi_data_read_done;
   spi_data_reader spi_data_reader_
     (
      .clk(clk),
      .calib_done(calib_done),
      .sclk_posedge(sclk_posedge),
      .sclk_negedge(sclk_negedge),
      .block_addr(block_addr),
      .en(spi_data_read_en),
      .in(sdcard_miso),
      .error(spi_data_read_error),
      .done(spi_data_read_done),
      .mem_cmd_en(mem_cmd_en),
      .mem_cmd_instr(mem_cmd_instr),
      .mem_cmd_bl(mem_cmd_bl),
      .mem_cmd_byte_addr(mem_cmd_byte_addr),
      .mem_cmd_empty(mem_cmd_empty),
      .mem_cmd_full(mem_cmd_full),
      .mem_wr_en(mem_wr_en),
      .mem_wr_mask(mem_wr_mask),
      .mem_wr_data(mem_wr_data),
      .mem_wr_full(mem_wr_full),
      .mem_wr_empty(mem_wr_empty),
      .mem_wr_count(mem_wr_count),
      .mem_wr_underrun(mem_wr_underrun),
      .mem_wr_error(mem_wr_error)
      );


   localparam STATE_POWER_ON    = 0;
   localparam STATE_DUMMY_CLK   = 1;
   localparam STATE_0xFF_WAIT   = 2;
   localparam STATE_R1_SEND     = 3;
   localparam STATE_R3_R7_SEND  = 4;
   localparam STATE_CMD0_SEND   = 5;
   localparam STATE_CMD0_RECV   = 6;
   localparam STATE_CMD8_SEND   = 7;
   localparam STATE_CMD8_RECV   = 8;
   localparam STATE_CMD55_SEND  = 9;
   localparam STATE_CMD55_RECV  = 10;
   localparam STATE_ACMD41_SEND = 11;
   localparam STATE_ACMD41_RECV = 12;
   localparam STATE_CMD58_SEND  = 13;
   localparam STATE_CMD58_RECV  = 14;
   localparam STATE_CALIB_WAIT  = 15;
   localparam STATE_CMD17_SEND  = 16;
   localparam STATE_CMD17_RECV  = 17;
   localparam STATE_DATA_RECV   = 18;
   localparam STATE_DONE        = 254;
   localparam STATE_ERROR       = 255;
   reg [7:0] state = STATE_POWER_ON;
   reg [7:0] next_state;
   reg [7:0] dummy_clk_counter = 0;
   reg [7:0] miso_ready_counter = 0;
   always @ (posedge clk) begin
      sclk_reset <= 0;
      spi_cmd_send_en <= 0;
      spi_cmd_send_reset <= 0;
      spi_r1_recv_en <= 0;
      spi_r1_recv_reset <= 0;
      spi_r3_r7_recv_en <= 0;
      spi_r3_r7_recv_reset <= 0;
      spi_data_read_en <= 0;
      case (state)

         STATE_POWER_ON: begin
            sclk_reset <= 1;
            sdcard_cs <= 1;
            if (power_on_done) begin
               state <= STATE_DUMMY_CLK;
            end
         end


         STATE_DUMMY_CLK: begin
            sdcard_cs <= 1;
            if (sdcard_miso && sclk_negedge && 74 <= dummy_clk_counter) begin
               state <= STATE_CMD0_SEND;
            end else if (sclk_posedge) begin
               dummy_clk_counter <= dummy_clk_counter + 1;
            end
         end

         STATE_0xFF_WAIT: begin
            if (sclk_posedge) begin
               if (sdcard_miso) begin
                  if (7 == miso_ready_counter) begin
                     miso_ready_counter <= 0;
                     state <= next_state;
                  end else begin
                     miso_ready_counter <= miso_ready_counter + 1;
                  end
               end else begin
                  miso_ready_counter <= 0;
               end
            end
         end

         STATE_R1_SEND: begin
            if (spi_cmd_send_done) begin
               spi_r1_recv_en <= 1;
               state <= next_state;
            end
         end

         STATE_R3_R7_SEND: begin
            if (spi_cmd_send_done) begin
               spi_r3_r7_recv_en <= 1;
               state <= next_state;
            end
         end

         STATE_CMD0_SEND: begin

            sclk_div <= 10;

            sdcard_cs <= 0;

            spi_cmd_send_index <= 6'd0;
            spi_cmd_send_arg <= 32'h00000000;
            spi_cmd_send_crc <= 7'b1001010;

            spi_cmd_send_en <= 1;
            state <= STATE_R1_SEND;
            next_state <= STATE_CMD0_RECV;
         end

         STATE_CMD0_RECV: begin
            if (spi_r1_recv_done && !disabled) begin
               started <= 1;

               if (8'b1 == spi_r1_recv_out) begin
                  state <= STATE_0xFF_WAIT;
                  next_state <= STATE_CMD8_SEND;
               end else begin
                  state <= STATE_ERROR;
               end
            end
         end

         STATE_CMD8_SEND: begin

            spi_cmd_send_index <= 6'd8;
            spi_cmd_send_arg <= 32'h000001AA;
            spi_cmd_send_crc <= 7'b1000011;

            spi_cmd_send_en <= 1;
            state <= STATE_R3_R7_SEND;
            next_state <= STATE_CMD8_RECV;
         end



         STATE_CMD8_RECV: begin
            if (spi_r3_r7_recv_done) begin
               if (40'h01000001AA == spi_r3_r7_recv_out) begin
                  state <= STATE_0xFF_WAIT;
                  next_state <= STATE_CMD55_SEND;
               end else begin
                  state <= STATE_ERROR;
               end
            end
         end

         STATE_CMD55_SEND: begin
            spi_cmd_send_index <= 6'd55;
            spi_cmd_send_arg <= 32'h00000000;
            spi_cmd_send_crc <= 7'b0000000;
            spi_cmd_send_en <= 1;
            state <= STATE_R1_SEND;
            next_state <= STATE_CMD55_RECV;
         end

         STATE_CMD55_RECV: begin
            if (spi_r1_recv_done) begin
               if (8'b1 == spi_r1_recv_out) begin
                  state <= STATE_0xFF_WAIT;
                  next_state <= STATE_ACMD41_SEND;
               end else begin
                  state <= STATE_ERROR;
               end
            end
         end

         STATE_ACMD41_SEND: begin
            spi_cmd_send_index <= 6'd41;
            spi_cmd_send_arg <= 32'h40000000;
            spi_cmd_send_crc <= 7'b0000000;
            spi_cmd_send_en <= 1;
            state <= STATE_R1_SEND;
            next_state <= STATE_ACMD41_RECV;
         end


         STATE_ACMD41_RECV: begin
            if (spi_r1_recv_done) begin
               if (8'b1 == spi_r1_recv_out) begin
                  state <= STATE_0xFF_WAIT;
                  next_state <= STATE_CMD55_SEND;
               end else if (8'b0 == spi_r1_recv_out) begin
                  state <= STATE_0xFF_WAIT;
                  next_state <= STATE_CMD58_SEND;
               end else begin
                  state <= STATE_ERROR;
               end
            end
         end

         STATE_CMD58_SEND: begin
            spi_cmd_send_index <= 6'd58;
            spi_cmd_send_arg <= 32'h00000000;
            spi_cmd_send_crc <= 7'b0000000;
            spi_cmd_send_en <= 1;
            state <= STATE_R3_R7_SEND;
            next_state <= STATE_CMD58_RECV;
         end



         STATE_CMD58_RECV: begin
            if (spi_r3_r7_recv_done) begin
               if (8'b0 == spi_r3_r7_recv_out[39:32] &&
                   spi_r3_r7_recv_out[30]) begin
                  state <= STATE_CALIB_WAIT;
               end else begin
                  state <= STATE_ERROR;
               end
            end
         end


         STATE_CALIB_WAIT: begin
            if (calib_done) begin
               state <= STATE_0xFF_WAIT;
               next_state <= STATE_CMD17_SEND;
            end
         end

         STATE_CMD17_SEND: begin
            spi_cmd_send_index <= 6'd17;
            spi_cmd_send_arg <= { 17'b0, program_index, block_addr };
            spi_cmd_send_crc <= 7'b0000000;
            spi_cmd_send_en <= 1;
            state <= STATE_R1_SEND;
            next_state <= STATE_CMD17_RECV;
         end


         STATE_CMD17_RECV: begin
            if (spi_r1_recv_done) begin
               if (8'b0 == spi_r1_recv_out) begin
                  spi_data_read_en <= 1;
                  state <= STATE_DATA_RECV;
               end else begin
                  state <= STATE_ERROR;
               end
            end
         end

         STATE_DATA_RECV: begin
            if (spi_data_read_error) begin
               state <= STATE_ERROR;
            end else if (spi_data_read_done) begin
               progress <= progress + 2;
               if (127 == block_addr) begin
                  state <= STATE_DONE;
               end else begin
                  block_addr <= block_addr + 1;
                  state <= STATE_0xFF_WAIT;
                  next_state <= STATE_CMD17_SEND;
               end
            end
         end

         STATE_DONE: begin
            sclk_reset <= 1;
            sdcard_cs <= 1;
            done <= 1;
         end

         STATE_ERROR: begin
            sclk_reset <= 1;
            sdcard_cs <= 1;
            error <= 1;
         end
      endcase
   end

endmodule