data/full_repos/permissive/424312442/HW3/Question 1/HW3_1.v
1: b'%Error: Cannot find file containing module: 1,data/full_repos/permissive/424312442\n        ... Looked in:\n             data/full_repos/permissive/424312442/HW3/Question/1,data/full_repos/permissive/424312442\n             data/full_repos/permissive/424312442/HW3/Question/1,data/full_repos/permissive/424312442.v\n             data/full_repos/permissive/424312442/HW3/Question/1,data/full_repos/permissive/424312442.sv\n             1,data/full_repos/permissive/424312442\n             1,data/full_repos/permissive/424312442.v\n             1,data/full_repos/permissive/424312442.sv\n             obj_dir/1,data/full_repos/permissive/424312442\n             obj_dir/1,data/full_repos/permissive/424312442.v\n             obj_dir/1,data/full_repos/permissive/424312442.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/424312442/HW3/Question\n%Error: Cannot find file containing module: 1/HW3_1.v\n%Error: Exiting due to 3 error(s)\n'
module HW3(clk, S0, S1, SP, AR, D, BUF_OUT, OUT, FB);
input clk, S0, S1, SP, AR, D, BUF_OUT;
output OUT, FB;
reg Q = 0;

always @(posedge AR) Q <= 0;

always @(posedge clk) begin
    if (SP && !AR) Q <= 1;
    else if (!AR) Q <= D;
end

assign OUT = (S1) ? (S0 ? !D : D) : (S0 ? !Q : Q);
assign FB = (S1) ? BUF_OUT : !Q;

endmodule
module HW3(clk, S0, S1, SP, AR, D, BUF_OUT, OUT, FB);

input clk, S0, S1, SP, AR, D, BUF_OUT;
output OUT, FB;
reg Q = 0;

always @(posedge AR) Q <= 0;

always @(posedge clk) begin
    if (SP && !AR) Q <= 1;
    else if (!AR) Q <= D;
end

assign OUT = (S1) ? (S0 ? !D : D) : (S0 ? !Q : Q);
assign FB = (S1) ? BUF_OUT : !Q;

endmodule