data/full_repos/permissive/523038000/lab1/1.FullAdder.v
data/verilator_xmls/b8fe29d8-84ab-47ca-a37e-95d21724c772.xml
module fulladder (
	 input a,
	 input b,
	 input cin,
	 output s,
	 output cout );
	 

	 wire w1, w2, w3;
	 

	 and( w1, a, b );
	 and( w2, a, cin );
	 and( w3, b, cin );
	 or( cout, w1, w2, w3 );
	 

	 xor( s, a, b, cin );

endmodule
module fulladder (
	 input a,
	 input b,
	 input cin,
	 output s,
	 output cout );

	 

	 wire w1, w2, w3;
	 

	 and( w1, a, b );
	 and( w2, a, cin );
	 and( w3, b, cin );
	 or( cout, w1, w2, w3 );
	 

	 xor( s, a, b, cin );

endmodule