data/full_repos/permissive/495525032/VIZ/simple.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/495525032/VIZ/simple.v:9: Unsupported: Ignoring delay on this delayed statement.\n  forever #5 clk = !clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/495525032/VIZ/simple.v:13: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("simple.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/495525032/VIZ/simple.v:14: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0,simple);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/495525032/VIZ/simple.v:17: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: Exiting due to 3 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module simple;

 integer i;
 reg [31:0] heat;
 reg clk;

 initial begin
	 clk = 0;
	 forever #5 clk = !clk;
 end

 initial begin
	 $dumpfile("simple.vcd");
	 $dumpvars(0,simple);
	 heat = 0;
	 for(i=0;i<=100;i++) begin
		 @(posedge clk);
		 heat = heat + 5;
	 end
	 $finish;
 end
endmodule
module simple;


 integer i;
 reg [31:0] heat;
 reg clk;

 initial begin
	 clk = 0;
	 forever #5 clk = !clk;
 end

 initial begin
	 $dumpfile("simple.vcd");
	 $dumpvars(0,simple);
	 heat = 0;
	 for(i=0;i<=100;i++) begin
		 @(posedge clk);
		 heat = heat + 5;
	 end
	 $finish;
 end
endmodule