data/full_repos/permissive/512077043/rgb_fifo/w-ptr-full.v
1: b'%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_fifo/w-ptr-full.v:45: Operator AND expects 5 bits on the LHS, but LHS\'s VARREF \'w_inc\' generates 1 bits.\n                                                                             : ... In instance w_ptr_full\n    assign w_bin_next = w_bin + (w_inc & ~w_full);\n                                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_fifo/w-ptr-full.v:45: Operator NOT expects 5 bits on the LHS, but LHS\'s VARREF \'w_full\' generates 1 bits.\n                                                                             : ... In instance w_ptr_full\n    assign w_bin_next = w_bin + (w_inc & ~w_full);\n                                         ^\n%Error: Exiting due to 2 warning(s)\n'
module w_ptr_full #(


    parameter   ADDR_SIZE = 4
) (
    

    input       [ADDR_SIZE:0]   w_syn_r_gray,
    input                       w_inc,
    input                       w_clk,
    input                       w_rst,
    

    output      [ADDR_SIZE-1:0] w_addr,
    output  reg [ADDR_SIZE:0]   w_gray,
    output  reg                 w_full
);


    wire    [ADDR_SIZE:0]   w_gray_next;
    wire    [ADDR_SIZE:0]   w_bin_next;
    wire                    w_full_val;
    

    reg     [ADDR_SIZE:0]   w_bin;
    

    assign w_addr = w_bin[ADDR_SIZE-1:0];
    

    assign w_bin_next = w_bin + (w_inc & ~w_full);
    

    assign w_gray_next = (w_bin_next >> 1) ^ w_bin_next;
    






    assign w_full_val = ((w_gray_next[ADDR_SIZE] != w_syn_r_gray[ADDR_SIZE]) &&
                   (w_gray_next[ADDR_SIZE-1] != w_syn_r_gray[ADDR_SIZE-1]) &&
                   (w_gray_next[ADDR_SIZE-2:0] == w_syn_r_gray[ADDR_SIZE-2:0]));
    

    always @ (posedge w_clk or posedge w_rst) begin
        if (w_rst == 1'b1) begin
            w_bin <= 0;
            w_gray <= 0;
        end else begin
            w_bin <= w_bin_next;
            w_gray <= w_gray_next;
        end
    end
    

    always @ (posedge w_clk or posedge w_rst) begin
        if (w_rst == 1'b1) begin
            w_full <= 1'b0;
        end else begin
            w_full <= w_full_val;
        end
    end
    
endmodule
module w_ptr_full #(


    parameter   ADDR_SIZE = 4
) (
    

    input       [ADDR_SIZE:0]   w_syn_r_gray,
    input                       w_inc,
    input                       w_clk,
    input                       w_rst,
    

    output      [ADDR_SIZE-1:0] w_addr,
    output  reg [ADDR_SIZE:0]   w_gray,
    output  reg                 w_full
);



    wire    [ADDR_SIZE:0]   w_gray_next;
    wire    [ADDR_SIZE:0]   w_bin_next;
    wire                    w_full_val;
    

    reg     [ADDR_SIZE:0]   w_bin;
    

    assign w_addr = w_bin[ADDR_SIZE-1:0];
    

    assign w_bin_next = w_bin + (w_inc & ~w_full);
    

    assign w_gray_next = (w_bin_next >> 1) ^ w_bin_next;
    






    assign w_full_val = ((w_gray_next[ADDR_SIZE] != w_syn_r_gray[ADDR_SIZE]) &&
                   (w_gray_next[ADDR_SIZE-1] != w_syn_r_gray[ADDR_SIZE-1]) &&
                   (w_gray_next[ADDR_SIZE-2:0] == w_syn_r_gray[ADDR_SIZE-2:0]));
    

    always @ (posedge w_clk or posedge w_rst) begin
        if (w_rst == 1'b1) begin
            w_bin <= 0;
            w_gray <= 0;
        end else begin
            w_bin <= w_bin_next;
            w_gray <= w_gray_next;
        end
    end
    

    always @ (posedge w_clk or posedge w_rst) begin
        if (w_rst == 1'b1) begin
            w_full <= 1'b0;
        end else begin
            w_full <= w_full_val;
        end
    end
    
endmodule