data/full_repos/permissive/481952562/de10-nano-quartus-project/counter.v
data/verilator_xmls/7eda94c4-9f44-48d2-b7f7-d2a14a29625b.xml
module Counter
(
	clk, 
	reset, 
	count
);
parameter width = 32;
output reg [width-1:0] count = 0;
input clk;
input reset;

always @ (posedge clk) begin
	if(reset) begin
		count = 0;
	end
	else begin
		count = count + 1;
	end
end

endmodule
module Counter
(
	clk, 
	reset, 
	count
);

parameter width = 32;
output reg [width-1:0] count = 0;
input clk;
input reset;

always @ (posedge clk) begin
	if(reset) begin
		count = 0;
	end
	else begin
		count = count + 1;
	end
end

endmodule