data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_10ge_attachment_v1_0_0/hdl/tx_queue.v
1: b'%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_10ge_attachment_v1_0_0/hdl/tx_queue.v:109: Cannot find file containing module: \'FIFO36E1\'\n      FIFO36E1 #(        \n      ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_10ge_attachment_v1_0_0/hdl,data/full_repos/permissive/498471995/FIFO36E1\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_10ge_attachment_v1_0_0/hdl,data/full_repos/permissive/498471995/FIFO36E1.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_10ge_attachment_v1_0_0/hdl,data/full_repos/permissive/498471995/FIFO36E1.sv\n             FIFO36E1\n             FIFO36E1.v\n             FIFO36E1.sv\n             obj_dir/FIFO36E1\n             obj_dir/FIFO36E1.v\n             obj_dir/FIFO36E1.sv\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_10ge_attachment_v1_0_0/hdl/tx_queue.v:153: Cannot find file containing module: \'fifo_generator_1_9\'\n fifo_generator_1_9 tx_info_fifo (\n ^~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_10ge_attachment_v1_0_0/hdl/tx_queue.v:271: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'SEND_PKT\' generates 2 bits.\n                                                                                                                                                      : ... In instance tx_queue\n                      state_next      = SEND_PKT;                     \n                                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_10ge_attachment_v1_0_0/hdl/tx_queue.v:290: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 2 bits.\n                                                                                                                                                      : ... In instance tx_queue\n                             state_next = IDLE;\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_10ge_attachment_v1_0_0/hdl/tx_queue.v:294: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'SEND_PKT\' generates 2 bits.\n                                                                                                                                                      : ... In instance tx_queue\n                             state_next = SEND_PKT;\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_10ge_attachment_v1_0_0/hdl/tx_queue.v:302: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 2 bits.\n                                                                                                                                                      : ... In instance tx_queue\n                  state_next = IDLE;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_10ge_attachment_v1_0_0/hdl/tx_queue.v:264: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'IDLE\' generates 2 bits.\n                                                                                                                                                      : ... In instance tx_queue\n          case(state)\n          ^~~~\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_10ge_attachment_v1_0_0/hdl/tx_queue.v:264: Operator CASE expects 3 bits on the Case Item, but Case Item\'s VARREF \'SEND_PKT\' generates 2 bits.\n                                                                                                                                                      : ... In instance tx_queue\n          case(state)\n          ^~~~\n%Warning-WIDTH: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_10ge_attachment_v1_0_0/hdl/tx_queue.v:308: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'IDLE\' generates 2 bits.\n                                                                                                                                                      : ... In instance tx_queue\n          if(reset) state <= IDLE;\n                          ^~\n%Error: Exiting due to 2 error(s), 7 warning(s)\n'
module tx_queue
 #(
    parameter AXI_DATA_WIDTH             = 64,
    parameter C_S_AXIS_TUSER_WIDTH       = 128
 
 )
 (

    input                               clk,
    input                               reset,
      
    input [C_S_AXIS_TUSER_WIDTH-1:0]    i_tuser,
    input [AXI_DATA_WIDTH-1:0]          i_tdata,
    input [(AXI_DATA_WIDTH/8)-1:0]      i_tkeep,
    input                               i_tvalid,
    input                               i_tlast,
    output                              i_tready,
    

    output                              tx_dequeued_pkt,
    output reg                          be,  
    output reg                          tx_pkts_enqueued_signal,
    output reg [15:0]                   tx_bytes_enqueued,
       

    input                               clk156,
   input                                areset_clk156,
    

    output [AXI_DATA_WIDTH-1:0]         o_tdata,
    output reg [(AXI_DATA_WIDTH/8)-1:0] o_tkeep,
    output reg                          o_tvalid,
    output reg                          o_tlast,
    output reg                          o_tuser,
    input                               o_tready   
 );
 
    localparam IDLE         = 2'd0;
    localparam SEND_PKT     = 2'd1;
 
    localparam METADATA     = 1'b0;
    localparam EOP          = 1'b1;
    
    wire [3:0]                          tkeep_encoded_o;
    reg  [7:0]                          tkeep_decoded_o;
    reg  [3:0]                          tkeep_encoded_i;
    wire                                tlast_axi_i;
    wire                                tlast_axi_o;
 
    wire                                fifo_almost_full, info_fifo_full;
    wire                                fifo_empty, info_fifo_empty;
    reg                                 fifo_rd_en, info_fifo_rd_en;
    reg                                 info_fifo_wr_en;
    wire                                fifo_wr_en;       
     
    reg                                 tx_dequeued_pkt_next;   

    reg  [2:0]                          state, state_next;
    reg                                 state1, state1_next;
   
    wire [2:0]                          zero_padding;



    assign fifo_wr_en  = (reset) ? 1'b0 : (i_tvalid & i_tready) ? 1'b1 : 1'b0; 
    assign i_tready    = ~fifo_almost_full;
    assign tlast_axi_i = i_tlast;

      		 



      FIFO36E1 #(        
        .ALMOST_FULL_OFFSET         (9'h100),
        .ALMOST_EMPTY_OFFSET        (9'hA),
        .DO_REG                     (1),
        .EN_ECC_READ                ("FALSE"),
        .EN_ECC_WRITE               ("FALSE"),
        .EN_SYN                     ("FALSE"),
        .FIRST_WORD_FALL_THROUGH    ("TRUE"),
        .DATA_WIDTH                 (72),       
        .FIFO_MODE                  ("FIFO36_72"),
        .INIT                       (72'h000000000000000000),
        .SIM_DEVICE                 ("7SERIES"), 
        .SRVAL                      (72'h000000000000000000)
      ) tx_fifo (
        .ALMOSTEMPTY                (),
        .ALMOSTFULL                 (fifo_almost_full),
        .EMPTY                      (fifo_empty),
        .FULL                       (),
               
        .DI                         (i_tdata),
        .DIP                        ({3'b0, tlast_axi_i , tkeep_encoded_i}),
        .WRCLK                      (clk),
        .WREN                       (fifo_wr_en),
        .WRCOUNT                    (),
        .WRERR                      (),    
                   
        .DO                         (o_tdata),
        .DOP                        ({zero_padding, tlast_axi_o, tkeep_encoded_o}),
        .RDCLK                      (clk156),
        .RDEN                       (fifo_rd_en),
        .RDCOUNT                    (),
        .RDERR                      (),
           
        .SBITERR                    (),
        .DBITERR                    (),
        .ECCPARITY                  (),
        .INJECTDBITERR              (),
        .INJECTSBITERR              (),    
      
        .RST                        (reset),
        .RSTREG                     (), 
        .REGCE                      ()     
      );
  	
	fifo_generator_1_9 tx_info_fifo (
		.din 			(1'b0							),	
		.wr_en			(info_fifo_wr_en					),
		.wr_clk			(clk							),
		
		.dout			(							),
		.rd_en			(info_fifo_rd_en					),
		.rd_clk			(clk156							),
		
		.full 			(info_fifo_full						),
		.empty 			(info_fifo_empty					),
 		.rst			(reset							)
	);	
	 



      always @(*) begin

          case (i_tkeep)
              8'h1:     tkeep_encoded_i = 4'h0;
              8'h3:     tkeep_encoded_i = 4'h1;
              8'h7:     tkeep_encoded_i = 4'h2;
              8'hF:     tkeep_encoded_i = 4'h3;
              8'h1F:    tkeep_encoded_i = 4'h4;
              8'h3F:    tkeep_encoded_i = 4'h5;
              8'h7F:    tkeep_encoded_i = 4'h6;
              8'hFF:    tkeep_encoded_i = 4'h7;
              default:  tkeep_encoded_i = 4'h8;
          endcase
      

          case (tkeep_encoded_o)
              4'h0:     tkeep_decoded_o = 8'h1;
              4'h1:     tkeep_decoded_o = 8'h3;
              4'h2:     tkeep_decoded_o = 8'h7;
              4'h3:     tkeep_decoded_o = 8'hF;
              4'h4:     tkeep_decoded_o = 8'h1F;
              4'h5:     tkeep_decoded_o = 8'h3F;
              4'h6:     tkeep_decoded_o = 8'h7F;
              4'h7:     tkeep_decoded_o = 8'hFF;
              default:  tkeep_decoded_o = 8'h0;
          endcase         
      end
 
      
          


      always @(*) begin 
          state1_next             = state1;
              
          tx_pkts_enqueued_signal = 0;
          tx_bytes_enqueued       = 0;
       
          case(state1)
              METADATA: begin
                  if(i_tvalid & i_tready) begin
                      tx_pkts_enqueued_signal = 1;
                      tx_bytes_enqueued       = i_tuser[15:0];
                      state1_next             = EOP;
                  end
              end
       
              EOP: begin
                  if(i_tvalid & i_tlast & i_tready) begin
                      state1_next = METADATA;
                  end
              end
                      
              default: begin 
                      state1_next = METADATA;
              end
           endcase     
      end
       

      always @(posedge clk) begin
           if (reset) state1 <= METADATA;
           else       state1 <= state1_next;
      end
           

      always @(posedge clk) begin
          info_fifo_wr_en <= i_tlast & i_tvalid & i_tready;
      end
 



      

      assign tx_dequeued_pkt = tx_dequeued_pkt_next; 

      always @(*) begin
          state_next            = state;
          

          o_tkeep               = tkeep_decoded_o;
          o_tuser               = 1'b0;
          o_tvalid              = 1'b0;
          o_tlast               = 1'b0;
          

          fifo_rd_en            = 1'b0;
          info_fifo_rd_en       = 1'b0;
          

          tx_dequeued_pkt_next  = 'b0;
          be                    = 'b0;
 
          case(state)
              IDLE: begin
                  o_tkeep = 8'b0;
                  if( ~info_fifo_empty) begin

                      info_fifo_rd_en = 1'b1;
                      be              = 'b0;                      
                      state_next      = SEND_PKT;                     
                  end
              end

              SEND_PKT: begin


                o_tvalid = 1'b1;
                if (o_tready & ~fifo_empty) begin
                    fifo_rd_en            = 1'b1;
                  
                    be                    = 1'b1;
                    tx_dequeued_pkt_next  = 1'b1; 

                    if (tlast_axi_o) begin
                         o_tlast    = 1'b1;
                         be         = 1'b1;    

                         if (info_fifo_empty) begin
                             state_next = IDLE;
                             info_fifo_rd_en = 'd0;
                         end 
                         else begin
                             state_next = SEND_PKT;
                             info_fifo_rd_en = 'd1;
                         end
                    end               
                end
              end

              default : begin
                  state_next = IDLE;
              end
          endcase
      end
 
      always @(posedge clk156) begin
          if(reset) state <= IDLE;
          else      state <= state_next;         
      end 
 endmodule
module tx_queue
 #(
    parameter AXI_DATA_WIDTH             = 64,
    parameter C_S_AXIS_TUSER_WIDTH       = 128
 
 )
 (

    input                               clk,
    input                               reset,
      
    input [C_S_AXIS_TUSER_WIDTH-1:0]    i_tuser,
    input [AXI_DATA_WIDTH-1:0]          i_tdata,
    input [(AXI_DATA_WIDTH/8)-1:0]      i_tkeep,
    input                               i_tvalid,
    input                               i_tlast,
    output                              i_tready,
    

    output                              tx_dequeued_pkt,
    output reg                          be,  
    output reg                          tx_pkts_enqueued_signal,
    output reg [15:0]                   tx_bytes_enqueued,
       

    input                               clk156,
   input                                areset_clk156,
    

    output [AXI_DATA_WIDTH-1:0]         o_tdata,
    output reg [(AXI_DATA_WIDTH/8)-1:0] o_tkeep,
    output reg                          o_tvalid,
    output reg                          o_tlast,
    output reg                          o_tuser,
    input                               o_tready   
 );

 
    localparam IDLE         = 2'd0;
    localparam SEND_PKT     = 2'd1;
 
    localparam METADATA     = 1'b0;
    localparam EOP          = 1'b1;
    
    wire [3:0]                          tkeep_encoded_o;
    reg  [7:0]                          tkeep_decoded_o;
    reg  [3:0]                          tkeep_encoded_i;
    wire                                tlast_axi_i;
    wire                                tlast_axi_o;
 
    wire                                fifo_almost_full, info_fifo_full;
    wire                                fifo_empty, info_fifo_empty;
    reg                                 fifo_rd_en, info_fifo_rd_en;
    reg                                 info_fifo_wr_en;
    wire                                fifo_wr_en;       
     
    reg                                 tx_dequeued_pkt_next;   

    reg  [2:0]                          state, state_next;
    reg                                 state1, state1_next;
   
    wire [2:0]                          zero_padding;



    assign fifo_wr_en  = (reset) ? 1'b0 : (i_tvalid & i_tready) ? 1'b1 : 1'b0; 
    assign i_tready    = ~fifo_almost_full;
    assign tlast_axi_i = i_tlast;

      		 



      FIFO36E1 #(        
        .ALMOST_FULL_OFFSET         (9'h100),
        .ALMOST_EMPTY_OFFSET        (9'hA),
        .DO_REG                     (1),
        .EN_ECC_READ                ("FALSE"),
        .EN_ECC_WRITE               ("FALSE"),
        .EN_SYN                     ("FALSE"),
        .FIRST_WORD_FALL_THROUGH    ("TRUE"),
        .DATA_WIDTH                 (72),       
        .FIFO_MODE                  ("FIFO36_72"),
        .INIT                       (72'h000000000000000000),
        .SIM_DEVICE                 ("7SERIES"), 
        .SRVAL                      (72'h000000000000000000)
      ) tx_fifo (
        .ALMOSTEMPTY                (),
        .ALMOSTFULL                 (fifo_almost_full),
        .EMPTY                      (fifo_empty),
        .FULL                       (),
               
        .DI                         (i_tdata),
        .DIP                        ({3'b0, tlast_axi_i , tkeep_encoded_i}),
        .WRCLK                      (clk),
        .WREN                       (fifo_wr_en),
        .WRCOUNT                    (),
        .WRERR                      (),    
                   
        .DO                         (o_tdata),
        .DOP                        ({zero_padding, tlast_axi_o, tkeep_encoded_o}),
        .RDCLK                      (clk156),
        .RDEN                       (fifo_rd_en),
        .RDCOUNT                    (),
        .RDERR                      (),
           
        .SBITERR                    (),
        .DBITERR                    (),
        .ECCPARITY                  (),
        .INJECTDBITERR              (),
        .INJECTSBITERR              (),    
      
        .RST                        (reset),
        .RSTREG                     (), 
        .REGCE                      ()     
      );
  	
	fifo_generator_1_9 tx_info_fifo (
		.din 			(1'b0							),	
		.wr_en			(info_fifo_wr_en					),
		.wr_clk			(clk							),
		
		.dout			(							),
		.rd_en			(info_fifo_rd_en					),
		.rd_clk			(clk156							),
		
		.full 			(info_fifo_full						),
		.empty 			(info_fifo_empty					),
 		.rst			(reset							)
	);	
	 



      always @(*) begin

          case (i_tkeep)
              8'h1:     tkeep_encoded_i = 4'h0;
              8'h3:     tkeep_encoded_i = 4'h1;
              8'h7:     tkeep_encoded_i = 4'h2;
              8'hF:     tkeep_encoded_i = 4'h3;
              8'h1F:    tkeep_encoded_i = 4'h4;
              8'h3F:    tkeep_encoded_i = 4'h5;
              8'h7F:    tkeep_encoded_i = 4'h6;
              8'hFF:    tkeep_encoded_i = 4'h7;
              default:  tkeep_encoded_i = 4'h8;
          endcase
      

          case (tkeep_encoded_o)
              4'h0:     tkeep_decoded_o = 8'h1;
              4'h1:     tkeep_decoded_o = 8'h3;
              4'h2:     tkeep_decoded_o = 8'h7;
              4'h3:     tkeep_decoded_o = 8'hF;
              4'h4:     tkeep_decoded_o = 8'h1F;
              4'h5:     tkeep_decoded_o = 8'h3F;
              4'h6:     tkeep_decoded_o = 8'h7F;
              4'h7:     tkeep_decoded_o = 8'hFF;
              default:  tkeep_decoded_o = 8'h0;
          endcase         
      end
 
      
          


      always @(*) begin 
          state1_next             = state1;
              
          tx_pkts_enqueued_signal = 0;
          tx_bytes_enqueued       = 0;
       
          case(state1)
              METADATA: begin
                  if(i_tvalid & i_tready) begin
                      tx_pkts_enqueued_signal = 1;
                      tx_bytes_enqueued       = i_tuser[15:0];
                      state1_next             = EOP;
                  end
              end
       
              EOP: begin
                  if(i_tvalid & i_tlast & i_tready) begin
                      state1_next = METADATA;
                  end
              end
                      
              default: begin 
                      state1_next = METADATA;
              end
           endcase     
      end
       

      always @(posedge clk) begin
           if (reset) state1 <= METADATA;
           else       state1 <= state1_next;
      end
           

      always @(posedge clk) begin
          info_fifo_wr_en <= i_tlast & i_tvalid & i_tready;
      end
 



      

      assign tx_dequeued_pkt = tx_dequeued_pkt_next; 

      always @(*) begin
          state_next            = state;
          

          o_tkeep               = tkeep_decoded_o;
          o_tuser               = 1'b0;
          o_tvalid              = 1'b0;
          o_tlast               = 1'b0;
          

          fifo_rd_en            = 1'b0;
          info_fifo_rd_en       = 1'b0;
          

          tx_dequeued_pkt_next  = 'b0;
          be                    = 'b0;
 
          case(state)
              IDLE: begin
                  o_tkeep = 8'b0;
                  if( ~info_fifo_empty) begin

                      info_fifo_rd_en = 1'b1;
                      be              = 'b0;                      
                      state_next      = SEND_PKT;                     
                  end
              end

              SEND_PKT: begin


                o_tvalid = 1'b1;
                if (o_tready & ~fifo_empty) begin
                    fifo_rd_en            = 1'b1;
                  
                    be                    = 1'b1;
                    tx_dequeued_pkt_next  = 1'b1; 

                    if (tlast_axi_o) begin
                         o_tlast    = 1'b1;
                         be         = 1'b1;    

                         if (info_fifo_empty) begin
                             state_next = IDLE;
                             info_fifo_rd_en = 'd0;
                         end 
                         else begin
                             state_next = SEND_PKT;
                             info_fifo_rd_en = 'd1;
                         end
                    end               
                end
              end

              default : begin
                  state_next = IDLE;
              end
          endcase
      end
 
      always @(posedge clk156) begin
          if(reset) state <= IDLE;
          else      state <= state_next;         
      end 
 endmodule