data/full_repos/permissive/482132588/verif/tests/test_pd.v
1: b'%Error: data/full_repos/permissive/482132588/verif/tests/test_pd.v:2: Cannot find include file: signals.h\n`include "signals.h" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/482132588/verif/tests,data/full_repos/permissive/482132588/signals.h\n             data/full_repos/permissive/482132588/verif/tests,data/full_repos/permissive/482132588/signals.h.v\n             data/full_repos/permissive/482132588/verif/tests,data/full_repos/permissive/482132588/signals.h.sv\n             signals.h\n             signals.h.v\n             signals.h.sv\n             obj_dir/signals.h\n             obj_dir/signals.h.v\n             obj_dir/signals.h.sv\n%Error: data/full_repos/permissive/482132588/verif/tests/test_pd.v:21: Cannot find include file: tracegen.v\n  `include "tracegen.v" \n           ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module top;
  wire clock, reset;
  clockgen clkg(
    .clk(clock),
    .rst(reset)
  );
  design_wrapper dut(
    .clock(clock),
    .reset(reset)
  );
  `ifdef VCD
  initial begin
    $dumpfile(`VCD_FILE);
    $dumpvars;
  end
  `endif

  `include "tracegen.v"
endmodule
module top;

  wire clock, reset;
  clockgen clkg(
    .clk(clock),
    .rst(reset)
  );
  design_wrapper dut(
    .clock(clock),
    .reset(reset)
  );
  `ifdef VCD
  initial begin
    $dumpfile(`VCD_FILE);
    $dumpvars;
  end
  `endif

  `include "tracegen.v"
endmodule