data/full_repos/permissive/436123010/design_sources/InsMem.v
data/verilator_xmls/1c92f496-abaf-441f-9598-a7150b220560.xml
module InsMem(input wire[31:0] pc, output wire[31:0] ins);
    reg[31:0] mem[255:0];    
    initial begin
        $readmemh("Instructions.txt",mem);
    end
    assign ins = mem[pc>>2]; 
endmodule
module InsMem(input wire[31:0] pc, output wire[31:0] ins);

    reg[31:0] mem[255:0];    
    initial begin
        $readmemh("Instructions.txt",mem);
    end
    assign ins = mem[pc>>2]; 
endmodule