data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_dregister.v
1: b'%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_dregister.v:36: Cannot find include file: pacoblaze_inc.v\n`include "pacoblaze_inc.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze,data/full_repos/permissive/487568919/pacoblaze_inc.v\n             data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze,data/full_repos/permissive/487568919/pacoblaze_inc.v.v\n             data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze,data/full_repos/permissive/487568919/pacoblaze_inc.v.sv\n             pacoblaze_inc.v\n             pacoblaze_inc.v.v\n             pacoblaze_inc.v.sv\n             obj_dir/pacoblaze_inc.v\n             obj_dir/pacoblaze_inc.v.v\n             obj_dir/pacoblaze_inc.v.sv\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_dregister.v:39: Define or directive not defined: \'`PACOBLAZE_REGISTER\'\n                                                                                                           : ... Suggested alternative: \'`PACOBLAZE_DREGISTER_V_\'\nmodule `PACOBLAZE_REGISTER(\n       ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_dregister.v:40: syntax error, unexpected \'(\', expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\n x_address, x_write_enable, x_data_in, x_data_out,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_dregister.v:47: Define or directive not defined: \'`register_depth\'\ninput [`register_depth-1:0] x_address, y_address;  \n       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_dregister.v:48: Define or directive not defined: \'`register_width\'\ninput [`register_width-1:0] x_data_in, w_data_in;  \n       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_dregister.v:49: Define or directive not defined: \'`register_width\'\noutput [`register_width-1:0] x_data_out, y_data_out;  \n        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_dregister.v:50: Define or directive not defined: \'`register_width\'\noutput [`register_width-1:0] u_data_out, v_data_out;  \n        ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_dregister.v:52: Define or directive not defined: \'`register_width\'\nreg [`register_width-1:0]\n     ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_dregister.v:53: Define or directive not defined: \'`register_size\'\n dpre[0:(`register_size>>1)-1],  \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_dregister.v:53: syntax error, unexpected >>, expecting TYPE-IDENTIFIER\n dpre[0:(`register_size>>1)-1],  \n                       ^~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_dregister.v:54: Define or directive not defined: \'`register_size\'\n dpro[0:(`register_size>>1)-1];  \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_dregister.v:56: Define or directive not defined: \'`register_depth\'\nwire [`register_depth-2:0]\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_dregister.v:57: Define or directive not defined: \'`register_depth\'\n x_address_base = x_address[`register_depth-1:1],  \n                            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_dregister.v:58: Define or directive not defined: \'`register_depth\'\n y_address_base = y_address[`register_depth-1:1];  \n                            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_dregister.v:60: Define or directive not defined: \'`register_width\'\nwire [`register_width-1:0]\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_dregister.v:68: syntax error, unexpected assign\nassign u_data_out = dpro[x_address_base];  \n^~~~~~\n%Error: Exiting due to 16 error(s)\n'
module `PACOBLAZE_REGISTER(
	x_address, x_write_enable, x_data_in, x_data_out,
	y_address, y_data_out,
	wx_write_enable, w_data_in, u_data_out, v_data_out,
	reset, clk
);
input clk, reset;
input x_write_enable, wx_write_enable;
input [`register_depth-1:0] x_address, y_address;
input [`register_width-1:0] x_data_in, w_data_in;
output [`register_width-1:0] x_data_out, y_data_out;
output [`register_width-1:0] u_data_out, v_data_out;

reg [`register_width-1:0]
	dpre[0:(`register_size>>1)-1],
	dpro[0:(`register_size>>1)-1];

wire [`register_depth-2:0]
	x_address_base = x_address[`register_depth-1:1],
	y_address_base = y_address[`register_depth-1:1];

wire [`register_width-1:0]
	dpre_in = x_data_in,
	dpro_in = (wx_write_enable) ? w_data_in : x_data_in;

wire
	dpre_we = (wx_write_enable || x_write_enable && !x_address[0]),
	dpro_we = (wx_write_enable || x_write_enable && x_address[0]);

assign u_data_out = dpro[x_address_base];
assign x_data_out =
	(x_address[0]) ? dpro[x_address_base] : dpre[x_address_base];
assign v_data_out = dpro[y_address_base];
assign y_data_out =
	(y_address[0]) ? dpro[y_address_base] : dpre[y_address_base];

always @(posedge clk)
begin
	if (dpre_we) dpre[x_address_base] <= dpre_in;
	if (dpro_we) dpro[x_address_base] <= dpro_in;
end

endmodule
module `PACOBLAZE_REGISTER(
	x_address, x_write_enable, x_data_in, x_data_out,
	y_address, y_data_out,
	wx_write_enable, w_data_in, u_data_out, v_data_out,
	reset, clk
);

input clk, reset;
input x_write_enable, wx_write_enable;
input [`register_depth-1:0] x_address, y_address;
input [`register_width-1:0] x_data_in, w_data_in;
output [`register_width-1:0] x_data_out, y_data_out;
output [`register_width-1:0] u_data_out, v_data_out;

reg [`register_width-1:0]
	dpre[0:(`register_size>>1)-1],
	dpro[0:(`register_size>>1)-1];

wire [`register_depth-2:0]
	x_address_base = x_address[`register_depth-1:1],
	y_address_base = y_address[`register_depth-1:1];

wire [`register_width-1:0]
	dpre_in = x_data_in,
	dpro_in = (wx_write_enable) ? w_data_in : x_data_in;

wire
	dpre_we = (wx_write_enable || x_write_enable && !x_address[0]),
	dpro_we = (wx_write_enable || x_write_enable && x_address[0]);

assign u_data_out = dpro[x_address_base];
assign x_data_out =
	(x_address[0]) ? dpro[x_address_base] : dpre[x_address_base];
assign v_data_out = dpro[y_address_base];
assign y_data_out =
	(y_address[0]) ? dpro[y_address_base] : dpre[y_address_base];

always @(posedge clk)
begin
	if (dpre_we) dpre[x_address_base] <= dpre_in;
	if (dpro_we) dpro[x_address_base] <= dpro_in;
end

endmodule