data/full_repos/permissive/474275312/Day 1/Counter/counter_clk_div_vio.v
1: b'%Error: Cannot find file containing module: 1/Counter,data/full_repos/permissive/474275312\n        ... Looked in:\n             data/full_repos/permissive/474275312/Day/1/Counter,data/full_repos/permissive/474275312\n             data/full_repos/permissive/474275312/Day/1/Counter,data/full_repos/permissive/474275312.v\n             data/full_repos/permissive/474275312/Day/1/Counter,data/full_repos/permissive/474275312.sv\n             1/Counter,data/full_repos/permissive/474275312\n             1/Counter,data/full_repos/permissive/474275312.v\n             1/Counter,data/full_repos/permissive/474275312.sv\n             obj_dir/1/Counter,data/full_repos/permissive/474275312\n             obj_dir/1/Counter,data/full_repos/permissive/474275312.v\n             obj_dir/1/Counter,data/full_repos/permissive/474275312.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/474275312/Day\n%Error: Cannot find file containing module: 1/Counter/counter_clk_div_vio.v\n%Error: Exiting due to 3 error(s)\n'
module counter_clk_div(clk);
input clk;
wire rst;
reg div_clk;
reg [25:0] delay_count;
reg [3:0] counter_out;






vio_0 vioname (
  .clk(clk),
  .probe_in0(div_clk),
  .probe_in1(counter_out),
  .probe_out0(rst)
);






always @(posedge clk or posedge rst)
begin

if(rst)
begin
delay_count<=26'd0;
counter_out<=4'b0000;
div_clk <= 1'b0;




end
else





if(delay_count==26'd32112212)
begin
delay_count<=26'd0;
div_clk <= ~div_clk;
end
else
begin
delay_count<=delay_count+1;
end
end



always @(posedge div_clk)
begin

if(rst)
begin
counter_out<=4'b0000;
end
else
begin
counter_out<= counter_out+1;
end
end

endmodule
module counter_clk_div(clk);

input clk;
wire rst;
reg div_clk;
reg [25:0] delay_count;
reg [3:0] counter_out;






vio_0 vioname (
  .clk(clk),
  .probe_in0(div_clk),
  .probe_in1(counter_out),
  .probe_out0(rst)
);






always @(posedge clk or posedge rst)
begin

if(rst)
begin
delay_count<=26'd0;
counter_out<=4'b0000;
div_clk <= 1'b0;




end
else





if(delay_count==26'd32112212)
begin
delay_count<=26'd0;
div_clk <= ~div_clk;
end
else
begin
delay_count<=delay_count+1;
end
end



always @(posedge div_clk)
begin

if(rst)
begin
counter_out<=4'b0000;
end
else
begin
counter_out<= counter_out+1;
end
end

endmodule