data/full_repos/permissive/452721391/VGA/hvsync_generator.v
data/verilator_xmls/d2458c8b-b9dc-4e9c-b0ed-2a7df2b34fa1.xml
module hvsync_generator(
    input clk50,
    output vga_h_sync,
    output vga_v_sync,
    output reg inDisplayArea,
    output reg [9:0] CounterX,
    output reg [9:0] CounterY,
	 output reg [19:0] loc
  );


reg pixel_clk;
localparam div_value = 0;
integer counter_value = 0;
always@ (posedge clk50)
begin
	if (counter_value == div_value)
	  counter_value <= 0;
	else
	  counter_value <= counter_value+1;
	if(counter_value == div_value)
	  pixel_clk <= ~pixel_clk;
end

reg vga_HS, vga_VS;

wire CounterXmaxed = (CounterX == 800);
wire CounterYmaxed = (CounterY == 525);

always @(posedge pixel_clk)
begin
	if (CounterXmaxed)
		CounterX <= 0;
	else
		CounterX <= CounterX + 1;
	if (CounterXmaxed)
	begin
		if(CounterYmaxed)
			CounterY <= 0;
		else
			CounterY <= CounterY + 1;
	end
	
	vga_HS <= (CounterX > (640 + 16) && (CounterX < (640 + 16 + 96)));
	vga_VS <= (CounterY > (480 + 10) && (CounterY < (480 + 10 + 2)));
	
	inDisplayArea <= (CounterX < 640) && (CounterY < 480);
end

assign vga_h_sync = ~vga_HS;
assign vga_v_sync = ~vga_VS;

always @(posedge clk50)
begin
	if(CounterYmaxed)
	begin
		loc <= 20'b00000000000000000000;
	end
	else
	begin
		loc <= loc + 1;
	end
end
endmodule
module hvsync_generator(
    input clk50,
    output vga_h_sync,
    output vga_v_sync,
    output reg inDisplayArea,
    output reg [9:0] CounterX,
    output reg [9:0] CounterY,
	 output reg [19:0] loc
  );



reg pixel_clk;
localparam div_value = 0;
integer counter_value = 0;
always@ (posedge clk50)
begin
	if (counter_value == div_value)
	  counter_value <= 0;
	else
	  counter_value <= counter_value+1;
	if(counter_value == div_value)
	  pixel_clk <= ~pixel_clk;
end

reg vga_HS, vga_VS;

wire CounterXmaxed = (CounterX == 800);
wire CounterYmaxed = (CounterY == 525);

always @(posedge pixel_clk)
begin
	if (CounterXmaxed)
		CounterX <= 0;
	else
		CounterX <= CounterX + 1;
	if (CounterXmaxed)
	begin
		if(CounterYmaxed)
			CounterY <= 0;
		else
			CounterY <= CounterY + 1;
	end
	
	vga_HS <= (CounterX > (640 + 16) && (CounterX < (640 + 16 + 96)));
	vga_VS <= (CounterY > (480 + 10) && (CounterY < (480 + 10 + 2)));
	
	inDisplayArea <= (CounterX < 640) && (CounterY < 480);
end

assign vga_h_sync = ~vga_HS;
assign vga_v_sync = ~vga_VS;

always @(posedge clk50)
begin
	if(CounterYmaxed)
	begin
		loc <= 20'b00000000000000000000;
	end
	else
	begin
		loc <= loc + 1;
	end
end
endmodule