data/full_repos/permissive/497870922/rtl/i2c module/i2c_master_top.v
1: b'%Error: Cannot find file containing module: module,data/full_repos/permissive/497870922\n        ... Looked in:\n             data/full_repos/permissive/497870922/rtl/i2c/module,data/full_repos/permissive/497870922\n             data/full_repos/permissive/497870922/rtl/i2c/module,data/full_repos/permissive/497870922.v\n             data/full_repos/permissive/497870922/rtl/i2c/module,data/full_repos/permissive/497870922.sv\n             module,data/full_repos/permissive/497870922\n             module,data/full_repos/permissive/497870922.v\n             module,data/full_repos/permissive/497870922.sv\n             obj_dir/module,data/full_repos/permissive/497870922\n             obj_dir/module,data/full_repos/permissive/497870922.v\n             obj_dir/module,data/full_repos/permissive/497870922.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/497870922/rtl/i2c\n%Error: Cannot find file containing module: module/i2c_master_top.v\n%Error: Exiting due to 3 error(s)\n'
module i2c_master_top (
	input clk_i,
	input arst_i,
	

	input  en_prer_lo_i,
	input  en_prer_hi_i,
	input  en_ctr_i,
	input  en_txr_i,
	input  en_cr_i,


	input  [7:0] reg_i,
	output reg [7:0] rxr_o,
	output reg [7:0] sr_o,
	


	input  scl_pad_i,
	output scl_pad_o,
	output scl_padoen_o,


	input  sda_pad_i,
	output sda_pad_o,
	output sda_padoen_o
	);






	reg  [15:0] prer;
	reg  [ 7:0] ctr;
	reg  [ 7:0] txr;
	wire [ 7:0] rxr;
	reg  [ 7:0] cr;
	wire [ 7:0] sr;


	wire done;


	wire core_en;
	wire ien;


	wire irxack;
	reg  rxack;
	reg  tip;
	reg  irq_flag;
	wire i2c_busy;
	wire i2c_al;
	reg  al;


	always @(posedge clk_i or negedge arst_i) begin
		if (!arst_i) begin
			prer <= 16'hFFFF;
			ctr <= 8'h00;
			txr <= 8'h00;
			cr <= 8'h00;
		end
		else if (done | i2c_al) begin
			prer <= prer;
			ctr <= ctr;
			txr <= txr;
			cr <= 8'h00;			
		end
		else begin
			if (en_prer_lo_i) begin
				prer [7:0] <= reg_i;
				prer [15:8] <= prer [15:8];
				ctr <= ctr;
				txr <= txr;
				cr <= cr;
			end
			else if (en_prer_hi_i) begin
				prer [7:0] <= prer [7:0];
				prer [15:8] <= reg_i;
				ctr <= ctr;
				txr <= txr;
				cr <= cr;
			end
			else if (en_ctr_i) begin
				prer [7:0] <= prer [7:0];
				prer [15:8] <= prer [15:8];
				ctr <= reg_i;
				txr <= txr;
				cr <= cr;
			end
			else if (en_txr_i) begin
				prer [7:0] <= prer [7:0];
				prer [15:8] <= prer [15:8];
				ctr <= ctr;
				txr <= reg_i;
				cr <= cr;
			end
			else if (en_cr_i) begin
				prer [7:0] <= prer [7:0];
				prer [15:8] <= prer [15:8];
				ctr <= ctr;
				txr <= txr;
				cr <= reg_i;
			end
			else begin
				prer <= prer;
				ctr <= ctr;
				txr <= txr;
				cr <= cr;
			end
		end
	end


	always @(clk_i) begin
		sr_o = sr;
		rxr_o = rxr;
	end







	wire sta  = cr[7];
	wire sto  = cr[6];
	wire rd   = cr[5];
	wire wr   = cr[4];
	wire ack  = cr[3];
	wire iack = cr[0];


	assign core_en = ctr[7];
	assign ien = ctr[6];


	i2c_master_byte_ctrl byte_controller (
		.clk      ( clk_i     	 ),
		.rst      ( 1'b0         ),
		.nReset   ( arst_i       ),
		.ena      ( core_en      ),
		.clk_cnt  ( prer         ),
		.start    ( sta          ),
		.stop     ( sto          ),
		.read     ( rd           ),
		.write    ( wr           ),
		.ack_in   ( ack          ),
		.din      ( txr          ),
		.cmd_ack  ( done         ),
		.ack_out  ( irxack       ),
		.dout     ( rxr          ),
		.i2c_busy ( i2c_busy     ),
		.i2c_al   ( i2c_al       ),
		.scl_i    ( scl_pad_i    ),
		.scl_o    ( scl_pad_o    ),
		.scl_oen  ( scl_padoen_o ),
		.sda_i    ( sda_pad_i    ),
		.sda_o    ( sda_pad_o    ),
		.sda_oen  ( sda_padoen_o )
	);


	always @(posedge clk_i or negedge arst_i)
	  	if (!arst_i) begin
	        al       <= 1'b0;
	        rxack    <= 1'b0;
	        tip      <= 1'b0;
	        irq_flag <= 1'b0;
	    end
	    else begin
	        al       <= i2c_al | (al & ~sta);
	        rxack    <= irxack;
	        tip      <= (rd | wr);
	        irq_flag <= (done | i2c_al | irq_flag) & ~iack;
	    end


	assign sr[7]   = rxack;
	assign sr[6]   = i2c_busy;
	assign sr[5]   = al;
	assign sr[4:2] = 3'h0;
	assign sr[1]   = tip;
	assign sr[0]   = irq_flag;

endmodule
module i2c_master_top (
	input clk_i,
	input arst_i,
	

	input  en_prer_lo_i,
	input  en_prer_hi_i,
	input  en_ctr_i,
	input  en_txr_i,
	input  en_cr_i,


	input  [7:0] reg_i,
	output reg [7:0] rxr_o,
	output reg [7:0] sr_o,
	


	input  scl_pad_i,
	output scl_pad_o,
	output scl_padoen_o,


	input  sda_pad_i,
	output sda_pad_o,
	output sda_padoen_o
	);







	reg  [15:0] prer;
	reg  [ 7:0] ctr;
	reg  [ 7:0] txr;
	wire [ 7:0] rxr;
	reg  [ 7:0] cr;
	wire [ 7:0] sr;


	wire done;


	wire core_en;
	wire ien;


	wire irxack;
	reg  rxack;
	reg  tip;
	reg  irq_flag;
	wire i2c_busy;
	wire i2c_al;
	reg  al;


	always @(posedge clk_i or negedge arst_i) begin
		if (!arst_i) begin
			prer <= 16'hFFFF;
			ctr <= 8'h00;
			txr <= 8'h00;
			cr <= 8'h00;
		end
		else if (done | i2c_al) begin
			prer <= prer;
			ctr <= ctr;
			txr <= txr;
			cr <= 8'h00;			
		end
		else begin
			if (en_prer_lo_i) begin
				prer [7:0] <= reg_i;
				prer [15:8] <= prer [15:8];
				ctr <= ctr;
				txr <= txr;
				cr <= cr;
			end
			else if (en_prer_hi_i) begin
				prer [7:0] <= prer [7:0];
				prer [15:8] <= reg_i;
				ctr <= ctr;
				txr <= txr;
				cr <= cr;
			end
			else if (en_ctr_i) begin
				prer [7:0] <= prer [7:0];
				prer [15:8] <= prer [15:8];
				ctr <= reg_i;
				txr <= txr;
				cr <= cr;
			end
			else if (en_txr_i) begin
				prer [7:0] <= prer [7:0];
				prer [15:8] <= prer [15:8];
				ctr <= ctr;
				txr <= reg_i;
				cr <= cr;
			end
			else if (en_cr_i) begin
				prer [7:0] <= prer [7:0];
				prer [15:8] <= prer [15:8];
				ctr <= ctr;
				txr <= txr;
				cr <= reg_i;
			end
			else begin
				prer <= prer;
				ctr <= ctr;
				txr <= txr;
				cr <= cr;
			end
		end
	end


	always @(clk_i) begin
		sr_o = sr;
		rxr_o = rxr;
	end







	wire sta  = cr[7];
	wire sto  = cr[6];
	wire rd   = cr[5];
	wire wr   = cr[4];
	wire ack  = cr[3];
	wire iack = cr[0];


	assign core_en = ctr[7];
	assign ien = ctr[6];


	i2c_master_byte_ctrl byte_controller (
		.clk      ( clk_i     	 ),
		.rst      ( 1'b0         ),
		.nReset   ( arst_i       ),
		.ena      ( core_en      ),
		.clk_cnt  ( prer         ),
		.start    ( sta          ),
		.stop     ( sto          ),
		.read     ( rd           ),
		.write    ( wr           ),
		.ack_in   ( ack          ),
		.din      ( txr          ),
		.cmd_ack  ( done         ),
		.ack_out  ( irxack       ),
		.dout     ( rxr          ),
		.i2c_busy ( i2c_busy     ),
		.i2c_al   ( i2c_al       ),
		.scl_i    ( scl_pad_i    ),
		.scl_o    ( scl_pad_o    ),
		.scl_oen  ( scl_padoen_o ),
		.sda_i    ( sda_pad_i    ),
		.sda_o    ( sda_pad_o    ),
		.sda_oen  ( sda_padoen_o )
	);


	always @(posedge clk_i or negedge arst_i)
	  	if (!arst_i) begin
	        al       <= 1'b0;
	        rxack    <= 1'b0;
	        tip      <= 1'b0;
	        irq_flag <= 1'b0;
	    end
	    else begin
	        al       <= i2c_al | (al & ~sta);
	        rxack    <= irxack;
	        tip      <= (rd | wr);
	        irq_flag <= (done | i2c_al | irq_flag) & ~iack;
	    end


	assign sr[7]   = rxack;
	assign sr[6]   = i2c_busy;
	assign sr[5]   = al;
	assign sr[4:2] = 3'h0;
	assign sr[1]   = tip;
	assign sr[0]   = irq_flag;

endmodule