data/full_repos/permissive/516743196/shift_and_add_binary_multiplier_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/516743196/shift_and_add_binary_multiplier_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n    forever #4 clk = ~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/516743196/shift_and_add_binary_multiplier_tb.v:18: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile ("shift_and_add_binary_multiplier_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/516743196/shift_and_add_binary_multiplier_tb.v:19: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars (0,shift_and_add_binary_multiplier_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/516743196/shift_and_add_binary_multiplier_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #2;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/516743196/shift_and_add_binary_multiplier_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/516743196/shift_and_add_binary_multiplier_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #2;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/516743196/shift_and_add_binary_multiplier_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/516743196/shift_and_add_binary_multiplier_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #2;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/516743196/shift_and_add_binary_multiplier_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module shift_and_add_binary_multiplier_tb;
parameter m=8, n=8;
reg clk, rst;
reg [m-1:0] A;
reg [n-1:0] B;
wire [m+n-1:0] C;

shift_and_add_binary_multiplier uut(clk, rst, A, B, C);

initial 
begin
    clk = 1'b1;
    forever #4 clk = ~clk;
end
initial
begin
    $dumpfile ("shift_and_add_binary_multiplier_tb.vcd");
    $dumpvars (0,shift_and_add_binary_multiplier_tb);
    rst = 1;
    #2;
    rst = 0;
    A = 8'b11111111;
    B = 8'b11111111;
    #20;
    rst = 1;
    #2;
    rst = 0;
    A = 8'b00011111;
    B = 8'b00011111;
    #20;
    rst = 1;
    #2;
    rst = 0;
    A = 8'b00000011;
    B = 8'b00000010;
    #20;
end
endmodule
module shift_and_add_binary_multiplier_tb;

parameter m=8, n=8;
reg clk, rst;
reg [m-1:0] A;
reg [n-1:0] B;
wire [m+n-1:0] C;

shift_and_add_binary_multiplier uut(clk, rst, A, B, C);

initial 
begin
    clk = 1'b1;
    forever #4 clk = ~clk;
end
initial
begin
    $dumpfile ("shift_and_add_binary_multiplier_tb.vcd");
    $dumpvars (0,shift_and_add_binary_multiplier_tb);
    rst = 1;
    #2;
    rst = 0;
    A = 8'b11111111;
    B = 8'b11111111;
    #20;
    rst = 1;
    #2;
    rst = 0;
    A = 8'b00011111;
    B = 8'b00011111;
    #20;
    rst = 1;
    #2;
    rst = 0;
    A = 8'b00000011;
    B = 8'b00000010;
    #20;
end
endmodule