data/full_repos/permissive/490031785/Assignments/ass4.v
1: b'%Warning-WIDTH: data/full_repos/permissive/490031785/Assignments/ass4.v:11: Operator ADD expects 5 bits on the RHS, but RHS\'s VARREF \'Carry_in\' generates 1 bits.\n                                                                          : ... In instance BCD_Adder\n             Sum_temp = Addend + Augend + Carry_in;  \n                                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module BCD_Adder (Sum, Carry_out, Addend, Augend, Carry_in);
     	 input [3:0] Addend, Augend;
     		 input Carry_in;
      output [3:0] Sum;
     	 output Carry_out;
     	 reg [4:0] Sum_temp;
     	 reg [3:0] Sum;
     	 reg Carry_out;
    	 always @(Addend, Augend, Carry_in)
    	    begin
    	        Sum_temp = Addend + Augend + Carry_in;
    	        if(Sum_temp > 9)    begin
    	            Sum_temp = Sum_temp+6;
    	            Carry_out = 1;
    	            Sum = Sum_temp[3:0];    end
    	        else    begin
    	            Carry_out = 0;
    	            Sum = Sum_temp[3:0];
    	        end
    	    end     
    	
    	endmodule
module BCD_Adder (Sum, Carry_out, Addend, Augend, Carry_in);

     	 input [3:0] Addend, Augend;
     		 input Carry_in;
      output [3:0] Sum;
     	 output Carry_out;
     	 reg [4:0] Sum_temp;
     	 reg [3:0] Sum;
     	 reg Carry_out;
    	 always @(Addend, Augend, Carry_in)
    	    begin
    	        Sum_temp = Addend + Augend + Carry_in;
    	        if(Sum_temp > 9)    begin
    	            Sum_temp = Sum_temp+6;
    	            Carry_out = 1;
    	            Sum = Sum_temp[3:0];    end
    	        else    begin
    	            Carry_out = 0;
    	            Sum = Sum_temp[3:0];
    	        end
    	    end     
    	
    	endmodule