data/full_repos/permissive/452183855/lab1/t_Lab1.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/452183855/lab1/t_Lab1.v:13: Unsupported: Ignoring delay on this delayed statement.\n        #10  A=1\'b0; B=1\'b0; C=1\'b0; D=1\'b1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab1/t_Lab1.v:14: Unsupported: Ignoring delay on this delayed statement.\n        #10  A=1\'b0; B=1\'b0; C=1\'b1; D=1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab1/t_Lab1.v:15: Unsupported: Ignoring delay on this delayed statement.\n        #10  A=1\'b0; B=1\'b0; C=1\'b1; D=1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab1/t_Lab1.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #10  A=1\'b0; B=1\'b1; C=1\'b0; D=1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab1/t_Lab1.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #10  A=1\'b0; B=1\'b1; C=1\'b0; D=1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab1/t_Lab1.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #10  A=1\'b0; B=1\'b1; C=1\'b1; D=1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab1/t_Lab1.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #10  A=1\'b0; B=1\'b1; C=1\'b1; D=1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab1/t_Lab1.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #10  A=1\'b1; B=1\'b0; C=1\'b0; D=1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab1/t_Lab1.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #10  A=1\'b1; B=1\'b0; C=1\'b0; D=1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab1/t_Lab1.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #10  A=1\'b1; B=1\'b0; C=1\'b1; D=1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab1/t_Lab1.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #10  A=1\'b1; B=1\'b0; C=1\'b1; D=1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab1/t_Lab1.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #10  A=1\'b1; B=1\'b1; C=1\'b0; D=1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab1/t_Lab1.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #10  A=1\'b1; B=1\'b1; C=1\'b0; D=1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab1/t_Lab1.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #10  A=1\'b1; B=1\'b1; C=1\'b1; D=1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab1/t_Lab1.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #10  A=1\'b1; B=1\'b1; C=1\'b1; D=1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452183855/lab1/t_Lab1.v:30: Unsupported: Ignoring delay on this delayed statement.\n    initial #160 $finish;\n            ^\n%Error: data/full_repos/permissive/452183855/lab1/t_Lab1.v:34: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("Lab1_Simple_Circuit.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/452183855/lab1/t_Lab1.v:35: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 16 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module t_Lab1();
    wire F1, F2 ,F3;
    reg  A, B, C, D;


    Lab1_gatelevel      M1(F1, A, B, C, D);
    Lab1_dataflow       M2(F2, A, B, C, D);
    Lab1_gatelevel_UDP  M3(F3, A, B, C, D);


    initial begin 
         A=1'b0; B=1'b0; C=1'b0; D=1'b0;
        #10  A=1'b0; B=1'b0; C=1'b0; D=1'b1;
        #10  A=1'b0; B=1'b0; C=1'b1; D=1'b0;
        #10  A=1'b0; B=1'b0; C=1'b1; D=1'b1;
        #10  A=1'b0; B=1'b1; C=1'b0; D=1'b0;
        #10  A=1'b0; B=1'b1; C=1'b0; D=1'b1;
        #10  A=1'b0; B=1'b1; C=1'b1; D=1'b0;
        #10  A=1'b0; B=1'b1; C=1'b1; D=1'b1;
        #10  A=1'b1; B=1'b0; C=1'b0; D=1'b0;
        #10  A=1'b1; B=1'b0; C=1'b0; D=1'b1;
        #10  A=1'b1; B=1'b0; C=1'b1; D=1'b0;
        #10  A=1'b1; B=1'b0; C=1'b1; D=1'b1;
        #10  A=1'b1; B=1'b1; C=1'b0; D=1'b0;
        #10  A=1'b1; B=1'b1; C=1'b0; D=1'b1;
        #10  A=1'b1; B=1'b1; C=1'b1; D=1'b0;
        #10  A=1'b1; B=1'b1; C=1'b1; D=1'b1;

    end
    initial #160 $finish;
    

    initial begin
        $dumpfile("Lab1_Simple_Circuit.vcd");
        $dumpvars;
    end
endmodule
module t_Lab1();

    wire F1, F2 ,F3;
    reg  A, B, C, D;


    Lab1_gatelevel      M1(F1, A, B, C, D);
    Lab1_dataflow       M2(F2, A, B, C, D);
    Lab1_gatelevel_UDP  M3(F3, A, B, C, D);


    initial begin 
         A=1'b0; B=1'b0; C=1'b0; D=1'b0;
        #10  A=1'b0; B=1'b0; C=1'b0; D=1'b1;
        #10  A=1'b0; B=1'b0; C=1'b1; D=1'b0;
        #10  A=1'b0; B=1'b0; C=1'b1; D=1'b1;
        #10  A=1'b0; B=1'b1; C=1'b0; D=1'b0;
        #10  A=1'b0; B=1'b1; C=1'b0; D=1'b1;
        #10  A=1'b0; B=1'b1; C=1'b1; D=1'b0;
        #10  A=1'b0; B=1'b1; C=1'b1; D=1'b1;
        #10  A=1'b1; B=1'b0; C=1'b0; D=1'b0;
        #10  A=1'b1; B=1'b0; C=1'b0; D=1'b1;
        #10  A=1'b1; B=1'b0; C=1'b1; D=1'b0;
        #10  A=1'b1; B=1'b0; C=1'b1; D=1'b1;
        #10  A=1'b1; B=1'b1; C=1'b0; D=1'b0;
        #10  A=1'b1; B=1'b1; C=1'b0; D=1'b1;
        #10  A=1'b1; B=1'b1; C=1'b1; D=1'b0;
        #10  A=1'b1; B=1'b1; C=1'b1; D=1'b1;

    end
    initial #160 $finish;
    

    initial begin
        $dumpfile("Lab1_Simple_Circuit.vcd");
        $dumpvars;
    end
endmodule