data/full_repos/permissive/480681467/Source/Main/dff.v
data/verilator_xmls/82e34cc9-d0d8-4267-81a4-e6e40b33e0c2.xml
module dff(
    input D,
    input rst,
    input clk,
    output reg q
    );
    
    always @(posedge clk or posedge rst) begin
        if(rst) q<=0;
        else q<=D;
    end
    
endmodule
module dff(
    input D,
    input rst,
    input clk,
    output reg q
    );

    
    always @(posedge clk or posedge rst) begin
        if(rst) q<=0;
        else q<=D;
    end
    
endmodule