data/full_repos/permissive/441359809/src/yosys/examples/cmos/counter_tb.v
1: b'%Error: data/full_repos/permissive/441359809/src/yosys/examples/cmos/counter_tb.v:6: Unsupported or unknown PLI call: $dumpfile\n     $dumpfile("counter_tb.vcd");\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/examples/cmos/counter_tb.v:7: Unsupported or unknown PLI call: $dumpvars\n     $dumpvars(0,counter_tb);\n     ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/examples/cmos/counter_tb.v:9: Unsupported: Ignoring delay on this delayed statement.\n     # 0 reset = 1;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/examples/cmos/counter_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n     # 4 reset = 0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/examples/cmos/counter_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n     # 36 reset = 1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/examples/cmos/counter_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n     # 4  reset = 0;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/examples/cmos/counter_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n     # 6 $finish;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/examples/cmos/counter_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #6;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/examples/cmos/counter_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #2;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/examples/cmos/counter_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n  always #1 clk = !clk;\n         ^\n%Error: Exiting due to 2 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module counter_tb;


  reg reset = 0;
  initial begin
     $dumpfile("counter_tb.vcd");
     $dumpvars(0,counter_tb);

     # 0 reset = 1;
     # 4 reset = 0;
     # 36 reset = 1;
     # 4  reset = 0;
     # 6 $finish;
  end


  reg en = 1;
  always begin
    en = 1;
    #6;
    en = 0;
    #2;
  end


  reg clk = 0;
  always #1 clk = !clk;


  wire [2:0] count;
  counter c1 (clk, reset, en, count);

endmodule
module counter_tb;



  reg reset = 0;
  initial begin
     $dumpfile("counter_tb.vcd");
     $dumpvars(0,counter_tb);

     # 0 reset = 1;
     # 4 reset = 0;
     # 36 reset = 1;
     # 4  reset = 0;
     # 6 $finish;
  end


  reg en = 1;
  always begin
    en = 1;
    #6;
    en = 0;
    #2;
  end


  reg clk = 0;
  always #1 clk = !clk;


  wire [2:0] count;
  counter c1 (clk, reset, en, count);

endmodule