data/full_repos/permissive/431863558/combinational-circuits/basic-arithmetic/half_adder.v
data/verilator_xmls/9f779b50-a61b-4126-98af-52406c575175.xml
module half_adder ( output S, C,
		input x, y);

	assign {C, S} = x + y;

endmodule
module half_adder ( output S, C,
		input x, y);


	assign {C, S} = x + y;

endmodule