data/full_repos/permissive/458134463/Modules/ALUcontrol.v
data/verilator_xmls/94f9a3bf-0e95-4184-a46e-e061863527f2.xml
module ALUcontrol(ALUOp, func, ALUctr);

input  [2:0] ALUOp;
input  [2:0] func;

output [2:0] ALUctr;

wire ctr2_and0, ctr2_and1, ctr2_and2, ctr2_and3;
wire ctr1_and0, ctr1_and1, ctr1_and2;
wire ctr0_and0, ctr0_and1;

wire [2:0] ALUOpNot;
wire [2:0] funcNot;


not not0(ALUOpNot[0], ALUOp[0]),
	 not1(ALUOpNot[1], ALUOp[1]),
	 not2(ALUOpNot[2], ALUOp[2]),
	 not3(funcNot[0], func[0]),
	 not4(funcNot[1], func[1]),
	 not5(funcNot[2], func[2]);


and and0(ctr2_and0, ALUOpNot[2], ALUOpNot[1], ALUOpNot[0], func[2], funcNot[1]),
	 and1(ctr2_and1, ALUOpNot[2], ALUOp[1], ALUOp[0]),
	 and2(ctr2_and2, ALUOp[2], ALUOpNot[1], ALUOpNot[0]),
	 and3(ctr2_and3, ALUOp[2], ALUOp[1], ALUOpNot[0]);
	 

and and4(ctr1_and0, ALUOpNot[2], ALUOpNot[1], ALUOpNot[0], funcNot[2], func[1]),
	 and5(ctr1_and1, ALUOp[2], ALUOpNot[1], ALUOp[0]),
	 and6(ctr1_and2, ALUOp[2], ALUOp[1], ALUOpNot[0]);
	 

and and8(ctr0_and0, ALUOpNot[2], ALUOpNot[1], ALUOpNot[0], func[0]),
	 and9(ctr0_and1, ALUOpNot[2], ALUOp[0]);
	 

or	or0(ALUctr[2], ctr2_and0, ctr2_and1, ctr2_and2, ctr2_and3),
	or1(ALUctr[1], ctr1_and0, ctr1_and1, ctr1_and2),
	or2(ALUctr[0], ctr0_and0, ctr0_and1);
	 
endmodule
module ALUcontrol(ALUOp, func, ALUctr);


input  [2:0] ALUOp;
input  [2:0] func;

output [2:0] ALUctr;

wire ctr2_and0, ctr2_and1, ctr2_and2, ctr2_and3;
wire ctr1_and0, ctr1_and1, ctr1_and2;
wire ctr0_and0, ctr0_and1;

wire [2:0] ALUOpNot;
wire [2:0] funcNot;


not not0(ALUOpNot[0], ALUOp[0]),
	 not1(ALUOpNot[1], ALUOp[1]),
	 not2(ALUOpNot[2], ALUOp[2]),
	 not3(funcNot[0], func[0]),
	 not4(funcNot[1], func[1]),
	 not5(funcNot[2], func[2]);


and and0(ctr2_and0, ALUOpNot[2], ALUOpNot[1], ALUOpNot[0], func[2], funcNot[1]),
	 and1(ctr2_and1, ALUOpNot[2], ALUOp[1], ALUOp[0]),
	 and2(ctr2_and2, ALUOp[2], ALUOpNot[1], ALUOpNot[0]),
	 and3(ctr2_and3, ALUOp[2], ALUOp[1], ALUOpNot[0]);
	 

and and4(ctr1_and0, ALUOpNot[2], ALUOpNot[1], ALUOpNot[0], funcNot[2], func[1]),
	 and5(ctr1_and1, ALUOp[2], ALUOpNot[1], ALUOp[0]),
	 and6(ctr1_and2, ALUOp[2], ALUOp[1], ALUOpNot[0]);
	 

and and8(ctr0_and0, ALUOpNot[2], ALUOpNot[1], ALUOpNot[0], func[0]),
	 and9(ctr0_and1, ALUOpNot[2], ALUOp[0]);
	 

or	or0(ALUctr[2], ctr2_and0, ctr2_and1, ctr2_and2, ctr2_and3),
	or1(ALUctr[1], ctr1_and0, ctr1_and1, ctr1_and2),
	or2(ALUctr[0], ctr0_and0, ctr0_and1);
	 
endmodule