data/full_repos/permissive/42434302/ivltests/pr1492075.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1492075.v:23: Unsupported: Ignoring delay on this delayed statement.\n      #(10 + -2) clkb = 1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1492075.v:24: Unsupported: Ignoring delay on this delayed statement.\n      #(10 - -2) clkb = 0;\n      ^\n%Error: data/full_repos/permissive/42434302/ivltests/pr1492075.v:31: Unsupported or unknown PLI call: $monitor\n $monitor("clkb=%b at %t", clkb, $time);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1492075.v:34: Unsupported: Ignoring delay on this delayed statement.\n #1 clocken = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1492075.v:35: Unsupported: Ignoring delay on this delayed statement.\n #(10*20) clocken = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1492075.v:37: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cnr_tb ();

   reg clkb;
   reg clocken;
   integer  cntb;


   always @ (posedge clocken)
     begin
	for (cntb=0; cntb<5; cntb=cntb+1)
	  begin
	     #(10 + -2) clkb = 1;
	     #(10 - -2) clkb = 0;
	  end
     end


   initial
     begin
	$monitor("clkb=%b at %t", clkb, $time);
	clkb = 1'b0;
	clocken = 0;
	#1 clocken = 1;
	#(10*20) clocken = 0;

	#100;
	$finish;
     end

endmodule
module cnr_tb ();


   reg clkb;
   reg clocken;
   integer  cntb;


   always @ (posedge clocken)
     begin
	for (cntb=0; cntb<5; cntb=cntb+1)
	  begin
	     #(10 + -2) clkb = 1;
	     #(10 - -2) clkb = 0;
	  end
     end


   initial
     begin
	$monitor("clkb=%b at %t", clkb, $time);
	clkb = 1'b0;
	clocken = 0;
	#1 clocken = 1;
	#(10*20) clocken = 0;

	#100;
	$finish;
     end

endmodule