data/full_repos/permissive/42149584/Lab6-Part1/SDAmodule_tb.v
1: b'%Error: data/full_repos/permissive/42149584/Lab6-Part1/SDAmodule_tb.v:22: Unsupported: fork statements\n initial fork\n         ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/SDAmodule_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #0 ReadorWrite = 0; #12 ReadorWrite = 1; #34 ReadorWrite = 0; #56 ReadorWrite = 1; #78 ReadorWrite = 0; \n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/SDAmodule_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #0 ReadorWrite = 0; #12 ReadorWrite = 1; #34 ReadorWrite = 0; #56 ReadorWrite = 1; #78 ReadorWrite = 0; \n                     ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/SDAmodule_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #0 ReadorWrite = 0; #12 ReadorWrite = 1; #34 ReadorWrite = 0; #56 ReadorWrite = 1; #78 ReadorWrite = 0; \n                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/SDAmodule_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #0 ReadorWrite = 0; #12 ReadorWrite = 1; #34 ReadorWrite = 0; #56 ReadorWrite = 1; #78 ReadorWrite = 0; \n                                                               ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/SDAmodule_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #0 ReadorWrite = 0; #12 ReadorWrite = 1; #34 ReadorWrite = 0; #56 ReadorWrite = 1; #78 ReadorWrite = 0; \n                                                                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/SDAmodule_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n #0 Select = 0;  #21 Select = 1; #35 Select = 0; #77 Select = 1; #96 Select = 0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/SDAmodule_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n #0 Select = 0;  #21 Select = 1; #35 Select = 0; #77 Select = 1; #96 Select = 0; \n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/SDAmodule_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n #0 Select = 0;  #21 Select = 1; #35 Select = 0; #77 Select = 1; #96 Select = 0; \n                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/SDAmodule_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n #0 Select = 0;  #21 Select = 1; #35 Select = 0; #77 Select = 1; #96 Select = 0; \n                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/SDAmodule_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n #0 Select = 0;  #21 Select = 1; #35 Select = 0; #77 Select = 1; #96 Select = 0; \n                                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/SDAmodule_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #0 StartStopAck = 1;  #38 StartStopAck =0; #43 StartStopAck = 1; #50 StartStopAck =0; #53 StartStopAck = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/SDAmodule_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #0 StartStopAck = 1;  #38 StartStopAck =0; #43 StartStopAck = 1; #50 StartStopAck =0; #53 StartStopAck = 1;\n                       ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/SDAmodule_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #0 StartStopAck = 1;  #38 StartStopAck =0; #43 StartStopAck = 1; #50 StartStopAck =0; #53 StartStopAck = 1;\n                                            ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/SDAmodule_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #0 StartStopAck = 1;  #38 StartStopAck =0; #43 StartStopAck = 1; #50 StartStopAck =0; #53 StartStopAck = 1;\n                                                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/SDAmodule_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #0 StartStopAck = 1;  #38 StartStopAck =0; #43 StartStopAck = 1; #50 StartStopAck =0; #53 StartStopAck = 1;\n                                                                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/SDAmodule_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #94 StartStopAck =0; #98 StartStopAck = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/SDAmodule_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #94 StartStopAck =0; #98 StartStopAck = 1;\n                       ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/SDAmodule_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #0 ShiftOut = 0;   #21 ShiftOut = 1;  #34 ShiftOut = 0;  #45 ShiftOut = 1;   #57 ShiftOut = 0;  #87 ShiftOut = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/SDAmodule_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #0 ShiftOut = 0;   #21 ShiftOut = 1;  #34 ShiftOut = 0;  #45 ShiftOut = 1;   #57 ShiftOut = 0;  #87 ShiftOut = 1;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/SDAmodule_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #0 ShiftOut = 0;   #21 ShiftOut = 1;  #34 ShiftOut = 0;  #45 ShiftOut = 1;   #57 ShiftOut = 0;  #87 ShiftOut = 1;\n                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/SDAmodule_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #0 ShiftOut = 0;   #21 ShiftOut = 1;  #34 ShiftOut = 0;  #45 ShiftOut = 1;   #57 ShiftOut = 0;  #87 ShiftOut = 1;\n                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/SDAmodule_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #0 ShiftOut = 0;   #21 ShiftOut = 1;  #34 ShiftOut = 0;  #45 ShiftOut = 1;   #57 ShiftOut = 0;  #87 ShiftOut = 1;\n                                                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/SDAmodule_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #0 ShiftOut = 0;   #21 ShiftOut = 1;  #34 ShiftOut = 0;  #45 ShiftOut = 1;   #57 ShiftOut = 0;  #87 ShiftOut = 1;\n                                                                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/SDAmodule_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #100 $stop;\n ^\n%Error: Exiting due to 1 error(s), 24 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module SDAmodule_tb;


	reg ReadorWrite;
	reg Select;
	reg StartStopAck;
	reg ShiftOut;


	wire ShiftIn;


	wire SDA;


	SDAmodule uut (SDA, ReadorWrite, Select, StartStopAck, ShiftIn, ShiftOut);

	initial begin  ReadorWrite = 0;  Select = 0;  StartStopAck=1;  ShiftOut = 0;  end
	
	initial fork
	
	#0 ReadorWrite = 0; #12 ReadorWrite = 1; #34 ReadorWrite = 0; #56 ReadorWrite = 1; #78 ReadorWrite = 0; 
	#0 Select = 0;  #21 Select = 1; #35 Select = 0; #77 Select = 1; #96 Select = 0; 
	#0 StartStopAck = 1;  #38 StartStopAck =0; #43 StartStopAck = 1; #50 StartStopAck =0; #53 StartStopAck = 1;
	 #94 StartStopAck =0; #98 StartStopAck = 1;
	
	#0 ShiftOut = 0;  	#21 ShiftOut = 1; 	#34 ShiftOut = 0; 	#45 ShiftOut = 1;  	#57 ShiftOut = 0;  #87 ShiftOut = 1;
	#100 $stop;
	join
      
endmodule
module SDAmodule_tb;



	reg ReadorWrite;
	reg Select;
	reg StartStopAck;
	reg ShiftOut;


	wire ShiftIn;


	wire SDA;


	SDAmodule uut (SDA, ReadorWrite, Select, StartStopAck, ShiftIn, ShiftOut);

	initial begin  ReadorWrite = 0;  Select = 0;  StartStopAck=1;  ShiftOut = 0;  end
	
	initial fork
	
	#0 ReadorWrite = 0; #12 ReadorWrite = 1; #34 ReadorWrite = 0; #56 ReadorWrite = 1; #78 ReadorWrite = 0; 
	#0 Select = 0;  #21 Select = 1; #35 Select = 0; #77 Select = 1; #96 Select = 0; 
	#0 StartStopAck = 1;  #38 StartStopAck =0; #43 StartStopAck = 1; #50 StartStopAck =0; #53 StartStopAck = 1;
	 #94 StartStopAck =0; #98 StartStopAck = 1;
	
	#0 ShiftOut = 0;  	#21 ShiftOut = 1; 	#34 ShiftOut = 0; 	#45 ShiftOut = 1;  	#57 ShiftOut = 0;  #87 ShiftOut = 1;
	#100 $stop;
	join
      
endmodule