data/full_repos/permissive/445379100/a4/alu.v
data/verilator_xmls/926530d0-3afb-4f11-8a3e-4e37a428bb82.xml
module alu (
    input [3:0] alu_op ,
    input [31:0] operand1 ,
    input [31:0] operand2 ,
    output reg [31:0] alu_out
);
    always @(*) begin

        case ( alu_op ) 
            4'd0         :  alu_out = (operand1) + (operand2) ;
            4'd1         :  alu_out = (operand1) - (operand2) ;
            4'd2         :  alu_out = operand1 << operand1 ;
            4'd3         :  alu_out = ( $signed(operand1) < $signed(operand2) )? 32'b1 : 32'b0 ;
            4'd4         :  alu_out = ( $unsigned(operand1) < $unsigned(operand2) )? 32'b1 : 32'b0 ;
            4'd5         :  alu_out = operand1 ^ operand2 ;
            4'd6         :  alu_out = operand1 >> operand2 ;
            4'd7         :  alu_out = $signed(operand1) >>> operand2 ;
            4'd8         :  alu_out = operand1 | operand2 ;
            4'd9         :  alu_out = operand1 & operand2 ;

            4'd10        :  alu_out = ( operand1 == operand2 )? 32'b1 : 32'b0 ;
            4'd11        :  begin
                                alu_out = operand1 + operand2 ;
                                alu_out[0] = 0 ;
                            end


            
            default   :  alu_out = 0 ;
        endcase       
    
    end

endmodule
module alu (
    input [3:0] alu_op ,
    input [31:0] operand1 ,
    input [31:0] operand2 ,
    output reg [31:0] alu_out
);

    always @(*) begin

        case ( alu_op ) 
            4'd0         :  alu_out = (operand1) + (operand2) ;
            4'd1         :  alu_out = (operand1) - (operand2) ;
            4'd2         :  alu_out = operand1 << operand1 ;
            4'd3         :  alu_out = ( $signed(operand1) < $signed(operand2) )? 32'b1 : 32'b0 ;
            4'd4         :  alu_out = ( $unsigned(operand1) < $unsigned(operand2) )? 32'b1 : 32'b0 ;
            4'd5         :  alu_out = operand1 ^ operand2 ;
            4'd6         :  alu_out = operand1 >> operand2 ;
            4'd7         :  alu_out = $signed(operand1) >>> operand2 ;
            4'd8         :  alu_out = operand1 | operand2 ;
            4'd9         :  alu_out = operand1 & operand2 ;

            4'd10        :  alu_out = ( operand1 == operand2 )? 32'b1 : 32'b0 ;
            4'd11        :  begin
                                alu_out = operand1 + operand2 ;
                                alu_out[0] = 0 ;
                            end


            
            default   :  alu_out = 0 ;
        endcase       
    
    end

endmodule