data/full_repos/permissive/434840709/week13/3.v
data/verilator_xmls/3a584867-37e3-487e-8166-9cc6b6c26680.xml
module top_module (
    input clk,
    input reset,
    output [3:0] q
);
    reg [3:0] count;
    always @(posedge clk) begin
        if (reset) begin
            count <= 0;
        end 
        else begin
            if (count < 15) begin
                count <= count + 1;
            end 
            else begin
                count <= 0;
            end
        end    
    end

    assign q = count;

endmodule
module top_module (
    input clk,
    input reset,
    output [3:0] q
);

    reg [3:0] count;
    always @(posedge clk) begin
        if (reset) begin
            count <= 0;
        end 
        else begin
            if (count < 15) begin
                count <= count + 1;
            end 
            else begin
                count <= 0;
            end
        end    
    end

    assign q = count;

endmodule