data/full_repos/permissive/504550651/verilog/rtl/rocketAlpha/chipyard.TestHarness.RocketAlphaConfig.top.mems.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/504550651/verilog/rtl/rocketAlpha/chipyard.TestHarness.RocketAlphaConfig.top.mems.v:472: Multiple top level modules\n                                                                                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                                                     : ... Top module \'data_arrays_0_ext\'\nmodule data_arrays_0_ext(\n       ^~~~~~~~~~~~~~~~~\n                                                                                                                                     : ... Top module \'tag_array_ext\'\nmodule tag_array_ext(\n       ^~~~~~~~~~~~~\n                                                                                                                                     : ... Top module \'data_arrays_0_0_ext\'\nmodule data_arrays_0_0_ext(\n       ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504550651/verilog/rtl/rocketAlpha/chipyard.TestHarness.RocketAlphaConfig.top.mems.v:549: Cannot find file containing module: \'sky130_sram_2kbyte_1rw1r_32x512_8\'\n  sky130_sram_2kbyte_1rw1r_32x512_8 mem_0_0 (\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/504550651/verilog/rtl/rocketAlpha,data/full_repos/permissive/504550651/sky130_sram_2kbyte_1rw1r_32x512_8\n             data/full_repos/permissive/504550651/verilog/rtl/rocketAlpha,data/full_repos/permissive/504550651/sky130_sram_2kbyte_1rw1r_32x512_8.v\n             data/full_repos/permissive/504550651/verilog/rtl/rocketAlpha,data/full_repos/permissive/504550651/sky130_sram_2kbyte_1rw1r_32x512_8.sv\n             sky130_sram_2kbyte_1rw1r_32x512_8\n             sky130_sram_2kbyte_1rw1r_32x512_8.v\n             sky130_sram_2kbyte_1rw1r_32x512_8.sv\n             obj_dir/sky130_sram_2kbyte_1rw1r_32x512_8\n             obj_dir/sky130_sram_2kbyte_1rw1r_32x512_8.v\n             obj_dir/sky130_sram_2kbyte_1rw1r_32x512_8.sv\n%Error: data/full_repos/permissive/504550651/verilog/rtl/rocketAlpha/chipyard.TestHarness.RocketAlphaConfig.top.mems.v:499: Cannot find file containing module: \'sky130_sram_1kbyte_1rw1r_32x256_8\'\n  sky130_sram_1kbyte_1rw1r_32x256_8 mem_0_0 (\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504550651/verilog/rtl/rocketAlpha/chipyard.TestHarness.RocketAlphaConfig.top.mems.v:251: Cannot find file containing module: \'sky130_sram_2kbyte_1rw1r_32x512_8\'\n  sky130_sram_2kbyte_1rw1r_32x512_8 mem_0_0 (\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504550651/verilog/rtl/rocketAlpha/chipyard.TestHarness.RocketAlphaConfig.top.mems.v:263: Cannot find file containing module: \'sky130_sram_2kbyte_1rw1r_32x512_8\'\n  sky130_sram_2kbyte_1rw1r_32x512_8 mem_0_1 (\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504550651/verilog/rtl/rocketAlpha/chipyard.TestHarness.RocketAlphaConfig.top.mems.v:275: Cannot find file containing module: \'sky130_sram_2kbyte_1rw1r_32x512_8\'\n  sky130_sram_2kbyte_1rw1r_32x512_8 mem_1_0 (\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504550651/verilog/rtl/rocketAlpha/chipyard.TestHarness.RocketAlphaConfig.top.mems.v:287: Cannot find file containing module: \'sky130_sram_2kbyte_1rw1r_32x512_8\'\n  sky130_sram_2kbyte_1rw1r_32x512_8 mem_1_1 (\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504550651/verilog/rtl/rocketAlpha/chipyard.TestHarness.RocketAlphaConfig.top.mems.v:299: Cannot find file containing module: \'sky130_sram_2kbyte_1rw1r_32x512_8\'\n  sky130_sram_2kbyte_1rw1r_32x512_8 mem_2_0 (\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504550651/verilog/rtl/rocketAlpha/chipyard.TestHarness.RocketAlphaConfig.top.mems.v:311: Cannot find file containing module: \'sky130_sram_2kbyte_1rw1r_32x512_8\'\n  sky130_sram_2kbyte_1rw1r_32x512_8 mem_2_1 (\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504550651/verilog/rtl/rocketAlpha/chipyard.TestHarness.RocketAlphaConfig.top.mems.v:323: Cannot find file containing module: \'sky130_sram_2kbyte_1rw1r_32x512_8\'\n  sky130_sram_2kbyte_1rw1r_32x512_8 mem_3_0 (\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504550651/verilog/rtl/rocketAlpha/chipyard.TestHarness.RocketAlphaConfig.top.mems.v:335: Cannot find file containing module: \'sky130_sram_2kbyte_1rw1r_32x512_8\'\n  sky130_sram_2kbyte_1rw1r_32x512_8 mem_3_1 (\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 10 error(s), 1 warning(s)\n'
module data_arrays_0_0_ext(
  input  [8:0]  RW0_addr,
  input         RW0_clk,
  input  [31:0] RW0_wdata,
  output [31:0] RW0_rdata,
  input         RW0_en,
  input         RW0_wmode,
  input         RW0_wmask
);
  wire [8:0] mem_0_0_addr0;
  wire  mem_0_0_clk0;
  wire [31:0] mem_0_0_din0;
  wire [31:0] mem_0_0_dout0;
  wire  mem_0_0_csb0;
  wire  mem_0_0_web0;
  wire [7:0] mem_0_0_wmask0;
  wire  mem_0_0_clk1;
  wire  mem_0_0_csb1;
  wire [8:0] mem_0_0_addr1;
  wire [31:0] RW0_rdata_0_0 = mem_0_0_dout0;
  wire [31:0] RW0_rdata_0 = RW0_rdata_0_0;
  wire [1:0] _GEN_0 = {RW0_wmask,RW0_wmask};
  wire [2:0] _GEN_1 = {RW0_wmask,RW0_wmask,RW0_wmask};
  wire [3:0] _GEN_2 = {RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask};
  wire [4:0] _GEN_3 = {RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask};
  wire [5:0] _GEN_4 = {RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask};
  wire [6:0] _GEN_5 = {RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask};
  sky130_sram_2kbyte_1rw1r_32x512_8 mem_0_0 (
    .addr0(mem_0_0_addr0),
    .clk0(mem_0_0_clk0),
    .din0(mem_0_0_din0),
    .dout0(mem_0_0_dout0),
    .csb0(mem_0_0_csb0),
    .web0(mem_0_0_web0),
    .wmask0(mem_0_0_wmask0),
    .clk1(mem_0_0_clk1),
    .csb1(mem_0_0_csb1),
    .addr1(mem_0_0_addr1)
  );
  assign RW0_rdata = mem_0_0_dout0;
  assign mem_0_0_addr0 = RW0_addr;
  assign mem_0_0_clk0 = RW0_clk;
  assign mem_0_0_din0 = RW0_wdata;
  assign mem_0_0_csb0 = ~RW0_en;
  assign mem_0_0_web0 = ~RW0_wmode;
  assign mem_0_0_wmask0 = {RW0_wmask,_GEN_5};
  assign mem_0_0_clk1 = 1'h0;
  assign mem_0_0_csb1 = 1'h0;
  assign mem_0_0_addr1 = 9'h0;
endmodule
module data_arrays_0_0_ext(
  input  [8:0]  RW0_addr,
  input         RW0_clk,
  input  [31:0] RW0_wdata,
  output [31:0] RW0_rdata,
  input         RW0_en,
  input         RW0_wmode,
  input         RW0_wmask
);

  wire [8:0] mem_0_0_addr0;
  wire  mem_0_0_clk0;
  wire [31:0] mem_0_0_din0;
  wire [31:0] mem_0_0_dout0;
  wire  mem_0_0_csb0;
  wire  mem_0_0_web0;
  wire [7:0] mem_0_0_wmask0;
  wire  mem_0_0_clk1;
  wire  mem_0_0_csb1;
  wire [8:0] mem_0_0_addr1;
  wire [31:0] RW0_rdata_0_0 = mem_0_0_dout0;
  wire [31:0] RW0_rdata_0 = RW0_rdata_0_0;
  wire [1:0] _GEN_0 = {RW0_wmask,RW0_wmask};
  wire [2:0] _GEN_1 = {RW0_wmask,RW0_wmask,RW0_wmask};
  wire [3:0] _GEN_2 = {RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask};
  wire [4:0] _GEN_3 = {RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask};
  wire [5:0] _GEN_4 = {RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask};
  wire [6:0] _GEN_5 = {RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask,RW0_wmask};
  sky130_sram_2kbyte_1rw1r_32x512_8 mem_0_0 (
    .addr0(mem_0_0_addr0),
    .clk0(mem_0_0_clk0),
    .din0(mem_0_0_din0),
    .dout0(mem_0_0_dout0),
    .csb0(mem_0_0_csb0),
    .web0(mem_0_0_web0),
    .wmask0(mem_0_0_wmask0),
    .clk1(mem_0_0_clk1),
    .csb1(mem_0_0_csb1),
    .addr1(mem_0_0_addr1)
  );
  assign RW0_rdata = mem_0_0_dout0;
  assign mem_0_0_addr0 = RW0_addr;
  assign mem_0_0_clk0 = RW0_clk;
  assign mem_0_0_din0 = RW0_wdata;
  assign mem_0_0_csb0 = ~RW0_en;
  assign mem_0_0_web0 = ~RW0_wmode;
  assign mem_0_0_wmask0 = {RW0_wmask,_GEN_5};
  assign mem_0_0_clk1 = 1'h0;
  assign mem_0_0_csb1 = 1'h0;
  assign mem_0_0_addr1 = 9'h0;
endmodule