data/full_repos/permissive/485129576/mux2t1.v
data/verilator_xmls/1fd0572f-1de9-4572-8051-7cde7405fe08.xml
module MUX2t1 (
    input [7:0] A,
    input [7:0] B,
    input sel,
    output reg [7:0] R
);
    always@(*) begin
        case(sel)
            1'b0 : R = A;
            1'b1 : R = B;
        endcase
    end

endmodule
module MUX2t1 (
    input [7:0] A,
    input [7:0] B,
    input sel,
    output reg [7:0] R
);

    always@(*) begin
        case(sel)
            1'b0 : R = A;
            1'b1 : R = B;
        endcase
    end

endmodule