data/full_repos/permissive/468612001/Week04/fulladder_4bit/tb_fulladder_4bit.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/468612001/Week04/fulladder_4bit/tb_fulladder_4bit.v:29: Unsupported: Ignoring delay on this delayed statement.\n   #10;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week04/fulladder_4bit/tb_fulladder_4bit.v:38: Unsupported: Ignoring delay on this delayed statement.\n   #10;\n   ^\n%Error: data/full_repos/permissive/468612001/Week04/fulladder_4bit/tb_fulladder_4bit.v:10: Cannot find file containing module: \'fulladder_4bit\'\n fulladder_4bit fa4(\n ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/468612001/Week04/fulladder_4bit,data/full_repos/permissive/468612001/fulladder_4bit\n             data/full_repos/permissive/468612001/Week04/fulladder_4bit,data/full_repos/permissive/468612001/fulladder_4bit.v\n             data/full_repos/permissive/468612001/Week04/fulladder_4bit,data/full_repos/permissive/468612001/fulladder_4bit.sv\n             fulladder_4bit\n             fulladder_4bit.v\n             fulladder_4bit.sv\n             obj_dir/fulladder_4bit\n             obj_dir/fulladder_4bit.v\n             obj_dir/fulladder_4bit.sv\n%Warning-WIDTH: data/full_repos/permissive/468612001/Week04/fulladder_4bit/tb_fulladder_4bit.v:28: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                                                 : ... In instance tb_fulladder_4bit\n   {b, a} = i;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/468612001/Week04/fulladder_4bit/tb_fulladder_4bit.v:37: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n                                                                                                 : ... In instance tb_fulladder_4bit\n   {b, a} = i;\n          ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_fulladder_4bit;
	parameter N = 4;
	reg [N-1:0] a;
	reg [N-1:0] b;
	reg c_in;
	
	wire [3:0] sum;
	wire c_cout;
	
	fulladder_4bit fa4(
		.a(a),
		.b(b),
		.cin(c_in),
		.sum(sum),
		.cout(c_cout)
	);
	
	integer i;
	

	initial
	begin
	

		c_in = 1'b0;
		for(i=0; i<2**(2*N); i=i+1)
		begin
			{b, a} = i;
			#10;
			$display("a=", a, " b=", b, " sum=", sum, " cout=", c_cout);
		end
	

		c_in = 1'b1;
		for(i=0; i<2**(2*N); i=i+1)
		begin
			{b, a} = i;
			#10;
			$display("a=", a, " b=", b, " sum=", sum, " cout=", c_cout);
		end
	end
endmodule
module tb_fulladder_4bit;

	parameter N = 4;
	reg [N-1:0] a;
	reg [N-1:0] b;
	reg c_in;
	
	wire [3:0] sum;
	wire c_cout;
	
	fulladder_4bit fa4(
		.a(a),
		.b(b),
		.cin(c_in),
		.sum(sum),
		.cout(c_cout)
	);
	
	integer i;
	

	initial
	begin
	

		c_in = 1'b0;
		for(i=0; i<2**(2*N); i=i+1)
		begin
			{b, a} = i;
			#10;
			$display("a=", a, " b=", b, " sum=", sum, " cout=", c_cout);
		end
	

		c_in = 1'b1;
		for(i=0; i<2**(2*N); i=i+1)
		begin
			{b, a} = i;
			#10;
			$display("a=", a, " b=", b, " sum=", sum, " cout=", c_cout);
		end
	end
endmodule