data/full_repos/permissive/500947188/rtl/AthenaCore.sv
1: b'%Error: data/full_repos/permissive/500947188/rtl/AthenaCore.sv:124: Cannot find file containing module: \'TNKIIICoreClocks_Cen\'\n    TNKIIICoreClocks_Cen amc_clk_cen(\n    ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/500947188/rtl,data/full_repos/permissive/500947188/TNKIIICoreClocks_Cen\n             data/full_repos/permissive/500947188/rtl,data/full_repos/permissive/500947188/TNKIIICoreClocks_Cen.v\n             data/full_repos/permissive/500947188/rtl,data/full_repos/permissive/500947188/TNKIIICoreClocks_Cen.sv\n             TNKIIICoreClocks_Cen\n             TNKIIICoreClocks_Cen.v\n             TNKIIICoreClocks_Cen.sv\n             obj_dir/TNKIIICoreClocks_Cen\n             obj_dir/TNKIIICoreClocks_Cen.v\n             obj_dir/TNKIIICoreClocks_Cen.sv\n%Error: data/full_repos/permissive/500947188/rtl/AthenaCore.sv:141: Cannot find file containing module: \'TNKIIICore_Clocks_Sync\'\nTNKIIICore_Clocks_Sync amc_clocks_sync(\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/AthenaCore.sv:207: Cannot find file containing module: \'AthenaCore_CPU_A_B_sync\'\n    AthenaCore_CPU_A_B_sync cpuA_B_sync\n    ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/AthenaCore.sv:275: Cannot find file containing module: \'Dual_YM3526_Sound\'\n    Dual_YM3526_Sound amc_snd_sync\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/AthenaCore.sv:310: Cannot find file containing module: \'AthenaCore_Registers_sync\'\n    AthenaCore_Registers_sync athena_registers(\n    ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/AthenaCore.sv:349: Cannot find file containing module: \'AthenaCore_Side_sync\'\n    AthenaCore_Side_sync amc_side_sync(\n    ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/AthenaCore.sv:397: Cannot find file containing module: \'TNKIIICore_Back1_sync\'\n    TNKIIICore_Back1_sync amc_back1_sync(\n    ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/AthenaCore.sv:459: Cannot find file containing module: \'AthenaCore_Front_sync\'\n    AthenaCore_Front_sync amc_front_sync(\n    ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/AthenaCore.sv:503: Cannot find file containing module: \'TNKIIICore_LineBuffer_sync\'\n    TNKIIICore_LineBuffer_sync amc_linebuf_sync(\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/AthenaCore.sv:534: Cannot find file containing module: \'TNKIIICore_FinalVideo_sync\'\n    TNKIIICore_FinalVideo_sync amc_video_mixer(\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/500947188/rtl/AthenaCore.sv:564: Operator ASSIGNW expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'X\' generates 8 bits.\n                                                                          : ... In instance AthenaCore\n    assign SCR_X = X;\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 10 error(s), 1 warning(s)\n'
module AthenaCore
(
    input wire RESETn,
    input wire VIDEO_RSTn,
    input wire pause_cpu,
    input wire i_clk,
    input wire [15:0] PLAYER1,
    input wire [15:0] PLAYER2,
    input wire [15:0] TRACKBALL1,
    input wire [15:0] TRACKBALL2,
    input wire [7:0] GAME,
    input wire [15:0] DSW,
    output wire player_ctrl_clk,


    input wire [7:0] hack_settings,


	input wire         [24:0] ioctl_addr,
	input wire         [7:0] ioctl_data,
	input wire               ioctl_wr,


    input wire [2:0] layer_ena_dbg,
    input wire [3:0] dbg_B1Voffset,
    input wire swap_px,


    output logic [3:0] R,
    output logic [3:0] G,
    output logic [3:0] B,
	 output logic HBLANK,
	 output logic VBLANK,
	 output logic HSYNC,
	 output logic VSYNC,
    output logic [8:0] SCR_Y,
    output logic [8:0] SCR_X,
    output logic VBL,
    output logic SYNC,
    output logic VS,
    output logic HS,
    output logic DISP,
    output logic PIX_CLK,
	 output logic CE_PIXEL,


    output wire signed [15:0] snd1,
    output wire signed [15:0] snd2,
    output wire sample
);
    logic VRD, AE, BE;
    
    logic CK0, CK0n, CK1, CK1n, LDn;
    logic HLDn;
    (* keep *) logic [8:0] H;
    (* keep *) logic [2:0] Hn;
    logic [8:0] FH;
    logic FCK;
    logic [7:0] Y;
    logic [7:0] X;
    logic [8:0] FV;
    logic VCKn;
    logic LT;
    logic VLK;
    logic VFLGn;
    logic VDG, V_C;
    logic VWE, VOE;
    logic BWA, A_B, RLA, RLB, WBA, WBB;
    logic LA, LC, LD, HD8;


    logic  [7:0] AD;
    

    logic [7:0] VD_out, VD_in;
    logic [12:0] VA;


    logic FRONT_VIDEO_CSn;
    logic SIDE_VRAM_CSn;
    logic DISC;
    logic MSB;
    logic FSX;
    logic FSY;
    logic B1SX;
    logic B1SY;
    logic COIN_COUNTERS;
    logic BACK1_VRAM_CSn;


    logic INV;
    logic INVn;
    logic B1X8;
    logic B1Y8;
    logic FX8;
    logic FY8;
    

    logic COIN;
    logic P1;
    logic P2;
    logic P1_P2;
    logic MCODE;
    logic DIP1;
    logic DIP2;

     logic clk_13p4_cen;
     logic clk_13p4;
     logic clk_13p4b_cen;
     logic clk_13p4b;
     logic clk_6p7_cen;
     logic clk_6p7b_cen;
     logic clk_3p35_cen;
     logic clk_3p35b_cen;
     logic clk_4_cen;
     logic clk_4b_cen;

    TNKIIICoreClocks_Cen amc_clk_cen(
        .i_clk(i_clk),
        .clk_13p4_cen(clk_13p4_cen),
        .clk_13p4(clk_13p4),
        .clk_13p4b_cen(clk_13p4b_cen),
        .clk_13p4b(clk_13p4b),
        .clk_6p7_cen(clk_6p7_cen),
        .clk_6p7b_cen(clk_6p7b_cen),
        .clk_3p35_cen(clk_3p35_cen),
        .clk_3p35b_cen(clk_3p35b_cen),
        .clk_4_cen(clk_4_cen),
        .clk_4b_cen(clk_4b_cen)
    );
    
    assign player_ctrl_clk = clk_3p35_cen;
	 assign CE_PIXEL = clk_6p7_cen; 

TNKIIICore_Clocks_Sync amc_clocks_sync(
    .clk(i_clk),
    .clk_13p4_cen(clk_13p4_cen),
    .clk_13p4(clk_13p4),
    .clk_13p4b_cen(clk_13p4b_cen),
    .clk_13p4b(clk_13p4b),
    .clk_6p7_cen(clk_6p7_cen),
    .clk_6p7b_cen(clk_6p7b_cen),
    .reset(VIDEO_RSTn),
    .VIDEO_RSTn(VIDEO_RSTn),
    .INVn(INVn),
    .FSX(FSX),
    .FX8(FX8),

    .hack_settings(hack_settings),
    .VD_in(VD_in),
    .VRD(VRD),
    .AE(AE),
    .BE(BE),

    .CK0(CK0),
    .CK0n(CK0n),
    .HLDn(HLDn),
    .CK1(CK1),
    .CK1n(CK1n),
    .H(H),
    .Hn(Hn),
    .FH(FH),
    .FCK(FCK),
    .Y(Y),
    .X(X),
    .FV(FV),
    .VCKn(VCKn),
    .VBL(VBL),
    .DISP(DISP),
    .SYNC(SYNC),
	 .HBLANK(HBLANK),
	 .VBLANK(VBLANK),
    .HSYNC(HSYNC),
    .VSYNC(VSYNC),
    .LT(LT),

    .VWE(VWE),
    .VOE(VOE),
    .BWA(BWA),
    .A_B(A_B),
    .RLA(RLA),
    .RLB(RLB),
    .WBA(WBA),
    .WBB(WBB),
    .VDG(VDG),
    .VLK(VLK),
    .V_C(V_C),
    .VFLGn(VFLGn),
    .HD8(HD8),
    .LC(LC),
    .LD(LD),
    .LA(LA)
	);
    logic SND_BUSY;
    logic CPUA_WR;
    logic CPUA_RD;
    logic [7:0] CPUAD;



    AthenaCore_CPU_A_B_sync cpuA_B_sync
    (

        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .pause_cpu(pause_cpu),
        .H0(H[0]),
        .Cen_p(clk_3p35_cen),
        .Cen_n(clk_3p35b_cen),
        .RESETn(VIDEO_RSTn),
        .PLAYER1(PLAYER1),
        .PLAYER2(PLAYER2),
        .TRACKBALL1(TRACKBALL1),
	    .TRACKBALL2(TRACKBALL2),
        .GAME(GAME),
        .DSW(DSW),
        .VBL(VBL),
        .BWA(BWA),
        .A_B(A_B),
        .RLA(RLA),
        .RLB(RLB),
        .WBA(WBA),
        .WBB(WBB),
        .VDG(VDG),

        .VRDn(VRD),
        .AE(AE),
        .BE(BE),
        

        .CPUAD(CPUAD),
        .CPUA_RD(CPUA_RD),
        .CPUA_WR(CPUA_WR),


        .VA(VA),

        .V_out(VD_in),
        .V_in(VD_out),
        

        .ioctl_addr(ioctl_addr[19:0]),
        .ioctl_wr(ioctl_wr),
        .ioctl_data(ioctl_data),
        

        .SND_BUSY(SND_BUSY),
        .COIN(COIN),
        .P1(P1),
        .P2(P2),
        .P1_P2(P1_P2),
        .MCODE(MCODE),
        .DIP1(DIP1),
        .DIP2(DIP2),


        .FRONT_VIDEO_CSn(FRONT_VIDEO_CSn),
        .SIDE_VRAM_CSn(SIDE_VRAM_CSn),
        .DISC(DISC),
        .MSB(MSB),
        .FSX(FSX),
        .FSY(FSY),
        .B1SX(B1SX),
        .B1SY(B1SY),
        .COIN_COUNTERS(COIN_COUNTERS),
        .BACK1_VRAM_CSn(BACK1_VRAM_CSn)
    );

    Dual_YM3526_Sound amc_snd_sync
    (
        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .pause_cpu(pause_cpu),
        .CEN_p(clk_4_cen),
        .CEN_n(clk_4b_cen),
        .RESETn(VIDEO_RSTn),
        .data_in(CPUAD),
        .ioctl_addr(ioctl_addr[19:0]),
        .ioctl_wr(ioctl_wr),
        .ioctl_data(ioctl_data),
        .MCODE(MCODE),
        .MS(SND_BUSY),
        .snd1(snd1),
        .snd2(snd2),
        .sample(sample)
    );






    logic COIN1_CNT, COIN2_CNT;
    logic SIDE_ROM_BK;
    logic [7:0] FY;


    logic HACK_INV;
    logic HACK_INVn;
    assign INV = ((hack_settings[0])) ? ~HACK_INV : HACK_INV;
    assign INVn = (hack_settings[0]) ? ~HACK_INVn : HACK_INVn;


    AthenaCore_Registers_sync athena_registers(
        .VIDEO_RSTn(VIDEO_RSTn),
        .reset(VIDEO_RSTn),

        .clk(i_clk),
        .MSB(MSB),
        .VD_in(VD_in),


        .INV(HACK_INV),
        .INVn(HACK_INVn),
        .SIDE_ROM_BK(SIDE_ROM_BK),
        .B1X8(B1X8),
        .FX8(FX8),
        .B1Y8(B1Y8),
        .FY8(FY8),










        .COIN_COUNTERS(COIN_COUNTERS),
        .COIN1_CNT(COIN1_CNT),
        .COIN2_CNT(COIN2_CNT),
        .FSY(FSY),
        .FY(FY)
    );


    logic [6:0] SD;


    logic SIDE_SELn;
    logic [7:0] side_vout;
    AthenaCore_Side_sync amc_side_sync(
        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .CK1(CK1),

        .INV(INV),
        .INVn(INVn),


        .VD_in(VD_in),
        .VD_out(side_vout),

        .ioctl_addr(ioctl_addr[19:0]),
        .ioctl_wr(ioctl_wr),
        .ioctl_data(ioctl_data),

        .V_C(V_C),

        .SIDE_VRAM_CSn(SIDE_VRAM_CSn),
        .VA(VA[10:0]),

        .VFLGn(VFLGn),
        .H8(H[8]),
        .Y(Y[7:3]),
        .X(X), 


        .VRD(VRD),
        .VDG(VDG),
        .VOE(VOE),
        .VWE(VWE),


        .VLK(VLK),
        .H2n(Hn[2]),
        .H1n(Hn[1]),
        .H0n(Hn[0]),


        .SD(SD[6:0]),


        .SIDE_BK(SIDE_ROM_BK)
    );

    logic [7:0] B1D;

    logic [7:0] back1_vout;
    TNKIIICore_Back1_sync amc_back1_sync(
        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .CK1(CK1),
        .RESET(VIDEO_RSTn),

        .INV(INV),
        .INVn(INVn),

        .VD_in(VD_in),
        .VD_out(back1_vout),


        .hack_settings(hack_settings),
        .dbg_B1Voffset(dbg_B1Voffset),
        .swap_px(swap_px),

        .ioctl_addr(ioctl_addr[19:0]),
        .ioctl_wr(ioctl_wr),
        .ioctl_data(ioctl_data),

        .B1SY(B1SY),
        .B1SX(B1SX),

        .B1Y8(B1Y8),
        .B1X8(B1X8),

        .V_C(V_C),

        .H8(H[8]),
        .Y(Y[7:3]),
        .H2(H[2]),
        .H1(H[1]),
        .H0(H[0]),
        .X(X), 
        .VA(VA),
        .BACK1_VRAM_CSn(BACK1_VRAM_CSn),
        

        .VFLGn(VFLGn),


        .VRD(VRD),
        .VDG(VDG),
        .VOE(VOE),
        .VWE(VWE),


        .CK1n(CK1n),
        .LA(LA),
        .VLK(VLK),



        .JMP_B1D7(1'b0),
        .B1_COLBK(1'b0),
        .B1D(B1D[7:0])
    );
    
    logic [7:0] FD;
    logic [8:0] FL_Y;
    logic [7:0] front_vout;
    AthenaCore_Front_sync amc_front_sync(
        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .CK1(CK1),

        .VD_in(VD_in),
        .VD_out(front_vout),

        .hack_settings(hack_settings),

        .ioctl_addr(ioctl_addr[19:0]),
        .ioctl_wr(ioctl_wr),
        .ioctl_data(ioctl_data),

        .V_C(V_C),

        .FRONT_VIDEO_CSn(FRONT_VIDEO_CSn),
        .VA(VA[10:0]),

        .VCKn(VCKn),

        .VRD(VRD),
        .VDG(VDG),
        .VOE(VOE),
        .VWE(VWE),

        .FH(FH[8:4]),
        .FV(FV),
        .LC(LC),
        .VLK(VLK),

        .FCK(FCK),

        .H3(H[3]),
        .LD(LD),
        .CK0(CK0),

        .FD(FD),
        .FL_Y(FL_Y)
    );

    logic [7:0] LD_BUF;
    logic FYocho;
    assign FYocho = FY8;
    TNKIIICore_LineBuffer_sync amc_linebuf_sync(

        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .RESETn(VIDEO_RSTn),
        .FD(FD),
        .LT(LT),
        .VCKn(VCKn),
        .CK1(CK1),
        .CK1n(CK1n),
        .CK0(CK0),
        .CK0n(CK0n),
        .FCK(FCK),
        .LD(LD),
        .FL_Y(FL_Y),
        .HLD(HLDn),

        .hack_settings(hack_settings),
        .FY8(FYocho),
        .FY(FY),
        .INVn(INVn),

        .LD_BUF(LD_BUF)
    );


        assign VD_out = ( (!VDG && !SIDE_VRAM_CSn)   ? side_vout  : (
                          (!VDG && !BACK1_VRAM_CSn)  ? back1_vout : (
                          (!VDG && !FRONT_VIDEO_CSn) ? front_vout : 8'hff )));


    TNKIIICore_FinalVideo_sync amc_video_mixer(

        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .HD8(HD8),
        .H1(H[1]),
        .CK1(CK1),
        .CK1n(CK1n),

        .ioctl_addr(ioctl_addr[19:0]),
        .ioctl_wr(ioctl_wr),
        .ioctl_data(ioctl_data),


        .layer_ena_dbg(layer_ena_dbg),

        .LD(LD_BUF),

        .SD(SD),
        .B1D(B1D),



        .DISP(DISP),

        .R(R),
        .G(G),
        .B(B)
    );

    assign SCR_X = X;
    assign SCR_Y = {H[8],Y[7:3],H[2:0]};
    assign PIX_CLK = CK1;
endmodule
module AthenaCore
(
    input wire RESETn,
    input wire VIDEO_RSTn,
    input wire pause_cpu,
    input wire i_clk,
    input wire [15:0] PLAYER1,
    input wire [15:0] PLAYER2,
    input wire [15:0] TRACKBALL1,
    input wire [15:0] TRACKBALL2,
    input wire [7:0] GAME,
    input wire [15:0] DSW,
    output wire player_ctrl_clk,


    input wire [7:0] hack_settings,


	input wire         [24:0] ioctl_addr,
	input wire         [7:0] ioctl_data,
	input wire               ioctl_wr,


    input wire [2:0] layer_ena_dbg,
    input wire [3:0] dbg_B1Voffset,
    input wire swap_px,


    output logic [3:0] R,
    output logic [3:0] G,
    output logic [3:0] B,
	 output logic HBLANK,
	 output logic VBLANK,
	 output logic HSYNC,
	 output logic VSYNC,
    output logic [8:0] SCR_Y,
    output logic [8:0] SCR_X,
    output logic VBL,
    output logic SYNC,
    output logic VS,
    output logic HS,
    output logic DISP,
    output logic PIX_CLK,
	 output logic CE_PIXEL,


    output wire signed [15:0] snd1,
    output wire signed [15:0] snd2,
    output wire sample
);

    logic VRD, AE, BE;
    
    logic CK0, CK0n, CK1, CK1n, LDn;
    logic HLDn;
    (* keep *) logic [8:0] H;
    (* keep *) logic [2:0] Hn;
    logic [8:0] FH;
    logic FCK;
    logic [7:0] Y;
    logic [7:0] X;
    logic [8:0] FV;
    logic VCKn;
    logic LT;
    logic VLK;
    logic VFLGn;
    logic VDG, V_C;
    logic VWE, VOE;
    logic BWA, A_B, RLA, RLB, WBA, WBB;
    logic LA, LC, LD, HD8;


    logic  [7:0] AD;
    

    logic [7:0] VD_out, VD_in;
    logic [12:0] VA;


    logic FRONT_VIDEO_CSn;
    logic SIDE_VRAM_CSn;
    logic DISC;
    logic MSB;
    logic FSX;
    logic FSY;
    logic B1SX;
    logic B1SY;
    logic COIN_COUNTERS;
    logic BACK1_VRAM_CSn;


    logic INV;
    logic INVn;
    logic B1X8;
    logic B1Y8;
    logic FX8;
    logic FY8;
    

    logic COIN;
    logic P1;
    logic P2;
    logic P1_P2;
    logic MCODE;
    logic DIP1;
    logic DIP2;

     logic clk_13p4_cen;
     logic clk_13p4;
     logic clk_13p4b_cen;
     logic clk_13p4b;
     logic clk_6p7_cen;
     logic clk_6p7b_cen;
     logic clk_3p35_cen;
     logic clk_3p35b_cen;
     logic clk_4_cen;
     logic clk_4b_cen;

    TNKIIICoreClocks_Cen amc_clk_cen(
        .i_clk(i_clk),
        .clk_13p4_cen(clk_13p4_cen),
        .clk_13p4(clk_13p4),
        .clk_13p4b_cen(clk_13p4b_cen),
        .clk_13p4b(clk_13p4b),
        .clk_6p7_cen(clk_6p7_cen),
        .clk_6p7b_cen(clk_6p7b_cen),
        .clk_3p35_cen(clk_3p35_cen),
        .clk_3p35b_cen(clk_3p35b_cen),
        .clk_4_cen(clk_4_cen),
        .clk_4b_cen(clk_4b_cen)
    );
    
    assign player_ctrl_clk = clk_3p35_cen;
	 assign CE_PIXEL = clk_6p7_cen; 

TNKIIICore_Clocks_Sync amc_clocks_sync(
    .clk(i_clk),
    .clk_13p4_cen(clk_13p4_cen),
    .clk_13p4(clk_13p4),
    .clk_13p4b_cen(clk_13p4b_cen),
    .clk_13p4b(clk_13p4b),
    .clk_6p7_cen(clk_6p7_cen),
    .clk_6p7b_cen(clk_6p7b_cen),
    .reset(VIDEO_RSTn),
    .VIDEO_RSTn(VIDEO_RSTn),
    .INVn(INVn),
    .FSX(FSX),
    .FX8(FX8),

    .hack_settings(hack_settings),
    .VD_in(VD_in),
    .VRD(VRD),
    .AE(AE),
    .BE(BE),

    .CK0(CK0),
    .CK0n(CK0n),
    .HLDn(HLDn),
    .CK1(CK1),
    .CK1n(CK1n),
    .H(H),
    .Hn(Hn),
    .FH(FH),
    .FCK(FCK),
    .Y(Y),
    .X(X),
    .FV(FV),
    .VCKn(VCKn),
    .VBL(VBL),
    .DISP(DISP),
    .SYNC(SYNC),
	 .HBLANK(HBLANK),
	 .VBLANK(VBLANK),
    .HSYNC(HSYNC),
    .VSYNC(VSYNC),
    .LT(LT),

    .VWE(VWE),
    .VOE(VOE),
    .BWA(BWA),
    .A_B(A_B),
    .RLA(RLA),
    .RLB(RLB),
    .WBA(WBA),
    .WBB(WBB),
    .VDG(VDG),
    .VLK(VLK),
    .V_C(V_C),
    .VFLGn(VFLGn),
    .HD8(HD8),
    .LC(LC),
    .LD(LD),
    .LA(LA)
	);
    logic SND_BUSY;
    logic CPUA_WR;
    logic CPUA_RD;
    logic [7:0] CPUAD;



    AthenaCore_CPU_A_B_sync cpuA_B_sync
    (

        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .pause_cpu(pause_cpu),
        .H0(H[0]),
        .Cen_p(clk_3p35_cen),
        .Cen_n(clk_3p35b_cen),
        .RESETn(VIDEO_RSTn),
        .PLAYER1(PLAYER1),
        .PLAYER2(PLAYER2),
        .TRACKBALL1(TRACKBALL1),
	    .TRACKBALL2(TRACKBALL2),
        .GAME(GAME),
        .DSW(DSW),
        .VBL(VBL),
        .BWA(BWA),
        .A_B(A_B),
        .RLA(RLA),
        .RLB(RLB),
        .WBA(WBA),
        .WBB(WBB),
        .VDG(VDG),

        .VRDn(VRD),
        .AE(AE),
        .BE(BE),
        

        .CPUAD(CPUAD),
        .CPUA_RD(CPUA_RD),
        .CPUA_WR(CPUA_WR),


        .VA(VA),

        .V_out(VD_in),
        .V_in(VD_out),
        

        .ioctl_addr(ioctl_addr[19:0]),
        .ioctl_wr(ioctl_wr),
        .ioctl_data(ioctl_data),
        

        .SND_BUSY(SND_BUSY),
        .COIN(COIN),
        .P1(P1),
        .P2(P2),
        .P1_P2(P1_P2),
        .MCODE(MCODE),
        .DIP1(DIP1),
        .DIP2(DIP2),


        .FRONT_VIDEO_CSn(FRONT_VIDEO_CSn),
        .SIDE_VRAM_CSn(SIDE_VRAM_CSn),
        .DISC(DISC),
        .MSB(MSB),
        .FSX(FSX),
        .FSY(FSY),
        .B1SX(B1SX),
        .B1SY(B1SY),
        .COIN_COUNTERS(COIN_COUNTERS),
        .BACK1_VRAM_CSn(BACK1_VRAM_CSn)
    );

    Dual_YM3526_Sound amc_snd_sync
    (
        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .pause_cpu(pause_cpu),
        .CEN_p(clk_4_cen),
        .CEN_n(clk_4b_cen),
        .RESETn(VIDEO_RSTn),
        .data_in(CPUAD),
        .ioctl_addr(ioctl_addr[19:0]),
        .ioctl_wr(ioctl_wr),
        .ioctl_data(ioctl_data),
        .MCODE(MCODE),
        .MS(SND_BUSY),
        .snd1(snd1),
        .snd2(snd2),
        .sample(sample)
    );






    logic COIN1_CNT, COIN2_CNT;
    logic SIDE_ROM_BK;
    logic [7:0] FY;


    logic HACK_INV;
    logic HACK_INVn;
    assign INV = ((hack_settings[0])) ? ~HACK_INV : HACK_INV;
    assign INVn = (hack_settings[0]) ? ~HACK_INVn : HACK_INVn;


    AthenaCore_Registers_sync athena_registers(
        .VIDEO_RSTn(VIDEO_RSTn),
        .reset(VIDEO_RSTn),

        .clk(i_clk),
        .MSB(MSB),
        .VD_in(VD_in),


        .INV(HACK_INV),
        .INVn(HACK_INVn),
        .SIDE_ROM_BK(SIDE_ROM_BK),
        .B1X8(B1X8),
        .FX8(FX8),
        .B1Y8(B1Y8),
        .FY8(FY8),










        .COIN_COUNTERS(COIN_COUNTERS),
        .COIN1_CNT(COIN1_CNT),
        .COIN2_CNT(COIN2_CNT),
        .FSY(FSY),
        .FY(FY)
    );


    logic [6:0] SD;


    logic SIDE_SELn;
    logic [7:0] side_vout;
    AthenaCore_Side_sync amc_side_sync(
        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .CK1(CK1),

        .INV(INV),
        .INVn(INVn),


        .VD_in(VD_in),
        .VD_out(side_vout),

        .ioctl_addr(ioctl_addr[19:0]),
        .ioctl_wr(ioctl_wr),
        .ioctl_data(ioctl_data),

        .V_C(V_C),

        .SIDE_VRAM_CSn(SIDE_VRAM_CSn),
        .VA(VA[10:0]),

        .VFLGn(VFLGn),
        .H8(H[8]),
        .Y(Y[7:3]),
        .X(X), 


        .VRD(VRD),
        .VDG(VDG),
        .VOE(VOE),
        .VWE(VWE),


        .VLK(VLK),
        .H2n(Hn[2]),
        .H1n(Hn[1]),
        .H0n(Hn[0]),


        .SD(SD[6:0]),


        .SIDE_BK(SIDE_ROM_BK)
    );

    logic [7:0] B1D;

    logic [7:0] back1_vout;
    TNKIIICore_Back1_sync amc_back1_sync(
        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .CK1(CK1),
        .RESET(VIDEO_RSTn),

        .INV(INV),
        .INVn(INVn),

        .VD_in(VD_in),
        .VD_out(back1_vout),


        .hack_settings(hack_settings),
        .dbg_B1Voffset(dbg_B1Voffset),
        .swap_px(swap_px),

        .ioctl_addr(ioctl_addr[19:0]),
        .ioctl_wr(ioctl_wr),
        .ioctl_data(ioctl_data),

        .B1SY(B1SY),
        .B1SX(B1SX),

        .B1Y8(B1Y8),
        .B1X8(B1X8),

        .V_C(V_C),

        .H8(H[8]),
        .Y(Y[7:3]),
        .H2(H[2]),
        .H1(H[1]),
        .H0(H[0]),
        .X(X), 
        .VA(VA),
        .BACK1_VRAM_CSn(BACK1_VRAM_CSn),
        

        .VFLGn(VFLGn),


        .VRD(VRD),
        .VDG(VDG),
        .VOE(VOE),
        .VWE(VWE),


        .CK1n(CK1n),
        .LA(LA),
        .VLK(VLK),



        .JMP_B1D7(1'b0),
        .B1_COLBK(1'b0),
        .B1D(B1D[7:0])
    );
    
    logic [7:0] FD;
    logic [8:0] FL_Y;
    logic [7:0] front_vout;
    AthenaCore_Front_sync amc_front_sync(
        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .CK1(CK1),

        .VD_in(VD_in),
        .VD_out(front_vout),

        .hack_settings(hack_settings),

        .ioctl_addr(ioctl_addr[19:0]),
        .ioctl_wr(ioctl_wr),
        .ioctl_data(ioctl_data),

        .V_C(V_C),

        .FRONT_VIDEO_CSn(FRONT_VIDEO_CSn),
        .VA(VA[10:0]),

        .VCKn(VCKn),

        .VRD(VRD),
        .VDG(VDG),
        .VOE(VOE),
        .VWE(VWE),

        .FH(FH[8:4]),
        .FV(FV),
        .LC(LC),
        .VLK(VLK),

        .FCK(FCK),

        .H3(H[3]),
        .LD(LD),
        .CK0(CK0),

        .FD(FD),
        .FL_Y(FL_Y)
    );

    logic [7:0] LD_BUF;
    logic FYocho;
    assign FYocho = FY8;
    TNKIIICore_LineBuffer_sync amc_linebuf_sync(

        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .RESETn(VIDEO_RSTn),
        .FD(FD),
        .LT(LT),
        .VCKn(VCKn),
        .CK1(CK1),
        .CK1n(CK1n),
        .CK0(CK0),
        .CK0n(CK0n),
        .FCK(FCK),
        .LD(LD),
        .FL_Y(FL_Y),
        .HLD(HLDn),

        .hack_settings(hack_settings),
        .FY8(FYocho),
        .FY(FY),
        .INVn(INVn),

        .LD_BUF(LD_BUF)
    );


        assign VD_out = ( (!VDG && !SIDE_VRAM_CSn)   ? side_vout  : (
                          (!VDG && !BACK1_VRAM_CSn)  ? back1_vout : (
                          (!VDG && !FRONT_VIDEO_CSn) ? front_vout : 8'hff )));


    TNKIIICore_FinalVideo_sync amc_video_mixer(

        .VIDEO_RSTn(VIDEO_RSTn),
        .clk(i_clk),
        .HD8(HD8),
        .H1(H[1]),
        .CK1(CK1),
        .CK1n(CK1n),

        .ioctl_addr(ioctl_addr[19:0]),
        .ioctl_wr(ioctl_wr),
        .ioctl_data(ioctl_data),


        .layer_ena_dbg(layer_ena_dbg),

        .LD(LD_BUF),

        .SD(SD),
        .B1D(B1D),



        .DISP(DISP),

        .R(R),
        .G(G),
        .B(B)
    );

    assign SCR_X = X;
    assign SCR_Y = {H[8],Y[7:3],H[2:0]};
    assign PIX_CLK = CK1;
endmodule