data/full_repos/permissive/419677538/Exercise_3/verilog_code/Exe3_part1/DigSysExe3.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/419677538/Exercise_3/verilog_code/Exe3_part1/DigSysExe3.v:9: Unsupported: Ignoring delay on this delayed statement.\n     #1 q <= 1\'b0;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Exercise_3/verilog_code/Exe3_part1/DigSysExe3.v:11: Unsupported: Ignoring delay on this delayed statement.\n     #2 q <= ~q;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Exercise_3/verilog_code/Exe3_part1/DigSysExe3.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #19 reset<=1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Exercise_3/verilog_code/Exe3_part1/DigSysExe3.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #20 reset<=~reset;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Exercise_3/verilog_code/Exe3_part1/DigSysExe3.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk <= ~clk;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Exercise_3/verilog_code/Exe3_part1/DigSysExe3.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #19 reset<=1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Exercise_3/verilog_code/Exe3_part1/DigSysExe3.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #20 reset<=~reset;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Exercise_3/verilog_code/Exe3_part1/DigSysExe3.v:64: Unsupported: Ignoring delay on this delayed statement.\n     #10 clk<=~clk;\n     ^\n%Warning-MULTITOP: data/full_repos/permissive/419677538/Exercise_3/verilog_code/Exe3_part1/DigSysExe3.v:54: Multiple top level modules\n                                                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                                          : ... Top module \'TestBenchRippleCounter\'\nmodule TestBenchRippleCounter;\n       ^~~~~~~~~~~~~~~~~~~~~~\n                                                                                                          : ... Top module \'TestBenchSynchronousCounter\'\nmodule TestBenchSynchronousCounter;\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TestBenchSynchronousCounter;
	reg clk,reset;
	wire [3:0] q;
	SynchronousCounter sc0(q,clk,reset);
	initial begin
		clk<=1'b0;
		#19 reset<=1'b1;
		#20 reset<=~reset;
	end
	always
	    #10 clk<=~clk;
endmodule
module TestBenchSynchronousCounter;

	reg clk,reset;
	wire [3:0] q;
	SynchronousCounter sc0(q,clk,reset);
	initial begin
		clk<=1'b0;
		#19 reset<=1'b1;
		#20 reset<=~reset;
	end
	always
	    #10 clk<=~clk;
endmodule