data/full_repos/permissive/518006745/src/dBounce.v
1: b'%Warning-WIDTH: data/full_repos/permissive/518006745/src/dBounce.v:22: Operator EQ expects 32 or 24 bits on the LHS, but LHS\'s VARREF \'counter\' generates 17 bits.\n                                                                     : ... In instance dBounce\n  if (counter == endcount) begin\n              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module dBounce (
		input wire i_clk, i_db, resetn,
		output wire o_db
	);
	parameter CLOCK = 50_000_000;
	parameter WINDOWSIZE = 10_000_000;
	parameter PERIOD = 20;

	parameter numpoints = 10;
	
	
	localparam endcount = WINDOWSIZE/PERIOD/numpoints;
	
	
	reg out_pin = 0;
	reg [numpoints:0] window;
	reg [$clog2(endcount):0] counter = 0;
	

	always @(posedge i_clk) begin
		if (counter == endcount) begin
			window = { window[numpoints-1:0] , i_db};
			counter = 0;
		end else begin
			counter = counter + 1;
		end
		
	end

	

	always @(posedge i_clk) begin
		if (i_db && &window) out_pin =  1'b1;
		if (i_db == 0 && ~|window) out_pin = 1'b0;

    end
    assign o_db = out_pin;
endmodule
module dBounce (
		input wire i_clk, i_db, resetn,
		output wire o_db
	);

	parameter CLOCK = 50_000_000;
	parameter WINDOWSIZE = 10_000_000;
	parameter PERIOD = 20;

	parameter numpoints = 10;
	
	
	localparam endcount = WINDOWSIZE/PERIOD/numpoints;
	
	
	reg out_pin = 0;
	reg [numpoints:0] window;
	reg [$clog2(endcount):0] counter = 0;
	

	always @(posedge i_clk) begin
		if (counter == endcount) begin
			window = { window[numpoints-1:0] , i_db};
			counter = 0;
		end else begin
			counter = counter + 1;
		end
		
	end

	

	always @(posedge i_clk) begin
		if (i_db && &window) out_pin =  1'b1;
		if (i_db == 0 && ~|window) out_pin = 1'b0;

    end
    assign o_db = out_pin;
endmodule