data/full_repos/permissive/504677412/src/pulsar.v
data/verilator_xmls/aed7e73f-c192-408d-9aef-54bb225f94d7.xml
module pulsar (
  clk,
  rst,
  pulse_out
); 
  

  parameter CLKFREQ_HZ            = 24000000;
  parameter CNTR_WIDTH            = $clog2(CLKFREQ_HZ);
  

  input  wire                       clk;
  input  wire                       rst;
  output reg                        pulse_out;
  

  

  reg  [CNTR_WIDTH-1:0]             pulse_cntr;
  wire                              pulse_gen;  
  
  

  always @(posedge clk or posedge rst) begin
    if (rst) begin
      pulse_cntr <= {CNTR_WIDTH{1'b0}};
    end else begin
      if (pulse_out) begin
        pulse_cntr <= {CNTR_WIDTH{1'b0}};
      end else begin
        pulse_cntr <= pulse_cntr + 1;
      end
    end
  end
  

  assign pulse_gen = pulse_cntr == CLKFREQ_HZ ? 1'b1 : 1'b0;
  

  always @(posedge clk) begin
    pulse_out <= pulse_gen;
  end

endmodule
module pulsar (
  clk,
  rst,
  pulse_out
);
 
  

  parameter CLKFREQ_HZ            = 24000000;
  parameter CNTR_WIDTH            = $clog2(CLKFREQ_HZ);
  

  input  wire                       clk;
  input  wire                       rst;
  output reg                        pulse_out;
  

  

  reg  [CNTR_WIDTH-1:0]             pulse_cntr;
  wire                              pulse_gen;  
  
  

  always @(posedge clk or posedge rst) begin
    if (rst) begin
      pulse_cntr <= {CNTR_WIDTH{1'b0}};
    end else begin
      if (pulse_out) begin
        pulse_cntr <= {CNTR_WIDTH{1'b0}};
      end else begin
        pulse_cntr <= pulse_cntr + 1;
      end
    end
  end
  

  assign pulse_gen = pulse_cntr == CLKFREQ_HZ ? 1'b1 : 1'b0;
  

  always @(posedge clk) begin
    pulse_out <= pulse_gen;
  end

endmodule