data/full_repos/permissive/430179659/LAB3/riscv_without_abs/tb/tb_riscv.v
1: b"%Error: data/full_repos/permissive/430179659/LAB3/riscv_without_abs/tb/tb_riscv.v:19: Cannot find file containing module: 'clk_gen'\n    clk_gen CG(  \n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/430179659/LAB3/riscv_without_abs/tb,data/full_repos/permissive/430179659/clk_gen\n             data/full_repos/permissive/430179659/LAB3/riscv_without_abs/tb,data/full_repos/permissive/430179659/clk_gen.v\n             data/full_repos/permissive/430179659/LAB3/riscv_without_abs/tb,data/full_repos/permissive/430179659/clk_gen.sv\n             clk_gen\n             clk_gen.v\n             clk_gen.sv\n             obj_dir/clk_gen\n             obj_dir/clk_gen.v\n             obj_dir/clk_gen.sv\n%Error: data/full_repos/permissive/430179659/LAB3/riscv_without_abs/tb/tb_riscv.v:24: Cannot find file containing module: 'inst_MEM'\n inst_MEM IM(\n ^~~~~~~~\n%Error: data/full_repos/permissive/430179659/LAB3/riscv_without_abs/tb/tb_riscv.v:30: Cannot find file containing module: 'data_MEM'\n data_MEM DM(\n ^~~~~~~~\n%Error: data/full_repos/permissive/430179659/LAB3/riscv_without_abs/tb/tb_riscv.v:40: Cannot find file containing module: 'riscv'\n    riscv UUT(\n    ^~~~~\n%Error: Exiting due to 4 error(s)\n"
module tb_riscv ();

    wire CLK_i;
    wire RST_n_i;

	

    wire [31:0] IM_ADDR_IN_i;
    wire [31:0] IM_DATA_OUT_i;
	

	wire [31:0] DM_ADDR_IN_i;
	wire [31:0] DM_DATA_IN_i;
    wire [31:0] DM_DATA_OUT_i;
	wire DM_WE_IN_i;
	wire DM_RE_IN_i;
    

    clk_gen CG(
		.RST_n(RST_n_i),
		.CLK(CLK_i)
	);
				
	inst_MEM IM(
		.rst_n(RST_n_i),
		.address(IM_ADDR_IN_i),
		.dout(IM_DATA_OUT_i)
	);
	
	data_MEM DM(
		.clock(CLK_i),
		.rst_n(RST_n_i),
		.din(DM_DATA_IN_i),
		.address(DM_ADDR_IN_i),
		.dout(DM_DATA_OUT_i),
		.we(DM_WE_IN_i),
		.re(DM_RE_IN_i)
	);

    riscv UUT(
		.CLK(CLK_i),
		.RST_N(RST_n_i),
	
	    .PC_OUT(IM_ADDR_IN_i),
		.IMem_IN(IM_DATA_OUT_i),
		
		.RM_OUT(DM_RE_IN_i),
		.WM_OUT(DM_WE_IN_i),
		.DM_ADD(DM_ADDR_IN_i),
		.DM_DIN(DM_DATA_IN_i),
		.DM_DOUT(DM_DATA_OUT_i)
	
	);
 
endmodule
module tb_riscv ();


    wire CLK_i;
    wire RST_n_i;

	

    wire [31:0] IM_ADDR_IN_i;
    wire [31:0] IM_DATA_OUT_i;
	

	wire [31:0] DM_ADDR_IN_i;
	wire [31:0] DM_DATA_IN_i;
    wire [31:0] DM_DATA_OUT_i;
	wire DM_WE_IN_i;
	wire DM_RE_IN_i;
    

    clk_gen CG(
		.RST_n(RST_n_i),
		.CLK(CLK_i)
	);
				
	inst_MEM IM(
		.rst_n(RST_n_i),
		.address(IM_ADDR_IN_i),
		.dout(IM_DATA_OUT_i)
	);
	
	data_MEM DM(
		.clock(CLK_i),
		.rst_n(RST_n_i),
		.din(DM_DATA_IN_i),
		.address(DM_ADDR_IN_i),
		.dout(DM_DATA_OUT_i),
		.we(DM_WE_IN_i),
		.re(DM_RE_IN_i)
	);

    riscv UUT(
		.CLK(CLK_i),
		.RST_N(RST_n_i),
	
	    .PC_OUT(IM_ADDR_IN_i),
		.IMem_IN(IM_DATA_OUT_i),
		
		.RM_OUT(DM_RE_IN_i),
		.WM_OUT(DM_WE_IN_i),
		.DM_ADD(DM_ADDR_IN_i),
		.DM_DIN(DM_DATA_IN_i),
		.DM_DOUT(DM_DATA_OUT_i)
	
	);
 
endmodule