data/full_repos/permissive/504478691/clock/divider100Hz.v
data/verilator_xmls/ab8425d5-1ae3-426d-b2f7-8f4f5e202011.xml
module divider100Hz(input I_CLK, output reg O_CLK = 0);
integer n = 1;
parameter times = 1000000;
always @(posedge I_CLK)
begin
    if (n == times / 2)
        begin
            O_CLK = ~O_CLK;
            n = 1;
        end
    else n = n + 1;
end
endmodule
module divider100Hz(input I_CLK, output reg O_CLK = 0);

integer n = 1;
parameter times = 1000000;
always @(posedge I_CLK)
begin
    if (n == times / 2)
        begin
            O_CLK = ~O_CLK;
            n = 1;
        end
    else n = n + 1;
end
endmodule