data/full_repos/permissive/487110065/MemDados.v
data/verilator_xmls/746d2faf-1b06-4a3c-a34a-e3b0dd0b0a71.xml
module MemDados (
    dados,
    endereco,
    clock,
    escrever,
    saida
);

input [31:0] dados;
input [31:0] endereco;
input clock, escrever;

output [31:0] saida;

reg [31:0] addr;
reg [31:0] memoriaD [(2**8 - 1):0];

always @(negedge clock) begin
    if (escrever) begin
        memoriaD[endereco] <= dados;
    end

    addr <= endereco;
end

assign saida = memoriaD[addr];

endmodule
module MemDados (
    dados,
    endereco,
    clock,
    escrever,
    saida
);


input [31:0] dados;
input [31:0] endereco;
input clock, escrever;

output [31:0] saida;

reg [31:0] addr;
reg [31:0] memoriaD [(2**8 - 1):0];

always @(negedge clock) begin
    if (escrever) begin
        memoriaD[endereco] <= dados;
    end

    addr <= endereco;
end

assign saida = memoriaD[addr];

endmodule