data/full_repos/permissive/520487363/EX1 - Clock and Periodic Signal Generation/PashaBarahimi/FPGA Design/UART/Register.v
1: b'%Error: Invalid Option: -\n'
module NBitRegister #(parameter N = 8) (input [N-1:0] in, input ld_en, clk, rst, output reg [N-1:0] out);
    always @(posedge clk or negedge rst) begin
        if (~rst)
            out <= {N{1'b0}};
        else if (ld_en)
            out <= in;
    end
endmodule
module NBitRegister #(parameter N = 8) (input [N-1:0] in, input ld_en, clk, rst, output reg [N-1:0] out);

    always @(posedge clk or negedge rst) begin
        if (~rst)
            out <= {N{1'b0}};
        else if (ld_en)
            out <= in;
    end
endmodule