data/full_repos/permissive/529618104/sim/uart_sim_receiver.v
data/verilator_xmls/bf7a13eb-1606-47f0-a888-51de973341ad.xml
module uart_sim_receiver
#(
  parameter BAUD_RATE  = 19200,
  parameter CLOCK_FREQ = 100000000
)
(
  input  wire       clk_i,
  input  wire       txd_i,
  output wire [7:0] data_o,
  output wire       valid_o
);


  localparam UART_BAUD_VAL = CLOCK_FREQ / BAUD_RATE;

  reg     [4:0] uart_rx_sync;
  reg           uart_rx_busy;
  reg     [8:0] uart_rx_sreg;
  integer       uart_rx_baud_cnt;
  integer       uart_rx_bitcnt;
  wire    [7:0] char = uart_rx_sreg[8:1];


  initial begin
    uart_rx_sync = 5'b11111;
    uart_rx_busy = 1'b0;
    uart_rx_sreg = 9'b000000000;
    uart_rx_baud_cnt = UART_BAUD_VAL / 2;
    uart_rx_bitcnt = 0;
  end


  always @(posedge clk_i) begin

    uart_rx_sync <= {uart_rx_sync[3:0], txd_i};

    if (!uart_rx_busy) begin
      uart_rx_busy     <= 0;
      uart_rx_baud_cnt <= UART_BAUD_VAL / 2;
      uart_rx_bitcnt   <= 9;
      if (uart_rx_sync[4:1] == 4'b1100) begin
        uart_rx_busy <= 1;
      end
    end else begin
      if (uart_rx_baud_cnt == 0) begin
        if (uart_rx_bitcnt == 1) begin
          uart_rx_baud_cnt <= UART_BAUD_VAL / 2;
        end else begin
          uart_rx_baud_cnt <= UART_BAUD_VAL;
        end

        if (uart_rx_bitcnt == 0) begin
          uart_rx_busy <= 1'b0;
          if ((char >= 32) && (char <= 127)) begin
            $write ("%c", char);
          end else if (char == 10) begin
            $display ("");
          end
        end else begin
          uart_rx_sreg   <= {uart_rx_sync[4], uart_rx_sreg[8:1]};
          uart_rx_bitcnt <= uart_rx_bitcnt - 1;
        end
      end else begin
        uart_rx_baud_cnt <= uart_rx_baud_cnt - 1;
      end
    end
  end


  assign data_o = char;
  assign valid_o = ((uart_rx_baud_cnt == 0) && (uart_rx_bitcnt == 0)) ? 1'b1 : 1'b0;

endmodule
module uart_sim_receiver
#(
  parameter BAUD_RATE  = 19200,
  parameter CLOCK_FREQ = 100000000
)
(
  input  wire       clk_i,
  input  wire       txd_i,
  output wire [7:0] data_o,
  output wire       valid_o
);



  localparam UART_BAUD_VAL = CLOCK_FREQ / BAUD_RATE;

  reg     [4:0] uart_rx_sync;
  reg           uart_rx_busy;
  reg     [8:0] uart_rx_sreg;
  integer       uart_rx_baud_cnt;
  integer       uart_rx_bitcnt;
  wire    [7:0] char = uart_rx_sreg[8:1];


  initial begin
    uart_rx_sync = 5'b11111;
    uart_rx_busy = 1'b0;
    uart_rx_sreg = 9'b000000000;
    uart_rx_baud_cnt = UART_BAUD_VAL / 2;
    uart_rx_bitcnt = 0;
  end


  always @(posedge clk_i) begin

    uart_rx_sync <= {uart_rx_sync[3:0], txd_i};

    if (!uart_rx_busy) begin
      uart_rx_busy     <= 0;
      uart_rx_baud_cnt <= UART_BAUD_VAL / 2;
      uart_rx_bitcnt   <= 9;
      if (uart_rx_sync[4:1] == 4'b1100) begin
        uart_rx_busy <= 1;
      end
    end else begin
      if (uart_rx_baud_cnt == 0) begin
        if (uart_rx_bitcnt == 1) begin
          uart_rx_baud_cnt <= UART_BAUD_VAL / 2;
        end else begin
          uart_rx_baud_cnt <= UART_BAUD_VAL;
        end

        if (uart_rx_bitcnt == 0) begin
          uart_rx_busy <= 1'b0;
          if ((char >= 32) && (char <= 127)) begin
            $write ("%c", char);
          end else if (char == 10) begin
            $display ("");
          end
        end else begin
          uart_rx_sreg   <= {uart_rx_sync[4], uart_rx_sreg[8:1]};
          uart_rx_bitcnt <= uart_rx_bitcnt - 1;
        end
      end else begin
        uart_rx_baud_cnt <= uart_rx_baud_cnt - 1;
      end
    end
  end


  assign data_o = char;
  assign valid_o = ((uart_rx_baud_cnt == 0) && (uart_rx_bitcnt == 0)) ? 1'b1 : 1'b0;

endmodule