data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_pipelining/cachelib/v_rtl/dut_OrReduction_2S_1U_1.v
data/verilator_xmls/f4119dec-d2c9-45e9-9e31-bc67d0238a0f.xml
module dut_OrReduction_2S_1U_1 (
	in1,
	out1
	);
input [1:0] in1;
output  out1;
wire  asc001;

assign asc001 = 
	(|in1);

assign out1 = asc001;
endmodule
module dut_OrReduction_2S_1U_1 (
	in1,
	out1
	);

input [1:0] in1;
output  out1;
wire  asc001;

assign asc001 = 
	(|in1);

assign out1 = asc001;
endmodule