data/full_repos/permissive/468929885/verilog/rtl _bak/user_proj_example.v
1: b'%Error: Cannot find file containing module: _bak,data/full_repos/permissive/468929885\n        ... Looked in:\n             data/full_repos/permissive/468929885/verilog/rtl/_bak,data/full_repos/permissive/468929885\n             data/full_repos/permissive/468929885/verilog/rtl/_bak,data/full_repos/permissive/468929885.v\n             data/full_repos/permissive/468929885/verilog/rtl/_bak,data/full_repos/permissive/468929885.sv\n             _bak,data/full_repos/permissive/468929885\n             _bak,data/full_repos/permissive/468929885.v\n             _bak,data/full_repos/permissive/468929885.sv\n             obj_dir/_bak,data/full_repos/permissive/468929885\n             obj_dir/_bak,data/full_repos/permissive/468929885.v\n             obj_dir/_bak,data/full_repos/permissive/468929885.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/468929885/verilog/rtl\n%Error: Cannot find file containing module: _bak/user_proj_example.v\n%Error: Exiting due to 3 error(s)\n'
module user_proj_example #(
	parameter BITS = 32
)(
`ifdef USE_POWER_PINS
	inout vccd1,
	inout vssd1,
`endif


	input wb_clk_i,
	input wb_rst_i,
	input wbs_stb_i,
	input wbs_cyc_i,
	input wbs_we_i,
	input [3:0] wbs_sel_i,
	input [31:0] wbs_dat_i,
	input [31:0] wbs_adr_i,
	output wbs_ack_o,
	output [31:0] wbs_dat_o,


	input  [127:0] la_data_in,
	output [127:0] la_data_out,
	input  [127:0] la_oenb,


	input  [`MPRJ_IO_PADS-1:0] io_in,
	output [`MPRJ_IO_PADS-1:0] io_out,
	output [`MPRJ_IO_PADS-1:0] io_oeb,


	output [2:0] irq
);

	parameter RAIL_NUM = 2;



	assign io_out = {{(`MPRJ_IO_PADS-1-BITS){1'b0}},count};

	assign io_oeb = {(`MPRJ_IO_PADS-1){1'b0}};

	wire [`MPRJ_IO_PADS-1:0] io_in;
	wire [`MPRJ_IO_PADS-1:0] io_out;
	wire [`MPRJ_IO_PADS-1:0] io_oeb;

	

	
	wire start;

	wire ack_i;
	wire ack_o;

	wire [BITS*RAIL_NUM-1 : 0] out;
	wire [BITS-1 : 0] count;



	assign irq = 3'b000;


	assign la_data_out = {{((128-1)-((1 + RAIL_NUM)*BITS)){1'b1}}, ack_o, count, out};
	



		

	assign start = la_data_in[124];
	assign ack_i = la_data_in[125];




	assign wbs_ack_o = 0;
	assign wbs_dat_o = 0;



	genvar bus_idx;
	
	generate
		for (bus_idx = 0; bus_idx < BITS ; bus_idx = bus_idx + 1)
		begin 
		
			el_sync sync
			(
				.rst(wb_rst_i),
				.clk(wb_clk_i),
				
				.in_async(out[2*bus_idx +: 2]),
				.in_ack(ack_o),
				
				.out_sync(count[bus_idx])
				
			);
			
		end
	endgenerate 

	

	
	
	el_fib#
	(
		.WIDTH(BITS)
	)
	FIB
	(
	    .rst(wb_rst_i),
	    .start(start),
	    
	    .ack_i(ack_i),
	    .ack_o(ack_o),
	    .out(out)
	    
	);
	



endmodule
module user_proj_example #(
	parameter BITS = 32
)(
`ifdef USE_POWER_PINS
	inout vccd1,
	inout vssd1,
`endif


	input wb_clk_i,
	input wb_rst_i,
	input wbs_stb_i,
	input wbs_cyc_i,
	input wbs_we_i,
	input [3:0] wbs_sel_i,
	input [31:0] wbs_dat_i,
	input [31:0] wbs_adr_i,
	output wbs_ack_o,
	output [31:0] wbs_dat_o,


	input  [127:0] la_data_in,
	output [127:0] la_data_out,
	input  [127:0] la_oenb,


	input  [`MPRJ_IO_PADS-1:0] io_in,
	output [`MPRJ_IO_PADS-1:0] io_out,
	output [`MPRJ_IO_PADS-1:0] io_oeb,


	output [2:0] irq
);


	parameter RAIL_NUM = 2;



	assign io_out = {{(`MPRJ_IO_PADS-1-BITS){1'b0}},count};

	assign io_oeb = {(`MPRJ_IO_PADS-1){1'b0}};

	wire [`MPRJ_IO_PADS-1:0] io_in;
	wire [`MPRJ_IO_PADS-1:0] io_out;
	wire [`MPRJ_IO_PADS-1:0] io_oeb;

	

	
	wire start;

	wire ack_i;
	wire ack_o;

	wire [BITS*RAIL_NUM-1 : 0] out;
	wire [BITS-1 : 0] count;



	assign irq = 3'b000;


	assign la_data_out = {{((128-1)-((1 + RAIL_NUM)*BITS)){1'b1}}, ack_o, count, out};
	



		

	assign start = la_data_in[124];
	assign ack_i = la_data_in[125];




	assign wbs_ack_o = 0;
	assign wbs_dat_o = 0;



	genvar bus_idx;
	
	generate
		for (bus_idx = 0; bus_idx < BITS ; bus_idx = bus_idx + 1)
		begin 
		
			el_sync sync
			(
				.rst(wb_rst_i),
				.clk(wb_clk_i),
				
				.in_async(out[2*bus_idx +: 2]),
				.in_ack(ack_o),
				
				.out_sync(count[bus_idx])
				
			);
			
		end
	endgenerate 

	

	
	
	el_fib#
	(
		.WIDTH(BITS)
	)
	FIB
	(
	    .rst(wb_rst_i),
	    .start(start),
	    
	    .ack_i(ack_i),
	    .ack_o(ack_o),
	    .out(out)
	    
	);
	



endmodule