data/full_repos/permissive/491135068/DFF1.v
data/verilator_xmls/0a94e4ed-4040-48fe-9d9c-4cc50d77205e.xml
module DFF1(DFFIN1, DFFOUT1, clk);
    input DFFIN1, clk;
    output reg DFFOUT1;

    always @(posedge clk) begin
        DFFOUT1 = DFFIN1;
    end
endmodule
module DFF1(DFFIN1, DFFOUT1, clk);

    input DFFIN1, clk;
    output reg DFFOUT1;

    always @(posedge clk) begin
        DFFOUT1 = DFFIN1;
    end
endmodule