data/full_repos/permissive/462122681/register_64.v
data/verilator_xmls/89e947a0-f71d-4cc3-adba-837b6794d64f.xml
module register_64 #(parameter init = 0)(
	input wire clk, 
	input wire rst,
	input wire enable,
	input wire [63:0] d,
	output reg [31:0] high,
	output reg [31:0] low
);


	initial high = init;
	initial low = init;
	always@(posedge clk) 
	begin
		if (rst) begin
			high = 32'b0;
			low = 32'b0;
		end
		else if(enable) begin
			high[31:0] = d[63:32];
			low[31:0] = d[31:0];
		end 
	end
endmodule
module register_64 #(parameter init = 0)(
	input wire clk, 
	input wire rst,
	input wire enable,
	input wire [63:0] d,
	output reg [31:0] high,
	output reg [31:0] low
);



	initial high = init;
	initial low = init;
	always@(posedge clk) 
	begin
		if (rst) begin
			high = 32'b0;
			low = 32'b0;
		end
		else if(enable) begin
			high[31:0] = d[63:32];
			low[31:0] = d[31:0];
		end 
	end
endmodule