data/full_repos/permissive/479923049/shifter_tb.v
1: b'%Error: data/full_repos/permissive/479923049/shifter_tb.v:10: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n    task checker;\n         ^~~~~~~\n%Error: data/full_repos/permissive/479923049/shifter_tb.v:10: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    task checker;\n                ^\n%Error: data/full_repos/permissive/479923049/shifter_tb.v:12: syntax error, unexpected begin\n        begin \n        ^~~~~\n%Error: data/full_repos/permissive/479923049/shifter_tb.v:23: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n        checker(16\'b0000_0000_0000_1111);  \n        ^~~~~~~\n%Error: data/full_repos/permissive/479923049/shifter_tb.v:26: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n        checker(16\'b0000_0000_0001_1110);  \n        ^~~~~~~\n%Error: data/full_repos/permissive/479923049/shifter_tb.v:29: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n        checker(16\'b0000_0000_0000_0111);  \n        ^~~~~~~\n%Error: data/full_repos/permissive/479923049/shifter_tb.v:32: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n        checker(16\'b1100_0000_0000_0111);  \n        ^~~~~~~\n%Error: data/full_repos/permissive/479923049/shifter_tb.v:34: syntax error, unexpected $display\n        if( ~err ) $display("PASSED");\n                   ^~~~~~~~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module shifter_tb();
    reg [15:0] in;
    reg [1:0] shift;

    wire [15:0] sout;
    reg err;

    shifter DUT (in,shift,sout);

    task checker;
        input [15:0] expected_sout;
        begin 
            if( sout !== expected_sout ) begin
            $display("ERROR ** out is %b, expected %b", sout, expected_sout);
            err = 1'b1;
            end
        end
    endtask

    initial begin 
        err = 0;
        in = 16'b0000_0000_0000_1111; shift = 00; #10;
        checker(16'b0000_0000_0000_1111);

        in = 16'b0000_0000_0000_1111; shift = 01; #10;
        checker(16'b0000_0000_0001_1110);

        in = 16'b0000_0000_0000_1111; shift = 10; #10;
        checker(16'b0000_0000_0000_0111);

        in = 16'b1000_0000_0000_1110; shift = 11; #10;
        checker(16'b1100_0000_0000_0111);

        if( ~err ) $display("PASSED");
        else $display("FAILED");

        
    end
endmodule
module shifter_tb();

    reg [15:0] in;
    reg [1:0] shift;

    wire [15:0] sout;
    reg err;

    shifter DUT (in,shift,sout);

    task checker;
        input [15:0] expected_sout;
        begin 
            if( sout !== expected_sout ) begin
            $display("ERROR ** out is %b, expected %b", sout, expected_sout);
            err = 1'b1;
            end
        end
    endtask

    initial begin 
        err = 0;
        in = 16'b0000_0000_0000_1111; shift = 00; #10;
        checker(16'b0000_0000_0000_1111);

        in = 16'b0000_0000_0000_1111; shift = 01; #10;
        checker(16'b0000_0000_0001_1110);

        in = 16'b0000_0000_0000_1111; shift = 10; #10;
        checker(16'b0000_0000_0000_0111);

        in = 16'b1000_0000_0000_1110; shift = 11; #10;
        checker(16'b1100_0000_0000_0111);

        if( ~err ) $display("PASSED");
        else $display("FAILED");

        
    end
endmodule