data/full_repos/permissive/42434302/ivltests/pr298.v
1: b'%Error: data/full_repos/permissive/42434302/ivltests/pr298.v:37: syntax error, unexpected \'(\', expecting IDENTIFIER\np(Q, D);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr298.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #1 $display(QQ, Q);\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr298.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr298.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #15\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr298.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr298.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #25\n    ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n'
module m;

reg D;
wire Q;
reg A;
wire QQ;

p(Q, D);
buf(QQ, Q);

initial
  begin


    #1 $display(QQ, Q);
    #10
    D = 0;
    #15
    $display(QQ, Q);
    #20
    D = 1;
    #25
    $display(QQ, Q);
    $finish;
  end
endmodule
module m;


reg D;
wire Q;
reg A;
wire QQ;

p(Q, D);
buf(QQ, Q);

initial
  begin


    #1 $display(QQ, Q);
    #10
    D = 0;
    #15
    $display(QQ, Q);
    #20
    D = 1;
    #25
    $display(QQ, Q);
    $finish;
  end
endmodule