data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_Front1.sv
1: b"%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_Front1.sv:52: Cannot find file containing module: 'ttl_74139_nodly'\n    ttl_74139_nodly b2_cpu_pcb(.Enable_bar(FRONT1_VIDEO_CSn), .A_2D(VA[1:0]), .Y_2D({F1B3, F1B2, F1B1, F1B0}));\n    ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/520811519/rtl/front,data/full_repos/permissive/520811519/ttl_74139_nodly\n             data/full_repos/permissive/520811519/rtl/front,data/full_repos/permissive/520811519/ttl_74139_nodly.v\n             data/full_repos/permissive/520811519/rtl/front,data/full_repos/permissive/520811519/ttl_74139_nodly.sv\n             ttl_74139_nodly\n             ttl_74139_nodly.v\n             ttl_74139_nodly.sv\n             obj_dir/ttl_74139_nodly\n             obj_dir/ttl_74139_nodly.v\n             obj_dir/ttl_74139_nodly.sv\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_Front1.sv:74: Cannot find file containing module: 'ttl_74157'\n    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) K6 (.Enable_bar(1'b0), .Select(V_C), .A_2D({F1B3,VCKn,F1B2,VCKn,F1B1,VCKn,F1B0,VCKn}), .Y({B3CSn, B2CSn, B1CSn, B0CSn}));\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_Front1.sv:76: Cannot find file containing module: 'ttl_74157'\n    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) J6 (.Enable_bar(1'b0), .Select(V_C), .A_2D({1'b0,1'b0, VA[11],1'b1,  VA[10],1'b0,  VA[9],1'b0}), .Y(A[10:7]));\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_Front1.sv:78: Cannot find file containing module: 'ttl_74157'\n    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) K8 (.Enable_bar(1'b0), .Select(V_C), .A_2D({VA[8],1'b0,VA[7],FH[4],VA[6],FH[3],VA[5],FH[2]}), .Y(A[6:3]));\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_Front1.sv:81: Cannot find file containing module: 'ttl_74157'\n    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) J8 (.Enable_bar(1'b0), .Select(V_C), .A_2D({VA[4],FH[1],VA[3],FH[0],VA[2],H3,1'b1,1'b1}), .Y({A[2:0],j8_dum}));\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_Front1.sv:90: Cannot find file containing module: 'DFF_pseudoAsyncClrPre'\n DFF_pseudoAsyncClrPre #(.W(1)) P7 (\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_Front1.sv:109: Cannot find file containing module: 'SRAM_dual_sync'\n    SRAM_dual_sync #(.ADDR_WIDTH(10)) h2_byte0\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_Front1.sv:125: Cannot find file containing module: 'SRAM_dual_sync'\n    SRAM_dual_sync #(.ADDR_WIDTH(10)) h3_byte1\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_Front1.sv:142: Cannot find file containing module: 'SRAM_dual_sync'\n    SRAM_dual_sync #(.ADDR_WIDTH(10)) h5_byte2\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_Front1.sv:158: Cannot find file containing module: 'SRAM_dual_sync'\n    SRAM_dual_sync #(.ADDR_WIDTH(10)) h6_byte3\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_Front1.sv:187: Cannot find file containing module: 'ttl_74273_sync'\n    ttl_74273_sync g2(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(VLK), .D(Dreg0), .Q(G2_Q));\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_Front1.sv:190: Cannot find file containing module: 'ttl_74273_sync'\n    ttl_74273_sync g3(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(VLK), .D((!VCKn ? Dreg1 : 8'hff)), .Q(Tile_num));\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_Front1.sv:193: Cannot find file containing module: 'ttl_74273_sync'\n    ttl_74273_sync g4(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(VLK), .D(Dreg2), .Q(Y_offset));\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_Front1.sv:196: Cannot find file containing module: 'ttl_74273_sync'\n    ttl_74273_sync g5(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(VLK), .D((!VCKn ? Dreg3 : 8'hff)), .Q(C6_Q));\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_Front1.sv:226: Cannot find file containing module: 'ttl_74273_sync'\n ttl_74273_sync C5(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(F1CK), .D({p7reg,C6_Q[7:5],C6_Q[3:0]}), .Q({f1d7_8reg,FL_1Y[8],Spr_bank,Spr_color_bank}));\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_Front1.sv:228: Cannot find file containing module: 'ttl_74273_sync'\n   ttl_74273_sync D5(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(F1CK), .D(Y_offset), .Q(FL_1Y[7:0]));\n   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_Front1.sv:231: Cannot find file containing module: 'ttl_74273_sync'\n   ttl_74273_sync G5(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(F1CK), .D(Tile_num), .Q(G5_Q));\n   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_Front1.sv:255: Cannot find file containing module: 'ttl_74283_nodly'\n    ttl_74283_nodly e5 (.A(F1V[7:4]), .B(X_offset[7:4]), .C_in(e4_cout),  .Sum(e5_sum), .C_out(e5_cout));\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_Front1.sv:258: Cannot find file containing module: 'ttl_74283_nodly'\n    ttl_74283_nodly e4 (.A(F1V[3:0]), .B(X_offset[3:0]), .C_in(1'b1), .Sum(e4_sum), .C_out(e4_cout));\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_Front1.sv:278: Cannot find file containing module: 'ttl_74174_sync'\n    ttl_74174_sync L5\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_Front1.sv:290: Cannot find file containing module: 'ttl_74174_sync'\n    ttl_74174_sync B5\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_Front1.sv:306: Cannot find file containing module: 'eprom_32K'\n    eprom_32K P8_3D\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_Front1.sv:321: Cannot find file containing module: 'eprom_32K'\n    eprom_32K P9_3F\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/front/IkariWarriorsCore_Front1.sv:335: Cannot find file containing module: 'eprom_32K'\n    eprom_32K P10_3H\n    ^~~~~~~~~\n%Error: Exiting due to 24 error(s)\n"
module IkariWarriorsCore_Front1(
    input  wire VIDEO_RSTn,
    input wire clk,
    input wire CK1,

    input wire V_C ,

    input wire FRONT1_VIDEO_CSn,
    input wire [11:0] VA,
    input wire [7:0] VD_in,
    output logic [7:0] VD_out,

	input wire         [24:0] ioctl_addr,
	input wire         [7:0] ioctl_data,
	input wire               ioctl_wr,

    input wire VCKn ,

    input wire VRD,
    input wire VDG,
    input wire VOE,
    input wire VWE,

    input wire [4:0] FH ,
    input wire [8:0] F1V ,
	input wire [5:0] FN ,
    input wire LC,
    input wire VLK ,
    input wire F1CK ,
    input wire H3 ,
    input wire LD,
    input wire CK0,

    output logic [7:0] F1D ,
	output logic [8:0] SPR_1Y ,
    output logic [8:0] SPR_1X ,
    output logic [8:0] FL_1Y 
);
    logic [7:0] D0_in, D1_in, D2_in, D3_in ;
    logic [7:0] Q0, Q1, Q2, Q3;
    logic [7:0] D0_out, D1_out, D2_out, D3_out;
    logic [7:0] Dreg0, Dreg1, Dreg2, Dreg3 ;

    logic F1B3, F1B2, F1B1, F1B0;
    ttl_74139_nodly b2_cpu_pcb(.Enable_bar(FRONT1_VIDEO_CSn), .A_2D(VA[1:0]), .Y_2D({F1B3, F1B2, F1B1, F1B0}));
    

    logic F2_EN;
    logic F3_EN;
    logic F4_EN;
    logic F5_EN;

    assign F2_EN =~(F1B0 | VDG);
    assign F3_EN =~(F1B1 | VDG);
    assign F4_EN =~(F1B2 | VDG);
    assign F5_EN =~(F1B3 | VDG);

    assign D0_in = (F2_EN && VRD) ? VD_in : 8'hFF;
    assign D1_in = (F3_EN && VRD) ? VD_in : 8'hFF;
    assign D2_in = (F4_EN && VRD) ? VD_in : 8'hFF;
    assign D3_in = (F5_EN && VRD) ? VD_in : 8'hFF;



    logic [10:0] A;
    logic B3CSn, B2CSn, B1CSn, B0CSn;
    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) K6 (.Enable_bar(1'b0), .Select(V_C), .A_2D({F1B3,VCKn,F1B2,VCKn,F1B1,VCKn,F1B0,VCKn}), .Y({B3CSn, B2CSn, B1CSn, B0CSn}));

    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) J6 (.Enable_bar(1'b0), .Select(V_C), .A_2D({1'b0,1'b0, VA[11],1'b1,  VA[10],1'b0,  VA[9],1'b0}), .Y(A[10:7]));

    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) K8 (.Enable_bar(1'b0), .Select(V_C), .A_2D({VA[8],1'b0,VA[7],FH[4],VA[6],FH[3],VA[5],FH[2]}), .Y(A[6:3]));
	
	logic j8_dum;
    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) J8 (.Enable_bar(1'b0), .Select(V_C), .A_2D({VA[4],FH[1],VA[3],FH[0],VA[2],H3,1'b1,1'b1}), .Y({A[2:0],j8_dum}));




	logic FHltFN ;
	assign FHltFN = ({FH[4:0],H3} < FN[5:0]) ? 1'b1: 1'b0;

	logic p7reg;
	DFF_pseudoAsyncClrPre #(.W(1)) P7 (
        .clk(clk),
        .rst(1'b0),
        .din(FHltFN),
        .q(p7reg),
        .qn(),
        .set(1'b0),
        .clr(1'b0),
        .cen(VLK)
    );
	








    SRAM_dual_sync #(.ADDR_WIDTH(10)) h2_byte0
    (
        .ADDR0({VA[11:2]}), 
        .clk0(clk), 
        .cen0(~F1B0), 
        .we0(~VWE), 
        .DATA0(D0_in), 
        .Q0(Q0),
        .ADDR1({4'b1000,FH[4:0],H3}), 
        .clk1(clk), 
        .cen1(~VCKn), 
        .we1(1'b0), 
        .DATA1(8'hff),
        .Q1(Dreg0)
    );

    SRAM_dual_sync #(.ADDR_WIDTH(10)) h3_byte1
    (
        .ADDR0({VA[11:2]}), 
        .clk0(clk), 
        .cen0(~F1B1), 
        .we0(~VWE), 
        .DATA0(D1_in), 
        .Q0(Q1),
        .ADDR1({4'b1000,FH[4:0],H3}), 
        .clk1(clk), 
        .cen1(~VCKn), 
        .we1(1'b0), 
        .DATA1(8'hff),
        .Q1(Dreg1)
    );


    SRAM_dual_sync #(.ADDR_WIDTH(10)) h5_byte2
    (
        .ADDR0({VA[11:2]}), 
        .clk0(clk), 
        .cen0(~F1B2), 
        .we0(~VWE), 
        .DATA0(D2_in), 
        .Q0(Q2),
        .ADDR1({4'b1000,FH[4:0],H3}), 
        .clk1(clk), 
        .cen1(~VCKn), 
        .we1(1'b0), 
        .DATA1(8'hff),
        .Q1(Dreg2)
    );

    SRAM_dual_sync #(.ADDR_WIDTH(10)) h6_byte3
    (
        .ADDR0({VA[11:2]}), 
        .clk0(clk), 
        .cen0(~F1B3), 
        .we0(~VWE), 
        .DATA0(D3_in), 
        .Q0(Q3),
        .ADDR1({4'b1000,FH[4:0],H3}), 
        .clk1(clk), 
        .cen1(~VCKn), 
        .we1(1'b0), 
        .DATA1(8'hff),
        .Q1(Dreg3)
    );

    assign D0_out = (!VOE && !F1B0) ? Q0 : 8'hff;
    assign D1_out = (!VOE && !F1B1) ? Q1 : 8'hff;
    assign D2_out = (!VOE && !F1B2) ? Q2 : 8'hff;
    assign D3_out = (!VOE && !F1B3) ? Q3 : 8'hff; 

    assign VD_out = ( (!VRD && F2_EN) ? D0_out : (
                      (!VRD && F3_EN) ? D1_out : (
                      (!VRD && F4_EN) ? D2_out : (
                      (!VRD && F5_EN) ? D3_out : 8'hff
                    ))));

    logic [7:0] G2_Q;

    ttl_74273_sync g2(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(VLK), .D(Dreg0), .Q(G2_Q));
    logic [7:0] Tile_num;

    ttl_74273_sync g3(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(VLK), .D((!VCKn ? Dreg1 : 8'hff)), .Q(Tile_num));
    logic [7:0] Y_offset;

    ttl_74273_sync g4(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(VLK), .D(Dreg2), .Q(Y_offset));
    logic [7:0] C6_Q;

    ttl_74273_sync g5(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(VLK), .D((!VCKn ? Dreg3 : 8'hff)), .Q(C6_Q));

	assign SPR_1Y[8] = C6_Q[7];
	assign SPR_1Y[7:0] = Y_offset;
    
    logic [3:0] Spr_color_bank;
    logic X_offset_MSB;
    logic [1:0] Spr_bank;
    logic Spr_XFlip;
    logic Y_offset_MSB;




    assign  X_offset_MSB = ~C6_Q[4];


    logic [7:0] X_offset;
    genvar i;
    generate
        for(i=0; i<8; i++) begin : x_offset_gen
            assign X_offset[i] = ~G2_Q[i];
        end
    endgenerate

    assign SPR_1X[7:0] = X_offset;
    assign SPR_1X[8]   = X_offset_MSB;


	logic f1d7_8reg;
	ttl_74273_sync C5(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(F1CK), .D({p7reg,C6_Q[7:5],C6_Q[3:0]}), .Q({f1d7_8reg,FL_1Y[8],Spr_bank,Spr_color_bank}));

   ttl_74273_sync D5(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(F1CK), .D(Y_offset), .Q(FL_1Y[7:0]));

   logic [7:0] G5_Q;
   ttl_74273_sync G5(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(F1CK), .D(Tile_num), .Q(G5_Q));


	 logic e5_cout;
	 logic [3:0] e5_sum;



    logic e7_C;

    logic X8OFFr, F1V8r, E5COUTr;
    logic [3:0] E5SUMr, E4SUMr;

    always @(posedge clk) begin
        X8OFFr  <= X_offset_MSB;
        F1V8r    <= F1V[8];
        E5COUTr <= e5_cout;
        E5SUMr  <= e5_sum;
        E4SUMr  <= e4_sum;
    end

    assign e7_C = F1V8r ^ X8OFFr ^ E5COUTr;

    logic e4_cout;
    ttl_74283_nodly e5 (.A(F1V[7:4]), .B(X_offset[7:4]), .C_in(e4_cout),  .Sum(e5_sum), .C_out(e5_cout));

    logic [3:0] e4_sum;
    ttl_74283_nodly e4 (.A(F1V[3:0]), .B(X_offset[3:0]), .C_in(1'b1), .Sum(e4_sum), .C_out(e4_cout));









    logic e6_B;
    assign e6_B = &E5SUMr;
    
    logic e8_C;
    assign e8_C = ~(e7_C & e6_B);

    logic [4:0] L5_Q;


    logic l5_dum;
    ttl_74174_sync L5
    (
        .Reset_n(VIDEO_RSTn),
        .Clk(clk),
        .Cen(F1CK),
        .Clr_n(1'b1),
        .D({1'b1,e8_C,E4SUMr}),
        .Q({l5_dum,L5_Q})
    );

    logic B5_dum;

    ttl_74174_sync B5
    (
        .Reset_n(VIDEO_RSTn),
        .Clk(clk),
        .Cen(LC),
        .Clr_n(1'b1),
        .D({f1d7_8reg,Spr_color_bank,1'b1}),
        .Q({F1D[7:3],B5_dum})
    );


    wire P8_3D_cs = (ioctl_addr >= 25'h60_000) & (ioctl_addr < 25'h68_000);
	wire P9_3F_cs  = (ioctl_addr >= 25'h70_000) & (ioctl_addr < 25'h78_000); 
	wire P10_3H_cs  = (ioctl_addr >= 25'h80_000) & (ioctl_addr < 25'h88_000);

    logic [7:0] P8_D, P8_Dout;
    eprom_32K P8_3D
    (
        .ADDR({Spr_bank,G5_Q,L5_Q[3:0],F1CK}),
        .CLK(clk),
        .DATA(P8_Dout),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data),
        .CS_DL(P8_3D_cs),
        .WR(ioctl_wr)
    );

    assign P8_D = (!L5_Q[4]) ? P8_Dout : 8'hFF;

    logic [7:0] P9_D, P9_Dout;
    eprom_32K P9_3F
    (
        .ADDR({Spr_bank,G5_Q,L5_Q[3:0],F1CK}),
        .CLK(clk),
        .DATA(P9_Dout),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data),
        .CS_DL(P9_3F_cs),
        .WR(ioctl_wr)
    );
    assign P9_D = (!L5_Q[4]) ? P9_Dout : 8'hFF;

    logic [7:0] P10_D,P10_Dout;
    eprom_32K P10_3H
    (
        .ADDR({Spr_bank,G5_Q,L5_Q[3:0],F1CK}),
        .CLK(clk),
        .DATA(P10_Dout),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data),
        .CS_DL(P10_3H_cs),
        .WR(ioctl_wr)
    );
    assign P10_D = (!L5_Q[4]) ? P10_Dout : 8'hFF;





    PLSO_shift g10 (.RESETn(VIDEO_RSTn), .CLK(clk), .CEN(~CK0), .LOADn(LD), .SI(1'b1), .D(P8_D), .SO(F1D[0]));
    PLSO_shift g9  (.RESETn(VIDEO_RSTn), .CLK(clk), .CEN(~CK0), .LOADn(LD), .SI(1'b1), .D(P9_D),  .SO(F1D[1]));
    PLSO_shift g8  (.RESETn(VIDEO_RSTn), .CLK(clk), .CEN(~CK0), .LOADn(LD), .SI(1'b1), .D(P10_D),  .SO(F1D[2]));
endmodule
module IkariWarriorsCore_Front1(
    input  wire VIDEO_RSTn,
    input wire clk,
    input wire CK1,

    input wire V_C ,

    input wire FRONT1_VIDEO_CSn,
    input wire [11:0] VA,
    input wire [7:0] VD_in,
    output logic [7:0] VD_out,

	input wire         [24:0] ioctl_addr,
	input wire         [7:0] ioctl_data,
	input wire               ioctl_wr,

    input wire VCKn ,

    input wire VRD,
    input wire VDG,
    input wire VOE,
    input wire VWE,

    input wire [4:0] FH ,
    input wire [8:0] F1V ,
	input wire [5:0] FN ,
    input wire LC,
    input wire VLK ,
    input wire F1CK ,
    input wire H3 ,
    input wire LD,
    input wire CK0,

    output logic [7:0] F1D ,
	output logic [8:0] SPR_1Y ,
    output logic [8:0] SPR_1X ,
    output logic [8:0] FL_1Y 
);

    logic [7:0] D0_in, D1_in, D2_in, D3_in ;
    logic [7:0] Q0, Q1, Q2, Q3;
    logic [7:0] D0_out, D1_out, D2_out, D3_out;
    logic [7:0] Dreg0, Dreg1, Dreg2, Dreg3 ;

    logic F1B3, F1B2, F1B1, F1B0;
    ttl_74139_nodly b2_cpu_pcb(.Enable_bar(FRONT1_VIDEO_CSn), .A_2D(VA[1:0]), .Y_2D({F1B3, F1B2, F1B1, F1B0}));
    

    logic F2_EN;
    logic F3_EN;
    logic F4_EN;
    logic F5_EN;

    assign F2_EN =~(F1B0 | VDG);
    assign F3_EN =~(F1B1 | VDG);
    assign F4_EN =~(F1B2 | VDG);
    assign F5_EN =~(F1B3 | VDG);

    assign D0_in = (F2_EN && VRD) ? VD_in : 8'hFF;
    assign D1_in = (F3_EN && VRD) ? VD_in : 8'hFF;
    assign D2_in = (F4_EN && VRD) ? VD_in : 8'hFF;
    assign D3_in = (F5_EN && VRD) ? VD_in : 8'hFF;



    logic [10:0] A;
    logic B3CSn, B2CSn, B1CSn, B0CSn;
    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) K6 (.Enable_bar(1'b0), .Select(V_C), .A_2D({F1B3,VCKn,F1B2,VCKn,F1B1,VCKn,F1B0,VCKn}), .Y({B3CSn, B2CSn, B1CSn, B0CSn}));

    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) J6 (.Enable_bar(1'b0), .Select(V_C), .A_2D({1'b0,1'b0, VA[11],1'b1,  VA[10],1'b0,  VA[9],1'b0}), .Y(A[10:7]));

    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) K8 (.Enable_bar(1'b0), .Select(V_C), .A_2D({VA[8],1'b0,VA[7],FH[4],VA[6],FH[3],VA[5],FH[2]}), .Y(A[6:3]));
	
	logic j8_dum;
    ttl_74157 #(.DELAY_RISE(0), .DELAY_FALL(0)) J8 (.Enable_bar(1'b0), .Select(V_C), .A_2D({VA[4],FH[1],VA[3],FH[0],VA[2],H3,1'b1,1'b1}), .Y({A[2:0],j8_dum}));




	logic FHltFN ;
	assign FHltFN = ({FH[4:0],H3} < FN[5:0]) ? 1'b1: 1'b0;

	logic p7reg;
	DFF_pseudoAsyncClrPre #(.W(1)) P7 (
        .clk(clk),
        .rst(1'b0),
        .din(FHltFN),
        .q(p7reg),
        .qn(),
        .set(1'b0),
        .clr(1'b0),
        .cen(VLK)
    );
	








    SRAM_dual_sync #(.ADDR_WIDTH(10)) h2_byte0
    (
        .ADDR0({VA[11:2]}), 
        .clk0(clk), 
        .cen0(~F1B0), 
        .we0(~VWE), 
        .DATA0(D0_in), 
        .Q0(Q0),
        .ADDR1({4'b1000,FH[4:0],H3}), 
        .clk1(clk), 
        .cen1(~VCKn), 
        .we1(1'b0), 
        .DATA1(8'hff),
        .Q1(Dreg0)
    );

    SRAM_dual_sync #(.ADDR_WIDTH(10)) h3_byte1
    (
        .ADDR0({VA[11:2]}), 
        .clk0(clk), 
        .cen0(~F1B1), 
        .we0(~VWE), 
        .DATA0(D1_in), 
        .Q0(Q1),
        .ADDR1({4'b1000,FH[4:0],H3}), 
        .clk1(clk), 
        .cen1(~VCKn), 
        .we1(1'b0), 
        .DATA1(8'hff),
        .Q1(Dreg1)
    );


    SRAM_dual_sync #(.ADDR_WIDTH(10)) h5_byte2
    (
        .ADDR0({VA[11:2]}), 
        .clk0(clk), 
        .cen0(~F1B2), 
        .we0(~VWE), 
        .DATA0(D2_in), 
        .Q0(Q2),
        .ADDR1({4'b1000,FH[4:0],H3}), 
        .clk1(clk), 
        .cen1(~VCKn), 
        .we1(1'b0), 
        .DATA1(8'hff),
        .Q1(Dreg2)
    );

    SRAM_dual_sync #(.ADDR_WIDTH(10)) h6_byte3
    (
        .ADDR0({VA[11:2]}), 
        .clk0(clk), 
        .cen0(~F1B3), 
        .we0(~VWE), 
        .DATA0(D3_in), 
        .Q0(Q3),
        .ADDR1({4'b1000,FH[4:0],H3}), 
        .clk1(clk), 
        .cen1(~VCKn), 
        .we1(1'b0), 
        .DATA1(8'hff),
        .Q1(Dreg3)
    );

    assign D0_out = (!VOE && !F1B0) ? Q0 : 8'hff;
    assign D1_out = (!VOE && !F1B1) ? Q1 : 8'hff;
    assign D2_out = (!VOE && !F1B2) ? Q2 : 8'hff;
    assign D3_out = (!VOE && !F1B3) ? Q3 : 8'hff; 

    assign VD_out = ( (!VRD && F2_EN) ? D0_out : (
                      (!VRD && F3_EN) ? D1_out : (
                      (!VRD && F4_EN) ? D2_out : (
                      (!VRD && F5_EN) ? D3_out : 8'hff
                    ))));

    logic [7:0] G2_Q;

    ttl_74273_sync g2(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(VLK), .D(Dreg0), .Q(G2_Q));
    logic [7:0] Tile_num;

    ttl_74273_sync g3(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(VLK), .D((!VCKn ? Dreg1 : 8'hff)), .Q(Tile_num));
    logic [7:0] Y_offset;

    ttl_74273_sync g4(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(VLK), .D(Dreg2), .Q(Y_offset));
    logic [7:0] C6_Q;

    ttl_74273_sync g5(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(VLK), .D((!VCKn ? Dreg3 : 8'hff)), .Q(C6_Q));

	assign SPR_1Y[8] = C6_Q[7];
	assign SPR_1Y[7:0] = Y_offset;
    
    logic [3:0] Spr_color_bank;
    logic X_offset_MSB;
    logic [1:0] Spr_bank;
    logic Spr_XFlip;
    logic Y_offset_MSB;




    assign  X_offset_MSB = ~C6_Q[4];


    logic [7:0] X_offset;
    genvar i;
    generate
        for(i=0; i<8; i++) begin : x_offset_gen
            assign X_offset[i] = ~G2_Q[i];
        end
    endgenerate

    assign SPR_1X[7:0] = X_offset;
    assign SPR_1X[8]   = X_offset_MSB;


	logic f1d7_8reg;
	ttl_74273_sync C5(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(F1CK), .D({p7reg,C6_Q[7:5],C6_Q[3:0]}), .Q({f1d7_8reg,FL_1Y[8],Spr_bank,Spr_color_bank}));

   ttl_74273_sync D5(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(F1CK), .D(Y_offset), .Q(FL_1Y[7:0]));

   logic [7:0] G5_Q;
   ttl_74273_sync G5(.RESETn(VIDEO_RSTn), .CLRn(1'b1), .Clk(clk), .Cen(F1CK), .D(Tile_num), .Q(G5_Q));


	 logic e5_cout;
	 logic [3:0] e5_sum;



    logic e7_C;

    logic X8OFFr, F1V8r, E5COUTr;
    logic [3:0] E5SUMr, E4SUMr;

    always @(posedge clk) begin
        X8OFFr  <= X_offset_MSB;
        F1V8r    <= F1V[8];
        E5COUTr <= e5_cout;
        E5SUMr  <= e5_sum;
        E4SUMr  <= e4_sum;
    end

    assign e7_C = F1V8r ^ X8OFFr ^ E5COUTr;

    logic e4_cout;
    ttl_74283_nodly e5 (.A(F1V[7:4]), .B(X_offset[7:4]), .C_in(e4_cout),  .Sum(e5_sum), .C_out(e5_cout));

    logic [3:0] e4_sum;
    ttl_74283_nodly e4 (.A(F1V[3:0]), .B(X_offset[3:0]), .C_in(1'b1), .Sum(e4_sum), .C_out(e4_cout));









    logic e6_B;
    assign e6_B = &E5SUMr;
    
    logic e8_C;
    assign e8_C = ~(e7_C & e6_B);

    logic [4:0] L5_Q;


    logic l5_dum;
    ttl_74174_sync L5
    (
        .Reset_n(VIDEO_RSTn),
        .Clk(clk),
        .Cen(F1CK),
        .Clr_n(1'b1),
        .D({1'b1,e8_C,E4SUMr}),
        .Q({l5_dum,L5_Q})
    );

    logic B5_dum;

    ttl_74174_sync B5
    (
        .Reset_n(VIDEO_RSTn),
        .Clk(clk),
        .Cen(LC),
        .Clr_n(1'b1),
        .D({f1d7_8reg,Spr_color_bank,1'b1}),
        .Q({F1D[7:3],B5_dum})
    );


    wire P8_3D_cs = (ioctl_addr >= 25'h60_000) & (ioctl_addr < 25'h68_000);
	wire P9_3F_cs  = (ioctl_addr >= 25'h70_000) & (ioctl_addr < 25'h78_000); 
	wire P10_3H_cs  = (ioctl_addr >= 25'h80_000) & (ioctl_addr < 25'h88_000);

    logic [7:0] P8_D, P8_Dout;
    eprom_32K P8_3D
    (
        .ADDR({Spr_bank,G5_Q,L5_Q[3:0],F1CK}),
        .CLK(clk),
        .DATA(P8_Dout),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data),
        .CS_DL(P8_3D_cs),
        .WR(ioctl_wr)
    );

    assign P8_D = (!L5_Q[4]) ? P8_Dout : 8'hFF;

    logic [7:0] P9_D, P9_Dout;
    eprom_32K P9_3F
    (
        .ADDR({Spr_bank,G5_Q,L5_Q[3:0],F1CK}),
        .CLK(clk),
        .DATA(P9_Dout),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data),
        .CS_DL(P9_3F_cs),
        .WR(ioctl_wr)
    );
    assign P9_D = (!L5_Q[4]) ? P9_Dout : 8'hFF;

    logic [7:0] P10_D,P10_Dout;
    eprom_32K P10_3H
    (
        .ADDR({Spr_bank,G5_Q,L5_Q[3:0],F1CK}),
        .CLK(clk),
        .DATA(P10_Dout),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data),
        .CS_DL(P10_3H_cs),
        .WR(ioctl_wr)
    );
    assign P10_D = (!L5_Q[4]) ? P10_Dout : 8'hFF;





    PLSO_shift g10 (.RESETn(VIDEO_RSTn), .CLK(clk), .CEN(~CK0), .LOADn(LD), .SI(1'b1), .D(P8_D), .SO(F1D[0]));
    PLSO_shift g9  (.RESETn(VIDEO_RSTn), .CLK(clk), .CEN(~CK0), .LOADn(LD), .SI(1'b1), .D(P9_D),  .SO(F1D[1]));
    PLSO_shift g8  (.RESETn(VIDEO_RSTn), .CLK(clk), .CEN(~CK0), .LOADn(LD), .SI(1'b1), .D(P10_D),  .SO(F1D[2]));
endmodule