data/full_repos/permissive/406831108/MEALY seqence detector.v
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/406831108/MEALY\n        ... Looked in:\n             data/full_repos/permissive/406831108,data/full_repos/permissive/406831108/data/full_repos/permissive/406831108/MEALY\n             data/full_repos/permissive/406831108,data/full_repos/permissive/406831108/data/full_repos/permissive/406831108/MEALY.v\n             data/full_repos/permissive/406831108,data/full_repos/permissive/406831108/data/full_repos/permissive/406831108/MEALY.sv\n             data/full_repos/permissive/406831108/MEALY\n             data/full_repos/permissive/406831108/MEALY.v\n             data/full_repos/permissive/406831108/MEALY.sv\n             obj_dir/data/full_repos/permissive/406831108/MEALY\n             obj_dir/data/full_repos/permissive/406831108/MEALY.v\n             obj_dir/data/full_repos/permissive/406831108/MEALY.sv\n%Error: Cannot find file containing module: seqence\n%Error: Cannot find file containing module: detector.v\n%Error: Exiting due to 3 error(s)\n'
module sequence_0111(clock, reset, in_bit, out_bit
 );
 input clock, reset, in_bit;
 output out_bit;

 reg [2:0] state_reg, next_state;
 
 parameter reset_state = 3'b000;
 parameter read_zero = 3'b001;
 parameter read_0_one = 3'b010;
 parameter read_zero_one_one = 3'b011;
 parameter read_zero_one_one_one= 3'b100;

 
 always @ (posedge clock or posedge reset)
 if (reset == 1)
 state_reg <= reset_state;
 else
 state_reg <= next_state;
 
always @ (state_reg or in_bit)
 case (state_reg)
 reset_state:
 if (in_bit == 0)
 next_state = read_zero;
 else if (in_bit == 1)
 next_state = reset_state;
 else next_state = reset_state;
 read_zero:
 if (in_bit == 0)
 next_state = read_zero;
 else if (in_bit == 1)
 next_state = read_0_one;
 else next_state = reset_state;
 read_0_one:
 if (in_bit == 0)
 next_state = read_zero;
 else if (in_bit == 1)
 next_state = read_zero_one_one;
 else next_state = reset_state;
read_zero_one_one:
 if (in_bit == 0)
 next_state = read_zero;
 else if (in_bit == 1)
 next_state = read_zero_one_one_one;
 else next_state = reset_state;
 read_zero_one_one_one:
 if (in_bit == 0)
 next_state = read_zero;
 else if (in_bit == 1)
 next_state = reset_state;
 else next_state = reset_state;
 default: next_state = reset_state;
endcase
assign out_bit = (state_reg == read_zero_one_one_one)? 1 : 0;
endmodule
module sequence_0111(clock, reset, in_bit, out_bit
 );

 input clock, reset, in_bit;
 output out_bit;

 reg [2:0] state_reg, next_state;
 
 parameter reset_state = 3'b000;
 parameter read_zero = 3'b001;
 parameter read_0_one = 3'b010;
 parameter read_zero_one_one = 3'b011;
 parameter read_zero_one_one_one= 3'b100;

 
 always @ (posedge clock or posedge reset)
 if (reset == 1)
 state_reg <= reset_state;
 else
 state_reg <= next_state;
 
always @ (state_reg or in_bit)
 case (state_reg)
 reset_state:
 if (in_bit == 0)
 next_state = read_zero;
 else if (in_bit == 1)
 next_state = reset_state;
 else next_state = reset_state;
 read_zero:
 if (in_bit == 0)
 next_state = read_zero;
 else if (in_bit == 1)
 next_state = read_0_one;
 else next_state = reset_state;
 read_0_one:
 if (in_bit == 0)
 next_state = read_zero;
 else if (in_bit == 1)
 next_state = read_zero_one_one;
 else next_state = reset_state;
read_zero_one_one:
 if (in_bit == 0)
 next_state = read_zero;
 else if (in_bit == 1)
 next_state = read_zero_one_one_one;
 else next_state = reset_state;
 read_zero_one_one_one:
 if (in_bit == 0)
 next_state = read_zero;
 else if (in_bit == 1)
 next_state = reset_state;
 else next_state = reset_state;
 default: next_state = reset_state;
endcase
assign out_bit = (state_reg == read_zero_one_one_one)? 1 : 0;
endmodule