data/full_repos/permissive/40989439/AdaptevaLib/src/eio_rx/hdl/eio_rx.v
1: b"%Error: data/full_repos/permissive/40989439/AdaptevaLib/src/eio_rx/hdl/eio_rx.v:90: Cannot find file containing module: 'IBUFDS'\n   IBUFDS\n   ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/40989439/AdaptevaLib/src/eio_rx/hdl,data/full_repos/permissive/40989439/IBUFDS\n             data/full_repos/permissive/40989439/AdaptevaLib/src/eio_rx/hdl,data/full_repos/permissive/40989439/IBUFDS.v\n             data/full_repos/permissive/40989439/AdaptevaLib/src/eio_rx/hdl,data/full_repos/permissive/40989439/IBUFDS.sv\n             IBUFDS\n             IBUFDS.v\n             IBUFDS.sv\n             obj_dir/IBUFDS\n             obj_dir/IBUFDS.v\n             obj_dir/IBUFDS.sv\n%Error: data/full_repos/permissive/40989439/AdaptevaLib/src/eio_rx/hdl/eio_rx.v:98: Cannot find file containing module: 'IBUFDS'\n   IBUFDS\n   ^~~~~~\n%Error: data/full_repos/permissive/40989439/AdaptevaLib/src/eio_rx/hdl/eio_rx.v:113: Cannot find file containing module: 'IBUFGDS'\n   IBUFGDS\n   ^~~~~~~\n%Error: data/full_repos/permissive/40989439/AdaptevaLib/src/eio_rx/hdl/eio_rx.v:121: Cannot find file containing module: 'BUFIO'\n   BUFIO bufio_rxlclk\n   ^~~~~\n%Error: data/full_repos/permissive/40989439/AdaptevaLib/src/eio_rx/hdl/eio_rx.v:126: Cannot find file containing module: 'BUFR'\n   BUFR\n   ^~~~\n%Error: data/full_repos/permissive/40989439/AdaptevaLib/src/eio_rx/hdl/eio_rx.v:146: Cannot find file containing module: 'ISERDESE2'\n        ISERDESE2 \n        ^~~~~~~~~\n%Error: data/full_repos/permissive/40989439/AdaptevaLib/src/eio_rx/hdl/eio_rx.v:214: Cannot find file containing module: 'ISERDESE2'\n   ISERDESE2 \n   ^~~~~~~~~\n%Error: data/full_repos/permissive/40989439/AdaptevaLib/src/eio_rx/hdl/eio_rx.v:343: Cannot find file containing module: 'OBUFDS'\n   OBUFDS \n   ^~~~~~\n%Error: data/full_repos/permissive/40989439/AdaptevaLib/src/eio_rx/hdl/eio_rx.v:354: Cannot find file containing module: 'OBUFDS'\n   OBUFDS \n   ^~~~~~\n%Error: Exiting due to 9 error(s)\n"
module eio_rx (

   RX_WR_WAIT_P, RX_WR_WAIT_N, RX_RD_WAIT_P, RX_RD_WAIT_N, rxlclk_p,
   rxframe_p, rxdata_p, ecfg_datain,

   RX_LCLK_P, RX_LCLK_N, reset, ioreset, RX_FRAME_P, RX_FRAME_N,
   RX_DATA_P, RX_DATA_N, rx_wr_wait, rx_rd_wait, ecfg_rx_enable,
   ecfg_rx_gpio_mode, ecfg_rx_loopback_mode, ecfg_dataout, tx_wr_wait,
   tx_rd_wait, txlclk_p, loopback_data, loopback_frame
   );

   parameter IOSTD_ELINK = "LVDS_25";
   



   input       RX_LCLK_P, RX_LCLK_N;
   input       reset;
   input       ioreset;

   input       RX_FRAME_P, RX_FRAME_N;
   input [7:0] RX_DATA_P, RX_DATA_N;

   output      RX_WR_WAIT_P, RX_WR_WAIT_N;
   output      RX_RD_WAIT_P, RX_RD_WAIT_N;




   output        rxlclk_p;
   output [7:0]  rxframe_p;
   output [63:0] rxdata_p;
   input         rx_wr_wait;
   input         rx_rd_wait;
   



   input         ecfg_rx_enable;
   input         ecfg_rx_gpio_mode;
   input         ecfg_rx_loopback_mode;
   input [10:0]  ecfg_dataout;
   output [10:0] ecfg_datain;
   input         tx_wr_wait, tx_rd_wait;


   input         txlclk_p;
   input [63:0]  loopback_data;
   input [7:0]   loopback_frame;
   



   reg [63:0]    rxdata_p;
   reg [7:0]     rxframe_p;
   



   wire [7:0]    rx_data;
   wire          rx_frame;
   wire          serdes_reset;
   



   IBUFDS
	 #(.DIFF_TERM  ("TRUE"),
       .IOSTANDARD (IOSTD_ELINK))
	 ibufds_rxdata[0:7]
	   (.I     (RX_DATA_P),
        .IB    (RX_DATA_N),
        .O     (rx_data));

   IBUFDS
	 #(.DIFF_TERM  ("TRUE"),
       .IOSTANDARD (IOSTD_ELINK))
	 ibufds_rxframe
	   (.I     (RX_FRAME_P),
        .IB    (RX_FRAME_N),
        .O     (rx_frame));





   wire          rx_lclk;
   wire          rx_lclk_s;
   
   IBUFGDS
     #(.DIFF_TERM  ("TRUE"),
       .IOSTANDARD (IOSTD_ELINK))
   ibufds_rxlclk
     (.I          (RX_LCLK_P),
      .IB         (RX_LCLK_N),
      .O          (rx_lclk));

   BUFIO bufio_rxlclk
     (.I (rx_lclk),
      .O (rx_lclk_s));
   

   BUFR
     #(.SIM_DEVICE("7SERIES"),
     .BUFR_DIVIDE("4"))
   clkout_bufr
     (.O (rxlclk_p),
      .CE(1'b1),
      .CLR(1'b0),
      .I (rx_lclk));





   wire [63:0]   rxdata_des;
   wire [7:0]    rxframe_des;
   wire          rx_lclk_sn = ~rx_lclk_s;
   
   genvar        i;
   generate for(i=0; i<8; i=i+1)
     begin : gen_serdes
        ISERDESE2 
          #(
            .DATA_RATE("DDR"),
            .DATA_WIDTH(8),
            .DYN_CLKDIV_INV_EN("FALSE"),
            .DYN_CLK_INV_EN("FALSE"),

            .INIT_Q1(1'b0),
            .INIT_Q2(1'b0),
            .INIT_Q3(1'b0),
            .INIT_Q4(1'b0),
            .INTERFACE_TYPE("NETWORKING"),

            .IOBDELAY("NONE"),
            .NUM_CE(2),
            .OFB_USED("FALSE"),
            .SERDES_MODE("MASTER"),

            .SRVAL_Q1(1'b0),
            .SRVAL_Q2(1'b0),
            .SRVAL_Q3(1'b0),
            .SRVAL_Q4(1'b0)
            )
        ISERDESE2_rxdata
          (
           .O(),

           .Q1(rxdata_des[i]),
           .Q2(rxdata_des[i+8]),
           .Q3(rxdata_des[i+16]),
           .Q4(rxdata_des[i+24]),
           .Q5(rxdata_des[i+32]),
           .Q6(rxdata_des[i+40]),
           .Q7(rxdata_des[i+48]),
           .Q8(rxdata_des[i+56]),

           .SHIFTOUT1(),
           .SHIFTOUT2(),
           .BITSLIP(1'b0),





           .CE1(1'b1),
           .CE2(1'b1),
           .CLKDIVP(1'b0),

           .CLK(rx_lclk_s),
           .CLKB(rx_lclk_sn),
           .CLKDIV(rxlclk_p),
           .OCLK(1'b0),

           .DYNCLKDIVSEL(1'b0),
           .DYNCLKSEL(1'b0),

           .D(rx_data[i]),
           .DDLY(1'b0),
           .OFB(1'b0),
           .OCLKB(1'b0),
           .RST(serdes_reset),

           .SHIFTIN1(1'b0),
           .SHIFTIN2(1'b0)
           );
     end
   endgenerate
   
   ISERDESE2 
     #(
       .DATA_RATE("DDR"),
       .DATA_WIDTH(8),
       .DYN_CLKDIV_INV_EN("FALSE"),
       .DYN_CLK_INV_EN("FALSE"),

       .INIT_Q1(1'b0),
       .INIT_Q2(1'b0),
       .INIT_Q3(1'b0),
       .INIT_Q4(1'b0),
       .INTERFACE_TYPE("NETWORKING"),

       .IOBDELAY("NONE"),
       .NUM_CE(2),
       .OFB_USED("FALSE"),
       .SERDES_MODE("MASTER"),

       .SRVAL_Q1(1'b0),
       .SRVAL_Q2(1'b0),
       .SRVAL_Q3(1'b0),
       .SRVAL_Q4(1'b0)
       )
   ISERDESE2_rxframe
     (
      .O(),

      .Q1(rxframe_des[0]),
      .Q2(rxframe_des[1]),
      .Q3(rxframe_des[2]),
      .Q4(rxframe_des[3]),
      .Q5(rxframe_des[4]),
      .Q6(rxframe_des[5]),
      .Q7(rxframe_des[6]),
      .Q8(rxframe_des[7]),

      .SHIFTOUT1(),
      .SHIFTOUT2(),
      .BITSLIP(1'b0),





      .CE1(1'b1),
      .CE2(1'b1),
      .CLKDIVP(1'b0),

      .CLK(rx_lclk_s),
      .CLKB(rx_lclk_sn),
      .CLKDIV(rxlclk_p),
      .OCLK(1'b0),

      .DYNCLKDIVSEL(1'b0),
      .DYNCLKSEL(1'b0),

      .D(rx_frame),
      .DDLY(1'b0),
      .OFB(1'b0),
      .OCLKB(1'b0),
      .RST(serdes_reset),

      .SHIFTIN1(1'b0),
      .SHIFTIN2(1'b0)
      );


   reg [1:0]   rxenb_sync;
   wire        rxenb = rxenb_sync[0];
   assign      serdes_reset = ~rxenb;
   reg [1:0]   rxloopback_sync;
   wire        rxloopback = rxloopback_sync[0];
   reg [1:0]   rxgpio_sync;
   wire        rxgpio = rxgpio_sync[0];
   

   reg [63:0]  rxdata_reg;
   reg [7:0]   rxframe_reg;

   wire        rxreset = reset | ~ecfg_rx_enable;


   always @ (posedge rxlclk_p or posedge rxreset) begin
      if(rxreset)
        rxenb_sync <= 'd0;
      else
        rxenb_sync <= {1'b1, rxenb_sync[1]};
   end

   always @ (posedge rxlclk_p) begin
      
      rxloopback_sync <= {ecfg_rx_loopback_mode, rxloopback_sync[1]};
      rxgpio_sync <= {ecfg_rx_gpio_mode, rxgpio_sync[1]};
      
      rxdata_reg  <= rxdata_des;
      rxframe_reg <= rxframe_des & {8{rxenb}} & {8{~rxgpio}};

      if(rxloopback) begin
         rxdata_p  <= loopback_data;
         rxframe_p <= loopback_frame;
      end else begin
         rxdata_p  <= rxdata_reg;
         rxframe_p <= rxframe_reg;
      end
   end




   reg [10:0] datain_reg;
   reg [10:0] ecfg_datain;

   always @ (posedge rxlclk_p) begin

      datain_reg[10]  <= tx_wr_wait;
      datain_reg[9]   <= tx_rd_wait;
      datain_reg[8]   <= rxframe_p[0];
      datain_reg[7:0] <= rxdata_p[7:0];
      ecfg_datain     <= datain_reg;
      
   end





   wire rd_wait = rxgpio ? ecfg_dataout[9]  : rx_rd_wait;
   wire wr_wait = rxgpio ? ecfg_dataout[10] : rx_wr_wait;

   OBUFDS 
     #(
       .IOSTANDARD(IOSTD_ELINK),
       .SLEW("SLOW")
       ) OBUFDS_RXWRWAIT
       (
        .O(RX_WR_WAIT_P),
        .OB(RX_WR_WAIT_N),
        .I(wr_wait)
        );
   
   OBUFDS 
     #(
       .IOSTANDARD(IOSTD_ELINK),
       .SLEW("SLOW")
       ) OBUFDS_RXRDWAIT
       (
        .O(RX_RD_WAIT_P),
        .OB(RX_RD_WAIT_N),
        .I(rd_wait)
        );
   
endmodule
module eio_rx (

   RX_WR_WAIT_P, RX_WR_WAIT_N, RX_RD_WAIT_P, RX_RD_WAIT_N, rxlclk_p,
   rxframe_p, rxdata_p, ecfg_datain,

   RX_LCLK_P, RX_LCLK_N, reset, ioreset, RX_FRAME_P, RX_FRAME_N,
   RX_DATA_P, RX_DATA_N, rx_wr_wait, rx_rd_wait, ecfg_rx_enable,
   ecfg_rx_gpio_mode, ecfg_rx_loopback_mode, ecfg_dataout, tx_wr_wait,
   tx_rd_wait, txlclk_p, loopback_data, loopback_frame
   );


   parameter IOSTD_ELINK = "LVDS_25";
   



   input       RX_LCLK_P, RX_LCLK_N;
   input       reset;
   input       ioreset;

   input       RX_FRAME_P, RX_FRAME_N;
   input [7:0] RX_DATA_P, RX_DATA_N;

   output      RX_WR_WAIT_P, RX_WR_WAIT_N;
   output      RX_RD_WAIT_P, RX_RD_WAIT_N;




   output        rxlclk_p;
   output [7:0]  rxframe_p;
   output [63:0] rxdata_p;
   input         rx_wr_wait;
   input         rx_rd_wait;
   



   input         ecfg_rx_enable;
   input         ecfg_rx_gpio_mode;
   input         ecfg_rx_loopback_mode;
   input [10:0]  ecfg_dataout;
   output [10:0] ecfg_datain;
   input         tx_wr_wait, tx_rd_wait;


   input         txlclk_p;
   input [63:0]  loopback_data;
   input [7:0]   loopback_frame;
   



   reg [63:0]    rxdata_p;
   reg [7:0]     rxframe_p;
   



   wire [7:0]    rx_data;
   wire          rx_frame;
   wire          serdes_reset;
   



   IBUFDS
	 #(.DIFF_TERM  ("TRUE"),
       .IOSTANDARD (IOSTD_ELINK))
	 ibufds_rxdata[0:7]
	   (.I     (RX_DATA_P),
        .IB    (RX_DATA_N),
        .O     (rx_data));

   IBUFDS
	 #(.DIFF_TERM  ("TRUE"),
       .IOSTANDARD (IOSTD_ELINK))
	 ibufds_rxframe
	   (.I     (RX_FRAME_P),
        .IB    (RX_FRAME_N),
        .O     (rx_frame));





   wire          rx_lclk;
   wire          rx_lclk_s;
   
   IBUFGDS
     #(.DIFF_TERM  ("TRUE"),
       .IOSTANDARD (IOSTD_ELINK))
   ibufds_rxlclk
     (.I          (RX_LCLK_P),
      .IB         (RX_LCLK_N),
      .O          (rx_lclk));

   BUFIO bufio_rxlclk
     (.I (rx_lclk),
      .O (rx_lclk_s));
   

   BUFR
     #(.SIM_DEVICE("7SERIES"),
     .BUFR_DIVIDE("4"))
   clkout_bufr
     (.O (rxlclk_p),
      .CE(1'b1),
      .CLR(1'b0),
      .I (rx_lclk));





   wire [63:0]   rxdata_des;
   wire [7:0]    rxframe_des;
   wire          rx_lclk_sn = ~rx_lclk_s;
   
   genvar        i;
   generate for(i=0; i<8; i=i+1)
     begin : gen_serdes
        ISERDESE2 
          #(
            .DATA_RATE("DDR"),
            .DATA_WIDTH(8),
            .DYN_CLKDIV_INV_EN("FALSE"),
            .DYN_CLK_INV_EN("FALSE"),

            .INIT_Q1(1'b0),
            .INIT_Q2(1'b0),
            .INIT_Q3(1'b0),
            .INIT_Q4(1'b0),
            .INTERFACE_TYPE("NETWORKING"),

            .IOBDELAY("NONE"),
            .NUM_CE(2),
            .OFB_USED("FALSE"),
            .SERDES_MODE("MASTER"),

            .SRVAL_Q1(1'b0),
            .SRVAL_Q2(1'b0),
            .SRVAL_Q3(1'b0),
            .SRVAL_Q4(1'b0)
            )
        ISERDESE2_rxdata
          (
           .O(),

           .Q1(rxdata_des[i]),
           .Q2(rxdata_des[i+8]),
           .Q3(rxdata_des[i+16]),
           .Q4(rxdata_des[i+24]),
           .Q5(rxdata_des[i+32]),
           .Q6(rxdata_des[i+40]),
           .Q7(rxdata_des[i+48]),
           .Q8(rxdata_des[i+56]),

           .SHIFTOUT1(),
           .SHIFTOUT2(),
           .BITSLIP(1'b0),





           .CE1(1'b1),
           .CE2(1'b1),
           .CLKDIVP(1'b0),

           .CLK(rx_lclk_s),
           .CLKB(rx_lclk_sn),
           .CLKDIV(rxlclk_p),
           .OCLK(1'b0),

           .DYNCLKDIVSEL(1'b0),
           .DYNCLKSEL(1'b0),

           .D(rx_data[i]),
           .DDLY(1'b0),
           .OFB(1'b0),
           .OCLKB(1'b0),
           .RST(serdes_reset),

           .SHIFTIN1(1'b0),
           .SHIFTIN2(1'b0)
           );
     end
   endgenerate
   
   ISERDESE2 
     #(
       .DATA_RATE("DDR"),
       .DATA_WIDTH(8),
       .DYN_CLKDIV_INV_EN("FALSE"),
       .DYN_CLK_INV_EN("FALSE"),

       .INIT_Q1(1'b0),
       .INIT_Q2(1'b0),
       .INIT_Q3(1'b0),
       .INIT_Q4(1'b0),
       .INTERFACE_TYPE("NETWORKING"),

       .IOBDELAY("NONE"),
       .NUM_CE(2),
       .OFB_USED("FALSE"),
       .SERDES_MODE("MASTER"),

       .SRVAL_Q1(1'b0),
       .SRVAL_Q2(1'b0),
       .SRVAL_Q3(1'b0),
       .SRVAL_Q4(1'b0)
       )
   ISERDESE2_rxframe
     (
      .O(),

      .Q1(rxframe_des[0]),
      .Q2(rxframe_des[1]),
      .Q3(rxframe_des[2]),
      .Q4(rxframe_des[3]),
      .Q5(rxframe_des[4]),
      .Q6(rxframe_des[5]),
      .Q7(rxframe_des[6]),
      .Q8(rxframe_des[7]),

      .SHIFTOUT1(),
      .SHIFTOUT2(),
      .BITSLIP(1'b0),





      .CE1(1'b1),
      .CE2(1'b1),
      .CLKDIVP(1'b0),

      .CLK(rx_lclk_s),
      .CLKB(rx_lclk_sn),
      .CLKDIV(rxlclk_p),
      .OCLK(1'b0),

      .DYNCLKDIVSEL(1'b0),
      .DYNCLKSEL(1'b0),

      .D(rx_frame),
      .DDLY(1'b0),
      .OFB(1'b0),
      .OCLKB(1'b0),
      .RST(serdes_reset),

      .SHIFTIN1(1'b0),
      .SHIFTIN2(1'b0)
      );


   reg [1:0]   rxenb_sync;
   wire        rxenb = rxenb_sync[0];
   assign      serdes_reset = ~rxenb;
   reg [1:0]   rxloopback_sync;
   wire        rxloopback = rxloopback_sync[0];
   reg [1:0]   rxgpio_sync;
   wire        rxgpio = rxgpio_sync[0];
   

   reg [63:0]  rxdata_reg;
   reg [7:0]   rxframe_reg;

   wire        rxreset = reset | ~ecfg_rx_enable;


   always @ (posedge rxlclk_p or posedge rxreset) begin
      if(rxreset)
        rxenb_sync <= 'd0;
      else
        rxenb_sync <= {1'b1, rxenb_sync[1]};
   end

   always @ (posedge rxlclk_p) begin
      
      rxloopback_sync <= {ecfg_rx_loopback_mode, rxloopback_sync[1]};
      rxgpio_sync <= {ecfg_rx_gpio_mode, rxgpio_sync[1]};
      
      rxdata_reg  <= rxdata_des;
      rxframe_reg <= rxframe_des & {8{rxenb}} & {8{~rxgpio}};

      if(rxloopback) begin
         rxdata_p  <= loopback_data;
         rxframe_p <= loopback_frame;
      end else begin
         rxdata_p  <= rxdata_reg;
         rxframe_p <= rxframe_reg;
      end
   end




   reg [10:0] datain_reg;
   reg [10:0] ecfg_datain;

   always @ (posedge rxlclk_p) begin

      datain_reg[10]  <= tx_wr_wait;
      datain_reg[9]   <= tx_rd_wait;
      datain_reg[8]   <= rxframe_p[0];
      datain_reg[7:0] <= rxdata_p[7:0];
      ecfg_datain     <= datain_reg;
      
   end





   wire rd_wait = rxgpio ? ecfg_dataout[9]  : rx_rd_wait;
   wire wr_wait = rxgpio ? ecfg_dataout[10] : rx_wr_wait;

   OBUFDS 
     #(
       .IOSTANDARD(IOSTD_ELINK),
       .SLEW("SLOW")
       ) OBUFDS_RXWRWAIT
       (
        .O(RX_WR_WAIT_P),
        .OB(RX_WR_WAIT_N),
        .I(wr_wait)
        );
   
   OBUFDS 
     #(
       .IOSTANDARD(IOSTD_ELINK),
       .SLEW("SLOW")
       ) OBUFDS_RXRDWAIT
       (
        .O(RX_RD_WAIT_P),
        .OB(RX_RD_WAIT_N),
        .I(rd_wait)
        );
   
endmodule