data/full_repos/permissive/458047849/TestBenchDataflow.v
1: b'%Error: data/full_repos/permissive/458047849/TestBenchDataflow.v:17: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("TestBenchDataflow.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/458047849/TestBenchDataflow.v:18: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0,TestBenchDataflow);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/458047849/TestBenchDataflow.v:20: Unsupported: Ignoring delay on this delayed statement.\n#16 W=0; X=0; Y=0; Z=1;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458047849/TestBenchDataflow.v:21: Unsupported: Ignoring delay on this delayed statement.\n#16 W=0; X=0; Y=1; Z=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/458047849/TestBenchDataflow.v:22: Unsupported: Ignoring delay on this delayed statement.\n#16 W=0; X=0; Y=1; Z=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/458047849/TestBenchDataflow.v:23: Unsupported: Ignoring delay on this delayed statement.\n#16 W=0; X=1; Y=0; Z=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/458047849/TestBenchDataflow.v:24: Unsupported: Ignoring delay on this delayed statement.\n#16 W=0; X=1; Y=0; Z=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/458047849/TestBenchDataflow.v:25: Unsupported: Ignoring delay on this delayed statement.\n#16 W=0; X=1; Y=1; Z=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/458047849/TestBenchDataflow.v:26: Unsupported: Ignoring delay on this delayed statement.\n#16 W=0; X=1; Y=1; Z=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/458047849/TestBenchDataflow.v:27: Unsupported: Ignoring delay on this delayed statement.\n#16 W=1; X=0; Y=0; Z=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/458047849/TestBenchDataflow.v:28: Unsupported: Ignoring delay on this delayed statement.\n#16 W=1; X=0; Y=0; Z=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/458047849/TestBenchDataflow.v:29: Unsupported: Ignoring delay on this delayed statement.\n#16\n^\n%Error: Exiting due to 2 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TestBenchDataflow();
reg W, X, Y, Z;
wire A, B, C, D, E, F, G;
SevenSegment SS0(W, X, Y, Z, A, B, C, D, E, F, G);

initial
begin

  $dumpfile("TestBenchDataflow.vcd");
  $dumpvars(0,TestBenchDataflow);
W=0; X=0; Y=0; Z=0;
#16 W=0; X=0; Y=0; Z=1;
#16 W=0; X=0; Y=1; Z=0;
#16 W=0; X=0; Y=1; Z=1;
#16 W=0; X=1; Y=0; Z=0;
#16 W=0; X=1; Y=0; Z=1;
#16 W=0; X=1; Y=1; Z=0;
#16 W=0; X=1; Y=1; Z=1;
#16 W=1; X=0; Y=0; Z=0;
#16 W=1; X=0; Y=0; Z=1;
#16
$finish();
end
endmodule
module TestBenchDataflow();

reg W, X, Y, Z;
wire A, B, C, D, E, F, G;
SevenSegment SS0(W, X, Y, Z, A, B, C, D, E, F, G);

initial
begin

  $dumpfile("TestBenchDataflow.vcd");
  $dumpvars(0,TestBenchDataflow);
W=0; X=0; Y=0; Z=0;
#16 W=0; X=0; Y=0; Z=1;
#16 W=0; X=0; Y=1; Z=0;
#16 W=0; X=0; Y=1; Z=1;
#16 W=0; X=1; Y=0; Z=0;
#16 W=0; X=1; Y=0; Z=1;
#16 W=0; X=1; Y=1; Z=0;
#16 W=0; X=1; Y=1; Z=1;
#16 W=1; X=0; Y=0; Z=0;
#16 W=1; X=0; Y=0; Z=1;
#16
$finish();
end
endmodule