data/full_repos/permissive/427281804/FPU/verilog/misc.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/427281804/FPU/verilog/misc.v:23: Multiple top level modules\n                                                                             : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                             : ... Top module \'xchg\'\nmodule xchg #(\n       ^~~~\n                                                                             : ... Top module \'bsr\'\nmodule bsr #(\n       ^~~\n                                                                             : ... Top module \'bsl\'\nmodule bsl #(\n       ^~~\n                                                                             : ... Top module \'count_lead_zero\'\nmodule count_lead_zero #(\n       ^~~~~~~~~~~~~~~\n                                                                             : ... Top module \'booth_enc_r4\'\nmodule booth_enc_r4(\n       ^~~~~~~~~~~~\n                                                                             : ... Top module \'cla_adder\'\nmodule cla_adder #(\n       ^~~~~~~~~\n                                                                             : ... Top module \'booth_ppgen_r4\'\nmodule booth_ppgen_r4 #(\n       ^~~~~~~~~~~~~~\n                                                                             : ... Top module \'compl2s\'\nmodule compl2s #(\n       ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:195: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                           : ... In instance booth_ppgen_r4\n  o = {(DWIDTH){1\'bx}};\n    ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:65: Operator COND expects 33 bits on the Conditional False, but Conditional False\'s ARRAYSEL generates 32 bits.\n                                                                          : ... In instance bsl\n  assign temp[gi+1] = s[gi] ? {temp[gi],{(2**gi){filler}}} : temp[gi];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:65: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 33 bits.\n                                                                          : ... In instance bsl\n  assign temp[gi+1] = s[gi] ? {temp[gi],{(2**gi){filler}}} : temp[gi];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:65: Operator COND expects 34 bits on the Conditional False, but Conditional False\'s ARRAYSEL generates 32 bits.\n                                                                          : ... In instance bsl\n  assign temp[gi+1] = s[gi] ? {temp[gi],{(2**gi){filler}}} : temp[gi];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:65: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 34 bits.\n                                                                          : ... In instance bsl\n  assign temp[gi+1] = s[gi] ? {temp[gi],{(2**gi){filler}}} : temp[gi];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:65: Operator COND expects 36 bits on the Conditional False, but Conditional False\'s ARRAYSEL generates 32 bits.\n                                                                          : ... In instance bsl\n  assign temp[gi+1] = s[gi] ? {temp[gi],{(2**gi){filler}}} : temp[gi];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:65: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 36 bits.\n                                                                          : ... In instance bsl\n  assign temp[gi+1] = s[gi] ? {temp[gi],{(2**gi){filler}}} : temp[gi];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:65: Operator COND expects 40 bits on the Conditional False, but Conditional False\'s ARRAYSEL generates 32 bits.\n                                                                          : ... In instance bsl\n  assign temp[gi+1] = s[gi] ? {temp[gi],{(2**gi){filler}}} : temp[gi];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:65: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 40 bits.\n                                                                          : ... In instance bsl\n  assign temp[gi+1] = s[gi] ? {temp[gi],{(2**gi){filler}}} : temp[gi];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:65: Operator COND expects 48 bits on the Conditional False, but Conditional False\'s ARRAYSEL generates 32 bits.\n                                                                          : ... In instance bsl\n  assign temp[gi+1] = s[gi] ? {temp[gi],{(2**gi){filler}}} : temp[gi];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:65: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 48 bits.\n                                                                          : ... In instance bsl\n  assign temp[gi+1] = s[gi] ? {temp[gi],{(2**gi){filler}}} : temp[gi];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:41: Operator COND expects 33 bits on the Conditional False, but Conditional False\'s ARRAYSEL generates 32 bits.\n                                                                          : ... In instance bsr\n  assign temp[gi+1] = s[gi] ? {{(2**gi){filler}},temp[gi]>>(2**gi)} : temp[gi];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:41: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 33 bits.\n                                                                          : ... In instance bsr\n  assign temp[gi+1] = s[gi] ? {{(2**gi){filler}},temp[gi]>>(2**gi)} : temp[gi];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:41: Operator COND expects 34 bits on the Conditional False, but Conditional False\'s ARRAYSEL generates 32 bits.\n                                                                          : ... In instance bsr\n  assign temp[gi+1] = s[gi] ? {{(2**gi){filler}},temp[gi]>>(2**gi)} : temp[gi];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:41: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 34 bits.\n                                                                          : ... In instance bsr\n  assign temp[gi+1] = s[gi] ? {{(2**gi){filler}},temp[gi]>>(2**gi)} : temp[gi];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:41: Operator COND expects 36 bits on the Conditional False, but Conditional False\'s ARRAYSEL generates 32 bits.\n                                                                          : ... In instance bsr\n  assign temp[gi+1] = s[gi] ? {{(2**gi){filler}},temp[gi]>>(2**gi)} : temp[gi];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:41: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 36 bits.\n                                                                          : ... In instance bsr\n  assign temp[gi+1] = s[gi] ? {{(2**gi){filler}},temp[gi]>>(2**gi)} : temp[gi];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:41: Operator COND expects 40 bits on the Conditional False, but Conditional False\'s ARRAYSEL generates 32 bits.\n                                                                          : ... In instance bsr\n  assign temp[gi+1] = s[gi] ? {{(2**gi){filler}},temp[gi]>>(2**gi)} : temp[gi];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:41: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 40 bits.\n                                                                          : ... In instance bsr\n  assign temp[gi+1] = s[gi] ? {{(2**gi){filler}},temp[gi]>>(2**gi)} : temp[gi];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:41: Operator COND expects 48 bits on the Conditional False, but Conditional False\'s ARRAYSEL generates 32 bits.\n                                                                          : ... In instance bsr\n  assign temp[gi+1] = s[gi] ? {{(2**gi){filler}},temp[gi]>>(2**gi)} : temp[gi];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/427281804/FPU/verilog/misc.v:41: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s COND generates 48 bits.\n                                                                          : ... In instance bsr\n  assign temp[gi+1] = s[gi] ? {{(2**gi){filler}},temp[gi]>>(2**gi)} : temp[gi];\n                    ^\n%Error: Exiting due to 22 warning(s)\n'
module booth_enc_r4(
	input      [2:0]	bin,
	output reg [2:0]	br4_out
);

localparam  BOOTH_0  = 3'b000;
localparam  BOOTH_P1 = 3'b001;
localparam  BOOTH_P2 = 3'b010;
localparam  BOOTH_N1 = 3'b111;
localparam  BOOTH_N2 = 3'b110;

always @* begin
	br4_out = 3'bxxx;
	case(bin)
		3'b000: br4_out = BOOTH_0;
		3'b001: br4_out = BOOTH_P1;
		3'b010: br4_out = BOOTH_P1;
		3'b011: br4_out = BOOTH_P2;
		3'b100: br4_out = BOOTH_N2;
		3'b101: br4_out = BOOTH_N1;
		3'b110: br4_out = BOOTH_N1;
		3'b111: br4_out = BOOTH_0;
	endcase
end

endmodule
module booth_enc_r4(
	input      [2:0]	bin,
	output reg [2:0]	br4_out
);


localparam  BOOTH_0  = 3'b000;
localparam  BOOTH_P1 = 3'b001;
localparam  BOOTH_P2 = 3'b010;
localparam  BOOTH_N1 = 3'b111;
localparam  BOOTH_N2 = 3'b110;

always @* begin
	br4_out = 3'bxxx;
	case(bin)
		3'b000: br4_out = BOOTH_0;
		3'b001: br4_out = BOOTH_P1;
		3'b010: br4_out = BOOTH_P1;
		3'b011: br4_out = BOOTH_P2;
		3'b100: br4_out = BOOTH_N2;
		3'b101: br4_out = BOOTH_N1;
		3'b110: br4_out = BOOTH_N1;
		3'b111: br4_out = BOOTH_0;
	endcase
end

endmodule