data/full_repos/permissive/497530416/pipe/memory.v
1: b'%Warning-WIDTH: data/full_repos/permissive/497530416/pipe/memory.v:17: Bit extraction of array[127:0] requires 7 bit index, not 64 bits.\n                                                                     : ... In instance memory_pipe\n    begin m_valM = memory[M_valE]; end\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/497530416/pipe/memory.v:20: Bit extraction of array[127:0] requires 7 bit index, not 64 bits.\n                                                                     : ... In instance memory_pipe\n    begin m_valM = memory[M_valA]; end\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/497530416/pipe/memory.v:23: Bit extraction of array[127:0] requires 7 bit index, not 64 bits.\n                                                                     : ... In instance memory_pipe\n    begin m_valM = memory[M_valA]; end\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/497530416/pipe/memory.v:32: Bit extraction of array[127:0] requires 7 bit index, not 64 bits.\n                                                                     : ... In instance memory_pipe\n    begin memory[M_valE] = M_valA; end\n                ^\n%Warning-WIDTH: data/full_repos/permissive/497530416/pipe/memory.v:35: Bit extraction of array[127:0] requires 7 bit index, not 64 bits.\n                                                                     : ... In instance memory_pipe\n    begin memory[M_valE] = M_valA; end\n                ^\n%Warning-WIDTH: data/full_repos/permissive/497530416/pipe/memory.v:38: Bit extraction of array[127:0] requires 7 bit index, not 64 bits.\n                                                                     : ... In instance memory_pipe\n    begin memory[M_valE] = M_valA; end\n                ^\n%Error: Exiting due to 6 warning(s)\n'
module memory_pipe(clk, M_icode, M_valA, M_valE, M_dstE, M_dstM, m_icode, m_dstE, m_dstM, m_valM, m_valE);

input clk;
input wire [3:0] M_icode, M_dstE, M_dstM;
input wire [63:0] M_valA, M_valE;

output reg [63:0] m_valM;
output reg [63:0] m_valE;
output reg [3:0] m_icode, m_dstE, m_dstM;
reg [63:0] memory [0:127];

always @(*)
begin
    case(M_icode)

    4'b0101:
    begin m_valM = memory[M_valE]; end

    4'b1001:
    begin m_valM = memory[M_valA]; end

    4'b1011:
    begin m_valM = memory[M_valA]; end
    
    endcase
end

always @(posedge clk) begin
    case(M_icode)

    4'b0100:
    begin memory[M_valE] = M_valA; end

    4'b1000:
    begin memory[M_valE] = M_valA; end

    4'b1010:
    begin memory[M_valE] = M_valA; end

    endcase
end

always@(*)
    begin
        m_icode = M_icode;
        m_dstE = M_dstE;
        m_dstM = M_dstM;
        m_valE = M_valE;
    end

endmodule
module memory_pipe(clk, M_icode, M_valA, M_valE, M_dstE, M_dstM, m_icode, m_dstE, m_dstM, m_valM, m_valE);


input clk;
input wire [3:0] M_icode, M_dstE, M_dstM;
input wire [63:0] M_valA, M_valE;

output reg [63:0] m_valM;
output reg [63:0] m_valE;
output reg [3:0] m_icode, m_dstE, m_dstM;
reg [63:0] memory [0:127];

always @(*)
begin
    case(M_icode)

    4'b0101:
    begin m_valM = memory[M_valE]; end

    4'b1001:
    begin m_valM = memory[M_valA]; end

    4'b1011:
    begin m_valM = memory[M_valA]; end
    
    endcase
end

always @(posedge clk) begin
    case(M_icode)

    4'b0100:
    begin memory[M_valE] = M_valA; end

    4'b1000:
    begin memory[M_valE] = M_valA; end

    4'b1010:
    begin memory[M_valE] = M_valA; end

    endcase
end

always@(*)
    begin
        m_icode = M_icode;
        m_dstE = M_dstE;
        m_dstM = M_dstM;
        m_valE = M_valE;
    end

endmodule