data/full_repos/permissive/429737743/sources_1/new/CU.v
1: b'%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:21: Cannot find include file: cpu_constant.v\n`include "cpu_constant.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/429737743/sources_1/new,data/full_repos/permissive/429737743/cpu_constant.v\n             data/full_repos/permissive/429737743/sources_1/new,data/full_repos/permissive/429737743/cpu_constant.v.v\n             data/full_repos/permissive/429737743/sources_1/new,data/full_repos/permissive/429737743/cpu_constant.v.sv\n             cpu_constant.v\n             cpu_constant.v.v\n             cpu_constant.v.sv\n             obj_dir/cpu_constant.v\n             obj_dir/cpu_constant.v.v\n             obj_dir/cpu_constant.v.sv\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:38: Define or directive not defined: \'`FETCH\'\n    if (!rst) curstate <= `FETCH;\n                          ^~~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:38: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    if (!rst) curstate <= `FETCH;\n                                ^\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:44: Define or directive not defined: \'`FETCH\'\n        `FETCH : nxtstate <= `DECODE;\n        ^~~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:44: syntax error, unexpected \':\', expecting endcase\n        `FETCH : nxtstate <= `DECODE;\n               ^\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:44: Define or directive not defined: \'`DECODE\'\n        `FETCH : nxtstate <= `DECODE;\n                             ^~~~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:45: Define or directive not defined: \'`DECODE\'\n        `DECODE : begin\n        ^~~~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:46: Define or directive not defined: \'`NULL_\'\n            if ($signed(ins) != `NULL_)\n                                ^~~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:47: Define or directive not defined: \'`EXECUTE\'\n                nxtstate <= `EXECUTE;\n                            ^~~~~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:49: Define or directive not defined: \'`FETCH\'\n                nxtstate <= `FETCH;\n                            ^~~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:51: Define or directive not defined: \'`EXECUTE\'\n        `EXECUTE : begin\n        ^~~~~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:51: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n        `EXECUTE : begin\n                   ^~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:53: Define or directive not defined: \'`SType\'\n                `SType : nxtstate <= `STORE;\n                ^~~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:53: Define or directive not defined: \'`STORE\'\n                `SType : nxtstate <= `STORE;\n                                     ^~~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:54: Define or directive not defined: \'`LType\'\n                `LType : nxtstate <= `LOAD;\n                ^~~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:54: Define or directive not defined: \'`LOAD\'\n                `LType : nxtstate <= `LOAD;\n                                     ^~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:55: Define or directive not defined: \'`WRITEB\'\n                default : nxtstate <= `WRITEB;\n                                      ^~~~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:58: Define or directive not defined: \'`STORE\'\n        `STORE : nxtstate <= `FETCH;\n        ^~~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:58: Define or directive not defined: \'`FETCH\'\n        `STORE : nxtstate <= `FETCH;\n                             ^~~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:59: Define or directive not defined: \'`LOAD\'\n        `LOAD : nxtstate <= `WRITEB;\n        ^~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:59: Define or directive not defined: \'`WRITEB\'\n        `LOAD : nxtstate <= `WRITEB;\n                            ^~~~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:60: Define or directive not defined: \'`WRITEB\'\n        `WRITEB : begin\n        ^~~~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:62: Define or directive not defined: \'`BType\'\n                `BType, `jalType, `jalrType : begin\n                ^~~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:62: Define or directive not defined: \'`jalType\'\n                `BType, `jalType, `jalrType : begin\n                        ^~~~~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:62: Define or directive not defined: \'`jalrType\'\n                `BType, `jalType, `jalrType : begin\n                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:63: Define or directive not defined: \'`CURD\'\n                    nxtstate <= `CURD;\n                                ^~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:65: syntax error, unexpected \':\', expecting clocking\n                default : nxtstate <= `FETCH;\n                        ^\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:65: Define or directive not defined: \'`FETCH\'\n                default : nxtstate <= `FETCH;\n                                      ^~~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:68: Define or directive not defined: \'`FETCH\'\n        default : nxtstate <= `FETCH;\n                              ^~~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:74: Define or directive not defined: \'`FETCH\'\n        `FETCH : begin\n        ^~~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:81: Define or directive not defined: \'`DECODE\'\n        `DECODE : begin\n        ^~~~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:84: Define or directive not defined: \'`RRD\'\n            Rf <= {1\'b1, `RRD};  \n                         ^~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:88: Define or directive not defined: \'`EXECUTE\'\n        `EXECUTE : begin\n        ^~~~~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:92: Define or directive not defined: \'`RType\'\n            if (op == `RType || op == `BType) C_mux0 <= 0;\n                      ^~~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:92: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n            if (op == `RType || op == `BType) C_mux0 <= 0;\n                             ^~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:92: Define or directive not defined: \'`BType\'\n            if (op == `RType || op == `BType) C_mux0 <= 0;\n                                      ^~~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:97: Define or directive not defined: \'`add_\'\n                `add_, `addi_ : op_Alu = `ADD;\n                ^~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:97: syntax error, unexpected \',\', expecting endcase\n                `add_, `addi_ : op_Alu = `ADD;\n                     ^\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:97: Define or directive not defined: \'`addi_\'\n                `add_, `addi_ : op_Alu = `ADD;\n                       ^~~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:97: Define or directive not defined: \'`ADD\'\n                `add_, `addi_ : op_Alu = `ADD;\n                                         ^~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:98: Define or directive not defined: \'`sub_\'\n                `sub_, `beq_, `bne_, `blt_, `bge_, `bltu_, `bgeu_ : op_Alu = `SUB;\n                ^~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:98: Define or directive not defined: \'`beq_\'\n                `sub_, `beq_, `bne_, `blt_, `bge_, `bltu_, `bgeu_ : op_Alu = `SUB;\n                       ^~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:98: Define or directive not defined: \'`bne_\'\n                `sub_, `beq_, `bne_, `blt_, `bge_, `bltu_, `bgeu_ : op_Alu = `SUB;\n                              ^~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:98: Define or directive not defined: \'`blt_\'\n                `sub_, `beq_, `bne_, `blt_, `bge_, `bltu_, `bgeu_ : op_Alu = `SUB;\n                                     ^~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:98: Define or directive not defined: \'`bge_\'\n                `sub_, `beq_, `bne_, `blt_, `bge_, `bltu_, `bgeu_ : op_Alu = `SUB;\n                                            ^~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:98: Define or directive not defined: \'`bltu_\'\n                `sub_, `beq_, `bne_, `blt_, `bge_, `bltu_, `bgeu_ : op_Alu = `SUB;\n                                                   ^~~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:98: Define or directive not defined: \'`bgeu_\'\n                `sub_, `beq_, `bne_, `blt_, `bge_, `bltu_, `bgeu_ : op_Alu = `SUB;\n                                                           ^~~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:98: Define or directive not defined: \'`SUB\'\n                `sub_, `beq_, `bne_, `blt_, `bge_, `bltu_, `bgeu_ : op_Alu = `SUB;\n                                                                             ^~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:99: Define or directive not defined: \'`xor_\'\n                `xor_, `xori_ : op_Alu = `XOR;\n                ^~~~~\n%Error: data/full_repos/permissive/429737743/sources_1/new/CU.v:99: Define or directive not defined: \'`xori_\'\n                `xor_, `xori_ : op_Alu = `XOR;\n                       ^~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module CU(
    ins, rst, clk, Zero, Neg, uNeg, op,
    Pcif, Id, Rf, C_mux0, C_mux1, C_mux2, C_mux3, C_mux4, op_Alu, e_Alu, Mct, Npc
);

input [6 : 0] ins, op;
input rst, clk, Zero, Neg, uNeg;
output Pcif, Id, C_mux0, C_mux1, C_mux3, C_mux4, e_Alu, Npc;
reg Pcif, Id, C_mux0, C_mux1, C_mux3, C_mux4, e_Alu, Npc;
output [1 : 0] Rf, C_mux2;reg [1 : 0] Rf, C_mux2;
output [3 : 0] op_Alu, Mct;reg [3 : 0] op_Alu, Mct;

reg [2 : 0] curstate, nxtstate;

always @(posedge clk  or posedge rst) begin
    if (!rst) curstate <= `FETCH;
    else curstate <= nxtstate;
end

always @(*) begin
    case (curstate)
        `FETCH : nxtstate <= `DECODE;
        `DECODE : begin
            if ($signed(ins) != `NULL_)
                nxtstate <= `EXECUTE;
            else 
                nxtstate <= `FETCH;
        end
        `EXECUTE : begin
            case (op)
                `SType : nxtstate <= `STORE;
                `LType : nxtstate <= `LOAD;
                default : nxtstate <= `WRITEB;
            endcase
        end
        `STORE : nxtstate <= `FETCH;
        `LOAD : nxtstate <= `WRITEB;
        `WRITEB : begin
            case (op)
                `BType, `jalType, `jalrType : begin
                    nxtstate <= `CURD;
                end
                default : nxtstate <= `FETCH;
            endcase
        end
        default : nxtstate <= `FETCH;
    endcase
end

always @(*) begin
    case (curstate)
        `FETCH : begin
            {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} <= 6'b01_01_00;
            {Pcif, Id, e_Alu, Npc} <= 4'b1000;
            Rf <= 0;
            op_Alu <= 0;
            Mct <= 4'b1111;
        end
        `DECODE : begin
            {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} <= 6'b00_01_00;
            {Pcif, Id, e_Alu, Npc} <= 4'b0100;
            Rf <= {1'b1, `RRD};
            op_Alu <= 0;
            Mct <= 4'b0000;
        end
        `EXECUTE : begin
            {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} <= 6'b00_00_00;


            if (op == `RType || op == `BType) C_mux0 <= 0;
            else C_mux0 <= 1;
            {Pcif, Id, e_Alu, Npc} <= 4'b0010;
            Rf <= 0;
            case (ins)
                `add_, `addi_ : op_Alu = `ADD;
                `sub_, `beq_, `bne_, `blt_, `bge_, `bltu_, `bgeu_ : op_Alu = `SUB;
                `xor_, `xori_ : op_Alu = `XOR;
                `or_, `ori_ : op_Alu = `OR;
                `and_, `andi_ : op_Alu = `AND;
                `sll_, `slli_ : op_Alu = `SLL;
                `srl_, `srli_ : op_Alu = `SRL;
                `sra_, `srai_ : op_Alu = `SRA;
                `slt_, `slti_ : op_Alu = `SLT;
                `sltu_, `sltiu_ : op_Alu = `SLTU;
                default : op_Alu = `ADD;
            endcase
        end
        `LOAD : begin
            {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} <= 6'b10_01_00;
            {Pcif, Id, e_Alu, Npc} <= 4'b0000;
            Rf <= 0;
            op_Alu <= 0;
            case (ins)
                `lw_ : Mct <= 4'b1000;
                `lb_ : Mct <= 4'b1010;
                `lh_ : Mct <= 4'b1001;
                default : Mct <= 4'b0000;
            endcase
        end
        `STORE : begin
            {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} <= 6'b10_00_00;
            {Pcif, Id, e_Alu, Npc} <= 4'b0001;
            Rf <= 0;
            op_Alu <= 0;
            case (ins)
                `sw_ : Mct <= 4'b1100;
                `sh_ : Mct <= 4'b1101;
                `sb_ : Mct <= 4'b1110;
                default : Mct <= 4'b0000;
            endcase
        end
        `WRITEB : begin
            {C_mux0, C_mux1, C_mux3, C_mux4} <= 4'b00_00;
            {Pcif, Id, e_Alu, Npc} = 4'b0001;
            Rf = {1'b1, `RWT};
            op_Alu = 0;
            Mct = 4'b0000;
        end
        `CURD : begin
            case (ins)
                `jal_ : begin
                    {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} = 6'b00_10_10;
                    {Pcif, Id, e_Alu, Npc} = 4'b0001;
                    Rf = {1'b1, `RWT};
                    op_Alu = 0;
                    Mct = 0;
                end
                `jalr_ : begin
                    {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} = 6'b00_10_01;
                    {Pcif, Id, e_Alu, Npc} = 4'b0001;
                    Rf = {1'b1, `RWT};
                    op_Alu = 0;
                    Mct = 0;
                end
                `beq_ : begin
                    if (Zero == 0) begin
                        {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} = 6'b00_00_10;
                        {Pcif, Id, e_Alu, Npc} = 4'b0001;
                        Rf = 0;
                        op_Alu = 0;
                        Mct = 0;
                    end
                    else begin
                        {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} = 6'b00_00_00;
                        {Pcif, Id, e_Alu, Npc} = 4'b0001;
                        Rf = 0;
                        op_Alu = 0;
                        Mct = 0;
                    end
                end
                `bne_ : begin
                    if (!Zero) begin
                        {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} = 6'b00_00_10;
                        {Pcif, Id, e_Alu, Npc} = 4'b0001;
                        Rf = 0;
                        op_Alu = 0;
                        Mct = 0;
                    end
                    else begin
                        {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} = 6'b00_00_00;
                        {Pcif, Id, e_Alu, Npc} = 4'b0001;
                        Rf = 0;
                        op_Alu = 0;
                        Mct = 0;
                    end
                end
                `blt_ : begin
                    if (!Zero && Neg) begin
                        {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} = 6'b00_00_10;
                        {Pcif, Id, e_Alu, Npc} = 4'b0001;
                        Rf = 0;
                        op_Alu = 0;
                        Mct = 0;
                    end
                    else begin
                        {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} = 6'b00_00_00;
                        {Pcif, Id, e_Alu, Npc} = 4'b0001;
                        Rf = 0;
                        op_Alu = 0;
                        Mct = 0;
                    end
                end
                `bge_ : begin
                    if (!Neg) begin
                        {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} = 6'b00_10_10;
                        {Pcif, Id, e_Alu, Npc} = 4'b0001;
                        Rf = 0;
                        op_Alu = 0;
                        Mct = 0;
                    end
                    else begin
                        {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} = 6'b00_00_00;
                        {Pcif, Id, e_Alu, Npc} = 4'b0001;
                        Rf = 0;
                        op_Alu = 0;
                        Mct = 0;
                    end
                end
                `bltu_ : begin
                    if (uNeg != Neg) begin
                        {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} = 6'b00_10_10;
                        {Pcif, Id, e_Alu, Npc} = 4'b0001;
                        Rf = 0;
                        op_Alu = 0;
                        Mct = 0;
                    end
                    else begin
                        {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} = 6'b00_00_00;
                        {Pcif, Id, e_Alu, Npc} = 4'b0001;
                        Rf = 0;
                        op_Alu = 0;
                        Mct = 0;
                    end
                end
                `bgeu_ : begin
                    if (uNeg == Neg) begin
                        {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} = 6'b00_10_10;
                        {Pcif, Id, e_Alu, Npc} = 4'b0001;
                        Rf = 0;
                        op_Alu = 0;
                        Mct = 0;
                    end
                    else begin
                        {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} = 6'b00_00_00;
                        {Pcif, Id, e_Alu, Npc} = 4'b0001;
                        Rf = 0;
                        op_Alu = 0;
                        Mct = 0;
                    end
                end
                default : begin
                    {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} = 6'b00_00_00;
                    {Pcif, Id, e_Alu, Npc} = 4'b0001;
                    Rf = 0;
                    op_Alu = 0;
                    Mct = 0;
                end
            endcase
        end
    endcase
end
endmodule
module CU(
    ins, rst, clk, Zero, Neg, uNeg, op,
    Pcif, Id, Rf, C_mux0, C_mux1, C_mux2, C_mux3, C_mux4, op_Alu, e_Alu, Mct, Npc
);


input [6 : 0] ins, op;
input rst, clk, Zero, Neg, uNeg;
output Pcif, Id, C_mux0, C_mux1, C_mux3, C_mux4, e_Alu, Npc;
reg Pcif, Id, C_mux0, C_mux1, C_mux3, C_mux4, e_Alu, Npc;
output [1 : 0] Rf, C_mux2;reg [1 : 0] Rf, C_mux2;
output [3 : 0] op_Alu, Mct;reg [3 : 0] op_Alu, Mct;

reg [2 : 0] curstate, nxtstate;

always @(posedge clk  or posedge rst) begin
    if (!rst) curstate <= `FETCH;
    else curstate <= nxtstate;
end

always @(*) begin
    case (curstate)
        `FETCH : nxtstate <= `DECODE;
        `DECODE : begin
            if ($signed(ins) != `NULL_)
                nxtstate <= `EXECUTE;
            else 
                nxtstate <= `FETCH;
        end
        `EXECUTE : begin
            case (op)
                `SType : nxtstate <= `STORE;
                `LType : nxtstate <= `LOAD;
                default : nxtstate <= `WRITEB;
            endcase
        end
        `STORE : nxtstate <= `FETCH;
        `LOAD : nxtstate <= `WRITEB;
        `WRITEB : begin
            case (op)
                `BType, `jalType, `jalrType : begin
                    nxtstate <= `CURD;
                end
                default : nxtstate <= `FETCH;
            endcase
        end
        default : nxtstate <= `FETCH;
    endcase
end

always @(*) begin
    case (curstate)
        `FETCH : begin
            {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} <= 6'b01_01_00;
            {Pcif, Id, e_Alu, Npc} <= 4'b1000;
            Rf <= 0;
            op_Alu <= 0;
            Mct <= 4'b1111;
        end
        `DECODE : begin
            {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} <= 6'b00_01_00;
            {Pcif, Id, e_Alu, Npc} <= 4'b0100;
            Rf <= {1'b1, `RRD};
            op_Alu <= 0;
            Mct <= 4'b0000;
        end
        `EXECUTE : begin
            {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} <= 6'b00_00_00;


            if (op == `RType || op == `BType) C_mux0 <= 0;
            else C_mux0 <= 1;
            {Pcif, Id, e_Alu, Npc} <= 4'b0010;
            Rf <= 0;
            case (ins)
                `add_, `addi_ : op_Alu = `ADD;
                `sub_, `beq_, `bne_, `blt_, `bge_, `bltu_, `bgeu_ : op_Alu = `SUB;
                `xor_, `xori_ : op_Alu = `XOR;
                `or_, `ori_ : op_Alu = `OR;
                `and_, `andi_ : op_Alu = `AND;
                `sll_, `slli_ : op_Alu = `SLL;
                `srl_, `srli_ : op_Alu = `SRL;
                `sra_, `srai_ : op_Alu = `SRA;
                `slt_, `slti_ : op_Alu = `SLT;
                `sltu_, `sltiu_ : op_Alu = `SLTU;
                default : op_Alu = `ADD;
            endcase
        end
        `LOAD : begin
            {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} <= 6'b10_01_00;
            {Pcif, Id, e_Alu, Npc} <= 4'b0000;
            Rf <= 0;
            op_Alu <= 0;
            case (ins)
                `lw_ : Mct <= 4'b1000;
                `lb_ : Mct <= 4'b1010;
                `lh_ : Mct <= 4'b1001;
                default : Mct <= 4'b0000;
            endcase
        end
        `STORE : begin
            {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} <= 6'b10_00_00;
            {Pcif, Id, e_Alu, Npc} <= 4'b0001;
            Rf <= 0;
            op_Alu <= 0;
            case (ins)
                `sw_ : Mct <= 4'b1100;
                `sh_ : Mct <= 4'b1101;
                `sb_ : Mct <= 4'b1110;
                default : Mct <= 4'b0000;
            endcase
        end
        `WRITEB : begin
            {C_mux0, C_mux1, C_mux3, C_mux4} <= 4'b00_00;
            {Pcif, Id, e_Alu, Npc} = 4'b0001;
            Rf = {1'b1, `RWT};
            op_Alu = 0;
            Mct = 4'b0000;
        end
        `CURD : begin
            case (ins)
                `jal_ : begin
                    {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} = 6'b00_10_10;
                    {Pcif, Id, e_Alu, Npc} = 4'b0001;
                    Rf = {1'b1, `RWT};
                    op_Alu = 0;
                    Mct = 0;
                end
                `jalr_ : begin
                    {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} = 6'b00_10_01;
                    {Pcif, Id, e_Alu, Npc} = 4'b0001;
                    Rf = {1'b1, `RWT};
                    op_Alu = 0;
                    Mct = 0;
                end
                `beq_ : begin
                    if (Zero == 0) begin
                        {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} = 6'b00_00_10;
                        {Pcif, Id, e_Alu, Npc} = 4'b0001;
                        Rf = 0;
                        op_Alu = 0;
                        Mct = 0;
                    end
                    else begin
                        {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} = 6'b00_00_00;
                        {Pcif, Id, e_Alu, Npc} = 4'b0001;
                        Rf = 0;
                        op_Alu = 0;
                        Mct = 0;
                    end
                end
                `bne_ : begin
                    if (!Zero) begin
                        {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} = 6'b00_00_10;
                        {Pcif, Id, e_Alu, Npc} = 4'b0001;
                        Rf = 0;
                        op_Alu = 0;
                        Mct = 0;
                    end
                    else begin
                        {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} = 6'b00_00_00;
                        {Pcif, Id, e_Alu, Npc} = 4'b0001;
                        Rf = 0;
                        op_Alu = 0;
                        Mct = 0;
                    end
                end
                `blt_ : begin
                    if (!Zero && Neg) begin
                        {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} = 6'b00_00_10;
                        {Pcif, Id, e_Alu, Npc} = 4'b0001;
                        Rf = 0;
                        op_Alu = 0;
                        Mct = 0;
                    end
                    else begin
                        {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} = 6'b00_00_00;
                        {Pcif, Id, e_Alu, Npc} = 4'b0001;
                        Rf = 0;
                        op_Alu = 0;
                        Mct = 0;
                    end
                end
                `bge_ : begin
                    if (!Neg) begin
                        {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} = 6'b00_10_10;
                        {Pcif, Id, e_Alu, Npc} = 4'b0001;
                        Rf = 0;
                        op_Alu = 0;
                        Mct = 0;
                    end
                    else begin
                        {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} = 6'b00_00_00;
                        {Pcif, Id, e_Alu, Npc} = 4'b0001;
                        Rf = 0;
                        op_Alu = 0;
                        Mct = 0;
                    end
                end
                `bltu_ : begin
                    if (uNeg != Neg) begin
                        {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} = 6'b00_10_10;
                        {Pcif, Id, e_Alu, Npc} = 4'b0001;
                        Rf = 0;
                        op_Alu = 0;
                        Mct = 0;
                    end
                    else begin
                        {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} = 6'b00_00_00;
                        {Pcif, Id, e_Alu, Npc} = 4'b0001;
                        Rf = 0;
                        op_Alu = 0;
                        Mct = 0;
                    end
                end
                `bgeu_ : begin
                    if (uNeg == Neg) begin
                        {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} = 6'b00_10_10;
                        {Pcif, Id, e_Alu, Npc} = 4'b0001;
                        Rf = 0;
                        op_Alu = 0;
                        Mct = 0;
                    end
                    else begin
                        {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} = 6'b00_00_00;
                        {Pcif, Id, e_Alu, Npc} = 4'b0001;
                        Rf = 0;
                        op_Alu = 0;
                        Mct = 0;
                    end
                end
                default : begin
                    {C_mux0, C_mux1, C_mux2, C_mux3, C_mux4} = 6'b00_00_00;
                    {Pcif, Id, e_Alu, Npc} = 4'b0001;
                    Rf = 0;
                    op_Alu = 0;
                    Mct = 0;
                end
            endcase
        end
    endcase
end
endmodule