data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_pkg.sv
1: b"%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_pkg.sv:8: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n  import cf_math_pkg::idx_width;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_pkg.sv:129: syntax error, unexpected ::, expecting ',' or ':'\n      riscv_instr::MUL,\n                 ^~\n                                                                                               : ... Perhaps 'riscv_instr' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_pkg.sv:156: syntax error, unexpected endpackage\nendpackage\n^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
function automatic logic shared_offload (logic [31:0] instr);
    logic offload;
    unique casez (instr)
      riscv_instr::MUL,
      riscv_instr::MULH,
      riscv_instr::MULHSU,
      riscv_instr::MULHU,
      riscv_instr::DIV,
      riscv_instr::DIVU,
      riscv_instr::REM,
      riscv_instr::REMU,
      riscv_instr::MULW,
      riscv_instr::DIVW,
      riscv_instr::DIVUW,
      riscv_instr::REMW,
      riscv_instr::REMUW: offload = 1;
      default: offload            = 0;
    endcase
    return offload;
  endfunction
function automatic logic shared_offload (logic [31:0] instr);

    logic offload;
    unique casez (instr)
      riscv_instr::MUL,
      riscv_instr::MULH,
      riscv_instr::MULHSU,
      riscv_instr::MULHU,
      riscv_instr::DIV,
      riscv_instr::DIVU,
      riscv_instr::REM,
      riscv_instr::REMU,
      riscv_instr::MULW,
      riscv_instr::DIVW,
      riscv_instr::DIVUW,
      riscv_instr::REMW,
      riscv_instr::REMUW: offload = 1;
      default: offload            = 0;
    endcase
    return offload;
  endfunction