data/full_repos/permissive/477054115/iitb-risc/registerBank.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/477054115/iitb-risc/registerBank.v:19: Multiple top level modules\n                                                                                   : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                   : ... Top module \'register_n\'\nmodule register_n\n       ^~~~~~~~~~\n                                                                                   : ... Top module \'register_bank\'\nmodule register_bank\n       ^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/477054115/iitb-risc/registerBank.v:39: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS\'s CONST \'127\'h0\' generates 127 bits.\n                                                                                : ... In instance register_bank\n     readData_R7_to_R0 = 127\'b0;\n                       ^\n%Error: Exiting due to 2 warning(s)\n'
module register_n
#(parameter N = 16)
(
	input  [N-1:0] in,
    input clk, reset, enable,
	output reg [N-1:0] out
);

	always @(posedge clk)
    if (reset)
	    out <= {N{1'b0}};
	else if (enable)
	   out <= in;

endmodule
module register_n
#(parameter N = 16)
(
	input  [N-1:0] in,
    input clk, reset, enable,
	output reg [N-1:0] out
);


	always @(posedge clk)
    if (reset)
	    out <= {N{1'b0}};
	else if (enable)
	   out <= in;

endmodule