data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic/mac-tb.v
1: b'%Error: data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic/mac-tb.v:1: Cannot find include file: mac.v\n`include "mac.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic,data/full_repos/permissive/474294847/mac.v\n             data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic,data/full_repos/permissive/474294847/mac.v.v\n             data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic,data/full_repos/permissive/474294847/mac.v.sv\n             mac.v\n             mac.v.v\n             mac.v.sv\n             obj_dir/mac.v\n             obj_dir/mac.v.v\n             obj_dir/mac.v.sv\n%Error: data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic/mac-tb.v:20: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("./build/rtl-sim/vcd/mac.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic/mac-tb.v:21: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic/mac-tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic/mac-tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic/mac-tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n'
module mac_tb;

reg clk, ce;
reg signed [7:0] a, b;
reg signed [7:0] c;
wire signed [15:0] p;

integer i;

mac dut 
(
    clk, ce, a, b, c, p
);
defparam dut.WIDTH = 8;

initial
begin
    $dumpfile("./build/rtl-sim/vcd/mac.vcd");
    $dumpvars;
end

initial
begin
    clk = 0;
    ce = 1;
    a = 15;
    b = -3;
    c = 3;
    i = 0;
    #100;
    for (i = 0; i < 32; i = i + 1)
    begin
        clk = ~clk;
        #100;
        clk = ~clk;
        #100;
    end
end

endmodule
module mac_tb;


reg clk, ce;
reg signed [7:0] a, b;
reg signed [7:0] c;
wire signed [15:0] p;

integer i;

mac dut 
(
    clk, ce, a, b, c, p
);
defparam dut.WIDTH = 8;

initial
begin
    $dumpfile("./build/rtl-sim/vcd/mac.vcd");
    $dumpvars;
end

initial
begin
    clk = 0;
    ce = 1;
    a = 15;
    b = -3;
    c = 3;
    i = 0;
    #100;
    for (i = 0; i < 32; i = i + 1)
    begin
        clk = ~clk;
        #100;
        clk = ~clk;
        #100;
    end
end

endmodule