data/full_repos/permissive/435516446/MIPS/ALU.v
1: b'%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/ALU.v:37: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'result\' generates 32 bits.\n                                                                  : ... In instance ALU\n  zero = result? 0:1;\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/ALU.v:41: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'result\' generates 32 bits.\n                                                                  : ... In instance ALU\n  zero = result? 0:1;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/ALU.v:45: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'result\' generates 32 bits.\n                                                                  : ... In instance ALU\n  zero = result? 0:1;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/ALU.v:49: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'result\' generates 32 bits.\n                                                                  : ... In instance ALU\n  zero = result? 0:1;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/ALU.v:53: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'result\' generates 32 bits.\n                                                                  : ... In instance ALU\n  zero = result? 0:1;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/ALU.v:57: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'result\' generates 32 bits.\n                                                                  : ... In instance ALU\n  zero = result? 0:1;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/ALU.v:61: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'result\' generates 32 bits.\n                                                                  : ... In instance ALU\n  zero = result? 0:1;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/ALU.v:65: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'result\' generates 32 bits.\n                                                                  : ... In instance ALU\n  zero = result? 0:1;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/ALU.v:95: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'result\' generates 32 bits.\n                                                                  : ... In instance ALU\n  zero = result? 0:1;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/ALU.v:100: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'result\' generates 32 bits.\n                                                                   : ... In instance ALU\n  zero = result? 0:1;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/ALU.v:105: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'result\' generates 32 bits.\n                                                                   : ... In instance ALU\n  zero = result? 0:1;\n               ^\n%Error: Exiting due to 11 warning(s)\n'
module ALU(
    input wire [4:0] ALUCnt,
    input wire [31:0] input1,
    input wire [31:0] input2,
    input [4:0] shamt,
    output reg [31:0] result,
    output reg zero
    );
initial begin
	result = 0;
	zero = 1;
end
	 
always @(*) begin
	if(ALUCnt == 0) begin
		result = input1 + input2;
		zero = result? 0:1;
	end
	else if(ALUCnt == 1) begin
		result = input1 - input2;
		zero = result? 0:1;
	end
	else if(ALUCnt == 2) begin
		result = ~input1;
		zero = result? 0:1;
	end
	else if(ALUCnt == 3) begin
		result = input1 << shamt;
		zero = result? 0:1;
	end
	else if(ALUCnt == 4) begin
		result = input1 >> shamt;
		zero = result? 0:1;
	end
	else if(ALUCnt == 5) begin
		result = input1 & input2;
		zero = result? 0:1;
	end
	else if(ALUCnt == 6) begin
		result = input1 | input2;
		zero = result? 0:1;
	end
	else if(ALUCnt == 7) begin
		result = (input1 < input2)? 1: 0;
		zero = result? 0:1;
	end


	else if(ALUCnt == 8) begin
		zero = (input1 == input2)? 1: 0;
	end
	else if(ALUCnt == 9) begin
		zero = (input1 != input2)? 1: 0;
	end
	else if(ALUCnt == 10) begin
		zero = (input1 > input2)? 1: 0;
	end
	else if(ALUCnt == 11) begin
		zero = (input1 >= input2)? 1: 0;
	end
	else if(ALUCnt == 12) begin
		zero = (input1 < input2)? 1: 0;
	end
	else if(ALUCnt == 13) begin
		zero = (input1 <= input2)? 1: 0;
	end

	else if(ALUCnt == 14) begin

		zero = 1;
	end

	else if(ALUCnt == 15) begin
		result = input1 * input2;
		zero = result? 0:1;
	end

	else if(ALUCnt == 16) begin
		result = input1 / input2;
		zero = result? 0:1;
	end

	else if(ALUCnt == 17) begin
		result = input1 >>> input2;
		zero = result? 0:1;
	end


end

endmodule
module ALU(
    input wire [4:0] ALUCnt,
    input wire [31:0] input1,
    input wire [31:0] input2,
    input [4:0] shamt,
    output reg [31:0] result,
    output reg zero
    );

initial begin
	result = 0;
	zero = 1;
end
	 
always @(*) begin
	if(ALUCnt == 0) begin
		result = input1 + input2;
		zero = result? 0:1;
	end
	else if(ALUCnt == 1) begin
		result = input1 - input2;
		zero = result? 0:1;
	end
	else if(ALUCnt == 2) begin
		result = ~input1;
		zero = result? 0:1;
	end
	else if(ALUCnt == 3) begin
		result = input1 << shamt;
		zero = result? 0:1;
	end
	else if(ALUCnt == 4) begin
		result = input1 >> shamt;
		zero = result? 0:1;
	end
	else if(ALUCnt == 5) begin
		result = input1 & input2;
		zero = result? 0:1;
	end
	else if(ALUCnt == 6) begin
		result = input1 | input2;
		zero = result? 0:1;
	end
	else if(ALUCnt == 7) begin
		result = (input1 < input2)? 1: 0;
		zero = result? 0:1;
	end


	else if(ALUCnt == 8) begin
		zero = (input1 == input2)? 1: 0;
	end
	else if(ALUCnt == 9) begin
		zero = (input1 != input2)? 1: 0;
	end
	else if(ALUCnt == 10) begin
		zero = (input1 > input2)? 1: 0;
	end
	else if(ALUCnt == 11) begin
		zero = (input1 >= input2)? 1: 0;
	end
	else if(ALUCnt == 12) begin
		zero = (input1 < input2)? 1: 0;
	end
	else if(ALUCnt == 13) begin
		zero = (input1 <= input2)? 1: 0;
	end

	else if(ALUCnt == 14) begin

		zero = 1;
	end

	else if(ALUCnt == 15) begin
		result = input1 * input2;
		zero = result? 0:1;
	end

	else if(ALUCnt == 16) begin
		result = input1 / input2;
		zero = result? 0:1;
	end

	else if(ALUCnt == 17) begin
		result = input1 >>> input2;
		zero = result? 0:1;
	end


end

endmodule