data/full_repos/permissive/492704601/verilog/dv/bfm/usb_device/core/usb1d_utmi_if.v
1: b'%Error: data/full_repos/permissive/492704601/verilog/dv/bfm/usb_device/core/usb1d_utmi_if.v:59: Cannot find include file: usb1d_defines.v\n`include "usb1d_defines.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/492704601/verilog/dv/bfm/usb_device/core,data/full_repos/permissive/492704601/usb1d_defines.v\n             data/full_repos/permissive/492704601/verilog/dv/bfm/usb_device/core,data/full_repos/permissive/492704601/usb1d_defines.v.v\n             data/full_repos/permissive/492704601/verilog/dv/bfm/usb_device/core,data/full_repos/permissive/492704601/usb1d_defines.v.sv\n             usb1d_defines.v\n             usb1d_defines.v.v\n             usb1d_defines.v.sv\n             obj_dir/usb1d_defines.v\n             obj_dir/usb1d_defines.v.v\n             obj_dir/usb1d_defines.v.sv\n%Error: Exiting due to 1 error(s)\n'
module usb1d_utmi_if(
		phy_clk, rst,
		DataOut, TxValid, TxReady,
		RxValid, RxActive, RxError, DataIn,


		rx_data, rx_valid, rx_active, rx_err,
		tx_data, tx_valid, tx_valid_last, tx_ready,
		tx_first

		);

input		phy_clk;
input		rst;

output	[7:0]	DataOut;
output		TxValid;
input		TxReady;

input	[7:0]	DataIn;
input		RxValid;
input		RxActive;
input		RxError;


output	[7:0]	rx_data;
output		rx_valid, rx_active, rx_err;
input	[7:0]	tx_data;
input		tx_valid;
input		tx_valid_last;
output		tx_ready;
input		tx_first;





reg	[7:0]	rx_data;
reg		rx_valid, rx_active, rx_err;
reg	[7:0]	DataOut;
reg		tx_ready;
reg		TxValid;












always @(posedge phy_clk or negedge rst)
	if(!rst)	rx_valid <= #1 1'b0;
	else		rx_valid <= #1 RxValid;

always @(posedge phy_clk or negedge rst)
	if(!rst)	rx_active <= #1 1'b0;
	else		rx_active <= #1 RxActive;

always @(posedge phy_clk or negedge rst)
	if(!rst)	rx_err <= #1 1'b0;
	else		rx_err <= #1 RxError;

always @(posedge phy_clk)
		rx_data <= #1 DataIn;






always @(posedge phy_clk)
	if(TxReady | tx_first)	DataOut <= #1 tx_data;

always @(posedge phy_clk)
	tx_ready <= #1 TxReady;

always @(posedge phy_clk or negedge rst)
	if(!rst)	TxValid <= #1 1'b0;
	else
	TxValid <= #1 tx_valid | tx_valid_last | (TxValid & !TxReady);

endmodule
module usb1d_utmi_if(
		phy_clk, rst,
		DataOut, TxValid, TxReady,
		RxValid, RxActive, RxError, DataIn,


		rx_data, rx_valid, rx_active, rx_err,
		tx_data, tx_valid, tx_valid_last, tx_ready,
		tx_first

		);


input		phy_clk;
input		rst;

output	[7:0]	DataOut;
output		TxValid;
input		TxReady;

input	[7:0]	DataIn;
input		RxValid;
input		RxActive;
input		RxError;


output	[7:0]	rx_data;
output		rx_valid, rx_active, rx_err;
input	[7:0]	tx_data;
input		tx_valid;
input		tx_valid_last;
output		tx_ready;
input		tx_first;





reg	[7:0]	rx_data;
reg		rx_valid, rx_active, rx_err;
reg	[7:0]	DataOut;
reg		tx_ready;
reg		TxValid;












always @(posedge phy_clk or negedge rst)
	if(!rst)	rx_valid <= #1 1'b0;
	else		rx_valid <= #1 RxValid;

always @(posedge phy_clk or negedge rst)
	if(!rst)	rx_active <= #1 1'b0;
	else		rx_active <= #1 RxActive;

always @(posedge phy_clk or negedge rst)
	if(!rst)	rx_err <= #1 1'b0;
	else		rx_err <= #1 RxError;

always @(posedge phy_clk)
		rx_data <= #1 DataIn;






always @(posedge phy_clk)
	if(TxReady | tx_first)	DataOut <= #1 tx_data;

always @(posedge phy_clk)
	tx_ready <= #1 TxReady;

always @(posedge phy_clk or negedge rst)
	if(!rst)	TxValid <= #1 1'b0;
	else
	TxValid <= #1 tx_valid | tx_valid_last | (TxValid & !TxReady);

endmodule