data/full_repos/permissive/431863558/combinational-circuits/basic-arithmetic/t_ripple_carry_adder.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/431863558/combinational-circuits/basic-arithmetic/t_ripple_carry_adder.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #10 x = x + 4\'b0001;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/431863558/combinational-circuits/basic-arithmetic/t_ripple_carry_adder.v:33: Unsupported: Ignoring delay on this delayed statement.\n   #10 y = y + 4\'b0001;\n   ^\n%Error: data/full_repos/permissive/431863558/combinational-circuits/basic-arithmetic/t_ripple_carry_adder.v:39: Unsupported or unknown PLI call: $monitor\n $monitor("x = %d y = %d c = %d S = %d C = %d", x, y, c, S, C);\n ^~~~~~~~\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module t_ripple_carry_adder ;

reg [3:0] x, y;
reg c;
wire [3:0] S;
wire C;

integer i, j;

ripple_carry_adder DUT  ( .S(S),
						.C(C),
						.x(x),
						.y(y),
						.c(c));

initial begin

	c = 1'b0;
	x = 4'b0000;
	y = 4'b0000;
	for (i=0; i<15; i++) begin
		#10 x = x + 4'b0001;
		for (j=0; j<15; j++) begin
			#10 y = y + 4'b0001;
		end
	end
end

initial 
	$monitor("x = %d y = %d c = %d S = %d C = %d", x, y, c, S, C);

endmodule
module t_ripple_carry_adder ;


reg [3:0] x, y;
reg c;
wire [3:0] S;
wire C;

integer i, j;

ripple_carry_adder DUT  ( .S(S),
						.C(C),
						.x(x),
						.y(y),
						.c(c));

initial begin

	c = 1'b0;
	x = 4'b0000;
	y = 4'b0000;
	for (i=0; i<15; i++) begin
		#10 x = x + 4'b0001;
		for (j=0; j<15; j++) begin
			#10 y = y + 4'b0001;
		end
	end
end

initial 
	$monitor("x = %d y = %d c = %d S = %d C = %d", x, y, c, S, C);

endmodule