data/full_repos/permissive/423216833/Introduction to Verilog Programming/1607021/alu_1607021.v
1: b'%Error: Cannot find file containing module: to\n        ... Looked in:\n             data/full_repos/permissive/423216833/Introduction/to\n             data/full_repos/permissive/423216833/Introduction/to.v\n             data/full_repos/permissive/423216833/Introduction/to.sv\n             to\n             to.v\n             to.sv\n             obj_dir/to\n             obj_dir/to.v\n             obj_dir/to.sv\n%Error: Cannot find file containing module: Verilog\n%Error: Cannot find file containing module: Programming/1607021,data/full_repos/permissive/423216833\n%Error: Cannot find file containing module: data/full_repos/permissive/423216833/Introduction\n%Error: Cannot find file containing module: Programming/1607021/alu_1607021.v\n%Error: Exiting due to 5 error(s)\n'
module alu(
           input [15:0] A,B,                 
           input [3:0] ALU_Sel,
           output [15:0] ALU_Out,
           output CarryOut,
	   input clk,
	   input reset
    );
    reg q;
    reg [15:0] ALU_Result;
    wire [16:0] tmp;

    assign ALU_Out = ALU_Result;
    assign tmp = {1'b0,A} + {1'b0,B};
    assign CarryOut = tmp[16];

    always @(*)
    begin
        case(ALU_Sel)
        4'b0000:
           ALU_Result = A + B ; 

        4'b0001:
           ALU_Result = A - B ;

        4'b0010:
           ALU_Result = A * B;

        4'b0011:
           ALU_Result = A/B;

        4'b0100:
           ALU_Result = B<<1;

         4'b0101:
           ALU_Result = B>>1;

         4'b0110:
           ALU_Result = {B[14:0],B[15]};

         4'b0111:
           ALU_Result = {A[0],A[15:1]};

         4'b1000:
           ALU_Result = A & B;

          4'b1001:
           ALU_Result = A | B;

          4'b1010:
           ALU_Result = A ^ B;

          4'b1011:
           ALU_Result = ~(A | B);

          4'b1100:
           ALU_Result = ~(A & B);

          4'b1101:
           ALU_Result = ~(A ^ B);

          4'b1110:
           ALU_Result = (A>B)?16'd1:16'd0 ;

          4'b1111:
            ALU_Result = (A==B)?16'd1:16'd0 ;

          default: ALU_Result = A + B ; 
        endcase
    end

    always @ (posedge clk)
    if (reset==1)
      begin
       q <= 1'b0;
      end else if(reset==0) begin
       q <= ALU_Result;
      end

endmodule
module alu(
           input [15:0] A,B,                 
           input [3:0] ALU_Sel,
           output [15:0] ALU_Out,
           output CarryOut,
	   input clk,
	   input reset
    );

    reg q;
    reg [15:0] ALU_Result;
    wire [16:0] tmp;

    assign ALU_Out = ALU_Result;
    assign tmp = {1'b0,A} + {1'b0,B};
    assign CarryOut = tmp[16];

    always @(*)
    begin
        case(ALU_Sel)
        4'b0000:
           ALU_Result = A + B ; 

        4'b0001:
           ALU_Result = A - B ;

        4'b0010:
           ALU_Result = A * B;

        4'b0011:
           ALU_Result = A/B;

        4'b0100:
           ALU_Result = B<<1;

         4'b0101:
           ALU_Result = B>>1;

         4'b0110:
           ALU_Result = {B[14:0],B[15]};

         4'b0111:
           ALU_Result = {A[0],A[15:1]};

         4'b1000:
           ALU_Result = A & B;

          4'b1001:
           ALU_Result = A | B;

          4'b1010:
           ALU_Result = A ^ B;

          4'b1011:
           ALU_Result = ~(A | B);

          4'b1100:
           ALU_Result = ~(A & B);

          4'b1101:
           ALU_Result = ~(A ^ B);

          4'b1110:
           ALU_Result = (A>B)?16'd1:16'd0 ;

          4'b1111:
            ALU_Result = (A==B)?16'd1:16'd0 ;

          default: ALU_Result = A + B ; 
        endcase
    end

    always @ (posedge clk)
    if (reset==1)
      begin
       q <= 1'b0;
      end else if(reset==0) begin
       q <= ALU_Result;
      end

endmodule