data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/tb/support/bytewrite_ram_wrap.v
1: b'%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/tb/support/bytewrite_ram_wrap.v:4: Cannot find include file: jedro_1_defines.v\n`include "jedro_1_defines.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/tb/support,data/full_repos/permissive/522553437/jedro_1_defines.v\n             data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/tb/support,data/full_repos/permissive/522553437/jedro_1_defines.v.v\n             data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/tb/support,data/full_repos/permissive/522553437/jedro_1_defines.v.sv\n             jedro_1_defines.v\n             jedro_1_defines.v.v\n             jedro_1_defines.v.sv\n             obj_dir/jedro_1_defines.v\n             obj_dir/jedro_1_defines.v.v\n             obj_dir/jedro_1_defines.v.sv\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/tb/support/bytewrite_ram_wrap.v:17: Define or directive not defined: \'`DATA_WIDTH\'\n  output [`DATA_WIDTH-1:0] rdata,\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/tb/support/bytewrite_ram_wrap.v:22: Define or directive not defined: \'`DATA_WIDTH\'\n  input  [`DATA_WIDTH-1:0] addr,\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/tb/support/bytewrite_ram_wrap.v:23: Define or directive not defined: \'`DATA_WIDTH\'\n  input  [`DATA_WIDTH-1:0] wdata\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/tb/support/bytewrite_ram_wrap.v:31: Define or directive not defined: \'`DATA_WIDTH\'\n                                                              .di(wdata[`DATA_WIDTH-1:0]), \n                                                                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/tb/support/bytewrite_ram_wrap.v:32: Define or directive not defined: \'`DATA_WIDTH\'\n                                                              .dout(rdata[`DATA_WIDTH-1:0]));\n                                                                          ^~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n'
module bytewrite_ram_wrap
#(
    parameter MEM_INIT_FILE="",
    parameter INIT_FILE_BIN=1,
    parameter MEM_SIZE_WORDS=2**12
)
(
  input clk_i,
  input rstn_i,
  

  output [`DATA_WIDTH-1:0] rdata,
  output reg               ack,
  output                   err,
  input  [3:0]             we,
  input                    stb,
  input  [`DATA_WIDTH-1:0] addr,
  input  [`DATA_WIDTH-1:0] wdata
);

  bytewrite_ram_1b #(.SIZE(MEM_SIZE_WORDS),
                     .INIT_FILE_BIN(INIT_FILE_BIN),
                     .MEM_INIT_FILE(MEM_INIT_FILE)) data_ram (.clk(clk_i), 
                                                              .we(we[3:0]), 
                                                              .addr(addr[$clog2(MEM_SIZE_WORDS*4)-1:0]), 
                                                              .di(wdata[`DATA_WIDTH-1:0]), 
                                                              .dout(rdata[`DATA_WIDTH-1:0]));

  assign err = 0;

  always @(posedge clk_i) begin
    if (rstn_i == 1'b0) ack <= 0;
    else                ack <= stb;
  end
  
endmodule
module bytewrite_ram_wrap
#(
    parameter MEM_INIT_FILE="",
    parameter INIT_FILE_BIN=1,
    parameter MEM_SIZE_WORDS=2**12
)
(
  input clk_i,
  input rstn_i,
  

  output [`DATA_WIDTH-1:0] rdata,
  output reg               ack,
  output                   err,
  input  [3:0]             we,
  input                    stb,
  input  [`DATA_WIDTH-1:0] addr,
  input  [`DATA_WIDTH-1:0] wdata
);


  bytewrite_ram_1b #(.SIZE(MEM_SIZE_WORDS),
                     .INIT_FILE_BIN(INIT_FILE_BIN),
                     .MEM_INIT_FILE(MEM_INIT_FILE)) data_ram (.clk(clk_i), 
                                                              .we(we[3:0]), 
                                                              .addr(addr[$clog2(MEM_SIZE_WORDS*4)-1:0]), 
                                                              .di(wdata[`DATA_WIDTH-1:0]), 
                                                              .dout(rdata[`DATA_WIDTH-1:0]));

  assign err = 0;

  always @(posedge clk_i) begin
    if (rstn_i == 1'b0) ack <= 0;
    else                ack <= stb;
  end
  
endmodule