data/full_repos/permissive/494490807/bench/ISCAS/Verilog/DFF2.v
data/verilator_xmls/73e749bd-15c1-4a83-94b9-451fada70024.xml
module DFF (Q, D, CK);
input   D, CK;
output  Q;
reg     Q;


always @(posedge CK) Q <= D;
endmodule
module DFF (Q, D, CK);

input   D, CK;
output  Q;
reg     Q;


always @(posedge CK) Q <= D;
endmodule