data/full_repos/permissive/476296842/rtl/core/id.v
1: b'%Error: data/full_repos/permissive/476296842/rtl/core/id.v:8: Cannot find include file: rtl/core/define.v\n`include "rtl/core/define.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/476296842/rtl/core,data/full_repos/permissive/476296842/rtl/core/define.v\n             data/full_repos/permissive/476296842/rtl/core,data/full_repos/permissive/476296842/rtl/core/define.v.v\n             data/full_repos/permissive/476296842/rtl/core,data/full_repos/permissive/476296842/rtl/core/define.v.sv\n             rtl/core/define.v\n             rtl/core/define.v.v\n             rtl/core/define.v.sv\n             obj_dir/rtl/core/define.v\n             obj_dir/rtl/core/define.v.v\n             obj_dir/rtl/core/define.v.sv\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:13: Define or directive not defined: \'`inst_bus\'\n    input wire [`inst_bus]              inst_i,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:13: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire [`inst_bus]              inst_i,\n                         ^\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:14: Define or directive not defined: \'`inst_addr_bus\'\n    input wire [`inst_addr_bus]         inst_addr_i,\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:17: Define or directive not defined: \'`reg_data_bus\'\n    input wire [`reg_data_bus]          r_reg_data_1_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:18: Define or directive not defined: \'`reg_data_bus\'\n    input wire [`reg_data_bus]          r_reg_data_2_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:19: Define or directive not defined: \'`reg_addr_bus\'\n    output reg [`reg_addr_bus]          r_reg_addr_1_o,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:20: Define or directive not defined: \'`reg_addr_bus\'\n    output reg [`reg_addr_bus]          r_reg_addr_2_o,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:22: Define or directive not defined: \'`csr_data_bus\'\n    input wire [`csr_data_bus]          r_csr_data_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:23: Define or directive not defined: \'`csr_addr_bus\'\n    output reg [`csr_addr_bus]          r_csr_addr_o,                   \n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:26: Define or directive not defined: \'`reg_data_bus\'\n    output wire [`reg_data_bus]         r_reg_data_1_o,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:27: Define or directive not defined: \'`reg_data_bus\'\n    output wire [`reg_data_bus]         r_reg_data_2_o,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:28: Define or directive not defined: \'`imm_data_bus\'\n    output reg [`imm_data_bus]          imm_data_o,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:29: Define or directive not defined: \'`csr_data_bus\'\n    output wire [`csr_data_bus]         r_csr_data_o,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:30: Define or directive not defined: \'`inst_addr_bus\'\n    output reg [`inst_addr_bus]         r_pc_data_o,\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:33: Define or directive not defined: \'`alu_inst_bus\'\n    output reg [`alu_inst_bus]          alu_inst_o,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:36: Define or directive not defined: \'`inst_bus\'\n    output reg [`inst_bus]              r_inst_o,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:39: Define or directive not defined: \'`reg_addr_bus\'\n    output reg [`reg_addr_bus]          w_reg_addr_o,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:40: Define or directive not defined: \'`csr_addr_bus\'\n    output reg [`csr_addr_bus]          w_csr_addr_o,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:43: Define or directive not defined: \'`data_type_bus\'\n    output reg [`data_type_bus]         data_type_o\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:59: syntax error, unexpected assign\n    assign r_reg_data_1_o = r_reg_data_1_i;\n    ^~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:64: Define or directive not defined: \'`reg_zero\'\n        r_reg_addr_1_o = `reg_zero;\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:65: Define or directive not defined: \'`reg_zero\'\n        r_reg_addr_2_o = `reg_zero;\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:66: Define or directive not defined: \'`csr_zero\'\n        r_csr_addr_o = `csr_zero;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:67: Define or directive not defined: \'`data_zero\'\n        imm_data_o = `data_zero;\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:69: Define or directive not defined: \'`alu_no\'\n        alu_inst_o = `alu_no;\n                     ^~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:71: Define or directive not defined: \'`reg_zero\'\n        w_reg_addr_o = `reg_zero;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:72: Define or directive not defined: \'`csr_zero\'\n        w_csr_addr_o = `csr_zero;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:73: Define or directive not defined: \'`datatype_no\'\n        data_type_o = `datatype_no;\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:76: Define or directive not defined: \'`inst_r\'\n            `inst_r: begin\n            ^~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:80: Define or directive not defined: \'`datatype_word\'\n                data_type_o = `datatype_word;\n                              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:82: Define or directive not defined: \'`inst_add_sub\'\n                    `inst_add_sub: begin\n                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:85: Define or directive not defined: \'`alu_add\'\n                            alu_inst_o = `alu_add;\n                                         ^~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:88: Define or directive not defined: \'`alu_sub\'\n                            alu_inst_o = `alu_sub;\n                                         ^~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:91: Define or directive not defined: \'`inst_xor\'\n                    `inst_xor: alu_inst_o = `alu_xor;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:91: Define or directive not defined: \'`alu_xor\'\n                    `inst_xor: alu_inst_o = `alu_xor;\n                                            ^~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:92: Define or directive not defined: \'`inst_or\'\n                    `inst_or: alu_inst_o = `alu_or;\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:92: Define or directive not defined: \'`alu_or\'\n                    `inst_or: alu_inst_o = `alu_or;\n                                           ^~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:93: Define or directive not defined: \'`inst_and\'\n                    `inst_and: alu_inst_o = `alu_and;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:93: Define or directive not defined: \'`alu_and\'\n                    `inst_and: alu_inst_o = `alu_and;\n                                            ^~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:94: Define or directive not defined: \'`inst_sll\'\n                    `inst_sll: alu_inst_o = `alu_ll;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:94: Define or directive not defined: \'`alu_ll\'\n                    `inst_sll: alu_inst_o = `alu_ll;\n                                            ^~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:95: Define or directive not defined: \'`inst_srl_sra\'\n                    `inst_srl_sra: begin\n                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:98: Define or directive not defined: \'`alu_rl\'\n                            alu_inst_o = `alu_rl;\n                                         ^~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:101: Define or directive not defined: \'`alu_arl\'\n                            alu_inst_o = `alu_arl;\n                                         ^~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:104: Define or directive not defined: \'`inst_slt\'\n                    `inst_slt: alu_inst_o = `alu_cmp_less;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:104: Define or directive not defined: \'`alu_cmp_less\'\n                    `inst_slt: alu_inst_o = `alu_cmp_less;\n                                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:105: Define or directive not defined: \'`inst_sltu\'\n                    `inst_sltu: alu_inst_o = `alu_cmp_lessu;\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:105: Define or directive not defined: \'`alu_cmp_lessu\'\n                    `inst_sltu: alu_inst_o = `alu_cmp_lessu;\n                                             ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id.v:106: Define or directive not defined: \'`alu_no\'\n                    default: alu_inst_o = `alu_no;\n                                          ^~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module id (

    input wire [`inst_bus]              inst_i,
    input wire [`inst_addr_bus]         inst_addr_i,


    input wire [`reg_data_bus]          r_reg_data_1_i,
    input wire [`reg_data_bus]          r_reg_data_2_i,
    output reg [`reg_addr_bus]          r_reg_addr_1_o,
    output reg [`reg_addr_bus]          r_reg_addr_2_o,

    input wire [`csr_data_bus]          r_csr_data_i,
    output reg [`csr_addr_bus]          r_csr_addr_o,                   


    output wire [`reg_data_bus]         r_reg_data_1_o,
    output wire [`reg_data_bus]         r_reg_data_2_o,
    output reg [`imm_data_bus]          imm_data_o,
    output wire [`csr_data_bus]         r_csr_data_o,
    output reg [`inst_addr_bus]         r_pc_data_o,
    

    output reg [`alu_inst_bus]          alu_inst_o,
    

    output reg [`inst_bus]              r_inst_o,


    output reg [`reg_addr_bus]          w_reg_addr_o,
    output reg [`csr_addr_bus]          w_csr_addr_o,


    output reg [`data_type_bus]         data_type_o
);

    wire [6:0] opcode = inst_i[6:0];
    wire [2:0] func3 = inst_i[14:12];
    wire [6:0] func7 = inst_i[31:25];
    wire [11:0] imm_i = inst_i[31:20];
    wire [11:0] imm_l = imm_i;
    wire [11:0] imm_s = {inst_i[31:25], inst_i[11:7]};
    wire [12:0] imm_b = {inst_i[31], inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
    wire [19:0] imm_u = inst_i[31:12];
    wire [20:0] imm_j = {inst_i[31], inst_i[19:12], inst_i[20], inst_i[30:21], 1'b0};
    wire [4:0] rs1 = inst_i[19:15];
    wire [4:0] rs2 = inst_i[24:20];
    wire [4:0] rd = inst_i[11:7];

    assign r_reg_data_1_o = r_reg_data_1_i;
    assign r_reg_data_2_o = r_reg_data_2_i;
    assign r_csr_data_o = r_csr_data_i;

    always @(*) begin
        r_reg_addr_1_o = `reg_zero;
        r_reg_addr_2_o = `reg_zero;
        r_csr_addr_o = `csr_zero;
        imm_data_o = `data_zero;
        r_pc_data_o = inst_addr_i;
        alu_inst_o = `alu_no;
        r_inst_o = inst_i;
        w_reg_addr_o = `reg_zero;
        w_csr_addr_o = `csr_zero;
        data_type_o = `datatype_no;

        case (opcode)
            `inst_r: begin
                r_reg_addr_1_o = rs1;
                r_reg_addr_2_o = rs2;
                w_reg_addr_o = rd;
                data_type_o = `datatype_word;
                case (func3)
                    `inst_add_sub: begin
                        if (func7 == 7'h00) begin

                            alu_inst_o = `alu_add;
                        end else begin

                            alu_inst_o = `alu_sub;
                        end
                    end
                    `inst_xor: alu_inst_o = `alu_xor;
                    `inst_or: alu_inst_o = `alu_or;
                    `inst_and: alu_inst_o = `alu_and;
                    `inst_sll: alu_inst_o = `alu_ll;
                    `inst_srl_sra: begin
                        if (func7 == 7'h00) begin

                            alu_inst_o = `alu_rl;
                        end else begin

                            alu_inst_o = `alu_arl;
                        end
                    end
                    `inst_slt: alu_inst_o = `alu_cmp_less;
                    `inst_sltu: alu_inst_o = `alu_cmp_lessu;
                    default: alu_inst_o = `alu_no;
                endcase
            end
            `inst_i: begin
                r_reg_addr_1_o = rs1;
                imm_data_o = $signed(imm_i);
                w_reg_addr_o = rd;
                data_type_o = `datatype_word;
                case (func3)
                    `inst_addi: alu_inst_o = `alu_add;
                    `inst_xori: alu_inst_o = `alu_xor;
                    `inst_ori: alu_inst_o = `alu_or;
                    `inst_andi: alu_inst_o = `alu_and;
                    `inst_slli: alu_inst_o = `alu_ll;
                    `inst_srli_srai: begin
                        if (imm_i[11: 5] == 7'h00) begin

                            alu_inst_o = `alu_rl;
                        end else begin

                            alu_inst_o = `alu_arl;
                        end
                    end
                    `inst_slti: alu_inst_o = `alu_cmp_less;
                    `inst_sltiu: alu_inst_o = `alu_cmp_lessu;
                    default: alu_inst_o = `alu_no;
                endcase
            end
            `inst_b: begin
                r_reg_addr_1_o = rs1;
                r_reg_addr_2_o = rs2;
                imm_data_o = $signed(imm_b);
                case (func3)
                    `inst_beq: alu_inst_o = `alu_cmp_eq;
                    `inst_bne: alu_inst_o = `alu_cmp_neq;
                    `inst_blt: alu_inst_o = `alu_cmp_less;
                    `inst_bge: alu_inst_o = `alu_cmp_more_eq;
                    `inst_bltu: alu_inst_o = `alu_cmp_lessu;
                    `inst_bgeu: alu_inst_o = `alu_cmp_more_equ;
                    default: alu_inst_o = `alu_no;
                endcase
            end
            `inst_l: begin
                r_reg_addr_1_o = rs1;
                imm_data_o = $signed(imm_l);
                w_reg_addr_o = rd;
                alu_inst_o = `alu_add;
                case (func3)
                    `inst_lb: data_type_o = `datatype_byte;
                    `inst_lh: data_type_o = `datatype_half;
                    `inst_lw: data_type_o = `datatype_word;
                    `inst_lbu: data_type_o = `datatype_ubyte;
                    `inst_lhu: data_type_o = `datatype_uhalf;
                    default: data_type_o = `datatype_no;
                endcase
            end
            `inst_s: begin
                r_reg_addr_1_o = rs1;
                r_reg_addr_2_o = rs2;
                imm_data_o = $signed(imm_s);
                alu_inst_o = `alu_add;
                case (func3)
                    `inst_sb: data_type_o = `datatype_byte;
                    `inst_sh: data_type_o = `datatype_half;
                    `inst_sw: data_type_o = `datatype_word;
                    default: data_type_o = `datatype_no;
                endcase
            end
            `inst_jal: begin
                imm_data_o = $signed(imm_j);
                w_reg_addr_o = rd;
                alu_inst_o = `alu_add;
            end
            `inst_jalr: begin
                imm_data_o = $signed(imm_i);
                r_reg_addr_1_o = rs1;
                w_reg_addr_o = rd;
                alu_inst_o = `alu_add;
            end
            `inst_lui: begin
                alu_inst_o = `alu_add;
                w_reg_addr_o = rd;
                imm_data_o = $signed(imm_u);
            end
            `inst_auipc: begin
                alu_inst_o = `alu_add;
                w_reg_addr_o = rd;
                imm_data_o = $signed(imm_u);
            end
            default: begin
                
            end 
        endcase

    end

endmodule
module id (

    input wire [`inst_bus]              inst_i,
    input wire [`inst_addr_bus]         inst_addr_i,


    input wire [`reg_data_bus]          r_reg_data_1_i,
    input wire [`reg_data_bus]          r_reg_data_2_i,
    output reg [`reg_addr_bus]          r_reg_addr_1_o,
    output reg [`reg_addr_bus]          r_reg_addr_2_o,

    input wire [`csr_data_bus]          r_csr_data_i,
    output reg [`csr_addr_bus]          r_csr_addr_o,                   


    output wire [`reg_data_bus]         r_reg_data_1_o,
    output wire [`reg_data_bus]         r_reg_data_2_o,
    output reg [`imm_data_bus]          imm_data_o,
    output wire [`csr_data_bus]         r_csr_data_o,
    output reg [`inst_addr_bus]         r_pc_data_o,
    

    output reg [`alu_inst_bus]          alu_inst_o,
    

    output reg [`inst_bus]              r_inst_o,


    output reg [`reg_addr_bus]          w_reg_addr_o,
    output reg [`csr_addr_bus]          w_csr_addr_o,


    output reg [`data_type_bus]         data_type_o
);


    wire [6:0] opcode = inst_i[6:0];
    wire [2:0] func3 = inst_i[14:12];
    wire [6:0] func7 = inst_i[31:25];
    wire [11:0] imm_i = inst_i[31:20];
    wire [11:0] imm_l = imm_i;
    wire [11:0] imm_s = {inst_i[31:25], inst_i[11:7]};
    wire [12:0] imm_b = {inst_i[31], inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
    wire [19:0] imm_u = inst_i[31:12];
    wire [20:0] imm_j = {inst_i[31], inst_i[19:12], inst_i[20], inst_i[30:21], 1'b0};
    wire [4:0] rs1 = inst_i[19:15];
    wire [4:0] rs2 = inst_i[24:20];
    wire [4:0] rd = inst_i[11:7];

    assign r_reg_data_1_o = r_reg_data_1_i;
    assign r_reg_data_2_o = r_reg_data_2_i;
    assign r_csr_data_o = r_csr_data_i;

    always @(*) begin
        r_reg_addr_1_o = `reg_zero;
        r_reg_addr_2_o = `reg_zero;
        r_csr_addr_o = `csr_zero;
        imm_data_o = `data_zero;
        r_pc_data_o = inst_addr_i;
        alu_inst_o = `alu_no;
        r_inst_o = inst_i;
        w_reg_addr_o = `reg_zero;
        w_csr_addr_o = `csr_zero;
        data_type_o = `datatype_no;

        case (opcode)
            `inst_r: begin
                r_reg_addr_1_o = rs1;
                r_reg_addr_2_o = rs2;
                w_reg_addr_o = rd;
                data_type_o = `datatype_word;
                case (func3)
                    `inst_add_sub: begin
                        if (func7 == 7'h00) begin

                            alu_inst_o = `alu_add;
                        end else begin

                            alu_inst_o = `alu_sub;
                        end
                    end
                    `inst_xor: alu_inst_o = `alu_xor;
                    `inst_or: alu_inst_o = `alu_or;
                    `inst_and: alu_inst_o = `alu_and;
                    `inst_sll: alu_inst_o = `alu_ll;
                    `inst_srl_sra: begin
                        if (func7 == 7'h00) begin

                            alu_inst_o = `alu_rl;
                        end else begin

                            alu_inst_o = `alu_arl;
                        end
                    end
                    `inst_slt: alu_inst_o = `alu_cmp_less;
                    `inst_sltu: alu_inst_o = `alu_cmp_lessu;
                    default: alu_inst_o = `alu_no;
                endcase
            end
            `inst_i: begin
                r_reg_addr_1_o = rs1;
                imm_data_o = $signed(imm_i);
                w_reg_addr_o = rd;
                data_type_o = `datatype_word;
                case (func3)
                    `inst_addi: alu_inst_o = `alu_add;
                    `inst_xori: alu_inst_o = `alu_xor;
                    `inst_ori: alu_inst_o = `alu_or;
                    `inst_andi: alu_inst_o = `alu_and;
                    `inst_slli: alu_inst_o = `alu_ll;
                    `inst_srli_srai: begin
                        if (imm_i[11: 5] == 7'h00) begin

                            alu_inst_o = `alu_rl;
                        end else begin

                            alu_inst_o = `alu_arl;
                        end
                    end
                    `inst_slti: alu_inst_o = `alu_cmp_less;
                    `inst_sltiu: alu_inst_o = `alu_cmp_lessu;
                    default: alu_inst_o = `alu_no;
                endcase
            end
            `inst_b: begin
                r_reg_addr_1_o = rs1;
                r_reg_addr_2_o = rs2;
                imm_data_o = $signed(imm_b);
                case (func3)
                    `inst_beq: alu_inst_o = `alu_cmp_eq;
                    `inst_bne: alu_inst_o = `alu_cmp_neq;
                    `inst_blt: alu_inst_o = `alu_cmp_less;
                    `inst_bge: alu_inst_o = `alu_cmp_more_eq;
                    `inst_bltu: alu_inst_o = `alu_cmp_lessu;
                    `inst_bgeu: alu_inst_o = `alu_cmp_more_equ;
                    default: alu_inst_o = `alu_no;
                endcase
            end
            `inst_l: begin
                r_reg_addr_1_o = rs1;
                imm_data_o = $signed(imm_l);
                w_reg_addr_o = rd;
                alu_inst_o = `alu_add;
                case (func3)
                    `inst_lb: data_type_o = `datatype_byte;
                    `inst_lh: data_type_o = `datatype_half;
                    `inst_lw: data_type_o = `datatype_word;
                    `inst_lbu: data_type_o = `datatype_ubyte;
                    `inst_lhu: data_type_o = `datatype_uhalf;
                    default: data_type_o = `datatype_no;
                endcase
            end
            `inst_s: begin
                r_reg_addr_1_o = rs1;
                r_reg_addr_2_o = rs2;
                imm_data_o = $signed(imm_s);
                alu_inst_o = `alu_add;
                case (func3)
                    `inst_sb: data_type_o = `datatype_byte;
                    `inst_sh: data_type_o = `datatype_half;
                    `inst_sw: data_type_o = `datatype_word;
                    default: data_type_o = `datatype_no;
                endcase
            end
            `inst_jal: begin
                imm_data_o = $signed(imm_j);
                w_reg_addr_o = rd;
                alu_inst_o = `alu_add;
            end
            `inst_jalr: begin
                imm_data_o = $signed(imm_i);
                r_reg_addr_1_o = rs1;
                w_reg_addr_o = rd;
                alu_inst_o = `alu_add;
            end
            `inst_lui: begin
                alu_inst_o = `alu_add;
                w_reg_addr_o = rd;
                imm_data_o = $signed(imm_u);
            end
            `inst_auipc: begin
                alu_inst_o = `alu_add;
                w_reg_addr_o = rd;
                imm_data_o = $signed(imm_u);
            end
            default: begin
                
            end 
        endcase

    end

endmodule