data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/ext_fifo.v
1: b"%Error: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/ext_fifo.v:50: Cannot find file containing module: 'dpram'\n   dpram #(.depth(10),.width(width),.size(1024))\n   ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib,data/full_repos/permissive/447976230/dpram\n             data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib,data/full_repos/permissive/447976230/dpram.v\n             data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib,data/full_repos/permissive/447976230/dpram.sv\n             dpram\n             dpram.v\n             dpram.sv\n             obj_dir/dpram\n             obj_dir/dpram.v\n             obj_dir/dpram.sv\n%Error: Exiting due to 1 error(s)\n"
module fifo (reset,data,write,wrclk,wr_used,q,read_ack,rdclk,rd_used);
   parameter width=32;
   parameter depth=10;

   input reset;
   input [width-1:0] data;
   input write;
   input wrclk;
   output [depth-1:0] wr_used;
   output [width-1:0] q;
   input read_ack;
   input rdclk;
   output [depth-1:0] rd_used;

   reg [depth-1:0] read_addr, write_addr, 
		   read_addr_gray, read_addr_gray_sync,
		   write_addr_gray, write_addr_gray_sync;


   dpram #(.depth(10),.width(width),.size(1024))
         fifo_ram (.wclk(wrclk),.wdata(data),.waddr(write_addr),.wen(write),
		   .rclk(rdclk), .rdata(q),.raddr(read_addr) );

   wire [depth-1:0] wag,rag;


   always @(posedge wrclk or posedge reset)
     if(reset) write_addr <= #1 0;
     else if(write) write_addr <= #1 write_addr + 1;

   always @(posedge rdclk or posedge reset)
     if(reset) read_addr <= #1 0;
     else if(read_ack) read_addr <= #1 read_addr + 1;


   bin2gray #(depth) write_b2g (write_addr,wag);
   bin2gray #(depth) read_b2g (read_addr,rag);


   always @(posedge wrclk or posedge reset)
     if(reset) write_addr_gray <= #1 0;
     else write_addr_gray <= #1 wag;

   always @(posedge rdclk or posedge reset)
     if(reset) read_addr_gray <= #1 0;
     else read_addr_gray <= #1 rag;


   always @(posedge wrclk or posedge reset)
     if(reset) read_addr_gray_sync <= #1 0;
     else read_addr_gray_sync <= #1 read_addr_gray;

   always @(posedge rdclk or posedge reset)
     if(reset) write_addr_gray_sync <= #1 0;
     else write_addr_gray_sync <= #1 write_addr_gray;

   wire [depth-1:0] write_addr_sync, read_addr_sync;
   

   gray2bin #(depth) write_g2b (write_addr_gray_sync, write_addr_sync);
   gray2bin #(depth) read_g2b (read_addr_gray_sync, read_addr_sync);
 
   assign rd_used = write_addr_sync - read_addr;
   assign wr_used = write_addr - read_addr_sync;
   		  
endmodule
module fifo (reset,data,write,wrclk,wr_used,q,read_ack,rdclk,rd_used);

   parameter width=32;
   parameter depth=10;

   input reset;
   input [width-1:0] data;
   input write;
   input wrclk;
   output [depth-1:0] wr_used;
   output [width-1:0] q;
   input read_ack;
   input rdclk;
   output [depth-1:0] rd_used;

   reg [depth-1:0] read_addr, write_addr, 
		   read_addr_gray, read_addr_gray_sync,
		   write_addr_gray, write_addr_gray_sync;


   dpram #(.depth(10),.width(width),.size(1024))
         fifo_ram (.wclk(wrclk),.wdata(data),.waddr(write_addr),.wen(write),
		   .rclk(rdclk), .rdata(q),.raddr(read_addr) );

   wire [depth-1:0] wag,rag;


   always @(posedge wrclk or posedge reset)
     if(reset) write_addr <= #1 0;
     else if(write) write_addr <= #1 write_addr + 1;

   always @(posedge rdclk or posedge reset)
     if(reset) read_addr <= #1 0;
     else if(read_ack) read_addr <= #1 read_addr + 1;


   bin2gray #(depth) write_b2g (write_addr,wag);
   bin2gray #(depth) read_b2g (read_addr,rag);


   always @(posedge wrclk or posedge reset)
     if(reset) write_addr_gray <= #1 0;
     else write_addr_gray <= #1 wag;

   always @(posedge rdclk or posedge reset)
     if(reset) read_addr_gray <= #1 0;
     else read_addr_gray <= #1 rag;


   always @(posedge wrclk or posedge reset)
     if(reset) read_addr_gray_sync <= #1 0;
     else read_addr_gray_sync <= #1 read_addr_gray;

   always @(posedge rdclk or posedge reset)
     if(reset) write_addr_gray_sync <= #1 0;
     else write_addr_gray_sync <= #1 write_addr_gray;

   wire [depth-1:0] write_addr_sync, read_addr_sync;
   

   gray2bin #(depth) write_g2b (write_addr_gray_sync, write_addr_sync);
   gray2bin #(depth) read_g2b (read_addr_gray_sync, read_addr_sync);
 
   assign rd_used = write_addr_sync - read_addr;
   assign wr_used = write_addr - read_addr_sync;
   		  
endmodule