data/full_repos/permissive/513398397/verilog/control.v
data/verilator_xmls/7a31be84-8ae8-4bd5-bc7a-7af51a7eacad.xml
module enc3b(
    output [2:0] enc_o,
    input  [4:0] enc_i
);

assign enc_o[0] = enc_i[3] | enc_i[1] | enc_i[0];
assign enc_o[1] = enc_i[3] | enc_i[2] | enc_i[0];
assign enc_o[2] = enc_i[4] | enc_i[0];

endmodule
module enc3b(
    output [2:0] enc_o,
    input  [4:0] enc_i
);


assign enc_o[0] = enc_i[3] | enc_i[1] | enc_i[0];
assign enc_o[1] = enc_i[3] | enc_i[2] | enc_i[0];
assign enc_o[2] = enc_i[4] | enc_i[0];

endmodule