data/full_repos/permissive/494696040/tb_processor.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/494696040/tb_processor.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #210 reset <= 1\'b1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/494696040/tb_processor.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset <= 1\'b0;\n        ^\n%Error: data/full_repos/permissive/494696040/tb_processor.v:42: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("dump.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/494696040/tb_processor.v:43: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/494696040/tb_processor.v:47: Unsupported: Ignoring delay on this delayed statement.\n    initial #230 $finish;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/494696040/tb_processor.v:51: Unsupported: Ignoring delay on this delayed statement.\n            #5 CLK <= ~CLK;\n            ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_processor;
    reg CLK;
    reg reset;
    

    initial begin
        CLK <= 1'b0;
        reset <= 1'b0;
        

        #210 reset <= 1'b1;
        #10 reset <= 1'b0;
    end


    processor mips(CLK, reset);
    

    initial begin
        $dumpfile("dump.vcd");
        $dumpvars;
    end


    initial #230 $finish;
        
    initial
        repeat(100)
            #5 CLK <= ~CLK;
    

    initial begin
        
    end
endmodule
module tb_processor;

    reg CLK;
    reg reset;
    

    initial begin
        CLK <= 1'b0;
        reset <= 1'b0;
        

        #210 reset <= 1'b1;
        #10 reset <= 1'b0;
    end


    processor mips(CLK, reset);
    

    initial begin
        $dumpfile("dump.vcd");
        $dumpvars;
    end


    initial #230 $finish;
        
    initial
        repeat(100)
            #5 CLK <= ~CLK;
    

    initial begin
        
    end
endmodule