data/full_repos/permissive/485467282/CPU.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/485467282/CPU.v:37: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/485467282/CPU.v:46: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485467282/CPU.v:55: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485467282/CPU.v:64: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485467282/CPU.v:73: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485467282/CPU.v:82: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485467282/CPU.v:91: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485467282/CPU.v:103: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485467282/CPU.v:113: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485467282/CPU.v:137: Unsupported: Ignoring delay on this delayed statement.\n                #1\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/485467282/CPU.v:155: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/485467282/CPU.v:159: Unsupported: Ignoring delay on this delayed statement.\n    always #50 clk = ~clk;\n           ^\n%Error: data/full_repos/permissive/485467282/CPU.v:172: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("test.vcd");\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/485467282/CPU.v:171: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n%Error: data/full_repos/permissive/485467282/CPU.v:173: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, clk, instruction, bus, tmp_alu, Rx[0], Rx[1], Rx[2], Rx[3]);\n        ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module CPU();



    reg [15:0] instruction;
    reg [15:0] A, B, zero;
    reg [15:0] Rx [15:0];
    reg [2:0] alu_sel;
    reg [3:0] addr, shamt, a, pc;
    reg en_alu, we, oe, clk;
    wire [15:0] bus, ins_bus;
    wire carryFlag;
    wire [3:0] Rn, Rd, Rm, opcode;
   
    integer i;

    assign opcode = instruction[15:12];
    assign Rd = instruction[11:8];
    assign Rn = instruction[7:4];
    assign Rm = instruction[3:0];

    wire [15:0] tmp_alu;
    alu aluop(.A(A), .B(B), .ALU_Out(tmp_alu), .ALU_Sel(alu_sel), .CarryOut(carryFlag), .shamt(shamt));
    buffer aluBuff(.clk(clk), .en(en_alu), .in(tmp_alu), .out(bus));
    RAM data(.data(bus), .clk(clk), .we(we), .oe(oe), .addr(addr));
    IMem mem(.a(pc), .data(ins_bus));
    
    always@(posedge clk)
    begin
        case(opcode)
            4'h0:begin
                A <= Rx[Rn];
                B <= Rx[Rm];
                alu_sel = 3'b000;
                en_alu = 1'b1;
                #1
                Rx[Rd] = bus;
                en_alu = 1'b0;
            end
            4'h1:begin
                A <= Rx[Rn];
                B <= Rm;
                alu_sel = 3'b000;
                en_alu = 1'b1;
                #1
                Rx[Rd] = bus;
                en_alu = 1'b0;
            end
            4'h2:begin
                A <= Rx[Rn];
                B <= Rx[Rm];
                alu_sel = 3'b001;
                en_alu = 1'b1;
                #1
                Rx[Rd] = bus;
                en_alu = 1'b0;
            end
            4'h3:begin
                A <= Rx[Rn];
                B <= Rm;
                alu_sel = 3'b001;
                en_alu = 1'b1;
                #1
                Rx[Rd] = bus;
                en_alu = 1'b0;
            end
            4'h4:begin
                A <= Rx[Rn];
                B <= Rx[Rm];
                alu_sel = 3'b010;
                en_alu = 1'b1;
                #1
                Rx[Rd] = bus;
                en_alu = 1'b0;
            end
            4'h5:begin
                A <= Rx[Rn];
                B <= Rx[Rm];
                alu_sel = 3'b011;
                en_alu = 1'b1;
                #1
                Rx[Rd] = bus;
                en_alu = 1'b0;
            end
            4'h6:begin
                A <= Rx[Rn];
                B <= Rx[Rm];
                alu_sel = 3'b100;
                en_alu = 1'b1;
                #1
                Rx[Rd] = bus;
                en_alu = 1'b0;
            end
            4'h7:begin
                $display("%d", Rx[Rd]);
            end
            4'h8:begin
                A <= Rx[Rn];
                B <= Rx[Rm];
                alu_sel = 3'b110;
                en_alu = 1'b1;
                #1
                Rx[Rd] = bus;
                en_alu = 1'b0;
            end
            4'h9: $finish;
            4'ha:begin
                A <= Rx[Rn];
                shamt <= Rm;
                alu_sel = 3'b111;
                en_alu = 1'b1;
                #1
                Rx[Rd] = bus;
                en_alu = 1'b0;
            end
            4'hb:begin
                Rx[15] = pc + 1;
                pc = Rx[Rd]-1;
            end
            4'hc:begin
                if(Rx[Rn] == Rx[Rm]) begin
                    pc = Rx[Rd]-1;
                end
            end
            4'hd:begin
                pc = Rx[Rd]-1;
            end
            4'he:begin
                addr = Rd;
                A <= 0;
                B <= Rx[Rn];
                alu_sel = 'b000;
                en_alu = 1;
                oe = 0;
                we = 1;
                #1
                we = 0;
                en_alu = 0;
            end
            4'hf:begin
                addr = Rd;
                we = 0;
                oe = 1;
                Rx[Rn] = bus;
                oe = 0;
            end
            default : A = 4'hz;
        endcase
    end

    always @(negedge clk)
    begin
        pc = pc + 1;
        #10
        instruction = ins_bus;
    end

    always #50 clk = ~clk;



    initial begin
        clk = 0;
        {we, oe, en_alu, addr, a, zero} <= 0;
        for(i = 0; i < 16; i = i+1) begin
            Rx[i] = 0;
        end
        i = 0;
        pc = -1;
        #100
        $dumpfile("test.vcd");
        $dumpvars(0, clk, instruction, bus, tmp_alu, Rx[0], Rx[1], Rx[2], Rx[3]);

        
    end
endmodule
module CPU();




    reg [15:0] instruction;
    reg [15:0] A, B, zero;
    reg [15:0] Rx [15:0];
    reg [2:0] alu_sel;
    reg [3:0] addr, shamt, a, pc;
    reg en_alu, we, oe, clk;
    wire [15:0] bus, ins_bus;
    wire carryFlag;
    wire [3:0] Rn, Rd, Rm, opcode;
   
    integer i;

    assign opcode = instruction[15:12];
    assign Rd = instruction[11:8];
    assign Rn = instruction[7:4];
    assign Rm = instruction[3:0];

    wire [15:0] tmp_alu;
    alu aluop(.A(A), .B(B), .ALU_Out(tmp_alu), .ALU_Sel(alu_sel), .CarryOut(carryFlag), .shamt(shamt));
    buffer aluBuff(.clk(clk), .en(en_alu), .in(tmp_alu), .out(bus));
    RAM data(.data(bus), .clk(clk), .we(we), .oe(oe), .addr(addr));
    IMem mem(.a(pc), .data(ins_bus));
    
    always@(posedge clk)
    begin
        case(opcode)
            4'h0:begin
                A <= Rx[Rn];
                B <= Rx[Rm];
                alu_sel = 3'b000;
                en_alu = 1'b1;
                #1
                Rx[Rd] = bus;
                en_alu = 1'b0;
            end
            4'h1:begin
                A <= Rx[Rn];
                B <= Rm;
                alu_sel = 3'b000;
                en_alu = 1'b1;
                #1
                Rx[Rd] = bus;
                en_alu = 1'b0;
            end
            4'h2:begin
                A <= Rx[Rn];
                B <= Rx[Rm];
                alu_sel = 3'b001;
                en_alu = 1'b1;
                #1
                Rx[Rd] = bus;
                en_alu = 1'b0;
            end
            4'h3:begin
                A <= Rx[Rn];
                B <= Rm;
                alu_sel = 3'b001;
                en_alu = 1'b1;
                #1
                Rx[Rd] = bus;
                en_alu = 1'b0;
            end
            4'h4:begin
                A <= Rx[Rn];
                B <= Rx[Rm];
                alu_sel = 3'b010;
                en_alu = 1'b1;
                #1
                Rx[Rd] = bus;
                en_alu = 1'b0;
            end
            4'h5:begin
                A <= Rx[Rn];
                B <= Rx[Rm];
                alu_sel = 3'b011;
                en_alu = 1'b1;
                #1
                Rx[Rd] = bus;
                en_alu = 1'b0;
            end
            4'h6:begin
                A <= Rx[Rn];
                B <= Rx[Rm];
                alu_sel = 3'b100;
                en_alu = 1'b1;
                #1
                Rx[Rd] = bus;
                en_alu = 1'b0;
            end
            4'h7:begin
                $display("%d", Rx[Rd]);
            end
            4'h8:begin
                A <= Rx[Rn];
                B <= Rx[Rm];
                alu_sel = 3'b110;
                en_alu = 1'b1;
                #1
                Rx[Rd] = bus;
                en_alu = 1'b0;
            end
            4'h9: $finish;
            4'ha:begin
                A <= Rx[Rn];
                shamt <= Rm;
                alu_sel = 3'b111;
                en_alu = 1'b1;
                #1
                Rx[Rd] = bus;
                en_alu = 1'b0;
            end
            4'hb:begin
                Rx[15] = pc + 1;
                pc = Rx[Rd]-1;
            end
            4'hc:begin
                if(Rx[Rn] == Rx[Rm]) begin
                    pc = Rx[Rd]-1;
                end
            end
            4'hd:begin
                pc = Rx[Rd]-1;
            end
            4'he:begin
                addr = Rd;
                A <= 0;
                B <= Rx[Rn];
                alu_sel = 'b000;
                en_alu = 1;
                oe = 0;
                we = 1;
                #1
                we = 0;
                en_alu = 0;
            end
            4'hf:begin
                addr = Rd;
                we = 0;
                oe = 1;
                Rx[Rn] = bus;
                oe = 0;
            end
            default : A = 4'hz;
        endcase
    end

    always @(negedge clk)
    begin
        pc = pc + 1;
        #10
        instruction = ins_bus;
    end

    always #50 clk = ~clk;



    initial begin
        clk = 0;
        {we, oe, en_alu, addr, a, zero} <= 0;
        for(i = 0; i < 16; i = i+1) begin
            Rx[i] = 0;
        end
        i = 0;
        pc = -1;
        #100
        $dumpfile("test.vcd");
        $dumpvars(0, clk, instruction, bus, tmp_alu, Rx[0], Rx[1], Rx[2], Rx[3]);

        
    end
endmodule