data/full_repos/permissive/515513819/neuron/neuron.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/515513819/neuron/neuron.v:49: Unsupported: Ignoring delay on this delayed statement.\n      #1  \n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module neuron (
  clk,
  weight,
  data_in,
  sign_in,
  data_out,
  sign_out
  );

  input clk, weight;
  input data_in, sign_in;
  output data_out, sign_out;

  reg [3:0] counter;
  reg data_out, sign_out;

  initial begin
    counter <= 4'b0;
    data_out <= 0;
    sign_out <= 0;
  end


  always @ ( data_in, sign_in ) begin






    if (data_in == 1 && sign_in == 1)
      begin
        counter <= counter + 1;
      end
    else if (data_in == 1 && sign_in == 0)
      begin
        counter <= (counter == 4'b0) ? 0 : counter - 1;
      end
  end


  always @ (negedge clk) begin
    if (counter > 4'b0010) begin
      data_out <= 1;
      sign_out <= weight;
      counter <= 4'b0;
      #1
      data_out <= 0;
      sign_out <= 0;
    end else begin
      data_out <= 0;
      sign_out <= 0;
    end
  end

endmodule
module neuron (
  clk,
  weight,
  data_in,
  sign_in,
  data_out,
  sign_out
  );


  input clk, weight;
  input data_in, sign_in;
  output data_out, sign_out;

  reg [3:0] counter;
  reg data_out, sign_out;

  initial begin
    counter <= 4'b0;
    data_out <= 0;
    sign_out <= 0;
  end


  always @ ( data_in, sign_in ) begin






    if (data_in == 1 && sign_in == 1)
      begin
        counter <= counter + 1;
      end
    else if (data_in == 1 && sign_in == 0)
      begin
        counter <= (counter == 4'b0) ? 0 : counter - 1;
      end
  end


  always @ (negedge clk) begin
    if (counter > 4'b0010) begin
      data_out <= 1;
      sign_out <= weight;
      counter <= 4'b0;
      #1
      data_out <= 0;
      sign_out <= 0;
    end else begin
      data_out <= 0;
      sign_out <= 0;
    end
  end

endmodule