data/full_repos/permissive/494905093/AES System with PUF/AES System with ROPUF/All.v
1: b'%Error: Cannot find file containing module: System\n        ... Looked in:\n             data/full_repos/permissive/494905093/AES/System\n             data/full_repos/permissive/494905093/AES/System.v\n             data/full_repos/permissive/494905093/AES/System.sv\n             System\n             System.v\n             System.sv\n             obj_dir/System\n             obj_dir/System.v\n             obj_dir/System.sv\n%Error: Cannot find file containing module: with\n%Error: Cannot find file containing module: PUF/AES\n%Error: Cannot find file containing module: ROPUF,data/full_repos/permissive/494905093\n%Error: Cannot find file containing module: data/full_repos/permissive/494905093/AES\n%Error: Cannot find file containing module: ROPUF/All.v\n%Error: Exiting due to 6 error(s)\n'
module All(clk,reset);

    input       clk,reset;

    
    reg         [127:0] data_in; 
    wire        [127:0] data;


    wire        [127:0] key_input;
    wire        [127:0] data_out,key_out;
    wire        Reset,clk_divided,reset_in, sure;
    wire        enable;

    
    assign Reset = reset;
    assign reset_in=~enable;

    reg [2:0] count;

    always@( posedge clk )begin
        
        count <= count + 3'd1;
    
    end

    assign clk_divided = count[2];

    All_Vio vio0( .clk(clk), .probe_in0(key_out), .probe_in1(data_out), .probe_out0(data), .probe_out1(key_input));
    
    AES_circuit a0( data_in, clk_divided, reset_in, key_out, data_out, sure);
    keygenerator k0( clk_divided, Reset, key_input, key_out, enable);

    
    always@(enable) begin
        
        if(enable) begin

            data_in = data;
        end
        
        else begin
            data_in = 128'd0;
        end

    end
    


endmodule
module All(clk,reset);


    input       clk,reset;

    
    reg         [127:0] data_in; 
    wire        [127:0] data;


    wire        [127:0] key_input;
    wire        [127:0] data_out,key_out;
    wire        Reset,clk_divided,reset_in, sure;
    wire        enable;

    
    assign Reset = reset;
    assign reset_in=~enable;

    reg [2:0] count;

    always@( posedge clk )begin
        
        count <= count + 3'd1;
    
    end

    assign clk_divided = count[2];

    All_Vio vio0( .clk(clk), .probe_in0(key_out), .probe_in1(data_out), .probe_out0(data), .probe_out1(key_input));
    
    AES_circuit a0( data_in, clk_divided, reset_in, key_out, data_out, sure);
    keygenerator k0( clk_divided, Reset, key_input, key_out, enable);

    
    always@(enable) begin
        
        if(enable) begin

            data_in = data;
        end
        
        else begin
            data_in = 128'd0;
        end

    end
    


endmodule