data/full_repos/permissive/501470173/verilog/rtl/regfile.v
data/verilator_xmls/79eac564-9992-4192-bbc0-f523bd9ef56b.xml
module regfile(
    input [7:0] datain,
    input clk, we,
    input [2:0] wa,
    input [2:0] raa,
    input [2:0] rab,
    output [7:0] porta,
    output [7:0] portb
    );


reg [7:0] mem [7:0];

    always@(posedge clk)
	 begin
		 mem[0]<=0;
		 if(we) 
			mem[wa]<=datain;
	 end	 
	
assign porta=mem[raa];
assign portb=mem[rab];


endmodule
module regfile(
    input [7:0] datain,
    input clk, we,
    input [2:0] wa,
    input [2:0] raa,
    input [2:0] rab,
    output [7:0] porta,
    output [7:0] portb
    );



reg [7:0] mem [7:0];

    always@(posedge clk)
	 begin
		 mem[0]<=0;
		 if(we) 
			mem[wa]<=datain;
	 end	 
	
assign porta=mem[raa];
assign portb=mem[rab];


endmodule