data/full_repos/permissive/500128826/but-2-led-Blocking-NonBlocking/top.v
data/verilator_xmls/03323b66-c0ed-4b22-9655-63a864fd8435.xml
module blocking (
    input  wire CLK,
    input  wire BUT,
    output wire LED
);

  reg b1, b2, b3;


  always @(posedge CLK) begin
    b1 = BUT;
    b2 = b1;
    b3 = b2;
  end

  assign LED = ~b3;


endmodule
module blocking (
    input  wire CLK,
    input  wire BUT,
    output wire LED
);


  reg b1, b2, b3;


  always @(posedge CLK) begin
    b1 = BUT;
    b2 = b1;
    b3 = b2;
  end

  assign LED = ~b3;


endmodule