data/full_repos/permissive/52714256/INTERFACES/src/SPI/spi_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/52714256/INTERFACES/src/SPI/spi_testbench.v:85: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/52714256/INTERFACES/src/SPI/spi_testbench.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/52714256/INTERFACES/src/SPI/spi_testbench.v:96: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/52714256/INTERFACES/src/SPI/spi_testbench.v:98: Unsupported: Ignoring delay on this delayed statement.\n        #200\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/52714256/INTERFACES/src/SPI/spi_testbench.v:100: Unsupported: Ignoring delay on this delayed statement.\n        #10000\n        ^\n%Warning-WIDTH: data/full_repos/permissive/52714256/INTERFACES/src/SPI/spi_testbench.v:37: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'15\'h2c36\' generates 15 bits.\n                                                                                         : ... In instance SPI_testbench\n    reg [m-1:0] MASTER_TX = 15\'b010110000110110;\n                            ^~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/52714256/INTERFACES/src/SPI/spi_testbench.v:39: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'15\'h6b36\' generates 15 bits.\n                                                                                         : ... In instance SPI_testbench\n    reg [m-1:0] SLAVE_TX = 15\'b110101100110110;\n                           ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/52714256/INTERFACES/src/SPI/spi_testbench.v:43: Cannot find file containing module: \'SPI_MASTER\'\n    SPI_MASTER #(.m(m)) spi_master\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52714256/INTERFACES/src/SPI,data/full_repos/permissive/52714256/SPI_MASTER\n             data/full_repos/permissive/52714256/INTERFACES/src/SPI,data/full_repos/permissive/52714256/SPI_MASTER.v\n             data/full_repos/permissive/52714256/INTERFACES/src/SPI,data/full_repos/permissive/52714256/SPI_MASTER.sv\n             SPI_MASTER\n             SPI_MASTER.v\n             SPI_MASTER.sv\n             obj_dir/SPI_MASTER\n             obj_dir/SPI_MASTER.v\n             obj_dir/SPI_MASTER.sv\n%Error: data/full_repos/permissive/52714256/INTERFACES/src/SPI/spi_testbench.v:58: Cannot find file containing module: \'SPI_SLAVE\'\n    SPI_SLAVE #(.m(m)) spi_slave \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/52714256/INTERFACES/src/SPI/spi_testbench.v:69: Cannot find file containing module: \'CLK_DIV\'\n    CLK_DIV clk_div\n    ^~~~~~~\n%Error: data/full_repos/permissive/52714256/INTERFACES/src/SPI/spi_testbench.v:77: Cannot find file containing module: \'D2STR_B\'\n    D2STR_B #(.len(15)) oled_d2b_1\n    ^~~~~~~\n%Error: Exiting due to 4 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module SPI_testbench();
    parameter integer m = 10;
    reg GCLK;
    reg st;
    reg LEFT;
    reg R;
    reg RST;
    wire MISO;
    wire MOSI;
    wire SS;
    wire SCLK;
    

    wire [m-1:0] MASTER_RX;
    reg [m-1:0] MASTER_TX = 15'b010110000110110;
    wire [m-1:0] SLAVE_RX;
    reg [m-1:0] SLAVE_TX = 15'b110101100110110;
    
    wire clk_Tbit;
        
    SPI_MASTER #(.m(m)) spi_master
        (
        .clk(GCLK),
        .ce(clk_Tbit),
        .st(st),
        .SCLK(SCLK),
        .MISO(MISO),
        .MOSI(MOSI),
        .LOAD(SS),
        .TX_MD(MASTER_TX),
        .RX_SD(MASTER_RX),
        .LEFT(LEFT),
        .R(R)
        );
    
    SPI_SLAVE #(.m(m)) spi_slave 
        (
        .RST(RST),
        .SCLK(SCLK),
        .MISO(MISO),
        .MOSI(MOSI),
        .SS(SS),
        .DIN(SLAVE_TX),
        .DOUT(SLAVE_RX)
        );
    
    CLK_DIV clk_div
        (
        .GCLK(GCLK),
        .out(clk_Tbit),
        .T(64'd10)
        );
    
    wire [127:0] w_str1;
    D2STR_B #(.len(15)) oled_d2b_1
        (
        .str(w_str1),
        .d(231)
        );
    
    always begin
        GCLK = 1'b0;
        #10;
        GCLK = 1'b1;
        #10;
    end
    
    initial begin
        GCLK = 1'b0;
        st = 1'b0;
        LEFT = 1'b1;
        R = 1'b0;
        RST = 1'b0;
        #100
        st = 1'b1;
        #200
        st = 1'b0;
        #10000
        $finish;
    end
endmodule
module SPI_testbench();

    parameter integer m = 10;
    reg GCLK;
    reg st;
    reg LEFT;
    reg R;
    reg RST;
    wire MISO;
    wire MOSI;
    wire SS;
    wire SCLK;
    

    wire [m-1:0] MASTER_RX;
    reg [m-1:0] MASTER_TX = 15'b010110000110110;
    wire [m-1:0] SLAVE_RX;
    reg [m-1:0] SLAVE_TX = 15'b110101100110110;
    
    wire clk_Tbit;
        
    SPI_MASTER #(.m(m)) spi_master
        (
        .clk(GCLK),
        .ce(clk_Tbit),
        .st(st),
        .SCLK(SCLK),
        .MISO(MISO),
        .MOSI(MOSI),
        .LOAD(SS),
        .TX_MD(MASTER_TX),
        .RX_SD(MASTER_RX),
        .LEFT(LEFT),
        .R(R)
        );
    
    SPI_SLAVE #(.m(m)) spi_slave 
        (
        .RST(RST),
        .SCLK(SCLK),
        .MISO(MISO),
        .MOSI(MOSI),
        .SS(SS),
        .DIN(SLAVE_TX),
        .DOUT(SLAVE_RX)
        );
    
    CLK_DIV clk_div
        (
        .GCLK(GCLK),
        .out(clk_Tbit),
        .T(64'd10)
        );
    
    wire [127:0] w_str1;
    D2STR_B #(.len(15)) oled_d2b_1
        (
        .str(w_str1),
        .d(231)
        );
    
    always begin
        GCLK = 1'b0;
        #10;
        GCLK = 1'b1;
        #10;
    end
    
    initial begin
        GCLK = 1'b0;
        st = 1'b0;
        LEFT = 1'b1;
        R = 1'b0;
        RST = 1'b0;
        #100
        st = 1'b1;
        #200
        st = 1'b0;
        #10000
        $finish;
    end
endmodule