data/full_repos/permissive/445357518/regfile_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/445357518/regfile_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n  clk = 1\'b0; #5;\n              ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/445357518/regfile_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n   clk = 1\'b1; #5;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/regfile_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n   clk = 1\'b0; #5;\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/regfile_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/regfile_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/regfile_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/regfile_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/regfile_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/regfile_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n  #7;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/regfile_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n  #3;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/regfile_tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n  #9;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/regfile_tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/regfile_tb.v:132: Unsupported: Ignoring delay on this delayed statement.\n  #2;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/regfile_tb.v:134: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/regfile_tb.v:143: Unsupported: Ignoring delay on this delayed statement.\n  #0.01\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/445357518/regfile_tb.v:145: Unsupported: Ignoring delay on this delayed statement.\n  #0.99\n  ^\n%Error: data/full_repos/permissive/445357518/regfile_tb.v:11: Cannot find file containing module: \'regfile\'\n       regfile DUT(data_in,writenum,write,readnum,clk,data_out);\n       ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/regfile\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/regfile.v\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/regfile.sv\n             regfile\n             regfile.v\n             regfile.sv\n             obj_dir/regfile\n             obj_dir/regfile.v\n             obj_dir/regfile.sv\n%Error: Exiting due to 1 error(s), 16 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module regfile_tb;
	
	reg[15:0] data_in;
	reg[2:0] writenum, readnum;
	reg write, clk;
	wire[15:0] data_out;
	reg err;
       

       regfile DUT(data_in,writenum,write,readnum,clk,data_out);


       initial begin
		clk = 1'b0; #5;
		forever begin
			clk = 1'b1; #5;
			clk = 1'b0; #5;
		end
	end


        initial begin

		err = 1'b0; 

		$display("NEXT CHECK: WRITE VALUE 8 TO R0 AND READ FROM IT");
		 
		data_in = 16'b0000000000001000;
		write = 1;
		writenum = 3'b000;
		readnum = 3'b000;
		#10;
		
		
		if (data_out !== 16'b0000000000001000) begin
			$display("ERROR WITH OUTPUT, EXPECTED %b BUT WAS %b", 16'b0000000000001000, data_out);
			err = 1'b1;
		end
		

		$display("NEXT CHECK: ENSURE NOTHING IS WRITTEN IF WRITE IS 0 AND READ FROM R0");  
		data_in = 16'b0000000000010000;
		write = 0;
		writenum = 3'b000;
		readnum = 3'b000;
		#10;
		
		
		if (data_out !== 16'b0000000000001000) begin
			$display("ERROR WITH OUTPUT, EXPECTED %b BUT WAS %b", 16'b0000000000001000, data_out);
			err = 1'b1;
		end
		

		$display("NEXT CHECK: WRITES 16 TO R0 AND READ FROM R0");
		
		data_in = 16'b0000000000010000;
		write = 1;
		writenum = 3'b000;
		readnum = 3'b000;
		#10;
		
		if (data_out !== 16'b0000000000010000) begin
			$display("ERROR WITH OUTPUT, EXPECTED %b BUT WAS %b", 16'b0000000000010000, data_out);
			err = 1'b1;
		end
		

		$display("NEXT CHECK: WRITES all 1's TO R7 AND READ FROM R7");
		 
		data_in = 16'b1111111111111111;
		write = 1;
		writenum = 3'b111;
		readnum = 3'b111;
		#10;
		

		if (data_out !== 16'b1111111111111111) begin
			$display("ERROR WITH OUTPUT, EXPECTED %b BUT WAS %b", 16'b1111111111111111, data_out);
			err = 1'b1;
		end


		$display("NEXT CHECK: WRITES the value 320 TO R3 BUT READ stays at R7");
		
		data_in = 16'd320;
		write = 1;
		writenum = 3'b011;
		readnum = 3'b111;
		#10;
		
		if (data_out !== 16'b1111111111111111) begin
			$display("ERROR WITH OUTPUT, EXPECTED %b BUT WAS %b", 16'b1111111111111111, data_out);
			err = 1'b1;
		end
		

		$display("NEXT CHECK: WRITES the value 1659 TO R2 AND reads the value at R3"); 
		data_in = 16'd1659;
		write = 1;
		writenum = 3'b010;
		readnum = 3'b111;
		#7;
		readnum = 3'b011;
		#3;

		if (data_out !== 16'd320) begin
			$display("ERROR WITH OUTPUT, EXPECTED %b BUT WAS %b", 16'd320, data_out);
			err = 1'b1;
		end
		

		$display("NEXT CHECK: DOES NOT WRITE ANYTHING, but reads the value at R2"); 
		data_in = 16'd9999;
		write = 0;
		writenum = 3'b001;
		readnum = 3'b011;

		#9;
		readnum = 3'b010;
		#1;

		if (data_out !== 16'd1659) begin
			$display("ERROR WITH OUTPUT, EXPECTED %b BUT WAS %b", 16'd1659, data_out);
			err = 1'b1;
		end
		

		$display("CHECKS THAT READ VALUES ARE UPDATED INDEPENDENTLY OF CLK");
		
		#2;
		readnum = 3'b001;
		#1;

		if (data_out !== 16'bxxxxxxxxxxxxxxxx) begin
			$display("ERROR WITH OUTPUT, EXPECTED %b BUT WAS %b", 16'bxxxxxxxxxxxxxxxx, data_out);
			err = 1'b1;
		end


		$display("FINAL READ OF R7");
		#0.01
		readnum = 3'b111;
		#0.99
		if (data_out !== 16'b1111111111111111) begin
			$display("ERROR WITH OUTPUT, EXPECTED %b BUT WAS %b", 16'b1111111111111111, data_out);
			err = 1'b1;
		end
			
		if (~err)
			$display("PASSED");
		else
			$display("FAILED");
		
	
	end
		
endmodule
module regfile_tb;

	
	reg[15:0] data_in;
	reg[2:0] writenum, readnum;
	reg write, clk;
	wire[15:0] data_out;
	reg err;
       

       regfile DUT(data_in,writenum,write,readnum,clk,data_out);


       initial begin
		clk = 1'b0; #5;
		forever begin
			clk = 1'b1; #5;
			clk = 1'b0; #5;
		end
	end


        initial begin

		err = 1'b0; 

		$display("NEXT CHECK: WRITE VALUE 8 TO R0 AND READ FROM IT");
		 
		data_in = 16'b0000000000001000;
		write = 1;
		writenum = 3'b000;
		readnum = 3'b000;
		#10;
		
		
		if (data_out !== 16'b0000000000001000) begin
			$display("ERROR WITH OUTPUT, EXPECTED %b BUT WAS %b", 16'b0000000000001000, data_out);
			err = 1'b1;
		end
		

		$display("NEXT CHECK: ENSURE NOTHING IS WRITTEN IF WRITE IS 0 AND READ FROM R0");  
		data_in = 16'b0000000000010000;
		write = 0;
		writenum = 3'b000;
		readnum = 3'b000;
		#10;
		
		
		if (data_out !== 16'b0000000000001000) begin
			$display("ERROR WITH OUTPUT, EXPECTED %b BUT WAS %b", 16'b0000000000001000, data_out);
			err = 1'b1;
		end
		

		$display("NEXT CHECK: WRITES 16 TO R0 AND READ FROM R0");
		
		data_in = 16'b0000000000010000;
		write = 1;
		writenum = 3'b000;
		readnum = 3'b000;
		#10;
		
		if (data_out !== 16'b0000000000010000) begin
			$display("ERROR WITH OUTPUT, EXPECTED %b BUT WAS %b", 16'b0000000000010000, data_out);
			err = 1'b1;
		end
		

		$display("NEXT CHECK: WRITES all 1's TO R7 AND READ FROM R7");
		 
		data_in = 16'b1111111111111111;
		write = 1;
		writenum = 3'b111;
		readnum = 3'b111;
		#10;
		

		if (data_out !== 16'b1111111111111111) begin
			$display("ERROR WITH OUTPUT, EXPECTED %b BUT WAS %b", 16'b1111111111111111, data_out);
			err = 1'b1;
		end


		$display("NEXT CHECK: WRITES the value 320 TO R3 BUT READ stays at R7");
		
		data_in = 16'd320;
		write = 1;
		writenum = 3'b011;
		readnum = 3'b111;
		#10;
		
		if (data_out !== 16'b1111111111111111) begin
			$display("ERROR WITH OUTPUT, EXPECTED %b BUT WAS %b", 16'b1111111111111111, data_out);
			err = 1'b1;
		end
		

		$display("NEXT CHECK: WRITES the value 1659 TO R2 AND reads the value at R3"); 
		data_in = 16'd1659;
		write = 1;
		writenum = 3'b010;
		readnum = 3'b111;
		#7;
		readnum = 3'b011;
		#3;

		if (data_out !== 16'd320) begin
			$display("ERROR WITH OUTPUT, EXPECTED %b BUT WAS %b", 16'd320, data_out);
			err = 1'b1;
		end
		

		$display("NEXT CHECK: DOES NOT WRITE ANYTHING, but reads the value at R2"); 
		data_in = 16'd9999;
		write = 0;
		writenum = 3'b001;
		readnum = 3'b011;

		#9;
		readnum = 3'b010;
		#1;

		if (data_out !== 16'd1659) begin
			$display("ERROR WITH OUTPUT, EXPECTED %b BUT WAS %b", 16'd1659, data_out);
			err = 1'b1;
		end
		

		$display("CHECKS THAT READ VALUES ARE UPDATED INDEPENDENTLY OF CLK");
		
		#2;
		readnum = 3'b001;
		#1;

		if (data_out !== 16'bxxxxxxxxxxxxxxxx) begin
			$display("ERROR WITH OUTPUT, EXPECTED %b BUT WAS %b", 16'bxxxxxxxxxxxxxxxx, data_out);
			err = 1'b1;
		end


		$display("FINAL READ OF R7");
		#0.01
		readnum = 3'b111;
		#0.99
		if (data_out !== 16'b1111111111111111) begin
			$display("ERROR WITH OUTPUT, EXPECTED %b BUT WAS %b", 16'b1111111111111111, data_out);
			err = 1'b1;
		end
			
		if (~err)
			$display("PASSED");
		else
			$display("FAILED");
		
	
	end
		
endmodule