data/full_repos/permissive/497604366/cpu/cpu.srcs/sources_1/new/writeback_mux.v
data/verilator_xmls/bc7c6b50-cb70-469a-b4b7-a2558ae4eb23.xml
module writeback_mux(
    input [31:0] wr,
    input [31:0] wdo,
    input wm2reg,
    output reg [31:0] wbData
    );
    always @(*) begin
        if (wm2reg == 0) begin
            wbData <= wr;
        end
        if (wm2reg == 1) begin
            wbData <= wdo;
        end
    end
endmodule
module writeback_mux(
    input [31:0] wr,
    input [31:0] wdo,
    input wm2reg,
    output reg [31:0] wbData
    );

    always @(*) begin
        if (wm2reg == 0) begin
            wbData <= wr;
        end
        if (wm2reg == 1) begin
            wbData <= wdo;
        end
    end
endmodule