data/full_repos/permissive/502135797/Lab4_March_2_2022/Code/seg7driver.v
data/verilator_xmls/d34423bf-c527-43f7-9ecb-0741e1407cb5.xml
module seg7driver(
        input [3:0] digit1,
        input [3:0] digit2, 
        output reg [6:0] Cnode,
        output dp,
        output reg [7:0] AN,
        input nexysCLK,
        output reg divided_clk = 0
        );
        reg [3:0] singledigit =0; 
        reg [1:0] refreshcounter = 0;

        
        localparam div_value = 25000;
        
        integer counter_value = 0;
        
        always @(posedge nexysCLK) 
        begin
            if (counter_value == div_value)
                counter_value <= 0;
            else
                counter_value <= counter_value + 1;
        end
        

        always @(posedge nexysCLK)
        begin
            if (counter_value == div_value)
                divided_clk <= ~divided_clk;
            else
                divided_clk <= divided_clk;
        end

        
         
        always @(posedge divided_clk)
        begin
            refreshcounter <= refreshcounter + 1;
        end
        
        always @(refreshcounter)
            begin 
                case(refreshcounter)
                    2'b00: singledigit = digit1;
                    2'b01: singledigit = digit2;


                endcase
            end
            
        always @(refreshcounter)
        begin
            case(refreshcounter)
                2'b00: AN = 8'b11111110;
                2'b01: AN = 8'b11111101;

                default: AN = 8'bZZZZZZZZ; 
            
            endcase 
        end
        
        assign dp = 1'b1;
        always@(singledigit)
            begin
                case (singledigit)
                    4'd0: Cnode<= 7'b0000001; 
                    4'd1: Cnode<= 7'b1001111; 
                    4'd2: Cnode<= 7'b0010010; 
                    4'd3: Cnode<= 7'b0000110; 
                    4'd4: Cnode<= 7'b1001100; 
                    4'd5: Cnode<= 7'b0100100; 
                    4'd6: Cnode<= 7'b0100000; 
                    4'd7: Cnode<= 7'b0001111; 
                    4'd8: Cnode<= 7'b0000000; 
                    4'd9: Cnode<= 7'b0000100; 
                    4'd10:Cnode<= 7'b0001000; 
                    4'd11:Cnode<= 7'b1100000; 
                    4'd12:Cnode<= 7'b0110001; 
                    4'd13:Cnode<= 7'b1000010; 
                    4'd14:Cnode<= 7'b0110000; 
                    4'd15:Cnode<= 7'b0111000; 
                endcase
            end
            
            
    endmodule
module seg7driver(
        input [3:0] digit1,
        input [3:0] digit2, 
        output reg [6:0] Cnode,
        output dp,
        output reg [7:0] AN,
        input nexysCLK,
        output reg divided_clk = 0
        );

        reg [3:0] singledigit =0; 
        reg [1:0] refreshcounter = 0;

        
        localparam div_value = 25000;
        
        integer counter_value = 0;
        
        always @(posedge nexysCLK) 
        begin
            if (counter_value == div_value)
                counter_value <= 0;
            else
                counter_value <= counter_value + 1;
        end
        

        always @(posedge nexysCLK)
        begin
            if (counter_value == div_value)
                divided_clk <= ~divided_clk;
            else
                divided_clk <= divided_clk;
        end

        
         
        always @(posedge divided_clk)
        begin
            refreshcounter <= refreshcounter + 1;
        end
        
        always @(refreshcounter)
            begin 
                case(refreshcounter)
                    2'b00: singledigit = digit1;
                    2'b01: singledigit = digit2;


                endcase
            end
            
        always @(refreshcounter)
        begin
            case(refreshcounter)
                2'b00: AN = 8'b11111110;
                2'b01: AN = 8'b11111101;

                default: AN = 8'bZZZZZZZZ; 
            
            endcase 
        end
        
        assign dp = 1'b1;
        always@(singledigit)
            begin
                case (singledigit)
                    4'd0: Cnode<= 7'b0000001; 
                    4'd1: Cnode<= 7'b1001111; 
                    4'd2: Cnode<= 7'b0010010; 
                    4'd3: Cnode<= 7'b0000110; 
                    4'd4: Cnode<= 7'b1001100; 
                    4'd5: Cnode<= 7'b0100100; 
                    4'd6: Cnode<= 7'b0100000; 
                    4'd7: Cnode<= 7'b0001111; 
                    4'd8: Cnode<= 7'b0000000; 
                    4'd9: Cnode<= 7'b0000100; 
                    4'd10:Cnode<= 7'b0001000; 
                    4'd11:Cnode<= 7'b1100000; 
                    4'd12:Cnode<= 7'b0110001; 
                    4'd13:Cnode<= 7'b1000010; 
                    4'd14:Cnode<= 7'b0110000; 
                    4'd15:Cnode<= 7'b0111000; 
                endcase
            end
            
            
    endmodule