data/full_repos/permissive/452016975/src/register_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/452016975/src/register_test.v:14: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/register_test.v:16: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/452016975/src/register_test.v:20: Unsupported: Ignoring delay on this delayed statement.\n #50 clk=~clk; \n ^\n%Error: data/full_repos/permissive/452016975/src/register_test.v:24: Unsupported or unknown PLI call: $monitor\n  $monitor("Time=%2d,ReadReg1:%3b,ReadReg2:%3b,WriteReg:%3b,write_data:%32b,RegWrite:%1b,ReadData1:%32b,ReadData2:%32b",$time,read_reg1,read_reg2,write_reg,write_data,reg_write,read_data1,read_data2);\n  ^~~~~~~~\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module register_test();

reg clk;
reg reg_write;
reg [2:0] read_reg1,read_reg2,write_reg;
reg [31:0] write_data;

wire [31:0] read_data1,read_data2;

register_block _reg(read_reg1,read_reg2,write_reg,write_data,reg_write,read_data1,read_data2,clk);

initial begin 
	clk = 0; read_reg1 = 3'b100;read_reg2 = 3'b011; write_reg = 3'b011; write_data = 32'b1111;  reg_write = 1'b0;
 #50;
 clk = 1; read_reg1 = 3'b011;read_reg2 = 3'b111; write_reg = 3'b010; write_data = 32'b1111;  reg_write = 1'b0;
 #50;
end
 
always begin 
	#50 clk=~clk; 
end

initial begin
  $monitor("Time=%2d,ReadReg1:%3b,ReadReg2:%3b,WriteReg:%3b,write_data:%32b,RegWrite:%1b,ReadData1:%32b,ReadData2:%32b",$time,read_reg1,read_reg2,write_reg,write_data,reg_write,read_data1,read_data2);
end

endmodule
module register_test();


reg clk;
reg reg_write;
reg [2:0] read_reg1,read_reg2,write_reg;
reg [31:0] write_data;

wire [31:0] read_data1,read_data2;

register_block _reg(read_reg1,read_reg2,write_reg,write_data,reg_write,read_data1,read_data2,clk);

initial begin 
	clk = 0; read_reg1 = 3'b100;read_reg2 = 3'b011; write_reg = 3'b011; write_data = 32'b1111;  reg_write = 1'b0;
 #50;
 clk = 1; read_reg1 = 3'b011;read_reg2 = 3'b111; write_reg = 3'b010; write_data = 32'b1111;  reg_write = 1'b0;
 #50;
end
 
always begin 
	#50 clk=~clk; 
end

initial begin
  $monitor("Time=%2d,ReadReg1:%3b,ReadReg2:%3b,WriteReg:%3b,write_data:%32b,RegWrite:%1b,ReadData1:%32b,ReadData2:%32b",$time,read_reg1,read_reg2,write_reg,write_data,reg_write,read_data1,read_data2);
end

endmodule