data/full_repos/permissive/502764644/Quartus Templates/SystemVerilog/Constructs/State Machines/State Machine with Enumerated Types.sv
1: b'%Error: Cannot find file containing module: Templates/SystemVerilog/Constructs/State\n        ... Looked in:\n             data/full_repos/permissive/502764644/Quartus/Templates/SystemVerilog/Constructs/State\n             data/full_repos/permissive/502764644/Quartus/Templates/SystemVerilog/Constructs/State.v\n             data/full_repos/permissive/502764644/Quartus/Templates/SystemVerilog/Constructs/State.sv\n             Templates/SystemVerilog/Constructs/State\n             Templates/SystemVerilog/Constructs/State.v\n             Templates/SystemVerilog/Constructs/State.sv\n             obj_dir/Templates/SystemVerilog/Constructs/State\n             obj_dir/Templates/SystemVerilog/Constructs/State.v\n             obj_dir/Templates/SystemVerilog/Constructs/State.sv\n%Error: Cannot find file containing module: Machines,data/full_repos/permissive/502764644\n%Error: Cannot find file containing module: data/full_repos/permissive/502764644/Quartus\n%Error: Cannot find file containing module: Machines/State\n%Error: Cannot find file containing module: Machine\n%Error: Cannot find file containing module: with\n%Error: Cannot find file containing module: Enumerated\n%Error: Cannot find file containing module: Types.sv\n%Error: Exiting due to 8 error(s)\n'
module enum_fsm (input clk, reset, input int data[3:0], output int o);
enum int unsigned { S0 = 0, S1 = 2, S2 = 4, S3 = 8 } state, next_state;
always_comb begin : next_state_logic
next_state = S0;
case(state)
S0: next_state = S1;
S1: next_state = S2;
S2: next_state = S3;
S3: next_state = S3;
endcase
end
always_comb begin
case(state)
S0: o = data[3];
S1: o = data[2];
S2: o = data[1];
S3: o = data[0];
endcase
end
always_ff@(posedge clk or negedge reset) begin
if(~reset)
state <= S0;
else
state <= next_state;
end
endmodule
module enum_fsm (input clk, reset, input int data[3:0], output int o);

enum int unsigned { S0 = 0, S1 = 2, S2 = 4, S3 = 8 } state, next_state;
always_comb begin : next_state_logic
next_state = S0;
case(state)
S0: next_state = S1;
S1: next_state = S2;
S2: next_state = S3;
S3: next_state = S3;
endcase
end
always_comb begin
case(state)
S0: o = data[3];
S1: o = data[2];
S2: o = data[1];
S3: o = data[0];
endcase
end
always_ff@(posedge clk or negedge reset) begin
if(~reset)
state <= S0;
else
state <= next_state;
end
endmodule