data/full_repos/permissive/496903659/028 module_addsub.v
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/496903659/028\n        ... Looked in:\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/028\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/028.v\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/028.sv\n             data/full_repos/permissive/496903659/028\n             data/full_repos/permissive/496903659/028.v\n             data/full_repos/permissive/496903659/028.sv\n             obj_dir/data/full_repos/permissive/496903659/028\n             obj_dir/data/full_repos/permissive/496903659/028.v\n             obj_dir/data/full_repos/permissive/496903659/028.sv\n%Error: Cannot find file containing module: module_addsub.v\n%Error: Exiting due to 2 error(s)\n'
module top_module(
    input [31:0] a,
    input [31:0] b,
    input sub,
    output [31:0] sum
);
   	wire carry, nouse;
    wire [31:0] bb;
    assign bb = sub ? (~b + 1) : b;	
    add16 obj0(a[15:0], bb[15:0], 0, sum[15:0], carry);
    add16 obj1(a[31:16], bb[31:16], carry, sum[31:16], nouse);
        
endmodule
module top_module(
    input [31:0] a,
    input [31:0] b,
    input sub,
    output [31:0] sum
);

   	wire carry, nouse;
    wire [31:0] bb;
    assign bb = sub ? (~b + 1) : b;	
    add16 obj0(a[15:0], bb[15:0], 0, sum[15:0], carry);
    add16 obj1(a[31:16], bb[31:16], carry, sum[31:16], nouse);
        
endmodule