data/full_repos/permissive/508522603/rtl/core/core_ifu.v
1: b'%Error: data/full_repos/permissive/508522603/rtl/core/core_ifu.v:24: Cannot find include file: core_defines.v\n`include "core_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/508522603/rtl/core,data/full_repos/permissive/508522603/core_defines.v\n             data/full_repos/permissive/508522603/rtl/core,data/full_repos/permissive/508522603/core_defines.v.v\n             data/full_repos/permissive/508522603/rtl/core,data/full_repos/permissive/508522603/core_defines.v.sv\n             core_defines.v\n             core_defines.v.v\n             core_defines.v.sv\n             obj_dir/core_defines.v\n             obj_dir/core_defines.v.v\n             obj_dir/core_defines.v.sv\n%Error: data/full_repos/permissive/508522603/rtl/core/core_ifu.v:30: Define or directive not defined: \'`CPU_PC_SIZE\'\n    output [`CPU_PC_SIZE-1:0] pc_addr,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/508522603/rtl/core/core_ifu.v:31: Define or directive not defined: \'`CPU_INSTR_SIZE\'\n    input  [`CPU_INSTR_SIZE-1:0] instr_fetched,\n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/508522603/rtl/core/core_ifu.v:35: Define or directive not defined: \'`CPU_PC_SIZE\'\n    output [`CPU_PC_SIZE-1:0] pc_o,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/508522603/rtl/core/core_ifu.v:36: Define or directive not defined: \'`CPU_INSTR_SIZE\'\n    output [`CPU_INSTR_SIZE-1:0] instr_o,  \n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/508522603/rtl/core/core_ifu.v:47: Define or directive not defined: \'`CPU_INSTR_SIZE\'\n    wire [`CPU_INSTR_SIZE-1:0] instr_fetched_me;\n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/508522603/rtl/core/core_ifu.v:48: Define or directive not defined: \'`CPU_PC_SIZE\'\n    wire [`CPU_PC_SIZE-1:0] pc_addr_me;\n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/508522603/rtl/core/core_ifu.v:49: Define or directive not defined: \'`CPU_PC_SIZE\'\n    wire [`CPU_PC_SIZE-1:0] pc_o_me;\n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/508522603/rtl/core/core_ifu.v:50: Define or directive not defined: \'`CPU_INSTR_SIZE\'\n    wire [`CPU_INSTR_SIZE-1:0] instr_o_me;\n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/508522603/rtl/core/core_ifu.v:58: Define or directive not defined: \'`Hold_Pc\'\n    assign pc_o_me = (instr_fetched_me == `Hold_Pc) ? pc_o_me : (pc_o_me + 4\'b4);\n                                          ^~~~~~~~\n%Error: data/full_repos/permissive/508522603/rtl/core/core_ifu.v:58: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign pc_o_me = (instr_fetched_me == `Hold_Pc) ? pc_o_me : (pc_o_me + 4\'b4);\n                                                  ^\n%Error: data/full_repos/permissive/508522603/rtl/core/core_ifu.v:58: Illegal character in binary constant: 4\n    assign pc_o_me = (instr_fetched_me == `Hold_Pc) ? pc_o_me : (pc_o_me + 4\'b4);\n                                                                           ^~~~\n%Error: data/full_repos/permissive/508522603/rtl/core/core_ifu.v:64: syntax error, unexpected endmodule, expecting TYPE-IDENTIFIER\nendmodule\n^~~~~~~~~\n%Error: Cannot continue\n'
module core_ifu #(

) (

    output [`CPU_PC_SIZE-1:0] pc_addr,
    input  [`CPU_INSTR_SIZE-1:0] instr_fetched,



    output [`CPU_PC_SIZE-1:0] pc_o,
    output [`CPU_INSTR_SIZE-1:0] instr_o,  





    input clk,
    input rst_n
);
    

    wire [`CPU_INSTR_SIZE-1:0] instr_fetched_me;
    wire [`CPU_PC_SIZE-1:0] pc_addr_me;
    wire [`CPU_PC_SIZE-1:0] pc_o_me;
    wire [`CPU_INSTR_SIZE-1:0] instr_o_me;

    assign instr_fetched_me = instr_fetched;
    assign pc_addr = pc_addr_me;

    assign instr_o = instr_o_me;

    assign pc_addr_me = pc_o_me;
    assign pc_o_me = (instr_fetched_me == `Hold_Pc) ? pc_o_me : (pc_o_me + 4'b4);
    assign instr_o_me = 




endmodule
module core_ifu #(

) (

    output [`CPU_PC_SIZE-1:0] pc_addr,
    input  [`CPU_INSTR_SIZE-1:0] instr_fetched,



    output [`CPU_PC_SIZE-1:0] pc_o,
    output [`CPU_INSTR_SIZE-1:0] instr_o,  





    input clk,
    input rst_n
);

    

    wire [`CPU_INSTR_SIZE-1:0] instr_fetched_me;
    wire [`CPU_PC_SIZE-1:0] pc_addr_me;
    wire [`CPU_PC_SIZE-1:0] pc_o_me;
    wire [`CPU_INSTR_SIZE-1:0] instr_o_me;

    assign instr_fetched_me = instr_fetched;
    assign pc_addr = pc_addr_me;

    assign instr_o = instr_o_me;

    assign pc_addr_me = pc_o_me;
    assign pc_o_me = (instr_fetched_me == `Hold_Pc) ? pc_o_me : (pc_o_me + 4'b4);
    assign instr_o_me = 




endmodule