data/full_repos/permissive/500128826/HDLBits/Modules/Module_fadd/add16.v
1: b"%Error: data/full_repos/permissive/500128826/HDLBits/Modules/Module_fadd/add16.v:23: Cannot find file containing module: 'add1'\n      add1 aN (\n      ^~~~\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Modules/Module_fadd,data/full_repos/permissive/500128826/add1\n             data/full_repos/permissive/500128826/HDLBits/Modules/Module_fadd,data/full_repos/permissive/500128826/add1.v\n             data/full_repos/permissive/500128826/HDLBits/Modules/Module_fadd,data/full_repos/permissive/500128826/add1.sv\n             add1\n             add1.v\n             add1.sv\n             obj_dir/add1\n             obj_dir/add1.v\n             obj_dir/add1.sv\n%Error: Exiting due to 1 error(s)\n"
module add16 (
    input wire [15:0] a,
    input wire [15:0] b,
    input wire cin,
    output wire [15:0] sum,
    output wire cout
);

  wire carry[15:0];

  generate
    genvar i;
    for (i = 0; i < 16; i = i + 1) begin
      add1 aN (
          a[i],
          b[i],
          (i == 0) ? cin : carry[i-1],
          sum[i],
          carry[i]
      );
    end
  endgenerate

  assign cout = carry[$bits(sum)-1];
endmodule
module add16 (
    input wire [15:0] a,
    input wire [15:0] b,
    input wire cin,
    output wire [15:0] sum,
    output wire cout
);


  wire carry[15:0];

  generate
    genvar i;
    for (i = 0; i < 16; i = i + 1) begin
      add1 aN (
          a[i],
          b[i],
          (i == 0) ? cin : carry[i-1],
          sum[i],
          carry[i]
      );
    end
  endgenerate

  assign cout = carry[$bits(sum)-1];
endmodule