data/full_repos/permissive/488835089/level-1/level-2/level-3/counter_0_7_tb.v
1: b'%Error: data/full_repos/permissive/488835089/level-1/level-2/level-3/counter_0_7_tb.v:1: Cannot find include file: counter_0_7.v\n`include "counter_0_7.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/488835089/level-1/level-2/level-3,data/full_repos/permissive/488835089/counter_0_7.v\n             data/full_repos/permissive/488835089/level-1/level-2/level-3,data/full_repos/permissive/488835089/counter_0_7.v.v\n             data/full_repos/permissive/488835089/level-1/level-2/level-3,data/full_repos/permissive/488835089/counter_0_7.v.sv\n             counter_0_7.v\n             counter_0_7.v.v\n             counter_0_7.v.sv\n             obj_dir/counter_0_7.v\n             obj_dir/counter_0_7.v.v\n             obj_dir/counter_0_7.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/488835089/level-1/level-2/level-3/counter_0_7_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n    always #0.5 CLK = ~CLK;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/488835089/level-1/level-2/level-3/counter_0_7_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/488835089/level-1/level-2/level-3/counter_0_7_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/488835089/level-1/level-2/level-3/counter_0_7_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/488835089/level-1/level-2/level-3/counter_0_7_tb.v:29: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("counter_0_7.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/488835089/level-1/level-2/level-3/counter_0_7_tb.v:30: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, counter_0_7_tb);\n        ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 4 warning(s)\n'
module counter_0_7_tb();

    reg CLK, CLEAR;
    wire OUT;

    counter_0_7 dut(CLK, CLEAR, OUT);

    always #0.5 CLK = ~CLK;

    initial begin
        
        CLK = 0;

        CLEAR = 0;
        #2;

        CLEAR = 1;
        #20;

        CLEAR = 0;
        #10;

        $finish();
    end

    initial begin
        $dumpfile("counter_0_7.vcd");
        $dumpvars(0, counter_0_7_tb);
    end
endmodule
module counter_0_7_tb();


    reg CLK, CLEAR;
    wire OUT;

    counter_0_7 dut(CLK, CLEAR, OUT);

    always #0.5 CLK = ~CLK;

    initial begin
        
        CLK = 0;

        CLEAR = 0;
        #2;

        CLEAR = 1;
        #20;

        CLEAR = 0;
        #10;

        $finish();
    end

    initial begin
        $dumpfile("counter_0_7.vcd");
        $dumpvars(0, counter_0_7_tb);
    end
endmodule