data/full_repos/permissive/459421171/Pipelined/execute_new.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/459421171/Pipelined/execute_new.v:416: Little bit endian vector: MSB < LSB of bit range: 0:63\ninput[0:63] x,y;\n     ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/459421171/Pipelined/execute_new.v:417: Little bit endian vector: MSB < LSB of bit range: 0:63\noutput[0:63]z;\n      ^\n%Error: Exiting due to 2 warning(s)\n'
module full_adder(x,y,carry_in,sum,carry);
   input signed x,y,carry_in;
   output signed sum,carry;
   wire signed w1,w2,w3,w4,w5;
   xor(w1,x,y);
   xor(sum,w1,carry_in);
   and(w2,x,y);
   and(w3,x,carry_in);
   and(w4,y,carry_in);
   or(w5,w2,w3);
   or(carry,w5,w4);
endmodule
module full_adder(x,y,carry_in,sum,carry);

   input signed x,y,carry_in;
   output signed sum,carry;
   wire signed w1,w2,w3,w4,w5;
   xor(w1,x,y);
   xor(sum,w1,carry_in);
   and(w2,x,y);
   and(w3,x,carry_in);
   and(w4,y,carry_in);
   or(w5,w2,w3);
   or(carry,w5,w4);
endmodule