data/full_repos/permissive/420726213/verilog/dv/tb/pin_compress_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/420726213/verilog/dv/tb/pin_compress_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n   #10\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/420726213/verilog/dv/tb/pin_compress_tb.v:14: Cannot find file containing module: \'pin_compress\'\npin_compress #(\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/420726213/verilog/dv/tb,data/full_repos/permissive/420726213/pin_compress\n             data/full_repos/permissive/420726213/verilog/dv/tb,data/full_repos/permissive/420726213/pin_compress.v\n             data/full_repos/permissive/420726213/verilog/dv/tb,data/full_repos/permissive/420726213/pin_compress.sv\n             pin_compress\n             pin_compress.v\n             pin_compress.sv\n             obj_dir/pin_compress\n             obj_dir/pin_compress.v\n             obj_dir/pin_compress.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pin_compress_tb ();

parameter WIDTH = 16;

reg [WIDTH-1:0] data;
reg [WIDTH-1:0] mask;
wire [WIDTH-1:0] result;

pin_compress #(
   .WIDTH(WIDTH)
) pin_compress_dut (
   .data(data),
   .mask(mask),
   .result(result)
);

initial begin
   data <= 16'b1001110100110101;
   mask <= 16'b0100100101000101;
   #10
   $display("%16b", result);
   $display("%16b", 16'b0000000000011011);
end

endmodule
module pin_compress_tb ();


parameter WIDTH = 16;

reg [WIDTH-1:0] data;
reg [WIDTH-1:0] mask;
wire [WIDTH-1:0] result;

pin_compress #(
   .WIDTH(WIDTH)
) pin_compress_dut (
   .data(data),
   .mask(mask),
   .result(result)
);

initial begin
   data <= 16'b1001110100110101;
   mask <= 16'b0100100101000101;
   #10
   $display("%16b", result);
   $display("%16b", 16'b0000000000011011);
end

endmodule