data/full_repos/permissive/504677412/src/audio_wr_burst_afifo.v
1: b'%Error: data/full_repos/permissive/504677412/src/audio_wr_burst_afifo.v:3: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/504677412/src,data/full_repos/permissive/504677412/defines.v\n             data/full_repos/permissive/504677412/src,data/full_repos/permissive/504677412/defines.v.v\n             data/full_repos/permissive/504677412/src,data/full_repos/permissive/504677412/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/504677412/src/audio_wr_burst_afifo.v:26: Define or directive not defined: \'`PCM_DSIZE\'\n  input  wire [`PCM_DSIZE-1:0]      wr_data_i;\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/audio_wr_burst_afifo.v:32: Define or directive not defined: \'`DSIZE\'\n  output wire [`DSIZE-1:0]          burst_rd_data;\n               ^~~~~~\n%Error: data/full_repos/permissive/504677412/src/audio_wr_burst_afifo.v:66: Define or directive not defined: \'`MEM_WR_BL\'\n  assign burst_avail = (!empty) & rd_data_count_d1 >= `MEM_WR_BL ? 1\'b1 : 1\'b0;\n                                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/audio_wr_burst_afifo.v:66: syntax error, unexpected \'?\', expecting TYPE-IDENTIFIER\n  assign burst_avail = (!empty) & rd_data_count_d1 >= `MEM_WR_BL ? 1\'b1 : 1\'b0;\n                                                                 ^\n%Error: Exiting due to 5 error(s)\n'
module audio_wr_burst_afifo (

  wr_rst,
  wr_clk,
  wr_vld_i,
  wr_rdy_o,
  wr_data_i,

  rd_rst,
  rd_clk,
  burst_avail,
  burst_rd_en,
  burst_rd_data,
  err_bfifo_full
);
  

  input  wire                       wr_rst;
  input  wire                       wr_clk;
  input  wire                       wr_vld_i;
  output wire                       wr_rdy_o;
  input  wire [`PCM_DSIZE-1:0]      wr_data_i;

  input  wire                       rd_rst;
  input  wire                       rd_clk;
  output wire                       burst_avail;
  input  wire                       burst_rd_en;
  output wire [`DSIZE-1:0]          burst_rd_data;
  output reg                        err_bfifo_full;


  

  wire                              full;
  wire                              empty;
  wire [31:0]                       burst_rd_data_i;
  wire [9:0]                        rd_data_count;
  reg  [9:0]                        rd_data_count_d1;

  
  afifo_fwft_w16r32x512 i_afifo_fwft_w16r32x512 (
    .WrClk               (wr_clk),
    .WrReset             (wr_rst),
    .WrEn                (wr_vld_i),
    .Data                (wr_data_i),
    .Full                (full),
    .RdClk               (rd_clk),
    .RdReset             (rd_rst),
    .RdEn                (burst_rd_en),
    .Q                   (burst_rd_data_i),
    .Rnum                (rd_data_count),
    .Empty               (empty)
  );
    
  assign wr_rdy_o = ~full;
  

  always @(posedge rd_clk) begin
    rd_data_count_d1 <= rd_data_count;
  end
  
  assign burst_avail = (!empty) & rd_data_count_d1 >= `MEM_WR_BL ? 1'b1 : 1'b0;
  
  assign burst_rd_data = {4'b0, burst_rd_data_i};
  

  always@(posedge wr_clk or posedge wr_rst) begin
    if(wr_rst) begin
      err_bfifo_full <= 1'b0;
    end else if(full & wr_vld_i) begin
      err_bfifo_full <= 1'b1;
      `ifdef SIM_ENABLE
        $display ("ERROR: Write Burst FIFO full error..!");
        $stop;
      `endif
    end      
  end
  
endmodule
module audio_wr_burst_afifo (

  wr_rst,
  wr_clk,
  wr_vld_i,
  wr_rdy_o,
  wr_data_i,

  rd_rst,
  rd_clk,
  burst_avail,
  burst_rd_en,
  burst_rd_data,
  err_bfifo_full
);

  

  input  wire                       wr_rst;
  input  wire                       wr_clk;
  input  wire                       wr_vld_i;
  output wire                       wr_rdy_o;
  input  wire [`PCM_DSIZE-1:0]      wr_data_i;

  input  wire                       rd_rst;
  input  wire                       rd_clk;
  output wire                       burst_avail;
  input  wire                       burst_rd_en;
  output wire [`DSIZE-1:0]          burst_rd_data;
  output reg                        err_bfifo_full;


  

  wire                              full;
  wire                              empty;
  wire [31:0]                       burst_rd_data_i;
  wire [9:0]                        rd_data_count;
  reg  [9:0]                        rd_data_count_d1;

  
  afifo_fwft_w16r32x512 i_afifo_fwft_w16r32x512 (
    .WrClk               (wr_clk),
    .WrReset             (wr_rst),
    .WrEn                (wr_vld_i),
    .Data                (wr_data_i),
    .Full                (full),
    .RdClk               (rd_clk),
    .RdReset             (rd_rst),
    .RdEn                (burst_rd_en),
    .Q                   (burst_rd_data_i),
    .Rnum                (rd_data_count),
    .Empty               (empty)
  );
    
  assign wr_rdy_o = ~full;
  

  always @(posedge rd_clk) begin
    rd_data_count_d1 <= rd_data_count;
  end
  
  assign burst_avail = (!empty) & rd_data_count_d1 >= `MEM_WR_BL ? 1'b1 : 1'b0;
  
  assign burst_rd_data = {4'b0, burst_rd_data_i};
  

  always@(posedge wr_clk or posedge wr_rst) begin
    if(wr_rst) begin
      err_bfifo_full <= 1'b0;
    end else if(full & wr_vld_i) begin
      err_bfifo_full <= 1'b1;
      `ifdef SIM_ENABLE
        $display ("ERROR: Write Burst FIFO full error..!");
        $stop;
      `endif
    end      
  end
  
endmodule