data/full_repos/permissive/441359809/src/yosys/manual/APPNOTE_011_Design_Investigation/foobaraddsub.v
data/verilator_xmls/6bfcea8e-b76f-4268-b21b-8f8350210cbb.xml
module foobaraddsub(a, b, c, d, fa, fs, ba, bs);
  input [7:0] a, b, c, d;
  output [7:0] fa, fs, ba, bs;
  assign fa = a + (* foo *) b;
  assign fs = a - (* foo *) b;
  assign ba = c + (* bar *) d;
  assign bs = c - (* bar *) d;
endmodule
module foobaraddsub(a, b, c, d, fa, fs, ba, bs);

  input [7:0] a, b, c, d;
  output [7:0] fa, fs, ba, bs;
  assign fa = a + (* foo *) b;
  assign fs = a - (* foo *) b;
  assign ba = c + (* bar *) d;
  assign bs = c - (* bar *) d;
endmodule