data/full_repos/permissive/435516446/MIPS/WriteBack_TEST.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/WriteBack_TEST.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #50 MemtoReg = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/WriteBack_TEST.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/435516446/MIPS/WriteBack_TEST.v:36: Cannot find file containing module: \'WriteBack\'\n WriteBack uut (\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/WriteBack\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/WriteBack.v\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/WriteBack.sv\n             WriteBack\n             WriteBack.v\n             WriteBack.sv\n             obj_dir/WriteBack\n             obj_dir/WriteBack.v\n             obj_dir/WriteBack.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module WriteBack_TEST;


	reg MemtoReg;
	reg [31:0] readData;
	reg [31:0] ALUResult;


	wire [31:0] writeData;


	WriteBack uut (
		.MemtoReg(MemtoReg), 
		.readData(readData), 
		.ALUResult(ALUResult), 
		.writeData(writeData)
	);

	initial begin

		MemtoReg = 0;
		readData = $random;
		ALUResult = 0;

		#50 MemtoReg = 1;

		#100;
        


	end
      
endmodule
module WriteBack_TEST;



	reg MemtoReg;
	reg [31:0] readData;
	reg [31:0] ALUResult;


	wire [31:0] writeData;


	WriteBack uut (
		.MemtoReg(MemtoReg), 
		.readData(readData), 
		.ALUResult(ALUResult), 
		.writeData(writeData)
	);

	initial begin

		MemtoReg = 0;
		readData = $random;
		ALUResult = 0;

		#50 MemtoReg = 1;

		#100;
        


	end
      
endmodule