data/full_repos/permissive/499017203/DSP_fir.v
1: b"%Error: data/full_repos/permissive/499017203/DSP_fir.v:27: Cannot find file containing module: 'dff'\ndff ff1(.d(mcm3),.clk(clock),.q(Q1));\n^~~\n        ... Looked in:\n             data/full_repos/permissive/499017203,data/full_repos/permissive/499017203/dff\n             data/full_repos/permissive/499017203,data/full_repos/permissive/499017203/dff.v\n             data/full_repos/permissive/499017203,data/full_repos/permissive/499017203/dff.sv\n             dff\n             dff.v\n             dff.sv\n             obj_dir/dff\n             obj_dir/dff.v\n             obj_dir/dff.sv\n%Error: data/full_repos/permissive/499017203/DSP_fir.v:28: Cannot find file containing module: 'dff'\ndff ff2(.d(add1),.clk(clock),.q(Q2));\n^~~\n%Error: data/full_repos/permissive/499017203/DSP_fir.v:29: Cannot find file containing module: 'dff'\ndff ff3(.d(add2),.clk(clock),.q(Q3));\n^~~\n%Error: Exiting due to 3 error(s)\n"
module DSP_fir(output reg signed[15:0]o_acc,input signed[7:0] i_a,input clock);
wire signed [7:0]h0,h1,h2,h3;
wire signed [15:0] mcm0,mcm1,mcm2,mcm3,add1,add2,add3;
wire signed [15:0] Q1,Q2,Q3;


assign h0=-2;
assign h1=-1;
assign h2=-3;
assign h3=4;


assign mcm0=h0*i_a;
assign mcm1=h1*i_a;
assign mcm2=h2*i_a;
assign mcm3=h3*i_a;


assign add1=Q1+mcm2;
assign add2=Q2+mcm1;
assign add3=Q3+mcm0;


dff ff1(.d(mcm3),.clk(clock),.q(Q1));
dff ff2(.d(add1),.clk(clock),.q(Q2));
dff ff3(.d(add2),.clk(clock),.q(Q3));

always@(posedge clock)
		o_acc<=add3;
endmodule
module DSP_fir(output reg signed[15:0]o_acc,input signed[7:0] i_a,input clock);

wire signed [7:0]h0,h1,h2,h3;
wire signed [15:0] mcm0,mcm1,mcm2,mcm3,add1,add2,add3;
wire signed [15:0] Q1,Q2,Q3;


assign h0=-2;
assign h1=-1;
assign h2=-3;
assign h3=4;


assign mcm0=h0*i_a;
assign mcm1=h1*i_a;
assign mcm2=h2*i_a;
assign mcm3=h3*i_a;


assign add1=Q1+mcm2;
assign add2=Q2+mcm1;
assign add3=Q3+mcm0;


dff ff1(.d(mcm3),.clk(clock),.q(Q1));
dff ff2(.d(add1),.clk(clock),.q(Q2));
dff ff3(.d(add2),.clk(clock),.q(Q3));

always@(posedge clock)
		o_acc<=add3;
endmodule