data/full_repos/permissive/487568919/basic_verilog/pwm_modulator.sv
1: b"%Error: data/full_repos/permissive/487568919/basic_verilog/pwm_modulator.sv:55: Cannot find file containing module: 'clk_divider'\nclk_divider #(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/487568919/basic_verilog,data/full_repos/permissive/487568919/clk_divider\n             data/full_repos/permissive/487568919/basic_verilog,data/full_repos/permissive/487568919/clk_divider.v\n             data/full_repos/permissive/487568919/basic_verilog,data/full_repos/permissive/487568919/clk_divider.sv\n             clk_divider\n             clk_divider.v\n             clk_divider.sv\n             obj_dir/clk_divider\n             obj_dir/clk_divider.v\n             obj_dir/clk_divider.sv\n%Error: data/full_repos/permissive/487568919/basic_verilog/pwm_modulator.sv:71: Cannot find file containing module: 'pulse_gen'\npulse_gen #(\n^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module pwm_modulator #( parameter
  CLK_HZ = 100_000_000,
  PWM_PERIOD_DIV = 16,
  PWM_PERIOD_HZ = CLK_HZ / (2**PWM_PERIOD_DIV),

  MOD_WIDTH = 8
)(
  input clk,
  input nrst,

  input [MOD_WIDTH-1:0] mod_setpoint,
  output pwm_out,


  output start_strobe,
  output busy
);



logic [31:0] div_clk;
clk_divider #(
  .WIDTH( 32 )
) cd1 (
  .clk( clk ),
  .nrst( nrst ),
  .ena( 1'b1 ),
  .out( div_clk[31:0] )
);



logic [MOD_WIDTH-1:0] mod_setpoint_inv;
assign mod_setpoint_inv[MOD_WIDTH-1:0] = {MOD_WIDTH{1'b1}} - mod_setpoint[MOD_WIDTH-1:0];



pulse_gen #(
  .CNTR_WIDTH( MOD_WIDTH+1 )
) pg1 (
  .clk( div_clk[(PWM_PERIOD_DIV-1)-MOD_WIDTH] ),
  .nrst( nrst ),

  .start( 1'b1 ),
  .cntr_max( {1'b0, {MOD_WIDTH{1'b1}} } ),
  .cntr_low( {1'b0, mod_setpoint_inv[MOD_WIDTH-1:0] } ),

  .pulse_out( pwm_out ),

  .start_strobe( start_strobe ),
  .busy( busy )
);


endmodule
module pwm_modulator #( parameter
  CLK_HZ = 100_000_000,
  PWM_PERIOD_DIV = 16,
  PWM_PERIOD_HZ = CLK_HZ / (2**PWM_PERIOD_DIV),

  MOD_WIDTH = 8
)(
  input clk,
  input nrst,

  input [MOD_WIDTH-1:0] mod_setpoint,
  output pwm_out,


  output start_strobe,
  output busy
);




logic [31:0] div_clk;
clk_divider #(
  .WIDTH( 32 )
) cd1 (
  .clk( clk ),
  .nrst( nrst ),
  .ena( 1'b1 ),
  .out( div_clk[31:0] )
);



logic [MOD_WIDTH-1:0] mod_setpoint_inv;
assign mod_setpoint_inv[MOD_WIDTH-1:0] = {MOD_WIDTH{1'b1}} - mod_setpoint[MOD_WIDTH-1:0];



pulse_gen #(
  .CNTR_WIDTH( MOD_WIDTH+1 )
) pg1 (
  .clk( div_clk[(PWM_PERIOD_DIV-1)-MOD_WIDTH] ),
  .nrst( nrst ),

  .start( 1'b1 ),
  .cntr_max( {1'b0, {MOD_WIDTH{1'b1}} } ),
  .cntr_low( {1'b0, mod_setpoint_inv[MOD_WIDTH-1:0] } ),

  .pulse_out( pwm_out ),

  .start_strobe( start_strobe ),
  .busy( busy )
);


endmodule