data/full_repos/permissive/46522718/KEY_MUX.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/46522718/KEY_MUX.v:92: Signal definition not found, creating implicitly: \'parity\'\n assign parity = register[1]; \n        ^~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/46522718/KEY_MUX.v:17: Signal definition not found, creating implicitly: \'parity_error\'\n ps keyboard(PS2_CLK, PS2_DAT, scan_code, parity_error, rdy);\n                                          ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/46522718/KEY_MUX.v:17: Signal definition not found, creating implicitly: \'rdy\'\n ps keyboard(PS2_CLK, PS2_DAT, scan_code, parity_error, rdy);\n                                                        ^~~\n%Error: Exiting due to 3 warning(s)\n'
module ps(clk,data,scan_code,parity_error,rdy); 

 input clk;
 input data;
 output[7:0] scan_code;
 output parity_error;
 output rdy;
  

 reg[9:0] register; 
 reg[3:0] counter; 
 reg parity_error, rdy; 
  
 assign scan_code = register[9:2]; 
 assign parity = register[1]; 
  

 always @ (negedge clk) 
  begin 
   register <= {register[8:0], data};
   if (counter == 4'b1011) 
     counter <= 4'b0000; 
   else 
     counter <= counter + 4'b1; 
  end 
  

 always @ (posedge clk) 
  begin 
   if (counter == 4'b1011) 
     if (!parity == ^scan_code)
      rdy <= 1'b1; 
     else 
      parity_error <= 1'b1; 
   else
    begin 
     rdy <= 1'b0; 
     parity_error <= 1'b0; 
    end 
  end 
  
endmodule
module ps(clk,data,scan_code,parity_error,rdy);
 

 input clk;
 input data;
 output[7:0] scan_code;
 output parity_error;
 output rdy;
  

 reg[9:0] register; 
 reg[3:0] counter; 
 reg parity_error, rdy; 
  
 assign scan_code = register[9:2]; 
 assign parity = register[1]; 
  

 always @ (negedge clk) 
  begin 
   register <= {register[8:0], data};
   if (counter == 4'b1011) 
     counter <= 4'b0000; 
   else 
     counter <= counter + 4'b1; 
  end 
  

 always @ (posedge clk) 
  begin 
   if (counter == 4'b1011) 
     if (!parity == ^scan_code)
      rdy <= 1'b1; 
     else 
      parity_error <= 1'b1; 
   else
    begin 
     rdy <= 1'b0; 
     parity_error <= 1'b0; 
    end 
  end 
  
endmodule