data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Basic_Gates/45_GND_q4i.v
data/verilator_xmls/1eb046e9-ba87-4728-ada5-f6f61c5a91e9.xml
module top_module (
    output out);

    assign out = 1'b0;
endmodule
module top_module (
    output out);


    assign out = 1'b0;
endmodule