data/full_repos/permissive/492772061/ADPPulse/slow/ADP_Sim_Slow.srcs/sources_1/new/counterDisplay.v
data/verilator_xmls/973b0493-1c29-49ef-b0cc-2f347b4561fb.xml
module counterDisplay(
    input clk,
    input enable,
    input clear,
    input aa,
    output [31:0] NoP
    );
    
	reg [23:0]clkdiv = 24'd0;
    
    reg [31:0] NoPbuf;
    
    assign NoP = NoPbuf;
    
    initial NoPbuf <= 0;
    
    always @ (posedge clk) begin
       if (clear)
            NoPbuf = 32'h0;
        
       if (aa)
            NoPbuf = 32'h10000000;
              
       if (enable) begin
            
            clkdiv <= clkdiv +1'd1;
            if (clkdiv >= 1000000) begin
                clkdiv <= 0;
                NoPbuf <= NoPbuf +1;
            end
        
        end
    end
endmodule
module counterDisplay(
    input clk,
    input enable,
    input clear,
    input aa,
    output [31:0] NoP
    );

    
	reg [23:0]clkdiv = 24'd0;
    
    reg [31:0] NoPbuf;
    
    assign NoP = NoPbuf;
    
    initial NoPbuf <= 0;
    
    always @ (posedge clk) begin
       if (clear)
            NoPbuf = 32'h0;
        
       if (aa)
            NoPbuf = 32'h10000000;
              
       if (enable) begin
            
            clkdiv <= clkdiv +1'd1;
            if (clkdiv >= 1000000) begin
                clkdiv <= 0;
                NoPbuf <= NoPbuf +1;
            end
        
        end
    end
endmodule