data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/argmax/test/testbench.v
1: b'%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/argmax/test/testbench.v:35: Unsupported or unknown PLI call: $urandom\n      ini[j] = $urandom%100;\n               ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/argmax/test/testbench.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();

  parameter S = 5;
  parameter M = 8;

  reg [M-1:0] ini [2**S-1:0];
  wire [(2**S)*M-1:0] in;
  wire [M-1:0] max;
  wire [S-1:0] ind;

  argmax
  #(
    .S(S),
    .M(M)
  )
  uut
  (
    .in(in),
    .max(max),
    .ind(ind)
  );


  genvar i;
  generate
  for(i=0;i<2**S;i=i+1) begin:TEST_GEN1
    assign in[(i+1)*M-1:i*M] = ini[i];
  end
  endgenerate

  integer j;
  initial begin
    $display("S = %d, M = %d", S, M);
    for(j=0;j<2**S;j=j+1) begin
      ini[j] = $urandom%100;
      $display("ini[%d] = %d",j ,ini[j]);
    end
    #10
    $display("max = %d, ind = %d", max, ind);
    $finish;
  end


endmodule
module testbench();


  parameter S = 5;
  parameter M = 8;

  reg [M-1:0] ini [2**S-1:0];
  wire [(2**S)*M-1:0] in;
  wire [M-1:0] max;
  wire [S-1:0] ind;

  argmax
  #(
    .S(S),
    .M(M)
  )
  uut
  (
    .in(in),
    .max(max),
    .ind(ind)
  );


  genvar i;
  generate
  for(i=0;i<2**S;i=i+1) begin:TEST_GEN1
    assign in[(i+1)*M-1:i*M] = ini[i];
  end
  endgenerate

  integer j;
  initial begin
    $display("S = %d, M = %d", S, M);
    for(j=0;j<2**S;j=j+1) begin
      ini[j] = $urandom%100;
      $display("ini[%d] = %d",j ,ini[j]);
    end
    #10
    $display("max = %d, ind = %d", max, ind);
    $finish;
  end


endmodule