data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/Processor/halfadder.v
data/verilator_xmls/330b8be2-80a7-4a77-85cc-4163f096e77c.xml
module halfadder(
	input a,b,
	output s,c
    );
assign c=a&b;
assign s=a^b;

endmodule
module halfadder(
	input a,b,
	output s,c
    );

assign c=a&b;
assign s=a^b;

endmodule