data/full_repos/permissive/478063538/RAM1.v
data/verilator_xmls/a50a68bb-c97d-407d-8ee0-1c2d88753dd6.xml
module RAM1 (
	input [9:0] addr,
	input [7:0] datain,
	input clk, we,
	output [7:0] dataout
);

	reg [7:0] M[0:1023];
	

	always@(posedge clk)
	begin
		if(we == 0)
			M[addr] <= datain;
	end
	

	assign dataout = M[addr];

endmodule
module RAM1 (
	input [9:0] addr,
	input [7:0] datain,
	input clk, we,
	output [7:0] dataout
);


	reg [7:0] M[0:1023];
	

	always@(posedge clk)
	begin
		if(we == 0)
			M[addr] <= datain;
	end
	

	assign dataout = M[addr];

endmodule