data/full_repos/permissive/527176783/Single/A_Single/dataMEM.v
1: b'%Warning-WIDTH: data/full_repos/permissive/527176783/Single/A_Single/dataMEM.v:13: Bit extraction of array[255:0] requires 8 bit index, not 5 bits.\n                                                                                 : ... In instance dataMEM\n    assign data_out = data_mem[address[6:2]];\n                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/527176783/Single/A_Single/dataMEM.v:17: Bit extraction of array[255:0] requires 8 bit index, not 5 bits.\n                                                                                 : ... In instance dataMEM\n            data_mem[address[6:2]] <= wdata;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/527176783/Single/A_Single/dataMEM.v:18: Bit extraction of array[255:0] requires 8 bit index, not 5 bits.\n                                                                                 : ... In instance dataMEM\n        else data_mem[address[6:2]] <= data_mem[address[6:2]];\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/527176783/Single/A_Single/dataMEM.v:18: Bit extraction of array[255:0] requires 8 bit index, not 5 bits.\n                                                                                 : ... In instance dataMEM\n        else data_mem[address[6:2]] <= data_mem[address[6:2]];\n                                               ^\n%Error: Exiting due to 4 warning(s)\n'
module dataMEM(
    input           clk,
    input           w_en,
    input  [31:0]   wdata,
    input  [31:0]   address,
    output [31:0]   data_out
);
    reg [31:0] data_mem [0:255];



    assign data_out = data_mem[address[6:2]];

    always @(posedge clk) begin
        if(w_en)
            data_mem[address[6:2]] <= wdata;
        else data_mem[address[6:2]] <= data_mem[address[6:2]];
    end


endmodule
module dataMEM(
    input           clk,
    input           w_en,
    input  [31:0]   wdata,
    input  [31:0]   address,
    output [31:0]   data_out
);

    reg [31:0] data_mem [0:255];



    assign data_out = data_mem[address[6:2]];

    always @(posedge clk) begin
        if(w_en)
            data_mem[address[6:2]] <= wdata;
        else data_mem[address[6:2]] <= data_mem[address[6:2]];
    end


endmodule