data/full_repos/permissive/494696040/testbenches/t_Instruction_Fetch_Module.v
1: b'%Error: data/full_repos/permissive/494696040/testbenches/t_Instruction_Fetch_Module.v:31: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("dump.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/494696040/testbenches/t_Instruction_Fetch_Module.v:32: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/494696040/testbenches/t_Instruction_Fetch_Module.v:37: Unsupported: Ignoring delay on this delayed statement.\n    initial #200 $finish;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/494696040/testbenches/t_Instruction_Fetch_Module.v:59: Unsupported: Ignoring delay on this delayed statement.\n            #5 CLK = ~CLK;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/494696040/testbenches/t_Instruction_Fetch_Module.v:64: Unsupported: Ignoring delay on this delayed statement.\n        #45 RESET <= 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/494696040/testbenches/t_Instruction_Fetch_Module.v:65: Unsupported: Ignoring delay on this delayed statement.\n        #15 RESET <= 1\'b0;\n        ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module t_Instruction_Fetch_Module;
    reg RESET;
    reg CLK;
    wire [31:0] instruction_output;
    
    Instruction_Fetch_Module Ins_fetch_module1(RESET, CLK, instruction_output);
    

    initial begin
        $dumpfile("dump.vcd");
        $dumpvars;
    end
    
    

    initial #200 $finish;
    
    
    initial begin

        CLK <= 1'b0;
        

        Ins_fetch_module1.instruction_memory[0] <= 32'd1;
        Ins_fetch_module1.instruction_memory[1] <= 32'd1;
        Ins_fetch_module1.instruction_memory[2] <= 32'd2;
        Ins_fetch_module1.instruction_memory[3] <= 32'd3;
        Ins_fetch_module1.instruction_memory[4] <= 32'd5;
        Ins_fetch_module1.instruction_memory[5] <= 32'd8;
        Ins_fetch_module1.instruction_memory[6] <= 32'd13;
        Ins_fetch_module1.instruction_memory[7] <= 32'd21;
        Ins_fetch_module1.instruction_memory[8] <= 32'd35;
    end
    

    initial
        repeat(40)
            #5 CLK = ~CLK;
    

    initial begin
        RESET <= 1'b0;
        #45 RESET <= 1'b1;
        #15 RESET <= 1'b0;
    end
endmodule
module t_Instruction_Fetch_Module;

    reg RESET;
    reg CLK;
    wire [31:0] instruction_output;
    
    Instruction_Fetch_Module Ins_fetch_module1(RESET, CLK, instruction_output);
    

    initial begin
        $dumpfile("dump.vcd");
        $dumpvars;
    end
    
    

    initial #200 $finish;
    
    
    initial begin

        CLK <= 1'b0;
        

        Ins_fetch_module1.instruction_memory[0] <= 32'd1;
        Ins_fetch_module1.instruction_memory[1] <= 32'd1;
        Ins_fetch_module1.instruction_memory[2] <= 32'd2;
        Ins_fetch_module1.instruction_memory[3] <= 32'd3;
        Ins_fetch_module1.instruction_memory[4] <= 32'd5;
        Ins_fetch_module1.instruction_memory[5] <= 32'd8;
        Ins_fetch_module1.instruction_memory[6] <= 32'd13;
        Ins_fetch_module1.instruction_memory[7] <= 32'd21;
        Ins_fetch_module1.instruction_memory[8] <= 32'd35;
    end
    

    initial
        repeat(40)
            #5 CLK = ~CLK;
    

    initial begin
        RESET <= 1'b0;
        #45 RESET <= 1'b1;
        #15 RESET <= 1'b0;
    end
endmodule