data/full_repos/permissive/520452389/source_codes/Instruction_decode.v
data/verilator_xmls/2e96dc06-b42e-437b-9353-c464005c937c.xml
module dff2(input clk,
         input RegDst,input ALUSrc,input MemtoReg,input RegWrite,input MemRead,input MemWrite,input Branch,
	input ALUOp1,input ALUOp0,output reg RegDst_s2,output reg  ALUSrc_s2,output reg  MemtoReg_s2,
        output reg  RegWrite_s2,output reg  MemRead_s2,output reg  MemWrite_s2,output reg  Branch_s2,output  reg ALUOp1_s2,
        output reg  ALUOp0_s2,input  [31:0]pc_out1_s1,output reg [31:0]pc_out1_s2,input [31:0] extended_32,output reg  [31:0] extended_32_s2,
        input [4:0] source,input [4:0]dest_for_I,input [4:0]dest_for_R,output reg [4:0]dest_for_I_s2,output reg [4:0]dest_for_R_s2,
        input [31:0] read_data1,input [31:0] read_data2,output reg [31:0] read_data1_s2,output reg [31:0] read_data2_s2,output reg [4:0]source_s2);

always @(posedge clk) begin 
     RegDst_s2<=RegDst;
     ALUSrc_s2<=ALUSrc;
     MemtoReg_s2<=MemtoReg;
     RegWrite_s2<=RegWrite;
     MemRead_s2<=MemRead;
     MemWrite_s2<=MemWrite;
     Branch_s2<=Branch;
     ALUOp1_s2<=ALUOp1;
     ALUOp0_s2<=ALUOp0;
     extended_32_s2<=extended_32;
     dest_for_I_s2 <=dest_for_I;
     dest_for_R_s2<=dest_for_R;
     read_data1_s2<=read_data1;
     read_data2_s2<=read_data2;
     pc_out1_s2<=pc_out1_s1;
     source_s2<=source;
end

endmodule
module dff2(input clk,
         input RegDst,input ALUSrc,input MemtoReg,input RegWrite,input MemRead,input MemWrite,input Branch,
	input ALUOp1,input ALUOp0,output reg RegDst_s2,output reg  ALUSrc_s2,output reg  MemtoReg_s2,
        output reg  RegWrite_s2,output reg  MemRead_s2,output reg  MemWrite_s2,output reg  Branch_s2,output  reg ALUOp1_s2,
        output reg  ALUOp0_s2,input  [31:0]pc_out1_s1,output reg [31:0]pc_out1_s2,input [31:0] extended_32,output reg  [31:0] extended_32_s2,
        input [4:0] source,input [4:0]dest_for_I,input [4:0]dest_for_R,output reg [4:0]dest_for_I_s2,output reg [4:0]dest_for_R_s2,
        input [31:0] read_data1,input [31:0] read_data2,output reg [31:0] read_data1_s2,output reg [31:0] read_data2_s2,output reg [4:0]source_s2);


always @(posedge clk) begin 
     RegDst_s2<=RegDst;
     ALUSrc_s2<=ALUSrc;
     MemtoReg_s2<=MemtoReg;
     RegWrite_s2<=RegWrite;
     MemRead_s2<=MemRead;
     MemWrite_s2<=MemWrite;
     Branch_s2<=Branch;
     ALUOp1_s2<=ALUOp1;
     ALUOp0_s2<=ALUOp0;
     extended_32_s2<=extended_32;
     dest_for_I_s2 <=dest_for_I;
     dest_for_R_s2<=dest_for_R;
     read_data1_s2<=read_data1;
     read_data2_s2<=read_data2;
     pc_out1_s2<=pc_out1_s1;
     source_s2<=source;
end

endmodule