data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/vfmau/rtl/ct_vfmau_lza_simd_half.v
data/verilator_xmls/bbd8ff31-b367-4072-a476-6453b3080e54.xml
module ct_vfmau_lza_simd_half(
  addend,
  lza_result,
  lza_result_zero,
  sub_vld,
  summand
);


input   [23:0]  addend;         
input           sub_vld;        
input   [23:0]  summand;        
output  [4 :0]  lza_result;     
output          lza_result_zero; 


reg     [4 :0]  lza_result;     


wire    [23:0]  addend;         
wire    [23:0]  carry_d;        
wire    [23:0]  carry_g;        
wire    [23:0]  carry_p;        
wire    [23:0]  lza_precod;     
wire            lza_result_zero; 
wire            sub_vld;        
wire    [23:0]  summand;        











assign carry_p[23:0] = summand[23:0] ^ addend[23:0];
assign carry_g[23:0] = summand[23:0] & addend[23:0];
assign carry_d[23:0] = ~(summand[23:0] | addend[23:0]);




assign lza_precod[0] = 
     carry_p[1] && (carry_g[0] && sub_vld || carry_d[0])
 || !carry_p[1] && (carry_d[0] && sub_vld || carry_g[0]);

assign lza_precod[23] = 
     sub_vld && (carry_g[23] && !carry_d[22] || carry_d[23] && !carry_g[22])
 || !sub_vld && (carry_d[23] && !carry_d[22] || !carry_d[23]);

assign lza_precod[22:1] = 
    carry_p[23:2] & (carry_g[22:1] & ~carry_d[21:0] | carry_d[22:1] & ~carry_g[21:0])
 | ~carry_p[23:2] & (carry_g[22:1] & ~carry_g[21:0] | carry_d[22:1] & ~carry_d[21:0]);





always @( lza_precod[23:0])
begin
casez(lza_precod[23:0])
  24'b1???????????????????????:lza_result[4:0] = 5'd0;
  24'b01??????????????????????:lza_result[4:0] = 5'd1;
  24'b001?????????????????????:lza_result[4:0] = 5'd2;
  24'b0001????????????????????:lza_result[4:0] = 5'd3;
  24'b00001???????????????????:lza_result[4:0] = 5'd4;
  24'b000001??????????????????:lza_result[4:0] = 5'd5;
  24'b0000001?????????????????:lza_result[4:0] = 5'd6;
  24'b00000001????????????????:lza_result[4:0] = 5'd7;
  24'b000000001???????????????:lza_result[4:0] = 5'd8;
  24'b0000000001??????????????:lza_result[4:0] = 5'd9;
  24'b00000000001?????????????:lza_result[4:0] = 5'd10;
  24'b000000000001????????????:lza_result[4:0] = 5'd11;
  24'b0000000000001???????????:lza_result[4:0] = 5'd12;
  24'b00000000000001??????????:lza_result[4:0] = 5'd13;
  24'b000000000000001?????????:lza_result[4:0] = 5'd14;
  24'b0000000000000001????????:lza_result[4:0] = 5'd15;
  24'b00000000000000001???????:lza_result[4:0] = 5'd16;
  24'b000000000000000001??????:lza_result[4:0] = 5'd17;
  24'b0000000000000000001?????:lza_result[4:0] = 5'd18;
  24'b00000000000000000001????:lza_result[4:0] = 5'd19;
  24'b000000000000000000001???:lza_result[4:0] = 5'd20;
  24'b0000000000000000000001??:lza_result[4:0] = 5'd21;
  24'b00000000000000000000001?:lza_result[4:0] = 5'd22;
  24'b000000000000000000000001:lza_result[4:0] = 5'd23;
  default                     :lza_result[4:0] = 5'd24;
endcase

end

assign lza_result_zero = ~|lza_precod[23:0];


endmodule
module ct_vfmau_lza_simd_half(
  addend,
  lza_result,
  lza_result_zero,
  sub_vld,
  summand
);



input   [23:0]  addend;         
input           sub_vld;        
input   [23:0]  summand;        
output  [4 :0]  lza_result;     
output          lza_result_zero; 


reg     [4 :0]  lza_result;     


wire    [23:0]  addend;         
wire    [23:0]  carry_d;        
wire    [23:0]  carry_g;        
wire    [23:0]  carry_p;        
wire    [23:0]  lza_precod;     
wire            lza_result_zero; 
wire            sub_vld;        
wire    [23:0]  summand;        











assign carry_p[23:0] = summand[23:0] ^ addend[23:0];
assign carry_g[23:0] = summand[23:0] & addend[23:0];
assign carry_d[23:0] = ~(summand[23:0] | addend[23:0]);




assign lza_precod[0] = 
     carry_p[1] && (carry_g[0] && sub_vld || carry_d[0])
 || !carry_p[1] && (carry_d[0] && sub_vld || carry_g[0]);

assign lza_precod[23] = 
     sub_vld && (carry_g[23] && !carry_d[22] || carry_d[23] && !carry_g[22])
 || !sub_vld && (carry_d[23] && !carry_d[22] || !carry_d[23]);

assign lza_precod[22:1] = 
    carry_p[23:2] & (carry_g[22:1] & ~carry_d[21:0] | carry_d[22:1] & ~carry_g[21:0])
 | ~carry_p[23:2] & (carry_g[22:1] & ~carry_g[21:0] | carry_d[22:1] & ~carry_d[21:0]);





always @( lza_precod[23:0])
begin
casez(lza_precod[23:0])
  24'b1???????????????????????:lza_result[4:0] = 5'd0;
  24'b01??????????????????????:lza_result[4:0] = 5'd1;
  24'b001?????????????????????:lza_result[4:0] = 5'd2;
  24'b0001????????????????????:lza_result[4:0] = 5'd3;
  24'b00001???????????????????:lza_result[4:0] = 5'd4;
  24'b000001??????????????????:lza_result[4:0] = 5'd5;
  24'b0000001?????????????????:lza_result[4:0] = 5'd6;
  24'b00000001????????????????:lza_result[4:0] = 5'd7;
  24'b000000001???????????????:lza_result[4:0] = 5'd8;
  24'b0000000001??????????????:lza_result[4:0] = 5'd9;
  24'b00000000001?????????????:lza_result[4:0] = 5'd10;
  24'b000000000001????????????:lza_result[4:0] = 5'd11;
  24'b0000000000001???????????:lza_result[4:0] = 5'd12;
  24'b00000000000001??????????:lza_result[4:0] = 5'd13;
  24'b000000000000001?????????:lza_result[4:0] = 5'd14;
  24'b0000000000000001????????:lza_result[4:0] = 5'd15;
  24'b00000000000000001???????:lza_result[4:0] = 5'd16;
  24'b000000000000000001??????:lza_result[4:0] = 5'd17;
  24'b0000000000000000001?????:lza_result[4:0] = 5'd18;
  24'b00000000000000000001????:lza_result[4:0] = 5'd19;
  24'b000000000000000000001???:lza_result[4:0] = 5'd20;
  24'b0000000000000000000001??:lza_result[4:0] = 5'd21;
  24'b00000000000000000000001?:lza_result[4:0] = 5'd22;
  24'b000000000000000000000001:lza_result[4:0] = 5'd23;
  default                     :lza_result[4:0] = 5'd24;
endcase

end

assign lza_result_zero = ~|lza_precod[23:0];


endmodule