data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v
1: b'%Warning-REDEFMACRO: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:198: Redefining existing define: \'M_W\', with different value: 8\n                     ... Use "/* verilator lint_off REDEFMACRO */" and lint_on around source to disable this message.\n%Warning-REDEFMACRO: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:198: Previous definition is here, with value: 4\n%Warning-PINMISSING: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:379: Cell has missing pin: \'RST\'\nmb24 b_mult(\n     ^~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:499: Cannot find file containing module: \'HALF_ADDER\'\nHALF_ADDER ha000(.a(cv[0]), .b(fpp0[0]) , .sum(has000), .cout(hac000));\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/HALF_ADDER\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/HALF_ADDER.v\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/HALF_ADDER.sv\n             HALF_ADDER\n             HALF_ADDER.v\n             HALF_ADDER.sv\n             obj_dir/HALF_ADDER\n             obj_dir/HALF_ADDER.v\n             obj_dir/HALF_ADDER.sv\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:500: Cannot find file containing module: \'HALF_ADDER\'\nHALF_ADDER ha001(.a(cv[1]), .b(fpp0[1]) , .sum(has001), .cout(hac001));\n^~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:501: Cannot find file containing module: \'HALF_ADDER\'\nHALF_ADDER ha002(.a(cv[2]), .b(fpp0[2]) , .sum(has002), .cout(hac002));\n^~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:505: Cannot find file containing module: \'HALF_ADDER\'\nHALF_ADDER aha002(.a(cv[7]), .b(fpp1[4]) , .sum(ahas002), .cout(ahac002));\n^~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:509: Cannot find file containing module: \'FULL_ADDER\'\n                FULL_ADDER fa000(.a(cv[i + 3]), .b(fpp0[i + 3]), .cin(fpp1[i]), .sum(fas0[i]), .cout(fac0[i]));\n                ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:209: Operator ADD expects 6 bits on the LHS, but LHS\'s VARREF \'my\' generates 4 bits.\n                                                                                  : ... In instance sa_2D.pre_process[1].prep00\nassign SUM=my+(my<<1);\n             ^\n%Warning-WIDTH: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:209: Operator SHIFTL expects 6 bits on the LHS, but LHS\'s VARREF \'my\' generates 4 bits.\n                                                                                  : ... In instance sa_2D.pre_process[1].prep00\nassign SUM=my+(my<<1);\n                 ^~\n%Warning-LITENDIAN: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:43: Little bit endian vector: MSB < LSB of bit range: 0:1\nreg [0:HPE-1]D_SHIFTEN;\n    ^\n%Error: Exiting due to 5 error(s), 6 warning(s)\n'
module mb24 #(parameter WIDTH = 4)(

input [WIDTH-1:0] my,
input CLK,
input RST,


input  [1:0] s, d, t, q, n,
input  [WIDTH+1:0] tmy,


output [(WIDTH*2)-1:0] product);

parameter group_cnt=(WIDTH>>2)+1;

wire [WIDTH+1:0] epp2d[0:group_cnt - 1];

wire [WIDTH+2:0] fpp0;
wire [WIDTH+2:0] fpp1;

genvar i, j;
generate
    for (j = 0; j < group_cnt; j = j + 1) begin: b_selector
          booth_sel bs(.y2(my[0]),.y1(1'b0),.y0(1'b0), .ty(tmy[0]), .single(s[j]), .double(d[j]), .triple(t[j]), .quad(q[j]), .neg(n[j]), .p(epp2d[j][0]));
                  booth_sel bs0(.y2(my[1]), .y1(my[0]),.y0(1'b0), .ty(tmy[1]), .single(s[j]), .double(d[j]), .triple(t[j]), .quad(q[j]), .neg(n[j]), .p(epp2d[j][1]));
                  booth_sel bs1(.y2(my[2]),.y1(my[1]),.y0(my[0]), .ty(tmy[2]), .single(s[j]), .double(d[j]), .triple(t[j]), .quad(q[j]), .neg(n[j]), .p(epp2d[j][2]));
                  booth_sel bs2(.y2(my[3]),.y1(my[2]),.y0(my[1]), .ty(tmy[3]), .single(s[j]), .double(d[j]), .triple(t[j]), .quad(q[j]), .neg(n[j]), .p(epp2d[j][3]));
          booth_sel bs3(.y2(1'b0),.y1(my[3]),.y0(my[2]), .ty(tmy[4]), .single(s[j]), .double(d[j]), .triple(t[j]), .quad(q[j]), .neg(n[j]), .p(epp2d[j][4]));
          booth_sel bs4(.y2(1'b0),.y1(1'b0),.y0(my[3]), .ty(tmy[5]), .single(s[j]), .double(d[j]), .triple(t[j]), .quad(q[j]), .neg(n[j]), .p(epp2d[j][5]));

                end
endgenerate


assign fpp0 = {~n[0] , epp2d[0]};
assign fpp1 = {~n[1] , epp2d[1]};

wire [7:0]cv= {4'b1100, n[1], 2'b00, n[0]};


wire has000;
wire hac000;
wire has001;
wire hac001;
wire has002;
wire hac002;

wire ahas000;
wire ahac000;
wire ahas001;
wire ahac001;
wire ahas002;
wire ahac002;


wire [3:0] fas0;
wire [3:0] fac0;

wire [7:0] st00;
wire [6:0] st01;




HALF_ADDER ha000(.a(cv[0]), .b(fpp0[0]) , .sum(has000), .cout(hac000));
HALF_ADDER ha001(.a(cv[1]), .b(fpp0[1]) , .sum(has001), .cout(hac001));
HALF_ADDER ha002(.a(cv[2]), .b(fpp0[2]) , .sum(has002), .cout(hac002));



HALF_ADDER aha002(.a(cv[7]), .b(fpp1[4]) , .sum(ahas002), .cout(ahac002));

generate
        for (i = 0; i < 4; i = i + 1) begin:    for_s0
                FULL_ADDER fa000(.a(cv[i + 3]), .b(fpp0[i + 3]), .cin(fpp1[i]), .sum(fas0[i]), .cout(fac0[i]));
        end
endgenerate

assign st00 = {ahas002, fas0, has002, has001, has000};
assign st01 = {fac0, hac002, hac001, hac000};



assign product = st00 + {st01, 1'b0};

endmodule
module mb24 #(parameter WIDTH = 4)(

input [WIDTH-1:0] my,
input CLK,
input RST,


input  [1:0] s, d, t, q, n,
input  [WIDTH+1:0] tmy,


output [(WIDTH*2)-1:0] product);


parameter group_cnt=(WIDTH>>2)+1;

wire [WIDTH+1:0] epp2d[0:group_cnt - 1];

wire [WIDTH+2:0] fpp0;
wire [WIDTH+2:0] fpp1;

genvar i, j;
generate
    for (j = 0; j < group_cnt; j = j + 1) begin: b_selector
          booth_sel bs(.y2(my[0]),.y1(1'b0),.y0(1'b0), .ty(tmy[0]), .single(s[j]), .double(d[j]), .triple(t[j]), .quad(q[j]), .neg(n[j]), .p(epp2d[j][0]));
                  booth_sel bs0(.y2(my[1]), .y1(my[0]),.y0(1'b0), .ty(tmy[1]), .single(s[j]), .double(d[j]), .triple(t[j]), .quad(q[j]), .neg(n[j]), .p(epp2d[j][1]));
                  booth_sel bs1(.y2(my[2]),.y1(my[1]),.y0(my[0]), .ty(tmy[2]), .single(s[j]), .double(d[j]), .triple(t[j]), .quad(q[j]), .neg(n[j]), .p(epp2d[j][2]));
                  booth_sel bs2(.y2(my[3]),.y1(my[2]),.y0(my[1]), .ty(tmy[3]), .single(s[j]), .double(d[j]), .triple(t[j]), .quad(q[j]), .neg(n[j]), .p(epp2d[j][3]));
          booth_sel bs3(.y2(1'b0),.y1(my[3]),.y0(my[2]), .ty(tmy[4]), .single(s[j]), .double(d[j]), .triple(t[j]), .quad(q[j]), .neg(n[j]), .p(epp2d[j][4]));
          booth_sel bs4(.y2(1'b0),.y1(1'b0),.y0(my[3]), .ty(tmy[5]), .single(s[j]), .double(d[j]), .triple(t[j]), .quad(q[j]), .neg(n[j]), .p(epp2d[j][5]));

                end
endgenerate


assign fpp0 = {~n[0] , epp2d[0]};
assign fpp1 = {~n[1] , epp2d[1]};

wire [7:0]cv= {4'b1100, n[1], 2'b00, n[0]};


wire has000;
wire hac000;
wire has001;
wire hac001;
wire has002;
wire hac002;

wire ahas000;
wire ahac000;
wire ahas001;
wire ahac001;
wire ahas002;
wire ahac002;


wire [3:0] fas0;
wire [3:0] fac0;

wire [7:0] st00;
wire [6:0] st01;




HALF_ADDER ha000(.a(cv[0]), .b(fpp0[0]) , .sum(has000), .cout(hac000));
HALF_ADDER ha001(.a(cv[1]), .b(fpp0[1]) , .sum(has001), .cout(hac001));
HALF_ADDER ha002(.a(cv[2]), .b(fpp0[2]) , .sum(has002), .cout(hac002));



HALF_ADDER aha002(.a(cv[7]), .b(fpp1[4]) , .sum(ahas002), .cout(ahac002));

generate
        for (i = 0; i < 4; i = i + 1) begin:    for_s0
                FULL_ADDER fa000(.a(cv[i + 3]), .b(fpp0[i + 3]), .cin(fpp1[i]), .sum(fas0[i]), .cout(fac0[i]));
        end
endgenerate

assign st00 = {ahas002, fas0, has002, has001, has000};
assign st01 = {fac0, hac002, hac001, hac000};



assign product = st00 + {st01, 1'b0};

endmodule