data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/ID.v
1: b'%Warning-WIDTH: data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/ID.v:41: Operator ASSIGN expects 21 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 20 bits.\n                                                                                           : ... In instance ID.imm_gen1\n            out[31:11] = {20{in[31]}};   \n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/ID.v:49: Operator ASSIGN expects 21 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 20 bits.\n                                                                                           : ... In instance ID.imm_gen1\n            out[31:11] = {20{in[31]}};\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/ID.v:57: Operator ASSIGN expects 21 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 20 bits.\n                                                                                           : ... In instance ID.imm_gen1\n            out[31:11] = {20{in[31]}};   \n                       ^\n%Warning-WIDTH: data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/ID.v:65: Operator ASSIGN expects 20 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 19 bits.\n                                                                                           : ... In instance ID.imm_gen1\n            out[31:12] = {19{in[31]}};   \n                       ^\n%Error: Exiting due to 4 warning(s)\n'
module imm_gen(input [31:0] in,
               output reg [31:0] out);
    integer i;
    always@(*) begin

        if (in[6:0] == 7'b0000011) begin

            out[31:11] = {20{in[31]}};   
            out[10:5] = in[30:25];
            out[4:1] = in[24:21];
            out[0] = in[20];
        end

        else if(in[6:0] == 7'b0010011) begin

            out[31:11] = {20{in[31]}};
            out[10:5] = in[30:25];
            out[4:1] = in[24:21];
            out[0] = in[20];       
        end

        else if (in[6:0] == 7'b0100011) begin

            out[31:11] = {20{in[31]}};   
            out[10:5] = in[30:25];
            out[4:1] = in[11:8];
            out[0] = in[7];
        end

        else if(in[6:0] == 7'b1100011) begin

            out[31:12] = {19{in[31]}};   
            out[10:5] = in[30:25];
            out[4:1] = in[11:8];
            out[11] = in[7];
            out[0] = 0;
        end

        else if(in[6:0] == 7'b0110011)
            out = 0;
        else
            out = in;
     end
endmodule
module imm_gen(input [31:0] in,
               output reg [31:0] out);

    integer i;
    always@(*) begin

        if (in[6:0] == 7'b0000011) begin

            out[31:11] = {20{in[31]}};   
            out[10:5] = in[30:25];
            out[4:1] = in[24:21];
            out[0] = in[20];
        end

        else if(in[6:0] == 7'b0010011) begin

            out[31:11] = {20{in[31]}};
            out[10:5] = in[30:25];
            out[4:1] = in[24:21];
            out[0] = in[20];       
        end

        else if (in[6:0] == 7'b0100011) begin

            out[31:11] = {20{in[31]}};   
            out[10:5] = in[30:25];
            out[4:1] = in[11:8];
            out[0] = in[7];
        end

        else if(in[6:0] == 7'b1100011) begin

            out[31:12] = {19{in[31]}};   
            out[10:5] = in[30:25];
            out[4:1] = in[11:8];
            out[11] = in[7];
            out[0] = 0;
        end

        else if(in[6:0] == 7'b0110011)
            out = 0;
        else
            out = in;
     end
endmodule