data/full_repos/permissive/514758517/logical_or.v
1: b'%Warning-WIDTH: data/full_repos/permissive/514758517/logical_or.v:8: Logical Operator LOGOR expects 1 bit on the LHS, but LHS\'s VARREF \'in1\' generates 5 bits.\n                                                                   : ... In instance logical_or\n  assign out_or = in1 || in2;\n                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/514758517/logical_or.v:8: Logical Operator LOGOR expects 1 bit on the RHS, but RHS\'s VARREF \'in2\' generates 5 bits.\n                                                                   : ... In instance logical_or\n  assign out_or = in1 || in2;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/514758517/logical_or.v:8: Operator ASSIGNW expects 9 bits on the Assign RHS, but Assign RHS\'s LOGOR generates 1 bits.\n                                                                   : ... In instance logical_or\n  assign out_or = in1 || in2;\n                ^\n%Error: Exiting due to 3 warning(s)\n'
module logical_or(in1 , in2 , out_or);
  
  input signed [4:0]in1;
  input signed [4:0]in2;
  output signed [8:0]out_or;
  
  assign out_or = in1 || in2;
  
endmodule
module logical_or(in1 , in2 , out_or);

  
  input signed [4:0]in1;
  input signed [4:0]in2;
  output signed [8:0]out_or;
  
  assign out_or = in1 || in2;
  
endmodule