data/full_repos/permissive/529457593/Sprint10/adderULA.v
data/verilator_xmls/be527eab-5f97-4ac2-a9fc-4979d4382d33.xml
module adderULA (input [17:0] sw, output reg [17:0] ledr);

always @(*) begin 
	if (sw[17:16] == 2'b00)
		ledr[3:0] = sw[3:0] + sw[7:4];
	else if (sw[17:16] == 2'b01)
		ledr[3:0] = sw[3:0] - sw[7:4];
	else if (sw[17:16] == 2'b10)
		ledr[3:0] = sw[3:0] & sw[7:4];
	else if (sw[17:16] == 2'b11)
		ledr[3:0] = sw[3:0] | sw[7:4];
end

endmodule
module adderULA (input [17:0] sw, output reg [17:0] ledr);


always @(*) begin 
	if (sw[17:16] == 2'b00)
		ledr[3:0] = sw[3:0] + sw[7:4];
	else if (sw[17:16] == 2'b01)
		ledr[3:0] = sw[3:0] - sw[7:4];
	else if (sw[17:16] == 2'b10)
		ledr[3:0] = sw[3:0] & sw[7:4];
	else if (sw[17:16] == 2'b11)
		ledr[3:0] = sw[3:0] | sw[7:4];
end

endmodule