data/full_repos/permissive/514313792/prj_quartus/rtl/nios2_camera_sdram_lcd_top.v
1: b"%Error: data/full_repos/permissive/514313792/prj_quartus/rtl/nios2_camera_sdram_lcd_top.v:49: Cannot find file containing module: 'nios2_camera_sdram_lcd'\n nios2_camera_sdram_lcd sopc(\n ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514313792/prj_quartus/rtl,data/full_repos/permissive/514313792/nios2_camera_sdram_lcd\n             data/full_repos/permissive/514313792/prj_quartus/rtl,data/full_repos/permissive/514313792/nios2_camera_sdram_lcd.v\n             data/full_repos/permissive/514313792/prj_quartus/rtl,data/full_repos/permissive/514313792/nios2_camera_sdram_lcd.sv\n             nios2_camera_sdram_lcd\n             nios2_camera_sdram_lcd.v\n             nios2_camera_sdram_lcd.sv\n             obj_dir/nios2_camera_sdram_lcd\n             obj_dir/nios2_camera_sdram_lcd.v\n             obj_dir/nios2_camera_sdram_lcd.sv\n%Error: Exiting due to 1 error(s)\n"
module nios2_camera_sdram_lcd_top
(
	input clk,
	input rst_n,

	output                      sdram_clk,
	output                      sdram_cke,
	output                      sdram_cs_n,
	output                      sdram_we_n,
	output                      sdram_cas_n,
	output                      sdram_ras_n,
	output[1:0]                 sdram_dqm,
	output[1:0]                 sdram_ba,
	output[12:0]                sdram_addr,
	inout[15:0]                 sdram_dq,
	output lcd_dclk,
	output lcd_de,
	output lcd_hs,
	output lcd_vs,
	output [7:0] lcd_r,
	output [7:0] lcd_g,
	output [7:0] lcd_b,
	inout                       cmos_scl,
	inout                       cmos_sda,
	input                       cmos_vsync,
	input                       cmos_href,
	input                       cmos_pclk,
	output                      cmos_xclk,
	input   [7:0]               cmos_db,
	output                      cmos_rst_n,
	output                      cmos_pwdn,
	output [3:0] led_pin
);

	wire vi_pclk;
	wire vi_out_href, vi_out_vsync;
	wire [7:0] vi_out_raw;
	wire isp_out_href, isp_out_vsync;
	wire [7:0] isp_out_y, isp_out_u, isp_out_v;
	wire vip_out_pclk;
	wire vip_out_href;
	wire vip_out_vsync;
	wire [7:0] vip_out_r, vip_out_g, vip_out_b;
	
	assign led_pin = {vip_out_vsync, isp_out_vsync, vi_out_vsync, cmos_rst_n};

	wire lcd_xclk;
	nios2_camera_sdram_lcd sopc(
		.sdram_addr(sdram_addr),
		.sdram_ba(sdram_ba),
		.sdram_cas_n(sdram_cas_n),
		.sdram_cke(sdram_cke),
		.sdram_cs_n(sdram_cs_n),
		.sdram_dq(sdram_dq),
		.sdram_dqm(sdram_dqm),
		.sdram_ras_n(sdram_ras_n),
		.sdram_we_n(sdram_we_n),
		.pio_export({4'hz, cmos_rst_n, cmos_pwdn, cmos_sda, cmos_scl}),
		.clk_clk(clk),
		.sdram_clk_clk(sdram_clk),
		  
        .lcd_pclk                     (lcd_xclk),
        .lcd_lcd_dclk                 (lcd_dclk),
        .lcd_lcd_de                   (lcd_de),
        .lcd_lcd_hs                   (lcd_hs),
        .lcd_lcd_vs                   (lcd_vs),
        .lcd_lcd_r                    (lcd_r),
        .lcd_lcd_g                    (lcd_g),
        .lcd_lcd_b                    (lcd_b),
        .lcd_xclk_clk                 (lcd_xclk),
	
        .cmos_xclk_clk (cmos_xclk),

        .dvp_vi_cmos_xclk  (cmos_xclk),
        .dvp_vi_cmos_pclk  (cmos_pclk),
        .dvp_vi_cmos_href  (cmos_href),
        .dvp_vi_cmos_vsync (cmos_vsync),
        .dvp_vi_cmos_db    (cmos_db),
        .dvp_vi_out_pclk   (vi_pclk),
        .dvp_vi_out_href   (vi_out_href),
        .dvp_vi_out_vsync  (vi_out_vsync),
        .dvp_vi_out_raw    (vi_out_raw),
		  
        .isp_pclk      (vi_pclk),
        .isp_rst_n     (cmos_rst_n),
        .isp_in_href   (vi_out_href),
        .isp_in_vsync  (vi_out_vsync),
        .isp_in_raw    (vi_out_raw),
        .isp_out_href  (isp_out_href),
        .isp_out_vsync (isp_out_vsync),
        .isp_out_y     (isp_out_y),
        .isp_out_u     (isp_out_u),
        .isp_out_v     (isp_out_v),

        .vip_pclk      (vi_pclk),
        .vip_rst_n     (cmos_rst_n),
        .vip_in_href   (isp_out_href),
        .vip_in_vsync  (isp_out_vsync),
        .vip_in_y      (isp_out_y),
        .vip_in_u      (isp_out_u),
        .vip_in_v      (isp_out_v),
        .vip_out_pclk  (vip_out_pclk),
        .vip_out_href  (vip_out_href),
        .vip_out_vsync (vip_out_vsync),
        .vip_out_r     (vip_out_r),
        .vip_out_g     (vip_out_g),
        .vip_out_b     (vip_out_b),
 
        .dvp_wch_pclk      (vip_out_pclk),
        .dvp_wch_href      (vip_out_href),
        .dvp_wch_vsync     (vip_out_vsync),
        .dvp_wch_raw       ({vip_out_r[7:3], vip_out_g[7:2], vip_out_b[7:3]})
 
		 
		 );

endmodule
module nios2_camera_sdram_lcd_top
(
	input clk,
	input rst_n,

	output                      sdram_clk,
	output                      sdram_cke,
	output                      sdram_cs_n,
	output                      sdram_we_n,
	output                      sdram_cas_n,
	output                      sdram_ras_n,
	output[1:0]                 sdram_dqm,
	output[1:0]                 sdram_ba,
	output[12:0]                sdram_addr,
	inout[15:0]                 sdram_dq,
	output lcd_dclk,
	output lcd_de,
	output lcd_hs,
	output lcd_vs,
	output [7:0] lcd_r,
	output [7:0] lcd_g,
	output [7:0] lcd_b,
	inout                       cmos_scl,
	inout                       cmos_sda,
	input                       cmos_vsync,
	input                       cmos_href,
	input                       cmos_pclk,
	output                      cmos_xclk,
	input   [7:0]               cmos_db,
	output                      cmos_rst_n,
	output                      cmos_pwdn,
	output [3:0] led_pin
);


	wire vi_pclk;
	wire vi_out_href, vi_out_vsync;
	wire [7:0] vi_out_raw;
	wire isp_out_href, isp_out_vsync;
	wire [7:0] isp_out_y, isp_out_u, isp_out_v;
	wire vip_out_pclk;
	wire vip_out_href;
	wire vip_out_vsync;
	wire [7:0] vip_out_r, vip_out_g, vip_out_b;
	
	assign led_pin = {vip_out_vsync, isp_out_vsync, vi_out_vsync, cmos_rst_n};

	wire lcd_xclk;
	nios2_camera_sdram_lcd sopc(
		.sdram_addr(sdram_addr),
		.sdram_ba(sdram_ba),
		.sdram_cas_n(sdram_cas_n),
		.sdram_cke(sdram_cke),
		.sdram_cs_n(sdram_cs_n),
		.sdram_dq(sdram_dq),
		.sdram_dqm(sdram_dqm),
		.sdram_ras_n(sdram_ras_n),
		.sdram_we_n(sdram_we_n),
		.pio_export({4'hz, cmos_rst_n, cmos_pwdn, cmos_sda, cmos_scl}),
		.clk_clk(clk),
		.sdram_clk_clk(sdram_clk),
		  
        .lcd_pclk                     (lcd_xclk),
        .lcd_lcd_dclk                 (lcd_dclk),
        .lcd_lcd_de                   (lcd_de),
        .lcd_lcd_hs                   (lcd_hs),
        .lcd_lcd_vs                   (lcd_vs),
        .lcd_lcd_r                    (lcd_r),
        .lcd_lcd_g                    (lcd_g),
        .lcd_lcd_b                    (lcd_b),
        .lcd_xclk_clk                 (lcd_xclk),
	
        .cmos_xclk_clk (cmos_xclk),

        .dvp_vi_cmos_xclk  (cmos_xclk),
        .dvp_vi_cmos_pclk  (cmos_pclk),
        .dvp_vi_cmos_href  (cmos_href),
        .dvp_vi_cmos_vsync (cmos_vsync),
        .dvp_vi_cmos_db    (cmos_db),
        .dvp_vi_out_pclk   (vi_pclk),
        .dvp_vi_out_href   (vi_out_href),
        .dvp_vi_out_vsync  (vi_out_vsync),
        .dvp_vi_out_raw    (vi_out_raw),
		  
        .isp_pclk      (vi_pclk),
        .isp_rst_n     (cmos_rst_n),
        .isp_in_href   (vi_out_href),
        .isp_in_vsync  (vi_out_vsync),
        .isp_in_raw    (vi_out_raw),
        .isp_out_href  (isp_out_href),
        .isp_out_vsync (isp_out_vsync),
        .isp_out_y     (isp_out_y),
        .isp_out_u     (isp_out_u),
        .isp_out_v     (isp_out_v),

        .vip_pclk      (vi_pclk),
        .vip_rst_n     (cmos_rst_n),
        .vip_in_href   (isp_out_href),
        .vip_in_vsync  (isp_out_vsync),
        .vip_in_y      (isp_out_y),
        .vip_in_u      (isp_out_u),
        .vip_in_v      (isp_out_v),
        .vip_out_pclk  (vip_out_pclk),
        .vip_out_href  (vip_out_href),
        .vip_out_vsync (vip_out_vsync),
        .vip_out_r     (vip_out_r),
        .vip_out_g     (vip_out_g),
        .vip_out_b     (vip_out_b),
 
        .dvp_wch_pclk      (vip_out_pclk),
        .dvp_wch_href      (vip_out_href),
        .dvp_wch_vsync     (vip_out_vsync),
        .dvp_wch_raw       ({vip_out_r[7:3], vip_out_g[7:2], vip_out_b[7:3]})
 
		 
		 );

endmodule