data/full_repos/permissive/425573648/fpga/pid.v
1: b'%Warning-WIDTH: data/full_repos/permissive/425573648/fpga/pid.v:157: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'k_p\' generates 12 bits.\n                                                                   : ... In instance pid\n   k_1 <= k_p + k_i + k_d;\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/425573648/fpga/pid.v:157: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'k_i\' generates 12 bits.\n                                                                   : ... In instance pid\n   k_1 <= k_p + k_i + k_d;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/425573648/fpga/pid.v:157: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'k_d\' generates 12 bits.\n                                                                   : ... In instance pid\n   k_1 <= k_p + k_i + k_d;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/425573648/fpga/pid.v:158: Operator NEGATE expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'k_p\' generates 12 bits.\n                                                                   : ... In instance pid\n   k_2 <= -k_p - (2 * k_d);\n          ^\n%Warning-WIDTH: data/full_repos/permissive/425573648/fpga/pid.v:159: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'k_d\' generates 12 bits.\n                                                                   : ... In instance pid\n   k_3 <= k_d; \n       ^~\n%Error: data/full_repos/permissive/425573648/fpga/pid.v:338: Cannot find file containing module: \'decimal_val\'\ndecimal_val kp_ascii(k_p, p100, p10, p1);\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/425573648/fpga,data/full_repos/permissive/425573648/decimal_val\n             data/full_repos/permissive/425573648/fpga,data/full_repos/permissive/425573648/decimal_val.v\n             data/full_repos/permissive/425573648/fpga,data/full_repos/permissive/425573648/decimal_val.sv\n             decimal_val\n             decimal_val.v\n             decimal_val.sv\n             obj_dir/decimal_val\n             obj_dir/decimal_val.v\n             obj_dir/decimal_val.sv\n%Error: data/full_repos/permissive/425573648/fpga/pid.v:339: Cannot find file containing module: \'decimal_val\'\ndecimal_val ki_ascii(k_i, i100, i10, i1);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/425573648/fpga/pid.v:340: Cannot find file containing module: \'decimal_val\'\ndecimal_val kd_ascii(k_d, d100, d10, d1);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/425573648/fpga/pid.v:343: Cannot find file containing module: \'velocity_decimal_val\'\nvelocity_decimal_val comm_ascii(command_speed, c1000, c100, c10, c1);\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/425573648/fpga/pid.v:344: Cannot find file containing module: \'velocity_decimal_val\'\nvelocity_decimal_val sens_ascii(feedback_speed, s1000, s100, s10, s1);\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/425573648/fpga/pid.v:385: Cannot find file containing module: \'motor_rpm_count\'\nmotor_rpm_count count_pulse(clk, motor_rot_pulse, motor_rpm_return);\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/425573648/fpga/pid.v:395: Cannot find file containing module: \'output_pwm_gen\'\noutput_pwm_gen out_pulse(clk, command_speed, velocity_command_pulse);\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/425573648/fpga/pid.v:398: Cannot find file containing module: \'seg7_act_val\'\nseg7_act_val kval_disp(k_p, k_i, k_d, user_control_speed, active_ui_control, seg7_k, seg7_eq, seg7_thousands, seg7_hundreds, seg7_tens, seg7_ones);\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/425573648/fpga/pid.v:399: Cannot find file containing module: \'lcd\'\nlcd lcd(lcd_clock_pulse, lcd_reset_pulse, kval_to_lcd, velocity_to_lcd, disp_rs, disp_rw, disp_en, disp_data);\n^~~\n%Error: Exiting due to 9 error(s), 5 warning(s)\n'
module pid (
	input clk,
	input res,
	input c_active,
	input kp_active,
	input ki_active,
	input kd_active,
	input inc_up,
	input inc_dn,
	input motor_rot_pulse,
	output disp_rs,
	output disp_rw,
	output disp_en,
	output display_on,
	output [7:0]disp_data,
	output [6:0]seg7_k,
	output [6:0]seg7_eq,
	output [6:0]seg7_thousands,
	output [6:0]seg7_hundreds,
	output [6:0]seg7_tens,
	output [6:0]seg7_ones,
	output velocity_command_pulse
);





reg signed [15:0]command_speed;
reg signed [15:0]prev_command_speed;
reg signed [15:0]current_error;
reg signed [15:0]last_error;
reg signed [15:0]prior_error;
reg signed [15:0]user_control_speed;
reg signed [15:0]feedback_speed;
wire [15:0]motor_rpm_return;




reg [71:0]kval_to_lcd;



reg [63:0]velocity_to_lcd;


reg signed [11:0]k_p;
reg signed [11:0]k_i;
reg signed [11:0]k_d;


wire [7:0]p100;
wire [7:0]p10;
wire [7:0]p1;
wire [7:0]i100;
wire [7:0]i10;
wire [7:0]i1;
wire [7:0]d100;
wire [7:0]d10;
wire [7:0]d1;


wire [7:0]c1000;
wire [7:0]c100;
wire [7:0]c10;
wire [7:0]c1;
wire [7:0]s1000;
wire [7:0]s100;
wire [7:0]s10;
wire [7:0]s1;



reg signed [15:0]k_1;
reg signed [15:0]k_2;
reg signed [15:0]k_3;


reg [3:0]active_ui_control;


reg [23:0]ui_clock_counter;


reg [15:0]lcd_clock_counter;


reg [31:0]lcd_reset_counter;


reg ui_clock_pulse;


reg lcd_clock_pulse;


reg lcd_reset_pulse;


initial
	begin
	 	k_p = 12'd0;
	 	k_i = 12'd0;
	 	k_d = 12'd0;
		user_control_speed = 16'd1000;
	 end 


 assign display_on = 1'b1;


 always @(posedge clk)
 	begin
 		k_1 <= k_p + k_i + k_d;
 		k_2 <= -k_p - (2 * k_d);
 		k_3 <= k_d; 
 	end


always @(posedge clk)
	begin
		if (res == 1'b0)
			begin

				prev_command_speed <= 16'd0;
				current_error <= 16'd0;
				last_error <= 16'd0;
				prior_error <= 16'd0;
			end
		else
			begin

				prev_command_speed <= command_speed;
				prior_error <= last_error;
				last_error <= current_error;
			end

		current_error <= command_speed - feedback_speed;
		command_speed <= prev_command_speed + (((k_1 * current_error) - (k_2 * last_error) + (k_3 * prior_error)) / 10000);

	end
	




always @(posedge ui_clock_pulse)
	begin

		active_ui_control<= {c_active, kp_active, ki_active, kd_active};


		case (active_ui_control)
		

		4'b1000:
			begin
				if (~inc_up && inc_dn && user_control_speed < 16'd9999)
					begin

						user_control_speed <= user_control_speed + 1'b1;
					end
				else if (~inc_up && inc_dn && user_control_speed == 16'd9999)
					begin

						user_control_speed <= 16'd0;
					end
				else if (inc_up && ~inc_dn && user_control_speed > 16'd0)
					begin

						user_control_speed <= user_control_speed - 1'b1;
					end
				else if (inc_up && ~inc_dn && user_control_speed == 16'd0)
					begin

						user_control_speed <= 16'd9999;
					end
				else
					begin

						user_control_speed <= user_control_speed;
					end
			end


		4'b0100:
			begin
				if (~inc_up && inc_dn && k_p < 12'd999)
					begin

						k_p <= k_p + 1'b1;
					end
				else if (~inc_up && inc_dn && k_p == 12'd999)
					begin

						k_p <= 12'd0;
					end
				else if (inc_up && ~inc_dn && k_p > 12'd0)
					begin

						k_p <= k_p - 1'b1;
					end
				else if (inc_up && ~inc_dn && k_p == 12'd0)
					begin

						k_p <= 12'd999;
					end
				else
					begin

						k_p <= k_p;
					end
			end


		4'b0010:
			begin
				if (~inc_up && inc_dn && k_i < 12'd999)
					begin

						k_i <= k_i + 1'b1;
					end
				else if (~inc_up && inc_dn && k_i == 12'd999)
					begin

						k_i <= 12'd0;
					end
				else if (inc_up && ~inc_dn && k_i > 12'd0)
					begin

						k_i <= k_i - 1'b1;
					end
				else if (inc_up && ~inc_dn && k_i == 12'd0)
					begin

						k_i <= 12'd999;
					end
				else
					begin

						k_i <= k_i;
					end
			end


		4'b0001:
			begin
				if (~inc_up && inc_dn && k_d < 12'd999)
					begin

						k_d <= k_d + 1'b1;
					end
				else if (~inc_up && inc_dn && k_d == 12'd999)
					begin

						k_d <= 12'd0;
					end
				else if (inc_up && ~inc_dn && k_d > 12'd0)
					begin

						k_d <= k_d - 1'b1;
					end
				else if (inc_up && ~inc_dn && k_d == 12'd0)
					begin

						k_d <= 12'd999;
					end
				else
					begin

						k_d <= k_d;
					end
			end

		default:
			begin

				k_p <= k_p;
				k_i <= k_i;
				k_d <= k_d;
				user_control_speed <= user_control_speed;
			end

		endcase


		kval_to_lcd <= {p100, p10, p1, i100, i10, i1, d100, d10, d1};
		velocity_to_lcd <= {c1000, c100, c10, c1, s1000, s100, s10, s1};


		
	end


decimal_val kp_ascii(k_p, p100, p10, p1);
decimal_val ki_ascii(k_i, i100, i10, i1);
decimal_val kd_ascii(k_d, d100, d10, d1);


velocity_decimal_val comm_ascii(command_speed, c1000, c100, c10, c1);
velocity_decimal_val sens_ascii(feedback_speed, s1000, s100, s10, s1);


always @(posedge clk)
	begin
		ui_clock_counter <= ui_clock_counter + 1'b1;
		
		if (ui_clock_counter == 24'b0011_1111_1111_1111_1111_1111)
			begin
				ui_clock_counter <= 24'd0;
				ui_clock_pulse <= ~ui_clock_pulse;
			end
	end


always @(posedge clk)
	begin
		lcd_clock_counter <= lcd_clock_counter + 1'b1;

		if (lcd_clock_counter == 16'd32_768)
			begin
				lcd_clock_counter <= 0;
				lcd_clock_pulse <= ~lcd_clock_pulse;
			end
	end


always @(posedge clk)
	begin
		if (lcd_reset_counter == 32'd0)
			begin
				lcd_reset_counter <= 32'd20_000_000;
				lcd_reset_pulse <= ~lcd_reset_pulse;
			end
		else 
			begin
				lcd_reset_counter <= lcd_reset_counter - 1'b1;
			end
	end
	

motor_rpm_count count_pulse(clk, motor_rot_pulse, motor_rpm_return);
	

always @(*)
	begin
		feedback_speed <= motor_rpm_return;
	end
	
	

output_pwm_gen out_pulse(clk, command_speed, velocity_command_pulse);
			

seg7_act_val kval_disp(k_p, k_i, k_d, user_control_speed, active_ui_control, seg7_k, seg7_eq, seg7_thousands, seg7_hundreds, seg7_tens, seg7_ones);
lcd lcd(lcd_clock_pulse, lcd_reset_pulse, kval_to_lcd, velocity_to_lcd, disp_rs, disp_rw, disp_en, disp_data);


endmodule
module pid (
	input clk,
	input res,
	input c_active,
	input kp_active,
	input ki_active,
	input kd_active,
	input inc_up,
	input inc_dn,
	input motor_rot_pulse,
	output disp_rs,
	output disp_rw,
	output disp_en,
	output display_on,
	output [7:0]disp_data,
	output [6:0]seg7_k,
	output [6:0]seg7_eq,
	output [6:0]seg7_thousands,
	output [6:0]seg7_hundreds,
	output [6:0]seg7_tens,
	output [6:0]seg7_ones,
	output velocity_command_pulse
);






reg signed [15:0]command_speed;
reg signed [15:0]prev_command_speed;
reg signed [15:0]current_error;
reg signed [15:0]last_error;
reg signed [15:0]prior_error;
reg signed [15:0]user_control_speed;
reg signed [15:0]feedback_speed;
wire [15:0]motor_rpm_return;




reg [71:0]kval_to_lcd;



reg [63:0]velocity_to_lcd;


reg signed [11:0]k_p;
reg signed [11:0]k_i;
reg signed [11:0]k_d;


wire [7:0]p100;
wire [7:0]p10;
wire [7:0]p1;
wire [7:0]i100;
wire [7:0]i10;
wire [7:0]i1;
wire [7:0]d100;
wire [7:0]d10;
wire [7:0]d1;


wire [7:0]c1000;
wire [7:0]c100;
wire [7:0]c10;
wire [7:0]c1;
wire [7:0]s1000;
wire [7:0]s100;
wire [7:0]s10;
wire [7:0]s1;



reg signed [15:0]k_1;
reg signed [15:0]k_2;
reg signed [15:0]k_3;


reg [3:0]active_ui_control;


reg [23:0]ui_clock_counter;


reg [15:0]lcd_clock_counter;


reg [31:0]lcd_reset_counter;


reg ui_clock_pulse;


reg lcd_clock_pulse;


reg lcd_reset_pulse;


initial
	begin
	 	k_p = 12'd0;
	 	k_i = 12'd0;
	 	k_d = 12'd0;
		user_control_speed = 16'd1000;
	 end 


 assign display_on = 1'b1;


 always @(posedge clk)
 	begin
 		k_1 <= k_p + k_i + k_d;
 		k_2 <= -k_p - (2 * k_d);
 		k_3 <= k_d; 
 	end


always @(posedge clk)
	begin
		if (res == 1'b0)
			begin

				prev_command_speed <= 16'd0;
				current_error <= 16'd0;
				last_error <= 16'd0;
				prior_error <= 16'd0;
			end
		else
			begin

				prev_command_speed <= command_speed;
				prior_error <= last_error;
				last_error <= current_error;
			end

		current_error <= command_speed - feedback_speed;
		command_speed <= prev_command_speed + (((k_1 * current_error) - (k_2 * last_error) + (k_3 * prior_error)) / 10000);

	end
	




always @(posedge ui_clock_pulse)
	begin

		active_ui_control<= {c_active, kp_active, ki_active, kd_active};


		case (active_ui_control)
		

		4'b1000:
			begin
				if (~inc_up && inc_dn && user_control_speed < 16'd9999)
					begin

						user_control_speed <= user_control_speed + 1'b1;
					end
				else if (~inc_up && inc_dn && user_control_speed == 16'd9999)
					begin

						user_control_speed <= 16'd0;
					end
				else if (inc_up && ~inc_dn && user_control_speed > 16'd0)
					begin

						user_control_speed <= user_control_speed - 1'b1;
					end
				else if (inc_up && ~inc_dn && user_control_speed == 16'd0)
					begin

						user_control_speed <= 16'd9999;
					end
				else
					begin

						user_control_speed <= user_control_speed;
					end
			end


		4'b0100:
			begin
				if (~inc_up && inc_dn && k_p < 12'd999)
					begin

						k_p <= k_p + 1'b1;
					end
				else if (~inc_up && inc_dn && k_p == 12'd999)
					begin

						k_p <= 12'd0;
					end
				else if (inc_up && ~inc_dn && k_p > 12'd0)
					begin

						k_p <= k_p - 1'b1;
					end
				else if (inc_up && ~inc_dn && k_p == 12'd0)
					begin

						k_p <= 12'd999;
					end
				else
					begin

						k_p <= k_p;
					end
			end


		4'b0010:
			begin
				if (~inc_up && inc_dn && k_i < 12'd999)
					begin

						k_i <= k_i + 1'b1;
					end
				else if (~inc_up && inc_dn && k_i == 12'd999)
					begin

						k_i <= 12'd0;
					end
				else if (inc_up && ~inc_dn && k_i > 12'd0)
					begin

						k_i <= k_i - 1'b1;
					end
				else if (inc_up && ~inc_dn && k_i == 12'd0)
					begin

						k_i <= 12'd999;
					end
				else
					begin

						k_i <= k_i;
					end
			end


		4'b0001:
			begin
				if (~inc_up && inc_dn && k_d < 12'd999)
					begin

						k_d <= k_d + 1'b1;
					end
				else if (~inc_up && inc_dn && k_d == 12'd999)
					begin

						k_d <= 12'd0;
					end
				else if (inc_up && ~inc_dn && k_d > 12'd0)
					begin

						k_d <= k_d - 1'b1;
					end
				else if (inc_up && ~inc_dn && k_d == 12'd0)
					begin

						k_d <= 12'd999;
					end
				else
					begin

						k_d <= k_d;
					end
			end

		default:
			begin

				k_p <= k_p;
				k_i <= k_i;
				k_d <= k_d;
				user_control_speed <= user_control_speed;
			end

		endcase


		kval_to_lcd <= {p100, p10, p1, i100, i10, i1, d100, d10, d1};
		velocity_to_lcd <= {c1000, c100, c10, c1, s1000, s100, s10, s1};


		
	end


decimal_val kp_ascii(k_p, p100, p10, p1);
decimal_val ki_ascii(k_i, i100, i10, i1);
decimal_val kd_ascii(k_d, d100, d10, d1);


velocity_decimal_val comm_ascii(command_speed, c1000, c100, c10, c1);
velocity_decimal_val sens_ascii(feedback_speed, s1000, s100, s10, s1);


always @(posedge clk)
	begin
		ui_clock_counter <= ui_clock_counter + 1'b1;
		
		if (ui_clock_counter == 24'b0011_1111_1111_1111_1111_1111)
			begin
				ui_clock_counter <= 24'd0;
				ui_clock_pulse <= ~ui_clock_pulse;
			end
	end


always @(posedge clk)
	begin
		lcd_clock_counter <= lcd_clock_counter + 1'b1;

		if (lcd_clock_counter == 16'd32_768)
			begin
				lcd_clock_counter <= 0;
				lcd_clock_pulse <= ~lcd_clock_pulse;
			end
	end


always @(posedge clk)
	begin
		if (lcd_reset_counter == 32'd0)
			begin
				lcd_reset_counter <= 32'd20_000_000;
				lcd_reset_pulse <= ~lcd_reset_pulse;
			end
		else 
			begin
				lcd_reset_counter <= lcd_reset_counter - 1'b1;
			end
	end
	

motor_rpm_count count_pulse(clk, motor_rot_pulse, motor_rpm_return);
	

always @(*)
	begin
		feedback_speed <= motor_rpm_return;
	end
	
	

output_pwm_gen out_pulse(clk, command_speed, velocity_command_pulse);
			

seg7_act_val kval_disp(k_p, k_i, k_d, user_control_speed, active_ui_control, seg7_k, seg7_eq, seg7_thousands, seg7_hundreds, seg7_tens, seg7_ones);
lcd lcd(lcd_clock_pulse, lcd_reset_pulse, kval_to_lcd, velocity_to_lcd, disp_rs, disp_rw, disp_en, disp_data);


endmodule