data/full_repos/permissive/493212017/processor/toplevel.v
1: b'%Error: data/full_repos/permissive/493212017/processor/toplevel.v:65: Cannot find file containing module: \'SB_HFOSC\'\n SB_HFOSC #(.CLKHF_DIV("0b10")) OSCInst0 (\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/493212017/processor,data/full_repos/permissive/493212017/SB_HFOSC\n             data/full_repos/permissive/493212017/processor,data/full_repos/permissive/493212017/SB_HFOSC.v\n             data/full_repos/permissive/493212017/processor,data/full_repos/permissive/493212017/SB_HFOSC.sv\n             SB_HFOSC\n             SB_HFOSC.v\n             SB_HFOSC.sv\n             obj_dir/SB_HFOSC\n             obj_dir/SB_HFOSC.v\n             obj_dir/SB_HFOSC.sv\n%Error: data/full_repos/permissive/493212017/processor/toplevel.v:71: Cannot find file containing module: \'pll\'\n pll pll_inst(\n ^~~\n%Error: data/full_repos/permissive/493212017/processor/toplevel.v:93: Cannot find file containing module: \'cpu\'\n cpu processor(\n ^~~\n%Error: data/full_repos/permissive/493212017/processor/toplevel.v:105: Cannot find file containing module: \'instruction_memory\'\n instruction_memory inst_mem(\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493212017/processor/toplevel.v:110: Cannot find file containing module: \'data_mem\'\n data_mem data_mem_inst(\n ^~~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module top (led);
	output [7:0]	led;

	reg		clk		= 1'b0;
	wire		clk_proc;
	wire		data_clk_stall;

`ifdef SIMULATION_MODE
	always #1 clk = ~clk;

	initial $dumpvars;
`else
	wire		clk_12;
	wire		clk_pll;


	SB_HFOSC #(.CLKHF_DIV("0b10")) OSCInst0 (
		.CLKHFEN(1'b1),
		.CLKHFPU(1'b1),
		.CLKHF(clk_12)
	);

	pll pll_inst(
		.clock_in(clk_12),
		.clock_out(clk_pll),
	);

	always @(posedge clk_pll)
		clk <= ~clk;
`endif


	wire[31:0]	inst_in;
	wire[31:0]	inst_out;
	wire[31:0]	data_out;
	wire[31:0]	data_addr;
	wire[31:0]	data_WrData;
	wire		data_memwrite;
	wire		data_memread;
	wire[3:0]	data_sign_mask;


	cpu processor(
		.clk(clk_proc),
		.inst_mem_in(inst_in),
		.inst_mem_out(inst_out),
		.data_mem_out(data_out),
		.data_mem_addr(data_addr),
		.data_mem_WrData(data_WrData),
		.data_mem_memwrite(data_memwrite),
		.data_mem_memread(data_memread),
		.data_mem_sign_mask(data_sign_mask)
	);

	instruction_memory inst_mem(
		.addr(inst_in),
		.out(inst_out)
	);

	data_mem data_mem_inst(
			.clk(clk),
			.addr(data_addr),
			.write_data(data_WrData),
			.memwrite(data_memwrite),
			.memread(data_memread),
			.read_data(data_out),
			.sign_mask(data_sign_mask),
			.led(led),
			.clk_stall(data_clk_stall)
		);

	assign clk_proc = data_clk_stall ? 1'b1 : clk;
endmodule
module top (led);

	output [7:0]	led;

	reg		clk		= 1'b0;
	wire		clk_proc;
	wire		data_clk_stall;

`ifdef SIMULATION_MODE
	always #1 clk = ~clk;

	initial $dumpvars;
`else
	wire		clk_12;
	wire		clk_pll;


	SB_HFOSC #(.CLKHF_DIV("0b10")) OSCInst0 (
		.CLKHFEN(1'b1),
		.CLKHFPU(1'b1),
		.CLKHF(clk_12)
	);

	pll pll_inst(
		.clock_in(clk_12),
		.clock_out(clk_pll),
	);

	always @(posedge clk_pll)
		clk <= ~clk;
`endif


	wire[31:0]	inst_in;
	wire[31:0]	inst_out;
	wire[31:0]	data_out;
	wire[31:0]	data_addr;
	wire[31:0]	data_WrData;
	wire		data_memwrite;
	wire		data_memread;
	wire[3:0]	data_sign_mask;


	cpu processor(
		.clk(clk_proc),
		.inst_mem_in(inst_in),
		.inst_mem_out(inst_out),
		.data_mem_out(data_out),
		.data_mem_addr(data_addr),
		.data_mem_WrData(data_WrData),
		.data_mem_memwrite(data_memwrite),
		.data_mem_memread(data_memread),
		.data_mem_sign_mask(data_sign_mask)
	);

	instruction_memory inst_mem(
		.addr(inst_in),
		.out(inst_out)
	);

	data_mem data_mem_inst(
			.clk(clk),
			.addr(data_addr),
			.write_data(data_WrData),
			.memwrite(data_memwrite),
			.memread(data_memread),
			.read_data(data_out),
			.sign_mask(data_sign_mask),
			.led(led),
			.clk_stall(data_clk_stall)
		);

	assign clk_proc = data_clk_stall ? 1'b1 : clk;
endmodule