data/full_repos/permissive/489633918/verilog/rtl/user_project_wrapper.v
1: b"%Error: data/full_repos/permissive/489633918/verilog/rtl/user_project_wrapper.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489633918/verilog/rtl/user_project_wrapper.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489633918/verilog/rtl/user_project_wrapper.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489633918/verilog/rtl/user_project_wrapper.v:72: Define or directive not defined: '`MPRJ_IO_PADS'\n    inout [`MPRJ_IO_PADS-10:0] analog_io,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489633918/verilog/rtl/user_project_wrapper.v:100: Define or directive not defined: '`MPRJ_IO_PADS'\n  assign io_oeb = {(`MPRJ_IO_PADS-1){1'b1}};\n                    ^~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module user_project_wrapper #(
    parameter BITS = 32
) (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,





    inout [`MPRJ_IO_PADS-10:0] analog_io,


    input   user_clock2,


    output [2:0] user_irq
);




  localparam  NRegisters = 3;

  wire [31:0] rdata; 
  wire [31:0] wdata;
  wire        ready;
  wire        valid;
  wire [31:0] la_write;

  wire clk;
  wire rst;

  assign valid = wbs_cyc_i && wbs_stb_i; 
  assign wbs_dat_o = rdata;
  assign wdata = wbs_dat_i;

  assign io_out = 0;
  assign io_oeb = {(`MPRJ_IO_PADS-1){1'b1}};


  assign user_irq = 3'b000;


  assign la_data_out = {{64{1'b0}}, wdata, rdata};

  assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
  assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
    
  assign wbs_ack_o = ready;


  reg         ready_q;
  
  assign rdata = sram0_dout1[sram_select];
  assign ready = ready_q;

  wire [31:0] sram0_dout0 [3:0];
  wire [31:0] sram0_dout1 [3:0];

  wire [1:0] sram_select;
  assign sram_select =  wbs_adr_i[12:11];
  wire [8:0] sram_address;
  assign sram_address = wbs_adr_i[10:0] >> 2;


  sky130_sram_2kbyte_1rw1r_32x512_8 SRAM0 (
    `ifdef USE_POWER_PINS
      .vccd1(vccd1),
      .vssd1(vssd1),
    `endif
    .clk0   (clk),
    .csb0   (!(!wbs_adr_i[12] & !wbs_adr_i[11] & valid & !ready_q & wbs_we_i)),
    .web0   (1'b0),
    .wmask0 (4'hF),
    .addr0  (sram_address),
    .din0   (wdata),
    .dout0  (sram0_dout0[0]),
    .clk1   (clk),
    .csb1   (!(!wbs_adr_i[12] & !wbs_adr_i[11] & valid & !ready_q & !wbs_we_i)),
    .addr1  (sram_address),
    .dout1  (sram0_dout1[0])
  );

    sky130_sram_2kbyte_1rw1r_32x512_8 SRAM1 (
    `ifdef USE_POWER_PINS
      .vccd1(vccd1),
      .vssd1(vssd1),
    `endif
    .clk0   (clk),
    .csb0   (!(!wbs_adr_i[12] & wbs_adr_i[11] & valid & !ready_q & wbs_we_i)),
    .web0   (1'b0),
    .wmask0 (4'hF),
    .addr0  (sram_address),
    .din0   (wdata),
    .dout0  (sram0_dout0[1]),
    .clk1   (clk),
    .csb1   (!(!wbs_adr_i[12] & wbs_adr_i[11] & valid & !ready_q & !wbs_we_i)),
    .addr1  (sram_address),
    .dout1  (sram0_dout1[1])
  );

    sky130_sram_2kbyte_1rw1r_32x512_8 SRAM2 (
    `ifdef USE_POWER_PINS
      .vccd1(vccd1),
      .vssd1(vssd1),
    `endif
    .clk0   (clk),
    .csb0   (!(wbs_adr_i[12] & !wbs_adr_i[11] & valid & !ready_q & wbs_we_i)),
    .web0   (1'b0),
    .wmask0 (4'hF),
    .addr0  (sram_address),
    .din0   (wdata),
    .dout0  (sram0_dout0[2]),
    .clk1   (clk),
    .csb1   (!(wbs_adr_i[12] & !wbs_adr_i[11] & valid & !ready_q & !wbs_we_i)),
    .addr1  (sram_address),
    .dout1  (sram0_dout1[2])
  );

    sky130_sram_2kbyte_1rw1r_32x512_8 SRAM3 (
    `ifdef USE_POWER_PINS
      .vccd1(vccd1),
      .vssd1(vssd1),
    `endif
    .clk0   (clk),
    .csb0   (!(wbs_adr_i[12] & wbs_adr_i[11] & valid & !ready_q & wbs_we_i)),
    .web0   (1'b0),
    .wmask0 (4'hF),
    .addr0  (sram_address),
    .din0   (wdata),
    .dout0  (sram0_dout0[3]),
    .clk1   (clk),
    .csb1   (!(wbs_adr_i[12] & wbs_adr_i[11] & valid & !ready_q & !wbs_we_i)),
    .addr1  (sram_address),
    .dout1  (sram0_dout1[3])
  );

  always @(posedge clk) begin
    if (!rst == 0) begin
      ready_q <= 0;
    end else begin
      ready_q <= 1'b0;
      if (valid && !ready_q) begin
        ready_q <= 1'b1;
      end
    end
  end
endmodule
module user_project_wrapper #(
    parameter BITS = 32
) (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,





    inout [`MPRJ_IO_PADS-10:0] analog_io,


    input   user_clock2,


    output [2:0] user_irq
);





  localparam  NRegisters = 3;

  wire [31:0] rdata; 
  wire [31:0] wdata;
  wire        ready;
  wire        valid;
  wire [31:0] la_write;

  wire clk;
  wire rst;

  assign valid = wbs_cyc_i && wbs_stb_i; 
  assign wbs_dat_o = rdata;
  assign wdata = wbs_dat_i;

  assign io_out = 0;
  assign io_oeb = {(`MPRJ_IO_PADS-1){1'b1}};


  assign user_irq = 3'b000;


  assign la_data_out = {{64{1'b0}}, wdata, rdata};

  assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
  assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
    
  assign wbs_ack_o = ready;


  reg         ready_q;
  
  assign rdata = sram0_dout1[sram_select];
  assign ready = ready_q;

  wire [31:0] sram0_dout0 [3:0];
  wire [31:0] sram0_dout1 [3:0];

  wire [1:0] sram_select;
  assign sram_select =  wbs_adr_i[12:11];
  wire [8:0] sram_address;
  assign sram_address = wbs_adr_i[10:0] >> 2;


  sky130_sram_2kbyte_1rw1r_32x512_8 SRAM0 (
    `ifdef USE_POWER_PINS
      .vccd1(vccd1),
      .vssd1(vssd1),
    `endif
    .clk0   (clk),
    .csb0   (!(!wbs_adr_i[12] & !wbs_adr_i[11] & valid & !ready_q & wbs_we_i)),
    .web0   (1'b0),
    .wmask0 (4'hF),
    .addr0  (sram_address),
    .din0   (wdata),
    .dout0  (sram0_dout0[0]),
    .clk1   (clk),
    .csb1   (!(!wbs_adr_i[12] & !wbs_adr_i[11] & valid & !ready_q & !wbs_we_i)),
    .addr1  (sram_address),
    .dout1  (sram0_dout1[0])
  );

    sky130_sram_2kbyte_1rw1r_32x512_8 SRAM1 (
    `ifdef USE_POWER_PINS
      .vccd1(vccd1),
      .vssd1(vssd1),
    `endif
    .clk0   (clk),
    .csb0   (!(!wbs_adr_i[12] & wbs_adr_i[11] & valid & !ready_q & wbs_we_i)),
    .web0   (1'b0),
    .wmask0 (4'hF),
    .addr0  (sram_address),
    .din0   (wdata),
    .dout0  (sram0_dout0[1]),
    .clk1   (clk),
    .csb1   (!(!wbs_adr_i[12] & wbs_adr_i[11] & valid & !ready_q & !wbs_we_i)),
    .addr1  (sram_address),
    .dout1  (sram0_dout1[1])
  );

    sky130_sram_2kbyte_1rw1r_32x512_8 SRAM2 (
    `ifdef USE_POWER_PINS
      .vccd1(vccd1),
      .vssd1(vssd1),
    `endif
    .clk0   (clk),
    .csb0   (!(wbs_adr_i[12] & !wbs_adr_i[11] & valid & !ready_q & wbs_we_i)),
    .web0   (1'b0),
    .wmask0 (4'hF),
    .addr0  (sram_address),
    .din0   (wdata),
    .dout0  (sram0_dout0[2]),
    .clk1   (clk),
    .csb1   (!(wbs_adr_i[12] & !wbs_adr_i[11] & valid & !ready_q & !wbs_we_i)),
    .addr1  (sram_address),
    .dout1  (sram0_dout1[2])
  );

    sky130_sram_2kbyte_1rw1r_32x512_8 SRAM3 (
    `ifdef USE_POWER_PINS
      .vccd1(vccd1),
      .vssd1(vssd1),
    `endif
    .clk0   (clk),
    .csb0   (!(wbs_adr_i[12] & wbs_adr_i[11] & valid & !ready_q & wbs_we_i)),
    .web0   (1'b0),
    .wmask0 (4'hF),
    .addr0  (sram_address),
    .din0   (wdata),
    .dout0  (sram0_dout0[3]),
    .clk1   (clk),
    .csb1   (!(wbs_adr_i[12] & wbs_adr_i[11] & valid & !ready_q & !wbs_we_i)),
    .addr1  (sram_address),
    .dout1  (sram0_dout1[3])
  );

  always @(posedge clk) begin
    if (!rst == 0) begin
      ready_q <= 0;
    end else begin
      ready_q <= 1'b0;
      if (valid && !ready_q) begin
        ready_q <= 1'b1;
      end
    end
  end
endmodule