data/full_repos/permissive/520452389/source_codes/Instruction_decode.v
data/verilator_xmls/2e96dc06-b42e-437b-9353-c464005c937c.xml
module Register_mem (input reset,input [4:0]read_reg1,input [4:0]read_reg2,input [4:0]write_reg_s4,
                     input [31:0]write_data,output reg [31:0]read_data1,output reg [31:0]read_data2,input RegWrite);

reg [31:0]reg_mem[31:0];
reg [31:0]i;
always @(*) begin 
     if(reset)begin 
     for (i = 0; i < 32; i=i+1) 
        reg_mem[i] = i;
     end
     read_data1 = reg_mem[read_reg1];
     read_data2 = reg_mem[read_reg2]; 
     if(RegWrite) begin
             reg_mem[write_reg_s4 ] = write_data;
     end
end

endmodule
module Register_mem (input reset,input [4:0]read_reg1,input [4:0]read_reg2,input [4:0]write_reg_s4,
                     input [31:0]write_data,output reg [31:0]read_data1,output reg [31:0]read_data2,input RegWrite);


reg [31:0]reg_mem[31:0];
reg [31:0]i;
always @(*) begin 
     if(reset)begin 
     for (i = 0; i < 32; i=i+1) 
        reg_mem[i] = i;
     end
     read_data1 = reg_mem[read_reg1];
     read_data2 = reg_mem[read_reg2]; 
     if(RegWrite) begin
             reg_mem[write_reg_s4 ] = write_data;
     end
end

endmodule