data/full_repos/permissive/507298761/Test_Bench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/507298761/Test_Bench.v:10: Unsupported: Ignoring delay on this delayed statement.\nalways #(20) clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/507298761/Test_Bench.v:14: Unsupported: Ignoring delay on this delayed statement.\n# 40;\n^\n%Warning-STMTDLY: data/full_repos/permissive/507298761/Test_Bench.v:16: Unsupported: Ignoring delay on this delayed statement.\n# 40;\n^\n%Error: data/full_repos/permissive/507298761/Test_Bench.v:5: Cannot find file containing module: \'traffic\'\ntraffic uut\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507298761,data/full_repos/permissive/507298761/traffic\n             data/full_repos/permissive/507298761,data/full_repos/permissive/507298761/traffic.v\n             data/full_repos/permissive/507298761,data/full_repos/permissive/507298761/traffic.sv\n             traffic\n             traffic.v\n             traffic.sv\n             obj_dir/traffic\n             obj_dir/traffic.v\n             obj_dir/traffic.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module traffic_test();
reg clk; reg rst;
wire [2:0] light_A; wire [2:0]
light_B;
traffic uut
(.clk(clk), .rst(rst), .light_A(light_A
),
.light_B(light_B));
initial clk = 1;
always #(20) clk = ~clk;

initial begin
rst = 0;
# 40;
rst = 1;
# 40;
rst = 0;
$stop;
end
endmodule
module traffic_test();

reg clk; reg rst;
wire [2:0] light_A; wire [2:0]
light_B;
traffic uut
(.clk(clk), .rst(rst), .light_A(light_A
),
.light_B(light_B));
initial clk = 1;
always #(20) clk = ~clk;

initial begin
rst = 0;
# 40;
rst = 1;
# 40;
rst = 0;
$stop;
end
endmodule