data/full_repos/permissive/446997925/hw4/control_unit_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/446997925/hw4/control_unit_testbench.v:13: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/446997925/hw4/control_unit_testbench.v:15: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/446997925/hw4/control_unit_testbench.v:17: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/446997925/hw4/control_unit_testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/446997925/hw4/control_unit_testbench.v:21: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/446997925/hw4/control_unit_testbench.v:23: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/446997925/hw4/control_unit_testbench.v:25: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/446997925/hw4/control_unit_testbench.v:27: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/446997925/hw4/control_unit_testbench.v:29: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Error: data/full_repos/permissive/446997925/hw4/control_unit_testbench.v:36: Unsupported or unknown PLI call: $monitor\n$monitor("time=%2d, op=%4b, regdst=%1b, alusrc=%1b, memtoreg=%1b, regwrite=%1b, memread=%1b, memwrite=%1b, branch=%1b, branchn=%1b, aluop=%3b",\n^~~~~~~~\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module control_unit_testbench();

reg [3:0] op;
wire regDst, aluSrc, memToReg,regWrite,memRead,memWrite,branch,branchN;
wire [2:0] aluop;

control_unit test (regDst, aluSrc, memToReg, regWrite, memRead, memWrite, branch, branchN,aluop,op);


initial begin
op = 4'b0000;
#`DELAY;
op = 4'b0001;
#`DELAY;
op = 4'b0010;
#`DELAY;
op = 4'b0011;
#`DELAY;
op = 4'b0100;
#`DELAY;
op = 4'b0101;
#`DELAY;
op = 4'b0110;
#`DELAY;
op = 4'b0111;
#`DELAY;
op = 4'b1000;
#`DELAY;
op = 4'b1001;
end
 
 
initial
begin
$monitor("time=%2d, op=%4b, regdst=%1b, alusrc=%1b, memtoreg=%1b, regwrite=%1b, memread=%1b, memwrite=%1b, branch=%1b, branchn=%1b, aluop=%3b",
													$time,op,regDst,aluSrc, memToReg,regWrite,memRead,memWrite,branch,branchN,aluop);
end
 


endmodule
module control_unit_testbench();


reg [3:0] op;
wire regDst, aluSrc, memToReg,regWrite,memRead,memWrite,branch,branchN;
wire [2:0] aluop;

control_unit test (regDst, aluSrc, memToReg, regWrite, memRead, memWrite, branch, branchN,aluop,op);


initial begin
op = 4'b0000;
#`DELAY;
op = 4'b0001;
#`DELAY;
op = 4'b0010;
#`DELAY;
op = 4'b0011;
#`DELAY;
op = 4'b0100;
#`DELAY;
op = 4'b0101;
#`DELAY;
op = 4'b0110;
#`DELAY;
op = 4'b0111;
#`DELAY;
op = 4'b1000;
#`DELAY;
op = 4'b1001;
end
 
 
initial
begin
$monitor("time=%2d, op=%4b, regdst=%1b, alusrc=%1b, memtoreg=%1b, regwrite=%1b, memread=%1b, memwrite=%1b, branch=%1b, branchn=%1b, aluop=%3b",
													$time,op,regDst,aluSrc, memToReg,regWrite,memRead,memWrite,branch,branchN,aluop);
end
 


endmodule