data/full_repos/permissive/463481430/RTL/core/ifu.v
1: b'%Error: data/full_repos/permissive/463481430/RTL/core/ifu.v:27: Cannot find include file: config.v\n`include "config.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463481430/RTL/core,data/full_repos/permissive/463481430/config.v\n             data/full_repos/permissive/463481430/RTL/core,data/full_repos/permissive/463481430/config.v.v\n             data/full_repos/permissive/463481430/RTL/core,data/full_repos/permissive/463481430/config.v.sv\n             config.v\n             config.v.v\n             config.v.sv\n             obj_dir/config.v\n             obj_dir/config.v.v\n             obj_dir/config.v.sv\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu.v:38: Define or directive not defined: \'`xlen_def\'\n    input wire[`xlen_def] i_bpu_jaddr,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu.v:38: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire[`xlen_def] i_bpu_jaddr,\n                        ^\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu.v:41: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[`xlen_def] i_exu_jaddr,\n    ^~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu.v:41: Define or directive not defined: \'`xlen_def\'\n    input wire[`xlen_def] i_exu_jaddr,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu.v:45: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire[`xlen_def] o_iaddr,\n    ^~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu.v:45: Define or directive not defined: \'`xlen_def\'\n    output wire[`xlen_def] o_iaddr,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu.v:46: Define or directive not defined: \'`ilen_def\'\n                                                              : ... Suggested alternative: \'`ifndef\'\n    output wire[`ilen_def] o_data,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu.v:51: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire o_ribm_wrcs, \n    ^~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu.v:52: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire[3:0] o_ribm_mask,  \n    ^~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu.v:53: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire[31:0] o_ribm_wdata,  \n    ^~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu.v:54: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[31:0] i_ribm_rdata,  \n    ^~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu.v:55: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire o_ribm_req,  \n    ^~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu.v:56: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire i_ribm_gnt,  \n    ^~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu.v:57: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire i_ribm_rsp,  \n    ^~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu.v:58: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire o_ribm_rdy  \n    ^~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu.v:62: Define or directive not defined: \'`xlen_def\'\n    wire[`xlen_def] jump_addr;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu.v:62: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`xlen_def] jump_addr;\n                  ^\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu.v:80: Define or directive not defined: \'`xlen_def\'\n    wire[`xlen_def] fetch_addr;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu.v:80: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    wire[`xlen_def] fetch_addr;\n                  ^\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu.v:83: syntax error, unexpected IDENTIFIER\n    IFU_PC u_IFU_PC(\n    ^~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu.v:134: syntax error, unexpected IDENTIFIER\n    IFU_FIFO#(\n    ^~~~~~~~\n%Error: Exiting due to 22 error(s)\n'
module IFU (
    input wire i_clk,
    input wire i_rstn,


    input wire i_fetch_vld,


    input wire i_bpu_taken,
    input wire[`xlen_def] i_bpu_jaddr,

    input wire i_exu_taken,
    input wire[`xlen_def] i_exu_jaddr,
    

    output wire o_data_vld,
    output wire[`xlen_def] o_iaddr,
    output wire[`ilen_def] o_data,



    output wire[31:0] o_ribm_addr,
    output wire o_ribm_wrcs,
    output wire[3:0] o_ribm_mask,
    output wire[31:0] o_ribm_wdata,
    input wire[31:0] i_ribm_rdata,
    output wire o_ribm_req,
    input wire i_ribm_gnt,
    input wire i_ribm_rsp,
    output wire o_ribm_rdy
);

    wire jump_flag;
    wire[`xlen_def] jump_addr;
    IFU_BJU u_IFU_BJU(
        .i_clk       ( i_clk       ),
        .i_rstn      ( i_rstn      ),

        .i_bpu_taken ( i_bpu_taken ),
        .i_bpu_jaddr ( i_bpu_jaddr ),

        .i_exu_taken ( i_exu_taken ),
        .i_exu_jaddr ( i_exu_jaddr ),

        .o_jump      ( jump_flag   ),
        .o_jump_addr ( jump_addr   )
    );

    wire pc_vld;
    wire access_vld;
    wire data_vld;
    wire[`xlen_def] fetch_addr;
    wire fifo_empty;

    IFU_PC u_IFU_PC(
        .i_clk        ( i_clk           ),
        .i_rstn       ( i_rstn          ),



        .i_fetch_vld  ( i_fetch_vld     ),
        .i_fifo_empty ( fifo_empty        ),
        .i_pc_goback  ( o_iaddr         ),


        .i_pc_vld     ( pc_vld          ),
        .i_jump       ( jump_flag       ),
        .i_jump_addr  ( jump_addr       ),   
        .o_fetch_addr ( fetch_addr      )
    );


    IFU_FETCH u_IFU_FETCH(  
        .i_clk           ( i_clk            ),
        .i_rstn          ( i_rstn           ),

        .i_fetch_addr    ( fetch_addr       ),
        .i_fetch_vld     ( i_fetch_vld      ),
        .i_jump_flag     ( jump_flag        ),

        .o_pc_vld        ( pc_vld           ),
        .o_access_vld    ( access_vld       ),
        .o_data_vld      ( data_vld         ),
        .o_data          ( o_data           ),

        .o_ribm_addr     ( o_ribm_addr      ),
        .o_ribm_wrcs     ( o_ribm_wrcs      ),
        .o_ribm_mask     ( o_ribm_mask      ),
        .o_ribm_wdata    ( o_ribm_wdata     ),
        .i_ribm_rdata    ( i_ribm_rdata     ),
        
        .o_ribm_req      ( o_ribm_req       ),
        .i_ribm_gnt      ( i_ribm_gnt       ),
        .i_ribm_rsp      ( i_ribm_rsp       ),
        .o_ribm_rdy      ( o_ribm_rdy       )
    );


    parameter fifo_dpth = 1;

    
    wire[$clog2(fifo_dpth):0] fifo_cnt;



    IFU_FIFO#(
        .unitwid    ( 32 ),
        .unitdpth   ( fifo_dpth ) 
    )u_IFU_FIFO(
        .i_clk      ( i_clk         ),
        .i_rstn     ( i_rstn  ),
       
        .i_flush    (  0  ),


        .i_wen      ( pc_vld        ),
        .i_unitdata ( fetch_addr    ),



        .i_ren      ( access_vld    ), 
        .o_unitdata ( o_iaddr    ),
        .o_empty    ( fifo_empty ),
        .o_fifo_cnt ( fifo_cnt   )
    );







    assign o_data_vld = i_fetch_vld & data_vld & (~fifo_empty);



endmodule
module IFU (
    input wire i_clk,
    input wire i_rstn,


    input wire i_fetch_vld,


    input wire i_bpu_taken,
    input wire[`xlen_def] i_bpu_jaddr,

    input wire i_exu_taken,
    input wire[`xlen_def] i_exu_jaddr,
    

    output wire o_data_vld,
    output wire[`xlen_def] o_iaddr,
    output wire[`ilen_def] o_data,



    output wire[31:0] o_ribm_addr,
    output wire o_ribm_wrcs,
    output wire[3:0] o_ribm_mask,
    output wire[31:0] o_ribm_wdata,
    input wire[31:0] i_ribm_rdata,
    output wire o_ribm_req,
    input wire i_ribm_gnt,
    input wire i_ribm_rsp,
    output wire o_ribm_rdy
);


    wire jump_flag;
    wire[`xlen_def] jump_addr;
    IFU_BJU u_IFU_BJU(
        .i_clk       ( i_clk       ),
        .i_rstn      ( i_rstn      ),

        .i_bpu_taken ( i_bpu_taken ),
        .i_bpu_jaddr ( i_bpu_jaddr ),

        .i_exu_taken ( i_exu_taken ),
        .i_exu_jaddr ( i_exu_jaddr ),

        .o_jump      ( jump_flag   ),
        .o_jump_addr ( jump_addr   )
    );

    wire pc_vld;
    wire access_vld;
    wire data_vld;
    wire[`xlen_def] fetch_addr;
    wire fifo_empty;

    IFU_PC u_IFU_PC(
        .i_clk        ( i_clk           ),
        .i_rstn       ( i_rstn          ),



        .i_fetch_vld  ( i_fetch_vld     ),
        .i_fifo_empty ( fifo_empty        ),
        .i_pc_goback  ( o_iaddr         ),


        .i_pc_vld     ( pc_vld          ),
        .i_jump       ( jump_flag       ),
        .i_jump_addr  ( jump_addr       ),   
        .o_fetch_addr ( fetch_addr      )
    );


    IFU_FETCH u_IFU_FETCH(  
        .i_clk           ( i_clk            ),
        .i_rstn          ( i_rstn           ),

        .i_fetch_addr    ( fetch_addr       ),
        .i_fetch_vld     ( i_fetch_vld      ),
        .i_jump_flag     ( jump_flag        ),

        .o_pc_vld        ( pc_vld           ),
        .o_access_vld    ( access_vld       ),
        .o_data_vld      ( data_vld         ),
        .o_data          ( o_data           ),

        .o_ribm_addr     ( o_ribm_addr      ),
        .o_ribm_wrcs     ( o_ribm_wrcs      ),
        .o_ribm_mask     ( o_ribm_mask      ),
        .o_ribm_wdata    ( o_ribm_wdata     ),
        .i_ribm_rdata    ( i_ribm_rdata     ),
        
        .o_ribm_req      ( o_ribm_req       ),
        .i_ribm_gnt      ( i_ribm_gnt       ),
        .i_ribm_rsp      ( i_ribm_rsp       ),
        .o_ribm_rdy      ( o_ribm_rdy       )
    );


    parameter fifo_dpth = 1;

    
    wire[$clog2(fifo_dpth):0] fifo_cnt;



    IFU_FIFO#(
        .unitwid    ( 32 ),
        .unitdpth   ( fifo_dpth ) 
    )u_IFU_FIFO(
        .i_clk      ( i_clk         ),
        .i_rstn     ( i_rstn  ),
       
        .i_flush    (  0  ),


        .i_wen      ( pc_vld        ),
        .i_unitdata ( fetch_addr    ),



        .i_ren      ( access_vld    ), 
        .o_unitdata ( o_iaddr    ),
        .o_empty    ( fifo_empty ),
        .o_fifo_cnt ( fifo_cnt   )
    );







    assign o_data_vld = i_fetch_vld & data_vld & (~fifo_empty);



endmodule