data/full_repos/permissive/40731079/rtl/phy/sdio_phy_sd_4bit.v
data/verilator_xmls/d48a26b8-b877-406e-9c2c-d323ed03fb82.xml
module sdio_device_phy_sd_hs (
  input               clk,
  input               rst,


  output              ddr_en,
  input               sdio_clk,
  input               sdio_cs_n,
  input [3:0]         sdio_data


);










endmodule
module sdio_device_phy_sd_hs (
  input               clk,
  input               rst,


  output              ddr_en,
  input               sdio_clk,
  input               sdio_cs_n,
  input [3:0]         sdio_data


);











endmodule