data/full_repos/permissive/435060225/top.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/435060225/top.v:14: Unsupported: Ignoring delay on this delayed statement.\n always #500 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/435060225/top.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #100000;\n  ^\n%Error: data/full_repos/permissive/435060225/top.v:35: syntax error, unexpected \'@\'\n  @(status[2] |status[1])\n  ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
    reg         resetn;
    reg [15:0]  target_clock;
    reg [15:0]  ref_counter;
    reg [ 8:0]  init;
    reg         clk;
    wire [2:0]  status;
    wire        out;


	always #500 clk = ~clk;

	CLOCK clock
	(
		.resetn(resetn),
		.ref_clk(clk),
		.ref_counter(ref_counter),
		.init(init),
		.counter(target_clock),
		.out(out),
		.status(status)
	);

	initial begin
		target_clock = 6000;
		ref_counter  = 10;
		init = 20;
		clk = 0;
		resetn = 0;
		#100000;
		resetn = 1;
		@(status[2] |status[1])
		#100000;
		$stop;
	end

endmodule
module top;

    reg         resetn;
    reg [15:0]  target_clock;
    reg [15:0]  ref_counter;
    reg [ 8:0]  init;
    reg         clk;
    wire [2:0]  status;
    wire        out;


	always #500 clk = ~clk;

	CLOCK clock
	(
		.resetn(resetn),
		.ref_clk(clk),
		.ref_counter(ref_counter),
		.init(init),
		.counter(target_clock),
		.out(out),
		.status(status)
	);

	initial begin
		target_clock = 6000;
		ref_counter  = 10;
		init = 20;
		clk = 0;
		resetn = 0;
		#100000;
		resetn = 1;
		@(status[2] |status[1])
		#100000;
		$stop;
	end

endmodule