data/full_repos/permissive/514519566/pipeline/src/source/IF_ID_Reg.v
data/verilator_xmls/e90a379b-2964-405d-b38e-560d116c26e5.xml
module IF_ID_Reg(reset, clk, wen, Flush, IF_Instuction, IF_PC_plus4);
    input reset, clk, wen, Flush;
    input [31:0] IF_Instuction, IF_PC_plus4;

    reg [31:0] Instruction, PC_plus4;
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            Instruction <= 32'h0;
            PC_plus4 <= 32'h0;
        end
        else if (wen) begin
            Instruction <= Flush? 32'h0: IF_Instuction;
            PC_plus4 <= IF_PC_plus4; 
        end
    end

endmodule
module IF_ID_Reg(reset, clk, wen, Flush, IF_Instuction, IF_PC_plus4);

    input reset, clk, wen, Flush;
    input [31:0] IF_Instuction, IF_PC_plus4;

    reg [31:0] Instruction, PC_plus4;
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            Instruction <= 32'h0;
            PC_plus4 <= 32'h0;
        end
        else if (wen) begin
            Instruction <= Flush? 32'h0: IF_Instuction;
            PC_plus4 <= IF_PC_plus4; 
        end
    end

endmodule