data/full_repos/permissive/430359604/Design/netlist/usr_nbit.v
data/verilator_xmls/9efe4e04-fb74-42c3-bf46-0b872de124b9.xml
module universal_shift_register_1bit(select, parallelin, left, right, parallelout, clk, rst);
  input [1:0] select; 
  input parallelin;
  input left;
  input right;
  input clk,rst;
  output parallelout;
  reg parallelout;
  always @(posedge clk)
    begin
	if (rst)
	begin
		parallelout<=1'b0;
	end
	else
	begin
		case(select)
			2'b00:
			begin
				parallelout <= parallelout;
                        end
                        2'b10:
                        begin
                        	parallelout <= left;
        		end
      			2'b01:
        		begin
          			parallelout <= right;
        		end
      			2'b11:
        		begin
          			parallelout <= parallelin;
        		end
		endcase
	end
      
    end
endmodule
module universal_shift_register_1bit(select, parallelin, left, right, parallelout, clk, rst);

  input [1:0] select; 
  input parallelin;
  input left;
  input right;
  input clk,rst;
  output parallelout;
  reg parallelout;
  always @(posedge clk)
    begin
	if (rst)
	begin
		parallelout<=1'b0;
	end
	else
	begin
		case(select)
			2'b00:
			begin
				parallelout <= parallelout;
                        end
                        2'b10:
                        begin
                        	parallelout <= left;
        		end
      			2'b01:
        		begin
          			parallelout <= right;
        		end
      			2'b11:
        		begin
          			parallelout <= parallelin;
        		end
		endcase
	end
      
    end
endmodule