data/full_repos/permissive/443520440/testbench/vga_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/443520440/testbench/vga_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n    always #1 vga_clk = ~vga_clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/443520440/testbench/vga_tb.v:10: Cannot find file containing module: \'vga_driver\'\n    vga_driver vga_driver_0(\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/443520440/testbench,data/full_repos/permissive/443520440/vga_driver\n             data/full_repos/permissive/443520440/testbench,data/full_repos/permissive/443520440/vga_driver.v\n             data/full_repos/permissive/443520440/testbench,data/full_repos/permissive/443520440/vga_driver.sv\n             vga_driver\n             vga_driver.v\n             vga_driver.sv\n             obj_dir/vga_driver\n             obj_dir/vga_driver.v\n             obj_dir/vga_driver.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module vga_driver_tb();
    reg vga_clk, sys_rst_n;
    reg [11:0] pixel_data;
    wire vga_hs, vga_vs;
    wire [11:0] vga_rgb;
    wire data_req;
    wire [18:0] pixel_addr;
    vga_driver vga_driver_0(
        vga_clk,
        sys_rst_n,
        vga_hs,
        vga_vs,
        vga_rgb,
        data_req,
        pixel_data,
        pixel_addr
    );
    
    initial begin
        vga_clk = 0;sys_rst_n =1;
        pixel_data = 0;
    end
    always @(pixel_addr)
        pixel_data <= pixel_addr[11:0];

    always #1 vga_clk = ~vga_clk;
    
endmodule
module vga_driver_tb();

    reg vga_clk, sys_rst_n;
    reg [11:0] pixel_data;
    wire vga_hs, vga_vs;
    wire [11:0] vga_rgb;
    wire data_req;
    wire [18:0] pixel_addr;
    vga_driver vga_driver_0(
        vga_clk,
        sys_rst_n,
        vga_hs,
        vga_vs,
        vga_rgb,
        data_req,
        pixel_data,
        pixel_addr
    );
    
    initial begin
        vga_clk = 0;sys_rst_n =1;
        pixel_data = 0;
    end
    always @(pixel_addr)
        pixel_data <= pixel_addr[11:0];

    always #1 vga_clk = ~vga_clk;
    
endmodule