data/full_repos/permissive/491294671/magnetron_control/hdl/mag_logic.v
data/verilator_xmls/ea7bc483-fc87-4ed6-a2c0-faaba521a0be.xml
module mag_logic (
    input wire startn , stopn , clearn, door_closed, timer_done, 
    output reg  s, r
);

	 always @(negedge startn, stopn, clearn, door_closed, timer_done) 
	 begin

        if(!clearn || !stopn || timer_done || !door_closed) 
            begin
                s = 0;  
                r = 1; 
            end

        else if(!startn && door_closed) 
            begin                       
                s = 1;    
                r = 0;  
            end

        else 
            begin
                s = 0; 
                r = 1; 
            end
    end

endmodule
module mag_logic (
    input wire startn , stopn , clearn, door_closed, timer_done, 
    output reg  s, r
);


	 always @(negedge startn, stopn, clearn, door_closed, timer_done) 
	 begin

        if(!clearn || !stopn || timer_done || !door_closed) 
            begin
                s = 0;  
                r = 1; 
            end

        else if(!startn && door_closed) 
            begin                       
                s = 1;    
                r = 0;  
            end

        else 
            begin
                s = 0; 
                r = 1; 
            end
    end

endmodule