data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v
1: b'%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:89: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_A_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_A: next_state = go ? S_LOAD_A_WAIT : S_LOAD_A;  \n                                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:89: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'S_LOAD_A\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_A: next_state = go ? S_LOAD_A_WAIT : S_LOAD_A;  \n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:90: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_A_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_A_WAIT: next_state = go ? S_LOAD_A_WAIT : S_LOAD_B;  \n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:90: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'S_LOAD_B\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_A_WAIT: next_state = go ? S_LOAD_A_WAIT : S_LOAD_B;  \n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:91: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_B_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_B: next_state = go ? S_LOAD_B_WAIT : S_LOAD_B;  \n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:91: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'S_LOAD_B\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_B: next_state = go ? S_LOAD_B_WAIT : S_LOAD_B;  \n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:92: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_B_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_B_WAIT: next_state = go ? S_LOAD_B_WAIT : S_LOAD_C;  \n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:92: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'S_LOAD_C\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_B_WAIT: next_state = go ? S_LOAD_B_WAIT : S_LOAD_C;  \n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:93: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_C_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_C: next_state = go ? S_LOAD_C_WAIT : S_LOAD_C;  \n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:93: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'S_LOAD_C\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_C: next_state = go ? S_LOAD_C_WAIT : S_LOAD_C;  \n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:94: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_C_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_C_WAIT: next_state = go ? S_LOAD_C_WAIT : S_LOAD_X;  \n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:94: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'S_LOAD_X\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_C_WAIT: next_state = go ? S_LOAD_C_WAIT : S_LOAD_X;  \n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:95: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_X_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_X: next_state = go ? S_LOAD_X_WAIT : S_LOAD_X;  \n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:95: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'S_LOAD_X\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_X: next_state = go ? S_LOAD_X_WAIT : S_LOAD_X;  \n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:96: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_X_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_X_WAIT: next_state = go ? S_LOAD_X_WAIT : S_CYCLE_0;  \n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:96: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'S_CYCLE_0\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_X_WAIT: next_state = go ? S_LOAD_X_WAIT : S_CYCLE_0;  \n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:97: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_CYCLE_1\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_CYCLE_0: next_state = S_CYCLE_1;\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:98: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_CYCLE_2\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_CYCLE_1: next_state = S_CYCLE_2;  \n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:99: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_CYCLE_3\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n      S_CYCLE_2: next_state = S_CYCLE_3;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:100: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_LOAD_A\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n      S_CYCLE_3: next_state = S_LOAD_A;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:101: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_LOAD_A\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n            default:     next_state = S_LOAD_A;\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_A\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_A_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_B\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_B_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_C\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_C_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_X\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_X_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_CYCLE_0\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_CYCLE_1\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_CYCLE_2\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_CYCLE_3\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:120: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_A\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n        case (current_state)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:120: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_B\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n        case (current_state)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:120: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_C\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n        case (current_state)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:120: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_X\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n        case (current_state)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:120: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_CYCLE_0\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n        case (current_state)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:120: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_CYCLE_1\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n        case (current_state)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:120: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_CYCLE_2\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n        case (current_state)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:120: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_CYCLE_3\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n        case (current_state)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:168: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_LOAD_A\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n            current_state <= S_LOAD_A;\n                          ^~\n%Error: Exiting due to 42 warning(s)\n'
module part2(Clock, Resetn, Go, DataIn, DataResult);
    input Clock;
    input Resetn;
    input Go;
    input [7:0] DataIn;
    output [7:0] DataResult;


    wire ld_a, ld_b, ld_c, ld_x, ld_r;
    wire ld_alu_out;
    wire [1:0]  alu_select_a, alu_select_b;
    wire alu_op;

    control C0(
        .clk(Clock),
        .resetn(Resetn),
        
        .go(Go),
        
        .ld_alu_out(ld_alu_out), 
        .ld_x(ld_x),
        .ld_a(ld_a),
        .ld_b(ld_b),
        .ld_c(ld_c), 
        .ld_r(ld_r), 
        
        .alu_select_a(alu_select_a),
        .alu_select_b(alu_select_b),
        .alu_op(alu_op)
    );

    datapath D0(
        .clk(Clock),
        .resetn(Resetn),

        .ld_alu_out(ld_alu_out), 
        .ld_x(ld_x),
        .ld_a(ld_a),
        .ld_b(ld_b),
        .ld_c(ld_c), 
        .ld_r(ld_r), 

        .alu_select_a(alu_select_a),
        .alu_select_b(alu_select_b),
        .alu_op(alu_op),

        .data_in(DataIn),
        .data_result(DataResult)
    );
                
 endmodule
module part2(Clock, Resetn, Go, DataIn, DataResult);

    input Clock;
    input Resetn;
    input Go;
    input [7:0] DataIn;
    output [7:0] DataResult;


    wire ld_a, ld_b, ld_c, ld_x, ld_r;
    wire ld_alu_out;
    wire [1:0]  alu_select_a, alu_select_b;
    wire alu_op;

    control C0(
        .clk(Clock),
        .resetn(Resetn),
        
        .go(Go),
        
        .ld_alu_out(ld_alu_out), 
        .ld_x(ld_x),
        .ld_a(ld_a),
        .ld_b(ld_b),
        .ld_c(ld_c), 
        .ld_r(ld_r), 
        
        .alu_select_a(alu_select_a),
        .alu_select_b(alu_select_b),
        .alu_op(alu_op)
    );

    datapath D0(
        .clk(Clock),
        .resetn(Resetn),

        .ld_alu_out(ld_alu_out), 
        .ld_x(ld_x),
        .ld_a(ld_a),
        .ld_b(ld_b),
        .ld_c(ld_c), 
        .ld_r(ld_r), 

        .alu_select_a(alu_select_a),
        .alu_select_b(alu_select_b),
        .alu_op(alu_op),

        .data_in(DataIn),
        .data_result(DataResult)
    );
                
 endmodule