data/full_repos/permissive/440575220/tb_miriscv_top.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/440575220/tb_miriscv_top.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #RST_WAIT;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/440575220/tb_miriscv_top.v:26: Unsupported: Ignoring delay on this delayed statement.\n     #200 $finish;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/440575220/tb_miriscv_top.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #HF_CYCLE;\n    ^\n%Error: data/full_repos/permissive/440575220/tb_miriscv_top.v:35: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("out.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/440575220/tb_miriscv_top.v:36: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars;\n      ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_miriscv_top();

  parameter     HF_CYCLE = 2.5;
  parameter     RST_WAIT = 10;
  parameter     RAM_SIZE = 512;


  reg clk;
  reg rst_n;

  miriscv_top #(
    .RAM_SIZE       ( RAM_SIZE           ),
    .RAM_INIT_FILE  ( "program_sort.dat" )
  ) dut (
    .clk_i    ( clk   ),
    .rst_n_i  ( rst_n )
  );

  initial begin
    clk   = 1'b0;
    rst_n = 1'b0;
    #RST_WAIT;
    rst_n = 1'b1;
     #200 $finish;

  end

  always begin
    #HF_CYCLE;
    clk = ~clk;
  end
   initial begin
      $dumpfile("out.vcd");
      $dumpvars;
   end

endmodule
module tb_miriscv_top();


  parameter     HF_CYCLE = 2.5;
  parameter     RST_WAIT = 10;
  parameter     RAM_SIZE = 512;


  reg clk;
  reg rst_n;

  miriscv_top #(
    .RAM_SIZE       ( RAM_SIZE           ),
    .RAM_INIT_FILE  ( "program_sort.dat" )
  ) dut (
    .clk_i    ( clk   ),
    .rst_n_i  ( rst_n )
  );

  initial begin
    clk   = 1'b0;
    rst_n = 1'b0;
    #RST_WAIT;
    rst_n = 1'b1;
     #200 $finish;

  end

  always begin
    #HF_CYCLE;
    clk = ~clk;
  end
   initial begin
      $dumpfile("out.vcd");
      $dumpvars;
   end

endmodule