data/full_repos/permissive/423924606/caravel/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/423924606/caravel/verilog/rtl/user_proj_example.v:90: syntax error, unexpected class\nDeepSAC_sleep DS(.class(wbs_ack_o), .clk(wb_clk_i), .rst(wb_rst_i), .x1(wbs_dat_i[15:0]), .x2(wbs_adr_i[15:0]));\n                  ^~~~~\n%Error: data/full_repos/permissive/423924606/caravel/verilog/rtl/user_proj_example.v:98: syntax error, unexpected class, expecting '['\noutput class,\n       ^~~~~\n%Error: data/full_repos/permissive/423924606/caravel/verilog/rtl/user_proj_example.v:202: syntax error, unexpected IDENTIFIER\ncomplement_rejfdb CP_L1_x1 (x1, x1c);\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423924606/caravel/verilog/rtl/user_proj_example.v:545: syntax error, unexpected begin\nbegin\n^~~~~\n%Error: data/full_repos/permissive/423924606/caravel/verilog/rtl/user_proj_example.v:553: syntax error, unexpected end\nend\n^~~\n%Error: data/full_repos/permissive/423924606/caravel/verilog/rtl/user_proj_example.v:752: syntax error, unexpected class, expecting '['\nmodule convert16_to_1(sig_out, class);\n                               ^~~~~\n%Error: Exiting due to 6 error(s)\n"
module user_proj_example #(
    parameter BITS = 32
) (
`ifdef USE_POWER_PINS




    inout vccd1,

    inout vssd1,

`endif


    input wb_clk_i,
    input wb_rst_i,




    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,



















    input   user_clock2,


    output [2:0] user_irq
);
    





 
DeepSAC_sleep DS(.class(wbs_ack_o), .clk(wb_clk_i), .rst(wb_rst_i), .x1(wbs_dat_i[15:0]), .x2(wbs_adr_i[15:0]));


endmodule
module user_proj_example #(
    parameter BITS = 32
) (
`ifdef USE_POWER_PINS




    inout vccd1,

    inout vssd1,

`endif


    input wb_clk_i,
    input wb_rst_i,




    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,



















    input   user_clock2,


    output [2:0] user_irq
);

    





 
DeepSAC_sleep DS(.class(wbs_ack_o), .clk(wb_clk_i), .rst(wb_rst_i), .x1(wbs_dat_i[15:0]), .x2(wbs_adr_i[15:0]));


endmodule