data/full_repos/permissive/494664634/AxiMM2STest/src/hdl/AxiMM2STest.v
data/verilator_xmls/f17048e6-79d5-470a-8c11-dfaf350e3188.xml
module AxiReadMaster(
  input         clock,
  input         reset,
  input         ctrl_start,
  output        ctrl_done,
  input  [31:0] ctrl_offset,
  input  [31:0] ctrl_length,
  input  [3:0]  ctrl_fkeep,
  input  [3:0]  ctrl_lkeep,
  output [31:0] m_axi_araddr,
  output        m_axi_arvalid,
  input         m_axi_arready,
  input  [31:0] m_axi_rdata,
  input         m_axi_rvalid,
  output        m_axi_rready,
  output [7:0]  m_axi_arlen,
  input         m_axi_rlast,
  output [31:0] m_tdata,
  output        m_tvalid,
  output [3:0]  m_tkeep
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
`endif
  wire  ar_transaction_cntr_clock;
  wire  ar_transaction_cntr_reset;
  wire  ar_transaction_cntr_load;
  wire  ar_transaction_cntr_decr;
  wire [23:0] ar_transaction_cntr_load_value;
  wire  ar_transaction_cntr_is_zero;
  wire  ar_to_r_transaction_cntr_clock;
  wire  ar_to_r_transaction_cntr_reset;
  wire  ar_to_r_transaction_cntr_incr;
  wire  ar_to_r_transaction_cntr_decr;
  wire  ar_to_r_transaction_cntr_is_zero;
  wire  r_transaction_cntr_clock;
  wire  r_transaction_cntr_reset;
  wire  r_transaction_cntr_load;
  wire  r_transaction_cntr_decr;
  wire [23:0] r_transaction_cntr_load_value;
  wire  r_transaction_cntr_is_zero;
  reg  arvalid_r;
  reg  ar_idle;
  reg [31:0] addr;
  reg [31:0] rxfer_cntr;
  wire  rxfer = m_axi_rready & m_axi_rvalid;
  wire  r_final_transaction = r_transaction_cntr_is_zero;
  wire [23:0] num_full_bursts = ctrl_length[31:8];
  wire  num_partial_bursts = ctrl_length[7:0] != 8'h0;
  reg  start;
  wire [23:0] _num_transactions_T_2 = num_full_bursts - 24'h1;
  reg [23:0] num_transactions;
  reg [7:0] final_burst_len;
  wire  single_transaction = num_transactions == 24'h0;
  wire  ar_final_transaction = ar_transaction_cntr_is_zero;
  wire  arxfer = arvalid_r & m_axi_arready;
  wire  stall_ar = ar_to_r_transaction_cntr_is_zero;
  wire  _arvalid_r_T_7 = m_axi_arready ? 1'h0 : arvalid_r;
  wire  ar_done = ar_final_transaction & arxfer;
  wire  _ar_idle_T_1 = start ? 1'h0 : ar_done | ar_idle;
  wire [31:0] _addr_T_1 = addr + 32'h400;
  wire  _m_tkeep_T = ctrl_length == 32'h1;
  wire [3:0] _m_tkeep_T_1 = ctrl_fkeep & ctrl_lkeep;
  wire  _m_tkeep_T_2 = rxfer_cntr == 32'h0;
  wire [31:0] _m_tkeep_T_4 = ctrl_length - 32'h1;
  wire  _m_tkeep_T_5 = rxfer_cntr == _m_tkeep_T_4;
  wire [3:0] _m_tkeep_T_6 = _m_tkeep_T_5 ? ctrl_lkeep : 4'hf;
  wire [3:0] _m_tkeep_T_7 = _m_tkeep_T_2 ? ctrl_fkeep : _m_tkeep_T_6;
  wire [31:0] _rxfer_cntr_T_1 = rxfer_cntr + 32'h1;
  UpDownLoadCounter ar_transaction_cntr (
    .clock(ar_transaction_cntr_clock),
    .reset(ar_transaction_cntr_reset),
    .load(ar_transaction_cntr_load),
    .decr(ar_transaction_cntr_decr),
    .load_value(ar_transaction_cntr_load_value),
    .is_zero(ar_transaction_cntr_is_zero)
  );
  UpDownLoadCounter_1 ar_to_r_transaction_cntr (
    .clock(ar_to_r_transaction_cntr_clock),
    .reset(ar_to_r_transaction_cntr_reset),
    .incr(ar_to_r_transaction_cntr_incr),
    .decr(ar_to_r_transaction_cntr_decr),
    .is_zero(ar_to_r_transaction_cntr_is_zero)
  );
  UpDownLoadCounter r_transaction_cntr (
    .clock(r_transaction_cntr_clock),
    .reset(r_transaction_cntr_reset),
    .load(r_transaction_cntr_load),
    .decr(r_transaction_cntr_decr),
    .load_value(r_transaction_cntr_load_value),
    .is_zero(r_transaction_cntr_is_zero)
  );
  assign ctrl_done = rxfer & m_axi_rlast & r_final_transaction;
  assign m_axi_araddr = addr;
  assign m_axi_arvalid = arvalid_r;
  assign m_axi_rready = 1'h1;
  assign m_axi_arlen = ar_final_transaction | start & single_transaction ? final_burst_len : 8'hff;
  assign m_tdata = m_axi_rdata;
  assign m_tvalid = m_axi_rvalid;
  assign m_tkeep = _m_tkeep_T ? _m_tkeep_T_1 : _m_tkeep_T_7;
  assign ar_transaction_cntr_clock = clock;
  assign ar_transaction_cntr_reset = reset;
  assign ar_transaction_cntr_load = start;
  assign ar_transaction_cntr_decr = arvalid_r & m_axi_arready;
  assign ar_transaction_cntr_load_value = num_transactions;
  assign ar_to_r_transaction_cntr_clock = clock;
  assign ar_to_r_transaction_cntr_reset = reset;
  assign ar_to_r_transaction_cntr_incr = rxfer & m_axi_rlast;
  assign ar_to_r_transaction_cntr_decr = arvalid_r & m_axi_arready;
  assign r_transaction_cntr_clock = clock;
  assign r_transaction_cntr_reset = reset;
  assign r_transaction_cntr_load = start;
  assign r_transaction_cntr_decr = rxfer & m_axi_rlast;
  assign r_transaction_cntr_load_value = num_transactions;
  always @(posedge clock) begin
    if (reset) begin
      arvalid_r <= 1'h0;
    end else begin
      arvalid_r <= ~ar_idle & ~stall_ar & ~arvalid_r | _arvalid_r_T_7;
    end
    ar_idle <= reset | _ar_idle_T_1;
    if (reset) begin
      addr <= 32'h0;
    end else if (ctrl_start) begin
      addr <= ctrl_offset;
    end else if (arxfer) begin
      addr <= _addr_T_1;
    end
    if (reset) begin
      rxfer_cntr <= 32'h0;
    end else if (start) begin
      rxfer_cntr <= 32'h0;
    end else if (rxfer) begin
      rxfer_cntr <= _rxfer_cntr_T_1;
    end
    if (reset) begin
      start <= 1'h0;
    end else begin
      start <= ctrl_start;
    end
    if (~num_partial_bursts) begin
      num_transactions <= _num_transactions_T_2;
    end else begin
      num_transactions <= num_full_bursts;
    end
    final_burst_len <= ctrl_length[7:0] - 8'h1;
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  arvalid_r = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  ar_idle = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  addr = _RAND_2[31:0];
  _RAND_3 = {1{`RANDOM}};
  rxfer_cntr = _RAND_3[31:0];
  _RAND_4 = {1{`RANDOM}};
  start = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  num_transactions = _RAND_5[23:0];
  _RAND_6 = {1{`RANDOM}};
  final_burst_len = _RAND_6[7:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module AxiReadMaster(
  input         clock,
  input         reset,
  input         ctrl_start,
  output        ctrl_done,
  input  [31:0] ctrl_offset,
  input  [31:0] ctrl_length,
  input  [3:0]  ctrl_fkeep,
  input  [3:0]  ctrl_lkeep,
  output [31:0] m_axi_araddr,
  output        m_axi_arvalid,
  input         m_axi_arready,
  input  [31:0] m_axi_rdata,
  input         m_axi_rvalid,
  output        m_axi_rready,
  output [7:0]  m_axi_arlen,
  input         m_axi_rlast,
  output [31:0] m_tdata,
  output        m_tvalid,
  output [3:0]  m_tkeep
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
`endif
  wire  ar_transaction_cntr_clock;
  wire  ar_transaction_cntr_reset;
  wire  ar_transaction_cntr_load;
  wire  ar_transaction_cntr_decr;
  wire [23:0] ar_transaction_cntr_load_value;
  wire  ar_transaction_cntr_is_zero;
  wire  ar_to_r_transaction_cntr_clock;
  wire  ar_to_r_transaction_cntr_reset;
  wire  ar_to_r_transaction_cntr_incr;
  wire  ar_to_r_transaction_cntr_decr;
  wire  ar_to_r_transaction_cntr_is_zero;
  wire  r_transaction_cntr_clock;
  wire  r_transaction_cntr_reset;
  wire  r_transaction_cntr_load;
  wire  r_transaction_cntr_decr;
  wire [23:0] r_transaction_cntr_load_value;
  wire  r_transaction_cntr_is_zero;
  reg  arvalid_r;
  reg  ar_idle;
  reg [31:0] addr;
  reg [31:0] rxfer_cntr;
  wire  rxfer = m_axi_rready & m_axi_rvalid;
  wire  r_final_transaction = r_transaction_cntr_is_zero;
  wire [23:0] num_full_bursts = ctrl_length[31:8];
  wire  num_partial_bursts = ctrl_length[7:0] != 8'h0;
  reg  start;
  wire [23:0] _num_transactions_T_2 = num_full_bursts - 24'h1;
  reg [23:0] num_transactions;
  reg [7:0] final_burst_len;
  wire  single_transaction = num_transactions == 24'h0;
  wire  ar_final_transaction = ar_transaction_cntr_is_zero;
  wire  arxfer = arvalid_r & m_axi_arready;
  wire  stall_ar = ar_to_r_transaction_cntr_is_zero;
  wire  _arvalid_r_T_7 = m_axi_arready ? 1'h0 : arvalid_r;
  wire  ar_done = ar_final_transaction & arxfer;
  wire  _ar_idle_T_1 = start ? 1'h0 : ar_done | ar_idle;
  wire [31:0] _addr_T_1 = addr + 32'h400;
  wire  _m_tkeep_T = ctrl_length == 32'h1;
  wire [3:0] _m_tkeep_T_1 = ctrl_fkeep & ctrl_lkeep;
  wire  _m_tkeep_T_2 = rxfer_cntr == 32'h0;
  wire [31:0] _m_tkeep_T_4 = ctrl_length - 32'h1;
  wire  _m_tkeep_T_5 = rxfer_cntr == _m_tkeep_T_4;
  wire [3:0] _m_tkeep_T_6 = _m_tkeep_T_5 ? ctrl_lkeep : 4'hf;
  wire [3:0] _m_tkeep_T_7 = _m_tkeep_T_2 ? ctrl_fkeep : _m_tkeep_T_6;
  wire [31:0] _rxfer_cntr_T_1 = rxfer_cntr + 32'h1;
  UpDownLoadCounter ar_transaction_cntr (
    .clock(ar_transaction_cntr_clock),
    .reset(ar_transaction_cntr_reset),
    .load(ar_transaction_cntr_load),
    .decr(ar_transaction_cntr_decr),
    .load_value(ar_transaction_cntr_load_value),
    .is_zero(ar_transaction_cntr_is_zero)
  );
  UpDownLoadCounter_1 ar_to_r_transaction_cntr (
    .clock(ar_to_r_transaction_cntr_clock),
    .reset(ar_to_r_transaction_cntr_reset),
    .incr(ar_to_r_transaction_cntr_incr),
    .decr(ar_to_r_transaction_cntr_decr),
    .is_zero(ar_to_r_transaction_cntr_is_zero)
  );
  UpDownLoadCounter r_transaction_cntr (
    .clock(r_transaction_cntr_clock),
    .reset(r_transaction_cntr_reset),
    .load(r_transaction_cntr_load),
    .decr(r_transaction_cntr_decr),
    .load_value(r_transaction_cntr_load_value),
    .is_zero(r_transaction_cntr_is_zero)
  );
  assign ctrl_done = rxfer & m_axi_rlast & r_final_transaction;
  assign m_axi_araddr = addr;
  assign m_axi_arvalid = arvalid_r;
  assign m_axi_rready = 1'h1;
  assign m_axi_arlen = ar_final_transaction | start & single_transaction ? final_burst_len : 8'hff;
  assign m_tdata = m_axi_rdata;
  assign m_tvalid = m_axi_rvalid;
  assign m_tkeep = _m_tkeep_T ? _m_tkeep_T_1 : _m_tkeep_T_7;
  assign ar_transaction_cntr_clock = clock;
  assign ar_transaction_cntr_reset = reset;
  assign ar_transaction_cntr_load = start;
  assign ar_transaction_cntr_decr = arvalid_r & m_axi_arready;
  assign ar_transaction_cntr_load_value = num_transactions;
  assign ar_to_r_transaction_cntr_clock = clock;
  assign ar_to_r_transaction_cntr_reset = reset;
  assign ar_to_r_transaction_cntr_incr = rxfer & m_axi_rlast;
  assign ar_to_r_transaction_cntr_decr = arvalid_r & m_axi_arready;
  assign r_transaction_cntr_clock = clock;
  assign r_transaction_cntr_reset = reset;
  assign r_transaction_cntr_load = start;
  assign r_transaction_cntr_decr = rxfer & m_axi_rlast;
  assign r_transaction_cntr_load_value = num_transactions;
  always @(posedge clock) begin
    if (reset) begin
      arvalid_r <= 1'h0;
    end else begin
      arvalid_r <= ~ar_idle & ~stall_ar & ~arvalid_r | _arvalid_r_T_7;
    end
    ar_idle <= reset | _ar_idle_T_1;
    if (reset) begin
      addr <= 32'h0;
    end else if (ctrl_start) begin
      addr <= ctrl_offset;
    end else if (arxfer) begin
      addr <= _addr_T_1;
    end
    if (reset) begin
      rxfer_cntr <= 32'h0;
    end else if (start) begin
      rxfer_cntr <= 32'h0;
    end else if (rxfer) begin
      rxfer_cntr <= _rxfer_cntr_T_1;
    end
    if (reset) begin
      start <= 1'h0;
    end else begin
      start <= ctrl_start;
    end
    if (~num_partial_bursts) begin
      num_transactions <= _num_transactions_T_2;
    end else begin
      num_transactions <= num_full_bursts;
    end
    final_burst_len <= ctrl_length[7:0] - 8'h1;
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  arvalid_r = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  ar_idle = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  addr = _RAND_2[31:0];
  _RAND_3 = {1{`RANDOM}};
  rxfer_cntr = _RAND_3[31:0];
  _RAND_4 = {1{`RANDOM}};
  start = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  num_transactions = _RAND_5[23:0];
  _RAND_6 = {1{`RANDOM}};
  final_burst_len = _RAND_6[7:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule