data/full_repos/permissive/477243413/rtl/dffen_2seg.v
data/verilator_xmls/765e1d61-5468-41ac-936b-43fd6ffd0c12.xml
module dffen_2seg
(
    input wire clk, reset,
    input wire en,
    input wire d,
    output reg q
);

reg data, nextdata;


always @(posedge clk , posedge reset)
if (reset)
    data <= 1'b0;
else
    data <= nextdata;

always @*
if(en)
    nextdata = d;
else
    nextdata = data;

always @*
    q = data;

endmodule
module dffen_2seg
(
    input wire clk, reset,
    input wire en,
    input wire d,
    output reg q
);


reg data, nextdata;


always @(posedge clk , posedge reset)
if (reset)
    data <= 1'b0;
else
    data <= nextdata;

always @*
if(en)
    nextdata = d;
else
    nextdata = data;

always @*
    q = data;

endmodule