data/full_repos/permissive/454263844/Project_files/DATA_PATH_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/454263844/Project_files/DATA_PATH_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n   always #5 i_clk = ~i_clk ;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/454263844/Project_files/DATA_PATH_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n       #15 reset = 1\'b1 ;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/454263844/Project_files/DATA_PATH_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n       #3 reset = 1\'b0 ;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/454263844/Project_files/DATA_PATH_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #4 a_in = 8\'b00001000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/454263844/Project_files/DATA_PATH_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n       #1 b_in = 8\'b00001000 ;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/454263844/Project_files/DATA_PATH_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n       #120  reset = 1\'b1 ;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/454263844/Project_files/DATA_PATH_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n       #40 reset = 1\'b0 ;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/454263844/Project_files/DATA_PATH_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n       #1000 $stop ;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/454263844/Project_files/DATA_PATH_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n       #60 a_in = 8\'b00011000;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/454263844/Project_files/DATA_PATH_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n       #20 b_in = 8\'b00001100 ;\n       ^\n%Error: data/full_repos/permissive/454263844/Project_files/DATA_PATH_tb.v:13: Cannot find file containing module: \'DATA_PATH\'\nDATA_PATH DUT ( i_clk , reset , sum , a_in , b_in ,  p_STATE, Count_out , B_o , A_o);\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/454263844/Project_files,data/full_repos/permissive/454263844/DATA_PATH\n             data/full_repos/permissive/454263844/Project_files,data/full_repos/permissive/454263844/DATA_PATH.v\n             data/full_repos/permissive/454263844/Project_files,data/full_repos/permissive/454263844/DATA_PATH.sv\n             DATA_PATH\n             DATA_PATH.v\n             DATA_PATH.sv\n             obj_dir/DATA_PATH\n             obj_dir/DATA_PATH.v\n             obj_dir/DATA_PATH.sv\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module DATA_PATH_tb();
parameter D_WIDTH  = 8;
parameter D_WID_4 = 4 ;
reg i_clk ;
reg reset ;
reg [D_WIDTH-1:0] a_in  , b_in ;
wire [D_WIDTH-1:0] sum ;
wire p_STATE ;
wire [D_WID_4-1:0] Count_out ;
wire [D_WIDTH-1:0] B_o ;
wire [D_WIDTH-1:0] A_o ;
DATA_PATH DUT ( i_clk , reset , sum , a_in , b_in ,  p_STATE, Count_out , B_o , A_o);



initial 
 begin
  i_clk = 1'b0 ;
  reset = 1'b0 ;
   end
   
   
   always #5 i_clk = ~i_clk ;
   
   
  initial
    begin
       #15 reset = 1'b1 ;
       #3 reset = 1'b0 ;
    
        end
        
        initial
          begin
        #4 a_in = 8'b00001000;
       #1 b_in = 8'b00001000 ;
       
       
       #120  reset = 1'b1 ;
       #40 reset = 1'b0 ;
       
       #1000 $stop ;
       end
       
       initial
          begin
       #60 a_in = 8'b00011000;
       #20 b_in = 8'b00001100 ;
       end
endmodule
module DATA_PATH_tb();

parameter D_WIDTH  = 8;
parameter D_WID_4 = 4 ;
reg i_clk ;
reg reset ;
reg [D_WIDTH-1:0] a_in  , b_in ;
wire [D_WIDTH-1:0] sum ;
wire p_STATE ;
wire [D_WID_4-1:0] Count_out ;
wire [D_WIDTH-1:0] B_o ;
wire [D_WIDTH-1:0] A_o ;
DATA_PATH DUT ( i_clk , reset , sum , a_in , b_in ,  p_STATE, Count_out , B_o , A_o);



initial 
 begin
  i_clk = 1'b0 ;
  reset = 1'b0 ;
   end
   
   
   always #5 i_clk = ~i_clk ;
   
   
  initial
    begin
       #15 reset = 1'b1 ;
       #3 reset = 1'b0 ;
    
        end
        
        initial
          begin
        #4 a_in = 8'b00001000;
       #1 b_in = 8'b00001000 ;
       
       
       #120  reset = 1'b1 ;
       #40 reset = 1'b0 ;
       
       #1000 $stop ;
       end
       
       initial
          begin
       #60 a_in = 8'b00011000;
       #20 b_in = 8'b00001100 ;
       end
endmodule