data/full_repos/permissive/447668373/SIPO/sipo.v
1: b'%Warning-WIDTH: data/full_repos/permissive/447668373/SIPO/sipo.v:8: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                  : ... In instance sipo.dd\n            q <= 4\'b0000;\n              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module sipo(d, clk, reset, q);
    input d, clk, reset;
    output [3:0]q;
    dff aa(d, clk, reset, q[3]);
    dff bb(q[3], clk, reset, q[2]);
    dff cc(q[2], clk, reset, q[1]);
    dff dd(q[1], clk, reset, q[0]);
endmodule
module sipo(d, clk, reset, q);

    input d, clk, reset;
    output [3:0]q;
    dff aa(d, clk, reset, q[3]);
    dff bb(q[3], clk, reset, q[2]);
    dff cc(q[2], clk, reset, q[1]);
    dff dd(q[1], clk, reset, q[0]);
endmodule