data/full_repos/permissive/458737381/src/verilog-parser/tests/adder_hier.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/adder_hier.v:8: Cannot find include file: addbit.v\n`include "addbit.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/addbit.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/addbit.v.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/addbit.v.sv\n             addbit.v\n             addbit.v.v\n             addbit.v.sv\n             obj_dir/addbit.v\n             obj_dir/addbit.v.v\n             obj_dir/addbit.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/adder_hier.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #10 r1 = 10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/adder_hier.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #10 r2 = 2;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/adder_hier.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #10 ci = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/adder_hier.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #10 $display("+--------------------------------------------------------+");\n  ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/adder_hier.v:73: Unsupported or unknown PLI call: $monitor\n  $monitor("|  %h   |  %h   |  %h   |    %h    |   %h   |   %h    |   %h    |",\n  ^~~~~~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n'
module adder_hier (
result        ,
carry         ,
r1            ,
r2            ,
ci
);


input    [3:0]   r1         ;
input    [3:0]   r2         ;
input            ci         ;


output   [3:0]  result      ;
output          carry       ;


wire     [3:0]    r1        ;
wire     [3:0]    r2        ;
wire              ci        ;
wire     [3:0]    result    ;
wire              carry     ;


wire              c1        ;
wire              c2        ;
wire              c3        ;


addbit u0 (r1[0],r2[0],ci,result[0],c1);
addbit u1 (r1[1],r2[1],c1,result[1],c2);
addbit u2 (r1[2],r2[2],c2,result[2],c3);
addbit u3 (r1[3],r2[3],c3,result[3],carry);

endmodule
module adder_hier (
result        ,
carry         ,
r1            ,
r2            ,
ci
);



input    [3:0]   r1         ;
input    [3:0]   r2         ;
input            ci         ;


output   [3:0]  result      ;
output          carry       ;


wire     [3:0]    r1        ;
wire     [3:0]    r2        ;
wire              ci        ;
wire     [3:0]    result    ;
wire              carry     ;


wire              c1        ;
wire              c2        ;
wire              c3        ;


addbit u0 (r1[0],r2[0],ci,result[0],c1);
addbit u1 (r1[1],r2[1],c1,result[1],c2);
addbit u2 (r1[2],r2[2],c2,result[2],c3);
addbit u3 (r1[3],r2[3],c3,result[3],carry);

endmodule