data/full_repos/permissive/520487363/EX1 - Clock and Periodic Signal Generation/PashaBarahimi/FPGA Design/RingOscillator/ringOscillator.v
1: b'%Error: Invalid Option: -\n'
module ringOscillator #(parameter InverterCount = 5, Delay = 1.9) (output w);
    reg [0:InverterCount-1] inverters = 0;
    integer i;

    assign w = inverters[0];


    initial begin
        while (1)
            for (i = 1; i <= InverterCount; i = i + 1) begin
                #Delay inverters[i % InverterCount] = ~inverters[i - 1];
            end
    end
endmodule
module ringOscillator #(parameter InverterCount = 5, Delay = 1.9) (output w);

    reg [0:InverterCount-1] inverters = 0;
    integer i;

    assign w = inverters[0];


    initial begin
        while (1)
            for (i = 1; i <= InverterCount; i = i + 1) begin
                #Delay inverters[i % InverterCount] = ~inverters[i - 1];
            end
    end
endmodule