data/full_repos/permissive/42581625/PersonalComputer/Memory.v
1: b"%Error: data/full_repos/permissive/42581625/PersonalComputer/Memory.v:48: Cannot find file containing module: 'BankA'\nBankA banka (\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/42581625/PersonalComputer,data/full_repos/permissive/42581625/BankA\n             data/full_repos/permissive/42581625/PersonalComputer,data/full_repos/permissive/42581625/BankA.v\n             data/full_repos/permissive/42581625/PersonalComputer,data/full_repos/permissive/42581625/BankA.sv\n             BankA\n             BankA.v\n             BankA.sv\n             obj_dir/BankA\n             obj_dir/BankA.v\n             obj_dir/BankA.sv\n%Error: data/full_repos/permissive/42581625/PersonalComputer/Memory.v:60: Cannot find file containing module: 'BankB'\nBankB bankb (\n^~~~~\n%Error: Exiting due to 2 error(s)\n"
module Memory(
input clk,
input[14:0] adrA,
input[14:0] adrB,
input we,
input[31:0] data,
input lh,
input sh,
output[31:0] outA,
output[15:0] outB
    );
wire weA,weB;
wire[13:0] addrAA,addrAB,addrBA,addrBB;
wire[15:0] doutAA,doutAB,doutBA,doutBB;
wire[15:0] dinA,dinB;
assign weA = we & ( ~sh | ~adrA[0] );
assign weB = we & ( ~sh | adrA[0] );
assign addrAA = adrA[0] ? (adrA[14:1]+1) : adrA[14:1];
assign addrBA = adrA[14:1];
assign dinA = sh ? data[15:0] : (adrA[0]? data[15:0] : data[31:16]);
assign dinB = sh ? data[15:0] : (adrA[0]? data[31:16] : data[15:0]);
assign outA = lh ? (adrA[0]? { {16{doutBA[15]}} ,doutBA} : { {16{doutAA[15]}}, doutAA}) : 
                   (adrA[0]? {doutBA,doutAA} : {doutAA,doutBA});

assign addrAB = adrB[14:1];
assign addrBB = adrB[14:1];
assign outB = adrB[0]? doutBB : doutAB;
BankA banka (
	.clka(clk),
	.wea(weA),
	.addra(addrAA),
	.dina(dinA),
	.douta(doutAA),
	.clkb(clk),
	.web(1'b0),
	.addrb(addrAB),
	.dinb(16'b0),
	.doutb(doutAB));
	
BankB bankb (
	.clka(clk),
	.wea(weB),
	.addra(addrBA),
	.dina(dinB),
	.douta(doutBA),
	.clkb(clk),
	.web(1'b0),
	.addrb(addrBB),
	.dinb(16'b0),
	.doutb(doutBB));
endmodule
module Memory(
input clk,
input[14:0] adrA,
input[14:0] adrB,
input we,
input[31:0] data,
input lh,
input sh,
output[31:0] outA,
output[15:0] outB
    );

wire weA,weB;
wire[13:0] addrAA,addrAB,addrBA,addrBB;
wire[15:0] doutAA,doutAB,doutBA,doutBB;
wire[15:0] dinA,dinB;
assign weA = we & ( ~sh | ~adrA[0] );
assign weB = we & ( ~sh | adrA[0] );
assign addrAA = adrA[0] ? (adrA[14:1]+1) : adrA[14:1];
assign addrBA = adrA[14:1];
assign dinA = sh ? data[15:0] : (adrA[0]? data[15:0] : data[31:16]);
assign dinB = sh ? data[15:0] : (adrA[0]? data[31:16] : data[15:0]);
assign outA = lh ? (adrA[0]? { {16{doutBA[15]}} ,doutBA} : { {16{doutAA[15]}}, doutAA}) : 
                   (adrA[0]? {doutBA,doutAA} : {doutAA,doutBA});

assign addrAB = adrB[14:1];
assign addrBB = adrB[14:1];
assign outB = adrB[0]? doutBB : doutAB;
BankA banka (
	.clka(clk),
	.wea(weA),
	.addra(addrAA),
	.dina(dinA),
	.douta(doutAA),
	.clkb(clk),
	.web(1'b0),
	.addrb(addrAB),
	.dinb(16'b0),
	.doutb(doutAB));
	
BankB bankb (
	.clka(clk),
	.wea(weB),
	.addra(addrBA),
	.dina(dinB),
	.douta(doutBA),
	.clkb(clk),
	.web(1'b0),
	.addrb(addrBB),
	.dinb(16'b0),
	.doutb(doutBB));
endmodule