data/full_repos/permissive/504677412/src/mem_rd_ctrl.v
1: b'%Error: data/full_repos/permissive/504677412/src/mem_rd_ctrl.v:3: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/504677412/src,data/full_repos/permissive/504677412/defines.v\n             data/full_repos/permissive/504677412/src,data/full_repos/permissive/504677412/defines.v.v\n             data/full_repos/permissive/504677412/src,data/full_repos/permissive/504677412/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/504677412/src/mem_rd_ctrl.v:45: Define or directive not defined: \'`FL_WIDTH\'\n  parameter FNUM_WIDTH             = $clog2(`FL_WIDTH);\n                                            ^~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/mem_rd_ctrl.v:45: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  parameter FNUM_WIDTH             = $clog2(`FL_WIDTH);\n                                                     ^\n%Error: data/full_repos/permissive/504677412/src/mem_rd_ctrl.v:61: Define or directive not defined: \'`FL_WIDTH\'\n  output wire [`FL_WIDTH-1:0]       r_frm_len;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/mem_rd_ctrl.v:122: Define or directive not defined: \'`FL_WIDTH\'\n  wire [`FL_WIDTH-1:0]              w_frm_len;\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/mem_rd_ctrl.v:123: Define or directive not defined: \'`FL_WIDTH\'\n  wire [`FL_WIDTH-1:0]              prev_r_frm_len;\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/mem_rd_ctrl.v:366: Define or directive not defined: \'`MEM_RD_BL\'\n      r_maddr <= r_maddr + (`MEM_RD_BL<<2);  \n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/mem_rd_ctrl.v:366: syntax error, unexpected <<, expecting TYPE-IDENTIFIER\n      r_maddr <= r_maddr + (`MEM_RD_BL<<2);  \n                                      ^~\n%Error: data/full_repos/permissive/504677412/src/mem_rd_ctrl.v:403: Define or directive not defined: \'`FL_WIDTH\'\n      rd_word_cntr <= {`FL_WIDTH{1\'b0}};\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/mem_rd_ctrl.v:406: Define or directive not defined: \'`FL_WIDTH\'\n        rd_word_cntr <= {`FL_WIDTH{1\'b0}};\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/mem_rd_ctrl.v:429: Define or directive not defined: \'`TIED_TO_VCC\'\n        .oce                  (`TIED_TO_VCC),\n                               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/mem_rd_ctrl.v:430: Define or directive not defined: \'`TIED_TO_VCC\'\n        .ceb                  (`TIED_TO_VCC),\n                               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/mem_rd_ctrl.v:439: Define or directive not defined: \'`FL_WIDTH\'\n  assign r_frm_len   = fcq_rdata[2+:`FL_WIDTH];\n                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/mem_rd_ctrl.v:439: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  assign r_frm_len   = fcq_rdata[2+:`FL_WIDTH];\n                                             ^\n%Error: data/full_repos/permissive/504677412/src/mem_rd_ctrl.v:444: Define or directive not defined: \'`FL_WIDTH\'\n  assign w_frm_len    = fcq_wdata[2+:`FL_WIDTH];\n                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/mem_rd_ctrl.v:444: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  assign w_frm_len    = fcq_wdata[2+:`FL_WIDTH];\n                                              ^\n%Error: data/full_repos/permissive/504677412/src/mem_rd_ctrl.v:454: Define or directive not defined: \'`TIED_TO_VCC\'\n    .oce                  (`TIED_TO_VCC),\n                           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/mem_rd_ctrl.v:455: Define or directive not defined: \'`TIED_TO_VCC\'\n    .ceb                  (`TIED_TO_VCC),\n                           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/mem_rd_ctrl.v:461: Define or directive not defined: \'`FL_WIDTH\'\n  assign prev_r_frm_len = fl_fcq_rdata[0+:`FL_WIDTH];\n                                          ^~~~~~~~~\n%Error: data/full_repos/permissive/504677412/src/mem_rd_ctrl.v:461: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  assign prev_r_frm_len = fl_fcq_rdata[0+:`FL_WIDTH];\n                                                   ^\n%Error: Exiting due to 20 error(s)\n'
module mem_rd_ctrl (
  rst,
  clk,
  rpt_rate_ctrl,

  fcq_wr_addr,
  fcq_wr_en,
  fcq_wdata,
  fcq_rd_en,
  buf_full,
  disc_this_buf,
  disc_buf_ack,
  send_wr_to_tob,
  capturing_frm,
  r_zoom_ctrl,
  r_frm_len,

  bcq_wr_en,
  bcq_wdata,
  bcq_tob_pulse,
  buf_size,

  mem_rd_cmd,
  mem_rd_vld,
  rpl_2x_done,
  buf_avail,
  frm_avail,
  r_maddr_d1,
  rd_video_buf,
  rd_frm_buf,
  rd_audio_buf,
  rd_sob,
  rd_eob,
  rd_sof,
  rd_eof,
  dbg_mrb_err
);
  

  parameter CAPT_CNTRL_SEL         = 1;
  parameter ADDR_WIDTH             = 25;
  parameter FNUM_WIDTH             = $clog2(`FL_WIDTH);
  

  input  wire                       rst;
  input  wire                       clk;
  input  wire [4:0]                 rpt_rate_ctrl;

  input  wire [FNUM_WIDTH-1:0]      fcq_wr_addr;
  input  wire                       fcq_wr_en;
  input  wire [71:0]                fcq_wdata;
  input  wire                       fcq_rd_en;
  input  wire                       buf_full;
  input  wire                       disc_this_buf;
  input  wire                       send_wr_to_tob;
  input  wire                       capturing_frm;
  output wire [3:0]                 r_zoom_ctrl;
  output wire [`FL_WIDTH-1:0]       r_frm_len;

  input  wire                       bcq_wr_en;
  input  wire [71:0]                bcq_wdata;
  output wire                       bcq_tob_pulse;
  output wire [31:0]                buf_size;

  input  wire                       mem_rd_cmd;
  input  wire                       mem_rd_vld;
  output reg                        rpl_2x_done;
  output wire                       disc_buf_ack;
  output reg                        buf_avail;
  output reg                        frm_avail;
  output reg  [ADDR_WIDTH-1:0]      r_maddr_d1;
  output reg                        rd_video_buf;
  output reg                        rd_frm_buf;
  output reg                        rd_audio_buf;
  output wire                       rd_sob;
  output wire                       rd_eob;
  output wire                       rd_sof;
  output wire                       rd_eof;
  output reg                        dbg_mrb_err;

  localparam  IDLE                = 14'b00_0000_0000_0001;
  localparam  FCQ_AVAIL           = 14'b00_0000_0000_0010;
  localparam  LOAD_TOP            = 14'b00_0000_0000_0100;
  localparam  LOAD_HEAD           = 14'b00_0000_0000_1000;
  localparam  FRM_RPT_WAIT        = 14'b00_0000_0001_0000;
  localparam  END_OF_BUF          = 14'b00_0000_0010_0000;
  localparam  BCQ_AVAIL           = 14'b00_0000_0100_0000;
  localparam  LOAD_SOF            = 14'b00_0000_1000_0000;
  localparam  INC_R_FNUM          = 14'b00_0001_0000_0000;
  localparam  RD_BCQ              = 14'b00_0010_0000_0000;
  localparam  RD_FCQ              = 14'b00_0100_0000_0000;
  localparam  DISCARD_BUF         = 14'b00_1000_0000_0000;
  localparam  SET_LIVE_MODE       = 14'b01_0000_0000_0000;
  localparam  SET_REPLAY_MODE     = 14'b10_0000_0000_0000;
  

  reg  [13:0]                       c_state;
  reg  [13:0]                       n_state;
  reg  [FNUM_WIDTH-1:0]             r_fnum;
  wire [71:0]                       fcq_rdata;
  wire [ADDR_WIDTH-1:0]             r_sof_maddr;
  wire                              r_tail_frm;
  wire                              r_bot_frm;
  wire                              bcq_full;
  wire                              bcq_empty;
  reg                               bcq_empty_d1;
  wire                              bcq_empty_fe;
  reg  [ADDR_WIDTH-1:0]             r_maddr;
  reg  [ADDR_WIDTH-1:0]             rd_word_cntr;
  wire [71:0]                       bcq_rdata;
  wire [FNUM_WIDTH-1:0]             w_top_fnum;
  wire [FNUM_WIDTH-1:0]             r_head_fnum;
  wire [FNUM_WIDTH-1:0]             r_top_fnum;
  wire [9:0]                        used_buf_cnt;
  wire [35:0]                       fl_fcq_wdata;
  wire [35:0]                       fl_fcq_rdata;
  wire [71:0]                       bcq_wdata_i;
  reg  [31:0]                       buf_size_cntr;
  wire [`FL_WIDTH-1:0]              w_frm_len;
  wire [`FL_WIDTH-1:0]              prev_r_frm_len;
  wire                              frm_rpt_done;
  reg  [4:0]                        frm_rpt_cntr;
  reg                               buf_rpt_done_i;
  wire                              buf_rpt_done;
  wire                              bcq_rd_req;
  wire                              video_buf_i;
  wire                              frm_buf_i;
  wire                              audio_buf_i;
  wire                              bcq_wr_en_i;
  wire                              is_video_buf;
  wire                              w_tail_frm;
  reg                               in_replay_mode;
  reg                               capturing_frm_d1;
  wire                              capturing_frm_re;
  wire [1:0]                        bcq_full_i;
  wire [1:0]                        bcq_empty_i;
   
  genvar i;





  always @(posedge clk) begin
    if (rst) begin
      c_state <= IDLE;
    end else begin
      c_state <= n_state;
    end
  end
  

  always @(*) begin
    case (c_state)
      IDLE:
if (!CAPT_CNTRL_SEL && frm_avail) begin
          n_state = SET_LIVE_MODE;
        end else begin
          n_state = IDLE;
        end

      SET_LIVE_MODE:
        n_state = RD_FCQ;
        
      SET_REPLAY_MODE:

          n_state = RD_BCQ;



        
      RD_BCQ:
        n_state = BCQ_AVAIL;
        
      BCQ_AVAIL:
        if (rd_eof) begin
		  n_state = RD_FCQ;
		end else begin
          n_state = BCQ_AVAIL;
        end
        
      RD_FCQ:
        n_state = FCQ_AVAIL;
        
      FCQ_AVAIL:
        n_state = FRM_RPT_WAIT;
        
      FRM_RPT_WAIT:
        if (!CAPT_CNTRL_SEL && disc_this_buf && frm_avail) begin
          n_state = DISCARD_BUF;
        end else if (CAPT_CNTRL_SEL && disc_this_buf) begin
          n_state = DISCARD_BUF;


        end else if (frm_rpt_done) begin
          if (CAPT_CNTRL_SEL && r_tail_frm) begin
            n_state = END_OF_BUF;
          end else if (!CAPT_CNTRL_SEL && ((in_replay_mode && r_tail_frm) || (!in_replay_mode && !bcq_empty))) begin
            n_state = LOAD_HEAD;
          end else if (r_bot_frm) begin
            n_state = LOAD_TOP;
          end else begin
            n_state = INC_R_FNUM;
          end
        end else begin
          n_state = LOAD_SOF;
        end
        
      LOAD_TOP:
        if (rd_eof) begin
          n_state = RD_FCQ;
        end else begin
          n_state = LOAD_TOP;
        end
        
      LOAD_HEAD:
        if (rd_eof) begin
          n_state = RD_FCQ;
        end else begin
          n_state = LOAD_HEAD;
        end

      LOAD_SOF:
        if (rd_eof) begin
          n_state = RD_FCQ;
        end else begin
          n_state = LOAD_SOF;
        end

      INC_R_FNUM:
        if (rd_eof) begin
          n_state = RD_FCQ;
        end else begin
          n_state = INC_R_FNUM;
        end
        
      END_OF_BUF:
        if (disc_this_buf) begin
          n_state = DISCARD_BUF;
        end else begin
          n_state = END_OF_BUF;
        end
        
      DISCARD_BUF:
        if (CAPT_CNTRL_SEL) begin
          n_state = IDLE;
        end else begin
          if (rd_eof) begin
            n_state = IDLE;
          end else begin
            n_state = DISCARD_BUF;
          end
        end
        
      default: n_state = IDLE;
    endcase
  end
  

  always @(posedge clk) begin
    if (rst) begin
      r_fnum <= {FNUM_WIDTH{1'b0}};
    end else if (c_state == SET_LIVE_MODE) begin
      r_fnum <= w_top_fnum;


    end else if (rd_eof) begin
      if (c_state == LOAD_HEAD) begin
        r_fnum <= r_head_fnum;
      end else if (c_state == LOAD_TOP) begin
        if (in_replay_mode) begin
		  r_fnum <= r_top_fnum;
		end else begin
		  r_fnum <= w_top_fnum;
		end
      end else if (c_state == INC_R_FNUM) begin
        r_fnum <= r_fnum + 9'd1;
      end
    end
  end
  

  assign rd_sob = ((r_fnum == r_head_fnum) && rd_sof) ? 1'b1 : 1'b0;
  

  assign rd_eob = (r_tail_frm && rd_eof) ? 1'b1 : 1'b0;
  

  always @(posedge clk) begin
    if (rst) begin
      frm_rpt_cntr <= 5'd0;
    end else if (rd_eof) begin
      if (frm_rpt_done) begin
        frm_rpt_cntr <= 5'd0;
      end else begin
        frm_rpt_cntr <= frm_rpt_cntr + 5'd1;
      end
    end
  end
  
  assign frm_rpt_done = (frm_rpt_cntr >= rpt_rate_ctrl-1) ? 1'b1 : 1'b0;
  
  always @(posedge clk) begin
    if (rst) begin
      in_replay_mode <= 1'b0;

    end else if (c_state == DISCARD_BUF) begin
      in_replay_mode <= 1'b0;

    end else if (rd_eof && c_state == LOAD_HEAD && (!in_replay_mode && !bcq_empty)) begin
      in_replay_mode <= 1'b1;
    end
  end
  
  assign disc_buf_ack = ((!CAPT_CNTRL_SEL && rd_eof) || (CAPT_CNTRL_SEL)) && (c_state == DISCARD_BUF) ? 1'b1 : 1'b0;
  assign bcq_rd_req = disc_buf_ack ? 1'b1 : 1'b0;
  
  assign is_video_buf = bcq_wdata[20];
  assign w_top_fnum = bcq_wdata[0+:FNUM_WIDTH];
  
  generate
    if (CAPT_CNTRL_SEL) begin : gen_capt
      assign buf_rpt_done = 1'b1;


    end else begin : gen_oled
      always @(posedge clk) begin
        if (rst) begin
          buf_rpt_done_i <= 1'b0;
        end else if (rd_eof && (c_state == END_OF_BUF || c_state == LOAD_HEAD)) begin
          buf_rpt_done_i <= ~buf_rpt_done_i;
        end
      end
      assign buf_rpt_done = buf_rpt_done_i;
      


    end
  endgenerate


  

  always @(posedge clk) begin
    if (rst) begin
      rpl_2x_done <= 1'b0;
    end else if (disc_buf_ack) begin
      rpl_2x_done <= 1'b0;
    end else if (buf_rpt_done && r_tail_frm && rd_eof) begin
      rpl_2x_done <= 1'b1;
	end
  end
  

  always @(posedge clk) begin
    if (rst) begin
      r_maddr <= {ADDR_WIDTH{1'b0}};
    end else if (c_state == FCQ_AVAIL) begin
      r_maddr <= r_sof_maddr;
	end else if (mem_rd_cmd) begin
      r_maddr <= r_maddr + (`MEM_RD_BL<<2);
    end
  end


  always @(posedge clk) begin
    r_maddr_d1 <= r_maddr;
  end
  

  always @(posedge clk) begin
    if (rst || c_state == IDLE) begin
      buf_avail <= 1'b0;
    end else if (c_state == FCQ_AVAIL) begin
      buf_avail <= 1'b1;
    end
  end
  
  assign w_tail_frm = fcq_wdata[1+:1];
  

  always@(posedge clk) begin
    if(rst) begin
      frm_avail <= 1'b0;
    end else if(fcq_wr_en) begin
      if(w_tail_frm) begin
        frm_avail <= 1'b0;
      end else begin
        frm_avail <= 1'b1;
      end
    end
  end



  always @(posedge clk) begin
    if (rst) begin
      rd_word_cntr <= {`FL_WIDTH{1'b0}};
    end else if(mem_rd_vld) begin
      if (rd_eof) begin
        rd_word_cntr <= {`FL_WIDTH{1'b0}};
      end else begin
        rd_word_cntr <= rd_word_cntr + 'd1;
      end
    end
  end
  
  assign rd_sof = rd_word_cntr == 0 ? 1'b1 : 1'b0;
  assign rd_eof = mem_rd_vld && rd_word_cntr == ((r_frm_len>>2)-1) ? 1'b1 : 1'b0;
  



  generate
    for (i=0; i<2; i=i+1) begin : fcq_gen  
      sp_bram_36x512 i_fcq (
        .clka                 (clk),
        .reseta               (rst),
        .cea                  (fcq_wr_en),
        .ada                  (fcq_wr_addr),
        .din                  (fcq_wdata[i*36+:36]),
        .clkb                 (clk),
        .resetb               (rst),
        .oce                  (`TIED_TO_VCC),
        .ceb                  (`TIED_TO_VCC),
        .adb                  (r_fnum),
        .dout                 (fcq_rdata[i*36+:36])
      );
    end
  endgenerate
  
  assign r_sof_maddr = fcq_rdata[30+:ADDR_WIDTH];
  assign r_zoom_ctrl = fcq_rdata[26+:4];
  assign r_frm_len   = fcq_rdata[2+:`FL_WIDTH];
  assign r_tail_frm  = fcq_rdata[1+:1];
  assign r_bot_frm   = fcq_rdata[0+:1];
  

  assign w_frm_len    = fcq_wdata[2+:`FL_WIDTH];
  assign fl_fcq_wdata = {12'b0, w_frm_len};
  sp_bram_36x512 i_fcq_frm_len (
    .clka                 (clk),
    .reseta               (rst),
    .cea                  (fcq_wr_en),
    .ada                  (fcq_wr_addr),
    .din                  (fl_fcq_wdata),
    .clkb                 (clk),
    .resetb               (rst),
    .oce                  (`TIED_TO_VCC),
    .ceb                  (`TIED_TO_VCC),
    .adb                  (fcq_wr_addr),
    .dout                 (fl_fcq_rdata)
  );
  

  assign prev_r_frm_len = fl_fcq_rdata[0+:`FL_WIDTH];

  always @(posedge clk) begin
    capturing_frm_d1 <= capturing_frm;
  end

  assign capturing_frm_re = (!capturing_frm_d1) & capturing_frm;
  
  always @(posedge clk) begin
    if (rst || send_wr_to_tob || capturing_frm_re) begin
      buf_size_cntr <= {32{1'b0}};
    end else if (fcq_wr_en) begin
      if (!capturing_frm && buf_full) begin
        buf_size_cntr <= buf_size_cntr + w_frm_len - prev_r_frm_len;
      end else begin
        buf_size_cntr <= buf_size_cntr + w_frm_len;
      end
    end
  end





























  
  assign bcq_wdata_i[0+:21] = bcq_wdata[0+:21];
  assign bcq_wdata_i[21+:32] = buf_size_cntr;
  assign bcq_wdata_i[53+:19] = 19'b0;
  generate
    for (i=0; i<2; i=i+1) begin : bcq_gen 
      fifo_fwft_36x512 i_bcq (
        .Clk                  (clk),
        .Reset                (rst),
        .WrEn                 (bcq_wr_en),
        .Data                 (bcq_wdata_i[i*36+:36]),
        .Full                 (bcq_full_i[i]),
        .Wnum                 (used_buf_cnt),
        .RdEn                 (bcq_rd_req),
        .Q                    (bcq_rdata[i*36+:36]),
        .Empty                (bcq_empty_i[i]),
        .Almost_Full          ()
      );
    end
  endgenerate
  
  assign bcq_full    = bcq_full_i[0] & bcq_full_i[1];
  assign bcq_empty   = bcq_empty_i[0] & bcq_empty_i[1];
  
  assign buf_size    = bcq_rdata[21+:32];
  assign video_buf_i = bcq_rdata[20+:1];
  assign frm_buf_i   = bcq_rdata[19+:1];
  assign audio_buf_i = bcq_rdata[18+:1];
  assign r_head_fnum = bcq_rdata[9+:FNUM_WIDTH];
  assign r_top_fnum  = bcq_rdata[0+:FNUM_WIDTH];
  
  always @(posedge clk) begin
    bcq_empty_d1 <= bcq_empty;
  end
  
  assign bcq_empty_fe = (!bcq_empty) & bcq_empty_d1;


  always @(posedge clk) begin
    rd_video_buf <= video_buf_i;
    rd_frm_buf   <= frm_buf_i;
    rd_audio_buf <= audio_buf_i;
  end
  

  















  
  always @(posedge clk) begin
    if (rst) begin
	  dbg_mrb_err <= 1'b0;
	end else if (rd_sof && mem_rd_cmd && r_maddr_d1 != 12'b0) begin
	  dbg_mrb_err <= 1'b1;
	end
  end
endmodule
module mem_rd_ctrl (
  rst,
  clk,
  rpt_rate_ctrl,

  fcq_wr_addr,
  fcq_wr_en,
  fcq_wdata,
  fcq_rd_en,
  buf_full,
  disc_this_buf,
  disc_buf_ack,
  send_wr_to_tob,
  capturing_frm,
  r_zoom_ctrl,
  r_frm_len,

  bcq_wr_en,
  bcq_wdata,
  bcq_tob_pulse,
  buf_size,

  mem_rd_cmd,
  mem_rd_vld,
  rpl_2x_done,
  buf_avail,
  frm_avail,
  r_maddr_d1,
  rd_video_buf,
  rd_frm_buf,
  rd_audio_buf,
  rd_sob,
  rd_eob,
  rd_sof,
  rd_eof,
  dbg_mrb_err
);

  

  parameter CAPT_CNTRL_SEL         = 1;
  parameter ADDR_WIDTH             = 25;
  parameter FNUM_WIDTH             = $clog2(`FL_WIDTH);
  

  input  wire                       rst;
  input  wire                       clk;
  input  wire [4:0]                 rpt_rate_ctrl;

  input  wire [FNUM_WIDTH-1:0]      fcq_wr_addr;
  input  wire                       fcq_wr_en;
  input  wire [71:0]                fcq_wdata;
  input  wire                       fcq_rd_en;
  input  wire                       buf_full;
  input  wire                       disc_this_buf;
  input  wire                       send_wr_to_tob;
  input  wire                       capturing_frm;
  output wire [3:0]                 r_zoom_ctrl;
  output wire [`FL_WIDTH-1:0]       r_frm_len;

  input  wire                       bcq_wr_en;
  input  wire [71:0]                bcq_wdata;
  output wire                       bcq_tob_pulse;
  output wire [31:0]                buf_size;

  input  wire                       mem_rd_cmd;
  input  wire                       mem_rd_vld;
  output reg                        rpl_2x_done;
  output wire                       disc_buf_ack;
  output reg                        buf_avail;
  output reg                        frm_avail;
  output reg  [ADDR_WIDTH-1:0]      r_maddr_d1;
  output reg                        rd_video_buf;
  output reg                        rd_frm_buf;
  output reg                        rd_audio_buf;
  output wire                       rd_sob;
  output wire                       rd_eob;
  output wire                       rd_sof;
  output wire                       rd_eof;
  output reg                        dbg_mrb_err;

  localparam  IDLE                = 14'b00_0000_0000_0001;
  localparam  FCQ_AVAIL           = 14'b00_0000_0000_0010;
  localparam  LOAD_TOP            = 14'b00_0000_0000_0100;
  localparam  LOAD_HEAD           = 14'b00_0000_0000_1000;
  localparam  FRM_RPT_WAIT        = 14'b00_0000_0001_0000;
  localparam  END_OF_BUF          = 14'b00_0000_0010_0000;
  localparam  BCQ_AVAIL           = 14'b00_0000_0100_0000;
  localparam  LOAD_SOF            = 14'b00_0000_1000_0000;
  localparam  INC_R_FNUM          = 14'b00_0001_0000_0000;
  localparam  RD_BCQ              = 14'b00_0010_0000_0000;
  localparam  RD_FCQ              = 14'b00_0100_0000_0000;
  localparam  DISCARD_BUF         = 14'b00_1000_0000_0000;
  localparam  SET_LIVE_MODE       = 14'b01_0000_0000_0000;
  localparam  SET_REPLAY_MODE     = 14'b10_0000_0000_0000;
  

  reg  [13:0]                       c_state;
  reg  [13:0]                       n_state;
  reg  [FNUM_WIDTH-1:0]             r_fnum;
  wire [71:0]                       fcq_rdata;
  wire [ADDR_WIDTH-1:0]             r_sof_maddr;
  wire                              r_tail_frm;
  wire                              r_bot_frm;
  wire                              bcq_full;
  wire                              bcq_empty;
  reg                               bcq_empty_d1;
  wire                              bcq_empty_fe;
  reg  [ADDR_WIDTH-1:0]             r_maddr;
  reg  [ADDR_WIDTH-1:0]             rd_word_cntr;
  wire [71:0]                       bcq_rdata;
  wire [FNUM_WIDTH-1:0]             w_top_fnum;
  wire [FNUM_WIDTH-1:0]             r_head_fnum;
  wire [FNUM_WIDTH-1:0]             r_top_fnum;
  wire [9:0]                        used_buf_cnt;
  wire [35:0]                       fl_fcq_wdata;
  wire [35:0]                       fl_fcq_rdata;
  wire [71:0]                       bcq_wdata_i;
  reg  [31:0]                       buf_size_cntr;
  wire [`FL_WIDTH-1:0]              w_frm_len;
  wire [`FL_WIDTH-1:0]              prev_r_frm_len;
  wire                              frm_rpt_done;
  reg  [4:0]                        frm_rpt_cntr;
  reg                               buf_rpt_done_i;
  wire                              buf_rpt_done;
  wire                              bcq_rd_req;
  wire                              video_buf_i;
  wire                              frm_buf_i;
  wire                              audio_buf_i;
  wire                              bcq_wr_en_i;
  wire                              is_video_buf;
  wire                              w_tail_frm;
  reg                               in_replay_mode;
  reg                               capturing_frm_d1;
  wire                              capturing_frm_re;
  wire [1:0]                        bcq_full_i;
  wire [1:0]                        bcq_empty_i;
   
  genvar i;





  always @(posedge clk) begin
    if (rst) begin
      c_state <= IDLE;
    end else begin
      c_state <= n_state;
    end
  end
  

  always @(*) begin
    case (c_state)
      IDLE:
if (!CAPT_CNTRL_SEL && frm_avail) begin
          n_state = SET_LIVE_MODE;
        end else begin
          n_state = IDLE;
        end

      SET_LIVE_MODE:
        n_state = RD_FCQ;
        
      SET_REPLAY_MODE:

          n_state = RD_BCQ;



        
      RD_BCQ:
        n_state = BCQ_AVAIL;
        
      BCQ_AVAIL:
        if (rd_eof) begin
		  n_state = RD_FCQ;
		end else begin
          n_state = BCQ_AVAIL;
        end
        
      RD_FCQ:
        n_state = FCQ_AVAIL;
        
      FCQ_AVAIL:
        n_state = FRM_RPT_WAIT;
        
      FRM_RPT_WAIT:
        if (!CAPT_CNTRL_SEL && disc_this_buf && frm_avail) begin
          n_state = DISCARD_BUF;
        end else if (CAPT_CNTRL_SEL && disc_this_buf) begin
          n_state = DISCARD_BUF;


        end else if (frm_rpt_done) begin
          if (CAPT_CNTRL_SEL && r_tail_frm) begin
            n_state = END_OF_BUF;
          end else if (!CAPT_CNTRL_SEL && ((in_replay_mode && r_tail_frm) || (!in_replay_mode && !bcq_empty))) begin
            n_state = LOAD_HEAD;
          end else if (r_bot_frm) begin
            n_state = LOAD_TOP;
          end else begin
            n_state = INC_R_FNUM;
          end
        end else begin
          n_state = LOAD_SOF;
        end
        
      LOAD_TOP:
        if (rd_eof) begin
          n_state = RD_FCQ;
        end else begin
          n_state = LOAD_TOP;
        end
        
      LOAD_HEAD:
        if (rd_eof) begin
          n_state = RD_FCQ;
        end else begin
          n_state = LOAD_HEAD;
        end

      LOAD_SOF:
        if (rd_eof) begin
          n_state = RD_FCQ;
        end else begin
          n_state = LOAD_SOF;
        end

      INC_R_FNUM:
        if (rd_eof) begin
          n_state = RD_FCQ;
        end else begin
          n_state = INC_R_FNUM;
        end
        
      END_OF_BUF:
        if (disc_this_buf) begin
          n_state = DISCARD_BUF;
        end else begin
          n_state = END_OF_BUF;
        end
        
      DISCARD_BUF:
        if (CAPT_CNTRL_SEL) begin
          n_state = IDLE;
        end else begin
          if (rd_eof) begin
            n_state = IDLE;
          end else begin
            n_state = DISCARD_BUF;
          end
        end
        
      default: n_state = IDLE;
    endcase
  end
  

  always @(posedge clk) begin
    if (rst) begin
      r_fnum <= {FNUM_WIDTH{1'b0}};
    end else if (c_state == SET_LIVE_MODE) begin
      r_fnum <= w_top_fnum;


    end else if (rd_eof) begin
      if (c_state == LOAD_HEAD) begin
        r_fnum <= r_head_fnum;
      end else if (c_state == LOAD_TOP) begin
        if (in_replay_mode) begin
		  r_fnum <= r_top_fnum;
		end else begin
		  r_fnum <= w_top_fnum;
		end
      end else if (c_state == INC_R_FNUM) begin
        r_fnum <= r_fnum + 9'd1;
      end
    end
  end
  

  assign rd_sob = ((r_fnum == r_head_fnum) && rd_sof) ? 1'b1 : 1'b0;
  

  assign rd_eob = (r_tail_frm && rd_eof) ? 1'b1 : 1'b0;
  

  always @(posedge clk) begin
    if (rst) begin
      frm_rpt_cntr <= 5'd0;
    end else if (rd_eof) begin
      if (frm_rpt_done) begin
        frm_rpt_cntr <= 5'd0;
      end else begin
        frm_rpt_cntr <= frm_rpt_cntr + 5'd1;
      end
    end
  end
  
  assign frm_rpt_done = (frm_rpt_cntr >= rpt_rate_ctrl-1) ? 1'b1 : 1'b0;
  
  always @(posedge clk) begin
    if (rst) begin
      in_replay_mode <= 1'b0;

    end else if (c_state == DISCARD_BUF) begin
      in_replay_mode <= 1'b0;

    end else if (rd_eof && c_state == LOAD_HEAD && (!in_replay_mode && !bcq_empty)) begin
      in_replay_mode <= 1'b1;
    end
  end
  
  assign disc_buf_ack = ((!CAPT_CNTRL_SEL && rd_eof) || (CAPT_CNTRL_SEL)) && (c_state == DISCARD_BUF) ? 1'b1 : 1'b0;
  assign bcq_rd_req = disc_buf_ack ? 1'b1 : 1'b0;
  
  assign is_video_buf = bcq_wdata[20];
  assign w_top_fnum = bcq_wdata[0+:FNUM_WIDTH];
  
  generate
    if (CAPT_CNTRL_SEL) begin : gen_capt
      assign buf_rpt_done = 1'b1;


    end else begin : gen_oled
      always @(posedge clk) begin
        if (rst) begin
          buf_rpt_done_i <= 1'b0;
        end else if (rd_eof && (c_state == END_OF_BUF || c_state == LOAD_HEAD)) begin
          buf_rpt_done_i <= ~buf_rpt_done_i;
        end
      end
      assign buf_rpt_done = buf_rpt_done_i;
      


    end
  endgenerate


  

  always @(posedge clk) begin
    if (rst) begin
      rpl_2x_done <= 1'b0;
    end else if (disc_buf_ack) begin
      rpl_2x_done <= 1'b0;
    end else if (buf_rpt_done && r_tail_frm && rd_eof) begin
      rpl_2x_done <= 1'b1;
	end
  end
  

  always @(posedge clk) begin
    if (rst) begin
      r_maddr <= {ADDR_WIDTH{1'b0}};
    end else if (c_state == FCQ_AVAIL) begin
      r_maddr <= r_sof_maddr;
	end else if (mem_rd_cmd) begin
      r_maddr <= r_maddr + (`MEM_RD_BL<<2);
    end
  end


  always @(posedge clk) begin
    r_maddr_d1 <= r_maddr;
  end
  

  always @(posedge clk) begin
    if (rst || c_state == IDLE) begin
      buf_avail <= 1'b0;
    end else if (c_state == FCQ_AVAIL) begin
      buf_avail <= 1'b1;
    end
  end
  
  assign w_tail_frm = fcq_wdata[1+:1];
  

  always@(posedge clk) begin
    if(rst) begin
      frm_avail <= 1'b0;
    end else if(fcq_wr_en) begin
      if(w_tail_frm) begin
        frm_avail <= 1'b0;
      end else begin
        frm_avail <= 1'b1;
      end
    end
  end



  always @(posedge clk) begin
    if (rst) begin
      rd_word_cntr <= {`FL_WIDTH{1'b0}};
    end else if(mem_rd_vld) begin
      if (rd_eof) begin
        rd_word_cntr <= {`FL_WIDTH{1'b0}};
      end else begin
        rd_word_cntr <= rd_word_cntr + 'd1;
      end
    end
  end
  
  assign rd_sof = rd_word_cntr == 0 ? 1'b1 : 1'b0;
  assign rd_eof = mem_rd_vld && rd_word_cntr == ((r_frm_len>>2)-1) ? 1'b1 : 1'b0;
  



  generate
    for (i=0; i<2; i=i+1) begin : fcq_gen  
      sp_bram_36x512 i_fcq (
        .clka                 (clk),
        .reseta               (rst),
        .cea                  (fcq_wr_en),
        .ada                  (fcq_wr_addr),
        .din                  (fcq_wdata[i*36+:36]),
        .clkb                 (clk),
        .resetb               (rst),
        .oce                  (`TIED_TO_VCC),
        .ceb                  (`TIED_TO_VCC),
        .adb                  (r_fnum),
        .dout                 (fcq_rdata[i*36+:36])
      );
    end
  endgenerate
  
  assign r_sof_maddr = fcq_rdata[30+:ADDR_WIDTH];
  assign r_zoom_ctrl = fcq_rdata[26+:4];
  assign r_frm_len   = fcq_rdata[2+:`FL_WIDTH];
  assign r_tail_frm  = fcq_rdata[1+:1];
  assign r_bot_frm   = fcq_rdata[0+:1];
  

  assign w_frm_len    = fcq_wdata[2+:`FL_WIDTH];
  assign fl_fcq_wdata = {12'b0, w_frm_len};
  sp_bram_36x512 i_fcq_frm_len (
    .clka                 (clk),
    .reseta               (rst),
    .cea                  (fcq_wr_en),
    .ada                  (fcq_wr_addr),
    .din                  (fl_fcq_wdata),
    .clkb                 (clk),
    .resetb               (rst),
    .oce                  (`TIED_TO_VCC),
    .ceb                  (`TIED_TO_VCC),
    .adb                  (fcq_wr_addr),
    .dout                 (fl_fcq_rdata)
  );
  

  assign prev_r_frm_len = fl_fcq_rdata[0+:`FL_WIDTH];

  always @(posedge clk) begin
    capturing_frm_d1 <= capturing_frm;
  end

  assign capturing_frm_re = (!capturing_frm_d1) & capturing_frm;
  
  always @(posedge clk) begin
    if (rst || send_wr_to_tob || capturing_frm_re) begin
      buf_size_cntr <= {32{1'b0}};
    end else if (fcq_wr_en) begin
      if (!capturing_frm && buf_full) begin
        buf_size_cntr <= buf_size_cntr + w_frm_len - prev_r_frm_len;
      end else begin
        buf_size_cntr <= buf_size_cntr + w_frm_len;
      end
    end
  end





























  
  assign bcq_wdata_i[0+:21] = bcq_wdata[0+:21];
  assign bcq_wdata_i[21+:32] = buf_size_cntr;
  assign bcq_wdata_i[53+:19] = 19'b0;
  generate
    for (i=0; i<2; i=i+1) begin : bcq_gen 
      fifo_fwft_36x512 i_bcq (
        .Clk                  (clk),
        .Reset                (rst),
        .WrEn                 (bcq_wr_en),
        .Data                 (bcq_wdata_i[i*36+:36]),
        .Full                 (bcq_full_i[i]),
        .Wnum                 (used_buf_cnt),
        .RdEn                 (bcq_rd_req),
        .Q                    (bcq_rdata[i*36+:36]),
        .Empty                (bcq_empty_i[i]),
        .Almost_Full          ()
      );
    end
  endgenerate
  
  assign bcq_full    = bcq_full_i[0] & bcq_full_i[1];
  assign bcq_empty   = bcq_empty_i[0] & bcq_empty_i[1];
  
  assign buf_size    = bcq_rdata[21+:32];
  assign video_buf_i = bcq_rdata[20+:1];
  assign frm_buf_i   = bcq_rdata[19+:1];
  assign audio_buf_i = bcq_rdata[18+:1];
  assign r_head_fnum = bcq_rdata[9+:FNUM_WIDTH];
  assign r_top_fnum  = bcq_rdata[0+:FNUM_WIDTH];
  
  always @(posedge clk) begin
    bcq_empty_d1 <= bcq_empty;
  end
  
  assign bcq_empty_fe = (!bcq_empty) & bcq_empty_d1;


  always @(posedge clk) begin
    rd_video_buf <= video_buf_i;
    rd_frm_buf   <= frm_buf_i;
    rd_audio_buf <= audio_buf_i;
  end
  

  















  
  always @(posedge clk) begin
    if (rst) begin
	  dbg_mrb_err <= 1'b0;
	end else if (rd_sof && mem_rd_cmd && r_maddr_d1 != 12'b0) begin
	  dbg_mrb_err <= 1'b1;
	end
  end
endmodule