data/full_repos/permissive/406635962/src/rtl/itcm_ctrl.v
1: b'%Error: data/full_repos/permissive/406635962/src/rtl/itcm_ctrl.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/406635962/src/rtl/itcm_ctrl.v:8: Define or directive not defined: \'`ITCM_ADDR_WIDTH\'\n    input [`ITCM_ADDR_WIDTH-1:0] ifu2itcm_cmd_addr,\n           ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/itcm_ctrl.v:12: Define or directive not defined: \'`ITCM_RAM_DW\'\n    output [`ITCM_RAM_DW-1:0] ifu2itcm_rsp_rdata,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/itcm_ctrl.v:15: Define or directive not defined: \'`ITCM_RAM_AW\'\n    output [`ITCM_RAM_AW-1:0] itcm_ram_addr,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/itcm_ctrl.v:16: Define or directive not defined: \'`ITCM_RAM_DW\'\n    input [`ITCM_RAM_DW-1:0] itcm_ram_dout,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/itcm_ctrl.v:24: Define or directive not defined: \'`ITCM_RAM_DW\'\n    assign ifu2itcm_rsp_rdata = {`ITCM_RAM_DW{ifu2itcm_rsp_hdskd}} & itcm_ram_dout;\n                                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/itcm_ctrl.v:25: Define or directive not defined: \'`ITCM_ADDR_WIDTH\'\n    assign itcm_ram_addr = ifu2itcm_cmd_addr[`ITCM_ADDR_WIDTH-1:2];\n                                             ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n'
module itcm_ctrl (


    input ifu2itcm_cmd_valid,
    output ifu2itcm_cmd_ready,
    input [`ITCM_ADDR_WIDTH-1:0] ifu2itcm_cmd_addr,
    
    output ifu2itcm_rsp_valid,
    input ifu2itcm_rsp_ready,
    output [`ITCM_RAM_DW-1:0] ifu2itcm_rsp_rdata,


    output [`ITCM_RAM_AW-1:0] itcm_ram_addr,
    input [`ITCM_RAM_DW-1:0] itcm_ram_dout,

    input clk,
    input rst_n
);

    assign ifu2itcm_cmd_ready = 1;
    wire ifu2itcm_rsp_hdskd = ifu2itcm_rsp_valid & ifu2itcm_rsp_ready;
    assign ifu2itcm_rsp_rdata = {`ITCM_RAM_DW{ifu2itcm_rsp_hdskd}} & itcm_ram_dout;
    assign itcm_ram_addr = ifu2itcm_cmd_addr[`ITCM_ADDR_WIDTH-1:2];
    
    wire ifu2itcm_rsp_valid_set = ifu2itcm_cmd_valid;
    wire ifu2itcm_rsp_valid_clr = ifu2itcm_rsp_valid;
    wire ifu2itcm_rsp_valid_nxt = ifu2itcm_rsp_valid_set | (~ifu2itcm_rsp_valid_clr);
    wire ifu2itcm_rsp_valid_ena = ifu2itcm_rsp_valid_set | ifu2itcm_rsp_valid_clr;
    gnrl_dfflr #(1) ifu2itcm_rsp_valid_dfflr(ifu2itcm_rsp_valid_ena, ifu2itcm_rsp_valid_nxt, ifu2itcm_rsp_valid, clk, rst_n);
endmodule
module itcm_ctrl (


    input ifu2itcm_cmd_valid,
    output ifu2itcm_cmd_ready,
    input [`ITCM_ADDR_WIDTH-1:0] ifu2itcm_cmd_addr,
    
    output ifu2itcm_rsp_valid,
    input ifu2itcm_rsp_ready,
    output [`ITCM_RAM_DW-1:0] ifu2itcm_rsp_rdata,


    output [`ITCM_RAM_AW-1:0] itcm_ram_addr,
    input [`ITCM_RAM_DW-1:0] itcm_ram_dout,

    input clk,
    input rst_n
);


    assign ifu2itcm_cmd_ready = 1;
    wire ifu2itcm_rsp_hdskd = ifu2itcm_rsp_valid & ifu2itcm_rsp_ready;
    assign ifu2itcm_rsp_rdata = {`ITCM_RAM_DW{ifu2itcm_rsp_hdskd}} & itcm_ram_dout;
    assign itcm_ram_addr = ifu2itcm_cmd_addr[`ITCM_ADDR_WIDTH-1:2];
    
    wire ifu2itcm_rsp_valid_set = ifu2itcm_cmd_valid;
    wire ifu2itcm_rsp_valid_clr = ifu2itcm_rsp_valid;
    wire ifu2itcm_rsp_valid_nxt = ifu2itcm_rsp_valid_set | (~ifu2itcm_rsp_valid_clr);
    wire ifu2itcm_rsp_valid_ena = ifu2itcm_rsp_valid_set | ifu2itcm_rsp_valid_clr;
    gnrl_dfflr #(1) ifu2itcm_rsp_valid_dfflr(ifu2itcm_rsp_valid_ena, ifu2itcm_rsp_valid_nxt, ifu2itcm_rsp_valid, clk, rst_n);
endmodule