data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Saber_blocks/ins_ROM.v
1: b'%Warning-WIDTH: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Saber_blocks/ins_ROM.v:9: Operator COND expects 38 bits on the Conditional True, but Conditional True\'s CONST \'37\'h0\' generates 37 bits.\n                                                                                                         : ... In instance ins_ROM_old\nassign rom_data_w = (address==6\'d0) ? 37\'d0 :\n                                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Saber_blocks/ins_ROM.v:10: Operator COND expects 38 bits on the Conditional True, but Conditional True\'s REPLICATE generates 37 bits.\n                                                                                                          : ... In instance ins_ROM_old\n          (address==6\'d1) ? {1\'b0,1\'b1,10\'d0,10\'d0,10\'d0,5\'d0} :\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Saber_blocks/ins_ROM.v:11: Operator COND expects 38 bits on the Conditional True, but Conditional True\'s REPLICATE generates 37 bits.\n                                                                                                          : ... In instance ins_ROM_old\n          (address==6\'d2) ? {1\'b1,1\'b0,3\'d0,16\'d32,16\'d32} :         \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Saber_blocks/ins_ROM.v:12: Operator COND expects 38 bits on the Conditional True, but Conditional True\'s REPLICATE generates 37 bits.\n                                                                                                          : ... In instance ins_ROM_old\n          (address==6\'d3) ? {1\'b0,1\'b1,10\'d124,10\'d0,10\'d124,5\'d1} :  \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Saber_blocks/ins_ROM.v:13: Operator COND expects 38 bits on the Conditional True, but Conditional True\'s REPLICATE generates 37 bits.\n                                                                                                          : ... In instance ins_ROM_old\n          (address==6\'d4) ? {1\'b0,1\'b1,10\'d0,10\'d0,10\'d0,5\'d0} :\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Saber_blocks/ins_ROM.v:14: Operator COND expects 38 bits on the Conditional True, but Conditional True\'s REPLICATE generates 37 bits.\n                                                                                                          : ... In instance ins_ROM_old\n          (address==6\'d5) ? {1\'b0,1\'b1,10\'d0,10\'d0,10\'d0,5\'d31} : \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Saber_blocks/ins_ROM.v:14: Operator COND expects 38 bits on the Conditional False, but Conditional False\'s CONST \'37\'h0\' generates 37 bits.\n                                                                                                          : ... In instance ins_ROM_old\n          (address==6\'d5) ? {1\'b0,1\'b1,10\'d0,10\'d0,10\'d0,5\'d31} : \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Saber_blocks/ins_ROM.v:18: Operator ASSIGNDLY expects 37 bits on the Assign RHS, but Assign RHS\'s VARREF \'rom_data_w\' generates 38 bits.\n                                                                                                          : ... In instance ins_ROM_old\n rom_data <= rom_data_w;\n          ^~\n%Error: Exiting due to 8 warning(s)\n'
module ins_ROM_old(clk, address, rom_data);
input clk;
input [5:0] address;
output reg [36:0] rom_data;

wire [37:0] rom_data_w;


assign rom_data_w = (address==6'd0) ? 37'd0 :
										(address==6'd1) ? {1'b0,1'b1,10'd0,10'd0,10'd0,5'd0} :
										(address==6'd2) ? {1'b1,1'b0,3'd0,16'd32,16'd32} :									
										(address==6'd3) ? {1'b0,1'b1,10'd124,10'd0,10'd124,5'd1} :
										(address==6'd4) ? {1'b0,1'b1,10'd0,10'd0,10'd0,5'd0} :
										(address==6'd5) ? {1'b0,1'b1,10'd0,10'd0,10'd0,5'd31} :	
										37'd0;
									
always @(posedge clk)
	rom_data <= rom_data_w;
	
endmodule
module ins_ROM_old(clk, address, rom_data);

input clk;
input [5:0] address;
output reg [36:0] rom_data;

wire [37:0] rom_data_w;


assign rom_data_w = (address==6'd0) ? 37'd0 :
										(address==6'd1) ? {1'b0,1'b1,10'd0,10'd0,10'd0,5'd0} :
										(address==6'd2) ? {1'b1,1'b0,3'd0,16'd32,16'd32} :									
										(address==6'd3) ? {1'b0,1'b1,10'd124,10'd0,10'd124,5'd1} :
										(address==6'd4) ? {1'b0,1'b1,10'd0,10'd0,10'd0,5'd0} :
										(address==6'd5) ? {1'b0,1'b1,10'd0,10'd0,10'd0,5'd31} :	
										37'd0;
									
always @(posedge clk)
	rom_data <= rom_data_w;
	
endmodule