data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/strobe_gen.v
data/verilator_xmls/ba47c397-2422-4f2f-b674-3c7fdc4079d9.xml
module strobe_gen 
  ( input clock,
    input reset,
    input enable,
    input [7:0] rate,
    input strobe_in,
    output wire strobe );
   

   
   reg [7:0] counter;
   assign strobe = ~|counter && enable && strobe_in;
   
   always @(posedge clock)
     if(reset | ~enable)
       counter <= #1 8'd0;
     else if(strobe_in)
       if(counter == 0)
	 counter <= #1 rate;
       else 
	 counter <= #1 counter - 8'd1;
   
endmodule
module strobe_gen 
  ( input clock,
    input reset,
    input enable,
    input [7:0] rate,
    input strobe_in,
    output wire strobe );

   

   
   reg [7:0] counter;
   assign strobe = ~|counter && enable && strobe_in;
   
   always @(posedge clock)
     if(reset | ~enable)
       counter <= #1 8'd0;
     else if(strobe_in)
       if(counter == 0)
	 counter <= #1 rate;
       else 
	 counter <= #1 counter - 8'd1;
   
endmodule