data/full_repos/permissive/427281804/FPU/verilog/FPALU_add29i_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/427281804/FPU/verilog/FPALU_add29i_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/427281804/FPU/verilog/FPALU_add29i_tb.v:53: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("dump.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/427281804/FPU/verilog/FPALU_add29i_tb.v:54: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/427281804/FPU/verilog/FPALU_add29i_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = ~clk;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/427281804/FPU/verilog/FPALU_add29i_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n   #1 clk = ~clk;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/427281804/FPU/verilog/FPALU_add29i_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n   #1 clk = ~clk;\n   ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module FPALU_tb();
	reg [31:0] a;
	reg [31:0] b;


	real      result;
	reg       clk;
	reg       rst_n;
	reg [1:0] opcode;
  
	wire          din_uni_a_sgn    = a[28];
	wire [5:0]    din_uni_a_exp    = a[27:22];
	wire [21:0]   din_uni_a_man_dn = a[21:0];
	wire          din_uni_b_sgn    = b[28];
	wire [5:0]    din_uni_b_exp    = b[27:22];
	wire [21:0]   din_uni_b_man_dn = b[21:0];
	wire          dout_uni_y_sgn;
	wire [5:0]    dout_uni_y_exp; 
	wire [21:0]   dout_uni_y_man_dn;

	FPALU dut(
		.clk(clk), .opcode(opcode),
		.din_uni_a_sgn     (din_uni_a_sgn    ),
		.din_uni_a_exp     (din_uni_a_exp    ),
		.din_uni_a_man_dn  (din_uni_a_man_dn ),
		.din_uni_b_sgn     (din_uni_b_sgn    ),
		.din_uni_b_exp     (din_uni_b_exp    ),
		.din_uni_b_man_dn  (din_uni_b_man_dn ),
		.dout_uni_y_sgn    (dout_uni_y_sgn   ),
		.dout_uni_y_exp    (dout_uni_y_exp   ),
		.dout_uni_y_man_dn (dout_uni_y_man_dn)
	);
	
	integer i;
	initial begin
		a = {$random};
		b = {$random};
		a = {$random};
		b = {$random};
		a = {$random};
		b = {$random};
		a = {$random};
		b = {$random};
		opcode = 2'b11;
		clk    = 0;
		#1;
		
		$dumpfile("dump.vcd");
		$dumpvars;
		#1 clk = ~clk;


		for(i=0;i<10;i=i+1) begin
			#1 clk = ~clk;
			#1 clk = ~clk;
		end
		$finish;
	end

endmodule
module FPALU_tb();

	reg [31:0] a;
	reg [31:0] b;


	real      result;
	reg       clk;
	reg       rst_n;
	reg [1:0] opcode;
  
	wire          din_uni_a_sgn    = a[28];
	wire [5:0]    din_uni_a_exp    = a[27:22];
	wire [21:0]   din_uni_a_man_dn = a[21:0];
	wire          din_uni_b_sgn    = b[28];
	wire [5:0]    din_uni_b_exp    = b[27:22];
	wire [21:0]   din_uni_b_man_dn = b[21:0];
	wire          dout_uni_y_sgn;
	wire [5:0]    dout_uni_y_exp; 
	wire [21:0]   dout_uni_y_man_dn;

	FPALU dut(
		.clk(clk), .opcode(opcode),
		.din_uni_a_sgn     (din_uni_a_sgn    ),
		.din_uni_a_exp     (din_uni_a_exp    ),
		.din_uni_a_man_dn  (din_uni_a_man_dn ),
		.din_uni_b_sgn     (din_uni_b_sgn    ),
		.din_uni_b_exp     (din_uni_b_exp    ),
		.din_uni_b_man_dn  (din_uni_b_man_dn ),
		.dout_uni_y_sgn    (dout_uni_y_sgn   ),
		.dout_uni_y_exp    (dout_uni_y_exp   ),
		.dout_uni_y_man_dn (dout_uni_y_man_dn)
	);
	
	integer i;
	initial begin
		a = {$random};
		b = {$random};
		a = {$random};
		b = {$random};
		a = {$random};
		b = {$random};
		a = {$random};
		b = {$random};
		opcode = 2'b11;
		clk    = 0;
		#1;
		
		$dumpfile("dump.vcd");
		$dumpvars;
		#1 clk = ~clk;


		for(i=0;i<10;i=i+1) begin
			#1 clk = ~clk;
			#1 clk = ~clk;
		end
		$finish;
	end

endmodule