data/full_repos/permissive/420117502/Basic/3_LED_Blink/LED.v
data/verilator_xmls/6f40c3a3-dc77-447c-a3c1-a910036baf64.xml
module LED(
    input clk,
    input rst_n,
    output wire led
);
    reg [23:0] cnt;
    always @ (posedge clk or negedge rst_n) begin
        if(~rst_n) cnt<='b0;
        else cnt<=cnt+1'b1;
    end
    assign led = cnt[23];
endmodule
module LED(
    input clk,
    input rst_n,
    output wire led
);

    reg [23:0] cnt;
    always @ (posedge clk or negedge rst_n) begin
        if(~rst_n) cnt<='b0;
        else cnt<=cnt+1'b1;
    end
    assign led = cnt[23];
endmodule