data/full_repos/permissive/498662723/Verilog Language/Vectors/Vector3.v
1: b'%Error: Cannot find file containing module: Language/Vectors,data/full_repos/permissive/498662723\n        ... Looked in:\n             data/full_repos/permissive/498662723/Verilog/Language/Vectors,data/full_repos/permissive/498662723\n             data/full_repos/permissive/498662723/Verilog/Language/Vectors,data/full_repos/permissive/498662723.v\n             data/full_repos/permissive/498662723/Verilog/Language/Vectors,data/full_repos/permissive/498662723.sv\n             Language/Vectors,data/full_repos/permissive/498662723\n             Language/Vectors,data/full_repos/permissive/498662723.v\n             Language/Vectors,data/full_repos/permissive/498662723.sv\n             obj_dir/Language/Vectors,data/full_repos/permissive/498662723\n             obj_dir/Language/Vectors,data/full_repos/permissive/498662723.v\n             obj_dir/Language/Vectors,data/full_repos/permissive/498662723.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/498662723/Verilog\n%Error: Cannot find file containing module: Language/Vectors/Vector3.v\n%Error: Exiting due to 3 error(s)\n'
module top_module (
    input [4:0] a, b, c, d, e, f,
    output [7:0] w, x, y, z );

    assign {w[7:0], x[7:0], y[7:0], z[7:0]} = {a[4:0], b[4:0], c[4:0], d[4:0], e[4:0], f[4:0], 2'b11};

endmodule
module top_module (
    input [4:0] a, b, c, d, e, f,
    output [7:0] w, x, y, z );


    assign {w[7:0], x[7:0], y[7:0], z[7:0]} = {a[4:0], b[4:0], c[4:0], d[4:0], e[4:0], f[4:0], 2'b11};

endmodule