data/full_repos/permissive/435516446/MIPS/ID_EX_Register.v
1: b'%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/ID_EX_Register.v:71: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'ALUOp\' generates 3 bits.\n                                                                             : ... In instance ID_EX_Register\n    ALUOpOut = ALUOp;\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module ID_EX_Register(
    input clock,
    input hit,
    input [31:0] readData1,
    input [31:0] readData2,
    input [31:0] signExImmediate,
    input RegDst,
    input ALUSrc,
    input MemtoReg,
    input RegWrite,
    input MemRead,
    input MemWrite,
    input Branch,
    input [2:0] ALUOp,
    input [4:0] rt,
    input [4:0] rd,
    input [5:0] funct,
    input [31:0] nextPC,
	 input jumpSignal,
    output reg [31:0] readData1Out,
    output reg [31:0] readData2Out,
    output reg [31:0] signExImmediateOut,
    output reg RegDstOut,
    output reg ALUSrcOut,
    output reg MemtoRegOut,
    output reg RegWriteOut,
    output reg MemReadOut,
    output reg MemWriteOut,
    output reg BranchOut,
    output reg [5:0] ALUOpOut,
    output reg [4:0] rtOut,
    output reg [4:0] rdOut,
    output reg [5:0] functOut,
    output reg [31:0] nextPCOut,
    output wire hitOut,
	 output reg jumpSignalOut
    );

always@ (negedge clock) begin
	if(hit) begin
	 readData1Out = readData1;
    readData2Out = readData2;
    signExImmediateOut = signExImmediate;
    RegDstOut = RegDst;
    ALUSrcOut = ALUSrc;
    MemtoRegOut = MemtoReg;
    RegWriteOut = RegWrite;
    MemReadOut = MemRead;
    MemWriteOut = MemWrite;
    BranchOut = Branch;
    ALUOpOut = ALUOp;
    rtOut = rt;
    rdOut = rd;
    functOut = funct;
    nextPCOut = nextPC;
	 jumpSignalOut = jumpSignal;
	end
end

assign hitOut = hit;

endmodule
module ID_EX_Register(
    input clock,
    input hit,
    input [31:0] readData1,
    input [31:0] readData2,
    input [31:0] signExImmediate,
    input RegDst,
    input ALUSrc,
    input MemtoReg,
    input RegWrite,
    input MemRead,
    input MemWrite,
    input Branch,
    input [2:0] ALUOp,
    input [4:0] rt,
    input [4:0] rd,
    input [5:0] funct,
    input [31:0] nextPC,
	 input jumpSignal,
    output reg [31:0] readData1Out,
    output reg [31:0] readData2Out,
    output reg [31:0] signExImmediateOut,
    output reg RegDstOut,
    output reg ALUSrcOut,
    output reg MemtoRegOut,
    output reg RegWriteOut,
    output reg MemReadOut,
    output reg MemWriteOut,
    output reg BranchOut,
    output reg [5:0] ALUOpOut,
    output reg [4:0] rtOut,
    output reg [4:0] rdOut,
    output reg [5:0] functOut,
    output reg [31:0] nextPCOut,
    output wire hitOut,
	 output reg jumpSignalOut
    );


always@ (negedge clock) begin
	if(hit) begin
	 readData1Out = readData1;
    readData2Out = readData2;
    signExImmediateOut = signExImmediate;
    RegDstOut = RegDst;
    ALUSrcOut = ALUSrc;
    MemtoRegOut = MemtoReg;
    RegWriteOut = RegWrite;
    MemReadOut = MemRead;
    MemWriteOut = MemWrite;
    BranchOut = Branch;
    ALUOpOut = ALUOp;
    rtOut = rt;
    rdOut = rd;
    functOut = funct;
    nextPCOut = nextPC;
	 jumpSignalOut = jumpSignal;
	end
end

assign hitOut = hit;

endmodule