data/full_repos/permissive/40581558/fpga_sim/src/DSC.v
1: b'%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/src/DSC.v:48: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s DIVS generates 32 or 22 bits.\n                                                                         : ... In instance DSC\n  Real_X <=   Amp*128/211;        \n         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/src/DSC.v:52: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'DeadZone\' generates 8 bits.\n                                                                         : ... In instance DSC\n  IN_Region <= (Angle[14]?(Angle>-SHADOW_ANGLE):(Angle<SHADOW_ANGLE)) && (Real_X[17:8] <10\'d255+DeadZone) && (Real_X[17:8] > DeadZone) && (Column>10\'d12 && Column<10\'d321)  ;  \n                                                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/src/DSC.v:52: Operator GT expects 10 bits on the RHS, but RHS\'s VARREF \'DeadZone\' generates 8 bits.\n                                                                         : ... In instance DSC\n  IN_Region <= (Angle[14]?(Angle>-SHADOW_ANGLE):(Angle<SHADOW_ANGLE)) && (Real_X[17:8] <10\'d255+DeadZone) && (Real_X[17:8] > DeadZone) && (Column>10\'d12 && Column<10\'d321)  ;  \n                                                                                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/src/DSC.v:54: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 10 bits.\n                                                                         : ... In instance DSC\n  SRAM_Addr[18:8]<= {3\'b0,Real_Y[14:8]};\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/src/DSC.v:55: Operator GT expects 10 bits on the RHS, but RHS\'s VARREF \'DeadZone\' generates 8 bits.\n                                                                         : ... In instance DSC\n  SRAM_Addr[7:0] <=(Real_X[17:8]>DeadZone)?({Real_X[17:8]}-DeadZone):9\'d0;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/src/DSC.v:55: Operator SUB expects 10 bits on the RHS, but RHS\'s VARREF \'DeadZone\' generates 8 bits.\n                                                                         : ... In instance DSC\n  SRAM_Addr[7:0] <=(Real_X[17:8]>DeadZone)?({Real_X[17:8]}-DeadZone):9\'d0;\n                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/src/DSC.v:55: Operator COND expects 10 bits on the Conditional False, but Conditional False\'s CONST \'9\'h0\' generates 9 bits.\n                                                                         : ... In instance DSC\n  SRAM_Addr[7:0] <=(Real_X[17:8]>DeadZone)?({Real_X[17:8]}-DeadZone):9\'d0;\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/src/DSC.v:55: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s COND generates 10 bits.\n                                                                         : ... In instance DSC\n  SRAM_Addr[7:0] <=(Real_X[17:8]>DeadZone)?({Real_X[17:8]}-DeadZone):9\'d0;\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/src/DSC.v:57: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'DeadZone\' generates 8 bits.\n                                                                         : ... In instance DSC\n  realIn <= {(Row +DeadZone),8\'d0};\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/src/DSC.v:57: Operator ASSIGNDLY expects 20 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 18 bits.\n                                                                         : ... In instance DSC\n  realIn <= {(Row +DeadZone),8\'d0};\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/src/DSC.v:58: Operator ADD expects 20 bits on the LHS, but LHS\'s REPLICATE generates 18 bits.\n                                                                         : ... In instance DSC\n  imagIn <= {Column,8\'d0}+{-12\'d156,8\'b1111_1111};  \n                         ^\n%Error: data/full_repos/permissive/40581558/fpga_sim/src/DSC.v:62: Cannot find file containing module: \'coordinate_cordic\'\n coordinate_cordic coordinate_cordic_Inst\n ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/40581558/fpga_sim/src,data/full_repos/permissive/40581558/coordinate_cordic\n             data/full_repos/permissive/40581558/fpga_sim/src,data/full_repos/permissive/40581558/coordinate_cordic.v\n             data/full_repos/permissive/40581558/fpga_sim/src,data/full_repos/permissive/40581558/coordinate_cordic.sv\n             coordinate_cordic\n             coordinate_cordic.v\n             coordinate_cordic.sv\n             obj_dir/coordinate_cordic\n             obj_dir/coordinate_cordic.v\n             obj_dir/coordinate_cordic.sv\n%Error: Exiting due to 1 error(s), 11 warning(s)\n'
module DSC(
	LCLK,
	Row,
	Column,
	SRAM_Addr,
	Inter_Ratio1,
	Inter_Ratio2,
	DeadZone,
	IN_Region,
	Real_X,
	Real_Y,
	DSC_ANGLE

);

	input LCLK;
	input [9:0] Row;
	input [9:0] Column;
	output reg [18:0] SRAM_Addr;
	output reg [7:0] Inter_Ratio1;
	output reg [7:0] Inter_Ratio2;
	input [7:0] DeadZone;
	output reg IN_Region;
	output reg [17:0] Real_X;
	output reg [14:0] Real_Y;
	input [15:0] DSC_ANGLE;
	
	reg signed [19:0] realIn;
	reg signed [19:0] imagIn;
	wire signed [14:0] Angle;
	wire signed [21:0] Amp; 	
	
	

	
	



	wire signed [14:0] SHADOW_ANGLE;	
	wire signed [14:0] Angle_pos;

	
	assign Angle_pos = Angle + DSC_ANGLE[14:0];
    assign SHADOW_ANGLE = DSC_ANGLE[14:0] - 14'd100;
	
	always @(posedge LCLK) begin
		Real_X <=   Amp*128/211;
		Real_Y <=   Angle_pos*256*64/DSC_ANGLE[14:0];
		Inter_Ratio1 <=Real_Y[7:0];
		Inter_Ratio2 <=Real_X[7:0];
		IN_Region <= (Angle[14]?(Angle>-SHADOW_ANGLE):(Angle<SHADOW_ANGLE)) && (Real_X[17:8] <10'd255+DeadZone) && (Real_X[17:8] > DeadZone) && (Column>10'd12 && Column<10'd321)  ;

		SRAM_Addr[18:8]<= {3'b0,Real_Y[14:8]};
		SRAM_Addr[7:0] <=(Real_X[17:8]>DeadZone)?({Real_X[17:8]}-DeadZone):9'd0;
				
		realIn <= {(Row +DeadZone),8'd0};
		imagIn <= {Column,8'd0}+{-12'd156,8'b1111_1111};		
	end	
	
	
	coordinate_cordic coordinate_cordic_Inst
	(
		.realIn(realIn),
		.imagIn(imagIn),
		.clk(LCLK),
		.amplitude(Amp),
		.angle(Angle),
		.test1(),
		.test2()
	);



 

endmodule
module DSC(
	LCLK,
	Row,
	Column,
	SRAM_Addr,
	Inter_Ratio1,
	Inter_Ratio2,
	DeadZone,
	IN_Region,
	Real_X,
	Real_Y,
	DSC_ANGLE

);


	input LCLK;
	input [9:0] Row;
	input [9:0] Column;
	output reg [18:0] SRAM_Addr;
	output reg [7:0] Inter_Ratio1;
	output reg [7:0] Inter_Ratio2;
	input [7:0] DeadZone;
	output reg IN_Region;
	output reg [17:0] Real_X;
	output reg [14:0] Real_Y;
	input [15:0] DSC_ANGLE;
	
	reg signed [19:0] realIn;
	reg signed [19:0] imagIn;
	wire signed [14:0] Angle;
	wire signed [21:0] Amp; 	
	
	

	
	



	wire signed [14:0] SHADOW_ANGLE;	
	wire signed [14:0] Angle_pos;

	
	assign Angle_pos = Angle + DSC_ANGLE[14:0];
    assign SHADOW_ANGLE = DSC_ANGLE[14:0] - 14'd100;
	
	always @(posedge LCLK) begin
		Real_X <=   Amp*128/211;
		Real_Y <=   Angle_pos*256*64/DSC_ANGLE[14:0];
		Inter_Ratio1 <=Real_Y[7:0];
		Inter_Ratio2 <=Real_X[7:0];
		IN_Region <= (Angle[14]?(Angle>-SHADOW_ANGLE):(Angle<SHADOW_ANGLE)) && (Real_X[17:8] <10'd255+DeadZone) && (Real_X[17:8] > DeadZone) && (Column>10'd12 && Column<10'd321)  ;

		SRAM_Addr[18:8]<= {3'b0,Real_Y[14:8]};
		SRAM_Addr[7:0] <=(Real_X[17:8]>DeadZone)?({Real_X[17:8]}-DeadZone):9'd0;
				
		realIn <= {(Row +DeadZone),8'd0};
		imagIn <= {Column,8'd0}+{-12'd156,8'b1111_1111};		
	end	
	
	
	coordinate_cordic coordinate_cordic_Inst
	(
		.realIn(realIn),
		.imagIn(imagIn),
		.clk(LCLK),
		.amplitude(Amp),
		.angle(Angle),
		.test1(),
		.test2()
	);



 

endmodule