data/full_repos/permissive/497819211/03/Bit_tb.v
1: b'%Error: data/full_repos/permissive/497819211/03/Bit_tb.v:1: Cannot find include file: Bit.v\n`include "Bit.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/497819211/03,data/full_repos/permissive/497819211/Bit.v\n             data/full_repos/permissive/497819211/03,data/full_repos/permissive/497819211/Bit.v.v\n             data/full_repos/permissive/497819211/03,data/full_repos/permissive/497819211/Bit.v.sv\n             Bit.v\n             Bit.v.v\n             Bit.v.sv\n             obj_dir/Bit.v\n             obj_dir/Bit.v.v\n             obj_dir/Bit.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/497819211/03/Bit_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/497819211/03/Bit_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n     #1 $fwrite(file, "|%4d|%1b|%1b|%1b|\\n", t,in,load,out);\n     ^\n%Error: data/full_repos/permissive/497819211/03/Bit_tb.v:26: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("Bit_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/497819211/03/Bit_tb.v:27: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, Bit_tb);\n  ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module Bit_tb();

	integer file;

	reg clk = 1;
	wire out;
	reg load = 0;
	reg in=0;
    reg[9:0] t = 10'b0;

	Bit BIT(
    	.clk(clk),
		.load(load),
		.in(in),
		.out(out)
  	);

	always #1 clk = ~clk;

    task display;
    	#1 $fwrite(file, "|%4d|%1b|%1b|%1b|\n", t,in,load,out);
  	endtask

initial begin
  $dumpfile("Bit_tb.vcd");
  $dumpvars(0, Bit_tb);
    	file = $fopen("Bit.out","w");
    	$fwrite(file, "|time|in|load|out|\n");
        display();

        t=1;display();

        in=0;load=1;display();

        t=2;display();

        in=1;load=0;display();

        t=3;display();

        in=1;load=1;display();

        t=4;display();

        in=0;load=0;display();

        t=5;display();

        in=1;load=0;display();
   $finish;
end

endmodule
module Bit_tb();


	integer file;

	reg clk = 1;
	wire out;
	reg load = 0;
	reg in=0;
    reg[9:0] t = 10'b0;

	Bit BIT(
    	.clk(clk),
		.load(load),
		.in(in),
		.out(out)
  	);

	always #1 clk = ~clk;

    task display;
    	#1 $fwrite(file, "|%4d|%1b|%1b|%1b|\n", t,in,load,out);
  	endtask

initial begin
  $dumpfile("Bit_tb.vcd");
  $dumpvars(0, Bit_tb);
    	file = $fopen("Bit.out","w");
    	$fwrite(file, "|time|in|load|out|\n");
        display();

        t=1;display();

        in=0;load=1;display();

        t=2;display();

        in=1;load=0;display();

        t=3;display();

        in=1;load=1;display();

        t=4;display();

        in=0;load=0;display();

        t=5;display();

        in=1;load=0;display();
   $finish;
end

endmodule