data/full_repos/permissive/418331750/periph/uart/uart_top.v
1: b'%Warning-WIDTH: data/full_repos/permissive/418331750/periph/uart/uart_top.v:33: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                              : ... In instance uart_top\n    uart_regs[2][1:0] <= 1\'b0;\n                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/418331750/periph/uart/uart_top.v:35: Operator EQ expects 2 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                              : ... In instance uart_top\n   end else if (uart_regs[2][1:0] == 1\'b1 && tx_data_ready == 1\'b1) begin\n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/418331750/periph/uart/uart_top.v:40: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                              : ... In instance uart_top\n    uart_regs[2][2:1] <= 1\'b1;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/418331750/periph/uart/uart_top.v:44: Bit extraction of array[4:0] requires 3 bit index, not 2 bits.\n                                                                              : ... In instance uart_top\n     uart_regs[write_address[1:0]] <= write_data;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/418331750/periph/uart/uart_top.v:49: Bit extraction of array[4:0] requires 3 bit index, not 2 bits.\n                                                                              : ... In instance uart_top\n     read_data <= uart_regs[read_address[1:0]];\n                           ^\n%Error: data/full_repos/permissive/418331750/periph/uart/uart_top.v:58: Cannot find file containing module: \'uart_rx\'\n uart_rx#\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418331750/periph/uart,data/full_repos/permissive/418331750/uart_rx\n             data/full_repos/permissive/418331750/periph/uart,data/full_repos/permissive/418331750/uart_rx.v\n             data/full_repos/permissive/418331750/periph/uart,data/full_repos/permissive/418331750/uart_rx.sv\n             uart_rx\n             uart_rx.v\n             uart_rx.sv\n             obj_dir/uart_rx\n             obj_dir/uart_rx.v\n             obj_dir/uart_rx.sv\n%Error: data/full_repos/permissive/418331750/periph/uart/uart_top.v:72: Cannot find file containing module: \'uart_tx\'\n uart_tx#\n ^~~~~~~\n%Error: Exiting due to 2 error(s), 5 warning(s)\n'
module uart_top #(
	parameter CLK_FREQUENCY = 50,
	parameter BAUD_RATE = 115200
)
(
    input clk_in,
    input rst_n,
    input rx_pin,
    output tx_pin,
	input write_valid,
	input read_valid,
	input [31:0] write_data,
	output reg [31:0] read_data,
	input [31:0] write_address,
	input [31:0] read_address
);

	reg [31:0] uart_regs[0:4];
	wire [7:0]tx_data, rx_data;
	reg tx_data_valid;
	wire tx_data_ready, rx_data_valid, rx_data_ready;

	always @(posedge clk_in or negedge rst_n)
	begin
		if (rst_n == 1'b0) begin
			uart_regs[0] <= 32'h00000000;
			uart_regs[1] <= 32'h00000000;
			uart_regs[2] <= 32'h00000000;
			uart_regs[3] <= 32'h00000000;
			tx_data_valid <= 1'b0;
		end else begin
			if (tx_data_ready == 1'b1 && tx_data_valid == 1'b1) begin
				uart_regs[2][1:0] <= 1'b0;
				tx_data_valid <= 1'b0;
			end else if (uart_regs[2][1:0] == 1'b1 && tx_data_ready == 1'b1) begin
				tx_data_valid <= 1'b1;
			end
			if (rx_data_valid == 1'b1) begin
				uart_regs[1][7:0] <= rx_data;
				uart_regs[2][2:1] <= 1'b1;
			end
			if (write_address[31:4] == 28'h1000000) begin
				if (write_valid == 1'b1) begin
					uart_regs[write_address[1:0]] <= write_data;
				end
			end
			if (read_address[31:4] == 28'h1000000) begin
				if (read_valid == 1'b1) begin
					read_data <= uart_regs[read_address[1:0]];
				end
			end
		end
	end

	assign tx_data = uart_regs[0][7:0];
	assign rx_data_ready = 1'b1;

	uart_rx#
	(
		.CLK_FREQUENCY(CLK_FREQUENCY),
		.BAUD_RATE(BAUD_RATE)
	) uart_rx_inst
	(
		.clk                        (clk_in       ),
		.rst_n                      (rst_n        ),
		.rx_data                    (rx_data      ),
		.rx_data_valid              (rx_data_valid),
		.rx_data_ready              (rx_data_ready),
		.rx_pin                     (rx_pin       )
	);

	uart_tx#
	(
		.CLK_FREQUENCY(CLK_FREQUENCY),
		.BAUD_RATE(BAUD_RATE)
	) uart_tx_inst
	(
		.clk                        (clk_in       ),
		.rst_n                      (rst_n        ),
		.tx_data                    (tx_data  ),
		.tx_data_valid              (tx_data_valid),
		.tx_data_ready              (tx_data_ready),
		.tx_pin                     (tx_pin       )
	);

endmodule
module uart_top #(
	parameter CLK_FREQUENCY = 50,
	parameter BAUD_RATE = 115200
)
(
    input clk_in,
    input rst_n,
    input rx_pin,
    output tx_pin,
	input write_valid,
	input read_valid,
	input [31:0] write_data,
	output reg [31:0] read_data,
	input [31:0] write_address,
	input [31:0] read_address
);


	reg [31:0] uart_regs[0:4];
	wire [7:0]tx_data, rx_data;
	reg tx_data_valid;
	wire tx_data_ready, rx_data_valid, rx_data_ready;

	always @(posedge clk_in or negedge rst_n)
	begin
		if (rst_n == 1'b0) begin
			uart_regs[0] <= 32'h00000000;
			uart_regs[1] <= 32'h00000000;
			uart_regs[2] <= 32'h00000000;
			uart_regs[3] <= 32'h00000000;
			tx_data_valid <= 1'b0;
		end else begin
			if (tx_data_ready == 1'b1 && tx_data_valid == 1'b1) begin
				uart_regs[2][1:0] <= 1'b0;
				tx_data_valid <= 1'b0;
			end else if (uart_regs[2][1:0] == 1'b1 && tx_data_ready == 1'b1) begin
				tx_data_valid <= 1'b1;
			end
			if (rx_data_valid == 1'b1) begin
				uart_regs[1][7:0] <= rx_data;
				uart_regs[2][2:1] <= 1'b1;
			end
			if (write_address[31:4] == 28'h1000000) begin
				if (write_valid == 1'b1) begin
					uart_regs[write_address[1:0]] <= write_data;
				end
			end
			if (read_address[31:4] == 28'h1000000) begin
				if (read_valid == 1'b1) begin
					read_data <= uart_regs[read_address[1:0]];
				end
			end
		end
	end

	assign tx_data = uart_regs[0][7:0];
	assign rx_data_ready = 1'b1;

	uart_rx#
	(
		.CLK_FREQUENCY(CLK_FREQUENCY),
		.BAUD_RATE(BAUD_RATE)
	) uart_rx_inst
	(
		.clk                        (clk_in       ),
		.rst_n                      (rst_n        ),
		.rx_data                    (rx_data      ),
		.rx_data_valid              (rx_data_valid),
		.rx_data_ready              (rx_data_ready),
		.rx_pin                     (rx_pin       )
	);

	uart_tx#
	(
		.CLK_FREQUENCY(CLK_FREQUENCY),
		.BAUD_RATE(BAUD_RATE)
	) uart_tx_inst
	(
		.clk                        (clk_in       ),
		.rst_n                      (rst_n        ),
		.tx_data                    (tx_data  ),
		.tx_data_valid              (tx_data_valid),
		.tx_data_ready              (tx_data_ready),
		.tx_pin                     (tx_pin       )
	);

endmodule