data/full_repos/permissive/531341619/rtl/bram_accumulator.v
1: b"%Error: data/full_repos/permissive/531341619/rtl/bram_accumulator.v:41: Cannot find file containing module: 'simple_dual_port_ram'\n  simple_dual_port_ram\n  ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/531341619/rtl,data/full_repos/permissive/531341619/simple_dual_port_ram\n             data/full_repos/permissive/531341619/rtl,data/full_repos/permissive/531341619/simple_dual_port_ram.v\n             data/full_repos/permissive/531341619/rtl,data/full_repos/permissive/531341619/simple_dual_port_ram.sv\n             simple_dual_port_ram\n             simple_dual_port_ram.v\n             simple_dual_port_ram.sv\n             obj_dir/simple_dual_port_ram\n             obj_dir/simple_dual_port_ram.v\n             obj_dir/simple_dual_port_ram.sv\n%Error: Exiting due to 1 error(s)\n"
module bram_accumulator
#(
  parameter ADDR_WIDTH = 8,
  parameter DATA_WIDTH = 64
)
(
  input wire clk,
  input wire i_rd_en,
  input wire i_wr_en,
  
  input wire [ADDR_WIDTH-1:0] i_rd_addr,  
  input wire [ADDR_WIDTH-1:0] i_wr_addr,
  
  input wire [DATA_WIDTH-1:0] i_data,
  output wire [DATA_WIDTH-1:0] o_data
);

    
  simple_dual_port_ram
  #(
    .ADDR_WIDTH(ADDR_WIDTH),
    .DATA_WIDTH(DATA_WIDTH)
  )simple_dual_port_ram_accumulator(
    .clk(clk), 
    .rd_en(i_rd_en),
    .wr_en(i_wr_en),
    .wr_addr(i_wr_addr),
    .data_i(i_data),
    .rd_addr(i_rd_addr),
    .data_o_r(o_data)
  );
endmodule
module bram_accumulator
#(
  parameter ADDR_WIDTH = 8,
  parameter DATA_WIDTH = 64
)
(
  input wire clk,
  input wire i_rd_en,
  input wire i_wr_en,
  
  input wire [ADDR_WIDTH-1:0] i_rd_addr,  
  input wire [ADDR_WIDTH-1:0] i_wr_addr,
  
  input wire [DATA_WIDTH-1:0] i_data,
  output wire [DATA_WIDTH-1:0] o_data
);


    
  simple_dual_port_ram
  #(
    .ADDR_WIDTH(ADDR_WIDTH),
    .DATA_WIDTH(DATA_WIDTH)
  )simple_dual_port_ram_accumulator(
    .clk(clk), 
    .rd_en(i_rd_en),
    .wr_en(i_wr_en),
    .wr_addr(i_wr_addr),
    .data_i(i_data),
    .rd_addr(i_rd_addr),
    .data_o_r(o_data)
  );
endmodule