data/full_repos/permissive/463549945/Problem_sets/Circuits/Sequential Logic/Latches and Flip-Flops/Mux and DFF_1.v
1: b'%Error: Cannot find file containing module: Logic/Latches\n        ... Looked in:\n             data/full_repos/permissive/463549945/Problem_sets/Circuits/Sequential/Logic/Latches\n             data/full_repos/permissive/463549945/Problem_sets/Circuits/Sequential/Logic/Latches.v\n             data/full_repos/permissive/463549945/Problem_sets/Circuits/Sequential/Logic/Latches.sv\n             Logic/Latches\n             Logic/Latches.v\n             Logic/Latches.sv\n             obj_dir/Logic/Latches\n             obj_dir/Logic/Latches.v\n             obj_dir/Logic/Latches.sv\n%Error: Cannot find file containing module: and\n%Error: Cannot find file containing module: Flip-Flops,data/full_repos/permissive/463549945\n%Error: Cannot find file containing module: data/full_repos/permissive/463549945/Problem_sets/Circuits/Sequential\n%Error: Cannot find file containing module: Flip-Flops/Mux\n%Error: Cannot find file containing module: DFF_1.v\n%Error: Exiting due to 6 error(s)\n'
module top_module (
    input clk,
    input L,
    input r_in,
    input q_in,
    output reg Q);

    wire temp;

    assign temp = L ? r_in : q_in;

    always @ (posedge clk )
        begin
           Q <= temp; 
        end

endmodule
module top_module (
    input clk,
    input L,
    input r_in,
    input q_in,
    output reg Q);


    wire temp;

    assign temp = L ? r_in : q_in;

    always @ (posedge clk )
        begin
           Q <= temp; 
        end

endmodule