data/full_repos/permissive/466874195/verilog/test/tb_gen_mask.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/466874195/verilog/test/tb_gen_mask.sv:30: Unsupported: Ignoring delay on this delayed statement.\n    always #hperiod clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/466874195/verilog/test/tb_gen_mask.sv:33: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("tb_gen_mask.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/466874195/verilog/test/tb_gen_mask.sv:34: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, tb_gen_mask);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/466874195/verilog/test/tb_gen_mask.sv:42: Unsupported: Ignoring delay on this delayed statement.\n        #period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/466874195/verilog/test/tb_gen_mask.sv:43: Unsupported: Ignoring delay on this delayed statement.\n        #period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/466874195/verilog/test/tb_gen_mask.sv:44: Unsupported: Ignoring delay on this delayed statement.\n        #period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/466874195/verilog/test/tb_gen_mask.sv:45: Unsupported: Ignoring delay on this delayed statement.\n        #period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/466874195/verilog/test/tb_gen_mask.sv:49: Unsupported: Ignoring delay on this delayed statement.\n        #period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/466874195/verilog/test/tb_gen_mask.sv:50: Unsupported: Ignoring delay on this delayed statement.\n        #period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/466874195/verilog/test/tb_gen_mask.sv:51: Unsupported: Ignoring delay on this delayed statement.\n        #period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/466874195/verilog/test/tb_gen_mask.sv:52: Unsupported: Ignoring delay on this delayed statement.\n        #period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/466874195/verilog/test/tb_gen_mask.sv:59: Unsupported: Ignoring delay on this delayed statement.\n            #period;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/466874195/verilog/test/tb_gen_mask.sv:63: Unsupported: Ignoring delay on this delayed statement.\n        #period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/466874195/verilog/test/tb_gen_mask.sv:64: Unsupported: Ignoring delay on this delayed statement.\n        #period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/466874195/verilog/test/tb_gen_mask.sv:65: Unsupported: Ignoring delay on this delayed statement.\n        #period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/466874195/verilog/test/tb_gen_mask.sv:66: Unsupported: Ignoring delay on this delayed statement.\n        #period;\n        ^\n%Error: Exiting due to 2 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_gen_mask;

    localparam period = 10;
    localparam hperiod = period/2;

    localparam SEQ_WIDTH = 20;

    integer ii;

    reg clk;
    reg rst;
    
    reg [6:0] i_offset;
    reg [SEQ_WIDTH-1:0] o_mask;

    gen_mask # (
        .SEQ_WIDTH(SEQ_WIDTH)
    ) UUT (
        .clk(clk),
        .rst(rst),

        .i_offset(i_offset),
        .o_mask(o_mask)
    );

    always #hperiod clk = ~clk;

    initial begin
        $dumpfile("tb_gen_mask.vcd");
        $dumpvars(0, tb_gen_mask);

        clk = 1'b0;
        rst = 1'b0;


        i_offset = 6'd0;

        #period;
        #period;
        #period;
        #period;

        rst = 1'b1;

        #period;
        #period;
        #period;
        #period;

        rst = 1'b0;

        for (ii = 0; ii < 128; ii++) begin
            i_offset = ii;

            #period;
        end;


        #period;
        #period;
        #period;
        #period;

        $finish();
    end

endmodule
module tb_gen_mask;


    localparam period = 10;
    localparam hperiod = period/2;

    localparam SEQ_WIDTH = 20;

    integer ii;

    reg clk;
    reg rst;
    
    reg [6:0] i_offset;
    reg [SEQ_WIDTH-1:0] o_mask;

    gen_mask # (
        .SEQ_WIDTH(SEQ_WIDTH)
    ) UUT (
        .clk(clk),
        .rst(rst),

        .i_offset(i_offset),
        .o_mask(o_mask)
    );

    always #hperiod clk = ~clk;

    initial begin
        $dumpfile("tb_gen_mask.vcd");
        $dumpvars(0, tb_gen_mask);

        clk = 1'b0;
        rst = 1'b0;


        i_offset = 6'd0;

        #period;
        #period;
        #period;
        #period;

        rst = 1'b1;

        #period;
        #period;
        #period;
        #period;

        rst = 1'b0;

        for (ii = 0; ii < 128; ii++) begin
            i_offset = ii;

            #period;
        end;


        #period;
        #period;
        #period;
        #period;

        $finish();
    end

endmodule