data/full_repos/permissive/443770883/lab6/Lab5-Student copy/reg_alu.v
1: b'%Error: Cannot find file containing module: copy,data/full_repos/permissive/443770883\n        ... Looked in:\n             data/full_repos/permissive/443770883/lab6/Lab5-Student/copy,data/full_repos/permissive/443770883\n             data/full_repos/permissive/443770883/lab6/Lab5-Student/copy,data/full_repos/permissive/443770883.v\n             data/full_repos/permissive/443770883/lab6/Lab5-Student/copy,data/full_repos/permissive/443770883.sv\n             copy,data/full_repos/permissive/443770883\n             copy,data/full_repos/permissive/443770883.v\n             copy,data/full_repos/permissive/443770883.sv\n             obj_dir/copy,data/full_repos/permissive/443770883\n             obj_dir/copy,data/full_repos/permissive/443770883.v\n             obj_dir/copy,data/full_repos/permissive/443770883.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/443770883/lab6/Lab5-Student\n%Error: Cannot find file containing module: copy/reg_alu.v\n%Error: Exiting due to 3 error(s)\n'
module reg_file (input wire clk, reset, wr, input wire [2:0] rd_addr_a, rd_addr_b, wr_addr, input wire [15:0] d_in, output wire [15:0] d_out_a, d_out_b);


	wire [0:7]load;
	wire [0:15]r0,r1,r2,r3,r4,r5,r6,r7;


	demux8 d0(wr,wr_addr[2],wr_addr[1],wr_addr[0],load);

	dfrl16 reg0(clk,reset,load[0],d_in,r0);
	dfrl16 reg1(clk,reset,load[1],d_in,r1);
	dfrl16 reg2(clk,reset,load[2],d_in,r2);
	dfrl16 reg3(clk,reset,load[3],d_in,r3);
	dfrl16 reg4(clk,reset,load[4],d_in,r4);
	dfrl16 reg5(clk,reset,load[5],d_in,r5);
	dfrl16 reg6(clk,reset,load[6],d_in,r6);
	dfrl16 reg7(clk,reset,load[7],d_in,r7);

	mux128_16 m0(r0,r1,r2,r3,r4,r5,r6,r7,rd_addr_a[0],rd_addr_a[1],rd_addr_a[2],d_out_a);
	mux128_16 m1(r0,r1,r2,r3,r4,r5,r6,r7,rd_addr_b[0],rd_addr_b[1],rd_addr_b[2],d_out_b);

endmodule
module reg_file (input wire clk, reset, wr, input wire [2:0] rd_addr_a, rd_addr_b, wr_addr, input wire [15:0] d_in, output wire [15:0] d_out_a, d_out_b);



	wire [0:7]load;
	wire [0:15]r0,r1,r2,r3,r4,r5,r6,r7;


	demux8 d0(wr,wr_addr[2],wr_addr[1],wr_addr[0],load);

	dfrl16 reg0(clk,reset,load[0],d_in,r0);
	dfrl16 reg1(clk,reset,load[1],d_in,r1);
	dfrl16 reg2(clk,reset,load[2],d_in,r2);
	dfrl16 reg3(clk,reset,load[3],d_in,r3);
	dfrl16 reg4(clk,reset,load[4],d_in,r4);
	dfrl16 reg5(clk,reset,load[5],d_in,r5);
	dfrl16 reg6(clk,reset,load[6],d_in,r6);
	dfrl16 reg7(clk,reset,load[7],d_in,r7);

	mux128_16 m0(r0,r1,r2,r3,r4,r5,r6,r7,rd_addr_a[0],rd_addr_a[1],rd_addr_a[2],d_out_a);
	mux128_16 m1(r0,r1,r2,r3,r4,r5,r6,r7,rd_addr_b[0],rd_addr_b[1],rd_addr_b[2],d_out_b);

endmodule