data/full_repos/permissive/42434302/ivltests/andnot1.v
1: b'%Error: data/full_repos/permissive/42434302/ivltests/andnot1.v:29: syntax error, unexpected ref, expecting IDENTIFIER or \'=\' or do or final\n   reg      ref;\n            ^~~\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/andnot1.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #1 if (c != d) begin\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module main;

   reg a, b, c;

   wire d = a & !b;
   reg [2:0] tmp;
   reg	     ref;
   initial begin

      for (tmp = 0 ;  tmp < 4 ;  tmp = tmp + 1) begin
	 a = tmp[0];
	 b = tmp[1];
	 c = a & ~b;
	 #1 if (c != d) begin
	    $display("FAILED -- a=%b, b=%b, c=%b, d=%b",
		     a, b, c, d);
	    $finish;
	 end
      end

      $display("PASSED");
   end

endmodule
module main;


   reg a, b, c;

   wire d = a & !b;
   reg [2:0] tmp;
   reg	     ref;
   initial begin

      for (tmp = 0 ;  tmp < 4 ;  tmp = tmp + 1) begin
	 a = tmp[0];
	 b = tmp[1];
	 c = a & ~b;
	 #1 if (c != d) begin
	    $display("FAILED -- a=%b, b=%b, c=%b, d=%b",
		     a, b, c, d);
	    $finish;
	 end
      end

      $display("PASSED");
   end

endmodule