data/full_repos/permissive/524616929/src/core/biriscv_exec.v
1: b'%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:62: Cannot find include file: biriscv_defs.v\n`include "biriscv_defs.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/524616929/src/core,data/full_repos/permissive/524616929/biriscv_defs.v\n             data/full_repos/permissive/524616929/src/core,data/full_repos/permissive/524616929/biriscv_defs.v.v\n             data/full_repos/permissive/524616929/src/core,data/full_repos/permissive/524616929/biriscv_defs.v.sv\n             biriscv_defs.v\n             biriscv_defs.v.v\n             biriscv_defs.v.sv\n             obj_dir/biriscv_defs.v\n             obj_dir/biriscv_defs.v.v\n             obj_dir/biriscv_defs.v.sv\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:91: Define or directive not defined: \'`ALU_NONE\'\n    alu_func_r     = `ALU_NONE;\n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:91: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    alu_func_r     = `ALU_NONE;\n                              ^\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:95: Define or directive not defined: \'`INST_ADD_MASK\'\n    if ((opcode_opcode_i & `INST_ADD_MASK) == `INST_ADD)  \n                           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:95: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    if ((opcode_opcode_i & `INST_ADD_MASK) == `INST_ADD)  \n                                         ^\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:95: Define or directive not defined: \'`INST_ADD\'\n    if ((opcode_opcode_i & `INST_ADD_MASK) == `INST_ADD)  \n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:97: Define or directive not defined: \'`ALU_ADD\'\n        alu_func_r     = `ALU_ADD;\n                         ^~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:101: syntax error, unexpected else\n    else if ((opcode_opcode_i & `INST_AND_MASK) == `INST_AND)  \n    ^~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:101: Define or directive not defined: \'`INST_AND_MASK\'\n    else if ((opcode_opcode_i & `INST_AND_MASK) == `INST_AND)  \n                                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:101: Define or directive not defined: \'`INST_AND\'\n    else if ((opcode_opcode_i & `INST_AND_MASK) == `INST_AND)  \n                                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:103: Define or directive not defined: \'`ALU_AND\'\n        alu_func_r     = `ALU_AND;\n                         ^~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:107: Define or directive not defined: \'`INST_OR_MASK\'\n    else if ((opcode_opcode_i & `INST_OR_MASK) == `INST_OR)  \n                                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:107: Define or directive not defined: \'`INST_OR\'\n    else if ((opcode_opcode_i & `INST_OR_MASK) == `INST_OR)  \n                                                  ^~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:109: Define or directive not defined: \'`ALU_OR\'\n        alu_func_r     = `ALU_OR;\n                         ^~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:113: Define or directive not defined: \'`INST_SLL_MASK\'\n    else if ((opcode_opcode_i & `INST_SLL_MASK) == `INST_SLL)  \n                                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:113: Define or directive not defined: \'`INST_SLL\'\n    else if ((opcode_opcode_i & `INST_SLL_MASK) == `INST_SLL)  \n                                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:115: Define or directive not defined: \'`ALU_SHIFTL\'\n        alu_func_r     = `ALU_SHIFTL;\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:119: Define or directive not defined: \'`INST_SRA_MASK\'\n    else if ((opcode_opcode_i & `INST_SRA_MASK) == `INST_SRA)  \n                                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:119: Define or directive not defined: \'`INST_SRA\'\n    else if ((opcode_opcode_i & `INST_SRA_MASK) == `INST_SRA)  \n                                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:121: Define or directive not defined: \'`ALU_SHIFTR_ARITH\'\n        alu_func_r     = `ALU_SHIFTR_ARITH;\n                         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:125: Define or directive not defined: \'`INST_SRL_MASK\'\n    else if ((opcode_opcode_i & `INST_SRL_MASK) == `INST_SRL)  \n                                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:125: Define or directive not defined: \'`INST_SRL\'\n    else if ((opcode_opcode_i & `INST_SRL_MASK) == `INST_SRL)  \n                                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:127: Define or directive not defined: \'`ALU_SHIFTR\'\n        alu_func_r     = `ALU_SHIFTR;\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:131: Define or directive not defined: \'`INST_SUB_MASK\'\n    else if ((opcode_opcode_i & `INST_SUB_MASK) == `INST_SUB)  \n                                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:131: Define or directive not defined: \'`INST_SUB\'\n    else if ((opcode_opcode_i & `INST_SUB_MASK) == `INST_SUB)  \n                                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:133: Define or directive not defined: \'`ALU_SUB\'\n        alu_func_r     = `ALU_SUB;\n                         ^~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:137: Define or directive not defined: \'`INST_XOR_MASK\'\n    else if ((opcode_opcode_i & `INST_XOR_MASK) == `INST_XOR)  \n                                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:137: Define or directive not defined: \'`INST_XOR\'\n    else if ((opcode_opcode_i & `INST_XOR_MASK) == `INST_XOR)  \n                                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:139: Define or directive not defined: \'`ALU_XOR\'\n        alu_func_r     = `ALU_XOR;\n                         ^~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:143: Define or directive not defined: \'`INST_SLT_MASK\'\n    else if ((opcode_opcode_i & `INST_SLT_MASK) == `INST_SLT)  \n                                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:143: Define or directive not defined: \'`INST_SLT\'\n    else if ((opcode_opcode_i & `INST_SLT_MASK) == `INST_SLT)  \n                                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:145: Define or directive not defined: \'`ALU_LESS_THAN_SIGNED\'\n        alu_func_r     = `ALU_LESS_THAN_SIGNED;\n                         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:149: Define or directive not defined: \'`INST_SLTU_MASK\'\n    else if ((opcode_opcode_i & `INST_SLTU_MASK) == `INST_SLTU)  \n                                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:149: Define or directive not defined: \'`INST_SLTU\'\n    else if ((opcode_opcode_i & `INST_SLTU_MASK) == `INST_SLTU)  \n                                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:151: Define or directive not defined: \'`ALU_LESS_THAN\'\n        alu_func_r     = `ALU_LESS_THAN;\n                         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:155: Define or directive not defined: \'`INST_ADDI_MASK\'\n    else if ((opcode_opcode_i & `INST_ADDI_MASK) == `INST_ADDI)  \n                                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:155: Define or directive not defined: \'`INST_ADDI\'\n    else if ((opcode_opcode_i & `INST_ADDI_MASK) == `INST_ADDI)  \n                                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:157: Define or directive not defined: \'`ALU_ADD\'\n        alu_func_r     = `ALU_ADD;\n                         ^~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:161: Define or directive not defined: \'`INST_ANDI_MASK\'\n    else if ((opcode_opcode_i & `INST_ANDI_MASK) == `INST_ANDI)  \n                                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:161: Define or directive not defined: \'`INST_ANDI\'\n    else if ((opcode_opcode_i & `INST_ANDI_MASK) == `INST_ANDI)  \n                                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:163: Define or directive not defined: \'`ALU_AND\'\n        alu_func_r     = `ALU_AND;\n                         ^~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:167: Define or directive not defined: \'`INST_SLTI_MASK\'\n    else if ((opcode_opcode_i & `INST_SLTI_MASK) == `INST_SLTI)  \n                                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:167: Define or directive not defined: \'`INST_SLTI\'\n    else if ((opcode_opcode_i & `INST_SLTI_MASK) == `INST_SLTI)  \n                                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:169: Define or directive not defined: \'`ALU_LESS_THAN_SIGNED\'\n        alu_func_r     = `ALU_LESS_THAN_SIGNED;\n                         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:173: Define or directive not defined: \'`INST_SLTIU_MASK\'\n    else if ((opcode_opcode_i & `INST_SLTIU_MASK) == `INST_SLTIU)  \n                                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:173: Define or directive not defined: \'`INST_SLTIU\'\n    else if ((opcode_opcode_i & `INST_SLTIU_MASK) == `INST_SLTIU)  \n                                                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:175: Define or directive not defined: \'`ALU_LESS_THAN\'\n        alu_func_r     = `ALU_LESS_THAN;\n                         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:179: Define or directive not defined: \'`INST_ORI_MASK\'\n    else if ((opcode_opcode_i & `INST_ORI_MASK) == `INST_ORI)  \n                                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:179: Define or directive not defined: \'`INST_ORI\'\n    else if ((opcode_opcode_i & `INST_ORI_MASK) == `INST_ORI)  \n                                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/524616929/src/core/biriscv_exec.v:181: Define or directive not defined: \'`ALU_OR\'\n        alu_func_r     = `ALU_OR;\n                         ^~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module biriscv_exec
(

     input           clk_i
    ,input           rst_i
    ,input           opcode_valid_i
    ,input  [ 31:0]  opcode_opcode_i
    ,input  [ 31:0]  opcode_pc_i
    ,input           opcode_invalid_i
    ,input  [  4:0]  opcode_rd_idx_i
    ,input  [  4:0]  opcode_ra_idx_i
    ,input  [  4:0]  opcode_rb_idx_i
    ,input  [ 31:0]  opcode_ra_operand_i
    ,input  [ 31:0]  opcode_rb_operand_i
    ,input           hold_i


    ,output          branch_request_o
    ,output          branch_is_taken_o
    ,output          branch_is_not_taken_o
    ,output [ 31:0]  branch_source_o
    ,output          branch_is_call_o
    ,output          branch_is_ret_o
    ,output          branch_is_jmp_o
    ,output [ 31:0]  branch_pc_o
    ,output          branch_d_request_o
    ,output [ 31:0]  branch_d_pc_o
    ,output [  1:0]  branch_d_priv_o
    ,output [ 31:0]  writeback_value_o
);






`include "biriscv_defs.v"




reg [31:0]  imm20_r;
reg [31:0]  imm12_r;
reg [31:0]  bimm_r;
reg [31:0]  jimm20_r;
reg [4:0]   shamt_r;

always @ *
begin
    imm20_r     = {opcode_opcode_i[31:12], 12'b0};
    imm12_r     = {{20{opcode_opcode_i[31]}}, opcode_opcode_i[31:20]};
    bimm_r      = {{19{opcode_opcode_i[31]}}, opcode_opcode_i[31], opcode_opcode_i[7], opcode_opcode_i[30:25], opcode_opcode_i[11:8], 1'b0};
    jimm20_r    = {{12{opcode_opcode_i[31]}}, opcode_opcode_i[19:12], opcode_opcode_i[20], opcode_opcode_i[30:25], opcode_opcode_i[24:21], 1'b0};
    shamt_r     = opcode_opcode_i[24:20];
end




reg [3:0]  alu_func_r;
reg [31:0] alu_input_a_r;
reg [31:0] alu_input_b_r;

always @ *
begin
    alu_func_r     = `ALU_NONE;
    alu_input_a_r  = 32'b0;
    alu_input_b_r  = 32'b0;

    if ((opcode_opcode_i & `INST_ADD_MASK) == `INST_ADD)
    begin
        alu_func_r     = `ALU_ADD;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
    end
    else if ((opcode_opcode_i & `INST_AND_MASK) == `INST_AND)
    begin
        alu_func_r     = `ALU_AND;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
    end
    else if ((opcode_opcode_i & `INST_OR_MASK) == `INST_OR)
    begin
        alu_func_r     = `ALU_OR;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
    end
    else if ((opcode_opcode_i & `INST_SLL_MASK) == `INST_SLL)
    begin
        alu_func_r     = `ALU_SHIFTL;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
    end
    else if ((opcode_opcode_i & `INST_SRA_MASK) == `INST_SRA)
    begin
        alu_func_r     = `ALU_SHIFTR_ARITH;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
    end
    else if ((opcode_opcode_i & `INST_SRL_MASK) == `INST_SRL)
    begin
        alu_func_r     = `ALU_SHIFTR;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
    end
    else if ((opcode_opcode_i & `INST_SUB_MASK) == `INST_SUB)
    begin
        alu_func_r     = `ALU_SUB;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
    end
    else if ((opcode_opcode_i & `INST_XOR_MASK) == `INST_XOR)
    begin
        alu_func_r     = `ALU_XOR;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
    end
    else if ((opcode_opcode_i & `INST_SLT_MASK) == `INST_SLT)
    begin
        alu_func_r     = `ALU_LESS_THAN_SIGNED;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
    end
    else if ((opcode_opcode_i & `INST_SLTU_MASK) == `INST_SLTU)
    begin
        alu_func_r     = `ALU_LESS_THAN;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
    end
    else if ((opcode_opcode_i & `INST_ADDI_MASK) == `INST_ADDI)
    begin
        alu_func_r     = `ALU_ADD;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = imm12_r;
    end
    else if ((opcode_opcode_i & `INST_ANDI_MASK) == `INST_ANDI)
    begin
        alu_func_r     = `ALU_AND;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = imm12_r;
    end
    else if ((opcode_opcode_i & `INST_SLTI_MASK) == `INST_SLTI)
    begin
        alu_func_r     = `ALU_LESS_THAN_SIGNED;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = imm12_r;
    end
    else if ((opcode_opcode_i & `INST_SLTIU_MASK) == `INST_SLTIU)
    begin
        alu_func_r     = `ALU_LESS_THAN;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = imm12_r;
    end
    else if ((opcode_opcode_i & `INST_ORI_MASK) == `INST_ORI)
    begin
        alu_func_r     = `ALU_OR;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = imm12_r;
    end
    else if ((opcode_opcode_i & `INST_XORI_MASK) == `INST_XORI)
    begin
        alu_func_r     = `ALU_XOR;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = imm12_r;
    end
    else if ((opcode_opcode_i & `INST_SLLI_MASK) == `INST_SLLI)
    begin
        alu_func_r     = `ALU_SHIFTL;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = {27'b0, shamt_r};
    end
    else if ((opcode_opcode_i & `INST_SRLI_MASK) == `INST_SRLI)
    begin
        alu_func_r     = `ALU_SHIFTR;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = {27'b0, shamt_r};
    end
    else if ((opcode_opcode_i & `INST_SRAI_MASK) == `INST_SRAI)
    begin
        alu_func_r     = `ALU_SHIFTR_ARITH;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = {27'b0, shamt_r};
    end
    else if ((opcode_opcode_i & `INST_LUI_MASK) == `INST_LUI)
    begin
        alu_input_a_r  = imm20_r;
    end
    else if ((opcode_opcode_i & `INST_AUIPC_MASK) == `INST_AUIPC)
    begin
        alu_func_r     = `ALU_ADD;
        alu_input_a_r  = opcode_pc_i;
        alu_input_b_r  = imm20_r;
    end     
    else if (((opcode_opcode_i & `INST_JAL_MASK) == `INST_JAL) || ((opcode_opcode_i & `INST_JALR_MASK) == `INST_JALR))
    begin
        alu_func_r     = `ALU_ADD;
        alu_input_a_r  = opcode_pc_i;
        alu_input_b_r  = 32'd4;
    end
end





wire [31:0]  alu_p_w;
biriscv_alu
u_alu
(
    .alu_op_i(alu_func_r),
    .alu_a_i(alu_input_a_r),
    .alu_b_i(alu_input_b_r),
    .alu_p_o(alu_p_w)
);




reg [31:0] result_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    result_q  <= 32'b0;
else if (~hold_i)
    result_q <= alu_p_w;

assign writeback_value_o  = result_q;




reg        branch_r;
reg        branch_taken_r;
reg [31:0] branch_target_r;
reg        branch_call_r;
reg        branch_ret_r;
reg        branch_jmp_r;

always @ *
begin
    branch_r        = 1'b0;
    branch_taken_r  = 1'b0;
    branch_call_r   = 1'b0;
    branch_ret_r    = 1'b0;
    branch_jmp_r    = 1'b0;


    branch_target_r = opcode_pc_i + bimm_r;

    if ((opcode_opcode_i & `INST_JAL_MASK) == `INST_JAL)
    begin
        branch_r        = 1'b1;
        branch_taken_r  = 1'b1;
        branch_target_r = opcode_pc_i + jimm20_r;
        branch_call_r   = (opcode_rd_idx_i == 5'd1);
        branch_jmp_r    = 1'b1;
    end
    else if ((opcode_opcode_i & `INST_JALR_MASK) == `INST_JALR)
    begin
        branch_r            = 1'b1;
        branch_taken_r      = 1'b1;
        branch_target_r     = opcode_ra_operand_i + imm12_r;
        branch_target_r[0]  = 1'b0;
        branch_ret_r        = (opcode_ra_idx_i == 5'd1 && imm12_r[11:0] == 12'b0);
        branch_call_r       = ~branch_ret_r && (opcode_rd_idx_i == 5'd1);
        branch_jmp_r        = ~(branch_call_r | branch_ret_r);
    end
    else if ((opcode_opcode_i & `INST_BEQ_MASK) == `INST_BEQ)
    begin
        branch_r      = 1'b1;
        branch_taken_r= (opcode_ra_operand_i == opcode_rb_operand_i);
    end
    else if ((opcode_opcode_i & `INST_BNE_MASK) == `INST_BNE)
    begin
        branch_r      = 1'b1;    
        branch_taken_r= (opcode_ra_operand_i != opcode_rb_operand_i);
    end
    else if ((opcode_opcode_i & `INST_BLT_MASK) == `INST_BLT)
    begin
        branch_r      = 1'b1;

        branch_taken_r= {~opcode_ra_operand_i[31],opcode_ra_operand_i[30:0]}<
                        {~opcode_rb_operand_i[31],opcode_rb_operand_i[30:0]};

    end
    else if ((opcode_opcode_i & `INST_BGE_MASK) == `INST_BGE)
    begin
        branch_r      = 1'b1;    

        branch_taken_r= ({~opcode_ra_operand_i[31],opcode_ra_operand_i[30:0]}>
                        {~opcode_rb_operand_i[31],opcode_rb_operand_i[30:0]})|
                        (opcode_ra_operand_i == opcode_rb_operand_i);

    end
    else if ((opcode_opcode_i & `INST_BLTU_MASK) == `INST_BLTU)
    begin
        branch_r      = 1'b1;    
        branch_taken_r= (opcode_ra_operand_i < opcode_rb_operand_i);
    end
    else if ((opcode_opcode_i & `INST_BGEU_MASK) == `INST_BGEU)
    begin
        branch_r      = 1'b1;
        branch_taken_r= (opcode_ra_operand_i >= opcode_rb_operand_i);
    end
end

reg        branch_taken_q;
reg        branch_ntaken_q;
reg [31:0] pc_x_q;
reg [31:0] pc_m_q;
reg        branch_call_q;
reg        branch_ret_q;
reg        branch_jmp_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
    branch_taken_q   <= 1'b0;
    branch_ntaken_q  <= 1'b0;
    pc_x_q           <= 32'b0;
    pc_m_q           <= 32'b0;
    branch_call_q    <= 1'b0;
    branch_ret_q     <= 1'b0;
    branch_jmp_q     <= 1'b0;
end
else if (opcode_valid_i)
begin
    branch_taken_q   <= branch_r && opcode_valid_i & branch_taken_r;
    branch_ntaken_q  <= branch_r && opcode_valid_i & ~branch_taken_r;
    pc_x_q           <= branch_taken_r ? branch_target_r : opcode_pc_i + 32'd4;
    branch_call_q    <= branch_r && opcode_valid_i && branch_call_r;
    branch_ret_q     <= branch_r && opcode_valid_i && branch_ret_r;
    branch_jmp_q     <= branch_r && opcode_valid_i && branch_jmp_r;
    pc_m_q           <= opcode_pc_i;
end

assign branch_request_o   = branch_taken_q | branch_ntaken_q;
assign branch_is_taken_o  = branch_taken_q;
assign branch_is_not_taken_o = branch_ntaken_q;
assign branch_source_o    = pc_m_q;
assign branch_pc_o        = pc_x_q;
assign branch_is_call_o   = branch_call_q;
assign branch_is_ret_o    = branch_ret_q;
assign branch_is_jmp_o    = branch_jmp_q;

assign branch_d_request_o = (branch_r && opcode_valid_i && branch_taken_r);
assign branch_d_pc_o      = branch_target_r;
assign branch_d_priv_o    = 2'b0;

endmodule
module biriscv_exec
(

     input           clk_i
    ,input           rst_i
    ,input           opcode_valid_i
    ,input  [ 31:0]  opcode_opcode_i
    ,input  [ 31:0]  opcode_pc_i
    ,input           opcode_invalid_i
    ,input  [  4:0]  opcode_rd_idx_i
    ,input  [  4:0]  opcode_ra_idx_i
    ,input  [  4:0]  opcode_rb_idx_i
    ,input  [ 31:0]  opcode_ra_operand_i
    ,input  [ 31:0]  opcode_rb_operand_i
    ,input           hold_i


    ,output          branch_request_o
    ,output          branch_is_taken_o
    ,output          branch_is_not_taken_o
    ,output [ 31:0]  branch_source_o
    ,output          branch_is_call_o
    ,output          branch_is_ret_o
    ,output          branch_is_jmp_o
    ,output [ 31:0]  branch_pc_o
    ,output          branch_d_request_o
    ,output [ 31:0]  branch_d_pc_o
    ,output [  1:0]  branch_d_priv_o
    ,output [ 31:0]  writeback_value_o
);







`include "biriscv_defs.v"




reg [31:0]  imm20_r;
reg [31:0]  imm12_r;
reg [31:0]  bimm_r;
reg [31:0]  jimm20_r;
reg [4:0]   shamt_r;

always @ *
begin
    imm20_r     = {opcode_opcode_i[31:12], 12'b0};
    imm12_r     = {{20{opcode_opcode_i[31]}}, opcode_opcode_i[31:20]};
    bimm_r      = {{19{opcode_opcode_i[31]}}, opcode_opcode_i[31], opcode_opcode_i[7], opcode_opcode_i[30:25], opcode_opcode_i[11:8], 1'b0};
    jimm20_r    = {{12{opcode_opcode_i[31]}}, opcode_opcode_i[19:12], opcode_opcode_i[20], opcode_opcode_i[30:25], opcode_opcode_i[24:21], 1'b0};
    shamt_r     = opcode_opcode_i[24:20];
end




reg [3:0]  alu_func_r;
reg [31:0] alu_input_a_r;
reg [31:0] alu_input_b_r;

always @ *
begin
    alu_func_r     = `ALU_NONE;
    alu_input_a_r  = 32'b0;
    alu_input_b_r  = 32'b0;

    if ((opcode_opcode_i & `INST_ADD_MASK) == `INST_ADD)
    begin
        alu_func_r     = `ALU_ADD;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
    end
    else if ((opcode_opcode_i & `INST_AND_MASK) == `INST_AND)
    begin
        alu_func_r     = `ALU_AND;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
    end
    else if ((opcode_opcode_i & `INST_OR_MASK) == `INST_OR)
    begin
        alu_func_r     = `ALU_OR;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
    end
    else if ((opcode_opcode_i & `INST_SLL_MASK) == `INST_SLL)
    begin
        alu_func_r     = `ALU_SHIFTL;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
    end
    else if ((opcode_opcode_i & `INST_SRA_MASK) == `INST_SRA)
    begin
        alu_func_r     = `ALU_SHIFTR_ARITH;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
    end
    else if ((opcode_opcode_i & `INST_SRL_MASK) == `INST_SRL)
    begin
        alu_func_r     = `ALU_SHIFTR;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
    end
    else if ((opcode_opcode_i & `INST_SUB_MASK) == `INST_SUB)
    begin
        alu_func_r     = `ALU_SUB;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
    end
    else if ((opcode_opcode_i & `INST_XOR_MASK) == `INST_XOR)
    begin
        alu_func_r     = `ALU_XOR;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
    end
    else if ((opcode_opcode_i & `INST_SLT_MASK) == `INST_SLT)
    begin
        alu_func_r     = `ALU_LESS_THAN_SIGNED;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
    end
    else if ((opcode_opcode_i & `INST_SLTU_MASK) == `INST_SLTU)
    begin
        alu_func_r     = `ALU_LESS_THAN;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = opcode_rb_operand_i;
    end
    else if ((opcode_opcode_i & `INST_ADDI_MASK) == `INST_ADDI)
    begin
        alu_func_r     = `ALU_ADD;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = imm12_r;
    end
    else if ((opcode_opcode_i & `INST_ANDI_MASK) == `INST_ANDI)
    begin
        alu_func_r     = `ALU_AND;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = imm12_r;
    end
    else if ((opcode_opcode_i & `INST_SLTI_MASK) == `INST_SLTI)
    begin
        alu_func_r     = `ALU_LESS_THAN_SIGNED;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = imm12_r;
    end
    else if ((opcode_opcode_i & `INST_SLTIU_MASK) == `INST_SLTIU)
    begin
        alu_func_r     = `ALU_LESS_THAN;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = imm12_r;
    end
    else if ((opcode_opcode_i & `INST_ORI_MASK) == `INST_ORI)
    begin
        alu_func_r     = `ALU_OR;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = imm12_r;
    end
    else if ((opcode_opcode_i & `INST_XORI_MASK) == `INST_XORI)
    begin
        alu_func_r     = `ALU_XOR;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = imm12_r;
    end
    else if ((opcode_opcode_i & `INST_SLLI_MASK) == `INST_SLLI)
    begin
        alu_func_r     = `ALU_SHIFTL;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = {27'b0, shamt_r};
    end
    else if ((opcode_opcode_i & `INST_SRLI_MASK) == `INST_SRLI)
    begin
        alu_func_r     = `ALU_SHIFTR;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = {27'b0, shamt_r};
    end
    else if ((opcode_opcode_i & `INST_SRAI_MASK) == `INST_SRAI)
    begin
        alu_func_r     = `ALU_SHIFTR_ARITH;
        alu_input_a_r  = opcode_ra_operand_i;
        alu_input_b_r  = {27'b0, shamt_r};
    end
    else if ((opcode_opcode_i & `INST_LUI_MASK) == `INST_LUI)
    begin
        alu_input_a_r  = imm20_r;
    end
    else if ((opcode_opcode_i & `INST_AUIPC_MASK) == `INST_AUIPC)
    begin
        alu_func_r     = `ALU_ADD;
        alu_input_a_r  = opcode_pc_i;
        alu_input_b_r  = imm20_r;
    end     
    else if (((opcode_opcode_i & `INST_JAL_MASK) == `INST_JAL) || ((opcode_opcode_i & `INST_JALR_MASK) == `INST_JALR))
    begin
        alu_func_r     = `ALU_ADD;
        alu_input_a_r  = opcode_pc_i;
        alu_input_b_r  = 32'd4;
    end
end





wire [31:0]  alu_p_w;
biriscv_alu
u_alu
(
    .alu_op_i(alu_func_r),
    .alu_a_i(alu_input_a_r),
    .alu_b_i(alu_input_b_r),
    .alu_p_o(alu_p_w)
);




reg [31:0] result_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
    result_q  <= 32'b0;
else if (~hold_i)
    result_q <= alu_p_w;

assign writeback_value_o  = result_q;




reg        branch_r;
reg        branch_taken_r;
reg [31:0] branch_target_r;
reg        branch_call_r;
reg        branch_ret_r;
reg        branch_jmp_r;

always @ *
begin
    branch_r        = 1'b0;
    branch_taken_r  = 1'b0;
    branch_call_r   = 1'b0;
    branch_ret_r    = 1'b0;
    branch_jmp_r    = 1'b0;


    branch_target_r = opcode_pc_i + bimm_r;

    if ((opcode_opcode_i & `INST_JAL_MASK) == `INST_JAL)
    begin
        branch_r        = 1'b1;
        branch_taken_r  = 1'b1;
        branch_target_r = opcode_pc_i + jimm20_r;
        branch_call_r   = (opcode_rd_idx_i == 5'd1);
        branch_jmp_r    = 1'b1;
    end
    else if ((opcode_opcode_i & `INST_JALR_MASK) == `INST_JALR)
    begin
        branch_r            = 1'b1;
        branch_taken_r      = 1'b1;
        branch_target_r     = opcode_ra_operand_i + imm12_r;
        branch_target_r[0]  = 1'b0;
        branch_ret_r        = (opcode_ra_idx_i == 5'd1 && imm12_r[11:0] == 12'b0);
        branch_call_r       = ~branch_ret_r && (opcode_rd_idx_i == 5'd1);
        branch_jmp_r        = ~(branch_call_r | branch_ret_r);
    end
    else if ((opcode_opcode_i & `INST_BEQ_MASK) == `INST_BEQ)
    begin
        branch_r      = 1'b1;
        branch_taken_r= (opcode_ra_operand_i == opcode_rb_operand_i);
    end
    else if ((opcode_opcode_i & `INST_BNE_MASK) == `INST_BNE)
    begin
        branch_r      = 1'b1;    
        branch_taken_r= (opcode_ra_operand_i != opcode_rb_operand_i);
    end
    else if ((opcode_opcode_i & `INST_BLT_MASK) == `INST_BLT)
    begin
        branch_r      = 1'b1;

        branch_taken_r= {~opcode_ra_operand_i[31],opcode_ra_operand_i[30:0]}<
                        {~opcode_rb_operand_i[31],opcode_rb_operand_i[30:0]};

    end
    else if ((opcode_opcode_i & `INST_BGE_MASK) == `INST_BGE)
    begin
        branch_r      = 1'b1;    

        branch_taken_r= ({~opcode_ra_operand_i[31],opcode_ra_operand_i[30:0]}>
                        {~opcode_rb_operand_i[31],opcode_rb_operand_i[30:0]})|
                        (opcode_ra_operand_i == opcode_rb_operand_i);

    end
    else if ((opcode_opcode_i & `INST_BLTU_MASK) == `INST_BLTU)
    begin
        branch_r      = 1'b1;    
        branch_taken_r= (opcode_ra_operand_i < opcode_rb_operand_i);
    end
    else if ((opcode_opcode_i & `INST_BGEU_MASK) == `INST_BGEU)
    begin
        branch_r      = 1'b1;
        branch_taken_r= (opcode_ra_operand_i >= opcode_rb_operand_i);
    end
end

reg        branch_taken_q;
reg        branch_ntaken_q;
reg [31:0] pc_x_q;
reg [31:0] pc_m_q;
reg        branch_call_q;
reg        branch_ret_q;
reg        branch_jmp_q;

always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
    branch_taken_q   <= 1'b0;
    branch_ntaken_q  <= 1'b0;
    pc_x_q           <= 32'b0;
    pc_m_q           <= 32'b0;
    branch_call_q    <= 1'b0;
    branch_ret_q     <= 1'b0;
    branch_jmp_q     <= 1'b0;
end
else if (opcode_valid_i)
begin
    branch_taken_q   <= branch_r && opcode_valid_i & branch_taken_r;
    branch_ntaken_q  <= branch_r && opcode_valid_i & ~branch_taken_r;
    pc_x_q           <= branch_taken_r ? branch_target_r : opcode_pc_i + 32'd4;
    branch_call_q    <= branch_r && opcode_valid_i && branch_call_r;
    branch_ret_q     <= branch_r && opcode_valid_i && branch_ret_r;
    branch_jmp_q     <= branch_r && opcode_valid_i && branch_jmp_r;
    pc_m_q           <= opcode_pc_i;
end

assign branch_request_o   = branch_taken_q | branch_ntaken_q;
assign branch_is_taken_o  = branch_taken_q;
assign branch_is_not_taken_o = branch_ntaken_q;
assign branch_source_o    = pc_m_q;
assign branch_pc_o        = pc_x_q;
assign branch_is_call_o   = branch_call_q;
assign branch_is_ret_o    = branch_ret_q;
assign branch_is_jmp_o    = branch_jmp_q;

assign branch_d_request_o = (branch_r && opcode_valid_i && branch_taken_r);
assign branch_d_pc_o      = branch_target_r;
assign branch_d_priv_o    = 2'b0;

endmodule