data/full_repos/permissive/496508301/Lesson4/m_gen/m_gen.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson4/m_gen/m_gen.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #10     res <= 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson4/m_gen/m_gen.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #300    $stop;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson4/m_gen/m_gen.v:30: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk=~clk;\n       ^\n%Error: data/full_repos/permissive/496508301/Lesson4/m_gen/m_gen.v:33: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("m_gen_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/496508301/Lesson4/m_gen/m_gen.v:34: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module m_gen_tb();
reg     clk, res;
wire    y;
m_gen m_gen(.clk(clk), .res(res), .y(y));
initial begin
            clk <= 0; res <= 0;
    #10     res <= 1;
    #300    $stop;
end
always #5 clk=~clk;

initial begin
    $dumpfile("m_gen_tb.vcd");
    $dumpvars;
end
endmodule
module m_gen_tb();

reg     clk, res;
wire    y;
m_gen m_gen(.clk(clk), .res(res), .y(y));
initial begin
            clk <= 0; res <= 0;
    #10     res <= 1;
    #300    $stop;
end
always #5 clk=~clk;

initial begin
    $dumpfile("m_gen_tb.vcd");
    $dumpvars;
end
endmodule