data/full_repos/permissive/476296842/rtl/tb/tb_alu.v
1: b'%Error: data/full_repos/permissive/476296842/rtl/tb/tb_alu.v:1: Cannot find include file: rtl/core/alu.v\n`include "rtl/core/alu.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/476296842/rtl/tb,data/full_repos/permissive/476296842/rtl/core/alu.v\n             data/full_repos/permissive/476296842/rtl/tb,data/full_repos/permissive/476296842/rtl/core/alu.v.v\n             data/full_repos/permissive/476296842/rtl/tb,data/full_repos/permissive/476296842/rtl/core/alu.v.sv\n             rtl/core/alu.v\n             rtl/core/alu.v.v\n             rtl/core/alu.v.sv\n             obj_dir/rtl/core/alu.v\n             obj_dir/rtl/core/alu.v.v\n             obj_dir/rtl/core/alu.v.sv\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_alu.v:5: Define or directive not defined: \'`alu_inst_bus\'\nreg [`alu_inst_bus] alu_inst_i = 0;\n     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_alu.v:5: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg [`alu_inst_bus] alu_inst_i = 0;\n                  ^\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_alu.v:6: Define or directive not defined: \'`data_bus\'\nreg signed [`data_bus] alu_src1_i = 0;\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_alu.v:6: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg signed [`data_bus] alu_src1_i = 0;\n                     ^\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_alu.v:8: Define or directive not defined: \'`data_bus\'\nwire [`data_bus] alu_result_o;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_alu.v:8: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [`data_bus] alu_result_o;\n               ^\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_alu.v:9: Define or directive not defined: \'`data_bus\'\nreg signed [`data_bus] alu_src2_i;\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_alu.v:9: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg signed [`data_bus] alu_src2_i;\n                     ^\n%Warning-STMTDLY: data/full_repos/permissive/476296842/rtl/tb/tb_alu.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_alu.v:21: Define or directive not defined: \'`alu_cmp_lessu\'\n    alu_inst_i = `alu_cmp_lessu;\n                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_alu.v:21: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    alu_inst_i = `alu_cmp_lessu;\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/476296842/rtl/tb/tb_alu.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_alu.v:28: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("./release/tb_alu.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/tb/tb_alu.v:29: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, tb_alu); \n    ^~~~~~~~~\n%Error: Exiting due to 13 error(s), 2 warning(s)\n'
module tb_alu;

reg [`alu_inst_bus] alu_inst_i = 0;
reg signed [`data_bus] alu_src1_i = 0;
reg signed [11: 0] alu_src2 = -1;
wire [`data_bus] alu_result_o;
reg signed [`data_bus] alu_src2_i;

alu u_alu(
    .alu_inst_i(alu_inst_i),
    .alu_src1_i(alu_src1_i),
    .alu_src2_i(alu_src2_i),        
    .alu_result_o(alu_result_o)
);
    

initial begin
    #1;
    alu_inst_i = `alu_cmp_lessu;
    alu_src1_i = 32'h8FFFFF00;
    alu_src2_i = alu_src2;
    #1;
end

initial begin
    $dumpfile("./release/tb_alu.vcd");
    $dumpvars(0, tb_alu); 
end

endmodule
module tb_alu;


reg [`alu_inst_bus] alu_inst_i = 0;
reg signed [`data_bus] alu_src1_i = 0;
reg signed [11: 0] alu_src2 = -1;
wire [`data_bus] alu_result_o;
reg signed [`data_bus] alu_src2_i;

alu u_alu(
    .alu_inst_i(alu_inst_i),
    .alu_src1_i(alu_src1_i),
    .alu_src2_i(alu_src2_i),        
    .alu_result_o(alu_result_o)
);
    

initial begin
    #1;
    alu_inst_i = `alu_cmp_lessu;
    alu_src1_i = 32'h8FFFFF00;
    alu_src2_i = alu_src2;
    #1;
end

initial begin
    $dumpfile("./release/tb_alu.vcd");
    $dumpvars(0, tb_alu); 
end

endmodule