data/full_repos/permissive/419538859/lab8/lab8.v
data/verilator_xmls/72eaa1fa-e1a0-4b8a-9606-e8f8e9cdaa6a.xml
module count6(clk, reset, count_out);
input clk, reset;
output[2:0] count_out;
reg[2:0] count_out;
always@ (posedge clk or posedge reset)
	begin
	if(reset)
			count_out= 3'b000;
	else
		begin
		if(count_out==3'b101)
				count_out= 3'b000;
		
		else count_out=count_out+3'b001;

		end	
	end
endmodule
module count6(clk, reset, count_out);

input clk, reset;
output[2:0] count_out;
reg[2:0] count_out;
always@ (posedge clk or posedge reset)
	begin
	if(reset)
			count_out= 3'b000;
	else
		begin
		if(count_out==3'b101)
				count_out= 3'b000;
		
		else count_out=count_out+3'b001;

		end	
	end
endmodule