data/full_repos/permissive/482168662/lab02_counter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/482168662/lab02_counter.v:56: Operator ASSIGNDLY expects 26 bits on the Assign RHS, but Assign RHS\'s CONST \'25\'h0\' generates 25 bits.\n                                                                       : ... In instance top_module.fenpiqi\n            cnt <= 25\'b0;\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/482168662/lab02_counter.v:58: Operator ASSIGNDLY expects 26 bits on the Assign RHS, but Assign RHS\'s CONST \'25\'h0\' generates 25 bits.\n                                                                       : ... In instance top_module.fenpiqi\n                cnt <= 25\'b0;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/482168662/lab02_counter.v:57: Operator EQ expects 26 bits on the RHS, but RHS\'s VARREF \'MAX\' generates 25 bits.\n                                                                       : ... In instance top_module.fenpiqi\n        else if(cnt == MAX)\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/482168662/lab02_counter.v:66: Operator EQ expects 26 bits on the RHS, but RHS\'s VARREF \'MAX\' generates 25 bits.\n                                                                       : ... In instance top_module.fenpiqi\n        else if(cnt == MAX)\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/482168662/lab02_counter.v:73: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                       : ... In instance top_module.fenpiqi\n            cnt_10Hz <= 22\'b0;\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/482168662/lab02_counter.v:75: Operator ASSIGNDLY expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                       : ... In instance top_module.fenpiqi\n                cnt_10Hz <= 22\'b0;\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/482168662/lab02_counter.v:74: Operator EQ expects 23 bits on the RHS, but RHS\'s VARREF \'MAX_10Hz\' generates 22 bits.\n                                                                       : ... In instance top_module.fenpiqi\n        else if(cnt_10Hz == MAX_10Hz)\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/482168662/lab02_counter.v:83: Operator EQ expects 23 bits on the RHS, but RHS\'s VARREF \'MAX_10Hz\' generates 22 bits.\n                                                                       : ... In instance top_module.fenpiqi\n        else if(cnt_10Hz == MAX_10Hz)\n                         ^~\n%Error: Exiting due to 8 warning(s)\n'
module divide(
    input clk,
    input rst_n,
    output clk_1Hz,
    output clk_10Hz
);

    parameter MAX = 25'd24_999_999;
    parameter MAX_10Hz = 22'd2_499_999;
    reg [25:0] cnt;
    reg [22:0] cnt_10Hz;
    reg clk_1Hz_reg;
    reg clk_10Hz_reg;


    always@(posedge clk,negedge rst_n)begin
        if(!rst_n)
            cnt <= 25'b0;
        else if(cnt == MAX)
                cnt <= 25'b0;
        else 
            cnt <= cnt + 25'd1;
    end

    always@(posedge clk,negedge rst_n)begin
        if(!rst_n)
          clk_1Hz_reg <= 1'd0;
        else if(cnt == MAX)
          clk_1Hz_reg <= ~clk_1Hz_reg;
    end


    always @(posedge clk,negedge rst_n) begin
        if(!rst_n)
            cnt_10Hz <= 22'b0;
        else if(cnt_10Hz == MAX_10Hz)
                cnt_10Hz <= 22'b0;
        else 
            cnt_10Hz <= cnt_10Hz + 22'd1;
    end

    always @(posedge clk,negedge rst_n) begin
        if(!rst_n)
          clk_10Hz_reg <= 1'd0;
        else if(cnt_10Hz == MAX_10Hz)
          clk_10Hz_reg <= ~clk_10Hz_reg;
    end

    assign clk_1Hz = clk_1Hz_reg;
    assign clk_10Hz = clk_10Hz_reg;  

endmodule
module divide(
    input clk,
    input rst_n,
    output clk_1Hz,
    output clk_10Hz
);


    parameter MAX = 25'd24_999_999;
    parameter MAX_10Hz = 22'd2_499_999;
    reg [25:0] cnt;
    reg [22:0] cnt_10Hz;
    reg clk_1Hz_reg;
    reg clk_10Hz_reg;


    always@(posedge clk,negedge rst_n)begin
        if(!rst_n)
            cnt <= 25'b0;
        else if(cnt == MAX)
                cnt <= 25'b0;
        else 
            cnt <= cnt + 25'd1;
    end

    always@(posedge clk,negedge rst_n)begin
        if(!rst_n)
          clk_1Hz_reg <= 1'd0;
        else if(cnt == MAX)
          clk_1Hz_reg <= ~clk_1Hz_reg;
    end


    always @(posedge clk,negedge rst_n) begin
        if(!rst_n)
            cnt_10Hz <= 22'b0;
        else if(cnt_10Hz == MAX_10Hz)
                cnt_10Hz <= 22'b0;
        else 
            cnt_10Hz <= cnt_10Hz + 22'd1;
    end

    always @(posedge clk,negedge rst_n) begin
        if(!rst_n)
          clk_10Hz_reg <= 1'd0;
        else if(cnt_10Hz == MAX_10Hz)
          clk_10Hz_reg <= ~clk_10Hz_reg;
    end

    assign clk_1Hz = clk_1Hz_reg;
    assign clk_10Hz = clk_10Hz_reg;  

endmodule