data/full_repos/permissive/500128826/HDLBits/Vectors/Vectorgates/top_module.v
1: b'%Warning-WIDTH: data/full_repos/permissive/500128826/HDLBits/Vectors/Vectorgates/top_module.v:19: Logical Operator LOGOR expects 1 bit on the LHS, but LHS\'s VARREF \'a\' generates 3 bits.\n                                                                                                : ... In instance top_module\n  assign out_or_logical = a || b;\n                            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/500128826/HDLBits/Vectors/Vectorgates/top_module.v:19: Logical Operator LOGOR expects 1 bit on the RHS, but RHS\'s VARREF \'b\' generates 3 bits.\n                                                                                                : ... In instance top_module\n  assign out_or_logical = a || b;\n                            ^~\n%Error: Exiting due to 2 warning(s)\n'
module top_module (
    input wire [2:0] a,
    input wire [2:0] b,
    output wire [2:0] out_or_bitwise,
    output wire out_or_logical,
    output wire [5:0] out_not
);

  assign out_or_bitwise = a | b;
  assign out_or_logical = a || b;
  assign out_not = ~{b, a};

endmodule
module top_module (
    input wire [2:0] a,
    input wire [2:0] b,
    output wire [2:0] out_or_bitwise,
    output wire out_or_logical,
    output wire [5:0] out_not
);


  assign out_or_bitwise = a | b;
  assign out_or_logical = a || b;
  assign out_not = ~{b, a};

endmodule