data/full_repos/permissive/429196919/FPGA/latchReg/latchReg.v
1: b'%Error: data/full_repos/permissive/429196919/FPGA/latchReg/latchReg.v:32: Cannot find include file: ../genericIOSateliteEnv.v\n `include "../genericIOSateliteEnv.v" \n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/429196919/FPGA/latchReg,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v\n             data/full_repos/permissive/429196919/FPGA/latchReg,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v.v\n             data/full_repos/permissive/429196919/FPGA/latchReg,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v.sv\n             ../genericIOSateliteEnv.v\n             ../genericIOSateliteEnv.v.v\n             ../genericIOSateliteEnv.v.sv\n             obj_dir/../genericIOSateliteEnv.v\n             obj_dir/../genericIOSateliteEnv.v.v\n             obj_dir/../genericIOSateliteEnv.v.sv\n%Error: Exiting due to 1 error(s)\n'
module latchReg	#(parameter WIDTH = 8)
				(input wire[WIDTH-1:0] latchInput,
				input reset,
				input masterClk,
				output reg[WIDTH-1:0] latchOutput);

	reg[WIDTH-1:0] latchInputMeta;
	reg[WIDTH-1:0] latchInputReclocked;
	



	reg prevReset;
	reg[WIDTH-1:0] prevLatchInputReclocked;
	integer i;

	always @ (posedge masterClk) begin
		prevReset <= reset;
		prevLatchInputReclocked <= latchInputReclocked;
	end
	`define LATCH_RESET_POSEDGE (reset && !prevReset)
	`define LATCH_RESET_NEGEDGE (!reset && prevReset)
	`define LATCH_INPUT_POSEDGE(INDEX) (latchInputReclocked[INDEX] && !prevLatchInputReclocked[INDEX])
	`define LATCH_INPUT_NEGEDGE(INDEX) (!latchInputReclocked[INDEX] && prevLatchInputReclocked[INDEX])





	always @ (posedge masterClk) begin
		if(`LATCH_RESET_POSEDGE) begin
			latchInputMeta <= 0;
			latchInputReclocked <= 0;
			latchOutput <= 0;
		end
		else begin
			latchInputMeta <= latchInput;
			latchInputReclocked <= latchInputMeta;
			for (i = 0; i < WIDTH; i = i + 1) begin
				if(`LATCH_INPUT_POSEDGE(i))
					latchOutput[i] <= 1;
			end
		end
	end

endmodule
module latchReg	#(parameter WIDTH = 8)
				(input wire[WIDTH-1:0] latchInput,
				input reset,
				input masterClk,
				output reg[WIDTH-1:0] latchOutput);


	reg[WIDTH-1:0] latchInputMeta;
	reg[WIDTH-1:0] latchInputReclocked;
	



	reg prevReset;
	reg[WIDTH-1:0] prevLatchInputReclocked;
	integer i;

	always @ (posedge masterClk) begin
		prevReset <= reset;
		prevLatchInputReclocked <= latchInputReclocked;
	end
	`define LATCH_RESET_POSEDGE (reset && !prevReset)
	`define LATCH_RESET_NEGEDGE (!reset && prevReset)
	`define LATCH_INPUT_POSEDGE(INDEX) (latchInputReclocked[INDEX] && !prevLatchInputReclocked[INDEX])
	`define LATCH_INPUT_NEGEDGE(INDEX) (!latchInputReclocked[INDEX] && prevLatchInputReclocked[INDEX])





	always @ (posedge masterClk) begin
		if(`LATCH_RESET_POSEDGE) begin
			latchInputMeta <= 0;
			latchInputReclocked <= 0;
			latchOutput <= 0;
		end
		else begin
			latchInputMeta <= latchInput;
			latchInputReclocked <= latchInputMeta;
			for (i = 0; i < WIDTH; i = i + 1) begin
				if(`LATCH_INPUT_POSEDGE(i))
					latchOutput[i] <= 1;
			end
		end
	end

endmodule