data/full_repos/permissive/447223480/00_setup/cpu.v
data/verilator_xmls/598f3bb0-da04-4da3-bea7-8b905d69d57a.xml
module cpu(clock, reset);
	input clock;
	input reset;

	reg [31:0] pc;

	always @(posedge clock) begin
		if (reset) begin
			pc <= 32'd0;
		end else begin
			pc <= pc + 32'd2;
		end
	end

endmodule
module cpu(clock, reset);

	input clock;
	input reset;

	reg [31:0] pc;

	always @(posedge clock) begin
		if (reset) begin
			pc <= 32'd0;
		end else begin
			pc <= pc + 32'd2;
		end
	end

endmodule