data/full_repos/permissive/516180498/al_ip/pll_clock.v
1: b"%Error: data/full_repos/permissive/516180498/al_ip/pll_clock.v:91: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n  .do({open, open, open, open, open, open, open, open}),\n   ^~\n%Error: data/full_repos/permissive/516180498/al_ip/pll_clock.v:91: syntax error, unexpected '(', expecting ')'\n  .do({open, open, open, open, open, open, open, open}),\n      ^\n%Error: Exiting due to 2 error(s)\n"
module pll_clock(refclk,
		reset,
		clk0_out,
		clk1_out,
		clk2_out,
		clk3_out);

	input refclk;
	input reset;
	output clk0_out;
	output clk1_out;
	output clk2_out;
	output clk3_out;

	wire clk0_buf;

	EG_LOGIC_BUFG bufg_feedback( .i(clk0_buf), .o(clk0_out) );

	EG_PHY_PLL #(.DPHASE_SOURCE("DISABLE"),
		.DYNCFG("DISABLE"),
		.FIN("24.000"),
		.FEEDBK_MODE("NORMAL"),
		.FEEDBK_PATH("CLKC0_EXT"),
		.STDBY_ENABLE("DISABLE"),
		.PLLRST_ENA("ENABLE"),
		.SYNC_ENABLE("DISABLE"),
		.DERIVE_PLL_CLOCKS("ENABLE"),
		.GEN_BASIC_CLOCK("ENABLE"),
		.GMC_GAIN(2),
		.ICP_CURRENT(9),
		.KVCO(2),
		.LPF_CAPACITOR(1),
		.LPF_RESISTOR(8),
		.REFCLK_DIV(1),
		.FBCLK_DIV(1),
		.CLKC0_ENABLE("ENABLE"),
		.CLKC0_DIV(40),
		.CLKC0_CPHASE(39),
		.CLKC0_FPHASE(0),
		.CLKC1_ENABLE("ENABLE"),
		.CLKC1_DIV(6),
		.CLKC1_CPHASE(5),
		.CLKC1_FPHASE(0),
		.CLKC2_ENABLE("ENABLE"),
		.CLKC2_DIV(24),
		.CLKC2_CPHASE(23),
		.CLKC2_FPHASE(0),
		.CLKC3_ENABLE("ENABLE"),
		.CLKC3_DIV(96),
		.CLKC3_CPHASE(95),
		.CLKC3_FPHASE(0)	)
	pll_inst (.refclk(refclk),
		.reset(reset),
		.stdby(1'b0),
		.extlock(open),
		.load_reg(1'b0),
		.psclk(1'b0),
		.psdown(1'b0),
		.psstep(1'b0),
		.psclksel(3'b000),
		.psdone(open),
		.dclk(1'b0),
		.dcs(1'b0),
		.dwe(1'b0),
		.di(8'b00000000),
		.daddr(6'b000000),
		.do({open, open, open, open, open, open, open, open}),
		.fbclk(clk0_out),
		.clkc({open, clk3_out, clk2_out, clk1_out, clk0_buf}));

endmodule
module pll_clock(refclk,
		reset,
		clk0_out,
		clk1_out,
		clk2_out,
		clk3_out);


	input refclk;
	input reset;
	output clk0_out;
	output clk1_out;
	output clk2_out;
	output clk3_out;

	wire clk0_buf;

	EG_LOGIC_BUFG bufg_feedback( .i(clk0_buf), .o(clk0_out) );

	EG_PHY_PLL #(.DPHASE_SOURCE("DISABLE"),
		.DYNCFG("DISABLE"),
		.FIN("24.000"),
		.FEEDBK_MODE("NORMAL"),
		.FEEDBK_PATH("CLKC0_EXT"),
		.STDBY_ENABLE("DISABLE"),
		.PLLRST_ENA("ENABLE"),
		.SYNC_ENABLE("DISABLE"),
		.DERIVE_PLL_CLOCKS("ENABLE"),
		.GEN_BASIC_CLOCK("ENABLE"),
		.GMC_GAIN(2),
		.ICP_CURRENT(9),
		.KVCO(2),
		.LPF_CAPACITOR(1),
		.LPF_RESISTOR(8),
		.REFCLK_DIV(1),
		.FBCLK_DIV(1),
		.CLKC0_ENABLE("ENABLE"),
		.CLKC0_DIV(40),
		.CLKC0_CPHASE(39),
		.CLKC0_FPHASE(0),
		.CLKC1_ENABLE("ENABLE"),
		.CLKC1_DIV(6),
		.CLKC1_CPHASE(5),
		.CLKC1_FPHASE(0),
		.CLKC2_ENABLE("ENABLE"),
		.CLKC2_DIV(24),
		.CLKC2_CPHASE(23),
		.CLKC2_FPHASE(0),
		.CLKC3_ENABLE("ENABLE"),
		.CLKC3_DIV(96),
		.CLKC3_CPHASE(95),
		.CLKC3_FPHASE(0)	)
	pll_inst (.refclk(refclk),
		.reset(reset),
		.stdby(1'b0),
		.extlock(open),
		.load_reg(1'b0),
		.psclk(1'b0),
		.psdown(1'b0),
		.psstep(1'b0),
		.psclksel(3'b000),
		.psdone(open),
		.dclk(1'b0),
		.dcs(1'b0),
		.dwe(1'b0),
		.di(8'b00000000),
		.daddr(6'b000000),
		.do({open, open, open, open, open, open, open, open}),
		.fbclk(clk0_out),
		.clkc({open, clk3_out, clk2_out, clk1_out, clk0_buf}));

endmodule