data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/gen/gen_counter_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/gen/gen_counter_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #H_period;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/gen/gen_counter_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #H_period;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/gen/gen_counter_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #F_period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/gen/gen_counter_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #F_period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/gen/gen_counter_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #COUNT_period;\n  ^\n%Error: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/gen/gen_counter_tb.v:19: Cannot find file containing module: \'gen_counter\'\ngen_counter #(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/gen,data/full_repos/permissive/503053625/gen_counter\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/gen,data/full_repos/permissive/503053625/gen_counter.v\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/gen,data/full_repos/permissive/503053625/gen_counter.sv\n             gen_counter\n             gen_counter.v\n             gen_counter.sv\n             obj_dir/gen_counter\n             obj_dir/gen_counter.v\n             obj_dir/gen_counter.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module gen_counter_tb;
localparam COUNT_TO = 1024;
localparam F_period=4;
localparam H_period=F_period/2;
localparam COUNT_period=F_period*COUNT_TO;
localparam DATA_WIDTH = 64;
localparam  ON = 1'b1;
localparam  OFF = 1'b0;

reg  CLK = ON;
reg  ENABLE = OFF;
reg	 [DATA_WIDTH - 1 : 0] COUNT = {DATA_WIDTH{1'b0}};
wire FINISH;

gen_counter #(
	.DATA_WIDTH(DATA_WIDTH)
) COUNT0 (
	.clk(CLK),
	.en(ENABLE),
	.wait_val(COUNT),
	.f(FINISH)
);

always begin
    CLK = OFF;
    #H_period;
    CLK = ON;
    #H_period;
end
initial
begin
    repeat(COUNT_TO) begin
        COUNT = COUNT + 1;
        #F_period;
        #F_period;
		ENABLE= ON;
		#COUNT_period;
		ENABLE= OFF;
    end
    $finish;
end

endmodule
module gen_counter_tb;

localparam COUNT_TO = 1024;
localparam F_period=4;
localparam H_period=F_period/2;
localparam COUNT_period=F_period*COUNT_TO;
localparam DATA_WIDTH = 64;
localparam  ON = 1'b1;
localparam  OFF = 1'b0;

reg  CLK = ON;
reg  ENABLE = OFF;
reg	 [DATA_WIDTH - 1 : 0] COUNT = {DATA_WIDTH{1'b0}};
wire FINISH;

gen_counter #(
	.DATA_WIDTH(DATA_WIDTH)
) COUNT0 (
	.clk(CLK),
	.en(ENABLE),
	.wait_val(COUNT),
	.f(FINISH)
);

always begin
    CLK = OFF;
    #H_period;
    CLK = ON;
    #H_period;
end
initial
begin
    repeat(COUNT_TO) begin
        COUNT = COUNT + 1;
        #F_period;
        #F_period;
		ENABLE= ON;
		#COUNT_period;
		ENABLE= OFF;
    end
    $finish;
end

endmodule