data/full_repos/permissive/52706914/vgalab1.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/52706914/vgalab1.v:10: Little bit endian vector: MSB < LSB of bit range: 0:6\n  output [0:6] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7,   \n         ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/52706914/vgalab1.v:41: Cannot find file containing module: \'Reset_Delay\'\nReset_Delay r0( .iCLK(CLOCK_50),.oRESET(DLY_RST) );\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52706914,data/full_repos/permissive/52706914/Reset_Delay\n             data/full_repos/permissive/52706914,data/full_repos/permissive/52706914/Reset_Delay.v\n             data/full_repos/permissive/52706914,data/full_repos/permissive/52706914/Reset_Delay.sv\n             Reset_Delay\n             Reset_Delay.v\n             Reset_Delay.sv\n             obj_dir/Reset_Delay\n             obj_dir/Reset_Delay.v\n             obj_dir/Reset_Delay.sv\n%Warning-WIDTH: data/full_repos/permissive/52706914/vgalab1.v:47: Operator ASSIGNW expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                : ... In instance vgalab1\nassign LEDG = 8\'h00;\n            ^\n%Error: data/full_repos/permissive/52706914/vgalab1.v:69: Cannot find file containing module: \'VGA_Audio_PLL\'\nVGA_Audio_PLL  p1 ( \n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/52706914/vgalab1.v:79: Cannot find file containing module: \'background\'\nbackground background(KEY[1], CLOCK_50, KEY[2], mCoord_X, mCoord_Y, r, g, b, HEX0, HEX1);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/52706914/vgalab1.v:113: Cannot find file containing module: \'vga_sync\'\nvga_sync u1(\n^~~~~~~~\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module vgalab1(

  input CLOCK_50,
  input CLOCK_27,

  input [3:0] KEY,

  input [17:0] SW,

  output [0:6]	HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7,

  output [8:0]	LEDG,
  output [17:0] LEDR,

 inout [35:0] GPIO_0,GPIO_1,




  output TD_RESET,

  output VGA_CLK,
  output VGA_HS,
  output VGA_VS,
  output VGA_BLANK,
  output VGA_SYNC,
  output [9:0] VGA_R,
  output [9:0] VGA_G,
  output [9:0] VGA_B
);


assign	GPIO_0		=	36'hzzzzzzzzz;
assign	GPIO_1		=	36'hzzzzzzzzz;

wire RST;
assign RST = KEY[0];


wire DLY_RST;
Reset_Delay r0(	.iCLK(CLOCK_50),.oRESET(DLY_RST) );


assign LEDR = SW;


assign LEDG = 8'h00;

wire [6:0] blank = 7'b0000001;


assign HEX2 = blank;
assign HEX3 = blank;
assign HEX4 = blank;
assign HEX5 = blank;
assign HEX6 = blank;
assign HEX7 = blank;

wire		VGA_CTRL_CLK;
wire		AUD_CTRL_CLK;
wire [9:0]	mVGA_R;
wire [9:0]	mVGA_G;
wire [9:0]	mVGA_B;
wire [9:0]	mCoord_X;
wire [9:0]	mCoord_Y;

assign	TD_RESET = 1'b1;

VGA_Audio_PLL 	p1 (	
	.areset(~DLY_RST),
	.inclk0(CLOCK_27),
	.c0(VGA_CTRL_CLK),
	.c1(AUD_CTRL_CLK),
	.c2(VGA_CLK)
);

wire [9:0] r, g, b;

background background(KEY[1], CLOCK_50, KEY[2], mCoord_X, mCoord_Y, r, g, b, HEX0, HEX1);

wire [9:0] gray = (mCoord_X<80 || mCoord_X>560? 10'h000:
	(mCoord_Y/15)<<5 | (mCoord_X-80)/15);
	
wire s = SW[0];
assign mVGA_R = (s? gray: r);
assign mVGA_G = (s? gray: g);
assign mVGA_B = (s? gray: b);




vga_sync u1(
   .iCLK(VGA_CTRL_CLK),
   .iRST_N(DLY_RST&KEY[0]),	
   .iRed(mVGA_R),
   .iGreen(mVGA_G),
   .iBlue(mVGA_B),

   .px(mCoord_X),
   .py(mCoord_Y),

   .VGA_R(VGA_R),
   .VGA_G(VGA_G),
   .VGA_B(VGA_B),
   .VGA_H_SYNC(VGA_HS),
   .VGA_V_SYNC(VGA_VS),
   .VGA_SYNC(VGA_SYNC),
   .VGA_BLANK(VGA_BLANK)
);


endmodule
module vgalab1(

  input CLOCK_50,
  input CLOCK_27,

  input [3:0] KEY,

  input [17:0] SW,

  output [0:6]	HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7,

  output [8:0]	LEDG,
  output [17:0] LEDR,

 inout [35:0] GPIO_0,GPIO_1,




  output TD_RESET,

  output VGA_CLK,
  output VGA_HS,
  output VGA_VS,
  output VGA_BLANK,
  output VGA_SYNC,
  output [9:0] VGA_R,
  output [9:0] VGA_G,
  output [9:0] VGA_B
);



assign	GPIO_0		=	36'hzzzzzzzzz;
assign	GPIO_1		=	36'hzzzzzzzzz;

wire RST;
assign RST = KEY[0];


wire DLY_RST;
Reset_Delay r0(	.iCLK(CLOCK_50),.oRESET(DLY_RST) );


assign LEDR = SW;


assign LEDG = 8'h00;

wire [6:0] blank = 7'b0000001;


assign HEX2 = blank;
assign HEX3 = blank;
assign HEX4 = blank;
assign HEX5 = blank;
assign HEX6 = blank;
assign HEX7 = blank;

wire		VGA_CTRL_CLK;
wire		AUD_CTRL_CLK;
wire [9:0]	mVGA_R;
wire [9:0]	mVGA_G;
wire [9:0]	mVGA_B;
wire [9:0]	mCoord_X;
wire [9:0]	mCoord_Y;

assign	TD_RESET = 1'b1;

VGA_Audio_PLL 	p1 (	
	.areset(~DLY_RST),
	.inclk0(CLOCK_27),
	.c0(VGA_CTRL_CLK),
	.c1(AUD_CTRL_CLK),
	.c2(VGA_CLK)
);

wire [9:0] r, g, b;

background background(KEY[1], CLOCK_50, KEY[2], mCoord_X, mCoord_Y, r, g, b, HEX0, HEX1);

wire [9:0] gray = (mCoord_X<80 || mCoord_X>560? 10'h000:
	(mCoord_Y/15)<<5 | (mCoord_X-80)/15);
	
wire s = SW[0];
assign mVGA_R = (s? gray: r);
assign mVGA_G = (s? gray: g);
assign mVGA_B = (s? gray: b);




vga_sync u1(
   .iCLK(VGA_CTRL_CLK),
   .iRST_N(DLY_RST&KEY[0]),	
   .iRed(mVGA_R),
   .iGreen(mVGA_G),
   .iBlue(mVGA_B),

   .px(mCoord_X),
   .py(mCoord_Y),

   .VGA_R(VGA_R),
   .VGA_G(VGA_G),
   .VGA_B(VGA_B),
   .VGA_H_SYNC(VGA_HS),
   .VGA_V_SYNC(VGA_VS),
   .VGA_SYNC(VGA_SYNC),
   .VGA_BLANK(VGA_BLANK)
);


endmodule