data/full_repos/permissive/497530416/pipe/ALU/alu_64bit.v
1: b'%Error: data/full_repos/permissive/497530416/pipe/ALU/alu_64bit.v:1: Cannot find include file: ./ADD_SUB/add_sub_64bit.v\n`include "./ADD_SUB/add_sub_64bit.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/497530416/pipe/ALU,data/full_repos/permissive/497530416/./ADD_SUB/add_sub_64bit.v\n             data/full_repos/permissive/497530416/pipe/ALU,data/full_repos/permissive/497530416/./ADD_SUB/add_sub_64bit.v.v\n             data/full_repos/permissive/497530416/pipe/ALU,data/full_repos/permissive/497530416/./ADD_SUB/add_sub_64bit.v.sv\n             ./ADD_SUB/add_sub_64bit.v\n             ./ADD_SUB/add_sub_64bit.v.v\n             ./ADD_SUB/add_sub_64bit.v.sv\n             obj_dir/./ADD_SUB/add_sub_64bit.v\n             obj_dir/./ADD_SUB/add_sub_64bit.v.v\n             obj_dir/./ADD_SUB/add_sub_64bit.v.sv\n%Error: data/full_repos/permissive/497530416/pipe/ALU/alu_64bit.v:2: Cannot find include file: ./ADD_SUB/add_1bit.v\n`include "./ADD_SUB/add_1bit.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/497530416/pipe/ALU/alu_64bit.v:3: Cannot find include file: ./XOR_64bit/xor_64bit.v\n`include "./XOR_64bit/xor_64bit.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/497530416/pipe/ALU/alu_64bit.v:4: Cannot find include file: ./AND_64bit/and_64bit.v\n`include "./AND_64bit/and_64bit.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module ALU_64bit(control, a, b, out, OF);

input [1:0] control;
input signed [63:0] a;
input signed [63:0] b;
output signed [63:0] out;
output OF;

wire signed [63:0] sum1, sum2, sum3;
reg [63:0] sum;
reg overflow;

add_sub_64bit adder64(a,b, sum1, control[0], OF);
and_64bit and64(a,b,sum2);
xor_64bit xor64(a,b,sum3);

always@(*)
begin
    case(control)
    2'b00, 2'b01: begin 
        sum=sum1; 
    end
    2'b10: begin sum=sum2; end
    2'b11: begin sum=sum3; end
    endcase
end

assign out=sum;

endmodule
module ALU_64bit(control, a, b, out, OF);


input [1:0] control;
input signed [63:0] a;
input signed [63:0] b;
output signed [63:0] out;
output OF;

wire signed [63:0] sum1, sum2, sum3;
reg [63:0] sum;
reg overflow;

add_sub_64bit adder64(a,b, sum1, control[0], OF);
and_64bit and64(a,b,sum2);
xor_64bit xor64(a,b,sum3);

always@(*)
begin
    case(control)
    2'b00, 2'b01: begin 
        sum=sum1; 
    end
    2'b10: begin sum=sum2; end
    2'b11: begin sum=sum3; end
    endcase
end

assign out=sum;

endmodule