data/full_repos/permissive/463439324/keygen/inv.v
1: b'%Error: data/full_repos/permissive/463439324/keygen/inv.v:270: Cannot find file containing module: \'f0_times_g0\'\n    f0_times_g0 f_times_g0 ( f[0], f[1],g0[0],g0[1],fg0[0],fg0[1]);\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463439324/keygen,data/full_repos/permissive/463439324/f0_times_g0\n             data/full_repos/permissive/463439324/keygen,data/full_repos/permissive/463439324/f0_times_g0.v\n             data/full_repos/permissive/463439324/keygen,data/full_repos/permissive/463439324/f0_times_g0.sv\n             f0_times_g0\n             f0_times_g0.v\n             f0_times_g0.sv\n             obj_dir/f0_times_g0\n             obj_dir/f0_times_g0.v\n             obj_dir/f0_times_g0.sv\n%Error: data/full_repos/permissive/463439324/keygen/inv.v:271: Cannot find file containing module: \'f0_times_g0\'\n    f0_times_g0 f0_times_g (f0[0],f0[1], g[0],g [1],gf0[0],gf0[1]);\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/keygen/inv.v:273: Cannot find file containing module: \'f0_times_g0\'\n    f0_times_g0 v_times_g0 (v_s1[0],v_s1[1],  g0[0],  g0[1],vg0[0],vg0[1]);\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/keygen/inv.v:274: Cannot find file containing module: \'f0_times_g0\'\n    f0_times_g0 f0_times_r (  f0[0],  f0[1],r_s1[0],r_s1[1],rf0[0],rf0[1]);\n    ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/463439324/keygen/inv.v:170: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                     : ... In instance r3_inverse\n            state <= 3\'d0;\n                  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 4 error(s), 1 warning(s)\n'
module r3_inverse(
    clk,
    rst,
    start,
    wr_en, wr_addr, rd_addr, wr_di, rd_dout,
	valid
);
    parameter P_WIDTH = 8;
	parameter Q_DEPTH = 10;
    parameter NTRU_Q = 4591;
	integer	  i;


	parameter IDLE = 0;
	parameter INVERSE = 1;
	parameter FINISH = 2;
    

    input					   clk;
	input					   rst;
	input	        		   start;
    output reg                 wr_en;
    output reg [Q_DEPTH-1 : 0] wr_addr;
    output     [Q_DEPTH-1 : 0] rd_addr;
    output     [P_WIDTH-1 : 0] wr_di;
    input      [P_WIDTH-1 : 0] rd_dout;
	output reg				   valid;

    reg         [1 : 0]  state, next_state;
    reg         [9 : 0]  counter;
    reg         [10 : 0] counter_t;
    wire                 counter_end, counter_t_end;
    reg                  start_i;
    reg  signed [10 : 0] delta;
    wire                 start_in [0 : 8];
    wire signed [10 : 0] delta_in [0 : 8];
    wire [P_WIDTH-1 : 0] vrfg_in  [0 : 8];
    wire                 pass_in  [0 : 8];
    reg                  s        [0 : 7];
    reg                  counter_start;
    reg                  pass;
    

    assign counter_end   = (counter == 761)   ? 1 : 0;
    assign counter_t_end = (counter_t == 191) ? 1 : 0;
    assign rd_addr = counter;
    assign vrfg_in[0] = rd_dout;
    assign delta_in[0] = delta;
    assign start_in[0] = start_i;
    assign wr_di = vrfg_in[8];
    assign pass_in[0] = pass;

    always @(posedge clk ) begin
        s[0] <= 0;
        s[1] <= 1;
        s[2] <= 1;
        s[3] <= 1;
        s[4] <= 1;
        s[5] <= 1;
        s[6] <= 1;
        s[7] <= 1;
    end


    always @(posedge clk ) begin
        if (counter_t == 190) begin
            pass <= 1;
        end else begin
            pass <= 0;
        end
    end


    always @(posedge clk ) begin
        if (rst) begin
            wr_en <= 0;
        end else begin
            if (counter == 24 && counter_t == 0) begin
                wr_en <= 1;
            end else begin
                wr_en <= wr_en;
            end
        end
    end


    always @(posedge clk ) begin
        if(counter_start)begin
            if(wr_addr == 761)begin
                wr_addr <= 0;
            end else begin
                wr_addr <= wr_addr + 1;
            end
        end else begin
            wr_addr <= 0;
        end

        if (rst) begin
            counter_start <= 0;
        end else begin
            if (counter == 24 && counter_t == 0) begin
                counter_start <= 1;
            end else begin
                counter_start <= counter_start;
            end
        end
    end


    always@(posedge clk)begin
        if(state == INVERSE)begin
            if(counter_end)begin
                counter <= 0;
            end else begin
                counter <= counter + 1;
            end
        end else begin 
            counter <= 0;
        end

        if(state == INVERSE)begin
            if (counter_end) begin
                counter_t <= counter_t + 1;
            end else begin
                counter_t <= counter_t;
            end
        end else begin
            counter_t <= 0;
        end
    end


    always@(*)begin
        if (state == FINISH) begin
            valid = 1;
        end else begin
            valid = 0;
        end
    end


	always@(posedge clk)begin
		if(rst) begin
            state <= 3'd0;
        end else begin
            state <= next_state;
        end
	end
	always@(*)begin
		case(state)
		IDLE: 
		begin
			if(start)
				next_state = INVERSE;
			else
				next_state = IDLE;
		end
		INVERSE: 
		begin
			if(counter_t == 191 && wr_addr == 761)
				next_state = FINISH;
			else
				next_state = INVERSE;
		end
		FINISH:
		begin
            next_state = FINISH;

		end
		default: next_state = state;
		endcase
	end


    always @(posedge clk ) begin
        if (counter == 0) begin
            start_i <= 1;
        end else begin
            start_i <= 0;
        end
    end


    always @(posedge clk ) begin
        if (counter_t == 0) begin
            delta <= 1;
        end else begin
            delta <= delta_in[8];
        end
    end

    inv inv_0(clk, s[0], pass_in[0], start_in[0], delta_in[0], vrfg_in[0], pass_in[1], start_in[1], delta_in[1], vrfg_in[1]);
    inv inv_1(clk, s[1], pass_in[1], start_in[1], delta_in[1], vrfg_in[1], pass_in[2], start_in[2], delta_in[2], vrfg_in[2]);
    inv inv_2(clk, s[2], pass_in[2], start_in[2], delta_in[2], vrfg_in[2], pass_in[3], start_in[3], delta_in[3], vrfg_in[3]);
    inv inv_3(clk, s[3], pass_in[3], start_in[3], delta_in[3], vrfg_in[3], pass_in[4], start_in[4], delta_in[4], vrfg_in[4]);
    inv inv_4(clk, s[4], pass_in[4], start_in[4], delta_in[4], vrfg_in[4], pass_in[5], start_in[5], delta_in[5], vrfg_in[5]);
    inv inv_5(clk, s[5], pass_in[5], start_in[5], delta_in[5], vrfg_in[5], pass_in[6], start_in[6], delta_in[6], vrfg_in[6]);
    inv inv_6(clk, s[6], pass_in[6], start_in[6], delta_in[6], vrfg_in[6], pass_in[7], start_in[7], delta_in[7], vrfg_in[7]);
    inv inv_7(clk, s[7], pass_in[7], start_in[7], delta_in[7], vrfg_in[7], pass_in[8], start_in[8], delta_in[8], vrfg_in[8]);

endmodule
module r3_inverse(
    clk,
    rst,
    start,
    wr_en, wr_addr, rd_addr, wr_di, rd_dout,
	valid
);

    parameter P_WIDTH = 8;
	parameter Q_DEPTH = 10;
    parameter NTRU_Q = 4591;
	integer	  i;


	parameter IDLE = 0;
	parameter INVERSE = 1;
	parameter FINISH = 2;
    

    input					   clk;
	input					   rst;
	input	        		   start;
    output reg                 wr_en;
    output reg [Q_DEPTH-1 : 0] wr_addr;
    output     [Q_DEPTH-1 : 0] rd_addr;
    output     [P_WIDTH-1 : 0] wr_di;
    input      [P_WIDTH-1 : 0] rd_dout;
	output reg				   valid;

    reg         [1 : 0]  state, next_state;
    reg         [9 : 0]  counter;
    reg         [10 : 0] counter_t;
    wire                 counter_end, counter_t_end;
    reg                  start_i;
    reg  signed [10 : 0] delta;
    wire                 start_in [0 : 8];
    wire signed [10 : 0] delta_in [0 : 8];
    wire [P_WIDTH-1 : 0] vrfg_in  [0 : 8];
    wire                 pass_in  [0 : 8];
    reg                  s        [0 : 7];
    reg                  counter_start;
    reg                  pass;
    

    assign counter_end   = (counter == 761)   ? 1 : 0;
    assign counter_t_end = (counter_t == 191) ? 1 : 0;
    assign rd_addr = counter;
    assign vrfg_in[0] = rd_dout;
    assign delta_in[0] = delta;
    assign start_in[0] = start_i;
    assign wr_di = vrfg_in[8];
    assign pass_in[0] = pass;

    always @(posedge clk ) begin
        s[0] <= 0;
        s[1] <= 1;
        s[2] <= 1;
        s[3] <= 1;
        s[4] <= 1;
        s[5] <= 1;
        s[6] <= 1;
        s[7] <= 1;
    end


    always @(posedge clk ) begin
        if (counter_t == 190) begin
            pass <= 1;
        end else begin
            pass <= 0;
        end
    end


    always @(posedge clk ) begin
        if (rst) begin
            wr_en <= 0;
        end else begin
            if (counter == 24 && counter_t == 0) begin
                wr_en <= 1;
            end else begin
                wr_en <= wr_en;
            end
        end
    end


    always @(posedge clk ) begin
        if(counter_start)begin
            if(wr_addr == 761)begin
                wr_addr <= 0;
            end else begin
                wr_addr <= wr_addr + 1;
            end
        end else begin
            wr_addr <= 0;
        end

        if (rst) begin
            counter_start <= 0;
        end else begin
            if (counter == 24 && counter_t == 0) begin
                counter_start <= 1;
            end else begin
                counter_start <= counter_start;
            end
        end
    end


    always@(posedge clk)begin
        if(state == INVERSE)begin
            if(counter_end)begin
                counter <= 0;
            end else begin
                counter <= counter + 1;
            end
        end else begin 
            counter <= 0;
        end

        if(state == INVERSE)begin
            if (counter_end) begin
                counter_t <= counter_t + 1;
            end else begin
                counter_t <= counter_t;
            end
        end else begin
            counter_t <= 0;
        end
    end


    always@(*)begin
        if (state == FINISH) begin
            valid = 1;
        end else begin
            valid = 0;
        end
    end


	always@(posedge clk)begin
		if(rst) begin
            state <= 3'd0;
        end else begin
            state <= next_state;
        end
	end
	always@(*)begin
		case(state)
		IDLE: 
		begin
			if(start)
				next_state = INVERSE;
			else
				next_state = IDLE;
		end
		INVERSE: 
		begin
			if(counter_t == 191 && wr_addr == 761)
				next_state = FINISH;
			else
				next_state = INVERSE;
		end
		FINISH:
		begin
            next_state = FINISH;

		end
		default: next_state = state;
		endcase
	end


    always @(posedge clk ) begin
        if (counter == 0) begin
            start_i <= 1;
        end else begin
            start_i <= 0;
        end
    end


    always @(posedge clk ) begin
        if (counter_t == 0) begin
            delta <= 1;
        end else begin
            delta <= delta_in[8];
        end
    end

    inv inv_0(clk, s[0], pass_in[0], start_in[0], delta_in[0], vrfg_in[0], pass_in[1], start_in[1], delta_in[1], vrfg_in[1]);
    inv inv_1(clk, s[1], pass_in[1], start_in[1], delta_in[1], vrfg_in[1], pass_in[2], start_in[2], delta_in[2], vrfg_in[2]);
    inv inv_2(clk, s[2], pass_in[2], start_in[2], delta_in[2], vrfg_in[2], pass_in[3], start_in[3], delta_in[3], vrfg_in[3]);
    inv inv_3(clk, s[3], pass_in[3], start_in[3], delta_in[3], vrfg_in[3], pass_in[4], start_in[4], delta_in[4], vrfg_in[4]);
    inv inv_4(clk, s[4], pass_in[4], start_in[4], delta_in[4], vrfg_in[4], pass_in[5], start_in[5], delta_in[5], vrfg_in[5]);
    inv inv_5(clk, s[5], pass_in[5], start_in[5], delta_in[5], vrfg_in[5], pass_in[6], start_in[6], delta_in[6], vrfg_in[6]);
    inv inv_6(clk, s[6], pass_in[6], start_in[6], delta_in[6], vrfg_in[6], pass_in[7], start_in[7], delta_in[7], vrfg_in[7]);
    inv inv_7(clk, s[7], pass_in[7], start_in[7], delta_in[7], vrfg_in[7], pass_in[8], start_in[8], delta_in[8], vrfg_in[8]);

endmodule