data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v
1: b'%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:1: Cannot find include file: StateTable.v\n`include "StateTable.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/46343463/src,data/full_repos/permissive/46343463/StateTable.v\n             data/full_repos/permissive/46343463/src,data/full_repos/permissive/46343463/StateTable.v.v\n             data/full_repos/permissive/46343463/src,data/full_repos/permissive/46343463/StateTable.v.sv\n             StateTable.v\n             StateTable.v.v\n             StateTable.v.sv\n             obj_dir/StateTable.v\n             obj_dir/StateTable.v.v\n             obj_dir/StateTable.v.sv\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:37: Define or directive not defined: \'`STATE_IDLE\'\n  state  = `STATE_IDLE;\n           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:37: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  state  = `STATE_IDLE;\n                      ^\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:38: Define or directive not defined: \'`STATE_IDLE\'\n  next_state  = `STATE_IDLE;\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:38: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  next_state  = `STATE_IDLE;\n                           ^\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:50: Define or directive not defined: \'`STATE_IDLE\'\n   next_state = `STATE_IDLE;\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:50: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   next_state = `STATE_IDLE;\n                           ^\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:54: Define or directive not defined: \'`STATE_IDLE\'\n    `STATE_IDLE: \n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:54: syntax error, unexpected \':\', expecting endcase\n    `STATE_IDLE: \n               ^\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:56: Define or directive not defined: \'`DEBUG\'\n     if(`DEBUG)\n        ^~~~~~\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:63: Define or directive not defined: \'`STATE_COMPARE\'\n      next_state = `STATE_COMPARE;\n                   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:63: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      next_state = `STATE_COMPARE;\n                                 ^\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:65: Define or directive not defined: \'`STATE_IDLE\'\n      next_state = `STATE_IDLE;\n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:65: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      next_state = `STATE_IDLE;\n                              ^\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:68: Define or directive not defined: \'`STATE_COMPARE\'\n    `STATE_COMPARE:\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:69: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n    begin\n    ^~~~~\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:70: Define or directive not defined: \'`DEBUG\'\n     if(`DEBUG)\n        ^~~~~~\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:74: Define or directive not defined: \'`STATE_WRITE_HIT\'\n       next_state = `STATE_WRITE_HIT; \n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:74: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       next_state = `STATE_WRITE_HIT; \n                                    ^\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:76: Define or directive not defined: \'`STATE_IDLE\'\n       next_state = `STATE_IDLE;\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:76: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       next_state = `STATE_IDLE;\n                               ^\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:78: Define or directive not defined: \'`DEBUG\'\n       if(`DEBUG)\n          ^~~~~~\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:78: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n       if(`DEBUG)\n                ^\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:84: Define or directive not defined: \'`STATE_WRITE_BACK\'\n       next_state = `STATE_WRITE_BACK;\n                    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:84: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       next_state = `STATE_WRITE_BACK;\n                                     ^\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:86: Define or directive not defined: \'`STATE_WRITE_MISS\'\n       next_state = `STATE_WRITE_MISS;\n                    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:86: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       next_state = `STATE_WRITE_MISS;\n                                     ^\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:88: Define or directive not defined: \'`STATE_READ_MISS\'\n       next_state = `STATE_READ_MISS;\n                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:88: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       next_state = `STATE_READ_MISS;\n                                    ^\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:92: Define or directive not defined: \'`STATE_READ_MISS\'\n    `STATE_READ_MISS:\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:93: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n    begin\n    ^~~~~\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:94: Define or directive not defined: \'`DEBUG\'\n     if(`DEBUG)\n        ^~~~~~\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:98: Define or directive not defined: \'`STATE_READ_DATA\'\n      next_state = `STATE_READ_DATA;\n                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:98: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      next_state = `STATE_READ_DATA;\n                                   ^\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:100: Define or directive not defined: \'`STATE_READ_MEM\'\n      next_state = `STATE_READ_MEM;\n                   ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:100: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      next_state = `STATE_READ_MEM;\n                                  ^\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:103: Define or directive not defined: \'`STATE_READ_DATA\'\n    `STATE_READ_DATA:\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:104: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n    begin\n    ^~~~~\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:105: Define or directive not defined: \'`DEBUG\'\n     if(`DEBUG)\n        ^~~~~~\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:108: Define or directive not defined: \'`STATE_IDLE\'\n     next_state = `STATE_IDLE;\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:108: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n     next_state = `STATE_IDLE;\n                             ^\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:111: Define or directive not defined: \'`STATE_WRITE_HIT\'\n    `STATE_WRITE_HIT:\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:112: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n    begin\n    ^~~~~\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:113: Define or directive not defined: \'`DEBUG\'\n     if(`DEBUG)\n        ^~~~~~\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:116: Define or directive not defined: \'`STATE_IDLE\'\n      next_state = `STATE_IDLE;\n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:116: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      next_state = `STATE_IDLE;\n                              ^\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:119: Define or directive not defined: \'`STATE_WRITE_MISS\'\n    `STATE_WRITE_MISS:\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:120: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n    begin\n    ^~~~~\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:121: Define or directive not defined: \'`DEBUG\'\n     if(`DEBUG)\n        ^~~~~~\n%Error: data/full_repos/permissive/46343463/src/L1_Cache_Controller_rework.v:125: Define or directive not defined: \'`STATE_WRITE_DATA\'\n      next_state = `STATE_WRITE_DATA;\n                   ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module L1_Cache_Controller (
	input			clk,
	input			rst,
	

	input			cache_cs,
	input			cache_we,
	output 			cache_ack,


	input			cache_hit,
	output reg		sram_we,
	input			cache_valid,
	input			cache_dirty_i,
	output reg		cache_dirty_o,
	output reg		sram_data_sel,
	

	output reg		dram_cs,
	output reg		dram_we,
	input 			dram_ack
);
	

	reg	[3:0]	state;	
	reg	[3:0]	next_state;

	reg			cache_ack_en;
	reg			r_cache_ack;
	
	reg			r_cache_cs;
	reg			r_cache_we;

	initial begin	
		state		= `STATE_IDLE;
		next_state 	= `STATE_IDLE;
	end


	assign cache_ack = (cache_ack_en && cache_hit && cache_valid && cache_we) || r_cache_ack;


	always @ (posedge clk) begin
		state = next_state;
		UpdateSignals(state);
		
		if(~rst) begin	
			next_state = `STATE_IDLE;
		end
		else begin
			case(state)
				`STATE_IDLE: 
				begin
					if(`DEBUG)
						$display(" -> IDLE", $time);
					
					r_cache_cs = cache_cs;
					r_cache_we = cache_we;
	
					if(r_cache_cs || r_cache_we)
						next_state = `STATE_COMPARE;
					else
						next_state = `STATE_IDLE;
				end

				`STATE_COMPARE:
				begin
					if(`DEBUG)
						$display(" -> COMPARE ", $time);
					if(cache_hit && cache_valid) begin
						if(r_cache_we)
							next_state = `STATE_WRITE_HIT;	
						else begin
							next_state = `STATE_IDLE;
							
							if(`DEBUG)
								$display(" ... READ HIT");
						end
					end
					else begin
						if(cache_valid && cache_dirty_i)
							next_state = `STATE_WRITE_BACK;
						else if(r_cache_we)
							next_state = `STATE_WRITE_MISS;
						else
							next_state = `STATE_READ_MISS;
					end
				end
		
				`STATE_READ_MISS:
				begin
					if(`DEBUG)
						$display(" ... READ MISS", $time);

					if(dram_ack)
						next_state = `STATE_READ_DATA;
					else
						next_state = `STATE_READ_MEM;
				end
				
				`STATE_READ_DATA:
				begin
					if(`DEBUG)
						$display(" -> READ DATA", $time);
				
					next_state = `STATE_IDLE;
				end
				
				`STATE_WRITE_HIT:
				begin
					if(`DEBUG)
						$display(" ... WRITE HIT", $time);
					
						next_state = `STATE_IDLE;
				end
	
				`STATE_WRITE_MISS:
				begin
					if(`DEBUG)
						$display(" ... WRITE MISS", $time);
					
					if(dram_ack)
						next_state = `STATE_WRITE_DATA;
					else
						next_state = `STATE_WRITE_MISS;
				end

				`STATE_WRITE_DATA:
				begin
					if(`DEBUG)
						$display(" -> WRITE DATA", $time);

					next_state = `STATE_WRITE_HIT;
				end

				`STATE_WRITE_BACK:
				begin
					if(`DEBUG)
						$display(" -> WRITE BACK", $time);

					if(dram_ack)
						next_state = `STATE_COMPARE;
					else
						next_state = `STATE_WRITE_BACK;
				end
								
			endcase
		end
	end

	task UpdateSignals (
		input	[3:0]	state
	);

		case(state)
			`STATE_IDLE:      		ApplySignals({2'b11, 3'b000, 2'b00});
	      	`STATE_COMPARE:      	ApplySignals({2'b00, 3'b000, 2'b00});
	     	`STATE_READ_MISS:  		ApplySignals({2'b00, 3'b000, 2'b10}); 
	     	`STATE_READ_DATA:  		ApplySignals({2'b00, 3'b101, 2'b00});
	     	`STATE_WRITE_HIT:  		ApplySignals({2'b00, 3'b110, 2'b00});
	     	`STATE_WRITE_MISS: 		ApplySignals({2'b00, 3'b000, 2'b10});
	     	`STATE_WRITE_DATA: 		ApplySignals({2'b00, 3'b101, 2'b00});
	     	`STATE_WRITE_BACK:		ApplySignals({2'b00, 3'b000, 2'b11}); 
		endcase

	endtask

	task ApplySignals (
		input	[6:0]	sig_vector
	);

		begin

			cache_ack_en	= sig_vector[6];
			r_cache_ack		= sig_vector[5];
	

			sram_we			= sig_vector[4];
			cache_dirty_o	= sig_vector[3];
			sram_data_sel	= sig_vector[2];
	

			dram_cs			= sig_vector[1];
			dram_we			= sig_vector[0];
		end
	endtask

endmodule
module L1_Cache_Controller (
	input			clk,
	input			rst,
	

	input			cache_cs,
	input			cache_we,
	output 			cache_ack,


	input			cache_hit,
	output reg		sram_we,
	input			cache_valid,
	input			cache_dirty_i,
	output reg		cache_dirty_o,
	output reg		sram_data_sel,
	

	output reg		dram_cs,
	output reg		dram_we,
	input 			dram_ack
);

	

	reg	[3:0]	state;	
	reg	[3:0]	next_state;

	reg			cache_ack_en;
	reg			r_cache_ack;
	
	reg			r_cache_cs;
	reg			r_cache_we;

	initial begin	
		state		= `STATE_IDLE;
		next_state 	= `STATE_IDLE;
	end


	assign cache_ack = (cache_ack_en && cache_hit && cache_valid && cache_we) || r_cache_ack;


	always @ (posedge clk) begin
		state = next_state;
		UpdateSignals(state);
		
		if(~rst) begin	
			next_state = `STATE_IDLE;
		end
		else begin
			case(state)
				`STATE_IDLE: 
				begin
					if(`DEBUG)
						$display(" -> IDLE", $time);
					
					r_cache_cs = cache_cs;
					r_cache_we = cache_we;
	
					if(r_cache_cs || r_cache_we)
						next_state = `STATE_COMPARE;
					else
						next_state = `STATE_IDLE;
				end

				`STATE_COMPARE:
				begin
					if(`DEBUG)
						$display(" -> COMPARE ", $time);
					if(cache_hit && cache_valid) begin
						if(r_cache_we)
							next_state = `STATE_WRITE_HIT;	
						else begin
							next_state = `STATE_IDLE;
							
							if(`DEBUG)
								$display(" ... READ HIT");
						end
					end
					else begin
						if(cache_valid && cache_dirty_i)
							next_state = `STATE_WRITE_BACK;
						else if(r_cache_we)
							next_state = `STATE_WRITE_MISS;
						else
							next_state = `STATE_READ_MISS;
					end
				end
		
				`STATE_READ_MISS:
				begin
					if(`DEBUG)
						$display(" ... READ MISS", $time);

					if(dram_ack)
						next_state = `STATE_READ_DATA;
					else
						next_state = `STATE_READ_MEM;
				end
				
				`STATE_READ_DATA:
				begin
					if(`DEBUG)
						$display(" -> READ DATA", $time);
				
					next_state = `STATE_IDLE;
				end
				
				`STATE_WRITE_HIT:
				begin
					if(`DEBUG)
						$display(" ... WRITE HIT", $time);
					
						next_state = `STATE_IDLE;
				end
	
				`STATE_WRITE_MISS:
				begin
					if(`DEBUG)
						$display(" ... WRITE MISS", $time);
					
					if(dram_ack)
						next_state = `STATE_WRITE_DATA;
					else
						next_state = `STATE_WRITE_MISS;
				end

				`STATE_WRITE_DATA:
				begin
					if(`DEBUG)
						$display(" -> WRITE DATA", $time);

					next_state = `STATE_WRITE_HIT;
				end

				`STATE_WRITE_BACK:
				begin
					if(`DEBUG)
						$display(" -> WRITE BACK", $time);

					if(dram_ack)
						next_state = `STATE_COMPARE;
					else
						next_state = `STATE_WRITE_BACK;
				end
								
			endcase
		end
	end

	task UpdateSignals (
		input	[3:0]	state
	);

		case(state)
			`STATE_IDLE:      		ApplySignals({2'b11, 3'b000, 2'b00});
	      	`STATE_COMPARE:      	ApplySignals({2'b00, 3'b000, 2'b00});
	     	`STATE_READ_MISS:  		ApplySignals({2'b00, 3'b000, 2'b10}); 
	     	`STATE_READ_DATA:  		ApplySignals({2'b00, 3'b101, 2'b00});
	     	`STATE_WRITE_HIT:  		ApplySignals({2'b00, 3'b110, 2'b00});
	     	`STATE_WRITE_MISS: 		ApplySignals({2'b00, 3'b000, 2'b10});
	     	`STATE_WRITE_DATA: 		ApplySignals({2'b00, 3'b101, 2'b00});
	     	`STATE_WRITE_BACK:		ApplySignals({2'b00, 3'b000, 2'b11}); 
		endcase

	endtask

	task ApplySignals (
		input	[6:0]	sig_vector
	);

		begin

			cache_ack_en	= sig_vector[6];
			r_cache_ack		= sig_vector[5];
	

			sram_we			= sig_vector[4];
			cache_dirty_o	= sig_vector[3];
			sram_data_sel	= sig_vector[2];
	

			dram_cs			= sig_vector[1];
			dram_we			= sig_vector[0];
		end
	endtask

endmodule