data/full_repos/permissive/415843050/cpu-src/ifetch.v
data/verilator_xmls/9639e84b-0fcd-40e9-896b-fa868761153d.xml
module Ifetch(
    Instruction,Instruction_ex_mem,
    PC_plus_4,PC_plus_4_latch,
    clock,reset,
    Jr,Jalr,Jmp,Jal,
    Beq,Bne,Bgez,Bgtz,Blez,Bltz,Bgezal,Bltzal,
    Zero,Positive,Negative,
    PC_add_result,Read_data_rs,
    Rom_adr_o,Jpadr,
    PC_exception,
    Nonflush_ex_mem,PC_plus_4_id_ex,flush_pipeline
    );
    
    output[31:0]    Instruction;
    input[31:0]     Instruction_ex_mem;
    output[31:0]    PC_plus_4;
    output[31:0]    PC_plus_4_latch;
    
    input   clock;
    input   reset;
    input   Jr,Jalr,Jmp,Jal;
    input   Beq,Bne,Bgez,Bgtz,Blez,Bltz,Bgezal,Bltzal;
    input   Zero;
    input   Positive;
    input   Negative;
    input[31:0] PC_add_result;
    input[31:0] Read_data_rs;
    

    output[13:0]    Rom_adr_o;
    input[31:0] Jpadr;
    
    input[31:0] PC_exception;
    
    input   Nonflush_ex_mem;
    input[31:0] PC_plus_4_id_ex;
    output  flush_pipeline;
    
    wire[31:0]  Instruction;
    
    reg[31:0]   PC;
    reg[31:0]   jump_PC;
    reg[31:0]   next_PC;
    reg[31:0]   PC_plus_4_latch;
    
    reg         flush_pipeline;
    

    

    assign Rom_adr_o = PC[15:2];
    assign Instruction = Jpadr;
    
    assign PC_plus_4 = {PC[31:2] + 1'b1,2'b00};
    

    always @(posedge clock)
    begin
        jump_PC = (Beq && Zero) || (Bne && !Zero) ||
                  (Bgez && !Negative) || (Bgtz && Positive) ||
                  (Blez && !Positive) || (Bltz && Negative) ||
                  (Bgezal && !Negative) || (Bltzal && Negative)
                  ? PC_add_result
                  : (
                        Jmp || Jal
                        ? Instruction_ex_mem & 32'h03FFFFFF
                        : (
                              Jr || Jalr
                              ? Read_data_rs >> 2
                              : (
                                    PC_exception == 32'hFFFFFFFF
                                    ? 32'hFFFFFFFF
                                    : PC_exception >> 2
                                )
                          )
                    );
        next_PC = (jump_PC == 32'hFFFFFFFF) ? PC_plus_4 >> 2 : jump_PC;
        flush_pipeline = (
                             jump_PC != 32'hFFFFFFFF ||
                             (Nonflush_ex_mem && (next_PC << 2) != PC_plus_4_id_ex + 8)
                         )
                         ? 1'b1 : 1'b0;
    end
    

    always @(negedge clock)
    begin
        if (Jal || Jalr)
            PC_plus_4_latch = PC_plus_4;
        PC = reset ? 32'h00000000 : next_PC << 2;
    end
    
endmodule
module Ifetch(
    Instruction,Instruction_ex_mem,
    PC_plus_4,PC_plus_4_latch,
    clock,reset,
    Jr,Jalr,Jmp,Jal,
    Beq,Bne,Bgez,Bgtz,Blez,Bltz,Bgezal,Bltzal,
    Zero,Positive,Negative,
    PC_add_result,Read_data_rs,
    Rom_adr_o,Jpadr,
    PC_exception,
    Nonflush_ex_mem,PC_plus_4_id_ex,flush_pipeline
    );

    
    output[31:0]    Instruction;
    input[31:0]     Instruction_ex_mem;
    output[31:0]    PC_plus_4;
    output[31:0]    PC_plus_4_latch;
    
    input   clock;
    input   reset;
    input   Jr,Jalr,Jmp,Jal;
    input   Beq,Bne,Bgez,Bgtz,Blez,Bltz,Bgezal,Bltzal;
    input   Zero;
    input   Positive;
    input   Negative;
    input[31:0] PC_add_result;
    input[31:0] Read_data_rs;
    

    output[13:0]    Rom_adr_o;
    input[31:0] Jpadr;
    
    input[31:0] PC_exception;
    
    input   Nonflush_ex_mem;
    input[31:0] PC_plus_4_id_ex;
    output  flush_pipeline;
    
    wire[31:0]  Instruction;
    
    reg[31:0]   PC;
    reg[31:0]   jump_PC;
    reg[31:0]   next_PC;
    reg[31:0]   PC_plus_4_latch;
    
    reg         flush_pipeline;
    

    

    assign Rom_adr_o = PC[15:2];
    assign Instruction = Jpadr;
    
    assign PC_plus_4 = {PC[31:2] + 1'b1,2'b00};
    

    always @(posedge clock)
    begin
        jump_PC = (Beq && Zero) || (Bne && !Zero) ||
                  (Bgez && !Negative) || (Bgtz && Positive) ||
                  (Blez && !Positive) || (Bltz && Negative) ||
                  (Bgezal && !Negative) || (Bltzal && Negative)
                  ? PC_add_result
                  : (
                        Jmp || Jal
                        ? Instruction_ex_mem & 32'h03FFFFFF
                        : (
                              Jr || Jalr
                              ? Read_data_rs >> 2
                              : (
                                    PC_exception == 32'hFFFFFFFF
                                    ? 32'hFFFFFFFF
                                    : PC_exception >> 2
                                )
                          )
                    );
        next_PC = (jump_PC == 32'hFFFFFFFF) ? PC_plus_4 >> 2 : jump_PC;
        flush_pipeline = (
                             jump_PC != 32'hFFFFFFFF ||
                             (Nonflush_ex_mem && (next_PC << 2) != PC_plus_4_id_ex + 8)
                         )
                         ? 1'b1 : 1'b0;
    end
    

    always @(negedge clock)
    begin
        if (Jal || Jalr)
            PC_plus_4_latch = PC_plus_4;
        PC = reset ? 32'h00000000 : next_PC << 2;
    end
    
endmodule