data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/corexxx/rsinv.v
data/verilator_xmls/e707ec0e-36ac-4d85-8826-5ad016b46234.xml
module rsinv
    (
     clk,
     rst,

     ramra,
     ramwd,
     ramwa,
     ramwe,
     

     acen_i,
     acen_r,
     acen_s,
     rsidone,

     aen,
     aop,
     adi,
     adivld
     );



parameter WID = 256;
parameter AWID = 5;

localparam          X_G     = 0;
localparam          Y_G     = 1;
localparam          X_3G    = 2;
localparam          Y_3G    = 3;
localparam          Z_3G    = 3;
localparam          X_5G    = 5;
localparam          Y_5G    = 6;
localparam          Z_5G    = 7;
localparam          X_7G    = 8;
localparam          Y_7G    = 9;
localparam          Z_7G    = 10;

localparam          K_NUM   = 11;
localparam          K_INV   = 12;
localparam          R_NUM   = 13;
localparam          S_NUM   = 14;
localparam          X_KG    = 15;
localparam          HASH    = 16;
localparam          PRKEY   = 17;
localparam          ZRRAM   = 18;
localparam          ONERAM  = 19;

localparam          S_RP    = 29;
localparam          S_RPH   = 30;
localparam          BLNK    = 31;

localparam FA  = 2'b00;
localparam MUL = 2'b01;
localparam INV = 2'b10;

localparam IDLE = 2'b00;
localparam RPRO = 2'b01;
localparam SPRO = 2'b10;
localparam IPRO = 2'b11;

localparam RIDLE = 2'b00;
localparam RCAL1 = 2'b01;
localparam RCAL2 = 2'b10;

localparam SIDLE  = 3'b000;
localparam SRP1   = 3'b001;
localparam SRP2   = 3'b010;
localparam SRPH1  = 3'b011;
localparam SRPH2  = 3'b100;
localparam SRPHK1 = 3'b101;
localparam SRPHK2 = 3'b110;

localparam IIDLE = 1'b0;
localparam ICAL = 1'b1;




input clk;
input rst;

output [AWID-1:0] ramra;
output [WID-1:0]  ramwd;
output [AWID-1:0] ramwa;
output            ramwe;

input             acen_i;
input             acen_r;
input             acen_s;
output            rsidone;

output            aen;
output [1:0]      aop;
input [WID-1:0]   adi;
input             adivld;












reg [1:0]         mainfsm;

wire              mainidle;

assign            mainidle = mainfsm == IDLE;


always@(posedge clk)
    begin
    if(rst)
        begin
        mainfsm <= IDLE;
        end
    else
        begin
        if(acen_i & mainidle)
            begin
            mainfsm <= IPRO;
            end
        else if(acen_r & mainidle)
            begin
            mainfsm <= RPRO;
            end
        else if(acen_s & mainidle)
            begin
            mainfsm <= SPRO;
            end
        else if(rsidone & !mainidle)
            begin
            mainfsm <= IDLE;
            end
        else
            begin
            mainfsm <= mainfsm;
            end
        end
    end


reg [1:0] rfsm;

reg       rdone;


reg      rproen;

always@(posedge clk)
    begin
    if(rst)
        rproen <= 1'b0;
    else
        if(acen_r)
            rproen <= 1'b1;
        else
            rproen <= 1'b0;
    end


wire      riscal1;

assign    riscal1 = rfsm == RCAL1;

wire      riscal2;

assign    riscal2 = rfsm == RCAL2;

wire      rprovld;

assign    rprovld = riscal2 & adivld;


reg       raen;


always@(posedge clk)
    begin
    if(rst)
        begin
        rfsm <= RIDLE;
        raen <= 1'b0;
        rdone <= 1'b0;
        end
    else
        begin
        if(rproen)
            begin
            rfsm <= RCAL1;
            raen <= 1'b0;
            rdone <= 1'b0;
            end
        else if(riscal1)
            begin
            rfsm <= RCAL2;
            raen <= 1'b1;
            rdone <= 1'b0;
            end
        else if(rprovld)
            begin
            rfsm <= RIDLE;
            raen <= 1'b0;
            rdone <= 1'b1;
            end
        else
            begin
            rfsm <= rfsm;
            raen <= 1'b0;
            rdone <= 1'b0;
            end
        end
    end



reg sdone;

reg [2:0] sfsm;


reg      sproen;

always@(posedge clk)
    begin
    if(rst)
        sproen <= 1'b0;
    else
        if(acen_s)
            sproen <= 1'b1;
        else
            sproen <= 1'b0;
    end

wire sisrp1;

assign sisrp1 = sfsm == SRP1;

wire   sisrp2;

assign sisrp2 = sfsm == SRP2;

wire   srpvld;

assign srpvld = sisrp2 & adivld;

wire   sisrph1;

assign sisrph1 = sfsm == SRPH1;

wire   sisrph2;

assign sisrph2 = sfsm == SRPH2;

wire   srphvld;

assign srphvld = sisrph2 & adivld;

wire   sisrphk1;

assign sisrphk1 = sfsm == SRPHK1;

wire   sisrphk2;

assign sisrphk2 = sfsm == SRPHK2;

wire   srphkvld;

assign srphkvld = sisrphk2 & adivld;


reg    saen;


always@(posedge clk)
    begin
    if(rst)
        begin
        sfsm <= SIDLE;
        saen <= 1'b0;
        sdone <= 1'b0;
        end
    else
        begin
        if(sproen)
            begin
            sfsm <= SRP1;
            saen <= 1'b0;
            sdone <= 1'b0;
            end
        else if(sisrp1)
            begin
            sfsm <= SRP2;
            saen <= 1'b1;
            sdone <= 1'b0;
            end
        else if(srpvld)
            begin
            sfsm <= SRPH1;
            saen <= 1'b0;
            sdone <= 1'b0;
            end
        else if(sisrph1)
            begin
            sfsm <= SRPH2;
            saen <= 1'b1;
            sdone <= 1'b0;
            end
        else if(srphvld)
            begin
            sfsm <= SRPHK1;
            saen <= 1'b0;
            sdone <= 1'b0;
            end
        else if(sisrphk1)
            begin
            sfsm <= SRPHK2;
            saen <= 1'b1;
            sdone <= 1'b0;
            end
        else if(srphkvld)
            begin
            sfsm <= SIDLE;
            saen <= 1'b0;
            sdone <= 1'b1;
            end
        else
            begin
            sfsm <= sfsm;
            saen <= 1'b0;
            sdone <= 1'b0;
            end
        end
    end


reg idone;

reg ifsm;


reg      iproen;

always@(posedge clk)
    begin
    if(rst)
        iproen <= 1'b0;
    else
        if(acen_i)
            iproen <= 1'b1;
        else
            iproen <= 1'b0;
    end

wire iiscal;

assign iiscal = ifsm == ICAL;

wire   iprovld;

assign iprovld = iiscal & adivld;


reg iaen;


always@(posedge clk)
    begin
    if(rst)
        begin
        ifsm <= IIDLE;
        iaen <= 1'b0;
        idone <= 1'b0;
        end
    else
        begin
        if(iproen)
            begin
            ifsm <= ICAL;
            iaen <= 1'b1;
            idone <= 1'b0;
            end
        else if(iprovld)
            begin
            ifsm <= IIDLE;
            iaen <= 1'b0;
            idone <= 1'b1;
            end
        else
            begin
            ifsm <= ifsm;
            iaen <= 1'b0;
            idone <= 1'b0;
            end
        end
    end














reg [AWID-1:0] ramra;

always@(posedge clk)
    begin
    ramra <= riscal1? X_KG :
             riscal2? ZRRAM:
             sisrp1? R_NUM :
             sisrp2? PRKEY :
             sisrph1? S_RP :
             sisrph2? HASH :
             sisrphk1?S_RPH:
             sisrphk2?K_INV:
             iiscal? K_NUM :
             ZRRAM;
    end

reg [WID-1:0] ramwd;

always@(posedge clk)
    begin
    ramwd <= adi;
    end








reg [AWID-1:0] ramwa;

always@(posedge clk)
    begin
    ramwa <= rprovld? R_NUM :
             srpvld? S_RP   : 
             srphvld? S_RPH :
             srphkvld? S_NUM:
             iprovld? K_INV :
             BLNK;
    end


reg ramwe;

always@(posedge clk)
    begin
    ramwe <= rprovld | srpvld | srphvld | srphkvld | iprovld;
    end


assign aen = raen | iaen | saen;



assign aop = riscal2? FA :
       sisrp2? MUL  :
       sisrph2? FA  :
       sisrphk2? MUL:
       iiscal? INV  :
       FA;



assign rsidone = idone | sdone | rdone;

endmodule
module rsinv
    (
     clk,
     rst,

     ramra,
     ramwd,
     ramwa,
     ramwe,
     

     acen_i,
     acen_r,
     acen_s,
     rsidone,

     aen,
     aop,
     adi,
     adivld
     );




parameter WID = 256;
parameter AWID = 5;

localparam          X_G     = 0;
localparam          Y_G     = 1;
localparam          X_3G    = 2;
localparam          Y_3G    = 3;
localparam          Z_3G    = 3;
localparam          X_5G    = 5;
localparam          Y_5G    = 6;
localparam          Z_5G    = 7;
localparam          X_7G    = 8;
localparam          Y_7G    = 9;
localparam          Z_7G    = 10;

localparam          K_NUM   = 11;
localparam          K_INV   = 12;
localparam          R_NUM   = 13;
localparam          S_NUM   = 14;
localparam          X_KG    = 15;
localparam          HASH    = 16;
localparam          PRKEY   = 17;
localparam          ZRRAM   = 18;
localparam          ONERAM  = 19;

localparam          S_RP    = 29;
localparam          S_RPH   = 30;
localparam          BLNK    = 31;

localparam FA  = 2'b00;
localparam MUL = 2'b01;
localparam INV = 2'b10;

localparam IDLE = 2'b00;
localparam RPRO = 2'b01;
localparam SPRO = 2'b10;
localparam IPRO = 2'b11;

localparam RIDLE = 2'b00;
localparam RCAL1 = 2'b01;
localparam RCAL2 = 2'b10;

localparam SIDLE  = 3'b000;
localparam SRP1   = 3'b001;
localparam SRP2   = 3'b010;
localparam SRPH1  = 3'b011;
localparam SRPH2  = 3'b100;
localparam SRPHK1 = 3'b101;
localparam SRPHK2 = 3'b110;

localparam IIDLE = 1'b0;
localparam ICAL = 1'b1;




input clk;
input rst;

output [AWID-1:0] ramra;
output [WID-1:0]  ramwd;
output [AWID-1:0] ramwa;
output            ramwe;

input             acen_i;
input             acen_r;
input             acen_s;
output            rsidone;

output            aen;
output [1:0]      aop;
input [WID-1:0]   adi;
input             adivld;












reg [1:0]         mainfsm;

wire              mainidle;

assign            mainidle = mainfsm == IDLE;


always@(posedge clk)
    begin
    if(rst)
        begin
        mainfsm <= IDLE;
        end
    else
        begin
        if(acen_i & mainidle)
            begin
            mainfsm <= IPRO;
            end
        else if(acen_r & mainidle)
            begin
            mainfsm <= RPRO;
            end
        else if(acen_s & mainidle)
            begin
            mainfsm <= SPRO;
            end
        else if(rsidone & !mainidle)
            begin
            mainfsm <= IDLE;
            end
        else
            begin
            mainfsm <= mainfsm;
            end
        end
    end


reg [1:0] rfsm;

reg       rdone;


reg      rproen;

always@(posedge clk)
    begin
    if(rst)
        rproen <= 1'b0;
    else
        if(acen_r)
            rproen <= 1'b1;
        else
            rproen <= 1'b0;
    end


wire      riscal1;

assign    riscal1 = rfsm == RCAL1;

wire      riscal2;

assign    riscal2 = rfsm == RCAL2;

wire      rprovld;

assign    rprovld = riscal2 & adivld;


reg       raen;


always@(posedge clk)
    begin
    if(rst)
        begin
        rfsm <= RIDLE;
        raen <= 1'b0;
        rdone <= 1'b0;
        end
    else
        begin
        if(rproen)
            begin
            rfsm <= RCAL1;
            raen <= 1'b0;
            rdone <= 1'b0;
            end
        else if(riscal1)
            begin
            rfsm <= RCAL2;
            raen <= 1'b1;
            rdone <= 1'b0;
            end
        else if(rprovld)
            begin
            rfsm <= RIDLE;
            raen <= 1'b0;
            rdone <= 1'b1;
            end
        else
            begin
            rfsm <= rfsm;
            raen <= 1'b0;
            rdone <= 1'b0;
            end
        end
    end



reg sdone;

reg [2:0] sfsm;


reg      sproen;

always@(posedge clk)
    begin
    if(rst)
        sproen <= 1'b0;
    else
        if(acen_s)
            sproen <= 1'b1;
        else
            sproen <= 1'b0;
    end

wire sisrp1;

assign sisrp1 = sfsm == SRP1;

wire   sisrp2;

assign sisrp2 = sfsm == SRP2;

wire   srpvld;

assign srpvld = sisrp2 & adivld;

wire   sisrph1;

assign sisrph1 = sfsm == SRPH1;

wire   sisrph2;

assign sisrph2 = sfsm == SRPH2;

wire   srphvld;

assign srphvld = sisrph2 & adivld;

wire   sisrphk1;

assign sisrphk1 = sfsm == SRPHK1;

wire   sisrphk2;

assign sisrphk2 = sfsm == SRPHK2;

wire   srphkvld;

assign srphkvld = sisrphk2 & adivld;


reg    saen;


always@(posedge clk)
    begin
    if(rst)
        begin
        sfsm <= SIDLE;
        saen <= 1'b0;
        sdone <= 1'b0;
        end
    else
        begin
        if(sproen)
            begin
            sfsm <= SRP1;
            saen <= 1'b0;
            sdone <= 1'b0;
            end
        else if(sisrp1)
            begin
            sfsm <= SRP2;
            saen <= 1'b1;
            sdone <= 1'b0;
            end
        else if(srpvld)
            begin
            sfsm <= SRPH1;
            saen <= 1'b0;
            sdone <= 1'b0;
            end
        else if(sisrph1)
            begin
            sfsm <= SRPH2;
            saen <= 1'b1;
            sdone <= 1'b0;
            end
        else if(srphvld)
            begin
            sfsm <= SRPHK1;
            saen <= 1'b0;
            sdone <= 1'b0;
            end
        else if(sisrphk1)
            begin
            sfsm <= SRPHK2;
            saen <= 1'b1;
            sdone <= 1'b0;
            end
        else if(srphkvld)
            begin
            sfsm <= SIDLE;
            saen <= 1'b0;
            sdone <= 1'b1;
            end
        else
            begin
            sfsm <= sfsm;
            saen <= 1'b0;
            sdone <= 1'b0;
            end
        end
    end


reg idone;

reg ifsm;


reg      iproen;

always@(posedge clk)
    begin
    if(rst)
        iproen <= 1'b0;
    else
        if(acen_i)
            iproen <= 1'b1;
        else
            iproen <= 1'b0;
    end

wire iiscal;

assign iiscal = ifsm == ICAL;

wire   iprovld;

assign iprovld = iiscal & adivld;


reg iaen;


always@(posedge clk)
    begin
    if(rst)
        begin
        ifsm <= IIDLE;
        iaen <= 1'b0;
        idone <= 1'b0;
        end
    else
        begin
        if(iproen)
            begin
            ifsm <= ICAL;
            iaen <= 1'b1;
            idone <= 1'b0;
            end
        else if(iprovld)
            begin
            ifsm <= IIDLE;
            iaen <= 1'b0;
            idone <= 1'b1;
            end
        else
            begin
            ifsm <= ifsm;
            iaen <= 1'b0;
            idone <= 1'b0;
            end
        end
    end














reg [AWID-1:0] ramra;

always@(posedge clk)
    begin
    ramra <= riscal1? X_KG :
             riscal2? ZRRAM:
             sisrp1? R_NUM :
             sisrp2? PRKEY :
             sisrph1? S_RP :
             sisrph2? HASH :
             sisrphk1?S_RPH:
             sisrphk2?K_INV:
             iiscal? K_NUM :
             ZRRAM;
    end

reg [WID-1:0] ramwd;

always@(posedge clk)
    begin
    ramwd <= adi;
    end








reg [AWID-1:0] ramwa;

always@(posedge clk)
    begin
    ramwa <= rprovld? R_NUM :
             srpvld? S_RP   : 
             srphvld? S_RPH :
             srphkvld? S_NUM:
             iprovld? K_INV :
             BLNK;
    end


reg ramwe;

always@(posedge clk)
    begin
    ramwe <= rprovld | srpvld | srphvld | srphkvld | iprovld;
    end


assign aen = raen | iaen | saen;



assign aop = riscal2? FA :
       sisrp2? MUL  :
       sisrph2? FA  :
       sisrphk2? MUL:
       iiscal? INV  :
       FA;



assign rsidone = idone | sdone | rdone;

endmodule