data/full_repos/permissive/494696040/ALU.v
data/verilator_xmls/8a6a342d-e883-4227-b623-32febcb62915.xml
module ALU(
    input [31:0] A,
    input [31:0] B,
    output reg [31:0] ALU_Result,
    input [3:0] ALU_op,
    output reg zero
    );
    


    always @(A, B, ALU_op)
    begin
        case(ALU_op)
            4'b0000: ALU_Result <= A & B;
            4'b0001: ALU_Result <= A | B;
            4'b0010: ALU_Result <= A + B;
            4'b0110: ALU_Result <= A + (~B + 1);
            4'b0111: ALU_Result <= (A < B) ? 32'd1 : 32'd0;
            4'b1100: ALU_Result <= ~(A | B);
        endcase
    end
    

    always @(ALU_Result)
    begin
        if(ALU_Result == 32'd0) zero <= 1'b1;
        else zero <= 1'b0;
    end
endmodule
module ALU(
    input [31:0] A,
    input [31:0] B,
    output reg [31:0] ALU_Result,
    input [3:0] ALU_op,
    output reg zero
    );

    


    always @(A, B, ALU_op)
    begin
        case(ALU_op)
            4'b0000: ALU_Result <= A & B;
            4'b0001: ALU_Result <= A | B;
            4'b0010: ALU_Result <= A + B;
            4'b0110: ALU_Result <= A + (~B + 1);
            4'b0111: ALU_Result <= (A < B) ? 32'd1 : 32'd0;
            4'b1100: ALU_Result <= ~(A | B);
        endcase
    end
    

    always @(ALU_Result)
    begin
        if(ALU_Result == 32'd0) zero <= 1'b1;
        else zero <= 1'b0;
    end
endmodule