data/full_repos/permissive/43858668/final_verilog/src/clib/c_prefix_arbiter_base.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/43858668/final_verilog/src/clib/c_prefix_arbiter_base.v:39: Little bit endian vector: MSB < LSB of bit range: 0:31\n   input [0:num_ports-1] prio_port;\n         ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/43858668/final_verilog/src/clib/c_prefix_arbiter_base.v:42: Little bit endian vector: MSB < LSB of bit range: 0:31\n   input [0:num_ports-1] req;\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/43858668/final_verilog/src/clib/c_prefix_arbiter_base.v:45: Little bit endian vector: MSB < LSB of bit range: 0:31\n   output [0:num_ports-1] gnt;\n          ^\n%Warning-LITENDIAN: data/full_repos/permissive/43858668/final_verilog/src/clib/c_prefix_arbiter_base.v:48: Little bit endian vector: MSB < LSB of bit range: 0:31\n   wire [0:num_ports-1]   g_in;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/43858668/final_verilog/src/clib/c_prefix_arbiter_base.v:51: Little bit endian vector: MSB < LSB of bit range: 0:31\n   wire [0:num_ports-1]   p_in;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/43858668/final_verilog/src/clib/c_prefix_arbiter_base.v:54: Little bit endian vector: MSB < LSB of bit range: 0:31\n   wire [0:num_ports-1]   g_out;\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/43858668/final_verilog/src/clib/c_prefix_arbiter_base.v:55: Little bit endian vector: MSB < LSB of bit range: 0:31\n   wire [0:num_ports-1]   p_out;\n        ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_prefix_arbiter_base.v:56: Cannot find file containing module: \'c_prefix_net\'\n   c_prefix_net\n   ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_prefix_net\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_prefix_net.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_prefix_net.sv\n             c_prefix_net\n             c_prefix_net.v\n             c_prefix_net.sv\n             obj_dir/c_prefix_net\n             obj_dir/c_prefix_net.v\n             obj_dir/c_prefix_net.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n'
module c_prefix_arbiter_base
  (prio_port, req, gnt);
   

   parameter num_ports = 32;
   

   input [0:num_ports-1] prio_port;
   

   input [0:num_ports-1] req;
   

   output [0:num_ports-1] gnt;
   wire [0:num_ports-1]   gnt;
   
   wire [0:num_ports-1]   g_in;
   assign g_in = prio_port;
   
   wire [0:num_ports-1]   p_in;
   assign p_in = ~{req[num_ports-1], req[0:num_ports-2]};
   
   wire [0:num_ports-1]   g_out;
   wire [0:num_ports-1]   p_out;
   c_prefix_net
     #(.width(num_ports),
       .enable_wraparound(1))
   g_out_pn
     (.g_in(g_in),
      .p_in(p_in),
      .g_out(g_out),
      .p_out(p_out));
   
   assign gnt = req & g_out;
   
endmodule
module c_prefix_arbiter_base
  (prio_port, req, gnt);

   

   parameter num_ports = 32;
   

   input [0:num_ports-1] prio_port;
   

   input [0:num_ports-1] req;
   

   output [0:num_ports-1] gnt;
   wire [0:num_ports-1]   gnt;
   
   wire [0:num_ports-1]   g_in;
   assign g_in = prio_port;
   
   wire [0:num_ports-1]   p_in;
   assign p_in = ~{req[num_ports-1], req[0:num_ports-2]};
   
   wire [0:num_ports-1]   g_out;
   wire [0:num_ports-1]   p_out;
   c_prefix_net
     #(.width(num_ports),
       .enable_wraparound(1))
   g_out_pn
     (.g_in(g_in),
      .p_in(p_in),
      .g_out(g_out),
      .p_out(p_out));
   
   assign gnt = req & g_out;
   
endmodule