data/full_repos/permissive/527176783/Pipeline/mux2x32.v
data/verilator_xmls/883b484d-dddd-4a14-a289-f8343af48ff5.xml
module mux2x32(
    input   wire [31:0] Qb,
    input   wire [31:0] im,
    input   wire        sel,
    output  reg [31:0]  result
);
    always @(*) begin
        case (sel)
            1'b0: result = Qb;
            1'b1: result = im;
            default: result = Qb;
        endcase
    end

endmodule
module mux2x32(
    input   wire [31:0] Qb,
    input   wire [31:0] im,
    input   wire        sel,
    output  reg [31:0]  result
);

    always @(*) begin
        case (sel)
            1'b0: result = Qb;
            1'b1: result = im;
            default: result = Qb;
        endcase
    end

endmodule