data/full_repos/permissive/487568919/basic_verilog/bin2pos.sv
data/verilator_xmls/c3d996f0-29c8-4dda-b19d-9fdd2fd4d345.xml
module bin2pos #( parameter
  BIN_WIDTH = 8,
  POS_WIDTH = 2**BIN_WIDTH
)(
  input [(BIN_WIDTH-1):0] bin,
  output logic [(POS_WIDTH-1):0] pos
);


always_comb begin
  pos = 0;
  pos[bin] = 1'b1;
end

endmodule
module bin2pos #( parameter
  BIN_WIDTH = 8,
  POS_WIDTH = 2**BIN_WIDTH
)(
  input [(BIN_WIDTH-1):0] bin,
  output logic [(POS_WIDTH-1):0] pos
);



always_comb begin
  pos = 0;
  pos[bin] = 1'b1;
end

endmodule