data/full_repos/permissive/419538859/lab7/lab7_1/lab7_1.v
1: b"%Error: data/full_repos/permissive/419538859/lab7/lab7_1/lab7_1.v:21: syntax error, unexpected '(', expecting IDENTIFIER\nfreq_div#(23)(clk, reset, clk_cnt);\n              ^~~\n%Error: data/full_repos/permissive/419538859/lab7/lab7_1/lab7_1.v:22: syntax error, unexpected '(', expecting IDENTIFIER\nfreq_div#(15)(clk, reset, clk_sel);\n              ^~~\n%Error: data/full_repos/permissive/419538859/lab7/lab7_1/lab7_1.v:24: syntax error, unexpected '(', expecting IDENTIFIER\nseg7_select#(4)(clk_sel, reset, seg7_sel);\n                ^~~~~~~\n%Error: data/full_repos/permissive/419538859/lab7/lab7_1/lab7_1.v:36: syntax error, unexpected '(', expecting IDENTIFIER\nryg_ctl (clk_cnt, reset, day_night, g1_cnt, g1_en, light_led, light_mode);\n         ^~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module 	light_cnt_dn_29(clk, reset, enable, cnt);

input	clk, reset, enable;
output	[7:0]cnt;
reg		[7:0]cnt;

always@(posedge clk or posedge reset) 
begin
	if(reset)
		cnt= 8'b0;
	else if(enable)  
		if(cnt== 8'b0)
			cnt=8'b0010_1001;
		else if(cnt[3:0] == 4'd0)
			begin
			cnt[7:4]=cnt[7:4]-4'b1; 
			cnt[3:0]=4'd9;	  
			end
			else
				cnt[3:0]=cnt[3:0]-4'd1;
		else
			cnt=8'd0;
end
endmodule
module 	light_cnt_dn_29(clk, reset, enable, cnt);


input	clk, reset, enable;
output	[7:0]cnt;
reg		[7:0]cnt;

always@(posedge clk or posedge reset) 
begin
	if(reset)
		cnt= 8'b0;
	else if(enable)  
		if(cnt== 8'b0)
			cnt=8'b0010_1001;
		else if(cnt[3:0] == 4'd0)
			begin
			cnt[7:4]=cnt[7:4]-4'b1; 
			cnt[3:0]=4'd9;	  
			end
			else
				cnt[3:0]=cnt[3:0]-4'd1;
		else
			cnt=8'd0;
end
endmodule