data/full_repos/permissive/451853158/MIPS_Multi_Cycle_Processor/mips_multi_cycle.v
1: b"%Error: data/full_repos/permissive/451853158/MIPS_Multi_Cycle_Processor/mips_multi_cycle.v:15: Cannot find file containing module: 'datapath'\ndatapath dp (.clk(clk), .reset(reset),\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/451853158/MIPS_Multi_Cycle_Processor,data/full_repos/permissive/451853158/datapath\n             data/full_repos/permissive/451853158/MIPS_Multi_Cycle_Processor,data/full_repos/permissive/451853158/datapath.v\n             data/full_repos/permissive/451853158/MIPS_Multi_Cycle_Processor,data/full_repos/permissive/451853158/datapath.sv\n             datapath\n             datapath.v\n             datapath.sv\n             obj_dir/datapath\n             obj_dir/datapath.v\n             obj_dir/datapath.sv\n%Error: data/full_repos/permissive/451853158/MIPS_Multi_Cycle_Processor/mips_multi_cycle.v:23: Cannot find file containing module: 'controlUnit'\ncontrolUnit ctrlU (.clk(clk), .reset(reset),\n^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module mips_multi_cycle (
  input clk, reset
);



wire PCEn, IorD, MemWrite, IRWrite, RegDst;
wire MemtoReg, RegWrite, ALUSrcA;
wire [1:0] PCSrc, ALUSrcB;
wire [2:0] ALUCtrl;
wire [5:0] OPCode, Funct;
wire Zero;


datapath dp (.clk(clk), .reset(reset),
             .PCEn(PCEn), .IorD(IorD), .MemWrite(MemWrite),
             .IRWrite(IRWrite), .RegDst(RegDst),
             .MemtoReg(MemtoReg), .RegWrite(RegWrite), .ALUSrcA(ALUSrcA),
             .PCSrc(PCSrc), .ALUSrcB(ALUSrcB), 
             .ALUCtrl(ALUCtrl), .OPCode(OPCode), .Funct(Funct), .Z(Zero));


controlUnit ctrlU (.clk(clk), .reset(reset),
                   .OPCode(OPCode), .Funct(Funct), .Zero(Zero),
                   .MemtoReg(MemtoReg), .RegDst(RegDst), .IorD(IorD), .ALUSrcA(ALUSrcA),
                   .PCSrc(PCSrc), .ALUSrcB(ALUSrcB),
                   .IRWrite(IRWrite), .MemWrite(MemWrite), .RegWrite(RegWrite), .PCEn(PCEn),
                   .ALUControl(ALUCtrl));

endmodule
module mips_multi_cycle (
  input clk, reset
);




wire PCEn, IorD, MemWrite, IRWrite, RegDst;
wire MemtoReg, RegWrite, ALUSrcA;
wire [1:0] PCSrc, ALUSrcB;
wire [2:0] ALUCtrl;
wire [5:0] OPCode, Funct;
wire Zero;


datapath dp (.clk(clk), .reset(reset),
             .PCEn(PCEn), .IorD(IorD), .MemWrite(MemWrite),
             .IRWrite(IRWrite), .RegDst(RegDst),
             .MemtoReg(MemtoReg), .RegWrite(RegWrite), .ALUSrcA(ALUSrcA),
             .PCSrc(PCSrc), .ALUSrcB(ALUSrcB), 
             .ALUCtrl(ALUCtrl), .OPCode(OPCode), .Funct(Funct), .Z(Zero));


controlUnit ctrlU (.clk(clk), .reset(reset),
                   .OPCode(OPCode), .Funct(Funct), .Zero(Zero),
                   .MemtoReg(MemtoReg), .RegDst(RegDst), .IorD(IorD), .ALUSrcA(ALUSrcA),
                   .PCSrc(PCSrc), .ALUSrcB(ALUSrcB),
                   .IRWrite(IRWrite), .MemWrite(MemWrite), .RegWrite(RegWrite), .PCEn(PCEn),
                   .ALUControl(ALUCtrl));

endmodule