data/full_repos/permissive/419677538/Exercise_4/verilog_code/Exe4_part1/DigSys4.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/419677538/Exercise_4/verilog_code/Exe4_part1/DigSys4.v:37: Unsupported: Ignoring delay on this delayed statement.\n     #10 reset<=1\'b1;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Exercise_4/verilog_code/Exe4_part1/DigSys4.v:38: Unsupported: Ignoring delay on this delayed statement.\n     #3 reset<=~reset;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Exercise_4/verilog_code/Exe4_part1/DigSys4.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk<=~clk;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Exercise_4/verilog_code/Exe4_part1/DigSys4.v:110: Unsupported: Ignoring delay on this delayed statement.\n     #10 reset<=1\'b1;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Exercise_4/verilog_code/Exe4_part1/DigSys4.v:111: Unsupported: Ignoring delay on this delayed statement.\n     #3 reset<=~reset;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Exercise_4/verilog_code/Exe4_part1/DigSys4.v:114: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk<=~clk;\n    ^\n%Warning-MULTITOP: data/full_repos/permissive/419677538/Exercise_4/verilog_code/Exe4_part1/DigSys4.v:103: Multiple top level modules\n                                                                                                        : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                                        : ... Top module \'TestBenchFobinacci\'\nmodule TestBenchFobinacci;\n       ^~~~~~~~~~~~~~~~~~\n                                                                                                        : ... Top module \'TestBenchRipleCarryAdderFibonacci\'\nmodule TestBenchRipleCarryAdderFibonacci;\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/419677538/Exercise_4/verilog_code/Exe4_part1/DigSys4.v:80: Output port connection \'s\' expects 9 bits on the pin connection, but pin connection\'s VARREF \'q\' generates 8 bits.\n                                                                                                    : ... In instance TestBenchRipleCarryAdderFibonacci.rcaf0\n EightBitRippleCarryAdder ebrca0(reg1,reg2,1\'b0,q);\n                                                ^\n%Error: Exiting due to 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module EightBitRippleCarryAdder(a,b,cstart,s);
   output [8:0] s;
   input [7:0] a,b;
   input cstart;
   wire [9:0] c;
   FourBitRippleCarryAdder fbrca1(a[3:0],b[3:0],cstart,c[4:0]);
   FourBitRippleCarryAdder fbrca2(a[7:4],b[7:4],c[4],c[9:5]);  
   assign s[3:0]=c[3:0];
   assign s[8:4]=c[9:5];
endmodule
module EightBitRippleCarryAdder(a,b,cstart,s);

   output [8:0] s;
   input [7:0] a,b;
   input cstart;
   wire [9:0] c;
   FourBitRippleCarryAdder fbrca1(a[3:0],b[3:0],cstart,c[4:0]);
   FourBitRippleCarryAdder fbrca2(a[7:4],b[7:4],c[4],c[9:5]);  
   assign s[3:0]=c[3:0];
   assign s[8:4]=c[9:5];
endmodule