data/full_repos/permissive/46804359/sign_extender.v
data/verilator_xmls/90dc0426-f75c-4dca-bcd7-1ba5b93b5c83.xml
module sign_extender(clk, in, out);

input wire clk;
input wire [15:0] in;

output reg [31:0] out;


always@(posedge clk)
    begin
        out <= {{16{in[15]}}, in[15:0]};
    end
	
endmodule
module sign_extender(clk, in, out);


input wire clk;
input wire [15:0] in;

output reg [31:0] out;


always@(posedge clk)
    begin
        out <= {{16{in[15]}}, in[15:0]};
    end
	
endmodule