data/full_repos/permissive/499944578/rtl/src/memory/memory.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/499944578/rtl/src/memory/memory.v:178: Multiple top level modules\n                                                                                   : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                   : ... Top module \'FIFO\'\nmodule FIFO #(\n       ^~~~\n                                                                                   : ... Top module \'single_port_ram\'\nmodule single_port_ram\n       ^~~~~~~~~~~~~~~\n                                                                                   : ... Top module \'ROM\'\nmodule ROM #(\n       ^~~\n                                                                                   : ... Top module \'simple_ram_dual_clock\'\nmodule simple_ram_dual_clock #(\n       ^~~~~~~~~~~~~~~~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/499944578/rtl/src/memory/memory.v:247: Little bit endian vector: MSB < LSB of bit range: -1:0\n    reg [(2**ADDR_WIDTH)-1:0][DATA_WIDTH-1:0] ram;  \n        ^\n%Error: Exiting due to 2 warning(s)\n'
module status_signal#(
    parameter DATAWIDTH = 8,
    parameter DEPTH = 16
)(
    output wire fifo_full, 
    output wire fifo_empty, 
    output wire fifo_lower_threshold, 
    output wire fifo_upper_threshold, 
    output reg fifo_overflow, 
    output reg fifo_underflow, 
    input wire wr, 
    input wire rd, 
    input wire fifo_we, 
    input wire fifo_rd, 
    input wire [$clog2(DEPTH):0]wptr,
    input wire [$clog2(DEPTH):0]rptr,
    input wire clk,
    input wire resetn,
    input wire [31:0] threshold_level
);  
    wire [31:0] upper_thres_cond;
    wire fbit_comp, overflow_set, underflow_set;  
    wire pointer_equal;  
    wire [$clog2(DEPTH):0] pointer_result;  
    assign fbit_comp = wptr[$clog2(DEPTH)] ^ rptr[$clog2(DEPTH)];  
    assign pointer_equal = ((wptr[$clog2(DEPTH)-1:0] - rptr[$clog2(DEPTH)-1:0]) == 'b0) ? 1:0;  
    assign pointer_result = wptr[$clog2(DEPTH)-1:0] - rptr[$clog2(DEPTH)-1:0];  
    assign overflow_set = fifo_full & wr;  
    assign underflow_set = fifo_empty&rd; 

    wire [31:0] fullness_count;
    reg [31:0] wr_count, rd_count;
    always @(posedge clk or negedge resetn) begin
        if(~resetn)begin
            rd_count <= 'b0;
            wr_count <= 'b0;
        end else begin
            if(wr) begin
                wr_count = wr_count + 'b1;
            end
            if(rd) begin
                rd_count = rd_count + 'b1;
            end
        end
    end
    assign fullness_count = wr_count - rd_count;
    assign fifo_lower_threshold = (fullness_count >= (threshold_level));
    assign upper_thres_cond = (DEPTH - threshold_level);
    assign fifo_upper_threshold = (fullness_count <= upper_thres_cond);
    assign fifo_full = (fullness_count >= DEPTH);
    assign fifo_empty = (fullness_count == 'b0);

    always @(posedge clk or negedge resetn) begin  
        if(~resetn) 
            fifo_overflow <=0;  
        else if((overflow_set==1)&&(fifo_rd==0))  
            fifo_overflow <=1;  
        else if(fifo_rd)  
            fifo_overflow <=0;  
        else  
            fifo_overflow <= fifo_overflow;  
    end  

    always @(posedge clk or negedge resetn) begin  
        if(~resetn) fifo_underflow <=0;  
        else if((underflow_set==1)&&(fifo_we==0))  
        fifo_underflow <=1;  
        else if(fifo_we)  
        fifo_underflow <=0;  
        else  
        fifo_underflow <= fifo_underflow;  
    end  
endmodule
module status_signal#(
    parameter DATAWIDTH = 8,
    parameter DEPTH = 16
)(
    output wire fifo_full, 
    output wire fifo_empty, 
    output wire fifo_lower_threshold, 
    output wire fifo_upper_threshold, 
    output reg fifo_overflow, 
    output reg fifo_underflow, 
    input wire wr, 
    input wire rd, 
    input wire fifo_we, 
    input wire fifo_rd, 
    input wire [$clog2(DEPTH):0]wptr,
    input wire [$clog2(DEPTH):0]rptr,
    input wire clk,
    input wire resetn,
    input wire [31:0] threshold_level
);
  
    wire [31:0] upper_thres_cond;
    wire fbit_comp, overflow_set, underflow_set;  
    wire pointer_equal;  
    wire [$clog2(DEPTH):0] pointer_result;  
    assign fbit_comp = wptr[$clog2(DEPTH)] ^ rptr[$clog2(DEPTH)];  
    assign pointer_equal = ((wptr[$clog2(DEPTH)-1:0] - rptr[$clog2(DEPTH)-1:0]) == 'b0) ? 1:0;  
    assign pointer_result = wptr[$clog2(DEPTH)-1:0] - rptr[$clog2(DEPTH)-1:0];  
    assign overflow_set = fifo_full & wr;  
    assign underflow_set = fifo_empty&rd; 

    wire [31:0] fullness_count;
    reg [31:0] wr_count, rd_count;
    always @(posedge clk or negedge resetn) begin
        if(~resetn)begin
            rd_count <= 'b0;
            wr_count <= 'b0;
        end else begin
            if(wr) begin
                wr_count = wr_count + 'b1;
            end
            if(rd) begin
                rd_count = rd_count + 'b1;
            end
        end
    end
    assign fullness_count = wr_count - rd_count;
    assign fifo_lower_threshold = (fullness_count >= (threshold_level));
    assign upper_thres_cond = (DEPTH - threshold_level);
    assign fifo_upper_threshold = (fullness_count <= upper_thres_cond);
    assign fifo_full = (fullness_count >= DEPTH);
    assign fifo_empty = (fullness_count == 'b0);

    always @(posedge clk or negedge resetn) begin  
        if(~resetn) 
            fifo_overflow <=0;  
        else if((overflow_set==1)&&(fifo_rd==0))  
            fifo_overflow <=1;  
        else if(fifo_rd)  
            fifo_overflow <=0;  
        else  
            fifo_overflow <= fifo_overflow;  
    end  

    always @(posedge clk or negedge resetn) begin  
        if(~resetn) fifo_underflow <=0;  
        else if((underflow_set==1)&&(fifo_we==0))  
        fifo_underflow <=1;  
        else if(fifo_we)  
        fifo_underflow <=0;  
        else  
        fifo_underflow <= fifo_underflow;  
    end  
endmodule