data/full_repos/permissive/498129202/src/counter.v
data/verilator_xmls/af02450a-53be-45b1-aa9f-44effbd77b58.xml
module counter(ck, en, rs, ld, d, q);


input ck, en, rs, ld;
input [3:0] d;
output reg [3:0] q;

always @ (posedge ck, negedge rs, negedge ld) begin
    if (!rs)
        q = 4'b0000;
    else begin
        if (!ld)
            q = d;
        else if (en)
            q = q + 1;
    end
end

endmodule
module counter(ck, en, rs, ld, d, q);



input ck, en, rs, ld;
input [3:0] d;
output reg [3:0] q;

always @ (posedge ck, negedge rs, negedge ld) begin
    if (!rs)
        q = 4'b0000;
    else begin
        if (!ld)
            q = d;
        else if (en)
            q = q + 1;
    end
end

endmodule