data/full_repos/permissive/42434302/ivltests/shift1.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/shift1.v:32: Unsupported: Ignoring delay on this delayed statement.\n#0;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/42434302/ivltests/shift1.v:33: Unsupported or unknown PLI call: $monitor\n$monitor("%h %h %h", decode_vec, data1, data2);\n^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/shift1.v:35: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/shift1.v:37: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/shift1.v:39: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module dummy;

reg  [7:0] decode_vec;
wire [7:0] data1;
wire [7:0] data2;


assign data1 = (decode_vec[8'h02>>1] ) ? 8'h55 : 8'h00;

assign data2 = (decode_vec[8'h01   ] ) ? 8'h55 : 8'h00;

initial
begin
#0;
$monitor("%h %h %h", decode_vec, data1, data2);
decode_vec = 8'h02;
#10;
decode_vec = 8'h80;
#10;
decode_vec = 8'h02;
#10;
$finish;
end

endmodule
module dummy;


reg  [7:0] decode_vec;
wire [7:0] data1;
wire [7:0] data2;


assign data1 = (decode_vec[8'h02>>1] ) ? 8'h55 : 8'h00;

assign data2 = (decode_vec[8'h01   ] ) ? 8'h55 : 8'h00;

initial
begin
#0;
$monitor("%h %h %h", decode_vec, data1, data2);
decode_vec = 8'h02;
#10;
decode_vec = 8'h80;
#10;
decode_vec = 8'h02;
#10;
$finish;
end

endmodule