data/full_repos/permissive/526589127/verilog/rtl/b_box/r8_8bit.v
1: b'%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/r8_8bit.v:2: Cannot find include file: ./const/parameters_r8mb8.v\n`include "./const/parameters_r8mb8.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters_r8mb8.v\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters_r8mb8.v.v\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters_r8mb8.v.sv\n             ./const/parameters_r8mb8.v\n             ./const/parameters_r8mb8.v.v\n             ./const/parameters_r8mb8.v.sv\n             obj_dir/./const/parameters_r8mb8.v\n             obj_dir/./const/parameters_r8mb8.v.v\n             obj_dir/./const/parameters_r8mb8.v.sv\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/r8_8bit.v:304: Cannot find include file: ./const/parameters_r8mb8.v\n`include "./const/parameters_r8mb8.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module m_booth_sel(y, ty, single, double, triple, quad, neg, p);

input [2:0] y;

input ty;

input single;

input double;

input triple;

input quad;

input neg;

output p;

assign  p = (neg ^ ((y[2] & single)|(ty & triple)| (y[1] & double) | (y[0] & quad)));

endmodule
module m_booth_sel(y, ty, single, double, triple, quad, neg, p);


input [2:0] y;

input ty;

input single;

input double;

input triple;

input quad;

input neg;

output p;

assign  p = (neg ^ ((y[2] & single)|(ty & triple)| (y[1] & double) | (y[0] & quad)));

endmodule