data/full_repos/permissive/493265923/01_CLKMUX4_NOGLITCH/CLKMUX4_NOGLITCH_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/493265923/01_CLKMUX4_NOGLITCH/CLKMUX4_NOGLITCH_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #1 DATA3_I <= ~DATA3_I;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/493265923/01_CLKMUX4_NOGLITCH/CLKMUX4_NOGLITCH_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #3 DATA2_I <= ~DATA2_I;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/493265923/01_CLKMUX4_NOGLITCH/CLKMUX4_NOGLITCH_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #5 DATA1_I <= ~DATA1_I;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/493265923/01_CLKMUX4_NOGLITCH/CLKMUX4_NOGLITCH_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #7 DATA0_I <= ~DATA0_I;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/493265923/01_CLKMUX4_NOGLITCH/CLKMUX4_NOGLITCH_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #211 SEL_I <= SEL_I + 2\'b01;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/493265923/01_CLKMUX4_NOGLITCH/CLKMUX4_NOGLITCH_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #197 EN_I <= ~EN_I;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/493265923/01_CLKMUX4_NOGLITCH/CLKMUX4_NOGLITCH_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #205 EN_I <= ~EN_I;\n        ^\n%Error: data/full_repos/permissive/493265923/01_CLKMUX4_NOGLITCH/CLKMUX4_NOGLITCH_tb.v:14: Cannot find file containing module: \'CLKMUX4_NOGLITCH\'\n    CLKMUX4_NOGLITCH CLKMUX4_NOGLITCH(\n    ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/493265923/01_CLKMUX4_NOGLITCH,data/full_repos/permissive/493265923/CLKMUX4_NOGLITCH\n             data/full_repos/permissive/493265923/01_CLKMUX4_NOGLITCH,data/full_repos/permissive/493265923/CLKMUX4_NOGLITCH.v\n             data/full_repos/permissive/493265923/01_CLKMUX4_NOGLITCH,data/full_repos/permissive/493265923/CLKMUX4_NOGLITCH.sv\n             CLKMUX4_NOGLITCH\n             CLKMUX4_NOGLITCH.v\n             CLKMUX4_NOGLITCH.sv\n             obj_dir/CLKMUX4_NOGLITCH\n             obj_dir/CLKMUX4_NOGLITCH.v\n             obj_dir/CLKMUX4_NOGLITCH.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module CLKMUX4_NOGLITCH_tb();

    reg DATA3_I = 1'b0;
    reg DATA2_I = 1'b0;
    reg DATA1_I = 1'b0;
    reg DATA0_I = 1'b0;

    reg unsigned [1:0] SEL_I = 2'b00;
    reg EN_I = 1'b1;

    wire DATA_O;

    CLKMUX4_NOGLITCH CLKMUX4_NOGLITCH(
        .DATA3_I (DATA3_I),
        .DATA2_I (DATA2_I),
        .DATA1_I (DATA1_I),
        .DATA0_I (DATA0_I),
        .SEL_I (SEL_I),
        .EN_I (EN_I),
        .DATA_O (DATA_O)
    );

    always begin
        #1 DATA3_I <= ~DATA3_I;
    end

    always begin
        #3 DATA2_I <= ~DATA2_I;
    end

    always begin
        #5 DATA1_I <= ~DATA1_I;
    end

    always begin
        #7 DATA0_I <= ~DATA0_I;
    end

    always begin
        #211 SEL_I <= SEL_I + 2'b01;
    end

    initial begin
        #197 EN_I <= ~EN_I;
        #205 EN_I <= ~EN_I;
    end

endmodule
module CLKMUX4_NOGLITCH_tb();


    reg DATA3_I = 1'b0;
    reg DATA2_I = 1'b0;
    reg DATA1_I = 1'b0;
    reg DATA0_I = 1'b0;

    reg unsigned [1:0] SEL_I = 2'b00;
    reg EN_I = 1'b1;

    wire DATA_O;

    CLKMUX4_NOGLITCH CLKMUX4_NOGLITCH(
        .DATA3_I (DATA3_I),
        .DATA2_I (DATA2_I),
        .DATA1_I (DATA1_I),
        .DATA0_I (DATA0_I),
        .SEL_I (SEL_I),
        .EN_I (EN_I),
        .DATA_O (DATA_O)
    );

    always begin
        #1 DATA3_I <= ~DATA3_I;
    end

    always begin
        #3 DATA2_I <= ~DATA2_I;
    end

    always begin
        #5 DATA1_I <= ~DATA1_I;
    end

    always begin
        #7 DATA0_I <= ~DATA0_I;
    end

    always begin
        #211 SEL_I <= SEL_I + 2'b01;
    end

    initial begin
        #197 EN_I <= ~EN_I;
        #205 EN_I <= ~EN_I;
    end

endmodule