data/full_repos/permissive/505451992/sr_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n              reset = 1;#125 \n                        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n              reset = 0;#125;\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n              reset = 0;#125;\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n             forever #125 clk=~clk;\n                     ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n            #500\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n            #375\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n             #1750  \n             ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n             #250\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n             #250\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n             #5125  \n             ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n                #125\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n                #250 \n                ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n                #250\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n                #250 \n                ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n                #250\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n                #250 \n                ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n                #250\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n                #250 \n                ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n                #250\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n                #250\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n             #625  \n             ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n             #375\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n             #125       \n             ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n             #125             \n             ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n             #125        \n             ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n             #125\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:125: Unsupported: Ignoring delay on this delayed statement.\n             #125         \n             ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:127: Unsupported: Ignoring delay on this delayed statement.\n             #125\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:129: Unsupported: Ignoring delay on this delayed statement.\n             #125         \n             ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:131: Unsupported: Ignoring delay on this delayed statement.\n             #125\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:133: Unsupported: Ignoring delay on this delayed statement.\n             #125         \n             ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:135: Unsupported: Ignoring delay on this delayed statement.\n             #125\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:137: Unsupported: Ignoring delay on this delayed statement.\n             #125         \n             ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:139: Unsupported: Ignoring delay on this delayed statement.\n             #125\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:141: Unsupported: Ignoring delay on this delayed statement.\n             #125         \n             ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:143: Unsupported: Ignoring delay on this delayed statement.\n             #125\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:145: Unsupported: Ignoring delay on this delayed statement.\n             #125         \n             ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:148: Unsupported: Ignoring delay on this delayed statement.\n             #125\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n             #125         \n             ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:152: Unsupported: Ignoring delay on this delayed statement.\n             #125\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:157: Unsupported: Ignoring delay on this delayed statement.\n                #5125 \n                ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:159: Unsupported: Ignoring delay on this delayed statement.\n                 #125\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:162: Unsupported: Ignoring delay on this delayed statement.\n                 #125       \n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:164: Unsupported: Ignoring delay on this delayed statement.\n                 #125             \n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:166: Unsupported: Ignoring delay on this delayed statement.\n                 #125        \n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:168: Unsupported: Ignoring delay on this delayed statement.\n                 #125\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:170: Unsupported: Ignoring delay on this delayed statement.\n                 #125         \n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:172: Unsupported: Ignoring delay on this delayed statement.\n                 #125\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:174: Unsupported: Ignoring delay on this delayed statement.\n                 #125         \n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:176: Unsupported: Ignoring delay on this delayed statement.\n                 #125\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:178: Unsupported: Ignoring delay on this delayed statement.\n                 #125         \n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:180: Unsupported: Ignoring delay on this delayed statement.\n                 #125\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:182: Unsupported: Ignoring delay on this delayed statement.\n                 #125         \n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:184: Unsupported: Ignoring delay on this delayed statement.\n                 #125\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:186: Unsupported: Ignoring delay on this delayed statement.\n                 #125         \n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:188: Unsupported: Ignoring delay on this delayed statement.\n                 #125\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:190: Unsupported: Ignoring delay on this delayed statement.\n                 #125         \n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:193: Unsupported: Ignoring delay on this delayed statement.\n                 #125\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:195: Unsupported: Ignoring delay on this delayed statement.\n                 #125         \n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/sr_tb.v:197: Unsupported: Ignoring delay on this delayed statement.\n                 #125\n                 ^\n%Error: data/full_repos/permissive/505451992/sr_tb.v:39: Cannot find file containing module: \'serial_receiver\'\n    serial_receiver  srr(\n    ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/505451992,data/full_repos/permissive/505451992/serial_receiver\n             data/full_repos/permissive/505451992,data/full_repos/permissive/505451992/serial_receiver.v\n             data/full_repos/permissive/505451992,data/full_repos/permissive/505451992/serial_receiver.sv\n             serial_receiver\n             serial_receiver.v\n             serial_receiver.sv\n             obj_dir/serial_receiver\n             obj_dir/serial_receiver.v\n             obj_dir/serial_receiver.sv\n%Error: Exiting due to 1 error(s), 60 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sr_tb(

    );
    
    reg reset;
    reg clk;
    reg SCL;
    reg SDA;
    reg SDA_Enable;
    wire[3:0] PR;
    wire[2:0] Rate;
    wire SDA_In;
    
   
    
    
    serial_receiver  srr(
    .reset(reset),
    .clk(clk),
    .SCL(SCL),
    .SDA(SDA_In),
    .SDA_Enable(SDA_Enable),
    .PR(PR),
    .Rate(Rate)
    
        );
        
        assign SDA_In = SDA_Enable ? 1'bz : SDA;
       initial begin
              reset = 1;#125 
              reset = 0;#125;
              reset = 0;#125;
              end
              
             initial begin
             clk=1;
             forever #125 clk=~clk;
             end   
             
             initial begin
             SDA_Enable = 0;
            
             SDA = 1;

            #500
             SDA = 0;
            #375

         
             SDA =1;
             #1750
             SDA = 0;
             #250
             SDA_Enable = 1;
             SDA = SDA_In;
             #250
             SDA_Enable = 0;
             SDA = 1;
             
             #5125
                SDA = 0;
                #125

                SDA =0;
                #250
                SDA = 1;
                #250
                SDA =0;
                #250
                SDA = 1;
                #250
                SDA =0;
                #250
                SDA = 1;
                #250
                SDA =0;
                #250
                SDA = 1;
                #250
                SDA_Enable = 1;
                SDA = SDA_In;
                #250
                SDA_Enable = 0;
                SDA = 1;             
             
            end 
             
            initial begin
             SCL = 1;
             #625  
             SCL = 0;
             #375

             SCL = 1;
             #125
             SCL = 0;
             #125             
             SCL = 1;
             #125
             SCL = 0;
             #125
             SCL = 1;
             #125
             SCL = 0;
             #125
             SCL = 1;
             #125
             SCL = 0;
             #125
             SCL = 1;
             #125
             SCL = 0;
             #125
             SCL = 1;
             #125
             SCL = 0;
             #125
             SCL = 1;
             #125
             SCL = 0;
             #125
             SCL = 1;
             #125
             
             SCL = 0;
             #125
             SCL = 1;
             #125
             SCL = 0;
             #125
             SCL = 1;

                 
                 
                #5125 
                 SCL = 0;
                 #125

                 SCL = 1;
                 #125
                 SCL = 0;
                 #125             
                 SCL = 1;
                 #125
                 SCL = 0;
                 #125
                 SCL = 1;
                 #125
                 SCL = 0;
                 #125
                 SCL = 1;
                 #125
                 SCL = 0;
                 #125
                 SCL = 1;
                 #125
                 SCL = 0;
                 #125
                 SCL = 1;
                 #125
                 SCL = 0;
                 #125
                 SCL = 1;
                 #125
                 SCL = 0;
                 #125
                 SCL = 1;
                 #125
                 
                 SCL = 0;
                 #125
                 SCL = 1;
                 #125
                 SCL = 0;
                 #125
                 SCL = 1;

          end


                                                                                     

    
endmodule
module sr_tb(

    );

    
    reg reset;
    reg clk;
    reg SCL;
    reg SDA;
    reg SDA_Enable;
    wire[3:0] PR;
    wire[2:0] Rate;
    wire SDA_In;
    
   
    
    
    serial_receiver  srr(
    .reset(reset),
    .clk(clk),
    .SCL(SCL),
    .SDA(SDA_In),
    .SDA_Enable(SDA_Enable),
    .PR(PR),
    .Rate(Rate)
    
        );
        
        assign SDA_In = SDA_Enable ? 1'bz : SDA;
       initial begin
              reset = 1;#125 
              reset = 0;#125;
              reset = 0;#125;
              end
              
             initial begin
             clk=1;
             forever #125 clk=~clk;
             end   
             
             initial begin
             SDA_Enable = 0;
            
             SDA = 1;

            #500
             SDA = 0;
            #375

         
             SDA =1;
             #1750
             SDA = 0;
             #250
             SDA_Enable = 1;
             SDA = SDA_In;
             #250
             SDA_Enable = 0;
             SDA = 1;
             
             #5125
                SDA = 0;
                #125

                SDA =0;
                #250
                SDA = 1;
                #250
                SDA =0;
                #250
                SDA = 1;
                #250
                SDA =0;
                #250
                SDA = 1;
                #250
                SDA =0;
                #250
                SDA = 1;
                #250
                SDA_Enable = 1;
                SDA = SDA_In;
                #250
                SDA_Enable = 0;
                SDA = 1;             
             
            end 
             
            initial begin
             SCL = 1;
             #625  
             SCL = 0;
             #375

             SCL = 1;
             #125
             SCL = 0;
             #125             
             SCL = 1;
             #125
             SCL = 0;
             #125
             SCL = 1;
             #125
             SCL = 0;
             #125
             SCL = 1;
             #125
             SCL = 0;
             #125
             SCL = 1;
             #125
             SCL = 0;
             #125
             SCL = 1;
             #125
             SCL = 0;
             #125
             SCL = 1;
             #125
             SCL = 0;
             #125
             SCL = 1;
             #125
             
             SCL = 0;
             #125
             SCL = 1;
             #125
             SCL = 0;
             #125
             SCL = 1;

                 
                 
                #5125 
                 SCL = 0;
                 #125

                 SCL = 1;
                 #125
                 SCL = 0;
                 #125             
                 SCL = 1;
                 #125
                 SCL = 0;
                 #125
                 SCL = 1;
                 #125
                 SCL = 0;
                 #125
                 SCL = 1;
                 #125
                 SCL = 0;
                 #125
                 SCL = 1;
                 #125
                 SCL = 0;
                 #125
                 SCL = 1;
                 #125
                 SCL = 0;
                 #125
                 SCL = 1;
                 #125
                 SCL = 0;
                 #125
                 SCL = 1;
                 #125
                 
                 SCL = 0;
                 #125
                 SCL = 1;
                 #125
                 SCL = 0;
                 #125
                 SCL = 1;

          end


                                                                                     

    
endmodule