data/full_repos/permissive/415843050/cpu-src/execute.v
1: b"%Error: data/full_repos/permissive/415843050/cpu-src/execute.v:126: Can't find definition of variable: 'Bgezal_ex_mem'\n                         !Bgezal_ex_mem && !Bltzal_ex_mem && !Jal_ex_mem\n                          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/415843050/cpu-src/execute.v:126: Can't find definition of variable: 'Bltzal_ex_mem'\n                                                                  : ... Suggested alternative: 'Bgezal_ex_mem'\n                         !Bgezal_ex_mem && !Bltzal_ex_mem && !Jal_ex_mem\n                                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/415843050/cpu-src/execute.v:126: Can't find definition of variable: 'Jal_ex_mem'\n                                                                  : ... Suggested alternative: 'Bgezal_ex_mem'\n                         !Bgezal_ex_mem && !Bltzal_ex_mem && !Jal_ex_mem\n                                                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/415843050/cpu-src/execute.v:128: Can't find definition of variable: 'Jalr_ex_mem'\n                                                                  : ... Suggested alternative: 'Jal_ex_mem'\n                     ? (Jalr_ex_mem ? PC_plus_4_latch_ex_mem : ALU_result_ex_mem)\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/415843050/cpu-src/execute.v:128: Can't find definition of variable: 'PC_plus_4_latch_ex_mem'\n                     ? (Jalr_ex_mem ? PC_plus_4_latch_ex_mem : ALU_result_ex_mem)\n                                      ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/415843050/cpu-src/execute.v:131: Can't find definition of variable: 'Negative_ex_mem'\n                         ((Bgezal_ex_mem && !Negative_ex_mem) || (Bltzal_ex_mem && Negative_ex_mem) || Jal_ex_mem)\n                                             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/415843050/cpu-src/execute.v:137: Can't find definition of variable: 'Bgezal_mem_wb'\n                           !Bgezal_mem_wb && !Bltzal_mem_wb && !Jal_mem_wb\n                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/415843050/cpu-src/execute.v:137: Can't find definition of variable: 'Bltzal_mem_wb'\n                                                                  : ... Suggested alternative: 'Bgezal_mem_wb'\n                           !Bgezal_mem_wb && !Bltzal_mem_wb && !Jal_mem_wb\n                                              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/415843050/cpu-src/execute.v:137: Can't find definition of variable: 'Jal_mem_wb'\n                                                                  : ... Suggested alternative: 'Bgezal_mem_wb'\n                           !Bgezal_mem_wb && !Bltzal_mem_wb && !Jal_mem_wb\n                                                                ^~~~~~~~~~\n%Error: data/full_repos/permissive/415843050/cpu-src/execute.v:140: Can't find definition of variable: 'Jalr_mem_wb'\n                                                                  : ... Suggested alternative: 'Jal_mem_wb'\n                             Jalr_mem_wb ? PC_plus_4_latch_mem_wb\n                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/415843050/cpu-src/execute.v:140: Can't find definition of variable: 'PC_plus_4_latch_mem_wb'\n                                                                  : ... Suggested alternative: 'PC_plus_4_latch_ex_mem'\n                             Jalr_mem_wb ? PC_plus_4_latch_mem_wb\n                                           ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/415843050/cpu-src/execute.v:145: Can't find definition of variable: 'Negative_mem_wb'\n                                                                  : ... Suggested alternative: 'Negative_ex_mem'\n                             ((Bgezal_mem_wb && !Negative_mem_wb) || (Bltzal_mem_wb && Negative_mem_wb) || Jal_mem_wb)\n                                                 ^~~~~~~~~~~~~~~\n%Error: Exiting due to 12 error(s)\n"
module Execute(
    clock,Instruction,
    ALU_src,ALU_op,Shift,I_type,
    Read_data_1,Read_data_2,Immediate_extend,PC_plus_4,
    ALU_result,PC_add_result,
    Zero,Positive,Negative,Overflow,Divide_zero,
    Mfhi,Mflo,Mthi,Mtlo,
    L_type,S_type,
    Memory_read,Memory_write,IO_read,IO_write,
    Register_write_ex_mem,Write_back_address_ex_mem,
    Register_write_mem_wb,Write_back_address_mem_wb,Memory_or_IO_mem_wb,
    ALU_result_ex_mem,ALU_result_mem_wb,Read_data_mem_wb,
    Forwarded_data_1,Forwarded_data_2
    );
    
    input       clock;
    input[31:0] Instruction;
    
    input       ALU_src;
    input[1:0]  ALU_op;
    input       Shift;
    input       I_type;
    input[31:0] Read_data_1;
    input[31:0] Read_data_2;
    input[31:0] Immediate_extend;
    input[31:0] PC_plus_4;
    
    output[31:0]    ALU_result;
    output[31:0]    PC_add_result;
    output          Zero;
    output          Positive;
    output          Negative;
    output          Overflow;
    output          Divide_zero;
    
    input       Mfhi,Mflo,Mthi,Mtlo;
    
    input       L_type,S_type;
    output      Memory_read,Memory_write,IO_read,IO_write;
    

    input       Register_write_ex_mem,Register_write_mem_wb,Memory_or_IO_mem_wb;
    input[4:0]  Write_back_address_ex_mem,Write_back_address_mem_wb;
    input[31:0] ALU_result_ex_mem,ALU_result_mem_wb,Read_data_mem_wb;
    
    output[31:0]    Forwarded_data_1,Forwarded_data_2;
    
    
    
    wire[31:0]  Forwarded_data_1,Forwarded_data_2;
    wire[31:0]  a_input,b_input;
    wire[5:0]   opcode;
    wire[4:0]   rs,rt;
    wire[4:0]   shamt;
    wire[5:0]   func;
    
    wire[6:0]   exec_code;
    wire[2:0]   ALU_ctrl;
    
    wire        signed_mul_div;
    wire[31:0]  transformed_data_1,transformed_data_2;
    
    wire        mul_sel;
    wire        div_sel;
    wire[63:0]  unsigned_mul_result;
    wire        divu_divisor_tvalid;
    wire        divu_dividend_tvalid;
    wire        divu_dout_tvalid;
    wire        divu_dout_tuser;
    wire[63:0]  unsigned_div_result;
    
    reg         inverse_mul_div_result;
    reg[31:0]   ALU_output;
    reg[31:0]   shift_result;
    reg[31:0]   hi,lo;
    reg[31:0]   ALU_result;
    
    
    
    assign opcode = Instruction[31:26];
    assign rs = Instruction[25:21];
    assign rt = Instruction[20:16];
    assign shamt = Instruction[10:6];
    assign func = Instruction[5:0];
    

    

    assign Forwarded_data_1 =
                     (
                         Register_write_ex_mem && Write_back_address_ex_mem != 5'd0 && 
                         Write_back_address_ex_mem == rs && 
                         !Bgezal_ex_mem && !Bltzal_ex_mem && !Jal_ex_mem
                     )
                     ? (Jalr_ex_mem ? PC_plus_4_latch_ex_mem : ALU_result_ex_mem)
                     : (
                         Register_write_ex_mem && rs == 5'd31 &&
                         ((Bgezal_ex_mem && !Negative_ex_mem) || (Bltzal_ex_mem && Negative_ex_mem) || Jal_ex_mem)
                       )
                       ? PC_plus_4_latch_ex_mem
                       : (
                           Register_write_mem_wb && Write_back_address_mem_wb != 5'd0 &&
                           Write_back_address_ex_mem != rs && Write_back_address_mem_wb == rs &&
                           !Bgezal_mem_wb && !Bltzal_mem_wb && !Jal_mem_wb
                         )
                         ? (
                             Jalr_mem_wb ? PC_plus_4_latch_mem_wb
                                         : (Memory_or_IO_mem_wb ? Read_data_mem_wb : ALU_result_mem_wb)
                           )
                         : (
                             Register_write_mem_wb && Write_back_address_mem_wb != 5'd31 && rs == 5'd31 &&
                             ((Bgezal_mem_wb && !Negative_mem_wb) || (Bltzal_mem_wb && Negative_mem_wb) || Jal_mem_wb)
                           )
                           ? PC_plus_4_latch_mem_wb
                           : Read_data_1;
    assign Forwarded_data_2 =
                     (
                         Register_write_ex_mem && Write_back_address_ex_mem != 5'd0 && 
                         Write_back_address_ex_mem == rt && 
                         !Bgezal_ex_mem && !Bltzal_ex_mem && !Jal_ex_mem
                     )
                     ? (Jalr_ex_mem ? PC_plus_4_latch_ex_mem : ALU_result_ex_mem)
                     : (
                         Register_write_ex_mem && rt == 5'd31 &&
                         ((Bgezal_ex_mem && !Negative_ex_mem) || (Bltzal_ex_mem && Negative_ex_mem) || Jal_ex_mem)
                       )
                       ? PC_plus_4_latch_ex_mem
                       : (
                           Register_write_mem_wb && Write_back_address_mem_wb != 5'd0 &&
                           Write_back_address_ex_mem != rt && Write_back_address_mem_wb == rt &&
                           !Bgezal_mem_wb && !Bltzal_mem_wb && !Jal_mem_wb
                         )
                         ? (
                             Jalr_mem_wb ? PC_plus_4_latch_mem_wb
                                         : (Memory_or_IO_mem_wb ? Read_data_mem_wb : ALU_result_mem_wb)
                           )
                         : (
                             Register_write_mem_wb && Write_back_address_mem_wb != 5'd31 && rt == 5'd31 &&
                             ((Bgezal_mem_wb && !Negative_mem_wb) || (Bltzal_mem_wb && Negative_mem_wb) || Jal_mem_wb)
                           )
                           ? PC_plus_4_latch_mem_wb
                           : Read_data_2;
    
    assign a_input = Forwarded_data_1;
    assign b_input = ALU_src == 0 ? Forwarded_data_2 : Immediate_extend;
    

    assign exec_code = (I_type == 1'b0) ? func : {3'b000, opcode[2:0]};
    assign ALU_ctrl[0] = (exec_code[0] | exec_code[3]) & ALU_op[1];
    assign ALU_ctrl[1] = (!exec_code[2]) | (!ALU_op[1]);
    assign ALU_ctrl[2] = (exec_code[1] & ALU_op[1]) | ALU_op[0];
    

    always @(ALU_ctrl or a_input or b_input)
    begin
        case (ALU_ctrl)
            3'b000: ALU_output = a_input & b_input;
            3'b001: ALU_output = a_input | b_input;
            3'b010: ALU_output = a_input + b_input;
            3'b011: ALU_output = a_input + b_input;
            3'b100: ALU_output = a_input ^ b_input;
            3'b101: ALU_output = ~(a_input | b_input);
            3'b110: ALU_output = a_input - b_input;
            3'b111: ALU_output = a_input - b_input;
            default:    ALU_output = 32'hZZZZZZZZ;
        endcase
    end
    

    assign PC_add_result = PC_plus_4[31:2] + Immediate_extend[31:0];
    

    assign Zero = (ALU_output == 32'h00000000) ? 1'b1 : 1'b0;

    assign Positive = (Forwarded_data_1[31] == 1'b0 &&
                       Forwarded_data_1 != 32'h00000000)
                      ? 1'b1 : 1'b0;

    assign Negative = Forwarded_data_1[31];
    

    assign Overflow = (ALU_ctrl[1:0] != 2'b10) ? 1'b0 :
                          (ALU_ctrl[2] == 1'b0)
                          ? (a_input[31] == b_input[31] && a_input[31] != ALU_output[31])
                          : (a_input[31] != b_input[31] && a_input[31] != ALU_output[31]);
    

    assign signed_mul_div = (opcode == 6'b000000 && func[5:2] == 4'b0110 && func[0] == 1'b0)
                            ? 1'b1 : 1'b0;
    assign transformed_data_1 = (signed_mul_div && a_input[31])
                                 ? (~a_input) + 1 : a_input;
    assign transformed_data_2 = (signed_mul_div && b_input[31])
                                 ? (~b_input) + 1 : b_input;
    always @(*)
    begin
        inverse_mul_div_result = signed_mul_div ? a_input[31] ^ b_input[31] : 1'b0;
    end
    
    

    assign mul_sel = (opcode == 6'b000000 && func[5:1] == 5'b01100) ? 1'b1 : 1'b0;
    
    multu multu(
        .A(transformed_data_1),
        .B(transformed_data_2),
        .P(unsigned_mul_result)
    );
    

    assign div_sel = (opcode == 6'b000000 && func[5:1] == 5'b01101) ? 1'b1 : 1'b0;
    assign divu_divisor_tvalid = div_sel;
    assign divu_dividend_tvalid = div_sel;
    assign Divide_zero = (div_sel && transformed_data_2 == 32'h00000000) ? 1'b1 : 1'b0;
    
    divu divu(
        .aclk(clock),
        .s_axis_divisor_tvalid(divu_divisor_tvalid),
        .s_axis_divisor_tdata(transformed_data_2),
        .s_axis_dividend_tvalid(divu_dividend_tvalid),
        .s_axis_dividend_tdata(transformed_data_1),
        .m_axis_dout_tvalid(divu_dout_tvalid),
        .m_axis_dout_tuser(divu_dout_tuser),
        .m_axis_dout_tdata(unsigned_div_result)
    );
    

    always @(*)
    begin
        if (Mthi)
            hi <= a_input;
        else if (Mtlo)
            lo <= a_input;
        else if (mul_sel)
        begin
            {hi,lo} <= inverse_mul_div_result
                       ? (~unsigned_mul_result) + 1
                       : unsigned_mul_result;
        end
        else if (div_sel && divu_dout_tvalid)
        begin
            hi <= inverse_mul_div_result
                  ? (~unsigned_div_result[31:0]) + 1
                  : unsigned_div_result[31:0];
            lo <= inverse_mul_div_result
                  ? (~unsigned_div_result[63:32]) + 1
                  : unsigned_div_result[63:32];
        end
    end
    


    always @(*)
    begin
        if (Shift)
            case (func[2:0])
                3'b000: shift_result = b_input << shamt;
                3'b010: shift_result = b_input >> shamt;
                3'b100: shift_result = b_input << a_input;
                3'b110: shift_result = b_input >> a_input;
                3'b011: shift_result = (b_input >> shamt) |
                            ({32{b_input[31]}} & ~({32{1'b1}} >> shamt));
                3'b111: shift_result = (b_input >> a_input) |
                            ({32{b_input[31]}} & ~({32{1'b1}} >> a_input));
                default:    shift_result = b_input;
            endcase
        else
            shift_result = b_input;
    end
        

    always @(*)
    begin

        if (Mfhi)
            ALU_result = hi;

        else if (Mflo)
            ALU_result = lo;

        else if (opcode == 6'b001111)
            ALU_result = Immediate_extend[15:0] << 16;

        else if (Shift)
            ALU_result = shift_result;

        else if (func[5:1] == 5'b10101 || opcode[5:1] == 5'b00101)
        begin
            if (func[5:0] == 6'b101010 || opcode[5:0] == 6'b001010)
                ALU_result = ALU_output[31] == 1'b1 ? 1'b1 : 1'b0;
            else







                ALU_result = a_input[31] == b_input[31]
                                 ? a_input[31] ^ b_input[31] ^ ALU_output[31]
                                 : b_input[31];
        end
        else
            ALU_result = ALU_output;
    end
    


    assign Memory_read = (L_type && ALU_result[31:10] != 22'h3FFFFF) ? 1'b1 : 1'b0;
    


    assign Memory_write = (S_type && ALU_result[31:10] != 22'h3FFFFF) ? 1'b1 : 1'b0;
    


    assign IO_read = (L_type && ALU_result[31:10] == 22'h3FFFFF) ? 1'b1 : 1'b0;
    


    assign IO_write = (S_type && ALU_result[31:10] == 22'h3FFFFF) ? 1'b1 : 1'b0;
    
endmodule
module Execute(
    clock,Instruction,
    ALU_src,ALU_op,Shift,I_type,
    Read_data_1,Read_data_2,Immediate_extend,PC_plus_4,
    ALU_result,PC_add_result,
    Zero,Positive,Negative,Overflow,Divide_zero,
    Mfhi,Mflo,Mthi,Mtlo,
    L_type,S_type,
    Memory_read,Memory_write,IO_read,IO_write,
    Register_write_ex_mem,Write_back_address_ex_mem,
    Register_write_mem_wb,Write_back_address_mem_wb,Memory_or_IO_mem_wb,
    ALU_result_ex_mem,ALU_result_mem_wb,Read_data_mem_wb,
    Forwarded_data_1,Forwarded_data_2
    );

    
    input       clock;
    input[31:0] Instruction;
    
    input       ALU_src;
    input[1:0]  ALU_op;
    input       Shift;
    input       I_type;
    input[31:0] Read_data_1;
    input[31:0] Read_data_2;
    input[31:0] Immediate_extend;
    input[31:0] PC_plus_4;
    
    output[31:0]    ALU_result;
    output[31:0]    PC_add_result;
    output          Zero;
    output          Positive;
    output          Negative;
    output          Overflow;
    output          Divide_zero;
    
    input       Mfhi,Mflo,Mthi,Mtlo;
    
    input       L_type,S_type;
    output      Memory_read,Memory_write,IO_read,IO_write;
    

    input       Register_write_ex_mem,Register_write_mem_wb,Memory_or_IO_mem_wb;
    input[4:0]  Write_back_address_ex_mem,Write_back_address_mem_wb;
    input[31:0] ALU_result_ex_mem,ALU_result_mem_wb,Read_data_mem_wb;
    
    output[31:0]    Forwarded_data_1,Forwarded_data_2;
    
    
    
    wire[31:0]  Forwarded_data_1,Forwarded_data_2;
    wire[31:0]  a_input,b_input;
    wire[5:0]   opcode;
    wire[4:0]   rs,rt;
    wire[4:0]   shamt;
    wire[5:0]   func;
    
    wire[6:0]   exec_code;
    wire[2:0]   ALU_ctrl;
    
    wire        signed_mul_div;
    wire[31:0]  transformed_data_1,transformed_data_2;
    
    wire        mul_sel;
    wire        div_sel;
    wire[63:0]  unsigned_mul_result;
    wire        divu_divisor_tvalid;
    wire        divu_dividend_tvalid;
    wire        divu_dout_tvalid;
    wire        divu_dout_tuser;
    wire[63:0]  unsigned_div_result;
    
    reg         inverse_mul_div_result;
    reg[31:0]   ALU_output;
    reg[31:0]   shift_result;
    reg[31:0]   hi,lo;
    reg[31:0]   ALU_result;
    
    
    
    assign opcode = Instruction[31:26];
    assign rs = Instruction[25:21];
    assign rt = Instruction[20:16];
    assign shamt = Instruction[10:6];
    assign func = Instruction[5:0];
    

    

    assign Forwarded_data_1 =
                     (
                         Register_write_ex_mem && Write_back_address_ex_mem != 5'd0 && 
                         Write_back_address_ex_mem == rs && 
                         !Bgezal_ex_mem && !Bltzal_ex_mem && !Jal_ex_mem
                     )
                     ? (Jalr_ex_mem ? PC_plus_4_latch_ex_mem : ALU_result_ex_mem)
                     : (
                         Register_write_ex_mem && rs == 5'd31 &&
                         ((Bgezal_ex_mem && !Negative_ex_mem) || (Bltzal_ex_mem && Negative_ex_mem) || Jal_ex_mem)
                       )
                       ? PC_plus_4_latch_ex_mem
                       : (
                           Register_write_mem_wb && Write_back_address_mem_wb != 5'd0 &&
                           Write_back_address_ex_mem != rs && Write_back_address_mem_wb == rs &&
                           !Bgezal_mem_wb && !Bltzal_mem_wb && !Jal_mem_wb
                         )
                         ? (
                             Jalr_mem_wb ? PC_plus_4_latch_mem_wb
                                         : (Memory_or_IO_mem_wb ? Read_data_mem_wb : ALU_result_mem_wb)
                           )
                         : (
                             Register_write_mem_wb && Write_back_address_mem_wb != 5'd31 && rs == 5'd31 &&
                             ((Bgezal_mem_wb && !Negative_mem_wb) || (Bltzal_mem_wb && Negative_mem_wb) || Jal_mem_wb)
                           )
                           ? PC_plus_4_latch_mem_wb
                           : Read_data_1;
    assign Forwarded_data_2 =
                     (
                         Register_write_ex_mem && Write_back_address_ex_mem != 5'd0 && 
                         Write_back_address_ex_mem == rt && 
                         !Bgezal_ex_mem && !Bltzal_ex_mem && !Jal_ex_mem
                     )
                     ? (Jalr_ex_mem ? PC_plus_4_latch_ex_mem : ALU_result_ex_mem)
                     : (
                         Register_write_ex_mem && rt == 5'd31 &&
                         ((Bgezal_ex_mem && !Negative_ex_mem) || (Bltzal_ex_mem && Negative_ex_mem) || Jal_ex_mem)
                       )
                       ? PC_plus_4_latch_ex_mem
                       : (
                           Register_write_mem_wb && Write_back_address_mem_wb != 5'd0 &&
                           Write_back_address_ex_mem != rt && Write_back_address_mem_wb == rt &&
                           !Bgezal_mem_wb && !Bltzal_mem_wb && !Jal_mem_wb
                         )
                         ? (
                             Jalr_mem_wb ? PC_plus_4_latch_mem_wb
                                         : (Memory_or_IO_mem_wb ? Read_data_mem_wb : ALU_result_mem_wb)
                           )
                         : (
                             Register_write_mem_wb && Write_back_address_mem_wb != 5'd31 && rt == 5'd31 &&
                             ((Bgezal_mem_wb && !Negative_mem_wb) || (Bltzal_mem_wb && Negative_mem_wb) || Jal_mem_wb)
                           )
                           ? PC_plus_4_latch_mem_wb
                           : Read_data_2;
    
    assign a_input = Forwarded_data_1;
    assign b_input = ALU_src == 0 ? Forwarded_data_2 : Immediate_extend;
    

    assign exec_code = (I_type == 1'b0) ? func : {3'b000, opcode[2:0]};
    assign ALU_ctrl[0] = (exec_code[0] | exec_code[3]) & ALU_op[1];
    assign ALU_ctrl[1] = (!exec_code[2]) | (!ALU_op[1]);
    assign ALU_ctrl[2] = (exec_code[1] & ALU_op[1]) | ALU_op[0];
    

    always @(ALU_ctrl or a_input or b_input)
    begin
        case (ALU_ctrl)
            3'b000: ALU_output = a_input & b_input;
            3'b001: ALU_output = a_input | b_input;
            3'b010: ALU_output = a_input + b_input;
            3'b011: ALU_output = a_input + b_input;
            3'b100: ALU_output = a_input ^ b_input;
            3'b101: ALU_output = ~(a_input | b_input);
            3'b110: ALU_output = a_input - b_input;
            3'b111: ALU_output = a_input - b_input;
            default:    ALU_output = 32'hZZZZZZZZ;
        endcase
    end
    

    assign PC_add_result = PC_plus_4[31:2] + Immediate_extend[31:0];
    

    assign Zero = (ALU_output == 32'h00000000) ? 1'b1 : 1'b0;

    assign Positive = (Forwarded_data_1[31] == 1'b0 &&
                       Forwarded_data_1 != 32'h00000000)
                      ? 1'b1 : 1'b0;

    assign Negative = Forwarded_data_1[31];
    

    assign Overflow = (ALU_ctrl[1:0] != 2'b10) ? 1'b0 :
                          (ALU_ctrl[2] == 1'b0)
                          ? (a_input[31] == b_input[31] && a_input[31] != ALU_output[31])
                          : (a_input[31] != b_input[31] && a_input[31] != ALU_output[31]);
    

    assign signed_mul_div = (opcode == 6'b000000 && func[5:2] == 4'b0110 && func[0] == 1'b0)
                            ? 1'b1 : 1'b0;
    assign transformed_data_1 = (signed_mul_div && a_input[31])
                                 ? (~a_input) + 1 : a_input;
    assign transformed_data_2 = (signed_mul_div && b_input[31])
                                 ? (~b_input) + 1 : b_input;
    always @(*)
    begin
        inverse_mul_div_result = signed_mul_div ? a_input[31] ^ b_input[31] : 1'b0;
    end
    
    

    assign mul_sel = (opcode == 6'b000000 && func[5:1] == 5'b01100) ? 1'b1 : 1'b0;
    
    multu multu(
        .A(transformed_data_1),
        .B(transformed_data_2),
        .P(unsigned_mul_result)
    );
    

    assign div_sel = (opcode == 6'b000000 && func[5:1] == 5'b01101) ? 1'b1 : 1'b0;
    assign divu_divisor_tvalid = div_sel;
    assign divu_dividend_tvalid = div_sel;
    assign Divide_zero = (div_sel && transformed_data_2 == 32'h00000000) ? 1'b1 : 1'b0;
    
    divu divu(
        .aclk(clock),
        .s_axis_divisor_tvalid(divu_divisor_tvalid),
        .s_axis_divisor_tdata(transformed_data_2),
        .s_axis_dividend_tvalid(divu_dividend_tvalid),
        .s_axis_dividend_tdata(transformed_data_1),
        .m_axis_dout_tvalid(divu_dout_tvalid),
        .m_axis_dout_tuser(divu_dout_tuser),
        .m_axis_dout_tdata(unsigned_div_result)
    );
    

    always @(*)
    begin
        if (Mthi)
            hi <= a_input;
        else if (Mtlo)
            lo <= a_input;
        else if (mul_sel)
        begin
            {hi,lo} <= inverse_mul_div_result
                       ? (~unsigned_mul_result) + 1
                       : unsigned_mul_result;
        end
        else if (div_sel && divu_dout_tvalid)
        begin
            hi <= inverse_mul_div_result
                  ? (~unsigned_div_result[31:0]) + 1
                  : unsigned_div_result[31:0];
            lo <= inverse_mul_div_result
                  ? (~unsigned_div_result[63:32]) + 1
                  : unsigned_div_result[63:32];
        end
    end
    


    always @(*)
    begin
        if (Shift)
            case (func[2:0])
                3'b000: shift_result = b_input << shamt;
                3'b010: shift_result = b_input >> shamt;
                3'b100: shift_result = b_input << a_input;
                3'b110: shift_result = b_input >> a_input;
                3'b011: shift_result = (b_input >> shamt) |
                            ({32{b_input[31]}} & ~({32{1'b1}} >> shamt));
                3'b111: shift_result = (b_input >> a_input) |
                            ({32{b_input[31]}} & ~({32{1'b1}} >> a_input));
                default:    shift_result = b_input;
            endcase
        else
            shift_result = b_input;
    end
        

    always @(*)
    begin

        if (Mfhi)
            ALU_result = hi;

        else if (Mflo)
            ALU_result = lo;

        else if (opcode == 6'b001111)
            ALU_result = Immediate_extend[15:0] << 16;

        else if (Shift)
            ALU_result = shift_result;

        else if (func[5:1] == 5'b10101 || opcode[5:1] == 5'b00101)
        begin
            if (func[5:0] == 6'b101010 || opcode[5:0] == 6'b001010)
                ALU_result = ALU_output[31] == 1'b1 ? 1'b1 : 1'b0;
            else







                ALU_result = a_input[31] == b_input[31]
                                 ? a_input[31] ^ b_input[31] ^ ALU_output[31]
                                 : b_input[31];
        end
        else
            ALU_result = ALU_output;
    end
    


    assign Memory_read = (L_type && ALU_result[31:10] != 22'h3FFFFF) ? 1'b1 : 1'b0;
    


    assign Memory_write = (S_type && ALU_result[31:10] != 22'h3FFFFF) ? 1'b1 : 1'b0;
    


    assign IO_read = (L_type && ALU_result[31:10] == 22'h3FFFFF) ? 1'b1 : 1'b0;
    


    assign IO_write = (S_type && ALU_result[31:10] == 22'h3FFFFF) ? 1'b1 : 1'b0;
    
endmodule