data/full_repos/permissive/455421905/src/fifo.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/455421905/src/fifo.v:57: Multiple top level modules\n                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                     : ... Top module \'ONE_ENTRY_FIFO\'\nmodule ONE_ENTRY_FIFO #(parameter                    FIFO_WIDTH = 64)   \n       ^~~~~~~~~~~~~~\n                                                                     : ... Top module \'TWO_ENTRY_FIFO\'\nmodule TWO_ENTRY_FIFO #(parameter                    FIFO_WIDTH = 64)   \n       ^~~~~~~~~~~~~~\n                                                                     : ... Top module \'DFIFO\'\nmodule DFIFO #(parameter                    FIFO_SIZE  =  4,   \n       ^~~~~\n                                                                     : ... Top module \'BS_FIFO\'\nmodule BS_FIFO #(parameter                    FIFO_SIZE  =  4,   \n       ^~~~~~~\n                                                                     : ... Top module \'RAM_LAYER_FIFO\'\nmodule RAM_LAYER_FIFO #(parameter                    C_LOG      = 2,   \n       ^~~~~~~~~~~~~~\n                                                                     : ... Top module \'MULTI_CHANNEL_TWOENTRY_FIFO\'\nmodule MULTI_CHANNEL_TWOENTRY_FIFO #(parameter                    C_LOG      = 2,   \n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/455421905/src/fifo.v:375: Cannot find file containing module: \'BRAM\'\n  BRAM #(C_LOG, FIFO_WIDTH, USE_IPCORE)\n  ^~~~\n        ... Looked in:\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/BRAM\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/BRAM.v\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/BRAM.sv\n             BRAM\n             BRAM.v\n             BRAM.sv\n             obj_dir/BRAM\n             obj_dir/BRAM.v\n             obj_dir/BRAM.sv\n%Error: data/full_repos/permissive/455421905/src/fifo.v:127: Cannot find file containing module: \'BRAM\'\n  BRAM #(FIFO_SIZE, FIFO_WIDTH, USE_IPCORE)\n  ^~~~\n%Error: data/full_repos/permissive/455421905/src/fifo.v:332: Cannot find file containing module: \'BRAM\'\n  BRAM #(C_LOG, FIFO_WIDTH, USE_IPCORE)\n  ^~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module MULTI_CHANNEL_TWOENTRY_FIFO #(parameter                    C_LOG      = 2,
                                     parameter                    FIFO_WIDTH = 32,
                                     parameter                    USE_IPCORE = "INTEL")
                                    (input  wire                  CLK,
                                     input  wire                  RST,
                                     input  wire                  enq,
                                     input  wire [C_LOG-1     :0] enq_idx,
                                     input  wire                  deq,
                                     input  wire [C_LOG-1     :0] deq_idx,
                                     input  wire [FIFO_WIDTH-1:0] din,
                                     output wire [FIFO_WIDTH-1:0] dot,
                                     output reg  [(1<<C_LOG)-1:0] emp,
                                     output reg  [(1<<C_LOG)-1:0] rdy);

  wire                   head_enq;
  wire [C_LOG-1      :0] head_enq_idx;
  wire                   head_deq;
  wire [C_LOG-1      :0] head_deq_idx;
  wire [FIFO_WIDTH-1 :0] head_din;
  wire [FIFO_WIDTH-1 :0] head_dot;
  wire [(1<<C_LOG)-1 :0] head_emp;
  wire [(1<<C_LOG)-1 :0] head_ful;

  wire                   tail_enq;
  wire [C_LOG-1      :0] tail_enq_idx;
  wire                   tail_deq;
  wire [C_LOG-1      :0] tail_deq_idx;
  wire [FIFO_WIDTH-1 :0] tail_din;
  wire [FIFO_WIDTH-1 :0] tail_dot;
  wire [(1<<C_LOG)-1 :0] tail_emp;
  wire [(1<<C_LOG)-1 :0] tail_ful;

  integer                p;
  reg [3:0]              valid;
  reg [C_LOG-1      :0]  idx [3:0];
  reg [C_LOG-1      :0]  round_robin_sel;

  assign head_enq     = valid[3];
  assign head_enq_idx = idx[3];
  assign head_deq     = deq;
  assign head_deq_idx = deq_idx;
  assign head_din     = tail_dot;

  assign tail_enq     = enq;
  assign tail_enq_idx = enq_idx;
  assign tail_deq     = valid[0];
  assign tail_deq_idx = idx[0];
  assign tail_din     = din;

  MULTI_CHANNEL_ONEENTRY_FIFO #(C_LOG, FIFO_WIDTH, USE_IPCORE)
  head(CLK, RST, head_enq, head_enq_idx, head_deq, head_deq_idx, head_din,
       head_dot, head_emp, head_ful);
  MULTI_CHANNEL_ONEENTRY_FIFO #(C_LOG, FIFO_WIDTH, USE_IPCORE)
  tail(CLK, RST, tail_enq, tail_enq_idx, tail_deq, tail_deq_idx, tail_din,
       tail_dot, tail_emp, tail_ful);

  always @(posedge CLK) begin
    round_robin_sel <= (RST) ? 0 : round_robin_sel + 1;
  end
  always @(posedge CLK) begin
    if (RST) begin
      valid <= 0;
    end else begin
      valid[0] <= ~|{head_ful[round_robin_sel], tail_emp[round_robin_sel]};
      for (p=1; p<4; p=p+1) begin
        valid[p] <= valid[p-1];
      end
    end
  end
  always @(posedge CLK) begin
    idx[0] <= round_robin_sel;
    for (p=1; p<4; p=p+1) begin
      idx[p] <= idx[p-1];
    end
  end


  assign dot = head_dot;

  always @(posedge CLK) emp  <= tail_emp;
  always @(posedge CLK) rdy  <= head_ful;

endmodule
module MULTI_CHANNEL_TWOENTRY_FIFO #(parameter                    C_LOG      = 2,
                                     parameter                    FIFO_WIDTH = 32,
                                     parameter                    USE_IPCORE = "INTEL")
                                    (input  wire                  CLK,
                                     input  wire                  RST,
                                     input  wire                  enq,
                                     input  wire [C_LOG-1     :0] enq_idx,
                                     input  wire                  deq,
                                     input  wire [C_LOG-1     :0] deq_idx,
                                     input  wire [FIFO_WIDTH-1:0] din,
                                     output wire [FIFO_WIDTH-1:0] dot,
                                     output reg  [(1<<C_LOG)-1:0] emp,
                                     output reg  [(1<<C_LOG)-1:0] rdy);


  wire                   head_enq;
  wire [C_LOG-1      :0] head_enq_idx;
  wire                   head_deq;
  wire [C_LOG-1      :0] head_deq_idx;
  wire [FIFO_WIDTH-1 :0] head_din;
  wire [FIFO_WIDTH-1 :0] head_dot;
  wire [(1<<C_LOG)-1 :0] head_emp;
  wire [(1<<C_LOG)-1 :0] head_ful;

  wire                   tail_enq;
  wire [C_LOG-1      :0] tail_enq_idx;
  wire                   tail_deq;
  wire [C_LOG-1      :0] tail_deq_idx;
  wire [FIFO_WIDTH-1 :0] tail_din;
  wire [FIFO_WIDTH-1 :0] tail_dot;
  wire [(1<<C_LOG)-1 :0] tail_emp;
  wire [(1<<C_LOG)-1 :0] tail_ful;

  integer                p;
  reg [3:0]              valid;
  reg [C_LOG-1      :0]  idx [3:0];
  reg [C_LOG-1      :0]  round_robin_sel;

  assign head_enq     = valid[3];
  assign head_enq_idx = idx[3];
  assign head_deq     = deq;
  assign head_deq_idx = deq_idx;
  assign head_din     = tail_dot;

  assign tail_enq     = enq;
  assign tail_enq_idx = enq_idx;
  assign tail_deq     = valid[0];
  assign tail_deq_idx = idx[0];
  assign tail_din     = din;

  MULTI_CHANNEL_ONEENTRY_FIFO #(C_LOG, FIFO_WIDTH, USE_IPCORE)
  head(CLK, RST, head_enq, head_enq_idx, head_deq, head_deq_idx, head_din,
       head_dot, head_emp, head_ful);
  MULTI_CHANNEL_ONEENTRY_FIFO #(C_LOG, FIFO_WIDTH, USE_IPCORE)
  tail(CLK, RST, tail_enq, tail_enq_idx, tail_deq, tail_deq_idx, tail_din,
       tail_dot, tail_emp, tail_ful);

  always @(posedge CLK) begin
    round_robin_sel <= (RST) ? 0 : round_robin_sel + 1;
  end
  always @(posedge CLK) begin
    if (RST) begin
      valid <= 0;
    end else begin
      valid[0] <= ~|{head_ful[round_robin_sel], tail_emp[round_robin_sel]};
      for (p=1; p<4; p=p+1) begin
        valid[p] <= valid[p-1];
      end
    end
  end
  always @(posedge CLK) begin
    idx[0] <= round_robin_sel;
    for (p=1; p<4; p=p+1) begin
      idx[p] <= idx[p-1];
    end
  end


  assign dot = head_dot;

  always @(posedge CLK) emp  <= tail_emp;
  always @(posedge CLK) rdy  <= head_ful;

endmodule