data/full_repos/permissive/445357518/cpu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/445357518/cpu.v:43: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 17 bits.\n                                                             : ... In instance cpu\n assign pc = {8\'b0, PC};\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/445357518/cpu.v:45: Cannot find file containing module: \'vDFF1\'\n vDFF1 #(16) instructionRegister(clk, in, load_ir, regOut);\n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/vDFF1\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/vDFF1.v\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/vDFF1.sv\n             vDFF1\n             vDFF1.v\n             vDFF1.sv\n             obj_dir/vDFF1\n             obj_dir/vDFF1.v\n             obj_dir/vDFF1.sv\n%Error: data/full_repos/permissive/445357518/cpu.v:54: Cannot find file containing module: \'datapath\'\n datapath DP(.clk(clk), .write(write),.loada(loada),.loadb(loadb),.loadc(loadc),.loads(loads)\n ^~~~~~~~\n%Error: data/full_repos/permissive/445357518/cpu.v:64: Cannot find file containing module: \'vDFF1\'\n vDFF1 #(9) Program_Counter(clk, next_PC, load_PC, PC);\n ^~~~~\n%Error: data/full_repos/permissive/445357518/cpu.v:73: Cannot find file containing module: \'vDFF1\'\n vDFF1 #(9) Data_Address(clk, out[8:0], load_addr, DA);\n ^~~~~\n%Error: Exiting due to 4 error(s), 1 warning(s)\n'
module FSM(clk,reset,opcode,op,nsel,loada,loadb,loadc,loads,asel,bsel,vsel,write, mem_cmd, address_select, load_PC, reset_PC, load_ir, load_addr);
input clk, reset;
input [1:0] op;
input [2:0] opcode; 
output loada,loadb,loadc,loads,write,asel,bsel, address_select, load_PC, reset_PC, load_ir, load_addr;
output [1:0] vsel, mem_cmd;
output[2:0] nsel;

wire [`SW-1:0] present_state, state_next_reset, next_state;

vDFF2 #(`SW) STATE(clk,state_next_reset,present_state);

assign state_next_reset = reset ? `RST: next_state;
reg [(`SW+19)-1:0] next;


assign {next_state,loada,loadb,loadc,loads,write,asel,bsel,vsel,nsel, address_select, load_PC, load_ir, reset_PC, mem_cmd, load_addr}=next;

always @(*) begin
	casex ({present_state, opcode, op})


           {`RST, 5'bxxxxx}: next= {`IF1, 18'b000000000000010100, 1'b0};


	   {`IF1, 5'bxxxxx}: next = {`IF2, 16'b0000000000001000, `MREAD, 1'b0};


	   {`IF2, 5'bxxxxx}: next= {`UpdatePC,{12{1'b0}},1'b1,1'b0,1'b1,1'b0,`MREAD, 1'b0};


           {`UpdatePC, 5'bxxxxx}: next= {`Decode, {12{1'b0}},1'b0,1'b1,2'b00,`MNONE, 1'b0};





           {`Decode,5'b11010 }: next={`WriteToRn,{19{1'b0}}};
	   {`Decode, 5'b11000},{`Decode, 5'b10111}: next={`ReadRm,{19{1'b0}}};
	   {`Decode, 5'b11100}: next = {`HALT, {19{1'b0}}};
           {`Decode,5'bxxxxx}: next={`ReadRn,{19{1'b0}}};



	   {`WriteToRn, {5{1'bx}}}: next={`IF1,1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,2'b01,3'b001, 4'b0000, `MNONE, 1'b0};




	   {`ReadRn, 5'b01100}, {`ReadRn, 5'b10000}: next = {`SXMM, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 2'b00, 3'b001, 4'b0000, `MNONE, 1'b0};
	   {`ReadRn, {5{1'bx}}}: next = {`ReadRm, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 2'b00, 3'b001, 4'b0000, `MNONE, 1'b0};
	   



	   {`ReadRm, 5'b11000}: next = {`Shift, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 2'b00, 3'b100, 4'b0000, `MNONE, 1'b0}; 

	   {`ReadRm, 5'b10111}: next = {`NOT, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 2'b00, 3'b100, 4'b0000, `MNONE, 1'b0}; 

	   {`ReadRm, 5'b10110}: next = {`AND, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 2'b00, 3'b100, 4'b0000, `MNONE, 1'b0}; 

	   {`ReadRm, 5'b10101}: next = {`CMP, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 2'b00, 3'b100, 4'b0000, `MNONE, 1'b0}; 

	   {`ReadRm, 5'b10100}: next = {`ADD, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 2'b00, 3'b100, 4'b0000, `MNONE, 1'b0};
            


           {`ADD, {5{1'bx}}}: next = {`WriteRd, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 2'b00, 3'b000,4'b0000, `MNONE, 1'b0};



           {`AND, {5{1'bx}}}: next = {`WriteRd, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 2'b00, 3'b000, 4'b0000, `MNONE, 1'b0};



           {`CMP,5'bxxxxx}: next={`IF1, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 2'b00, 3'b000, 4'b0000, `MNONE, 1'b0};



           {`NOT,5'bxxxxx}: next={`WriteRd, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 2'b00, 3'b000, 4'b0000, `MNONE, 1'b0};



           {`Shift,5'bxxxxx}: next={`WriteRd, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 2'b00, 3'b000, 4'b0000, `MNONE, 1'b0};



           {`WriteRd,5'bxxxxx}: next={`IF1, 1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,2'b11,3'b010, 4'b0000, `MNONE, 1'b0};



	   {`SXMM, 5'bxxxxx}: next = {`DataAdd, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b1, 2'b00, 3'b000, 4'b0000, `MNONE, 1'b0};



	   {`DataAdd, 5'b01100}: next = {`ReadMem, {16{1'b0}}, `MNONE, 1'b1};
	   {`DataAdd, 5'b10000}: next = {`ReadRd, {16{1'b0}}, `MNONE, 1'b1};



	   {`ReadRd, 5'bxxxxx}: next = {`OutputRd, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 2'b00, 3'b010, 4'b0000, `MNONE, 1'b0};



	   {`OutputRd, 5'bxxxxx}: next = {`WriteMem, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 2'b00, 3'b000, 4'b0000, `MNONE, 1'b0};
	   


	   {`WriteMem, 5'bxxxxx}: next = {`IF1, 12'b000000000000, 4'b0000, `MWRITE, 1'b0};



            {`ReadMem,5'bxxxxx}: next={`WriteMemToRd, 1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,2'b00,3'b000, 4'b0000, `MREAD, 1'b0};
	    


            {`WriteMemToRd,5'bxxxxx}: next={`IF1, 1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,2'b00,3'b010, 4'b0000, `MREAD, 1'b0};


	   {`HALT,5'bxxxxx}: next={`HALT, {19{1'b0}}};

         default: next={{`SW{1'bx}},{19{1'bx}}};
         endcase
end



endmodule
module FSM(clk,reset,opcode,op,nsel,loada,loadb,loadc,loads,asel,bsel,vsel,write, mem_cmd, address_select, load_PC, reset_PC, load_ir, load_addr);

input clk, reset;
input [1:0] op;
input [2:0] opcode; 
output loada,loadb,loadc,loads,write,asel,bsel, address_select, load_PC, reset_PC, load_ir, load_addr;
output [1:0] vsel, mem_cmd;
output[2:0] nsel;

wire [`SW-1:0] present_state, state_next_reset, next_state;

vDFF2 #(`SW) STATE(clk,state_next_reset,present_state);

assign state_next_reset = reset ? `RST: next_state;
reg [(`SW+19)-1:0] next;


assign {next_state,loada,loadb,loadc,loads,write,asel,bsel,vsel,nsel, address_select, load_PC, load_ir, reset_PC, mem_cmd, load_addr}=next;

always @(*) begin
	casex ({present_state, opcode, op})


           {`RST, 5'bxxxxx}: next= {`IF1, 18'b000000000000010100, 1'b0};


	   {`IF1, 5'bxxxxx}: next = {`IF2, 16'b0000000000001000, `MREAD, 1'b0};


	   {`IF2, 5'bxxxxx}: next= {`UpdatePC,{12{1'b0}},1'b1,1'b0,1'b1,1'b0,`MREAD, 1'b0};


           {`UpdatePC, 5'bxxxxx}: next= {`Decode, {12{1'b0}},1'b0,1'b1,2'b00,`MNONE, 1'b0};





           {`Decode,5'b11010 }: next={`WriteToRn,{19{1'b0}}};
	   {`Decode, 5'b11000},{`Decode, 5'b10111}: next={`ReadRm,{19{1'b0}}};
	   {`Decode, 5'b11100}: next = {`HALT, {19{1'b0}}};
           {`Decode,5'bxxxxx}: next={`ReadRn,{19{1'b0}}};



	   {`WriteToRn, {5{1'bx}}}: next={`IF1,1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,2'b01,3'b001, 4'b0000, `MNONE, 1'b0};




	   {`ReadRn, 5'b01100}, {`ReadRn, 5'b10000}: next = {`SXMM, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 2'b00, 3'b001, 4'b0000, `MNONE, 1'b0};
	   {`ReadRn, {5{1'bx}}}: next = {`ReadRm, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 2'b00, 3'b001, 4'b0000, `MNONE, 1'b0};
	   



	   {`ReadRm, 5'b11000}: next = {`Shift, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 2'b00, 3'b100, 4'b0000, `MNONE, 1'b0}; 

	   {`ReadRm, 5'b10111}: next = {`NOT, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 2'b00, 3'b100, 4'b0000, `MNONE, 1'b0}; 

	   {`ReadRm, 5'b10110}: next = {`AND, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 2'b00, 3'b100, 4'b0000, `MNONE, 1'b0}; 

	   {`ReadRm, 5'b10101}: next = {`CMP, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 2'b00, 3'b100, 4'b0000, `MNONE, 1'b0}; 

	   {`ReadRm, 5'b10100}: next = {`ADD, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 2'b00, 3'b100, 4'b0000, `MNONE, 1'b0};
            


           {`ADD, {5{1'bx}}}: next = {`WriteRd, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 2'b00, 3'b000,4'b0000, `MNONE, 1'b0};



           {`AND, {5{1'bx}}}: next = {`WriteRd, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 2'b00, 3'b000, 4'b0000, `MNONE, 1'b0};



           {`CMP,5'bxxxxx}: next={`IF1, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 2'b00, 3'b000, 4'b0000, `MNONE, 1'b0};



           {`NOT,5'bxxxxx}: next={`WriteRd, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 2'b00, 3'b000, 4'b0000, `MNONE, 1'b0};



           {`Shift,5'bxxxxx}: next={`WriteRd, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 2'b00, 3'b000, 4'b0000, `MNONE, 1'b0};



           {`WriteRd,5'bxxxxx}: next={`IF1, 1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,2'b11,3'b010, 4'b0000, `MNONE, 1'b0};



	   {`SXMM, 5'bxxxxx}: next = {`DataAdd, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b1, 2'b00, 3'b000, 4'b0000, `MNONE, 1'b0};



	   {`DataAdd, 5'b01100}: next = {`ReadMem, {16{1'b0}}, `MNONE, 1'b1};
	   {`DataAdd, 5'b10000}: next = {`ReadRd, {16{1'b0}}, `MNONE, 1'b1};



	   {`ReadRd, 5'bxxxxx}: next = {`OutputRd, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 2'b00, 3'b010, 4'b0000, `MNONE, 1'b0};



	   {`OutputRd, 5'bxxxxx}: next = {`WriteMem, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 2'b00, 3'b000, 4'b0000, `MNONE, 1'b0};
	   


	   {`WriteMem, 5'bxxxxx}: next = {`IF1, 12'b000000000000, 4'b0000, `MWRITE, 1'b0};



            {`ReadMem,5'bxxxxx}: next={`WriteMemToRd, 1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,2'b00,3'b000, 4'b0000, `MREAD, 1'b0};
	    


            {`WriteMemToRd,5'bxxxxx}: next={`IF1, 1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,2'b00,3'b010, 4'b0000, `MREAD, 1'b0};


	   {`HALT,5'bxxxxx}: next={`HALT, {19{1'b0}}};

         default: next={{`SW{1'bx}},{19{1'bx}}};
         endcase
end



endmodule