data/full_repos/permissive/446312960/Verilog_Simulation/02_mux/my_mux.v
data/verilator_xmls/f81542ad-94bf-4c87-a4fb-cf10264615ed.xml
module my_mux (a,b,sel,out);

input a,b,sel;
output out;

`ifdef GATE_LEVEL
wire selb, out1, out2;
not i1(selb,sel);

and a1(out1, a, selb);
and a2(out2, b, sel);
or  o1(out, out1, out2);

`elsif   DATAFLOW_LEVEL
assign out = sel ? b : a ;

`endif

endmodule
module my_mux (a,b,sel,out);


input a,b,sel;
output out;

`ifdef GATE_LEVEL
wire selb, out1, out2;
not i1(selb,sel);

and a1(out1, a, selb);
and a2(out2, b, sel);
or  o1(out, out1, out2);

`elsif   DATAFLOW_LEVEL
assign out = sel ? b : a ;

`endif

endmodule