data/full_repos/permissive/493019833/test/testcase/firrtl/NestedModsWithReg/reference/NestedModsWithReg.v
data/verilator_xmls/df9e1374-d511-4bee-a424-b81a16869189.xml
module Level3(
    input clk,
    input reset,
    input [15:0] in1,
    output [15:0] out3
);
    wire [15:0] _reg3__q;
    wire [15:0] _reg3__d;
    DFF_POSCLK #(.width(16)) reg3 (
        .q(_reg3__q),
        .d(_reg3__d),
        .clk(clk)
    );
    assign out3 = in1;
    assign _reg3__d = in1;
endmodule
module Level3(
    input clk,
    input reset,
    input [15:0] in1,
    output [15:0] out3
);

    wire [15:0] _reg3__q;
    wire [15:0] _reg3__d;
    DFF_POSCLK #(.width(16)) reg3 (
        .q(_reg3__q),
        .d(_reg3__d),
        .clk(clk)
    );
    assign out3 = in1;
    assign _reg3__d = in1;
endmodule