data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_1r1w_rf16x160.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_1r1w_rf16x160.v:29: Cannot find include file: sys.h\n`include "sys.h" // system level definition file which contains the  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: Exiting due to 1 error(s)\n'
module iobdg_1r1w_rf16x160 (

   so_w, so_r, dout, 

   wr_en, wr_clk, wr_adr, word_wen, si_w, si_r, sehold, se, 
   rst_tri_en, reset_l, read_en, rd_clk, rd_adr, din, byte_wen, 
   testmux_sel
   );

   





   input [19:0]		byte_wen;
   input [159:0]	din;
   input [3:0]		rd_adr;
   input		rd_clk;
   input		read_en;
   input		reset_l;
   input		rst_tri_en;
   input		se;
   input		sehold;
   input		si_r;
   input		si_w;
   input [3:0]		word_wen;
   input [3:0]		wr_adr;
   input		wr_clk;
   input		wr_en;

   


   output		so_r;
   output		so_w;

   




   input 		testmux_sel;
   output [159:0] 	dout;
   wire [159:0] 	dout_array;
   wire [159:0] 	dout_scan;
   
   



   bw_r_rf16x160 bw_r_rf16x160 (.dout	(dout_array[159:0]),


				.so_w	(so_w),
				.so_r	(so_r),

				.din	(din[159:0]),
				.rd_adr	(rd_adr[3:0]),
				.wr_adr	(wr_adr[3:0]),
				.read_en(read_en),
				.wr_en	(wr_en),
				.rst_tri_en(rst_tri_en),
				.word_wen(word_wen[3:0]),
				.byte_wen(byte_wen[19:0]),
				.rd_clk	(rd_clk),
				.wr_clk	(wr_clk),
				.se	(se),
				.si_r	(si_r),
				.si_w	(si_w),
				.reset_l(reset_l),
				.sehold	(sehold));


   assign 		dout = testmux_sel ? dout_scan : dout_array;

   dff_ns #(160) dout_scan_ff (.din(dout_array),
			       .clk(rd_clk),
			       .q(dout_scan));
   
endmodule
module iobdg_1r1w_rf16x160 (

   so_w, so_r, dout, 

   wr_en, wr_clk, wr_adr, word_wen, si_w, si_r, sehold, se, 
   rst_tri_en, reset_l, read_en, rd_clk, rd_adr, din, byte_wen, 
   testmux_sel
   );


   





   input [19:0]		byte_wen;
   input [159:0]	din;
   input [3:0]		rd_adr;
   input		rd_clk;
   input		read_en;
   input		reset_l;
   input		rst_tri_en;
   input		se;
   input		sehold;
   input		si_r;
   input		si_w;
   input [3:0]		word_wen;
   input [3:0]		wr_adr;
   input		wr_clk;
   input		wr_en;

   


   output		so_r;
   output		so_w;

   




   input 		testmux_sel;
   output [159:0] 	dout;
   wire [159:0] 	dout_array;
   wire [159:0] 	dout_scan;
   
   



   bw_r_rf16x160 bw_r_rf16x160 (.dout	(dout_array[159:0]),


				.so_w	(so_w),
				.so_r	(so_r),

				.din	(din[159:0]),
				.rd_adr	(rd_adr[3:0]),
				.wr_adr	(wr_adr[3:0]),
				.read_en(read_en),
				.wr_en	(wr_en),
				.rst_tri_en(rst_tri_en),
				.word_wen(word_wen[3:0]),
				.byte_wen(byte_wen[19:0]),
				.rd_clk	(rd_clk),
				.wr_clk	(wr_clk),
				.se	(se),
				.si_r	(si_r),
				.si_w	(si_w),
				.reset_l(reset_l),
				.sehold	(sehold));


   assign 		dout = testmux_sel ? dout_scan : dout_array;

   dff_ns #(160) dout_scan_ff (.din(dout_array),
			       .clk(rd_clk),
			       .q(dout_scan));
   
endmodule