data/full_repos/permissive/484799296/verilog/rom/rom.v
data/verilator_xmls/7e7ba5fe-de6e-416a-b451-996f84ab01bf.xml
module rom (
    input [11:0] addr,
    output [15:0] data
);

    reg [15:0] mem [0:4095];

    assign data = mem[addr];

    initial begin
        $readmemb("rom.list", mem);
    end

endmodule
module rom (
    input [11:0] addr,
    output [15:0] data
);


    reg [15:0] mem [0:4095];

    assign data = mem[addr];

    initial begin
        $readmemb("rom.list", mem);
    end

endmodule