data/full_repos/permissive/499550390/andgate/andgate.v
data/verilator_xmls/4f289b8e-ebaf-4423-a810-46bce58dcda5.xml
module andgate (a,b,y);
	
	
	input a,b;
	output y;
	
	assign y = a&b;
	
endmodule
module andgate (a,b,y);

	
	
	input a,b;
	output y;
	
	assign y = a&b;
	
endmodule