data/full_repos/permissive/526589127/verilog/rtl/b_box/r8_8bit.v
1: b'%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/r8_8bit.v:2: Cannot find include file: ./const/parameters_r8mb8.v\n`include "./const/parameters_r8mb8.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters_r8mb8.v\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters_r8mb8.v.v\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters_r8mb8.v.sv\n             ./const/parameters_r8mb8.v\n             ./const/parameters_r8mb8.v.v\n             ./const/parameters_r8mb8.v.sv\n             obj_dir/./const/parameters_r8mb8.v\n             obj_dir/./const/parameters_r8mb8.v.v\n             obj_dir/./const/parameters_r8mb8.v.sv\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/r8_8bit.v:304: Cannot find include file: ./const/parameters_r8mb8.v\n`include "./const/parameters_r8mb8.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module pre_process_TMY(my, CLK, RST, TMY);
`include "./const/parameters_r8mb8.v"
input signed [WIDTH-1:0] my;
input CLK;
input RST;

output wire [WIDTH+1:0] TMY;

wire [WIDTH+1:0] SUM;


assign SUM = my+(my<<1);





assign TMY = SUM;


endmodule
module pre_process_TMY(my, CLK, RST, TMY);

`include "./const/parameters_r8mb8.v"
input signed [WIDTH-1:0] my;
input CLK;
input RST;

output wire [WIDTH+1:0] TMY;

wire [WIDTH+1:0] SUM;


assign SUM = my+(my<<1);





assign TMY = SUM;


endmodule