data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v
1: b"%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:572: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit (\n    ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference,data/full_repos/permissive/493019833/AsyncRegInit\n             data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference,data/full_repos/permissive/493019833/AsyncRegInit.v\n             data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference,data/full_repos/permissive/493019833/AsyncRegInit.sv\n             AsyncRegInit\n             AsyncRegInit.v\n             AsyncRegInit.sv\n             obj_dir/AsyncRegInit\n             obj_dir/AsyncRegInit.v\n             obj_dir/AsyncRegInit.sv\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:584: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit_1 (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:596: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit_2 (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:608: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit_3 (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:440: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:452: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit_1 (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:464: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit_2 (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:476: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit_3 (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:302: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:314: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit_1 (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:326: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit_2 (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:338: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit_3 (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:524: Cannot find file containing module: 'FakeBBClk'\n    FakeBBClk bb (\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:392: Cannot find file containing module: 'FakeBBClk'\n    FakeBBClk bb (\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:254: Cannot find file containing module: 'FakeBBClk'\n    FakeBBClk bb (\n    ^~~~~~~~~\n%Error: Exiting due to 15 error(s)\n"
module ModWithNestedClk_2(
    input clock,
    input reset,
    input io_inClk,
    output io_bbOutClk_0,
    output io_bbOutClk_1,
    output io_bbOutClk_2,
    output io_clkDivOut_0,
    output io_clkDivOut_1,
    output io_clkDivOut_2
);
    wire _bb__outClk_0;
    wire _bb__outClk_1;
    wire _bb__outClk_2;
    wire _bb__inClk;
    FakeBBClk bb (
        .outClk_0(_bb__outClk_0),
        .outClk_1(_bb__outClk_1),
        .outClk_2(_bb__outClk_2),
        .inClk(_bb__inClk)
    );
    wire _clkDiv__clock;
    wire _clkDiv__reset;
    wire _clkDiv__io_reset;
    wire _clkDiv__io_inClk;
    wire _clkDiv__io_outClks_3;
    wire _clkDiv__io_outClks_1;
    wire _clkDiv__io_outClks_0;
    SEClkDivider_2 clkDiv (
        .clock(_clkDiv__clock),
        .reset(_clkDiv__reset),
        .io_reset(_clkDiv__io_reset),
        .io_inClk(_clkDiv__io_inClk),
        .io_outClks_3(_clkDiv__io_outClks_3),
        .io_outClks_1(_clkDiv__io_outClks_1),
        .io_outClks_0(_clkDiv__io_outClks_0)
    );
    assign _bb__inClk = io_inClk;
    assign _clkDiv__clock = clock;
    assign _clkDiv__io_inClk = io_inClk;
    assign _clkDiv__io_reset = reset;
    assign _clkDiv__reset = reset;
    assign io_bbOutClk_0 = _bb__outClk_0;
    assign io_bbOutClk_1 = _bb__outClk_1;
    assign io_bbOutClk_2 = _bb__outClk_2;
    assign io_clkDivOut_0 = _clkDiv__io_outClks_0;
    assign io_clkDivOut_1 = _clkDiv__io_outClks_1;
    assign io_clkDivOut_2 = _clkDiv__io_outClks_3;
endmodule
module ModWithNestedClk_2(
    input clock,
    input reset,
    input io_inClk,
    output io_bbOutClk_0,
    output io_bbOutClk_1,
    output io_bbOutClk_2,
    output io_clkDivOut_0,
    output io_clkDivOut_1,
    output io_clkDivOut_2
);

    wire _bb__outClk_0;
    wire _bb__outClk_1;
    wire _bb__outClk_2;
    wire _bb__inClk;
    FakeBBClk bb (
        .outClk_0(_bb__outClk_0),
        .outClk_1(_bb__outClk_1),
        .outClk_2(_bb__outClk_2),
        .inClk(_bb__inClk)
    );
    wire _clkDiv__clock;
    wire _clkDiv__reset;
    wire _clkDiv__io_reset;
    wire _clkDiv__io_inClk;
    wire _clkDiv__io_outClks_3;
    wire _clkDiv__io_outClks_1;
    wire _clkDiv__io_outClks_0;
    SEClkDivider_2 clkDiv (
        .clock(_clkDiv__clock),
        .reset(_clkDiv__reset),
        .io_reset(_clkDiv__io_reset),
        .io_inClk(_clkDiv__io_inClk),
        .io_outClks_3(_clkDiv__io_outClks_3),
        .io_outClks_1(_clkDiv__io_outClks_1),
        .io_outClks_0(_clkDiv__io_outClks_0)
    );
    assign _bb__inClk = io_inClk;
    assign _clkDiv__clock = clock;
    assign _clkDiv__io_inClk = io_inClk;
    assign _clkDiv__io_reset = reset;
    assign _clkDiv__reset = reset;
    assign io_bbOutClk_0 = _bb__outClk_0;
    assign io_bbOutClk_1 = _bb__outClk_1;
    assign io_bbOutClk_2 = _bb__outClk_2;
    assign io_clkDivOut_0 = _clkDiv__io_outClks_0;
    assign io_clkDivOut_1 = _clkDiv__io_outClks_1;
    assign io_clkDivOut_2 = _clkDiv__io_outClks_3;
endmodule