data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/Program_Counter.v
data/verilator_xmls/889834c1-8ae4-4244-b383-3c0afad095f0.xml
module Program_Counter(
    input wire clk,
    input wire rst,
    input wire [5:0] I_FromCL_stall,
    input wire I_FromCL_flush,
    input wire [31:0] I_FromCL_newpc,
    input wire I_FromID_branchflag,
    input wire [31:0] I_FromID_branch_taraddr,
    output reg [31:0] O_ToIM_IFID_pc

);





always @(posedge clk or negedge rst) begin
    if(rst == 1'b0)begin
        O_ToIM_IFID_pc = -32'h4;
    end else if(I_FromCL_stall[0] == 1'b0) begin
        if (I_FromID_branchflag == 1'b1) begin
            O_ToIM_IFID_pc <= I_FromID_branch_taraddr;
        end else begin
            O_ToIM_IFID_pc <= O_ToIM_IFID_pc  + 1;
        end
    end 
end

endmodule
module Program_Counter(
    input wire clk,
    input wire rst,
    input wire [5:0] I_FromCL_stall,
    input wire I_FromCL_flush,
    input wire [31:0] I_FromCL_newpc,
    input wire I_FromID_branchflag,
    input wire [31:0] I_FromID_branch_taraddr,
    output reg [31:0] O_ToIM_IFID_pc

);






always @(posedge clk or negedge rst) begin
    if(rst == 1'b0)begin
        O_ToIM_IFID_pc = -32'h4;
    end else if(I_FromCL_stall[0] == 1'b0) begin
        if (I_FromID_branchflag == 1'b1) begin
            O_ToIM_IFID_pc <= I_FromID_branch_taraddr;
        end else begin
            O_ToIM_IFID_pc <= O_ToIM_IFID_pc  + 1;
        end
    end 
end

endmodule