data/full_repos/permissive/485085993/verilog/rtl/dff.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/485085993/verilog/rtl/dff.v:30: Multiple top level modules\n                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                            : ... Top module \'DFFQ\'\nmodule DFFQ (\n       ^~~~\n                                                                            : ... Top module \'DFF\'\nmodule DFF (\n       ^~~\n                                                                            : ... Top module \'DFFR\'\nmodule DFFR (\n       ^~~~\n                                                                            : ... Top module \'DFFRN\'\nmodule DFFRN (\n       ^~~~~\n                                                                            : ... Top module \'DFFS\'\nmodule DFFS (\n       ^~~~\n                                                                            : ... Top module \'DFFSN\'\nmodule DFFSN (\n       ^~~~~\n                                                                            : ... Top module \'DFFSR\'\nmodule DFFSR (\n       ^~~~~\n                                                                            : ... Top module \'MULTI_MODE_DFFSRQ\'\nmodule MULTI_MODE_DFFSRQ (\n       ^~~~~~~~~~~~~~~~~\n                                                                            : ... Top module \'MULTI_MODE_DFFRQ\'\nmodule MULTI_MODE_DFFRQ (\n       ^~~~~~~~~~~~~~~~\n                                                                            : ... Top module \'SDFFSR\'\nmodule SDFFSR (\n       ^~~~~~\n                                                                            : ... Top module \'SDFFRQ\'\nmodule SDFFRQ (\n       ^~~~~~\n                                                                            : ... Top module \'SDFFSRQ\'\nmodule SDFFSRQ (\n       ^~~~~~~\n                                                                            : ... Top module \'CFGSDFFR\'\nmodule CFGSDFFR (\n       ^~~~~~~~\n                                                                            : ... Top module \'BL_DFFRQ\'\nmodule BL_DFFRQ (\n       ^~~~~~~~\n                                                                            : ... Top module \'WL_DFFRQ\'\nmodule WL_DFFRQ (\n       ^~~~~~~~\n                                                                            : ... Top module \'WLR_DFFRQ\'\nmodule WLR_DFFRQ (\n       ^~~~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/dff.v:259: Little bit endian vector: MSB < LSB of bit range: 0:1\n  input [0:1] mode  \n        ^\n%Error: Exiting due to 2 warning(s)\n'
module DFFR (
  input RST,
  input CK,
  input D,
  output Q,
  output QN
);

reg q_reg;


always @ ( posedge CK or posedge RST)
if (RST) begin
  q_reg <= 1'b0;
end else begin
  q_reg <= D;
end

assign Q = q_reg;
assign QN = ~q_reg;

endmodule
module DFFR (
  input RST,
  input CK,
  input D,
  output Q,
  output QN
);


reg q_reg;


always @ ( posedge CK or posedge RST)
if (RST) begin
  q_reg <= 1'b0;
end else begin
  q_reg <= D;
end

assign Q = q_reg;
assign QN = ~q_reg;

endmodule