data/full_repos/permissive/434886680/simulation/tb_spi_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/434886680/simulation/tb_spi_test.v:34: Unsupported: Ignoring delay on this delayed statement.\n      #(250);\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/434886680/simulation/tb_spi_test.v:37: Unsupported: Ignoring delay on this delayed statement.\n      #(250);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/434886680/simulation/tb_spi_test.v:42: Unsupported: Ignoring delay on this delayed statement.\n          #(250);\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/434886680/simulation/tb_spi_test.v:44: Unsupported: Ignoring delay on this delayed statement.\n          #(250);\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/434886680/simulation/tb_spi_test.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #(250);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/434886680/simulation/tb_spi_test.v:73: Unsupported: Ignoring delay on this delayed statement.\n      #20;  \n      ^\n%Error: data/full_repos/permissive/434886680/simulation/tb_spi_test.v:90: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("tb_spi_test.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/434886680/simulation/tb_spi_test.v:91: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0, tb_spi_test);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/434886680/simulation/tb_spi_test.v:98: Unsupported: Ignoring delay on this delayed statement.\n      #100;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/434886680/simulation/tb_spi_test.v:100: Unsupported: Ignoring delay on this delayed statement.\n      #100;\n      ^\n%Error: data/full_repos/permissive/434886680/simulation/tb_spi_test.v:106: Unsupported: Verilog 1995 force\n          force u_adc_top.u_adc_core.adc.udt.sample_B = in_data;  \n          ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/434886680/simulation/tb_spi_test.v:108: Unsupported: Ignoring delay on this delayed statement.\n          #1000;\n          ^\n%Error: Exiting due to 3 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_spi_test;
  reg          CLK   = 1'b0;
  reg          XRES  = 1'b0;
  reg          SCLK;
  reg          SS;
  reg          MOSI;
  wire         MISO;
  reg  [15:0]  rdata;
  reg  [15:0]  RD;

  reg  [15:0]  in_data;

  integer      err = 0;
  integer      x   = 0;


  task spi_write;
    input [15:0] data;
    integer i;
    begin
      SS   = 1'b1;
      SCLK = 1'b0;
      #(`SPI_CLK2_DLY);
      SS   = 1'b0;
      MOSI = data[0];
      #(`SPI_CLK2_DLY);
      for (i = 0; i < 16; i = i + 1)
        begin
          MOSI = data[i];
          SCLK = 1'b0;
          #(`SPI_CLK2_DLY);
          SCLK = 1'b1;
          #(`SPI_CLK2_DLY);
        end
        SCLK = 1'b0;
        #(`SPI_CLK2_DLY);
      SS   = 1'b1;
    end
  endtask


  always @(posedge SCLK)
    if (SS)
      begin
        rdata <= 16'd0;
      end
    else
      begin
        rdata <= {rdata[14:0], MISO};
      end


  always @(posedge SS)
      begin
        RD <= rdata;
      end
  

  always
    begin
      CLK = ~CLK;
      #20;
    end


  adc_top u_adc_top
    ( 
      .CLK_IN(CLK),
      .XRES_IN(XRES),
      .SCLK(SCLK),
      .SS(SS),
      .MISO(MISO),
      .MOSI(MOSI)
      );
  

  initial
    begin
      $dumpfile("tb_spi_test.vcd");
      $dumpvars(0, tb_spi_test);
    end


  initial
    begin
      XRES = 1'b0;
      #100;
      XRES = 1'b1;
      #100;


      for (x = 0; x < 12; x = x + 1)
        begin
          in_data = 1'b1 << x;
          force u_adc_top.u_adc_core.adc.udt.sample_B = in_data;
          spi_write(16'h5555);
          #`SPI_SS_WAIT;
          if (RD !== in_data)
            begin
              err = err + 1;
              $display("ERR: %t", $time);
            end
        end

      if (err == 0)
        begin
          $display("=============");
          $display(" PASS");
          $display("=============");
        end
      else
        begin
          $display("=============");
          $display(" FAIL");
          $display("=============");
        end

      $finish;
    end

endmodule
module tb_spi_test;

  reg          CLK   = 1'b0;
  reg          XRES  = 1'b0;
  reg          SCLK;
  reg          SS;
  reg          MOSI;
  wire         MISO;
  reg  [15:0]  rdata;
  reg  [15:0]  RD;

  reg  [15:0]  in_data;

  integer      err = 0;
  integer      x   = 0;


  task spi_write;
    input [15:0] data;
    integer i;
    begin
      SS   = 1'b1;
      SCLK = 1'b0;
      #(`SPI_CLK2_DLY);
      SS   = 1'b0;
      MOSI = data[0];
      #(`SPI_CLK2_DLY);
      for (i = 0; i < 16; i = i + 1)
        begin
          MOSI = data[i];
          SCLK = 1'b0;
          #(`SPI_CLK2_DLY);
          SCLK = 1'b1;
          #(`SPI_CLK2_DLY);
        end
        SCLK = 1'b0;
        #(`SPI_CLK2_DLY);
      SS   = 1'b1;
    end
  endtask


  always @(posedge SCLK)
    if (SS)
      begin
        rdata <= 16'd0;
      end
    else
      begin
        rdata <= {rdata[14:0], MISO};
      end


  always @(posedge SS)
      begin
        RD <= rdata;
      end
  

  always
    begin
      CLK = ~CLK;
      #20;
    end


  adc_top u_adc_top
    ( 
      .CLK_IN(CLK),
      .XRES_IN(XRES),
      .SCLK(SCLK),
      .SS(SS),
      .MISO(MISO),
      .MOSI(MOSI)
      );
  

  initial
    begin
      $dumpfile("tb_spi_test.vcd");
      $dumpvars(0, tb_spi_test);
    end


  initial
    begin
      XRES = 1'b0;
      #100;
      XRES = 1'b1;
      #100;


      for (x = 0; x < 12; x = x + 1)
        begin
          in_data = 1'b1 << x;
          force u_adc_top.u_adc_core.adc.udt.sample_B = in_data;
          spi_write(16'h5555);
          #`SPI_SS_WAIT;
          if (RD !== in_data)
            begin
              err = err + 1;
              $display("ERR: %t", $time);
            end
        end

      if (err == 0)
        begin
          $display("=============");
          $display(" PASS");
          $display("=============");
        end
      else
        begin
          $display("=============");
          $display(" FAIL");
          $display("=============");
        end

      $finish;
    end

endmodule