data/full_repos/permissive/503053625/resources/verilog_source/OR_CHECK.v
1: b'%Warning-WIDTH: data/full_repos/permissive/503053625/resources/verilog_source/OR_CHECK.v:15: Operator ASSIGN expects 14 bits on the Assign RHS, but Assign RHS\'s VARREF \'ones_field\' generates 13 bits.\n                                                                                           : ... In instance OR_CHECK\n reg [IN_WIDTH - 1:0] max_out_val = ones_field;\n                                    ^~~~~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module OR_CHECK
#(
	parameter IN_WIDTH = 14
)
(
	input [IN_WIDTH - 1:0] a,
	input [IN_WIDTH - 1:0] b,
	input sub_sel,
	input [IN_WIDTH - 1:0] request,
	output [IN_WIDTH - 1:0] actual
);

    localparam ones_field = {(IN_WIDTH-1){1'b1}};
	reg [IN_WIDTH - 1:0] min_out_val = {IN_WIDTH{1'b0}};
	reg [IN_WIDTH - 1:0] max_out_val = ones_field;

	reg [IN_WIDTH - 1:0] out_val;
	
	assign actual = out_val;

	always @(a or b or request)
	begin
		if (~request[IN_WIDTH - 1])
		begin
			out_val = request;
		end
		else
		begin
			if (~sub_sel && ~b[IN_WIDTH -1])
			begin
				out_val = max_out_val;
			end
			else if (~sub_sel && b[IN_WIDTH -1])
			begin
				out_val = min_out_val;
			end
			else if (sub_sel && ~b[IN_WIDTH -1])
			begin
				out_val = min_out_val;
			end
			else
			begin
				out_val = max_out_val;
			end
		end
	end
endmodule
module OR_CHECK
#(
	parameter IN_WIDTH = 14
)
(
	input [IN_WIDTH - 1:0] a,
	input [IN_WIDTH - 1:0] b,
	input sub_sel,
	input [IN_WIDTH - 1:0] request,
	output [IN_WIDTH - 1:0] actual
);


    localparam ones_field = {(IN_WIDTH-1){1'b1}};
	reg [IN_WIDTH - 1:0] min_out_val = {IN_WIDTH{1'b0}};
	reg [IN_WIDTH - 1:0] max_out_val = ones_field;

	reg [IN_WIDTH - 1:0] out_val;
	
	assign actual = out_val;

	always @(a or b or request)
	begin
		if (~request[IN_WIDTH - 1])
		begin
			out_val = request;
		end
		else
		begin
			if (~sub_sel && ~b[IN_WIDTH -1])
			begin
				out_val = max_out_val;
			end
			else if (~sub_sel && b[IN_WIDTH -1])
			begin
				out_val = min_out_val;
			end
			else if (sub_sel && ~b[IN_WIDTH -1])
			begin
				out_val = min_out_val;
			end
			else
			begin
				out_val = max_out_val;
			end
		end
	end
endmodule