data/full_repos/permissive/412666169/UART.v
1: b'%Warning-WIDTH: data/full_repos/permissive/412666169/UART.v:10: Operator ASSIGN expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h0\' generates 13 bits.\n                                                              : ... In instance HW1_UART\nreg [13:0]freq = 13\'d0;\n                 ^~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/412666169/UART.v:18: Cannot find file containing module: \'edge_detect\'\nedge_detect ed1(.clk(clk_50M),.rst_n(reset_n),.data_in(write),.pos_edge(w_pos),.neg_edge(w_neg));\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/412666169,data/full_repos/permissive/412666169/edge_detect\n             data/full_repos/permissive/412666169,data/full_repos/permissive/412666169/edge_detect.v\n             data/full_repos/permissive/412666169,data/full_repos/permissive/412666169/edge_detect.sv\n             edge_detect\n             edge_detect.v\n             edge_detect.sv\n             obj_dir/edge_detect\n             obj_dir/edge_detect.v\n             obj_dir/edge_detect.sv\n%Warning-WIDTH: data/full_repos/permissive/412666169/UART.v:24: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                              : ... In instance HW1_UART\n  freq <= 1\'d0;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/412666169/UART.v:26: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                              : ... In instance HW1_UART\n  freq <= 1\'d0;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/412666169/UART.v:25: Operator EQ expects 14 bits on the RHS, but RHS\'s CONST \'13\'h1458\' generates 13 bits.\n                                                              : ... In instance HW1_UART\n else if(freq == 13\'d5208)\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/412666169/UART.v:43: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                              : ... In instance HW1_UART\n   i = 4\'d0;\n     ^\n%Warning-WIDTH: data/full_repos/permissive/412666169/UART.v:57: Bit extraction of var[7:0] requires 3 bit index, not 5 bits.\n                                                              : ... In instance HW1_UART\n     TX = indata[i];\n                ^\n%Warning-WIDTH: data/full_repos/permissive/412666169/UART.v:63: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                              : ... In instance HW1_UART\n     i = 4\'d0;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/412666169/UART.v:55: Operator LT expects 5 bits on the RHS, but RHS\'s CONST \'4\'h8\' generates 4 bits.\n                                                              : ... In instance HW1_UART\n    if(i < 4\'d8)\n         ^\n%Error: Exiting due to 1 error(s), 8 warning(s)\n'
module HW1_UART(
	input [7:0]indata, 
	input clk_50M,
	input write,
	input reset_n, 
	output uart_txd
	);
	
reg [13:0]freq = 13'd0;
reg [4:0]i = 5'd0;
reg TX = 1'b1;
reg flag = 1'b0;
reg sflag = 1'b0;
reg dflag = 1'b0;
wire w_pos;
wire w_neg;
edge_detect ed1(.clk(clk_50M),.rst_n(reset_n),.data_in(write),.pos_edge(w_pos),.neg_edge(w_neg));

assign uart_txd = TX;
always@(posedge clk_50M or negedge reset_n)
begin
	if(!reset_n)
		freq <= 1'd0;
	else if(freq == 13'd5208)
		freq <= 1'd0;
	else
		freq <= freq + 1'd1;
end

always@(posedge clk_50M or negedge reset_n)
begin
	if(!reset_n)
	begin
		TX = 1'b1;
		flag = 1'b0;
	end
	else
	begin
		if(w_neg)
		begin
			flag = 1'b1;
			i = 4'd0;
			sflag = 1'b1;
		end
		if(freq == 0 && sflag == 1'b1)
		begin
			TX = 1'b0;
			sflag = 1'b0;
		end
		if(flag && !sflag)
		begin
			if(freq == 5208)
			begin
				if(i < 4'd8)
				begin
					TX = indata[i];
					i = i + 1'd1;
				end
				else
				begin
					TX = 1'b1;
					i = 4'd0;
					flag = 1'b0;
				end
			end
		end
	end
end

endmodule
module HW1_UART(
	input [7:0]indata, 
	input clk_50M,
	input write,
	input reset_n, 
	output uart_txd
	);

	
reg [13:0]freq = 13'd0;
reg [4:0]i = 5'd0;
reg TX = 1'b1;
reg flag = 1'b0;
reg sflag = 1'b0;
reg dflag = 1'b0;
wire w_pos;
wire w_neg;
edge_detect ed1(.clk(clk_50M),.rst_n(reset_n),.data_in(write),.pos_edge(w_pos),.neg_edge(w_neg));

assign uart_txd = TX;
always@(posedge clk_50M or negedge reset_n)
begin
	if(!reset_n)
		freq <= 1'd0;
	else if(freq == 13'd5208)
		freq <= 1'd0;
	else
		freq <= freq + 1'd1;
end

always@(posedge clk_50M or negedge reset_n)
begin
	if(!reset_n)
	begin
		TX = 1'b1;
		flag = 1'b0;
	end
	else
	begin
		if(w_neg)
		begin
			flag = 1'b1;
			i = 4'd0;
			sflag = 1'b1;
		end
		if(freq == 0 && sflag == 1'b1)
		begin
			TX = 1'b0;
			sflag = 1'b0;
		end
		if(flag && !sflag)
		begin
			if(freq == 5208)
			begin
				if(i < 4'd8)
				begin
					TX = indata[i];
					i = i + 1'd1;
				end
				else
				begin
					TX = 1'b1;
					i = 4'd0;
					flag = 1'b0;
				end
			end
		end
	end
end

endmodule