data/full_repos/permissive/449652714/src/sources_1/rtl/loader.v
1: b'%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/loader.v:7: Cannot find include file: define.vh\n`include "define.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/449652714/src/sources_1/rtl,data/full_repos/permissive/449652714/define.vh\n             data/full_repos/permissive/449652714/src/sources_1/rtl,data/full_repos/permissive/449652714/define.vh.v\n             data/full_repos/permissive/449652714/src/sources_1/rtl,data/full_repos/permissive/449652714/define.vh.sv\n             define.vh\n             define.vh.v\n             define.vh.sv\n             obj_dir/define.vh\n             obj_dir/define.vh.v\n             obj_dir/define.vh.sv\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/loader.v:52: Define or directive not defined: \'`BIN_SIZE\'\n                if(waddr>=`BIN_SIZE) DONE <= 1;\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/loader.v:52: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n                if(waddr>=`BIN_SIZE) DONE <= 1;\n                                   ^\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/loader.v:82: Define or directive not defined: \'`SERIAL_WCNT\'\n        end else if( waitnum >= `SERIAL_WCNT ) begin\n                                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/loader.v:82: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        end else if( waitnum >= `SERIAL_WCNT ) begin\n                                             ^\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/loader.v:88: syntax error, unexpected else\n        end else begin\n            ^~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/loader.v:123: Define or directive not defined: \'`SERIAL_WCNT\'\n    assign waitcnt = `SERIAL_WCNT;\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/loader.v:123: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    assign waitcnt = `SERIAL_WCNT;\n                                 ^\n%Error: Exiting due to 8 error(s)\n'
module UartTx(CLK, RST_X, DATA, WE, TXD, READY);
    input  wire        CLK, RST_X, WE;
    input  wire [7:0]  DATA;
    output reg         TXD, READY;
    reg [8:0]   cmd;
    reg [31:0]  waitnum;
    reg [3:0]   cnt;

    always @(posedge CLK) begin
        if(!RST_X) begin
            TXD       <= 1'b1;
            READY     <= 1'b1;
            cmd       <= 9'h1ff;
            waitnum   <= 0;
            cnt       <= 0;
        end else if( READY ) begin
            TXD       <= 1'b1;
            waitnum   <= 0;
            if( WE )begin
                READY <= 1'b0;
                cmd   <= {DATA, 1'b0};
                cnt   <= 10;
            end
        end else if( waitnum >= `SERIAL_WCNT ) begin
            TXD       <= cmd[0];
            READY     <= (cnt == 1);
            cmd       <= {1'b1, cmd[8:1]};
            waitnum   <= 1;
            cnt       <= cnt - 1;
        end else begin
            waitnum   <= waitnum + 1;
        end
    end

    (* mark_debug *) reg WE_d;
    (* mark_debug *) reg [7:0] DATA_d;
    always @(posedge CLK) begin
	WE_d <= WE;
	if(WE) begin
	    DATA_d <= DATA;
	end
    end

endmodule
module UartTx(CLK, RST_X, DATA, WE, TXD, READY);

    input  wire        CLK, RST_X, WE;
    input  wire [7:0]  DATA;
    output reg         TXD, READY;
    reg [8:0]   cmd;
    reg [31:0]  waitnum;
    reg [3:0]   cnt;

    always @(posedge CLK) begin
        if(!RST_X) begin
            TXD       <= 1'b1;
            READY     <= 1'b1;
            cmd       <= 9'h1ff;
            waitnum   <= 0;
            cnt       <= 0;
        end else if( READY ) begin
            TXD       <= 1'b1;
            waitnum   <= 0;
            if( WE )begin
                READY <= 1'b0;
                cmd   <= {DATA, 1'b0};
                cnt   <= 10;
            end
        end else if( waitnum >= `SERIAL_WCNT ) begin
            TXD       <= cmd[0];
            READY     <= (cnt == 1);
            cmd       <= {1'b1, cmd[8:1]};
            waitnum   <= 1;
            cnt       <= cnt - 1;
        end else begin
            waitnum   <= waitnum + 1;
        end
    end

    (* mark_debug *) reg WE_d;
    (* mark_debug *) reg [7:0] DATA_d;
    always @(posedge CLK) begin
	WE_d <= WE;
	if(WE) begin
	    DATA_d <= DATA;
	end
    end

endmodule