data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v
1: b'%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:3: Cannot find include file: noc_parameter.vh\n    `include "noc_parameter.vh" \n             ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh\n             data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.v\n             data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.sv\n             noc_parameter.vh\n             noc_parameter.vh.v\n             noc_parameter.vh.sv\n             obj_dir/noc_parameter.vh\n             obj_dir/noc_parameter.vh.v\n             obj_dir/noc_parameter.vh.sv\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:4: Cannot find include file: ddr4_user_parameter.vh\n    ,`include "ddr4_user_parameter.vh" \n              ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:4: syntax error, unexpected \',\', expecting \'[\'\n    , \n    ^\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:6: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter HOME_MODID = {NOC_MODID_SIZE{1\'b0}},\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:7: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter SIMULATION = 0         \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:8: syntax error, unexpected \')\', expecting \';\'\n)\n^\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:11: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire                                  sys_clk_p,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:12: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire            [NOC_CHIPID_SIZE-1:0] home_chipid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:13: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire                                  sys_rst,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:14: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire                                  ddr4_clk_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:15: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire                                  ddr4_init_calib_complete_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:16: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire           [DDR4_STATUS_SIZE-1:0] ddr4_status_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:19: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] noc_fifo_in_data_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:20: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire        [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_in_raddr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:21: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire        [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_in_waddr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:22: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] noc_fifo_out_data_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:23: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire        [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_out_raddr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:24: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire        [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_out_waddr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:26: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire                                  ddr4_act_n,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:27: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire                           [16:0] ddr4_addr,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:28: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire                            [1:0] ddr4_ba,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:29: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire                                  ddr4_bg,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:30: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire                                  ddr4_cke,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:31: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire                                  ddr4_odt,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:32: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire                                  ddr4_cs_n,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:33: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire                                  ddr4_ck_t,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:34: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire                                  ddr4_ck_c,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:35: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire                                  ddr4_reset_n,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:36: syntax error, unexpected inout, expecting IDENTIFIER or do or final\n    inout   wire                            [9:0] ddr4_dm_dbi_n,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:37: syntax error, unexpected inout, expecting IDENTIFIER or do or final\n    inout   wire                           [79:0] ddr4_dq,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:38: syntax error, unexpected inout, expecting IDENTIFIER or do or final\n    inout   wire                            [9:0] ddr4_dqs_c,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:39: syntax error, unexpected inout, expecting IDENTIFIER or do or final\n    inout   wire                            [9:0] ddr4_dqs_t\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:40: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_domain.v:48: syntax error, unexpected IDENTIFIER\nddr4_wrap #(\n^~~~~~~~~\n%Error: Exiting due to 34 error(s)\n'
module ddr4_domain #(
    `include "noc_parameter.vh"
    ,`include "ddr4_user_parameter.vh"
    ,parameter INST = "C1",
    parameter HOME_MODID = {NOC_MODID_SIZE{1'b0}},
    parameter SIMULATION = 0
)
(
    input   wire                                  sys_clk_n,
    input   wire                                  sys_clk_p,
    input   wire            [NOC_CHIPID_SIZE-1:0] home_chipid_i,
    input   wire                                  sys_rst,
    input   wire                                  ddr4_clk_i,
    output  wire                                  ddr4_init_calib_complete_o,
    output  wire           [DDR4_STATUS_SIZE-1:0] ddr4_status_o,


    input	wire [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] noc_fifo_in_data_i,
    output	wire        [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_in_raddr_o,
    input	wire        [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_in_waddr_i,
    output	wire [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] noc_fifo_out_data_o,
    input	wire        [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_out_raddr_i,
    output	wire        [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_out_waddr_o,

    output  wire                                  ddr4_act_n,
    output  wire                           [16:0] ddr4_addr,
    output  wire                            [1:0] ddr4_ba,
    output  wire                                  ddr4_bg,
    output  wire                                  ddr4_cke,
    output  wire                                  ddr4_odt,
    output  wire                                  ddr4_cs_n,
    output  wire                                  ddr4_ck_t,
    output  wire                                  ddr4_ck_c,
    output  wire                                  ddr4_reset_n,
    inout   wire                            [9:0] ddr4_dm_dbi_n,
    inout   wire                           [79:0] ddr4_dq,
    inout   wire                            [9:0] ddr4_dqs_c,
    inout   wire                            [9:0] ddr4_dqs_t
);

    wire ddr4_rst_n_s;

    wire [NOC_CHIPID_SIZE-1:0] home_chipid_s;



ddr4_wrap #(
    .INST                        (INST),
    .HOME_MODID                  (HOME_MODID),
    .SIMULATION                  (SIMULATION)
) i_ddr4_wrap (
    .sys_clk_n                   (sys_clk_n),
    .sys_clk_p                   (sys_clk_p),
    .sys_rst                     (sys_rst),
    .home_chipid_i               (home_chipid_s),
    .ddr4_clk_i                  (ddr4_clk_i),
    .ddr4_rst_n_i                (ddr4_rst_n_s),
    .ddr4_init_calib_complete_o  (ddr4_init_calib_complete_o),
    .ddr4_status_o               (ddr4_status_o),

    .noc_fifo_in_data_i          (noc_fifo_in_data_i),
    .noc_fifo_in_raddr_o         (noc_fifo_in_raddr_o),
    .noc_fifo_in_waddr_i         (noc_fifo_in_waddr_i),
    .noc_fifo_out_data_o         (noc_fifo_out_data_o),
    .noc_fifo_out_raddr_i        (noc_fifo_out_raddr_i),
    .noc_fifo_out_waddr_o        (noc_fifo_out_waddr_o),

    .ddr4_act_n                  (ddr4_act_n),
    .ddr4_addr                   (ddr4_addr),
    .ddr4_ba                     (ddr4_ba),
    .ddr4_bg                     (ddr4_bg),
    .ddr4_cke                    (ddr4_cke),
    .ddr4_odt                    (ddr4_odt),
    .ddr4_cs_n                   (ddr4_cs_n),
    .ddr4_ck_t                   (ddr4_ck_t),
    .ddr4_ck_c                   (ddr4_ck_c),
    .ddr4_reset_n                (ddr4_reset_n),
    .ddr4_dm_dbi_n               (ddr4_dm_dbi_n),
    .ddr4_dq                     (ddr4_dq),
    .ddr4_dqs_c                  (ddr4_dqs_c),
    .ddr4_dqs_t                  (ddr4_dqs_t)
);



util_reset_sync i_util_reset_sync_ref (
    .clk_i             (ddr4_clk_i),
    .reset_q_i         (~sys_rst),
    .scan_mode_i       (1'b0),
    .sync_reset_q_o    (ddr4_rst_n_s)
);


util_sync #(
    .WIDTH     (NOC_CHIPID_SIZE)
) i_util_sync_chipid (
    .clk_i     (ddr4_clk_i),
    .reset_n_i (ddr4_rst_n_s),
    .data_i    (home_chipid_i),
    .data_o    (home_chipid_s)
);


endmodule
module ddr4_domain #(
    `include "noc_parameter.vh"
    ,`include "ddr4_user_parameter.vh"
    ,parameter INST = "C1",
    parameter HOME_MODID = {NOC_MODID_SIZE{1'b0}},
    parameter SIMULATION = 0
)
(
    input   wire                                  sys_clk_n,
    input   wire                                  sys_clk_p,
    input   wire            [NOC_CHIPID_SIZE-1:0] home_chipid_i,
    input   wire                                  sys_rst,
    input   wire                                  ddr4_clk_i,
    output  wire                                  ddr4_init_calib_complete_o,
    output  wire           [DDR4_STATUS_SIZE-1:0] ddr4_status_o,


    input	wire [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] noc_fifo_in_data_i,
    output	wire        [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_in_raddr_o,
    input	wire        [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_in_waddr_i,
    output	wire [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] noc_fifo_out_data_o,
    input	wire        [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_out_raddr_i,
    output	wire        [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_out_waddr_o,

    output  wire                                  ddr4_act_n,
    output  wire                           [16:0] ddr4_addr,
    output  wire                            [1:0] ddr4_ba,
    output  wire                                  ddr4_bg,
    output  wire                                  ddr4_cke,
    output  wire                                  ddr4_odt,
    output  wire                                  ddr4_cs_n,
    output  wire                                  ddr4_ck_t,
    output  wire                                  ddr4_ck_c,
    output  wire                                  ddr4_reset_n,
    inout   wire                            [9:0] ddr4_dm_dbi_n,
    inout   wire                           [79:0] ddr4_dq,
    inout   wire                            [9:0] ddr4_dqs_c,
    inout   wire                            [9:0] ddr4_dqs_t
);


    wire ddr4_rst_n_s;

    wire [NOC_CHIPID_SIZE-1:0] home_chipid_s;



ddr4_wrap #(
    .INST                        (INST),
    .HOME_MODID                  (HOME_MODID),
    .SIMULATION                  (SIMULATION)
) i_ddr4_wrap (
    .sys_clk_n                   (sys_clk_n),
    .sys_clk_p                   (sys_clk_p),
    .sys_rst                     (sys_rst),
    .home_chipid_i               (home_chipid_s),
    .ddr4_clk_i                  (ddr4_clk_i),
    .ddr4_rst_n_i                (ddr4_rst_n_s),
    .ddr4_init_calib_complete_o  (ddr4_init_calib_complete_o),
    .ddr4_status_o               (ddr4_status_o),

    .noc_fifo_in_data_i          (noc_fifo_in_data_i),
    .noc_fifo_in_raddr_o         (noc_fifo_in_raddr_o),
    .noc_fifo_in_waddr_i         (noc_fifo_in_waddr_i),
    .noc_fifo_out_data_o         (noc_fifo_out_data_o),
    .noc_fifo_out_raddr_i        (noc_fifo_out_raddr_i),
    .noc_fifo_out_waddr_o        (noc_fifo_out_waddr_o),

    .ddr4_act_n                  (ddr4_act_n),
    .ddr4_addr                   (ddr4_addr),
    .ddr4_ba                     (ddr4_ba),
    .ddr4_bg                     (ddr4_bg),
    .ddr4_cke                    (ddr4_cke),
    .ddr4_odt                    (ddr4_odt),
    .ddr4_cs_n                   (ddr4_cs_n),
    .ddr4_ck_t                   (ddr4_ck_t),
    .ddr4_ck_c                   (ddr4_ck_c),
    .ddr4_reset_n                (ddr4_reset_n),
    .ddr4_dm_dbi_n               (ddr4_dm_dbi_n),
    .ddr4_dq                     (ddr4_dq),
    .ddr4_dqs_c                  (ddr4_dqs_c),
    .ddr4_dqs_t                  (ddr4_dqs_t)
);



util_reset_sync i_util_reset_sync_ref (
    .clk_i             (ddr4_clk_i),
    .reset_q_i         (~sys_rst),
    .scan_mode_i       (1'b0),
    .sync_reset_q_o    (ddr4_rst_n_s)
);


util_sync #(
    .WIDTH     (NOC_CHIPID_SIZE)
) i_util_sync_chipid (
    .clk_i     (ddr4_clk_i),
    .reset_n_i (ddr4_rst_n_s),
    .data_i    (home_chipid_i),
    .data_o    (home_chipid_s)
);


endmodule