data/full_repos/permissive/520428138/verilog/rtl/user_module_341493393195532884.v
data/verilator_xmls/45353a9e-2f32-4532-8131-900317a99fdd.xml
module full_addr_341493393195532884
    #(
         parameter WIDTH = 16
     )
     (
         input      [WIDTH-1:0] a,
         input      [WIDTH-1:0] b,
         output reg [WIDTH-1:0] y = 0
     );

    integer i;
    reg [WIDTH-1:0] c = 1;
generate always @(*) begin
            c[0] = 0;
            y[0] = c[0] ^ (a[0] ^ b[0]);
            c[0] = a[0]&b[0] | b[0]&c[0] | a[0]&c[0];
            for (i = 1; i < WIDTH; i = i +1) begin
                y[i] = c[i -1] ^ (a[i] ^ b[i]);
                c[i] = a[i]&b[i] | b[i]&c[i -1] | a[i]&c[i -1];
            end
        end endgenerate

endmodule
module full_addr_341493393195532884
    #(
         parameter WIDTH = 16
     )
     (
         input      [WIDTH-1:0] a,
         input      [WIDTH-1:0] b,
         output reg [WIDTH-1:0] y = 0
     );


    integer i;
    reg [WIDTH-1:0] c = 1;
generate always @(*) begin
            c[0] = 0;
            y[0] = c[0] ^ (a[0] ^ b[0]);
            c[0] = a[0]&b[0] | b[0]&c[0] | a[0]&c[0];
            for (i = 1; i < WIDTH; i = i +1) begin
                y[i] = c[i -1] ^ (a[i] ^ b[i]);
                c[i] = a[i]&b[i] | b[i]&c[i -1] | a[i]&c[i -1];
            end
        end endgenerate

endmodule