data/full_repos/permissive/49670587/vtr/ODIN_II/FULL_REGRESSION_TESTS/paj_framebuftop_hierarchy_no_mem_no_combinational.v
1: b'%Warning-WIDTH: data/full_repos/permissive/49670587/vtr/ODIN_II/FULL_REGRESSION_TESTS/paj_framebuftop_hierarchy_no_mem_no_combinational.v:295: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                                                                                             : ... In instance paj_framebuftop_hierarchy_no_mem.vidoutinst\n       tm3_vidout_red <= {(({1\'b0, primarypixel[20:14]}) + ({1\'b0, primarybuffer[20:14]})), 3\'b000} ; \n                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/49670587/vtr/ODIN_II/FULL_REGRESSION_TESTS/paj_framebuftop_hierarchy_no_mem_no_combinational.v:296: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                                                                                             : ... In instance paj_framebuftop_hierarchy_no_mem.vidoutinst\n       tm3_vidout_green <= {(({1\'b0, primarypixel[13:7]}) + ({1\'b0, primarybuffer[13:7]})), 3\'b000} ; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/49670587/vtr/ODIN_II/FULL_REGRESSION_TESTS/paj_framebuftop_hierarchy_no_mem_no_combinational.v:297: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                                                                                             : ... In instance paj_framebuftop_hierarchy_no_mem.vidoutinst\n       tm3_vidout_blue <= {(({1\'b0, primarypixel[6:0]}) + ({1\'b0, primarybuffer[6:0]})), 3\'b000} ; \n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/49670587/vtr/ODIN_II/FULL_REGRESSION_TESTS/paj_framebuftop_hierarchy_no_mem_no_combinational.v:310: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                                                                                             : ... In instance paj_framebuftop_hierarchy_no_mem.vidoutinst\n       tm3_vidout_red <= {(({1\'b0, primarypixel[20:14]}) + ({1\'b0, secondarypixel[20:14]})), 3\'b000} ; \n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/49670587/vtr/ODIN_II/FULL_REGRESSION_TESTS/paj_framebuftop_hierarchy_no_mem_no_combinational.v:311: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                                                                                             : ... In instance paj_framebuftop_hierarchy_no_mem.vidoutinst\n       tm3_vidout_green <= {(({1\'b0, primarypixel[13:7]}) + ({1\'b0, secondarypixel[13:7]})), 3\'b000} ; \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/49670587/vtr/ODIN_II/FULL_REGRESSION_TESTS/paj_framebuftop_hierarchy_no_mem_no_combinational.v:312: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                                                                                             : ... In instance paj_framebuftop_hierarchy_no_mem.vidoutinst\n       tm3_vidout_blue <= {(({1\'b0, primarypixel[6:0]}) + ({1\'b0, secondarypixel[6:0]})), 3\'b000} ; \n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/49670587/vtr/ODIN_II/FULL_REGRESSION_TESTS/paj_framebuftop_hierarchy_no_mem_no_combinational.v:322: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 12 bits.\n                                                                                                                                             : ... In instance paj_framebuftop_hierarchy_no_mem.vidoutinst\n       tm3_vidout_red <= {(({2\'b00, primarypixel[20:14]}) \n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/49670587/vtr/ODIN_II/FULL_REGRESSION_TESTS/paj_framebuftop_hierarchy_no_mem_no_combinational.v:326: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 12 bits.\n                                                                                                                                             : ... In instance paj_framebuftop_hierarchy_no_mem.vidoutinst\n       tm3_vidout_green <= {(({2\'b00, primarypixel[13:7]}) \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/49670587/vtr/ODIN_II/FULL_REGRESSION_TESTS/paj_framebuftop_hierarchy_no_mem_no_combinational.v:330: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 12 bits.\n                                                                                                                                             : ... In instance paj_framebuftop_hierarchy_no_mem.vidoutinst\n       tm3_vidout_blue <= {(({2\'b00, primarypixel[6:0]}) \n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/49670587/vtr/ODIN_II/FULL_REGRESSION_TESTS/paj_framebuftop_hierarchy_no_mem_no_combinational.v:43: Input port connection \'fbdata\' expects 63 bits on the pin connection, but pin connection\'s VARREF \'fbdata\' generates 64 bits.\n                                                                                                                                            : ... In instance paj_framebuftop_hierarchy_no_mem\n    scanlinebuffer scanlinebuf (pixeldataA, pixeldataB, pixeldataC, nextpixelA, nextpixelB, nextpixelC, startframe, nextscanline, fbdata, fbnextscanlineint, fbdatavalid, globalreset, tm3_clk_v0); \n                                                                                                                                  ^~~~~~\n%Error: Exiting due to 10 warning(s)\n'
module scanline (nextpixel, we, datain, pixeldata, globalreset, clk);

    input nextpixel; 
    input we; 
    input[62:0] datain; 
    output[20:0] pixeldata; 
    reg[20:0] pixeldata;
    input globalreset; 
    input clk; 

    reg[6:0] addr; 
    reg[6:0] waddr; 

    reg[6:0] raddr; 
    reg[1:0] subitem; 
    reg wedelayed; 
    reg[62:0]mem1; 
    reg[62:0]mem2; 
    wire[62:0] mdataout; 

    assign mdataout = mem2 ;

    always @(posedge clk)
    begin
       if (globalreset == 1'b1)
       begin
          subitem <= 2'b00 ; 
          waddr <= 1;
          raddr <= 1;
          wedelayed <= 1'b0 ; 
          pixeldata <= 1;
       end
       else
       begin
          wedelayed <= we ; 
          if (nextpixel == 1'b1 | wedelayed == 1'b1)
          begin

             case (subitem)
                2'b00 :
                         begin
                            pixeldata <= mdataout[62:42] ; 
                         end
                2'b01 :
                         begin
                            pixeldata <= mdataout[41:21] ; 
                         end
                2'b10 :
                         begin
                            pixeldata <= mdataout[20:0] ; 

                         end
                default :
                         begin
                            pixeldata <= 1;
                         end
             endcase 
          end 
          if (nextpixel == 1'b1)
          begin
             case (subitem)
                2'b00 :
                         begin

                            subitem <= 2'b01 ; 
                         end
                2'b01 :
                         begin
                            subitem <= 2'b10 ; 
                         end
                2'b10 :
                         begin
                            subitem <= 2'b00 ; 
                            if (raddr != 7'b1101010)
                            begin
                               raddr <= raddr + 1 ; 
                            end
                            else
                            begin
                               raddr <= 1;
                            end 
                         end
             endcase 
          end 
          if (we == 1'b1)
          begin
             if (waddr != 7'b1101010)
             begin
                waddr <= waddr + 1 ; 
             end
             else
             begin

                waddr <= 1;
             end 
          end 
       end 
     end 

	always @(posedge clk)
	begin
       addr <= raddr ; 
       if (we == 1'b1)
       begin
          mem1 <= datain ; 
          mem2 <= mem1 ; 
       end  
	end
 endmodule
module scanline (nextpixel, we, datain, pixeldata, globalreset, clk);


    input nextpixel; 
    input we; 
    input[62:0] datain; 
    output[20:0] pixeldata; 
    reg[20:0] pixeldata;
    input globalreset; 
    input clk; 

    reg[6:0] addr; 
    reg[6:0] waddr; 

    reg[6:0] raddr; 
    reg[1:0] subitem; 
    reg wedelayed; 
    reg[62:0]mem1; 
    reg[62:0]mem2; 
    wire[62:0] mdataout; 

    assign mdataout = mem2 ;

    always @(posedge clk)
    begin
       if (globalreset == 1'b1)
       begin
          subitem <= 2'b00 ; 
          waddr <= 1;
          raddr <= 1;
          wedelayed <= 1'b0 ; 
          pixeldata <= 1;
       end
       else
       begin
          wedelayed <= we ; 
          if (nextpixel == 1'b1 | wedelayed == 1'b1)
          begin

             case (subitem)
                2'b00 :
                         begin
                            pixeldata <= mdataout[62:42] ; 
                         end
                2'b01 :
                         begin
                            pixeldata <= mdataout[41:21] ; 
                         end
                2'b10 :
                         begin
                            pixeldata <= mdataout[20:0] ; 

                         end
                default :
                         begin
                            pixeldata <= 1;
                         end
             endcase 
          end 
          if (nextpixel == 1'b1)
          begin
             case (subitem)
                2'b00 :
                         begin

                            subitem <= 2'b01 ; 
                         end
                2'b01 :
                         begin
                            subitem <= 2'b10 ; 
                         end
                2'b10 :
                         begin
                            subitem <= 2'b00 ; 
                            if (raddr != 7'b1101010)
                            begin
                               raddr <= raddr + 1 ; 
                            end
                            else
                            begin
                               raddr <= 1;
                            end 
                         end
             endcase 
          end 
          if (we == 1'b1)
          begin
             if (waddr != 7'b1101010)
             begin
                waddr <= waddr + 1 ; 
             end
             else
             begin

                waddr <= 1;
             end 
          end 
       end 
     end 

	always @(posedge clk)
	begin
       addr <= raddr ; 
       if (we == 1'b1)
       begin
          mem1 <= datain ; 
          mem2 <= mem1 ; 
       end  
	end
 endmodule