data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v:24: Unsupported: Ignoring delay on this delayed statement.\n   always #5 clock <= ~clock;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v:28: Unsupported: Ignoring delay on this delayed statement.\n   initial #1000 reset = 1\'b0;\n           ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v:30: Unsupported or unknown PLI call: $dumpfile\n   initial $dumpfile("test_hbd.vcd");\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v:31: Unsupported or unknown PLI call: $dumpvars\n   initial $dumpvars(0,test_hbd);\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v:55: syntax error, unexpected \'@\'\n @(negedge reset);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v:60: syntax error, unexpected \'@\'\n      @(posedge clock);\n      ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v:62: Define or directive not defined: \'`RATE\'\n      repeat (`RATE)\n              ^~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v:62: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n      repeat (`RATE)\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v:67: Unsupported: Ignoring delay on this delayed statement.\n   initial #10000000 $finish;     \n           ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v:72: syntax error, unexpected \'@\'\n repeat (40) @(posedge strobe_in);\n             ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v:74: syntax error, unexpected \'@\'\n @(posedge strobe_in);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v:76: syntax error, unexpected \'@\'\n repeat (40) @(posedge strobe_in);\n             ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v:78: syntax error, unexpected \'@\'\n @(posedge strobe_in);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v:80: syntax error, unexpected \'@\'\n repeat (40) @(posedge strobe_in);\n             ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v:82: syntax error, unexpected \'@\'\n repeat (40) @(posedge strobe_in);\n             ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v:84: syntax error, unexpected \'@\'\n repeat (41) @(posedge strobe_in);\n             ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v:86: syntax error, unexpected \'@\'\n repeat (40) @(posedge strobe_in);\n             ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v:88: syntax error, unexpected \'@\'\n repeat (40) @(posedge strobe_in);\n             ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v:89: syntax error, unexpected \'@\'\n repeat (7) @(posedge clock);\n            ^\n%Error: Exiting due to 16 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_hbd();

   reg clock;
   initial clock = 1'b0;
   always #5 clock <= ~clock;

   reg reset;
   initial reset = 1'b1;
   initial #1000 reset = 1'b0;
   
   initial $dumpfile("test_hbd.vcd");
   initial $dumpvars(0,test_hbd);

   reg [15:0] i_in, q_in;
   wire [15:0] i_out, q_out;

   reg 	       strobe_in;
   wire        strobe_out;
   reg 	       coeff_write;
   reg [15:0]  coeff_data;
   reg [4:0]   coeff_addr;
   
   halfband_decim halfband_decim 
     ( .clock(clock),.reset(reset),.enable(),.strobe_in(strobe_in),.strobe_out(strobe_out),
       .data_in(i_in),.data_out(i_out) );
   
   always @(posedge strobe_out)
     if(i_out[15])
       $display("-%d",65536-i_out);
     else
       $display("%d",i_out);

   initial
     begin
	strobe_in = 1'b0;
	@(negedge reset);
	@(posedge clock);
	while(1)
	  begin
	     strobe_in <= #1 1'b1;
	     @(posedge clock);
	     strobe_in <= #1 1'b0;
	     repeat (`RATE)
	       @(posedge clock);
	  end
     end

   initial #10000000 $finish;

   initial
     begin
	i_in <= #1 16'd0;
	repeat (40) @(posedge strobe_in);
	i_in <= #1 16'd16384;
	@(posedge strobe_in);
	i_in <= #1 16'd0;
	repeat (40) @(posedge strobe_in);
	i_in <= #1 16'd16384;
	@(posedge strobe_in);
	i_in <= #1 16'd0;
	repeat (40) @(posedge strobe_in);
	i_in <= #1 16'd16384;
	repeat (40) @(posedge strobe_in);
	i_in <= #1 16'd0;
	repeat (41) @(posedge strobe_in);
	i_in <= #1 16'd16384;
	repeat (40) @(posedge strobe_in);
	i_in <= #1 16'd0;
	repeat (40) @(posedge strobe_in);
	repeat (7) @(posedge clock);
	$finish;
     end
endmodule
module test_hbd();


   reg clock;
   initial clock = 1'b0;
   always #5 clock <= ~clock;

   reg reset;
   initial reset = 1'b1;
   initial #1000 reset = 1'b0;
   
   initial $dumpfile("test_hbd.vcd");
   initial $dumpvars(0,test_hbd);

   reg [15:0] i_in, q_in;
   wire [15:0] i_out, q_out;

   reg 	       strobe_in;
   wire        strobe_out;
   reg 	       coeff_write;
   reg [15:0]  coeff_data;
   reg [4:0]   coeff_addr;
   
   halfband_decim halfband_decim 
     ( .clock(clock),.reset(reset),.enable(),.strobe_in(strobe_in),.strobe_out(strobe_out),
       .data_in(i_in),.data_out(i_out) );
   
   always @(posedge strobe_out)
     if(i_out[15])
       $display("-%d",65536-i_out);
     else
       $display("%d",i_out);

   initial
     begin
	strobe_in = 1'b0;
	@(negedge reset);
	@(posedge clock);
	while(1)
	  begin
	     strobe_in <= #1 1'b1;
	     @(posedge clock);
	     strobe_in <= #1 1'b0;
	     repeat (`RATE)
	       @(posedge clock);
	  end
     end

   initial #10000000 $finish;

   initial
     begin
	i_in <= #1 16'd0;
	repeat (40) @(posedge strobe_in);
	i_in <= #1 16'd16384;
	@(posedge strobe_in);
	i_in <= #1 16'd0;
	repeat (40) @(posedge strobe_in);
	i_in <= #1 16'd16384;
	@(posedge strobe_in);
	i_in <= #1 16'd0;
	repeat (40) @(posedge strobe_in);
	i_in <= #1 16'd16384;
	repeat (40) @(posedge strobe_in);
	i_in <= #1 16'd0;
	repeat (41) @(posedge strobe_in);
	i_in <= #1 16'd16384;
	repeat (40) @(posedge strobe_in);
	i_in <= #1 16'd0;
	repeat (40) @(posedge strobe_in);
	repeat (7) @(posedge clock);
	$finish;
     end
endmodule