data/full_repos/permissive/506562943/HDLBits/Circuits/Sequential Logic/Latches and Flip-Flops/edgecapture.v
1: b'%Error: Cannot find file containing module: Logic/Latches\n        ... Looked in:\n             data/full_repos/permissive/506562943/HDLBits/Circuits/Sequential/Logic/Latches\n             data/full_repos/permissive/506562943/HDLBits/Circuits/Sequential/Logic/Latches.v\n             data/full_repos/permissive/506562943/HDLBits/Circuits/Sequential/Logic/Latches.sv\n             Logic/Latches\n             Logic/Latches.v\n             Logic/Latches.sv\n             obj_dir/Logic/Latches\n             obj_dir/Logic/Latches.v\n             obj_dir/Logic/Latches.sv\n%Error: Cannot find file containing module: and\n%Error: Cannot find file containing module: Flip-Flops,data/full_repos/permissive/506562943\n%Error: Cannot find file containing module: data/full_repos/permissive/506562943/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Flip-Flops/edgecapture.v\n%Error: Exiting due to 5 error(s)\n'
module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);

    reg [31:0] last, outval;

    always @(posedge clk) begin
        if (reset) begin

            last <= in;
            outval <= 32'd0;
            out <= 0;
        end
        else begin


            outval |= ~in & last;

            out = outval;

            last = in;
        end
    end

endmodule
module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);


    reg [31:0] last, outval;

    always @(posedge clk) begin
        if (reset) begin

            last <= in;
            outval <= 32'd0;
            out <= 0;
        end
        else begin


            outval |= ~in & last;

            out = outval;

            last = in;
        end
    end

endmodule