data/full_repos/permissive/508331744/verilog/rtl/ALU.v
1: b'%Warning-WIDTH: data/full_repos/permissive/508331744/verilog/rtl/ALU.v:44: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS\'s SEL generates 6 bits.\n                                                                         : ... In instance ALU\nassign shamt = alu_in2[5:0];  \n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/508331744/verilog/rtl/ALU.v:80: Cannot find file containing module: \'SQRT_CSLA_ZFC\'\nSQRT_CSLA_ZFC adder (.A(alu_reg1),\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/508331744/verilog/rtl,data/full_repos/permissive/508331744/SQRT_CSLA_ZFC\n             data/full_repos/permissive/508331744/verilog/rtl,data/full_repos/permissive/508331744/SQRT_CSLA_ZFC.v\n             data/full_repos/permissive/508331744/verilog/rtl,data/full_repos/permissive/508331744/SQRT_CSLA_ZFC.sv\n             SQRT_CSLA_ZFC\n             SQRT_CSLA_ZFC.v\n             SQRT_CSLA_ZFC.sv\n             obj_dir/SQRT_CSLA_ZFC\n             obj_dir/SQRT_CSLA_ZFC.v\n             obj_dir/SQRT_CSLA_ZFC.sv\n%Warning-WIDTH: data/full_repos/permissive/508331744/verilog/rtl/ALU.v:91: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'ADD_SUB\' generates 4 bits.\n                                                                         : ... In instance ALU\n    case(sel[4:0])\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/508331744/verilog/rtl/ALU.v:91: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'XOR\' generates 4 bits.\n                                                                         : ... In instance ALU\n    case(sel[4:0])\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/508331744/verilog/rtl/ALU.v:91: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'OR\' generates 4 bits.\n                                                                         : ... In instance ALU\n    case(sel[4:0])\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/508331744/verilog/rtl/ALU.v:91: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'AND\' generates 4 bits.\n                                                                         : ... In instance ALU\n    case(sel[4:0])\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/508331744/verilog/rtl/ALU.v:91: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'SLTU\' generates 4 bits.\n                                                                         : ... In instance ALU\n    case(sel[4:0])\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/508331744/verilog/rtl/ALU.v:91: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'SLT\' generates 4 bits.\n                                                                         : ... In instance ALU\n    case(sel[4:0])\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/508331744/verilog/rtl/ALU.v:91: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'SRL\' generates 4 bits.\n                                                                         : ... In instance ALU\n    case(sel[4:0])\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/508331744/verilog/rtl/ALU.v:91: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'SRLIW\' generates 4 bits.\n                                                                         : ... In instance ALU\n    case(sel[4:0])\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/508331744/verilog/rtl/ALU.v:91: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'SLL\' generates 4 bits.\n                                                                         : ... In instance ALU\n    case(sel[4:0])\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/508331744/verilog/rtl/ALU.v:91: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'SLLIW\' generates 4 bits.\n                                                                         : ... In instance ALU\n    case(sel[4:0])\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/508331744/verilog/rtl/ALU.v:91: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'SRAW\' generates 4 bits.\n                                                                         : ... In instance ALU\n    case(sel[4:0])\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/508331744/verilog/rtl/ALU.v:91: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'SRA\' generates 4 bits.\n                                                                         : ... In instance ALU\n    case(sel[4:0])\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/508331744/verilog/rtl/ALU.v:91: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'BEQ\' generates 4 bits.\n                                                                         : ... In instance ALU\n    case(sel[4:0])\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/508331744/verilog/rtl/ALU.v:91: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'BNE\' generates 4 bits.\n                                                                         : ... In instance ALU\n    case(sel[4:0])\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/508331744/verilog/rtl/ALU.v:91: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'BGTU\' generates 4 bits.\n                                                                         : ... In instance ALU\n    case(sel[4:0])\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/508331744/verilog/rtl/ALU.v:91: Operator CASE expects 5 bits on the Case Item, but Case Item\'s VARREF \'BGT\' generates 4 bits.\n                                                                         : ... In instance ALU\n    case(sel[4:0])\n    ^~~~\n%Error: Exiting due to 1 error(s), 17 warning(s)\n'
module ALU(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif 
    input [63:0] alu_in1,
    input [63:0] alu_in2, 
    input [6:0] sel,
    input alu_select,sladd,
    output reg [63:0] alu_out
    );

wire cout;
reg cin;
wire Z;
reg [63:0] alu_reg1;
reg [63:0] alu_reg2;
reg [63:0] adder_reg2;
wire [63:0] adder_out;
wire [31:0] src1_32;
wire [4:0] shamt;

localparam ADD_SUB = 4'b0000;
localparam XOR     = 4'b0001;
localparam OR      = 4'b0010;
localparam AND     = 4'b0011;
localparam SLTU    = 4'b0100;
localparam SLT     = 4'b0101;
localparam SRL     = 4'b0110;
localparam SRLIW   = 4'b0111;
localparam SLL     = 4'b1000;
localparam SLLIW   = 4'b1001;
localparam SRAW    = 4'b1010;
localparam SRA     = 4'b1011;
localparam BEQ     = 4'b1100;
localparam BNE     = 4'b1101;
localparam BGTU    = 4'b1110;
localparam BGT     = 4'b1111;



assign shamt = alu_in2[5:0];
assign src1_32 = alu_in1[31:0];



always @(*) begin
    
if (alu_select)begin 

alu_reg1 = alu_in1;
alu_reg2 = alu_in2;

    if (sel[5])
        cin        = 0;
    else if (sladd) begin
        cin        = 0;        
        alu_reg1   = alu_in1 << 1;
        adder_reg2 = alu_in2;       
    end 

    else begin
        cin        = 1;
        alu_reg1   = alu_in1;
        adder_reg2 = alu_in2 ^ {64{cin}};
    end
end
else if (!alu_select) begin
    cin        = 0;
    alu_reg1   = alu_reg1;
    alu_reg2   = alu_reg2;
    adder_reg2 = adder_reg2;   
end
end



SQRT_CSLA_ZFC adder (.A(alu_reg1),
                     .B(adder_reg2),
                     .cin(cin),
                     .Y(adder_out),    
                     .cout(cout),
                     .Z(Z)
 
);

always @(*) begin

    case(sel[4:0])
       ADD_SUB: alu_out = adder_out;
       XOR    : alu_out = alu_reg1 ^ alu_reg2;
       OR     : alu_out = alu_reg1 | alu_reg2;
       AND    : alu_out = alu_reg1 & alu_reg2;
       SLTU   : alu_out = (~cout) ? 64'd1:64'd0;
       SLT    : alu_out = (adder_out[63]) ? 64'd1 : 64'd0;
       SRL    : alu_out = ((alu_reg1)) >> shamt;
       SRLIW  : alu_out = {{32{alu_reg1[31]}},(src1_32) >> shamt};
       SLL    : alu_out = (alu_reg1) << shamt;
       SLLIW  : alu_out = {{32{alu_reg1[31]}},((src1_32)) << shamt};
       SRAW   : alu_out = {{32{alu_reg1[31]}},((src1_32)) >>> shamt};
       SRA    : alu_out = ($signed(alu_reg1)) >>> shamt;
       BEQ    : alu_out = (Z) ?  64'd1 : 64'd0;
       BNE    : alu_out = (Z) ?  64'd0 : 64'd1;
       BGTU   : alu_out = (cout | Z) ? 64'd1 : 64'd0;
       BGT    : alu_out = (~adder_out[63] | Z) ? 64'd1 : 64'd0;
endcase
end
endmodule
module ALU(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif 
    input [63:0] alu_in1,
    input [63:0] alu_in2, 
    input [6:0] sel,
    input alu_select,sladd,
    output reg [63:0] alu_out
    );


wire cout;
reg cin;
wire Z;
reg [63:0] alu_reg1;
reg [63:0] alu_reg2;
reg [63:0] adder_reg2;
wire [63:0] adder_out;
wire [31:0] src1_32;
wire [4:0] shamt;

localparam ADD_SUB = 4'b0000;
localparam XOR     = 4'b0001;
localparam OR      = 4'b0010;
localparam AND     = 4'b0011;
localparam SLTU    = 4'b0100;
localparam SLT     = 4'b0101;
localparam SRL     = 4'b0110;
localparam SRLIW   = 4'b0111;
localparam SLL     = 4'b1000;
localparam SLLIW   = 4'b1001;
localparam SRAW    = 4'b1010;
localparam SRA     = 4'b1011;
localparam BEQ     = 4'b1100;
localparam BNE     = 4'b1101;
localparam BGTU    = 4'b1110;
localparam BGT     = 4'b1111;



assign shamt = alu_in2[5:0];
assign src1_32 = alu_in1[31:0];



always @(*) begin
    
if (alu_select)begin 

alu_reg1 = alu_in1;
alu_reg2 = alu_in2;

    if (sel[5])
        cin        = 0;
    else if (sladd) begin
        cin        = 0;        
        alu_reg1   = alu_in1 << 1;
        adder_reg2 = alu_in2;       
    end 

    else begin
        cin        = 1;
        alu_reg1   = alu_in1;
        adder_reg2 = alu_in2 ^ {64{cin}};
    end
end
else if (!alu_select) begin
    cin        = 0;
    alu_reg1   = alu_reg1;
    alu_reg2   = alu_reg2;
    adder_reg2 = adder_reg2;   
end
end



SQRT_CSLA_ZFC adder (.A(alu_reg1),
                     .B(adder_reg2),
                     .cin(cin),
                     .Y(adder_out),    
                     .cout(cout),
                     .Z(Z)
 
);

always @(*) begin

    case(sel[4:0])
       ADD_SUB: alu_out = adder_out;
       XOR    : alu_out = alu_reg1 ^ alu_reg2;
       OR     : alu_out = alu_reg1 | alu_reg2;
       AND    : alu_out = alu_reg1 & alu_reg2;
       SLTU   : alu_out = (~cout) ? 64'd1:64'd0;
       SLT    : alu_out = (adder_out[63]) ? 64'd1 : 64'd0;
       SRL    : alu_out = ((alu_reg1)) >> shamt;
       SRLIW  : alu_out = {{32{alu_reg1[31]}},(src1_32) >> shamt};
       SLL    : alu_out = (alu_reg1) << shamt;
       SLLIW  : alu_out = {{32{alu_reg1[31]}},((src1_32)) << shamt};
       SRAW   : alu_out = {{32{alu_reg1[31]}},((src1_32)) >>> shamt};
       SRA    : alu_out = ($signed(alu_reg1)) >>> shamt;
       BEQ    : alu_out = (Z) ?  64'd1 : 64'd0;
       BNE    : alu_out = (Z) ?  64'd0 : 64'd1;
       BGTU   : alu_out = (cout | Z) ? 64'd1 : 64'd0;
       BGT    : alu_out = (~adder_out[63] | Z) ? 64'd1 : 64'd0;
endcase
end
endmodule