data/full_repos/permissive/429462627/mips_pipeline.v
1: b'%Error: data/full_repos/permissive/429462627/mips_pipeline.v:138: Unsupported or unknown PLI call: $monitor\n        $monitor($time, " :A = %b,\\n\\t B = %b,\\n\\t ALU_ctrlerartion = %b,\\n\\t Result = %b,\\n\\t Carry Out = %b,\\n\\t Zero = %b.", A, B, ALU_ctrl, result, carry_out, zero);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:139: Unsupported: Ignoring delay on this delayed statement.\n        #0  A = 32\'ha5a5a5a5; B = 32\'h5a5a5a5a; ALU_ctrl = 4\'b0000;      \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:140: Unsupported: Ignoring delay on this delayed statement.\n        #10  ALU_ctrl = 4\'b0001;                                         \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:141: Unsupported: Ignoring delay on this delayed statement.\n        #10  ALU_ctrl = 4\'b0010;                                         \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:142: Unsupported: Ignoring delay on this delayed statement.\n        #10  ALU_ctrl = 4\'b0110;                                         \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:143: Unsupported: Ignoring delay on this delayed statement.\n        #10  A = 32\'hA5A5A5A5; B = 32\'hA5A5A5A5; ALU_ctrl = 4\'b0110;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:144: Unsupported: Ignoring delay on this delayed statement.\n        #10  B = 32\'hA5A5A5A5; A = 32\'h5A5A5A5A; ALU_ctrl = 4\'b0111;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:145: Unsupported: Ignoring delay on this delayed statement.\n        #10  B = 32\'hA5A5A5A5; A = 32\'h5A5A5A5A; ALU_ctrl = 4\'b1100;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:146: Unsupported: Ignoring delay on this delayed statement.\n        #20  $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:1090: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk = ~clk;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:1096: Unsupported: Ignoring delay on this delayed statement.\n        #5 reset = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:1098: Unsupported: Ignoring delay on this delayed statement.\n        #300 $finish;\n        ^\n%Error: Exiting due to 1 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main_control ( 
    input [5:0] op_code,
    output RegDst, Jump, Branch, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite,
    output [1:0] ALU_op);

    assign RegDst =(~op_code[5])&(~op_code[4])&(~op_code[3])&(~op_code[2])&(~op_code[1])&(~op_code[0]);
    assign Jump =(~op_code[5])&(~op_code[4])&(~op_code[3])&(~op_code[2])&(op_code[1])&(~op_code[0]);
    assign Branch =(~op_code[5])&(~op_code[4])&(~op_code[3])&(op_code[2])&(~op_code[1])&(~op_code[0]);
    assign MemRead =(op_code[5])&(~op_code[4])&(~op_code[3])&(~op_code[2])&(op_code[1])&(op_code[0]);
    assign MemtoReg =(op_code[5])&(~op_code[4])&(~op_code[3])&(~op_code[2])&(op_code[1])&(op_code[0]);
    assign MemWrite =(op_code[5])&(~op_code[4])&(op_code[3])&(~op_code[2])&(op_code[1])&(op_code[0]);

    assign ALUSrc = ((~op_code[5])&(~op_code[4])&(op_code[3])&(~op_code[2])&(~op_code[1])&(~op_code[0])) |
                    ((~op_code[5])&(~op_code[4])&(op_code[3])&(op_code[2])&(~op_code[1])&(~op_code[0])) |
                    ((op_code[5])&(~op_code[4])&(~op_code[3])&(~op_code[2])&(op_code[1])&(op_code[0])) |
                    (((op_code[5])&(~op_code[4])&(op_code[3])&(~op_code[2])&(op_code[1])&(op_code[0]))) |
                    ((~op_code[5])&(~op_code[4])&(op_code[3])&(op_code[2])&(~op_code[1])&(op_code[0])) |
                    (((~op_code[5])&(~op_code[4])&(op_code[3])&(~op_code[2])&(op_code[1])&(~op_code[0])));

    assign RegWrite = (~op_code[5])&(~op_code[4])&(~op_code[3])&(~op_code[2])&(~op_code[1])&(~op_code[0]) |
                      ((~op_code[5])&(~op_code[4])&(op_code[3])&(~op_code[2])&(~op_code[1])&(~op_code[0])) |
                      ((~op_code[5])&(~op_code[4])&(op_code[3])&(op_code[2])&(~op_code[1])&(~op_code[0])) |
                      ((op_code[5])&(~op_code[4])&(~op_code[3])&(~op_code[2])&(op_code[1])&(op_code[0])) |
                      ((~op_code[5])&(~op_code[4])&(op_code[3])&(op_code[2])&(~op_code[1])&(op_code[0])) |
                      ((~op_code[5])&(~op_code[4])&(op_code[3])&(~op_code[2])&(op_code[1])&(~op_code[0]));
    
    assign ALU_op[1] = ((~op_code[5])&(~op_code[4])&(~op_code[3])&(~op_code[2])&(~op_code[1])&(~op_code[0])) |
                       ((~op_code[5])&(~op_code[4])&(op_code[3])&(op_code[2])&(~op_code[1])&(~op_code[0])) |
                       ((~op_code[5])&(~op_code[4])&(op_code[3])&(~op_code[2])&(~op_code[1])&(~op_code[0])) |
                       ((~op_code[5])&(~op_code[4])&(op_code[3])&(op_code[2])&(~op_code[1])&(op_code[0])) |
                       ((~op_code[5])&(~op_code[4])&(op_code[3])&(~op_code[2])&(op_code[1])&(~op_code[0]));

    assign ALU_op[0] = ((~op_code[5])&(~op_code[4])&(~op_code[3])&(op_code[2])&(~op_code[1])&(~op_code[0])) |
                       ((~op_code[5])&(~op_code[4])&(op_code[3])&(op_code[2])&(~op_code[1])&(~op_code[0])) |
                       ((~op_code[5])&(~op_code[4])&(op_code[3])&(~op_code[2])&(~op_code[1])&(~op_code[0])) |
                       ((~op_code[5])&(~op_code[4])&(op_code[3])&(op_code[2])&(~op_code[1])&(op_code[0])) |
                       ((~op_code[5])&(~op_code[4])&(op_code[3])&(~op_code[2])&(op_code[1])&(~op_code[0]));
endmodule
module main_control ( 
    input [5:0] op_code,
    output RegDst, Jump, Branch, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite,
    output [1:0] ALU_op);


    assign RegDst =(~op_code[5])&(~op_code[4])&(~op_code[3])&(~op_code[2])&(~op_code[1])&(~op_code[0]);
    assign Jump =(~op_code[5])&(~op_code[4])&(~op_code[3])&(~op_code[2])&(op_code[1])&(~op_code[0]);
    assign Branch =(~op_code[5])&(~op_code[4])&(~op_code[3])&(op_code[2])&(~op_code[1])&(~op_code[0]);
    assign MemRead =(op_code[5])&(~op_code[4])&(~op_code[3])&(~op_code[2])&(op_code[1])&(op_code[0]);
    assign MemtoReg =(op_code[5])&(~op_code[4])&(~op_code[3])&(~op_code[2])&(op_code[1])&(op_code[0]);
    assign MemWrite =(op_code[5])&(~op_code[4])&(op_code[3])&(~op_code[2])&(op_code[1])&(op_code[0]);

    assign ALUSrc = ((~op_code[5])&(~op_code[4])&(op_code[3])&(~op_code[2])&(~op_code[1])&(~op_code[0])) |
                    ((~op_code[5])&(~op_code[4])&(op_code[3])&(op_code[2])&(~op_code[1])&(~op_code[0])) |
                    ((op_code[5])&(~op_code[4])&(~op_code[3])&(~op_code[2])&(op_code[1])&(op_code[0])) |
                    (((op_code[5])&(~op_code[4])&(op_code[3])&(~op_code[2])&(op_code[1])&(op_code[0]))) |
                    ((~op_code[5])&(~op_code[4])&(op_code[3])&(op_code[2])&(~op_code[1])&(op_code[0])) |
                    (((~op_code[5])&(~op_code[4])&(op_code[3])&(~op_code[2])&(op_code[1])&(~op_code[0])));

    assign RegWrite = (~op_code[5])&(~op_code[4])&(~op_code[3])&(~op_code[2])&(~op_code[1])&(~op_code[0]) |
                      ((~op_code[5])&(~op_code[4])&(op_code[3])&(~op_code[2])&(~op_code[1])&(~op_code[0])) |
                      ((~op_code[5])&(~op_code[4])&(op_code[3])&(op_code[2])&(~op_code[1])&(~op_code[0])) |
                      ((op_code[5])&(~op_code[4])&(~op_code[3])&(~op_code[2])&(op_code[1])&(op_code[0])) |
                      ((~op_code[5])&(~op_code[4])&(op_code[3])&(op_code[2])&(~op_code[1])&(op_code[0])) |
                      ((~op_code[5])&(~op_code[4])&(op_code[3])&(~op_code[2])&(op_code[1])&(~op_code[0]));
    
    assign ALU_op[1] = ((~op_code[5])&(~op_code[4])&(~op_code[3])&(~op_code[2])&(~op_code[1])&(~op_code[0])) |
                       ((~op_code[5])&(~op_code[4])&(op_code[3])&(op_code[2])&(~op_code[1])&(~op_code[0])) |
                       ((~op_code[5])&(~op_code[4])&(op_code[3])&(~op_code[2])&(~op_code[1])&(~op_code[0])) |
                       ((~op_code[5])&(~op_code[4])&(op_code[3])&(op_code[2])&(~op_code[1])&(op_code[0])) |
                       ((~op_code[5])&(~op_code[4])&(op_code[3])&(~op_code[2])&(op_code[1])&(~op_code[0]));

    assign ALU_op[0] = ((~op_code[5])&(~op_code[4])&(~op_code[3])&(op_code[2])&(~op_code[1])&(~op_code[0])) |
                       ((~op_code[5])&(~op_code[4])&(op_code[3])&(op_code[2])&(~op_code[1])&(~op_code[0])) |
                       ((~op_code[5])&(~op_code[4])&(op_code[3])&(~op_code[2])&(~op_code[1])&(~op_code[0])) |
                       ((~op_code[5])&(~op_code[4])&(op_code[3])&(op_code[2])&(~op_code[1])&(op_code[0])) |
                       ((~op_code[5])&(~op_code[4])&(op_code[3])&(~op_code[2])&(op_code[1])&(~op_code[0]));
endmodule