data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_lib.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_lib.v:27: Cannot find include file: sys.h\n`include "sys.h"  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: Exiting due to 1 error(s)\n'
module ctu_mux21 (d0, d1, s, z);

parameter SIZE = 1;
input [SIZE-1:0] d0 ;
input [SIZE-1:0] d1 ;
input s;

output [SIZE-1:0]      z ;

wire [SIZE-1:0] z_pre ;      



     bw_u1_muxi21_4x u_muxi21 [SIZE-1:0] (
    .z(z_pre), .d0(d0), .d1(d1), .s(s) );

     bw_u1_inv_5x u_inv [SIZE-1:0] (
     .z(z), .a(z_pre));

endmodule
module ctu_mux21 (d0, d1, s, z);


parameter SIZE = 1;
input [SIZE-1:0] d0 ;
input [SIZE-1:0] d1 ;
input s;

output [SIZE-1:0]      z ;

wire [SIZE-1:0] z_pre ;      



     bw_u1_muxi21_4x u_muxi21 [SIZE-1:0] (
    .z(z_pre), .d0(d0), .d1(d1), .s(s) );

     bw_u1_inv_5x u_inv [SIZE-1:0] (
     .z(z), .a(z_pre));

endmodule