data/full_repos/permissive/497604366/cpu/cpu.srcs/sources_1/new/fwdamux.v
data/verilator_xmls/d8a67f11-3222-4575-8270-bc7169ab2f62.xml
module fwdamux(
    input [1:0] fwda,
    input [31:0] qa,
    input [31:0] r,
    input [31:0] mr,
    input [31:00] mdo,
    output reg [31:00] fwda_output
    );
    always @(*) begin
        if (fwda == 2'b00) begin
            fwda_output <= qa;
        end
        else if (fwda == 2'b01) begin
            fwda_output <= mr;
        end
        else if (fwda == 2'b10) begin
            fwda_output <= mr;
        end
        else if (fwda == 2'b11) begin
            fwda_output <= mdo;
        end
    end
endmodule
module fwdamux(
    input [1:0] fwda,
    input [31:0] qa,
    input [31:0] r,
    input [31:0] mr,
    input [31:00] mdo,
    output reg [31:00] fwda_output
    );

    always @(*) begin
        if (fwda == 2'b00) begin
            fwda_output <= qa;
        end
        else if (fwda == 2'b01) begin
            fwda_output <= mr;
        end
        else if (fwda == 2'b10) begin
            fwda_output <= mr;
        end
        else if (fwda == 2'b11) begin
            fwda_output <= mdo;
        end
    end
endmodule