data/full_repos/permissive/428334706/verilog/rtl/BB/ibex_controller.v
1: b'%Error: data/full_repos/permissive/428334706/verilog/rtl/BB/ibex_controller.v:130: Can\'t find definition of scope/variable: \'ibex_core\'\n   $display("%t: Illegal instruction (core %0d) at PC 0x%h: 0x%h", $time, ibex_core.core_id_i, ibex_id_stage.pc_id_i, ibex_id_stage.instr_rdata_i);\n                                                                          ^~~~~~~~~\n%Error: data/full_repos/permissive/428334706/verilog/rtl/BB/ibex_controller.v:130: Can\'t find definition of scope/variable: \'ibex_id_stage\'\n   $display("%t: Illegal instruction (core %0d) at PC 0x%h: 0x%h", $time, ibex_core.core_id_i, ibex_id_stage.pc_id_i, ibex_id_stage.instr_rdata_i);\n                                                                                               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/428334706/verilog/rtl/BB/ibex_controller.v:130: Can\'t find definition of scope/variable: \'ibex_id_stage\'\n   $display("%t: Illegal instruction (core %0d) at PC 0x%h: 0x%h", $time, ibex_core.core_id_i, ibex_id_stage.pc_id_i, ibex_id_stage.instr_rdata_i);\n                                                                                                                      ^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
function automatic [5:0] sv2v_cast_6;
		input reg [5:0] inp;
		sv2v_cast_6 = inp;
	endfunction
function automatic [5:0] sv2v_cast_6;

		input reg [5:0] inp;
		sv2v_cast_6 = inp;
	endfunction