data/full_repos/permissive/528677531/LAB-7/Q1/QA/q.v
data/verilator_xmls/857799e2-032c-4e30-b853-b6198dad1e16.xml
module eighttoone(d,s,f);
input d;
input [2:0]s;
output f;
reg f;
always @(s)
begin
	case(s)
	0:f=0;
	1:f=0;
	2:f=1;
	3:f=1;
	4:f=1;
	5:f=0;
	6:f=1;
	7:f=~d;
	endcase
end
endmodule
module eighttoone(d,s,f);

input d;
input [2:0]s;
output f;
reg f;
always @(s)
begin
	case(s)
	0:f=0;
	1:f=0;
	2:f=1;
	3:f=1;
	4:f=1;
	5:f=0;
	6:f=1;
	7:f=~d;
	endcase
end
endmodule