data/full_repos/permissive/484543204/verilog/rtl/ece5745_project_wrapper.v
1: b"%Error: data/full_repos/permissive/484543204/verilog/rtl/ece5745_project_wrapper.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/484543204/verilog/rtl/ece5745_project_wrapper.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/484543204/verilog/rtl/ece5745_project_wrapper.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,  \n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/484543204/verilog/rtl/ece5745_project_wrapper.v:72: Define or directive not defined: '`MPRJ_IO_PADS'\n    inout [`MPRJ_IO_PADS-10:0] analog_io,\n           ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module ece5745_project_wrapper #(
    parameter BITS = 32
) (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,





    inout [`MPRJ_IO_PADS-10:0] analog_io,


    input   user_clock2,


    output [2:0] user_irq
);









































grp_15_SPI_TapeOutBlock_32bits_5entries grp_15
(
`ifdef USE_POWER_PINS
	.vccd1(vccd1),
	.vssd1(vssd1),
`endif 
    .clk(io_in[26]),
    .reset(io_in[27]),
    .loopthrough_sel(io_in[35]),
    .minion_parity(io_out[36]),
    .adapter_parity(io_out[37]),
    .cs(io_in[8]),
    .sclk(io_in[9]),
    .miso(io_out[10]),
    .mosi(io_in[11]),
    .lt_sel_en(io_oeb[35]),
    .mp_en(io_oeb[36]),
    .ap_en(io_oeb[37]),
    .cs_en(io_oeb[8]),
    .sclk_en(io_oeb[9]),
    .miso_en(io_oeb[10]),
    .mosi_en(io_oeb[11])
);

grp_16_SPI_TapeOutBlock_32bits_5entries grp_16
(
`ifdef USE_POWER_PINS
	.vccd1(vccd1),
	.vssd1(vssd1),
`endif 
    .clk(io_in[26]),
    .reset(io_in[27]),
    .loopthrough_sel(io_in[25]),
    .minion_parity(io_out[24]),
    .adapter_parity(io_out[23]),
    .cs(io_in[22]),
    .sclk(io_in[21]),
    .miso(io_out[20]),
    .mosi(io_in[19]),
    .lt_sel_en(io_oeb[25]),
    .mp_en(io_oeb[24]),
    .ap_en(io_oeb[23]),
    .cs_en(io_oeb[22]),
    .sclk_en(io_oeb[21]),
    .miso_en(io_oeb[20]),
    .mosi_en(io_oeb[19])
);

grp_17_SPI_TapeOutBlock_32bits_5entries grp_17
(
`ifdef USE_POWER_PINS
	.vccd1(vccd1),
	.vssd1(vssd1),
`endif 
    .clk(io_in[26]),
    .reset(io_in[27]),
    .loopthrough_sel(io_in[34]),
    .minion_parity(io_out[33]),
    .adapter_parity(io_out[32]),
    .cs(io_in[31]),
    .sclk(io_in[30]),
    .miso(io_out[29]),
    .mosi(io_in[28]),
    .lt_sel_en(io_oeb[34]),
    .mp_en(io_oeb[33]),
    .ap_en(io_oeb[32]),
    .cs_en(io_oeb[31]),
    .sclk_en(io_oeb[30]),
    .miso_en(io_oeb[29]),
    .mosi_en(io_oeb[28])
);

grp_99_SPI_TapeOutBlock_32bits_5entries grp_99
(
`ifdef USE_POWER_PINS
	.vccd1(vccd1),
	.vssd1(vssd1),
`endif 
    .clk(io_in[26]),
    .reset(io_in[27]),
    .loopthrough_sel(io_in[12]),
    .minion_parity(io_out[13]),
    .adapter_parity(io_out[14]),
    .cs(io_in[15]),
    .sclk(io_in[16]),
    .miso(io_out[17]),
    .mosi(io_in[18]),
    .clk_en(io_oeb[26]),
    .reset_en(io_oeb[27]),
    .lt_sel_en(io_oeb[12]),
    .mp_en(io_oeb[13]),
    .ap_en(io_oeb[14]),
    .cs_en(io_oeb[15]),
    .sclk_en(io_oeb[16]),
    .miso_en(io_oeb[17]),
    .mosi_en(io_oeb[18])
);

endmodule
module ece5745_project_wrapper #(
    parameter BITS = 32
) (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,





    inout [`MPRJ_IO_PADS-10:0] analog_io,


    input   user_clock2,


    output [2:0] user_irq
);










































grp_15_SPI_TapeOutBlock_32bits_5entries grp_15
(
`ifdef USE_POWER_PINS
	.vccd1(vccd1),
	.vssd1(vssd1),
`endif 
    .clk(io_in[26]),
    .reset(io_in[27]),
    .loopthrough_sel(io_in[35]),
    .minion_parity(io_out[36]),
    .adapter_parity(io_out[37]),
    .cs(io_in[8]),
    .sclk(io_in[9]),
    .miso(io_out[10]),
    .mosi(io_in[11]),
    .lt_sel_en(io_oeb[35]),
    .mp_en(io_oeb[36]),
    .ap_en(io_oeb[37]),
    .cs_en(io_oeb[8]),
    .sclk_en(io_oeb[9]),
    .miso_en(io_oeb[10]),
    .mosi_en(io_oeb[11])
);

grp_16_SPI_TapeOutBlock_32bits_5entries grp_16
(
`ifdef USE_POWER_PINS
	.vccd1(vccd1),
	.vssd1(vssd1),
`endif 
    .clk(io_in[26]),
    .reset(io_in[27]),
    .loopthrough_sel(io_in[25]),
    .minion_parity(io_out[24]),
    .adapter_parity(io_out[23]),
    .cs(io_in[22]),
    .sclk(io_in[21]),
    .miso(io_out[20]),
    .mosi(io_in[19]),
    .lt_sel_en(io_oeb[25]),
    .mp_en(io_oeb[24]),
    .ap_en(io_oeb[23]),
    .cs_en(io_oeb[22]),
    .sclk_en(io_oeb[21]),
    .miso_en(io_oeb[20]),
    .mosi_en(io_oeb[19])
);

grp_17_SPI_TapeOutBlock_32bits_5entries grp_17
(
`ifdef USE_POWER_PINS
	.vccd1(vccd1),
	.vssd1(vssd1),
`endif 
    .clk(io_in[26]),
    .reset(io_in[27]),
    .loopthrough_sel(io_in[34]),
    .minion_parity(io_out[33]),
    .adapter_parity(io_out[32]),
    .cs(io_in[31]),
    .sclk(io_in[30]),
    .miso(io_out[29]),
    .mosi(io_in[28]),
    .lt_sel_en(io_oeb[34]),
    .mp_en(io_oeb[33]),
    .ap_en(io_oeb[32]),
    .cs_en(io_oeb[31]),
    .sclk_en(io_oeb[30]),
    .miso_en(io_oeb[29]),
    .mosi_en(io_oeb[28])
);

grp_99_SPI_TapeOutBlock_32bits_5entries grp_99
(
`ifdef USE_POWER_PINS
	.vccd1(vccd1),
	.vssd1(vssd1),
`endif 
    .clk(io_in[26]),
    .reset(io_in[27]),
    .loopthrough_sel(io_in[12]),
    .minion_parity(io_out[13]),
    .adapter_parity(io_out[14]),
    .cs(io_in[15]),
    .sclk(io_in[16]),
    .miso(io_out[17]),
    .mosi(io_in[18]),
    .clk_en(io_oeb[26]),
    .reset_en(io_oeb[27]),
    .lt_sel_en(io_oeb[12]),
    .mp_en(io_oeb[13]),
    .ap_en(io_oeb[14]),
    .cs_en(io_oeb[15]),
    .sclk_en(io_oeb[16]),
    .miso_en(io_oeb[17]),
    .mosi_en(io_oeb[18])
);

endmodule