data/full_repos/permissive/447223480/03_branch/cpu.v
data/verilator_xmls/ef745a06-91c9-4025-8e90-b28da7cb2eee.xml
module pmem(addr, data);
	input[31:0] addr;
	output[15:0] data;

	reg [15:0] mem[0:1023];

	assign data = mem[addr[10:1]];

endmodule
module pmem(addr, data);

	input[31:0] addr;
	output[15:0] data;

	reg [15:0] mem[0:1023];

	assign data = mem[addr[10:1]];

endmodule