data/full_repos/permissive/52682338/Testbench/testbench_1.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/52682338/Testbench/testbench_1.v:141: Unsupported: Ignoring delay on this delayed statement.\n  #30         \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/52682338/Testbench/testbench_1.v:143: Unsupported: Ignoring delay on this delayed statement.\n  #1000\n  ^\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/Testbench/testbench_1.v:124: Signal definition not found, creating implicitly: \'M68K_RW\'\n assign M68K_DATA = (M68K_RW & ~nCRDC) ? CDD : 16\'bzzzzzzzzzzzzzzzz;\n                     ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/Testbench/testbench_1.v:124: Signal definition not found, creating implicitly: \'nCRDC\'\n assign M68K_DATA = (M68K_RW & ~nCRDC) ? CDD : 16\'bzzzzzzzzzzzzzzzz;\n                                ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/Testbench/testbench_1.v:147: Signal definition not found, creating implicitly: \'nLDS\'\n assign DEBUG_ADDR = (~|{nLDS, nUDS}) ? {M68K_ADDR, 1\'b0} :\n                         ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/Testbench/testbench_1.v:147: Signal definition not found, creating implicitly: \'nUDS\'\n                                                                                  : ... Suggested alternative: \'nLDS\'\n assign DEBUG_ADDR = (~|{nLDS, nUDS}) ? {M68K_ADDR, 1\'b0} :\n                               ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/Testbench/testbench_1.v:151: Signal definition not found, creating implicitly: \'nAS\'\n always @(negedge nAS)\n                  ^~~\n%Error: data/full_repos/permissive/52682338/Testbench/testbench_1.v:66: Cannot find file containing module: \'neogeo\'\n neogeo NG(\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52682338/Testbench,data/full_repos/permissive/52682338/neogeo\n             data/full_repos/permissive/52682338/Testbench,data/full_repos/permissive/52682338/neogeo.v\n             data/full_repos/permissive/52682338/Testbench,data/full_repos/permissive/52682338/neogeo.sv\n             neogeo\n             neogeo.v\n             neogeo.sv\n             obj_dir/neogeo\n             obj_dir/neogeo.v\n             obj_dir/neogeo.sv\n%Error: data/full_repos/permissive/52682338/Testbench/testbench_1.v:112: Cannot find file containing module: \'mvs_cart\'\n mvs_cart MVSCART(nRESET, CLK_24M, CLK_12M, CLK_8M, CLK_68KCLKB, CLK_4MB, nAS, M68K_RW, M68K_ADDR[19:1], M68K_DATA,\n ^~~~~~~~\n%Error: data/full_repos/permissive/52682338/Testbench/testbench_1.v:123: Cannot find file containing module: \'memcard\'\n memcard MC({CDA_U, M68K_ADDR[19:1]}, CDD, nCRDC, nCRDO, CARD_PIN_nWE, CARD_PIN_nREG, nCD1, nCD2, nWP);\n ^~~~~~~\n%Error: data/full_repos/permissive/52682338/Testbench/testbench_1.v:129: Cannot find file containing module: \'neo_zmc2\'\n neo_zmc2 ZMC2(CLK_12M, EVEN, LOAD, H, CR, GAD, GBD, , );\n ^~~~~~~~\n%Error: Exiting due to 4 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench_1();
	reg nRESET_BTN;
	reg [9:0] P1_IN;
	reg [9:0] P2_IN;
	reg nTEST_BTN;
	reg [7:0] DIPSW;
	
	wire [15:0] M68K_DATA;
	wire [23:1] M68K_ADDR;
	
	wire [2:0] LED_LATCH;
	wire [7:0] LED_DATA;
	
	wire [23:0] PBUS;
	
	wire [7:0] FIXD_CART;

	wire [2:0] P1_OUT;
	wire [2:0] P2_OUT;
	
	wire [4:0] CDA_U;
	wire [15:0] CDD;

	wire [3:0] EL_OUT;

	wire [7:0] SDRAD;
	wire [9:8] SDRA_L;
	wire [23:20] SDRA_U;
	wire [7:0] SDPAD;
	wire [11:8] SDPA;

	wire [15:0] SDA;
	wire [7:0] SDD;
	
	wire [31:0] CR;
	wire [3:0] GAD, GBD;
	
	wire [6:0] VIDEO_R;
	wire [6:0] VIDEO_G;
	wire [6:0] VIDEO_B;
	
	wire [23:0] DEBUG_ADDR;

	neogeo NG(
		nRESET_BTN,
		
		P1_IN, P2_IN,
		
		DIPSW,
		
		M68K_DATA, M68K_ADDR,
		M68K_RW,	nAS, nLDS, nUDS,
		LED_LATCH, LED_DATA,
		
		CLK_68KCLKB,
		CLK_8M,
		CLK_4MB,

		nROMOE, nSLOTCS,
		nROMWAIT, nPWAIT0, nPWAIT1, PDTACK,
		nPORTOEL, nPORTOEU, nPORTWEL, nPORTWEU,
		nPORTADRS,
		
		SDRAD, SDRA_L, SDRA_U, SDRMPX, nSDROE,
		SDPAD, SDPA, SDPMPX, nSDPOE,
		nSDROM, nSDMRD,
		SDA, SDD,
		
		PBUS,
		nVCS,
		S2H1, CA4,
		PCK1B, PCK2B,
		
		CLK_12M, EVEN, LOAD, H,
		GAD, GBD,
		FIXD_CART,
		
		CDA_U,
		nCRDC, nCRDO,
		CARD_PIN_nWE, CARD_PIN_nREG,
		nCD1, nCD2, nWP,

		VIDEO_R,
		VIDEO_G,
		VIDEO_B,
		VIDEO_SYNC
	);
	

	mvs_cart MVSCART(nRESET, CLK_24M, CLK_12M, CLK_8M, CLK_68KCLKB, CLK_4MB, nAS, M68K_RW, M68K_ADDR[19:1], M68K_DATA,
					nROMOE, nROMOEL, nROMOEU, nPORTADRS, nPORTOEL, nPORTOEU,	nPORTWEL, nPORTWEU, nROMWAIT, nPWAIT0, nPWAIT1,
					PDTACK, nSLOTCS, PBUS, CA4, S2H1, PCK1B, PCK2B, CR, FIXD_CART, SDRAD, SDRA_L, SDRA_U, SDRMPX, nSDROE,
					SDPAD, SDPA, SDPMPX, nSDPOE, SDRD0, SDRD1, nSDROM, nSDMRD, SDA, SDD);
	




	memcard MC({CDA_U, M68K_ADDR[19:1]}, CDD, nCRDC, nCRDO, CARD_PIN_nWE, CARD_PIN_nREG, nCD1, nCD2, nWP);
	assign M68K_DATA = (M68K_RW & ~nCRDC) ? CDD : 16'bzzzzzzzzzzzzzzzz;
	assign CDD = (~M68K_RW | nCRDC) ? 16'bzzzzzzzzzzzzzzzz : M68K_DATA;
	


	neo_zmc2 ZMC2(CLK_12M, EVEN, LOAD, H, CR, GAD, GBD, , );
	
	
	initial
	begin
		nRESET_BTN = 1;
		P1_IN = 10'b1111111111;
		P2_IN = 10'b1111111111;
		
		nTEST_BTN = 1;
		DIPSW = 8'b11111111;
		
		#30
		nRESET_BTN = 0;
		#1000
		nRESET_BTN = 1;
	end
	
	assign DEBUG_ADDR = (~|{nLDS, nUDS}) ? {M68K_ADDR, 1'b0} :
									(~nLDS) ? {M68K_ADDR, 1'b1} :
									{M68K_ADDR, 1'b0};

	always @(negedge nAS)
	begin
		if (DEBUG_ADDR == 24'hC18F74)
		begin
			$display("Going to BIOS menu !");
			$stop;
		end
		
		if (DEBUG_ADDR == 24'hC11002) $display("Reset procedure !");
		if (DEBUG_ADDR == 24'hC11046) $display("Clearing WRAM...");
		if (DEBUG_ADDR == 24'hC11080) $display("Clearing Palettes...");
		if (DEBUG_ADDR == 24'hC11B04) $display("WRAM check passed");
		if (DEBUG_ADDR == 24'hC11B16) $display("BRAM check passed");
		if (DEBUG_ADDR == 24'hC11B2C) $display("PAL BANK 1 check passed");
		if (DEBUG_ADDR == 24'hC11B3E) $display("PAL BANK 0 check passed");
		if (DEBUG_ADDR == 24'hC11B5C) $display("VRAM LOW check passed");
		if (DEBUG_ADDR == 24'hC11B6A) $display("VRAM FAST check passed");
		if (DEBUG_ADDR == 24'hC11BD6) $display("Testing RTC...");
		if (DEBUG_ADDR == 24'hC11C66) $display("BIOS CRC check passed");
		if (DEBUG_ADDR == 24'hC11F76) $display("Cart detected OK");
		if (DEBUG_ADDR == 24'hC125E6) $display("Formatting BRAM...");
		if (DEBUG_ADDR == 24'hC1835E) $display("Call: FIX_CLEAR");
		if (DEBUG_ADDR == 24'hC1839A) $display("Call: LSP_1ST");
	
		if (DEBUG_ADDR == 24'hC16ADA)
		begin

			$display("Self-test fail ! Check 68K D6 for error code.");
			$stop;
		end
		
		if (DEBUG_ADDR == 24'hC12038)
		begin



		end
		
		if (DEBUG_ADDR == 24'hC11D46)
		begin
			$display("SYSTEM ROM ERROR !");
			$stop;
		end
		
		if (DEBUG_ADDR == 24'hC11D8C)
		begin
			$display("CALENDAR ERROR ! (B)");
			$stop;
		end
		
		if (DEBUG_ADDR == 24'hC17E26) $display("Going to eye-catcher !");
		if (DEBUG_ADDR == 24'h000122) $display("Jump to game entry point !");
	end
	
endmodule
module testbench_1();

	reg nRESET_BTN;
	reg [9:0] P1_IN;
	reg [9:0] P2_IN;
	reg nTEST_BTN;
	reg [7:0] DIPSW;
	
	wire [15:0] M68K_DATA;
	wire [23:1] M68K_ADDR;
	
	wire [2:0] LED_LATCH;
	wire [7:0] LED_DATA;
	
	wire [23:0] PBUS;
	
	wire [7:0] FIXD_CART;

	wire [2:0] P1_OUT;
	wire [2:0] P2_OUT;
	
	wire [4:0] CDA_U;
	wire [15:0] CDD;

	wire [3:0] EL_OUT;

	wire [7:0] SDRAD;
	wire [9:8] SDRA_L;
	wire [23:20] SDRA_U;
	wire [7:0] SDPAD;
	wire [11:8] SDPA;

	wire [15:0] SDA;
	wire [7:0] SDD;
	
	wire [31:0] CR;
	wire [3:0] GAD, GBD;
	
	wire [6:0] VIDEO_R;
	wire [6:0] VIDEO_G;
	wire [6:0] VIDEO_B;
	
	wire [23:0] DEBUG_ADDR;

	neogeo NG(
		nRESET_BTN,
		
		P1_IN, P2_IN,
		
		DIPSW,
		
		M68K_DATA, M68K_ADDR,
		M68K_RW,	nAS, nLDS, nUDS,
		LED_LATCH, LED_DATA,
		
		CLK_68KCLKB,
		CLK_8M,
		CLK_4MB,

		nROMOE, nSLOTCS,
		nROMWAIT, nPWAIT0, nPWAIT1, PDTACK,
		nPORTOEL, nPORTOEU, nPORTWEL, nPORTWEU,
		nPORTADRS,
		
		SDRAD, SDRA_L, SDRA_U, SDRMPX, nSDROE,
		SDPAD, SDPA, SDPMPX, nSDPOE,
		nSDROM, nSDMRD,
		SDA, SDD,
		
		PBUS,
		nVCS,
		S2H1, CA4,
		PCK1B, PCK2B,
		
		CLK_12M, EVEN, LOAD, H,
		GAD, GBD,
		FIXD_CART,
		
		CDA_U,
		nCRDC, nCRDO,
		CARD_PIN_nWE, CARD_PIN_nREG,
		nCD1, nCD2, nWP,

		VIDEO_R,
		VIDEO_G,
		VIDEO_B,
		VIDEO_SYNC
	);
	

	mvs_cart MVSCART(nRESET, CLK_24M, CLK_12M, CLK_8M, CLK_68KCLKB, CLK_4MB, nAS, M68K_RW, M68K_ADDR[19:1], M68K_DATA,
					nROMOE, nROMOEL, nROMOEU, nPORTADRS, nPORTOEL, nPORTOEU,	nPORTWEL, nPORTWEU, nROMWAIT, nPWAIT0, nPWAIT1,
					PDTACK, nSLOTCS, PBUS, CA4, S2H1, PCK1B, PCK2B, CR, FIXD_CART, SDRAD, SDRA_L, SDRA_U, SDRMPX, nSDROE,
					SDPAD, SDPA, SDPMPX, nSDPOE, SDRD0, SDRD1, nSDROM, nSDMRD, SDA, SDD);
	




	memcard MC({CDA_U, M68K_ADDR[19:1]}, CDD, nCRDC, nCRDO, CARD_PIN_nWE, CARD_PIN_nREG, nCD1, nCD2, nWP);
	assign M68K_DATA = (M68K_RW & ~nCRDC) ? CDD : 16'bzzzzzzzzzzzzzzzz;
	assign CDD = (~M68K_RW | nCRDC) ? 16'bzzzzzzzzzzzzzzzz : M68K_DATA;
	


	neo_zmc2 ZMC2(CLK_12M, EVEN, LOAD, H, CR, GAD, GBD, , );
	
	
	initial
	begin
		nRESET_BTN = 1;
		P1_IN = 10'b1111111111;
		P2_IN = 10'b1111111111;
		
		nTEST_BTN = 1;
		DIPSW = 8'b11111111;
		
		#30
		nRESET_BTN = 0;
		#1000
		nRESET_BTN = 1;
	end
	
	assign DEBUG_ADDR = (~|{nLDS, nUDS}) ? {M68K_ADDR, 1'b0} :
									(~nLDS) ? {M68K_ADDR, 1'b1} :
									{M68K_ADDR, 1'b0};

	always @(negedge nAS)
	begin
		if (DEBUG_ADDR == 24'hC18F74)
		begin
			$display("Going to BIOS menu !");
			$stop;
		end
		
		if (DEBUG_ADDR == 24'hC11002) $display("Reset procedure !");
		if (DEBUG_ADDR == 24'hC11046) $display("Clearing WRAM...");
		if (DEBUG_ADDR == 24'hC11080) $display("Clearing Palettes...");
		if (DEBUG_ADDR == 24'hC11B04) $display("WRAM check passed");
		if (DEBUG_ADDR == 24'hC11B16) $display("BRAM check passed");
		if (DEBUG_ADDR == 24'hC11B2C) $display("PAL BANK 1 check passed");
		if (DEBUG_ADDR == 24'hC11B3E) $display("PAL BANK 0 check passed");
		if (DEBUG_ADDR == 24'hC11B5C) $display("VRAM LOW check passed");
		if (DEBUG_ADDR == 24'hC11B6A) $display("VRAM FAST check passed");
		if (DEBUG_ADDR == 24'hC11BD6) $display("Testing RTC...");
		if (DEBUG_ADDR == 24'hC11C66) $display("BIOS CRC check passed");
		if (DEBUG_ADDR == 24'hC11F76) $display("Cart detected OK");
		if (DEBUG_ADDR == 24'hC125E6) $display("Formatting BRAM...");
		if (DEBUG_ADDR == 24'hC1835E) $display("Call: FIX_CLEAR");
		if (DEBUG_ADDR == 24'hC1839A) $display("Call: LSP_1ST");
	
		if (DEBUG_ADDR == 24'hC16ADA)
		begin

			$display("Self-test fail ! Check 68K D6 for error code.");
			$stop;
		end
		
		if (DEBUG_ADDR == 24'hC12038)
		begin



		end
		
		if (DEBUG_ADDR == 24'hC11D46)
		begin
			$display("SYSTEM ROM ERROR !");
			$stop;
		end
		
		if (DEBUG_ADDR == 24'hC11D8C)
		begin
			$display("CALENDAR ERROR ! (B)");
			$stop;
		end
		
		if (DEBUG_ADDR == 24'hC17E26) $display("Going to eye-catcher !");
		if (DEBUG_ADDR == 24'h000122) $display("Jump to game entry point !");
	end
	
endmodule