data/full_repos/permissive/447976230/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v
1: b"%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v:61: Cannot find file containing module: 'synchronizer'\n   synchronizer #(.INITIAL_VAL(1'b1)) clear_sync_phyclk_i (\n   ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma,data/full_repos/permissive/447976230/synchronizer\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma,data/full_repos/permissive/447976230/synchronizer.v\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma,data/full_repos/permissive/447976230/synchronizer.sv\n             synchronizer\n             synchronizer.v\n             synchronizer.sv\n             obj_dir/synchronizer\n             obj_dir/synchronizer.v\n             obj_dir/synchronizer.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v:63: Cannot find file containing module: 'synchronizer'\n   synchronizer #(.INITIAL_VAL(1'b1)) clear_sync_sysclk_i (\n   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v:88: Cannot find file containing module: 'fifo_short_2clk'\n   fifo_short_2clk status_counters_2clk_i (\n   ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v:158: Cannot find file containing module: 'axi64_4k_2clk_fifo'\n   axi64_4k_2clk_fifo ingress_fifo_i (\n   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v:168: Cannot find file containing module: 'axi_fifo_flop2'\n   axi_fifo_flop2 #(.WIDTH(64)) input_pipe_i0 (\n   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v:182: Cannot find file containing module: 'axi_strip_preamble'\n   axi_strip_preamble #(.WIDTH(64), .MAX_PKT_SIZE(MAX_PACKET_SIZE)) axi_strip_preamble_i (\n   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v:189: Cannot find file containing module: 'axi_fifo_flop2'\n  axi_fifo_flop2 #(.WIDTH(65)) input_pipe_i1 (\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v:216: Cannot find file containing module: 'axi_fifo_flop2'\n   axi_fifo_flop2 #(.WIDTH(65)) output_pipe_i0 (\n   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v:224: Cannot find file containing module: 'axi_add_preamble'\n   axi_add_preamble #(.WIDTH(64)) axi_add_preamble_i (\n   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v:231: Cannot find file containing module: 'axi_fifo_flop2'\n   axi_fifo_flop2 #(.WIDTH(64)) output_pipe_i1 (\n   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/aurora_axis_mac.v:244: Cannot find file containing module: 'axi64_4k_2clk_fifo'\n   axi64_4k_2clk_fifo egress_fifo_i (\n   ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 11 error(s)\n"
module aurora_axis_mac #(
   parameter PHY_ENDIANNESS   = "LITTLE",
      assign phy_s_axis_tdata_endian = {
         phy_s_axis_tdata[7:0], phy_s_axis_tdata[15:8], phy_s_axis_tdata[23:16], phy_s_axis_tdata[31:24],
         phy_s_axis_tdata[39:32], phy_s_axis_tdata[47:40], phy_s_axis_tdata[55:48], phy_s_axis_tdata[63:56]
      };
      assign phy_m_axis_tdata = {
         phy_m_axis_tdata_endian[7:0], phy_m_axis_tdata_endian[15:8], phy_m_axis_tdata_endian[23:16], phy_m_axis_tdata_endian[31:24],
         phy_m_axis_tdata_endian[39:32], phy_m_axis_tdata_endian[47:40], phy_m_axis_tdata_endian[55:48], phy_m_axis_tdata_endian[63:56]
      };
   end else begin
      assign phy_s_axis_tdata_endian = phy_s_axis_tdata;
      assign phy_m_axis_tdata = phy_m_axis_tdata_endian;
   end endgenerate


   axi64_4k_2clk_fifo ingress_fifo_i (
      .s_aresetn(~phy_rst), .s_aclk(phy_clk),
      .s_axis_tdata(phy_s_axis_tdata_endian), .s_axis_tlast(phy_s_axis_tvalid), .s_axis_tuser(4'h0),
      .s_axis_tvalid(phy_s_axis_tvalid), .s_axis_tready(phy_s_axis_tready), .axis_wr_data_count(),
      .m_aclk(sys_clk),
      .m_axis_tdata(i_raw_tdata), .m_axis_tlast(), .m_axis_tuser(),
      .m_axis_tvalid(i_raw_tvalid), .m_axis_tready(i_raw_tready), .axis_rd_data_count()
   );


   axi_fifo_flop2 #(.WIDTH(64)) input_pipe_i0 (
      .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk),
      .i_tdata(i_raw_tdata), .i_tvalid(i_raw_tvalid), .i_tready(i_raw_tready),
      .o_tdata(i_pip_tdata), .o_tvalid(i_pip_tvalid),
      .o_tready(bist_checker_en_reg ? bist_i_tready : (bist_loopback_en_reg ? loopback_tready : i_pip_tready)),
      .space(), .occupied()
   );

   assign bist_i_tdata     = i_pip_tdata;
   assign bist_i_tvalid    = i_pip_tvalid & bist_checker_en_reg;

   assign loopback_tdata   = i_pip_tdata;
   assign loopback_tvalid  = i_pip_tvalid & bist_loopback_en_reg;
   
   axi_strip_preamble #(.WIDTH(64), .MAX_PKT_SIZE(MAX_PACKET_SIZE)) axi_strip_preamble_i (
      .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk),
      .i_tdata(i_pip_tdata), .i_tvalid(i_pip_tvalid & ~bist_checker_en_reg & ~bist_loopback_en_reg), .i_tready(i_pip_tready),
      .o_tdata(i_gt_tdata), .o_tlast(i_gt_tlast), .o_tvalid(i_gt_tvalid), .o_tready(i_gt_tready),
      .crc_err(checksum_err), .pkt_dropped(), .crit_error(critical_err)
   );

  axi_fifo_flop2 #(.WIDTH(65)) input_pipe_i1 (
     .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk),
     .i_tdata({i_gt_tlast, i_gt_tdata}), .i_tvalid(i_gt_tvalid), .i_tready(i_gt_tready),
     .o_tdata({m_axis_tlast, m_axis_tdata}), .o_tvalid(m_axis_tvalid), .o_tready(m_axis_tready),
     .space(), .occupied()
  );

   always @(posedge sys_clk)
      if (sys_rst | clear_sysclk)
         checksum_errors <= 32'd0;
      else if (checksum_err)
         checksum_errors <= checksum_errors + 32'd1;





   wire [63:0]    o_pkt_tdata;
   wire           o_pkt_tlast, o_pkt_tvalid, o_pkt_tready;

   wire [63:0]    o_pip_tdata;
   wire           o_pip_tvalid, o_pip_tready;

   wire [63:0]    o_raw_tdata;
   wire           o_raw_tvalid, o_raw_tready;


   axi_fifo_flop2 #(.WIDTH(65)) output_pipe_i0 (
      .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk),
      .i_tdata({s_axis_tlast, s_axis_tdata}), .i_tvalid(s_axis_tvalid), .i_tready(s_axis_tready),
      .o_tdata({o_pkt_tlast, o_pkt_tdata}), .o_tvalid(o_pkt_tvalid), .o_tready(o_pkt_tready),
      .space(), .occupied()
   );


   axi_add_preamble #(.WIDTH(64)) axi_add_preamble_i (
      .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk),
      .i_tdata(o_pkt_tdata), .i_tlast(o_pkt_tlast), .i_tvalid(o_pkt_tvalid), .i_tready(o_pkt_tready),
      .o_tdata(o_pip_tdata), .o_tvalid(o_pip_tvalid), .o_tready(o_pip_tready & ~bist_gen_en_reg & ~bist_loopback_en_reg)
   );


   axi_fifo_flop2 #(.WIDTH(64)) output_pipe_i1 (
      .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk),
      .i_tdata(bist_gen_en_reg ? bist_o_tdata : (bist_loopback_en_reg ? loopback_tdata : o_pip_tdata)),
      .i_tvalid(bist_gen_en_reg ? bist_o_tvalid : (bist_loopback_en_reg ? loopback_tvalid : o_pip_tvalid)),
      .i_tready(o_pip_tready),
      .o_tdata(o_raw_tdata), .o_tvalid(o_raw_tvalid), .o_tready(o_raw_tready),
      .space(), .occupied()
   );

   assign bist_o_tready    = o_pip_tready;
   assign loopback_tready  = o_pip_tready;


   axi64_4k_2clk_fifo egress_fifo_i (
      .s_aresetn(~phy_rst), .s_aclk(sys_clk),
      .s_axis_tdata(o_raw_tdata), .s_axis_tlast(o_raw_tvalid), .s_axis_tuser(4'h0),
      .s_axis_tvalid(o_raw_tvalid), .s_axis_tready(o_raw_tready), .axis_wr_data_count(),
      .m_aclk(phy_clk),
      .m_axis_tdata(phy_m_axis_tdata_endian), .m_axis_tlast(), .m_axis_tuser(),
      .m_axis_tvalid(phy_m_axis_tvalid), .m_axis_tready(phy_m_axis_tready), .axis_rd_data_count()
   );




   localparam LFSR_LEN  = 32;
   localparam LFSR_SEED = {LFSR_LEN{1'b1}};
   
   function [LFSR_LEN-1:0] compute_lfsr_next;
      input [LFSR_LEN-1:0] current;

      compute_lfsr_next = {current[30:0], current[31]^current[21]^current[1]^current[0]};
   endfunction

   function [63:0] lfsr_to_axis;
      input [LFSR_LEN-1:0] lfsr;
      lfsr_to_axis = {~lfsr, lfsr};
   endfunction

   function [LFSR_LEN-1:0] axis_to_lfsr;
      input [63:0] axis;
      axis_to_lfsr = axis[LFSR_LEN-1:0];
   endfunction

   generate if (BIST_ENABLED == 1) begin


      reg [5:0] throttle_cnt;
      always @(posedge sys_clk) begin
         if (sys_rst | clear_sysclk)
            throttle_cnt <= 6'd0;
         else if (bist_gen_en_reg)
            throttle_cnt <= throttle_cnt + 6'd1;
      end

      assign bist_o_tvalid = bist_gen_en_reg && (throttle_cnt <= bist_gen_rate_reg);


      reg [LFSR_LEN-1:0] lfsr_gen = LFSR_SEED, lfsr_check = LFSR_SEED;
      always @(posedge sys_clk) begin
         if (sys_rst | clear_sysclk | ~bist_gen_en_reg)
            lfsr_gen <= LFSR_SEED;
         else if (bist_o_tready & bist_o_tvalid)
            lfsr_gen <= compute_lfsr_next(lfsr_gen);
      end
      assign bist_o_tdata = lfsr_to_axis(lfsr_gen);


      wire [LFSR_LEN-1:0] lfsr_next = compute_lfsr_next(lfsr_check);;
      always @(posedge sys_clk) begin
         if (sys_rst | clear_sysclk | ~bist_checker_en_reg) begin
            bist_checker_locked <= 1'b0;
            lfsr_check <= LFSR_SEED;
         end else if (bist_i_tvalid && bist_i_tready) begin
            lfsr_check <= axis_to_lfsr(bist_i_tdata);
            if (bist_i_tdata == lfsr_to_axis(LFSR_SEED))
               bist_checker_locked <= 1'b1;
         end
      end


      always @(posedge sys_clk) begin
         if (bist_checker_locked) begin
            if (bist_i_tvalid & bist_i_tready) begin
               bist_checker_samps <= bist_checker_samps + 48'd1;
               if (bist_i_tdata != lfsr_to_axis(lfsr_next)) begin
                  bist_checker_errors <= bist_checker_errors + 48'd1;
               end
            end
         end else begin
            bist_checker_samps  <= 48'd0;
            bist_checker_errors <= 48'd0;
         end
      end
      assign bist_i_tready = 1'b1;
   end endgenerate

endmodule
module aurora_axis_mac #(
   parameter PHY_ENDIANNESS   = "LITTLE",
      assign phy_s_axis_tdata_endian = {
         phy_s_axis_tdata[7:0], phy_s_axis_tdata[15:8], phy_s_axis_tdata[23:16], phy_s_axis_tdata[31:24],
         phy_s_axis_tdata[39:32], phy_s_axis_tdata[47:40], phy_s_axis_tdata[55:48], phy_s_axis_tdata[63:56]
      };

      assign phy_m_axis_tdata = {
         phy_m_axis_tdata_endian[7:0], phy_m_axis_tdata_endian[15:8], phy_m_axis_tdata_endian[23:16], phy_m_axis_tdata_endian[31:24],
         phy_m_axis_tdata_endian[39:32], phy_m_axis_tdata_endian[47:40], phy_m_axis_tdata_endian[55:48], phy_m_axis_tdata_endian[63:56]
      };
   end else begin
      assign phy_s_axis_tdata_endian = phy_s_axis_tdata;
      assign phy_m_axis_tdata = phy_m_axis_tdata_endian;
   end endgenerate


   axi64_4k_2clk_fifo ingress_fifo_i (
      .s_aresetn(~phy_rst), .s_aclk(phy_clk),
      .s_axis_tdata(phy_s_axis_tdata_endian), .s_axis_tlast(phy_s_axis_tvalid), .s_axis_tuser(4'h0),
      .s_axis_tvalid(phy_s_axis_tvalid), .s_axis_tready(phy_s_axis_tready), .axis_wr_data_count(),
      .m_aclk(sys_clk),
      .m_axis_tdata(i_raw_tdata), .m_axis_tlast(), .m_axis_tuser(),
      .m_axis_tvalid(i_raw_tvalid), .m_axis_tready(i_raw_tready), .axis_rd_data_count()
   );


   axi_fifo_flop2 #(.WIDTH(64)) input_pipe_i0 (
      .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk),
      .i_tdata(i_raw_tdata), .i_tvalid(i_raw_tvalid), .i_tready(i_raw_tready),
      .o_tdata(i_pip_tdata), .o_tvalid(i_pip_tvalid),
      .o_tready(bist_checker_en_reg ? bist_i_tready : (bist_loopback_en_reg ? loopback_tready : i_pip_tready)),
      .space(), .occupied()
   );

   assign bist_i_tdata     = i_pip_tdata;
   assign bist_i_tvalid    = i_pip_tvalid & bist_checker_en_reg;

   assign loopback_tdata   = i_pip_tdata;
   assign loopback_tvalid  = i_pip_tvalid & bist_loopback_en_reg;
   
   axi_strip_preamble #(.WIDTH(64), .MAX_PKT_SIZE(MAX_PACKET_SIZE)) axi_strip_preamble_i (
      .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk),
      .i_tdata(i_pip_tdata), .i_tvalid(i_pip_tvalid & ~bist_checker_en_reg & ~bist_loopback_en_reg), .i_tready(i_pip_tready),
      .o_tdata(i_gt_tdata), .o_tlast(i_gt_tlast), .o_tvalid(i_gt_tvalid), .o_tready(i_gt_tready),
      .crc_err(checksum_err), .pkt_dropped(), .crit_error(critical_err)
   );

  axi_fifo_flop2 #(.WIDTH(65)) input_pipe_i1 (
     .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk),
     .i_tdata({i_gt_tlast, i_gt_tdata}), .i_tvalid(i_gt_tvalid), .i_tready(i_gt_tready),
     .o_tdata({m_axis_tlast, m_axis_tdata}), .o_tvalid(m_axis_tvalid), .o_tready(m_axis_tready),
     .space(), .occupied()
  );

   always @(posedge sys_clk)
      if (sys_rst | clear_sysclk)
         checksum_errors <= 32'd0;
      else if (checksum_err)
         checksum_errors <= checksum_errors + 32'd1;





   wire [63:0]    o_pkt_tdata;
   wire           o_pkt_tlast, o_pkt_tvalid, o_pkt_tready;

   wire [63:0]    o_pip_tdata;
   wire           o_pip_tvalid, o_pip_tready;

   wire [63:0]    o_raw_tdata;
   wire           o_raw_tvalid, o_raw_tready;


   axi_fifo_flop2 #(.WIDTH(65)) output_pipe_i0 (
      .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk),
      .i_tdata({s_axis_tlast, s_axis_tdata}), .i_tvalid(s_axis_tvalid), .i_tready(s_axis_tready),
      .o_tdata({o_pkt_tlast, o_pkt_tdata}), .o_tvalid(o_pkt_tvalid), .o_tready(o_pkt_tready),
      .space(), .occupied()
   );


   axi_add_preamble #(.WIDTH(64)) axi_add_preamble_i (
      .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk),
      .i_tdata(o_pkt_tdata), .i_tlast(o_pkt_tlast), .i_tvalid(o_pkt_tvalid), .i_tready(o_pkt_tready),
      .o_tdata(o_pip_tdata), .o_tvalid(o_pip_tvalid), .o_tready(o_pip_tready & ~bist_gen_en_reg & ~bist_loopback_en_reg)
   );


   axi_fifo_flop2 #(.WIDTH(64)) output_pipe_i1 (
      .clk(sys_clk), .reset(sys_rst), .clear(clear_sysclk),
      .i_tdata(bist_gen_en_reg ? bist_o_tdata : (bist_loopback_en_reg ? loopback_tdata : o_pip_tdata)),
      .i_tvalid(bist_gen_en_reg ? bist_o_tvalid : (bist_loopback_en_reg ? loopback_tvalid : o_pip_tvalid)),
      .i_tready(o_pip_tready),
      .o_tdata(o_raw_tdata), .o_tvalid(o_raw_tvalid), .o_tready(o_raw_tready),
      .space(), .occupied()
   );

   assign bist_o_tready    = o_pip_tready;
   assign loopback_tready  = o_pip_tready;


   axi64_4k_2clk_fifo egress_fifo_i (
      .s_aresetn(~phy_rst), .s_aclk(sys_clk),
      .s_axis_tdata(o_raw_tdata), .s_axis_tlast(o_raw_tvalid), .s_axis_tuser(4'h0),
      .s_axis_tvalid(o_raw_tvalid), .s_axis_tready(o_raw_tready), .axis_wr_data_count(),
      .m_aclk(phy_clk),
      .m_axis_tdata(phy_m_axis_tdata_endian), .m_axis_tlast(), .m_axis_tuser(),
      .m_axis_tvalid(phy_m_axis_tvalid), .m_axis_tready(phy_m_axis_tready), .axis_rd_data_count()
   );




   localparam LFSR_LEN  = 32;
   localparam LFSR_SEED = {LFSR_LEN{1'b1}};
   
   function [LFSR_LEN-1:0] compute_lfsr_next;
      input [LFSR_LEN-1:0] current;

      compute_lfsr_next = {current[30:0], current[31]^current[21]^current[1]^current[0]};
   endfunction

   function [63:0] lfsr_to_axis;
      input [LFSR_LEN-1:0] lfsr;
      lfsr_to_axis = {~lfsr, lfsr};
   endfunction

   function [LFSR_LEN-1:0] axis_to_lfsr;
      input [63:0] axis;
      axis_to_lfsr = axis[LFSR_LEN-1:0];
   endfunction

   generate if (BIST_ENABLED == 1) begin


      reg [5:0] throttle_cnt;
      always @(posedge sys_clk) begin
         if (sys_rst | clear_sysclk)
            throttle_cnt <= 6'd0;
         else if (bist_gen_en_reg)
            throttle_cnt <= throttle_cnt + 6'd1;
      end

      assign bist_o_tvalid = bist_gen_en_reg && (throttle_cnt <= bist_gen_rate_reg);


      reg [LFSR_LEN-1:0] lfsr_gen = LFSR_SEED, lfsr_check = LFSR_SEED;
      always @(posedge sys_clk) begin
         if (sys_rst | clear_sysclk | ~bist_gen_en_reg)
            lfsr_gen <= LFSR_SEED;
         else if (bist_o_tready & bist_o_tvalid)
            lfsr_gen <= compute_lfsr_next(lfsr_gen);
      end
      assign bist_o_tdata = lfsr_to_axis(lfsr_gen);


      wire [LFSR_LEN-1:0] lfsr_next = compute_lfsr_next(lfsr_check);;
      always @(posedge sys_clk) begin
         if (sys_rst | clear_sysclk | ~bist_checker_en_reg) begin
            bist_checker_locked <= 1'b0;
            lfsr_check <= LFSR_SEED;
         end else if (bist_i_tvalid && bist_i_tready) begin
            lfsr_check <= axis_to_lfsr(bist_i_tdata);
            if (bist_i_tdata == lfsr_to_axis(LFSR_SEED))
               bist_checker_locked <= 1'b1;
         end
      end


      always @(posedge sys_clk) begin
         if (bist_checker_locked) begin
            if (bist_i_tvalid & bist_i_tready) begin
               bist_checker_samps <= bist_checker_samps + 48'd1;
               if (bist_i_tdata != lfsr_to_axis(lfsr_next)) begin
                  bist_checker_errors <= bist_checker_errors + 48'd1;
               end
            end
         end else begin
            bist_checker_samps  <= 48'd0;
            bist_checker_errors <= 48'd0;
         end
      end
      assign bist_i_tready = 1'b1;
   end endgenerate

endmodule