data/full_repos/permissive/445455582/single/RiSC16_system.v
1: b'%Error: data/full_repos/permissive/445455582/single/RiSC16_system.v:21: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/445455582/single,data/full_repos/permissive/445455582/defines.v\n             data/full_repos/permissive/445455582/single,data/full_repos/permissive/445455582/defines.v.v\n             data/full_repos/permissive/445455582/single,data/full_repos/permissive/445455582/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/445455582/single/RiSC16_system.v:22: Cannot find include file: RiSC16_memory.v\n`include "RiSC16_memory.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_system.v:23: Cannot find include file: RiSC16_registerFile.v\n`include "RiSC16_registerFile.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_system.v:24: Cannot find include file: RiSC16_alu.v\n`include "RiSC16_alu.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_system.v:25: Cannot find include file: RiSC16_control.v\n`include "RiSC16_control.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/RiSC16_system.v:98: Define or directive not defined: \'`ALU_FUNCT_LEN\'\n    wire [`ALU_FUNCT_LEN - 1 : 0] alu_funct;\n          ^~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n'
module RiSC16_system #(
    parameter WORD_LENGTH = 16,
    parameter PROGRAM_SIZE = 65536,
    parameter DATA_SIZE = 65536
) (
    clk, addr, pen, instr, rst
);
    input pen;
    input [WORD_LENGTH - 1 : 0] instr;
    input [WORD_LENGTH - 1 : 0] addr;
    input clk;
    input rst;

    reg [WORD_LENGTH - 1 : 0] PC = 0;
    reg [WORD_LENGTH - 1 : 0] PC_in = 0;
    reg [WORD_LENGTH - 1 : 0] IR = 0;
    wire [WORD_LENGTH - 1 : 0] IR_in;
    
    reg i_rst = 0;
    reg [WORD_LENGTH - 1 : 0] i_addr = 0;

    reg [2:0] rf_addr2 = 0;
    wire rf_wen;
    reg [WORD_LENGTH - 1 : 0] rf_tgt = 0 ;

    wire [WORD_LENGTH - 1 : 0] rf_src1;
    wire [WORD_LENGTH - 1 : 0] rf_src2;

    wire [WORD_LENGTH - 1 : 0] d_out;
    wire d_wen;

    reg [WORD_LENGTH - 1 : 0] alu_1 = 0;
    reg [WORD_LENGTH - 1 : 0] alu_2 = 0;
    wire alu_state;
    wire [`ALU_FUNCT_LEN - 1 : 0] alu_funct;
    wire [WORD_LENGTH - 1 : 0] alu_out;

    wire muxSrc1;
    wire muxSrc2;
    wire [1:0] muxTrgt;
    wire muxAddr2;
    wire [1:0] muxPc;

    reg [WORD_LENGTH - 1 : 0] pc_inc = 0;

    wire [2:0] op;
    wire [2:0] rf_addr1;
    wire [2:0] rf_addrT;

    assign op = IR[15:13];
    assign rf_addr1 = IR[9:7];
    assign rf_addrT = IR[12:10];

    RiSC16_control #(
        .OP_LEN(3)
    ) control (
        .op(op), 
        .state(alu_state), 
        .pen(pen), 
        .aluFunct(alu_funct), 
        .muxSrc1(muxSrc1), 
        .muxSrc2(muxSrc2),
        .d_wen(d_wen), 
        .reg_wen(rf_wen), 
        .muxTrgt(muxTrgt), 
        .muxAddr2(muxAddr2),  
        .muxPc(muxPc)
    );

    RiSC16_memory #(
        .WORD_LENGTH(16),
        .MEM_SIZE(DATA_SIZE) 
    ) data_mem (
        .dataOut(d_out), 
        .address(alu_out), 
        .dataIn(rf_src2), 
        .clk(clk), 
        .writeEn(d_wen), 
        .rst(rst) 
    );

    RiSC16_registerFile #(
        .WORD_LENGTH(16),
        .REG_ADDR_LEN(3),
        .REG_NUM(8)
    ) rf (
        .addr1(rf_addr1), 
        .src1(rf_src1), 
        .addr2(rf_addr2), 
        .src2(rf_src2), 
        .addrT(rf_addrT), 
        .trgt(rf_tgt),
        .wen(rf_wen), 
        .clk(clk), 
        .rst(rst)
    );

    RiSC16_alu #(
        .WORD_LENGTH(16)
    ) alu (
        .src1(alu_1), 
        .src2(alu_2), 
        .result(alu_out), 
        .state(alu_state), 
        .funct(alu_funct)
    );

    RiSC16_memory #(
        .WORD_LENGTH(16),
        .MEM_SIZE(PROGRAM_SIZE) 
    ) instr_mem (
        .dataOut(IR_in), 
        .address(i_addr), 
        .dataIn(instr), 
        .clk(clk), 
        .writeEn(pen), 
        .rst(i_rst) 
    );

    always @(*) begin
        i_rst = rst & pen;
        pc_inc = PC + 1;

        if(rst & pen) begin
            PC_in <= 0;
            i_addr <= addr;
        end else if(pen & ~rst) begin
            PC_in <= pc_inc;
            i_addr <= addr;
        end else if(~pen & rst) begin
            PC_in <= 0;
            i_addr <= PC;
        end else if(~pen & ~rst) begin
            if(muxAddr2)
                rf_addr2 <= IR[12:10];
            else
                rf_addr2 <= IR[2:0];
            
            if(muxSrc1)
                alu_1 <= { IR[9:0], 6'b000000};
            else
                alu_1 <= rf_src1;

            if(muxSrc2)
                alu_2 <= { {9{IR[6]}}, IR[6:0]};
            else
                alu_2 <= rf_src2;

            case (muxTrgt)
                2'b00: rf_tgt <= d_out;
                2'b01: rf_tgt <= alu_out;
                2'b10: rf_tgt <= pc_inc;
                default: rf_tgt = d_out;
            endcase

            case (muxPc)
                
                2'b00: begin
                    PC_in <= pc_inc;
                end

                2'b10: begin
                    PC_in <= pc_inc + { {9{IR[6]}}, IR[6:0]};
                end

                2'b11: begin
                    PC_in <= pc_inc + alu_out;
                end

                default: begin
                    PC_in <= pc_inc;
                end
            endcase
            i_addr <= PC;

        end
    end

    always @(negedge clk) begin
        IR <= IR_in;     
        PC <= PC_in;
        
    end
        
endmodule
module RiSC16_system #(
    parameter WORD_LENGTH = 16,
    parameter PROGRAM_SIZE = 65536,
    parameter DATA_SIZE = 65536
) (
    clk, addr, pen, instr, rst
);

    input pen;
    input [WORD_LENGTH - 1 : 0] instr;
    input [WORD_LENGTH - 1 : 0] addr;
    input clk;
    input rst;

    reg [WORD_LENGTH - 1 : 0] PC = 0;
    reg [WORD_LENGTH - 1 : 0] PC_in = 0;
    reg [WORD_LENGTH - 1 : 0] IR = 0;
    wire [WORD_LENGTH - 1 : 0] IR_in;
    
    reg i_rst = 0;
    reg [WORD_LENGTH - 1 : 0] i_addr = 0;

    reg [2:0] rf_addr2 = 0;
    wire rf_wen;
    reg [WORD_LENGTH - 1 : 0] rf_tgt = 0 ;

    wire [WORD_LENGTH - 1 : 0] rf_src1;
    wire [WORD_LENGTH - 1 : 0] rf_src2;

    wire [WORD_LENGTH - 1 : 0] d_out;
    wire d_wen;

    reg [WORD_LENGTH - 1 : 0] alu_1 = 0;
    reg [WORD_LENGTH - 1 : 0] alu_2 = 0;
    wire alu_state;
    wire [`ALU_FUNCT_LEN - 1 : 0] alu_funct;
    wire [WORD_LENGTH - 1 : 0] alu_out;

    wire muxSrc1;
    wire muxSrc2;
    wire [1:0] muxTrgt;
    wire muxAddr2;
    wire [1:0] muxPc;

    reg [WORD_LENGTH - 1 : 0] pc_inc = 0;

    wire [2:0] op;
    wire [2:0] rf_addr1;
    wire [2:0] rf_addrT;

    assign op = IR[15:13];
    assign rf_addr1 = IR[9:7];
    assign rf_addrT = IR[12:10];

    RiSC16_control #(
        .OP_LEN(3)
    ) control (
        .op(op), 
        .state(alu_state), 
        .pen(pen), 
        .aluFunct(alu_funct), 
        .muxSrc1(muxSrc1), 
        .muxSrc2(muxSrc2),
        .d_wen(d_wen), 
        .reg_wen(rf_wen), 
        .muxTrgt(muxTrgt), 
        .muxAddr2(muxAddr2),  
        .muxPc(muxPc)
    );

    RiSC16_memory #(
        .WORD_LENGTH(16),
        .MEM_SIZE(DATA_SIZE) 
    ) data_mem (
        .dataOut(d_out), 
        .address(alu_out), 
        .dataIn(rf_src2), 
        .clk(clk), 
        .writeEn(d_wen), 
        .rst(rst) 
    );

    RiSC16_registerFile #(
        .WORD_LENGTH(16),
        .REG_ADDR_LEN(3),
        .REG_NUM(8)
    ) rf (
        .addr1(rf_addr1), 
        .src1(rf_src1), 
        .addr2(rf_addr2), 
        .src2(rf_src2), 
        .addrT(rf_addrT), 
        .trgt(rf_tgt),
        .wen(rf_wen), 
        .clk(clk), 
        .rst(rst)
    );

    RiSC16_alu #(
        .WORD_LENGTH(16)
    ) alu (
        .src1(alu_1), 
        .src2(alu_2), 
        .result(alu_out), 
        .state(alu_state), 
        .funct(alu_funct)
    );

    RiSC16_memory #(
        .WORD_LENGTH(16),
        .MEM_SIZE(PROGRAM_SIZE) 
    ) instr_mem (
        .dataOut(IR_in), 
        .address(i_addr), 
        .dataIn(instr), 
        .clk(clk), 
        .writeEn(pen), 
        .rst(i_rst) 
    );

    always @(*) begin
        i_rst = rst & pen;
        pc_inc = PC + 1;

        if(rst & pen) begin
            PC_in <= 0;
            i_addr <= addr;
        end else if(pen & ~rst) begin
            PC_in <= pc_inc;
            i_addr <= addr;
        end else if(~pen & rst) begin
            PC_in <= 0;
            i_addr <= PC;
        end else if(~pen & ~rst) begin
            if(muxAddr2)
                rf_addr2 <= IR[12:10];
            else
                rf_addr2 <= IR[2:0];
            
            if(muxSrc1)
                alu_1 <= { IR[9:0], 6'b000000};
            else
                alu_1 <= rf_src1;

            if(muxSrc2)
                alu_2 <= { {9{IR[6]}}, IR[6:0]};
            else
                alu_2 <= rf_src2;

            case (muxTrgt)
                2'b00: rf_tgt <= d_out;
                2'b01: rf_tgt <= alu_out;
                2'b10: rf_tgt <= pc_inc;
                default: rf_tgt = d_out;
            endcase

            case (muxPc)
                
                2'b00: begin
                    PC_in <= pc_inc;
                end

                2'b10: begin
                    PC_in <= pc_inc + { {9{IR[6]}}, IR[6:0]};
                end

                2'b11: begin
                    PC_in <= pc_inc + alu_out;
                end

                default: begin
                    PC_in <= pc_inc;
                end
            endcase
            i_addr <= PC;

        end
    end

    always @(negedge clk) begin
        IR <= IR_in;     
        PC <= PC_in;
        
    end
        
endmodule