data/full_repos/permissive/476411617/TopTop_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/476411617/TopTop_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n  forever #5 clk = !clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/476411617/TopTop_tb.v:294: Too many digits for 32 bit number: \'h00000000_00000001_00000000_00000000_00000000\nram[0]  = \'h00000000_00000001_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/476411617/TopTop_tb.v:316: Unsupported: Ignoring delay on this delayed statement.\n#1610\n^\n%Warning-STMTDLY: data/full_repos/permissive/476411617/TopTop_tb.v:695: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Warning-STMTDLY: data/full_repos/permissive/476411617/TopTop_tb.v:697: Unsupported: Ignoring delay on this delayed statement.\n#10000\n^\n%Warning-STMTDLY: data/full_repos/permissive/476411617/TopTop_tb.v:706: Unsupported: Ignoring delay on this delayed statement.\n#1000\n^\n%Warning-STMTDLY: data/full_repos/permissive/476411617/TopTop_tb.v:699: Unsupported: Ignoring delay on this delayed statement.\n#2000\n^\n%Warning-STMTDLY: data/full_repos/permissive/476411617/TopTop_tb.v:722: Unsupported: Ignoring delay on this delayed statement.\n#100 start = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/476411617/TopTop_tb.v:723: Unsupported: Ignoring delay on this delayed statement.\n#1000\n^\n%Warning-STMTDLY: data/full_repos/permissive/476411617/TopTop_tb.v:726: Unsupported: Ignoring delay on this delayed statement.\n#100 start = 0;\n^\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TopTop_tb;


parameter[15:0] SIZE = 16'h0101;
parameter MAX_WORD_LENGTH = 32;
parameter Slice_Size = 16;
parameter PE_W = 1;
parameter PE_H = 1;

reg clk, reset, start;
reg[31:0] instruction;




reg external;
reg[7:0] Tile_i = 8'b0;
reg[7:0] Tile_j = 8'b0;
reg[7:0] BRAM_i = 8'b0;
reg[7:0] BRAM_j = 8'b0;
reg WEA, WEB, mode;
reg[9:0] ADDRA = -1;
reg[9:0] ADDRB = 5;
reg[15:0] DINA, DINB;
wire[15:0] DOUTA, DOUTB;
reg[159:0] ram[15:0];
reg[9:0] ram_ptr = 0;
reg[1:0] Activation_Function;
reg Tanh_In;
integer i=0, j=0, k=0;




TopTop #(SIZE[15:8], SIZE[7:0], MAX_WORD_LENGTH, Slice_Size, PE_W, PE_H) TopTopTB(clk, reset, start, instruction, external, Tile_i, Tile_j, BRAM_i, BRAM_j, WEA, 1'b0, ADDRA, ADDRB, DINA, DINB, DOUTA, DOUTB, Activation_Function, Tanh_In);

initial begin
  clk = 1;
  forever #5 clk = !clk;
end

always @ (posedge clk) begin



           


    if(Tile_i == 0 && Tile_j == 0 && BRAM_i == 0 && BRAM_j == 0) begin
        if(!reset) begin
            WEA = 1;
            for(k=15; k>=0; k=k-1) begin  
                DINA[k] = ram[k][ram_ptr];
            end
           
            ADDRA = ADDRA + 1;
            ram_ptr = ram_ptr + 1;
        end 
        else DINA = 0;
    end 

	
	
end
initial
 
begin

Tanh_In = 0;
Activation_Function = 0;






reset = 0; 
start = 0;
mode = 0;
external = 1;

ram[0]  = 'h00000000_00000001_00000000_00000000_00000000;
ram[1]  = 'h00000000_00000000_00000000_00000000_00000000;
ram[2]  = 'h00000000_00000000_00000000_00000000_00000000;
ram[3]  = 'h00000000_00000000_00000000_00000000_00000000;
ram[4]  = 'h00000000_00000000_00000000_00000000_00000000;
ram[5]  = 'h00000000_00000000_00000000_00000000_00000000;
ram[6] 	= 'h00000000_00000000_00000000_00000000_00000000;
ram[7] 	= 'h00000000_00000000_00000000_00000000_00000000;
ram[8] 	= 'h00000000_00000000_00000000_00000000_00000000;
ram[9] 	= 'h00000000_00000000_00000000_00000000_00000000;
ram[10]	= 'h00000000_00000000_00000000_00000000_00000000;
ram[11]	= 'h00000000_00000000_00000000_00000000_00000000;
ram[12]	= 'h00000000_00000000_00000000_00000000_00000000;
ram[13]	= 'h00000000_00000000_00000000_00000000_00000000;
ram[14]	= 'h00000000_00000000_00000000_00000000_00000000;
ram[15]	= 'h00000000_00000000_00000000_00000000_00000000;
BRAM_i = 8'b0;
BRAM_j = 8'b0;
Tile_i = 8'b0;
Tile_j = 8'b0;
ADDRA = -1;
ram_ptr = 0;
#1610




DINA = 0;
#10
external = 0;
#10000
reset = 1;
#2000






#1000

Activation_Function = 2'b0;
Tanh_In = 0;










instruction = (5<<26) + (3<<21) + (3<<16) + (0<<11);
start = 1;
#100 start = 0;
#1000
instruction = (7<<26) + (3<<21) + (3<<16) + (0<<11);
start = 1;
#100 start = 0;






















































































end

endmodule
module TopTop_tb;



parameter[15:0] SIZE = 16'h0101;
parameter MAX_WORD_LENGTH = 32;
parameter Slice_Size = 16;
parameter PE_W = 1;
parameter PE_H = 1;

reg clk, reset, start;
reg[31:0] instruction;




reg external;
reg[7:0] Tile_i = 8'b0;
reg[7:0] Tile_j = 8'b0;
reg[7:0] BRAM_i = 8'b0;
reg[7:0] BRAM_j = 8'b0;
reg WEA, WEB, mode;
reg[9:0] ADDRA = -1;
reg[9:0] ADDRB = 5;
reg[15:0] DINA, DINB;
wire[15:0] DOUTA, DOUTB;
reg[159:0] ram[15:0];
reg[9:0] ram_ptr = 0;
reg[1:0] Activation_Function;
reg Tanh_In;
integer i=0, j=0, k=0;




TopTop #(SIZE[15:8], SIZE[7:0], MAX_WORD_LENGTH, Slice_Size, PE_W, PE_H) TopTopTB(clk, reset, start, instruction, external, Tile_i, Tile_j, BRAM_i, BRAM_j, WEA, 1'b0, ADDRA, ADDRB, DINA, DINB, DOUTA, DOUTB, Activation_Function, Tanh_In);

initial begin
  clk = 1;
  forever #5 clk = !clk;
end

always @ (posedge clk) begin



           


    if(Tile_i == 0 && Tile_j == 0 && BRAM_i == 0 && BRAM_j == 0) begin
        if(!reset) begin
            WEA = 1;
            for(k=15; k>=0; k=k-1) begin  
                DINA[k] = ram[k][ram_ptr];
            end
           
            ADDRA = ADDRA + 1;
            ram_ptr = ram_ptr + 1;
        end 
        else DINA = 0;
    end 

	
	
end
initial
 
begin

Tanh_In = 0;
Activation_Function = 0;






reset = 0; 
start = 0;
mode = 0;
external = 1;

ram[0]  = 'h00000000_00000001_00000000_00000000_00000000;
ram[1]  = 'h00000000_00000000_00000000_00000000_00000000;
ram[2]  = 'h00000000_00000000_00000000_00000000_00000000;
ram[3]  = 'h00000000_00000000_00000000_00000000_00000000;
ram[4]  = 'h00000000_00000000_00000000_00000000_00000000;
ram[5]  = 'h00000000_00000000_00000000_00000000_00000000;
ram[6] 	= 'h00000000_00000000_00000000_00000000_00000000;
ram[7] 	= 'h00000000_00000000_00000000_00000000_00000000;
ram[8] 	= 'h00000000_00000000_00000000_00000000_00000000;
ram[9] 	= 'h00000000_00000000_00000000_00000000_00000000;
ram[10]	= 'h00000000_00000000_00000000_00000000_00000000;
ram[11]	= 'h00000000_00000000_00000000_00000000_00000000;
ram[12]	= 'h00000000_00000000_00000000_00000000_00000000;
ram[13]	= 'h00000000_00000000_00000000_00000000_00000000;
ram[14]	= 'h00000000_00000000_00000000_00000000_00000000;
ram[15]	= 'h00000000_00000000_00000000_00000000_00000000;
BRAM_i = 8'b0;
BRAM_j = 8'b0;
Tile_i = 8'b0;
Tile_j = 8'b0;
ADDRA = -1;
ram_ptr = 0;
#1610




DINA = 0;
#10
external = 0;
#10000
reset = 1;
#2000






#1000

Activation_Function = 2'b0;
Tanh_In = 0;










instruction = (5<<26) + (3<<21) + (3<<16) + (0<<11);
start = 1;
#100 start = 0;
#1000
instruction = (7<<26) + (3<<21) + (3<<16) + (0<<11);
start = 1;
#100 start = 0;






















































































end

endmodule