data/full_repos/permissive/46343463/src/Latch_TestBench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/46343463/src/Latch_TestBench.v:9: Unsupported: Ignoring delay on this delayed statement.\n always #(10/2) clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/46343463/src/Latch_TestBench.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #(10/4)\n  ^\n%Error: data/full_repos/permissive/46343463/src/Latch_TestBench.v:24: Unsupported: fork statements\n  fork   \n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/46343463/src/Latch_TestBench.v:25: Unsupported: Ignoring delay on this delayed statement.\n      #0 in   = 42;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/46343463/src/Latch_TestBench.v:29: Unsupported: Ignoring delay on this delayed statement.\n      #10 en   = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/46343463/src/Latch_TestBench.v:30: Unsupported: Ignoring delay on this delayed statement.\n      #20 en    = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/46343463/src/Latch_TestBench.v:31: Unsupported: Ignoring delay on this delayed statement.\n      #30 in    = 7;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/46343463/src/Latch_TestBench.v:32: Unsupported: Ignoring delay on this delayed statement.\n      #40 en    = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/46343463/src/Latch_TestBench.v:33: Unsupported: Ignoring delay on this delayed statement.\n   #50 en    = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/46343463/src/Latch_TestBench.v:34: Unsupported: Ignoring delay on this delayed statement.\n   #60 rst   = 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/46343463/src/Latch_TestBench.v:35: Unsupported: Ignoring delay on this delayed statement.\n      #70 rst   = 0;\n      ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Latch_TestBench;

	reg		[7:0]		in;
	reg					clk, rst, en;
	wire 	[7:0]		out;
	
	always #(`CYCLE_TIME/2) clk = ~clk;

	Latch #(.width(8)) d_ff (
		.clk		(clk),
		.rst		(rst),
		.en			(en),
		.data_i		(in),
		.data_o		(out)
	);

	initial begin		
		#(`CYCLE_TIME/4)

		clk = 0;

		fork   
	    	#0	in	  = 42;
				rst   = 0;
	    	    en    = 0;
	        
	    	#10 en	  = 1;
	    	#20 en    = 0;
	    	#30 in    = 7;
	    	#40 en    = 1;
			#50 en 	  = 0;
			#60 rst   = 1;
		    #70 rst	  = 0;
		join
	end

endmodule
module Latch_TestBench;


	reg		[7:0]		in;
	reg					clk, rst, en;
	wire 	[7:0]		out;
	
	always #(`CYCLE_TIME/2) clk = ~clk;

	Latch #(.width(8)) d_ff (
		.clk		(clk),
		.rst		(rst),
		.en			(en),
		.data_i		(in),
		.data_o		(out)
	);

	initial begin		
		#(`CYCLE_TIME/4)

		clk = 0;

		fork   
	    	#0	in	  = 42;
				rst   = 0;
	    	    en    = 0;
	        
	    	#10 en	  = 1;
	    	#20 en    = 0;
	    	#30 in    = 7;
	    	#40 en    = 1;
			#50 en 	  = 0;
			#60 rst   = 1;
		    #70 rst	  = 0;
		join
	end

endmodule