data/full_repos/permissive/515477729/source/booth_rad_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/515477729/source/booth_rad_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/515477729/source/booth_rad_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/515477729/source/booth_rad_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/515477729/source/booth_rad_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/515477729/source/booth_rad_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n%Error: data/full_repos/permissive/515477729/source/booth_rad_tb.v:42: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile ("booth_rad.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/515477729/source/booth_rad_tb.v:43: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars (0, booth_rad_tb);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/515477729/source/booth_rad_tb.v:44: Unsupported or unknown PLI call: $monitor\n        $monitor(done);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/515477729/source/booth_rad_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #5 clk = ~clk;\n    ^\n%Error: Exiting due to 3 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module booth_rad_tb;


    reg clk;
    reg [15:0] data_in;
    reg start;


    wire done;

    booth_rad uut (
        .done(done),
        .clk(clk),
        .data_in(data_in),
        .start(start)
    );

    initial begin
        clk = 0;
        start = 0;
        data_in = 16'b0;

        #100

        #10
        start = 1; 
        
        #10
        data_in = 16'b1111111111110110;

        #10
        data_in = 16'b0000000000001101;

        #100
        $finish;

    
    
    end

    initial begin
        $dumpfile ("booth_rad.vcd");
        $dumpvars (0, booth_rad_tb);
        $monitor(done);
    end

    always begin
    
    #5 clk = ~clk;
    
    end

endmodule
module booth_rad_tb;



    reg clk;
    reg [15:0] data_in;
    reg start;


    wire done;

    booth_rad uut (
        .done(done),
        .clk(clk),
        .data_in(data_in),
        .start(start)
    );

    initial begin
        clk = 0;
        start = 0;
        data_in = 16'b0;

        #100

        #10
        start = 1; 
        
        #10
        data_in = 16'b1111111111110110;

        #10
        data_in = 16'b0000000000001101;

        #100
        $finish;

    
    
    end

    initial begin
        $dumpfile ("booth_rad.vcd");
        $dumpvars (0, booth_rad_tb);
        $monitor(done);
    end

    always begin
    
    #5 clk = ~clk;
    
    end

endmodule