data/full_repos/permissive/472097485/Chu04/StopWatch_06/ModMCounterWithUDFD.v
1: b'%Error: data/full_repos/permissive/472097485/Chu04/StopWatch_06/ModMCounterWithUDFD.v:6: Cannot find file containing module: \'ModMCounterWithUD\'\n ModMCounterWithUD #( M, N ) counter ( clk, reset, en, up, count );\n ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/472097485/Chu04/StopWatch_06,data/full_repos/permissive/472097485/ModMCounterWithUD\n             data/full_repos/permissive/472097485/Chu04/StopWatch_06,data/full_repos/permissive/472097485/ModMCounterWithUD.v\n             data/full_repos/permissive/472097485/Chu04/StopWatch_06,data/full_repos/permissive/472097485/ModMCounterWithUD.sv\n             ModMCounterWithUD\n             ModMCounterWithUD.v\n             ModMCounterWithUD.sv\n             obj_dir/ModMCounterWithUD\n             obj_dir/ModMCounterWithUD.v\n             obj_dir/ModMCounterWithUD.sv\n%Warning-WIDTH: data/full_repos/permissive/472097485/Chu04/StopWatch_06/ModMCounterWithUDFD.v:8: Operator EQ expects 32 or 2 bits on the LHS, but LHS\'s VARREF \'count\' generates 1 bits.\n                                                                                               : ... In instance ModMCounterWithUDFD\n assign tick = en && count == ( up ? M - 1 : 0 );\n                           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module ModMCounterWithUDFD #( parameter M = 2, parameter N = 1 )( input clk, input reset, input en, input up, output [N-1:0] count, output tick );

	ModMCounterWithUD #( M, N ) counter ( clk, reset, en, up, count );
	
	assign tick = en && count == ( up ? M - 1 : 0 );

endmodule
module ModMCounterWithUDFD #( parameter M = 2, parameter N = 1 )( input clk, input reset, input en, input up, output [N-1:0] count, output tick );


	ModMCounterWithUD #( M, N ) counter ( clk, reset, en, up, count );
	
	assign tick = en && count == ( up ? M - 1 : 0 );

endmodule