data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #2 ps2_data = 1\'b0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #1 ps2_clock = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #1 ps2_clock = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #2 ps2_data = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #1 ps2_clock = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #1 ps2_clock = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #2 ps2_data = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #1 ps2_clock = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #1 ps2_clock = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #2 ps2_data = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #1 ps2_clock = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #1 ps2_clock = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #2 ps2_data = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #1 ps2_clock = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #1 ps2_clock = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #2 ps2_data = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #1 ps2_clock = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #1 ps2_clock = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #2 ps2_data = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #1 ps2_clock = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #1 ps2_clock = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #2 ps2_data = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #1 ps2_clock = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #1 ps2_clock = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #2 ps2_data = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #1 ps2_clock = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #1 ps2_clock = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n        #2 ps2_data = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #1 ps2_clock = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n        #1 ps2_clock = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n        #2 ps2_data = 1\'b1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n        #1 ps2_clock = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n        #1 ps2_clock = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n        #1 clk = !clk;\n        ^\n%Error: data/full_repos/permissive/50724111/ps2/bench/verilog/ps2_controller_tb.v:12: Cannot find file containing module: \'ps2_controller\'\n    ps2_controller keyboard (\n    ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/50724111/ps2/bench/verilog,data/full_repos/permissive/50724111/ps2_controller\n             data/full_repos/permissive/50724111/ps2/bench/verilog,data/full_repos/permissive/50724111/ps2_controller.v\n             data/full_repos/permissive/50724111/ps2/bench/verilog,data/full_repos/permissive/50724111/ps2_controller.sv\n             ps2_controller\n             ps2_controller.v\n             ps2_controller.sv\n             obj_dir/ps2_controller\n             obj_dir/ps2_controller.v\n             obj_dir/ps2_controller.sv\n%Error: Exiting due to 1 error(s), 34 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ps2_controller_tb();


    reg clk, reset;
    reg ps2_clock, ps2_data;
    
    wire scan_ready;
    wire [7:0] scan_code;

    ps2_controller keyboard (
        .reset(reset),
        .clk(clk),
        .ps2_clock(ps2_clock),
        .ps2_data(ps2_data),
        .scan_ready(scan_ready),
        .scan_code(scan_code)
    );
    
    initial begin  
        clk = 0;
        reset = 0;
        ps2_clock = 1;
        


        #2 ps2_data = 1'b0;
        #1 ps2_clock = 0;
        #1 ps2_clock = 1;
        
        
        #2 ps2_data = 1'b0;
        #1 ps2_clock = 0;
        #1 ps2_clock = 1;
        #2 ps2_data = 1'b1;
        #1 ps2_clock = 0;
        #1 ps2_clock = 1;
        #2 ps2_data = 1'b1;
        #1 ps2_clock = 0;
        #1 ps2_clock = 1;
        #2 ps2_data = 1'b1;
        #1 ps2_clock = 0;
        #1 ps2_clock = 1;
        
        #2 ps2_data = 1'b1;
        #1 ps2_clock = 0;
        #1 ps2_clock = 1;
        #2 ps2_data = 1'b0;
        #1 ps2_clock = 0;
        #1 ps2_clock = 1;
        #2 ps2_data = 1'b0;
        #1 ps2_clock = 0;
        #1 ps2_clock = 1;
        #2 ps2_data = 1'b0;
        #1 ps2_clock = 0;
        #1 ps2_clock = 1;
        
        
        #2 ps2_data = 1'b1;
        #1 ps2_clock = 0;
        #1 ps2_clock = 1;
        
        #2 ps2_data = 1'b1;
        #1 ps2_clock = 0;
        #1 ps2_clock = 1;

    end

    always begin
        #1 clk = !clk;
    end
    
endmodule
module ps2_controller_tb();



    reg clk, reset;
    reg ps2_clock, ps2_data;
    
    wire scan_ready;
    wire [7:0] scan_code;

    ps2_controller keyboard (
        .reset(reset),
        .clk(clk),
        .ps2_clock(ps2_clock),
        .ps2_data(ps2_data),
        .scan_ready(scan_ready),
        .scan_code(scan_code)
    );
    
    initial begin  
        clk = 0;
        reset = 0;
        ps2_clock = 1;
        


        #2 ps2_data = 1'b0;
        #1 ps2_clock = 0;
        #1 ps2_clock = 1;
        
        
        #2 ps2_data = 1'b0;
        #1 ps2_clock = 0;
        #1 ps2_clock = 1;
        #2 ps2_data = 1'b1;
        #1 ps2_clock = 0;
        #1 ps2_clock = 1;
        #2 ps2_data = 1'b1;
        #1 ps2_clock = 0;
        #1 ps2_clock = 1;
        #2 ps2_data = 1'b1;
        #1 ps2_clock = 0;
        #1 ps2_clock = 1;
        
        #2 ps2_data = 1'b1;
        #1 ps2_clock = 0;
        #1 ps2_clock = 1;
        #2 ps2_data = 1'b0;
        #1 ps2_clock = 0;
        #1 ps2_clock = 1;
        #2 ps2_data = 1'b0;
        #1 ps2_clock = 0;
        #1 ps2_clock = 1;
        #2 ps2_data = 1'b0;
        #1 ps2_clock = 0;
        #1 ps2_clock = 1;
        
        
        #2 ps2_data = 1'b1;
        #1 ps2_clock = 0;
        #1 ps2_clock = 1;
        
        #2 ps2_data = 1'b1;
        #1 ps2_clock = 0;
        #1 ps2_clock = 1;

    end

    always begin
        #1 clk = !clk;
    end
    
endmodule