data/full_repos/permissive/470590146/core/exe_stage.v
1: b"%Error: data/full_repos/permissive/470590146/core/exe_stage.v:80: Cannot find file containing module: 'alu'\nalu U_alu\n^~~\n        ... Looked in:\n             data/full_repos/permissive/470590146/core,data/full_repos/permissive/470590146/alu\n             data/full_repos/permissive/470590146/core,data/full_repos/permissive/470590146/alu.v\n             data/full_repos/permissive/470590146/core,data/full_repos/permissive/470590146/alu.sv\n             alu\n             alu.v\n             alu.sv\n             obj_dir/alu\n             obj_dir/alu.v\n             obj_dir/alu.sv\n%Error: Exiting due to 1 error(s)\n"
module exe_stage (
	 input 			clk
	,input 			rst_n

    ,input  ms_ready
    ,input  ds_valid
    ,output es_valid
    ,output es_ready

    ,input  [150:0] ds2es_bus
    ,output reg [106:0] es2ms_bus
);


wire  [31:0] ds_pc;
wire  [31:0] ds_src1;
wire  [31:0] ds_src2;
wire  [31:0] ds_imm;
wire  [11:0] ds_alu_control;
wire  [ 5:0] ds_ctrl;
wire  [ 4:0] ds_rd;

wire [31:0] es_pc;
wire [31:0] es_alu_result;
wire [31:0] es_data_ram_wdata;
wire [ 4:0] es_rd;
wire [ 4:0] es_ctrl;
wire 		es_zero;

assign  {
    ds_pc         ,
    ds_src1       ,
    ds_src2       ,
    ds_imm        ,
    ds_rd         ,
    ds_alu_control,
    ds_ctrl
} = ds2es_bus;

assign es_data_ram_wdata = ds_src2;
assign es_rd   = ds_rd;

wire branch;
wire mem_read;
wire mem_write;
wire mem2reg;

wire alu_src_op;
wire reg_write;

assign alu_src_op = ds_ctrl[5];
assign branch	  = ds_ctrl[4];
assign mem_read	  = ds_ctrl[3];
assign mem_write  = ds_ctrl[2];
assign mem2reg	  = ds_ctrl[1];
assign reg_write  = ds_ctrl[0];

assign es_ctrl = ds_ctrl[4:0];


assign es_pc = ds_pc + ds_imm;


wire [31:0] alu_src2_true = alu_src_op ? ds_imm : ds_src2;

alu U_alu
	(
		.alu_control (ds_alu_control),
		.alu_src1    (ds_src1       ),
		.alu_src2    (alu_src2_true ),
		.alu_result  (es_alu_result ),
		.zero		 (es_zero       )
	);

wire [106:0] es2ms_bus_reg;
assign es2ms_bus_reg = {
    es_pc,
    es_alu_result,
    es_data_ram_wdata,
    es_rd,
    es_ctrl,
    es_zero
};

wire es_ok_go = 1'b1;
reg es_valid_pre;
assign es_ready = !ds_valid || es_ok_go && ms_ready;
assign es_valid = es_valid_pre && es_ok_go;

always @(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0) begin
        es_valid_pre <= 0;
    end
    else if (es_ready) begin
        es_valid_pre <= ds_valid;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (rst_n == 0) begin
        es2ms_bus <= 0;
    end
    else if (es_ready && ds_valid) begin
        es2ms_bus <= es2ms_bus_reg;
    end
end

endmodule
module exe_stage (
	 input 			clk
	,input 			rst_n

    ,input  ms_ready
    ,input  ds_valid
    ,output es_valid
    ,output es_ready

    ,input  [150:0] ds2es_bus
    ,output reg [106:0] es2ms_bus
);



wire  [31:0] ds_pc;
wire  [31:0] ds_src1;
wire  [31:0] ds_src2;
wire  [31:0] ds_imm;
wire  [11:0] ds_alu_control;
wire  [ 5:0] ds_ctrl;
wire  [ 4:0] ds_rd;

wire [31:0] es_pc;
wire [31:0] es_alu_result;
wire [31:0] es_data_ram_wdata;
wire [ 4:0] es_rd;
wire [ 4:0] es_ctrl;
wire 		es_zero;

assign  {
    ds_pc         ,
    ds_src1       ,
    ds_src2       ,
    ds_imm        ,
    ds_rd         ,
    ds_alu_control,
    ds_ctrl
} = ds2es_bus;

assign es_data_ram_wdata = ds_src2;
assign es_rd   = ds_rd;

wire branch;
wire mem_read;
wire mem_write;
wire mem2reg;

wire alu_src_op;
wire reg_write;

assign alu_src_op = ds_ctrl[5];
assign branch	  = ds_ctrl[4];
assign mem_read	  = ds_ctrl[3];
assign mem_write  = ds_ctrl[2];
assign mem2reg	  = ds_ctrl[1];
assign reg_write  = ds_ctrl[0];

assign es_ctrl = ds_ctrl[4:0];


assign es_pc = ds_pc + ds_imm;


wire [31:0] alu_src2_true = alu_src_op ? ds_imm : ds_src2;

alu U_alu
	(
		.alu_control (ds_alu_control),
		.alu_src1    (ds_src1       ),
		.alu_src2    (alu_src2_true ),
		.alu_result  (es_alu_result ),
		.zero		 (es_zero       )
	);

wire [106:0] es2ms_bus_reg;
assign es2ms_bus_reg = {
    es_pc,
    es_alu_result,
    es_data_ram_wdata,
    es_rd,
    es_ctrl,
    es_zero
};

wire es_ok_go = 1'b1;
reg es_valid_pre;
assign es_ready = !ds_valid || es_ok_go && ms_ready;
assign es_valid = es_valid_pre && es_ok_go;

always @(posedge clk or negedge rst_n) begin
    if (rst_n == 1'b0) begin
        es_valid_pre <= 0;
    end
    else if (es_ready) begin
        es_valid_pre <= ds_valid;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (rst_n == 0) begin
        es2ms_bus <= 0;
    end
    else if (es_ready && ds_valid) begin
        es2ms_bus <= es2ms_bus_reg;
    end
end

endmodule