data/full_repos/permissive/493847347/src/base_lut.v
1: b"%Error: data/full_repos/permissive/493847347/src/base_lut.v:44: Cannot find file containing module: 'Predecoder'\nPredecoder #(\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/493847347/src,data/full_repos/permissive/493847347/Predecoder\n             data/full_repos/permissive/493847347/src,data/full_repos/permissive/493847347/Predecoder.v\n             data/full_repos/permissive/493847347/src,data/full_repos/permissive/493847347/Predecoder.sv\n             Predecoder\n             Predecoder.v\n             Predecoder.sv\n             obj_dir/Predecoder\n             obj_dir/Predecoder.v\n             obj_dir/Predecoder.sv\n%Error: Exiting due to 1 error(s)\n"
module BaseLUT #(
    parameter INPUTS=4,
    parameter MEM_SIZE=1<<INPUTS,
    parameter FRAME_WIDTH=1
) (
    input [INPUTS-1:0] s, 
    output z,


    input config_clk,
    input config_en,
    `ifdef LATCH_EXTERNAL
    input [MEM_SIZE-1:0] config_in,
    `else
    input [FRAME_WIDTH-1:0] config_in,
    `endif
    output [FRAME_WIDTH-1:0] config_out,

    input wire reset
);




reg [MEM_SIZE-1:0] mem = 0;




Predecoder #(
  .INPUTS(INPUTS),
  .WIDTH(MEM_SIZE)
) predecode (
  .values(mem),
  .s(s),
  .z(z)
);

`ifdef LATCH_EXTERNAL
generate 
  genvar i;
  always @(config_en or config_in or reset)
    if (reset)
      mem = 0;
    else if (config_en)
      mem = config_in
endgenerate
assign config_out = mem[MEM_SIZE-1];

`elsif LATCH_INTERNAL
`else



generate 
  genvar i;
  for (i=1; i<(MEM_SIZE/FRAME_WIDTH); i=i+1) begin
    always @(posedge config_clk) begin
      if (reset) begin
        mem[i] <= 0;
      end else if (config_en) begin
        mem[(i+1)*FRAME_WIDTH-1:i*FRAME_WIDTH] <= mem[(i)*FRAME_WIDTH-1:(i-1)*FRAME_WIDTH];
      end
    end
  end
  always @(posedge config_clk) begin
    if (reset) begin
      mem[0] <= 0;
    end else if (config_en) begin
      mem[FRAME_WIDTH-1:0] <= config_in;
    end
  end
endgenerate
assign config_out = mem[MEM_SIZE-1:MEM_SIZE-FRAME_WIDTH];
`endif

endmodule
module BaseLUT #(
    parameter INPUTS=4,
    parameter MEM_SIZE=1<<INPUTS,
    parameter FRAME_WIDTH=1
) (
    input [INPUTS-1:0] s, 
    output z,


    input config_clk,
    input config_en,
    `ifdef LATCH_EXTERNAL
    input [MEM_SIZE-1:0] config_in,
    `else
    input [FRAME_WIDTH-1:0] config_in,
    `endif
    output [FRAME_WIDTH-1:0] config_out,

    input wire reset
);





reg [MEM_SIZE-1:0] mem = 0;




Predecoder #(
  .INPUTS(INPUTS),
  .WIDTH(MEM_SIZE)
) predecode (
  .values(mem),
  .s(s),
  .z(z)
);

`ifdef LATCH_EXTERNAL
generate 
  genvar i;
  always @(config_en or config_in or reset)
    if (reset)
      mem = 0;
    else if (config_en)
      mem = config_in
endgenerate
assign config_out = mem[MEM_SIZE-1];

`elsif LATCH_INTERNAL
`else



generate 
  genvar i;
  for (i=1; i<(MEM_SIZE/FRAME_WIDTH); i=i+1) begin
    always @(posedge config_clk) begin
      if (reset) begin
        mem[i] <= 0;
      end else if (config_en) begin
        mem[(i+1)*FRAME_WIDTH-1:i*FRAME_WIDTH] <= mem[(i)*FRAME_WIDTH-1:(i-1)*FRAME_WIDTH];
      end
    end
  end
  always @(posedge config_clk) begin
    if (reset) begin
      mem[0] <= 0;
    end else if (config_en) begin
      mem[FRAME_WIDTH-1:0] <= config_in;
    end
  end
endgenerate
assign config_out = mem[MEM_SIZE-1:MEM_SIZE-FRAME_WIDTH];
`endif

endmodule