data/full_repos/permissive/421030651/src/peri/uart.sv
1: b'%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:1: Cannot find include file: clkdef.h\n`include "clkdef.h" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/421030651/src/peri,data/full_repos/permissive/421030651/clkdef.h\n             data/full_repos/permissive/421030651/src/peri,data/full_repos/permissive/421030651/clkdef.h.v\n             data/full_repos/permissive/421030651/src/peri,data/full_repos/permissive/421030651/clkdef.h.sv\n             clkdef.h\n             clkdef.h.v\n             clkdef.h.sv\n             obj_dir/clkdef.h\n             obj_dir/clkdef.h.v\n             obj_dir/clkdef.h.sv\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:2: Cannot find include file: uart_define.h\n`include "uart_define.h" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:3: Cannot find include file: uart_mmap.h\n`include "uart_mmap.h" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:26: Define or directive not defined: \'`UART_DATA_WIDTH\'\nlogic [`UART_DATA_WIDTH-1:0] tx_fifo_wdata;\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:28: Define or directive not defined: \'`UART_DATA_WIDTH\'\nlogic [`UART_DATA_WIDTH-1:0] tx_fifo_rdata;\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:33: Define or directive not defined: \'`UART_DATA_WIDTH\'\nlogic [`UART_DATA_WIDTH-1:0] rx_fifo_wdata;\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:35: Define or directive not defined: \'`UART_DATA_WIDTH\'\nlogic [`UART_DATA_WIDTH-1:0] rx_fifo_rdata;\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:59: Define or directive not defined: \'`UART_TXFIFO\'\nassign tx_fifo_wr    = apb_wr && s_apb_intf.paddr[11:0] == `UART_TXFIFO && ~tx_fifo_full && ~s_apb_intf.pwdata[31];\n                                                           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:59: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\nassign tx_fifo_wr    = apb_wr && s_apb_intf.paddr[11:0] == `UART_TXFIFO && ~tx_fifo_full && ~s_apb_intf.pwdata[31];\n                                                                        ^~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:60: Define or directive not defined: \'`UART_DATA_WIDTH\'\nassign tx_fifo_wdata = s_apb_intf.pwdata[`UART_DATA_WIDTH-1:0];\n                                         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:106: Define or directive not defined: \'`UART_TXCTRL\'\n    else if (apb_wr && s_apb_intf.paddr[11:0] == `UART_TXCTRL) begin\n                                                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:106: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    else if (apb_wr && s_apb_intf.paddr[11:0] == `UART_TXCTRL) begin\n                                                             ^\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:111: syntax error, unexpected end\nend\n^~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:113: Define or directive not defined: \'`UART_RXFIFO\'\nassign rx_fifo_rd = apb_rd && s_apb_intf.paddr[11:0] == `UART_RXFIFO;\n                                                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:146: Define or directive not defined: \'`UART_RXCTRL\'\n    else if (apb_wr && s_apb_intf.paddr[11:0] == `UART_RXCTRL) begin\n                                                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:146: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    else if (apb_wr && s_apb_intf.paddr[11:0] == `UART_RXCTRL) begin\n                                                             ^\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:150: syntax error, unexpected end\nend\n^~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:158: Define or directive not defined: \'`UART_IE\'\n    else if (apb_wr && s_apb_intf.paddr[11:0] == `UART_IE) begin\n                                                 ^~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:171: Define or directive not defined: \'`UART_IC\'\n    else if (apb_wr && s_apb_intf.paddr[11:0] == `UART_IC) begin\n                                                 ^~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:190: Define or directive not defined: \'`UART_DIV\'\n    else if (apb_wr && s_apb_intf.paddr[11:0] == `UART_DIV) begin\n                                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:199: Define or directive not defined: \'`UART_LCR\'\n    else if (apb_wr && s_apb_intf.paddr[11:0] == `UART_LCR) begin\n                                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:207: Define or directive not defined: \'`UART_TXFIFO\'\n        `UART_TXFIFO: prdata_t = {tx_fifo_full,  31\'b0};\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:207: syntax error, unexpected \':\', expecting endcase\n        `UART_TXFIFO: prdata_t = {tx_fifo_full,  31\'b0};\n                    ^\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:208: Define or directive not defined: \'`UART_RXFIFO\'\n        `UART_RXFIFO: prdata_t = {rx_fifo_empty, 23\'b0, rx_fifo_rdata & {8{~rx_fifo_empty}}};\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:209: Define or directive not defined: \'`UART_TXCTRL\'\n        `UART_TXCTRL: prdata_t = {13\'b0, txcnt, 14\'b0, nstop, txen};\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:210: Define or directive not defined: \'`UART_RXCTRL\'\n        `UART_RXCTRL: prdata_t = {13\'b0, rxcnt, 14\'b0,  1\'b0, rxen};\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:211: Define or directive not defined: \'`UART_IE\'\n        `UART_IE    : prdata_t = {29\'b0, perror_ie, rxwm_ie, txwm_ie};\n        ^~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:212: Define or directive not defined: \'`UART_IP\'\n        `UART_IP    : prdata_t = {29\'b0, perror_ip, rxwm_ip, txwm_ip};\n        ^~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:213: Define or directive not defined: \'`UART_IC\'\n        `UART_IC    : prdata_t = {29\'b0, perror_ip, rxwm_ip, txwm_ip};\n        ^~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:214: Define or directive not defined: \'`UART_DIV\'\n        `UART_DIV   : prdata_t = {16\'b0, div};\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:215: Define or directive not defined: \'`UART_LCR\'\n        `UART_LCR   : prdata_t = {26\'b0, lcr, 3\'b0};\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:237: Define or directive not defined: \'`UART_DATA_WIDTH\'\n    input        [`UART_DATA_WIDTH-1:0] wdata,\n                  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:239: Define or directive not defined: \'`UART_DATA_WIDTH\'\n    output logic [`UART_DATA_WIDTH-1:0] rdata,\n                  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:248: Define or directive not defined: \'`UART_FIFO_DEPTH\'\nlocalparam PTR_WIDTH = $clog2(`UART_FIFO_DEPTH);\n                              ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:248: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nlocalparam PTR_WIDTH = $clog2(`UART_FIFO_DEPTH);\n                                              ^\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:250: Define or directive not defined: \'`UART_DATA_WIDTH\'\nlogic [`UART_DATA_WIDTH-1:0] fifo [`UART_FIFO_DEPTH];\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:250: Define or directive not defined: \'`UART_FIFO_DEPTH\'\nlogic [`UART_DATA_WIDTH-1:0] fifo [`UART_FIFO_DEPTH];\n                                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:277: Define or directive not defined: \'`UART_FIFO_DEPTH\'\n        for (i = 0; i < `UART_FIFO_DEPTH; i = i + 1) begin\n                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:277: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        for (i = 0; i < `UART_FIFO_DEPTH; i = i + 1) begin\n                                        ^\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:277: syntax error, unexpected \')\', expecting \';\'\n        for (i = 0; i < `UART_FIFO_DEPTH; i = i + 1) begin\n                                                   ^\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:278: Define or directive not defined: \'`UART_DATA_WIDTH\'\n            fifo[i] <= `UART_DATA_WIDTH\'b0;\n                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:281: syntax error, unexpected else\n    else begin\n    ^~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:433: Define or directive not defined: \'`UART_N_SYNC\'\nlogic [`UART_N_SYNC-1:0] uart_tx_dly;\n       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:446: Define or directive not defined: \'`UART_N_SYNC\'\n    if (~rstn) uart_tx_dly <= `UART_N_SYNC\'b0;\n                              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/peri/uart.sv:447: Define or directive not defined: \'`UART_N_SYNC\'\n    else       uart_tx_dly <= {uart_rx, uart_tx_dly[`UART_N_SYNC-1:1]};\n                                                    ^~~~~~~~~~~~\n%Error: Exiting due to 45 error(s)\n'
module uart (
    input                 clk,
    input                 rstn,
    apb_intf.slave        s_apb_intf,

    output logic          irq_out,
    input                 uart_rx,
    output logic          uart_tx
);

logic [                31:0] prdata_t;
logic                        txen;
logic                        nstop;
logic [                 2:0] txcnt;
logic                        rxen;
logic [                 2:0] rxcnt;
logic [                15:0] div;
logic                        apb_wr;
logic                        apb_rd;

logic                        tx_fifo_wr;
logic [`UART_DATA_WIDTH-1:0] tx_fifo_wdata;
logic                        tx_fifo_rd;
logic [`UART_DATA_WIDTH-1:0] tx_fifo_rdata;
logic                        tx_fifo_full;
logic                        tx_fifo_empty;

logic                        rx_fifo_wr;
logic [`UART_DATA_WIDTH-1:0] rx_fifo_wdata;
logic                        rx_fifo_rd;
logic [`UART_DATA_WIDTH-1:0] rx_fifo_rdata;
logic                        rx_fifo_full;
logic                        rx_fifo_empty;

logic                        txwm_ie;
logic                        rxwm_ie;
logic                        perror_ie;
logic                        txwm_ip;
logic                        rxwm_ip;
logic                        perror_ip;
logic                        txwm_ip_tmp;
logic                        rxwm_ip_tmp;
logic                        perror_ip_tmp;

logic [                 2:0] lcr;

assign irq_out    = (txwm_ip   && txwm_ie  ) ||
                    (rxwm_ip   && rxwm_ie  ) ||
                    (perror_ip && perror_ie);

assign apb_wr     = ~s_apb_intf.penable && s_apb_intf.psel &&  s_apb_intf.pwrite;
assign apb_rd     = ~s_apb_intf.penable && s_apb_intf.psel && ~s_apb_intf.pwrite;

`ifndef FAKE_UART
assign tx_fifo_wr    = apb_wr && s_apb_intf.paddr[11:0] == `UART_TXFIFO && ~tx_fifo_full && ~s_apb_intf.pwdata[31];
assign tx_fifo_wdata = s_apb_intf.pwdata[`UART_DATA_WIDTH-1:0];
`else
assign tx_fifo_wr    = 1'b0;
assign tx_fifo_wdata = s_apb_intf.pwdata[`UART_DATA_WIDTH-1:0];
always @(posedge clk or negedge rstn) begin: fake_uart_tx
    if (~rstn) begin
    end
    else if (apb_wr && s_apb_intf.paddr[11:0] == `UART_TXFIFO && ~s_apb_intf.pwdata[31]) begin
        $write("%c", tx_fifo_wdata[7:0]);
    end
end
`endif

uart_fifo u_tx_fifo(
    .clk          ( clk              ),
    .rstn         ( rstn             ),
    .wr           ( tx_fifo_wr       ),
    .wdata        ( tx_fifo_wdata    ),
    .rd           ( tx_fifo_rd       ),
    .rdata        ( tx_fifo_rdata    ),
    .full         ( tx_fifo_full     ),
    .empty        ( tx_fifo_empty    ),
    .full_th      ( 3'b0             ),
    .empty_th     ( txcnt            ),
    .almost_empty ( txwm_ip_tmp      )
);

tx_ctrl u_tx_ctrl(
    .clk      ( clk              ),
    .rstn     ( rstn             ),
    .enable   ( txen             ),
    .lcr      ( lcr              ),
    .nstop    ( nstop            ),
    .div      ( div              ),
    .data_vld ( ~tx_fifo_empty   ),
    .data_in  ( tx_fifo_rdata    ),
    .pop      ( tx_fifo_rd       ),
    .uart_tx  ( uart_tx          )
);

always_ff @(posedge clk or negedge rstn) begin
    if (~rstn) begin
        txen  <= 1'b0;
        nstop <= 1'b0;
        txcnt <= 3'b0;
    end
    else if (apb_wr && s_apb_intf.paddr[11:0] == `UART_TXCTRL) begin
        txen  <= s_apb_intf.pwdata[0];
        nstop <= s_apb_intf.pwdata[1];
        txcnt <= s_apb_intf.pwdata[18:16];
    end
end

assign rx_fifo_rd = apb_rd && s_apb_intf.paddr[11:0] == `UART_RXFIFO;

uart_fifo u_rx_fifo(
    .clk          ( clk              ),
    .rstn         ( rstn             ),
    .wr           ( rx_fifo_wr       ),
    .wdata        ( rx_fifo_wdata    ),
    .rd           ( rx_fifo_rd       ),
    .rdata        ( rx_fifo_rdata    ),
    .full         ( rx_fifo_full     ),
    .empty        ( rx_fifo_empty    ),
    .full_th      ( rxcnt            ),
    .almost_full  ( rxwm_ip_tmp      ),
    .empty_th     ( 3'b0             )
);

rx_ctrl u_rx_ctrl (
    .clk      ( clk              ),
    .rstn     ( rstn             ),
    .enable   ( rxen             ),
    .lcr      ( lcr              ),
    .div      ( div              ),
    .push     ( rx_fifo_wr       ),
    .data_out ( rx_fifo_wdata    ),
    .perror   ( perror_ip_tmp    ),
    .uart_rx  ( uart_rx          )
);

always_ff @(posedge clk or negedge rstn) begin
    if (~rstn) begin
        rxen  <= 1'b0;
        rxcnt <= 3'b0;
    end
    else if (apb_wr && s_apb_intf.paddr[11:0] == `UART_RXCTRL) begin
        rxen  <= s_apb_intf.pwdata[0];
        rxcnt <= s_apb_intf.pwdata[18:16];
    end
end

always_ff @(posedge clk or negedge rstn) begin
    if (~rstn) begin
        txwm_ie   <= 1'b0;
        rxwm_ie   <= 1'b0;
        perror_ie <= 1'b0;
    end
    else if (apb_wr && s_apb_intf.paddr[11:0] == `UART_IE) begin
        txwm_ie   <= s_apb_intf.pwdata[0];
        rxwm_ie   <= s_apb_intf.pwdata[1];
        perror_ie <= s_apb_intf.pwdata[2];
    end
end

always_ff @(posedge clk or negedge rstn) begin
    if (~rstn) begin
        txwm_ip   <= 1'b0;
        rxwm_ip   <= 1'b0;
        perror_ip <= 1'b0;
    end
    else if (apb_wr && s_apb_intf.paddr[11:0] == `UART_IC) begin
        txwm_ip   <= txwm_ip   && ~s_apb_intf.pwdata[0];
        rxwm_ip   <= rxwm_ip   && ~s_apb_intf.pwdata[1];
        perror_ip <= perror_ip && ~s_apb_intf.pwdata[2];
    end
    else begin
        txwm_ip   <= txwm_ip_tmp;
        rxwm_ip   <= rxwm_ip_tmp;
        perror_ip <= perror_ip_tmp;



    end
end

always_ff @(posedge clk or negedge rstn) begin
    if (~rstn) begin
        div <= 1000000000/22/115200;
    end
    else if (apb_wr && s_apb_intf.paddr[11:0] == `UART_DIV) begin
        div <= s_apb_intf.pwdata[15:0];
    end
end

always_ff @(posedge clk or negedge rstn) begin
    if (~rstn) begin
        lcr <= 3'b0;
    end
    else if (apb_wr && s_apb_intf.paddr[11:0] == `UART_LCR) begin
        lcr <= s_apb_intf.pwdata[5:3];
    end
end

always_comb begin
    prdata_t = 32'b0;
    case (s_apb_intf.paddr[11:0])
        `UART_TXFIFO: prdata_t = {tx_fifo_full,  31'b0};
        `UART_RXFIFO: prdata_t = {rx_fifo_empty, 23'b0, rx_fifo_rdata & {8{~rx_fifo_empty}}};
        `UART_TXCTRL: prdata_t = {13'b0, txcnt, 14'b0, nstop, txen};
        `UART_RXCTRL: prdata_t = {13'b0, rxcnt, 14'b0,  1'b0, rxen};
        `UART_IE    : prdata_t = {29'b0, perror_ie, rxwm_ie, txwm_ie};
        `UART_IP    : prdata_t = {29'b0, perror_ip, rxwm_ip, txwm_ip};
        `UART_IC    : prdata_t = {29'b0, perror_ip, rxwm_ip, txwm_ip};
        `UART_DIV   : prdata_t = {16'b0, div};
        `UART_LCR   : prdata_t = {26'b0, lcr, 3'b0};
    endcase
end

always_ff @(posedge clk or negedge rstn) begin
    if (~rstn) begin
        s_apb_intf.prdata <= 32'b0;
    end
    else begin
        s_apb_intf.prdata <= prdata_t;
    end
end

assign s_apb_intf.pslverr = 1'b0;
assign s_apb_intf.pready  = 1'b1;

endmodule
module uart (
    input                 clk,
    input                 rstn,
    apb_intf.slave        s_apb_intf,

    output logic          irq_out,
    input                 uart_rx,
    output logic          uart_tx
);


logic [                31:0] prdata_t;
logic                        txen;
logic                        nstop;
logic [                 2:0] txcnt;
logic                        rxen;
logic [                 2:0] rxcnt;
logic [                15:0] div;
logic                        apb_wr;
logic                        apb_rd;

logic                        tx_fifo_wr;
logic [`UART_DATA_WIDTH-1:0] tx_fifo_wdata;
logic                        tx_fifo_rd;
logic [`UART_DATA_WIDTH-1:0] tx_fifo_rdata;
logic                        tx_fifo_full;
logic                        tx_fifo_empty;

logic                        rx_fifo_wr;
logic [`UART_DATA_WIDTH-1:0] rx_fifo_wdata;
logic                        rx_fifo_rd;
logic [`UART_DATA_WIDTH-1:0] rx_fifo_rdata;
logic                        rx_fifo_full;
logic                        rx_fifo_empty;

logic                        txwm_ie;
logic                        rxwm_ie;
logic                        perror_ie;
logic                        txwm_ip;
logic                        rxwm_ip;
logic                        perror_ip;
logic                        txwm_ip_tmp;
logic                        rxwm_ip_tmp;
logic                        perror_ip_tmp;

logic [                 2:0] lcr;

assign irq_out    = (txwm_ip   && txwm_ie  ) ||
                    (rxwm_ip   && rxwm_ie  ) ||
                    (perror_ip && perror_ie);

assign apb_wr     = ~s_apb_intf.penable && s_apb_intf.psel &&  s_apb_intf.pwrite;
assign apb_rd     = ~s_apb_intf.penable && s_apb_intf.psel && ~s_apb_intf.pwrite;

`ifndef FAKE_UART
assign tx_fifo_wr    = apb_wr && s_apb_intf.paddr[11:0] == `UART_TXFIFO && ~tx_fifo_full && ~s_apb_intf.pwdata[31];
assign tx_fifo_wdata = s_apb_intf.pwdata[`UART_DATA_WIDTH-1:0];
`else
assign tx_fifo_wr    = 1'b0;
assign tx_fifo_wdata = s_apb_intf.pwdata[`UART_DATA_WIDTH-1:0];
always @(posedge clk or negedge rstn) begin: fake_uart_tx
    if (~rstn) begin
    end
    else if (apb_wr && s_apb_intf.paddr[11:0] == `UART_TXFIFO && ~s_apb_intf.pwdata[31]) begin
        $write("%c", tx_fifo_wdata[7:0]);
    end
end
`endif

uart_fifo u_tx_fifo(
    .clk          ( clk              ),
    .rstn         ( rstn             ),
    .wr           ( tx_fifo_wr       ),
    .wdata        ( tx_fifo_wdata    ),
    .rd           ( tx_fifo_rd       ),
    .rdata        ( tx_fifo_rdata    ),
    .full         ( tx_fifo_full     ),
    .empty        ( tx_fifo_empty    ),
    .full_th      ( 3'b0             ),
    .empty_th     ( txcnt            ),
    .almost_empty ( txwm_ip_tmp      )
);

tx_ctrl u_tx_ctrl(
    .clk      ( clk              ),
    .rstn     ( rstn             ),
    .enable   ( txen             ),
    .lcr      ( lcr              ),
    .nstop    ( nstop            ),
    .div      ( div              ),
    .data_vld ( ~tx_fifo_empty   ),
    .data_in  ( tx_fifo_rdata    ),
    .pop      ( tx_fifo_rd       ),
    .uart_tx  ( uart_tx          )
);

always_ff @(posedge clk or negedge rstn) begin
    if (~rstn) begin
        txen  <= 1'b0;
        nstop <= 1'b0;
        txcnt <= 3'b0;
    end
    else if (apb_wr && s_apb_intf.paddr[11:0] == `UART_TXCTRL) begin
        txen  <= s_apb_intf.pwdata[0];
        nstop <= s_apb_intf.pwdata[1];
        txcnt <= s_apb_intf.pwdata[18:16];
    end
end

assign rx_fifo_rd = apb_rd && s_apb_intf.paddr[11:0] == `UART_RXFIFO;

uart_fifo u_rx_fifo(
    .clk          ( clk              ),
    .rstn         ( rstn             ),
    .wr           ( rx_fifo_wr       ),
    .wdata        ( rx_fifo_wdata    ),
    .rd           ( rx_fifo_rd       ),
    .rdata        ( rx_fifo_rdata    ),
    .full         ( rx_fifo_full     ),
    .empty        ( rx_fifo_empty    ),
    .full_th      ( rxcnt            ),
    .almost_full  ( rxwm_ip_tmp      ),
    .empty_th     ( 3'b0             )
);

rx_ctrl u_rx_ctrl (
    .clk      ( clk              ),
    .rstn     ( rstn             ),
    .enable   ( rxen             ),
    .lcr      ( lcr              ),
    .div      ( div              ),
    .push     ( rx_fifo_wr       ),
    .data_out ( rx_fifo_wdata    ),
    .perror   ( perror_ip_tmp    ),
    .uart_rx  ( uart_rx          )
);

always_ff @(posedge clk or negedge rstn) begin
    if (~rstn) begin
        rxen  <= 1'b0;
        rxcnt <= 3'b0;
    end
    else if (apb_wr && s_apb_intf.paddr[11:0] == `UART_RXCTRL) begin
        rxen  <= s_apb_intf.pwdata[0];
        rxcnt <= s_apb_intf.pwdata[18:16];
    end
end

always_ff @(posedge clk or negedge rstn) begin
    if (~rstn) begin
        txwm_ie   <= 1'b0;
        rxwm_ie   <= 1'b0;
        perror_ie <= 1'b0;
    end
    else if (apb_wr && s_apb_intf.paddr[11:0] == `UART_IE) begin
        txwm_ie   <= s_apb_intf.pwdata[0];
        rxwm_ie   <= s_apb_intf.pwdata[1];
        perror_ie <= s_apb_intf.pwdata[2];
    end
end

always_ff @(posedge clk or negedge rstn) begin
    if (~rstn) begin
        txwm_ip   <= 1'b0;
        rxwm_ip   <= 1'b0;
        perror_ip <= 1'b0;
    end
    else if (apb_wr && s_apb_intf.paddr[11:0] == `UART_IC) begin
        txwm_ip   <= txwm_ip   && ~s_apb_intf.pwdata[0];
        rxwm_ip   <= rxwm_ip   && ~s_apb_intf.pwdata[1];
        perror_ip <= perror_ip && ~s_apb_intf.pwdata[2];
    end
    else begin
        txwm_ip   <= txwm_ip_tmp;
        rxwm_ip   <= rxwm_ip_tmp;
        perror_ip <= perror_ip_tmp;



    end
end

always_ff @(posedge clk or negedge rstn) begin
    if (~rstn) begin
        div <= 1000000000/22/115200;
    end
    else if (apb_wr && s_apb_intf.paddr[11:0] == `UART_DIV) begin
        div <= s_apb_intf.pwdata[15:0];
    end
end

always_ff @(posedge clk or negedge rstn) begin
    if (~rstn) begin
        lcr <= 3'b0;
    end
    else if (apb_wr && s_apb_intf.paddr[11:0] == `UART_LCR) begin
        lcr <= s_apb_intf.pwdata[5:3];
    end
end

always_comb begin
    prdata_t = 32'b0;
    case (s_apb_intf.paddr[11:0])
        `UART_TXFIFO: prdata_t = {tx_fifo_full,  31'b0};
        `UART_RXFIFO: prdata_t = {rx_fifo_empty, 23'b0, rx_fifo_rdata & {8{~rx_fifo_empty}}};
        `UART_TXCTRL: prdata_t = {13'b0, txcnt, 14'b0, nstop, txen};
        `UART_RXCTRL: prdata_t = {13'b0, rxcnt, 14'b0,  1'b0, rxen};
        `UART_IE    : prdata_t = {29'b0, perror_ie, rxwm_ie, txwm_ie};
        `UART_IP    : prdata_t = {29'b0, perror_ip, rxwm_ip, txwm_ip};
        `UART_IC    : prdata_t = {29'b0, perror_ip, rxwm_ip, txwm_ip};
        `UART_DIV   : prdata_t = {16'b0, div};
        `UART_LCR   : prdata_t = {26'b0, lcr, 3'b0};
    endcase
end

always_ff @(posedge clk or negedge rstn) begin
    if (~rstn) begin
        s_apb_intf.prdata <= 32'b0;
    end
    else begin
        s_apb_intf.prdata <= prdata_t;
    end
end

assign s_apb_intf.pslverr = 1'b0;
assign s_apb_intf.pready  = 1'b1;

endmodule