data/full_repos/permissive/419538859/lab2/lab2_1/sim/lab2_1_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/419538859/lab2/lab2_1/sim/lab2_1_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n #20;   \n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab2/lab2_1/sim/lab2_1_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n #20; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab2/lab2_1/sim/lab2_1_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n #20; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab2/lab2_1/sim/lab2_1_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab2/lab2_1/sim/lab2_1_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab2/lab2_1/sim/lab2_1_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab2/lab2_1/sim/lab2_1_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab2/lab2_1/sim/lab2_1_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n #20; \n ^\n%Error: data/full_repos/permissive/419538859/lab2/lab2_1/sim/lab2_1_tb.v:9: Cannot find file containing module: \'bcd_to_seg7\'\nbcd_to_seg7 bcd_to_seg7_instance(bcd_in, seg7_sel, seg7_out, dpt_out);\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/419538859/lab2/lab2_1/sim,data/full_repos/permissive/419538859/bcd_to_seg7\n             data/full_repos/permissive/419538859/lab2/lab2_1/sim,data/full_repos/permissive/419538859/bcd_to_seg7.v\n             data/full_repos/permissive/419538859/lab2/lab2_1/sim,data/full_repos/permissive/419538859/bcd_to_seg7.sv\n             bcd_to_seg7\n             bcd_to_seg7.v\n             bcd_to_seg7.sv\n             obj_dir/bcd_to_seg7\n             obj_dir/bcd_to_seg7.v\n             obj_dir/bcd_to_seg7.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module 	testbench;
reg [3:0] bcd_in;
wire [2:0] seg7_sel;
wire [6:0] seg7_out;
wire dpt_out;

bcd_to_seg7 bcd_to_seg7_instance(bcd_in, seg7_sel, seg7_out, dpt_out);




initial
begin
 bcd_in=4'b0000;
 #20;		 
 bcd_in=4'b0001;
 #20; 
 bcd_in=4'b0010;
 #20; 
 bcd_in=4'b0011;
 #20;
 bcd_in=4'b0100;
 #20;
 bcd_in=4'b0101;
 #20;
 bcd_in=4'b0110;
 #20;
 bcd_in=4'b0111;
 #20; 
end
endmodule
module 	testbench;

reg [3:0] bcd_in;
wire [2:0] seg7_sel;
wire [6:0] seg7_out;
wire dpt_out;

bcd_to_seg7 bcd_to_seg7_instance(bcd_in, seg7_sel, seg7_out, dpt_out);




initial
begin
 bcd_in=4'b0000;
 #20;		 
 bcd_in=4'b0001;
 #20; 
 bcd_in=4'b0010;
 #20; 
 bcd_in=4'b0011;
 #20;
 bcd_in=4'b0100;
 #20;
 bcd_in=4'b0101;
 #20;
 bcd_in=4'b0110;
 #20;
 bcd_in=4'b0111;
 #20; 
end
endmodule