data/full_repos/permissive/513806017/generated/Hello.v
data/verilator_xmls/8cd341e1-d444-46ce-b0bf-2288791e475a.xml
module Tx(
  input        clock,
  input        reset,
  output       io_txd,
  output       io_channel_ready,
  input        io_channel_valid,
  input  [7:0] io_channel_bits
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif
  reg [10:0] shiftReg;
  reg [19:0] cntReg;
  reg [3:0] bitsReg;
  wire  _io_channel_ready_T = cntReg == 20'h0;
  wire [9:0] shift = shiftReg[10:1];
  wire [10:0] _shiftReg_T_1 = {1'h1,shift};
  wire [3:0] _bitsReg_T_1 = bitsReg - 4'h1;
  wire [10:0] _shiftReg_T_3 = {2'h3,io_channel_bits,1'h0};
  wire [19:0] _cntReg_T_1 = cntReg - 20'h1;
  assign io_txd = shiftReg[0];
  assign io_channel_ready = cntReg == 20'h0 & bitsReg == 4'h0;
  always @(posedge clock) begin
    if (reset) begin
      shiftReg <= 11'h7ff;
    end else if (_io_channel_ready_T) begin
      if (bitsReg != 4'h0) begin
        shiftReg <= _shiftReg_T_1;
      end else if (io_channel_valid) begin
        shiftReg <= _shiftReg_T_3;
      end else begin
        shiftReg <= 11'h7ff;
      end
    end
    if (reset) begin
      cntReg <= 20'h0;
    end else if (_io_channel_ready_T) begin
      cntReg <= 20'h4e1;
    end else begin
      cntReg <= _cntReg_T_1;
    end
    if (reset) begin
      bitsReg <= 4'h0;
    end else if (_io_channel_ready_T) begin
      if (bitsReg != 4'h0) begin
        bitsReg <= _bitsReg_T_1;
      end else if (io_channel_valid) begin
        bitsReg <= 4'hb;
      end
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  shiftReg = _RAND_0[10:0];
  _RAND_1 = {1{`RANDOM}};
  cntReg = _RAND_1[19:0];
  _RAND_2 = {1{`RANDOM}};
  bitsReg = _RAND_2[3:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module Tx(
  input        clock,
  input        reset,
  output       io_txd,
  output       io_channel_ready,
  input        io_channel_valid,
  input  [7:0] io_channel_bits
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif
  reg [10:0] shiftReg;
  reg [19:0] cntReg;
  reg [3:0] bitsReg;
  wire  _io_channel_ready_T = cntReg == 20'h0;
  wire [9:0] shift = shiftReg[10:1];
  wire [10:0] _shiftReg_T_1 = {1'h1,shift};
  wire [3:0] _bitsReg_T_1 = bitsReg - 4'h1;
  wire [10:0] _shiftReg_T_3 = {2'h3,io_channel_bits,1'h0};
  wire [19:0] _cntReg_T_1 = cntReg - 20'h1;
  assign io_txd = shiftReg[0];
  assign io_channel_ready = cntReg == 20'h0 & bitsReg == 4'h0;
  always @(posedge clock) begin
    if (reset) begin
      shiftReg <= 11'h7ff;
    end else if (_io_channel_ready_T) begin
      if (bitsReg != 4'h0) begin
        shiftReg <= _shiftReg_T_1;
      end else if (io_channel_valid) begin
        shiftReg <= _shiftReg_T_3;
      end else begin
        shiftReg <= 11'h7ff;
      end
    end
    if (reset) begin
      cntReg <= 20'h0;
    end else if (_io_channel_ready_T) begin
      cntReg <= 20'h4e1;
    end else begin
      cntReg <= _cntReg_T_1;
    end
    if (reset) begin
      bitsReg <= 4'h0;
    end else if (_io_channel_ready_T) begin
      if (bitsReg != 4'h0) begin
        bitsReg <= _bitsReg_T_1;
      end else if (io_channel_valid) begin
        bitsReg <= 4'hb;
      end
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  shiftReg = _RAND_0[10:0];
  _RAND_1 = {1{`RANDOM}};
  cntReg = _RAND_1[19:0];
  _RAND_2 = {1{`RANDOM}};
  bitsReg = _RAND_2[3:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule