data/full_repos/permissive/471089853/src/pe_s3.v
1: b"%Error: data/full_repos/permissive/471089853/src/pe_s3.v:68: Cannot find file containing module: 's3fdp'\n  s3fdp s3fdp_inst (\n  ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/471089853/src,data/full_repos/permissive/471089853/s3fdp\n             data/full_repos/permissive/471089853/src,data/full_repos/permissive/471089853/s3fdp.v\n             data/full_repos/permissive/471089853/src,data/full_repos/permissive/471089853/s3fdp.sv\n             s3fdp\n             s3fdp.v\n             s3fdp.sv\n             obj_dir/s3fdp\n             obj_dir/s3fdp.v\n             obj_dir/s3fdp.sv\n%Error: Exiting due to 1 error(s)\n"
module PE_S3(clk, rst, s3_row_i_A, s3_col_j_B, C_out, SOB, EOB, s3_row_im1_A, s3_col_jm1_B, SOB_Q, EOB_Q, C_out_Q);
  reg [32:0] _00_;
  wire _01_;
  wire _02_;
  reg [32:0] _03_;
  reg [11:0] _04_;
  reg [11:0] _05_;
  reg _06_;
  reg _07_;
  wire _08_;
  wire [32:0] _09_;
  wire [31:0] _10_;
  input [32:0] C_out;
  output [32:0] C_out_Q;
  input EOB;
  output EOB_Q;
  input SOB;
  output SOB_Q;
  wire [31:0] a_s3fdp;
  input clk;
  wire eob_d1;
  wire eob_delayed;
  wire eob_s3fdp;
  wire isnan_s3fdp;
  wire [32:0] mux_c_out;
  wire [32:0] mux_c_out_d1;
  wire [32:0] mux_c_out_d2;
  wire [32:0] mux_c_out_hssd;
  input rst;
  input [11:0] s3_col_j_B;
  wire [11:0] s3_col_j_b_d1;
  wire [11:0] s3_col_j_b_q;
  output [11:0] s3_col_jm1_B;
  input [11:0] s3_row_i_A;
  wire [11:0] s3_row_i_a_d1;
  wire [11:0] s3_row_i_a_q;
  output [11:0] s3_row_im1_A;
  wire sob_d1;
  wire sob_delayed;
  always @(posedge clk)
    _00_ <= mux_c_out;
  always @(posedge clk)
    _03_ <= mux_c_out_d1;
  always @(posedge clk)
    _04_ <= s3_row_i_A;
  always @(posedge clk)
    _05_ <= s3_col_j_B;
  always @(posedge clk)
    _06_ <= SOB;
  always @(posedge clk)
    _07_ <= EOB;
  assign _08_ = eob_s3fdp == 1'h1;
  function [32:0] \24 ;
    input [32:0] a;
    input [32:0] b;
    input [0:0] s;
    (* parallel_case *)
    casez (s)
      1'b1:
        \24  = b[32:0];
      default:
        \24  = a;
    endcase
  endfunction
  assign _09_ = \24 (C_out, { isnan_s3fdp, a_s3fdp }, _08_);
  s3fdp s3fdp_inst (
    .A(_10_),
    .EOB(EOB),
    .EOB_Q(_01_),
    .FTZ(SOB),
    .S3_x(s3_row_i_A),
    .S3_y(s3_col_j_B),
    .clk(clk),
    .isNaN(_02_),
    .rst(rst)
  );
  assign s3_row_i_a_q = s3_row_i_a_d1;
  assign s3_col_j_b_q = s3_col_j_b_d1;
  assign sob_delayed = sob_d1;
  assign eob_delayed = eob_d1;
  assign mux_c_out = _09_;
  assign mux_c_out_d1 = _00_;
  assign mux_c_out_d2 = _03_;
  assign mux_c_out_hssd = mux_c_out_d2;
  assign isnan_s3fdp = _02_;
  assign eob_s3fdp = _01_;
  assign a_s3fdp = _10_;
  assign s3_row_i_a_d1 = _04_;
  assign s3_col_j_b_d1 = _05_;
  assign sob_d1 = _06_;
  assign eob_d1 = _07_;
  assign s3_row_im1_A = s3_row_i_a_q;
  assign s3_col_jm1_B = s3_col_j_b_q;
  assign SOB_Q = sob_delayed;
  assign EOB_Q = eob_delayed;
  assign C_out_Q = mux_c_out_hssd;
endmodule
module PE_S3(clk, rst, s3_row_i_A, s3_col_j_B, C_out, SOB, EOB, s3_row_im1_A, s3_col_jm1_B, SOB_Q, EOB_Q, C_out_Q);

  reg [32:0] _00_;
  wire _01_;
  wire _02_;
  reg [32:0] _03_;
  reg [11:0] _04_;
  reg [11:0] _05_;
  reg _06_;
  reg _07_;
  wire _08_;
  wire [32:0] _09_;
  wire [31:0] _10_;
  input [32:0] C_out;
  output [32:0] C_out_Q;
  input EOB;
  output EOB_Q;
  input SOB;
  output SOB_Q;
  wire [31:0] a_s3fdp;
  input clk;
  wire eob_d1;
  wire eob_delayed;
  wire eob_s3fdp;
  wire isnan_s3fdp;
  wire [32:0] mux_c_out;
  wire [32:0] mux_c_out_d1;
  wire [32:0] mux_c_out_d2;
  wire [32:0] mux_c_out_hssd;
  input rst;
  input [11:0] s3_col_j_B;
  wire [11:0] s3_col_j_b_d1;
  wire [11:0] s3_col_j_b_q;
  output [11:0] s3_col_jm1_B;
  input [11:0] s3_row_i_A;
  wire [11:0] s3_row_i_a_d1;
  wire [11:0] s3_row_i_a_q;
  output [11:0] s3_row_im1_A;
  wire sob_d1;
  wire sob_delayed;
  always @(posedge clk)
    _00_ <= mux_c_out;
  always @(posedge clk)
    _03_ <= mux_c_out_d1;
  always @(posedge clk)
    _04_ <= s3_row_i_A;
  always @(posedge clk)
    _05_ <= s3_col_j_B;
  always @(posedge clk)
    _06_ <= SOB;
  always @(posedge clk)
    _07_ <= EOB;
  assign _08_ = eob_s3fdp == 1'h1;
  function [32:0] \24 ;
    input [32:0] a;
    input [32:0] b;
    input [0:0] s;
    (* parallel_case *)
    casez (s)
      1'b1:
        \24  = b[32:0];
      default:
        \24  = a;
    endcase
  endfunction
  assign _09_ = \24 (C_out, { isnan_s3fdp, a_s3fdp }, _08_);
  s3fdp s3fdp_inst (
    .A(_10_),
    .EOB(EOB),
    .EOB_Q(_01_),
    .FTZ(SOB),
    .S3_x(s3_row_i_A),
    .S3_y(s3_col_j_B),
    .clk(clk),
    .isNaN(_02_),
    .rst(rst)
  );
  assign s3_row_i_a_q = s3_row_i_a_d1;
  assign s3_col_j_b_q = s3_col_j_b_d1;
  assign sob_delayed = sob_d1;
  assign eob_delayed = eob_d1;
  assign mux_c_out = _09_;
  assign mux_c_out_d1 = _00_;
  assign mux_c_out_d2 = _03_;
  assign mux_c_out_hssd = mux_c_out_d2;
  assign isnan_s3fdp = _02_;
  assign eob_s3fdp = _01_;
  assign a_s3fdp = _10_;
  assign s3_row_i_a_d1 = _04_;
  assign s3_col_j_b_d1 = _05_;
  assign sob_d1 = _06_;
  assign eob_d1 = _07_;
  assign s3_row_im1_A = s3_row_i_a_q;
  assign s3_col_jm1_B = s3_col_j_b_q;
  assign SOB_Q = sob_delayed;
  assign EOB_Q = eob_delayed;
  assign C_out_Q = mux_c_out_hssd;
endmodule