data/full_repos/permissive/501470173/verilog/rtl/vga_control.v
1: b'%Warning-WIDTH: data/full_repos/permissive/501470173/verilog/rtl/vga_control.v:62: Operator LT expects 32 or 10 bits on the LHS, but LHS\'s VARREF \'vcnt\' generates 9 bits.\n                                                                                 : ... In instance vga_control\n   if (vcnt<524)\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/501470173/verilog/rtl/vga_control.v:104: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s SEL generates 6 bits.\n                                                                                  : ... In instance vga_control\nassign x=hcnt[9:4];\n        ^\n%Warning-WIDTH: data/full_repos/permissive/501470173/verilog/rtl/vga_control.v:105: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                                  : ... In instance vga_control\nassign y=vcnt[8:4];\n        ^\n%Warning-WIDTH: data/full_repos/permissive/501470173/verilog/rtl/vga_control.v:106: Operator ASSIGNW expects 11 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 13 bits.\n                                                                                  : ... In instance vga_control\nassign addrb={y, x};\n            ^\n%Error: Exiting due to 4 warning(s)\n'
module vga_control(
    input clk,
    input rst,
	 input [2:0] ncolor,
    output reg hs, vs,
	 output [2:0] color,
    output [10:0] addrb
    );

reg [9:0] hcnt;
reg [8:0] vcnt;
reg clk25;

reg hsync, vsync;
wire [6:0] x;
wire [5:0] y;
wire blank;


always@(posedge clk or posedge rst)
	if (rst)
		clk25<=0;
	else
		clk25<=~clk25;


always@(posedge clk25 or posedge rst)
	if (rst)
		hcnt<=0;
	else
		if (hcnt<800)
			hcnt<=hcnt+1;
		else
			hcnt<=0;


always@(posedge clk25 or posedge rst)
	if (rst)
		vcnt<=0;
	else
		if (hcnt==0)
			if (vcnt<524)
				vcnt<=vcnt+1;
			else
			   vcnt<=0;


always@(posedge clk25 or posedge rst)
	if (rst)
		hsync<=1;
	else
		if (hcnt>=656 && hcnt<752)
			hsync<=0;
		else
			hsync<=1;


always@(posedge clk25 or posedge rst)
	if (rst)
		vsync<=1;
	else
		if (vcnt>=491 && vcnt<493)
			vsync<=0;
		else
			vsync<=1;

assign blank=(hcnt>=640 || vcnt>=480)? 1: 0;

always@(posedge clk or posedge rst)
	if (rst) 
		begin
			hs<=1;
			vs<=1; 
		end
	else 
		begin
			hs<=hsync;
			vs<=vsync;
		end

assign color=blank? 0: ncolor;
			

assign x=hcnt[9:4];
assign y=vcnt[8:4];
assign addrb={y, x};


endmodule
module vga_control(
    input clk,
    input rst,
	 input [2:0] ncolor,
    output reg hs, vs,
	 output [2:0] color,
    output [10:0] addrb
    );


reg [9:0] hcnt;
reg [8:0] vcnt;
reg clk25;

reg hsync, vsync;
wire [6:0] x;
wire [5:0] y;
wire blank;


always@(posedge clk or posedge rst)
	if (rst)
		clk25<=0;
	else
		clk25<=~clk25;


always@(posedge clk25 or posedge rst)
	if (rst)
		hcnt<=0;
	else
		if (hcnt<800)
			hcnt<=hcnt+1;
		else
			hcnt<=0;


always@(posedge clk25 or posedge rst)
	if (rst)
		vcnt<=0;
	else
		if (hcnt==0)
			if (vcnt<524)
				vcnt<=vcnt+1;
			else
			   vcnt<=0;


always@(posedge clk25 or posedge rst)
	if (rst)
		hsync<=1;
	else
		if (hcnt>=656 && hcnt<752)
			hsync<=0;
		else
			hsync<=1;


always@(posedge clk25 or posedge rst)
	if (rst)
		vsync<=1;
	else
		if (vcnt>=491 && vcnt<493)
			vsync<=0;
		else
			vsync<=1;

assign blank=(hcnt>=640 || vcnt>=480)? 1: 0;

always@(posedge clk or posedge rst)
	if (rst) 
		begin
			hs<=1;
			vs<=1; 
		end
	else 
		begin
			hs<=hsync;
			vs<=vsync;
		end

assign color=blank? 0: ncolor;
			

assign x=hcnt[9:4];
assign y=vcnt[8:4];
assign addrb={y, x};


endmodule