data/full_repos/permissive/506186384/project-files/lab5/ALU.v
data/verilator_xmls/d5c03c54-62d0-4f47-ab5d-3b6122b6b588.xml
module ALU(
    input [31:0] input1,
    input [31:0] input2,
    input [3:0] ALUCtr,
    output zero,
    output [31:0] ALURes
    );
    
    reg Zero;
    reg [31:0] alures;
    reg signed [31:0] slt_input1;
    reg signed [31:0] slt_input2;
    
    always @ (input1 or input2 or ALUCtr)
    begin
        case(ALUCtr)
            4'b0000:
            begin
                alures = input1 & input2;
                if(alures == 0)
                    Zero = 1;
                else
                    Zero = 0;
            end
            
            4'b0001:
            begin
                alures = input1 | input2;
                if(alures == 0)
                    Zero = 1;
                else
                    Zero = 0;
            end
            
            4'b0010:
            begin
                alures = input1 + input2;
                if(alures == 0)
                    Zero = 1;
                else
                    Zero = 0;
            end
            
            4'b0110:
            begin
                alures = input1 - input2;
                if(alures == 0)
                    Zero = 1;
                else
                    Zero = 0;
            end
            
            4'b0111:
            begin
                slt_input1 = input1;
                slt_input2 = input2;
                if(slt_input1 < slt_input2)
                    alures = 1;
                else
                    alures = 0;
                if(alures == 0)
                    Zero = 1;
                else
                    Zero = 0;
            end
            
            4'b1100:
            begin
                alures = ~(input1 | input2);
                if(alures == 0)
                    Zero = 1;
                else
                    Zero = 0;
            end
            
            4'b0011:
            begin
                alures = input1 << input2[4:0];
                if(alures == 0)
                    Zero = 1;
                else
                    Zero = 0;
            end
            
            4'b0100:
            begin
                alures = input1 >> input2[4:0];
                if(alures == 0)
                    Zero = 1;
                else
                    Zero = 0;
            end
            
            4'b0101:
            begin
                alures = 0;
                Zero = 1;
            end
            
            default:
            begin
                alures = 0;
                Zero = 1;
            end
        endcase
    end
    assign ALURes = alures;
    assign zero = Zero;
endmodule
module ALU(
    input [31:0] input1,
    input [31:0] input2,
    input [3:0] ALUCtr,
    output zero,
    output [31:0] ALURes
    );

    
    reg Zero;
    reg [31:0] alures;
    reg signed [31:0] slt_input1;
    reg signed [31:0] slt_input2;
    
    always @ (input1 or input2 or ALUCtr)
    begin
        case(ALUCtr)
            4'b0000:
            begin
                alures = input1 & input2;
                if(alures == 0)
                    Zero = 1;
                else
                    Zero = 0;
            end
            
            4'b0001:
            begin
                alures = input1 | input2;
                if(alures == 0)
                    Zero = 1;
                else
                    Zero = 0;
            end
            
            4'b0010:
            begin
                alures = input1 + input2;
                if(alures == 0)
                    Zero = 1;
                else
                    Zero = 0;
            end
            
            4'b0110:
            begin
                alures = input1 - input2;
                if(alures == 0)
                    Zero = 1;
                else
                    Zero = 0;
            end
            
            4'b0111:
            begin
                slt_input1 = input1;
                slt_input2 = input2;
                if(slt_input1 < slt_input2)
                    alures = 1;
                else
                    alures = 0;
                if(alures == 0)
                    Zero = 1;
                else
                    Zero = 0;
            end
            
            4'b1100:
            begin
                alures = ~(input1 | input2);
                if(alures == 0)
                    Zero = 1;
                else
                    Zero = 0;
            end
            
            4'b0011:
            begin
                alures = input1 << input2[4:0];
                if(alures == 0)
                    Zero = 1;
                else
                    Zero = 0;
            end
            
            4'b0100:
            begin
                alures = input1 >> input2[4:0];
                if(alures == 0)
                    Zero = 1;
                else
                    Zero = 0;
            end
            
            4'b0101:
            begin
                alures = 0;
                Zero = 1;
            end
            
            default:
            begin
                alures = 0;
                Zero = 1;
            end
        endcase
    end
    assign ALURes = alures;
    assign zero = Zero;
endmodule