data/full_repos/permissive/465580112/testbench/adder_tb.v
1: b'%Error: data/full_repos/permissive/465580112/testbench/adder_tb.v:2: syntax error, unexpected --\n----------------------Test Bench-------------------------------\n^~\n%Warning-STMTDLY: data/full_repos/permissive/465580112/testbench/adder_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/465580112/testbench/adder_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module addq_tb(); 
reg rst;
reg [15:0] x,y;
wire [15:0] sum;
  addq addd(rst,x,y,sum);

initial
begin
rst=1;
#10;
rst=0;
x=16'b1011010000000000;
y=16'b1011010000000000;
#50;
$finish;
end

endmodule
module addq_tb();
 
reg rst;
reg [15:0] x,y;
wire [15:0] sum;
  addq addd(rst,x,y,sum);

initial
begin
rst=1;
#10;
rst=0;
x=16'b1011010000000000;
y=16'b1011010000000000;
#50;
$finish;
end

endmodule