data/full_repos/permissive/515524111/fifo_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/515524111/fifo_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n   forever #(T/2) clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/515524111/fifo_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #T;\n ^\n%Error: data/full_repos/permissive/515524111/fifo_tb.v:58: syntax error, unexpected \'@\'\n    @(negedge clk);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515524111/fifo_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n   #T;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/515524111/fifo_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n #T;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/515524111/fifo_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n #T;\n ^\n%Error: data/full_repos/permissive/515524111/fifo_tb.v:82: Unsupported or unknown PLI call: $monitor\ninitial $monitor($time,"rst=%b,wr_en=%b,rd_en=%b,clk=%b,data_in=%b,data_out=%b,empty=%b,full=%b",rst,wr_en,rd_en,clk,data_in,data_out,empty,full); \n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/515524111/fifo_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\ninitial #1000 $finish;\n        ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fifo_tb();

reg clk,rst,wr_en,rd_en;
reg [7:0]data_in;
wire [7:0]data_out;
wire empty,full;
integer i;
parameter T = 10;

fifo DUT(clk,rst,wr_en,rd_en,data_in,data_out,empty,full);


initial 
  begin
   clk = 1'b0;  

   forever #(T/2) clk = ~clk;

 end



task reset;
  begin
    rst = 1'b1;
	#T;

    rst = 1'b0;
  end
endtask



task write;
  begin
    wr_en = 1'b1;
	rd_en = 1'b0;


  end
endtask



task read;
  begin
    rd_en = 1'b1;
	wr_en = 1'b0;


  end
endtask



task stimulus(input [7:0]p);
  begin
    @(negedge clk);
	data_in = p;
  end
endtask

initial 
  begin
	  reset;
	  write;
	  for(i=0;i<16;i=i+1)
	    begin
		 stimulus({$random}%256);
		 #T;
		end
	repeat(16)   
	read;
	#T;
	rd_en = 1'b1;
	wr_en = 1'b1;
	repeat(16)
	stimulus({$random}%256);
	#T;
 end
 
initial $monitor($time,"rst=%b,wr_en=%b,rd_en=%b,clk=%b,data_in=%b,data_out=%b,empty=%b,full=%b",rst,wr_en,rd_en,clk,data_in,data_out,empty,full); 
initial #1000 $finish;

endmodule
module fifo_tb();


reg clk,rst,wr_en,rd_en;
reg [7:0]data_in;
wire [7:0]data_out;
wire empty,full;
integer i;
parameter T = 10;

fifo DUT(clk,rst,wr_en,rd_en,data_in,data_out,empty,full);


initial 
  begin
   clk = 1'b0;  

   forever #(T/2) clk = ~clk;

 end



task reset;
  begin
    rst = 1'b1;
	#T;

    rst = 1'b0;
  end
endtask



task write;
  begin
    wr_en = 1'b1;
	rd_en = 1'b0;


  end
endtask



task read;
  begin
    rd_en = 1'b1;
	wr_en = 1'b0;


  end
endtask



task stimulus(input [7:0]p);
  begin
    @(negedge clk);
	data_in = p;
  end
endtask

initial 
  begin
	  reset;
	  write;
	  for(i=0;i<16;i=i+1)
	    begin
		 stimulus({$random}%256);
		 #T;
		end
	repeat(16)   
	read;
	#T;
	rd_en = 1'b1;
	wr_en = 1'b1;
	repeat(16)
	stimulus({$random}%256);
	#T;
 end
 
initial $monitor($time,"rst=%b,wr_en=%b,rd_en=%b,clk=%b,data_in=%b,data_out=%b,empty=%b,full=%b",rst,wr_en,rd_en,clk,data_in,data_out,empty,full); 
initial #1000 $finish;

endmodule