data/full_repos/permissive/507312280/rtl/core/trap.v
1: b'%Error: data/full_repos/permissive/507312280/rtl/core/trap.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507312280/rtl/core,data/full_repos/permissive/507312280/defines.v\n             data/full_repos/permissive/507312280/rtl/core,data/full_repos/permissive/507312280/defines.v.v\n             data/full_repos/permissive/507312280/rtl/core,data/full_repos/permissive/507312280/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/507312280/rtl/core/trap.v:7: Define or directive not defined: \'`RegBus\'\n    input wire[`RegBus] csr_rdata_i,         \n               ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/trap.v:7: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire[`RegBus] csr_rdata_i,         \n                      ^\n%Error: data/full_repos/permissive/507312280/rtl/core/trap.v:8: Define or directive not defined: \'`RegBus\'\n    output reg[`RegBus] csr_wdata_o,         \n               ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/trap.v:10: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg[`CsrAddrBus] csr_addr_o,      \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/trap.v:10: Define or directive not defined: \'`CsrAddrBus\'\n    output reg[`CsrAddrBus] csr_addr_o,      \n               ^~~~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/trap.v:14: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire ebreak_i, \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/trap.v:15: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire inst_err_i, \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/trap.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire mem_err_i, \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/trap.v:19: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire ex_trap_valid_i, \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/trap.v:20: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire tcmp_trap_valid_i, \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/trap.v:21: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire soft_trap_valid_i, \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/trap.v:23: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire mstatus_MIE3, \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/trap.v:24: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire wfi_i, \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/trap.v:26: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire[`InstAddrBus] pc_i,             \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/trap.v:26: Define or directive not defined: \'`InstAddrBus\'\n    input wire[`InstAddrBus] pc_i,             \n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/trap.v:27: Define or directive not defined: \'`InstBus\'\n    input wire[`InstBus] inst_i,               \n               ^~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/trap.v:28: Define or directive not defined: \'`MemAddrBus\'\n    input wire [`MemAddrBus] mem_addr_i,       \n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/trap.v:34: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input wire[`InstAddrBus] pc_n_i,           \n    ^~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/trap.v:34: Define or directive not defined: \'`InstAddrBus\'\n    input wire[`InstAddrBus] pc_n_i,           \n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/trap.v:35: Define or directive not defined: \'`InstAddrBus\'\n    output reg[`InstAddrBus] pc_n_o,           \n               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/trap.v:39: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg trap_in_o \n    ^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/trap.v:51: Define or directive not defined: \'`RegBus\'\nreg [`RegBus] mcause_gen; \n     ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/trap.v:51: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg [`RegBus] mcause_gen; \n            ^\n%Error: data/full_repos/permissive/507312280/rtl/core/trap.v:52: Define or directive not defined: \'`RegBus\'\nreg [`RegBus] mtval_gen; \n     ^~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/trap.v:52: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg [`RegBus] mtval_gen; \n            ^\n%Error: data/full_repos/permissive/507312280/rtl/core/trap.v:104: syntax error, unexpected always\nalways @(posedge clk or negedge rst_n) begin \n^~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/trap.v:192: Define or directive not defined: \'`CSR_MSTATUS\'\n            csr_addr_o=`CSR_MSTATUS;\n                       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/trap.v:198: Define or directive not defined: \'`CSR_MEPC\'\n            csr_addr_o=`CSR_MEPC;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/trap.v:204: Define or directive not defined: \'`CSR_MCAUSE\'\n            csr_addr_o=`CSR_MCAUSE;\n                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/trap.v:210: Define or directive not defined: \'`CSR_MTVAL\'\n            csr_addr_o=`CSR_MTVAL;\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/507312280/rtl/core/trap.v:216: Define or directive not defined: \'`CSR_MTVEC\'\n            csr_addr_o=`CSR_MTVEC;\n                       ^~~~~~~~~~\n%Error: Exiting due to 32 error(s)\n'
module trap (
    input clk,
    input rst_n,


    input wire[`RegBus] csr_rdata_i,
    output reg[`RegBus] csr_wdata_o,
    output reg csr_we_o,
    output reg[`CsrAddrBus] csr_addr_o,


    input wire ecall_i,
    input wire ebreak_i,
    input wire inst_err_i,
    input wire mem_err_i,


    input wire ex_trap_valid_i,
    input wire tcmp_trap_valid_i,
    input wire soft_trap_valid_i,

    input wire mstatus_MIE3,
    input wire wfi_i,

    input wire[`InstAddrBus] pc_i,
    input wire[`InstBus] inst_i,
    input wire [`MemAddrBus] mem_addr_i,


    output reg ex_trap_ready_o  ,


    input wire[`InstAddrBus] pc_n_i,
    output reg[`InstAddrBus] pc_n_o,
    output reg trap_jump_o,


    output reg trap_in_o

);

reg pex_trap_r;
reg ptcmp_trap_r;
reg psoft_trap_r;


wire trap_exception_en = ecall_i | ebreak_i | inst_err_i | mem_err_i;
wire trap_interrupt_en = ex_trap_valid_i | tcmp_trap_valid_i | soft_trap_valid_i;

reg [`RegBus] mcause_gen;
reg [`RegBus] mtval_gen;

always @(*) begin
    ex_trap_ready_o = 0;
    if(trap_interrupt_en) begin
        mcause_gen[31] = 1'b1;
        if(pex_trap_r) begin
            mcause_gen[30:0] = 31'd11;
            ex_trap_ready_o  = 1;
        end
        else
            if(ptcmp_trap_r) begin
                mcause_gen[30:0] = 7;
            end
            else
                if(psoft_trap_r) begin
                    mcause_gen[30:0] = 31'd3;
                end
                else begin
                    mcause_gen[30:0] = 31'd0;
                end
    end
    else begin
        mcause_gen[31] = 1'b0;
        mcause_gen[30:0] = 31'hffff;
    end
end

always @(*) begin
    if(trap_exception_en)
        if(inst_err_i)
            mtval_gen = inst_i;
        else
            mtval_gen = mem_addr_i;
    else
        mtval_gen = 0;
    
end




reg [2:0]sta_n,sta_p;

localparam IDLE = 3'd0;
localparam SWFI = 3'd1;
localparam CMIE = 3'd2;
localparam WRPC = 3'd3;
localparam WMCA = 3'd4;
localparam RTVA = 3'd5;
localparam JVPC = 3'd6;

always @(posedge clk or negedge rst_n) begin
    if (~rst_n)
        sta_p <= IDLE;
    else
        sta_p <= sta_n;
end

always @(*) begin
    case (sta_p)
        IDLE: begin
            if(trap_exception_en)
                sta_n = CMIE;
            else
                if(mstatus_MIE3)
                    if(trap_interrupt_en)
                        sta_n = CMIE;
                    else
                        if(wfi_i)
                            sta_n = SWFI;
                        else
                            sta_n = IDLE;
                else
                    if(wfi_i)
                        sta_n = SWFI;
                    else
                        sta_n = IDLE;
        end
        SWFI: begin
            if(trap_exception_en)
                sta_n = CMIE;
            else
                if(mstatus_MIE3)
                    if(trap_interrupt_en)
                        sta_n = CMIE;
                    else
                        sta_n = SWFI;
                else
                    if(trap_interrupt_en)
                        sta_n = IDLE;
                    else
                        sta_n = SWFI;
        end
        CMIE: begin
            sta_n = WRPC;
        end
        WRPC: begin
            sta_n = WMCA;
        end
        WMCA: begin
            sta_n = RTVA;
        end
        RTVA: begin
            sta_n = JVPC;
        end
        JVPC: begin
            sta_n = IDLE;
        end
        default: sta_n = IDLE;
    endcase
end

always @(*) begin
    csr_wdata_o=0;
    csr_we_o=0;
    csr_addr_o=0;
    trap_in_o=0;
    trap_jump_o=0;
    pc_n_o=pc_n_i;
    case (sta_p)
        IDLE: begin
            if(trap_exception_en)
                trap_in_o=1;
            else
                if(mstatus_MIE3)
                    if(trap_interrupt_en)
                        trap_in_o=1;
                    else
                        trap_in_o=0;
                else
                    trap_in_o=0;
        end
        SWFI: begin
            trap_in_o=1;
        end
        CMIE: begin
            trap_in_o=1;
            csr_wdata_o={csr_rdata_i[31:8],csr_rdata_i[3],csr_rdata_i[6:4],1'b0,csr_rdata_i[2:0]};
            csr_we_o=1;
            csr_addr_o=`CSR_MSTATUS;
        end
        WRPC: begin
            trap_in_o=1;
            csr_wdata_o=pc_i;
            csr_we_o=1;
            csr_addr_o=`CSR_MEPC;
        end
        WMCA: begin
            trap_in_o=1;
            csr_wdata_o=mcause_gen;
            csr_we_o=1;
            csr_addr_o=`CSR_MCAUSE;
        end
        RTVA: begin
            trap_in_o=1;
            csr_wdata_o=mtval_gen;
            csr_we_o=1;
            csr_addr_o=`CSR_MTVAL;
        end
        JVPC: begin
            trap_in_o=1;
            trap_jump_o=1;
            csr_we_o=0;
            csr_addr_o=`CSR_MTVEC;
            pc_n_o={csr_rdata_i[31:2],2'b00};
        end
        default: ;
    endcase
end




always @(posedge clk) begin
    if(sta_n == CMIE) begin
        pex_trap_r   <= ex_trap_valid_i   ;
        ptcmp_trap_r <= tcmp_trap_valid_i ;
        psoft_trap_r <= soft_trap_valid_i ;
    end
    else begin
        
    end
end



endmodule
module trap (
    input clk,
    input rst_n,


    input wire[`RegBus] csr_rdata_i,
    output reg[`RegBus] csr_wdata_o,
    output reg csr_we_o,
    output reg[`CsrAddrBus] csr_addr_o,


    input wire ecall_i,
    input wire ebreak_i,
    input wire inst_err_i,
    input wire mem_err_i,


    input wire ex_trap_valid_i,
    input wire tcmp_trap_valid_i,
    input wire soft_trap_valid_i,

    input wire mstatus_MIE3,
    input wire wfi_i,

    input wire[`InstAddrBus] pc_i,
    input wire[`InstBus] inst_i,
    input wire [`MemAddrBus] mem_addr_i,


    output reg ex_trap_ready_o  ,


    input wire[`InstAddrBus] pc_n_i,
    output reg[`InstAddrBus] pc_n_o,
    output reg trap_jump_o,


    output reg trap_in_o

);


reg pex_trap_r;
reg ptcmp_trap_r;
reg psoft_trap_r;


wire trap_exception_en = ecall_i | ebreak_i | inst_err_i | mem_err_i;
wire trap_interrupt_en = ex_trap_valid_i | tcmp_trap_valid_i | soft_trap_valid_i;

reg [`RegBus] mcause_gen;
reg [`RegBus] mtval_gen;

always @(*) begin
    ex_trap_ready_o = 0;
    if(trap_interrupt_en) begin
        mcause_gen[31] = 1'b1;
        if(pex_trap_r) begin
            mcause_gen[30:0] = 31'd11;
            ex_trap_ready_o  = 1;
        end
        else
            if(ptcmp_trap_r) begin
                mcause_gen[30:0] = 7;
            end
            else
                if(psoft_trap_r) begin
                    mcause_gen[30:0] = 31'd3;
                end
                else begin
                    mcause_gen[30:0] = 31'd0;
                end
    end
    else begin
        mcause_gen[31] = 1'b0;
        mcause_gen[30:0] = 31'hffff;
    end
end

always @(*) begin
    if(trap_exception_en)
        if(inst_err_i)
            mtval_gen = inst_i;
        else
            mtval_gen = mem_addr_i;
    else
        mtval_gen = 0;
    
end




reg [2:0]sta_n,sta_p;

localparam IDLE = 3'd0;
localparam SWFI = 3'd1;
localparam CMIE = 3'd2;
localparam WRPC = 3'd3;
localparam WMCA = 3'd4;
localparam RTVA = 3'd5;
localparam JVPC = 3'd6;

always @(posedge clk or negedge rst_n) begin
    if (~rst_n)
        sta_p <= IDLE;
    else
        sta_p <= sta_n;
end

always @(*) begin
    case (sta_p)
        IDLE: begin
            if(trap_exception_en)
                sta_n = CMIE;
            else
                if(mstatus_MIE3)
                    if(trap_interrupt_en)
                        sta_n = CMIE;
                    else
                        if(wfi_i)
                            sta_n = SWFI;
                        else
                            sta_n = IDLE;
                else
                    if(wfi_i)
                        sta_n = SWFI;
                    else
                        sta_n = IDLE;
        end
        SWFI: begin
            if(trap_exception_en)
                sta_n = CMIE;
            else
                if(mstatus_MIE3)
                    if(trap_interrupt_en)
                        sta_n = CMIE;
                    else
                        sta_n = SWFI;
                else
                    if(trap_interrupt_en)
                        sta_n = IDLE;
                    else
                        sta_n = SWFI;
        end
        CMIE: begin
            sta_n = WRPC;
        end
        WRPC: begin
            sta_n = WMCA;
        end
        WMCA: begin
            sta_n = RTVA;
        end
        RTVA: begin
            sta_n = JVPC;
        end
        JVPC: begin
            sta_n = IDLE;
        end
        default: sta_n = IDLE;
    endcase
end

always @(*) begin
    csr_wdata_o=0;
    csr_we_o=0;
    csr_addr_o=0;
    trap_in_o=0;
    trap_jump_o=0;
    pc_n_o=pc_n_i;
    case (sta_p)
        IDLE: begin
            if(trap_exception_en)
                trap_in_o=1;
            else
                if(mstatus_MIE3)
                    if(trap_interrupt_en)
                        trap_in_o=1;
                    else
                        trap_in_o=0;
                else
                    trap_in_o=0;
        end
        SWFI: begin
            trap_in_o=1;
        end
        CMIE: begin
            trap_in_o=1;
            csr_wdata_o={csr_rdata_i[31:8],csr_rdata_i[3],csr_rdata_i[6:4],1'b0,csr_rdata_i[2:0]};
            csr_we_o=1;
            csr_addr_o=`CSR_MSTATUS;
        end
        WRPC: begin
            trap_in_o=1;
            csr_wdata_o=pc_i;
            csr_we_o=1;
            csr_addr_o=`CSR_MEPC;
        end
        WMCA: begin
            trap_in_o=1;
            csr_wdata_o=mcause_gen;
            csr_we_o=1;
            csr_addr_o=`CSR_MCAUSE;
        end
        RTVA: begin
            trap_in_o=1;
            csr_wdata_o=mtval_gen;
            csr_we_o=1;
            csr_addr_o=`CSR_MTVAL;
        end
        JVPC: begin
            trap_in_o=1;
            trap_jump_o=1;
            csr_we_o=0;
            csr_addr_o=`CSR_MTVEC;
            pc_n_o={csr_rdata_i[31:2],2'b00};
        end
        default: ;
    endcase
end




always @(posedge clk) begin
    if(sta_n == CMIE) begin
        pex_trap_r   <= ex_trap_valid_i   ;
        ptcmp_trap_r <= tcmp_trap_valid_i ;
        psoft_trap_r <= soft_trap_valid_i ;
    end
    else begin
        
    end
end



endmodule