data/full_repos/permissive/486598419/6.6/pcreg.v
data/verilator_xmls/c7b7a878-32e2-4bfe-be0f-b2beda5ae8b5.xml
module Asynchronous_D_FF_Ena
(
    input CLK,
    input D,
    input RST_n,
    input iEna,
    output reg Q1
);
always@(posedge RST_n or posedge CLK)
    if(RST_n==1)
        begin
        Q1<=0;
        end
    else 
        if(iEna==1)
        begin
        Q1<=D;
        end
endmodule
module Asynchronous_D_FF_Ena
(
    input CLK,
    input D,
    input RST_n,
    input iEna,
    output reg Q1
);

always@(posedge RST_n or posedge CLK)
    if(RST_n==1)
        begin
        Q1<=0;
        end
    else 
        if(iEna==1)
        begin
        Q1<=D;
        end
endmodule