data/full_repos/permissive/50693363/riffa_builder/src/fpga/riffa_alite_m.v
1: b'%Warning-WIDTH: data/full_repos/permissive/50693363/riffa_builder/src/fpga/riffa_alite_m.v:232: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                              : ... In instance riffa_alite_m\n                        data_cnt <= 3\'b0;\n                                 ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/50693363/riffa_builder/src/fpga/riffa_alite_m.v:244: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'data_cnt\' generates 4 bits.\n                                                                                              : ... In instance riffa_alite_m\n                            if (data_cnt == i)\n                                         ^~\n%Warning-WIDTH: data/full_repos/permissive/50693363/riffa_builder/src/fpga/riffa_alite_m.v:247: Operator EQ expects 32 or 8 bits on the LHS, but LHS\'s VARREF \'data_cnt\' generates 4 bits.\n                                                                                              : ... In instance riffa_alite_m\n                        if (data_cnt == C_RX_DATA_CNT - 1)\n                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/50693363/riffa_builder/src/fpga/riffa_alite_m.v:259: Operator EQ expects 32 bits on the LHS, but LHS\'s SEL generates 16 bits.\n                                                                                              : ... In instance riffa_alite_m\n                        if (rx_data[C_RX_BIT_HEAD +: 16] == 32\'h55aa)\n                                                         ^~\n%Warning-WIDTH: data/full_repos/permissive/50693363/riffa_builder/src/fpga/riffa_alite_m.v:387: Operator ASSIGNDLY expects 256 bits on the Assign RHS, but Assign RHS\'s SEL generates 128 bits.\n                                                                                              : ... In instance riffa_alite_m\n                    tx_data <= tx_data[(C_TX_DATA_WORD_NUM*32-1)\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/50693363/riffa_builder/src/fpga/riffa_alite_m.v:397: Operator ASSIGNDLY expects 256 bits on the Assign RHS, but Assign RHS\'s SEL generates 128 bits.\n                                                                                              : ... In instance riffa_alite_m\n                        tx_data <= tx_data[(C_TX_DATA_WORD_NUM*32-1)\n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/50693363/riffa_builder/src/fpga/riffa_alite_m.v:400: Operator EQ expects 32 or 8 bits on the LHS, but LHS\'s VARREF \'data_cnt\' generates 4 bits.\n                                                                                              : ... In instance riffa_alite_m\n                        if (data_cnt == C_TX_DATA_CNT - 1)\n                                     ^~\n%Error: Exiting due to 7 warning(s)\n'
function integer addr_bits_32;
	input [31:0] v;
	reg [31:0] value;
	begin
		value = v;
		if (value <= 32) begin
			addr_bits_32 = 1;
		end
		else begin
			value = value-1;
			for (addr_bits_32=0; value>0; addr_bits_32=addr_bits_32+1)
				value = value>>1;
		    addr_bits_32 = addr_bits_32 - 5;
		end
	end
endfunction
function integer addr_bits_32;

	input [31:0] v;
	reg [31:0] value;
	begin
		value = v;
		if (value <= 32) begin
			addr_bits_32 = 1;
		end
		else begin
			value = value-1;
			for (addr_bits_32=0; value>0; addr_bits_32=addr_bits_32+1)
				value = value>>1;
		    addr_bits_32 = addr_bits_32 - 5;
		end
	end
endfunction