data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_findfirst.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_findfirst.v:29: Cannot find include file: sys.h\n`include "sys.h" // system level definition file which contains the  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_findfirst.v:31: Cannot find include file: iop.h\n`include        "iop.h" \n                ^~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module iobdg_findfirst (

   vec_out, 

   vec_in
   );



   parameter VEC_WIDTH = 64;
   



   input [VEC_WIDTH-1:0]     vec_in;
   output [VEC_WIDTH-1:0]    vec_out;
   reg [VEC_WIDTH-1:0]       vec_out;
   
   reg [VEC_WIDTH-1:0]       selected;
   
   integer 		      i;

   



   always @(vec_in or selected)
     begin
     	selected[0] = vec_in[0];
	vec_out[0] = vec_in[0];
	for (i=1; i<VEC_WIDTH; i=i+1)
	  begin
	     selected[i] = vec_in[i] | selected[i-1];
	     vec_out[i] = vec_in[i] & ~selected[i-1];
	  end
     end

endmodule
module iobdg_findfirst (

   vec_out, 

   vec_in
   );




   parameter VEC_WIDTH = 64;
   



   input [VEC_WIDTH-1:0]     vec_in;
   output [VEC_WIDTH-1:0]    vec_out;
   reg [VEC_WIDTH-1:0]       vec_out;
   
   reg [VEC_WIDTH-1:0]       selected;
   
   integer 		      i;

   



   always @(vec_in or selected)
     begin
     	selected[0] = vec_in[0];
	vec_out[0] = vec_in[0];
	for (i=1; i<VEC_WIDTH; i=i+1)
	  begin
	     selected[i] = vec_in[i] | selected[i-1];
	     vec_out[i] = vec_in[i] & ~selected[i-1];
	  end
     end

endmodule