data/full_repos/permissive/429421342/files/renamed_pixelTop_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/429421342/files/renamed_pixelTop_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n   always #clk_period CLK=~CLK;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/429421342/files/renamed_pixelTop_tb.v:124: Unsupported: Ignoring delay on this delayed statement.\n        #clk_period  RESET=0;\n        ^\n%Error: data/full_repos/permissive/429421342/files/renamed_pixelTop_tb.v:126: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("test_shit_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/429421342/files/renamed_pixelTop_tb.v:127: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0,test_shit_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/429421342/files/renamed_pixelTop_tb.v:129: Unsupported: Ignoring delay on this delayed statement.\n        #sim_end\n        ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_shit_tb;




   logic CLK = 0;
   logic RESET = 0;
   parameter integer clk_period = 500;
   parameter integer sim_end = clk_period*2400;
   always #clk_period CLK=~CLK;




   




 


   wire [3:0] READ;
   tri[7:0] pixData;


   pixelTop entire_sensor(RESET, CLK, pixData, READ);




   




   logic [7:0] pixelDataOut1;
   logic [7:0] pixelDataOut2;
   logic [7:0] pixelDataOut3;
   logic [7:0] pixelDataOut4;

   always_ff @(posedge CLK or posedge RESET) begin
      if(RESET) begin
         pixelDataOut1 = 0;
         pixelDataOut2 = 0;
         pixelDataOut3 = 0;
         pixelDataOut4 = 0;
      end
      else begin
         if(READ[0])
           pixelDataOut1 <= pixData;
         if(READ[1])
           pixelDataOut2 <= pixData;
         if(READ[2])
           pixelDataOut3 <= pixData;
         if(READ[3])
           pixelDataOut4 <= pixData;
      end
   end




   initial
     begin
        RESET = 1;

        #clk_period  RESET=0;

        $dumpfile("test_shit_tb.vcd");
        $dumpvars(0,test_shit_tb);

        #sim_end
          $stop;

     end

endmodule
module test_shit_tb;





   logic CLK = 0;
   logic RESET = 0;
   parameter integer clk_period = 500;
   parameter integer sim_end = clk_period*2400;
   always #clk_period CLK=~CLK;




   




 


   wire [3:0] READ;
   tri[7:0] pixData;


   pixelTop entire_sensor(RESET, CLK, pixData, READ);




   




   logic [7:0] pixelDataOut1;
   logic [7:0] pixelDataOut2;
   logic [7:0] pixelDataOut3;
   logic [7:0] pixelDataOut4;

   always_ff @(posedge CLK or posedge RESET) begin
      if(RESET) begin
         pixelDataOut1 = 0;
         pixelDataOut2 = 0;
         pixelDataOut3 = 0;
         pixelDataOut4 = 0;
      end
      else begin
         if(READ[0])
           pixelDataOut1 <= pixData;
         if(READ[1])
           pixelDataOut2 <= pixData;
         if(READ[2])
           pixelDataOut3 <= pixData;
         if(READ[3])
           pixelDataOut4 <= pixData;
      end
   end




   initial
     begin
        RESET = 1;

        #clk_period  RESET=0;

        $dumpfile("test_shit_tb.vcd");
        $dumpvars(0,test_shit_tb);

        #sim_end
          $stop;

     end

endmodule