data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:41: Unsupported: Ignoring delay on this delayed statement.\n            #5;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:43: Unsupported: Ignoring delay on this delayed statement.\n            #5;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:65: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:72: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:74: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:82: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:88: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:95: Unsupported: Ignoring delay on this delayed statement.\n        #20; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:97: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:104: Unsupported: Ignoring delay on this delayed statement.\n        #20; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:106: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:113: Unsupported: Ignoring delay on this delayed statement.\n        #20; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:115: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:122: Unsupported: Ignoring delay on this delayed statement.\n        #20; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:124: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:131: Unsupported: Ignoring delay on this delayed statement.\n        #20; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:133: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:140: Unsupported: Ignoring delay on this delayed statement.\n        #20; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:144: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:153: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:155: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:164: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:166: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:175: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:177: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:186: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:188: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:197: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:201: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:209: Unsupported: Ignoring delay on this delayed statement.\n        #15;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:211: Unsupported: Ignoring delay on this delayed statement.\n        #15;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:213: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:221: Unsupported: Ignoring delay on this delayed statement.\n        #15;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:223: Unsupported: Ignoring delay on this delayed statement.\n        #15;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:225: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:233: Unsupported: Ignoring delay on this delayed statement.\n        #15;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:235: Unsupported: Ignoring delay on this delayed statement.\n        #15;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:239: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:246: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:248: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:255: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:257: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:264: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:266: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:273: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:275: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:282: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:284: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:291: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:293: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:300: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:302: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:309: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:311: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:318: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:322: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:328: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:330: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:336: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:338: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:344: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:346: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:352: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:354: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:360: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:362: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:368: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:370: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:376: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:378: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:384: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:386: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:392: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:394: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:400: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:403: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:409: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:411: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:417: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ControlUnit_TB.v:29: Cannot find file containing module: \'ControlUnit\'\n    ControlUnit dut(\n    ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new,data/full_repos/permissive/433174928/ControlUnit\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new,data/full_repos/permissive/433174928/ControlUnit.v\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new,data/full_repos/permissive/433174928/ControlUnit.sv\n             ControlUnit\n             ControlUnit.v\n             ControlUnit.sv\n             obj_dir/ControlUnit\n             obj_dir/ControlUnit.v\n             obj_dir/ControlUnit.sv\n%Error: Exiting due to 1 error(s), 84 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ControlUnit_TB(

    );

    reg clk=0;
    reg rstn=0;
    reg [31:0] instruction;
    reg bc_out=0;
    

    wire pc_we;
    wire imem_rd;
    wire rf_we;
    wire [2:0] imm_op;
    wire [2:0] data_op;
    wire [2:0] bc_op;
    wire [3:0] alu_op;
    wire [3:0] dmem_we;
    wire dmem_rd;
    wire pc_mux;
    wire rfile_mux;
    wire alu_mux1;
    wire alu_mux2;
    wire [1:0] op_mux;
    
    ControlUnit dut(
    .clk(clk), .rstn(rstn), .instruction(instruction), .bc_out(bc_out), 
    .pc_we(pc_we), .imem_rd(imem_rd), .rf_we(rf_we), .imm_op(imm_op), .data_op(data_op), 
    .bc_op(bc_op), .alu_op(alu_op), .dmem_we(dmem_we), .dmem_rd(dmem_rd), .pc_mux(pc_mux),
    .rfile_mux(rfile_mux), .alu_mux1(alu_mux1), .alu_mux2(alu_mux2), .op_mux(op_mux)
    );
    
    initial begin: CLK_GEN
        #5;
        rstn <=1;
        forever begin
            clk <=0;
            #5;
            clk <=1;
            #5;
        end
    end
    
    initial begin 
    
        instruction <= 32'h000012b7;
        #10;
        if(op_mux !=2'd2) $fatal("Expected output mux select line not received for LUI");
        if(imm_op !=3'd4) $fatal("Expected immediate extension opcode not received for LUI");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for LUI");
        #20;
        instruction <= 32'h00110297;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for AUIPC");
        if(imm_op !=3'd4) $fatal("Expected immediate extension opcode not received for AUIPC");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for AUIPC");
        if(alu_mux1 != 1) $fatal("Expected ALU input data1 not received for AUIPC");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for AUIPC");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for AUIPC");
        #20;
        instruction <= 32'h0100016f;
        #10;
        if(imm_op !=3'd0) $fatal("Expected immediate extension opcode not received for JAL");
        if(pc_mux !=1) $fatal("Expected PC update select line not received for JAL");
        if(alu_mux1 != 1) $fatal("Expected ALU input data1 not received for JAL");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for JAL");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for JAL");
        if(rfile_mux != 1) $fatal("Expected RF destination select line not received for JAL");
        #20;
        instruction <= 32'h00008067;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for JALR");
        if(imm_op !=3'd1) $fatal("Expected immediate extension opcode not received for JALR");
        if(pc_mux !=1) $fatal("Expected PC update select line not received for JALR");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for JALR");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for JALR");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for JALR");
        if(rfile_mux != 1) $fatal("Expected RF destination select line not received for JALR");
        #20;
        

        

        instruction <= 32'b00000000000100010000011101100011;
        #10;
        if(imm_op !=3'd2) $fatal("Expected immediate extension opcode not received for Branch");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for Branch");
        if(alu_mux1 != 1) $fatal("Expected ALU input data1 not received for Branch");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for Branch");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for Branch");
        if(bc_op != 3'd0) $fatal ("Expected branch comparator opcode not received for BEQ");
        #20; 
        instruction <= 32'b00000000000100010001011101100011;
        #10;
        if(imm_op !=3'd2) $fatal("Expected immediate extension opcode not received for Branch");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for Branch");
        if(alu_mux1 != 1) $fatal("Expected ALU input data1 not received for Branch");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for Branch");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for Branch");
        if(bc_op != 3'd1) $fatal ("Expected branch comparator opcode not received for BNE");
        #20; 
        instruction <= 32'b00000000000100010100011101100011;
        #10;
        if(imm_op !=3'd2) $fatal("Expected immediate extension opcode not received for Branch");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for Branch");
        if(alu_mux1 != 1) $fatal("Expected ALU input data1 not received for Branch");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for Branch");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for Branch");
        if(bc_op != 3'd4) $fatal ("Expected branch comparator opcode not received for BLT");
        #20; 
        instruction <= 32'b00000000000100010101011101100011;
        #10;
        if(imm_op !=3'd2) $fatal("Expected immediate extension opcode not received for Branch");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for Branch");
        if(alu_mux1 != 1) $fatal("Expected ALU input data1 not received for Branch");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for Branch");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for Branch");
        if(bc_op != 3'd5) $fatal ("Expected branch comparator opcode not received for BEQ");
        #20; 
        instruction <= 32'b00000000000100010110011101100011;
        #10;
        if(imm_op !=3'd2) $fatal("Expected immediate extension opcode not received for Branch");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for Branch");
        if(alu_mux1 != 1) $fatal("Expected ALU input data1 not received for Branch");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for Branch");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for Branch");
        if(bc_op != 3'd6) $fatal ("Expected branch comparator opcode not received for BEQ");
        #20; 
        instruction <= 32'b00000000000100010111011101100011;
        #10;
        if(imm_op !=3'd2) $fatal("Expected immediate extension opcode not received for Branch");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for Branch");
        if(alu_mux1 != 1) $fatal("Expected ALU input data1 not received for Branch");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for Branch");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for Branch");
        if(bc_op != 3'd7) $fatal ("Expected branch comparator opcode not received for BEQ");
        #20; 
        

        instruction <= 32'h02830283;
        #10;
        if(op_mux !=2'd1) $fatal("Expected output mux select line not received for Load");
        if(imm_op !=3'd1) $fatal("Expected immediate extension opcode not received for Load");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for Load");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for Load");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for Load");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for Load");
        if(rfile_mux != 0) $fatal("Expected RF destination select line not received for Load");
        if(data_op != 3'd0) $fatal("Expected data extension select line not received for LB");
        #30;
        instruction <= 32'h00031283;
        #10;
        if(op_mux !=2'd1) $fatal("Expected output mux select line not received for Load");
        if(imm_op !=3'd1) $fatal("Expected immediate extension opcode not received for Load");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for Load");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for Load");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for Load");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for Load");
        if(rfile_mux != 0) $fatal("Expected RF destination select line not received for Load");
        if(data_op != 3'd1) $fatal("Expected data extension select line not received for LH");
        #30;
        instruction <= 32'h02832283;
        #10;
        if(op_mux !=2'd1) $fatal("Expected output mux select line not received for Load");
        if(imm_op !=3'd1) $fatal("Expected immediate extension opcode not received for Load");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for Load");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for Load");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for Load");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for Load");
        if(rfile_mux != 0) $fatal("Expected RF destination select line not received for Load");
        if(data_op != 3'd2) $fatal("Expected data extension select line not received for LW");
        #30;
        instruction <= 32'h02834283;
        #10;
        if(op_mux !=2'd1) $fatal("Expected output mux select line not received for Load");
        if(imm_op !=3'd1) $fatal("Expected immediate extension opcode not received for Load");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for Load");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for Load");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for Load");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for Load");
        if(rfile_mux != 0) $fatal("Expected RF destination select line not received for Load");
        if(data_op != 3'd4) $fatal("Expected data extension select line not received for LBU");
        #30;
        instruction <= 32'h00035283;
        #10;
        if(op_mux !=2'd1) $fatal("Expected output mux select line not received for Load");
        if(imm_op !=3'd1) $fatal("Expected immediate extension opcode not received for Load");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for Load");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for Load");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for Load");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for Load");
        if(rfile_mux != 0) $fatal("Expected RF destination select line not received for Load");
        if(data_op != 3'd5) $fatal("Expected data extension select line not received for LHU");
        #30;
        

        instruction <= 32'h00128023;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for Store");
        if(imm_op !=3'd3) $fatal("Expected immediate extension opcode not received for Store");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for Store");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for Store");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for Store");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for Store");
        if(rfile_mux != 0) $fatal("Expected RF destination select line not received for Store");
        #15;
        if(dmem_we != 4'd1) $fatal("Expected DMem write enable not received for SB");
        #15;
         instruction <= 32'h00129023;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for Store");
        if(imm_op !=3'd3) $fatal("Expected immediate extension opcode not received for Store");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for Store");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for Store");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for Store");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for Store");
        if(rfile_mux != 0) $fatal("Expected RF destination select line not received for Store");
        #15;
        if(dmem_we != 4'd3) $fatal("Expected DMem write enable not received for SH");
        #15;
         instruction <= 32'h0012a023;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for Store");
        if(imm_op !=3'd3) $fatal("Expected immediate extension opcode not received for Store");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for Store");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for Store");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for Store");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for Store");
        if(rfile_mux != 0) $fatal("Expected RF destination select line not received for Store");
        #15;
        if(dmem_we != 4'b1111) $fatal("Expected DMem write enable not received for SW");
        #15;
        

        instruction <= 32'h00108293;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for I-type Arithmetic");
        if(imm_op !=3'd1) $fatal("Expected immediate extension opcode not received for I-type Arithmetic");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for I-type Arithmetic");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for I-type Arithmetic");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for I-type Arithmetic");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for ADDI");
        #20;
        instruction <= 32'h0020a293;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for I-type Arithmetic");
        if(imm_op !=3'd1) $fatal("Expected immediate extension opcode not received for I-type Arithmetic");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for I-type Arithmetic");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for I-type Arithmetic");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for I-type Arithmetic");
        if(alu_op != 4'd2) $fatal("Expected ALU opcode not received for SLTI");
        #20;
        instruction <= 32'h0020b293;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for I-type Arithmetic");
        if(imm_op !=3'd1) $fatal("Expected immediate extension opcode not received for I-type Arithmetic");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for I-type Arithmetic");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for I-type Arithmetic");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for I-type Arithmetic");
        if(alu_op != 4'd3) $fatal("Expected ALU opcode not received for SLTIU");
        #20;
        instruction <= 32'h0202c293;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for I-type Arithmetic");
        if(imm_op !=3'd1) $fatal("Expected immediate extension opcode not received for I-type Arithmetic");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for I-type Arithmetic");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for I-type Arithmetic");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for I-type Arithmetic");
        if(alu_op != 4'd4) $fatal("Expected ALU opcode not received for XORI");
        #20;
        instruction <= 32'h0102e093;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for I-type Arithmetic");
        if(imm_op !=3'd1) $fatal("Expected immediate extension opcode not received for I-type Arithmetic");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for I-type Arithmetic");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for I-type Arithmetic");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for I-type Arithmetic");
        if(alu_op != 4'd6) $fatal("Expected ALU opcode not received for ORI");
        #20;
        instruction <= 32'h0042f293;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for I-type Arithmetic");
        if(imm_op !=3'd1) $fatal("Expected immediate extension opcode not received for I-type Arithmetic");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for I-type Arithmetic");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for I-type Arithmetic");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for I-type Arithmetic");
        if(alu_op != 4'd7) $fatal("Expected ALU opcode not received for ANDI");
        #20;
         instruction <= 32'h00109093;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for I-type Arithmetic");
        if(imm_op !=3'd1) $fatal("Expected immediate extension opcode not received for I-type Arithmetic");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for I-type Arithmetic");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for I-type Arithmetic");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for I-type Arithmetic");
        if(alu_op != 4'd1) $fatal("Expected ALU opcode not received for SLLI");
        #20;
         instruction <= 32'h0010d093;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for I-type Arithmetic");
        if(imm_op !=3'd1) $fatal("Expected immediate extension opcode not received for I-type Arithmetic");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for I-type Arithmetic");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for I-type Arithmetic");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for I-type Arithmetic");
        if(alu_op != 4'd5) $fatal("Expected ALU opcode not received for SRLI");
        #20;
         instruction <= 32'h4010d093;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for I-type Arithmetic");
        if(imm_op !=3'd1) $fatal("Expected immediate extension opcode not received for I-type Arithmetic");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for I-type Arithmetic");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for I-type Arithmetic");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for I-type Arithmetic");
        if(alu_op != 4'b1101) $fatal("Expected ALU opcode not received for SRAI");
        #20;
        

        instruction <= 32'h003100b3;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for R-type");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for R-type");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for R-type");
        if(alu_mux2 != 1) $fatal("Expected ALU input data2 not received for R-type");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for ADD");
        #20;
        instruction <= 32'h403100b3;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for R-type");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for R-type");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for R-type");
        if(alu_mux2 != 1) $fatal("Expected ALU input data2 not received for R-type");
        if(alu_op != 4'd8) $fatal("Expected ALU opcode not received for SUB");
        #20;
        instruction <= 32'h003290b3;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for R-type");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for R-type");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for R-type");
        if(alu_mux2 != 1) $fatal("Expected ALU input data2 not received for R-type");
        if(alu_op != 4'd1) $fatal("Expected ALU opcode not received for SLL");
        #20;
        instruction <= 32'h0032a0b3;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for R-type");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for R-type");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for R-type");
        if(alu_mux2 != 1) $fatal("Expected ALU input data2 not received for R-type");
        if(alu_op != 4'd2) $fatal("Expected ALU opcode not received for SLT");
        #20;
        instruction <= 32'h0032b0b3;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for R-type");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for R-type");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for R-type");
        if(alu_mux2 != 1) $fatal("Expected ALU input data2 not received for R-type");
        if(alu_op != 4'd3) $fatal("Expected ALU opcode not received for SLTU");
        #20;
        instruction <= 32'h0032c0b3;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for R-type");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for R-type");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for R-type");
        if(alu_mux2 != 1) $fatal("Expected ALU input data2 not received for R-type");
        if(alu_op != 4'd4) $fatal("Expected ALU opcode not received for XOR");
        #20;
        instruction <= 32'h0032d0b3;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for R-type");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for R-type");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for R-type");
        if(alu_mux2 != 1) $fatal("Expected ALU input data2 not received for R-type");
        if(alu_op != 4'd5) $fatal("Expected ALU opcode not received for SRL");
        #20;
        instruction <= 32'h4032d0b3;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for R-type");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for R-type");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for R-type");
        if(alu_mux2 != 1) $fatal("Expected ALU input data2 not received for R-type");
        if(alu_op != 4'b1101) $fatal("Expected ALU opcode not received for SRA");
        #20;
        instruction <= 32'h0032e0b3;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for R-type");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for R-type");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for R-type");
        if(alu_mux2 != 1) $fatal("Expected ALU input data2 not received for R-type");
        if(alu_op != 4'd6) $fatal("Expected ALU opcode not received for OR");
        #20;
        instruction <= 32'h0032f0b3;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for R-type");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for R-type");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for R-type");
        if(alu_mux2 != 1) $fatal("Expected ALU input data2 not received for R-type");
        if(alu_op != 4'd7) $fatal("Expected ALU opcode not received for AND");
        #20;
        
        instruction <= 32'h00000073;
        #20;
        if(imem_rd !=0) $fatal("Expected IMem read enable not received for Halt instruction");
        if(pc_we !=0) $fatal("Expected PC write enable not received for Halt instruction");
        if(rf_we != 0) $fatal("Expected RF write enable not received for Halt instruction");
        if(dmem_rd != 0) $fatal("Expected DMem read enable not received for Halt instruction");
        if(dmem_we != 4'd0) $fatal("Expected DMem write enable not received for Halt instruction");
        #20;
        instruction <= 32'h00100073;
        #20;
        if(imem_rd !=0) $fatal("Expected IMem read enable not received for Halt instruction");
        if(pc_we !=0) $fatal("Expected PC write enable not received for Halt instruction");
        if(rf_we != 0) $fatal("Expected RF write enable not received for Halt instruction");
        if(dmem_rd != 0) $fatal("Expected DMem read enable not received for Halt instruction");
        if(dmem_we != 4'd0) $fatal("Expected DMem write enable not received for Halt instruction");
        #20;
        
        $display("All test cases passed");
        $finish;
    end
    
endmodule
module ControlUnit_TB(

    );


    reg clk=0;
    reg rstn=0;
    reg [31:0] instruction;
    reg bc_out=0;
    

    wire pc_we;
    wire imem_rd;
    wire rf_we;
    wire [2:0] imm_op;
    wire [2:0] data_op;
    wire [2:0] bc_op;
    wire [3:0] alu_op;
    wire [3:0] dmem_we;
    wire dmem_rd;
    wire pc_mux;
    wire rfile_mux;
    wire alu_mux1;
    wire alu_mux2;
    wire [1:0] op_mux;
    
    ControlUnit dut(
    .clk(clk), .rstn(rstn), .instruction(instruction), .bc_out(bc_out), 
    .pc_we(pc_we), .imem_rd(imem_rd), .rf_we(rf_we), .imm_op(imm_op), .data_op(data_op), 
    .bc_op(bc_op), .alu_op(alu_op), .dmem_we(dmem_we), .dmem_rd(dmem_rd), .pc_mux(pc_mux),
    .rfile_mux(rfile_mux), .alu_mux1(alu_mux1), .alu_mux2(alu_mux2), .op_mux(op_mux)
    );
    
    initial begin: CLK_GEN
        #5;
        rstn <=1;
        forever begin
            clk <=0;
            #5;
            clk <=1;
            #5;
        end
    end
    
    initial begin 
    
        instruction <= 32'h000012b7;
        #10;
        if(op_mux !=2'd2) $fatal("Expected output mux select line not received for LUI");
        if(imm_op !=3'd4) $fatal("Expected immediate extension opcode not received for LUI");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for LUI");
        #20;
        instruction <= 32'h00110297;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for AUIPC");
        if(imm_op !=3'd4) $fatal("Expected immediate extension opcode not received for AUIPC");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for AUIPC");
        if(alu_mux1 != 1) $fatal("Expected ALU input data1 not received for AUIPC");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for AUIPC");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for AUIPC");
        #20;
        instruction <= 32'h0100016f;
        #10;
        if(imm_op !=3'd0) $fatal("Expected immediate extension opcode not received for JAL");
        if(pc_mux !=1) $fatal("Expected PC update select line not received for JAL");
        if(alu_mux1 != 1) $fatal("Expected ALU input data1 not received for JAL");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for JAL");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for JAL");
        if(rfile_mux != 1) $fatal("Expected RF destination select line not received for JAL");
        #20;
        instruction <= 32'h00008067;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for JALR");
        if(imm_op !=3'd1) $fatal("Expected immediate extension opcode not received for JALR");
        if(pc_mux !=1) $fatal("Expected PC update select line not received for JALR");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for JALR");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for JALR");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for JALR");
        if(rfile_mux != 1) $fatal("Expected RF destination select line not received for JALR");
        #20;
        

        

        instruction <= 32'b00000000000100010000011101100011;
        #10;
        if(imm_op !=3'd2) $fatal("Expected immediate extension opcode not received for Branch");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for Branch");
        if(alu_mux1 != 1) $fatal("Expected ALU input data1 not received for Branch");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for Branch");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for Branch");
        if(bc_op != 3'd0) $fatal ("Expected branch comparator opcode not received for BEQ");
        #20; 
        instruction <= 32'b00000000000100010001011101100011;
        #10;
        if(imm_op !=3'd2) $fatal("Expected immediate extension opcode not received for Branch");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for Branch");
        if(alu_mux1 != 1) $fatal("Expected ALU input data1 not received for Branch");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for Branch");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for Branch");
        if(bc_op != 3'd1) $fatal ("Expected branch comparator opcode not received for BNE");
        #20; 
        instruction <= 32'b00000000000100010100011101100011;
        #10;
        if(imm_op !=3'd2) $fatal("Expected immediate extension opcode not received for Branch");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for Branch");
        if(alu_mux1 != 1) $fatal("Expected ALU input data1 not received for Branch");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for Branch");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for Branch");
        if(bc_op != 3'd4) $fatal ("Expected branch comparator opcode not received for BLT");
        #20; 
        instruction <= 32'b00000000000100010101011101100011;
        #10;
        if(imm_op !=3'd2) $fatal("Expected immediate extension opcode not received for Branch");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for Branch");
        if(alu_mux1 != 1) $fatal("Expected ALU input data1 not received for Branch");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for Branch");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for Branch");
        if(bc_op != 3'd5) $fatal ("Expected branch comparator opcode not received for BEQ");
        #20; 
        instruction <= 32'b00000000000100010110011101100011;
        #10;
        if(imm_op !=3'd2) $fatal("Expected immediate extension opcode not received for Branch");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for Branch");
        if(alu_mux1 != 1) $fatal("Expected ALU input data1 not received for Branch");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for Branch");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for Branch");
        if(bc_op != 3'd6) $fatal ("Expected branch comparator opcode not received for BEQ");
        #20; 
        instruction <= 32'b00000000000100010111011101100011;
        #10;
        if(imm_op !=3'd2) $fatal("Expected immediate extension opcode not received for Branch");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for Branch");
        if(alu_mux1 != 1) $fatal("Expected ALU input data1 not received for Branch");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for Branch");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for Branch");
        if(bc_op != 3'd7) $fatal ("Expected branch comparator opcode not received for BEQ");
        #20; 
        

        instruction <= 32'h02830283;
        #10;
        if(op_mux !=2'd1) $fatal("Expected output mux select line not received for Load");
        if(imm_op !=3'd1) $fatal("Expected immediate extension opcode not received for Load");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for Load");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for Load");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for Load");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for Load");
        if(rfile_mux != 0) $fatal("Expected RF destination select line not received for Load");
        if(data_op != 3'd0) $fatal("Expected data extension select line not received for LB");
        #30;
        instruction <= 32'h00031283;
        #10;
        if(op_mux !=2'd1) $fatal("Expected output mux select line not received for Load");
        if(imm_op !=3'd1) $fatal("Expected immediate extension opcode not received for Load");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for Load");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for Load");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for Load");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for Load");
        if(rfile_mux != 0) $fatal("Expected RF destination select line not received for Load");
        if(data_op != 3'd1) $fatal("Expected data extension select line not received for LH");
        #30;
        instruction <= 32'h02832283;
        #10;
        if(op_mux !=2'd1) $fatal("Expected output mux select line not received for Load");
        if(imm_op !=3'd1) $fatal("Expected immediate extension opcode not received for Load");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for Load");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for Load");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for Load");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for Load");
        if(rfile_mux != 0) $fatal("Expected RF destination select line not received for Load");
        if(data_op != 3'd2) $fatal("Expected data extension select line not received for LW");
        #30;
        instruction <= 32'h02834283;
        #10;
        if(op_mux !=2'd1) $fatal("Expected output mux select line not received for Load");
        if(imm_op !=3'd1) $fatal("Expected immediate extension opcode not received for Load");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for Load");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for Load");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for Load");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for Load");
        if(rfile_mux != 0) $fatal("Expected RF destination select line not received for Load");
        if(data_op != 3'd4) $fatal("Expected data extension select line not received for LBU");
        #30;
        instruction <= 32'h00035283;
        #10;
        if(op_mux !=2'd1) $fatal("Expected output mux select line not received for Load");
        if(imm_op !=3'd1) $fatal("Expected immediate extension opcode not received for Load");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for Load");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for Load");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for Load");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for Load");
        if(rfile_mux != 0) $fatal("Expected RF destination select line not received for Load");
        if(data_op != 3'd5) $fatal("Expected data extension select line not received for LHU");
        #30;
        

        instruction <= 32'h00128023;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for Store");
        if(imm_op !=3'd3) $fatal("Expected immediate extension opcode not received for Store");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for Store");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for Store");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for Store");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for Store");
        if(rfile_mux != 0) $fatal("Expected RF destination select line not received for Store");
        #15;
        if(dmem_we != 4'd1) $fatal("Expected DMem write enable not received for SB");
        #15;
         instruction <= 32'h00129023;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for Store");
        if(imm_op !=3'd3) $fatal("Expected immediate extension opcode not received for Store");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for Store");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for Store");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for Store");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for Store");
        if(rfile_mux != 0) $fatal("Expected RF destination select line not received for Store");
        #15;
        if(dmem_we != 4'd3) $fatal("Expected DMem write enable not received for SH");
        #15;
         instruction <= 32'h0012a023;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for Store");
        if(imm_op !=3'd3) $fatal("Expected immediate extension opcode not received for Store");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for Store");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for Store");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for Store");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for Store");
        if(rfile_mux != 0) $fatal("Expected RF destination select line not received for Store");
        #15;
        if(dmem_we != 4'b1111) $fatal("Expected DMem write enable not received for SW");
        #15;
        

        instruction <= 32'h00108293;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for I-type Arithmetic");
        if(imm_op !=3'd1) $fatal("Expected immediate extension opcode not received for I-type Arithmetic");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for I-type Arithmetic");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for I-type Arithmetic");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for I-type Arithmetic");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for ADDI");
        #20;
        instruction <= 32'h0020a293;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for I-type Arithmetic");
        if(imm_op !=3'd1) $fatal("Expected immediate extension opcode not received for I-type Arithmetic");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for I-type Arithmetic");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for I-type Arithmetic");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for I-type Arithmetic");
        if(alu_op != 4'd2) $fatal("Expected ALU opcode not received for SLTI");
        #20;
        instruction <= 32'h0020b293;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for I-type Arithmetic");
        if(imm_op !=3'd1) $fatal("Expected immediate extension opcode not received for I-type Arithmetic");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for I-type Arithmetic");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for I-type Arithmetic");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for I-type Arithmetic");
        if(alu_op != 4'd3) $fatal("Expected ALU opcode not received for SLTIU");
        #20;
        instruction <= 32'h0202c293;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for I-type Arithmetic");
        if(imm_op !=3'd1) $fatal("Expected immediate extension opcode not received for I-type Arithmetic");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for I-type Arithmetic");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for I-type Arithmetic");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for I-type Arithmetic");
        if(alu_op != 4'd4) $fatal("Expected ALU opcode not received for XORI");
        #20;
        instruction <= 32'h0102e093;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for I-type Arithmetic");
        if(imm_op !=3'd1) $fatal("Expected immediate extension opcode not received for I-type Arithmetic");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for I-type Arithmetic");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for I-type Arithmetic");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for I-type Arithmetic");
        if(alu_op != 4'd6) $fatal("Expected ALU opcode not received for ORI");
        #20;
        instruction <= 32'h0042f293;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for I-type Arithmetic");
        if(imm_op !=3'd1) $fatal("Expected immediate extension opcode not received for I-type Arithmetic");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for I-type Arithmetic");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for I-type Arithmetic");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for I-type Arithmetic");
        if(alu_op != 4'd7) $fatal("Expected ALU opcode not received for ANDI");
        #20;
         instruction <= 32'h00109093;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for I-type Arithmetic");
        if(imm_op !=3'd1) $fatal("Expected immediate extension opcode not received for I-type Arithmetic");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for I-type Arithmetic");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for I-type Arithmetic");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for I-type Arithmetic");
        if(alu_op != 4'd1) $fatal("Expected ALU opcode not received for SLLI");
        #20;
         instruction <= 32'h0010d093;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for I-type Arithmetic");
        if(imm_op !=3'd1) $fatal("Expected immediate extension opcode not received for I-type Arithmetic");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for I-type Arithmetic");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for I-type Arithmetic");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for I-type Arithmetic");
        if(alu_op != 4'd5) $fatal("Expected ALU opcode not received for SRLI");
        #20;
         instruction <= 32'h4010d093;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for I-type Arithmetic");
        if(imm_op !=3'd1) $fatal("Expected immediate extension opcode not received for I-type Arithmetic");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for I-type Arithmetic");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for I-type Arithmetic");
        if(alu_mux2 != 0) $fatal("Expected ALU input data2 not received for I-type Arithmetic");
        if(alu_op != 4'b1101) $fatal("Expected ALU opcode not received for SRAI");
        #20;
        

        instruction <= 32'h003100b3;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for R-type");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for R-type");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for R-type");
        if(alu_mux2 != 1) $fatal("Expected ALU input data2 not received for R-type");
        if(alu_op != 4'd0) $fatal("Expected ALU opcode not received for ADD");
        #20;
        instruction <= 32'h403100b3;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for R-type");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for R-type");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for R-type");
        if(alu_mux2 != 1) $fatal("Expected ALU input data2 not received for R-type");
        if(alu_op != 4'd8) $fatal("Expected ALU opcode not received for SUB");
        #20;
        instruction <= 32'h003290b3;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for R-type");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for R-type");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for R-type");
        if(alu_mux2 != 1) $fatal("Expected ALU input data2 not received for R-type");
        if(alu_op != 4'd1) $fatal("Expected ALU opcode not received for SLL");
        #20;
        instruction <= 32'h0032a0b3;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for R-type");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for R-type");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for R-type");
        if(alu_mux2 != 1) $fatal("Expected ALU input data2 not received for R-type");
        if(alu_op != 4'd2) $fatal("Expected ALU opcode not received for SLT");
        #20;
        instruction <= 32'h0032b0b3;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for R-type");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for R-type");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for R-type");
        if(alu_mux2 != 1) $fatal("Expected ALU input data2 not received for R-type");
        if(alu_op != 4'd3) $fatal("Expected ALU opcode not received for SLTU");
        #20;
        instruction <= 32'h0032c0b3;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for R-type");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for R-type");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for R-type");
        if(alu_mux2 != 1) $fatal("Expected ALU input data2 not received for R-type");
        if(alu_op != 4'd4) $fatal("Expected ALU opcode not received for XOR");
        #20;
        instruction <= 32'h0032d0b3;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for R-type");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for R-type");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for R-type");
        if(alu_mux2 != 1) $fatal("Expected ALU input data2 not received for R-type");
        if(alu_op != 4'd5) $fatal("Expected ALU opcode not received for SRL");
        #20;
        instruction <= 32'h4032d0b3;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for R-type");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for R-type");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for R-type");
        if(alu_mux2 != 1) $fatal("Expected ALU input data2 not received for R-type");
        if(alu_op != 4'b1101) $fatal("Expected ALU opcode not received for SRA");
        #20;
        instruction <= 32'h0032e0b3;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for R-type");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for R-type");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for R-type");
        if(alu_mux2 != 1) $fatal("Expected ALU input data2 not received for R-type");
        if(alu_op != 4'd6) $fatal("Expected ALU opcode not received for OR");
        #20;
        instruction <= 32'h0032f0b3;
        #10;
        if(op_mux !=2'd0) $fatal("Expected output mux select line not received for R-type");
        if(pc_mux !=0) $fatal("Expected PC update select line not received for R-type");
        if(alu_mux1 != 0) $fatal("Expected ALU input data1 not received for R-type");
        if(alu_mux2 != 1) $fatal("Expected ALU input data2 not received for R-type");
        if(alu_op != 4'd7) $fatal("Expected ALU opcode not received for AND");
        #20;
        
        instruction <= 32'h00000073;
        #20;
        if(imem_rd !=0) $fatal("Expected IMem read enable not received for Halt instruction");
        if(pc_we !=0) $fatal("Expected PC write enable not received for Halt instruction");
        if(rf_we != 0) $fatal("Expected RF write enable not received for Halt instruction");
        if(dmem_rd != 0) $fatal("Expected DMem read enable not received for Halt instruction");
        if(dmem_we != 4'd0) $fatal("Expected DMem write enable not received for Halt instruction");
        #20;
        instruction <= 32'h00100073;
        #20;
        if(imem_rd !=0) $fatal("Expected IMem read enable not received for Halt instruction");
        if(pc_we !=0) $fatal("Expected PC write enable not received for Halt instruction");
        if(rf_we != 0) $fatal("Expected RF write enable not received for Halt instruction");
        if(dmem_rd != 0) $fatal("Expected DMem read enable not received for Halt instruction");
        if(dmem_we != 4'd0) $fatal("Expected DMem write enable not received for Halt instruction");
        #20;
        
        $display("All test cases passed");
        $finish;
    end
    
endmodule