data/full_repos/permissive/475642691/simulations/new/simOL.v
1: b'%Error: data/full_repos/permissive/475642691/simulations/new/simOL.v:16: Unsupported or unknown PLI call: $monitor\n$monitor($time,"FS = %b, Current State = %b%b%b%b, FD = %b",FS,CS[3],CS[2],CS[1],CS[0],FD);\n^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/475642691/simulations/new/simOL.v:17: Unsupported: Ignoring delay on this delayed statement.\n#5  CS[3] = 1;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/475642691/simulations/new/simOL.v:23: Unsupported: Ignoring delay on this delayed statement.\n#5 CS[3] = 1;\n^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module simOL();
wire FD;
reg FS;
reg [3:0]CS;
OL outputLogic(FS,CS,FD);
initial
begin
FS <=0;
CS[3]<=0;
CS[2]<=0;
CS[1]<=0;
CS[0]<=0;
$monitor($time,"FS = %b, Current State = %b%b%b%b, FD = %b",FS,CS[3],CS[2],CS[1],CS[0],FD);
#5  CS[3] = 1;
    CS[2] = 1;
    CS[1] = 1;
    CS[0] = 1;
    FS = 1;

#5 CS[3] = 1;
    CS[2] = 0;
    CS[1] = 0;
    CS[0] = 0;
    FS = 0;
end
endmodule
module simOL();

wire FD;
reg FS;
reg [3:0]CS;
OL outputLogic(FS,CS,FD);
initial
begin
FS <=0;
CS[3]<=0;
CS[2]<=0;
CS[1]<=0;
CS[0]<=0;
$monitor($time,"FS = %b, Current State = %b%b%b%b, FD = %b",FS,CS[3],CS[2],CS[1],CS[0],FD);
#5  CS[3] = 1;
    CS[2] = 1;
    CS[1] = 1;
    CS[0] = 1;
    FS = 1;

#5 CS[3] = 1;
    CS[2] = 0;
    CS[1] = 0;
    CS[0] = 0;
    FS = 0;
end
endmodule