data/full_repos/permissive/458737381/src/verilog-parser/tests/dff_async_reset_async_preset.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dff_async_reset_async_preset.v:17: Unsupported or unknown PLI call: $monitor\n  $monitor("CLK = %b RESET = %b PRESET = %b D = %b Q = %b",\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/dff_async_reset_async_preset.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #1 reset  = 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/dff_async_reset_async_preset.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #1 reset = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/dff_async_reset_async_preset.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #2 reset = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/dff_async_reset_async_preset.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #2 preset = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/dff_async_reset_async_preset.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #2 preset = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/dff_async_reset_async_preset.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #2 d      = ~d;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/dff_async_reset_async_preset.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #2 $finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/dff_async_reset_async_preset.v:34: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = ~clk;\n ^\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module dff_async_reset_async_preset();

reg clk,reset,preset,d;
reg  q;

always @ (posedge clk or posedge reset or posedge preset)
if (reset) begin
  q <= 0;
end else if (preset) begin
  q <= 1;
end else begin
  q <= d;
end


initial begin
  $monitor("CLK = %b RESET = %b PRESET = %b D = %b Q = %b",
    clk,reset,preset,d,q);
  clk    = 0;
  #1 reset  = 0;
  preset = 0;
  d      = 0;
  #1 reset = 1;
  #2 reset = 0;
  #2 preset = 1;
  #2 preset = 0;
  repeat (4) begin
    #2 d      = ~d;
  end
  #2 $finish;
end

always
 #1 clk = ~clk;

endmodule
module dff_async_reset_async_preset();


reg clk,reset,preset,d;
reg  q;

always @ (posedge clk or posedge reset or posedge preset)
if (reset) begin
  q <= 0;
end else if (preset) begin
  q <= 1;
end else begin
  q <= d;
end


initial begin
  $monitor("CLK = %b RESET = %b PRESET = %b D = %b Q = %b",
    clk,reset,preset,d,q);
  clk    = 0;
  #1 reset  = 0;
  preset = 0;
  d      = 0;
  #1 reset = 1;
  #2 reset = 0;
  #2 preset = 1;
  #2 preset = 0;
  repeat (4) begin
    #2 d      = ~d;
  end
  #2 $finish;
end

always
 #1 clk = ~clk;

endmodule