data/full_repos/permissive/494148647/src/mb_soc_top.v
1: b"%Error: data/full_repos/permissive/494148647/src/mb_soc_top.v:72: Cannot find file containing module: 'mbsoc_clk_gen'\n    mbsoc_clk_gen cc (\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/494148647/src,data/full_repos/permissive/494148647/mbsoc_clk_gen\n             data/full_repos/permissive/494148647/src,data/full_repos/permissive/494148647/mbsoc_clk_gen.v\n             data/full_repos/permissive/494148647/src,data/full_repos/permissive/494148647/mbsoc_clk_gen.sv\n             mbsoc_clk_gen\n             mbsoc_clk_gen.v\n             mbsoc_clk_gen.sv\n             obj_dir/mbsoc_clk_gen\n             obj_dir/mbsoc_clk_gen.v\n             obj_dir/mbsoc_clk_gen.sv\n%Error: data/full_repos/permissive/494148647/src/mb_soc_top.v:84: Cannot find file containing module: 'debounce'\n    debounce#(\n    ^~~~~~~~\n%Error: data/full_repos/permissive/494148647/src/mb_soc_top.v:95: Cannot find file containing module: 'reset_synchronizer'\n    reset_synchronizer#(\n    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/494148647/src/mb_soc_top.v:103: Cannot find file containing module: 'reset_synchronizer'\n    reset_synchronizer#(\n    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/494148647/src/mb_soc_top.v:112: Cannot find file containing module: 'iobus_top'\n    iobus_top#(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/494148647/src/mb_soc_top.v:154: Cannot find file containing module: 'microblaze_mcs_v1_4'\n    microblaze_mcs_v1_4 mcs_0 (\n    ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n"
module mb_soc_top#(
    parameter GCNT_BITS = 56,
    parameter PDM_COUNT = 4,
    parameter IRQ_COUNT = 8
    ) (


    input clk,

    input rst_n,

    input cclk,

    output[7:0]led,

    output spi_miso,
    input spi_ss,
    input spi_mosi,
    input spi_sck,

    output [3:0] spi_channel,

    input avr_tx,
    output avr_rx,
    input avr_rx_busy,

    output uart0_tx,
    input  uart0_rx,

    output [PDM_COUNT-1:0]pdm,


    inout i2cm_scl,
    inout i2cm_sda,


    output sdram_clk,
    output sdram_cle,
    output sdram_dqm,
    output sdram_cs,
    output sdram_we,
    output sdram_cas,
    output sdram_ras,
    output [1:0] sdram_ba,
    output [12:0] sdram_a,
    inout [7:0] sdram_dq
    );


    assign spi_miso = 1'bz;
    assign avr_rx = 1'bz;
    assign spi_channel = 4'bzzzz;


    wire io_addr_strobe, io_read_strobe, io_write_strobe, io_ready;
    wire [31:0] io_address, io_write_data, io_read_data;
    wire [3:0] io_byte_enable;


    wire [IRQ_COUNT-1:0] irq;


    wire rst, lock, xo_clk, cpu_clk, mc_clk;

    mbsoc_clk_gen cc (
        .lock(lock),
        .clk_in(clk),
        .xo_clk(xo_clk),
        .cpu_clk(cpu_clk),
        .sdram_clk(mc_clk)
    );


    debounce#(
        .CTR_BITS(20)
    ) rst_debounce (
        .clk(xo_clk),
        .btn(~rst_n),
        .out(rst)
    );


    wire cpu_rst, mc_rst;

    reset_synchronizer#(
        .DELAY(4)
    ) cpu_rst_sync (
        .clk(cpu_clk),
        .rst_in(rst),
        .rst_out(cpu_rst)
    );

    reset_synchronizer#(
        .DELAY(4)
    ) mc_rst_sync (
        .clk(mc_clk),
        .rst_in(cpu_rst),
        .rst_out(mc_rst)
    );


    iobus_top#(
        .GCNT_BITS(GCNT_BITS),
        .PDM_COUNT(PDM_COUNT)
    ) iom (

        .io_clk(cpu_clk),
        .io_rst(cpu_rst),
        .io_addr_strobe(io_addr_strobe),
        .io_read_strobe(io_read_strobe),
        .io_write_strobe(io_write_strobe),
        .io_address(io_address),
        .io_byte_enable(io_byte_enable),
        .io_write_data(io_write_data),
        .io_read_data(io_read_data),
        .io_ready(io_ready),


        .mc_clk(mc_clk),
        .mc_rst(mc_rst),
        .sdram_clk(sdram_clk),
        .sdram_cle(sdram_cle),
        .sdram_cs(sdram_cs),
        .sdram_cas(sdram_cas),
        .sdram_ras(sdram_ras),
        .sdram_we(sdram_we),
        .sdram_dqm(sdram_dqm),
        .sdram_ba(sdram_ba),
        .sdram_a(sdram_a),
        .sdram_dq(sdram_dq),


        .irq(irq),


        .pdm(pdm),


        .sda(i2cm_sda),
        .scl(i2cm_scl)
    );


    microblaze_mcs_v1_4 mcs_0 (

        .Clk(cpu_clk),
        .Reset(cpu_rst),
        .IO_Addr_Strobe(io_addr_strobe),
        .IO_Read_Strobe(io_read_strobe),
        .IO_Write_Strobe(io_write_strobe),
        .IO_Address(io_address),
        .IO_Byte_Enable(io_byte_enable),
        .IO_Write_Data(io_write_data),
        .IO_Read_Data(io_read_data),
        .IO_Ready(io_ready),


        .UART_Rx(uart0_rx),
        .UART_Tx(uart0_tx),
        .UART_Interrupt(),


        .FIT1_Interrupt(),
        .FIT1_Toggle(),
        .PIT1_Enable(1'b0),
        .PIT1_Interrupt(),
        .PIT1_Toggle(),
        .PIT2_Enable(1'b0),
        .PIT2_Interrupt(),
        .PIT2_Toggle(),
        .PIT3_Interrupt(),
        .PIT3_Toggle(),
        .PIT4_Interrupt(),
        .PIT4_Toggle(),


        .GPO1(),
        .GPO2(led),
        .GPI1(32'd0),
        .GPI1_Interrupt(),


        .INTC_Interrupt(irq),
        .INTC_IRQ()
    );

endmodule
module mb_soc_top#(
    parameter GCNT_BITS = 56,
    parameter PDM_COUNT = 4,
    parameter IRQ_COUNT = 8
    ) (


    input clk,

    input rst_n,

    input cclk,

    output[7:0]led,

    output spi_miso,
    input spi_ss,
    input spi_mosi,
    input spi_sck,

    output [3:0] spi_channel,

    input avr_tx,
    output avr_rx,
    input avr_rx_busy,

    output uart0_tx,
    input  uart0_rx,

    output [PDM_COUNT-1:0]pdm,


    inout i2cm_scl,
    inout i2cm_sda,


    output sdram_clk,
    output sdram_cle,
    output sdram_dqm,
    output sdram_cs,
    output sdram_we,
    output sdram_cas,
    output sdram_ras,
    output [1:0] sdram_ba,
    output [12:0] sdram_a,
    inout [7:0] sdram_dq
    );



    assign spi_miso = 1'bz;
    assign avr_rx = 1'bz;
    assign spi_channel = 4'bzzzz;


    wire io_addr_strobe, io_read_strobe, io_write_strobe, io_ready;
    wire [31:0] io_address, io_write_data, io_read_data;
    wire [3:0] io_byte_enable;


    wire [IRQ_COUNT-1:0] irq;


    wire rst, lock, xo_clk, cpu_clk, mc_clk;

    mbsoc_clk_gen cc (
        .lock(lock),
        .clk_in(clk),
        .xo_clk(xo_clk),
        .cpu_clk(cpu_clk),
        .sdram_clk(mc_clk)
    );


    debounce#(
        .CTR_BITS(20)
    ) rst_debounce (
        .clk(xo_clk),
        .btn(~rst_n),
        .out(rst)
    );


    wire cpu_rst, mc_rst;

    reset_synchronizer#(
        .DELAY(4)
    ) cpu_rst_sync (
        .clk(cpu_clk),
        .rst_in(rst),
        .rst_out(cpu_rst)
    );

    reset_synchronizer#(
        .DELAY(4)
    ) mc_rst_sync (
        .clk(mc_clk),
        .rst_in(cpu_rst),
        .rst_out(mc_rst)
    );


    iobus_top#(
        .GCNT_BITS(GCNT_BITS),
        .PDM_COUNT(PDM_COUNT)
    ) iom (

        .io_clk(cpu_clk),
        .io_rst(cpu_rst),
        .io_addr_strobe(io_addr_strobe),
        .io_read_strobe(io_read_strobe),
        .io_write_strobe(io_write_strobe),
        .io_address(io_address),
        .io_byte_enable(io_byte_enable),
        .io_write_data(io_write_data),
        .io_read_data(io_read_data),
        .io_ready(io_ready),


        .mc_clk(mc_clk),
        .mc_rst(mc_rst),
        .sdram_clk(sdram_clk),
        .sdram_cle(sdram_cle),
        .sdram_cs(sdram_cs),
        .sdram_cas(sdram_cas),
        .sdram_ras(sdram_ras),
        .sdram_we(sdram_we),
        .sdram_dqm(sdram_dqm),
        .sdram_ba(sdram_ba),
        .sdram_a(sdram_a),
        .sdram_dq(sdram_dq),


        .irq(irq),


        .pdm(pdm),


        .sda(i2cm_sda),
        .scl(i2cm_scl)
    );


    microblaze_mcs_v1_4 mcs_0 (

        .Clk(cpu_clk),
        .Reset(cpu_rst),
        .IO_Addr_Strobe(io_addr_strobe),
        .IO_Read_Strobe(io_read_strobe),
        .IO_Write_Strobe(io_write_strobe),
        .IO_Address(io_address),
        .IO_Byte_Enable(io_byte_enable),
        .IO_Write_Data(io_write_data),
        .IO_Read_Data(io_read_data),
        .IO_Ready(io_ready),


        .UART_Rx(uart0_rx),
        .UART_Tx(uart0_tx),
        .UART_Interrupt(),


        .FIT1_Interrupt(),
        .FIT1_Toggle(),
        .PIT1_Enable(1'b0),
        .PIT1_Interrupt(),
        .PIT1_Toggle(),
        .PIT2_Enable(1'b0),
        .PIT2_Interrupt(),
        .PIT2_Toggle(),
        .PIT3_Interrupt(),
        .PIT3_Toggle(),
        .PIT4_Interrupt(),
        .PIT4_Toggle(),


        .GPO1(),
        .GPO2(led),
        .GPI1(32'd0),
        .GPI1_Interrupt(),


        .INTC_Interrupt(irq),
        .INTC_IRQ()
    );

endmodule