data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/hb/ram16_2port.v
1: b'%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/hb/ram16_2port.v:11: Bit extraction of array[31:0] requires 5 bit index, not 4 bits.\n                                                                                           : ... In instance ram16_2port\n     rd_data1 <= #1 ram_array[rd_addr1];\n                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/hb/ram16_2port.v:14: Bit extraction of array[31:0] requires 5 bit index, not 4 bits.\n                                                                                           : ... In instance ram16_2port\n     rd_data2 <= #1 ram_array[rd_addr2];\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/hb/ram16_2port.v:18: Bit extraction of array[31:0] requires 5 bit index, not 4 bits.\n                                                                                           : ... In instance ram16_2port\n       ram_array[wr_addr] <= #1 wr_data;\n                ^\n%Error: Exiting due to 3 warning(s)\n'
module ram16_2port (input clock, input write, 
		    input [3:0] wr_addr, input [15:0] wr_data,
		    input [3:0] rd_addr1, output reg [15:0] rd_data1,
		    input [3:0] rd_addr2, output reg [15:0] rd_data2);
   
   reg [15:0] 			ram_array [0:31];
   
   always @(posedge clock)
     rd_data1 <= #1 ram_array[rd_addr1];
   
   always @(posedge clock)
     rd_data2 <= #1 ram_array[rd_addr2];
   
   always @(posedge clock)
     if(write)
       ram_array[wr_addr] <= #1 wr_data;
   
endmodule
module ram16_2port (input clock, input write, 
		    input [3:0] wr_addr, input [15:0] wr_data,
		    input [3:0] rd_addr1, output reg [15:0] rd_data1,
		    input [3:0] rd_addr2, output reg [15:0] rd_data2);

   
   reg [15:0] 			ram_array [0:31];
   
   always @(posedge clock)
     rd_data1 <= #1 ram_array[rd_addr1];
   
   always @(posedge clock)
     rd_data2 <= #1 ram_array[rd_addr2];
   
   always @(posedge clock)
     if(write)
       ram_array[wr_addr] <= #1 wr_data;
   
endmodule