data/full_repos/permissive/445455582/single/tb/control_tb.v
1: b'%Error: data/full_repos/permissive/445455582/single/tb/control_tb.v:22: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/445455582/single/tb,data/full_repos/permissive/445455582/defines.v\n             data/full_repos/permissive/445455582/single/tb,data/full_repos/permissive/445455582/defines.v.v\n             data/full_repos/permissive/445455582/single/tb,data/full_repos/permissive/445455582/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/445455582/single/tb/control_tb.v:23: Cannot find include file: RiSC16_control.v\n`include "RiSC16_control.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/tb/control_tb.v:58: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("control_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/445455582/single/tb/control_tb.v:59: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, control_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/control_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n            #10 op <= op + 1;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/control_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n        #10 pen <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/control_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n            #10 op <= op + 1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/control_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n        #10 pen <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/control_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n            #10 op <= op + 1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/control_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n        #10 pen <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/control_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n            #10 op <= op + 1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/445455582/single/tb/control_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n        #10 $finish;\n        ^\n%Error: Exiting due to 4 error(s), 8 warning(s)\n'
module control_tb;

    reg [2:0] op = 3'b000;
    reg state = 0;
    reg pen = 0;
    wire [1:0] aluFunct;
    wire muxSrc1; 
    wire muxSrc2;
    wire d_wen;
    wire reg_wen;
    wire [1:0] muxTrgt;
    wire muxAddr2;
    wire [1:0] muxPc;

    RiSC16_control #(
        .OP_LEN(3)
    ) control (
        .op(op), 
        .state(state), 
        .pen(pen), 
        .aluFunct(aluFunct),
        .muxSrc1(muxSrc1), 
        .muxSrc2(muxSrc2), 
        .d_wen(d_wen), 
        .reg_wen(reg_wen), 
        .muxTrgt(muxTrgt), 
        .muxAddr2(muxAddr2), 
        .muxPc(muxPc) 
    );

    integer i;
    initial begin
        
        $dumpfile("control_tb.vcd");
        $dumpvars(0, control_tb);

        
        for ( i = 0; i< 8; i = i + 1) begin
            #10 op <= op + 1;
        end

        #10 pen <= 1;

        for ( i = 0; i< 8; i = i + 1) begin
            #10 op <= op + 1;
        end

        #10 pen <= 0;
            state <= 1;
        
        for ( i = 0; i< 8; i = i + 1) begin
            #10 op <= op + 1;
        end

        #10 pen <= 1;
            state <= 1;

        for ( i = 0; i< 8; i = i + 1) begin
            #10 op <= op + 1;
        end

        #10 $finish;

    end



endmodule
module control_tb;


    reg [2:0] op = 3'b000;
    reg state = 0;
    reg pen = 0;
    wire [1:0] aluFunct;
    wire muxSrc1; 
    wire muxSrc2;
    wire d_wen;
    wire reg_wen;
    wire [1:0] muxTrgt;
    wire muxAddr2;
    wire [1:0] muxPc;

    RiSC16_control #(
        .OP_LEN(3)
    ) control (
        .op(op), 
        .state(state), 
        .pen(pen), 
        .aluFunct(aluFunct),
        .muxSrc1(muxSrc1), 
        .muxSrc2(muxSrc2), 
        .d_wen(d_wen), 
        .reg_wen(reg_wen), 
        .muxTrgt(muxTrgt), 
        .muxAddr2(muxAddr2), 
        .muxPc(muxPc) 
    );

    integer i;
    initial begin
        
        $dumpfile("control_tb.vcd");
        $dumpvars(0, control_tb);

        
        for ( i = 0; i< 8; i = i + 1) begin
            #10 op <= op + 1;
        end

        #10 pen <= 1;

        for ( i = 0; i< 8; i = i + 1) begin
            #10 op <= op + 1;
        end

        #10 pen <= 0;
            state <= 1;
        
        for ( i = 0; i< 8; i = i + 1) begin
            #10 op <= op + 1;
        end

        #10 pen <= 1;
            state <= 1;

        for ( i = 0; i< 8; i = i + 1) begin
            #10 op <= op + 1;
        end

        #10 $finish;

    end



endmodule