data/full_repos/permissive/445695969/src_rtl/unprotected/deoxys_rnd.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/445695969/src_rtl/unprotected/deoxys_rnd.v:128: Multiple top level modules\n                                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                            : ... Top module \'deoxys_rnd\'\nmodule deoxys_rnd ( \n       ^~~~~~~~~~\n                                                                                            : ... Top module \'aes_sbox\'\nmodule aes_sbox ( \n       ^~~~~~~~\n                                                                                            : ... Top module \'deoxys_lfsr2_16\'\nmodule deoxys_lfsr2_16 ( \n       ^~~~~~~~~~~~~~~\n                                                                                            : ... Top module \'deoxys_lfsr3_16\'\nmodule deoxys_lfsr3_16 ( \n       ^~~~~~~~~~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/445695969/src_rtl/unprotected/deoxys_rnd.v:536: Little bit endian vector: MSB < LSB of bit range: 0:7\n   wire [0:7]         s, x;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/445695969/src_rtl/unprotected/deoxys_rnd.v:91: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n                                                                                        : ... In instance deoxys_rnd\n         assign rndconstant[i] = constant[7+8*i:0+8*i];\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/445695969/src_rtl/unprotected/deoxys_rnd.v:101: Operator XOR expects 128 bits on the RHS, but RHS\'s REPLICATE generates 120 bits.\n                                                                                         : ... In instance deoxys_rnd\n         assign rkey[i] = rndkey[i] ^ rndcnt[i] ^ rndtweak[i] ^\n                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/445695969/src_rtl/unprotected/deoxys_rnd.v:835: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 9 bits.\n                                                                                         : ... In instance deoxys_lfsr3_16\n            assign m[i+1][7+8*j:8*j] = {m[i][6]^m[i][0],m[i][7+8*j:8*j]};\n                                     ^\n%Error: Exiting due to 5 warning(s)\n'
module deoxys_lfsr2_16 (

   so,

   si
   ) ;
   output [127:0] so;
   input [127:0]  si;

   wire [127:0]     m [16:0];

   genvar           i, j;

   assign m[0] =si;

   generate
      for (i = 0; i < 16; i = i + 1) begin:lfsr_outer
         for (j= 0; j < 16; j = j + 1) begin:lfsr_inner
            assign m[i+1][7+8*j:8*j] = {m[i][6+8*j:8*j],m[i][7]^m[i][5]};
         end
      end
   endgenerate

   assign so = m[16];

endmodule
module deoxys_lfsr2_16 (

   so,

   si
   ) ;

   output [127:0] so;
   input [127:0]  si;

   wire [127:0]     m [16:0];

   genvar           i, j;

   assign m[0] =si;

   generate
      for (i = 0; i < 16; i = i + 1) begin:lfsr_outer
         for (j= 0; j < 16; j = j + 1) begin:lfsr_inner
            assign m[i+1][7+8*j:8*j] = {m[i][6+8*j:8*j],m[i][7]^m[i][5]};
         end
      end
   endgenerate

   assign so = m[16];

endmodule