data/full_repos/permissive/500128826/HDLBits/Vectors/Gates4/top_module.v
data/verilator_xmls/dd3622ee-1ef8-49b8-9cd5-a8a4e2ed2429.xml
module top_module (
    input wire [3:0] in,
    output wire out_and,
    output wire out_or,
    output wire out_xor
);

  assign out_and = &in;
  assign out_or  = |in;
  assign out_xor = ^in;

endmodule
module top_module (
    input wire [3:0] in,
    output wire out_and,
    output wire out_or,
    output wire out_xor
);


  assign out_and = &in;
  assign out_or  = |in;
  assign out_xor = ^in;

endmodule