data/full_repos/permissive/458737381/src/verilog-parser/tests/ansiport_example.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ansiport_example.v:9: Unsupported or unknown PLI call: $monitor\n  $monitor (\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/ansiport_example.v:12: Unsupported: Ignoring delay on this delayed statement.\n  #1 read = 0;  \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/ansiport_example.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #1 addr = addr + 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/ansiport_example.v:13: Unsupported: Ignoring delay on this delayed statement.\n  #3 repeat (16) begin\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/ansiport_example.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #1 addr = addr + 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/ansiport_example.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #3 repeat (16) begin\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/ansiport_example.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #1 $finish;\n  ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module memory_ansi (
  input wire read,
  input wire write,
  input wire [7:0] data_in,
  input wire [3:0] addr,
  output reg [7:0] data_out
);

reg [7:0] mem [0:15];

always @ (*)
begin
  if (write) mem[addr] = data_in;
end

always @ (read, addr)
begin
  if (read) data_out = mem[addr];
end

endmodule
module memory_ansi (
  input wire read,
  input wire write,
  input wire [7:0] data_in,
  input wire [3:0] addr,
  output reg [7:0] data_out
);


reg [7:0] mem [0:15];

always @ (*)
begin
  if (write) mem[addr] = data_in;
end

always @ (read, addr)
begin
  if (read) data_out = mem[addr];
end

endmodule