data/full_repos/permissive/496030466/Verilog/source/Bus_DPRAM.v
1: b"%Error: data/full_repos/permissive/496030466/Verilog/source/Bus_DPRAM.v:22: Cannot find file containing module: 'Dual_Port_RAM_Single_Clock'\n  Dual_Port_RAM_Single_Clock #(.WIDTH(16), .DEPTH(DEPTH)) Bus_RAM_Inst\n  ^~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/496030466/Verilog/source,data/full_repos/permissive/496030466/Dual_Port_RAM_Single_Clock\n             data/full_repos/permissive/496030466/Verilog/source,data/full_repos/permissive/496030466/Dual_Port_RAM_Single_Clock.v\n             data/full_repos/permissive/496030466/Verilog/source,data/full_repos/permissive/496030466/Dual_Port_RAM_Single_Clock.sv\n             Dual_Port_RAM_Single_Clock\n             Dual_Port_RAM_Single_Clock.v\n             Dual_Port_RAM_Single_Clock.sv\n             obj_dir/Dual_Port_RAM_Single_Clock\n             obj_dir/Dual_Port_RAM_Single_Clock.v\n             obj_dir/Dual_Port_RAM_Single_Clock.sv\n%Error: Exiting due to 1 error(s)\n"
module Bus_DPRAM #(parameter DEPTH = 256)
 (input             i_Bus_Rst_L,
  input             i_Bus_Clk,
  input             i_Bus_CS,
  input             i_Bus_Wr_Rd_n,
  input [15:0]      i_Bus_Addr8,
  input [15:0]      i_Bus_Wr_Data,
  output [15:0]     o_Bus_Rd_Data,
  output reg        o_Bus_Rd_DV,

  input [15:0]              i_PortB_Data,
  input [$clog2(DEPTH)-1:0] i_PortB_Addr16,
  input                     i_PortB_WE,
  output [15:0]             o_PortB_Data
  );



  Dual_Port_RAM_Single_Clock #(.WIDTH(16), .DEPTH(DEPTH)) Bus_RAM_Inst
  (.i_Clk(i_Bus_Clk),

   .i_PortA_Data(i_Bus_Wr_Data),
   .i_PortA_Addr(i_Bus_Addr8[$clog2(DEPTH):1]),
   .i_PortA_WE(i_Bus_Wr_Rd_n & i_Bus_CS),
   .o_PortA_Data(o_Bus_Rd_Data),

   .i_PortB_Data(i_PortB_Data),
   .i_PortB_Addr(i_PortB_Addr),
   .i_PortB_WE(i_PortB_WE),
   .o_PortB_Data(o_PortB_Data)
   );



  always @(posedge i_Bus_Clk)
  begin
    o_Bus_Rd_DV <= i_Bus_CS & ~i_Bus_Wr_Rd_n;
  end

	
endmodule
module Bus_DPRAM #(parameter DEPTH = 256)
 (input             i_Bus_Rst_L,
  input             i_Bus_Clk,
  input             i_Bus_CS,
  input             i_Bus_Wr_Rd_n,
  input [15:0]      i_Bus_Addr8,
  input [15:0]      i_Bus_Wr_Data,
  output [15:0]     o_Bus_Rd_Data,
  output reg        o_Bus_Rd_DV,

  input [15:0]              i_PortB_Data,
  input [$clog2(DEPTH)-1:0] i_PortB_Addr16,
  input                     i_PortB_WE,
  output [15:0]             o_PortB_Data
  );




  Dual_Port_RAM_Single_Clock #(.WIDTH(16), .DEPTH(DEPTH)) Bus_RAM_Inst
  (.i_Clk(i_Bus_Clk),

   .i_PortA_Data(i_Bus_Wr_Data),
   .i_PortA_Addr(i_Bus_Addr8[$clog2(DEPTH):1]),
   .i_PortA_WE(i_Bus_Wr_Rd_n & i_Bus_CS),
   .o_PortA_Data(o_Bus_Rd_Data),

   .i_PortB_Data(i_PortB_Data),
   .i_PortB_Addr(i_PortB_Addr),
   .i_PortB_WE(i_PortB_WE),
   .o_PortB_Data(o_PortB_Data)
   );



  always @(posedge i_Bus_Clk)
  begin
    o_Bus_Rd_DV <= i_Bus_CS & ~i_Bus_Wr_Rd_n;
  end

	
endmodule