data/full_repos/permissive/423693009/Modules/Mul_Reg_to_ALU_Module.v
data/verilator_xmls/91d1d4ed-dec5-40a1-9706-fea92e4a9c4e.xml
module Mul_Reg_to_ALU_Module(
	input selection,
	input [7:0] Immediate_data,
	input [7:0] Register_data,
	output [7:0] Data_out,
	output check
    );
	 
	 reg [7:0] data_out;
	 assign Data_out = data_out;
	 reg CHECK;
	 assign check = CHECK;
	 initial
	  begin
		CHECK = 1'b1;
	  end


	always@(selection or Register_data or Immediate_data )
		if(selection == 0)
			data_out <= Register_data;
		else if(selection == 1)
			data_out <= Immediate_data;
endmodule
module Mul_Reg_to_ALU_Module(
	input selection,
	input [7:0] Immediate_data,
	input [7:0] Register_data,
	output [7:0] Data_out,
	output check
    );

	 
	 reg [7:0] data_out;
	 assign Data_out = data_out;
	 reg CHECK;
	 assign check = CHECK;
	 initial
	  begin
		CHECK = 1'b1;
	  end


	always@(selection or Register_data or Immediate_data )
		if(selection == 0)
			data_out <= Register_data;
		else if(selection == 1)
			data_out <= Immediate_data;
endmodule