data/full_repos/permissive/493019833/test/testcase/firrtl/IntegerModule/reference/IntegerModule.v
data/verilator_xmls/dce721cb-4346-4a5d-93f5-76e57ed6147f.xml
module IntegerModule(
    input clock,
    input reset,
    input [9:0] io_in,
    output [9:0] io_out
);
    wire [9:0] _T_4;
    assign _T_4 = 10'sh0;
    wire [10:0] _T_5;
    ADD_SIGNED #(.width(10)) s_add_1 (
        .y(_T_5),
        .a(io_in),
        .b(_T_4)
    );
    wire [9:0] _T_6;
    TAIL #(.width(11), .n(1)) tail_2 (
        .y(_T_6),
        .in(_T_5)
    );
    wire [9:0] _T_7;
    ASSINT #(.width(10)) assint_3 (
        .y(_T_7),
        .in(_T_6)
    );
    assign io_out = _T_7;
endmodule
module IntegerModule(
    input clock,
    input reset,
    input [9:0] io_in,
    output [9:0] io_out
);

    wire [9:0] _T_4;
    assign _T_4 = 10'sh0;
    wire [10:0] _T_5;
    ADD_SIGNED #(.width(10)) s_add_1 (
        .y(_T_5),
        .a(io_in),
        .b(_T_4)
    );
    wire [9:0] _T_6;
    TAIL #(.width(11), .n(1)) tail_2 (
        .y(_T_6),
        .in(_T_5)
    );
    wire [9:0] _T_7;
    ASSINT #(.width(10)) assint_3 (
        .y(_T_7),
        .in(_T_6)
    );
    assign io_out = _T_7;
endmodule