data/full_repos/permissive/412289941/add_v.v
data/verilator_xmls/3dbeb8ad-65b0-4d37-8b29-df535ea26529.xml
module add_v(rst,data_in,data_out,clk);

input data_in,rst,clk;
output [1:0]data_out;
reg [1:0]data_out;
reg [1:0]counter;

always@(posedge clk or negedge rst) begin
    if(!rst) begin
        counter <= 0;
        data_out <= 0;
    end
    else if(data_in == 1'b1) begin
        counter <= 0;
        data_out <= 2'b01;
    end
    else if(data_in == 1'b0) begin
        counter <= counter + 1; 
        if(counter == 2'b11) begin
            data_out <= 2'b11;
            counter <= 0;
        end
        else data_out <= 2'b00;
    end
end

endmodule
module add_v(rst,data_in,data_out,clk);


input data_in,rst,clk;
output [1:0]data_out;
reg [1:0]data_out;
reg [1:0]counter;

always@(posedge clk or negedge rst) begin
    if(!rst) begin
        counter <= 0;
        data_out <= 0;
    end
    else if(data_in == 1'b1) begin
        counter <= 0;
        data_out <= 2'b01;
    end
    else if(data_in == 1'b0) begin
        counter <= counter + 1; 
        if(counter == 2'b11) begin
            data_out <= 2'b11;
            counter <= 0;
        end
        else data_out <= 2'b00;
    end
end

endmodule