data/full_repos/permissive/426889244/verilog/DMEM.v
data/verilator_xmls/ad8097e1-7057-4057-a106-e4fd1ed67e8b.xml
module DMEM (
    input wire clk,
    input wire we,
    input wire[31:0] ask_addr,
    input wire[31:0] fetch_addr,
    input wire[31:0] wdata,
    
    output wire[31:0] rdata
);










    reg[31:0] data_array[0:255];
    wire[31:0] src_rdata = data_array[ask_addr[9:2]];

    reg[31:0] rdata_reg;

    assign rdata = rdata_reg;

    always @(posedge clk) begin
        if (we) begin
            data_array[ask_addr[9:2]] <= wdata;
        end

        rdata_reg <= src_rdata;
    end
endmodule
module DMEM (
    input wire clk,
    input wire we,
    input wire[31:0] ask_addr,
    input wire[31:0] fetch_addr,
    input wire[31:0] wdata,
    
    output wire[31:0] rdata
);











    reg[31:0] data_array[0:255];
    wire[31:0] src_rdata = data_array[ask_addr[9:2]];

    reg[31:0] rdata_reg;

    assign rdata = rdata_reg;

    always @(posedge clk) begin
        if (we) begin
            data_array[ask_addr[9:2]] <= wdata;
        end

        rdata_reg <= src_rdata;
    end
endmodule