data/full_repos/permissive/515704782/bcd_ex3_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/515704782/bcd_ex3_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\nforever #5 clk=~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/515704782/bcd_ex3_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n#150 $finish;\n^\n%Error: data/full_repos/permissive/515704782/bcd_ex3_tb.v:27: Cannot find file containing module: \'bcd_ex3_nand\'\nbcd_ex3_nand n(clk,q,w,x,y,z);\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/515704782,data/full_repos/permissive/515704782/bcd_ex3_nand\n             data/full_repos/permissive/515704782,data/full_repos/permissive/515704782/bcd_ex3_nand.v\n             data/full_repos/permissive/515704782,data/full_repos/permissive/515704782/bcd_ex3_nand.sv\n             bcd_ex3_nand\n             bcd_ex3_nand.v\n             bcd_ex3_nand.sv\n             obj_dir/bcd_ex3_nand\n             obj_dir/bcd_ex3_nand.v\n             obj_dir/bcd_ex3_nand.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bcd_ex3_tb();
reg clk;
wire [3:0] q;
wire w,x,y,z;
bcd_ex3_nand n(clk,q,w,x,y,z);
initial begin
clk=0;
forever #5 clk=~clk;
end
initial begin
#150 $finish;
end
endmodule
module bcd_ex3_tb();

reg clk;
wire [3:0] q;
wire w,x,y,z;
bcd_ex3_nand n(clk,q,w,x,y,z);
initial begin
clk=0;
forever #5 clk=~clk;
end
initial begin
#150 $finish;
end
endmodule