data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:7: Multiple top level modules\n                                                                                                                : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                                : ... Top module \'cell0\'\nmodule cell0(Result0);\n       ^~~~~\n                                                                                                                : ... Top module \'cell1\'\nmodule cell1(Result0);\n       ^~~~~\n                                                                                                                : ... Top module \'ADD4\'\nmodule ADD4(\n       ^~~~\n                                                                                                                : ... Top module \'BUF\'\nmodule BUF(DATA, RESULT);\n       ^~~\n                                                                                                                : ... Top module \'INV\'\nmodule INV(DATA, RESULT);\n       ^~~\n                                                                                                                : ... Top module \'fd4\'\nmodule fd4(\n       ^~~\n                                                                                                                : ... Top module \'fdce1\'\nmodule fdce1(\n       ^~~~~\n                                                                                                                : ... Top module \'fdce4\'\nmodule fdce4(\n       ^~~~~\n                                                                                                                : ... Top module \'mux4_1_2\'\nmodule mux4_1_2(\n       ^~~~~~~~\n                                                                                                                : ... Top module \'mux1_1_2\'\nmodule mux1_1_2(\n       ^~~~~~~~\n                                                                                                                : ... Top module \'xor2\'\nmodule xor2(\n       ^~~~\n                                                                                                                : ... Top module \'fdce64\'\nmodule fdce64(\n       ^~~~~~\n                                                                                                                : ... Top module \'mux4_4_16\'\nmodule mux4_4_16(\n       ^~~~~~~~~\n                                                                                                                : ... Top module \'mux1_5_32\'\nmodule mux1_5_32(\n       ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:191: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Data0x0\' generates 1 bits.\n                                                                                                               : ... In instance mux1_5_32\n {Sel4, Sel3, Sel2, Sel1, Sel0} == 0 ? Data0x0 :\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:192: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Data1x0\' generates 1 bits.\n                                                                                                               : ... In instance mux1_5_32\n {Sel4, Sel3, Sel2, Sel1, Sel0} == 1 ? Data1x0 :\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:193: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Data2x0\' generates 1 bits.\n                                                                                                               : ... In instance mux1_5_32\n {Sel4, Sel3, Sel2, Sel1, Sel0} == 2 ? Data2x0 :\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:194: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Data3x0\' generates 1 bits.\n                                                                                                               : ... In instance mux1_5_32\n {Sel4, Sel3, Sel2, Sel1, Sel0} == 3 ? Data3x0 :\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:195: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Data4x0\' generates 1 bits.\n                                                                                                               : ... In instance mux1_5_32\n {Sel4, Sel3, Sel2, Sel1, Sel0} == 4 ? Data4x0 :\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:196: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Data5x0\' generates 1 bits.\n                                                                                                               : ... In instance mux1_5_32\n {Sel4, Sel3, Sel2, Sel1, Sel0} == 5 ? Data5x0 :\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:197: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Data6x0\' generates 1 bits.\n                                                                                                               : ... In instance mux1_5_32\n {Sel4, Sel3, Sel2, Sel1, Sel0} == 6 ? Data6x0 :\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:198: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Data7x0\' generates 1 bits.\n                                                                                                               : ... In instance mux1_5_32\n {Sel4, Sel3, Sel2, Sel1, Sel0} == 7 ? Data7x0 :\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:199: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Data8x0\' generates 1 bits.\n                                                                                                               : ... In instance mux1_5_32\n {Sel4, Sel3, Sel2, Sel1, Sel0} == 8 ? Data8x0 :\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:200: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Data9x0\' generates 1 bits.\n                                                                                                               : ... In instance mux1_5_32\n {Sel4, Sel3, Sel2, Sel1, Sel0} == 9 ? Data9x0 :\n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:201: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Data10x0\' generates 1 bits.\n                                                                                                               : ... In instance mux1_5_32\n {Sel4, Sel3, Sel2, Sel1, Sel0} == 10 ? Data10x0 :\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:202: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Data11x0\' generates 1 bits.\n                                                                                                               : ... In instance mux1_5_32\n {Sel4, Sel3, Sel2, Sel1, Sel0} == 11 ? Data11x0 :\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:203: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Data12x0\' generates 1 bits.\n                                                                                                               : ... In instance mux1_5_32\n {Sel4, Sel3, Sel2, Sel1, Sel0} == 12 ? Data12x0 :\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:204: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Data13x0\' generates 1 bits.\n                                                                                                               : ... In instance mux1_5_32\n {Sel4, Sel3, Sel2, Sel1, Sel0} == 13 ? Data13x0 :\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:205: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Data14x0\' generates 1 bits.\n                                                                                                               : ... In instance mux1_5_32\n {Sel4, Sel3, Sel2, Sel1, Sel0} == 14 ? Data14x0 :\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:206: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Data15x0\' generates 1 bits.\n                                                                                                               : ... In instance mux1_5_32\n {Sel4, Sel3, Sel2, Sel1, Sel0} == 15 ? Data15x0 :\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:207: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Data16x0\' generates 1 bits.\n                                                                                                               : ... In instance mux1_5_32\n {Sel4, Sel3, Sel2, Sel1, Sel0} == 16 ? Data16x0 :\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:208: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Data17x0\' generates 1 bits.\n                                                                                                               : ... In instance mux1_5_32\n {Sel4, Sel3, Sel2, Sel1, Sel0} == 17 ? Data17x0 :\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:209: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Data18x0\' generates 1 bits.\n                                                                                                               : ... In instance mux1_5_32\n {Sel4, Sel3, Sel2, Sel1, Sel0} == 18 ? Data18x0 :\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:210: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Data19x0\' generates 1 bits.\n                                                                                                               : ... In instance mux1_5_32\n {Sel4, Sel3, Sel2, Sel1, Sel0} == 19 ? Data19x0 :\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:211: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Data20x0\' generates 1 bits.\n                                                                                                               : ... In instance mux1_5_32\n {Sel4, Sel3, Sel2, Sel1, Sel0} == 20 ? Data20x0 :\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:212: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Data21x0\' generates 1 bits.\n                                                                                                               : ... In instance mux1_5_32\n {Sel4, Sel3, Sel2, Sel1, Sel0} == 21 ? Data21x0 :\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:213: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Data22x0\' generates 1 bits.\n                                                                                                               : ... In instance mux1_5_32\n {Sel4, Sel3, Sel2, Sel1, Sel0} == 22 ? Data22x0 :\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:214: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Data23x0\' generates 1 bits.\n                                                                                                               : ... In instance mux1_5_32\n {Sel4, Sel3, Sel2, Sel1, Sel0} == 23 ? Data23x0 :\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:215: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Data24x0\' generates 1 bits.\n                                                                                                               : ... In instance mux1_5_32\n {Sel4, Sel3, Sel2, Sel1, Sel0} == 24 ? Data24x0 :\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:216: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Data25x0\' generates 1 bits.\n                                                                                                               : ... In instance mux1_5_32\n {Sel4, Sel3, Sel2, Sel1, Sel0} == 25 ? Data25x0 :\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:217: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Data26x0\' generates 1 bits.\n                                                                                                               : ... In instance mux1_5_32\n {Sel4, Sel3, Sel2, Sel1, Sel0} == 26 ? Data26x0 :\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:218: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Data27x0\' generates 1 bits.\n                                                                                                               : ... In instance mux1_5_32\n {Sel4, Sel3, Sel2, Sel1, Sel0} == 27 ? Data27x0 :\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:219: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Data28x0\' generates 1 bits.\n                                                                                                               : ... In instance mux1_5_32\n {Sel4, Sel3, Sel2, Sel1, Sel0} == 28 ? Data28x0 :\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:220: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Data29x0\' generates 1 bits.\n                                                                                                               : ... In instance mux1_5_32\n {Sel4, Sel3, Sel2, Sel1, Sel0} == 29 ? Data29x0 :\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:221: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Data30x0\' generates 1 bits.\n                                                                                                               : ... In instance mux1_5_32\n {Sel4, Sel3, Sel2, Sel1, Sel0} == 30 ? Data30x0 :\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:222: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Data31x0\' generates 1 bits.\n                                                                                                               : ... In instance mux1_5_32\n {Sel4, Sel3, Sel2, Sel1, Sel0} == 31 ? Data31x0 : \'bx;\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:190: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                                               : ... In instance mux1_5_32\nassign Result0 =\n               ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:162: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s REPLICATE generates 4 bits.\n                                                                                                               : ... In instance mux4_4_16\n {Sel3, Sel2, Sel1, Sel0} == 0 ? { Data0x0, Data0x1, Data0x2, Data0x3 } :\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:163: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s REPLICATE generates 4 bits.\n                                                                                                               : ... In instance mux4_4_16\n {Sel3, Sel2, Sel1, Sel0} == 1 ? { Data1x0, Data1x1, Data1x2, Data1x3 } :\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:164: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s REPLICATE generates 4 bits.\n                                                                                                               : ... In instance mux4_4_16\n {Sel3, Sel2, Sel1, Sel0} == 2 ? { Data2x0, Data2x1, Data2x2, Data2x3 } :\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:165: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s REPLICATE generates 4 bits.\n                                                                                                               : ... In instance mux4_4_16\n {Sel3, Sel2, Sel1, Sel0} == 3 ? { Data3x0, Data3x1, Data3x2, Data3x3 } :\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:166: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s REPLICATE generates 4 bits.\n                                                                                                               : ... In instance mux4_4_16\n {Sel3, Sel2, Sel1, Sel0} == 4 ? { Data4x0, Data4x1, Data4x2, Data4x3 } :\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:167: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s REPLICATE generates 4 bits.\n                                                                                                               : ... In instance mux4_4_16\n {Sel3, Sel2, Sel1, Sel0} == 5 ? { Data5x0, Data5x1, Data5x2, Data5x3 } :\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:168: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s REPLICATE generates 4 bits.\n                                                                                                               : ... In instance mux4_4_16\n {Sel3, Sel2, Sel1, Sel0} == 6 ? { Data6x0, Data6x1, Data6x2, Data6x3 } :\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:169: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s REPLICATE generates 4 bits.\n                                                                                                               : ... In instance mux4_4_16\n {Sel3, Sel2, Sel1, Sel0} == 7 ? { Data7x0, Data7x1, Data7x2, Data7x3 } :\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:170: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s REPLICATE generates 4 bits.\n                                                                                                               : ... In instance mux4_4_16\n {Sel3, Sel2, Sel1, Sel0} == 8 ? { Data8x0, Data8x1, Data8x2, Data8x3 } :\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:171: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s REPLICATE generates 4 bits.\n                                                                                                               : ... In instance mux4_4_16\n {Sel3, Sel2, Sel1, Sel0} == 9 ? { Data9x0, Data9x1, Data9x2, Data9x3 } :\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:172: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s REPLICATE generates 4 bits.\n                                                                                                               : ... In instance mux4_4_16\n {Sel3, Sel2, Sel1, Sel0} == 10 ? { Data10x0, Data10x1, Data10x2, Data10x3 } :\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:173: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s REPLICATE generates 4 bits.\n                                                                                                               : ... In instance mux4_4_16\n {Sel3, Sel2, Sel1, Sel0} == 11 ? { Data11x0, Data11x1, Data11x2, Data11x3 } :\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:174: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s REPLICATE generates 4 bits.\n                                                                                                               : ... In instance mux4_4_16\n {Sel3, Sel2, Sel1, Sel0} == 12 ? { Data12x0, Data12x1, Data12x2, Data12x3 } :\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:175: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s REPLICATE generates 4 bits.\n                                                                                                               : ... In instance mux4_4_16\n {Sel3, Sel2, Sel1, Sel0} == 13 ? { Data13x0, Data13x1, Data13x2, Data13x3 } :\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:176: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s REPLICATE generates 4 bits.\n                                                                                                               : ... In instance mux4_4_16\n {Sel3, Sel2, Sel1, Sel0} == 14 ? { Data14x0, Data14x1, Data14x2, Data14x3 } :\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:177: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s REPLICATE generates 4 bits.\n                                                                                                               : ... In instance mux4_4_16\n {Sel3, Sel2, Sel1, Sel0} == 15 ? { Data15x0, Data15x1, Data15x2, Data15x3 } : \'bx;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_icarus.v:161: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n                                                                                                               : ... In instance mux4_4_16\nassign {Result0, Result1, Result2, Result3} =\n                                            ^\n%Error: Exiting due to 51 warning(s)\n'
module fdce64(
	Clock, Enable,
	Data0, Data1, Data2, Data3, Data4, Data5, Data6, Data7, Data8, Data9, Data10, Data11, Data12, Data13, Data14, Data15, Data16, Data17, Data18, Data19, Data20, Data21, Data22, Data23, Data24, Data25, Data26, Data27, Data28, Data29, Data30, Data31, Data32, Data33, Data34, Data35, Data36, Data37, Data38, Data39, Data40, Data41, Data42, Data43, Data44, Data45, Data46, Data47, Data48, Data49, Data50, Data51, Data52, Data53, Data54, Data55, Data56, Data57, Data58, Data59, Data60, Data61, Data62, Data63,
	Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38, Q39, Q40, Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48, Q49, Q50, Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58, Q59, Q60, Q61, Q62, Q63
);
input Clock, Enable;
input Data0, Data1, Data2, Data3, Data4, Data5, Data6, Data7, Data8, Data9, Data10, Data11, Data12, Data13, Data14, Data15, Data16, Data17, Data18, Data19, Data20, Data21, Data22, Data23, Data24, Data25, Data26, Data27, Data28, Data29, Data30, Data31, Data32, Data33, Data34, Data35, Data36, Data37, Data38, Data39, Data40, Data41, Data42, Data43, Data44, Data45, Data46, Data47, Data48, Data49, Data50, Data51, Data52, Data53, Data54, Data55, Data56, Data57, Data58, Data59, Data60, Data61, Data62, Data63;
output reg Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38, Q39, Q40, Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48, Q49, Q50, Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58, Q59, Q60, Q61, Q62, Q63;
always @(posedge Clock)
	if (Enable)
		{ Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38, Q39, Q40, Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48, Q49, Q50, Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58, Q59, Q60, Q61, Q62, Q63 } <= { Data0, Data1, Data2, Data3, Data4, Data5, Data6, Data7, Data8, Data9, Data10, Data11, Data12, Data13, Data14, Data15, Data16, Data17, Data18, Data19, Data20, Data21, Data22, Data23, Data24, Data25, Data26, Data27, Data28, Data29, Data30, Data31, Data32, Data33, Data34, Data35, Data36, Data37, Data38, Data39, Data40, Data41, Data42, Data43, Data44, Data45, Data46, Data47, Data48, Data49, Data50, Data51, Data52, Data53, Data54, Data55, Data56, Data57, Data58, Data59, Data60, Data61, Data62, Data63 };
endmodule
module fdce64(
	Clock, Enable,
	Data0, Data1, Data2, Data3, Data4, Data5, Data6, Data7, Data8, Data9, Data10, Data11, Data12, Data13, Data14, Data15, Data16, Data17, Data18, Data19, Data20, Data21, Data22, Data23, Data24, Data25, Data26, Data27, Data28, Data29, Data30, Data31, Data32, Data33, Data34, Data35, Data36, Data37, Data38, Data39, Data40, Data41, Data42, Data43, Data44, Data45, Data46, Data47, Data48, Data49, Data50, Data51, Data52, Data53, Data54, Data55, Data56, Data57, Data58, Data59, Data60, Data61, Data62, Data63,
	Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38, Q39, Q40, Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48, Q49, Q50, Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58, Q59, Q60, Q61, Q62, Q63
);

input Clock, Enable;
input Data0, Data1, Data2, Data3, Data4, Data5, Data6, Data7, Data8, Data9, Data10, Data11, Data12, Data13, Data14, Data15, Data16, Data17, Data18, Data19, Data20, Data21, Data22, Data23, Data24, Data25, Data26, Data27, Data28, Data29, Data30, Data31, Data32, Data33, Data34, Data35, Data36, Data37, Data38, Data39, Data40, Data41, Data42, Data43, Data44, Data45, Data46, Data47, Data48, Data49, Data50, Data51, Data52, Data53, Data54, Data55, Data56, Data57, Data58, Data59, Data60, Data61, Data62, Data63;
output reg Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38, Q39, Q40, Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48, Q49, Q50, Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58, Q59, Q60, Q61, Q62, Q63;
always @(posedge Clock)
	if (Enable)
		{ Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38, Q39, Q40, Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48, Q49, Q50, Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58, Q59, Q60, Q61, Q62, Q63 } <= { Data0, Data1, Data2, Data3, Data4, Data5, Data6, Data7, Data8, Data9, Data10, Data11, Data12, Data13, Data14, Data15, Data16, Data17, Data18, Data19, Data20, Data21, Data22, Data23, Data24, Data25, Data26, Data27, Data28, Data29, Data30, Data31, Data32, Data33, Data34, Data35, Data36, Data37, Data38, Data39, Data40, Data41, Data42, Data43, Data44, Data45, Data46, Data47, Data48, Data49, Data50, Data51, Data52, Data53, Data54, Data55, Data56, Data57, Data58, Data59, Data60, Data61, Data62, Data63 };
endmodule