data/full_repos/permissive/433640910/RateDivider/ratedivider.v
data/verilator_xmls/57a74fa6-75f9-4eaa-9a52-504b12b5b704.xml
module RateDivider(Speed, ClockIn, Clear_b, Out);
	input [1:0]Speed;
	input	ClockIn, Clear_b;
	output reg [26:0] Out;
	reg [26:0] d;
	
	always @(Speed)
	begin
	case (Speed)
		2'b00: d <= 27'b0;
		2'b01: d <= 27'b001011111010111100000111111;
		2'b10: d <= 27'b010111110101111000001111111;
		2'b11: d <= 27'b101111101011110000011111111;
		default: d <= 27'b0;
	endcase
	end
	
	always@ (posedge ClockIn)
	begin
		if(Clear_b)
			Out <= 0;
		else if (Out == 0)				
			Out <= d;
		else  
			Out <= Out - 1;
		end
	
endmodule
module RateDivider(Speed, ClockIn, Clear_b, Out);

	input [1:0]Speed;
	input	ClockIn, Clear_b;
	output reg [26:0] Out;
	reg [26:0] d;
	
	always @(Speed)
	begin
	case (Speed)
		2'b00: d <= 27'b0;
		2'b01: d <= 27'b001011111010111100000111111;
		2'b10: d <= 27'b010111110101111000001111111;
		2'b11: d <= 27'b101111101011110000011111111;
		default: d <= 27'b0;
	endcase
	end
	
	always@ (posedge ClockIn)
	begin
		if(Clear_b)
			Out <= 0;
		else if (Out == 0)				
			Out <= d;
		else  
			Out <= Out - 1;
		end
	
endmodule