data/full_repos/permissive/43856783/j1_soc/hdl/j1/j1_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/j1/j1_TB.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #10 sys_rst_i = 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/j1/j1_TB.v:31: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("j1_TB.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/j1/j1_TB.v:32: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(-1, uut);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/j1/j1_TB.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #100000 $finish;\n  ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module j1_TB ();

reg sys_clk_i, sys_rst_i;
reg [15:0] io_din;

wire io_rd, io_wr; 
wire [11:0] io_addr; 
wire [15:0] io_dout; 

j1 uut (
	sys_clk_i, sys_rst_i, io_din, io_rd, io_wr, io_addr, io_dout
);

initial begin
  sys_clk_i   = 1;
  sys_rst_i = 1;
  #10 sys_rst_i = 0;
  io_din = 20;

end

always sys_clk_i = #1 ~sys_clk_i;


initial begin: TEST_CASE
  $dumpfile("j1_TB.vcd");
  $dumpvars(-1, uut);
  #100000 $finish;
end

endmodule
module j1_TB ();


reg sys_clk_i, sys_rst_i;
reg [15:0] io_din;

wire io_rd, io_wr; 
wire [11:0] io_addr; 
wire [15:0] io_dout; 

j1 uut (
	sys_clk_i, sys_rst_i, io_din, io_rd, io_wr, io_addr, io_dout
);

initial begin
  sys_clk_i   = 1;
  sys_rst_i = 1;
  #10 sys_rst_i = 0;
  io_din = 20;

end

always sys_clk_i = #1 ~sys_clk_i;


initial begin: TEST_CASE
  $dumpfile("j1_TB.vcd");
  $dumpvars(-1, uut);
  #100000 $finish;
end

endmodule