data/full_repos/permissive/511377659/verilog/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/511377659/verilog/tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/511377659/verilog/tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/511377659/verilog/tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #491520          \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/511377659/verilog/tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #(20);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/511377659/verilog/tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/511377659/verilog/tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #(20);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/511377659/verilog/tb.v:41: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk <= ~clk;\n       ^\n%Error: data/full_repos/permissive/511377659/verilog/tb.v:12: Cannot find file containing module: \'top_deinter\'\ntop_deinter TEST(deleav_data, clk, rst, in_data, en_in);\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/511377659/verilog,data/full_repos/permissive/511377659/top_deinter\n             data/full_repos/permissive/511377659/verilog,data/full_repos/permissive/511377659/top_deinter.v\n             data/full_repos/permissive/511377659/verilog,data/full_repos/permissive/511377659/top_deinter.sv\n             top_deinter\n             top_deinter.v\n             top_deinter.sv\n             obj_dir/top_deinter\n             obj_dir/top_deinter.v\n             obj_dir/top_deinter.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();

reg clk, rst, en_in;
reg [10:0] data [0:12288-1]; 
reg [10:0] in_data;
wire [10:0] deleav_data;
wire NWRT, en_out;


top_deinter TEST(deleav_data, clk, rst, in_data, en_in);

initial begin
    rst <= 1;
    clk <= 1;
    en_in <= 0;
    #10
    rst <= 0;
    #10
    en_in <= 1;
    #491520
    $finish;
end

integer i, j;

initial begin
    $readmemb("vector1.txt", data);
    #20
    for (i=0;i<12288;i=i+1) begin
        in_data <= data[i];
        #(20);
    end
    for (j=0;j<12288;j=j+1) begin
        in_data <= data[j];
        #(20);
    end
end

always #5 clk <= ~clk;

endmodule
module tb();


reg clk, rst, en_in;
reg [10:0] data [0:12288-1]; 
reg [10:0] in_data;
wire [10:0] deleav_data;
wire NWRT, en_out;


top_deinter TEST(deleav_data, clk, rst, in_data, en_in);

initial begin
    rst <= 1;
    clk <= 1;
    en_in <= 0;
    #10
    rst <= 0;
    #10
    en_in <= 1;
    #491520
    $finish;
end

integer i, j;

initial begin
    $readmemb("vector1.txt", data);
    #20
    for (i=0;i<12288;i=i+1) begin
        in_data <= data[i];
        #(20);
    end
    for (j=0;j<12288;j=j+1) begin
        in_data <= data[j];
        #(20);
    end
end

always #5 clk <= ~clk;

endmodule