data/full_repos/permissive/471766415/src/vga_pll.v
1: b"%Error: data/full_repos/permissive/471766415/src/vga_pll.v:17: syntax error, unexpected ')', expecting '['\n );\n ^\n%Error: Exiting due to 1 error(s)\n"
module vga_pll(
	input  clock_in,
	output clock_out,
	output pll_locked,
	);

	SB_PLL40_PAD #(
		.DIVR(4'b1001),
		.DIVF(7'b1010000),
		.DIVQ(3'b101),
		.FILTER_RANGE(3'b001),
		.FEEDBACK_PATH("SIMPLE"),
		.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
		.FDA_FEEDBACK(4'b0000),
		.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
		.FDA_RELATIVE(4'b0000),
		.SHIFTREG_DIV_MODE(2'b00),
		.PLLOUT_SELECT("GENCLK"),
		.ENABLE_ICEGATE(1'b0)
	) pll_inst (
		.PACKAGEPIN(clock_in),
		.PLLOUTCORE(),
		.PLLOUTGLOBAL(clock_out),
		.EXTFEEDBACK(),
		.DYNAMICDELAY(),
		.RESETB(1'b1),
		.BYPASS(1'b0),
		.LOCK(pll_locked),
		.LATCHINPUTVALUE(),
	);

endmodule
module vga_pll(
	input  clock_in,
	output clock_out,
	output pll_locked,
	);


	SB_PLL40_PAD #(
		.DIVR(4'b1001),
		.DIVF(7'b1010000),
		.DIVQ(3'b101),
		.FILTER_RANGE(3'b001),
		.FEEDBACK_PATH("SIMPLE"),
		.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
		.FDA_FEEDBACK(4'b0000),
		.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
		.FDA_RELATIVE(4'b0000),
		.SHIFTREG_DIV_MODE(2'b00),
		.PLLOUT_SELECT("GENCLK"),
		.ENABLE_ICEGATE(1'b0)
	) pll_inst (
		.PACKAGEPIN(clock_in),
		.PLLOUTCORE(),
		.PLLOUTGLOBAL(clock_out),
		.EXTFEEDBACK(),
		.DYNAMICDELAY(),
		.RESETB(1'b1),
		.BYPASS(1'b0),
		.LOCK(pll_locked),
		.LATCHINPUTVALUE(),
	);

endmodule