data/full_repos/permissive/427048176/verilog/rtl/VgaSyncGen.v
data/verilator_xmls/9f7d9dae-30bf-46eb-b3a2-7bf5cde986ca.xml
module VgaSyncGen (
            input wire       px_clk,
            input wire       reset,
            output wire      hsync,
            output wire      vsync,
            output reg [9:0] x_px,
            output reg [9:0] y_px,
            output wire      activevideo
         );




    parameter activeHvideo = 640;
    parameter activeVvideo = 480;
    parameter hfp = 24;
    parameter hpulse = 40;
    parameter hbp = 128;
    parameter vfp = 9;
    parameter vpulse = 3;
    parameter vbp = 28;
    parameter blackH = hfp + hpulse + hbp;
    parameter blackV = vfp + vpulse + vbp;
    parameter hpixels = blackH + activeHvideo;
    parameter vlines = blackV + activeVvideo;


    reg [9:0] hc;
    reg [9:0] vc;


    always @(posedge px_clk)
    begin
        if(reset) begin
            hc <= 0;
            vc <= 0;
        end else begin

            if (hc < hpixels - 1)
                hc <= hc + 1;
            else




            begin
                hc <= 0;
                if (vc < vlines - 1)
                vc <= vc + 1;
            else
               vc <= 0;
            end
        end
     end


    assign hsync = (hc >= hfp && hc < hfp + hpulse) ? 0:1;
    assign vsync = (vc >= vfp && vc < vfp + vpulse) ? 0:1;
    assign activevideo = (hc >= blackH && vc >= blackV) ? 1:0;


    always @(posedge px_clk)
    begin
        if(reset) begin
            x_px <= 0;
            y_px <= 0;
        end else begin
            x_px <= hc - blackH;
            y_px <= vc - blackV;
        end
     end
 endmodule
module VgaSyncGen (
            input wire       px_clk,
            input wire       reset,
            output wire      hsync,
            output wire      vsync,
            output reg [9:0] x_px,
            output reg [9:0] y_px,
            output wire      activevideo
         );





    parameter activeHvideo = 640;
    parameter activeVvideo = 480;
    parameter hfp = 24;
    parameter hpulse = 40;
    parameter hbp = 128;
    parameter vfp = 9;
    parameter vpulse = 3;
    parameter vbp = 28;
    parameter blackH = hfp + hpulse + hbp;
    parameter blackV = vfp + vpulse + vbp;
    parameter hpixels = blackH + activeHvideo;
    parameter vlines = blackV + activeVvideo;


    reg [9:0] hc;
    reg [9:0] vc;


    always @(posedge px_clk)
    begin
        if(reset) begin
            hc <= 0;
            vc <= 0;
        end else begin

            if (hc < hpixels - 1)
                hc <= hc + 1;
            else




            begin
                hc <= 0;
                if (vc < vlines - 1)
                vc <= vc + 1;
            else
               vc <= 0;
            end
        end
     end


    assign hsync = (hc >= hfp && hc < hfp + hpulse) ? 0:1;
    assign vsync = (vc >= vfp && vc < vfp + vpulse) ? 0:1;
    assign activevideo = (hc >= blackH && vc >= blackV) ? 1:0;


    always @(posedge px_clk)
    begin
        if(reset) begin
            x_px <= 0;
            y_px <= 0;
        end else begin
            x_px <= hc - blackH;
            y_px <= vc - blackV;
        end
     end
 endmodule