data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_clk_edgelogic.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_clk_edgelogic.v:60: Signal definition not found, creating implicitly: \'dram_io_clk_enable_d1\'\n                                                                                                        : ... Suggested alternative: \'dram_io_clk_enable\'\nwire clk_out = clk_value & dram_io_clk_enable_d1;\n                           ^~~~~~~~~~~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_clk_edgelogic.v:54: Cannot find file containing module: \'dff_s\'\ndff_s #(1)        flop_io_pad_flip_clk(\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/dff_s\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/dff_s.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/dff_s.sv\n             dff_s\n             dff_s.v\n             dff_s.sv\n             obj_dir/dff_s\n             obj_dir/dff_s.v\n             obj_dir/dff_s.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module dram_clk_edgelogic(

   clk_pad_clk_so, to_pad, 

   clk, clk_pad_clk_si, clk_pad_clk_se, clk_value, 
   dram_io_clk_enable, testmode_l
   );




input			clk;
input			testmode_l;
input			clk_pad_clk_si;
input			clk_pad_clk_se;
input			clk_value;
input			dram_io_clk_enable;




output			clk_pad_clk_so;
output			to_pad;






wire tclk = testmode_l ? ~clk : clk;



dff_s #(1)        flop_io_pad_flip_clk(
                .din(dram_io_clk_enable),
                .q(dram_io_clk_enable_d1),
                .clk(tclk),
                .si(clk_pad_clk_si), .so(clk_pad_clk_so), .se(clk_pad_clk_se));

wire clk_out = clk_value & dram_io_clk_enable_d1;

wire enable_mux_val = dram_io_clk_enable_d1 ? ~clk_out : clk_out;

assign to_pad = clk ? clk_out : enable_mux_val;

endmodule
module dram_clk_edgelogic(

   clk_pad_clk_so, to_pad, 

   clk, clk_pad_clk_si, clk_pad_clk_se, clk_value, 
   dram_io_clk_enable, testmode_l
   );





input			clk;
input			testmode_l;
input			clk_pad_clk_si;
input			clk_pad_clk_se;
input			clk_value;
input			dram_io_clk_enable;




output			clk_pad_clk_so;
output			to_pad;






wire tclk = testmode_l ? ~clk : clk;



dff_s #(1)        flop_io_pad_flip_clk(
                .din(dram_io_clk_enable),
                .q(dram_io_clk_enable_d1),
                .clk(tclk),
                .si(clk_pad_clk_si), .so(clk_pad_clk_so), .se(clk_pad_clk_se));

wire clk_out = clk_value & dram_io_clk_enable_d1;

wire enable_mux_val = dram_io_clk_enable_d1 ? ~clk_out : clk_out;

assign to_pad = clk ? clk_out : enable_mux_val;

endmodule