data/full_repos/permissive/440081696/baud_rate_gen.v
1: b'%Warning-WIDTH: data/full_repos/permissive/440081696/baud_rate_gen.v:27: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                       : ... In instance baud_rate_gen\nassign rxclk_en_o = (rx_acc == 5\'d0);\n                            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/440081696/baud_rate_gen.v:28: Operator EQ expects 10 bits on the RHS, but RHS\'s CONST \'9\'h0\' generates 9 bits.\n                                                                       : ... In instance baud_rate_gen\nassign txclk_en_o = (tx_acc == 9\'d0);\n                            ^~\n%Error: Exiting due to 2 warning(s)\n'
module baud_rate_gen(
  input       clk_50m_i,
  input       rst_n_i,
  output wire rxclk_en_o,
  output wire txclk_en_o
);
parameter CLK_HZ        = 50000000,
          RX_ACC_MAX    = CLK_HZ / (115200 * 16),
          TX_ACC_MAX    = CLK_HZ / 115200,


          RX_ACC_WIDTH  = $clog2(RX_ACC_MAX)+1,
          TX_ACC_WIDTH  = $clog2(TX_ACC_MAX)+1;

reg [RX_ACC_WIDTH - 1:0] rx_acc;
reg [TX_ACC_WIDTH - 1:0] tx_acc;

assign rxclk_en_o = (rx_acc == 5'd0);
assign txclk_en_o = (tx_acc == 9'd0);

always @(posedge clk_50m_i or negedge rst_n_i) begin
  if(!rst_n_i) begin
    rx_acc      <= 0;
    tx_acc      <= 0;
  end
  else begin

    if(rx_acc == RX_ACC_MAX[RX_ACC_WIDTH - 1:0])
      rx_acc    <= 0;
    else
      rx_acc    <= rx_acc + {{(RX_ACC_WIDTH - 1){1'b0}},1'b1};

    if (tx_acc == TX_ACC_MAX[TX_ACC_WIDTH - 1:0])
      tx_acc    <= 0;
    else
      tx_acc    <= tx_acc + {{(TX_ACC_WIDTH - 1){1'b0}},1'b1};
  end
end

endmodule
module baud_rate_gen(
  input       clk_50m_i,
  input       rst_n_i,
  output wire rxclk_en_o,
  output wire txclk_en_o
);

parameter CLK_HZ        = 50000000,
          RX_ACC_MAX    = CLK_HZ / (115200 * 16),
          TX_ACC_MAX    = CLK_HZ / 115200,


          RX_ACC_WIDTH  = $clog2(RX_ACC_MAX)+1,
          TX_ACC_WIDTH  = $clog2(TX_ACC_MAX)+1;

reg [RX_ACC_WIDTH - 1:0] rx_acc;
reg [TX_ACC_WIDTH - 1:0] tx_acc;

assign rxclk_en_o = (rx_acc == 5'd0);
assign txclk_en_o = (tx_acc == 9'd0);

always @(posedge clk_50m_i or negedge rst_n_i) begin
  if(!rst_n_i) begin
    rx_acc      <= 0;
    tx_acc      <= 0;
  end
  else begin

    if(rx_acc == RX_ACC_MAX[RX_ACC_WIDTH - 1:0])
      rx_acc    <= 0;
    else
      rx_acc    <= rx_acc + {{(RX_ACC_WIDTH - 1){1'b0}},1'b1};

    if (tx_acc == TX_ACC_MAX[TX_ACC_WIDTH - 1:0])
      tx_acc    <= 0;
    else
      tx_acc    <= tx_acc + {{(TX_ACC_WIDTH - 1){1'b0}},1'b1};
  end
end

endmodule