data/full_repos/permissive/447976230/fpga/usrp1/toplevel/sizetest/sizetest.v
1: b"%Error: data/full_repos/permissive/447976230/fpga/usrp1/toplevel/sizetest/sizetest.v:35: Duplicate declaration of signal: 'zo'\n                                                                                       : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nwire [16:0] zo;\n            ^~\n        data/full_repos/permissive/447976230/fpga/usrp1/toplevel/sizetest/sizetest.v:31: ... Location of original declaration\n    output [15:0] zo\n                  ^~\n%Error: Exiting due to 1 error(s)\n"
module sizetest(input clock, 
				input reset, 
				input enable, 
				input [15:0]xi, 
				input [15:0] yi, 
				input [15:0] zi, 
				output [15:0] xo, 
				output [15:0] yo,
				output [15:0] zo

				);

wire [16:0] zo;

cordic_stage cordic_stage(clock, reset, enable, xi, yi, zi, 16'd16383, xo, yo, zo );

endmodule
module sizetest(input clock, 
				input reset, 
				input enable, 
				input [15:0]xi, 
				input [15:0] yi, 
				input [15:0] zi, 
				output [15:0] xo, 
				output [15:0] yo,
				output [15:0] zo

				);


wire [16:0] zo;

cordic_stage cordic_stage(clock, reset, enable, xi, yi, zi, 16'd16383, xo, yo, zo );

endmodule