data/full_repos/permissive/463481430/RTL/core/ifu_fetch.v
1: b'%Error: data/full_repos/permissive/463481430/RTL/core/ifu_fetch.v:18: Cannot find include file: config.v\n`include "config.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463481430/RTL/core,data/full_repos/permissive/463481430/config.v\n             data/full_repos/permissive/463481430/RTL/core,data/full_repos/permissive/463481430/config.v.v\n             data/full_repos/permissive/463481430/RTL/core,data/full_repos/permissive/463481430/config.v.sv\n             config.v\n             config.v.v\n             config.v.sv\n             obj_dir/config.v\n             obj_dir/config.v.v\n             obj_dir/config.v.sv\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu_fetch.v:28: Define or directive not defined: \'`xlen_def\'\n    input wire[`xlen_def] i_fetch_addr,\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu_fetch.v:28: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire[`xlen_def] i_fetch_addr,\n                        ^\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu_fetch.v:32: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire i_jump_flag,\n    ^~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu_fetch.v:35: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire o_pc_vld,\n    ^~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu_fetch.v:37: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire o_access_vld,\n    ^~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu_fetch.v:39: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire o_data_vld,\n    ^~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu_fetch.v:42: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire[`ilen_def] o_data,\n    ^~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu_fetch.v:42: Define or directive not defined: \'`ilen_def\'\n                                                                    : ... Suggested alternative: \'`ifndef\'\n    output wire[`ilen_def] o_data,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu_fetch.v:47: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire o_ribm_wrcs, \n    ^~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu_fetch.v:48: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire[3:0] o_ribm_mask,  \n    ^~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu_fetch.v:49: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire[31:0] o_ribm_wdata,  \n    ^~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu_fetch.v:50: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire[31:0] i_ribm_rdata,\n    ^~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu_fetch.v:52: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire o_ribm_req,  \n    ^~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu_fetch.v:53: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire i_ribm_gnt,  \n    ^~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu_fetch.v:54: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire i_ribm_rsp,  \n    ^~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu_fetch.v:55: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire o_ribm_rdy  \n    ^~~~~~\n%Error: data/full_repos/permissive/463481430/RTL/core/ifu_fetch.v:74: syntax error, unexpected always\n    always @(posedge i_clk or negedge i_rstn) begin\n    ^~~~~~\n%Error: Exiting due to 18 error(s)\n'
module IFU_FETCH (
    input wire i_clk,
    input wire i_rstn,


    input wire[`xlen_def] i_fetch_addr,

    input wire i_fetch_vld,

    input wire i_jump_flag,


    output wire o_pc_vld,

    output wire o_access_vld,

    output wire o_data_vld,


    output wire[`ilen_def] o_data,



    output wire[31:0] o_ribm_addr,
    output wire o_ribm_wrcs,
    output wire[3:0] o_ribm_mask,
    output wire[31:0] o_ribm_wdata,
    input  wire[31:0] i_ribm_rdata,

    output wire o_ribm_req,
    input wire i_ribm_gnt,
    input wire i_ribm_rsp,
    output wire o_ribm_rdy
);


    assign o_ribm_wrcs = 0;
    assign o_ribm_mask = 4'b1111;
    assign o_ribm_wdata = 0;

    assign o_ribm_req = i_rstn & i_fetch_vld;
    assign o_ribm_rdy = i_ribm_rsp;


    wire handshake_rdy = o_ribm_req & i_ribm_gnt;

    wire access_rdy = i_ribm_rsp;
    reg handshake_rdy_last;

    wire trans_finish = handshake_rdy_last & access_rdy;

    always @(posedge i_clk or negedge i_rstn) begin
        if(~i_rstn)begin
            handshake_rdy_last <= 0;
        end
        else begin

            if(i_jump_flag & (~handshake_rdy))begin
                handshake_rdy_last<=0;
            end
            else 
            if(i_fetch_vld )begin
                if(access_rdy | (~handshake_rdy_last))begin
                handshake_rdy_last <= handshake_rdy;
                end
            end
            else begin
                handshake_rdy_last <= 0;
            end
        end
    end


    assign o_pc_vld =  handshake_rdy;
    assign o_access_vld = access_rdy;
    assign o_data_vld =  trans_finish;

    assign o_data = i_ribm_rdata;
    assign o_ribm_addr = {i_fetch_addr[31:2],2'd0};

endmodule
module IFU_FETCH (
    input wire i_clk,
    input wire i_rstn,


    input wire[`xlen_def] i_fetch_addr,

    input wire i_fetch_vld,

    input wire i_jump_flag,


    output wire o_pc_vld,

    output wire o_access_vld,

    output wire o_data_vld,


    output wire[`ilen_def] o_data,



    output wire[31:0] o_ribm_addr,
    output wire o_ribm_wrcs,
    output wire[3:0] o_ribm_mask,
    output wire[31:0] o_ribm_wdata,
    input  wire[31:0] i_ribm_rdata,

    output wire o_ribm_req,
    input wire i_ribm_gnt,
    input wire i_ribm_rsp,
    output wire o_ribm_rdy
);



    assign o_ribm_wrcs = 0;
    assign o_ribm_mask = 4'b1111;
    assign o_ribm_wdata = 0;

    assign o_ribm_req = i_rstn & i_fetch_vld;
    assign o_ribm_rdy = i_ribm_rsp;


    wire handshake_rdy = o_ribm_req & i_ribm_gnt;

    wire access_rdy = i_ribm_rsp;
    reg handshake_rdy_last;

    wire trans_finish = handshake_rdy_last & access_rdy;

    always @(posedge i_clk or negedge i_rstn) begin
        if(~i_rstn)begin
            handshake_rdy_last <= 0;
        end
        else begin

            if(i_jump_flag & (~handshake_rdy))begin
                handshake_rdy_last<=0;
            end
            else 
            if(i_fetch_vld )begin
                if(access_rdy | (~handshake_rdy_last))begin
                handshake_rdy_last <= handshake_rdy;
                end
            end
            else begin
                handshake_rdy_last <= 0;
            end
        end
    end


    assign o_pc_vld =  handshake_rdy;
    assign o_access_vld = access_rdy;
    assign o_data_vld =  trans_finish;

    assign o_data = i_ribm_rdata;
    assign o_ribm_addr = {i_fetch_addr[31:2],2'd0};

endmodule