data/full_repos/permissive/492462267/pc_reg.v
1: b'%Error: data/full_repos/permissive/492462267/pc_reg.v:1: Cannot find include file: define.vh\n`include "define.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh.v\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh.sv\n             define.vh\n             define.vh.v\n             define.vh.sv\n             obj_dir/define.vh\n             obj_dir/define.vh.v\n             obj_dir/define.vh.sv\n%Error: data/full_repos/permissive/492462267/pc_reg.v:14: Define or directive not defined: \'`InstAddrBus\'\n    output  reg[`InstAddrBus]    pc      \n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/pc_reg.v:14: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    output  reg[`InstAddrBus]    pc      \n                            ^\n%Error: data/full_repos/permissive/492462267/pc_reg.v:19: Define or directive not defined: \'`Disable\'\n        ce <= `Disable;                  \n              ^~~~~~~~\n%Error: data/full_repos/permissive/492462267/pc_reg.v:21: Define or directive not defined: \'`Enable\'\n        ce <= `Enable;                   \n              ^~~~~~~\n%Error: data/full_repos/permissive/492462267/pc_reg.v:29: Define or directive not defined: \'`ZeroWord\'\n        pc <= `ZeroWord;\n              ^~~~~~~~~\n%Error: Exiting due to 6 error(s)\n'
module pc_reg (
    input   wire        clk,
    input   wire        rst,
    input   wire[5:0]   stall,

    output  reg     ce,
    output  reg[`InstAddrBus]    pc
);

always @(posedge clk) begin
    if (rst) begin
        ce <= `Disable;
    end else begin
        ce <= `Enable;
    end
end


always @(posedge clk) begin

    if(~ce) begin
        pc <= `ZeroWord;
    end 

    else if(!stall[0])begin
        pc <= pc + 4;
    end 
    else begin
        pc <= pc;
    end
end

endmodule
module pc_reg (
    input   wire        clk,
    input   wire        rst,
    input   wire[5:0]   stall,

    output  reg     ce,
    output  reg[`InstAddrBus]    pc
);


always @(posedge clk) begin
    if (rst) begin
        ce <= `Disable;
    end else begin
        ce <= `Enable;
    end
end


always @(posedge clk) begin

    if(~ce) begin
        pc <= `ZeroWord;
    end 

    else if(!stall[0])begin
        pc <= pc + 4;
    end 
    else begin
        pc <= pc;
    end
end

endmodule