data/full_repos/permissive/435890256/my_riscv/instr_rom.sv
1: b'%Error: data/full_repos/permissive/435890256/my_riscv/instr_rom.sv:3: Cannot find include file: dualport_bus.sv\n`include "dualport_bus.sv" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/435890256/my_riscv,data/full_repos/permissive/435890256/dualport_bus.sv\n             data/full_repos/permissive/435890256/my_riscv,data/full_repos/permissive/435890256/dualport_bus.sv.v\n             data/full_repos/permissive/435890256/my_riscv,data/full_repos/permissive/435890256/dualport_bus.sv.sv\n             dualport_bus.sv\n             dualport_bus.sv.v\n             dualport_bus.sv.sv\n             obj_dir/dualport_bus.sv\n             obj_dir/dualport_bus.sv.v\n             obj_dir/dualport_bus.sv.sv\n%Error: Exiting due to 1 error(s)\n'
module instr_rom(
  input logic clk,
  input logic rst_n,
  dualport_bus.slave instr_slave
);
localparam  INSTR_CNT = 30'd22;
wire [0:INSTR_CNT-1] [31:0] instr_rom_cell = {
  32'h00708093,   

  32'h00710113,   

  32'h00110863,

  32'h002081b3,   

  32'h00720213,  

  32'h00728293,   

  32'h002081b3,   

  32'h00708093,   

  32'h00710113,   

  32'h002081b3,   

  32'h00708093,   

  32'h00000013,   

  32'h00000013,

  32'h00710113,   

  32'h002081b3,   

  32'h00708093,  

  32'h00710113,   

  32'h002081b3,   

  32'hff9ff06f,   

  32'h00708093,   

  32'h00710113,   

  32'h002081b3    

};

logic [29:0] cell_rd_addr;

assign instr_slave.rd_gnt = instr_slave.rd_req;
assign instr_slave.wr_gnt = instr_slave.wr_req;
assign cell_rd_addr = instr_slave.rd_addr[31:2];
always_ff @ (posedge clk or negedge rst_n) begin
  if(~rst_n)
    instr_slave.rd_data <= 0;
  else begin
    if(instr_slave.rd_req)
      instr_slave.rd_data <= (cell_rd_addr>=INSTR_CNT) ? 0 : instr_rom_cell[cell_rd_addr];
    else
      instr_slave.rd_data <= 0;
    end
end

endmodule
module instr_rom(
  input logic clk,
  input logic rst_n,
  dualport_bus.slave instr_slave
);

localparam  INSTR_CNT = 30'd22;
wire [0:INSTR_CNT-1] [31:0] instr_rom_cell = {
  32'h00708093,   

  32'h00710113,   

  32'h00110863,

  32'h002081b3,   

  32'h00720213,  

  32'h00728293,   

  32'h002081b3,   

  32'h00708093,   

  32'h00710113,   

  32'h002081b3,   

  32'h00708093,   

  32'h00000013,   

  32'h00000013,

  32'h00710113,   

  32'h002081b3,   

  32'h00708093,  

  32'h00710113,   

  32'h002081b3,   

  32'hff9ff06f,   

  32'h00708093,   

  32'h00710113,   

  32'h002081b3    

};

logic [29:0] cell_rd_addr;

assign instr_slave.rd_gnt = instr_slave.rd_req;
assign instr_slave.wr_gnt = instr_slave.wr_req;
assign cell_rd_addr = instr_slave.rd_addr[31:2];
always_ff @ (posedge clk or negedge rst_n) begin
  if(~rst_n)
    instr_slave.rd_data <= 0;
  else begin
    if(instr_slave.rd_req)
      instr_slave.rd_data <= (cell_rd_addr>=INSTR_CNT) ? 0 : instr_rom_cell[cell_rd_addr];
    else
      instr_slave.rd_data <= 0;
    end
end

endmodule