data/full_repos/permissive/440081696/uart_control.v
1: b'%Warning-WIDTH: data/full_repos/permissive/440081696/uart_control.v:114: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'dout_rx\' generates 8 bits.\n                                                                       : ... In instance uart_control\n            dout_32b_o        <= dout_rx;\n                              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/440081696/uart_control.v:132: Cannot find file containing module: \'fifo_8b_512\'\nfifo_8b_512 data_rx(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/440081696,data/full_repos/permissive/440081696/fifo_8b_512\n             data/full_repos/permissive/440081696,data/full_repos/permissive/440081696/fifo_8b_512.v\n             data/full_repos/permissive/440081696,data/full_repos/permissive/440081696/fifo_8b_512.sv\n             fifo_8b_512\n             fifo_8b_512.v\n             fifo_8b_512.sv\n             obj_dir/fifo_8b_512\n             obj_dir/fifo_8b_512.v\n             obj_dir/fifo_8b_512.sv\n%Error: data/full_repos/permissive/440081696/uart_control.v:144: Cannot find file containing module: \'fifo_8b_512\'\nfifo_8b_512 data_tx(\n^~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module uart_control(
  input                 clk_50m_i,
  input                 rst_n_i,
  input         [31:0]  addr_32b_i,
  input                 wren_i,
  input                 rden_i,
  input         [31:0]  din_32b_i,
  output  reg           dout_32b_valid_o,
  output  reg   [31:0]  dout_32b_o,
  output  wire          interrupt_o,

  input         [7:0]   din_8b_i,
  input                 din_valid_i,
  output  wire  [7:0]   dout_8b_o,
  output  wire          dout_valid_o,
  input                 tx_busy_i
);

parameter BASE_ADDR     = 32'h10010000;

/

assign dout_8b_o = dout_tx;
assign dout_valid_o = rden_tx;

assign interrupt_o = ~empty_rx;

reg   [3:0] state_reg;
localparam    IDLE_S          = 4'd0;

always @(posedge clk_50m_i or negedge rst_n_i) begin
  if(!rst_n_i) begin
    rden_rx           <= 1'b0;
    rden_tx           <= 1'b0;
    wren_tx           <= 1'b0;
    din_tx            <= 8'b0;
    dout_32b_valid_o  <= 1'b0;
    dout_32b_o        <= 32'b0;
  end
  else begin

    if(empty_tx == 1'b0 && rden_tx == 1'b0 && tx_busy_i == 1'b0) begin
      rden_tx         <= 1'b1;
    end
    else begin
      rden_tx         <= 1'b0;
    end


    dout_32b_valid_o  <= 1'b0;
    wren_tx           <= 1'b0;
    rden_rx           <= 1'b0;
    case(state_reg)
      IDLE_S: begin
        if(addr_32b_i[31:16] == BASE_ADDR[31:16]) begin

          if(addr_32b_i[5:2] == 4'h0 && rden_i == 1'b1) begin
            dout_32b_valid_o  <= 1'b1;
            dout_32b_o        <= dout_rx;
            rden_rx           <= 1'b1;
          end
          else if(addr_32b_i[5:2] == 4'h1 && wren_i == 1'b1) begin
            wren_tx           <= 1'b1;
            din_tx            <= din_32b_i[7:0];
          end
        end
      end
      default: begin
        state_reg     <= IDLE_S;
      end
    endcase
  end
end



fifo_8b_512 data_rx(
  .clk(clk_50m_i),
  .srst(!rst_n_i),
  .din(din_8b_i),
  .wr_en(din_valid_i),
  .rd_en(rden_rx),
  .dout(dout_rx),
  .full(),
  .empty(empty_rx),
  .data_count()
);

fifo_8b_512 data_tx(
  .clk(clk_50m_i),
  .srst(!rst_n_i),
  .din(din_tx),
  .wr_en(wren_tx),
  .rd_en(rden_tx),
  .dout(dout_tx),
  .full(),
  .empty(empty_tx),
  .data_count()
);

endmodule
module uart_control(
  input                 clk_50m_i,
  input                 rst_n_i,
  input         [31:0]  addr_32b_i,
  input                 wren_i,
  input                 rden_i,
  input         [31:0]  din_32b_i,
  output  reg           dout_32b_valid_o,
  output  reg   [31:0]  dout_32b_o,
  output  wire          interrupt_o,

  input         [7:0]   din_8b_i,
  input                 din_valid_i,
  output  wire  [7:0]   dout_8b_o,
  output  wire          dout_valid_o,
  input                 tx_busy_i
);


parameter BASE_ADDR     = 32'h10010000;

/

assign dout_8b_o = dout_tx;
assign dout_valid_o = rden_tx;

assign interrupt_o = ~empty_rx;

reg   [3:0] state_reg;
localparam    IDLE_S          = 4'd0;

always @(posedge clk_50m_i or negedge rst_n_i) begin
  if(!rst_n_i) begin
    rden_rx           <= 1'b0;
    rden_tx           <= 1'b0;
    wren_tx           <= 1'b0;
    din_tx            <= 8'b0;
    dout_32b_valid_o  <= 1'b0;
    dout_32b_o        <= 32'b0;
  end
  else begin

    if(empty_tx == 1'b0 && rden_tx == 1'b0 && tx_busy_i == 1'b0) begin
      rden_tx         <= 1'b1;
    end
    else begin
      rden_tx         <= 1'b0;
    end


    dout_32b_valid_o  <= 1'b0;
    wren_tx           <= 1'b0;
    rden_rx           <= 1'b0;
    case(state_reg)
      IDLE_S: begin
        if(addr_32b_i[31:16] == BASE_ADDR[31:16]) begin

          if(addr_32b_i[5:2] == 4'h0 && rden_i == 1'b1) begin
            dout_32b_valid_o  <= 1'b1;
            dout_32b_o        <= dout_rx;
            rden_rx           <= 1'b1;
          end
          else if(addr_32b_i[5:2] == 4'h1 && wren_i == 1'b1) begin
            wren_tx           <= 1'b1;
            din_tx            <= din_32b_i[7:0];
          end
        end
      end
      default: begin
        state_reg     <= IDLE_S;
      end
    endcase
  end
end



fifo_8b_512 data_rx(
  .clk(clk_50m_i),
  .srst(!rst_n_i),
  .din(din_8b_i),
  .wr_en(din_valid_i),
  .rd_en(rden_rx),
  .dout(dout_rx),
  .full(),
  .empty(empty_rx),
  .data_count()
);

fifo_8b_512 data_tx(
  .clk(clk_50m_i),
  .srst(!rst_n_i),
  .din(din_tx),
  .wr_en(wren_tx),
  .rd_en(rden_tx),
  .dout(dout_tx),
  .full(),
  .empty(empty_tx),
  .data_count()
);

endmodule