data/full_repos/permissive/519551680/src/int-clk-div.sv
data/verilator_xmls/5632f8f4-3e6c-421e-94b9-181a9b9bfa15.xml
module int_clk_div #(
  parameter D = 3,
  parameter W = 2
) (
  input  clk,
  output out
);

  localparam up   = 0,
	     down = 1;
  logic [(W-1):0] count = 0;
  logic state;
  
  assign out = state;


  always @ (clk) begin
    case (state)
      up     : begin
		 count <= count + 1;
		 if (count == D-1)
		   state <= down;
		 else
		   state <= up;
	       end
      down   : begin
		 count <= count - 1;
		 if (count == 1)
		   state <= up;
		 else
		   state <= down;
	       end
      default: state <= up;






    endcase
  end
endmodule
module int_clk_div #(
  parameter D = 3,
  parameter W = 2
) (
  input  clk,
  output out
);


  localparam up   = 0,
	     down = 1;
  logic [(W-1):0] count = 0;
  logic state;
  
  assign out = state;


  always @ (clk) begin
    case (state)
      up     : begin
		 count <= count + 1;
		 if (count == D-1)
		   state <= down;
		 else
		   state <= up;
	       end
      down   : begin
		 count <= count - 1;
		 if (count == 1)
		   state <= up;
		 else
		   state <= down;
	       end
      default: state <= up;






    endcase
  end
endmodule