data/full_repos/permissive/419538859/lab7/lab7_2self/qts/lab7_2self.v
1: b'%Warning-WIDTH: data/full_repos/permissive/419538859/lab7/lab7_2self/qts/lab7_2self.v:516: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                         : ... In instance lab7_2self.u7.M4\n  cnt  =4\'d0;\n       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab7/lab7_2self/qts/lab7_2self.v:27: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s VARREF \'timer1\' generates 2 bits.\n                                                                                        : ... In instance lab7_2self\n    (seg7_sel == 3\'b100 )? timer1 :\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab7/lab7_2self/qts/lab7_2self.v:29: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s VARREF \'timer3\' generates 2 bits.\n                                                                                        : ... In instance lab7_2self\n    (seg7_sel == 3\'b010 )? timer3 :4\'b0;\n                         ^\n%Error: Exiting due to 3 warning(s)\n'
module bcd_to_seg7_1(bcd_in,seg7);

input	[3:0]bcd_in;
output	[6:0]seg7;
reg		[6:0]seg7;

always@ (bcd_in)
	case(bcd_in)
			4'b0000: seg7 = 7'b1111110;
			4'b0001: seg7 = 7'b0110000;
			4'b0010: seg7 = 7'b1101101;
			4'b0011: seg7 = 7'b1111001;
			4'b0100: seg7 = 7'b0110011;
			4'b0101: seg7 = 7'b1011011;
			4'b0110: seg7 = 7'b1011111;
			4'b0111: seg7 = 7'b1110000;
			4'b1000: seg7 = 7'b1111111;
			4'b1001: seg7 = 7'b1111011;
			default: seg7 = 7'b0000001; 
	endcase
endmodule
module bcd_to_seg7_1(bcd_in,seg7);


input	[3:0]bcd_in;
output	[6:0]seg7;
reg		[6:0]seg7;

always@ (bcd_in)
	case(bcd_in)
			4'b0000: seg7 = 7'b1111110;
			4'b0001: seg7 = 7'b0110000;
			4'b0010: seg7 = 7'b1101101;
			4'b0011: seg7 = 7'b1111001;
			4'b0100: seg7 = 7'b0110011;
			4'b0101: seg7 = 7'b1011011;
			4'b0110: seg7 = 7'b1011111;
			4'b0111: seg7 = 7'b1110000;
			4'b1000: seg7 = 7'b1111111;
			4'b1001: seg7 = 7'b1111011;
			default: seg7 = 7'b0000001; 
	endcase
endmodule