data/full_repos/permissive/450922687/Task 1/design.sv
1: b'%Error: Cannot find file containing module: 1,data/full_repos/permissive/450922687\n        ... Looked in:\n             data/full_repos/permissive/450922687/Task/1,data/full_repos/permissive/450922687\n             data/full_repos/permissive/450922687/Task/1,data/full_repos/permissive/450922687.v\n             data/full_repos/permissive/450922687/Task/1,data/full_repos/permissive/450922687.sv\n             1,data/full_repos/permissive/450922687\n             1,data/full_repos/permissive/450922687.v\n             1,data/full_repos/permissive/450922687.sv\n             obj_dir/1,data/full_repos/permissive/450922687\n             obj_dir/1,data/full_repos/permissive/450922687.v\n             obj_dir/1,data/full_repos/permissive/450922687.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/450922687/Task\n%Error: Cannot find file containing module: 1/design.sv\n%Error: Exiting due to 3 error(s)\n'
module RISC_V_Processor(
	input clk,
	input reset);



  wire [63:0] out_adder1;
  wire [63:0] b1;
  wire [63:0] out_adder2;




  wire [3:0] Operation;
    wire [3:0] functx;
  wire [2:0] funct_out;


  wire [1:0] ALUOp;
  wire Branch,MemRead,MemtoReg,MemWrite,ALUSrc,Regwrite;




  wire [63:0] Read_Data;


  wire [63:0] imm_data;
  assign b1 = imm_data << 1;


  wire [31:0] Instruction;



  wire [6:0] opcode;
  wire [4:0] rd;
  wire [2:0] func3;
  wire [4:0] rs1;
  wire [4:0] rs2;
  wire [6:0] func7;




  wire sel;
  wire [63:0] data_out;
  wire [63:0] data_out1;


  wire [63:0] Result;
  wire equal_;


  wire [4:0] RS1;
  wire [4:0] RS2;
  wire [4:0] RD;
  wire [63:0] ReadData1;
  wire [63:0] ReadData2;
wire [63:0] data_out2;


  wire [63:0] PC_Out;

  wire [63:0] b;
  assign b = 64'd4;
  assign sel = (Branch & equal_);
  assign functx = {Instruction[30] ,Instruction[14:12]};
 
pc_counter pc(
  .PC_In(data_out),
  .reset(reset),
  .clk(clk),
  .PC_Out(PC_Out)
);
  
adder adder1(
  .a(PC_Out), 
  .b(b), 
  .out(out_adder1)
);
  
instruction_memory  ins_mem(
  .Inst_Address(PC_Out),
  .Instruction(Instruction)
);
  
  
instruction_parser ins_par(
  .ins(Instruction),
  .opcode(opcode),
  .rd(rd),
  .func3(func3),
  .rs1(rs1),
  .rs2(rs2),
  .func7(func7)
);
  
Control_Unit ctrl_unit(
  .Opcode(opcode),
  .ALUOp(ALUOp),
  .Branch(Branch),
  .MemRead(MemRead),
  .MemtoReg(MemtoReg),
  .MemWrite(MemWrite),
  .ALUSrc(ALUSrc),
  .Regwrite(Regwrite)
);
  
  
registerFile reg_file(
  .clk(clk),
  .reset(reset),
  .RegWrite(Regwrite),
  .WriteData(data_out2),
  .RS1(rs1),
  .RS2(rs2),
  .RD(rd),
  .ReadData1(ReadData1),
  .ReadData2(ReadData2)
);
  
dataExtract ext(
  .instruction(Instruction),
  .imm_data(imm_data)
);
  
ALU_Control  alu_ctrl(
  .ALUOp(ALUOp),
  .Funct(functx),
  .Operation(Operation),
  .FunctOut(funct_out) 
);
  
  
  mux2_1 mux1( 
  .a(ReadData2),
  .b(imm_data),
  .sel(ALUSrc),
  .data_out(data_out1)
);
  
alu_64 alu64(
  .a(ReadData1),
  .b(data_out1),
  .ALUOp(Operation),
  .funct(funct_out),
  .Result(Result),
  .equal(equal_)
);

  adder adder2( 
    .a(PC_Out), 
    .b(b1), 
  .out(out_adder2)
);
  
  
  mux2_1 mux2( 
    .a(out_adder1),
    .b(out_adder2),
    .sel(sel), 
  .data_out(data_out)
);
  
Data_Memory  data_mem(
  .Mem_Addr(Result),
  .Write_Data(ReadData2),
  .clk(clk),
  .MemWrite(MemWrite),
  .MemRead(MemRead),
  .Read_Data(Read_Data)
);
  
  mux2_1 mux3(
  .a(Result),
  .b(Read_Data),
  .sel(MemtoReg),
  .data_out(data_out2)
);
  
	
endmodule
module RISC_V_Processor(
	input clk,
	input reset);




  wire [63:0] out_adder1;
  wire [63:0] b1;
  wire [63:0] out_adder2;




  wire [3:0] Operation;
    wire [3:0] functx;
  wire [2:0] funct_out;


  wire [1:0] ALUOp;
  wire Branch,MemRead,MemtoReg,MemWrite,ALUSrc,Regwrite;




  wire [63:0] Read_Data;


  wire [63:0] imm_data;
  assign b1 = imm_data << 1;


  wire [31:0] Instruction;



  wire [6:0] opcode;
  wire [4:0] rd;
  wire [2:0] func3;
  wire [4:0] rs1;
  wire [4:0] rs2;
  wire [6:0] func7;




  wire sel;
  wire [63:0] data_out;
  wire [63:0] data_out1;


  wire [63:0] Result;
  wire equal_;


  wire [4:0] RS1;
  wire [4:0] RS2;
  wire [4:0] RD;
  wire [63:0] ReadData1;
  wire [63:0] ReadData2;
wire [63:0] data_out2;


  wire [63:0] PC_Out;

  wire [63:0] b;
  assign b = 64'd4;
  assign sel = (Branch & equal_);
  assign functx = {Instruction[30] ,Instruction[14:12]};
 
pc_counter pc(
  .PC_In(data_out),
  .reset(reset),
  .clk(clk),
  .PC_Out(PC_Out)
);
  
adder adder1(
  .a(PC_Out), 
  .b(b), 
  .out(out_adder1)
);
  
instruction_memory  ins_mem(
  .Inst_Address(PC_Out),
  .Instruction(Instruction)
);
  
  
instruction_parser ins_par(
  .ins(Instruction),
  .opcode(opcode),
  .rd(rd),
  .func3(func3),
  .rs1(rs1),
  .rs2(rs2),
  .func7(func7)
);
  
Control_Unit ctrl_unit(
  .Opcode(opcode),
  .ALUOp(ALUOp),
  .Branch(Branch),
  .MemRead(MemRead),
  .MemtoReg(MemtoReg),
  .MemWrite(MemWrite),
  .ALUSrc(ALUSrc),
  .Regwrite(Regwrite)
);
  
  
registerFile reg_file(
  .clk(clk),
  .reset(reset),
  .RegWrite(Regwrite),
  .WriteData(data_out2),
  .RS1(rs1),
  .RS2(rs2),
  .RD(rd),
  .ReadData1(ReadData1),
  .ReadData2(ReadData2)
);
  
dataExtract ext(
  .instruction(Instruction),
  .imm_data(imm_data)
);
  
ALU_Control  alu_ctrl(
  .ALUOp(ALUOp),
  .Funct(functx),
  .Operation(Operation),
  .FunctOut(funct_out) 
);
  
  
  mux2_1 mux1( 
  .a(ReadData2),
  .b(imm_data),
  .sel(ALUSrc),
  .data_out(data_out1)
);
  
alu_64 alu64(
  .a(ReadData1),
  .b(data_out1),
  .ALUOp(Operation),
  .funct(funct_out),
  .Result(Result),
  .equal(equal_)
);

  adder adder2( 
    .a(PC_Out), 
    .b(b1), 
  .out(out_adder2)
);
  
  
  mux2_1 mux2( 
    .a(out_adder1),
    .b(out_adder2),
    .sel(sel), 
  .data_out(data_out)
);
  
Data_Memory  data_mem(
  .Mem_Addr(Result),
  .Write_Data(ReadData2),
  .clk(clk),
  .MemWrite(MemWrite),
  .MemRead(MemRead),
  .Read_Data(Read_Data)
);
  
  mux2_1 mux3(
  .a(Result),
  .b(Read_Data),
  .sel(MemtoReg),
  .data_out(data_out2)
);
  
	
endmodule