data/full_repos/permissive/521337848/Hardware/GRAPHICS/VGAGen.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/521337848/Hardware/GRAPHICS/VGAGen.v:166: Cell has missing pin: \'cclk\'\noutputVideo oV(.clk(clk),\n            ^~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-MULTITOP: data/full_repos/permissive/521337848/Hardware/GRAPHICS/VGAGen.v:40: Multiple top level modules\n                                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                     : ... Top module \'collector\'\nmodule collector(\n       ^~~~~~~~~\n                                                                                     : ... Top module \'lastBlock\'\nmodule lastBlock(\n       ^~~~~~~~~\n                                                                                     : ... Top module \'buffer9\'\nmodule buffer9(\n       ^~~~~~~\n                                                                                     : ... Top module \'next\'\nmodule next(\n       ^~~~\n                                                                                     : ... Top module \'clkdiv\'\nmodule clkdiv(\n       ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/521337848/Hardware/GRAPHICS/VGAGen.v:113: Signal definition not found, creating implicitly: \'ins4\'\n                                                                                      : ... Suggested alternative: \'ins\'\nbuffer b13(.clk(dclk),.in(ins3),.out(ins4));\n                                     ^~~~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/GRAPHICS/VGAGen.v:155: Input port connection \'CounterX\' expects 10 bits on the pin connection, but pin connection\'s VARREF \'xc2\' generates 1 bits.\n                                                                                   : ... In instance lastBlock\n    .CounterX(xc2),\n     ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/GRAPHICS/VGAGen.v:156: Input port connection \'CounterY\' expects 9 bits on the pin connection, but pin connection\'s VARREF \'yc2\' generates 1 bits.\n                                                                                   : ... In instance lastBlock\n    .CounterY(yc2),\n     ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/GRAPHICS/VGAGen.v:354: Operator ASSIGNW expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                   : ... In instance next\nassign out = {CounterX[6:2],3\'b0};\n           ^\n%Error: Exiting due to 6 warning(s)\n'
module lastBlock(
	
	input dclk,
	input clk,
	input rst,
	input splash,
	
	input xhsync,
	input xvsync,
	
	input[4:0] col,
	
	input ins,
	input[9:0] CounterX,
	input[8:0] CounterY,
	
	output R,
	output G,
	output B,
	
	output hsync,
	output vsync
);


wire xc;
wire yc;

wire xc1;
wire yc1;

wire xc2;
wire yc2;


wire xhsync1;
wire xvsync1;

wire xhsync2;
wire xvsync2;

wire xhsync3;
wire xvsync3;

wire xhsync4;
wire xvsync4;

wire ins1;
wire ins2;
wire ins3;

buffer b15(.clk(dclk),.in(CounterX[0]),.out(xc));
buffer b16(.clk(dclk),.in(xc),.out(xc1));
buffer b17(.clk(dclk),.in(xc1),.out(xc2));

buffer b18(.clk(dclk),.in(CounterY[0]),.out(yc));
buffer b19(.clk(dclk),.in(yc),.out(yc1));
buffer b20(.clk(dclk),.in(yc1),.out(yc2));
				 
buffer b1(.clk(dclk),.in(xhsync),.out(xhsync1));
buffer b2(.clk(dclk),.in(xvsync),.out(xvsync1));
buffer b10(.clk(dclk),.in(ins),.out(ins1));

buffer b3(.clk(dclk),.in(xhsync1),.out(xhsync2));
buffer b4(.clk(dclk),.in(xvsync1),.out(xvsync2));
buffer b11(.clk(dclk),.in(ins1),.out(ins2));

buffer b5(.clk(dclk),.in(xhsync2),.out(xhsync3));
buffer b6(.clk(dclk),.in(xvsync2),.out(xvsync3));
buffer b12(.clk(dclk),.in(ins2),.out(ins3));

buffer b8(.clk(dclk),.in(xhsync3),.out(xhsync4));
buffer b9(.clk(dclk),.in(xvsync3),.out(xvsync4));
buffer b13(.clk(dclk),.in(ins3),.out(ins4));

wire[4:0] col41;
wire[4:0] col42;
buffer4 b22(.clk(dclk),.in(col),.out(col41));
buffer4 b23(.clk(dclk),.in(col41),.out(col42));

wire comb;
wire comb1;
wire comb2;



combiner com(.clk(dclk),
				 .rst(rst),
				 .CounterX(CounterX),
				 .CounterY(CounterY),
	
				 .comb(comb)
	
);

buffer b7(.clk(dclk),.in(comb),.out(comb1));
buffer b14(.clk(dclk),.in(comb1),.out(comb2));

wire[5:0] color;

wire xR;
wire xG;
wire xB;

wire iscolmix;
wire[2:0] colmix;

colorDecoder cD(.clk(dclk),
					 .inCol(col42),
	
					 .decCol(color)
);

mixer mix(.clk(clk),
	
			 .CounterX(xc2),
			 .CounterY(yc2),
	
			 .color(color),
			 .comb(comb2),
			
			 .R(xR),
			 .G(xG),
			 .B(xB)
);

outputVideo oV(.clk(clk),
	
			.xR(xR),
			.xG(xG),
			.xB(xB),
			
			.ins(ins4 & splash),
			
			.xhsync(xhsync4),
			.xvsync(xvsync4),
			
			.hsync(hsync),
			.vsync(vsync),
			
			.R(R),
			.G(G),
			.B(B)
);

endmodule
module lastBlock(
	
	input dclk,
	input clk,
	input rst,
	input splash,
	
	input xhsync,
	input xvsync,
	
	input[4:0] col,
	
	input ins,
	input[9:0] CounterX,
	input[8:0] CounterY,
	
	output R,
	output G,
	output B,
	
	output hsync,
	output vsync
);



wire xc;
wire yc;

wire xc1;
wire yc1;

wire xc2;
wire yc2;


wire xhsync1;
wire xvsync1;

wire xhsync2;
wire xvsync2;

wire xhsync3;
wire xvsync3;

wire xhsync4;
wire xvsync4;

wire ins1;
wire ins2;
wire ins3;

buffer b15(.clk(dclk),.in(CounterX[0]),.out(xc));
buffer b16(.clk(dclk),.in(xc),.out(xc1));
buffer b17(.clk(dclk),.in(xc1),.out(xc2));

buffer b18(.clk(dclk),.in(CounterY[0]),.out(yc));
buffer b19(.clk(dclk),.in(yc),.out(yc1));
buffer b20(.clk(dclk),.in(yc1),.out(yc2));
				 
buffer b1(.clk(dclk),.in(xhsync),.out(xhsync1));
buffer b2(.clk(dclk),.in(xvsync),.out(xvsync1));
buffer b10(.clk(dclk),.in(ins),.out(ins1));

buffer b3(.clk(dclk),.in(xhsync1),.out(xhsync2));
buffer b4(.clk(dclk),.in(xvsync1),.out(xvsync2));
buffer b11(.clk(dclk),.in(ins1),.out(ins2));

buffer b5(.clk(dclk),.in(xhsync2),.out(xhsync3));
buffer b6(.clk(dclk),.in(xvsync2),.out(xvsync3));
buffer b12(.clk(dclk),.in(ins2),.out(ins3));

buffer b8(.clk(dclk),.in(xhsync3),.out(xhsync4));
buffer b9(.clk(dclk),.in(xvsync3),.out(xvsync4));
buffer b13(.clk(dclk),.in(ins3),.out(ins4));

wire[4:0] col41;
wire[4:0] col42;
buffer4 b22(.clk(dclk),.in(col),.out(col41));
buffer4 b23(.clk(dclk),.in(col41),.out(col42));

wire comb;
wire comb1;
wire comb2;



combiner com(.clk(dclk),
				 .rst(rst),
				 .CounterX(CounterX),
				 .CounterY(CounterY),
	
				 .comb(comb)
	
);

buffer b7(.clk(dclk),.in(comb),.out(comb1));
buffer b14(.clk(dclk),.in(comb1),.out(comb2));

wire[5:0] color;

wire xR;
wire xG;
wire xB;

wire iscolmix;
wire[2:0] colmix;

colorDecoder cD(.clk(dclk),
					 .inCol(col42),
	
					 .decCol(color)
);

mixer mix(.clk(clk),
	
			 .CounterX(xc2),
			 .CounterY(yc2),
	
			 .color(color),
			 .comb(comb2),
			
			 .R(xR),
			 .G(xG),
			 .B(xB)
);

outputVideo oV(.clk(clk),
	
			.xR(xR),
			.xG(xG),
			.xB(xB),
			
			.ins(ins4 & splash),
			
			.xhsync(xhsync4),
			.xvsync(xvsync4),
			
			.hsync(hsync),
			.vsync(vsync),
			
			.R(R),
			.G(G),
			.B(B)
);

endmodule