data/full_repos/permissive/479094658/HA_D_testbench.v
1: b'%Error: data/full_repos/permissive/479094658/HA_D_testbench.v:13: Unsupported or unknown PLI call: $monitor\n    $monitor($time, "a=%b, b=%b, s=%b, c=%b", a, b, s, c);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/479094658/HA_D_testbench.v:18: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(1, HA_D_testbench);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/479094658/HA_D_testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #0  a=0; b=0;  \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/479094658/HA_D_testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #50 a=0; b=1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/479094658/HA_D_testbench.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #50 a=1; b=0;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/479094658/HA_D_testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #50 a=1; b=1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/479094658/HA_D_testbench.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #50 $finish;\n    ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module HA_D_testbench();
  
  reg a, b;
  wire s, c;
  
  HA_D DUT (.a(a), .b(b), .s(s), .c(c));
  
  initial
  begin
    $monitor($time, "a=%b, b=%b, s=%b, c=%b", a, b, s, c);
  end
  
  initial
  begin
    $dumpvars(1, HA_D_testbench);
    #0  a=0; b=0;
    #50 a=0; b=1;
    #50 a=1; b=0;
    #50 a=1; b=1;
    #50 $finish;
  end
endmodule
module HA_D_testbench();

  
  reg a, b;
  wire s, c;
  
  HA_D DUT (.a(a), .b(b), .s(s), .c(c));
  
  initial
  begin
    $monitor($time, "a=%b, b=%b, s=%b, c=%b", a, b, s, c);
  end
  
  initial
  begin
    $dumpvars(1, HA_D_testbench);
    #0  a=0; b=0;
    #50 a=0; b=1;
    #50 a=1; b=0;
    #50 a=1; b=1;
    #50 $finish;
  end
endmodule