data/full_repos/permissive/441216763/ALU.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441216763/ALU.v:275: Multiple top level modules\n                                                                 : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                 : ... Top module \'ALU\'\nmodule ALU(OP,A,B,Rst,clk,F,ZF,CF,OF,SF,PF);\n       ^~~\n                                                                 : ... Top module \'fulladder\'\nmodule fulladder(\n       ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/441216763/ALU.v:252: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                              : ... In instance ALU\n            4\'b0110:begin F=A<B; end     \n                           ^\n%Error: Exiting due to 2 warning(s)\n'
module shiftrne(R,L,E,w,clk,Q);

   parameter n=32;
	input [n-1:0] R;
	input L,E,w,clk;
	output reg [n-1:0] Q;

	integer k;

	always @(posedge clk) begin
	   if(L)
		  Q<=R;
		else if(E) begin
		   for(k=n-1; k>0; k=k-1)
			   Q[k-1] <= Q[k];
			Q[n-1] <=w;
		end
	end

endmodule
module shiftrne(R,L,E,w,clk,Q);


   parameter n=32;
	input [n-1:0] R;
	input L,E,w,clk;
	output reg [n-1:0] Q;

	integer k;

	always @(posedge clk) begin
	   if(L)
		  Q<=R;
		else if(E) begin
		   for(k=n-1; k>0; k=k-1)
			   Q[k-1] <= Q[k];
			Q[n-1] <=w;
		end
	end

endmodule