data/full_repos/permissive/514354758/testbench/tb_top.v
1: b'%Error: data/full_repos/permissive/514354758/testbench/tb_top.v:2: Cannot find include file: top.v\n`include "top.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514354758/testbench,data/full_repos/permissive/514354758/top.v\n             data/full_repos/permissive/514354758/testbench,data/full_repos/permissive/514354758/top.v.v\n             data/full_repos/permissive/514354758/testbench,data/full_repos/permissive/514354758/top.v.sv\n             top.v\n             top.v.v\n             top.v.sv\n             obj_dir/top.v\n             obj_dir/top.v.v\n             obj_dir/top.v.sv\n%Error: data/full_repos/permissive/514354758/testbench/tb_top.v:3: Cannot find include file: image_read.v\n`include "image_read.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/514354758/testbench/tb_top.v:4: Cannot find include file: remover.v\n`include "remover.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/514354758/testbench/tb_top.v:5: Cannot find include file: image_write.v\n`include "image_write.v" \n         ^~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/514354758/testbench/tb_top.v:19: Unsupported: Ignoring delay on this delayed statement.\n    always #10 HCLK = ~HCLK;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/514354758/testbench/tb_top.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #25 HRESETn = 1;\n        ^\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module tb_top;
    reg HCLK;
    reg HRESETn;
    wire VSYNC;
    wire HSYNC;
    wire [7:0] data;
    wire [7:0] VGA_data;
    wire ctrl_done;
    wire write_done;

    top top_inst(HCLK,HRESETn,VSYNC,HSYNC,data,VGA_data,ctrl_done,write_done);

    always #10 HCLK = ~HCLK;

    initial begin
        HCLK = 0;
        HRESETn = 0;
        #25 HRESETn = 1;
    end

endmodule
module tb_top;

    reg HCLK;
    reg HRESETn;
    wire VSYNC;
    wire HSYNC;
    wire [7:0] data;
    wire [7:0] VGA_data;
    wire ctrl_done;
    wire write_done;

    top top_inst(HCLK,HRESETn,VSYNC,HSYNC,data,VGA_data,ctrl_done,write_done);

    always #10 HCLK = ~HCLK;

    initial begin
        HCLK = 0;
        HRESETn = 0;
        #25 HRESETn = 1;
    end

endmodule