data/full_repos/permissive/515598112/3_Circuits/02_Sequential_Logic/01_Latches_and_Flip-Flops/09_DFF.v
data/verilator_xmls/7aa55dd5-cc78-4684-b029-1d5f506d70f2.xml
module top_module (
    input clk,
    input d, 
    input r,
    output reg q
);
    
    always @(posedge clk) begin
        q <= r ? 1'b0 : d;
    end

endmodule
module top_module (
    input clk,
    input d, 
    input r,
    output reg q
);

    
    always @(posedge clk) begin
        q <= r ? 1'b0 : d;
    end

endmodule