data/full_repos/permissive/528287433/NValuesAdder.v
data/verilator_xmls/924a0bc4-42da-4fab-8fd8-e9578c607037.xml
module NValuesAdder(
  input         clock,
  input         reset,
  output        inputs_ready,
  input         inputs_valid,
  input  [31:0] inputs_bits_ops_0_op1,
  input  [31:0] inputs_bits_ops_0_op2,
  input  [31:0] inputs_bits_ops_1_op1,
  input  [31:0] inputs_bits_ops_1_op2,
  output [31:0] outputs
);
  wire  res1_clock;
  wire  res1_reset;
  wire [31:0] res1_input_bits_op1;
  wire [31:0] res1_input_bits_op2;
  wire [31:0] res1_output_bits_res;
  wire  res2_clock;
  wire  res2_reset;
  wire [31:0] res2_input_bits_op1;
  wire [31:0] res2_input_bits_op2;
  wire [31:0] res2_output_bits_res;
  wire  res3_clock;
  wire  res3_reset;
  wire [31:0] res3_input_bits_op1;
  wire [31:0] res3_input_bits_op2;
  wire [31:0] res3_output_bits_res;
  DecoupledAdder res1 (
    .clock(res1_clock),
    .reset(res1_reset),
    .input_bits_op1(res1_input_bits_op1),
    .input_bits_op2(res1_input_bits_op2),
    .output_bits_res(res1_output_bits_res)
  );
  DecoupledAdder res2 (
    .clock(res2_clock),
    .reset(res2_reset),
    .input_bits_op1(res2_input_bits_op1),
    .input_bits_op2(res2_input_bits_op2),
    .output_bits_res(res2_output_bits_res)
  );
  DecoupledAdder res3 (
    .clock(res3_clock),
    .reset(res3_reset),
    .input_bits_op1(res3_input_bits_op1),
    .input_bits_op2(res3_input_bits_op2),
    .output_bits_res(res3_output_bits_res)
  );
  assign inputs_ready = 1'h1;
  assign outputs = res3_output_bits_res;
  assign res1_clock = clock;
  assign res1_reset = reset;
  assign res1_input_bits_op1 = inputs_bits_ops_0_op1;
  assign res1_input_bits_op2 = inputs_bits_ops_0_op2;
  assign res2_clock = clock;
  assign res2_reset = reset;
  assign res2_input_bits_op1 = inputs_bits_ops_1_op1;
  assign res2_input_bits_op2 = inputs_bits_ops_1_op2;
  assign res3_clock = clock;
  assign res3_reset = reset;
  assign res3_input_bits_op1 = res1_output_bits_res;
  assign res3_input_bits_op2 = res2_output_bits_res;
endmodule
module NValuesAdder(
  input         clock,
  input         reset,
  output        inputs_ready,
  input         inputs_valid,
  input  [31:0] inputs_bits_ops_0_op1,
  input  [31:0] inputs_bits_ops_0_op2,
  input  [31:0] inputs_bits_ops_1_op1,
  input  [31:0] inputs_bits_ops_1_op2,
  output [31:0] outputs
);

  wire  res1_clock;
  wire  res1_reset;
  wire [31:0] res1_input_bits_op1;
  wire [31:0] res1_input_bits_op2;
  wire [31:0] res1_output_bits_res;
  wire  res2_clock;
  wire  res2_reset;
  wire [31:0] res2_input_bits_op1;
  wire [31:0] res2_input_bits_op2;
  wire [31:0] res2_output_bits_res;
  wire  res3_clock;
  wire  res3_reset;
  wire [31:0] res3_input_bits_op1;
  wire [31:0] res3_input_bits_op2;
  wire [31:0] res3_output_bits_res;
  DecoupledAdder res1 (
    .clock(res1_clock),
    .reset(res1_reset),
    .input_bits_op1(res1_input_bits_op1),
    .input_bits_op2(res1_input_bits_op2),
    .output_bits_res(res1_output_bits_res)
  );
  DecoupledAdder res2 (
    .clock(res2_clock),
    .reset(res2_reset),
    .input_bits_op1(res2_input_bits_op1),
    .input_bits_op2(res2_input_bits_op2),
    .output_bits_res(res2_output_bits_res)
  );
  DecoupledAdder res3 (
    .clock(res3_clock),
    .reset(res3_reset),
    .input_bits_op1(res3_input_bits_op1),
    .input_bits_op2(res3_input_bits_op2),
    .output_bits_res(res3_output_bits_res)
  );
  assign inputs_ready = 1'h1;
  assign outputs = res3_output_bits_res;
  assign res1_clock = clock;
  assign res1_reset = reset;
  assign res1_input_bits_op1 = inputs_bits_ops_0_op1;
  assign res1_input_bits_op2 = inputs_bits_ops_0_op2;
  assign res2_clock = clock;
  assign res2_reset = reset;
  assign res2_input_bits_op1 = inputs_bits_ops_1_op1;
  assign res2_input_bits_op2 = inputs_bits_ops_1_op2;
  assign res3_clock = clock;
  assign res3_reset = reset;
  assign res3_input_bits_op1 = res1_output_bits_res;
  assign res3_input_bits_op2 = res2_output_bits_res;
endmodule