data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/src/axi_arbiter.sv
1: b'%Warning-MULTITOP: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/src/axi_arbiter.sv:22: Multiple top level modules\n                                                                                                                                  : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                                                  : ... Top module \'axi_arbiter\'\nmodule axi_arbiter #(\n       ^~~~~~~~~~~\n                                                                                                                                  : ... Top module \'AXI_ARBITRATION\'\n  AXI_ARBITRATION.arb arb\n  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/src/axi_arbiter.sv:22: Unsupported: Interfaced port on top level module\n  AXI_ARBITRATION.arb arb\n                      ^~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/src/axi_arbiter.sv:22: Cannot find file containing interface: \'AXI_ARBITRATION\'\n  AXI_ARBITRATION.arb arb\n  ^~~~~~~~~~~~~~~\n%Error: Internal Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/src/axi_arbiter.sv:22: ../V3LinkDot.cpp:2055: Unlinked interface\n  AXI_ARBITRATION.arb arb\n  ^~~~~~~~~~~~~~~\n'
module axi_arbiter_tree #(

  parameter int NUM_REQ = -1,

  parameter int ID_WIDTH = -1
)(
  input  logic [NUM_REQ-1:0]                  in_req_i  ,
  output logic [NUM_REQ-1:0]                  in_ack_o  ,
  input  logic [NUM_REQ-1:0][ID_WIDTH-1:0]    in_id_i   ,
  output logic                                out_req_o ,
  input  logic                                out_ack_i ,
  output logic [ID_WIDTH+$clog2(NUM_REQ)-1:0] out_id_o  ,
  input  logic [$clog2(NUM_REQ)-1:0]          shift_i
);

  `ifndef SYNTHESIS
  initial begin
    assert(NUM_REQ  >= 0);
    assert(ID_WIDTH >= 0);
  end
  `endif



  localparam int NUM_INNER_REQ = NUM_REQ > 0 ? 2**($clog2(NUM_REQ)-1) : 0;
  localparam logic [ID_WIDTH:0] ID_MASK = (1 << ID_WIDTH) - 1;


  logic shift_bit;
  assign shift_bit = shift_i[$high(shift_i)];


  logic [NUM_INNER_REQ-1:0] inner_req, inner_ack;
  logic [NUM_INNER_REQ-1:0][ID_WIDTH:0] inner_id;

  for (genvar i = 0; i < NUM_INNER_REQ; i++) begin : g_head
    localparam iA = i*2;
    localparam iB = i*2+1;
    if (iB < NUM_REQ) begin



      logic sel;
      always_comb begin
        if (in_req_i[iA] && in_req_i[iB])
          sel = shift_bit;
        else if (in_req_i[iA])
          sel = 0;
        else if (in_req_i[iB])
          sel = 1;
        else
          sel = 0;
      end

      assign inner_req[i] = in_req_i[iA] | in_req_i[iB];
      assign in_ack_o[iA] = inner_ack[i] && (sel == 0);
      assign in_ack_o[iB] = inner_ack[i] && (sel == 1);
      assign inner_id[i]  = (sel << ID_WIDTH) | ((sel ? in_id_i[iB] : in_id_i[iA]) & ID_MASK);
    end else if (iA < NUM_REQ) begin
      assign inner_req[i] = in_req_i[iA];
      assign in_ack_o[iA] = inner_ack[i];
      assign inner_id[i]  = in_id_i[iA] & ID_MASK;
    end
  end


  if (NUM_INNER_REQ > 1) begin : g_tail
    axi_arbiter_tree #(
      .NUM_REQ  ( NUM_INNER_REQ ),
      .ID_WIDTH ( ID_WIDTH+1    )
    ) i_tail (
      .in_req_i  ( inner_req                   ),
      .in_ack_o  ( inner_ack                   ),
      .in_id_i   ( inner_id                    ),
      .out_req_o ( out_req_o                   ),
      .out_ack_i ( out_ack_i                   ),
      .out_id_o  ( out_id_o                    ),
      .shift_i   ( shift_i[$high(shift_i)-1:0] )
    );
  end else if (NUM_INNER_REQ == 1) begin : g_tail
    assign out_req_o = inner_req;
    assign inner_ack = out_ack_i;
    assign out_id_o  = inner_id[0];
  end else begin : g_tail
    assign out_req_o   = in_req_i[0];
    assign in_ack_o[0] = out_ack_i;
    assign out_id_o    = in_id_i[0];
  end

endmodule
module axi_arbiter_tree #(

  parameter int NUM_REQ = -1,

  parameter int ID_WIDTH = -1
)(
  input  logic [NUM_REQ-1:0]                  in_req_i  ,
  output logic [NUM_REQ-1:0]                  in_ack_o  ,
  input  logic [NUM_REQ-1:0][ID_WIDTH-1:0]    in_id_i   ,
  output logic                                out_req_o ,
  input  logic                                out_ack_i ,
  output logic [ID_WIDTH+$clog2(NUM_REQ)-1:0] out_id_o  ,
  input  logic [$clog2(NUM_REQ)-1:0]          shift_i
);


  `ifndef SYNTHESIS
  initial begin
    assert(NUM_REQ  >= 0);
    assert(ID_WIDTH >= 0);
  end
  `endif



  localparam int NUM_INNER_REQ = NUM_REQ > 0 ? 2**($clog2(NUM_REQ)-1) : 0;
  localparam logic [ID_WIDTH:0] ID_MASK = (1 << ID_WIDTH) - 1;


  logic shift_bit;
  assign shift_bit = shift_i[$high(shift_i)];


  logic [NUM_INNER_REQ-1:0] inner_req, inner_ack;
  logic [NUM_INNER_REQ-1:0][ID_WIDTH:0] inner_id;

  for (genvar i = 0; i < NUM_INNER_REQ; i++) begin : g_head
    localparam iA = i*2;
    localparam iB = i*2+1;
    if (iB < NUM_REQ) begin



      logic sel;
      always_comb begin
        if (in_req_i[iA] && in_req_i[iB])
          sel = shift_bit;
        else if (in_req_i[iA])
          sel = 0;
        else if (in_req_i[iB])
          sel = 1;
        else
          sel = 0;
      end

      assign inner_req[i] = in_req_i[iA] | in_req_i[iB];
      assign in_ack_o[iA] = inner_ack[i] && (sel == 0);
      assign in_ack_o[iB] = inner_ack[i] && (sel == 1);
      assign inner_id[i]  = (sel << ID_WIDTH) | ((sel ? in_id_i[iB] : in_id_i[iA]) & ID_MASK);
    end else if (iA < NUM_REQ) begin
      assign inner_req[i] = in_req_i[iA];
      assign in_ack_o[iA] = inner_ack[i];
      assign inner_id[i]  = in_id_i[iA] & ID_MASK;
    end
  end


  if (NUM_INNER_REQ > 1) begin : g_tail
    axi_arbiter_tree #(
      .NUM_REQ  ( NUM_INNER_REQ ),
      .ID_WIDTH ( ID_WIDTH+1    )
    ) i_tail (
      .in_req_i  ( inner_req                   ),
      .in_ack_o  ( inner_ack                   ),
      .in_id_i   ( inner_id                    ),
      .out_req_o ( out_req_o                   ),
      .out_ack_i ( out_ack_i                   ),
      .out_id_o  ( out_id_o                    ),
      .shift_i   ( shift_i[$high(shift_i)-1:0] )
    );
  end else if (NUM_INNER_REQ == 1) begin : g_tail
    assign out_req_o = inner_req;
    assign inner_ack = out_ack_i;
    assign out_id_o  = inner_id[0];
  end else begin : g_tail
    assign out_req_o   = in_req_i[0];
    assign in_ack_o[0] = out_ack_i;
    assign out_id_o    = in_id_i[0];
  end

endmodule