data/full_repos/permissive/412284801/registers/register_nbit_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/412284801/registers/register_nbit_tb.v:7: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/412284801/registers/register_nbit_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n        #10 clr = 0;\n        ^\n%Error: data/full_repos/permissive/412284801/registers/register_nbit_tb.v:11: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/412284801/registers/register_nbit_tb.v:13: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/412284801/registers/register_nbit_tb.v:15: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/412284801/registers/register_nbit_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #10 clr = 1;\n        ^\n%Error: data/full_repos/permissive/412284801/registers/register_nbit_tb.v:19: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/412284801/registers/register_nbit_tb.v:21: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/412284801/registers/register_nbit_tb.v:23: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: Exiting due to 6 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module register_nbit_tb;
    reg clk,clr;
    reg [7:0] d;
    wire [7:0 ]q;
    
    register_nbit#(8) r(d,clk,clr,q);
    always #5 clk = ~clk;
    initial begin
        clk =0;
        #10 clr = 0;
        @(posedge clk);
            d <= 0;
        @(posedge clk);
            d <= 1;
        @(posedge clk);
            d <= 0;
      
        #10 clr = 1;
        @(posedge clk);
            d <= 0;
        @(posedge clk);
            d <= 1;
        @(posedge clk);
            d <= 0;
    end
endmodule
module register_nbit_tb;

    reg clk,clr;
    reg [7:0] d;
    wire [7:0 ]q;
    
    register_nbit#(8) r(d,clk,clr,q);
    always #5 clk = ~clk;
    initial begin
        clk =0;
        #10 clr = 0;
        @(posedge clk);
            d <= 0;
        @(posedge clk);
            d <= 1;
        @(posedge clk);
            d <= 0;
      
        #10 clr = 1;
        @(posedge clk);
            d <= 0;
        @(posedge clk);
            d <= 1;
        @(posedge clk);
            d <= 0;
    end
endmodule