data/full_repos/permissive/492462267/id.v
1: b'%Error: data/full_repos/permissive/492462267/id.v:1: Cannot find include file: define.vh\n`include "define.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh.v\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh.sv\n             define.vh\n             define.vh.v\n             define.vh.sv\n             obj_dir/define.vh\n             obj_dir/define.vh.v\n             obj_dir/define.vh.sv\n%Error: data/full_repos/permissive/492462267/id.v:12: Define or directive not defined: \'`InstAddrBus\'\n    input   wire[`InstAddrBus]  pc_i,        \n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:12: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input   wire[`InstAddrBus]  pc_i,        \n                             ^\n%Error: data/full_repos/permissive/492462267/id.v:13: Define or directive not defined: \'`InstBus\'\n    input   wire[`InstBus]      inst_i,      \n                 ^~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:17: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output  reg                 re2_o,       \n    ^~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:18: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output  reg[`RegAddrBus]    raddr1_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:18: Define or directive not defined: \'`RegAddrBus\'\n    output  reg[`RegAddrBus]    raddr1_o,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:19: Define or directive not defined: \'`RegAddrBus\'\n    output  reg[`RegAddrBus]    raddr2_o,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:20: Define or directive not defined: \'`RegDataBus\'\n    input   wire[`RegDataBus]   rdata1_i,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:21: Define or directive not defined: \'`RegDataBus\'\n    input   wire[`RegDataBus]   rdata2_i,     \n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:25: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output  reg[`RegAddrBus]    waddr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:25: Define or directive not defined: \'`RegAddrBus\'\n    output  reg[`RegAddrBus]    waddr_o,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:30: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire[`RegAddrBus]   ex_waddr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/492462267/id.v:30: Define or directive not defined: \'`RegAddrBus\'\n    input   wire[`RegAddrBus]   ex_waddr_i,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:31: Define or directive not defined: \'`RegDataBus\'\n    input   wire[`RegDataBus]   ex_wdata_i,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:35: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire[`RegAddrBus]   mem_waddr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/492462267/id.v:35: Define or directive not defined: \'`RegAddrBus\'\n    input   wire[`RegAddrBus]   mem_waddr_i,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:36: Define or directive not defined: \'`RegDataBus\'\n    input   wire[`RegDataBus]   mem_wdata_i,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:40: Define or directive not defined: \'`AluOpBus\'\n    output  reg[`AluOpBus]      aluop_o,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:41: Define or directive not defined: \'`AluSelBus\'\n    output  reg[`AluSelBus]     alusel_o,\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:42: Define or directive not defined: \'`RegDataBus\'\n    output  reg[`RegDataBus]    data1_o,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:43: Define or directive not defined: \'`RegDataBus\'\n    output  reg[`RegDataBus]    data2_o,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:61: Define or directive not defined: \'`RegDataBus\'\nreg[`RegDataBus]    imme;\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:61: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg[`RegDataBus]    imme;\n               ^\n%Error: data/full_repos/permissive/492462267/id.v:69: syntax error, unexpected always\nalways @(*) begin\n^~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:71: Define or directive not defined: \'`EXE_NOP_OP\'\n        aluop_o   = `EXE_NOP_OP;\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:72: Define or directive not defined: \'`EXE_RES_NOP\'\n        alusel_o  = `EXE_RES_NOP;\n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:73: Define or directive not defined: \'`Disable\'\n        we_o      = `Disable;\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:74: Define or directive not defined: \'`RegAddr_0\'\n        waddr_o   = `RegAddr_0;\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:75: Define or directive not defined: \'`False\'\n                                                    : ... Suggested alternative: \'`else\'\n        instvalid = `False;\n                    ^~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:76: Define or directive not defined: \'`Disable\'\n        re1_o     = `Disable;\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:77: Define or directive not defined: \'`Disable\'\n        re2_o     = `Disable;\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:78: Define or directive not defined: \'`RegAddr_0\'\n        raddr1_o  = `RegAddr_0;\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:79: Define or directive not defined: \'`RegAddr_0\'\n        raddr2_o  = `RegAddr_0;\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:80: Define or directive not defined: \'`ZeroWord\'\n        imme      = `ZeroWord;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:82: Define or directive not defined: \'`EXE_NOP_OP\'\n        aluop_o   = `EXE_NOP_OP;\n                    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:83: Define or directive not defined: \'`EXE_RES_NOP\'\n        alusel_o  = `EXE_RES_NOP;\n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:84: Define or directive not defined: \'`Enable\'\n        we_o      = `Enable;             \n                    ^~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:86: Define or directive not defined: \'`True\'\n        instvalid = `True;\n                    ^~~~~\n%Error: data/full_repos/permissive/492462267/id.v:87: Define or directive not defined: \'`Disable\'\n        re1_o     = `Disable;            \n                    ^~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:88: Define or directive not defined: \'`Disable\'\n        re2_o     = `Disable;            \n                    ^~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:91: Define or directive not defined: \'`ZeroWord\'\n        imme      = `ZeroWord;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:93: Define or directive not defined: \'`EXE_SPECIAL\'\n            `EXE_SPECIAL: begin          \n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:97: Define or directive not defined: \'`EXE_AND\'\n                            `EXE_AND: begin                  \n                            ^~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:98: Define or directive not defined: \'`True\'\n                                instvalid = `True;\n                                            ^~~~~\n%Error: data/full_repos/permissive/492462267/id.v:99: Define or directive not defined: \'`Enable\'\n                                we_o      = `Enable;\n                                            ^~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:100: Define or directive not defined: \'`Enable\'\n                                re1_o     = `Enable;\n                                            ^~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:101: Define or directive not defined: \'`Enable\'\n                                re2_o     = `Enable;\n                                            ^~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:102: Define or directive not defined: \'`EXE_AND_OP\'\n                                aluop_o   = `EXE_AND_OP;\n                                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/id.v:103: Define or directive not defined: \'`EXE_RES_LOGIC\'\n                                alusel_o  = `EXE_RES_LOGIC;\n                                            ^~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module id (
    input   wire                rst,
    input   wire[`InstAddrBus]  pc_i,
    input   wire[`InstBus]      inst_i,


    output  reg                 re1_o,
    output  reg                 re2_o,
    output  reg[`RegAddrBus]    raddr1_o,
    output  reg[`RegAddrBus]    raddr2_o,
    input   wire[`RegDataBus]   rdata1_i,
    input   wire[`RegDataBus]   rdata2_i,     


    output  reg                 we_o,
    output  reg[`RegAddrBus]    waddr_o,



    input   wire                ex_we_i,
    input   wire[`RegAddrBus]   ex_waddr_i,
    input   wire[`RegDataBus]   ex_wdata_i,


    input   wire                mem_we_i,
    input   wire[`RegAddrBus]   mem_waddr_i,
    input   wire[`RegDataBus]   mem_wdata_i,



    output  reg[`AluOpBus]      aluop_o,
    output  reg[`AluSelBus]     alusel_o,
    output  reg[`RegDataBus]    data1_o,
    output  reg[`RegDataBus]    data2_o,


    output  reg                 stallreq
    
);



wire[5:0]   op     = inst_i[31:26];
wire[4:0]   rs    = inst_i[25:21];
wire[4:0]   rt    = inst_i[20:16];
wire[4:0]   rd     = inst_i[15:11];
wire[4:0]   sa     = inst_i[10:6];
wire[5:0]   func   = inst_i[5:0];



reg[`RegDataBus]    imme;


reg instvalid;


always @(*) begin
    if(rst) begin
        aluop_o   = `EXE_NOP_OP;
        alusel_o  = `EXE_RES_NOP;
        we_o      = `Disable;
        waddr_o   = `RegAddr_0;
        instvalid = `False;
        re1_o     = `Disable;
        re2_o     = `Disable;
        raddr1_o  = `RegAddr_0;
        raddr2_o  = `RegAddr_0;
        imme      = `ZeroWord;
    end else begin
        aluop_o   = `EXE_NOP_OP;
        alusel_o  = `EXE_RES_NOP;
        we_o      = `Enable;
        waddr_o   =  rd;
        instvalid = `True;
        re1_o     = `Disable;
        re2_o     = `Disable;
        raddr1_o  = rs;
        raddr2_o  = rt;
        imme      = `ZeroWord;
        case (op)
            `EXE_SPECIAL: begin
                case (sa)
                    5'b00000: begin
                        case (func)
                            `EXE_AND: begin
                                instvalid = `True;
                                we_o      = `Enable;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_AND_OP;
                                alusel_o  = `EXE_RES_LOGIC;
                            end
                            `EXE_OR: begin
                                instvalid = `True;
                                we_o      = `Enable;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_OR_OP;
                                alusel_o  = `EXE_RES_LOGIC;
                            end
                            `EXE_XOR: begin
                                instvalid = `True;
                                we_o      = `Enable;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_XOR_OP;
                                alusel_o  = `EXE_RES_LOGIC;
                            end
                            `EXE_NOR: begin
                                instvalid = `True;
                                we_o      = `Enable;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_NOR_OP;
                                alusel_o  = `EXE_RES_LOGIC;
                            end
                            `EXE_SLLV: begin
                                instvalid = `True;
                                we_o      = `Enable;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_SLL_OP;
                                alusel_o  = `EXE_RES_SHIFT;
                            end
                            `EXE_SRLV: begin
                                instvalid = `True;
                                we_o      = `Enable;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_SRL_OP;
                                alusel_o  = `EXE_RES_SHIFT;
                            end
                            `EXE_SRAV: begin
                                instvalid = `True;
                                we_o      = `Enable;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_SRA_OP;
                                alusel_o  = `EXE_RES_SHIFT;
                            end

                            `EXE_SYNC: begin
                                instvalid = `True;
                                we_o      = `Disable;
                                re1_o     = `Disable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_NOP_OP;
                                alusel_o  = `EXE_RES_NOP;
                            end

                            `EXE_MOVN: begin
                                instvalid = `True;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_MOVN_OP;
                                alusel_o  = `EXE_RES_MOVE;
                                if (data2_o == `ZeroWord) begin
                                    we_o  = `Disable;
                                end else begin
                                    we_o  = `Enable;
                                end
                            end

                            `EXE_MOVZ: begin
                                instvalid = `True;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_MOVZ_OP;
                                alusel_o  = `EXE_RES_MOVE;
                                if (data2_o == `ZeroWord) begin
                                    we_o  = `Enable;
                                end else begin
                                    we_o = `Disable;
                                end
                            end

                            `EXE_MFHI: begin
                                instvalid = `True;
                                we_o      = `Enable;
                                re1_o     = `Disable;
                                re2_o     = `Disable;
                                aluop_o   = `EXE_MFHI_OP;
                                alusel_o  = `EXE_RES_MOVE;
                            end

                            `EXE_MFLO: begin
                                instvalid = `True;
                                we_o      = `Enable;
                                re1_o     = `Disable;
                                re2_o     = `Disable;
                                aluop_o   = `EXE_MFLO_OP;
                                alusel_o  = `EXE_RES_MOVE;
                            end

                            `EXE_MTHI: begin
                                instvalid = `True;
                                we_o      = `Disable;
                                re1_o     = `Enable;
                                re2_o     = `Disable;
                                aluop_o   = `EXE_MTHI_OP;

                            end

                            `EXE_MTLO: begin
                                instvalid = `True;
                                we_o      = `Disable;
                                re1_o     = `Enable;
                                re2_o     = `Disable;
                                aluop_o   = `EXE_MTLO_OP;

                            end

                            `EXE_ADD: begin
                                instvalid = `True;
                                we_o      = `Enable;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_ADD_OP;
                                alusel_o  = `EXE_RES_ARITHMETIC;
                            end

                            `EXE_ADDU: begin
                                instvalid = `True;
                                we_o      = `Enable;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_ADDU_OP;
                                alusel_o  = `EXE_RES_ARITHMETIC;
                            end

                            `EXE_SUB: begin
                                instvalid = `True;
                                we_o      = `Enable;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_SUB_OP;
                                alusel_o  = `EXE_RES_ARITHMETIC;
                            end

                            `EXE_SUBU: begin
                                instvalid = `True;
                                we_o      = `Enable;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_SUBU_OP;
                                alusel_o  = `EXE_RES_ARITHMETIC;
                            end

                            `EXE_SLT: begin
                                instvalid = `True;
                                we_o      = `Enable;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_SLT_OP;
                                alusel_o  = `EXE_RES_ARITHMETIC;
                            end

                            `EXE_SLTU: begin
                                instvalid = `True;
                                we_o      = `Enable;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_SLTU_OP;
                                alusel_o  = `EXE_RES_ARITHMETIC;
                            end

                            `EXE_MULT: begin                
                                instvalid = `True;
                                we_o      = `Disable;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_MULT_OP;

                            end

                            `EXE_MULTU: begin                
                                instvalid = `True;
                                we_o      = `Disable;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_MULTU_OP;

                            end

                            default: begin
                            end
                            endcase
                    end

                    default: begin
                    end
                endcase
            end

            `EXE_SPECIAL_2: begin
                case (func)
                    `EXE_CLZ: begin
                        instvalid = `True;
                        we_o      = `Enable;
                        re1_o     = `Enable;
                        re2_o     = `Disable;
                        aluop_o   = `EXE_CLZ_OP;
                        alusel_o  = `EXE_RES_ARITHMETIC;
                    end
                    `EXE_CLO: begin
                        instvalid = `True;
                        we_o      = `Enable;
                        re1_o     = `Enable;
                        re2_o     = `Disable;
                        aluop_o   = `EXE_CLO_OP;
                        alusel_o  = `EXE_RES_ARITHMETIC;
                    end
                    `EXE_MUL: begin
                        instvalid = `True;
                        we_o      = `Enable;
                        re1_o     = `Enable;
                        re2_o     = `Enable;
                        aluop_o   = `EXE_MUL_OP;
                        alusel_o  = `EXE_RES_MUL;
                    end
                endcase
            end
                    
            `EXE_ORI: begin
                instvalid = `True;
                aluop_o   = `EXE_OR_OP;
                alusel_o  = `EXE_RES_LOGIC;
                re1_o     = `Enable;
                re2_o     = `Disable;
                imme      = {16'h0, inst_i[15:0]};
                we_o      = `Enable;
                waddr_o   = rt;
            end

            `EXE_ANDI: begin
                instvalid = `True;
                aluop_o   = `EXE_AND_OP;
                alusel_o  = `EXE_RES_LOGIC;
                re1_o     = `Enable;
                re2_o     = `Disable;
                raddr1_o  = rs;
                imme      = {16'h0, inst_i[15:0]};
                we_o      = `Enable;
                waddr_o   = rt;
            end

            `EXE_XORI: begin
                instvalid = `True;
                aluop_o   = `EXE_XOR_OP;
                alusel_o  = `EXE_RES_LOGIC;
                re1_o     = `Enable;
                re2_o     = `Disable;
                raddr1_o  = rs;
                imme      = {16'h0, inst_i[15:0]};
                we_o      = `Enable;
                waddr_o   = rt;
            end


            `EXE_LUI: begin
                instvalid = `True;
                aluop_o   = `EXE_OR_OP;      
                alusel_o  = `EXE_RES_LOGIC;  
                re1_o     = `Enable;         
                re2_o     = `Disable;        
                raddr1_o  = rs;             
                imme      = {inst_i[15:0], 16'h0};
                we_o      = `Enable;         
                waddr_o   = rt;             
            end

            `EXE_ADDI: begin
                instvalid   = `True;
                we_o        = `Enable;
                re1_o       = `Enable;
                re2_o       = `Disable;
                aluop_o     = `EXE_ADD_OP;
                alusel_o    = `EXE_RES_ARITHMETIC;
                imme        = { { 16{inst_i[15]} }, inst_i[15:0] };
                waddr_o     = rt;
            end

            `EXE_ADDIU: begin
                instvalid   = `True;
                we_o        = `Enable;
                re1_o       = `Enable;
                re2_o       = `Disable;
                aluop_o     = `EXE_ADDU_OP;
                alusel_o    = `EXE_RES_ARITHMETIC;
                imme        = { { 16{inst_i[15]} }, inst_i[15:0] };
                waddr_o     = rt;
            end

            `EXE_SLTI: begin
                instvalid   = `True;
                we_o        = `Enable;
                re1_o       = `Enable;
                re2_o       = `Disable;
                aluop_o     = `EXE_SLT_OP;
                alusel_o    = `EXE_RES_ARITHMETIC;
                imme        = { { 16{inst_i[15]} }, inst_i[15:0] };
                waddr_o     = rt;
            end

            `EXE_SLTIU: begin
                instvalid   = `True;
                we_o        = `Enable;
                re1_o       = `Enable;
                re2_o       = `Disable;
                aluop_o     = `EXE_SLTU_OP;
                alusel_o    = `EXE_RES_ARITHMETIC;
                imme        = { { 16{inst_i[15]} }, inst_i[15:0] };
                waddr_o     = rt;
            end


            `EXE_PREF: begin
                instvalid = `True;           
                aluop_o   = `EXE_NOP_OP;      
                alusel_o  = `EXE_RES_NOP;
                we_o      = `Disable;  
                re1_o     = `Disable;         
                re2_o     = `Disable;        
                raddr1_o  = rs;                        
            end

            default: begin
            end    
        endcase


        if (inst_i[31:21] == 11'b00000000000) begin
            case(func)
                `EXE_SLL: begin
                    instvalid   = `True;
                    aluop_o     = `EXE_SLL_OP;
                    alusel_o    = `EXE_RES_SHIFT;
                    we_o        = `Enable;
                    re1_o       = `Disable;
                    re2_o       = `Enable;
                    imme[4:0]   = sa;
                end

                `EXE_SRL: begin
                    instvalid   = `True;
                    aluop_o     = `EXE_SRL_OP;
                    alusel_o    = `EXE_RES_SHIFT;
                    we_o        = `Enable;
                    re1_o       = `Disable;
                    re2_o       = `Enable;
                    imme[4:0]   = sa;
                end

                `EXE_SRA: begin
                    instvalid   = `True;
                    aluop_o     = `EXE_SRA_OP;
                    alusel_o    = `EXE_RES_SHIFT;
                    we_o        = `Enable;
                    re1_o       = `Disable;
                    re2_o       = `Enable;
                    imme[4:0]   = sa;
                end

                default begin
                end

            endcase
        end
    end
end



always @(*) begin
    if(rst) begin
        data1_o = `ZeroWord;
    end else if( re1_o && ex_we_i 
                && (raddr1_o == ex_waddr_i)
                ) begin     
        data1_o = ex_wdata_i;
    end else if( re1_o && mem_we_i
                && (raddr1_o == mem_waddr_i)
                ) begin   
        data1_o = mem_wdata_i;
    end else if(re1_o) begin
        data1_o = rdata1_i;    
    end else if(~re1_o) begin
        data1_o = imme;
    end else begin
        data1_o = `ZeroWord;
    end
end


always @(*) begin
    if(rst) begin
        data2_o = `ZeroWord;
    end else if( re2_o && ex_we_i 
                && (raddr2_o == ex_waddr_i)
                ) begin     
        data2_o = ex_wdata_i;
    end else if( re2_o && mem_we_i
                && (raddr2_o == mem_waddr_i)
                ) begin   
        data2_o = mem_wdata_i;
    end else if(re2_o) begin
        data2_o = rdata2_i;    
    end else if(~re2_o) begin
        data2_o = imme;
    end else begin
        data2_o = `ZeroWord;
    end
end

endmodule
module id (
    input   wire                rst,
    input   wire[`InstAddrBus]  pc_i,
    input   wire[`InstBus]      inst_i,


    output  reg                 re1_o,
    output  reg                 re2_o,
    output  reg[`RegAddrBus]    raddr1_o,
    output  reg[`RegAddrBus]    raddr2_o,
    input   wire[`RegDataBus]   rdata1_i,
    input   wire[`RegDataBus]   rdata2_i,     


    output  reg                 we_o,
    output  reg[`RegAddrBus]    waddr_o,



    input   wire                ex_we_i,
    input   wire[`RegAddrBus]   ex_waddr_i,
    input   wire[`RegDataBus]   ex_wdata_i,


    input   wire                mem_we_i,
    input   wire[`RegAddrBus]   mem_waddr_i,
    input   wire[`RegDataBus]   mem_wdata_i,



    output  reg[`AluOpBus]      aluop_o,
    output  reg[`AluSelBus]     alusel_o,
    output  reg[`RegDataBus]    data1_o,
    output  reg[`RegDataBus]    data2_o,


    output  reg                 stallreq
    
);




wire[5:0]   op     = inst_i[31:26];
wire[4:0]   rs    = inst_i[25:21];
wire[4:0]   rt    = inst_i[20:16];
wire[4:0]   rd     = inst_i[15:11];
wire[4:0]   sa     = inst_i[10:6];
wire[5:0]   func   = inst_i[5:0];



reg[`RegDataBus]    imme;


reg instvalid;


always @(*) begin
    if(rst) begin
        aluop_o   = `EXE_NOP_OP;
        alusel_o  = `EXE_RES_NOP;
        we_o      = `Disable;
        waddr_o   = `RegAddr_0;
        instvalid = `False;
        re1_o     = `Disable;
        re2_o     = `Disable;
        raddr1_o  = `RegAddr_0;
        raddr2_o  = `RegAddr_0;
        imme      = `ZeroWord;
    end else begin
        aluop_o   = `EXE_NOP_OP;
        alusel_o  = `EXE_RES_NOP;
        we_o      = `Enable;
        waddr_o   =  rd;
        instvalid = `True;
        re1_o     = `Disable;
        re2_o     = `Disable;
        raddr1_o  = rs;
        raddr2_o  = rt;
        imme      = `ZeroWord;
        case (op)
            `EXE_SPECIAL: begin
                case (sa)
                    5'b00000: begin
                        case (func)
                            `EXE_AND: begin
                                instvalid = `True;
                                we_o      = `Enable;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_AND_OP;
                                alusel_o  = `EXE_RES_LOGIC;
                            end
                            `EXE_OR: begin
                                instvalid = `True;
                                we_o      = `Enable;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_OR_OP;
                                alusel_o  = `EXE_RES_LOGIC;
                            end
                            `EXE_XOR: begin
                                instvalid = `True;
                                we_o      = `Enable;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_XOR_OP;
                                alusel_o  = `EXE_RES_LOGIC;
                            end
                            `EXE_NOR: begin
                                instvalid = `True;
                                we_o      = `Enable;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_NOR_OP;
                                alusel_o  = `EXE_RES_LOGIC;
                            end
                            `EXE_SLLV: begin
                                instvalid = `True;
                                we_o      = `Enable;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_SLL_OP;
                                alusel_o  = `EXE_RES_SHIFT;
                            end
                            `EXE_SRLV: begin
                                instvalid = `True;
                                we_o      = `Enable;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_SRL_OP;
                                alusel_o  = `EXE_RES_SHIFT;
                            end
                            `EXE_SRAV: begin
                                instvalid = `True;
                                we_o      = `Enable;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_SRA_OP;
                                alusel_o  = `EXE_RES_SHIFT;
                            end

                            `EXE_SYNC: begin
                                instvalid = `True;
                                we_o      = `Disable;
                                re1_o     = `Disable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_NOP_OP;
                                alusel_o  = `EXE_RES_NOP;
                            end

                            `EXE_MOVN: begin
                                instvalid = `True;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_MOVN_OP;
                                alusel_o  = `EXE_RES_MOVE;
                                if (data2_o == `ZeroWord) begin
                                    we_o  = `Disable;
                                end else begin
                                    we_o  = `Enable;
                                end
                            end

                            `EXE_MOVZ: begin
                                instvalid = `True;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_MOVZ_OP;
                                alusel_o  = `EXE_RES_MOVE;
                                if (data2_o == `ZeroWord) begin
                                    we_o  = `Enable;
                                end else begin
                                    we_o = `Disable;
                                end
                            end

                            `EXE_MFHI: begin
                                instvalid = `True;
                                we_o      = `Enable;
                                re1_o     = `Disable;
                                re2_o     = `Disable;
                                aluop_o   = `EXE_MFHI_OP;
                                alusel_o  = `EXE_RES_MOVE;
                            end

                            `EXE_MFLO: begin
                                instvalid = `True;
                                we_o      = `Enable;
                                re1_o     = `Disable;
                                re2_o     = `Disable;
                                aluop_o   = `EXE_MFLO_OP;
                                alusel_o  = `EXE_RES_MOVE;
                            end

                            `EXE_MTHI: begin
                                instvalid = `True;
                                we_o      = `Disable;
                                re1_o     = `Enable;
                                re2_o     = `Disable;
                                aluop_o   = `EXE_MTHI_OP;

                            end

                            `EXE_MTLO: begin
                                instvalid = `True;
                                we_o      = `Disable;
                                re1_o     = `Enable;
                                re2_o     = `Disable;
                                aluop_o   = `EXE_MTLO_OP;

                            end

                            `EXE_ADD: begin
                                instvalid = `True;
                                we_o      = `Enable;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_ADD_OP;
                                alusel_o  = `EXE_RES_ARITHMETIC;
                            end

                            `EXE_ADDU: begin
                                instvalid = `True;
                                we_o      = `Enable;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_ADDU_OP;
                                alusel_o  = `EXE_RES_ARITHMETIC;
                            end

                            `EXE_SUB: begin
                                instvalid = `True;
                                we_o      = `Enable;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_SUB_OP;
                                alusel_o  = `EXE_RES_ARITHMETIC;
                            end

                            `EXE_SUBU: begin
                                instvalid = `True;
                                we_o      = `Enable;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_SUBU_OP;
                                alusel_o  = `EXE_RES_ARITHMETIC;
                            end

                            `EXE_SLT: begin
                                instvalid = `True;
                                we_o      = `Enable;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_SLT_OP;
                                alusel_o  = `EXE_RES_ARITHMETIC;
                            end

                            `EXE_SLTU: begin
                                instvalid = `True;
                                we_o      = `Enable;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_SLTU_OP;
                                alusel_o  = `EXE_RES_ARITHMETIC;
                            end

                            `EXE_MULT: begin                
                                instvalid = `True;
                                we_o      = `Disable;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_MULT_OP;

                            end

                            `EXE_MULTU: begin                
                                instvalid = `True;
                                we_o      = `Disable;
                                re1_o     = `Enable;
                                re2_o     = `Enable;
                                aluop_o   = `EXE_MULTU_OP;

                            end

                            default: begin
                            end
                            endcase
                    end

                    default: begin
                    end
                endcase
            end

            `EXE_SPECIAL_2: begin
                case (func)
                    `EXE_CLZ: begin
                        instvalid = `True;
                        we_o      = `Enable;
                        re1_o     = `Enable;
                        re2_o     = `Disable;
                        aluop_o   = `EXE_CLZ_OP;
                        alusel_o  = `EXE_RES_ARITHMETIC;
                    end
                    `EXE_CLO: begin
                        instvalid = `True;
                        we_o      = `Enable;
                        re1_o     = `Enable;
                        re2_o     = `Disable;
                        aluop_o   = `EXE_CLO_OP;
                        alusel_o  = `EXE_RES_ARITHMETIC;
                    end
                    `EXE_MUL: begin
                        instvalid = `True;
                        we_o      = `Enable;
                        re1_o     = `Enable;
                        re2_o     = `Enable;
                        aluop_o   = `EXE_MUL_OP;
                        alusel_o  = `EXE_RES_MUL;
                    end
                endcase
            end
                    
            `EXE_ORI: begin
                instvalid = `True;
                aluop_o   = `EXE_OR_OP;
                alusel_o  = `EXE_RES_LOGIC;
                re1_o     = `Enable;
                re2_o     = `Disable;
                imme      = {16'h0, inst_i[15:0]};
                we_o      = `Enable;
                waddr_o   = rt;
            end

            `EXE_ANDI: begin
                instvalid = `True;
                aluop_o   = `EXE_AND_OP;
                alusel_o  = `EXE_RES_LOGIC;
                re1_o     = `Enable;
                re2_o     = `Disable;
                raddr1_o  = rs;
                imme      = {16'h0, inst_i[15:0]};
                we_o      = `Enable;
                waddr_o   = rt;
            end

            `EXE_XORI: begin
                instvalid = `True;
                aluop_o   = `EXE_XOR_OP;
                alusel_o  = `EXE_RES_LOGIC;
                re1_o     = `Enable;
                re2_o     = `Disable;
                raddr1_o  = rs;
                imme      = {16'h0, inst_i[15:0]};
                we_o      = `Enable;
                waddr_o   = rt;
            end


            `EXE_LUI: begin
                instvalid = `True;
                aluop_o   = `EXE_OR_OP;      
                alusel_o  = `EXE_RES_LOGIC;  
                re1_o     = `Enable;         
                re2_o     = `Disable;        
                raddr1_o  = rs;             
                imme      = {inst_i[15:0], 16'h0};
                we_o      = `Enable;         
                waddr_o   = rt;             
            end

            `EXE_ADDI: begin
                instvalid   = `True;
                we_o        = `Enable;
                re1_o       = `Enable;
                re2_o       = `Disable;
                aluop_o     = `EXE_ADD_OP;
                alusel_o    = `EXE_RES_ARITHMETIC;
                imme        = { { 16{inst_i[15]} }, inst_i[15:0] };
                waddr_o     = rt;
            end

            `EXE_ADDIU: begin
                instvalid   = `True;
                we_o        = `Enable;
                re1_o       = `Enable;
                re2_o       = `Disable;
                aluop_o     = `EXE_ADDU_OP;
                alusel_o    = `EXE_RES_ARITHMETIC;
                imme        = { { 16{inst_i[15]} }, inst_i[15:0] };
                waddr_o     = rt;
            end

            `EXE_SLTI: begin
                instvalid   = `True;
                we_o        = `Enable;
                re1_o       = `Enable;
                re2_o       = `Disable;
                aluop_o     = `EXE_SLT_OP;
                alusel_o    = `EXE_RES_ARITHMETIC;
                imme        = { { 16{inst_i[15]} }, inst_i[15:0] };
                waddr_o     = rt;
            end

            `EXE_SLTIU: begin
                instvalid   = `True;
                we_o        = `Enable;
                re1_o       = `Enable;
                re2_o       = `Disable;
                aluop_o     = `EXE_SLTU_OP;
                alusel_o    = `EXE_RES_ARITHMETIC;
                imme        = { { 16{inst_i[15]} }, inst_i[15:0] };
                waddr_o     = rt;
            end


            `EXE_PREF: begin
                instvalid = `True;           
                aluop_o   = `EXE_NOP_OP;      
                alusel_o  = `EXE_RES_NOP;
                we_o      = `Disable;  
                re1_o     = `Disable;         
                re2_o     = `Disable;        
                raddr1_o  = rs;                        
            end

            default: begin
            end    
        endcase


        if (inst_i[31:21] == 11'b00000000000) begin
            case(func)
                `EXE_SLL: begin
                    instvalid   = `True;
                    aluop_o     = `EXE_SLL_OP;
                    alusel_o    = `EXE_RES_SHIFT;
                    we_o        = `Enable;
                    re1_o       = `Disable;
                    re2_o       = `Enable;
                    imme[4:0]   = sa;
                end

                `EXE_SRL: begin
                    instvalid   = `True;
                    aluop_o     = `EXE_SRL_OP;
                    alusel_o    = `EXE_RES_SHIFT;
                    we_o        = `Enable;
                    re1_o       = `Disable;
                    re2_o       = `Enable;
                    imme[4:0]   = sa;
                end

                `EXE_SRA: begin
                    instvalid   = `True;
                    aluop_o     = `EXE_SRA_OP;
                    alusel_o    = `EXE_RES_SHIFT;
                    we_o        = `Enable;
                    re1_o       = `Disable;
                    re2_o       = `Enable;
                    imme[4:0]   = sa;
                end

                default begin
                end

            endcase
        end
    end
end



always @(*) begin
    if(rst) begin
        data1_o = `ZeroWord;
    end else if( re1_o && ex_we_i 
                && (raddr1_o == ex_waddr_i)
                ) begin     
        data1_o = ex_wdata_i;
    end else if( re1_o && mem_we_i
                && (raddr1_o == mem_waddr_i)
                ) begin   
        data1_o = mem_wdata_i;
    end else if(re1_o) begin
        data1_o = rdata1_i;    
    end else if(~re1_o) begin
        data1_o = imme;
    end else begin
        data1_o = `ZeroWord;
    end
end


always @(*) begin
    if(rst) begin
        data2_o = `ZeroWord;
    end else if( re2_o && ex_we_i 
                && (raddr2_o == ex_waddr_i)
                ) begin     
        data2_o = ex_wdata_i;
    end else if( re2_o && mem_we_i
                && (raddr2_o == mem_waddr_i)
                ) begin   
        data2_o = mem_wdata_i;
    end else if(re2_o) begin
        data2_o = rdata2_i;    
    end else if(~re2_o) begin
        data2_o = imme;
    end else begin
        data2_o = `ZeroWord;
    end
end

endmodule