data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_syncstress.v
data/verilator_xmls/b8ab7ca1-d39c-4c31-b115-14de47f3fab3.xml
module ipsmacge_syncstress
    (
     rst_,
     iclk,
     idat,
     odat
     );


parameter NUM_DW  = 2;



input     rst_;
input     iclk;
input     idat;
output    odat;



reg [NUM_DW-1:0] cnt_nstress;
reg              edat;



always @(posedge iclk or negedge rst_)
    begin
    if (!rst_)              cnt_nstress <= {NUM_DW{1'b0}};
    else if (idat)          cnt_nstress <= {NUM_DW{1'b0}} + 1'b1;
    else if (|cnt_nstress)  cnt_nstress <= cnt_nstress + 1'b1;
    end

always @(posedge iclk or negedge rst_)
    begin
    if (!rst_)              edat <= 1'b0;
    else if (idat)          edat <= 1'b1;
    else if (|cnt_nstress)  edat <= 1'b1;
    else                    edat <= 1'b0;
    end
assign odat = edat;

endmodule
module ipsmacge_syncstress
    (
     rst_,
     iclk,
     idat,
     odat
     );



parameter NUM_DW  = 2;



input     rst_;
input     iclk;
input     idat;
output    odat;



reg [NUM_DW-1:0] cnt_nstress;
reg              edat;



always @(posedge iclk or negedge rst_)
    begin
    if (!rst_)              cnt_nstress <= {NUM_DW{1'b0}};
    else if (idat)          cnt_nstress <= {NUM_DW{1'b0}} + 1'b1;
    else if (|cnt_nstress)  cnt_nstress <= cnt_nstress + 1'b1;
    end

always @(posedge iclk or negedge rst_)
    begin
    if (!rst_)              edat <= 1'b0;
    else if (idat)          edat <= 1'b1;
    else if (|cnt_nstress)  edat <= 1'b1;
    else                    edat <= 1'b0;
    end
assign odat = edat;

endmodule