data/full_repos/permissive/458737381/src/verilog-parser/tests/std-3.11.1-parameters.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/std-3.11.1-parameters.v:13: Duplicate declaration of signal: 'newconst'\nparameter newconst = 4;\n          ^~~~~~~~\n        data/full_repos/permissive/458737381/src/verilog-parser/tests/std-3.11.1-parameters.v:12: ... Location of original declaration\nparameter newconst = 3'h4;\n          ^~~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module test;
parameter msb = 7;
parameter e = 25, f = 9;
parameter r = 5.7;
parameter byte_size = 8;
parameter byte_mask = byte_size -1;
parameter average_delay = (r + f)/2;
parameter signed [3:0] mux_selector = 0;
parameter real r1 = 3.5e17;
parameter p1 = 13'h7e;
parameter [31:0] dec_const = 1'b1;
parameter newconst = 3'h4;
parameter newconst = 4;
endmodule
module test;

parameter msb = 7;
parameter e = 25, f = 9;
parameter r = 5.7;
parameter byte_size = 8;
parameter byte_mask = byte_size -1;
parameter average_delay = (r + f)/2;
parameter signed [3:0] mux_selector = 0;
parameter real r1 = 3.5e17;
parameter p1 = 13'h7e;
parameter [31:0] dec_const = 1'b1;
parameter newconst = 3'h4;
parameter newconst = 4;
endmodule