data/full_repos/permissive/472196771/verilog/rtl/src/clk_divider.v
1: b'%Warning-WIDTH: data/full_repos/permissive/472196771/verilog/rtl/src/clk_divider.v:9: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                    : ... In instance CLKDivider\n  reg [3:0] counter = 1\'b0;\n                      ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module CLKDivider(clk, clkdiv2, clkdiv4, clkdiv8, clkdiv16);
  input clk;
  output clkdiv2, clkdiv4, clkdiv8, clkdiv16;
  
  reg [3:0] counter = 1'b0;
  
  always @(posedge clk)
    counter <= counter + 1;
    
  assign clkdiv2 = counter[0];
  assign clkdiv4 = counter[1];
  assign clkdiv8 = counter[2];
  assign clkdiv16 = counter[3];

endmodule
module CLKDivider(clk, clkdiv2, clkdiv4, clkdiv8, clkdiv16);

  input clk;
  output clkdiv2, clkdiv4, clkdiv8, clkdiv16;
  
  reg [3:0] counter = 1'b0;
  
  always @(posedge clk)
    counter <= counter + 1;
    
  assign clkdiv2 = counter[0];
  assign clkdiv4 = counter[1];
  assign clkdiv8 = counter[2];
  assign clkdiv16 = counter[3];

endmodule