data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v
1: b'%Error: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:96: Cannot find file containing module: \'dist_mem_gen_0\'\ndist_mem_gen_0 dmg0_sine(\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new,data/full_repos/permissive/432862802/dist_mem_gen_0\n             data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new,data/full_repos/permissive/432862802/dist_mem_gen_0.v\n             data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new,data/full_repos/permissive/432862802/dist_mem_gen_0.sv\n             dist_mem_gen_0\n             dist_mem_gen_0.v\n             dist_mem_gen_0.sv\n             obj_dir/dist_mem_gen_0\n             obj_dir/dist_mem_gen_0.v\n             obj_dir/dist_mem_gen_0.sv\n%Error: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:101: Cannot find file containing module: \'dist_mem_gen_0\'\ndist_mem_gen_0 dmg1_sine(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:106: Cannot find file containing module: \'dist_mem_gen_0\'\ndist_mem_gen_0 dmg2_sine(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:111: Cannot find file containing module: \'dist_mem_gen_0\'\ndist_mem_gen_0 dmg3_sine(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:117: Cannot find file containing module: \'dist_mem_gen_5\'\ndist_mem_gen_5 dmg0_sawtooth(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:122: Cannot find file containing module: \'dist_mem_gen_5\'\ndist_mem_gen_5 dmg1_sawtooth(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:127: Cannot find file containing module: \'dist_mem_gen_5\'\ndist_mem_gen_5 dmg2_sawtooth(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:132: Cannot find file containing module: \'dist_mem_gen_5\'\ndist_mem_gen_5 dmg3_sawtooth(\n^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:155: Operator COND expects 32 or 12 bits on the Conditional True, but Conditional True\'s VARREF \'od_level\' generates 10 bits.\n                                                                                                      : ... In instance Single_Note\nassign pwm_level_sine =  ((note_0 == 12) ? 0 : ((lut_out_0_sine > od_level_top) ? od_level : ((lut_out_0_sine < od_level_bot) ? od_level_bot : lut_out_0_sine))) + \n                                                                                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:155: Operator COND expects 32 or 12 bits on the Conditional True, but Conditional True\'s VARREF \'od_level_bot\' generates 10 bits.\n                                                                                                      : ... In instance Single_Note\nassign pwm_level_sine =  ((note_0 == 12) ? 0 : ((lut_out_0_sine > od_level_top) ? od_level : ((lut_out_0_sine < od_level_bot) ? od_level_bot : lut_out_0_sine))) + \n                                                                                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:155: Operator COND expects 32 or 12 bits on the Conditional False, but Conditional False\'s VARREF \'lut_out_0_sine\' generates 10 bits.\n                                                                                                      : ... In instance Single_Note\nassign pwm_level_sine =  ((note_0 == 12) ? 0 : ((lut_out_0_sine > od_level_top) ? od_level : ((lut_out_0_sine < od_level_bot) ? od_level_bot : lut_out_0_sine))) + \n                                                                                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:156: Operator COND expects 32 or 12 bits on the Conditional True, but Conditional True\'s VARREF \'od_level\' generates 10 bits.\n                                                                                                      : ... In instance Single_Note\n                    ((note_1 == 12) ? 0 : ((lut_out_1_sine > od_level_top) ? od_level : ((lut_out_1_sine < od_level_bot) ? od_level_bot : lut_out_1_sine))) + \n                                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:156: Operator COND expects 32 or 12 bits on the Conditional True, but Conditional True\'s VARREF \'od_level_bot\' generates 10 bits.\n                                                                                                      : ... In instance Single_Note\n                    ((note_1 == 12) ? 0 : ((lut_out_1_sine > od_level_top) ? od_level : ((lut_out_1_sine < od_level_bot) ? od_level_bot : lut_out_1_sine))) + \n                                                                                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:156: Operator COND expects 32 or 12 bits on the Conditional False, but Conditional False\'s VARREF \'lut_out_1_sine\' generates 10 bits.\n                                                                                                      : ... In instance Single_Note\n                    ((note_1 == 12) ? 0 : ((lut_out_1_sine > od_level_top) ? od_level : ((lut_out_1_sine < od_level_bot) ? od_level_bot : lut_out_1_sine))) + \n                                                                                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:157: Operator COND expects 32 or 12 bits on the Conditional True, but Conditional True\'s VARREF \'od_level\' generates 10 bits.\n                                                                                                      : ... In instance Single_Note\n                    ((note_2 == 12) ? 0 : ((lut_out_2_sine > od_level_top) ? od_level : ((lut_out_2_sine < od_level_bot) ? od_level_bot : lut_out_2_sine))) + \n                                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:157: Operator COND expects 32 or 12 bits on the Conditional True, but Conditional True\'s VARREF \'od_level_bot\' generates 10 bits.\n                                                                                                      : ... In instance Single_Note\n                    ((note_2 == 12) ? 0 : ((lut_out_2_sine > od_level_top) ? od_level : ((lut_out_2_sine < od_level_bot) ? od_level_bot : lut_out_2_sine))) + \n                                                                                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:157: Operator COND expects 32 or 12 bits on the Conditional False, but Conditional False\'s VARREF \'lut_out_2_sine\' generates 10 bits.\n                                                                                                      : ... In instance Single_Note\n                    ((note_2 == 12) ? 0 : ((lut_out_2_sine > od_level_top) ? od_level : ((lut_out_2_sine < od_level_bot) ? od_level_bot : lut_out_2_sine))) + \n                                                                                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:158: Operator COND expects 32 or 12 bits on the Conditional True, but Conditional True\'s VARREF \'od_level\' generates 10 bits.\n                                                                                                      : ... In instance Single_Note\n                    ((note_3 == 12) ? 0 : ((lut_out_3_sine > od_level_top) ? od_level : ((lut_out_3_sine < od_level_bot) ? od_level_bot : lut_out_3_sine)));\n                                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:158: Operator COND expects 32 or 12 bits on the Conditional True, but Conditional True\'s VARREF \'od_level_bot\' generates 10 bits.\n                                                                                                      : ... In instance Single_Note\n                    ((note_3 == 12) ? 0 : ((lut_out_3_sine > od_level_top) ? od_level : ((lut_out_3_sine < od_level_bot) ? od_level_bot : lut_out_3_sine)));\n                                                                                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:158: Operator COND expects 32 or 12 bits on the Conditional False, but Conditional False\'s VARREF \'lut_out_3_sine\' generates 10 bits.\n                                                                                                      : ... In instance Single_Note\n                    ((note_3 == 12) ? 0 : ((lut_out_3_sine > od_level_top) ? od_level : ((lut_out_3_sine < od_level_bot) ? od_level_bot : lut_out_3_sine)));\n                                                                                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:160: Operator COND expects 32 or 12 bits on the Conditional True, but Conditional True\'s VARREF \'od_level\' generates 10 bits.\n                                                                                                      : ... In instance Single_Note\nassign pwm_level_sawtooth =  ((note_0 == 12) ? 0 : ((lut_out_0_sawtooth > od_level_top) ? od_level : ((lut_out_0_sawtooth < od_level_bot) ? od_level_bot : lut_out_0_sawtooth))) + \n                                                                                        ^\n%Warning-WIDTH: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:160: Operator COND expects 32 or 12 bits on the Conditional True, but Conditional True\'s VARREF \'od_level_bot\' generates 10 bits.\n                                                                                                      : ... In instance Single_Note\nassign pwm_level_sawtooth =  ((note_0 == 12) ? 0 : ((lut_out_0_sawtooth > od_level_top) ? od_level : ((lut_out_0_sawtooth < od_level_bot) ? od_level_bot : lut_out_0_sawtooth))) + \n                                                                                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:160: Operator COND expects 32 or 12 bits on the Conditional False, but Conditional False\'s VARREF \'lut_out_0_sawtooth\' generates 10 bits.\n                                                                                                      : ... In instance Single_Note\nassign pwm_level_sawtooth =  ((note_0 == 12) ? 0 : ((lut_out_0_sawtooth > od_level_top) ? od_level : ((lut_out_0_sawtooth < od_level_bot) ? od_level_bot : lut_out_0_sawtooth))) + \n                                                                                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:161: Operator COND expects 32 or 12 bits on the Conditional True, but Conditional True\'s VARREF \'od_level\' generates 10 bits.\n                                                                                                      : ... In instance Single_Note\n                    ((note_1 == 12) ? 0 : ((lut_out_1_sawtooth > od_level_top) ? od_level : ((lut_out_1_sawtooth < od_level_bot) ? od_level_bot : lut_out_1_sawtooth))) + \n                                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:161: Operator COND expects 32 or 12 bits on the Conditional True, but Conditional True\'s VARREF \'od_level_bot\' generates 10 bits.\n                                                                                                      : ... In instance Single_Note\n                    ((note_1 == 12) ? 0 : ((lut_out_1_sawtooth > od_level_top) ? od_level : ((lut_out_1_sawtooth < od_level_bot) ? od_level_bot : lut_out_1_sawtooth))) + \n                                                                                                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:161: Operator COND expects 32 or 12 bits on the Conditional False, but Conditional False\'s VARREF \'lut_out_1_sawtooth\' generates 10 bits.\n                                                                                                      : ... In instance Single_Note\n                    ((note_1 == 12) ? 0 : ((lut_out_1_sawtooth > od_level_top) ? od_level : ((lut_out_1_sawtooth < od_level_bot) ? od_level_bot : lut_out_1_sawtooth))) + \n                                                                                                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:162: Operator COND expects 32 or 12 bits on the Conditional True, but Conditional True\'s VARREF \'od_level\' generates 10 bits.\n                                                                                                      : ... In instance Single_Note\n                    ((note_2 == 12) ? 0 : ((lut_out_2_sawtooth > od_level_top) ? od_level : ((lut_out_2_sawtooth < od_level_bot) ? od_level_bot : lut_out_2_sawtooth))) + \n                                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:162: Operator COND expects 32 or 12 bits on the Conditional True, but Conditional True\'s VARREF \'od_level_bot\' generates 10 bits.\n                                                                                                      : ... In instance Single_Note\n                    ((note_2 == 12) ? 0 : ((lut_out_2_sawtooth > od_level_top) ? od_level : ((lut_out_2_sawtooth < od_level_bot) ? od_level_bot : lut_out_2_sawtooth))) + \n                                                                                                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:162: Operator COND expects 32 or 12 bits on the Conditional False, but Conditional False\'s VARREF \'lut_out_2_sawtooth\' generates 10 bits.\n                                                                                                      : ... In instance Single_Note\n                    ((note_2 == 12) ? 0 : ((lut_out_2_sawtooth > od_level_top) ? od_level : ((lut_out_2_sawtooth < od_level_bot) ? od_level_bot : lut_out_2_sawtooth))) + \n                                                                                                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:163: Operator COND expects 32 or 12 bits on the Conditional True, but Conditional True\'s VARREF \'od_level\' generates 10 bits.\n                                                                                                      : ... In instance Single_Note\n                    ((note_3 == 12) ? 0 : ((lut_out_3_sawtooth > od_level_top) ? od_level : ((lut_out_3_sawtooth < od_level_bot) ? od_level_bot : lut_out_3_sawtooth)));\n                                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:163: Operator COND expects 32 or 12 bits on the Conditional True, but Conditional True\'s VARREF \'od_level_bot\' generates 10 bits.\n                                                                                                      : ... In instance Single_Note\n                    ((note_3 == 12) ? 0 : ((lut_out_3_sawtooth > od_level_top) ? od_level : ((lut_out_3_sawtooth < od_level_bot) ? od_level_bot : lut_out_3_sawtooth)));\n                                                                                                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:163: Operator COND expects 32 or 12 bits on the Conditional False, but Conditional False\'s VARREF \'lut_out_3_sawtooth\' generates 10 bits.\n                                                                                                      : ... In instance Single_Note\n                    ((note_3 == 12) ? 0 : ((lut_out_3_sawtooth > od_level_top) ? od_level : ((lut_out_3_sawtooth < od_level_bot) ? od_level_bot : lut_out_3_sawtooth)));\n                                                                                                                                 ^\n%Error: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:170: Cannot find file containing module: \'PWMDriver\'\nPWMDriver driver_inst(\n^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:381: Operator EQ expects 18 bits on the RHS, but RHS\'s VARREF \'compare_0\' generates 11 bits.\n                                                                                                      : ... In instance Single_Note\n    else if(sine_count_0 == compare_0)\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:396: Operator EQ expects 18 bits on the RHS, but RHS\'s VARREF \'compare_1\' generates 11 bits.\n                                                                                                      : ... In instance Single_Note\n    else if(sine_count_1 == compare_1)\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:411: Operator EQ expects 18 bits on the RHS, but RHS\'s VARREF \'compare_2\' generates 11 bits.\n                                                                                                      : ... In instance Single_Note\n    else if(sine_count_2 == compare_2)\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/432862802/DigitalPiano.srcs/sources_1/new/Single_Note.v:426: Operator EQ expects 18 bits on the RHS, but RHS\'s VARREF \'compare_3\' generates 11 bits.\n                                                                                                      : ... In instance Single_Note\n    else if(sine_count_3 == compare_3)\n                         ^~\n%Error: Exiting due to 9 error(s), 28 warning(s)\n'
module Single_Note(
    input clk_100, 

    input [1:0] state,
    input rst_n,


    input [9:0] od_level,
    input [9:0] od_level_bottom,


    input tone,
    

    input [3:0] note_0,
    input [3:0] note_1,
    input [3:0] note_2,
    input [3:0] note_3,
    input [1:0] octave_0,
    input [1:0] octave_1,
    input [1:0] octave_2,
    input [1:0] octave_3,
    output [11:0] PWM_LEVEL_OUT,
    output AUD_PWM,
    output AUD_SD
    );


reg [10:0] sine_freq_0 = 0;
reg [10:0] sine_freq_1 = 0;
reg [10:0] sine_freq_2 = 0;
reg [10:0] sine_freq_3 = 0;

reg [17:0] sine_count_0 = 0;
reg [17:0] sine_count_1 = 0;
reg [17:0] sine_count_2 = 0;
reg [17:0] sine_count_3 = 0;


reg [9:0] lut_addr_0;
reg [9:0] lut_addr_1;
reg [9:0] lut_addr_2;
reg [9:0] lut_addr_3;

wire [9:0] lut_out_0_sine;
wire [9:0] lut_out_1_sine;
wire [9:0] lut_out_2_sine;
wire [9:0] lut_out_3_sine;
wire [9:0] lut_out_0_sawtooth;
wire [9:0] lut_out_1_sawtooth;
wire [9:0] lut_out_2_sawtooth;
wire [9:0] lut_out_3_sawtooth;


wire pwm_int;

parameter C = 746;
parameter CS = 706;
parameter D = 664;
parameter DS = 628;
parameter E = 592;
parameter F = 560;
parameter FS = 528;
parameter G = 498;
parameter GS = 470;
parameter A = 444;
parameter AS = 418;
parameter B = 394;


assign AUD_SD = 1'b1;


dist_mem_gen_0 dmg0_sine(
    .a(lut_addr_0), 
    .spo(lut_out_0_sine)
    );

dist_mem_gen_0 dmg1_sine(
    .a(lut_addr_1), 
    .spo(lut_out_1_sine)
    );

dist_mem_gen_0 dmg2_sine(
    .a(lut_addr_2), 
    .spo(lut_out_2_sine)
    );

dist_mem_gen_0 dmg3_sine(
    .a(lut_addr_3), 
    .spo(lut_out_3_sine)
    );


dist_mem_gen_5 dmg0_sawtooth(
    .a(lut_addr_0), 
    .spo(lut_out_0_sawtooth)
    );

dist_mem_gen_5 dmg1_sawtooth(
    .a(lut_addr_1), 
    .spo(lut_out_1_sawtooth)
    );

dist_mem_gen_5 dmg2_sawtooth(
    .a(lut_addr_2), 
    .spo(lut_out_2_sawtooth)
    );

dist_mem_gen_5 dmg3_sawtooth(
    .a(lut_addr_3), 
    .spo(lut_out_3_sawtooth)
    );

wire [11:0] pwm_level_sine;
wire [11:0] pwm_level_sawtooth;
wire [11:0] pwm_level;






reg [9:0] od_level_top;
reg [9:0] od_level_bot;

always @ (posedge clk_100)
begin
    od_level_top <= od_level;
    od_level_bot <= od_level_bottom;
end

assign pwm_level_sine =  ((note_0 == 12) ? 0 : ((lut_out_0_sine > od_level_top) ? od_level : ((lut_out_0_sine < od_level_bot) ? od_level_bot : lut_out_0_sine))) + 
                    ((note_1 == 12) ? 0 : ((lut_out_1_sine > od_level_top) ? od_level : ((lut_out_1_sine < od_level_bot) ? od_level_bot : lut_out_1_sine))) + 
                    ((note_2 == 12) ? 0 : ((lut_out_2_sine > od_level_top) ? od_level : ((lut_out_2_sine < od_level_bot) ? od_level_bot : lut_out_2_sine))) + 
                    ((note_3 == 12) ? 0 : ((lut_out_3_sine > od_level_top) ? od_level : ((lut_out_3_sine < od_level_bot) ? od_level_bot : lut_out_3_sine)));

assign pwm_level_sawtooth =  ((note_0 == 12) ? 0 : ((lut_out_0_sawtooth > od_level_top) ? od_level : ((lut_out_0_sawtooth < od_level_bot) ? od_level_bot : lut_out_0_sawtooth))) + 
                    ((note_1 == 12) ? 0 : ((lut_out_1_sawtooth > od_level_top) ? od_level : ((lut_out_1_sawtooth < od_level_bot) ? od_level_bot : lut_out_1_sawtooth))) + 
                    ((note_2 == 12) ? 0 : ((lut_out_2_sawtooth > od_level_top) ? od_level : ((lut_out_2_sawtooth < od_level_bot) ? od_level_bot : lut_out_2_sawtooth))) + 
                    ((note_3 == 12) ? 0 : ((lut_out_3_sawtooth > od_level_top) ? od_level : ((lut_out_3_sawtooth < od_level_bot) ? od_level_bot : lut_out_3_sawtooth)));

assign pwm_level = (tone == 0) ? pwm_level_sine : pwm_level_sawtooth;

assign PWM_LEVEL_OUT = pwm_level;


PWMDriver driver_inst(
    .clk_100(clk_100),
    .pwm_level(pwm_level),
    .pwm_out(pwm_int)
    );

assign AUD_PWM = (pwm_int == 1'b0) ? 1'b0 : 
                    1'b1;


always @ (note_0 or octave_0)
begin
    case (note_0)
        4'd0 : begin
            sine_freq_0 <= C;
        end
        4'd1 : begin
            sine_freq_0 <= CS;
        end
        4'd2 : begin
            sine_freq_0 <= D;
        end
        4'd3 : begin
            sine_freq_0 <= DS;
        end
        4'd4 : begin
            sine_freq_0 <= E;
        end
        4'd5 : begin
            sine_freq_0 <= F;
        end
        4'd6 : begin
            sine_freq_0 <= FS;
        end
        4'd7 : begin
            sine_freq_0 <= G;
        end
        4'd8 : begin
            sine_freq_0 <= GS;
        end
        4'd9 : begin
            sine_freq_0 <= A;
        end
        4'd10 : begin
            sine_freq_0 <= AS;
        end
        4'd11 : begin
            sine_freq_0 <= B;
        end

        default : begin
            sine_freq_0 <= 0;
        end
    endcase
end

always @ (note_1 or octave_1)
begin
    case (note_1)
        4'd0 : begin
            sine_freq_1 <= C;
        end
        4'd1 : begin
            sine_freq_1 <= CS;
        end
        4'd2 : begin
            sine_freq_1 <= D;
        end
        4'd3 : begin
            sine_freq_1 <= DS;
        end
        4'd4 : begin
            sine_freq_1 <= E;
        end
        4'd5 : begin
            sine_freq_1 <= F;
        end
        4'd6 : begin
            sine_freq_1 <= FS;
        end
        4'd7 : begin
            sine_freq_1 <= G;
        end
        4'd8 : begin
            sine_freq_1 <= GS;
        end
        4'd9 : begin
            sine_freq_1 <= A;
        end
        4'd10 : begin
            sine_freq_1 <= AS;
        end
        4'd11 : begin
            sine_freq_1 <= B;
        end

        default : begin
            sine_freq_1 <= 0;
        end
    endcase
end

always @ (note_2 or octave_2)
begin
    case (note_2)
        4'd0 : begin
            sine_freq_2 <= C;
        end
        4'd1 : begin
            sine_freq_2 <= CS;
        end
        4'd2 : begin
            sine_freq_2 <= D;
        end
        4'd3 : begin
            sine_freq_2 <= DS;
        end
        4'd4 : begin
            sine_freq_2 <= E;
        end
        4'd5 : begin
            sine_freq_2 <= F;
        end
        4'd6 : begin
            sine_freq_2 <= FS;
        end
        4'd7 : begin
            sine_freq_2 <= G;
        end
        4'd8 : begin
            sine_freq_2 <= GS;
        end
        4'd9 : begin
            sine_freq_2 <= A;
        end
        4'd10 : begin
            sine_freq_2 <= AS;
        end
        4'd11 : begin
            sine_freq_2 <= B;
        end

        default : begin
            sine_freq_2 <= 0;
        end
    endcase
end

always @ (note_3 or octave_3)
begin
    case (note_3)
        4'd0 : begin
            sine_freq_3 <= C;
        end
        4'd1 : begin
            sine_freq_3 <= CS;
        end
        4'd2 : begin
            sine_freq_3 <= D;
        end
        4'd3 : begin
            sine_freq_3 <= DS;
        end
        4'd4 : begin
            sine_freq_3 <= E;
        end
        4'd5 : begin
            sine_freq_3 <= F;
        end
        4'd6 : begin
            sine_freq_3 <= FS;
        end
        4'd7 : begin
            sine_freq_3 <= G;
        end
        4'd8 : begin
            sine_freq_3 <= GS;
        end
        4'd9 : begin
            sine_freq_3 <= A;
        end
        4'd10 : begin
            sine_freq_3 <= AS;
        end
        4'd11 : begin
            sine_freq_3 <= B;
        end

        default : begin
            sine_freq_3 <= 0;
        end
    endcase
end

wire [10:0] compare_0;
wire [10:0] compare_1;
wire [10:0] compare_2;
wire [10:0] compare_3;

assign compare_0 = (sine_freq_0>>octave_0);
assign compare_1 = (sine_freq_1>>octave_1);
assign compare_2 = (sine_freq_2>>octave_2);
assign compare_3 = (sine_freq_3>>octave_3);



always @ (posedge clk_100 or negedge rst_n)
begin
    if(!rst_n) begin
        lut_addr_0 <= 0;
    end
    else if(sine_count_0 == compare_0)
    begin
        lut_addr_0 <= lut_addr_0 + 1;
        sine_count_0 <= 18'b0;   
    end
    else begin
        sine_count_0 <= sine_count_0 + 1'b1;
    end
end

always @ (posedge clk_100 or negedge rst_n)
begin
    if(!rst_n) begin
        lut_addr_1 <= 0;
    end
    else if(sine_count_1 == compare_1)
    begin
        lut_addr_1 <= lut_addr_1 + 1;
        sine_count_1 <= 18'b0;   
    end
    else begin
        sine_count_1 <= sine_count_1 + 1'b1;
    end
end

always @ (posedge clk_100 or negedge rst_n)
begin
    if(!rst_n) begin
        lut_addr_2 <= 0;
    end
    else if(sine_count_2 == compare_2)
    begin
        lut_addr_2 <= lut_addr_2 + 1;
        sine_count_2 <= 18'b0;   
    end
    else begin
        sine_count_2 <= sine_count_2 + 1'b1;
    end
end

always @ (posedge clk_100 or negedge rst_n)
begin
    if(!rst_n) begin
        lut_addr_3 <= 0;
    end
    else if(sine_count_3 == compare_3)
    begin
        lut_addr_3 <= lut_addr_3 + 1;
        sine_count_3 <= 18'b0;   
    end
    else begin
        sine_count_3 <= sine_count_3 + 1'b1;
    end
end

endmodule
module Single_Note(
    input clk_100, 

    input [1:0] state,
    input rst_n,


    input [9:0] od_level,
    input [9:0] od_level_bottom,


    input tone,
    

    input [3:0] note_0,
    input [3:0] note_1,
    input [3:0] note_2,
    input [3:0] note_3,
    input [1:0] octave_0,
    input [1:0] octave_1,
    input [1:0] octave_2,
    input [1:0] octave_3,
    output [11:0] PWM_LEVEL_OUT,
    output AUD_PWM,
    output AUD_SD
    );



reg [10:0] sine_freq_0 = 0;
reg [10:0] sine_freq_1 = 0;
reg [10:0] sine_freq_2 = 0;
reg [10:0] sine_freq_3 = 0;

reg [17:0] sine_count_0 = 0;
reg [17:0] sine_count_1 = 0;
reg [17:0] sine_count_2 = 0;
reg [17:0] sine_count_3 = 0;


reg [9:0] lut_addr_0;
reg [9:0] lut_addr_1;
reg [9:0] lut_addr_2;
reg [9:0] lut_addr_3;

wire [9:0] lut_out_0_sine;
wire [9:0] lut_out_1_sine;
wire [9:0] lut_out_2_sine;
wire [9:0] lut_out_3_sine;
wire [9:0] lut_out_0_sawtooth;
wire [9:0] lut_out_1_sawtooth;
wire [9:0] lut_out_2_sawtooth;
wire [9:0] lut_out_3_sawtooth;


wire pwm_int;

parameter C = 746;
parameter CS = 706;
parameter D = 664;
parameter DS = 628;
parameter E = 592;
parameter F = 560;
parameter FS = 528;
parameter G = 498;
parameter GS = 470;
parameter A = 444;
parameter AS = 418;
parameter B = 394;


assign AUD_SD = 1'b1;


dist_mem_gen_0 dmg0_sine(
    .a(lut_addr_0), 
    .spo(lut_out_0_sine)
    );

dist_mem_gen_0 dmg1_sine(
    .a(lut_addr_1), 
    .spo(lut_out_1_sine)
    );

dist_mem_gen_0 dmg2_sine(
    .a(lut_addr_2), 
    .spo(lut_out_2_sine)
    );

dist_mem_gen_0 dmg3_sine(
    .a(lut_addr_3), 
    .spo(lut_out_3_sine)
    );


dist_mem_gen_5 dmg0_sawtooth(
    .a(lut_addr_0), 
    .spo(lut_out_0_sawtooth)
    );

dist_mem_gen_5 dmg1_sawtooth(
    .a(lut_addr_1), 
    .spo(lut_out_1_sawtooth)
    );

dist_mem_gen_5 dmg2_sawtooth(
    .a(lut_addr_2), 
    .spo(lut_out_2_sawtooth)
    );

dist_mem_gen_5 dmg3_sawtooth(
    .a(lut_addr_3), 
    .spo(lut_out_3_sawtooth)
    );

wire [11:0] pwm_level_sine;
wire [11:0] pwm_level_sawtooth;
wire [11:0] pwm_level;






reg [9:0] od_level_top;
reg [9:0] od_level_bot;

always @ (posedge clk_100)
begin
    od_level_top <= od_level;
    od_level_bot <= od_level_bottom;
end

assign pwm_level_sine =  ((note_0 == 12) ? 0 : ((lut_out_0_sine > od_level_top) ? od_level : ((lut_out_0_sine < od_level_bot) ? od_level_bot : lut_out_0_sine))) + 
                    ((note_1 == 12) ? 0 : ((lut_out_1_sine > od_level_top) ? od_level : ((lut_out_1_sine < od_level_bot) ? od_level_bot : lut_out_1_sine))) + 
                    ((note_2 == 12) ? 0 : ((lut_out_2_sine > od_level_top) ? od_level : ((lut_out_2_sine < od_level_bot) ? od_level_bot : lut_out_2_sine))) + 
                    ((note_3 == 12) ? 0 : ((lut_out_3_sine > od_level_top) ? od_level : ((lut_out_3_sine < od_level_bot) ? od_level_bot : lut_out_3_sine)));

assign pwm_level_sawtooth =  ((note_0 == 12) ? 0 : ((lut_out_0_sawtooth > od_level_top) ? od_level : ((lut_out_0_sawtooth < od_level_bot) ? od_level_bot : lut_out_0_sawtooth))) + 
                    ((note_1 == 12) ? 0 : ((lut_out_1_sawtooth > od_level_top) ? od_level : ((lut_out_1_sawtooth < od_level_bot) ? od_level_bot : lut_out_1_sawtooth))) + 
                    ((note_2 == 12) ? 0 : ((lut_out_2_sawtooth > od_level_top) ? od_level : ((lut_out_2_sawtooth < od_level_bot) ? od_level_bot : lut_out_2_sawtooth))) + 
                    ((note_3 == 12) ? 0 : ((lut_out_3_sawtooth > od_level_top) ? od_level : ((lut_out_3_sawtooth < od_level_bot) ? od_level_bot : lut_out_3_sawtooth)));

assign pwm_level = (tone == 0) ? pwm_level_sine : pwm_level_sawtooth;

assign PWM_LEVEL_OUT = pwm_level;


PWMDriver driver_inst(
    .clk_100(clk_100),
    .pwm_level(pwm_level),
    .pwm_out(pwm_int)
    );

assign AUD_PWM = (pwm_int == 1'b0) ? 1'b0 : 
                    1'b1;


always @ (note_0 or octave_0)
begin
    case (note_0)
        4'd0 : begin
            sine_freq_0 <= C;
        end
        4'd1 : begin
            sine_freq_0 <= CS;
        end
        4'd2 : begin
            sine_freq_0 <= D;
        end
        4'd3 : begin
            sine_freq_0 <= DS;
        end
        4'd4 : begin
            sine_freq_0 <= E;
        end
        4'd5 : begin
            sine_freq_0 <= F;
        end
        4'd6 : begin
            sine_freq_0 <= FS;
        end
        4'd7 : begin
            sine_freq_0 <= G;
        end
        4'd8 : begin
            sine_freq_0 <= GS;
        end
        4'd9 : begin
            sine_freq_0 <= A;
        end
        4'd10 : begin
            sine_freq_0 <= AS;
        end
        4'd11 : begin
            sine_freq_0 <= B;
        end

        default : begin
            sine_freq_0 <= 0;
        end
    endcase
end

always @ (note_1 or octave_1)
begin
    case (note_1)
        4'd0 : begin
            sine_freq_1 <= C;
        end
        4'd1 : begin
            sine_freq_1 <= CS;
        end
        4'd2 : begin
            sine_freq_1 <= D;
        end
        4'd3 : begin
            sine_freq_1 <= DS;
        end
        4'd4 : begin
            sine_freq_1 <= E;
        end
        4'd5 : begin
            sine_freq_1 <= F;
        end
        4'd6 : begin
            sine_freq_1 <= FS;
        end
        4'd7 : begin
            sine_freq_1 <= G;
        end
        4'd8 : begin
            sine_freq_1 <= GS;
        end
        4'd9 : begin
            sine_freq_1 <= A;
        end
        4'd10 : begin
            sine_freq_1 <= AS;
        end
        4'd11 : begin
            sine_freq_1 <= B;
        end

        default : begin
            sine_freq_1 <= 0;
        end
    endcase
end

always @ (note_2 or octave_2)
begin
    case (note_2)
        4'd0 : begin
            sine_freq_2 <= C;
        end
        4'd1 : begin
            sine_freq_2 <= CS;
        end
        4'd2 : begin
            sine_freq_2 <= D;
        end
        4'd3 : begin
            sine_freq_2 <= DS;
        end
        4'd4 : begin
            sine_freq_2 <= E;
        end
        4'd5 : begin
            sine_freq_2 <= F;
        end
        4'd6 : begin
            sine_freq_2 <= FS;
        end
        4'd7 : begin
            sine_freq_2 <= G;
        end
        4'd8 : begin
            sine_freq_2 <= GS;
        end
        4'd9 : begin
            sine_freq_2 <= A;
        end
        4'd10 : begin
            sine_freq_2 <= AS;
        end
        4'd11 : begin
            sine_freq_2 <= B;
        end

        default : begin
            sine_freq_2 <= 0;
        end
    endcase
end

always @ (note_3 or octave_3)
begin
    case (note_3)
        4'd0 : begin
            sine_freq_3 <= C;
        end
        4'd1 : begin
            sine_freq_3 <= CS;
        end
        4'd2 : begin
            sine_freq_3 <= D;
        end
        4'd3 : begin
            sine_freq_3 <= DS;
        end
        4'd4 : begin
            sine_freq_3 <= E;
        end
        4'd5 : begin
            sine_freq_3 <= F;
        end
        4'd6 : begin
            sine_freq_3 <= FS;
        end
        4'd7 : begin
            sine_freq_3 <= G;
        end
        4'd8 : begin
            sine_freq_3 <= GS;
        end
        4'd9 : begin
            sine_freq_3 <= A;
        end
        4'd10 : begin
            sine_freq_3 <= AS;
        end
        4'd11 : begin
            sine_freq_3 <= B;
        end

        default : begin
            sine_freq_3 <= 0;
        end
    endcase
end

wire [10:0] compare_0;
wire [10:0] compare_1;
wire [10:0] compare_2;
wire [10:0] compare_3;

assign compare_0 = (sine_freq_0>>octave_0);
assign compare_1 = (sine_freq_1>>octave_1);
assign compare_2 = (sine_freq_2>>octave_2);
assign compare_3 = (sine_freq_3>>octave_3);



always @ (posedge clk_100 or negedge rst_n)
begin
    if(!rst_n) begin
        lut_addr_0 <= 0;
    end
    else if(sine_count_0 == compare_0)
    begin
        lut_addr_0 <= lut_addr_0 + 1;
        sine_count_0 <= 18'b0;   
    end
    else begin
        sine_count_0 <= sine_count_0 + 1'b1;
    end
end

always @ (posedge clk_100 or negedge rst_n)
begin
    if(!rst_n) begin
        lut_addr_1 <= 0;
    end
    else if(sine_count_1 == compare_1)
    begin
        lut_addr_1 <= lut_addr_1 + 1;
        sine_count_1 <= 18'b0;   
    end
    else begin
        sine_count_1 <= sine_count_1 + 1'b1;
    end
end

always @ (posedge clk_100 or negedge rst_n)
begin
    if(!rst_n) begin
        lut_addr_2 <= 0;
    end
    else if(sine_count_2 == compare_2)
    begin
        lut_addr_2 <= lut_addr_2 + 1;
        sine_count_2 <= 18'b0;   
    end
    else begin
        sine_count_2 <= sine_count_2 + 1'b1;
    end
end

always @ (posedge clk_100 or negedge rst_n)
begin
    if(!rst_n) begin
        lut_addr_3 <= 0;
    end
    else if(sine_count_3 == compare_3)
    begin
        lut_addr_3 <= lut_addr_3 + 1;
        sine_count_3 <= 18'b0;   
    end
    else begin
        sine_count_3 <= sine_count_3 + 1'b1;
    end
end

endmodule