data/full_repos/permissive/458737381/src/verilog-parser/tests/ccx_arbctl.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ccx_arbctl.v:31: Cannot find include file: sys.h\n`include "sys.h" // system level definition file which contains the  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ccx_arbctl.v:34: Cannot find include file: iop.h\n`include "iop.h" \n         ^~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module ccx_arbctl(

   scan_out, arbctl_atom, reset_d1, direction, wrptr_l, rdptr, 
   fifo_sel15_12, fifo_sel11_8, fifo_sel7_4, fifo_sel3_0, 
   fifo_bypass, fifo_bypass_l, fifo_valid, qfull, input_req_sel, 
   input_req_sel_d1, fifo_req_sel, current_req_sel, stall_a, 
   ccx_dest_data_rdy_x, ccx_dest_atom_x, arb_dp_q0_hold_a, 
   arb_dp_qsel0_a, arb_dp_qsel1_a, arb_dp_shift_x, 

   src7_arb_atom_q, src6_arb_atom_q, src5_arb_atom_q, 
   src4_arb_atom_q, src3_arb_atom_q, src2_arb_atom_q, 
   src1_arb_atom_q, src0_arb_atom_q, src7_arb_req_q, src6_arb_req_q, 
   src5_arb_req_q, src4_arb_req_q, src3_arb_req_q, src2_arb_req_q, 
   src1_arb_req_q, src0_arb_req_q, stall1_q, stall2_q, 
   ccx_dest_data_rdy_a, ccx_dest_atom_a, grant_a, req_pkt_empty, 
   inreg_req_vld_d1, reset_l, rclk, adbginit_l, se
   );
   






   output             reset_d1;
   output 	     direction;
 
  

   output [15:0]     wrptr_l;
   output [15:0]     rdptr;
   output 	     fifo_sel15_12,fifo_sel11_8, fifo_sel7_4, fifo_sel3_0;
   output 	     fifo_bypass, fifo_bypass_l;
   output 	     fifo_valid;


   output [7:0]      qfull;
   output 	     input_req_sel, input_req_sel_d1;
   output 	     fifo_req_sel, current_req_sel;
   output 	     stall_a;
   

   output 	     ccx_dest_data_rdy_x;
   output 	     ccx_dest_atom_x;


   output [7:0]      arb_dp_q0_hold_a;
   output [7:0]      arb_dp_qsel0_a;
   output [7:0]      arb_dp_qsel1_a;
   output [7:0]      arb_dp_shift_x;




   output [7:0]		arbctl_atom;
   output		scan_out;

    



   input        src7_arb_atom_q;
   input        src6_arb_atom_q;  
   input        src5_arb_atom_q;  
   input        src4_arb_atom_q;  
   input        src3_arb_atom_q;  
   input        src2_arb_atom_q;  
   input        src1_arb_atom_q;  
   input        src0_arb_atom_q;  
                                  
                                  
   input        src7_arb_req_q;
   input        src6_arb_req_q;   
   input        src5_arb_req_q;   
   input        src4_arb_req_q;   
   input        src3_arb_req_q;   
   input        src2_arb_req_q;   
   input        src1_arb_req_q;   
   input        src0_arb_req_q;   
                                

   input 	     stall1_q;
   input 	     stall2_q;


   input 	     ccx_dest_data_rdy_a;
   input 	     ccx_dest_atom_a;
   input [7:0] 	     grant_a;
   input 	     req_pkt_empty;
   input 	     inreg_req_vld_d1;
   

   input 	     reset_l;

   input 	     rclk;

   input             adbginit_l;
   input             se;
   



   wire 	     reset;
   wire 	     dbginit;
   


   wire 	   fifo_rd_vld_d1;
   wire 	   fifo_wr_vld_d1;



   wire 	   fifo_empty_d1 ;
   wire 	   fifo_empty_d1_l;
   wire 	   fifo_empty_d2 ;
   wire 	   fifo_bypass_d1,fifo_bypass, fifo_bypass_l;
   wire 	   fifo_valid ;
   wire [4:0] 	   rdptr_mux,rdptr_d1, rdptr_inc,rdptr_inc_d1;
   wire [4:0] 	   wrptr,wrptr_d1, wrptr_inc;
   wire 	   wr_en, wr_en_d1 ;
   wire 	   rd_en, rd_en_d1 ;
   wire [15:0] 	   wrptr_dcd,wrptr_l;
   wire [15:0] 	   rdptr;
   wire 	   current_req_sel_d1;
   wire 	   fifo_req_sel_d1;
   wire 	   direction_in;
   wire		   stall1_a, stall2_a;
   wire            wrap_wren;
   
   wire            rdptr_dcd_3,
                   rdptr_dcd_7,
                   rdptr_dcd_11,
                   rdptr_dcd_15;



wire [7:0]		atom_a;
wire [7:0]		ctl_qsel0_a;
wire [7:0]		ctl_qsel1_a_l;
wire [7:0]		ctl_shift_a;


wire  ccx_reset_l_d1,ccx_reset2_l_d1;
wire  dbginit_d1;



   assign dbginit_d1 = ~ccx_reset2_l_d1;
   


   dffrl_async  ff_rstl(
                .din(reset_l),
                .q(ccx_reset_l_d1),
                .clk(rclk), 
                .se(se),
                .rst_l(adbginit_l));

   assign       reset_d1 = ~ccx_reset_l_d1;









   
   dffrl_async  ff_rstl2(
                .din(reset_l),
                .q(ccx_reset2_l_d1),
                .clk(rclk), 
                .se(se),
                .rst_l(adbginit_l));




   assign direction_in = ~direction | dbginit_d1;

   dff_s #(1) dff_ccx_com_dir(
            .din           (direction_in),
	    .q             (direction),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (1'b0),
	    .so            ());




   
   
   assign current_req_sel = ~req_pkt_empty & ~reset_d1;
   assign fifo_req_sel    =  req_pkt_empty & (fifo_valid & ~input_req_sel_d1) & ~reset_d1;
   assign input_req_sel   =  req_pkt_empty & ~(fifo_valid & ~input_req_sel_d1) | reset_d1;
   

      dff_s #(1) dff_ccx_com_dr(
            .din           (ccx_dest_data_rdy_a),
	    .q             (ccx_dest_data_rdy_x),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (1'b0),
	    .so            ());

      dff_s #(1) dff_ccx_atom_dr(         
            .din           (ccx_dest_atom_a),
	    .q             (ccx_dest_atom_x),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (1'b0),
	    .so            ());




   dff_s  dff_ccx_arb_stall1(
	.din           (stall1_q),
	.q             (stall1_a),
	.clk           (rclk),
	.se            (1'd0),
	.si            (1'd0),
	.so            ());

   dff_s  dff_ccx_arb_stall2(
	.din           (stall2_q),
	.q             (stall2_a),
	.clk           (rclk),
	.se            (1'd0),
	.si            (1'd0),
	.so            ());

assign	stall_a  =  stall1_a | stall2_a;

   dff_s  dff_ccx_arb_inpsel(
	.din           (input_req_sel),
	.q             (input_req_sel_d1),
	.clk           (rclk),
	.se            (1'd0),
	.si            (1'd0),
	.so            ());
   



   










 

   dff_s #(5) dff_ccx_com_fifo_wrptrd1(
            .din           (wrptr[4:0]),
	    .q             (wrptr_d1[4:0]),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (5'd0),
	    .so            ());



   dff_s #(5) dff_ccx_com_fifo_rdptrd1(
            .din           (rdptr_mux[4:0]),
	    .q             (rdptr_d1[4:0]),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (5'd0),
	    .so            ());

   dff_s #(1) dff_ccx_com_fifo_wrend1(
            .din           (wr_en),
	    .q             (wr_en_d1),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (1'b0),
	    .so            ());

   dff_s #(1) dff_ccx_com_fifo_rdend1(
            .din           (rd_en),
	    .q             (rd_en_d1),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (1'b0),
	    .so            ());
   
   dff_s #(1) dff_ccx_com_fifo_emptyd1(
            .din           (fifo_empty_d1),
	    .q             (fifo_empty_d2),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (1'b0),
	    .so            ());
   

   dff_s #(1) dff_ccx_com_fifo_bypassd1(
            .din           (fifo_bypass),
	    .q             (fifo_bypass_d1),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (1'b0),
	    .so            ());

   
   dff_s #(1) dff_ccx_com_fifo_fifoseld1(
            .din           (fifo_req_sel),
	    .q             (fifo_req_sel_d1),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (1'b0),
	    .so            ());

      dff_s #(1) dff_ccx_com_fifo_currseld1(
            .din           (current_req_sel),
	    .q             (current_req_sel_d1),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (1'b0),
	    .so            ());

      dff_s #(5) dff_ccx_rdptr_incd1(
            .din           (rdptr_inc[4:0]),
	    .q             (rdptr_inc_d1[4:0]),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (5'd0),
	    .so            ());





   assign fifo_rd_vld_d1 =  rd_en_d1 & ~fifo_bypass_d1 & fifo_req_sel_d1;

   assign fifo_wr_vld_d1 =  wr_en_d1 & ~(fifo_bypass_d1 & fifo_req_sel_d1);





























   assign fifo_empty_d1 = &(wrptr[4:0] ~^ rdptr_mux[4:0]);
   assign fifo_empty_d1_l = ~fifo_empty_d1 ;



   assign fifo_bypass   = inreg_req_vld_d1 & fifo_empty_d1 ;
   assign fifo_bypass_l = ~fifo_bypass;



   assign fifo_valid    = inreg_req_vld_d1 | fifo_empty_d1_l;






   assign rdptr_inc[0] = ~rdptr_mux[0];
   assign rdptr_inc[1] =  rdptr_mux[1] ^ rdptr_mux[0];
   assign rdptr_inc[2] = (~&(rdptr_mux[1:0]) ~^ rdptr_mux[2]);
   assign rdptr_inc[3] = (~&(rdptr_mux[2:0]) ~^ rdptr_mux[3]);
   assign rdptr_inc[4] = (~&(rdptr_mux[3:0]) ~^ rdptr_mux[4]);


   assign wrptr_inc[0] = ~wrptr_d1[0];
   assign wrptr_inc[1] =  wrptr_d1[1] ^ wrptr_d1[0];
   assign wrptr_inc[2] = (~&(wrptr_d1[1:0]) ~^ wrptr_d1[2]);
   assign wrptr_inc[3] = (~&(wrptr_d1[2:0]) ~^ wrptr_d1[3]);
   assign wrptr_inc[4] = (~&(wrptr_d1[3:0]) ~^ wrptr_d1[4]);

 



   assign wrptr[4:0] = (fifo_empty_d2 & ~fifo_wr_vld_d1| reset_d1) ? 5'h0 : (fifo_wr_vld_d1 ? wrptr_inc[4:0] : wrptr_d1[4:0]);


   assign wrptr_dcd[0]  =  (~wrptr[3] & ~wrptr[2] & ~wrptr[1] & ~wrptr[0]);
   assign wrptr_dcd[1]  =  (~wrptr[3] & ~wrptr[2] & ~wrptr[1] &  wrptr[0]);
   assign wrptr_dcd[2]  =  (~wrptr[3] & ~wrptr[2] &  wrptr[1] & ~wrptr[0]);
   assign wrptr_dcd[3]  =  (~wrptr[3] & ~wrptr[2] &  wrptr[1] &  wrptr[0]);
   assign wrptr_dcd[4]  =  (~wrptr[3] &  wrptr[2] & ~wrptr[1] & ~wrptr[0]);
   assign wrptr_dcd[5]  =  (~wrptr[3] &  wrptr[2] & ~wrptr[1] &  wrptr[0]);
   assign wrptr_dcd[6]  =  (~wrptr[3] &  wrptr[2] &  wrptr[1] & ~wrptr[0]);
   assign wrptr_dcd[7]  =  (~wrptr[3] &  wrptr[2] &  wrptr[1] &  wrptr[0]);
   assign wrptr_dcd[8]  =  ( wrptr[3] & ~wrptr[2] & ~wrptr[1] & ~wrptr[0]);
   assign wrptr_dcd[9]  =  ( wrptr[3] & ~wrptr[2] & ~wrptr[1] &  wrptr[0]);
   assign wrptr_dcd[10] =  ( wrptr[3] & ~wrptr[2] &  wrptr[1] & ~wrptr[0]);
   assign wrptr_dcd[11] =  ( wrptr[3] & ~wrptr[2] &  wrptr[1] &  wrptr[0]);
   assign wrptr_dcd[12] =  ( wrptr[3] &  wrptr[2] & ~wrptr[1] & ~wrptr[0]);
   assign wrptr_dcd[13] =  ( wrptr[3] &  wrptr[2] & ~wrptr[1] &  wrptr[0]);
   assign wrptr_dcd[14] =  ( wrptr[3] &  wrptr[2] &  wrptr[1] & ~wrptr[0]);
   assign wrptr_dcd[15] =  ( wrptr[3] &  wrptr[2] &  wrptr[1] &  wrptr[0]);

   assign wrptr_l[15:0] = ~(wrptr_dcd[15:0]);
   

   assign rdptr_mux[4:0]=(fifo_empty_d2 & ~fifo_wr_vld_d1 | reset_d1) ? 5'h0 : (fifo_rd_vld_d1 ? rdptr_inc_d1[4:0] : rdptr_d1[4:0]);    



   assign rdptr[0]  =  (~rdptr_mux[3] & ~rdptr_mux[2] & ~rdptr_mux[1] & ~rdptr_mux[0]);
   assign rdptr[1]  =  (~rdptr_mux[3] & ~rdptr_mux[2] & ~rdptr_mux[1] &  rdptr_mux[0]);
   assign rdptr[2]  =  (~rdptr_mux[3] & ~rdptr_mux[2] &  rdptr_mux[1] & ~rdptr_mux[0]);
   assign rdptr[3]  =  ~|rdptr[2:0];
   assign rdptr_dcd_3  =  (~rdptr_mux[3] & ~rdptr_mux[2] &  rdptr_mux[1] &  rdptr_mux[0]);

   assign rdptr[4]  =  (~rdptr_mux[3] &  rdptr_mux[2] & ~rdptr_mux[1] & ~rdptr_mux[0]);
   assign rdptr[5]  =  (~rdptr_mux[3] &  rdptr_mux[2] & ~rdptr_mux[1] &  rdptr_mux[0]);
   assign rdptr[6]  =  (~rdptr_mux[3] &  rdptr_mux[2] &  rdptr_mux[1] & ~rdptr_mux[0]);
   assign rdptr[7]  =  ~|rdptr[6:4];
   assign rdptr_dcd_7  =  (~rdptr_mux[3] &  rdptr_mux[2] &  rdptr_mux[1] &  rdptr_mux[0]);

   assign rdptr[8]  =  ( rdptr_mux[3] & ~rdptr_mux[2] & ~rdptr_mux[1] & ~rdptr_mux[0]);
   assign rdptr[9]  =  ( rdptr_mux[3] & ~rdptr_mux[2] & ~rdptr_mux[1] &  rdptr_mux[0]);
   assign rdptr[10] =  ( rdptr_mux[3] & ~rdptr_mux[2] &  rdptr_mux[1] & ~rdptr_mux[0]);
   assign rdptr[11] =  ~|rdptr[10:8];
   assign rdptr_dcd_11 =  ( rdptr_mux[3] & ~rdptr_mux[2] &  rdptr_mux[1] &  rdptr_mux[0]);

   assign rdptr[12] =  ( rdptr_mux[3] &  rdptr_mux[2] & ~rdptr_mux[1] & ~rdptr_mux[0]);
   assign rdptr[13] =  ( rdptr_mux[3] &  rdptr_mux[2] & ~rdptr_mux[1] &  rdptr_mux[0]);
   assign rdptr[14] =  ( rdptr_mux[3] &  rdptr_mux[2] &  rdptr_mux[1] & ~rdptr_mux[0]);
   assign rdptr[15] =  ~|rdptr[14:12];
   assign rdptr_dcd_15 =  ( rdptr_mux[3] &  rdptr_mux[2] &  rdptr_mux[1] &  rdptr_mux[0]);


   assign fifo_sel15_12 = |({rdptr_dcd_15,rdptr[14:12]});
   assign fifo_sel11_8  = |({rdptr_dcd_11,rdptr[10:8]});
   assign fifo_sel7_4   = |({rdptr_dcd_7, rdptr[6:4]});
   assign fifo_sel3_0   = |({rdptr_dcd_3, rdptr[2:0]});




   assign wrap_wren  = ~(&(wrptr[3:0] ~^ rdptr_mux[3:0]) & (wrptr_inc[4] ^ rdptr_inc[4])) | fifo_empty_d1;
   
   assign wr_en = (inreg_req_vld_d1 & (fifo_req_sel_d1 | current_req_sel_d1)) & wrap_wren & ~reset_d1;


   assign rd_en = fifo_empty_d1_l & ~reset_d1 ;






   ccx_arb_srcq q0(

		   .qfull		(qfull[0]),
		   .qsel0		(arb_dp_qsel0_a[0]),
		   .qsel1		(arb_dp_qsel1_a[0]),
		   .shift_x		(arb_dp_shift_x[0]),
		   .ctl_qsel0_a		(ctl_qsel0_a[0]),
		   .ctl_qsel1_a_l	(ctl_qsel1_a_l[0]),
		   .ctl_shift_a		(ctl_shift_a[0]),
		   .q0_hold_a		(arb_dp_q0_hold_a[0]),
		   .atom_a		(atom_a[0]),

		   .req_q		(src0_arb_req_q),
		   .atom_q		(src0_arb_atom_q),
		   .grant_a		(grant_a[0]),
		   .rclk		(rclk),
		   .reset_d1		(reset_d1));
   ccx_arb_srcq q1(

		   .qfull		(qfull[1]),
		   .qsel0		(arb_dp_qsel0_a[1]),
		   .qsel1		(arb_dp_qsel1_a[1]),
		   .shift_x		(arb_dp_shift_x[1]),
		   .ctl_qsel0_a		(ctl_qsel0_a[1]),
		   .ctl_qsel1_a_l	(ctl_qsel1_a_l[1]),
		   .ctl_shift_a		(ctl_shift_a[1]),
		   .q0_hold_a		(arb_dp_q0_hold_a[1]),
		   .atom_a		(atom_a[1]),

		   .req_q		(src1_arb_req_q),
		   .atom_q		(src1_arb_atom_q),
		   .grant_a		(grant_a[1]),
		   .rclk		(rclk),
		   .reset_d1		(reset_d1));
   ccx_arb_srcq q2(

		   .qfull		(qfull[2]),
		   .qsel0		(arb_dp_qsel0_a[2]),
		   .qsel1		(arb_dp_qsel1_a[2]),
		   .shift_x		(arb_dp_shift_x[2]),
		   .ctl_qsel0_a		(ctl_qsel0_a[2]),
		   .ctl_qsel1_a_l	(ctl_qsel1_a_l[2]),
		   .ctl_shift_a		(ctl_shift_a[2]),
		   .q0_hold_a		(arb_dp_q0_hold_a[2]),
		   .atom_a		(atom_a[2]),

		   .req_q		(src2_arb_req_q),
		   .atom_q		(src2_arb_atom_q),
		   .grant_a		(grant_a[2]),
		   .rclk		(rclk),
		   .reset_d1		(reset_d1));
   ccx_arb_srcq q3(

		   .qfull		(qfull[3]),
		   .qsel0		(arb_dp_qsel0_a[3]),
		   .qsel1		(arb_dp_qsel1_a[3]),
		   .shift_x		(arb_dp_shift_x[3]),
		   .ctl_qsel0_a		(ctl_qsel0_a[3]),
		   .ctl_qsel1_a_l	(ctl_qsel1_a_l[3]),
		   .ctl_shift_a		(ctl_shift_a[3]),
		   .q0_hold_a		(arb_dp_q0_hold_a[3]),
		   .atom_a		(atom_a[3]),

		   .req_q		(src3_arb_req_q),
		   .atom_q		(src3_arb_atom_q),
		   .grant_a		(grant_a[3]),
		   .rclk		(rclk),
		   .reset_d1		(reset_d1));
   ccx_arb_srcq q4(

		   .qfull		(qfull[4]),
		   .qsel0		(arb_dp_qsel0_a[4]),
		   .qsel1		(arb_dp_qsel1_a[4]),
		   .shift_x		(arb_dp_shift_x[4]),
		   .ctl_qsel0_a		(ctl_qsel0_a[4]),
		   .ctl_qsel1_a_l	(ctl_qsel1_a_l[4]),
		   .ctl_shift_a		(ctl_shift_a[4]),
		   .q0_hold_a		(arb_dp_q0_hold_a[4]),
		   .atom_a		(atom_a[4]),

		   .req_q		(src4_arb_req_q),
		   .atom_q		(src4_arb_atom_q),
		   .grant_a		(grant_a[4]),
		   .rclk		(rclk),
		   .reset_d1		(reset_d1));
   ccx_arb_srcq q5(

		   .qfull		(qfull[5]),
		   .qsel0		(arb_dp_qsel0_a[5]),
		   .qsel1		(arb_dp_qsel1_a[5]),
		   .shift_x		(arb_dp_shift_x[5]),
		   .ctl_qsel0_a		(ctl_qsel0_a[5]),
		   .ctl_qsel1_a_l	(ctl_qsel1_a_l[5]),
		   .ctl_shift_a		(ctl_shift_a[5]),
		   .q0_hold_a		(arb_dp_q0_hold_a[5]),
		   .atom_a		(atom_a[5]),

		   .req_q		(src5_arb_req_q),
		   .atom_q		(src5_arb_atom_q),
		   .grant_a		(grant_a[5]),
		   .rclk		(rclk),
		   .reset_d1		(reset_d1));
   ccx_arb_srcq q6(

		   .qfull		(qfull[6]),
		   .qsel0		(arb_dp_qsel0_a[6]),
		   .qsel1		(arb_dp_qsel1_a[6]),
		   .shift_x		(arb_dp_shift_x[6]),
		   .ctl_qsel0_a		(ctl_qsel0_a[6]),
		   .ctl_qsel1_a_l	(ctl_qsel1_a_l[6]),
		   .ctl_shift_a		(ctl_shift_a[6]),
		   .q0_hold_a		(arb_dp_q0_hold_a[6]),
		   .atom_a		(atom_a[6]),

		   .req_q		(src6_arb_req_q),
		   .atom_q		(src6_arb_atom_q),
		   .grant_a		(grant_a[6]),
		   .rclk		(rclk),
		   .reset_d1		(reset_d1));
   ccx_arb_srcq q7(

		   .qfull		(qfull[7]),
		   .qsel0		(arb_dp_qsel0_a[7]),
		   .qsel1		(arb_dp_qsel1_a[7]),
		   .shift_x		(arb_dp_shift_x[7]),
		   .ctl_qsel0_a		(ctl_qsel0_a[7]),
		   .ctl_qsel1_a_l	(ctl_qsel1_a_l[7]),
		   .ctl_shift_a		(ctl_shift_a[7]),
		   .q0_hold_a		(arb_dp_q0_hold_a[7]),
		   .atom_a		(atom_a[7]),

		   .req_q		(src7_arb_req_q),
		   .atom_q		(src7_arb_atom_q),
		   .grant_a		(grant_a[7]),
		   .rclk		(rclk),
		   .reset_d1		(reset_d1));



   ccx_arb_atomq atomq0(

			.q0_dataout	(arbctl_atom[0]),
`ifdef FPGA_SYN
			.scan_out	(),
`else 
			.scan_out	(scan_out),
`endif

			.ctl_qsel1_a_l	(ctl_qsel1_a_l[0]),
			.ctl_qsel0_a	(ctl_qsel0_a[0]),
			.ctl_shift_a	(ctl_shift_a[0]),
			.atom_a		(atom_a[0]),
			.rclk		(rclk),
			.reset_d1	(reset_d1));
   ccx_arb_atomq atomq1(

			.q0_dataout	(arbctl_atom[1]),
`ifdef FPGA_SYN
			.scan_out	(),
`else 
			.scan_out	(scan_out),
`endif

			.ctl_qsel1_a_l	(ctl_qsel1_a_l[1]),
			.ctl_qsel0_a	(ctl_qsel0_a[1]),
			.ctl_shift_a	(ctl_shift_a[1]),
			.atom_a		(atom_a[1]),
			.rclk		(rclk),
			.reset_d1	(reset_d1));
   ccx_arb_atomq atomq2(

			.q0_dataout	(arbctl_atom[2]),
`ifdef FPGA_SYN
			.scan_out	(),
`else 
			.scan_out	(scan_out),
`endif

			.ctl_qsel1_a_l	(ctl_qsel1_a_l[2]),
			.ctl_qsel0_a	(ctl_qsel0_a[2]),
			.ctl_shift_a	(ctl_shift_a[2]),
			.atom_a		(atom_a[2]),
			.rclk		(rclk),
			.reset_d1	(reset_d1));
   ccx_arb_atomq atomq3(

			.q0_dataout	(arbctl_atom[3]),
`ifdef FPGA_SYN
			.scan_out	(),
`else 
			.scan_out	(scan_out),
`endif

			.ctl_qsel1_a_l	(ctl_qsel1_a_l[3]),
			.ctl_qsel0_a	(ctl_qsel0_a[3]),
			.ctl_shift_a	(ctl_shift_a[3]),
			.atom_a		(atom_a[3]),
			.rclk		(rclk),
			.reset_d1	(reset_d1));
   ccx_arb_atomq atomq4(

			.q0_dataout	(arbctl_atom[4]),
`ifdef FPGA_SYN
			.scan_out	(),
`else 
			.scan_out	(scan_out),
`endif

			.ctl_qsel1_a_l	(ctl_qsel1_a_l[4]),
			.ctl_qsel0_a	(ctl_qsel0_a[4]),
			.ctl_shift_a	(ctl_shift_a[4]),
			.atom_a		(atom_a[4]),
			.rclk		(rclk),
			.reset_d1	(reset_d1));
   ccx_arb_atomq atomq5(

			.q0_dataout	(arbctl_atom[5]),
`ifdef FPGA_SYN
			.scan_out	(),
`else 
			.scan_out	(scan_out),
`endif

			.ctl_qsel1_a_l	(ctl_qsel1_a_l[5]),
			.ctl_qsel0_a	(ctl_qsel0_a[5]),
			.ctl_shift_a	(ctl_shift_a[5]),
			.atom_a		(atom_a[5]),
			.rclk		(rclk),
			.reset_d1	(reset_d1));
   ccx_arb_atomq atomq6(

			.q0_dataout	(arbctl_atom[6]),
`ifdef FPGA_SYN
			.scan_out	(),
`else 
			.scan_out	(scan_out),
`endif

			.ctl_qsel1_a_l	(ctl_qsel1_a_l[6]),
			.ctl_qsel0_a	(ctl_qsel0_a[6]),
			.ctl_shift_a	(ctl_shift_a[6]),
			.atom_a		(atom_a[6]),
			.rclk		(rclk),
			.reset_d1	(reset_d1));
   ccx_arb_atomq atomq7(

			.q0_dataout	(arbctl_atom[7]),
`ifdef FPGA_SYN
			.scan_out	(),
`else 
			.scan_out	(scan_out),
`endif

			.ctl_qsel1_a_l	(ctl_qsel1_a_l[7]),
			.ctl_qsel0_a	(ctl_qsel0_a[7]),
			.ctl_shift_a	(ctl_shift_a[7]),
			.atom_a		(atom_a[7]),
			.rclk		(rclk),
			.reset_d1	(reset_d1));

endmodule
module ccx_arbctl(

   scan_out, arbctl_atom, reset_d1, direction, wrptr_l, rdptr, 
   fifo_sel15_12, fifo_sel11_8, fifo_sel7_4, fifo_sel3_0, 
   fifo_bypass, fifo_bypass_l, fifo_valid, qfull, input_req_sel, 
   input_req_sel_d1, fifo_req_sel, current_req_sel, stall_a, 
   ccx_dest_data_rdy_x, ccx_dest_atom_x, arb_dp_q0_hold_a, 
   arb_dp_qsel0_a, arb_dp_qsel1_a, arb_dp_shift_x, 

   src7_arb_atom_q, src6_arb_atom_q, src5_arb_atom_q, 
   src4_arb_atom_q, src3_arb_atom_q, src2_arb_atom_q, 
   src1_arb_atom_q, src0_arb_atom_q, src7_arb_req_q, src6_arb_req_q, 
   src5_arb_req_q, src4_arb_req_q, src3_arb_req_q, src2_arb_req_q, 
   src1_arb_req_q, src0_arb_req_q, stall1_q, stall2_q, 
   ccx_dest_data_rdy_a, ccx_dest_atom_a, grant_a, req_pkt_empty, 
   inreg_req_vld_d1, reset_l, rclk, adbginit_l, se
   );

   






   output             reset_d1;
   output 	     direction;
 
  

   output [15:0]     wrptr_l;
   output [15:0]     rdptr;
   output 	     fifo_sel15_12,fifo_sel11_8, fifo_sel7_4, fifo_sel3_0;
   output 	     fifo_bypass, fifo_bypass_l;
   output 	     fifo_valid;


   output [7:0]      qfull;
   output 	     input_req_sel, input_req_sel_d1;
   output 	     fifo_req_sel, current_req_sel;
   output 	     stall_a;
   

   output 	     ccx_dest_data_rdy_x;
   output 	     ccx_dest_atom_x;


   output [7:0]      arb_dp_q0_hold_a;
   output [7:0]      arb_dp_qsel0_a;
   output [7:0]      arb_dp_qsel1_a;
   output [7:0]      arb_dp_shift_x;




   output [7:0]		arbctl_atom;
   output		scan_out;

    



   input        src7_arb_atom_q;
   input        src6_arb_atom_q;  
   input        src5_arb_atom_q;  
   input        src4_arb_atom_q;  
   input        src3_arb_atom_q;  
   input        src2_arb_atom_q;  
   input        src1_arb_atom_q;  
   input        src0_arb_atom_q;  
                                  
                                  
   input        src7_arb_req_q;
   input        src6_arb_req_q;   
   input        src5_arb_req_q;   
   input        src4_arb_req_q;   
   input        src3_arb_req_q;   
   input        src2_arb_req_q;   
   input        src1_arb_req_q;   
   input        src0_arb_req_q;   
                                

   input 	     stall1_q;
   input 	     stall2_q;


   input 	     ccx_dest_data_rdy_a;
   input 	     ccx_dest_atom_a;
   input [7:0] 	     grant_a;
   input 	     req_pkt_empty;
   input 	     inreg_req_vld_d1;
   

   input 	     reset_l;

   input 	     rclk;

   input             adbginit_l;
   input             se;
   



   wire 	     reset;
   wire 	     dbginit;
   


   wire 	   fifo_rd_vld_d1;
   wire 	   fifo_wr_vld_d1;



   wire 	   fifo_empty_d1 ;
   wire 	   fifo_empty_d1_l;
   wire 	   fifo_empty_d2 ;
   wire 	   fifo_bypass_d1,fifo_bypass, fifo_bypass_l;
   wire 	   fifo_valid ;
   wire [4:0] 	   rdptr_mux,rdptr_d1, rdptr_inc,rdptr_inc_d1;
   wire [4:0] 	   wrptr,wrptr_d1, wrptr_inc;
   wire 	   wr_en, wr_en_d1 ;
   wire 	   rd_en, rd_en_d1 ;
   wire [15:0] 	   wrptr_dcd,wrptr_l;
   wire [15:0] 	   rdptr;
   wire 	   current_req_sel_d1;
   wire 	   fifo_req_sel_d1;
   wire 	   direction_in;
   wire		   stall1_a, stall2_a;
   wire            wrap_wren;
   
   wire            rdptr_dcd_3,
                   rdptr_dcd_7,
                   rdptr_dcd_11,
                   rdptr_dcd_15;



wire [7:0]		atom_a;
wire [7:0]		ctl_qsel0_a;
wire [7:0]		ctl_qsel1_a_l;
wire [7:0]		ctl_shift_a;


wire  ccx_reset_l_d1,ccx_reset2_l_d1;
wire  dbginit_d1;



   assign dbginit_d1 = ~ccx_reset2_l_d1;
   


   dffrl_async  ff_rstl(
                .din(reset_l),
                .q(ccx_reset_l_d1),
                .clk(rclk), 
                .se(se),
                .rst_l(adbginit_l));

   assign       reset_d1 = ~ccx_reset_l_d1;









   
   dffrl_async  ff_rstl2(
                .din(reset_l),
                .q(ccx_reset2_l_d1),
                .clk(rclk), 
                .se(se),
                .rst_l(adbginit_l));




   assign direction_in = ~direction | dbginit_d1;

   dff_s #(1) dff_ccx_com_dir(
            .din           (direction_in),
	    .q             (direction),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (1'b0),
	    .so            ());




   
   
   assign current_req_sel = ~req_pkt_empty & ~reset_d1;
   assign fifo_req_sel    =  req_pkt_empty & (fifo_valid & ~input_req_sel_d1) & ~reset_d1;
   assign input_req_sel   =  req_pkt_empty & ~(fifo_valid & ~input_req_sel_d1) | reset_d1;
   

      dff_s #(1) dff_ccx_com_dr(
            .din           (ccx_dest_data_rdy_a),
	    .q             (ccx_dest_data_rdy_x),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (1'b0),
	    .so            ());

      dff_s #(1) dff_ccx_atom_dr(         
            .din           (ccx_dest_atom_a),
	    .q             (ccx_dest_atom_x),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (1'b0),
	    .so            ());




   dff_s  dff_ccx_arb_stall1(
	.din           (stall1_q),
	.q             (stall1_a),
	.clk           (rclk),
	.se            (1'd0),
	.si            (1'd0),
	.so            ());

   dff_s  dff_ccx_arb_stall2(
	.din           (stall2_q),
	.q             (stall2_a),
	.clk           (rclk),
	.se            (1'd0),
	.si            (1'd0),
	.so            ());

assign	stall_a  =  stall1_a | stall2_a;

   dff_s  dff_ccx_arb_inpsel(
	.din           (input_req_sel),
	.q             (input_req_sel_d1),
	.clk           (rclk),
	.se            (1'd0),
	.si            (1'd0),
	.so            ());
   



   










 

   dff_s #(5) dff_ccx_com_fifo_wrptrd1(
            .din           (wrptr[4:0]),
	    .q             (wrptr_d1[4:0]),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (5'd0),
	    .so            ());



   dff_s #(5) dff_ccx_com_fifo_rdptrd1(
            .din           (rdptr_mux[4:0]),
	    .q             (rdptr_d1[4:0]),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (5'd0),
	    .so            ());

   dff_s #(1) dff_ccx_com_fifo_wrend1(
            .din           (wr_en),
	    .q             (wr_en_d1),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (1'b0),
	    .so            ());

   dff_s #(1) dff_ccx_com_fifo_rdend1(
            .din           (rd_en),
	    .q             (rd_en_d1),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (1'b0),
	    .so            ());
   
   dff_s #(1) dff_ccx_com_fifo_emptyd1(
            .din           (fifo_empty_d1),
	    .q             (fifo_empty_d2),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (1'b0),
	    .so            ());
   

   dff_s #(1) dff_ccx_com_fifo_bypassd1(
            .din           (fifo_bypass),
	    .q             (fifo_bypass_d1),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (1'b0),
	    .so            ());

   
   dff_s #(1) dff_ccx_com_fifo_fifoseld1(
            .din           (fifo_req_sel),
	    .q             (fifo_req_sel_d1),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (1'b0),
	    .so            ());

      dff_s #(1) dff_ccx_com_fifo_currseld1(
            .din           (current_req_sel),
	    .q             (current_req_sel_d1),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (1'b0),
	    .so            ());

      dff_s #(5) dff_ccx_rdptr_incd1(
            .din           (rdptr_inc[4:0]),
	    .q             (rdptr_inc_d1[4:0]),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (5'd0),
	    .so            ());





   assign fifo_rd_vld_d1 =  rd_en_d1 & ~fifo_bypass_d1 & fifo_req_sel_d1;

   assign fifo_wr_vld_d1 =  wr_en_d1 & ~(fifo_bypass_d1 & fifo_req_sel_d1);





























   assign fifo_empty_d1 = &(wrptr[4:0] ~^ rdptr_mux[4:0]);
   assign fifo_empty_d1_l = ~fifo_empty_d1 ;



   assign fifo_bypass   = inreg_req_vld_d1 & fifo_empty_d1 ;
   assign fifo_bypass_l = ~fifo_bypass;



   assign fifo_valid    = inreg_req_vld_d1 | fifo_empty_d1_l;






   assign rdptr_inc[0] = ~rdptr_mux[0];
   assign rdptr_inc[1] =  rdptr_mux[1] ^ rdptr_mux[0];
   assign rdptr_inc[2] = (~&(rdptr_mux[1:0]) ~^ rdptr_mux[2]);
   assign rdptr_inc[3] = (~&(rdptr_mux[2:0]) ~^ rdptr_mux[3]);
   assign rdptr_inc[4] = (~&(rdptr_mux[3:0]) ~^ rdptr_mux[4]);


   assign wrptr_inc[0] = ~wrptr_d1[0];
   assign wrptr_inc[1] =  wrptr_d1[1] ^ wrptr_d1[0];
   assign wrptr_inc[2] = (~&(wrptr_d1[1:0]) ~^ wrptr_d1[2]);
   assign wrptr_inc[3] = (~&(wrptr_d1[2:0]) ~^ wrptr_d1[3]);
   assign wrptr_inc[4] = (~&(wrptr_d1[3:0]) ~^ wrptr_d1[4]);

 



   assign wrptr[4:0] = (fifo_empty_d2 & ~fifo_wr_vld_d1| reset_d1) ? 5'h0 : (fifo_wr_vld_d1 ? wrptr_inc[4:0] : wrptr_d1[4:0]);


   assign wrptr_dcd[0]  =  (~wrptr[3] & ~wrptr[2] & ~wrptr[1] & ~wrptr[0]);
   assign wrptr_dcd[1]  =  (~wrptr[3] & ~wrptr[2] & ~wrptr[1] &  wrptr[0]);
   assign wrptr_dcd[2]  =  (~wrptr[3] & ~wrptr[2] &  wrptr[1] & ~wrptr[0]);
   assign wrptr_dcd[3]  =  (~wrptr[3] & ~wrptr[2] &  wrptr[1] &  wrptr[0]);
   assign wrptr_dcd[4]  =  (~wrptr[3] &  wrptr[2] & ~wrptr[1] & ~wrptr[0]);
   assign wrptr_dcd[5]  =  (~wrptr[3] &  wrptr[2] & ~wrptr[1] &  wrptr[0]);
   assign wrptr_dcd[6]  =  (~wrptr[3] &  wrptr[2] &  wrptr[1] & ~wrptr[0]);
   assign wrptr_dcd[7]  =  (~wrptr[3] &  wrptr[2] &  wrptr[1] &  wrptr[0]);
   assign wrptr_dcd[8]  =  ( wrptr[3] & ~wrptr[2] & ~wrptr[1] & ~wrptr[0]);
   assign wrptr_dcd[9]  =  ( wrptr[3] & ~wrptr[2] & ~wrptr[1] &  wrptr[0]);
   assign wrptr_dcd[10] =  ( wrptr[3] & ~wrptr[2] &  wrptr[1] & ~wrptr[0]);
   assign wrptr_dcd[11] =  ( wrptr[3] & ~wrptr[2] &  wrptr[1] &  wrptr[0]);
   assign wrptr_dcd[12] =  ( wrptr[3] &  wrptr[2] & ~wrptr[1] & ~wrptr[0]);
   assign wrptr_dcd[13] =  ( wrptr[3] &  wrptr[2] & ~wrptr[1] &  wrptr[0]);
   assign wrptr_dcd[14] =  ( wrptr[3] &  wrptr[2] &  wrptr[1] & ~wrptr[0]);
   assign wrptr_dcd[15] =  ( wrptr[3] &  wrptr[2] &  wrptr[1] &  wrptr[0]);

   assign wrptr_l[15:0] = ~(wrptr_dcd[15:0]);
   

   assign rdptr_mux[4:0]=(fifo_empty_d2 & ~fifo_wr_vld_d1 | reset_d1) ? 5'h0 : (fifo_rd_vld_d1 ? rdptr_inc_d1[4:0] : rdptr_d1[4:0]);    



   assign rdptr[0]  =  (~rdptr_mux[3] & ~rdptr_mux[2] & ~rdptr_mux[1] & ~rdptr_mux[0]);
   assign rdptr[1]  =  (~rdptr_mux[3] & ~rdptr_mux[2] & ~rdptr_mux[1] &  rdptr_mux[0]);
   assign rdptr[2]  =  (~rdptr_mux[3] & ~rdptr_mux[2] &  rdptr_mux[1] & ~rdptr_mux[0]);
   assign rdptr[3]  =  ~|rdptr[2:0];
   assign rdptr_dcd_3  =  (~rdptr_mux[3] & ~rdptr_mux[2] &  rdptr_mux[1] &  rdptr_mux[0]);

   assign rdptr[4]  =  (~rdptr_mux[3] &  rdptr_mux[2] & ~rdptr_mux[1] & ~rdptr_mux[0]);
   assign rdptr[5]  =  (~rdptr_mux[3] &  rdptr_mux[2] & ~rdptr_mux[1] &  rdptr_mux[0]);
   assign rdptr[6]  =  (~rdptr_mux[3] &  rdptr_mux[2] &  rdptr_mux[1] & ~rdptr_mux[0]);
   assign rdptr[7]  =  ~|rdptr[6:4];
   assign rdptr_dcd_7  =  (~rdptr_mux[3] &  rdptr_mux[2] &  rdptr_mux[1] &  rdptr_mux[0]);

   assign rdptr[8]  =  ( rdptr_mux[3] & ~rdptr_mux[2] & ~rdptr_mux[1] & ~rdptr_mux[0]);
   assign rdptr[9]  =  ( rdptr_mux[3] & ~rdptr_mux[2] & ~rdptr_mux[1] &  rdptr_mux[0]);
   assign rdptr[10] =  ( rdptr_mux[3] & ~rdptr_mux[2] &  rdptr_mux[1] & ~rdptr_mux[0]);
   assign rdptr[11] =  ~|rdptr[10:8];
   assign rdptr_dcd_11 =  ( rdptr_mux[3] & ~rdptr_mux[2] &  rdptr_mux[1] &  rdptr_mux[0]);

   assign rdptr[12] =  ( rdptr_mux[3] &  rdptr_mux[2] & ~rdptr_mux[1] & ~rdptr_mux[0]);
   assign rdptr[13] =  ( rdptr_mux[3] &  rdptr_mux[2] & ~rdptr_mux[1] &  rdptr_mux[0]);
   assign rdptr[14] =  ( rdptr_mux[3] &  rdptr_mux[2] &  rdptr_mux[1] & ~rdptr_mux[0]);
   assign rdptr[15] =  ~|rdptr[14:12];
   assign rdptr_dcd_15 =  ( rdptr_mux[3] &  rdptr_mux[2] &  rdptr_mux[1] &  rdptr_mux[0]);


   assign fifo_sel15_12 = |({rdptr_dcd_15,rdptr[14:12]});
   assign fifo_sel11_8  = |({rdptr_dcd_11,rdptr[10:8]});
   assign fifo_sel7_4   = |({rdptr_dcd_7, rdptr[6:4]});
   assign fifo_sel3_0   = |({rdptr_dcd_3, rdptr[2:0]});




   assign wrap_wren  = ~(&(wrptr[3:0] ~^ rdptr_mux[3:0]) & (wrptr_inc[4] ^ rdptr_inc[4])) | fifo_empty_d1;
   
   assign wr_en = (inreg_req_vld_d1 & (fifo_req_sel_d1 | current_req_sel_d1)) & wrap_wren & ~reset_d1;


   assign rd_en = fifo_empty_d1_l & ~reset_d1 ;






   ccx_arb_srcq q0(

		   .qfull		(qfull[0]),
		   .qsel0		(arb_dp_qsel0_a[0]),
		   .qsel1		(arb_dp_qsel1_a[0]),
		   .shift_x		(arb_dp_shift_x[0]),
		   .ctl_qsel0_a		(ctl_qsel0_a[0]),
		   .ctl_qsel1_a_l	(ctl_qsel1_a_l[0]),
		   .ctl_shift_a		(ctl_shift_a[0]),
		   .q0_hold_a		(arb_dp_q0_hold_a[0]),
		   .atom_a		(atom_a[0]),

		   .req_q		(src0_arb_req_q),
		   .atom_q		(src0_arb_atom_q),
		   .grant_a		(grant_a[0]),
		   .rclk		(rclk),
		   .reset_d1		(reset_d1));
   ccx_arb_srcq q1(

		   .qfull		(qfull[1]),
		   .qsel0		(arb_dp_qsel0_a[1]),
		   .qsel1		(arb_dp_qsel1_a[1]),
		   .shift_x		(arb_dp_shift_x[1]),
		   .ctl_qsel0_a		(ctl_qsel0_a[1]),
		   .ctl_qsel1_a_l	(ctl_qsel1_a_l[1]),
		   .ctl_shift_a		(ctl_shift_a[1]),
		   .q0_hold_a		(arb_dp_q0_hold_a[1]),
		   .atom_a		(atom_a[1]),

		   .req_q		(src1_arb_req_q),
		   .atom_q		(src1_arb_atom_q),
		   .grant_a		(grant_a[1]),
		   .rclk		(rclk),
		   .reset_d1		(reset_d1));
   ccx_arb_srcq q2(

		   .qfull		(qfull[2]),
		   .qsel0		(arb_dp_qsel0_a[2]),
		   .qsel1		(arb_dp_qsel1_a[2]),
		   .shift_x		(arb_dp_shift_x[2]),
		   .ctl_qsel0_a		(ctl_qsel0_a[2]),
		   .ctl_qsel1_a_l	(ctl_qsel1_a_l[2]),
		   .ctl_shift_a		(ctl_shift_a[2]),
		   .q0_hold_a		(arb_dp_q0_hold_a[2]),
		   .atom_a		(atom_a[2]),

		   .req_q		(src2_arb_req_q),
		   .atom_q		(src2_arb_atom_q),
		   .grant_a		(grant_a[2]),
		   .rclk		(rclk),
		   .reset_d1		(reset_d1));
   ccx_arb_srcq q3(

		   .qfull		(qfull[3]),
		   .qsel0		(arb_dp_qsel0_a[3]),
		   .qsel1		(arb_dp_qsel1_a[3]),
		   .shift_x		(arb_dp_shift_x[3]),
		   .ctl_qsel0_a		(ctl_qsel0_a[3]),
		   .ctl_qsel1_a_l	(ctl_qsel1_a_l[3]),
		   .ctl_shift_a		(ctl_shift_a[3]),
		   .q0_hold_a		(arb_dp_q0_hold_a[3]),
		   .atom_a		(atom_a[3]),

		   .req_q		(src3_arb_req_q),
		   .atom_q		(src3_arb_atom_q),
		   .grant_a		(grant_a[3]),
		   .rclk		(rclk),
		   .reset_d1		(reset_d1));
   ccx_arb_srcq q4(

		   .qfull		(qfull[4]),
		   .qsel0		(arb_dp_qsel0_a[4]),
		   .qsel1		(arb_dp_qsel1_a[4]),
		   .shift_x		(arb_dp_shift_x[4]),
		   .ctl_qsel0_a		(ctl_qsel0_a[4]),
		   .ctl_qsel1_a_l	(ctl_qsel1_a_l[4]),
		   .ctl_shift_a		(ctl_shift_a[4]),
		   .q0_hold_a		(arb_dp_q0_hold_a[4]),
		   .atom_a		(atom_a[4]),

		   .req_q		(src4_arb_req_q),
		   .atom_q		(src4_arb_atom_q),
		   .grant_a		(grant_a[4]),
		   .rclk		(rclk),
		   .reset_d1		(reset_d1));
   ccx_arb_srcq q5(

		   .qfull		(qfull[5]),
		   .qsel0		(arb_dp_qsel0_a[5]),
		   .qsel1		(arb_dp_qsel1_a[5]),
		   .shift_x		(arb_dp_shift_x[5]),
		   .ctl_qsel0_a		(ctl_qsel0_a[5]),
		   .ctl_qsel1_a_l	(ctl_qsel1_a_l[5]),
		   .ctl_shift_a		(ctl_shift_a[5]),
		   .q0_hold_a		(arb_dp_q0_hold_a[5]),
		   .atom_a		(atom_a[5]),

		   .req_q		(src5_arb_req_q),
		   .atom_q		(src5_arb_atom_q),
		   .grant_a		(grant_a[5]),
		   .rclk		(rclk),
		   .reset_d1		(reset_d1));
   ccx_arb_srcq q6(

		   .qfull		(qfull[6]),
		   .qsel0		(arb_dp_qsel0_a[6]),
		   .qsel1		(arb_dp_qsel1_a[6]),
		   .shift_x		(arb_dp_shift_x[6]),
		   .ctl_qsel0_a		(ctl_qsel0_a[6]),
		   .ctl_qsel1_a_l	(ctl_qsel1_a_l[6]),
		   .ctl_shift_a		(ctl_shift_a[6]),
		   .q0_hold_a		(arb_dp_q0_hold_a[6]),
		   .atom_a		(atom_a[6]),

		   .req_q		(src6_arb_req_q),
		   .atom_q		(src6_arb_atom_q),
		   .grant_a		(grant_a[6]),
		   .rclk		(rclk),
		   .reset_d1		(reset_d1));
   ccx_arb_srcq q7(

		   .qfull		(qfull[7]),
		   .qsel0		(arb_dp_qsel0_a[7]),
		   .qsel1		(arb_dp_qsel1_a[7]),
		   .shift_x		(arb_dp_shift_x[7]),
		   .ctl_qsel0_a		(ctl_qsel0_a[7]),
		   .ctl_qsel1_a_l	(ctl_qsel1_a_l[7]),
		   .ctl_shift_a		(ctl_shift_a[7]),
		   .q0_hold_a		(arb_dp_q0_hold_a[7]),
		   .atom_a		(atom_a[7]),

		   .req_q		(src7_arb_req_q),
		   .atom_q		(src7_arb_atom_q),
		   .grant_a		(grant_a[7]),
		   .rclk		(rclk),
		   .reset_d1		(reset_d1));



   ccx_arb_atomq atomq0(

			.q0_dataout	(arbctl_atom[0]),
`ifdef FPGA_SYN
			.scan_out	(),
`else 
			.scan_out	(scan_out),
`endif

			.ctl_qsel1_a_l	(ctl_qsel1_a_l[0]),
			.ctl_qsel0_a	(ctl_qsel0_a[0]),
			.ctl_shift_a	(ctl_shift_a[0]),
			.atom_a		(atom_a[0]),
			.rclk		(rclk),
			.reset_d1	(reset_d1));
   ccx_arb_atomq atomq1(

			.q0_dataout	(arbctl_atom[1]),
`ifdef FPGA_SYN
			.scan_out	(),
`else 
			.scan_out	(scan_out),
`endif

			.ctl_qsel1_a_l	(ctl_qsel1_a_l[1]),
			.ctl_qsel0_a	(ctl_qsel0_a[1]),
			.ctl_shift_a	(ctl_shift_a[1]),
			.atom_a		(atom_a[1]),
			.rclk		(rclk),
			.reset_d1	(reset_d1));
   ccx_arb_atomq atomq2(

			.q0_dataout	(arbctl_atom[2]),
`ifdef FPGA_SYN
			.scan_out	(),
`else 
			.scan_out	(scan_out),
`endif

			.ctl_qsel1_a_l	(ctl_qsel1_a_l[2]),
			.ctl_qsel0_a	(ctl_qsel0_a[2]),
			.ctl_shift_a	(ctl_shift_a[2]),
			.atom_a		(atom_a[2]),
			.rclk		(rclk),
			.reset_d1	(reset_d1));
   ccx_arb_atomq atomq3(

			.q0_dataout	(arbctl_atom[3]),
`ifdef FPGA_SYN
			.scan_out	(),
`else 
			.scan_out	(scan_out),
`endif

			.ctl_qsel1_a_l	(ctl_qsel1_a_l[3]),
			.ctl_qsel0_a	(ctl_qsel0_a[3]),
			.ctl_shift_a	(ctl_shift_a[3]),
			.atom_a		(atom_a[3]),
			.rclk		(rclk),
			.reset_d1	(reset_d1));
   ccx_arb_atomq atomq4(

			.q0_dataout	(arbctl_atom[4]),
`ifdef FPGA_SYN
			.scan_out	(),
`else 
			.scan_out	(scan_out),
`endif

			.ctl_qsel1_a_l	(ctl_qsel1_a_l[4]),
			.ctl_qsel0_a	(ctl_qsel0_a[4]),
			.ctl_shift_a	(ctl_shift_a[4]),
			.atom_a		(atom_a[4]),
			.rclk		(rclk),
			.reset_d1	(reset_d1));
   ccx_arb_atomq atomq5(

			.q0_dataout	(arbctl_atom[5]),
`ifdef FPGA_SYN
			.scan_out	(),
`else 
			.scan_out	(scan_out),
`endif

			.ctl_qsel1_a_l	(ctl_qsel1_a_l[5]),
			.ctl_qsel0_a	(ctl_qsel0_a[5]),
			.ctl_shift_a	(ctl_shift_a[5]),
			.atom_a		(atom_a[5]),
			.rclk		(rclk),
			.reset_d1	(reset_d1));
   ccx_arb_atomq atomq6(

			.q0_dataout	(arbctl_atom[6]),
`ifdef FPGA_SYN
			.scan_out	(),
`else 
			.scan_out	(scan_out),
`endif

			.ctl_qsel1_a_l	(ctl_qsel1_a_l[6]),
			.ctl_qsel0_a	(ctl_qsel0_a[6]),
			.ctl_shift_a	(ctl_shift_a[6]),
			.atom_a		(atom_a[6]),
			.rclk		(rclk),
			.reset_d1	(reset_d1));
   ccx_arb_atomq atomq7(

			.q0_dataout	(arbctl_atom[7]),
`ifdef FPGA_SYN
			.scan_out	(),
`else 
			.scan_out	(scan_out),
`endif

			.ctl_qsel1_a_l	(ctl_qsel1_a_l[7]),
			.ctl_qsel0_a	(ctl_qsel0_a[7]),
			.ctl_shift_a	(ctl_shift_a[7]),
			.atom_a		(atom_a[7]),
			.rclk		(rclk),
			.reset_d1	(reset_d1));

endmodule