data/full_repos/permissive/453763315/datacache.v
1: b'%Warning-WIDTH: data/full_repos/permissive/453763315/datacache.v:12: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 11 bits.\n                                                                   : ... In instance datacache\n     read <= cache[address];\n          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/453763315/datacache.v:13: Operator ASSIGNDLY expects 11 bits on the Assign RHS, but Assign RHS\'s VARREF \'write\' generates 8 bits.\n                                                                   : ... In instance datacache\n     if (!rw) cache[address] <= write;\n                             ^~\n%Error: Exiting due to 2 warning(s)\n'
module datacache(clk, rw, address, write, read, en);
  input clk;
  input en;
  input reg rw;
  input reg [10:0] address;
  input reg [7:0] write;
  output reg [7:0] read;
  reg [7:0][10:0] cache;

  always @(posedge clk or negedge clk) begin
    if (en) begin
    	read <= cache[address];
    	if (!rw) cache[address] <= write;
    end
  end
endmodule
module datacache(clk, rw, address, write, read, en);

  input clk;
  input en;
  input reg rw;
  input reg [10:0] address;
  input reg [7:0] write;
  output reg [7:0] read;
  reg [7:0][10:0] cache;

  always @(posedge clk or negedge clk) begin
    if (en) begin
    	read <= cache[address];
    	if (!rw) cache[address] <= write;
    end
  end
endmodule