data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v
1: b'%Warning-WIDTH: data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v:107: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                  : ... In instance part3.u2\n    X_out <= Location[7:0] + Counter[1:0];\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v:108: Operator ADD expects 7 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                  : ... In instance part3.u2\n    Y_out <= Location[14:8] + Counter[3:2];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v:113: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                  : ... In instance part3.u2\n    X_out <= Location[7:0] + Counter[1:0];\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v:114: Operator ADD expects 7 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                  : ... In instance part3.u2\n    Y_out <= Location[14:8] + Counter[3:2];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v:40: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'Divider\' generates 7 bits.\n                                                                                 : ... In instance part3.u0\n  else if(Divider == (Frame_num - 1))\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v:49: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'Divider\' generates 7 bits.\n                                                                                 : ... In instance part3.u0\n  else if(Divider == (Frame_num - 1))\n                  ^~\n%Error: Exiting due to 6 warning(s)\n'
module datapath(Clock, Resetn, Color, Width_max, Height_max, X_out, Y_out, Color_out, Counter, Create_enable, Black_enable, Move_enable);
	
	input Clock, Resetn, Create_enable, Black_enable, Move_enable;
	input [2:0] Color;
	input [6:0] Height_max;
	input [7:0] Width_max;
	
	output reg [2:0] Color_out;	
	output reg [3:0] Counter;
	output reg [6:0] Y_out;
	output reg [7:0] X_out;

	reg [1:0] Direction;
	reg [14:0] Location;
	
	
	always @ (posedge Clock)
	begin
		if (Resetn == 0)
			Location <= 0;
		else if (Create_enable == 1)
			begin
				X_out <= Location[7:0] + Counter[1:0];
				Y_out <= Location[14:8] + Counter[3:2];
				Color_out <= Color;
			end
		else if (Black_enable == 1)
			begin
				X_out <= Location[7:0] + Counter[1:0];
				Y_out <= Location[14:8] + Counter[3:2];
				Color_out <= 0;
			end
		else if (Move_enable == 1)
			begin
				if(Direction[0] == 1'b1)
					Location[7:0] <= Location[7:0] + 1;
				else
					Location[7:0] <= Location[7:0] - 1;
				if(Direction[1] == 1'b1)
					Location[14:8] <= Location[14:8] + 1;
				else
					Location[14:8] <= Location[14:8] - 1;
			end
	end

	
	always @ (posedge Clock)
		begin
			if (Resetn == 1'b0)
				Direction <= 2'b11;
			else
				begin
					if (Location[7:0] == 0)
						Direction[0] <= 1'b1;
					if (Location[7:0] == Width_max)
						Direction[0] <= 1'b0;
					if (Location[14:8] == 0)
						Direction[1] <= 1'b1;
					if (Location[14:8] == Height_max)
						Direction[1] <= 1'b0;
				end
		end
    
	
	always @ (posedge Clock)
		begin
			if (Resetn == 0)
				Counter <= 4'b0000;
			else if (Counter == 4'b1111)
				Counter <= 4'b0000;
			else if (Create_enable == 1 || Black_enable == 1)
				Counter <= Counter + 1;
		end

endmodule
module datapath(Clock, Resetn, Color, Width_max, Height_max, X_out, Y_out, Color_out, Counter, Create_enable, Black_enable, Move_enable);

	
	input Clock, Resetn, Create_enable, Black_enable, Move_enable;
	input [2:0] Color;
	input [6:0] Height_max;
	input [7:0] Width_max;
	
	output reg [2:0] Color_out;	
	output reg [3:0] Counter;
	output reg [6:0] Y_out;
	output reg [7:0] X_out;

	reg [1:0] Direction;
	reg [14:0] Location;
	
	
	always @ (posedge Clock)
	begin
		if (Resetn == 0)
			Location <= 0;
		else if (Create_enable == 1)
			begin
				X_out <= Location[7:0] + Counter[1:0];
				Y_out <= Location[14:8] + Counter[3:2];
				Color_out <= Color;
			end
		else if (Black_enable == 1)
			begin
				X_out <= Location[7:0] + Counter[1:0];
				Y_out <= Location[14:8] + Counter[3:2];
				Color_out <= 0;
			end
		else if (Move_enable == 1)
			begin
				if(Direction[0] == 1'b1)
					Location[7:0] <= Location[7:0] + 1;
				else
					Location[7:0] <= Location[7:0] - 1;
				if(Direction[1] == 1'b1)
					Location[14:8] <= Location[14:8] + 1;
				else
					Location[14:8] <= Location[14:8] - 1;
			end
	end

	
	always @ (posedge Clock)
		begin
			if (Resetn == 1'b0)
				Direction <= 2'b11;
			else
				begin
					if (Location[7:0] == 0)
						Direction[0] <= 1'b1;
					if (Location[7:0] == Width_max)
						Direction[0] <= 1'b0;
					if (Location[14:8] == 0)
						Direction[1] <= 1'b1;
					if (Location[14:8] == Height_max)
						Direction[1] <= 1'b0;
				end
		end
    
	
	always @ (posedge Clock)
		begin
			if (Resetn == 0)
				Counter <= 4'b0000;
			else if (Counter == 4'b1111)
				Counter <= 4'b0000;
			else if (Create_enable == 1 || Black_enable == 1)
				Counter <= Counter + 1;
		end

endmodule