data/full_repos/permissive/458737381/src/verilog-parser/tests/cpx_datacx2_ff.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/cpx_datacx2_ff.v:25: Cannot find include file: sys.h\n`include "sys.h" // system level definition file which contains the  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/cpx_datacx2_ff.v:28: Cannot find include file: iop.h\n`include "iop.h" \n         ^~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/cpx_datacx2_ff.v:44: Define or directive not defined: \'`CPX_WIDTH\'\n   output [`CPX_WIDTH-1:0]  cpx_spc_data_cx2; \n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/cpx_datacx2_ff.v:48: Define or directive not defined: \'`CPX_WIDTH\'\n   input [`CPX_WIDTH-1:0]  cpx_spc_data_cx_l; \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/cpx_datacx2_ff.v:55: Define or directive not defined: \'`CPX_WIDTH\'\n   wire [`CPX_WIDTH-1:0]  cpx_spc_data_cx2_l; \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/cpx_datacx2_ff.v:58: Define or directive not defined: \'`CPX_WIDTH\'\n   dff_s #(`CPX_WIDTH) dff_ccx_data_spc(\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/cpx_datacx2_ff.v:59: Define or directive not defined: \'`CPX_WIDTH\'\n            .din           (cpx_spc_data_cx_l[`CPX_WIDTH-1:0]),\n                                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/cpx_datacx2_ff.v:60: Define or directive not defined: \'`CPX_WIDTH\'\n     .q             (cpx_spc_data_cx2_l[`CPX_WIDTH-1:0]),\n                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/cpx_datacx2_ff.v:63: Define or directive not defined: \'`CPX_WIDTH\'\n     .si            (`CPX_WIDTH\'d0),\n                     ^~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n'
module cpx_datacx2_ff(

   cpx_spc_data_cx2, cpx_spc_data_rdy_cx2, so, 

   cpx_spc_data_cx_l, cpx_spc_data_rdy_cx, rclk, si, se
   );
   

   output [`CPX_WIDTH-1:0]		cpx_spc_data_cx2;	
   output 		cpx_spc_data_rdy_cx2;	
   output 		so;
   
   input [`CPX_WIDTH-1:0]		cpx_spc_data_cx_l;	
   input 		cpx_spc_data_rdy_cx;	
   input 		rclk;
   input 		si;
   input 		se;
   

   wire [`CPX_WIDTH-1:0]		cpx_spc_data_cx2_l;	
   
   
   dff_s #(`CPX_WIDTH) dff_ccx_data_spc(
            .din           (cpx_spc_data_cx_l[`CPX_WIDTH-1:0]),
	    .q             (cpx_spc_data_cx2_l[`CPX_WIDTH-1:0]),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (`CPX_WIDTH'd0),
	    .so            ());



assign cpx_spc_data_cx2 = ~cpx_spc_data_cx2_l; 



      dff_s #(1) dff_ccx_datardy_spc(
            .din           (cpx_spc_data_rdy_cx),
	    .q             (cpx_spc_data_rdy_cx2),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (1'd0),
	    .so            ());


endmodule
module cpx_datacx2_ff(

   cpx_spc_data_cx2, cpx_spc_data_rdy_cx2, so, 

   cpx_spc_data_cx_l, cpx_spc_data_rdy_cx, rclk, si, se
   );

   

   output [`CPX_WIDTH-1:0]		cpx_spc_data_cx2;	
   output 		cpx_spc_data_rdy_cx2;	
   output 		so;
   
   input [`CPX_WIDTH-1:0]		cpx_spc_data_cx_l;	
   input 		cpx_spc_data_rdy_cx;	
   input 		rclk;
   input 		si;
   input 		se;
   

   wire [`CPX_WIDTH-1:0]		cpx_spc_data_cx2_l;	
   
   
   dff_s #(`CPX_WIDTH) dff_ccx_data_spc(
            .din           (cpx_spc_data_cx_l[`CPX_WIDTH-1:0]),
	    .q             (cpx_spc_data_cx2_l[`CPX_WIDTH-1:0]),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (`CPX_WIDTH'd0),
	    .so            ());



assign cpx_spc_data_cx2 = ~cpx_spc_data_cx2_l; 



      dff_s #(1) dff_ccx_datardy_spc(
            .din           (cpx_spc_data_rdy_cx),
	    .q             (cpx_spc_data_rdy_cx2),
	    .clk           (rclk),
	    .se            (1'b0),
	    .si            (1'd0),
	    .so            ());


endmodule