data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v
1: b'%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:15: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[0:0] <= din;\n                            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:17: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[1:1] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:19: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[2:2] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:21: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[3:3] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:23: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[4:4] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:25: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[5:5] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:27: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[6:6] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:29: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[7:7] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:31: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[8:8] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:33: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[9:9] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:35: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[10:10] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:37: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[11:11] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:39: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[12:12] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:41: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[13:13] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:43: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[14:14] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:45: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[15:15] <= din;\n                              ^~\n%Warning-WIDTHCONCAT: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:13: Unsized numbers/parameters not allowed in replications.\n                                                                                                                               : ... In instance forloop_select_gate\n              case (({(ctrl)*(0)})+(0))\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:49: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[0:0] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:51: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[1:1] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:53: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[2:2] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:55: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[3:3] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:57: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[4:4] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:59: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[5:5] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:61: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[6:6] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:63: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[7:7] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:65: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[8:8] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:67: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[9:9] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:69: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[10:10] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:71: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[11:11] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:73: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[12:12] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:75: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[13:13] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:77: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[14:14] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:79: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[15:15] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:83: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[0:0] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:85: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[1:1] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:87: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[2:2] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:89: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[3:3] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:91: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[4:4] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:93: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[5:5] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:95: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[6:6] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:97: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[7:7] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:99: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                         : ... In instance forloop_select_gate\n                  dout[8:8] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:101: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[9:9] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:103: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[10:10] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:105: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[11:11] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:107: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[12:12] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:109: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[13:13] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:111: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[14:14] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:113: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[15:15] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:117: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[0:0] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:119: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[1:1] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:121: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[2:2] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:123: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[3:3] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:125: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[4:4] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:127: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[5:5] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:129: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[6:6] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:131: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[7:7] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:133: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[8:8] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:135: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[9:9] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:137: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[10:10] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:139: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[11:11] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:141: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[12:12] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:143: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[13:13] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:145: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[14:14] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:147: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[15:15] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:151: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[0:0] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:153: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[1:1] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:155: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[2:2] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:157: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[3:3] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:159: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[4:4] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:161: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[5:5] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:163: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[6:6] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:165: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[7:7] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:167: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[8:8] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:169: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[9:9] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:171: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[10:10] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:173: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[11:11] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:175: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[12:12] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:177: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[13:13] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:179: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[14:14] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:181: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[15:15] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:185: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[0:0] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:187: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[1:1] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:189: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[2:2] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:191: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[3:3] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:193: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[4:4] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:195: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[5:5] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:197: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[6:6] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:199: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[7:7] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:201: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[8:8] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:203: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[9:9] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:205: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[10:10] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:207: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[11:11] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:209: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[12:12] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:211: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[13:13] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:213: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[14:14] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:215: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[15:15] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:219: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[0:0] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:221: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[1:1] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:223: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[2:2] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:225: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[3:3] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:227: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[4:4] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:229: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[5:5] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:231: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[6:6] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:233: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[7:7] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:235: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[8:8] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:237: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[9:9] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:239: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[10:10] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:241: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[11:11] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:243: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[12:12] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:245: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[13:13] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:247: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[14:14] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:249: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[15:15] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:253: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[0:0] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:255: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[1:1] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:257: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[2:2] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:259: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[3:3] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:261: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[4:4] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:263: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[5:5] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:265: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[6:6] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:267: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[7:7] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:269: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[8:8] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:271: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[9:9] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:273: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[10:10] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:275: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[11:11] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:277: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[12:12] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:279: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[13:13] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:281: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[14:14] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:283: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[15:15] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:287: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[0:0] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:289: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[1:1] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:291: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[2:2] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:293: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[3:3] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:295: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[4:4] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:297: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[5:5] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:299: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[6:6] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:301: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[7:7] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:303: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[8:8] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:305: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[9:9] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:307: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[10:10] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:309: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[11:11] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:311: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[12:12] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:313: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[13:13] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:315: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[14:14] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:317: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[15:15] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:321: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[0:0] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:323: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[1:1] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:325: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[2:2] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:327: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[3:3] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:329: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[4:4] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:331: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[5:5] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:333: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[6:6] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:335: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[7:7] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:337: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[8:8] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:339: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[9:9] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:341: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[10:10] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:343: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[11:11] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:345: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[12:12] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:347: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[13:13] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:349: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[14:14] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:351: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[15:15] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:355: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[0:0] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:357: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[1:1] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:359: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[2:2] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:361: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[3:3] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:363: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[4:4] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:365: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[5:5] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:367: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[6:6] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:369: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[7:7] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:371: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[8:8] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:373: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[9:9] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:375: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[10:10] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:377: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[11:11] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:379: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[12:12] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:381: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[13:13] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:383: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[14:14] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:385: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[15:15] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:389: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[0:0] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:391: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[1:1] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:393: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[2:2] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:395: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[3:3] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:397: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[4:4] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:399: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[5:5] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:401: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[6:6] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:403: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[7:7] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:405: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[8:8] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:407: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[9:9] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:409: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[10:10] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:411: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[11:11] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:413: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[12:12] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:415: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[13:13] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:417: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[14:14] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:419: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[15:15] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:423: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[0:0] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:425: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[1:1] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:427: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[2:2] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:429: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[3:3] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:431: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[4:4] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:433: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[5:5] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:435: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[6:6] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:437: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[7:7] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:439: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[8:8] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:441: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[9:9] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:443: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[10:10] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:445: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[11:11] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:447: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[12:12] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:449: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[13:13] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:451: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[14:14] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:453: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[15:15] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:457: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[0:0] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:459: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[1:1] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:461: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[2:2] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:463: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[3:3] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:465: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[4:4] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:467: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[5:5] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:469: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[6:6] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:471: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[7:7] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:473: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[8:8] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:475: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[9:9] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:477: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[10:10] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:479: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[11:11] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:481: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[12:12] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:483: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[13:13] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:485: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[14:14] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:487: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[15:15] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:491: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[0:0] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:493: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[1:1] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:495: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[2:2] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:497: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[3:3] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:499: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[4:4] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:501: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[5:5] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:503: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[6:6] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:505: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[7:7] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:507: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[8:8] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:509: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[9:9] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:511: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[10:10] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:513: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[11:11] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:515: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[12:12] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:517: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[13:13] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:519: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[14:14] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:521: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[15:15] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:525: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[0:0] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:527: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[1:1] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:529: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[2:2] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:531: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[3:3] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:533: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[4:4] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:535: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[5:5] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:537: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[6:6] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:539: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[7:7] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:541: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[8:8] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:543: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[9:9] <= din;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:545: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[10:10] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:547: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[11:11] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:549: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[12:12] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:551: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[13:13] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:553: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[14:14] <= din;\n                              ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select_gate.v:555: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                          : ... In instance forloop_select_gate\n                  dout[15:15] <= din;\n                              ^~\n%Error: Exiting due to 257 warning(s)\n'
module forloop_select_gate (clk, ctrl, din, en, dout);
      input wire clk;
      input wire [3:0] ctrl;
      input wire [15:0] din;
      input wire en;
      output reg [15:0] dout;
      reg [4:0] sel;
      always @(posedge clk)
        case (|(en))
          1'b 1:
            begin
              case (({(ctrl)*(0)})+(0))
                0:
                  dout[0:0] <= din;
                1:
                  dout[1:1] <= din;
                2:
                  dout[2:2] <= din;
                3:
                  dout[3:3] <= din;
                4:
                  dout[4:4] <= din;
                5:
                  dout[5:5] <= din;
                6:
                  dout[6:6] <= din;
                7:
                  dout[7:7] <= din;
                8:
                  dout[8:8] <= din;
                9:
                  dout[9:9] <= din;
                10:
                  dout[10:10] <= din;
                11:
                  dout[11:11] <= din;
                12:
                  dout[12:12] <= din;
                13:
                  dout[13:13] <= din;
                14:
                  dout[14:14] <= din;
                15:
                  dout[15:15] <= din;
              endcase
              case (({(ctrl)*(5'b 00001)})+(0))
                0:
                  dout[0:0] <= din;
                1:
                  dout[1:1] <= din;
                2:
                  dout[2:2] <= din;
                3:
                  dout[3:3] <= din;
                4:
                  dout[4:4] <= din;
                5:
                  dout[5:5] <= din;
                6:
                  dout[6:6] <= din;
                7:
                  dout[7:7] <= din;
                8:
                  dout[8:8] <= din;
                9:
                  dout[9:9] <= din;
                10:
                  dout[10:10] <= din;
                11:
                  dout[11:11] <= din;
                12:
                  dout[12:12] <= din;
                13:
                  dout[13:13] <= din;
                14:
                  dout[14:14] <= din;
                15:
                  dout[15:15] <= din;
              endcase
              case (({(ctrl)*(5'b 00010)})+(0))
                0:
                  dout[0:0] <= din;
                1:
                  dout[1:1] <= din;
                2:
                  dout[2:2] <= din;
                3:
                  dout[3:3] <= din;
                4:
                  dout[4:4] <= din;
                5:
                  dout[5:5] <= din;
                6:
                  dout[6:6] <= din;
                7:
                  dout[7:7] <= din;
                8:
                  dout[8:8] <= din;
                9:
                  dout[9:9] <= din;
                10:
                  dout[10:10] <= din;
                11:
                  dout[11:11] <= din;
                12:
                  dout[12:12] <= din;
                13:
                  dout[13:13] <= din;
                14:
                  dout[14:14] <= din;
                15:
                  dout[15:15] <= din;
              endcase
              case (({(ctrl)*(5'b 00011)})+(0))
                0:
                  dout[0:0] <= din;
                1:
                  dout[1:1] <= din;
                2:
                  dout[2:2] <= din;
                3:
                  dout[3:3] <= din;
                4:
                  dout[4:4] <= din;
                5:
                  dout[5:5] <= din;
                6:
                  dout[6:6] <= din;
                7:
                  dout[7:7] <= din;
                8:
                  dout[8:8] <= din;
                9:
                  dout[9:9] <= din;
                10:
                  dout[10:10] <= din;
                11:
                  dout[11:11] <= din;
                12:
                  dout[12:12] <= din;
                13:
                  dout[13:13] <= din;
                14:
                  dout[14:14] <= din;
                15:
                  dout[15:15] <= din;
              endcase
              case (({(ctrl)*(5'b 00100)})+(0))
                0:
                  dout[0:0] <= din;
                1:
                  dout[1:1] <= din;
                2:
                  dout[2:2] <= din;
                3:
                  dout[3:3] <= din;
                4:
                  dout[4:4] <= din;
                5:
                  dout[5:5] <= din;
                6:
                  dout[6:6] <= din;
                7:
                  dout[7:7] <= din;
                8:
                  dout[8:8] <= din;
                9:
                  dout[9:9] <= din;
                10:
                  dout[10:10] <= din;
                11:
                  dout[11:11] <= din;
                12:
                  dout[12:12] <= din;
                13:
                  dout[13:13] <= din;
                14:
                  dout[14:14] <= din;
                15:
                  dout[15:15] <= din;
              endcase
              case (({(ctrl)*(5'b 00101)})+(0))
                0:
                  dout[0:0] <= din;
                1:
                  dout[1:1] <= din;
                2:
                  dout[2:2] <= din;
                3:
                  dout[3:3] <= din;
                4:
                  dout[4:4] <= din;
                5:
                  dout[5:5] <= din;
                6:
                  dout[6:6] <= din;
                7:
                  dout[7:7] <= din;
                8:
                  dout[8:8] <= din;
                9:
                  dout[9:9] <= din;
                10:
                  dout[10:10] <= din;
                11:
                  dout[11:11] <= din;
                12:
                  dout[12:12] <= din;
                13:
                  dout[13:13] <= din;
                14:
                  dout[14:14] <= din;
                15:
                  dout[15:15] <= din;
              endcase
              case (({(ctrl)*(5'b 00110)})+(0))
                0:
                  dout[0:0] <= din;
                1:
                  dout[1:1] <= din;
                2:
                  dout[2:2] <= din;
                3:
                  dout[3:3] <= din;
                4:
                  dout[4:4] <= din;
                5:
                  dout[5:5] <= din;
                6:
                  dout[6:6] <= din;
                7:
                  dout[7:7] <= din;
                8:
                  dout[8:8] <= din;
                9:
                  dout[9:9] <= din;
                10:
                  dout[10:10] <= din;
                11:
                  dout[11:11] <= din;
                12:
                  dout[12:12] <= din;
                13:
                  dout[13:13] <= din;
                14:
                  dout[14:14] <= din;
                15:
                  dout[15:15] <= din;
              endcase
              case (({(ctrl)*(5'b 00111)})+(0))
                0:
                  dout[0:0] <= din;
                1:
                  dout[1:1] <= din;
                2:
                  dout[2:2] <= din;
                3:
                  dout[3:3] <= din;
                4:
                  dout[4:4] <= din;
                5:
                  dout[5:5] <= din;
                6:
                  dout[6:6] <= din;
                7:
                  dout[7:7] <= din;
                8:
                  dout[8:8] <= din;
                9:
                  dout[9:9] <= din;
                10:
                  dout[10:10] <= din;
                11:
                  dout[11:11] <= din;
                12:
                  dout[12:12] <= din;
                13:
                  dout[13:13] <= din;
                14:
                  dout[14:14] <= din;
                15:
                  dout[15:15] <= din;
              endcase
              case (({(ctrl)*(5'b 01000)})+(0))
                0:
                  dout[0:0] <= din;
                1:
                  dout[1:1] <= din;
                2:
                  dout[2:2] <= din;
                3:
                  dout[3:3] <= din;
                4:
                  dout[4:4] <= din;
                5:
                  dout[5:5] <= din;
                6:
                  dout[6:6] <= din;
                7:
                  dout[7:7] <= din;
                8:
                  dout[8:8] <= din;
                9:
                  dout[9:9] <= din;
                10:
                  dout[10:10] <= din;
                11:
                  dout[11:11] <= din;
                12:
                  dout[12:12] <= din;
                13:
                  dout[13:13] <= din;
                14:
                  dout[14:14] <= din;
                15:
                  dout[15:15] <= din;
              endcase
              case (({(ctrl)*(5'b 01001)})+(0))
                0:
                  dout[0:0] <= din;
                1:
                  dout[1:1] <= din;
                2:
                  dout[2:2] <= din;
                3:
                  dout[3:3] <= din;
                4:
                  dout[4:4] <= din;
                5:
                  dout[5:5] <= din;
                6:
                  dout[6:6] <= din;
                7:
                  dout[7:7] <= din;
                8:
                  dout[8:8] <= din;
                9:
                  dout[9:9] <= din;
                10:
                  dout[10:10] <= din;
                11:
                  dout[11:11] <= din;
                12:
                  dout[12:12] <= din;
                13:
                  dout[13:13] <= din;
                14:
                  dout[14:14] <= din;
                15:
                  dout[15:15] <= din;
              endcase
              case (({(ctrl)*(5'b 01010)})+(0))
                0:
                  dout[0:0] <= din;
                1:
                  dout[1:1] <= din;
                2:
                  dout[2:2] <= din;
                3:
                  dout[3:3] <= din;
                4:
                  dout[4:4] <= din;
                5:
                  dout[5:5] <= din;
                6:
                  dout[6:6] <= din;
                7:
                  dout[7:7] <= din;
                8:
                  dout[8:8] <= din;
                9:
                  dout[9:9] <= din;
                10:
                  dout[10:10] <= din;
                11:
                  dout[11:11] <= din;
                12:
                  dout[12:12] <= din;
                13:
                  dout[13:13] <= din;
                14:
                  dout[14:14] <= din;
                15:
                  dout[15:15] <= din;
              endcase
              case (({(ctrl)*(5'b 01011)})+(0))
                0:
                  dout[0:0] <= din;
                1:
                  dout[1:1] <= din;
                2:
                  dout[2:2] <= din;
                3:
                  dout[3:3] <= din;
                4:
                  dout[4:4] <= din;
                5:
                  dout[5:5] <= din;
                6:
                  dout[6:6] <= din;
                7:
                  dout[7:7] <= din;
                8:
                  dout[8:8] <= din;
                9:
                  dout[9:9] <= din;
                10:
                  dout[10:10] <= din;
                11:
                  dout[11:11] <= din;
                12:
                  dout[12:12] <= din;
                13:
                  dout[13:13] <= din;
                14:
                  dout[14:14] <= din;
                15:
                  dout[15:15] <= din;
              endcase
              case (({(ctrl)*(5'b 01100)})+(0))
                0:
                  dout[0:0] <= din;
                1:
                  dout[1:1] <= din;
                2:
                  dout[2:2] <= din;
                3:
                  dout[3:3] <= din;
                4:
                  dout[4:4] <= din;
                5:
                  dout[5:5] <= din;
                6:
                  dout[6:6] <= din;
                7:
                  dout[7:7] <= din;
                8:
                  dout[8:8] <= din;
                9:
                  dout[9:9] <= din;
                10:
                  dout[10:10] <= din;
                11:
                  dout[11:11] <= din;
                12:
                  dout[12:12] <= din;
                13:
                  dout[13:13] <= din;
                14:
                  dout[14:14] <= din;
                15:
                  dout[15:15] <= din;
              endcase
              case (({(ctrl)*(5'b 01101)})+(0))
                0:
                  dout[0:0] <= din;
                1:
                  dout[1:1] <= din;
                2:
                  dout[2:2] <= din;
                3:
                  dout[3:3] <= din;
                4:
                  dout[4:4] <= din;
                5:
                  dout[5:5] <= din;
                6:
                  dout[6:6] <= din;
                7:
                  dout[7:7] <= din;
                8:
                  dout[8:8] <= din;
                9:
                  dout[9:9] <= din;
                10:
                  dout[10:10] <= din;
                11:
                  dout[11:11] <= din;
                12:
                  dout[12:12] <= din;
                13:
                  dout[13:13] <= din;
                14:
                  dout[14:14] <= din;
                15:
                  dout[15:15] <= din;
              endcase
              case (({(ctrl)*(5'b 01110)})+(0))
                0:
                  dout[0:0] <= din;
                1:
                  dout[1:1] <= din;
                2:
                  dout[2:2] <= din;
                3:
                  dout[3:3] <= din;
                4:
                  dout[4:4] <= din;
                5:
                  dout[5:5] <= din;
                6:
                  dout[6:6] <= din;
                7:
                  dout[7:7] <= din;
                8:
                  dout[8:8] <= din;
                9:
                  dout[9:9] <= din;
                10:
                  dout[10:10] <= din;
                11:
                  dout[11:11] <= din;
                12:
                  dout[12:12] <= din;
                13:
                  dout[13:13] <= din;
                14:
                  dout[14:14] <= din;
                15:
                  dout[15:15] <= din;
              endcase
              case (({(ctrl)*(5'b 01111)})+(0))
                0:
                  dout[0:0] <= din;
                1:
                  dout[1:1] <= din;
                2:
                  dout[2:2] <= din;
                3:
                  dout[3:3] <= din;
                4:
                  dout[4:4] <= din;
                5:
                  dout[5:5] <= din;
                6:
                  dout[6:6] <= din;
                7:
                  dout[7:7] <= din;
                8:
                  dout[8:8] <= din;
                9:
                  dout[9:9] <= din;
                10:
                  dout[10:10] <= din;
                11:
                  dout[11:11] <= din;
                12:
                  dout[12:12] <= din;
                13:
                  dout[13:13] <= din;
                14:
                  dout[14:14] <= din;
                15:
                  dout[15:15] <= din;
              endcase
              sel = 5'b 10000;
            end
        endcase
    endmodule
module forloop_select_gate (clk, ctrl, din, en, dout);

      input wire clk;
      input wire [3:0] ctrl;
      input wire [15:0] din;
      input wire en;
      output reg [15:0] dout;
      reg [4:0] sel;
      always @(posedge clk)
        case (|(en))
          1'b 1:
            begin
              case (({(ctrl)*(0)})+(0))
                0:
                  dout[0:0] <= din;
                1:
                  dout[1:1] <= din;
                2:
                  dout[2:2] <= din;
                3:
                  dout[3:3] <= din;
                4:
                  dout[4:4] <= din;
                5:
                  dout[5:5] <= din;
                6:
                  dout[6:6] <= din;
                7:
                  dout[7:7] <= din;
                8:
                  dout[8:8] <= din;
                9:
                  dout[9:9] <= din;
                10:
                  dout[10:10] <= din;
                11:
                  dout[11:11] <= din;
                12:
                  dout[12:12] <= din;
                13:
                  dout[13:13] <= din;
                14:
                  dout[14:14] <= din;
                15:
                  dout[15:15] <= din;
              endcase
              case (({(ctrl)*(5'b 00001)})+(0))
                0:
                  dout[0:0] <= din;
                1:
                  dout[1:1] <= din;
                2:
                  dout[2:2] <= din;
                3:
                  dout[3:3] <= din;
                4:
                  dout[4:4] <= din;
                5:
                  dout[5:5] <= din;
                6:
                  dout[6:6] <= din;
                7:
                  dout[7:7] <= din;
                8:
                  dout[8:8] <= din;
                9:
                  dout[9:9] <= din;
                10:
                  dout[10:10] <= din;
                11:
                  dout[11:11] <= din;
                12:
                  dout[12:12] <= din;
                13:
                  dout[13:13] <= din;
                14:
                  dout[14:14] <= din;
                15:
                  dout[15:15] <= din;
              endcase
              case (({(ctrl)*(5'b 00010)})+(0))
                0:
                  dout[0:0] <= din;
                1:
                  dout[1:1] <= din;
                2:
                  dout[2:2] <= din;
                3:
                  dout[3:3] <= din;
                4:
                  dout[4:4] <= din;
                5:
                  dout[5:5] <= din;
                6:
                  dout[6:6] <= din;
                7:
                  dout[7:7] <= din;
                8:
                  dout[8:8] <= din;
                9:
                  dout[9:9] <= din;
                10:
                  dout[10:10] <= din;
                11:
                  dout[11:11] <= din;
                12:
                  dout[12:12] <= din;
                13:
                  dout[13:13] <= din;
                14:
                  dout[14:14] <= din;
                15:
                  dout[15:15] <= din;
              endcase
              case (({(ctrl)*(5'b 00011)})+(0))
                0:
                  dout[0:0] <= din;
                1:
                  dout[1:1] <= din;
                2:
                  dout[2:2] <= din;
                3:
                  dout[3:3] <= din;
                4:
                  dout[4:4] <= din;
                5:
                  dout[5:5] <= din;
                6:
                  dout[6:6] <= din;
                7:
                  dout[7:7] <= din;
                8:
                  dout[8:8] <= din;
                9:
                  dout[9:9] <= din;
                10:
                  dout[10:10] <= din;
                11:
                  dout[11:11] <= din;
                12:
                  dout[12:12] <= din;
                13:
                  dout[13:13] <= din;
                14:
                  dout[14:14] <= din;
                15:
                  dout[15:15] <= din;
              endcase
              case (({(ctrl)*(5'b 00100)})+(0))
                0:
                  dout[0:0] <= din;
                1:
                  dout[1:1] <= din;
                2:
                  dout[2:2] <= din;
                3:
                  dout[3:3] <= din;
                4:
                  dout[4:4] <= din;
                5:
                  dout[5:5] <= din;
                6:
                  dout[6:6] <= din;
                7:
                  dout[7:7] <= din;
                8:
                  dout[8:8] <= din;
                9:
                  dout[9:9] <= din;
                10:
                  dout[10:10] <= din;
                11:
                  dout[11:11] <= din;
                12:
                  dout[12:12] <= din;
                13:
                  dout[13:13] <= din;
                14:
                  dout[14:14] <= din;
                15:
                  dout[15:15] <= din;
              endcase
              case (({(ctrl)*(5'b 00101)})+(0))
                0:
                  dout[0:0] <= din;
                1:
                  dout[1:1] <= din;
                2:
                  dout[2:2] <= din;
                3:
                  dout[3:3] <= din;
                4:
                  dout[4:4] <= din;
                5:
                  dout[5:5] <= din;
                6:
                  dout[6:6] <= din;
                7:
                  dout[7:7] <= din;
                8:
                  dout[8:8] <= din;
                9:
                  dout[9:9] <= din;
                10:
                  dout[10:10] <= din;
                11:
                  dout[11:11] <= din;
                12:
                  dout[12:12] <= din;
                13:
                  dout[13:13] <= din;
                14:
                  dout[14:14] <= din;
                15:
                  dout[15:15] <= din;
              endcase
              case (({(ctrl)*(5'b 00110)})+(0))
                0:
                  dout[0:0] <= din;
                1:
                  dout[1:1] <= din;
                2:
                  dout[2:2] <= din;
                3:
                  dout[3:3] <= din;
                4:
                  dout[4:4] <= din;
                5:
                  dout[5:5] <= din;
                6:
                  dout[6:6] <= din;
                7:
                  dout[7:7] <= din;
                8:
                  dout[8:8] <= din;
                9:
                  dout[9:9] <= din;
                10:
                  dout[10:10] <= din;
                11:
                  dout[11:11] <= din;
                12:
                  dout[12:12] <= din;
                13:
                  dout[13:13] <= din;
                14:
                  dout[14:14] <= din;
                15:
                  dout[15:15] <= din;
              endcase
              case (({(ctrl)*(5'b 00111)})+(0))
                0:
                  dout[0:0] <= din;
                1:
                  dout[1:1] <= din;
                2:
                  dout[2:2] <= din;
                3:
                  dout[3:3] <= din;
                4:
                  dout[4:4] <= din;
                5:
                  dout[5:5] <= din;
                6:
                  dout[6:6] <= din;
                7:
                  dout[7:7] <= din;
                8:
                  dout[8:8] <= din;
                9:
                  dout[9:9] <= din;
                10:
                  dout[10:10] <= din;
                11:
                  dout[11:11] <= din;
                12:
                  dout[12:12] <= din;
                13:
                  dout[13:13] <= din;
                14:
                  dout[14:14] <= din;
                15:
                  dout[15:15] <= din;
              endcase
              case (({(ctrl)*(5'b 01000)})+(0))
                0:
                  dout[0:0] <= din;
                1:
                  dout[1:1] <= din;
                2:
                  dout[2:2] <= din;
                3:
                  dout[3:3] <= din;
                4:
                  dout[4:4] <= din;
                5:
                  dout[5:5] <= din;
                6:
                  dout[6:6] <= din;
                7:
                  dout[7:7] <= din;
                8:
                  dout[8:8] <= din;
                9:
                  dout[9:9] <= din;
                10:
                  dout[10:10] <= din;
                11:
                  dout[11:11] <= din;
                12:
                  dout[12:12] <= din;
                13:
                  dout[13:13] <= din;
                14:
                  dout[14:14] <= din;
                15:
                  dout[15:15] <= din;
              endcase
              case (({(ctrl)*(5'b 01001)})+(0))
                0:
                  dout[0:0] <= din;
                1:
                  dout[1:1] <= din;
                2:
                  dout[2:2] <= din;
                3:
                  dout[3:3] <= din;
                4:
                  dout[4:4] <= din;
                5:
                  dout[5:5] <= din;
                6:
                  dout[6:6] <= din;
                7:
                  dout[7:7] <= din;
                8:
                  dout[8:8] <= din;
                9:
                  dout[9:9] <= din;
                10:
                  dout[10:10] <= din;
                11:
                  dout[11:11] <= din;
                12:
                  dout[12:12] <= din;
                13:
                  dout[13:13] <= din;
                14:
                  dout[14:14] <= din;
                15:
                  dout[15:15] <= din;
              endcase
              case (({(ctrl)*(5'b 01010)})+(0))
                0:
                  dout[0:0] <= din;
                1:
                  dout[1:1] <= din;
                2:
                  dout[2:2] <= din;
                3:
                  dout[3:3] <= din;
                4:
                  dout[4:4] <= din;
                5:
                  dout[5:5] <= din;
                6:
                  dout[6:6] <= din;
                7:
                  dout[7:7] <= din;
                8:
                  dout[8:8] <= din;
                9:
                  dout[9:9] <= din;
                10:
                  dout[10:10] <= din;
                11:
                  dout[11:11] <= din;
                12:
                  dout[12:12] <= din;
                13:
                  dout[13:13] <= din;
                14:
                  dout[14:14] <= din;
                15:
                  dout[15:15] <= din;
              endcase
              case (({(ctrl)*(5'b 01011)})+(0))
                0:
                  dout[0:0] <= din;
                1:
                  dout[1:1] <= din;
                2:
                  dout[2:2] <= din;
                3:
                  dout[3:3] <= din;
                4:
                  dout[4:4] <= din;
                5:
                  dout[5:5] <= din;
                6:
                  dout[6:6] <= din;
                7:
                  dout[7:7] <= din;
                8:
                  dout[8:8] <= din;
                9:
                  dout[9:9] <= din;
                10:
                  dout[10:10] <= din;
                11:
                  dout[11:11] <= din;
                12:
                  dout[12:12] <= din;
                13:
                  dout[13:13] <= din;
                14:
                  dout[14:14] <= din;
                15:
                  dout[15:15] <= din;
              endcase
              case (({(ctrl)*(5'b 01100)})+(0))
                0:
                  dout[0:0] <= din;
                1:
                  dout[1:1] <= din;
                2:
                  dout[2:2] <= din;
                3:
                  dout[3:3] <= din;
                4:
                  dout[4:4] <= din;
                5:
                  dout[5:5] <= din;
                6:
                  dout[6:6] <= din;
                7:
                  dout[7:7] <= din;
                8:
                  dout[8:8] <= din;
                9:
                  dout[9:9] <= din;
                10:
                  dout[10:10] <= din;
                11:
                  dout[11:11] <= din;
                12:
                  dout[12:12] <= din;
                13:
                  dout[13:13] <= din;
                14:
                  dout[14:14] <= din;
                15:
                  dout[15:15] <= din;
              endcase
              case (({(ctrl)*(5'b 01101)})+(0))
                0:
                  dout[0:0] <= din;
                1:
                  dout[1:1] <= din;
                2:
                  dout[2:2] <= din;
                3:
                  dout[3:3] <= din;
                4:
                  dout[4:4] <= din;
                5:
                  dout[5:5] <= din;
                6:
                  dout[6:6] <= din;
                7:
                  dout[7:7] <= din;
                8:
                  dout[8:8] <= din;
                9:
                  dout[9:9] <= din;
                10:
                  dout[10:10] <= din;
                11:
                  dout[11:11] <= din;
                12:
                  dout[12:12] <= din;
                13:
                  dout[13:13] <= din;
                14:
                  dout[14:14] <= din;
                15:
                  dout[15:15] <= din;
              endcase
              case (({(ctrl)*(5'b 01110)})+(0))
                0:
                  dout[0:0] <= din;
                1:
                  dout[1:1] <= din;
                2:
                  dout[2:2] <= din;
                3:
                  dout[3:3] <= din;
                4:
                  dout[4:4] <= din;
                5:
                  dout[5:5] <= din;
                6:
                  dout[6:6] <= din;
                7:
                  dout[7:7] <= din;
                8:
                  dout[8:8] <= din;
                9:
                  dout[9:9] <= din;
                10:
                  dout[10:10] <= din;
                11:
                  dout[11:11] <= din;
                12:
                  dout[12:12] <= din;
                13:
                  dout[13:13] <= din;
                14:
                  dout[14:14] <= din;
                15:
                  dout[15:15] <= din;
              endcase
              case (({(ctrl)*(5'b 01111)})+(0))
                0:
                  dout[0:0] <= din;
                1:
                  dout[1:1] <= din;
                2:
                  dout[2:2] <= din;
                3:
                  dout[3:3] <= din;
                4:
                  dout[4:4] <= din;
                5:
                  dout[5:5] <= din;
                6:
                  dout[6:6] <= din;
                7:
                  dout[7:7] <= din;
                8:
                  dout[8:8] <= din;
                9:
                  dout[9:9] <= din;
                10:
                  dout[10:10] <= din;
                11:
                  dout[11:11] <= din;
                12:
                  dout[12:12] <= din;
                13:
                  dout[13:13] <= din;
                14:
                  dout[14:14] <= din;
                15:
                  dout[15:15] <= din;
              endcase
              sel = 5'b 10000;
            end
        endcase
    endmodule