data/full_repos/permissive/472097485/Chu04/StopWatch_06/BoardTest.v
1: b"%Error: data/full_repos/permissive/472097485/Chu04/StopWatch_06/BoardTest.v:15: Cannot find file containing module: 'FrequencyDivider'\n FrequencyDivider #( 12000000, 24 ) secondClk ( clk, ~bt[0], bt[1], sec_tick );\n ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/472097485/Chu04/StopWatch_06,data/full_repos/permissive/472097485/FrequencyDivider\n             data/full_repos/permissive/472097485/Chu04/StopWatch_06,data/full_repos/permissive/472097485/FrequencyDivider.v\n             data/full_repos/permissive/472097485/Chu04/StopWatch_06,data/full_repos/permissive/472097485/FrequencyDivider.sv\n             FrequencyDivider\n             FrequencyDivider.v\n             FrequencyDivider.sv\n             obj_dir/FrequencyDivider\n             obj_dir/FrequencyDivider.v\n             obj_dir/FrequencyDivider.sv\n%Error: data/full_repos/permissive/472097485/Chu04/StopWatch_06/BoardTest.v:17: Cannot find file containing module: 'ModMCounterWithUDFD'\n ModMCounterWithUDFD #( 10, 4 ) seconds( clk, ~bt[0], sec_tick && bt[1], bt[2], hex0, sec10_tick );\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472097485/Chu04/StopWatch_06/BoardTest.v:19: Cannot find file containing module: 'ModMCounterWithUDFD'\n ModMCounterWithUDFD #( 6, 4 ) tenSeconds( clk, ~bt[0], sec10_tick && bt[1], bt[2], hex1, minute_tick );\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472097485/Chu04/StopWatch_06/BoardTest.v:21: Cannot find file containing module: 'ModMCounterWithUD'\n ModMCounterWithUD #( 6, 3 ) minutes( clk, ~bt[0], minute_tick && bt[1], bt[2], hex2 );\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472097485/Chu04/StopWatch_06/BoardTest.v:23: Cannot find file containing module: 'DispHexMux'\n DispHexMux disp( clk, ~bt[0], hex2, hex1, hex0, 3'b100, 3'b111, en, ss );\n ^~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module BoardTest( input wire clk, input wire [2:0] bt, output wire [7:0] ss, output wire [2:0] en );





	wire [3:0] hex2, hex1, hex0;
	wire sec_tick, sec10_tick, minute_tick;

	FrequencyDivider #( 12000000, 24 ) secondClk ( clk, ~bt[0], bt[1], sec_tick );

	ModMCounterWithUDFD #( 10, 4 ) seconds( clk, ~bt[0], sec_tick && bt[1], bt[2], hex0, sec10_tick );

	ModMCounterWithUDFD #( 6, 4 ) tenSeconds( clk, ~bt[0], sec10_tick && bt[1], bt[2], hex1, minute_tick );

	ModMCounterWithUD #( 6, 3 ) minutes( clk, ~bt[0], minute_tick && bt[1], bt[2], hex2 );

	DispHexMux disp( clk, ~bt[0], hex2, hex1, hex0, 3'b100, 3'b111, en, ss );

endmodule
module BoardTest( input wire clk, input wire [2:0] bt, output wire [7:0] ss, output wire [2:0] en );






	wire [3:0] hex2, hex1, hex0;
	wire sec_tick, sec10_tick, minute_tick;

	FrequencyDivider #( 12000000, 24 ) secondClk ( clk, ~bt[0], bt[1], sec_tick );

	ModMCounterWithUDFD #( 10, 4 ) seconds( clk, ~bt[0], sec_tick && bt[1], bt[2], hex0, sec10_tick );

	ModMCounterWithUDFD #( 6, 4 ) tenSeconds( clk, ~bt[0], sec10_tick && bt[1], bt[2], hex1, minute_tick );

	ModMCounterWithUD #( 6, 3 ) minutes( clk, ~bt[0], minute_tick && bt[1], bt[2], hex2 );

	DispHexMux disp( clk, ~bt[0], hex2, hex1, hex0, 3'b100, 3'b111, en, ss );

endmodule