data/full_repos/permissive/461141714/src/Pipelined CPU supporting DMA/DMA.v
1: b'%Error: Cannot find file containing module: CPU\n        ... Looked in:\n             data/full_repos/permissive/461141714/src/Pipelined/CPU\n             data/full_repos/permissive/461141714/src/Pipelined/CPU.v\n             data/full_repos/permissive/461141714/src/Pipelined/CPU.sv\n             CPU\n             CPU.v\n             CPU.sv\n             obj_dir/CPU\n             obj_dir/CPU.v\n             obj_dir/CPU.sv\n%Error: Cannot find file containing module: supporting\n%Error: Cannot find file containing module: DMA,data/full_repos/permissive/461141714\n%Error: Cannot find file containing module: data/full_repos/permissive/461141714/src/Pipelined\n%Error: Cannot find file containing module: DMA/DMA.v\n%Error: Exiting due to 5 error(s)\n'
module DMA (
    input CLK,
    input BG,
    input [4 * `WORD_SIZE - 1 : 0] edata,
    input [`WORD_SIZE-1:0] cmd,
    output reg BR,
    output reg WRITE,
    output reg [`WORD_SIZE - 1 : 0] addr, 
    output reg [4 * `WORD_SIZE - 1 : 0] data,
    output reg [1:0] offset,
    output reg interrupt
);


    

    wire clk = CLK;
    
    reg [1:0] state;
    reg [`WORD_SIZE-1:0] command_addr;
    reg [1:0] offset_count;
    reg [2:0] data_count;
    
    initial begin
        state = `WAIT_DMA_COMMAND;
        command_addr = `WORD_SIZE'bz;
        BR = 0;
        WRITE = 0;
        addr = `WORD_SIZE'bz;
        data = 4*`WORD_SIZE-1'bz;
        offset = 2'bz;
        interrupt = 0;
    end
    
    always @(*) begin
        if(BG) data = edata;
        offset = offset_count;
        addr = command_addr + offset_count * 4;
    end
    
    always @(posedge clk) begin
        if(state == `WAIT_DMA_COMMAND) begin
            interrupt = 0;
            if(cmd !== `WORD_SIZE'bz) begin
                command_addr = cmd;
                state = `WAIT_BUS_GRANT_START;
                BR = 1;
            end
        end
        else if(state == `WAIT_BUS_GRANT_START) begin
            if(BG == 1) begin
                state = `WRITE_MEMORY;
                offset_count = 0;
                data_count = 0;
            end
        end
        else if(state == `WRITE_MEMORY) begin
            if(offset_count == 3) begin
                offset_count = 2'bz;
                state = `WAIT_BUS_GRANT_END;
                BR = 0;
            end
            data_count = data_count + 1;
            if(data_count == 4) begin
                offset_count = offset_count + 1;
                data_count = 0;
            end
        end
        else if(state == `WAIT_BUS_GRANT_END) begin
            if(BG == 0) begin
                state = `WAIT_DMA_COMMAND;
                interrupt = 1;
            end
        end
    end

endmodule
module DMA (
    input CLK,
    input BG,
    input [4 * `WORD_SIZE - 1 : 0] edata,
    input [`WORD_SIZE-1:0] cmd,
    output reg BR,
    output reg WRITE,
    output reg [`WORD_SIZE - 1 : 0] addr, 
    output reg [4 * `WORD_SIZE - 1 : 0] data,
    output reg [1:0] offset,
    output reg interrupt
);



    

    wire clk = CLK;
    
    reg [1:0] state;
    reg [`WORD_SIZE-1:0] command_addr;
    reg [1:0] offset_count;
    reg [2:0] data_count;
    
    initial begin
        state = `WAIT_DMA_COMMAND;
        command_addr = `WORD_SIZE'bz;
        BR = 0;
        WRITE = 0;
        addr = `WORD_SIZE'bz;
        data = 4*`WORD_SIZE-1'bz;
        offset = 2'bz;
        interrupt = 0;
    end
    
    always @(*) begin
        if(BG) data = edata;
        offset = offset_count;
        addr = command_addr + offset_count * 4;
    end
    
    always @(posedge clk) begin
        if(state == `WAIT_DMA_COMMAND) begin
            interrupt = 0;
            if(cmd !== `WORD_SIZE'bz) begin
                command_addr = cmd;
                state = `WAIT_BUS_GRANT_START;
                BR = 1;
            end
        end
        else if(state == `WAIT_BUS_GRANT_START) begin
            if(BG == 1) begin
                state = `WRITE_MEMORY;
                offset_count = 0;
                data_count = 0;
            end
        end
        else if(state == `WRITE_MEMORY) begin
            if(offset_count == 3) begin
                offset_count = 2'bz;
                state = `WAIT_BUS_GRANT_END;
                BR = 0;
            end
            data_count = data_count + 1;
            if(data_count == 4) begin
                offset_count = offset_count + 1;
                data_count = 0;
            end
        end
        else if(state == `WAIT_BUS_GRANT_END) begin
            if(BG == 0) begin
                state = `WAIT_DMA_COMMAND;
                interrupt = 1;
            end
        end
    end

endmodule