data/full_repos/permissive/485129576/reg8.v
data/verilator_xmls/1e0fc161-6d72-4716-a25b-d2aa5e03cf12.xml
module REG8 (
    input clkR,
    input [7:0] D,
    output reg [7:0] Q
);
    initial begin
        Q = 8'b0;
    end

    always @(posedge clkR) begin
        Q = D;
    end

endmodule
module REG8 (
    input clkR,
    input [7:0] D,
    output reg [7:0] Q
);

    initial begin
        Q = 8'b0;
    end

    always @(posedge clkR) begin
        Q = D;
    end

endmodule