data/full_repos/permissive/463204869/units/async_fifo/source/rtl/verilog/async_fifo_out.v
1: b"%Error: data/full_repos/permissive/463204869/units/async_fifo/source/rtl/verilog/async_fifo_out.v:27: Cannot find file containing module: 'util_reset_sync'\n    util_reset_sync i_reset_sync_w2r (\n    ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/async_fifo/source/rtl/verilog,data/full_repos/permissive/463204869/util_reset_sync\n             data/full_repos/permissive/463204869/units/async_fifo/source/rtl/verilog,data/full_repos/permissive/463204869/util_reset_sync.v\n             data/full_repos/permissive/463204869/units/async_fifo/source/rtl/verilog,data/full_repos/permissive/463204869/util_reset_sync.sv\n             util_reset_sync\n             util_reset_sync.v\n             util_reset_sync.sv\n             obj_dir/util_reset_sync\n             obj_dir/util_reset_sync.v\n             obj_dir/util_reset_sync.sv\n%Error: data/full_repos/permissive/463204869/units/async_fifo/source/rtl/verilog/async_fifo_out.v:34: Cannot find file containing module: 'util_sync'\n    util_sync #(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/async_fifo/source/rtl/verilog/async_fifo_out.v:43: Cannot find file containing module: 'async_fifo_rptr_empty_ctrl'\n    async_fifo_rptr_empty_ctrl #(\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module async_fifo_out #(
    parameter DATA_WIDTH          = 16,
    parameter ADDR_WIDTH          = 3,
    parameter ALMOST_EMPTY_BUFFER = 2
)(
    input  wire                   aresetn_i,
    input  wire                   scan_mode_i,

    input  wire                   rclk_i,
    input  wire                   rd_en_i,
    output wire  [DATA_WIDTH-1:0] rdata_o,
    output wire    [ADDR_WIDTH:0] rd_ptr_o,
    output wire                   ralmost_empty_o,
    output wire                   rempty_o,

    input  wire    [ADDR_WIDTH:0] wr_ptr_i,
    input  wire  [DATA_WIDTH-1:0] rdata_i
);


    wire                rresetn;
    wire [ADDR_WIDTH:0] rsync_wr_ptr;

    assign rdata_o = rdata_i;

    util_reset_sync i_reset_sync_w2r (
        .clk_i          (rclk_i),
        .reset_q_i      (aresetn_i),
        .scan_mode_i    (scan_mode_i),
        .sync_reset_q_o (rresetn)
    );

    util_sync #(
        .WIDTH     (ADDR_WIDTH+1)
    ) i_sync_w2r (
        .clk_i     (rclk_i),
        .reset_n_i (rresetn),
        .data_i    (wr_ptr_i),
        .data_o    (rsync_wr_ptr)
    );

    async_fifo_rptr_empty_ctrl #(
        .ADDR_WIDTH          (ADDR_WIDTH),
        .ALMOST_EMPTY_BUFFER (ALMOST_EMPTY_BUFFER)
    ) i_rptr_empty_ctrl (
        .rclk_i              (rclk_i),
        .rresetn_i           (rresetn),
        .rd_en_i             (rd_en_i),
        .rsync_wr_ptr_i      (rsync_wr_ptr),
        .ralmost_empty_o     (ralmost_empty_o),
        .rempty_o            (rempty_o),
        .rd_ptr_o            (rd_ptr_o)
    );

endmodule
module async_fifo_out #(
    parameter DATA_WIDTH          = 16,
    parameter ADDR_WIDTH          = 3,
    parameter ALMOST_EMPTY_BUFFER = 2
)(
    input  wire                   aresetn_i,
    input  wire                   scan_mode_i,

    input  wire                   rclk_i,
    input  wire                   rd_en_i,
    output wire  [DATA_WIDTH-1:0] rdata_o,
    output wire    [ADDR_WIDTH:0] rd_ptr_o,
    output wire                   ralmost_empty_o,
    output wire                   rempty_o,

    input  wire    [ADDR_WIDTH:0] wr_ptr_i,
    input  wire  [DATA_WIDTH-1:0] rdata_i
);



    wire                rresetn;
    wire [ADDR_WIDTH:0] rsync_wr_ptr;

    assign rdata_o = rdata_i;

    util_reset_sync i_reset_sync_w2r (
        .clk_i          (rclk_i),
        .reset_q_i      (aresetn_i),
        .scan_mode_i    (scan_mode_i),
        .sync_reset_q_o (rresetn)
    );

    util_sync #(
        .WIDTH     (ADDR_WIDTH+1)
    ) i_sync_w2r (
        .clk_i     (rclk_i),
        .reset_n_i (rresetn),
        .data_i    (wr_ptr_i),
        .data_o    (rsync_wr_ptr)
    );

    async_fifo_rptr_empty_ctrl #(
        .ADDR_WIDTH          (ADDR_WIDTH),
        .ALMOST_EMPTY_BUFFER (ALMOST_EMPTY_BUFFER)
    ) i_rptr_empty_ctrl (
        .rclk_i              (rclk_i),
        .rresetn_i           (rresetn),
        .rd_en_i             (rd_en_i),
        .rsync_wr_ptr_i      (rsync_wr_ptr),
        .ralmost_empty_o     (ralmost_empty_o),
        .rempty_o            (rempty_o),
        .rd_ptr_o            (rd_ptr_o)
    );

endmodule