data/full_repos/permissive/488739248/rtl/ttl/ttl_74166_sync.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/488739248/rtl/ttl/ttl_74166_sync.v:56: Cell has missing pin: \'qb\'\n            SR_FlipFlop u0 (.s(not_norSER_SHLD[i]), .r(norSER_SHLD[i]), .Reset_n(Reset_n), .clk(CLK), .cen(CLKn),.rst(CLR), .q(SR_Q[i]));\n                        ^~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/488739248/rtl/ttl/ttl_74166_sync.v:46: Cannot find file containing module: \'srff\'\n    srff u_init (.s(not_norSER_SHLD[0]),.r(norSER_SHLD[0]),.clk(CLKn),.rst(CLR), .q(SR_Q[0]));\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/488739248/rtl/ttl,data/full_repos/permissive/488739248/srff\n             data/full_repos/permissive/488739248/rtl/ttl,data/full_repos/permissive/488739248/srff.v\n             data/full_repos/permissive/488739248/rtl/ttl,data/full_repos/permissive/488739248/srff.sv\n             srff\n             srff.v\n             srff.sv\n             obj_dir/srff\n             obj_dir/srff.v\n             obj_dir/srff.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module SR_FlipFlop(s,r,Reset_n,clk,cen,rst, q,qb);
    input wire s,r,Reset_n,clk,cen,rst;
    output wire q,qb;

    reg q_r;
    reg [1:0]sr;
    reg last_cen;

    always@(posedge clk) begin
        if(!Reset_n) begin
            q_r=1'b0;
            last_cen<= 1'b1;
        end
        else begin
            last_cen <= cen;
            sr={s,r};
            if(!rst) begin
                q_r<=1'b0;
            end 
            else begin
                if (cen && !last_cen) begin
                    case (sr)
                        2'd1:q_r<=1'b0;
                        2'd2:q_r<=1'b1;
                        2'd3:q_r<=1'b1;
                        default: q_r<=1'bx;
                    endcase
                end
            end
        end
    end

    assign q = q_r;
    assign qb = ~q_r;
endmodule
module SR_FlipFlop(s,r,Reset_n,clk,cen,rst, q,qb);

    input wire s,r,Reset_n,clk,cen,rst;
    output wire q,qb;

    reg q_r;
    reg [1:0]sr;
    reg last_cen;

    always@(posedge clk) begin
        if(!Reset_n) begin
            q_r=1'b0;
            last_cen<= 1'b1;
        end
        else begin
            last_cen <= cen;
            sr={s,r};
            if(!rst) begin
                q_r<=1'b0;
            end 
            else begin
                if (cen && !last_cen) begin
                    case (sr)
                        2'd1:q_r<=1'b0;
                        2'd2:q_r<=1'b1;
                        2'd3:q_r<=1'b1;
                        default: q_r<=1'bx;
                    endcase
                end
            end
        end
    end

    assign q = q_r;
    assign qb = ~q_r;
endmodule