data/full_repos/permissive/522546962/FPGA_code(motor_Trigg).v
1: b"%Error: data/full_repos/permissive/522546962/FPGA_code(motor_Trigg).v:32: syntax error, unexpected IDENTIFIER\nVISVESWARAYA TECHNOLOGICAL UNIVERSITY\n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/522546962/FPGA_code(motor_Trigg).v:37: syntax error, unexpected IDENTIFIER\nmotor a1(clk,hours,count);\n      ^~\n%Error: data/full_repos/permissive/522546962/FPGA_code(motor_Trigg).v:56: syntax error, unexpected $end, expecting ',' or ';'\nreg[3:0]register=4   b1001;\n                  ^\n%Error: Cannot continue\n"
module motor(clk,count,d_out);
input clk,count;
output[3:0]d_out;
reg[3:0]d_out;
reg[3:0]register=4’b1001;
integer n=8;
integer i=0;
always @posedge(clk)
begin
if(count==12)
begin
if(i<(n*12))
begin
register<={register[0],register[3:1]};
d_out=register;
i=i+1;
end

VISVESWARAYA TECHNOLOGICAL UNIVERSITY

Dept.of EC, VCET, Puttur Page 15
else
begin
if(i<n)
begin
register<={register[2:0],register[3]};
d_out=register;
i=i+1;
end end
assign d_out=register;
endmodule
module motor(clk,count,d_out);

input clk,count;
output[3:0]d_out;
reg[3:0]d_out;
reg[3:0]register=4’b1001;
integer n=8;
integer i=0;
always @posedge(clk)
begin
if(count==12)
begin
if(i<(n*12))
begin
register<={register[0],register[3:1]};
d_out=register;
i=i+1;
end

VISVESWARAYA TECHNOLOGICAL UNIVERSITY

Dept.of EC, VCET, Puttur Page 15
else
begin
if(i<n)
begin
register<={register[2:0],register[3]};
d_out=register;
i=i+1;
end end
assign d_out=register;
endmodule