data/full_repos/permissive/413582930/branch_unit.v
data/verilator_xmls/6b168bf9-1d74-40c8-a091-996b53c8d7c0.xml
module branch_unit(
    funct3,
    val1,
    val2,
    take_branch
);
    input wire [2:0]  funct3;
    input wire [31:0] val1, val2;
    output reg take_branch;

    wire signed [31:0] s_val1 = $signed(val1);
    wire signed [31:0] s_val2 = $signed(val2);

    always @(*)
        case (funct3)
            `BEQ:  take_branch <= val1 == val2;
            `BNE:  take_branch <= val1 != val2;
            `BLT:  take_branch <= s_val1 < s_val2;
            `BLTU: take_branch <= val1 < val2;
            `BGE:  take_branch <= s_val1 >= s_val2;
            `BGEU: take_branch <= val1 >= val2;
            default: take_branch <= 1'b0;
        endcase



endmodule
module branch_unit(
    funct3,
    val1,
    val2,
    take_branch
);

    input wire [2:0]  funct3;
    input wire [31:0] val1, val2;
    output reg take_branch;

    wire signed [31:0] s_val1 = $signed(val1);
    wire signed [31:0] s_val2 = $signed(val2);

    always @(*)
        case (funct3)
            `BEQ:  take_branch <= val1 == val2;
            `BNE:  take_branch <= val1 != val2;
            `BLT:  take_branch <= s_val1 < s_val2;
            `BLTU: take_branch <= val1 < val2;
            `BGE:  take_branch <= s_val1 >= s_val2;
            `BGEU: take_branch <= val1 >= val2;
            default: take_branch <= 1'b0;
        endcase



endmodule