data/full_repos/permissive/461000256/hdl/IF_ID.v
data/verilator_xmls/7d6c77d9-3dcb-4701-91b5-303b41b3b295.xml
module IF_ID (
	input wire 			clk,	
	input wire [`IW-1:0] in,	
	output reg [`IW-1:0] out
);

	always @(posedge clk) begin
		out <= #2 in;
	end

endmodule
module IF_ID (
	input wire 			clk,	
	input wire [`IW-1:0] in,	
	output reg [`IW-1:0] out
);


	always @(posedge clk) begin
		out <= #2 in;
	end

endmodule