data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_ddr_vref_rptr.v
data/verilator_xmls/333f3560-03bc-4971-b02b-e7cc27680a00.xml
module bw_io_ddr_vref_rptr(in,out,vdd18);
input vdd18;
input [7:0] in;
output [7:0] out;

assign out = in;
endmodule
module bw_io_ddr_vref_rptr(in,out,vdd18);

input vdd18;
input [7:0] in;
output [7:0] out;

assign out = in;
endmodule