data/full_repos/permissive/462122681/flipflop.v
data/verilator_xmls/615c98bd-9559-487e-a205-ebc4e16c8395.xml
module flipflop(
	input wire clk, 
	input wire d, 
	output reg q, 
	output reg q_
);
	
	initial begin
			q <= 0;
			q_ <= 1;
	end
	
	always@(clk) 
	begin
		q <= d;
		q_ <= ~d;
	end
endmodule
module flipflop(
	input wire clk, 
	input wire d, 
	output reg q, 
	output reg q_
);

	
	initial begin
			q <= 0;
			q_ <= 1;
	end
	
	always@(clk) 
	begin
		q <= d;
		q_ <= ~d;
	end
endmodule