data/full_repos/permissive/496903659/123 fsm3comb.v
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/496903659/123\n        ... Looked in:\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/123\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/123.v\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/123.sv\n             data/full_repos/permissive/496903659/123\n             data/full_repos/permissive/496903659/123.v\n             data/full_repos/permissive/496903659/123.sv\n             obj_dir/data/full_repos/permissive/496903659/123\n             obj_dir/data/full_repos/permissive/496903659/123.v\n             obj_dir/data/full_repos/permissive/496903659/123.sv\n%Error: Cannot find file containing module: fsm3comb.v\n%Error: Exiting due to 2 error(s)\n'
module top_module(
    input in,
    input [1:0] state,
    output reg [1:0] next_state,
    output out);

    parameter A=2'd0, B=2'd1, C=2'd2, D=2'd3;


    always @(*) begin
        if (in == 0) begin
            if (state == A)
                next_state <= A;
            else if (state == B)
                next_state <= C;
            else if (state == C)
                next_state <= A;
            else
                next_state <= C;
        end 
        else begin
            if (state == A)
                next_state <= B;
            else if (state == B)
                next_state <= B;
            else if (state == C)
                next_state <= D;
            else
                next_state <= B;
        end
    end
    

    assign out = (state == D);

endmodule
module top_module(
    input in,
    input [1:0] state,
    output reg [1:0] next_state,
    output out);


    parameter A=2'd0, B=2'd1, C=2'd2, D=2'd3;


    always @(*) begin
        if (in == 0) begin
            if (state == A)
                next_state <= A;
            else if (state == B)
                next_state <= C;
            else if (state == C)
                next_state <= A;
            else
                next_state <= C;
        end 
        else begin
            if (state == A)
                next_state <= B;
            else if (state == B)
                next_state <= B;
            else if (state == C)
                next_state <= D;
            else
                next_state <= B;
        end
    end
    

    assign out = (state == D);

endmodule