data/full_repos/permissive/455657973/shift_R.v
data/verilator_xmls/5bc34a67-c542-4db7-ae1f-07422a7f8fbc.xml
module shift_R(input [31:0]in, output [31:0]shifted);
assign shifted = in >> 32'b1;

endmodule
module shift_R(input [31:0]in, output [31:0]shifted);

assign shifted = in >> 32'b1;

endmodule