data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram/BPAD.v
1: b'%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram/BPAD.v:9: syntax error, unexpected int, expecting IDENTIFIER or \'=\' or do or final\nreg [WIDE-1:0]      int;\n                    ^~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram/BPAD.v:13: syntax error, unexpected <=, expecting "\'{"\n        int <= {WIDE{1\'bx}};\n            ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram/BPAD.v:14: syntax error, unexpected <=, expecting "\'{"\n     else int <= PAD;\n              ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/ram/BPAD.v:16: syntax error, unexpected \';\', expecting "\'{"\nassign  O = int;\n               ^\n%Error: Exiting due to 4 error(s)\n'
module BPAD (PAD, EN, I, O);
parameter   WIDE    = 1;

input [WIDE-1:0]    I;
input               EN;
output [WIDE-1:0]   O;
inout [WIDE-1:0]    PAD;

reg [WIDE-1:0]      int;
wire [WIDE-1:0] PAD = EN ? I : {WIDE{1'bz}};
always @ (PAD)
    if (PAD === {WIDE{1'bz}})
        int <= {WIDE{1'bx}};
     else int <= PAD;

assign  O = int;
endmodule
module BPAD (PAD, EN, I, O);

parameter   WIDE    = 1;

input [WIDE-1:0]    I;
input               EN;
output [WIDE-1:0]   O;
inout [WIDE-1:0]    PAD;

reg [WIDE-1:0]      int;
wire [WIDE-1:0] PAD = EN ? I : {WIDE{1'bz}};
always @ (PAD)
    if (PAD === {WIDE{1'bz}})
        int <= {WIDE{1'bx}};
     else int <= PAD;

assign  O = int;
endmodule