data/full_repos/permissive/414867793/Logic_Circuits/Half_Substractor/H_SUBS.v
data/verilator_xmls/b21c3417-7bee-42e7-ac7e-5f9294eb2dad.xml
module H_SUBS(A,B,D,C);
input A,B;
output D,C;
assign D=A^B;
assign C=(~(A))&B;
endmodule
module H_SUBS(A,B,D,C);

input A,B;
output D,C;
assign D=A^B;
assign C=(~(A))&B;
endmodule