data/full_repos/permissive/482720319/alu.v
1: b'%Error: data/full_repos/permissive/482720319/alu.v:45: Unsupported or unknown PLI call: $monitor\n            $monitor("opcode : %b, A = %b(%d)B = %b(%d) :::: res = %b(%d) --- %b", opt, At, At, Bt, Bt, res, res, zero);\n            ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/482720319/alu.v:50: Unsupported: Ignoring delay on this delayed statement.\n            #10 $finish;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/482720319/alu.v:55: Unsupported: Ignoring delay on this delayed statement.\n            repeat(7) #1 opt = opt + 1;\n                      ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ALU(
      input [2:0] opcode,
      input signed [15:0] A,
      input signed [15:0] B,
      output reg [15:0] res,
      output zero
);
      

      always @(*) begin
            
            case(opcode)
                  3'b000 : res <= A + B;
                  3'b001 : res <= A - B;
                  3'b010 : res <= A << B;
                  3'b011 : res <= A >> B;
                  3'b100 : res <= (A >>> B) ;
                  3'b101 : res <= (A ~& B);
                  3'b110 : res <= (A | B);
                  default : res <= A + B;
            endcase
      end

      assign zero = &(A ~^ B);

endmodule
module ALU(
      input [2:0] opcode,
      input signed [15:0] A,
      input signed [15:0] B,
      output reg [15:0] res,
      output zero
);

      

      always @(*) begin
            
            case(opcode)
                  3'b000 : res <= A + B;
                  3'b001 : res <= A - B;
                  3'b010 : res <= A << B;
                  3'b011 : res <= A >> B;
                  3'b100 : res <= (A >>> B) ;
                  3'b101 : res <= (A ~& B);
                  3'b110 : res <= (A | B);
                  default : res <= A + B;
            endcase
      end

      assign zero = &(A ~^ B);

endmodule