data/full_repos/permissive/493019833/test/testcase/firrtl/TopOfVisualizer/reference/TopOfVisualizer.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/TopOfVisualizer/reference/TopOfVisualizer.v:219: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 16 bits.\n                                                                                                                         : ... In instance TopOfVisualizer.u_pad_6\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module TopOfVisualizer(
    input clock,
    input reset,
    input [31:0] io_in1,
    input [31:0] io_in2,
    input io_select,
    output [31:0] io_out,
    output [31:0] io_memOut
);
    wire [31:0] _x__q;
    wire [31:0] _x__d;
    DFF_POSCLK #(.width(32)) x (
        .q(_x__q),
        .d(_x__d),
        .clk(clock)
    );
    wire [31:0] _y__q;
    wire [31:0] _y__d;
    DFF_POSCLK #(.width(32)) y (
        .q(_y__q),
        .d(_y__d),
        .clk(clock)
    );
    wire myMem__T_12_clk;
    wire myMem__T_12_en;
    wire myMem__T_12_mask;
    wire [3:0] myMem__T_12_addr;
    wire [31:0] myMem__T_12_data;
    wire [31:0] myMem__T_16_data;
    wire myMem__T_16_clk;
    wire myMem__T_16_en;
    wire [3:0] myMem__T_16_addr;
    RAMMEM #(.depth(16), .addrbits(4), .width(32), .isSyncRead(0)) myMem (
        .read_data(myMem__T_16_data),
        .read_clk(myMem__T_16_clk),
        .read_en(myMem__T_16_en),
        .read_addr(myMem__T_16_addr),
        .write_clk(myMem__T_12_clk),
        .write_en(myMem__T_12_en),
        .write_mask(myMem__T_12_mask),
        .write_addr(myMem__T_12_addr),
        .write_data(myMem__T_12_data)
    );
    wire _modA__clock;
    wire _modA__reset;
    wire [31:0] _modA__io_in;
    wire [15:0] _modA__io_out;
    VizModA modA (
        .clock(_modA__clock),
        .reset(_modA__reset),
        .io_in(_modA__io_in),
        .io_out(_modA__io_out)
    );
    wire [3:0] _T_11;
    BITS #(.width(32), .high(3), .low(0)) bits_2 (
        .y(_T_11),
        .in(io_in1)
    );
    assign myMem__T_12_addr = _T_11;
    assign myMem__T_12_en = io_select;
    assign myMem__T_12_clk = clock;
    assign myMem__T_12_mask = 1'h1;
    wire _T_14;
    EQ_UNSIGNED #(.width(1)) u_eq_3 (
        .y(_T_14),
        .a(io_select),
        .b(1'h0)
    );
    wire [3:0] _T_15;
    BITS #(.width(32), .high(3), .low(0)) bits_4 (
        .y(_T_15),
        .in(io_in1)
    );
    assign myMem__T_16_addr = _T_15;
    assign myMem__T_16_en = _T_14;
    assign myMem__T_16_clk = clock;
    wire [31:0] _node_0;
    MUX_UNSIGNED #(.width(32)) u_mux_5 (
        .y(_node_0),
        .sel(io_select),
        .a(io_in1),
        .b(_x__q)
    );
    wire [32:0] _T_17;
    wire [31:0] _WTEMP_0;
    PAD_UNSIGNED #(.width(16), .n(32)) u_pad_6 (
        .y(_WTEMP_0),
        .in(_modA__io_out)
    );
    ADD_UNSIGNED #(.width(32)) u_add_7 (
        .y(_T_17),
        .a(_WTEMP_0),
        .b(io_in2)
    );
    wire [31:0] _T_18;
    TAIL #(.width(33), .n(1)) tail_8 (
        .y(_T_18),
        .in(_T_17)
    );
    assign io_memOut = myMem__T_16_data;
    assign io_out = _y__q;
    assign _modA__clock = clock;
    assign _modA__io_in = _x__q;
    assign _modA__reset = reset;
    assign myMem__T_12_data = io_in2;
    MUX_UNSIGNED #(.width(32)) u_mux_9 (
        .y(_x__d),
        .sel(_T_14),
        .a(io_in2),
        .b(_node_0)
    );
    assign _y__d = _T_18;
endmodule
module TopOfVisualizer(
    input clock,
    input reset,
    input [31:0] io_in1,
    input [31:0] io_in2,
    input io_select,
    output [31:0] io_out,
    output [31:0] io_memOut
);

    wire [31:0] _x__q;
    wire [31:0] _x__d;
    DFF_POSCLK #(.width(32)) x (
        .q(_x__q),
        .d(_x__d),
        .clk(clock)
    );
    wire [31:0] _y__q;
    wire [31:0] _y__d;
    DFF_POSCLK #(.width(32)) y (
        .q(_y__q),
        .d(_y__d),
        .clk(clock)
    );
    wire myMem__T_12_clk;
    wire myMem__T_12_en;
    wire myMem__T_12_mask;
    wire [3:0] myMem__T_12_addr;
    wire [31:0] myMem__T_12_data;
    wire [31:0] myMem__T_16_data;
    wire myMem__T_16_clk;
    wire myMem__T_16_en;
    wire [3:0] myMem__T_16_addr;
    RAMMEM #(.depth(16), .addrbits(4), .width(32), .isSyncRead(0)) myMem (
        .read_data(myMem__T_16_data),
        .read_clk(myMem__T_16_clk),
        .read_en(myMem__T_16_en),
        .read_addr(myMem__T_16_addr),
        .write_clk(myMem__T_12_clk),
        .write_en(myMem__T_12_en),
        .write_mask(myMem__T_12_mask),
        .write_addr(myMem__T_12_addr),
        .write_data(myMem__T_12_data)
    );
    wire _modA__clock;
    wire _modA__reset;
    wire [31:0] _modA__io_in;
    wire [15:0] _modA__io_out;
    VizModA modA (
        .clock(_modA__clock),
        .reset(_modA__reset),
        .io_in(_modA__io_in),
        .io_out(_modA__io_out)
    );
    wire [3:0] _T_11;
    BITS #(.width(32), .high(3), .low(0)) bits_2 (
        .y(_T_11),
        .in(io_in1)
    );
    assign myMem__T_12_addr = _T_11;
    assign myMem__T_12_en = io_select;
    assign myMem__T_12_clk = clock;
    assign myMem__T_12_mask = 1'h1;
    wire _T_14;
    EQ_UNSIGNED #(.width(1)) u_eq_3 (
        .y(_T_14),
        .a(io_select),
        .b(1'h0)
    );
    wire [3:0] _T_15;
    BITS #(.width(32), .high(3), .low(0)) bits_4 (
        .y(_T_15),
        .in(io_in1)
    );
    assign myMem__T_16_addr = _T_15;
    assign myMem__T_16_en = _T_14;
    assign myMem__T_16_clk = clock;
    wire [31:0] _node_0;
    MUX_UNSIGNED #(.width(32)) u_mux_5 (
        .y(_node_0),
        .sel(io_select),
        .a(io_in1),
        .b(_x__q)
    );
    wire [32:0] _T_17;
    wire [31:0] _WTEMP_0;
    PAD_UNSIGNED #(.width(16), .n(32)) u_pad_6 (
        .y(_WTEMP_0),
        .in(_modA__io_out)
    );
    ADD_UNSIGNED #(.width(32)) u_add_7 (
        .y(_T_17),
        .a(_WTEMP_0),
        .b(io_in2)
    );
    wire [31:0] _T_18;
    TAIL #(.width(33), .n(1)) tail_8 (
        .y(_T_18),
        .in(_T_17)
    );
    assign io_memOut = myMem__T_16_data;
    assign io_out = _y__q;
    assign _modA__clock = clock;
    assign _modA__io_in = _x__q;
    assign _modA__reset = reset;
    assign myMem__T_12_data = io_in2;
    MUX_UNSIGNED #(.width(32)) u_mux_9 (
        .y(_x__d),
        .sel(_T_14),
        .a(io_in2),
        .b(_node_0)
    );
    assign _y__d = _T_18;
endmodule