data/full_repos/permissive/43858668/final_verilog/src/clib/c_interleave.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/43858668/final_verilog/src/clib/c_interleave.v:46: Little bit endian vector: MSB < LSB of bit range: 0:7\n   input [0:width-1] data_in;\n         ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/43858668/final_verilog/src/clib/c_interleave.v:49: Little bit endian vector: MSB < LSB of bit range: 0:7\n   output [0:width-1] data_out;\n          ^\n%Error: Exiting due to 2 warning(s)\n'
module c_interleave
  (data_in, data_out);
   

   parameter width = 8;
   

   parameter num_blocks = 2;
   

   localparam step = width / num_blocks;
   

   input [0:width-1] data_in;
   

   output [0:width-1] data_out;
   wire [0:width-1] data_out;
   
   generate
      
      genvar 	    i;
      for(i = 0; i < step; i = i + 1)
	begin:blocks
	   
	   genvar j;
	   for(j = 0; j < num_blocks; j = j + 1)
	     begin:bits
		assign data_out[i*num_blocks+j] = data_in[i+j*step];
	     end
	   
	end
      
   endgenerate
   
endmodule
module c_interleave
  (data_in, data_out);

   

   parameter width = 8;
   

   parameter num_blocks = 2;
   

   localparam step = width / num_blocks;
   

   input [0:width-1] data_in;
   

   output [0:width-1] data_out;
   wire [0:width-1] data_out;
   
   generate
      
      genvar 	    i;
      for(i = 0; i < step; i = i + 1)
	begin:blocks
	   
	   genvar j;
	   for(j = 0; j < num_blocks; j = j + 1)
	     begin:bits
		assign data_out[i*num_blocks+j] = data_in[i+j*step];
	     end
	   
	end
      
   endgenerate
   
endmodule