data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v
1: b'%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new,data/full_repos/permissive/433174928/defines.vh\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new,data/full_repos/permissive/433174928/defines.vh.v\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new,data/full_repos/permissive/433174928/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:22: Define or directive not defined: \'`ADD\'\n        operation <= `ADD;\n                     ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:22: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        operation <= `ADD;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:26: Define or directive not defined: \'`SUB\'\n        operation <= `SUB;\n                     ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:26: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        operation <= `SUB;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:30: Define or directive not defined: \'`SLL\'\n        operation <= `SLL;\n                     ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:30: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        operation <= `SLL;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:34: Define or directive not defined: \'`SLT\'\n        operation <= `SLT;\n                     ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:34: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        operation <= `SLT;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:38: Define or directive not defined: \'`SLTU\'\n        operation <= `SLTU;\n                     ^~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:38: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        operation <= `SLTU;\n                          ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:42: Define or directive not defined: \'`XOR\'\n        operation <= `XOR;\n                     ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:42: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        operation <= `XOR;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:46: Define or directive not defined: \'`SRL\'\n        operation <= `SRL;\n                     ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:46: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        operation <= `SRL;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:54: Define or directive not defined: \'`SRA\'\n        operation <= `SRA;\n                     ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:54: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        operation <= `SRA;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:58: Define or directive not defined: \'`OR\'\n        operation <= `OR;\n                     ^~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:58: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        operation <= `OR;\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:62: Define or directive not defined: \'`AND\'\n        operation <= `AND;\n                     ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:62: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        operation <= `AND;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:65: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:68: Define or directive not defined: \'`ADD\'\n        operation <= `ADD;\n                     ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:68: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        operation <= `ADD;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:69: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:71: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:72: Define or directive not defined: \'`SUB\'\n        operation <= `SUB;\n                     ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:72: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        operation <= `SUB;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:73: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:75: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:76: Define or directive not defined: \'`SLL\'\n        operation <= `SLL;\n                     ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:76: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        operation <= `SLL;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:77: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:79: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:80: Define or directive not defined: \'`SLT\'\n        operation <= `SLT;\n                     ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:80: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        operation <= `SLT;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:81: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:83: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:84: Define or directive not defined: \'`SLTU\'\n        operation <= `SLTU;\n                     ^~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:84: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        operation <= `SLTU;\n                          ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:85: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:88: Define or directive not defined: \'`XOR\'\n        operation <= `XOR;\n                     ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:88: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        operation <= `XOR;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:89: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:91: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:92: Define or directive not defined: \'`SRL\'\n        operation <= `SRL;\n                     ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:92: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        operation <= `SRL;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:93: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:95: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:97: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:99: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:100: Define or directive not defined: \'`SRA\'\n        operation <= `SRA;\n                     ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:100: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        operation <= `SRA;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:101: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:103: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:104: Define or directive not defined: \'`OR\'\n        operation <= `OR;\n                     ^~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:104: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        operation <= `OR;\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:105: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:107: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:108: Define or directive not defined: \'`AND\'\n        operation <= `AND;\n                     ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:108: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        operation <= `AND;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:109: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sim_1/new/ALU_TB.v:111: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: Exiting due to 41 error(s), 45 warning(s)\n'
module ALU_TB(

    );
    
    reg [31:0] operand1;
    reg [31:0] operand2;
    reg [3:0] operation;
    wire [31:0] ALUresult;
    
    ALU dut(
        .operand1(operand1), .operand2(operand2), .operation(operation), .ALUresult(ALUresult)
    );
    
   initial begin
        #5;
        operand1 <= 32'd10; 
        operand2 <= 32'd12;       
        operation <= `ADD;
        #5;
        if (ALUresult != 32'h00000016) $fatal("The expected output was not received");
        #5;
        operation <= `SUB;
        #5;
        if (ALUresult != 32'hfffffffe) $fatal("The expected output was not received");
        #5;
        operation <= `SLL;
        #5;
        if (ALUresult != 32'h0000a000) $fatal("The expected output was not received");
        #5;
        operation <= `SLT;
        #5;
        if (ALUresult != 32'h00000001) $fatal("The expected output was not received");
        #5;
        operation <= `SLTU;
        #5;
        if (ALUresult != 32'h00000001) $fatal("The expected output was not received");
        #5;
        operation <= `XOR;
        #5;
        if (ALUresult != 32'h00000006) $fatal("The expected output was not received");
        #5;
        operation <= `SRL;
        #5;
        if (ALUresult != 32'h00000000) $fatal("The expected output was not received");
        #5;
        operation <= 4'd11;
        #5;
        if (ALUresult != 32'h00000000) $fatal("The expected output was not received");
        #5;
        operation <= `SRA;
        #5;
        if (ALUresult != 32'h00000000) $fatal("The expected output was not received");
        #5;
        operation <= `OR;
        #5;
        if (ALUresult != 32'h0000000e) $fatal("The expected output was not received");
        #5;
        operation <= `AND;
        #5;
        if (ALUresult != 32'h00000008) $fatal("The expected output was not received");
        #5;
        operand1 <= 32'b10011011100110101100101011110011;
        operand2 <= 32'b00101110010101101001111001010110;
        operation <= `ADD;
        #5;
        if (ALUresult != 32'hc9f16949) $fatal("The expected output was not received");
        #5;
        operation <= `SUB;
        #5;
        if (ALUresult != 32'h6d442c9d) $fatal("The expected output was not received");
        #5;
        operation <= `SLL;
        #5;
        if (ALUresult != 32'hbcc00000) $fatal("The expected output was not received");
        #5;
        operation <= `SLT;
        #5;
        if (ALUresult != 32'h00000001) $fatal("The expected output was not received");
        #5;
        operation <= `SLTU;
        #5;
        if (ALUresult != 32'h00000000) $fatal("The expected output was not received");
        #5;
        operation <= `XOR;
        #5;
        if (ALUresult != 32'hb5cc54a5) $fatal("The expected output was not received");
        #5;
        operation <= `SRL;
        #5;
        if (ALUresult != 32'h0000026e) $fatal("The expected output was not received");
        #5;
        operation <= 4'd11;
        #5;
        if (ALUresult != 32'h0000026e) $fatal("The expected output was not received");
        #5;
        operation <= `SRA;
        #5;
        if (ALUresult != 32'hfffffe6e) $fatal("The expected output was not received");
        #5;
        operation <= `OR;
        #5;
        if (ALUresult != 32'hbfdedef7) $fatal("The expected output was not received");
        #5;
        operation <= `AND;
        #5;
        if (ALUresult != 32'h0a128a52) $fatal("The expected output was not received");
        #10;
        $display ("All test cases passed");
        $finish;
   end 
    
endmodule
module ALU_TB(

    );

    
    reg [31:0] operand1;
    reg [31:0] operand2;
    reg [3:0] operation;
    wire [31:0] ALUresult;
    
    ALU dut(
        .operand1(operand1), .operand2(operand2), .operation(operation), .ALUresult(ALUresult)
    );
    
   initial begin
        #5;
        operand1 <= 32'd10; 
        operand2 <= 32'd12;       
        operation <= `ADD;
        #5;
        if (ALUresult != 32'h00000016) $fatal("The expected output was not received");
        #5;
        operation <= `SUB;
        #5;
        if (ALUresult != 32'hfffffffe) $fatal("The expected output was not received");
        #5;
        operation <= `SLL;
        #5;
        if (ALUresult != 32'h0000a000) $fatal("The expected output was not received");
        #5;
        operation <= `SLT;
        #5;
        if (ALUresult != 32'h00000001) $fatal("The expected output was not received");
        #5;
        operation <= `SLTU;
        #5;
        if (ALUresult != 32'h00000001) $fatal("The expected output was not received");
        #5;
        operation <= `XOR;
        #5;
        if (ALUresult != 32'h00000006) $fatal("The expected output was not received");
        #5;
        operation <= `SRL;
        #5;
        if (ALUresult != 32'h00000000) $fatal("The expected output was not received");
        #5;
        operation <= 4'd11;
        #5;
        if (ALUresult != 32'h00000000) $fatal("The expected output was not received");
        #5;
        operation <= `SRA;
        #5;
        if (ALUresult != 32'h00000000) $fatal("The expected output was not received");
        #5;
        operation <= `OR;
        #5;
        if (ALUresult != 32'h0000000e) $fatal("The expected output was not received");
        #5;
        operation <= `AND;
        #5;
        if (ALUresult != 32'h00000008) $fatal("The expected output was not received");
        #5;
        operand1 <= 32'b10011011100110101100101011110011;
        operand2 <= 32'b00101110010101101001111001010110;
        operation <= `ADD;
        #5;
        if (ALUresult != 32'hc9f16949) $fatal("The expected output was not received");
        #5;
        operation <= `SUB;
        #5;
        if (ALUresult != 32'h6d442c9d) $fatal("The expected output was not received");
        #5;
        operation <= `SLL;
        #5;
        if (ALUresult != 32'hbcc00000) $fatal("The expected output was not received");
        #5;
        operation <= `SLT;
        #5;
        if (ALUresult != 32'h00000001) $fatal("The expected output was not received");
        #5;
        operation <= `SLTU;
        #5;
        if (ALUresult != 32'h00000000) $fatal("The expected output was not received");
        #5;
        operation <= `XOR;
        #5;
        if (ALUresult != 32'hb5cc54a5) $fatal("The expected output was not received");
        #5;
        operation <= `SRL;
        #5;
        if (ALUresult != 32'h0000026e) $fatal("The expected output was not received");
        #5;
        operation <= 4'd11;
        #5;
        if (ALUresult != 32'h0000026e) $fatal("The expected output was not received");
        #5;
        operation <= `SRA;
        #5;
        if (ALUresult != 32'hfffffe6e) $fatal("The expected output was not received");
        #5;
        operation <= `OR;
        #5;
        if (ALUresult != 32'hbfdedef7) $fatal("The expected output was not received");
        #5;
        operation <= `AND;
        #5;
        if (ALUresult != 32'h0a128a52) $fatal("The expected output was not received");
        #10;
        $display ("All test cases passed");
        $finish;
   end 
    
endmodule