data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/macro/pconfigx.v
data/verilator_xmls/57b8f0e2-49c4-4d39-aedc-2d785da7c4c3.xml
module pconfigx
    (
     clk,
     rst,
     upen,
     upws,
     updi,
     out,
     updo
     );

parameter WIDTH = 8;
parameter RESET_VALUE = {WIDTH{1'b0}};

input   clk,
        rst,
        upen,
        upws;
        
input   [WIDTH-1:0] updi;

output  [WIDTH-1:0] out;

output  [WIDTH-1:0] updo;

reg     [WIDTH-1:0] xxxfpcfg = RESET_VALUE;

assign updo = upen ? xxxfpcfg : {WIDTH{1'b0}};

always @(posedge clk)
    begin
    if(rst) xxxfpcfg <= RESET_VALUE;
    else if(upen & upws) xxxfpcfg <= updi;
    end
assign out = xxxfpcfg;

endmodule
module pconfigx
    (
     clk,
     rst,
     upen,
     upws,
     updi,
     out,
     updo
     );


parameter WIDTH = 8;
parameter RESET_VALUE = {WIDTH{1'b0}};

input   clk,
        rst,
        upen,
        upws;
        
input   [WIDTH-1:0] updi;

output  [WIDTH-1:0] out;

output  [WIDTH-1:0] updo;

reg     [WIDTH-1:0] xxxfpcfg = RESET_VALUE;

assign updo = upen ? xxxfpcfg : {WIDTH{1'b0}};

always @(posedge clk)
    begin
    if(rst) xxxfpcfg <= RESET_VALUE;
    else if(upen & upws) xxxfpcfg <= updi;
    end
assign out = xxxfpcfg;

endmodule