data/full_repos/permissive/486367830/debug/top_debug/deb_src/comp_mult_top_test.v
1: b"%Error: data/full_repos/permissive/486367830/debug/top_debug/deb_src/comp_mult_top_test.v:56: syntax error, unexpected '@'\n    @(posedge rst_n);\n    ^\n%Error: data/full_repos/permissive/486367830/debug/top_debug/deb_src/comp_mult_top_test.v:57: syntax error, unexpected '@'\n    repeat(3) @(posedge clk);\n              ^\n%Error: data/full_repos/permissive/486367830/debug/top_debug/deb_src/comp_mult_top_test.v:61: syntax error, unexpected '@'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/486367830/debug/top_debug/deb_src/comp_mult_top_test.v:65: syntax error, unexpected '@'\n    @(posedge clk);           \n    ^\n%Error: data/full_repos/permissive/486367830/debug/top_debug/deb_src/comp_mult_top_test.v:69: syntax error, unexpected '@'\n    @(posedge clk);           \n    ^\n%Error: data/full_repos/permissive/486367830/debug/top_debug/deb_src/comp_mult_top_test.v:75: syntax error, unexpected '@'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/486367830/debug/top_debug/deb_src/comp_mult_top_test.v:79: syntax error, unexpected '@'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/486367830/debug/top_debug/deb_src/comp_mult_top_test.v:83: syntax error, unexpected '@'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/486367830/debug/top_debug/deb_src/comp_mult_top_test.v:87: syntax error, unexpected '@'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/486367830/debug/top_debug/deb_src/comp_mult_top_test.v:91: syntax error, unexpected '@'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/486367830/debug/top_debug/deb_src/comp_mult_top_test.v:96: syntax error, unexpected '@'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/486367830/debug/top_debug/deb_src/comp_mult_top_test.v:102: syntax error, unexpected '@'\n        repeat(4) @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/486367830/debug/top_debug/deb_src/comp_mult_top_test.v:104: syntax error, unexpected '@'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/486367830/debug/top_debug/deb_src/comp_mult_top_test.v:109: syntax error, unexpected '@'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/486367830/debug/top_debug/deb_src/comp_mult_top_test.v:125: syntax error, unexpected '@'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/486367830/debug/top_debug/deb_src/comp_mult_top_test.v:132: syntax error, unexpected '@'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/486367830/debug/top_debug/deb_src/comp_mult_top_test.v:137: syntax error, unexpected '@'\n    repeat(3) @(posedge clk);\n              ^\n%Error: Exiting due to 17 error(s)\n"
module comp_mult_top_test; 

localparam NO_MULT    = 4    ;
localparam APB_BADDR  = 1024 ;
localparam SYS_AW     = 16   ;
localparam REG_DW     = 16   ;
                      
localparam OP1_BA     = 16'd500  ;
localparam OP2_BA     = 16'd1500 ;
localparam RES_BA     = 16'd4500 ;
localparam EXP_RES_BA = 16'd6500 ;
localparam NR_OP      = 16'd300  ;
                    
localparam VERBOSE = 1;

wire                clk         ;
wire                rst_n       ;
           
reg   [ SYS_AW-1:0] apb_paddr   ;
reg                 apb_penable ;
reg                 apb_pwrite  ;
reg   [REG_DW -1:0] apb_pwdata  ;
reg                 apb_psel    ;
wire                apb_pready  ;
wire  [REG_DW -1:0] apb_prdata  ;
wire                apb_pslverr ;

wire                mem_ce      ;
wire                mem_we      ;
wire  [SYS_AW -1:0] mem_addr    ;
wire  [     8 -1:0] mem_wr_data ;
wire  [     8 -1:0] mem_rd_data ;

integer i;
integer fb;


initial begin 
    apb_paddr  <= 'd0;
    apb_pwrite <= 'd0;
    apb_pwdata <= 'd0;
    apb_psel   <= 'd0;
end 


initial begin 

    @(posedge rst_n);
    repeat(3) @(posedge clk);
    
    apb_paddr   <= APB_BADDR+4;
    apb_pwdata  <= 'b10;
    @(posedge clk);
    
    apb_psel    <= 1'b1;
    
    @(posedge clk);           
    apb_pwrite  <= 1'b1;
    apb_penable <= 1'b1;
                
    @(posedge clk);           
    apb_pwrite  <= 1'b1;
    apb_penable <= 1'b1;
    
    apb_paddr   <= APB_BADDR;
    apb_pwdata  <= OP1_BA;
    @(posedge clk);
    
    apb_paddr   <= APB_BADDR+1;
    apb_pwdata  <= OP2_BA;
    @(posedge clk);
    
    apb_paddr   <= APB_BADDR+2;
    apb_pwdata  <= RES_BA;
    @(posedge clk);
    
    apb_paddr   <= APB_BADDR+3;
    apb_pwdata  <= NR_OP;
    @(posedge clk);
    
    apb_paddr   <= APB_BADDR+4;
    apb_pwdata  <= 'b01;
    @(posedge clk);
    

    apb_pwrite  <= 1'b0;
    apb_paddr   <= APB_BADDR+5;
    @(posedge clk);
    

    while(~apb_prdata[0]) begin 
        
        apb_penable <= 1'b0; 
        repeat(4) @(posedge clk);
        apb_penable <= 1'b1;
        @(posedge clk);
        

        apb_paddr   <= APB_BADDR+6;
        apb_penable <= 1'b1;
        @(posedge clk);
        
        apb_paddr  <= APB_BADDR+5;
    end 
    






    

    apb_pwrite <= 1'b1;
    apb_paddr  <= APB_BADDR+69;
    apb_pwdata <= 16'hDEAD;
    @(posedge clk);
    

    apb_pwrite  <= 1'b0;
    apb_penable <= 1'b0;
    apb_psel    <= 1'b0;
    
    @(posedge clk);
    if(~apb_pslverr)
        $display("%M WARNING: Expected slave error!");
        

    repeat(3) @(posedge clk);
    

    for(i = 0; i < NR_OP*6; i = i + 1) begin 
        if(i_mem_1rw.mem[RES_BA + i] == i_mem_1rw.mem[EXP_RES_BA + i])
            $display("%M OP %0d ----- OK    , %0h == %0h", i/6, i_mem_1rw.mem[RES_BA + i], i_mem_1rw.mem[EXP_RES_BA + i]);
        else 
            $display("%M OP %0d ----- FAILED, %0h != %0h", i/6, i_mem_1rw.mem[RES_BA + i], i_mem_1rw.mem[EXP_RES_BA + i]);
    end 
    

    fb = $fopen("../deb_src/mem.raw", "rb+");
    if($fseek(fb, RES_BA, 0) == -1) $display("%M ERROR: fseek failed!");
    
    for(i = RES_BA; i < RES_BA + NR_OP*6; i = i + 1) begin 
        
        $fwrite(fb, "%c", i_mem_1rw.mem[i]);

    end 

    $fclose(fb);
    
    $display("END SIM");
    $stop;
    
end 

comp_mult_top #(
.NO_MULT     (NO_MULT    ),
.APB_BADDR   (APB_BADDR  ),
.SYS_AW      (SYS_AW     ),
.REG_DW      (REG_DW     )
) DUT_comp_mult_top (
.clk         (clk        ),
.rst_n       (rst_n      ),
.apb_paddr   (apb_paddr  ),
.apb_penable (apb_penable),
.apb_pwrite  (apb_pwrite ),
.apb_pwdata  (apb_pwdata ),
.apb_psel    (apb_psel   ),
.apb_pready  (apb_pready ),
.apb_prdata  (apb_prdata ),
.apb_pslverr (apb_pslverr),
.mem_ce      (mem_ce     ),
.mem_we      (mem_we     ),
.mem_addr    (mem_addr   ),
.mem_wr_data (mem_wr_data),
.mem_rd_data (mem_rd_data)
);


mem_1rw #(
.ADDR_WIDTH  (SYS_AW      ),
.MEM_DEPTH   (2 ** SYS_AW ),
.WORD_BYTES  (1           )
) i_mem_1rw (
.clk         (clk         ),
.ce          (mem_ce      ),
.we          (mem_we      ),
.addr        (mem_addr    ),
.wr_data     (mem_wr_data ),
.be          (1'b1        ),
.rd_data     (mem_rd_data )
);

comp_mult_ref_model #(
.DWIDTH  (8       ),
.VERBOSE (0       )
) i_comp_mult_ref_model (

.clk          (clk                                            ),
.rst_n        (rst_n                                          ),
.sw_rst       (sw_rst                                         ),
.op_val       (DUT_comp_mult_top.i_comp_mult_wrapper.op_val   ),
.op_rdy       (DUT_comp_mult_top.i_comp_mult_wrapper.op_rdy   ),
.op_data      (DUT_comp_mult_top.i_comp_mult_wrapper.op_data  ),
.res_val      (DUT_comp_mult_top.i_comp_mult_wrapper.res_val  ),
.res_rdy      (DUT_comp_mult_top.i_comp_mult_wrapper.res_rdy  ),
.res_data     (DUT_comp_mult_top.i_comp_mult_wrapper.res_data ),
.exp_res_data (                                               )
); 

clk_rst_tb #(
.PERIOD (5)
) i_clk_rst_tb (
.clk   (clk  ),
.rst_n (rst_n)
);



endmodule
module comp_mult_top_test;
 

localparam NO_MULT    = 4    ;
localparam APB_BADDR  = 1024 ;
localparam SYS_AW     = 16   ;
localparam REG_DW     = 16   ;
                      
localparam OP1_BA     = 16'd500  ;
localparam OP2_BA     = 16'd1500 ;
localparam RES_BA     = 16'd4500 ;
localparam EXP_RES_BA = 16'd6500 ;
localparam NR_OP      = 16'd300  ;
                    
localparam VERBOSE = 1;

wire                clk         ;
wire                rst_n       ;
           
reg   [ SYS_AW-1:0] apb_paddr   ;
reg                 apb_penable ;
reg                 apb_pwrite  ;
reg   [REG_DW -1:0] apb_pwdata  ;
reg                 apb_psel    ;
wire                apb_pready  ;
wire  [REG_DW -1:0] apb_prdata  ;
wire                apb_pslverr ;

wire                mem_ce      ;
wire                mem_we      ;
wire  [SYS_AW -1:0] mem_addr    ;
wire  [     8 -1:0] mem_wr_data ;
wire  [     8 -1:0] mem_rd_data ;

integer i;
integer fb;


initial begin 
    apb_paddr  <= 'd0;
    apb_pwrite <= 'd0;
    apb_pwdata <= 'd0;
    apb_psel   <= 'd0;
end 


initial begin 

    @(posedge rst_n);
    repeat(3) @(posedge clk);
    
    apb_paddr   <= APB_BADDR+4;
    apb_pwdata  <= 'b10;
    @(posedge clk);
    
    apb_psel    <= 1'b1;
    
    @(posedge clk);           
    apb_pwrite  <= 1'b1;
    apb_penable <= 1'b1;
                
    @(posedge clk);           
    apb_pwrite  <= 1'b1;
    apb_penable <= 1'b1;
    
    apb_paddr   <= APB_BADDR;
    apb_pwdata  <= OP1_BA;
    @(posedge clk);
    
    apb_paddr   <= APB_BADDR+1;
    apb_pwdata  <= OP2_BA;
    @(posedge clk);
    
    apb_paddr   <= APB_BADDR+2;
    apb_pwdata  <= RES_BA;
    @(posedge clk);
    
    apb_paddr   <= APB_BADDR+3;
    apb_pwdata  <= NR_OP;
    @(posedge clk);
    
    apb_paddr   <= APB_BADDR+4;
    apb_pwdata  <= 'b01;
    @(posedge clk);
    

    apb_pwrite  <= 1'b0;
    apb_paddr   <= APB_BADDR+5;
    @(posedge clk);
    

    while(~apb_prdata[0]) begin 
        
        apb_penable <= 1'b0; 
        repeat(4) @(posedge clk);
        apb_penable <= 1'b1;
        @(posedge clk);
        

        apb_paddr   <= APB_BADDR+6;
        apb_penable <= 1'b1;
        @(posedge clk);
        
        apb_paddr  <= APB_BADDR+5;
    end 
    






    

    apb_pwrite <= 1'b1;
    apb_paddr  <= APB_BADDR+69;
    apb_pwdata <= 16'hDEAD;
    @(posedge clk);
    

    apb_pwrite  <= 1'b0;
    apb_penable <= 1'b0;
    apb_psel    <= 1'b0;
    
    @(posedge clk);
    if(~apb_pslverr)
        $display("%M WARNING: Expected slave error!");
        

    repeat(3) @(posedge clk);
    

    for(i = 0; i < NR_OP*6; i = i + 1) begin 
        if(i_mem_1rw.mem[RES_BA + i] == i_mem_1rw.mem[EXP_RES_BA + i])
            $display("%M OP %0d ----- OK    , %0h == %0h", i/6, i_mem_1rw.mem[RES_BA + i], i_mem_1rw.mem[EXP_RES_BA + i]);
        else 
            $display("%M OP %0d ----- FAILED, %0h != %0h", i/6, i_mem_1rw.mem[RES_BA + i], i_mem_1rw.mem[EXP_RES_BA + i]);
    end 
    

    fb = $fopen("../deb_src/mem.raw", "rb+");
    if($fseek(fb, RES_BA, 0) == -1) $display("%M ERROR: fseek failed!");
    
    for(i = RES_BA; i < RES_BA + NR_OP*6; i = i + 1) begin 
        
        $fwrite(fb, "%c", i_mem_1rw.mem[i]);

    end 

    $fclose(fb);
    
    $display("END SIM");
    $stop;
    
end 

comp_mult_top #(
.NO_MULT     (NO_MULT    ),
.APB_BADDR   (APB_BADDR  ),
.SYS_AW      (SYS_AW     ),
.REG_DW      (REG_DW     )
) DUT_comp_mult_top (
.clk         (clk        ),
.rst_n       (rst_n      ),
.apb_paddr   (apb_paddr  ),
.apb_penable (apb_penable),
.apb_pwrite  (apb_pwrite ),
.apb_pwdata  (apb_pwdata ),
.apb_psel    (apb_psel   ),
.apb_pready  (apb_pready ),
.apb_prdata  (apb_prdata ),
.apb_pslverr (apb_pslverr),
.mem_ce      (mem_ce     ),
.mem_we      (mem_we     ),
.mem_addr    (mem_addr   ),
.mem_wr_data (mem_wr_data),
.mem_rd_data (mem_rd_data)
);


mem_1rw #(
.ADDR_WIDTH  (SYS_AW      ),
.MEM_DEPTH   (2 ** SYS_AW ),
.WORD_BYTES  (1           )
) i_mem_1rw (
.clk         (clk         ),
.ce          (mem_ce      ),
.we          (mem_we      ),
.addr        (mem_addr    ),
.wr_data     (mem_wr_data ),
.be          (1'b1        ),
.rd_data     (mem_rd_data )
);

comp_mult_ref_model #(
.DWIDTH  (8       ),
.VERBOSE (0       )
) i_comp_mult_ref_model (

.clk          (clk                                            ),
.rst_n        (rst_n                                          ),
.sw_rst       (sw_rst                                         ),
.op_val       (DUT_comp_mult_top.i_comp_mult_wrapper.op_val   ),
.op_rdy       (DUT_comp_mult_top.i_comp_mult_wrapper.op_rdy   ),
.op_data      (DUT_comp_mult_top.i_comp_mult_wrapper.op_data  ),
.res_val      (DUT_comp_mult_top.i_comp_mult_wrapper.res_val  ),
.res_rdy      (DUT_comp_mult_top.i_comp_mult_wrapper.res_rdy  ),
.res_data     (DUT_comp_mult_top.i_comp_mult_wrapper.res_data ),
.exp_res_data (                                               )
); 

clk_rst_tb #(
.PERIOD (5)
) i_clk_rst_tb (
.clk   (clk  ),
.rst_n (rst_n)
);



endmodule