data/full_repos/permissive/516679177/M_ALU/tb_M_ALU.v
1: b'%Error: data/full_repos/permissive/516679177/M_ALU/tb_M_ALU.v:22: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("dump.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/516679177/M_ALU/tb_M_ALU.v:23: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(1);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/516679177/M_ALU/tb_M_ALU.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/516679177/M_ALU/tb_M_ALU.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/M_ALU/tb_M_ALU.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/M_ALU/tb_M_ALU.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/M_ALU/tb_M_ALU.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/M_ALU/tb_M_ALU.v:75: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/M_ALU/tb_M_ALU.v:85: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/M_ALU/tb_M_ALU.v:95: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/M_ALU/tb_M_ALU.v:105: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/M_ALU/tb_M_ALU.v:115: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/M_ALU/tb_M_ALU.v:125: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/M_ALU/tb_M_ALU.v:135: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/M_ALU/tb_M_ALU.v:145: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/M_ALU/tb_M_ALU.v:155: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/M_ALU/tb_M_ALU.v:165: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/M_ALU/tb_M_ALU.v:175: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/M_ALU/tb_M_ALU.v:185: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/M_ALU/tb_M_ALU.v:195: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/M_ALU/tb_M_ALU.v:205: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/M_ALU/tb_M_ALU.v:216: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Error: Exiting due to 2 error(s), 20 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench_M_ALU;
  
  reg [7:0] A;
  reg [7:0] B;
  
  reg [3:0] SEL_TMP;
  
  
  wire [7:0] ALU_OUT_TMP;
  wire [3:0] FLAG_TMP;
  
  M_ALU DUT(.ALU_OUT_TMP(ALU_OUT_TMP),
             .FLAG_TMP(FLAG_TMP),
             .A(A),
             .B(B),
             .SEL_TMP(SEL_TMP)
            );
  
  
  initial begin

    $dumpfile("dump.vcd");
    $dumpvars(1);
    
    

    
    #1
    
    SEL_TMP = 4'h0;
    A= 8'b0010_1011;
    B= 8'b0000_0100;
    
    #1
    
    display;
    

    
    SEL_TMP = 4'h0;
    A= 8'b1010_1011;
    B= 8'b1000_0100;
    
    #1
    
    display;
    
    

    
    SEL_TMP = 4'h1;
    A= 8'b0010_1011;
    B= 8'b0000_0100;
    
    #1
    
    display;
    

    
    SEL_TMP = 4'h1;
    B = 8'b0010_1011;
    A = 8'b0000_0100;
    
    #1
    
    display;


    
    SEL_TMP = 4'h2;
    A = 8'b0010_1011;
    B = 8'b0000_0100;
    
    #1
    
    display;
    

    
    SEL_TMP = 4'h2;
    A = 8'b1010_1011;
    B = 8'b1000_0100;
    
    #1
    
    display;
    

    
    SEL_TMP = 4'h3;
    A = 8'b0010_1011;
    B = 8'b0000_0100;
    
    #1
    
    display;
    

    
    SEL_TMP = 4'h3;
    B = 8'b0010_1011;
    A = 8'b0000_0100;
    
    #1
    
    display;
    

    
    SEL_TMP = 4'h4;
    A= 8'b0010_1011;
    B= 8'b0000_0100;
    
    #1
    
    display;
    

    
    SEL_TMP = 4'h4;
    A= 8'b0010_1011;
    B= 8'b0000_0011;
    
    #1
    
    display;
    

    
    SEL_TMP = 4'h5;
    A= 8'b0010_1011;
    B= 8'b0000_0100;
    
    #1
    
    display;
    

    
    SEL_TMP = 4'h5;
    A= 8'b0010_1011;
    B= 8'b1000_0100;
    
    #1
    
    display;
    

    
    SEL_TMP = 4'h6;
    A= 8'b0010_1011;
    B= 8'b0000_0110;
    
    #1
    
    display;
    

    
    SEL_TMP = 4'h7;
    A= 8'b0010_1011;
    B= 8'b0000_0100;
    
    #1
    
    display;
    

    
    SEL_TMP = 4'h8;
    A= 8'b0010_1011;
    B= 8'b0000_0100;
    
    #1
    
    display;
    

    
    SEL_TMP = 4'h9;
    A= 8'b0010_1011;
    B= 8'b0000_0100;
    
    #1
    
    display;
    

    
    SEL_TMP = 4'hA;
    A= 8'b0010_1011;
    B= 8'b0000_0100;
    
    #1
    
    display;
    

    
    SEL_TMP = 4'hB;
    A= 8'b0010_1011;
    B= 8'b0000_0100;
    
    #1
    
    display;
    
    

    
    SEL_TMP = 4'hC;
    A= 8'b0010_1011;
    B= 8'b0000_0100;
    
    #1
    
    display;
   
  end
  
  task display;
    $display("A:%b, B:%b, SEL_TMP:%h, ALU_OUT_TMP:%b, FLAG_TMP:%b",
             A, B, SEL_TMP, ALU_OUT_TMP, FLAG_TMP);
  endtask
  
endmodule
module testbench_M_ALU;

  
  reg [7:0] A;
  reg [7:0] B;
  
  reg [3:0] SEL_TMP;
  
  
  wire [7:0] ALU_OUT_TMP;
  wire [3:0] FLAG_TMP;
  
  M_ALU DUT(.ALU_OUT_TMP(ALU_OUT_TMP),
             .FLAG_TMP(FLAG_TMP),
             .A(A),
             .B(B),
             .SEL_TMP(SEL_TMP)
            );
  
  
  initial begin

    $dumpfile("dump.vcd");
    $dumpvars(1);
    
    

    
    #1
    
    SEL_TMP = 4'h0;
    A= 8'b0010_1011;
    B= 8'b0000_0100;
    
    #1
    
    display;
    

    
    SEL_TMP = 4'h0;
    A= 8'b1010_1011;
    B= 8'b1000_0100;
    
    #1
    
    display;
    
    

    
    SEL_TMP = 4'h1;
    A= 8'b0010_1011;
    B= 8'b0000_0100;
    
    #1
    
    display;
    

    
    SEL_TMP = 4'h1;
    B = 8'b0010_1011;
    A = 8'b0000_0100;
    
    #1
    
    display;


    
    SEL_TMP = 4'h2;
    A = 8'b0010_1011;
    B = 8'b0000_0100;
    
    #1
    
    display;
    

    
    SEL_TMP = 4'h2;
    A = 8'b1010_1011;
    B = 8'b1000_0100;
    
    #1
    
    display;
    

    
    SEL_TMP = 4'h3;
    A = 8'b0010_1011;
    B = 8'b0000_0100;
    
    #1
    
    display;
    

    
    SEL_TMP = 4'h3;
    B = 8'b0010_1011;
    A = 8'b0000_0100;
    
    #1
    
    display;
    

    
    SEL_TMP = 4'h4;
    A= 8'b0010_1011;
    B= 8'b0000_0100;
    
    #1
    
    display;
    

    
    SEL_TMP = 4'h4;
    A= 8'b0010_1011;
    B= 8'b0000_0011;
    
    #1
    
    display;
    

    
    SEL_TMP = 4'h5;
    A= 8'b0010_1011;
    B= 8'b0000_0100;
    
    #1
    
    display;
    

    
    SEL_TMP = 4'h5;
    A= 8'b0010_1011;
    B= 8'b1000_0100;
    
    #1
    
    display;
    

    
    SEL_TMP = 4'h6;
    A= 8'b0010_1011;
    B= 8'b0000_0110;
    
    #1
    
    display;
    

    
    SEL_TMP = 4'h7;
    A= 8'b0010_1011;
    B= 8'b0000_0100;
    
    #1
    
    display;
    

    
    SEL_TMP = 4'h8;
    A= 8'b0010_1011;
    B= 8'b0000_0100;
    
    #1
    
    display;
    

    
    SEL_TMP = 4'h9;
    A= 8'b0010_1011;
    B= 8'b0000_0100;
    
    #1
    
    display;
    

    
    SEL_TMP = 4'hA;
    A= 8'b0010_1011;
    B= 8'b0000_0100;
    
    #1
    
    display;
    

    
    SEL_TMP = 4'hB;
    A= 8'b0010_1011;
    B= 8'b0000_0100;
    
    #1
    
    display;
    
    

    
    SEL_TMP = 4'hC;
    A= 8'b0010_1011;
    B= 8'b0000_0100;
    
    #1
    
    display;
   
  end
  
  task display;
    $display("A:%b, B:%b, SEL_TMP:%h, ALU_OUT_TMP:%b, FLAG_TMP:%b",
             A, B, SEL_TMP, ALU_OUT_TMP, FLAG_TMP);
  endtask
  
endmodule