data/full_repos/permissive/452016975/src/instruction_memory.v
data/verilator_xmls/aa076dd6-9923-4001-b6fc-4b60d5737200.xml
module instruction_memory(read_address,_instruction);

input [31:0] read_address;
output reg[15:0] _instruction;

reg [15:0] instr_memory [29:0];

initial begin
	$readmemb("C:/Users/okant/Desktop/16-bit-MiniMIPS-CPU/simulation/modelsim/instruction_data.txt", instr_memory);
end


always @(*) begin
	_instruction = instr_memory[read_address];
end

endmodule
module instruction_memory(read_address,_instruction);


input [31:0] read_address;
output reg[15:0] _instruction;

reg [15:0] instr_memory [29:0];

initial begin
	$readmemb("C:/Users/okant/Desktop/16-bit-MiniMIPS-CPU/simulation/modelsim/instruction_data.txt", instr_memory);
end


always @(*) begin
	_instruction = instr_memory[read_address];
end

endmodule