data/full_repos/permissive/419538859/lab3/lab3_1self/sim/clock_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/419538859/lab3/lab3_1self/sim/clock_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n #(clkper / 2)  clk = ~clk;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab3/lab3_1self/sim/clock_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n #20;   \n ^\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab3/lab3_1self/sim/clock_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #80;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab3/lab3_1self/sim/clock_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #712000;   \n ^\n%Error: data/full_repos/permissive/419538859/lab3/lab3_1self/sim/clock_tb.v:12: Cannot find file containing module: \'clock\'\nclock clock_instance\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/419538859/lab3/lab3_1self/sim,data/full_repos/permissive/419538859/clock\n             data/full_repos/permissive/419538859/lab3/lab3_1self/sim,data/full_repos/permissive/419538859/clock.v\n             data/full_repos/permissive/419538859/lab3/lab3_1self/sim,data/full_repos/permissive/419538859/clock.sv\n             clock\n             clock.v\n             clock.sv\n             obj_dir/clock\n             obj_dir/clock.v\n             obj_dir/clock.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module 	testbench;

reg 	clk,reset,enable;

wire	[3:0]count5,count4,count3,count2,count1,count0;
wire	[3:0]count1reg,count0reg;

wire 	carry,carry2,carry1,carry0,carry4;

clock clock_instance
				(.clk(clk),.reset(reset),.enable(enable),
					.count5(count5),.count4(count4),.count3(count3),
					.count2(count2),.count1(count1),.count0(count0),.carry(carry));


parameter clkper = 5;

initial
begin
	clk = 1;
end

always 
begin
	#(clkper / 2)  clk = ~clk;
end

initial
begin
 reset	=1'b1;
 enable =1'b0;
 #20;			
 reset  =1'b0;
 #80;
 enable =1'b1; 
 #712000;			
end
endmodule
module 	testbench;


reg 	clk,reset,enable;

wire	[3:0]count5,count4,count3,count2,count1,count0;
wire	[3:0]count1reg,count0reg;

wire 	carry,carry2,carry1,carry0,carry4;

clock clock_instance
				(.clk(clk),.reset(reset),.enable(enable),
					.count5(count5),.count4(count4),.count3(count3),
					.count2(count2),.count1(count1),.count0(count0),.carry(carry));


parameter clkper = 5;

initial
begin
	clk = 1;
end

always 
begin
	#(clkper / 2)  clk = ~clk;
end

initial
begin
 reset	=1'b1;
 enable =1'b0;
 #20;			
 reset  =1'b0;
 #80;
 enable =1'b1; 
 #712000;			
end
endmodule