data/full_repos/permissive/485085993/verilog/rtl/luts.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/luts.v:20: Little bit endian vector: MSB < LSB of bit range: 0:3\ninput [0:3] in;\n      ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/luts.v:22: Little bit endian vector: MSB < LSB of bit range: 0:15\ninput [0:15] sram;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/luts.v:24: Little bit endian vector: MSB < LSB of bit range: 0:15\ninput [0:15] sram_inv;\n      ^\n%Error: data/full_repos/permissive/485085993/verilog/rtl/luts.v:52: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_0_ (\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/INVTX1\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/INVTX1.v\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/INVTX1.sv\n             INVTX1\n             INVTX1.v\n             INVTX1.sv\n             obj_dir/INVTX1\n             obj_dir/INVTX1.v\n             obj_dir/INVTX1.sv\n%Error: data/full_repos/permissive/485085993/verilog/rtl/luts.v:56: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_1_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/luts.v:60: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_2_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/luts.v:64: Cannot find file containing module: \'INVTX1\'\n INVTX1 INVTX1_3_ (\n ^~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/luts.v:68: Cannot find file containing module: \'buf4\'\n buf4 buf4_0_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/luts.v:72: Cannot find file containing module: \'buf4\'\n buf4 buf4_1_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/luts.v:76: Cannot find file containing module: \'buf4\'\n buf4 buf4_2_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/luts.v:80: Cannot find file containing module: \'buf4\'\n buf4 buf4_3_ (\n ^~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/luts.v:84: Cannot find file containing module: \'lut4_mux\'\n lut4_mux lut4_mux_0_ (\n ^~~~~~~~\n%Error: Exiting due to 9 error(s), 3 warning(s)\n'
module lut4(in,
            sram,
            sram_inv,
            out);

input [0:3] in;

input [0:15] sram;

input [0:15] sram_inv;

output [0:0] out;


wire [0:3] in;
wire [0:0] out;







wire [0:0] INVTX1_0_out;
wire [0:0] INVTX1_1_out;
wire [0:0] INVTX1_2_out;
wire [0:0] INVTX1_3_out;
wire [0:0] buf4_0_out;
wire [0:0] buf4_1_out;
wire [0:0] buf4_2_out;
wire [0:0] buf4_3_out;






	INVTX1 INVTX1_0_ (
		.in(in[0]),
		.out(INVTX1_0_out));

	INVTX1 INVTX1_1_ (
		.in(in[1]),
		.out(INVTX1_1_out));

	INVTX1 INVTX1_2_ (
		.in(in[2]),
		.out(INVTX1_2_out));

	INVTX1 INVTX1_3_ (
		.in(in[3]),
		.out(INVTX1_3_out));

	buf4 buf4_0_ (
		.in(in[0]),
		.out(buf4_0_out));

	buf4 buf4_1_ (
		.in(in[1]),
		.out(buf4_1_out));

	buf4 buf4_2_ (
		.in(in[2]),
		.out(buf4_2_out));

	buf4 buf4_3_ (
		.in(in[3]),
		.out(buf4_3_out));

	lut4_mux lut4_mux_0_ (
		.in(sram[0:15]),
		.sram({buf4_0_out, buf4_1_out, buf4_2_out, buf4_3_out}),
		.sram_inv({INVTX1_0_out, INVTX1_1_out, INVTX1_2_out, INVTX1_3_out}),
		.out(out));

endmodule
module lut4(in,
            sram,
            sram_inv,
            out);


input [0:3] in;

input [0:15] sram;

input [0:15] sram_inv;

output [0:0] out;


wire [0:3] in;
wire [0:0] out;







wire [0:0] INVTX1_0_out;
wire [0:0] INVTX1_1_out;
wire [0:0] INVTX1_2_out;
wire [0:0] INVTX1_3_out;
wire [0:0] buf4_0_out;
wire [0:0] buf4_1_out;
wire [0:0] buf4_2_out;
wire [0:0] buf4_3_out;






	INVTX1 INVTX1_0_ (
		.in(in[0]),
		.out(INVTX1_0_out));

	INVTX1 INVTX1_1_ (
		.in(in[1]),
		.out(INVTX1_1_out));

	INVTX1 INVTX1_2_ (
		.in(in[2]),
		.out(INVTX1_2_out));

	INVTX1 INVTX1_3_ (
		.in(in[3]),
		.out(INVTX1_3_out));

	buf4 buf4_0_ (
		.in(in[0]),
		.out(buf4_0_out));

	buf4 buf4_1_ (
		.in(in[1]),
		.out(buf4_1_out));

	buf4 buf4_2_ (
		.in(in[2]),
		.out(buf4_2_out));

	buf4 buf4_3_ (
		.in(in[3]),
		.out(buf4_3_out));

	lut4_mux lut4_mux_0_ (
		.in(sram[0:15]),
		.sram({buf4_0_out, buf4_1_out, buf4_2_out, buf4_3_out}),
		.sram_inv({INVTX1_0_out, INVTX1_1_out, INVTX1_2_out, INVTX1_3_out}),
		.out(out));

endmodule