data/full_repos/permissive/425175279/MIPS_Pipeline/Forward_Unit.v
data/verilator_xmls/809d37f5-50da-40dd-a496-4f065a27def3.xml
module Forward_Unit(

    input        rst_n,


    input       [4:0]   RsE,
    input       [4:0]   RtE,
    input       [4:0]   RsD,
    input       [4:0]   RtD,
    input       [4:0]   WriteRegM,
    input       [4:0]   WriteRegW,
    input               RegWriteM,
    input               RegWriteW,

    output  reg [1:0]   ForwardAE,
    output  reg [1:0]   ForwardBE,
    output  reg         ForwardAD,
    output  reg         ForwardBD
);


    always @(*) begin
        if (~rst_n) begin
            ForwardAE = 2'b00;
        end
        else begin


            if ((RsE != 0) && (RsE == WriteRegM) && RegWriteM) begin

                ForwardAE = 2'b10;
            end

            else if ((RsE != 0) && (RsE == WriteRegW) && RegWriteW) begin

                ForwardAE = 2'b01;
            end
            else
                ForwardAE = 2'b00;
        end
    end

    always @(*) begin
        if (~rst_n) begin
            ForwardBE = 2'b00;
        end
        else begin


            if ((RtE != 0) && (RtE == WriteRegM) && RegWriteM) begin

                ForwardBE = 2'b10;
            end

            else if ((RtE != 0) && (RtE == WriteRegW) && RegWriteW) begin

                ForwardBE = 2'b01;
            end
            else
                ForwardBE = 2'b00;
        end
    end


    always @(*) begin
        if (~rst_n) begin
            ForwardAD = 1'b0;
        end
        else if ((RsD != 0) && (RsD == WriteRegM) && RegWriteM) begin
            ForwardAD = 1'b1;
        end
        else begin
            ForwardAD = 1'b0;
        end
    end

    always @(*) begin
        if (~rst_n) begin
            ForwardBD = 1'b0;
        end
        else if ((RtD != 0) && (RtD == WriteRegM) && RegWriteM) begin
            ForwardBD = 1'b1;
        end
        else begin
            ForwardBD = 1'b0;
        end
    end


endmodule
module Forward_Unit(

    input        rst_n,


    input       [4:0]   RsE,
    input       [4:0]   RtE,
    input       [4:0]   RsD,
    input       [4:0]   RtD,
    input       [4:0]   WriteRegM,
    input       [4:0]   WriteRegW,
    input               RegWriteM,
    input               RegWriteW,

    output  reg [1:0]   ForwardAE,
    output  reg [1:0]   ForwardBE,
    output  reg         ForwardAD,
    output  reg         ForwardBD
);



    always @(*) begin
        if (~rst_n) begin
            ForwardAE = 2'b00;
        end
        else begin


            if ((RsE != 0) && (RsE == WriteRegM) && RegWriteM) begin

                ForwardAE = 2'b10;
            end

            else if ((RsE != 0) && (RsE == WriteRegW) && RegWriteW) begin

                ForwardAE = 2'b01;
            end
            else
                ForwardAE = 2'b00;
        end
    end

    always @(*) begin
        if (~rst_n) begin
            ForwardBE = 2'b00;
        end
        else begin


            if ((RtE != 0) && (RtE == WriteRegM) && RegWriteM) begin

                ForwardBE = 2'b10;
            end

            else if ((RtE != 0) && (RtE == WriteRegW) && RegWriteW) begin

                ForwardBE = 2'b01;
            end
            else
                ForwardBE = 2'b00;
        end
    end


    always @(*) begin
        if (~rst_n) begin
            ForwardAD = 1'b0;
        end
        else if ((RsD != 0) && (RsD == WriteRegM) && RegWriteM) begin
            ForwardAD = 1'b1;
        end
        else begin
            ForwardAD = 1'b0;
        end
    end

    always @(*) begin
        if (~rst_n) begin
            ForwardBD = 1'b0;
        end
        else if ((RtD != 0) && (RtD == WriteRegM) && RegWriteM) begin
            ForwardBD = 1'b1;
        end
        else begin
            ForwardBD = 1'b0;
        end
    end


endmodule