data/full_repos/permissive/509809169/Circuits/Sequential Logic/Latches and Flip Flops/Create circuit from truth table.v
1: b'%Error: Cannot find file containing module: Logic/Latches\n        ... Looked in:\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Latches\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Latches.v\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Latches.sv\n             Logic/Latches\n             Logic/Latches.v\n             Logic/Latches.sv\n             obj_dir/Logic/Latches\n             obj_dir/Logic/Latches.v\n             obj_dir/Logic/Latches.sv\n%Error: Cannot find file containing module: and\n%Error: Cannot find file containing module: Flip\n%Error: Cannot find file containing module: Flops,data/full_repos/permissive/509809169\n%Error: Cannot find file containing module: data/full_repos/permissive/509809169/Circuits/Sequential\n%Error: Cannot find file containing module: Flops/Create\n%Error: Cannot find file containing module: circuit\n%Error: Cannot find file containing module: from\n%Error: Cannot find file containing module: truth\n%Error: Cannot find file containing module: table.v\n%Error: Exiting due to 10 error(s)\n'
module top_module (
    input clk,
    input j,
    input k,
    output Q); 
    always @(posedge clk) begin
        case({j,k})
            2'b00:Q<=Q;
            2'b01: Q<=0;
            2'b10: Q<=1;
            2'b11: Q<=~Q;
        endcase
    end
endmodule
module top_module (
    input clk,
    input j,
    input k,
    output Q);
 
    always @(posedge clk) begin
        case({j,k})
            2'b00:Q<=Q;
            2'b01: Q<=0;
            2'b10: Q<=1;
            2'b11: Q<=~Q;
        endcase
    end
endmodule