data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/tb_cva6_icache/hdl/tlb_emul.sv
1: b"%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/tb_cva6_icache/hdl/tlb_emul.sv:17: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER\nmodule tlb_emul import ariane_pkg::*; import wt_cache_pkg::*; #(\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/tb_cva6_icache/hdl/tlb_emul.sv:19: syntax error, unexpected ')', expecting ';'\n) (\n^\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/tb_cva6_icache/hdl/tlb_emul.sv:21: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input logic            rst_ni,\n  ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/tb_cva6_icache/hdl/tlb_emul.sv:23: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input logic            tlb_rand_en_i,\n  ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/tb_cva6_icache/hdl/tlb_emul.sv:24: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input logic            exception_en_i,\n  ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/tb_cva6_icache/hdl/tlb_emul.sv:25: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input logic [63:0]     tlb_offset_i,\n  ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/tb_cva6_icache/hdl/tlb_emul.sv:28: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  icache_areq_o_t req_i,\n  ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/tb_cva6_icache/hdl/tlb_emul.sv:34: syntax error, unexpected always_ff\nalways_ff @(posedge clk_i or negedge rst_ni) begin : p_tlb_rand\n^~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/tb_cva6_icache/hdl/tlb_emul.sv:38: syntax error, unexpected assert\n  assert(TlbRandHitRate<=100 && TlbRandHitRate>=0) else\n  ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/tb_cva6_icache/hdl/tlb_emul.sv:45: Unsupported: SystemVerilog 2005 reserved word not implemented: 'randomize'\n      ok = randomize(rnd) with {rnd > 0; rnd <= 100;};\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/tb_cva6_icache/hdl/tlb_emul.sv:45: Unsupported: SystemVerilog 2005 reserved word not implemented: 'with'\n      ok = randomize(rnd) with {rnd > 0; rnd <= 100;};\n                          ^~~~\n%Error: Exiting due to 11 error(s)\n"
module tlb_emul import ariane_pkg::*; import wt_cache_pkg::*; #(
  parameter TlbRandHitRate = 10
) (
  input logic            clk_i,
  input logic            rst_ni,

  input logic            tlb_rand_en_i,
  input logic            exception_en_i,
  input logic [63:0]     tlb_offset_i,


  input  icache_areq_o_t req_i,
  output icache_areq_i_t req_o
);

logic tlb_ready_d, tlb_ready_q;

always_ff @(posedge clk_i or negedge rst_ni) begin : p_tlb_rand
  automatic bit ok  = 0;
  automatic int rnd = 0;

  assert(TlbRandHitRate<=100 && TlbRandHitRate>=0) else
    $fatal("TlbRandHitRate must be a percentage");

  if(~rst_ni) begin
    tlb_ready_q <= '0;
  end else begin
    if (tlb_rand_en_i) begin
      ok = randomize(rnd) with {rnd > 0; rnd <= 100;};
      if(rnd < TlbRandHitRate) begin
        tlb_ready_q = '1;
      end else
        tlb_ready_q = '0;
    end else begin
      tlb_ready_q = '1;
    end
  end
end


always_comb begin : proc_tlb
  req_o.fetch_valid     = '0;
  req_o.fetch_paddr     = '0;
  req_o.fetch_exception = '0;

  if (req_i.fetch_req && tlb_ready_q) begin
    req_o.fetch_valid = 1'b1;
    req_o.fetch_paddr = req_i.fetch_vaddr + tlb_offset_i;
  end
end

endmodule
module tlb_emul import ariane_pkg::*;
 import wt_cache_pkg::*; #(
  parameter TlbRandHitRate = 10
) (
  input logic            clk_i,
  input logic            rst_ni,

  input logic            tlb_rand_en_i,
  input logic            exception_en_i,
  input logic [63:0]     tlb_offset_i,


  input  icache_areq_o_t req_i,
  output icache_areq_i_t req_o
);

logic tlb_ready_d, tlb_ready_q;

always_ff @(posedge clk_i or negedge rst_ni) begin : p_tlb_rand
  automatic bit ok  = 0;
  automatic int rnd = 0;

  assert(TlbRandHitRate<=100 && TlbRandHitRate>=0) else
    $fatal("TlbRandHitRate must be a percentage");

  if(~rst_ni) begin
    tlb_ready_q <= '0;
  end else begin
    if (tlb_rand_en_i) begin
      ok = randomize(rnd) with {rnd > 0; rnd <= 100;};
      if(rnd < TlbRandHitRate) begin
        tlb_ready_q = '1;
      end else
        tlb_ready_q = '0;
    end else begin
      tlb_ready_q = '1;
    end
  end
end


always_comb begin : proc_tlb
  req_o.fetch_valid     = '0;
  req_o.fetch_paddr     = '0;
  req_o.fetch_exception = '0;

  if (req_i.fetch_req && tlb_ready_q) begin
    req_o.fetch_valid = 1'b1;
    req_o.fetch_paddr = req_i.fetch_vaddr + tlb_offset_i;
  end
end

endmodule