data/full_repos/permissive/435516446/MIPS/OpcodeBasedMux2X1.v
1: b'%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/OpcodeBasedMux2X1.v:34: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'next_pc\' generates 32 bits.\n                                                                                : ... In instance OpcodeBasedMux2X1\n  write_data_out = next_pc;\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module OpcodeBasedMux2X1(
	 input RegWrite_from_controlUnit,
    input [5:0] opcode,
    input [31:0] next_pc,
    input [5:0] write_reg,
    input [5:0] write_data,
    output reg [5:0] write_reg_out,
    output reg [5:0] write_data_out
    );
always @(RegWrite_from_controlUnit) begin
if (RegWrite_from_controlUnit) begin
	if (opcode == 6'b010001) begin
		write_reg_out = 31;
		write_data_out = next_pc;
	end
	else begin
		write_reg_out = write_reg;
		write_data_out = write_data;
	end
end
end

endmodule
module OpcodeBasedMux2X1(
	 input RegWrite_from_controlUnit,
    input [5:0] opcode,
    input [31:0] next_pc,
    input [5:0] write_reg,
    input [5:0] write_data,
    output reg [5:0] write_reg_out,
    output reg [5:0] write_data_out
    );

always @(RegWrite_from_controlUnit) begin
if (RegWrite_from_controlUnit) begin
	if (opcode == 6'b010001) begin
		write_reg_out = 31;
		write_data_out = next_pc;
	end
	else begin
		write_reg_out = write_reg;
		write_data_out = write_data;
	end
end
end

endmodule