data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/sim_single_ram_asyn.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/sim_single_ram_asyn.v:41: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/sim_single_ram_asyn.v:46: Unsupported: Ignoring delay on this delayed statement.\n    #100 we = 1;\n    ^\n%Error: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/sim_single_ram_asyn.v:48: syntax error, unexpected \'@\'\n       @(negedge clk) begin\n       ^\n%Error: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/sim_single_ram_asyn.v:54: syntax error, unexpected \'#\'\n    #100 we = 0;\n    ^\n%Error: data/full_repos/permissive/426072575/labs/lab14_memory/codes/RAM/sim_single_ram_asyn.v:56: syntax error, unexpected \'@\'\n        @(negedge clk) begin\n        ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sim_single_ram_asyn(
);
reg clk;
reg [7:0] address;
wire [7:0] data;
reg [7:0] dataIn;


reg we;

assign data = (we == 1) ? dataIn : 8'dz;

initial begin
    clk = 0;
    address = 0;
    dataIn = 0;
    we = 0;
end

always #5 clk = ~clk;

integer i;
initial begin

    #100 we = 1;
    for (i = 0; i < 256; i = i + 1) begin
       @(negedge clk) begin
           address = i;
           dataIn = dataIn + 1;
       end
    end 

    #100 we = 0;
    for (i = 0; i < 256; i = i + 1) begin
        @(negedge clk) begin
            address = i;
        end
    end

end
single_ram_sy my_single_ram_sy(.clk(clk), .address(address), .we(we), .data(data));



endmodule
module sim_single_ram_asyn(
);

reg clk;
reg [7:0] address;
wire [7:0] data;
reg [7:0] dataIn;


reg we;

assign data = (we == 1) ? dataIn : 8'dz;

initial begin
    clk = 0;
    address = 0;
    dataIn = 0;
    we = 0;
end

always #5 clk = ~clk;

integer i;
initial begin

    #100 we = 1;
    for (i = 0; i < 256; i = i + 1) begin
       @(negedge clk) begin
           address = i;
           dataIn = dataIn + 1;
       end
    end 

    #100 we = 0;
    for (i = 0; i < 256; i = i + 1) begin
        @(negedge clk) begin
            address = i;
        end
    end

end
single_ram_sy my_single_ram_sy(.clk(clk), .address(address), .we(we), .data(data));



endmodule