data/full_repos/permissive/43856783/j1_soc/hdl/PWM/PWM_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/PWM/PWM_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n        repeat ( 4 ) #5 clk = ~clk ;\n                     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/PWM/PWM_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n        forever #5 clk = ~clk ;\n                ^\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/PWM/PWM_tb.v:8: Cannot find file containing module: \'PWM\'\n    PWM dut (\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/43856783/j1_soc/hdl/PWM,data/full_repos/permissive/43856783/PWM\n             data/full_repos/permissive/43856783/j1_soc/hdl/PWM,data/full_repos/permissive/43856783/PWM.v\n             data/full_repos/permissive/43856783/j1_soc/hdl/PWM,data/full_repos/permissive/43856783/PWM.sv\n             PWM\n             PWM.v\n             PWM.sv\n             obj_dir/PWM\n             obj_dir/PWM.v\n             obj_dir/PWM.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module PWM_tb (
    ) ;

    reg clk , rst_n ;
    reg [9:0] number ;
    wire pwm ;

    PWM dut (
        .clk ( clk ) ,
        .rst_n ( rst_n ) ,
        .number ( number ) ,
        .pwm  ( pwm ) 
        ) ;

    initial begin
        clk = 0 ;
        rst_n = 0 ;
        repeat ( 4 ) #5 clk = ~clk ;
        rst_n = 1 ;
        forever #5 clk = ~clk ;
    end

    initial begin
        number = 10'b10_000_000 ;
    end 

endmodule
module PWM_tb (
    ) ;


    reg clk , rst_n ;
    reg [9:0] number ;
    wire pwm ;

    PWM dut (
        .clk ( clk ) ,
        .rst_n ( rst_n ) ,
        .number ( number ) ,
        .pwm  ( pwm ) 
        ) ;

    initial begin
        clk = 0 ;
        rst_n = 0 ;
        repeat ( 4 ) #5 clk = ~clk ;
        rst_n = 1 ;
        forever #5 clk = ~clk ;
    end

    initial begin
        number = 10'b10_000_000 ;
    end 

endmodule