data/full_repos/permissive/431550602/sim_1/tb_uartRX.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/431550602/sim_1/tb_uartRX.v:30: Unsupported: Ignoring delay on this delayed statement.\n always begin clk <= ~clk; #5; end\n                           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/431550602/sim_1/tb_uartRX.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/431550602/sim_1/tb_uartRX.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #one_bit_time;      \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/431550602/sim_1/tb_uartRX.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #one_bit_time;      \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/431550602/sim_1/tb_uartRX.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #one_bit_time;      \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/431550602/sim_1/tb_uartRX.v:42: Unsupported: Ignoring delay on this delayed statement.\n  #one_bit_time;      \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/431550602/sim_1/tb_uartRX.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #one_bit_time;      \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/431550602/sim_1/tb_uartRX.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #one_bit_time;      \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/431550602/sim_1/tb_uartRX.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #one_bit_time;      \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/431550602/sim_1/tb_uartRX.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #one_bit_time;      \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/431550602/sim_1/tb_uartRX.v:52: Unsupported: Ignoring delay on this delayed statement.\n  #one_bit_time;      \n  ^\n%Error: data/full_repos/permissive/431550602/sim_1/tb_uartRX.v:54: Unsupported: wait statements\n  wait(rx_done);  \n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/431550602/sim_1/tb_uartRX.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/431550602/sim_1/tb_uartRX.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #one_bit_time;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/431550602/sim_1/tb_uartRX.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #one_bit_time;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/431550602/sim_1/tb_uartRX.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #one_bit_time;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/431550602/sim_1/tb_uartRX.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #one_bit_time;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/431550602/sim_1/tb_uartRX.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #one_bit_time;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/431550602/sim_1/tb_uartRX.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #one_bit_time;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/431550602/sim_1/tb_uartRX.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #one_bit_time;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/431550602/sim_1/tb_uartRX.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #one_bit_time;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/431550602/sim_1/tb_uartRX.v:74: Unsupported: Ignoring delay on this delayed statement.\n  #one_bit_time;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/431550602/sim_1/tb_uartRX.v:76: Unsupported: Ignoring delay on this delayed statement.\n  #one_bit_time;\n  ^\n%Error: data/full_repos/permissive/431550602/sim_1/tb_uartRX.v:77: Unsupported: wait statements\n  wait(rx_done);\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/431550602/sim_1/tb_uartRX.v:78: Unsupported: Ignoring delay on this delayed statement.\n  #40;\n  ^\n%Error: Exiting due to 2 error(s), 23 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_uartRX;

    reg clk; 
    reg reset;
    reg rx;
    wire [7:0] r_data;
    wire rx_done;
    wire baud_tick;
	
	localparam baud_gen_divisior = 54,
                   data_bits = 8,
                   stop_ticks = 16,
	           bit_ticks = 16;
			   
	localparam one_bit_time = 8680;
	
	uart_baudrate_generator #(.divisior(baud_gen_divisior)) baud_gen(clk, reset, baud_tick);
	
	uart_rx #(.DBIT(data_bits), .S_TICK_LIM(bit_ticks), .STOP_BITS_LIM(stop_ticks)) 
	uut(.clk(clk), .reset(reset), .rx(rx), .s_tick(baud_tick), .rx_done_tick(rx_done), .data_out(r_data));
	
	initial begin	
		clk    = 1'b0;       
                reset  = 1'b0;
                rx     = 1'b1;	
	end
	
	always begin clk <= ~clk; #5; end
	
	always begin
	
		#50;
		rx = 1'b0;
		#one_bit_time;      
		rx = 1'b0;
		#one_bit_time;      
		rx = 1'b1;
		#one_bit_time;      
		rx = 1'b0;
		#one_bit_time;      
		rx = 1'b0;
		#one_bit_time;      
		rx = 1'b1;
		#one_bit_time;      
		rx = 1'b1;
		#one_bit_time;      
		rx = 1'b0;
		#one_bit_time;      
		rx = 1'b0;
		#one_bit_time;      
		rx = 1'b1;
		wait(rx_done);		
		#40;
		
		rx = 1'b0;
		#one_bit_time;
		rx = 1'b1;
		#one_bit_time;
		rx = 1'b0;
		#one_bit_time;
		rx = 1'b1;
		#one_bit_time;
		rx = 1'b1;
		#one_bit_time;
		rx = 1'b0;
		#one_bit_time;
		rx = 1'b1;
		#one_bit_time;
		rx = 1'b1;
		#one_bit_time;
		rx = 1'b1;
		#one_bit_time;
		rx = 1'b1;
		#one_bit_time;
		wait(rx_done);
		#40;
		
		$display("Simulasyon Tamamlandi");
		$finish;

	end
	
	

endmodule
module tb_uartRX;


    reg clk; 
    reg reset;
    reg rx;
    wire [7:0] r_data;
    wire rx_done;
    wire baud_tick;
	
	localparam baud_gen_divisior = 54,
                   data_bits = 8,
                   stop_ticks = 16,
	           bit_ticks = 16;
			   
	localparam one_bit_time = 8680;
	
	uart_baudrate_generator #(.divisior(baud_gen_divisior)) baud_gen(clk, reset, baud_tick);
	
	uart_rx #(.DBIT(data_bits), .S_TICK_LIM(bit_ticks), .STOP_BITS_LIM(stop_ticks)) 
	uut(.clk(clk), .reset(reset), .rx(rx), .s_tick(baud_tick), .rx_done_tick(rx_done), .data_out(r_data));
	
	initial begin	
		clk    = 1'b0;       
                reset  = 1'b0;
                rx     = 1'b1;	
	end
	
	always begin clk <= ~clk; #5; end
	
	always begin
	
		#50;
		rx = 1'b0;
		#one_bit_time;      
		rx = 1'b0;
		#one_bit_time;      
		rx = 1'b1;
		#one_bit_time;      
		rx = 1'b0;
		#one_bit_time;      
		rx = 1'b0;
		#one_bit_time;      
		rx = 1'b1;
		#one_bit_time;      
		rx = 1'b1;
		#one_bit_time;      
		rx = 1'b0;
		#one_bit_time;      
		rx = 1'b0;
		#one_bit_time;      
		rx = 1'b1;
		wait(rx_done);		
		#40;
		
		rx = 1'b0;
		#one_bit_time;
		rx = 1'b1;
		#one_bit_time;
		rx = 1'b0;
		#one_bit_time;
		rx = 1'b1;
		#one_bit_time;
		rx = 1'b1;
		#one_bit_time;
		rx = 1'b0;
		#one_bit_time;
		rx = 1'b1;
		#one_bit_time;
		rx = 1'b1;
		#one_bit_time;
		rx = 1'b1;
		#one_bit_time;
		rx = 1'b1;
		#one_bit_time;
		wait(rx_done);
		#40;
		
		$display("Simulasyon Tamamlandi");
		$finish;

	end
	
	

endmodule