data/full_repos/permissive/500326609/a6/pc.v
data/verilator_xmls/11b792ba-0266-4cf3-8dd5-9df59465d8da.xml
module PC(
    input [31:0] PC,
    input [31:0] imm,
    input [2:0] branch,
    input condition_out,
	  input [31:0] alu_out,
	  output [31:0] PC_plus4,
    output [31:0] PC_next
    );

wire [31:0] PC_branch;

assign PC_branch = PC + imm;
assign PC_plus4 = PC + 32'd4;

assign PC_next = (branch == 3'b001 && (~condition_out) ) ? PC_branch :
                 (branch == 3'b001 && condition_out ) ? PC_plus4 :
					       (branch == 3'b010 && condition_out ) ? PC_branch :
                 (branch == 3'b010 && (~condition_out) ) ? PC_plus4 :
					       (branch == 3'b011) ?  PC_branch :
					       (branch == 3'b100) ? (alu_out & 32'hFFFFFFFE) :PC_plus4;

endmodule
module PC(
    input [31:0] PC,
    input [31:0] imm,
    input [2:0] branch,
    input condition_out,
	  input [31:0] alu_out,
	  output [31:0] PC_plus4,
    output [31:0] PC_next
    );


wire [31:0] PC_branch;

assign PC_branch = PC + imm;
assign PC_plus4 = PC + 32'd4;

assign PC_next = (branch == 3'b001 && (~condition_out) ) ? PC_branch :
                 (branch == 3'b001 && condition_out ) ? PC_plus4 :
					       (branch == 3'b010 && condition_out ) ? PC_branch :
                 (branch == 3'b010 && (~condition_out) ) ? PC_plus4 :
					       (branch == 3'b011) ?  PC_branch :
					       (branch == 3'b100) ? (alu_out & 32'hFFFFFFFE) :PC_plus4;

endmodule