data/full_repos/permissive/463549945/Problem_sets/Circuits/Sequential Logic/Counters/4-digit decimal counter.v
1: b'%Error: Cannot find file containing module: Logic/Counters,data/full_repos/permissive/463549945\n        ... Looked in:\n             data/full_repos/permissive/463549945/Problem_sets/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/463549945\n             data/full_repos/permissive/463549945/Problem_sets/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/463549945.v\n             data/full_repos/permissive/463549945/Problem_sets/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/463549945.sv\n             Logic/Counters,data/full_repos/permissive/463549945\n             Logic/Counters,data/full_repos/permissive/463549945.v\n             Logic/Counters,data/full_repos/permissive/463549945.sv\n             obj_dir/Logic/Counters,data/full_repos/permissive/463549945\n             obj_dir/Logic/Counters,data/full_repos/permissive/463549945.v\n             obj_dir/Logic/Counters,data/full_repos/permissive/463549945.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/463549945/Problem_sets/Circuits/Sequential\n%Error: Cannot find file containing module: Logic/Counters/4-digit\n%Error: Cannot find file containing module: decimal\n%Error: Cannot find file containing module: counter.v\n%Error: Exiting due to 5 error(s)\n'
module top_module (
    input clk,
    input reset,
    output [3:1] ena,
    output [15:0] q);

    always @(posedge clk) begin
        if (reset) begin
            ena <= 3'b0;
        end else begin



            if (q[3:0] == 4'd8) begin
                ena[1] <= 1'b1;
            end else begin
                ena[1] <= 1'b0;
            end

            if (q[3:0] == 4'd8 && q[7:4] == 4'd9) begin
                ena[2] <= 1'b1;
            end else begin
                ena[2] <= 1'b0;
            end

            if (q[3:0]==4'd8 && q[7:4]==4'd9 && q[11:8]==4'd9) begin
                ena[3] <= 1'b1;
            end else begin
                ena[3] <= 1'b0;
            end
        end
    end

    decade_cnt cnt0 (.clk(clk), 
                     .reset(reset), 
                     .enable(1'b1), 
                     .q(q[3:0]));

    decade_cnt cnt1 (.clk(clk), 
                     .reset(reset), 
                     .enable(ena[1]), 
                     .q(q[7:4]));

    decade_cnt cnt2 (.clk(clk), 
                     .reset(reset), 
                     .enable(ena[2]), 
                     .q(q[11:8]));

    decade_cnt cnt3 (.clk(clk), 
                     .reset(reset), 
                     .enable(ena[3]), 
                     .q(q[15:12]));

endmodule
module top_module (
    input clk,
    input reset,
    output [3:1] ena,
    output [15:0] q);


    always @(posedge clk) begin
        if (reset) begin
            ena <= 3'b0;
        end else begin



            if (q[3:0] == 4'd8) begin
                ena[1] <= 1'b1;
            end else begin
                ena[1] <= 1'b0;
            end

            if (q[3:0] == 4'd8 && q[7:4] == 4'd9) begin
                ena[2] <= 1'b1;
            end else begin
                ena[2] <= 1'b0;
            end

            if (q[3:0]==4'd8 && q[7:4]==4'd9 && q[11:8]==4'd9) begin
                ena[3] <= 1'b1;
            end else begin
                ena[3] <= 1'b0;
            end
        end
    end

    decade_cnt cnt0 (.clk(clk), 
                     .reset(reset), 
                     .enable(1'b1), 
                     .q(q[3:0]));

    decade_cnt cnt1 (.clk(clk), 
                     .reset(reset), 
                     .enable(ena[1]), 
                     .q(q[7:4]));

    decade_cnt cnt2 (.clk(clk), 
                     .reset(reset), 
                     .enable(ena[2]), 
                     .q(q[11:8]));

    decade_cnt cnt3 (.clk(clk), 
                     .reset(reset), 
                     .enable(ena[3]), 
                     .q(q[15:12]));

endmodule