data/full_repos/permissive/493019833/test/testcase/firrtl/Cvt/reference/Cvt.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/Cvt/reference/Cvt.v:133: Operator COND expects 10 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 8 bits.\n                                                                                                 : ... In instance Cvt.u_pad_16\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/Cvt/reference/Cvt.v:112: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                 : ... In instance Cvt.s_pad_4\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/Cvt/reference/Cvt.v:112: Operator COND expects 10 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 8 bits.\n                                                                                                 : ... In instance Cvt.s_pad_12\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Error: Exiting due to 3 warning(s)\n'
module SUB_SIGNED(y, a, b);
    parameter width = 4;
    output [width:0] y;
    input [width-1:0] a;
    input [width-1:0] b;
    assign y = $signed(a) - $signed(b);
endmodule
module SUB_SIGNED(y, a, b);

    parameter width = 4;
    output [width:0] y;
    input [width-1:0] a;
    input [width-1:0] b;
    assign y = $signed(a) - $signed(b);
endmodule