data/full_repos/permissive/450962776/processor/src/test_bench_data_memory.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/450962776/processor/src/test_bench_data_memory.v:13: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/450962776/processor/src/test_bench_data_memory.v:16: Unsupported or unknown PLI call: $monitor\n$monitor("access_addr=%32b,mem_read=%1b,mem_write=%1b,read_data=%32b",\n^~~~~~~~\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_bench_data_memory();
 reg clk;
 reg [31:0]   access_addr;
 reg [31:0]   write_data;
 reg mem_write;
 reg mem_read;
 wire [31:0]   read_data;
 Data_Memory ahmet(clk,access_addr,write_data,mem_write, mem_read,read_data);
 initial begin
 $readmemb("data.txt",ahmet.memory);
 access_addr=32'b00000000000000000000000000000011; mem_read=1'b1; mem_write=1'b0;
#`DELAY;
 end
 initial begin
$monitor("access_addr=%32b,mem_read=%1b,mem_write=%1b,read_data=%32b",
					access_addr,mem_read,mem_write,read_data);


end
endmodule
module test_bench_data_memory();

 reg clk;
 reg [31:0]   access_addr;
 reg [31:0]   write_data;
 reg mem_write;
 reg mem_read;
 wire [31:0]   read_data;
 Data_Memory ahmet(clk,access_addr,write_data,mem_write, mem_read,read_data);
 initial begin
 $readmemb("data.txt",ahmet.memory);
 access_addr=32'b00000000000000000000000000000011; mem_read=1'b1; mem_write=1'b0;
#`DELAY;
 end
 initial begin
$monitor("access_addr=%32b,mem_read=%1b,mem_write=%1b,read_data=%32b",
					access_addr,mem_read,mem_write,read_data);


end
endmodule