data/full_repos/permissive/496096937/verilog/rtl/tdc.v
1: b"%Error: data/full_repos/permissive/496096937/verilog/rtl/tdc.v:21: Can't resolve module reference: 'sky130_fd_sc_hd__inv_1'\n        sky130_fd_sc_hd__inv_1 u_inv(\n                               ^~~~~\n%Error: Exiting due to 1 error(s)\n"
module tdc(
`ifdef USE_POWER_PINS
	inout vccd1,
	inout vssd1,
`endif
    input          start,
    input          stop,
    input          invstop,
    output         tail,
    output  [63:0] dq
);

wire latch = stop ^ invstop;
wire [64:0] imm;
assign imm[0] = start;
assign tail = imm[64];

genvar gi;
generate
    for(gi=0;gi<64;gi=gi+1) begin : gen_tdc    
        sky130_fd_sc_hd__inv_1 u_inv(
            .Y (imm[gi+1]),
            .A (imm[gi]  )
        );
        sky130_fd_sc_hd__dlxtp_1 u_dlxtp(
            .D    (imm[gi+1]),
            .Q    (dq[gi]   ),
            .GATE (latch    )
        );
    end
endgenerate

endmodule
module tdc(
`ifdef USE_POWER_PINS
	inout vccd1,
	inout vssd1,
`endif
    input          start,
    input          stop,
    input          invstop,
    output         tail,
    output  [63:0] dq
);


wire latch = stop ^ invstop;
wire [64:0] imm;
assign imm[0] = start;
assign tail = imm[64];

genvar gi;
generate
    for(gi=0;gi<64;gi=gi+1) begin : gen_tdc    
        sky130_fd_sc_hd__inv_1 u_inv(
            .Y (imm[gi+1]),
            .A (imm[gi]  )
        );
        sky130_fd_sc_hd__dlxtp_1 u_dlxtp(
            .D    (imm[gi+1]),
            .Q    (dq[gi]   ),
            .GATE (latch    )
        );
    end
endgenerate

endmodule