data/full_repos/permissive/449689971/SYSTOLIC_ARRAY/PE.v
1: b'%Error: data/full_repos/permissive/449689971/SYSTOLIC_ARRAY/PE.v:31: Cannot find file containing module: \'MUL_APP\'\n MUL_APP MUL_APP(weight_w,input_w,mul_w);\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/449689971/SYSTOLIC_ARRAY,data/full_repos/permissive/449689971/MUL_APP\n             data/full_repos/permissive/449689971/SYSTOLIC_ARRAY,data/full_repos/permissive/449689971/MUL_APP.v\n             data/full_repos/permissive/449689971/SYSTOLIC_ARRAY,data/full_repos/permissive/449689971/MUL_APP.sv\n             MUL_APP\n             MUL_APP.v\n             MUL_APP.sv\n             obj_dir/MUL_APP\n             obj_dir/MUL_APP.v\n             obj_dir/MUL_APP.sv\n%Warning-WIDTH: data/full_repos/permissive/449689971/SYSTOLIC_ARRAY/PE.v:38: Operator ADD expects 35 bits on the RHS, but RHS\'s VARREF \'mul_w\' generates 32 bits.\n                                                                           : ... In instance PE\n   acc_w=acc_r+mul_w;\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module PE
		(
		clk, 
		reset_n,
		weight_w,
		input_w,
		
		weight_r,
		input_r,
		acc_r
		);


    input 						clk; 
	input 						reset_n;
	input signed        [15:0] 	weight_w;
	input signed 		[15:0]	input_w;

	reg signed  		[34:0]	acc_w;
	wire signed			[31:0]	mul_w;
	
	MUL_APP MUL_APP(weight_w,input_w,mul_w);


	always @(*)
		begin

	always @(posedge clk)
		begin
			if (reset_n==1'b0)
				begin
					input_r<=16'd0;
					weight_r<=16'd0;
					acc_r<=35'd0;
				end
			else
				begin
					input_r<=input_w;
					weight_r<=weight_w;
					acc_r<=acc_w;
				end
		end	

	
endmodule
module PE
		(
		clk, 
		reset_n,
		weight_w,
		input_w,
		
		weight_r,
		input_r,
		acc_r
		);



    input 						clk; 
	input 						reset_n;
	input signed        [15:0] 	weight_w;
	input signed 		[15:0]	input_w;

	reg signed  		[34:0]	acc_w;
	wire signed			[31:0]	mul_w;
	
	MUL_APP MUL_APP(weight_w,input_w,mul_w);


	always @(*)
		begin

	always @(posedge clk)
		begin
			if (reset_n==1'b0)
				begin
					input_r<=16'd0;
					weight_r<=16'd0;
					acc_r<=35'd0;
				end
			else
				begin
					input_r<=input_w;
					weight_r<=weight_w;
					acc_r<=acc_w;
				end
		end	

	
endmodule