data/full_repos/permissive/447223480/05_mmio/runner.v
1: b'%Error: data/full_repos/permissive/447223480/05_mmio/runner.v:40: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("result.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/447223480/05_mmio/runner.v:41: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, runner);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/447223480/05_mmio/runner.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/447223480/05_mmio/runner.v:51: Unsupported: Ignoring delay on this delayed statement.\n  #1000000000\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/447223480/05_mmio/runner.v:55: Unsupported: Ignoring delay on this delayed statement.\n always #50 begin\n        ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module runner();
	reg clock;
	reg reset;

	wire [31:0] paddr, pread, pwrite;
	wire pread_req, pwrite_req;
	wire [2:0] psize;

	cpu CPU(
		.clock(clock), .reset(reset),
		.paddr(paddr), .pread(pread), .pwrite(pwrite),
		.pread_req(pread_req), .pwrite_req(pwrite_req), .psize(psize)
	);

	assign pread = 32'b0;
	reg endsim;

	always @(posedge clock) begin
		if (reset) begin
			endsim <= 1'b0;
		end else begin
			if (pwrite_req) begin
				if (paddr == 32'hc0000000) begin
					$display("%08x", pwrite);
				end else if (paddr == 32'hc0000004) begin
					endsim <= 1'b1;
				end
			end
			if (endsim) begin
				$finish;
			end
		end
	end

	reg [15:0] mem_temp[0:1023];
	integer i;
	initial begin
		$dumpfile("result.vcd");
		$dumpvars(0, runner);
		$readmemb("prog.txt", mem_temp);
		for (i = 0; i < 512; i = i + 1) begin
			CPU.mem.mem_array[i] <= { mem_temp[i * 2 + 1], mem_temp[i * 2] };
		end

		clock <= 1'b0;
		reset <= 1'b1;
		#100
		reset <= 1'b0;
		#1000000000
		$finish;
	end

	always #50 begin
		clock <= ~clock;
	end

endmodule
module runner();

	reg clock;
	reg reset;

	wire [31:0] paddr, pread, pwrite;
	wire pread_req, pwrite_req;
	wire [2:0] psize;

	cpu CPU(
		.clock(clock), .reset(reset),
		.paddr(paddr), .pread(pread), .pwrite(pwrite),
		.pread_req(pread_req), .pwrite_req(pwrite_req), .psize(psize)
	);

	assign pread = 32'b0;
	reg endsim;

	always @(posedge clock) begin
		if (reset) begin
			endsim <= 1'b0;
		end else begin
			if (pwrite_req) begin
				if (paddr == 32'hc0000000) begin
					$display("%08x", pwrite);
				end else if (paddr == 32'hc0000004) begin
					endsim <= 1'b1;
				end
			end
			if (endsim) begin
				$finish;
			end
		end
	end

	reg [15:0] mem_temp[0:1023];
	integer i;
	initial begin
		$dumpfile("result.vcd");
		$dumpvars(0, runner);
		$readmemb("prog.txt", mem_temp);
		for (i = 0; i < 512; i = i + 1) begin
			CPU.mem.mem_array[i] <= { mem_temp[i * 2 + 1], mem_temp[i * 2] };
		end

		clock <= 1'b0;
		reset <= 1'b1;
		#100
		reset <= 1'b0;
		#1000000000
		$finish;
	end

	always #50 begin
		clock <= ~clock;
	end

endmodule