data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/rtlwartermark.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/rtlwartermark.v:59: Cannot find file containing module: 'fflopx'\nfflopx #(1)     ppin (clk,rst,dtvl,crrdtvl);\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/fflopx\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/fflopx.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/fflopx.sv\n             fflopx\n             fflopx.v\n             fflopx.sv\n             obj_dir/fflopx\n             obj_dir/fflopx.v\n             obj_dir/fflopx.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/rtlwartermark.v:74: Cannot find file containing module: 'watermarkx'\nwatermarkx #(BW,1)  wmmin\n^~~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/rtlwartermark.v:91: Cannot find file containing module: 'watermarkx'\nwatermarkx #(BW,0)  wmmax\n^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module rtlwartermark
    (
     clk,
     rst,
     dtvl,
     data,

     upact,
     upen,
     upa,
     upws,
     uprs,
     updi,
     updo,
     uprdy
     );

parameter BW = 32;



input           clk;
input           rst;
input           dtvl;
input [BW-1:0]  data;

input           upact;
input           upen;
input [1:0]     upa;
input           upws;
input           uprs;
input [BW-1:0]  updi;
output [BW-1:0] updo;
output          uprdy;










wire            crrdtvl;
fflopx #(1)     ppin (clk,rst,dtvl,crrdtvl);

wire            crrpen;
wire [BW-1:0]   crrpdo;
reg [BW-1:0]    crrdata;
always @(posedge clk)
    begin
    if(rst) crrdata <= {BW{1'b0}};
    else if(dtvl) crrdata <= data;
    end
assign crrpdo = crrpen ? crrdata : {BW{1'b0}};


wire            minpen;
wire [BW-1:0]   minpdo;
watermarkx #(BW,1)  wmmin
    (
     .clk       (clk),
     .rst      (rst),
     .dtvl      (crrdtvl),
     .alarm     (crrdata),
     .upact     (upact),
     .upen      (minpen),
     .upws      (upws),
     .updi      (updi[BW-1:0]),
     .updo      (minpdo),
     .lalarm    ()
     );


wire            maxpen;
wire [BW-1:0]   maxpdo;
watermarkx #(BW,0)  wmmax
    (
     .clk       (clk),
     .rst      (rst),
     .dtvl      (crrdtvl),
     .alarm     (crrdata),
     .upact     (upact),
     .upen      (maxpen),
     .upws      (upws),
     .updi      (updi[BW-1:0]),
     .updo      (maxpdo),
     .lalarm    ()
     );

wire            uprdy;
assign          uprdy = upen & (upws | uprs);
wire [BW-1:0]   updo;
assign          updo = crrpdo | minpdo | maxpdo;
assign          minpen = upen & (upa[1:0] == 2'b00);
assign          maxpen = upen & (upa[1:0] == 2'b01);
assign          crrpen = upen & (upa[1:0] == 2'b10);
 
endmodule
module rtlwartermark
    (
     clk,
     rst,
     dtvl,
     data,

     upact,
     upen,
     upa,
     upws,
     uprs,
     updi,
     updo,
     uprdy
     );


parameter BW = 32;



input           clk;
input           rst;
input           dtvl;
input [BW-1:0]  data;

input           upact;
input           upen;
input [1:0]     upa;
input           upws;
input           uprs;
input [BW-1:0]  updi;
output [BW-1:0] updo;
output          uprdy;










wire            crrdtvl;
fflopx #(1)     ppin (clk,rst,dtvl,crrdtvl);

wire            crrpen;
wire [BW-1:0]   crrpdo;
reg [BW-1:0]    crrdata;
always @(posedge clk)
    begin
    if(rst) crrdata <= {BW{1'b0}};
    else if(dtvl) crrdata <= data;
    end
assign crrpdo = crrpen ? crrdata : {BW{1'b0}};


wire            minpen;
wire [BW-1:0]   minpdo;
watermarkx #(BW,1)  wmmin
    (
     .clk       (clk),
     .rst      (rst),
     .dtvl      (crrdtvl),
     .alarm     (crrdata),
     .upact     (upact),
     .upen      (minpen),
     .upws      (upws),
     .updi      (updi[BW-1:0]),
     .updo      (minpdo),
     .lalarm    ()
     );


wire            maxpen;
wire [BW-1:0]   maxpdo;
watermarkx #(BW,0)  wmmax
    (
     .clk       (clk),
     .rst      (rst),
     .dtvl      (crrdtvl),
     .alarm     (crrdata),
     .upact     (upact),
     .upen      (maxpen),
     .upws      (upws),
     .updi      (updi[BW-1:0]),
     .updo      (maxpdo),
     .lalarm    ()
     );

wire            uprdy;
assign          uprdy = upen & (upws | uprs);
wire [BW-1:0]   updo;
assign          updo = crrpdo | minpdo | maxpdo;
assign          minpen = upen & (upa[1:0] == 2'b00);
assign          maxpen = upen & (upa[1:0] == 2'b01);
assign          crrpen = upen & (upa[1:0] == 2'b10);
 
endmodule