data/full_repos/permissive/494664634/AxisRRArbiter/src/hdl/AxisRRArbiter.v
data/verilator_xmls/77276ae1-e71d-4168-a1cb-6afecbb96e26.xml
module AxisRRArbiter(

  (*
    X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clock CLK", X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF S00_AXIS:S01_AXIS:S02_AXIS:S03_AXIS:M_AXIS"
     *)
  input         clock,

  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 reset RST", X_INTERFACE_PARAMETER = "POLARITY ACTIVE_HIGH" *)
  input         reset,

  (*
    X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S00_AXIS TDATA", X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXIS, CLK_DOMAIN clock"
     *)
  input  [31:0] s00_axis_tdata,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S00_AXIS TVALID" *)
  input         s00_axis_tvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S00_AXIS TREADY" *)
  output        s00_axis_tready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S00_AXIS TLAST" *)
  input         s00_axis_tlast,

  (*
    X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S01_AXIS TDATA", X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S01_AXIS, CLK_DOMAIN clock"
     *)
  input  [31:0] s01_axis_tdata,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S01_AXIS TVALID" *)
  input         s01_axis_tvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S01_AXIS TREADY" *)
  output        s01_axis_tready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S01_AXIS TLAST" *)
  input         s01_axis_tlast,

  (*
    X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S02_AXIS TDATA", X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S02_AXIS, CLK_DOMAIN clock"
     *)
  input  [31:0] s02_axis_tdata,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S02_AXIS TVALID" *)
  input         s02_axis_tvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S02_AXIS TREADY" *)
  output        s02_axis_tready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S02_AXIS TLAST" *)
  input         s02_axis_tlast,

  (*
    X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S03_AXIS TDATA", X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S03_AXIS, CLK_DOMAIN clock"
     *)
  input  [31:0] s03_axis_tdata,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S03_AXIS TVALID" *)
  input         s03_axis_tvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S03_AXIS TREADY" *)
  output        s03_axis_tready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S03_AXIS TLAST" *)
  input         s03_axis_tlast,

  (*
    X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA", X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, CLK_DOMAIN clock"
     *)
  output [31:0] m_axis_tdata,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
  output        m_axis_tvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
  input         m_axis_tready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *)
  output        m_axis_tlast
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif
  wire  rr_arbiter_clock;
  wire  rr_arbiter_reset;
  wire [3:0] rr_arbiter_req;
  wire [3:0] rr_arbiter_fin;
  wire [3:0] rr_arbiter_grant;
  wire  rr_arbiter_ready;
  reg  processing_0;
  reg  processing_1;
  reg  processing_2;
  reg  processing_3;
  wire  arb_req_0 = s00_axis_tvalid | processing_0;
  wire  arb_fin_0 = s00_axis_tvalid & s00_axis_tlast & s00_axis_tready;
  wire  arb_req_1 = s01_axis_tvalid | processing_1;
  wire  arb_fin_1 = s01_axis_tvalid & s01_axis_tlast & s01_axis_tready;
  wire  arb_req_2 = s02_axis_tvalid | processing_2;
  wire  arb_fin_2 = s02_axis_tvalid & s02_axis_tlast & s02_axis_tready;
  wire  arb_req_3 = s03_axis_tvalid | processing_3;
  wire  arb_fin_3 = s03_axis_tvalid & s03_axis_tlast & s03_axis_tready;
  wire [1:0] rr_arbiter_req_lo = {arb_req_1,arb_req_0};
  wire [1:0] rr_arbiter_req_hi = {arb_req_3,arb_req_2};
  wire [1:0] rr_arbiter_fin_lo = {arb_fin_1,arb_fin_0};
  wire [1:0] rr_arbiter_fin_hi = {arb_fin_3,arb_fin_2};
  wire  arb_grant_0 = rr_arbiter_grant[0];
  wire  arb_grant_1 = rr_arbiter_grant[1];
  wire  arb_grant_2 = rr_arbiter_grant[2];
  wire  arb_grant_3 = rr_arbiter_grant[3];
  wire [31:0] _GEN_8 = arb_grant_3 ? s03_axis_tdata : 32'h0;
  wire  _GEN_9 = arb_grant_3 & s03_axis_tvalid;
  wire  _GEN_10 = arb_grant_3 & s03_axis_tlast;
  wire [31:0] _GEN_11 = arb_grant_2 ? s02_axis_tdata : _GEN_8;
  wire  _GEN_12 = arb_grant_2 ? s02_axis_tvalid : _GEN_9;
  wire  _GEN_13 = arb_grant_2 ? s02_axis_tlast : _GEN_10;
  wire [31:0] _GEN_14 = arb_grant_1 ? s01_axis_tdata : _GEN_11;
  wire  _GEN_15 = arb_grant_1 ? s01_axis_tvalid : _GEN_12;
  wire  _GEN_16 = arb_grant_1 ? s01_axis_tlast : _GEN_13;
  PacketRRArbiter rr_arbiter (
    .clock(rr_arbiter_clock),
    .reset(rr_arbiter_reset),
    .req(rr_arbiter_req),
    .fin(rr_arbiter_fin),
    .grant(rr_arbiter_grant),
    .ready(rr_arbiter_ready)
  );
  assign s00_axis_tready = rr_arbiter_grant[0];
  assign s01_axis_tready = rr_arbiter_grant[1];
  assign s02_axis_tready = rr_arbiter_grant[2];
  assign s03_axis_tready = rr_arbiter_grant[3];
  assign m_axis_tdata = arb_grant_0 ? s00_axis_tdata : _GEN_14;
  assign m_axis_tvalid = arb_grant_0 ? s00_axis_tvalid : _GEN_15;
  assign m_axis_tlast = arb_grant_0 ? s00_axis_tlast : _GEN_16;
  assign rr_arbiter_clock = clock;
  assign rr_arbiter_reset = reset;
  assign rr_arbiter_req = {rr_arbiter_req_hi,rr_arbiter_req_lo};
  assign rr_arbiter_fin = {rr_arbiter_fin_hi,rr_arbiter_fin_lo};
  assign rr_arbiter_ready = m_axis_tready;
  always @(posedge clock) begin
    if (reset) begin
      processing_0 <= 1'h0;
    end else if (~processing_0 & s00_axis_tvalid) begin
      processing_0 <= ~(s00_axis_tlast & s00_axis_tready);
    end else if (processing_0 & s00_axis_tvalid & s00_axis_tlast & s00_axis_tready) begin
      processing_0 <= 1'h0;
    end
    if (reset) begin
      processing_1 <= 1'h0;
    end else if (~processing_1 & s01_axis_tvalid) begin
      processing_1 <= ~(s01_axis_tlast & s01_axis_tready);
    end else if (processing_1 & s01_axis_tvalid & s01_axis_tlast & s01_axis_tready) begin
      processing_1 <= 1'h0;
    end
    if (reset) begin
      processing_2 <= 1'h0;
    end else if (~processing_2 & s02_axis_tvalid) begin
      processing_2 <= ~(s02_axis_tlast & s02_axis_tready);
    end else if (processing_2 & s02_axis_tvalid & s02_axis_tlast & s02_axis_tready) begin
      processing_2 <= 1'h0;
    end
    if (reset) begin
      processing_3 <= 1'h0;
    end else if (~processing_3 & s03_axis_tvalid) begin
      processing_3 <= ~(s03_axis_tlast & s03_axis_tready);
    end else if (processing_3 & s03_axis_tvalid & s03_axis_tlast & s03_axis_tready) begin
      processing_3 <= 1'h0;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  processing_0 = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  processing_1 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  processing_2 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  processing_3 = _RAND_3[0:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module AxisRRArbiter(

  (*
    X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clock CLK", X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF S00_AXIS:S01_AXIS:S02_AXIS:S03_AXIS:M_AXIS"
     *)
  input         clock,

  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 reset RST", X_INTERFACE_PARAMETER = "POLARITY ACTIVE_HIGH" *)
  input         reset,

  (*
    X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S00_AXIS TDATA", X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXIS, CLK_DOMAIN clock"
     *)
  input  [31:0] s00_axis_tdata,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S00_AXIS TVALID" *)
  input         s00_axis_tvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S00_AXIS TREADY" *)
  output        s00_axis_tready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S00_AXIS TLAST" *)
  input         s00_axis_tlast,

  (*
    X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S01_AXIS TDATA", X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S01_AXIS, CLK_DOMAIN clock"
     *)
  input  [31:0] s01_axis_tdata,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S01_AXIS TVALID" *)
  input         s01_axis_tvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S01_AXIS TREADY" *)
  output        s01_axis_tready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S01_AXIS TLAST" *)
  input         s01_axis_tlast,

  (*
    X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S02_AXIS TDATA", X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S02_AXIS, CLK_DOMAIN clock"
     *)
  input  [31:0] s02_axis_tdata,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S02_AXIS TVALID" *)
  input         s02_axis_tvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S02_AXIS TREADY" *)
  output        s02_axis_tready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S02_AXIS TLAST" *)
  input         s02_axis_tlast,

  (*
    X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S03_AXIS TDATA", X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S03_AXIS, CLK_DOMAIN clock"
     *)
  input  [31:0] s03_axis_tdata,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S03_AXIS TVALID" *)
  input         s03_axis_tvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S03_AXIS TREADY" *)
  output        s03_axis_tready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S03_AXIS TLAST" *)
  input         s03_axis_tlast,

  (*
    X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA", X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, CLK_DOMAIN clock"
     *)
  output [31:0] m_axis_tdata,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
  output        m_axis_tvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
  input         m_axis_tready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TLAST" *)
  output        m_axis_tlast
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif
  wire  rr_arbiter_clock;
  wire  rr_arbiter_reset;
  wire [3:0] rr_arbiter_req;
  wire [3:0] rr_arbiter_fin;
  wire [3:0] rr_arbiter_grant;
  wire  rr_arbiter_ready;
  reg  processing_0;
  reg  processing_1;
  reg  processing_2;
  reg  processing_3;
  wire  arb_req_0 = s00_axis_tvalid | processing_0;
  wire  arb_fin_0 = s00_axis_tvalid & s00_axis_tlast & s00_axis_tready;
  wire  arb_req_1 = s01_axis_tvalid | processing_1;
  wire  arb_fin_1 = s01_axis_tvalid & s01_axis_tlast & s01_axis_tready;
  wire  arb_req_2 = s02_axis_tvalid | processing_2;
  wire  arb_fin_2 = s02_axis_tvalid & s02_axis_tlast & s02_axis_tready;
  wire  arb_req_3 = s03_axis_tvalid | processing_3;
  wire  arb_fin_3 = s03_axis_tvalid & s03_axis_tlast & s03_axis_tready;
  wire [1:0] rr_arbiter_req_lo = {arb_req_1,arb_req_0};
  wire [1:0] rr_arbiter_req_hi = {arb_req_3,arb_req_2};
  wire [1:0] rr_arbiter_fin_lo = {arb_fin_1,arb_fin_0};
  wire [1:0] rr_arbiter_fin_hi = {arb_fin_3,arb_fin_2};
  wire  arb_grant_0 = rr_arbiter_grant[0];
  wire  arb_grant_1 = rr_arbiter_grant[1];
  wire  arb_grant_2 = rr_arbiter_grant[2];
  wire  arb_grant_3 = rr_arbiter_grant[3];
  wire [31:0] _GEN_8 = arb_grant_3 ? s03_axis_tdata : 32'h0;
  wire  _GEN_9 = arb_grant_3 & s03_axis_tvalid;
  wire  _GEN_10 = arb_grant_3 & s03_axis_tlast;
  wire [31:0] _GEN_11 = arb_grant_2 ? s02_axis_tdata : _GEN_8;
  wire  _GEN_12 = arb_grant_2 ? s02_axis_tvalid : _GEN_9;
  wire  _GEN_13 = arb_grant_2 ? s02_axis_tlast : _GEN_10;
  wire [31:0] _GEN_14 = arb_grant_1 ? s01_axis_tdata : _GEN_11;
  wire  _GEN_15 = arb_grant_1 ? s01_axis_tvalid : _GEN_12;
  wire  _GEN_16 = arb_grant_1 ? s01_axis_tlast : _GEN_13;
  PacketRRArbiter rr_arbiter (
    .clock(rr_arbiter_clock),
    .reset(rr_arbiter_reset),
    .req(rr_arbiter_req),
    .fin(rr_arbiter_fin),
    .grant(rr_arbiter_grant),
    .ready(rr_arbiter_ready)
  );
  assign s00_axis_tready = rr_arbiter_grant[0];
  assign s01_axis_tready = rr_arbiter_grant[1];
  assign s02_axis_tready = rr_arbiter_grant[2];
  assign s03_axis_tready = rr_arbiter_grant[3];
  assign m_axis_tdata = arb_grant_0 ? s00_axis_tdata : _GEN_14;
  assign m_axis_tvalid = arb_grant_0 ? s00_axis_tvalid : _GEN_15;
  assign m_axis_tlast = arb_grant_0 ? s00_axis_tlast : _GEN_16;
  assign rr_arbiter_clock = clock;
  assign rr_arbiter_reset = reset;
  assign rr_arbiter_req = {rr_arbiter_req_hi,rr_arbiter_req_lo};
  assign rr_arbiter_fin = {rr_arbiter_fin_hi,rr_arbiter_fin_lo};
  assign rr_arbiter_ready = m_axis_tready;
  always @(posedge clock) begin
    if (reset) begin
      processing_0 <= 1'h0;
    end else if (~processing_0 & s00_axis_tvalid) begin
      processing_0 <= ~(s00_axis_tlast & s00_axis_tready);
    end else if (processing_0 & s00_axis_tvalid & s00_axis_tlast & s00_axis_tready) begin
      processing_0 <= 1'h0;
    end
    if (reset) begin
      processing_1 <= 1'h0;
    end else if (~processing_1 & s01_axis_tvalid) begin
      processing_1 <= ~(s01_axis_tlast & s01_axis_tready);
    end else if (processing_1 & s01_axis_tvalid & s01_axis_tlast & s01_axis_tready) begin
      processing_1 <= 1'h0;
    end
    if (reset) begin
      processing_2 <= 1'h0;
    end else if (~processing_2 & s02_axis_tvalid) begin
      processing_2 <= ~(s02_axis_tlast & s02_axis_tready);
    end else if (processing_2 & s02_axis_tvalid & s02_axis_tlast & s02_axis_tready) begin
      processing_2 <= 1'h0;
    end
    if (reset) begin
      processing_3 <= 1'h0;
    end else if (~processing_3 & s03_axis_tvalid) begin
      processing_3 <= ~(s03_axis_tlast & s03_axis_tready);
    end else if (processing_3 & s03_axis_tvalid & s03_axis_tlast & s03_axis_tready) begin
      processing_3 <= 1'h0;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  processing_0 = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  processing_1 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  processing_2 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  processing_3 = _RAND_3[0:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule