data/full_repos/permissive/435885222/sources/mem.v
data/verilator_xmls/f324c77f-4dd0-4c68-8fc6-06856576724f.xml
module mem(
    input rst,
    input [4:0] wd_in,
    input wreg_in,
    input [31:0] wdata_in,
    input [7:0] aluop_in,
    input [31:0] mem_addr_in,
    input [31:0] reg2_in,
    input [31:0] mem_data_in,
    output reg[4:0] wd_out,
    output reg wreg_out,
    output reg[31:0] wdata_out,
    output reg[31:0] mem_addr_out,
    output wire mem_we_out,
    output reg[31:0] mem_data_out,
    output reg mem_ce_out
    );
    reg mem_we;
    assign mem_we_out=mem_we;
    always @(*)begin
        if(rst==1'b1)begin
            wd_out<=5'b00000;
            wreg_out<=1'b0;
            wdata_out<=32'h00000000;
            mem_addr_out<=32'h00000000;
            mem_we<=1'b0;
            mem_data_out<=32'h00000000;
            mem_ce_out<=1'b0;
        end else begin
            wd_out<=wd_in;
            wreg_out<=wreg_in;
            wdata_out<=wdata_in;
            mem_we<=1'b0;
            mem_addr_out<=32'h00000000;
            mem_data_out<=32'h00000000;
            mem_ce_out<=1'b0;
            case(aluop_in)
                8'b11100011:begin
                    mem_addr_out<=mem_addr_in;
                    mem_ce_out<=1'b1;
                    wdata_out<=mem_data_in;
                end
                8'b11101011:begin
                    mem_addr_out<=mem_addr_in;
                    mem_we<=1'b1;
                    mem_data_out<=reg2_in;
                    mem_ce_out<=1'b1;
                end
                default:begin
                end
            endcase
        end
    end
endmodule
module mem(
    input rst,
    input [4:0] wd_in,
    input wreg_in,
    input [31:0] wdata_in,
    input [7:0] aluop_in,
    input [31:0] mem_addr_in,
    input [31:0] reg2_in,
    input [31:0] mem_data_in,
    output reg[4:0] wd_out,
    output reg wreg_out,
    output reg[31:0] wdata_out,
    output reg[31:0] mem_addr_out,
    output wire mem_we_out,
    output reg[31:0] mem_data_out,
    output reg mem_ce_out
    );

    reg mem_we;
    assign mem_we_out=mem_we;
    always @(*)begin
        if(rst==1'b1)begin
            wd_out<=5'b00000;
            wreg_out<=1'b0;
            wdata_out<=32'h00000000;
            mem_addr_out<=32'h00000000;
            mem_we<=1'b0;
            mem_data_out<=32'h00000000;
            mem_ce_out<=1'b0;
        end else begin
            wd_out<=wd_in;
            wreg_out<=wreg_in;
            wdata_out<=wdata_in;
            mem_we<=1'b0;
            mem_addr_out<=32'h00000000;
            mem_data_out<=32'h00000000;
            mem_ce_out<=1'b0;
            case(aluop_in)
                8'b11100011:begin
                    mem_addr_out<=mem_addr_in;
                    mem_ce_out<=1'b1;
                    wdata_out<=mem_data_in;
                end
                8'b11101011:begin
                    mem_addr_out<=mem_addr_in;
                    mem_we<=1'b1;
                    mem_data_out<=reg2_in;
                    mem_ce_out<=1'b1;
                end
                default:begin
                end
            endcase
        end
    end
endmodule