data/full_repos/permissive/524553217/src/alu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/524553217/src/alu.v:22: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LTS generates 1 bits.\n                                                                 : ... In instance alu\n                        if(full_op[16:10]==7\'b0000000) out_value = $signed(in_value1) < $signed(in_value2);\n                                                                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/524553217/src/alu.v:24: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                                 : ... In instance alu\n                        if(full_op[16:10]==7\'b0000000) out_value = in_value1 < in_value2;\n                                                                 ^\n%Error: Exiting due to 2 warning(s)\n'
module alu(
    input [16:0] full_op,
    input [31:0] in_value1,
    input [31:0] in_value2,
    output reg [31:0] out_value
    );
    
    always @(*) begin
        out_value = 32'b0;
        case(full_op[6:0])
            7'b0110011,
            7'b0010011:
                case(full_op[9:7])
                    3'b000:
                        if(full_op[16:10]==7'b0000000) out_value = in_value1 + in_value2;
                        else if(full_op[6:0]==7'b0110011 && full_op[16:10]==7'b0100000) out_value = in_value1 - in_value2;
                    3'b001:
                        if(full_op[16:10]==7'b0000000) out_value = in_value1 << in_value2[4:0];
                    3'b010:
                        if(full_op[16:10]==7'b0000000) out_value = $signed(in_value1) < $signed(in_value2);
                    3'b011:
                        if(full_op[16:10]==7'b0000000) out_value = in_value1 < in_value2;
                    3'b100:
                        if(full_op[16:10]==7'b0000000) out_value = in_value1 ^ in_value2;
                    3'b101:
                        if(full_op[16:10]==7'b0000000) out_value = in_value1 >> in_value2[4:0];
                        else if(full_op[16:10]==7'b0100000) out_value = $signed(in_value1) >>> in_value2[4:0];
                    3'b110:
                        if(full_op[16:10]==7'b0000000) out_value = in_value1 | in_value2;
                    3'b111:
                        if(full_op[16:10]==7'b0000000) out_value = in_value1 & in_value2;
                endcase
            7'b1101111,
            7'b1100111,
            7'b0110111,
            7'b0010111,
            7'b1100011: begin
                out_value = in_value1 + in_value2;
            end

            default:
                out_value = 32'hdeadbeef;
        endcase
    end
endmodule
module alu(
    input [16:0] full_op,
    input [31:0] in_value1,
    input [31:0] in_value2,
    output reg [31:0] out_value
    );

    
    always @(*) begin
        out_value = 32'b0;
        case(full_op[6:0])
            7'b0110011,
            7'b0010011:
                case(full_op[9:7])
                    3'b000:
                        if(full_op[16:10]==7'b0000000) out_value = in_value1 + in_value2;
                        else if(full_op[6:0]==7'b0110011 && full_op[16:10]==7'b0100000) out_value = in_value1 - in_value2;
                    3'b001:
                        if(full_op[16:10]==7'b0000000) out_value = in_value1 << in_value2[4:0];
                    3'b010:
                        if(full_op[16:10]==7'b0000000) out_value = $signed(in_value1) < $signed(in_value2);
                    3'b011:
                        if(full_op[16:10]==7'b0000000) out_value = in_value1 < in_value2;
                    3'b100:
                        if(full_op[16:10]==7'b0000000) out_value = in_value1 ^ in_value2;
                    3'b101:
                        if(full_op[16:10]==7'b0000000) out_value = in_value1 >> in_value2[4:0];
                        else if(full_op[16:10]==7'b0100000) out_value = $signed(in_value1) >>> in_value2[4:0];
                    3'b110:
                        if(full_op[16:10]==7'b0000000) out_value = in_value1 | in_value2;
                    3'b111:
                        if(full_op[16:10]==7'b0000000) out_value = in_value1 & in_value2;
                endcase
            7'b1101111,
            7'b1100111,
            7'b0110111,
            7'b0010111,
            7'b1100011: begin
                out_value = in_value1 + in_value2;
            end

            default:
                out_value = 32'hdeadbeef;
        endcase
    end
endmodule