data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v
1: b'%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:2: Cannot find include file: gpu_definitions.v\n`include "gpu_definitions.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/48192473/rtl,data/full_repos/permissive/48192473/gpu_definitions.v\n             data/full_repos/permissive/48192473/rtl,data/full_repos/permissive/48192473/gpu_definitions.v.v\n             data/full_repos/permissive/48192473/rtl,data/full_repos/permissive/48192473/gpu_definitions.v.sv\n             gpu_definitions.v\n             gpu_definitions.v.v\n             gpu_definitions.v.sv\n             obj_dir/gpu_definitions.v\n             obj_dir/gpu_definitions.v.v\n             obj_dir/gpu_definitions.v.sv\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:28: Define or directive not defined: \'`GPU_UOP_SZ\'\n  output reg [`GPU_UOP_SZ-1:0]  oUop\n              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:77: Define or directive not defined: \'`gnop\'\n  0: oUop = { `gnop,  `gnull, `gnull, `gnull };  \n              ^~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:77: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  0: oUop = { `gnop,  `gnull, `gnull, `gnull };  \n                   ^\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:77: Define or directive not defined: \'`gnull\'\n  0: oUop = { `gnop,  `gnull, `gnull, `gnull };  \n                      ^~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:77: Define or directive not defined: \'`gnull\'\n  0: oUop = { `gnop,  `gnull, `gnull, `gnull };  \n                              ^~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:77: Define or directive not defined: \'`gnull\'\n  0: oUop = { `gnop,  `gnull, `gnull, `gnull };  \n                                      ^~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:78: Define or directive not defined: \'`gwrl\'\n  1: oUop = { `gwrl,  `state, `SCANLINE_VRAM_READ }; \n              ^~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:78: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  1: oUop = { `gwrl,  `state, `SCANLINE_VRAM_READ }; \n                   ^\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:78: Define or directive not defined: \'`state\'\n  1: oUop = { `gwrl,  `state, `SCANLINE_VRAM_READ }; \n                      ^~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:78: Define or directive not defined: \'`SCANLINE_VRAM_READ\'\n  1: oUop = { `gwrl,  `state, `SCANLINE_VRAM_READ }; \n                              ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:81: Define or directive not defined: \'`gwrr\'\n  2: oUop = { `gwrr, `cur_tile, `scy_shl_5__plus_scx, `gnull }; \n              ^~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:81: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  2: oUop = { `gwrr, `cur_tile, `scy_shl_5__plus_scx, `gnull }; \n                   ^\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:81: Define or directive not defined: \'`cur_tile\'\n  2: oUop = { `gwrr, `cur_tile, `scy_shl_5__plus_scx, `gnull }; \n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:81: Define or directive not defined: \'`scy_shl_5__plus_scx\'\n  2: oUop = { `gwrr, `cur_tile, `scy_shl_5__plus_scx, `gnull }; \n                                ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:81: Define or directive not defined: \'`gnull\'\n  2: oUop = { `gwrr, `cur_tile, `scy_shl_5__plus_scx, `gnull }; \n                                                      ^~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:82: Define or directive not defined: \'`gwrr\'\n  3: oUop = { `gwrr, `WinTile, `Win_index, `gnull };   \n              ^~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:82: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  3: oUop = { `gwrr, `WinTile, `Win_index, `gnull };   \n                   ^\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:82: Define or directive not defined: \'`WinTile\'\n  3: oUop = { `gwrr, `WinTile, `Win_index, `gnull };   \n                     ^~~~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:82: Define or directive not defined: \'`Win_index\'\n                                                                  : ... Suggested alternative: \'`inline\'\n  3: oUop = { `gwrr, `WinTile, `Win_index, `gnull };   \n                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:82: Define or directive not defined: \'`gnull\'\n  3: oUop = { `gwrr, `WinTile, `Win_index, `gnull };   \n                                           ^~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:84: Define or directive not defined: \'`gwrr\'\n  4: oUop = { `gwrr, `tile_row, `scy_tile_row_offset, `gnull};  \n              ^~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:84: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  4: oUop = { `gwrr, `tile_row, `scy_tile_row_offset, `gnull};  \n                   ^\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:84: Define or directive not defined: \'`tile_row\'\n  4: oUop = { `gwrr, `tile_row, `scy_tile_row_offset, `gnull};  \n                     ^~~~~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:84: Define or directive not defined: \'`scy_tile_row_offset\'\n  4: oUop = { `gwrr, `tile_row, `scy_tile_row_offset, `gnull};  \n                                ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:84: Define or directive not defined: \'`gnull\'\n  4: oUop = { `gwrr, `tile_row, `scy_tile_row_offset, `gnull};  \n                                                      ^~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:86: Define or directive not defined: \'`gwrl\'\n  5: oUop = { `gwrl,  `r2, 12\'d32 }; \n              ^~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:86: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  5: oUop = { `gwrl,  `r2, 12\'d32 }; \n                   ^\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:86: Define or directive not defined: \'`r2\'\n  5: oUop = { `gwrl,  `r2, 12\'d32 }; \n                      ^~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:89: Define or directive not defined: \'`gadd\'\n  6: oUop = { `gadd,  `vmem_addr, `bgmoffset, `cur_tile }; \n              ^~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:89: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  6: oUop = { `gadd,  `vmem_addr, `bgmoffset, `cur_tile }; \n                   ^\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:89: Define or directive not defined: \'`vmem_addr\'\n  6: oUop = { `gadd,  `vmem_addr, `bgmoffset, `cur_tile }; \n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:89: Define or directive not defined: \'`bgmoffset\'\n  6: oUop = { `gadd,  `vmem_addr, `bgmoffset, `cur_tile }; \n                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:89: Define or directive not defined: \'`cur_tile\'\n  6: oUop = { `gadd,  `vmem_addr, `bgmoffset, `cur_tile }; \n                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:90: Define or directive not defined: \'`grvmem\'\n  7: oUop = { `grvmem, `gnull, `gnull, `gnull }; \n              ^~~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:90: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  7: oUop = { `grvmem, `gnull, `gnull, `gnull }; \n                     ^\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:90: Define or directive not defined: \'`gnull\'\n  7: oUop = { `grvmem, `gnull, `gnull, `gnull }; \n                       ^~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:90: Define or directive not defined: \'`gnull\'\n  7: oUop = { `grvmem, `gnull, `gnull, `gnull }; \n                               ^~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:90: Define or directive not defined: \'`gnull\'\n  7: oUop = { `grvmem, `gnull, `gnull, `gnull }; \n                                       ^~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:91: Define or directive not defined: \'`gwrr\'\n  8: oUop = { `gwrr, `r3, `vmem_addr, `gnull }; \n              ^~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:91: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  8: oUop = { `gwrr, `r3, `vmem_addr, `gnull }; \n                   ^\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:91: Define or directive not defined: \'`r3\'\n  8: oUop = { `gwrr, `r3, `vmem_addr, `gnull }; \n                     ^~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:91: Define or directive not defined: \'`vmem_addr\'\n  8: oUop = { `gwrr, `r3, `vmem_addr, `gnull }; \n                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:91: Define or directive not defined: \'`gnull\'\n  8: oUop = { `gwrr, `r3, `vmem_addr, `gnull }; \n                                      ^~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:92: Define or directive not defined: \'`gadd\'\n  9: oUop = { `gadd,  `r1,`vmem_data_shl_4, `tile_row }; \n              ^~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:92: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  9: oUop = { `gadd,  `r1,`vmem_data_shl_4, `tile_row }; \n                   ^\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:92: Define or directive not defined: \'`r1\'\n  9: oUop = { `gadd,  `r1,`vmem_data_shl_4, `tile_row }; \n                      ^~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:92: Define or directive not defined: \'`vmem_data_shl_4\'\n  9: oUop = { `gadd,  `r1,`vmem_data_shl_4, `tile_row }; \n                          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:92: Define or directive not defined: \'`tile_row\'\n  9: oUop = { `gadd,  `r1,`vmem_data_shl_4, `tile_row }; \n                                            ^~~~~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/gpu_ucode_rom.v:93: Define or directive not defined: \'`gadd\'\n  10: oUop = { `gadd,  `vmem_addr, `r1, `bgtoffset }; \n               ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module gpu_ucode_rom
(
  input  wire[7:0]  iAddr,
  output reg [`GPU_UOP_SZ-1:0]  oUop
);



always @ ( iAddr )
begin
  case ( iAddr )




  0: oUop = { `gnop,  `gnull, `gnull, `gnull };
  1: oUop = { `gwrl,  `state, `SCANLINE_VRAM_READ };


  2: oUop = { `gwrr, `cur_tile, `scy_shl_5__plus_scx, `gnull };
  3: oUop = { `gwrr, `WinTile, `Win_index, `gnull };

  4: oUop = { `gwrr, `tile_row, `scy_tile_row_offset, `gnull};

  5: oUop = { `gwrl,  `r2, 12'd32 };


  6: oUop = { `gadd,  `vmem_addr, `bgmoffset, `cur_tile };
  7: oUop = { `grvmem, `gnull, `gnull, `gnull };
  8: oUop = { `gwrr, `r3, `vmem_addr, `gnull };
  9: oUop = { `gadd,  `r1,`vmem_data_shl_4, `tile_row };
  10: oUop = { `gadd,  `vmem_addr, `r1, `bgtoffset };
  11: oUop = { `grvmem, `gnull, `gnull, `gnull };
  12: oUop = {  `gwrr,   `bh, `vmem_data, `gnull };
  13: oUop = {  `gaddl,  `vmem_addr, 12'd1  };
  14: oUop = {  `grvmem, `gnull, `gnull, `gnull };
  15: oUop = {  `gwrr,   `bl, `vmem_data, `gnull };
  16: oUop = {  `gwfbuffer,   `gnull,`gnull, `gnull};



  17: oUop = {`gwrl, `r6, 12'b10};
  18: oUop = {`gand, `r3, `r6, `lcdc};
  19: oUop = {`gjz,`skip_the_sprites};
  20:
  begin
   oUop = {`gwrl, `r6, 12'd0};

  end

  21: oUop = {`gadd, `vmem_addr, `r6, `oam_offset};
  22: oUop = {`grvmem, `gnull, `gnull, `gnull};
  23: oUop = {`gsubl,  `vmem_data, 12'd0};
  24: oUop = {`gjz, `get_next_sprite};
  25: oUop = {`gwrl,`r4 , 12'd16};
  26: oUop = {`gsub,`sprite_y_coord ,`vmem_data,`r4};
  27: oUop = {`gaddl, `vmem_addr, 12'd1};
  28: oUop = {`grvmem, `gnull,`gnull,`gnull};
  29: oUop = {`gsubl,  `vmem_data, 12'd0};
  30: oUop = {`gjz,    `get_next_sprite};
  31: oUop = {`gwrl,`r4 , 12'd8};
  32: oUop = {`gsub, `sprite_x_coord ,`vmem_data ,`r4 };
  33: oUop = {`gnop,  `gnull, `gnull, `gnull};
  34: oUop = {`gsprtt,  `r4, `sprite_x_coord, `sprite_y_coord};
  35: oUop = {`gjz,    `get_next_sprite};

  36: oUop = {`gaddl, `vmem_addr, 12'd1};
  37: oUop = {`grvmem, `gnull,`gnull,`gnull};
  38: oUop = {`gadd, `r4 ,`vmem_data_shl_4, `tile_row };
  39: oUop = {`gaddl, `vmem_addr, 12'd1};
  40: oUop = {`grvmem, `gnull,`gnull,`gnull};
  41: oUop = {`gwrr, `sprite_info,`vmem_data};




  42: oUop = {`gadd, `vmem_addr,`bgtoffset,`r4};
  43: oUop = {`grvmem,`gnull,`gnull,`gnull};
  44: oUop = {`gwrr, `sh, `vmem_data, `gnull};
  45: oUop = {`gaddl, `vmem_addr, 12'd1};
  46: oUop = {`grvmem, `gnull,`gnull,`gnull};
  47: oUop = {`gwrr, `sl,`vmem_data, `gnull};
  48: oUop = {`gnop,  `gnull, `gnull, `gnull};
  49: oUop = {`gnop,  `gnull, `gnull, `gnull};


  50: oUop = {`gwfbuffer, `gnull,`gnull, `gnull};

  51: oUop = {`gaddl,`r6, 12'd4};
  52: oUop = {`gsubl,`r6, 12'd156};
  53:  begin


    oUop = {`gwrr,  `sprite_current_row_offset, `tile_row, `gnull};

end




 54: oUop = {`gwrl, `r6, 12'b00100001};
 55: oUop = {`gand, `r3, `r6, `lcdc};
 56: oUop = {`gjz,`skip_the_window};
 57: oUop = {`gwx,  `gnull, `gnull, `gnull};
 58: oUop = {`gjz,`skip_the_window};
 59: oUop = {`gwy,  `gnull, `gnull, `gnull};
 60:

 oUop = {`gjz,`skip_the_window};


61: oUop = {`gsubl, `IsThisTileWin, 12'b0 };
62: oUop = {`gjnz,`initialize_window};
63: oUop = {`gsubl,`Window_render,12'b0};
64: oUop = {`gjnz,`render_window};
65: oUop = {`ggoto,`skip_the_window};

66: oUop = {`gwrl,`r5, 12'b0};
67: oUop = {`gwrl,`Window_render, 12'b1};

68: oUop = { `gadd,  `vmem_addr, `Winmoffset, `r5 };
69: oUop = { `grvmem, `gnull, `gnull, `gnull };
70: oUop = { `gwrr, `r3, `vmem_addr, `gnull };
71: oUop = { `gadd,  `r1,`vmem_data_shl_4, `tile_row };
72: oUop = { `gadd,  `vmem_addr, `r1, `bgtoffset };
73: oUop = { `grvmem, `gnull, `gnull, `gnull };
74: oUop = { `gwrr,   `bh, `vmem_data, `gnull };
75: oUop = { `gaddl,  `vmem_addr, 12'd1  };
76: oUop = { `grvmem, `gnull, `gnull, `gnull };
77: oUop = { `gwrr,   `bl, `vmem_data, `gnull };
78: oUop = { `gwfbuffer,   `gnull,`gnull, `gnull};

79: oUop = {`gaddl,  `r5, 12'd1};
80: oUop = { `gaddl, `WinTile, 12'd1  };
81: oUop = { `gsubl, `WinTile, 12'd255  };
82: oUop = { `gjnz, `skip_the_window };
83: oUop = { `gwrl, `Window_render, 12'd0 };



  84: oUop = {`ginfbaddr, `gnull, `gnull, `gnull};
  85: oUop = {`gwrl, `sl, 12'd0};
  86: oUop = {`gwrl, `sh, 12'd0};
  87: oUop = { `gsubl, `r1, 12'd8191};
  88: oUop = { `gsub, `r1, `fbuffer_addr, `r8191};
  89: oUop = { `gjz, 18'h2};
  90: oUop = {  `gaddl, `r5, 12'd0 };
  91: oUop = { `gwrl,`sprite_current_row_offset, 12'd0};
  92: oUop = {  `gaddl, `cur_tile, 12'd1  };
  93: oUop = {  `gsubl, `r2, 12'd1 };
  94: oUop = {  `gjnz ,  18'd6};
  95: oUop = {  `gaddl,  `tile_row, 12'd2  };
  96: oUop = {  `gaddl , `ly, 12'd1 };
  97: oUop = {  `gwrr,  `r1, `tile_row, `gnull };
  98: oUop = {  `gsubl,  `r1, 12'h10 };
  99: oUop = {  `gjz , 18'd4  };


  100: oUop = {  `gsubl, `r5, 12'd32 };
  101: oUop = {  `gsubl, `cur_tile, 12'd32 };
  102: oUop = {  `ggoto,  18'd5 };

  endcase
end

endmodule
module gpu_ucode_rom
(
  input  wire[7:0]  iAddr,
  output reg [`GPU_UOP_SZ-1:0]  oUop
);




always @ ( iAddr )
begin
  case ( iAddr )




  0: oUop = { `gnop,  `gnull, `gnull, `gnull };
  1: oUop = { `gwrl,  `state, `SCANLINE_VRAM_READ };


  2: oUop = { `gwrr, `cur_tile, `scy_shl_5__plus_scx, `gnull };
  3: oUop = { `gwrr, `WinTile, `Win_index, `gnull };

  4: oUop = { `gwrr, `tile_row, `scy_tile_row_offset, `gnull};

  5: oUop = { `gwrl,  `r2, 12'd32 };


  6: oUop = { `gadd,  `vmem_addr, `bgmoffset, `cur_tile };
  7: oUop = { `grvmem, `gnull, `gnull, `gnull };
  8: oUop = { `gwrr, `r3, `vmem_addr, `gnull };
  9: oUop = { `gadd,  `r1,`vmem_data_shl_4, `tile_row };
  10: oUop = { `gadd,  `vmem_addr, `r1, `bgtoffset };
  11: oUop = { `grvmem, `gnull, `gnull, `gnull };
  12: oUop = {  `gwrr,   `bh, `vmem_data, `gnull };
  13: oUop = {  `gaddl,  `vmem_addr, 12'd1  };
  14: oUop = {  `grvmem, `gnull, `gnull, `gnull };
  15: oUop = {  `gwrr,   `bl, `vmem_data, `gnull };
  16: oUop = {  `gwfbuffer,   `gnull,`gnull, `gnull};



  17: oUop = {`gwrl, `r6, 12'b10};
  18: oUop = {`gand, `r3, `r6, `lcdc};
  19: oUop = {`gjz,`skip_the_sprites};
  20:
  begin
   oUop = {`gwrl, `r6, 12'd0};

  end

  21: oUop = {`gadd, `vmem_addr, `r6, `oam_offset};
  22: oUop = {`grvmem, `gnull, `gnull, `gnull};
  23: oUop = {`gsubl,  `vmem_data, 12'd0};
  24: oUop = {`gjz, `get_next_sprite};
  25: oUop = {`gwrl,`r4 , 12'd16};
  26: oUop = {`gsub,`sprite_y_coord ,`vmem_data,`r4};
  27: oUop = {`gaddl, `vmem_addr, 12'd1};
  28: oUop = {`grvmem, `gnull,`gnull,`gnull};
  29: oUop = {`gsubl,  `vmem_data, 12'd0};
  30: oUop = {`gjz,    `get_next_sprite};
  31: oUop = {`gwrl,`r4 , 12'd8};
  32: oUop = {`gsub, `sprite_x_coord ,`vmem_data ,`r4 };
  33: oUop = {`gnop,  `gnull, `gnull, `gnull};
  34: oUop = {`gsprtt,  `r4, `sprite_x_coord, `sprite_y_coord};
  35: oUop = {`gjz,    `get_next_sprite};

  36: oUop = {`gaddl, `vmem_addr, 12'd1};
  37: oUop = {`grvmem, `gnull,`gnull,`gnull};
  38: oUop = {`gadd, `r4 ,`vmem_data_shl_4, `tile_row };
  39: oUop = {`gaddl, `vmem_addr, 12'd1};
  40: oUop = {`grvmem, `gnull,`gnull,`gnull};
  41: oUop = {`gwrr, `sprite_info,`vmem_data};




  42: oUop = {`gadd, `vmem_addr,`bgtoffset,`r4};
  43: oUop = {`grvmem,`gnull,`gnull,`gnull};
  44: oUop = {`gwrr, `sh, `vmem_data, `gnull};
  45: oUop = {`gaddl, `vmem_addr, 12'd1};
  46: oUop = {`grvmem, `gnull,`gnull,`gnull};
  47: oUop = {`gwrr, `sl,`vmem_data, `gnull};
  48: oUop = {`gnop,  `gnull, `gnull, `gnull};
  49: oUop = {`gnop,  `gnull, `gnull, `gnull};


  50: oUop = {`gwfbuffer, `gnull,`gnull, `gnull};

  51: oUop = {`gaddl,`r6, 12'd4};
  52: oUop = {`gsubl,`r6, 12'd156};
  53:  begin


    oUop = {`gwrr,  `sprite_current_row_offset, `tile_row, `gnull};

end




 54: oUop = {`gwrl, `r6, 12'b00100001};
 55: oUop = {`gand, `r3, `r6, `lcdc};
 56: oUop = {`gjz,`skip_the_window};
 57: oUop = {`gwx,  `gnull, `gnull, `gnull};
 58: oUop = {`gjz,`skip_the_window};
 59: oUop = {`gwy,  `gnull, `gnull, `gnull};
 60:

 oUop = {`gjz,`skip_the_window};


61: oUop = {`gsubl, `IsThisTileWin, 12'b0 };
62: oUop = {`gjnz,`initialize_window};
63: oUop = {`gsubl,`Window_render,12'b0};
64: oUop = {`gjnz,`render_window};
65: oUop = {`ggoto,`skip_the_window};

66: oUop = {`gwrl,`r5, 12'b0};
67: oUop = {`gwrl,`Window_render, 12'b1};

68: oUop = { `gadd,  `vmem_addr, `Winmoffset, `r5 };
69: oUop = { `grvmem, `gnull, `gnull, `gnull };
70: oUop = { `gwrr, `r3, `vmem_addr, `gnull };
71: oUop = { `gadd,  `r1,`vmem_data_shl_4, `tile_row };
72: oUop = { `gadd,  `vmem_addr, `r1, `bgtoffset };
73: oUop = { `grvmem, `gnull, `gnull, `gnull };
74: oUop = { `gwrr,   `bh, `vmem_data, `gnull };
75: oUop = { `gaddl,  `vmem_addr, 12'd1  };
76: oUop = { `grvmem, `gnull, `gnull, `gnull };
77: oUop = { `gwrr,   `bl, `vmem_data, `gnull };
78: oUop = { `gwfbuffer,   `gnull,`gnull, `gnull};

79: oUop = {`gaddl,  `r5, 12'd1};
80: oUop = { `gaddl, `WinTile, 12'd1  };
81: oUop = { `gsubl, `WinTile, 12'd255  };
82: oUop = { `gjnz, `skip_the_window };
83: oUop = { `gwrl, `Window_render, 12'd0 };



  84: oUop = {`ginfbaddr, `gnull, `gnull, `gnull};
  85: oUop = {`gwrl, `sl, 12'd0};
  86: oUop = {`gwrl, `sh, 12'd0};
  87: oUop = { `gsubl, `r1, 12'd8191};
  88: oUop = { `gsub, `r1, `fbuffer_addr, `r8191};
  89: oUop = { `gjz, 18'h2};
  90: oUop = {  `gaddl, `r5, 12'd0 };
  91: oUop = { `gwrl,`sprite_current_row_offset, 12'd0};
  92: oUop = {  `gaddl, `cur_tile, 12'd1  };
  93: oUop = {  `gsubl, `r2, 12'd1 };
  94: oUop = {  `gjnz ,  18'd6};
  95: oUop = {  `gaddl,  `tile_row, 12'd2  };
  96: oUop = {  `gaddl , `ly, 12'd1 };
  97: oUop = {  `gwrr,  `r1, `tile_row, `gnull };
  98: oUop = {  `gsubl,  `r1, 12'h10 };
  99: oUop = {  `gjz , 18'd4  };


  100: oUop = {  `gsubl, `r5, 12'd32 };
  101: oUop = {  `gsubl, `cur_tile, 12'd32 };
  102: oUop = {  `ggoto,  18'd5 };

  endcase
end

endmodule