data/full_repos/permissive/509809169/Circuits/Sequential Logic/Finite State Machines/Q6c FSM one-hot next state logic.v
1: b'%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines,data/full_repos/permissive/509809169\n%Error: Cannot find file containing module: data/full_repos/permissive/509809169/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/Q6c\n%Error: Cannot find file containing module: FSM\n%Error: Cannot find file containing module: one-hot\n%Error: Cannot find file containing module: next\n%Error: Cannot find file containing module: state\n%Error: Cannot find file containing module: logic.v\n%Error: Exiting due to 10 error(s)\n'
module top_module (
    input [6:1] y,
    input w,
    output Y2,
    output Y4);

    assign Y2 = y[1] && (~w) ;
    assign Y4 = (y[2] || y[3] || y[5] || y[6]) && w ;
endmodule
module top_module (
    input [6:1] y,
    input w,
    output Y2,
    output Y4);


    assign Y2 = y[1] && (~w) ;
    assign Y4 = (y[2] || y[3] || y[5] || y[6]) && w ;
endmodule