data/full_repos/permissive/423958267/lab04_3/lab04_3.srcs/sources_1/imports/sources_1/imports/new/main.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/423958267/lab04_3/lab04_3.srcs/sources_1/imports/sources_1/imports/new/main.v:68: Signal definition not found, creating implicitly: \'BtnU\'\n                                                                                                                              : ... Suggested alternative: \'btnU\'\n        if(BtnU) mode <= 2\'d0;\n           ^~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/423958267/lab04_3/lab04_3.srcs/sources_1/imports/sources_1/imports/new/main.v:69: Signal definition not found, creating implicitly: \'BtnL\'\n                                                                                                                              : ... Suggested alternative: \'BtnU\'\n        else if(BtnL) mode <= 2\'d1;\n                ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/423958267/lab04_3/lab04_3.srcs/sources_1/imports/sources_1/imports/new/main.v:70: Signal definition not found, creating implicitly: \'BtnD\'\n                                                                                                                              : ... Suggested alternative: \'BtnL\'\n        else if(BtnD) mode <= 2\'d2;\n                ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/423958267/lab04_3/lab04_3.srcs/sources_1/imports/sources_1/imports/new/main.v:71: Signal definition not found, creating implicitly: \'BtnR\'\n                                                                                                                              : ... Suggested alternative: \'BtnD\'\n        else if(BtnR) mode <= 2\'d3;\n                ^~~~\n%Error: data/full_repos/permissive/423958267/lab04_3/lab04_3.srcs/sources_1/imports/sources_1/imports/new/main.v:52: Cannot find file containing module: \'Button\'\n    Button bu(BtnU,btnU,clk);\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423958267/lab04_3/lab04_3.srcs/sources_1/imports/sources_1/imports/new,data/full_repos/permissive/423958267/Button\n             data/full_repos/permissive/423958267/lab04_3/lab04_3.srcs/sources_1/imports/sources_1/imports/new,data/full_repos/permissive/423958267/Button.v\n             data/full_repos/permissive/423958267/lab04_3/lab04_3.srcs/sources_1/imports/sources_1/imports/new,data/full_repos/permissive/423958267/Button.sv\n             Button\n             Button.v\n             Button.sv\n             obj_dir/Button\n             obj_dir/Button.v\n             obj_dir/Button.sv\n%Error: data/full_repos/permissive/423958267/lab04_3/lab04_3.srcs/sources_1/imports/sources_1/imports/new/main.v:53: Cannot find file containing module: \'Button\'\n    Button bd(BtnD,btnD,clk);\n    ^~~~~~\n%Error: data/full_repos/permissive/423958267/lab04_3/lab04_3.srcs/sources_1/imports/sources_1/imports/new/main.v:54: Cannot find file containing module: \'Button\'\n    Button bl(BtnL,btnL,clk);\n    ^~~~~~\n%Error: data/full_repos/permissive/423958267/lab04_3/lab04_3.srcs/sources_1/imports/sources_1/imports/new/main.v:55: Cannot find file containing module: \'Button\'\n    Button br(BtnR,btnR,clk);\n    ^~~~~~\n%Error: data/full_repos/permissive/423958267/lab04_3/lab04_3.srcs/sources_1/imports/sources_1/imports/new/main.v:60: Cannot find file containing module: \'Switch\'\n            Switch s(SW[i],sw[i],clk);\n            ^~~~~~\n%Error: data/full_repos/permissive/423958267/lab04_3/lab04_3.srcs/sources_1/imports/sources_1/imports/new/main.v:75: Cannot find file containing module: \'ROM\'\n    ROM r(data,addr,clk);\n    ^~~\n%Error: data/full_repos/permissive/423958267/lab04_3/lab04_3.srcs/sources_1/imports/sources_1/imports/new/main.v:82: Cannot find file containing module: \'Counter\'\n    Counter #(20) c(counter,nreset,clk);\n    ^~~~~~~\n%Error: data/full_repos/permissive/423958267/lab04_3/lab04_3.srcs/sources_1/imports/sources_1/imports/new/main.v:84: Cannot find file containing module: \'Mux4to1\'\n    Mux4to1 #(4) mx(d,q,digit0,digit1,digit2,digit3);\n    ^~~~~~~\n%Error: data/full_repos/permissive/423958267/lab04_3/lab04_3.srcs/sources_1/imports/sources_1/imports/new/main.v:85: Cannot find file containing module: \'Decoder4\'\n    Decoder4 dec(sel,q);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/423958267/lab04_3/lab04_3.srcs/sources_1/imports/sources_1/imports/new/main.v:86: Cannot find file containing module: \'HexTo7Seg\'\n    HexTo7Seg h(segments,d);\n    ^~~~~~~~~\n%Error: Exiting due to 10 error(s), 4 warning(s)\n'
module main(
    output wire [6:0] seg,
    output wire [3:0] an,
    input btnU,
    input btnD,
    input btnL,
    input btnR,
    input [7:0] sw,
    input clk
);
    wire [1:0] q;
    wire d0,d1;
    wire [3:0] d;
    wire [3:0] digit0,digit1,digit2,digit3;
    wire [3:0] sel;
    wire [19:0] counter;

    wire [7:0] SW;
    wire [12:0] data;
    wire [9:0] addr;

    reg nreset;
    
    assign digit0 = data[3:0];
    assign digit1 = data[7:4];
    assign digit2 = data[11:8];
    
    assign digit3 = 4'd0;
    
    Button bu(BtnU,btnU,clk);
    Button bd(BtnD,btnD,clk);
    Button bl(BtnL,btnL,clk);
    Button br(BtnR,btnR,clk);
    
    genvar i;
    generate
        for(i=0;i<8;i=i+1) begin
            Switch s(SW[i],sw[i],clk);
        end
    endgenerate
    
    reg [1:0] mode;
    initial mode <= 2'd0;
    always @(posedge clk)
    begin
        if(BtnU) mode <= 2'd0;
        else if(BtnL) mode <= 2'd1;
        else if(BtnD) mode <= 2'd2;
        else if(BtnR) mode <= 2'd3;
    end
    
    assign addr = {SW,mode};
    ROM r(data,addr,clk);

    assign q = {counter[19],counter[18]};

    assign an = ~sel;
    
    initial nreset <= 1;
    Counter #(20) c(counter,nreset,clk);

    Mux4to1 #(4) mx(d,q,digit0,digit1,digit2,digit3);
    Decoder4 dec(sel,q);
    HexTo7Seg h(segments,d);
    
    wire [6:0] segments;
    wire divideByZero;
    wire minus;
    assign minus = data[12];
    assign divideByZero = (mode == 2'd3 && SW[3:0] == 4'd0);
    assign seg = (divideByZero || (minus && sel[3])) ? 7'b0111111 : segments;

endmodule
module main(
    output wire [6:0] seg,
    output wire [3:0] an,
    input btnU,
    input btnD,
    input btnL,
    input btnR,
    input [7:0] sw,
    input clk
);

    wire [1:0] q;
    wire d0,d1;
    wire [3:0] d;
    wire [3:0] digit0,digit1,digit2,digit3;
    wire [3:0] sel;
    wire [19:0] counter;

    wire [7:0] SW;
    wire [12:0] data;
    wire [9:0] addr;

    reg nreset;
    
    assign digit0 = data[3:0];
    assign digit1 = data[7:4];
    assign digit2 = data[11:8];
    
    assign digit3 = 4'd0;
    
    Button bu(BtnU,btnU,clk);
    Button bd(BtnD,btnD,clk);
    Button bl(BtnL,btnL,clk);
    Button br(BtnR,btnR,clk);
    
    genvar i;
    generate
        for(i=0;i<8;i=i+1) begin
            Switch s(SW[i],sw[i],clk);
        end
    endgenerate
    
    reg [1:0] mode;
    initial mode <= 2'd0;
    always @(posedge clk)
    begin
        if(BtnU) mode <= 2'd0;
        else if(BtnL) mode <= 2'd1;
        else if(BtnD) mode <= 2'd2;
        else if(BtnR) mode <= 2'd3;
    end
    
    assign addr = {SW,mode};
    ROM r(data,addr,clk);

    assign q = {counter[19],counter[18]};

    assign an = ~sel;
    
    initial nreset <= 1;
    Counter #(20) c(counter,nreset,clk);

    Mux4to1 #(4) mx(d,q,digit0,digit1,digit2,digit3);
    Decoder4 dec(sel,q);
    HexTo7Seg h(segments,d);
    
    wire [6:0] segments;
    wire divideByZero;
    wire minus;
    assign minus = data[12];
    assign divideByZero = (mode == 2'd3 && SW[3:0] == 4'd0);
    assign seg = (divideByZero || (minus && sel[3])) ? 7'b0111111 : segments;

endmodule