data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/PEDC.v
1: b"%Error: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/PEDC.v:72: Cannot find file containing module: 'PEDC_STATEMACHINE'\nPEDC_STATEMACHINE Pedc_Statemachine(\n^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules,data/full_repos/permissive/436253691/PEDC_STATEMACHINE\n             data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules,data/full_repos/permissive/436253691/PEDC_STATEMACHINE.v\n             data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules,data/full_repos/permissive/436253691/PEDC_STATEMACHINE.sv\n             PEDC_STATEMACHINE\n             PEDC_STATEMACHINE.v\n             PEDC_STATEMACHINE.sv\n             obj_dir/PEDC_STATEMACHINE\n             obj_dir/PEDC_STATEMACHINE.v\n             obj_dir/PEDC_STATEMACHINE.sv\n%Error: Exiting due to 1 error(s)\n"
module PEDC(


PEDC_Clk,
PEDC_Start_Routine,
PEDC_Stop_Routine,


PEDC_OutReg_Set,
PEDC_Reset

);







input PEDC_Clk;
input PEDC_Start_Routine;
input PEDC_Stop_Routine;
output PEDC_OutReg_Set;
output PEDC_Reset;





wire Pedc_Statemachine_Set_Signal_En;
reg Set;






always@(PEDC_Clk)
begin
		if(Pedc_Statemachine_Set_Signal_En)
			Set=~PEDC_Clk;
		else
			Set=1'b0;
end






PEDC_STATEMACHINE Pedc_Statemachine(

.PEDC_STATEMACHINE_Clk(PEDC_Clk),
.PEDC_STATEMACHINE_Start_Routine(PEDC_Start_Routine),
.PEDC_STATEMACHINE_Stop_Routine(PEDC_Stop_Routine),


.PEDC_STATEMACHINE_Reset(PEDC_Reset),
.PEDC_STATEMACHINE_Set_Signal_En(Pedc_Statemachine_Set_Signal_En)

);





assign PEDC_OutReg_Set=Set;


endmodule
module PEDC(


PEDC_Clk,
PEDC_Start_Routine,
PEDC_Stop_Routine,


PEDC_OutReg_Set,
PEDC_Reset

);








input PEDC_Clk;
input PEDC_Start_Routine;
input PEDC_Stop_Routine;
output PEDC_OutReg_Set;
output PEDC_Reset;





wire Pedc_Statemachine_Set_Signal_En;
reg Set;






always@(PEDC_Clk)
begin
		if(Pedc_Statemachine_Set_Signal_En)
			Set=~PEDC_Clk;
		else
			Set=1'b0;
end






PEDC_STATEMACHINE Pedc_Statemachine(

.PEDC_STATEMACHINE_Clk(PEDC_Clk),
.PEDC_STATEMACHINE_Start_Routine(PEDC_Start_Routine),
.PEDC_STATEMACHINE_Stop_Routine(PEDC_Stop_Routine),


.PEDC_STATEMACHINE_Reset(PEDC_Reset),
.PEDC_STATEMACHINE_Set_Signal_En(Pedc_Statemachine_Set_Signal_En)

);





assign PEDC_OutReg_Set=Set;


endmodule