data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/frontend/btb.sv
1: b"%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/frontend/btb.sv:25: syntax error, unexpected ::, expecting ':'\n    input  logic [riscv::VLEN-1:0]      vpc_i,            \n                       ^~\n                                                                                                                : ... Perhaps 'riscv' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/frontend/btb.sv:32: syntax error, unexpected ::, expecting ';'\n    localparam NR_ROWS = NR_ENTRIES / ariane_pkg::INSTR_PER_FETCH;\n                                                ^~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/frontend/btb.sv:34: syntax error, unexpected ::\n    localparam ROW_ADDR_BITS = $clog2(ariane_pkg::INSTR_PER_FETCH);\n                                                ^~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/frontend/btb.sv:40: syntax error, unexpected IDENTIFIER\n    unread i_unread (.d_i(|vpc_i));\n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/frontend/btb.sv:49: syntax error, unexpected assign\n    assign index     = vpc_i[PREDICTION_BITS - 1:ROW_ADDR_BITS + OFFSET];\n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/frontend/btb.sv:76: syntax error, unexpected IDENTIFIER\n            for (int i = 0; i < NR_ROWS; i++)\n                            ^\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/frontend/btb.sv:81: syntax error, unexpected IDENTIFIER\n                for (int i = 0; i < NR_ROWS; i++) begin\n                                ^\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/frontend/btb.sv:82: syntax error, unexpected IDENTIFIER\n                    for (int j = 0; j < ariane_pkg::INSTR_PER_FETCH; j++) begin\n                                    ^\n%Error: Exiting due to 8 error(s)\n"
module btb #(
    parameter int NR_ENTRIES = 8
)(
    input  logic                        clk_i,
    input  logic                        rst_ni,
    input  logic                        flush_i,
    input  logic                        debug_mode_i,

    input  logic [riscv::VLEN-1:0]      vpc_i,
    input  ariane_pkg::btb_update_t     btb_update_i,
    output ariane_pkg::btb_prediction_t [ariane_pkg::INSTR_PER_FETCH-1:0] btb_prediction_o
);

    localparam OFFSET = 1;

    localparam NR_ROWS = NR_ENTRIES / ariane_pkg::INSTR_PER_FETCH;

    localparam ROW_ADDR_BITS = $clog2(ariane_pkg::INSTR_PER_FETCH);

    localparam PREDICTION_BITS = $clog2(NR_ROWS) + OFFSET + ROW_ADDR_BITS;

    localparam ANTIALIAS_BITS = 8;

    unread i_unread (.d_i(|vpc_i));



    ariane_pkg::btb_prediction_t btb_d [NR_ROWS-1:0][ariane_pkg::INSTR_PER_FETCH-1:0],
                                 btb_q [NR_ROWS-1:0][ariane_pkg::INSTR_PER_FETCH-1:0];
    logic [$clog2(NR_ROWS)-1:0]  index, update_pc;
    logic [ROW_ADDR_BITS-1:0]    update_row_index;

    assign index     = vpc_i[PREDICTION_BITS - 1:ROW_ADDR_BITS + OFFSET];
    assign update_pc = btb_update_i.pc[PREDICTION_BITS - 1:ROW_ADDR_BITS + OFFSET];
    assign update_row_index = btb_update_i.pc[ROW_ADDR_BITS + OFFSET - 1:OFFSET];


    for (genvar i = 0; i < ariane_pkg::INSTR_PER_FETCH; i++) begin : gen_btb_output
        assign btb_prediction_o[i] = btb_q[index][i];
    end





    always_comb begin : update_branch_predict
        btb_d = btb_q;

        if (btb_update_i.valid && !debug_mode_i) begin
            btb_d[update_pc][update_row_index].valid = 1'b1;

            btb_d[update_pc][update_row_index].target_address = btb_update_i.target_address;
        end
    end


    always_ff @(posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin

            for (int i = 0; i < NR_ROWS; i++)
                btb_q[i] <= '{default: 0};
        end else begin

            if (flush_i) begin
                for (int i = 0; i < NR_ROWS; i++) begin
                    for (int j = 0; j < ariane_pkg::INSTR_PER_FETCH; j++) begin
                        btb_q[i][j].valid <=  1'b0;
                    end
                end
            end else begin
                btb_q <=  btb_d;
            end
        end
    end
endmodule
module btb #(
    parameter int NR_ENTRIES = 8
)(
    input  logic                        clk_i,
    input  logic                        rst_ni,
    input  logic                        flush_i,
    input  logic                        debug_mode_i,

    input  logic [riscv::VLEN-1:0]      vpc_i,
    input  ariane_pkg::btb_update_t     btb_update_i,
    output ariane_pkg::btb_prediction_t [ariane_pkg::INSTR_PER_FETCH-1:0] btb_prediction_o
);


    localparam OFFSET = 1;

    localparam NR_ROWS = NR_ENTRIES / ariane_pkg::INSTR_PER_FETCH;

    localparam ROW_ADDR_BITS = $clog2(ariane_pkg::INSTR_PER_FETCH);

    localparam PREDICTION_BITS = $clog2(NR_ROWS) + OFFSET + ROW_ADDR_BITS;

    localparam ANTIALIAS_BITS = 8;

    unread i_unread (.d_i(|vpc_i));



    ariane_pkg::btb_prediction_t btb_d [NR_ROWS-1:0][ariane_pkg::INSTR_PER_FETCH-1:0],
                                 btb_q [NR_ROWS-1:0][ariane_pkg::INSTR_PER_FETCH-1:0];
    logic [$clog2(NR_ROWS)-1:0]  index, update_pc;
    logic [ROW_ADDR_BITS-1:0]    update_row_index;

    assign index     = vpc_i[PREDICTION_BITS - 1:ROW_ADDR_BITS + OFFSET];
    assign update_pc = btb_update_i.pc[PREDICTION_BITS - 1:ROW_ADDR_BITS + OFFSET];
    assign update_row_index = btb_update_i.pc[ROW_ADDR_BITS + OFFSET - 1:OFFSET];


    for (genvar i = 0; i < ariane_pkg::INSTR_PER_FETCH; i++) begin : gen_btb_output
        assign btb_prediction_o[i] = btb_q[index][i];
    end





    always_comb begin : update_branch_predict
        btb_d = btb_q;

        if (btb_update_i.valid && !debug_mode_i) begin
            btb_d[update_pc][update_row_index].valid = 1'b1;

            btb_d[update_pc][update_row_index].target_address = btb_update_i.target_address;
        end
    end


    always_ff @(posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin

            for (int i = 0; i < NR_ROWS; i++)
                btb_q[i] <= '{default: 0};
        end else begin

            if (flush_i) begin
                for (int i = 0; i < NR_ROWS; i++) begin
                    for (int j = 0; j < ariane_pkg::INSTR_PER_FETCH; j++) begin
                        btb_q[i][j].valid <=  1'b0;
                    end
                end
            end else begin
                btb_q <=  btb_d;
            end
        end
    end
endmodule