data/full_repos/permissive/474294847/rtl-src/systolic-elements/systolic-cell.v
1: b'%Error: data/full_repos/permissive/474294847/rtl-src/systolic-elements/systolic-cell.v:1: Cannot find include file: mac.v\n`include "mac.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/474294847/rtl-src/systolic-elements,data/full_repos/permissive/474294847/mac.v\n             data/full_repos/permissive/474294847/rtl-src/systolic-elements,data/full_repos/permissive/474294847/mac.v.v\n             data/full_repos/permissive/474294847/rtl-src/systolic-elements,data/full_repos/permissive/474294847/mac.v.sv\n             mac.v\n             mac.v.v\n             mac.v.sv\n             obj_dir/mac.v\n             obj_dir/mac.v.v\n             obj_dir/mac.v.sv\n%Error: data/full_repos/permissive/474294847/rtl-src/systolic-elements/systolic-cell.v:2: Cannot find include file: rom.v\n`include "rom.v" \n         ^~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module systolic_cell 
    (clk, ce, ctrl_in, ctrl_out, mem_addr_in, mem_addr_out, y_in, y_out, x_in, x_out);


    parameter WIDTH = 8;
    parameter MEM_ADDR_WIDTH = 4;
    parameter ROM_FILE = "weights/cell-weights.mem";
    localparam ACCUM_WIDTH = WIDTH * 2;
    localparam SATURATED_MAX = (1 << WIDTH - 1) - 1;
    localparam SATURATED_MIN = -(1 << WIDTH - 1);


    input clk, ce;
    input [31:0] ctrl_in; 
    input [MEM_ADDR_WIDTH-1:0] mem_addr_in;
    input signed [WIDTH-1:0] y_in, x_in;
    output signed [WIDTH-1:0] y_out, x_out;
    output [31:0] ctrl_out; 
    output [MEM_ADDR_WIDTH-1:0] mem_addr_out;


wire signed [ACCUM_WIDTH-1:0] mac_out;
wire signed [WIDTH-1:0] kernel_weight;
reg [31:0] ctrl_reg;
reg [MEM_ADDR_WIDTH-1:0] mem_addr_reg;
reg signed [WIDTH-1:0] x_in_reg1, x_in_reg2;


mac mac_inst
(
    clk, ce, 
    x_in, kernel_weight, y_in, 
    mac_out
);
defparam mac_inst.WIDTH = WIDTH;


rom cell_memory
(
    clk, 1'b1,
    mem_addr_reg, 
    kernel_weight
);
defparam cell_memory.ADDR_WIDTH = MEM_ADDR_WIDTH;
defparam cell_memory.DATA_WIDTH = WIDTH;
defparam cell_memory.ROM_FILE = ROM_FILE;


initial
begin
    mem_addr_reg = 0;
    ctrl_reg = 0;
    x_in_reg1 = 0;
    x_in_reg2 = 0;
end


always@ (posedge clk)
begin
    if (ce)
    begin
        mem_addr_reg <= mem_addr_in;
        ctrl_reg <= ctrl_in;
        x_in_reg1 <= x_in;
        x_in_reg2 <= x_in_reg1;
    end
end


assign y_out = 
(mac_out >= SATURATED_MAX) ? (SATURATED_MAX) : 
(mac_out <= SATURATED_MIN) ? (SATURATED_MIN) : 
(mac_out[WIDTH-1:0]);


assign x_out = x_in_reg2;


assign ctrl_out = ctrl_reg;
assign mem_addr_out = mem_addr_reg;

endmodule
module systolic_cell 
    (clk, ce, ctrl_in, ctrl_out, mem_addr_in, mem_addr_out, y_in, y_out, x_in, x_out);



    parameter WIDTH = 8;
    parameter MEM_ADDR_WIDTH = 4;
    parameter ROM_FILE = "weights/cell-weights.mem";
    localparam ACCUM_WIDTH = WIDTH * 2;
    localparam SATURATED_MAX = (1 << WIDTH - 1) - 1;
    localparam SATURATED_MIN = -(1 << WIDTH - 1);


    input clk, ce;
    input [31:0] ctrl_in; 
    input [MEM_ADDR_WIDTH-1:0] mem_addr_in;
    input signed [WIDTH-1:0] y_in, x_in;
    output signed [WIDTH-1:0] y_out, x_out;
    output [31:0] ctrl_out; 
    output [MEM_ADDR_WIDTH-1:0] mem_addr_out;


wire signed [ACCUM_WIDTH-1:0] mac_out;
wire signed [WIDTH-1:0] kernel_weight;
reg [31:0] ctrl_reg;
reg [MEM_ADDR_WIDTH-1:0] mem_addr_reg;
reg signed [WIDTH-1:0] x_in_reg1, x_in_reg2;


mac mac_inst
(
    clk, ce, 
    x_in, kernel_weight, y_in, 
    mac_out
);
defparam mac_inst.WIDTH = WIDTH;


rom cell_memory
(
    clk, 1'b1,
    mem_addr_reg, 
    kernel_weight
);
defparam cell_memory.ADDR_WIDTH = MEM_ADDR_WIDTH;
defparam cell_memory.DATA_WIDTH = WIDTH;
defparam cell_memory.ROM_FILE = ROM_FILE;


initial
begin
    mem_addr_reg = 0;
    ctrl_reg = 0;
    x_in_reg1 = 0;
    x_in_reg2 = 0;
end


always@ (posedge clk)
begin
    if (ce)
    begin
        mem_addr_reg <= mem_addr_in;
        ctrl_reg <= ctrl_in;
        x_in_reg1 <= x_in;
        x_in_reg2 <= x_in_reg1;
    end
end


assign y_out = 
(mac_out >= SATURATED_MAX) ? (SATURATED_MAX) : 
(mac_out <= SATURATED_MIN) ? (SATURATED_MIN) : 
(mac_out[WIDTH-1:0]);


assign x_out = x_in_reg2;


assign ctrl_out = ctrl_reg;
assign mem_addr_out = mem_addr_reg;

endmodule