data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_1/new/bcd_tester.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_1/new/bcd_tester.v:32: Unsupported: Ignoring delay on this delayed statement.\n    always #10 clock = ~clock;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_1/new/bcd_tester.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #0 up = 1; down = 0; set0 = 0; set9 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_1/new/bcd_tester.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #400 up = 0; down = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_1/new/bcd_tester.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #400 up = 1; down = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_1/new/bcd_tester.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #100 up = 0; down = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_1/new/bcd_tester.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #100 up = 1; down = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_1/new/bcd_tester.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #400 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_1/new/bcd_tester.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #0 in = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_1/new/bcd_tester.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #50 in = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_1/new/bcd_tester.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #40 in = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_1/new/bcd_tester.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #50 in = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_1/new/bcd_tester.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #30 in = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_1/new/bcd_tester.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #5 in = 0;\n        ^\n%Error: data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_1/new/bcd_tester.v:30: Cannot find file containing module: \'OneDigitBCDCounter\'\n    OneDigitBCDCounter counter(count[3],count[2],count[1],count[0],cout,bout,up,down,set9,set0,clock);\n    ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_1/new,data/full_repos/permissive/423958267/OneDigitBCDCounter\n             data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_1/new,data/full_repos/permissive/423958267/OneDigitBCDCounter.v\n             data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_1/new,data/full_repos/permissive/423958267/OneDigitBCDCounter.sv\n             OneDigitBCDCounter\n             OneDigitBCDCounter.v\n             OneDigitBCDCounter.sv\n             obj_dir/OneDigitBCDCounter\n             obj_dir/OneDigitBCDCounter.v\n             obj_dir/OneDigitBCDCounter.sv\n%Error: data/full_repos/permissive/423958267/lab03/lab03.srcs/sim_1/new/bcd_tester.v:48: Cannot find file containing module: \'SinglePulser\'\n    SinglePulser pulser(out,in,clock);\n    ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bcd_tester(

);
    reg clock;
    wire [3:0] count;
    wire cout, bout;
    reg up, down, set9, set0;
    OneDigitBCDCounter counter(count[3],count[2],count[1],count[0],cout,bout,up,down,set9,set0,clock);

    always #10 clock = ~clock;
    
    initial clock = 0;
    
    initial
    begin
        #0 up = 1; down = 0; set0 = 0; set9 = 0;
        #400 up = 0; down = 1;
        #400 up = 1; down = 0;
        #100 up = 0; down = 1;
        #100 up = 1; down = 0;
        #400 $finish;
    end
    
    wire out;
    reg in;
    SinglePulser pulser(out,in,clock);

    initial
    begin
        #0 in = 1;
        #50 in = 0;
        #40 in = 1;
        #50 in = 0;
        #30 in = 1;
        #5 in = 0;

    end

endmodule
module bcd_tester(

);

    reg clock;
    wire [3:0] count;
    wire cout, bout;
    reg up, down, set9, set0;
    OneDigitBCDCounter counter(count[3],count[2],count[1],count[0],cout,bout,up,down,set9,set0,clock);

    always #10 clock = ~clock;
    
    initial clock = 0;
    
    initial
    begin
        #0 up = 1; down = 0; set0 = 0; set9 = 0;
        #400 up = 0; down = 1;
        #400 up = 1; down = 0;
        #100 up = 0; down = 1;
        #100 up = 1; down = 0;
        #400 $finish;
    end
    
    wire out;
    reg in;
    SinglePulser pulser(out,in,clock);

    initial
    begin
        #0 in = 1;
        #50 in = 0;
        #40 in = 1;
        #50 in = 0;
        #30 in = 1;
        #5 in = 0;

    end

endmodule