data/full_repos/permissive/463395574/MIO_BUS.v
1: b'%Error: data/full_repos/permissive/463395574/MIO_BUS.v:3: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v.v\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/463395574/MIO_BUS.v:17: Define or directive not defined: \'`ADDR_SIZE\'\n    output reg [`ADDR_SIZE-1:0] ram_addr,       \n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/MIO_BUS.v:27: Define or directive not defined: \'`ADDR_SIZE\'\n    ram_addr = `ADDR_SIZE\'h0;\n               ^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module MIO_BUS(
    input mem_w,
    input [15:0]  sw_i,
    input [31:0]  cpu_data_out,
    input [31:0]  cpu_data_addr,
    input [2:0]   cpu_data_amp,
    input [31:0]  ram_data_out,

    output reg [31:0]  cpu_data_in,
    output reg [31:0]  ram_data_in,
    output reg [`ADDR_SIZE-1:0] ram_addr,
    output reg [31:0]  cpuseg7_data,
    output reg         ram_we,
    output reg [2:0]   ram_amp,
    output reg         seg7_we
);



  always @(*) begin
    ram_addr = `ADDR_SIZE'h0;
    ram_data_in = 32'h0;
    cpuseg7_data = 32'h0;
    cpu_data_in = 32'h0;
    seg7_we = 0;
    ram_we = 0;
    ram_amp = 3'b0;

    case(cpu_data_addr[31:0])
      32'hffff0004:
        cpu_data_in = {16'h0, sw_i};
      32'hffff000c: begin
        cpuseg7_data = cpu_data_out;
        seg7_we = mem_w;
      end
      default: begin
        ram_addr = cpu_data_addr;
        ram_data_in = cpu_data_out;
        ram_we = mem_w;
        ram_amp = cpu_data_amp;
        cpu_data_in = ram_data_out;
      end
    endcase
  end

endmodule
module MIO_BUS(
    input mem_w,
    input [15:0]  sw_i,
    input [31:0]  cpu_data_out,
    input [31:0]  cpu_data_addr,
    input [2:0]   cpu_data_amp,
    input [31:0]  ram_data_out,

    output reg [31:0]  cpu_data_in,
    output reg [31:0]  ram_data_in,
    output reg [`ADDR_SIZE-1:0] ram_addr,
    output reg [31:0]  cpuseg7_data,
    output reg         ram_we,
    output reg [2:0]   ram_amp,
    output reg         seg7_we
);




  always @(*) begin
    ram_addr = `ADDR_SIZE'h0;
    ram_data_in = 32'h0;
    cpuseg7_data = 32'h0;
    cpu_data_in = 32'h0;
    seg7_we = 0;
    ram_we = 0;
    ram_amp = 3'b0;

    case(cpu_data_addr[31:0])
      32'hffff0004:
        cpu_data_in = {16'h0, sw_i};
      32'hffff000c: begin
        cpuseg7_data = cpu_data_out;
        seg7_we = mem_w;
      end
      default: begin
        ram_addr = cpu_data_addr;
        ram_data_in = cpu_data_out;
        ram_we = mem_w;
        ram_amp = cpu_data_amp;
        cpu_data_in = ram_data_out;
      end
    endcase
  end

endmodule