data/full_repos/permissive/446997925/hw3/or.v
data/verilator_xmls/91d6b0c7-80e9-4fd8-b698-4e241996a499.xml
module or_16(out, a, b);
input [15:0] a, b;
output [15:0] out;

or_8 f(out[7:0], a[7:0], b[7:0]),
          s(out[15:8], a[15:8], b[15:8]);
endmodule
module or_16(out, a, b);

input [15:0] a, b;
output [15:0] out;

or_8 f(out[7:0], a[7:0], b[7:0]),
          s(out[15:8], a[15:8], b[15:8]);
endmodule