data/full_repos/permissive/449807379/CPU_design/memory_control.v
data/verilator_xmls/044d34f6-11ee-4a6b-8775-17de7c15ef8b.xml
module memory_control(source1, source2, alu_result, opcode, address, rw, datain, dataout, en, LDR_sel, address_sel);

input [31:0] source1, source2, alu_result, datain;
input [3:0] opcode;

output reg [31:0] dataout;
output reg rw;
output reg en;
output reg [15:0] address;
output reg LDR_sel, address_sel;

always @ (*)
begin

if( opcode == 4'b1001)
begin

	
	address = source1[15:0];
	LDR_sel = 1'b1;
	address_sel = 1'b1;
	rw = 1'b1;
	en = 1'b1;

end
else if( opcode == 4'b1010 )
begin


	address = source1[15:0];
	dataout = source2;
	LDR_sel = 1'b0;
	address_sel = 1'b1;
	en = 1'b1;
	rw = 1'b0;
	
end
else
begin

	en = 1'b1;
	rw = 1'b1;
	LDR_sel = 1'b0;
	address_sel = 1'b0;
end

end










endmodule
module memory_control(source1, source2, alu_result, opcode, address, rw, datain, dataout, en, LDR_sel, address_sel);


input [31:0] source1, source2, alu_result, datain;
input [3:0] opcode;

output reg [31:0] dataout;
output reg rw;
output reg en;
output reg [15:0] address;
output reg LDR_sel, address_sel;

always @ (*)
begin

if( opcode == 4'b1001)
begin

	
	address = source1[15:0];
	LDR_sel = 1'b1;
	address_sel = 1'b1;
	rw = 1'b1;
	en = 1'b1;

end
else if( opcode == 4'b1010 )
begin


	address = source1[15:0];
	dataout = source2;
	LDR_sel = 1'b0;
	address_sel = 1'b1;
	en = 1'b1;
	rw = 1'b0;
	
end
else
begin

	en = 1'b1;
	rw = 1'b1;
	LDR_sel = 1'b0;
	address_sel = 1'b0;
end

end










endmodule