data/full_repos/permissive/467394306/qsim_rtl/tb_ctrl/tb_ctrl.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/467394306/qsim_rtl/tb_ctrl/tb_ctrl.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/467394306/qsim_rtl/tb_ctrl/tb_ctrl.v:43: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/467394306/qsim_rtl/tb_ctrl/tb_ctrl.v:48: syntax error, unexpected \'@\'\n  @(posedge clk);    \n  ^\n%Error: data/full_repos/permissive/467394306/qsim_rtl/tb_ctrl/tb_ctrl.v:54: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/467394306/qsim_rtl/tb_ctrl/tb_ctrl.v:56: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/467394306/qsim_rtl/tb_ctrl/tb_ctrl.v:58: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/467394306/qsim_rtl/tb_ctrl/tb_ctrl.v:60: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/467394306/qsim_rtl/tb_ctrl/tb_ctrl.v:67: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/467394306/qsim_rtl/tb_ctrl/tb_ctrl.v:76: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/467394306/qsim_rtl/tb_ctrl/tb_ctrl.v:82: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: Exiting due to 9 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();

	reg clk;
	reg rstn;
	reg enable;

	reg [1:0] mode;

	reg data_load;
	reg [7:0] data_in;



	wire [16*8 - 1 : 0] aouts, wouts;
	wire saclk;
	wire fire, done;

	integer i;
	

	ARR_CTRL_16x16 ARR_CTRL_16x16_0 ( .clk(clk), .rstn(rstn), .enable(enable), .mode(mode), .data_load(data_load), .data_in(data_in), .aouts(aouts), .wouts(wouts), .saclk(saclk), .fire(fire), .done(done));

	always begin
		`HALF_CLOCK_PERIOD;
		clk = ~clk;
	end

	initial begin

		clk = 0;
		rstn = 0;
		enable = 0;
		mode = 2'b00;
		data_load = 0;
		data_in = 8'd0;
		
		@(posedge clk);

		@(negedge clk);
		rstn = 1;      

		@(posedge clk);
		
		enable = 1;
		data_load = 1;
		mode = 2'b00;
		data_in = 8'd16;
		@(posedge clk);
		data_in = 8'd3;
		@(posedge clk);
		data_in = 8'd16;
		@(posedge clk);
		data_in = 8'd16;
		@(posedge clk);

		mode = 2'b01;
		data_in = 8'd0;


		for (i=0; i<3*3*3*16; i=i+1) begin
			@(posedge clk);
			data_in = data_in +1;
		end

                mode = 2'b10;
		data_in = 8'd0;


		for (i=0; i<3*16*16; i=i+1) begin
			@(posedge clk);
			data_in = data_in +1;
		end

		for (i=0; i<`SIM_CYCLES; i=i+1) begin
			mode = 2'b11;
			@(posedge clk);
		end


		
		$finish;
	end 

endmodule
module testbench();


	reg clk;
	reg rstn;
	reg enable;

	reg [1:0] mode;

	reg data_load;
	reg [7:0] data_in;



	wire [16*8 - 1 : 0] aouts, wouts;
	wire saclk;
	wire fire, done;

	integer i;
	

	ARR_CTRL_16x16 ARR_CTRL_16x16_0 ( .clk(clk), .rstn(rstn), .enable(enable), .mode(mode), .data_load(data_load), .data_in(data_in), .aouts(aouts), .wouts(wouts), .saclk(saclk), .fire(fire), .done(done));

	always begin
		`HALF_CLOCK_PERIOD;
		clk = ~clk;
	end

	initial begin

		clk = 0;
		rstn = 0;
		enable = 0;
		mode = 2'b00;
		data_load = 0;
		data_in = 8'd0;
		
		@(posedge clk);

		@(negedge clk);
		rstn = 1;      

		@(posedge clk);
		
		enable = 1;
		data_load = 1;
		mode = 2'b00;
		data_in = 8'd16;
		@(posedge clk);
		data_in = 8'd3;
		@(posedge clk);
		data_in = 8'd16;
		@(posedge clk);
		data_in = 8'd16;
		@(posedge clk);

		mode = 2'b01;
		data_in = 8'd0;


		for (i=0; i<3*3*3*16; i=i+1) begin
			@(posedge clk);
			data_in = data_in +1;
		end

                mode = 2'b10;
		data_in = 8'd0;


		for (i=0; i<3*16*16; i=i+1) begin
			@(posedge clk);
			data_in = data_in +1;
		end

		for (i=0; i<`SIM_CYCLES; i=i+1) begin
			mode = 2'b11;
			@(posedge clk);
		end


		
		$finish;
	end 

endmodule