data/full_repos/permissive/419538859/lab7/lab7_1self/lab7_1self4.v
1: b'%Warning-WIDTH: data/full_repos/permissive/419538859/lab7/lab7_1self/lab7_1self4.v:19: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s VARREF \'timer1\' generates 2 bits.\n                                                                                     : ... In instance lab7_1self4\n    (seg7_sel == 3\'b100 )? timer1 :\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab7/lab7_1self/lab7_1self4.v:21: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s VARREF \'timer3\' generates 2 bits.\n                                                                                     : ... In instance lab7_1self4\n    (seg7_sel == 3\'b010 )? timer3 :4\'b0;\n                         ^\n%Error: Exiting due to 2 warning(s)\n'
module 		seg7_select(clk,reset,seg7_sel);

parameter	num_use= 6;
input		clk,reset;
output		[2:0]seg7_sel;
reg			[2:0]seg7_sel;

always@ (posedge clk or posedge reset) 
begin
	if(reset == 1)
		seg7_sel = 3'b101;
	else
		if(seg7_sel == 6 -num_use)
			seg7_sel = 3'b101;
		else
			seg7_sel = seg7_sel-3'b001;
	end
endmodule
module 		seg7_select(clk,reset,seg7_sel);


parameter	num_use= 6;
input		clk,reset;
output		[2:0]seg7_sel;
reg			[2:0]seg7_sel;

always@ (posedge clk or posedge reset) 
begin
	if(reset == 1)
		seg7_sel = 3'b101;
	else
		if(seg7_sel == 6 -num_use)
			seg7_sel = 3'b101;
		else
			seg7_sel = seg7_sel-3'b001;
	end
endmodule