data/full_repos/permissive/487478597/riscv_pipedline_cpu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:307: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Raddr1 = instruction[19:15];\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:308: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Raddr2 = instruction[24:20];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:309: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Waddr = instruction[11:7];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:26: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s EQ generates 1 bits.\n                                                                             : ... In instance top.uut11\n            4\'h4: ALUResult = (in1 == in2);  \n                            ^\n%Error: Exiting due to 4 warning(s)\n'
module branch_forward #(parameter addr_width = 8)(
    input Branch,
    input [addr_width-1:0] rs1,
    input [addr_width-1:0] rs2,
    input [addr_width-1:0] MEM_rd,
    input MEM_RegWrite,
    input MEM_MemRead,
    input [addr_width-1:0] EX_rd,
    input EX_RegWrite,
    output reg forward_1,
    output reg forward_2,
    output reg stall
);
    initial begin forward_1 = 0; forward_2 = 0; stall = 0; end
    always @(*) begin
        if (Branch == 1) begin
            forward_1 = ((MEM_rd == rs1) & MEM_RegWrite & ~MEM_MemRead);
            forward_2 = ((MEM_rd == rs2) & MEM_RegWrite & ~MEM_MemRead);
            stall = (MEM_RegWrite & MEM_MemRead & (MEM_rd == rs1 | MEM_rd == rs2)) | (EX_RegWrite & (EX_rd == rs1 | EX_rd == rs2));
        end 
        else begin {forward_1, forward_2, stall} = 3'b000; end
    end

endmodule
module branch_forward #(parameter addr_width = 8)(
    input Branch,
    input [addr_width-1:0] rs1,
    input [addr_width-1:0] rs2,
    input [addr_width-1:0] MEM_rd,
    input MEM_RegWrite,
    input MEM_MemRead,
    input [addr_width-1:0] EX_rd,
    input EX_RegWrite,
    output reg forward_1,
    output reg forward_2,
    output reg stall
);

    initial begin forward_1 = 0; forward_2 = 0; stall = 0; end
    always @(*) begin
        if (Branch == 1) begin
            forward_1 = ((MEM_rd == rs1) & MEM_RegWrite & ~MEM_MemRead);
            forward_2 = ((MEM_rd == rs2) & MEM_RegWrite & ~MEM_MemRead);
            stall = (MEM_RegWrite & MEM_MemRead & (MEM_rd == rs1 | MEM_rd == rs2)) | (EX_RegWrite & (EX_rd == rs1 | EX_rd == rs2));
        end 
        else begin {forward_1, forward_2, stall} = 3'b000; end
    end

endmodule