data/full_repos/permissive/449767923/v2/wbcores/simple_spi/bench/verilog/wb_master_model.v
1: b'%Error: data/full_repos/permissive/449767923/v2/wbcores/simple_spi/bench/verilog/wb_master_model.v:50: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/449767923/v2/wbcores/simple_spi/bench/verilog,data/full_repos/permissive/449767923/timescale.v\n             data/full_repos/permissive/449767923/v2/wbcores/simple_spi/bench/verilog,data/full_repos/permissive/449767923/timescale.v.v\n             data/full_repos/permissive/449767923/v2/wbcores/simple_spi/bench/verilog,data/full_repos/permissive/449767923/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/449767923/v2/wbcores/simple_spi/bench/verilog/wb_master_model.v:94: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/449767923/v2/wbcores/simple_spi/bench/verilog/wb_master_model.v:113: syntax error, unexpected \'@\'\n  repeat(delay) @(posedge clk);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/449767923/v2/wbcores/simple_spi/bench/verilog/wb_master_model.v:116: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/449767923/v2/wbcores/simple_spi/bench/verilog/wb_master_model.v:123: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/449767923/v2/wbcores/simple_spi/bench/verilog/wb_master_model.v:126: syntax error, unexpected \'@\'\n  while(~ack) @(posedge clk);\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/449767923/v2/wbcores/simple_spi/bench/verilog/wb_master_model.v:129: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/449767923/v2/wbcores/simple_spi/bench/verilog/wb_master_model.v:155: syntax error, unexpected \'@\'\n  repeat(delay) @(posedge clk);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/449767923/v2/wbcores/simple_spi/bench/verilog/wb_master_model.v:158: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/449767923/v2/wbcores/simple_spi/bench/verilog/wb_master_model.v:165: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/449767923/v2/wbcores/simple_spi/bench/verilog/wb_master_model.v:168: syntax error, unexpected \'@\'\n  while(~ack) @(posedge clk);\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/449767923/v2/wbcores/simple_spi/bench/verilog/wb_master_model.v:171: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: Exiting due to 7 error(s), 5 warning(s)\n'
module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);

parameter dwidth = 32;
parameter awidth = 32;

input               clk, rst;
output [awidth:1]   adr;
input  [dwidth:1]   din;
output [dwidth:1]   dout;
output              cyc, stb;
output              we;
output [dwidth/8:1] sel;
input               ack, err, rty;






reg [awidth:1]   adr;
reg [dwidth:1]   dout;
reg              cyc, stb;
reg              we;
reg [dwidth/8:1] sel;

reg [dwidth:1]   q;






initial
	begin


		adr  = {awidth{1'bx}};
		dout = {dwidth{1'bx}};
		cyc  = 1'b0;
		stb  = 1'bx;
		we   = 1'hx;
		sel  = {dwidth/8{1'bx}};
		#1;
		$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
	end






task wb_write;
	input   delay;
	integer delay;

	input	[awidth:1] a;
	input	[dwidth:1] d;

	begin


		repeat(delay) @(posedge clk);


		#1;
		adr  = a;
		dout = d;
		cyc  = 1'b1;
		stb  = 1'b1;
		we   = 1'b1;
		sel  = {dwidth/8{1'b1}};
		@(posedge clk);


		while(~ack) @(posedge clk);


		#1;
		cyc  = 1'b0;
		stb  = 1'bx;
		adr  = {awidth{1'bx}};
		dout = {dwidth{1'bx}};
		we   = 1'hx;
		sel  = {dwidth/8{1'bx}};

	end
endtask






task wb_read;
	input   delay;
	integer delay;

	input   [awidth:1] a;
	output  [dwidth:1] d;

	begin


		repeat(delay) @(posedge clk);


		#1;
		adr  = a;
		dout = {dwidth{1'bx}};
		cyc  = 1'b1;
		stb  = 1'b1;
		we   = 1'b0;
		sel  = {dwidth/8{1'b1}};
		@(posedge clk);


		while(~ack) @(posedge clk);


		#1;
		cyc  = 1'b0;
		stb  = 1'bx;
		adr  = {awidth{1'bx}};
		dout = {dwidth{1'bx}};
		we   = 1'hx;
		sel  = {dwidth/8{1'bx}};
		d    = din;

	end
endtask






task wb_cmp;
	input   delay;
	integer delay;

	input [awidth:1] a;
	input [dwidth:1] d_exp;

	begin
	  wb_read (delay, a, q);

	  if (d_exp !== q)
	    $display("Data compare error. Received %h, expected %h at time %t", q, d_exp, $time);
	end
endtask

endmodule
module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);


parameter dwidth = 32;
parameter awidth = 32;

input               clk, rst;
output [awidth:1]   adr;
input  [dwidth:1]   din;
output [dwidth:1]   dout;
output              cyc, stb;
output              we;
output [dwidth/8:1] sel;
input               ack, err, rty;






reg [awidth:1]   adr;
reg [dwidth:1]   dout;
reg              cyc, stb;
reg              we;
reg [dwidth/8:1] sel;

reg [dwidth:1]   q;






initial
	begin


		adr  = {awidth{1'bx}};
		dout = {dwidth{1'bx}};
		cyc  = 1'b0;
		stb  = 1'bx;
		we   = 1'hx;
		sel  = {dwidth/8{1'bx}};
		#1;
		$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
	end






task wb_write;
	input   delay;
	integer delay;

	input	[awidth:1] a;
	input	[dwidth:1] d;

	begin


		repeat(delay) @(posedge clk);


		#1;
		adr  = a;
		dout = d;
		cyc  = 1'b1;
		stb  = 1'b1;
		we   = 1'b1;
		sel  = {dwidth/8{1'b1}};
		@(posedge clk);


		while(~ack) @(posedge clk);


		#1;
		cyc  = 1'b0;
		stb  = 1'bx;
		adr  = {awidth{1'bx}};
		dout = {dwidth{1'bx}};
		we   = 1'hx;
		sel  = {dwidth/8{1'bx}};

	end
endtask






task wb_read;
	input   delay;
	integer delay;

	input   [awidth:1] a;
	output  [dwidth:1] d;

	begin


		repeat(delay) @(posedge clk);


		#1;
		adr  = a;
		dout = {dwidth{1'bx}};
		cyc  = 1'b1;
		stb  = 1'b1;
		we   = 1'b0;
		sel  = {dwidth/8{1'b1}};
		@(posedge clk);


		while(~ack) @(posedge clk);


		#1;
		cyc  = 1'b0;
		stb  = 1'bx;
		adr  = {awidth{1'bx}};
		dout = {dwidth{1'bx}};
		we   = 1'hx;
		sel  = {dwidth/8{1'bx}};
		d    = din;

	end
endtask






task wb_cmp;
	input   delay;
	integer delay;

	input [awidth:1] a;
	input [dwidth:1] d_exp;

	begin
	  wb_read (delay, a, q);

	  if (d_exp !== q)
	    $display("Data compare error. Received %h, expected %h at time %t", q, d_exp, $time);
	end
endtask

endmodule