data/full_repos/permissive/488739248/rtl/ttl/ttl_74155.v
1: b'%Error: data/full_repos/permissive/488739248/rtl/ttl/ttl_74155.v:2: Cannot find include file: helper.v\n`include "helper.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/488739248/rtl/ttl,data/full_repos/permissive/488739248/helper.v\n             data/full_repos/permissive/488739248/rtl/ttl,data/full_repos/permissive/488739248/helper.v.v\n             data/full_repos/permissive/488739248/rtl/ttl,data/full_repos/permissive/488739248/helper.v.sv\n             helper.v\n             helper.v.v\n             helper.v.sv\n             obj_dir/helper.v\n             obj_dir/helper.v.v\n             obj_dir/helper.v.sv\n%Error: data/full_repos/permissive/488739248/rtl/ttl/ttl_74155.v:43: Define or directive not defined: \'`PACK_ARRAY\'\nassign #(DELAY_RISE, DELAY_FALL) Y_2D = `PACK_ARRAY(BLOCKS_DIFFERENT, WIDTH_OUT, computed)\n                                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/488739248/rtl/ttl/ttl_74155.v:43: syntax error, unexpected \',\'\nassign #(DELAY_RISE, DELAY_FALL) Y_2D = `PACK_ARRAY(BLOCKS_DIFFERENT, WIDTH_OUT, computed)\n                                                                    ^\n%Error: Cannot continue\n'
module ttl_74155 #(parameter BLOCKS_DIFFERENT = 2, BLOCK0 = 0, BLOCK1 = 1, WIDTH_OUT = 4,
                   WIDTH_IN = $clog2(WIDTH_OUT), DELAY_RISE = 13, DELAY_FALL = 18)
(
  input Enable1C,
  input Enable1G_bar,
  input Enable2C_bar,
  input Enable2G_bar,
  input [WIDTH_IN-1:0] A,
  output [BLOCKS_DIFFERENT*WIDTH_OUT-1:0] Y_2D
);


reg [WIDTH_OUT-1:0] computed [0:BLOCKS_DIFFERENT-1];
integer i;

always @(*)
begin
  for (i = 0; i < WIDTH_OUT; i=i+1)
  begin
    if (Enable1C && !Enable1G_bar && i == A)
      computed[BLOCK0][i] = 1'b0;
    else
      computed[BLOCK0][i] = 1'b1;

    if (!Enable2C_bar && !Enable2G_bar && i == A)
      computed[BLOCK1][i] = 1'b0;
    else
      computed[BLOCK1][i] = 1'b1;
  end
end


assign #(DELAY_RISE, DELAY_FALL) Y_2D = `PACK_ARRAY(BLOCKS_DIFFERENT, WIDTH_OUT, computed)

endmodule
module ttl_74155 #(parameter BLOCKS_DIFFERENT = 2, BLOCK0 = 0, BLOCK1 = 1, WIDTH_OUT = 4,
                   WIDTH_IN = $clog2(WIDTH_OUT), DELAY_RISE = 13, DELAY_FALL = 18)
(
  input Enable1C,
  input Enable1G_bar,
  input Enable2C_bar,
  input Enable2G_bar,
  input [WIDTH_IN-1:0] A,
  output [BLOCKS_DIFFERENT*WIDTH_OUT-1:0] Y_2D
);



reg [WIDTH_OUT-1:0] computed [0:BLOCKS_DIFFERENT-1];
integer i;

always @(*)
begin
  for (i = 0; i < WIDTH_OUT; i=i+1)
  begin
    if (Enable1C && !Enable1G_bar && i == A)
      computed[BLOCK0][i] = 1'b0;
    else
      computed[BLOCK0][i] = 1'b1;

    if (!Enable2C_bar && !Enable2G_bar && i == A)
      computed[BLOCK1][i] = 1'b0;
    else
      computed[BLOCK1][i] = 1'b1;
  end
end


assign #(DELAY_RISE, DELAY_FALL) Y_2D = `PACK_ARRAY(BLOCKS_DIFFERENT, WIDTH_OUT, computed)

endmodule