data/full_repos/permissive/485295380/UART com/uart_tx_tb.v
1: b'%Error: Cannot find file containing module: com,data/full_repos/permissive/485295380\n        ... Looked in:\n             data/full_repos/permissive/485295380/UART/com,data/full_repos/permissive/485295380\n             data/full_repos/permissive/485295380/UART/com,data/full_repos/permissive/485295380.v\n             data/full_repos/permissive/485295380/UART/com,data/full_repos/permissive/485295380.sv\n             com,data/full_repos/permissive/485295380\n             com,data/full_repos/permissive/485295380.v\n             com,data/full_repos/permissive/485295380.sv\n             obj_dir/com,data/full_repos/permissive/485295380\n             obj_dir/com,data/full_repos/permissive/485295380.v\n             obj_dir/com,data/full_repos/permissive/485295380.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/485295380/UART\n%Error: Cannot find file containing module: com/uart_tx_tb.v\n%Error: Exiting due to 3 error(s)\n'
module uart_tb;
    reg clk;			
	reg rst;			

	reg uart_en;			
	wire uart_tx;			
	wire uart_busy;			
	reg[7:0] data;


	uart_transmit uut(
		.clk(clk),		
		.rst(rst),		
		.uart_en(uart_en),			
		.uart_tx(uart_tx),		
		.uart_busy(uart_busy)
	);


	always begin
		#271.27 
		clk = 1'b0;
		#271.27 
		clk = 1'b1;
	end

	initial begin

		clk = 1;
		rst = 1;
		uart_en = 0;
		#100 
		rst = 0;
		#100
		uart_en = 1;

		send(8'h75);
	end


	task send;
		input [7:0] char;
		begin
			wait(!clk);
			wait(clk); 
			#1 
			data = {char};

			wait(!clk);
			wait(clk); 
			#1 uart_en = 1;
			wait(!clk);
			wait(clk); #1 uart_en = 0;

			wait(!clk);
			wait(clk); 
			#1
			 data = 8'hx;
		end
	endtask

endmodule
module uart_tb;

    reg clk;			
	reg rst;			

	reg uart_en;			
	wire uart_tx;			
	wire uart_busy;			
	reg[7:0] data;


	uart_transmit uut(
		.clk(clk),		
		.rst(rst),		
		.uart_en(uart_en),			
		.uart_tx(uart_tx),		
		.uart_busy(uart_busy)
	);


	always begin
		#271.27 
		clk = 1'b0;
		#271.27 
		clk = 1'b1;
	end

	initial begin

		clk = 1;
		rst = 1;
		uart_en = 0;
		#100 
		rst = 0;
		#100
		uart_en = 1;

		send(8'h75);
	end


	task send;
		input [7:0] char;
		begin
			wait(!clk);
			wait(clk); 
			#1 
			data = {char};

			wait(!clk);
			wait(clk); 
			#1 uart_en = 1;
			wait(!clk);
			wait(clk); #1 uart_en = 0;

			wait(!clk);
			wait(clk); 
			#1
			 data = 8'hx;
		end
	endtask

endmodule