data/full_repos/permissive/425529933/Proyecto1Digitales2/phy/phy_e.v
data/verilator_xmls/48a23935-edb4-47cd-985d-3864d06e071d.xml
module phy_e(clk_32f, reset, valid_in, Data_in, valid_out_e, Data_out_e);
  (* src = "phy_e.v:53" *)
  reg [31:0] _0_;
  (* src = "phy_e.v:53" *)
  reg _1_;
  (* src = "phy_e.v:16" *)
  wire [31:0] Data;
  (* src = "phy_e.v:9" *)
  input [31:0] Data_in;
  (* src = "phy_e.v:14" *)
  wire Data_out_1bit_0_c;
  (* src = "phy_e.v:15" *)
  wire Data_out_1bit_1_c;
  (* src = "phy_e.v:11" *)
  output [31:0] Data_out_e;
  reg [31:0] Data_out_e;
  (* src = "phy_e.v:26" *)
  wire clk_2f_e;
  (* src = "phy_e.v:6" *)
  input clk_32f;
  (* src = "phy_e.v:27" *)
  wire clk_4f_e;
  (* src = "phy_e.v:36" *)
  wire clk_f_c;
  (* src = "phy_e.v:7" *)
  input reset;
  (* src = "phy_e.v:17" *)
  wire valid;
  (* src = "phy_e.v:8" *)
  input valid_in;
  (* src = "phy_e.v:10" *)
  output valid_out_e;
  reg valid_out_e;
  (* module_not_derived = 32'd1 *)
  (* src = "phy_e.v:32" *)
  clk_generator_e clk_generador (
    .clk_2f_e(clk_2f_e),
    .clk_32f(clk_32f),
    .clk_4f_e(clk_4f_e),
    .clk_f_c(clk_f_c),
    .reset(reset)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "phy_e.v:41" *)
  phy_rx_e phy_rx_c00 (
    .Data_in_0(Data_out_1bit_0_c),
    .Data_in_1(Data_out_1bit_1_c),
    .Data_out_e(Data),
    .clk_2f_e(clk_2f_e),
    .clk_32f(clk_32f),
    .clk_4f_e(clk_4f_e),
    .reset(reset),
    .valid_out_e(valid)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "phy_e.v:19" *)
  phy_tx_e phy_tx_c00 (
    .Data_in(Data_in),
    .Data_out_1bit_0_c(Data_out_1bit_0_c),
    .Data_out_1bit_1_c(Data_out_1bit_1_c),
    .clk_2f_e(clk_2f_e),
    .clk_32f(clk_32f),
    .clk_4f_e(clk_4f_e),
    .reset(reset),
    .valid_in(valid_in)
  );
  always @* begin
    _1_ = valid;
    _0_ = Data;
  end
  always @* begin
      valid_out_e <= _1_;
      Data_out_e <= _0_;
  end
endmodule
module phy_e(clk_32f, reset, valid_in, Data_in, valid_out_e, Data_out_e);

  (* src = "phy_e.v:53" *)
  reg [31:0] _0_;
  (* src = "phy_e.v:53" *)
  reg _1_;
  (* src = "phy_e.v:16" *)
  wire [31:0] Data;
  (* src = "phy_e.v:9" *)
  input [31:0] Data_in;
  (* src = "phy_e.v:14" *)
  wire Data_out_1bit_0_c;
  (* src = "phy_e.v:15" *)
  wire Data_out_1bit_1_c;
  (* src = "phy_e.v:11" *)
  output [31:0] Data_out_e;
  reg [31:0] Data_out_e;
  (* src = "phy_e.v:26" *)
  wire clk_2f_e;
  (* src = "phy_e.v:6" *)
  input clk_32f;
  (* src = "phy_e.v:27" *)
  wire clk_4f_e;
  (* src = "phy_e.v:36" *)
  wire clk_f_c;
  (* src = "phy_e.v:7" *)
  input reset;
  (* src = "phy_e.v:17" *)
  wire valid;
  (* src = "phy_e.v:8" *)
  input valid_in;
  (* src = "phy_e.v:10" *)
  output valid_out_e;
  reg valid_out_e;
  (* module_not_derived = 32'd1 *)
  (* src = "phy_e.v:32" *)
  clk_generator_e clk_generador (
    .clk_2f_e(clk_2f_e),
    .clk_32f(clk_32f),
    .clk_4f_e(clk_4f_e),
    .clk_f_c(clk_f_c),
    .reset(reset)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "phy_e.v:41" *)
  phy_rx_e phy_rx_c00 (
    .Data_in_0(Data_out_1bit_0_c),
    .Data_in_1(Data_out_1bit_1_c),
    .Data_out_e(Data),
    .clk_2f_e(clk_2f_e),
    .clk_32f(clk_32f),
    .clk_4f_e(clk_4f_e),
    .reset(reset),
    .valid_out_e(valid)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "phy_e.v:19" *)
  phy_tx_e phy_tx_c00 (
    .Data_in(Data_in),
    .Data_out_1bit_0_c(Data_out_1bit_0_c),
    .Data_out_1bit_1_c(Data_out_1bit_1_c),
    .clk_2f_e(clk_2f_e),
    .clk_32f(clk_32f),
    .clk_4f_e(clk_4f_e),
    .reset(reset),
    .valid_in(valid_in)
  );
  always @* begin
    _1_ = valid;
    _0_ = Data;
  end
  always @* begin
      valid_out_e <= _1_;
      Data_out_e <= _0_;
  end
endmodule