data/full_repos/permissive/531279620/resource/src/tb_crc32.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/531279620/resource/src/tb_crc32.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #2.5 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/531279620/resource/src/tb_crc32.v:39: Unsupported: fork statements\n  fork begin\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/531279620/resource/src/tb_crc32.v:41: Unsupported: Ignoring delay on this delayed statement.\n   #0 clk = 1\'b0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/531279620/resource/src/tb_crc32.v:46: Unsupported: Ignoring delay on this delayed statement.\n   #100 nrst = 1\'b1;\n   ^\n%Error: data/full_repos/permissive/531279620/resource/src/tb_crc32.v:48: syntax error, unexpected \'@\'\n   @(posedge clk)\n   ^\n%Error: data/full_repos/permissive/531279620/resource/src/tb_crc32.v:51: syntax error, unexpected \'@\'\n   @(posedge clk)\n   ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_crc32;

	reg		clk;
	reg		nrst;
	reg		enable;
	
	reg		[7 : 0]		data;
	
	wire	[31 : 0]	crc_out;
	
	crc32 DUT(
		.nrst	(nrst),
		.clock	(clk),
		.enable	(enable),
		
		.din	(data),
		.crc_o	(crc_out)
	);
	
	always begin
		#2.5 clk = ~clk;
	end
	
	initial begin
		fork begin
			
			#0 clk = 1'b0;
			nrst = 1'b0;
			enable = 1'b0;
			data = 8'd0;
			
			#100 nrst = 1'b1;
			
			@(posedge clk)
			enable <= 1'b1;
			data <= 8'h4d;
			@(posedge clk)
			data <= 8'h00;
			@(posedge clk)
			enable <= 1'b0;
			
		end join
	end
	
endmodule
module tb_crc32;


	reg		clk;
	reg		nrst;
	reg		enable;
	
	reg		[7 : 0]		data;
	
	wire	[31 : 0]	crc_out;
	
	crc32 DUT(
		.nrst	(nrst),
		.clock	(clk),
		.enable	(enable),
		
		.din	(data),
		.crc_o	(crc_out)
	);
	
	always begin
		#2.5 clk = ~clk;
	end
	
	initial begin
		fork begin
			
			#0 clk = 1'b0;
			nrst = 1'b0;
			enable = 1'b0;
			data = 8'd0;
			
			#100 nrst = 1'b1;
			
			@(posedge clk)
			enable <= 1'b1;
			data <= 8'h4d;
			@(posedge clk)
			data <= 8'h00;
			@(posedge clk)
			enable <= 1'b0;
			
		end join
	end
	
endmodule