data/full_repos/permissive/502135797/Lab6_March_16_2022/Code/top.v
1: b"%Error: data/full_repos/permissive/502135797/Lab6_March_16_2022/Code/top.v:18: Cannot find file containing module: 'CLKMANAGER'\n    CLKMANAGER clockmanager_wrapper(\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502135797/Lab6_March_16_2022/Code,data/full_repos/permissive/502135797/CLKMANAGER\n             data/full_repos/permissive/502135797/Lab6_March_16_2022/Code,data/full_repos/permissive/502135797/CLKMANAGER.v\n             data/full_repos/permissive/502135797/Lab6_March_16_2022/Code,data/full_repos/permissive/502135797/CLKMANAGER.sv\n             CLKMANAGER\n             CLKMANAGER.v\n             CLKMANAGER.sv\n             obj_dir/CLKMANAGER\n             obj_dir/CLKMANAGER.v\n             obj_dir/CLKMANAGER.sv\n%Error: data/full_repos/permissive/502135797/Lab6_March_16_2022/Code/top.v:26: Cannot find file containing module: 'UPDOWN'\n    UPDOWN udcounter_wrapper(\n    ^~~~~~\n%Error: data/full_repos/permissive/502135797/Lab6_March_16_2022/Code/top.v:37: Cannot find file containing module: 'bin2bcd'\n   bin2bcd bin2bcd_wrapper(\n   ^~~~~~~\n%Error: data/full_repos/permissive/502135797/Lab6_March_16_2022/Code/top.v:44: Cannot find file containing module: 'SEGDRIVE'\n    SEGDRIVE seg7driver_wrapper(\n    ^~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module top(
    input clkt,
    input rstt,
    input ent,
    input udt, 
    input [4:0] SW,
input load1,
    input [3:0] udsw1,
    input [2:0] numsel1,
    output seg,
    output [6:0] Cnode1,
    output [7:0] AN1
    );
    wire slowclk_out;
    wire [31:0] inDigit; 
    CLKMANAGER clockmanager_wrapper(
        .clk(clkt),
        .SW(SW),
        .clkout(slowclk_out)
    );
    
    
    wire [31:0] tmp_cnt; 
    UPDOWN udcounter_wrapper(
        .rst1(rstt),
        .en(ent),
        .clk1(slowclk_out),       
       .load(load1),
        .udsw(udsw1),
        .numsel(numsel1), 
        .tmp(tmp_cnt),
        .ud(udt)
    );
    
   bin2bcd bin2bcd_wrapper(
        .bin(tmp_cnt), 
          
        .bcd(inDigit)
    );
    
    
    SEGDRIVE seg7driver_wrapper(
        .nexysCLK(clkt), 
        .inDigit(inDigit),
         .Cnode(Cnode1),
        .dp(seg),
        .AN(AN1)
    );
endmodule
module top(
    input clkt,
    input rstt,
    input ent,
    input udt, 
    input [4:0] SW,
input load1,
    input [3:0] udsw1,
    input [2:0] numsel1,
    output seg,
    output [6:0] Cnode1,
    output [7:0] AN1
    );

    wire slowclk_out;
    wire [31:0] inDigit; 
    CLKMANAGER clockmanager_wrapper(
        .clk(clkt),
        .SW(SW),
        .clkout(slowclk_out)
    );
    
    
    wire [31:0] tmp_cnt; 
    UPDOWN udcounter_wrapper(
        .rst1(rstt),
        .en(ent),
        .clk1(slowclk_out),       
       .load(load1),
        .udsw(udsw1),
        .numsel(numsel1), 
        .tmp(tmp_cnt),
        .ud(udt)
    );
    
   bin2bcd bin2bcd_wrapper(
        .bin(tmp_cnt), 
          
        .bcd(inDigit)
    );
    
    
    SEGDRIVE seg7driver_wrapper(
        .nexysCLK(clkt), 
        .inDigit(inDigit),
         .Cnode(Cnode1),
        .dp(seg),
        .AN(AN1)
    );
endmodule