data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:29: Cannot find include file: sys.h\n`include "sys.h" // system level definition file which contains the  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:31: Cannot find include file: iop.h\n`include        "iop.h" \n                ^~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:58: Define or directive not defined: \'`UCB_64PAY_PKT_WIDTH\'\n   input [`UCB_64PAY_PKT_WIDTH-1:0]  tap_iob_packet;\n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:62: Define or directive not defined: \'`PCX_WIDTH\'\n   wire [`PCX_WIDTH-1:0]       cpu_buf_dout;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:66: Define or directive not defined: \'`PCX_WIDTH\'\n   assign  cpu_buf_dout = {cpu_buf_dout_hi[`PCX_WIDTH-64-1:0],cpu_buf_dout_lo[63:0]};\n                                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:70: Define or directive not defined: \'`PCX_WIDTH\'\n   output [`PCX_WIDTH-1:0]       pcx_packet;\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:71: Define or directive not defined: \'`UCB_64PAY_PKT_WIDTH\'\n   output [`UCB_64PAY_PKT_WIDTH-1:0] tap_packet;\n           ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:75: Define or directive not defined: \'`UCB_PKT_WIDTH\'\n   input [`UCB_PKT_WIDTH-1:0]       cpu_packet_type;\n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:77: Define or directive not defined: \'`UCB_ADDR_WIDTH\'\n   output [`UCB_ADDR_WIDTH-1:0]      c2i_packet_addr;\n           ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:81: Define or directive not defined: \'`UCB_64PAY_PKT_WIDTH\'\n   output [`UCB_64PAY_PKT_WIDTH-1:0] c2i_packet;\n           ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:85: Define or directive not defined: \'`UCB_NOPAY_PKT_WIDTH\'\n   output [`UCB_NOPAY_PKT_WIDTH-1:0] c2i_rd_nack_packet;\n           ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:89: Define or directive not defined: \'`IOB_IO_BUF_WIDTH\'\n   output [`IOB_IO_BUF_WIDTH-1:0]    wr_ack_io_buf_din;\n           ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:93: Define or directive not defined: \'`UCB_64PAY_PKT_WIDTH\'\n   wire [`UCB_64PAY_PKT_WIDTH-1:0]   cpu_packet;\n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:94: Define or directive not defined: \'`CPX_WIDTH\'\n   wire [`CPX_WIDTH-1:0]       wr_ack_packet;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:95: Define or directive not defined: \'`IOB_CPU_WIDTH\'\n   wire [`IOB_CPU_WIDTH-1:0]       wr_ack_packet_cpu;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:97: Define or directive not defined: \'`UCB_PKT_WIDTH\'\n   wire [`UCB_PKT_WIDTH-1:0]       nack_packet_type;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:106: Define or directive not defined: \'`PCX_WIDTH\'\n   dffe_ns #(`PCX_WIDTH) pcx_packet_ff (.din(cpu_buf_dout),\n             ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:115: Define or directive not defined: \'`PCX_DA_HI\'\n        {pcx_packet[`PCX_DA_HI:`PCX_DA_LO],  \n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:115: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n        {pcx_packet[`PCX_DA_HI:`PCX_DA_LO],  \n                              ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:115: Define or directive not defined: \'`PCX_DA_LO\'\n        {pcx_packet[`PCX_DA_HI:`PCX_DA_LO],  \n                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:116: Define or directive not defined: \'`UCB_RSV_WIDTH\'\n         `UCB_RSV_WIDTH\'b0,                  \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:117: Define or directive not defined: \'`PCX_AD_HI\'\n         pcx_packet[`PCX_AD_HI:`PCX_AD_LO],  \n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:117: Define or directive not defined: \'`PCX_AD_LO\'\n         pcx_packet[`PCX_AD_HI:`PCX_AD_LO],  \n                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:118: Define or directive not defined: \'`PCX_SZ_HI\'\n         pcx_packet[`PCX_SZ_HI:`PCX_SZ_LO],  \n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:118: Define or directive not defined: \'`PCX_SZ_LO\'\n         pcx_packet[`PCX_SZ_HI:`PCX_SZ_LO],  \n                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:119: Define or directive not defined: \'`UCB_BID_CMP\'\n         `UCB_BID_CMP,                       \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:122: Define or directive not defined: \'`PCX_CP_HI\'\n         pcx_packet[`PCX_CP_HI:`PCX_CP_LO],\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:122: Define or directive not defined: \'`PCX_CP_LO\'\n         pcx_packet[`PCX_CP_HI:`PCX_CP_LO],\n                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:123: Define or directive not defined: \'`PCX_TH_HI\'\n         pcx_packet[`PCX_TH_HI:`PCX_TH_LO],\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:123: Define or directive not defined: \'`PCX_TH_LO\'\n         pcx_packet[`PCX_TH_HI:`PCX_TH_LO],\n                               ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:126: Define or directive not defined: \'`PCX_DA_HI\'\n               {pcx_packet[`PCX_DA_HI:`PCX_DA_LO],  \n                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:126: Define or directive not defined: \'`PCX_DA_LO\'\n               {pcx_packet[`PCX_DA_HI:`PCX_DA_LO],  \n                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:127: Define or directive not defined: \'`UCB_RSV_WIDTH\'\n         `UCB_RSV_WIDTH\'b0,                  \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:128: Define or directive not defined: \'`UCB_ADDR_WIDTH\'\n         `UCB_ADDR_WIDTH\'b0,                 \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:129: Define or directive not defined: \'`UCB_SIZE_WIDTH\'\n         `UCB_SIZE_WIDTH\'b0,                 \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:130: Define or directive not defined: \'`UCB_BID_TAP\'\n         `UCB_BID_TAP,                       \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:131: Define or directive not defined: \'`UCB_THR_WIDTH\'\n         `UCB_THR_WIDTH\'b0,                  \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:139: Define or directive not defined: \'`ST_ACK\'\n     `ST_ACK,                            \n     ^~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:139: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n     `ST_ACK,                            \n            ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:142: Define or directive not defined: \'`PCX_TH_HI\'\n     pcx_packet[`PCX_TH_HI:`PCX_TH_LO],  \n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:142: Define or directive not defined: \'`PCX_TH_LO\'\n     pcx_packet[`PCX_TH_HI:`PCX_TH_LO],  \n                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:144: Define or directive not defined: \'`PCX_P_HI\'\n     pcx_packet[`PCX_P_HI:`PCX_P_LO],    \n                ^~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:144: Define or directive not defined: \'`PCX_P_LO\'\n     pcx_packet[`PCX_P_HI:`PCX_P_LO],    \n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:150: Define or directive not defined: \'`PCX_CP_HI\'\n     pcx_packet[`PCX_CP_HI:`PCX_CP_LO],  \n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:150: Define or directive not defined: \'`PCX_CP_LO\'\n     pcx_packet[`PCX_CP_HI:`PCX_CP_LO],  \n                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:153: Define or directive not defined: \'`PCX_CP_HI\'\n   assign  wr_ack_packet_cpu = 1\'b1 << pcx_packet[`PCX_CP_HI:`PCX_CP_LO];\n                                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:153: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   assign  wr_ack_packet_cpu = 1\'b1 << pcx_packet[`PCX_CP_HI:`PCX_CP_LO];\n                                                            ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:153: Define or directive not defined: \'`PCX_CP_LO\'\n   assign  wr_ack_packet_cpu = 1\'b1 << pcx_packet[`PCX_CP_HI:`PCX_CP_LO];\n                                                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:172: Define or directive not defined: \'`UCB_ADDR_HI\'\n   assign  c2i_packet_addr = c2i_packet[`UCB_ADDR_HI:`UCB_ADDR_LO];\n                                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/c2i_sdp.v:172: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   assign  c2i_packet_addr = c2i_packet[`UCB_ADDR_HI:`UCB_ADDR_LO];\n                                                    ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module c2i_sdp (

   pcx_packet, tap_packet, c2i_packet_addr, c2i_packet, 
   c2i_rd_nack_packet, wr_ack_io_buf_din, 

   clk, tap_iob_packet, cpu_buf_dout_lo, cpu_buf_dout_hi, cpu_buf_rd, 
   tap_sel, cpu_packet_is_req, cpu_packet_type
   );





   input 			     clk;



   input [`UCB_64PAY_PKT_WIDTH-1:0]  tap_iob_packet;
   


   wire [`PCX_WIDTH-1:0] 	     cpu_buf_dout;
   input [64:0] 		     cpu_buf_dout_lo;
   input [64:0] 		     cpu_buf_dout_hi;
   
   assign 	cpu_buf_dout = {cpu_buf_dout_hi[`PCX_WIDTH-64-1:0],cpu_buf_dout_lo[63:0]};

   

   output [`PCX_WIDTH-1:0] 	     pcx_packet;
   output [`UCB_64PAY_PKT_WIDTH-1:0] tap_packet;
   input 			     cpu_buf_rd;
   input 			     tap_sel;
   input 			     cpu_packet_is_req;
   input [`UCB_PKT_WIDTH-1:0] 	     cpu_packet_type;

   output [`UCB_ADDR_WIDTH-1:0]      c2i_packet_addr;
   
   

   output [`UCB_64PAY_PKT_WIDTH-1:0] c2i_packet;

   

   output [`UCB_NOPAY_PKT_WIDTH-1:0] c2i_rd_nack_packet;

   

   output [`IOB_IO_BUF_WIDTH-1:0]    wr_ack_io_buf_din;

   

   wire [`UCB_64PAY_PKT_WIDTH-1:0]   cpu_packet;
   wire [`CPX_WIDTH-1:0] 	     wr_ack_packet;
   wire [`IOB_CPU_WIDTH-1:0] 	     wr_ack_packet_cpu;
   
   wire [`UCB_PKT_WIDTH-1:0] 	     nack_packet_type;
   





   dffe_ns #(`PCX_WIDTH) pcx_packet_ff (.din(cpu_buf_dout),
					.en(cpu_buf_rd),
					.clk(clk),
					.q(pcx_packet));

   

   assign 	cpu_packet = cpu_packet_is_req ?

			     {pcx_packet[`PCX_DA_HI:`PCX_DA_LO],
			      `UCB_RSV_WIDTH'b0,
			      pcx_packet[`PCX_AD_HI:`PCX_AD_LO],
			      pcx_packet[`PCX_SZ_HI:`PCX_SZ_LO],
			      `UCB_BID_CMP,

			      1'b0,
			      pcx_packet[`PCX_CP_HI:`PCX_CP_LO],
			      pcx_packet[`PCX_TH_HI:`PCX_TH_LO],
			      cpu_packet_type} :

		             {pcx_packet[`PCX_DA_HI:`PCX_DA_LO],
			      `UCB_RSV_WIDTH'b0,
			      `UCB_ADDR_WIDTH'b0,
			      `UCB_SIZE_WIDTH'b0,
			      `UCB_BID_TAP,
			      `UCB_THR_WIDTH'b0,
			      cpu_packet_type};

   

   assign 	wr_ack_packet = {1'b1,
				 `ST_ACK,
				 3'b0,
				 1'b1,
				 pcx_packet[`PCX_TH_HI:`PCX_TH_LO],
				 2'b0,
				 pcx_packet[`PCX_P_HI:`PCX_P_LO],
				 1'b0,
				 1'b0,
				 2'b0,
				 pcx_packet[109],
				 4'b0,
				 pcx_packet[`PCX_CP_HI:`PCX_CP_LO],
				 118'b0};

   assign 	wr_ack_packet_cpu = 1'b1 << pcx_packet[`PCX_CP_HI:`PCX_CP_LO];
   
   assign 	wr_ack_io_buf_din = {wr_ack_packet_cpu,
				     wr_ack_packet};

   

   assign 	tap_packet = tap_iob_packet;

   


   assign 	c2i_packet = tap_sel ? tap_packet :
		                       cpu_packet;

   assign 	c2i_packet_addr = c2i_packet[`UCB_ADDR_HI:`UCB_ADDR_LO];

   

   assign 	nack_packet_type = (cpu_packet[`UCB_PKT_HI:`UCB_PKT_LO] == `UCB_IFILL_REQ) ?
				    `UCB_IFILL_NACK :
		                    `UCB_READ_NACK;
   
   assign 	c2i_rd_nack_packet = {`UCB_RSV_WIDTH'b0,
				      `UCB_ADDR_WIDTH'b0,
				      `UCB_SIZE_WIDTH'b0,
				      c2i_packet[`UCB_BUF_HI:`UCB_BUF_LO],
				      c2i_packet[`UCB_THR_HI:`UCB_THR_LO],
				      nack_packet_type};

   
endmodule
module c2i_sdp (

   pcx_packet, tap_packet, c2i_packet_addr, c2i_packet, 
   c2i_rd_nack_packet, wr_ack_io_buf_din, 

   clk, tap_iob_packet, cpu_buf_dout_lo, cpu_buf_dout_hi, cpu_buf_rd, 
   tap_sel, cpu_packet_is_req, cpu_packet_type
   );






   input 			     clk;



   input [`UCB_64PAY_PKT_WIDTH-1:0]  tap_iob_packet;
   


   wire [`PCX_WIDTH-1:0] 	     cpu_buf_dout;
   input [64:0] 		     cpu_buf_dout_lo;
   input [64:0] 		     cpu_buf_dout_hi;
   
   assign 	cpu_buf_dout = {cpu_buf_dout_hi[`PCX_WIDTH-64-1:0],cpu_buf_dout_lo[63:0]};

   

   output [`PCX_WIDTH-1:0] 	     pcx_packet;
   output [`UCB_64PAY_PKT_WIDTH-1:0] tap_packet;
   input 			     cpu_buf_rd;
   input 			     tap_sel;
   input 			     cpu_packet_is_req;
   input [`UCB_PKT_WIDTH-1:0] 	     cpu_packet_type;

   output [`UCB_ADDR_WIDTH-1:0]      c2i_packet_addr;
   
   

   output [`UCB_64PAY_PKT_WIDTH-1:0] c2i_packet;

   

   output [`UCB_NOPAY_PKT_WIDTH-1:0] c2i_rd_nack_packet;

   

   output [`IOB_IO_BUF_WIDTH-1:0]    wr_ack_io_buf_din;

   

   wire [`UCB_64PAY_PKT_WIDTH-1:0]   cpu_packet;
   wire [`CPX_WIDTH-1:0] 	     wr_ack_packet;
   wire [`IOB_CPU_WIDTH-1:0] 	     wr_ack_packet_cpu;
   
   wire [`UCB_PKT_WIDTH-1:0] 	     nack_packet_type;
   





   dffe_ns #(`PCX_WIDTH) pcx_packet_ff (.din(cpu_buf_dout),
					.en(cpu_buf_rd),
					.clk(clk),
					.q(pcx_packet));

   

   assign 	cpu_packet = cpu_packet_is_req ?

			     {pcx_packet[`PCX_DA_HI:`PCX_DA_LO],
			      `UCB_RSV_WIDTH'b0,
			      pcx_packet[`PCX_AD_HI:`PCX_AD_LO],
			      pcx_packet[`PCX_SZ_HI:`PCX_SZ_LO],
			      `UCB_BID_CMP,

			      1'b0,
			      pcx_packet[`PCX_CP_HI:`PCX_CP_LO],
			      pcx_packet[`PCX_TH_HI:`PCX_TH_LO],
			      cpu_packet_type} :

		             {pcx_packet[`PCX_DA_HI:`PCX_DA_LO],
			      `UCB_RSV_WIDTH'b0,
			      `UCB_ADDR_WIDTH'b0,
			      `UCB_SIZE_WIDTH'b0,
			      `UCB_BID_TAP,
			      `UCB_THR_WIDTH'b0,
			      cpu_packet_type};

   

   assign 	wr_ack_packet = {1'b1,
				 `ST_ACK,
				 3'b0,
				 1'b1,
				 pcx_packet[`PCX_TH_HI:`PCX_TH_LO],
				 2'b0,
				 pcx_packet[`PCX_P_HI:`PCX_P_LO],
				 1'b0,
				 1'b0,
				 2'b0,
				 pcx_packet[109],
				 4'b0,
				 pcx_packet[`PCX_CP_HI:`PCX_CP_LO],
				 118'b0};

   assign 	wr_ack_packet_cpu = 1'b1 << pcx_packet[`PCX_CP_HI:`PCX_CP_LO];
   
   assign 	wr_ack_io_buf_din = {wr_ack_packet_cpu,
				     wr_ack_packet};

   

   assign 	tap_packet = tap_iob_packet;

   


   assign 	c2i_packet = tap_sel ? tap_packet :
		                       cpu_packet;

   assign 	c2i_packet_addr = c2i_packet[`UCB_ADDR_HI:`UCB_ADDR_LO];

   

   assign 	nack_packet_type = (cpu_packet[`UCB_PKT_HI:`UCB_PKT_LO] == `UCB_IFILL_REQ) ?
				    `UCB_IFILL_NACK :
		                    `UCB_READ_NACK;
   
   assign 	c2i_rd_nack_packet = {`UCB_RSV_WIDTH'b0,
				      `UCB_ADDR_WIDTH'b0,
				      `UCB_SIZE_WIDTH'b0,
				      c2i_packet[`UCB_BUF_HI:`UCB_BUF_LO],
				      c2i_packet[`UCB_THR_HI:`UCB_THR_LO],
				      nack_packet_type};

   
endmodule