data/full_repos/permissive/494148647/src/util/counter_tb.v
1: b'%Error: data/full_repos/permissive/494148647/src/util/counter_tb.v:44: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("counter_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/494148647/src/util/counter_tb.v:45: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, counter_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/494148647/src/util/counter_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n        repeat(4) #10 clk = ~clk;\n                  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/494148647/src/util/counter_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n        repeat(1000) #10 clk = ~clk;\n                     ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module counter_tb ();

    localparam COUNT_BITS = 6;
    localparam HIDDEN_BITS = 0;

    reg clk, rst;
    wire [COUNT_BITS-1:0] count;

    integer i, err_count = 0;

    counter #(
        .COUNT_BITS(COUNT_BITS),
        .HIDDEN_BITS(HIDDEN_BITS)
    ) DUT (
        .clk(clk),
        .rst(rst),
        .count(count)
    );


    always @(posedge clk) begin
        if (rst || (i == {COUNT_BITS{1'b1}}))
            i <= 0;
        else
            i <= i + 1;

        if (i != count) begin
            $display("ERROR: counter has value %d, expected %d", count, i);
            err_count = err_count + 1;
        end
    end


    initial begin
        $dumpfile("counter_tb.vcd");
        $dumpvars(0, counter_tb);

        clk = 1'b0;
        rst = 1'b1;
        repeat(4) #10 clk = ~clk;

        rst = 1'b0;
        repeat(1000) #10 clk = ~clk;

        $display("test finished with %d errors", err_count);
        $finish;
    end

endmodule
module counter_tb ();


    localparam COUNT_BITS = 6;
    localparam HIDDEN_BITS = 0;

    reg clk, rst;
    wire [COUNT_BITS-1:0] count;

    integer i, err_count = 0;

    counter #(
        .COUNT_BITS(COUNT_BITS),
        .HIDDEN_BITS(HIDDEN_BITS)
    ) DUT (
        .clk(clk),
        .rst(rst),
        .count(count)
    );


    always @(posedge clk) begin
        if (rst || (i == {COUNT_BITS{1'b1}}))
            i <= 0;
        else
            i <= i + 1;

        if (i != count) begin
            $display("ERROR: counter has value %d, expected %d", count, i);
            err_count = err_count + 1;
        end
    end


    initial begin
        $dumpfile("counter_tb.vcd");
        $dumpvars(0, counter_tb);

        clk = 1'b0;
        rst = 1'b1;
        repeat(4) #10 clk = ~clk;

        rst = 1'b0;
        repeat(1000) #10 clk = ~clk;

        $display("test finished with %d errors", err_count);
        $finish;
    end

endmodule