data/full_repos/permissive/489994352/Image-Part/lineBuffer.v
data/verilator_xmls/7a9fe3ba-0239-4d32-8424-0faca817c27c.xml
module lineBuffer(
input   i_clk,
input   i_rst,
input [7:0] i_data,
input   i_data_valid,
output [23:0] o_data,
input i_rd_data
);

reg [7:0] line [223:0];
reg [7:0] wrPntr;
reg [7:0] rdPntr;

always @(posedge i_clk)
begin
    if(i_data_valid)
        line[wrPntr] <= i_data;
end

always @(posedge i_clk)
begin
    if(i_rst)
        wrPntr <= 'd0;
    else if(i_data_valid)
        if(wrPntr == 'd223)
            wrPntr <= 0;
        else
            wrPntr <= wrPntr + 'd1;
end

assign o_data = {line[rdPntr],line[rdPntr+1],line[rdPntr+2]};

always @(posedge i_clk)
begin
    if(i_rst)
        rdPntr <= 'd0;
    else if(i_rd_data)
        if (rdPntr == 'd220)
            rdPntr <= 0;
        else
            rdPntr <= rdPntr + 'd2;
end


endmodule
module lineBuffer(
input   i_clk,
input   i_rst,
input [7:0] i_data,
input   i_data_valid,
output [23:0] o_data,
input i_rd_data
);


reg [7:0] line [223:0];
reg [7:0] wrPntr;
reg [7:0] rdPntr;

always @(posedge i_clk)
begin
    if(i_data_valid)
        line[wrPntr] <= i_data;
end

always @(posedge i_clk)
begin
    if(i_rst)
        wrPntr <= 'd0;
    else if(i_data_valid)
        if(wrPntr == 'd223)
            wrPntr <= 0;
        else
            wrPntr <= wrPntr + 'd1;
end

assign o_data = {line[rdPntr],line[rdPntr+1],line[rdPntr+2]};

always @(posedge i_clk)
begin
    if(i_rst)
        rdPntr <= 'd0;
    else if(i_rd_data)
        if (rdPntr == 'd220)
            rdPntr <= 0;
        else
            rdPntr <= rdPntr + 'd2;
end


endmodule