data/full_repos/permissive/452098851/tutorial/demo_add/cachelib/v_rtl/dut_N_Muxb_1_2_0_4.v
data/verilator_xmls/8d6a50ab-cb79-4e4a-ac46-7a0a77279e99.xml
module dut_N_Muxb_1_2_0_4 (
	in3,
	in2,
	ctrl1,
	out1
	);
input  in3,
	in2,
	ctrl1;
output  out1;
wire  asc001;

reg [0:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @ (ctrl1 or in2 or in3) begin
	case (ctrl1)
		1'B1 : asc001_tmp_0 = in2 ;
		default : asc001_tmp_0 = in3 ;
	endcase
end

assign out1 = asc001;
endmodule
module dut_N_Muxb_1_2_0_4 (
	in3,
	in2,
	ctrl1,
	out1
	);

input  in3,
	in2,
	ctrl1;
output  out1;
wire  asc001;

reg [0:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @ (ctrl1 or in2 or in3) begin
	case (ctrl1)
		1'B1 : asc001_tmp_0 = in2 ;
		default : asc001_tmp_0 = in3 ;
	endcase
end

assign out1 = asc001;
endmodule