data/full_repos/permissive/505053576/myStateMachine_tb.v
1: b'%Error: data/full_repos/permissive/505053576/myStateMachine_tb.v:1: Cannot find include file: myStateMachine.v\n`include "myStateMachine.v" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/505053576,data/full_repos/permissive/505053576/myStateMachine.v\n             data/full_repos/permissive/505053576,data/full_repos/permissive/505053576/myStateMachine.v.v\n             data/full_repos/permissive/505053576,data/full_repos/permissive/505053576/myStateMachine.v.sv\n             myStateMachine.v\n             myStateMachine.v.v\n             myStateMachine.v.sv\n             obj_dir/myStateMachine.v\n             obj_dir/myStateMachine.v.v\n             obj_dir/myStateMachine.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/505053576/myStateMachine_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n            #10 clk = ~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/505053576/myStateMachine_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #30\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/505053576/myStateMachine_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n        u2 = 1; #1 u2 = 0;  \n                ^\n%Warning-STMTDLY: data/full_repos/permissive/505053576/myStateMachine_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #100 s2 = 1; #1 s2 = 0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/505053576/myStateMachine_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #100 s2 = 1; #1 s2 = 0;  \n                     ^\n%Warning-STMTDLY: data/full_repos/permissive/505053576/myStateMachine_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #30\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/505053576/myStateMachine_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n        u3 = 1; #1 u3 = 0;  \n                ^\n%Warning-STMTDLY: data/full_repos/permissive/505053576/myStateMachine_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #100 s3 = 1; #1 s3 = 0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/505053576/myStateMachine_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #100 s3 = 1; #1 s3 = 0;  \n                     ^\n%Warning-STMTDLY: data/full_repos/permissive/505053576/myStateMachine_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n        f1 = 1; #1 f1 = 0;  \n                ^\n%Warning-STMTDLY: data/full_repos/permissive/505053576/myStateMachine_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #100 s2 = 1; #1 s2 = 0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/505053576/myStateMachine_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #100 s2 = 1; #1 s2 = 0;  \n                     ^\n%Warning-STMTDLY: data/full_repos/permissive/505053576/myStateMachine_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #100 s1 = 1; #1 s1 = 0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/505053576/myStateMachine_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #100 s1 = 1; #1 s1 = 0;  \n                     ^\n%Warning-STMTDLY: data/full_repos/permissive/505053576/myStateMachine_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #30\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/505053576/myStateMachine_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n        d3 = 1; #1 d3 = 0;  \n                ^\n%Warning-STMTDLY: data/full_repos/permissive/505053576/myStateMachine_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #50 u2 = 1; #1 u2 = 0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/505053576/myStateMachine_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #50 u2 = 1; #1 u2 = 0;  \n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/505053576/myStateMachine_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #50 s2 = 1; #1 s2 = 0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/505053576/myStateMachine_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #50 s2 = 1; #1 s2 = 0;  \n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/505053576/myStateMachine_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #100 s3 = 1; #1 s3 = 0;  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/505053576/myStateMachine_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #100 s3 = 1; #1 s3 = 0;  \n                     ^\n%Warning-STMTDLY: data/full_repos/permissive/505053576/myStateMachine_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #30\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/505053576/myStateMachine_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/505053576/myStateMachine_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n        d3 = 1; #1 d3 = 0;  \n                ^\n%Warning-STMTDLY: data/full_repos/permissive/505053576/myStateMachine_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #20 rst = 0;\n        ^\n%Error: Exiting due to 1 error(s), 26 warning(s)\n'
module elevator_tb ();
    wire [1:0] ac;
    wire [1:0] display;
    wire doorOpen;

    reg s1, s2, s3, f1, f2, f3, u1, u2, u3, d1, d2, d3, clk, rst;

    elevator elevator(s1, s2, s3, f1, f2, f3, u1, u2, u3, d1, d2, d3, clk, rst, ac, display, doorOpen); 

    initial begin 
        forever begin
            #10 clk = ~clk;
        end 
    end

    initial begin
        rst = 0;
        clk = 0;
        s1 = 0;
        s2 = 0;
        s3 = 0;
        f1 = 0;
        f2 = 0;
        f3 = 0;
        u1 = 0;
        u2 = 0;
        u3 = 0;
        d1 = 0;
        d2 = 0;
        d3 = 0;


        #30
        u2 = 1; #1 u2 = 0;
        #100 s2 = 1; #1 s2 = 0;


        #30
        u3 = 1; #1 u3 = 0;
        #100 s3 = 1; #1 s3 = 0;
        f1 = 1; #1 f1 = 0;
        #100 s2 = 1; #1 s2 = 0;
        #100 s1 = 1; #1 s1 = 0;


        #30
        d3 = 1; #1 d3 = 0;
        #50 u2 = 1; #1 u2 = 0;
        #50 s2 = 1; #1 s2 = 0;
        #100 s3 = 1; #1 s3 = 0;


        #30
        rst = 1;
        #20
        d3 = 1; #1 d3 = 0;
        #20 rst = 0;
    end

endmodule
module elevator_tb ();

    wire [1:0] ac;
    wire [1:0] display;
    wire doorOpen;

    reg s1, s2, s3, f1, f2, f3, u1, u2, u3, d1, d2, d3, clk, rst;

    elevator elevator(s1, s2, s3, f1, f2, f3, u1, u2, u3, d1, d2, d3, clk, rst, ac, display, doorOpen); 

    initial begin 
        forever begin
            #10 clk = ~clk;
        end 
    end

    initial begin
        rst = 0;
        clk = 0;
        s1 = 0;
        s2 = 0;
        s3 = 0;
        f1 = 0;
        f2 = 0;
        f3 = 0;
        u1 = 0;
        u2 = 0;
        u3 = 0;
        d1 = 0;
        d2 = 0;
        d3 = 0;


        #30
        u2 = 1; #1 u2 = 0;
        #100 s2 = 1; #1 s2 = 0;


        #30
        u3 = 1; #1 u3 = 0;
        #100 s3 = 1; #1 s3 = 0;
        f1 = 1; #1 f1 = 0;
        #100 s2 = 1; #1 s2 = 0;
        #100 s1 = 1; #1 s1 = 0;


        #30
        d3 = 1; #1 d3 = 0;
        #50 u2 = 1; #1 u2 = 0;
        #50 s2 = 1; #1 s2 = 0;
        #100 s3 = 1; #1 s3 = 0;


        #30
        rst = 1;
        #20
        d3 = 1; #1 d3 = 0;
        #20 rst = 0;
    end

endmodule