data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/xc6s_dsp_map.v
1: b'%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/xc6s_dsp_map.v:9: Cannot find file containing module: \'DSP48A1\'\n DSP48A1 #(\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx,data/full_repos/permissive/441359809/DSP48A1\n             data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx,data/full_repos/permissive/441359809/DSP48A1.v\n             data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx,data/full_repos/permissive/441359809/DSP48A1.sv\n             DSP48A1\n             DSP48A1.v\n             DSP48A1.sv\n             obj_dir/DSP48A1\n             obj_dir/DSP48A1.v\n             obj_dir/DSP48A1.sv\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/xc6s_dsp_map.v:32: Operator ASSIGNW expects 36 bits on the Assign RHS, but Assign RHS\'s VARREF \'P_48\' generates 48 bits.\n                                                                                                : ... In instance __024___05FMUL18X18\n assign Y = P_48;\n          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
	parameter A_SIGNED = 0;
	parameter B_SIGNED = 0;
	parameter A_WIDTH = 0;
	parameter B_WIDTH = 0;
	parameter Y_WIDTH = 0;

	wire [47:0] P_48;
	DSP48A1 #(

		.A0REG(0),
		.A1REG(0),
		.B0REG(0),
		.B1REG(0),
		.CARRYINREG(0),
		.CARRYINSEL("OPMODE5"),
		.CREG(0),
		.DREG(0),
		.MREG(0),
		.OPMODEREG(0),
		.PREG(0)
	) _TECHMAP_REPLACE_ (

		.A(A),
		.B(B),
		.C(48'b0),
		.D(18'b0),
		.P(P_48),

		.OPMODE(8'b0000001)
	);
	assign Y = P_48;
endmodule
module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);

	parameter A_SIGNED = 0;
	parameter B_SIGNED = 0;
	parameter A_WIDTH = 0;
	parameter B_WIDTH = 0;
	parameter Y_WIDTH = 0;

	wire [47:0] P_48;
	DSP48A1 #(

		.A0REG(0),
		.A1REG(0),
		.B0REG(0),
		.B1REG(0),
		.CARRYINREG(0),
		.CARRYINSEL("OPMODE5"),
		.CREG(0),
		.DREG(0),
		.MREG(0),
		.OPMODEREG(0),
		.PREG(0)
	) _TECHMAP_REPLACE_ (

		.A(A),
		.B(B),
		.C(48'b0),
		.D(18'b0),
		.P(P_48),

		.OPMODE(8'b0000001)
	);
	assign Y = P_48;
endmodule