data/full_repos/permissive/445216371/ALU.v
1: b'%Error: data/full_repos/permissive/445216371/ALU.v:37: Cannot find include file: parameters.vh\n    `include "parameters.vh" \n             ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/445216371,data/full_repos/permissive/445216371/parameters.vh\n             data/full_repos/permissive/445216371,data/full_repos/permissive/445216371/parameters.vh.v\n             data/full_repos/permissive/445216371,data/full_repos/permissive/445216371/parameters.vh.sv\n             parameters.vh\n             parameters.vh.v\n             parameters.vh.sv\n             obj_dir/parameters.vh\n             obj_dir/parameters.vh.v\n             obj_dir/parameters.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module compare(
    output lt,eq,
    input [31:0] a,b,
    input unsig
    );

    wire [31:0] atemp,btemp;
    assign atemp = {a[31]^(!unsig),a[30:0]^(a[31]&(!unsig))};
    assign btemp = {b[31]^(!unsig),b[30:0]^(b[31]&(!unsig))};

    assign lt = atemp<btemp;
    assign eq = atemp==btemp;
endmodule
module compare(
    output lt,eq,
    input [31:0] a,b,
    input unsig
    );


    wire [31:0] atemp,btemp;
    assign atemp = {a[31]^(!unsig),a[30:0]^(a[31]&(!unsig))};
    assign btemp = {b[31]^(!unsig),b[30:0]^(b[31]&(!unsig))};

    assign lt = atemp<btemp;
    assign eq = atemp==btemp;
endmodule