data/full_repos/permissive/41334298/tests/elementary/t2.v
data/verilator_xmls/49d98958-80b6-4f43-b1db-f409ba4d4f98.xml
module top (a, b, c, y);
input a, b, c;
output y;


or (y, a, b, c);

endmodule
module top (a, b, c, y);

input a, b, c;
output y;


or (y, a, b, c);

endmodule