data/full_repos/permissive/492581806/alumod.v
data/verilator_xmls/1b5d26a6-2f6f-42bc-ae7c-abcd2c58b0fe.xml
module alu(DATA1, DATA2, RESULT, SELECT,ZERO);

input [7:0] DATA1,DATA2;
input [2:0] SELECT;
output reg [7:0] RESULT;
output reg ZERO;
wire [7:0] WFORWARD,WADD,WAND,WOR;



FORWARD F1 (DATA2,WFORWARD);
ADD F2 (DATA1, DATA2,WADD);
AND F3 (DATA1, DATA2,WAND);
OR F4 (DATA1, DATA2,WOR);

always@(SELECT,WFORWARD,WADD,WAND,WOR)
begin
case(SELECT)                          

3'b000:  RESULT=WFORWARD;
3'b001:  RESULT=WADD;
3'b010:  RESULT=WAND;
3'b011:  RESULT=WOR;

endcase

if(RESULT==8'b00000000)
ZERO=1'b1;
else
ZERO=1'b0;

end

endmodule
module alu(DATA1, DATA2, RESULT, SELECT,ZERO);


input [7:0] DATA1,DATA2;
input [2:0] SELECT;
output reg [7:0] RESULT;
output reg ZERO;
wire [7:0] WFORWARD,WADD,WAND,WOR;



FORWARD F1 (DATA2,WFORWARD);
ADD F2 (DATA1, DATA2,WADD);
AND F3 (DATA1, DATA2,WAND);
OR F4 (DATA1, DATA2,WOR);

always@(SELECT,WFORWARD,WADD,WAND,WOR)
begin
case(SELECT)                          

3'b000:  RESULT=WFORWARD;
3'b001:  RESULT=WADD;
3'b010:  RESULT=WAND;
3'b011:  RESULT=WOR;

endcase

if(RESULT==8'b00000000)
ZERO=1'b1;
else
ZERO=1'b0;

end

endmodule