data/full_repos/permissive/444555755/mp4/hdl/given_cache/cache_L2.sv
1: b"%Error: data/full_repos/permissive/444555755/mp4/hdl/given_cache/cache_L2.sv:41: Cannot find file containing module: 'cache_control'\ncache_control control(.*);\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/444555755/mp4/hdl/given_cache,data/full_repos/permissive/444555755/cache_control\n             data/full_repos/permissive/444555755/mp4/hdl/given_cache,data/full_repos/permissive/444555755/cache_control.v\n             data/full_repos/permissive/444555755/mp4/hdl/given_cache,data/full_repos/permissive/444555755/cache_control.sv\n             cache_control\n             cache_control.v\n             cache_control.sv\n             obj_dir/cache_control\n             obj_dir/cache_control.v\n             obj_dir/cache_control.sv\n%Error: data/full_repos/permissive/444555755/mp4/hdl/given_cache/cache_L2.sv:42: Cannot find file containing module: 'cache_datapath'\ncache_datapath #(s_offset,s_index) datapath(.*);\n^~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module cache_L2 #(
  parameter s_offset = 5,
  parameter s_index = 3,
  parameter s_tag = 32 - s_offset - s_index,
  parameter s_mask = 2**s_offset,
  parameter s_line = 8*s_mask,
  parameter num_sets = 2**s_index
)(
  input clk,

  input logic pmem_resp,
  input logic [s_line - 1:0] pmem_rdata,
  output logic [31:0] pmem_address,
  output logic [s_line-1:0] pmem_wdata,
  output logic pmem_read,
  output logic pmem_write,


  input logic mem_read,
  input logic mem_write,
  input logic [3:0] mem_byte_enable_cpu,
  input logic [31:0] mem_address,
  input logic [s_line -1 :0] mem_wdata,
  output logic mem_resp,
  output logic [s_line -1 :0] mem_rdata
);

logic tag_load;
logic valid_load;
logic dirty_load;
logic dirty_in;
logic dirty_out;

logic hit;
logic [1:0] writing;

logic [31:0] mem_byte_enable;

assign mem_byte_enable = 32'hFFFFFFFF;

cache_control control(.*);
cache_datapath #(s_offset,s_index) datapath(.*);


endmodule
module cache_L2 #(
  parameter s_offset = 5,
  parameter s_index = 3,
  parameter s_tag = 32 - s_offset - s_index,
  parameter s_mask = 2**s_offset,
  parameter s_line = 8*s_mask,
  parameter num_sets = 2**s_index
)(
  input clk,

  input logic pmem_resp,
  input logic [s_line - 1:0] pmem_rdata,
  output logic [31:0] pmem_address,
  output logic [s_line-1:0] pmem_wdata,
  output logic pmem_read,
  output logic pmem_write,


  input logic mem_read,
  input logic mem_write,
  input logic [3:0] mem_byte_enable_cpu,
  input logic [31:0] mem_address,
  input logic [s_line -1 :0] mem_wdata,
  output logic mem_resp,
  output logic [s_line -1 :0] mem_rdata
);


logic tag_load;
logic valid_load;
logic dirty_load;
logic dirty_in;
logic dirty_out;

logic hit;
logic [1:0] writing;

logic [31:0] mem_byte_enable;

assign mem_byte_enable = 32'hFFFFFFFF;

cache_control control(.*);
cache_datapath #(s_offset,s_index) datapath(.*);


endmodule