data/full_repos/permissive/516500786/vivado/ultra_ram/xilinx_block_ram_dp_512x20480.v
1: b"%Error: data/full_repos/permissive/516500786/vivado/ultra_ram/xilinx_block_ram_dp_512x20480.v:7: Cannot find file containing module: 'xpm_memory_tdpram'\n   xpm_memory_tdpram #(\n   ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/516500786/vivado/ultra_ram,data/full_repos/permissive/516500786/xpm_memory_tdpram\n             data/full_repos/permissive/516500786/vivado/ultra_ram,data/full_repos/permissive/516500786/xpm_memory_tdpram.v\n             data/full_repos/permissive/516500786/vivado/ultra_ram,data/full_repos/permissive/516500786/xpm_memory_tdpram.sv\n             xpm_memory_tdpram\n             xpm_memory_tdpram.v\n             xpm_memory_tdpram.sv\n             obj_dir/xpm_memory_tdpram\n             obj_dir/xpm_memory_tdpram.v\n             obj_dir/xpm_memory_tdpram.sv\n%Error: Exiting due to 1 error(s)\n"
module xilinx_block_ram_dp_512x20480 (clka,clkb,ena,enb,wea,web,addra,addrb,dia,dib,doa,dob);
   input clka,clkb,ena,enb,wea,web;
   input [14:0] addra,addrb;
   input [511:0] dia,dib;
   output [511:0] doa,dob;

   xpm_memory_tdpram #(
      .ADDR_WIDTH_A(15),
      .ADDR_WIDTH_B(15),
      .AUTO_SLEEP_TIME(0),
      .BYTE_WRITE_WIDTH_A(512),
      .BYTE_WRITE_WIDTH_B(512),
      .CASCADE_HEIGHT(0),
      .CLOCKING_MODE("common_clock"),
      .ECC_MODE("no_ecc"),
      .MEMORY_INIT_FILE("none"),
      .MEMORY_INIT_PARAM("0"),
      .MEMORY_OPTIMIZATION("true"),
      .MEMORY_PRIMITIVE("block"),
      .MEMORY_SIZE(10485760),
      .MESSAGE_CONTROL(0),
      .READ_DATA_WIDTH_A(512),
      .READ_DATA_WIDTH_B(512),
      .READ_LATENCY_A(1),
      .READ_LATENCY_B(1),
      .READ_RESET_VALUE_A("0"),
      .READ_RESET_VALUE_B("0"),
      .RST_MODE_A("SYNC"),
      .RST_MODE_B("SYNC"),
      .SIM_ASSERT_CHK(0),
      .USE_EMBEDDED_CONSTRAINT(0),
      .USE_MEM_INIT(1),
      .USE_MEM_INIT_MMI(0),
      .WAKEUP_TIME("disable_sleep"),
      .WRITE_DATA_WIDTH_A(512),
      .WRITE_DATA_WIDTH_B(512),
      .WRITE_MODE_A("no_change"),
      .WRITE_MODE_B("no_change"),
      .WRITE_PROTECT(1)
   )
   xpm_memory_tdpram_inst (
      .douta(doa),
      .doutb(dob),

      .addra(addra),
      .addrb(addrb),
      .clka(clka),


      .clkb(clkb),



      .dina(dia),
      .dinb(dib),
      .ena(ena),



      .enb(enb),



      .injectdbiterra(1'b0),



      .injectdbiterrb(1'b0),



      .injectsbiterra(1'b0),



      .injectsbiterrb(1'b0),



      .regcea(1'b1),


      .regceb(1'b1),


      .rsta(1'b0),



      .rstb(1'b0),



      .sleep(1'b0),
      .wea(wea),






      .web(web)





);
endmodule
module xilinx_block_ram_dp_512x20480 (clka,clkb,ena,enb,wea,web,addra,addrb,dia,dib,doa,dob);

   input clka,clkb,ena,enb,wea,web;
   input [14:0] addra,addrb;
   input [511:0] dia,dib;
   output [511:0] doa,dob;

   xpm_memory_tdpram #(
      .ADDR_WIDTH_A(15),
      .ADDR_WIDTH_B(15),
      .AUTO_SLEEP_TIME(0),
      .BYTE_WRITE_WIDTH_A(512),
      .BYTE_WRITE_WIDTH_B(512),
      .CASCADE_HEIGHT(0),
      .CLOCKING_MODE("common_clock"),
      .ECC_MODE("no_ecc"),
      .MEMORY_INIT_FILE("none"),
      .MEMORY_INIT_PARAM("0"),
      .MEMORY_OPTIMIZATION("true"),
      .MEMORY_PRIMITIVE("block"),
      .MEMORY_SIZE(10485760),
      .MESSAGE_CONTROL(0),
      .READ_DATA_WIDTH_A(512),
      .READ_DATA_WIDTH_B(512),
      .READ_LATENCY_A(1),
      .READ_LATENCY_B(1),
      .READ_RESET_VALUE_A("0"),
      .READ_RESET_VALUE_B("0"),
      .RST_MODE_A("SYNC"),
      .RST_MODE_B("SYNC"),
      .SIM_ASSERT_CHK(0),
      .USE_EMBEDDED_CONSTRAINT(0),
      .USE_MEM_INIT(1),
      .USE_MEM_INIT_MMI(0),
      .WAKEUP_TIME("disable_sleep"),
      .WRITE_DATA_WIDTH_A(512),
      .WRITE_DATA_WIDTH_B(512),
      .WRITE_MODE_A("no_change"),
      .WRITE_MODE_B("no_change"),
      .WRITE_PROTECT(1)
   )
   xpm_memory_tdpram_inst (
      .douta(doa),
      .doutb(dob),

      .addra(addra),
      .addrb(addrb),
      .clka(clka),


      .clkb(clkb),



      .dina(dia),
      .dinb(dib),
      .ena(ena),



      .enb(enb),



      .injectdbiterra(1'b0),



      .injectdbiterrb(1'b0),



      .injectsbiterra(1'b0),



      .injectsbiterrb(1'b0),



      .regcea(1'b1),


      .regceb(1'b1),


      .rsta(1'b0),



      .rstb(1'b0),



      .sleep(1'b0),
      .wea(wea),






      .web(web)





);
endmodule