data/full_repos/permissive/517239653/hmc960.v
1: b'%Error: data/full_repos/permissive/517239653/hmc960.v:85: Cannot find file containing module: \'divider\'\ndivider CLOCK_DIV(spi_sys_clk, clk, clk_div << 1);  \n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/517239653,data/full_repos/permissive/517239653/divider\n             data/full_repos/permissive/517239653,data/full_repos/permissive/517239653/divider.v\n             data/full_repos/permissive/517239653,data/full_repos/permissive/517239653/divider.sv\n             divider\n             divider.v\n             divider.sv\n             obj_dir/divider\n             obj_dir/divider.v\n             obj_dir/divider.sv\n%Warning-WIDTH: data/full_repos/permissive/517239653/hmc960.v:125: Bit extraction of var[31:0] requires 5 bit index, not 8 bits.\n                                                                 : ... In instance hmc960\n                    mosi_reg <= tx_data[tx_bit_ind];\n                                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/517239653/hmc960.v:140: Bit extraction of var[31:0] requires 5 bit index, not 8 bits.\n                                                                 : ... In instance hmc960\n                    rx_data_reg[rx_bit_ind] <= miso;      \n                               ^\n%Warning-WIDTH: data/full_repos/permissive/517239653/hmc960.v:143: Bit extraction of var[31:0] requires 5 bit index, not 8 bits.\n                                                                 : ... In instance hmc960\n                    mosi_reg <= tx_data[tx_bit_ind];  \n                                       ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module hmc960(
    rx_data,
    sclk,
    mosi,
    cs,
    miso,
    clk,
    clk_div,
    tx_data,
    xfer_begin,
    reset
);

parameter BITS = 32;
parameter CHIP_ADDR = 3'b110;

output [BITS-1:0] rx_data;
output sclk;
output mosi;
output cs;

input miso;
input clk;
input [31:0] clk_div;
input [BITS-1:0] tx_data;
input xfer_begin;
input reset;

wire spi_sys_clk;
reg spi_clk = 'b0;

reg last_xfer_begin;
reg last_reset;
reg [2:0] spi_state = STATE_IDLE;
reg signed [7:0] tx_bit_ind;
reg signed [7:0] rx_bit_ind;
reg [BITS-1:0] rx_data_reg;

reg cs_reg;
reg mosi_reg;
reg sclk_reg;

assign cs = cs_reg;
assign mosi = mosi_reg;
assign sclk = sclk_reg;
assign rx_data = rx_data_reg;

divider CLOCK_DIV(spi_sys_clk, clk, clk_div << 1);


parameter   STATE_IDLE      = 0,
            STATE_INIT      = 1,
            STATE_TRANSFER  = 2,
            STATE_FINAL_CLK = 3,
            STATE_SCLK_TO_SEN = 4;

always @(posedge reset or posedge spi_sys_clk or posedge xfer_begin) begin
    if(reset) begin

        cs_reg <= 'b1;
        sclk_reg <= 'b0;
        mosi_reg <= 'b0;
        spi_state <= STATE_IDLE;
    end else if(xfer_begin) begin

        cs_reg <= 'b1;
        sclk_reg <= 'b0;
        mosi_reg <= 'b0;
        spi_state <= STATE_INIT;
    end else if (spi_sys_clk) begin
        spi_clk <= ~spi_clk;
        case (spi_state)
            STATE_IDLE: begin
                sclk_reg <= 'b0;
                mosi_reg <= 'b0;
                cs_reg <= 'b1;
                tx_bit_ind <= BITS-1;
                rx_bit_ind <= BITS-1;
            end
            STATE_INIT: begin
                cs_reg <= 'b0;
                sclk_reg <= 'b0;

                if (!spi_clk) begin

                    

                    mosi_reg <= tx_data[tx_bit_ind];
                    tx_bit_ind <= tx_bit_ind - 1;

                    spi_state <= STATE_TRANSFER;
                end 



            end
            STATE_TRANSFER: begin
                cs_reg <= 'b0;
                sclk_reg <= spi_clk;

                if (!spi_clk) begin

                    rx_data_reg[rx_bit_ind] <= miso;
                    rx_bit_ind <= rx_bit_ind - 1;

                    mosi_reg <= tx_data[tx_bit_ind];

                    if (tx_bit_ind == 0) begin

                        spi_state <= STATE_FINAL_CLK;
                    end else begin
                        tx_bit_ind <= tx_bit_ind - 1;

                    end
                    
                end
            end
            STATE_FINAL_CLK: begin
                sclk_reg <= spi_clk;
                if (spi_clk) begin
                    spi_state <= STATE_SCLK_TO_SEN;
                end
            end
            STATE_SCLK_TO_SEN: begin
                sclk_reg <= spi_clk;
                spi_state <= STATE_IDLE;
            end
            default: begin
                cs_reg = 'b1;
                spi_state = STATE_IDLE;
            end
        endcase

    end

end


endmodule
module hmc960(
    rx_data,
    sclk,
    mosi,
    cs,
    miso,
    clk,
    clk_div,
    tx_data,
    xfer_begin,
    reset
);


parameter BITS = 32;
parameter CHIP_ADDR = 3'b110;

output [BITS-1:0] rx_data;
output sclk;
output mosi;
output cs;

input miso;
input clk;
input [31:0] clk_div;
input [BITS-1:0] tx_data;
input xfer_begin;
input reset;

wire spi_sys_clk;
reg spi_clk = 'b0;

reg last_xfer_begin;
reg last_reset;
reg [2:0] spi_state = STATE_IDLE;
reg signed [7:0] tx_bit_ind;
reg signed [7:0] rx_bit_ind;
reg [BITS-1:0] rx_data_reg;

reg cs_reg;
reg mosi_reg;
reg sclk_reg;

assign cs = cs_reg;
assign mosi = mosi_reg;
assign sclk = sclk_reg;
assign rx_data = rx_data_reg;

divider CLOCK_DIV(spi_sys_clk, clk, clk_div << 1);


parameter   STATE_IDLE      = 0,
            STATE_INIT      = 1,
            STATE_TRANSFER  = 2,
            STATE_FINAL_CLK = 3,
            STATE_SCLK_TO_SEN = 4;

always @(posedge reset or posedge spi_sys_clk or posedge xfer_begin) begin
    if(reset) begin

        cs_reg <= 'b1;
        sclk_reg <= 'b0;
        mosi_reg <= 'b0;
        spi_state <= STATE_IDLE;
    end else if(xfer_begin) begin

        cs_reg <= 'b1;
        sclk_reg <= 'b0;
        mosi_reg <= 'b0;
        spi_state <= STATE_INIT;
    end else if (spi_sys_clk) begin
        spi_clk <= ~spi_clk;
        case (spi_state)
            STATE_IDLE: begin
                sclk_reg <= 'b0;
                mosi_reg <= 'b0;
                cs_reg <= 'b1;
                tx_bit_ind <= BITS-1;
                rx_bit_ind <= BITS-1;
            end
            STATE_INIT: begin
                cs_reg <= 'b0;
                sclk_reg <= 'b0;

                if (!spi_clk) begin

                    

                    mosi_reg <= tx_data[tx_bit_ind];
                    tx_bit_ind <= tx_bit_ind - 1;

                    spi_state <= STATE_TRANSFER;
                end 



            end
            STATE_TRANSFER: begin
                cs_reg <= 'b0;
                sclk_reg <= spi_clk;

                if (!spi_clk) begin

                    rx_data_reg[rx_bit_ind] <= miso;
                    rx_bit_ind <= rx_bit_ind - 1;

                    mosi_reg <= tx_data[tx_bit_ind];

                    if (tx_bit_ind == 0) begin

                        spi_state <= STATE_FINAL_CLK;
                    end else begin
                        tx_bit_ind <= tx_bit_ind - 1;

                    end
                    
                end
            end
            STATE_FINAL_CLK: begin
                sclk_reg <= spi_clk;
                if (spi_clk) begin
                    spi_state <= STATE_SCLK_TO_SEN;
                end
            end
            STATE_SCLK_TO_SEN: begin
                sclk_reg <= spi_clk;
                spi_state <= STATE_IDLE;
            end
            default: begin
                cs_reg = 'b1;
                spi_state = STATE_IDLE;
            end
        endcase

    end

end


endmodule