data/full_repos/permissive/531279620/resource/src/tb_usb_pd_phy_rd.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/531279620/resource/src/tb_usb_pd_phy_rd.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #2.5 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/531279620/resource/src/tb_usb_pd_phy_rd.v:67: Unsupported: fork statements\n  fork begin\n  ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/531279620/resource/src/tb_usb_pd_phy_rd.v:69: Unsupported: Ignoring delay on this delayed statement.\n   #0 clk = 1\'b0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/531279620/resource/src/tb_usb_pd_phy_rd.v:73: Unsupported: Ignoring delay on this delayed statement.\n   #1000 nrst = 1\'b1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/531279620/resource/src/tb_usb_pd_phy_rd.v:75: Unsupported: Ignoring delay on this delayed statement.\n   #1532 start = 1\'b1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/531279620/resource/src/tb_usb_pd_phy_rd.v:77: Unsupported: Ignoring delay on this delayed statement.\n   #10 start = 1\'b0;\n   ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_usb_pd_phy_rd;

	reg		clk;
	reg		nrst;
	reg		start;
	
	wire	bmc_dout;
	wire	busy;
	
	usb_pd_phy_wr#(
		.system_khz(200000)
	)sender(
		.nrst			(nrst),
		.clock			(clk),
		
		.hdr_sop_hrst	(1'b0),
		.start			(start),
		.busy			(busy),
		

		.send_num		(3'd6),

		.send_type		(4'b1),
		
		.send_word0		(32'h0801_912C),
		.send_word1		(32'h0002_D12C),
		.send_word2		(32'h0003_C12C),
		.send_word3		(32'h0004_B12C),
		.send_word4		(32'h0006_4145),
		.send_word5		(32'hC8DC_2164),
		.send_word6		(32'd0),
		
		.bmc_dout		(bmc_dout)
	);
	
	usb_pd_phy_rd#(
		.system_khz(200000)
	)DUT(
		.nrst		(nrst),
		.clock		(clk),
		.enable		(1'b1),
		
		.bmc_din	(bmc_dout)
	);
	
	always begin
		#2.5 clk = ~clk;
	end
	
	integer i = 0;
	
	initial begin
		fork begin
			
			#0 clk = 1'b0;
			nrst = 1'b0;
			start = 1'b0;
			
			#1000 nrst = 1'b1;
			
			#1532 start = 1'b1;
			
			#10 start = 1'b0;
			
			
		end join
	end
	
endmodule
module tb_usb_pd_phy_rd;


	reg		clk;
	reg		nrst;
	reg		start;
	
	wire	bmc_dout;
	wire	busy;
	
	usb_pd_phy_wr#(
		.system_khz(200000)
	)sender(
		.nrst			(nrst),
		.clock			(clk),
		
		.hdr_sop_hrst	(1'b0),
		.start			(start),
		.busy			(busy),
		

		.send_num		(3'd6),

		.send_type		(4'b1),
		
		.send_word0		(32'h0801_912C),
		.send_word1		(32'h0002_D12C),
		.send_word2		(32'h0003_C12C),
		.send_word3		(32'h0004_B12C),
		.send_word4		(32'h0006_4145),
		.send_word5		(32'hC8DC_2164),
		.send_word6		(32'd0),
		
		.bmc_dout		(bmc_dout)
	);
	
	usb_pd_phy_rd#(
		.system_khz(200000)
	)DUT(
		.nrst		(nrst),
		.clock		(clk),
		.enable		(1'b1),
		
		.bmc_din	(bmc_dout)
	);
	
	always begin
		#2.5 clk = ~clk;
	end
	
	integer i = 0;
	
	initial begin
		fork begin
			
			#0 clk = 1'b0;
			nrst = 1'b0;
			start = 1'b0;
			
			#1000 nrst = 1'b1;
			
			#1532 start = 1'b1;
			
			#10 start = 1'b0;
			
			
		end join
	end
	
endmodule