data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/fpga/src/ariane-ethernet/ssio_ddr_in.sv
1: b"%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/fpga/src/ariane-ethernet/ssio_ddr_in.sv:157: Cannot find file containing module: 'iddr'\niddr #(\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/fpga/src/ariane-ethernet,data/full_repos/permissive/509468557/iddr\n             data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/fpga/src/ariane-ethernet,data/full_repos/permissive/509468557/iddr.v\n             data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/fpga/src/ariane-ethernet,data/full_repos/permissive/509468557/iddr.sv\n             iddr\n             iddr.v\n             iddr.sv\n             obj_dir/iddr\n             obj_dir/iddr.v\n             obj_dir/iddr.sv\n%Error: Exiting due to 1 error(s)\n"
module ssio_ddr_in #
(

    parameter TARGET = "GENERIC",



    parameter IODDR_STYLE = "IODDR2",




    parameter CLOCK_INPUT_STYLE = "BUFIO2",

    parameter WIDTH = 1
)
(
    input  wire             input_clk,

    input  wire [WIDTH-1:0] input_d,

    output wire             output_clk,

    output wire [WIDTH-1:0] output_q1,
    output wire [WIDTH-1:0] output_q2
);

wire clk_int;
wire clk_io;

generate

if (TARGET == "XILINX") begin



    if (CLOCK_INPUT_STYLE == "BUFG") begin


        BUFG
        clk_bufg (
            .I(input_clk),
            .O(clk_int)
        );


        assign clk_io = clk_int;
        assign output_clk = clk_int;

    end else if (CLOCK_INPUT_STYLE == "BUFR") begin

        assign clk_int = input_clk;


        BUFIO
        clk_bufio (
            .I(clk_int),
            .O(clk_io)
        );


        BUFR #(
            .BUFR_DIVIDE("BYPASS")
        )
        clk_bufr (
            .I(clk_int),
            .O(output_clk),
            .CE(1'b1),
            .CLR(1'b0)
        );
        
    end else if (CLOCK_INPUT_STYLE == "BUFIO") begin

        assign clk_int = input_clk;


        BUFIO
        clk_bufio (
            .I(clk_int),
            .O(clk_io)
        );


        BUFG
        clk_bufg (
            .I(clk_int),
            .O(output_clk)
        );

    end else if (CLOCK_INPUT_STYLE == "BUFIO2") begin


        BUFIO2 #(
            .DIVIDE(1),
            .DIVIDE_BYPASS("TRUE"),
            .I_INVERT("FALSE"),
            .USE_DOUBLER("FALSE")
        )
        clk_bufio (
            .I(input_clk),
            .DIVCLK(clk_int),
            .IOCLK(clk_io),
            .SERDESSTROBE()
        );


        BUFG
        clk_bufg (
            .I(clk_int),
            .O(output_clk)
        );

    end

end else begin


    assign clk_io = input_clk;


    assign clk_int = input_clk;
    assign output_clk = clk_int;

end

endgenerate

iddr #(
    .TARGET(TARGET),
    .IODDR_STYLE(IODDR_STYLE),
    .WIDTH(WIDTH)
)
data_iddr_inst (
    .clk(clk_io),
    .d(input_d),
    .q1(output_q1),
    .q2(output_q2)
);

endmodule
module ssio_ddr_in #
(

    parameter TARGET = "GENERIC",



    parameter IODDR_STYLE = "IODDR2",




    parameter CLOCK_INPUT_STYLE = "BUFIO2",

    parameter WIDTH = 1
)
(
    input  wire             input_clk,

    input  wire [WIDTH-1:0] input_d,

    output wire             output_clk,

    output wire [WIDTH-1:0] output_q1,
    output wire [WIDTH-1:0] output_q2
);


wire clk_int;
wire clk_io;

generate

if (TARGET == "XILINX") begin



    if (CLOCK_INPUT_STYLE == "BUFG") begin


        BUFG
        clk_bufg (
            .I(input_clk),
            .O(clk_int)
        );


        assign clk_io = clk_int;
        assign output_clk = clk_int;

    end else if (CLOCK_INPUT_STYLE == "BUFR") begin

        assign clk_int = input_clk;


        BUFIO
        clk_bufio (
            .I(clk_int),
            .O(clk_io)
        );


        BUFR #(
            .BUFR_DIVIDE("BYPASS")
        )
        clk_bufr (
            .I(clk_int),
            .O(output_clk),
            .CE(1'b1),
            .CLR(1'b0)
        );
        
    end else if (CLOCK_INPUT_STYLE == "BUFIO") begin

        assign clk_int = input_clk;


        BUFIO
        clk_bufio (
            .I(clk_int),
            .O(clk_io)
        );


        BUFG
        clk_bufg (
            .I(clk_int),
            .O(output_clk)
        );

    end else if (CLOCK_INPUT_STYLE == "BUFIO2") begin


        BUFIO2 #(
            .DIVIDE(1),
            .DIVIDE_BYPASS("TRUE"),
            .I_INVERT("FALSE"),
            .USE_DOUBLER("FALSE")
        )
        clk_bufio (
            .I(input_clk),
            .DIVCLK(clk_int),
            .IOCLK(clk_io),
            .SERDESSTROBE()
        );


        BUFG
        clk_bufg (
            .I(clk_int),
            .O(output_clk)
        );

    end

end else begin


    assign clk_io = input_clk;


    assign clk_int = input_clk;
    assign output_clk = clk_int;

end

endgenerate

iddr #(
    .TARGET(TARGET),
    .IODDR_STYLE(IODDR_STYLE),
    .WIDTH(WIDTH)
)
data_iddr_inst (
    .clk(clk_io),
    .d(input_d),
    .q1(output_q1),
    .q2(output_q2)
);

endmodule