data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/iarray113x.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/iarray113x.v:32: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n     do,\n     ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/iarray113x.v:55: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\noutput [WIDTH-1:0]  do;      \n                    ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/iarray113x.v:65: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\nreg [WIDTH-1:0]     do = {WIDTH{1'b0}};      \n                    ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/iarray113x.v:65: syntax error, unexpected '=', expecting ',' or ';'\nreg [WIDTH-1:0]     do = {WIDTH{1'b0}};      \n                       ^\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/iarray113x.v:109: syntax error, unexpected <=\n    do <= ido;\n       ^~\n%Error: Cannot continue\n"
module iarray113x
    (
     wrst_,
     wclk,
     wa,
     we,
     di,

     rrst_,
     rclk,
     ra,
     re,
     do,
     
     test,
     mask
     );

parameter ADDRBIT = 9;
parameter DEPTH   = 512;
parameter WIDTH   = 32;
parameter TYPE = "AUTO";
parameter MAXDEPTH = 0;
parameter MEM_RESET = "OFF";

input               wrst_;
input               wclk;
input [ADDRBIT-1:0] wa;
input               we;
input [WIDTH-1:0]   di;

input               rrst_;
input               rclk;
input [ADDRBIT-1:0] ra;
input               re;
output [WIDTH-1:0]  do;

input               test;
input               mask;

reg [ADDRBIT-1:0]   iwa = {ADDRBIT{1'b0}};
reg                 iwe;
reg [WIDTH-1:0]     idi = {WIDTH{1'b0}};

reg [ADDRBIT-1:0]   ira = {ADDRBIT{1'b0}};
reg [WIDTH-1:0]     do = {WIDTH{1'b0}};
wire [WIDTH-1:0]    ido;

reg [ADDRBIT-1:0]   cnt = {ADDRBIT{1'b0}};



generate
if (MEM_RESET == "ON")
    begin: on_reset
always @ (posedge wclk)
    if (~wrst_)
        begin
        cnt <= cnt + 1'b1;      
        iwa <= cnt;
        iwe <= 1'b1;
        idi <= {WIDTH{1'b0}};
        end
    else
        begin
        cnt <= {ADDRBIT{1'b0}};
        iwa <= wa;
        iwe <= we;
        idi <= di;
        end
    end
else
    begin: off_reset
always @ (posedge wclk)
    if (~wrst_) iwe <= 1'b0;
    else        iwe <= we;

always @ (posedge wclk)
        begin
        iwa <= wa;
        idi <= di;
        end
    end
endgenerate


always @ (posedge rclk)     
    begin
    ira <= ra;
    do <= ido;
    end


`ifdef  RTL_SIMULATION
reg                 ire = {1{1'b0}};
always @ (posedge rclk)  ire <= re;    
iramrwpx #(ADDRBIT,DEPTH,WIDTH) ram (wclk,iwa,iwe,idi,rclk,ira,ire,ido,test,mask);
`else
altsyncram111x #(ADDRBIT,DEPTH,WIDTH,TYPE, MAXDEPTH) ram
    (
    .data(idi),
    .wren(iwe),
    .wraddress(iwa),
    .rdaddress(ira),
    .wrclock(wclk),
    .rdclock(rclk),
    .q(ido));
`endif

endmodule
module iarray113x
    (
     wrst_,
     wclk,
     wa,
     we,
     di,

     rrst_,
     rclk,
     ra,
     re,
     do,
     
     test,
     mask
     );


parameter ADDRBIT = 9;
parameter DEPTH   = 512;
parameter WIDTH   = 32;
parameter TYPE = "AUTO";
parameter MAXDEPTH = 0;
parameter MEM_RESET = "OFF";

input               wrst_;
input               wclk;
input [ADDRBIT-1:0] wa;
input               we;
input [WIDTH-1:0]   di;

input               rrst_;
input               rclk;
input [ADDRBIT-1:0] ra;
input               re;
output [WIDTH-1:0]  do;

input               test;
input               mask;

reg [ADDRBIT-1:0]   iwa = {ADDRBIT{1'b0}};
reg                 iwe;
reg [WIDTH-1:0]     idi = {WIDTH{1'b0}};

reg [ADDRBIT-1:0]   ira = {ADDRBIT{1'b0}};
reg [WIDTH-1:0]     do = {WIDTH{1'b0}};
wire [WIDTH-1:0]    ido;

reg [ADDRBIT-1:0]   cnt = {ADDRBIT{1'b0}};



generate
if (MEM_RESET == "ON")
    begin: on_reset
always @ (posedge wclk)
    if (~wrst_)
        begin
        cnt <= cnt + 1'b1;      
        iwa <= cnt;
        iwe <= 1'b1;
        idi <= {WIDTH{1'b0}};
        end
    else
        begin
        cnt <= {ADDRBIT{1'b0}};
        iwa <= wa;
        iwe <= we;
        idi <= di;
        end
    end
else
    begin: off_reset
always @ (posedge wclk)
    if (~wrst_) iwe <= 1'b0;
    else        iwe <= we;

always @ (posedge wclk)
        begin
        iwa <= wa;
        idi <= di;
        end
    end
endgenerate


always @ (posedge rclk)     
    begin
    ira <= ra;
    do <= ido;
    end


`ifdef  RTL_SIMULATION
reg                 ire = {1{1'b0}};
always @ (posedge rclk)  ire <= re;    
iramrwpx #(ADDRBIT,DEPTH,WIDTH) ram (wclk,iwa,iwe,idi,rclk,ira,ire,ido,test,mask);
`else
altsyncram111x #(ADDRBIT,DEPTH,WIDTH,TYPE, MAXDEPTH) ram
    (
    .data(idi),
    .wren(iwe),
    .wraddress(iwa),
    .rdaddress(ira),
    .wrclock(wclk),
    .rdclock(rclk),
    .q(ido));
`endif

endmodule