data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v
1: b'%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:13: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog,data/full_repos/permissive/411838135/timescale.v\n             data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog,data/full_repos/permissive/411838135/timescale.v.v\n             data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog,data/full_repos/permissive/411838135/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:14: Cannot find include file: UART_defines.v\n`include "UART_defines.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:35: Define or directive not defined: \'`ADDR_WIDTH\'\ninput [`ADDR_WIDTH-1:0] wb_addr_i;\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:63: Define or directive not defined: \'`ADDR_WIDTH\'\nwire [`ADDR_WIDTH-1:0] wb_addr_i;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:79: Define or directive not defined: \'`FIFO_WIDTH\'\nwire [`FIFO_WIDTH-1:0] tf_data_in;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:80: Define or directive not defined: \'`FIFO_WIDTH\'\nwire [`FIFO_WIDTH-1:0] tf_data_out;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:85: Define or directive not defined: \'`FIFO_COUNTER_W\'\nwire [`FIFO_COUNTER_W-1:0] tf_count;\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:88: Define or directive not defined: \'`FIFO_REC_WIDTH\'\nreg [`FIFO_REC_WIDTH-1:0] rf_data_in;\n     ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:89: Define or directive not defined: \'`FIFO_REC_WIDTH\'\nwire [`FIFO_REC_WIDTH-1:0] rf_data_out;\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:94: Define or directive not defined: \'`FIFO_COUNTER_W\'\nwire [`FIFO_COUNTER_W-1:0] rf_count;\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:109: Define or directive not defined: \'`MC_RTS\'\nassign {cts, dsr, ri, dcd} = loopback ? {mcr[`MC_RTS],mcr[`MC_DTR],mcr[`MC_OUT1],mcr[`MC_OUT2]}\n                                             ^~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:109: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign {cts, dsr, ri, dcd} = loopback ? {mcr[`MC_RTS],mcr[`MC_DTR],mcr[`MC_OUT1],mcr[`MC_OUT2]}\n                                                    ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:109: Define or directive not defined: \'`MC_DTR\'\nassign {cts, dsr, ri, dcd} = loopback ? {mcr[`MC_RTS],mcr[`MC_DTR],mcr[`MC_OUT1],mcr[`MC_OUT2]}\n                                                          ^~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:109: Define or directive not defined: \'`MC_OUT1\'\nassign {cts, dsr, ri, dcd} = loopback ? {mcr[`MC_RTS],mcr[`MC_DTR],mcr[`MC_OUT1],mcr[`MC_OUT2]}\n                                                                       ^~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:109: Define or directive not defined: \'`MC_OUT2\'\nassign {cts, dsr, ri, dcd} = loopback ? {mcr[`MC_RTS],mcr[`MC_DTR],mcr[`MC_OUT1],mcr[`MC_OUT2]}\n                                                                                     ^~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:112: Define or directive not defined: \'`LC_DL\'\nassign dlab = lcr[`LC_DL];\n                  ^~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:112: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign dlab = lcr[`LC_DL];\n                        ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:117: Define or directive not defined: \'`MC_RTS\'\nassign rts_o = mcr[`MC_RTS];\n                   ^~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:117: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign rts_o = mcr[`MC_RTS];\n                          ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:118: Define or directive not defined: \'`MC_DTR\'\nassign dtr_o = mcr[`MC_DTR];\n                   ^~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:118: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign dtr_o = mcr[`MC_DTR];\n                          ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:131: Define or directive not defined: \'`FIFO_REC_WIDTH\'\ndefparam fifo_rx.fifo_width = `FIFO_REC_WIDTH;\n                              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:131: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\ndefparam fifo_rx.fifo_width = `FIFO_REC_WIDTH;\n                                             ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:137: Define or directive not defined: \'`REG_RB\'\n `REG_RB : begin  \n ^~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:137: syntax error, unexpected \':\', expecting endcase\n `REG_RB : begin  \n         ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:142: Define or directive not defined: \'`REG_IE\'\n `REG_IE : wb_dat_o <= #1 dlab ? dl[15:8] : ier;\n ^~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:143: Define or directive not defined: \'`REG_II\'\n `REG_II : wb_dat_o <= #1 iir;\n ^~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:144: Define or directive not defined: \'`REG_LC\'\n `REG_LC : wb_dat_o <= #1 lcr;\n ^~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:145: Define or directive not defined: \'`REG_LS\'\n `REG_LS : if (dlab)\n ^~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:153: Define or directive not defined: \'`REG_MS\'\n `REG_MS : wb_dat_o <= #1 msr;\n ^~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:154: Define or directive not defined: \'`REG_DL3\'\n `REG_DL3: wb_dat_o <= #1 dlab ? dl[23:16] : 8\'b0;\n ^~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:170: Define or directive not defined: \'`REG_LC\'\n if (wb_we_i && wb_addr_i==`REG_LC)\n                           ^~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:170: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (wb_we_i && wb_addr_i==`REG_LC)\n                                  ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:178: Define or directive not defined: \'`REG_IE\'\n if (wb_we_i && wb_addr_i==`REG_IE)\n                           ^~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:178: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (wb_we_i && wb_addr_i==`REG_IE)\n                                  ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:193: Define or directive not defined: \'`REG_FC\'\n if (wb_we_i && wb_addr_i==`REG_FC)\n                           ^~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:193: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (wb_we_i && wb_addr_i==`REG_FC)\n                                  ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:201: Define or directive not defined: \'`REG_MC\'\n if (wb_we_i && wb_addr_i==`REG_MC)\n                           ^~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:201: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (wb_we_i && wb_addr_i==`REG_MC)\n                                  ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:212: Define or directive not defined: \'`REG_TR\'\n if (!wb_rst_i && wb_we_i && wb_addr_i==`REG_TR)\n                                        ^~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:212: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (!wb_rst_i && wb_we_i && wb_addr_i==`REG_TR)\n                                               ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:222: Define or directive not defined: \'`FC_TL\'\nalways @(fcr[`FC_TL])\n             ^~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:222: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nalways @(fcr[`FC_TL])\n                   ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:223: Define or directive not defined: \'`FC_TL\'\n case (fcr[`FC_TL])\n           ^~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:262: Define or directive not defined: \'`REG_DL4\'\n if (!wb_rst_i && wb_we_i && wb_addr_i==`REG_DL4)\n                                        ^~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:262: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (!wb_rst_i && wb_we_i && wb_addr_i==`REG_DL4)\n                                                ^\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:275: Define or directive not defined: \'`MS_DDCD\'\n msr[`MS_DDCD:`MS_DCTS] <= #1 {dcd, ri, dsr, cts} ^ msr[`MS_DDCD:`MS_DCTS];\n     ^~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:275: Define or directive not defined: \'`MS_DCTS\'\n msr[`MS_DDCD:`MS_DCTS] <= #1 {dcd, ri, dsr, cts} ^ msr[`MS_DDCD:`MS_DCTS];\n              ^~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:275: Define or directive not defined: \'`MS_DDCD\'\n msr[`MS_DDCD:`MS_DCTS] <= #1 {dcd, ri, dsr, cts} ^ msr[`MS_DDCD:`MS_DCTS];\n                                                        ^~~~~~~~\n%Error: data/full_repos/permissive/411838135/rv/uart/uart16550/tags/initial/verilog/UART_regs.v:275: Define or directive not defined: \'`MS_DCTS\'\n msr[`MS_DDCD:`MS_DCTS] <= #1 {dcd, ri, dsr, cts} ^ msr[`MS_DDCD:`MS_DCTS];\n                                                                 ^~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module UART_regs (clk,
	wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i,


	ier, iir, fcr, mcr, lcr, lsr, msr, dl,

	modem_inputs,
	stx_o, srx_i,
	enable,
	rts_o, dtr_o
	);

input		clk;
input		wb_rst_i;
input	[`ADDR_WIDTH-1:0]	wb_addr_i;
input	[7:0]	wb_dat_i;
output	[7:0]	wb_dat_o;
input		wb_we_i;

output	[3:0]	ier;
output	[7:0]	iir;
output	[3:0]	fcr;
output	[4:0]	mcr;
output	[7:0]	lcr;
output	[7:0]	lsr;
output	[7:0]	msr;
output	[31:0]	dl;
output		stx_o;
input		srx_i;

input	[3:0]	modem_inputs;
output		enable;
output		rts_o;
output		dtr_o;

wire	[3:0]	modem_inputs;
reg		enable;
reg		stx_o;
wire		srx_i;

reg	[7:0]	wb_dat_o;

wire	[`ADDR_WIDTH-1:0]	wb_addr_i;
wire	[7:0]	wb_dat_i;


reg	[3:0]	ier;
reg	[7:0]	iir;
reg	[3:0]	fcr;
reg	[4:0]	mcr;
reg	[7:0]	lcr;
reg	[7:0]	lsr;
reg	[7:0]	msr;
reg	[31:0]	dl;

reg	[31:0]	dlc;


wire	[`FIFO_WIDTH-1:0]	tf_data_in;
wire	[`FIFO_WIDTH-1:0]	tf_data_out;
reg				tf_push;
reg				tf_pop;
wire				tf_underrun;
wire				tf_overrun;
wire	[`FIFO_COUNTER_W-1:0]	tf_count;


reg	[`FIFO_REC_WIDTH-1:0]	rf_data_in;
wire	[`FIFO_REC_WIDTH-1:0]	rf_data_out;
reg				rf_push;
reg				rf_pop;
wire				rf_underrun;
wire				rf_overrun;
wire	[`FIFO_COUNTER_W-1:0]	rf_count;
wire				rf_error_bit;

reg	[3:0]			trigger_level;

wire		dlab;
wire		cts_i, dsr_i, ri_i, dcd_i;
wire		loopback;
wire		cts, dsr, ri, dcd;
wire		rts_o, dtr_o;




assign {cts_i, dsr_i, ri_i, dcd_i} = modem_inputs;
assign {cts, dsr, ri, dcd} = loopback ? {mcr[`MC_RTS],mcr[`MC_DTR],mcr[`MC_OUT1],mcr[`MC_OUT2]}
		 : ~{cts_i,dsr_i,ri_i,dcd_i};

assign dlab = lcr[`LC_DL];
assign tf_data_in = wb_dat_i;
assign loopback = mcr[4];


assign	rts_o = mcr[`MC_RTS];
assign	dtr_o = mcr[`MC_DTR];






UART_TX_FIFO fifo_tx(clk, wb_rst_i, tf_data_in, tf_data_out,
	tf_push, tf_pop, tf_underrun, tf_overrun, tf_count);

UART_RX_FIFO fifo_rx(clk, wb_rst_i, rf_data_in, rf_data_out,
	rf_push, rf_pop, rf_underrun, rf_overrun, rf_count, rf_error_bit);

defparam fifo_rx.fifo_width = `FIFO_REC_WIDTH;

always @(posedge clk)

    if (~wb_we_i)
	case (wb_addr_i)
	`REG_RB : begin
			rf_pop <= #1 1;
			wb_dat_o <= #1 dlab ? dl[`DL1] : rf_data_out;
		  end

	`REG_IE	: wb_dat_o <= #1 dlab ? dl[`DL2] : ier;
	`REG_II	: wb_dat_o <= #1 iir;
	`REG_LC	: wb_dat_o <= #1 lcr;
	`REG_LS	: if (dlab)
			wb_dat_o <= #1 dl[`DL4];
		  else
		  begin
			wb_dat_o <= #1 lsr;

			lsr <= #1 lsr & 8'b00000001;
		  end
	`REG_MS	: wb_dat_o <= #1 msr;
	`REG_DL3: wb_dat_o <= #1 dlab ? dl[`DL3] : 8'b0;

	default:  wb_dat_o <= #1 8'b0;
	endcase
    else
	wb_dat_o <= #1 8'b0;






always @(posedge clk)
	if (wb_rst_i)
		lcr <= #1 8'b00000011;
	else
	if (wb_we_i && wb_addr_i==`REG_LC)
		lcr <= #1 wb_dat_i;


always @(posedge clk or posedge wb_rst_i)
	if (wb_rst_i)
		ier <= #1 4'b0000;
	else
	if (wb_we_i && wb_addr_i==`REG_IE)
		if (dlab)
		begin
			dl[`DL2] <= #1 wb_dat_i;
			dlc <= #1 dl;
		end
		else
			ier <= #1 wb_dat_i[3:0];



always @(posedge clk or posedge wb_rst_i)
	if (wb_rst_i)
		fcr <= #1 4'b1100;
	else
	if (wb_we_i && wb_addr_i==`REG_FC)
		fcr <= #1 {wb_dat_i[7:6],wb_dat_i[2:1]};


always @(posedge clk or posedge wb_rst_i)
	if (wb_rst_i)
		mcr <= #1 5'b00000;
	else
	if (wb_we_i && wb_addr_i==`REG_MC)
		if (dlab)
		begin
			dl[`DL3] <= #1 wb_dat_i;
			dlc <= #1 dl;
		end
		else
			mcr <= #1 wb_dat_i[4:0];


always @(posedge clk or posedge wb_rst_i)
	if (!wb_rst_i && wb_we_i && wb_addr_i==`REG_TR)
		if (dlab)
		begin
			dl[`DL1] <= #1 wb_dat_i;
			dlc <= #1 dl;
		end
		else
			tf_push  <= #1 1;


always @(fcr[`FC_TL])
	case (fcr[`FC_TL])
		2'b00 : trigger_level <= #1 1;
		2'b01 : trigger_level <= #1 4;
		2'b10 : trigger_level <= #1 8;
		2'b11 : trigger_level <= #1 14;
	endcase
	

always @(posedge clk or posedge wb_rst_i)
	if (wb_rst_i)
		tf_push <= #1 0;
	else
	if (tf_push == 1)
		tf_push <= #1 0;

always @(posedge clk or posedge wb_rst_i)
	if (wb_rst_i)
		tf_pop <= #1 0;
	else
	if (tf_pop == 1)
		tf_pop <= #1 0;

always @(posedge clk or posedge wb_rst_i)
	if (wb_rst_i)
		rf_push <= #1 0;
	else
	if (rf_push == 1)
		rf_push <= #1 0;

always @(posedge clk or posedge wb_rst_i)
	if (wb_rst_i)
		rf_pop <= #1 0;
	else
	if (rf_pop == 1)
		rf_pop <= #1 0;



always @(posedge clk)
	if (!wb_rst_i && wb_we_i && wb_addr_i==`REG_DL4)
	begin
		dl[`DL4] <= #1 wb_dat_i;
		dlc <= #1 dl;
	end






always @(posedge clk)
begin
	msr[`MS_DDCD:`MS_DCTS] <= #1 {dcd, ri, dsr, cts} ^ msr[`MS_DDCD:`MS_DCTS];
	msr[`MS_CDCD:`MS_CCTS] <= #1 {dcd, ri, dsr, cts};
end


always @(posedge wb_rst_i)
	dl <= #1 32'b0;




always @(posedge clk)
begin
	if (|dl)
		if (enable)
			dlc <= #1 dl;
		else
			dlc <= #1 dlc - 1;
end

always @(dlc)
	if (~|dlc)
		enable = 1;
	else
		enable = 0;




reg	rls_int;
reg	rda_int;
reg	ti_int;
reg	thre_int;
reg	ms_int;

reg	[5:0]	counter_t;

always @(posedge clk or posedge wb_rst_i)
begin
	if (wb_rst_i)
	begin
		rls_int  <= #1 0;
		rda_int  <= #1 0;
		ti_int   <= #1 0;
		thre_int <= #1 0;
		ms_int   <= #1 0;
	end
	else
	begin
		rls_int  <= #1 lsr[`LS_OE] | lsr[`LS_PE] | lsr['LS_FE] | lsr[`LS_BE];
		rda_int  <= #1 (rf_count >= trigger_level);
		thre_int <= #1 lsr[`LS_TFE];
		ms_int   <= #1 | msr[7:4];
		ti_int   <= #1 (counter_t == 0);
	end
end

always @(posedge clk or posedge wb_rst_i)
begin
	if (rls_int && ier[`IE_RLS])
	begin
		iir[`II_II] <= #1 `II_RLS;
		iir
	end
end







`define S_IDLE        0
`define S_SEND_START  1
`define S_SEND_BYTE   2
`define S_SEND_PARITY 3
`define S_SEND_STOP   4
`define S_POP_BYTE    5

reg	[2:0]	state;
reg	[3:0]	counter16;
reg	[2:0]	bit_counter;
reg	[6:0]	shift_out;
reg		bit_out;
reg		parity_xor;

always @(posedge clk or posedge wb_rst_i)
begin
  if (wb_rst_i)
  begin
	state     <= #1 `S_IDLE;
	stx_o     <= #1 0;
	counter16 <= #1 0;
  end
  else
  if (enable)
  begin
	case (state)
	`S_IDLE	 :	if (~|tf_count)
			begin
				state <= #1 `S_IDLE;
				stx_o <= #1 0;
			end
			else
			begin
				tf_pop <= #1 1;
				stx_o  <= #1 0;
				state  <= #1 `S_POP_BYTE;
			end
	`S_POP_BYTE :	begin
				tf_pop <= #1 0;
				case (lcr[1:0])
				2'b00 : begin
					bit_counter <= #1 3'b100;
					parity_xor  <= #1 ^tf_data_out[4:0];
				     end
				2'b01 : begin
					bit_counter <= #1 3'b101;
					parity_xor  <= #1 ^tf_data_out[5:0];
				     end
				2'b10 : begin
					bit_counter <= #1 3'b110;
					parity_xor  <= #1 ^tf_data_out[6:0];
				     end
				2'b11 : begin
					bit_counter <= #1 3'b111;
					parity_xor <= #1 ^tf_data_out[7:0];
				     end
				endcase
				{shift_out[6:0], bit_out} <= #1 tf_data_out;
				state <= #1 `S_SEND_START;
			end
	`S_SEND_START :	begin
				if (~|counter16)
					counter16 <= #1 4'b1111;
				else
				if (counter16 == 1)
				begin
					counter16 <= #1 0;
					state <= #1 `S_SEND_BYTE;
				end
				else
					counter16 <= #1 counter16 - 1;
				stx_o <= #1 1;
			end
	`S_SEND_BYTE :	begin
				if (~|counter16)
					counter16 <= #1 4'b1111;
				else
				if (counter16 == 1)
				begin
					if (|bit_counter)
					begin
						bit_counter <= #1 bit_counter - 1;
						{shift_out[5:0],bit_out  } <= #1 {shift_out[6:1], shift_out[0]};
						state <= #1 `S_SEND_BYTE;
					end
					else
					if (~lcr[`LC_PE])
					begin
						state <= #1 `S_SEND_STOP;
					end
					else
					begin
						case ({lcr[`LC_EP],lcr[`LC_SP]})
						2'b00:	bit_out <= #1 ~parity_xor;
						2'b01:	bit_out <= #1 1;
						2'b10:	bit_out <= #1 parity_xor;
						2'b11:	bit_out <= #1 0;
						endcase
						state <= #1 `S_SEND_PARITY;
					end
					counter16 <= #1 0;
				end
				else
					counter16 <= #1 counter16 - 1;
				stx_o <= #1 bit_out;
			end
	`S_SEND_PARITY :	begin
				if (~|counter16)
					counter16 <= #1 4'b1111;
				else
				if (counter16 == 1)
				begin
					counter16 <= #1 0;
					state <= #1 `S_SEND_STOP;
				end
				else
					counter16 <= #1 counter16 - 1;
				stx_o <= #1 bit_out;
			end
	`S_SEND_STOP :  begin
				if (~|counter16)
					counter16 <= #1 4'b1111;
				else
				if (counter16 == 1)
				begin
					counter16 <= #1 0;
					state <= #1 `S_IDLE;
				end
				else
					counter16 <= #1 counter16 - 1;
				stx_o <= #1 0;
			end

		default :
			state <= #1 `S_IDLE;
	endcase
  end
end






`define SR_IDLE		0
`define SR_REC_START	1
`define SR_REC_BIT	2
`define	SR_REC_PARITY	3
`define SR_REC_STOP	4
`define SR_CHECK_PARITY	5
`define SR_REC_PREPARE	6
`define SR_END_BIT	7
`define SR_CALC_PARITY	8
`define SR_WAIT1	9
`define SR_PUSH		10
`define SR_LAST		11

reg	[3:0]	rstate;
reg	[3:0]	rcounter16;
reg	[2:0]	rbit_counter;
reg	[7:0]	rshift;
reg		rparity;
reg		rparity_error;
reg		rframing_error;
reg		rbit_in;
reg		rparity_xor;

wire		rcounter16_eq_7 = (rcounter16 == 7);
wire		rcounter16_eq_0 = (rcounter16 == 0);
wire	[3:0]	rcounter16_minus_1 = rcounter16 - 1;

always @(posedge clk or posedge wb_rst_i)
begin
  if (wb_rst_i)
  begin
	rstate		<= #1 `SR_IDLE;
	rbit_in		<= #1 0;
	rcounter16	<= #1 0;
	rbit_counter	<= #1 0;
	rparity_xor	<= #1 0;
	rframing_error	<= #1 0;
	rparity_error	<= #1 0;
	rshift		<= #1 0;
  end
  else
  if (enable)
  begin
	case (rstate)
	`SR_IDLE :	if (srx_i==1)
			begin
				rstate <= #1 `SR_REC_START;
				rcounter16 <= #1 4'b1110;
			end
			else
				rstate <= #1 `SR_IDLE;
	`SR_REC_START :	begin
				if (rcounter16_eq_7)
					if (srx_i==0)
						rstate <= #1 `SR_IDLE;
					else
						rstate <= #1 `SR_REC_PREPARE;
				rcounter16 <= #1 rcounter16_minus_1;
			end
	`SR_REC_PREPARE:begin
				case (lcr[1:0])
				2'b00 : rbit_counter <= #1 3'b100;
				2'b01 : rbit_counter <= #1 3'b101;
				2'b10 : rbit_counter <= #1 3'b110;
				2'b11 : rbit_counter <= #1 3'b111;
				endcase
				if (rcounter16_eq_0)
				begin
					rstate		<= #1 `SR_REC_BIT;
					rcounter16	<= #1 4'b1110;
					rshift		<= #1 0;
				end
				else
					rstate <= #1 `SR_REC_PREPARE;
				rcounter16 <= #1 rcounter16_minus_1;
			end
	`SR_REC_BIT :	begin
				if (rcounter16_eq_0)
					rstate <= #1 `SR_END_BIT;
				if (rcounter16_eq_7)
					case (lcr[1:0])
					2'b00 : rshift[4:0]  <= #1 {srx_i, rshift[4:1]};
					2'b01 : rshift[5:0]  <= #1 {srx_i, rshift[5:1]};
					2'b10 : rshift[6:0]  <= #1 {srx_i, rshift[6:1]};
					2'b11 : rshift[7:0]  <= #1 {srx_i, rshift[7:1]};
					endcase
				rcounter16 <= #1 rcounter16_minus_1;
			end
	`SR_END_BIT :   begin
				if (rbit_counter==0)
					if (lcr[`LC_PE])
						rstate <= #1 `SR_REC_PARITY;
					else
					begin
						rstate <= #1 `SR_REC_STOP;
						rparity_error <= #1 0;
					end
				else
				begin
					rstate <= #1 `SR_REC_BIT;
					rbit_counter <= #1 rbit_counter - 1;
				end
				rcounter16 <= #1 4'b1110;
			end
	`SR_REC_PARITY: begin
				if (rcounter16_eq_7)
				begin
					rparity <= #1 srx_i;
					rstate <= #1 `SR_CALC_PARITY;
				end
				rcounter16 <= #1 rcounter16_minus_1;
			end
	`SR_CALC_PARITY : begin
				rcounter16  <= #1 rcounter16_minus_1;
				rparity_xor <= #1 ^{rshift,rparity};
				rstate      <= #1 `SR_CHECK_PARITY;
			  end
	`SR_CHECK_PARITY: begin
				case ({lcr[`LC_EP],lcr[`LC_SP]})
				2'b00: rparity_error <= #1 ~rparity_xor;
				2'b01: rparity_error <= #1 ~rparity;
				2'b10: rparity_error <= #1 rparity_xor;
				2'b11: rparity_error <= #1 rparity;
				endcase
				rcounter16 <= #1 rcounter16_minus_1;
				rstate <= #1 `SR_WAIT1;
			  end
	`SR_WAIT1 :	if (rcounter16_eq_0)
			begin
				rstate <= #1 `SR_REC_STOP;
				rcounter16 <= #1 4'b1110;
			end
			else
			begin
				rcounter16 <= #1 rcounter16_minus_1;

			end
	`SR_REC_STOP :	begin
				if (rcounter16_eq_7)
				begin
					rframing_error <= #1 srx_i;
					rf_data_in <= #1 {rshift, rparity_error, rframing_error};
					rstate <= #1 `SR_PUSH;
				end
				rcounter16 <= #1 rcounter16_minus_1;
			end
	`SR_PUSH :	begin

				$display($time, ": received: %b", rf_data_in);
				rf_push    <= #1 1;
				rstate     <= #1 `SR_LAST;
			end
	`SR_LAST :	begin
				if (rcounter16_eq_0)
					rstate <= #1 `SR_IDLE;
				rcounter16 <= #1 rcounter16_minus_1;
				rf_push <= #1 0;
			end
	default : rstate <= #1 `SR_IDLE;
	endcase
  end
end




reg	[3:0]	counter_b;

always @(posedge clk or posedge wb_rst_i)
begin
	if (wb_rst_i)
		counter_b <= #1 4'd11;
	else
	if (enable)
		if (srx_i)
		begin
			counter_b <= #1 4'd11;
			lsr[`LS_BI] <= #1 0;
		end
		else
		if (counter_b == 0)
			lsr[`LS_BI] <= #1 1;
		else
			counter_b <= #1 counter_b - 1;
end




always @(posedge clk or posedge wb_rst_i)
begin
	if (wb_rst_i)
		counter_t <= #1 6'd44;
	else
	if (enable)
		if(rf_push | rf_pop | rda_int)
			counter_t <= #1 6'd44;
		else
		if (counter_t != 0)
			counter_t <= #1 counter_t - 1;		
end


always @(posedge clk or wb_rst_i)
begin
	if (wb_rst_i)
		lsr <= #1 8'b01100000;
	else
	begin
		lsr[0] <= #1 (rf_count!=0);
		lsr[1] <= #1 rf_overrun;
		lsr[2] <= #1 rf_data_out[1];

		lsr[3] <= #1 rf_data_out[0];
		lsr[5] <= #1 (tf_count==0);
		lsr[6] <= #1 (tf_count==0 && state == `S_IDLE);
		lsr[7] <= #1 rf_error_bit;
	end
end

endmodule
module UART_regs (clk,
	wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i,


	ier, iir, fcr, mcr, lcr, lsr, msr, dl,

	modem_inputs,
	stx_o, srx_i,
	enable,
	rts_o, dtr_o
	);


input		clk;
input		wb_rst_i;
input	[`ADDR_WIDTH-1:0]	wb_addr_i;
input	[7:0]	wb_dat_i;
output	[7:0]	wb_dat_o;
input		wb_we_i;

output	[3:0]	ier;
output	[7:0]	iir;
output	[3:0]	fcr;
output	[4:0]	mcr;
output	[7:0]	lcr;
output	[7:0]	lsr;
output	[7:0]	msr;
output	[31:0]	dl;
output		stx_o;
input		srx_i;

input	[3:0]	modem_inputs;
output		enable;
output		rts_o;
output		dtr_o;

wire	[3:0]	modem_inputs;
reg		enable;
reg		stx_o;
wire		srx_i;

reg	[7:0]	wb_dat_o;

wire	[`ADDR_WIDTH-1:0]	wb_addr_i;
wire	[7:0]	wb_dat_i;


reg	[3:0]	ier;
reg	[7:0]	iir;
reg	[3:0]	fcr;
reg	[4:0]	mcr;
reg	[7:0]	lcr;
reg	[7:0]	lsr;
reg	[7:0]	msr;
reg	[31:0]	dl;

reg	[31:0]	dlc;


wire	[`FIFO_WIDTH-1:0]	tf_data_in;
wire	[`FIFO_WIDTH-1:0]	tf_data_out;
reg				tf_push;
reg				tf_pop;
wire				tf_underrun;
wire				tf_overrun;
wire	[`FIFO_COUNTER_W-1:0]	tf_count;


reg	[`FIFO_REC_WIDTH-1:0]	rf_data_in;
wire	[`FIFO_REC_WIDTH-1:0]	rf_data_out;
reg				rf_push;
reg				rf_pop;
wire				rf_underrun;
wire				rf_overrun;
wire	[`FIFO_COUNTER_W-1:0]	rf_count;
wire				rf_error_bit;

reg	[3:0]			trigger_level;

wire		dlab;
wire		cts_i, dsr_i, ri_i, dcd_i;
wire		loopback;
wire		cts, dsr, ri, dcd;
wire		rts_o, dtr_o;




assign {cts_i, dsr_i, ri_i, dcd_i} = modem_inputs;
assign {cts, dsr, ri, dcd} = loopback ? {mcr[`MC_RTS],mcr[`MC_DTR],mcr[`MC_OUT1],mcr[`MC_OUT2]}
		 : ~{cts_i,dsr_i,ri_i,dcd_i};

assign dlab = lcr[`LC_DL];
assign tf_data_in = wb_dat_i;
assign loopback = mcr[4];


assign	rts_o = mcr[`MC_RTS];
assign	dtr_o = mcr[`MC_DTR];






UART_TX_FIFO fifo_tx(clk, wb_rst_i, tf_data_in, tf_data_out,
	tf_push, tf_pop, tf_underrun, tf_overrun, tf_count);

UART_RX_FIFO fifo_rx(clk, wb_rst_i, rf_data_in, rf_data_out,
	rf_push, rf_pop, rf_underrun, rf_overrun, rf_count, rf_error_bit);

defparam fifo_rx.fifo_width = `FIFO_REC_WIDTH;

always @(posedge clk)

    if (~wb_we_i)
	case (wb_addr_i)
	`REG_RB : begin
			rf_pop <= #1 1;
			wb_dat_o <= #1 dlab ? dl[`DL1] : rf_data_out;
		  end

	`REG_IE	: wb_dat_o <= #1 dlab ? dl[`DL2] : ier;
	`REG_II	: wb_dat_o <= #1 iir;
	`REG_LC	: wb_dat_o <= #1 lcr;
	`REG_LS	: if (dlab)
			wb_dat_o <= #1 dl[`DL4];
		  else
		  begin
			wb_dat_o <= #1 lsr;

			lsr <= #1 lsr & 8'b00000001;
		  end
	`REG_MS	: wb_dat_o <= #1 msr;
	`REG_DL3: wb_dat_o <= #1 dlab ? dl[`DL3] : 8'b0;

	default:  wb_dat_o <= #1 8'b0;
	endcase
    else
	wb_dat_o <= #1 8'b0;






always @(posedge clk)
	if (wb_rst_i)
		lcr <= #1 8'b00000011;
	else
	if (wb_we_i && wb_addr_i==`REG_LC)
		lcr <= #1 wb_dat_i;


always @(posedge clk or posedge wb_rst_i)
	if (wb_rst_i)
		ier <= #1 4'b0000;
	else
	if (wb_we_i && wb_addr_i==`REG_IE)
		if (dlab)
		begin
			dl[`DL2] <= #1 wb_dat_i;
			dlc <= #1 dl;
		end
		else
			ier <= #1 wb_dat_i[3:0];



always @(posedge clk or posedge wb_rst_i)
	if (wb_rst_i)
		fcr <= #1 4'b1100;
	else
	if (wb_we_i && wb_addr_i==`REG_FC)
		fcr <= #1 {wb_dat_i[7:6],wb_dat_i[2:1]};


always @(posedge clk or posedge wb_rst_i)
	if (wb_rst_i)
		mcr <= #1 5'b00000;
	else
	if (wb_we_i && wb_addr_i==`REG_MC)
		if (dlab)
		begin
			dl[`DL3] <= #1 wb_dat_i;
			dlc <= #1 dl;
		end
		else
			mcr <= #1 wb_dat_i[4:0];


always @(posedge clk or posedge wb_rst_i)
	if (!wb_rst_i && wb_we_i && wb_addr_i==`REG_TR)
		if (dlab)
		begin
			dl[`DL1] <= #1 wb_dat_i;
			dlc <= #1 dl;
		end
		else
			tf_push  <= #1 1;


always @(fcr[`FC_TL])
	case (fcr[`FC_TL])
		2'b00 : trigger_level <= #1 1;
		2'b01 : trigger_level <= #1 4;
		2'b10 : trigger_level <= #1 8;
		2'b11 : trigger_level <= #1 14;
	endcase
	

always @(posedge clk or posedge wb_rst_i)
	if (wb_rst_i)
		tf_push <= #1 0;
	else
	if (tf_push == 1)
		tf_push <= #1 0;

always @(posedge clk or posedge wb_rst_i)
	if (wb_rst_i)
		tf_pop <= #1 0;
	else
	if (tf_pop == 1)
		tf_pop <= #1 0;

always @(posedge clk or posedge wb_rst_i)
	if (wb_rst_i)
		rf_push <= #1 0;
	else
	if (rf_push == 1)
		rf_push <= #1 0;

always @(posedge clk or posedge wb_rst_i)
	if (wb_rst_i)
		rf_pop <= #1 0;
	else
	if (rf_pop == 1)
		rf_pop <= #1 0;



always @(posedge clk)
	if (!wb_rst_i && wb_we_i && wb_addr_i==`REG_DL4)
	begin
		dl[`DL4] <= #1 wb_dat_i;
		dlc <= #1 dl;
	end






always @(posedge clk)
begin
	msr[`MS_DDCD:`MS_DCTS] <= #1 {dcd, ri, dsr, cts} ^ msr[`MS_DDCD:`MS_DCTS];
	msr[`MS_CDCD:`MS_CCTS] <= #1 {dcd, ri, dsr, cts};
end


always @(posedge wb_rst_i)
	dl <= #1 32'b0;




always @(posedge clk)
begin
	if (|dl)
		if (enable)
			dlc <= #1 dl;
		else
			dlc <= #1 dlc - 1;
end

always @(dlc)
	if (~|dlc)
		enable = 1;
	else
		enable = 0;




reg	rls_int;
reg	rda_int;
reg	ti_int;
reg	thre_int;
reg	ms_int;

reg	[5:0]	counter_t;

always @(posedge clk or posedge wb_rst_i)
begin
	if (wb_rst_i)
	begin
		rls_int  <= #1 0;
		rda_int  <= #1 0;
		ti_int   <= #1 0;
		thre_int <= #1 0;
		ms_int   <= #1 0;
	end
	else
	begin
		rls_int  <= #1 lsr[`LS_OE] | lsr[`LS_PE] | lsr['LS_FE] | lsr[`LS_BE];
		rda_int  <= #1 (rf_count >= trigger_level);
		thre_int <= #1 lsr[`LS_TFE];
		ms_int   <= #1 | msr[7:4];
		ti_int   <= #1 (counter_t == 0);
	end
end

always @(posedge clk or posedge wb_rst_i)
begin
	if (rls_int && ier[`IE_RLS])
	begin
		iir[`II_II] <= #1 `II_RLS;
		iir
	end
end







`define S_IDLE        0
`define S_SEND_START  1
`define S_SEND_BYTE   2
`define S_SEND_PARITY 3
`define S_SEND_STOP   4
`define S_POP_BYTE    5

reg	[2:0]	state;
reg	[3:0]	counter16;
reg	[2:0]	bit_counter;
reg	[6:0]	shift_out;
reg		bit_out;
reg		parity_xor;

always @(posedge clk or posedge wb_rst_i)
begin
  if (wb_rst_i)
  begin
	state     <= #1 `S_IDLE;
	stx_o     <= #1 0;
	counter16 <= #1 0;
  end
  else
  if (enable)
  begin
	case (state)
	`S_IDLE	 :	if (~|tf_count)
			begin
				state <= #1 `S_IDLE;
				stx_o <= #1 0;
			end
			else
			begin
				tf_pop <= #1 1;
				stx_o  <= #1 0;
				state  <= #1 `S_POP_BYTE;
			end
	`S_POP_BYTE :	begin
				tf_pop <= #1 0;
				case (lcr[1:0])
				2'b00 : begin
					bit_counter <= #1 3'b100;
					parity_xor  <= #1 ^tf_data_out[4:0];
				     end
				2'b01 : begin
					bit_counter <= #1 3'b101;
					parity_xor  <= #1 ^tf_data_out[5:0];
				     end
				2'b10 : begin
					bit_counter <= #1 3'b110;
					parity_xor  <= #1 ^tf_data_out[6:0];
				     end
				2'b11 : begin
					bit_counter <= #1 3'b111;
					parity_xor <= #1 ^tf_data_out[7:0];
				     end
				endcase
				{shift_out[6:0], bit_out} <= #1 tf_data_out;
				state <= #1 `S_SEND_START;
			end
	`S_SEND_START :	begin
				if (~|counter16)
					counter16 <= #1 4'b1111;
				else
				if (counter16 == 1)
				begin
					counter16 <= #1 0;
					state <= #1 `S_SEND_BYTE;
				end
				else
					counter16 <= #1 counter16 - 1;
				stx_o <= #1 1;
			end
	`S_SEND_BYTE :	begin
				if (~|counter16)
					counter16 <= #1 4'b1111;
				else
				if (counter16 == 1)
				begin
					if (|bit_counter)
					begin
						bit_counter <= #1 bit_counter - 1;
						{shift_out[5:0],bit_out  } <= #1 {shift_out[6:1], shift_out[0]};
						state <= #1 `S_SEND_BYTE;
					end
					else
					if (~lcr[`LC_PE])
					begin
						state <= #1 `S_SEND_STOP;
					end
					else
					begin
						case ({lcr[`LC_EP],lcr[`LC_SP]})
						2'b00:	bit_out <= #1 ~parity_xor;
						2'b01:	bit_out <= #1 1;
						2'b10:	bit_out <= #1 parity_xor;
						2'b11:	bit_out <= #1 0;
						endcase
						state <= #1 `S_SEND_PARITY;
					end
					counter16 <= #1 0;
				end
				else
					counter16 <= #1 counter16 - 1;
				stx_o <= #1 bit_out;
			end
	`S_SEND_PARITY :	begin
				if (~|counter16)
					counter16 <= #1 4'b1111;
				else
				if (counter16 == 1)
				begin
					counter16 <= #1 0;
					state <= #1 `S_SEND_STOP;
				end
				else
					counter16 <= #1 counter16 - 1;
				stx_o <= #1 bit_out;
			end
	`S_SEND_STOP :  begin
				if (~|counter16)
					counter16 <= #1 4'b1111;
				else
				if (counter16 == 1)
				begin
					counter16 <= #1 0;
					state <= #1 `S_IDLE;
				end
				else
					counter16 <= #1 counter16 - 1;
				stx_o <= #1 0;
			end

		default :
			state <= #1 `S_IDLE;
	endcase
  end
end






`define SR_IDLE		0
`define SR_REC_START	1
`define SR_REC_BIT	2
`define	SR_REC_PARITY	3
`define SR_REC_STOP	4
`define SR_CHECK_PARITY	5
`define SR_REC_PREPARE	6
`define SR_END_BIT	7
`define SR_CALC_PARITY	8
`define SR_WAIT1	9
`define SR_PUSH		10
`define SR_LAST		11

reg	[3:0]	rstate;
reg	[3:0]	rcounter16;
reg	[2:0]	rbit_counter;
reg	[7:0]	rshift;
reg		rparity;
reg		rparity_error;
reg		rframing_error;
reg		rbit_in;
reg		rparity_xor;

wire		rcounter16_eq_7 = (rcounter16 == 7);
wire		rcounter16_eq_0 = (rcounter16 == 0);
wire	[3:0]	rcounter16_minus_1 = rcounter16 - 1;

always @(posedge clk or posedge wb_rst_i)
begin
  if (wb_rst_i)
  begin
	rstate		<= #1 `SR_IDLE;
	rbit_in		<= #1 0;
	rcounter16	<= #1 0;
	rbit_counter	<= #1 0;
	rparity_xor	<= #1 0;
	rframing_error	<= #1 0;
	rparity_error	<= #1 0;
	rshift		<= #1 0;
  end
  else
  if (enable)
  begin
	case (rstate)
	`SR_IDLE :	if (srx_i==1)
			begin
				rstate <= #1 `SR_REC_START;
				rcounter16 <= #1 4'b1110;
			end
			else
				rstate <= #1 `SR_IDLE;
	`SR_REC_START :	begin
				if (rcounter16_eq_7)
					if (srx_i==0)
						rstate <= #1 `SR_IDLE;
					else
						rstate <= #1 `SR_REC_PREPARE;
				rcounter16 <= #1 rcounter16_minus_1;
			end
	`SR_REC_PREPARE:begin
				case (lcr[1:0])
				2'b00 : rbit_counter <= #1 3'b100;
				2'b01 : rbit_counter <= #1 3'b101;
				2'b10 : rbit_counter <= #1 3'b110;
				2'b11 : rbit_counter <= #1 3'b111;
				endcase
				if (rcounter16_eq_0)
				begin
					rstate		<= #1 `SR_REC_BIT;
					rcounter16	<= #1 4'b1110;
					rshift		<= #1 0;
				end
				else
					rstate <= #1 `SR_REC_PREPARE;
				rcounter16 <= #1 rcounter16_minus_1;
			end
	`SR_REC_BIT :	begin
				if (rcounter16_eq_0)
					rstate <= #1 `SR_END_BIT;
				if (rcounter16_eq_7)
					case (lcr[1:0])
					2'b00 : rshift[4:0]  <= #1 {srx_i, rshift[4:1]};
					2'b01 : rshift[5:0]  <= #1 {srx_i, rshift[5:1]};
					2'b10 : rshift[6:0]  <= #1 {srx_i, rshift[6:1]};
					2'b11 : rshift[7:0]  <= #1 {srx_i, rshift[7:1]};
					endcase
				rcounter16 <= #1 rcounter16_minus_1;
			end
	`SR_END_BIT :   begin
				if (rbit_counter==0)
					if (lcr[`LC_PE])
						rstate <= #1 `SR_REC_PARITY;
					else
					begin
						rstate <= #1 `SR_REC_STOP;
						rparity_error <= #1 0;
					end
				else
				begin
					rstate <= #1 `SR_REC_BIT;
					rbit_counter <= #1 rbit_counter - 1;
				end
				rcounter16 <= #1 4'b1110;
			end
	`SR_REC_PARITY: begin
				if (rcounter16_eq_7)
				begin
					rparity <= #1 srx_i;
					rstate <= #1 `SR_CALC_PARITY;
				end
				rcounter16 <= #1 rcounter16_minus_1;
			end
	`SR_CALC_PARITY : begin
				rcounter16  <= #1 rcounter16_minus_1;
				rparity_xor <= #1 ^{rshift,rparity};
				rstate      <= #1 `SR_CHECK_PARITY;
			  end
	`SR_CHECK_PARITY: begin
				case ({lcr[`LC_EP],lcr[`LC_SP]})
				2'b00: rparity_error <= #1 ~rparity_xor;
				2'b01: rparity_error <= #1 ~rparity;
				2'b10: rparity_error <= #1 rparity_xor;
				2'b11: rparity_error <= #1 rparity;
				endcase
				rcounter16 <= #1 rcounter16_minus_1;
				rstate <= #1 `SR_WAIT1;
			  end
	`SR_WAIT1 :	if (rcounter16_eq_0)
			begin
				rstate <= #1 `SR_REC_STOP;
				rcounter16 <= #1 4'b1110;
			end
			else
			begin
				rcounter16 <= #1 rcounter16_minus_1;

			end
	`SR_REC_STOP :	begin
				if (rcounter16_eq_7)
				begin
					rframing_error <= #1 srx_i;
					rf_data_in <= #1 {rshift, rparity_error, rframing_error};
					rstate <= #1 `SR_PUSH;
				end
				rcounter16 <= #1 rcounter16_minus_1;
			end
	`SR_PUSH :	begin

				$display($time, ": received: %b", rf_data_in);
				rf_push    <= #1 1;
				rstate     <= #1 `SR_LAST;
			end
	`SR_LAST :	begin
				if (rcounter16_eq_0)
					rstate <= #1 `SR_IDLE;
				rcounter16 <= #1 rcounter16_minus_1;
				rf_push <= #1 0;
			end
	default : rstate <= #1 `SR_IDLE;
	endcase
  end
end




reg	[3:0]	counter_b;

always @(posedge clk or posedge wb_rst_i)
begin
	if (wb_rst_i)
		counter_b <= #1 4'd11;
	else
	if (enable)
		if (srx_i)
		begin
			counter_b <= #1 4'd11;
			lsr[`LS_BI] <= #1 0;
		end
		else
		if (counter_b == 0)
			lsr[`LS_BI] <= #1 1;
		else
			counter_b <= #1 counter_b - 1;
end




always @(posedge clk or posedge wb_rst_i)
begin
	if (wb_rst_i)
		counter_t <= #1 6'd44;
	else
	if (enable)
		if(rf_push | rf_pop | rda_int)
			counter_t <= #1 6'd44;
		else
		if (counter_t != 0)
			counter_t <= #1 counter_t - 1;		
end


always @(posedge clk or wb_rst_i)
begin
	if (wb_rst_i)
		lsr <= #1 8'b01100000;
	else
	begin
		lsr[0] <= #1 (rf_count!=0);
		lsr[1] <= #1 rf_overrun;
		lsr[2] <= #1 rf_data_out[1];

		lsr[3] <= #1 rf_data_out[0];
		lsr[5] <= #1 (tf_count==0);
		lsr[6] <= #1 (tf_count==0 && state == `S_IDLE);
		lsr[7] <= #1 rf_error_bit;
	end
end

endmodule