data/full_repos/permissive/43858668/final_verilog/src/clib/c_incr.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_incr.v:35: Cannot find include file: c_functions.v\n`include "c_functions.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v.sv\n             c_functions.v\n             c_functions.v.v\n             c_functions.v.sv\n             obj_dir/c_functions.v\n             obj_dir/c_functions.v.v\n             obj_dir/c_functions.v.sv\n%Error: Exiting due to 1 error(s)\n'
module c_incr
  (data_in, data_out);
   
`include "c_functions.v"
   
   parameter width = 3;
   
   parameter [0:width-1] min_value = 0;
   parameter [0:width-1] max_value = (1 << width) - 1;
   
   localparam num_values = max_value - min_value + 1;
   
   localparam swidth = suffix_length(min_value, max_value);
   
   localparam cwidth = clogb(num_values);
   

   input [0:width-1] data_in;
   

   output [0:width-1] data_out;
   wire [0:width-1]   data_out;
   
   wire 	      wrap;
   
   genvar 	      i;
   
   generate
      


      for(i = 0; i < (width-swidth); i = i + 1)
	begin:prefix
	   assign data_out[i] = min_value[i];
	end
      

      if(cwidth > 0)
	begin
	   
	   assign wrap = (data_in[(width-cwidth):width-1] ==
			  max_value[(width-cwidth):width-1]);
	   
	   wire [0:cwidth-1] lsb_incr;
	   assign lsb_incr = data_in[(width-cwidth):width-1] + 1'b1;
	   
	   if((1 << cwidth) == num_values)
	     begin
		


		assign data_out[(width-cwidth):width-1] = lsb_incr;
		
	     end
	   else
	     begin
		


		assign data_out[(width-cwidth):width-1]
		  = wrap ? min_value[(width-cwidth):width-1] : lsb_incr;
		
	     end
	   
	end
      else
	assign wrap = 1'b1;
      




      if(swidth > cwidth)
	begin
	   
	   wire carry;
	   assign carry = &data_in[(width-cwidth):width-1];
	   
	   assign data_out[(width-swidth):(width-cwidth)-1]
	     = wrap ? min_value[(width-swidth):(width-cwidth)-1] :
	       carry ? max_value[(width-swidth):(width-cwidth)-1] :
	       data_in[(width-swidth):(width-cwidth)-1];
	   
	end
      
   endgenerate
   
endmodule
module c_incr
  (data_in, data_out);

   
`include "c_functions.v"
   
   parameter width = 3;
   
   parameter [0:width-1] min_value = 0;
   parameter [0:width-1] max_value = (1 << width) - 1;
   
   localparam num_values = max_value - min_value + 1;
   
   localparam swidth = suffix_length(min_value, max_value);
   
   localparam cwidth = clogb(num_values);
   

   input [0:width-1] data_in;
   

   output [0:width-1] data_out;
   wire [0:width-1]   data_out;
   
   wire 	      wrap;
   
   genvar 	      i;
   
   generate
      


      for(i = 0; i < (width-swidth); i = i + 1)
	begin:prefix
	   assign data_out[i] = min_value[i];
	end
      

      if(cwidth > 0)
	begin
	   
	   assign wrap = (data_in[(width-cwidth):width-1] ==
			  max_value[(width-cwidth):width-1]);
	   
	   wire [0:cwidth-1] lsb_incr;
	   assign lsb_incr = data_in[(width-cwidth):width-1] + 1'b1;
	   
	   if((1 << cwidth) == num_values)
	     begin
		


		assign data_out[(width-cwidth):width-1] = lsb_incr;
		
	     end
	   else
	     begin
		


		assign data_out[(width-cwidth):width-1]
		  = wrap ? min_value[(width-cwidth):width-1] : lsb_incr;
		
	     end
	   
	end
      else
	assign wrap = 1'b1;
      




      if(swidth > cwidth)
	begin
	   
	   wire carry;
	   assign carry = &data_in[(width-cwidth):width-1];
	   
	   assign data_out[(width-swidth):(width-cwidth)-1]
	     = wrap ? min_value[(width-swidth):(width-cwidth)-1] :
	       carry ? max_value[(width-swidth):(width-cwidth)-1] :
	       data_in[(width-swidth):(width-cwidth)-1];
	   
	end
      
   endgenerate
   
endmodule