data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Polynomial_multiplier_prime/old_codes/pol_mul256_parallel_in_old.v
1: b"%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Polynomial_multiplier_prime/old_codes/pol_mul256_parallel_in_old.v:76: Cannot find file containing module: 'poly_load_control_BRAM1'\npoly_load_control_BRAM1 PLC(clk, rst, s_address, s_load, s_load_done);\n^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Polynomial_multiplier_prime/old_codes,data/full_repos/permissive/428190211/poly_load_control_BRAM1\n             data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Polynomial_multiplier_prime/old_codes,data/full_repos/permissive/428190211/poly_load_control_BRAM1.v\n             data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Polynomial_multiplier_prime/old_codes,data/full_repos/permissive/428190211/poly_load_control_BRAM1.sv\n             poly_load_control_BRAM1\n             poly_load_control_BRAM1.v\n             poly_load_control_BRAM1.sv\n             obj_dir/poly_load_control_BRAM1\n             obj_dir/poly_load_control_BRAM1.v\n             obj_dir/poly_load_control_BRAM1.sv\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Polynomial_multiplier_prime/old_codes/pol_mul256_parallel_in_old.v:78: Cannot find file containing module: 'buffer_muxer1'\nbuffer_muxer1 BUFFMUX(a_buffer[624 : 612], a_buffer[573 : 561], a_buffer[522 : 510],\n^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module poly_mul256_parallel_in1(clk, rst, acc_clear, pol_load_coeff4x,
								bram_address_relative, pol_64bit_in,  
								s_address, s_vec_64, 
								read, coeff4x_out, pol_mul_done);
								
input clk, rst;
input pol_load_coeff4x;
input acc_clear;
output reg [6:0] bram_address_relative;
input [63:0] pol_64bit_in;								
output [7:0] s_address;
input [63:0] s_vec_64;
input read;

output [63:0] coeff4x_out;
output pol_mul_done;

reg rst_s_load;
wire s_load, s_load_done;

reg poly_load;

reg shift_secret, acc_en, bram_address_inc;
reg [3:0] state, nextstate;
reg [8:0] counter;
wire counter_finish;
wire [12:0] a_coeff;

reg [675:0] a_buffer;
reg poly_shift, buffer_empty;

reg [3:0] buffer_counter;
reg rst_buffer_counter;
wire buffer_counter_finish;


reg [3327:0] acc;
wire [3327:0] result;
wire [63:0] bug;
reg [1023:0] secret;


always @(posedge clk)
begin
	if (s_load)
		secret <= {s_vec_64, secret[1023:64]};
	else if (shift_secret)
			secret <= {secret[1019:0], secret[1023:1020] ^ 4'b1000};
	else
	       secret <= secret;
end

assign bug = secret[1023:960];


poly_load_control_BRAM1 PLC(clk, rst, s_address, s_load, s_load_done);

buffer_muxer1 BUFFMUX(a_buffer[624 : 612], a_buffer[573 : 561], a_buffer[522 : 510],
					 a_buffer[471 : 459], a_buffer[420 : 408], a_buffer[369 : 357],
					 a_buffer[318 : 306], a_buffer[267 : 255], a_buffer[216 : 204],
					 a_buffer[165 : 153], a_buffer[114 : 102], a_buffer[63 : 51],
					 a_buffer[12 : 0], 
					 a_buffer[60 : 48],
					 buffer_counter, pol_load_coeff4x, a_coeff);





always @(posedge clk)
begin
	if (pol_load_coeff4x == 0)
		begin
			if (poly_load)
				begin
					a_buffer <= {pol_64bit_in, a_buffer[675:64]};
					buffer_empty <= 0;
				end
			else if (poly_shift)
				begin
					a_buffer <= {13'bxxxxxxxxxxxxx, a_buffer[675:13]};
					buffer_empty <= a_buffer[13*4 + 1] === 1'bx;
				end
		end
	else
		begin
			if (poly_load) begin
				a_buffer[111:0] <= {pol_64bit_in, a_buffer[111:64]};
				buffer_empty <= 0;
			end else if (poly_shift) begin
				a_buffer[111:0] <= {16'bxxxxxxxxxxxxxxxx, a_buffer[111:16]};
				buffer_empty <= a_buffer[16*4 + 1] === 1'bx;
				
			end
		end
end


always @(posedge clk)
begin
	if (rst || rst_buffer_counter)
		buffer_counter <= 4'd0;
	else if (bram_address_inc)
		buffer_counter <= buffer_counter + 4'd1;
	else
		buffer_counter <= buffer_counter;
end

assign buffer_counter_finish = pol_load_coeff4x ? (state == 4'd4) : buffer_counter == 4'd11 ? 1'b1 : 1'b0;


always @(posedge clk)
begin
	if (acc_clear)
		acc <= 3328'd0;
	else if (shift_secret)
		acc <= result;
	else if (read)
		acc <= {acc[51:0], acc[3327:52]};
end

assign coeff4x_out = pol_load_coeff4x ?
					  {6'd0, acc[48:39], 6'd0, acc[35:26], 6'd0, acc[22:13], 6'd0, acc[9:0]} :
					  {3'd0, acc[51:39], 3'd0, acc[38:26], 3'd0, acc[25:13], 3'd0, acc[12:0]};


always @(posedge clk)
begin
	if (rst)
		bram_address_relative <= 7'd0;
	else if (bram_address_inc && !buffer_counter_finish)
		bram_address_relative <= bram_address_relative + 7'd1;
	else
		bram_address_relative <= bram_address_relative;
end
		



always @(posedge clk)
begin
	if (rst)
		counter <= 9'd0;
	else if (shift_secret)
		counter <= counter + 9'd1;
	else
		counter <= counter;
end

assign counter_finish = counter == 9'd255;




always @(posedge clk)
begin
	if (rst)
		state <= 4'd0;
	else 
		state <= nextstate;
end

always @(state)
begin
	case(state)
		0: begin
				shift_secret<=1'b0; bram_address_inc<=1'b0; poly_load <= 0; poly_shift <= 0; rst_buffer_counter <= 0;
		   end
		1: begin
				shift_secret<=1'b0; bram_address_inc<=1'b0; poly_load <= 0; poly_shift <= 0; rst_buffer_counter <= 0;
		   end		
		2: begin
				shift_secret<=1'b0; bram_address_inc<=1'b1; poly_load <= 0; poly_shift <= 0; rst_buffer_counter <= 1;
		   end
		3: begin
				shift_secret<=1'b0; bram_address_inc<=1'b1; poly_load <= 1; poly_shift <= 0; rst_buffer_counter <= 1;
		   end
		4: begin
				shift_secret<=1'b1; bram_address_inc<=1'b1; poly_load <= 1; poly_shift <= 0; rst_buffer_counter <= 0;
		   end
		5: begin
				shift_secret<=1'b1; bram_address_inc<=1'b0; poly_load <= 0; poly_shift <= 1; rst_buffer_counter <= 0;
		   end
		6: begin
				shift_secret<=1'b1; bram_address_inc<=1'b1; poly_load <= 0; poly_shift <= 1; rst_buffer_counter <= 0;
		   end
		7: begin
				shift_secret<=1'b1; bram_address_inc<=1'b1; poly_load <= 1; poly_shift <= 0; rst_buffer_counter <= 1;
		   end	
		8: begin
				shift_secret<=1'b0; bram_address_inc<=1'b0; poly_load <= 0; poly_shift <= 0; rst_buffer_counter <= 0;
		   end			
		default: begin
				shift_secret<=1'b0; bram_address_inc<=1'b0; poly_load <= 0; poly_shift <= 0; rst_buffer_counter <= 0;
		   end			
	endcase
end	

always @(state or counter_finish or s_load_done or buffer_counter_finish or buffer_empty)
begin
	case(state)
		0: nextstate <= 1;
		1: begin
				if (s_load_done)
					nextstate <= 2;
				else
					nextstate <= 1;
			  end
		2: nextstate <= 3;
		3: nextstate <= 4;
		4: begin
				if (buffer_counter_finish)
					nextstate <= 5;
				else
					nextstate <= 4;
			  end
		5: begin
				if (buffer_empty)
					nextstate <= 6;
				else
					nextstate <= 5;
			  end
		6: nextstate <= 7;
		7: begin	
				if (counter_finish)
					nextstate <= 8;
				else
					nextstate <= 4;
			  end
		8: nextstate <= 8;
		default: nextstate <= 0;
	endcase
end

wire pol_mul_done = (state == 4'd8) ? 1'b1 : 1'b0;



always @(posedge clk)
	begin
		if (pol_mul_done)
			begin
				$display("Input 16 bit: %b\n\n", pol_load_coeff4x);
				$display("Multiplication result: %b\n\n",acc);
			end
	end



	
endmodule
module poly_mul256_parallel_in1(clk, rst, acc_clear, pol_load_coeff4x,
								bram_address_relative, pol_64bit_in,  
								s_address, s_vec_64, 
								read, coeff4x_out, pol_mul_done);

								
input clk, rst;
input pol_load_coeff4x;
input acc_clear;
output reg [6:0] bram_address_relative;
input [63:0] pol_64bit_in;								
output [7:0] s_address;
input [63:0] s_vec_64;
input read;

output [63:0] coeff4x_out;
output pol_mul_done;

reg rst_s_load;
wire s_load, s_load_done;

reg poly_load;

reg shift_secret, acc_en, bram_address_inc;
reg [3:0] state, nextstate;
reg [8:0] counter;
wire counter_finish;
wire [12:0] a_coeff;

reg [675:0] a_buffer;
reg poly_shift, buffer_empty;

reg [3:0] buffer_counter;
reg rst_buffer_counter;
wire buffer_counter_finish;


reg [3327:0] acc;
wire [3327:0] result;
wire [63:0] bug;
reg [1023:0] secret;


always @(posedge clk)
begin
	if (s_load)
		secret <= {s_vec_64, secret[1023:64]};
	else if (shift_secret)
			secret <= {secret[1019:0], secret[1023:1020] ^ 4'b1000};
	else
	       secret <= secret;
end

assign bug = secret[1023:960];


poly_load_control_BRAM1 PLC(clk, rst, s_address, s_load, s_load_done);

buffer_muxer1 BUFFMUX(a_buffer[624 : 612], a_buffer[573 : 561], a_buffer[522 : 510],
					 a_buffer[471 : 459], a_buffer[420 : 408], a_buffer[369 : 357],
					 a_buffer[318 : 306], a_buffer[267 : 255], a_buffer[216 : 204],
					 a_buffer[165 : 153], a_buffer[114 : 102], a_buffer[63 : 51],
					 a_buffer[12 : 0], 
					 a_buffer[60 : 48],
					 buffer_counter, pol_load_coeff4x, a_coeff);





always @(posedge clk)
begin
	if (pol_load_coeff4x == 0)
		begin
			if (poly_load)
				begin
					a_buffer <= {pol_64bit_in, a_buffer[675:64]};
					buffer_empty <= 0;
				end
			else if (poly_shift)
				begin
					a_buffer <= {13'bxxxxxxxxxxxxx, a_buffer[675:13]};
					buffer_empty <= a_buffer[13*4 + 1] === 1'bx;
				end
		end
	else
		begin
			if (poly_load) begin
				a_buffer[111:0] <= {pol_64bit_in, a_buffer[111:64]};
				buffer_empty <= 0;
			end else if (poly_shift) begin
				a_buffer[111:0] <= {16'bxxxxxxxxxxxxxxxx, a_buffer[111:16]};
				buffer_empty <= a_buffer[16*4 + 1] === 1'bx;
				
			end
		end
end


always @(posedge clk)
begin
	if (rst || rst_buffer_counter)
		buffer_counter <= 4'd0;
	else if (bram_address_inc)
		buffer_counter <= buffer_counter + 4'd1;
	else
		buffer_counter <= buffer_counter;
end

assign buffer_counter_finish = pol_load_coeff4x ? (state == 4'd4) : buffer_counter == 4'd11 ? 1'b1 : 1'b0;


always @(posedge clk)
begin
	if (acc_clear)
		acc <= 3328'd0;
	else if (shift_secret)
		acc <= result;
	else if (read)
		acc <= {acc[51:0], acc[3327:52]};
end

assign coeff4x_out = pol_load_coeff4x ?
					  {6'd0, acc[48:39], 6'd0, acc[35:26], 6'd0, acc[22:13], 6'd0, acc[9:0]} :
					  {3'd0, acc[51:39], 3'd0, acc[38:26], 3'd0, acc[25:13], 3'd0, acc[12:0]};


always @(posedge clk)
begin
	if (rst)
		bram_address_relative <= 7'd0;
	else if (bram_address_inc && !buffer_counter_finish)
		bram_address_relative <= bram_address_relative + 7'd1;
	else
		bram_address_relative <= bram_address_relative;
end
		



always @(posedge clk)
begin
	if (rst)
		counter <= 9'd0;
	else if (shift_secret)
		counter <= counter + 9'd1;
	else
		counter <= counter;
end

assign counter_finish = counter == 9'd255;




always @(posedge clk)
begin
	if (rst)
		state <= 4'd0;
	else 
		state <= nextstate;
end

always @(state)
begin
	case(state)
		0: begin
				shift_secret<=1'b0; bram_address_inc<=1'b0; poly_load <= 0; poly_shift <= 0; rst_buffer_counter <= 0;
		   end
		1: begin
				shift_secret<=1'b0; bram_address_inc<=1'b0; poly_load <= 0; poly_shift <= 0; rst_buffer_counter <= 0;
		   end		
		2: begin
				shift_secret<=1'b0; bram_address_inc<=1'b1; poly_load <= 0; poly_shift <= 0; rst_buffer_counter <= 1;
		   end
		3: begin
				shift_secret<=1'b0; bram_address_inc<=1'b1; poly_load <= 1; poly_shift <= 0; rst_buffer_counter <= 1;
		   end
		4: begin
				shift_secret<=1'b1; bram_address_inc<=1'b1; poly_load <= 1; poly_shift <= 0; rst_buffer_counter <= 0;
		   end
		5: begin
				shift_secret<=1'b1; bram_address_inc<=1'b0; poly_load <= 0; poly_shift <= 1; rst_buffer_counter <= 0;
		   end
		6: begin
				shift_secret<=1'b1; bram_address_inc<=1'b1; poly_load <= 0; poly_shift <= 1; rst_buffer_counter <= 0;
		   end
		7: begin
				shift_secret<=1'b1; bram_address_inc<=1'b1; poly_load <= 1; poly_shift <= 0; rst_buffer_counter <= 1;
		   end	
		8: begin
				shift_secret<=1'b0; bram_address_inc<=1'b0; poly_load <= 0; poly_shift <= 0; rst_buffer_counter <= 0;
		   end			
		default: begin
				shift_secret<=1'b0; bram_address_inc<=1'b0; poly_load <= 0; poly_shift <= 0; rst_buffer_counter <= 0;
		   end			
	endcase
end	

always @(state or counter_finish or s_load_done or buffer_counter_finish or buffer_empty)
begin
	case(state)
		0: nextstate <= 1;
		1: begin
				if (s_load_done)
					nextstate <= 2;
				else
					nextstate <= 1;
			  end
		2: nextstate <= 3;
		3: nextstate <= 4;
		4: begin
				if (buffer_counter_finish)
					nextstate <= 5;
				else
					nextstate <= 4;
			  end
		5: begin
				if (buffer_empty)
					nextstate <= 6;
				else
					nextstate <= 5;
			  end
		6: nextstate <= 7;
		7: begin	
				if (counter_finish)
					nextstate <= 8;
				else
					nextstate <= 4;
			  end
		8: nextstate <= 8;
		default: nextstate <= 0;
	endcase
end

wire pol_mul_done = (state == 4'd8) ? 1'b1 : 1'b0;



always @(posedge clk)
	begin
		if (pol_mul_done)
			begin
				$display("Input 16 bit: %b\n\n", pol_load_coeff4x);
				$display("Multiplication result: %b\n\n",acc);
			end
	end



	
endmodule