data/full_repos/permissive/459277146/subtractor.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/459277146/subtractor.v:13: Signal definition not found, creating implicitly: \'dout_adder_temp\'\n                                                                       : ... Suggested alternative: \'dout_adder_temp_ff\'\n dout_adder_temp_ff <= dout_adder_temp;\n                       ^~~~~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/459277146/subtractor.v:8: Cannot find file containing module: \'adder\'\nadder add2((~din2),1,dout_adder_temp);\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/459277146,data/full_repos/permissive/459277146/adder\n             data/full_repos/permissive/459277146,data/full_repos/permissive/459277146/adder.v\n             data/full_repos/permissive/459277146,data/full_repos/permissive/459277146/adder.sv\n             adder\n             adder.v\n             adder.sv\n             obj_dir/adder\n             obj_dir/adder.v\n             obj_dir/adder.sv\n%Error: data/full_repos/permissive/459277146/subtractor.v:9: Cannot find file containing module: \'adder\'\nadder add3(din1,dout_adder_temp_ff,dout_subtractor);\n^~~~~\n%Warning-WIDTH: data/full_repos/permissive/459277146/subtractor.v:13: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'dout_adder_temp\' generates 1 bits.\n                                                                    : ... In instance subtractor\n dout_adder_temp_ff <= dout_adder_temp;\n                    ^~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module subtractor #(parameter DWIDTH = 8) (clk, din1, din2, dout_subtractor);
input clk;
input [DWIDTH-1:0] din1;
input [DWIDTH-1:0] din2;
output [DWIDTH-1:0] dout_subtractor;

reg [DWIDTH-1:0] dout_adder_temp_ff;
adder add2((~din2),1,dout_adder_temp);
adder add3(din1,dout_adder_temp_ff,dout_subtractor);

always @(posedge clk)
begin
	dout_adder_temp_ff <= dout_adder_temp;
end

endmodule
module subtractor #(parameter DWIDTH = 8) (clk, din1, din2, dout_subtractor);

input clk;
input [DWIDTH-1:0] din1;
input [DWIDTH-1:0] din2;
output [DWIDTH-1:0] dout_subtractor;

reg [DWIDTH-1:0] dout_adder_temp_ff;
adder add2((~din2),1,dout_adder_temp);
adder add3(din1,dout_adder_temp_ff,dout_subtractor);

always @(posedge clk)
begin
	dout_adder_temp_ff <= dout_adder_temp;
end

endmodule