data/full_repos/permissive/43858668/final_verilog/src/clib/c_mat_mult.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_mat_mult.v:35: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_constants.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_constants.v.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_constants.v.sv\n             c_constants.v\n             c_constants.v.v\n             c_constants.v.sv\n             obj_dir/c_constants.v\n             obj_dir/c_constants.v.v\n             obj_dir/c_constants.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_mat_mult.v:43: Define or directive not defined: \'`BINARY_OP_AND\'\n   parameter prod_op = `BINARY_OP_AND;\n                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_mat_mult.v:43: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter prod_op = `BINARY_OP_AND;\n                                     ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_mat_mult.v:46: Define or directive not defined: \'`BINARY_OP_XOR\'\n   parameter sum_op = `BINARY_OP_XOR;\n                      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_mat_mult.v:46: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter sum_op = `BINARY_OP_XOR;\n                                    ^\n%Error: Exiting due to 5 error(s)\n'
module c_mat_mult
  (input_a, input_b, result);
   
`include "c_constants.v"
   

   parameter dim1_width = 1;
   parameter dim2_width = 1;
   parameter dim3_width = 1;
   

   parameter prod_op = `BINARY_OP_AND;
   

   parameter sum_op = `BINARY_OP_XOR;
   

   input [0:dim1_width*dim2_width-1] input_a;
   

   input [0:dim2_width*dim3_width-1] input_b;
   
   output [0:dim1_width*dim3_width-1] result;
   wire [0:dim1_width*dim3_width-1] result;
   
   generate
      
      genvar 			    row;
      
      for(row = 0; row < dim1_width; row = row + 1)
	begin:rows
	   
	   genvar col;
	   
	   for(col = 0; col < dim3_width; col = col + 1)
	     begin:cols
		
		wire [0:dim2_width-1] products;
		
		genvar 		      idx;
		
		for(idx = 0; idx < dim2_width; idx = idx + 1)
		  begin:idxs
		     
		     c_binary_op
			  #(.num_ports(2),
			    .width(1),
			    .op(prod_op))
		     prod
			  (.data_in({input_a[row*dim2_width+idx], 
				     input_b[idx*dim3_width+col]}),
			   .data_out(products[idx]));
		     
		  end
		
		c_binary_op
		  #(.num_ports(dim2_width),
		    .width(1),
		    .op(sum_op))
		sum
		  (.data_in(products),
		   .data_out(result[row*dim3_width+col]));
		
	     end
	   
	end
      
   endgenerate
   
endmodule
module c_mat_mult
  (input_a, input_b, result);

   
`include "c_constants.v"
   

   parameter dim1_width = 1;
   parameter dim2_width = 1;
   parameter dim3_width = 1;
   

   parameter prod_op = `BINARY_OP_AND;
   

   parameter sum_op = `BINARY_OP_XOR;
   

   input [0:dim1_width*dim2_width-1] input_a;
   

   input [0:dim2_width*dim3_width-1] input_b;
   
   output [0:dim1_width*dim3_width-1] result;
   wire [0:dim1_width*dim3_width-1] result;
   
   generate
      
      genvar 			    row;
      
      for(row = 0; row < dim1_width; row = row + 1)
	begin:rows
	   
	   genvar col;
	   
	   for(col = 0; col < dim3_width; col = col + 1)
	     begin:cols
		
		wire [0:dim2_width-1] products;
		
		genvar 		      idx;
		
		for(idx = 0; idx < dim2_width; idx = idx + 1)
		  begin:idxs
		     
		     c_binary_op
			  #(.num_ports(2),
			    .width(1),
			    .op(prod_op))
		     prod
			  (.data_in({input_a[row*dim2_width+idx], 
				     input_b[idx*dim3_width+col]}),
			   .data_out(products[idx]));
		     
		  end
		
		c_binary_op
		  #(.num_ports(dim2_width),
		    .width(1),
		    .op(sum_op))
		sum
		  (.data_in(products),
		   .data_out(result[row*dim3_width+col]));
		
	     end
	   
	end
      
   endgenerate
   
endmodule