data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic/mux2-tb.v
1: b'%Error: data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic/mux2-tb.v:1: Cannot find include file: mux2.v\n`include "mux2.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic,data/full_repos/permissive/474294847/mux2.v\n             data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic,data/full_repos/permissive/474294847/mux2.v.v\n             data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic,data/full_repos/permissive/474294847/mux2.v.sv\n             mux2.v\n             mux2.v.v\n             mux2.v.sv\n             obj_dir/mux2.v\n             obj_dir/mux2.v.v\n             obj_dir/mux2.v.sv\n%Error: data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic/mux2-tb.v:17: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("./build/rtl-sim/vcd/mux2.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic/mux2-tb.v:18: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic/mux2-tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/474294847/rtl-tests/arithmetic-logic/mux2-tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module mux2_tb;

reg in1, in2, sel;
wire out;

mux2 dut
(
    in1, in2, sel, out
);
defparam dut.WIDTH = 1;


initial
begin
    $dumpfile("./build/rtl-sim/vcd/mux2.vcd");
    $dumpvars;
end

initial
begin
    in1 = 0;
    in2 = 1;
    sel = 0;
    #100;
    sel = 1;
    #100;
end

endmodule
module mux2_tb;


reg in1, in2, sel;
wire out;

mux2 dut
(
    in1, in2, sel, out
);
defparam dut.WIDTH = 1;


initial
begin
    $dumpfile("./build/rtl-sim/vcd/mux2.vcd");
    $dumpvars;
end

initial
begin
    in1 = 0;
    in2 = 1;
    sel = 0;
    #100;
    sel = 1;
    #100;
end

endmodule