data/full_repos/permissive/439731184/test_memory.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/439731184/test_memory.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #1 x = memory[i];\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_memory();

parameter WORD_SIZE = 6;
parameter MEM_SIZE = 10;


reg [WORD_SIZE-1:0] memory [0:MEM_SIZE-1];
integer unsigned i;
reg [WORD_SIZE-1:0] x;

initial begin


    $readmemh("memory.list", memory);
    

    for (i=0; i<MEM_SIZE; i=i+1) begin
        #1 x = memory[i];
        $display("%h", x);
    end
end

endmodule
module test_memory();


parameter WORD_SIZE = 6;
parameter MEM_SIZE = 10;


reg [WORD_SIZE-1:0] memory [0:MEM_SIZE-1];
integer unsigned i;
reg [WORD_SIZE-1:0] x;

initial begin


    $readmemh("memory.list", memory);
    

    for (i=0; i<MEM_SIZE; i=i+1) begin
        #1 x = memory[i];
        $display("%h", x);
    end
end

endmodule