data/full_repos/permissive/418752214/smart_run/impl/mem_icg_test/cpu_bht_mem_test_tb.v
1: b'%Error: data/full_repos/permissive/418752214/smart_run/impl/mem_icg_test/cpu_bht_mem_test_tb.v:73: syntax error, unexpected \'@\'\n           @(posedge temp_data_CLK)\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/418752214/smart_run/impl/mem_icg_test/cpu_bht_mem_test_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n           #20\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/418752214/smart_run/impl/mem_icg_test/cpu_bht_mem_test_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n           #0.1 temp_data_cen_internal  = 1\'b0; \n           ^\n%Error: data/full_repos/permissive/418752214/smart_run/impl/mem_icg_test/cpu_bht_mem_test_tb.v:81: syntax error, unexpected \'@\'\n               @(posedge temp_data_CLK)\n               ^\n%Error: data/full_repos/permissive/418752214/smart_run/impl/mem_icg_test/cpu_bht_mem_test_tb.v:89: syntax error, unexpected \'@\'\n           @(posedge temp_data_CLK)\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/418752214/smart_run/impl/mem_icg_test/cpu_bht_mem_test_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n           #0.1 temp_data_cen_internal  = 1\'b0; \n           ^\n%Error: data/full_repos/permissive/418752214/smart_run/impl/mem_icg_test/cpu_bht_mem_test_tb.v:94: syntax error, unexpected \'@\'\n               @(posedge temp_data_CLK)\n               ^\n%Error: data/full_repos/permissive/418752214/smart_run/impl/mem_icg_test/cpu_bht_mem_test_tb.v:98: syntax error, unexpected \'@\'\n               @(posedge temp_data_CLK)\n               ^\n%Error: data/full_repos/permissive/418752214/smart_run/impl/mem_icg_test/cpu_bht_mem_test_tb.v:111: syntax error, unexpected \'#\'\n           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1\'b0}};\n           ^\n%Error: data/full_repos/permissive/418752214/smart_run/impl/mem_icg_test/cpu_bht_mem_test_tb.v:116: syntax error, unexpected \'@\'\n               @(posedge temp_data_CLK)\n               ^\n%Error: data/full_repos/permissive/418752214/smart_run/impl/mem_icg_test/cpu_bht_mem_test_tb.v:139: syntax error, unexpected \'@\'\n                 @(posedge temp_data_CLK)\n                 ^\n%Error: data/full_repos/permissive/418752214/smart_run/impl/mem_icg_test/cpu_bht_mem_test_tb.v:168: syntax error, unexpected \'#\'\n           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1\'b0}};\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/418752214/smart_run/impl/mem_icg_test/cpu_bht_mem_test_tb.v:287: Unsupported: Ignoring delay on this delayed statement.\n#(10/2)  temp_forever_cpuclk = ~temp_forever_cpuclk;\n^\n%Error: Exiting due to 9 error(s), 4 warning(s)\n'
module cpu_bht_mem_test_tb(
bht_mem_passed
);
output bht_mem_passed;
reg    bht_mem_passed;



parameter LOCAL_DATA_ADDR_WIDTH = 10;




parameter LOCAL_DATA_DATA_WIDTH = 64;
parameter LOCAL_DATA_WE_WIDTH   = 64;






reg [ LOCAL_DATA_ADDR_WIDTH-1 : 0 ] temp_data_addr_internal;
reg [ LOCAL_DATA_DATA_WIDTH-1 : 0 ] temp_data_din_internal ;
reg [ LOCAL_DATA_WE_WIDTH  -1 : 0 ] temp_data_wen_internal ;
reg                                 temp_data_cen_internal ;
reg                                 temp_data_CLK          ;
wire [ LOCAL_DATA_DATA_WIDTH-1 : 0] temp_data_q_internal   ;
reg  [ LOCAL_DATA_DATA_WIDTH-1 : 0] golden_data      ;
reg  [ LOCAL_DATA_DATA_WIDTH-1 : 0] data_mask   ;
reg  [ LOCAL_DATA_DATA_WIDTH-1 : 0] data_mask_ff   ;


reg temp_forever_cpuclk      ;
reg temp_external_en         ;
reg temp_pad_yy_test_mode    ;
wire temp_xor_clk            ;


integer i;

initial 
begin
bht_mem_passed =1'b0;



           temp_data_CLK               = 1'b0; 
           temp_data_cen_internal      = 1'b0; 
           temp_data_wen_internal      = {LOCAL_DATA_WE_WIDTH{1'b1}};
           temp_data_addr_internal     = {LOCAL_DATA_ADDR_WIDTH{1'b0}};
           temp_data_din_internal      = {LOCAL_DATA_DATA_WIDTH{1'b0}};
           golden_data                 = {LOCAL_DATA_DATA_WIDTH{1'b0}};
           data_mask                   = {LOCAL_DATA_DATA_WIDTH{1'b0}};
           #20
           @(posedge temp_data_CLK)



           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b0}};
           #0.1 temp_data_cen_internal  = 1'b0; 
           for(i=1;i<10;i=i+1)
           begin
               @(posedge temp_data_CLK)
                temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
                temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
                golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
           end



           @(posedge temp_data_CLK)
           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b1}};
           #0.1 temp_data_cen_internal  = 1'b0; 
           for(i=1;i<10;i=i+1)
           begin
               @(posedge temp_data_CLK)
                temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
                temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
                golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
               @(posedge temp_data_CLK)
               #0.1   

               if(temp_data_q_internal !== golden_data)
               begin

                   $finish;
               end
           end




           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b0}};
           #0.1 temp_data_cen_internal  = 1'b1; 

           for(i=10;i<15;i=i+1)
           begin
               @(posedge temp_data_CLK)
                temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
                temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 2;
                golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 2;
               @(posedge temp_data_CLK)
               #0.1   

               if(temp_data_q_internal === golden_data)
               begin

                   $finish;
               end
           end






           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b0}};
           #0.1 temp_data_cen_internal   = 1'b0; 
          for(i=0;i<LOCAL_DATA_WE_WIDTH/2 ;i=i+1)
          begin
                 @(posedge temp_data_CLK)
                  temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} ;
                  temp_data_wen_internal  <= {{LOCAL_DATA_WE_WIDTH-2{1'b1}},2'b0} <<2*i ; 
                  temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b1}} ;
                  golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b1}} ;
                 @(posedge temp_data_CLK)
                 @(posedge temp_data_CLK)
                  #0.1 temp_data_wen_internal  <= {LOCAL_DATA_WE_WIDTH{1'b1}};
                       golden_data             <= temp_data_din_internal ;
                       data_mask_ff            <= data_mask;
                 @(posedge temp_data_CLK)
                  #0.1 

                 if(temp_data_q_internal !== (golden_data &(~data_mask_ff)) )
                 begin

                      $finish;
                 end
           end
            




           @(posedge temp_data_CLK)
           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b0}};
           #0.1 temp_data_cen_internal   = 1'b0; 
           for(i=10;i<15;i = i+1)
           begin
           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b0}};
           #0.1 temp_data_cen_internal   = 1'b0; 
               @(posedge temp_data_CLK)
                temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
                temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
                golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
               @(posedge temp_data_CLK)
               #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b1}};
                    golden_data             <= temp_data_din_internal ;
               @(posedge temp_data_CLK)
               #0.1   

               if(temp_data_q_internal !== golden_data)
               begin

                   $finish;
               end
           end






           @(posedge temp_data_CLK)
           #0.1 temp_data_cen_internal   = 1'b0; 
           @(posedge temp_data_CLK)
           temp_data_wen_internal  <= {LOCAL_DATA_WE_WIDTH{1'b0}};
           temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} ;
           temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hbb;
           golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hbb;
           @(posedge temp_data_CLK)
           temp_data_wen_internal  <= {LOCAL_DATA_WE_WIDTH{1'b0}};
           temp_data_addr_internal <= { {1{1'b1}},{LOCAL_DATA_ADDR_WIDTH-1{1'b0}} } ;
           temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'haa;
           golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'haa;


           @(posedge temp_data_CLK)
           temp_data_wen_internal  <= {LOCAL_DATA_WE_WIDTH{1'b1}};
           temp_data_addr_internal <= { {1{1'b1}},{LOCAL_DATA_ADDR_WIDTH-1{1'b0}} } ;
           temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hff;
           golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'haa;
           @(posedge temp_data_CLK)
           #0.1   
           if(temp_data_q_internal !== golden_data)
           begin

               $finish;
           end


           @(posedge temp_data_CLK)
           temp_data_wen_internal  <= {LOCAL_DATA_WE_WIDTH{1'b1}};
           temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} ;
           temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hff;
           golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hbb;
           @(posedge temp_data_CLK)
           #0.1   
           if(temp_data_q_internal !== golden_data)
           begin

               $finish;
           end



     
           @(posedge temp_data_CLK)
           #0.1 temp_data_cen_internal   = 1'b0; 
           @(posedge temp_data_CLK)
           temp_data_wen_internal  <= {LOCAL_DATA_WE_WIDTH{1'b0}};
           temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b1}} ;
           temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b1}} ;
           golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b1}} ;
           @(posedge temp_data_CLK)
           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b1}};
                golden_data             <= temp_data_din_internal ;
           @(posedge temp_data_CLK)
           #0.1   

           if(temp_data_q_internal !== golden_data)
           begin

               $finish;
           end









           $display("$$$$$$$$  bht  Congratuations PASS!!!!!!!!!                     $");   
           #10
             bht_mem_passed = 1'b1;

end












always 
#(`CLK_PERIOD/2)  temp_data_CLK = ~temp_data_CLK;




always 
#(`CLK_PERIOD/2)  temp_forever_cpuclk = ~temp_forever_cpuclk;

always @(posedge temp_data_CLK)
begin

 data_mask <= { {temp_data_wen_internal[63:0]} };
end 



ct_ifu_bht_pre_array  x_way0_smbist_wrap (
  .bht_pred_array_index        (  temp_data_addr_internal   ),
  .bht_pred_array_cen_b        (  temp_data_cen_internal    ),
  .forever_cpuclk              (  temp_data_CLK             ),
  .bht_pred_array_din          (  temp_data_din_internal    ),
  .bht_pre_data_out            (  temp_data_q_internal      ),
  .bht_pred_bwen               (  temp_data_wen_internal    ),
  .bht_pred_array_gwen         ( &temp_data_wen_internal    ),

  .pad_yy_icg_scan_en                 (   1'b0                     ),
  .cp0_ifu_icg_en          (  1'b0                      ),
  .cp0_yy_clk_en          (  1'b1                      ),
  .bht_pre_array_clk_en          (  1'b1                      )
);


endmodule
module cpu_bht_mem_test_tb(
bht_mem_passed
);

output bht_mem_passed;
reg    bht_mem_passed;



parameter LOCAL_DATA_ADDR_WIDTH = 10;




parameter LOCAL_DATA_DATA_WIDTH = 64;
parameter LOCAL_DATA_WE_WIDTH   = 64;






reg [ LOCAL_DATA_ADDR_WIDTH-1 : 0 ] temp_data_addr_internal;
reg [ LOCAL_DATA_DATA_WIDTH-1 : 0 ] temp_data_din_internal ;
reg [ LOCAL_DATA_WE_WIDTH  -1 : 0 ] temp_data_wen_internal ;
reg                                 temp_data_cen_internal ;
reg                                 temp_data_CLK          ;
wire [ LOCAL_DATA_DATA_WIDTH-1 : 0] temp_data_q_internal   ;
reg  [ LOCAL_DATA_DATA_WIDTH-1 : 0] golden_data      ;
reg  [ LOCAL_DATA_DATA_WIDTH-1 : 0] data_mask   ;
reg  [ LOCAL_DATA_DATA_WIDTH-1 : 0] data_mask_ff   ;


reg temp_forever_cpuclk      ;
reg temp_external_en         ;
reg temp_pad_yy_test_mode    ;
wire temp_xor_clk            ;


integer i;

initial 
begin
bht_mem_passed =1'b0;



           temp_data_CLK               = 1'b0; 
           temp_data_cen_internal      = 1'b0; 
           temp_data_wen_internal      = {LOCAL_DATA_WE_WIDTH{1'b1}};
           temp_data_addr_internal     = {LOCAL_DATA_ADDR_WIDTH{1'b0}};
           temp_data_din_internal      = {LOCAL_DATA_DATA_WIDTH{1'b0}};
           golden_data                 = {LOCAL_DATA_DATA_WIDTH{1'b0}};
           data_mask                   = {LOCAL_DATA_DATA_WIDTH{1'b0}};
           #20
           @(posedge temp_data_CLK)



           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b0}};
           #0.1 temp_data_cen_internal  = 1'b0; 
           for(i=1;i<10;i=i+1)
           begin
               @(posedge temp_data_CLK)
                temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
                temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
                golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
           end



           @(posedge temp_data_CLK)
           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b1}};
           #0.1 temp_data_cen_internal  = 1'b0; 
           for(i=1;i<10;i=i+1)
           begin
               @(posedge temp_data_CLK)
                temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
                temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
                golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
               @(posedge temp_data_CLK)
               #0.1   

               if(temp_data_q_internal !== golden_data)
               begin

                   $finish;
               end
           end




           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b0}};
           #0.1 temp_data_cen_internal  = 1'b1; 

           for(i=10;i<15;i=i+1)
           begin
               @(posedge temp_data_CLK)
                temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
                temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 2;
                golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 2;
               @(posedge temp_data_CLK)
               #0.1   

               if(temp_data_q_internal === golden_data)
               begin

                   $finish;
               end
           end






           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b0}};
           #0.1 temp_data_cen_internal   = 1'b0; 
          for(i=0;i<LOCAL_DATA_WE_WIDTH/2 ;i=i+1)
          begin
                 @(posedge temp_data_CLK)
                  temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} ;
                  temp_data_wen_internal  <= {{LOCAL_DATA_WE_WIDTH-2{1'b1}},2'b0} <<2*i ; 
                  temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b1}} ;
                  golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b1}} ;
                 @(posedge temp_data_CLK)
                 @(posedge temp_data_CLK)
                  #0.1 temp_data_wen_internal  <= {LOCAL_DATA_WE_WIDTH{1'b1}};
                       golden_data             <= temp_data_din_internal ;
                       data_mask_ff            <= data_mask;
                 @(posedge temp_data_CLK)
                  #0.1 

                 if(temp_data_q_internal !== (golden_data &(~data_mask_ff)) )
                 begin

                      $finish;
                 end
           end
            




           @(posedge temp_data_CLK)
           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b0}};
           #0.1 temp_data_cen_internal   = 1'b0; 
           for(i=10;i<15;i = i+1)
           begin
           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b0}};
           #0.1 temp_data_cen_internal   = 1'b0; 
               @(posedge temp_data_CLK)
                temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} + i;
                temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
                golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + i;
               @(posedge temp_data_CLK)
               #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b1}};
                    golden_data             <= temp_data_din_internal ;
               @(posedge temp_data_CLK)
               #0.1   

               if(temp_data_q_internal !== golden_data)
               begin

                   $finish;
               end
           end






           @(posedge temp_data_CLK)
           #0.1 temp_data_cen_internal   = 1'b0; 
           @(posedge temp_data_CLK)
           temp_data_wen_internal  <= {LOCAL_DATA_WE_WIDTH{1'b0}};
           temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} ;
           temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hbb;
           golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hbb;
           @(posedge temp_data_CLK)
           temp_data_wen_internal  <= {LOCAL_DATA_WE_WIDTH{1'b0}};
           temp_data_addr_internal <= { {1{1'b1}},{LOCAL_DATA_ADDR_WIDTH-1{1'b0}} } ;
           temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'haa;
           golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'haa;


           @(posedge temp_data_CLK)
           temp_data_wen_internal  <= {LOCAL_DATA_WE_WIDTH{1'b1}};
           temp_data_addr_internal <= { {1{1'b1}},{LOCAL_DATA_ADDR_WIDTH-1{1'b0}} } ;
           temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hff;
           golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'haa;
           @(posedge temp_data_CLK)
           #0.1   
           if(temp_data_q_internal !== golden_data)
           begin

               $finish;
           end


           @(posedge temp_data_CLK)
           temp_data_wen_internal  <= {LOCAL_DATA_WE_WIDTH{1'b1}};
           temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b0}} ;
           temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hff;
           golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b0}} + 8'hbb;
           @(posedge temp_data_CLK)
           #0.1   
           if(temp_data_q_internal !== golden_data)
           begin

               $finish;
           end



     
           @(posedge temp_data_CLK)
           #0.1 temp_data_cen_internal   = 1'b0; 
           @(posedge temp_data_CLK)
           temp_data_wen_internal  <= {LOCAL_DATA_WE_WIDTH{1'b0}};
           temp_data_addr_internal <= {LOCAL_DATA_ADDR_WIDTH{1'b1}} ;
           temp_data_din_internal  <= {LOCAL_DATA_DATA_WIDTH{1'b1}} ;
           golden_data             <= {LOCAL_DATA_DATA_WIDTH{1'b1}} ;
           @(posedge temp_data_CLK)
           #0.1 temp_data_wen_internal   = {LOCAL_DATA_WE_WIDTH{1'b1}};
                golden_data             <= temp_data_din_internal ;
           @(posedge temp_data_CLK)
           #0.1   

           if(temp_data_q_internal !== golden_data)
           begin

               $finish;
           end









           $display("$$$$$$$$  bht  Congratuations PASS!!!!!!!!!                     $");   
           #10
             bht_mem_passed = 1'b1;

end












always 
#(`CLK_PERIOD/2)  temp_data_CLK = ~temp_data_CLK;




always 
#(`CLK_PERIOD/2)  temp_forever_cpuclk = ~temp_forever_cpuclk;

always @(posedge temp_data_CLK)
begin

 data_mask <= { {temp_data_wen_internal[63:0]} };
end 



ct_ifu_bht_pre_array  x_way0_smbist_wrap (
  .bht_pred_array_index        (  temp_data_addr_internal   ),
  .bht_pred_array_cen_b        (  temp_data_cen_internal    ),
  .forever_cpuclk              (  temp_data_CLK             ),
  .bht_pred_array_din          (  temp_data_din_internal    ),
  .bht_pre_data_out            (  temp_data_q_internal      ),
  .bht_pred_bwen               (  temp_data_wen_internal    ),
  .bht_pred_array_gwen         ( &temp_data_wen_internal    ),

  .pad_yy_icg_scan_en                 (   1'b0                     ),
  .cp0_ifu_icg_en          (  1'b0                      ),
  .cp0_yy_clk_en          (  1'b1                      ),
  .bht_pre_array_clk_en          (  1'b1                      )
);


endmodule