data/full_repos/permissive/452183855/lab3/Lab3_BCD_OPG_structure.v
1: b"%Error: data/full_repos/permissive/452183855/lab3/Lab3_BCD_OPG_structure.v:15: Cannot find file containing module: 'D_ff_AR'\n    D_ff_AR M0(A, DA, clock, reset);\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/452183855/lab3,data/full_repos/permissive/452183855/D_ff_AR\n             data/full_repos/permissive/452183855/lab3,data/full_repos/permissive/452183855/D_ff_AR.v\n             data/full_repos/permissive/452183855/lab3,data/full_repos/permissive/452183855/D_ff_AR.sv\n             D_ff_AR\n             D_ff_AR.v\n             D_ff_AR.sv\n             obj_dir/D_ff_AR\n             obj_dir/D_ff_AR.v\n             obj_dir/D_ff_AR.sv\n%Error: data/full_repos/permissive/452183855/lab3/Lab3_BCD_OPG_structure.v:16: Cannot find file containing module: 'D_ff_AR'\n    D_ff_AR M1(B, DB, clock, reset);\n    ^~~~~~~\n%Error: data/full_repos/permissive/452183855/lab3/Lab3_BCD_OPG_structure.v:17: Cannot find file containing module: 'D_ff_AR'\n    D_ff_AR M2(C, DC, clock, reset);\n    ^~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module Lab3_BCD_OPG_structure (output z,
                               input x, clock, reset);


    wire DA, DB, DC;
    wire A, B, C;

    assign DA = ((~(A))&B)|(A&(~(B)))|((~(A))&C&x);
    assign DB = (A&(~(B)))|((~(B))&(~(C))&x)|((~(A))&B&C)|((~(A))&C&(~(x)));
    assign DC = ((~(B))&(~(x)))|((~(A))&(~(C))&(~(x)))|((~(A))&B&x);

    assign z = (A&B&(~(C))&(~(x)))|(A&C&x);

    D_ff_AR M0(A, DA, clock, reset);
    D_ff_AR M1(B, DB, clock, reset);
    D_ff_AR M2(C, DC, clock, reset);

endmodule
module Lab3_BCD_OPG_structure (output z,
                               input x, clock, reset);



    wire DA, DB, DC;
    wire A, B, C;

    assign DA = ((~(A))&B)|(A&(~(B)))|((~(A))&C&x);
    assign DB = (A&(~(B)))|((~(B))&(~(C))&x)|((~(A))&B&C)|((~(A))&C&(~(x)));
    assign DC = ((~(B))&(~(x)))|((~(A))&(~(C))&(~(x)))|((~(A))&B&x);

    assign z = (A&B&(~(C))&(~(x)))|(A&C&x);

    D_ff_AR M0(A, DA, clock, reset);
    D_ff_AR M1(B, DB, clock, reset);
    D_ff_AR M2(C, DC, clock, reset);

endmodule