data/full_repos/permissive/435890256/my_riscv/ram_32x32.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/435890256/my_riscv/ram_32x32.sv:47: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'31\'h0\' generates 31 bits.\n                                                                             : ... In instance ram32x32\n    o_rdata1 = 31\'b0;\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/435890256/my_riscv/ram_32x32.sv:48: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'31\'h0\' generates 31 bits.\n                                                                             : ... In instance ram32x32\n    o_rdata2 = 31\'b0;\n             ^\n%Error: Exiting due to 2 warning(s)\n'
module ram32x32 (
  input logic clk,
  input logic rst_n,
  input logic i_we,
  input logic [ 4:0] i_waddr,
  input logic [31:0] i_wdata,
  input logic [ 4:0] i_raddr1,
  input logic [ 4:0] i_raddr2,
  output logic [31:0] o_rdata1,
  output logic [31:0] o_rdata2
);


logic [31:0] data_ram_cell [0:31];





























always_comb begin
  if (~rst_n) begin
    data_ram_cell = '{default:'0};
    o_rdata1 = 31'b0;
    o_rdata2 = 31'b0;
  end else begin
    if (i_we) begin
      data_ram_cell[i_waddr] = i_wdata;
    end
    o_rdata1 = data_ram_cell[i_raddr1];
    o_rdata2 = data_ram_cell[i_raddr2];
  end
end

endmodule
module ram32x32 (
  input logic clk,
  input logic rst_n,
  input logic i_we,
  input logic [ 4:0] i_waddr,
  input logic [31:0] i_wdata,
  input logic [ 4:0] i_raddr1,
  input logic [ 4:0] i_raddr2,
  output logic [31:0] o_rdata1,
  output logic [31:0] o_rdata2
);



logic [31:0] data_ram_cell [0:31];





























always_comb begin
  if (~rst_n) begin
    data_ram_cell = '{default:'0};
    o_rdata1 = 31'b0;
    o_rdata2 = 31'b0;
  end else begin
    if (i_we) begin
      data_ram_cell[i_waddr] = i_wdata;
    end
    o_rdata1 = data_ram_cell[i_raddr1];
    o_rdata2 = data_ram_cell[i_raddr2];
  end
end

endmodule