data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_dtlhstl_rcv.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_dtlhstl_rcv.v:31: syntax error, unexpected ',', expecting '['\n  pad, ref, clk, pad_clk_en_l, cmsi_clk_en_l, cmsi_l, se_buf, vddo\n          ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_dtlhstl_rcv.v:51: syntax error, unexpected always\n  always @(posedge clk) begin\n  ^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module bw_io_dtlhstl_rcv (

  out, so, 

  pad, ref, clk, pad_clk_en_l, cmsi_clk_en_l, cmsi_l, se_buf, vddo
  );

  input		pad;
  input 	ref;
  input		clk;
  input		pad_clk_en_l;
  input		cmsi_clk_en_l;
  input		cmsi_l;
  input		se_buf;
  input		vddo;

  output	out;
  output	so;


  assign so = out;
  wire net0281 = se_buf;

  reg out;
  always @(posedge clk) begin
    casex ({ pad_clk_en_l, pad, cmsi_clk_en_l, cmsi_l })
      4'b001x: out <= 1'b0;
      4'b011x: out <= 1'b1;
      4'b1x00: out <= 1'b1;
      4'b1x01: out <= 1'b0;
      default: out <= 1'bx;
      endcase
    end


  endmodule
module bw_io_dtlhstl_rcv (

  out, so, 

  pad, ref, clk, pad_clk_en_l, cmsi_clk_en_l, cmsi_l, se_buf, vddo
  );


  input		pad;
  input 	ref;
  input		clk;
  input		pad_clk_en_l;
  input		cmsi_clk_en_l;
  input		cmsi_l;
  input		se_buf;
  input		vddo;

  output	out;
  output	so;


  assign so = out;
  wire net0281 = se_buf;

  reg out;
  always @(posedge clk) begin
    casex ({ pad_clk_en_l, pad, cmsi_clk_en_l, cmsi_l })
      4'b001x: out <= 1'b0;
      4'b011x: out <= 1'b1;
      4'b1x00: out <= 1'b1;
      4'b1x01: out <= 1'b0;
      default: out <= 1'bx;
      endcase
    end


  endmodule