data/full_repos/permissive/426864978/lab2/task3/tb_syn_task3.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_task3.sv:18: Unsupported: Ignoring delay on this delayed statement.\n        forever #5 CLOCK_50 = ~CLOCK_50;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_task3.sv:55: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_task3.sv:60: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_task3.sv:65: Unsupported: Ignoring delay on this delayed statement.\n        #10; cycle_count = cycle_count + 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_task3.sv:71: Unsupported: Ignoring delay on this delayed statement.\n                #10; cycle_count = cycle_count + 1;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_task3.sv:77: Unsupported: Ignoring delay on this delayed statement.\n        #10; cycle_count = cycle_count + 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_task3.sv:81: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_task3.sv:86: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_task3.sv:91: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_task3.sv:96: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_task3.sv:101: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_task3.sv:106: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_task3.sv:111: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_task3.sv:116: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/426864978/lab2/task3/tb_syn_task3.sv:121: Unsupported: wait statements\n        wait (tb_syn_task3.dut.VGA_X == 8\'d108 && tb_syn_task3.dut.VGA_Y == 7\'d31);\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task3/tb_syn_task3.sv:126: Unsupported: Ignoring delay on this delayed statement.\n        #20;  \n        ^\n%Error: Exiting due to 1 error(s), 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_syn_task3();


    logic CLOCK_50, VGA_HS, VGA_VS, VGA_CLK, VGA_PLOT, err;
    logic [3:0] KEY;
    logic [9:0] SW, LEDR;
    logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, VGA_Y;
    logic [7:0] VGA_R, VGA_G, VGA_B, VGA_X;
    logic [2:0] VGA_COLOUR;
    integer i, j, cycle_count;

    task3 dut(.*);

    initial begin
        CLOCK_50 = 0;
        forever #5 CLOCK_50 = ~CLOCK_50;
    end

    task validator;
        input [7:0] exp_x;
        input [6:0] exp_y;
        input [2:0] exp_colour;
        input exp_plot;
        begin
            if (tb_syn_task3.dut.VGA_X !== exp_x) begin
                $display("ERROR A: Expected VGA_X is %d, actual VGA_X is %d at x =%d, y =%d", exp_x, tb_syn_task3.dut.VGA_X, i, j);
                err = 1'b1;
            end
            if (tb_syn_task3.dut.VGA_Y !== exp_y) begin
                $display("ERROR B: Expected VGA_Y is %d, actual VGA_Y is %d at x =%d, y =%d", exp_y, tb_syn_task3.dut.VGA_Y, i, j);
                err = 1'b1;
            end
            if (tb_syn_task3.dut.VGA_COLOUR !== exp_colour) begin
                $display("ERROR C: Expected VGA_COLOUR is %d, actual VGA_COLOUR is %d at x =%d, y =%d", exp_colour, tb_syn_task3.dut.VGA_COLOUR, i, j);
                err = 1'b1;
            end
            if (tb_syn_task3.dut.VGA_PLOT !== exp_plot) begin
                $display("ERROR D: Expected VGA_PLOT is %b, actual VGA_PLOT is %b at x =%d, y =%d", exp_plot, tb_syn_task3.dut.VGA_PLOT, i, j);
                err = 1'b1;
            end
        end
    endtask

    `define BLACK    3'b000
    `define GREEN    3'b010

    initial begin
        err = 1'b0;
        cycle_count = 0;


        KEY[3] = 1'bx;
        #10;
        validator(8'b0, 7'b0, 3'b0, 1'b0);


        KEY[3] = 1'b0;
        #10;
        validator(8'b0, 7'b0, 3'b0, 1'b0);


        KEY[3] = 1'b1;
        #10; cycle_count = cycle_count + 1;
        validator(8'b0, 7'b0, 3'b0, 1'b1);

        for (i = 0; i < 160; i = i + 1) begin
            for (j = 0; j < 120; j = j + 1) begin
                validator(i, j, `BLACK, 1'b1);
                #10; cycle_count = cycle_count + 1;
            end
        end



        #10; cycle_count = cycle_count + 1;
        validator(8'd0, 7'd0, `GREEN, 1'b0);


        #10;
        $display("CASE 5");
        validator(8'd120, 7'd60, `GREEN, 1'b1);


        #10;
        $display("CASE 6");
        validator(8'd80, 7'd100, `GREEN, 1'b1);


        #10;
        $display("CASE 7");
        validator(8'd40, 7'd60, `GREEN, 1'b1);


        #10;
        $display("CASE 8");
        validator(8'd80, 7'd100, `GREEN, 1'b1);


        #10;
        $display("CASE 9");
        validator(8'd40, 7'd60, `GREEN, 1'b1);


        #10;
        $display("CASE 10");
        validator(8'd80, 7'd20, `GREEN, 1'b1);


        #10;
        $display("CASE 11");
        validator(8'd120, 7'd60, `GREEN, 1'b1);


        #10;
        $display("CASE 12");
        validator(8'd80, 7'd20, `GREEN, 1'b1);


        wait (tb_syn_task3.dut.VGA_X == 8'd108 && tb_syn_task3.dut.VGA_Y == 7'd31);
        $display("CASE 13");
        validator(8'd108, 7'd31, `GREEN, 1'b1);


        #20;
        $display("CASE 14");
        validator(8'd108, 7'd31, `GREEN, 1'b0);

        $display("TOTAL NO OF CYCLES: %d", cycle_count);

        if (~err) begin
            $display("SUCCESS: All tests passed.");
        end
        $stop;
    end

endmodule
module tb_syn_task3();



    logic CLOCK_50, VGA_HS, VGA_VS, VGA_CLK, VGA_PLOT, err;
    logic [3:0] KEY;
    logic [9:0] SW, LEDR;
    logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, VGA_Y;
    logic [7:0] VGA_R, VGA_G, VGA_B, VGA_X;
    logic [2:0] VGA_COLOUR;
    integer i, j, cycle_count;

    task3 dut(.*);

    initial begin
        CLOCK_50 = 0;
        forever #5 CLOCK_50 = ~CLOCK_50;
    end

    task validator;
        input [7:0] exp_x;
        input [6:0] exp_y;
        input [2:0] exp_colour;
        input exp_plot;
        begin
            if (tb_syn_task3.dut.VGA_X !== exp_x) begin
                $display("ERROR A: Expected VGA_X is %d, actual VGA_X is %d at x =%d, y =%d", exp_x, tb_syn_task3.dut.VGA_X, i, j);
                err = 1'b1;
            end
            if (tb_syn_task3.dut.VGA_Y !== exp_y) begin
                $display("ERROR B: Expected VGA_Y is %d, actual VGA_Y is %d at x =%d, y =%d", exp_y, tb_syn_task3.dut.VGA_Y, i, j);
                err = 1'b1;
            end
            if (tb_syn_task3.dut.VGA_COLOUR !== exp_colour) begin
                $display("ERROR C: Expected VGA_COLOUR is %d, actual VGA_COLOUR is %d at x =%d, y =%d", exp_colour, tb_syn_task3.dut.VGA_COLOUR, i, j);
                err = 1'b1;
            end
            if (tb_syn_task3.dut.VGA_PLOT !== exp_plot) begin
                $display("ERROR D: Expected VGA_PLOT is %b, actual VGA_PLOT is %b at x =%d, y =%d", exp_plot, tb_syn_task3.dut.VGA_PLOT, i, j);
                err = 1'b1;
            end
        end
    endtask

    `define BLACK    3'b000
    `define GREEN    3'b010

    initial begin
        err = 1'b0;
        cycle_count = 0;


        KEY[3] = 1'bx;
        #10;
        validator(8'b0, 7'b0, 3'b0, 1'b0);


        KEY[3] = 1'b0;
        #10;
        validator(8'b0, 7'b0, 3'b0, 1'b0);


        KEY[3] = 1'b1;
        #10; cycle_count = cycle_count + 1;
        validator(8'b0, 7'b0, 3'b0, 1'b1);

        for (i = 0; i < 160; i = i + 1) begin
            for (j = 0; j < 120; j = j + 1) begin
                validator(i, j, `BLACK, 1'b1);
                #10; cycle_count = cycle_count + 1;
            end
        end



        #10; cycle_count = cycle_count + 1;
        validator(8'd0, 7'd0, `GREEN, 1'b0);


        #10;
        $display("CASE 5");
        validator(8'd120, 7'd60, `GREEN, 1'b1);


        #10;
        $display("CASE 6");
        validator(8'd80, 7'd100, `GREEN, 1'b1);


        #10;
        $display("CASE 7");
        validator(8'd40, 7'd60, `GREEN, 1'b1);


        #10;
        $display("CASE 8");
        validator(8'd80, 7'd100, `GREEN, 1'b1);


        #10;
        $display("CASE 9");
        validator(8'd40, 7'd60, `GREEN, 1'b1);


        #10;
        $display("CASE 10");
        validator(8'd80, 7'd20, `GREEN, 1'b1);


        #10;
        $display("CASE 11");
        validator(8'd120, 7'd60, `GREEN, 1'b1);


        #10;
        $display("CASE 12");
        validator(8'd80, 7'd20, `GREEN, 1'b1);


        wait (tb_syn_task3.dut.VGA_X == 8'd108 && tb_syn_task3.dut.VGA_Y == 7'd31);
        $display("CASE 13");
        validator(8'd108, 7'd31, `GREEN, 1'b1);


        #20;
        $display("CASE 14");
        validator(8'd108, 7'd31, `GREEN, 1'b0);

        $display("TOTAL NO OF CYCLES: %d", cycle_count);

        if (~err) begin
            $display("SUCCESS: All tests passed.");
        end
        $stop;
    end

endmodule