data/full_repos/permissive/433640910/SynchronousCounter/synchcounter.v
data/verilator_xmls/7c55c7bf-0daf-49e2-8548-0577ea34707d.xml
module tff(T, Clock, Clear_b, Q);
	input T, Clock, Clear_b;
	output reg Q;
	
	always @(posedge Clock, negedge Clear_b)
		begin
			if(Clear_b == 0)
				Q <=0;
			else
				begin
					if(T == 0)
						Q <= Q;
					else
						Q <= ~Q;
				end
		end
endmodule
module tff(T, Clock, Clear_b, Q);

	input T, Clock, Clear_b;
	output reg Q;
	
	always @(posedge Clock, negedge Clear_b)
		begin
			if(Clear_b == 0)
				Q <=0;
			else
				begin
					if(T == 0)
						Q <= Q;
					else
						Q <= ~Q;
				end
		end
endmodule