data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_output.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_output.v:36: Cannot find include file: c_functions.v\n`include "c_functions.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v.v\n             data/full_repos/permissive/43858668/final_verilog/src,data/full_repos/permissive/43858668/c_functions.v.sv\n             c_functions.v\n             c_functions.v.v\n             c_functions.v.sv\n             obj_dir/c_functions.v\n             obj_dir/c_functions.v.v\n             obj_dir/c_functions.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_output.v:37: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_output.v:38: Cannot find include file: rtr_constants.v\n`include "rtr_constants.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_output.v:49: Define or directive not defined: \'`PACKET_FORMAT_EXPLICIT_LENGTH\'\n   parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;\n                             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_output.v:49: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;\n                                                           ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_output.v:57: Define or directive not defined: \'`RESET_TYPE_ASYNC\'\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_output.v:57: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                                           ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_output.v:72: Define or directive not defined: \'`PACKET_FORMAT_HEAD_TAIL\'\n     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_output.v:72: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? \n                                                 ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_output.v:74: Define or directive not defined: \'`PACKET_FORMAT_TAIL_ONLY\'\n       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_output.v:76: Define or directive not defined: \'`PACKET_FORMAT_EXPLICIT_LENGTH\'\n       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? \n                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_output.v:154: Define or directive not defined: \'`PACKET_FORMAT_HEAD_TAIL\'\n `PACKET_FORMAT_HEAD_TAIL, \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_output.v:154: syntax error, unexpected \',\', expecting endcase\n `PACKET_FORMAT_HEAD_TAIL, \n                         ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_output.v:155: Define or directive not defined: \'`PACKET_FORMAT_TAIL_ONLY\'\n `PACKET_FORMAT_TAIL_ONLY, \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_output.v:156: Define or directive not defined: \'`PACKET_FORMAT_EXPLICIT_LENGTH\'\n `PACKET_FORMAT_EXPLICIT_LENGTH:\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_output.v:226: Define or directive not defined: \'`PACKET_FORMAT_HEAD_TAIL\'\n        `PACKET_FORMAT_HEAD_TAIL:\n        ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_output.v:226: syntax error, unexpected \':\', expecting endcase\n        `PACKET_FORMAT_HEAD_TAIL:\n                                ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_output.v:232: syntax error, unexpected end\n   end\n   ^~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_output.v:234: Define or directive not defined: \'`PACKET_FORMAT_TAIL_ONLY\'\n        `PACKET_FORMAT_TAIL_ONLY:\n        ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/rtr_channel_output.v:241: Define or directive not defined: \'`PACKET_FORMAT_EXPLICIT_LENGTH\'\n        `PACKET_FORMAT_EXPLICIT_LENGTH:\n        ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Cannot continue\n'
module rtr_channel_output
  (clk, reset, active, flit_valid_in, flit_head_in, flit_tail_in, flit_data_in, 
   flit_sel_in_ovc, channel_out);
   
`include "c_functions.v"
`include "c_constants.v"
`include "rtr_constants.v"
   
   



   

   parameter num_vcs = 4;
   

   parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;
   

   parameter enable_link_pm = 1;
   

   parameter flit_data_width = 64;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   



   

   localparam vc_idx_width = clogb(num_vcs);
   

   localparam link_ctrl_width = enable_link_pm ? 1 : 0;
   

   localparam flit_ctrl_width
     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? 
       (1 + vc_idx_width + 1 + 1) : 
       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? 
       (1 + vc_idx_width + 1) : 
       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? 
       (1 + vc_idx_width + 1) : 
       -1;
   

   localparam channel_width
     = link_ctrl_width + flit_ctrl_width + flit_data_width;
   
   



   
   input clk;
   input reset;
   input active;
   

   input flit_valid_in;
   

   input flit_head_in;
   

   input flit_tail_in;
   

   input [0:flit_data_width-1] flit_data_in;
   

   input [0:num_vcs-1] 	       flit_sel_in_ovc;
   

   output [0:channel_width-1]  channel_out;
   wire [0:channel_width-1]    channel_out;
   
   



   
   wire 		       flit_valid_out;
   
   generate
      
      if(enable_link_pm)
	assign channel_out[0] = active | flit_valid_out;
      
   endgenerate
   
   wire [0:flit_ctrl_width-1]  flit_ctrl_out;
   wire [0:flit_data_width-1]  flit_data_out;
   
   assign channel_out[link_ctrl_width:
		      link_ctrl_width+flit_ctrl_width-1]
     = flit_ctrl_out;
   assign channel_out[link_ctrl_width+flit_ctrl_width:
		      link_ctrl_width+flit_ctrl_width+flit_data_width-1]
     = flit_data_out;
   
   wire [0:flit_data_width-1]  flit_data_s, flit_data_q;
   assign flit_data_s = flit_data_in;
   c_dff
     #(.width(flit_data_width),
       .reset_type(reset_type))
   flit_dataq
     (.clk(clk),
      .reset(1'b0),
      .active(active),
      .d(flit_data_s),
      .q(flit_data_q));
   
   assign flit_data_out = flit_data_q;
   
   generate
      
      case(packet_format)
	
	`PACKET_FORMAT_HEAD_TAIL, 
	`PACKET_FORMAT_TAIL_ONLY, 
	`PACKET_FORMAT_EXPLICIT_LENGTH:
	  begin
	     
	     wire [0:flit_ctrl_width-1] flit_ctrl_s, flit_ctrl_q;
	     
	     assign flit_ctrl_s[0] = flit_valid_in;
	     













	     
	     wire 			flit_valid_active;
	     assign flit_valid_active = active | flit_valid_out;
	     
	     wire 			flit_valid_s, flit_valid_q;
	     assign flit_valid_s = flit_ctrl_s[0];
	     c_dff
	       #(.width(1),
		 .reset_type(reset_type))
	     flit_validq
	       (.clk(clk),
		.reset(reset),
		.active(flit_valid_active),
		.d(flit_valid_s),
		.q(flit_valid_q));
	     
	     assign flit_valid_out = flit_valid_q;
	     assign flit_ctrl_q[0] = flit_valid_q;
	     
	     if(flit_ctrl_width > 1)
	       begin
		  
		  c_dff
		    #(.width(flit_ctrl_width - 1),
		      .reset_type(reset_type))
		  flit_ctrlq
		    (.clk(clk),
		     .reset(1'b0),
		     .active(active),
		     .d(flit_ctrl_s[1:flit_ctrl_width-1]),
		     .q(flit_ctrl_q[1:flit_ctrl_width-1]));
		  
	       end
	     
	     if(num_vcs > 1)
	       begin
		  
		  wire [0:vc_idx_width-1] flit_vc;
		  c_encode
		    #(.num_ports(num_vcs))
		  flit_vc_enc
		    (.data_in(flit_sel_in_ovc),
		     .data_out(flit_vc));
		  
		  assign flit_ctrl_s[1:1+vc_idx_width-1] = flit_vc;
		  
	       end

	     case(packet_format)
	       
	       `PACKET_FORMAT_HEAD_TAIL:
		 begin
		    
		    assign flit_ctrl_s[1+vc_idx_width+0] = flit_head_in;
		    assign flit_ctrl_s[1+vc_idx_width+1] = flit_tail_in;
		    
		 end
	       
	       `PACKET_FORMAT_TAIL_ONLY:
		 begin
		    
		    assign flit_ctrl_s[1+vc_idx_width+0] = flit_tail_in;
		    
		 end
	       
	       `PACKET_FORMAT_EXPLICIT_LENGTH:
		 begin
		    
		    assign flit_ctrl_s[1+vc_idx_width+0] = flit_head_in;
		    
		 end
	       
	     endcase
	     
	     assign flit_ctrl_out = flit_ctrl_q;
	     
	  end
	
      endcase
      
   endgenerate
   
endmodule
module rtr_channel_output
  (clk, reset, active, flit_valid_in, flit_head_in, flit_tail_in, flit_data_in, 
   flit_sel_in_ovc, channel_out);

   
`include "c_functions.v"
`include "c_constants.v"
`include "rtr_constants.v"
   
   



   

   parameter num_vcs = 4;
   

   parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;
   

   parameter enable_link_pm = 1;
   

   parameter flit_data_width = 64;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   



   

   localparam vc_idx_width = clogb(num_vcs);
   

   localparam link_ctrl_width = enable_link_pm ? 1 : 0;
   

   localparam flit_ctrl_width
     = (packet_format == `PACKET_FORMAT_HEAD_TAIL) ? 
       (1 + vc_idx_width + 1 + 1) : 
       (packet_format == `PACKET_FORMAT_TAIL_ONLY) ? 
       (1 + vc_idx_width + 1) : 
       (packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ? 
       (1 + vc_idx_width + 1) : 
       -1;
   

   localparam channel_width
     = link_ctrl_width + flit_ctrl_width + flit_data_width;
   
   



   
   input clk;
   input reset;
   input active;
   

   input flit_valid_in;
   

   input flit_head_in;
   

   input flit_tail_in;
   

   input [0:flit_data_width-1] flit_data_in;
   

   input [0:num_vcs-1] 	       flit_sel_in_ovc;
   

   output [0:channel_width-1]  channel_out;
   wire [0:channel_width-1]    channel_out;
   
   



   
   wire 		       flit_valid_out;
   
   generate
      
      if(enable_link_pm)
	assign channel_out[0] = active | flit_valid_out;
      
   endgenerate
   
   wire [0:flit_ctrl_width-1]  flit_ctrl_out;
   wire [0:flit_data_width-1]  flit_data_out;
   
   assign channel_out[link_ctrl_width:
		      link_ctrl_width+flit_ctrl_width-1]
     = flit_ctrl_out;
   assign channel_out[link_ctrl_width+flit_ctrl_width:
		      link_ctrl_width+flit_ctrl_width+flit_data_width-1]
     = flit_data_out;
   
   wire [0:flit_data_width-1]  flit_data_s, flit_data_q;
   assign flit_data_s = flit_data_in;
   c_dff
     #(.width(flit_data_width),
       .reset_type(reset_type))
   flit_dataq
     (.clk(clk),
      .reset(1'b0),
      .active(active),
      .d(flit_data_s),
      .q(flit_data_q));
   
   assign flit_data_out = flit_data_q;
   
   generate
      
      case(packet_format)
	
	`PACKET_FORMAT_HEAD_TAIL, 
	`PACKET_FORMAT_TAIL_ONLY, 
	`PACKET_FORMAT_EXPLICIT_LENGTH:
	  begin
	     
	     wire [0:flit_ctrl_width-1] flit_ctrl_s, flit_ctrl_q;
	     
	     assign flit_ctrl_s[0] = flit_valid_in;
	     













	     
	     wire 			flit_valid_active;
	     assign flit_valid_active = active | flit_valid_out;
	     
	     wire 			flit_valid_s, flit_valid_q;
	     assign flit_valid_s = flit_ctrl_s[0];
	     c_dff
	       #(.width(1),
		 .reset_type(reset_type))
	     flit_validq
	       (.clk(clk),
		.reset(reset),
		.active(flit_valid_active),
		.d(flit_valid_s),
		.q(flit_valid_q));
	     
	     assign flit_valid_out = flit_valid_q;
	     assign flit_ctrl_q[0] = flit_valid_q;
	     
	     if(flit_ctrl_width > 1)
	       begin
		  
		  c_dff
		    #(.width(flit_ctrl_width - 1),
		      .reset_type(reset_type))
		  flit_ctrlq
		    (.clk(clk),
		     .reset(1'b0),
		     .active(active),
		     .d(flit_ctrl_s[1:flit_ctrl_width-1]),
		     .q(flit_ctrl_q[1:flit_ctrl_width-1]));
		  
	       end
	     
	     if(num_vcs > 1)
	       begin
		  
		  wire [0:vc_idx_width-1] flit_vc;
		  c_encode
		    #(.num_ports(num_vcs))
		  flit_vc_enc
		    (.data_in(flit_sel_in_ovc),
		     .data_out(flit_vc));
		  
		  assign flit_ctrl_s[1:1+vc_idx_width-1] = flit_vc;
		  
	       end

	     case(packet_format)
	       
	       `PACKET_FORMAT_HEAD_TAIL:
		 begin
		    
		    assign flit_ctrl_s[1+vc_idx_width+0] = flit_head_in;
		    assign flit_ctrl_s[1+vc_idx_width+1] = flit_tail_in;
		    
		 end
	       
	       `PACKET_FORMAT_TAIL_ONLY:
		 begin
		    
		    assign flit_ctrl_s[1+vc_idx_width+0] = flit_tail_in;
		    
		 end
	       
	       `PACKET_FORMAT_EXPLICIT_LENGTH:
		 begin
		    
		    assign flit_ctrl_s[1+vc_idx_width+0] = flit_head_in;
		    
		 end
	       
	     endcase
	     
	     assign flit_ctrl_out = flit_ctrl_q;
	     
	  end
	
      endcase
      
   endgenerate
   
endmodule