data/full_repos/permissive/494235676/rtl/cordic_fpga.v
data/verilator_xmls/004c93c6-0f4a-4be6-b838-a42a05ab96a4.xml
module cordic #(
    parameter W = 7
) (
    input clk,
    input reset,
    input signed [W:0] x_in,
    input signed [W:0] y_in,
    output reg signed [W:0] r,
    output reg signed [W:0] phi,
    output reg signed [W:0] eps
);




endmodule
module cordic #(
    parameter W = 7
) (
    input clk,
    input reset,
    input signed [W:0] x_in,
    input signed [W:0] y_in,
    output reg signed [W:0] r,
    output reg signed [W:0] phi,
    output reg signed [W:0] eps
);





endmodule