data/full_repos/permissive/491135068/comparisonModule.v
data/verilator_xmls/d097ffbf-545b-4d86-91be-60553e5f6673.xml
module comparisonModule(
    input [31:0] compInput,
    output reg [31:0] compOut,
    input C, Z,
    input [1:0] setType
    );
    
    always@(C, Z, setType) begin
        case(setType)
            2'b00: begin
                if(!C && !Z)
                    compOut[0] = 1;
                else
                    compOut = 32'b0;
            end         






            2'b10: begin
                if(!C || Z)
                    compOut[0] = 1;
                else
                    compOut = 32'b0;
            end






            default: compOut = compInput;
        endcase
    end
endmodule
module comparisonModule(
    input [31:0] compInput,
    output reg [31:0] compOut,
    input C, Z,
    input [1:0] setType
    );

    
    always@(C, Z, setType) begin
        case(setType)
            2'b00: begin
                if(!C && !Z)
                    compOut[0] = 1;
                else
                    compOut = 32'b0;
            end         






            2'b10: begin
                if(!C || Z)
                    compOut[0] = 1;
                else
                    compOut = 32'b0;
            end






            default: compOut = compInput;
        endcase
    end
endmodule