data/full_repos/permissive/433640910/RateDivider/500hertzdivider.v
data/verilator_xmls/b39f86ae-6406-42e9-ab5c-066d899b9777.xml
module part2(ClockIn, Reset, Speed, CounterValue);
	input ClockIn, Reset;
	input [1:0] Speed;
	output [3:0] CounterValue;
	
	wire Enable;
	wire [10:0] RateDividerCounter;		
	
	RateDivider u0(Speed, ClockIn, Reset, RateDividerCounter);

	assign Enable = (RateDividerCounter == 11'b00000000000) ? 1 : 0;
	
	counter c1 (ClockIn, ~Reset, Enable, CounterValue);
	
endmodule
module part2(ClockIn, Reset, Speed, CounterValue);

	input ClockIn, Reset;
	input [1:0] Speed;
	output [3:0] CounterValue;
	
	wire Enable;
	wire [10:0] RateDividerCounter;		
	
	RateDivider u0(Speed, ClockIn, Reset, RateDividerCounter);

	assign Enable = (RateDividerCounter == 11'b00000000000) ? 1 : 0;
	
	counter c1 (ClockIn, ~Reset, Enable, CounterValue);
	
endmodule