data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Finite State Machines/Lemmings2/top_module_tb.v
1: b'%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines/Lemmings2,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/Lemmings2/top_module_tb.v\n%Error: Exiting due to 5 error(s)\n'
module top_module_tb ();
  wire walk_left;
  wire walk_right;
  wire aaah;

  reg clk = 1'd1;
  reg areset = 1'd0;
  reg bump_left = 1'd0;
  reg bump_right = 1'd0;
  reg ground = 1'd1;

  localparam ITERATIONS = 1000;

  always begin
    #5 clk = clk + 1;
  end

  always begin
    #10 bump_left = 1'b1;
    #10 bump_left = 1'b0;
    #50;
    #10 bump_left = 1'b1;
    bump_right = 1'b1;
    #50 bump_left = 1'b0;
    bump_right = 1'b0;
    #50;
    #10 bump_right = 1'b1;
    #10 bump_right = 1'b0;
    #50;
  end

  always begin
    #125 ground = 1'b0;
    #125 ground = 1'b1;
  end

  initial begin
    #57 areset = 1'b1;
    #1 areset = 1'b0;
  end

  top_module uut (
      .clk(clk),
      .areset(areset),
      .bump_left(bump_left),
      .bump_right(bump_right),
      .ground(ground),
      .walk_left(walk_left),
      .walk_right(walk_right),
      .aaah(aaah)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule
module top_module_tb ();

  wire walk_left;
  wire walk_right;
  wire aaah;

  reg clk = 1'd1;
  reg areset = 1'd0;
  reg bump_left = 1'd0;
  reg bump_right = 1'd0;
  reg ground = 1'd1;

  localparam ITERATIONS = 1000;

  always begin
    #5 clk = clk + 1;
  end

  always begin
    #10 bump_left = 1'b1;
    #10 bump_left = 1'b0;
    #50;
    #10 bump_left = 1'b1;
    bump_right = 1'b1;
    #50 bump_left = 1'b0;
    bump_right = 1'b0;
    #50;
    #10 bump_right = 1'b1;
    #10 bump_right = 1'b0;
    #50;
  end

  always begin
    #125 ground = 1'b0;
    #125 ground = 1'b1;
  end

  initial begin
    #57 areset = 1'b1;
    #1 areset = 1'b0;
  end

  top_module uut (
      .clk(clk),
      .areset(areset),
      .bump_left(bump_left),
      .bump_right(bump_right),
      .ground(ground),
      .walk_left(walk_left),
      .walk_right(walk_right),
      .aaah(aaah)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule