data/full_repos/permissive/488093047/Verilog Codes/TB_Decoder8x3.v
1: b'%Error: Cannot find file containing module: Codes,data/full_repos/permissive/488093047\n        ... Looked in:\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.v\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.sv\n             Codes,data/full_repos/permissive/488093047\n             Codes,data/full_repos/permissive/488093047.v\n             Codes,data/full_repos/permissive/488093047.sv\n             obj_dir/Codes,data/full_repos/permissive/488093047\n             obj_dir/Codes,data/full_repos/permissive/488093047.v\n             obj_dir/Codes,data/full_repos/permissive/488093047.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/488093047/Verilog\n%Error: Cannot find file containing module: Codes/TB_Decoder8x3.v\n%Error: Exiting due to 3 error(s)\n'
module TB_Decoder8x3();
reg [2:0]S;
reg EN;
wire Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7;
Decoder8x3 DUT (.S(S),.EN(EN),.Y0(Y0),.Y1(Y1),.Y2(Y2),.Y3(Y3),.Y4(Y4),.Y5(Y5),.Y6(Y6),.Y7(Y7));
initial begin
EN=1'b0;S=3'b000;
#10 EN=1'b1;S=3'b000;
#10 EN=1'b1;S=3'b001;
#10 EN=1'b1;S=3'b010;
#10 EN=1'b1;S=3'b011;
#10 EN=1'b1;S=3'b100;
#10 EN=1'b1;S=3'b101;
#10 EN=1'b1;S=3'b110;
#10 EN=1'b1;S=3'b111;

end
endmodule
module TB_Decoder8x3();

reg [2:0]S;
reg EN;
wire Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7;
Decoder8x3 DUT (.S(S),.EN(EN),.Y0(Y0),.Y1(Y1),.Y2(Y2),.Y3(Y3),.Y4(Y4),.Y5(Y5),.Y6(Y6),.Y7(Y7));
initial begin
EN=1'b0;S=3'b000;
#10 EN=1'b1;S=3'b000;
#10 EN=1'b1;S=3'b001;
#10 EN=1'b1;S=3'b010;
#10 EN=1'b1;S=3'b011;
#10 EN=1'b1;S=3'b100;
#10 EN=1'b1;S=3'b101;
#10 EN=1'b1;S=3'b110;
#10 EN=1'b1;S=3'b111;

end
endmodule