data/full_repos/permissive/509809169/Verilog Language/Vectors/Four input gates.v
1: b'%Error: Cannot find file containing module: Language/Vectors,data/full_repos/permissive/509809169\n        ... Looked in:\n             data/full_repos/permissive/509809169/Verilog/Language/Vectors,data/full_repos/permissive/509809169\n             data/full_repos/permissive/509809169/Verilog/Language/Vectors,data/full_repos/permissive/509809169.v\n             data/full_repos/permissive/509809169/Verilog/Language/Vectors,data/full_repos/permissive/509809169.sv\n             Language/Vectors,data/full_repos/permissive/509809169\n             Language/Vectors,data/full_repos/permissive/509809169.v\n             Language/Vectors,data/full_repos/permissive/509809169.sv\n             obj_dir/Language/Vectors,data/full_repos/permissive/509809169\n             obj_dir/Language/Vectors,data/full_repos/permissive/509809169.v\n             obj_dir/Language/Vectors,data/full_repos/permissive/509809169.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/509809169/Verilog\n%Error: Cannot find file containing module: Language/Vectors/Four\n%Error: Cannot find file containing module: input\n%Error: Cannot find file containing module: gates.v\n%Error: Exiting due to 5 error(s)\n'
module top_module( 
    input [3:0] in,
    output out_and,
    output out_or,
    output out_xor
);
    assign out_and=in[3]&in[2]&in[1]&in[0];
    assign out_or=in[3]|in[2]|in[1]|in[0];
    assign out_xor=in[3]^in[2]^in[1]^in[0];

endmodule
module top_module( 
    input [3:0] in,
    output out_and,
    output out_or,
    output out_xor
);

    assign out_and=in[3]&in[2]&in[1]&in[0];
    assign out_or=in[3]|in[2]|in[1]|in[0];
    assign out_xor=in[3]^in[2]^in[1]^in[0];

endmodule