data/full_repos/permissive/449807379/CPU_design/test_RAM_write.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/test_RAM_write.v:12: Unsupported: Ignoring delay on this delayed statement.\n#5 enable =1;   ReadWrite=0; Address=16\'d0; D_In =16\'hAAAA;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/test_RAM_write.v:13: Unsupported: Ignoring delay on this delayed statement.\n#5 enable =1;   ReadWrite=0; Address=16\'d1; D_In =16\'h00AA;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/test_RAM_write.v:14: Unsupported: Ignoring delay on this delayed statement.\n#5 enable =1;   ReadWrite=0; Address=16\'d2; D_In =16\'h00BB;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/test_RAM_write.v:15: Unsupported: Ignoring delay on this delayed statement.\n#5 enable =1;   ReadWrite=0; Address=16\'d3; D_In =16\'h00CC;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/test_RAM_write.v:16: Unsupported: Ignoring delay on this delayed statement.\n#5 enable =1;   ReadWrite=0; Address=16\'d4; D_In =16\'h00DD;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/test_RAM_write.v:17: Unsupported: Ignoring delay on this delayed statement.\n#5 enable =1;   ReadWrite=0; Address=16\'d5; D_In =16\'h00EE;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/test_RAM_write.v:18: Unsupported: Ignoring delay on this delayed statement.\n#5 enable =1;   ReadWrite=0; Address=16\'d6; D_In =16\'h00FF;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/test_RAM_write.v:19: Unsupported: Ignoring delay on this delayed statement.\n#5 enable =1;   ReadWrite=0; Address=16\'d7; D_In =16\'hFFFF;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449807379/CPU_design/test_RAM_write.v:20: Unsupported: Ignoring delay on this delayed statement.\n#10\n^\n%Error: data/full_repos/permissive/449807379/CPU_design/test_RAM_write.v:22: Can\'t find definition of \'RAM\' in dotted variable: \'test_ram.RAM\'\n  $writememh("data_h.txt", test_ram.RAM);\n                                    ^~~\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_memory;
    reg  enable,ReadWrite;
    reg [31:0] D_In;
    reg [15:0] Address;
    wire [31:0] D_Out;

RAM test_ram(enable,ReadWrite,Address,D_In,D_Out); 

initial  
begin
   enable =0;   ReadWrite=0;	Address=16'd0;	D_In =16'hAAAA;
#5 enable =1;   ReadWrite=0;	Address=16'd0;	D_In =16'hAAAA;
#5 enable =1;   ReadWrite=0;	Address=16'd1;	D_In =16'h00AA;
#5 enable =1;   ReadWrite=0;	Address=16'd2;	D_In =16'h00BB;
#5 enable =1;   ReadWrite=0;	Address=16'd3;	D_In =16'h00CC;
#5 enable =1;   ReadWrite=0;	Address=16'd4;	D_In =16'h00DD;
#5 enable =1;   ReadWrite=0;	Address=16'd5;	D_In =16'h00EE;
#5 enable =1;   ReadWrite=0;	Address=16'd6;	D_In =16'h00FF;
#5 enable =1;   ReadWrite=0;	Address=16'd7;	D_In =16'hFFFF;
#10

  $writememh("data_h.txt", test_ram.RAM);
end
endmodule
module test_memory;

    reg  enable,ReadWrite;
    reg [31:0] D_In;
    reg [15:0] Address;
    wire [31:0] D_Out;

RAM test_ram(enable,ReadWrite,Address,D_In,D_Out); 

initial  
begin
   enable =0;   ReadWrite=0;	Address=16'd0;	D_In =16'hAAAA;
#5 enable =1;   ReadWrite=0;	Address=16'd0;	D_In =16'hAAAA;
#5 enable =1;   ReadWrite=0;	Address=16'd1;	D_In =16'h00AA;
#5 enable =1;   ReadWrite=0;	Address=16'd2;	D_In =16'h00BB;
#5 enable =1;   ReadWrite=0;	Address=16'd3;	D_In =16'h00CC;
#5 enable =1;   ReadWrite=0;	Address=16'd4;	D_In =16'h00DD;
#5 enable =1;   ReadWrite=0;	Address=16'd5;	D_In =16'h00EE;
#5 enable =1;   ReadWrite=0;	Address=16'd6;	D_In =16'h00FF;
#5 enable =1;   ReadWrite=0;	Address=16'd7;	D_In =16'hFFFF;
#10

  $writememh("data_h.txt", test_ram.RAM);
end
endmodule