data/full_repos/permissive/447976230/fpga/usrp2/fifo/packet32_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/fifo/packet32_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n   always #10 clk <= ~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/fifo/packet32_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n   initial #1000 reset <= 0;\n           ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/fifo/packet32_tb.v:32: Unsupported or unknown PLI call: $dumpfile\n   initial $dumpfile("packet32_tb.vcd");\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/fifo/packet32_tb.v:33: Unsupported or unknown PLI call: $dumpvars\n   initial $dumpvars(0,packet32_tb);\n           ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module packet32_tb();

   wire [35:0] data;
   wire       src_rdy, dst_rdy;

   wire       clear = 0;
   reg 	      clk = 0;
   reg 	      reset = 1;

   always #10 clk <= ~clk;
   initial #1000 reset <= 0;

   initial $dumpfile("packet32_tb.vcd");
   initial $dumpvars(0,packet32_tb);

   wire [31:0] total, crc_err, seq_err, len_err;
   
   packet_generator32 pkt_gen (.clk(clk), .reset(reset), .clear(clear),
			       .data_o(data), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy));

   packet_verifier32 pkt_ver (.clk(clk), .reset(reset), .clear(clear),
			      .data_i(data), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy),
			      .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));

endmodule
module packet32_tb();


   wire [35:0] data;
   wire       src_rdy, dst_rdy;

   wire       clear = 0;
   reg 	      clk = 0;
   reg 	      reset = 1;

   always #10 clk <= ~clk;
   initial #1000 reset <= 0;

   initial $dumpfile("packet32_tb.vcd");
   initial $dumpvars(0,packet32_tb);

   wire [31:0] total, crc_err, seq_err, len_err;
   
   packet_generator32 pkt_gen (.clk(clk), .reset(reset), .clear(clear),
			       .data_o(data), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy));

   packet_verifier32 pkt_ver (.clk(clk), .reset(reset), .clear(clear),
			      .data_i(data), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy),
			      .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));

endmodule