data/full_repos/permissive/509499516/alu.v
1: b"%Error: data/full_repos/permissive/509499516/alu.v:16: syntax error, unexpected reg, expecting ',' or ';'\nreg [31:0] lo\n^~~\n%Error: Cannot continue\n"
module alu(opA, opB, ALUop, result, zero);

input [31:0] opA;
input [31:0] opB;


input [4:0] ALUop;

output reg [31:0] result;
output zero;

assign zero = (result==0);


reg [31:0] hi
reg [31:0] lo

always @(ALUop, opA, opB) begin
	case(ALUop)

		5'b00000: result=opA&opB;
		5'b00010: result=opA|opB;
		5'b00110: result=opA^opB;
		5'b11000: result=~(opA|opB);
		5'b00100: result=opA+opB;
		5'b01100: result=opA-opB;


		5'b01000: assign {hi, lo}=opA*opB; 

		5'b01010: assign {hi, lo}=opA/opB;

		5'b10000: result=opA<<<1;
		5'b10010: result=opA>>>1;
		5'b10100: result=opA>>1;
		5'b10110: result=opA<<opB;
		5'b11001: result=opA>>opB;
		5'b11010: result=~(opA-opB);
		5'b11100: result=(opA-opB)<=0?1:0;
		5'b11110: result=(opA-opB)>0?1:0;

		5'b11111: result=  hi ;
		5'b00001: result= lo ;
		
		5'b00011: result=(opA<<16);
		5'b01110: result=opA<opB?1:0;

		default: result=32'bx

	endcase
end

endmodule
module alu(opA, opB, ALUop, result, zero);


input [31:0] opA;
input [31:0] opB;


input [4:0] ALUop;

output reg [31:0] result;
output zero;

assign zero = (result==0);


reg [31:0] hi
reg [31:0] lo

always @(ALUop, opA, opB) begin
	case(ALUop)

		5'b00000: result=opA&opB;
		5'b00010: result=opA|opB;
		5'b00110: result=opA^opB;
		5'b11000: result=~(opA|opB);
		5'b00100: result=opA+opB;
		5'b01100: result=opA-opB;


		5'b01000: assign {hi, lo}=opA*opB; 

		5'b01010: assign {hi, lo}=opA/opB;

		5'b10000: result=opA<<<1;
		5'b10010: result=opA>>>1;
		5'b10100: result=opA>>1;
		5'b10110: result=opA<<opB;
		5'b11001: result=opA>>opB;
		5'b11010: result=~(opA-opB);
		5'b11100: result=(opA-opB)<=0?1:0;
		5'b11110: result=(opA-opB)>0?1:0;

		5'b11111: result=  hi ;
		5'b00001: result= lo ;
		
		5'b00011: result=(opA<<16);
		5'b01110: result=opA<opB?1:0;

		default: result=32'bx

	endcase
end

endmodule