data/full_repos/permissive/494490807/bench/MCNC/add_64.v
data/verilator_xmls/80057f9e-643e-49bf-a776-27ffba6ccb01.xml
module addition(q, a, b);
output[N - 1:0] q;
input[N - 1:0] a, b;

assign q = a + b;

endmodule
module addition(q, a, b);

output[N - 1:0] q;
input[N - 1:0] a, b;

assign q = a + b;

endmodule