data/full_repos/permissive/521104862/rtl/Psychic5_cpuboard/Psychic5_obj.v
1: b'%Error: data/full_repos/permissive/521104862/rtl/Psychic5_cpuboard/Psychic5_obj.v:19: Cannot find include file: rtl/Psychic5_emu_header.v\n`include "rtl/Psychic5_emu_header.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/521104862/rtl/Psychic5_cpuboard,data/full_repos/permissive/521104862/rtl/Psychic5_emu_header.v\n             data/full_repos/permissive/521104862/rtl/Psychic5_cpuboard,data/full_repos/permissive/521104862/rtl/Psychic5_emu_header.v.v\n             data/full_repos/permissive/521104862/rtl/Psychic5_cpuboard,data/full_repos/permissive/521104862/rtl/Psychic5_emu_header.v.sv\n             rtl/Psychic5_emu_header.v\n             rtl/Psychic5_emu_header.v.v\n             rtl/Psychic5_emu_header.v.sv\n             obj_dir/rtl/Psychic5_emu_header.v\n             obj_dir/rtl/Psychic5_emu_header.v.v\n             obj_dir/rtl/Psychic5_emu_header.v.sv\n%Error: Exiting due to 1 error(s)\n'
module Psychic5_obj
(

    input   wire            i_EMU_MCLK,
    input   wire            i_EMU_CLK6MPCEN_n,

    input   wire            i_EMU_INITRST_n,


    output  reg             o_OBJDMA_BUSRQ_n = 1'b1,
    input   wire            i_OBJDMA_BUSACK_n,


    output  wire    [12:0]  o_OBJDMA_ADDR_BUS,
    input   wire    [7:0]   i_OBJDMA_DATA_READ_BUS,
    output  wire            o_OBJDMA_CTRL_RD_n,
    output  wire            o_OBJDMA_CTRL_WR_n,


    input   wire            i_FLIP,
    input   wire            i_OBJ_BUF_INIT_STOP_n,


    input   wire    [7:0]   i_FLIP_HV_BUS,
    input   wire            i_ABS_4H, i_ABS_2H, i_ABS_1H,

    input   wire            i_DFFD_7E_A_Q,
    input   wire            i_DFFD_7E_A_Q_PCEN_n,
    input   wire            i_DFFD_8E_B_Q,
    input   wire            i_DFFQ_8F_Q2_NCEN_n,
    input   wire            i_DFFQ_8F_Q1,


    input   wire            i_DFFQ_8F_Q1_DLYD_n,
    input   wire            i_DFFQ_8F_Q3_DLYD,
    input   wire            i_DFFQ_8F_Q2_DLYD,
    input   wire            i_DFFQ_8F_Q2_DLYD_n,

    output  wire    [7:0]   o_OBJ_PIXELOUT,


    output  wire    [16:0]  o_EMU_OBJROM_ADDR,
    input   wire    [7:0]   i_EMU_OBJROM_DATA,
    output  wire            o_EMU_OBJROM_RQ_n,


    input   wire    [16:0]  i_EMU_BRAM_ADDR,
    input   wire    [7:0]   i_EMU_BRAM_DATA,
    input   wire            i_EMU_BRAM_WR_n,

    input   wire            i_EMU_BRAM_SEQROM_CS_n
);











assign  o_OBJDMA_CTRL_RD_n = 1'b0;
assign  o_OBJDMA_CTRL_WR_n = 1'b1;




reg             objdma_start_n;
wire            objdma_complete;

always @(posedge i_EMU_MCLK)
begin
    if(!i_EMU_INITRST_n) 
    begin
        o_OBJDMA_BUSRQ_n <= 1'b1;
    end
    else 
    begin
        if(!i_EMU_CLK6MPCEN_n)
        begin
            if(i_ABS_1H == 1'b1)
            begin
                if(objdma_complete == 1'b1)
                begin
                    o_OBJDMA_BUSRQ_n <= 1'b1;
                    objdma_start_n <= 1'b1;
                end
                else
                begin
                    if(i_DFFQ_8F_Q2_NCEN_n == 1'b0) 
                    begin
                        o_OBJDMA_BUSRQ_n <= 1'b0;
                    end
                    else
                    begin
                        o_OBJDMA_BUSRQ_n <= o_OBJDMA_BUSRQ_n;
                    end

                    if(o_OBJDMA_BUSRQ_n == 1'b1) 
                    begin
                        objdma_start_n <= 1'b1;
                    end
                    else
                    begin
                        objdma_start_n <= i_OBJDMA_BUSACK_n;
                    end
                end
            end
            else
            begin
                if(i_DFFQ_8F_Q2_NCEN_n == 1'b0)
                begin
                    o_OBJDMA_BUSRQ_n <= 1'b0;
                end
                else
                begin
                    o_OBJDMA_BUSRQ_n <= o_OBJDMA_BUSRQ_n;
                end

                if(o_OBJDMA_BUSRQ_n == 1'b1) 
                begin
                    objdma_start_n <= 1'b1;
                end
                else
                begin
                    objdma_start_n <= objdma_start_n;
                end
            end
        end
    end
end








reg     [3:0]   objdma_attr_cntr = 4'b1011;
reg     [7:0]   objdma_objcode_cntr = 8'b1010_0000;


wire            objdma_attr_byte_f = &{objdma_attr_cntr};
wire            objdma_attr_byte_7_n = ~&{~objdma_attr_cntr[3], objdma_attr_cntr[2:0]};


wire            next_objcode;
wire            objcode_cntup = ((~objdma_attr_byte_7_n & next_objcode) | objdma_attr_byte_f);
wire            objcode_rst_n = ~objdma_start_n | i_DFFD_8E_B_Q;
assign  objdma_complete = &{objdma_objcode_cntr, objcode_cntup};


wire    [9:0]   objtable_ram_addr = {objdma_objcode_cntr[6:0], objdma_attr_cntr[2:0]};
wire            objtable_ram_rd = ~i_OBJDMA_BUSACK_n;
wire            objtable_ram_wr = objdma_start_n | ~i_ABS_1H;


assign  o_OBJDMA_ADDR_BUS = {2'b10, objdma_objcode_cntr[6:0], objdma_attr_cntr[3:0]};

always @(posedge i_EMU_MCLK)
begin
    if(!i_EMU_CLK6MPCEN_n)
    begin
        if(i_ABS_1H == 1'b1)
        begin

            if((~objcode_cntup & objcode_rst_n) == 1'b0)
            begin
                objdma_attr_cntr <= {~i_OBJDMA_BUSACK_n, 3'b011};
            end
            else
            begin
                if(objdma_attr_byte_7_n == 1'b1)
                begin
                    objdma_attr_cntr <= objdma_attr_cntr + 4'h1;
                end
            end


            if(objcode_rst_n == 1'b0)
            begin
                objdma_objcode_cntr <= 8'hA0;
            end
            else
            begin
                if(objcode_cntup == 1'b1)
                begin
                    objdma_objcode_cntr <= objdma_objcode_cntr + 8'h01;
                end
            end
        end
    end
end








wire    [7:0]   objtable_dout;

SRAM #(.aw( 10 ), .dw( 8 ), .pol( 1 ), .simhexfile()) OBJTABLE
(
    .i_MCLK                     (i_EMU_MCLK                 ),
    .i_ADDR                     (objtable_ram_addr          ),
    .i_DIN                      (i_OBJDMA_DATA_READ_BUS     ),
    .o_DOUT                     (objtable_dout              ),
    .i_CS_n                     (1'b0                       ),
    .i_RD_n                     (objtable_ram_rd            ),
    .i_WR_n                     (objtable_ram_wr            )
);






reg     [7:0]   obj_attr_latch_a, obj_attr_latch_b, obj_attr_latch_c, obj_attr_latch_d;
reg     [5:0]   obj_attr_latch_e, obj_attr_latch_f;


wire    [8:0]   obj_hpos = {obj_attr_latch_c[0], obj_attr_latch_b};
wire    [7:0]   obj_vpos = obj_attr_latch_a;
wire    [9:0]   obj_code = {obj_attr_latch_e[5:4], obj_attr_latch_d};
wire            obj_disable = obj_attr_latch_f[4];
wire            obj_size = obj_attr_latch_e[1];
wire    [3:0]   obj_palette = obj_attr_latch_f[3:0];
wire            obj_hflip = obj_attr_latch_e[2];
wire            obj_hflip_dlyd = obj_attr_latch_f[5];
wire            obj_vflip = obj_attr_latch_e[3];








always @(posedge i_EMU_MCLK)
begin
    if(!i_EMU_CLK6MPCEN_n)
    begin
        if(i_ABS_1H == 1'b1)
        begin
            if(i_DFFD_8E_B_Q == 1'b1)
            begin
                case(objtable_ram_addr[2:0])
                    3'h3: obj_attr_latch_a <= objtable_dout;      
                    3'h4: obj_attr_latch_b <= objtable_dout;      
                    3'h5: obj_attr_latch_c <= objtable_dout;      
                    3'h6: begin obj_attr_latch_d <= objtable_dout; obj_attr_latch_e <= obj_attr_latch_c[7:2]; end 
                    3'h7: obj_attr_latch_f <= {obj_attr_latch_e[2], obj_attr_latch_c[1], objtable_dout[3:0]};
                    default: ;
                endcase
            end
        end
    end
end









reg     [3:0]   seqrom_cntr_A = 4'h0;
reg     [3:0]   seqrom_cntr_B = 4'h0;
reg     [3:0]   seqrom_cntr_C = 4'hE;
reg     [3:0]   seqrom_cntr_D = 4'hE;

wire    [9:0]   seqrom_addr = {seqrom_cntr_D[0], seqrom_cntr_C[0], seqrom_cntr_B, seqrom_cntr_A};
wire    [3:0]   seqrom_dout;
assign  next_objcode = (obj_size == 1'b0) ? seqrom_dout[2] : seqrom_dout[3];

wire    [7:0]   obj_rom_low_dout, obj_rom_high_dout;
reg     [7:0]   obj_pixellatch = 8'hFF;
wire            obj_buf_hcntr_ld_n = seqrom_dout[0];
wire            obj_buf_vcntr_ld_n = seqrom_dout[1];

always @(posedge i_EMU_MCLK)
begin
    if(!i_EMU_CLK6MPCEN_n)
    begin
        if(i_DFFQ_8F_Q1 == 1'b0)
        begin
            seqrom_cntr_A <= 4'h0;
            seqrom_cntr_B <= 4'h0;
            seqrom_cntr_C <= 4'hE;
            seqrom_cntr_D <= 4'hE;
        end
        else
        begin

            if(seqrom_cntr_A == 4'hF)
            begin
                seqrom_cntr_A <= 4'h0;
            end
            else
            begin
                seqrom_cntr_A <= seqrom_cntr_A + 4'h1;
            end

            if(seqrom_cntr_A[0] == 1'b1)
            begin
                if(obj_code[9] == 1'b0)
                begin
                    `ifdef FASTBOOT
                    obj_pixellatch <= obj_rom_low_dout;

                    `else
                    obj_pixellatch <= i_EMU_OBJROM_DATA;

                    `endif
                end
                else
                begin
                    `ifdef FASTBOOT
                    obj_pixellatch <= obj_rom_high_dout;

                    `else
                    obj_pixellatch <= i_EMU_OBJROM_DATA;

                    `endif
                end
            end


            if(obj_size == 1'b0)
            begin
                if(seqrom_cntr_A == 4'hF)
                begin
                    if(seqrom_cntr_B == 4'hF)
                    begin
                        seqrom_cntr_B <= 4'h0;
                    end
                    else
                    begin
                        seqrom_cntr_B <= seqrom_cntr_B + 4'h1;
                    end
                end
            end
            else
            begin
                if(seqrom_cntr_A == 4'hF && seqrom_cntr_C == 4'hF)
                begin
                    if(seqrom_cntr_B == 4'hF)
                    begin
                        seqrom_cntr_B <= 4'h0;
                    end
                    else
                    begin
                        seqrom_cntr_B <= seqrom_cntr_B + 4'h1;
                    end
                end
            end


            if(obj_size == 1'b0)
            begin
                if(seqrom_cntr_A == 4'hF)
                begin
                    seqrom_cntr_C <= 4'hE;
                end
            end
            else
            begin
                if(seqrom_cntr_A == 4'hF)
                begin
                    if(seqrom_cntr_C == 4'hF)
                    begin
                        seqrom_cntr_C <= 4'hE;
                    end
                    else
                    begin
                        seqrom_cntr_C <= seqrom_cntr_C + 4'h1;
                    end
                end
            end


            if(obj_size == 1'b0)
            begin
                if(seqrom_cntr_B == 4'hF)
                begin
                    seqrom_cntr_D <= 4'hE;
                end
            end
            else
            begin
                if(seqrom_cntr_A == 4'hF && seqrom_cntr_C == 4'hF && seqrom_cntr_B == 4'hF)
                begin
                    if(seqrom_cntr_D == 4'hF)
                    begin
                        seqrom_cntr_D <= 4'hE;
                    end
                    else
                    begin
                        seqrom_cntr_D <= seqrom_cntr_D + 4'h1;
                    end
                end
            end
        end
    end
end


`ifdef FASTBOOT
PROM #(.aw( 10 ), .dw( 4 ), .pol( 0 ), .simhexfile("roms/rom_3t.txt")) ROM_3T
(
    .i_EMU_PROG_CLK             (                           ),
    .i_EMU_PROG_ADDR            (                           ),
    .i_EMU_PROG_DIN             (                           ),
    .i_EMU_PROG_CS_n            (1'b1                       ),
    .i_EMU_PROG_WR_n            (                           ),
    
    .i_MCLK                     (i_EMU_MCLK                 ),
    .i_ADDR                     (seqrom_addr                ),
    .o_DOUT                     (seqrom_dout                ),
    .i_CS_n                     (1'b0                       ),
    .i_RD_n                     (1'b0                       )
);

`else
PROM #(.aw( 10 ), .dw( 4 ), .pol( 0 ), .simhexfile()) ROM_3T
(
    .i_EMU_PROG_CLK             (i_EMU_MCLK                 ),
    .i_EMU_PROG_ADDR            (i_EMU_BRAM_ADDR[9:0]       ),
    .i_EMU_PROG_DIN             (i_EMU_BRAM_DATA[3:0]       ),
    .i_EMU_PROG_CS_n            (i_EMU_BRAM_SEQROM_CS_n     ),
    .i_EMU_PROG_WR_n            (i_EMU_BRAM_WR_n            ),
    
    .i_MCLK                     (i_EMU_MCLK                 ),
    .i_ADDR                     (seqrom_addr                ),
    .o_DOUT                     (seqrom_dout                ),
    .i_CS_n                     (1'b0                       ),
    .i_RD_n                     (1'b0                       )
);

`endif






wire    [15:0]  obj_rom_addr;
assign  obj_rom_addr[15:9] = obj_code[8:2];
assign  obj_rom_addr[8:7] = (obj_size == 1'b0) ? obj_code[1:0] : {seqrom_addr[8] ^ obj_hflip, seqrom_addr[9] ^ obj_vflip};
assign  obj_rom_addr[6:0] = {seqrom_addr[3], seqrom_addr[7:4], seqrom_addr[2:1]} ^ {obj_hflip, {4{obj_vflip}}, {2{obj_hflip}}};

wire    [3:0]   obj_pixelout = ((obj_hflip_dlyd ^ seqrom_addr[0]) == 1'b0) ? obj_pixellatch[7:4] : obj_pixellatch[3:0];



assign          o_EMU_OBJROM_ADDR = {obj_code[9], obj_rom_addr};

wire    [16:0]  objrom_addr;
reg     [16:0]  objrom_addr_latched;
always @(posedge i_EMU_MCLK) begin
    objrom_addr_latched <= o_EMU_OBJROM_ADDR;
end
assign          o_EMU_OBJROM_RQ_n = o_EMU_OBJROM_ADDR === objrom_addr_latched[16:1];







reg     [8:0]   obj_buf_hcntr;
wire            obj_offscreen_n = obj_buf_hcntr[8];
wire    [7:0]   obj_buf_hcntr_flip = obj_buf_hcntr[7:0] ^ {8{(i_FLIP && i_DFFQ_8F_Q2_DLYD)}};

wire    [7:0]   obj_buf_even_dout, obj_buf_odd_dout;

always @(posedge i_EMU_MCLK)
begin
    if(!i_EMU_CLK6MPCEN_n)
    begin
        if((i_DFFQ_8F_Q3_DLYD || i_DFFQ_8F_Q2_DLYD_n) == 1'b0)
        begin
            obj_buf_hcntr <= 9'd0;
        end
        else
        begin
            if(obj_buf_hcntr_ld_n == 1'b0)
            begin
                obj_buf_hcntr <= {~obj_hpos[8], obj_hpos[7:0]}; 
            end
            else
            begin
                obj_buf_hcntr <= obj_buf_hcntr + 9'd1;
            end
        end
    end
end



reg     [7:0]   obj_buf_vcntr;
reg     [7:0]   flip_v_bus;
wire    [7:0]   obj_buf_vcntr_flip = (i_DFFQ_8F_Q2_DLYD == 1'b0) ? obj_buf_vcntr : flip_v_bus;


always @(posedge i_EMU_MCLK)
begin
    if(!i_EMU_CLK6MPCEN_n)
    begin
        if(!i_DFFD_7E_A_Q_PCEN_n)
        begin
            flip_v_bus <= i_FLIP_HV_BUS;
        end
    end
end

always @(posedge i_EMU_MCLK)
begin
    if(!i_EMU_CLK6MPCEN_n)
    begin
        if(obj_buf_vcntr_ld_n == 1'b0)
        begin
            obj_buf_vcntr <= obj_vpos;
        end
        else
        begin
            if(~obj_buf_hcntr_ld_n == 1'b1)
            begin
                obj_buf_vcntr <= obj_buf_vcntr + 8'd1;
            end
            else
            begin
                obj_buf_vcntr <= obj_buf_vcntr;
            end
        end
    end
end





wire            obj_buf_even_din_en_n = i_DFFQ_8F_Q1_DLYD_n | obj_buf_hcntr_flip[0];
wire            obj_buf_odd_din_en_n = i_DFFQ_8F_Q1_DLYD_n | ~obj_buf_hcntr_flip[0];


wire            obj_buf_write_stop_n = {~obj_disable & obj_offscreen_n};
wire            obj_pixel_trn_n = ~&{obj_pixelout};
wire            obj_buf_init_n = ~&{i_OBJ_BUF_INIT_STOP_n, obj_buf_hcntr[0], {i_DFFQ_8F_Q3_DLYD & i_DFFQ_8F_Q2_DLYD}};


wire            obj_buf_even_we_n = {~&{~obj_buf_even_din_en_n, obj_buf_write_stop_n, obj_pixel_trn_n} & obj_buf_init_n};
wire            obj_buf_odd_we_n = {~&{~obj_buf_odd_din_en_n, obj_buf_write_stop_n, obj_pixel_trn_n} & obj_buf_init_n};



wire    [14:0]  obj_buf_addr = {obj_buf_vcntr_flip, obj_buf_hcntr_flip[7:1]};
wire    [7:0]   obj_buf_even_din = (obj_buf_even_din_en_n == 1'b0) ? {obj_palette, obj_pixelout} : 8'hFF;
wire    [7:0]   obj_buf_odd_din = (obj_buf_odd_din_en_n == 1'b0) ? {obj_palette, obj_pixelout} : 8'hFF;


SRAM #(.aw( 15 ), .dw( 8 ), .pol( 1 ), .simhexfile()) OBJ_BUF_EVEN
(
    .i_MCLK                     (i_EMU_MCLK                 ),
    .i_ADDR                     (obj_buf_addr               ),
    .i_DIN                      (obj_buf_even_din           ),
    .o_DOUT                     (obj_buf_even_dout          ),
    .i_CS_n                     (1'b0                       ),
    .i_RD_n                     (~i_DFFQ_8F_Q1_DLYD_n       ),
    .i_WR_n                     (obj_buf_even_we_n          )
);

SRAM #(.aw( 15 ), .dw( 8 ), .pol( 1 ), .simhexfile()) OBJ_BUF_ODD
(
    .i_MCLK                     (i_EMU_MCLK                 ),
    .i_ADDR                     (obj_buf_addr               ),
    .i_DIN                      (obj_buf_odd_din            ),
    .o_DOUT                     (obj_buf_odd_dout           ),
    .i_CS_n                     (1'b0                       ),
    .i_RD_n                     (~i_DFFQ_8F_Q1_DLYD_n       ),
    .i_WR_n                     (obj_buf_odd_we_n           )
);



reg     [15:0]      obj_outlatch;
always @(posedge i_EMU_MCLK)
begin
    if(!i_EMU_CLK6MPCEN_n)
    begin
        if(obj_buf_hcntr[0] == 1'b0)
        begin
            obj_outlatch <= {obj_buf_even_dout, obj_buf_odd_dout};
        end
    end
end

assign  o_OBJ_PIXELOUT = (~obj_buf_hcntr_flip[0] == 1'b0) ? obj_outlatch[15:8] : obj_outlatch[7:0];


endmodule
module Psychic5_obj
(

    input   wire            i_EMU_MCLK,
    input   wire            i_EMU_CLK6MPCEN_n,

    input   wire            i_EMU_INITRST_n,


    output  reg             o_OBJDMA_BUSRQ_n = 1'b1,
    input   wire            i_OBJDMA_BUSACK_n,


    output  wire    [12:0]  o_OBJDMA_ADDR_BUS,
    input   wire    [7:0]   i_OBJDMA_DATA_READ_BUS,
    output  wire            o_OBJDMA_CTRL_RD_n,
    output  wire            o_OBJDMA_CTRL_WR_n,


    input   wire            i_FLIP,
    input   wire            i_OBJ_BUF_INIT_STOP_n,


    input   wire    [7:0]   i_FLIP_HV_BUS,
    input   wire            i_ABS_4H, i_ABS_2H, i_ABS_1H,

    input   wire            i_DFFD_7E_A_Q,
    input   wire            i_DFFD_7E_A_Q_PCEN_n,
    input   wire            i_DFFD_8E_B_Q,
    input   wire            i_DFFQ_8F_Q2_NCEN_n,
    input   wire            i_DFFQ_8F_Q1,


    input   wire            i_DFFQ_8F_Q1_DLYD_n,
    input   wire            i_DFFQ_8F_Q3_DLYD,
    input   wire            i_DFFQ_8F_Q2_DLYD,
    input   wire            i_DFFQ_8F_Q2_DLYD_n,

    output  wire    [7:0]   o_OBJ_PIXELOUT,


    output  wire    [16:0]  o_EMU_OBJROM_ADDR,
    input   wire    [7:0]   i_EMU_OBJROM_DATA,
    output  wire            o_EMU_OBJROM_RQ_n,


    input   wire    [16:0]  i_EMU_BRAM_ADDR,
    input   wire    [7:0]   i_EMU_BRAM_DATA,
    input   wire            i_EMU_BRAM_WR_n,

    input   wire            i_EMU_BRAM_SEQROM_CS_n
);












assign  o_OBJDMA_CTRL_RD_n = 1'b0;
assign  o_OBJDMA_CTRL_WR_n = 1'b1;




reg             objdma_start_n;
wire            objdma_complete;

always @(posedge i_EMU_MCLK)
begin
    if(!i_EMU_INITRST_n) 
    begin
        o_OBJDMA_BUSRQ_n <= 1'b1;
    end
    else 
    begin
        if(!i_EMU_CLK6MPCEN_n)
        begin
            if(i_ABS_1H == 1'b1)
            begin
                if(objdma_complete == 1'b1)
                begin
                    o_OBJDMA_BUSRQ_n <= 1'b1;
                    objdma_start_n <= 1'b1;
                end
                else
                begin
                    if(i_DFFQ_8F_Q2_NCEN_n == 1'b0) 
                    begin
                        o_OBJDMA_BUSRQ_n <= 1'b0;
                    end
                    else
                    begin
                        o_OBJDMA_BUSRQ_n <= o_OBJDMA_BUSRQ_n;
                    end

                    if(o_OBJDMA_BUSRQ_n == 1'b1) 
                    begin
                        objdma_start_n <= 1'b1;
                    end
                    else
                    begin
                        objdma_start_n <= i_OBJDMA_BUSACK_n;
                    end
                end
            end
            else
            begin
                if(i_DFFQ_8F_Q2_NCEN_n == 1'b0)
                begin
                    o_OBJDMA_BUSRQ_n <= 1'b0;
                end
                else
                begin
                    o_OBJDMA_BUSRQ_n <= o_OBJDMA_BUSRQ_n;
                end

                if(o_OBJDMA_BUSRQ_n == 1'b1) 
                begin
                    objdma_start_n <= 1'b1;
                end
                else
                begin
                    objdma_start_n <= objdma_start_n;
                end
            end
        end
    end
end








reg     [3:0]   objdma_attr_cntr = 4'b1011;
reg     [7:0]   objdma_objcode_cntr = 8'b1010_0000;


wire            objdma_attr_byte_f = &{objdma_attr_cntr};
wire            objdma_attr_byte_7_n = ~&{~objdma_attr_cntr[3], objdma_attr_cntr[2:0]};


wire            next_objcode;
wire            objcode_cntup = ((~objdma_attr_byte_7_n & next_objcode) | objdma_attr_byte_f);
wire            objcode_rst_n = ~objdma_start_n | i_DFFD_8E_B_Q;
assign  objdma_complete = &{objdma_objcode_cntr, objcode_cntup};


wire    [9:0]   objtable_ram_addr = {objdma_objcode_cntr[6:0], objdma_attr_cntr[2:0]};
wire            objtable_ram_rd = ~i_OBJDMA_BUSACK_n;
wire            objtable_ram_wr = objdma_start_n | ~i_ABS_1H;


assign  o_OBJDMA_ADDR_BUS = {2'b10, objdma_objcode_cntr[6:0], objdma_attr_cntr[3:0]};

always @(posedge i_EMU_MCLK)
begin
    if(!i_EMU_CLK6MPCEN_n)
    begin
        if(i_ABS_1H == 1'b1)
        begin

            if((~objcode_cntup & objcode_rst_n) == 1'b0)
            begin
                objdma_attr_cntr <= {~i_OBJDMA_BUSACK_n, 3'b011};
            end
            else
            begin
                if(objdma_attr_byte_7_n == 1'b1)
                begin
                    objdma_attr_cntr <= objdma_attr_cntr + 4'h1;
                end
            end


            if(objcode_rst_n == 1'b0)
            begin
                objdma_objcode_cntr <= 8'hA0;
            end
            else
            begin
                if(objcode_cntup == 1'b1)
                begin
                    objdma_objcode_cntr <= objdma_objcode_cntr + 8'h01;
                end
            end
        end
    end
end








wire    [7:0]   objtable_dout;

SRAM #(.aw( 10 ), .dw( 8 ), .pol( 1 ), .simhexfile()) OBJTABLE
(
    .i_MCLK                     (i_EMU_MCLK                 ),
    .i_ADDR                     (objtable_ram_addr          ),
    .i_DIN                      (i_OBJDMA_DATA_READ_BUS     ),
    .o_DOUT                     (objtable_dout              ),
    .i_CS_n                     (1'b0                       ),
    .i_RD_n                     (objtable_ram_rd            ),
    .i_WR_n                     (objtable_ram_wr            )
);






reg     [7:0]   obj_attr_latch_a, obj_attr_latch_b, obj_attr_latch_c, obj_attr_latch_d;
reg     [5:0]   obj_attr_latch_e, obj_attr_latch_f;


wire    [8:0]   obj_hpos = {obj_attr_latch_c[0], obj_attr_latch_b};
wire    [7:0]   obj_vpos = obj_attr_latch_a;
wire    [9:0]   obj_code = {obj_attr_latch_e[5:4], obj_attr_latch_d};
wire            obj_disable = obj_attr_latch_f[4];
wire            obj_size = obj_attr_latch_e[1];
wire    [3:0]   obj_palette = obj_attr_latch_f[3:0];
wire            obj_hflip = obj_attr_latch_e[2];
wire            obj_hflip_dlyd = obj_attr_latch_f[5];
wire            obj_vflip = obj_attr_latch_e[3];








always @(posedge i_EMU_MCLK)
begin
    if(!i_EMU_CLK6MPCEN_n)
    begin
        if(i_ABS_1H == 1'b1)
        begin
            if(i_DFFD_8E_B_Q == 1'b1)
            begin
                case(objtable_ram_addr[2:0])
                    3'h3: obj_attr_latch_a <= objtable_dout;      
                    3'h4: obj_attr_latch_b <= objtable_dout;      
                    3'h5: obj_attr_latch_c <= objtable_dout;      
                    3'h6: begin obj_attr_latch_d <= objtable_dout; obj_attr_latch_e <= obj_attr_latch_c[7:2]; end 
                    3'h7: obj_attr_latch_f <= {obj_attr_latch_e[2], obj_attr_latch_c[1], objtable_dout[3:0]};
                    default: ;
                endcase
            end
        end
    end
end









reg     [3:0]   seqrom_cntr_A = 4'h0;
reg     [3:0]   seqrom_cntr_B = 4'h0;
reg     [3:0]   seqrom_cntr_C = 4'hE;
reg     [3:0]   seqrom_cntr_D = 4'hE;

wire    [9:0]   seqrom_addr = {seqrom_cntr_D[0], seqrom_cntr_C[0], seqrom_cntr_B, seqrom_cntr_A};
wire    [3:0]   seqrom_dout;
assign  next_objcode = (obj_size == 1'b0) ? seqrom_dout[2] : seqrom_dout[3];

wire    [7:0]   obj_rom_low_dout, obj_rom_high_dout;
reg     [7:0]   obj_pixellatch = 8'hFF;
wire            obj_buf_hcntr_ld_n = seqrom_dout[0];
wire            obj_buf_vcntr_ld_n = seqrom_dout[1];

always @(posedge i_EMU_MCLK)
begin
    if(!i_EMU_CLK6MPCEN_n)
    begin
        if(i_DFFQ_8F_Q1 == 1'b0)
        begin
            seqrom_cntr_A <= 4'h0;
            seqrom_cntr_B <= 4'h0;
            seqrom_cntr_C <= 4'hE;
            seqrom_cntr_D <= 4'hE;
        end
        else
        begin

            if(seqrom_cntr_A == 4'hF)
            begin
                seqrom_cntr_A <= 4'h0;
            end
            else
            begin
                seqrom_cntr_A <= seqrom_cntr_A + 4'h1;
            end

            if(seqrom_cntr_A[0] == 1'b1)
            begin
                if(obj_code[9] == 1'b0)
                begin
                    `ifdef FASTBOOT
                    obj_pixellatch <= obj_rom_low_dout;

                    `else
                    obj_pixellatch <= i_EMU_OBJROM_DATA;

                    `endif
                end
                else
                begin
                    `ifdef FASTBOOT
                    obj_pixellatch <= obj_rom_high_dout;

                    `else
                    obj_pixellatch <= i_EMU_OBJROM_DATA;

                    `endif
                end
            end


            if(obj_size == 1'b0)
            begin
                if(seqrom_cntr_A == 4'hF)
                begin
                    if(seqrom_cntr_B == 4'hF)
                    begin
                        seqrom_cntr_B <= 4'h0;
                    end
                    else
                    begin
                        seqrom_cntr_B <= seqrom_cntr_B + 4'h1;
                    end
                end
            end
            else
            begin
                if(seqrom_cntr_A == 4'hF && seqrom_cntr_C == 4'hF)
                begin
                    if(seqrom_cntr_B == 4'hF)
                    begin
                        seqrom_cntr_B <= 4'h0;
                    end
                    else
                    begin
                        seqrom_cntr_B <= seqrom_cntr_B + 4'h1;
                    end
                end
            end


            if(obj_size == 1'b0)
            begin
                if(seqrom_cntr_A == 4'hF)
                begin
                    seqrom_cntr_C <= 4'hE;
                end
            end
            else
            begin
                if(seqrom_cntr_A == 4'hF)
                begin
                    if(seqrom_cntr_C == 4'hF)
                    begin
                        seqrom_cntr_C <= 4'hE;
                    end
                    else
                    begin
                        seqrom_cntr_C <= seqrom_cntr_C + 4'h1;
                    end
                end
            end


            if(obj_size == 1'b0)
            begin
                if(seqrom_cntr_B == 4'hF)
                begin
                    seqrom_cntr_D <= 4'hE;
                end
            end
            else
            begin
                if(seqrom_cntr_A == 4'hF && seqrom_cntr_C == 4'hF && seqrom_cntr_B == 4'hF)
                begin
                    if(seqrom_cntr_D == 4'hF)
                    begin
                        seqrom_cntr_D <= 4'hE;
                    end
                    else
                    begin
                        seqrom_cntr_D <= seqrom_cntr_D + 4'h1;
                    end
                end
            end
        end
    end
end


`ifdef FASTBOOT
PROM #(.aw( 10 ), .dw( 4 ), .pol( 0 ), .simhexfile("roms/rom_3t.txt")) ROM_3T
(
    .i_EMU_PROG_CLK             (                           ),
    .i_EMU_PROG_ADDR            (                           ),
    .i_EMU_PROG_DIN             (                           ),
    .i_EMU_PROG_CS_n            (1'b1                       ),
    .i_EMU_PROG_WR_n            (                           ),
    
    .i_MCLK                     (i_EMU_MCLK                 ),
    .i_ADDR                     (seqrom_addr                ),
    .o_DOUT                     (seqrom_dout                ),
    .i_CS_n                     (1'b0                       ),
    .i_RD_n                     (1'b0                       )
);

`else
PROM #(.aw( 10 ), .dw( 4 ), .pol( 0 ), .simhexfile()) ROM_3T
(
    .i_EMU_PROG_CLK             (i_EMU_MCLK                 ),
    .i_EMU_PROG_ADDR            (i_EMU_BRAM_ADDR[9:0]       ),
    .i_EMU_PROG_DIN             (i_EMU_BRAM_DATA[3:0]       ),
    .i_EMU_PROG_CS_n            (i_EMU_BRAM_SEQROM_CS_n     ),
    .i_EMU_PROG_WR_n            (i_EMU_BRAM_WR_n            ),
    
    .i_MCLK                     (i_EMU_MCLK                 ),
    .i_ADDR                     (seqrom_addr                ),
    .o_DOUT                     (seqrom_dout                ),
    .i_CS_n                     (1'b0                       ),
    .i_RD_n                     (1'b0                       )
);

`endif






wire    [15:0]  obj_rom_addr;
assign  obj_rom_addr[15:9] = obj_code[8:2];
assign  obj_rom_addr[8:7] = (obj_size == 1'b0) ? obj_code[1:0] : {seqrom_addr[8] ^ obj_hflip, seqrom_addr[9] ^ obj_vflip};
assign  obj_rom_addr[6:0] = {seqrom_addr[3], seqrom_addr[7:4], seqrom_addr[2:1]} ^ {obj_hflip, {4{obj_vflip}}, {2{obj_hflip}}};

wire    [3:0]   obj_pixelout = ((obj_hflip_dlyd ^ seqrom_addr[0]) == 1'b0) ? obj_pixellatch[7:4] : obj_pixellatch[3:0];



assign          o_EMU_OBJROM_ADDR = {obj_code[9], obj_rom_addr};

wire    [16:0]  objrom_addr;
reg     [16:0]  objrom_addr_latched;
always @(posedge i_EMU_MCLK) begin
    objrom_addr_latched <= o_EMU_OBJROM_ADDR;
end
assign          o_EMU_OBJROM_RQ_n = o_EMU_OBJROM_ADDR === objrom_addr_latched[16:1];







reg     [8:0]   obj_buf_hcntr;
wire            obj_offscreen_n = obj_buf_hcntr[8];
wire    [7:0]   obj_buf_hcntr_flip = obj_buf_hcntr[7:0] ^ {8{(i_FLIP && i_DFFQ_8F_Q2_DLYD)}};

wire    [7:0]   obj_buf_even_dout, obj_buf_odd_dout;

always @(posedge i_EMU_MCLK)
begin
    if(!i_EMU_CLK6MPCEN_n)
    begin
        if((i_DFFQ_8F_Q3_DLYD || i_DFFQ_8F_Q2_DLYD_n) == 1'b0)
        begin
            obj_buf_hcntr <= 9'd0;
        end
        else
        begin
            if(obj_buf_hcntr_ld_n == 1'b0)
            begin
                obj_buf_hcntr <= {~obj_hpos[8], obj_hpos[7:0]}; 
            end
            else
            begin
                obj_buf_hcntr <= obj_buf_hcntr + 9'd1;
            end
        end
    end
end



reg     [7:0]   obj_buf_vcntr;
reg     [7:0]   flip_v_bus;
wire    [7:0]   obj_buf_vcntr_flip = (i_DFFQ_8F_Q2_DLYD == 1'b0) ? obj_buf_vcntr : flip_v_bus;


always @(posedge i_EMU_MCLK)
begin
    if(!i_EMU_CLK6MPCEN_n)
    begin
        if(!i_DFFD_7E_A_Q_PCEN_n)
        begin
            flip_v_bus <= i_FLIP_HV_BUS;
        end
    end
end

always @(posedge i_EMU_MCLK)
begin
    if(!i_EMU_CLK6MPCEN_n)
    begin
        if(obj_buf_vcntr_ld_n == 1'b0)
        begin
            obj_buf_vcntr <= obj_vpos;
        end
        else
        begin
            if(~obj_buf_hcntr_ld_n == 1'b1)
            begin
                obj_buf_vcntr <= obj_buf_vcntr + 8'd1;
            end
            else
            begin
                obj_buf_vcntr <= obj_buf_vcntr;
            end
        end
    end
end





wire            obj_buf_even_din_en_n = i_DFFQ_8F_Q1_DLYD_n | obj_buf_hcntr_flip[0];
wire            obj_buf_odd_din_en_n = i_DFFQ_8F_Q1_DLYD_n | ~obj_buf_hcntr_flip[0];


wire            obj_buf_write_stop_n = {~obj_disable & obj_offscreen_n};
wire            obj_pixel_trn_n = ~&{obj_pixelout};
wire            obj_buf_init_n = ~&{i_OBJ_BUF_INIT_STOP_n, obj_buf_hcntr[0], {i_DFFQ_8F_Q3_DLYD & i_DFFQ_8F_Q2_DLYD}};


wire            obj_buf_even_we_n = {~&{~obj_buf_even_din_en_n, obj_buf_write_stop_n, obj_pixel_trn_n} & obj_buf_init_n};
wire            obj_buf_odd_we_n = {~&{~obj_buf_odd_din_en_n, obj_buf_write_stop_n, obj_pixel_trn_n} & obj_buf_init_n};



wire    [14:0]  obj_buf_addr = {obj_buf_vcntr_flip, obj_buf_hcntr_flip[7:1]};
wire    [7:0]   obj_buf_even_din = (obj_buf_even_din_en_n == 1'b0) ? {obj_palette, obj_pixelout} : 8'hFF;
wire    [7:0]   obj_buf_odd_din = (obj_buf_odd_din_en_n == 1'b0) ? {obj_palette, obj_pixelout} : 8'hFF;


SRAM #(.aw( 15 ), .dw( 8 ), .pol( 1 ), .simhexfile()) OBJ_BUF_EVEN
(
    .i_MCLK                     (i_EMU_MCLK                 ),
    .i_ADDR                     (obj_buf_addr               ),
    .i_DIN                      (obj_buf_even_din           ),
    .o_DOUT                     (obj_buf_even_dout          ),
    .i_CS_n                     (1'b0                       ),
    .i_RD_n                     (~i_DFFQ_8F_Q1_DLYD_n       ),
    .i_WR_n                     (obj_buf_even_we_n          )
);

SRAM #(.aw( 15 ), .dw( 8 ), .pol( 1 ), .simhexfile()) OBJ_BUF_ODD
(
    .i_MCLK                     (i_EMU_MCLK                 ),
    .i_ADDR                     (obj_buf_addr               ),
    .i_DIN                      (obj_buf_odd_din            ),
    .o_DOUT                     (obj_buf_odd_dout           ),
    .i_CS_n                     (1'b0                       ),
    .i_RD_n                     (~i_DFFQ_8F_Q1_DLYD_n       ),
    .i_WR_n                     (obj_buf_odd_we_n           )
);



reg     [15:0]      obj_outlatch;
always @(posedge i_EMU_MCLK)
begin
    if(!i_EMU_CLK6MPCEN_n)
    begin
        if(obj_buf_hcntr[0] == 1'b0)
        begin
            obj_outlatch <= {obj_buf_even_dout, obj_buf_odd_dout};
        end
    end
end

assign  o_OBJ_PIXELOUT = (~obj_buf_hcntr_flip[0] == 1'b0) ? obj_outlatch[15:8] : obj_outlatch[7:0];


endmodule