data/full_repos/permissive/441359809/src/yosys/techlibs/sf2/cells_map.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/techlibs/sf2/cells_map.v:5: Multiple top level modules\n                                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                            : ... Top module \'$_DFFE_PN0P_\'\nmodule \\$_DFFE_PN0P_ (input D, C, R, E, output Q);\n       ^~~~~~~~~~~~~\n                                                                                            : ... Top module \'$_DFFE_PN1P_\'\nmodule \\$_DFFE_PN1P_ (input D, C, R, E, output Q);\n       ^~~~~~~~~~~~~\n                                                                                            : ... Top module \'$_SDFFCE_PN0P_\'\nmodule \\$_SDFFCE_PN0P_ (input D, C, R, E, output Q);\n       ^~~~~~~~~~~~~~~\n                                                                                            : ... Top module \'$_SDFFCE_PN1P_\'\nmodule \\$_SDFFCE_PN1P_ (input D, C, R, E, output Q);\n       ^~~~~~~~~~~~~~~\n                                                                                            : ... Top module \'$_DLATCH_PN0_\'\nmodule \\$_DLATCH_PN0_ (input D, R, E, output Q);\n       ^~~~~~~~~~~~~~\n                                                                                            : ... Top module \'$_DLATCH_PN1_\'\nmodule \\$_DLATCH_PN1_ (input D, R, E, output Q);\n       ^~~~~~~~~~~~~~\n                                                                                            : ... Top module \'$lut\'\nmodule \\$lut (A, Y);\n       ^~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/441359809/src/yosys/techlibs/sf2/cells_map.v:31: Little bit endian vector: MSB < LSB of bit range: -1:0\n  input [WIDTH-1:0] A;\n        ^\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/sf2/cells_map.v:22: Cannot find file containing module: \'SLE\'\n  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(E), .EN(1\'b1), .ALn(R), .ADn(1\'b0), .SLn(1\'b1), .SD(1\'b0), .LAT(1\'b1), .Q(Q));\n  ^~~\n        ... Looked in:\n             data/full_repos/permissive/441359809/src/yosys/techlibs/sf2,data/full_repos/permissive/441359809/SLE\n             data/full_repos/permissive/441359809/src/yosys/techlibs/sf2,data/full_repos/permissive/441359809/SLE.v\n             data/full_repos/permissive/441359809/src/yosys/techlibs/sf2,data/full_repos/permissive/441359809/SLE.sv\n             SLE\n             SLE.v\n             SLE.sv\n             obj_dir/SLE\n             obj_dir/SLE.v\n             obj_dir/SLE.sv\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/sf2/cells_map.v:18: Cannot find file containing module: \'SLE\'\n  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(E), .EN(1\'b1), .ALn(R), .ADn(1\'b1), .SLn(1\'b1), .SD(1\'b0), .LAT(1\'b1), .Q(Q));\n  ^~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/sf2/cells_map.v:14: Cannot find file containing module: \'SLE\'\n  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(E), .ALn(1\'b1), .ADn(1\'b0), .SLn(R), .SD(1\'b1), .LAT(1\'b0), .Q(Q));\n  ^~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/sf2/cells_map.v:10: Cannot find file containing module: \'SLE\'\n  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(E), .ALn(1\'b1), .ADn(1\'b0), .SLn(R), .SD(1\'b0), .LAT(1\'b0), .Q(Q));\n  ^~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/sf2/cells_map.v:6: Cannot find file containing module: \'SLE\'\n  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(E), .ALn(R), .ADn(1\'b0), .SLn(1\'b1), .SD(1\'b0), .LAT(1\'b0), .Q(Q));\n  ^~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/sf2/cells_map.v:2: Cannot find file containing module: \'SLE\'\n  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(E), .ALn(R), .ADn(1\'b1), .SLn(1\'b1), .SD(1\'b0), .LAT(1\'b0), .Q(Q));\n  ^~~\n%Error: Exiting due to 6 error(s), 2 warning(s)\n'
module \$_DLATCH_PN0_ (input D, R, E, output Q);
  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(E), .EN(1'b1), .ALn(R), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b1), .Q(Q));
endmodule
module \$_DLATCH_PN0_ (input D, R, E, output Q);

  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(E), .EN(1'b1), .ALn(R), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b1), .Q(Q));
endmodule