data/full_repos/permissive/443770883/lab3/dtestBench.v
1: b'%Error: data/full_repos/permissive/443770883/lab3/dtestBench.v:10: Unsupported or unknown PLI call: $dumpfile\n  initial begin $dumpfile("dump1.vcd");\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/443770883/lab3/dtestBench.v:11: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,tb); \n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/443770883/lab3/dtestBench.v:13: Unsupported: Ignoring delay on this delayed statement.\n  initial begin reset = 1\'b1; #12.5 reset = 1\'b0; end\n                              ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/443770883/lab3/dtestBench.v:14: Unsupported: Ignoring delay on this delayed statement.\n  initial clk = 1\'b0; always #5 clk =~ clk;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/443770883/lab3/dtestBench.v:29: Unsupported: Ignoring delay on this delayed statement.\n      begin #10 {i0, i1, cin}=test_vecs[i]; end\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/443770883/lab3/dtestBench.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #6 for(i=0;i<8;i=i+1)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/443770883/lab3/dtestBench.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #100 $finish;\n    ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;
  reg clk, reset;
  reg [3:0] i0, i1; reg cin;
  wire [3:0] o; wire cout;
  reg [8:0] test_vecs [0:(`TESTVECS-1)];
  integer i;
  initial begin $dumpfile("dump1.vcd");
 $dumpvars(0,tb); 
  end
  initial begin reset = 1'b1; #12.5 reset = 1'b0; end
  initial clk = 1'b0; always #5 clk =~ clk;
  initial begin
    test_vecs[0] = 9'b000000010;
    test_vecs[1] = 9'b000100010;
    test_vecs[2] = 9'b011100010;
    test_vecs[3] = 9'b000001110;
    test_vecs[4] = 9'b011001111;
    test_vecs[5] = 9'b001110011;
    test_vecs[6] = 9'b111100011;
    test_vecs[7] = 9'b011101110;
  end
  initial {i0, i1, cin, i} = 0;
  fulladdR u0 (i0, i1, cin, o, cout);
  initial begin
    #6 for(i=0;i<`TESTVECS;i=i+1)
      begin #10 {i0, i1, cin}=test_vecs[i]; end
    #100 $finish;
  end
endmodule
module tb;

  reg clk, reset;
  reg [3:0] i0, i1; reg cin;
  wire [3:0] o; wire cout;
  reg [8:0] test_vecs [0:(`TESTVECS-1)];
  integer i;
  initial begin $dumpfile("dump1.vcd");
 $dumpvars(0,tb); 
  end
  initial begin reset = 1'b1; #12.5 reset = 1'b0; end
  initial clk = 1'b0; always #5 clk =~ clk;
  initial begin
    test_vecs[0] = 9'b000000010;
    test_vecs[1] = 9'b000100010;
    test_vecs[2] = 9'b011100010;
    test_vecs[3] = 9'b000001110;
    test_vecs[4] = 9'b011001111;
    test_vecs[5] = 9'b001110011;
    test_vecs[6] = 9'b111100011;
    test_vecs[7] = 9'b011101110;
  end
  initial {i0, i1, cin, i} = 0;
  fulladdR u0 (i0, i1, cin, o, cout);
  initial begin
    #6 for(i=0;i<`TESTVECS;i=i+1)
      begin #10 {i0, i1, cin}=test_vecs[i]; end
    #100 $finish;
  end
endmodule