data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Saber_blocks/ComputeCoreWrapper.v
1: b"%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Saber_blocks/ComputeCoreWrapper.v:61: Cannot find file containing module: 'ComputeCore3'\nComputeCore3 CORE(clk, rst_core, address_ext, dina_ext, wea_ext_core,\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Saber_blocks,data/full_repos/permissive/428190211/ComputeCore3\n             data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Saber_blocks,data/full_repos/permissive/428190211/ComputeCore3.v\n             data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Saber_blocks,data/full_repos/permissive/428190211/ComputeCore3.sv\n             ComputeCore3\n             ComputeCore3.v\n             ComputeCore3.sv\n             obj_dir/ComputeCore3\n             obj_dir/ComputeCore3.v\n             obj_dir/ComputeCore3.sv\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Saber_blocks/ComputeCoreWrapper.v:74: Cannot find file containing module: 'ISA_control'\nISA_control ISA_CTRL(clk, rst_ISA, start_ISA, done_ins_computation,\n^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module ComputeCoreWrapper(clk, control_low_word, control_high_word, 
                    dina_ext_low_word, dina_ext_high_word, 
                    dout_ext_low_word, dout_ext_high_word, 
                    status);
input clk;
input [31:0] control_low_word, control_high_word;
input [31:0] dina_ext_low_word, dina_ext_high_word;

output [31:0] dout_ext_low_word, dout_ext_high_word;
output [31:0] status;


wire [63:0] dina_ext = {dina_ext_high_word,dina_ext_low_word};
wire [63:0] dout_ext;
reg [31:0] status;
wire rst_core;

wire [9:0] address_ext;
wire wea_ext, wea_ext_core, wea_ext_ISA;

wire [34:0] command_in;
wire command_we0, command_we1;
wire done_shake, done_vmul, done_addround, done_addpack, done_bs2polvecp, done_unpack, done_copy, done_sampler, done_verify, done_cmov, done_timer;

wire rst_ISA, start_ISA, done_ins_computation, done_all_computation;
wire [31:0] status_wire;
wire [30:0] cycle_count;

assign address_ext = control_low_word[9:0];
assign wea_ext = control_low_word[10];





assign status_wire = {cycle_count,done_all_computation};
assign {dout_ext_high_word,dout_ext_low_word} = dout_ext;
assign wea_ext_core = (wea_ext==1'b1 & control_low_word[11]==1'b0) ? 1'b1 : 1'b0;

always @(posedge clk)
    status <= status_wire;
    
ComputeCore3 CORE(clk, rst_core, address_ext, dina_ext, wea_ext_core,
					command_in, command_we0, command_we1,
					dout_ext, 
					done_shake, done_vmul, done_addround, 
					done_addpack, done_bs2polvecp, done_unpack, done_copy, done_sampler, done_verify, done_cmov, done_timer);

assign done_ins_computation = done_shake|done_vmul|done_addround|done_addpack|done_bs2polvecp|done_unpack|done_copy|done_sampler|done_verify|done_cmov|done_timer;

assign rst_core = control_high_word[0];
assign rst_ISA = control_high_word[0];
assign start_ISA = control_high_word[1];
assign wea_ext_ISA = (wea_ext==1'b1 & control_low_word[11]==1'b1) ? 1'b1 : 1'b0;

ISA_control ISA_CTRL(clk, rst_ISA, start_ISA, done_ins_computation,
                                    address_ext[5:0], dina_ext[36:0], wea_ext_ISA,
									command_in,	command_we0, command_we1,
									done_all_computation,
									cycle_count);

endmodule
module ComputeCoreWrapper(clk, control_low_word, control_high_word, 
                    dina_ext_low_word, dina_ext_high_word, 
                    dout_ext_low_word, dout_ext_high_word, 
                    status);

input clk;
input [31:0] control_low_word, control_high_word;
input [31:0] dina_ext_low_word, dina_ext_high_word;

output [31:0] dout_ext_low_word, dout_ext_high_word;
output [31:0] status;


wire [63:0] dina_ext = {dina_ext_high_word,dina_ext_low_word};
wire [63:0] dout_ext;
reg [31:0] status;
wire rst_core;

wire [9:0] address_ext;
wire wea_ext, wea_ext_core, wea_ext_ISA;

wire [34:0] command_in;
wire command_we0, command_we1;
wire done_shake, done_vmul, done_addround, done_addpack, done_bs2polvecp, done_unpack, done_copy, done_sampler, done_verify, done_cmov, done_timer;

wire rst_ISA, start_ISA, done_ins_computation, done_all_computation;
wire [31:0] status_wire;
wire [30:0] cycle_count;

assign address_ext = control_low_word[9:0];
assign wea_ext = control_low_word[10];





assign status_wire = {cycle_count,done_all_computation};
assign {dout_ext_high_word,dout_ext_low_word} = dout_ext;
assign wea_ext_core = (wea_ext==1'b1 & control_low_word[11]==1'b0) ? 1'b1 : 1'b0;

always @(posedge clk)
    status <= status_wire;
    
ComputeCore3 CORE(clk, rst_core, address_ext, dina_ext, wea_ext_core,
					command_in, command_we0, command_we1,
					dout_ext, 
					done_shake, done_vmul, done_addround, 
					done_addpack, done_bs2polvecp, done_unpack, done_copy, done_sampler, done_verify, done_cmov, done_timer);

assign done_ins_computation = done_shake|done_vmul|done_addround|done_addpack|done_bs2polvecp|done_unpack|done_copy|done_sampler|done_verify|done_cmov|done_timer;

assign rst_core = control_high_word[0];
assign rst_ISA = control_high_word[0];
assign start_ISA = control_high_word[1];
assign wea_ext_ISA = (wea_ext==1'b1 & control_low_word[11]==1'b1) ? 1'b1 : 1'b0;

ISA_control ISA_CTRL(clk, rst_ISA, start_ISA, done_ins_computation,
                                    address_ext[5:0], dina_ext[36:0], wea_ext_ISA,
									command_in,	command_we0, command_we1,
									done_all_computation,
									cycle_count);

endmodule