data/full_repos/permissive/446997925/hw4/mips_registers.v
1: b'%Warning-WIDTH: data/full_repos/permissive/446997925/hw4/mips_registers.v:16: Operator NEQ expects 5 bits on the LHS, but LHS\'s VARREF \'write_reg\' generates 3 bits.\n                                                                            : ... In instance mips_registers\n  if(signal_reg_write && write_reg != 5\'b0) begin  \n                                   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module mips_registers
( read_data_1, read_data_2, write_data, read_reg_1, read_reg_2, write_reg, signal_reg_write, clk );

	output [31:0] read_data_1, read_data_2;
	input [31:0] write_data;
	input [2:0] read_reg_1, read_reg_2, write_reg;
	input signal_reg_write, clk;
	
	reg [31:0] registers [7:0];
	
	assign read_data_1 = registers[read_reg_1];
	assign read_data_2 = registers[read_reg_2];
	
	always @(posedge clk) begin

		if(signal_reg_write && write_reg != 5'b0) begin
			registers[write_reg]<=write_data;
		end


	end
	
endmodule
module mips_registers
( read_data_1, read_data_2, write_data, read_reg_1, read_reg_2, write_reg, signal_reg_write, clk );


	output [31:0] read_data_1, read_data_2;
	input [31:0] write_data;
	input [2:0] read_reg_1, read_reg_2, write_reg;
	input signal_reg_write, clk;
	
	reg [31:0] registers [7:0];
	
	assign read_data_1 = registers[read_reg_1];
	assign read_data_2 = registers[read_reg_2];
	
	always @(posedge clk) begin

		if(signal_reg_write && write_reg != 5'b0) begin
			registers[write_reg]<=write_data;
		end


	end
	
endmodule