data/full_repos/permissive/449071180/mux.v
data/verilator_xmls/be91d328-a115-4b68-a8a6-63c3a60a36d4.xml
module mux(in1,in2,cntrl,out1);
input in1;
input in2;

input cntrl;

output reg out1;

always@* begin
if( cntrl == 0) begin
out1 = in2;
end else begin
out1 = in1;
end
end

endmodule
module mux(in1,in2,cntrl,out1);

input in1;
input in2;

input cntrl;

output reg out1;

always@* begin
if( cntrl == 0) begin
out1 = in2;
end else begin
out1 = in1;
end
end

endmodule