data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v
1: b'%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:68: Cannot find include file: sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v\n`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/504248338/verilog/dv/user_i2cm,data/full_repos/permissive/504248338/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v\n             data/full_repos/permissive/504248338/verilog/dv/user_i2cm,data/full_repos/permissive/504248338/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v.v\n             data/full_repos/permissive/504248338/verilog/dv/user_i2cm,data/full_repos/permissive/504248338/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v.sv\n             sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v\n             sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v.v\n             sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v.sv\n             obj_dir/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v\n             obj_dir/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v.v\n             obj_dir/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v.sv\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:69: Cannot find include file: i2c_slave_model.v\n`include "i2c_slave_model.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n always #12.5 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:129: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:136: Unsupported: Ignoring delay on this delayed statement.\n   #200;  \n   ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:137: syntax error, unexpected \'@\'\n   repeat (10) @(posedge clock);\n               ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:143: syntax error, unexpected \'@\'\n   repeat (10) @(posedge clock);\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:144: Unsupported: Ignoring delay on this delayed statement.\n   #1;\n   ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:146: Define or directive not defined: \'`ADDR_SPACE_WBHOST\'\n   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,\'h01);\n                      ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:146: Define or directive not defined: \'`WBHOST_GLBL_CFG\'\n   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,\'h01);\n                                         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:146: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,\'h01);\n                                                         ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:149: Define or directive not defined: \'`ADDR_SPACE_PINMUX\'\n   wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,\'h4000);\n                      ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:149: Define or directive not defined: \'`PINMUX_GPIO_MULTI_FUNC\'\n   wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,\'h4000);\n                                         ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:149: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n   wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,\'h4000);\n                                                                ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:152: Define or directive not defined: \'`ADDR_SPACE_PINMUX\'\n   wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h010);\n                      ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:152: Define or directive not defined: \'`PINMUX_GBL_CFG0\'\n   wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h010);\n                                         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:152: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n   wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h010);\n                                                         ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:154: syntax error, unexpected \'@\'\n   repeat (100) @(posedge clock);  \n                ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:160: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n     wb_user_core_write(`ADDR_SPACE_I2CM+(8\'h0<<2),8\'hC7);  \n                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:161: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n     wb_user_core_write(`ADDR_SPACE_I2CM+(8\'h1<<2),8\'h00);  \n                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:163: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n     wb_user_core_write(`ADDR_SPACE_I2CM+(8\'h2<<2),8\'h80);  \n                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:168: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n    wb_user_core_write(`ADDR_SPACE_I2CM+(8\'h3<<2),8\'h20);  \n                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:169: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n    wb_user_core_write(`ADDR_SPACE_I2CM+(8\'h4<<2),8\'h90);  \n                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:172: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n      wb_user_core_read(`ADDR_SPACE_I2CM+(8\'h4<<2),read_data);  \n                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:174: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n    wb_user_core_write(`ADDR_SPACE_I2CM+(8\'h3<<2),8\'h66);  \n                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:175: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n    wb_user_core_write(`ADDR_SPACE_I2CM+(8\'h4<<2),8\'h10);  \n                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:179: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n      wb_user_core_read(`ADDR_SPACE_I2CM+(8\'h4<<2),read_data);  \n                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:182: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n    wb_user_core_write(`ADDR_SPACE_I2CM+(8\'h3<<2),8\'h12);  \n                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:183: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n    wb_user_core_write(`ADDR_SPACE_I2CM+(8\'h4<<2),8\'h10);  \n                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:187: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n      wb_user_core_read(`ADDR_SPACE_I2CM+(8\'h4<<2),read_data);  \n                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:190: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n    wb_user_core_write(`ADDR_SPACE_I2CM+(8\'h3<<2),8\'h34);  \n                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:191: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n    wb_user_core_write(`ADDR_SPACE_I2CM+(8\'h4<<2),8\'h10);  \n                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:195: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n      wb_user_core_read(`ADDR_SPACE_I2CM+(8\'h4<<2),read_data);  \n                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:198: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n    wb_user_core_write(`ADDR_SPACE_I2CM+(8\'h3<<2),8\'h56);  \n                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:199: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n    wb_user_core_write(`ADDR_SPACE_I2CM+(8\'h4<<2),8\'h10);  \n                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:203: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n      wb_user_core_read(`ADDR_SPACE_I2CM+(8\'h4<<2),read_data);  \n                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:206: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n    wb_user_core_write(`ADDR_SPACE_I2CM+(8\'h3<<2),8\'h78);  \n                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:207: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n    wb_user_core_write(`ADDR_SPACE_I2CM+(8\'h4<<2),8\'h50);  \n                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:211: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n      wb_user_core_read(`ADDR_SPACE_I2CM+(8\'h4<<2),read_data);  \n                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:217: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n    wb_user_core_write(`ADDR_SPACE_I2CM+(8\'h3<<2),8\'h20);  \n                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:218: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n    wb_user_core_write(`ADDR_SPACE_I2CM+(8\'h4<<2),8\'h90);  \n                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:221: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n      wb_user_core_read(`ADDR_SPACE_I2CM+(8\'h4<<2),read_data);  \n                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:223: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n    wb_user_core_write(`ADDR_SPACE_I2CM+(8\'h3<<2),8\'h66);  \n                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:224: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n    wb_user_core_write(`ADDR_SPACE_I2CM+(8\'h4<<2),8\'h50);  \n                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:228: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n      wb_user_core_read(`ADDR_SPACE_I2CM+(8\'h4<<2),read_data);  \n                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:232: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n    wb_user_core_write(`ADDR_SPACE_I2CM+(8\'h3<<2),8\'h21);  \n                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:233: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n    wb_user_core_write(`ADDR_SPACE_I2CM+(8\'h4<<2),8\'h90);  \n                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:236: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n      wb_user_core_read(`ADDR_SPACE_I2CM+(8\'h4<<2),read_data);  \n                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:239: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n    wb_user_core_write(`ADDR_SPACE_I2CM+(8\'h4<<2),8\'h20);   \n                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:243: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n      wb_user_core_read(`ADDR_SPACE_I2CM+(8\'h4<<2),read_data);  \n                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:246: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n    wb_user_core_read_cmp(`ADDR_SPACE_I2CM+(8\'h3<<2),8\'h12);  \n                          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:249: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n    wb_user_core_write(`ADDR_SPACE_I2CM+(8\'h4<<2),8\'h20);   \n                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:253: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n      wb_user_core_read(`ADDR_SPACE_I2CM+(8\'h4<<2),read_data);  \n                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_i2cm/user_i2cm_tb.v:256: Define or directive not defined: \'`ADDR_SPACE_I2CM\'\n    wb_user_core_read_cmp(`ADDR_SPACE_I2CM+(8\'h3<<2),8\'h34);  \n                          ^~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module tb_top;

reg            clock         ;
reg            wb_rst_i      ;
reg            power1, power2;
reg            power3, power4;

reg            wbd_ext_cyc_i;
reg            wbd_ext_stb_i;
reg [31:0]     wbd_ext_adr_i;
reg            wbd_ext_we_i;
reg [31:0]     wbd_ext_dat_i;
reg [3:0]      wbd_ext_sel_i;

wire [31:0]    wbd_ext_dat_o;
wire           wbd_ext_ack_o;
wire           wbd_ext_err_o;


wire [37:0]    io_oeb        ;
wire [37:0]    io_out        ;
wire [37:0]    io_in         ;

wire [37:0]    mprj_io       ;
wire [7:0]     mprj_io_0     ;
reg            test_fail     ;
reg [31:0]     read_data     ;




integer i,j;





	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
                wbd_ext_cyc_i ='h0;
                wbd_ext_stb_i ='h0;
                wbd_ext_adr_i ='h0;
                wbd_ext_we_i  ='h0;
                wbd_ext_dat_i ='h0;
                wbd_ext_sel_i ='h0;
	end

	`ifdef WFDUMP
	   initial begin
	   	$dumpfile("simx.vcd");
	   	$dumpvars(0, tb_top);
	   end
       `endif

	initial begin
		wb_rst_i <= 1'b1;
		#100;
		wb_rst_i <= 1'b0;
	end
initial
begin
   test_fail = 0;

   #200;
   repeat (10) @(posedge clock);
   $display("############################################");
   $display("   Testing I2CM Read/Write Access           ");
   $display("############################################");
   

   repeat (10) @(posedge clock);
   #1;

   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h01);


   wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h4000);


   wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h010);

   repeat (100) @(posedge clock);  

    @(posedge  clock);
    $display("---------- Initialize I2C Master ----------"); 


     wb_user_core_write(`ADDR_SPACE_I2CM+(8'h0<<2),8'hC7);  
     wb_user_core_write(`ADDR_SPACE_I2CM+(8'h1<<2),8'h00);  

     wb_user_core_write(`ADDR_SPACE_I2CM+(8'h2<<2),8'h80);  
    


    $display("---------- Writing Data ----------"); 
    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h3<<2),8'h20);
    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h90);  
    read_data[1] = 1'b1;
    while(read_data[1]==1)
      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  
     
    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h3<<2),8'h66);  
    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h10);  

    read_data[1] = 1'b1;
    while(read_data[1]==1)
      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  
   

    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h3<<2),8'h12);  
    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h10);

    read_data[1] = 1'b1;
    while(read_data[1]==1)
      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  
   

    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h3<<2),8'h34);  
    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h10);

    read_data[1] = 1'b1;
    while(read_data[1]==1)
      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  


    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h3<<2),8'h56);  
    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h10);

    read_data[1] = 1'b1;
    while(read_data[1]==1)
      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  


    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h3<<2),8'h78);  
    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h50);

    read_data[1] = 1'b1;
    while(read_data[1]==1)
      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  


    

    $display("---------- Writing Data ----------"); 
    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h3<<2),8'h20);  
    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h90);  
    read_data[1] = 1'b1;
    while(read_data[1]==1)
      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  
     
    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h3<<2),8'h66);  
    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h50);  

    read_data[1] = 1'b1;
    while(read_data[1]==1)
      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  


    $display("---------- Writing Data ----------"); 
    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h3<<2),8'h21);
    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h90);  
    read_data[1] = 1'b1;
    while(read_data[1]==1)
      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  


    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h20);

    read_data[1] = 1'b1;
    while(read_data[1]==1)
      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  


    wb_user_core_read_cmp(`ADDR_SPACE_I2CM+(8'h3<<2),8'h12);  
     

    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h20);

    read_data[1] = 1'b1;
    while(read_data[1]==1)
      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  


    wb_user_core_read_cmp(`ADDR_SPACE_I2CM+(8'h3<<2),8'h34);  


    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4 <<2),8'h20);

    read_data[1] = 1'b1;
    while(read_data[1]==1)
      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  


    wb_user_core_read_cmp(`ADDR_SPACE_I2CM+(8'h3<<2),8'h56);  


    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h68);

    read_data[1] = 1'b1;
    while(read_data[1]==1)
      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4 <<2),read_data);  


    wb_user_core_read_cmp(`ADDR_SPACE_I2CM+(8'h3 <<2),8'h78);  

    repeat(100)@(posedge clock);



     $display("###################################################");
     if(test_fail == 0) begin
        `ifdef GL
            $display("Monitor: Standalone User I2M Test (GL) Passed");
        `else
            $display("Monitor: Standalone User I2M Test (RTL) Passed");
        `endif
     end else begin
         `ifdef GL
             $display("Monitor: Standalone User I2M Test (GL) Failed");
         `else
             $display("Monitor: Standalone User I2M Test (RTL) Failed");
         `endif
      end
     $display("###################################################");
     #100
     $finish;
end


wire USER_VDD1V8 = 1'b1;
wire VSS = 1'b0;


user_project_wrapper u_top(
`ifdef USE_POWER_PINS
    .vccd1(USER_VDD1V8),
    .vssd1(VSS),
`endif
    .wb_clk_i        (clock),
    .user_clock2     (1'b1),
    .wb_rst_i        (wb_rst_i),

    .wbs_cyc_i   (wbd_ext_cyc_i),
    .wbs_stb_i   (wbd_ext_stb_i),
    .wbs_adr_i   (wbd_ext_adr_i),
    .wbs_we_i    (wbd_ext_we_i),
    .wbs_dat_i   (wbd_ext_dat_i),
    .wbs_sel_i   (wbd_ext_sel_i),

    .wbs_dat_o   (wbd_ext_dat_o),
    .wbs_ack_o   (wbd_ext_ack_o),

 

    .la_data_in      ('1) ,
    .la_data_out     (),
    .la_oenb         ('0),
 


    .io_in          (io_in)  ,
    .io_out         (io_out) ,
    .io_oeb         (io_oeb) ,

    .user_irq       () 

);

`ifndef GL

    initial begin

    end
`endif    




tri scl,sda;

assign sda  =  (io_oeb[22] == 1'b0) ? io_out[22] : 1'bz;
assign scl   = (io_oeb[23] == 1'b0) ? io_out[23]: 1'bz;
assign io_in[22]  =  sda;
assign io_in[23]  =  scl;

pullup p1(scl);
pullup p2(sda);

 
i2c_slave_model u_i2c_slave (
	.scl   (scl), 
	.sda   (sda)
       );


task wb_user_core_write;
input [31:0] address;
input [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h1;
  wbd_ext_dat_i =data;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read;
input [31:0] address;
output [31:0] data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(negedge clock);
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;

  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read_cmp;
input [31:0] address;
input [31:0] cmp_data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(negedge clock);
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  if(data !== cmp_data) begin
     $display("ERROR : WB USER ACCESS READ  Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
     test_fail = 1;
  end else begin
     $display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,data);
  end
  repeat (2) @(posedge clock);
end
endtask

`ifdef GL

wire        wbd_spi_stb_i   = u_top.u_qspi_master.wbd_stb_i;
wire        wbd_spi_ack_o   = u_top.u_qspi_master.wbd_ack_o;
wire        wbd_spi_we_i    = u_top.u_qspi_master.wbd_we_i;
wire [31:0] wbd_spi_adr_i   = u_top.u_qspi_master.wbd_adr_i;
wire [31:0] wbd_spi_dat_i   = u_top.u_qspi_master.wbd_dat_i;
wire [31:0] wbd_spi_dat_o   = u_top.u_qspi_master.wbd_dat_o;
wire [3:0]  wbd_spi_sel_i   = u_top.u_qspi_master.wbd_sel_i;

wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb_spi.reg_cs;
wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb_spi.reg_ack;
wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb_spi.reg_wr;
wire [8:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb_spi.reg_addr;
wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb_spi.reg_wdata;
wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb_spi.reg_rdata;
wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb_spi.reg_be;

`endif


endmodule
module tb_top;


reg            clock         ;
reg            wb_rst_i      ;
reg            power1, power2;
reg            power3, power4;

reg            wbd_ext_cyc_i;
reg            wbd_ext_stb_i;
reg [31:0]     wbd_ext_adr_i;
reg            wbd_ext_we_i;
reg [31:0]     wbd_ext_dat_i;
reg [3:0]      wbd_ext_sel_i;

wire [31:0]    wbd_ext_dat_o;
wire           wbd_ext_ack_o;
wire           wbd_ext_err_o;


wire [37:0]    io_oeb        ;
wire [37:0]    io_out        ;
wire [37:0]    io_in         ;

wire [37:0]    mprj_io       ;
wire [7:0]     mprj_io_0     ;
reg            test_fail     ;
reg [31:0]     read_data     ;




integer i,j;





	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
                wbd_ext_cyc_i ='h0;
                wbd_ext_stb_i ='h0;
                wbd_ext_adr_i ='h0;
                wbd_ext_we_i  ='h0;
                wbd_ext_dat_i ='h0;
                wbd_ext_sel_i ='h0;
	end

	`ifdef WFDUMP
	   initial begin
	   	$dumpfile("simx.vcd");
	   	$dumpvars(0, tb_top);
	   end
       `endif

	initial begin
		wb_rst_i <= 1'b1;
		#100;
		wb_rst_i <= 1'b0;
	end
initial
begin
   test_fail = 0;

   #200;
   repeat (10) @(posedge clock);
   $display("############################################");
   $display("   Testing I2CM Read/Write Access           ");
   $display("############################################");
   

   repeat (10) @(posedge clock);
   #1;

   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h01);


   wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h4000);


   wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h010);

   repeat (100) @(posedge clock);  

    @(posedge  clock);
    $display("---------- Initialize I2C Master ----------"); 


     wb_user_core_write(`ADDR_SPACE_I2CM+(8'h0<<2),8'hC7);  
     wb_user_core_write(`ADDR_SPACE_I2CM+(8'h1<<2),8'h00);  

     wb_user_core_write(`ADDR_SPACE_I2CM+(8'h2<<2),8'h80);  
    


    $display("---------- Writing Data ----------"); 
    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h3<<2),8'h20);
    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h90);  
    read_data[1] = 1'b1;
    while(read_data[1]==1)
      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  
     
    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h3<<2),8'h66);  
    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h10);  

    read_data[1] = 1'b1;
    while(read_data[1]==1)
      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  
   

    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h3<<2),8'h12);  
    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h10);

    read_data[1] = 1'b1;
    while(read_data[1]==1)
      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  
   

    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h3<<2),8'h34);  
    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h10);

    read_data[1] = 1'b1;
    while(read_data[1]==1)
      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  


    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h3<<2),8'h56);  
    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h10);

    read_data[1] = 1'b1;
    while(read_data[1]==1)
      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  


    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h3<<2),8'h78);  
    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h50);

    read_data[1] = 1'b1;
    while(read_data[1]==1)
      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  


    

    $display("---------- Writing Data ----------"); 
    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h3<<2),8'h20);  
    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h90);  
    read_data[1] = 1'b1;
    while(read_data[1]==1)
      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  
     
    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h3<<2),8'h66);  
    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h50);  

    read_data[1] = 1'b1;
    while(read_data[1]==1)
      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  


    $display("---------- Writing Data ----------"); 
    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h3<<2),8'h21);
    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h90);  
    read_data[1] = 1'b1;
    while(read_data[1]==1)
      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  


    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h20);

    read_data[1] = 1'b1;
    while(read_data[1]==1)
      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  


    wb_user_core_read_cmp(`ADDR_SPACE_I2CM+(8'h3<<2),8'h12);  
     

    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h20);

    read_data[1] = 1'b1;
    while(read_data[1]==1)
      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  


    wb_user_core_read_cmp(`ADDR_SPACE_I2CM+(8'h3<<2),8'h34);  


    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4 <<2),8'h20);

    read_data[1] = 1'b1;
    while(read_data[1]==1)
      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4<<2),read_data);  


    wb_user_core_read_cmp(`ADDR_SPACE_I2CM+(8'h3<<2),8'h56);  


    wb_user_core_write(`ADDR_SPACE_I2CM+(8'h4<<2),8'h68);

    read_data[1] = 1'b1;
    while(read_data[1]==1)
      wb_user_core_read(`ADDR_SPACE_I2CM+(8'h4 <<2),read_data);  


    wb_user_core_read_cmp(`ADDR_SPACE_I2CM+(8'h3 <<2),8'h78);  

    repeat(100)@(posedge clock);



     $display("###################################################");
     if(test_fail == 0) begin
        `ifdef GL
            $display("Monitor: Standalone User I2M Test (GL) Passed");
        `else
            $display("Monitor: Standalone User I2M Test (RTL) Passed");
        `endif
     end else begin
         `ifdef GL
             $display("Monitor: Standalone User I2M Test (GL) Failed");
         `else
             $display("Monitor: Standalone User I2M Test (RTL) Failed");
         `endif
      end
     $display("###################################################");
     #100
     $finish;
end


wire USER_VDD1V8 = 1'b1;
wire VSS = 1'b0;


user_project_wrapper u_top(
`ifdef USE_POWER_PINS
    .vccd1(USER_VDD1V8),
    .vssd1(VSS),
`endif
    .wb_clk_i        (clock),
    .user_clock2     (1'b1),
    .wb_rst_i        (wb_rst_i),

    .wbs_cyc_i   (wbd_ext_cyc_i),
    .wbs_stb_i   (wbd_ext_stb_i),
    .wbs_adr_i   (wbd_ext_adr_i),
    .wbs_we_i    (wbd_ext_we_i),
    .wbs_dat_i   (wbd_ext_dat_i),
    .wbs_sel_i   (wbd_ext_sel_i),

    .wbs_dat_o   (wbd_ext_dat_o),
    .wbs_ack_o   (wbd_ext_ack_o),

 

    .la_data_in      ('1) ,
    .la_data_out     (),
    .la_oenb         ('0),
 


    .io_in          (io_in)  ,
    .io_out         (io_out) ,
    .io_oeb         (io_oeb) ,

    .user_irq       () 

);

`ifndef GL

    initial begin

    end
`endif    




tri scl,sda;

assign sda  =  (io_oeb[22] == 1'b0) ? io_out[22] : 1'bz;
assign scl   = (io_oeb[23] == 1'b0) ? io_out[23]: 1'bz;
assign io_in[22]  =  sda;
assign io_in[23]  =  scl;

pullup p1(scl);
pullup p2(sda);

 
i2c_slave_model u_i2c_slave (
	.scl   (scl), 
	.sda   (sda)
       );


task wb_user_core_write;
input [31:0] address;
input [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h1;
  wbd_ext_dat_i =data;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read;
input [31:0] address;
output [31:0] data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(negedge clock);
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;

  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read_cmp;
input [31:0] address;
input [31:0] cmp_data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(negedge clock);
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  if(data !== cmp_data) begin
     $display("ERROR : WB USER ACCESS READ  Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
     test_fail = 1;
  end else begin
     $display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,data);
  end
  repeat (2) @(posedge clock);
end
endtask

`ifdef GL

wire        wbd_spi_stb_i   = u_top.u_qspi_master.wbd_stb_i;
wire        wbd_spi_ack_o   = u_top.u_qspi_master.wbd_ack_o;
wire        wbd_spi_we_i    = u_top.u_qspi_master.wbd_we_i;
wire [31:0] wbd_spi_adr_i   = u_top.u_qspi_master.wbd_adr_i;
wire [31:0] wbd_spi_dat_i   = u_top.u_qspi_master.wbd_dat_i;
wire [31:0] wbd_spi_dat_o   = u_top.u_qspi_master.wbd_dat_o;
wire [3:0]  wbd_spi_sel_i   = u_top.u_qspi_master.wbd_sel_i;

wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb_spi.reg_cs;
wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb_spi.reg_ack;
wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb_spi.reg_wr;
wire [8:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb_spi.reg_addr;
wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb_spi.reg_wdata;
wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb_spi.reg_rdata;
wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb_spi.reg_be;

`endif


endmodule