data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:118: Multiple top level modules\n                                                                                         : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                         : ... Top module \'rs_7_5_encoder\'\nmodule rs_7_5_encoder\n       ^~~~~~~~~~~~~~\n                                                                                         : ... Top module \'rs_7_5_decoder\'\nmodule rs_7_5_decoder\n       ^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:170: Operator ADD expects 32 bits on the RHS, but RHS\'s ARRAYSEL generates 3 bits.\n                                                                                      : ... In instance rs_7_5_decoder\n    S1_poly[idx] = (7 - idx) + GF_log[s[idx]];               \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:170: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                      : ... In instance rs_7_5_decoder\n    S1_poly[idx] = (7 - idx) + GF_log[s[idx]];               \n                 ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:171: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                      : ... In instance rs_7_5_decoder\n    S1_poly[idx] = S1_poly[idx][2:0] + S1_poly[idx][3];      \n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:172: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s ARRAYSEL generates 3 bits.\n                                                                                      : ... In instance rs_7_5_decoder\n    S1_poly[idx] = s[idx] ? GF_alog[S1_poly[idx]] : 3\'b000;  \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:172: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s ARRAYSEL generates 3 bits.\n                                                                                      : ... In instance rs_7_5_decoder\n    S1_poly[idx] = s[idx] ? GF_alog[S1_poly[idx]] : 3\'b000;  \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:172: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                      : ... In instance rs_7_5_decoder\n    S1_poly[idx] = s[idx] ? GF_alog[S1_poly[idx]] : 3\'b000;  \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:175: Operator XOR expects 4 bits on the LHS, but LHS\'s VARREF \'S1\' generates 3 bits.\n                                                                                      : ... In instance rs_7_5_decoder\n    S1           = S1 ^ S1_poly[idx];\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:175: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s XOR generates 4 bits.\n                                                                                      : ... In instance rs_7_5_decoder\n    S1           = S1 ^ S1_poly[idx];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:183: Operator SUB expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                      : ... In instance rs_7_5_decoder\n    k      = k[2:0] - k[3];                                  \n                    ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:184: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s ARRAYSEL generates 3 bits.\n                                                                                      : ... In instance rs_7_5_decoder\n    k      = (k == 4\'b0000) ? GF_log[3\'b001] : k;            \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:100: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                      : ... In instance rs_7_5_encoder\n    p_data[idx] = p_data[idx][2:0] + p_data[idx][3];  \n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:101: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 3 bits.\n                                                                                      : ... In instance rs_7_5_encoder\n    p_data[idx] = GF_alog[p_data[idx]];               \n                ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:102: Operator XOR expects 4 bits on the LHS, but LHS\'s VARREF \'P\' generates 3 bits.\n                                                                                      : ... In instance rs_7_5_encoder\n    P           = P ^ p_data[idx];                    \n                    ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:102: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s XOR generates 4 bits.\n                                                                                      : ... In instance rs_7_5_encoder\n    P           = P ^ p_data[idx];                    \n                ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:106: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                      : ... In instance rs_7_5_encoder\n    q_data[idx] = q_data[idx][2:0] + q_data[idx][3];  \n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:107: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 3 bits.\n                                                                                      : ... In instance rs_7_5_encoder\n    q_data[idx] = GF_alog[q_data[idx]];               \n                ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:108: Operator XOR expects 4 bits on the LHS, but LHS\'s VARREF \'Q\' generates 3 bits.\n                                                                                      : ... In instance rs_7_5_encoder\n    Q           = Q ^ q_data[idx];                    \n                    ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:108: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s XOR generates 4 bits.\n                                                                                      : ... In instance rs_7_5_encoder\n    Q           = Q ^ q_data[idx];                    \n                ^\n%Error: Exiting due to 19 warning(s)\n'
module rs_7_5_decoder
(
  input  [20:0] icode,
  output [14:0] odata
);

reg [2:0] s [0:6];

integer idx;
reg  [2:0] GF_log  [1:7];
reg  [2:0] GF_alog [1:7];
reg  [3:0] S1_poly [0:6];
reg  [3:0] k;
reg  [2:0] S0;
reg  [2:0] S1;

assign odata = {s[4], s[3], s[2], s[1], s[0]};

initial
begin

  GF_alog[1] = 3'b010; GF_alog[2] = 3'b100;
  GF_alog[3] = 3'b011; GF_alog[4] = 3'b110;
  GF_alog[5] = 3'b111; GF_alog[6] = 3'b101;
  GF_alog[7] = 3'b001;


  GF_log[1]  = 3'b111; GF_log[2]  = 3'b001;
  GF_log[3]  = 3'b011; GF_log[4]  = 3'b010;
  GF_log[5]  = 3'b110; GF_log[6]  = 3'b100;
  GF_log[7]  = 3'b101;
end

always @(icode)
begin

  s[0] = icode[2:0];
  s[1] = icode[5:3];
  s[2] = icode[8:6];
  s[3] = icode[11:9];
  s[4] = icode[14:12];
  s[5] = icode[17:15];
  s[6] = icode[20:18];


  S0   = s[0] ^ s[1] ^ s[2] ^ s[3] ^ s[4] ^ s[5] ^ s[6];


  S1   = 3'b000;

  for (idx = 0; idx < 7; idx = idx + 1)
  begin
    S1_poly[idx] = (7 - idx) + GF_log[s[idx]];
    S1_poly[idx] = S1_poly[idx][2:0] + S1_poly[idx][3];
    S1_poly[idx] = s[idx] ? GF_alog[S1_poly[idx]] : 3'b000;


    S1           = S1 ^ S1_poly[idx];
  end


  if (S0 != 3'b000)
  begin

    k      = GF_log[S1] - GF_log[S0];
    k      = k[2:0] - k[3];
    k      = (k == 4'b0000) ? GF_log[3'b001] : k;



    s[7-k] = s[7-k] ^ S0;
  end
end

endmodule
module rs_7_5_decoder
(
  input  [20:0] icode,
  output [14:0] odata
);


reg [2:0] s [0:6];

integer idx;
reg  [2:0] GF_log  [1:7];
reg  [2:0] GF_alog [1:7];
reg  [3:0] S1_poly [0:6];
reg  [3:0] k;
reg  [2:0] S0;
reg  [2:0] S1;

assign odata = {s[4], s[3], s[2], s[1], s[0]};

initial
begin

  GF_alog[1] = 3'b010; GF_alog[2] = 3'b100;
  GF_alog[3] = 3'b011; GF_alog[4] = 3'b110;
  GF_alog[5] = 3'b111; GF_alog[6] = 3'b101;
  GF_alog[7] = 3'b001;


  GF_log[1]  = 3'b111; GF_log[2]  = 3'b001;
  GF_log[3]  = 3'b011; GF_log[4]  = 3'b010;
  GF_log[5]  = 3'b110; GF_log[6]  = 3'b100;
  GF_log[7]  = 3'b101;
end

always @(icode)
begin

  s[0] = icode[2:0];
  s[1] = icode[5:3];
  s[2] = icode[8:6];
  s[3] = icode[11:9];
  s[4] = icode[14:12];
  s[5] = icode[17:15];
  s[6] = icode[20:18];


  S0   = s[0] ^ s[1] ^ s[2] ^ s[3] ^ s[4] ^ s[5] ^ s[6];


  S1   = 3'b000;

  for (idx = 0; idx < 7; idx = idx + 1)
  begin
    S1_poly[idx] = (7 - idx) + GF_log[s[idx]];
    S1_poly[idx] = S1_poly[idx][2:0] + S1_poly[idx][3];
    S1_poly[idx] = s[idx] ? GF_alog[S1_poly[idx]] : 3'b000;


    S1           = S1 ^ S1_poly[idx];
  end


  if (S0 != 3'b000)
  begin

    k      = GF_log[S1] - GF_log[S0];
    k      = k[2:0] - k[3];
    k      = (k == 4'b0000) ? GF_log[3'b001] : k;



    s[7-k] = s[7-k] ^ S0;
  end
end

endmodule