data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v
1: b'%Error: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:19: Define or directive not defined: \'`round_max\'\n    recFNToIN#(8,24,32) maxxCiel2int(.control(1\'b0),.in(maxx),.roundingMode(`round_max),.signedOut(1\'b1),.out(maxx_int),.intExceptionFlags());\n                                                                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:20: Define or directive not defined: \'`round_min\'\n    recFNToIN#(8,24,32) minxFloor2int(.control(1\'b0),.in(minx),.roundingMode(`round_min),.signedOut(1\'b1),.out(minx_int),.intExceptionFlags());\n                                                                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:21: Define or directive not defined: \'`round_max\'\n    recFNToIN#(8,24,32) maxyCiel2int(.control(1\'b0),.in(maxy),.roundingMode(`round_max),.signedOut(1\'b1),.out(maxy_int),.intExceptionFlags());\n                                                                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:22: Define or directive not defined: \'`round_min\'\n    recFNToIN#(8,24,32) minyFloor2int(.control(1\'b0),.in(miny),.roundingMode(`round_min),.signedOut(1\'b1),.out(miny_int),.intExceptionFlags());\n                                                                             ^~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:110: Unsupported: Ignoring delay on this delayed statement.\n        #10 \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:114: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:120: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:124: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:130: Unsupported: Ignoring delay on this delayed statement.\n        #10 \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:134: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:140: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:144: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:150: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:154: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:160: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:164: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Error: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:169: Unsupported or unknown PLI call: $dumpfile\n            $dumpfile("limitBB_tb.vcd");\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:170: Unsupported or unknown PLI call: $dumpvars\n            $dumpvars(0,limitBB_tb);\n            ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/src/bounding_box_traverser/boundingBoxGen.v:171: Unsupported: Ignoring delay on this delayed statement.\n            #1;\n            ^\n%Error: Exiting due to 6 error(s), 13 warning(s)\n'
module limitBB_tb();
    reg [31:0] resx, resy, maxx, minx,maxy,miny;
    wire [31:0] Top,Bottom,Left, Right;
    limitBB limitBB_inst(resx,resy, maxx,minx,maxy,miny, Top,Bottom,Left,Right);  
    initial begin
        $display("Starting");
        resx = 32'd1920;
        resy = 32'd1080;

        maxx = 32'd11;
        minx = 32'd4;
        maxy = 32'd14;
        miny = 32'd4;
        #10 
        if((Top == miny) && (Bottom == maxy) && (Left == minx) && (Right == maxx)) begin
            $display("basic tst passed");
        end
        #10

        maxx = 32'd1980;
        minx = 32'd4;
        maxy = 32'd14;
        miny = 32'd4;
        #10
        if((Top == miny) && (Bottom == maxy) && (Left == minx) && (Right == resx)) begin
            $display("right tst passed");
        end
        #10

        maxx = 32'd11;
        minx = 32'hFFFF_FFFC;
        maxy = 32'd14;
        miny = 32'd4;
        #10 
        if((Top == miny) && (Bottom == maxy) && (Left == 'b0) && (Right == maxx)) begin
            $display("left tst passed");
        end
        #10

        maxx = 32'd11;
        minx = 32'd4;
        maxy = 32'd14;
        miny = 32'hFFFF_FFFC;
        #10
        if((Top == 'b0) && (Bottom == maxy) && (Left == minx) && (Right == maxx)) begin
            $display("top tst passed");
        end
        #10

        maxx = 32'd11;
        minx = 32'd4;
        maxy = 32'd1090;
        miny = 32'd4;
        #10
        if((Top == miny) && (Bottom == resy) && (Left == minx) && (Right == maxx)) begin
            $display("bottom tst passed");
        end
        #10

        maxx = 32'd1980;
        minx = 32'hFFFF_FFFC;
        maxy = 32'd1090;
        miny = 32'hFFFF_FFFC;
        #10
        if((Top == 'b0) && (Bottom == resy) && (Left == 'b0) && (Right == resx)) begin
            $display("all tst passed");
        end
        #10
        $finish;
    end
    initial
        begin
            $dumpfile("limitBB_tb.vcd");
            $dumpvars(0,limitBB_tb);
            #1;
        end
    
endmodule
module limitBB_tb();

    reg [31:0] resx, resy, maxx, minx,maxy,miny;
    wire [31:0] Top,Bottom,Left, Right;
    limitBB limitBB_inst(resx,resy, maxx,minx,maxy,miny, Top,Bottom,Left,Right);  
    initial begin
        $display("Starting");
        resx = 32'd1920;
        resy = 32'd1080;

        maxx = 32'd11;
        minx = 32'd4;
        maxy = 32'd14;
        miny = 32'd4;
        #10 
        if((Top == miny) && (Bottom == maxy) && (Left == minx) && (Right == maxx)) begin
            $display("basic tst passed");
        end
        #10

        maxx = 32'd1980;
        minx = 32'd4;
        maxy = 32'd14;
        miny = 32'd4;
        #10
        if((Top == miny) && (Bottom == maxy) && (Left == minx) && (Right == resx)) begin
            $display("right tst passed");
        end
        #10

        maxx = 32'd11;
        minx = 32'hFFFF_FFFC;
        maxy = 32'd14;
        miny = 32'd4;
        #10 
        if((Top == miny) && (Bottom == maxy) && (Left == 'b0) && (Right == maxx)) begin
            $display("left tst passed");
        end
        #10

        maxx = 32'd11;
        minx = 32'd4;
        maxy = 32'd14;
        miny = 32'hFFFF_FFFC;
        #10
        if((Top == 'b0) && (Bottom == maxy) && (Left == minx) && (Right == maxx)) begin
            $display("top tst passed");
        end
        #10

        maxx = 32'd11;
        minx = 32'd4;
        maxy = 32'd1090;
        miny = 32'd4;
        #10
        if((Top == miny) && (Bottom == resy) && (Left == minx) && (Right == maxx)) begin
            $display("bottom tst passed");
        end
        #10

        maxx = 32'd1980;
        minx = 32'hFFFF_FFFC;
        maxy = 32'd1090;
        miny = 32'hFFFF_FFFC;
        #10
        if((Top == 'b0) && (Bottom == resy) && (Left == 'b0) && (Right == resx)) begin
            $display("all tst passed");
        end
        #10
        $finish;
    end
    initial
        begin
            $dumpfile("limitBB_tb.vcd");
            $dumpvars(0,limitBB_tb);
            #1;
        end
    
endmodule