data/full_repos/permissive/420117502/Basic/2_Freq_Divider/Freq_Divider_1.v
1: b'%Warning-WIDTH: data/full_repos/permissive/420117502/Basic/2_Freq_Divider/Freq_Divider_1.v:13: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                             : ... In instance FD\n        cnt<=1\'b1;\n           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/420117502/Basic/2_Freq_Divider/Freq_Divider_1.v:22: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                             : ... In instance FD\n            cnt<=1\'b1;\n               ^~\n%Error: Exiting due to 2 warning(s)\n'
module FD (
    input wire clk_in,
    input wire [31:0] N,
    output reg clk_out
);
    initial begin
        cnt<=1'b1;
        clk_out<='b0;
    end

    reg [31:0] cnt;
    always @(edge clk_in) begin
        if (cnt<N)begin
            cnt<=1'b1+cnt;
        end else begin
            cnt<=1'b1;
            clk_out<=~clk_out;
        end
    end
endmodule
module FD (
    input wire clk_in,
    input wire [31:0] N,
    output reg clk_out
);

    initial begin
        cnt<=1'b1;
        clk_out<='b0;
    end

    reg [31:0] cnt;
    always @(edge clk_in) begin
        if (cnt<N)begin
            cnt<=1'b1+cnt;
        end else begin
            cnt<=1'b1;
            clk_out<=~clk_out;
        end
    end
endmodule