data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_sstl_bscan.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_sstl_bscan.v:47: Cannot find file containing module: 'bw_io_jp_sstl_bscan'\nbw_io_jp_sstl_bscan bscan_input (\n^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_io_jp_sstl_bscan\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_io_jp_sstl_bscan.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_io_jp_sstl_bscan.sv\n             bw_io_jp_sstl_bscan\n             bw_io_jp_sstl_bscan.v\n             bw_io_jp_sstl_bscan.sv\n             obj_dir/bw_io_jp_sstl_bscan\n             obj_dir/bw_io_jp_sstl_bscan.v\n             obj_dir/bw_io_jp_sstl_bscan.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_sstl_bscan.v:56: Cannot find file containing module: 'bw_io_jp_sstl_oebscan'\nbw_io_jp_sstl_oebscan bscan_oe (\n^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_sstl_bscan.v:68: Cannot find file containing module: 'bw_u1_nor2_1x'\nbw_u1_nor2_1x odt_nor2 (\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_sstl_bscan.v:72: Cannot find file containing module: 'bw_io_jp_sstl_bscan'\nbw_io_jp_sstl_bscan bscan_output (\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_sstl_bscan.v:81: Cannot find file containing module: 'bw_io_jp_sstl_oebscan'\nbw_io_jp_sstl_oebscan bscan_odt_en (\n^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module bw_io_sstl_bscan(hiz_l ,odt_enable ,odt_enable_mask ,to_core ,
     drv_oe ,rcv_in ,data_out ,bso ,oe ,data_in ,mode_ctrl ,bsi ,
     clock_dr ,update_dr ,shift_dr );
output		odt_enable ;
output		to_core ;
output		data_out ;
output		bso ;
output		oe ;
input		hiz_l ;
input		odt_enable_mask ;
input		drv_oe ;
input		rcv_in ;
input		data_in ;
input		mode_ctrl ;
input		bsi ;
input		clock_dr ;
input		update_dr ;
input		shift_dr ;
supply0		vss ;
 
wire		bso_1 ;
wire		bso_2 ;
wire		bso_3 ;
wire		odt_enable_in ;
 
 
bw_io_jp_sstl_bscan bscan_input (
     .in              (rcv_in ),
     .update_dr       (update_dr ),
     .mode_ctl        (mode_ctrl ),
     .shift_dr        (shift_dr ),
     .clock_dr        (clock_dr ),
     .bsr_so          (bso_1 ),
     .out             (to_core ),
     .bsr_si          (bsi ) );
bw_io_jp_sstl_oebscan bscan_oe (
     .bsr_si          (bso_3 ),
     .update_dr       (update_dr ),
     .in              (drv_oe ),
     .bsr_hiz_l       (hiz_l ),
     .test_mode_oe    (vss ),
     .mode_ctl        (mode_ctrl ),
     .shift_dr        (shift_dr ),
     .clock_dr        (clock_dr ),
     .out_type        (vss ),
     .bsr_so          (bso ),
     .out             (oe ) );
bw_u1_nor2_1x odt_nor2 (
     .z               (odt_enable_in ),
     .a               (drv_oe ),
     .b               (odt_enable_mask ) );
bw_io_jp_sstl_bscan bscan_output (
     .in              (data_in ),
     .update_dr       (update_dr ),
     .mode_ctl        (mode_ctrl ),
     .shift_dr        (shift_dr ),
     .clock_dr        (clock_dr ),
     .bsr_so          (bso_3 ),
     .out             (data_out ),
     .bsr_si          (bso_2 ) );
bw_io_jp_sstl_oebscan bscan_odt_en (
     .bsr_si          (bso_1 ),
     .update_dr       (update_dr ),
     .in              (odt_enable_in ),
     .bsr_hiz_l       (hiz_l ),
     .test_mode_oe    (vss ),
     .mode_ctl        (mode_ctrl ),
     .shift_dr        (shift_dr ),
     .clock_dr        (clock_dr ),
     .out_type        (vss ),
     .bsr_so          (bso_2 ),
     .out             (odt_enable ) );
endmodule
module bw_io_sstl_bscan(hiz_l ,odt_enable ,odt_enable_mask ,to_core ,
     drv_oe ,rcv_in ,data_out ,bso ,oe ,data_in ,mode_ctrl ,bsi ,
     clock_dr ,update_dr ,shift_dr );

output		odt_enable ;
output		to_core ;
output		data_out ;
output		bso ;
output		oe ;
input		hiz_l ;
input		odt_enable_mask ;
input		drv_oe ;
input		rcv_in ;
input		data_in ;
input		mode_ctrl ;
input		bsi ;
input		clock_dr ;
input		update_dr ;
input		shift_dr ;
supply0		vss ;
 
wire		bso_1 ;
wire		bso_2 ;
wire		bso_3 ;
wire		odt_enable_in ;
 
 
bw_io_jp_sstl_bscan bscan_input (
     .in              (rcv_in ),
     .update_dr       (update_dr ),
     .mode_ctl        (mode_ctrl ),
     .shift_dr        (shift_dr ),
     .clock_dr        (clock_dr ),
     .bsr_so          (bso_1 ),
     .out             (to_core ),
     .bsr_si          (bsi ) );
bw_io_jp_sstl_oebscan bscan_oe (
     .bsr_si          (bso_3 ),
     .update_dr       (update_dr ),
     .in              (drv_oe ),
     .bsr_hiz_l       (hiz_l ),
     .test_mode_oe    (vss ),
     .mode_ctl        (mode_ctrl ),
     .shift_dr        (shift_dr ),
     .clock_dr        (clock_dr ),
     .out_type        (vss ),
     .bsr_so          (bso ),
     .out             (oe ) );
bw_u1_nor2_1x odt_nor2 (
     .z               (odt_enable_in ),
     .a               (drv_oe ),
     .b               (odt_enable_mask ) );
bw_io_jp_sstl_bscan bscan_output (
     .in              (data_in ),
     .update_dr       (update_dr ),
     .mode_ctl        (mode_ctrl ),
     .shift_dr        (shift_dr ),
     .clock_dr        (clock_dr ),
     .bsr_so          (bso_3 ),
     .out             (data_out ),
     .bsr_si          (bso_2 ) );
bw_io_jp_sstl_oebscan bscan_odt_en (
     .bsr_si          (bso_1 ),
     .update_dr       (update_dr ),
     .in              (odt_enable_in ),
     .bsr_hiz_l       (hiz_l ),
     .test_mode_oe    (vss ),
     .mode_ctl        (mode_ctrl ),
     .shift_dr        (shift_dr ),
     .clock_dr        (clock_dr ),
     .out_type        (vss ),
     .bsr_so          (bso_2 ),
     .out             (odt_enable ) );
endmodule