data/full_repos/permissive/423412549/src/rtl/dri_vga.v
1: b'%Error: data/full_repos/permissive/423412549/src/rtl/dri_vga.v:10: Cannot find include file: ../header/define.v\n`include "../header/define.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423412549/src/rtl,data/full_repos/permissive/423412549/../header/define.v\n             data/full_repos/permissive/423412549/src/rtl,data/full_repos/permissive/423412549/../header/define.v.v\n             data/full_repos/permissive/423412549/src/rtl,data/full_repos/permissive/423412549/../header/define.v.sv\n             ../header/define.v\n             ../header/define.v.v\n             ../header/define.v.sv\n             obj_dir/../header/define.v\n             obj_dir/../header/define.v.v\n             obj_dir/../header/define.v.sv\n%Error: data/full_repos/permissive/423412549/src/rtl/dri_vga.v:19: Define or directive not defined: \'`H_DISP_LEN\'\n        output wire [`H_DISP_LEN-1:0]   req_x_addr_o,\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/dri_vga.v:20: Define or directive not defined: \'`V_DISP_LEN\'\n        output wire [`V_DISP_LEN-1:0]   req_y_addr_o\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/dri_vga.v:23: Define or directive not defined: \'`H_BIT_LEN\'\n    reg  [ `H_BIT_LEN-1:0] h_cnt;\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/dri_vga.v:24: Define or directive not defined: \'`V_BIT_LEN\'\n    reg  [ `V_BIT_LEN-1:0] v_cnt;\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/dri_vga.v:25: Define or directive not defined: \'`H_DISP_LEN\'\n    wire [`H_DISP_LEN-1:0] req_x_addr;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/dri_vga.v:26: Define or directive not defined: \'`V_DISP_LEN\'\n    wire [`V_DISP_LEN-1:0] req_y_addr;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/dri_vga.v:35: Define or directive not defined: \'`H_SYNC\'\n    assign h_sync_o = ~(h_cnt < `H_SYNC);\n                                ^~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/dri_vga.v:35: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign h_sync_o = ~(h_cnt < `H_SYNC);\n                                       ^\n%Error: data/full_repos/permissive/423412549/src/rtl/dri_vga.v:36: Define or directive not defined: \'`V_SYNC\'\n    assign v_sync_o = ~(v_cnt < `V_SYNC);\n                                ^~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/dri_vga.v:36: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign v_sync_o = ~(v_cnt < `V_SYNC);\n                                       ^\n%Error: data/full_repos/permissive/423412549/src/rtl/dri_vga.v:45: Define or directive not defined: \'`H_TOTAL\'\n                if(h_cnt == `H_TOTAL - 1\'b1) begin\n                            ^~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/dri_vga.v:47: Define or directive not defined: \'`V_TOTAL\'\n                    if(v_cnt == `V_TOTAL - 1\'b1) begin\n                                ^~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/dri_vga.v:66: Define or directive not defined: \'`H_START\'\n    assign disp_o = (h_cnt >= `H_START) && (h_cnt < `H_END)\n                              ^~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/dri_vga.v:66: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign disp_o = (h_cnt >= `H_START) && (h_cnt < `H_END)\n                                      ^\n%Error: data/full_repos/permissive/423412549/src/rtl/dri_vga.v:66: Define or directive not defined: \'`H_END\'\n    assign disp_o = (h_cnt >= `H_START) && (h_cnt < `H_END)\n                                                    ^~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/dri_vga.v:67: Define or directive not defined: \'`V_START\'\n                                                                 : ... Suggested alternative: \'`SV_COV_START\'\n           && (v_cnt >= `V_START) && (v_cnt < `V_END);\n                        ^~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/dri_vga.v:67: Define or directive not defined: \'`V_END\'\n           && (v_cnt >= `V_START) && (v_cnt < `V_END);\n                                              ^~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/dri_vga.v:70: Define or directive not defined: \'`ROM_READ_DELAY\'\n    assign req_x_addr = h_cnt + `ROM_READ_DELAY - `H_START;\n                                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/dri_vga.v:70: Define or directive not defined: \'`H_START\'\n    assign req_x_addr = h_cnt + `ROM_READ_DELAY - `H_START;\n                                                  ^~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/dri_vga.v:70: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    assign req_x_addr = h_cnt + `ROM_READ_DELAY - `H_START;\n                                                          ^\n%Error: data/full_repos/permissive/423412549/src/rtl/dri_vga.v:71: Define or directive not defined: \'`V_START\'\n                                                                 : ... Suggested alternative: \'`SV_COV_START\'\n    assign req_y_addr = v_cnt - `V_START;\n                                ^~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/dri_vga.v:71: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    assign req_y_addr = v_cnt - `V_START;\n                                        ^\n%Error: data/full_repos/permissive/423412549/src/rtl/dri_vga.v:72: Define or directive not defined: \'`H_DISP\'\n    assign req = (req_x_addr >= 0) && (req_y_addr < `H_DISP);\n                                                    ^~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/dri_vga.v:72: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign req = (req_x_addr >= 0) && (req_y_addr < `H_DISP);\n                                                           ^\n%Error: Exiting due to 25 error(s)\n'
module dri_vga (
        input  wire                     clk,
        input  wire                     rst,
        input  wire                     en_i,

        output wire                     h_sync_o,
        output wire                     v_sync_o,
        output wire                     disp_o,
        output wire [`H_DISP_LEN-1:0]   req_x_addr_o,
        output wire [`V_DISP_LEN-1:0]   req_y_addr_o
    );

    reg  [ `H_BIT_LEN-1:0] h_cnt;
    reg  [ `V_BIT_LEN-1:0] v_cnt;
    wire [`H_DISP_LEN-1:0] req_x_addr;
    wire [`V_DISP_LEN-1:0] req_y_addr;
    wire                   req;

    initial begin
        h_cnt = 0;
        v_cnt = 0;
    end


    assign h_sync_o = ~(h_cnt < `H_SYNC);
    assign v_sync_o = ~(v_cnt < `V_SYNC);

    always @(posedge clk or posedge rst) begin
        if(rst) begin
            h_cnt <= 0;
            v_cnt <= 0;
        end
        else begin
            if(en_i) begin
                if(h_cnt == `H_TOTAL - 1'b1) begin
                    h_cnt <= 0;
                    if(v_cnt == `V_TOTAL - 1'b1) begin
                        v_cnt <= 0;
                    end
                    else begin
                        v_cnt <= v_cnt + 1;
                    end
                end
                else begin
                    h_cnt <= h_cnt + 1;
                end
            end
            else begin
                h_cnt <= 0;
                v_cnt <= 0;
            end
        end
    end


    assign disp_o = (h_cnt >= `H_START) && (h_cnt < `H_END)
           && (v_cnt >= `V_START) && (v_cnt < `V_END);


    assign req_x_addr = h_cnt + `ROM_READ_DELAY - `H_START;
    assign req_y_addr = v_cnt - `V_START;
    assign req = (req_x_addr >= 0) && (req_y_addr < `H_DISP);
    assign req_x_addr_o = req ? req_x_addr : 0;
    assign req_y_addr_o = req ? req_y_addr : 0;

endmodule
module dri_vga (
        input  wire                     clk,
        input  wire                     rst,
        input  wire                     en_i,

        output wire                     h_sync_o,
        output wire                     v_sync_o,
        output wire                     disp_o,
        output wire [`H_DISP_LEN-1:0]   req_x_addr_o,
        output wire [`V_DISP_LEN-1:0]   req_y_addr_o
    );


    reg  [ `H_BIT_LEN-1:0] h_cnt;
    reg  [ `V_BIT_LEN-1:0] v_cnt;
    wire [`H_DISP_LEN-1:0] req_x_addr;
    wire [`V_DISP_LEN-1:0] req_y_addr;
    wire                   req;

    initial begin
        h_cnt = 0;
        v_cnt = 0;
    end


    assign h_sync_o = ~(h_cnt < `H_SYNC);
    assign v_sync_o = ~(v_cnt < `V_SYNC);

    always @(posedge clk or posedge rst) begin
        if(rst) begin
            h_cnt <= 0;
            v_cnt <= 0;
        end
        else begin
            if(en_i) begin
                if(h_cnt == `H_TOTAL - 1'b1) begin
                    h_cnt <= 0;
                    if(v_cnt == `V_TOTAL - 1'b1) begin
                        v_cnt <= 0;
                    end
                    else begin
                        v_cnt <= v_cnt + 1;
                    end
                end
                else begin
                    h_cnt <= h_cnt + 1;
                end
            end
            else begin
                h_cnt <= 0;
                v_cnt <= 0;
            end
        end
    end


    assign disp_o = (h_cnt >= `H_START) && (h_cnt < `H_END)
           && (v_cnt >= `V_START) && (v_cnt < `V_END);


    assign req_x_addr = h_cnt + `ROM_READ_DELAY - `H_START;
    assign req_y_addr = v_cnt - `V_START;
    assign req = (req_x_addr >= 0) && (req_y_addr < `H_DISP);
    assign req_x_addr_o = req ? req_x_addr : 0;
    assign req_y_addr_o = req ? req_y_addr : 0;

endmodule