data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/pfpu_marocchino/pfpu_marocchino_f2i.v
1: b'%Error: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/pfpu_marocchino/pfpu_marocchino_f2i.v:40: Cannot find include file: or1k_defines.v\n`include "or1k_defines.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/pfpu_marocchino,data/full_repos/permissive/447681894/or1k_defines.v\n             data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/pfpu_marocchino,data/full_repos/permissive/447681894/or1k_defines.v.v\n             data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/pfpu_marocchino,data/full_repos/permissive/447681894/or1k_defines.v.sv\n             or1k_defines.v\n             or1k_defines.v.v\n             or1k_defines.v.sv\n             obj_dir/or1k_defines.v\n             obj_dir/or1k_defines.v.v\n             obj_dir/or1k_defines.v.sv\n%Error: Exiting due to 1 error(s)\n'
module pfpu_marocchino_f2i
(

  input             cpu_clk,

  input             pipeline_flush_i,
  input             start_i,
  output            f2i_taking_op_o,
  output reg        f2i_rdy_o,
  input             rnd_taking_f2i_i,

  input             signa_i,
  input      [12:0] exp13a_i,
  input      [52:0] fract53a_i,
  input             exec_op_fp64_arith_i,
  input             snan_i,
  input             qnan_i,

  output reg        f2i_sign_o,
  output reg [52:0] f2i_int53_o,
  output reg  [5:0] f2i_shr_o,
  output reg  [3:0] f2i_shl_o,
  output reg        f2i_ovf_o
);






  reg  s0o_ready, s0o_pending;

  wire s1_busy = f2i_rdy_o & ~rnd_taking_f2i_i;
  wire s0_busy = s0o_ready & s0o_pending;

  wire s0_adv  = start_i                   & ~s0_busy;
  wire s1_adv  = (s0o_ready | s0o_pending) & ~s1_busy;


  assign f2i_taking_op_o = s0_adv;




  reg         s0o_signa;
  reg  [12:0] s0o_exp13a;
  reg  [52:0] s0o_fract53a;
  reg         s0o_op_fp64_arith;
  reg         s0o_snan;
  reg         s0o_qnan;


  always @(posedge cpu_clk) begin
    if (s0_adv) begin
      s0o_signa    <= signa_i;
      s0o_exp13a   <= exp13a_i;
      s0o_fract53a <= fract53a_i;
      s0o_op_fp64_arith <= exec_op_fp64_arith_i;
      s0o_snan     <= snan_i;
      s0o_qnan     <= qnan_i;
    end
  end


  always @(posedge cpu_clk) begin
    if (pipeline_flush_i)
      s0o_ready <= 1'b0;
    else if (s0_adv)
      s0o_ready <= 1'b1;
    else if (s1_adv)
      s0o_ready <= s0_busy;
    else if (~s0o_pending)
      s0o_ready <= 1'b0;
  end


  always @(posedge cpu_clk) begin
    if (pipeline_flush_i)
      s0o_pending <= 1'b0;
    else if (s1_adv)
      s0o_pending <= 1'b0;
    else if (~s0o_pending)
      s0o_pending <= s0o_ready;
  end








  wire [12:0] s1t_exp13m = s0o_exp13a + (s0o_op_fp64_arith ? 13'h1bcd : 13'h1f6a);


  wire [12:0] s1t_shr_t = {13{s1t_exp13m[12]}} &
                          ((s0o_op_fp64_arith ? 13'd1075 : 13'd150) - s0o_exp13a);

  wire  [5:0] s1t_shr = s1t_shr_t[5:0] | {6{|s1t_shr_t[12:6]}};



  wire [3:0] s1t_shl = {4{~s1t_exp13m[12]}} & (s1t_exp13m[3:0] | {4{|s1t_exp13m[12:4]}});



  wire s1t_is_shl_gt11 = (s1t_shl  > (s0o_op_fp64_arith ? 4'd11 : 4'd8));
  wire s1t_is_shl_eq11 = (s1t_shl == (s0o_op_fp64_arith ? 4'd11 : 4'd8));
  wire s1t_is_shl_ovf =
     s1t_is_shl_gt11 |
    (s1t_is_shl_eq11 & (~s0o_signa)) |
    (s1t_is_shl_eq11 &   s0o_signa & (|s0o_fract53a[51:0]));



  reg         f2i_sign_p;
  wire        f2i_sign_w;
  reg  [52:0] f2i_int53_p;
  wire [52:0] f2i_int53_m;
  reg   [5:0] f2i_shr_p;
  reg   [3:0] f2i_shl_p;
  reg         f2i_ovf_p;



  assign f2i_sign_w  = s0o_signa & (~(s0o_qnan | s0o_snan));
  assign f2i_int53_m = s0o_op_fp64_arith ? (s0o_fract53a) : ({29'd0,s0o_fract53a[52:29]});


  always @(posedge cpu_clk) begin
    if (~s0o_pending) begin
      f2i_sign_p  <= f2i_sign_w;
      f2i_int53_p <= f2i_int53_m;
      f2i_shr_p   <= s1t_shr;
      f2i_shl_p   <= s1t_shl;
      f2i_ovf_p   <= s1t_is_shl_ovf;
    end
  end


  always @(posedge cpu_clk) begin
    if (s1_adv) begin
      f2i_sign_o  <= s0o_pending ? f2i_sign_p  : f2i_sign_w;
      f2i_int53_o <= s0o_pending ? f2i_int53_p : f2i_int53_m;
      f2i_shr_o   <= s0o_pending ? f2i_shr_p   : s1t_shr;
      f2i_shl_o   <= s0o_pending ? f2i_shl_p   : s1t_shl;
      f2i_ovf_o   <= s0o_pending ? f2i_ovf_p   : s1t_is_shl_ovf;
    end
  end


  always @(posedge cpu_clk) begin
    if (pipeline_flush_i)
      f2i_rdy_o <= 1'b0;
    else if (s1_adv)
      f2i_rdy_o <= 1'b1;
    else if (rnd_taking_f2i_i)
      f2i_rdy_o <= 1'b0;
  end

endmodule
module pfpu_marocchino_f2i
(

  input             cpu_clk,

  input             pipeline_flush_i,
  input             start_i,
  output            f2i_taking_op_o,
  output reg        f2i_rdy_o,
  input             rnd_taking_f2i_i,

  input             signa_i,
  input      [12:0] exp13a_i,
  input      [52:0] fract53a_i,
  input             exec_op_fp64_arith_i,
  input             snan_i,
  input             qnan_i,

  output reg        f2i_sign_o,
  output reg [52:0] f2i_int53_o,
  output reg  [5:0] f2i_shr_o,
  output reg  [3:0] f2i_shl_o,
  output reg        f2i_ovf_o
);







  reg  s0o_ready, s0o_pending;

  wire s1_busy = f2i_rdy_o & ~rnd_taking_f2i_i;
  wire s0_busy = s0o_ready & s0o_pending;

  wire s0_adv  = start_i                   & ~s0_busy;
  wire s1_adv  = (s0o_ready | s0o_pending) & ~s1_busy;


  assign f2i_taking_op_o = s0_adv;




  reg         s0o_signa;
  reg  [12:0] s0o_exp13a;
  reg  [52:0] s0o_fract53a;
  reg         s0o_op_fp64_arith;
  reg         s0o_snan;
  reg         s0o_qnan;


  always @(posedge cpu_clk) begin
    if (s0_adv) begin
      s0o_signa    <= signa_i;
      s0o_exp13a   <= exp13a_i;
      s0o_fract53a <= fract53a_i;
      s0o_op_fp64_arith <= exec_op_fp64_arith_i;
      s0o_snan     <= snan_i;
      s0o_qnan     <= qnan_i;
    end
  end


  always @(posedge cpu_clk) begin
    if (pipeline_flush_i)
      s0o_ready <= 1'b0;
    else if (s0_adv)
      s0o_ready <= 1'b1;
    else if (s1_adv)
      s0o_ready <= s0_busy;
    else if (~s0o_pending)
      s0o_ready <= 1'b0;
  end


  always @(posedge cpu_clk) begin
    if (pipeline_flush_i)
      s0o_pending <= 1'b0;
    else if (s1_adv)
      s0o_pending <= 1'b0;
    else if (~s0o_pending)
      s0o_pending <= s0o_ready;
  end








  wire [12:0] s1t_exp13m = s0o_exp13a + (s0o_op_fp64_arith ? 13'h1bcd : 13'h1f6a);


  wire [12:0] s1t_shr_t = {13{s1t_exp13m[12]}} &
                          ((s0o_op_fp64_arith ? 13'd1075 : 13'd150) - s0o_exp13a);

  wire  [5:0] s1t_shr = s1t_shr_t[5:0] | {6{|s1t_shr_t[12:6]}};



  wire [3:0] s1t_shl = {4{~s1t_exp13m[12]}} & (s1t_exp13m[3:0] | {4{|s1t_exp13m[12:4]}});



  wire s1t_is_shl_gt11 = (s1t_shl  > (s0o_op_fp64_arith ? 4'd11 : 4'd8));
  wire s1t_is_shl_eq11 = (s1t_shl == (s0o_op_fp64_arith ? 4'd11 : 4'd8));
  wire s1t_is_shl_ovf =
     s1t_is_shl_gt11 |
    (s1t_is_shl_eq11 & (~s0o_signa)) |
    (s1t_is_shl_eq11 &   s0o_signa & (|s0o_fract53a[51:0]));



  reg         f2i_sign_p;
  wire        f2i_sign_w;
  reg  [52:0] f2i_int53_p;
  wire [52:0] f2i_int53_m;
  reg   [5:0] f2i_shr_p;
  reg   [3:0] f2i_shl_p;
  reg         f2i_ovf_p;



  assign f2i_sign_w  = s0o_signa & (~(s0o_qnan | s0o_snan));
  assign f2i_int53_m = s0o_op_fp64_arith ? (s0o_fract53a) : ({29'd0,s0o_fract53a[52:29]});


  always @(posedge cpu_clk) begin
    if (~s0o_pending) begin
      f2i_sign_p  <= f2i_sign_w;
      f2i_int53_p <= f2i_int53_m;
      f2i_shr_p   <= s1t_shr;
      f2i_shl_p   <= s1t_shl;
      f2i_ovf_p   <= s1t_is_shl_ovf;
    end
  end


  always @(posedge cpu_clk) begin
    if (s1_adv) begin
      f2i_sign_o  <= s0o_pending ? f2i_sign_p  : f2i_sign_w;
      f2i_int53_o <= s0o_pending ? f2i_int53_p : f2i_int53_m;
      f2i_shr_o   <= s0o_pending ? f2i_shr_p   : s1t_shr;
      f2i_shl_o   <= s0o_pending ? f2i_shl_p   : s1t_shl;
      f2i_ovf_o   <= s0o_pending ? f2i_ovf_p   : s1t_is_shl_ovf;
    end
  end


  always @(posedge cpu_clk) begin
    if (pipeline_flush_i)
      f2i_rdy_o <= 1'b0;
    else if (s1_adv)
      f2i_rdy_o <= 1'b1;
    else if (rnd_taking_f2i_i)
      f2i_rdy_o <= 1'b0;
  end

endmodule