data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_mem_app_bridge.v
1: b'%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_mem_app_bridge.v:3: Cannot find include file: noc_parameter.vh\n    `include "noc_parameter.vh" \n             ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh\n             data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.v\n             data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.sv\n             noc_parameter.vh\n             noc_parameter.vh.v\n             noc_parameter.vh.sv\n             obj_dir/noc_parameter.vh\n             obj_dir/noc_parameter.vh.v\n             obj_dir/noc_parameter.vh.sv\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_mem_app_bridge.v:4: Cannot find include file: ddr4_user_parameter.vh\n    ,`include "ddr4_user_parameter.vh" \n              ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_mem_app_bridge.v:5: Cannot find include file: tcu_parameter.vh\n    ,`include "tcu_parameter.vh" \n              ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_mem_app_bridge.v:4: syntax error, unexpected \',\', expecting \'[\'\n    , \n    ^\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_mem_app_bridge.v:9: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                             mem_reset_n_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_mem_app_bridge.v:12: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                             mem_en_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_mem_app_bridge.v:13: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                             mem_req_i,           \n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_mem_app_bridge.v:14: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire     [TCU_MEM_BSEL_SIZE-1:0] mem_wben_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_mem_app_bridge.v:15: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire     [TCU_MEM_ADDR_SIZE-1:0] mem_addr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_mem_app_bridge.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire     [TCU_MEM_DATA_SIZE-1:0] mem_wdata_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_mem_app_bridge.v:17: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire     [TCU_MEM_DATA_SIZE-1:0] mem_rdata_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_mem_app_bridge.v:18: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                             mem_rdata_avail_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_mem_app_bridge.v:19: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                             mem_wstall_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_mem_app_bridge.v:20: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                             mem_rstall_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_mem_app_bridge.v:21: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                             mem_access_i,        \n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_mem_app_bridge.v:24: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg    [DDR4_APP_ADDR_WIDTH-1:0] ddr4_app_addr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_mem_app_bridge.v:25: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg     [DDR4_APP_CMD_WIDTH-1:0] ddr4_app_cmd_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_mem_app_bridge.v:26: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg                              ddr4_app_en_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_mem_app_bridge.v:27: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output wire   [DDR4_APP_DATA_WIDTH-1:0] ddr4_app_wdf_data_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_mem_app_bridge.v:28: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                              ddr4_app_wdf_end_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_mem_app_bridge.v:29: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output wire [DDR4_APP_DATA_WIDTH/8-1:0] ddr4_app_wdf_mask_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_mem_app_bridge.v:30: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                              ddr4_app_wdf_wren_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_mem_app_bridge.v:32: syntax error, unexpected input, expecting IDENTIFIER or \'=\' or do or final\n    input  wire   [DDR4_APP_DATA_WIDTH-1:0] ddr4_app_rd_data_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_mem_app_bridge.v:33: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                             ddr4_app_rd_data_end_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_mem_app_bridge.v:34: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                             ddr4_app_rd_data_valid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_mem_app_bridge.v:35: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                             ddr4_app_rdy_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_mem_app_bridge.v:36: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                             ddr4_app_wdf_rdy_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_mem_app_bridge.v:38: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire      [DDR4_STATUS_SIZE-1:0] ddr4_status_o\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_mem_app_bridge.v:39: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/463204869/units/ddr4/source/rtl/verilog/ddr4_mem_app_bridge.v:196: syntax error, unexpected IDENTIFIER\n    mem_tp_wrap #(\n    ^~~~~~~~~~~\n%Error: Exiting due to 30 error(s)\n'
function [TCU_MEM_DATA_SIZE-1:0] sel_data512;
        input [1:0] addr;
        input [DDR4_APP_DATA_CUT_WIDTH-1:0] data;
        begin
            case(addr)
                2'd0: sel_data512 = data[  TCU_MEM_DATA_SIZE-1 :                   0];
                2'd1: sel_data512 = data[2*TCU_MEM_DATA_SIZE-1 :   TCU_MEM_DATA_SIZE];
                2'd2: sel_data512 = data[3*TCU_MEM_DATA_SIZE-1 : 2*TCU_MEM_DATA_SIZE];
                2'd3: sel_data512 = data[4*TCU_MEM_DATA_SIZE-1 : 3*TCU_MEM_DATA_SIZE];
            endcase
        end
    endfunction
function [TCU_MEM_DATA_SIZE-1:0] sel_data512;

        input [1:0] addr;
        input [DDR4_APP_DATA_CUT_WIDTH-1:0] data;
        begin
            case(addr)
                2'd0: sel_data512 = data[  TCU_MEM_DATA_SIZE-1 :                   0];
                2'd1: sel_data512 = data[2*TCU_MEM_DATA_SIZE-1 :   TCU_MEM_DATA_SIZE];
                2'd2: sel_data512 = data[3*TCU_MEM_DATA_SIZE-1 : 2*TCU_MEM_DATA_SIZE];
                2'd3: sel_data512 = data[4*TCU_MEM_DATA_SIZE-1 : 3*TCU_MEM_DATA_SIZE];
            endcase
        end
    endfunction