data/full_repos/permissive/419538859/lab1_5/lab1_5.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/419538859/lab1_5/lab1_5.v:9: Signal definition not found, creating implicitly: \'clk_work1\'\nfreq_div#(20)red (clk, reset, clk_work1); \n                              ^~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/419538859/lab1_5/lab1_5.v:10: Signal definition not found, creating implicitly: \'clk_work2\'\n                                                                          : ... Suggested alternative: \'clk_work1\'\nfreq_div#(23)green (clk, reset, clk_work2); \n                                ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/419538859/lab1_5/lab1_5.v:11: Signal definition not found, creating implicitly: \'clk_work\'\n                                                                          : ... Suggested alternative: \'clk_work1\'\nlab01_4 M2 (clk_work, reset, shift_red,shift_green,w1);\n            ^~~~~~~~\n%Warning-SELRANGE: data/full_repos/permissive/419538859/lab1_5/lab1_5.v:21: Selection index out of range: 8 outside 7:0\n                                                                          : ... In instance lab1_5.M2\nassign shift_red=pattern[8]?{8\'b00000000}:(pattern[7:0]); \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab1_5/lab1_5.v:21: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s VARREF \'pattern\' generates 1 bits.\n                                                                       : ... In instance lab1_5.M2\nassign shift_red=pattern[8]?{8\'b00000000}:(pattern[7:0]); \n                           ^\n%Warning-SELRANGE: data/full_repos/permissive/419538859/lab1_5/lab1_5.v:22: Selection index out of range: 8 outside 7:0\n                                                                          : ... In instance lab1_5.M2\nassign shift_green=pattern[8]?(pattern[7:0]):{8\'b00000000};  \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab1_5/lab1_5.v:22: Operator COND expects 8 bits on the Conditional True, but Conditional True\'s VARREF \'pattern\' generates 1 bits.\n                                                                       : ... In instance lab1_5.M2\nassign shift_green=pattern[8]?(pattern[7:0]):{8\'b00000000};  \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab1_5/lab1_5.v:26: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'he0\' generates 9 bits.\n                                                                       : ... In instance lab1_5.M2\npattern = 9\'b0_1110_0000;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab1_5/lab1_5.v:29: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h70\' generates 9 bits.\n                                                                       : ... In instance lab1_5.M2\n  9\'b0_11100000:pattern = 9\'b0_01110000;   \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab1_5/lab1_5.v:30: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h38\' generates 9 bits.\n                                                                       : ... In instance lab1_5.M2\n  9\'b0_01110000:pattern = 9\'b0_00111000; \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab1_5/lab1_5.v:31: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h1c\' generates 9 bits.\n                                                                       : ... In instance lab1_5.M2\n  9\'b0_00111000:pattern = 9\'b0_00011100;  \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab1_5/lab1_5.v:32: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'he\' generates 9 bits.\n                                                                       : ... In instance lab1_5.M2\n  9\'b0_00011100:pattern = 9\'b0_00001110;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab1_5/lab1_5.v:33: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h7\' generates 9 bits.\n                                                                       : ... In instance lab1_5.M2\n  9\'b0_00001110:pattern = 9\'b0_00000111;  \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab1_5/lab1_5.v:34: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h10e\' generates 9 bits.\n                                                                       : ... In instance lab1_5.M2\n  9\'b0_00000111:pattern = 9\'b1_00001110;  \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab1_5/lab1_5.v:35: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h11c\' generates 9 bits.\n                                                                       : ... In instance lab1_5.M2\n  9\'b1_00001110:pattern = 9\'b1_00011100;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab1_5/lab1_5.v:36: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h138\' generates 9 bits.\n                                                                       : ... In instance lab1_5.M2\n  9\'b1_00011100:pattern = 9\'b1_00111000;  \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab1_5/lab1_5.v:37: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h170\' generates 9 bits.\n                                                                       : ... In instance lab1_5.M2\n  9\'b1_00111000:pattern = 9\'b1_01110000;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab1_5/lab1_5.v:38: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h1e0\' generates 9 bits.\n                                                                       : ... In instance lab1_5.M2\n  9\'b1_01110000:pattern = 9\'b1_11100000;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab1_5/lab1_5.v:39: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'h70\' generates 9 bits.\n                                                                       : ... In instance lab1_5.M2\n  9\'b1_11100000:pattern = 9\'b0_01110000;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab1_5/lab1_5.v:40: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'9\'he0\' generates 9 bits.\n                                                                       : ... In instance lab1_5.M2\ndefault:pattern = 9\'b0_11100000;endcase\n                ^\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab1_5/lab1_5.v:28: Operator CASE expects 9 bits on the Case expression, but Case expression\'s VARREF \'pattern\' generates 1 bits.\n                                                                       : ... In instance lab1_5.M2\ncase(pattern)\n^~~~\n%Error: Exiting due to 21 warning(s)\n'
module lab1_5 (clk, reset, shift_red,shift_green, ctl_bit);
input clk;
input reset;
wire	w1;
output[7:0]shift_red;
output[7:0]shift_green;
output ctl_bit;
assign ctl_bit= 1'b1;
freq_div#(20)red (clk, reset, clk_work1); 
freq_div#(23)green (clk, reset, clk_work2); 
lab01_4 M2 (clk_work, reset, shift_red,shift_green,w1);
assign	clk_work=w1?clk_work2:clk_work1;
endmodule
module lab1_5 (clk, reset, shift_red,shift_green, ctl_bit);

input clk;
input reset;
wire	w1;
output[7:0]shift_red;
output[7:0]shift_green;
output ctl_bit;
assign ctl_bit= 1'b1;
freq_div#(20)red (clk, reset, clk_work1); 
freq_div#(23)green (clk, reset, clk_work2); 
lab01_4 M2 (clk_work, reset, shift_red,shift_green,w1);
assign	clk_work=w1?clk_work2:clk_work1;
endmodule