data/full_repos/permissive/446997925/hw3/and.v
data/verilator_xmls/e2b82ace-9d56-43df-a68f-94f4fe8a4f8c.xml
module and_2(out, a, b);
input [1:0] a, b;
output [1:0] out;

and f(out[0], a[0], b[0]),
    s(out[1], a[1], b[1]);
endmodule
module and_2(out, a, b);

input [1:0] a, b;
output [1:0] out;

and f(out[0], a[0], b[0]),
    s(out[1], a[1], b[1]);
endmodule