data/full_repos/permissive/515100461/ALU/And.v
data/verilator_xmls/bda393a9-c9a9-453d-a451-2d5771603dc3.xml
module And(A,B,OUT);

    input signed [63:0]A,B;
    output signed [63:0] OUT;
 

    genvar i;

    generate for(i=0;i<64;i=i+1)
        begin

            and G1(OUT[i],A[i],B[i]);            

        end
    endgenerate
    
    
endmodule
module And(A,B,OUT);


    input signed [63:0]A,B;
    output signed [63:0] OUT;
 

    genvar i;

    generate for(i=0;i<64;i=i+1)
        begin

            and G1(OUT[i],A[i],B[i]);            

        end
    endgenerate
    
    
endmodule