data/full_repos/permissive/497819211/03/DFF.v
data/verilator_xmls/568b5d2a-fb20-4590-b288-0594b7d45cbf.xml
module DFFusr(
		input wire clk,
		input wire in,
		output reg out
);
	always @(negedge clk)
		if (in) out <= 1'b1;
		else out <= 1'b0;

endmodule
module DFFusr(
		input wire clk,
		input wire in,
		output reg out
);

	always @(negedge clk)
		if (in) out <= 1'b1;
		else out <= 1'b0;

endmodule