data/full_repos/permissive/497530416/pipe/ADD_SUB/add_64bit_test.v
1: b'%Error: data/full_repos/permissive/497530416/pipe/ADD_SUB/add_64bit_test.v:14: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("add_64_bit_test.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/497530416/pipe/ADD_SUB/add_64bit_test.v:15: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, test_add_64bit);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/497530416/pipe/ADD_SUB/add_64bit_test.v:21: Unsupported or unknown PLI call: $monitor\n        $monitor("time: %0d\\n a  : %b\\t%d\\n b  : %b\\t%d\\n sum: %b\\t%d\\n overflow=%b\\n ", $time, a,a,b,b,sum,sum, OF);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/497530416/pipe/ADD_SUB/add_64bit_test.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #5 a=64\'d2811; b= 64\'d1012;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/497530416/pipe/ADD_SUB/add_64bit_test.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #5 a=-64\'d1243; b= 64\'d1234;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497530416/pipe/ADD_SUB/add_64bit_test.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #5 a=-64\'d7478; b=-64\'d46474;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497530416/pipe/ADD_SUB/add_64bit_test.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #5 a = 64\'d1092835; b = -64\'d1020;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497530416/pipe/ADD_SUB/add_64bit_test.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #5 a = 64\'d7890678653; b = 64\'d4238598110567;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497530416/pipe/ADD_SUB/add_64bit_test.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #5 a = 64\'b0111111111111111111111111111111111111111111111111111111111111111; b = 64\'d1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/497530416/pipe/ADD_SUB/add_64bit_test.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #5 a = -64\'d9223372036854770000; b=-64\'d6000;\n        ^\n%Error: Exiting due to 3 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_add_64bit();

reg signed [63:0] a;
reg signed [63:0] b;
reg m;

wire signed [63:0] sum;
wire OF;

add_sub_64bit Adder64(a,b,sum,m,OF);

initial
    begin
        $dumpfile("add_64_bit_test.vcd");
        $dumpvars(0, test_add_64bit);
        a = 64'b0;
        b = 64'b0;
        m = 0;
        

        $monitor("time: %0d\n a  : %b\t%d\n b  : %b\t%d\n sum: %b\t%d\n overflow=%b\n ", $time, a,a,b,b,sum,sum, OF);


        #5 a=64'd2811; b= 64'd1012;
        #5 a=-64'd1243; b= 64'd1234;
        #5 a=-64'd7478; b=-64'd46474;
        #5 a = 64'd1092835; b = -64'd1020;
        #5 a = 64'd7890678653; b = 64'd4238598110567;

        #5 a = 64'b0111111111111111111111111111111111111111111111111111111111111111; b = 64'd1;
        
        #5 a = -64'd9223372036854770000; b=-64'd6000;

        

    end
endmodule
module test_add_64bit();


reg signed [63:0] a;
reg signed [63:0] b;
reg m;

wire signed [63:0] sum;
wire OF;

add_sub_64bit Adder64(a,b,sum,m,OF);

initial
    begin
        $dumpfile("add_64_bit_test.vcd");
        $dumpvars(0, test_add_64bit);
        a = 64'b0;
        b = 64'b0;
        m = 0;
        

        $monitor("time: %0d\n a  : %b\t%d\n b  : %b\t%d\n sum: %b\t%d\n overflow=%b\n ", $time, a,a,b,b,sum,sum, OF);


        #5 a=64'd2811; b= 64'd1012;
        #5 a=-64'd1243; b= 64'd1234;
        #5 a=-64'd7478; b=-64'd46474;
        #5 a = 64'd1092835; b = -64'd1020;
        #5 a = 64'd7890678653; b = 64'd4238598110567;

        #5 a = 64'b0111111111111111111111111111111111111111111111111111111111111111; b = 64'd1;
        
        #5 a = -64'd9223372036854770000; b=-64'd6000;

        

    end
endmodule