data/full_repos/permissive/469804105/RTL/Project_files/Top_level_design_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/469804105/RTL/Project_files/Top_level_design_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n  always #5 i_clk = ~i_clk ;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/469804105/RTL/Project_files/Top_level_design_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #1 start = 1\'b1 ;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/469804105/RTL/Project_files/Top_level_design_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n    #2 data_in_1 = 4\'b0010;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/469804105/RTL/Project_files/Top_level_design_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n    #1 data_in_2 = 4\'b1111;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/469804105/RTL/Project_files/Top_level_design_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #300 $stop;\n    ^\n%Error: data/full_repos/permissive/469804105/RTL/Project_files/Top_level_design_tb.v:40: Cannot find file containing module: \'Top_level_design\'\nTop_level_design DUT(\n^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/469804105/RTL/Project_files,data/full_repos/permissive/469804105/Top_level_design\n             data/full_repos/permissive/469804105/RTL/Project_files,data/full_repos/permissive/469804105/Top_level_design.v\n             data/full_repos/permissive/469804105/RTL/Project_files,data/full_repos/permissive/469804105/Top_level_design.sv\n             Top_level_design\n             Top_level_design.v\n             Top_level_design.sv\n             obj_dir/Top_level_design\n             obj_dir/Top_level_design.v\n             obj_dir/Top_level_design.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Top_level_design_tb();

reg i_clk ;
reg [`WID_1-1:0] data_in_1 ;

reg start ;
reg [`WID_1-1:0] data_in_2 ;
wire [`WID_1-1:0] o_reg_B ;
wire [`WID_1-1:0] o_reg_R ;
wire [`WID_1-1:0] o_reg_Q ;
wire [`WID_3-1:0] Count_out ;
wire [`WID_2-1:0] p_STATE ; 
wire done ;


Top_level_design DUT(
i_clk , data_in_1 , data_in_2 ,  start , p_STATE , o_reg_Q , o_reg_R  , o_reg_B ,Count_out,done  );


initial
 begin
  i_clk = 1'b0 ;
  start = 1'b1 ;


  end
 
  always #5 i_clk = ~i_clk ;
  
  initial
   begin

    #1 start = 1'b1 ;
    #2 data_in_1 = 4'b0010;
    #1 data_in_2 = 4'b1111;
    #300 $stop;
   end
endmodule
module Top_level_design_tb();


reg i_clk ;
reg [`WID_1-1:0] data_in_1 ;

reg start ;
reg [`WID_1-1:0] data_in_2 ;
wire [`WID_1-1:0] o_reg_B ;
wire [`WID_1-1:0] o_reg_R ;
wire [`WID_1-1:0] o_reg_Q ;
wire [`WID_3-1:0] Count_out ;
wire [`WID_2-1:0] p_STATE ; 
wire done ;


Top_level_design DUT(
i_clk , data_in_1 , data_in_2 ,  start , p_STATE , o_reg_Q , o_reg_R  , o_reg_B ,Count_out,done  );


initial
 begin
  i_clk = 1'b0 ;
  start = 1'b1 ;


  end
 
  always #5 i_clk = ~i_clk ;
  
  initial
   begin

    #1 start = 1'b1 ;
    #2 data_in_1 = 4'b0010;
    #1 data_in_2 = 4'b1111;
    #300 $stop;
   end
endmodule