data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/src/axi_address_resolver.sv
1: b'%Warning-MULTITOP: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/src/axi_address_resolver.sv:26: Multiple top level modules\n                                                                                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                                                           : ... Top module \'axi_address_resolver\'\nmodule axi_address_resolver #(\n       ^~~~~~~~~~~~~~~~~~~~\n                                                                                                                                           : ... Top module \'AXI_ROUTING_RULES\'\n  AXI_ROUTING_RULES.xbar               rules       ,\n  ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/src/axi_address_resolver.sv:26: Unsupported: Interfaced port on top level module\n  AXI_ROUTING_RULES.xbar               rules       ,\n                                       ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/src/axi_address_resolver.sv:26: Cannot find file containing interface: \'AXI_ROUTING_RULES\'\n  AXI_ROUTING_RULES.xbar               rules       ,\n  ^~~~~~~~~~~~~~~~~\n%Error: Internal Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/src/axi_address_resolver.sv:26: ../V3LinkDot.cpp:2055: Unlinked interface\n  AXI_ROUTING_RULES.xbar               rules       ,\n  ^~~~~~~~~~~~~~~~~\n'
module axi_address_resolver #(

  parameter int ADDR_WIDTH = -1,

  parameter int NUM_SLAVE = -1,

  parameter int NUM_RULES = -1
)(
  AXI_ROUTING_RULES.xbar               rules       ,
  input  logic [ADDR_WIDTH-1:0]        addr_i      ,
  output logic [$clog2(NUM_SLAVE)-1:0] match_idx_o ,
  output logic                         match_ok_o
);

  logic [NUM_SLAVE-1:0][NUM_RULES-1:0] matched_rules;
  logic [NUM_SLAVE-1:0]                matched_slaves;

  for (genvar i = 0; i < NUM_SLAVE; i++) begin : g_slave

    for (genvar j = 0; j < NUM_RULES; j++) begin : g_rule
      logic [ADDR_WIDTH-1:0] base, mask;
      logic enabled;
      assign base    = rules.rules[i][j].base;
      assign mask    = rules.rules[i][j].mask;
      assign enabled = rules.rules[i][j].enabled;

      assign matched_rules[i][j] = (enabled && (addr_i & mask) == (base & mask));
    end


    assign matched_slaves[i] = |matched_rules[i];
  end


  assign match_ok_o = |matched_slaves;


  find_first_one #(.WIDTH(NUM_SLAVE), .FLIP(0)) i_lzc (
    .in_i        ( matched_slaves ),
    .first_one_o ( match_idx_o    ),
    .no_ones_o   (                )
  );



  `ifndef SYNTHESIS
  always @(matched_rules, matched_slaves) begin
    assert ($onehot0(matched_rules)) else $error("%m: more than one rule matches 0x%0h: %0b", addr_i, matched_rules);
    assert ($onehot0(matched_slaves)) else $error("%m: more than one slave matches 0x%0h: %0b", addr_i, matched_slaves);
  end
  `endif

endmodule
module axi_address_resolver #(

  parameter int ADDR_WIDTH = -1,

  parameter int NUM_SLAVE = -1,

  parameter int NUM_RULES = -1
)(
  AXI_ROUTING_RULES.xbar               rules       ,
  input  logic [ADDR_WIDTH-1:0]        addr_i      ,
  output logic [$clog2(NUM_SLAVE)-1:0] match_idx_o ,
  output logic                         match_ok_o
);


  logic [NUM_SLAVE-1:0][NUM_RULES-1:0] matched_rules;
  logic [NUM_SLAVE-1:0]                matched_slaves;

  for (genvar i = 0; i < NUM_SLAVE; i++) begin : g_slave

    for (genvar j = 0; j < NUM_RULES; j++) begin : g_rule
      logic [ADDR_WIDTH-1:0] base, mask;
      logic enabled;
      assign base    = rules.rules[i][j].base;
      assign mask    = rules.rules[i][j].mask;
      assign enabled = rules.rules[i][j].enabled;

      assign matched_rules[i][j] = (enabled && (addr_i & mask) == (base & mask));
    end


    assign matched_slaves[i] = |matched_rules[i];
  end


  assign match_ok_o = |matched_slaves;


  find_first_one #(.WIDTH(NUM_SLAVE), .FLIP(0)) i_lzc (
    .in_i        ( matched_slaves ),
    .first_one_o ( match_idx_o    ),
    .no_ones_o   (                )
  );



  `ifndef SYNTHESIS
  always @(matched_rules, matched_slaves) begin
    assert ($onehot0(matched_rules)) else $error("%m: more than one rule matches 0x%0h: %0b", addr_i, matched_rules);
    assert ($onehot0(matched_slaves)) else $error("%m: more than one slave matches 0x%0h: %0b", addr_i, matched_slaves);
  end
  `endif

endmodule