data/full_repos/permissive/435877241/prj_301.v
data/verilator_xmls/1dca80a5-ddc4-482a-934a-6fb209304795.xml
module prj_301(
	input in0,
	input in1,
	output [1:0] out0
	);
	assign out0={in0,in1};
endmodule
module prj_301(
	input in0,
	input in1,
	output [1:0] out0
	);

	assign out0={in0,in1};
endmodule