data/full_repos/permissive/493019833/test/testcase/firrtl/SIntTester/reference/SIntTester.v
data/verilator_xmls/fe853b3f-e54d-42a9-8b44-b0145c8ba08f.xml
module EQ_SIGNED(y, a, b);
    parameter width = 4;
    output y;
    input [width-1:0] a;
    input [width-1:0] b;
    assign y = $signed(a) == $signed(b);
endmodule
module EQ_SIGNED(y, a, b);

    parameter width = 4;
    output y;
    input [width-1:0] a;
    input [width-1:0] b;
    assign y = $signed(a) == $signed(b);
endmodule