data/full_repos/permissive/520487363/EX1 - Clock and Periodic Signal Generation/MisaghM/Verilog/ring_osc_tb.v
1: b'%Error: Invalid Option: -\n'
module ring_osc_tb();
    wire out;
    reg rst = 1'b1;

    ring_osc #(.N(5), .Delay(1.8)) osc(out, rst);

    initial begin
        #20 rst = 1'b0;
        #200 $stop;
    end
endmodule
module ring_osc_tb();

    wire out;
    reg rst = 1'b1;

    ring_osc #(.N(5), .Delay(1.8)) osc(out, rst);

    initial begin
        #20 rst = 1'b0;
        #200 $stop;
    end
endmodule