data/full_repos/permissive/472097485/Chu04/Counters_00/SimTest.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu04/Counters_00/SimTest.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #(T/2);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu04/Counters_00/SimTest.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #(T/2)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu04/Counters_00/SimTest.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #(T*2500);\n  ^\n%Error: data/full_repos/permissive/472097485/Chu04/Counters_00/SimTest.v:19: Cannot find file containing module: \'FrequencyDivider\'\n FrequencyDivider #( 12, 4 ) frequencyDivider ( clk, reset, max_tick );\n ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/472097485/Chu04/Counters_00,data/full_repos/permissive/472097485/FrequencyDivider\n             data/full_repos/permissive/472097485/Chu04/Counters_00,data/full_repos/permissive/472097485/FrequencyDivider.v\n             data/full_repos/permissive/472097485/Chu04/Counters_00,data/full_repos/permissive/472097485/FrequencyDivider.sv\n             FrequencyDivider\n             FrequencyDivider.v\n             FrequencyDivider.sv\n             obj_dir/FrequencyDivider\n             obj_dir/FrequencyDivider.v\n             obj_dir/FrequencyDivider.sv\n%Error: data/full_repos/permissive/472097485/Chu04/Counters_00/SimTest.v:21: Cannot find file containing module: \'ModMCounter\'\n ModMCounter #( 100, 8 ) counter ( max_tick, reset, r );\n ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module SimTest();

	localparam T = 2;


	reg clk, reset;

	wire max_tick;


	wire [7:0] r;


	FrequencyDivider #( 12, 4 ) frequencyDivider ( clk, reset, max_tick );
	
	ModMCounter #( 100, 8 ) counter ( max_tick, reset, r );

	always
	begin


		clk = 1'b0;
		#(T/2);
	end

	initial begin

		reset = 1'b1;
		#(T/2)
		reset = 1'b0;
		

		#(T*2500);
        

		$stop;
	end
      
endmodule
module SimTest();


	localparam T = 2;


	reg clk, reset;

	wire max_tick;


	wire [7:0] r;


	FrequencyDivider #( 12, 4 ) frequencyDivider ( clk, reset, max_tick );
	
	ModMCounter #( 100, 8 ) counter ( max_tick, reset, r );

	always
	begin


		clk = 1'b0;
		#(T/2);
	end

	initial begin

		reset = 1'b1;
		#(T/2)
		reset = 1'b0;
		

		#(T*2500);
        

		$stop;
	end
      
endmodule