data/full_repos/permissive/509809169/Verilog Language/More Verilog Features/Combinational for loop_ 255 bit population count.v
1: b'%Error: Cannot find file containing module: Language/More\n        ... Looked in:\n             data/full_repos/permissive/509809169/Verilog/Language/More\n             data/full_repos/permissive/509809169/Verilog/Language/More.v\n             data/full_repos/permissive/509809169/Verilog/Language/More.sv\n             Language/More\n             Language/More.v\n             Language/More.sv\n             obj_dir/Language/More\n             obj_dir/Language/More.v\n             obj_dir/Language/More.sv\n%Error: Cannot find file containing module: Verilog\n%Error: Cannot find file containing module: Features,data/full_repos/permissive/509809169\n%Error: Cannot find file containing module: data/full_repos/permissive/509809169/Verilog\n%Error: Cannot find file containing module: Features/Combinational\n%Error: Cannot find file containing module: for\n%Error: Cannot find file containing module: loop_\n%Error: Cannot find file containing module: 255\n%Error: Cannot find file containing module: bit\n%Error: Cannot find file containing module: population\n%Error: Cannot find file containing module: count.v\n%Error: Exiting due to 11 error(s)\n'
module top_module( 
    input [254:0] in,
    output [7:0] out );
    int i;
    reg [7:0]out_;
    always @(*) begin
        out_=0;
        for(i=0;i<255;i++) begin
            if(in[i]==1'b1)	out_=out_+1;
        end
    end
    assign out=out_;
endmodule
module top_module( 
    input [254:0] in,
    output [7:0] out );

    int i;
    reg [7:0]out_;
    always @(*) begin
        out_=0;
        for(i=0;i<255;i++) begin
            if(in[i]==1'b1)	out_=out_+1;
        end
    end
    assign out=out_;
endmodule