data/full_repos/permissive/52881156/fpga_files/catapult_proj/Background Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1/cycle_mgc_ioport.v
1: b'%Error: Cannot find file containing module: Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156\n        ... Looked in:\n             data/full_repos/permissive/52881156/fpga_files/catapult_proj/Background/Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156\n             data/full_repos/permissive/52881156/fpga_files/catapult_proj/Background/Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156.v\n             data/full_repos/permissive/52881156/fpga_files/catapult_proj/Background/Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156.sv\n             Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156\n             Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156.v\n             Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156.sv\n             obj_dir/Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156\n             obj_dir/Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156.v\n             obj_dir/Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1,data/full_repos/permissive/52881156.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/52881156/fpga_files/catapult_proj/Background\n%Error: Cannot find file containing module: Subtraction/MemoryTestBench/catapult/MemoryTester/MemoryTester.v1/cycle_mgc_ioport.v\n%Error: Exiting due to 3 error(s)\n'
module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);

    parameter integer rscid = 1;
    parameter integer width = 8;

    input              ldin;
    output [width-1:0] din;
    input              ldout;
    input  [width-1:0] dout;
    output             lzin;
    output             lzout;
    inout  [width-1:0] z;

    wire   [width-1:0] din;
    wire               lzin;
    wire               lzout;
    wire   [width-1:0] z;

    assign lzin = ldin;
    assign din = ldin ? z : {width{1'bz}};
    assign lzout = ldout;
    assign z = ldout ? dout : {width{1'bz}};

endmodule
module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z);


    parameter integer rscid = 1;
    parameter integer width = 8;

    input              ldin;
    output [width-1:0] din;
    input              ldout;
    input  [width-1:0] dout;
    output             lzin;
    output             lzout;
    inout  [width-1:0] z;

    wire   [width-1:0] din;
    wire               lzin;
    wire               lzout;
    wire   [width-1:0] z;

    assign lzin = ldin;
    assign din = ldin ? z : {width{1'bz}};
    assign lzout = ldout;
    assign z = ldout ? dout : {width{1'bz}};

endmodule