data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_always_example.v
data/verilator_xmls/56127937-295b-42a9-a1ac-9c8eeb809635.xml
module always_example();
reg clk,reset,enable,q_in,data;

always @ (posedge clk)
if (reset)  begin
   data <= 0;
end else if (enable) begin   
   data <= q_in;
end

endmodule
module always_example();

reg clk,reset,enable,q_in,data;

always @ (posedge clk)
if (reset)  begin
   data <= 0;
end else if (enable) begin   
   data <= q_in;
end

endmodule