data/full_repos/permissive/443556793/lab_4/rtl/hazard.v
1: b'%Warning-WIDTH: data/full_repos/permissive/443556793/lab_4/rtl/hazard.v:173: Operator AND expects 5 bits on the LHS, but LHS\'s VARREF \'jrD\' generates 1 bits.\n                                                                           : ... In instance hazard\nassign #1 jrstall = jrD & (((writeregE == rsD) & regwriteE) | (writeregM & (writeregM == rsD)));\n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/443556793/lab_4/rtl/hazard.v:173: Operator AND expects 5 bits on the LHS, but LHS\'s EQ generates 1 bits.\n                                                                           : ... In instance hazard\nassign #1 jrstall = jrD & (((writeregE == rsD) & regwriteE) | (writeregM & (writeregM == rsD)));\n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/443556793/lab_4/rtl/hazard.v:173: Operator AND expects 5 bits on the RHS, but RHS\'s VARREF \'regwriteE\' generates 1 bits.\n                                                                           : ... In instance hazard\nassign #1 jrstall = jrD & (((writeregE == rsD) & regwriteE) | (writeregM & (writeregM == rsD)));\n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/443556793/lab_4/rtl/hazard.v:173: Operator AND expects 5 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                           : ... In instance hazard\nassign #1 jrstall = jrD & (((writeregE == rsD) & regwriteE) | (writeregM & (writeregM == rsD)));\n                                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/443556793/lab_4/rtl/hazard.v:173: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s AND generates 5 bits.\n                                                                           : ... In instance hazard\nassign #1 jrstall = jrD & (((writeregE == rsD) & regwriteE) | (writeregM & (writeregM == rsD)));\n                  ^\n%Error: Exiting due to 5 warning(s)\n'
module hazard(

           output wire stallF,
           output wire flushF,

           input wire[4:0] rsD,rtD,
           input wire branchD,
           output reg[1:0] forwardaD,
           output wire forwardbD,
           output wire stallD,
           input wire jrD,
           input wire hilowriteD,
           input wire[4:0] rdD,
           output reg[1:0] forwardcD,
           output reg[1:0] forwarddD,

           input wire[4:0] rsE,rtE,
           input wire[4:0] writeregE,
           input wire regwriteE,
           input wire memtoregE,
           output reg[1:0] forwardaE,forwardbE,
           output wire flushE,
           output wire stallE,
           input wire div_stallE,
           input wire[4:0] rdE,
           input wire hilotoregE,

           input wire[4:0] writeregM,
           input wire regwriteM,
           input wire memtoregM,
           input wire hilotoregM,
           input wire hiloreadM,

           input wire[4:0] writeregW,
           input wire regwriteW,
           input wire hiloreadW
       );

wire lwstallD,branchstallD;
wire divstall,multistall,jrstall,hilostall;



assign forwardbD = (rtD != 0 & rtD == writeregM & regwriteM);
always @(*)
begin
    forwardaD = 2'b00;
    if(rsD != 0)
    begin

        if(rsD == writeregE & regwriteE)
        begin

            forwardaD = 2'b10;
        end
        else if(rsD == writeregM & regwriteM)
        begin

            forwardaD = 2'b01;
        end
    end
end

always @(*)
begin
    forwarddD = 2'b00;
    if(rsD != 0)
    begin

        if((rsD == writeregM & regwriteM & hiloreadM)|(rsD == writeregW & regwriteW & hiloreadW))
        begin
            if(({memtoregE,hilotoregE}==2'b01)||({memtoregM,hilotoregM}==2'b01))

                forwarddD = 2'b01;
            else if(({memtoregE,hilotoregE}==2'b11)||({memtoregM,hilotoregM}==2'b11))

                forwarddD = 2'b10;
            else
                forwarddD = 2'b00;
        end
    end
end

always @(*)
begin
    forwardcD = 2'b00;
    if(rtD != 0)
    begin

        if((rtD == writeregE & regwriteE)|(rtD == writeregM & regwriteM))
        begin
            if(({memtoregE,hilotoregE}==2'b01)||({memtoregM,hilotoregM}==2'b01))

                forwardcD = 2'b01;
            else if(({memtoregE,hilotoregE}==2'b11)||({memtoregM,hilotoregM}==2'b11))

                forwardcD = 2'b10;
            else
                forwardcD = 2'b00;
        end
    end
end






always @(*)
begin
    forwardaE = 2'b00;
    forwardbE = 2'b00;
    if(rsE != 0)
    begin

        if(rsE == writeregM & regwriteM)
        begin

            forwardaE = 2'b10;
        end
        else if(rsE == writeregW & regwriteW)
        begin

            forwardaE = 2'b01;
        end
    end
    if(rtE != 0)
    begin

        if(rtE == writeregM & regwriteM)
        begin

            forwardbE = 2'b10;
        end
        else if(rtE == writeregW & regwriteW)
        begin

            forwardbE = 2'b01;
        end
    end
end


assign #1 lwstallD = memtoregE & (rtE == rsD | rtE == rtD);
assign #1 branchstallD = branchD &
       (regwriteE &
        (writeregE == rsD | writeregE == rtD) |
        memtoregM &
        (writeregM == rsD | writeregM == rtD));
assign #1 divstall = div_stallE;
assign #1 jrstall = jrD & (((writeregE == rsD) & regwriteE) | (writeregM & (writeregM == rsD)));

assign #1 hilostall = hilowriteD & ((rsD == writeregM) & regwriteM);

assign #1 stallE = divstall;
assign #1 stallD = lwstallD | branchstallD | jrstall | stallE | hilostall;
assign #1 stallF = stallD;

assign #1 flushE = lwstallD | branchstallD|hilostall;
assign #1 flushF = 1'b0;





endmodule
module hazard(

           output wire stallF,
           output wire flushF,

           input wire[4:0] rsD,rtD,
           input wire branchD,
           output reg[1:0] forwardaD,
           output wire forwardbD,
           output wire stallD,
           input wire jrD,
           input wire hilowriteD,
           input wire[4:0] rdD,
           output reg[1:0] forwardcD,
           output reg[1:0] forwarddD,

           input wire[4:0] rsE,rtE,
           input wire[4:0] writeregE,
           input wire regwriteE,
           input wire memtoregE,
           output reg[1:0] forwardaE,forwardbE,
           output wire flushE,
           output wire stallE,
           input wire div_stallE,
           input wire[4:0] rdE,
           input wire hilotoregE,

           input wire[4:0] writeregM,
           input wire regwriteM,
           input wire memtoregM,
           input wire hilotoregM,
           input wire hiloreadM,

           input wire[4:0] writeregW,
           input wire regwriteW,
           input wire hiloreadW
       );


wire lwstallD,branchstallD;
wire divstall,multistall,jrstall,hilostall;



assign forwardbD = (rtD != 0 & rtD == writeregM & regwriteM);
always @(*)
begin
    forwardaD = 2'b00;
    if(rsD != 0)
    begin

        if(rsD == writeregE & regwriteE)
        begin

            forwardaD = 2'b10;
        end
        else if(rsD == writeregM & regwriteM)
        begin

            forwardaD = 2'b01;
        end
    end
end

always @(*)
begin
    forwarddD = 2'b00;
    if(rsD != 0)
    begin

        if((rsD == writeregM & regwriteM & hiloreadM)|(rsD == writeregW & regwriteW & hiloreadW))
        begin
            if(({memtoregE,hilotoregE}==2'b01)||({memtoregM,hilotoregM}==2'b01))

                forwarddD = 2'b01;
            else if(({memtoregE,hilotoregE}==2'b11)||({memtoregM,hilotoregM}==2'b11))

                forwarddD = 2'b10;
            else
                forwarddD = 2'b00;
        end
    end
end

always @(*)
begin
    forwardcD = 2'b00;
    if(rtD != 0)
    begin

        if((rtD == writeregE & regwriteE)|(rtD == writeregM & regwriteM))
        begin
            if(({memtoregE,hilotoregE}==2'b01)||({memtoregM,hilotoregM}==2'b01))

                forwardcD = 2'b01;
            else if(({memtoregE,hilotoregE}==2'b11)||({memtoregM,hilotoregM}==2'b11))

                forwardcD = 2'b10;
            else
                forwardcD = 2'b00;
        end
    end
end






always @(*)
begin
    forwardaE = 2'b00;
    forwardbE = 2'b00;
    if(rsE != 0)
    begin

        if(rsE == writeregM & regwriteM)
        begin

            forwardaE = 2'b10;
        end
        else if(rsE == writeregW & regwriteW)
        begin

            forwardaE = 2'b01;
        end
    end
    if(rtE != 0)
    begin

        if(rtE == writeregM & regwriteM)
        begin

            forwardbE = 2'b10;
        end
        else if(rtE == writeregW & regwriteW)
        begin

            forwardbE = 2'b01;
        end
    end
end


assign #1 lwstallD = memtoregE & (rtE == rsD | rtE == rtD);
assign #1 branchstallD = branchD &
       (regwriteE &
        (writeregE == rsD | writeregE == rtD) |
        memtoregM &
        (writeregM == rsD | writeregM == rtD));
assign #1 divstall = div_stallE;
assign #1 jrstall = jrD & (((writeregE == rsD) & regwriteE) | (writeregM & (writeregM == rsD)));

assign #1 hilostall = hilowriteD & ((rsD == writeregM) & regwriteM);

assign #1 stallE = divstall;
assign #1 stallD = lwstallD | branchstallD | jrstall | stallE | hilostall;
assign #1 stallF = stallD;

assign #1 flushE = lwstallD | branchstallD|hilostall;
assign #1 flushF = 1'b0;





endmodule