data/full_repos/permissive/459497172/verilog/rtl/pinmux/src/pwm.sv
data/verilator_xmls/07f0e48d-78fe-4c02-bebe-195961ba17cd.xml
module pwm(
	output  logic         waveform,

	input  logic         h_reset_n,
	input  logic         mclk,
	input  logic         pulse1m_mclk,
	input  logic         cfg_pwm_enb,
	input  logic [15:0]  cfg_pwm_high,
	input  logic [15:0]  cfg_pwm_low
);

logic [15:0]  pwm_cnt  ;


always @(posedge mclk or negedge h_reset_n)
begin 
   if ( ~h_reset_n )
   begin
      pwm_cnt  <= 16'h0;
      waveform <= 1'b0;
   end
   else if ( pulse1m_mclk  && cfg_pwm_enb)
   begin 
      if ( pwm_cnt == 16'h0 && waveform  == 1'b0) begin
         pwm_cnt       <= cfg_pwm_high;
         waveform      <= ~waveform;
      end else if ( pwm_cnt == 16'h0 && waveform  == 1'b1) begin
         pwm_cnt       <= cfg_pwm_low;
         waveform      <= ~waveform;
      end else begin
     	   pwm_cnt <= pwm_cnt - 1;
      end
   end
end 

endmodule
module pwm(
	output  logic         waveform,

	input  logic         h_reset_n,
	input  logic         mclk,
	input  logic         pulse1m_mclk,
	input  logic         cfg_pwm_enb,
	input  logic [15:0]  cfg_pwm_high,
	input  logic [15:0]  cfg_pwm_low
);


logic [15:0]  pwm_cnt  ;


always @(posedge mclk or negedge h_reset_n)
begin 
   if ( ~h_reset_n )
   begin
      pwm_cnt  <= 16'h0;
      waveform <= 1'b0;
   end
   else if ( pulse1m_mclk  && cfg_pwm_enb)
   begin 
      if ( pwm_cnt == 16'h0 && waveform  == 1'b0) begin
         pwm_cnt       <= cfg_pwm_high;
         waveform      <= ~waveform;
      end else if ( pwm_cnt == 16'h0 && waveform  == 1'b1) begin
         pwm_cnt       <= cfg_pwm_low;
         waveform      <= ~waveform;
      end else begin
     	   pwm_cnt <= pwm_cnt - 1;
      end
   end
end 

endmodule