data/full_repos/permissive/500596939/rtl/TV80/tv80pa.v
1: b'%Error: data/full_repos/permissive/500596939/rtl/TV80/tv80pa.v:76: Cannot find file containing module: \'tv80_core\'\n  tv80_core #(Mode, IOWait) i_tv80_core\n  ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/500596939/rtl/TV80,data/full_repos/permissive/500596939/tv80_core\n             data/full_repos/permissive/500596939/rtl/TV80,data/full_repos/permissive/500596939/tv80_core.v\n             data/full_repos/permissive/500596939/rtl/TV80,data/full_repos/permissive/500596939/tv80_core.sv\n             tv80_core\n             tv80_core.v\n             tv80_core.sv\n             obj_dir/tv80_core\n             obj_dir/tv80_core.v\n             obj_dir/tv80_core.sv\n%Warning-WIDTH: data/full_repos/permissive/500596939/rtl/TV80/tv80pa.v:124: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'3\'h2\' generates 3 bits.\n                                                                          : ... In instance tv80pa\n      if (tstate==3\'b010) begin\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/500596939/rtl/TV80/tv80pa.v:131: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                          : ... In instance tv80pa\n      if (tstate==3\'b001 && iorq==1\'b1) begin\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/500596939/rtl/TV80/tv80pa.v:139: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'3\'h2\' generates 3 bits.\n                                                                          : ... In instance tv80pa\n    if (tstate==3\'b010)\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/500596939/rtl/TV80/tv80pa.v:143: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'3\'h3\' generates 3 bits.\n                                                                          : ... In instance tv80pa\n    if (tstate==3\'b011 && BUSAK_n==1\'b1) di_reg <= DI;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/500596939/rtl/TV80/tv80pa.v:145: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                          : ... In instance tv80pa\n      if (tstate==3\'b001) begin\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/500596939/rtl/TV80/tv80pa.v:152: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'3\'h3\' generates 3 bits.\n                                                                          : ... In instance tv80pa\n      if (tstate==3\'b011) begin\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/500596939/rtl/TV80/tv80pa.v:157: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                                          : ... In instance tv80pa\n      if (tstate==3\'b100) MREQ_n <= 1\'b1;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/500596939/rtl/TV80/tv80pa.v:161: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                          : ... In instance tv80pa\n        if (tstate==3\'b001) begin\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/500596939/rtl/TV80/tv80pa.v:167: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'3\'h2\' generates 3 bits.\n                                                                          : ... In instance tv80pa\n      if (tstate==3\'b010) WR_n <= ~write;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/500596939/rtl/TV80/tv80pa.v:168: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'3\'h3\' generates 3 bits.\n                                                                          : ... In instance tv80pa\n      if (tstate==3\'b011) begin\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/500596939/rtl/TV80/tv80pa.v:144: Operator EQ expects 7 bits on the RHS, but RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                          : ... In instance tv80pa\n    if (mcycle==3\'b001) begin\n              ^~\n%Error: Exiting due to 1 error(s), 11 warning(s)\n'
module tv80pa (

  M1_n, MREQ_n, IORQ_n, RD_n, WR_n, RFSH_n, HALT_n, BUSAK_n, A, DO,

  RESET_n, CLK, CEN_p, CEN_n, WAIT_n, INT_n, NMI_n, BUSRQ_n, DI
  );

  parameter Mode = 0;
  parameter T2Write = 1;
  parameter IOWait  = 1;


  input         RESET_n;
  input         CLK;
  input         CEN_p;
  input         CEN_n;
  input         WAIT_n;
  input         INT_n;
  input         NMI_n;
  input         BUSRQ_n;
  output        M1_n;
  output        MREQ_n;
  output        IORQ_n;
  output        RD_n;
  output        WR_n;
  output        RFSH_n;
  output        HALT_n;
  output        BUSAK_n;
  output reg [15:0] A;
  input [7:0]   DI;
  output [7:0]  DO;

  reg           MREQ_n;
  reg           IORQ_n;
  reg           RD_n;
  reg           WR_n;

  reg           CEN_pol;
  wire          intcycle_n;
  wire          no_read;
  wire          write;
  wire          iorq;
  reg [7:0]     di_reg;
  wire [6:0]    mcycle;
  wire [6:0]    tstate;

  reg [1:0]     intcycled_n;
  wire [15:0]   A_int;
  reg [15:0]    A_last;

  tv80_core #(Mode, IOWait) i_tv80_core
    (
     .cen (CEN_p && ~CEN_pol),
     .m1_n (M1_n),
     .iorq (iorq),
     .no_read (no_read),
     .write (write),
     .rfsh_n (RFSH_n),
     .halt_n (HALT_n),
     .wait_n (WAIT_n),
     .int_n (INT_n),
     .nmi_n (NMI_n),
     .reset_n (RESET_n),
     .busrq_n (BUSRQ_n),
     .busak_n (BUSAK_n),
     .clk (CLK),
     .IntE (),
     .stop (),
     .A (A_int),
     .dinst (DI),
     .di (di_reg),
     .dout (DO),
     .mc (mcycle),
     .ts (tstate),
     .intcycle_n (intcycle_n)
     );

always @(posedge CLK) begin

  if (no_read==1'b0 || write==1'b1) begin
        A <= A_int;
  end
  else begin
    A <= A_last;
  end

  if (~RESET_n) begin
    WR_n    <= 1'b1;
    RD_n    <= 1'b1;
    IORQ_n  <= 1'b1;
    MREQ_n  <= 1'b1;
    di_reg  <= 0;
    CEN_pol <= 1'b0;

  end
  else if (CEN_p==1'b1 && CEN_pol==1'b0) begin
    CEN_pol <= 1'b1;
    if (mcycle=='b001) begin
      if (tstate==3'b010) begin
        IORQ_n <= 1'b1;
        MREQ_n <= 1'b1;
        RD_n   <= 1'b1;
      end
    end
    else begin
      if (tstate==3'b001 && iorq==1'b1) begin
        WR_n   <= ~write;
        RD_n   <= write;
        IORQ_n <= 1'b0;
      end
    end
  end
  else if (CEN_n==1'b1 && CEN_pol==1'b1) begin
    if (tstate==3'b010)
      CEN_pol <= ~WAIT_n;
    else
      CEN_pol <= 1'b0;
    if (tstate==3'b011 && BUSAK_n==1'b1) di_reg <= DI;
    if (mcycle==3'b001) begin
      if (tstate==3'b001) begin
        intcycled_n <= {intcycled_n[0],intcycle_n};
        RD_n   <= ~intcycle_n;
        MREQ_n <= ~intcycle_n;
        IORQ_n <= intcycled_n[1];
        A_last <= A_int;
      end
      if (tstate==3'b011) begin
        intcycled_n <= 2'b11;
        RD_n   <= 1'b1;
        MREQ_n <= 1'b0;
      end
      if (tstate==3'b100) MREQ_n <= 1'b1;
    end
    else begin
      if (no_read==1'b0 && iorq==1'b0) begin
        if (tstate==3'b001) begin
          RD_n   <= write;
          MREQ_n <= 1'b0;
          A_last <= A_int;
        end
      end
      if (tstate==3'b010) WR_n <= ~write;
      if (tstate==3'b011) begin
        WR_n   <= 1'b1;
        RD_n   <= 1'b1;
        IORQ_n <= 1'b1;
        MREQ_n <= 1'b1;
      end
    end
  end
end

endmodule
module tv80pa (

  M1_n, MREQ_n, IORQ_n, RD_n, WR_n, RFSH_n, HALT_n, BUSAK_n, A, DO,

  RESET_n, CLK, CEN_p, CEN_n, WAIT_n, INT_n, NMI_n, BUSRQ_n, DI
  );


  parameter Mode = 0;
  parameter T2Write = 1;
  parameter IOWait  = 1;


  input         RESET_n;
  input         CLK;
  input         CEN_p;
  input         CEN_n;
  input         WAIT_n;
  input         INT_n;
  input         NMI_n;
  input         BUSRQ_n;
  output        M1_n;
  output        MREQ_n;
  output        IORQ_n;
  output        RD_n;
  output        WR_n;
  output        RFSH_n;
  output        HALT_n;
  output        BUSAK_n;
  output reg [15:0] A;
  input [7:0]   DI;
  output [7:0]  DO;

  reg           MREQ_n;
  reg           IORQ_n;
  reg           RD_n;
  reg           WR_n;

  reg           CEN_pol;
  wire          intcycle_n;
  wire          no_read;
  wire          write;
  wire          iorq;
  reg [7:0]     di_reg;
  wire [6:0]    mcycle;
  wire [6:0]    tstate;

  reg [1:0]     intcycled_n;
  wire [15:0]   A_int;
  reg [15:0]    A_last;

  tv80_core #(Mode, IOWait) i_tv80_core
    (
     .cen (CEN_p && ~CEN_pol),
     .m1_n (M1_n),
     .iorq (iorq),
     .no_read (no_read),
     .write (write),
     .rfsh_n (RFSH_n),
     .halt_n (HALT_n),
     .wait_n (WAIT_n),
     .int_n (INT_n),
     .nmi_n (NMI_n),
     .reset_n (RESET_n),
     .busrq_n (BUSRQ_n),
     .busak_n (BUSAK_n),
     .clk (CLK),
     .IntE (),
     .stop (),
     .A (A_int),
     .dinst (DI),
     .di (di_reg),
     .dout (DO),
     .mc (mcycle),
     .ts (tstate),
     .intcycle_n (intcycle_n)
     );

always @(posedge CLK) begin

  if (no_read==1'b0 || write==1'b1) begin
        A <= A_int;
  end
  else begin
    A <= A_last;
  end

  if (~RESET_n) begin
    WR_n    <= 1'b1;
    RD_n    <= 1'b1;
    IORQ_n  <= 1'b1;
    MREQ_n  <= 1'b1;
    di_reg  <= 0;
    CEN_pol <= 1'b0;

  end
  else if (CEN_p==1'b1 && CEN_pol==1'b0) begin
    CEN_pol <= 1'b1;
    if (mcycle=='b001) begin
      if (tstate==3'b010) begin
        IORQ_n <= 1'b1;
        MREQ_n <= 1'b1;
        RD_n   <= 1'b1;
      end
    end
    else begin
      if (tstate==3'b001 && iorq==1'b1) begin
        WR_n   <= ~write;
        RD_n   <= write;
        IORQ_n <= 1'b0;
      end
    end
  end
  else if (CEN_n==1'b1 && CEN_pol==1'b1) begin
    if (tstate==3'b010)
      CEN_pol <= ~WAIT_n;
    else
      CEN_pol <= 1'b0;
    if (tstate==3'b011 && BUSAK_n==1'b1) di_reg <= DI;
    if (mcycle==3'b001) begin
      if (tstate==3'b001) begin
        intcycled_n <= {intcycled_n[0],intcycle_n};
        RD_n   <= ~intcycle_n;
        MREQ_n <= ~intcycle_n;
        IORQ_n <= intcycled_n[1];
        A_last <= A_int;
      end
      if (tstate==3'b011) begin
        intcycled_n <= 2'b11;
        RD_n   <= 1'b1;
        MREQ_n <= 1'b0;
      end
      if (tstate==3'b100) MREQ_n <= 1'b1;
    end
    else begin
      if (no_read==1'b0 && iorq==1'b0) begin
        if (tstate==3'b001) begin
          RD_n   <= write;
          MREQ_n <= 1'b0;
          A_last <= A_int;
        end
      end
      if (tstate==3'b010) WR_n <= ~write;
      if (tstate==3'b011) begin
        WR_n   <= 1'b1;
        RD_n   <= 1'b1;
        IORQ_n <= 1'b1;
        MREQ_n <= 1'b1;
      end
    end
  end
end

endmodule