data/full_repos/permissive/461099925/salemachine/salem.v
1: b'%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:118: Value too large for 5 bit number: 40\n                        end  else if(residue < 5\'d40)begin \n                                               ^~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:121: Value too large for 5 bit number: 50\n                        end  else if(residue < 5\'d50)begin \n                                               ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:122: Value too large for 5 bit number: 40\n                            res_c[3:0]      <=  residue - 5\'d40 ;\n                                                          ^~~~~\n%Warning-MULTITOP: data/full_repos/permissive/461099925/salemachine/salem.v:158: Multiple top level modules\n                                                                               : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                               : ... Top module \'salem\'\nmodule salem(\n       ^~~~~\n                                                                               : ... Top module \'bcd2seg\'\nmodule bcd2seg(SW,SEG);\n       ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:63: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 5 bits.\n                                                                           : ... In instance salem\n            gm_c[3:0]      <=  swb - 5\'d10 ;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:91: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                           : ... In instance salem\n            residue     <= 8\'h00;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:106: Operator SUB expects 6 bits on the LHS, but LHS\'s SEL generates 4 bits.\n                                                                            : ... In instance salem\n                                residue <=  (im_c[7:4] -item[swb][7:4])*4\'ha + im_c[3:0] - item[swb][3:0];\n                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:106: Operator SUB expects 6 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                            : ... In instance salem\n                                residue <=  (im_c[7:4] -item[swb][7:4])*4\'ha + im_c[3:0] - item[swb][3:0];\n                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:106: Operator ADD expects 6 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                            : ... In instance salem\n                                residue <=  (im_c[7:4] -item[swb][7:4])*4\'ha + im_c[3:0] - item[swb][3:0];\n                                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:106: Operator SUB expects 6 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                            : ... In instance salem\n                                residue <=  (im_c[7:4] -item[swb][7:4])*4\'ha + im_c[3:0] - item[swb][3:0];\n                                                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:111: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'residue\' generates 6 bits.\n                                                                            : ... In instance salem\n                            res_c      <=  residue     ;\n                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:113: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 6 bits.\n                                                                            : ... In instance salem\n                            res_c[3:0]      <=  residue - 5\'d10 ;\n                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:116: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 6 bits.\n                                                                            : ... In instance salem\n                            res_c[3:0]      <=  residue - 5\'d20 ;\n                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:119: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 6 bits.\n                                                                            : ... In instance salem\n                            res_c[3:0]      <=  residue - 5\'d30 ;\n                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:122: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 6 bits.\n                                                                            : ... In instance salem\n                            res_c[3:0]      <=  residue - 5\'d40 ;\n                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:121: Operator LT expects 6 bits on the RHS, but RHS\'s CONST \'5\'h12\' generates 5 bits.\n                                                                            : ... In instance salem\n                        end  else if(residue < 5\'d50)begin \n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:118: Operator LT expects 6 bits on the RHS, but RHS\'s CONST \'5\'h8\' generates 5 bits.\n                                                                            : ... In instance salem\n                        end  else if(residue < 5\'d40)begin \n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:115: Operator LT expects 6 bits on the RHS, but RHS\'s CONST \'5\'h1e\' generates 5 bits.\n                                                                            : ... In instance salem\n                        end  else if(residue < 5\'d30)begin \n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:112: Operator LT expects 6 bits on the RHS, but RHS\'s CONST \'5\'h14\' generates 5 bits.\n                                                                            : ... In instance salem\n                        else if(residue < 5\'d20) begin \n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/461099925/salemachine/salem.v:110: Operator LT expects 6 bits on the RHS, but RHS\'s CONST \'5\'ha\' generates 5 bits.\n                                                                            : ... In instance salem\n                        if(residue < 5\'d10)\n                                   ^\n%Error: Exiting due to 20 warning(s)\n'
module salem(
    input              clk      ,
    input              rstn     ,
    input [4:0]        swb      ,
    input [4:0]        mty      ,
    input              get      ,
    output reg         alarm    ,
    output reg [7:0]   gm_c     ,
    output reg [7:0]   im_c     ,
    output reg [7:0]   res_c    ,
    output[7:0]        dbg_good_price
);


    reg [5:0]       residue     ;

    wire [7:0]      item[0:19]  ;
    reg [2:0]       cst         ;
    reg [2:0]       nst         ;
    reg [4:0]       cnt         ;
    parameter  IDLE         = 3'b000;
    parameter  GMONEY       = 3'b001;
    parameter  SHOPPING     = 3'b010;
    parameter  BACK         = 3'b100;
    parameter  RETURN       = 3'b111;


    assign item[0]         = 8'h01;
    assign item[1]         = 8'h02;
    assign item[2]         = 8'h02;
    assign item[3]         = 8'h03;
    assign item[4]         = 8'h03;
    assign item[5]         = 8'h04;
    assign item[6]         = 8'h08;
    assign item[7]         = 8'h09;
    assign item[8]         = 8'h12;
    assign item[9]         = 8'h18;
    assign item[10]         = 8'h10;
    assign item[11]         = 8'h10;
    assign item[12]         = 8'h12;
    assign item[13]         = 8'h12;
    assign item[14]         = 8'h15;
    assign item[15]         = 8'h15;
    assign item[16]         = 8'h20;
    assign item[17]         = 8'h25;
    assign item[18]         = 8'h30;
    assign item[19]         = 8'h30;

    assign dbg_good_price = item[swb];

    always @(posedge clk or negedge rstn) begin
        if(rstn == 1'b0)
            gm_c      <=  8'h00   ;
        else if(swb < 5'd10)
            gm_c      <=  {3'b000,swb}     ;
        else if(swb < 5'd20) begin 
            gm_c[3:0]      <=  swb - 5'd10 ;
            gm_c[7:4]      <=  4'h1;
        end 
    end

    always @(posedge clk or negedge rstn) begin
        if(rstn == 1'b0)
            im_c      <=  8'h00   ;
        else begin case (mty)
                5'h1    :       im_c      <=  8'h01   ;
                5'h2    :       im_c      <=  8'h05   ;
                5'h4    :       im_c      <=  8'h10   ;
                5'h8    :       im_c      <=  8'h20   ;
                5'h10   :       im_c      <=  8'h50   ;
                default :       im_c      <=  8'h00   ;
             endcase
        end  
    end

    always @(posedge clk or negedge rstn) begin
        if(rstn == 1'b0)
            cst     <=  IDLE;
        else 
            cst     <=  nst;
    end

    always @(posedge clk or negedge rstn) begin
        if(rstn == 1'b0) begin 
            residue     <= 8'h00;
            res_c       <= 'd0;
            nst         <= IDLE ;   
        end else case(cst)
            IDLE:
                if(mty == 5'h00)
                    nst     <=   IDLE;
                else 
                    nst     <=    GMONEY;
            GMONEY: 
                if(im_c > item[swb] || im_c == item[swb]) 
                    nst     <=    SHOPPING;
                else
                    nst     <=   RETURN;
            SHOPPING:begin if(im_c > item[swb] || im_c == item[swb]) 
                                residue <=  (im_c[7:4] -item[swb][7:4])*4'ha + im_c[3:0] - item[swb][3:0];
                    nst     <=   BACK;
            end                              
            BACK:   begin 
                        if(residue < 5'd10)
                            res_c      <=  residue     ;
                        else if(residue < 5'd20) begin 
                            res_c[3:0]      <=  residue - 5'd10 ;
                            res_c[7:4]      <=  4'h1;
                        end  else if(residue < 5'd30)begin 
                            res_c[3:0]      <=  residue - 5'd20 ;
                            res_c[7:4]      <=  4'h2;
                        end  else if(residue < 5'd40)begin 
                            res_c[3:0]      <=  residue - 5'd30 ;
                            res_c[7:4]      <=  4'h3;
                        end  else if(residue < 5'd50)begin 
                            res_c[3:0]      <=  residue - 5'd40 ;
                            res_c[7:4]      <=  4'h4;
                        end 
                    nst     <=   IDLE;
            end
            RETURN:   begin 
                       if(get) begin 
                        res_c   <= 8'h00   ;
                        nst     <= IDLE  ;
                       end else begin 
                            res_c   <=  im_c    ;
                            nst     <=  GMONEY  ;
                        end 
            end  
        endcase
    end

    always @(posedge clk or negedge rstn) begin
        if(rstn == 1'b0) 
            cnt <= 5'd19;
        else if(cst == SHOPPING && nst == BACK)
            cnt <= cnt - 1'b1;
    end
     always @(posedge clk or negedge rstn) begin
        if(rstn == 1'b0) 
            alarm   <=  1'b0;
        else if(cnt < 5'd5)
            alarm   <= 1'b1;
        else 
            alarm   <=  1'b0;
    end

endmodule
module salem(
    input              clk      ,
    input              rstn     ,
    input [4:0]        swb      ,
    input [4:0]        mty      ,
    input              get      ,
    output reg         alarm    ,
    output reg [7:0]   gm_c     ,
    output reg [7:0]   im_c     ,
    output reg [7:0]   res_c    ,
    output[7:0]        dbg_good_price
);



    reg [5:0]       residue     ;

    wire [7:0]      item[0:19]  ;
    reg [2:0]       cst         ;
    reg [2:0]       nst         ;
    reg [4:0]       cnt         ;
    parameter  IDLE         = 3'b000;
    parameter  GMONEY       = 3'b001;
    parameter  SHOPPING     = 3'b010;
    parameter  BACK         = 3'b100;
    parameter  RETURN       = 3'b111;


    assign item[0]         = 8'h01;
    assign item[1]         = 8'h02;
    assign item[2]         = 8'h02;
    assign item[3]         = 8'h03;
    assign item[4]         = 8'h03;
    assign item[5]         = 8'h04;
    assign item[6]         = 8'h08;
    assign item[7]         = 8'h09;
    assign item[8]         = 8'h12;
    assign item[9]         = 8'h18;
    assign item[10]         = 8'h10;
    assign item[11]         = 8'h10;
    assign item[12]         = 8'h12;
    assign item[13]         = 8'h12;
    assign item[14]         = 8'h15;
    assign item[15]         = 8'h15;
    assign item[16]         = 8'h20;
    assign item[17]         = 8'h25;
    assign item[18]         = 8'h30;
    assign item[19]         = 8'h30;

    assign dbg_good_price = item[swb];

    always @(posedge clk or negedge rstn) begin
        if(rstn == 1'b0)
            gm_c      <=  8'h00   ;
        else if(swb < 5'd10)
            gm_c      <=  {3'b000,swb}     ;
        else if(swb < 5'd20) begin 
            gm_c[3:0]      <=  swb - 5'd10 ;
            gm_c[7:4]      <=  4'h1;
        end 
    end

    always @(posedge clk or negedge rstn) begin
        if(rstn == 1'b0)
            im_c      <=  8'h00   ;
        else begin case (mty)
                5'h1    :       im_c      <=  8'h01   ;
                5'h2    :       im_c      <=  8'h05   ;
                5'h4    :       im_c      <=  8'h10   ;
                5'h8    :       im_c      <=  8'h20   ;
                5'h10   :       im_c      <=  8'h50   ;
                default :       im_c      <=  8'h00   ;
             endcase
        end  
    end

    always @(posedge clk or negedge rstn) begin
        if(rstn == 1'b0)
            cst     <=  IDLE;
        else 
            cst     <=  nst;
    end

    always @(posedge clk or negedge rstn) begin
        if(rstn == 1'b0) begin 
            residue     <= 8'h00;
            res_c       <= 'd0;
            nst         <= IDLE ;   
        end else case(cst)
            IDLE:
                if(mty == 5'h00)
                    nst     <=   IDLE;
                else 
                    nst     <=    GMONEY;
            GMONEY: 
                if(im_c > item[swb] || im_c == item[swb]) 
                    nst     <=    SHOPPING;
                else
                    nst     <=   RETURN;
            SHOPPING:begin if(im_c > item[swb] || im_c == item[swb]) 
                                residue <=  (im_c[7:4] -item[swb][7:4])*4'ha + im_c[3:0] - item[swb][3:0];
                    nst     <=   BACK;
            end                              
            BACK:   begin 
                        if(residue < 5'd10)
                            res_c      <=  residue     ;
                        else if(residue < 5'd20) begin 
                            res_c[3:0]      <=  residue - 5'd10 ;
                            res_c[7:4]      <=  4'h1;
                        end  else if(residue < 5'd30)begin 
                            res_c[3:0]      <=  residue - 5'd20 ;
                            res_c[7:4]      <=  4'h2;
                        end  else if(residue < 5'd40)begin 
                            res_c[3:0]      <=  residue - 5'd30 ;
                            res_c[7:4]      <=  4'h3;
                        end  else if(residue < 5'd50)begin 
                            res_c[3:0]      <=  residue - 5'd40 ;
                            res_c[7:4]      <=  4'h4;
                        end 
                    nst     <=   IDLE;
            end
            RETURN:   begin 
                       if(get) begin 
                        res_c   <= 8'h00   ;
                        nst     <= IDLE  ;
                       end else begin 
                            res_c   <=  im_c    ;
                            nst     <=  GMONEY  ;
                        end 
            end  
        endcase
    end

    always @(posedge clk or negedge rstn) begin
        if(rstn == 1'b0) 
            cnt <= 5'd19;
        else if(cst == SHOPPING && nst == BACK)
            cnt <= cnt - 1'b1;
    end
     always @(posedge clk or negedge rstn) begin
        if(rstn == 1'b0) 
            alarm   <=  1'b0;
        else if(cnt < 5'd5)
            alarm   <= 1'b1;
        else 
            alarm   <=  1'b0;
    end

endmodule