data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/Counter16B.v
1: b"%Error: data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/Counter16B.v:42: Cannot find file containing module: 'Buffer16B'\n  Buffer16B buf0 (\n  ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new,data/full_repos/permissive/42815087/Buffer16B\n             data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new,data/full_repos/permissive/42815087/Buffer16B.v\n             data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new,data/full_repos/permissive/42815087/Buffer16B.sv\n             Buffer16B\n             Buffer16B.v\n             Buffer16B.sv\n             obj_dir/Buffer16B\n             obj_dir/Buffer16B.v\n             obj_dir/Buffer16B.sv\n%Error: Exiting due to 1 error(s)\n"
module Counter16B(
    input clockSig,
    input en,
    input [15:0] valIn,
    input set,
    input res,
    output [15:0] valOut,
    output [15:0] debugOut
  );
  
  reg [15:0] count = 16'h0000;
  reg firstCountFlag = 1'b0;
  


  wire wSetBuf;
  buf #(1) (wSetBuf, set);
  
  wire [15:0] wBuf;
  Buffer16B buf0 (
    .dIn(valIn[15:0]),
    .dOut(wBuf[15:0])
  );
  
  always @ (negedge clockSig) begin
    if(firstCountFlag == 1'b0) begin
      firstCountFlag <= 1'b1;
    end else begin
      if(res == 1'b1) count[15:0] <= 16'h0000;
      else if(wSetBuf == 1'b1) count[15:0] <= wBuf[15:0];
      else if (en == 1'b1) count[15:0] <= count[15:0] + 1'b1;
    end
    
  end
  
  assign debugOut[15:0] = count[15:0];
  assign valOut[15:0] = count[15:0];
  
endmodule
module Counter16B(
    input clockSig,
    input en,
    input [15:0] valIn,
    input set,
    input res,
    output [15:0] valOut,
    output [15:0] debugOut
  );

  
  reg [15:0] count = 16'h0000;
  reg firstCountFlag = 1'b0;
  


  wire wSetBuf;
  buf #(1) (wSetBuf, set);
  
  wire [15:0] wBuf;
  Buffer16B buf0 (
    .dIn(valIn[15:0]),
    .dOut(wBuf[15:0])
  );
  
  always @ (negedge clockSig) begin
    if(firstCountFlag == 1'b0) begin
      firstCountFlag <= 1'b1;
    end else begin
      if(res == 1'b1) count[15:0] <= 16'h0000;
      else if(wSetBuf == 1'b1) count[15:0] <= wBuf[15:0];
      else if (en == 1'b1) count[15:0] <= count[15:0] + 1'b1;
    end
    
  end
  
  assign debugOut[15:0] = count[15:0];
  assign valOut[15:0] = count[15:0];
  
endmodule