data/full_repos/permissive/471933052/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/471933052/verilog/rtl/user_proj_example.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/471933052/verilog/rtl/user_proj_example.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/471933052/verilog/rtl/user_proj_example.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/471933052/verilog/rtl/user_proj_example.v:311: syntax error, unexpected ')', expecting '['\nmodule delay_element #(parameter REG_WIDTH = 8) (clk,a_n_1,b_n_1,a_n,b_n,);\n                                                                         ^\n%Error: data/full_repos/permissive/471933052/verilog/rtl/user_proj_example.v:317: syntax error, unexpected output\n    output reg [REG_WIDTH-1:0] b_n;  \n    ^~~~~~\n%Error: data/full_repos/permissive/471933052/verilog/rtl/user_proj_example.v:319: syntax error, unexpected always\n    always @(posedge clk) begin\n    ^~~~~~\n%Error: Exiting due to 6 error(s)\n"
module main(clk,in,out1,out2,out3,out4,out5);

input [7:0] in;
input clk;
output [7:0] out1;
output [7:0] out2;
output [7:0] out3;
output [7:0] out4;
output [7:0] out5;

systolic_module dut(clk,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,out1,out2,out3,out4,out5);

endmodule
module main(clk,in,out1,out2,out3,out4,out5);


input [7:0] in;
input clk;
output [7:0] out1;
output [7:0] out2;
output [7:0] out3;
output [7:0] out4;
output [7:0] out5;

systolic_module dut(clk,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,out1,out2,out3,out4,out5);

endmodule