data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v
1: b'%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:116: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_X_WAIT\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   S_LOAD_X: next = LoadX ? S_LOAD_X_WAIT : S_LOAD_X;\n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:116: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s VARREF \'S_LOAD_X\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   S_LOAD_X: next = LoadX ? S_LOAD_X_WAIT : S_LOAD_X;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:117: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_X_WAIT\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   S_LOAD_X_WAIT: next = LoadX ? S_LOAD_X_WAIT : S_LOAD_Y_COLOUR;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:117: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s VARREF \'S_LOAD_Y_COLOUR\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   S_LOAD_X_WAIT: next = LoadX ? S_LOAD_X_WAIT : S_LOAD_Y_COLOUR;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:118: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_Y_WAIT\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   S_LOAD_Y_COLOUR: next = PlotBox ? S_LOAD_Y_WAIT : S_LOAD_Y_COLOUR;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:118: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s VARREF \'S_LOAD_Y_COLOUR\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   S_LOAD_Y_COLOUR: next = PlotBox ? S_LOAD_Y_WAIT : S_LOAD_Y_COLOUR;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:119: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_Y_WAIT\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   S_LOAD_Y_WAIT: next = PlotBox ? S_LOAD_Y_WAIT : S_DRAW;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:119: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s VARREF \'S_DRAW\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   S_LOAD_Y_WAIT: next = PlotBox ? S_LOAD_Y_WAIT : S_DRAW;\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:120: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_X\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   S_DRAW: next = LoadX ? S_LOAD_X : S_DRAW;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:120: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s VARREF \'S_DRAW\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   S_DRAW: next = LoadX ? S_LOAD_X : S_DRAW;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:121: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_LOAD_X\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   default next = S_LOAD_X;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:115: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_X\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n  case(now)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:115: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_X_WAIT\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n  case(now)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:115: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_Y_COLOUR\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n  case(now)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:115: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_Y_WAIT\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n  case(now)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:115: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'S_DRAW\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n  case(now)\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:128: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_LOAD_X\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n   now <= S_LOAD_X;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:140: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_X_WAIT\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n       case (now)\n       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:140: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_Y_COLOUR\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n       case (now)\n       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:140: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'S_DRAW\' generates 3 bits.\n                                                                                  : ... In instance part2.C0\n       case (now)\n       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:90: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                 : ... In instance part2.d0\n    X_Coordinates <= temp_x + Counter[1:0];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/ColoringVGA/coloringvga.v:91: Operator ADD expects 7 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                 : ... In instance part2.d0\n    Y_Coordinates <= temp_y + Counter[3:2];\n                            ^\n%Error: Exiting due to 22 warning(s)\n'
module controlpath(Clock, Resetn, LoadX, PlotBox, X_enable, Y_enable, Color_enable, Counter_enable, Plot);

	localparam S_LOAD_X = 3'd0, S_LOAD_X_WAIT = 3'd1, S_LOAD_Y_COLOUR = 3'd2, S_LOAD_Y_WAIT = 3'd3, S_DRAW = 3'd4;
	
	input Clock, Resetn, LoadX, PlotBox;
	
	output reg X_enable, Y_enable, Color_enable;
	output reg Counter_enable;
	output reg Plot;
	
	reg [3:0] now, next;
	
	
	always@(*)
	begin: state_table
		case(now)
			S_LOAD_X: next = LoadX ? S_LOAD_X_WAIT : S_LOAD_X;
			S_LOAD_X_WAIT: next = LoadX ? S_LOAD_X_WAIT : S_LOAD_Y_COLOUR;
			S_LOAD_Y_COLOUR: next = PlotBox ? S_LOAD_Y_WAIT : S_LOAD_Y_COLOUR;
			S_LOAD_Y_WAIT: next = PlotBox ? S_LOAD_Y_WAIT : S_DRAW;
			S_DRAW: next = LoadX ? S_LOAD_X : S_DRAW;
			default next = S_LOAD_X;
		endcase
	end
	
	always@(posedge Clock)
	begin
		if(Resetn == 1'b0)
			now <= S_LOAD_X;
		else 
			now <= next;
	end
	
	always @(*)
   begin: enable_signals
       X_enable = 0;
		 Y_enable = 0;
		 Color_enable = 0;
		 Plot = 0;

       case (now)
           S_LOAD_X_WAIT: 
					begin
						X_enable = 1'b1;
               end
           S_LOAD_Y_COLOUR: 
					begin
						Y_enable = 1'b1;
						Color_enable = 1'b1;
               end
           S_DRAW: 
					begin 
						Plot = 1'b1;
						Counter_enable = 1'b1;
					end
        endcase
    end 
	
	

endmodule
module controlpath(Clock, Resetn, LoadX, PlotBox, X_enable, Y_enable, Color_enable, Counter_enable, Plot);


	localparam S_LOAD_X = 3'd0, S_LOAD_X_WAIT = 3'd1, S_LOAD_Y_COLOUR = 3'd2, S_LOAD_Y_WAIT = 3'd3, S_DRAW = 3'd4;
	
	input Clock, Resetn, LoadX, PlotBox;
	
	output reg X_enable, Y_enable, Color_enable;
	output reg Counter_enable;
	output reg Plot;
	
	reg [3:0] now, next;
	
	
	always@(*)
	begin: state_table
		case(now)
			S_LOAD_X: next = LoadX ? S_LOAD_X_WAIT : S_LOAD_X;
			S_LOAD_X_WAIT: next = LoadX ? S_LOAD_X_WAIT : S_LOAD_Y_COLOUR;
			S_LOAD_Y_COLOUR: next = PlotBox ? S_LOAD_Y_WAIT : S_LOAD_Y_COLOUR;
			S_LOAD_Y_WAIT: next = PlotBox ? S_LOAD_Y_WAIT : S_DRAW;
			S_DRAW: next = LoadX ? S_LOAD_X : S_DRAW;
			default next = S_LOAD_X;
		endcase
	end
	
	always@(posedge Clock)
	begin
		if(Resetn == 1'b0)
			now <= S_LOAD_X;
		else 
			now <= next;
	end
	
	always @(*)
   begin: enable_signals
       X_enable = 0;
		 Y_enable = 0;
		 Color_enable = 0;
		 Plot = 0;

       case (now)
           S_LOAD_X_WAIT: 
					begin
						X_enable = 1'b1;
               end
           S_LOAD_Y_COLOUR: 
					begin
						Y_enable = 1'b1;
						Color_enable = 1'b1;
               end
           S_DRAW: 
					begin 
						Plot = 1'b1;
						Counter_enable = 1'b1;
					end
        endcase
    end 
	
	

endmodule