data/full_repos/permissive/411838135/rv/rviodtb.sv
1: b"%Error: data/full_repos/permissive/411838135/rv/rviodtb.sv:42: Cannot find file containing module: 'dtbrom'\n dtbrom dtbrom(.addr(r_addr), .data(rdata));\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/411838135/rv,data/full_repos/permissive/411838135/dtbrom\n             data/full_repos/permissive/411838135/rv,data/full_repos/permissive/411838135/dtbrom.v\n             data/full_repos/permissive/411838135/rv,data/full_repos/permissive/411838135/dtbrom.sv\n             dtbrom\n             dtbrom.v\n             dtbrom.sv\n             obj_dir/dtbrom\n             obj_dir/dtbrom.v\n             obj_dir/dtbrom.sv\n%Error: Exiting due to 1 error(s)\n"
module rv_io_dtb(
    input clk,
    input reset,

    input              addr_req,
    output             addr_ack,
    input			   sel,
    input        [11:0]addr,
    input              read,

    output             data_req,
    input              data_ack,
    output     [RV-1:0]rdata);

	
	parameter RV=64;

	reg [11:3]r_addr;
	reg		  r_req;
	assign data_req = r_req;

	dtbrom dtbrom(.addr(r_addr), .data(rdata));

	assign addr_ack = addr_req&&sel;

	always @(posedge clk) begin
		if (sel && read)
			r_addr <= addr[11:3];
		if (reset) begin
			r_req <= 0;
		end else
		if (addr_req && sel && read) begin
			r_req <= 1;
		end else
		if (data_ack)
			r_req <= 0;
	end
			
endmodule
module rv_io_dtb(
    input clk,
    input reset,

    input              addr_req,
    output             addr_ack,
    input			   sel,
    input        [11:0]addr,
    input              read,

    output             data_req,
    input              data_ack,
    output     [RV-1:0]rdata);


	
	parameter RV=64;

	reg [11:3]r_addr;
	reg		  r_req;
	assign data_req = r_req;

	dtbrom dtbrom(.addr(r_addr), .data(rdata));

	assign addr_ack = addr_req&&sel;

	always @(posedge clk) begin
		if (sel && read)
			r_addr <= addr[11:3];
		if (reset) begin
			r_req <= 0;
		end else
		if (addr_req && sel && read) begin
			r_req <= 1;
		end else
		if (data_ack)
			r_req <= 0;
	end
			
endmodule