data/full_repos/permissive/454159683/mux4to1f/mux4to1f.v
data/verilator_xmls/77457c5a-dc1f-41b1-a076-431d065e6bc5.xml
module mux4to1f(input a, b, c, d, input [1:0] sel, output out);
	assign out = (a & !sel[0] & !sel[1]) | 
		(b & !sel[1] & sel[0]) | 
		(c & sel[1] & !sel[0]) |
		(d & sel[1] & sel[0]);
endmodule
module mux4to1f(input a, b, c, d, input [1:0] sel, output out);

	assign out = (a & !sel[0] & !sel[1]) | 
		(b & !sel[1] & sel[0]) | 
		(c & sel[1] & !sel[0]) |
		(d & sel[1] & sel[0]);
endmodule