data/full_repos/permissive/420117502/Basic/2_Freq_Divider/Freq_Divider_3.v
data/verilator_xmls/465bcaee-a2f2-48f6-b4a9-de8db4982f28.xml
module FD3(
    input wire clk,
    output wire clk_div
);

parameter integer N=3;
reg [31:0] cnt;
reg clk_r;
always @ (edge clk) begin
    if( cnt == N-1'b1 ) cnt <= 'b0;
    else cnt <= cnt + 1'b1;
end

always @ (posedge clk) begin
    if(cnt == N-1'b1) clk_r<=~clk_r;
end

assign clk_div = clk_r;

initial begin
    cnt <='b0;
    clk_r<='b0;
end

endmodule
module FD3(
    input wire clk,
    output wire clk_div
);


parameter integer N=3;
reg [31:0] cnt;
reg clk_r;
always @ (edge clk) begin
    if( cnt == N-1'b1 ) cnt <= 'b0;
    else cnt <= cnt + 1'b1;
end

always @ (posedge clk) begin
    if(cnt == N-1'b1) clk_r<=~clk_r;
end

assign clk_div = clk_r;

initial begin
    cnt <='b0;
    clk_r<='b0;
end

endmodule