data/full_repos/permissive/419538859/lab3/lab3_1/sim/lab3_1.v
data/verilator_xmls/d89cb592-853a-462b-ac31-75bbc05039e0.xml
module 

module	clock(clk,reset,enable,count5,count4,count3,count2,count1,count0,carry);

input	clk,reset,enable;
output	[3:0]count5,count4,count3,count2,count1,count0;
output 	carry;
wire	[3:0]count5,count4,count3,count2,count1,count0;
wire 	carry,carry2,carry1,carry0,carry4;

assign 	carry = carry2 & carry1 & carry0;
assign	carry4=	carry0 & carry1;

count_00_23_bcd m6(clk, reset,  carry4, count5, count4, carry2);

count_00_59_bcd m7(clk, reset,  carry0, count3, count2, carry1);

count_00_59_bcd m8(clk, reset, enable, count1, count0, carry0); 

endmodule
module 

module	clock(clk,reset,enable,count5,count4,count3,count2,count1,count0,carry);


input	clk,reset,enable;
output	[3:0]count5,count4,count3,count2,count1,count0;
output 	carry;
wire	[3:0]count5,count4,count3,count2,count1,count0;
wire 	carry,carry2,carry1,carry0,carry4;

assign 	carry = carry2 & carry1 & carry0;
assign	carry4=	carry0 & carry1;

count_00_23_bcd m6(clk, reset,  carry4, count5, count4, carry2);

count_00_59_bcd m7(clk, reset,  carry0, count3, count2, carry1);

count_00_59_bcd m8(clk, reset, enable, count1, count0, carry0); 

endmodule