data/full_repos/permissive/502540587/TestBench/total_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/502540587/TestBench/total_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n            #5\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/502540587/TestBench/total_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n            #12.5\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/502540587/TestBench/total_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #17\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/502540587/TestBench/total_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/502540587/TestBench/total_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/502540587/TestBench/total_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/502540587/TestBench/total_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/502540587/TestBench/total_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/502540587/TestBench/total_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/502540587/TestBench/total_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Error: data/full_repos/permissive/502540587/TestBench/total_tb.v:19: Cannot find file containing module: \'GPUTop\'\n    GPUTop gpu(\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502540587/TestBench,data/full_repos/permissive/502540587/GPUTop\n             data/full_repos/permissive/502540587/TestBench,data/full_repos/permissive/502540587/GPUTop.v\n             data/full_repos/permissive/502540587/TestBench,data/full_repos/permissive/502540587/GPUTop.sv\n             GPUTop\n             GPUTop.v\n             GPUTop.sv\n             obj_dir/GPUTop\n             obj_dir/GPUTop.v\n             obj_dir/GPUTop.sv\n%Warning-WIDTH: data/full_repos/permissive/502540587/TestBench/total_tb.v:68: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h2000\' generates 26 bits.\n                                                                            : ... In instance total_tb\n        wb_adr = 26\'h2000;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/502540587/TestBench/total_tb.v:72: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h100\' generates 26 bits.\n                                                                            : ... In instance total_tb\n        wb_adr = 26\'h100;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/502540587/TestBench/total_tb.v:76: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h104\' generates 26 bits.\n                                                                            : ... In instance total_tb\n        wb_adr = 26\'h104;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/502540587/TestBench/total_tb.v:80: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'36\'hc\' generates 36 bits.\n                                                                            : ... In instance total_tb\n        wb_adr = 36\'hc;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/502540587/TestBench/total_tb.v:84: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h0\' generates 26 bits.\n                                                                            : ... In instance total_tb\n        wb_adr = 26\'h0;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/502540587/TestBench/total_tb.v:88: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h4\' generates 26 bits.\n                                                                            : ... In instance total_tb\n        wb_adr = 26\'h4;\n               ^\n%Error: Exiting due to 1 error(s), 16 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module total_tb ();
    reg reset_n;
    reg clk;
    reg clk_vga;

    reg wb_we;
    reg [31:0] wb_dat;
    reg [26:0] wb_adr;

    wire wb_ack;
    wire [3:0] oRed;
    wire [3:0] oGreen;
    wire [3:0] oBlue;
    wire oHs;
    wire oVs;

    GPUTop gpu(
        .clk_100MHz(clk),
        .reset_n(reset_n),
        .wb_we_i(wb_we),
        .wb_sel_i(4'hf),
        .wb_adr_i(wb_adr),
        .wb_dat_i(wb_dat),
        .wb_ack_o(wb_ack),

        .clk_vga(clk_vga),

        .oRed(oRed),
        .oBlue(oBlue),
        .oGreen(oGreen),
        .oHs(oHs),
        .oVs(oVs)
    );

    initial begin
        clk = 0;

        forever begin
            #5
            clk = ~clk;
        end
    end

    initial begin
        clk_vga = 0;

        forever begin
            #12.5
            clk_vga = ~clk_vga;
        end

    end

    initial begin
        reset_n = 0;

        wb_we = 0;
        wb_adr = 0;
        wb_dat = 1;

        #17
        reset_n = 1;

        #20
        wb_we = 1;
        wb_adr = 26'h2000;
        wb_dat = 32'hfcfefdfa;

        #20
        wb_adr = 26'h100;
        wb_dat = 32'h0103;

        #20
        wb_adr = 26'h104;
        wb_dat = 32'h2010;

        #20
        wb_adr = 36'hc;
        wb_dat = 1;

        #20
        wb_adr = 26'h0;
        wb_dat = 1;

        #20
        wb_adr = 26'h4;

        #20
        wb_we = 0;
    end
endmodule
module total_tb ();

    reg reset_n;
    reg clk;
    reg clk_vga;

    reg wb_we;
    reg [31:0] wb_dat;
    reg [26:0] wb_adr;

    wire wb_ack;
    wire [3:0] oRed;
    wire [3:0] oGreen;
    wire [3:0] oBlue;
    wire oHs;
    wire oVs;

    GPUTop gpu(
        .clk_100MHz(clk),
        .reset_n(reset_n),
        .wb_we_i(wb_we),
        .wb_sel_i(4'hf),
        .wb_adr_i(wb_adr),
        .wb_dat_i(wb_dat),
        .wb_ack_o(wb_ack),

        .clk_vga(clk_vga),

        .oRed(oRed),
        .oBlue(oBlue),
        .oGreen(oGreen),
        .oHs(oHs),
        .oVs(oVs)
    );

    initial begin
        clk = 0;

        forever begin
            #5
            clk = ~clk;
        end
    end

    initial begin
        clk_vga = 0;

        forever begin
            #12.5
            clk_vga = ~clk_vga;
        end

    end

    initial begin
        reset_n = 0;

        wb_we = 0;
        wb_adr = 0;
        wb_dat = 1;

        #17
        reset_n = 1;

        #20
        wb_we = 1;
        wb_adr = 26'h2000;
        wb_dat = 32'hfcfefdfa;

        #20
        wb_adr = 26'h100;
        wb_dat = 32'h0103;

        #20
        wb_adr = 26'h104;
        wb_dat = 32'h2010;

        #20
        wb_adr = 36'hc;
        wb_dat = 1;

        #20
        wb_adr = 26'h0;
        wb_dat = 1;

        #20
        wb_adr = 26'h4;

        #20
        wb_we = 0;
    end
endmodule