data/full_repos/permissive/515890445/ARM_SingleCycle/SingleCycle/ALU.v
1: b'%Warning-WIDTH: data/full_repos/permissive/515890445/ARM_SingleCycle/SingleCycle/ALU.v:25: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s NOT generates 4 bits.\n                                                                                         : ... In instance ALU\n assign Z   = ~Out;\n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/515890445/ARM_SingleCycle/SingleCycle/ALU.v:30: Cannot find file containing module: \'FullAdder_O\'\n FullAdder_O  #(\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/515890445/ARM_SingleCycle/SingleCycle,data/full_repos/permissive/515890445/FullAdder_O\n             data/full_repos/permissive/515890445/ARM_SingleCycle/SingleCycle,data/full_repos/permissive/515890445/FullAdder_O.v\n             data/full_repos/permissive/515890445/ARM_SingleCycle/SingleCycle,data/full_repos/permissive/515890445/FullAdder_O.sv\n             FullAdder_O\n             FullAdder_O.v\n             FullAdder_O.sv\n             obj_dir/FullAdder_O\n             obj_dir/FullAdder_O.v\n             obj_dir/FullAdder_O.sv\n%Error: data/full_repos/permissive/515890445/ARM_SingleCycle/SingleCycle/ALU.v:40: Cannot find file containing module: \'Mux2x1\'\n Mux2x1 #( \n ^~~~~~\n%Error: data/full_repos/permissive/515890445/ARM_SingleCycle/SingleCycle/ALU.v:50: Cannot find file containing module: \'Mux2x1\'\n Mux2x1 #( \n ^~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module ALU  #(
	parameter W = 4
)(
	input 	wire [W-1:0] 	In1,
	input 	wire [W-1:0] 	In2,
	input		wire [1:0]		OpSel, 
	output 	wire [W-1:0] 	Out,
	output 	wire [3:0]		Status
);


	wire needComp;
	wire [W-1:0] OutSrcLog;
	wire [W-1:0] FA_Out;
	wire Cout, CO, OVF, Z, N;



	assign needComp = ~OpSel[1] & OpSel[0];



	assign CO   = Cout & (~OpSel[1]);
	assign OVF 	= ~(In1[N-1]^In2[N-1]^OpSel[0]) & (In1[N-1]^Out[N-1])&~OpSel[1];
	assign Z  	= ~Out;
	assign N 	= Out[W-1];
	assign Status 	= {N, Z, CO, OVF};
	

	FullAdder_O  #(
		.W(W)
	) FullAdder_O_0 (
		.A(In1),
		.B(In2 ^ {W{needComp}}),
		.Cin(needComp),
		.Cout(Cout),
		.Out(FA_Out)
	);
		
	Mux2x1 #( 
		.W(W)
	) Mux2x1_ArOp  (
		.In1(In1&In2), 
		.In2(In1|In2), 
		.Sel(OpSel[0]),
		.Out(OutSrcLog)
	);


	Mux2x1 #( 
		.W(W)
	) Mux2x1_SelOut (
		.In1(FA_Out), 
		.In2(OutSrcLog), 
		.Sel(OpSel[1]),
		.Out(Out)
	);

endmodule
module ALU  #(
	parameter W = 4
)(
	input 	wire [W-1:0] 	In1,
	input 	wire [W-1:0] 	In2,
	input		wire [1:0]		OpSel, 
	output 	wire [W-1:0] 	Out,
	output 	wire [3:0]		Status
);



	wire needComp;
	wire [W-1:0] OutSrcLog;
	wire [W-1:0] FA_Out;
	wire Cout, CO, OVF, Z, N;



	assign needComp = ~OpSel[1] & OpSel[0];



	assign CO   = Cout & (~OpSel[1]);
	assign OVF 	= ~(In1[N-1]^In2[N-1]^OpSel[0]) & (In1[N-1]^Out[N-1])&~OpSel[1];
	assign Z  	= ~Out;
	assign N 	= Out[W-1];
	assign Status 	= {N, Z, CO, OVF};
	

	FullAdder_O  #(
		.W(W)
	) FullAdder_O_0 (
		.A(In1),
		.B(In2 ^ {W{needComp}}),
		.Cin(needComp),
		.Cout(Cout),
		.Out(FA_Out)
	);
		
	Mux2x1 #( 
		.W(W)
	) Mux2x1_ArOp  (
		.In1(In1&In2), 
		.In2(In1|In2), 
		.Sel(OpSel[0]),
		.Out(OutSrcLog)
	);


	Mux2x1 #( 
		.W(W)
	) Mux2x1_SelOut (
		.In1(FA_Out), 
		.In2(OutSrcLog), 
		.Sel(OpSel[1]),
		.Out(Out)
	);

endmodule