data/full_repos/permissive/524567962/designs/Adder/Full_Adder.sv
data/verilator_xmls/ed5ae850-a539-4b15-a888-48421b78bf29.xml
module Full_Adder(                                                              
  input logic   a, b, cin,                                                      
                                                                                
  output logic  y, cout                                                         
                                                                                
);                                                                              
                                                                                
  assign {cout, y}  = a + b + cin;                                              
                                                                                
endmodule
module Full_Adder(                                                              
  input logic   a, b, cin,                                                      
                                                                                
  output logic  y, cout                                                         
                                                                                
);
                                                                              
                                                                                
  assign {cout, y}  = a + b + cin;                                              
                                                                                
endmodule