data/full_repos/permissive/499137621/CheckPoint5-main/Control_flow.v
data/verilator_xmls/5132b6de-55be-4ebc-97ad-df923d0acd9c.xml
module Control_flow(opcode, ALUopcode, Rd, isOverflow, Rwe, ctrl_writeReg, ALUinB, preALUopcode, exception, Dwe_wire, Rwd);
	input[4:0]opcode, ALUopcode, Rd;
	input isOverflow;
	output Rwe, ALUinB;
	output[4:0] preALUopcode, ctrl_writeReg;
	output[31:0] exception;
	output Dwe_wire, Rwd;
	wire[4:0]reg_30;
	assign reg_30 = 5'b11110;
	
	reg Rwe, ALUinB;
	reg[4:0]preALUopcode, ctrl_writeReg;
	reg[31:0] exception;
	reg Rwd;
	
	always@(*)begin

		

		if ((opcode == 5'b00000) || (opcode == 5'b00101) || (opcode == 5'b01000) ||
		(opcode == 5'b10101)) begin
			Rwe <=  1'b1;
		end else if (opcode == 5'b00111 ||opcode == 5'b00001 || opcode == 5'b00010
		||opcode == 5'b00100 ||opcode ==5'b00110 || opcode == 5'b10110) begin
			Rwe <= 1'b0;
		end



		if (opcode == 5'b00101 || opcode == 5'b01000 || opcode == 5'b00111) begin
			ALUinB <= 1'b1;
		end else if (opcode == 5'b00000) begin
			ALUinB <= 1'b0;
		end else begin 
			ALUinB <= 1'b0;
		end
		

		if (opcode == 5'b00000)
			preALUopcode <= ALUopcode;

		else if (opcode == 5'b00010)
			preALUopcode <= 5'b00001;
		else
			preALUopcode <= 5'b00000;
			


		if (isOverflow && opcode == 5'b00000 && ALUopcode == 5'b00000)
			exception <= 32'b1;

		else if (isOverflow && opcode == 5'b00000 && ALUopcode == 5'b00001)
			exception <= 32'b11;

		else if (isOverflow && opcode == 5'b00101)
			exception <= 32'b10;
		else
			exception <= 32'b0;
		


		if (isOverflow && ((opcode == 5'b00000 && ALUopcode == 5'b00000) ||(opcode == 5'b00000 && ALUopcode == 5'b00001)
		|| (opcode == 5'b00101)))
			ctrl_writeReg <= reg_30;
		else if (opcode == 5'b10101)
			ctrl_writeReg <= reg_30;
		else
			ctrl_writeReg <= Rd;
			

		if (opcode == 5'b01000)
			Rwd <= 1'b1;
		else
			Rwd <= 1'b0;

	end
	

		assign Dwe_wire = ((opcode == 5'b00111)? 1'b1:1'b0);

endmodule
module Control_flow(opcode, ALUopcode, Rd, isOverflow, Rwe, ctrl_writeReg, ALUinB, preALUopcode, exception, Dwe_wire, Rwd);

	input[4:0]opcode, ALUopcode, Rd;
	input isOverflow;
	output Rwe, ALUinB;
	output[4:0] preALUopcode, ctrl_writeReg;
	output[31:0] exception;
	output Dwe_wire, Rwd;
	wire[4:0]reg_30;
	assign reg_30 = 5'b11110;
	
	reg Rwe, ALUinB;
	reg[4:0]preALUopcode, ctrl_writeReg;
	reg[31:0] exception;
	reg Rwd;
	
	always@(*)begin

		

		if ((opcode == 5'b00000) || (opcode == 5'b00101) || (opcode == 5'b01000) ||
		(opcode == 5'b10101)) begin
			Rwe <=  1'b1;
		end else if (opcode == 5'b00111 ||opcode == 5'b00001 || opcode == 5'b00010
		||opcode == 5'b00100 ||opcode ==5'b00110 || opcode == 5'b10110) begin
			Rwe <= 1'b0;
		end



		if (opcode == 5'b00101 || opcode == 5'b01000 || opcode == 5'b00111) begin
			ALUinB <= 1'b1;
		end else if (opcode == 5'b00000) begin
			ALUinB <= 1'b0;
		end else begin 
			ALUinB <= 1'b0;
		end
		

		if (opcode == 5'b00000)
			preALUopcode <= ALUopcode;

		else if (opcode == 5'b00010)
			preALUopcode <= 5'b00001;
		else
			preALUopcode <= 5'b00000;
			


		if (isOverflow && opcode == 5'b00000 && ALUopcode == 5'b00000)
			exception <= 32'b1;

		else if (isOverflow && opcode == 5'b00000 && ALUopcode == 5'b00001)
			exception <= 32'b11;

		else if (isOverflow && opcode == 5'b00101)
			exception <= 32'b10;
		else
			exception <= 32'b0;
		


		if (isOverflow && ((opcode == 5'b00000 && ALUopcode == 5'b00000) ||(opcode == 5'b00000 && ALUopcode == 5'b00001)
		|| (opcode == 5'b00101)))
			ctrl_writeReg <= reg_30;
		else if (opcode == 5'b10101)
			ctrl_writeReg <= reg_30;
		else
			ctrl_writeReg <= Rd;
			

		if (opcode == 5'b01000)
			Rwd <= 1'b1;
		else
			Rwd <= 1'b0;

	end
	

		assign Dwe_wire = ((opcode == 5'b00111)? 1'b1:1'b0);

endmodule