data/full_repos/permissive/515477729/source/shiftreg.v
1: b'%Warning-WIDTH: data/full_repos/permissive/515477729/source/shiftreg.v:11: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'15\'h0\' generates 15 bits.\n                                                                         : ... In instance shiftreg\n            data_out <= 15\'b0;\n                     ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module shiftreg (output reg [15:0] data_out, input [15:0] data_in, input s_in, clk, ld, clr, sft);


    always @(posedge clk)   begin
        if (clr) 
            data_out <= 15'b0;
        else if (ld)
            data_out <= data_in;
        else if (sft)
            data_out <= {s_in, data_out[15:1]};
    end

endmodule
module shiftreg (output reg [15:0] data_out, input [15:0] data_in, input s_in, clk, ld, clr, sft);



    always @(posedge clk)   begin
        if (clr) 
            data_out <= 15'b0;
        else if (ld)
            data_out <= data_in;
        else if (sft)
            data_out <= {s_in, data_out[15:1]};
    end

endmodule