data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/test/tb_axi_to_axi_lite.sv
1: b'%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/test/tb_axi_to_axi_lite.sv:13: Cannot find include file: axi/assign.svh\n`include "axi/assign.svh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/test,data/full_repos/permissive/509468557/axi/assign.svh\n             data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/test,data/full_repos/permissive/509468557/axi/assign.svh.v\n             data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/test,data/full_repos/permissive/509468557/axi/assign.svh.sv\n             axi/assign.svh\n             axi/assign.svh.v\n             axi/assign.svh.sv\n             obj_dir/axi/assign.svh\n             obj_dir/axi/assign.svh.v\n             obj_dir/axi/assign.svh.sv\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/test/tb_axi_to_axi_lite.sv:22: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n  localparam tCK = 1ns;\n                   ^~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/test/tb_axi_to_axi_lite.sv:40: Define or directive not defined: \'`AXI_LITE_ASSIGN\'\n  `AXI_LITE_ASSIGN(axi_lite_dv, axi_lite);\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/test/tb_axi_to_axi_lite.sv:40: syntax error, unexpected \'(\'\n  `AXI_LITE_ASSIGN(axi_lite_dv, axi_lite);\n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/test/tb_axi_to_axi_lite.sv:56: Define or directive not defined: \'`AXI_ASSIGN\'\n  `AXI_ASSIGN(axi, axi_dv);\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/test/tb_axi_to_axi_lite.sv:56: syntax error, unexpected \'(\'\n  `AXI_ASSIGN(axi, axi_dv);\n              ^~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/test/tb_axi_to_axi_lite.sv:66: syntax error, unexpected ::, expecting \'.\' or \';\'\n  typedef axi_test::axi_lite_driver #(.AW(AW), .DW(DW), .TA(TA), .TT(TT)) axi_lite_drv_t;\n                  ^~\n                                                                                                                               : ... Perhaps \'axi_test\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/test/tb_axi_to_axi_lite.sv:67: syntax error, unexpected ::, expecting \'.\' or \';\'\n  typedef axi_test::axi_driver #(.AW(AW), .DW(DW), .IW(IW), .UW(UW), .TA(TA), .TT(TT)) axi_drv_t;\n                  ^~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/test/tb_axi_to_axi_lite.sv:68: syntax error, unexpected \'=\', expecting \',\' or \';\'\n  axi_lite_drv_t axi_lite_drv = new(axi_lite_dv);\n                              ^\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/test/tb_axi_to_axi_lite.sv:69: syntax error, unexpected \'=\', expecting \',\' or \';\'\n  axi_drv_t axi_drv = new(axi_dv);\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/test/tb_axi_to_axi_lite.sv:72: Unsupported: Ignoring delay on this delayed statement.\n    #tCK;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/test/tb_axi_to_axi_lite.sv:74: Unsupported: Ignoring delay on this delayed statement.\n    #tCK;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/test/tb_axi_to_axi_lite.sv:76: Unsupported: Ignoring delay on this delayed statement.\n    #tCK;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/test/tb_axi_to_axi_lite.sv:79: Unsupported: Ignoring delay on this delayed statement.\n      #(tCK/2);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/test/tb_axi_to_axi_lite.sv:81: Unsupported: Ignoring delay on this delayed statement.\n      #(tCK/2);\n      ^\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/test/tb_axi_to_axi_lite.sv:86: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n    automatic axi_drv_t::ax_beat_t ax = new;\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/test/tb_axi_to_axi_lite.sv:91: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/test/tb_axi_to_axi_lite.sv:93: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n    ax.randomize();\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/test/tb_axi_to_axi_lite.sv:93: syntax error, unexpected \'(\'\n    ax.randomize();\n                 ^\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/test/tb_axi_to_axi_lite.sv:94: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n    w.randomize();\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/test/tb_axi_to_axi_lite.sv:94: syntax error, unexpected \'(\'\n    w.randomize();\n                ^\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/test/tb_axi_to_axi_lite.sv:100: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n    ax.randomize();\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/test/tb_axi_to_axi_lite.sv:100: syntax error, unexpected \'(\'\n    ax.randomize();\n                 ^\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/test/tb_axi_to_axi_lite.sv:104: syntax error, unexpected \'@\'\n    repeat (4) @(posedge clk);\n               ^\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/test/tb_axi_to_axi_lite.sv:114: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/test/tb_axi_to_axi_lite.sv:118: syntax error, unexpected ::, expecting \')\'\n    axi_lite_drv.send_b(axi_pkg::RESP_OKAY);\n                               ^~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/axi/test/tb_axi_to_axi_lite.sv:121: syntax error, unexpected ::, expecting \')\'\n    axi_lite_drv.send_r(\'0, axi_pkg::RESP_OKAY);\n                                   ^~\n%Error: Exiting due to 22 error(s), 5 warning(s)\n'
module tb_axi_to_axi_lite;

  parameter AW = 32;
  parameter DW = 32;
  parameter IW = 8;
  parameter UW = 8;

  localparam tCK = 1ns;
  localparam TA = tCK * 1/4;
  localparam TT = tCK * 3/4;

  logic clk = 0;
  logic rst = 1;
  logic done = 0;

  AXI_LITE_DV #(
    .AXI_ADDR_WIDTH(AW),
    .AXI_DATA_WIDTH(DW)
  ) axi_lite_dv(clk);

  AXI_LITE #(
    .AXI_ADDR_WIDTH(AW),
    .AXI_DATA_WIDTH(DW)
  ) axi_lite();

  `AXI_LITE_ASSIGN(axi_lite_dv, axi_lite);

  AXI_BUS_DV #(
    .AXI_ADDR_WIDTH(AW),
    .AXI_DATA_WIDTH(DW),
    .AXI_ID_WIDTH(IW),
    .AXI_USER_WIDTH(UW)
  ) axi_dv(clk);

  AXI_BUS #(
    .AXI_ADDR_WIDTH(AW),
    .AXI_DATA_WIDTH(DW),
    .AXI_ID_WIDTH(IW),
    .AXI_USER_WIDTH(UW)
  ) axi();

  `AXI_ASSIGN(axi, axi_dv);

  axi_to_axi_lite i_dut (
    .clk_i      ( clk      ),
    .rst_ni     ( rst      ),
    .testmode_i ( 1'b0     ),
    .in         ( axi      ),
    .out        ( axi_lite )
  );

  typedef axi_test::axi_lite_driver #(.AW(AW), .DW(DW), .TA(TA), .TT(TT)) axi_lite_drv_t;
  typedef axi_test::axi_driver #(.AW(AW), .DW(DW), .IW(IW), .UW(UW), .TA(TA), .TT(TT)) axi_drv_t;
  axi_lite_drv_t axi_lite_drv = new(axi_lite_dv);
  axi_drv_t axi_drv = new(axi_dv);

  initial begin
    #tCK;
    rst <= 0;
    #tCK;
    rst <= 1;
    #tCK;
    while (!done) begin
      clk <= 1;
      #(tCK/2);
      clk <= 0;
      #(tCK/2);
    end
  end

  initial begin
    automatic axi_drv_t::ax_beat_t ax = new;
    automatic axi_drv_t::w_beat_t w = new;
    automatic axi_drv_t::b_beat_t b = new;
    automatic axi_drv_t::r_beat_t r = new;
    axi_drv.reset_master();
    @(posedge clk);

    ax.randomize();
    w.randomize();
    w.last = 1'b1;
    axi_drv.send_aw(ax);
    axi_drv.send_w(w);
    axi_drv.recv_b(b);

    ax.randomize();
    axi_drv.send_ar(ax);
    axi_drv.recv_r(r);

    repeat (4) @(posedge clk);
    done = 1;
  end

  initial begin
    automatic logic [AW-1:0] addr;
    automatic logic [DW-1:0] data;
    automatic logic [DW/8-1:0] strb;

    axi_lite_drv.reset_slave();
    @(posedge clk);

    axi_lite_drv.recv_aw(addr);
    axi_lite_drv.recv_w(data, strb);
    axi_lite_drv.send_b(axi_pkg::RESP_OKAY);

    axi_lite_drv.recv_ar(addr);
    axi_lite_drv.send_r('0, axi_pkg::RESP_OKAY);
  end

endmodule
module tb_axi_to_axi_lite;


  parameter AW = 32;
  parameter DW = 32;
  parameter IW = 8;
  parameter UW = 8;

  localparam tCK = 1ns;
  localparam TA = tCK * 1/4;
  localparam TT = tCK * 3/4;

  logic clk = 0;
  logic rst = 1;
  logic done = 0;

  AXI_LITE_DV #(
    .AXI_ADDR_WIDTH(AW),
    .AXI_DATA_WIDTH(DW)
  ) axi_lite_dv(clk);

  AXI_LITE #(
    .AXI_ADDR_WIDTH(AW),
    .AXI_DATA_WIDTH(DW)
  ) axi_lite();

  `AXI_LITE_ASSIGN(axi_lite_dv, axi_lite);

  AXI_BUS_DV #(
    .AXI_ADDR_WIDTH(AW),
    .AXI_DATA_WIDTH(DW),
    .AXI_ID_WIDTH(IW),
    .AXI_USER_WIDTH(UW)
  ) axi_dv(clk);

  AXI_BUS #(
    .AXI_ADDR_WIDTH(AW),
    .AXI_DATA_WIDTH(DW),
    .AXI_ID_WIDTH(IW),
    .AXI_USER_WIDTH(UW)
  ) axi();

  `AXI_ASSIGN(axi, axi_dv);

  axi_to_axi_lite i_dut (
    .clk_i      ( clk      ),
    .rst_ni     ( rst      ),
    .testmode_i ( 1'b0     ),
    .in         ( axi      ),
    .out        ( axi_lite )
  );

  typedef axi_test::axi_lite_driver #(.AW(AW), .DW(DW), .TA(TA), .TT(TT)) axi_lite_drv_t;
  typedef axi_test::axi_driver #(.AW(AW), .DW(DW), .IW(IW), .UW(UW), .TA(TA), .TT(TT)) axi_drv_t;
  axi_lite_drv_t axi_lite_drv = new(axi_lite_dv);
  axi_drv_t axi_drv = new(axi_dv);

  initial begin
    #tCK;
    rst <= 0;
    #tCK;
    rst <= 1;
    #tCK;
    while (!done) begin
      clk <= 1;
      #(tCK/2);
      clk <= 0;
      #(tCK/2);
    end
  end

  initial begin
    automatic axi_drv_t::ax_beat_t ax = new;
    automatic axi_drv_t::w_beat_t w = new;
    automatic axi_drv_t::b_beat_t b = new;
    automatic axi_drv_t::r_beat_t r = new;
    axi_drv.reset_master();
    @(posedge clk);

    ax.randomize();
    w.randomize();
    w.last = 1'b1;
    axi_drv.send_aw(ax);
    axi_drv.send_w(w);
    axi_drv.recv_b(b);

    ax.randomize();
    axi_drv.send_ar(ax);
    axi_drv.recv_r(r);

    repeat (4) @(posedge clk);
    done = 1;
  end

  initial begin
    automatic logic [AW-1:0] addr;
    automatic logic [DW-1:0] data;
    automatic logic [DW/8-1:0] strb;

    axi_lite_drv.reset_slave();
    @(posedge clk);

    axi_lite_drv.recv_aw(addr);
    axi_lite_drv.recv_w(data, strb);
    axi_lite_drv.send_b(axi_pkg::RESP_OKAY);

    axi_lite_drv.recv_ar(addr);
    axi_lite_drv.send_r('0, axi_pkg::RESP_OKAY);
  end

endmodule