data/full_repos/permissive/488739248/rtl/registers/AlphaMissionCore_Registers_sync.sv
1: b"%Error: data/full_repos/permissive/488739248/rtl/registers/AlphaMissionCore_Registers_sync.sv:43: Cannot find file containing module: 'ttl_74174_sync'\n    ttl_74174_sync b11\n    ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/488739248/rtl/registers,data/full_repos/permissive/488739248/ttl_74174_sync\n             data/full_repos/permissive/488739248/rtl/registers,data/full_repos/permissive/488739248/ttl_74174_sync.v\n             data/full_repos/permissive/488739248/rtl/registers,data/full_repos/permissive/488739248/ttl_74174_sync.sv\n             ttl_74174_sync\n             ttl_74174_sync.v\n             ttl_74174_sync.sv\n             obj_dir/ttl_74174_sync\n             obj_dir/ttl_74174_sync.v\n             obj_dir/ttl_74174_sync.sv\n%Error: data/full_repos/permissive/488739248/rtl/registers/AlphaMissionCore_Registers_sync.sv:60: Cannot find file containing module: 'ttl_74174_sync'\n    ttl_74174_sync a5\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/488739248/rtl/registers/AlphaMissionCore_Registers_sync.sv:71: Cannot find file containing module: 'ttl_74174_sync'\n    ttl_74174_sync a6\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/488739248/rtl/registers/AlphaMissionCore_Registers_sync.sv:81: Cannot find file containing module: 'ttl_74273_sync'\n    ttl_74273_sync b8(.RESETn(reset), .CLRn(1'b1), .Clk(clk), .Cen(FSY), .D(vdin_r), .Q(FY));\n    ^~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module AlphaMissionCore_Registers_sync(
  input wire VIDEO_RSTn,
  input wire reset,
  input wire clk,
  input wire MSB,
  input wire [7:0] VD_in,


  output logic INV,
  output logic INVn,
  output logic B1X8,
  output logic FX8,
  output logic B1Y8,
  output logic FY8,

  input wire BACK1_TILE_COLOR_BANK,

  output logic [1:0] BACK1_TILE_BANK,
  output logic [3:0] BACK1_COLOR_BANK,

  input wire SIDE_COLOR_BANK,

  output logic [2:0] SIDE_COL_BANK,

  input wire FSY,
  output logic [7:0] FY
);
    logic b11_q2, b11_inv;

    reg [7:0] vdin_r;

     always @(posedge clk) begin
        vdin_r <= VD_in;
    end

    ttl_74174_sync b11
    (
        .Reset_n(reset),
        .Clk(clk),
        .Cen(MSB),
        .Clr_n(1'b1),
        .D(vdin_r[5:0]),
        .Q({b11_inv, B1X8, FX8, b11_q2, B1Y8, FY8})
    );





    assign INV = b11_inv;
    assign INVn = ~b11_inv;

    ttl_74174_sync a5
    (
        .Reset_n(reset),
        .Clk(clk),
        .Cen(BACK1_TILE_COLOR_BANK),
        .Clr_n(1'b1),
        .D(vdin_r[5:0]),
        .Q({BACK1_TILE_BANK,BACK1_COLOR_BANK})
    );

    logic a6_d5, a6_d4, a6_d3;
    ttl_74174_sync a6
    (
        .Reset_n(reset),
        .Clk(clk),
        .Cen(SIDE_COLOR_BANK),
        .Clr_n(1'b1),
        .D(vdin_r[5:0]),
        .Q({a6_d5, a6_d4, a6_d3, SIDE_COL_BANK})
    );

    ttl_74273_sync b8(.RESETn(reset), .CLRn(1'b1), .Clk(clk), .Cen(FSY), .D(vdin_r), .Q(FY));
endmodule
module AlphaMissionCore_Registers_sync(
  input wire VIDEO_RSTn,
  input wire reset,
  input wire clk,
  input wire MSB,
  input wire [7:0] VD_in,


  output logic INV,
  output logic INVn,
  output logic B1X8,
  output logic FX8,
  output logic B1Y8,
  output logic FY8,

  input wire BACK1_TILE_COLOR_BANK,

  output logic [1:0] BACK1_TILE_BANK,
  output logic [3:0] BACK1_COLOR_BANK,

  input wire SIDE_COLOR_BANK,

  output logic [2:0] SIDE_COL_BANK,

  input wire FSY,
  output logic [7:0] FY
);

    logic b11_q2, b11_inv;

    reg [7:0] vdin_r;

     always @(posedge clk) begin
        vdin_r <= VD_in;
    end

    ttl_74174_sync b11
    (
        .Reset_n(reset),
        .Clk(clk),
        .Cen(MSB),
        .Clr_n(1'b1),
        .D(vdin_r[5:0]),
        .Q({b11_inv, B1X8, FX8, b11_q2, B1Y8, FY8})
    );





    assign INV = b11_inv;
    assign INVn = ~b11_inv;

    ttl_74174_sync a5
    (
        .Reset_n(reset),
        .Clk(clk),
        .Cen(BACK1_TILE_COLOR_BANK),
        .Clr_n(1'b1),
        .D(vdin_r[5:0]),
        .Q({BACK1_TILE_BANK,BACK1_COLOR_BANK})
    );

    logic a6_d5, a6_d4, a6_d3;
    ttl_74174_sync a6
    (
        .Reset_n(reset),
        .Clk(clk),
        .Cen(SIDE_COLOR_BANK),
        .Clr_n(1'b1),
        .D(vdin_r[5:0]),
        .Q({a6_d5, a6_d4, a6_d3, SIDE_COL_BANK})
    );

    ttl_74273_sync b8(.RESETn(reset), .CLRn(1'b1), .Clk(clk), .Cen(FSY), .D(vdin_r), .Q(FY));
endmodule