data/full_repos/permissive/42434302/ivltests/vhdl_shift.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/vhdl_shift.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #1;        \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/42434302/ivltests/vhdl_shift.v:24: Cannot find file containing module: \'shifter\'\nshifter dut(inp, out_srl, out_sll, out_sra, out_sla);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/42434302/ivltests,data/full_repos/permissive/42434302/shifter\n             data/full_repos/permissive/42434302/ivltests,data/full_repos/permissive/42434302/shifter.v\n             data/full_repos/permissive/42434302/ivltests,data/full_repos/permissive/42434302/shifter.sv\n             shifter\n             shifter.v\n             shifter.sv\n             obj_dir/shifter\n             obj_dir/shifter.v\n             obj_dir/shifter.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module shifter_test;
reg signed [7:0] inp, out_srl, out_sll, out_sra, out_sla;
shifter dut(inp, out_srl, out_sll, out_sra, out_sla);

initial begin
  inp = 8'b11101100;
  #1;

  if(out_srl !== 8'b01110110)
  begin
    $display("FAILED 1");
    $finish();
  end

  if(out_sll !== 8'b11011000)
  begin
    $display("FAILED 2");
    $finish();
  end

  if(out_sra !== 8'b11110110)
  begin
    $display("FAILED 3");
    $finish();
  end

  if(out_sla !== 8'b11011000)
  begin
    $display("FAILED 4");
    $finish();
  end

  $display("PASSED");
end
endmodule
module shifter_test;

reg signed [7:0] inp, out_srl, out_sll, out_sra, out_sla;
shifter dut(inp, out_srl, out_sll, out_sra, out_sla);

initial begin
  inp = 8'b11101100;
  #1;

  if(out_srl !== 8'b01110110)
  begin
    $display("FAILED 1");
    $finish();
  end

  if(out_sll !== 8'b11011000)
  begin
    $display("FAILED 2");
    $finish();
  end

  if(out_sra !== 8'b11110110)
  begin
    $display("FAILED 3");
    $finish();
  end

  if(out_sla !== 8'b11011000)
  begin
    $display("FAILED 4");
    $finish();
  end

  $display("PASSED");
end
endmodule