data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v
1: b"%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:572: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit (\n    ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference,data/full_repos/permissive/493019833/AsyncRegInit\n             data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference,data/full_repos/permissive/493019833/AsyncRegInit.v\n             data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference,data/full_repos/permissive/493019833/AsyncRegInit.sv\n             AsyncRegInit\n             AsyncRegInit.v\n             AsyncRegInit.sv\n             obj_dir/AsyncRegInit\n             obj_dir/AsyncRegInit.v\n             obj_dir/AsyncRegInit.sv\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:584: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit_1 (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:596: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit_2 (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:608: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit_3 (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:440: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:452: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit_1 (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:464: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit_2 (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:476: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit_3 (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:302: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:314: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit_1 (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:326: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit_2 (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:338: Cannot find file containing module: 'AsyncRegInit'\n    AsyncRegInit AsyncRegInit_3 (\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:524: Cannot find file containing module: 'FakeBBClk'\n    FakeBBClk bb (\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:392: Cannot find file containing module: 'FakeBBClk'\n    FakeBBClk bb (\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/TopModuleWithClks/reference/TopModuleWithClks.v:254: Cannot find file containing module: 'FakeBBClk'\n    FakeBBClk bb (\n    ^~~~~~~~~\n%Error: Exiting due to 15 error(s)\n"
module TopModuleWithClks(
    input clock,
    input reset,
    output io_gen1_bbOutClk_0,
    output io_gen1_bbOutClk_1,
    output io_gen1_bbOutClk_2,
    output io_gen1_clkDivOut_0,
    output io_gen1_clkDivOut_1,
    output io_gen1_clkDivOut_2,
    output io_gen2_bbOutClk_0,
    output io_gen2_bbOutClk_1,
    output io_gen2_bbOutClk_2,
    output io_gen2_clkDivOut_0,
    output io_gen2_clkDivOut_1,
    output io_gen2_clkDivOut_2,
    output io_gen3_bbOutClk_0,
    output io_gen3_bbOutClk_1,
    output io_gen3_bbOutClk_2,
    output io_gen3_clkDivOut_0,
    output io_gen3_clkDivOut_1,
    output io_gen3_clkDivOut_2,
    input io_fakeClk1,
    input io_fakeClk2
);
    wire _gen1__clock;
    wire _gen1__reset;
    wire _gen1__io_inClk;
    wire _gen1__io_bbOutClk_0;
    wire _gen1__io_bbOutClk_1;
    wire _gen1__io_bbOutClk_2;
    wire _gen1__io_clkDivOut_0;
    wire _gen1__io_clkDivOut_1;
    wire _gen1__io_clkDivOut_2;
    ModWithNestedClk gen1 (
        .clock(_gen1__clock),
        .reset(_gen1__reset),
        .io_inClk(_gen1__io_inClk),
        .io_bbOutClk_0(_gen1__io_bbOutClk_0),
        .io_bbOutClk_1(_gen1__io_bbOutClk_1),
        .io_bbOutClk_2(_gen1__io_bbOutClk_2),
        .io_clkDivOut_0(_gen1__io_clkDivOut_0),
        .io_clkDivOut_1(_gen1__io_clkDivOut_1),
        .io_clkDivOut_2(_gen1__io_clkDivOut_2)
    );
    wire _T_63;
    ASUINT #(.width(1)) asuint_1 (
        .y(_T_63),
        .in(_gen1__io_bbOutClk_0)
    );
    wire _T_64;
    ASUINT #(.width(1)) asuint_2 (
        .y(_T_64),
        .in(_gen1__io_bbOutClk_1)
    );
    wire _T_65;
    ASUINT #(.width(1)) asuint_3 (
        .y(_T_65),
        .in(_gen1__io_bbOutClk_2)
    );
    wire _T_68_0;
    wire _T_68_1;
    wire _T_68_2;
    wire _T_74;
    ASUINT #(.width(1)) asuint_4 (
        .y(_T_74),
        .in(_gen1__io_clkDivOut_0)
    );
    wire _T_75;
    ASUINT #(.width(1)) asuint_5 (
        .y(_T_75),
        .in(_gen1__io_clkDivOut_1)
    );
    wire _T_76;
    ASUINT #(.width(1)) asuint_6 (
        .y(_T_76),
        .in(_gen1__io_clkDivOut_2)
    );
    wire _T_79_0;
    wire _T_79_1;
    wire _T_79_2;
    wire _gen2__clock;
    wire _gen2__reset;
    wire _gen2__io_inClk;
    wire _gen2__io_bbOutClk_0;
    wire _gen2__io_bbOutClk_1;
    wire _gen2__io_bbOutClk_2;
    wire _gen2__io_clkDivOut_0;
    wire _gen2__io_clkDivOut_1;
    wire _gen2__io_clkDivOut_2;
    ModWithNestedClk_1 gen2 (
        .clock(_gen2__clock),
        .reset(_gen2__reset),
        .io_inClk(_gen2__io_inClk),
        .io_bbOutClk_0(_gen2__io_bbOutClk_0),
        .io_bbOutClk_1(_gen2__io_bbOutClk_1),
        .io_bbOutClk_2(_gen2__io_bbOutClk_2),
        .io_clkDivOut_0(_gen2__io_clkDivOut_0),
        .io_clkDivOut_1(_gen2__io_clkDivOut_1),
        .io_clkDivOut_2(_gen2__io_clkDivOut_2)
    );
    wire _T_85;
    ASUINT #(.width(1)) asuint_7 (
        .y(_T_85),
        .in(_gen2__io_bbOutClk_0)
    );
    wire _T_86;
    ASUINT #(.width(1)) asuint_8 (
        .y(_T_86),
        .in(_gen2__io_bbOutClk_1)
    );
    wire _T_87;
    ASUINT #(.width(1)) asuint_9 (
        .y(_T_87),
        .in(_gen2__io_bbOutClk_2)
    );
    wire _T_90_0;
    wire _T_90_1;
    wire _T_90_2;
    wire _T_96;
    ASUINT #(.width(1)) asuint_10 (
        .y(_T_96),
        .in(_gen2__io_clkDivOut_0)
    );
    wire _T_97;
    ASUINT #(.width(1)) asuint_11 (
        .y(_T_97),
        .in(_gen2__io_clkDivOut_1)
    );
    wire _T_98;
    ASUINT #(.width(1)) asuint_12 (
        .y(_T_98),
        .in(_gen2__io_clkDivOut_2)
    );
    wire _T_101_0;
    wire _T_101_1;
    wire _T_101_2;
    wire _gen3__clock;
    wire _gen3__reset;
    wire _gen3__io_inClk;
    wire _gen3__io_bbOutClk_0;
    wire _gen3__io_bbOutClk_1;
    wire _gen3__io_bbOutClk_2;
    wire _gen3__io_clkDivOut_0;
    wire _gen3__io_clkDivOut_1;
    wire _gen3__io_clkDivOut_2;
    ModWithNestedClk_2 gen3 (
        .clock(_gen3__clock),
        .reset(_gen3__reset),
        .io_inClk(_gen3__io_inClk),
        .io_bbOutClk_0(_gen3__io_bbOutClk_0),
        .io_bbOutClk_1(_gen3__io_bbOutClk_1),
        .io_bbOutClk_2(_gen3__io_bbOutClk_2),
        .io_clkDivOut_0(_gen3__io_clkDivOut_0),
        .io_clkDivOut_1(_gen3__io_clkDivOut_1),
        .io_clkDivOut_2(_gen3__io_clkDivOut_2)
    );
    wire _T_107;
    ASUINT #(.width(1)) asuint_13 (
        .y(_T_107),
        .in(_gen3__io_bbOutClk_0)
    );
    wire _T_108;
    ASUINT #(.width(1)) asuint_14 (
        .y(_T_108),
        .in(_gen3__io_bbOutClk_1)
    );
    wire _T_109;
    ASUINT #(.width(1)) asuint_15 (
        .y(_T_109),
        .in(_gen3__io_bbOutClk_2)
    );
    wire _T_112_0;
    wire _T_112_1;
    wire _T_112_2;
    wire _T_118;
    ASUINT #(.width(1)) asuint_16 (
        .y(_T_118),
        .in(_gen3__io_clkDivOut_0)
    );
    wire _T_119;
    ASUINT #(.width(1)) asuint_17 (
        .y(_T_119),
        .in(_gen3__io_clkDivOut_1)
    );
    wire _T_120;
    ASUINT #(.width(1)) asuint_18 (
        .y(_T_120),
        .in(_gen3__io_clkDivOut_2)
    );
    wire _T_123_0;
    wire _T_123_1;
    wire _T_123_2;
    assign _T_101_0 = _T_96;
    assign _T_101_1 = _T_97;
    assign _T_101_2 = _T_98;
    assign _T_112_0 = _T_107;
    assign _T_112_1 = _T_108;
    assign _T_112_2 = _T_109;
    assign _T_123_0 = _T_118;
    assign _T_123_1 = _T_119;
    assign _T_123_2 = _T_120;
    assign _T_68_0 = _T_63;
    assign _T_68_1 = _T_64;
    assign _T_68_2 = _T_65;
    assign _T_79_0 = _T_74;
    assign _T_79_1 = _T_75;
    assign _T_79_2 = _T_76;
    assign _T_90_0 = _T_85;
    assign _T_90_1 = _T_86;
    assign _T_90_2 = _T_87;
    assign _gen1__clock = clock;
    assign _gen1__io_inClk = clock;
    assign _gen1__reset = reset;
    assign _gen2__clock = clock;
    assign _gen2__io_inClk = _gen1__io_clkDivOut_2;
    assign _gen2__reset = reset;
    assign _gen3__clock = clock;
    assign _gen3__io_inClk = _gen1__io_clkDivOut_2;
    assign _gen3__reset = reset;
    assign io_gen1_bbOutClk_0 = _T_68_0;
    assign io_gen1_bbOutClk_1 = _T_68_1;
    assign io_gen1_bbOutClk_2 = _T_68_2;
    assign io_gen1_clkDivOut_0 = _T_79_0;
    assign io_gen1_clkDivOut_1 = _T_79_1;
    assign io_gen1_clkDivOut_2 = _T_79_2;
    assign io_gen2_bbOutClk_0 = _T_90_0;
    assign io_gen2_bbOutClk_1 = _T_90_1;
    assign io_gen2_bbOutClk_2 = _T_90_2;
    assign io_gen2_clkDivOut_0 = _T_101_0;
    assign io_gen2_clkDivOut_1 = _T_101_1;
    assign io_gen2_clkDivOut_2 = _T_101_2;
    assign io_gen3_bbOutClk_0 = _T_112_0;
    assign io_gen3_bbOutClk_1 = _T_112_1;
    assign io_gen3_bbOutClk_2 = _T_112_2;
    assign io_gen3_clkDivOut_0 = _T_123_0;
    assign io_gen3_clkDivOut_1 = _T_123_1;
    assign io_gen3_clkDivOut_2 = _T_123_2;
endmodule
module TopModuleWithClks(
    input clock,
    input reset,
    output io_gen1_bbOutClk_0,
    output io_gen1_bbOutClk_1,
    output io_gen1_bbOutClk_2,
    output io_gen1_clkDivOut_0,
    output io_gen1_clkDivOut_1,
    output io_gen1_clkDivOut_2,
    output io_gen2_bbOutClk_0,
    output io_gen2_bbOutClk_1,
    output io_gen2_bbOutClk_2,
    output io_gen2_clkDivOut_0,
    output io_gen2_clkDivOut_1,
    output io_gen2_clkDivOut_2,
    output io_gen3_bbOutClk_0,
    output io_gen3_bbOutClk_1,
    output io_gen3_bbOutClk_2,
    output io_gen3_clkDivOut_0,
    output io_gen3_clkDivOut_1,
    output io_gen3_clkDivOut_2,
    input io_fakeClk1,
    input io_fakeClk2
);

    wire _gen1__clock;
    wire _gen1__reset;
    wire _gen1__io_inClk;
    wire _gen1__io_bbOutClk_0;
    wire _gen1__io_bbOutClk_1;
    wire _gen1__io_bbOutClk_2;
    wire _gen1__io_clkDivOut_0;
    wire _gen1__io_clkDivOut_1;
    wire _gen1__io_clkDivOut_2;
    ModWithNestedClk gen1 (
        .clock(_gen1__clock),
        .reset(_gen1__reset),
        .io_inClk(_gen1__io_inClk),
        .io_bbOutClk_0(_gen1__io_bbOutClk_0),
        .io_bbOutClk_1(_gen1__io_bbOutClk_1),
        .io_bbOutClk_2(_gen1__io_bbOutClk_2),
        .io_clkDivOut_0(_gen1__io_clkDivOut_0),
        .io_clkDivOut_1(_gen1__io_clkDivOut_1),
        .io_clkDivOut_2(_gen1__io_clkDivOut_2)
    );
    wire _T_63;
    ASUINT #(.width(1)) asuint_1 (
        .y(_T_63),
        .in(_gen1__io_bbOutClk_0)
    );
    wire _T_64;
    ASUINT #(.width(1)) asuint_2 (
        .y(_T_64),
        .in(_gen1__io_bbOutClk_1)
    );
    wire _T_65;
    ASUINT #(.width(1)) asuint_3 (
        .y(_T_65),
        .in(_gen1__io_bbOutClk_2)
    );
    wire _T_68_0;
    wire _T_68_1;
    wire _T_68_2;
    wire _T_74;
    ASUINT #(.width(1)) asuint_4 (
        .y(_T_74),
        .in(_gen1__io_clkDivOut_0)
    );
    wire _T_75;
    ASUINT #(.width(1)) asuint_5 (
        .y(_T_75),
        .in(_gen1__io_clkDivOut_1)
    );
    wire _T_76;
    ASUINT #(.width(1)) asuint_6 (
        .y(_T_76),
        .in(_gen1__io_clkDivOut_2)
    );
    wire _T_79_0;
    wire _T_79_1;
    wire _T_79_2;
    wire _gen2__clock;
    wire _gen2__reset;
    wire _gen2__io_inClk;
    wire _gen2__io_bbOutClk_0;
    wire _gen2__io_bbOutClk_1;
    wire _gen2__io_bbOutClk_2;
    wire _gen2__io_clkDivOut_0;
    wire _gen2__io_clkDivOut_1;
    wire _gen2__io_clkDivOut_2;
    ModWithNestedClk_1 gen2 (
        .clock(_gen2__clock),
        .reset(_gen2__reset),
        .io_inClk(_gen2__io_inClk),
        .io_bbOutClk_0(_gen2__io_bbOutClk_0),
        .io_bbOutClk_1(_gen2__io_bbOutClk_1),
        .io_bbOutClk_2(_gen2__io_bbOutClk_2),
        .io_clkDivOut_0(_gen2__io_clkDivOut_0),
        .io_clkDivOut_1(_gen2__io_clkDivOut_1),
        .io_clkDivOut_2(_gen2__io_clkDivOut_2)
    );
    wire _T_85;
    ASUINT #(.width(1)) asuint_7 (
        .y(_T_85),
        .in(_gen2__io_bbOutClk_0)
    );
    wire _T_86;
    ASUINT #(.width(1)) asuint_8 (
        .y(_T_86),
        .in(_gen2__io_bbOutClk_1)
    );
    wire _T_87;
    ASUINT #(.width(1)) asuint_9 (
        .y(_T_87),
        .in(_gen2__io_bbOutClk_2)
    );
    wire _T_90_0;
    wire _T_90_1;
    wire _T_90_2;
    wire _T_96;
    ASUINT #(.width(1)) asuint_10 (
        .y(_T_96),
        .in(_gen2__io_clkDivOut_0)
    );
    wire _T_97;
    ASUINT #(.width(1)) asuint_11 (
        .y(_T_97),
        .in(_gen2__io_clkDivOut_1)
    );
    wire _T_98;
    ASUINT #(.width(1)) asuint_12 (
        .y(_T_98),
        .in(_gen2__io_clkDivOut_2)
    );
    wire _T_101_0;
    wire _T_101_1;
    wire _T_101_2;
    wire _gen3__clock;
    wire _gen3__reset;
    wire _gen3__io_inClk;
    wire _gen3__io_bbOutClk_0;
    wire _gen3__io_bbOutClk_1;
    wire _gen3__io_bbOutClk_2;
    wire _gen3__io_clkDivOut_0;
    wire _gen3__io_clkDivOut_1;
    wire _gen3__io_clkDivOut_2;
    ModWithNestedClk_2 gen3 (
        .clock(_gen3__clock),
        .reset(_gen3__reset),
        .io_inClk(_gen3__io_inClk),
        .io_bbOutClk_0(_gen3__io_bbOutClk_0),
        .io_bbOutClk_1(_gen3__io_bbOutClk_1),
        .io_bbOutClk_2(_gen3__io_bbOutClk_2),
        .io_clkDivOut_0(_gen3__io_clkDivOut_0),
        .io_clkDivOut_1(_gen3__io_clkDivOut_1),
        .io_clkDivOut_2(_gen3__io_clkDivOut_2)
    );
    wire _T_107;
    ASUINT #(.width(1)) asuint_13 (
        .y(_T_107),
        .in(_gen3__io_bbOutClk_0)
    );
    wire _T_108;
    ASUINT #(.width(1)) asuint_14 (
        .y(_T_108),
        .in(_gen3__io_bbOutClk_1)
    );
    wire _T_109;
    ASUINT #(.width(1)) asuint_15 (
        .y(_T_109),
        .in(_gen3__io_bbOutClk_2)
    );
    wire _T_112_0;
    wire _T_112_1;
    wire _T_112_2;
    wire _T_118;
    ASUINT #(.width(1)) asuint_16 (
        .y(_T_118),
        .in(_gen3__io_clkDivOut_0)
    );
    wire _T_119;
    ASUINT #(.width(1)) asuint_17 (
        .y(_T_119),
        .in(_gen3__io_clkDivOut_1)
    );
    wire _T_120;
    ASUINT #(.width(1)) asuint_18 (
        .y(_T_120),
        .in(_gen3__io_clkDivOut_2)
    );
    wire _T_123_0;
    wire _T_123_1;
    wire _T_123_2;
    assign _T_101_0 = _T_96;
    assign _T_101_1 = _T_97;
    assign _T_101_2 = _T_98;
    assign _T_112_0 = _T_107;
    assign _T_112_1 = _T_108;
    assign _T_112_2 = _T_109;
    assign _T_123_0 = _T_118;
    assign _T_123_1 = _T_119;
    assign _T_123_2 = _T_120;
    assign _T_68_0 = _T_63;
    assign _T_68_1 = _T_64;
    assign _T_68_2 = _T_65;
    assign _T_79_0 = _T_74;
    assign _T_79_1 = _T_75;
    assign _T_79_2 = _T_76;
    assign _T_90_0 = _T_85;
    assign _T_90_1 = _T_86;
    assign _T_90_2 = _T_87;
    assign _gen1__clock = clock;
    assign _gen1__io_inClk = clock;
    assign _gen1__reset = reset;
    assign _gen2__clock = clock;
    assign _gen2__io_inClk = _gen1__io_clkDivOut_2;
    assign _gen2__reset = reset;
    assign _gen3__clock = clock;
    assign _gen3__io_inClk = _gen1__io_clkDivOut_2;
    assign _gen3__reset = reset;
    assign io_gen1_bbOutClk_0 = _T_68_0;
    assign io_gen1_bbOutClk_1 = _T_68_1;
    assign io_gen1_bbOutClk_2 = _T_68_2;
    assign io_gen1_clkDivOut_0 = _T_79_0;
    assign io_gen1_clkDivOut_1 = _T_79_1;
    assign io_gen1_clkDivOut_2 = _T_79_2;
    assign io_gen2_bbOutClk_0 = _T_90_0;
    assign io_gen2_bbOutClk_1 = _T_90_1;
    assign io_gen2_bbOutClk_2 = _T_90_2;
    assign io_gen2_clkDivOut_0 = _T_101_0;
    assign io_gen2_clkDivOut_1 = _T_101_1;
    assign io_gen2_clkDivOut_2 = _T_101_2;
    assign io_gen3_bbOutClk_0 = _T_112_0;
    assign io_gen3_bbOutClk_1 = _T_112_1;
    assign io_gen3_bbOutClk_2 = _T_112_2;
    assign io_gen3_clkDivOut_0 = _T_123_0;
    assign io_gen3_clkDivOut_1 = _T_123_1;
    assign io_gen3_clkDivOut_2 = _T_123_2;
endmodule