data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/dram_test/dram_test_tb.sv
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/dram_test/dram_test_tb.sv:13: Cannot find include file: sim_clks_rsts.vh\n`include "sim_clks_rsts.vh" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/dram_test,data/full_repos/permissive/447976230/sim_clks_rsts.vh\n             data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/dram_test,data/full_repos/permissive/447976230/sim_clks_rsts.vh.v\n             data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/dram_test,data/full_repos/permissive/447976230/sim_clks_rsts.vh.sv\n             sim_clks_rsts.vh\n             sim_clks_rsts.vh.v\n             sim_clks_rsts.vh.sv\n             obj_dir/sim_clks_rsts.vh\n             obj_dir/sim_clks_rsts.vh.v\n             obj_dir/sim_clks_rsts.vh.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/dram_test/dram_test_tb.sv:14: Cannot find include file: sim_exec_report.vh\n`include "sim_exec_report.vh" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/dram_test/dram_test_tb.sv:17: Define or directive not defined: \'`TEST_BENCH_INIT\'\n  `TEST_BENCH_INIT("dram_test_tb",3,1)\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/dram_test/dram_test_tb.sv:17: syntax error, unexpected \'(\'\n  `TEST_BENCH_INIT("dram_test_tb",3,1)\n                   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/dram_test/dram_test_tb.sv:20: Define or directive not defined: \'`DEFINE_CLK\'\n  `DEFINE_CLK(sys_clk, 10, 50)     \n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/dram_test/dram_test_tb.sv:21: Define or directive not defined: \'`DEFINE_CLK\'\n  `DEFINE_CLK(ref_clk, 5, 50)      \n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/dram_test/dram_test_tb.sv:22: Define or directive not defined: \'`DEFINE_RESET\'\n  `DEFINE_RESET(sys_rst, 0, 250000)   \n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/dram_test/dram_test_tb.sv:103: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                  : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Wait for reset");\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/dram_test/dram_test_tb.sv:103: syntax error, unexpected \';\'\n    `TEST_CASE_START("Wait for reset");\n                                      ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/dram_test/dram_test_tb.sv:104: syntax error, unexpected \'@\'\n    while (sys_rst) @(posedge sys_clk);\n                    ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/dram_test/dram_test_tb.sv:105: Define or directive not defined: \'`TEST_CASE_DONE\'\n    `TEST_CASE_DONE((~sys_rst));\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/dram_test/dram_test_tb.sv:105: syntax error, unexpected \';\'\n    `TEST_CASE_DONE((~sys_rst));\n                               ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/dram_test/dram_test_tb.sv:107: syntax error, unexpected \'@\'\n    repeat (200) @(posedge sys_clk);\n                 ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/dram_test/dram_test_tb.sv:109: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                  : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Wait for initial calibration to complete");\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/dram_test/dram_test_tb.sv:109: syntax error, unexpected \';\'\n    `TEST_CASE_START("Wait for initial calibration to complete");\n                                                                ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/dram_test/dram_test_tb.sv:110: syntax error, unexpected \'@\'\n    while (calib_complete !== 1\'b1) @(posedge sys_clk);\n                                    ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/dram_test/dram_test_tb.sv:111: Define or directive not defined: \'`TEST_CASE_DONE\'\n    `TEST_CASE_DONE(calib_complete);\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/dram_test/dram_test_tb.sv:111: syntax error, unexpected \';\'\n    `TEST_CASE_DONE(calib_complete);\n                                   ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/dram_test/dram_test_tb.sv:113: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                  : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Run for a while, then check for error");\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/dram_test/dram_test_tb.sv:113: syntax error, unexpected \';\'\n    `TEST_CASE_START("Run for a while, then check for error");\n                                                             ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/dram_test/dram_test_tb.sv:114: syntax error, unexpected \'@\'\n    repeat (2_000_000) @(posedge sys_clk);\n                       ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/dram_test/dram_test_tb.sv:115: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(tg_compare_error_reg == 1\'b0, "Test generator reported error");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/dram_test/dram_test_tb.sv:115: syntax error, unexpected \',\'\n    `ASSERT_ERROR(tg_compare_error_reg == 1\'b0, "Test generator reported error");\n                                              ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/dram_test/dram_test_tb.sv:116: Define or directive not defined: \'`TEST_CASE_DONE\'\n    `TEST_CASE_DONE(1\'b1);\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/dram_test/dram_test_tb.sv:116: syntax error, unexpected \';\'\n    `TEST_CASE_DONE(1\'b1);\n                         ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/e31x/sim/dram_test/dram_test_tb.sv:117: Define or directive not defined: \'`TEST_BENCH_DONE\'\n    `TEST_BENCH_DONE;\n    ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 26 error(s)\n'
module dram_test_tb();
  `TEST_BENCH_INIT("dram_test_tb",`NUM_TEST_CASES,`NS_PER_TICK)


  `DEFINE_CLK(sys_clk, 10, 50)
  `DEFINE_CLK(ref_clk, 5, 50)
  `DEFINE_RESET(sys_rst, 0, 250000)


  wire calib_complete;

  wire [15:0]   ddr3_dq;
  wire [1:0]    ddr3_dqs_n;
  wire [1:0]    ddr3_dqs_p;
  wire [14:0]   ddr3_addr;
  wire [2:0]    ddr3_ba;
  wire          ddr3_ras_n;
  wire          ddr3_cas_n;
  wire          ddr3_we_n;
  wire          ddr3_reset_n;
  wire [0:0]    ddr3_ck_p;
  wire [0:0]    ddr3_ck_n;
  wire [0:0]    ddr3_cke;
  wire [0:0]    ddr3_cs_n;
  wire [3:0]    ddr3_dm;
  wire [0:0]    ddr3_odt;

  ddr3_model #(
    .DEBUG(1)
  ) sdram_i0 (
    .rst_n    (ddr3_reset_n),
    .ck       (ddr3_ck_p),
    .ck_n     (ddr3_ck_n),
    .cke      (ddr3_cke),
    .cs_n     (1'b0),
    .ras_n    (ddr3_ras_n),
    .cas_n    (ddr3_cas_n),
    .we_n     (ddr3_we_n),
    .dm_tdqs  (ddr3_dm[1:0]),
    .ba       (ddr3_ba),
    .addr     (ddr3_addr),
    .dq       (ddr3_dq[15:0]),
    .dqs      (ddr3_dqs_p[1:0]),
    .dqs_n    (ddr3_dqs_n[1:0]),
    .tdqs_n   (),
    .odt      (ddr3_odt)
  );

  example_top inst_example_top
  (
    .ddr3_dq                       (ddr3_dq),
    .ddr3_dqs_n                    (ddr3_dqs_n),
    .ddr3_dqs_p                    (ddr3_dqs_p),
    .ddr3_addr                     (ddr3_addr),
    .ddr3_ba                       (ddr3_ba),
    .ddr3_ras_n                    (ddr3_ras_n),
    .ddr3_cas_n                    (ddr3_cas_n),
    .ddr3_we_n                     (ddr3_we_n),
    .ddr3_reset_n                  (ddr3_reset_n),
    .ddr3_ck_p                     (ddr3_ck_p),
    .ddr3_ck_n                     (ddr3_ck_n),
    .ddr3_cke                      (ddr3_cke),
    .ddr3_dm                       (ddr3_dm),
    .ddr3_odt                      (ddr3_odt),
    .sys_clk_i                     (sys_clk),
    .clk_ref_i                     (ref_clk),
    .tg_compare_error              (tg_compare_error),
    .init_calib_complete           (calib_complete),
    .sys_rst                       (sys_rst)
  );




  reg tg_compare_error_reg;
  always @ (posedge sys_clk)
    if (sys_rst)
      tg_compare_error_reg = 1'b0;
    else
      tg_compare_error_reg = tg_compare_error | tg_compare_error_reg;





  initial begin : tb_main

    `TEST_CASE_START("Wait for reset");
    while (sys_rst) @(posedge sys_clk);
    `TEST_CASE_DONE((~sys_rst));

    repeat (200) @(posedge sys_clk);

    `TEST_CASE_START("Wait for initial calibration to complete");
    while (calib_complete !== 1'b1) @(posedge sys_clk);
    `TEST_CASE_DONE(calib_complete);

    `TEST_CASE_START("Run for a while, then check for error");
    repeat (2_000_000) @(posedge sys_clk);
    `ASSERT_ERROR(tg_compare_error_reg == 1'b0, "Test generator reported error");
    `TEST_CASE_DONE(1'b1);
    `TEST_BENCH_DONE;

  end

endmodule
module dram_test_tb();

  `TEST_BENCH_INIT("dram_test_tb",`NUM_TEST_CASES,`NS_PER_TICK)


  `DEFINE_CLK(sys_clk, 10, 50)
  `DEFINE_CLK(ref_clk, 5, 50)
  `DEFINE_RESET(sys_rst, 0, 250000)


  wire calib_complete;

  wire [15:0]   ddr3_dq;
  wire [1:0]    ddr3_dqs_n;
  wire [1:0]    ddr3_dqs_p;
  wire [14:0]   ddr3_addr;
  wire [2:0]    ddr3_ba;
  wire          ddr3_ras_n;
  wire          ddr3_cas_n;
  wire          ddr3_we_n;
  wire          ddr3_reset_n;
  wire [0:0]    ddr3_ck_p;
  wire [0:0]    ddr3_ck_n;
  wire [0:0]    ddr3_cke;
  wire [0:0]    ddr3_cs_n;
  wire [3:0]    ddr3_dm;
  wire [0:0]    ddr3_odt;

  ddr3_model #(
    .DEBUG(1)
  ) sdram_i0 (
    .rst_n    (ddr3_reset_n),
    .ck       (ddr3_ck_p),
    .ck_n     (ddr3_ck_n),
    .cke      (ddr3_cke),
    .cs_n     (1'b0),
    .ras_n    (ddr3_ras_n),
    .cas_n    (ddr3_cas_n),
    .we_n     (ddr3_we_n),
    .dm_tdqs  (ddr3_dm[1:0]),
    .ba       (ddr3_ba),
    .addr     (ddr3_addr),
    .dq       (ddr3_dq[15:0]),
    .dqs      (ddr3_dqs_p[1:0]),
    .dqs_n    (ddr3_dqs_n[1:0]),
    .tdqs_n   (),
    .odt      (ddr3_odt)
  );

  example_top inst_example_top
  (
    .ddr3_dq                       (ddr3_dq),
    .ddr3_dqs_n                    (ddr3_dqs_n),
    .ddr3_dqs_p                    (ddr3_dqs_p),
    .ddr3_addr                     (ddr3_addr),
    .ddr3_ba                       (ddr3_ba),
    .ddr3_ras_n                    (ddr3_ras_n),
    .ddr3_cas_n                    (ddr3_cas_n),
    .ddr3_we_n                     (ddr3_we_n),
    .ddr3_reset_n                  (ddr3_reset_n),
    .ddr3_ck_p                     (ddr3_ck_p),
    .ddr3_ck_n                     (ddr3_ck_n),
    .ddr3_cke                      (ddr3_cke),
    .ddr3_dm                       (ddr3_dm),
    .ddr3_odt                      (ddr3_odt),
    .sys_clk_i                     (sys_clk),
    .clk_ref_i                     (ref_clk),
    .tg_compare_error              (tg_compare_error),
    .init_calib_complete           (calib_complete),
    .sys_rst                       (sys_rst)
  );




  reg tg_compare_error_reg;
  always @ (posedge sys_clk)
    if (sys_rst)
      tg_compare_error_reg = 1'b0;
    else
      tg_compare_error_reg = tg_compare_error | tg_compare_error_reg;





  initial begin : tb_main

    `TEST_CASE_START("Wait for reset");
    while (sys_rst) @(posedge sys_clk);
    `TEST_CASE_DONE((~sys_rst));

    repeat (200) @(posedge sys_clk);

    `TEST_CASE_START("Wait for initial calibration to complete");
    while (calib_complete !== 1'b1) @(posedge sys_clk);
    `TEST_CASE_DONE(calib_complete);

    `TEST_CASE_START("Run for a while, then check for error");
    repeat (2_000_000) @(posedge sys_clk);
    `ASSERT_ERROR(tg_compare_error_reg == 1'b0, "Test generator reported error");
    `TEST_CASE_DONE(1'b1);
    `TEST_BENCH_DONE;

  end

endmodule