data/full_repos/permissive/458935738/common/ir_modules.v
1: b'%Warning-WIDTH: data/full_repos/permissive/458935738/common/ir_modules.v:152: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s SEL generates 16 bits.\n                                                                            : ... In instance IRcontrol.ch7\n            ttd <= timerttd[15:0];\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/458935738/common/ir_modules.v:27: Cannot find file containing module: \'pwm\'\n    pwm irevenLED (clk, ir_evenLED_en, 16\'d16000, ir_evenLED);\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/458935738/common,data/full_repos/permissive/458935738/pwm\n             data/full_repos/permissive/458935738/common,data/full_repos/permissive/458935738/pwm.v\n             data/full_repos/permissive/458935738/common,data/full_repos/permissive/458935738/pwm.sv\n             pwm\n             pwm.v\n             pwm.sv\n             obj_dir/pwm\n             obj_dir/pwm.v\n             obj_dir/pwm.sv\n%Error: data/full_repos/permissive/458935738/common/ir_modules.v:28: Cannot find file containing module: \'pwm\'\n    pwm iroddLED (clk, ir_oddLED_en, 16\'d16000, ir_oddLED);\n    ^~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module timer (
    input clk, enable, stop,
    output reg[31:0] counter
    );
    
    always @(posedge clk)
    begin
        if (!enable)
            counter <= 0;
        else if (stop)
            counter <= counter;
        else
            counter <= counter + 1;
    end
endmodule
module timer (
    input clk, enable, stop,
    output reg[31:0] counter
    );

    
    always @(posedge clk)
    begin
        if (!enable)
            counter <= 0;
        else if (stop)
            counter <= counter;
        else
            counter <= counter + 1;
    end
endmodule