data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/ADC_AVERAGE_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/ADC_AVERAGE_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #H_period;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/ADC_AVERAGE_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #H_period;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/ADC_AVERAGE_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #F_period;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/ADC_AVERAGE_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #AVE_period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/ADC_AVERAGE_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #F_period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/ADC_AVERAGE_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #F_period;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/ADC_AVERAGE_tb.v:15: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h2\' generates 16 bits.\n                                                                                                  : ... In instance ADC_AVERAGE_tb\nreg [32-1 :0] TIMER_OFFSET = 16\'h0000_0002;\n                             ^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/ADC_AVERAGE_tb.v:16: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h80\' generates 16 bits.\n                                                                                                  : ... In instance ADC_AVERAGE_tb\nreg [32-1 :0] TIME_VALUE =  16\'h0000_0080;\n                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/ADC_AVERAGE_tb.v:27: Cannot find file containing module: \'ADC_DAC_LOOP\'\nADC_DAC_LOOP #(\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb,data/full_repos/permissive/503053625/ADC_DAC_LOOP\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb,data/full_repos/permissive/503053625/ADC_DAC_LOOP.v\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb,data/full_repos/permissive/503053625/ADC_DAC_LOOP.sv\n             ADC_DAC_LOOP\n             ADC_DAC_LOOP.v\n             ADC_DAC_LOOP.sv\n             obj_dir/ADC_DAC_LOOP\n             obj_dir/ADC_DAC_LOOP.v\n             obj_dir/ADC_DAC_LOOP.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ADC_AVERAGE_tb;
localparam NUM_SAMPS = 4096;
localparam H_period=2;
localparam F_period=4;
localparam AVE_period = F_period*1024;
localparam FP_WIDTH = 32;
localparam GPIO_WIDTH = 32;
localparam ADC_WIDTH = 12;
localparam DAC_WIDTH = 14;

reg ADC_CLK = 1'b0;
reg [11:0] DATA_IN=12'h000;

wire DONE;
reg [32-1 :0] TIMER_OFFSET = 16'h0000_0002;
reg [32-1 :0] TIME_VALUE =  16'h0000_0080;
reg [32-1 :0] ADC_CAL_GAIN =  32'h0001_0000;
reg [1023:0] CFG_IN = {{896{1'b0}}, 32'h0000_0000, 32'h0001_0000, 32'hFFFF_FBD1, 32'h0001_1D8F};
wire [14-1:0] DACA_CODE_WIRE_OUT;
wire [14-1:0] DACB_CODE_WIRE_OUT;
wire [12-1:0] ADC_CODE_WIRE_OUT;

reg [32-1:0] GPIO_REG = 32'h8000_0000;
wire [32-1:0] GPIO_WIRE;


ADC_DAC_LOOP #(
    .FP_WIDTH(FP_WIDTH), 
    .ADC_WIDTH(ADC_WIDTH), 
    .DAC_WIDTH(DAC_WIDTH), 
    .GPIO_WIDTH(GPIO_WIDTH)
) ADC_DAC_LOOP0 (
    .CFG_IN(CFG_IN),
    .ADC_DATA_IN(DATA_IN),
    .ADC_CLK(ADC_CLK),
    .GP_IN(GPIO_REG),
    .GP_OUT(GPIO_WIRE),
    .DONE(DONE),
    .DACA_CODE_OUT(DACA_CODE_WIRE_OUT),
    .DACB_CODE_OUT(DACB_CODE_WIRE_OUT)
);

always begin
    ADC_CLK = 1'b0;
    #H_period;
    ADC_CLK = 1'b1;
    #H_period;
end
initial
begin
    #F_period;

    repeat(NUM_SAMPS) begin
        #AVE_period;

        #F_period;
        #F_period;
        DATA_IN = DATA_IN + 1;
    end

    $finish;
end
endmodule
module ADC_AVERAGE_tb;

localparam NUM_SAMPS = 4096;
localparam H_period=2;
localparam F_period=4;
localparam AVE_period = F_period*1024;
localparam FP_WIDTH = 32;
localparam GPIO_WIDTH = 32;
localparam ADC_WIDTH = 12;
localparam DAC_WIDTH = 14;

reg ADC_CLK = 1'b0;
reg [11:0] DATA_IN=12'h000;

wire DONE;
reg [32-1 :0] TIMER_OFFSET = 16'h0000_0002;
reg [32-1 :0] TIME_VALUE =  16'h0000_0080;
reg [32-1 :0] ADC_CAL_GAIN =  32'h0001_0000;
reg [1023:0] CFG_IN = {{896{1'b0}}, 32'h0000_0000, 32'h0001_0000, 32'hFFFF_FBD1, 32'h0001_1D8F};
wire [14-1:0] DACA_CODE_WIRE_OUT;
wire [14-1:0] DACB_CODE_WIRE_OUT;
wire [12-1:0] ADC_CODE_WIRE_OUT;

reg [32-1:0] GPIO_REG = 32'h8000_0000;
wire [32-1:0] GPIO_WIRE;


ADC_DAC_LOOP #(
    .FP_WIDTH(FP_WIDTH), 
    .ADC_WIDTH(ADC_WIDTH), 
    .DAC_WIDTH(DAC_WIDTH), 
    .GPIO_WIDTH(GPIO_WIDTH)
) ADC_DAC_LOOP0 (
    .CFG_IN(CFG_IN),
    .ADC_DATA_IN(DATA_IN),
    .ADC_CLK(ADC_CLK),
    .GP_IN(GPIO_REG),
    .GP_OUT(GPIO_WIRE),
    .DONE(DONE),
    .DACA_CODE_OUT(DACA_CODE_WIRE_OUT),
    .DACB_CODE_OUT(DACB_CODE_WIRE_OUT)
);

always begin
    ADC_CLK = 1'b0;
    #H_period;
    ADC_CLK = 1'b1;
    #H_period;
end
initial
begin
    #F_period;

    repeat(NUM_SAMPS) begin
        #AVE_period;

        #F_period;
        #F_period;
        DATA_IN = DATA_IN + 1;
    end

    $finish;
end
endmodule