data/full_repos/permissive/477054115/Mips16_singlecycle/InstrMem.v
data/verilator_xmls/22c005f6-cfbb-4d1f-99fe-125ec31a412e.xml
module instr_mem
 (  
      input     [15:0]     pc,  
      output wire     [15:0]          instruction  
 );  
      wire [2 : 0] rom_addr = pc[3 : 1];  

      reg [15:0] rom[7:0];  
      initial  
      begin
          rom[0] = 16'b0000000000000000;
          rom[1] = 16'hE48F;
          rom[2] = 16'hE904;
          rom[3] = 16'hF206;
          rom[4] = 16'hFB30;
          rom[5] = 16'h0535;
          rom[6] = 16'h1156;
          rom[7] = 16'h1907;
          








                 
      end  
      assign instruction = (pc[15:0] < 48 )? rom[rom_addr[2:0]]: 16'd0;  
 endmodule
module instr_mem
 (  
      input     [15:0]     pc,  
      output wire     [15:0]          instruction  
 );
  
      wire [2 : 0] rom_addr = pc[3 : 1];  

      reg [15:0] rom[7:0];  
      initial  
      begin
          rom[0] = 16'b0000000000000000;
          rom[1] = 16'hE48F;
          rom[2] = 16'hE904;
          rom[3] = 16'hF206;
          rom[4] = 16'hFB30;
          rom[5] = 16'h0535;
          rom[6] = 16'h1156;
          rom[7] = 16'h1907;
          








                 
      end  
      assign instruction = (pc[15:0] < 48 )? rom[rom_addr[2:0]]: 16'd0;  
 endmodule