data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/dut_cosim.v
1: b'%Error: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/dut_cosim.v:29: Cannot find include file: hub.v\n `include "hub.v" \n          ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers,data/full_repos/permissive/452098851/hub.v\n             data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers,data/full_repos/permissive/452098851/hub.v.v\n             data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers,data/full_repos/permissive/452098851/hub.v.sv\n             hub.v\n             hub.v.v\n             hub.v.sv\n             obj_dir/hub.v\n             obj_dir/hub.v.v\n             obj_dir/hub.v.sv\n%Error: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/dut_cosim.v:65: syntax error, unexpected \'@\'\n         @( clk_initialized );\n         ^\n%Error: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/dut_cosim.v:89: syntax error, unexpected \'@\'\n         @( clk_started );\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/dut_cosim.v:93: Unsupported: Ignoring delay on this delayed statement.\n         #clk_firstHalf;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/dut_cosim.v:105: Unsupported: Ignoring delay on this delayed statement.\n         #clk_secondHalf;\n         ^\n%Error: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/dut_cosim.v:136: syntax error, unexpected \'@\'\n         @( rst_initialized );\n         ^\n%Error: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/dut_cosim.v:160: syntax error, unexpected \'@\'\n         @( rst_started );\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/dut_cosim.v:164: Unsupported: Ignoring delay on this delayed statement.\n         #rst_firstHalf;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/dut_cosim.v:176: Unsupported: Ignoring delay on this delayed statement.\n         #rst_secondHalf;\n         ^\n%Error: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/dut_cosim.v:207: syntax error, unexpected \'@\'\n         @( find_max_x_out_busy_initialized );\n         ^\n%Error: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/dut_cosim.v:231: syntax error, unexpected \'@\'\n         @( find_max_x_out_busy_started );\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/dut_cosim.v:235: Unsupported: Ignoring delay on this delayed statement.\n         #find_max_x_out_busy_firstHalf;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/dut_cosim.v:247: Unsupported: Ignoring delay on this delayed statement.\n         #find_max_x_out_busy_secondHalf;\n         ^\n%Error: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/dut_cosim.v:278: syntax error, unexpected \'@\'\n         @( find_max_return_in_vld_initialized );\n         ^\n%Error: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/dut_cosim.v:302: syntax error, unexpected \'@\'\n         @( find_max_return_in_vld_started );\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/dut_cosim.v:306: Unsupported: Ignoring delay on this delayed statement.\n         #find_max_return_in_vld_firstHalf;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/452098851/hierarchy/project/bdw_work/wrappers/dut_cosim.v:318: Unsupported: Ignoring delay on this delayed statement.\n         #find_max_return_in_vld_secondHalf;\n         ^\n%Error: Exiting due to 9 error(s), 8 warning(s)\n'
module dut_cosim;

	reg clk;
	reg rst;
	wire finish;
	reg find_max_x_out_busy;
	wire find_max_x_out_vld;
	wire[31:0] find_max_x_out_data;
	wire find_max_return_in_busy;
	reg find_max_return_in_vld;
	reg[31:0] find_max_return_in_data;


	`include "hub.v"

	dut dut0( .clk(clk),
	 .rst(rst),
	 .finish(finish),
	 .find_max_x_out_busy(find_max_x_out_busy),
	 .find_max_x_out_vld(find_max_x_out_vld),
	 .find_max_x_out_data(find_max_x_out_data),
	 .find_max_return_in_busy(find_max_return_in_busy),
	 .find_max_return_in_vld(find_max_return_in_vld),
	 .find_max_return_in_data(find_max_return_in_data) );



	reg clk_firstEdge;
	reg clk_initialized;
	reg clk_started;
	real clk_startTime;
	real clk_firstHalf;
	real clk_secondHalf;
	
	initial begin
	

	    hubSetOption("cycleOnly=1");
	

	    clk_firstEdge = 1'b1;
	    clk_startTime = 0.000;
	    clk_firstHalf = 5.000;
	    clk_secondHalf = 5.000;
	

	    hubScheduleDelayedAssignments;
	
	    while ( clk_initialized !== 1'b1 )
	        @( clk_initialized );
	
	    if ( clk_startTime > 0.0 ) begin
	        clk_started = #clk_startTime 1;
	    end
	    else begin
	        clk_started = 1;
	    end
	end
	

	always @( dut0.clk ) begin
	    if ( clk_started === 1'b1 ) begin
	        if ($time == top.cur_time) top.n_cur_time=top.n_cur_time-1;
	        else top.n_cur_time=0;
	        if (top.n_cur_time==0) begin
	            hubScheduleDelayedAssignments;
	        end
	    end
	end
	
	always begin

	    while ( clk_started !== 1'b1 )
	        @( clk_started );
	
	    clk <= clk_firstEdge;
	    if ( clk_firstHalf > 0.0 ) begin
	        #clk_firstHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	        clk = ~clk_firstEdge;
	    end
	    else begin
	        clk = ~clk_firstEdge;
	    end
	    if ( clk_secondHalf > 0.0 ) begin
	        #clk_secondHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	    end
	end

	reg rst_firstEdge;
	reg rst_initialized;
	reg rst_started;
	real rst_startTime;
	real rst_firstHalf;
	real rst_secondHalf;
	
	initial begin
	

	    hubSetOption("cycleOnly=1");
	

	    rst_firstEdge = 1'b1;
	    rst_startTime = 0.000;
	    rst_firstHalf = 5.000;
	    rst_secondHalf = 5.000;
	

	    hubScheduleDelayedAssignments;
	
	    while ( rst_initialized !== 1'b1 )
	        @( rst_initialized );
	
	    if ( rst_startTime > 0.0 ) begin
	        rst_started = #rst_startTime 1;
	    end
	    else begin
	        rst_started = 1;
	    end
	end
	

	always @( dut0.rst ) begin
	    if ( rst_started === 1'b1 ) begin
	        if ($time == top.cur_time) top.n_cur_time=top.n_cur_time-1;
	        else top.n_cur_time=0;
	        if (top.n_cur_time==0) begin
	            hubScheduleDelayedAssignments;
	        end
	    end
	end
	
	always begin

	    while ( rst_started !== 1'b1 )
	        @( rst_started );
	
	    rst <= rst_firstEdge;
	    if ( rst_firstHalf > 0.0 ) begin
	        #rst_firstHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	        rst = ~rst_firstEdge;
	    end
	    else begin
	        rst = ~rst_firstEdge;
	    end
	    if ( rst_secondHalf > 0.0 ) begin
	        #rst_secondHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	    end
	end

	reg find_max_x_out_busy_firstEdge;
	reg find_max_x_out_busy_initialized;
	reg find_max_x_out_busy_started;
	real find_max_x_out_busy_startTime;
	real find_max_x_out_busy_firstHalf;
	real find_max_x_out_busy_secondHalf;
	
	initial begin
	

	    hubSetOption("cycleOnly=1");
	

	    find_max_x_out_busy_firstEdge = 1'b1;
	    find_max_x_out_busy_startTime = 0.000;
	    find_max_x_out_busy_firstHalf = 5.000;
	    find_max_x_out_busy_secondHalf = 5.000;
	

	    hubScheduleDelayedAssignments;
	
	    while ( find_max_x_out_busy_initialized !== 1'b1 )
	        @( find_max_x_out_busy_initialized );
	
	    if ( find_max_x_out_busy_startTime > 0.0 ) begin
	        find_max_x_out_busy_started = #find_max_x_out_busy_startTime 1;
	    end
	    else begin
	        find_max_x_out_busy_started = 1;
	    end
	end
	

	always @( dut0.find_max_x_out_busy ) begin
	    if ( find_max_x_out_busy_started === 1'b1 ) begin
	        if ($time == top.cur_time) top.n_cur_time=top.n_cur_time-1;
	        else top.n_cur_time=0;
	        if (top.n_cur_time==0) begin
	            hubScheduleDelayedAssignments;
	        end
	    end
	end
	
	always begin

	    while ( find_max_x_out_busy_started !== 1'b1 )
	        @( find_max_x_out_busy_started );
	
	    find_max_x_out_busy <= find_max_x_out_busy_firstEdge;
	    if ( find_max_x_out_busy_firstHalf > 0.0 ) begin
	        #find_max_x_out_busy_firstHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	        find_max_x_out_busy = ~find_max_x_out_busy_firstEdge;
	    end
	    else begin
	        find_max_x_out_busy = ~find_max_x_out_busy_firstEdge;
	    end
	    if ( find_max_x_out_busy_secondHalf > 0.0 ) begin
	        #find_max_x_out_busy_secondHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	    end
	end

	reg find_max_return_in_vld_firstEdge;
	reg find_max_return_in_vld_initialized;
	reg find_max_return_in_vld_started;
	real find_max_return_in_vld_startTime;
	real find_max_return_in_vld_firstHalf;
	real find_max_return_in_vld_secondHalf;
	
	initial begin
	

	    hubSetOption("cycleOnly=1");
	

	    find_max_return_in_vld_firstEdge = 1'b1;
	    find_max_return_in_vld_startTime = 0.000;
	    find_max_return_in_vld_firstHalf = 5.000;
	    find_max_return_in_vld_secondHalf = 5.000;
	

	    hubScheduleDelayedAssignments;
	
	    while ( find_max_return_in_vld_initialized !== 1'b1 )
	        @( find_max_return_in_vld_initialized );
	
	    if ( find_max_return_in_vld_startTime > 0.0 ) begin
	        find_max_return_in_vld_started = #find_max_return_in_vld_startTime 1;
	    end
	    else begin
	        find_max_return_in_vld_started = 1;
	    end
	end
	

	always @( dut0.find_max_return_in_vld ) begin
	    if ( find_max_return_in_vld_started === 1'b1 ) begin
	        if ($time == top.cur_time) top.n_cur_time=top.n_cur_time-1;
	        else top.n_cur_time=0;
	        if (top.n_cur_time==0) begin
	            hubScheduleDelayedAssignments;
	        end
	    end
	end
	
	always begin

	    while ( find_max_return_in_vld_started !== 1'b1 )
	        @( find_max_return_in_vld_started );
	
	    find_max_return_in_vld <= find_max_return_in_vld_firstEdge;
	    if ( find_max_return_in_vld_firstHalf > 0.0 ) begin
	        #find_max_return_in_vld_firstHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	        find_max_return_in_vld = ~find_max_return_in_vld_firstEdge;
	    end
	    else begin
	        find_max_return_in_vld = ~find_max_return_in_vld_firstEdge;
	    end
	    if ( find_max_return_in_vld_secondHalf > 0.0 ) begin
	        #find_max_return_in_vld_secondHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	    end
	end


endmodule
module dut_cosim;


	reg clk;
	reg rst;
	wire finish;
	reg find_max_x_out_busy;
	wire find_max_x_out_vld;
	wire[31:0] find_max_x_out_data;
	wire find_max_return_in_busy;
	reg find_max_return_in_vld;
	reg[31:0] find_max_return_in_data;


	`include "hub.v"

	dut dut0( .clk(clk),
	 .rst(rst),
	 .finish(finish),
	 .find_max_x_out_busy(find_max_x_out_busy),
	 .find_max_x_out_vld(find_max_x_out_vld),
	 .find_max_x_out_data(find_max_x_out_data),
	 .find_max_return_in_busy(find_max_return_in_busy),
	 .find_max_return_in_vld(find_max_return_in_vld),
	 .find_max_return_in_data(find_max_return_in_data) );



	reg clk_firstEdge;
	reg clk_initialized;
	reg clk_started;
	real clk_startTime;
	real clk_firstHalf;
	real clk_secondHalf;
	
	initial begin
	

	    hubSetOption("cycleOnly=1");
	

	    clk_firstEdge = 1'b1;
	    clk_startTime = 0.000;
	    clk_firstHalf = 5.000;
	    clk_secondHalf = 5.000;
	

	    hubScheduleDelayedAssignments;
	
	    while ( clk_initialized !== 1'b1 )
	        @( clk_initialized );
	
	    if ( clk_startTime > 0.0 ) begin
	        clk_started = #clk_startTime 1;
	    end
	    else begin
	        clk_started = 1;
	    end
	end
	

	always @( dut0.clk ) begin
	    if ( clk_started === 1'b1 ) begin
	        if ($time == top.cur_time) top.n_cur_time=top.n_cur_time-1;
	        else top.n_cur_time=0;
	        if (top.n_cur_time==0) begin
	            hubScheduleDelayedAssignments;
	        end
	    end
	end
	
	always begin

	    while ( clk_started !== 1'b1 )
	        @( clk_started );
	
	    clk <= clk_firstEdge;
	    if ( clk_firstHalf > 0.0 ) begin
	        #clk_firstHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	        clk = ~clk_firstEdge;
	    end
	    else begin
	        clk = ~clk_firstEdge;
	    end
	    if ( clk_secondHalf > 0.0 ) begin
	        #clk_secondHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	    end
	end

	reg rst_firstEdge;
	reg rst_initialized;
	reg rst_started;
	real rst_startTime;
	real rst_firstHalf;
	real rst_secondHalf;
	
	initial begin
	

	    hubSetOption("cycleOnly=1");
	

	    rst_firstEdge = 1'b1;
	    rst_startTime = 0.000;
	    rst_firstHalf = 5.000;
	    rst_secondHalf = 5.000;
	

	    hubScheduleDelayedAssignments;
	
	    while ( rst_initialized !== 1'b1 )
	        @( rst_initialized );
	
	    if ( rst_startTime > 0.0 ) begin
	        rst_started = #rst_startTime 1;
	    end
	    else begin
	        rst_started = 1;
	    end
	end
	

	always @( dut0.rst ) begin
	    if ( rst_started === 1'b1 ) begin
	        if ($time == top.cur_time) top.n_cur_time=top.n_cur_time-1;
	        else top.n_cur_time=0;
	        if (top.n_cur_time==0) begin
	            hubScheduleDelayedAssignments;
	        end
	    end
	end
	
	always begin

	    while ( rst_started !== 1'b1 )
	        @( rst_started );
	
	    rst <= rst_firstEdge;
	    if ( rst_firstHalf > 0.0 ) begin
	        #rst_firstHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	        rst = ~rst_firstEdge;
	    end
	    else begin
	        rst = ~rst_firstEdge;
	    end
	    if ( rst_secondHalf > 0.0 ) begin
	        #rst_secondHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	    end
	end

	reg find_max_x_out_busy_firstEdge;
	reg find_max_x_out_busy_initialized;
	reg find_max_x_out_busy_started;
	real find_max_x_out_busy_startTime;
	real find_max_x_out_busy_firstHalf;
	real find_max_x_out_busy_secondHalf;
	
	initial begin
	

	    hubSetOption("cycleOnly=1");
	

	    find_max_x_out_busy_firstEdge = 1'b1;
	    find_max_x_out_busy_startTime = 0.000;
	    find_max_x_out_busy_firstHalf = 5.000;
	    find_max_x_out_busy_secondHalf = 5.000;
	

	    hubScheduleDelayedAssignments;
	
	    while ( find_max_x_out_busy_initialized !== 1'b1 )
	        @( find_max_x_out_busy_initialized );
	
	    if ( find_max_x_out_busy_startTime > 0.0 ) begin
	        find_max_x_out_busy_started = #find_max_x_out_busy_startTime 1;
	    end
	    else begin
	        find_max_x_out_busy_started = 1;
	    end
	end
	

	always @( dut0.find_max_x_out_busy ) begin
	    if ( find_max_x_out_busy_started === 1'b1 ) begin
	        if ($time == top.cur_time) top.n_cur_time=top.n_cur_time-1;
	        else top.n_cur_time=0;
	        if (top.n_cur_time==0) begin
	            hubScheduleDelayedAssignments;
	        end
	    end
	end
	
	always begin

	    while ( find_max_x_out_busy_started !== 1'b1 )
	        @( find_max_x_out_busy_started );
	
	    find_max_x_out_busy <= find_max_x_out_busy_firstEdge;
	    if ( find_max_x_out_busy_firstHalf > 0.0 ) begin
	        #find_max_x_out_busy_firstHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	        find_max_x_out_busy = ~find_max_x_out_busy_firstEdge;
	    end
	    else begin
	        find_max_x_out_busy = ~find_max_x_out_busy_firstEdge;
	    end
	    if ( find_max_x_out_busy_secondHalf > 0.0 ) begin
	        #find_max_x_out_busy_secondHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	    end
	end

	reg find_max_return_in_vld_firstEdge;
	reg find_max_return_in_vld_initialized;
	reg find_max_return_in_vld_started;
	real find_max_return_in_vld_startTime;
	real find_max_return_in_vld_firstHalf;
	real find_max_return_in_vld_secondHalf;
	
	initial begin
	

	    hubSetOption("cycleOnly=1");
	

	    find_max_return_in_vld_firstEdge = 1'b1;
	    find_max_return_in_vld_startTime = 0.000;
	    find_max_return_in_vld_firstHalf = 5.000;
	    find_max_return_in_vld_secondHalf = 5.000;
	

	    hubScheduleDelayedAssignments;
	
	    while ( find_max_return_in_vld_initialized !== 1'b1 )
	        @( find_max_return_in_vld_initialized );
	
	    if ( find_max_return_in_vld_startTime > 0.0 ) begin
	        find_max_return_in_vld_started = #find_max_return_in_vld_startTime 1;
	    end
	    else begin
	        find_max_return_in_vld_started = 1;
	    end
	end
	

	always @( dut0.find_max_return_in_vld ) begin
	    if ( find_max_return_in_vld_started === 1'b1 ) begin
	        if ($time == top.cur_time) top.n_cur_time=top.n_cur_time-1;
	        else top.n_cur_time=0;
	        if (top.n_cur_time==0) begin
	            hubScheduleDelayedAssignments;
	        end
	    end
	end
	
	always begin

	    while ( find_max_return_in_vld_started !== 1'b1 )
	        @( find_max_return_in_vld_started );
	
	    find_max_return_in_vld <= find_max_return_in_vld_firstEdge;
	    if ( find_max_return_in_vld_firstHalf > 0.0 ) begin
	        #find_max_return_in_vld_firstHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	        find_max_return_in_vld = ~find_max_return_in_vld_firstEdge;
	    end
	    else begin
	        find_max_return_in_vld = ~find_max_return_in_vld_firstEdge;
	    end
	    if ( find_max_return_in_vld_secondHalf > 0.0 ) begin
	        #find_max_return_in_vld_secondHalf;
	        if ($time==top.cur_time) begin
	            top.n_cur_time=top.n_cur_time+1;
	        end else begin
	            top.n_cur_time=1; top.cur_time=$time;
	        end
	    end
	end


endmodule