data/full_repos/permissive/445455582/single/RiSC16_registerFile.v
1: b'%Error: data/full_repos/permissive/445455582/single/RiSC16_registerFile.v:21: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/445455582/single,data/full_repos/permissive/445455582/defines.v\n             data/full_repos/permissive/445455582/single,data/full_repos/permissive/445455582/defines.v.v\n             data/full_repos/permissive/445455582/single,data/full_repos/permissive/445455582/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: Exiting due to 1 error(s)\n'
module RiSC16_registerFile #(
    parameter WORD_LENGTH = 16,
    parameter REG_ADDR_LEN = 3,
    parameter REG_NUM = 8
) (
    addr1, src1, addr2, src2, addrT, trgt,
    wen, clk, rst
);

    input [REG_ADDR_LEN - 1 : 0] addr1;
    input [REG_ADDR_LEN - 1 : 0] addr2;
    input [REG_ADDR_LEN - 1 : 0] addrT;
    input [WORD_LENGTH - 1 : 0] trgt;

    input wen;
    input clk;
    input rst;

    output [WORD_LENGTH - 1 : 0] src1;
    output [WORD_LENGTH - 1 : 0] src2;

    reg [WORD_LENGTH - 1 : 0] dataRegister [0 : REG_NUM - 1];

    assign src1 = dataRegister[addr1];
    assign src2 = dataRegister[addr2];

    integer i;

    always @(negedge clk) begin
        if(wen) begin
            if(addrT != 3'b000)
                dataRegister[addrT] <= trgt;
        end else if(rst)
            for ( i = 0; i < REG_NUM; i = i + 1) begin
                dataRegister[i] <= 0;
            end
    end

    
endmodule
module RiSC16_registerFile #(
    parameter WORD_LENGTH = 16,
    parameter REG_ADDR_LEN = 3,
    parameter REG_NUM = 8
) (
    addr1, src1, addr2, src2, addrT, trgt,
    wen, clk, rst
);


    input [REG_ADDR_LEN - 1 : 0] addr1;
    input [REG_ADDR_LEN - 1 : 0] addr2;
    input [REG_ADDR_LEN - 1 : 0] addrT;
    input [WORD_LENGTH - 1 : 0] trgt;

    input wen;
    input clk;
    input rst;

    output [WORD_LENGTH - 1 : 0] src1;
    output [WORD_LENGTH - 1 : 0] src2;

    reg [WORD_LENGTH - 1 : 0] dataRegister [0 : REG_NUM - 1];

    assign src1 = dataRegister[addr1];
    assign src2 = dataRegister[addr2];

    integer i;

    always @(negedge clk) begin
        if(wen) begin
            if(addrT != 3'b000)
                dataRegister[addrT] <= trgt;
        end else if(rst)
            for ( i = 0; i < REG_NUM; i = i + 1) begin
                dataRegister[i] <= 0;
            end
    end

    
endmodule