data/full_repos/permissive/468612001/Week03/mux8b_4to1/tb_mux8b_4to1.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/468612001/Week03/mux8b_4to1/tb_mux8b_4to1.v:11: Unsupported: Ignoring delay on this delayed statement.\n  #20 a = 4\'b0010; b = 4\'b0011; c = 4\'b0101; d = 4\'b1110;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week03/mux8b_4to1/tb_mux8b_4to1.v:12: Unsupported: Ignoring delay on this delayed statement.\n  #20 a = 4\'b1101; b = 4\'b1000; c = 4\'b1110; d = 4\'b1001;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week03/mux8b_4to1/tb_mux8b_4to1.v:13: Unsupported: Ignoring delay on this delayed statement.\n  #20 a = 4\'b1111; b = 4\'b1010; c = 4\'b0110; d = 4\'b1111;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week03/mux8b_4to1/tb_mux8b_4to1.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #20 a = 4\'b0011; b = 4\'b1110; c = 4\'b0101; d = 4\'b1010;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week03/mux8b_4to1/tb_mux8b_4to1.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #20 a = 4\'b1001; b = 4\'b0011; c = 4\'b1100; d = 4\'b1110;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week03/mux8b_4to1/tb_mux8b_4to1.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #20 a = 4\'b1011; b = 4\'b0111; c = 4\'b0101; d = 4\'b1001;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week03/mux8b_4to1/tb_mux8b_4to1.v:21: Unsupported: Ignoring delay on this delayed statement.\n #20 sel = 2\'b01;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week03/mux8b_4to1/tb_mux8b_4to1.v:22: Unsupported: Ignoring delay on this delayed statement.\n #30 sel = 2\'b10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week03/mux8b_4to1/tb_mux8b_4to1.v:23: Unsupported: Ignoring delay on this delayed statement.\n #40 sel = 2\'b11;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week03/mux8b_4to1/tb_mux8b_4to1.v:28: Unsupported: Ignoring delay on this delayed statement.\n #10 enable = 1\'b0;\n ^\n%Error: data/full_repos/permissive/468612001/Week03/mux8b_4to1/tb_mux8b_4to1.v:7: Cannot find file containing module: \'mux8b_4to1\'\n mux8b_4to1 U0 (a, b, c, d, sel, enable, out);\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/468612001/Week03/mux8b_4to1,data/full_repos/permissive/468612001/mux8b_4to1\n             data/full_repos/permissive/468612001/Week03/mux8b_4to1,data/full_repos/permissive/468612001/mux8b_4to1.v\n             data/full_repos/permissive/468612001/Week03/mux8b_4to1,data/full_repos/permissive/468612001/mux8b_4to1.sv\n             mux8b_4to1\n             mux8b_4to1.v\n             mux8b_4to1.sv\n             obj_dir/mux8b_4to1\n             obj_dir/mux8b_4to1.v\n             obj_dir/mux8b_4to1.sv\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_mux8b_4to1();
	reg [3:0] a, b, c, d;
	reg [1:0] sel;
	reg enable;
	wire [3:0] out;
	
	mux8b_4to1 U0 (a, b, c, d, sel, enable, out);
	
	initial begin
				a = 4'b0001; b = 4'b0010; c = 4'b0100; d = 4'b1000;
		#20	a = 4'b0010; b = 4'b0011; c = 4'b0101; d = 4'b1110;
		#20	a = 4'b1101; b = 4'b1000; c = 4'b1110; d = 4'b1001;
		#20	a = 4'b1111; b = 4'b1010; c = 4'b0110; d = 4'b1111;
		#20	a = 4'b0011; b = 4'b1110; c = 4'b0101; d = 4'b1010;
		#20	a = 4'b1001; b = 4'b0011; c = 4'b1100; d = 4'b1110;
		#20	a = 4'b1011; b = 4'b0111; c = 4'b0101; d = 4'b1001;
	end
	
	initial begin
			sel = 2'b00;
	#20	sel = 2'b01;
	#30	sel = 2'b10;
	#40	sel = 2'b11;
	end
	
	initial begin
			enable = 1'b1;
	#10	enable = 1'b0;
	end
endmodule
module tb_mux8b_4to1();

	reg [3:0] a, b, c, d;
	reg [1:0] sel;
	reg enable;
	wire [3:0] out;
	
	mux8b_4to1 U0 (a, b, c, d, sel, enable, out);
	
	initial begin
				a = 4'b0001; b = 4'b0010; c = 4'b0100; d = 4'b1000;
		#20	a = 4'b0010; b = 4'b0011; c = 4'b0101; d = 4'b1110;
		#20	a = 4'b1101; b = 4'b1000; c = 4'b1110; d = 4'b1001;
		#20	a = 4'b1111; b = 4'b1010; c = 4'b0110; d = 4'b1111;
		#20	a = 4'b0011; b = 4'b1110; c = 4'b0101; d = 4'b1010;
		#20	a = 4'b1001; b = 4'b0011; c = 4'b1100; d = 4'b1110;
		#20	a = 4'b1011; b = 4'b0111; c = 4'b0101; d = 4'b1001;
	end
	
	initial begin
			sel = 2'b00;
	#20	sel = 2'b01;
	#30	sel = 2'b10;
	#40	sel = 2'b11;
	end
	
	initial begin
			enable = 1'b1;
	#10	enable = 1'b0;
	end
endmodule