data/full_repos/permissive/481044442/BDCDrv/single_pulse.v
data/verilator_xmls/540c8af2-9c33-4ef6-9f40-cb4ebd55ae83.xml
module single_pulse(clk,reset,pulse_out);
input clk;
input reset;
output reg pulse_out;




reg[15:0] counter;
always@(posedge clk or posedge reset)
begin
	if(reset) begin
				counter<=16'd0;
				pulse_out<=1'b0;
				end
	else begin
			if(counter==16'd4800) begin
										pulse_out<=1'b1;
										counter<=16'd0;
									end
			else begin
					counter<=counter+1'b1;	
					pulse_out<=1'b0;
					end
			end
end
endmodule
module single_pulse(clk,reset,pulse_out);

input clk;
input reset;
output reg pulse_out;




reg[15:0] counter;
always@(posedge clk or posedge reset)
begin
	if(reset) begin
				counter<=16'd0;
				pulse_out<=1'b0;
				end
	else begin
			if(counter==16'd4800) begin
										pulse_out<=1'b1;
										counter<=16'd0;
									end
			else begin
					counter<=counter+1'b1;	
					pulse_out<=1'b0;
					end
			end
end
endmodule