data/full_repos/permissive/492462267/regfile.v
1: b'%Error: data/full_repos/permissive/492462267/regfile.v:1: Cannot find include file: define.vh\n`include "define.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh.v\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh.sv\n             define.vh\n             define.vh.v\n             define.vh.sv\n             obj_dir/define.vh\n             obj_dir/define.vh.v\n             obj_dir/define.vh.sv\n%Error: data/full_repos/permissive/492462267/regfile.v:19: Define or directive not defined: \'`RegAddrBus\'\n    input   wire[`RegAddrBus]    waddr,      \n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/regfile.v:19: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input   wire[`RegAddrBus]    waddr,      \n                            ^\n%Error: data/full_repos/permissive/492462267/regfile.v:20: Define or directive not defined: \'`RegDataBus\'\n    input   wire[`RegDataBus]    wdata,      \n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/regfile.v:24: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire[`RegAddrBus]    raddr_1,    \n    ^~~~~\n%Error: data/full_repos/permissive/492462267/regfile.v:24: Define or directive not defined: \'`RegAddrBus\'\n    input   wire[`RegAddrBus]    raddr_1,    \n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/regfile.v:25: Define or directive not defined: \'`RegDataBus\'\n    output  reg[`RegDataBus]     rdata_1,    \n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/regfile.v:29: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire[`RegAddrBus]    raddr_2,\n    ^~~~~\n%Error: data/full_repos/permissive/492462267/regfile.v:29: Define or directive not defined: \'`RegAddrBus\'\n    input   wire[`RegAddrBus]    raddr_2,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/regfile.v:30: Define or directive not defined: \'`RegDataBus\'\n    output  reg[`RegDataBus]     rdata_2\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/regfile.v:34: Define or directive not defined: \'`RegDataBus\'\nreg [`RegDataBus] regs[0 : `RegNum-1];\n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/regfile.v:34: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg [`RegDataBus] regs[0 : `RegNum-1];\n                ^\n%Error: data/full_repos/permissive/492462267/regfile.v:34: Define or directive not defined: \'`RegNum\'\nreg [`RegDataBus] regs[0 : `RegNum-1];\n                           ^~~~~~~\n%Error: data/full_repos/permissive/492462267/regfile.v:43: Define or directive not defined: \'`RegAddr_0\'\n         if ( we && waddr != `RegAddr_0) begin\n                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/regfile.v:59: Define or directive not defined: \'`ZeroWord\'\n         rdata_1 <= `ZeroWord;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/regfile.v:60: Define or directive not defined: \'`RegAddr_0\'\n     end else if(raddr_1 == `RegAddr_0) begin\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/regfile.v:61: Define or directive not defined: \'`ZeroWord\'\n         rdata_1 <= `ZeroWord;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/regfile.v:67: Define or directive not defined: \'`ZeroWord\'\n         rdata_1 <= `ZeroWord;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/regfile.v:77: Define or directive not defined: \'`ZeroWord\'\n         rdata_2 <= `ZeroWord;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/regfile.v:78: Define or directive not defined: \'`RegAddr_0\'\n     end else if(raddr_2 == `RegAddr_0) begin\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/regfile.v:79: Define or directive not defined: \'`ZeroWord\'\n         rdata_2 <= `ZeroWord;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/regfile.v:85: Define or directive not defined: \'`ZeroWord\'\n         rdata_2 <= `ZeroWord;\n                    ^~~~~~~~~\n%Error: Exiting due to 22 error(s)\n'
module regfile (
    input   wire    clk,
    input   wire    rst,


    input   wire    we,
    input   wire[`RegAddrBus]    waddr,
    input   wire[`RegDataBus]    wdata,


    input   wire    re1,
    input   wire[`RegAddrBus]    raddr_1,
    output  reg[`RegDataBus]     rdata_1,


    input   wire    re2,
    input   wire[`RegAddrBus]    raddr_2,
    output  reg[`RegDataBus]     rdata_2
);


reg [`RegDataBus] regs[0 : `RegNum-1];



 always @(posedge clk) begin
     if(~rst) begin
         if ( we && waddr != `RegAddr_0) begin
             regs[waddr] <= wdata;
         end
     end
 end




 always @(*) begin
     if(rst) begin
         rdata_1 <= `ZeroWord;
     end else if(raddr_1 == `RegAddr_0) begin
         rdata_1 <= `ZeroWord;
     end else if(raddr_1 == waddr && we && re1) begin
         rdata_1 <= wdata;
     end else if(re1) begin
         rdata_1 <= regs[raddr_1];
     end else begin
         rdata_1 <= `ZeroWord;
     end
 end



 always @(*) begin
     if(rst) begin
         rdata_2 <= `ZeroWord;
     end else if(raddr_2 == `RegAddr_0) begin
         rdata_2 <= `ZeroWord;
     end else if(raddr_2 == waddr && we && re2) begin
         rdata_2 <= wdata;
     end else if(re2) begin
         rdata_2 <= regs[raddr_2];
     end else begin
         rdata_2 <= `ZeroWord;
     end
 end


endmodule
module regfile (
    input   wire    clk,
    input   wire    rst,


    input   wire    we,
    input   wire[`RegAddrBus]    waddr,
    input   wire[`RegDataBus]    wdata,


    input   wire    re1,
    input   wire[`RegAddrBus]    raddr_1,
    output  reg[`RegDataBus]     rdata_1,


    input   wire    re2,
    input   wire[`RegAddrBus]    raddr_2,
    output  reg[`RegDataBus]     rdata_2
);



reg [`RegDataBus] regs[0 : `RegNum-1];



 always @(posedge clk) begin
     if(~rst) begin
         if ( we && waddr != `RegAddr_0) begin
             regs[waddr] <= wdata;
         end
     end
 end




 always @(*) begin
     if(rst) begin
         rdata_1 <= `ZeroWord;
     end else if(raddr_1 == `RegAddr_0) begin
         rdata_1 <= `ZeroWord;
     end else if(raddr_1 == waddr && we && re1) begin
         rdata_1 <= wdata;
     end else if(re1) begin
         rdata_1 <= regs[raddr_1];
     end else begin
         rdata_1 <= `ZeroWord;
     end
 end



 always @(*) begin
     if(rst) begin
         rdata_2 <= `ZeroWord;
     end else if(raddr_2 == `RegAddr_0) begin
         rdata_2 <= `ZeroWord;
     end else if(raddr_2 == waddr && we && re2) begin
         rdata_2 <= wdata;
     end else if(re2) begin
         rdata_2 <= regs[raddr_2];
     end else begin
         rdata_2 <= `ZeroWord;
     end
 end


endmodule