data/full_repos/permissive/458737381/src/verilog-parser/tests/buf_gate.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/buf_gate.v:8: Unsupported or unknown PLI call: $monitor\n  $monitor ("Time = %g in = %b out=%b", $time, in, out);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/buf_gate.v:10: Unsupported: Ignoring delay on this delayed statement.\n  #10 in = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/buf_gate.v:11: Unsupported: Ignoring delay on this delayed statement.\n  #10 in = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/buf_gate.v:12: Unsupported: Ignoring delay on this delayed statement.\n  #10 $finish;\n  ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module  buf_gate ();
reg in;
wire out;
	 
buf #(5) (out,in);

initial begin
  $monitor ("Time = %g in = %b out=%b", $time, in, out);
  in = 0;
  #10 in = 1;
  #10 in = 0;
  #10 $finish;
end
  	 
endmodule
module  buf_gate ();

reg in;
wire out;
	 
buf #(5) (out,in);

initial begin
  $monitor ("Time = %g in = %b out=%b", $time, in, out);
  in = 0;
  #10 in = 1;
  #10 in = 0;
  #10 $finish;
end
  	 
endmodule