data/full_repos/permissive/450922687/Task 2/Data_Memory.v
1: b'%Error: Cannot find file containing module: 2,data/full_repos/permissive/450922687\n        ... Looked in:\n             data/full_repos/permissive/450922687/Task/2,data/full_repos/permissive/450922687\n             data/full_repos/permissive/450922687/Task/2,data/full_repos/permissive/450922687.v\n             data/full_repos/permissive/450922687/Task/2,data/full_repos/permissive/450922687.sv\n             2,data/full_repos/permissive/450922687\n             2,data/full_repos/permissive/450922687.v\n             2,data/full_repos/permissive/450922687.sv\n             obj_dir/2,data/full_repos/permissive/450922687\n             obj_dir/2,data/full_repos/permissive/450922687.v\n             obj_dir/2,data/full_repos/permissive/450922687.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/450922687/Task\n%Error: Cannot find file containing module: 2/Data_Memory.v\n%Error: Exiting due to 3 error(s)\n'
module Data_Memory(
  input clk, 
  input MemWrite, MemRead,
  input [63:0] MemAdd,WriteData,
  output reg [63:0] ReadData1);
  reg [7:0] memory [63:0];
  integer i;
  integer j;
  initial 
    begin
      for (i=0; i<64; i=i+1)
        begin j = $urandom%100;
          memory[i] = j; 
          $display("data = ", j,"mem = ",i);
       end 
    end 
  always @(*)
    begin 
      if (MemRead)
        begin 
          ReadData1[7:0] = memory[MemAdd+0];
          ReadData1[15:8] = memory[MemAdd+1];
          ReadData1[23:16] = memory[MemAdd+2];
          ReadData1[31:24] = memory[MemAdd+3];
          ReadData1[39:32] = memory[MemAdd+4];
          ReadData1[47:40] = memory[MemAdd+5];
          ReadData1[55:48] = memory[MemAdd+6];
          ReadData1[63:56] = memory[MemAdd+7];
        end
    end
  always @(posedge clk)
    begin 
      if (MemWrite)
        begin
          memory[MemAdd] = WriteData[7:0];
          memory[MemAdd+1] = WriteData[15:8];
          memory[MemAdd+2] = WriteData[23:16];
          memory[MemAdd+3] = WriteData[31:24];
          memory[MemAdd+4] = WriteData[39:32];
          memory[MemAdd+5] = WriteData[47:40];
          memory[MemAdd+6] = WriteData[55:48];
          memory[MemAdd+7] = WriteData[63:56];
        end
    end
endmodule
module Data_Memory(
  input clk, 
  input MemWrite, MemRead,
  input [63:0] MemAdd,WriteData,
  output reg [63:0] ReadData1);

  reg [7:0] memory [63:0];
  integer i;
  integer j;
  initial 
    begin
      for (i=0; i<64; i=i+1)
        begin j = $urandom%100;
          memory[i] = j; 
          $display("data = ", j,"mem = ",i);
       end 
    end 
  always @(*)
    begin 
      if (MemRead)
        begin 
          ReadData1[7:0] = memory[MemAdd+0];
          ReadData1[15:8] = memory[MemAdd+1];
          ReadData1[23:16] = memory[MemAdd+2];
          ReadData1[31:24] = memory[MemAdd+3];
          ReadData1[39:32] = memory[MemAdd+4];
          ReadData1[47:40] = memory[MemAdd+5];
          ReadData1[55:48] = memory[MemAdd+6];
          ReadData1[63:56] = memory[MemAdd+7];
        end
    end
  always @(posedge clk)
    begin 
      if (MemWrite)
        begin
          memory[MemAdd] = WriteData[7:0];
          memory[MemAdd+1] = WriteData[15:8];
          memory[MemAdd+2] = WriteData[23:16];
          memory[MemAdd+3] = WriteData[31:24];
          memory[MemAdd+4] = WriteData[39:32];
          memory[MemAdd+5] = WriteData[47:40];
          memory[MemAdd+6] = WriteData[55:48];
          memory[MemAdd+7] = WriteData[63:56];
        end
    end
endmodule