data/full_repos/permissive/460328193/ipa_proj_pipe/pc_update.v
1: b"%Error: data/full_repos/permissive/460328193/ipa_proj_pipe/pc_update.v:4: Input/output/inout does not appear in port list: 'Cnd'\ninput Cnd;\n      ^~~\n%Error: Exiting due to 1 error(s)\n"
module pc_update(predPC,icode,valC,valP,clock);
input clock;
input [3:0]icode;
input Cnd;
input [63:0]valC;
input [63:0]valP;
output reg [63:0]predPC;

reg [63:0]new_pc;
always @(*)
begin
	if(icode==4'h7)
        new_pc<=valC;
	else if(icode==4'h8)
        new_pc<=valC;
	else
        new_pc<=valP;
    predPC<=new_pc;
end

endmodule
module pc_update(predPC,icode,valC,valP,clock);

input clock;
input [3:0]icode;
input Cnd;
input [63:0]valC;
input [63:0]valP;
output reg [63:0]predPC;

reg [63:0]new_pc;
always @(*)
begin
	if(icode==4'h7)
        new_pc<=valC;
	else if(icode==4'h8)
        new_pc<=valC;
	else
        new_pc<=valP;
    predPC<=new_pc;
end

endmodule