data/full_repos/permissive/475231219/BabyRuner/wire_decl0.v
data/verilator_xmls/c76d3d89-c8e9-4ee9-83df-c1febe38071c.xml
module top_modul(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   ); 
    assign out = (a&b) | (c&d);
    assign out_n = ~out;
endmodule
module top_modul(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   );
 
    assign out = (a&b) | (c&d);
    assign out_n = ~out;
endmodule