data/full_repos/permissive/500326609/a1/seq_mult.v
1: b'%Warning-WIDTH: data/full_repos/permissive/500326609/a1/seq_mult.v:53: Bit extraction of var[15:0] requires 4 bit index, not 5 bits.\n                                                                     : ... In instance seq_mult\n   p = p + (( multiplier[ctr] * multiplicand ) << ctr);\n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module seq_mult (

		 p, rdy,

		 clk, reset, a, b
		 ) ;
   input 		 clk, reset;
   input [`width-1:0] 	 a, b;

	 output [2*`width-1:0] p;
	 output 		 rdy;


	 reg [2*`width-1:0] p;
	 reg 			 rdy;
	 reg [2*`width-1:0] 	 multiplier, multiplicand,temp;
   reg [`ctrwidth:0] 	 ctr;

   always @(posedge clk or posedge reset)
     if (reset) begin
	rdy 		<= 0;
	p 		<= 0;
	ctr 		<= 0;
	multiplier 	<= {{`width{a[`width-1]}}, a};
	multiplicand 	<= {{`width{b[`width-1]}}, b};
     end else begin
	if (ctr < 2*`width )
	  begin
			p = p + (( multiplier[ctr] * multiplicand ) << ctr);
			ctr++;


	  end else begin
	     rdy <= 1;
	  end
     end

endmodule
module seq_mult (

		 p, rdy,

		 clk, reset, a, b
		 ) ;

   input 		 clk, reset;
   input [`width-1:0] 	 a, b;

	 output [2*`width-1:0] p;
	 output 		 rdy;


	 reg [2*`width-1:0] p;
	 reg 			 rdy;
	 reg [2*`width-1:0] 	 multiplier, multiplicand,temp;
   reg [`ctrwidth:0] 	 ctr;

   always @(posedge clk or posedge reset)
     if (reset) begin
	rdy 		<= 0;
	p 		<= 0;
	ctr 		<= 0;
	multiplier 	<= {{`width{a[`width-1]}}, a};
	multiplicand 	<= {{`width{b[`width-1]}}, b};
     end else begin
	if (ctr < 2*`width )
	  begin
			p = p + (( multiplier[ctr] * multiplicand ) << ctr);
			ctr++;


	  end else begin
	     rdy <= 1;
	  end
     end

endmodule