data/full_repos/permissive/432564927/Lab1 (Verilog)/decoder3to8Test.v
1: b'%Error: Cannot find file containing module: (Verilog),data/full_repos/permissive/432564927\n        ... Looked in:\n             data/full_repos/permissive/432564927/Lab1/(Verilog),data/full_repos/permissive/432564927\n             data/full_repos/permissive/432564927/Lab1/(Verilog),data/full_repos/permissive/432564927.v\n             data/full_repos/permissive/432564927/Lab1/(Verilog),data/full_repos/permissive/432564927.sv\n             (Verilog),data/full_repos/permissive/432564927\n             (Verilog),data/full_repos/permissive/432564927.v\n             (Verilog),data/full_repos/permissive/432564927.sv\n             obj_dir/(Verilog),data/full_repos/permissive/432564927\n             obj_dir/(Verilog),data/full_repos/permissive/432564927.v\n             obj_dir/(Verilog),data/full_repos/permissive/432564927.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/432564927/Lab1\n%Error: Cannot find file containing module: (Verilog)/decoder3to8Test.v\n%Error: Exiting due to 3 error(s)\n'
module decoder3to8Test;

    reg in0;
    reg in1;
    reg in2;

    wire out0;
    wire out1;
    wire out2;
    wire out3;
    wire out4;
    wire out5;
    wire out6;
    wire out7;
    
    decoder3to8 uut(
        .in0 (in0),
        .in1 (in1),
        .in2 (in2),
        
        .out0(out0),
        .out1(out1),
        .out2(out2),
        .out3(out3),
        .out4(out4),
        .out5(out5),
        .out6(out6),
        .out7(out7)
    );
    initial begin

        in0 = 0;
        in1 = 0;
        in2 = 0;

        #100;
        in0 = 1;
        in1 = 0;
        in2 = 1;

        #100;
    end    
endmodule
module decoder3to8Test;


    reg in0;
    reg in1;
    reg in2;

    wire out0;
    wire out1;
    wire out2;
    wire out3;
    wire out4;
    wire out5;
    wire out6;
    wire out7;
    
    decoder3to8 uut(
        .in0 (in0),
        .in1 (in1),
        .in2 (in2),
        
        .out0(out0),
        .out1(out1),
        .out2(out2),
        .out3(out3),
        .out4(out4),
        .out5(out5),
        .out6(out6),
        .out7(out7)
    );
    initial begin

        in0 = 0;
        in1 = 0;
        in2 = 0;

        #100;
        in0 = 1;
        in1 = 0;
        in2 = 1;

        #100;
    end    
endmodule