data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/rx_chain_dual.v
1: b"%Error: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/rx_chain_dual.v:53: Cannot find file containing module: 'phase_acc'\n   phase_acc rx_phase_acc_0\n   ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib,data/full_repos/permissive/447976230/phase_acc\n             data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib,data/full_repos/permissive/447976230/phase_acc.v\n             data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib,data/full_repos/permissive/447976230/phase_acc.sv\n             phase_acc\n             phase_acc.v\n             phase_acc.sv\n             obj_dir/phase_acc\n             obj_dir/phase_acc.v\n             obj_dir/phase_acc.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/rx_chain_dual.v:57: Cannot find file containing module: 'phase_acc'\n   phase_acc rx_phase_acc_1\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/rx_chain_dual.v:78: Cannot find file containing module: 'cordic'\n   cordic rx_cordic\n   ^~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/rx_chain_dual.v:83: Cannot find file containing module: 'cic_decim'\n   cic_decim cic_decim_i_0\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/rx_chain_dual.v:88: Cannot find file containing module: 'cic_decim'\n   cic_decim cic_decim_q_0\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/rx_chain_dual.v:93: Cannot find file containing module: 'cic_decim'\n   cic_decim cic_decim_i_1\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/rx_chain_dual.v:98: Cannot find file containing module: 'cic_decim'\n   cic_decim cic_decim_q_1\n   ^~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module rx_chain_dual
  (input clock,
   input clock_2x,
   input reset,
   input enable,
   input wire [7:0] decim_rate,
   input sample_strobe,
   input decimator_strobe,
   input wire [31:0] freq0,
   input wire [15:0] i_in0,
   input wire [15:0] q_in0,
   output wire [15:0] i_out0,
   output wire [15:0] q_out0,
   input wire [31:0] freq1,
   input wire [15:0] i_in1,
   input wire [15:0] q_in1,
   output wire [15:0] i_out1,
   output wire [15:0] q_out1
   );

   wire [15:0] phase;
   wire [15:0] bb_i, bb_q;
   wire [15:0] i_in, q_in;
   
   wire [31:0] phase0;
   wire [31:0] phase1;
   reg [15:0] bb_i0, bb_q0;
   reg [15:0] bb_i1, bb_q1;


   
   phase_acc rx_phase_acc_0
     (.clk(clock),.reset(reset),.enable(enable),
      .strobe(sample_strobe),.freq(freq0),.phase(phase0) );

   phase_acc rx_phase_acc_1
     (.clk(clock),.reset(reset),.enable(enable),
      .strobe(sample_strobe),.freq(freq1),.phase(phase1) );
   
   assign phase = clock ? phase0[31:16] : phase1[31:16];
   assign i_in = clock ? i_in0 : i_in1;
   assign q_in = clock ? q_in0 : q_in1;


   always @(posedge clock_2x)
     if(clock)
       begin
	  bb_i1 <= #1 bb_i;
	  bb_q1 <= #1 bb_q;
       end
     else
       begin
	  bb_i0 <= #1 bb_i;
	  bb_q0 <= #1 bb_q;
       end
	
   cordic rx_cordic
     ( .clock(clock_2x),.reset(reset),.enable(enable), 
       .xi(i_in),.yi(q_in),.zi(phase),
       .xo(bb_i),.yo(bb_q),.zo() );
   
   cic_decim cic_decim_i_0
     ( .clock(clock),.reset(reset),.enable(enable),
       .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
       .signal_in(bb_i0),.signal_out(i_out0) );

   cic_decim cic_decim_q_0
     ( .clock(clock),.reset(reset),.enable(enable),
       .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
       .signal_in(bb_q0),.signal_out(q_out0) );

   cic_decim cic_decim_i_1
     ( .clock(clock),.reset(reset),.enable(enable),
       .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
       .signal_in(bb_i1),.signal_out(i_out1) );

   cic_decim cic_decim_q_1
     ( .clock(clock),.reset(reset),.enable(enable),
       .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
       .signal_in(bb_q1),.signal_out(q_out1) );

endmodule
module rx_chain_dual
  (input clock,
   input clock_2x,
   input reset,
   input enable,
   input wire [7:0] decim_rate,
   input sample_strobe,
   input decimator_strobe,
   input wire [31:0] freq0,
   input wire [15:0] i_in0,
   input wire [15:0] q_in0,
   output wire [15:0] i_out0,
   output wire [15:0] q_out0,
   input wire [31:0] freq1,
   input wire [15:0] i_in1,
   input wire [15:0] q_in1,
   output wire [15:0] i_out1,
   output wire [15:0] q_out1
   );


   wire [15:0] phase;
   wire [15:0] bb_i, bb_q;
   wire [15:0] i_in, q_in;
   
   wire [31:0] phase0;
   wire [31:0] phase1;
   reg [15:0] bb_i0, bb_q0;
   reg [15:0] bb_i1, bb_q1;


   
   phase_acc rx_phase_acc_0
     (.clk(clock),.reset(reset),.enable(enable),
      .strobe(sample_strobe),.freq(freq0),.phase(phase0) );

   phase_acc rx_phase_acc_1
     (.clk(clock),.reset(reset),.enable(enable),
      .strobe(sample_strobe),.freq(freq1),.phase(phase1) );
   
   assign phase = clock ? phase0[31:16] : phase1[31:16];
   assign i_in = clock ? i_in0 : i_in1;
   assign q_in = clock ? q_in0 : q_in1;


   always @(posedge clock_2x)
     if(clock)
       begin
	  bb_i1 <= #1 bb_i;
	  bb_q1 <= #1 bb_q;
       end
     else
       begin
	  bb_i0 <= #1 bb_i;
	  bb_q0 <= #1 bb_q;
       end
	
   cordic rx_cordic
     ( .clock(clock_2x),.reset(reset),.enable(enable), 
       .xi(i_in),.yi(q_in),.zi(phase),
       .xo(bb_i),.yo(bb_q),.zo() );
   
   cic_decim cic_decim_i_0
     ( .clock(clock),.reset(reset),.enable(enable),
       .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
       .signal_in(bb_i0),.signal_out(i_out0) );

   cic_decim cic_decim_q_0
     ( .clock(clock),.reset(reset),.enable(enable),
       .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
       .signal_in(bb_q0),.signal_out(q_out0) );

   cic_decim cic_decim_i_1
     ( .clock(clock),.reset(reset),.enable(enable),
       .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
       .signal_in(bb_i1),.signal_out(i_out1) );

   cic_decim cic_decim_q_1
     ( .clock(clock),.reset(reset),.enable(enable),
       .rate(decim_rate),.strobe_in(sample_strobe),.strobe_out(decimator_strobe),
       .signal_in(bb_q1),.signal_out(q_out1) );

endmodule