data/full_repos/permissive/423547971/10 Verilog Projects Book/Section_1/seq_det_101c.v
1: b'%Error: Cannot find file containing module: Verilog\n        ... Looked in:\n             data/full_repos/permissive/423547971/10/Verilog\n             data/full_repos/permissive/423547971/10/Verilog.v\n             data/full_repos/permissive/423547971/10/Verilog.sv\n             Verilog\n             Verilog.v\n             Verilog.sv\n             obj_dir/Verilog\n             obj_dir/Verilog.v\n             obj_dir/Verilog.sv\n%Error: Cannot find file containing module: Projects\n%Error: Cannot find file containing module: Book/Section_1,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/10\n%Error: Cannot find file containing module: Book/Section_1/seq_det_101c.v\n%Error: Exiting due to 5 error(s)\n'
module seq_det_101c(
	input clock,
	input reset,
	input serial_in,
	output detect_101
);

	parameter S0 = 2'b00;
	parameter S1 = 2'b01;
	parameter S2 = 2'b10;
	parameter S3 = 2'b11;
	
	reg [1:0] current_state, next_state;

	always @(posedge clock or negedge reset)
		if(~reset)
			current_state <= S0;
		else
			current_state <= next_state;
			
	always @(*)
		case(current_state)
			S0 : next_state = (serial_in == 1) ? S1 : S0;
			S1 : next_state = (serial_in == 0) ? S2 : S1;
			S2 : next_state = (serial_in == 1) ? S3 : S0;
			S3 : next_state = (serial_in == 1) ? S1 : S2;
		endcase

	assign detect_101 = (current_state == S3) ? 1 : 0;

endmodule
module seq_det_101c(
	input clock,
	input reset,
	input serial_in,
	output detect_101
);


	parameter S0 = 2'b00;
	parameter S1 = 2'b01;
	parameter S2 = 2'b10;
	parameter S3 = 2'b11;
	
	reg [1:0] current_state, next_state;

	always @(posedge clock or negedge reset)
		if(~reset)
			current_state <= S0;
		else
			current_state <= next_state;
			
	always @(*)
		case(current_state)
			S0 : next_state = (serial_in == 1) ? S1 : S0;
			S1 : next_state = (serial_in == 0) ? S2 : S1;
			S2 : next_state = (serial_in == 1) ? S3 : S0;
			S3 : next_state = (serial_in == 1) ? S1 : S2;
		endcase

	assign detect_101 = (current_state == S3) ? 1 : 0;

endmodule