data/full_repos/permissive/493019833/test/testcase/firrtl/SimpleDspModule/reference/SimpleDspModule.v
data/verilator_xmls/ba81de7e-1e64-4b1a-8e3c-76f2700dc68d.xml
module ADD_SIGNED(y, a, b);
    parameter width = 4;
    output [width:0] y;
    input [width-1:0] a;
    input [width-1:0] b;
    assign y = $signed(a) + $signed(b);
endmodule
module ADD_SIGNED(y, a, b);

    parameter width = 4;
    output [width:0] y;
    input [width-1:0] a;
    input [width-1:0] b;
    assign y = $signed(a) + $signed(b);
endmodule