data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_idu_tb.v
1: b'%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_idu_tb.v:38: Cannot find include file: timescale_inc.v\n`include "timescale_inc.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze,data/full_repos/permissive/487568919/timescale_inc.v\n             data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze,data/full_repos/permissive/487568919/timescale_inc.v.v\n             data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze,data/full_repos/permissive/487568919/timescale_inc.v.sv\n             timescale_inc.v\n             timescale_inc.v.v\n             timescale_inc.v.sv\n             obj_dir/timescale_inc.v\n             obj_dir/timescale_inc.v.v\n             obj_dir/timescale_inc.v.sv\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_idu_tb.v:39: Cannot find include file: pacoblaze_inc.v\n`include "pacoblaze_inc.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_idu_tb.v:46: Define or directive not defined: \'`code_width\'\nreg [`code_width-1:0] instruction;  \n     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_idu_tb.v:48: Define or directive not defined: \'`operation_width\'\nwire [`operation_width-1:0] operation;  \n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_idu_tb.v:53: Define or directive not defined: \'`register_depth\'\nwire [`register_depth-1:0] x_address, y_address;  \n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_idu_tb.v:54: Define or directive not defined: \'`operand_width\'\nwire [`operand_width-1:0] implied_value;  \n      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_idu_tb.v:55: Define or directive not defined: \'`port_depth\'\nwire [`port_depth-1:0] port_address;  \n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_idu_tb.v:59: Define or directive not defined: \'`code_depth\'\nwire [`code_depth-1:0] code_address;  \n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_idu_tb.v:65: Define or directive not defined: \'`idu_debug_width\'\nwire [8*`idu_debug_width:1] debug;\n        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_idu_tb.v:65: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire [8*`idu_debug_width:1] debug;\n                        ^\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_idu_tb.v:89: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(1, dut);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_idu_tb.v:90: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("pacoblaze_idu_tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_idu_tb.v:97: Define or directive not defined: \'`code_width\'\n for (i=0; i<(1<<`code_width); i=i+1) begin\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_idu_tb.v:97: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n for (i=0; i<(1<<`code_width); i=i+1) begin\n                            ^\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_idu_tb.v:97: syntax error, unexpected \')\', expecting \';\'\n for (i=0; i<(1<<`code_width); i=i+1) begin\n                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_idu_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n  #tck $display("%h: %s", instruction, debug);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/487568919/basic_verilog/pacoblaze-2.2/pacoblaze/pacoblaze_idu_tb.v:102: syntax error, unexpected $finish\n $finish;\n ^~~~~~~\n%Error: Cannot continue\n'
module pacoblaze_idu_tb;

parameter tck = 10;


reg [`code_width-1:0] instruction;

wire [`operation_width-1:0] operation;
wire [2:0] shift_operation;
wire shift_direction;
wire shift_constant;
wire operand_selection;
wire [`register_depth-1:0] x_address, y_address;
wire [`operand_width-1:0] implied_value;
wire [`port_depth-1:0] port_address;
`ifdef HAS_SCRATCH_MEMORY
wire [`scratch_depth-1:0] scratch_address;
`endif
wire [`code_depth-1:0] code_address;
wire conditional;
wire [1:0] condition_flags;
wire interrupt_enable;

`ifdef HAS_DEBUG
wire [8*`idu_debug_width:1] debug;
`endif


`PACOBLAZE_IDU dut(
	instruction,
	operation,
	shift_operation, shift_direction, shift_constant,
	operand_selection,
	x_address, y_address,
	implied_value, port_address,
`ifdef HAS_SCRATCH_MEMORY
	scratch_address,
`endif
	code_address,
	conditional, condition_flags,
	interrupt_enable
`ifdef HAS_DEBUG
	, debug
`endif
);


initial begin
	$dumpvars(1, dut);
	$dumpfile("pacoblaze_idu_tb.vcd");

end


integer i;
initial begin
	for (i=0; i<(1<<`code_width); i=i+1) begin

		instruction = i;
		#tck $display("%h: %s", instruction, debug);
	end
	$finish;
end

endmodule
module pacoblaze_idu_tb;


parameter tck = 10;


reg [`code_width-1:0] instruction;

wire [`operation_width-1:0] operation;
wire [2:0] shift_operation;
wire shift_direction;
wire shift_constant;
wire operand_selection;
wire [`register_depth-1:0] x_address, y_address;
wire [`operand_width-1:0] implied_value;
wire [`port_depth-1:0] port_address;
`ifdef HAS_SCRATCH_MEMORY
wire [`scratch_depth-1:0] scratch_address;
`endif
wire [`code_depth-1:0] code_address;
wire conditional;
wire [1:0] condition_flags;
wire interrupt_enable;

`ifdef HAS_DEBUG
wire [8*`idu_debug_width:1] debug;
`endif


`PACOBLAZE_IDU dut(
	instruction,
	operation,
	shift_operation, shift_direction, shift_constant,
	operand_selection,
	x_address, y_address,
	implied_value, port_address,
`ifdef HAS_SCRATCH_MEMORY
	scratch_address,
`endif
	code_address,
	conditional, condition_flags,
	interrupt_enable
`ifdef HAS_DEBUG
	, debug
`endif
);


initial begin
	$dumpvars(1, dut);
	$dumpfile("pacoblaze_idu_tb.vcd");

end


integer i;
initial begin
	for (i=0; i<(1<<`code_width); i=i+1) begin

		instruction = i;
		#tck $display("%h: %s", instruction, debug);
	end
	$finish;
end

endmodule