data/full_repos/permissive/405912356/rv32i.v
1: b'%Error: data/full_repos/permissive/405912356/rv32i.v:4: Cannot find include file: rv32i_pc.v\n`include "rv32i_pc.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/405912356,data/full_repos/permissive/405912356/rv32i_pc.v\n             data/full_repos/permissive/405912356,data/full_repos/permissive/405912356/rv32i_pc.v.v\n             data/full_repos/permissive/405912356,data/full_repos/permissive/405912356/rv32i_pc.v.sv\n             rv32i_pc.v\n             rv32i_pc.v.v\n             rv32i_pc.v.sv\n             obj_dir/rv32i_pc.v\n             obj_dir/rv32i_pc.v.v\n             obj_dir/rv32i_pc.v.sv\n%Error: data/full_repos/permissive/405912356/rv32i.v:5: Cannot find include file: rv32i_pmem.v\n`include "rv32i_pmem.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/405912356/rv32i.v:6: Cannot find include file: rv32i_dmem.v\n`include "rv32i_dmem.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/405912356/rv32i.v:7: Cannot find include file: rv32i_decoder.v\n`include "rv32i_decoder.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/405912356/rv32i.v:8: Cannot find include file: rv32i_regfile.v\n`include "rv32i_regfile.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/405912356/rv32i.v:9: Cannot find include file: rv32i_selector.v\n`include "rv32i_selector.v" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/405912356/rv32i.v:10: Cannot find include file: rv32i_alu.v\n`include "rv32i_alu.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/405912356/rv32i.v:11: Cannot find include file: rv32i_comparator.v\n`include "rv32i_comparator.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/405912356/rv32i.v:43: syntax error, unexpected type\n    Comparator comparator(.in_a(out_0), .in_b(out_1), .type(funct3), .val_type(val_sel), .ld(ld));\n                                                       ^~~~\n%Error: data/full_repos/permissive/405912356/rv32i.v:56: Unsupported or unknown PLI call: $monitor\n        $monitor("cnt: %d .. clk: %b, reset: %b .. alu_out = %x", cnt, clk, reset, alu_out);\n        ^~~~~~~~\n%Error: data/full_repos/permissive/405912356/rv32i.v:57: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("rv32i.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/405912356/rv32i.v:58: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, rv32i);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/405912356/rv32i.v:62: Unsupported: Ignoring delay on this delayed statement.\n        #1 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/405912356/rv32i.v:70: Unsupported: Ignoring delay on this delayed statement.\n        #4\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/405912356/rv32i.v:72: Unsupported: Ignoring delay on this delayed statement.\n        #150\n        ^\n%Error: Exiting due to 12 error(s), 3 warning(s)\n'
module RV32I_tb();
    reg [9: 0] cnt;
    reg clk;
    reg reset;
    wire [31: 0] alu_out;
    RV32I rv32i(clk, reset, alu_out);

    initial begin
        $monitor("cnt: %d .. clk: %b, reset: %b .. alu_out = %x", cnt, clk, reset, alu_out);
        $dumpfile("rv32i.vcd");
        $dumpvars(0, rv32i);
    end

    always begin
        #1 clk = ~clk;
        cnt += (clk == 1) ? 1 : 0;
    end

    initial begin
        cnt = 0;
        clk = 0;
        reset = 0;
        #4
        reset = 1;
        #150
        $finish;
    end
endmodule
module RV32I_tb();

    reg [9: 0] cnt;
    reg clk;
    reg reset;
    wire [31: 0] alu_out;
    RV32I rv32i(clk, reset, alu_out);

    initial begin
        $monitor("cnt: %d .. clk: %b, reset: %b .. alu_out = %x", cnt, clk, reset, alu_out);
        $dumpfile("rv32i.vcd");
        $dumpvars(0, rv32i);
    end

    always begin
        #1 clk = ~clk;
        cnt += (clk == 1) ? 1 : 0;
    end

    initial begin
        cnt = 0;
        clk = 0;
        reset = 0;
        #4
        reset = 1;
        #150
        $finish;
    end
endmodule