data/full_repos/permissive/484799296/verilog/pc_add/pc_add.v
data/verilator_xmls/21e14ecb-07ab-4422-8a12-2246e740e194.xml
module pc_add (
    input enable,
    input [11:0] pc_addr,
    input [11:0] in_addr,
    output [11:0] out_addr
);

    assign out_addr = enable? in_addr + pc_addr:pc_addr;

endmodule
module pc_add (
    input enable,
    input [11:0] pc_addr,
    input [11:0] in_addr,
    output [11:0] out_addr
);


    assign out_addr = enable? in_addr + pc_addr:pc_addr;

endmodule