data/full_repos/permissive/485467282/alu.v
data/verilator_xmls/5c6e51c7-6a5d-4307-9c97-21fd3bbe3d13.xml
module alu(
           input [15:0] A,B,
           input [2:0] ALU_Sel,
           input [3:0] shamt,
           output [15:0] ALU_Out,
           output CarryOut
    );
    reg [15:0] ALU_Result;
    wire [16:0] tmp;
    assign ALU_Out = ALU_Result;
    assign tmp = {1'b0,A} + {1'b0,B};
    assign CarryOut = tmp[16];

    always @(*)
    begin
        case(ALU_Sel)
          3'b000:
           ALU_Result = A + B ; 
          3'b001:
           ALU_Result = A - B ;
          3'b010:
           ALU_Result = A & B;
          3'b011:
           ALU_Result = A | B;
          3'b100:
           ALU_Result = A ^ B;
          3'b101:
           ALU_Result = ~(A | B);
          3'b110:
           ALU_Result = ~(A & B);
          3'b111:
           ALU_Result = A<<shamt;
          default: ALU_Result = A + B; 
        endcase
    end
endmodule
module alu(
           input [15:0] A,B,
           input [2:0] ALU_Sel,
           input [3:0] shamt,
           output [15:0] ALU_Out,
           output CarryOut
    );

    reg [15:0] ALU_Result;
    wire [16:0] tmp;
    assign ALU_Out = ALU_Result;
    assign tmp = {1'b0,A} + {1'b0,B};
    assign CarryOut = tmp[16];

    always @(*)
    begin
        case(ALU_Sel)
          3'b000:
           ALU_Result = A + B ; 
          3'b001:
           ALU_Result = A - B ;
          3'b010:
           ALU_Result = A & B;
          3'b011:
           ALU_Result = A | B;
          3'b100:
           ALU_Result = A ^ B;
          3'b101:
           ALU_Result = ~(A | B);
          3'b110:
           ALU_Result = ~(A & B);
          3'b111:
           ALU_Result = A<<shamt;
          default: ALU_Result = A + B; 
        endcase
    end
endmodule