data/full_repos/permissive/434187796/src/TIME_MODULE.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/434187796/src/TIME_MODULE.v:71: Cell has missing pin: \'cy\'\n                hour_h\n                ^~~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module TIME_SEG_UNIT
        #(
                parameter [3:0] target_cy_count = 4'd0,
                parameter [3:0] target_cy_num = 4'h9
        )
        (
                input clk,
                input rst,
                output reg cy,
                output reg [3:0] time_data
        );

        wire [3:0] time_next;
        wire [3:0] cy_count_next;
        wire cy_is_enough;
        wire [3:0] target_max;
        reg [3:0] cy_count;

        initial begin
                cy_count <= 4'd0;
                time_data <= 4'h0;
                cy <= 1'b0;
        end

        assign cy_is_enough = (cy_count == target_cy_count) ? 1'b1 : 1'b0;
        assign target_max = cy_is_enough ? target_cy_num : 4'h9;
        assign cy_count_next = cy_is_enough ? 4'd0 : cy_count + 4'd1;
        assign time_next = (time_data == target_max) ? 4'b0 : time_data + 4'b1;

        always @(posedge clk or negedge rst) begin
                if (rst == 1'b0) begin
                        time_data <= 4'h0;
                        cy <= 1'b0;
                end else begin
                        time_data <= time_next;
                        cy <= (time_next == 4'b0) ? 1'b1 : 1'b0;
                end
        end

        always @(posedge cy or negedge rst) begin
                if (rst == 1'b0) begin
                        cy_count <= 4'd0;
                end else begin
                        cy_count <= cy_count_next;
                end
        end
endmodule
module TIME_SEG_UNIT
        #(
                parameter [3:0] target_cy_count = 4'd0,
                parameter [3:0] target_cy_num = 4'h9
        )
        (
                input clk,
                input rst,
                output reg cy,
                output reg [3:0] time_data
        );


        wire [3:0] time_next;
        wire [3:0] cy_count_next;
        wire cy_is_enough;
        wire [3:0] target_max;
        reg [3:0] cy_count;

        initial begin
                cy_count <= 4'd0;
                time_data <= 4'h0;
                cy <= 1'b0;
        end

        assign cy_is_enough = (cy_count == target_cy_count) ? 1'b1 : 1'b0;
        assign target_max = cy_is_enough ? target_cy_num : 4'h9;
        assign cy_count_next = cy_is_enough ? 4'd0 : cy_count + 4'd1;
        assign time_next = (time_data == target_max) ? 4'b0 : time_data + 4'b1;

        always @(posedge clk or negedge rst) begin
                if (rst == 1'b0) begin
                        time_data <= 4'h0;
                        cy <= 1'b0;
                end else begin
                        time_data <= time_next;
                        cy <= (time_next == 4'b0) ? 1'b1 : 1'b0;
                end
        end

        always @(posedge cy or negedge rst) begin
                if (rst == 1'b0) begin
                        cy_count <= 4'd0;
                end else begin
                        cy_count <= cy_count_next;
                end
        end
endmodule