data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/aes/MixColumns.v
data/verilator_xmls/79ff5761-0178-4c10-bf7e-e631745ed092.xml
module xtime (
	output [7:0] y,
	input [7:0] x
	);
	
	wire [7:0] w;
	assign w = x << 1;


	assign y = x[7]? w ^ 8'h1B : w;
	

endmodule
module xtime (
	output [7:0] y,
	input [7:0] x
	);

	
	wire [7:0] w;
	assign w = x << 1;


	assign y = x[7]? w ^ 8'h1B : w;
	

endmodule