data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v
1: b'%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:41: Cannot find include file: uprj_netlists.v\n`include "uprj_netlists.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1,data/full_repos/permissive/432384243/uprj_netlists.v\n             data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1,data/full_repos/permissive/432384243/uprj_netlists.v.v\n             data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1,data/full_repos/permissive/432384243/uprj_netlists.v.sv\n             uprj_netlists.v\n             uprj_netlists.v.v\n             uprj_netlists.v.sv\n             obj_dir/uprj_netlists.v\n             obj_dir/uprj_netlists.v.v\n             obj_dir/uprj_netlists.v.sv\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:42: Cannot find include file: user_reg_map.v\n`include "user_reg_map.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:74: Unsupported: event data types\n        event      error_insert;\n        ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n always #12.5 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n  #200;  \n  ^\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:107: syntax error, unexpected \'@\'\n         repeat (10) @(posedge clock);\n                     ^\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:112: Define or directive not defined: \'`ADDR_SPACE_WBHOST\'\n  wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,\'h1);\n                     ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:112: Define or directive not defined: \'`WBHOST_GLBL_CFG\'\n  wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,\'h1);\n                                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:112: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,\'h1);\n                                                        ^\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:114: Unsupported or unknown PLI call: $dumpoff\n  $dumpoff;\n  ^~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:132: Unsupported or unknown PLI call: $dumpon\n  $dumpon;\n  ^~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:152: Unsupported or unknown PLI call: $dumpoff\n  $dumpoff;\n  ^~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:193: Unsupported or unknown PLI call: $dumpoff\n                $dumpoff;\n                ^~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:216: Unsupported or unknown PLI call: $dumpon\n  $dumpon;\n  ^~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:260: Unsupported or unknown PLI call: $dumpon\n  $dumpon;\n  ^~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:284: Unsupported or unknown PLI call: $dumpon\n  $dumpon;\n  ^~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:288: Unsupported or unknown PLI call: $dumpon\n  $dumpon;\n  ^~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:289: Unsupported: fork statements\n  fork\n  ^~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:292: Define or directive not defined: \'`ADDR_SPACE_GLBL\'\n                    wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_BIST_CTRL2,\'h000);\n                                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:292: Define or directive not defined: \'`GLBL_BIST_CTRL2\'\n                    wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_BIST_CTRL2,\'h000);\n                                                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:292: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                    wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_BIST_CTRL2,\'h000);\n                                                                        ^\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:297: Define or directive not defined: \'`ADDR_SPACE_MBIST1\'\n                        wb_user_core_write(`ADDR_SPACE_MBIST1+(i*4),writemem[i]);\n                                           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:298: Define or directive not defined: \'`ADDR_SPACE_MBIST2\'\n                        wb_user_core_write(`ADDR_SPACE_MBIST2+(i*4),writemem[i]);\n                                           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:299: Define or directive not defined: \'`ADDR_SPACE_MBIST3\'\n                        wb_user_core_write(`ADDR_SPACE_MBIST3+(i*4),writemem[i]);\n                                           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:300: Define or directive not defined: \'`ADDR_SPACE_MBIST4\'\n                        wb_user_core_write(`ADDR_SPACE_MBIST4+(i*4),writemem[i]);\n                                           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:302: Define or directive not defined: \'`ADDR_SPACE_MBIST5\'\n                           wb_user_core_write(`ADDR_SPACE_MBIST5+(i*4),writemem[i]);\n                                              ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:303: Define or directive not defined: \'`ADDR_SPACE_MBIST6\'\n                           wb_user_core_write(`ADDR_SPACE_MBIST6+(i*4),writemem[i]);\n                                              ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:304: Define or directive not defined: \'`ADDR_SPACE_MBIST7\'\n                           wb_user_core_write(`ADDR_SPACE_MBIST7+(i*4),writemem[i]);\n                                              ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:305: Define or directive not defined: \'`ADDR_SPACE_MBIST8\'\n                           wb_user_core_write(`ADDR_SPACE_MBIST8+(i*4),writemem[i]);\n                                              ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:310: Define or directive not defined: \'`ADDR_SPACE_MBIST1\'\n                        wb_user_core_read_check(`ADDR_SPACE_MBIST1+(i*4),read_data,writemem[i],32\'hFFFFFFFF);\n                                                ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:311: Define or directive not defined: \'`ADDR_SPACE_MBIST2\'\n                        wb_user_core_read_check(`ADDR_SPACE_MBIST2+(i*4),read_data,writemem[i],32\'hFFFFFFFF);\n                                                ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:312: Define or directive not defined: \'`ADDR_SPACE_MBIST3\'\n                        wb_user_core_read_check(`ADDR_SPACE_MBIST3+(i*4),read_data,writemem[i],32\'hFFFFFFFF);\n                                                ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:313: Define or directive not defined: \'`ADDR_SPACE_MBIST4\'\n                        wb_user_core_read_check(`ADDR_SPACE_MBIST4+(i*4),read_data,writemem[i],32\'hFFFFFFFF);\n                                                ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:315: Define or directive not defined: \'`ADDR_SPACE_MBIST5\'\n                           wb_user_core_read_check(`ADDR_SPACE_MBIST5+(i*4),read_data,writemem[i],32\'hFFFFFFFF);\n                                                   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:316: Define or directive not defined: \'`ADDR_SPACE_MBIST6\'\n                           wb_user_core_read_check(`ADDR_SPACE_MBIST6+(i*4),read_data,writemem[i],32\'hFFFFFFFF);\n                                                   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:317: Define or directive not defined: \'`ADDR_SPACE_MBIST7\'\n                           wb_user_core_read_check(`ADDR_SPACE_MBIST7+(i*4),read_data,writemem[i],32\'hFFFFFFFF);\n                                                   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:318: Define or directive not defined: \'`ADDR_SPACE_MBIST8\'\n                           wb_user_core_read_check(`ADDR_SPACE_MBIST8+(i*4),read_data,writemem[i],32\'hFFFFFFFF);\n                                                   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:327: Define or directive not defined: \'`ADDR_SPACE_MBIST1\'\n                    wb_user_core_read_check(`ADDR_SPACE_MBIST1 + (9\'h1FC *4),read_data,writemem[9\'h10],32\'hFFFFFFFF);\n                                            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:328: Define or directive not defined: \'`ADDR_SPACE_MBIST1\'\n                    wb_user_core_read_check(`ADDR_SPACE_MBIST1 + (9\'h1FD *4),read_data,writemem[9\'h20],32\'hFFFFFFFF);\n                                            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:329: Define or directive not defined: \'`ADDR_SPACE_MBIST1\'\n                    wb_user_core_read_check(`ADDR_SPACE_MBIST1 + (9\'h1FE *4),read_data,writemem[9\'h30],32\'hFFFFFFFF);\n                                            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:330: Define or directive not defined: \'`ADDR_SPACE_MBIST1\'\n                    wb_user_core_read_check(`ADDR_SPACE_MBIST1 + (9\'h1FF *4),read_data,writemem[9\'h40],32\'hFFFFFFFF);\n                                            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:333: Define or directive not defined: \'`ADDR_SPACE_MBIST2\'\n                    wb_user_core_read_check(`ADDR_SPACE_MBIST2 + (9\'h1FC *4),read_data,writemem[9\'h11],32\'hFFFFFFFF);\n                                            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:334: Define or directive not defined: \'`ADDR_SPACE_MBIST2\'\n                    wb_user_core_read_check(`ADDR_SPACE_MBIST2 + (9\'h1FD *4),read_data,writemem[9\'h21],32\'hFFFFFFFF);\n                                            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:335: Define or directive not defined: \'`ADDR_SPACE_MBIST2\'\n                    wb_user_core_read_check(`ADDR_SPACE_MBIST2 + (9\'h1FE *4),read_data,writemem[9\'h31],32\'hFFFFFFFF);\n                                            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:336: Define or directive not defined: \'`ADDR_SPACE_MBIST2\'\n                    wb_user_core_read_check(`ADDR_SPACE_MBIST2 + (9\'h1FF *4),read_data,writemem[9\'h41],32\'hFFFFFFFF);\n                                            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:339: Define or directive not defined: \'`ADDR_SPACE_MBIST3\'\n                    wb_user_core_read_check(`ADDR_SPACE_MBIST3 + (9\'h1FC *4),read_data,writemem[9\'h12],32\'hFFFFFFFF);\n                                            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:340: Define or directive not defined: \'`ADDR_SPACE_MBIST3\'\n                    wb_user_core_read_check(`ADDR_SPACE_MBIST3 + (9\'h1FD *4),read_data,writemem[9\'h22],32\'hFFFFFFFF);\n                                            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:341: Define or directive not defined: \'`ADDR_SPACE_MBIST3\'\n                    wb_user_core_read_check(`ADDR_SPACE_MBIST3 + (9\'h1FE *4),read_data,writemem[9\'h32],32\'hFFFFFFFF);\n                                            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:342: Define or directive not defined: \'`ADDR_SPACE_MBIST3\'\n                    wb_user_core_read_check(`ADDR_SPACE_MBIST3 + (9\'h1FF *4),read_data,writemem[9\'h42],32\'hFFFFFFFF);\n                                            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:345: Define or directive not defined: \'`ADDR_SPACE_MBIST4\'\n                    wb_user_core_read_check(`ADDR_SPACE_MBIST4 + (9\'h1FC *4),read_data,writemem[9\'h13],32\'hFFFFFFFF);\n                                            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:346: Define or directive not defined: \'`ADDR_SPACE_MBIST4\'\n                    wb_user_core_read_check(`ADDR_SPACE_MBIST4 + (9\'h1FD *4),read_data,writemem[9\'h23],32\'hFFFFFFFF);\n                                            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v:347: Define or directive not defined: \'`ADDR_SPACE_MBIST4\'\n                    wb_user_core_read_check(`ADDR_SPACE_MBIST4 + (9\'h1FE *4),read_data,writemem[9\'h33],32\'hFFFFFFFF);\n                                            ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module user_mbist_test1_tb;
	reg clock;
	reg wb_rst_i;
	reg power1, power2;
	reg power3, power4;

        reg        wbd_ext_cyc_i;
        reg        wbd_ext_stb_i;
        reg [31:0] wbd_ext_adr_i;
        reg        wbd_ext_we_i;
        reg [31:0] wbd_ext_dat_i;
        reg [3:0]  wbd_ext_sel_i;

        wire [31:0] wbd_ext_dat_o;
        wire        wbd_ext_ack_o;
        wire        wbd_ext_err_o;


	wire [37:0] io_oeb;
	wire [37:0] io_out;
	wire [37:0] io_in;

	wire gpio;
	wire [37:0] mprj_io;
	wire [7:0] mprj_io_0;
	reg        test_fail;
	reg [31:0] read_data;
        reg [31:0] writemem [0:511];
        reg [8:0]  faultaddr [0:7];
        integer i;
        event      error_insert;






	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
                wbd_ext_cyc_i ='h0;
                wbd_ext_stb_i ='h0;
                wbd_ext_adr_i ='h0;
                wbd_ext_we_i  ='h0;
                wbd_ext_dat_i ='h0;
                wbd_ext_sel_i ='h0;
	end

	`ifdef WFDUMP
	   initial begin
	   	$dumpfile("simx.vcd");
	   	$dumpvars(5, user_mbist_test1_tb);
		$dumpoff;
	   end
       `endif

	initial begin
		wb_rst_i <= 1'b1;
		#100;
		wb_rst_i <= 1'b0;

		#200;
	        repeat (10) @(posedge clock);
		$display("Monitor: Standalone User Test Started");

		test_fail = 0;

		wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);

		$dumpoff;
	    	$display("###################################################");
	    	$display(" MBIST Test with Without Address Failure");
	    	$display("###################################################");







		insert_fault(0,0,64'h01010101_01010101);

          	if(test_fail == 0) begin
	    	    $display("Monitor: Step-1: BIST Test without any Memory Error insertion test Passed");
	        end else begin
	    	    $display("Monitor: Step-1: BIST Test without any Memory Error insertion test Failed");
		end
		$dumpon;
	    	$display("###################################################");
	    	$display(" MBIST Test with Single Address Failure");
	    	$display("###################################################");







		faultaddr[0] = 9'h10;
		insert_fault(1,1,64'h15151515_15151515);

          	if(test_fail == 0) begin
	    	    $display("Monitor: Step-2: BIST Test with One Memory Error insertion test Passed");
	        end else begin
	    	    $display("Monitor: Step-2: BIST Test with One Memory Error insertion test Failed");
		 end
	    	$display("###################################################");
		$dumpoff;
	    	$display("###################################################");
	    	$display(" MBIST Test with Two Address Failure");
	    	$display("###################################################");







		faultaddr[0] = 9'h10;
		faultaddr[1] = 9'h20;
		insert_fault(2,0,64'h25252525_25252525);

          	if(test_fail == 0) begin
	    	    $display("Monitor: Step-3: BIST Test with Two Memory Error insertion test Passed");
	        end else begin
	    	    $display("Monitor: Step-3: BIST Test with Two Memory Error insertion test Failed");
		 end
	    	$display("###################################################");
	    	$display(" MBIST Test with Three Address Failure");
	    	$display("###################################################");








		faultaddr[0] = 9'h10;
		faultaddr[1] = 9'h20;
		faultaddr[2] = 9'h30;
		insert_fault(3,1,64'h35353535_35353535);

          	if(test_fail == 0) begin
	    	    $display("Monitor: Step-4: BIST Test with Three Memory Error insertion test Passed");
	        end else begin
	    	    $display("Monitor: Step-4: BIST Test with Three Memory Error insertion test Failed");
		 end
                $dumpoff;
	    	$display("###################################################");
	    	$display(" MBIST Test with Fours Address Failure");
	    	$display("###################################################");







		faultaddr[0] = 9'h10;
		faultaddr[1] = 9'h20;
		faultaddr[2] = 9'h30;
		faultaddr[3] = 9'h40;
		insert_fault(4,0,64'h45454545_45454545);

          	if(test_fail == 0) begin
	    	    $display("Monitor: Step-5: BIST Test with Four Memory Error insertion test Passed");
	        end else begin
	    	    $display("Monitor: Step-5: BIST Test with Four Memory Error insertion test Failed");
		end

		$dumpon;
	    	$display("###################################################");
	    	$display(" MBIST Test with Fours Address(Continous Starting Addrsess) Failure");
	    	$display("###################################################");







		faultaddr[0] = 9'h0;
		faultaddr[1] = 9'h1;
		faultaddr[2] = 9'h2;
		faultaddr[3] = 9'h3;
		insert_fault(4,0,64'h45454545_45454545);

          	if(test_fail == 0) begin
	    	    $display("Monitor: Step-5.2: BIST Test with Four Memory Error insertion test Passed");
	        end else begin
	    	    $display("Monitor: Step-5.2: BIST Test with Four Memory Error insertion test Failed");
		end

	    	$display("###################################################");
	    	$display(" MBIST Test with Fours Address(Last Addrsess) Failure");
	    	$display("###################################################");







		faultaddr[0] = 9'hF0;
		faultaddr[1] = 9'hF1;
		faultaddr[2] = 9'hF2;
		faultaddr[3] = 9'hF3;
		insert_fault(4,0,64'h45454545_45454545);

          	if(test_fail == 0) begin
	    	    $display("Monitor: Step-5.3: BIST Test with Four Memory Error insertion test Passed");
	        end else begin
	    	    $display("Monitor: Step-5.3: BIST Test with Four Memory Error insertion test Failed");
		end
		$dumpon;
	    	$display("###################################################");
	    	$display(" MBIST Test with Five Address Failure");
	    	$display("###################################################");







		faultaddr[0] = 9'h10;
		faultaddr[1] = 9'h20;
		faultaddr[2] = 9'h30;
		faultaddr[3] = 9'h40;
		faultaddr[4] = 9'h50;
		insert_fault(5,1,64'h47474747_47474747);

          	if(test_fail == 0) begin
	    	    $display("Monitor: Step-5: BIST Test with Five Memory Error insertion test Passed");
	        end else begin
	    	    $display("Monitor: Step-5: BIST Test with Five Memory Error insertion test Failed");
		 end

		$dumpon;
	    	$display("###################################################");
	    	$display(" MBIST Test with Functional Access, continuation of previous MBIST Signature");
	    	$display("###################################################");
		$dumpon;
		fork
		begin

                    wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_BIST_CTRL2,'h000);
  

		    for (i=0; i< 9'h1FC; i=i+1) begin
   	                writemem[i] = $random;
                        wb_user_core_write(`ADDR_SPACE_MBIST1+(i*4),writemem[i]);
                        wb_user_core_write(`ADDR_SPACE_MBIST2+(i*4),writemem[i]);
                        wb_user_core_write(`ADDR_SPACE_MBIST3+(i*4),writemem[i]);
                        wb_user_core_write(`ADDR_SPACE_MBIST4+(i*4),writemem[i]);
		        if(i < 9'h0FC) begin
                           wb_user_core_write(`ADDR_SPACE_MBIST5+(i*4),writemem[i]);
                           wb_user_core_write(`ADDR_SPACE_MBIST6+(i*4),writemem[i]);
                           wb_user_core_write(`ADDR_SPACE_MBIST7+(i*4),writemem[i]);
                           wb_user_core_write(`ADDR_SPACE_MBIST8+(i*4),writemem[i]);
	                end
		    end

		    for (i=0; i< 9'h1FC; i=i+1) begin
                        wb_user_core_read_check(`ADDR_SPACE_MBIST1+(i*4),read_data,writemem[i],32'hFFFFFFFF);
                        wb_user_core_read_check(`ADDR_SPACE_MBIST2+(i*4),read_data,writemem[i],32'hFFFFFFFF);
                        wb_user_core_read_check(`ADDR_SPACE_MBIST3+(i*4),read_data,writemem[i],32'hFFFFFFFF);
                        wb_user_core_read_check(`ADDR_SPACE_MBIST4+(i*4),read_data,writemem[i],32'hFFFFFFFF);
		        if(i < 9'h0FC) begin
                           wb_user_core_read_check(`ADDR_SPACE_MBIST5+(i*4),read_data,writemem[i],32'hFFFFFFFF);
                           wb_user_core_read_check(`ADDR_SPACE_MBIST6+(i*4),read_data,writemem[i],32'hFFFFFFFF);
                           wb_user_core_read_check(`ADDR_SPACE_MBIST7+(i*4),read_data,writemem[i],32'hFFFFFFFF);
                           wb_user_core_read_check(`ADDR_SPACE_MBIST8+(i*4),read_data,writemem[i],32'hFFFFFFFF);
	                end
		    end






                    wb_user_core_read_check(`ADDR_SPACE_MBIST1 + (9'h1FC *4),read_data,writemem[9'h10],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST1 + (9'h1FD *4),read_data,writemem[9'h20],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST1 + (9'h1FE *4),read_data,writemem[9'h30],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST1 + (9'h1FF *4),read_data,writemem[9'h40],32'hFFFFFFFF);


                    wb_user_core_read_check(`ADDR_SPACE_MBIST2 + (9'h1FC *4),read_data,writemem[9'h11],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST2 + (9'h1FD *4),read_data,writemem[9'h21],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST2 + (9'h1FE *4),read_data,writemem[9'h31],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST2 + (9'h1FF *4),read_data,writemem[9'h41],32'hFFFFFFFF);


                    wb_user_core_read_check(`ADDR_SPACE_MBIST3 + (9'h1FC *4),read_data,writemem[9'h12],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST3 + (9'h1FD *4),read_data,writemem[9'h22],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST3 + (9'h1FE *4),read_data,writemem[9'h32],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST3 + (9'h1FF *4),read_data,writemem[9'h42],32'hFFFFFFFF);


                    wb_user_core_read_check(`ADDR_SPACE_MBIST4 + (9'h1FC *4),read_data,writemem[9'h13],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST4 + (9'h1FD *4),read_data,writemem[9'h23],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST4 + (9'h1FE *4),read_data,writemem[9'h33],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST4 + (9'h1FF *4),read_data,writemem[9'h43],32'hFFFFFFFF);


                    wb_user_core_read_check(`ADDR_SPACE_MBIST5 + (8'hFC *4),read_data,writemem[9'h14],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST5 + (8'hFD *4),read_data,writemem[9'h24],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST5 + (8'hFE *4),read_data,writemem[9'h34],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST5 + (8'hFF *4),read_data,writemem[9'h44],32'hFFFFFFFF);


                    wb_user_core_read_check(`ADDR_SPACE_MBIST6 + (8'hFC *4),read_data,writemem[9'h15],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST6 + (8'hFD *4),read_data,writemem[9'h25],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST6 + (8'hFE *4),read_data,writemem[9'h35],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST6 + (8'hFF *4),read_data,writemem[9'h45],32'hFFFFFFFF);


                    wb_user_core_read_check(`ADDR_SPACE_MBIST7 + (8'hFC *4),read_data,writemem[9'h16],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST7 + (8'hFD *4),read_data,writemem[9'h26],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST7 + (8'hFE *4),read_data,writemem[9'h36],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST7 + (8'hFF *4),read_data,writemem[9'h46],32'hFFFFFFFF);


                    wb_user_core_read_check(`ADDR_SPACE_MBIST8 + (8'hFC *4),read_data,writemem[9'h17],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST8 + (8'hFD *4),read_data,writemem[9'h27],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST8 + (8'hFE *4),read_data,writemem[9'h37],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST8 + (8'hFF *4),read_data,writemem[9'h47],32'hFFFFFFFF);
                end
                begin

                   repeat (200000) @(posedge clock);

                   test_fail = 1;
                end
                join_any
                disable fork;
          	if(test_fail == 0) begin
	    	    $display("Monitor: Step-5: BIST Test with Functional access test Passed");
	        end else begin
	    	    $display("Monitor: Step-5: BIST Test with Functional access test failed");
		 end

	    	$display("###################################################");
	        $finish;
	end

wire USER_VDD1V8 = 1'b1;
wire VSS = 1'b0;


user_project_wrapper u_top(
`ifdef USE_POWER_PINS
    .vccd1(USER_VDD1V8),
    .vssd1(VSS),
`endif
    .wb_clk_i        (clock),
    .user_clock2     (1'b1),
    .wb_rst_i        (wb_rst_i),

    .wbs_cyc_i   (wbd_ext_cyc_i),
    .wbs_stb_i   (wbd_ext_stb_i),
    .wbs_adr_i   (wbd_ext_adr_i),
    .wbs_we_i    (wbd_ext_we_i),
    .wbs_dat_i   (wbd_ext_dat_i),
    .wbs_sel_i   (wbd_ext_sel_i),

    .wbs_dat_o   (wbd_ext_dat_o),
    .wbs_ack_o   (wbd_ext_ack_o),

 

    .la_data_in      ('1) ,
    .la_data_out     (),
    .la_oenb         ('0),
 


    .io_in          (io_in)  ,
    .io_out         (io_out) ,
    .io_oeb         (io_oeb) ,

    .user_irq       () 

);

`ifndef GL

    initial begin


    end
`endif    






task insert_fault;
input [3:0]  num_fault;
input        fault_type;
input [63:0]  mbist_signature;
reg [31:0] datain;
reg [8:0]  fail_addr1;
reg [8:0]  fail_addr2;
reg [8:0]  fail_addr3;
reg [8:0]  fail_addr4;
integer j;
begin
   repeat (2) @(posedge clock);

   wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_BIST_CTRL2,'h000);

   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h001);

   wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_BIST_CTRL2,'h33333333);

   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h003);
   fork
   begin

      read_data = 'h0;
      while (read_data[0] != 1'b1) begin
         wb_user_core_read(`ADDR_SPACE_GLBL+`GLBL_BIST_STAT1,read_data);
      end

      repeat (1000) @(posedge clock);






      wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_BIST_STAT1,read_data,mbist_signature[31:0],32'hFFFFFFFF);
      wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_BIST_STAT2,read_data,mbist_signature[63:32],32'hFFFFFFFF);
   end

   begin
      while(1) begin
         repeat (1) @(posedge clock);
         #1;

         if(u_top.u_sram1_2kb.web0 == 1'b0 && 
	   ((num_fault > 0 && u_top.u_sram1_2kb.addr0 == faultaddr[0]) ||
	    (num_fault > 1 && u_top.u_sram1_2kb.addr0 == faultaddr[1]) ||
	    (num_fault > 2 && u_top.u_sram1_2kb.addr0 == faultaddr[2]) ||
	    (num_fault > 3 && u_top.u_sram1_2kb.addr0 == faultaddr[3]) ||
	    (num_fault > 4 && u_top.u_sram1_2kb.addr0 == faultaddr[4]) ||
	    (num_fault > 5 && u_top.u_sram1_2kb.addr0 == faultaddr[5]) ||
	    (num_fault > 6 && u_top.u_sram1_2kb.addr0 == faultaddr[6]) ||
	    (num_fault > 7 && u_top.u_sram1_2kb.addr0 == faultaddr[7])))
             begin
	   if(fault_type == 0)
	      force u_top.u_sram1_2kb.din0 = u_top.mem1_din_b  & 32'hFFFF_FFFE;
	   else
	      force u_top.u_sram1_2kb.din0 = u_top.mem1_din_b | 32'h1;
   	   -> error_insert;
         end else begin
            release u_top.u_sram1_2kb.din0;
         end

         if(u_top.u_sram2_2kb.web0 == 1'b0 && 
	   ((num_fault > 0 && u_top.u_sram2_2kb.addr0 == faultaddr[0]+1) ||
	    (num_fault > 1 && u_top.u_sram2_2kb.addr0 == faultaddr[1]+1) ||
	    (num_fault > 2 && u_top.u_sram2_2kb.addr0 == faultaddr[2]+1) ||
	    (num_fault > 3 && u_top.u_sram2_2kb.addr0 == faultaddr[3]+1) ||
	    (num_fault > 4 && u_top.u_sram2_2kb.addr0 == faultaddr[4]+1) ||
	    (num_fault > 5 && u_top.u_sram2_2kb.addr0 == faultaddr[5]+1) ||
	    (num_fault > 6 && u_top.u_sram2_2kb.addr0 == faultaddr[6]+1) ||
	    (num_fault > 7 && u_top.u_sram2_2kb.addr0 == faultaddr[7]+1)))
             begin
	   if(fault_type == 0)
	      force u_top.u_sram2_2kb.din0 = u_top.mem2_din_b  & 32'hFFFF_FFFE;
	   else
	      force u_top.u_sram2_2kb.din0 = u_top.mem2_din_b | 32'h1;
   	   -> error_insert;
         end else begin
            release u_top.u_sram2_2kb.din0;
         end

         if(u_top.u_sram3_2kb.web0 == 1'b0 && 
	   ((num_fault > 0 && u_top.u_sram3_2kb.addr0 == faultaddr[0]+2) ||
	    (num_fault > 1 && u_top.u_sram3_2kb.addr0 == faultaddr[1]+2) ||
	    (num_fault > 2 && u_top.u_sram3_2kb.addr0 == faultaddr[2]+2) ||
	    (num_fault > 3 && u_top.u_sram3_2kb.addr0 == faultaddr[3]+2) ||
	    (num_fault > 4 && u_top.u_sram3_2kb.addr0 == faultaddr[4]+2) ||
	    (num_fault > 5 && u_top.u_sram3_2kb.addr0 == faultaddr[5]+2) ||
	    (num_fault > 6 && u_top.u_sram3_2kb.addr0 == faultaddr[6]+2) ||
	    (num_fault > 7 && u_top.u_sram3_2kb.addr0 == faultaddr[7]+2)))
             begin
	   if(fault_type == 0)
	      force u_top.u_sram3_2kb.din0 = u_top.mem3_din_b  & 32'hFFFF_FFFE;
	   else
	      force u_top.u_sram3_2kb.din0 = u_top.mem3_din_b | 32'h1;
   	   -> error_insert;
         end else begin
            release u_top.u_sram3_2kb.din0;
         end

         if(u_top.u_sram4_2kb.web0 == 1'b0 && 
	   ((num_fault > 0 && u_top.u_sram4_2kb.addr0 == faultaddr[0]+3) ||
	    (num_fault > 1 && u_top.u_sram4_2kb.addr0 == faultaddr[1]+3) ||
	    (num_fault > 2 && u_top.u_sram4_2kb.addr0 == faultaddr[2]+3) ||
	    (num_fault > 3 && u_top.u_sram4_2kb.addr0 == faultaddr[3]+3) ||
	    (num_fault > 4 && u_top.u_sram4_2kb.addr0 == faultaddr[4]+3) ||
	    (num_fault > 5 && u_top.u_sram4_2kb.addr0 == faultaddr[5]+3) ||
	    (num_fault > 6 && u_top.u_sram4_2kb.addr0 == faultaddr[6]+3) ||
	    (num_fault > 7 && u_top.u_sram4_2kb.addr0 == faultaddr[7]+3)))
             begin
	   if(fault_type == 0)
	      force u_top.u_sram4_2kb.din0 = u_top.mem4_din_b  & 32'hFFFF_FFFE;
	   else
	      force u_top.u_sram4_2kb.din0 = u_top.mem4_din_b | 32'h1;
   	   -> error_insert;
         end else begin
            release u_top.u_sram4_2kb.din0;
         end

         if(u_top.u_sram5_1kb.web0 == 1'b0 && 
	   ((num_fault > 0 && u_top.u_sram5_1kb.addr0 == faultaddr[0]+4) ||
	    (num_fault > 1 && u_top.u_sram5_1kb.addr0 == faultaddr[1]+4) ||
	    (num_fault > 2 && u_top.u_sram5_1kb.addr0 == faultaddr[2]+4) ||
	    (num_fault > 3 && u_top.u_sram5_1kb.addr0 == faultaddr[3]+4) ||
	    (num_fault > 4 && u_top.u_sram5_1kb.addr0 == faultaddr[4]+4) ||
	    (num_fault > 5 && u_top.u_sram5_1kb.addr0 == faultaddr[5]+4) ||
	    (num_fault > 6 && u_top.u_sram5_1kb.addr0 == faultaddr[6]+4) ||
	    (num_fault > 7 && u_top.u_sram5_1kb.addr0 == faultaddr[7]+4)))
             begin
	   if(fault_type == 0)
	      force u_top.u_sram5_1kb.din0 = u_top.mem5_din_b  & 32'hFFFF_FFFE;
	   else
	      force u_top.u_sram5_1kb.din0 = u_top.mem5_din_b | 32'h1;
   	   -> error_insert;
         end else begin
            release u_top.u_sram5_1kb.din0;
         end

         if(u_top.u_sram6_1kb.web0 == 1'b0 && 
	   ((num_fault > 0 && u_top.u_sram6_1kb.addr0 == faultaddr[0]+5) ||
	    (num_fault > 1 && u_top.u_sram6_1kb.addr0 == faultaddr[1]+5) ||
	    (num_fault > 2 && u_top.u_sram6_1kb.addr0 == faultaddr[2]+5) ||
	    (num_fault > 3 && u_top.u_sram6_1kb.addr0 == faultaddr[3]+5) ||
	    (num_fault > 4 && u_top.u_sram6_1kb.addr0 == faultaddr[4]+5) ||
	    (num_fault > 5 && u_top.u_sram6_1kb.addr0 == faultaddr[5]+5) ||
	    (num_fault > 6 && u_top.u_sram6_1kb.addr0 == faultaddr[6]+5) ||
	    (num_fault > 7 && u_top.u_sram6_1kb.addr0 == faultaddr[7]+5)))
             begin
	   if(fault_type == 0)
	      force u_top.u_sram6_1kb.din0 = u_top.mem6_din_b  & 32'hFFFF_FFFE;
	   else
	      force u_top.u_sram6_1kb.din0 = u_top.mem6_din_b | 32'h1;
   	   -> error_insert;
         end else begin
            release u_top.u_sram6_1kb.din0;
         end

         if(u_top.u_sram7_1kb.web0 == 1'b0 && 
	   ((num_fault > 0 && u_top.u_sram7_1kb.addr0 == faultaddr[0]+6) ||
	    (num_fault > 1 && u_top.u_sram7_1kb.addr0 == faultaddr[1]+6) ||
	    (num_fault > 2 && u_top.u_sram7_1kb.addr0 == faultaddr[2]+6) ||
	    (num_fault > 3 && u_top.u_sram7_1kb.addr0 == faultaddr[3]+6) ||
	    (num_fault > 4 && u_top.u_sram7_1kb.addr0 == faultaddr[4]+6) ||
	    (num_fault > 5 && u_top.u_sram7_1kb.addr0 == faultaddr[5]+6) ||
	    (num_fault > 6 && u_top.u_sram7_1kb.addr0 == faultaddr[6]+6) ||
	    (num_fault > 7 && u_top.u_sram7_1kb.addr0 == faultaddr[7]+6)))
             begin
	   if(fault_type == 0)
	      force u_top.u_sram7_1kb.din0 = u_top.mem7_din_b  & 32'hFFFF_FFFE;
	   else
	      force u_top.u_sram7_1kb.din0 = u_top.mem7_din_b | 32'h1;
   	   -> error_insert;
         end else begin
            release u_top.u_sram7_1kb.din0;
         end

         if(u_top.u_sram8_1kb.web0 == 1'b0 && 
	   ((num_fault > 0 && u_top.u_sram8_1kb.addr0 == faultaddr[0]+7) ||
	    (num_fault > 1 && u_top.u_sram8_1kb.addr0 == faultaddr[1]+7) ||
	    (num_fault > 2 && u_top.u_sram8_1kb.addr0 == faultaddr[2]+7) ||
	    (num_fault > 3 && u_top.u_sram8_1kb.addr0 == faultaddr[3]+7) ||
	    (num_fault > 4 && u_top.u_sram8_1kb.addr0 == faultaddr[4]+7) ||
	    (num_fault > 5 && u_top.u_sram8_1kb.addr0 == faultaddr[5]+7) ||
	    (num_fault > 6 && u_top.u_sram8_1kb.addr0 == faultaddr[6]+7) ||
	    (num_fault > 7 && u_top.u_sram8_1kb.addr0 == faultaddr[7]+7)))
             begin
	   if(fault_type == 0)
	      force u_top.u_sram8_1kb.din0 = u_top.mem8_din_b  & 32'hFFFF_FFFE;
	   else
	      force u_top.u_sram8_1kb.din0 = u_top.mem8_din_b | 32'h1;
   	   -> error_insert;
         end else begin
            release u_top.u_sram8_1kb.din0;
         end

      end
   end
   begin

      repeat (200000) @(posedge clock);

      test_fail = 1;
   end
   join_any
   disable fork;


   for(j=0; j < 8; j=j+1) begin
      fail_addr1 = faultaddr[0]+j;
      fail_addr2 = faultaddr[1]+j;
      fail_addr3 = faultaddr[2]+j;
      fail_addr4 = faultaddr[3]+j;


      wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_BIST_CTRL1,j); 
      if(num_fault == 1)
          wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_BIST_SRDATA,read_data,{16'h0,7'h0,fail_addr1},32'h0000_FFFF);
      if(num_fault == 2)
          wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_BIST_SRDATA,read_data,{7'h0,fail_addr2,7'h0,fail_addr1},32'hFFFF_FFFF);
      if(num_fault == 3) begin
          wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_BIST_SRDATA,read_data,{7'h0,fail_addr2,7'h0,fail_addr1},32'hFFFF_FFFF);
          wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_BIST_SRDATA,read_data,{16'h0,7'h0,fail_addr3},32'h0000_FFFF);
      end
      if(num_fault >= 4) begin
          wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_BIST_SRDATA,read_data,{7'h0,fail_addr2,7'h0,fail_addr1},32'hFFFF_FFFF);
          wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_BIST_SRDATA,read_data,{7'h0,faultaddr[3]+j,7'h0,fail_addr3},32'hFFFF_FFFF);
      end
   end
end
endtask


task wb_user_core_write;
input [31:0] address;
input [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h1;
  wbd_ext_dat_i =data;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  $display("STATUS: WB USER ACCESS WRITE Address : 0x%x, Data : 0x%x",address,data);
  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read;
input [31:0] address;
output [31:0] data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  #1;
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;

  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read_check;
input [31:0] address;
output [31:0] data;
input [31:0] cmp_data;
input [31:0] cmp_mask;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  #1;
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  if((data & cmp_mask) !== (cmp_data & cmp_mask) ) begin
     $display("ERROR : WB USER ACCESS READ  Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,(cmp_data & cmp_mask),(data & cmp_mask));
     test_fail = 1;
  end else begin
     $display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,(data & cmp_mask));
  end
  repeat (2) @(posedge clock);
end
endtask


endmodule
module user_mbist_test1_tb;

	reg clock;
	reg wb_rst_i;
	reg power1, power2;
	reg power3, power4;

        reg        wbd_ext_cyc_i;
        reg        wbd_ext_stb_i;
        reg [31:0] wbd_ext_adr_i;
        reg        wbd_ext_we_i;
        reg [31:0] wbd_ext_dat_i;
        reg [3:0]  wbd_ext_sel_i;

        wire [31:0] wbd_ext_dat_o;
        wire        wbd_ext_ack_o;
        wire        wbd_ext_err_o;


	wire [37:0] io_oeb;
	wire [37:0] io_out;
	wire [37:0] io_in;

	wire gpio;
	wire [37:0] mprj_io;
	wire [7:0] mprj_io_0;
	reg        test_fail;
	reg [31:0] read_data;
        reg [31:0] writemem [0:511];
        reg [8:0]  faultaddr [0:7];
        integer i;
        event      error_insert;






	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
                wbd_ext_cyc_i ='h0;
                wbd_ext_stb_i ='h0;
                wbd_ext_adr_i ='h0;
                wbd_ext_we_i  ='h0;
                wbd_ext_dat_i ='h0;
                wbd_ext_sel_i ='h0;
	end

	`ifdef WFDUMP
	   initial begin
	   	$dumpfile("simx.vcd");
	   	$dumpvars(5, user_mbist_test1_tb);
		$dumpoff;
	   end
       `endif

	initial begin
		wb_rst_i <= 1'b1;
		#100;
		wb_rst_i <= 1'b0;

		#200;
	        repeat (10) @(posedge clock);
		$display("Monitor: Standalone User Test Started");

		test_fail = 0;

		wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);

		$dumpoff;
	    	$display("###################################################");
	    	$display(" MBIST Test with Without Address Failure");
	    	$display("###################################################");







		insert_fault(0,0,64'h01010101_01010101);

          	if(test_fail == 0) begin
	    	    $display("Monitor: Step-1: BIST Test without any Memory Error insertion test Passed");
	        end else begin
	    	    $display("Monitor: Step-1: BIST Test without any Memory Error insertion test Failed");
		end
		$dumpon;
	    	$display("###################################################");
	    	$display(" MBIST Test with Single Address Failure");
	    	$display("###################################################");







		faultaddr[0] = 9'h10;
		insert_fault(1,1,64'h15151515_15151515);

          	if(test_fail == 0) begin
	    	    $display("Monitor: Step-2: BIST Test with One Memory Error insertion test Passed");
	        end else begin
	    	    $display("Monitor: Step-2: BIST Test with One Memory Error insertion test Failed");
		 end
	    	$display("###################################################");
		$dumpoff;
	    	$display("###################################################");
	    	$display(" MBIST Test with Two Address Failure");
	    	$display("###################################################");







		faultaddr[0] = 9'h10;
		faultaddr[1] = 9'h20;
		insert_fault(2,0,64'h25252525_25252525);

          	if(test_fail == 0) begin
	    	    $display("Monitor: Step-3: BIST Test with Two Memory Error insertion test Passed");
	        end else begin
	    	    $display("Monitor: Step-3: BIST Test with Two Memory Error insertion test Failed");
		 end
	    	$display("###################################################");
	    	$display(" MBIST Test with Three Address Failure");
	    	$display("###################################################");








		faultaddr[0] = 9'h10;
		faultaddr[1] = 9'h20;
		faultaddr[2] = 9'h30;
		insert_fault(3,1,64'h35353535_35353535);

          	if(test_fail == 0) begin
	    	    $display("Monitor: Step-4: BIST Test with Three Memory Error insertion test Passed");
	        end else begin
	    	    $display("Monitor: Step-4: BIST Test with Three Memory Error insertion test Failed");
		 end
                $dumpoff;
	    	$display("###################################################");
	    	$display(" MBIST Test with Fours Address Failure");
	    	$display("###################################################");







		faultaddr[0] = 9'h10;
		faultaddr[1] = 9'h20;
		faultaddr[2] = 9'h30;
		faultaddr[3] = 9'h40;
		insert_fault(4,0,64'h45454545_45454545);

          	if(test_fail == 0) begin
	    	    $display("Monitor: Step-5: BIST Test with Four Memory Error insertion test Passed");
	        end else begin
	    	    $display("Monitor: Step-5: BIST Test with Four Memory Error insertion test Failed");
		end

		$dumpon;
	    	$display("###################################################");
	    	$display(" MBIST Test with Fours Address(Continous Starting Addrsess) Failure");
	    	$display("###################################################");







		faultaddr[0] = 9'h0;
		faultaddr[1] = 9'h1;
		faultaddr[2] = 9'h2;
		faultaddr[3] = 9'h3;
		insert_fault(4,0,64'h45454545_45454545);

          	if(test_fail == 0) begin
	    	    $display("Monitor: Step-5.2: BIST Test with Four Memory Error insertion test Passed");
	        end else begin
	    	    $display("Monitor: Step-5.2: BIST Test with Four Memory Error insertion test Failed");
		end

	    	$display("###################################################");
	    	$display(" MBIST Test with Fours Address(Last Addrsess) Failure");
	    	$display("###################################################");







		faultaddr[0] = 9'hF0;
		faultaddr[1] = 9'hF1;
		faultaddr[2] = 9'hF2;
		faultaddr[3] = 9'hF3;
		insert_fault(4,0,64'h45454545_45454545);

          	if(test_fail == 0) begin
	    	    $display("Monitor: Step-5.3: BIST Test with Four Memory Error insertion test Passed");
	        end else begin
	    	    $display("Monitor: Step-5.3: BIST Test with Four Memory Error insertion test Failed");
		end
		$dumpon;
	    	$display("###################################################");
	    	$display(" MBIST Test with Five Address Failure");
	    	$display("###################################################");







		faultaddr[0] = 9'h10;
		faultaddr[1] = 9'h20;
		faultaddr[2] = 9'h30;
		faultaddr[3] = 9'h40;
		faultaddr[4] = 9'h50;
		insert_fault(5,1,64'h47474747_47474747);

          	if(test_fail == 0) begin
	    	    $display("Monitor: Step-5: BIST Test with Five Memory Error insertion test Passed");
	        end else begin
	    	    $display("Monitor: Step-5: BIST Test with Five Memory Error insertion test Failed");
		 end

		$dumpon;
	    	$display("###################################################");
	    	$display(" MBIST Test with Functional Access, continuation of previous MBIST Signature");
	    	$display("###################################################");
		$dumpon;
		fork
		begin

                    wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_BIST_CTRL2,'h000);
  

		    for (i=0; i< 9'h1FC; i=i+1) begin
   	                writemem[i] = $random;
                        wb_user_core_write(`ADDR_SPACE_MBIST1+(i*4),writemem[i]);
                        wb_user_core_write(`ADDR_SPACE_MBIST2+(i*4),writemem[i]);
                        wb_user_core_write(`ADDR_SPACE_MBIST3+(i*4),writemem[i]);
                        wb_user_core_write(`ADDR_SPACE_MBIST4+(i*4),writemem[i]);
		        if(i < 9'h0FC) begin
                           wb_user_core_write(`ADDR_SPACE_MBIST5+(i*4),writemem[i]);
                           wb_user_core_write(`ADDR_SPACE_MBIST6+(i*4),writemem[i]);
                           wb_user_core_write(`ADDR_SPACE_MBIST7+(i*4),writemem[i]);
                           wb_user_core_write(`ADDR_SPACE_MBIST8+(i*4),writemem[i]);
	                end
		    end

		    for (i=0; i< 9'h1FC; i=i+1) begin
                        wb_user_core_read_check(`ADDR_SPACE_MBIST1+(i*4),read_data,writemem[i],32'hFFFFFFFF);
                        wb_user_core_read_check(`ADDR_SPACE_MBIST2+(i*4),read_data,writemem[i],32'hFFFFFFFF);
                        wb_user_core_read_check(`ADDR_SPACE_MBIST3+(i*4),read_data,writemem[i],32'hFFFFFFFF);
                        wb_user_core_read_check(`ADDR_SPACE_MBIST4+(i*4),read_data,writemem[i],32'hFFFFFFFF);
		        if(i < 9'h0FC) begin
                           wb_user_core_read_check(`ADDR_SPACE_MBIST5+(i*4),read_data,writemem[i],32'hFFFFFFFF);
                           wb_user_core_read_check(`ADDR_SPACE_MBIST6+(i*4),read_data,writemem[i],32'hFFFFFFFF);
                           wb_user_core_read_check(`ADDR_SPACE_MBIST7+(i*4),read_data,writemem[i],32'hFFFFFFFF);
                           wb_user_core_read_check(`ADDR_SPACE_MBIST8+(i*4),read_data,writemem[i],32'hFFFFFFFF);
	                end
		    end






                    wb_user_core_read_check(`ADDR_SPACE_MBIST1 + (9'h1FC *4),read_data,writemem[9'h10],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST1 + (9'h1FD *4),read_data,writemem[9'h20],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST1 + (9'h1FE *4),read_data,writemem[9'h30],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST1 + (9'h1FF *4),read_data,writemem[9'h40],32'hFFFFFFFF);


                    wb_user_core_read_check(`ADDR_SPACE_MBIST2 + (9'h1FC *4),read_data,writemem[9'h11],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST2 + (9'h1FD *4),read_data,writemem[9'h21],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST2 + (9'h1FE *4),read_data,writemem[9'h31],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST2 + (9'h1FF *4),read_data,writemem[9'h41],32'hFFFFFFFF);


                    wb_user_core_read_check(`ADDR_SPACE_MBIST3 + (9'h1FC *4),read_data,writemem[9'h12],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST3 + (9'h1FD *4),read_data,writemem[9'h22],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST3 + (9'h1FE *4),read_data,writemem[9'h32],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST3 + (9'h1FF *4),read_data,writemem[9'h42],32'hFFFFFFFF);


                    wb_user_core_read_check(`ADDR_SPACE_MBIST4 + (9'h1FC *4),read_data,writemem[9'h13],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST4 + (9'h1FD *4),read_data,writemem[9'h23],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST4 + (9'h1FE *4),read_data,writemem[9'h33],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST4 + (9'h1FF *4),read_data,writemem[9'h43],32'hFFFFFFFF);


                    wb_user_core_read_check(`ADDR_SPACE_MBIST5 + (8'hFC *4),read_data,writemem[9'h14],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST5 + (8'hFD *4),read_data,writemem[9'h24],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST5 + (8'hFE *4),read_data,writemem[9'h34],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST5 + (8'hFF *4),read_data,writemem[9'h44],32'hFFFFFFFF);


                    wb_user_core_read_check(`ADDR_SPACE_MBIST6 + (8'hFC *4),read_data,writemem[9'h15],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST6 + (8'hFD *4),read_data,writemem[9'h25],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST6 + (8'hFE *4),read_data,writemem[9'h35],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST6 + (8'hFF *4),read_data,writemem[9'h45],32'hFFFFFFFF);


                    wb_user_core_read_check(`ADDR_SPACE_MBIST7 + (8'hFC *4),read_data,writemem[9'h16],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST7 + (8'hFD *4),read_data,writemem[9'h26],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST7 + (8'hFE *4),read_data,writemem[9'h36],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST7 + (8'hFF *4),read_data,writemem[9'h46],32'hFFFFFFFF);


                    wb_user_core_read_check(`ADDR_SPACE_MBIST8 + (8'hFC *4),read_data,writemem[9'h17],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST8 + (8'hFD *4),read_data,writemem[9'h27],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST8 + (8'hFE *4),read_data,writemem[9'h37],32'hFFFFFFFF);
                    wb_user_core_read_check(`ADDR_SPACE_MBIST8 + (8'hFF *4),read_data,writemem[9'h47],32'hFFFFFFFF);
                end
                begin

                   repeat (200000) @(posedge clock);

                   test_fail = 1;
                end
                join_any
                disable fork;
          	if(test_fail == 0) begin
	    	    $display("Monitor: Step-5: BIST Test with Functional access test Passed");
	        end else begin
	    	    $display("Monitor: Step-5: BIST Test with Functional access test failed");
		 end

	    	$display("###################################################");
	        $finish;
	end

wire USER_VDD1V8 = 1'b1;
wire VSS = 1'b0;


user_project_wrapper u_top(
`ifdef USE_POWER_PINS
    .vccd1(USER_VDD1V8),
    .vssd1(VSS),
`endif
    .wb_clk_i        (clock),
    .user_clock2     (1'b1),
    .wb_rst_i        (wb_rst_i),

    .wbs_cyc_i   (wbd_ext_cyc_i),
    .wbs_stb_i   (wbd_ext_stb_i),
    .wbs_adr_i   (wbd_ext_adr_i),
    .wbs_we_i    (wbd_ext_we_i),
    .wbs_dat_i   (wbd_ext_dat_i),
    .wbs_sel_i   (wbd_ext_sel_i),

    .wbs_dat_o   (wbd_ext_dat_o),
    .wbs_ack_o   (wbd_ext_ack_o),

 

    .la_data_in      ('1) ,
    .la_data_out     (),
    .la_oenb         ('0),
 


    .io_in          (io_in)  ,
    .io_out         (io_out) ,
    .io_oeb         (io_oeb) ,

    .user_irq       () 

);

`ifndef GL

    initial begin


    end
`endif    






task insert_fault;
input [3:0]  num_fault;
input        fault_type;
input [63:0]  mbist_signature;
reg [31:0] datain;
reg [8:0]  fail_addr1;
reg [8:0]  fail_addr2;
reg [8:0]  fail_addr3;
reg [8:0]  fail_addr4;
integer j;
begin
   repeat (2) @(posedge clock);

   wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_BIST_CTRL2,'h000);

   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h001);

   wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_BIST_CTRL2,'h33333333);

   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h003);
   fork
   begin

      read_data = 'h0;
      while (read_data[0] != 1'b1) begin
         wb_user_core_read(`ADDR_SPACE_GLBL+`GLBL_BIST_STAT1,read_data);
      end

      repeat (1000) @(posedge clock);






      wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_BIST_STAT1,read_data,mbist_signature[31:0],32'hFFFFFFFF);
      wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_BIST_STAT2,read_data,mbist_signature[63:32],32'hFFFFFFFF);
   end

   begin
      while(1) begin
         repeat (1) @(posedge clock);
         #1;

         if(u_top.u_sram1_2kb.web0 == 1'b0 && 
	   ((num_fault > 0 && u_top.u_sram1_2kb.addr0 == faultaddr[0]) ||
	    (num_fault > 1 && u_top.u_sram1_2kb.addr0 == faultaddr[1]) ||
	    (num_fault > 2 && u_top.u_sram1_2kb.addr0 == faultaddr[2]) ||
	    (num_fault > 3 && u_top.u_sram1_2kb.addr0 == faultaddr[3]) ||
	    (num_fault > 4 && u_top.u_sram1_2kb.addr0 == faultaddr[4]) ||
	    (num_fault > 5 && u_top.u_sram1_2kb.addr0 == faultaddr[5]) ||
	    (num_fault > 6 && u_top.u_sram1_2kb.addr0 == faultaddr[6]) ||
	    (num_fault > 7 && u_top.u_sram1_2kb.addr0 == faultaddr[7])))
             begin
	   if(fault_type == 0)
	      force u_top.u_sram1_2kb.din0 = u_top.mem1_din_b  & 32'hFFFF_FFFE;
	   else
	      force u_top.u_sram1_2kb.din0 = u_top.mem1_din_b | 32'h1;
   	   -> error_insert;
         end else begin
            release u_top.u_sram1_2kb.din0;
         end

         if(u_top.u_sram2_2kb.web0 == 1'b0 && 
	   ((num_fault > 0 && u_top.u_sram2_2kb.addr0 == faultaddr[0]+1) ||
	    (num_fault > 1 && u_top.u_sram2_2kb.addr0 == faultaddr[1]+1) ||
	    (num_fault > 2 && u_top.u_sram2_2kb.addr0 == faultaddr[2]+1) ||
	    (num_fault > 3 && u_top.u_sram2_2kb.addr0 == faultaddr[3]+1) ||
	    (num_fault > 4 && u_top.u_sram2_2kb.addr0 == faultaddr[4]+1) ||
	    (num_fault > 5 && u_top.u_sram2_2kb.addr0 == faultaddr[5]+1) ||
	    (num_fault > 6 && u_top.u_sram2_2kb.addr0 == faultaddr[6]+1) ||
	    (num_fault > 7 && u_top.u_sram2_2kb.addr0 == faultaddr[7]+1)))
             begin
	   if(fault_type == 0)
	      force u_top.u_sram2_2kb.din0 = u_top.mem2_din_b  & 32'hFFFF_FFFE;
	   else
	      force u_top.u_sram2_2kb.din0 = u_top.mem2_din_b | 32'h1;
   	   -> error_insert;
         end else begin
            release u_top.u_sram2_2kb.din0;
         end

         if(u_top.u_sram3_2kb.web0 == 1'b0 && 
	   ((num_fault > 0 && u_top.u_sram3_2kb.addr0 == faultaddr[0]+2) ||
	    (num_fault > 1 && u_top.u_sram3_2kb.addr0 == faultaddr[1]+2) ||
	    (num_fault > 2 && u_top.u_sram3_2kb.addr0 == faultaddr[2]+2) ||
	    (num_fault > 3 && u_top.u_sram3_2kb.addr0 == faultaddr[3]+2) ||
	    (num_fault > 4 && u_top.u_sram3_2kb.addr0 == faultaddr[4]+2) ||
	    (num_fault > 5 && u_top.u_sram3_2kb.addr0 == faultaddr[5]+2) ||
	    (num_fault > 6 && u_top.u_sram3_2kb.addr0 == faultaddr[6]+2) ||
	    (num_fault > 7 && u_top.u_sram3_2kb.addr0 == faultaddr[7]+2)))
             begin
	   if(fault_type == 0)
	      force u_top.u_sram3_2kb.din0 = u_top.mem3_din_b  & 32'hFFFF_FFFE;
	   else
	      force u_top.u_sram3_2kb.din0 = u_top.mem3_din_b | 32'h1;
   	   -> error_insert;
         end else begin
            release u_top.u_sram3_2kb.din0;
         end

         if(u_top.u_sram4_2kb.web0 == 1'b0 && 
	   ((num_fault > 0 && u_top.u_sram4_2kb.addr0 == faultaddr[0]+3) ||
	    (num_fault > 1 && u_top.u_sram4_2kb.addr0 == faultaddr[1]+3) ||
	    (num_fault > 2 && u_top.u_sram4_2kb.addr0 == faultaddr[2]+3) ||
	    (num_fault > 3 && u_top.u_sram4_2kb.addr0 == faultaddr[3]+3) ||
	    (num_fault > 4 && u_top.u_sram4_2kb.addr0 == faultaddr[4]+3) ||
	    (num_fault > 5 && u_top.u_sram4_2kb.addr0 == faultaddr[5]+3) ||
	    (num_fault > 6 && u_top.u_sram4_2kb.addr0 == faultaddr[6]+3) ||
	    (num_fault > 7 && u_top.u_sram4_2kb.addr0 == faultaddr[7]+3)))
             begin
	   if(fault_type == 0)
	      force u_top.u_sram4_2kb.din0 = u_top.mem4_din_b  & 32'hFFFF_FFFE;
	   else
	      force u_top.u_sram4_2kb.din0 = u_top.mem4_din_b | 32'h1;
   	   -> error_insert;
         end else begin
            release u_top.u_sram4_2kb.din0;
         end

         if(u_top.u_sram5_1kb.web0 == 1'b0 && 
	   ((num_fault > 0 && u_top.u_sram5_1kb.addr0 == faultaddr[0]+4) ||
	    (num_fault > 1 && u_top.u_sram5_1kb.addr0 == faultaddr[1]+4) ||
	    (num_fault > 2 && u_top.u_sram5_1kb.addr0 == faultaddr[2]+4) ||
	    (num_fault > 3 && u_top.u_sram5_1kb.addr0 == faultaddr[3]+4) ||
	    (num_fault > 4 && u_top.u_sram5_1kb.addr0 == faultaddr[4]+4) ||
	    (num_fault > 5 && u_top.u_sram5_1kb.addr0 == faultaddr[5]+4) ||
	    (num_fault > 6 && u_top.u_sram5_1kb.addr0 == faultaddr[6]+4) ||
	    (num_fault > 7 && u_top.u_sram5_1kb.addr0 == faultaddr[7]+4)))
             begin
	   if(fault_type == 0)
	      force u_top.u_sram5_1kb.din0 = u_top.mem5_din_b  & 32'hFFFF_FFFE;
	   else
	      force u_top.u_sram5_1kb.din0 = u_top.mem5_din_b | 32'h1;
   	   -> error_insert;
         end else begin
            release u_top.u_sram5_1kb.din0;
         end

         if(u_top.u_sram6_1kb.web0 == 1'b0 && 
	   ((num_fault > 0 && u_top.u_sram6_1kb.addr0 == faultaddr[0]+5) ||
	    (num_fault > 1 && u_top.u_sram6_1kb.addr0 == faultaddr[1]+5) ||
	    (num_fault > 2 && u_top.u_sram6_1kb.addr0 == faultaddr[2]+5) ||
	    (num_fault > 3 && u_top.u_sram6_1kb.addr0 == faultaddr[3]+5) ||
	    (num_fault > 4 && u_top.u_sram6_1kb.addr0 == faultaddr[4]+5) ||
	    (num_fault > 5 && u_top.u_sram6_1kb.addr0 == faultaddr[5]+5) ||
	    (num_fault > 6 && u_top.u_sram6_1kb.addr0 == faultaddr[6]+5) ||
	    (num_fault > 7 && u_top.u_sram6_1kb.addr0 == faultaddr[7]+5)))
             begin
	   if(fault_type == 0)
	      force u_top.u_sram6_1kb.din0 = u_top.mem6_din_b  & 32'hFFFF_FFFE;
	   else
	      force u_top.u_sram6_1kb.din0 = u_top.mem6_din_b | 32'h1;
   	   -> error_insert;
         end else begin
            release u_top.u_sram6_1kb.din0;
         end

         if(u_top.u_sram7_1kb.web0 == 1'b0 && 
	   ((num_fault > 0 && u_top.u_sram7_1kb.addr0 == faultaddr[0]+6) ||
	    (num_fault > 1 && u_top.u_sram7_1kb.addr0 == faultaddr[1]+6) ||
	    (num_fault > 2 && u_top.u_sram7_1kb.addr0 == faultaddr[2]+6) ||
	    (num_fault > 3 && u_top.u_sram7_1kb.addr0 == faultaddr[3]+6) ||
	    (num_fault > 4 && u_top.u_sram7_1kb.addr0 == faultaddr[4]+6) ||
	    (num_fault > 5 && u_top.u_sram7_1kb.addr0 == faultaddr[5]+6) ||
	    (num_fault > 6 && u_top.u_sram7_1kb.addr0 == faultaddr[6]+6) ||
	    (num_fault > 7 && u_top.u_sram7_1kb.addr0 == faultaddr[7]+6)))
             begin
	   if(fault_type == 0)
	      force u_top.u_sram7_1kb.din0 = u_top.mem7_din_b  & 32'hFFFF_FFFE;
	   else
	      force u_top.u_sram7_1kb.din0 = u_top.mem7_din_b | 32'h1;
   	   -> error_insert;
         end else begin
            release u_top.u_sram7_1kb.din0;
         end

         if(u_top.u_sram8_1kb.web0 == 1'b0 && 
	   ((num_fault > 0 && u_top.u_sram8_1kb.addr0 == faultaddr[0]+7) ||
	    (num_fault > 1 && u_top.u_sram8_1kb.addr0 == faultaddr[1]+7) ||
	    (num_fault > 2 && u_top.u_sram8_1kb.addr0 == faultaddr[2]+7) ||
	    (num_fault > 3 && u_top.u_sram8_1kb.addr0 == faultaddr[3]+7) ||
	    (num_fault > 4 && u_top.u_sram8_1kb.addr0 == faultaddr[4]+7) ||
	    (num_fault > 5 && u_top.u_sram8_1kb.addr0 == faultaddr[5]+7) ||
	    (num_fault > 6 && u_top.u_sram8_1kb.addr0 == faultaddr[6]+7) ||
	    (num_fault > 7 && u_top.u_sram8_1kb.addr0 == faultaddr[7]+7)))
             begin
	   if(fault_type == 0)
	      force u_top.u_sram8_1kb.din0 = u_top.mem8_din_b  & 32'hFFFF_FFFE;
	   else
	      force u_top.u_sram8_1kb.din0 = u_top.mem8_din_b | 32'h1;
   	   -> error_insert;
         end else begin
            release u_top.u_sram8_1kb.din0;
         end

      end
   end
   begin

      repeat (200000) @(posedge clock);

      test_fail = 1;
   end
   join_any
   disable fork;


   for(j=0; j < 8; j=j+1) begin
      fail_addr1 = faultaddr[0]+j;
      fail_addr2 = faultaddr[1]+j;
      fail_addr3 = faultaddr[2]+j;
      fail_addr4 = faultaddr[3]+j;


      wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_BIST_CTRL1,j); 
      if(num_fault == 1)
          wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_BIST_SRDATA,read_data,{16'h0,7'h0,fail_addr1},32'h0000_FFFF);
      if(num_fault == 2)
          wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_BIST_SRDATA,read_data,{7'h0,fail_addr2,7'h0,fail_addr1},32'hFFFF_FFFF);
      if(num_fault == 3) begin
          wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_BIST_SRDATA,read_data,{7'h0,fail_addr2,7'h0,fail_addr1},32'hFFFF_FFFF);
          wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_BIST_SRDATA,read_data,{16'h0,7'h0,fail_addr3},32'h0000_FFFF);
      end
      if(num_fault >= 4) begin
          wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_BIST_SRDATA,read_data,{7'h0,fail_addr2,7'h0,fail_addr1},32'hFFFF_FFFF);
          wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_BIST_SRDATA,read_data,{7'h0,faultaddr[3]+j,7'h0,fail_addr3},32'hFFFF_FFFF);
      end
   end
end
endtask


task wb_user_core_write;
input [31:0] address;
input [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h1;
  wbd_ext_dat_i =data;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  $display("STATUS: WB USER ACCESS WRITE Address : 0x%x, Data : 0x%x",address,data);
  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read;
input [31:0] address;
output [31:0] data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  #1;
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;

  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read_check;
input [31:0] address;
output [31:0] data;
input [31:0] cmp_data;
input [31:0] cmp_mask;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  #1;
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  if((data & cmp_mask) !== (cmp_data & cmp_mask) ) begin
     $display("ERROR : WB USER ACCESS READ  Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,(cmp_data & cmp_mask),(data & cmp_mask));
     test_fail = 1;
  end else begin
     $display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,(data & cmp_mask));
  end
  repeat (2) @(posedge clock);
end
endtask


endmodule