data/full_repos/permissive/476411617/BRAM.v
1: b'%Warning-WIDTH: data/full_repos/permissive/476411617/BRAM.v:63: Bit extraction of var[159:0] requires 8 bit index, not 10 bits.\n                                                              : ... In instance BRAM\n      ram[i][addra] = dia[i];\n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/476411617/BRAM.v:68: Bit extraction of var[159:0] requires 8 bit index, not 10 bits.\n                                                              : ... In instance BRAM\n     doa[i] = ram[i][addra];\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/476411617/BRAM.v:76: Bit extraction of var[159:0] requires 8 bit index, not 10 bits.\n                                                              : ... In instance BRAM\n        ram[i][addrb] = dib[i];\n              ^\n%Warning-WIDTH: data/full_repos/permissive/476411617/BRAM.v:80: Bit extraction of var[159:0] requires 8 bit index, not 10 bits.\n                                                              : ... In instance BRAM\n    dob[i] = ram[i][addrb];\n                   ^\n%Error: Exiting due to 4 warning(s)\n'
module BRAM
	(	
		clk,
		reset,
		wea,
		web,
		addra,
		addrb,
		dia,
		dib,
		doa,
		dob

	);
input clk, reset, wea, web;

input [9:0] addra,addrb;
input [15:0] dia, dib;
output reg [15:0] doa,dob;
reg[159:0] ram[15:0] ;
integer i;

always @(posedge clk) 
begin


	



	


		if (wea) begin
		   for(i=0; i<16; i=i+1) begin
			   ram[i][addra] = dia[i];
		   end
		end
		
		for(i=0; i<16; i=i+1) begin
		   doa[i] = ram[i][addra];
		end

end
always @(posedge clk) 
begin  
	if (web) begin
	   for(i=0; i<16; i=i+1) begin
	       ram[i][addrb] = dib[i];
	   end
	end
    for(i=0; i<16; i=i+1) begin
	   dob[i] = ram[i][addrb];
	end 
end

endmodule
module BRAM
	(	
		clk,
		reset,
		wea,
		web,
		addra,
		addrb,
		dia,
		dib,
		doa,
		dob

	);

input clk, reset, wea, web;

input [9:0] addra,addrb;
input [15:0] dia, dib;
output reg [15:0] doa,dob;
reg[159:0] ram[15:0] ;
integer i;

always @(posedge clk) 
begin


	



	


		if (wea) begin
		   for(i=0; i<16; i=i+1) begin
			   ram[i][addra] = dia[i];
		   end
		end
		
		for(i=0; i<16; i=i+1) begin
		   doa[i] = ram[i][addra];
		end

end
always @(posedge clk) 
begin  
	if (web) begin
	   for(i=0; i<16; i=i+1) begin
	       ram[i][addrb] = dib[i];
	   end
	end
    for(i=0; i<16; i=i+1) begin
	   dob[i] = ram[i][addrb];
	end 
end

endmodule