data/full_repos/permissive/482974522/TimeMultiplexed_FIR.srcs/sim_1/new/tb_TimeMultiplexedFIR.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/482974522/TimeMultiplexed_FIR.srcs/sim_1/new/tb_TimeMultiplexedFIR.v:33: Unsupported: Ignoring delay on this delayed statement.\n    always #(ClockPeriod/2) CLK = ~CLK;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/482974522/TimeMultiplexed_FIR.srcs/sim_1/new/tb_TimeMultiplexedFIR.v:37: Unsupported: $fopen with multichannel descriptor.  Add ,"w" as second argument to open a file descriptor.\n        c = $fopen("TimeMultiplexedFIR.txt");\n            ^~~~~~\n%Error: data/full_repos/permissive/482974522/TimeMultiplexed_FIR.srcs/sim_1/new/tb_TimeMultiplexedFIR.v:47: syntax error, unexpected \'@\'\n        @(posedge CLK) x <= 8\'b00000000; muxSel = \'b00; topRegister = 1\'b1;\n        ^\n%Error: data/full_repos/permissive/482974522/TimeMultiplexed_FIR.srcs/sim_1/new/tb_TimeMultiplexedFIR.v:48: syntax error, unexpected \'@\'\n        @(posedge CLK) x <= 8\'b00000000; muxSel = \'b00; \n        ^\n%Error: data/full_repos/permissive/482974522/TimeMultiplexed_FIR.srcs/sim_1/new/tb_TimeMultiplexedFIR.v:49: syntax error, unexpected \'@\'\n        @(posedge CLK) x <= 8\'b00000000; muxSel = \'b00; \n        ^\n%Error: data/full_repos/permissive/482974522/TimeMultiplexed_FIR.srcs/sim_1/new/tb_TimeMultiplexedFIR.v:51: syntax error, unexpected \'@\'\n        @(posedge CLK) x <= inputsList[0]; muxSel = \'b00; RST = 1\'b0;\n        ^\n%Error: data/full_repos/permissive/482974522/TimeMultiplexed_FIR.srcs/sim_1/new/tb_TimeMultiplexedFIR.v:54: syntax error, unexpected \'@\'\n        @(posedge CLK) muxSel = \'b01; \n        ^\n%Error: data/full_repos/permissive/482974522/TimeMultiplexed_FIR.srcs/sim_1/new/tb_TimeMultiplexedFIR.v:56: syntax error, unexpected \'@\'\n        @(posedge CLK) topRegister = 1\'b1; $fwrite(c,"%b\\n",y);\n        ^\n%Error: data/full_repos/permissive/482974522/TimeMultiplexed_FIR.srcs/sim_1/new/tb_TimeMultiplexedFIR.v:61: syntax error, unexpected \'@\'\n        @(posedge CLK) x <= inputsList[1]; muxSel = \'b00; RST = 1\'b0;\n        ^\n%Error: data/full_repos/permissive/482974522/TimeMultiplexed_FIR.srcs/sim_1/new/tb_TimeMultiplexedFIR.v:64: syntax error, unexpected \'@\'\n        @(posedge CLK) muxSel = \'b01; \n        ^\n%Error: data/full_repos/permissive/482974522/TimeMultiplexed_FIR.srcs/sim_1/new/tb_TimeMultiplexedFIR.v:66: syntax error, unexpected \'@\'\n        @(posedge CLK) topRegister = 1\'b1; $fwrite(c,"%b\\n",y);\n        ^\n%Error: data/full_repos/permissive/482974522/TimeMultiplexed_FIR.srcs/sim_1/new/tb_TimeMultiplexedFIR.v:71: syntax error, unexpected \'@\'\n        @(posedge CLK) x <= inputsList[2]; muxSel = \'b00; RST = 1\'b0;\n        ^\n%Error: data/full_repos/permissive/482974522/TimeMultiplexed_FIR.srcs/sim_1/new/tb_TimeMultiplexedFIR.v:74: syntax error, unexpected \'@\'\n        @(posedge CLK) muxSel = \'b01; \n        ^\n%Error: data/full_repos/permissive/482974522/TimeMultiplexed_FIR.srcs/sim_1/new/tb_TimeMultiplexedFIR.v:76: syntax error, unexpected \'@\'\n        @(posedge CLK) topRegister = 1\'b1; $fwrite(c,"%b\\n",y);\n        ^\n%Error: data/full_repos/permissive/482974522/TimeMultiplexed_FIR.srcs/sim_1/new/tb_TimeMultiplexedFIR.v:81: syntax error, unexpected \'@\'\n        @(posedge CLK) x <= inputsList[3]; muxSel = \'b00; RST = 1\'b0;\n        ^\n%Error: data/full_repos/permissive/482974522/TimeMultiplexed_FIR.srcs/sim_1/new/tb_TimeMultiplexedFIR.v:84: syntax error, unexpected \'@\'\n        @(posedge CLK) muxSel = \'b01; \n        ^\n%Error: data/full_repos/permissive/482974522/TimeMultiplexed_FIR.srcs/sim_1/new/tb_TimeMultiplexedFIR.v:86: syntax error, unexpected \'@\'\n        @(posedge CLK) topRegister = 1\'b1; $fwrite(c,"%b\\n",y);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/482974522/TimeMultiplexed_FIR.srcs/sim_1/new/tb_TimeMultiplexedFIR.v:91: Unsupported: Ignoring delay on this delayed statement.\n        #(ClockPeriod *6) $fclose(c); $finish;\n        ^\n%Error: Exiting due to 16 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_TimeMultiplexed_FIR;
    parameter WI = 2, WF = 6;
    reg CLK, RST;
    reg topRegister, bottomRegister, outputRegister;
    reg [1:0] muxSel;
    reg signed [(WI+WF)-1:0] x, h0, h1, h2;
    wire signed [(WI+WF)-1:0] y;

    TimeMultiplexed_FIR #(.WI(WI),.WF(WF)) DUT (.CLK(CLK),.RST(RST),.topRegister(topRegister),.bottomRegister(bottomRegister),.outputRegister(outputRegister),.muxSel(muxSel),.x(x),.h0(h0),.h1(h1),.h2(h2),.y(y));
    
    parameter ClockPeriod = 10;
    initial CLK = 0;
    always #(ClockPeriod/2) CLK = ~CLK;
    
    integer c;
    initial begin
        c = $fopen("TimeMultiplexedFIR.txt");
    end
    reg [7:0] inputsList [3:0];
    reg [7:0] coeff [2:0];
    
    initial begin
        $readmemb("inputX.mem", inputsList);
        $readmemb("coeff.mem", coeff);
        h0 <= coeff[0]; h1 <= coeff[1]; h2 <= coeff[2]; RST = 1'b1;
        x <= 8'b00000000;
        @(posedge CLK) x <= 8'b00000000; muxSel = 'b00; topRegister = 1'b1;
        @(posedge CLK) x <= 8'b00000000; muxSel = 'b00; 
        @(posedge CLK) x <= 8'b00000000; muxSel = 'b00; 
        
        @(posedge CLK) x <= inputsList[0]; muxSel = 'b00; RST = 1'b0;
        topRegister = 1'b0;
        bottomRegister = 1'b1;
        @(posedge CLK) muxSel = 'b01; 
        @(posedge CLK) muxSel = 'b10; outputRegister = 1'b1; 
        @(posedge CLK) topRegister = 1'b1; $fwrite(c,"%b\n",y);
        bottomRegister = 1'b1;
        outputRegister = 1'b0;
        RST = 1'b1;
        
        @(posedge CLK) x <= inputsList[1]; muxSel = 'b00; RST = 1'b0;
        topRegister = 1'b0;
        bottomRegister = 1'b1;
        @(posedge CLK) muxSel = 'b01; 
        @(posedge CLK) muxSel = 'b10; outputRegister = 1'b1;
        @(posedge CLK) topRegister = 1'b1; $fwrite(c,"%b\n",y);
        bottomRegister = 1'b1;
        outputRegister = 1'b0;
        RST = 1'b1;
        
        @(posedge CLK) x <= inputsList[2]; muxSel = 'b00; RST = 1'b0;
        topRegister = 1'b0;
        bottomRegister = 1'b1;
        @(posedge CLK) muxSel = 'b01; 
        @(posedge CLK) muxSel = 'b10; outputRegister = 1'b1;
        @(posedge CLK) topRegister = 1'b1; $fwrite(c,"%b\n",y);
        bottomRegister = 1'b1;
        outputRegister = 1'b0;
        RST = 1'b1;
        
        @(posedge CLK) x <= inputsList[3]; muxSel = 'b00; RST = 1'b0;
        topRegister = 1'b0;
        bottomRegister = 1'b1;
        @(posedge CLK) muxSel = 'b01; 
        @(posedge CLK) muxSel = 'b10; outputRegister = 1'b1;
        @(posedge CLK) topRegister = 1'b1; $fwrite(c,"%b\n",y);
        bottomRegister = 1'b1;
        outputRegister = 1'b0;
        RST = 1'b1;
        
        #(ClockPeriod *6) $fclose(c); $finish;
    end
endmodule
module tb_TimeMultiplexed_FIR;

    parameter WI = 2, WF = 6;
    reg CLK, RST;
    reg topRegister, bottomRegister, outputRegister;
    reg [1:0] muxSel;
    reg signed [(WI+WF)-1:0] x, h0, h1, h2;
    wire signed [(WI+WF)-1:0] y;

    TimeMultiplexed_FIR #(.WI(WI),.WF(WF)) DUT (.CLK(CLK),.RST(RST),.topRegister(topRegister),.bottomRegister(bottomRegister),.outputRegister(outputRegister),.muxSel(muxSel),.x(x),.h0(h0),.h1(h1),.h2(h2),.y(y));
    
    parameter ClockPeriod = 10;
    initial CLK = 0;
    always #(ClockPeriod/2) CLK = ~CLK;
    
    integer c;
    initial begin
        c = $fopen("TimeMultiplexedFIR.txt");
    end
    reg [7:0] inputsList [3:0];
    reg [7:0] coeff [2:0];
    
    initial begin
        $readmemb("inputX.mem", inputsList);
        $readmemb("coeff.mem", coeff);
        h0 <= coeff[0]; h1 <= coeff[1]; h2 <= coeff[2]; RST = 1'b1;
        x <= 8'b00000000;
        @(posedge CLK) x <= 8'b00000000; muxSel = 'b00; topRegister = 1'b1;
        @(posedge CLK) x <= 8'b00000000; muxSel = 'b00; 
        @(posedge CLK) x <= 8'b00000000; muxSel = 'b00; 
        
        @(posedge CLK) x <= inputsList[0]; muxSel = 'b00; RST = 1'b0;
        topRegister = 1'b0;
        bottomRegister = 1'b1;
        @(posedge CLK) muxSel = 'b01; 
        @(posedge CLK) muxSel = 'b10; outputRegister = 1'b1; 
        @(posedge CLK) topRegister = 1'b1; $fwrite(c,"%b\n",y);
        bottomRegister = 1'b1;
        outputRegister = 1'b0;
        RST = 1'b1;
        
        @(posedge CLK) x <= inputsList[1]; muxSel = 'b00; RST = 1'b0;
        topRegister = 1'b0;
        bottomRegister = 1'b1;
        @(posedge CLK) muxSel = 'b01; 
        @(posedge CLK) muxSel = 'b10; outputRegister = 1'b1;
        @(posedge CLK) topRegister = 1'b1; $fwrite(c,"%b\n",y);
        bottomRegister = 1'b1;
        outputRegister = 1'b0;
        RST = 1'b1;
        
        @(posedge CLK) x <= inputsList[2]; muxSel = 'b00; RST = 1'b0;
        topRegister = 1'b0;
        bottomRegister = 1'b1;
        @(posedge CLK) muxSel = 'b01; 
        @(posedge CLK) muxSel = 'b10; outputRegister = 1'b1;
        @(posedge CLK) topRegister = 1'b1; $fwrite(c,"%b\n",y);
        bottomRegister = 1'b1;
        outputRegister = 1'b0;
        RST = 1'b1;
        
        @(posedge CLK) x <= inputsList[3]; muxSel = 'b00; RST = 1'b0;
        topRegister = 1'b0;
        bottomRegister = 1'b1;
        @(posedge CLK) muxSel = 'b01; 
        @(posedge CLK) muxSel = 'b10; outputRegister = 1'b1;
        @(posedge CLK) topRegister = 1'b1; $fwrite(c,"%b\n",y);
        bottomRegister = 1'b1;
        outputRegister = 1'b0;
        RST = 1'b1;
        
        #(ClockPeriod *6) $fclose(c); $finish;
    end
endmodule