data/full_repos/permissive/509809169/Verilog Language/Modules_Hierarchy/Three modules.v
1: b'%Error: Cannot find file containing module: Language/Modules_Hierarchy,data/full_repos/permissive/509809169\n        ... Looked in:\n             data/full_repos/permissive/509809169/Verilog/Language/Modules_Hierarchy,data/full_repos/permissive/509809169\n             data/full_repos/permissive/509809169/Verilog/Language/Modules_Hierarchy,data/full_repos/permissive/509809169.v\n             data/full_repos/permissive/509809169/Verilog/Language/Modules_Hierarchy,data/full_repos/permissive/509809169.sv\n             Language/Modules_Hierarchy,data/full_repos/permissive/509809169\n             Language/Modules_Hierarchy,data/full_repos/permissive/509809169.v\n             Language/Modules_Hierarchy,data/full_repos/permissive/509809169.sv\n             obj_dir/Language/Modules_Hierarchy,data/full_repos/permissive/509809169\n             obj_dir/Language/Modules_Hierarchy,data/full_repos/permissive/509809169.v\n             obj_dir/Language/Modules_Hierarchy,data/full_repos/permissive/509809169.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/509809169/Verilog\n%Error: Cannot find file containing module: Language/Modules_Hierarchy/Three\n%Error: Cannot find file containing module: modules.v\n%Error: Exiting due to 4 error(s)\n'
module top_module ( input clk, input d, output q );
	wire q1,q2;
    my_dff ins1(clk,d,q1);
    my_dff ins2(clk,q1,q2);
    my_dff ins3(clk,q2,q);
endmodule
module top_module ( input clk, input d, output q );

	wire q1,q2;
    my_dff ins1(clk,d,q1);
    my_dff ins2(clk,q1,q2);
    my_dff ins3(clk,q2,q);
endmodule