data/full_repos/permissive/420070038/examples/bootloader/fusesoc/rtl/clk/dcm_pll_generator.v
1: b"%Error: data/full_repos/permissive/420070038/examples/bootloader/fusesoc/rtl/clk/dcm_pll_generator.v:21: Cannot find file containing module: 'IBUFG'\nIBUFG sys_clk_in_ibufg (\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/420070038/examples/bootloader/fusesoc/rtl/clk,data/full_repos/permissive/420070038/IBUFG\n             data/full_repos/permissive/420070038/examples/bootloader/fusesoc/rtl/clk,data/full_repos/permissive/420070038/IBUFG.v\n             data/full_repos/permissive/420070038/examples/bootloader/fusesoc/rtl/clk,data/full_repos/permissive/420070038/IBUFG.sv\n             IBUFG\n             IBUFG.v\n             IBUFG.sv\n             obj_dir/IBUFG\n             obj_dir/IBUFG.v\n             obj_dir/IBUFG.sv\n%Error: data/full_repos/permissive/420070038/examples/bootloader/fusesoc/rtl/clk/dcm_pll_generator.v:65: Cannot find file containing module: 'MMCME2_BASE'\nMMCME2_BASE #(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/420070038/examples/bootloader/fusesoc/rtl/clk/dcm_pll_generator.v:129: Cannot find file containing module: 'BUFG'\nBUFG clk0(\n^~~~\n%Error: data/full_repos/permissive/420070038/examples/bootloader/fusesoc/rtl/clk/dcm_pll_generator.v:134: Cannot find file containing module: 'BUFG'\nBUFG clk1(\n^~~~\n%Error: data/full_repos/permissive/420070038/examples/bootloader/fusesoc/rtl/clk/dcm_pll_generator.v:139: Cannot find file containing module: 'BUFG'\nBUFG clk2(\n^~~~\n%Error: data/full_repos/permissive/420070038/examples/bootloader/fusesoc/rtl/clk/dcm_pll_generator.v:144: Cannot find file containing module: 'BUFG'\nBUFG clk_feedback(\n^~~~\n%Error: Exiting due to 6 error(s)\n"
module dcm_pll_generator(
  input global_clk_in,
  input rst,
  output locked,
  output clk200,
  output clk100,
  output clk50
  );



IBUFG sys_clk_in_ibufg (
	.I	(global_clk_in),
	.O	(global_clk_in_ibufg)
);


assign locked = mmcm_locked;
wire mmcm_clkout0;
wire mmcm_clkout1;
wire mmcm_clkout2;
wire mmcm_clkout3;
wire mmcm_clkout4;
wire mmcm_clkout5;
wire mmcm_clkout_feedback;
wire mmcm_locked;
wire mmcm_clkin_feedback;


MMCME2_BASE #(

  .BANDWIDTH("OPTIMIZED"),


  .CLKOUT0_DIVIDE_F(4),
  .CLKOUT1_DIVIDE(8),
  .CLKOUT2_DIVIDE(16),
  .CLKOUT3_DIVIDE(1),
  .CLKOUT4_DIVIDE(1),
  .CLKOUT5_DIVIDE(1),
  .CLKOUT6_DIVIDE(1),

  .CLKOUT0_PHASE(0.0),
  .CLKOUT1_PHASE(0.0),
  .CLKOUT2_PHASE(0.0),
  .CLKOUT3_PHASE(0.0),
  .CLKOUT4_PHASE(0.0),
  .CLKOUT5_PHASE(0.0),
  .CLKOUT6_PHASE(0.0),

  .CLKOUT0_DUTY_CYCLE(0.50),
  .CLKOUT1_DUTY_CYCLE(0.50),
  .CLKOUT2_DUTY_CYCLE(0.50),
  .CLKOUT3_DUTY_CYCLE(0.50),
  .CLKOUT4_DUTY_CYCLE(0.50),
  .CLKOUT5_DUTY_CYCLE(0.50),
  .CLKOUT6_DUTY_CYCLE(0.50),


  .CLKFBOUT_MULT_F(8),


  .DIVCLK_DIVIDE(1),

  .CLKFBOUT_PHASE(0.0),

  .REF_JITTER1(0.010),

  .CLKIN1_PERIOD(10.000),

  .STARTUP_WAIT("FALSE"),

  .CLKOUT4_CASCADE("FALSE")
)
mcmm(
  .CLKIN1(global_clk_in_ibufg),
  .CLKFBIN(mmcm_clkin_feedback),
  .RST(rst),
  .PWRDWN(1'b0),

  .CLKOUT0(mmcm_clkout0),
  .CLKOUT1(mmcm_clkout1),
  .CLKOUT2(mmcm_clkout2),
  .CLKOUT3(mmcm_clkout3),
  .CLKOUT4(mmcm_clkout4),
  .CLKOUT5(mmcm_clkout5),
  .CLKFBOUT(mmcm_clkout_feedback),

  .LOCKED(mmcm_locked)
);



BUFG clk0(
  .I(mmcm_clkout0),
  .O(clk200)
  );

BUFG clk1(
  .I(mmcm_clkout1),
  .O(clk100)
  );

BUFG clk2(
  .I(mmcm_clkout2),
  .O(clk50)
  );

BUFG clk_feedback(
  .I(mmcm_clkout_feedback),
  .O(mmcm_clkin_feedback)
  );


endmodule
module dcm_pll_generator(
  input global_clk_in,
  input rst,
  output locked,
  output clk200,
  output clk100,
  output clk50
  );




IBUFG sys_clk_in_ibufg (
	.I	(global_clk_in),
	.O	(global_clk_in_ibufg)
);


assign locked = mmcm_locked;
wire mmcm_clkout0;
wire mmcm_clkout1;
wire mmcm_clkout2;
wire mmcm_clkout3;
wire mmcm_clkout4;
wire mmcm_clkout5;
wire mmcm_clkout_feedback;
wire mmcm_locked;
wire mmcm_clkin_feedback;


MMCME2_BASE #(

  .BANDWIDTH("OPTIMIZED"),


  .CLKOUT0_DIVIDE_F(4),
  .CLKOUT1_DIVIDE(8),
  .CLKOUT2_DIVIDE(16),
  .CLKOUT3_DIVIDE(1),
  .CLKOUT4_DIVIDE(1),
  .CLKOUT5_DIVIDE(1),
  .CLKOUT6_DIVIDE(1),

  .CLKOUT0_PHASE(0.0),
  .CLKOUT1_PHASE(0.0),
  .CLKOUT2_PHASE(0.0),
  .CLKOUT3_PHASE(0.0),
  .CLKOUT4_PHASE(0.0),
  .CLKOUT5_PHASE(0.0),
  .CLKOUT6_PHASE(0.0),

  .CLKOUT0_DUTY_CYCLE(0.50),
  .CLKOUT1_DUTY_CYCLE(0.50),
  .CLKOUT2_DUTY_CYCLE(0.50),
  .CLKOUT3_DUTY_CYCLE(0.50),
  .CLKOUT4_DUTY_CYCLE(0.50),
  .CLKOUT5_DUTY_CYCLE(0.50),
  .CLKOUT6_DUTY_CYCLE(0.50),


  .CLKFBOUT_MULT_F(8),


  .DIVCLK_DIVIDE(1),

  .CLKFBOUT_PHASE(0.0),

  .REF_JITTER1(0.010),

  .CLKIN1_PERIOD(10.000),

  .STARTUP_WAIT("FALSE"),

  .CLKOUT4_CASCADE("FALSE")
)
mcmm(
  .CLKIN1(global_clk_in_ibufg),
  .CLKFBIN(mmcm_clkin_feedback),
  .RST(rst),
  .PWRDWN(1'b0),

  .CLKOUT0(mmcm_clkout0),
  .CLKOUT1(mmcm_clkout1),
  .CLKOUT2(mmcm_clkout2),
  .CLKOUT3(mmcm_clkout3),
  .CLKOUT4(mmcm_clkout4),
  .CLKOUT5(mmcm_clkout5),
  .CLKFBOUT(mmcm_clkout_feedback),

  .LOCKED(mmcm_locked)
);



BUFG clk0(
  .I(mmcm_clkout0),
  .O(clk200)
  );

BUFG clk1(
  .I(mmcm_clkout1),
  .O(clk100)
  );

BUFG clk2(
  .I(mmcm_clkout2),
  .O(clk50)
  );

BUFG clk_feedback(
  .I(mmcm_clkout_feedback),
  .O(mmcm_clkin_feedback)
  );


endmodule