data/full_repos/permissive/484799296/verilog/stack/top_tb.v
1: b'%Error: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:15: Unsupported or unknown PLI call: $monitor\n        $monitor("%b\\t%b\\t%b\\t%b\\t\\t%h\\t%h\\t", clk, reset, enable, w_enable, data_in, data_out);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #1 reset=1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #2 reset=0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=0; w_enable=0; data_in=4\'hF;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=0; w_enable=1; data_in=4\'hF;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=1; w_enable=1; data_in=4\'hF;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=0; w_enable=1; data_in=4\'h7;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=1; w_enable=1; data_in=4\'h7;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=0; w_enable=1; data_in=4\'ha;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=1; w_enable=1; data_in=4\'ha;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=0; w_enable=1; data_in=4\'h4;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=1; w_enable=1; data_in=4\'h4;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=0; w_enable=1; data_in=4\'h1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=1; w_enable=1; data_in=4\'h1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=0; w_enable=1; data_in=4\'h9;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=1; w_enable=1; data_in=4\'h9;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=0; w_enable=1; data_in=4\'hc;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=1; w_enable=1; data_in=4\'hc;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=0; w_enable=1; data_in=4\'h8;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=1; w_enable=1; data_in=4\'h8;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=0; w_enable=1; data_in=4\'h3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=1; w_enable=1; data_in=4\'h3;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=0; w_enable=0; data_in=4\'h0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=1; w_enable=0; data_in=4\'h0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=0; w_enable=0; data_in=4\'h0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=1; w_enable=0; data_in=4\'h0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=0; w_enable=0; data_in=4\'h0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=1; w_enable=0; data_in=4\'h0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=0; w_enable=0; data_in=4\'h0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=1; w_enable=0; data_in=4\'h0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=0; w_enable=0; data_in=4\'h0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=1; w_enable=0; data_in=4\'h0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=0; w_enable=0; data_in=4\'h0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=1; w_enable=0; data_in=4\'h0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=0; w_enable=0; data_in=4\'h0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=1; w_enable=0; data_in=4\'h0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=0; w_enable=0; data_in=4\'h0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=1; w_enable=0; data_in=4\'h0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=0; w_enable=0; data_in=4\'h0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=1; w_enable=0; data_in=4\'h0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n        #2 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n        #2 clk = ~clk;\n        ^\n%Error: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:77: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("top_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/484799296/verilog/stack/top_tb.v:78: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, Stack);\n        ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 41 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench ();
    reg clk;
    reg reset;
    reg enable;
    reg w_enable;
    reg [3:0] data_in;
    wire [3:0] data_out;

    stack_8x4 Stack(clk, reset, enable, w_enable, data_in, data_out);

    initial begin
        clk=0; reset=0; enable=0; w_enable=0; data_in=4'h0;
        $display("\nclk\treset\tenable\tw_enable\tdata_in\tdata_out");
        $monitor("%b\t%b\t%b\t%b\t\t%h\t%h\t", clk, reset, enable, w_enable, data_in, data_out);
        #1 reset=1;
        #2 reset=0;
        #2 enable=0; w_enable=0; data_in=4'hF;
        #2 enable=0; w_enable=1; data_in=4'hF;
        #2 enable=1; w_enable=1; data_in=4'hF;

        #2 enable=0; w_enable=1; data_in=4'h7;
        #2 enable=1; w_enable=1; data_in=4'h7;

        #2 enable=0; w_enable=1; data_in=4'ha;
        #2 enable=1; w_enable=1; data_in=4'ha;

        #2 enable=0; w_enable=1; data_in=4'h4;
        #2 enable=1; w_enable=1; data_in=4'h4;

        #2 enable=0; w_enable=1; data_in=4'h1;
        #2 enable=1; w_enable=1; data_in=4'h1;

        #2 enable=0; w_enable=1; data_in=4'h9;
        #2 enable=1; w_enable=1; data_in=4'h9;

        #2 enable=0; w_enable=1; data_in=4'hc;
        #2 enable=1; w_enable=1; data_in=4'hc;

        #2 enable=0; w_enable=1; data_in=4'h8;
        #2 enable=1; w_enable=1; data_in=4'h8;

        #2 enable=0; w_enable=1; data_in=4'h3;
        #2 enable=1; w_enable=1; data_in=4'h3;
        

        #2 enable=0; w_enable=0; data_in=4'h0;
        #2 enable=1; w_enable=0; data_in=4'h0;
        #2 enable=0; w_enable=0; data_in=4'h0;
        #2 enable=1; w_enable=0; data_in=4'h0;
        #2 enable=0; w_enable=0; data_in=4'h0;
        #2 enable=1; w_enable=0; data_in=4'h0;
        #2 enable=0; w_enable=0; data_in=4'h0;
        #2 enable=1; w_enable=0; data_in=4'h0;
        #2 enable=0; w_enable=0; data_in=4'h0;
        #2 enable=1; w_enable=0; data_in=4'h0;
        #2 enable=0; w_enable=0; data_in=4'h0;
        #2 enable=1; w_enable=0; data_in=4'h0;
        #2 enable=0; w_enable=0; data_in=4'h0;
        #2 enable=1; w_enable=0; data_in=4'h0;
        #2 enable=0; w_enable=0; data_in=4'h0;
        #2 enable=1; w_enable=0; data_in=4'h0;
        #2 enable=0; w_enable=0; data_in=4'h0;
        #2 enable=1; w_enable=0; data_in=4'h0;
        


        #2 $finish;
    end

    always begin
        #2 clk = ~clk;
    end


    initial begin
        $dumpfile("top_tb.vcd");
        $dumpvars(0, Stack);
    end

endmodule
module testbench ();

    reg clk;
    reg reset;
    reg enable;
    reg w_enable;
    reg [3:0] data_in;
    wire [3:0] data_out;

    stack_8x4 Stack(clk, reset, enable, w_enable, data_in, data_out);

    initial begin
        clk=0; reset=0; enable=0; w_enable=0; data_in=4'h0;
        $display("\nclk\treset\tenable\tw_enable\tdata_in\tdata_out");
        $monitor("%b\t%b\t%b\t%b\t\t%h\t%h\t", clk, reset, enable, w_enable, data_in, data_out);
        #1 reset=1;
        #2 reset=0;
        #2 enable=0; w_enable=0; data_in=4'hF;
        #2 enable=0; w_enable=1; data_in=4'hF;
        #2 enable=1; w_enable=1; data_in=4'hF;

        #2 enable=0; w_enable=1; data_in=4'h7;
        #2 enable=1; w_enable=1; data_in=4'h7;

        #2 enable=0; w_enable=1; data_in=4'ha;
        #2 enable=1; w_enable=1; data_in=4'ha;

        #2 enable=0; w_enable=1; data_in=4'h4;
        #2 enable=1; w_enable=1; data_in=4'h4;

        #2 enable=0; w_enable=1; data_in=4'h1;
        #2 enable=1; w_enable=1; data_in=4'h1;

        #2 enable=0; w_enable=1; data_in=4'h9;
        #2 enable=1; w_enable=1; data_in=4'h9;

        #2 enable=0; w_enable=1; data_in=4'hc;
        #2 enable=1; w_enable=1; data_in=4'hc;

        #2 enable=0; w_enable=1; data_in=4'h8;
        #2 enable=1; w_enable=1; data_in=4'h8;

        #2 enable=0; w_enable=1; data_in=4'h3;
        #2 enable=1; w_enable=1; data_in=4'h3;
        

        #2 enable=0; w_enable=0; data_in=4'h0;
        #2 enable=1; w_enable=0; data_in=4'h0;
        #2 enable=0; w_enable=0; data_in=4'h0;
        #2 enable=1; w_enable=0; data_in=4'h0;
        #2 enable=0; w_enable=0; data_in=4'h0;
        #2 enable=1; w_enable=0; data_in=4'h0;
        #2 enable=0; w_enable=0; data_in=4'h0;
        #2 enable=1; w_enable=0; data_in=4'h0;
        #2 enable=0; w_enable=0; data_in=4'h0;
        #2 enable=1; w_enable=0; data_in=4'h0;
        #2 enable=0; w_enable=0; data_in=4'h0;
        #2 enable=1; w_enable=0; data_in=4'h0;
        #2 enable=0; w_enable=0; data_in=4'h0;
        #2 enable=1; w_enable=0; data_in=4'h0;
        #2 enable=0; w_enable=0; data_in=4'h0;
        #2 enable=1; w_enable=0; data_in=4'h0;
        #2 enable=0; w_enable=0; data_in=4'h0;
        #2 enable=1; w_enable=0; data_in=4'h0;
        


        #2 $finish;
    end

    always begin
        #2 clk = ~clk;
    end


    initial begin
        $dumpfile("top_tb.vcd");
        $dumpvars(0, Stack);
    end

endmodule