data/full_repos/permissive/48330045/test/tb_ram_sp.v
1: b'%Error: data/full_repos/permissive/48330045/test/tb_ram_sp.v:1: Cannot find include file: ../rtl/ram_sp.v\n`include "../rtl/ram_sp.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/48330045/test,data/full_repos/permissive/48330045/../rtl/ram_sp.v\n             data/full_repos/permissive/48330045/test,data/full_repos/permissive/48330045/../rtl/ram_sp.v.v\n             data/full_repos/permissive/48330045/test,data/full_repos/permissive/48330045/../rtl/ram_sp.v.sv\n             ../rtl/ram_sp.v\n             ../rtl/ram_sp.v.v\n             ../rtl/ram_sp.v.sv\n             obj_dir/../rtl/ram_sp.v\n             obj_dir/../rtl/ram_sp.v.v\n             obj_dir/../rtl/ram_sp.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/48330045/test/tb_ram_sp.v:32: Unsupported: Ignoring delay on this delayed statement.\nalways #(CLK_PERIOD/2) clock = ~clock;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/48330045/test/tb_ram_sp.v:36: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("tb_ram_sp.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/48330045/test/tb_ram_sp.v:37: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, tb_ram_sp);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/48330045/test/tb_ram_sp.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #1 clock=1\'bx;wren=1\'bx;address={AWIDTH{1\'bx}};data={DWIDTH{1\'bx}};\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48330045/test/tb_ram_sp.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD) clock=0;address=0;wren=0;data=0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48330045/test/tb_ram_sp.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #(CLK_PERIOD) address=i;wren=1;data=(100-i);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/48330045/test/tb_ram_sp.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD) wren=0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48330045/test/tb_ram_sp.v:45: Unsupported: Ignoring delay on this delayed statement.\n    #(CLK_PERIOD) address=i;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/48330045/test/tb_ram_sp.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #(CLK_PERIOD*50);\n  ^\n%Error: Exiting due to 3 error(s), 7 warning(s)\n'
module tb_ram_sp;

parameter DWIDTH  = 8;
parameter AWIDTH  = 12;
parameter CONTENT = "./memory.txt";

reg               clock;
reg               wren;
reg  [AWIDTH-1:0] address;
reg  [DWIDTH-1:0] data;
wire [DWIDTH-1:0] q;

ram_sp
#(
  .DWIDTH  ( 8                   ),
  .AWIDTH  ( 12                  ),
  .CONTENT ( "./ram_content.txt" )
) _ram_sp
(
  .clock   ( clock   ),
  .wren    ( wren    ),
  .address ( address ),
  .data    ( data    ),
  .q       ( q       )
);

parameter CLK_PERIOD = 10.0;
always #(CLK_PERIOD/2) clock = ~clock;

integer i;
initial begin
  $dumpfile("tb_ram_sp.vcd");
  $dumpvars(0, tb_ram_sp);
  #1 clock=1'bx;wren=1'bx;address={AWIDTH{1'bx}};data={DWIDTH{1'bx}};
  #(CLK_PERIOD) clock=0;address=0;wren=0;data=0;
  for (i=0;i<=100;i=i+1) begin
    #(CLK_PERIOD) address=i;wren=1;data=(100-i);
  end
  #(CLK_PERIOD) wren=0;
  for (i=0;i<=100;i=i+1) begin
    #(CLK_PERIOD) address=i;
  end
  #(CLK_PERIOD*50);
  $finish(2);
end

endmodule
module tb_ram_sp;


parameter DWIDTH  = 8;
parameter AWIDTH  = 12;
parameter CONTENT = "./memory.txt";

reg               clock;
reg               wren;
reg  [AWIDTH-1:0] address;
reg  [DWIDTH-1:0] data;
wire [DWIDTH-1:0] q;

ram_sp
#(
  .DWIDTH  ( 8                   ),
  .AWIDTH  ( 12                  ),
  .CONTENT ( "./ram_content.txt" )
) _ram_sp
(
  .clock   ( clock   ),
  .wren    ( wren    ),
  .address ( address ),
  .data    ( data    ),
  .q       ( q       )
);

parameter CLK_PERIOD = 10.0;
always #(CLK_PERIOD/2) clock = ~clock;

integer i;
initial begin
  $dumpfile("tb_ram_sp.vcd");
  $dumpvars(0, tb_ram_sp);
  #1 clock=1'bx;wren=1'bx;address={AWIDTH{1'bx}};data={DWIDTH{1'bx}};
  #(CLK_PERIOD) clock=0;address=0;wren=0;data=0;
  for (i=0;i<=100;i=i+1) begin
    #(CLK_PERIOD) address=i;wren=1;data=(100-i);
  end
  #(CLK_PERIOD) wren=0;
  for (i=0;i<=100;i=i+1) begin
    #(CLK_PERIOD) address=i;
  end
  #(CLK_PERIOD*50);
  $finish(2);
end

endmodule