data/full_repos/permissive/488660558/addroundkey/test2.v
data/verilator_xmls/4aa81ad9-f419-4960-80e3-bf8fe875ec2b.xml
module addroundkey(state,state_out,key);
	input wire [127:0] key;
	input wire [127:0] state;
	output [127:0] state_out;
	
    assign state_out=key^state;
endmodule
module addroundkey(state,state_out,key);

	input wire [127:0] key;
	input wire [127:0] state;
	output [127:0] state_out;
	
    assign state_out=key^state;
endmodule