data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/original.v
1: b'%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/original.v:11: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 2 bits.\n                                                                                                              : ... In instance original\n        dout[ctrl*sel+:SLICE] <= din ;\n                              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module original #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SELW)
   (input wire             clk,
    input wire [CTRLW-1:0] ctrl,
    input wire [DINW-1:0]  din,
    input wire [SELW-1:0]  sel,
    output reg [WIDTH-1:0] dout);
   localparam SLICE = WIDTH/(SELW**2);
   always @(posedge clk)
     begin
        dout[ctrl*sel+:SLICE] <= din ;
     end
endmodule
module original #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SELW)
   (input wire             clk,
    input wire [CTRLW-1:0] ctrl,
    input wire [DINW-1:0]  din,
    input wire [SELW-1:0]  sel,
    output reg [WIDTH-1:0] dout);

   localparam SLICE = WIDTH/(SELW**2);
   always @(posedge clk)
     begin
        dout[ctrl*sel+:SLICE] <= din ;
     end
endmodule