data/full_repos/permissive/432564927/Lab3 (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new/CPU.v
1: b'%Error: Cannot find file containing module: (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927\n        ... Looked in:\n             data/full_repos/permissive/432564927/Lab3/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927\n             data/full_repos/permissive/432564927/Lab3/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             data/full_repos/permissive/432564927/Lab3/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927\n             (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             obj_dir/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927\n             obj_dir/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             obj_dir/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/432564927/Lab3\n%Error: Cannot find file containing module: (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new/CPU.v\n%Error: Exiting due to 3 error(s)\n'
module RegFile(
    input we,
    input [4:0] rna,
    input [4:0] rnb,
    input [4:0] wn,
    input [4:0] d,
    output reg [31:0] qa,
    output reg [31:0] qb
    );

    reg [31:0] registers [0:127];
    initial begin
        registers[0] = 0;
        registers[1] = 0;
        registers[2] = 0;
        registers[3] = 0;
        registers[4] = 0;
        registers[5] = 0;
        registers[6] = 0;
        registers[7] = 0;
        registers[8] = 0;
        registers[9] = 0;
        registers[10] = 0;
        registers[11] = 0;
        registers[12] = 0;
        registers[13] = 0;
        registers[14] = 0;
        registers[15] = 0;
    end
    always@(rna, rnb) begin
        qa = registers[rna];
        qb = registers[rnb];
    end
endmodule
module RegFile(
    input we,
    input [4:0] rna,
    input [4:0] rnb,
    input [4:0] wn,
    input [4:0] d,
    output reg [31:0] qa,
    output reg [31:0] qb
    );


    reg [31:0] registers [0:127];
    initial begin
        registers[0] = 0;
        registers[1] = 0;
        registers[2] = 0;
        registers[3] = 0;
        registers[4] = 0;
        registers[5] = 0;
        registers[6] = 0;
        registers[7] = 0;
        registers[8] = 0;
        registers[9] = 0;
        registers[10] = 0;
        registers[11] = 0;
        registers[12] = 0;
        registers[13] = 0;
        registers[14] = 0;
        registers[15] = 0;
    end
    always@(rna, rnb) begin
        qa = registers[rna];
        qb = registers[rnb];
    end
endmodule