data/full_repos/permissive/52714256/INTERFACES/src/ARINC429/reciever.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/52714256/INTERFACES/src/ARINC429/reciever.v:54: Signal definition not found, creating implicitly: \'parity\'\n        assign parity =^ data[31:1];                                         \n               ^~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/52714256/INTERFACES/src/ARINC429/reciever.v:56: Signal definition not found, creating implicitly: \'sig\'\n        assign sig = (in1 | in0);\n               ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/52714256/INTERFACES/src/ARINC429/reciever.v:57: Signal definition not found, creating implicitly: \'glitch\'\n        assign glitch = ((!sig) && ((cc != m12_5kb) || (cc != m12_5kb-1))  \n               ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/52714256/INTERFACES/src/ARINC429/reciever.v:57: Operator NEQ expects 32 or 26 bits on the LHS, but LHS\'s VARREF \'cc\' generates 11 bits.\n                                                                                         : ... In instance AR_RXD\n        assign glitch = ((!sig) && ((cc != m12_5kb) || (cc != m12_5kb-1))  \n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/52714256/INTERFACES/src/ARINC429/reciever.v:57: Operator NEQ expects 32 or 26 bits on the LHS, but LHS\'s VARREF \'cc\' generates 11 bits.\n                                                                                         : ... In instance AR_RXD\n        assign glitch = ((!sig) && ((cc != m12_5kb) || (cc != m12_5kb-1))  \n                                                           ^~\n%Warning-WIDTH: data/full_repos/permissive/52714256/INTERFACES/src/ARINC429/reciever.v:58: Operator NEQ expects 32 or 26 bits on the LHS, but LHS\'s VARREF \'cc\' generates 11 bits.\n                                                                                         : ... In instance AR_RXD\n                                      && ((cc != m50kb) || (cc != m50kb-1)) \n                                              ^~\n%Warning-WIDTH: data/full_repos/permissive/52714256/INTERFACES/src/ARINC429/reciever.v:58: Operator NEQ expects 32 or 26 bits on the LHS, but LHS\'s VARREF \'cc\' generates 11 bits.\n                                                                                         : ... In instance AR_RXD\n                                      && ((cc != m50kb) || (cc != m50kb-1)) \n                                                               ^~\n%Warning-WIDTH: data/full_repos/permissive/52714256/INTERFACES/src/ARINC429/reciever.v:59: Operator NEQ expects 32 or 26 bits on the LHS, but LHS\'s VARREF \'cc\' generates 11 bits.\n                                                                                         : ... In instance AR_RXD\n                                      && ((cc != m100kb) || (cc != m100kb-1)));\n                                              ^~\n%Warning-WIDTH: data/full_repos/permissive/52714256/INTERFACES/src/ARINC429/reciever.v:59: Operator NEQ expects 32 or 26 bits on the LHS, but LHS\'s VARREF \'cc\' generates 11 bits.\n                                                                                         : ... In instance AR_RXD\n                                      && ((cc != m100kb) || (cc != m100kb-1)));\n                                                                ^~\n%Warning-WIDTH: data/full_repos/permissive/52714256/INTERFACES/src/ARINC429/reciever.v:64: Operator EQ expects 32 or 26 bits on the LHS, but LHS\'s VARREF \'cc\' generates 11 bits.\n                                                                                         : ... In instance AR_RXD\n            if (!sig & !glitch) cur_mode = ((cc == m12_5kb) || (cc == m12_5kb-1)) ? 1 :\n                                                ^~\n%Warning-WIDTH: data/full_repos/permissive/52714256/INTERFACES/src/ARINC429/reciever.v:64: Operator EQ expects 32 or 26 bits on the LHS, but LHS\'s VARREF \'cc\' generates 11 bits.\n                                                                                         : ... In instance AR_RXD\n            if (!sig & !glitch) cur_mode = ((cc == m12_5kb) || (cc == m12_5kb-1)) ? 1 :\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/52714256/INTERFACES/src/ARINC429/reciever.v:65: Operator EQ expects 32 or 26 bits on the LHS, but LHS\'s VARREF \'cc\' generates 11 bits.\n                                                                                         : ... In instance AR_RXD\n                          ((cc == m50kb) || (cc == m50kb-1)) ? 2 :\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/52714256/INTERFACES/src/ARINC429/reciever.v:65: Operator EQ expects 32 or 26 bits on the LHS, but LHS\'s VARREF \'cc\' generates 11 bits.\n                                                                                         : ... In instance AR_RXD\n                          ((cc == m50kb) || (cc == m50kb-1)) ? 2 :\n                                                ^~\n%Warning-WIDTH: data/full_repos/permissive/52714256/INTERFACES/src/ARINC429/reciever.v:66: Operator EQ expects 32 or 26 bits on the LHS, but LHS\'s VARREF \'cc\' generates 11 bits.\n                                                                                         : ... In instance AR_RXD\n                          ((cc == m100kb) || (cc == m100kb-1)) ? 3 :\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/52714256/INTERFACES/src/ARINC429/reciever.v:66: Operator EQ expects 32 or 26 bits on the LHS, but LHS\'s VARREF \'cc\' generates 11 bits.\n                                                                                         : ... In instance AR_RXD\n                          ((cc == m100kb) || (cc == m100kb-1)) ? 3 :\n                                                 ^~\n%Error: Exiting due to 15 warning(s)\n'
module AR_RXD(
    input clk,
    input in0,
    input in1,
    output [22:0] sr_dat,
    output [7:0]  sr_adr,
    output ce_wr
    );
	 
        parameter Fclk = 50000000;
        parameter V100kb = 100000;
        parameter V50kb = 50000;
        parameter V12_5kb = 12500;
        parameter m100kb = Fclk/V100kb;
        parameter m50kb = Fclk/V50kb;
        parameter m12_5kb = Fclk/V12_5kb;
    
        reg [31:0]data = 0;
        reg [6:0] cb = 0;
        reg [10:0] cc = 0;
        reg [1:0] cur_mode = 0;
        reg [1:0] prev_mode = 0;
        reg [1:0] new_bit = 0;
        reg [0:0] err = 0;
        
        genvar i;
         generate for (i = 23; i >= 1; i = i - 1)
           begin
               assign sr_dat[i-1] = data[24-i];
           end  
        endgenerate
        
        assign sr_adr = data[31:24];
        assign parity =^ data[31:1];
        assign ce_wr = (!parity == data[0]) && (cb == 32);
        assign sig = (in1 | in0);
        assign glitch = ((!sig) && ((cc != m12_5kb) || (cc != m12_5kb-1))
                                      && ((cc != m50kb) || (cc != m50kb-1)) 
                                      && ((cc != m100kb) || (cc != m100kb-1)));
        
    
        always @(posedge clk) begin
            if (!sig & !glitch) prev_mode = cur_mode;
            if (!sig & !glitch) cur_mode = ((cc == m12_5kb) || (cc == m12_5kb-1)) ? 1 :
                          ((cc == m50kb) || (cc == m50kb-1)) ? 2 :
                          ((cc == m100kb) || (cc == m100kb-1)) ? 3 :
                          0;
            if ((!sig) && (cur_mode != prev_mode) && (cb != 32)) err <= 1;
    
            data <= ((!err) && (!sig) && (new_bit == 1)) ? ((data << 1) + 1) :
                     ((!err) && (!sig) && (new_bit == 0)) ? (data << 1):
                     ((!err) && (!sig)) ? data:
                     (sig) ? data :
                     0;
            if ((!err) && (!sig) && (cb != 32) && ((new_bit == 1) ||(new_bit == 0))) 
                cb <= cb + 1;
            
            new_bit <= (in1 && !glitch && !err) ? 1 : (in0 && !glitch && !err) ? 0 : 2;
            
            if (new_bit == 2) cc <= 0;
            if (sig) cc <= cc + 1;
            if (glitch) cc <= 0;
        end

endmodule
module AR_RXD(
    input clk,
    input in0,
    input in1,
    output [22:0] sr_dat,
    output [7:0]  sr_adr,
    output ce_wr
    );

	 
        parameter Fclk = 50000000;
        parameter V100kb = 100000;
        parameter V50kb = 50000;
        parameter V12_5kb = 12500;
        parameter m100kb = Fclk/V100kb;
        parameter m50kb = Fclk/V50kb;
        parameter m12_5kb = Fclk/V12_5kb;
    
        reg [31:0]data = 0;
        reg [6:0] cb = 0;
        reg [10:0] cc = 0;
        reg [1:0] cur_mode = 0;
        reg [1:0] prev_mode = 0;
        reg [1:0] new_bit = 0;
        reg [0:0] err = 0;
        
        genvar i;
         generate for (i = 23; i >= 1; i = i - 1)
           begin
               assign sr_dat[i-1] = data[24-i];
           end  
        endgenerate
        
        assign sr_adr = data[31:24];
        assign parity =^ data[31:1];
        assign ce_wr = (!parity == data[0]) && (cb == 32);
        assign sig = (in1 | in0);
        assign glitch = ((!sig) && ((cc != m12_5kb) || (cc != m12_5kb-1))
                                      && ((cc != m50kb) || (cc != m50kb-1)) 
                                      && ((cc != m100kb) || (cc != m100kb-1)));
        
    
        always @(posedge clk) begin
            if (!sig & !glitch) prev_mode = cur_mode;
            if (!sig & !glitch) cur_mode = ((cc == m12_5kb) || (cc == m12_5kb-1)) ? 1 :
                          ((cc == m50kb) || (cc == m50kb-1)) ? 2 :
                          ((cc == m100kb) || (cc == m100kb-1)) ? 3 :
                          0;
            if ((!sig) && (cur_mode != prev_mode) && (cb != 32)) err <= 1;
    
            data <= ((!err) && (!sig) && (new_bit == 1)) ? ((data << 1) + 1) :
                     ((!err) && (!sig) && (new_bit == 0)) ? (data << 1):
                     ((!err) && (!sig)) ? data:
                     (sig) ? data :
                     0;
            if ((!err) && (!sig) && (cb != 32) && ((new_bit == 1) ||(new_bit == 0))) 
                cb <= cb + 1;
            
            new_bit <= (in1 && !glitch && !err) ? 1 : (in0 && !glitch && !err) ? 0 : 2;
            
            if (new_bit == 2) cc <= 0;
            if (sig) cc <= cc + 1;
            if (glitch) cc <= 0;
        end

endmodule