data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v
1: b"%Error: data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v:85: syntax error, unexpected type, expecting IDENTIFIER or '[' or do or final\n input  wire [1:0]           type,     \n                             ^~~~\n%Error: data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v:87: syntax error, unexpected ')', expecting ',' or ';'\n);\n^\n%Error: data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v:90: syntax error, unexpected IDENTIFIER\n    mirror m1(.in(a), .out(ma));\n    ^~~~~~\n%Error: data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v:379: syntax error, unexpected type\n        .type(alufn[1:0]),\n         ^~~~\n%Error: Exiting due to 4 error(s)\n"
module rv32i_alu #(parameter ADDER_TYPE = 2) (
	input   wire [31:0]     a, b,
	input   wire [ 4:0]     shamt,
	output  reg  [31:0]     r,
	output  wire            cf, zf, vf, sf,
	input   wire [ 3:0]     alufn
);

    wire [31: 0] add, sub, op_b;
    wire [31: 0] sh;

    assign op_b = b ^ {32{alufn[0]}};

    adder_32 #(.ADDER_TYPE(ADDER_TYPE)) adder ( 
        .a(a), .b(op_b),
        .ci(alufn[0]),
        .s(add),
        .co(cf)
    );

    assign zf = (add == 0);
    assign sf = add[31];
    assign vf = (a[31] ^ (op_b[31]) ^ add[31] ^ cf);

    shift shift0 (
        .a(a),
        .shamt(shamt),
        .type(alufn[1:0]),
        .r(sh)
	);

    always @ * begin
        (* full_case *)
        (* parallel_case *)
        case (alufn)

            4'b00_00 :  r = add;
            4'b00_01 :  r = add;
            4'b00_11 :  r = b;

            4'b01_00:   r = a | b;
            4'b01_01:   r = a & b;
            4'b01_11:   r = a ^ b;

            4'b10_00:   r = sh;
            4'b10_01:   r = sh;
            4'b10_10:   r = sh;

            4'b11_01:   r = {31'b0,(sf != vf)};
            4'b11_11:   r = {31'b0,(~cf)};

			default:    r = add;
        endcase
    end
endmodule
module rv32i_alu #(parameter ADDER_TYPE = 2) (
	input   wire [31:0]     a, b,
	input   wire [ 4:0]     shamt,
	output  reg  [31:0]     r,
	output  wire            cf, zf, vf, sf,
	input   wire [ 3:0]     alufn
);


    wire [31: 0] add, sub, op_b;
    wire [31: 0] sh;

    assign op_b = b ^ {32{alufn[0]}};

    adder_32 #(.ADDER_TYPE(ADDER_TYPE)) adder ( 
        .a(a), .b(op_b),
        .ci(alufn[0]),
        .s(add),
        .co(cf)
    );

    assign zf = (add == 0);
    assign sf = add[31];
    assign vf = (a[31] ^ (op_b[31]) ^ add[31] ^ cf);

    shift shift0 (
        .a(a),
        .shamt(shamt),
        .type(alufn[1:0]),
        .r(sh)
	);

    always @ * begin
        (* full_case *)
        (* parallel_case *)
        case (alufn)

            4'b00_00 :  r = add;
            4'b00_01 :  r = add;
            4'b00_11 :  r = b;

            4'b01_00:   r = a | b;
            4'b01_01:   r = a & b;
            4'b01_11:   r = a ^ b;

            4'b10_00:   r = sh;
            4'b10_01:   r = sh;
            4'b10_10:   r = sh;

            4'b11_01:   r = {31'b0,(sf != vf)};
            4'b11_11:   r = {31'b0,(~cf)};

			default:    r = add;
        endcase
    end
endmodule