data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Shift Registers/ece241_2013_q12/top_module_tb.v
1: b'%Error: Cannot find file containing module: Logic/Shift\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Shift\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Shift.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Shift.sv\n             Logic/Shift\n             Logic/Shift.v\n             Logic/Shift.sv\n             obj_dir/Logic/Shift\n             obj_dir/Logic/Shift.v\n             obj_dir/Logic/Shift.sv\n%Error: Cannot find file containing module: Registers/ece241_2013_q12,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Registers/ece241_2013_q12/top_module_tb.v\n%Error: Exiting due to 4 error(s)\n'
module top_module_tb ();
  reg clk = 1'b1;
  reg enable = 1'b0;
  reg in = 1'b0;
  reg [2:0] select = 3'b0;
  wire out;

  localparam ITERATIONS = 300;

  always begin
    in = $random;
    #1 clk = clk + 1;
  end

  initial begin
    #30 enable = 1'b1;
    #30 enable = 1'b0;
  end

  initial begin
    #70 select = select + 1;
    #0.5 select = select + 1;
    #0.5 select = select + 1;
    #0.5 select = select + 1;
    #0.5 select = select + 1;
    #0.5 select = select + 1;
    #0.5 select = select + 1;
    #0.5 select = select + 1;
    #0.5 select = select + 1;
  end

  top_module uut (
      .clk(clk),
      .enable(enable),
      .S(in),
      .A(select[2]),
      .B(select[1]),
      .C(select[0]),
      .Z(out)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule
module top_module_tb ();

  reg clk = 1'b1;
  reg enable = 1'b0;
  reg in = 1'b0;
  reg [2:0] select = 3'b0;
  wire out;

  localparam ITERATIONS = 300;

  always begin
    in = $random;
    #1 clk = clk + 1;
  end

  initial begin
    #30 enable = 1'b1;
    #30 enable = 1'b0;
  end

  initial begin
    #70 select = select + 1;
    #0.5 select = select + 1;
    #0.5 select = select + 1;
    #0.5 select = select + 1;
    #0.5 select = select + 1;
    #0.5 select = select + 1;
    #0.5 select = select + 1;
    #0.5 select = select + 1;
    #0.5 select = select + 1;
  end

  top_module uut (
      .clk(clk),
      .enable(enable),
      .S(in),
      .A(select[2]),
      .B(select[1]),
      .C(select[0]),
      .Z(out)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule