data/full_repos/permissive/42061259/LIFO_FIFO/DUT.v
1: b'%Error: data/full_repos/permissive/42061259/LIFO_FIFO/DUT.v:7: Cannot find include file: ram.v\n`include "ram.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/42061259/LIFO_FIFO,data/full_repos/permissive/42061259/ram.v\n             data/full_repos/permissive/42061259/LIFO_FIFO,data/full_repos/permissive/42061259/ram.v.v\n             data/full_repos/permissive/42061259/LIFO_FIFO,data/full_repos/permissive/42061259/ram.v.sv\n             ram.v\n             ram.v.v\n             ram.v.sv\n             obj_dir/ram.v\n             obj_dir/ram.v.v\n             obj_dir/ram.v.sv\n%Error: Exiting due to 1 error(s)\n'
module DUT #(parameter MODE=1'b1, parameter dat_width=32, parameter L=6, parameter DEPTH=64) 
(	input   [dat_width-1:0] Datain,
	input   Wren,
	input   Rden, 
	input   Wrclk,   
	input   Rdclk,   
	input   Rst,
	output  reg Full,
	output  reg Empty,
	output  reg [dat_width-1:0] Dataout
);   





	wire [dat_width-1:0] data_ram;
	wire CLK;
  

	reg [L-1:0] adr_rd_i;
	reg [L-1:0] adr_wr_i;
	reg [L-1:0] status_cnt; 
  	



   

	assign CLK = (MODE == 1'b1 )? Rdclk : Wrclk;

  		
	



	always @ (posedge Wrclk or posedge Rst) begin : WRITE_POINTER

		if (Rst) begin
			adr_wr_i <= 0;
		end 
		
		else if (Wrclk && Wren) begin
		
			if (adr_wr_i == DEPTH ) begin
				adr_wr_i <= adr_wr_i;
			end 
			
			else begin
				adr_wr_i <= adr_wr_i + 1;
			end
			
		end
		

		if((MODE==0) && Rden) begin
			
			if(adr_wr_i == 0) begin
				adr_wr_i <= adr_wr_i;
			end
			
			else begin		
				adr_wr_i <= adr_wr_i -1;
			end
		
		end
		
	end





	always @ (posedge CLK or posedge Rst) begin : READ_POINTER
	
		if (Rst) begin
			adr_rd_i <= 0;
		end 
		

		else if (Rden && (MODE == 1'b1) ) begin
			if (adr_rd_i == DEPTH ) begin
				adr_rd_i <= adr_rd_i;               
			end 
			
			else begin
				adr_rd_i <= adr_rd_i + 1;
         end    		
		end 
		

		if(MODE == 1'b0) begin
			adr_rd_i <= adr_wr_i-1;
		end
		
	end
	
	




	always  @ (posedge CLK or posedge Rst ) begin : READ_DATA
		if (Rst ||!Rden ) begin
			Dataout <= 0;
		end else if (Rden) begin
			Dataout <= data_ram;
		end 
	end
	



	always @ (posedge CLK or posedge Rst) begin : STATUS_COUNTER
		

		if (Rst) begin
			status_cnt <= 0;
		

		end else if (Rden &&  !(Wren) && (status_cnt  != 0) ) begin
			status_cnt <= status_cnt - 1;
			

		end else if (Wren &&  !(Rden) && (status_cnt  != DEPTH)) begin
			

			if (status_cnt == (DEPTH-1)) begin
				status_cnt <=status_cnt;
			

			end else begin
				status_cnt <= status_cnt + 1;
			

			
			end
		end
	end 




	always @ (posedge Wrclk or posedge Rst) begin: FULL_EMPTY
	
		if (Rst) begin
			Full  <= 0 ;
			Empty <= 1 ;

		end else if (status_cnt == (DEPTH-1)) begin
			Full  <= 1 ;
			Empty <= 0 ;
			
		end else if (status_cnt == 0) begin
			Full  <= 0 ;
			Empty <= 1 ;
		
		end else begin
			Full  <= 0 ;
			Empty <= 0 ;
		end
	end
	



	ram #(
		.mem_size(DEPTH),
		.adr_width(L),
		.dat_width(dat_width)
	) RAM(
			.dat_i(Datain), 
			.dat_o(data_ram), 
			.adr_wr_i(adr_wr_i), 
			.adr_rd_i(adr_rd_i), 
			.we_i(Wren), 
			.rde_i(Rden), 
			.clk(CLK)
			);

endmodule
module DUT #(parameter MODE=1'b1, parameter dat_width=32, parameter L=6, parameter DEPTH=64) 
(	input   [dat_width-1:0] Datain,
	input   Wren,
	input   Rden, 
	input   Wrclk,   
	input   Rdclk,   
	input   Rst,
	output  reg Full,
	output  reg Empty,
	output  reg [dat_width-1:0] Dataout
);
   





	wire [dat_width-1:0] data_ram;
	wire CLK;
  

	reg [L-1:0] adr_rd_i;
	reg [L-1:0] adr_wr_i;
	reg [L-1:0] status_cnt; 
  	



   

	assign CLK = (MODE == 1'b1 )? Rdclk : Wrclk;

  		
	



	always @ (posedge Wrclk or posedge Rst) begin : WRITE_POINTER

		if (Rst) begin
			adr_wr_i <= 0;
		end 
		
		else if (Wrclk && Wren) begin
		
			if (adr_wr_i == DEPTH ) begin
				adr_wr_i <= adr_wr_i;
			end 
			
			else begin
				adr_wr_i <= adr_wr_i + 1;
			end
			
		end
		

		if((MODE==0) && Rden) begin
			
			if(adr_wr_i == 0) begin
				adr_wr_i <= adr_wr_i;
			end
			
			else begin		
				adr_wr_i <= adr_wr_i -1;
			end
		
		end
		
	end





	always @ (posedge CLK or posedge Rst) begin : READ_POINTER
	
		if (Rst) begin
			adr_rd_i <= 0;
		end 
		

		else if (Rden && (MODE == 1'b1) ) begin
			if (adr_rd_i == DEPTH ) begin
				adr_rd_i <= adr_rd_i;               
			end 
			
			else begin
				adr_rd_i <= adr_rd_i + 1;
         end    		
		end 
		

		if(MODE == 1'b0) begin
			adr_rd_i <= adr_wr_i-1;
		end
		
	end
	
	




	always  @ (posedge CLK or posedge Rst ) begin : READ_DATA
		if (Rst ||!Rden ) begin
			Dataout <= 0;
		end else if (Rden) begin
			Dataout <= data_ram;
		end 
	end
	



	always @ (posedge CLK or posedge Rst) begin : STATUS_COUNTER
		

		if (Rst) begin
			status_cnt <= 0;
		

		end else if (Rden &&  !(Wren) && (status_cnt  != 0) ) begin
			status_cnt <= status_cnt - 1;
			

		end else if (Wren &&  !(Rden) && (status_cnt  != DEPTH)) begin
			

			if (status_cnt == (DEPTH-1)) begin
				status_cnt <=status_cnt;
			

			end else begin
				status_cnt <= status_cnt + 1;
			

			
			end
		end
	end 




	always @ (posedge Wrclk or posedge Rst) begin: FULL_EMPTY
	
		if (Rst) begin
			Full  <= 0 ;
			Empty <= 1 ;

		end else if (status_cnt == (DEPTH-1)) begin
			Full  <= 1 ;
			Empty <= 0 ;
			
		end else if (status_cnt == 0) begin
			Full  <= 0 ;
			Empty <= 1 ;
		
		end else begin
			Full  <= 0 ;
			Empty <= 0 ;
		end
	end
	



	ram #(
		.mem_size(DEPTH),
		.adr_width(L),
		.dat_width(dat_width)
	) RAM(
			.dat_i(Datain), 
			.dat_o(data_ram), 
			.adr_wr_i(adr_wr_i), 
			.adr_rd_i(adr_rd_i), 
			.we_i(Wren), 
			.rde_i(Rden), 
			.clk(CLK)
			);

endmodule