data/full_repos/permissive/42434302/ivltests/pr1648365.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1648365.v:6: Unsupported: Ignoring delay on this delayed statement.\n    #0;  \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/42434302/ivltests/pr1648365.v:9: Unsupported or unknown PLI call: $monitor\n    $monitor($time,,"w0=%h, w1=%h", w0, w1);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/pr1648365.v:9: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    $monitor($time,,"w0=%h, w1=%h", w0, w1);\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1648365.v:10: Unsupported: Ignoring delay on this delayed statement.\n    #1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1648365.v:14: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1648365.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1648365.v:59: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ivitest;

reg clock_1x, clock_2x;

initial begin
    #0;
    clock_1x = 0;
    clock_2x = 0;
    $monitor($time,,"w0=%h, w1=%h", w0, w1);
    #1;
    forever begin
        clock_1x = !clock_1x;
        clock_2x = !clock_2x;
        #5;
        clock_2x = !clock_2x;
        #5;
    end
end

reg phase;
always @(clock_1x) begin
    phase = #1 clock_1x;
end

reg [31:1] u;

always @(posedge clock_2x) begin
    u <= 'haaaaaaaa;
end


reg [31:1] v;
reg [31:1] w [0:1];

wire [31:1] w0 = w[0];
wire [31:1] w1 = w[1];

always @(posedge clock_2x) begin
    v <= 'h99999999;
    if (phase) begin
        w[0] <= v;
        w[1] <= u;
    end
end


reg [31:1] x0, x1;

always @(posedge clock_1x) begin
    x0 <= w[0];
    x1 <= w[1];
end


initial begin



    #100;
    $finish;
end


endmodule
module ivitest;


reg clock_1x, clock_2x;

initial begin
    #0;
    clock_1x = 0;
    clock_2x = 0;
    $monitor($time,,"w0=%h, w1=%h", w0, w1);
    #1;
    forever begin
        clock_1x = !clock_1x;
        clock_2x = !clock_2x;
        #5;
        clock_2x = !clock_2x;
        #5;
    end
end

reg phase;
always @(clock_1x) begin
    phase = #1 clock_1x;
end

reg [31:1] u;

always @(posedge clock_2x) begin
    u <= 'haaaaaaaa;
end


reg [31:1] v;
reg [31:1] w [0:1];

wire [31:1] w0 = w[0];
wire [31:1] w1 = w[1];

always @(posedge clock_2x) begin
    v <= 'h99999999;
    if (phase) begin
        w[0] <= v;
        w[1] <= u;
    end
end


reg [31:1] x0, x1;

always @(posedge clock_1x) begin
    x0 <= w[0];
    x1 <= w[1];
end


initial begin



    #100;
    $finish;
end


endmodule