data/full_repos/permissive/48192473/rtl/collaterals.v
1: b'%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:5: Cannot find include file: aDefinitions.v\n`include "aDefinitions.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/48192473/rtl,data/full_repos/permissive/48192473/aDefinitions.v\n             data/full_repos/permissive/48192473/rtl,data/full_repos/permissive/48192473/aDefinitions.v.v\n             data/full_repos/permissive/48192473/rtl,data/full_repos/permissive/48192473/aDefinitions.v.sv\n             aDefinitions.v\n             aDefinitions.v.v\n             aDefinitions.v.sv\n             obj_dir/aDefinitions.v\n             obj_dir/aDefinitions.v.v\n             obj_dir/aDefinitions.v.sv\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:27: Define or directive not defined: \'`WIDTH\'\nmodule FFD_POSEDGE_SYNCRONOUS_RESET # ( parameter SIZE=`WIDTH )\n                                                       ^~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:27: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nmodule FFD_POSEDGE_SYNCRONOUS_RESET # ( parameter SIZE=`WIDTH )\n                                                              ^\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:30: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire    Reset,\n ^~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:31: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire    Enable,\n ^~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:32: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [SIZE-1:0] D,\n ^~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:33: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output reg [SIZE-1:0] Q\n ^~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:34: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:67: Define or directive not defined: \'`WIDTH\'\nmodule FFD_POSEDGE_SYNCRONOUS_RESET_INIT # ( parameter SIZE=`WIDTH )\n                                                            ^~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:67: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nmodule FFD_POSEDGE_SYNCRONOUS_RESET_INIT # ( parameter SIZE=`WIDTH )\n                                                                   ^\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:70: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire    Reset,\n ^~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:71: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire    Enable,\n ^~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:72: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [SIZE-1:0]   iInitial,\n ^~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:73: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [SIZE-1:0] D,\n ^~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:74: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output reg [SIZE-1:0] Q\n ^~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:75: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:92: Define or directive not defined: \'`WIDTH\'\nmodule UPCOUNTER_POSEDGE # (parameter SIZE=`WIDTH)\n                                           ^~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:92: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nmodule UPCOUNTER_POSEDGE # (parameter SIZE=`WIDTH)\n                                                 ^\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:95: syntax error, unexpected input, expecting IDENTIFIER or do or final\ninput wire [SIZE-1:0] Initial,\n^~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:96: syntax error, unexpected input, expecting IDENTIFIER or do or final\ninput wire Enable,\n^~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:97: syntax error, unexpected output, expecting IDENTIFIER or do or final\noutput reg [SIZE-1:0] Q\n^~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:98: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:183: Define or directive not defined: \'`WIDTH\'\nmodule MUXFULLPARALELL_3SEL_GENERIC # ( parameter SIZE=`WIDTH )\n                                                       ^~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:183: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nmodule MUXFULLPARALELL_3SEL_GENERIC # ( parameter SIZE=`WIDTH )\n                                                              ^\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:186: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [SIZE-1:0] I0, I1, I2, I3,I4, I5, I6, I7,\n ^~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:187: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output reg [SIZE-1:0] O\n ^~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:188: syntax error, unexpected \')\', expecting \',\' or \';\'\n );\n ^\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:211: Define or directive not defined: \'`WIDTH\'\nmodule MUXFULLPARALELL_4SEL_GENERIC # ( parameter SIZE=`WIDTH )\n                                                       ^~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:211: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nmodule MUXFULLPARALELL_4SEL_GENERIC # ( parameter SIZE=`WIDTH )\n                                                              ^\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:214: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [SIZE-1:0] I0, I1, I2, I3,I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15,\n ^~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:215: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output reg [SIZE-1:0] O\n ^~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:216: syntax error, unexpected \')\', expecting \',\' or \';\'\n );\n ^\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:248: Define or directive not defined: \'`WIDTH\'\nmodule MUXFULLPARALELL_5SEL_GENERIC # ( parameter SIZE=`WIDTH )\n                                                       ^~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:248: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nmodule MUXFULLPARALELL_5SEL_GENERIC # ( parameter SIZE=`WIDTH )\n                                                              ^\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:251: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [SIZE-1:0] I0, I1, I2, I3,I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15,\n ^~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:252: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [SIZE-1:0] I16, I17, I18, I19,I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31,\n ^~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:253: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output reg [SIZE-1:0] O\n ^~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:254: syntax error, unexpected \')\', expecting \',\' or \';\'\n );\n ^\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:302: Define or directive not defined: \'`WIDTH\'\nmodule MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )\n                                                       ^~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:302: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nmodule MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )\n                                                              ^\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:305: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire [SIZE-1:0]I0, I1, I2,I3,\n ^~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:306: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output reg [SIZE-1:0] O\n ^~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:307: syntax error, unexpected \')\', expecting \',\' or \';\'\n );\n ^\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:328: Define or directive not defined: \'`WIDTH\'\nmodule CIRCULAR_SHIFTLEFT_POSEDGE_EX # ( parameter SIZE=`WIDTH )\n                                                        ^~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:328: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nmodule CIRCULAR_SHIFTLEFT_POSEDGE_EX # ( parameter SIZE=`WIDTH )\n                                                               ^\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:330: syntax error, unexpected input, expecting IDENTIFIER or do or final\n  input wire Reset,\n  ^~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:331: syntax error, unexpected input, expecting IDENTIFIER or do or final\n  input wire[SIZE-1:0] Initial,\n  ^~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:332: syntax error, unexpected input, expecting IDENTIFIER or do or final\n  input wire      Enable,\n  ^~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:333: syntax error, unexpected output, expecting IDENTIFIER or do or final\n  output wire[SIZE-1:0] O\n  ^~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/collaterals.v:334: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module FFD_POSEDGE_SYNCRONOUS_RESET_INIT # ( parameter SIZE=`WIDTH )
(
	input wire				Clock,
	input wire				Reset,
	input wire				Enable,
	input wire [SIZE-1:0]   iInitial,
	input wire [SIZE-1:0]	D,
	output reg [SIZE-1:0]	Q
);


always @ (posedge Clock)
begin
	if ( Reset )
		Q <= iInitial;
	else
	begin
		if (Enable)
			Q <= D;
	end

end

endmodule
module FFD_POSEDGE_SYNCRONOUS_RESET_INIT # ( parameter SIZE=`WIDTH )
(
	input wire				Clock,
	input wire				Reset,
	input wire				Enable,
	input wire [SIZE-1:0]   iInitial,
	input wire [SIZE-1:0]	D,
	output reg [SIZE-1:0]	Q
);



always @ (posedge Clock)
begin
	if ( Reset )
		Q <= iInitial;
	else
	begin
		if (Enable)
			Q <= D;
	end

end

endmodule