data/full_repos/permissive/503053625/fpga_projects/SPGD/src/DAC_offset_to_twos.v
data/verilator_xmls/02be95ec-579e-423e-8c2b-2704a8880874.xml
module DAC_offset_to_twos
#(
	parameter WIRE_WIDTH = 14
)
(
    input [WIRE_WIDTH - 1:0] data_in,
	output [WIRE_WIDTH - 1:0] data_out
);

    reg [WIRE_WIDTH - 1:0] data_register1 = 14'h00000000;
    
    always @(data_in)
    begin

        data_register1 = data_in;








    end

    assign data_out = data_register1;
endmodule
module DAC_offset_to_twos
#(
	parameter WIRE_WIDTH = 14
)
(
    input [WIRE_WIDTH - 1:0] data_in,
	output [WIRE_WIDTH - 1:0] data_out
);


    reg [WIRE_WIDTH - 1:0] data_register1 = 14'h00000000;
    
    always @(data_in)
    begin

        data_register1 = data_in;








    end

    assign data_out = data_register1;
endmodule