data/full_repos/permissive/460468583/data/yosys/gatemate/cells_bb.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/460468583/data/yosys/gatemate/cells_bb.v:37: Multiple top level modules\n                                                                                         : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                         : ... Top module \'CC_PLL\'\nmodule CC_PLL #(\n       ^~~~~~\n                                                                                         : ... Top module \'CC_PLL_ADV\'\nmodule CC_PLL_ADV #(\n       ^~~~~~~~~~\n                                                                                         : ... Top module \'CC_SERDES\'\nmodule CC_SERDES #(\n       ^~~~~~~~~\n                                                                                         : ... Top module \'CC_CFG_CTRL\'\nmodule CC_CFG_CTRL(\n       ^~~~~~~~~~~\n                                                                                         : ... Top module \'CC_FIFO_40K\'\nmodule CC_FIFO_40K (\n       ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/460468583/data/yosys/gatemate/cells_bb.v:165: Operator VAR \'ALMOST_FULL_OFFSET\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'h0\' generates 12 bits.\n                                                                                       : ... In instance CC_FIFO_40K\n parameter [12:0] ALMOST_FULL_OFFSET = 12\'b0;\n                  ^~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/460468583/data/yosys/gatemate/cells_bb.v:166: Operator VAR \'ALMOST_EMPTY_OFFSET\' expects 13 bits on the Initial value, but Initial value\'s CONST \'12\'h0\' generates 12 bits.\n                                                                                       : ... In instance CC_FIFO_40K\n parameter [12:0] ALMOST_EMPTY_OFFSET = 12\'b0;\n                  ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 warning(s)\n'
module CC_FIFO_40K (
	output A_ECC_1B_ERR,
	output B_ECC_1B_ERR,
	output A_ECC_2B_ERR,
	output B_ECC_2B_ERR,

	output [39:0] A_DO,
	output [39:0] B_DO,
	(* clkbuf_sink *)
	input  A_CLK,
	input  A_EN,

	input  [39:0] A_DI,
	input  [39:0] B_DI,
	input  [39:0] A_BM,
	input  [39:0] B_BM,
	(* clkbuf_sink *)
	input  B_CLK,
	input  B_EN,
	input  B_WE,

	input  F_RST_N,
	input  [12:0] F_ALMOST_FULL_OFFSET,
	input  [12:0] F_ALMOST_EMPTY_OFFSET,

	output F_FULL,
	output F_EMPTY,
	output F_ALMOST_FULL,
	output F_ALMOST_EMPTY,
	output F_RD_ERROR,
	output F_WR_ERROR,
	output [15:0] F_RD_PTR,
	output [15:0] F_WR_PTR
);

	parameter LOC = "UNPLACED";


	parameter [12:0] ALMOST_FULL_OFFSET = 12'b0;
	parameter [12:0] ALMOST_EMPTY_OFFSET = 12'b0;


	parameter A_WIDTH = 0;
	parameter B_WIDTH = 0;


	parameter RAM_MODE = "SDP";
	parameter FIFO_MODE = "SYNC";


	parameter A_CLK_INV = 1'b0;
	parameter B_CLK_INV = 1'b0;
	parameter A_EN_INV = 1'b0;
	parameter B_EN_INV = 1'b0;
	parameter A_WE_INV = 1'b0;
	parameter B_WE_INV = 1'b0;


	parameter A_DO_REG = 1'b0;
	parameter B_DO_REG = 1'b0;


	parameter A_ECC_EN  = 1'b0;
	parameter B_ECC_EN  = 1'b0;
endmodule
module CC_FIFO_40K (
	output A_ECC_1B_ERR,
	output B_ECC_1B_ERR,
	output A_ECC_2B_ERR,
	output B_ECC_2B_ERR,

	output [39:0] A_DO,
	output [39:0] B_DO,
	(* clkbuf_sink *)
	input  A_CLK,
	input  A_EN,

	input  [39:0] A_DI,
	input  [39:0] B_DI,
	input  [39:0] A_BM,
	input  [39:0] B_BM,
	(* clkbuf_sink *)
	input  B_CLK,
	input  B_EN,
	input  B_WE,

	input  F_RST_N,
	input  [12:0] F_ALMOST_FULL_OFFSET,
	input  [12:0] F_ALMOST_EMPTY_OFFSET,

	output F_FULL,
	output F_EMPTY,
	output F_ALMOST_FULL,
	output F_ALMOST_EMPTY,
	output F_RD_ERROR,
	output F_WR_ERROR,
	output [15:0] F_RD_PTR,
	output [15:0] F_WR_PTR
);


	parameter LOC = "UNPLACED";


	parameter [12:0] ALMOST_FULL_OFFSET = 12'b0;
	parameter [12:0] ALMOST_EMPTY_OFFSET = 12'b0;


	parameter A_WIDTH = 0;
	parameter B_WIDTH = 0;


	parameter RAM_MODE = "SDP";
	parameter FIFO_MODE = "SYNC";


	parameter A_CLK_INV = 1'b0;
	parameter B_CLK_INV = 1'b0;
	parameter A_EN_INV = 1'b0;
	parameter B_EN_INV = 1'b0;
	parameter A_WE_INV = 1'b0;
	parameter B_WE_INV = 1'b0;


	parameter A_DO_REG = 1'b0;
	parameter B_DO_REG = 1'b0;


	parameter A_ECC_EN  = 1'b0;
	parameter B_ECC_EN  = 1'b0;
endmodule