data/full_repos/permissive/507307707/generated/D_FIFO.v
data/verilator_xmls/0c787bbb-eb75-4cbd-b951-a8ff4fda6882.xml
module D_FIFO(
  input         clock,
  input         reset,
  input  [31:0] io_din,
  input         io_din_v,
  input         io_dout_r,
  output        io_din_r,
  output [31:0] io_dout,
  output        io_dout_v
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
`endif
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
`endif
  reg [31:0] memory [0:3];
  wire  memory_io_dout_MPORT_en;
  wire [1:0] memory_io_dout_MPORT_addr;
  wire [31:0] memory_io_dout_MPORT_data;
  wire [31:0] memory_MPORT_data;
  wire [1:0] memory_MPORT_addr;
  wire  memory_MPORT_mask;
  wire  memory_MPORT_en;
  reg  memory_io_dout_MPORT_en_pipe_0;
  reg [1:0] memory_io_dout_MPORT_addr_pipe_0;
  reg [3:0] write_pointer;
  reg [3:0] read_pointer;
  reg [3:0] num_data;
  wire  full = num_data == 4'h4;
  wire  _T = ~full;
  wire  wr_en = io_din_v & _T;
  wire [3:0] _num_data_T_1 = num_data + 4'h1;
  wire [2:0] _T_5 = 3'h4 - 3'h1;
  wire [3:0] _GEN_19 = {{1'd0}, _T_5};
  wire [3:0] _write_pointer_T_1 = write_pointer + 4'h1;
  wire  empty = num_data == 4'h0;
  wire  _T_7 = ~empty;
  wire  rd_en = io_dout_r & _T_7;
  wire [3:0] _num_data_T_3 = num_data - 4'h1;
  wire [3:0] _read_pointer_T_1 = read_pointer + 4'h1;
  assign memory_io_dout_MPORT_en = memory_io_dout_MPORT_en_pipe_0;
  assign memory_io_dout_MPORT_addr = memory_io_dout_MPORT_addr_pipe_0;
  assign memory_io_dout_MPORT_data = memory[memory_io_dout_MPORT_addr];
  assign memory_MPORT_data = io_din;
  assign memory_MPORT_addr = write_pointer[1:0];
  assign memory_MPORT_mask = 1'h1;
  assign memory_MPORT_en = _T & wr_en;
  assign io_din_r = ~full;
  assign io_dout = ~empty & rd_en ? memory_io_dout_MPORT_data : 32'h0;
  assign io_dout_v = ~empty & rd_en;
  always @(posedge clock) begin
    if (memory_MPORT_en & memory_MPORT_mask) begin
      memory[memory_MPORT_addr] <= memory_MPORT_data;
    end
    memory_io_dout_MPORT_en_pipe_0 <= _T_7 & rd_en;
    if (_T_7 & rd_en) begin
      memory_io_dout_MPORT_addr_pipe_0 <= read_pointer[1:0];
    end
    if (reset) begin
      write_pointer <= 4'h0;
    end else if (~full & wr_en) begin
      if (write_pointer == _GEN_19) begin
        write_pointer <= 4'h0;
      end else begin
        write_pointer <= _write_pointer_T_1;
      end
    end else begin
      write_pointer <= 4'h0;
    end
    if (reset) begin
      read_pointer <= 4'h0;
    end else if (~empty & rd_en) begin
      if (read_pointer == _GEN_19) begin
        read_pointer <= 4'h0;
      end else begin
        read_pointer <= _read_pointer_T_1;
      end
    end else begin
      read_pointer <= 4'h0;
    end
    if (reset) begin
      num_data <= 4'h0;
    end else if (~empty & rd_en) begin
      num_data <= _num_data_T_3;
    end else if (~full & wr_en) begin
      num_data <= _num_data_T_1;
    end else begin
      num_data <= 4'h0;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 4; initvar = initvar+1)
    memory[initvar] = _RAND_0[31:0];
`endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_1 = {1{`RANDOM}};
  memory_io_dout_MPORT_en_pipe_0 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  memory_io_dout_MPORT_addr_pipe_0 = _RAND_2[1:0];
  _RAND_3 = {1{`RANDOM}};
  write_pointer = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  read_pointer = _RAND_4[3:0];
  _RAND_5 = {1{`RANDOM}};
  num_data = _RAND_5[3:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module D_FIFO(
  input         clock,
  input         reset,
  input  [31:0] io_din,
  input         io_din_v,
  input         io_dout_r,
  output        io_din_r,
  output [31:0] io_dout,
  output        io_dout_v
);

`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
`endif
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
`endif
  reg [31:0] memory [0:3];
  wire  memory_io_dout_MPORT_en;
  wire [1:0] memory_io_dout_MPORT_addr;
  wire [31:0] memory_io_dout_MPORT_data;
  wire [31:0] memory_MPORT_data;
  wire [1:0] memory_MPORT_addr;
  wire  memory_MPORT_mask;
  wire  memory_MPORT_en;
  reg  memory_io_dout_MPORT_en_pipe_0;
  reg [1:0] memory_io_dout_MPORT_addr_pipe_0;
  reg [3:0] write_pointer;
  reg [3:0] read_pointer;
  reg [3:0] num_data;
  wire  full = num_data == 4'h4;
  wire  _T = ~full;
  wire  wr_en = io_din_v & _T;
  wire [3:0] _num_data_T_1 = num_data + 4'h1;
  wire [2:0] _T_5 = 3'h4 - 3'h1;
  wire [3:0] _GEN_19 = {{1'd0}, _T_5};
  wire [3:0] _write_pointer_T_1 = write_pointer + 4'h1;
  wire  empty = num_data == 4'h0;
  wire  _T_7 = ~empty;
  wire  rd_en = io_dout_r & _T_7;
  wire [3:0] _num_data_T_3 = num_data - 4'h1;
  wire [3:0] _read_pointer_T_1 = read_pointer + 4'h1;
  assign memory_io_dout_MPORT_en = memory_io_dout_MPORT_en_pipe_0;
  assign memory_io_dout_MPORT_addr = memory_io_dout_MPORT_addr_pipe_0;
  assign memory_io_dout_MPORT_data = memory[memory_io_dout_MPORT_addr];
  assign memory_MPORT_data = io_din;
  assign memory_MPORT_addr = write_pointer[1:0];
  assign memory_MPORT_mask = 1'h1;
  assign memory_MPORT_en = _T & wr_en;
  assign io_din_r = ~full;
  assign io_dout = ~empty & rd_en ? memory_io_dout_MPORT_data : 32'h0;
  assign io_dout_v = ~empty & rd_en;
  always @(posedge clock) begin
    if (memory_MPORT_en & memory_MPORT_mask) begin
      memory[memory_MPORT_addr] <= memory_MPORT_data;
    end
    memory_io_dout_MPORT_en_pipe_0 <= _T_7 & rd_en;
    if (_T_7 & rd_en) begin
      memory_io_dout_MPORT_addr_pipe_0 <= read_pointer[1:0];
    end
    if (reset) begin
      write_pointer <= 4'h0;
    end else if (~full & wr_en) begin
      if (write_pointer == _GEN_19) begin
        write_pointer <= 4'h0;
      end else begin
        write_pointer <= _write_pointer_T_1;
      end
    end else begin
      write_pointer <= 4'h0;
    end
    if (reset) begin
      read_pointer <= 4'h0;
    end else if (~empty & rd_en) begin
      if (read_pointer == _GEN_19) begin
        read_pointer <= 4'h0;
      end else begin
        read_pointer <= _read_pointer_T_1;
      end
    end else begin
      read_pointer <= 4'h0;
    end
    if (reset) begin
      num_data <= 4'h0;
    end else if (~empty & rd_en) begin
      num_data <= _num_data_T_3;
    end else if (~full & wr_en) begin
      num_data <= _num_data_T_1;
    end else begin
      num_data <= 4'h0;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 4; initvar = initvar+1)
    memory[initvar] = _RAND_0[31:0];
`endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_1 = {1{`RANDOM}};
  memory_io_dout_MPORT_en_pipe_0 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  memory_io_dout_MPORT_addr_pipe_0 = _RAND_2[1:0];
  _RAND_3 = {1{`RANDOM}};
  write_pointer = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  read_pointer = _RAND_4[3:0];
  _RAND_5 = {1{`RANDOM}};
  num_data = _RAND_5[3:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule