data/full_repos/permissive/493019833/test/testcase/firrtl/Complex2R1WSMem/reference/Complex2R1WSMem.v
data/verilator_xmls/28864c4a-cb47-4a3c-afc3-7052dc080c91.xml
module Complex2R1WSMem(
    input clock,
    input reset,
    input [3:0] io_rdAddr,
    output [7:0] io_rdData,
    input [3:0] io_rdAddr2,
    output [7:0] io_rdData2,
    input io_wrEna,
    input [7:0] io_wrData,
    input [3:0] io_wrAddr
);
    wire [7:0] mem__T_21_data;
    wire mem__T_21_clk;
    wire mem__T_21_en;
    wire [3:0] mem__T_21_addr;
    wire [7:0] mem__T_22_data;
    wire mem__T_22_clk;
    wire mem__T_22_en;
    wire [3:0] mem__T_22_addr;
    wire mem__T_23_clk;
    wire mem__T_23_en;
    wire mem__T_23_mask;
    wire [3:0] mem__T_23_addr;
    wire [7:0] mem__T_23_data;
    wire [15:0] mem_read_datas;
    wire [1:0] mem_read_clks;
    wire [1:0] mem_read_ens;
    wire [7:0] mem_read_addrs;
    wire mem_write_clks;
    wire mem_write_ens;
    wire mem_write_masks;
    wire [3:0] mem_write_addrs;
    wire [7:0] mem_write_datas;
    BITS #(.width(16), .high(7), .low(0)) bits_1 (
        .y(mem__T_21_data),
        .in(mem_read_datas)
    );
    BITS #(.width(16), .high(15), .low(8)) bits_2 (
        .y(mem__T_22_data),
        .in(mem_read_datas)
    );
    CAT #(.width_a(1), .width_b(1)) cat_3 (
        .y(mem_read_clks),
        .a(mem__T_22_clk),
        .b(mem__T_21_clk)
    );
    CAT #(.width_a(1), .width_b(1)) cat_4 (
        .y(mem_read_ens),
        .a(mem__T_22_en),
        .b(mem__T_21_en)
    );
    CAT #(.width_a(4), .width_b(4)) cat_5 (
        .y(mem_read_addrs),
        .a(mem__T_22_addr),
        .b(mem__T_21_addr)
    );
    assign mem_write_datas = mem__T_23_data;
    assign mem_write_clks = mem__T_23_clk;
    assign mem_write_ens = mem__T_23_en;
    assign mem_write_addrs = mem__T_23_addr;
    assign mem_write_masks = mem__T_23_mask;
    MRMWMEM #(.depth(16), .addrbits(4), .width(8), .readernum(2), .writernum(1), .isSyncRead(1)) mem (
        .read_datas(mem_read_datas),
        .read_clks(mem_read_clks),
        .read_ens(mem_read_ens),
        .read_addrs(mem_read_addrs),
        .write_clks(mem_write_clks),
        .write_ens(mem_write_ens),
        .write_masks(mem_write_masks),
        .write_addrs(mem_write_addrs),
        .write_datas(mem_write_datas)
    );
    assign mem__T_21_addr = io_rdAddr;
    assign mem__T_21_en = 1'h1;
    assign mem__T_21_clk = clock;
    assign mem__T_22_addr = io_rdAddr2;
    assign mem__T_22_en = 1'h1;
    assign mem__T_22_clk = clock;
    assign mem__T_23_addr = io_wrAddr;
    assign mem__T_23_en = io_wrEna;
    assign mem__T_23_clk = clock;
    assign mem__T_23_mask = 1'h1;
    assign io_rdData = mem__T_21_data;
    assign io_rdData2 = mem__T_22_data;
    assign mem__T_23_data = io_wrData;
endmodule
module Complex2R1WSMem(
    input clock,
    input reset,
    input [3:0] io_rdAddr,
    output [7:0] io_rdData,
    input [3:0] io_rdAddr2,
    output [7:0] io_rdData2,
    input io_wrEna,
    input [7:0] io_wrData,
    input [3:0] io_wrAddr
);

    wire [7:0] mem__T_21_data;
    wire mem__T_21_clk;
    wire mem__T_21_en;
    wire [3:0] mem__T_21_addr;
    wire [7:0] mem__T_22_data;
    wire mem__T_22_clk;
    wire mem__T_22_en;
    wire [3:0] mem__T_22_addr;
    wire mem__T_23_clk;
    wire mem__T_23_en;
    wire mem__T_23_mask;
    wire [3:0] mem__T_23_addr;
    wire [7:0] mem__T_23_data;
    wire [15:0] mem_read_datas;
    wire [1:0] mem_read_clks;
    wire [1:0] mem_read_ens;
    wire [7:0] mem_read_addrs;
    wire mem_write_clks;
    wire mem_write_ens;
    wire mem_write_masks;
    wire [3:0] mem_write_addrs;
    wire [7:0] mem_write_datas;
    BITS #(.width(16), .high(7), .low(0)) bits_1 (
        .y(mem__T_21_data),
        .in(mem_read_datas)
    );
    BITS #(.width(16), .high(15), .low(8)) bits_2 (
        .y(mem__T_22_data),
        .in(mem_read_datas)
    );
    CAT #(.width_a(1), .width_b(1)) cat_3 (
        .y(mem_read_clks),
        .a(mem__T_22_clk),
        .b(mem__T_21_clk)
    );
    CAT #(.width_a(1), .width_b(1)) cat_4 (
        .y(mem_read_ens),
        .a(mem__T_22_en),
        .b(mem__T_21_en)
    );
    CAT #(.width_a(4), .width_b(4)) cat_5 (
        .y(mem_read_addrs),
        .a(mem__T_22_addr),
        .b(mem__T_21_addr)
    );
    assign mem_write_datas = mem__T_23_data;
    assign mem_write_clks = mem__T_23_clk;
    assign mem_write_ens = mem__T_23_en;
    assign mem_write_addrs = mem__T_23_addr;
    assign mem_write_masks = mem__T_23_mask;
    MRMWMEM #(.depth(16), .addrbits(4), .width(8), .readernum(2), .writernum(1), .isSyncRead(1)) mem (
        .read_datas(mem_read_datas),
        .read_clks(mem_read_clks),
        .read_ens(mem_read_ens),
        .read_addrs(mem_read_addrs),
        .write_clks(mem_write_clks),
        .write_ens(mem_write_ens),
        .write_masks(mem_write_masks),
        .write_addrs(mem_write_addrs),
        .write_datas(mem_write_datas)
    );
    assign mem__T_21_addr = io_rdAddr;
    assign mem__T_21_en = 1'h1;
    assign mem__T_21_clk = clock;
    assign mem__T_22_addr = io_rdAddr2;
    assign mem__T_22_en = 1'h1;
    assign mem__T_22_clk = clock;
    assign mem__T_23_addr = io_wrAddr;
    assign mem__T_23_en = io_wrEna;
    assign mem__T_23_clk = clock;
    assign mem__T_23_mask = 1'h1;
    assign io_rdData = mem__T_21_data;
    assign io_rdData2 = mem__T_22_data;
    assign mem__T_23_data = io_wrData;
endmodule