data/full_repos/permissive/430359604/Design/netlist/usr_nbit.v
data/verilator_xmls/9efe4e04-fb74-42c3-bf46-0b872de124b9.xml
module usr_nbit(select, parallelin, left, right, parallelout, clk, rst);
  parameter size = 4;
  input [1:0]select;
  input [size-1:0] parallelin;
  input left;
  input right;
  input clk,rst;
  output [size-1:0] parallelout;

genvar i;

universal_shift_register_1bit m0(.select(select),.parallelin(parallelin[0]),.left(left),.right(parallelout[1]),.parallelout(parallelout[0]),.clk(clk),.rst(rst));

generate for (i=1;i<=size-2;i=i+1)
	begin
		universal_shift_register_1bit m1(.select(select),.parallelin(parallelin[i]),.left(parallelout[i-1]),.right(parallelout[i+1]),.parallelout(parallelout[i]),.clk(clk),.rst(rst));
  	end
endgenerate

universal_shift_register_1bit mn(.select(select),.parallelin(parallelin[size-1]),.left(parallelout[size-2]),.right(right),.parallelout(parallelout[size-1]),.clk(clk),.rst(rst));
endmodule
module usr_nbit(select, parallelin, left, right, parallelout, clk, rst);

  parameter size = 4;
  input [1:0]select;
  input [size-1:0] parallelin;
  input left;
  input right;
  input clk,rst;
  output [size-1:0] parallelout;

genvar i;

universal_shift_register_1bit m0(.select(select),.parallelin(parallelin[0]),.left(left),.right(parallelout[1]),.parallelout(parallelout[0]),.clk(clk),.rst(rst));

generate for (i=1;i<=size-2;i=i+1)
	begin
		universal_shift_register_1bit m1(.select(select),.parallelin(parallelin[i]),.left(parallelout[i-1]),.right(parallelout[i+1]),.parallelout(parallelout[i]),.clk(clk),.rst(rst));
  	end
endgenerate

universal_shift_register_1bit mn(.select(select),.parallelin(parallelin[size-1]),.left(parallelout[size-2]),.right(right),.parallelout(parallelout[size-1]),.clk(clk),.rst(rst));
endmodule