data/full_repos/permissive/430337995/unibuf_systolic_tb/src/data_fetch.v
1: b'%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/data_fetch.v:1: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/430337995/unibuf_systolic_tb/src,data/full_repos/permissive/430337995/define.v\n             data/full_repos/permissive/430337995/unibuf_systolic_tb/src,data/full_repos/permissive/430337995/define.v.v\n             data/full_repos/permissive/430337995/unibuf_systolic_tb/src,data/full_repos/permissive/430337995/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/data_fetch.v:26: Define or directive not defined: \'`WORD_ADDR_BITS\'\ninput [`WORD_ADDR_BITS-1:0]         src_addr;\n       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/data_fetch.v:27: Define or directive not defined: \'`DATA_MAX_BITS\'\ninput [`DATA_MAX_BITS-1:0]          channel;\n       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/data_fetch.v:29: Define or directive not defined: \'`DATA_MAX_BITS\'\ninput [`DATA_MAX_BITS-1:0]          row;\n       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/data_fetch.v:31: Define or directive not defined: \'`DATA_MAX_BITS\'\ninput [`DATA_MAX_BITS-1:0]          col;\n       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/data_fetch.v:34: Define or directive not defined: \'`WORD_ADDR_BITS\'\noutput reg [`WORD_ADDR_BITS-1:0]    addr_out;\n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/data_fetch.v:36: Define or directive not defined: \'`DATA_MAX_BITS\'\noutput  [`DATA_MAX_BITS-1:0]        row_index;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/data_fetch.v:37: Define or directive not defined: \'`DATA_MAX_BITS\'\noutput  [`DATA_MAX_BITS-1:0]        channel_index;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/data_fetch.v:38: Define or directive not defined: \'`DATA_MAX_BITS\'\noutput  [`DATA_MAX_BITS-1:0]        col_index;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/data_fetch.v:43: Define or directive not defined: \'`DATA_MAX_BITS\'\nreg [`DATA_MAX_BITS-1:0]        row_index_reg;\n     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/data_fetch.v:44: Define or directive not defined: \'`DATA_MAX_BITS\'\nreg [`DATA_MAX_BITS-1:0]        channel_index_reg;\n     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/data_fetch.v:45: Define or directive not defined: \'`DATA_MAX_BITS\'\nreg [`DATA_MAX_BITS-1:0]        col_index_reg;\n     ^~~~~~~~~~~~~~\n%Error: Exiting due to 12 error(s)\n'
module DataFetch(
    clk,
    rst,
    data_ready,
    fetch,
    src_addr,
    channel,
    channel_index_rst,
    channel_index,
    row,
    row_index_rst,
    row_index,
    col,
    col_index_rst,
    col_index,
    wen,
    addr_out,
    data_NA
);

input                               clk;
input                               rst;
input                               fetch;
input                               data_ready;
input [`WORD_ADDR_BITS-1:0]         src_addr;
input [`DATA_MAX_BITS-1:0]          channel;
input                               channel_index_rst;
input [`DATA_MAX_BITS-1:0]          row;
input                               row_index_rst;
input [`DATA_MAX_BITS-1:0]          col;
input                               col_index_rst;
output                              wen;
output reg [`WORD_ADDR_BITS-1:0]    addr_out;
output reg                          data_NA;
output  [`DATA_MAX_BITS-1:0]        row_index;
output  [`DATA_MAX_BITS-1:0]        channel_index;
output  [`DATA_MAX_BITS-1:0]        col_index;




reg [`DATA_MAX_BITS-1:0]        row_index_reg;
reg [`DATA_MAX_BITS-1:0]        channel_index_reg;
reg [`DATA_MAX_BITS-1:0]        col_index_reg;



assign wen = 1'b0;
assign row_index = row_index_reg;
assign channel_index = channel_index_reg;
assign col_index = col_index_reg;


always@(posedge clk or negedge rst) begin
    if(!rst) begin
        row_index_reg <= 8'd0;
        channel_index_reg <= 8'd0;
        addr_out <= 8'd0;
        data_NA <= 1'b0;
    end else begin
        if(data_ready & fetch & !data_NA) begin
            addr_out <= (src_addr) + (channel_index_reg * row)  +  row_index_reg;
            if(!row_index_rst) begin
                row_index_reg <= (row_index_reg == row - 1) ? 8'd0 : row_index_reg + 8'd1;
            end else begin
                row_index_reg <= 8'd0;
            end
            if(!channel_index_rst) begin
                channel_index_reg <= (row_index_reg == row - 1) ? ((channel_index_reg == channel -1) ? 8'd0 : channel_index_reg + 8'd1) : channel_index_reg;
            end else begin
                channel_index_reg <= 8'd0;
            end
            data_NA <= ((channel_index_reg == channel -1) && (row_index_reg == row -1) && (~channel_index_rst) && (~row_index_rst) ) ? 1'b1 : 1'b0;
        end else if(!data_ready) begin
            row_index_reg <= 8'd0;
            channel_index_reg <= 8'd0;
            addr_out <= 8'd0;
            data_NA <= 0;
        end 
    end
end


endmodule
module DataFetch(
    clk,
    rst,
    data_ready,
    fetch,
    src_addr,
    channel,
    channel_index_rst,
    channel_index,
    row,
    row_index_rst,
    row_index,
    col,
    col_index_rst,
    col_index,
    wen,
    addr_out,
    data_NA
);


input                               clk;
input                               rst;
input                               fetch;
input                               data_ready;
input [`WORD_ADDR_BITS-1:0]         src_addr;
input [`DATA_MAX_BITS-1:0]          channel;
input                               channel_index_rst;
input [`DATA_MAX_BITS-1:0]          row;
input                               row_index_rst;
input [`DATA_MAX_BITS-1:0]          col;
input                               col_index_rst;
output                              wen;
output reg [`WORD_ADDR_BITS-1:0]    addr_out;
output reg                          data_NA;
output  [`DATA_MAX_BITS-1:0]        row_index;
output  [`DATA_MAX_BITS-1:0]        channel_index;
output  [`DATA_MAX_BITS-1:0]        col_index;




reg [`DATA_MAX_BITS-1:0]        row_index_reg;
reg [`DATA_MAX_BITS-1:0]        channel_index_reg;
reg [`DATA_MAX_BITS-1:0]        col_index_reg;



assign wen = 1'b0;
assign row_index = row_index_reg;
assign channel_index = channel_index_reg;
assign col_index = col_index_reg;


always@(posedge clk or negedge rst) begin
    if(!rst) begin
        row_index_reg <= 8'd0;
        channel_index_reg <= 8'd0;
        addr_out <= 8'd0;
        data_NA <= 1'b0;
    end else begin
        if(data_ready & fetch & !data_NA) begin
            addr_out <= (src_addr) + (channel_index_reg * row)  +  row_index_reg;
            if(!row_index_rst) begin
                row_index_reg <= (row_index_reg == row - 1) ? 8'd0 : row_index_reg + 8'd1;
            end else begin
                row_index_reg <= 8'd0;
            end
            if(!channel_index_rst) begin
                channel_index_reg <= (row_index_reg == row - 1) ? ((channel_index_reg == channel -1) ? 8'd0 : channel_index_reg + 8'd1) : channel_index_reg;
            end else begin
                channel_index_reg <= 8'd0;
            end
            data_NA <= ((channel_index_reg == channel -1) && (row_index_reg == row -1) && (~channel_index_rst) && (~row_index_rst) ) ? 1'b1 : 1'b0;
        end else if(!data_ready) begin
            row_index_reg <= 8'd0;
            channel_index_reg <= 8'd0;
            addr_out <= 8'd0;
            data_NA <= 0;
        end 
    end
end


endmodule