data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/latch_002.v
data/verilator_xmls/65211387-210e-4920-97ec-68f49cddfe89.xml
module latch_002
  (dword, sel, st, vect);
   output reg [63:0] dword;
   input wire [7:0]  vect;
   input wire [7:0]  sel;
   input wire        st;
   
   always @(*) begin
      if (st)
	dword[8*sel +:8] <= vect[7:0];
   end
endmodule
module latch_002
  (dword, sel, st, vect);

   output reg [63:0] dword;
   input wire [7:0]  vect;
   input wire [7:0]  sel;
   input wire        st;
   
   always @(*) begin
      if (st)
	dword[8*sel +:8] <= vect[7:0];
   end
endmodule