data/full_repos/permissive/423958267/lab03/lab03.srcs/sources_1/new/SinglePulser.v
data/verilator_xmls/2eb86b7e-e632-4d45-a7d1-616337d75d6e.xml
module SinglePulser(
    output reg out,
    input in,
    input clock
);
reg current;

initial
begin
    current <= 0;
    out <= 0;
end

always @(posedge clock)
begin
    if(in && !current)
    begin
        current <= 1;
        out <= 1;
    end
    else if(!in && current)
    begin
        current <= 0;
        out <= 0;
    end 
    else
    begin
        out <= 0;
    end
end

endmodule
module SinglePulser(
    output reg out,
    input in,
    input clock
);

reg current;

initial
begin
    current <= 0;
    out <= 0;
end

always @(posedge clock)
begin
    if(in && !current)
    begin
        current <= 1;
        out <= 1;
    end
    else if(!in && current)
    begin
        current <= 0;
        out <= 0;
    end 
    else
    begin
        out <= 0;
    end
end

endmodule