data/full_repos/permissive/460328193/ipa_proj_seq/Register.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/460328193/ipa_proj_seq/Register.v:14: Little bit endian vector: MSB < LSB of bit range: 0:63\nreg [0:63]reg_store[14:0];\n    ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Register(icode,Cnd,rA,rB,valA,valB,valE,valM,clk);

input [3:0] icode;
input Cnd;
input [3:0] rA;
input [3:0] rB;
input [63:0] valE;
input [63:0] valM;
input clk;
output reg [63:0] valA;
output reg [63:0] valB;
  

reg [0:63]reg_store[14:0];

initial 
    begin
		$readmemh("REG_MEM.txt", reg_store, 0, 14);
	end

reg [3:0] srcA,srcB,destM,destE;

always @(*)    
begin
    if(icode==4'h0)
	begin
		srcA<=4'hF;
        srcB<=4'hF;
	end
	else if(icode==4'h1)
	begin
		srcA<=4'hF;
        srcB<=4'hF;
	end
	else if(icode==4'h2)
	begin
		srcA<=rA;
        srcB<=4'hF;
	end
	else if(icode==4'h3)
	begin
		srcA<=4'hF;
        srcB<=4'hF;
	end
	else if(icode==4'h4)
	begin
		srcA<=rA;
        srcB<=rB;
	end	
	else if(icode==4'h5)
	begin
		srcA<=4'hF;
        srcB<=rB;
	end
	else if(icode==4'h6)
	begin
		srcA<=rA;
        srcB<=rB;
	end
	else if(icode==4'h7)
	begin
		srcA<=4'hF;
        srcB<=4'hF;
	end
	else if(icode==4'h8)
	begin
		srcA<=4'hF;
        srcB<=4;
	end
	else if(icode==4'h9)
	begin
		srcA<=4;
        srcB<=4;
	end
	else if(icode==4'hA)
	begin
		srcA<=rA;
        srcB<=4;
	end
	else if(icode==4'hB)
	begin
		srcA<=4;
        srcB<=4;
	end
    if(srcA!=4'hF)
        valA<=reg_store[srcA];
    if(srcB!=4'hF)
        valB<=reg_store[srcB];
end

always @(*)  
begin
    if(icode==4'h0)
	begin
		destM<=4'hF;
        destE<=4'hF;
	end
	else if(icode==4'h1)
	begin
		destM<=4'hF;
        destE<=4'hF;
	end
	else if((icode==4'h2) && (Cnd==1'b1))
	begin
		destM<=4'hF;
        destE<=rB;
	end
	else if(icode==4'h3)
	begin
		destM<=4'hF;
        destE<=rB;
	end
	else if(icode==4'h4)
	begin
		destM<=4'hF;
        destE<=4'hF;
	end	
	else if(icode==4'h5)
	begin
		destM<=rA;
        destE<=4'hF;
	end
	else if(icode==4'h6)
	begin
		destM<=4'hF;
        destE<=rB;
	end
	else if(icode==4'h7)
	begin
		destM<=4'hF;
        destE<=4'hF;
	end
	else if(icode==4'h8)
	begin
		destM<=4'hF;
        destE<=4;
	end
	else if(icode==4'h9)
	begin
		destM<=4'hF;
        destE<=4;
	end
	else if(icode==4'hA)
	begin
		destM<=4'hF;
        destE<=4;
	end
	else if(icode==4'hB)
	begin
		destM<=rA;
        destE<=4;
	end
end
always @(posedge clk)
begin
if(destE!=4'hF)
    begin
        reg_store[destE]<=valE;
        $writememh("REG_MEM.txt", reg_store, 0,14);
    end
if(destM!=4'hF)
    begin
        reg_store[destM]<=valM;
        $writememh("REG_MEM.txt", reg_store, 0,14);
    end
end
endmodule
module Register(icode,Cnd,rA,rB,valA,valB,valE,valM,clk);


input [3:0] icode;
input Cnd;
input [3:0] rA;
input [3:0] rB;
input [63:0] valE;
input [63:0] valM;
input clk;
output reg [63:0] valA;
output reg [63:0] valB;
  

reg [0:63]reg_store[14:0];

initial 
    begin
		$readmemh("REG_MEM.txt", reg_store, 0, 14);
	end

reg [3:0] srcA,srcB,destM,destE;

always @(*)    
begin
    if(icode==4'h0)
	begin
		srcA<=4'hF;
        srcB<=4'hF;
	end
	else if(icode==4'h1)
	begin
		srcA<=4'hF;
        srcB<=4'hF;
	end
	else if(icode==4'h2)
	begin
		srcA<=rA;
        srcB<=4'hF;
	end
	else if(icode==4'h3)
	begin
		srcA<=4'hF;
        srcB<=4'hF;
	end
	else if(icode==4'h4)
	begin
		srcA<=rA;
        srcB<=rB;
	end	
	else if(icode==4'h5)
	begin
		srcA<=4'hF;
        srcB<=rB;
	end
	else if(icode==4'h6)
	begin
		srcA<=rA;
        srcB<=rB;
	end
	else if(icode==4'h7)
	begin
		srcA<=4'hF;
        srcB<=4'hF;
	end
	else if(icode==4'h8)
	begin
		srcA<=4'hF;
        srcB<=4;
	end
	else if(icode==4'h9)
	begin
		srcA<=4;
        srcB<=4;
	end
	else if(icode==4'hA)
	begin
		srcA<=rA;
        srcB<=4;
	end
	else if(icode==4'hB)
	begin
		srcA<=4;
        srcB<=4;
	end
    if(srcA!=4'hF)
        valA<=reg_store[srcA];
    if(srcB!=4'hF)
        valB<=reg_store[srcB];
end

always @(*)  
begin
    if(icode==4'h0)
	begin
		destM<=4'hF;
        destE<=4'hF;
	end
	else if(icode==4'h1)
	begin
		destM<=4'hF;
        destE<=4'hF;
	end
	else if((icode==4'h2) && (Cnd==1'b1))
	begin
		destM<=4'hF;
        destE<=rB;
	end
	else if(icode==4'h3)
	begin
		destM<=4'hF;
        destE<=rB;
	end
	else if(icode==4'h4)
	begin
		destM<=4'hF;
        destE<=4'hF;
	end	
	else if(icode==4'h5)
	begin
		destM<=rA;
        destE<=4'hF;
	end
	else if(icode==4'h6)
	begin
		destM<=4'hF;
        destE<=rB;
	end
	else if(icode==4'h7)
	begin
		destM<=4'hF;
        destE<=4'hF;
	end
	else if(icode==4'h8)
	begin
		destM<=4'hF;
        destE<=4;
	end
	else if(icode==4'h9)
	begin
		destM<=4'hF;
        destE<=4;
	end
	else if(icode==4'hA)
	begin
		destM<=4'hF;
        destE<=4;
	end
	else if(icode==4'hB)
	begin
		destM<=rA;
        destE<=4;
	end
end
always @(posedge clk)
begin
if(destE!=4'hF)
    begin
        reg_store[destE]<=valE;
        $writememh("REG_MEM.txt", reg_store, 0,14);
    end
if(destM!=4'hF)
    begin
        reg_store[destM]<=valM;
        $writememh("REG_MEM.txt", reg_store, 0,14);
    end
end
endmodule