data/full_repos/permissive/511377659/iverilog_deinter_22/sram.v
data/verilator_xmls/e1888ff7-534b-4645-93da-84f1f80eaf5a.xml
module SRAM
#(parameter WORDSIZE = 11)
(
    input NWRT,
    input [WORDSIZE-1:0] DIN,
    input [10-1:0] RA,
    input [4-1:0] CA,
    input NCE,
    input CK,
    output [WORDSIZE-1:0] DO 
);

syncRAM MEM(DIN, DO, {RA, CA}, ~NCE, ~NWRT, NWRT, CK);

endmodule
module SRAM
#(parameter WORDSIZE = 11)
(
    input NWRT,
    input [WORDSIZE-1:0] DIN,
    input [10-1:0] RA,
    input [4-1:0] CA,
    input NCE,
    input CK,
    output [WORDSIZE-1:0] DO 
);


syncRAM MEM(DIN, DO, {RA, CA}, ~NCE, ~NWRT, NWRT, CK);

endmodule