data/full_repos/permissive/420117502/Basic/2_Freq_Divider/tb.v
1: b'%Error: data/full_repos/permissive/420117502/Basic/2_Freq_Divider/tb.v:11: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("dumpfile.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/420117502/Basic/2_Freq_Divider/tb.v:12: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/2_Freq_Divider/tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/2_Freq_Divider/tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clk<=~clk;\n           ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb ();
    reg clk;
    wire clk_out;
    reg [31:0] N;
    FD3 fd(
        .clk(clk),
        .clk_div(clk_out)
    );
    initial begin
        $dumpfile("dumpfile.vcd");
        $dumpvars;
        clk<=1'b0;
        #20
        $finish;
    end
    always #1 clk<=~clk;
endmodule
module tb ();

    reg clk;
    wire clk_out;
    reg [31:0] N;
    FD3 fd(
        .clk(clk),
        .clk_div(clk_out)
    );
    initial begin
        $dumpfile("dumpfile.vcd");
        $dumpvars;
        clk<=1'b0;
        #20
        $finish;
    end
    always #1 clk<=~clk;
endmodule