data/full_repos/permissive/450069022/hardware/src/iob-cache.v
1: b'%Error: data/full_repos/permissive/450069022/hardware/src/iob-cache.v:2: Cannot find include file: iob-cache.vh\n`include "iob-cache.vh" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/450069022/hardware/src,data/full_repos/permissive/450069022/iob-cache.vh\n             data/full_repos/permissive/450069022/hardware/src,data/full_repos/permissive/450069022/iob-cache.vh.v\n             data/full_repos/permissive/450069022/hardware/src,data/full_repos/permissive/450069022/iob-cache.vh.sv\n             iob-cache.vh\n             iob-cache.vh.v\n             iob-cache.vh.sv\n             obj_dir/iob-cache.vh\n             obj_dir/iob-cache.vh.v\n             obj_dir/iob-cache.vh.sv\n%Error: data/full_repos/permissive/450069022/hardware/src/iob-cache.v:18: Define or directive not defined: \'`PLRU_mru\'\n    parameter REP_POLICY = `PLRU_mru,  \n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/450069022/hardware/src/iob-cache.v:18: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    parameter REP_POLICY = `PLRU_mru,  \n                                    ^\n%Error: data/full_repos/permissive/450069022/hardware/src/iob-cache.v:21: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter FE_NBYTES  = FE_DATA_W/8,         \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/450069022/hardware/src/iob-cache.v:22: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter FE_BYTE_W  = $clog2(FE_NBYTES),  \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/450069022/hardware/src/iob-cache.v:25: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter BE_ADDR_W = FE_ADDR_W,  \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/450069022/hardware/src/iob-cache.v:26: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter BE_DATA_W = FE_DATA_W,  \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/450069022/hardware/src/iob-cache.v:27: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter BE_NBYTES = BE_DATA_W/8,  \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/450069022/hardware/src/iob-cache.v:28: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter BE_BYTE_W = $clog2(BE_NBYTES),  \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/450069022/hardware/src/iob-cache.v:30: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter LINE2MEM_W = WORD_OFF_W-$clog2(BE_DATA_W/FE_DATA_W), \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/450069022/hardware/src/iob-cache.v:33: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter WRITE_POL = `WRITE_THROUGH,  \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/450069022/hardware/src/iob-cache.v:33: Define or directive not defined: \'`WRITE_THROUGH\'\n    parameter WRITE_POL = `WRITE_THROUGH,  \n                          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/450069022/hardware/src/iob-cache.v:33: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    parameter WRITE_POL = `WRITE_THROUGH,  \n                                        ^\n%Error: data/full_repos/permissive/450069022/hardware/src/iob-cache.v:37: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter CTRL_CNT = 0   \n    ^~~~~~~~~\n%Error: data/full_repos/permissive/450069022/hardware/src/iob-cache.v:38: syntax error, unexpected \')\', expecting \';\'\n    ) \n    ^\n%Error: data/full_repos/permissive/450069022/hardware/src/iob-cache.v:104: Define or directive not defined: \'`CTRL_ADDR_W\'\n                                                                         : ... Suggested alternative: \'`MEM_ADDR_W\'\n   wire [`CTRL_ADDR_W-1:0]                             ctrl_addr;\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/450069022/hardware/src/iob-cache.v:121: syntax error, unexpected IDENTIFIER\n   front_end\n   ^~~~~~~~~\n%Error: Exiting due to 17 error(s)\n'
module iob_cache 
  #(

    parameter FE_ADDR_W   = 32,
    parameter FE_DATA_W  = 32,
    parameter N_WAYS   = 2,
    parameter LINE_OFF_W = 7,
    parameter WORD_OFF_W = 3,
    parameter WTBUF_DEPTH_W = 5,

    parameter REP_POLICY = `PLRU_mru,

    parameter NWAY_W   = $clog2(N_WAYS),
    parameter FE_NBYTES  = FE_DATA_W/8,
    parameter FE_BYTE_W  = $clog2(FE_NBYTES),


    parameter BE_ADDR_W = FE_ADDR_W,
    parameter BE_DATA_W = FE_DATA_W,
    parameter BE_NBYTES = BE_DATA_W/8,
    parameter BE_BYTE_W = $clog2(BE_NBYTES),

    parameter LINE2MEM_W = WORD_OFF_W-$clog2(BE_DATA_W/FE_DATA_W),


    parameter WRITE_POL = `WRITE_THROUGH,


    parameter CTRL_CACHE = 0,
    parameter CTRL_CNT = 0
    ) 
   (
    input                                       clk,
    input                                       reset,

    input                                       valid,
`ifdef WORD_ADDR   
    input [CTRL_CACHE + FE_ADDR_W -1:FE_BYTE_W] addr,
`else
    input [CTRL_CACHE + FE_ADDR_W -1:0]         addr,
`endif
    input [FE_DATA_W-1:0]                       wdata,
    input [FE_NBYTES-1:0]                       wstrb,
    output [FE_DATA_W-1:0]                      rdata,
    output                                      ready,
`ifdef CTRL_IO

    input                                       force_inv_in,
    output                                      force_inv_out, 
    input                                       wtb_empty_in,
    output                                      wtb_empty_out
`endif  







    );

    wire [BE_DATA_W-1:0]                      mem_rdata;
    wire                                      mem_valid;
    wire [BE_ADDR_W-1:0]                      mem_addr;
    wire [BE_DATA_W-1:0]                      mem_wdata;
    wire [BE_NBYTES-1:0]                      mem_wstrb;
    reg                                       mem_ready;

   

   wire                                         data_valid, data_ready;
   wire [FE_ADDR_W -1:FE_BYTE_W]                data_addr; 
   wire [FE_DATA_W-1 : 0]                       data_wdata, data_rdata;
   wire [FE_NBYTES-1: 0]                        data_wstrb;
   

   wire [FE_ADDR_W -1:FE_BYTE_W]                data_addr_reg; 
   wire [FE_DATA_W-1 : 0]                       data_wdata_reg;
   wire [FE_NBYTES-1: 0]                        data_wstrb_reg;
   wire                                         data_valid_reg;


   wire                                         write_valid, write_ready;
   wire [FE_ADDR_W-1:FE_BYTE_W + WRITE_POL*WORD_OFF_W] write_addr;
   wire [FE_DATA_W + WRITE_POL*(FE_DATA_W*(2**WORD_OFF_W)-FE_DATA_W)-1 :0] write_wdata;
   wire [FE_NBYTES-1:0]                                write_wstrb;
   

   wire                                                replace_valid, replace;
   wire [FE_ADDR_W -1:BE_BYTE_W+LINE2MEM_W]            replace_addr; 
   wire                                                read_valid;
   wire [LINE2MEM_W-1:0]                               read_addr;
   wire [BE_DATA_W-1:0]                                read_rdata;
   

   wire                                                ctrl_valid, ctrl_ready;   
   wire [`CTRL_ADDR_W-1:0]                             ctrl_addr;
   wire                                                wtbuf_full, wtbuf_empty;
   wire                                                write_hit, write_miss, read_hit, read_miss;
   wire [CTRL_CACHE*(FE_DATA_W-1):0]            ctrl_rdata;
   wire                                         invalidate;
   
`ifdef CTRL_IO
   assign force_inv_out = invalidate;

   generate
      if (CTRL_CACHE)
        assign wtb_empty_out = wtbuf_empty;
      else
        assign wtb_empty_out = wtbuf_empty & wtb_empty_in;
   endgenerate 
`endif
   
   front_end
     #(
       .FE_ADDR_W (FE_ADDR_W),
       .FE_DATA_W (FE_DATA_W),
       .CTRL_CACHE(CTRL_CACHE)
       )
   front_end
     (
      .clk   (clk),
      .reset (reset),

      .valid (valid),
      .addr  (addr),
      .wdata (wdata),
      .wstrb (wstrb),
      .rdata (rdata),
      .ready (ready),

      .data_valid (data_valid),
      .data_addr  (data_addr),

      .data_rdata (data_rdata),
      .data_ready (data_ready),

      .data_valid_reg (data_valid_reg),
      .data_addr_reg  (data_addr_reg),
      .data_wdata_reg (data_wdata_reg),
      .data_wstrb_reg (data_wstrb_reg),

      .ctrl_valid (ctrl_valid),
      .ctrl_addr  (ctrl_addr),
      .ctrl_rdata (ctrl_rdata),
      .ctrl_ready (ctrl_ready)
      );


   
   cache_memory
     #(
       .FE_ADDR_W (FE_ADDR_W),
       .FE_DATA_W (FE_DATA_W),
       .BE_DATA_W (BE_DATA_W),
       .N_WAYS     (N_WAYS),
       .LINE_OFF_W (LINE_OFF_W),
       .WORD_OFF_W (WORD_OFF_W),
       .REP_POLICY (REP_POLICY),    
       .WTBUF_DEPTH_W (WTBUF_DEPTH_W),
       .CTRL_CACHE(CTRL_CACHE),
       .CTRL_CNT  (CTRL_CNT),
       .WRITE_POL (WRITE_POL)
       )
   cache_memory
     (
      .clk   (clk),
      .reset (reset),


      .valid (data_valid),
      .addr  (data_addr[FE_ADDR_W-1:BE_BYTE_W + LINE2MEM_W]),


      .rdata (data_rdata),
      .ready (data_ready),

      .valid_reg (data_valid_reg),   
      .addr_reg  (data_addr_reg),
      .wdata_reg (data_wdata_reg),
      .wstrb_reg (data_wstrb_reg),


      .write_valid (write_valid),
      .write_addr  (write_addr),
      .write_wdata (write_wdata),
      .write_wstrb (write_wstrb),
      .write_ready (write_ready),

      .replace_valid (replace_valid),
      .replace_addr  (replace_addr),
      .replace (replace),
      .read_valid (read_valid),
      .read_addr  (read_addr),
      .read_rdata (read_rdata),

      .wtbuf_empty (wtbuf_empty),
      .wtbuf_full  (wtbuf_full),
      .write_hit   (write_hit),
      .write_miss  (write_miss),
      .read_hit    (read_hit),
      .read_miss   (read_miss),
`ifdef CTRL_IO
      .invalidate  (invalidate | force_inv_in)
`else
      .invalidate  (invalidate)
`endif
      );
   


   
   back_end_native
     #(
       .FE_ADDR_W (FE_ADDR_W),
       .FE_DATA_W (FE_DATA_W),  
       .BE_ADDR_W (BE_ADDR_W),
       .BE_DATA_W (BE_DATA_W),
       .WORD_OFF_W (WORD_OFF_W),
       .WRITE_POL (WRITE_POL)
       )
   back_end
     (
      .clk(clk),
      .reset(reset),

      .write_valid (write_valid),
      .write_addr  (write_addr),
      .write_wdata (write_wdata),
      .write_wstrb (write_wstrb),
      .write_ready (write_ready),

      .replace_valid (replace_valid),
      .replace_addr  (replace_addr),
      .replace (replace),
      .read_valid (read_valid),
      .read_addr  (read_addr),
      .read_rdata (read_rdata),

      .mem_valid (mem_valid),
      .mem_addr  (mem_addr),
      .mem_wdata (mem_wdata),
      .mem_wstrb (mem_wstrb),
      .mem_rdata (mem_rdata),
      .mem_ready (mem_ready)  
      );
   
   `define MEM_ADDR_W 14
   `define MEM_DATA_W 64
     iob_sp_ram #(
       .DATA_W(`MEM_DATA_W),
       .ADDR_W(`MEM_ADDR_W-2)
      )

     native_ram(
         .clk(clk),
         .en   (mem_valid),
         .we   (mem_wstrb),
         .addr (mem_addr[`MEM_ADDR_W-1:$clog2(`MEM_DATA_W/8)]),
         .dout (mem_rdata),
         .din  (mem_wdata)
     );

     always @(posedge clk)
        begin
         mem_ready <= mem_valid;
        end
   
   generate
      if (CTRL_CACHE)
         
        cache_control
          #(
            .FE_DATA_W  (FE_DATA_W),
            .CTRL_CNT   (CTRL_CNT)
            )
      cache_control
        (
         .clk   (clk),
         .reset (reset),

         .valid (ctrl_valid),
         .addr  (ctrl_addr),

         .wtbuf_full (wtbuf_full),
`ifdef CTRL_IO
         .wtbuf_empty (wtbuf_empty & wtb_empty_in),
`else
         .wtbuf_empty (wtbuf_empty), 
`endif
         .write_hit  (write_hit),
         .write_miss (write_miss),
         .read_hit   (read_hit),
         .read_miss  (read_miss),

         .rdata (ctrl_rdata),
         .ready (ctrl_ready),
         .invalidate (invalidate)
         );
      else
        begin
           assign ctrl_rdata = 1'bx;
           assign ctrl_ready = 1'bx;
           assign invalidate = 1'b0;
        end
      
   endgenerate

endmodule
module iob_cache 
  #(

    parameter FE_ADDR_W   = 32,
    parameter FE_DATA_W  = 32,
    parameter N_WAYS   = 2,
    parameter LINE_OFF_W = 7,
    parameter WORD_OFF_W = 3,
    parameter WTBUF_DEPTH_W = 5,

    parameter REP_POLICY = `PLRU_mru,

    parameter NWAY_W   = $clog2(N_WAYS),
    parameter FE_NBYTES  = FE_DATA_W/8,
    parameter FE_BYTE_W  = $clog2(FE_NBYTES),


    parameter BE_ADDR_W = FE_ADDR_W,
    parameter BE_DATA_W = FE_DATA_W,
    parameter BE_NBYTES = BE_DATA_W/8,
    parameter BE_BYTE_W = $clog2(BE_NBYTES),

    parameter LINE2MEM_W = WORD_OFF_W-$clog2(BE_DATA_W/FE_DATA_W),


    parameter WRITE_POL = `WRITE_THROUGH,


    parameter CTRL_CACHE = 0,
    parameter CTRL_CNT = 0
    ) 
   (
    input                                       clk,
    input                                       reset,

    input                                       valid,
`ifdef WORD_ADDR   
    input [CTRL_CACHE + FE_ADDR_W -1:FE_BYTE_W] addr,
`else
    input [CTRL_CACHE + FE_ADDR_W -1:0]         addr,
`endif
    input [FE_DATA_W-1:0]                       wdata,
    input [FE_NBYTES-1:0]                       wstrb,
    output [FE_DATA_W-1:0]                      rdata,
    output                                      ready,
`ifdef CTRL_IO

    input                                       force_inv_in,
    output                                      force_inv_out, 
    input                                       wtb_empty_in,
    output                                      wtb_empty_out
`endif  







    );


    wire [BE_DATA_W-1:0]                      mem_rdata;
    wire                                      mem_valid;
    wire [BE_ADDR_W-1:0]                      mem_addr;
    wire [BE_DATA_W-1:0]                      mem_wdata;
    wire [BE_NBYTES-1:0]                      mem_wstrb;
    reg                                       mem_ready;

   

   wire                                         data_valid, data_ready;
   wire [FE_ADDR_W -1:FE_BYTE_W]                data_addr; 
   wire [FE_DATA_W-1 : 0]                       data_wdata, data_rdata;
   wire [FE_NBYTES-1: 0]                        data_wstrb;
   

   wire [FE_ADDR_W -1:FE_BYTE_W]                data_addr_reg; 
   wire [FE_DATA_W-1 : 0]                       data_wdata_reg;
   wire [FE_NBYTES-1: 0]                        data_wstrb_reg;
   wire                                         data_valid_reg;


   wire                                         write_valid, write_ready;
   wire [FE_ADDR_W-1:FE_BYTE_W + WRITE_POL*WORD_OFF_W] write_addr;
   wire [FE_DATA_W + WRITE_POL*(FE_DATA_W*(2**WORD_OFF_W)-FE_DATA_W)-1 :0] write_wdata;
   wire [FE_NBYTES-1:0]                                write_wstrb;
   

   wire                                                replace_valid, replace;
   wire [FE_ADDR_W -1:BE_BYTE_W+LINE2MEM_W]            replace_addr; 
   wire                                                read_valid;
   wire [LINE2MEM_W-1:0]                               read_addr;
   wire [BE_DATA_W-1:0]                                read_rdata;
   

   wire                                                ctrl_valid, ctrl_ready;   
   wire [`CTRL_ADDR_W-1:0]                             ctrl_addr;
   wire                                                wtbuf_full, wtbuf_empty;
   wire                                                write_hit, write_miss, read_hit, read_miss;
   wire [CTRL_CACHE*(FE_DATA_W-1):0]            ctrl_rdata;
   wire                                         invalidate;
   
`ifdef CTRL_IO
   assign force_inv_out = invalidate;

   generate
      if (CTRL_CACHE)
        assign wtb_empty_out = wtbuf_empty;
      else
        assign wtb_empty_out = wtbuf_empty & wtb_empty_in;
   endgenerate 
`endif
   
   front_end
     #(
       .FE_ADDR_W (FE_ADDR_W),
       .FE_DATA_W (FE_DATA_W),
       .CTRL_CACHE(CTRL_CACHE)
       )
   front_end
     (
      .clk   (clk),
      .reset (reset),

      .valid (valid),
      .addr  (addr),
      .wdata (wdata),
      .wstrb (wstrb),
      .rdata (rdata),
      .ready (ready),

      .data_valid (data_valid),
      .data_addr  (data_addr),

      .data_rdata (data_rdata),
      .data_ready (data_ready),

      .data_valid_reg (data_valid_reg),
      .data_addr_reg  (data_addr_reg),
      .data_wdata_reg (data_wdata_reg),
      .data_wstrb_reg (data_wstrb_reg),

      .ctrl_valid (ctrl_valid),
      .ctrl_addr  (ctrl_addr),
      .ctrl_rdata (ctrl_rdata),
      .ctrl_ready (ctrl_ready)
      );


   
   cache_memory
     #(
       .FE_ADDR_W (FE_ADDR_W),
       .FE_DATA_W (FE_DATA_W),
       .BE_DATA_W (BE_DATA_W),
       .N_WAYS     (N_WAYS),
       .LINE_OFF_W (LINE_OFF_W),
       .WORD_OFF_W (WORD_OFF_W),
       .REP_POLICY (REP_POLICY),    
       .WTBUF_DEPTH_W (WTBUF_DEPTH_W),
       .CTRL_CACHE(CTRL_CACHE),
       .CTRL_CNT  (CTRL_CNT),
       .WRITE_POL (WRITE_POL)
       )
   cache_memory
     (
      .clk   (clk),
      .reset (reset),


      .valid (data_valid),
      .addr  (data_addr[FE_ADDR_W-1:BE_BYTE_W + LINE2MEM_W]),


      .rdata (data_rdata),
      .ready (data_ready),

      .valid_reg (data_valid_reg),   
      .addr_reg  (data_addr_reg),
      .wdata_reg (data_wdata_reg),
      .wstrb_reg (data_wstrb_reg),


      .write_valid (write_valid),
      .write_addr  (write_addr),
      .write_wdata (write_wdata),
      .write_wstrb (write_wstrb),
      .write_ready (write_ready),

      .replace_valid (replace_valid),
      .replace_addr  (replace_addr),
      .replace (replace),
      .read_valid (read_valid),
      .read_addr  (read_addr),
      .read_rdata (read_rdata),

      .wtbuf_empty (wtbuf_empty),
      .wtbuf_full  (wtbuf_full),
      .write_hit   (write_hit),
      .write_miss  (write_miss),
      .read_hit    (read_hit),
      .read_miss   (read_miss),
`ifdef CTRL_IO
      .invalidate  (invalidate | force_inv_in)
`else
      .invalidate  (invalidate)
`endif
      );
   


   
   back_end_native
     #(
       .FE_ADDR_W (FE_ADDR_W),
       .FE_DATA_W (FE_DATA_W),  
       .BE_ADDR_W (BE_ADDR_W),
       .BE_DATA_W (BE_DATA_W),
       .WORD_OFF_W (WORD_OFF_W),
       .WRITE_POL (WRITE_POL)
       )
   back_end
     (
      .clk(clk),
      .reset(reset),

      .write_valid (write_valid),
      .write_addr  (write_addr),
      .write_wdata (write_wdata),
      .write_wstrb (write_wstrb),
      .write_ready (write_ready),

      .replace_valid (replace_valid),
      .replace_addr  (replace_addr),
      .replace (replace),
      .read_valid (read_valid),
      .read_addr  (read_addr),
      .read_rdata (read_rdata),

      .mem_valid (mem_valid),
      .mem_addr  (mem_addr),
      .mem_wdata (mem_wdata),
      .mem_wstrb (mem_wstrb),
      .mem_rdata (mem_rdata),
      .mem_ready (mem_ready)  
      );
   
   `define MEM_ADDR_W 14
   `define MEM_DATA_W 64
     iob_sp_ram #(
       .DATA_W(`MEM_DATA_W),
       .ADDR_W(`MEM_ADDR_W-2)
      )

     native_ram(
         .clk(clk),
         .en   (mem_valid),
         .we   (mem_wstrb),
         .addr (mem_addr[`MEM_ADDR_W-1:$clog2(`MEM_DATA_W/8)]),
         .dout (mem_rdata),
         .din  (mem_wdata)
     );

     always @(posedge clk)
        begin
         mem_ready <= mem_valid;
        end
   
   generate
      if (CTRL_CACHE)
         
        cache_control
          #(
            .FE_DATA_W  (FE_DATA_W),
            .CTRL_CNT   (CTRL_CNT)
            )
      cache_control
        (
         .clk   (clk),
         .reset (reset),

         .valid (ctrl_valid),
         .addr  (ctrl_addr),

         .wtbuf_full (wtbuf_full),
`ifdef CTRL_IO
         .wtbuf_empty (wtbuf_empty & wtb_empty_in),
`else
         .wtbuf_empty (wtbuf_empty), 
`endif
         .write_hit  (write_hit),
         .write_miss (write_miss),
         .read_hit   (read_hit),
         .read_miss  (read_miss),

         .rdata (ctrl_rdata),
         .ready (ctrl_ready),
         .invalidate (invalidate)
         );
      else
        begin
           assign ctrl_rdata = 1'bx;
           assign ctrl_ready = 1'bx;
           assign invalidate = 1'b0;
        end
      
   endgenerate

endmodule