data/full_repos/permissive/460468583/data/yosys/gatemate/reg_map.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/460468583/data/yosys/gatemate/reg_map.v:35: Multiple top level modules\n                                                                                        : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                        : ... Top module \'$_DFFE_xxxx_\'\nmodule \\$_DFFE_xxxx_ (input D, C, R, E, output Q);\n       ^~~~~~~~~~~~~\n                                                                                        : ... Top module \'$_DLATCH_xxx_\'\nmodule \\$_DLATCH_xxx_ (input E, R, D, output Q);\n       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/gatemate/reg_map.v:39: Cannot find file containing module: \'CC_DLT\'\n CC_DLT #(\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/460468583/data/yosys/gatemate,data/full_repos/permissive/460468583/CC_DLT\n             data/full_repos/permissive/460468583/data/yosys/gatemate,data/full_repos/permissive/460468583/CC_DLT.v\n             data/full_repos/permissive/460468583/data/yosys/gatemate,data/full_repos/permissive/460468583/CC_DLT.sv\n             CC_DLT\n             CC_DLT.v\n             CC_DLT.sv\n             obj_dir/CC_DLT\n             obj_dir/CC_DLT.v\n             obj_dir/CC_DLT.sv\n%Error: data/full_repos/permissive/460468583/data/yosys/gatemate/reg_map.v:25: Cannot find file containing module: \'CC_DFF\'\n CC_DFF #(\n ^~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module \$_DLATCH_xxx_ (input E, R, D, output Q);

	parameter _TECHMAP_CELLTYPE_ = "";

	CC_DLT #(
		.G_INV(_TECHMAP_CELLTYPE_[31:24] == "N"),
		.SR_INV(_TECHMAP_CELLTYPE_[23:16] == "N"),
		.SR_VAL(_TECHMAP_CELLTYPE_[15:8] == "1")
	) _TECHMAP_REPLACE_ (.D(D), .G(E), .SR(R), .Q(Q));

endmodule
module \$_DLATCH_xxx_ (input E, R, D, output Q);


	parameter _TECHMAP_CELLTYPE_ = "";

	CC_DLT #(
		.G_INV(_TECHMAP_CELLTYPE_[31:24] == "N"),
		.SR_INV(_TECHMAP_CELLTYPE_[23:16] == "N"),
		.SR_VAL(_TECHMAP_CELLTYPE_[15:8] == "1")
	) _TECHMAP_REPLACE_ (.D(D), .G(E), .SR(R), .Q(Q));

endmodule