data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/fpga-support/rtl/AxiToAxiLitePc.sv
1: b'%Warning-MULTITOP: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/fpga-support/rtl/AxiToAxiLitePc.sv:46: Multiple top level modules\n                                                                                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                                                              : ... Top module \'AxiToAxiLitePc\'\nmodule AxiToAxiLitePc\n       ^~~~~~~~~~~~~~\n                                                                                                                                              : ... Top module \'AXI_BUS\'\n    AXI_BUS.Slave   Axi_PS,\n    ^~~~~~~\n                                                                                                                                              : ... Top module \'AXI_LITE\'\n    AXI_LITE.Master AxiLite_PM\n    ^~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/fpga-support/rtl/AxiToAxiLitePc.sv:46: Unsupported: Interfaced port on top level module\n    AXI_BUS.Slave   Axi_PS,\n                    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/fpga-support/rtl/AxiToAxiLitePc.sv:47: Unsupported: Interfaced port on top level module\n    AXI_LITE.Master AxiLite_PM\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/fpga-support/rtl/AxiToAxiLitePc.sv:46: Cannot find file containing interface: \'AXI_BUS\'\n    AXI_BUS.Slave   Axi_PS,\n    ^~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/fpga-support/rtl/AxiToAxiLitePc.sv:47: Cannot find file containing interface: \'AXI_LITE\'\n    AXI_LITE.Master AxiLite_PM\n    ^~~~~~~~\n%Error: Internal Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/fpga-support/rtl/AxiToAxiLitePc.sv:46: ../V3LinkDot.cpp:2055: Unlinked interface\n    AXI_BUS.Slave   Axi_PS,\n    ^~~~~~~\n'
module AxiToAxiLitePc


  #(
    parameter AXI_ADDR_WIDTH  = 32,
    parameter AXI_ID_WIDTH    = 10
  )



  (

    input  logic    Clk_CI,
    input  logic    Rst_RBI,

    AXI_BUS.Slave   Axi_PS,
    AXI_LITE.Master AxiLite_PM

  );



  logic   [AXI_ID_WIDTH-1:0]  ArId_DN,    ArId_DP;
  logic [AXI_ADDR_WIDTH-1:0]  AwAddr_DN,  AwAddr_DP;
  logic   [AXI_ID_WIDTH-1:0]  AwId_DN,    AwId_DP;
  logic                       AwValid_DN, AwValid_DP;

  enum logic [1:0] {RREADY, READ, RERR}
                              StateRead_SP,   StateRead_SN;
  enum logic [2:0] {WREADY, WRITE, WAITAWREADY, WAITWREADY, WRESP, WERRBEATS, WERRRESP}
                              StateWrite_SP,  StateWrite_SN;



  always_comb begin

    AwAddr_DN           = AwAddr_DP;
    AwId_DN             = AwId_DP;
    Axi_PS.aw_ready     = 1'b0;
    Axi_PS.w_ready      = 1'b0;
    Axi_PS.b_resp       = 2'b00;
    Axi_PS.b_valid      = 1'b0;
    AxiLite_PM.aw_valid = 1'b0;
    AxiLite_PM.w_valid  = 1'b0;
    AxiLite_PM.b_ready  = 1'b0;
    StateWrite_SN       = StateWrite_SP;

    case (StateWrite_SP)

      WREADY: begin
        if (Axi_PS.aw_valid) begin
          Axi_PS.aw_ready = 1'b1;
          AwId_DN         = Axi_PS.aw_id;
          if (Axi_PS.aw_len != '0) begin
            StateWrite_SN = WERRBEATS;
          end else begin
            AwAddr_DN     = Axi_PS.aw_addr;
            StateWrite_SN = WRITE;
          end
        end
      end

      WRITE: begin
        if (Axi_PS.w_valid) begin
          AxiLite_PM.aw_valid = 1'b1;
          AxiLite_PM.w_valid  = 1'b1;

          if (AxiLite_PM.w_ready && AxiLite_PM.aw_ready) begin
            Axi_PS.w_ready = 1'b1;
            StateWrite_SN  = WRESP;
          end else if (AxiLite_PM.w_ready) begin
            Axi_PS.w_ready = 1'b1;
            StateWrite_SN  = WAITAWREADY;
          end else if (AxiLite_PM.aw_ready) begin
            StateWrite_SN  = WAITWREADY;
          end
        end
      end

      WAITAWREADY: begin
        AxiLite_PM.aw_valid = 1'b1;
        if (AxiLite_PM.aw_ready) begin
            StateWrite_SN = WRESP;
        end
      end

      WAITWREADY: begin
        AxiLite_PM.w_valid = 1'b1;
        if (AxiLite_PM.w_ready) begin
            StateWrite_SN = WRESP;
        end
      end



      WRESP: begin
        AxiLite_PM.b_ready  = Axi_PS.b_ready;
        Axi_PS.b_valid      = AxiLite_PM.b_valid;
        Axi_PS.b_resp       = AxiLite_PM.b_resp;
        if (Axi_PS.b_ready && AxiLite_PM.b_valid) begin
          StateWrite_SN = WREADY;
        end
      end


      WERRBEATS: begin
        Axi_PS.w_ready = 1'b1;
        if (Axi_PS.w_valid && Axi_PS.w_last) begin
          StateWrite_SN = WERRRESP;
        end
      end


      WERRRESP: begin
        Axi_PS.b_resp   = 2'b10;
        Axi_PS.b_valid  = 1'b1;
        if (Axi_PS.b_ready) begin
          StateWrite_SN = WREADY;
        end
      end

      default: begin
        StateWrite_SN = WREADY;
      end

    endcase
  end



  always_comb begin

    ArId_DN             = ArId_DP;
    Axi_PS.ar_ready     = 1'b0;
    Axi_PS.r_resp       = 2'b00;
    Axi_PS.r_last       = 1'b0;
    Axi_PS.r_valid      = 1'b0;
    AxiLite_PM.ar_valid = 1'b0;
    StateRead_SN        = StateRead_SP;

    case (StateRead_SP)

      RREADY: begin
        if (Axi_PS.ar_valid) begin
          if (Axi_PS.ar_len != '0) begin
            StateRead_SN    = RERR;
            ArId_DN         = Axi_PS.ar_id;
            Axi_PS.ar_ready = 1'b1;
          end else begin
            AxiLite_PM.ar_valid = Axi_PS.ar_valid;
            if (AxiLite_PM.ar_ready) begin
              Axi_PS.ar_ready = 1'b1;
              ArId_DN         = Axi_PS.ar_id;
              StateRead_SN    = READ;
            end
          end
        end
      end

      READ: begin
        if (AxiLite_PM.r_valid) begin
          Axi_PS.r_resp   = AxiLite_PM.r_resp;
          Axi_PS.r_last   = 1'b1;
          Axi_PS.r_valid  = 1'b1;
          if (Axi_PS.r_ready) begin
            StateRead_SN = RREADY;
          end
        end
      end

      RERR: begin
        Axi_PS.r_resp   = 2'b10;
        Axi_PS.r_last   = 1'b1;
        Axi_PS.r_valid  = 1'b1;
        if (Axi_PS.r_ready) begin
          StateRead_SN = RREADY;
        end
      end

      default: begin
        StateRead_SN = RREADY;
      end

    endcase
  end




  assign AxiLite_PM.aw_addr   = AwAddr_DP;

  assign AxiLite_PM.w_data    = Axi_PS.w_data;
  assign AxiLite_PM.w_strb    = Axi_PS.w_strb;

  assign AxiLite_PM.ar_addr   = Axi_PS.ar_addr;

  assign AxiLite_PM.r_ready   = Axi_PS.r_ready;





  assign Axi_PS.r_data   = AxiLite_PM.r_data;
  assign Axi_PS.r_id     = ArId_DP;
  assign Axi_PS.r_user   = 'b0;

  assign Axi_PS.b_id     = AwId_DP;
  assign Axi_PS.b_user   = 'b0;




  always_ff @ (posedge Clk_CI)
  begin
    ArId_DP       <= 'b0;
    AwAddr_DP     <= 'b0;
    AwId_DP       <= 'b0;
    AwValid_DP    <= 'b0;
    StateRead_SP  <= RREADY;
    StateWrite_SP <= WREADY;
    if (Rst_RBI) begin
      ArId_DP       <= ArId_DN;
      AwAddr_DP     <= AwAddr_DN;
      AwId_DP       <= AwId_DN;
      AwValid_DP    <= AwValid_DN;
      StateRead_SP  <= StateRead_SN;
      StateWrite_SP <= StateWrite_SN;
    end
  end



  always @(posedge Clk_CI) begin
    if (Rst_RBI) begin
      assert (!(Axi_PS.aw_valid && Axi_PS.aw_len != '0))
        else $error("Unsupported burst on AW channel!");
      assert (!(Axi_PS.ar_valid && Axi_PS.ar_len != '0))
        else $error("Unsupported burst on AR channel!");
    end
  end


endmodule
module AxiToAxiLitePc


  #(
    parameter AXI_ADDR_WIDTH  = 32,
    parameter AXI_ID_WIDTH    = 10
  )



  (

    input  logic    Clk_CI,
    input  logic    Rst_RBI,

    AXI_BUS.Slave   Axi_PS,
    AXI_LITE.Master AxiLite_PM

  );




  logic   [AXI_ID_WIDTH-1:0]  ArId_DN,    ArId_DP;
  logic [AXI_ADDR_WIDTH-1:0]  AwAddr_DN,  AwAddr_DP;
  logic   [AXI_ID_WIDTH-1:0]  AwId_DN,    AwId_DP;
  logic                       AwValid_DN, AwValid_DP;

  enum logic [1:0] {RREADY, READ, RERR}
                              StateRead_SP,   StateRead_SN;
  enum logic [2:0] {WREADY, WRITE, WAITAWREADY, WAITWREADY, WRESP, WERRBEATS, WERRRESP}
                              StateWrite_SP,  StateWrite_SN;



  always_comb begin

    AwAddr_DN           = AwAddr_DP;
    AwId_DN             = AwId_DP;
    Axi_PS.aw_ready     = 1'b0;
    Axi_PS.w_ready      = 1'b0;
    Axi_PS.b_resp       = 2'b00;
    Axi_PS.b_valid      = 1'b0;
    AxiLite_PM.aw_valid = 1'b0;
    AxiLite_PM.w_valid  = 1'b0;
    AxiLite_PM.b_ready  = 1'b0;
    StateWrite_SN       = StateWrite_SP;

    case (StateWrite_SP)

      WREADY: begin
        if (Axi_PS.aw_valid) begin
          Axi_PS.aw_ready = 1'b1;
          AwId_DN         = Axi_PS.aw_id;
          if (Axi_PS.aw_len != '0) begin
            StateWrite_SN = WERRBEATS;
          end else begin
            AwAddr_DN     = Axi_PS.aw_addr;
            StateWrite_SN = WRITE;
          end
        end
      end

      WRITE: begin
        if (Axi_PS.w_valid) begin
          AxiLite_PM.aw_valid = 1'b1;
          AxiLite_PM.w_valid  = 1'b1;

          if (AxiLite_PM.w_ready && AxiLite_PM.aw_ready) begin
            Axi_PS.w_ready = 1'b1;
            StateWrite_SN  = WRESP;
          end else if (AxiLite_PM.w_ready) begin
            Axi_PS.w_ready = 1'b1;
            StateWrite_SN  = WAITAWREADY;
          end else if (AxiLite_PM.aw_ready) begin
            StateWrite_SN  = WAITWREADY;
          end
        end
      end

      WAITAWREADY: begin
        AxiLite_PM.aw_valid = 1'b1;
        if (AxiLite_PM.aw_ready) begin
            StateWrite_SN = WRESP;
        end
      end

      WAITWREADY: begin
        AxiLite_PM.w_valid = 1'b1;
        if (AxiLite_PM.w_ready) begin
            StateWrite_SN = WRESP;
        end
      end



      WRESP: begin
        AxiLite_PM.b_ready  = Axi_PS.b_ready;
        Axi_PS.b_valid      = AxiLite_PM.b_valid;
        Axi_PS.b_resp       = AxiLite_PM.b_resp;
        if (Axi_PS.b_ready && AxiLite_PM.b_valid) begin
          StateWrite_SN = WREADY;
        end
      end


      WERRBEATS: begin
        Axi_PS.w_ready = 1'b1;
        if (Axi_PS.w_valid && Axi_PS.w_last) begin
          StateWrite_SN = WERRRESP;
        end
      end


      WERRRESP: begin
        Axi_PS.b_resp   = 2'b10;
        Axi_PS.b_valid  = 1'b1;
        if (Axi_PS.b_ready) begin
          StateWrite_SN = WREADY;
        end
      end

      default: begin
        StateWrite_SN = WREADY;
      end

    endcase
  end



  always_comb begin

    ArId_DN             = ArId_DP;
    Axi_PS.ar_ready     = 1'b0;
    Axi_PS.r_resp       = 2'b00;
    Axi_PS.r_last       = 1'b0;
    Axi_PS.r_valid      = 1'b0;
    AxiLite_PM.ar_valid = 1'b0;
    StateRead_SN        = StateRead_SP;

    case (StateRead_SP)

      RREADY: begin
        if (Axi_PS.ar_valid) begin
          if (Axi_PS.ar_len != '0) begin
            StateRead_SN    = RERR;
            ArId_DN         = Axi_PS.ar_id;
            Axi_PS.ar_ready = 1'b1;
          end else begin
            AxiLite_PM.ar_valid = Axi_PS.ar_valid;
            if (AxiLite_PM.ar_ready) begin
              Axi_PS.ar_ready = 1'b1;
              ArId_DN         = Axi_PS.ar_id;
              StateRead_SN    = READ;
            end
          end
        end
      end

      READ: begin
        if (AxiLite_PM.r_valid) begin
          Axi_PS.r_resp   = AxiLite_PM.r_resp;
          Axi_PS.r_last   = 1'b1;
          Axi_PS.r_valid  = 1'b1;
          if (Axi_PS.r_ready) begin
            StateRead_SN = RREADY;
          end
        end
      end

      RERR: begin
        Axi_PS.r_resp   = 2'b10;
        Axi_PS.r_last   = 1'b1;
        Axi_PS.r_valid  = 1'b1;
        if (Axi_PS.r_ready) begin
          StateRead_SN = RREADY;
        end
      end

      default: begin
        StateRead_SN = RREADY;
      end

    endcase
  end




  assign AxiLite_PM.aw_addr   = AwAddr_DP;

  assign AxiLite_PM.w_data    = Axi_PS.w_data;
  assign AxiLite_PM.w_strb    = Axi_PS.w_strb;

  assign AxiLite_PM.ar_addr   = Axi_PS.ar_addr;

  assign AxiLite_PM.r_ready   = Axi_PS.r_ready;





  assign Axi_PS.r_data   = AxiLite_PM.r_data;
  assign Axi_PS.r_id     = ArId_DP;
  assign Axi_PS.r_user   = 'b0;

  assign Axi_PS.b_id     = AwId_DP;
  assign Axi_PS.b_user   = 'b0;




  always_ff @ (posedge Clk_CI)
  begin
    ArId_DP       <= 'b0;
    AwAddr_DP     <= 'b0;
    AwId_DP       <= 'b0;
    AwValid_DP    <= 'b0;
    StateRead_SP  <= RREADY;
    StateWrite_SP <= WREADY;
    if (Rst_RBI) begin
      ArId_DP       <= ArId_DN;
      AwAddr_DP     <= AwAddr_DN;
      AwId_DP       <= AwId_DN;
      AwValid_DP    <= AwValid_DN;
      StateRead_SP  <= StateRead_SN;
      StateWrite_SP <= StateWrite_SN;
    end
  end



  always @(posedge Clk_CI) begin
    if (Rst_RBI) begin
      assert (!(Axi_PS.aw_valid && Axi_PS.aw_len != '0))
        else $error("Unsupported burst on AW channel!");
      assert (!(Axi_PS.ar_valid && Axi_PS.ar_len != '0))
        else $error("Unsupported burst on AR channel!");
    end
  end


endmodule