data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Motion_Compensation/Completed_Prediction_Buffer.v
1: b'%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Motion_Compensation/Completed_Prediction_Buffer.v:17: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Motion_Compensation,data/full_repos/permissive/502764644/defines.v\n             data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Motion_Compensation,data/full_repos/permissive/502764644/defines.v.v\n             data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/Motion_Compensation,data/full_repos/permissive/502764644/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: Exiting due to 1 error(s)\n'
module Completed_Prediction_Buffer (
	clock,

	Write_En_A_I,
	Address_A_I,
	Data_A_I,

	Address_B_I,
	Data_B_O
);

input 				clock;

input 				Write_En_A_I;
input 	[9:0]		Address_A_I;
input 	[15:0]	Data_A_I;

input 	[10:0] 	Address_B_I;
output 	[7:0]		Data_B_O;

wire 					enable_A;

assign enable_A = ~(Write_En_A_I & (Address_B_I[10:1] == Address_A_I));

RAMB16_S9_S18 Buffer_RAM (
   .DOA(Data_B_O),
   .DOB(),
   .DOPA(),
   .DOPB(),
   .ADDRA(Address_B_I),
   .ADDRB(Address_A_I),
   .CLKA(clock),
   .CLKB(clock),
   .DIA(8'h00),
   .DIB(Data_A_I),
   .DIPA(1'b0),
   .DIPB(2'b00),
   .ENA(enable_A),
   .ENB(1'b1),
   .SSRA(1'b0),
   .SSRB(1'b0),
   .WEA(1'b0),
   .WEB(Write_En_A_I)
);

endmodule
module Completed_Prediction_Buffer (
	clock,

	Write_En_A_I,
	Address_A_I,
	Data_A_I,

	Address_B_I,
	Data_B_O
);


input 				clock;

input 				Write_En_A_I;
input 	[9:0]		Address_A_I;
input 	[15:0]	Data_A_I;

input 	[10:0] 	Address_B_I;
output 	[7:0]		Data_B_O;

wire 					enable_A;

assign enable_A = ~(Write_En_A_I & (Address_B_I[10:1] == Address_A_I));

RAMB16_S9_S18 Buffer_RAM (
   .DOA(Data_B_O),
   .DOB(),
   .DOPA(),
   .DOPB(),
   .ADDRA(Address_B_I),
   .ADDRB(Address_A_I),
   .CLKA(clock),
   .CLKB(clock),
   .DIA(8'h00),
   .DIB(Data_A_I),
   .DIPA(1'b0),
   .DIPB(2'b00),
   .ENA(enable_A),
   .ENB(1'b1),
   .SSRA(1'b0),
   .SSRB(1'b0),
   .WEA(1'b0),
   .WEB(Write_En_A_I)
);

endmodule