data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/Processor/ALU.v
1: b"%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/Processor/ALU.v:38: Cannot find file containing module: 'Adder'\nAdder a1(a,ar1,(s[0]&(~k_mov)),ar2,cout);\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/Processor,data/full_repos/permissive/435890256/Adder\n             data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/Processor,data/full_repos/permissive/435890256/Adder.v\n             data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/Processor,data/full_repos/permissive/435890256/Adder.sv\n             Adder\n             Adder.v\n             Adder.sv\n             obj_dir/Adder\n             obj_dir/Adder.v\n             obj_dir/Adder.sv\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/Processor/ALU.v:45: Cannot find file containing module: 'mux2_1_1bit'\nmux2_1_1bit m1[15:0](l1,l2,s[0],l5);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/Processor/ALU.v:46: Cannot find file containing module: 'mux2_1_1bit'\nmux2_1_1bit m2[15:0](l3,l4,s[0],l6);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/Processor/ALU.v:47: Cannot find file containing module: 'mux2_1_1bit'\nmux2_1_1bit m3[15:0](l5,l6,s[1],l7);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/Processor/ALU.v:52: Cannot find file containing module: 'mux2_1_1bit'\nmux2_1_1bit mmul1[7:0](a[7:0],a[15:8],~mul[0],wmul1);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/Processor/ALU.v:53: Cannot find file containing module: 'mux2_1_1bit'\nmux2_1_1bit mmul2[7:0](b[7:0],b[15:8],~mul[0],wmul2);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/Processor/ALU.v:54: Cannot find file containing module: 'mux2_1_1bit'\nmux2_1_1bit mmul3[7:0]({8{1'b0}},wmul1,mul[0]|mul[1],wmul11);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/Processor/ALU.v:55: Cannot find file containing module: 'mux2_1_1bit'\nmux2_1_1bit mmul4[7:0]({8{1'b0}},wmul2,mul[0]|mul[1],wmul22);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/Processor/ALU.v:56: Cannot find file containing module: 'wallace_8bit'\nwallace_8bit m4(wmul11,wmul22,mul1); \n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/Processor/ALU.v:61: Cannot find file containing module: 'mux2_1_1bit'\nmux2_1_1bit m5[15:0](sh1,sh2,sel,sh3);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/Processor/ALU.v:64: Cannot find file containing module: 'mux2_1_1bit'\nmux2_1_1bit m6[15:0](ar2,l8,alu_sel[0],w1);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/Processor/ALU.v:65: Cannot find file containing module: 'mux2_1_1bit'\nmux2_1_1bit m7[15:0](mul1,sh3,alu_sel[0],w2);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/435890256/uvm_ref1/Processor-UVM-Verification/Code/Processor/ALU.v:66: Cannot find file containing module: 'mux2_1_1bit'\nmux2_1_1bit m8[15:0](w1,w2,alu_sel[1]&(~k_mov),y);\n^~~~~~~~~~~\n%Error: Exiting due to 13 error(s)\n"
module ALU(
input [15:0]a,
input [15:0]b,
input [1:0]alu_sel,
input [1:0]s,
input sel,
input [1:0]mul,
output [15:0]y,
output cout
    );  
wire [15:0]ar1,ar2,l1,l2,l3,l4,l5,l6,l7,l8,sh1,sh2,sh3,w1,w2,mul1;

wire k_mov=alu_sel[1]&~alu_sel[0]&~s[1]&s[0];



assign ar1=((~({16{s[0]}}))&b)|((({16{s[0]}})^({16{s[1]}}))&~b)&({16{~k_mov}});	
Adder a1(a,ar1,(s[0]&(~k_mov)),ar2,cout);


assign l1=a&b;
assign l2=a|b;
assign l3=a^b;
assign l4=a;
mux2_1_1bit m1[15:0](l1,l2,s[0],l5);
mux2_1_1bit m2[15:0](l3,l4,s[0],l6);
mux2_1_1bit m3[15:0](l5,l6,s[1],l7);
assign l8=l7^({16{sel}});


wire[7:0] wmul1,wmul2,wmul11,wmul22;
mux2_1_1bit mmul1[7:0](a[7:0],a[15:8],~mul[0],wmul1);
mux2_1_1bit mmul2[7:0](b[7:0],b[15:8],~mul[0],wmul2);
mux2_1_1bit mmul3[7:0]({8{1'b0}},wmul1,mul[0]|mul[1],wmul11);
mux2_1_1bit mmul4[7:0]({8{1'b0}},wmul2,mul[0]|mul[1],wmul22);
wallace_8bit m4(wmul11,wmul22,mul1); 


assign sh1=a<<b;
assign sh2=a>>b;
mux2_1_1bit m5[15:0](sh1,sh2,sel,sh3);


mux2_1_1bit m6[15:0](ar2,l8,alu_sel[0],w1);
mux2_1_1bit m7[15:0](mul1,sh3,alu_sel[0],w2);
mux2_1_1bit m8[15:0](w1,w2,alu_sel[1]&(~k_mov),y);

endmodule
module ALU(
input [15:0]a,
input [15:0]b,
input [1:0]alu_sel,
input [1:0]s,
input sel,
input [1:0]mul,
output [15:0]y,
output cout
    );
  
wire [15:0]ar1,ar2,l1,l2,l3,l4,l5,l6,l7,l8,sh1,sh2,sh3,w1,w2,mul1;

wire k_mov=alu_sel[1]&~alu_sel[0]&~s[1]&s[0];



assign ar1=((~({16{s[0]}}))&b)|((({16{s[0]}})^({16{s[1]}}))&~b)&({16{~k_mov}});	
Adder a1(a,ar1,(s[0]&(~k_mov)),ar2,cout);


assign l1=a&b;
assign l2=a|b;
assign l3=a^b;
assign l4=a;
mux2_1_1bit m1[15:0](l1,l2,s[0],l5);
mux2_1_1bit m2[15:0](l3,l4,s[0],l6);
mux2_1_1bit m3[15:0](l5,l6,s[1],l7);
assign l8=l7^({16{sel}});


wire[7:0] wmul1,wmul2,wmul11,wmul22;
mux2_1_1bit mmul1[7:0](a[7:0],a[15:8],~mul[0],wmul1);
mux2_1_1bit mmul2[7:0](b[7:0],b[15:8],~mul[0],wmul2);
mux2_1_1bit mmul3[7:0]({8{1'b0}},wmul1,mul[0]|mul[1],wmul11);
mux2_1_1bit mmul4[7:0]({8{1'b0}},wmul2,mul[0]|mul[1],wmul22);
wallace_8bit m4(wmul11,wmul22,mul1); 


assign sh1=a<<b;
assign sh2=a>>b;
mux2_1_1bit m5[15:0](sh1,sh2,sel,sh3);


mux2_1_1bit m6[15:0](ar2,l8,alu_sel[0],w1);
mux2_1_1bit m7[15:0](mul1,sh3,alu_sel[0],w2);
mux2_1_1bit m8[15:0](w1,w2,alu_sel[1]&(~k_mov),y);

endmodule