data/full_repos/permissive/520428138/verilog/rtl/user_module_340067262721426004.v
1: b"%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_340067262721426004.v:32: Duplicate declaration of signal: 'in'\n                                                                                            : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nwire in, rst, nrst, out, s0, s1, s2;\n     ^~\n        data/full_repos/permissive/520428138/verilog/rtl/user_module_340067262721426004.v:30: ... Location of original declaration\nmodule div3_340067262721426004 (input in, rst, output out);\n                                      ^~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_340067262721426004.v:32: Duplicate declaration of signal: 'rst'\nwire in, rst, nrst, out, s0, s1, s2;\n         ^~~\n        data/full_repos/permissive/520428138/verilog/rtl/user_module_340067262721426004.v:30: ... Location of original declaration\nmodule div3_340067262721426004 (input in, rst, output out);\n                                          ^~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_340067262721426004.v:32: Duplicate declaration of signal: 'out'\nwire in, rst, nrst, out, s0, s1, s2;\n                    ^~~\n        data/full_repos/permissive/520428138/verilog/rtl/user_module_340067262721426004.v:30: ... Location of original declaration\nmodule div3_340067262721426004 (input in, rst, output out);\n                                                      ^~~\n%Error: Exiting due to 3 error(s)\n"
module div3_340067262721426004 (input in, rst, output out);

wire in, rst, nrst, out, s0, s1, s2;

assign #1 out = ~s0;
assign #1 nrst = ~rst;

wire a,b,c;




assign a = s0&s1;
assign b = ~s2&in&s0;
assign c = s2&in&s1;

assign #1 s0 = nrst & ( a|b|c ); 

wire d,e,f,g;

assign d=~s0&s1;
assign e=~s2&~in&s1;
assign f=s2&~in&~s0;
assign g=s1&s2;

assign #1 s1 = nrst & ( d|e|f|g );

wire h,i,j;

assign h = ~s0&s2;
assign i = ~s0&~s1&in;
assign j = s2&in;

assign #1 s2 = nrst & ( h|i|j );

endmodule
module div3_340067262721426004 (input in, rst, output out);


wire in, rst, nrst, out, s0, s1, s2;

assign #1 out = ~s0;
assign #1 nrst = ~rst;

wire a,b,c;




assign a = s0&s1;
assign b = ~s2&in&s0;
assign c = s2&in&s1;

assign #1 s0 = nrst & ( a|b|c ); 

wire d,e,f,g;

assign d=~s0&s1;
assign e=~s2&~in&s1;
assign f=s2&~in&~s0;
assign g=s1&s2;

assign #1 s1 = nrst & ( d|e|f|g );

wire h,i,j;

assign h = ~s0&s2;
assign i = ~s0&~s1&in;
assign j = s2&in;

assign #1 s2 = nrst & ( h|i|j );

endmodule