data/full_repos/permissive/453763315/ram.v
1: b'%Warning-WIDTH: data/full_repos/permissive/453763315/ram.v:11: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 16 bits.\n                                                             : ... In instance ram\n     read <= ram[addr];\n          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/453763315/ram.v:12: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'write\' generates 8 bits.\n                                                             : ... In instance ram\n        if (!rw) ram[addr] <= write;\n                           ^~\n%Error: Exiting due to 2 warning(s)\n'
module ram(en, rw, addr, write, read);
  input en;
  input reg rw;
  input reg [10:0] addr;
  input reg [7:0] write;
  output reg [7:0] read;
  reg [31:0][15:0] ram;

  always @(*) begin
    if (en) begin
    	read <= ram[addr];
        if (!rw) ram[addr] <= write;
    end
  end
endmodule
module ram(en, rw, addr, write, read);

  input en;
  input reg rw;
  input reg [10:0] addr;
  input reg [7:0] write;
  output reg [7:0] read;
  reg [31:0][15:0] ram;

  always @(*) begin
    if (en) begin
    	read <= ram[addr];
        if (!rw) ram[addr] <= write;
    end
  end
endmodule