data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/atmux1.v
data/verilator_xmls/93718e9a-d6c7-4a01-9e49-8933c66c5790.xml
module atmux1 (a, b, sela, o);

input   a,
        b,
        sela;

output  o;



wire    o;
assign  o = sela ? a : b;

endmodule
module atmux1 (a, b, sela, o);


input   a,
        b,
        sela;

output  o;



wire    o;
assign  o = sela ? a : b;

endmodule