data/full_repos/permissive/459233267/cpu.v
1: b'%Error: data/full_repos/permissive/459233267/cpu.v:3: Cannot find include file: eprom.v\n`include "eprom.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/459233267,data/full_repos/permissive/459233267/eprom.v\n             data/full_repos/permissive/459233267,data/full_repos/permissive/459233267/eprom.v.v\n             data/full_repos/permissive/459233267,data/full_repos/permissive/459233267/eprom.v.sv\n             eprom.v\n             eprom.v.v\n             eprom.v.sv\n             obj_dir/eprom.v\n             obj_dir/eprom.v.v\n             obj_dir/eprom.v.sv\n%Error: data/full_repos/permissive/459233267/cpu.v:4: Cannot find include file: sram.v\n`include "sram.v" \n         ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/459233267/cpu.v:170: Unsupported: Ignoring delay on this delayed statement.\n    #5 clk = ~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/459233267/cpu.v:175: Unsupported: Ignoring delay on this delayed statement.\n    #3 rst = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/459233267/cpu.v:180: Unsupported: Ignoring delay on this delayed statement.\n    #159 buff_in = 8\'d9; \n    ^\n%Error: data/full_repos/permissive/459233267/cpu.v:184: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/459233267/cpu.v:185: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,tb);\n    ^~~~~~~~~\n%Error: Exiting due to 4 error(s), 3 warning(s)\n'
module top_cpu(
    input clk, rst,
    input [7:0] buff_in,
    output [7:0] buff_out
);

wire [4:0] w_ab;
wire [7:0] w_db;
wire w_rd,w_wr;

cpu i_cpu(
    .clk(clk),
    .rst(rst),
    .data_bus(w_db),
    .adr_bus(w_ab),
    .buff_in(buff_in),
    .buff_out(buff_out),
    .rd(w_rd),
    .wr(w_wr)
);

eprom i_eprom(
    .clk(clk),
    .cs(w_ab[4]),
    .rd(w_rd),
    .dr(w_db),
    .ar(w_ab[3:0])      
);

sram i_sram(
    .clk(clk),
    .cs(~w_ab[4]),
    .rd(w_rd),
    .wr(w_wr),
    .ar(w_ab[3:0]),
    .dr(w_db)
);

endmodule
module top_cpu(
    input clk, rst,
    input [7:0] buff_in,
    output [7:0] buff_out
);


wire [4:0] w_ab;
wire [7:0] w_db;
wire w_rd,w_wr;

cpu i_cpu(
    .clk(clk),
    .rst(rst),
    .data_bus(w_db),
    .adr_bus(w_ab),
    .buff_in(buff_in),
    .buff_out(buff_out),
    .rd(w_rd),
    .wr(w_wr)
);

eprom i_eprom(
    .clk(clk),
    .cs(w_ab[4]),
    .rd(w_rd),
    .dr(w_db),
    .ar(w_ab[3:0])      
);

sram i_sram(
    .clk(clk),
    .cs(~w_ab[4]),
    .rd(w_rd),
    .wr(w_wr),
    .ar(w_ab[3:0]),
    .dr(w_db)
);

endmodule