data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv
1: b'%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:1: Cannot find include file: csr_define.h\n`include "csr_define.h" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/421030651/src/cpu,data/full_repos/permissive/421030651/csr_define.h\n             data/full_repos/permissive/421030651/src/cpu,data/full_repos/permissive/421030651/csr_define.h.v\n             data/full_repos/permissive/421030651/src/cpu,data/full_repos/permissive/421030651/csr_define.h.sv\n             csr_define.h\n             csr_define.h.v\n             csr_define.h.sv\n             obj_dir/csr_define.h\n             obj_dir/csr_define.h.v\n             obj_dir/csr_define.h.sv\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:9: Define or directive not defined: \'`SATP_PPN_WIDTH\'\n    output logic [ `SATP_PPN_WIDTH-1:0] satp_ppn,\n                   ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:10: Define or directive not defined: \'`SATP_ASID_WIDTH\'\n    output logic [`SATP_ASID_WIDTH-1:0] satp_asid,\n                  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:11: Define or directive not defined: \'`SATP_MODE_WIDTH\'\n    output logic [`SATP_MODE_WIDTH-1:0] satp_mode,\n                  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:17: Define or directive not defined: \'`XLEN\'\n    input        [           `XLEN-1:0] csr_sdata,\n                             ^~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:18: Define or directive not defined: \'`XLEN\'\n    input        [           `XLEN-1:0] csr_cdata,\n                             ^~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:19: Define or directive not defined: \'`XLEN\'\n    output logic [           `XLEN-1:0] csr_rdata\n                             ^~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:22: Define or directive not defined: \'`XLEN\'\nlogic [           `XLEN-1:0] satp;\n                  ^~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:27: Define or directive not defined: \'`SATP32_MODE_WIDTH\'\nassign satp = misa_mxl == 2\'h1 ? {32\'b0, satp_mode[0+:`SATP32_MODE_WIDTH],\n                                                      ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:27: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nassign satp = misa_mxl == 2\'h1 ? {32\'b0, satp_mode[0+:`SATP32_MODE_WIDTH],\n                                                                        ^\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:28: Define or directive not defined: \'`SATP32_ASID_WIDTH\'\n                                         satp_asid[0+:`SATP32_ASID_WIDTH],\n                                                      ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:29: Define or directive not defined: \'`SATP32_PPN_WIDTH\'\n                                         satp_ppn [0+:`SATP32_PPN_WIDTH]}:\n                                                      ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:35: Define or directive not defined: \'`SATP_PPN_WIDTH\'\n        satp_ppn  <= `SATP_PPN_WIDTH\'b0;\n                     ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:36: Define or directive not defined: \'`SATP_ASID_WIDTH\'\n        satp_asid <= `SATP_ASID_WIDTH\'b0;\n                     ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:37: Define or directive not defined: \'`SATP_MODE_WIDTH\'\n        satp_mode <= `SATP_MODE_WIDTH\'b0;\n                     ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:39: Define or directive not defined: \'`CSR_SATP_ADDR\'\n    else if (csr_wr && csr_waddr == `CSR_SATP_ADDR) begin\n                                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:39: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    else if (csr_wr && csr_waddr == `CSR_SATP_ADDR) begin\n                                                  ^\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:45: Define or directive not defined: \'`CSR_WDATA\'\n        satp_ppn  <= misa_mxl == 2\'h1 ? `CSR_WDATA(satp_ppn , `SATP32_PPN_BIT):\n                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:45: Define or directive not defined: \'`SATP32_PPN_BIT\'\n        satp_ppn  <= misa_mxl == 2\'h1 ? `CSR_WDATA(satp_ppn , `SATP32_PPN_BIT):\n                                                              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:46: Define or directive not defined: \'`CSR_WDATA\'\n                                        `CSR_WDATA(satp_ppn , `SATP64_PPN_BIT);\n                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:46: Define or directive not defined: \'`SATP64_PPN_BIT\'\n                                        `CSR_WDATA(satp_ppn , `SATP64_PPN_BIT);\n                                                              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:47: Define or directive not defined: \'`CSR_WDATA\'\n        satp_asid <= misa_mxl == 2\'h1 ? `CSR_WDATA(satp_asid, `SATP32_ASID_BIT):\n                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:47: syntax error, unexpected \',\'\n        satp_asid <= misa_mxl == 2\'h1 ? `CSR_WDATA(satp_asid, `SATP32_ASID_BIT):\n                                                            ^\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:47: Define or directive not defined: \'`SATP32_ASID_BIT\'\n        satp_asid <= misa_mxl == 2\'h1 ? `CSR_WDATA(satp_asid, `SATP32_ASID_BIT):\n                                                              ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:48: Define or directive not defined: \'`CSR_WDATA\'\n                                        `CSR_WDATA(satp_asid, `SATP64_ASID_BIT);\n                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:48: Define or directive not defined: \'`SATP64_ASID_BIT\'\n                                        `CSR_WDATA(satp_asid, `SATP64_ASID_BIT);\n                                                              ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:49: Define or directive not defined: \'`CSR_WDATA\'\n        satp_mode <= misa_mxl == 2\'h1 ? `CSR_WDATA(satp_mode, `SATP32_MODE_BIT):\n                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:49: syntax error, unexpected \',\'\n        satp_mode <= misa_mxl == 2\'h1 ? `CSR_WDATA(satp_mode, `SATP32_MODE_BIT):\n                                                            ^\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:49: Define or directive not defined: \'`SATP32_MODE_BIT\'\n        satp_mode <= misa_mxl == 2\'h1 ? `CSR_WDATA(satp_mode, `SATP32_MODE_BIT):\n                                                              ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:50: Define or directive not defined: \'`CSR_WDATA\'\n                                        `CSR_WDATA(satp_mode, `SATP64_MODE_BIT);\n                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:50: Define or directive not defined: \'`SATP64_MODE_BIT\'\n                                        `CSR_WDATA(satp_mode, `SATP64_MODE_BIT);\n                                                              ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:56: Define or directive not defined: \'`XLEN\'\n    csr_rdata = `XLEN\'b0;\n                ^~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:58: Define or directive not defined: \'`CSR_SATP_ADDR\'\n        `CSR_SATP_ADDR   : csr_rdata = satp;\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mmu_csr.sv:58: syntax error, unexpected \':\', expecting endcase\n        `CSR_SATP_ADDR   : csr_rdata = satp;\n                         ^\n%Error: Cannot continue\n'
module mmu_csr (
    input                               clk,
    input                               rstn,

    input        [                 1:0] misa_mxl,

    output logic [ `SATP_PPN_WIDTH-1:0] satp_ppn,
    output logic [`SATP_ASID_WIDTH-1:0] satp_asid,
    output logic [`SATP_MODE_WIDTH-1:0] satp_mode,

    input                               csr_wr,
    input        [                11:0] csr_waddr,
    input        [                11:0] csr_raddr,

    input        [           `XLEN-1:0] csr_sdata,
    input        [           `XLEN-1:0] csr_cdata,
    output logic [           `XLEN-1:0] csr_rdata
);

logic [           `XLEN-1:0] satp;

`ifdef RV32
assign satp = {satp_mode, satp_asid, satp_ppn};
`else
assign satp = misa_mxl == 2'h1 ? {32'b0, satp_mode[0+:`SATP32_MODE_WIDTH],
                                         satp_asid[0+:`SATP32_ASID_WIDTH],
                                         satp_ppn [0+:`SATP32_PPN_WIDTH]}:
                                 {satp_mode, satp_asid, satp_ppn};
`endif

always_ff @(posedge clk or negedge rstn) begin
    if (~rstn) begin
        satp_ppn  <= `SATP_PPN_WIDTH'b0;
        satp_asid <= `SATP_ASID_WIDTH'b0;
        satp_mode <= `SATP_MODE_WIDTH'b0;
    end
    else if (csr_wr && csr_waddr == `CSR_SATP_ADDR) begin
`ifdef RV32
        satp_ppn  <= `CSR_WDATA(satp_ppn ,  `SATP32_PPN_BIT);
        satp_asid <= `CSR_WDATA(satp_asid, `SATP32_ASID_BIT);
        satp_mode <= `CSR_WDATA(satp_mode, `SATP32_MODE_BIT);
`else
        satp_ppn  <= misa_mxl == 2'h1 ? `CSR_WDATA(satp_ppn , `SATP32_PPN_BIT):
                                        `CSR_WDATA(satp_ppn , `SATP64_PPN_BIT);
        satp_asid <= misa_mxl == 2'h1 ? `CSR_WDATA(satp_asid, `SATP32_ASID_BIT):
                                        `CSR_WDATA(satp_asid, `SATP64_ASID_BIT);
        satp_mode <= misa_mxl == 2'h1 ? `CSR_WDATA(satp_mode, `SATP32_MODE_BIT):
                                        `CSR_WDATA(satp_mode, `SATP64_MODE_BIT);
`endif
    end
end

always_comb begin
    csr_rdata = `XLEN'b0;
    case (csr_raddr) 
        `CSR_SATP_ADDR   : csr_rdata = satp;
    endcase
end

endmodule
module mmu_csr (
    input                               clk,
    input                               rstn,

    input        [                 1:0] misa_mxl,

    output logic [ `SATP_PPN_WIDTH-1:0] satp_ppn,
    output logic [`SATP_ASID_WIDTH-1:0] satp_asid,
    output logic [`SATP_MODE_WIDTH-1:0] satp_mode,

    input                               csr_wr,
    input        [                11:0] csr_waddr,
    input        [                11:0] csr_raddr,

    input        [           `XLEN-1:0] csr_sdata,
    input        [           `XLEN-1:0] csr_cdata,
    output logic [           `XLEN-1:0] csr_rdata
);


logic [           `XLEN-1:0] satp;

`ifdef RV32
assign satp = {satp_mode, satp_asid, satp_ppn};
`else
assign satp = misa_mxl == 2'h1 ? {32'b0, satp_mode[0+:`SATP32_MODE_WIDTH],
                                         satp_asid[0+:`SATP32_ASID_WIDTH],
                                         satp_ppn [0+:`SATP32_PPN_WIDTH]}:
                                 {satp_mode, satp_asid, satp_ppn};
`endif

always_ff @(posedge clk or negedge rstn) begin
    if (~rstn) begin
        satp_ppn  <= `SATP_PPN_WIDTH'b0;
        satp_asid <= `SATP_ASID_WIDTH'b0;
        satp_mode <= `SATP_MODE_WIDTH'b0;
    end
    else if (csr_wr && csr_waddr == `CSR_SATP_ADDR) begin
`ifdef RV32
        satp_ppn  <= `CSR_WDATA(satp_ppn ,  `SATP32_PPN_BIT);
        satp_asid <= `CSR_WDATA(satp_asid, `SATP32_ASID_BIT);
        satp_mode <= `CSR_WDATA(satp_mode, `SATP32_MODE_BIT);
`else
        satp_ppn  <= misa_mxl == 2'h1 ? `CSR_WDATA(satp_ppn , `SATP32_PPN_BIT):
                                        `CSR_WDATA(satp_ppn , `SATP64_PPN_BIT);
        satp_asid <= misa_mxl == 2'h1 ? `CSR_WDATA(satp_asid, `SATP32_ASID_BIT):
                                        `CSR_WDATA(satp_asid, `SATP64_ASID_BIT);
        satp_mode <= misa_mxl == 2'h1 ? `CSR_WDATA(satp_mode, `SATP32_MODE_BIT):
                                        `CSR_WDATA(satp_mode, `SATP64_MODE_BIT);
`endif
    end
end

always_comb begin
    csr_rdata = `XLEN'b0;
    case (csr_raddr) 
        `CSR_SATP_ADDR   : csr_rdata = satp;
    endcase
end

endmodule