data/full_repos/permissive/474104412/hardware/src/system_core.v
1: b'%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:2: Cannot find include file: system.vh\n`include "system.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/474104412/hardware/src,data/full_repos/permissive/474104412/system.vh\n             data/full_repos/permissive/474104412/hardware/src,data/full_repos/permissive/474104412/system.vh.v\n             data/full_repos/permissive/474104412/hardware/src,data/full_repos/permissive/474104412/system.vh.sv\n             system.vh\n             system.vh.v\n             system.vh.sv\n             obj_dir/system.vh\n             obj_dir/system.vh.v\n             obj_dir/system.vh.sv\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:3: Cannot find include file: iob_lib.vh\n`include "iob_lib.vh" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:4: Cannot find include file: iob_intercon.vh\n`include "iob_intercon.vh" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:30: Cannot find include file: iob_gen_if.vh\n`include "iob_gen_if.vh" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:11: Define or directive not defined: \'`ADDR_W\'\n    parameter ADDR_W=`ADDR_W,\n                     ^~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:11: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    parameter ADDR_W=`ADDR_W,\n                            ^\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:12: Define or directive not defined: \'`DATA_W\'\n    parameter DATA_W=`DATA_W,\n                     ^~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:12: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    parameter DATA_W=`DATA_W,\n                            ^\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:14: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter AXI_ADDR_W=`ADDR_W,\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:14: Define or directive not defined: \'`ADDR_W\'\n    parameter AXI_ADDR_W=`ADDR_W,\n                         ^~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:14: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    parameter AXI_ADDR_W=`ADDR_W,\n                                ^\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:15: Define or directive not defined: \'`DATA_W\'\n    parameter AXI_DATA_W=`DATA_W\n                         ^~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:16: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    )\n    ^\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:45: Define or directive not defined: \'`REQ_W\'\n   wire [`REQ_W-1:0] cpu_i_req;\n         ^~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:46: Define or directive not defined: \'`RESP_W\'\n   wire [`RESP_W-1:0] cpu_i_resp;\n         ^~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:49: Define or directive not defined: \'`REQ_W\'\n   wire [`REQ_W-1:0]         cpu_d_req;\n         ^~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:50: Define or directive not defined: \'`RESP_W\'\n   wire [`RESP_W-1:0]        cpu_d_resp;\n         ^~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:52: Define or directive not defined: \'`N_CORES\'\n   wire [`N_CORES-1:0]       timerInterrupt;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:53: Define or directive not defined: \'`N_CORES\'\n   wire [`N_CORES-1:0]       softwareInterrupt;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:54: Define or directive not defined: \'`N_CORES\'\n   wire [`N_CORES-1:0]       externalInterrupt;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:58: syntax error, unexpected IDENTIFIER\n   iob_VexRiscv cpu\n   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:85: Define or directive not defined: \'`REQ_W\'\n   wire [`REQ_W-1:0]  int_mem_i_req;\n         ^~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:86: Define or directive not defined: \'`RESP_W\'\n   wire [`RESP_W-1:0] int_mem_i_resp;\n         ^~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:94: syntax error, unexpected IDENTIFIER\n   iob_split\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:101: Define or directive not defined: \'`E_BIT\'\n       .P_SLAVES(`E_BIT)\n                 ^~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:157: Define or directive not defined: \'`REQ_W\'\n   wire [`REQ_W-1:0]         int_mem_d_req;\n         ^~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:158: Define or directive not defined: \'`RESP_W\'\n   wire [`RESP_W-1:0]        int_mem_d_resp;\n         ^~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:160: Define or directive not defined: \'`REQ_W\'\n   wire [`REQ_W-1:0]         pbus_req;\n         ^~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:161: Define or directive not defined: \'`RESP_W\'\n   wire [`RESP_W-1:0]        pbus_resp;\n         ^~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:163: syntax error, unexpected IDENTIFIER\n   iob_split\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:166: Define or directive not defined: \'`P_BIT\'\n       .P_SLAVES(`P_BIT)\n                 ^~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:194: Define or directive not defined: \'`N_SLAVES\'\n   wire [`N_SLAVES*`REQ_W-1:0] slaves_req;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:194: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n   wire [`N_SLAVES*`REQ_W-1:0] slaves_req;\n                  ^\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:194: Define or directive not defined: \'`REQ_W\'\n   wire [`N_SLAVES*`REQ_W-1:0] slaves_req;\n                   ^~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:195: Define or directive not defined: \'`N_SLAVES\'\n   wire [`N_SLAVES*`RESP_W-1:0] slaves_resp;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:195: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n   wire [`N_SLAVES*`RESP_W-1:0] slaves_resp;\n                  ^\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:195: Define or directive not defined: \'`RESP_W\'\n   wire [`N_SLAVES*`RESP_W-1:0] slaves_resp;\n                   ^~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:199: Define or directive not defined: \'`N_SLAVES\'\n       .N_SLAVES(`N_SLAVES),\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/system_core.v:200: Define or directive not defined: \'`P_BIT\'\n       .P_SLAVES(`P_BIT-1)\n                 ^~~~~~\n%Error: Exiting due to 39 error(s)\n'
module system
  #(
    parameter ADDR_W=`ADDR_W,
    parameter DATA_W=`DATA_W,
    parameter AXI_ID_W=0,
    parameter AXI_ADDR_W=`ADDR_W,
    parameter AXI_DATA_W=`DATA_W
    )
  (




   output trap,
          
          
`ifdef USE_DDR 

 `include "m_axi_m_port.vh"
`endif
          
`include "iob_gen_if.vh"
   );
   




   wire   boot;
   wire   cpu_reset;
   





   wire [`REQ_W-1:0] cpu_i_req;
   wire [`RESP_W-1:0] cpu_i_resp;


   wire [`REQ_W-1:0]         cpu_d_req;
   wire [`RESP_W-1:0]        cpu_d_resp;

   wire [`N_CORES-1:0]       timerInterrupt;
   wire [`N_CORES-1:0]       softwareInterrupt;
   wire [`N_CORES-1:0]       externalInterrupt;



   iob_VexRiscv cpu
       (
        .clk     (clk),
        .rst     (cpu_reset),
        .boot    (boot),
        .trap    (trap),


        .ibus_req(cpu_i_req),
        .ibus_resp(cpu_i_resp),


        .dbus_req(cpu_d_req),
        .dbus_resp(cpu_d_resp),


        .timerInterrupt(timerInterrupt),
        .softwareInterrupt(softwareInterrupt),
        .externalInterrupt(externalInterrupt)
        );







   wire [`REQ_W-1:0]  int_mem_i_req;
   wire [`RESP_W-1:0] int_mem_i_resp;

`ifdef RUN_EXTMEM
   wire [`REQ_W-1:0]  ext_mem_i_req;
   wire [`RESP_W-1:0] ext_mem_i_resp;
`endif


   iob_split
     #(
`ifdef RUN_EXTMEM
       .N_SLAVES(2),
`else
       .N_SLAVES(1),
`endif
       .P_SLAVES(`E_BIT)
       )
   ibus_split
     (
      .clk (clk),
      .rst (cpu_reset),

      .m_req (cpu_i_req),
      .m_resp (cpu_i_resp),
      

`ifdef RUN_EXTMEM
      .s_req ( {ext_mem_i_req, int_mem_i_req} ),
      .s_resp ( {ext_mem_i_resp, int_mem_i_resp} )
`else
      .s_req (int_mem_i_req),
      .s_resp ( int_mem_i_resp)
`endif
      );




`ifdef USE_DDR

   wire [`REQ_W-1:0]         ext_mem_d_req;
   wire [`RESP_W-1:0]        ext_mem_d_resp;

   wire [`REQ_W-1:0]         int_d_req;
   wire [`RESP_W-1:0]        int_d_resp;

   iob_split
     #(
       .N_SLAVES(2),
       .P_SLAVES(`E_BIT)
       )
   dbus_split
     (
      .clk    ( clk   ),
      .rst    ( cpu_reset ),


      .m_req  ( cpu_d_req  ),
      .m_resp ( cpu_d_resp ),


      .s_req  ( {ext_mem_d_req, int_d_req}   ),
      .s_resp ( {ext_mem_d_resp, int_d_resp} )
      );
`endif






   wire [`REQ_W-1:0]         int_mem_d_req;
   wire [`RESP_W-1:0]        int_mem_d_resp;

   wire [`REQ_W-1:0]         pbus_req;
   wire [`RESP_W-1:0]        pbus_resp;

   iob_split
     #(
       .N_SLAVES(2),
       .P_SLAVES(`P_BIT)
       )
   int_dbus_split
     (
      .clk (clk),
      .rst (cpu_reset),

`ifdef USE_DDR

      .m_req  ( int_d_req  ),
      .m_resp ( int_d_resp ),
`else

      .m_req  ( cpu_d_req  ),
      .m_resp ( cpu_d_resp ),
`endif


      .s_req  ( {pbus_req, int_mem_d_req}   ),
      .s_resp ( {pbus_resp, int_mem_d_resp} )
      );







   wire [`N_SLAVES*`REQ_W-1:0] slaves_req;
   wire [`N_SLAVES*`RESP_W-1:0] slaves_resp;

   iob_split
     #(
       .N_SLAVES(`N_SLAVES),
       .P_SLAVES(`P_BIT-1)
       )
   pbus_split
     (
      .clk (clk),
      .rst (cpu_reset),

      .m_req (pbus_req),
      .m_resp (pbus_resp),
      

      .s_req (slaves_req),
      .s_resp (slaves_resp)
      );






   int_mem int_mem0
     (
      .clk (clk),
      .rst (rst),
      .boot (boot),
      .cpu_reset (cpu_reset),


      .i_req (int_mem_i_req),
      .i_resp (int_mem_i_resp),


      .d_req (int_mem_d_req),
      .d_resp (int_mem_d_resp)
      );

`ifdef USE_DDR



   ext_mem
     #(
       .AXI_ID_W(AXI_ID_W),
       .AXI_ADDR_W(AXI_ADDR_W),
       .AXI_DATA_W(AXI_DATA_W)
       )
   ext_mem0
   (
 `ifdef RUN_EXTMEM

      .i_req ( {ext_mem_i_req[`valid(0)], ext_mem_i_req[`address(0, `FIRM_ADDR_W)-2], ext_mem_i_req[`write(0)]} ),
      .i_resp (ext_mem_i_resp),
 `endif

      .d_req ( {ext_mem_d_req[`valid(0)], ext_mem_d_req[`address(0, `DCACHE_ADDR_W+1)-2], ext_mem_d_req[`write(0)]} ),
      .d_resp (ext_mem_d_resp),


`include "m_axi_portmap.vh"
      .clk (clk),
      .rst (cpu_reset)
      );
`endif



endmodule
module system
  #(
    parameter ADDR_W=`ADDR_W,
    parameter DATA_W=`DATA_W,
    parameter AXI_ID_W=0,
    parameter AXI_ADDR_W=`ADDR_W,
    parameter AXI_DATA_W=`DATA_W
    )
  (




   output trap,
          
          
`ifdef USE_DDR 

 `include "m_axi_m_port.vh"
`endif
          
`include "iob_gen_if.vh"
   );

   




   wire   boot;
   wire   cpu_reset;
   





   wire [`REQ_W-1:0] cpu_i_req;
   wire [`RESP_W-1:0] cpu_i_resp;


   wire [`REQ_W-1:0]         cpu_d_req;
   wire [`RESP_W-1:0]        cpu_d_resp;

   wire [`N_CORES-1:0]       timerInterrupt;
   wire [`N_CORES-1:0]       softwareInterrupt;
   wire [`N_CORES-1:0]       externalInterrupt;



   iob_VexRiscv cpu
       (
        .clk     (clk),
        .rst     (cpu_reset),
        .boot    (boot),
        .trap    (trap),


        .ibus_req(cpu_i_req),
        .ibus_resp(cpu_i_resp),


        .dbus_req(cpu_d_req),
        .dbus_resp(cpu_d_resp),


        .timerInterrupt(timerInterrupt),
        .softwareInterrupt(softwareInterrupt),
        .externalInterrupt(externalInterrupt)
        );







   wire [`REQ_W-1:0]  int_mem_i_req;
   wire [`RESP_W-1:0] int_mem_i_resp;

`ifdef RUN_EXTMEM
   wire [`REQ_W-1:0]  ext_mem_i_req;
   wire [`RESP_W-1:0] ext_mem_i_resp;
`endif


   iob_split
     #(
`ifdef RUN_EXTMEM
       .N_SLAVES(2),
`else
       .N_SLAVES(1),
`endif
       .P_SLAVES(`E_BIT)
       )
   ibus_split
     (
      .clk (clk),
      .rst (cpu_reset),

      .m_req (cpu_i_req),
      .m_resp (cpu_i_resp),
      

`ifdef RUN_EXTMEM
      .s_req ( {ext_mem_i_req, int_mem_i_req} ),
      .s_resp ( {ext_mem_i_resp, int_mem_i_resp} )
`else
      .s_req (int_mem_i_req),
      .s_resp ( int_mem_i_resp)
`endif
      );




`ifdef USE_DDR

   wire [`REQ_W-1:0]         ext_mem_d_req;
   wire [`RESP_W-1:0]        ext_mem_d_resp;

   wire [`REQ_W-1:0]         int_d_req;
   wire [`RESP_W-1:0]        int_d_resp;

   iob_split
     #(
       .N_SLAVES(2),
       .P_SLAVES(`E_BIT)
       )
   dbus_split
     (
      .clk    ( clk   ),
      .rst    ( cpu_reset ),


      .m_req  ( cpu_d_req  ),
      .m_resp ( cpu_d_resp ),


      .s_req  ( {ext_mem_d_req, int_d_req}   ),
      .s_resp ( {ext_mem_d_resp, int_d_resp} )
      );
`endif






   wire [`REQ_W-1:0]         int_mem_d_req;
   wire [`RESP_W-1:0]        int_mem_d_resp;

   wire [`REQ_W-1:0]         pbus_req;
   wire [`RESP_W-1:0]        pbus_resp;

   iob_split
     #(
       .N_SLAVES(2),
       .P_SLAVES(`P_BIT)
       )
   int_dbus_split
     (
      .clk (clk),
      .rst (cpu_reset),

`ifdef USE_DDR

      .m_req  ( int_d_req  ),
      .m_resp ( int_d_resp ),
`else

      .m_req  ( cpu_d_req  ),
      .m_resp ( cpu_d_resp ),
`endif


      .s_req  ( {pbus_req, int_mem_d_req}   ),
      .s_resp ( {pbus_resp, int_mem_d_resp} )
      );







   wire [`N_SLAVES*`REQ_W-1:0] slaves_req;
   wire [`N_SLAVES*`RESP_W-1:0] slaves_resp;

   iob_split
     #(
       .N_SLAVES(`N_SLAVES),
       .P_SLAVES(`P_BIT-1)
       )
   pbus_split
     (
      .clk (clk),
      .rst (cpu_reset),

      .m_req (pbus_req),
      .m_resp (pbus_resp),
      

      .s_req (slaves_req),
      .s_resp (slaves_resp)
      );






   int_mem int_mem0
     (
      .clk (clk),
      .rst (rst),
      .boot (boot),
      .cpu_reset (cpu_reset),


      .i_req (int_mem_i_req),
      .i_resp (int_mem_i_resp),


      .d_req (int_mem_d_req),
      .d_resp (int_mem_d_resp)
      );

`ifdef USE_DDR



   ext_mem
     #(
       .AXI_ID_W(AXI_ID_W),
       .AXI_ADDR_W(AXI_ADDR_W),
       .AXI_DATA_W(AXI_DATA_W)
       )
   ext_mem0
   (
 `ifdef RUN_EXTMEM

      .i_req ( {ext_mem_i_req[`valid(0)], ext_mem_i_req[`address(0, `FIRM_ADDR_W)-2], ext_mem_i_req[`write(0)]} ),
      .i_resp (ext_mem_i_resp),
 `endif

      .d_req ( {ext_mem_d_req[`valid(0)], ext_mem_d_req[`address(0, `DCACHE_ADDR_W+1)-2], ext_mem_d_req[`write(0)]} ),
      .d_resp (ext_mem_d_resp),


`include "m_axi_portmap.vh"
      .clk (clk),
      .rst (cpu_reset)
      );
`endif



endmodule