data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/sum/sum.v
1: b'%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/sum/sum.v:2: Extra underscore in meta-comment; use /*synopsys {...}*/ not /*synopsys_{...}*/\n// synopsys_ template \n^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n'
module sum
#(
	parameter N=8,
	parameter CC=1
)
( 
	clk,
	rst,
	g_input,
	e_input,
	o
);
	input clk, rst;
	input  [N/CC-1:0] g_input;
	input  [N/CC-1:0] e_input;
	output [N/CC-1:0] o;
	

	reg carry_on; 
	wire carry_on_d;


	generate
	if(CC>1)
	begin
		always@(posedge clk or posedge rst)
		begin
			if(rst)
				carry_on <= 0;
			else
				carry_on <= carry_on_d;
		end
	end
	endgenerate

	generate
	if(CC>1)
	begin

		ADD 
		#(
			.N(N/CC)
		)
		ADD_
		(
			.A(g_input),
			.B(e_input),
			.CI(carry_on),
			.S(o),
			.CO(carry_on_d)
		);
	end
	else
	begin

		ADD 
		#(
			.N(N/CC)
		)
		ADD_
		(
			.A(g_input),
			.B(e_input),
			.CI(1'b0),
			.S(o),
			.CO()
		);
	end
	endgenerate
endmodule
module sum
#(
	parameter N=8,
	parameter CC=1
)
( 
	clk,
	rst,
	g_input,
	e_input,
	o
);

	input clk, rst;
	input  [N/CC-1:0] g_input;
	input  [N/CC-1:0] e_input;
	output [N/CC-1:0] o;
	

	reg carry_on; 
	wire carry_on_d;


	generate
	if(CC>1)
	begin
		always@(posedge clk or posedge rst)
		begin
			if(rst)
				carry_on <= 0;
			else
				carry_on <= carry_on_d;
		end
	end
	endgenerate

	generate
	if(CC>1)
	begin

		ADD 
		#(
			.N(N/CC)
		)
		ADD_
		(
			.A(g_input),
			.B(e_input),
			.CI(carry_on),
			.S(o),
			.CO(carry_on_d)
		);
	end
	else
	begin

		ADD 
		#(
			.N(N/CC)
		)
		ADD_
		(
			.A(g_input),
			.B(e_input),
			.CI(1'b0),
			.S(o),
			.CO()
		);
	end
	endgenerate
endmodule