data/full_repos/permissive/482975152/PipelinedProcessor.srcs/sources_1/new/PC.v
data/verilator_xmls/93a8b2dd-85fa-49db-871c-b0427420870e.xml
module PC(
    input clk,
    input EN,
    input [31:0] PCIn,
    output reg [31:0] PCOut
    );
    
    initial begin
        PCOut <= 0;
    end
    
    always @(posedge clk) begin
        if (EN == 1) begin
            PCOut <= PCOut;
        end
        else begin
            PCOut <= PCIn;
        end
    end
endmodule
module PC(
    input clk,
    input EN,
    input [31:0] PCIn,
    output reg [31:0] PCOut
    );

    
    initial begin
        PCOut <= 0;
    end
    
    always @(posedge clk) begin
        if (EN == 1) begin
            PCOut <= PCOut;
        end
        else begin
            PCOut <= PCIn;
        end
    end
endmodule