data/full_repos/permissive/422650017/verilog/rtl/elpis/arbiter.v
1: b'%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/arbiter.v:17: Cannot find include file: /project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v\n    `include "/project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v" \n             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/422650017/verilog/rtl/elpis,data/full_repos/permissive/422650017//project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v\n             data/full_repos/permissive/422650017/verilog/rtl/elpis,data/full_repos/permissive/422650017//project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v.v\n             data/full_repos/permissive/422650017/verilog/rtl/elpis,data/full_repos/permissive/422650017//project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v.sv\n             /project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v\n             /project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v.v\n             /project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v.sv\n             obj_dir//project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v\n             obj_dir//project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v.v\n             obj_dir//project/openlane/user_proj_example/../../verilog/rtl/elpis/definitions.v.sv\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/arbiter.v:52: Define or directive not defined: \'`ARB_IDLE_STATE\'\n   arb_state <= `ARB_IDLE_STATE;\n                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/arbiter.v:52: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   arb_state <= `ARB_IDLE_STATE;\n                               ^\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/arbiter.v:59: Define or directive not defined: \'`ARB_IDLE_STATE\'\n            `ARB_IDLE_STATE: begin\n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/arbiter.v:59: syntax error, unexpected \':\', expecting endcase\n            `ARB_IDLE_STATE: begin\n                           ^\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/arbiter.v:60: Define or directive not defined: \'`ARB_DCACHE_REQUEST\'\n                if (dcache_request && hit_dtlb_in) next_arb_state <= `ARB_DCACHE_REQUEST;\n                                                                     ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/arbiter.v:61: Define or directive not defined: \'`ARB_ICACHE_REQUEST\'\n                else if (icache_request && hit_itlb_in) next_arb_state <= `ARB_ICACHE_REQUEST;\n                                                                          ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/arbiter.v:62: Define or directive not defined: \'`ARB_IDLE_STATE\'\n                else next_arb_state <= `ARB_IDLE_STATE;\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/arbiter.v:64: Define or directive not defined: \'`ARB_DCACHE_REQUEST\'\n            `ARB_DCACHE_REQUEST: begin\n            ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/arbiter.v:64: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `ARB_DCACHE_REQUEST: begin\n                                 ^~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/arbiter.v:65: Define or directive not defined: \'`ARB_DCACHE_WAIT\'\n                next_arb_state <= `ARB_DCACHE_WAIT;\n                                  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/arbiter.v:67: Define or directive not defined: \'`ARB_ICACHE_REQUEST\'\n            `ARB_ICACHE_REQUEST: begin\n            ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/arbiter.v:67: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `ARB_ICACHE_REQUEST: begin\n                                 ^~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/arbiter.v:68: Define or directive not defined: \'`ARB_ICACHE_WAIT\'\n                next_arb_state <= `ARB_ICACHE_WAIT;\n                                  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/arbiter.v:70: Define or directive not defined: \'`ARB_DCACHE_WAIT\'\n            `ARB_DCACHE_WAIT: begin\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/arbiter.v:70: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `ARB_DCACHE_WAIT: begin\n                              ^~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/arbiter.v:72: Define or directive not defined: \'`ARB_IDLE_STATE\'\n                    next_arb_state <= `ARB_IDLE_STATE;\n                                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/arbiter.v:74: Define or directive not defined: \'`ARB_DCACHE_WAIT\'\n                    next_arb_state <= `ARB_DCACHE_WAIT;\n                                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/arbiter.v:77: Define or directive not defined: \'`ARB_ICACHE_WAIT\'\n            `ARB_ICACHE_WAIT: begin\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/arbiter.v:79: Define or directive not defined: \'`ARB_IDLE_STATE\'\n                    next_arb_state <= `ARB_IDLE_STATE;\n                                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/arbiter.v:81: Define or directive not defined: \'`ARB_ICACHE_WAIT\'\n                    next_arb_state <= `ARB_ICACHE_WAIT;\n                                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/arbiter.v:84: Define or directive not defined: \'`ARB_IDLE_STATE\'\n            default: next_arb_state <= `ARB_IDLE_STATE;\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/arbiter.v:90: Define or directive not defined: \'`ARB_IDLE_STATE\'\n            `ARB_IDLE_STATE: begin\n            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/arbiter.v:98: Define or directive not defined: \'`ARB_DCACHE_REQUEST\'\n            `ARB_DCACHE_REQUEST: begin\n            ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/arbiter.v:106: Define or directive not defined: \'`ARB_ICACHE_REQUEST\'\n            `ARB_ICACHE_REQUEST: begin\n            ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/arbiter.v:114: Define or directive not defined: \'`ARB_DCACHE_WAIT\'\n            `ARB_DCACHE_WAIT: begin\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422650017/verilog/rtl/elpis/arbiter.v:127: Define or directive not defined: \'`ARB_ICACHE_WAIT\'\n            `ARB_ICACHE_WAIT: begin\n            ^~~~~~~~~~~~~~~~\n%Error: Cannot continue\n'
module arbiter(
	input clk,
	input reset,
	output reg[19:0] mem_addr,
	input[127:0] dcache_to_mem_data_in,
	output reg[127:0] dcache_to_mem_data_out,
	output [127:0] mem_to_icache_data,
  	output [127:0] mem_to_dcache_data,
  	input[127:0] data_from_mem,
  	input dcache_we,
  	output reg mem_we,
  	input icache_request,
  	input dcache_request,
  	input mem_ready,
 	output reg is_icache_ready,
  	output reg is_dcache_ready,
  	input reset_mem_req,
  	input hit_itlb_in,
 	input hit_dtlb_in,
  	input[19:0] itlb_physical_addr_in,
  	input[19:0] dtlb_physical_addr_in,
  	input dcache_re,
    output reg is_mem_req
);

	reg[2:0] arb_state, next_arb_state;

	assign mem_to_icache_data = data_from_mem;
	assign mem_to_dcache_data = data_from_mem;

 	always@(posedge clk) begin
		if (reset || reset_mem_req) begin
			arb_state <= `ARB_IDLE_STATE;
		end
		else arb_state <= next_arb_state;
	end

    always@(dcache_request or icache_request or hit_dtlb_in or hit_itlb_in or mem_ready or arb_state) begin
        case(arb_state)
            `ARB_IDLE_STATE: begin
                if (dcache_request && hit_dtlb_in) next_arb_state <= `ARB_DCACHE_REQUEST;
                else if (icache_request && hit_itlb_in) next_arb_state <= `ARB_ICACHE_REQUEST;
                else next_arb_state <= `ARB_IDLE_STATE;
            end
            `ARB_DCACHE_REQUEST: begin
                next_arb_state <= `ARB_DCACHE_WAIT;
            end
            `ARB_ICACHE_REQUEST: begin
                next_arb_state <= `ARB_ICACHE_WAIT;
            end
            `ARB_DCACHE_WAIT: begin
                if(mem_ready)begin
                    next_arb_state <= `ARB_IDLE_STATE;
                end else begin
                    next_arb_state <= `ARB_DCACHE_WAIT;
                end
            end
            `ARB_ICACHE_WAIT: begin
                if(mem_ready) begin
                    next_arb_state <= `ARB_IDLE_STATE;
                end else begin
                    next_arb_state <= `ARB_ICACHE_WAIT;
                end
            end
            default: next_arb_state <= `ARB_IDLE_STATE;
        endcase
    end

    always@(arb_state or mem_ready) begin
        case(arb_state)
            `ARB_IDLE_STATE: begin
                is_dcache_ready <= 0;
                is_icache_ready <= 0;
                mem_we <= 0;
                dcache_to_mem_data_out <= 0;
                mem_addr <= 0;
                is_mem_req <= 1'b0;
            end
            `ARB_DCACHE_REQUEST: begin
                is_dcache_ready <= 0;
                is_icache_ready <= 0;
                mem_we <= dcache_we;
                mem_addr <= dtlb_physical_addr_in;
                dcache_to_mem_data_out <= dcache_to_mem_data_in;
                is_mem_req <= 1'b1;
            end
            `ARB_ICACHE_REQUEST: begin
                is_dcache_ready <= 0;
                is_icache_ready <= 0;
                mem_we <= 0;
                mem_addr <= itlb_physical_addr_in;
                dcache_to_mem_data_out <= 0;
                is_mem_req <= 1'b1;
            end
            `ARB_DCACHE_WAIT: begin
                if (mem_ready) begin
                    is_dcache_ready <= mem_ready;
                    is_mem_req <= 1'b0;
                end else begin
                    is_dcache_ready <= 0;
                    is_mem_req <= 1'b1;
                end
                is_icache_ready <= 0; 
                mem_we <= dcache_we;
                dcache_to_mem_data_out <= dcache_to_mem_data_in;
                mem_addr <= dtlb_physical_addr_in;
            end
            `ARB_ICACHE_WAIT: begin
                if (mem_ready) begin
                    is_icache_ready <= mem_ready;
                    is_mem_req <= 1'b0;
                end else begin
                    is_icache_ready <= 0;
                    is_mem_req <= 1'b1;
                end
                is_dcache_ready <= 0;
                mem_we <= 0;
                dcache_to_mem_data_out <= 0;
                mem_addr <= itlb_physical_addr_in;
            end
            default: begin
                is_dcache_ready <= 0;
                is_icache_ready <= 0;
                mem_we <= 0;
                dcache_to_mem_data_out <= 0;
                mem_addr <= 0;
                is_mem_req <= 1'b0;
            end
        endcase
    end

endmodule
module arbiter(
	input clk,
	input reset,
	output reg[19:0] mem_addr,
	input[127:0] dcache_to_mem_data_in,
	output reg[127:0] dcache_to_mem_data_out,
	output [127:0] mem_to_icache_data,
  	output [127:0] mem_to_dcache_data,
  	input[127:0] data_from_mem,
  	input dcache_we,
  	output reg mem_we,
  	input icache_request,
  	input dcache_request,
  	input mem_ready,
 	output reg is_icache_ready,
  	output reg is_dcache_ready,
  	input reset_mem_req,
  	input hit_itlb_in,
 	input hit_dtlb_in,
  	input[19:0] itlb_physical_addr_in,
  	input[19:0] dtlb_physical_addr_in,
  	input dcache_re,
    output reg is_mem_req
);


	reg[2:0] arb_state, next_arb_state;

	assign mem_to_icache_data = data_from_mem;
	assign mem_to_dcache_data = data_from_mem;

 	always@(posedge clk) begin
		if (reset || reset_mem_req) begin
			arb_state <= `ARB_IDLE_STATE;
		end
		else arb_state <= next_arb_state;
	end

    always@(dcache_request or icache_request or hit_dtlb_in or hit_itlb_in or mem_ready or arb_state) begin
        case(arb_state)
            `ARB_IDLE_STATE: begin
                if (dcache_request && hit_dtlb_in) next_arb_state <= `ARB_DCACHE_REQUEST;
                else if (icache_request && hit_itlb_in) next_arb_state <= `ARB_ICACHE_REQUEST;
                else next_arb_state <= `ARB_IDLE_STATE;
            end
            `ARB_DCACHE_REQUEST: begin
                next_arb_state <= `ARB_DCACHE_WAIT;
            end
            `ARB_ICACHE_REQUEST: begin
                next_arb_state <= `ARB_ICACHE_WAIT;
            end
            `ARB_DCACHE_WAIT: begin
                if(mem_ready)begin
                    next_arb_state <= `ARB_IDLE_STATE;
                end else begin
                    next_arb_state <= `ARB_DCACHE_WAIT;
                end
            end
            `ARB_ICACHE_WAIT: begin
                if(mem_ready) begin
                    next_arb_state <= `ARB_IDLE_STATE;
                end else begin
                    next_arb_state <= `ARB_ICACHE_WAIT;
                end
            end
            default: next_arb_state <= `ARB_IDLE_STATE;
        endcase
    end

    always@(arb_state or mem_ready) begin
        case(arb_state)
            `ARB_IDLE_STATE: begin
                is_dcache_ready <= 0;
                is_icache_ready <= 0;
                mem_we <= 0;
                dcache_to_mem_data_out <= 0;
                mem_addr <= 0;
                is_mem_req <= 1'b0;
            end
            `ARB_DCACHE_REQUEST: begin
                is_dcache_ready <= 0;
                is_icache_ready <= 0;
                mem_we <= dcache_we;
                mem_addr <= dtlb_physical_addr_in;
                dcache_to_mem_data_out <= dcache_to_mem_data_in;
                is_mem_req <= 1'b1;
            end
            `ARB_ICACHE_REQUEST: begin
                is_dcache_ready <= 0;
                is_icache_ready <= 0;
                mem_we <= 0;
                mem_addr <= itlb_physical_addr_in;
                dcache_to_mem_data_out <= 0;
                is_mem_req <= 1'b1;
            end
            `ARB_DCACHE_WAIT: begin
                if (mem_ready) begin
                    is_dcache_ready <= mem_ready;
                    is_mem_req <= 1'b0;
                end else begin
                    is_dcache_ready <= 0;
                    is_mem_req <= 1'b1;
                end
                is_icache_ready <= 0; 
                mem_we <= dcache_we;
                dcache_to_mem_data_out <= dcache_to_mem_data_in;
                mem_addr <= dtlb_physical_addr_in;
            end
            `ARB_ICACHE_WAIT: begin
                if (mem_ready) begin
                    is_icache_ready <= mem_ready;
                    is_mem_req <= 1'b0;
                end else begin
                    is_icache_ready <= 0;
                    is_mem_req <= 1'b1;
                end
                is_dcache_ready <= 0;
                mem_we <= 0;
                dcache_to_mem_data_out <= 0;
                mem_addr <= itlb_physical_addr_in;
            end
            default: begin
                is_dcache_ready <= 0;
                is_icache_ready <= 0;
                mem_we <= 0;
                dcache_to_mem_data_out <= 0;
                mem_addr <= 0;
                is_mem_req <= 1'b0;
            end
        endcase
    end

endmodule