data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/clk/rtl/aq_mp_clk_top.v
1: b"%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/clk/rtl/aq_mp_clk_top.v:79: Cannot find file containing module: 'BUFGCE'\nBUFGCE apb_clk_buf\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/clk/rtl,data/full_repos/permissive/418750043/BUFGCE\n             data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/clk/rtl,data/full_repos/permissive/418750043/BUFGCE.v\n             data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/clk/rtl,data/full_repos/permissive/418750043/BUFGCE.sv\n             BUFGCE\n             BUFGCE.v\n             BUFGCE.sv\n             obj_dir/BUFGCE\n             obj_dir/BUFGCE.v\n             obj_dir/BUFGCE.sv\n%Error: Exiting due to 1 error(s)\n"
module aq_mp_clk_top(
  apb_clk,
  apb_clk_en,
  axim_clk_en,
  axim_clk_en_f,
  clkgen_rst_b,
  forever_cpuclk,
  pad_yy_scan_mode,
  pll_core_cpuclk
);


input        axim_clk_en;      
input        clkgen_rst_b;     
input        pad_yy_scan_mode; 
input        pll_core_cpuclk;  
output       apb_clk;          
output       apb_clk_en;       
output       axim_clk_en_f;    
output       forever_cpuclk;   


reg          apb_clk_en_f;     
reg          axim_clk_en_f;    
reg          peripheral_clk_en; 


wire         apb_clk_en;       
wire         axim_clk_en;      
wire         clkgen_rst_b;     
wire         forever_cpuclk;   
wire         pad_yy_scan_mode; 
wire         pll_core_cpuclk;  





assign forever_cpuclk = pll_core_cpuclk;






always@(posedge forever_cpuclk or negedge clkgen_rst_b)
begin
  if (!clkgen_rst_b)
    peripheral_clk_en <= 1'b0;
  else
    peripheral_clk_en <= ~peripheral_clk_en;
end

always@(posedge forever_cpuclk)
begin
  apb_clk_en_f <= peripheral_clk_en;
end

assign apb_clk_en = pad_yy_scan_mode ? 1'b1 : apb_clk_en_f;



BUFGCE apb_clk_buf
(.O   (apb_clk),
 .I   (forever_cpuclk),
 .CE  (apb_clk_en_f)
);
















always@(posedge forever_cpuclk)
begin
  axim_clk_en_f <= axim_clk_en;
end








endmodule
module aq_mp_clk_top(
  apb_clk,
  apb_clk_en,
  axim_clk_en,
  axim_clk_en_f,
  clkgen_rst_b,
  forever_cpuclk,
  pad_yy_scan_mode,
  pll_core_cpuclk
);



input        axim_clk_en;      
input        clkgen_rst_b;     
input        pad_yy_scan_mode; 
input        pll_core_cpuclk;  
output       apb_clk;          
output       apb_clk_en;       
output       axim_clk_en_f;    
output       forever_cpuclk;   


reg          apb_clk_en_f;     
reg          axim_clk_en_f;    
reg          peripheral_clk_en; 


wire         apb_clk_en;       
wire         axim_clk_en;      
wire         clkgen_rst_b;     
wire         forever_cpuclk;   
wire         pad_yy_scan_mode; 
wire         pll_core_cpuclk;  





assign forever_cpuclk = pll_core_cpuclk;






always@(posedge forever_cpuclk or negedge clkgen_rst_b)
begin
  if (!clkgen_rst_b)
    peripheral_clk_en <= 1'b0;
  else
    peripheral_clk_en <= ~peripheral_clk_en;
end

always@(posedge forever_cpuclk)
begin
  apb_clk_en_f <= peripheral_clk_en;
end

assign apb_clk_en = pad_yy_scan_mode ? 1'b1 : apb_clk_en_f;



BUFGCE apb_clk_buf
(.O   (apb_clk),
 .I   (forever_cpuclk),
 .CE  (apb_clk_en_f)
);
















always@(posedge forever_cpuclk)
begin
  axim_clk_en_f <= axim_clk_en;
end








endmodule