data/full_repos/permissive/408955603/Sesion8/biestableD.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion8/biestableD.v:12: Unsupported: Ignoring delay on this delayed statement.\n always #7 CD[1] = ~CD[1];\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/408955603/Sesion8/biestableD.v:16: Unsupported or unknown PLI call: $monitor\n  $monitor($time, " | | C: %b, D: %b, Q: %b", CD[1], CD[0], Q);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/408955603/Sesion8/biestableD.v:17: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("saluda.dmp");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/408955603/Sesion8/biestableD.v:18: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion8/biestableD.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #5 CD[0] = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion8/biestableD.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #15 CD[0] = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion8/biestableD.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #5 CD[0] = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion8/biestableD.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #15 CD[0] = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion8/biestableD.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #15 CD[0] = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion8/biestableD.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #30\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion8/biestableD.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #15 CD[0] = 0;\n  ^\n%Error: data/full_repos/permissive/408955603/Sesion8/biestableD.v:31: Unsupported or unknown PLI call: $dumpoff\n  $dumpoff;\n  ^~~~~~~~\n%Error: Exiting due to 4 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module D(output reg Q, input wire D, input wire C);
	initial Q = 0;
	always @(negedge C) Q = D;
endmodule
module D(output reg Q, input wire D, input wire C);

	initial Q = 0;
	always @(negedge C) Q = D;
endmodule