data/full_repos/permissive/494664634/AxiMM2S2MMTest/src/hdl/AxiMM2S2MMTest.v
data/verilator_xmls/d3017545-f862-41ac-bdb1-40a911ceef28.xml
module AxiCtrlMM2S2MM(
  input         clock,
  input         reset,
  input  [31:0] s_axi_araddr,
  input         s_axi_arvalid,
  output        s_axi_arready,
  output [31:0] s_axi_rdata,
  output        s_axi_rvalid,
  input         s_axi_rready,
  input  [31:0] s_axi_awaddr,
  input         s_axi_awvalid,
  output        s_axi_awready,
  input  [31:0] s_axi_wdata,
  input         s_axi_wvalid,
  output        s_axi_wready,
  output        s_axi_bvalid,
  input         s_axi_bready,
  output        start,
  input         done_0,
  input         done_1,
  output [31:0] read_addr,
  output [31:0] write_addr,
  output [31:0] rw_length
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
`endif
  reg [31:0] int_read_addr;
  reg [31:0] int_write_addr;
  reg [31:0] int_rw_length;
  reg [31:0] rdata;
  reg  rvalid;
  reg  bvalid;
  reg  rd_req;
  reg  wr_req_0;
  reg  wr_req_1;
  reg [11:0] rd_addr;
  reg [11:0] wr_addr;
  reg [31:0] wr_data;
  wire [31:0] _GEN_0 = s_axi_awready & s_axi_awvalid ? s_axi_awaddr : {{20'd0}, wr_addr};
  wire  _GEN_1 = s_axi_awready & s_axi_awvalid | wr_req_0;
  wire  _GEN_3 = s_axi_wready & s_axi_wvalid | wr_req_1;
  wire  _T_3 = ~bvalid;
  wire [31:0] _GEN_4 = wr_addr == 12'h0 ? wr_data : 32'h0;
  wire [31:0] _GEN_8 = ~bvalid & wr_req_0 & wr_req_1 ? _GEN_4 : 32'h0;
  wire  _GEN_13 = ~bvalid & wr_req_0 & wr_req_1 | bvalid;
  wire [31:0] _GEN_17 = bvalid & s_axi_bready ? 32'h0 : _GEN_8;
  wire [31:0] _GEN_24 = s_axi_arready & s_axi_arvalid ? s_axi_araddr : {{20'd0}, rd_addr};
  wire  _GEN_25 = s_axi_arready & s_axi_arvalid | rd_req;
  wire  _T_12 = ~rvalid;
  wire [1:0] _rdata_T = {done_1,done_0};
  wire [15:0] _GEN_26 = rd_addr == 12'h4 ? {{14'd0}, _rdata_T} : 16'hdead;
  wire  _GEN_29 = ~rvalid & rd_req | rvalid;
  wire [31:0] _GEN_35 = reset ? 32'h0 : _GEN_24;
  wire [31:0] _GEN_36 = reset ? 32'h0 : _GEN_0;
  assign s_axi_arready = ~rd_req & _T_12;
  assign s_axi_rdata = rdata;
  assign s_axi_rvalid = rvalid;
  assign s_axi_awready = ~wr_req_0 & _T_3;
  assign s_axi_wready = ~wr_req_1 & _T_3;
  assign s_axi_bvalid = bvalid;
  assign start = _GEN_17[0];
  assign read_addr = int_read_addr;
  assign write_addr = int_write_addr;
  assign rw_length = int_rw_length;
  always @(posedge clock) begin
    if (reset) begin
      int_read_addr <= 32'h0;
    end else if (!(bvalid & s_axi_bready)) begin
      if (~bvalid & wr_req_0 & wr_req_1) begin
        if (wr_addr == 12'h10) begin
          int_read_addr <= wr_data;
        end
      end
    end
    if (reset) begin
      int_write_addr <= 32'h0;
    end else if (!(bvalid & s_axi_bready)) begin
      if (~bvalid & wr_req_0 & wr_req_1) begin
        if (wr_addr == 12'h14) begin
          int_write_addr <= wr_data;
        end
      end
    end
    if (reset) begin
      int_rw_length <= 32'h0;
    end else if (!(bvalid & s_axi_bready)) begin
      if (~bvalid & wr_req_0 & wr_req_1) begin
        if (wr_addr == 12'h18) begin
          int_rw_length <= wr_data;
        end
      end
    end
    if (reset) begin
      rdata <= 32'h0;
    end else if (!(rvalid & s_axi_rready)) begin
      if (~rvalid & rd_req) begin
        rdata <= {{16'd0}, _GEN_26};
      end
    end
    if (reset) begin
      rvalid <= 1'h0;
    end else if (rvalid & s_axi_rready) begin
      rvalid <= 1'h0;
    end else begin
      rvalid <= _GEN_29;
    end
    if (reset) begin
      bvalid <= 1'h0;
    end else if (bvalid & s_axi_bready) begin
      bvalid <= 1'h0;
    end else begin
      bvalid <= _GEN_13;
    end
    if (reset) begin
      rd_req <= 1'h0;
    end else if (rvalid & s_axi_rready) begin
      rd_req <= _GEN_25;
    end else if (~rvalid & rd_req) begin
      rd_req <= 1'h0;
    end else begin
      rd_req <= _GEN_25;
    end
    if (reset) begin
      wr_req_0 <= 1'h0;
    end else if (bvalid & s_axi_bready) begin
      wr_req_0 <= _GEN_1;
    end else if (~bvalid & wr_req_0 & wr_req_1) begin
      wr_req_0 <= 1'h0;
    end else begin
      wr_req_0 <= _GEN_1;
    end
    if (reset) begin
      wr_req_1 <= 1'h0;
    end else if (bvalid & s_axi_bready) begin
      wr_req_1 <= _GEN_3;
    end else if (~bvalid & wr_req_0 & wr_req_1) begin
      wr_req_1 <= 1'h0;
    end else begin
      wr_req_1 <= _GEN_3;
    end
    rd_addr <= _GEN_35[11:0];
    wr_addr <= _GEN_36[11:0];
    if (reset) begin
      wr_data <= 32'h0;
    end else if (s_axi_wready & s_axi_wvalid) begin
      wr_data <= s_axi_wdata;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  int_read_addr = _RAND_0[31:0];
  _RAND_1 = {1{`RANDOM}};
  int_write_addr = _RAND_1[31:0];
  _RAND_2 = {1{`RANDOM}};
  int_rw_length = _RAND_2[31:0];
  _RAND_3 = {1{`RANDOM}};
  rdata = _RAND_3[31:0];
  _RAND_4 = {1{`RANDOM}};
  rvalid = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  bvalid = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  rd_req = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  wr_req_0 = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  wr_req_1 = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  rd_addr = _RAND_9[11:0];
  _RAND_10 = {1{`RANDOM}};
  wr_addr = _RAND_10[11:0];
  _RAND_11 = {1{`RANDOM}};
  wr_data = _RAND_11[31:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module AxiCtrlMM2S2MM(
  input         clock,
  input         reset,
  input  [31:0] s_axi_araddr,
  input         s_axi_arvalid,
  output        s_axi_arready,
  output [31:0] s_axi_rdata,
  output        s_axi_rvalid,
  input         s_axi_rready,
  input  [31:0] s_axi_awaddr,
  input         s_axi_awvalid,
  output        s_axi_awready,
  input  [31:0] s_axi_wdata,
  input         s_axi_wvalid,
  output        s_axi_wready,
  output        s_axi_bvalid,
  input         s_axi_bready,
  output        start,
  input         done_0,
  input         done_1,
  output [31:0] read_addr,
  output [31:0] write_addr,
  output [31:0] rw_length
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
`endif
  reg [31:0] int_read_addr;
  reg [31:0] int_write_addr;
  reg [31:0] int_rw_length;
  reg [31:0] rdata;
  reg  rvalid;
  reg  bvalid;
  reg  rd_req;
  reg  wr_req_0;
  reg  wr_req_1;
  reg [11:0] rd_addr;
  reg [11:0] wr_addr;
  reg [31:0] wr_data;
  wire [31:0] _GEN_0 = s_axi_awready & s_axi_awvalid ? s_axi_awaddr : {{20'd0}, wr_addr};
  wire  _GEN_1 = s_axi_awready & s_axi_awvalid | wr_req_0;
  wire  _GEN_3 = s_axi_wready & s_axi_wvalid | wr_req_1;
  wire  _T_3 = ~bvalid;
  wire [31:0] _GEN_4 = wr_addr == 12'h0 ? wr_data : 32'h0;
  wire [31:0] _GEN_8 = ~bvalid & wr_req_0 & wr_req_1 ? _GEN_4 : 32'h0;
  wire  _GEN_13 = ~bvalid & wr_req_0 & wr_req_1 | bvalid;
  wire [31:0] _GEN_17 = bvalid & s_axi_bready ? 32'h0 : _GEN_8;
  wire [31:0] _GEN_24 = s_axi_arready & s_axi_arvalid ? s_axi_araddr : {{20'd0}, rd_addr};
  wire  _GEN_25 = s_axi_arready & s_axi_arvalid | rd_req;
  wire  _T_12 = ~rvalid;
  wire [1:0] _rdata_T = {done_1,done_0};
  wire [15:0] _GEN_26 = rd_addr == 12'h4 ? {{14'd0}, _rdata_T} : 16'hdead;
  wire  _GEN_29 = ~rvalid & rd_req | rvalid;
  wire [31:0] _GEN_35 = reset ? 32'h0 : _GEN_24;
  wire [31:0] _GEN_36 = reset ? 32'h0 : _GEN_0;
  assign s_axi_arready = ~rd_req & _T_12;
  assign s_axi_rdata = rdata;
  assign s_axi_rvalid = rvalid;
  assign s_axi_awready = ~wr_req_0 & _T_3;
  assign s_axi_wready = ~wr_req_1 & _T_3;
  assign s_axi_bvalid = bvalid;
  assign start = _GEN_17[0];
  assign read_addr = int_read_addr;
  assign write_addr = int_write_addr;
  assign rw_length = int_rw_length;
  always @(posedge clock) begin
    if (reset) begin
      int_read_addr <= 32'h0;
    end else if (!(bvalid & s_axi_bready)) begin
      if (~bvalid & wr_req_0 & wr_req_1) begin
        if (wr_addr == 12'h10) begin
          int_read_addr <= wr_data;
        end
      end
    end
    if (reset) begin
      int_write_addr <= 32'h0;
    end else if (!(bvalid & s_axi_bready)) begin
      if (~bvalid & wr_req_0 & wr_req_1) begin
        if (wr_addr == 12'h14) begin
          int_write_addr <= wr_data;
        end
      end
    end
    if (reset) begin
      int_rw_length <= 32'h0;
    end else if (!(bvalid & s_axi_bready)) begin
      if (~bvalid & wr_req_0 & wr_req_1) begin
        if (wr_addr == 12'h18) begin
          int_rw_length <= wr_data;
        end
      end
    end
    if (reset) begin
      rdata <= 32'h0;
    end else if (!(rvalid & s_axi_rready)) begin
      if (~rvalid & rd_req) begin
        rdata <= {{16'd0}, _GEN_26};
      end
    end
    if (reset) begin
      rvalid <= 1'h0;
    end else if (rvalid & s_axi_rready) begin
      rvalid <= 1'h0;
    end else begin
      rvalid <= _GEN_29;
    end
    if (reset) begin
      bvalid <= 1'h0;
    end else if (bvalid & s_axi_bready) begin
      bvalid <= 1'h0;
    end else begin
      bvalid <= _GEN_13;
    end
    if (reset) begin
      rd_req <= 1'h0;
    end else if (rvalid & s_axi_rready) begin
      rd_req <= _GEN_25;
    end else if (~rvalid & rd_req) begin
      rd_req <= 1'h0;
    end else begin
      rd_req <= _GEN_25;
    end
    if (reset) begin
      wr_req_0 <= 1'h0;
    end else if (bvalid & s_axi_bready) begin
      wr_req_0 <= _GEN_1;
    end else if (~bvalid & wr_req_0 & wr_req_1) begin
      wr_req_0 <= 1'h0;
    end else begin
      wr_req_0 <= _GEN_1;
    end
    if (reset) begin
      wr_req_1 <= 1'h0;
    end else if (bvalid & s_axi_bready) begin
      wr_req_1 <= _GEN_3;
    end else if (~bvalid & wr_req_0 & wr_req_1) begin
      wr_req_1 <= 1'h0;
    end else begin
      wr_req_1 <= _GEN_3;
    end
    rd_addr <= _GEN_35[11:0];
    wr_addr <= _GEN_36[11:0];
    if (reset) begin
      wr_data <= 32'h0;
    end else if (s_axi_wready & s_axi_wvalid) begin
      wr_data <= s_axi_wdata;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  int_read_addr = _RAND_0[31:0];
  _RAND_1 = {1{`RANDOM}};
  int_write_addr = _RAND_1[31:0];
  _RAND_2 = {1{`RANDOM}};
  int_rw_length = _RAND_2[31:0];
  _RAND_3 = {1{`RANDOM}};
  rdata = _RAND_3[31:0];
  _RAND_4 = {1{`RANDOM}};
  rvalid = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  bvalid = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  rd_req = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  wr_req_0 = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  wr_req_1 = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  rd_addr = _RAND_9[11:0];
  _RAND_10 = {1{`RANDOM}};
  wr_addr = _RAND_10[11:0];
  _RAND_11 = {1{`RANDOM}};
  wr_data = _RAND_11[31:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule