data/full_repos/permissive/527007664/openlane/pixel/src/Pixel.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/527007664/openlane/pixel/src/Pixel.v:287: Cell has missing pin: \'reset\'\n loc_timer_int inst2(\n               ^~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/527007664/openlane/pixel/src/Pixel.v:294: Cell has missing pin: \'reset\'\n adj_timer_int inst3(\n               ^~~~~\n%Error: Exiting due to 2 warning(s)\n'
module pixel_fsm (clk, reset, pxl_start_i, loc_timer_m_i, loc_timer_en, adj_timer_m_i, adj_timer_en, s_p1, s_p2, s1, s2, s1_inv, s2_inv, v_b1, v_b0, pxl_done_o);
	input clk, reset, pxl_start_i, loc_timer_m_i, adj_timer_m_i;
	output reg loc_timer_en, adj_timer_en, s_p1, s_p2, s1, s2, s1_inv, s2_inv, v_b1, v_b0, pxl_done_o;
	reg [2:0] state;
	reg [2:0] next_state;

	parameter RESET = 3'b000; parameter LOC_PIXEL = 3'b001; parameter IDLE = 3'b010; 
	parameter ADJ_PIXEL = 3'b011; parameter PXL_DONE = 3'b100;

	initial begin
		state = 3'b000;
	end

	always @(posedge clk or posedge reset)
	begin
		if (reset) state <= RESET;
		else state <= next_state;
	end

	always @(state or pxl_start_i or loc_timer_m_i or adj_timer_m_i)
	begin
		case (state)
			RESET:		if (pxl_start_i==1'b0) begin
						next_state = RESET; end
					else begin
						next_state = LOC_PIXEL; end
			
			LOC_PIXEL: 	if (loc_timer_m_i==1'b0) begin
						next_state = LOC_PIXEL; end
					else begin
						next_state = IDLE;	end		
			
			IDLE: next_state = ADJ_PIXEL;
			
			ADJ_PIXEL: 	if (adj_timer_m_i==1'b0) begin
						next_state = ADJ_PIXEL; end
					else begin
						next_state = PXL_DONE; end			

			PXL_DONE: next_state = RESET;
		endcase
	end

	always @(state)
	begin
		case (state)
			RESET:		begin
						loc_timer_en = 1'b0;
						adj_timer_en = 1'b0;
						s_p1 = 1'b0;
						s_p2 = 1'b0; 
						s1 = 1'b0; 
						s1_inv = ~s1;
						s2 = 1'b0;
						s2_inv = ~s2;
						v_b1 = 1'b0;
						v_b0 = ~v_b1;
						pxl_done_o = 1'b0;
					end
				
			LOC_PIXEL:	begin 
						loc_timer_en = 1'b1;
						adj_timer_en = 1'b0;
						s_p1 = 1'b1; 
						s_p2 = 1'b0; 
						s1 = 1'b1;
						s1_inv = ~s1; 
						s2 = 1'b0;
						s2_inv = ~s2; 
						v_b1 = 1'b1; 
						v_b0 = ~v_b1;
						pxl_done_o = 1'b0;
					end
			
			IDLE:		begin 
						loc_timer_en = 1'b0;
						adj_timer_en = 1'b0;
						s_p1 = 1'b0; 
						s_p2 = 1'b0; 
						s1 = 1'b0; 
						s1_inv = ~s1;
						s2 = 1'b0; 
						s2_inv = ~s2;
						v_b1 = 1'b0; 
						v_b0 = ~v_b1;
						pxl_done_o = 1'b0;
					end
				
			ADJ_PIXEL: 	begin
						loc_timer_en = 1'b0;
						adj_timer_en = 1'b1;
						s_p1 = 1'b0; 
						s_p2 = 1'b1;
						s1 = 1'b0;
						s1_inv = ~s1;
						s2 = 1'b1; 
						s2_inv = ~s2;
						v_b1 = 1'b1; 
						v_b0 = ~v_b1;
						pxl_done_o = 1'b0;
					end
				
			PXL_DONE:	begin 
						loc_timer_en = 1'b0;
						adj_timer_en = 1'b0;
						s_p1 = 1'b0; 
						s_p2 = 1'b0; 
						s1 = 1'b0; 
						s1_inv = ~s1;
						s2 = 1'b0; 
						s2_inv = ~s2;
						v_b1 = 1'b0; 
						v_b0 = ~v_b1;
						pxl_done_o = 1'b1;
					end
		endcase
	end

endmodule
module pixel_fsm (clk, reset, pxl_start_i, loc_timer_m_i, loc_timer_en, adj_timer_m_i, adj_timer_en, s_p1, s_p2, s1, s2, s1_inv, s2_inv, v_b1, v_b0, pxl_done_o);

	input clk, reset, pxl_start_i, loc_timer_m_i, adj_timer_m_i;
	output reg loc_timer_en, adj_timer_en, s_p1, s_p2, s1, s2, s1_inv, s2_inv, v_b1, v_b0, pxl_done_o;
	reg [2:0] state;
	reg [2:0] next_state;

	parameter RESET = 3'b000; parameter LOC_PIXEL = 3'b001; parameter IDLE = 3'b010; 
	parameter ADJ_PIXEL = 3'b011; parameter PXL_DONE = 3'b100;

	initial begin
		state = 3'b000;
	end

	always @(posedge clk or posedge reset)
	begin
		if (reset) state <= RESET;
		else state <= next_state;
	end

	always @(state or pxl_start_i or loc_timer_m_i or adj_timer_m_i)
	begin
		case (state)
			RESET:		if (pxl_start_i==1'b0) begin
						next_state = RESET; end
					else begin
						next_state = LOC_PIXEL; end
			
			LOC_PIXEL: 	if (loc_timer_m_i==1'b0) begin
						next_state = LOC_PIXEL; end
					else begin
						next_state = IDLE;	end		
			
			IDLE: next_state = ADJ_PIXEL;
			
			ADJ_PIXEL: 	if (adj_timer_m_i==1'b0) begin
						next_state = ADJ_PIXEL; end
					else begin
						next_state = PXL_DONE; end			

			PXL_DONE: next_state = RESET;
		endcase
	end

	always @(state)
	begin
		case (state)
			RESET:		begin
						loc_timer_en = 1'b0;
						adj_timer_en = 1'b0;
						s_p1 = 1'b0;
						s_p2 = 1'b0; 
						s1 = 1'b0; 
						s1_inv = ~s1;
						s2 = 1'b0;
						s2_inv = ~s2;
						v_b1 = 1'b0;
						v_b0 = ~v_b1;
						pxl_done_o = 1'b0;
					end
				
			LOC_PIXEL:	begin 
						loc_timer_en = 1'b1;
						adj_timer_en = 1'b0;
						s_p1 = 1'b1; 
						s_p2 = 1'b0; 
						s1 = 1'b1;
						s1_inv = ~s1; 
						s2 = 1'b0;
						s2_inv = ~s2; 
						v_b1 = 1'b1; 
						v_b0 = ~v_b1;
						pxl_done_o = 1'b0;
					end
			
			IDLE:		begin 
						loc_timer_en = 1'b0;
						adj_timer_en = 1'b0;
						s_p1 = 1'b0; 
						s_p2 = 1'b0; 
						s1 = 1'b0; 
						s1_inv = ~s1;
						s2 = 1'b0; 
						s2_inv = ~s2;
						v_b1 = 1'b0; 
						v_b0 = ~v_b1;
						pxl_done_o = 1'b0;
					end
				
			ADJ_PIXEL: 	begin
						loc_timer_en = 1'b0;
						adj_timer_en = 1'b1;
						s_p1 = 1'b0; 
						s_p2 = 1'b1;
						s1 = 1'b0;
						s1_inv = ~s1;
						s2 = 1'b1; 
						s2_inv = ~s2;
						v_b1 = 1'b1; 
						v_b0 = ~v_b1;
						pxl_done_o = 1'b0;
					end
				
			PXL_DONE:	begin 
						loc_timer_en = 1'b0;
						adj_timer_en = 1'b0;
						s_p1 = 1'b0; 
						s_p2 = 1'b0; 
						s1 = 1'b0; 
						s1_inv = ~s1;
						s2 = 1'b0; 
						s2_inv = ~s2;
						v_b1 = 1'b0; 
						v_b0 = ~v_b1;
						pxl_done_o = 1'b1;
					end
		endcase
	end

endmodule