data/full_repos/permissive/488739248/rtl/ym3526/jtopl_eg_comb.v
1: b"%Error: data/full_repos/permissive/488739248/rtl/ym3526/jtopl_eg_comb.v:72: Cannot find file containing module: 'jtopl_eg_ctrl'\njtopl_eg_ctrl u_ctrl(    \n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/488739248/rtl/ym3526,data/full_repos/permissive/488739248/jtopl_eg_ctrl\n             data/full_repos/permissive/488739248/rtl/ym3526,data/full_repos/permissive/488739248/jtopl_eg_ctrl.v\n             data/full_repos/permissive/488739248/rtl/ym3526,data/full_repos/permissive/488739248/jtopl_eg_ctrl.sv\n             jtopl_eg_ctrl\n             jtopl_eg_ctrl.v\n             jtopl_eg_ctrl.sv\n             obj_dir/jtopl_eg_ctrl\n             obj_dir/jtopl_eg_ctrl.v\n             obj_dir/jtopl_eg_ctrl.sv\n%Error: data/full_repos/permissive/488739248/rtl/ym3526/jtopl_eg_comb.v:91: Cannot find file containing module: 'jtopl_eg_step'\njtopl_eg_step u_step(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/488739248/rtl/ym3526/jtopl_eg_comb.v:107: Cannot find file containing module: 'jtopl_eg_pure'\njtopl_eg_pure u_pure(\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/488739248/rtl/ym3526/jtopl_eg_comb.v:118: Cannot find file containing module: 'jtopl_eg_final'\njtopl_eg_final u_final(\n^~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module jtopl_eg_comb(
    input wire          keyon_now,
    input wire          keyoff_now,
    input wire  [ 2:0]  state_in,
    input wire  [ 9:0]  eg_in,

    input wire          en_sus,
    input wire  [ 3:0]  arate,
    input wire  [ 3:0]  drate,
    input wire  [ 3:0]  rrate,
    input wire  [ 3:0]  sl,

    output wire [ 4:0]  base_rate,
    output wire [ 2:0]  state_next,
    output wire         pg_rst,


    input wire          step_attack,
    input wire  [ 4:0]  step_rate_in,
    input wire  [ 3:0]  keycode,
    input wire  [14:0]  eg_cnt,
    input wire          cnt_in,
    input wire          ksr,
    output wire         cnt_lsb,
    output wire         step,
    output wire [ 5:0]  step_rate_out,
    output wire         sum_up_out,


    input wire          pure_attack,
    input wire          pure_step,
    input wire  [ 5:1]  pure_rate,
    input wire  [ 9:0]  pure_eg_in,
    output wire  [ 9:0]  pure_eg_out,
    input wire          sum_up_in,


    input wire  [ 3:0]  lfo_mod,
    input wire  [ 3:0]  fnum,
    input wire  [ 2:0]  block,
    input wire          amsen,
    input wire          ams,
    input wire  [ 5:0]  tl,
    input wire  [ 1:0]  ksl,
    input wire  [ 3:0]  final_keycode,
    input wire  [ 9:0]  final_eg_in,
    output wire [ 9:0]  final_eg_out
);


jtopl_eg_ctrl u_ctrl(    
    .keyon_now      ( keyon_now     ),
    .keyoff_now     ( keyoff_now    ),
    .state_in       ( state_in      ),
    .eg             ( eg_in         ),

    .en_sus         ( en_sus        ),
    .arate          ( arate         ),
    .drate          ( drate         ),
    .rrate          ( rrate         ),
    .sl             ( sl            ),

    .base_rate      ( base_rate     ),
    .state_next     ( state_next    ),
    .pg_rst         ( pg_rst        )
);



jtopl_eg_step u_step(
    .attack     ( step_attack   ),
    .base_rate  ( step_rate_in  ),
    .keycode    ( keycode       ),
    .eg_cnt     ( eg_cnt        ),
    .cnt_in     ( cnt_in        ),
    .ksr        ( ksr           ),
    .cnt_lsb    ( cnt_lsb       ),
    .step       ( step          ),
    .rate       ( step_rate_out ),
    .sum_up     ( sum_up_out    )
);



wire [9:0] egin, egout;
jtopl_eg_pure u_pure(
    .attack ( pure_attack   ),
    .step   ( pure_step     ),
    .rate   ( pure_rate     ),
    .eg_in  ( pure_eg_in    ),
    .eg_pure( pure_eg_out   ),
    .sum_up ( sum_up_in     )
);



jtopl_eg_final u_final(
    .fnum       ( fnum          ),
    .block      ( block         ),
    .lfo_mod    ( lfo_mod       ),
    .amsen      ( amsen         ),
    .ams        ( ams           ),
    .tl         ( tl            ),
    .ksl        ( ksl           ),
    .keycode    ( final_keycode ),
    .eg_pure_in ( final_eg_in   ),
    .eg_limited ( final_eg_out  )
);

endmodule
module jtopl_eg_comb(
    input wire          keyon_now,
    input wire          keyoff_now,
    input wire  [ 2:0]  state_in,
    input wire  [ 9:0]  eg_in,

    input wire          en_sus,
    input wire  [ 3:0]  arate,
    input wire  [ 3:0]  drate,
    input wire  [ 3:0]  rrate,
    input wire  [ 3:0]  sl,

    output wire [ 4:0]  base_rate,
    output wire [ 2:0]  state_next,
    output wire         pg_rst,


    input wire          step_attack,
    input wire  [ 4:0]  step_rate_in,
    input wire  [ 3:0]  keycode,
    input wire  [14:0]  eg_cnt,
    input wire          cnt_in,
    input wire          ksr,
    output wire         cnt_lsb,
    output wire         step,
    output wire [ 5:0]  step_rate_out,
    output wire         sum_up_out,


    input wire          pure_attack,
    input wire          pure_step,
    input wire  [ 5:1]  pure_rate,
    input wire  [ 9:0]  pure_eg_in,
    output wire  [ 9:0]  pure_eg_out,
    input wire          sum_up_in,


    input wire  [ 3:0]  lfo_mod,
    input wire  [ 3:0]  fnum,
    input wire  [ 2:0]  block,
    input wire          amsen,
    input wire          ams,
    input wire  [ 5:0]  tl,
    input wire  [ 1:0]  ksl,
    input wire  [ 3:0]  final_keycode,
    input wire  [ 9:0]  final_eg_in,
    output wire [ 9:0]  final_eg_out
);



jtopl_eg_ctrl u_ctrl(    
    .keyon_now      ( keyon_now     ),
    .keyoff_now     ( keyoff_now    ),
    .state_in       ( state_in      ),
    .eg             ( eg_in         ),

    .en_sus         ( en_sus        ),
    .arate          ( arate         ),
    .drate          ( drate         ),
    .rrate          ( rrate         ),
    .sl             ( sl            ),

    .base_rate      ( base_rate     ),
    .state_next     ( state_next    ),
    .pg_rst         ( pg_rst        )
);



jtopl_eg_step u_step(
    .attack     ( step_attack   ),
    .base_rate  ( step_rate_in  ),
    .keycode    ( keycode       ),
    .eg_cnt     ( eg_cnt        ),
    .cnt_in     ( cnt_in        ),
    .ksr        ( ksr           ),
    .cnt_lsb    ( cnt_lsb       ),
    .step       ( step          ),
    .rate       ( step_rate_out ),
    .sum_up     ( sum_up_out    )
);



wire [9:0] egin, egout;
jtopl_eg_pure u_pure(
    .attack ( pure_attack   ),
    .step   ( pure_step     ),
    .rate   ( pure_rate     ),
    .eg_in  ( pure_eg_in    ),
    .eg_pure( pure_eg_out   ),
    .sum_up ( sum_up_in     )
);



jtopl_eg_final u_final(
    .fnum       ( fnum          ),
    .block      ( block         ),
    .lfo_mod    ( lfo_mod       ),
    .amsen      ( amsen         ),
    .ams        ( ams           ),
    .tl         ( tl            ),
    .ksl        ( ksl           ),
    .keycode    ( final_keycode ),
    .eg_pure_in ( final_eg_in   ),
    .eg_limited ( final_eg_out  )
);

endmodule