data/full_repos/permissive/485610894/tianji-4bit-env/rtl/74HC161.v
1: b'%Error: data/full_repos/permissive/485610894/tianji-4bit-env/rtl/74HC161.v:11: Cannot find include file: pa_soc_param.v\n`include "pa_soc_param.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/485610894/tianji-4bit-env/rtl,data/full_repos/permissive/485610894/pa_soc_param.v\n             data/full_repos/permissive/485610894/tianji-4bit-env/rtl,data/full_repos/permissive/485610894/pa_soc_param.v.v\n             data/full_repos/permissive/485610894/tianji-4bit-env/rtl,data/full_repos/permissive/485610894/pa_soc_param.v.sv\n             pa_soc_param.v\n             pa_soc_param.v.v\n             pa_soc_param.v.sv\n             obj_dir/pa_soc_param.v\n             obj_dir/pa_soc_param.v.v\n             obj_dir/pa_soc_param.v.sv\n%Error: Exiting due to 1 error(s)\n'
module M74HC161 (
    input                       CP,
    input                       MRn,
           
    input  [3:0]                Di,
    input                       PEn,
    input                       CEP,
    input                       CET,
           
    output                      TC,
    output [3:0]                Qo
);

reg  [3:0]                      COUNT;
reg                             TCO;

always @ (posedge CP or negedge MRn) begin
    if (!MRn) begin
        COUNT[3:0] <= 4'b0;
    end
    else if (!PEn) begin
        COUNT[3:0] <= Di[3:0];
    end
    else if (CEP && CET) begin
        COUNT[3:0] <= COUNT[3:0] + 4'b1;
    end
    else begin
        COUNT[3:0] <= COUNT[3:0];
    end
end

always @ (posedge CP or negedge MRn) begin
    if (!MRn) begin
        TCO <= 1'b0;
    end
    else if (!PEn) begin
        if (4'b1111 == COUNT[3:0]) begin
            TCO <= 1'b1;
        end
        else begin
            TCO <= 1'b0;
        end
    end
    else if (CEP && CET) begin
        if (4'b1111 == COUNT[3:0]) begin
            TCO <= 1'b1;
        end
        else begin
            TCO <= 1'b0;
        end
    end
    else if (!CET) begin
        TCO <= 1'b0;
    end
    else if (!CEP) begin
        if (4'b1111 == COUNT[3:0]) begin
            TCO <= 1'b1;
        end
        else begin
            TCO <= 1'b0;
        end
    end
    else begin
        TCO <= TCO;
    end
end

assign Qo[3:0] = COUNT[3:0];
assign TC = TCO;

endmodule
module M74HC161 (
    input                       CP,
    input                       MRn,
           
    input  [3:0]                Di,
    input                       PEn,
    input                       CEP,
    input                       CET,
           
    output                      TC,
    output [3:0]                Qo
);


reg  [3:0]                      COUNT;
reg                             TCO;

always @ (posedge CP or negedge MRn) begin
    if (!MRn) begin
        COUNT[3:0] <= 4'b0;
    end
    else if (!PEn) begin
        COUNT[3:0] <= Di[3:0];
    end
    else if (CEP && CET) begin
        COUNT[3:0] <= COUNT[3:0] + 4'b1;
    end
    else begin
        COUNT[3:0] <= COUNT[3:0];
    end
end

always @ (posedge CP or negedge MRn) begin
    if (!MRn) begin
        TCO <= 1'b0;
    end
    else if (!PEn) begin
        if (4'b1111 == COUNT[3:0]) begin
            TCO <= 1'b1;
        end
        else begin
            TCO <= 1'b0;
        end
    end
    else if (CEP && CET) begin
        if (4'b1111 == COUNT[3:0]) begin
            TCO <= 1'b1;
        end
        else begin
            TCO <= 1'b0;
        end
    end
    else if (!CET) begin
        TCO <= 1'b0;
    end
    else if (!CEP) begin
        if (4'b1111 == COUNT[3:0]) begin
            TCO <= 1'b1;
        end
        else begin
            TCO <= 1'b0;
        end
    end
    else begin
        TCO <= TCO;
    end
end

assign Qo[3:0] = COUNT[3:0];
assign TC = TCO;

endmodule