data/full_repos/permissive/476477303/verilog/dv/video/video_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/476477303/verilog/dv/video/video_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n always #12.5 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/476477303/verilog/dv/video/video_tb.v:58: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("video.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/476477303/verilog/dv/video/video_tb.v:63: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(1, video_tb);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/476477303/verilog/dv/video/video_tb.v:64: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(2, video_tb.uut.mprj);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/476477303/verilog/dv/video/video_tb.v:69: syntax error, unexpected \'@\'\n   repeat (1000) @(posedge clock);\n                 ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/video/video_tb.v:86: Unsupported or unknown PLI call: $timeformat\n  $timeformat(-6, 3, "us", 8);\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/476477303/verilog/dv/video/video_tb.v:89: syntax error, unexpected \'@\'\n  @(posedge nextTestOutput);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/video/video_tb.v:105: syntax error, unexpected \'@\'\n  @(posedge vgaHSync);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/video/video_tb.v:114: syntax error, unexpected \'@\'\n  @(negedge vgaHSync);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/video/video_tb.v:122: syntax error, unexpected \'@\'\n  @(negedge vgaVSync);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/video/video_tb.v:126: syntax error, unexpected \'@\'\n  @(posedge vgaVSync);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/video/video_tb.v:135: syntax error, unexpected \'@\'\n  @(negedge vgaVSync);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/video/video_tb.v:144: syntax error, unexpected \'@\'\n  @(posedge nextTestOutput);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/video/video_tb.v:150: syntax error, unexpected \'@\'\n  @(posedge vgaHSync);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/video/video_tb.v:159: syntax error, unexpected \'@\'\n  @(negedge vgaHSync);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/video/video_tb.v:167: syntax error, unexpected \'@\'\n  @(negedge vgaVSync);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/video/video_tb.v:171: syntax error, unexpected \'@\'\n  @(posedge vgaVSync);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/video/video_tb.v:180: syntax error, unexpected \'@\'\n  @(negedge vgaVSync);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/video/video_tb.v:189: syntax error, unexpected \'@\'\n  @(posedge nextTestOutput);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/476477303/verilog/dv/video/video_tb.v:222: Unsupported: Ignoring delay on this delayed statement.\n  #2000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/476477303/verilog/dv/video/video_tb.v:224: Unsupported: Ignoring delay on this delayed statement.\n  #300000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/476477303/verilog/dv/video/video_tb.v:233: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/476477303/verilog/dv/video/video_tb.v:235: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/476477303/verilog/dv/video/video_tb.v:237: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/476477303/verilog/dv/video/video_tb.v:239: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/476477303/verilog/dv/video/video_tb.v:244: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("Success:0b%b Timing Valid:0b%b Next test:0b%b", succesOutput, timingValid, nextTestOutput);\n  ^\n%Error: Exiting due to 18 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module video_tb;
	reg clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

	wire gpio;
	wire [37:0] mprj_io;

	wire succesOutput = mprj_io[12];
	wire nextTestOutput = mprj_io[13];
	
	wire[5:0] vgaPixel = mprj_io[35:30];
	wire vgaVSync = mprj_io[36];
	wire vgaHSync = mprj_io[37];

	pullup(mprj_io[3]);
	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;

	reg timingValid = 1'b1;




	always #12.5 clock <= (clock === 1'b0);


	assign mprj_io[2:0] = 3'b0;
	assign mprj_io[11:4] = 8'b0;
	assign mprj_io[29:14] = 16'b0;

	initial begin
		clock = 0;
		timingValid = 1'b1;
	end

	initial begin
		$dumpfile("video.vcd");

`ifdef SIM
		$dumpvars(0, video_tb);
`else
		$dumpvars(1, video_tb);
		$dumpvars(2, video_tb.uut.mprj);
`endif


		repeat (1000) begin
			repeat (1000) @(posedge clock);

		end
		$display("%c[1;35m",27);
		`ifdef GL
			$display ("Monitor: Timeout, Peripherals Video Test (GL) Failed");
		`else
			$display ("Monitor: Timeout, Peripherals Video Test (RTL) Failed");
		`endif
		$display("%c[0m",27);
		$finish;
	end

	realtime timerStart;
	realtime timerLength;

	initial begin
		$timeformat(-6, 3, "us", 8);


		@(posedge nextTestOutput);
		@(posedge nextTestOutput);
		@(posedge nextTestOutput);
		@(posedge nextTestOutput);
		@(posedge nextTestOutput);
		@(posedge nextTestOutput);
		@(posedge nextTestOutput);
		@(posedge nextTestOutput);
		@(posedge nextTestOutput);
		@(posedge nextTestOutput);


		@(negedge vgaHSync);
		timerStart = $realtime;
		

		@(posedge vgaHSync);
		timerLength = $realtime - timerStart;
		$display("H Sync pulse period: %t", timerLength);
		if (timerLength < 390 || timerLength > 410) begin
			timingValid = 1'b0;
			$display("Invalid time, should be between 0.390us and 0.410us");
		end


		@(negedge vgaHSync);
		timerLength = $realtime - timerStart;
		$display("H Sync period: %t", timerLength);
		if (timerLength < 3290 || timerLength > 3310) begin
			timingValid = 1'b0;
			$display("Invalid time, should be between 3.290us and 3.310us");
		end

		@(negedge vgaVSync);
		timerStart = $realtime;
		

		@(posedge vgaVSync);
		timerLength = $realtime - timerStart;
		$display("V Sync pulse period: %t", timerLength);
		if (timerLength < 13190 || timerLength > 13210) begin
			timingValid = 1'b0;
			$display("Invalid time, should be between 13.190us and 13.210us");
		end


		@(negedge vgaVSync);
		timerLength = $realtime - timerStart;
		$display("V Sync period: %t", timerLength);
		if (timerLength < 2072390 || timerLength > 2072410) begin
			timingValid = 1'b0;
			$display("Invalid time, should be between 2072.390us and 2072.410us");
		end


		@(posedge nextTestOutput);

		@(negedge vgaHSync);
		timerStart = $realtime;
		

		@(posedge vgaHSync);
		timerLength = $realtime - timerStart;
		$display("H Sync pulse period: %t", timerLength);
		if (timerLength < 390 || timerLength > 410) begin
			timingValid = 1'b0;
			$display("Invalid time, should be between 0.390us and 0.410us");
		end


		@(negedge vgaHSync);
		timerLength = $realtime - timerStart;
		$display("H Sync period: %t", timerLength);
		if (timerLength < 3290 || timerLength > 3310) begin
			timingValid = 1'b0;
			$display("Invalid time, should be between 3.290us and 3.310us");
		end

		@(negedge vgaVSync);
		timerStart = $realtime;
		

		@(posedge vgaVSync);
		timerLength = $realtime - timerStart;
		$display("V Sync pulse period: %t", timerLength);
		if (timerLength < 13190 || timerLength > 13210) begin
			timingValid = 1'b0;
			$display("Invalid time, should be between 13.190us and 13.210us");
		end


		@(negedge vgaVSync);
		timerLength = $realtime - timerStart;
		$display("V Sync period: %t", timerLength);
		if (timerLength < 2072390 || timerLength > 2072410) begin
			timingValid = 1'b0;
			$display("Invalid time, should be between 2072.390us and 2072.410us");
		end


		@(posedge nextTestOutput);
		
		if (!timingValid) begin
			$display("%c[1;31m",27);
			`ifdef GL
				$display ("Monitor: Video Test VGA Timing (GL) Failed");
			`else
				$display ("Monitor: Video Test VGA Timing (RTL) Failed");
			`endif
			$display("%c[0m",27);
		end else if (succesOutput) begin
			$display("%c[1;92m",27);
			`ifdef GL
				$display("Monitor: Video Test (GL) Passed");
			`else
				$display("Monitor: Video Test (RTL) Passed");
			`endif
			$display("%c[0m",27);
		end else begin
			$display("%c[1;31m",27);
			`ifdef GL
				$display ("Monitor: Video Test (GL) Failed");
			`else
				$display ("Monitor: Video Test (RTL) Failed");
			`endif
			$display("%c[0m",27);
		end
	    $finish;
	end

	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#300000;
		CSB = 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end

	always @(succesOutput, nextTestOutput, timingValid) begin
		#1 $display("Success:0b%b Timing Valid:0b%b Next test:0b%b", succesOutput, timingValid, nextTestOutput);
	end

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3;
	wire VDD1V8;
	wire VSS;
	
	assign VDD3V3 = power1;
	assign VDD1V8 = power2;
	assign VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda1_2  (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock    (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("video.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule
module video_tb;

	reg clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

	wire gpio;
	wire [37:0] mprj_io;

	wire succesOutput = mprj_io[12];
	wire nextTestOutput = mprj_io[13];
	
	wire[5:0] vgaPixel = mprj_io[35:30];
	wire vgaVSync = mprj_io[36];
	wire vgaHSync = mprj_io[37];

	pullup(mprj_io[3]);
	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;

	reg timingValid = 1'b1;




	always #12.5 clock <= (clock === 1'b0);


	assign mprj_io[2:0] = 3'b0;
	assign mprj_io[11:4] = 8'b0;
	assign mprj_io[29:14] = 16'b0;

	initial begin
		clock = 0;
		timingValid = 1'b1;
	end

	initial begin
		$dumpfile("video.vcd");

`ifdef SIM
		$dumpvars(0, video_tb);
`else
		$dumpvars(1, video_tb);
		$dumpvars(2, video_tb.uut.mprj);
`endif


		repeat (1000) begin
			repeat (1000) @(posedge clock);

		end
		$display("%c[1;35m",27);
		`ifdef GL
			$display ("Monitor: Timeout, Peripherals Video Test (GL) Failed");
		`else
			$display ("Monitor: Timeout, Peripherals Video Test (RTL) Failed");
		`endif
		$display("%c[0m",27);
		$finish;
	end

	realtime timerStart;
	realtime timerLength;

	initial begin
		$timeformat(-6, 3, "us", 8);


		@(posedge nextTestOutput);
		@(posedge nextTestOutput);
		@(posedge nextTestOutput);
		@(posedge nextTestOutput);
		@(posedge nextTestOutput);
		@(posedge nextTestOutput);
		@(posedge nextTestOutput);
		@(posedge nextTestOutput);
		@(posedge nextTestOutput);
		@(posedge nextTestOutput);


		@(negedge vgaHSync);
		timerStart = $realtime;
		

		@(posedge vgaHSync);
		timerLength = $realtime - timerStart;
		$display("H Sync pulse period: %t", timerLength);
		if (timerLength < 390 || timerLength > 410) begin
			timingValid = 1'b0;
			$display("Invalid time, should be between 0.390us and 0.410us");
		end


		@(negedge vgaHSync);
		timerLength = $realtime - timerStart;
		$display("H Sync period: %t", timerLength);
		if (timerLength < 3290 || timerLength > 3310) begin
			timingValid = 1'b0;
			$display("Invalid time, should be between 3.290us and 3.310us");
		end

		@(negedge vgaVSync);
		timerStart = $realtime;
		

		@(posedge vgaVSync);
		timerLength = $realtime - timerStart;
		$display("V Sync pulse period: %t", timerLength);
		if (timerLength < 13190 || timerLength > 13210) begin
			timingValid = 1'b0;
			$display("Invalid time, should be between 13.190us and 13.210us");
		end


		@(negedge vgaVSync);
		timerLength = $realtime - timerStart;
		$display("V Sync period: %t", timerLength);
		if (timerLength < 2072390 || timerLength > 2072410) begin
			timingValid = 1'b0;
			$display("Invalid time, should be between 2072.390us and 2072.410us");
		end


		@(posedge nextTestOutput);

		@(negedge vgaHSync);
		timerStart = $realtime;
		

		@(posedge vgaHSync);
		timerLength = $realtime - timerStart;
		$display("H Sync pulse period: %t", timerLength);
		if (timerLength < 390 || timerLength > 410) begin
			timingValid = 1'b0;
			$display("Invalid time, should be between 0.390us and 0.410us");
		end


		@(negedge vgaHSync);
		timerLength = $realtime - timerStart;
		$display("H Sync period: %t", timerLength);
		if (timerLength < 3290 || timerLength > 3310) begin
			timingValid = 1'b0;
			$display("Invalid time, should be between 3.290us and 3.310us");
		end

		@(negedge vgaVSync);
		timerStart = $realtime;
		

		@(posedge vgaVSync);
		timerLength = $realtime - timerStart;
		$display("V Sync pulse period: %t", timerLength);
		if (timerLength < 13190 || timerLength > 13210) begin
			timingValid = 1'b0;
			$display("Invalid time, should be between 13.190us and 13.210us");
		end


		@(negedge vgaVSync);
		timerLength = $realtime - timerStart;
		$display("V Sync period: %t", timerLength);
		if (timerLength < 2072390 || timerLength > 2072410) begin
			timingValid = 1'b0;
			$display("Invalid time, should be between 2072.390us and 2072.410us");
		end


		@(posedge nextTestOutput);
		
		if (!timingValid) begin
			$display("%c[1;31m",27);
			`ifdef GL
				$display ("Monitor: Video Test VGA Timing (GL) Failed");
			`else
				$display ("Monitor: Video Test VGA Timing (RTL) Failed");
			`endif
			$display("%c[0m",27);
		end else if (succesOutput) begin
			$display("%c[1;92m",27);
			`ifdef GL
				$display("Monitor: Video Test (GL) Passed");
			`else
				$display("Monitor: Video Test (RTL) Passed");
			`endif
			$display("%c[0m",27);
		end else begin
			$display("%c[1;31m",27);
			`ifdef GL
				$display ("Monitor: Video Test (GL) Failed");
			`else
				$display ("Monitor: Video Test (RTL) Failed");
			`endif
			$display("%c[0m",27);
		end
	    $finish;
	end

	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#300000;
		CSB = 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end

	always @(succesOutput, nextTestOutput, timingValid) begin
		#1 $display("Success:0b%b Timing Valid:0b%b Next test:0b%b", succesOutput, timingValid, nextTestOutput);
	end

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3;
	wire VDD1V8;
	wire VSS;
	
	assign VDD3V3 = power1;
	assign VDD1V8 = power2;
	assign VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda1_2  (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock    (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("video.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule