data/full_repos/permissive/529642835/rtl/Pokey/synchronizer.v
data/verilator_xmls/d01ab5d2-53ea-488f-ab99-7bc4b0f13c61.xml
module synchronizer(clk, ce, raw, sync);
   input      clk;
   input      ce;
   input      raw;
   output     sync;
   
   wire [2:0] ff_next;
   reg [2:0]  ff_reg;
   
   always @(posedge clk)
       if (ce)
         ff_reg <= ff_next;
   
   assign ff_next = {raw, ff_reg[2:1]};
   
   assign sync = ff_reg[0];
   
endmodule
module synchronizer(clk, ce, raw, sync);

   input      clk;
   input      ce;
   input      raw;
   output     sync;
   
   wire [2:0] ff_next;
   reg [2:0]  ff_reg;
   
   always @(posedge clk)
       if (ce)
         ff_reg <= ff_next;
   
   assign ff_next = {raw, ff_reg[2:1]};
   
   assign sync = ff_reg[0];
   
endmodule