data/full_repos/permissive/446939020/risc-v/mux2.v
data/verilator_xmls/a1230932-1447-4115-89b3-e5cbb5f9a461.xml
module mux2
  (input [31:0] d0, d1,
   input s,
   output [31:0] y);
     assign y = s ? d1 : d0;
endmodule
module mux2
  (input [31:0] d0, d1,
   input s,
   output [31:0] y);

     assign y = s ? d1 : d0;
endmodule