data/full_repos/permissive/515890445/ARM_MultiCycle/MultiCycle/Modules/Reg_RWE.v
data/verilator_xmls/ed8f454d-2008-49f3-906e-59f7fd4d04ac.xml
module Reg_RWE  #(
	parameter W = 4
) (
	input 	wire [W-1:0] 	In,
	input 	wire 				WE,
	input 	wire 				RESET_N,
	input 	wire 				CLK,
	output 	reg  [W-1:0]	Out
);

	initial
		Out = 0;


	always @ (negedge RESET_N or posedge CLK)
	begin

		if (!RESET_N)
			Out <= {W{1'b0}};

		else if (WE)
			Out <= In;
		
	end

endmodule
module Reg_RWE  #(
	parameter W = 4
) (
	input 	wire [W-1:0] 	In,
	input 	wire 				WE,
	input 	wire 				RESET_N,
	input 	wire 				CLK,
	output 	reg  [W-1:0]	Out
);


	initial
		Out = 0;


	always @ (negedge RESET_N or posedge CLK)
	begin

		if (!RESET_N)
			Out <= {W{1'b0}};

		else if (WE)
			Out <= In;
		
	end

endmodule