data/full_repos/permissive/463481430/simulation/tb.v
1: b'%Error: data/full_repos/permissive/463481430/simulation/tb.v:2: Cannot find include file: ../RTL/core/config.v\n`include "../RTL/core/config.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463481430/simulation,data/full_repos/permissive/463481430/../RTL/core/config.v\n             data/full_repos/permissive/463481430/simulation,data/full_repos/permissive/463481430/../RTL/core/config.v.v\n             data/full_repos/permissive/463481430/simulation,data/full_repos/permissive/463481430/../RTL/core/config.v.sv\n             ../RTL/core/config.v\n             ../RTL/core/config.v.v\n             ../RTL/core/config.v.sv\n             obj_dir/../RTL/core/config.v\n             obj_dir/../RTL/core/config.v.v\n             obj_dir/../RTL/core/config.v.sv\n%Error: data/full_repos/permissive/463481430/simulation/tb.v:3: Cannot find include file: ../RTL/core/defines.v\n`include "../RTL/core/defines.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/463481430/simulation/tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n    #1 i_clk = ~i_clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/463481430/simulation/tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #3 i_rstn = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/463481430/simulation/tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #2 i_rstn = 1;\n    ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module TEST_TOP ();

reg i_clk=1;
reg i_rstn=1;

always  begin
    #1 i_clk = ~i_clk;
end
initial begin
    i_rstn = 1;
    #3 i_rstn = 0;
    #2 i_rstn = 1;
end

SOC_TOP u_SOC_TOP(
    .i_clk   ( i_clk   ),
    .i_rstn  ( i_rstn  ),

    .i_io_rx ( 1 ),
    .o_io_tx  (   )
);




endmodule
module TEST_TOP ();


reg i_clk=1;
reg i_rstn=1;

always  begin
    #1 i_clk = ~i_clk;
end
initial begin
    i_rstn = 1;
    #3 i_rstn = 0;
    #2 i_rstn = 1;
end

SOC_TOP u_SOC_TOP(
    .i_clk   ( i_clk   ),
    .i_rstn  ( i_rstn  ),

    .i_io_rx ( 1 ),
    .o_io_tx  (   )
);




endmodule