data/full_repos/permissive/464089711/sasebo_giii_aes/aes_composite_enc.v
1: b"%Error: data/full_repos/permissive/464089711/sasebo_giii_aes/aes_composite_enc.v:181: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule AES_Comp_EncCore(di, ki, Rrg, do, ko);\n                                     ^~\n%Error: data/full_repos/permissive/464089711/sasebo_giii_aes/aes_composite_enc.v:184: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n  output [127:0] do, ko;\n                 ^~\n%Error: data/full_repos/permissive/464089711/sasebo_giii_aes/aes_composite_enc.v:205: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n  assign do = ((Rrg[0] == 1)? sr: mx) ^ ki;\n         ^~\n%Error: Exiting due to 3 error(s)\n"
function [7:0] rcon;
  input [9:0] x;
    casex (x)
      10'bxxxxxxxxx1: rcon = 8'h01;
      10'bxxxxxxxx1x: rcon = 8'h02;
      10'bxxxxxxx1xx: rcon = 8'h04;
      10'bxxxxxx1xxx: rcon = 8'h08;
      10'bxxxxx1xxxx: rcon = 8'h10;
      10'bxxxx1xxxxx: rcon = 8'h20;
      10'bxxx1xxxxxx: rcon = 8'h40;
      10'bxx1xxxxxxx: rcon = 8'h80;
      10'bx1xxxxxxxx: rcon = 8'h1b;
      10'b1xxxxxxxxx: rcon = 8'h36;
      default       : rcon = 8'h00;
    endcase
  endfunction
function [7:0] rcon;

  input [9:0] x;
    casex (x)
      10'bxxxxxxxxx1: rcon = 8'h01;
      10'bxxxxxxxx1x: rcon = 8'h02;
      10'bxxxxxxx1xx: rcon = 8'h04;
      10'bxxxxxx1xxx: rcon = 8'h08;
      10'bxxxxx1xxxx: rcon = 8'h10;
      10'bxxxx1xxxxx: rcon = 8'h20;
      10'bxxx1xxxxxx: rcon = 8'h40;
      10'bxx1xxxxxxx: rcon = 8'h80;
      10'bx1xxxxxxxx: rcon = 8'h1b;
      10'b1xxxxxxxxx: rcon = 8'h36;
      default       : rcon = 8'h00;
    endcase
  endfunction