data/full_repos/permissive/40989439/ohLocal/common/dv/dv_ctrl_local.v
data/verilator_xmls/ad7cc304-ea21-46f9-bca9-f33f0e77a7e0.xml
module dv_ctrl_local(

   nreset, clk1, clk2, start,

   dut_active, stim_done, test_done
   );

   parameter CFG_CLK1_PERIOD = 10;   
   parameter CFG_CLK1_PHASE  = CFG_CLK1_PERIOD/2;
   parameter CFG_CLK2_PERIOD = 100;
   parameter CFG_CLK2_PHASE  = CFG_CLK2_PERIOD/2;
   parameter CFG_TIMEOUT     = 50000;
   parameter TIMEOUT    = 10000;

   output nreset;
   output clk1;
   output clk2;
   output start;

   input  dut_active;
   input  stim_done;
   input  test_done;
   

   reg 	     nreset;
   reg 	     start;
   reg 	     clk1=0;
   reg 	     clk2=0;
   reg [6:0] clk1_phase;
   reg [6:0] clk2_phase;   
   integer   seed,r;





   initial
     begin
	r=$value$plusargs("SEED=%s", seed);	
	$display("SEED=%d", seed);	
`ifdef CFG_RANDOM
	clk1_phase = 1 + {$random(seed)};
	clk2_phase = 1 + {$random(seed)};
`else
	clk1_phase = CFG_CLK1_PHASE;	
	clk2_phase = CFG_CLK2_PHASE; 
`endif
	$display("clk1_phase=%d clk2_phase=%d", clk1_phase,clk2_phase);	
     end
   



   always
     #(clk1_phase) clk1 = ~clk1;




   always
     #(clk2_phase) clk2 = ~clk2;




   initial
     begin	
	#(1)
	nreset   = 'b0;	
	#(clk1_phase * 20 + 100)
	nreset   = 'b1;
     end


   always @ (posedge clk1 or negedge nreset)
     if(!nreset)
       start = 1'b0;
     else if(dut_active)       
       start = 1'b1;


   always @ (posedge clk1)


     if(nreset)
       #(TIMEOUT) $finish;	  
   	   


`ifndef VERILATOR 
   initial
     begin
	$dumpfile("waveform.vcd");
	$dumpvars(0, dv_top);
     end
`endif
   
endmodule
module dv_ctrl_local(

   nreset, clk1, clk2, start,

   dut_active, stim_done, test_done
   );


   parameter CFG_CLK1_PERIOD = 10;   
   parameter CFG_CLK1_PHASE  = CFG_CLK1_PERIOD/2;
   parameter CFG_CLK2_PERIOD = 100;
   parameter CFG_CLK2_PHASE  = CFG_CLK2_PERIOD/2;
   parameter CFG_TIMEOUT     = 50000;
   parameter TIMEOUT    = 10000;

   output nreset;
   output clk1;
   output clk2;
   output start;

   input  dut_active;
   input  stim_done;
   input  test_done;
   

   reg 	     nreset;
   reg 	     start;
   reg 	     clk1=0;
   reg 	     clk2=0;
   reg [6:0] clk1_phase;
   reg [6:0] clk2_phase;   
   integer   seed,r;





   initial
     begin
	r=$value$plusargs("SEED=%s", seed);	
	$display("SEED=%d", seed);	
`ifdef CFG_RANDOM
	clk1_phase = 1 + {$random(seed)};
	clk2_phase = 1 + {$random(seed)};
`else
	clk1_phase = CFG_CLK1_PHASE;	
	clk2_phase = CFG_CLK2_PHASE; 
`endif
	$display("clk1_phase=%d clk2_phase=%d", clk1_phase,clk2_phase);	
     end
   



   always
     #(clk1_phase) clk1 = ~clk1;




   always
     #(clk2_phase) clk2 = ~clk2;




   initial
     begin	
	#(1)
	nreset   = 'b0;	
	#(clk1_phase * 20 + 100)
	nreset   = 'b1;
     end


   always @ (posedge clk1 or negedge nreset)
     if(!nreset)
       start = 1'b0;
     else if(dut_active)       
       start = 1'b1;


   always @ (posedge clk1)


     if(nreset)
       #(TIMEOUT) $finish;	  
   	   


`ifndef VERILATOR 
   initial
     begin
	$dumpfile("waveform.vcd");
	$dumpvars(0, dv_top);
     end
`endif
   
endmodule