data/full_repos/permissive/492772061/ADPPulse/slow/ADP_Sim_Slow.srcs/sources_1/new/SlowLogicHW.v
data/verilator_xmls/ffff283d-7055-4b85-9593-01a54a458b66.xml
module SlowLogicHW(

    input wire clk,

    input wire Adp_pulse,
    

    input wire [31:0] Quench_T,
    input wire [31:0] Wait_T,
    input wire [31:0] Reset_T,
    
    input wire enable,
    input wire clear,
    

    output reg Quench,
    output reg Reset,
    

    output reg [31:0] NoP
    );

reg [1:0] state = 2'd0;

reg [31:0]clk_tgt = 32'd0;




parameter S0 = 2'd0, S1 = 2'd1, S2 = 2'd2, S3 = 2'd3;


always @ (state) 
begin
    case (state)
        S1:begin
           Quench = 1'b1;
           Reset = 1'b0;
           end
        S2:begin
           Quench = 1'b0;
           Reset = 1'b0;
           end
        S3:begin
           Quench = 1'b0;
           Reset = 1'b1;
           end
        default:begin
           Quench = 1'b0;
           Reset = 1'b0;
           end
    endcase
end

initial NoP <= 0;

always @ (posedge clk) 
begin



    if (clear)
        NoP <= 0;
        
    if (!enable) 
        begin
            state <= S0;
        end
    else 
        begin
            case (state)
               S1:
               begin
                  if(clk_tgt >= Quench_T) 
                      begin
                        clk_tgt <= 0;
                        state <= S2;
                      end
                  else
                      clk_tgt<=clk_tgt+1;
               end
               S2:
               begin
                  if(clk_tgt >= Wait_T) 
                      begin
                        clk_tgt <= 0;
                        state <= S3;
                      end
                  else
                      clk_tgt=clk_tgt+1;
               end
               S3:
               begin
                  if(clk_tgt >= Reset_T) 
                      begin
                        clk_tgt <= 0;
                        state <= S0;
                        NoP <= NoP +1;
                      end
                  else
                      clk_tgt=clk_tgt+1;
               end
               default:
               begin
                  if(Adp_pulse) 
                      begin
                        clk_tgt <= 0;
                        state = S1;
                      end
                  else
                      state <= S0;
               end
            endcase
        end
    end

endmodule
module SlowLogicHW(

    input wire clk,

    input wire Adp_pulse,
    

    input wire [31:0] Quench_T,
    input wire [31:0] Wait_T,
    input wire [31:0] Reset_T,
    
    input wire enable,
    input wire clear,
    

    output reg Quench,
    output reg Reset,
    

    output reg [31:0] NoP
    );


reg [1:0] state = 2'd0;

reg [31:0]clk_tgt = 32'd0;




parameter S0 = 2'd0, S1 = 2'd1, S2 = 2'd2, S3 = 2'd3;


always @ (state) 
begin
    case (state)
        S1:begin
           Quench = 1'b1;
           Reset = 1'b0;
           end
        S2:begin
           Quench = 1'b0;
           Reset = 1'b0;
           end
        S3:begin
           Quench = 1'b0;
           Reset = 1'b1;
           end
        default:begin
           Quench = 1'b0;
           Reset = 1'b0;
           end
    endcase
end

initial NoP <= 0;

always @ (posedge clk) 
begin



    if (clear)
        NoP <= 0;
        
    if (!enable) 
        begin
            state <= S0;
        end
    else 
        begin
            case (state)
               S1:
               begin
                  if(clk_tgt >= Quench_T) 
                      begin
                        clk_tgt <= 0;
                        state <= S2;
                      end
                  else
                      clk_tgt<=clk_tgt+1;
               end
               S2:
               begin
                  if(clk_tgt >= Wait_T) 
                      begin
                        clk_tgt <= 0;
                        state <= S3;
                      end
                  else
                      clk_tgt=clk_tgt+1;
               end
               S3:
               begin
                  if(clk_tgt >= Reset_T) 
                      begin
                        clk_tgt <= 0;
                        state <= S0;
                        NoP <= NoP +1;
                      end
                  else
                      clk_tgt=clk_tgt+1;
               end
               default:
               begin
                  if(Adp_pulse) 
                      begin
                        clk_tgt <= 0;
                        state = S1;
                      end
                  else
                      state <= S0;
               end
            endcase
        end
    end

endmodule