data/full_repos/permissive/502544928/ALU.v
data/verilator_xmls/53e67cce-c2d7-4879-82f3-7ca91477b04b.xml
module ALU #(parameter DATA_WIDTH = 32)(
		ALU_Op, 
		operand_A, operand_B, 
		ALU_result, zero
); 
input [3:0] ALU_Op; 
input [DATA_WIDTH-1:0]  operand_A ;
input [DATA_WIDTH-1:0]  operand_B ;
output zero; 
output [DATA_WIDTH-1:0] ALU_result;

assign zero = (ALU_result==0); 
assign ALU_result   = (ALU_Op == 0)? operand_A + operand_B : 
					  (ALU_Op == 1)? operand_A & operand_B :
					  (ALU_Op == 2)? ~(operand_A | operand_B) :
					  (ALU_Op == 3)? operand_A | operand_B :
					  (ALU_Op == 4)? operand_A << operand_B :
					  (ALU_Op == 5)? (operand_A < operand_B)? 1 : 0 :
					  (ALU_Op == 6)? operand_A >> operand_B :
					  (ALU_Op == 7)? operand_A >>> operand_B :
					  (ALU_Op == 8)? operand_A - operand_B :
					  (ALU_Op == 9)? operand_A ^ operand_B :
					  (ALU_Op == 10)? (operand_A == operand_B)? 0 : 1  :
					  (ALU_Op == 11)? (operand_A >= operand_B)? 0 : 1  :
					  (ALU_Op == 12)? (operand_A > operand_B)? 0 : 1  :
					  (ALU_Op == 13)? (operand_A <= operand_B)? 0 : 1  :
					  (ALU_Op == 14)? (operand_A < operand_B)? 0 : 1  :
					  (ALU_Op == 15)? (operand_A != operand_B)? 0 : 1  : 1;
endmodule
module ALU #(parameter DATA_WIDTH = 32)(
		ALU_Op, 
		operand_A, operand_B, 
		ALU_result, zero
);
 
input [3:0] ALU_Op; 
input [DATA_WIDTH-1:0]  operand_A ;
input [DATA_WIDTH-1:0]  operand_B ;
output zero; 
output [DATA_WIDTH-1:0] ALU_result;

assign zero = (ALU_result==0); 
assign ALU_result   = (ALU_Op == 0)? operand_A + operand_B : 
					  (ALU_Op == 1)? operand_A & operand_B :
					  (ALU_Op == 2)? ~(operand_A | operand_B) :
					  (ALU_Op == 3)? operand_A | operand_B :
					  (ALU_Op == 4)? operand_A << operand_B :
					  (ALU_Op == 5)? (operand_A < operand_B)? 1 : 0 :
					  (ALU_Op == 6)? operand_A >> operand_B :
					  (ALU_Op == 7)? operand_A >>> operand_B :
					  (ALU_Op == 8)? operand_A - operand_B :
					  (ALU_Op == 9)? operand_A ^ operand_B :
					  (ALU_Op == 10)? (operand_A == operand_B)? 0 : 1  :
					  (ALU_Op == 11)? (operand_A >= operand_B)? 0 : 1  :
					  (ALU_Op == 12)? (operand_A > operand_B)? 0 : 1  :
					  (ALU_Op == 13)? (operand_A <= operand_B)? 0 : 1  :
					  (ALU_Op == 14)? (operand_A < operand_B)? 0 : 1  :
					  (ALU_Op == 15)? (operand_A != operand_B)? 0 : 1  : 1;
endmodule