data/full_repos/permissive/531216051/verilog/rtl/Sha256.v
data/verilator_xmls/1e0784be-1c22-4201-b880-1a957364598a.xml
function automatic reg [31:0] right_rotate(input reg [31:0] number, input reg[31:0] n);
    right_rotate = (number >> n) | (number << (32 - n));
  endfunction
function automatic reg [31:0] right_rotate(input reg [31:0] number, input reg[31:0] n);

    right_rotate = (number >> n) | (number << (32 - n));
  endfunction