data/full_repos/permissive/436123010/design_sources/multiplexer5Bit.v
data/verilator_xmls/3a0ce6b6-cb9a-4ab9-a2db-e83bcdc61829.xml
module multiplexer5Bit(D0, D1, S, Y);
    input wire [4:0] D0, D1;
    input wire S;
    output reg [4:0] Y;
    
    always @(D0 or D1 or S)
    begin
    if(S)
        Y = D1;
    else
        Y = D0;    
    end
endmodule
module multiplexer5Bit(D0, D1, S, Y);

    input wire [4:0] D0, D1;
    input wire S;
    output reg [4:0] Y;
    
    always @(D0 or D1 or S)
    begin
    if(S)
        Y = D1;
    else
        Y = D0;    
    end
endmodule