data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c_fdp.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c_fdp.v:29: Cannot find include file: sys.h\n`include "sys.h" // system level definition file which contains the  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c_fdp.v:31: Cannot find include file: iop.h\n`include        "iop.h" \n                ^~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c_fdp.v:59: Define or directive not defined: \'`IOB_CPU_WIDTH\'\n   output [`IOB_CPU_WIDTH-1:0]     iob_cpx_req_cq;\n           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c_fdp.v:60: Define or directive not defined: \'`CPX_WIDTH\'\n   output [`CPX_WIDTH-1:0]     iob_cpx_data_ca;\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c_fdp.v:70: Define or directive not defined: \'`IOB_CPU_WIDTH\'\n   output [`IOB_CPU_WIDTH-1:0]     int_buf_cpx_req;\n           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c_fdp.v:71: Define or directive not defined: \'`IOB_CPU_WIDTH\'\n   output [`IOB_CPU_WIDTH-1:0]     io_buf_cpx_req;\n           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c_fdp.v:72: Define or directive not defined: \'`IOB_CPU_WIDTH\'\n   output [`IOB_CPU_WIDTH-1:0]     iob_cpx_req_next;\n           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c_fdp.v:76: Define or directive not defined: \'`IOB_INT_BUF_WIDTH\'\n   wire [`IOB_INT_BUF_WIDTH-1:0]   int_buf_dout;\n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c_fdp.v:79: Define or directive not defined: \'`IOB_INT_BUF_WIDTH\'\n   assign   int_buf_dout = int_buf_dout_raw[`IOB_INT_BUF_WIDTH-1:0];\n                                            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c_fdp.v:83: Define or directive not defined: \'`IOB_IO_BUF_WIDTH\'\n   wire [`IOB_IO_BUF_WIDTH-1:0]    io_buf_dout;\n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c_fdp.v:86: Define or directive not defined: \'`IOB_IO_BUF_WIDTH\'\n   assign   io_buf_dout = io_buf_dout_raw[`IOB_IO_BUF_WIDTH-1:0];\n                                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c_fdp.v:90: Define or directive not defined: \'`CPX_WIDTH\'\n   wire [`CPX_WIDTH-1:0]     iob_cpx_data_next;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c_fdp.v:91: Define or directive not defined: \'`CPX_WIDTH\'\n   wire [`CPX_WIDTH-1:0]     int_buf_cpx_data;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c_fdp.v:92: Define or directive not defined: \'`CPX_WIDTH\'\n   wire [`CPX_WIDTH-1:0]     io_buf_cpx_data;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c_fdp.v:93: Define or directive not defined: \'`CPX_WIDTH\'\n   wire [`CPX_WIDTH-1:0]     iob_cpx_data_cq;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c_fdp.v:95: Define or directive not defined: \'`IOB_INT_BUF_WIDTH\'\n   wire [`IOB_INT_BUF_WIDTH-1:0]   int_buf_dout_d1;\n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c_fdp.v:97: Define or directive not defined: \'`IOB_IO_BUF_WIDTH\'\n   wire [`IOB_IO_BUF_WIDTH-1:0]    io_buf_dout_d1;\n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c_fdp.v:106: Define or directive not defined: \'`IOB_CPU_WIDTH\'\n   assign   iob_cpx_req_next = ({`IOB_CPU_WIDTH{int_buf_sel_next}} & int_buf_cpx_req) |\n                                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c_fdp.v:107: Define or directive not defined: \'`IOB_CPU_WIDTH\'\n        ({`IOB_CPU_WIDTH{io_buf_sel_next}} & io_buf_cpx_req);\n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c_fdp.v:109: Define or directive not defined: \'`IOB_CPU_WIDTH\'\n   dff_ns #(`IOB_CPU_WIDTH) iob_cpx_req_cq_ff (.din(iob_cpx_req_next),\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c_fdp.v:113: Define or directive not defined: \'`CPX_WIDTH\'\n   assign   iob_cpx_data_next = ({`CPX_WIDTH{int_buf_sel_next}} & int_buf_cpx_data) |\n                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c_fdp.v:114: Define or directive not defined: \'`CPX_WIDTH\'\n         ({`CPX_WIDTH{io_buf_sel_next}} & io_buf_cpx_data);\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c_fdp.v:116: Define or directive not defined: \'`CPX_WIDTH\'\n   dff_ns #(`CPX_WIDTH) iob_cpx_data_cq_ff (.din(iob_cpx_data_next),\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c_fdp.v:121: Define or directive not defined: \'`CPX_WIDTH\'\n   dff_ns #(`CPX_WIDTH) iob_cpx_data_ca_ff (.din(iob_cpx_data_cq),\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c_fdp.v:133: Define or directive not defined: \'`IOB_INT_BUF_WIDTH\'\n   dffe_ns #(`IOB_INT_BUF_WIDTH) int_buf_dout_d1_ff (.din(int_buf_dout),\n             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c_fdp.v:148: Define or directive not defined: \'`IOB_IO_BUF_WIDTH\'\n   dffe_ns #(`IOB_IO_BUF_WIDTH) io_buf_dout_d1_ff (.din(io_buf_dout),\n             ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 26 error(s)\n'
module i2c_fdp (

   iob_cpx_req_cq, iob_cpx_data_ca, int_buf_cpx_req, io_buf_cpx_req, 
   iob_cpx_req_next, 

   cpu_clk, rx_sync, int_buf_sel_next, io_buf_sel_next, int_buf_rd, 
   io_buf_rd, int_buf_dout_raw, io_buf_dout_raw
   );
   




   input 		           cpu_clk;
   input 			   rx_sync;
   
   

   output [`IOB_CPU_WIDTH-1:0] 	   iob_cpx_req_cq;
   output [`CPX_WIDTH-1:0] 	   iob_cpx_data_ca;
   
    

   input 			   int_buf_sel_next;
   input 			   io_buf_sel_next;

   input 			   int_buf_rd;
   input 			   io_buf_rd;

   output [`IOB_CPU_WIDTH-1:0] 	   int_buf_cpx_req;
   output [`IOB_CPU_WIDTH-1:0] 	   io_buf_cpx_req;
   output [`IOB_CPU_WIDTH-1:0] 	   iob_cpx_req_next;

   

   wire [`IOB_INT_BUF_WIDTH-1:0]   int_buf_dout;
   input [159:0] 		   int_buf_dout_raw;

   assign 	 int_buf_dout = int_buf_dout_raw[`IOB_INT_BUF_WIDTH-1:0];

   

   wire [`IOB_IO_BUF_WIDTH-1:0]    io_buf_dout;
   input [159:0] 		   io_buf_dout_raw;
   
   assign 	 io_buf_dout = io_buf_dout_raw[`IOB_IO_BUF_WIDTH-1:0];



   wire [`CPX_WIDTH-1:0] 	   iob_cpx_data_next;
   wire [`CPX_WIDTH-1:0] 	   int_buf_cpx_data;
   wire [`CPX_WIDTH-1:0] 	   io_buf_cpx_data;
   wire [`CPX_WIDTH-1:0] 	   iob_cpx_data_cq;
   
   wire [`IOB_INT_BUF_WIDTH-1:0]   int_buf_dout_d1;

   wire [`IOB_IO_BUF_WIDTH-1:0]    io_buf_dout_d1;

   




   assign 	 iob_cpx_req_next = ({`IOB_CPU_WIDTH{int_buf_sel_next}} & int_buf_cpx_req) |
				    ({`IOB_CPU_WIDTH{io_buf_sel_next}} & io_buf_cpx_req);
   
   dff_ns #(`IOB_CPU_WIDTH) iob_cpx_req_cq_ff (.din(iob_cpx_req_next),
					       .clk(cpu_clk),
					       .q(iob_cpx_req_cq));

   assign 	 iob_cpx_data_next = ({`CPX_WIDTH{int_buf_sel_next}} & int_buf_cpx_data) |
				     ({`CPX_WIDTH{io_buf_sel_next}} & io_buf_cpx_data);
   
   dff_ns #(`CPX_WIDTH) iob_cpx_data_cq_ff (.din(iob_cpx_data_next),
					    .clk(cpu_clk),
					    .q(iob_cpx_data_cq));


   dff_ns #(`CPX_WIDTH) iob_cpx_data_ca_ff (.din(iob_cpx_data_cq),
					    .clk(cpu_clk),
					    .q(iob_cpx_data_ca));

   




   dffe_ns #(`IOB_INT_BUF_WIDTH) int_buf_dout_d1_ff (.din(int_buf_dout),
						     .en(int_buf_rd),
						     .clk(cpu_clk),
						     .q(int_buf_dout_d1));

   assign 	 {int_buf_cpx_req,
		  int_buf_cpx_data} = int_buf_dout_d1;

   




   dffe_ns #(`IOB_IO_BUF_WIDTH) io_buf_dout_d1_ff (.din(io_buf_dout),
						   .en(io_buf_rd),
						   .clk(cpu_clk),
						   .q(io_buf_dout_d1));

   assign 	 {io_buf_cpx_req,
		  io_buf_cpx_data} = io_buf_dout_d1;
	  
   
endmodule
module i2c_fdp (

   iob_cpx_req_cq, iob_cpx_data_ca, int_buf_cpx_req, io_buf_cpx_req, 
   iob_cpx_req_next, 

   cpu_clk, rx_sync, int_buf_sel_next, io_buf_sel_next, int_buf_rd, 
   io_buf_rd, int_buf_dout_raw, io_buf_dout_raw
   );

   




   input 		           cpu_clk;
   input 			   rx_sync;
   
   

   output [`IOB_CPU_WIDTH-1:0] 	   iob_cpx_req_cq;
   output [`CPX_WIDTH-1:0] 	   iob_cpx_data_ca;
   
    

   input 			   int_buf_sel_next;
   input 			   io_buf_sel_next;

   input 			   int_buf_rd;
   input 			   io_buf_rd;

   output [`IOB_CPU_WIDTH-1:0] 	   int_buf_cpx_req;
   output [`IOB_CPU_WIDTH-1:0] 	   io_buf_cpx_req;
   output [`IOB_CPU_WIDTH-1:0] 	   iob_cpx_req_next;

   

   wire [`IOB_INT_BUF_WIDTH-1:0]   int_buf_dout;
   input [159:0] 		   int_buf_dout_raw;

   assign 	 int_buf_dout = int_buf_dout_raw[`IOB_INT_BUF_WIDTH-1:0];

   

   wire [`IOB_IO_BUF_WIDTH-1:0]    io_buf_dout;
   input [159:0] 		   io_buf_dout_raw;
   
   assign 	 io_buf_dout = io_buf_dout_raw[`IOB_IO_BUF_WIDTH-1:0];



   wire [`CPX_WIDTH-1:0] 	   iob_cpx_data_next;
   wire [`CPX_WIDTH-1:0] 	   int_buf_cpx_data;
   wire [`CPX_WIDTH-1:0] 	   io_buf_cpx_data;
   wire [`CPX_WIDTH-1:0] 	   iob_cpx_data_cq;
   
   wire [`IOB_INT_BUF_WIDTH-1:0]   int_buf_dout_d1;

   wire [`IOB_IO_BUF_WIDTH-1:0]    io_buf_dout_d1;

   




   assign 	 iob_cpx_req_next = ({`IOB_CPU_WIDTH{int_buf_sel_next}} & int_buf_cpx_req) |
				    ({`IOB_CPU_WIDTH{io_buf_sel_next}} & io_buf_cpx_req);
   
   dff_ns #(`IOB_CPU_WIDTH) iob_cpx_req_cq_ff (.din(iob_cpx_req_next),
					       .clk(cpu_clk),
					       .q(iob_cpx_req_cq));

   assign 	 iob_cpx_data_next = ({`CPX_WIDTH{int_buf_sel_next}} & int_buf_cpx_data) |
				     ({`CPX_WIDTH{io_buf_sel_next}} & io_buf_cpx_data);
   
   dff_ns #(`CPX_WIDTH) iob_cpx_data_cq_ff (.din(iob_cpx_data_next),
					    .clk(cpu_clk),
					    .q(iob_cpx_data_cq));


   dff_ns #(`CPX_WIDTH) iob_cpx_data_ca_ff (.din(iob_cpx_data_cq),
					    .clk(cpu_clk),
					    .q(iob_cpx_data_ca));

   




   dffe_ns #(`IOB_INT_BUF_WIDTH) int_buf_dout_d1_ff (.din(int_buf_dout),
						     .en(int_buf_rd),
						     .clk(cpu_clk),
						     .q(int_buf_dout_d1));

   assign 	 {int_buf_cpx_req,
		  int_buf_cpx_data} = int_buf_dout_d1;

   




   dffe_ns #(`IOB_IO_BUF_WIDTH) io_buf_dout_d1_ff (.din(io_buf_dout),
						   .en(io_buf_rd),
						   .clk(cpu_clk),
						   .q(io_buf_dout_d1));

   assign 	 {io_buf_cpx_req,
		  io_buf_cpx_data} = io_buf_dout_d1;
	  
   
endmodule