data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/aes/aes_1cc.v
1: b"%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/aes/aes_1cc.v:37: Cannot find file containing module: 'KeyExpansion'\n  KeyExpansion e (.key(key), .expandedKey(expandedKey));\n  ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/aes,data/full_repos/permissive/486954482/KeyExpansion\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/aes,data/full_repos/permissive/486954482/KeyExpansion.v\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/aes,data/full_repos/permissive/486954482/KeyExpansion.sv\n             KeyExpansion\n             KeyExpansion.v\n             KeyExpansion.sv\n             obj_dir/KeyExpansion\n             obj_dir/KeyExpansion.v\n             obj_dir/KeyExpansion.sv\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/aes/aes_1cc.v:47: Cannot find file containing module: 'AddRoundKey'\n  AddRoundKey a(.x(msg), .y(expandedKeyi[0]), .z(x1[0]));\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/aes/aes_1cc.v:52: Cannot find file containing module: 'SubBytes'\n    SubBytes a(.x(x1[i]), .z(x2[i]));\n    ^~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/aes/aes_1cc.v:59: Cannot find file containing module: 'ShiftRows'\n    ShiftRows c(.x(x2[i]), .z(x3[i]));\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/aes/aes_1cc.v:66: Cannot find file containing module: 'MixColumns'\n    MixColumns d(.x(x3[i]), .z(x4[i]));\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/aes/aes_1cc.v:76: Cannot find file containing module: 'AddRoundKey'\n      AddRoundKey a(.x(x4[i]), .y(expandedKeyi[i+1]), .z(x1[i+1]));\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/aes/aes_1cc.v:74: Cannot find file containing module: 'AddRoundKey'\n      AddRoundKey a(.x(x3[i]), .y(expandedKeyi[i+1]), .z(out));\n      ^~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module aes_1cc
(
  clk,
  rst,
  g_input,
  e_input,
  o
);
  localparam    NR = 10;
  input                 clk;
  input                 rst;
  input   [127:0]       g_input;
  input   [127:0]       e_input;
  output  [127:0]       o;

  wire    [127:0]          key;
  wire    [127:0]          msg;
  wire    [127:0]          out;
  wire    [128*(NR+1)-1:0] expandedKey;
  wire    [127:0]          expandedKeyi[NR:0];
  wire    [127:0]          x1[NR-1:0];
  wire    [127:0]          x2[NR-1:0];
  wire    [127:0]          x3[NR-1:0];
  wire    [127:0]          x4[NR-2:0];


  assign  key = g_input;   
  assign  msg = e_input;
  assign  o = out;

  genvar i;

  KeyExpansion e (.key(key), .expandedKey(expandedKey));


  generate 
  for(i=0;i<(NR+1);i=i+1)
  begin:EXPANDKEY
    assign expandedKeyi[i] = expandedKey[128*(i+1)-1:128*i];
  end
  endgenerate

  AddRoundKey a(.x(msg), .y(expandedKeyi[0]), .z(x1[0]));

  generate 
  for(i=0;i<NR;i=i+1)
  begin:SUBBYTES
    SubBytes a(.x(x1[i]), .z(x2[i]));
  end
  endgenerate

  generate 
  for(i=0;i<NR;i=i+1)
  begin:SHIFTROWS
    ShiftRows c(.x(x2[i]), .z(x3[i]));
  end
  endgenerate

  generate 
  for(i=0;i<NR-1;i=i+1)
  begin:MIXCOLUMNS
    MixColumns d(.x(x3[i]), .z(x4[i]));
  end
  endgenerate

  generate 
  for(i=0;i<NR;i=i+1)
  begin:ADDROUNDKEY
    if(i==NR-1) begin:LAST
      AddRoundKey a(.x(x3[i]), .y(expandedKeyi[i+1]), .z(out));
    end else begin:ELSE
      AddRoundKey a(.x(x4[i]), .y(expandedKeyi[i+1]), .z(x1[i+1]));
    end
  end
  endgenerate


endmodule
module aes_1cc
(
  clk,
  rst,
  g_input,
  e_input,
  o
);

  localparam    NR = 10;
  input                 clk;
  input                 rst;
  input   [127:0]       g_input;
  input   [127:0]       e_input;
  output  [127:0]       o;

  wire    [127:0]          key;
  wire    [127:0]          msg;
  wire    [127:0]          out;
  wire    [128*(NR+1)-1:0] expandedKey;
  wire    [127:0]          expandedKeyi[NR:0];
  wire    [127:0]          x1[NR-1:0];
  wire    [127:0]          x2[NR-1:0];
  wire    [127:0]          x3[NR-1:0];
  wire    [127:0]          x4[NR-2:0];


  assign  key = g_input;   
  assign  msg = e_input;
  assign  o = out;

  genvar i;

  KeyExpansion e (.key(key), .expandedKey(expandedKey));


  generate 
  for(i=0;i<(NR+1);i=i+1)
  begin:EXPANDKEY
    assign expandedKeyi[i] = expandedKey[128*(i+1)-1:128*i];
  end
  endgenerate

  AddRoundKey a(.x(msg), .y(expandedKeyi[0]), .z(x1[0]));

  generate 
  for(i=0;i<NR;i=i+1)
  begin:SUBBYTES
    SubBytes a(.x(x1[i]), .z(x2[i]));
  end
  endgenerate

  generate 
  for(i=0;i<NR;i=i+1)
  begin:SHIFTROWS
    ShiftRows c(.x(x2[i]), .z(x3[i]));
  end
  endgenerate

  generate 
  for(i=0;i<NR-1;i=i+1)
  begin:MIXCOLUMNS
    MixColumns d(.x(x3[i]), .z(x4[i]));
  end
  endgenerate

  generate 
  for(i=0;i<NR;i=i+1)
  begin:ADDROUNDKEY
    if(i==NR-1) begin:LAST
      AddRoundKey a(.x(x3[i]), .y(expandedKeyi[i+1]), .z(out));
    end else begin:ELSE
      AddRoundKey a(.x(x4[i]), .y(expandedKeyi[i+1]), .z(x1[i+1]));
    end
  end
  endgenerate


endmodule