data/full_repos/permissive/452215364/rtl/opl2/operator/syn_fifo.v
data/verilator_xmls/c2910f74-2677-4aca-a382-314d7c05e393.xml
module syn_fifo (
clk      ,
rst      ,
data_in  ,
rd_en    ,
wr_en    ,
data_out ,
empty    ,
half_full,
full
);    
 

parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 10;
parameter RAM_DEPTH = (1 << ADDR_WIDTH);

input clk ;
input rst ;
input rd_en ;
input wr_en ;
input [DATA_WIDTH-1:0] data_in ;
output full ;
output half_full;
output empty ;
output [DATA_WIDTH-1:0] data_out ;


reg [ADDR_WIDTH-1:0] wr_pointer;
reg [ADDR_WIDTH-1:0] rd_pointer;
reg [ADDR_WIDTH :0] status_cnt;
reg [DATA_WIDTH-1:0] data_out ;
reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0];

assign full = (status_cnt == (RAM_DEPTH-1));
assign half_full = (status_cnt >= (RAM_DEPTH/2));
assign empty = (status_cnt == 0);


always @ (posedge clk or posedge rst)
begin : WRITE_POINTER
  if (rst) begin
    wr_pointer <= 0;
  end else if (wr_en ) begin
    wr_pointer <= wr_pointer + 1;
  end
end

always @ (posedge clk or posedge rst)
begin : READ_POINTER
  if (rst) begin
    rd_pointer <= 0;
  end else if (rd_en ) begin
    rd_pointer <= rd_pointer + 1;
  end
end


always @ (posedge clk or posedge rst)
begin : STATUS_COUNTER
  if (rst) begin
    status_cnt <= 0;

  end else if (rd_en && !wr_en 
                && (status_cnt != 0)) begin
    status_cnt <= status_cnt - 1;

  end else if (wr_en && !rd_en 
               && (status_cnt != RAM_DEPTH)) begin
    status_cnt <= status_cnt + 1;
  end
end 


always @(posedge clk)
begin
  if (wr_en)
    ram[wr_pointer] <= data_in;
end

always @(posedge clk or posedge rst)
begin
  if (rst) begin
    data_out <= 0;
  end else if (rd_en )
    data_out <= ram[rd_pointer];
end


endmodule
module syn_fifo (
clk      ,
rst      ,
data_in  ,
rd_en    ,
wr_en    ,
data_out ,
empty    ,
half_full,
full
);
    
 

parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 10;
parameter RAM_DEPTH = (1 << ADDR_WIDTH);

input clk ;
input rst ;
input rd_en ;
input wr_en ;
input [DATA_WIDTH-1:0] data_in ;
output full ;
output half_full;
output empty ;
output [DATA_WIDTH-1:0] data_out ;


reg [ADDR_WIDTH-1:0] wr_pointer;
reg [ADDR_WIDTH-1:0] rd_pointer;
reg [ADDR_WIDTH :0] status_cnt;
reg [DATA_WIDTH-1:0] data_out ;
reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0];

assign full = (status_cnt == (RAM_DEPTH-1));
assign half_full = (status_cnt >= (RAM_DEPTH/2));
assign empty = (status_cnt == 0);


always @ (posedge clk or posedge rst)
begin : WRITE_POINTER
  if (rst) begin
    wr_pointer <= 0;
  end else if (wr_en ) begin
    wr_pointer <= wr_pointer + 1;
  end
end

always @ (posedge clk or posedge rst)
begin : READ_POINTER
  if (rst) begin
    rd_pointer <= 0;
  end else if (rd_en ) begin
    rd_pointer <= rd_pointer + 1;
  end
end


always @ (posedge clk or posedge rst)
begin : STATUS_COUNTER
  if (rst) begin
    status_cnt <= 0;

  end else if (rd_en && !wr_en 
                && (status_cnt != 0)) begin
    status_cnt <= status_cnt - 1;

  end else if (wr_en && !rd_en 
               && (status_cnt != RAM_DEPTH)) begin
    status_cnt <= status_cnt + 1;
  end
end 


always @(posedge clk)
begin
  if (wr_en)
    ram[wr_pointer] <= data_in;
end

always @(posedge clk or posedge rst)
begin
  if (rst) begin
    data_out <= 0;
  end else if (rd_en )
    data_out <= ram[rd_pointer];
end


endmodule