data/full_repos/permissive/495910568/rtl/frequency_divider/test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/495910568/rtl/frequency_divider/test.v:20: Unsupported: Ignoring delay on this delayed statement.\n        forever #10 clock_in = ~clock_in;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/495910568/rtl/frequency_divider/test.v:12: Cannot find file containing module: \'freq_divider\'\n freq_divider uut (\n ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/495910568/rtl/frequency_divider,data/full_repos/permissive/495910568/freq_divider\n             data/full_repos/permissive/495910568/rtl/frequency_divider,data/full_repos/permissive/495910568/freq_divider.v\n             data/full_repos/permissive/495910568/rtl/frequency_divider,data/full_repos/permissive/495910568/freq_divider.sv\n             freq_divider\n             freq_divider.v\n             freq_divider.sv\n             obj_dir/freq_divider\n             obj_dir/freq_divider.v\n             obj_dir/freq_divider.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_clock_divider;

 reg clock_in;

 wire clock_out;


 freq_divider uut (
  .clock_in(clock_in), 
  .clock_out(clock_out)
 );
 initial begin

  clock_in = 0;

        forever #10 clock_in = ~clock_in;
 end
      
endmodule
module tb_clock_divider;


 reg clock_in;

 wire clock_out;


 freq_divider uut (
  .clock_in(clock_in), 
  .clock_out(clock_out)
 );
 initial begin

  clock_in = 0;

        forever #10 clock_in = ~clock_in;
 end
      
endmodule