data/full_repos/permissive/487031610/verilog/rtl/mini_design.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/487031610/verilog/rtl/mini_design.v:19: Multiple top level modules\n                                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                    : ... Top module \'lesson1\'\nmodule lesson1(\n       ^~~~~~~\n                                                                                    : ... Top module \'lesson2\'\nmodule lesson2(\n       ^~~~~~~\n                                                                                    : ... Top module \'lesson3\'\nmodule lesson3(\n       ^~~~~~~\n                                                                                    : ... Top module \'lesson4\'\nmodule lesson4(\n       ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/487031610/verilog/rtl/mini_design.v:97: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n                                                                                 : ... In instance lesson4\n    assign outputs[7:1] = 6\'b0;\n                        ^\n%Error: Exiting due to 2 warning(s)\n'
module lesson4(
    input wire [NUM_IOS-1:0] inputs,
    output wire [NUM_IOS-1:0] outputs
);
    parameter NUM_IOS = 8;


    reg [17:0] morse;
    reg [4:0] count;
    wire clk = inputs[0];
    wire reset = inputs[1];
    assign outputs[0] = morse[count];
    assign outputs[7:1] = 6'b0;
    always @(posedge clk) begin
        if(reset) begin
            count <= 17;
            morse <= 18'b110110010011001100;
        end else begin
            count <= count - 1;
            if(count == 0)
                count <= 17;
        end
    end


endmodule
module lesson4(
    input wire [NUM_IOS-1:0] inputs,
    output wire [NUM_IOS-1:0] outputs
);

    parameter NUM_IOS = 8;


    reg [17:0] morse;
    reg [4:0] count;
    wire clk = inputs[0];
    wire reset = inputs[1];
    assign outputs[0] = morse[count];
    assign outputs[7:1] = 6'b0;
    always @(posedge clk) begin
        if(reset) begin
            count <= 17;
            morse <= 18'b110110010011001100;
        end else begin
            count <= count - 1;
            if(count == 0)
                count <= 17;
        end
    end


endmodule