data/full_repos/permissive/485085993/verilog/rtl/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v
1: b"%Error: data/full_repos/permissive/485085993/verilog/rtl/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v:51: Cannot find file containing module: 'DFFSRQ'\n DFFSRQ DFFSRQ_0_ (\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/DFFSRQ\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/DFFSRQ.v\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/DFFSRQ.sv\n             DFFSRQ\n             DFFSRQ.v\n             DFFSRQ.sv\n             obj_dir/DFFSRQ\n             obj_dir/DFFSRQ.v\n             obj_dir/DFFSRQ.sv\n%Error: Exiting due to 1 error(s)\n"
module logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff(set,
                                                                              reset,
                                                                              clk,
                                                                              ff_D,
                                                                              ff_Q,
                                                                              ff_clk);

input [0:0] set;

input [0:0] reset;

input [0:0] clk;

input [0:0] ff_D;

output [0:0] ff_Q;

input [0:0] ff_clk;


wire [0:0] ff_D;
wire [0:0] ff_Q;
wire [0:0] ff_clk;













	DFFSRQ DFFSRQ_0_ (
		.SET(set),
		.RST(reset),
		.CK(clk),
		.D(ff_D),
		.Q(ff_Q));

endmodule
module logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff(set,
                                                                              reset,
                                                                              clk,
                                                                              ff_D,
                                                                              ff_Q,
                                                                              ff_clk);


input [0:0] set;

input [0:0] reset;

input [0:0] clk;

input [0:0] ff_D;

output [0:0] ff_Q;

input [0:0] ff_clk;


wire [0:0] ff_D;
wire [0:0] ff_Q;
wire [0:0] ff_clk;













	DFFSRQ DFFSRQ_0_ (
		.SET(set),
		.RST(reset),
		.CK(clk),
		.D(ff_D),
		.Q(ff_Q));

endmodule