data/full_repos/permissive/509468557/sims/firesim/sim/midas/src/main/verilog/BUFGCE.v
data/verilator_xmls/f3fc9511-6664-498f-b2c8-3131cb2d0343.xml
module BUFGCE(
  input      I,
  input      CE,
  output reg O
);
   reg       enable_latch;
   always @(posedge I)
     enable_latch <= CE;
`ifdef VERILATOR


   assign O = (I & enable_latch);
`else



   always @(posedge I or negedge I) begin
     if (CE)
       O = I;
     else
       O = 1'h0;
   end
`endif
endmodule
module BUFGCE(
  input      I,
  input      CE,
  output reg O
);

   reg       enable_latch;
   always @(posedge I)
     enable_latch <= CE;
`ifdef VERILATOR


   assign O = (I & enable_latch);
`else



   always @(posedge I or negedge I) begin
     if (CE)
       O = I;
     else
       O = 1'h0;
   end
`endif
endmodule