data/full_repos/permissive/462323524/platform/sky130_fd_sc_hvl/sky130_fd_sc_hvl_ff_map.v
1: b'%Error: data/full_repos/permissive/462323524/platform/sky130_fd_sc_hvl/sky130_fd_sc_hvl_ff_map.v:36: Unsupported or unknown PLI call: $adff\n    $adff  #( \n    ^~~~~\n%Error: data/full_repos/permissive/462323524/platform/sky130_fd_sc_hvl/sky130_fd_sc_hvl_ff_map.v:36: syntax error, unexpected ${ignored-bbox-sys}\n    $adff  #( \n         ^\n%Error: data/full_repos/permissive/462323524/platform/sky130_fd_sc_hvl/sky130_fd_sc_hvl_ff_map.v:66: Unsupported or unknown PLI call: $dff\n    $dff  #( \n    ^~~~\n%Error: data/full_repos/permissive/462323524/platform/sky130_fd_sc_hvl/sky130_fd_sc_hvl_ff_map.v:66: syntax error, unexpected ${ignored-bbox-sys}\n    $dff  #( \n        ^\n%Error: data/full_repos/permissive/462323524/platform/sky130_fd_sc_hvl/sky130_fd_sc_hvl_ff_map.v:95: Unsupported or unknown PLI call: $dffsr\n    $dffsr  #( \n    ^~~~~~\n%Error: data/full_repos/permissive/462323524/platform/sky130_fd_sc_hvl/sky130_fd_sc_hvl_ff_map.v:95: syntax error, unexpected ${ignored-bbox-sys}\n    $dffsr  #( \n          ^\n%Error: data/full_repos/permissive/462323524/platform/sky130_fd_sc_hvl/sky130_fd_sc_hvl_ff_map.v:128: Unsupported or unknown PLI call: $aldff\n    $aldff  #( \n    ^~~~~~\n%Error: data/full_repos/permissive/462323524/platform/sky130_fd_sc_hvl/sky130_fd_sc_hvl_ff_map.v:128: syntax error, unexpected ${ignored-bbox-sys}\n    $aldff  #( \n          ^\n%Error: data/full_repos/permissive/462323524/platform/sky130_fd_sc_hvl/sky130_fd_sc_hvl_ff_map.v:192: Unsupported or unknown PLI call: $sdff\n    $sdff  #( \n    ^~~~~\n%Error: data/full_repos/permissive/462323524/platform/sky130_fd_sc_hvl/sky130_fd_sc_hvl_ff_map.v:192: syntax error, unexpected ${ignored-bbox-sys}\n    $sdff  #( \n         ^\n%Error: Exiting due to 10 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module \$adffe (ARST, CLK, D, EN, Q);
    parameter ARST_POLARITY =1'b1;
    parameter ARST_VALUE  =1'b0;
    parameter CLK_POLARITY =1'b1;
    parameter EN_POLARITY =1'b1;
    parameter WIDTH =1;

    input ARST, CLK, EN;
    input [WIDTH -1 :0] D; 
    output [WIDTH -1 :0] Q;

    wire GCLK;

  
    sky130_fd_sc_hvl__dlclkp_1  clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
   

    $adff  #( 
            .WIDTH(WIDTH), 
            .CLK_POLARITY(CLK_POLARITY),
            .ARST_VALUE(ARST_VALUE) ,
            .ARST_POLARITY (ARST_POLARITY)
            ) 
            flipflop(  
            .CLK(GCLK), 
            .ARST(ARST),
            .D(D), 
            .Q(Q)
            );
endmodule
module \$adffe (ARST, CLK, D, EN, Q);

    parameter ARST_POLARITY =1'b1;
    parameter ARST_VALUE  =1'b0;
    parameter CLK_POLARITY =1'b1;
    parameter EN_POLARITY =1'b1;
    parameter WIDTH =1;

    input ARST, CLK, EN;
    input [WIDTH -1 :0] D; 
    output [WIDTH -1 :0] Q;

    wire GCLK;

  
    sky130_fd_sc_hvl__dlclkp_1  clk_gate ( .GCLK(GCLK), .CLK(CLK), .GATE(EN) );
   

    $adff  #( 
            .WIDTH(WIDTH), 
            .CLK_POLARITY(CLK_POLARITY),
            .ARST_VALUE(ARST_VALUE) ,
            .ARST_POLARITY (ARST_POLARITY)
            ) 
            flipflop(  
            .CLK(GCLK), 
            .ARST(ARST),
            .D(D), 
            .Q(Q)
            );
endmodule