data/full_repos/permissive/478970138/4-6/user/src/top.v
1: b'%Warning-WIDTH: data/full_repos/permissive/478970138/4-6/user/src/top.v:15: Operator ADD expects 8 bits on the LHS, but LHS\'s VARREF \'t0\' generates 4 bits.\n                                                                          : ... In instance multiplier4\n    assign S = t0 + {t1, 1\'b0} + {t2, 2\'b0} + {t3, 3\'b0};\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/478970138/4-6/user/src/top.v:15: Operator ADD expects 8 bits on the RHS, but RHS\'s REPLICATE generates 5 bits.\n                                                                          : ... In instance multiplier4\n    assign S = t0 + {t1, 1\'b0} + {t2, 2\'b0} + {t3, 3\'b0};\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/478970138/4-6/user/src/top.v:15: Operator ADD expects 8 bits on the RHS, but RHS\'s REPLICATE generates 6 bits.\n                                                                          : ... In instance multiplier4\n    assign S = t0 + {t1, 1\'b0} + {t2, 2\'b0} + {t3, 3\'b0};\n                               ^\n%Error: Exiting due to 3 warning(s)\n'
module multiplier4(A, B, S);
    input [3:0] A, B;
    output [7:0] S;

    wire [3:0] t0, t1, t2, t3;


    assign t0 = {4{A[0]}} & B;
    assign t1 = {4{A[1]}} & B;
    assign t2 = {4{A[2]}} & B;
    assign t3 = {4{A[3]}} & B;


    assign S = t0 + {t1, 1'b0} + {t2, 2'b0} + {t3, 3'b0};

endmodule
module multiplier4(A, B, S);

    input [3:0] A, B;
    output [7:0] S;

    wire [3:0] t0, t1, t2, t3;


    assign t0 = {4{A[0]}} & B;
    assign t1 = {4{A[1]}} & B;
    assign t2 = {4{A[2]}} & B;
    assign t3 = {4{A[3]}} & B;


    assign S = t0 + {t1, 1'b0} + {t2, 2'b0} + {t3, 3'b0};

endmodule