data/full_repos/permissive/433336136/cpu/Risc_16_bit.v
1: b'%Error: data/full_repos/permissive/433336136/cpu/Risc_16_bit.v:1: Cannot find include file: Control_Unit.v\n`include "Control_Unit.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/433336136/cpu,data/full_repos/permissive/433336136/Control_Unit.v\n             data/full_repos/permissive/433336136/cpu,data/full_repos/permissive/433336136/Control_Unit.v.v\n             data/full_repos/permissive/433336136/cpu,data/full_repos/permissive/433336136/Control_Unit.v.sv\n             Control_Unit.v\n             Control_Unit.v.v\n             Control_Unit.v.sv\n             obj_dir/Control_Unit.v\n             obj_dir/Control_Unit.v.v\n             obj_dir/Control_Unit.v.sv\n%Error: data/full_repos/permissive/433336136/cpu/Risc_16_bit.v:2: Cannot find include file: Datapath_Unit.v\n`include "Datapath_Unit.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module Risc_16_bit(
 input clk
);
 wire jump,bne,beq,mem_read,mem_write,alu_src,reg_dst,mem_to_reg,reg_write;
 wire[1:0] alu_op;
 wire [3:0] opcode;

 Datapath_Unit DU
 (
  .clk(clk),
  .jump(jump),
  .beq(beq),
  .mem_read(mem_read),
  .mem_write(mem_write),
  .alu_src(alu_src),
  .reg_dst(reg_dst),
  .mem_to_reg(mem_to_reg),
  .reg_write(reg_write),
  .bne(bne),
  .alu_op(alu_op),
  .opcode(opcode)
 );

 Control_Unit control
 (
  .opcode(opcode),
  .reg_dst(reg_dst),
  .mem_to_reg(mem_to_reg),
  .alu_op(alu_op),
  .jump(jump),
  .bne(bne),
  .beq(beq),
  .mem_read(mem_read),
  .mem_write(mem_write),
  .alu_src(alu_src),
  .reg_write(reg_write)
 );

endmodule
module Risc_16_bit(
 input clk
);

 wire jump,bne,beq,mem_read,mem_write,alu_src,reg_dst,mem_to_reg,reg_write;
 wire[1:0] alu_op;
 wire [3:0] opcode;

 Datapath_Unit DU
 (
  .clk(clk),
  .jump(jump),
  .beq(beq),
  .mem_read(mem_read),
  .mem_write(mem_write),
  .alu_src(alu_src),
  .reg_dst(reg_dst),
  .mem_to_reg(mem_to_reg),
  .reg_write(reg_write),
  .bne(bne),
  .alu_op(alu_op),
  .opcode(opcode)
 );

 Control_Unit control
 (
  .opcode(opcode),
  .reg_dst(reg_dst),
  .mem_to_reg(mem_to_reg),
  .alu_op(alu_op),
  .jump(jump),
  .bne(bne),
  .beq(beq),
  .mem_read(mem_read),
  .mem_write(mem_write),
  .alu_src(alu_src),
  .reg_write(reg_write)
 );

endmodule