data/full_repos/permissive/449142214/Project files/debouncer.v
1: b'%Error: Cannot find file containing module: files,data/full_repos/permissive/449142214\n        ... Looked in:\n             data/full_repos/permissive/449142214/Project/files,data/full_repos/permissive/449142214\n             data/full_repos/permissive/449142214/Project/files,data/full_repos/permissive/449142214.v\n             data/full_repos/permissive/449142214/Project/files,data/full_repos/permissive/449142214.sv\n             files,data/full_repos/permissive/449142214\n             files,data/full_repos/permissive/449142214.v\n             files,data/full_repos/permissive/449142214.sv\n             obj_dir/files,data/full_repos/permissive/449142214\n             obj_dir/files,data/full_repos/permissive/449142214.v\n             obj_dir/files,data/full_repos/permissive/449142214.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/449142214/Project\n%Error: Cannot find file containing module: files/debouncer.v\n%Error: Exiting due to 3 error(s)\n'
module debouncer(input D,input CLK_190,input RESET,output OUT);
reg A,B,C;
always @(posedge CLK_190,posedge RESET)
begin
    if (RESET == 1)
        begin
            A = 0;
            B = 0;
            C = 0;
        end
    else
        begin
            A <= D;
            B <= A;
            C <= B;
        end
end
assign OUT = A & B & ~C;
 
endmodule
module debouncer(input D,input CLK_190,input RESET,output OUT);

reg A,B,C;
always @(posedge CLK_190,posedge RESET)
begin
    if (RESET == 1)
        begin
            A = 0;
            B = 0;
            C = 0;
        end
    else
        begin
            A <= D;
            B <= A;
            C <= B;
        end
end
assign OUT = A & B & ~C;
 
endmodule