data/full_repos/permissive/509468557/generators/icenet/src/main/resources/vsrc/TraceROM.v
1: b'%Warning-WIDTH: data/full_repos/permissive/509468557/generators/icenet/src/main/resources/vsrc/TraceROM.v:56: Operator ASSIGN expects 48 bits on the Assign RHS, but Assign RHS\'s VARREF \'__macAddr\' generates 64 bits.\n                                                                                                            : ... In instance TraceROM\n            macAddr_reg = __macAddr;\n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module TraceROM (
    input         clock,
    input         reset,
    output        stream_valid,
    input         stream_ready,
    output [63:0] stream_bits_data,
    output [7:0]  stream_bits_keep,
    output        stream_bits_last,
    output [47:0] macAddr,
    output [31:0] length
);

    bit     __stream_valid;
    longint __stream_data;
    byte    __stream_keep;
    bit     __stream_last;

    reg        __stream_valid_reg;
    reg [63:0] __stream_data_reg;
    reg [7:0]  __stream_keep_reg;
    reg        __stream_last_reg;

    string fname;
    longint __macAddr;
    int     __length;

    reg [47:0] macAddr_reg;
    reg [31:0] length_reg;

    assign macAddr = macAddr_reg;
    assign length  = length_reg;

    assign stream_valid = __stream_valid_reg;
    assign stream_bits_data = __stream_data_reg;
    assign stream_bits_keep = __stream_keep_reg;
    assign stream_bits_last = __stream_last_reg;

    initial begin
        if ($value$plusargs("trace=%s", fname)) begin
            __length = trace_rom_init(fname);
            length_reg = __length;
        end
        if ($value$plusargs("macaddr=%x", __macAddr)) begin
            macAddr_reg = __macAddr;
        end
    end

    always @(posedge clock) begin
        if (reset) begin
            __stream_valid = 0;
            __stream_data  = 0;
            __stream_keep  = 0;
            __stream_last  = 0;

            __stream_valid_reg <= 0;
            __stream_data_reg  <= 0;
            __stream_keep_reg  <= 0;
            __stream_last_reg  <= 0;
        end else begin
            trace_rom_tick(
                __stream_valid,
                stream_ready,
                __stream_data,
                __stream_keep,
                __stream_last);

            __stream_valid_reg <= __stream_valid;
            __stream_data_reg  <= __stream_data;
            __stream_keep_reg  <= __stream_keep;
            __stream_last_reg  <= __stream_last;
        end
    end
endmodule
module TraceROM (
    input         clock,
    input         reset,
    output        stream_valid,
    input         stream_ready,
    output [63:0] stream_bits_data,
    output [7:0]  stream_bits_keep,
    output        stream_bits_last,
    output [47:0] macAddr,
    output [31:0] length
);


    bit     __stream_valid;
    longint __stream_data;
    byte    __stream_keep;
    bit     __stream_last;

    reg        __stream_valid_reg;
    reg [63:0] __stream_data_reg;
    reg [7:0]  __stream_keep_reg;
    reg        __stream_last_reg;

    string fname;
    longint __macAddr;
    int     __length;

    reg [47:0] macAddr_reg;
    reg [31:0] length_reg;

    assign macAddr = macAddr_reg;
    assign length  = length_reg;

    assign stream_valid = __stream_valid_reg;
    assign stream_bits_data = __stream_data_reg;
    assign stream_bits_keep = __stream_keep_reg;
    assign stream_bits_last = __stream_last_reg;

    initial begin
        if ($value$plusargs("trace=%s", fname)) begin
            __length = trace_rom_init(fname);
            length_reg = __length;
        end
        if ($value$plusargs("macaddr=%x", __macAddr)) begin
            macAddr_reg = __macAddr;
        end
    end

    always @(posedge clock) begin
        if (reset) begin
            __stream_valid = 0;
            __stream_data  = 0;
            __stream_keep  = 0;
            __stream_last  = 0;

            __stream_valid_reg <= 0;
            __stream_data_reg  <= 0;
            __stream_keep_reg  <= 0;
            __stream_last_reg  <= 0;
        end else begin
            trace_rom_tick(
                __stream_valid,
                stream_ready,
                __stream_data,
                __stream_keep,
                __stream_last);

            __stream_valid_reg <= __stream_valid;
            __stream_data_reg  <= __stream_data;
            __stream_keep_reg  <= __stream_keep;
            __stream_last_reg  <= __stream_last;
        end
    end
endmodule