data/full_repos/permissive/419538859/lab1_1/lab1_1_tb.v
1: b'%Error: data/full_repos/permissive/419538859/lab1_1/lab1_1_tb.v:10: Unsupported: Verilog 2001-config reserved word not implemented: \'instance\'\nlab1_1 instance(\n       ^~~~~~~~\n%Error: data/full_repos/permissive/419538859/lab1_1/lab1_1_tb.v:11: syntax error, unexpected \'(\', expecting IDENTIFIER\n    .clk(clk),\n    ^\n%Error: data/full_repos/permissive/419538859/lab1_1/lab1_1_tb.v:26: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("wave.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/419538859/lab1_1/lab1_1_tb.v:27: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,testbench);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab1_1/lab1_1_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n #(clkper / 2)  clk = ~clk;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab1_1/lab1_1_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #20;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab1_1/lab1_1_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n #1980000;  \n ^\n%Error: Exiting due to 4 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module 	testbench();
reg clk;	 	    
reg reset;	    
wire [7:0]shift_out; 

wire ctl_bit;

lab1_1 instance(
				.clk(clk),
				.reset(reset),
				.shift_out(shift_out), 
				.ctl_bit(ctl_bit)
				);


parameter	clkper = 5;

initial
begin
	clk = 1;
end

initial begin
	$dumpfile("wave.vcd");
	$dumpvars(0,testbench);
end

always 
begin
	#(clkper / 2)  clk = ~clk;
end

initial
begin
 reset	=1'b1;
 #20;		
 reset  =1'b0;
 #1980000;		
end
endmodule
module 	testbench();

reg clk;	 	    
reg reset;	    
wire [7:0]shift_out; 

wire ctl_bit;

lab1_1 instance(
				.clk(clk),
				.reset(reset),
				.shift_out(shift_out), 
				.ctl_bit(ctl_bit)
				);


parameter	clkper = 5;

initial
begin
	clk = 1;
end

initial begin
	$dumpfile("wave.vcd");
	$dumpvars(0,testbench);
end

always 
begin
	#(clkper / 2)  clk = ~clk;
end

initial
begin
 reset	=1'b1;
 #20;		
 reset  =1'b0;
 #1980000;		
end
endmodule