data/full_repos/permissive/452648646/test/cpu.t.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/452648646/test/cpu.t.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/452648646/test/cpu.t.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/452648646/test/cpu.t.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/452648646/test/cpu.t.v:44: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/452648646/test/cpu.t.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk = 0;\n    ^\n%Error: data/full_repos/permissive/452648646/test/cpu.t.v:12: Cannot find file containing module: \'cpu\'\ncpu cpu(\n^~~\n        ... Looked in:\n             data/full_repos/permissive/452648646/test,data/full_repos/permissive/452648646/cpu\n             data/full_repos/permissive/452648646/test,data/full_repos/permissive/452648646/cpu.v\n             data/full_repos/permissive/452648646/test,data/full_repos/permissive/452648646/cpu.sv\n             cpu\n             cpu.v\n             cpu.sv\n             obj_dir/cpu\n             obj_dir/cpu.v\n             obj_dir/cpu.sv\n%Error: data/full_repos/permissive/452648646/test/cpu.t.v:23: Cannot find file containing module: \'memory\'\nmemory memory (\n^~~~~~\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cpu_test();

reg clk;
reg rst;
wire [31:0] memory_in;
wire [31:0] memory_out;
wire [31:2] address;
wire write_enable;
wire write_capable;
wire read_capable;

cpu cpu(
  .clk(clk),
  .rst(rst),
  .memory_out(memory_out),
  .memory_in(memory_in),
  .address(address),
  .write_enable(write_enable),
  .read_capable(read_capable),
  .write_capable(write_capable)
);

memory memory (
  .clk(clk),
  .memory_out(memory_out),
  .memory_in(memory_in),
  .address(address),
  .write_enable(write_enable),
  .read_capable(read_capable),
  .write_capable(write_capable)
);

initial begin
  rst = 1;
  clk = 0;
  #10;
  clk = 1;
  #10;
  rst = 0;
  clk = 0;
  #10;

  forever begin
    #10 clk = 1;

    `ifdef VERBOSE
    $display("%h %b - %h %b - %h %b (%b)", { address, 2'd0 }, address, memory_out, memory_out, memory_in, memory_in, write_enable);
    `endif

    #10 clk = 0;
  end
end

endmodule
module cpu_test();


reg clk;
reg rst;
wire [31:0] memory_in;
wire [31:0] memory_out;
wire [31:2] address;
wire write_enable;
wire write_capable;
wire read_capable;

cpu cpu(
  .clk(clk),
  .rst(rst),
  .memory_out(memory_out),
  .memory_in(memory_in),
  .address(address),
  .write_enable(write_enable),
  .read_capable(read_capable),
  .write_capable(write_capable)
);

memory memory (
  .clk(clk),
  .memory_out(memory_out),
  .memory_in(memory_in),
  .address(address),
  .write_enable(write_enable),
  .read_capable(read_capable),
  .write_capable(write_capable)
);

initial begin
  rst = 1;
  clk = 0;
  #10;
  clk = 1;
  #10;
  rst = 0;
  clk = 0;
  #10;

  forever begin
    #10 clk = 1;

    `ifdef VERBOSE
    $display("%h %b - %h %b - %h %b (%b)", { address, 2'd0 }, address, memory_out, memory_out, memory_in, memory_in, write_enable);
    `endif

    #10 clk = 0;
  end
end

endmodule