data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Counters/Count_clock_4/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Counters/Count_clock_4,data/full_repos/permissive/500128826\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/Count_clock_4,data/full_repos/permissive/500128826\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/Count_clock_4,data/full_repos/permissive/500128826.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/Count_clock_4,data/full_repos/permissive/500128826.sv\n             Logic/Counters/Count_clock_4,data/full_repos/permissive/500128826\n             Logic/Counters/Count_clock_4,data/full_repos/permissive/500128826.v\n             Logic/Counters/Count_clock_4,data/full_repos/permissive/500128826.sv\n             obj_dir/Logic/Counters/Count_clock_4,data/full_repos/permissive/500128826\n             obj_dir/Logic/Counters/Count_clock_4,data/full_repos/permissive/500128826.v\n             obj_dir/Logic/Counters/Count_clock_4,data/full_repos/permissive/500128826.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Logic/Counters/Count_clock_4/top_module.v\n%Error: Exiting due to 3 error(s)\n'
module bcdcount24h (
    input wire clk,
    input wire reset,
    input wire enable,
    output wire [23:0] Q
);

  reg [3:0] seconds0;
  reg [3:0] seconds1;
  reg [3:0] minutes0;
  reg [3:0] minutes1;
  reg [3:0] hours0;
  reg [3:0] hours1;

  wire increment_seconds1, increment_minutes0, increment_minutes1, increment_hours0, increment_hours1;
  assign increment_seconds1 = seconds0 == 4'd9;
  assign increment_minutes0 = seconds1 == 4'd5 && increment_seconds1;
  assign increment_minutes1 = minutes0 == 4'd9 && increment_minutes0;
  assign increment_hours0   = minutes1 == 4'd5 && increment_minutes1;
  assign increment_hours1   = hours0 == 4'd9 && increment_hours0;

  always @(posedge clk) begin
    if (reset) {hours1, hours0, minutes1, minutes0, seconds1, seconds0} = 24'd0;
    else if (enable) begin
      if ({hours1, hours0, minutes1, minutes0, seconds1, seconds0} == 24'h235959) begin
        {hours1, hours0, minutes1, minutes0, seconds1, seconds0} <= 24'd0;
      end else begin
        if (increment_hours1) begin
          {hours0, minutes1, minutes0, seconds1, seconds0} <= 1'd0;
          hours1 <= hours1 + 1'd1;
        end else if (increment_hours0) begin
          {minutes1, minutes0, seconds1, seconds0} <= 1'd0;
          hours0 <= hours0 + 1'd1;
        end else if (increment_minutes1) begin
          {minutes0, seconds1, seconds0} <= 1'd0;
          minutes1 <= minutes1 + 1'd1;
        end else if (increment_minutes0) begin
          {seconds1, seconds0} <= 1'd0;
          minutes0 <= minutes0 + 1'd1;
        end else if (increment_seconds1) begin
          {seconds0} <= 1'd0;
          seconds1   <= seconds1 + 1'd1;
        end else begin
          seconds0 = seconds0 + 1'd1;
        end
      end

    end
  end

  assign Q = {hours1, hours0, minutes1, minutes0, seconds1, seconds0};

endmodule
module bcdcount24h (
    input wire clk,
    input wire reset,
    input wire enable,
    output wire [23:0] Q
);


  reg [3:0] seconds0;
  reg [3:0] seconds1;
  reg [3:0] minutes0;
  reg [3:0] minutes1;
  reg [3:0] hours0;
  reg [3:0] hours1;

  wire increment_seconds1, increment_minutes0, increment_minutes1, increment_hours0, increment_hours1;
  assign increment_seconds1 = seconds0 == 4'd9;
  assign increment_minutes0 = seconds1 == 4'd5 && increment_seconds1;
  assign increment_minutes1 = minutes0 == 4'd9 && increment_minutes0;
  assign increment_hours0   = minutes1 == 4'd5 && increment_minutes1;
  assign increment_hours1   = hours0 == 4'd9 && increment_hours0;

  always @(posedge clk) begin
    if (reset) {hours1, hours0, minutes1, minutes0, seconds1, seconds0} = 24'd0;
    else if (enable) begin
      if ({hours1, hours0, minutes1, minutes0, seconds1, seconds0} == 24'h235959) begin
        {hours1, hours0, minutes1, minutes0, seconds1, seconds0} <= 24'd0;
      end else begin
        if (increment_hours1) begin
          {hours0, minutes1, minutes0, seconds1, seconds0} <= 1'd0;
          hours1 <= hours1 + 1'd1;
        end else if (increment_hours0) begin
          {minutes1, minutes0, seconds1, seconds0} <= 1'd0;
          hours0 <= hours0 + 1'd1;
        end else if (increment_minutes1) begin
          {minutes0, seconds1, seconds0} <= 1'd0;
          minutes1 <= minutes1 + 1'd1;
        end else if (increment_minutes0) begin
          {seconds1, seconds0} <= 1'd0;
          minutes0 <= minutes0 + 1'd1;
        end else if (increment_seconds1) begin
          {seconds0} <= 1'd0;
          seconds1   <= seconds1 + 1'd1;
        end else begin
          seconds0 = seconds0 + 1'd1;
        end
      end

    end
  end

  assign Q = {hours1, hours0, minutes1, minutes0, seconds1, seconds0};

endmodule