data/full_repos/permissive/480681467/Source/Main/main.v
1: b'%Warning-WIDTH: data/full_repos/permissive/480681467/Source/Main/main.v:32: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'msg_in\' generates 32 bits.\n                                                                          : ... In instance control\n         msg_reg <= msg_in;\n                 ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/480681467/Source/Main/main.v:35: Cannot find file containing module: \'inverter\'\n    inverter i(p,q,clk,reset,inverter_finish,e,d);\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/480681467/Source/Main,data/full_repos/permissive/480681467/inverter\n             data/full_repos/permissive/480681467/Source/Main,data/full_repos/permissive/480681467/inverter.v\n             data/full_repos/permissive/480681467/Source/Main,data/full_repos/permissive/480681467/inverter.sv\n             inverter\n             inverter.v\n             inverter.sv\n             obj_dir/inverter\n             obj_dir/inverter.v\n             obj_dir/inverter.sv\n%Error: data/full_repos/permissive/480681467/Source/Main/main.v:37: Cannot find file containing module: \'mod_exp\'\n    mod_exp m(msg_reg,mod_reg,exp_reg,clk,reset1,mod_exp_finish,msg_out);\n    ^~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module control(
    input [WIDTH-1:0] p,q,
    input clk,
    input reset,
    input reset1,
    input encrypt_decrypt,
    input [WIDTH-1:0] msg_in,
    output [WIDTH*2-1:0] msg_out,
    output mod_exp_finish
    );
   
    parameter WIDTH = 32;
    
    wire inverter_finish;
    wire [WIDTH*2-1:0] e,d;
    wire [WIDTH*2-1:0] exponent = encrypt_decrypt?e:d;
    wire [WIDTH*2-1:0] modulo = p*q;
    wire mod_exp_reset  = 1'b0;
    
    reg [WIDTH*2-1:0] exp_reg,msg_reg;
    reg [WIDTH*2-1:0] mod_reg;
    
    always @(posedge clk)begin
         exp_reg <= exponent;
         mod_reg <= modulo;
         msg_reg <= msg_in;
    end
    
    inverter i(p,q,clk,reset,inverter_finish,e,d);
    defparam i.WIDTH = WIDTH;
    mod_exp m(msg_reg,mod_reg,exp_reg,clk,reset1,mod_exp_finish,msg_out);
    defparam m.WIDTH = WIDTH;
    
endmodule
module control(
    input [WIDTH-1:0] p,q,
    input clk,
    input reset,
    input reset1,
    input encrypt_decrypt,
    input [WIDTH-1:0] msg_in,
    output [WIDTH*2-1:0] msg_out,
    output mod_exp_finish
    );

   
    parameter WIDTH = 32;
    
    wire inverter_finish;
    wire [WIDTH*2-1:0] e,d;
    wire [WIDTH*2-1:0] exponent = encrypt_decrypt?e:d;
    wire [WIDTH*2-1:0] modulo = p*q;
    wire mod_exp_reset  = 1'b0;
    
    reg [WIDTH*2-1:0] exp_reg,msg_reg;
    reg [WIDTH*2-1:0] mod_reg;
    
    always @(posedge clk)begin
         exp_reg <= exponent;
         mod_reg <= modulo;
         msg_reg <= msg_in;
    end
    
    inverter i(p,q,clk,reset,inverter_finish,e,d);
    defparam i.WIDTH = WIDTH;
    mod_exp m(msg_reg,mod_reg,exp_reg,clk,reset1,mod_exp_finish,msg_out);
    defparam m.WIDTH = WIDTH;
    
endmodule