data/full_repos/permissive/512077043/rgb_fifo/async-fifo_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_fifo/async-fifo_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #0.005  \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_fifo/async-fifo_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n        #0.1\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_fifo/async-fifo_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n        #0.01\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_fifo/async-fifo_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n        #0.005  \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_fifo/async-fifo_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n            #0.05\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_fifo/async-fifo_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n            #0.01\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_fifo/async-fifo_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n            #0.05\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_fifo/async-fifo_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n            #0.01\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_fifo/async-fifo_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n            #0.05\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_fifo/async-fifo_tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n            #0.01\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_fifo/async-fifo_tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n            #0.05\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_fifo/async-fifo_tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n            #0.01\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_fifo/async-fifo_tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n            #0.1\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_fifo/async-fifo_tb.v:129: Unsupported: Ignoring delay on this delayed statement.\n            #0.01\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_fifo/async-fifo_tb.v:134: Unsupported: Ignoring delay on this delayed statement.\n            #0.1\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_fifo/async-fifo_tb.v:138: Unsupported: Ignoring delay on this delayed statement.\n            #0.01\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_fifo/async-fifo_tb.v:143: Unsupported: Ignoring delay on this delayed statement.\n            #0.1\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_fifo/async-fifo_tb.v:145: Unsupported: Ignoring delay on this delayed statement.\n            #0.01\n            ^\n%Error: data/full_repos/permissive/512077043/rgb_fifo/async-fifo_tb.v:156: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("async-fifo_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/512077043/rgb_fifo/async-fifo_tb.v:157: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, async_fifo_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/512077043/rgb_fifo/async-fifo_tb.v:160: Unsupported: Ignoring delay on this delayed statement.\n        #(DURATION)\n        ^\n%Error: Exiting due to 2 error(s), 19 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module async_fifo_tb();


    localparam  DATA_SIZE = 32;
    localparam  ADDR_SIZE = 8;
    

    wire    [DATA_SIZE-1:0]     r_data;
    wire                        r_empty;
    wire                        r_full;
    

    reg                         r_en = 0;
    reg                         r_clk = 0;
    reg                         r_rst = 0;
    reg     [DATA_SIZE-1:0]     w_data;
    reg                         w_en = 0;
    reg                         w_clk = 0;
    reg                         w_rst = 0;
    

    integer                     i;
    

    localparam DURATION = 10000;
    

    always begin
        #0.005
        r_clk = ~r_clk;
        w_clk = ~w_clk;
    end
    

    async_fifo #(
        .DATA_SIZE(DATA_SIZE),
        .ADDR_SIZE(ADDR_SIZE)
    ) uut (
        .w_data(w_data),
        .w_en(w_en),
        .w_clk(w_clk),
        .w_rst(w_rst),
        .r_en(r_en),
        .r_clk(r_clk),
        .r_rst(r_rst),
        .w_full(w_full),
        .r_data(r_data),
        .r_empty(r_empty)
    );
    

    initial begin
    

        #0.1
        w_rst = 1;
        r_rst = 1;
        #0.01
        w_rst = 0;
        r_rst = 0;
        #0.005
        r_rst = 0;
        

        for (i = 0; i < 4; i = i + 1) begin
            #0.05
            w_data = i;
            w_en = 1'b1;
            #0.01
            w_en = 1'b0;
        end
        

        for (i = 0; i < 6; i = i + 1) begin
            #0.05
            r_en = 1'b1;
            #0.01
            r_en = 1'b0;
        end
        

        for (i = 0; i < 18; i = i + 1) begin
            #0.05
            w_en = 1'b1;
            w_data = i;
            #0.01
            w_en = 1'b0;
        end
        

        for (i = 0; i < 20; i = i + 1) begin
            #0.05
            r_en = 1'b1;
            #0.01
            r_en = 1'b0;
        end


        for (i = 0; i < 3; i = i + 1) begin
            #0.1
            w_en = 1'b1;
            w_data = i;
            #0.01
            w_en = 1'b0;
        end

        for (i = 3; i < 15; i = i + 1) begin
            #0.1
            r_en = 1'b1;
            w_en = 1'b1;
            w_data = i;
            #0.01
            w_en = 1'b0;
            r_en = 1'b0;
        end
        for (i = 15; i < 20; i = i + 1) begin
            #0.1
            r_en = 1'b1;
            #0.01
            r_en = 1'b0;
        end


    end
    

    initial begin
    

        $dumpfile("async-fifo_tb.vcd");
        $dumpvars(0, async_fifo_tb);
        

        #(DURATION)
        

        $display("Finished!");
        $finish;
    end

endmodule
module async_fifo_tb();



    localparam  DATA_SIZE = 32;
    localparam  ADDR_SIZE = 8;
    

    wire    [DATA_SIZE-1:0]     r_data;
    wire                        r_empty;
    wire                        r_full;
    

    reg                         r_en = 0;
    reg                         r_clk = 0;
    reg                         r_rst = 0;
    reg     [DATA_SIZE-1:0]     w_data;
    reg                         w_en = 0;
    reg                         w_clk = 0;
    reg                         w_rst = 0;
    

    integer                     i;
    

    localparam DURATION = 10000;
    

    always begin
        #0.005
        r_clk = ~r_clk;
        w_clk = ~w_clk;
    end
    

    async_fifo #(
        .DATA_SIZE(DATA_SIZE),
        .ADDR_SIZE(ADDR_SIZE)
    ) uut (
        .w_data(w_data),
        .w_en(w_en),
        .w_clk(w_clk),
        .w_rst(w_rst),
        .r_en(r_en),
        .r_clk(r_clk),
        .r_rst(r_rst),
        .w_full(w_full),
        .r_data(r_data),
        .r_empty(r_empty)
    );
    

    initial begin
    

        #0.1
        w_rst = 1;
        r_rst = 1;
        #0.01
        w_rst = 0;
        r_rst = 0;
        #0.005
        r_rst = 0;
        

        for (i = 0; i < 4; i = i + 1) begin
            #0.05
            w_data = i;
            w_en = 1'b1;
            #0.01
            w_en = 1'b0;
        end
        

        for (i = 0; i < 6; i = i + 1) begin
            #0.05
            r_en = 1'b1;
            #0.01
            r_en = 1'b0;
        end
        

        for (i = 0; i < 18; i = i + 1) begin
            #0.05
            w_en = 1'b1;
            w_data = i;
            #0.01
            w_en = 1'b0;
        end
        

        for (i = 0; i < 20; i = i + 1) begin
            #0.05
            r_en = 1'b1;
            #0.01
            r_en = 1'b0;
        end


        for (i = 0; i < 3; i = i + 1) begin
            #0.1
            w_en = 1'b1;
            w_data = i;
            #0.01
            w_en = 1'b0;
        end

        for (i = 3; i < 15; i = i + 1) begin
            #0.1
            r_en = 1'b1;
            w_en = 1'b1;
            w_data = i;
            #0.01
            w_en = 1'b0;
            r_en = 1'b0;
        end
        for (i = 15; i < 20; i = i + 1) begin
            #0.1
            r_en = 1'b1;
            #0.01
            r_en = 1'b0;
        end


    end
    

    initial begin
    

        $dumpfile("async-fifo_tb.vcd");
        $dumpvars(0, async_fifo_tb);
        

        #(DURATION)
        

        $display("Finished!");
        $finish;
    end

endmodule