data/full_repos/permissive/500396778/3-Bit-Synchronous-Up-Down-Counter/Up.v
data/verilator_xmls/459ae218-bb26-4ae7-a4df-789f645db6b0.xml
module and2 (input wire i0, i1, output wire o);
  assign o = i0 & i1;
endmodule
module and2 (input wire i0, i1, output wire o);

  assign o = i0 & i1;
endmodule