data/full_repos/permissive/453280627/RTL/tb/tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/453280627/RTL/tb/tb.sv:32: Unsupported: Ignoring delay on this delayed statement.\n forever #(0.5) clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/453280627/RTL/tb/tb.sv:38: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/453280627/RTL/tb/tb.sv:40: Unsupported: Ignoring delay on this delayed statement.\n #(ADC_WIDTH+timeoffset)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/453280627/RTL/tb/tb.sv:42: Unsupported: Ignoring delay on this delayed statement.\n #(ADC_WIDTH+timeoffset)\n ^\n%Error: data/full_repos/permissive/453280627/RTL/tb/tb.sv:65: syntax error, unexpected \'@\'\n @(posedge clk)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/453280627/RTL/tb/tb.sv:74: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/453280627/RTL/tb/tb.sv:76: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n%Error: data/full_repos/permissive/453280627/RTL/tb/tb.sv:96: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tb.lxt");   \n ^~~~~~~~~\n%Error: data/full_repos/permissive/453280627/RTL/tb/tb.sv:97: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, test);    \n ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();


`define ANL_vol 0.6

`define ADC_bits 8

parameter ADC_WIDTH = `ADC_bits;
`ifdef random_test
logic [ADC_WIDTH-1:0]test_sig = $random();
`else
parameter vol_input = `ANL_vol;
parameter test_sig = vol_input*(2**ADC_WIDTH-1);
`endif


parameter timeoffset = 4;

logic clk;
logic rst_n;
logic cmp;
logic start;
logic [ADC_WIDTH-1:0] DACF;
logic eoc;
logic den;
logic [ADC_WIDTH-1:0] Dout;


initial begin
	clk = '0;
	forever #(0.5) clk = ~clk;
end


initial begin
	adcrst();
	#1
	startsw();
	#(ADC_WIDTH+timeoffset)
	startsw();
	#(ADC_WIDTH+timeoffset)
	`ifdef random_test
	$display("|---------------------------|");
	$display("|---随机测试，目标值=%d---",test_sig);
	$display("|---------------------------|");
	`else
	$display("|---------------------------|");
	$display("|-------指定目标值=%d-------",test_sig);
	$display("|---------------------------|");
	`endif
	$finish;
end


always@(*) begin
	if(DACF>test_sig)
		cmp = '0;
	else
		cmp = '1;
end

task startsw;
	start <= '0;
	@(posedge clk)
	start <= '1;
	@(posedge clk)
	start <= '0;
endtask : startsw

task adcrst;
	rst_n <= '0;
	start <= '0;
	#10
	rst_n <= '1;
	#5;
endtask : adcrst



SAR_ADC #(
		.ADC_WIDTH(ADC_WIDTH)
	) test (
		.clk   (clk),
		.rst_n (rst_n),
		.cmp   (cmp),
		.start (start),
		.DACF  (DACF),
		.eoc   (eoc),
		.den   (den),
		.Dout  (Dout)
	);


initial begin
	$dumpfile("tb.lxt");
	$dumpvars(0, test);
end

endmodule
module tb();



`define ANL_vol 0.6

`define ADC_bits 8

parameter ADC_WIDTH = `ADC_bits;
`ifdef random_test
logic [ADC_WIDTH-1:0]test_sig = $random();
`else
parameter vol_input = `ANL_vol;
parameter test_sig = vol_input*(2**ADC_WIDTH-1);
`endif


parameter timeoffset = 4;

logic clk;
logic rst_n;
logic cmp;
logic start;
logic [ADC_WIDTH-1:0] DACF;
logic eoc;
logic den;
logic [ADC_WIDTH-1:0] Dout;


initial begin
	clk = '0;
	forever #(0.5) clk = ~clk;
end


initial begin
	adcrst();
	#1
	startsw();
	#(ADC_WIDTH+timeoffset)
	startsw();
	#(ADC_WIDTH+timeoffset)
	`ifdef random_test
	$display("|---------------------------|");
	$display("|---随机测试，目标值=%d---",test_sig);
	$display("|---------------------------|");
	`else
	$display("|---------------------------|");
	$display("|-------指定目标值=%d-------",test_sig);
	$display("|---------------------------|");
	`endif
	$finish;
end


always@(*) begin
	if(DACF>test_sig)
		cmp = '0;
	else
		cmp = '1;
end

task startsw;
	start <= '0;
	@(posedge clk)
	start <= '1;
	@(posedge clk)
	start <= '0;
endtask : startsw

task adcrst;
	rst_n <= '0;
	start <= '0;
	#10
	rst_n <= '1;
	#5;
endtask : adcrst



SAR_ADC #(
		.ADC_WIDTH(ADC_WIDTH)
	) test (
		.clk   (clk),
		.rst_n (rst_n),
		.cmp   (cmp),
		.start (start),
		.DACF  (DACF),
		.eoc   (eoc),
		.den   (den),
		.Dout  (Dout)
	);


initial begin
	$dumpfile("tb.lxt");
	$dumpvars(0, test);
end

endmodule