data/full_repos/permissive/436064619/tb_cpu.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_cpu.v:21: Unsupported: Ignoring delay on this delayed statement.\nforever #T  clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/436064619/tb_cpu.v:26: Unsupported: $fopen with multichannel descriptor.  Add ,"w" as second argument to open a file descriptor.\nhandle3 = $fopen ("stim_proj.out");\n          ^~~~~~\n%Error: data/full_repos/permissive/436064619/tb_cpu.v:27: Unsupported or unknown PLI call: $shm_open\n  $shm_open("shm.db",1);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/436064619/tb_cpu.v:28: Unsupported or unknown PLI call: $shm_probe\n  $shm_probe(stimulus,"AS");\n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/436064619/tb_cpu.v:29: Unsupported or unknown PLI call: $shm_close\n  #500  $shm_close();\n        ^~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_cpu.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #500  $shm_close();\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_cpu.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #1 $finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_cpu.v:37: Unsupported: Ignoring delay on this delayed statement.\n#1 $fdisplay(desc3, $time,"clk=%b, addressA=%d, addressB=%d, dataIn=%d, opsel=%d, outsel=%d, asel=%d, bsel=%d, oen=%d, OUT=%d", clk, addressA, addressB, dataIn, opsel, outsel,asel, bsel, oen, outPut);\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_cpu.v:47: Unsupported: Ignoring delay on this delayed statement.\n#T\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_cpu.v:66: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_cpu.v:87: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_cpu.v:109: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_cpu.v:129: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_cpu.v:152: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_cpu.v:150: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_cpu.v:171: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_cpu.v:190: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_cpu.v:209: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_cpu.v:228: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Error: Exiting due to 4 error(s), 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module stimulus;

parameter T = 20;

reg [31:0] dataIn;
reg [1:0] opsel, outsel;
reg [4:0] addressA, addressB;
reg asel, bsel, oen, clk;

wire [31:0] outPut;
wire over;


integer handle3,desc3;


cpu proj(addressA, addressB, dataIn, asel,bsel, clk, opsel, outsel, oen, outPut, over);
initial
begin
clk = 1'b1;
forever #T  clk = ~clk;
end

initial
 begin
handle3 = $fopen ("stim_proj.out");
  $shm_open("shm.db",1);
  $shm_probe(stimulus,"AS");
  #500  $shm_close();
  #1 $finish;
  end


always
begin
desc3=handle3;
#1 $fdisplay(desc3, $time,"clk=%b, addressA=%d, addressB=%d, dataIn=%d, opsel=%d, outsel=%d, asel=%d, bsel=%d, oen=%d, OUT=%d", clk, addressA, addressB, dataIn, opsel, outsel,asel, bsel, oen, outPut);

end


initial
 begin



#T

addressA = 5'b00000;

addressB = 5'b00000;

dataIn = 32'hFFFF_FFE7;  

opsel = 2'b01;

outsel =2'b00;

asel = 0;

bsel = 0;

oen = 1;


#(T*2)




addressA=5'b00000;

addressB= 5'b00001;

dataIn = 32'hF;  

opsel = 2'b01;

outsel = 2'b00;

asel = 0;

bsel = 0;

oen = 1;

#(T*2)



addressA = 5'b00000;

addressB = 5'b00010;

dataIn = 32'h23; 

opsel = 2'b01;

outsel =2'b00;

asel = 0;

bsel = 0;

oen = 1;



#(T*2)



addressA = 5'b00000;

addressB = 5'b10100;

dataIn = 32'h37;   

opsel = 2'b01;

outsel =2'b00;

asel = 0;

bsel = 0;

oen = 1;

#(T*2)



addressA = 5'd0;

addressB = 5'd1;

dataIn = 32'd0;

opsel = 2'b00;

outsel =2'b01;

asel = 1;

bsel = 1;

oen = 1;


#(T*2)

#(T*2)


addressA = 5'd1;

addressB = 5'd2;

dataIn = 32'd0;

opsel = 2'b00;

outsel =2'b01;

asel = 1;

bsel = 1;

oen = 1;

#(T*2)


addressA = 5'd2;

addressB = 5'd20;

dataIn = 32'd0;

opsel = 2'b01;

outsel =2'b01;

asel = 1;

bsel = 1;

oen = 1;

#(T*2)


addressA = 5'd1;

addressB = 5'd1;

dataIn = 32'd0;

opsel = 2'b01;

outsel =2'b00;

asel = 1;

bsel = 0;

oen = 1;

#(T*2)


addressA = 5'd2;

addressB = 5'd2;

dataIn = 32'd0;

opsel = 2'b01;

outsel =2'b00;

asel = 1;

bsel = 0;

oen = 1;

#(T*2)


addressA = 5'd20;

addressB = 5'd20;

dataIn = 32'd0;

opsel = 2'b01;

outsel =2'b00;

asel = 1;

bsel = 0;

oen = 1;

end
endmodule
module stimulus;


parameter T = 20;

reg [31:0] dataIn;
reg [1:0] opsel, outsel;
reg [4:0] addressA, addressB;
reg asel, bsel, oen, clk;

wire [31:0] outPut;
wire over;


integer handle3,desc3;


cpu proj(addressA, addressB, dataIn, asel,bsel, clk, opsel, outsel, oen, outPut, over);
initial
begin
clk = 1'b1;
forever #T  clk = ~clk;
end

initial
 begin
handle3 = $fopen ("stim_proj.out");
  $shm_open("shm.db",1);
  $shm_probe(stimulus,"AS");
  #500  $shm_close();
  #1 $finish;
  end


always
begin
desc3=handle3;
#1 $fdisplay(desc3, $time,"clk=%b, addressA=%d, addressB=%d, dataIn=%d, opsel=%d, outsel=%d, asel=%d, bsel=%d, oen=%d, OUT=%d", clk, addressA, addressB, dataIn, opsel, outsel,asel, bsel, oen, outPut);

end


initial
 begin



#T

addressA = 5'b00000;

addressB = 5'b00000;

dataIn = 32'hFFFF_FFE7;  

opsel = 2'b01;

outsel =2'b00;

asel = 0;

bsel = 0;

oen = 1;


#(T*2)




addressA=5'b00000;

addressB= 5'b00001;

dataIn = 32'hF;  

opsel = 2'b01;

outsel = 2'b00;

asel = 0;

bsel = 0;

oen = 1;

#(T*2)



addressA = 5'b00000;

addressB = 5'b00010;

dataIn = 32'h23; 

opsel = 2'b01;

outsel =2'b00;

asel = 0;

bsel = 0;

oen = 1;



#(T*2)



addressA = 5'b00000;

addressB = 5'b10100;

dataIn = 32'h37;   

opsel = 2'b01;

outsel =2'b00;

asel = 0;

bsel = 0;

oen = 1;

#(T*2)



addressA = 5'd0;

addressB = 5'd1;

dataIn = 32'd0;

opsel = 2'b00;

outsel =2'b01;

asel = 1;

bsel = 1;

oen = 1;


#(T*2)

#(T*2)


addressA = 5'd1;

addressB = 5'd2;

dataIn = 32'd0;

opsel = 2'b00;

outsel =2'b01;

asel = 1;

bsel = 1;

oen = 1;

#(T*2)


addressA = 5'd2;

addressB = 5'd20;

dataIn = 32'd0;

opsel = 2'b01;

outsel =2'b01;

asel = 1;

bsel = 1;

oen = 1;

#(T*2)


addressA = 5'd1;

addressB = 5'd1;

dataIn = 32'd0;

opsel = 2'b01;

outsel =2'b00;

asel = 1;

bsel = 0;

oen = 1;

#(T*2)


addressA = 5'd2;

addressB = 5'd2;

dataIn = 32'd0;

opsel = 2'b01;

outsel =2'b00;

asel = 1;

bsel = 0;

oen = 1;

#(T*2)


addressA = 5'd20;

addressB = 5'd20;

dataIn = 32'd0;

opsel = 2'b01;

outsel =2'b00;

asel = 1;

bsel = 0;

oen = 1;

end
endmodule