data/full_repos/permissive/509809169/Verilog Language/More Verilog Features/Generate for loop_ 100bit BCD adder.v
1: b'%Error: Cannot find file containing module: Language/More\n        ... Looked in:\n             data/full_repos/permissive/509809169/Verilog/Language/More\n             data/full_repos/permissive/509809169/Verilog/Language/More.v\n             data/full_repos/permissive/509809169/Verilog/Language/More.sv\n             Language/More\n             Language/More.v\n             Language/More.sv\n             obj_dir/Language/More\n             obj_dir/Language/More.v\n             obj_dir/Language/More.sv\n%Error: Cannot find file containing module: Verilog\n%Error: Cannot find file containing module: Features,data/full_repos/permissive/509809169\n%Error: Cannot find file containing module: data/full_repos/permissive/509809169/Verilog\n%Error: Cannot find file containing module: Features/Generate\n%Error: Cannot find file containing module: for\n%Error: Cannot find file containing module: loop_\n%Error: Cannot find file containing module: 100bit\n%Error: Cannot find file containing module: BCD\n%Error: Cannot find file containing module: adder.v\n%Error: Exiting due to 10 error(s)\n'
module top_module( 
    input [399:0] a, b,
    input cin,
    output cout,
    output [399:0] sum );

    wire[99:0] cout_wires;
    genvar i;
    
    generate
        bcd_fadd(a[3:0], b[3:0], cin, cout_wires[0],sum[3:0]);
        for (i=4; i<400; i=i+4) begin: bcd_adder_instances
            bcd_fadd bcd_adder(a[i+3:i], b[i+3:i], cout_wires[i/4-1],cout_wires[i/4],sum[i+3:i]);
        end
    endgenerate
    
    assign cout = cout_wires[99];
    
endmodule
module top_module( 
    input [399:0] a, b,
    input cin,
    output cout,
    output [399:0] sum );


    wire[99:0] cout_wires;
    genvar i;
    
    generate
        bcd_fadd(a[3:0], b[3:0], cin, cout_wires[0],sum[3:0]);
        for (i=4; i<400; i=i+4) begin: bcd_adder_instances
            bcd_fadd bcd_adder(a[i+3:i], b[i+3:i], cout_wires[i/4-1],cout_wires[i/4],sum[i+3:i]);
        end
    endgenerate
    
    assign cout = cout_wires[99];
    
endmodule