data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/main.v
1: b"%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/main.v:71: syntax error, unexpected output, expecting ')' or ','\nmodule nor5 (input wire i0, i1, i2, i3, i4 output wire o);\n                                           ^~~~~~\n%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/main.v:73: syntax error, unexpected IDENTIFIER\n   or2 or2_0 (i0, i1, t0);\n   ^~~\n%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/main.v:387: syntax error, unexpected IDENTIFIER, expecting ',' or ';'\n pc_inc = load_ir\n ^~~~~~\n%Error: Cannot continue\n"
module control_logic (input wire clk, reset, input wire [15:0] cur_ins, output wire [2:0] rd_addr_a, rd_addr_b, wr_addr, output wire [1:0] op, output wire pc_inc, load_ir, wr_reg);



	wire t, alu_ins;	

	dfsl dfsl_d0 (clk, set, 1'b1, wr_reg, load_ir);
	dfrl dfrl_d0 (clk, reset, load_ir, 1'b1, t);
	nor5 nor5_n0 (cur_ins[15], cur_ins[14], cur_ins[13], cur_ins[12], cur_ins[11], alu_ins);
	and2 and2_a0 (t, alu_ins, wr_reg)
	pc_inc = load_ir

endmodule
module control_logic (input wire clk, reset, input wire [15:0] cur_ins, output wire [2:0] rd_addr_a, rd_addr_b, wr_addr, output wire [1:0] op, output wire pc_inc, load_ir, wr_reg);




	wire t, alu_ins;	

	dfsl dfsl_d0 (clk, set, 1'b1, wr_reg, load_ir);
	dfrl dfrl_d0 (clk, reset, load_ir, 1'b1, t);
	nor5 nor5_n0 (cur_ins[15], cur_ins[14], cur_ins[13], cur_ins[12], cur_ins[11], alu_ins);
	and2 and2_a0 (t, alu_ins, wr_reg)
	pc_inc = load_ir

endmodule