data/full_repos/permissive/479308240/d4breg.v
data/verilator_xmls/8c8bf341-beaa-4cfe-a970-a8a6d2c51be0.xml
module d4breg( 
            input wire [3:0] INna,
            input wire clk,
            output reg [3:0] Outna,
            input wire CE
            );

always@(posedge clk)
begin
            if(!CE) 
                      begin 
                      Outna=Outna;
                      end
            if(CE)
                      begin
                      Outna=INna;
                      end
end

endmodule
module d4breg( 
            input wire [3:0] INna,
            input wire clk,
            output reg [3:0] Outna,
            input wire CE
            );


always@(posedge clk)
begin
            if(!CE) 
                      begin 
                      Outna=Outna;
                      end
            if(CE)
                      begin
                      Outna=INna;
                      end
end

endmodule