data/full_repos/permissive/434840709/lab1/counter.v
data/verilator_xmls/d23676fa-75d4-44cf-aa1c-2c09a1ef060d.xml
module counter(
    input clk,
    input rst,
    output clk_bps
);    

    reg [13:0] count_first,count_second;

     
    always @(posedge clk or posedge rst) 
            if (rst)
                count_first <= 14'd0;
            else if (count_first==14'd10000)
                count_first <= 14'd0;
            else
                count_first <= count_first + 1'b1;

    always @(posedge clk or posedge rst)
            if (rst)
                count_second <= 14'd0; 
            else if (count_second==14'd10000)
                count_second <= 14'd0;
            else if (count_first==14'd10000) 
                count_second <= count_second + 1'b1;
            assign clk_bps = count_second == 14'd10000 ? 1'b1 : 1'b0;
endmodule
module counter(
    input clk,
    input rst,
    output clk_bps
);
    

    reg [13:0] count_first,count_second;

     
    always @(posedge clk or posedge rst) 
            if (rst)
                count_first <= 14'd0;
            else if (count_first==14'd10000)
                count_first <= 14'd0;
            else
                count_first <= count_first + 1'b1;

    always @(posedge clk or posedge rst)
            if (rst)
                count_second <= 14'd0; 
            else if (count_second==14'd10000)
                count_second <= 14'd0;
            else if (count_first==14'd10000) 
                count_second <= count_second + 1'b1;
            assign clk_bps = count_second == 14'd10000 ? 1'b1 : 1'b0;
endmodule