data/full_repos/permissive/450922687/Task 2/Control_Unit.v
1: b'%Error: Cannot find file containing module: 2,data/full_repos/permissive/450922687\n        ... Looked in:\n             data/full_repos/permissive/450922687/Task/2,data/full_repos/permissive/450922687\n             data/full_repos/permissive/450922687/Task/2,data/full_repos/permissive/450922687.v\n             data/full_repos/permissive/450922687/Task/2,data/full_repos/permissive/450922687.sv\n             2,data/full_repos/permissive/450922687\n             2,data/full_repos/permissive/450922687.v\n             2,data/full_repos/permissive/450922687.sv\n             obj_dir/2,data/full_repos/permissive/450922687\n             obj_dir/2,data/full_repos/permissive/450922687.v\n             obj_dir/2,data/full_repos/permissive/450922687.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/450922687/Task\n%Error: Cannot find file containing module: 2/Control_Unit.v\n%Error: Exiting due to 3 error(s)\n'
module Control_Unit(
  
  input [6:0] Opcode,
  input [2:0] funct3,
  output reg [1:0]ALUOp,
  output reg BranchEq,MemRead,MemtoReg,MemWrite,ALUSrc,RegWrite,BranchGt);
  
  always @(*)
    begin


      case(Opcode)
        7'b0110011:
          begin
            ALUOp = 2'b10;
            BranchEq = 1'b0;
            MemRead = 1'b0;
            MemtoReg = 1'b0;
            MemWrite = 1'b0;
            ALUSrc = 1'b0;
            RegWrite = 1'b1;
            BranchGt = 1'b0;
          end
        7'b0000011:
          begin
              ALUOp = 2'b00;
              BranchEq = 1'b0;
              MemRead = 1'b1;
              MemtoReg = 1'b1;
              MemWrite = 1'b0;
              ALUSrc = 1'b1;
              RegWrite = 1'b1;
              BranchGt = 1'b0;
            end
        7'b0100011:
          begin
              ALUOp = 2'b00;
              BranchEq = 1'b0;
              MemRead = 1'b0;
              MemtoReg = 1'bx;
              MemWrite = 1'b1;
              ALUSrc = 1'b1;
              RegWrite = 1'b0;
              BranchGt = 1'b0;
            end
        7'b1100011:
          begin
              ALUOp = 2'b01;
              BranchEq = 1'b1;
              MemRead = 1'b0;
              MemtoReg = 1'bx;
              MemWrite = 1'b0;
              ALUSrc = 1'b0;
              RegWrite = 1'b0;
              BranchGt = 1'b0;
            end
          7'b0010011:
            begin
              ALUOp = 2'b00;
              MemRead = 1'b0;
              MemtoReg = 1'b0;
              MemWrite = 1'b0;
              ALUSrc = 1'b1;
              RegWrite = 1'b1;
              if (funct3 == 3'b000)
                begin
                    BranchEq = 1'b1;
                    BranchGt = 1'b0;
                end
            else
                begin
                    BranchEq = 1'b0;
                    BranchGt = 1'b1;
                end
            end

      endcase
	end
endmodule
module Control_Unit(
  
  input [6:0] Opcode,
  input [2:0] funct3,
  output reg [1:0]ALUOp,
  output reg BranchEq,MemRead,MemtoReg,MemWrite,ALUSrc,RegWrite,BranchGt);

  
  always @(*)
    begin


      case(Opcode)
        7'b0110011:
          begin
            ALUOp = 2'b10;
            BranchEq = 1'b0;
            MemRead = 1'b0;
            MemtoReg = 1'b0;
            MemWrite = 1'b0;
            ALUSrc = 1'b0;
            RegWrite = 1'b1;
            BranchGt = 1'b0;
          end
        7'b0000011:
          begin
              ALUOp = 2'b00;
              BranchEq = 1'b0;
              MemRead = 1'b1;
              MemtoReg = 1'b1;
              MemWrite = 1'b0;
              ALUSrc = 1'b1;
              RegWrite = 1'b1;
              BranchGt = 1'b0;
            end
        7'b0100011:
          begin
              ALUOp = 2'b00;
              BranchEq = 1'b0;
              MemRead = 1'b0;
              MemtoReg = 1'bx;
              MemWrite = 1'b1;
              ALUSrc = 1'b1;
              RegWrite = 1'b0;
              BranchGt = 1'b0;
            end
        7'b1100011:
          begin
              ALUOp = 2'b01;
              BranchEq = 1'b1;
              MemRead = 1'b0;
              MemtoReg = 1'bx;
              MemWrite = 1'b0;
              ALUSrc = 1'b0;
              RegWrite = 1'b0;
              BranchGt = 1'b0;
            end
          7'b0010011:
            begin
              ALUOp = 2'b00;
              MemRead = 1'b0;
              MemtoReg = 1'b0;
              MemWrite = 1'b0;
              ALUSrc = 1'b1;
              RegWrite = 1'b1;
              if (funct3 == 3'b000)
                begin
                    BranchEq = 1'b1;
                    BranchGt = 1'b0;
                end
            else
                begin
                    BranchEq = 1'b0;
                    BranchGt = 1'b1;
                end
            end

      endcase
	end
endmodule