data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb.v:39: Cannot find include file: ccx2mb.h\n`include "ccx2mb.h" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/ccx2mb.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/ccx2mb.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/ccx2mb.h.sv\n             ccx2mb.h\n             ccx2mb.h.v\n             ccx2mb.h.sv\n             obj_dir/ccx2mb.h\n             obj_dir/ccx2mb.h.v\n             obj_dir/ccx2mb.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb.v:66: Define or directive not defined: \'`PCX_WIDTH\'\n    parameter PCX_GEAR_RATIO = (((`PCX_WIDTH+PCX_REQ_WIDTH)/`FSL_D_WIDTH)+1);\n                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb.v:66: Define or directive not defined: \'`FSL_D_WIDTH\'\n    parameter PCX_GEAR_RATIO = (((`PCX_WIDTH+PCX_REQ_WIDTH)/`FSL_D_WIDTH)+1);\n                                                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb.v:66: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    parameter PCX_GEAR_RATIO = (((`PCX_WIDTH+PCX_REQ_WIDTH)/`FSL_D_WIDTH)+1);\n                                                                        ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb.v:67: Define or directive not defined: \'`FSL_D_WIDTH\'\n    parameter PCX_FSL_EXTRA_BITS  = (`FSL_D_WIDTH * PCX_GEAR_RATIO) -\n                                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb.v:67: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n    parameter PCX_FSL_EXTRA_BITS  = (`FSL_D_WIDTH * PCX_GEAR_RATIO) -\n                                                  ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb.v:68: Define or directive not defined: \'`PCX_WIDTH\'\n        (`PCX_WIDTH+PCX_REQ_WIDTH+1);\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb.v:78: Define or directive not defined: \'`FSL_D_WIDTH\'\n    output [`FSL_D_WIDTH-1:0] pcx_fsl_m_data;\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb.v:87: Define or directive not defined: \'`PCX_WIDTH\'\n    input [`PCX_WIDTH-1:0] spc_pcx_data_pa;\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb.v:103: Define or directive not defined: \'`FSL_D_WIDTH\'\n    wire [`FSL_D_WIDTH-1:0] pcx_fsl_m_data;\n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb.v:211: Define or directive not defined: \'`PCX_WIDTH\'\n    wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry2_data;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb.v:215: Define or directive not defined: \'`PCX_WIDTH\'\n    assign    entry2_atom = entry2_data[`PCX_WIDTH];\n                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb.v:215: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign    entry2_atom = entry2_data[`PCX_WIDTH];\n                                                  ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb.v:217: Define or directive not defined: \'`PCX_WIDTH\'\n    wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry3_data;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb.v:221: Define or directive not defined: \'`PCX_WIDTH\'\n    wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry4_data;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb.v:225: Define or directive not defined: \'`PCX_WIDTH\'\n    wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry5_data;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb.v:229: Define or directive not defined: \'`PCX_WIDTH\'\n    wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry6_data;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb.v:233: Define or directive not defined: \'`PCX_WIDTH\'\n    wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry7_data;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb.v:237: Define or directive not defined: \'`PCX_WIDTH\'\n    wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry8_data;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb.v:241: Define or directive not defined: \'`PCX_WIDTH\'\n    wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry9_data;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb.v:245: Define or directive not defined: \'`PCX_WIDTH\'\n    wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry10_data;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb.v:250: Define or directive not defined: \'`FSL_D_WIDTH\'\n    reg [PCX_GEAR_RATIO*`FSL_D_WIDTH-1:0] entry1;\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb.v:465: Define or directive not defined: \'`PCX_WIDTH\'\n     .prev_data({`PCX_WIDTH+PCX_REQ_WIDTH+1{1\'b0}}),\n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb.v:508: Define or directive not defined: \'`FSL_D_WIDTH\'\n     entry1 <= {PCX_GEAR_RATIO*`FSL_D_WIDTH{1\'b0}};\n                               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb.v:512: Define or directive not defined: \'`FSL_D_WIDTH\'\n     entry1 <= entry1 << `FSL_D_WIDTH;\n                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb.v:512: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n     entry1 <= entry1 << `FSL_D_WIDTH;\n                                     ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb.v:540: Define or directive not defined: \'`FSL_D_WIDTH\'\n    assign pcx_fsl_m_data = entry1[PCX_GEAR_RATIO*`FSL_D_WIDTH-1:(PCX_GEAR_RATIO-1)*`FSL_D_WIDTH];\n                                                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb.v:540: Define or directive not defined: \'`FSL_D_WIDTH\'\n    assign pcx_fsl_m_data = entry1[PCX_GEAR_RATIO*`FSL_D_WIDTH-1:(PCX_GEAR_RATIO-1)*`FSL_D_WIDTH];\n                                                                                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx2mb.v:540: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    assign pcx_fsl_m_data = entry1[PCX_GEAR_RATIO*`FSL_D_WIDTH-1:(PCX_GEAR_RATIO-1)*`FSL_D_WIDTH];\n                                                                                                ^\n%Error: Exiting due to 29 error(s)\n'
module pcx2mb (

	pcx_spc_grant_px,
	pcx_fsl_m_control,
	pcx_fsl_m_data,
	pcx_fsl_m_write,


	rclk,
	reset_l,

	spc_pcx_data_pa,
	spc_pcx_atom_pq,
	spc_pcx_req_pq,

	fsl_pcx_m_full
	);

`ifdef PCX2MB_5_BIT_REQ
    parameter PCX_REQ_WIDTH = 5;
`else
    parameter PCX_REQ_WIDTH = 2;
`endif

    parameter PCX_GEAR_RATIO = (((`PCX_WIDTH+PCX_REQ_WIDTH)/`FSL_D_WIDTH)+1);
    parameter PCX_FSL_EXTRA_BITS  = (`FSL_D_WIDTH * PCX_GEAR_RATIO) -
				    (`PCX_WIDTH+PCX_REQ_WIDTH+1);





    output [4:0] pcx_spc_grant_px;


    output                    pcx_fsl_m_control;
    output [`FSL_D_WIDTH-1:0] pcx_fsl_m_data;
    output                    pcx_fsl_m_write;



    input rclk;
    input reset_l;


    input [`PCX_WIDTH-1:0] spc_pcx_data_pa;
    input                  spc_pcx_atom_pq;
    input [4:0]            spc_pcx_req_pq;


    input fsl_pcx_m_full;


    



    wire [4:0] pcx_spc_grant_px;


    wire                    pcx_fsl_m_control;
    wire [`FSL_D_WIDTH-1:0] pcx_fsl_m_data;
    wire                    pcx_fsl_m_write;


    wire any_req_pq;
    wire any_req_pa;
    reg  any_req_px;
    wire [4:0] req_dest_pq;
    reg  [4:0] req_dest_pa_raw;
    wire [4:0] req_dest_pa;
    reg  [4:0] req_dest_px;
    reg  req_atom_pa;
    reg  req_atom_px;
    wire [4:0] request_mask_pa;








    pcx2mb_link_ctr dest_ctr_0 (
	    .request_mask_pa(request_mask_pa[0]),

	    .rclk(rclk),
	    .reset_l(reset_l),

	    .pcx_req_pa(req_dest_pa[0]),
	    .pcx_req_px(req_dest_px[0]),
	    .pcx_atom_px(req_atom_px),

	    .pcx_grant_px(pcx_spc_grant_px[0])
	    );

    pcx2mb_link_ctr dest_ctr_1 (
	    .request_mask_pa(request_mask_pa[1]),

	    .rclk(rclk),
	    .reset_l(reset_l),

	    .pcx_req_pa(req_dest_pa[1]),
	    .pcx_req_px(req_dest_px[1]),
	    .pcx_atom_px(req_atom_px),

	    .pcx_grant_px(pcx_spc_grant_px[1])
	    );

    pcx2mb_link_ctr dest_ctr_2 (
	    .request_mask_pa(request_mask_pa[2]),

	    .rclk(rclk),
	    .reset_l(reset_l),

	    .pcx_req_pa(req_dest_pa[2]),
	    .pcx_req_px(req_dest_px[2]),
	    .pcx_atom_px(req_atom_px),

	    .pcx_grant_px(pcx_spc_grant_px[2])
	    );

    pcx2mb_link_ctr dest_ctr_3 (
	    .request_mask_pa(request_mask_pa[3]),

	    .rclk(rclk),
	    .reset_l(reset_l),

	    .pcx_req_pa(req_dest_pa[3]),
	    .pcx_req_px(req_dest_px[3]),
	    .pcx_atom_px(req_atom_px),

	    .pcx_grant_px(pcx_spc_grant_px[3])
	    );

    pcx2mb_link_ctr dest_ctr_4 (
	    .request_mask_pa(request_mask_pa[4]),

	    .rclk(rclk),
	    .reset_l(reset_l),

	    .pcx_req_pa(req_dest_pa[4]),
	    .pcx_req_px(req_dest_px[4]),
	    .pcx_atom_px(req_atom_px),

	    .pcx_grant_px(pcx_spc_grant_px[4])
	    );





    assign any_req_pq = | (spc_pcx_req_pq &
	    ~(request_mask_pa & ~pcx_spc_grant_px));
    assign req_dest_pq = spc_pcx_req_pq;
    assign req_dest_pa = req_dest_pa_raw & ~request_mask_pa;
    assign any_req_pa = | req_dest_pa;

    always @ (posedge rclk) begin
	req_dest_pa_raw <= req_dest_pq;
	req_atom_pa <= spc_pcx_atom_pq;

	any_req_px <= any_req_pa;
	req_dest_px <= req_dest_pa;
	req_atom_px <= req_atom_pa;
    end
    


    wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry2_data;
    wire       entry2_active;
    wire [4:0] entry2_dest;
    wire       entry2_atom;
    assign    entry2_atom = entry2_data[`PCX_WIDTH];

    wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry3_data;
    wire       entry3_active;
    wire [4:0] entry3_dest;

    wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry4_data;
    wire       entry4_active;
    wire [4:0] entry4_dest;

    wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry5_data;
    wire       entry5_active;
    wire [4:0] entry5_dest;

    wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry6_data;
    wire       entry6_active;
    wire [4:0] entry6_dest;

    wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry7_data;
    wire       entry7_active;
    wire [4:0] entry7_dest;

    wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry8_data;
    wire       entry8_active;
    wire [4:0] entry8_dest;

    wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry9_data;
    wire       entry9_active;
    wire [4:0] entry9_dest;

    wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry10_data;
    wire       entry10_active;
    wire [4:0] entry10_dest;


    reg [PCX_GEAR_RATIO*`FSL_D_WIDTH-1:0] entry1;
    wire      entry1_active;
    reg       entry1_active_d1;
    reg [4:0] entry1_dest;

    wire load_data;
    wire shift_data;




    pcx2mb_entry #(PCX_REQ_WIDTH) i_entry2 (
	    .rclk(rclk),
	    .reset_l(reset_l),
	    .any_req_pa(any_req_pa),
	    .spc_pcx_data_pa(spc_pcx_data_pa),
	    .req_dest_pa(req_dest_pa),
	    .req_atom_pa(req_atom_pa),
	    .any_req_px(any_req_px),
	    .req_dest_px(req_dest_px),
	    .req_atom_px(req_atom_px),
	    .load_data(load_data),

	    .prev_data(entry3_data),
	    .prev_active(entry3_active),
	    .prev_dest(entry3_dest),

	    .next_active(entry1_active & entry1_active_d1),


	    .e_data(entry2_data),
	    .e_active(entry2_active),
	    .e_dest(entry2_dest)
    );

    pcx2mb_entry #(PCX_REQ_WIDTH) i_entry3 (
	    .rclk(rclk),
	    .reset_l(reset_l),
	    .any_req_pa(any_req_pa),
	    .spc_pcx_data_pa(spc_pcx_data_pa),
	    .req_dest_pa(req_dest_pa),
	    .req_atom_pa(req_atom_pa),
	    .any_req_px(any_req_px),
	    .req_dest_px(req_dest_px),
	    .req_atom_px(req_atom_px),
	    .load_data(load_data),

	    .prev_data(entry4_data),
	    .prev_active(entry4_active),
	    .prev_dest(entry4_dest),

	    .next_active(entry2_active),


	    .e_data(entry3_data),
	    .e_active(entry3_active),
	    .e_dest(entry3_dest)
    );

    pcx2mb_entry #(PCX_REQ_WIDTH) i_entry4 (
	    .rclk(rclk),
	    .reset_l(reset_l),
	    .any_req_pa(any_req_pa),
	    .spc_pcx_data_pa(spc_pcx_data_pa),
	    .req_dest_pa(req_dest_pa),
	    .req_atom_pa(req_atom_pa),
	    .any_req_px(any_req_px),
	    .req_dest_px(req_dest_px),
	    .req_atom_px(req_atom_px),
	    .load_data(load_data),

	    .prev_data(entry5_data),
	    .prev_active(entry5_active),
	    .prev_dest(entry5_dest),

	    .next_active(entry3_active),


	    .e_data(entry4_data),
	    .e_active(entry4_active),
	    .e_dest(entry4_dest)
    );

    pcx2mb_entry #(PCX_REQ_WIDTH) i_entry5 (
	    .rclk(rclk),
	    .reset_l(reset_l),
	    .any_req_pa(any_req_pa),
	    .spc_pcx_data_pa(spc_pcx_data_pa),
	    .req_dest_pa(req_dest_pa),
	    .req_atom_pa(req_atom_pa),
	    .any_req_px(any_req_px),
	    .req_dest_px(req_dest_px),
	    .req_atom_px(req_atom_px),
	    .load_data(load_data),

	    .prev_data(entry6_data),
	    .prev_active(entry6_active),
	    .prev_dest(entry6_dest),

	    .next_active(entry4_active),


	    .e_data(entry5_data),
	    .e_active(entry5_active),
	    .e_dest(entry5_dest)
    );

    pcx2mb_entry #(PCX_REQ_WIDTH) i_entry6 (
	    .rclk(rclk),
	    .reset_l(reset_l),
	    .any_req_pa(any_req_pa),
	    .spc_pcx_data_pa(spc_pcx_data_pa),
	    .req_dest_pa(req_dest_pa),
	    .req_atom_pa(req_atom_pa),
	    .any_req_px(any_req_px),
	    .req_dest_px(req_dest_px),
	    .req_atom_px(req_atom_px),
	    .load_data(load_data),

	    .prev_data(entry7_data),
	    .prev_active(entry7_active),
	    .prev_dest(entry7_dest),

	    .next_active(entry5_active),


	    .e_data(entry6_data),
	    .e_active(entry6_active),
	    .e_dest(entry6_dest)
    );

    pcx2mb_entry #(PCX_REQ_WIDTH) i_entry7 (
	    .rclk(rclk),
	    .reset_l(reset_l),
	    .any_req_pa(any_req_pa),
	    .spc_pcx_data_pa(spc_pcx_data_pa),
	    .req_dest_pa(req_dest_pa),
	    .req_atom_pa(req_atom_pa),
	    .any_req_px(any_req_px),
	    .req_dest_px(req_dest_px),
	    .req_atom_px(req_atom_px),
	    .load_data(load_data),

	    .prev_data(entry8_data),
	    .prev_active(entry8_active),
	    .prev_dest(entry8_dest),

	    .next_active(entry6_active),


	    .e_data(entry7_data),
	    .e_active(entry7_active),
	    .e_dest(entry7_dest)
    );

    pcx2mb_entry #(PCX_REQ_WIDTH) i_entry8 (
	    .rclk(rclk),
	    .reset_l(reset_l),
	    .any_req_pa(any_req_pa),
	    .spc_pcx_data_pa(spc_pcx_data_pa),
	    .req_dest_pa(req_dest_pa),
	    .req_atom_pa(req_atom_pa),
	    .any_req_px(any_req_px),
	    .req_dest_px(req_dest_px),
	    .req_atom_px(req_atom_px),
	    .load_data(load_data),

	    .prev_data(entry9_data),
	    .prev_active(entry9_active),
	    .prev_dest(entry9_dest),

	    .next_active(entry7_active),


	    .e_data(entry8_data),
	    .e_active(entry8_active),
	    .e_dest(entry8_dest)
    );

    pcx2mb_entry #(PCX_REQ_WIDTH) i_entry9 (
	    .rclk(rclk),
	    .reset_l(reset_l),
	    .any_req_pa(any_req_pa),
	    .spc_pcx_data_pa(spc_pcx_data_pa),
	    .req_dest_pa(req_dest_pa),
	    .req_atom_pa(req_atom_pa),
	    .any_req_px(any_req_px),
	    .req_dest_px(req_dest_px),
	    .req_atom_px(req_atom_px),
	    .load_data(load_data),

	    .prev_data(entry10_data),
	    .prev_active(entry10_active),
	    .prev_dest(entry10_dest),

	    .next_active(entry8_active),


	    .e_data(entry9_data),
	    .e_active(entry9_active),
	    .e_dest(entry9_dest)
    );

    pcx2mb_entry #(PCX_REQ_WIDTH) i_entry10 (
	    .rclk(rclk),
	    .reset_l(reset_l),
	    .any_req_pa(any_req_pa),
	    .spc_pcx_data_pa(spc_pcx_data_pa),
	    .req_dest_pa(req_dest_pa),
	    .req_atom_pa(req_atom_pa),
	    .any_req_px(any_req_px),
	    .req_dest_px(req_dest_px),
	    .req_atom_px(req_atom_px),
	    .load_data(load_data),

	    .prev_data({`PCX_WIDTH+PCX_REQ_WIDTH+1{1'b0}}),
	    .prev_active(1'b0),
	    .prev_dest(5'b00000),

	    .next_active(entry9_active),


	    .e_data(entry10_data),
	    .e_active(entry10_active),
	    .e_dest(entry10_dest)
    );






    pcx2mb_sm shft_state (
	    .load_data(load_data),
	    .shift_data(shift_data),
	    .entry1_active(entry1_active),
	    .pcx_fsl_m_control(pcx_fsl_m_control),
	    .pcx_fsl_m_write(pcx_fsl_m_write),
	    .pcx_spc_grant_px(pcx_spc_grant_px),

	    .rclk(rclk),
	    .reset_l(reset_l),

	    .any_req_pq(any_req_pq),
	    .any_req_pa(any_req_pa),
	    .spc_pcx_atom_pq(spc_pcx_atom_pq),
	    .entry1_dest(entry1_dest),
	    .entry2_active(entry2_active),
	    .entry2_atom(entry2_atom),

	    .fsl_pcx_m_full(fsl_pcx_m_full)
	    );




    always @(posedge rclk) begin
	if (!reset_l) begin
	    entry1 <= {PCX_GEAR_RATIO*`FSL_D_WIDTH{1'b0}};
	    entry1_dest <= 5'b00000;
	end
	else if (shift_data) begin
	    entry1 <= entry1 << `FSL_D_WIDTH;
	    entry1_dest <= entry1_dest;
	end
	else if (load_data && entry2_active) begin
	    entry1 <= { {PCX_FSL_EXTRA_BITS{1'b0}},entry2_data};
	    entry1_dest <= entry2_dest;
	end
	else if (load_data) begin
`ifdef PCX2MB_5_BIT_REQ
	    entry1 <= { {PCX_FSL_EXTRA_BITS{1'b0}},
			req_dest_pa[4:0], req_atom_pa, spc_pcx_data_pa};
`else
	    entry1 <= { {PCX_FSL_EXTRA_BITS{1'b0}}, req_dest_pa[4],
			(|req_dest_pa[3:0]), req_atom_pa, spc_pcx_data_pa};
`endif
	    entry1_dest <= req_dest_pa;
	end
	else begin
	    entry1 <= entry1;
	    entry1_dest <= entry1_dest;
	end
    end

    always @(posedge rclk) begin
	entry1_active_d1 <= entry1_active;
    end


    assign pcx_fsl_m_data = entry1[PCX_GEAR_RATIO*`FSL_D_WIDTH-1:(PCX_GEAR_RATIO-1)*`FSL_D_WIDTH];

endmodule
module pcx2mb (

	pcx_spc_grant_px,
	pcx_fsl_m_control,
	pcx_fsl_m_data,
	pcx_fsl_m_write,


	rclk,
	reset_l,

	spc_pcx_data_pa,
	spc_pcx_atom_pq,
	spc_pcx_req_pq,

	fsl_pcx_m_full
	);


`ifdef PCX2MB_5_BIT_REQ
    parameter PCX_REQ_WIDTH = 5;
`else
    parameter PCX_REQ_WIDTH = 2;
`endif

    parameter PCX_GEAR_RATIO = (((`PCX_WIDTH+PCX_REQ_WIDTH)/`FSL_D_WIDTH)+1);
    parameter PCX_FSL_EXTRA_BITS  = (`FSL_D_WIDTH * PCX_GEAR_RATIO) -
				    (`PCX_WIDTH+PCX_REQ_WIDTH+1);





    output [4:0] pcx_spc_grant_px;


    output                    pcx_fsl_m_control;
    output [`FSL_D_WIDTH-1:0] pcx_fsl_m_data;
    output                    pcx_fsl_m_write;



    input rclk;
    input reset_l;


    input [`PCX_WIDTH-1:0] spc_pcx_data_pa;
    input                  spc_pcx_atom_pq;
    input [4:0]            spc_pcx_req_pq;


    input fsl_pcx_m_full;


    



    wire [4:0] pcx_spc_grant_px;


    wire                    pcx_fsl_m_control;
    wire [`FSL_D_WIDTH-1:0] pcx_fsl_m_data;
    wire                    pcx_fsl_m_write;


    wire any_req_pq;
    wire any_req_pa;
    reg  any_req_px;
    wire [4:0] req_dest_pq;
    reg  [4:0] req_dest_pa_raw;
    wire [4:0] req_dest_pa;
    reg  [4:0] req_dest_px;
    reg  req_atom_pa;
    reg  req_atom_px;
    wire [4:0] request_mask_pa;








    pcx2mb_link_ctr dest_ctr_0 (
	    .request_mask_pa(request_mask_pa[0]),

	    .rclk(rclk),
	    .reset_l(reset_l),

	    .pcx_req_pa(req_dest_pa[0]),
	    .pcx_req_px(req_dest_px[0]),
	    .pcx_atom_px(req_atom_px),

	    .pcx_grant_px(pcx_spc_grant_px[0])
	    );

    pcx2mb_link_ctr dest_ctr_1 (
	    .request_mask_pa(request_mask_pa[1]),

	    .rclk(rclk),
	    .reset_l(reset_l),

	    .pcx_req_pa(req_dest_pa[1]),
	    .pcx_req_px(req_dest_px[1]),
	    .pcx_atom_px(req_atom_px),

	    .pcx_grant_px(pcx_spc_grant_px[1])
	    );

    pcx2mb_link_ctr dest_ctr_2 (
	    .request_mask_pa(request_mask_pa[2]),

	    .rclk(rclk),
	    .reset_l(reset_l),

	    .pcx_req_pa(req_dest_pa[2]),
	    .pcx_req_px(req_dest_px[2]),
	    .pcx_atom_px(req_atom_px),

	    .pcx_grant_px(pcx_spc_grant_px[2])
	    );

    pcx2mb_link_ctr dest_ctr_3 (
	    .request_mask_pa(request_mask_pa[3]),

	    .rclk(rclk),
	    .reset_l(reset_l),

	    .pcx_req_pa(req_dest_pa[3]),
	    .pcx_req_px(req_dest_px[3]),
	    .pcx_atom_px(req_atom_px),

	    .pcx_grant_px(pcx_spc_grant_px[3])
	    );

    pcx2mb_link_ctr dest_ctr_4 (
	    .request_mask_pa(request_mask_pa[4]),

	    .rclk(rclk),
	    .reset_l(reset_l),

	    .pcx_req_pa(req_dest_pa[4]),
	    .pcx_req_px(req_dest_px[4]),
	    .pcx_atom_px(req_atom_px),

	    .pcx_grant_px(pcx_spc_grant_px[4])
	    );





    assign any_req_pq = | (spc_pcx_req_pq &
	    ~(request_mask_pa & ~pcx_spc_grant_px));
    assign req_dest_pq = spc_pcx_req_pq;
    assign req_dest_pa = req_dest_pa_raw & ~request_mask_pa;
    assign any_req_pa = | req_dest_pa;

    always @ (posedge rclk) begin
	req_dest_pa_raw <= req_dest_pq;
	req_atom_pa <= spc_pcx_atom_pq;

	any_req_px <= any_req_pa;
	req_dest_px <= req_dest_pa;
	req_atom_px <= req_atom_pa;
    end
    


    wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry2_data;
    wire       entry2_active;
    wire [4:0] entry2_dest;
    wire       entry2_atom;
    assign    entry2_atom = entry2_data[`PCX_WIDTH];

    wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry3_data;
    wire       entry3_active;
    wire [4:0] entry3_dest;

    wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry4_data;
    wire       entry4_active;
    wire [4:0] entry4_dest;

    wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry5_data;
    wire       entry5_active;
    wire [4:0] entry5_dest;

    wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry6_data;
    wire       entry6_active;
    wire [4:0] entry6_dest;

    wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry7_data;
    wire       entry7_active;
    wire [4:0] entry7_dest;

    wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry8_data;
    wire       entry8_active;
    wire [4:0] entry8_dest;

    wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry9_data;
    wire       entry9_active;
    wire [4:0] entry9_dest;

    wire [`PCX_WIDTH+PCX_REQ_WIDTH:0] entry10_data;
    wire       entry10_active;
    wire [4:0] entry10_dest;


    reg [PCX_GEAR_RATIO*`FSL_D_WIDTH-1:0] entry1;
    wire      entry1_active;
    reg       entry1_active_d1;
    reg [4:0] entry1_dest;

    wire load_data;
    wire shift_data;




    pcx2mb_entry #(PCX_REQ_WIDTH) i_entry2 (
	    .rclk(rclk),
	    .reset_l(reset_l),
	    .any_req_pa(any_req_pa),
	    .spc_pcx_data_pa(spc_pcx_data_pa),
	    .req_dest_pa(req_dest_pa),
	    .req_atom_pa(req_atom_pa),
	    .any_req_px(any_req_px),
	    .req_dest_px(req_dest_px),
	    .req_atom_px(req_atom_px),
	    .load_data(load_data),

	    .prev_data(entry3_data),
	    .prev_active(entry3_active),
	    .prev_dest(entry3_dest),

	    .next_active(entry1_active & entry1_active_d1),


	    .e_data(entry2_data),
	    .e_active(entry2_active),
	    .e_dest(entry2_dest)
    );

    pcx2mb_entry #(PCX_REQ_WIDTH) i_entry3 (
	    .rclk(rclk),
	    .reset_l(reset_l),
	    .any_req_pa(any_req_pa),
	    .spc_pcx_data_pa(spc_pcx_data_pa),
	    .req_dest_pa(req_dest_pa),
	    .req_atom_pa(req_atom_pa),
	    .any_req_px(any_req_px),
	    .req_dest_px(req_dest_px),
	    .req_atom_px(req_atom_px),
	    .load_data(load_data),

	    .prev_data(entry4_data),
	    .prev_active(entry4_active),
	    .prev_dest(entry4_dest),

	    .next_active(entry2_active),


	    .e_data(entry3_data),
	    .e_active(entry3_active),
	    .e_dest(entry3_dest)
    );

    pcx2mb_entry #(PCX_REQ_WIDTH) i_entry4 (
	    .rclk(rclk),
	    .reset_l(reset_l),
	    .any_req_pa(any_req_pa),
	    .spc_pcx_data_pa(spc_pcx_data_pa),
	    .req_dest_pa(req_dest_pa),
	    .req_atom_pa(req_atom_pa),
	    .any_req_px(any_req_px),
	    .req_dest_px(req_dest_px),
	    .req_atom_px(req_atom_px),
	    .load_data(load_data),

	    .prev_data(entry5_data),
	    .prev_active(entry5_active),
	    .prev_dest(entry5_dest),

	    .next_active(entry3_active),


	    .e_data(entry4_data),
	    .e_active(entry4_active),
	    .e_dest(entry4_dest)
    );

    pcx2mb_entry #(PCX_REQ_WIDTH) i_entry5 (
	    .rclk(rclk),
	    .reset_l(reset_l),
	    .any_req_pa(any_req_pa),
	    .spc_pcx_data_pa(spc_pcx_data_pa),
	    .req_dest_pa(req_dest_pa),
	    .req_atom_pa(req_atom_pa),
	    .any_req_px(any_req_px),
	    .req_dest_px(req_dest_px),
	    .req_atom_px(req_atom_px),
	    .load_data(load_data),

	    .prev_data(entry6_data),
	    .prev_active(entry6_active),
	    .prev_dest(entry6_dest),

	    .next_active(entry4_active),


	    .e_data(entry5_data),
	    .e_active(entry5_active),
	    .e_dest(entry5_dest)
    );

    pcx2mb_entry #(PCX_REQ_WIDTH) i_entry6 (
	    .rclk(rclk),
	    .reset_l(reset_l),
	    .any_req_pa(any_req_pa),
	    .spc_pcx_data_pa(spc_pcx_data_pa),
	    .req_dest_pa(req_dest_pa),
	    .req_atom_pa(req_atom_pa),
	    .any_req_px(any_req_px),
	    .req_dest_px(req_dest_px),
	    .req_atom_px(req_atom_px),
	    .load_data(load_data),

	    .prev_data(entry7_data),
	    .prev_active(entry7_active),
	    .prev_dest(entry7_dest),

	    .next_active(entry5_active),


	    .e_data(entry6_data),
	    .e_active(entry6_active),
	    .e_dest(entry6_dest)
    );

    pcx2mb_entry #(PCX_REQ_WIDTH) i_entry7 (
	    .rclk(rclk),
	    .reset_l(reset_l),
	    .any_req_pa(any_req_pa),
	    .spc_pcx_data_pa(spc_pcx_data_pa),
	    .req_dest_pa(req_dest_pa),
	    .req_atom_pa(req_atom_pa),
	    .any_req_px(any_req_px),
	    .req_dest_px(req_dest_px),
	    .req_atom_px(req_atom_px),
	    .load_data(load_data),

	    .prev_data(entry8_data),
	    .prev_active(entry8_active),
	    .prev_dest(entry8_dest),

	    .next_active(entry6_active),


	    .e_data(entry7_data),
	    .e_active(entry7_active),
	    .e_dest(entry7_dest)
    );

    pcx2mb_entry #(PCX_REQ_WIDTH) i_entry8 (
	    .rclk(rclk),
	    .reset_l(reset_l),
	    .any_req_pa(any_req_pa),
	    .spc_pcx_data_pa(spc_pcx_data_pa),
	    .req_dest_pa(req_dest_pa),
	    .req_atom_pa(req_atom_pa),
	    .any_req_px(any_req_px),
	    .req_dest_px(req_dest_px),
	    .req_atom_px(req_atom_px),
	    .load_data(load_data),

	    .prev_data(entry9_data),
	    .prev_active(entry9_active),
	    .prev_dest(entry9_dest),

	    .next_active(entry7_active),


	    .e_data(entry8_data),
	    .e_active(entry8_active),
	    .e_dest(entry8_dest)
    );

    pcx2mb_entry #(PCX_REQ_WIDTH) i_entry9 (
	    .rclk(rclk),
	    .reset_l(reset_l),
	    .any_req_pa(any_req_pa),
	    .spc_pcx_data_pa(spc_pcx_data_pa),
	    .req_dest_pa(req_dest_pa),
	    .req_atom_pa(req_atom_pa),
	    .any_req_px(any_req_px),
	    .req_dest_px(req_dest_px),
	    .req_atom_px(req_atom_px),
	    .load_data(load_data),

	    .prev_data(entry10_data),
	    .prev_active(entry10_active),
	    .prev_dest(entry10_dest),

	    .next_active(entry8_active),


	    .e_data(entry9_data),
	    .e_active(entry9_active),
	    .e_dest(entry9_dest)
    );

    pcx2mb_entry #(PCX_REQ_WIDTH) i_entry10 (
	    .rclk(rclk),
	    .reset_l(reset_l),
	    .any_req_pa(any_req_pa),
	    .spc_pcx_data_pa(spc_pcx_data_pa),
	    .req_dest_pa(req_dest_pa),
	    .req_atom_pa(req_atom_pa),
	    .any_req_px(any_req_px),
	    .req_dest_px(req_dest_px),
	    .req_atom_px(req_atom_px),
	    .load_data(load_data),

	    .prev_data({`PCX_WIDTH+PCX_REQ_WIDTH+1{1'b0}}),
	    .prev_active(1'b0),
	    .prev_dest(5'b00000),

	    .next_active(entry9_active),


	    .e_data(entry10_data),
	    .e_active(entry10_active),
	    .e_dest(entry10_dest)
    );






    pcx2mb_sm shft_state (
	    .load_data(load_data),
	    .shift_data(shift_data),
	    .entry1_active(entry1_active),
	    .pcx_fsl_m_control(pcx_fsl_m_control),
	    .pcx_fsl_m_write(pcx_fsl_m_write),
	    .pcx_spc_grant_px(pcx_spc_grant_px),

	    .rclk(rclk),
	    .reset_l(reset_l),

	    .any_req_pq(any_req_pq),
	    .any_req_pa(any_req_pa),
	    .spc_pcx_atom_pq(spc_pcx_atom_pq),
	    .entry1_dest(entry1_dest),
	    .entry2_active(entry2_active),
	    .entry2_atom(entry2_atom),

	    .fsl_pcx_m_full(fsl_pcx_m_full)
	    );




    always @(posedge rclk) begin
	if (!reset_l) begin
	    entry1 <= {PCX_GEAR_RATIO*`FSL_D_WIDTH{1'b0}};
	    entry1_dest <= 5'b00000;
	end
	else if (shift_data) begin
	    entry1 <= entry1 << `FSL_D_WIDTH;
	    entry1_dest <= entry1_dest;
	end
	else if (load_data && entry2_active) begin
	    entry1 <= { {PCX_FSL_EXTRA_BITS{1'b0}},entry2_data};
	    entry1_dest <= entry2_dest;
	end
	else if (load_data) begin
`ifdef PCX2MB_5_BIT_REQ
	    entry1 <= { {PCX_FSL_EXTRA_BITS{1'b0}},
			req_dest_pa[4:0], req_atom_pa, spc_pcx_data_pa};
`else
	    entry1 <= { {PCX_FSL_EXTRA_BITS{1'b0}}, req_dest_pa[4],
			(|req_dest_pa[3:0]), req_atom_pa, spc_pcx_data_pa};
`endif
	    entry1_dest <= req_dest_pa;
	end
	else begin
	    entry1 <= entry1;
	    entry1_dest <= entry1_dest;
	end
    end

    always @(posedge rclk) begin
	entry1_active_d1 <= entry1_active;
    end


    assign pcx_fsl_m_data = entry1[PCX_GEAR_RATIO*`FSL_D_WIDTH-1:(PCX_GEAR_RATIO-1)*`FSL_D_WIDTH];

endmodule