data/full_repos/permissive/433984388/nios_monitor/source/pwm_gen.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/433984388/nios_monitor/source/pwm_gen.sv:23: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'i_DUTY\' generates 16 bits.\n                                                                                      : ... In instance pwm_gen\n    duty_cycle  <= i_DUTY;\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module pwm_gen  #(parameter MODULO = 10000)
(
 input  logic       CLK,
 input  logic       RST,
 input  logic       i_PWM_TIC,
 input  logic[15:0] i_MIN_DUTY,
 input  logic[15:0] i_MAX_DUTY,
 input  logic[15:0] i_DUTY,
 input  logic       i_START,
 output logic       o_PWM

); 





logic [31:0] count = 0; 
logic [31:0] duty_cycle = 0; 

always_ff@(posedge CLK) begin 
if (RST || i_START) begin
    duty_cycle  <= i_DUTY;
    count       <= 0; 
	o_PWM       <= 1'b0; 
	end 
else if ( duty_cycle == 0 ) begin 
    o_PWM <= 1'b0; 
	 end 
else if ( duty_cycle == MODULO) begin 
    o_PWM <= 1'b1;
	 end 
else if ( duty_cycle < i_MIN_DUTY) begin 
	o_PWM <= 1'b0;
	end 
else if (  count < duty_cycle ) begin 
        o_PWM <= 1'b1; 
		if (i_PWM_TIC)
	    count <= count + 1;  
		end 
else begin 
		o_PWM <= 1'b0; 
	end
end  

endmodule
module pwm_gen  #(parameter MODULO = 10000)
(
 input  logic       CLK,
 input  logic       RST,
 input  logic       i_PWM_TIC,
 input  logic[15:0] i_MIN_DUTY,
 input  logic[15:0] i_MAX_DUTY,
 input  logic[15:0] i_DUTY,
 input  logic       i_START,
 output logic       o_PWM

);
 





logic [31:0] count = 0; 
logic [31:0] duty_cycle = 0; 

always_ff@(posedge CLK) begin 
if (RST || i_START) begin
    duty_cycle  <= i_DUTY;
    count       <= 0; 
	o_PWM       <= 1'b0; 
	end 
else if ( duty_cycle == 0 ) begin 
    o_PWM <= 1'b0; 
	 end 
else if ( duty_cycle == MODULO) begin 
    o_PWM <= 1'b1;
	 end 
else if ( duty_cycle < i_MIN_DUTY) begin 
	o_PWM <= 1'b0;
	end 
else if (  count < duty_cycle ) begin 
        o_PWM <= 1'b1; 
		if (i_PWM_TIC)
	    count <= count + 1;  
		end 
else begin 
		o_PWM <= 1'b0; 
	end
end  

endmodule