data/full_repos/permissive/43856783/j1_soc/hdl/multiplier/mult_32/mult_32.v
1: b"%Error: data/full_repos/permissive/43856783/j1_soc/hdl/multiplier/mult_32/mult_32.v:20: Cannot find file containing module: 'rsr'\n  rsr rsr0 (.clk(clk), .in_B(B) , .shift(w_sh) , .load(w_reset) , .s_B(w_B));\n  ^~~\n        ... Looked in:\n             data/full_repos/permissive/43856783/j1_soc/hdl/multiplier/mult_32,data/full_repos/permissive/43856783/rsr\n             data/full_repos/permissive/43856783/j1_soc/hdl/multiplier/mult_32,data/full_repos/permissive/43856783/rsr.v\n             data/full_repos/permissive/43856783/j1_soc/hdl/multiplier/mult_32,data/full_repos/permissive/43856783/rsr.sv\n             rsr\n             rsr.v\n             rsr.sv\n             obj_dir/rsr\n             obj_dir/rsr.v\n             obj_dir/rsr.sv\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/multiplier/mult_32/mult_32.v:21: Cannot find file containing module: 'lsr'\n  lsr lsr0 (.clk(clk), .in_A(A) , .shift(w_sh) , .load(w_reset) , .s_A(w_A));\n  ^~~\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/multiplier/mult_32/mult_32.v:22: Cannot find file containing module: 'comp'\n  comp comp0(.B(w_B), .z(w_z));\n  ^~~~\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/multiplier/mult_32/mult_32.v:23: Cannot find file containing module: 'acc'\n  acc acc0 (.clk(clk), .A(w_A) , .add(w_add), .rst(w_reset), .pp(pp));\n  ^~~\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/multiplier/mult_32/mult_32.v:24: Cannot find file containing module: 'control_mult'\n  control_mult control0 (.clk(clk), .rst(rst) , .lsb_B(w_B[0]) , .init(init) , .z(w_z) , .done(done) , .sh(w_sh) , .reset(w_reset) , .add(w_add) );\n  ^~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module mult_32(clk , rst , init , A , B , pp , done);
  
  input rst;
  input clk;
  input init;
  input [15:0]A;
  input [15:0]B;
  output [31:0]pp;
  output done;

  wire w_sh;
  wire w_reset;
  wire w_add;
  wire w_z;
  
  wire [31:0]w_A;
  wire [15:0] w_B;
  
 
  rsr rsr0 (.clk(clk), .in_B(B) , .shift(w_sh) , .load(w_reset) , .s_B(w_B));
  lsr lsr0 (.clk(clk), .in_A(A) , .shift(w_sh) , .load(w_reset) , .s_A(w_A));
  comp comp0(.B(w_B), .z(w_z));
  acc acc0 (.clk(clk), .A(w_A) , .add(w_add), .rst(w_reset), .pp(pp));
  control_mult control0 (.clk(clk), .rst(rst) , .lsb_B(w_B[0]) , .init(init) , .z(w_z) , .done(done) , .sh(w_sh) , .reset(w_reset) , .add(w_add) );
  
  
  

endmodule
module mult_32(clk , rst , init , A , B , pp , done);

  
  input rst;
  input clk;
  input init;
  input [15:0]A;
  input [15:0]B;
  output [31:0]pp;
  output done;

  wire w_sh;
  wire w_reset;
  wire w_add;
  wire w_z;
  
  wire [31:0]w_A;
  wire [15:0] w_B;
  
 
  rsr rsr0 (.clk(clk), .in_B(B) , .shift(w_sh) , .load(w_reset) , .s_B(w_B));
  lsr lsr0 (.clk(clk), .in_A(A) , .shift(w_sh) , .load(w_reset) , .s_A(w_A));
  comp comp0(.B(w_B), .z(w_z));
  acc acc0 (.clk(clk), .A(w_A) , .add(w_add), .rst(w_reset), .pp(pp));
  control_mult control0 (.clk(clk), .rst(rst) , .lsb_B(w_B[0]) , .init(init) , .z(w_z) , .done(done) , .sh(w_sh) , .reset(w_reset) , .add(w_add) );
  
  
  

endmodule