data/full_repos/permissive/466009483/HDL/PROJECT_FILES/D_FLIP_FLOP.v
data/verilator_xmls/f61e1fb6-704a-43dd-99a9-8a2be2620740.xml
module D_FLIP_FLOP(
    input in,
    input rst_n,
    input clk_in,
    input load,
    output reg q_out
    );

always @ (posedge clk_in)
  begin
     if(~rst_n)
	    begin
    q_out<= 1'b0 ;
          end
      else if (load==1'b1)
        begin
    q_out<= in ;
     end
 end
 endmodule
module D_FLIP_FLOP(
    input in,
    input rst_n,
    input clk_in,
    input load,
    output reg q_out
    );


always @ (posedge clk_in)
  begin
     if(~rst_n)
	    begin
    q_out<= 1'b0 ;
          end
      else if (load==1'b1)
        begin
    q_out<= in ;
     end
 end
 endmodule