data/full_repos/permissive/523236004/vrased/hw-mod/hwmod.v
1: b'%Error: data/full_repos/permissive/523236004/vrased/hw-mod/hwmod.v:1: Cannot find include file: vrased.v\n`include "vrased.v"  \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/523236004/vrased/hw-mod,data/full_repos/permissive/523236004/vrased.v\n             data/full_repos/permissive/523236004/vrased/hw-mod,data/full_repos/permissive/523236004/vrased.v.v\n             data/full_repos/permissive/523236004/vrased/hw-mod,data/full_repos/permissive/523236004/vrased.v.sv\n             vrased.v\n             vrased.v.v\n             vrased.v.sv\n             obj_dir/vrased.v\n             obj_dir/vrased.v.v\n             obj_dir/vrased.v.sv\n%Error: data/full_repos/permissive/523236004/vrased/hw-mod/hwmod.v:2: Cannot find include file: casu.v\n`include "casu.v"  \n         ^~~~~~~~\n%Error: data/full_repos/permissive/523236004/vrased/hw-mod/hwmod.v:6: Cannot find include file: openMSP430_defines.v\n`include "openMSP430_defines.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module hwmod (
    clk,
    pc,

    data_en,
    data_wr,
    data_addr,

    dma_addr,
    dma_en,

    ER_min,
    ER_max,

    irq,
    
    reset
);




input           clk;
input   [15:0]  pc;
input           data_en;
input           data_wr;
input   [15:0]  data_addr;
input   [15:0]  dma_addr;
input           dma_en;
input   [15:0]  ER_min;
input   [15:0]  ER_max;
input           irq;

output          reset;




parameter SDATA_BASE = 16'h400;
parameter SDATA_SIZE = 16'hC00;

parameter SMEM_BASE = 16'hA000;
parameter SMEM_SIZE = 16'h4000;

parameter KMEM_BASE = 16'h6A00;
parameter KMEM_SIZE = 16'h0040;

parameter SCACHE_BASE  = 16'hFFDF;
parameter SCACHE_SIZE  = 16'h0021;

parameter EP_BASE = 16'h0140;
parameter EP_SIZE = 16'h0004;

parameter HMAC_BASE = 16'h03D0;
parameter HMAC_SIZE = 16'h0020;

parameter RESET_HANDLER = 16'h0000;




wire vrased_reset;

vrased #(
        .SMEM_BASE (SMEM_BASE),
        .SMEM_SIZE (SMEM_SIZE),
        .SDATA_BASE (SDATA_BASE),
        .SDATA_SIZE (SDATA_SIZE),
        .HMAC_BASE (HMAC_BASE),
        .HMAC_SIZE (HMAC_SIZE),
        .KMEM_BASE (KMEM_BASE),
        .KMEM_SIZE (KMEM_SIZE),
        .CTR_BASE  (EP_BASE),
        .CTR_SIZE  (EP_SIZE),
        .SCACHE_BASE  (SCACHE_BASE),
        .SCACHE_SIZE  (SCACHE_SIZE),
        .RESET_HANDLER (RESET_HANDLER)
) vrased_0 (
    .clk        (clk),
    .pc         (pc),
    .data_en    (data_en),
    .data_wr    (data_wr),
    .data_addr  (data_addr),
    .dma_addr   (dma_addr),
    .dma_en     (dma_en),
    .irq        (irq),
    
    .reset      (vrased_reset)
);



wire casu_reset;

casu #(
        .SMEM_BASE (SMEM_BASE),
        .SMEM_SIZE (SMEM_SIZE),
        .SCACHE_BASE (SCACHE_BASE),
        .SCACHE_SIZE (SCACHE_SIZE),
        .EP_BASE (EP_BASE),
        .EP_SIZE (EP_SIZE),
        .RESET_HANDLER (RESET_HANDLER)
) casu_0 (
    .clk        (clk),

    .pc         (pc),

    .data_wr    (data_wr),
    .data_addr  (data_addr),
    
    .dma_addr   (dma_addr),
    .dma_en     (dma_en),

    .ER_min     (ER_min),
    .ER_max     (ER_max),
    
    .reset      (casu_reset)

);

assign reset = vrased_reset | casu_reset;

endmodule
module hwmod (
    clk,
    pc,

    data_en,
    data_wr,
    data_addr,

    dma_addr,
    dma_en,

    ER_min,
    ER_max,

    irq,
    
    reset
);





input           clk;
input   [15:0]  pc;
input           data_en;
input           data_wr;
input   [15:0]  data_addr;
input   [15:0]  dma_addr;
input           dma_en;
input   [15:0]  ER_min;
input   [15:0]  ER_max;
input           irq;

output          reset;




parameter SDATA_BASE = 16'h400;
parameter SDATA_SIZE = 16'hC00;

parameter SMEM_BASE = 16'hA000;
parameter SMEM_SIZE = 16'h4000;

parameter KMEM_BASE = 16'h6A00;
parameter KMEM_SIZE = 16'h0040;

parameter SCACHE_BASE  = 16'hFFDF;
parameter SCACHE_SIZE  = 16'h0021;

parameter EP_BASE = 16'h0140;
parameter EP_SIZE = 16'h0004;

parameter HMAC_BASE = 16'h03D0;
parameter HMAC_SIZE = 16'h0020;

parameter RESET_HANDLER = 16'h0000;




wire vrased_reset;

vrased #(
        .SMEM_BASE (SMEM_BASE),
        .SMEM_SIZE (SMEM_SIZE),
        .SDATA_BASE (SDATA_BASE),
        .SDATA_SIZE (SDATA_SIZE),
        .HMAC_BASE (HMAC_BASE),
        .HMAC_SIZE (HMAC_SIZE),
        .KMEM_BASE (KMEM_BASE),
        .KMEM_SIZE (KMEM_SIZE),
        .CTR_BASE  (EP_BASE),
        .CTR_SIZE  (EP_SIZE),
        .SCACHE_BASE  (SCACHE_BASE),
        .SCACHE_SIZE  (SCACHE_SIZE),
        .RESET_HANDLER (RESET_HANDLER)
) vrased_0 (
    .clk        (clk),
    .pc         (pc),
    .data_en    (data_en),
    .data_wr    (data_wr),
    .data_addr  (data_addr),
    .dma_addr   (dma_addr),
    .dma_en     (dma_en),
    .irq        (irq),
    
    .reset      (vrased_reset)
);



wire casu_reset;

casu #(
        .SMEM_BASE (SMEM_BASE),
        .SMEM_SIZE (SMEM_SIZE),
        .SCACHE_BASE (SCACHE_BASE),
        .SCACHE_SIZE (SCACHE_SIZE),
        .EP_BASE (EP_BASE),
        .EP_SIZE (EP_SIZE),
        .RESET_HANDLER (RESET_HANDLER)
) casu_0 (
    .clk        (clk),

    .pc         (pc),

    .data_wr    (data_wr),
    .data_addr  (data_addr),
    
    .dma_addr   (dma_addr),
    .dma_en     (dma_en),

    .ER_min     (ER_min),
    .ER_max     (ER_max),
    
    .reset      (casu_reset)

);

assign reset = vrased_reset | casu_reset;

endmodule