data/full_repos/permissive/415103295/verilog/synth/fwvexrisc_rv32im_i4k_d4k_wb/wb_target_synth_stub.v
1: b'%Error: data/full_repos/permissive/415103295/verilog/synth/fwvexrisc_rv32im_i4k_d4k_wb/wb_target_synth_stub.v:4: Cannot find include file: wishbone_macros.svh\n`include "wishbone_macros.svh" \n         ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/415103295/verilog/synth/fwvexrisc_rv32im_i4k_d4k_wb,data/full_repos/permissive/415103295/wishbone_macros.svh\n             data/full_repos/permissive/415103295/verilog/synth/fwvexrisc_rv32im_i4k_d4k_wb,data/full_repos/permissive/415103295/wishbone_macros.svh.v\n             data/full_repos/permissive/415103295/verilog/synth/fwvexrisc_rv32im_i4k_d4k_wb,data/full_repos/permissive/415103295/wishbone_macros.svh.sv\n             wishbone_macros.svh\n             wishbone_macros.svh.v\n             wishbone_macros.svh.sv\n             obj_dir/wishbone_macros.svh\n             obj_dir/wishbone_macros.svh.v\n             obj_dir/wishbone_macros.svh.sv\n%Error: data/full_repos/permissive/415103295/verilog/synth/fwvexrisc_rv32im_i4k_d4k_wb/wb_target_synth_stub.v:17: Define or directive not defined: \'`WB_TARGET_PORT\'\n  `WB_TARGET_PORT(i_, ADDR_WIDTH, DATA_WIDTH)\n  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/415103295/verilog/synth/fwvexrisc_rv32im_i4k_d4k_wb/wb_target_synth_stub.v:17: syntax error, unexpected \'(\', expecting \'[\'\n  `WB_TARGET_PORT(i_, ADDR_WIDTH, DATA_WIDTH)\n                  ^~\n%Error: data/full_repos/permissive/415103295/verilog/synth/fwvexrisc_rv32im_i4k_d4k_wb/wb_target_synth_stub.v:23: syntax error, unexpected always\n always @(posedge clock or posedge reset) begin\n ^~~~~~\n%Error: Exiting due to 4 error(s)\n'
module wb_target_synth_stub #(
		parameter ADDR_WIDTH=32, 
		parameter DATA_WIDTH=32
		) (
		input			clock,
		input			reset,
		`WB_TARGET_PORT(i_, ADDR_WIDTH, DATA_WIDTH)
		);
	
	reg[DATA_WIDTH-1:0]		store;
	reg						ack_r;

	always @(posedge clock or posedge reset) begin
		if (reset) begin
			store <= {DATA_WIDTH{1'b0}};
			ack_r <= 1'b0;
		end else begin
			if (i_stb && i_cyc) begin
				if (i_we) begin
					store <= ((store << 2) ^ i_adr ^ i_dat_w);
				end else begin
					store <= ((store << 2) ^ i_adr);
				end
				ack_r <= 1'b1;
			end else begin
				ack_r <= 1'b0;
			end
		end
	end 
	
	assign i_dat_r = store;

endmodule
module wb_target_synth_stub #(
		parameter ADDR_WIDTH=32, 
		parameter DATA_WIDTH=32
		) (
		input			clock,
		input			reset,
		`WB_TARGET_PORT(i_, ADDR_WIDTH, DATA_WIDTH)
		);

	
	reg[DATA_WIDTH-1:0]		store;
	reg						ack_r;

	always @(posedge clock or posedge reset) begin
		if (reset) begin
			store <= {DATA_WIDTH{1'b0}};
			ack_r <= 1'b0;
		end else begin
			if (i_stb && i_cyc) begin
				if (i_we) begin
					store <= ((store << 2) ^ i_adr ^ i_dat_w);
				end else begin
					store <= ((store << 2) ^ i_adr);
				end
				ack_r <= 1'b1;
			end else begin
				ack_r <= 1'b0;
			end
		end
	end 
	
	assign i_dat_r = store;

endmodule