data/full_repos/permissive/43398611/execute.v
1: b'%Warning-WIDTH: data/full_repos/permissive/43398611/execute.v:47: Operator COND expects 16 bits on the Conditional True, but Conditional True\'s VARREF \'id_sign_ext_addr\' generates 7 bits.\n                                                                : ... In instance execute\nassign b = cu_alu_sel_b ? id_sign_ext_addr : id_register2_data;\n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/43398611/execute.v:55: Cannot find file containing module: \'alu\'\nalu i_alu(\n^~~\n        ... Looked in:\n             data/full_repos/permissive/43398611,data/full_repos/permissive/43398611/alu\n             data/full_repos/permissive/43398611,data/full_repos/permissive/43398611/alu.v\n             data/full_repos/permissive/43398611,data/full_repos/permissive/43398611/alu.sv\n             alu\n             alu.v\n             alu.sv\n             obj_dir/alu\n             obj_dir/alu.v\n             obj_dir/alu.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module execute(
    input         clk_n,
    input         rst_n,
    input [6:0]   id_next_addr,
    input [15:0]  id_register1_data,
    input [15:0]  id_register2_data,
    input [6:0]   id_sign_ext_addr,
    input [2:0]   id_dest_reg_addr,
    input [10:0]  cu_alu_opcode,
    input         cu_alu_sel_b,
    output [6:0]  ex_sign_ext_next_addr,
    output        ex_alu_z,
    output [15:0] ex_alu_result,
    output [15:0] ex_register2_data,
    output [2:0]  ex_reg_waddr
);

wire [15:0] b;







assign b = cu_alu_sel_b ? id_sign_ext_addr : id_register2_data;

assign ex_reg_waddr = id_dest_reg_addr;

assign ex_sign_ext_next_addr = id_next_addr + id_sign_ext_addr;
assign ex_register2_data = id_register2_data;


alu i_alu(
    .a(id_register1_data),
    .b(b),
    .opcode(cu_alu_opcode),
    .rst_n(rst_n),
    .clk_n(clk_n),
    .out(ex_alu_result),
    .z(ex_alu_z)
);

endmodule
module execute(
    input         clk_n,
    input         rst_n,
    input [6:0]   id_next_addr,
    input [15:0]  id_register1_data,
    input [15:0]  id_register2_data,
    input [6:0]   id_sign_ext_addr,
    input [2:0]   id_dest_reg_addr,
    input [10:0]  cu_alu_opcode,
    input         cu_alu_sel_b,
    output [6:0]  ex_sign_ext_next_addr,
    output        ex_alu_z,
    output [15:0] ex_alu_result,
    output [15:0] ex_register2_data,
    output [2:0]  ex_reg_waddr
);


wire [15:0] b;







assign b = cu_alu_sel_b ? id_sign_ext_addr : id_register2_data;

assign ex_reg_waddr = id_dest_reg_addr;

assign ex_sign_ext_next_addr = id_next_addr + id_sign_ext_addr;
assign ex_register2_data = id_register2_data;


alu i_alu(
    .a(id_register1_data),
    .b(b),
    .opcode(cu_alu_opcode),
    .rst_n(rst_n),
    .clk_n(clk_n),
    .out(ex_alu_result),
    .z(ex_alu_z)
);

endmodule