data/full_repos/permissive/417288846/List_3/Task_2/div_3_sync.v
data/verilator_xmls/a7032394-579c-4324-95c0-ed3332099027.xml
module div_3(input [4:0] num, input clk, en, rst, output divisable);
    reg [4:0] segment;
    wire [4:0] reminder;

    rem_3 rem1(.num(segment + num), .result(reminder));
    always @(posedge clk or posedge rst)
    begin
        segment <= rst == 1 ? 0 :
                   en  == 1 ? reminder :
                   segment;
    end

    assign divisable = (segment == 0);
endmodule
module div_3(input [4:0] num, input clk, en, rst, output divisable);

    reg [4:0] segment;
    wire [4:0] reminder;

    rem_3 rem1(.num(segment + num), .result(reminder));
    always @(posedge clk or posedge rst)
    begin
        segment <= rst == 1 ? 0 :
                   en  == 1 ? reminder :
                   segment;
    end

    assign divisable = (segment == 0);
endmodule