data/full_repos/permissive/486598419/6.3/display7_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/486598419/6.3/display7_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n      #40 iData=4\'b0001;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.3/display7_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n      #40 iData=4\'b0010;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.3/display7_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n      #40 iData=4\'b0011;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.3/display7_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n      #40 iData=4\'b0100;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.3/display7_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n      #40 iData=4\'b0101;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.3/display7_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n      #40 iData=4\'b0110;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.3/display7_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n      #40 iData=4\'b0111;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.3/display7_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n      #40 iData=4\'b1000;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.3/display7_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n      #40 iData=4\'b1001;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.3/display7_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n      #40 iData=4\'b0000;\n      ^\n%Error: data/full_repos/permissive/486598419/6.3/display7_tb.v:40: Cannot find file containing module: \'display7\'\n   display7\n   ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/486598419/6.3,data/full_repos/permissive/486598419/display7\n             data/full_repos/permissive/486598419/6.3,data/full_repos/permissive/486598419/display7.v\n             data/full_repos/permissive/486598419/6.3,data/full_repos/permissive/486598419/display7.sv\n             display7\n             display7.v\n             display7.sv\n             obj_dir/display7\n             obj_dir/display7.v\n             obj_dir/display7.sv\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module display7_tb();
   reg [3:0] iData;
   wire [6:0] oData;
   initial
   begin
      iData=4'b0000;
      #40 iData=4'b0001;
      #40 iData=4'b0010;
      #40 iData=4'b0011;
      #40 iData=4'b0100;
      #40 iData=4'b0101;
      #40 iData=4'b0110;
      #40 iData=4'b0111;
      #40 iData=4'b1000;
      #40 iData=4'b1001;
      #40 iData=4'b0000;
   end
   display7
   display7_inst(
      .iData(iData),
      .oData(oData)
      );
endmodule
module display7_tb();

   reg [3:0] iData;
   wire [6:0] oData;
   initial
   begin
      iData=4'b0000;
      #40 iData=4'b0001;
      #40 iData=4'b0010;
      #40 iData=4'b0011;
      #40 iData=4'b0100;
      #40 iData=4'b0101;
      #40 iData=4'b0110;
      #40 iData=4'b0111;
      #40 iData=4'b1000;
      #40 iData=4'b1001;
      #40 iData=4'b0000;
   end
   display7
   display7_inst(
      .iData(iData),
      .oData(oData)
      );
endmodule