data/full_repos/permissive/519893543/verilog/rtl/biquad/bqmain.v
1: b"%Error: data/full_repos/permissive/519893543/verilog/rtl/biquad/bqmain.v:72: Cannot find file containing module: 'biquad'\nbiquad biquadi\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/519893543/verilog/rtl/biquad,data/full_repos/permissive/519893543/biquad\n             data/full_repos/permissive/519893543/verilog/rtl/biquad,data/full_repos/permissive/519893543/biquad.v\n             data/full_repos/permissive/519893543/verilog/rtl/biquad,data/full_repos/permissive/519893543/biquad.sv\n             biquad\n             biquad.v\n             biquad.sv\n             obj_dir/biquad\n             obj_dir/biquad.v\n             obj_dir/biquad.sv\n%Error: data/full_repos/permissive/519893543/verilog/rtl/biquad/bqmain.v:87: Cannot find file containing module: 'coefio'\ncoefio coefioi\n^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module bqmain #(
    parameter	DATAWIDTH = 12,
    parameter	COEFWIDTH = 16
)
	(
    `ifdef USE_POWER_PINS
		inout vccd1,
		inout vssd1,
    `endif 
	input wb_clk_i,
	input wb_rst_i,
	input wb_we_i,
	input wb_stb_i,
	output wb_ack_o,
	input	[31:0] wb_dat_i,
	output	[31:0] wb_dat_o,
	input	[31:0] wb_adr_i,
	input bq_clk_i,

	input nreset,
	input	[DATAWIDTH-1:0] x,
	output wire    [DATAWIDTH-1:0] y,
	input wb_cyc_i
	);


wire	[31:0]	a11;
wire	[31:0]	a12;
wire	[31:0]	b10;
wire	[31:0]	b11;
wire	[31:0]	b12;



biquad biquadi
	(
	.clk(bq_clk_i),
	.nreset(1'b1),
	.x(x),
	.valid(1'b1),
	.a11(a11[COEFWIDTH-1:0]),
	.a12(a12[COEFWIDTH-1:0]),
	.b10(b10[COEFWIDTH-1:0]),
	.b11(b11[COEFWIDTH-1:0]),
	.b12(b12[COEFWIDTH-1:0]),
	.yout(y)
	);


coefio coefioi
	(
	.clk_i(wb_clk_i),
	.rst_i(1'b0),
	.we_i(wb_we_i),	
	.stb_i(wb_stb_i),
	.cyc_i(wb_cyc_i),
	.ack_o(wb_ack_o),
	.dat_i(wb_dat_i[31:0]),
	.dat_o(wb_dat_o[31:0]),
	.adr_i(wb_adr_i[31:0]),
	.a11(a11),
	.a12(a12),
	.b10(b10),
	.b11(b11),
	.b12(b12),
	.x(x),
	.y(y)
	);

endmodule
module bqmain #(
    parameter	DATAWIDTH = 12,
    parameter	COEFWIDTH = 16
)
	(
    `ifdef USE_POWER_PINS
		inout vccd1,
		inout vssd1,
    `endif 
	input wb_clk_i,
	input wb_rst_i,
	input wb_we_i,
	input wb_stb_i,
	output wb_ack_o,
	input	[31:0] wb_dat_i,
	output	[31:0] wb_dat_o,
	input	[31:0] wb_adr_i,
	input bq_clk_i,

	input nreset,
	input	[DATAWIDTH-1:0] x,
	output wire    [DATAWIDTH-1:0] y,
	input wb_cyc_i
	);



wire	[31:0]	a11;
wire	[31:0]	a12;
wire	[31:0]	b10;
wire	[31:0]	b11;
wire	[31:0]	b12;



biquad biquadi
	(
	.clk(bq_clk_i),
	.nreset(1'b1),
	.x(x),
	.valid(1'b1),
	.a11(a11[COEFWIDTH-1:0]),
	.a12(a12[COEFWIDTH-1:0]),
	.b10(b10[COEFWIDTH-1:0]),
	.b11(b11[COEFWIDTH-1:0]),
	.b12(b12[COEFWIDTH-1:0]),
	.yout(y)
	);


coefio coefioi
	(
	.clk_i(wb_clk_i),
	.rst_i(1'b0),
	.we_i(wb_we_i),	
	.stb_i(wb_stb_i),
	.cyc_i(wb_cyc_i),
	.ack_o(wb_ack_o),
	.dat_i(wb_dat_i[31:0]),
	.dat_o(wb_dat_o[31:0]),
	.adr_i(wb_adr_i[31:0]),
	.a11(a11),
	.a12(a12),
	.b10(b10),
	.b11(b11),
	.b12(b12),
	.x(x),
	.y(y)
	);

endmodule