data/full_repos/permissive/508949345/verilog/r88_mc.v
1: b'%Error: data/full_repos/permissive/508949345/verilog/r88_mc.v:28: syntax error, unexpected edge, expecting TYPE-IDENTIFIER\nalways @ edge sysClock begin\n         ^~~~\n%Error: Cannot continue\n'
module r88_mc (
	input sysClock,
	output [15:0] extA,
	inout [7:0] extD,
	input readMem,
	input writeMem,
	inout [7:0] intD,
	input mc_use_regAddr,
	input mc_write_low,
	input mc_write_high,
	input [15:0] regAddr
);


assign extD = writeMem? intD : 8'Z;
assign intD = readMem? extD : 8'Z;


reg [15:0] r_extA;
assign extA = mc_use_regAddr? regAddr : r_extA;


always @ edge sysClock begin
	if mc_write_low r_extA[7:0] <= intD;
	else if mc_write_high r_extA[15:8] <= intD;
end

endmodule
module r88_mc (
	input sysClock,
	output [15:0] extA,
	inout [7:0] extD,
	input readMem,
	input writeMem,
	inout [7:0] intD,
	input mc_use_regAddr,
	input mc_write_low,
	input mc_write_high,
	input [15:0] regAddr
);



assign extD = writeMem? intD : 8'Z;
assign intD = readMem? extD : 8'Z;


reg [15:0] r_extA;
assign extA = mc_use_regAddr? regAddr : r_extA;


always @ edge sysClock begin
	if mc_write_low r_extA[7:0] <= intD;
	else if mc_write_high r_extA[15:8] <= intD;
end

endmodule