data/full_repos/permissive/43858668/final_verilog/src/clib/c_reverse.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/43858668/final_verilog/src/clib/c_reverse.v:39: Little bit endian vector: MSB < LSB of bit range: 0:31\n   input [0:width-1] data_in;\n         ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/43858668/final_verilog/src/clib/c_reverse.v:42: Little bit endian vector: MSB < LSB of bit range: 0:31\n   output [0:width-1] data_out;\n          ^\n%Error: Exiting due to 2 warning(s)\n'
module c_reverse
  (data_in, data_out);


   parameter width = 32;
   

   input [0:width-1] data_in;
   

   output [0:width-1] data_out;
   wire [0:width-1] data_out;
   
   generate   
      
      genvar 	   i;
      for(i = 0; i < width; i = i + 1)
	begin:connect
	   

	   assign data_out[i] = data_in[(width-1)-i];
	   
	end
      
   endgenerate
   
endmodule
module c_reverse
  (data_in, data_out);



   parameter width = 32;
   

   input [0:width-1] data_in;
   

   output [0:width-1] data_out;
   wire [0:width-1] data_out;
   
   generate   
      
      genvar 	   i;
      for(i = 0; i < width; i = i + 1)
	begin:connect
	   

	   assign data_out[i] = data_in[(width-1)-i];
	   
	end
      
   endgenerate
   
endmodule