data/full_repos/permissive/434837003/test/specify.v
1: b"%Error: data/full_repos/permissive/434837003/test/specify.v:28: Unsupported or unknown PLI call: $q\n        PATHPULSE$clr[2]$q = (0,4),\n                        ^~\n%Error: data/full_repos/permissive/434837003/test/specify.v:78: syntax error, unexpected '(', expecting IDENTIFIER\nposdff_udp (ffout, clock, data, preset, clear, notifier);\n            ^~~~~\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module ALU (o1, i1, i2, opcode);

input [7:0] i1, i2;
input [2:1] opcode;
output [7:0] o1;


specify

    if (opcode == 2'b00) (i1,i2 *> o1) = (25.0, 25.0);

    if (opcode == 2'b01) (i1 => o1) = (5.6, 8.0);

    if (opcode == 2'b10) (i2 => o1) = (5.6, 8.0);

    (opcode *> o1) = (6.1, 6.5);

    if (C1) (IN => OUT) = (1,1);
    ifnone (IN => OUT) = (2,2);

    if (opcode == 2'b00) (i1,i2 *> o1) = (25.0, 25.0);

    if (opcode == 2'b01) (i1 => o1) = (5.6, 8.0);

    if (opcode == 2'b10) (i2 => o1) = (5.6, 8.0);

    ifnone (i2 => o1) = (15.0, 15.0);
    (posedge CLK => (Q +: D)) = (1,1);
    ifnone (CLK => Q) = (2,2);
endspecify

endmodule
module ALU (o1, i1, i2, opcode);


input [7:0] i1, i2;
input [2:1] opcode;
output [7:0] o1;


specify

    if (opcode == 2'b00) (i1,i2 *> o1) = (25.0, 25.0);

    if (opcode == 2'b01) (i1 => o1) = (5.6, 8.0);

    if (opcode == 2'b10) (i2 => o1) = (5.6, 8.0);

    (opcode *> o1) = (6.1, 6.5);

    if (C1) (IN => OUT) = (1,1);
    ifnone (IN => OUT) = (2,2);

    if (opcode == 2'b00) (i1,i2 *> o1) = (25.0, 25.0);

    if (opcode == 2'b01) (i1 => o1) = (5.6, 8.0);

    if (opcode == 2'b10) (i2 => o1) = (5.6, 8.0);

    ifnone (i2 => o1) = (15.0, 15.0);
    (posedge CLK => (Q +: D)) = (1,1);
    ifnone (CLK => Q) = (2,2);
endspecify

endmodule