data/full_repos/permissive/453763315/regarray.v
data/verilator_xmls/e9ed7d9e-d346-48d3-a47c-3f30f8947308.xml
module regarray(clk, en, we, sela, selb, reada, readb, write);
  input clk, en, we;
  input reg [5:0] sela, selb;
  output reg [7:0] reada, readb;
  input reg [7:0] write;
  reg [4:0][7:0] arr;

  integer i;

  initial begin
    for (i = 0; i < 32; i = i + 1) begin
      arr[i] = 8'h00;
    end
  end

  always @ (posedge clk or negedge clk) begin
    if (en) begin
      if (we) begin
        arr[sela] <= write;
      end
         reada <= arr[sela];
         readb <= arr[selb];
          end
  		else begin
          readb <= 8'hzz;
          reada <= 8'hzz;
        end
       end
endmodule
module regarray(clk, en, we, sela, selb, reada, readb, write);

  input clk, en, we;
  input reg [5:0] sela, selb;
  output reg [7:0] reada, readb;
  input reg [7:0] write;
  reg [4:0][7:0] arr;

  integer i;

  initial begin
    for (i = 0; i < 32; i = i + 1) begin
      arr[i] = 8'h00;
    end
  end

  always @ (posedge clk or negedge clk) begin
    if (en) begin
      if (we) begin
        arr[sela] <= write;
      end
         reada <= arr[sela];
         readb <= arr[selb];
          end
  		else begin
          readb <= 8'hzz;
          reada <= 8'hzz;
        end
       end
endmodule