data/full_repos/permissive/407433468/2010-PRJ0_BASE_1/rtl/SC_DEBOUNCE1.v
data/verilator_xmls/67b79237-0e40-4c00-a82b-223ea39b87fe.xml
module  SC_DEBOUNCE1 
	(
	input 			SC_DEBOUNCE1_CLOCK_50, SC_DEBOUNCE1_RESET_InHigh, SC_DEBOUNCE1_button_In,
	output reg 	SC_DEBOUNCE1_button_Out
	);

	parameter N = 11 ;

	reg  [N-1 : 0]	q_reg;
	reg  [N-1 : 0]	q_next;
	reg DFF1, DFF2;
	wire q_add;
	wire q_reset;



	assign q_reset = (DFF1  ^ DFF2);
	assign  q_add = ~(q_reg[N-1]);
	

	always @ ( q_reset, q_add, q_reg)
		begin
			case( {q_reset , q_add})
				2'b00 :
						q_next <= q_reg;
				2'b01 :
						q_next <= q_reg + 1;
				default :
						q_next <= { N {1'b0} };
			endcase 	
		end
	

	always @ ( posedge SC_DEBOUNCE1_CLOCK_50 )
		begin
			if(SC_DEBOUNCE1_RESET_InHigh ==  1'b1)
				begin
					DFF1 <= 1'b0;
					DFF2 <= 1'b0;
					q_reg <= { N {1'b0} };
				end
			else
				begin
					DFF1 <= SC_DEBOUNCE1_button_In;
					DFF2 <= DFF1;
					q_reg <= q_next;
				end
		end
	

	always @ ( posedge SC_DEBOUNCE1_CLOCK_50 )
		begin
			if(q_reg[N-1] == 1'b1)
					SC_DEBOUNCE1_button_Out <= DFF2;
			else
					SC_DEBOUNCE1_button_Out <= SC_DEBOUNCE1_button_Out;
		end

	endmodule
module  SC_DEBOUNCE1 
	(
	input 			SC_DEBOUNCE1_CLOCK_50, SC_DEBOUNCE1_RESET_InHigh, SC_DEBOUNCE1_button_In,
	output reg 	SC_DEBOUNCE1_button_Out
	);


	parameter N = 11 ;

	reg  [N-1 : 0]	q_reg;
	reg  [N-1 : 0]	q_next;
	reg DFF1, DFF2;
	wire q_add;
	wire q_reset;



	assign q_reset = (DFF1  ^ DFF2);
	assign  q_add = ~(q_reg[N-1]);
	

	always @ ( q_reset, q_add, q_reg)
		begin
			case( {q_reset , q_add})
				2'b00 :
						q_next <= q_reg;
				2'b01 :
						q_next <= q_reg + 1;
				default :
						q_next <= { N {1'b0} };
			endcase 	
		end
	

	always @ ( posedge SC_DEBOUNCE1_CLOCK_50 )
		begin
			if(SC_DEBOUNCE1_RESET_InHigh ==  1'b1)
				begin
					DFF1 <= 1'b0;
					DFF2 <= 1'b0;
					q_reg <= { N {1'b0} };
				end
			else
				begin
					DFF1 <= SC_DEBOUNCE1_button_In;
					DFF2 <= DFF1;
					q_reg <= q_next;
				end
		end
	

	always @ ( posedge SC_DEBOUNCE1_CLOCK_50 )
		begin
			if(q_reg[N-1] == 1'b1)
					SC_DEBOUNCE1_button_Out <= DFF2;
			else
					SC_DEBOUNCE1_button_Out <= SC_DEBOUNCE1_button_Out;
		end

	endmodule