data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Vectors/Vectorgates.v
data/verilator_xmls/6187944f-adbb-447c-87dd-dd034a7af72c.xml
module top_module( 
    input [2:0] a,
    input [2:0] b,
    output [2:0] out_or_bitwise,
    output out_or_logical,
    output [5:0] out_not
);

    
endmodule
module top_module( 
    input [2:0] a,
    input [2:0] b,
    output [2:0] out_or_bitwise,
    output out_or_logical,
    output [5:0] out_not
);


    
endmodule