data/full_repos/permissive/42434302/ivltests/pr538.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr538.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #d set = 0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr538.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #d set = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr538.v:35: Unsupported: Ignoring delay on this delayed statement.\n      #0.1;\n      ^\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;
  reg set;
  parameter d = 1.55;
  reg fail;
  reg [7:0] ii;

  initial begin
    fail = 0;
    #d set = 0;

    if((ii < 15) || (ii > 16)) fail = 1;
    #d set = 1;

    if((ii < 31) || (ii > 32)) fail = 1;
  end

  initial begin

    for(ii = 0; ii < 50; ii = ii + 1) begin

      #0.1;
    end
    $display("\n\t\t**********************************************");
    if(fail) $display("\t\t********** timescale test FAILED *************");
    else     $display("\t\t********** timescale test PASSED *************");
    $display("\t\t**********************************************\n");
    $finish;
  end
endmodule
module test;

  reg set;
  parameter d = 1.55;
  reg fail;
  reg [7:0] ii;

  initial begin
    fail = 0;
    #d set = 0;

    if((ii < 15) || (ii > 16)) fail = 1;
    #d set = 1;

    if((ii < 31) || (ii > 32)) fail = 1;
  end

  initial begin

    for(ii = 0; ii < 50; ii = ii + 1) begin

      #0.1;
    end
    $display("\n\t\t**********************************************");
    if(fail) $display("\t\t********** timescale test FAILED *************");
    else     $display("\t\t********** timescale test PASSED *************");
    $display("\t\t**********************************************\n");
    $finish;
  end
endmodule