data/full_repos/permissive/521337848/Hardware/procesor/aluX.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/521337848/Hardware/procesor/aluX.v:111: Cell has missing pin: \'sreg3\'\ncollectsubreg csr(.bank(bank[1]),\n              ^~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/521337848/Hardware/procesor/aluX.v:111: Cell has missing pin: \'sreg4\'\ncollectsubreg csr(.bank(bank[1]),\n              ^~~\n%Error: Exiting due to 2 warning(s)\n'
module register(
	input[1:0] bank,
	
	input save,
	input clk,
	input rst,
	
	input[15:0] f_reg,
	
	output[15:0] s_reg
);

wire[15:0] s_reg1;
wire[15:0] s_reg2;
wire[15:0] s_reg3;
wire[15:0] s_reg4;


subreg sr1(.clk(clk),
			  .rst(rst),
			  .setBank(1'b0),
			  .bank(bank[0]),
			  
			  .save(save),
			  .f_reg(f_reg),

			  .s_reg1(s_reg1)
);

subreg sr2(.clk(clk),
			  .rst(rst),
			  .setBank(1'b1),
			  .bank(bank[0]),
	
			  .f_reg(f_reg),
				
			  .save(save),
			  .s_reg1(s_reg2)
);


collectsubreg csr(.bank(bank[1]),
	
						.sreg1(s_reg1),
						.sreg2(s_reg2),
						

						.sreg(s_reg)
);

endmodule
module register(
	input[1:0] bank,
	
	input save,
	input clk,
	input rst,
	
	input[15:0] f_reg,
	
	output[15:0] s_reg
);


wire[15:0] s_reg1;
wire[15:0] s_reg2;
wire[15:0] s_reg3;
wire[15:0] s_reg4;


subreg sr1(.clk(clk),
			  .rst(rst),
			  .setBank(1'b0),
			  .bank(bank[0]),
			  
			  .save(save),
			  .f_reg(f_reg),

			  .s_reg1(s_reg1)
);

subreg sr2(.clk(clk),
			  .rst(rst),
			  .setBank(1'b1),
			  .bank(bank[0]),
	
			  .f_reg(f_reg),
				
			  .save(save),
			  .s_reg1(s_reg2)
);


collectsubreg csr(.bank(bank[1]),
	
						.sreg1(s_reg1),
						.sreg2(s_reg2),
						

						.sreg(s_reg)
);

endmodule