data/full_repos/permissive/411838135/rv/synth/vsram.v
1: b'%Error: No top level module found\n%Error: Exiting due to 1 error(s)\n'
module tc2_combined(input [7:0]addra,
                input clka,
                input [79:0]dina,
                output [79:0]douta,
		input wea);

	reg 	[80-1:0]mem[0:255];


        reg [8-1:0]r_addra;
	always @(posedge clka)
		r_addra <= addra;
	always @(posedge clka)
	if (wea)
		mem[addra] <= dina;

	reg [80-1:0]outa;
	assign douta = outa;
	always @(*)
	if (clka)
		outa = mem[r_addra];


endmodule
module tc2_combined(input [7:0]addra,
                input clka,
                input [79:0]dina,
                output [79:0]douta,
		input wea);


	reg 	[80-1:0]mem[0:255];


        reg [8-1:0]r_addra;
	always @(posedge clka)
		r_addra <= addra;
	always @(posedge clka)
	if (wea)
		mem[addra] <= dina;

	reg [80-1:0]outa;
	assign douta = outa;
	always @(*)
	if (clka)
		outa = mem[r_addra];


endmodule