data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Shift Registers/Lfsr5/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Shift\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Shift\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Shift.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Shift.sv\n             Logic/Shift\n             Logic/Shift.v\n             Logic/Shift.sv\n             obj_dir/Logic/Shift\n             obj_dir/Logic/Shift.v\n             obj_dir/Logic/Shift.sv\n%Error: Cannot find file containing module: Registers/Lfsr5,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Registers/Lfsr5/top_module.v\n%Error: Exiting due to 4 error(s)\n'
module top_module (
    input wire clk,
    input wire reset,
    output wire [4:0] q
);

  reg [4:0] q_i;
  assign q = q_i;

  always @(posedge clk) begin
    if (reset) q_i <= {5{1'b1}};
    else begin
      q_i[0] <= q_i[1];
      q_i[1] <= q_i[2];
      q_i[2] <= q_i[3] ^ q_i[0];
      q_i[3] <= q_i[4];
      q_i[4] <= q_i[0] ^ 1'b0;
    end
  end

endmodule
module top_module (
    input wire clk,
    input wire reset,
    output wire [4:0] q
);


  reg [4:0] q_i;
  assign q = q_i;

  always @(posedge clk) begin
    if (reset) q_i <= {5{1'b1}};
    else begin
      q_i[0] <= q_i[1];
      q_i[1] <= q_i[2];
      q_i[2] <= q_i[3] ^ q_i[0];
      q_i[3] <= q_i[4];
      q_i[4] <= q_i[0] ^ 1'b0;
    end
  end

endmodule