data/full_repos/permissive/406831108/CRC_16_Generator.v
1: b'%Error: data/full_repos/permissive/406831108/CRC_16_Generator.v:38: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("dump.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/406831108/CRC_16_Generator.v:39: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(1);\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/406831108/CRC_16_Generator.v:41: Unsupported: Ignoring delay on this delayed statement.\nforever #5 clk=~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/406831108/CRC_16_Generator.v:43: Unsupported: fork statements\ninitial fork\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/406831108/CRC_16_Generator.v:45: Unsupported: Ignoring delay on this delayed statement.\n#10 start=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/406831108/CRC_16_Generator.v:46: Unsupported: Ignoring delay on this delayed statement.\n#20 start=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/406831108/CRC_16_Generator.v:47: Unsupported: Ignoring delay on this delayed statement.\n#20 x=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/406831108/CRC_16_Generator.v:48: Unsupported: Ignoring delay on this delayed statement.\n#80 x=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/406831108/CRC_16_Generator.v:49: Unsupported: Ignoring delay on this delayed statement.\n#100 x=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/406831108/CRC_16_Generator.v:50: Unsupported: Ignoring delay on this delayed statement.\n#170 x=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/406831108/CRC_16_Generator.v:51: Unsupported: Ignoring delay on this delayed statement.\n#180 x=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/406831108/CRC_16_Generator.v:52: Unsupported: Ignoring delay on this delayed statement.\n#240 x=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/406831108/CRC_16_Generator.v:53: Unsupported: Ignoring delay on this delayed statement.\n#250 x=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/406831108/CRC_16_Generator.v:54: Unsupported: Ignoring delay on this delayed statement.\n#320 x=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/406831108/CRC_16_Generator.v:55: Unsupported: Ignoring delay on this delayed statement.\n#340 $finish;\n^\n%Error: Exiting due to 3 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module crc_16(
input x16,
input clk,start,
output reg [15:0]r,
output reg done);
reg temp;
parameter active=1;
integer count;
reg state;
always @(negedge clk) begin
if(start==1) begin
state<=active;
r<=16'hffff; count<=1;
end
end
always @(negedge clk) begin
if(state==active) begin
r[0]<=r[15]+x16;
r[1]<=r[0];
r[2]<=r[1]+r[15]+x16;
r[14:3]<=r[13:2];
r[15]<=r[14]+r[15]+x16;
count<=count+1;
end
if(count==40)
done<=1;
end
endmodule
module crc_16(
input x16,
input clk,start,
output reg [15:0]r,
output reg done);

reg temp;
parameter active=1;
integer count;
reg state;
always @(negedge clk) begin
if(start==1) begin
state<=active;
r<=16'hffff; count<=1;
end
end
always @(negedge clk) begin
if(state==active) begin
r[0]<=r[15]+x16;
r[1]<=r[0];
r[2]<=r[1]+r[15]+x16;
r[14:3]<=r[13:2];
r[15]<=r[14]+r[15]+x16;
count<=count+1;
end
if(count==40)
done<=1;
end
endmodule