data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Counters/Countbcd/top_module_tb.v
1: b'%Error: Cannot find file containing module: Logic/Counters/Countbcd,data/full_repos/permissive/500128826\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/Countbcd,data/full_repos/permissive/500128826\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/Countbcd,data/full_repos/permissive/500128826.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/Countbcd,data/full_repos/permissive/500128826.sv\n             Logic/Counters/Countbcd,data/full_repos/permissive/500128826\n             Logic/Counters/Countbcd,data/full_repos/permissive/500128826.v\n             Logic/Counters/Countbcd,data/full_repos/permissive/500128826.sv\n             obj_dir/Logic/Counters/Countbcd,data/full_repos/permissive/500128826\n             obj_dir/Logic/Counters/Countbcd,data/full_repos/permissive/500128826.v\n             obj_dir/Logic/Counters/Countbcd,data/full_repos/permissive/500128826.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Logic/Counters/Countbcd/top_module_tb.v\n%Error: Exiting due to 3 error(s)\n'
module top_module_tb ();
  wire [3:1] ena;
  wire [15:0] q;

  reg clk = 1'd1;
  reg reset = 1'd1;

  localparam ITERATIONS = 100000;

  always begin
    #0.5 clk = clk + 1;
  end

  always begin
    #90001 reset = reset + 1;
    #9 reset = reset + 1;
  end

  initial begin
    #0.5 reset = reset + 1;
  end

  top_module uut (
      .clk(clk),
      .reset(reset),
      .q(q),
      .ena(ena)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule
module top_module_tb ();

  wire [3:1] ena;
  wire [15:0] q;

  reg clk = 1'd1;
  reg reset = 1'd1;

  localparam ITERATIONS = 100000;

  always begin
    #0.5 clk = clk + 1;
  end

  always begin
    #90001 reset = reset + 1;
    #9 reset = reset + 1;
  end

  initial begin
    #0.5 reset = reset + 1;
  end

  top_module uut (
      .clk(clk),
      .reset(reset),
      .q(q),
      .ena(ena)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule