data/full_repos/permissive/440575220/instruction_memory.v
data/verilator_xmls/3a3fdff0-89f1-48d9-8ce9-86519843f5a0.xml
module instruction_memory(
                          input [31:0]   A,
                          output [31:0] RD
                          );
   reg [31:0]                           RAM[0:255];
   assign RD = RAM[A[9:2]];

   initial $readmemh("binfile.mem", RAM);
endmodule
module instruction_memory(
                          input [31:0]   A,
                          output [31:0] RD
                          );

   reg [31:0]                           RAM[0:255];
   assign RD = RAM[A[9:2]];

   initial $readmemh("binfile.mem", RAM);
endmodule