data/full_repos/permissive/43974493/src/vga_buffer.v
1: b'%Error: data/full_repos/permissive/43974493/src/vga_buffer.v:26: Cannot find include file: definitions.vh\n`include "definitions.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43974493/src,data/full_repos/permissive/43974493/definitions.vh\n             data/full_repos/permissive/43974493/src,data/full_repos/permissive/43974493/definitions.vh.v\n             data/full_repos/permissive/43974493/src,data/full_repos/permissive/43974493/definitions.vh.sv\n             definitions.vh\n             definitions.vh.v\n             definitions.vh.sv\n             obj_dir/definitions.vh\n             obj_dir/definitions.vh.v\n             obj_dir/definitions.vh.sv\n%Error: data/full_repos/permissive/43974493/src/vga_buffer.v:70: Define or directive not defined: \'`SCREEN_HEIGHT\'\n   wire [7:0] y_coord_next = y_coord == `SCREEN_HEIGHT - 1 ? 8\'b0 : y_coord + 1;\n                                        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43974493/src/vga_buffer.v:71: Define or directive not defined: \'`GRAPHICS_MEM_PREFIX\'\n   assign mem_cmd_byte_addr = { `GRAPHICS_MEM_PREFIX, y_coord_next, 8\'b0 };\n                                ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43974493/src/vga_buffer.v:71: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n   assign mem_cmd_byte_addr = { `GRAPHICS_MEM_PREFIX, y_coord_next, 8\'b0 };\n                                                    ^\n%Error: Exiting due to 4 error(s)\n'
module vga_buffer
  (
   input         clk,
   input         clk_fast,
   input         calib_done,
   input [7:0]   x_coord,
   input [7:0]   y_coord,
   input         invalidate,
   output [7:0]  rgb,

   output reg    mem_cmd_en,
   output [2:0]  mem_cmd_instr,
   output [5:0]  mem_cmd_bl,
   output [29:0] mem_cmd_byte_addr,
   input         mem_cmd_empty,
   input         mem_cmd_full,
   output reg    mem_rd_en,
   input [31:0]  mem_rd_data,
   input         mem_rd_full,
   input         mem_rd_empty,
   input [6:0]   mem_rd_count,
   input         mem_rd_overflow,
   input         mem_rd_error
   );

   initial begin
      mem_cmd_en = 0;
      mem_rd_en = 0;
   end


   assign mem_cmd_instr = 3'b001;

   assign mem_cmd_bl = 6'b111111;

   wire [7:0] y_coord_next = y_coord == `SCREEN_HEIGHT - 1 ? 8'b0 : y_coord + 1;
   assign mem_cmd_byte_addr = { `GRAPHICS_MEM_PREFIX, y_coord_next, 8'b0 };


   reg [1:0]   mem_state = `MEM_STATE_IDLE;
   reg [5:0]   mem_words_read = 0;


   reg         write_en = 0;
   reg [5:0]   write_addr = 0;
   reg [31:0]  write_data = 0;
   vga_block_ram vga_block_ram_
     (
      .wr_clk(clk),
      .rd_clk(clk_fast),

      .wr_en(write_en),
      .wr_addr(write_addr),
      .wr_data(write_data),

      .rd_addr(x_coord),
      .rd_data(rgb)
      );


   reg [7:0] invalid_index = 0;
   reg [6:0] mem_wait_timer = 0;
   always @ (posedge clk) begin
      write_en <= 0;
      mem_rd_en <= 0;
      if (calib_done) begin

         case (mem_state)



           `MEM_STATE_IDLE: begin
              if (invalidate && x_coord == 0) begin
                 invalid_index <= 0;
                 mem_state <= `MEM_STATE_CMD;
              end
           end


           `MEM_STATE_CMD: begin
              mem_cmd_en <= ~mem_cmd_en;
              if (mem_cmd_en) begin
                 mem_state <= `MEM_STATE_WAIT;
                 mem_wait_timer <= 0;
              end
           end




           `MEM_STATE_WAIT: begin


              if (invalid_index < x_coord) begin
                 invalid_index <= x_coord;
              end



              if (invalid_index == 255) begin
                 if (!mem_rd_empty) begin
                    mem_rd_en <= 1;
                    mem_state <= `MEM_STATE_READ;
                 end else if (`MEM_WAIT_TIMEOUT <= mem_wait_timer) begin
                    mem_words_read <= 0;
                    mem_state <= `MEM_STATE_IDLE;
                 end else begin
                    mem_wait_timer <= mem_wait_timer + 1;
                 end
              end
           end



           `MEM_STATE_READ: begin
              write_en <= 1;
              write_addr <= mem_words_read;
              write_data <= mem_rd_data;
              mem_words_read <= mem_words_read + 1;
              if (mem_words_read == mem_cmd_bl) begin
                 mem_state <= `MEM_STATE_IDLE;
              end else if (mem_rd_empty) begin
                 mem_state <= `MEM_STATE_WAIT;
                 mem_wait_timer <= 0;
              end else begin
                 mem_rd_en <= 1;
              end
           end
         endcase
      end
   end

endmodule
module vga_buffer
  (
   input         clk,
   input         clk_fast,
   input         calib_done,
   input [7:0]   x_coord,
   input [7:0]   y_coord,
   input         invalidate,
   output [7:0]  rgb,

   output reg    mem_cmd_en,
   output [2:0]  mem_cmd_instr,
   output [5:0]  mem_cmd_bl,
   output [29:0] mem_cmd_byte_addr,
   input         mem_cmd_empty,
   input         mem_cmd_full,
   output reg    mem_rd_en,
   input [31:0]  mem_rd_data,
   input         mem_rd_full,
   input         mem_rd_empty,
   input [6:0]   mem_rd_count,
   input         mem_rd_overflow,
   input         mem_rd_error
   );


   initial begin
      mem_cmd_en = 0;
      mem_rd_en = 0;
   end


   assign mem_cmd_instr = 3'b001;

   assign mem_cmd_bl = 6'b111111;

   wire [7:0] y_coord_next = y_coord == `SCREEN_HEIGHT - 1 ? 8'b0 : y_coord + 1;
   assign mem_cmd_byte_addr = { `GRAPHICS_MEM_PREFIX, y_coord_next, 8'b0 };


   reg [1:0]   mem_state = `MEM_STATE_IDLE;
   reg [5:0]   mem_words_read = 0;


   reg         write_en = 0;
   reg [5:0]   write_addr = 0;
   reg [31:0]  write_data = 0;
   vga_block_ram vga_block_ram_
     (
      .wr_clk(clk),
      .rd_clk(clk_fast),

      .wr_en(write_en),
      .wr_addr(write_addr),
      .wr_data(write_data),

      .rd_addr(x_coord),
      .rd_data(rgb)
      );


   reg [7:0] invalid_index = 0;
   reg [6:0] mem_wait_timer = 0;
   always @ (posedge clk) begin
      write_en <= 0;
      mem_rd_en <= 0;
      if (calib_done) begin

         case (mem_state)



           `MEM_STATE_IDLE: begin
              if (invalidate && x_coord == 0) begin
                 invalid_index <= 0;
                 mem_state <= `MEM_STATE_CMD;
              end
           end


           `MEM_STATE_CMD: begin
              mem_cmd_en <= ~mem_cmd_en;
              if (mem_cmd_en) begin
                 mem_state <= `MEM_STATE_WAIT;
                 mem_wait_timer <= 0;
              end
           end




           `MEM_STATE_WAIT: begin


              if (invalid_index < x_coord) begin
                 invalid_index <= x_coord;
              end



              if (invalid_index == 255) begin
                 if (!mem_rd_empty) begin
                    mem_rd_en <= 1;
                    mem_state <= `MEM_STATE_READ;
                 end else if (`MEM_WAIT_TIMEOUT <= mem_wait_timer) begin
                    mem_words_read <= 0;
                    mem_state <= `MEM_STATE_IDLE;
                 end else begin
                    mem_wait_timer <= mem_wait_timer + 1;
                 end
              end
           end



           `MEM_STATE_READ: begin
              write_en <= 1;
              write_addr <= mem_words_read;
              write_data <= mem_rd_data;
              mem_words_read <= mem_words_read + 1;
              if (mem_words_read == mem_cmd_bl) begin
                 mem_state <= `MEM_STATE_IDLE;
              end else if (mem_rd_empty) begin
                 mem_state <= `MEM_STATE_WAIT;
                 mem_wait_timer <= 0;
              end else begin
                 mem_rd_en <= 1;
              end
           end
         endcase
      end
   end

endmodule