data/full_repos/permissive/48192473/rtl/sound_controller_modules/tb_simple_channel4.v
1: b'%Error: data/full_repos/permissive/48192473/rtl/sound_controller_modules/tb_simple_channel4.v:5: Cannot find include file: aDefinitions.v\n`include "aDefinitions.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/48192473/rtl/sound_controller_modules,data/full_repos/permissive/48192473/aDefinitions.v\n             data/full_repos/permissive/48192473/rtl/sound_controller_modules,data/full_repos/permissive/48192473/aDefinitions.v.v\n             data/full_repos/permissive/48192473/rtl/sound_controller_modules,data/full_repos/permissive/48192473/aDefinitions.v.sv\n             aDefinitions.v\n             aDefinitions.v.v\n             aDefinitions.v.sv\n             obj_dir/aDefinitions.v\n             obj_dir/aDefinitions.v.v\n             obj_dir/aDefinitions.v.sv\n%Error: data/full_repos/permissive/48192473/rtl/sound_controller_modules/tb_simple_channel4.v:6: Cannot find include file: collaterals.v\n`include "collaterals.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/sound_controller_modules/tb_simple_channel4.v:7: Cannot find include file: SoundControllerChannel4.v\n`include "SoundControllerChannel4.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/sound_controller_modules/tb_simple_channel4.v:8: Cannot find include file: SoundControllerOSC1.v\n`include "SoundControllerOSC1.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/sound_controller_modules/tb_simple_channel4.v:9: Cannot find include file: SoundControllerOSC2.v\n`include "SoundControllerOSC2.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/sound_controller_modules/tb_simple_channel4.v:28: Define or directive not defined: \'`CLOCK_CYCLE\'\n    #`CLOCK_CYCLE clk = ~clk;\n     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/48192473/rtl/sound_controller_modules/tb_simple_channel4.v:28: syntax error, unexpected \'=\'\n    #`CLOCK_CYCLE clk = ~clk;\n                      ^\n%Warning-STMTDLY: data/full_repos/permissive/48192473/rtl/sound_controller_modules/tb_simple_channel4.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #`CLOCK_CYCLE clk = ~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/48192473/rtl/sound_controller_modules/tb_simple_channel4.v:69: syntax error, unexpected \'@\'\n    @(negedge clk) rst = 1\'b1;\n    ^\n%Error: data/full_repos/permissive/48192473/rtl/sound_controller_modules/tb_simple_channel4.v:87: syntax error, unexpected \'@\'\n    repeat (2) @ (negedge clk);\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/48192473/rtl/sound_controller_modules/tb_simple_channel4.v:91: Unsupported: Ignoring delay on this delayed statement.\n      #5120 $display ("%0d, ", out);\n      ^\n%Error: Exiting due to 9 error(s), 2 warning(s)\n'
module tb;
  
  reg clk;
  wire clk64;
  wire clk256;
  wire clk131k;
  wire clk262k;
  reg rst;
  wire [4:0] out;
  
  reg [7:0] nr41;
  reg [7:0] nr42;
  reg [7:0] nr43;
  reg [7:0] nr44;


  always begin
    #`CLOCK_CYCLE clk = ~clk;
  end
  
 osc1 o1
  (
    .iClock(clk),
    .iReset(rst),
    .oOut64(clk64),
    .oOut256(clk256)
  );

 osc2 o2
  (
    .iClock(clk),
    .iReset(rst),
    .oOut131k(clk131k),
    .oOut262k(clk262k)
  );


  SoundCtrlChannel4 # () scc2 (
    .iClock(clk),
    .iReset(rst),
    .iOsc64(clk64),
    .iOsc256(clk256),
    .iNR41(nr41),
    .iNR42(nr42),
    .iNR43(nr43),
    .iNR44(nr44),
    .oOut(out)
  );

integer i;

  initial begin




    clk = 0;
    rst = 1'b0;
    @(negedge clk) rst = 1'b1;







    repeat (2) @ (negedge clk);
    rst = 1'b0;

    for ( i = 0; i < 10000; i = i+1) begin
      #5120 $display ("%0d, ", out);
    end

    $finish;
  end
  
endmodule
module tb;

  
  reg clk;
  wire clk64;
  wire clk256;
  wire clk131k;
  wire clk262k;
  reg rst;
  wire [4:0] out;
  
  reg [7:0] nr41;
  reg [7:0] nr42;
  reg [7:0] nr43;
  reg [7:0] nr44;


  always begin
    #`CLOCK_CYCLE clk = ~clk;
  end
  
 osc1 o1
  (
    .iClock(clk),
    .iReset(rst),
    .oOut64(clk64),
    .oOut256(clk256)
  );

 osc2 o2
  (
    .iClock(clk),
    .iReset(rst),
    .oOut131k(clk131k),
    .oOut262k(clk262k)
  );


  SoundCtrlChannel4 # () scc2 (
    .iClock(clk),
    .iReset(rst),
    .iOsc64(clk64),
    .iOsc256(clk256),
    .iNR41(nr41),
    .iNR42(nr42),
    .iNR43(nr43),
    .iNR44(nr44),
    .oOut(out)
  );

integer i;

  initial begin




    clk = 0;
    rst = 1'b0;
    @(negedge clk) rst = 1'b1;







    repeat (2) @ (negedge clk);
    rst = 1'b0;

    for ( i = 0; i < 10000; i = i+1) begin
      #5120 $display ("%0d, ", out);
    end

    $finish;
  end
  
endmodule