data/full_repos/permissive/439731184/multiplexer_from_gates.v
1: b'%Error: data/full_repos/permissive/439731184/multiplexer_from_gates.v:32: Unsupported or unknown PLI call: $monitor\n    $monitor("%b\\t%b\\t%b\\t%b\\t%b\\t%b\\t%b\\t", c0, c1, c2, c3, a, b, y);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/439731184/multiplexer_from_gates.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #10 b = 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/439731184/multiplexer_from_gates.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #10 b = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/multiplexer_from_gates.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #10 b = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/multiplexer_from_gates.v:43: Unsupported: Ignoring delay on this delayed statement.\n    #10 $finish;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/multiplexer_from_gates.v:46: Unsupported: Ignoring delay on this delayed statement.\nalways #1 c0 = ~c0;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/multiplexer_from_gates.v:47: Unsupported: Ignoring delay on this delayed statement.\nalways #2 c1 = ~c1;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/multiplexer_from_gates.v:48: Unsupported: Ignoring delay on this delayed statement.\nalways #3 c2 = ~c2;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/multiplexer_from_gates.v:49: Unsupported: Ignoring delay on this delayed statement.\nalways #4 c3 = ~c3;\n       ^\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux_from_gates(y, c0, c1, c2, c3, a, b);

output y;
input c0, c1, c2, c3, a, b;

wire y, c0, c1, c2, c3, a, b;
wire y0, y1, y2, y3;
wire a_inv, b_inv;

not(a_inv, a);
not(b_inv, b);

and(y0, c0, a_inv, b_inv);
and(y1, c1, a_inv, b);
and(y2, c2, a, b_inv);
and(y3, c3, a, b);

or(y, y0, y1, y2, y3);

endmodule
module mux_from_gates(y, c0, c1, c2, c3, a, b);


output y;
input c0, c1, c2, c3, a, b;

wire y, c0, c1, c2, c3, a, b;
wire y0, y1, y2, y3;
wire a_inv, b_inv;

not(a_inv, a);
not(b_inv, b);

and(y0, c0, a_inv, b_inv);
and(y1, c1, a_inv, b);
and(y2, c2, a, b_inv);
and(y3, c3, a, b);

or(y, y0, y1, y2, y3);

endmodule