data/full_repos/permissive/435516446/MIPS/MEM_WE_Register_TEST.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/MEM_WE_Register_TEST.v:61: Unsupported: Ignoring delay on this delayed statement.\n always #20 clock =~clock;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/MEM_WE_Register_TEST.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #50 hit = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/MEM_WE_Register_TEST.v:74: Unsupported: Ignoring delay on this delayed statement.\n  #50 readData = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/MEM_WE_Register_TEST.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #50 ALUResult = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/MEM_WE_Register_TEST.v:76: Unsupported: Ignoring delay on this delayed statement.\n  #50 writeReg = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/MEM_WE_Register_TEST.v:77: Unsupported: Ignoring delay on this delayed statement.\n  #50 RegWrite = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/MEM_WE_Register_TEST.v:78: Unsupported: Ignoring delay on this delayed statement.\n  #50 MemtoReg = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/MEM_WE_Register_TEST.v:80: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/435516446/MIPS/MEM_WE_Register_TEST.v:45: Cannot find file containing module: \'MEM_WB_Register\'\n MEM_WB_Register uut (\n ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/MEM_WB_Register\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/MEM_WB_Register.v\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/MEM_WB_Register.sv\n             MEM_WB_Register\n             MEM_WB_Register.v\n             MEM_WB_Register.sv\n             obj_dir/MEM_WB_Register\n             obj_dir/MEM_WB_Register.v\n             obj_dir/MEM_WB_Register.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module MEM_WE_Register_TEST;


	reg clock;
	reg hit;
	reg [31:0] readData;
	reg [31:0] ALUResult;
	reg [4:0] writeReg;
	reg RegWrite;
	reg MemtoReg;


	wire hitOut;
	wire [31:0] readDataOut;
	wire [31:0] ALUResultOut;
	wire [4:0] writeRegOut;
	wire RegWriteOut;
	wire MemtoRegOut;


	MEM_WB_Register uut (
		.clock(clock), 
		.hit(hit), 
		.readData(readData), 
		.ALUResult(ALUResult), 
		.writeReg(writeReg), 
		.RegWrite(RegWrite), 
		.MemtoReg(MemtoReg), 
		.hitOut(hitOut), 
		.readDataOut(readDataOut), 
		.ALUResultOut(ALUResultOut), 
		.writeRegOut(writeRegOut), 
		.RegWriteOut(RegWriteOut), 
		.MemtoRegOut(MemtoRegOut)
	);

	always #20 clock =~clock;
	initial begin

		clock = 0;
		hit = 0;
		readData = 0;
		ALUResult = 0;
		writeReg = 0;
		RegWrite = 0;
		MemtoReg = 0;

		
		#50 hit = 1;
		#50 readData = 0;
		#50 ALUResult = 0;
		#50 writeReg = 0;
		#50 RegWrite = 0;
		#50 MemtoReg = 0;

		#100;
        


	end
      
endmodule
module MEM_WE_Register_TEST;



	reg clock;
	reg hit;
	reg [31:0] readData;
	reg [31:0] ALUResult;
	reg [4:0] writeReg;
	reg RegWrite;
	reg MemtoReg;


	wire hitOut;
	wire [31:0] readDataOut;
	wire [31:0] ALUResultOut;
	wire [4:0] writeRegOut;
	wire RegWriteOut;
	wire MemtoRegOut;


	MEM_WB_Register uut (
		.clock(clock), 
		.hit(hit), 
		.readData(readData), 
		.ALUResult(ALUResult), 
		.writeReg(writeReg), 
		.RegWrite(RegWrite), 
		.MemtoReg(MemtoReg), 
		.hitOut(hitOut), 
		.readDataOut(readDataOut), 
		.ALUResultOut(ALUResultOut), 
		.writeRegOut(writeRegOut), 
		.RegWriteOut(RegWriteOut), 
		.MemtoRegOut(MemtoRegOut)
	);

	always #20 clock =~clock;
	initial begin

		clock = 0;
		hit = 0;
		readData = 0;
		ALUResult = 0;
		writeReg = 0;
		RegWrite = 0;
		MemtoReg = 0;

		
		#50 hit = 1;
		#50 readData = 0;
		#50 ALUResult = 0;
		#50 writeReg = 0;
		#50 RegWrite = 0;
		#50 MemtoReg = 0;

		#100;
        


	end
      
endmodule