data/full_repos/permissive/477770962/add4_tb.v
1: b'%Error: data/full_repos/permissive/477770962/add4_tb.v:11: Unsupported or unknown PLI call: $monitor\n $monitor(cout);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/477770962/add4_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n #20 $finish;  \n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/477770962/add4_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n #1 a = $random; b = $random;  \n ^\n%Error: data/full_repos/permissive/477770962/add4_tb.v:24: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("output.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/477770962/add4_tb.v:25: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0);\n ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module add4_tb();
	reg [3:0] a, b;
	wire [3:0] s_7108;
	wire cout;
	
add4 u1(a, b, s_8107, cout);

initial begin
	$monitor(cout);
	
	a = 4'b0000;
	b = 4'b0000;
		
	#20 $finish;
end

always begin
	#1 a = $random; b = $random;
end

initial begin
    $dumpfile("output.vcd");
	$dumpvars(0);
end

endmodule
module add4_tb();

	reg [3:0] a, b;
	wire [3:0] s_7108;
	wire cout;
	
add4 u1(a, b, s_8107, cout);

initial begin
	$monitor(cout);
	
	a = 4'b0000;
	b = 4'b0000;
		
	#20 $finish;
end

always begin
	#1 a = $random; b = $random;
end

initial begin
    $dumpfile("output.vcd");
	$dumpvars(0);
end

endmodule