data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_jp_sstl_bscan.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_jp_sstl_bscan.v:38: Cannot find file containing module: 'bw_u1_muxi21_2x'\nbw_u1_muxi21_2x bs_mux (\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_muxi21_2x\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_muxi21_2x.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_muxi21_2x.sv\n             bw_u1_muxi21_2x\n             bw_u1_muxi21_2x.v\n             bw_u1_muxi21_2x.sv\n             obj_dir/bw_u1_muxi21_2x\n             obj_dir/bw_u1_muxi21_2x.v\n             obj_dir/bw_u1_muxi21_2x.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_jp_sstl_bscan.v:43: Cannot find file containing module: 'bw_u1_inv_2x'\nbw_u1_inv_2x ctl_inv2x (\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_jp_sstl_bscan.v:46: Cannot find file containing module: 'bw_io_jp_bs_baseblk'\nbw_io_jp_bs_baseblk bs_baseblk (\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_jp_sstl_bscan.v:54: Cannot find file containing module: 'bw_u1_inv_1x'\nbw_u1_inv_1x ctl_inv1x (\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_jp_sstl_bscan.v:57: Cannot find file containing module: 'bw_u1_inv_5x'\nbw_u1_inv_5x out_inv5x (\n^~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module bw_io_jp_sstl_bscan(in ,update_dr ,mode_ctl ,shift_dr ,clock_dr ,
     bsr_so ,out ,bsr_si );
output		bsr_so ;
output		out ;
input		in ;
input		update_dr ;
input		mode_ctl ;
input		shift_dr ;
input		clock_dr ;
input		bsr_si ;
 
wire		net033 ;
wire		net035 ;
wire		net042 ;
wire		update_q ;
 
 
bw_u1_muxi21_2x bs_mux (
     .z               (net033 ),
     .d0              (in ),
     .d1              (update_q ),
     .s               (net042 ) );
bw_u1_inv_2x ctl_inv2x (
     .z               (net042 ),
     .a               (net035 ) );
bw_io_jp_bs_baseblk bs_baseblk (
     .upd_q           (update_q ),
     .bsr_si          (bsr_si ),
     .update_dr       (update_dr ),
     .clock_dr        (clock_dr ),
     .shift_dr        (shift_dr ),
     .bsr_so          (bsr_so ),
     .in              (in ) );
bw_u1_inv_1x ctl_inv1x (
     .z               (net035 ),
     .a               (mode_ctl ) );
bw_u1_inv_5x out_inv5x (
     .z               (out ),
     .a               (net033 ) );
endmodule
module bw_io_jp_sstl_bscan(in ,update_dr ,mode_ctl ,shift_dr ,clock_dr ,
     bsr_so ,out ,bsr_si );

output		bsr_so ;
output		out ;
input		in ;
input		update_dr ;
input		mode_ctl ;
input		shift_dr ;
input		clock_dr ;
input		bsr_si ;
 
wire		net033 ;
wire		net035 ;
wire		net042 ;
wire		update_q ;
 
 
bw_u1_muxi21_2x bs_mux (
     .z               (net033 ),
     .d0              (in ),
     .d1              (update_q ),
     .s               (net042 ) );
bw_u1_inv_2x ctl_inv2x (
     .z               (net042 ),
     .a               (net035 ) );
bw_io_jp_bs_baseblk bs_baseblk (
     .upd_q           (update_q ),
     .bsr_si          (bsr_si ),
     .update_dr       (update_dr ),
     .clock_dr        (clock_dr ),
     .shift_dr        (shift_dr ),
     .bsr_so          (bsr_so ),
     .in              (in ) );
bw_u1_inv_1x ctl_inv1x (
     .z               (net035 ),
     .a               (mode_ctl ) );
bw_u1_inv_5x out_inv5x (
     .z               (out ),
     .a               (net033 ) );
endmodule