data/full_repos/permissive/491120667/verilog/rtl/seven_segment_seconds.v
data/verilator_xmls/563f4992-0bbc-46ca-90e9-eb01612d06e6.xml
module seven_segment_seconds (
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif
    input wire clk,
    input wire reset,
    output wire [6:0] led_out,
    output wire [6:0] io_oeb
);

    assign io_oeb = 7'b0000000;

    reg [23:0] second_counter;
    reg [3:0] digit;

    `ifdef COCOTB_SIM
        initial begin
            $dumpfile ("seven_segment_seconds.vcd");
            $dumpvars (0, seven_segment_seconds);
            #1;
        end
        localparam MAX_COUNT = 100;
    `else
        localparam MAX_COUNT = 100;
    `endif


    always @(posedge clk) begin

        if (reset) begin
            second_counter <= 0;
            digit <= 0;
        end else begin

            if (second_counter == MAX_COUNT) begin

                second_counter <= 0;


                digit <= digit + 1'b1;


                if (digit == 9)
                    digit <= 0;

            end else

                second_counter <= second_counter + 1'b1;
        end
    end


    seg7 seg7(.counter(digit), .segments(led_out));

endmodule
module seven_segment_seconds (
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif
    input wire clk,
    input wire reset,
    output wire [6:0] led_out,
    output wire [6:0] io_oeb
);


    assign io_oeb = 7'b0000000;

    reg [23:0] second_counter;
    reg [3:0] digit;

    `ifdef COCOTB_SIM
        initial begin
            $dumpfile ("seven_segment_seconds.vcd");
            $dumpvars (0, seven_segment_seconds);
            #1;
        end
        localparam MAX_COUNT = 100;
    `else
        localparam MAX_COUNT = 100;
    `endif


    always @(posedge clk) begin

        if (reset) begin
            second_counter <= 0;
            digit <= 0;
        end else begin

            if (second_counter == MAX_COUNT) begin

                second_counter <= 0;


                digit <= digit + 1'b1;


                if (digit == 9)
                    digit <= 0;

            end else

                second_counter <= second_counter + 1'b1;
        end
    end


    seg7 seg7(.counter(digit), .segments(led_out));

endmodule