data/full_repos/permissive/449370139/verilog_code/uart_run_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/449370139/verilog_code/uart_run_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/449370139/verilog_code/uart_run_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n             #10\n             ^\n%Error: data/full_repos/permissive/449370139/verilog_code/uart_run_tb.v:34: Cannot find file containing module: \'uart_run\'\nuart_run #(0)uart(.clrn(clrn),.clk(clk),.d_in(d_in),.d_out(d_out),.write(write),.rxd(rxd),.txd(txd),.get(get));\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/449370139/verilog_code,data/full_repos/permissive/449370139/uart_run\n             data/full_repos/permissive/449370139/verilog_code,data/full_repos/permissive/449370139/uart_run.v\n             data/full_repos/permissive/449370139/verilog_code,data/full_repos/permissive/449370139/uart_run.sv\n             uart_run\n             uart_run.v\n             uart_run.sv\n             obj_dir/uart_run\n             obj_dir/uart_run.v\n             obj_dir/uart_run.sv\n%Warning-WIDTH: data/full_repos/permissive/449370139/verilog_code/uart_run_tb.v:49: Operator LT expects 32 or 24 bits on the LHS, but LHS\'s VARREF \'invect\' generates 8 bits.\n                                                                                  : ... In instance uart_run_tb\n    for (invect = 0; invect < 9999999; invect = invect + 1)\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/449370139/verilog_code/uart_run_tb.v:64: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                  : ... In instance uart_run_tb\n                  cou1<=1\'b0;\n                      ^~\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module uart_run_tb();

reg clrn;
reg clk;
reg [7:0] d_in;
reg write;
reg rxd;

wire[7:0] d_out;
wire txd;
wire get;
uart_run #(0)uart(.clrn(clrn),.clk(clk),.d_in(d_in),.d_out(d_out),.write(write),.rxd(rxd),.txd(txd),.get(get));

reg [7:0] invect;
reg [7:0]cou1;
reg [7:0]cou2;
initial
begin
    cou1<=0;
    cou2<=0;
    write<=1'b1;
    clk<=1'b0;
    d_in<=8'b01101110;
    clrn=1'b0;
    #10
    rxd=1'b1;
    for (invect = 0; invect < 9999999; invect = invect + 1)
             begin  
             cou1=cou1+8'b00000001;
             write=~write;
             clrn=1'b1;
             #10
             clk=~clk;
             if(cou1>=16)
             begin
                  rxd<=1'b1;
                  cou2<=cou2+8'b00000001;
                  if(cou2>=14)begin
                      rxd<=1'b0;
                      cou2<=8'b00000000;
                  end
                  cou1<=1'b0;
             end
             end
end

endmodule
module uart_run_tb();


reg clrn;
reg clk;
reg [7:0] d_in;
reg write;
reg rxd;

wire[7:0] d_out;
wire txd;
wire get;
uart_run #(0)uart(.clrn(clrn),.clk(clk),.d_in(d_in),.d_out(d_out),.write(write),.rxd(rxd),.txd(txd),.get(get));

reg [7:0] invect;
reg [7:0]cou1;
reg [7:0]cou2;
initial
begin
    cou1<=0;
    cou2<=0;
    write<=1'b1;
    clk<=1'b0;
    d_in<=8'b01101110;
    clrn=1'b0;
    #10
    rxd=1'b1;
    for (invect = 0; invect < 9999999; invect = invect + 1)
             begin  
             cou1=cou1+8'b00000001;
             write=~write;
             clrn=1'b1;
             #10
             clk=~clk;
             if(cou1>=16)
             begin
                  rxd<=1'b1;
                  cou2<=cou2+8'b00000001;
                  if(cou2>=14)begin
                      rxd<=1'b0;
                      cou2<=8'b00000000;
                  end
                  cou1<=1'b0;
             end
             end
end

endmodule