data/full_repos/permissive/480141277/ps2.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/480141277/ps2.v:68: Signal definition not found, creating implicitly: \'clk2\'\n assign clk2 = FPGAClk;\n        ^~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/480141277/ps2.v:71: Cannot find file containing module: \'shiftreg\'\n shiftreg sr1(.clk(~PS2Clk),.rst(~rst),.shren(1),.din(datain),.dout(D));\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/480141277,data/full_repos/permissive/480141277/shiftreg\n             data/full_repos/permissive/480141277,data/full_repos/permissive/480141277/shiftreg.v\n             data/full_repos/permissive/480141277,data/full_repos/permissive/480141277/shiftreg.sv\n             shiftreg\n             shiftreg.v\n             shiftreg.sv\n             obj_dir/shiftreg\n             obj_dir/shiftreg.v\n             obj_dir/shiftreg.sv\n%Error: data/full_repos/permissive/480141277/ps2.v:73: Cannot find file containing module: \'counter\'\n counter c(.clk(PS2Clk),.clr(clrCounter),.rst(~rst),.count(count));\n ^~~~~~~\n%Error: data/full_repos/permissive/480141277/ps2.v:93: Cannot find file containing module: \'synch\'\n synch s(.PS2Clk(PS2Clk),.FPGAClk(FPGAClk),.rst(~rst),.midout(midout),.count(countSynch));\n ^~~~~\n%Error: data/full_repos/permissive/480141277/ps2.v:123: Cannot find file containing module: \'shiftreg2\'\n shiftreg2 s2(.clk(FPGAClk),.data(Qseg),.rst(~rst),.shren(midout),.dout0(segments0),.dout1(segments1),.dout2(segments2),.dout3(segments3),.dout4(segments4),.dout5(segments5));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/480141277/ps2.v:124: Cannot find file containing module: \'decoder\'\n decoder d1(.in(segments0),.outSeg(SEG1));\n ^~~~~~~\n%Error: data/full_repos/permissive/480141277/ps2.v:125: Cannot find file containing module: \'decoder\'\n decoder d2(.in(segments1),.outSeg(SEG2));\n ^~~~~~~\n%Error: data/full_repos/permissive/480141277/ps2.v:126: Cannot find file containing module: \'decoder\'\n decoder d3(.in(segments2),.outSeg(SEG3));\n ^~~~~~~\n%Error: data/full_repos/permissive/480141277/ps2.v:127: Cannot find file containing module: \'decoder\'\n decoder d4(.in(segments3),.outSeg(SEG4));\n ^~~~~~~\n%Error: data/full_repos/permissive/480141277/ps2.v:128: Cannot find file containing module: \'decoder\'\n decoder d5(.in(segments4),.outSeg(SEG5));\n ^~~~~~~\n%Error: data/full_repos/permissive/480141277/ps2.v:129: Cannot find file containing module: \'decoder\'\n decoder d6(.in(segments5),.outSeg(SEG6));\n ^~~~~~~\n%Error: Exiting due to 10 error(s), 1 warning(s)\n'
module ps2(
	input PS2Clk,
	input FPGAClk,
	input rst,
	input datain,
	output [7:0] scanCode,
	output [6:0] SEG1,
	output [6:0] SEG2,
	output [6:0] SEG3,
	output [6:0] SEG4,
	output [6:0] SEG5,
	output [6:0] SEG6,
	output [7:0] key,
	output shift
	);
	
	reg Qreg;
	reg Qreg2;
	reg [10:0] Q;
	reg [7:0] Qseg;
	reg clrCounter;
	reg [5:0] QSynch;
	
	wire comp0a;
	wire compf0;
	wire [5:0] count;
	wire [10:0] D;
	wire [7:0] D1;
	wire [5:0] DSynch;
	wire [5:0] seg7;
	wire comp21;
	wire midout;
	wire [5:0] countSynch;
	
	wire [7:0]segments0;
	wire [7:0]segments1;
	wire [7:0]segments2;
	wire [7:0]segments3;
	wire [7:0]segments4;
	wire [7:0]segments5;
	
	assign key = Qseg;
	assign clk2 = FPGAClk;
	assign shift = midout;
	
	shiftreg sr1(.clk(~PS2Clk),.rst(~rst),.shren(1),.din(datain),.dout(D));
	assign D1 =  Q[8:1];
	counter c(.clk(PS2Clk),.clr(clrCounter),.rst(~rst),.count(count));
	assign comp0a = (count == 10) ? 1 : 0;
	

	always @(posedge FPGAClk) begin
		if(FPGAClk)
			Qreg <= comp0a;
		else 
			Qreg <= Qreg;
	end
	
	
	always @(posedge FPGAClk) begin
		if(FPGAClk)
			clrCounter <= Qreg;
		else
			clrCounter <= clrCounter;
	end
	

	synch s(.PS2Clk(PS2Clk),.FPGAClk(FPGAClk),.rst(~rst),.midout(midout),.count(countSynch));
	
	

	assign comp21 = (countSynch == 33) ? 1 : 0;
	
	always @ (negedge Qreg) begin
		
		if(comp21)
			Q <= 0;
		else
			Q <= D;
	end
	
	assign compf0 = (D1 != 240) ? 1 : 0;
	
	reg [8:0] keycount;
	

	always @(posedge FPGAClk) begin
		if(compf0) begin
			Qseg <= D1;
			keycount <= keycount + 1;
			end
		else begin
			Qseg <= Qseg;
	end
	end

	
	shiftreg2 s2(.clk(FPGAClk),.data(Qseg),.rst(~rst),.shren(midout),.dout0(segments0),.dout1(segments1),.dout2(segments2),.dout3(segments3),.dout4(segments4),.dout5(segments5));
	decoder d1(.in(segments0),.outSeg(SEG1));
	decoder d2(.in(segments1),.outSeg(SEG2));
	decoder d3(.in(segments2),.outSeg(SEG3));
	decoder d4(.in(segments3),.outSeg(SEG4));
	decoder d5(.in(segments4),.outSeg(SEG5));
	decoder d6(.in(segments5),.outSeg(SEG6));
	
	
	assign scanCode = Q[8:1];
	
	
endmodule
module ps2(
	input PS2Clk,
	input FPGAClk,
	input rst,
	input datain,
	output [7:0] scanCode,
	output [6:0] SEG1,
	output [6:0] SEG2,
	output [6:0] SEG3,
	output [6:0] SEG4,
	output [6:0] SEG5,
	output [6:0] SEG6,
	output [7:0] key,
	output shift
	);

	
	reg Qreg;
	reg Qreg2;
	reg [10:0] Q;
	reg [7:0] Qseg;
	reg clrCounter;
	reg [5:0] QSynch;
	
	wire comp0a;
	wire compf0;
	wire [5:0] count;
	wire [10:0] D;
	wire [7:0] D1;
	wire [5:0] DSynch;
	wire [5:0] seg7;
	wire comp21;
	wire midout;
	wire [5:0] countSynch;
	
	wire [7:0]segments0;
	wire [7:0]segments1;
	wire [7:0]segments2;
	wire [7:0]segments3;
	wire [7:0]segments4;
	wire [7:0]segments5;
	
	assign key = Qseg;
	assign clk2 = FPGAClk;
	assign shift = midout;
	
	shiftreg sr1(.clk(~PS2Clk),.rst(~rst),.shren(1),.din(datain),.dout(D));
	assign D1 =  Q[8:1];
	counter c(.clk(PS2Clk),.clr(clrCounter),.rst(~rst),.count(count));
	assign comp0a = (count == 10) ? 1 : 0;
	

	always @(posedge FPGAClk) begin
		if(FPGAClk)
			Qreg <= comp0a;
		else 
			Qreg <= Qreg;
	end
	
	
	always @(posedge FPGAClk) begin
		if(FPGAClk)
			clrCounter <= Qreg;
		else
			clrCounter <= clrCounter;
	end
	

	synch s(.PS2Clk(PS2Clk),.FPGAClk(FPGAClk),.rst(~rst),.midout(midout),.count(countSynch));
	
	

	assign comp21 = (countSynch == 33) ? 1 : 0;
	
	always @ (negedge Qreg) begin
		
		if(comp21)
			Q <= 0;
		else
			Q <= D;
	end
	
	assign compf0 = (D1 != 240) ? 1 : 0;
	
	reg [8:0] keycount;
	

	always @(posedge FPGAClk) begin
		if(compf0) begin
			Qseg <= D1;
			keycount <= keycount + 1;
			end
		else begin
			Qseg <= Qseg;
	end
	end

	
	shiftreg2 s2(.clk(FPGAClk),.data(Qseg),.rst(~rst),.shren(midout),.dout0(segments0),.dout1(segments1),.dout2(segments2),.dout3(segments3),.dout4(segments4),.dout5(segments5));
	decoder d1(.in(segments0),.outSeg(SEG1));
	decoder d2(.in(segments1),.outSeg(SEG2));
	decoder d3(.in(segments2),.outSeg(SEG3));
	decoder d4(.in(segments3),.outSeg(SEG4));
	decoder d5(.in(segments4),.outSeg(SEG5));
	decoder d6(.in(segments5),.outSeg(SEG6));
	
	
	assign scanCode = Q[8:1];
	
	
endmodule