data/full_repos/permissive/509468557/tools/dsptools/src/main/resources/BBFSinh.v
data/verilator_xmls/dc986669-f97d-4be6-ba33-4fb8c341020d.xml
module BBFSinh(
    input  [63:0] in,
    output reg [63:0] out
);
  always @* begin
  out = $realtobits($sinh($bitstoreal(in)));
  end
endmodule
module BBFSinh(
    input  [63:0] in,
    output reg [63:0] out
);

  always @* begin
  out = $realtobits($sinh($bitstoreal(in)));
  end
endmodule