data/full_repos/permissive/484553918/rtl/tmds_encoder.v
1: b'%Warning-WIDTH: data/full_repos/permissive/484553918/rtl/tmds_encoder.v:97: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                          : ... In instance tmds_encoder\n  assign ones = 4\'b0000 + data[0] + data[1] + data[2] + data[3] + data[4] + data[5] + data[6] + data[7];\n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/484553918/rtl/tmds_encoder.v:97: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                          : ... In instance tmds_encoder\n  assign ones = 4\'b0000 + data[0] + data[1] + data[2] + data[3] + data[4] + data[5] + data[6] + data[7];\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/484553918/rtl/tmds_encoder.v:97: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                          : ... In instance tmds_encoder\n  assign ones = 4\'b0000 + data[0] + data[1] + data[2] + data[3] + data[4] + data[5] + data[6] + data[7];\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/484553918/rtl/tmds_encoder.v:97: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                          : ... In instance tmds_encoder\n  assign ones = 4\'b0000 + data[0] + data[1] + data[2] + data[3] + data[4] + data[5] + data[6] + data[7];\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/484553918/rtl/tmds_encoder.v:97: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                          : ... In instance tmds_encoder\n  assign ones = 4\'b0000 + data[0] + data[1] + data[2] + data[3] + data[4] + data[5] + data[6] + data[7];\n                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/484553918/rtl/tmds_encoder.v:97: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                          : ... In instance tmds_encoder\n  assign ones = 4\'b0000 + data[0] + data[1] + data[2] + data[3] + data[4] + data[5] + data[6] + data[7];\n                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/484553918/rtl/tmds_encoder.v:97: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                          : ... In instance tmds_encoder\n  assign ones = 4\'b0000 + data[0] + data[1] + data[2] + data[3] + data[4] + data[5] + data[6] + data[7];\n                                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/484553918/rtl/tmds_encoder.v:97: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                          : ... In instance tmds_encoder\n  assign ones = 4\'b0000 + data[0] + data[1] + data[2] + data[3] + data[4] + data[5] + data[6] + data[7];\n                                                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/484553918/rtl/tmds_encoder.v:111: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                           : ... In instance tmds_encoder\n  assign data_word_disparity = 4\'b1100 + data_word[0] + data_word[1] + data_word[2] + data_word[3] + data_word[4] + data_word[5] + data_word[6] + data_word[7];\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/484553918/rtl/tmds_encoder.v:111: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                           : ... In instance tmds_encoder\n  assign data_word_disparity = 4\'b1100 + data_word[0] + data_word[1] + data_word[2] + data_word[3] + data_word[4] + data_word[5] + data_word[6] + data_word[7];\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/484553918/rtl/tmds_encoder.v:111: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                           : ... In instance tmds_encoder\n  assign data_word_disparity = 4\'b1100 + data_word[0] + data_word[1] + data_word[2] + data_word[3] + data_word[4] + data_word[5] + data_word[6] + data_word[7];\n                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/484553918/rtl/tmds_encoder.v:111: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                           : ... In instance tmds_encoder\n  assign data_word_disparity = 4\'b1100 + data_word[0] + data_word[1] + data_word[2] + data_word[3] + data_word[4] + data_word[5] + data_word[6] + data_word[7];\n                                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/484553918/rtl/tmds_encoder.v:111: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                           : ... In instance tmds_encoder\n  assign data_word_disparity = 4\'b1100 + data_word[0] + data_word[1] + data_word[2] + data_word[3] + data_word[4] + data_word[5] + data_word[6] + data_word[7];\n                                                                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/484553918/rtl/tmds_encoder.v:111: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                           : ... In instance tmds_encoder\n  assign data_word_disparity = 4\'b1100 + data_word[0] + data_word[1] + data_word[2] + data_word[3] + data_word[4] + data_word[5] + data_word[6] + data_word[7];\n                                                                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/484553918/rtl/tmds_encoder.v:111: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                           : ... In instance tmds_encoder\n  assign data_word_disparity = 4\'b1100 + data_word[0] + data_word[1] + data_word[2] + data_word[3] + data_word[4] + data_word[5] + data_word[6] + data_word[7];\n                                                                                                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/484553918/rtl/tmds_encoder.v:111: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                           : ... In instance tmds_encoder\n  assign data_word_disparity = 4\'b1100 + data_word[0] + data_word[1] + data_word[2] + data_word[3] + data_word[4] + data_word[5] + data_word[6] + data_word[7];\n                                                                                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/484553918/rtl/tmds_encoder.v:115: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                           : ... In instance tmds_encoder\n      dc_bias <= 1\'b0;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/484553918/rtl/tmds_encoder.v:148: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                           : ... In instance tmds_encoder\n        dc_bias <= dc_bias + data_word[8] - data_word_disparity;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/484553918/rtl/tmds_encoder.v:152: Operator SUB expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                           : ... In instance tmds_encoder\n        dc_bias <= dc_bias - data_word_inv[8] + data_word_disparity;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/484553918/rtl/tmds_encoder.v:135: Operator EQ expects 5 bits on the LHS, but LHS\'s VARREF \'dc_bias\' generates 4 bits.\n                                                                           : ... In instance tmds_encoder\n      if(dc_bias == 5\'b00000 || data_word_disparity == 0) begin\n                 ^~\n%Error: Exiting due to 20 warning(s)\n'
module tmds_encoder(
input wire clk,
input wire [7:0] data,
input wire [1:0] c,
input wire blank,
input wire resetn,
output reg [9:0] encoded
);




wire [8:0] xored;
wire [8:0] xnored;
wire [3:0] ones;
reg [8:0] data_word;
reg [8:0] data_word_inv;
wire [3:0] data_word_disparity;
reg [3:0] dc_bias;


  assign xored[0] = data[0];
  assign xored[1] = data[1] ^ xored[0];
  assign xored[2] = data[2] ^ xored[1];
  assign xored[3] = data[3] ^ xored[2];
  assign xored[4] = data[4] ^ xored[3];
  assign xored[5] = data[5] ^ xored[4];
  assign xored[6] = data[6] ^ xored[5];
  assign xored[7] = data[7] ^ xored[6];
  assign xored[8] = 1'b1;
  assign xnored[0] = data[0];
  assign xnored[1] =  ~(data[1] ^ xnored[0]);
  assign xnored[2] =  ~(data[2] ^ xnored[1]);
  assign xnored[3] =  ~(data[3] ^ xnored[2]);
  assign xnored[4] =  ~(data[4] ^ xnored[3]);
  assign xnored[5] =  ~(data[5] ^ xnored[4]);
  assign xnored[6] =  ~(data[6] ^ xnored[5]);
  assign xnored[7] =  ~(data[7] ^ xnored[6]);
  assign xnored[8] = 1'b0;

  assign ones = 4'b0000 + data[0] + data[1] + data[2] + data[3] + data[4] + data[5] + data[6] + data[7];

  always @(ones, data[0], xnored, xored) begin
    if(ones > 4 || (ones == 4 && data[0] == 1'b0)) begin
      data_word <= xnored;
      data_word_inv <=  ~(xnored);
    end
    else begin
      data_word <= xored;
      data_word_inv <=  ~(xored);
    end
  end


  assign data_word_disparity = 4'b1100 + data_word[0] + data_word[1] + data_word[2] + data_word[3] + data_word[4] + data_word[5] + data_word[6] + data_word[7];

  always @(posedge clk) begin
    if (!resetn)
      dc_bias <= 1'b0;
    if(blank == 1'b1) begin

      case(c)
      2'b00 : begin
        encoded <= 10'b1101010100;
      end
      2'b01 : begin
        encoded <= 10'b0010101011;
      end
      2'b10 : begin
        encoded <= 10'b0101010100;
      end
      default : begin
        encoded <= 10'b1010101011;
      end
      endcase
      dc_bias <= {4{1'b0}};
    end
    else begin
      if(dc_bias == 5'b00000 || data_word_disparity == 0) begin

        if(data_word[8] == 1'b1) begin
          encoded <= {2'b01,data_word[7:0]};
          dc_bias <= dc_bias + data_word_disparity;
        end
        else begin
          encoded <= {2'b10,data_word_inv[7:0]};
          dc_bias <= dc_bias - data_word_disparity;
        end
      end
      else if((dc_bias[3] == 1'b0 && data_word_disparity[3] == 1'b0) || (dc_bias[3] == 1'b1 && data_word_disparity[3] == 1'b1)) begin
        encoded <= {1'b1,data_word[8],data_word_inv[7:0]};
        dc_bias <= dc_bias + data_word[8] - data_word_disparity;
      end
      else begin
        encoded <= {1'b0,data_word};
        dc_bias <= dc_bias - data_word_inv[8] + data_word_disparity;
      end
    end
  end


endmodule
module tmds_encoder(
input wire clk,
input wire [7:0] data,
input wire [1:0] c,
input wire blank,
input wire resetn,
output reg [9:0] encoded
);





wire [8:0] xored;
wire [8:0] xnored;
wire [3:0] ones;
reg [8:0] data_word;
reg [8:0] data_word_inv;
wire [3:0] data_word_disparity;
reg [3:0] dc_bias;


  assign xored[0] = data[0];
  assign xored[1] = data[1] ^ xored[0];
  assign xored[2] = data[2] ^ xored[1];
  assign xored[3] = data[3] ^ xored[2];
  assign xored[4] = data[4] ^ xored[3];
  assign xored[5] = data[5] ^ xored[4];
  assign xored[6] = data[6] ^ xored[5];
  assign xored[7] = data[7] ^ xored[6];
  assign xored[8] = 1'b1;
  assign xnored[0] = data[0];
  assign xnored[1] =  ~(data[1] ^ xnored[0]);
  assign xnored[2] =  ~(data[2] ^ xnored[1]);
  assign xnored[3] =  ~(data[3] ^ xnored[2]);
  assign xnored[4] =  ~(data[4] ^ xnored[3]);
  assign xnored[5] =  ~(data[5] ^ xnored[4]);
  assign xnored[6] =  ~(data[6] ^ xnored[5]);
  assign xnored[7] =  ~(data[7] ^ xnored[6]);
  assign xnored[8] = 1'b0;

  assign ones = 4'b0000 + data[0] + data[1] + data[2] + data[3] + data[4] + data[5] + data[6] + data[7];

  always @(ones, data[0], xnored, xored) begin
    if(ones > 4 || (ones == 4 && data[0] == 1'b0)) begin
      data_word <= xnored;
      data_word_inv <=  ~(xnored);
    end
    else begin
      data_word <= xored;
      data_word_inv <=  ~(xored);
    end
  end


  assign data_word_disparity = 4'b1100 + data_word[0] + data_word[1] + data_word[2] + data_word[3] + data_word[4] + data_word[5] + data_word[6] + data_word[7];

  always @(posedge clk) begin
    if (!resetn)
      dc_bias <= 1'b0;
    if(blank == 1'b1) begin

      case(c)
      2'b00 : begin
        encoded <= 10'b1101010100;
      end
      2'b01 : begin
        encoded <= 10'b0010101011;
      end
      2'b10 : begin
        encoded <= 10'b0101010100;
      end
      default : begin
        encoded <= 10'b1010101011;
      end
      endcase
      dc_bias <= {4{1'b0}};
    end
    else begin
      if(dc_bias == 5'b00000 || data_word_disparity == 0) begin

        if(data_word[8] == 1'b1) begin
          encoded <= {2'b01,data_word[7:0]};
          dc_bias <= dc_bias + data_word_disparity;
        end
        else begin
          encoded <= {2'b10,data_word_inv[7:0]};
          dc_bias <= dc_bias - data_word_disparity;
        end
      end
      else if((dc_bias[3] == 1'b0 && data_word_disparity[3] == 1'b0) || (dc_bias[3] == 1'b1 && data_word_disparity[3] == 1'b1)) begin
        encoded <= {1'b1,data_word[8],data_word_inv[7:0]};
        dc_bias <= dc_bias + data_word[8] - data_word_disparity;
      end
      else begin
        encoded <= {1'b0,data_word};
        dc_bias <= dc_bias - data_word_inv[8] + data_word_disparity;
      end
    end
  end


endmodule