data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/cp0/rtl/pa_cp0_srst.v
data/verilator_xmls/5030d8d7-0590-490f-8ca5-d5047a950684.xml
module pa_cp0_srst(
  cp0_ifu_srst_mask,
  cp0_ifu_srst_req,
  cp0_sysio_srst,
  cpurst_b,
  ifu_cp0_srst_ack,
  lsu_cp0_sync_ack,
  regs_srst_srst_vld,
  regs_srst_srstmd,
  rtu_yy_xx_dbgon,
  rtu_yy_xx_flush,
  srst_in_wait_state,
  srst_iui_stall,
  srst_sm_clk,
  srst_special_srst_sm_clk_en,
  sysio_cp0_clk_en
);


input          cpurst_b;                   
input          ifu_cp0_srst_ack;           
input          lsu_cp0_sync_ack;           
input          regs_srst_srst_vld;         
input   [1:0]  regs_srst_srstmd;           
input          rtu_yy_xx_dbgon;            
input          rtu_yy_xx_flush;            
input          srst_sm_clk;                
input          sysio_cp0_clk_en;           
output         cp0_ifu_srst_mask;          
output         cp0_ifu_srst_req;           
output  [1:0]  cp0_sysio_srst;             
output         srst_in_wait_state;         
output         srst_iui_stall;             
output         srst_special_srst_sm_clk_en; 


reg     [1:0]  cur_state;                  
reg     [1:0]  next_state;                 


wire           cp0_ifu_srst_mask;          
wire           cp0_ifu_srst_req;           
wire    [1:0]  cp0_sysio_srst;             
wire           cpurst_b;                   
wire           ifu_cp0_srst_ack;           
wire           lsu_cp0_sync_ack;           
wire           regs_srst_srst_vld;         
wire    [1:0]  regs_srst_srstmd;           
wire           rtu_yy_xx_dbgon;            
wire           rtu_yy_xx_flush;            
wire           srst_ack;                   
wire           srst_cmplt;                 
wire           srst_in_wait_state;         
wire           srst_iui_stall;             
wire           srst_sm_clk;                
wire           srst_sm_clk_en;             
wire           srst_special_srst_sm_clk_en; 
wire           sysio_cp0_clk_en;           


parameter IDLE   = 2'b00;
parameter WFACK  = 2'b01;
parameter WFCPLT = 2'b10;
parameter WFRST  = 2'b11;




assign srst_sm_clk_en = regs_srst_srst_vld || (cur_state[1:0] != IDLE); 













always @(posedge srst_sm_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    cur_state[1:0] <= IDLE;
  else if(rtu_yy_xx_flush)
    cur_state[1:0] <= IDLE;
  else
    cur_state[1:0] <= next_state[1:0];
end


always @( cur_state[1:0]
       or regs_srst_srst_vld
       or sysio_cp0_clk_en
       or srst_ack)
begin
    case(cur_state[1:0])
  IDLE   : if(regs_srst_srst_vld)
             next_state[1:0] = WFACK;
           else
             next_state[1:0] = IDLE;
  WFACK  : if(srst_ack)
             next_state[1:0] = WFCPLT;
           else
             next_state[1:0] = WFACK;
  WFCPLT : if(sysio_cp0_clk_en)
             next_state[1:0] = WFRST;
           else
             next_state[1:0] = WFCPLT;
  WFRST  :   next_state[1:0] = WFRST;
  default:   next_state[1:0] = IDLE;
  endcase

end

assign srst_in_wait_state = (cur_state[1:0] == WFACK);
assign srst_cmplt         = (cur_state[1:0] == WFCPLT);



assign srst_iui_stall = (cur_state[1:0] == IDLE) && regs_srst_srst_vld
                     || (cur_state[1:0] != IDLE);

assign cp0_ifu_srst_req = srst_in_wait_state;





assign srst_ack = (ifu_cp0_srst_ack && lsu_cp0_sync_ack)
               || rtu_yy_xx_dbgon;
assign cp0_sysio_srst[1:0] = {2{srst_cmplt && sysio_cp0_clk_en}} & regs_srst_srstmd[1:0];

assign cp0_ifu_srst_mask = (cur_state[1:0] == WFCPLT) || (cur_state[1:0] == WFRST);

assign srst_special_srst_sm_clk_en = srst_sm_clk_en;


endmodule
module pa_cp0_srst(
  cp0_ifu_srst_mask,
  cp0_ifu_srst_req,
  cp0_sysio_srst,
  cpurst_b,
  ifu_cp0_srst_ack,
  lsu_cp0_sync_ack,
  regs_srst_srst_vld,
  regs_srst_srstmd,
  rtu_yy_xx_dbgon,
  rtu_yy_xx_flush,
  srst_in_wait_state,
  srst_iui_stall,
  srst_sm_clk,
  srst_special_srst_sm_clk_en,
  sysio_cp0_clk_en
);



input          cpurst_b;                   
input          ifu_cp0_srst_ack;           
input          lsu_cp0_sync_ack;           
input          regs_srst_srst_vld;         
input   [1:0]  regs_srst_srstmd;           
input          rtu_yy_xx_dbgon;            
input          rtu_yy_xx_flush;            
input          srst_sm_clk;                
input          sysio_cp0_clk_en;           
output         cp0_ifu_srst_mask;          
output         cp0_ifu_srst_req;           
output  [1:0]  cp0_sysio_srst;             
output         srst_in_wait_state;         
output         srst_iui_stall;             
output         srst_special_srst_sm_clk_en; 


reg     [1:0]  cur_state;                  
reg     [1:0]  next_state;                 


wire           cp0_ifu_srst_mask;          
wire           cp0_ifu_srst_req;           
wire    [1:0]  cp0_sysio_srst;             
wire           cpurst_b;                   
wire           ifu_cp0_srst_ack;           
wire           lsu_cp0_sync_ack;           
wire           regs_srst_srst_vld;         
wire    [1:0]  regs_srst_srstmd;           
wire           rtu_yy_xx_dbgon;            
wire           rtu_yy_xx_flush;            
wire           srst_ack;                   
wire           srst_cmplt;                 
wire           srst_in_wait_state;         
wire           srst_iui_stall;             
wire           srst_sm_clk;                
wire           srst_sm_clk_en;             
wire           srst_special_srst_sm_clk_en; 
wire           sysio_cp0_clk_en;           


parameter IDLE   = 2'b00;
parameter WFACK  = 2'b01;
parameter WFCPLT = 2'b10;
parameter WFRST  = 2'b11;




assign srst_sm_clk_en = regs_srst_srst_vld || (cur_state[1:0] != IDLE); 













always @(posedge srst_sm_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    cur_state[1:0] <= IDLE;
  else if(rtu_yy_xx_flush)
    cur_state[1:0] <= IDLE;
  else
    cur_state[1:0] <= next_state[1:0];
end


always @( cur_state[1:0]
       or regs_srst_srst_vld
       or sysio_cp0_clk_en
       or srst_ack)
begin
    case(cur_state[1:0])
  IDLE   : if(regs_srst_srst_vld)
             next_state[1:0] = WFACK;
           else
             next_state[1:0] = IDLE;
  WFACK  : if(srst_ack)
             next_state[1:0] = WFCPLT;
           else
             next_state[1:0] = WFACK;
  WFCPLT : if(sysio_cp0_clk_en)
             next_state[1:0] = WFRST;
           else
             next_state[1:0] = WFCPLT;
  WFRST  :   next_state[1:0] = WFRST;
  default:   next_state[1:0] = IDLE;
  endcase

end

assign srst_in_wait_state = (cur_state[1:0] == WFACK);
assign srst_cmplt         = (cur_state[1:0] == WFCPLT);



assign srst_iui_stall = (cur_state[1:0] == IDLE) && regs_srst_srst_vld
                     || (cur_state[1:0] != IDLE);

assign cp0_ifu_srst_req = srst_in_wait_state;





assign srst_ack = (ifu_cp0_srst_ack && lsu_cp0_sync_ack)
               || rtu_yy_xx_dbgon;
assign cp0_sysio_srst[1:0] = {2{srst_cmplt && sysio_cp0_clk_en}} & regs_srst_srstmd[1:0];

assign cp0_ifu_srst_mask = (cur_state[1:0] == WFCPLT) || (cur_state[1:0] == WFRST);

assign srst_special_srst_sm_clk_en = srst_sm_clk_en;


endmodule