data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/ALU.v
1: b'%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/ALU.v:1: Cannot find include file: ../defined.vh\n`include "../defined.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips,data/full_repos/permissive/486954482/../defined.vh\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips,data/full_repos/permissive/486954482/../defined.vh.v\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips,data/full_repos/permissive/486954482/../defined.vh.sv\n             ../defined.vh\n             ../defined.vh.v\n             ../defined.vh.sv\n             obj_dir/../defined.vh\n             obj_dir/../defined.vh.v\n             obj_dir/../defined.vh.sv\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/ALU.v:49: Define or directive not defined: \'`ALU_NOTHING\'\n  `ALU_NOTHING:\n  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/ALU.v:49: syntax error, unexpected \':\', expecting endcase\n  `ALU_NOTHING:\n              ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/ALU.v:51: Define or directive not defined: \'`ALU_ADD\'\n  `ALU_ADD:\n  ^~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/ALU.v:56: Define or directive not defined: \'`ALU_SUBTRACT\'\n  `ALU_SUBTRACT:\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/ALU.v:57: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n  begin\n  ^~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/ALU.v:61: Define or directive not defined: \'`ALU_LESS_THAN\'\n  `ALU_LESS_THAN: \n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/ALU.v:62: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n  begin\n  ^~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/ALU.v:66: Define or directive not defined: \'`ALU_LESS_THAN_SIGNED\'\n  `ALU_LESS_THAN_SIGNED: \n  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/ALU.v:67: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n  begin\n  ^~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/ALU.v:71: Define or directive not defined: \'`ALU_OR\'\n  `ALU_OR:\n  ^~~~~~~\n%Warning-ENDLABEL: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/ALU.v:72: End label \'c_alu\' does not match begin label \'\'\n   c_alu<=a_in|b_in;\n   ^~~~~\n                   ... Use "/* verilator lint_off ENDLABEL */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/ALU.v:72: syntax error, unexpected <=\n   c_alu<=a_in|b_in;\n        ^~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/ALU.v:73: Define or directive not defined: \'`ALU_AND\'\n  `ALU_AND:\n  ^~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/ALU.v:75: Define or directive not defined: \'`ALU_XOR\'\n  `ALU_XOR:      \n  ^~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/mips/ALU.v:77: Define or directive not defined: \'`ALU_NOR\'\n  `ALU_NOR:\n  ^~~~~~~~\n%Error: Cannot continue\n'
module  ALU
( 
	a_in ,
	b_in ,
	alu_function ,
	c_alu 
);
	input [31:0]a_in;
	input [31:0]b_in;
	input [3:0]alu_function;
	output reg [31:0]c_alu;
	

	
	wire signed [31:0]a_in_s, b_in_s;
	
	assign a_in_s=a_in;
	assign b_in_s=b_in;
	

	wire [31:0] b_b_not;
	wire [31:0] adder_out;
	wire cout;
	reg cin;

	assign b_b_not = (cin)?~b_in:b_in;

	ADD 
	#(
		.N(32)
	)
	ADD_
	(
		.A(a_in),
		.B(b_b_not),
		.CI(cin),
		.S(adder_out),
		.CO(cout)
	);

	
	always@(*)
	begin
		c_alu<=32'b0;
		cin <= 0;
		case(alu_function)
		`ALU_NOTHING:
			c_alu<=32'b0;
		`ALU_ADD:
		begin
			cin <= 0;
			c_alu<=adder_out;
		end
		`ALU_SUBTRACT:
		begin
			cin <= 1;
			c_alu<=adder_out;
		end
		`ALU_LESS_THAN:
		begin
			cin <= 1;
			c_alu<={31'b0, ~cout};
		end
		`ALU_LESS_THAN_SIGNED:
		begin
			cin <= 1;
			c_alu<={31'b0, (a_in[31]&~b_in[31] | adder_out[31]&(~a_in[31]^b_in[31]))};
		end
		`ALU_OR:
			c_alu<=a_in|b_in;
		`ALU_AND:
			c_alu<=a_in&b_in;
		`ALU_XOR:      
			c_alu<=a_in^b_in;
		`ALU_NOR:
			c_alu<=~(a_in|b_in);
		default:
			c_alu<=32'b0;
		endcase
	end
   
   
endmodule
module  ALU
( 
	a_in ,
	b_in ,
	alu_function ,
	c_alu 
);

	input [31:0]a_in;
	input [31:0]b_in;
	input [3:0]alu_function;
	output reg [31:0]c_alu;
	

	
	wire signed [31:0]a_in_s, b_in_s;
	
	assign a_in_s=a_in;
	assign b_in_s=b_in;
	

	wire [31:0] b_b_not;
	wire [31:0] adder_out;
	wire cout;
	reg cin;

	assign b_b_not = (cin)?~b_in:b_in;

	ADD 
	#(
		.N(32)
	)
	ADD_
	(
		.A(a_in),
		.B(b_b_not),
		.CI(cin),
		.S(adder_out),
		.CO(cout)
	);

	
	always@(*)
	begin
		c_alu<=32'b0;
		cin <= 0;
		case(alu_function)
		`ALU_NOTHING:
			c_alu<=32'b0;
		`ALU_ADD:
		begin
			cin <= 0;
			c_alu<=adder_out;
		end
		`ALU_SUBTRACT:
		begin
			cin <= 1;
			c_alu<=adder_out;
		end
		`ALU_LESS_THAN:
		begin
			cin <= 1;
			c_alu<={31'b0, ~cout};
		end
		`ALU_LESS_THAN_SIGNED:
		begin
			cin <= 1;
			c_alu<={31'b0, (a_in[31]&~b_in[31] | adder_out[31]&(~a_in[31]^b_in[31]))};
		end
		`ALU_OR:
			c_alu<=a_in|b_in;
		`ALU_AND:
			c_alu<=a_in&b_in;
		`ALU_XOR:      
			c_alu<=a_in^b_in;
		`ALU_NOR:
			c_alu<=~(a_in|b_in);
		default:
			c_alu<=32'b0;
		endcase
	end
   
   
endmodule