data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift_tb/tf_dir36to8.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift_tb/tf_dir36to8.v:36: Unsupported: Ignoring delay on this delayed statement.\nalways #10 clk <= ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift_tb/tf_dir36to8.v:51: Cannot find file containing module: \'dir36to8\'\ndir36to8 tb_dir36to8\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift_tb,data/full_repos/permissive/507203156/dir36to8\n             data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift_tb,data/full_repos/permissive/507203156/dir36to8.v\n             data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift_tb,data/full_repos/permissive/507203156/dir36to8.sv\n             dir36to8\n             dir36to8.v\n             dir36to8.sv\n             obj_dir/dir36to8\n             obj_dir/dir36to8.v\n             obj_dir/dir36to8.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tf_dir36to8();

reg     clk;
reg [5:0]   dir_in;
reg [5:0]   dir_main;
wire    [2:0]   dir_out;

initial begin
    clk = 1'b0;
    dir_in = 6'd0;
    dir_main = 6'd0;
end

always #10 clk <= ~clk;

always@(posedge clk)
    if(dir_in > 6'd34)
        dir_in <= 6'd0;
    else
        dir_in <= dir_in + 6'd1;

always@(posedge clk)
    if(dir_main > 6'd33)
        dir_main <= 6'd0;
    else
        dir_main <= dir_main + 6'd2;
        
        
dir36to8 tb_dir36to8
(
    .dir_in(dir_in),
	.dir_main(dir_main),
    .dir_out(dir_out)
);


endmodule
module tf_dir36to8();


reg     clk;
reg [5:0]   dir_in;
reg [5:0]   dir_main;
wire    [2:0]   dir_out;

initial begin
    clk = 1'b0;
    dir_in = 6'd0;
    dir_main = 6'd0;
end

always #10 clk <= ~clk;

always@(posedge clk)
    if(dir_in > 6'd34)
        dir_in <= 6'd0;
    else
        dir_in <= dir_in + 6'd1;

always@(posedge clk)
    if(dir_main > 6'd33)
        dir_main <= 6'd0;
    else
        dir_main <= dir_main + 6'd2;
        
        
dir36to8 tb_dir36to8
(
    .dir_in(dir_in),
	.dir_main(dir_main),
    .dir_out(dir_out)
);


endmodule