data/full_repos/permissive/520471938/iiit_ba.v
1: b'%Warning-WIDTH: data/full_repos/permissive/520471938/iiit_ba.v:33: Operator ADD expects 5 bits on the RHS, but RHS\'s VARREF \'carry_in\' generates 1 bits.\n                                                                 : ... In instance iiitb_ba\n        sum_temp = a+b+carry_in;  \n                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module iiitb_ba(a,b,carry_in,sum,carry);





    input [3:0] a,b;

    input carry_in;

    output [3:0] sum;

    output carry;



    reg [4:0] sum_temp;

    reg [3:0] sum;

    reg carry;  





    always @(a,b,carry_in)

    begin

        sum_temp = a+b+carry_in;

        if(sum_temp > 9)    begin

            sum_temp = sum_temp+6;

            carry = 1;

            sum = sum_temp[3:0];    end

        else    begin

            carry = 0;

            sum = sum_temp[3:0];

        end

    end     



endmodule
module iiitb_ba(a,b,carry_in,sum,carry);






    input [3:0] a,b;

    input carry_in;

    output [3:0] sum;

    output carry;



    reg [4:0] sum_temp;

    reg [3:0] sum;

    reg carry;  





    always @(a,b,carry_in)

    begin

        sum_temp = a+b+carry_in;

        if(sum_temp > 9)    begin

            sum_temp = sum_temp+6;

            carry = 1;

            sum = sum_temp[3:0];    end

        else    begin

            carry = 0;

            sum = sum_temp[3:0];

        end

    end     



endmodule