data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa/fpmult.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa/fpmult.v:47: Cannot find file containing module: 'expcal'\nexpcal expcali(a[30:23],b[30:23],biasd,exprslt);\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa,data/full_repos/permissive/530013823/expcal\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa,data/full_repos/permissive/530013823/expcal.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa,data/full_repos/permissive/530013823/expcal.sv\n             expcal\n             expcal.v\n             expcal.sv\n             obj_dir/expcal\n             obj_dir/expcal.v\n             obj_dir/expcal.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa/fpmult.v:54: Cannot find file containing module: 'i2424vedic'\ni2424vedic i24vedici({1'b1,a[22:0]},{1'b1,b[22:0]},vedicrs);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/csa/fpmult.v:55: Cannot find file containing module: 'normalize23'\nnormalize23 normi(vedicrs,mtsrs,biasd);\n^~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module fpmult
    (
     a,
     b,
     rslt
     );




parameter WIDTH = 32;




input [WIDTH-1:0] a;
input [WIDTH-1:0] b;

output [WIDTH-1:0] rslt;







wire [31:0] calrslt;

assign             calrslt[31] = a[31] ^ b[31];

wire [7:0]         exprslt;
wire [7:0]         biasd;

expcal expcali(a[30:23],b[30:23],biasd,exprslt);

assign             calrslt[30:23] = exprslt;

wire [22:0]        mtsrs;
wire [47:0]        vedicrs;

i2424vedic i24vedici({1'b1,a[22:0]},{1'b1,b[22:0]},vedicrs);
normalize23 normi(vedicrs,mtsrs,biasd);

assign             calrslt[22:0] = mtsrs;

wire               zrdet;

assign             zrdet = !(|a) | !(|b);

assign             rslt = zrdet ? 32'b0 : calrslt;

endmodule
module fpmult
    (
     a,
     b,
     rslt
     );





parameter WIDTH = 32;




input [WIDTH-1:0] a;
input [WIDTH-1:0] b;

output [WIDTH-1:0] rslt;







wire [31:0] calrslt;

assign             calrslt[31] = a[31] ^ b[31];

wire [7:0]         exprslt;
wire [7:0]         biasd;

expcal expcali(a[30:23],b[30:23],biasd,exprslt);

assign             calrslt[30:23] = exprslt;

wire [22:0]        mtsrs;
wire [47:0]        vedicrs;

i2424vedic i24vedici({1'b1,a[22:0]},{1'b1,b[22:0]},vedicrs);
normalize23 normi(vedicrs,mtsrs,biasd);

assign             calrslt[22:0] = mtsrs;

wire               zrdet;

assign             zrdet = !(|a) | !(|b);

assign             rslt = zrdet ? 32'b0 : calrslt;

endmodule