data/full_repos/permissive/406635962/src/rtl/exu_branchslv.v
1: b'%Error: data/full_repos/permissive/406635962/src/rtl/exu_branchslv.v:7: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_branchslv.v:15: Define or directive not defined: \'`PC_SIZE\'\n    input [`PC_SIZE-1:0] cmt_i_pc,\n           ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_branchslv.v:16: Define or directive not defined: \'`XLEN\'\n    input [`XLEN-1:0] cmt_i_imm,\n           ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_branchslv.v:20: Define or directive not defined: \'`PC_SIZE\'\n    output [`PC_SIZE-1:0] brchmis_flush_add_op1,\n            ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_branchslv.v:21: Define or directive not defined: \'`PC_SIZE\'\n    output [`PC_SIZE-1:0] brchmis_flush_add_op2\n            ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_branchslv.v:32: Define or directive not defined: \'`PC_SIZE\'\nassign brchmis_flush_add_op2 = cmt_i_bjp_prdt? `PC_SIZE\'d4:cmt_i_imm[`PC_SIZE-1:0];\n                                               ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/exu_branchslv.v:32: Define or directive not defined: \'`PC_SIZE\'\nassign brchmis_flush_add_op2 = cmt_i_bjp_prdt? `PC_SIZE\'d4:cmt_i_imm[`PC_SIZE-1:0];\n                                                                     ^~~~~~~~\n%Error: Exiting due to 7 error(s)\n'
module exu_branchslv (
    input cmt_i_valid,
    output cmt_i_ready,
    input cmt_i_bjp,
    input cmt_i_bjp_prdt,
    input cmt_i_bjp_rslv,
    input [`PC_SIZE-1:0] cmt_i_pc,
    input [`XLEN-1:0] cmt_i_imm,

    input brchmis_flush_ack,
    output brchmis_flush_req,
    output [`PC_SIZE-1:0] brchmis_flush_add_op1,
    output [`PC_SIZE-1:0] brchmis_flush_add_op2
);
wire brchmis_need_flush = cmt_i_bjp
                                            & (cmt_i_bjp_prdt ^ cmt_i_bjp_rslv);
assign brchmis_flush_req = cmt_i_valid & brchmis_need_flush;


assign cmt_i_ready = (~cmt_i_bjp) | 
                                   (brchmis_need_flush? brchmis_flush_ack:1'b1);

assign brchmis_flush_add_op1    = cmt_i_pc;
assign brchmis_flush_add_op2 = cmt_i_bjp_prdt? `PC_SIZE'd4:cmt_i_imm[`PC_SIZE-1:0];
endmodule
module exu_branchslv (
    input cmt_i_valid,
    output cmt_i_ready,
    input cmt_i_bjp,
    input cmt_i_bjp_prdt,
    input cmt_i_bjp_rslv,
    input [`PC_SIZE-1:0] cmt_i_pc,
    input [`XLEN-1:0] cmt_i_imm,

    input brchmis_flush_ack,
    output brchmis_flush_req,
    output [`PC_SIZE-1:0] brchmis_flush_add_op1,
    output [`PC_SIZE-1:0] brchmis_flush_add_op2
);

wire brchmis_need_flush = cmt_i_bjp
                                            & (cmt_i_bjp_prdt ^ cmt_i_bjp_rslv);
assign brchmis_flush_req = cmt_i_valid & brchmis_need_flush;


assign cmt_i_ready = (~cmt_i_bjp) | 
                                   (brchmis_need_flush? brchmis_flush_ack:1'b1);

assign brchmis_flush_add_op1    = cmt_i_pc;
assign brchmis_flush_add_op2 = cmt_i_bjp_prdt? `PC_SIZE'd4:cmt_i_imm[`PC_SIZE-1:0];
endmodule