data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/DataExt.v
1: b'%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/DataExt.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new,data/full_repos/permissive/433174928/defines.vh\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new,data/full_repos/permissive/433174928/defines.vh.v\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new,data/full_repos/permissive/433174928/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/DataExt.v:16: Define or directive not defined: \'`LB\'\n            `LB: begin\n            ^~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/DataExt.v:16: syntax error, unexpected \':\', expecting endcase\n            `LB: begin\n               ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/DataExt.v:24: Define or directive not defined: \'`LH\'\n            `LH: begin \n            ^~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/DataExt.v:24: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `LH: begin \n                 ^~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/DataExt.v:32: Define or directive not defined: \'`LW\'\n            `LW: begin       \n            ^~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/DataExt.v:32: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `LW: begin       \n                 ^~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/DataExt.v:35: Define or directive not defined: \'`LBU\'\n            `LBU: begin\n            ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/DataExt.v:35: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `LBU: begin\n                  ^~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/DataExt.v:39: Define or directive not defined: \'`LHU\'\n            `LHU: begin  \n            ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/DataExt.v:39: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `LHU: begin  \n                  ^~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/DataExt.v:43: syntax error, unexpected \':\', expecting clocking\n            default:\n                   ^\n%Error: Exiting due to 12 error(s)\n'
module DataExt(
    input wire [2:0] opcode,
    input wire [31:0] data,
    output wire [31:0] dout
    );
    
    reg [31:0] d_out;
    
    always@(*) begin
        case(opcode)
            `LB: begin
                if (data[7]==1)

                    d_out <= {{24 {1'b1}}, data[7:0]};
                else

                    d_out <= {{24 {1'b0}}, data[7:0]};
            end
            `LH: begin 
                if (data[15]==1)

                    d_out <= {{16 {1'b1}}, data[15:0]};
                else

                    d_out <= {{16 {1'b0}}, data[15:0]};    
            end
            `LW: begin       
                d_out <= data;
            end
            `LBU: begin

                    d_out <= {{24 {1'b0}}, data[7:0]};
            end
            `LHU: begin  

                d_out <= {{16 {1'b0}}, data[15:0]}; 
            end
            default:
                d_out <= 0;
        endcase
    end
    
    assign dout = d_out;
    
endmodule
module DataExt(
    input wire [2:0] opcode,
    input wire [31:0] data,
    output wire [31:0] dout
    );

    
    reg [31:0] d_out;
    
    always@(*) begin
        case(opcode)
            `LB: begin
                if (data[7]==1)

                    d_out <= {{24 {1'b1}}, data[7:0]};
                else

                    d_out <= {{24 {1'b0}}, data[7:0]};
            end
            `LH: begin 
                if (data[15]==1)

                    d_out <= {{16 {1'b1}}, data[15:0]};
                else

                    d_out <= {{16 {1'b0}}, data[15:0]};    
            end
            `LW: begin       
                d_out <= data;
            end
            `LBU: begin

                    d_out <= {{24 {1'b0}}, data[7:0]};
            end
            `LHU: begin  

                d_out <= {{16 {1'b0}}, data[15:0]}; 
            end
            default:
                d_out <= 0;
        endcase
    end
    
    assign dout = d_out;
    
endmodule