data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/aes/AddRoundKey.v
data/verilator_xmls/5caa8637-a6eb-45eb-b3d1-ec30b81055cf.xml
module AddRoundKey(
x,
y,
z);

	input [127:0] x;
	input [127:0] y;
	output [127:0] z;

	assign z = x ^ y;
	
endmodule
module AddRoundKey(
x,
y,
z);


	input [127:0] x;
	input [127:0] y;
	output [127:0] z;

	assign z = x ^ y;
	
endmodule