data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/multiplier.sv
1: b"%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/multiplier.sv:18: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER\nmodule multiplier import ariane_pkg::*; (\n                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/multiplier.sv:20: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic                     rst_ni,\n    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/multiplier.sv:21: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic [TRANS_ID_BITS-1:0] trans_id_i,\n    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/multiplier.sv:22: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic                     mult_valid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/multiplier.sv:23: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  fu_op                     operator_i,\n    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/multiplier.sv:28: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic                     mult_ready_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/multiplier.sv:29: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic [TRANS_ID_BITS-1:0] mult_trans_id_o\n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/multiplier.sv:30: syntax error, unexpected ')', expecting ',' or ';'\n);\n^\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/multiplier.sv:34: syntax error, unexpected IDENTIFIER\n    fu_op                        operator_d, operator_q;\n    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/multiplier.sv:35: syntax error, unexpected ::, expecting ':'\n    logic [riscv::XLEN*2-1:0] mult_result_d, mult_result_q;\n                ^~\n                                                                                                              : ... Perhaps 'riscv' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/multiplier.sv:42: syntax error, unexpected assign\n    assign mult_valid_o    = mult_valid_q;\n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/multiplier.sv:48: syntax error, unexpected ::, expecting ':'\n    logic [riscv::XLEN*2-1:0] mult_result;\n                ^~\n%Error: Exiting due to 12 error(s)\n"
module multiplier import ariane_pkg::*; (
    input  logic                     clk_i,
    input  logic                     rst_ni,
    input  logic [TRANS_ID_BITS-1:0] trans_id_i,
    input  logic                     mult_valid_i,
    input  fu_op                     operator_i,
    input  riscv::xlen_t             operand_a_i,
    input  riscv::xlen_t             operand_b_i,
    output riscv::xlen_t             result_o,
    output logic                     mult_valid_o,
    output logic                     mult_ready_o,
    output logic [TRANS_ID_BITS-1:0] mult_trans_id_o
);

    logic [TRANS_ID_BITS-1:0]    trans_id_q;
    logic                        mult_valid_q;
    fu_op                        operator_d, operator_q;
    logic [riscv::XLEN*2-1:0] mult_result_d, mult_result_q;


    logic                       sign_a, sign_b;
    logic                       mult_valid;


    assign mult_valid_o    = mult_valid_q;
    assign mult_trans_id_o = trans_id_q;
    assign mult_ready_o    = 1'b1;

    assign mult_valid      = mult_valid_i && (operator_i inside {MUL, MULH, MULHU, MULHSU, MULW});

    logic [riscv::XLEN*2-1:0] mult_result;
    assign mult_result   = $signed({operand_a_i[riscv::XLEN-1] & sign_a, operand_a_i}) * $signed({operand_b_i[riscv::XLEN-1] & sign_b, operand_b_i});


    always_comb begin
        sign_a = 1'b0;
        sign_b = 1'b0;


        if (operator_i == MULH) begin
            sign_a   = 1'b1;
            sign_b   = 1'b1;

        end else if (operator_i == MULHSU) begin
            sign_a   = 1'b1;

        end else begin
            sign_a   = 1'b0;
            sign_b   = 1'b0;
        end
    end



    assign mult_result_d   = $signed({operand_a_i[riscv::XLEN-1] & sign_a, operand_a_i}) *
                             $signed({operand_b_i[riscv::XLEN-1] & sign_b, operand_b_i});


    assign operator_d = operator_i;
    always_comb begin : p_selmux
        unique case (operator_q)
            MULH, MULHU, MULHSU: result_o = mult_result_q[riscv::XLEN*2-1:riscv::XLEN];
            MULW:                result_o = sext32(mult_result_q[31:0]);

            default:             result_o = mult_result_q[riscv::XLEN-1:0];
        endcase
    end




    always_ff @(posedge clk_i or negedge rst_ni) begin
        if (~rst_ni) begin
            mult_valid_q    <= '0;
            trans_id_q      <= '0;
            operator_q      <=  MUL;
            mult_result_q   <= '0;
         end else begin

            trans_id_q   <= trans_id_i;

            mult_valid_q    <= mult_valid;
            operator_q      <= operator_d;
            mult_result_q   <= mult_result_d;
         end
    end
endmodule
module multiplier import ariane_pkg::*;
 (
    input  logic                     clk_i,
    input  logic                     rst_ni,
    input  logic [TRANS_ID_BITS-1:0] trans_id_i,
    input  logic                     mult_valid_i,
    input  fu_op                     operator_i,
    input  riscv::xlen_t             operand_a_i,
    input  riscv::xlen_t             operand_b_i,
    output riscv::xlen_t             result_o,
    output logic                     mult_valid_o,
    output logic                     mult_ready_o,
    output logic [TRANS_ID_BITS-1:0] mult_trans_id_o
);

    logic [TRANS_ID_BITS-1:0]    trans_id_q;
    logic                        mult_valid_q;
    fu_op                        operator_d, operator_q;
    logic [riscv::XLEN*2-1:0] mult_result_d, mult_result_q;


    logic                       sign_a, sign_b;
    logic                       mult_valid;


    assign mult_valid_o    = mult_valid_q;
    assign mult_trans_id_o = trans_id_q;
    assign mult_ready_o    = 1'b1;

    assign mult_valid      = mult_valid_i && (operator_i inside {MUL, MULH, MULHU, MULHSU, MULW});

    logic [riscv::XLEN*2-1:0] mult_result;
    assign mult_result   = $signed({operand_a_i[riscv::XLEN-1] & sign_a, operand_a_i}) * $signed({operand_b_i[riscv::XLEN-1] & sign_b, operand_b_i});


    always_comb begin
        sign_a = 1'b0;
        sign_b = 1'b0;


        if (operator_i == MULH) begin
            sign_a   = 1'b1;
            sign_b   = 1'b1;

        end else if (operator_i == MULHSU) begin
            sign_a   = 1'b1;

        end else begin
            sign_a   = 1'b0;
            sign_b   = 1'b0;
        end
    end



    assign mult_result_d   = $signed({operand_a_i[riscv::XLEN-1] & sign_a, operand_a_i}) *
                             $signed({operand_b_i[riscv::XLEN-1] & sign_b, operand_b_i});


    assign operator_d = operator_i;
    always_comb begin : p_selmux
        unique case (operator_q)
            MULH, MULHU, MULHSU: result_o = mult_result_q[riscv::XLEN*2-1:riscv::XLEN];
            MULW:                result_o = sext32(mult_result_q[31:0]);

            default:             result_o = mult_result_q[riscv::XLEN-1:0];
        endcase
    end




    always_ff @(posedge clk_i or negedge rst_ni) begin
        if (~rst_ni) begin
            mult_valid_q    <= '0;
            trans_id_q      <= '0;
            operator_q      <=  MUL;
            mult_result_q   <= '0;
         end else begin

            trans_id_q   <= trans_id_i;

            mult_valid_q    <= mult_valid;
            operator_q      <= operator_d;
            mult_result_q   <= mult_result_d;
         end
    end
endmodule