data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v
1: b'%Error: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:22: Unsupported: fork statements\ninitial fork\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:26: Unsupported: Ignoring delay on this delayed statement.\n #1 RESET = 0 ; #1 Pcin = 32\'bz ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0   ; #1 RSLCT[7:4] = 0  ; #1 RSLCT[11:8] = 0  ; #1 RSLCT[15:12] = 0  ; #1 RSLCT[19:16] = 0   ; #1 OP=16;#1 FLAGS=0;#1 S=0;#1 ALU_OUT=0;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:26: Unsupported: Ignoring delay on this delayed statement.\n #1 RESET = 0 ; #1 Pcin = 32\'bz ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0   ; #1 RSLCT[7:4] = 0  ; #1 RSLCT[11:8] = 0  ; #1 RSLCT[15:12] = 0  ; #1 RSLCT[19:16] = 0   ; #1 OP=16;#1 FLAGS=0;#1 S=0;#1 ALU_OUT=0;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:26: Unsupported: Ignoring delay on this delayed statement.\n #1 RESET = 0 ; #1 Pcin = 32\'bz ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0   ; #1 RSLCT[7:4] = 0  ; #1 RSLCT[11:8] = 0  ; #1 RSLCT[15:12] = 0  ; #1 RSLCT[19:16] = 0   ; #1 OP=16;#1 FLAGS=0;#1 S=0;#1 ALU_OUT=0;\n                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:26: Unsupported: Ignoring delay on this delayed statement.\n #1 RESET = 0 ; #1 Pcin = 32\'bz ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0   ; #1 RSLCT[7:4] = 0  ; #1 RSLCT[11:8] = 0  ; #1 RSLCT[15:12] = 0  ; #1 RSLCT[19:16] = 0   ; #1 OP=16;#1 FLAGS=0;#1 S=0;#1 ALU_OUT=0;\n                                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:26: Unsupported: Ignoring delay on this delayed statement.\n #1 RESET = 0 ; #1 Pcin = 32\'bz ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0   ; #1 RSLCT[7:4] = 0  ; #1 RSLCT[11:8] = 0  ; #1 RSLCT[15:12] = 0  ; #1 RSLCT[19:16] = 0   ; #1 OP=16;#1 FLAGS=0;#1 S=0;#1 ALU_OUT=0;\n                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:26: Unsupported: Ignoring delay on this delayed statement.\n #1 RESET = 0 ; #1 Pcin = 32\'bz ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0   ; #1 RSLCT[7:4] = 0  ; #1 RSLCT[11:8] = 0  ; #1 RSLCT[15:12] = 0  ; #1 RSLCT[19:16] = 0   ; #1 OP=16;#1 FLAGS=0;#1 S=0;#1 ALU_OUT=0;\n                                                                               ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:26: Unsupported: Ignoring delay on this delayed statement.\n #1 RESET = 0 ; #1 Pcin = 32\'bz ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0   ; #1 RSLCT[7:4] = 0  ; #1 RSLCT[11:8] = 0  ; #1 RSLCT[15:12] = 0  ; #1 RSLCT[19:16] = 0   ; #1 OP=16;#1 FLAGS=0;#1 S=0;#1 ALU_OUT=0;\n                                                                                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:26: Unsupported: Ignoring delay on this delayed statement.\n #1 RESET = 0 ; #1 Pcin = 32\'bz ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0   ; #1 RSLCT[7:4] = 0  ; #1 RSLCT[11:8] = 0  ; #1 RSLCT[15:12] = 0  ; #1 RSLCT[19:16] = 0   ; #1 OP=16;#1 FLAGS=0;#1 S=0;#1 ALU_OUT=0;\n                                                                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:26: Unsupported: Ignoring delay on this delayed statement.\n #1 RESET = 0 ; #1 Pcin = 32\'bz ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0   ; #1 RSLCT[7:4] = 0  ; #1 RSLCT[11:8] = 0  ; #1 RSLCT[15:12] = 0  ; #1 RSLCT[19:16] = 0   ; #1 OP=16;#1 FLAGS=0;#1 S=0;#1 ALU_OUT=0;\n                                                                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:26: Unsupported: Ignoring delay on this delayed statement.\n #1 RESET = 0 ; #1 Pcin = 32\'bz ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0   ; #1 RSLCT[7:4] = 0  ; #1 RSLCT[11:8] = 0  ; #1 RSLCT[15:12] = 0  ; #1 RSLCT[19:16] = 0   ; #1 OP=16;#1 FLAGS=0;#1 S=0;#1 ALU_OUT=0;\n                                                                                                                                                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:26: Unsupported: Ignoring delay on this delayed statement.\n #1 RESET = 0 ; #1 Pcin = 32\'bz ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0   ; #1 RSLCT[7:4] = 0  ; #1 RSLCT[11:8] = 0  ; #1 RSLCT[15:12] = 0  ; #1 RSLCT[19:16] = 0   ; #1 OP=16;#1 FLAGS=0;#1 S=0;#1 ALU_OUT=0;\n                                                                                                                                                                                               ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:26: Unsupported: Ignoring delay on this delayed statement.\n #1 RESET = 0 ; #1 Pcin = 32\'bz ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0   ; #1 RSLCT[7:4] = 0  ; #1 RSLCT[11:8] = 0  ; #1 RSLCT[15:12] = 0  ; #1 RSLCT[19:16] = 0   ; #1 OP=16;#1 FLAGS=0;#1 S=0;#1 ALU_OUT=0;\n                                                                                                                                                                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:26: Unsupported: Ignoring delay on this delayed statement.\n #1 RESET = 0 ; #1 Pcin = 32\'bz ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0   ; #1 RSLCT[7:4] = 0  ; #1 RSLCT[11:8] = 0  ; #1 RSLCT[15:12] = 0  ; #1 RSLCT[19:16] = 0   ; #1 OP=16;#1 FLAGS=0;#1 S=0;#1 ALU_OUT=0;\n                                                                                                                                                                                                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:26: Unsupported: Ignoring delay on this delayed statement.\n #1 RESET = 0 ; #1 Pcin = 32\'bz ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0   ; #1 RSLCT[7:4] = 0  ; #1 RSLCT[11:8] = 0  ; #1 RSLCT[15:12] = 0  ; #1 RSLCT[19:16] = 0   ; #1 OP=16;#1 FLAGS=0;#1 S=0;#1 ALU_OUT=0;\n                                                                                                                                                                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:28: Unsupported: Ignoring delay on this delayed statement.\n #2 Pcin = 32\'bz ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ; #2 RSLCT[3:0] = 0   ; #2 RSLCT[7:4] = 0  ; #2 RSLCT[11:8] = 0  ; #2 RSLCT[15:12] = 0  ; #2 RSLCT[19:16] = 0   ; #2 OP=17; #2 FLAGS=0;#2 S=1; #2 ALU_OUT=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:28: Unsupported: Ignoring delay on this delayed statement.\n #2 Pcin = 32\'bz ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ; #2 RSLCT[3:0] = 0   ; #2 RSLCT[7:4] = 0  ; #2 RSLCT[11:8] = 0  ; #2 RSLCT[15:12] = 0  ; #2 RSLCT[19:16] = 0   ; #2 OP=17; #2 FLAGS=0;#2 S=1; #2 ALU_OUT=1;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:28: Unsupported: Ignoring delay on this delayed statement.\n #2 Pcin = 32\'bz ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ; #2 RSLCT[3:0] = 0   ; #2 RSLCT[7:4] = 0  ; #2 RSLCT[11:8] = 0  ; #2 RSLCT[15:12] = 0  ; #2 RSLCT[19:16] = 0   ; #2 OP=17; #2 FLAGS=0;#2 S=1; #2 ALU_OUT=1;\n                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:28: Unsupported: Ignoring delay on this delayed statement.\n #2 Pcin = 32\'bz ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ; #2 RSLCT[3:0] = 0   ; #2 RSLCT[7:4] = 0  ; #2 RSLCT[11:8] = 0  ; #2 RSLCT[15:12] = 0  ; #2 RSLCT[19:16] = 0   ; #2 OP=17; #2 FLAGS=0;#2 S=1; #2 ALU_OUT=1;\n                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:28: Unsupported: Ignoring delay on this delayed statement.\n #2 Pcin = 32\'bz ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ; #2 RSLCT[3:0] = 0   ; #2 RSLCT[7:4] = 0  ; #2 RSLCT[11:8] = 0  ; #2 RSLCT[15:12] = 0  ; #2 RSLCT[19:16] = 0   ; #2 OP=17; #2 FLAGS=0;#2 S=1; #2 ALU_OUT=1;\n                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:28: Unsupported: Ignoring delay on this delayed statement.\n #2 Pcin = 32\'bz ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ; #2 RSLCT[3:0] = 0   ; #2 RSLCT[7:4] = 0  ; #2 RSLCT[11:8] = 0  ; #2 RSLCT[15:12] = 0  ; #2 RSLCT[19:16] = 0   ; #2 OP=17; #2 FLAGS=0;#2 S=1; #2 ALU_OUT=1;\n                                                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:28: Unsupported: Ignoring delay on this delayed statement.\n #2 Pcin = 32\'bz ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ; #2 RSLCT[3:0] = 0   ; #2 RSLCT[7:4] = 0  ; #2 RSLCT[11:8] = 0  ; #2 RSLCT[15:12] = 0  ; #2 RSLCT[19:16] = 0   ; #2 OP=17; #2 FLAGS=0;#2 S=1; #2 ALU_OUT=1;\n                                                                                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:28: Unsupported: Ignoring delay on this delayed statement.\n #2 Pcin = 32\'bz ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ; #2 RSLCT[3:0] = 0   ; #2 RSLCT[7:4] = 0  ; #2 RSLCT[11:8] = 0  ; #2 RSLCT[15:12] = 0  ; #2 RSLCT[19:16] = 0   ; #2 OP=17; #2 FLAGS=0;#2 S=1; #2 ALU_OUT=1;\n                                                                                                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:28: Unsupported: Ignoring delay on this delayed statement.\n #2 Pcin = 32\'bz ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ; #2 RSLCT[3:0] = 0   ; #2 RSLCT[7:4] = 0  ; #2 RSLCT[11:8] = 0  ; #2 RSLCT[15:12] = 0  ; #2 RSLCT[19:16] = 0   ; #2 OP=17; #2 FLAGS=0;#2 S=1; #2 ALU_OUT=1;\n                                                                                                                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:28: Unsupported: Ignoring delay on this delayed statement.\n #2 Pcin = 32\'bz ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ; #2 RSLCT[3:0] = 0   ; #2 RSLCT[7:4] = 0  ; #2 RSLCT[11:8] = 0  ; #2 RSLCT[15:12] = 0  ; #2 RSLCT[19:16] = 0   ; #2 OP=17; #2 FLAGS=0;#2 S=1; #2 ALU_OUT=1;\n                                                                                                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:28: Unsupported: Ignoring delay on this delayed statement.\n #2 Pcin = 32\'bz ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ; #2 RSLCT[3:0] = 0   ; #2 RSLCT[7:4] = 0  ; #2 RSLCT[11:8] = 0  ; #2 RSLCT[15:12] = 0  ; #2 RSLCT[19:16] = 0   ; #2 OP=17; #2 FLAGS=0;#2 S=1; #2 ALU_OUT=1;\n                                                                                                                                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:28: Unsupported: Ignoring delay on this delayed statement.\n #2 Pcin = 32\'bz ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ; #2 RSLCT[3:0] = 0   ; #2 RSLCT[7:4] = 0  ; #2 RSLCT[11:8] = 0  ; #2 RSLCT[15:12] = 0  ; #2 RSLCT[19:16] = 0   ; #2 OP=17; #2 FLAGS=0;#2 S=1; #2 ALU_OUT=1;\n                                                                                                                                                                                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:28: Unsupported: Ignoring delay on this delayed statement.\n #2 Pcin = 32\'bz ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ; #2 RSLCT[3:0] = 0   ; #2 RSLCT[7:4] = 0  ; #2 RSLCT[11:8] = 0  ; #2 RSLCT[15:12] = 0  ; #2 RSLCT[19:16] = 0   ; #2 OP=17; #2 FLAGS=0;#2 S=1; #2 ALU_OUT=1;\n                                                                                                                                                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:30: Unsupported: Ignoring delay on this delayed statement.\n #3 RESET = 0 ; #3 Pcin = 32\'bz ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0   ; #3 RSLCT[7:4] = 0  ; #3 RSLCT[11:8] = 0  ; #3 RSLCT[15:12] = 0  ; #3 RSLCT[19:16] = 0   ; #3 OP=17;#3 FLAGS=0;#3 S=1;#3 ALU_OUT=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:30: Unsupported: Ignoring delay on this delayed statement.\n #3 RESET = 0 ; #3 Pcin = 32\'bz ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0   ; #3 RSLCT[7:4] = 0  ; #3 RSLCT[11:8] = 0  ; #3 RSLCT[15:12] = 0  ; #3 RSLCT[19:16] = 0   ; #3 OP=17;#3 FLAGS=0;#3 S=1;#3 ALU_OUT=1;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:30: Unsupported: Ignoring delay on this delayed statement.\n #3 RESET = 0 ; #3 Pcin = 32\'bz ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0   ; #3 RSLCT[7:4] = 0  ; #3 RSLCT[11:8] = 0  ; #3 RSLCT[15:12] = 0  ; #3 RSLCT[19:16] = 0   ; #3 OP=17;#3 FLAGS=0;#3 S=1;#3 ALU_OUT=1;\n                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:30: Unsupported: Ignoring delay on this delayed statement.\n #3 RESET = 0 ; #3 Pcin = 32\'bz ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0   ; #3 RSLCT[7:4] = 0  ; #3 RSLCT[11:8] = 0  ; #3 RSLCT[15:12] = 0  ; #3 RSLCT[19:16] = 0   ; #3 OP=17;#3 FLAGS=0;#3 S=1;#3 ALU_OUT=1;\n                                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:30: Unsupported: Ignoring delay on this delayed statement.\n #3 RESET = 0 ; #3 Pcin = 32\'bz ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0   ; #3 RSLCT[7:4] = 0  ; #3 RSLCT[11:8] = 0  ; #3 RSLCT[15:12] = 0  ; #3 RSLCT[19:16] = 0   ; #3 OP=17;#3 FLAGS=0;#3 S=1;#3 ALU_OUT=1;\n                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:30: Unsupported: Ignoring delay on this delayed statement.\n #3 RESET = 0 ; #3 Pcin = 32\'bz ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0   ; #3 RSLCT[7:4] = 0  ; #3 RSLCT[11:8] = 0  ; #3 RSLCT[15:12] = 0  ; #3 RSLCT[19:16] = 0   ; #3 OP=17;#3 FLAGS=0;#3 S=1;#3 ALU_OUT=1;\n                                                                               ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:30: Unsupported: Ignoring delay on this delayed statement.\n #3 RESET = 0 ; #3 Pcin = 32\'bz ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0   ; #3 RSLCT[7:4] = 0  ; #3 RSLCT[11:8] = 0  ; #3 RSLCT[15:12] = 0  ; #3 RSLCT[19:16] = 0   ; #3 OP=17;#3 FLAGS=0;#3 S=1;#3 ALU_OUT=1;\n                                                                                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:30: Unsupported: Ignoring delay on this delayed statement.\n #3 RESET = 0 ; #3 Pcin = 32\'bz ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0   ; #3 RSLCT[7:4] = 0  ; #3 RSLCT[11:8] = 0  ; #3 RSLCT[15:12] = 0  ; #3 RSLCT[19:16] = 0   ; #3 OP=17;#3 FLAGS=0;#3 S=1;#3 ALU_OUT=1;\n                                                                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:30: Unsupported: Ignoring delay on this delayed statement.\n #3 RESET = 0 ; #3 Pcin = 32\'bz ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0   ; #3 RSLCT[7:4] = 0  ; #3 RSLCT[11:8] = 0  ; #3 RSLCT[15:12] = 0  ; #3 RSLCT[19:16] = 0   ; #3 OP=17;#3 FLAGS=0;#3 S=1;#3 ALU_OUT=1;\n                                                                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:30: Unsupported: Ignoring delay on this delayed statement.\n #3 RESET = 0 ; #3 Pcin = 32\'bz ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0   ; #3 RSLCT[7:4] = 0  ; #3 RSLCT[11:8] = 0  ; #3 RSLCT[15:12] = 0  ; #3 RSLCT[19:16] = 0   ; #3 OP=17;#3 FLAGS=0;#3 S=1;#3 ALU_OUT=1;\n                                                                                                                                                                       ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:30: Unsupported: Ignoring delay on this delayed statement.\n #3 RESET = 0 ; #3 Pcin = 32\'bz ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0   ; #3 RSLCT[7:4] = 0  ; #3 RSLCT[11:8] = 0  ; #3 RSLCT[15:12] = 0  ; #3 RSLCT[19:16] = 0   ; #3 OP=17;#3 FLAGS=0;#3 S=1;#3 ALU_OUT=1;\n                                                                                                                                                                                               ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:30: Unsupported: Ignoring delay on this delayed statement.\n #3 RESET = 0 ; #3 Pcin = 32\'bz ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0   ; #3 RSLCT[7:4] = 0  ; #3 RSLCT[11:8] = 0  ; #3 RSLCT[15:12] = 0  ; #3 RSLCT[19:16] = 0   ; #3 OP=17;#3 FLAGS=0;#3 S=1;#3 ALU_OUT=1;\n                                                                                                                                                                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:30: Unsupported: Ignoring delay on this delayed statement.\n #3 RESET = 0 ; #3 Pcin = 32\'bz ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0   ; #3 RSLCT[7:4] = 0  ; #3 RSLCT[11:8] = 0  ; #3 RSLCT[15:12] = 0  ; #3 RSLCT[19:16] = 0   ; #3 OP=17;#3 FLAGS=0;#3 S=1;#3 ALU_OUT=1;\n                                                                                                                                                                                                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:30: Unsupported: Ignoring delay on this delayed statement.\n #3 RESET = 0 ; #3 Pcin = 32\'bz ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0   ; #3 RSLCT[7:4] = 0  ; #3 RSLCT[11:8] = 0  ; #3 RSLCT[15:12] = 0  ; #3 RSLCT[19:16] = 0   ; #3 OP=17;#3 FLAGS=0;#3 S=1;#3 ALU_OUT=1;\n                                                                                                                                                                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:32: Unsupported: Ignoring delay on this delayed statement.\n #4 Pcin = 32\'bz ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ; #4 RSLCT[3:0] = 0   ; #4 RSLCT[7:4] = 0  ; #4 RSLCT[11:8] = 0  ; #4 RSLCT[15:12] = 1  ; #4 RSLCT[19:16] = 0   ; #4 OP=16; #4 FLAGS=0;#4 S=1; #4 ALU_OUT=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:32: Unsupported: Ignoring delay on this delayed statement.\n #4 Pcin = 32\'bz ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ; #4 RSLCT[3:0] = 0   ; #4 RSLCT[7:4] = 0  ; #4 RSLCT[11:8] = 0  ; #4 RSLCT[15:12] = 1  ; #4 RSLCT[19:16] = 0   ; #4 OP=16; #4 FLAGS=0;#4 S=1; #4 ALU_OUT=1;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:32: Unsupported: Ignoring delay on this delayed statement.\n #4 Pcin = 32\'bz ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ; #4 RSLCT[3:0] = 0   ; #4 RSLCT[7:4] = 0  ; #4 RSLCT[11:8] = 0  ; #4 RSLCT[15:12] = 1  ; #4 RSLCT[19:16] = 0   ; #4 OP=16; #4 FLAGS=0;#4 S=1; #4 ALU_OUT=1;\n                                   ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:32: Unsupported: Ignoring delay on this delayed statement.\n #4 Pcin = 32\'bz ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ; #4 RSLCT[3:0] = 0   ; #4 RSLCT[7:4] = 0  ; #4 RSLCT[11:8] = 0  ; #4 RSLCT[15:12] = 1  ; #4 RSLCT[19:16] = 0   ; #4 OP=16; #4 FLAGS=0;#4 S=1; #4 ALU_OUT=1;\n                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:32: Unsupported: Ignoring delay on this delayed statement.\n #4 Pcin = 32\'bz ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ; #4 RSLCT[3:0] = 0   ; #4 RSLCT[7:4] = 0  ; #4 RSLCT[11:8] = 0  ; #4 RSLCT[15:12] = 1  ; #4 RSLCT[19:16] = 0   ; #4 OP=16; #4 FLAGS=0;#4 S=1; #4 ALU_OUT=1;\n                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:32: Unsupported: Ignoring delay on this delayed statement.\n #4 Pcin = 32\'bz ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ; #4 RSLCT[3:0] = 0   ; #4 RSLCT[7:4] = 0  ; #4 RSLCT[11:8] = 0  ; #4 RSLCT[15:12] = 1  ; #4 RSLCT[19:16] = 0   ; #4 OP=16; #4 FLAGS=0;#4 S=1; #4 ALU_OUT=1;\n                                                                                      ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:32: Unsupported: Ignoring delay on this delayed statement.\n #4 Pcin = 32\'bz ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ; #4 RSLCT[3:0] = 0   ; #4 RSLCT[7:4] = 0  ; #4 RSLCT[11:8] = 0  ; #4 RSLCT[15:12] = 1  ; #4 RSLCT[19:16] = 0   ; #4 OP=16; #4 FLAGS=0;#4 S=1; #4 ALU_OUT=1;\n                                                                                                           ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:32: Unsupported: Ignoring delay on this delayed statement.\n #4 Pcin = 32\'bz ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ; #4 RSLCT[3:0] = 0   ; #4 RSLCT[7:4] = 0  ; #4 RSLCT[11:8] = 0  ; #4 RSLCT[15:12] = 1  ; #4 RSLCT[19:16] = 0   ; #4 OP=16; #4 FLAGS=0;#4 S=1; #4 ALU_OUT=1;\n                                                                                                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:32: Unsupported: Ignoring delay on this delayed statement.\n #4 Pcin = 32\'bz ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ; #4 RSLCT[3:0] = 0   ; #4 RSLCT[7:4] = 0  ; #4 RSLCT[11:8] = 0  ; #4 RSLCT[15:12] = 1  ; #4 RSLCT[19:16] = 0   ; #4 OP=16; #4 FLAGS=0;#4 S=1; #4 ALU_OUT=1;\n                                                                                                                                                        ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:32: Unsupported: Ignoring delay on this delayed statement.\n #4 Pcin = 32\'bz ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ; #4 RSLCT[3:0] = 0   ; #4 RSLCT[7:4] = 0  ; #4 RSLCT[11:8] = 0  ; #4 RSLCT[15:12] = 1  ; #4 RSLCT[19:16] = 0   ; #4 OP=16; #4 FLAGS=0;#4 S=1; #4 ALU_OUT=1;\n                                                                                                                                                                                ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:32: Unsupported: Ignoring delay on this delayed statement.\n #4 Pcin = 32\'bz ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ; #4 RSLCT[3:0] = 0   ; #4 RSLCT[7:4] = 0  ; #4 RSLCT[11:8] = 0  ; #4 RSLCT[15:12] = 1  ; #4 RSLCT[19:16] = 0   ; #4 OP=16; #4 FLAGS=0;#4 S=1; #4 ALU_OUT=1;\n                                                                                                                                                                                          ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:32: Unsupported: Ignoring delay on this delayed statement.\n #4 Pcin = 32\'bz ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ; #4 RSLCT[3:0] = 0   ; #4 RSLCT[7:4] = 0  ; #4 RSLCT[11:8] = 0  ; #4 RSLCT[15:12] = 1  ; #4 RSLCT[19:16] = 0   ; #4 OP=16; #4 FLAGS=0;#4 S=1; #4 ALU_OUT=1;\n                                                                                                                                                                                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:32: Unsupported: Ignoring delay on this delayed statement.\n #4 Pcin = 32\'bz ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ; #4 RSLCT[3:0] = 0   ; #4 RSLCT[7:4] = 0  ; #4 RSLCT[11:8] = 0  ; #4 RSLCT[15:12] = 1  ; #4 RSLCT[19:16] = 0   ; #4 OP=16; #4 FLAGS=0;#4 S=1; #4 ALU_OUT=1;\n                                                                                                                                                                                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:36: Unsupported: Ignoring delay on this delayed statement.\n #1 Clk = ~Clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:38: Unsupported: Ignoring delay on this delayed statement.\ninitial #sim_time $finish; \n        ^\n%Error: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:41: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("prefab_alu_rf.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:42: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,prefab_alu_rf);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/PreFab_ALU+RF/prefab_alu_rf.v:44: Unsupported or unknown PLI call: $monitor\n $monitor("time = %3d ,Pcin = %3d , in = %3d , LOADPC = %3d , LOAD = %3d , IR_CU = %3d , RSLCT = %3h, Rn = %3d ,Rm = %3d ,Rs = %3d ,PCout = %3d,OP=%3d;FLAGS=0; S=%1b;ALU_OUT=%1b;",$time,Pcin, in, LOADPC, LOAD, IR_CU, RSLCT,Rn,Rm,Rs,PCout,OP,FLAGS,S,ALU_OUT);\n ^~~~~~~~\n%Error: Exiting due to 4 error(s), 56 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module prefab_alu_rf;

parameter sim_time = 750*2;

reg [31:0] Pcin;
reg [19:0] RSLCT;
reg Clk, RESET, LOADPC, LOAD,IR_CU;
wire [31:0] Rn,Rm,Rs,PCout,in;

RegisterFile RF(in,Pcin,RSLCT,Clk, RESET, LOADPC, LOAD,IR_CU, Rn,Rm,Rs,PCout);


reg [4:0] OP;
reg [3:0] FLAGS;
reg S,ALU_OUT;
wire [31:0] Out;
wire [3:0] FLAGS_OUT;


ARM_ALU alu(Rn,Rm, OP, FLAGS, in,FLAGS_OUT,S,ALU_OUT);

initial fork

	Clk = 0 ; RESET = 1 ; Pcin = 32'bz ;  LOADPC = 0 ; LOAD = 0 ;IR_CU = 1 ; RSLCT[3:0] = 0 ; RSLCT[7:4] = 0 ; RSLCT[11:8] = 0 ; RSLCT[15:12] = 0 ; RSLCT[19:16] = 0 ; OP=17; FLAGS=0; S=1;ALU_OUT=1;

	#1 RESET = 0 ; #1 Pcin = 32'bz ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0; #1 RSLCT[7:4] = 0; #1 RSLCT[11:8] = 0; #1 RSLCT[15:12] = 0; #1 RSLCT[19:16] = 0; #1 OP=16;#1 FLAGS=0;#1 S=0;#1 ALU_OUT=0;

	#2 Pcin = 32'bz ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ; #2 RSLCT[3:0] = 0; #2 RSLCT[7:4] = 0; #2 RSLCT[11:8] = 0; #2 RSLCT[15:12] = 0; #2 RSLCT[19:16] = 0; #2 OP=17; #2 FLAGS=0;#2 S=1; #2 ALU_OUT=1;

	#3 RESET = 0 ; #3 Pcin = 32'bz ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0; #3 RSLCT[7:4] = 0; #3 RSLCT[11:8] = 0; #3 RSLCT[15:12] = 0; #3 RSLCT[19:16] = 0; #3 OP=17;#3 FLAGS=0;#3 S=1;#3 ALU_OUT=1;

	#4 Pcin = 32'bz ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ; #4 RSLCT[3:0] = 0; #4 RSLCT[7:4] = 0; #4 RSLCT[11:8] = 0; #4 RSLCT[15:12] = 1; #4 RSLCT[19:16] = 0; #4 OP=16; #4 FLAGS=0;#4 S=1; #4 ALU_OUT=1;
join

always 
	#1 Clk = ~Clk;
	
initial #sim_time $finish; 

initial begin
	$dumpfile("prefab_alu_rf.vcd");
	$dumpvars(0,prefab_alu_rf);
	$display(" Test Results" );
	$monitor("time = %3d ,Pcin = %3d , in = %3d , LOADPC = %3d , LOAD = %3d , IR_CU = %3d , RSLCT = %3h, Rn = %3d ,Rm = %3d ,Rs = %3d ,PCout = %3d,OP=%3d;FLAGS=0; S=%1b;ALU_OUT=%1b;",$time,Pcin, in, LOADPC, LOAD, IR_CU, RSLCT,Rn,Rm,Rs,PCout,OP,FLAGS,S,ALU_OUT);
end

endmodule
module prefab_alu_rf;


parameter sim_time = 750*2;

reg [31:0] Pcin;
reg [19:0] RSLCT;
reg Clk, RESET, LOADPC, LOAD,IR_CU;
wire [31:0] Rn,Rm,Rs,PCout,in;

RegisterFile RF(in,Pcin,RSLCT,Clk, RESET, LOADPC, LOAD,IR_CU, Rn,Rm,Rs,PCout);


reg [4:0] OP;
reg [3:0] FLAGS;
reg S,ALU_OUT;
wire [31:0] Out;
wire [3:0] FLAGS_OUT;


ARM_ALU alu(Rn,Rm, OP, FLAGS, in,FLAGS_OUT,S,ALU_OUT);

initial fork

	Clk = 0 ; RESET = 1 ; Pcin = 32'bz ;  LOADPC = 0 ; LOAD = 0 ;IR_CU = 1 ; RSLCT[3:0] = 0 ; RSLCT[7:4] = 0 ; RSLCT[11:8] = 0 ; RSLCT[15:12] = 0 ; RSLCT[19:16] = 0 ; OP=17; FLAGS=0; S=1;ALU_OUT=1;

	#1 RESET = 0 ; #1 Pcin = 32'bz ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0; #1 RSLCT[7:4] = 0; #1 RSLCT[11:8] = 0; #1 RSLCT[15:12] = 0; #1 RSLCT[19:16] = 0; #1 OP=16;#1 FLAGS=0;#1 S=0;#1 ALU_OUT=0;

	#2 Pcin = 32'bz ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 1 ; #2 RSLCT[3:0] = 0; #2 RSLCT[7:4] = 0; #2 RSLCT[11:8] = 0; #2 RSLCT[15:12] = 0; #2 RSLCT[19:16] = 0; #2 OP=17; #2 FLAGS=0;#2 S=1; #2 ALU_OUT=1;

	#3 RESET = 0 ; #3 Pcin = 32'bz ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0; #3 RSLCT[7:4] = 0; #3 RSLCT[11:8] = 0; #3 RSLCT[15:12] = 0; #3 RSLCT[19:16] = 0; #3 OP=17;#3 FLAGS=0;#3 S=1;#3 ALU_OUT=1;

	#4 Pcin = 32'bz ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 1 ; #4 RSLCT[3:0] = 0; #4 RSLCT[7:4] = 0; #4 RSLCT[11:8] = 0; #4 RSLCT[15:12] = 1; #4 RSLCT[19:16] = 0; #4 OP=16; #4 FLAGS=0;#4 S=1; #4 ALU_OUT=1;
join

always 
	#1 Clk = ~Clk;
	
initial #sim_time $finish; 

initial begin
	$dumpfile("prefab_alu_rf.vcd");
	$dumpvars(0,prefab_alu_rf);
	$display(" Test Results" );
	$monitor("time = %3d ,Pcin = %3d , in = %3d , LOADPC = %3d , LOAD = %3d , IR_CU = %3d , RSLCT = %3h, Rn = %3d ,Rm = %3d ,Rs = %3d ,PCout = %3d,OP=%3d;FLAGS=0; S=%1b;ALU_OUT=%1b;",$time,Pcin, in, LOADPC, LOAD, IR_CU, RSLCT,Rn,Rm,Rs,PCout,OP,FLAGS,S,ALU_OUT);
end

endmodule