data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/src/stream_join.sv
1: b'%Warning-LITENDIAN: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/src/stream_join.sv:22: Little bit endian vector: MSB < LSB of bit range: -1:0\n  input  logic  [N_INP-1:0] inp_valid_i,\n                ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/src/stream_join.sv:24: Little bit endian vector: MSB < LSB of bit range: -1:0\n  output logic  [N_INP-1:0] inp_ready_o,\n                ^\n%Error: Exiting due to 2 warning(s)\n'
module stream_join #(

  parameter int unsigned N_INP = 32'd0
) (

  input  logic  [N_INP-1:0] inp_valid_i,

  output logic  [N_INP-1:0] inp_ready_o,

  output logic              oup_valid_o,

  input  logic              oup_ready_i
);

  assign oup_valid_o = (&inp_valid_i);
  for (genvar i = 0; i < N_INP; i++) begin : gen_inp_ready
    assign inp_ready_o[i] = oup_valid_o & oup_ready_i;
  end


`ifndef VERILATOR
  initial begin: p_assertions
    assert (N_INP >= 1) else $fatal(1, "N_INP must be at least 1!");
  end
`endif

endmodule
module stream_join #(

  parameter int unsigned N_INP = 32'd0
) (

  input  logic  [N_INP-1:0] inp_valid_i,

  output logic  [N_INP-1:0] inp_ready_o,

  output logic              oup_valid_o,

  input  logic              oup_ready_i
);


  assign oup_valid_o = (&inp_valid_i);
  for (genvar i = 0; i < N_INP; i++) begin : gen_inp_ready
    assign inp_ready_o[i] = oup_valid_o & oup_ready_i;
  end


`ifndef VERILATOR
  initial begin: p_assertions
    assert (N_INP >= 1) else $fatal(1, "N_INP must be at least 1!");
  end
`endif

endmodule