data/full_repos/permissive/416882019/src/wb_openram_wrapper.v
1: b"%Error: data/full_repos/permissive/416882019/src/wb_openram_wrapper.v:97: Cannot find file containing module: 'register_rw'\nregister_rw \n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/416882019/src,data/full_repos/permissive/416882019/register_rw\n             data/full_repos/permissive/416882019/src,data/full_repos/permissive/416882019/register_rw.v\n             data/full_repos/permissive/416882019/src,data/full_repos/permissive/416882019/register_rw.sv\n             register_rw\n             register_rw.v\n             register_rw.sv\n             obj_dir/register_rw\n             obj_dir/register_rw.v\n             obj_dir/register_rw.sv\n%Error: data/full_repos/permissive/416882019/src/wb_openram_wrapper.v:132: Cannot find file containing module: 'wb_port_control'\nwb_port_control\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/416882019/src/wb_openram_wrapper.v:184: Cannot find file containing module: 'wb_port_control'\nwb_port_control \n^~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module wb_openram_wrapper 
#(
    parameter RAM_ADDR_WIDTH = 8
)
(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input           		    writable_port_req,



    input           		    wb_a_clk_i,
    input           		    wb_a_rst_i,
    input           		    wbs_a_stb_i,
    input           		    wbs_a_cyc_i,
    input           		    wbs_a_we_i,
    input   [3:0]   		    wbs_a_sel_i,
    input   [31:0]  		    wbs_a_dat_i,
    input   [RAM_ADDR_WIDTH+2:0]  	wbs_a_adr_i,
    output          		    wbs_a_ack_o,
    output  [31:0]  		    wbs_a_dat_o,


    input           		    wb_b_clk_i,
    input           		    wb_b_rst_i,
    input           		    wbs_b_stb_i,
    input           		    wbs_b_cyc_i,
    input           		    wbs_b_we_i,
    input   [3:0]   		    wbs_b_sel_i,
    input   [31:0]  		    wbs_b_dat_i,
    input   [RAM_ADDR_WIDTH+1:0] 	wbs_b_adr_i,
    output          		    wbs_b_ack_o,
    output  [31:0]  		    wbs_b_dat_o,



    output                          ram_clk0,
    output                          ram_csb0,
    output                          ram_web0,
    output  [3:0]              	    ram_wmask0,
    output  [RAM_ADDR_WIDTH-1:0]    ram_addr0,
    output  [31:0]                  ram_din0,
    input   [31:0]                  ram_dout0,
    

    output                          ram_clk1,
    output                          ram_csb1,
    output  [RAM_ADDR_WIDTH-1:0]    ram_addr1,  
    input   [31:0]                  ram_dout1
);

reg writable_port_req_r;

always @(negedge wb_a_clk_i) begin
    if (wb_a_rst_i) begin
	writable_port_req_r <= 0;
    end else begin
	writable_port_req_r <= writable_port_req;
    end
end




wire wbs_a_csr;
assign wbs_a_csr = wbs_a_adr_i[RAM_ADDR_WIDTH+2] == 0;


wire [3:0] port0_lat_prefetch;
wire [3:0] port0_lat_read;

wire [3:0] port1_lat_prefetch;
wire [3:0] port1_lat_read;

register_rw 
#(
    .WIDTH(16),	
    .DEFAULT_VALUE(16'h2222)
)
latency_reg
(
    .rst        (wb_a_rst_i),
    .clk        (wb_a_clk_i),
    .wren       ( wbs_a_cyc_i & wbs_a_stb_i & wbs_a_we_i & wbs_a_csr ),
    .data_in    ( {wbs_a_dat_i[27:24], wbs_a_dat_i[19:16], wbs_a_dat_i[11:8], wbs_a_dat_i[3:0]} ),
    .data_out   ( {port1_lat_prefetch, port1_lat_read, port0_lat_prefetch, port0_lat_read} )
);


wire port0_clk_i;
wire port0_rst_i;
wire port0_stb_i;
wire port0_cyc_i;
wire port0_we_i;
wire port0_ack_o;
wire [31:0] port0_dat_o;


assign port0_clk_i = writable_port_req_r ? wb_b_clk_i : wb_a_clk_i;
assign port0_rst_i = writable_port_req_r ? wb_b_rst_i : wb_a_rst_i;
assign port0_stb_i = writable_port_req_r ? wbs_b_stb_i : (wbs_a_stb_i & !wbs_a_csr);
assign port0_cyc_i = writable_port_req_r ? wbs_b_cyc_i : (wbs_a_cyc_i & !wbs_a_csr);
assign port0_we_i = writable_port_req_r ? wbs_b_we_i : wbs_a_we_i;


assign ram_wmask0 = writable_port_req_r ? wbs_b_sel_i : wbs_a_sel_i;
assign ram_addr0 = writable_port_req_r ? wbs_b_adr_i[RAM_ADDR_WIDTH+1:2] : wbs_a_adr_i[RAM_ADDR_WIDTH+1:2];
assign ram_din0 = writable_port_req_r ? wbs_b_dat_i : wbs_a_dat_i;

wb_port_control
#(
    .READ_ONLY(0),
    .LATENCY_CNTR_WIDTH(4)
) port0_rw
(
`ifdef USE_POWER_PINS
    .vccd1 (vccd1),
    .vssd1 (vssd1),
`endif


    .prefetch_cycles (port0_lat_prefetch),
    .read_cycles    (port0_lat_read),


    .wb_clk_i       (port0_clk_i),
    .wb_rst_i       (port0_rst_i),
    .wbs_stb_i      (port0_stb_i),
    .wbs_cyc_i      (port0_cyc_i),
    .wbs_we_i       (port0_we_i),
    .wbs_ack_o      (port0_ack_o),
    .wbs_dat_o      (port0_dat_o),


    .ram_clk        (ram_clk0),
    .ram_csb        (ram_csb0),
    .ram_web        (ram_web0),
    .ram_dout       (ram_dout0)
);




wire port1_clk_i;
wire port1_rst_i;
wire port1_stb_i;
wire port1_cyc_i;
wire port1_we_i;
wire port1_ack_o;
wire [31:0] port1_dat_o;


assign port1_clk_i = writable_port_req_r ? wb_a_clk_i : wb_b_clk_i;
assign port1_rst_i = writable_port_req_r ? wb_a_rst_i : wb_b_rst_i;
assign port1_stb_i = writable_port_req_r ? (wbs_a_stb_i & !wbs_a_csr) : wbs_b_stb_i;
assign port1_cyc_i = writable_port_req_r ? (wbs_a_cyc_i & !wbs_a_csr) : wbs_b_cyc_i;
assign port1_we_i = writable_port_req_r ? wbs_a_we_i : wbs_b_we_i;


assign ram_addr1 = writable_port_req_r ? wbs_a_adr_i[RAM_ADDR_WIDTH+1:2] : wbs_b_adr_i[RAM_ADDR_WIDTH+1:2];

wb_port_control 
#(
    .READ_ONLY(1),
    .LATENCY_CNTR_WIDTH(4)
) port1_r
(
`ifdef USE_POWER_PINS
    .vccd1 (vccd1),
    .vssd1 (vssd1),
`endif


    .prefetch_cycles (port1_lat_prefetch),
    .read_cycles    (port1_lat_read),


    .wb_clk_i       (port1_clk_i),
    .wb_rst_i       (port1_rst_i),
    .wbs_stb_i      (port1_stb_i),
    .wbs_cyc_i      (port1_cyc_i),
    .wbs_we_i       (port1_we_i),
    .wbs_ack_o      (port1_ack_o),
    .wbs_dat_o      (port1_dat_o),


    .ram_clk        (ram_clk1),
    .ram_csb        (ram_csb1),

    .ram_dout       (ram_dout1)
);
   


wire ackA_ram;
assign ackA_ram = writable_port_req_r ? port1_ack_o : port0_ack_o;
assign wbs_a_ack_o = wbs_a_csr ? (wbs_a_cyc_i & wbs_a_stb_i & wbs_a_csr) : ackA_ram;

wire [31:0] doutA;
wire [31:0] doutA_ram;
assign doutA_ram = writable_port_req_r ? port1_dat_o : port0_dat_o;
assign doutA = wbs_a_csr ? ({4'h0, port1_lat_prefetch, 4'h0, port1_lat_read, 4'h0, port0_lat_prefetch, 4'h0, port0_lat_read}) : doutA_ram;
assign wbs_a_dat_o = wbs_a_we_i ? wbs_a_dat_i : doutA;


assign wbs_b_ack_o = writable_port_req_r ? port0_ack_o : port1_ack_o;

wire [31:0] doutB;
assign doutB = writable_port_req_r ? port0_dat_o : port1_dat_o;
assign wbs_b_dat_o = wbs_b_we_i ? wbs_b_dat_i : doutB;


endmodule
module wb_openram_wrapper 
#(
    parameter RAM_ADDR_WIDTH = 8
)
(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input           		    writable_port_req,



    input           		    wb_a_clk_i,
    input           		    wb_a_rst_i,
    input           		    wbs_a_stb_i,
    input           		    wbs_a_cyc_i,
    input           		    wbs_a_we_i,
    input   [3:0]   		    wbs_a_sel_i,
    input   [31:0]  		    wbs_a_dat_i,
    input   [RAM_ADDR_WIDTH+2:0]  	wbs_a_adr_i,
    output          		    wbs_a_ack_o,
    output  [31:0]  		    wbs_a_dat_o,


    input           		    wb_b_clk_i,
    input           		    wb_b_rst_i,
    input           		    wbs_b_stb_i,
    input           		    wbs_b_cyc_i,
    input           		    wbs_b_we_i,
    input   [3:0]   		    wbs_b_sel_i,
    input   [31:0]  		    wbs_b_dat_i,
    input   [RAM_ADDR_WIDTH+1:0] 	wbs_b_adr_i,
    output          		    wbs_b_ack_o,
    output  [31:0]  		    wbs_b_dat_o,



    output                          ram_clk0,
    output                          ram_csb0,
    output                          ram_web0,
    output  [3:0]              	    ram_wmask0,
    output  [RAM_ADDR_WIDTH-1:0]    ram_addr0,
    output  [31:0]                  ram_din0,
    input   [31:0]                  ram_dout0,
    

    output                          ram_clk1,
    output                          ram_csb1,
    output  [RAM_ADDR_WIDTH-1:0]    ram_addr1,  
    input   [31:0]                  ram_dout1
);


reg writable_port_req_r;

always @(negedge wb_a_clk_i) begin
    if (wb_a_rst_i) begin
	writable_port_req_r <= 0;
    end else begin
	writable_port_req_r <= writable_port_req;
    end
end




wire wbs_a_csr;
assign wbs_a_csr = wbs_a_adr_i[RAM_ADDR_WIDTH+2] == 0;


wire [3:0] port0_lat_prefetch;
wire [3:0] port0_lat_read;

wire [3:0] port1_lat_prefetch;
wire [3:0] port1_lat_read;

register_rw 
#(
    .WIDTH(16),	
    .DEFAULT_VALUE(16'h2222)
)
latency_reg
(
    .rst        (wb_a_rst_i),
    .clk        (wb_a_clk_i),
    .wren       ( wbs_a_cyc_i & wbs_a_stb_i & wbs_a_we_i & wbs_a_csr ),
    .data_in    ( {wbs_a_dat_i[27:24], wbs_a_dat_i[19:16], wbs_a_dat_i[11:8], wbs_a_dat_i[3:0]} ),
    .data_out   ( {port1_lat_prefetch, port1_lat_read, port0_lat_prefetch, port0_lat_read} )
);


wire port0_clk_i;
wire port0_rst_i;
wire port0_stb_i;
wire port0_cyc_i;
wire port0_we_i;
wire port0_ack_o;
wire [31:0] port0_dat_o;


assign port0_clk_i = writable_port_req_r ? wb_b_clk_i : wb_a_clk_i;
assign port0_rst_i = writable_port_req_r ? wb_b_rst_i : wb_a_rst_i;
assign port0_stb_i = writable_port_req_r ? wbs_b_stb_i : (wbs_a_stb_i & !wbs_a_csr);
assign port0_cyc_i = writable_port_req_r ? wbs_b_cyc_i : (wbs_a_cyc_i & !wbs_a_csr);
assign port0_we_i = writable_port_req_r ? wbs_b_we_i : wbs_a_we_i;


assign ram_wmask0 = writable_port_req_r ? wbs_b_sel_i : wbs_a_sel_i;
assign ram_addr0 = writable_port_req_r ? wbs_b_adr_i[RAM_ADDR_WIDTH+1:2] : wbs_a_adr_i[RAM_ADDR_WIDTH+1:2];
assign ram_din0 = writable_port_req_r ? wbs_b_dat_i : wbs_a_dat_i;

wb_port_control
#(
    .READ_ONLY(0),
    .LATENCY_CNTR_WIDTH(4)
) port0_rw
(
`ifdef USE_POWER_PINS
    .vccd1 (vccd1),
    .vssd1 (vssd1),
`endif


    .prefetch_cycles (port0_lat_prefetch),
    .read_cycles    (port0_lat_read),


    .wb_clk_i       (port0_clk_i),
    .wb_rst_i       (port0_rst_i),
    .wbs_stb_i      (port0_stb_i),
    .wbs_cyc_i      (port0_cyc_i),
    .wbs_we_i       (port0_we_i),
    .wbs_ack_o      (port0_ack_o),
    .wbs_dat_o      (port0_dat_o),


    .ram_clk        (ram_clk0),
    .ram_csb        (ram_csb0),
    .ram_web        (ram_web0),
    .ram_dout       (ram_dout0)
);




wire port1_clk_i;
wire port1_rst_i;
wire port1_stb_i;
wire port1_cyc_i;
wire port1_we_i;
wire port1_ack_o;
wire [31:0] port1_dat_o;


assign port1_clk_i = writable_port_req_r ? wb_a_clk_i : wb_b_clk_i;
assign port1_rst_i = writable_port_req_r ? wb_a_rst_i : wb_b_rst_i;
assign port1_stb_i = writable_port_req_r ? (wbs_a_stb_i & !wbs_a_csr) : wbs_b_stb_i;
assign port1_cyc_i = writable_port_req_r ? (wbs_a_cyc_i & !wbs_a_csr) : wbs_b_cyc_i;
assign port1_we_i = writable_port_req_r ? wbs_a_we_i : wbs_b_we_i;


assign ram_addr1 = writable_port_req_r ? wbs_a_adr_i[RAM_ADDR_WIDTH+1:2] : wbs_b_adr_i[RAM_ADDR_WIDTH+1:2];

wb_port_control 
#(
    .READ_ONLY(1),
    .LATENCY_CNTR_WIDTH(4)
) port1_r
(
`ifdef USE_POWER_PINS
    .vccd1 (vccd1),
    .vssd1 (vssd1),
`endif


    .prefetch_cycles (port1_lat_prefetch),
    .read_cycles    (port1_lat_read),


    .wb_clk_i       (port1_clk_i),
    .wb_rst_i       (port1_rst_i),
    .wbs_stb_i      (port1_stb_i),
    .wbs_cyc_i      (port1_cyc_i),
    .wbs_we_i       (port1_we_i),
    .wbs_ack_o      (port1_ack_o),
    .wbs_dat_o      (port1_dat_o),


    .ram_clk        (ram_clk1),
    .ram_csb        (ram_csb1),

    .ram_dout       (ram_dout1)
);
   


wire ackA_ram;
assign ackA_ram = writable_port_req_r ? port1_ack_o : port0_ack_o;
assign wbs_a_ack_o = wbs_a_csr ? (wbs_a_cyc_i & wbs_a_stb_i & wbs_a_csr) : ackA_ram;

wire [31:0] doutA;
wire [31:0] doutA_ram;
assign doutA_ram = writable_port_req_r ? port1_dat_o : port0_dat_o;
assign doutA = wbs_a_csr ? ({4'h0, port1_lat_prefetch, 4'h0, port1_lat_read, 4'h0, port0_lat_prefetch, 4'h0, port0_lat_read}) : doutA_ram;
assign wbs_a_dat_o = wbs_a_we_i ? wbs_a_dat_i : doutA;


assign wbs_b_ack_o = writable_port_req_r ? port0_ack_o : port1_ack_o;

wire [31:0] doutB;
assign doutB = writable_port_req_r ? port0_dat_o : port1_dat_o;
assign wbs_b_dat_o = wbs_b_we_i ? wbs_b_dat_i : doutB;


endmodule