data/full_repos/permissive/531257706/src/mbsFSK.v
1: b"%Error: data/full_repos/permissive/531257706/src/mbsFSK.v:34: Cannot find file containing module: 'sampleClockGen'\n    sampleClockGen #(.CLK_DIV(1),  .CLK_TOTAL(128)) sampClockBlock (\n    ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/531257706/src,data/full_repos/permissive/531257706/sampleClockGen\n             data/full_repos/permissive/531257706/src,data/full_repos/permissive/531257706/sampleClockGen.v\n             data/full_repos/permissive/531257706/src,data/full_repos/permissive/531257706/sampleClockGen.sv\n             sampleClockGen\n             sampleClockGen.v\n             sampleClockGen.sv\n             obj_dir/sampleClockGen\n             obj_dir/sampleClockGen.v\n             obj_dir/sampleClockGen.sv\n%Error: data/full_repos/permissive/531257706/src/mbsFSK.v:41: Cannot find file containing module: 'SymbLUT'\n    SymbLUT symbolLUT (\n    ^~~~~~~\n%Error: data/full_repos/permissive/531257706/src/mbsFSK.v:50: Cannot find file containing module: 'LFSRmod'\n    LFSRmod prnGen (\n    ^~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module mbsFSK (
    input clk,
    input reset,
    output READY,
    output SHIFT,
    output [4:0] LFSR,
    output [6:0] COUNT,
    output GPIO2,
    output GPIO1
);

    reg reset_d, reset_sync;
    wire outReal, outImag, ready, shift;
    wire [4:0] dataOut;
    wire [6:0] count;

    assign READY = ready;
    assign SHIFT = shift;
    assign LFSR  = dataOut;
    assign COUNT = count;
    assign GPIO2 = outReal;
    assign GPIO1 = outImag;


    always @(posedge clk)
    begin
        reset_d      <= reset;
        reset_sync   <= reset_d;
    end


    sampleClockGen #(.CLK_DIV(1),  .CLK_TOTAL(128)) sampClockBlock (
        .CLOCK(clk),
        .RESET(reset_sync),
        .COUNT(count),
        .SAMP(ready),
        .SHIFT(shift));

    SymbLUT symbolLUT (
        .CLOCK(clk),
        .RESET(reset_sync),
        .READY(ready),
        .SHIFT(shift),
        .ADDRESS(dataOut),
        .DOUTREAL(outReal),
        .DOUTIMAG(outImag));

    LFSRmod prnGen (
        .CLOCK(clk),
        .RESET(reset_sync),
        .ENABLE(ready),
        .OUTDATA(dataOut));

endmodule
module mbsFSK (
    input clk,
    input reset,
    output READY,
    output SHIFT,
    output [4:0] LFSR,
    output [6:0] COUNT,
    output GPIO2,
    output GPIO1
);


    reg reset_d, reset_sync;
    wire outReal, outImag, ready, shift;
    wire [4:0] dataOut;
    wire [6:0] count;

    assign READY = ready;
    assign SHIFT = shift;
    assign LFSR  = dataOut;
    assign COUNT = count;
    assign GPIO2 = outReal;
    assign GPIO1 = outImag;


    always @(posedge clk)
    begin
        reset_d      <= reset;
        reset_sync   <= reset_d;
    end


    sampleClockGen #(.CLK_DIV(1),  .CLK_TOTAL(128)) sampClockBlock (
        .CLOCK(clk),
        .RESET(reset_sync),
        .COUNT(count),
        .SAMP(ready),
        .SHIFT(shift));

    SymbLUT symbolLUT (
        .CLOCK(clk),
        .RESET(reset_sync),
        .READY(ready),
        .SHIFT(shift),
        .ADDRESS(dataOut),
        .DOUTREAL(outReal),
        .DOUTIMAG(outImag));

    LFSRmod prnGen (
        .CLOCK(clk),
        .RESET(reset_sync),
        .ENABLE(ready),
        .OUTDATA(dataOut));

endmodule