data/full_repos/permissive/501138203/verilog/rtl/puf_top.v
1: b"%Error: data/full_repos/permissive/501138203/verilog/rtl/puf_top.v:25: syntax error, unexpected '.', expecting ')'\n        .\\puf_sel[0](puf_sel[0])\n        ^\n%Error: Exiting due to 1 error(s)\n"
module puf_top 
(
    `ifdef USE_POWER_PINS
        inout vccd2,
        inout vssd2,
    `endif
    input wire reset,
    input wire [1:0] puf_sel,
    input wire clk,
    input wire si,
    input wire rstn,
    input wire [1:0] length,
    output reg out,
    output reg so
);

    puf_super puf_super_0 (
        .reset(reset),
        .clk(clk),
        .si(si),
        .rstn(rstn),
        .\puf_sel[1](puf_sel[1]),
        .\puf_sel[0](puf_sel[0])
        .\length[1](length[1]),
        .\length[0](length[0]),
        .out(out),
        .so(so)
    `ifdef USE_POWER_PINS
        ,
        .vssd1(vssd2),
        .vccd1(vccd2)
    `endif
    );



endmodule
module puf_top 
(
    `ifdef USE_POWER_PINS
        inout vccd2,
        inout vssd2,
    `endif
    input wire reset,
    input wire [1:0] puf_sel,
    input wire clk,
    input wire si,
    input wire rstn,
    input wire [1:0] length,
    output reg out,
    output reg so
);


    puf_super puf_super_0 (
        .reset(reset),
        .clk(clk),
        .si(si),
        .rstn(rstn),
        .\puf_sel[1](puf_sel[1]),
        .\puf_sel[0](puf_sel[0])
        .\length[1](length[1]),
        .\length[0](length[0]),
        .out(out),
        .so(so)
    `ifdef USE_POWER_PINS
        ,
        .vssd1(vssd2),
        .vccd1(vccd2)
    `endif
    );



endmodule