data/full_repos/permissive/425175279/MIPS_Multi_Cycle/MIPS_Multi_Cycle.v
1: b"%Error: data/full_repos/permissive/425175279/MIPS_Multi_Cycle/MIPS_Multi_Cycle.v:56: Cannot find file containing module: 'PC_Counter'\n    PC_Counter u_PC_Counter(\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/425175279/MIPS_Multi_Cycle,data/full_repos/permissive/425175279/PC_Counter\n             data/full_repos/permissive/425175279/MIPS_Multi_Cycle,data/full_repos/permissive/425175279/PC_Counter.v\n             data/full_repos/permissive/425175279/MIPS_Multi_Cycle,data/full_repos/permissive/425175279/PC_Counter.sv\n             PC_Counter\n             PC_Counter.v\n             PC_Counter.sv\n             obj_dir/PC_Counter\n             obj_dir/PC_Counter.v\n             obj_dir/PC_Counter.sv\n%Error: data/full_repos/permissive/425175279/MIPS_Multi_Cycle/MIPS_Multi_Cycle.v:69: Cannot find file containing module: 'Instr_Data_Memory'\n    Instr_Data_Memory u_Instr_Data_Memory(\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/425175279/MIPS_Multi_Cycle/MIPS_Multi_Cycle.v:79: Cannot find file containing module: 'Control_Unit'\n    Control_Unit u_Control_Unit(\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/425175279/MIPS_Multi_Cycle/MIPS_Multi_Cycle.v:97: Cannot find file containing module: 'Reg_File'\n    Reg_File u_Reg_File(\n    ^~~~~~~~\n%Error: data/full_repos/permissive/425175279/MIPS_Multi_Cycle/MIPS_Multi_Cycle.v:108: Cannot find file containing module: 'Imm_Sign_Extend'\n    Imm_Sign_Extend u_Imm_Sign_Extend(\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/425175279/MIPS_Multi_Cycle/MIPS_Multi_Cycle.v:114: Cannot find file containing module: 'ALU_Control_Unit'\n    ALU_Control_Unit u_ALU_Control_Unit(\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/425175279/MIPS_Multi_Cycle/MIPS_Multi_Cycle.v:120: Cannot find file containing module: 'ALU'\n    ALU u_ALU(\n    ^~~\n%Error: Exiting due to 7 error(s)\n"
module MIPS_Multi_Cycle(

    input               clk,
    input               rst_n


    
);
    wire [31:0]         PC;
    wire [31:0]         ALUResult;
    wire [31:0]         SignImm;
    wire [31:0]         ALUOut;
    wire [31:0]         Instr;
    wire [31:0]         Data;
    wire [31:0]         A,B;
    wire [31:0]         Adr;
    wire [31:0]         WriteRegData;
    
    wire [2:0]          ALUControl;
    wire [1:0]          ALUOp;
    wire [1:0]          PCSrc;
    wire [4:0]          WriteReg;
    wire [1:0]          ALUSrcB;
    wire                ALUSrcA;     

    wire                MemWrite, RegWrite, IorD;
    wire                RegDst, ALUSrc, MemtoReg;
    wire                Branch, Zero;
    wire                PCEn, PCWrite, IRWrite;
    


    assign PCEn         = (Branch & Zero) | PCWrite;

    assign WriteReg     = RegDst ? Instr[15:11] : Instr[20:16];
    assign WriteRegData = MemtoReg ? Data : ALUOut;

    PC_Counter u_PC_Counter(
        .clk            (clk),
        .rst_n          (rst_n),
        .PCSrc          (PCSrc),
        .PCEn           (PCEn),
        .IorD           (IorD),
        .ALUOut         (ALUOut),
        .ALUResult      (ALUResult),
        .Jump_low_26Bit (Instr[25:0]),
        .Adr            (Adr),
        .PC             (PC)
    );

    Instr_Data_Memory u_Instr_Data_Memory(
        .clk            (clk),
        .A              (Adr),
        .WD             (B),
        .IRWrite        (IRWrite),
        .MemWrite       (MemWrite),
        .Instr          (Instr),
        .Data           (Data)
    );

    Control_Unit u_Control_Unit(
        .clk            (clk),
        .rst_n          (rst_n),
        .Opcode         (Instr[31:26]),
        .ALUOp          (ALUOp),
        .MemtoReg       (MemtoReg),
        .RegDst         (RegDst),
        .IorD           (IorD),
        .PCSrc          (PCSrc),
        .ALUSrcA        (ALUSrcA),
        .ALUSrcB        (ALUSrcB),
        .IRWrite        (IRWrite),
        .MemWrite       (MemWrite),
        .PCWrite        (PCWrite),
        .Branch         (Branch),
        .RegWrite       (RegWrite)
    );

    Reg_File u_Reg_File(
        .clk            (clk),
        .A1             (Instr[25:21]),
        .A2             (Instr[20:16]),
        .A3             (WriteReg),
        .A              (A),
        .B              (B),
        .RegWrite       (RegWrite),
        .WD3            (WriteRegData)
    );

    Imm_Sign_Extend u_Imm_Sign_Extend(
        .Immediate      (Instr[15:0]),
        .SignImm        (SignImm)
    );


    ALU_Control_Unit u_ALU_Control_Unit(
        .Funct          (Instr[5:0]),
        .ALUOp          (ALUOp),
        .ALUControl     (ALUControl)
    );

    ALU u_ALU(
        .clk            (clk),
        .ALUSrcA        (ALUSrcA),
        .ALUSrcB        (ALUSrcB),
        .ALUControl     (ALUControl),
        .A              (A),
        .B              (B),
        .PC             (PC),
        .SignImm        (SignImm),
        .ALUOut         (ALUOut),
        .ALUResult      (ALUResult),
        .Zero           (Zero)
    );

endmodule
module MIPS_Multi_Cycle(

    input               clk,
    input               rst_n


    
);

    wire [31:0]         PC;
    wire [31:0]         ALUResult;
    wire [31:0]         SignImm;
    wire [31:0]         ALUOut;
    wire [31:0]         Instr;
    wire [31:0]         Data;
    wire [31:0]         A,B;
    wire [31:0]         Adr;
    wire [31:0]         WriteRegData;
    
    wire [2:0]          ALUControl;
    wire [1:0]          ALUOp;
    wire [1:0]          PCSrc;
    wire [4:0]          WriteReg;
    wire [1:0]          ALUSrcB;
    wire                ALUSrcA;     

    wire                MemWrite, RegWrite, IorD;
    wire                RegDst, ALUSrc, MemtoReg;
    wire                Branch, Zero;
    wire                PCEn, PCWrite, IRWrite;
    


    assign PCEn         = (Branch & Zero) | PCWrite;

    assign WriteReg     = RegDst ? Instr[15:11] : Instr[20:16];
    assign WriteRegData = MemtoReg ? Data : ALUOut;

    PC_Counter u_PC_Counter(
        .clk            (clk),
        .rst_n          (rst_n),
        .PCSrc          (PCSrc),
        .PCEn           (PCEn),
        .IorD           (IorD),
        .ALUOut         (ALUOut),
        .ALUResult      (ALUResult),
        .Jump_low_26Bit (Instr[25:0]),
        .Adr            (Adr),
        .PC             (PC)
    );

    Instr_Data_Memory u_Instr_Data_Memory(
        .clk            (clk),
        .A              (Adr),
        .WD             (B),
        .IRWrite        (IRWrite),
        .MemWrite       (MemWrite),
        .Instr          (Instr),
        .Data           (Data)
    );

    Control_Unit u_Control_Unit(
        .clk            (clk),
        .rst_n          (rst_n),
        .Opcode         (Instr[31:26]),
        .ALUOp          (ALUOp),
        .MemtoReg       (MemtoReg),
        .RegDst         (RegDst),
        .IorD           (IorD),
        .PCSrc          (PCSrc),
        .ALUSrcA        (ALUSrcA),
        .ALUSrcB        (ALUSrcB),
        .IRWrite        (IRWrite),
        .MemWrite       (MemWrite),
        .PCWrite        (PCWrite),
        .Branch         (Branch),
        .RegWrite       (RegWrite)
    );

    Reg_File u_Reg_File(
        .clk            (clk),
        .A1             (Instr[25:21]),
        .A2             (Instr[20:16]),
        .A3             (WriteReg),
        .A              (A),
        .B              (B),
        .RegWrite       (RegWrite),
        .WD3            (WriteRegData)
    );

    Imm_Sign_Extend u_Imm_Sign_Extend(
        .Immediate      (Instr[15:0]),
        .SignImm        (SignImm)
    );


    ALU_Control_Unit u_ALU_Control_Unit(
        .Funct          (Instr[5:0]),
        .ALUOp          (ALUOp),
        .ALUControl     (ALUControl)
    );

    ALU u_ALU(
        .clk            (clk),
        .ALUSrcA        (ALUSrcA),
        .ALUSrcB        (ALUSrcB),
        .ALUControl     (ALUControl),
        .A              (A),
        .B              (B),
        .PC             (PC),
        .SignImm        (SignImm),
        .ALUOut         (ALUOut),
        .ALUResult      (ALUResult),
        .Zero           (Zero)
    );

endmodule