data/full_repos/permissive/405799749/amg_new2/adder/FSA_16_64_Carry_select_adder.v
data/verilator_xmls/a1e22f4f-1bee-4d86-a007-eae88622d5c2.xml
module UBRCB_45_37 (Co, S, X, Y, Ci);
  output Co;
  output [45:37] S;
  input Ci;
  input [45:37] X;
  input [45:37] Y;
  wire C38;
  wire C39;
  wire C40;
  wire C41;
  wire C42;
  wire C43;
  wire C44;
  wire C45;
  UBFA_37 U0 (C38, S[37], X[37], Y[37], Ci);
  UBFA_38 U1 (C39, S[38], X[38], Y[38], C38);
  UBFA_39 U2 (C40, S[39], X[39], Y[39], C39);
  UBFA_40 U3 (C41, S[40], X[40], Y[40], C40);
  UBFA_41 U4 (C42, S[41], X[41], Y[41], C41);
  UBFA_42 U5 (C43, S[42], X[42], Y[42], C42);
  UBFA_43 U6 (C44, S[43], X[43], Y[43], C43);
  UBFA_44 U7 (C45, S[44], X[44], Y[44], C44);
  UBFA_45 U8 (Co, S[45], X[45], Y[45], C45);
endmodule
module UBRCB_45_37 (Co, S, X, Y, Ci);

  output Co;
  output [45:37] S;
  input Ci;
  input [45:37] X;
  input [45:37] Y;
  wire C38;
  wire C39;
  wire C40;
  wire C41;
  wire C42;
  wire C43;
  wire C44;
  wire C45;
  UBFA_37 U0 (C38, S[37], X[37], Y[37], Ci);
  UBFA_38 U1 (C39, S[38], X[38], Y[38], C38);
  UBFA_39 U2 (C40, S[39], X[39], Y[39], C39);
  UBFA_40 U3 (C41, S[40], X[40], Y[40], C40);
  UBFA_41 U4 (C42, S[41], X[41], Y[41], C41);
  UBFA_42 U5 (C43, S[42], X[42], Y[42], C42);
  UBFA_43 U6 (C44, S[43], X[43], Y[43], C43);
  UBFA_44 U7 (C45, S[44], X[44], Y[44], C44);
  UBFA_45 U8 (Co, S[45], X[45], Y[45], C45);
endmodule