data/full_repos/permissive/493847347/src/predecoder.v
data/verilator_xmls/ae3a69d0-df34-4c01-a35f-728a0ffd86a2.xml
module Predecoder #(
  parameter INPUTS=4,
  parameter WIDTH=1<<INPUTS
) (
  input wire [WIDTH-1:0] values,
  input wire [INPUTS-1:0] s,
  output wire z
);

`ifdef PREDECODE_2
localparam LOWER_BITS = WIDTH/4;








wire [INPUTS-3:0] s_lower = s[INPUTS-3:0];








wire [LOWER_BITS-1:0] values_11 = values[4*LOWER_BITS-1:3*LOWER_BITS];
wire select_11 = values_11[s_lower];
wire [LOWER_BITS-1:0] values_10 = values[3*LOWER_BITS-1:2*LOWER_BITS];
wire select_10 = values_10[s_lower];
wire [LOWER_BITS-1:0] values_01 = values[2*LOWER_BITS-1:1*LOWER_BITS];
wire select_01 = values_01[s_lower];
wire [LOWER_BITS-1:0] values_00 = values[1*LOWER_BITS-1:0*LOWER_BITS];
wire select_00 = values_00[s_lower];


reg z_int;
always @(*) begin
  case (s[INPUTS-1:INPUTS-2])
    2'b00: z_int = select_00;
    2'b01: z_int = select_01;
    2'b10: z_int = select_10;
    2'b11: z_int = select_11;
  endcase
end
assign z = z_int;






















           

`else
assign z = values[s];
`endif

endmodule
module Predecoder #(
  parameter INPUTS=4,
  parameter WIDTH=1<<INPUTS
) (
  input wire [WIDTH-1:0] values,
  input wire [INPUTS-1:0] s,
  output wire z
);


`ifdef PREDECODE_2
localparam LOWER_BITS = WIDTH/4;








wire [INPUTS-3:0] s_lower = s[INPUTS-3:0];








wire [LOWER_BITS-1:0] values_11 = values[4*LOWER_BITS-1:3*LOWER_BITS];
wire select_11 = values_11[s_lower];
wire [LOWER_BITS-1:0] values_10 = values[3*LOWER_BITS-1:2*LOWER_BITS];
wire select_10 = values_10[s_lower];
wire [LOWER_BITS-1:0] values_01 = values[2*LOWER_BITS-1:1*LOWER_BITS];
wire select_01 = values_01[s_lower];
wire [LOWER_BITS-1:0] values_00 = values[1*LOWER_BITS-1:0*LOWER_BITS];
wire select_00 = values_00[s_lower];


reg z_int;
always @(*) begin
  case (s[INPUTS-1:INPUTS-2])
    2'b00: z_int = select_00;
    2'b01: z_int = select_01;
    2'b10: z_int = select_10;
    2'b11: z_int = select_11;
  endcase
end
assign z = z_int;






















           

`else
assign z = values[s];
`endif

endmodule