data/full_repos/permissive/408955603/Sesion6/alu.v
1: b'%Error: data/full_repos/permissive/408955603/Sesion6/alu.v:1: Cannot find include file: 74181.v\n`include "74181.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/408955603/Sesion6,data/full_repos/permissive/408955603/74181.v\n             data/full_repos/permissive/408955603/Sesion6,data/full_repos/permissive/408955603/74181.v.v\n             data/full_repos/permissive/408955603/Sesion6,data/full_repos/permissive/408955603/74181.v.sv\n             74181.v\n             74181.v.v\n             74181.v.sv\n             obj_dir/74181.v\n             obj_dir/74181.v.v\n             obj_dir/74181.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion6/alu.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #5 $display("%d + %d = %d(%b)", A, B, F, ~CN4b);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion6/alu.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #5 $display("%b AND %b = %b", A, B, F);\n  ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module Ej2;
	reg [3:0] A, B, S;
	reg M, CNb;

	wire [3:0] F;
	wire AEB, CN4b;

	Circuit74181 ALU(S, A, B, M, CNb, F, , , CN4b, AEB);

	initial
	begin

		M = 0;
		S='b1001;
		A = 5; B = 7; CNb = 1;

		#5 $display("%d + %d = %d(%b)", A, B, F, ~CN4b);


		M = 1;
		S = 'b1011;
		A = 'b0011; B = 'b1101;
		#5 $display("%b AND %b = %b", A, B, F);
	end
endmodule
module Ej2;

	reg [3:0] A, B, S;
	reg M, CNb;

	wire [3:0] F;
	wire AEB, CN4b;

	Circuit74181 ALU(S, A, B, M, CNb, F, , , CN4b, AEB);

	initial
	begin

		M = 0;
		S='b1001;
		A = 5; B = 7; CNb = 1;

		#5 $display("%d + %d = %d(%b)", A, B, F, ~CN4b);


		M = 1;
		S = 'b1011;
		A = 'b0011; B = 'b1101;
		#5 $display("%b AND %b = %b", A, B, F);
	end
endmodule