data/full_repos/permissive/507383616/rtl/pmu_module.v
1: b'%Warning-WIDTH: data/full_repos/permissive/507383616/rtl/pmu_module.v:98: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                        : ... In instance pmu_module\n                total_command_arrive[0] <=  total_command_arrive[0] + command_arrive[0];\n                                                                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/507383616/rtl/pmu_module.v:99: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                        : ... In instance pmu_module\n                total_command_arrive[1] <=  total_command_arrive[1] + command_arrive[1];\n                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/507383616/rtl/pmu_module.v:100: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                         : ... In instance pmu_module\n                total_command_arrive[2] <=  total_command_arrive[2] + command_arrive[2];\n                                                                    ^\n%Error: Exiting due to 3 warning(s)\n'
module pmu_module #
(

    parameter COUNTERSIZE = 8,
    parameter REGISTER_SIZE = 4
	)
(
    input clk,
    input rst,
    input  wire [2:0] trx_error,
    input  wire [2:0] output_io_error,
    input  wire [2:0] command_arrive,
    input  wire  [2:0] command_arrive_discrepancy,
    input  wire  [REGISTER_SIZE-1:0] pmu_register,
    input  wire  valid_pmu_register,
    output reg  [COUNTERSIZE-1:0] pmu_value,
    output reg  valid_value

    );

    reg [COUNTERSIZE-1:0] total_errors_trx                  [0:2];
    reg [COUNTERSIZE-1:0] total_errors_io                   [0:2];
    reg [COUNTERSIZE-1:0] total_command_arrive              [0:2];
    reg [COUNTERSIZE-1:0] total_command_arrive_discrepancy  [0:2];
    reg [COUNTERSIZE-1:0] total_unrecobable_errors_trx;
    reg [COUNTERSIZE-1:0] total_unrecobable_errors_io;
    reg [COUNTERSIZE-1:0] total_unrecobable_commands;
    (* mark_debug = "true" *) reg [COUNTERSIZE-1:0] total_request;


    always @(posedge clk) begin
        if (rst) begin
            total_errors_trx[0]                 <= {COUNTERSIZE {1'b0}};
            total_errors_trx[1]                 <= {COUNTERSIZE {1'b0}};
            total_errors_trx[2]                 <= {COUNTERSIZE {1'b0}};
            total_errors_io[0]                  <= {COUNTERSIZE {1'b0}};
            total_errors_io[1]                  <= {COUNTERSIZE {1'b0}};
            total_errors_io[2]                  <= {COUNTERSIZE {1'b0}};
            total_command_arrive[0]             <= {COUNTERSIZE {1'b0}};
            total_command_arrive[1]             <= {COUNTERSIZE {1'b0}};
            total_command_arrive[2]             <= {COUNTERSIZE {1'b0}};
            total_command_arrive_discrepancy[0] <= {COUNTERSIZE {1'b0}};
            total_command_arrive_discrepancy[1] <= {COUNTERSIZE {1'b0}};
            total_command_arrive_discrepancy[2] <= {COUNTERSIZE {1'b0}};
            total_unrecobable_errors_trx        <= {COUNTERSIZE {1'b0}};
            total_unrecobable_errors_io         <= {COUNTERSIZE {1'b0}};
            total_unrecobable_commands          <= {COUNTERSIZE {1'b0}};
            total_request                       <= {COUNTERSIZE {1'b0}};
            valid_value                         <= 1'b0;
            pmu_value                           <= {COUNTERSIZE {1'b0}};
        end
        else begin

            valid_value <= 1'b0;

            if (trx_error != 3'b000) begin
                case (trx_error)
                    3'b001:  total_errors_trx[0] <= total_errors_trx[0] + 1;
                    3'b010:  total_errors_trx[1] <= total_errors_trx[1] + 1;
                    3'b100:  total_errors_trx[2] <= total_errors_trx[2] + 1;
                    default: total_unrecobable_errors_trx <= total_unrecobable_errors_trx + 1;
                endcase
            end 
            if (output_io_error != 3'b000) begin
                case (trx_error)
                    3'b001:  total_errors_io[0] <= total_errors_io[0] + 1;
                    3'b010:  total_errors_io[1] <= total_errors_io[1] + 1;
                    3'b100:  total_errors_io[2] <= total_errors_io[2] + 1;
                    default: total_unrecobable_errors_io <= total_unrecobable_errors_io + 1;
                endcase
            end
            if (command_arrive != 3'b000) begin

                total_request <= total_request +1;

                total_command_arrive[0] <=  total_command_arrive[0] + command_arrive[0];
                total_command_arrive[1] <=  total_command_arrive[1] + command_arrive[1];
                total_command_arrive[2] <=  total_command_arrive[2] + command_arrive[2];
            end
            if (command_arrive_discrepancy != 3'b000) begin
                case (trx_error)
                    3'b001:  total_command_arrive_discrepancy[0] <= total_command_arrive_discrepancy[0] + 1;
                    3'b010:  total_command_arrive_discrepancy[1] <= total_command_arrive_discrepancy[1] + 1;
                    3'b100:  total_command_arrive_discrepancy[2] <= total_command_arrive_discrepancy[2] + 1;
                    default: total_unrecobable_commands <= total_unrecobable_commands + 1;
                endcase
            end

        end

        if (valid_pmu_register) begin
            case (pmu_register)
                4'h0: pmu_value <= total_request;
                4'h1: pmu_value <= total_unrecobable_commands;
                4'h2: pmu_value <= total_unrecobable_errors_trx;
                4'h3: pmu_value <= total_unrecobable_errors_io;
                4'h4: pmu_value <= total_command_arrive[0];
                4'h5: pmu_value <= total_command_arrive[1];
                4'h6: pmu_value <= total_command_arrive[2];
                4'h7: pmu_value <= total_command_arrive_discrepancy[0];
                4'h8: pmu_value <= total_command_arrive_discrepancy[1];
                4'h9: pmu_value <= total_command_arrive_discrepancy[2];
                4'hA: pmu_value <= total_errors_trx[0];
                4'hB: pmu_value <= total_errors_trx[1];
                4'hC: pmu_value <= total_errors_trx[2];
                4'hD: pmu_value <= total_errors_io[0];
                4'hE: pmu_value <= total_errors_io[1];
                4'hF: pmu_value <= total_errors_io[2];
                default: pmu_value <= {COUNTERSIZE {1'b0}};
            endcase
            valid_value <= 1'b1;
        end
    end
endmodule
module pmu_module #
(

    parameter COUNTERSIZE = 8,
    parameter REGISTER_SIZE = 4
	)
(
    input clk,
    input rst,
    input  wire [2:0] trx_error,
    input  wire [2:0] output_io_error,
    input  wire [2:0] command_arrive,
    input  wire  [2:0] command_arrive_discrepancy,
    input  wire  [REGISTER_SIZE-1:0] pmu_register,
    input  wire  valid_pmu_register,
    output reg  [COUNTERSIZE-1:0] pmu_value,
    output reg  valid_value

    );


    reg [COUNTERSIZE-1:0] total_errors_trx                  [0:2];
    reg [COUNTERSIZE-1:0] total_errors_io                   [0:2];
    reg [COUNTERSIZE-1:0] total_command_arrive              [0:2];
    reg [COUNTERSIZE-1:0] total_command_arrive_discrepancy  [0:2];
    reg [COUNTERSIZE-1:0] total_unrecobable_errors_trx;
    reg [COUNTERSIZE-1:0] total_unrecobable_errors_io;
    reg [COUNTERSIZE-1:0] total_unrecobable_commands;
    (* mark_debug = "true" *) reg [COUNTERSIZE-1:0] total_request;


    always @(posedge clk) begin
        if (rst) begin
            total_errors_trx[0]                 <= {COUNTERSIZE {1'b0}};
            total_errors_trx[1]                 <= {COUNTERSIZE {1'b0}};
            total_errors_trx[2]                 <= {COUNTERSIZE {1'b0}};
            total_errors_io[0]                  <= {COUNTERSIZE {1'b0}};
            total_errors_io[1]                  <= {COUNTERSIZE {1'b0}};
            total_errors_io[2]                  <= {COUNTERSIZE {1'b0}};
            total_command_arrive[0]             <= {COUNTERSIZE {1'b0}};
            total_command_arrive[1]             <= {COUNTERSIZE {1'b0}};
            total_command_arrive[2]             <= {COUNTERSIZE {1'b0}};
            total_command_arrive_discrepancy[0] <= {COUNTERSIZE {1'b0}};
            total_command_arrive_discrepancy[1] <= {COUNTERSIZE {1'b0}};
            total_command_arrive_discrepancy[2] <= {COUNTERSIZE {1'b0}};
            total_unrecobable_errors_trx        <= {COUNTERSIZE {1'b0}};
            total_unrecobable_errors_io         <= {COUNTERSIZE {1'b0}};
            total_unrecobable_commands          <= {COUNTERSIZE {1'b0}};
            total_request                       <= {COUNTERSIZE {1'b0}};
            valid_value                         <= 1'b0;
            pmu_value                           <= {COUNTERSIZE {1'b0}};
        end
        else begin

            valid_value <= 1'b0;

            if (trx_error != 3'b000) begin
                case (trx_error)
                    3'b001:  total_errors_trx[0] <= total_errors_trx[0] + 1;
                    3'b010:  total_errors_trx[1] <= total_errors_trx[1] + 1;
                    3'b100:  total_errors_trx[2] <= total_errors_trx[2] + 1;
                    default: total_unrecobable_errors_trx <= total_unrecobable_errors_trx + 1;
                endcase
            end 
            if (output_io_error != 3'b000) begin
                case (trx_error)
                    3'b001:  total_errors_io[0] <= total_errors_io[0] + 1;
                    3'b010:  total_errors_io[1] <= total_errors_io[1] + 1;
                    3'b100:  total_errors_io[2] <= total_errors_io[2] + 1;
                    default: total_unrecobable_errors_io <= total_unrecobable_errors_io + 1;
                endcase
            end
            if (command_arrive != 3'b000) begin

                total_request <= total_request +1;

                total_command_arrive[0] <=  total_command_arrive[0] + command_arrive[0];
                total_command_arrive[1] <=  total_command_arrive[1] + command_arrive[1];
                total_command_arrive[2] <=  total_command_arrive[2] + command_arrive[2];
            end
            if (command_arrive_discrepancy != 3'b000) begin
                case (trx_error)
                    3'b001:  total_command_arrive_discrepancy[0] <= total_command_arrive_discrepancy[0] + 1;
                    3'b010:  total_command_arrive_discrepancy[1] <= total_command_arrive_discrepancy[1] + 1;
                    3'b100:  total_command_arrive_discrepancy[2] <= total_command_arrive_discrepancy[2] + 1;
                    default: total_unrecobable_commands <= total_unrecobable_commands + 1;
                endcase
            end

        end

        if (valid_pmu_register) begin
            case (pmu_register)
                4'h0: pmu_value <= total_request;
                4'h1: pmu_value <= total_unrecobable_commands;
                4'h2: pmu_value <= total_unrecobable_errors_trx;
                4'h3: pmu_value <= total_unrecobable_errors_io;
                4'h4: pmu_value <= total_command_arrive[0];
                4'h5: pmu_value <= total_command_arrive[1];
                4'h6: pmu_value <= total_command_arrive[2];
                4'h7: pmu_value <= total_command_arrive_discrepancy[0];
                4'h8: pmu_value <= total_command_arrive_discrepancy[1];
                4'h9: pmu_value <= total_command_arrive_discrepancy[2];
                4'hA: pmu_value <= total_errors_trx[0];
                4'hB: pmu_value <= total_errors_trx[1];
                4'hC: pmu_value <= total_errors_trx[2];
                4'hD: pmu_value <= total_errors_io[0];
                4'hE: pmu_value <= total_errors_io[1];
                4'hF: pmu_value <= total_errors_io[2];
                default: pmu_value <= {COUNTERSIZE {1'b0}};
            endcase
            valid_value <= 1'b1;
        end
    end
endmodule