data/full_repos/permissive/435877241/prj_1.v
1: b'%Warning-WIDTH: data/full_repos/permissive/435877241/prj_1.v:26: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                               : ... In instance prj_1\n                cnt<=#1 1\'b0;\n                   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/435877241/prj_1.v:31: Operator EQ expects 3 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                               : ... In instance prj_1\n        if(scan_cnt==2\'d2) scan_cnt<=0;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/435877241/prj_1.v:35: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                               : ... In instance prj_1\n            0:d<=3\'b001;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/435877241/prj_1.v:36: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h2\' generates 3 bits.\n                                                               : ... In instance prj_1\n            1:d<=3\'b010;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/435877241/prj_1.v:37: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h4\' generates 3 bits.\n                                                               : ... In instance prj_1\n            2:d<=3\'b100;\n               ^~\n%Warning-WIDTH: data/full_repos/permissive/435877241/prj_1.v:38: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                               : ... In instance prj_1\n            default:d<=3\'b000;\n                     ^~\n%Error: Exiting due to 6 warning(s)\n'
module prj_1(
    input clk,
    output [3:0] dig,
    output [7:0] number
    );
    reg clkout;
    integer cnt;
    reg [2:0] scan_cnt;
    parameter period=50;
    reg [6:0] num;
    reg [3:0] d;
    assign number={num[6:0],1'b0};
    assign dig=~d;
    always @(posedge clk)begin
        cnt<=cnt+1;
        if(cnt==(period>>1)-1) clkout<=#1 1'b1;
        else if(cnt==period-1)begin
                clkout<=#1 1'b0;
                cnt<=#1 1'b0;
            end
    end
    always @(posedge clkout)begin
        scan_cnt<=scan_cnt+1;
        if(scan_cnt==2'd2) scan_cnt<=0;
    end
    always @(scan_cnt)begin
        case(scan_cnt)
            0:d<=3'b001;
            1:d<=3'b010;
            2:d<=3'b100;
            default:d<=3'b000;
        endcase
    end
    always @(scan_cnt)begin
        case(scan_cnt)
            0:num=7'b0110000;
            1:num=7'b1111110;
            2:num=7'b1011111;
            default:num=7'b0000000;
        endcase
    end
endmodule
module prj_1(
    input clk,
    output [3:0] dig,
    output [7:0] number
    );

    reg clkout;
    integer cnt;
    reg [2:0] scan_cnt;
    parameter period=50;
    reg [6:0] num;
    reg [3:0] d;
    assign number={num[6:0],1'b0};
    assign dig=~d;
    always @(posedge clk)begin
        cnt<=cnt+1;
        if(cnt==(period>>1)-1) clkout<=#1 1'b1;
        else if(cnt==period-1)begin
                clkout<=#1 1'b0;
                cnt<=#1 1'b0;
            end
    end
    always @(posedge clkout)begin
        scan_cnt<=scan_cnt+1;
        if(scan_cnt==2'd2) scan_cnt<=0;
    end
    always @(scan_cnt)begin
        case(scan_cnt)
            0:d<=3'b001;
            1:d<=3'b010;
            2:d<=3'b100;
            default:d<=3'b000;
        endcase
    end
    always @(scan_cnt)begin
        case(scan_cnt)
            0:num=7'b0110000;
            1:num=7'b1111110;
            2:num=7'b1011111;
            default:num=7'b0000000;
        endcase
    end
endmodule