data/full_repos/permissive/426864978/lab3/task3/tb_rtl_arc4.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task3/tb_rtl_arc4.sv:20: Unsupported: Ignoring delay on this delayed statement.\n        forever #5 clk = ~clk;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task3/tb_rtl_arc4.sv:37: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_rtl_arc4.sv:49: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_rtl_arc4.sv:61: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_rtl_arc4.sv:73: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_rtl_arc4.sv:85: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_rtl_arc4.sv:96: Unsupported: wait statements\n        wait (tb_rtl_arc4.dut.done_init == 1\'b1);\n        ^~~~\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_rtl_arc4.sv:105: Unsupported: wait statements\n        wait (tb_rtl_arc4.dut.done_ksa == 1\'b1);\n        ^~~~\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_rtl_arc4.sv:115: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_rtl_arc4.sv:118: syntax error, unexpected \'@\'\n            @(posedge clk);   \n            ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_rtl_arc4.sv:121: syntax error, unexpected \'@\'\n            @(posedge clk);   \n            ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_rtl_arc4.sv:150: syntax error, unexpected \'@\'\n            @(posedge clk);   \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task3/tb_rtl_arc4.sv:163: Unsupported: Ignoring delay on this delayed statement.\n        #50;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task3/tb_rtl_arc4.sv:182: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_rtl_arc4.sv:194: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_rtl_arc4.sv:206: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_rtl_arc4.sv:218: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_rtl_arc4.sv:230: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_rtl_arc4.sv:241: Unsupported: wait statements\n        wait (tb_rtl_arc4.dut.done_init == 1\'b1);\n        ^~~~\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_rtl_arc4.sv:250: Unsupported: wait statements\n        wait (tb_rtl_arc4.dut.done_ksa == 1\'b1);\n        ^~~~\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_rtl_arc4.sv:260: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_rtl_arc4.sv:263: syntax error, unexpected \'@\'\n            @(posedge clk);   \n            ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_rtl_arc4.sv:266: syntax error, unexpected \'@\'\n            @(posedge clk);   \n            ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_rtl_arc4.sv:295: syntax error, unexpected \'@\'\n            @(posedge clk);   \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task3/tb_rtl_arc4.sv:308: Unsupported: Ignoring delay on this delayed statement.\n        #50;\n        ^\n%Error: Exiting due to 20 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_rtl_arc4();

    logic clk, rst_n, en, rdy, pt_wren, err;
    logic [23:0] key;
    logic [7:0] ct_addr, ct_rddata, pt_addr, pt_rddata, pt_wrdata;


    logic [7:0] exp_ksa [255:0];
    logic [7:0] exp_pad [255:0];
    logic [7:0] exp_pt [255:0];
    logic [7:0] ciphertext [255:0];
    logic [7:0] pt [255:0];

    arc4 dut(.*);

    initial begin
        clk = 1;
        forever #5 clk = ~clk;
    end

    initial begin
        err = 1'b0;


        $readmemh("ksa_res.txt", exp_ksa);
        $readmemh("pad_res.txt", exp_pad);
        $readmemh("prga_res.txt", exp_pt);
        $readmemh("test1.memh", ciphertext);

        `define IDLE  2'b00
        `define START 2'b01


        rst_n = 1'bx; en = 1'bx;
        #10;
        if (tb_rtl_arc4.dut.rdy !== 1'b0) begin
            $display("ERROR 1A: Expected rdy is %d, actual rdy is %d", 1'b0, tb_rtl_arc4.dut.rdy);
            err = 1'b1;
        end
        if (tb_rtl_arc4.dut.state !== `IDLE) begin
            $display("ERROR 1B: Expected state is %d, actual state is %d", `IDLE, tb_rtl_arc4.dut.state);
            err = 1'b1;
        end


        rst_n = 1'b0; en = 1'b0; key = 24'h1E4600;
        @(negedge clk);
        if (tb_rtl_arc4.dut.rdy !== 1'b0) begin
            $display("ERROR 2A: Expected rdy is %d, actual rdy is %d", 1'b0, tb_rtl_arc4.dut.rdy);
            err = 1'b1;
        end
        if (tb_rtl_arc4.dut.state !== `IDLE) begin
            $display("ERROR 2B: Expected state is %d, actual state is %d", `IDLE, tb_rtl_arc4.dut.state);
            err = 1'b1;
        end


        rst_n = 1'b1;
        @(posedge clk);
        if (tb_rtl_arc4.dut.rdy !== 1'b0) begin
            $display("ERROR 3A: Expected rdy is %d, actual rdy is %d", 1'b0, tb_rtl_arc4.dut.rdy);
            err = 1'b1;
        end
        if (tb_rtl_arc4.dut.state !== `IDLE) begin
            $display("ERROR 3B: Expected state is %d, actual state is %d", `IDLE, tb_rtl_arc4.dut.state);
            err = 1'b1;
        end


        en = 1'b1; ct_rddata = ciphertext[0];
        @(posedge clk);
        if (tb_rtl_arc4.dut.rdy !== 1'b1) begin
            $display("ERROR 4A: Expected rdy is %d, actual rdy is %d", 1'b1, tb_rtl_arc4.dut.rdy);
            err = 1'b1;
        end
        if (tb_rtl_arc4.dut.state !== `IDLE) begin
            $display("ERROR 4B: Expected state is %d, actual state is %d", `IDLE, tb_rtl_arc4.dut.state);
            err = 1'b1;
        end


        en = 1'b0;
        @(posedge clk);
        if (tb_rtl_arc4.dut.rdy !== 1'b0) begin
            $display("ERROR 5A: Expected rdy is %d, actual rdy is %d", 1'b0, tb_rtl_arc4.dut.rdy);
            err = 1'b1;
        end
        if (tb_rtl_arc4.dut.state !== `START) begin
            $display("ERROR 5B: Expected state is %d, actual state is %d", `START, tb_rtl_arc4.dut.state);
            err = 1'b1;
        end


        wait (tb_rtl_arc4.dut.done_init == 1'b1);
        for (int i = 0; i < 256; i++) begin
            if (tb_rtl_arc4.dut.s.altsyncram_component.m_default.altsyncram_inst.mem_data[i] !== i) begin
                $display("INIT MEM ERR: Expected value is %d, actual value is %d", i, tb_rtl_arc4.dut.s.altsyncram_component.m_default.altsyncram_inst.mem_data[i]);
                err = 1'b1;
            end
        end


        wait (tb_rtl_arc4.dut.done_ksa == 1'b1);
        for (int i = 0; i < 256; i++) begin
            if (tb_rtl_arc4.dut.s.altsyncram_component.m_default.altsyncram_inst.mem_data[i] !== exp_ksa[i]) begin
                $display("KSA MEM ERR: Expected value is %d, actual value is %d", exp_ksa[i], tb_rtl_arc4.dut.s.altsyncram_component.m_default.altsyncram_inst.mem_data[i]);
                err = 1'b1;
            end
        end


        ct_rddata = ciphertext[0];
        @(posedge clk);

        for (int i = 0; i < 8'h49; i++) begin
            @(posedge clk);
            @(posedge clk);
            ct_rddata = ciphertext[tb_rtl_arc4.dut.ct_addr];
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
        end


        @(posedge clk);
        for (int i = 0; i <= 8'h49; i++) begin
            if (tb_rtl_arc4.dut.p.ct_mem[i] !== ciphertext[i]) begin 
                $display("CT[%d] ERROR: Expected ct is %h, actual ct is %h", i[7:0], ciphertext[i], tb_rtl_arc4.dut.p.ct_mem[i]);
                err = 1'b1;
            end
        end


        for (int i = 0; i < 8'h49; i++) begin
            if (tb_rtl_arc4.dut.p.pad[i] !== exp_pad[i]) begin 
                $display("PAD[%d] ERROR: Expected pad is %h, actual pad is %h", i[7:0], exp_pad[i], tb_rtl_arc4.dut.p.pad[i]);
                err = 1'b1;
            end
        end


        pt[0] = tb_rtl_arc4.dut.p.message_length;
        for (int k = 0; k < 8'h49; k++) begin
            @(posedge clk);
            pt[tb_rtl_arc4.dut.pt_addr] = tb_rtl_arc4.dut.p.pad[tb_rtl_arc4.dut.p.k] ^ ciphertext[tb_rtl_arc4.dut.p.k + 8'b1];
        end


        for (int i = 0; i < 8'h49; i++) begin
           if (exp_pt[i] !== pt[i]) begin 
                $display("PT[%d] ERROR: Expected pt is %h, actual pt is %h", i[7:0], exp_pt[i], pt[i]);
                err = 1'b1;
            end
        end


        #50;
        if (tb_rtl_arc4.dut.done_prga !== 1'b1) begin
            $display("ERROR 12A: Expected done_prga is %d, actual done_prga is %d", 1'b1, tb_rtl_arc4.dut.done_prga);
            err = 1'b1;
        end
        if (tb_rtl_arc4.dut.rdy !== 1'b1) begin
            $display("ERROR 12B: Expected rdy is %d, actual rdy is %d", 1'b1, tb_rtl_arc4.dut.rdy);
            err = 1'b1;
        end




        $readmemh("ksa_res2.txt", exp_ksa);
        $readmemh("pad_res2.txt", exp_pad);
        $readmemh("prga_res2.txt", exp_pt);
        $readmemh("test2.memh", ciphertext);


        #10;
        if (tb_rtl_arc4.dut.rdy !== 1'b1) begin
            $display("ERROR 13A: Expected rdy is %d, actual rdy is %d", 1'b1, tb_rtl_arc4.dut.rdy);
            err = 1'b1;
        end
        if (tb_rtl_arc4.dut.state !== `IDLE) begin
            $display("ERROR 13B: Expected state is %d, actual state is %d", `IDLE, tb_rtl_arc4.dut.state);
            err = 1'b1;
        end


        rst_n = 1'b0; en = 1'b0; key = 24'h000018;
        @(negedge clk);
        if (tb_rtl_arc4.dut.rdy !== 1'b0) begin
            $display("ERROR 14A: Expected rdy is %d, actual rdy is %d", 1'b0, tb_rtl_arc4.dut.rdy);
            err = 1'b1;
        end
        if (tb_rtl_arc4.dut.state !== `IDLE) begin
            $display("ERROR 14B: Expected state is %d, actual state is %d", `IDLE, tb_rtl_arc4.dut.state);
            err = 1'b1;
        end


        rst_n = 1'b1;
        @(posedge clk);
        if (tb_rtl_arc4.dut.rdy !== 1'b0) begin
            $display("ERROR 15A: Expected rdy is %d, actual rdy is %d", 1'b0, tb_rtl_arc4.dut.rdy);
            err = 1'b1;
        end
        if (tb_rtl_arc4.dut.state !== `IDLE) begin
            $display("ERROR 15B: Expected state is %d, actual state is %d", `IDLE, tb_rtl_arc4.dut.state);
            err = 1'b1;
        end


        en = 1'b1; ct_rddata = ciphertext[0];
        @(posedge clk);
        if (tb_rtl_arc4.dut.rdy !== 1'b1) begin
            $display("ERROR 16A: Expected rdy is %d, actual rdy is %d", 1'b1, tb_rtl_arc4.dut.rdy);
            err = 1'b1;
        end
        if (tb_rtl_arc4.dut.state !== `IDLE) begin
            $display("ERROR 16B: Expected state is %d, actual state is %d", `IDLE, tb_rtl_arc4.dut.state);
            err = 1'b1;
        end


        en = 1'b0;
        @(posedge clk);
        if (tb_rtl_arc4.dut.rdy !== 1'b0) begin
            $display("ERROR 17A: Expected rdy is %d, actual rdy is %d", 1'b0, tb_rtl_arc4.dut.rdy);
            err = 1'b1;
        end
        if (tb_rtl_arc4.dut.state !== `START) begin
            $display("ERROR 17B: Expected state is %d, actual state is %d", `START, tb_rtl_arc4.dut.state);
            err = 1'b1;
        end


        wait (tb_rtl_arc4.dut.done_init == 1'b1);
        for (int i = 0; i < 256; i++) begin
            if (tb_rtl_arc4.dut.s.altsyncram_component.m_default.altsyncram_inst.mem_data[i] !== i) begin
                $display("INIT 2 MEM ERR: Expected value is %d, actual value is %d", i, tb_rtl_arc4.dut.s.altsyncram_component.m_default.altsyncram_inst.mem_data[i]);
                err = 1'b1;
            end
        end


        wait (tb_rtl_arc4.dut.done_ksa == 1'b1);
        for (int i = 0; i < 256; i++) begin
            if (tb_rtl_arc4.dut.s.altsyncram_component.m_default.altsyncram_inst.mem_data[i] !== exp_ksa[i]) begin
                $display("KSA 2 MEM ERR: Expected value is %d, actual value is %d", exp_ksa[i], tb_rtl_arc4.dut.s.altsyncram_component.m_default.altsyncram_inst.mem_data[i]);
                err = 1'b1;
            end
        end


        ct_rddata = ciphertext[0];
        @(posedge clk);

        for (int i = 0; i < 8'd53; i++) begin
            @(posedge clk);
            @(posedge clk);
            ct_rddata = ciphertext[tb_rtl_arc4.dut.ct_addr];
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
        end


        @(posedge clk);
        for (int i = 0; i <= 8'd53; i++) begin
            if (tb_rtl_arc4.dut.p.ct_mem[i] !== ciphertext[i]) begin 
                $display("CT 2[%d] ERROR: Expected ct is %h, actual ct is %h", i[7:0], ciphertext[i], tb_rtl_arc4.dut.p.ct_mem[i]);
                err = 1'b1;
            end
        end


        for (int i = 0; i < 8'd53; i++) begin
            if (tb_rtl_arc4.dut.p.pad[i] !== exp_pad[i]) begin 
                $display("PAD 2[%d] ERROR: Expected pad is %h, actual pad is %h", i[7:0], exp_pad[i], tb_rtl_arc4.dut.p.pad[i]);
                err = 1'b1;
            end
        end


        pt[0] = tb_rtl_arc4.dut.p.message_length;
        for (int k = 0; k < 8'd53; k++) begin
            @(posedge clk);
            pt[tb_rtl_arc4.dut.pt_addr] = tb_rtl_arc4.dut.p.pad[tb_rtl_arc4.dut.p.k] ^ ciphertext[tb_rtl_arc4.dut.p.k + 8'b1];
        end


        for (int i = 0; i < 8'd53; i++) begin
           if (exp_pt[i] !== pt[i]) begin 
                $display("PT 2[%d] ERROR: Expected pt is %h, actual pt is %h", i[7:0], exp_pt[i], pt[i]);
                err = 1'b1;
            end
        end


        #50;
        if (tb_rtl_arc4.dut.done_prga !== 1'b1) begin
            $display("ERROR 24A: Expected done_prga is %d, actual done_prga is %d", 1'b1, tb_rtl_arc4.dut.done_prga);
            err = 1'b1;
        end
        if (tb_rtl_arc4.dut.rdy !== 1'b1) begin
            $display("ERROR 24B: Expected rdy is %d, actual rdy is %d", 1'b1, tb_rtl_arc4.dut.rdy);
            err = 1'b1;
        end

        if (~err)
            $display("SUCCESS: All tests passed.");
        $stop;
    end

endmodule
module tb_rtl_arc4();


    logic clk, rst_n, en, rdy, pt_wren, err;
    logic [23:0] key;
    logic [7:0] ct_addr, ct_rddata, pt_addr, pt_rddata, pt_wrdata;


    logic [7:0] exp_ksa [255:0];
    logic [7:0] exp_pad [255:0];
    logic [7:0] exp_pt [255:0];
    logic [7:0] ciphertext [255:0];
    logic [7:0] pt [255:0];

    arc4 dut(.*);

    initial begin
        clk = 1;
        forever #5 clk = ~clk;
    end

    initial begin
        err = 1'b0;


        $readmemh("ksa_res.txt", exp_ksa);
        $readmemh("pad_res.txt", exp_pad);
        $readmemh("prga_res.txt", exp_pt);
        $readmemh("test1.memh", ciphertext);

        `define IDLE  2'b00
        `define START 2'b01


        rst_n = 1'bx; en = 1'bx;
        #10;
        if (tb_rtl_arc4.dut.rdy !== 1'b0) begin
            $display("ERROR 1A: Expected rdy is %d, actual rdy is %d", 1'b0, tb_rtl_arc4.dut.rdy);
            err = 1'b1;
        end
        if (tb_rtl_arc4.dut.state !== `IDLE) begin
            $display("ERROR 1B: Expected state is %d, actual state is %d", `IDLE, tb_rtl_arc4.dut.state);
            err = 1'b1;
        end


        rst_n = 1'b0; en = 1'b0; key = 24'h1E4600;
        @(negedge clk);
        if (tb_rtl_arc4.dut.rdy !== 1'b0) begin
            $display("ERROR 2A: Expected rdy is %d, actual rdy is %d", 1'b0, tb_rtl_arc4.dut.rdy);
            err = 1'b1;
        end
        if (tb_rtl_arc4.dut.state !== `IDLE) begin
            $display("ERROR 2B: Expected state is %d, actual state is %d", `IDLE, tb_rtl_arc4.dut.state);
            err = 1'b1;
        end


        rst_n = 1'b1;
        @(posedge clk);
        if (tb_rtl_arc4.dut.rdy !== 1'b0) begin
            $display("ERROR 3A: Expected rdy is %d, actual rdy is %d", 1'b0, tb_rtl_arc4.dut.rdy);
            err = 1'b1;
        end
        if (tb_rtl_arc4.dut.state !== `IDLE) begin
            $display("ERROR 3B: Expected state is %d, actual state is %d", `IDLE, tb_rtl_arc4.dut.state);
            err = 1'b1;
        end


        en = 1'b1; ct_rddata = ciphertext[0];
        @(posedge clk);
        if (tb_rtl_arc4.dut.rdy !== 1'b1) begin
            $display("ERROR 4A: Expected rdy is %d, actual rdy is %d", 1'b1, tb_rtl_arc4.dut.rdy);
            err = 1'b1;
        end
        if (tb_rtl_arc4.dut.state !== `IDLE) begin
            $display("ERROR 4B: Expected state is %d, actual state is %d", `IDLE, tb_rtl_arc4.dut.state);
            err = 1'b1;
        end


        en = 1'b0;
        @(posedge clk);
        if (tb_rtl_arc4.dut.rdy !== 1'b0) begin
            $display("ERROR 5A: Expected rdy is %d, actual rdy is %d", 1'b0, tb_rtl_arc4.dut.rdy);
            err = 1'b1;
        end
        if (tb_rtl_arc4.dut.state !== `START) begin
            $display("ERROR 5B: Expected state is %d, actual state is %d", `START, tb_rtl_arc4.dut.state);
            err = 1'b1;
        end


        wait (tb_rtl_arc4.dut.done_init == 1'b1);
        for (int i = 0; i < 256; i++) begin
            if (tb_rtl_arc4.dut.s.altsyncram_component.m_default.altsyncram_inst.mem_data[i] !== i) begin
                $display("INIT MEM ERR: Expected value is %d, actual value is %d", i, tb_rtl_arc4.dut.s.altsyncram_component.m_default.altsyncram_inst.mem_data[i]);
                err = 1'b1;
            end
        end


        wait (tb_rtl_arc4.dut.done_ksa == 1'b1);
        for (int i = 0; i < 256; i++) begin
            if (tb_rtl_arc4.dut.s.altsyncram_component.m_default.altsyncram_inst.mem_data[i] !== exp_ksa[i]) begin
                $display("KSA MEM ERR: Expected value is %d, actual value is %d", exp_ksa[i], tb_rtl_arc4.dut.s.altsyncram_component.m_default.altsyncram_inst.mem_data[i]);
                err = 1'b1;
            end
        end


        ct_rddata = ciphertext[0];
        @(posedge clk);

        for (int i = 0; i < 8'h49; i++) begin
            @(posedge clk);
            @(posedge clk);
            ct_rddata = ciphertext[tb_rtl_arc4.dut.ct_addr];
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
        end


        @(posedge clk);
        for (int i = 0; i <= 8'h49; i++) begin
            if (tb_rtl_arc4.dut.p.ct_mem[i] !== ciphertext[i]) begin 
                $display("CT[%d] ERROR: Expected ct is %h, actual ct is %h", i[7:0], ciphertext[i], tb_rtl_arc4.dut.p.ct_mem[i]);
                err = 1'b1;
            end
        end


        for (int i = 0; i < 8'h49; i++) begin
            if (tb_rtl_arc4.dut.p.pad[i] !== exp_pad[i]) begin 
                $display("PAD[%d] ERROR: Expected pad is %h, actual pad is %h", i[7:0], exp_pad[i], tb_rtl_arc4.dut.p.pad[i]);
                err = 1'b1;
            end
        end


        pt[0] = tb_rtl_arc4.dut.p.message_length;
        for (int k = 0; k < 8'h49; k++) begin
            @(posedge clk);
            pt[tb_rtl_arc4.dut.pt_addr] = tb_rtl_arc4.dut.p.pad[tb_rtl_arc4.dut.p.k] ^ ciphertext[tb_rtl_arc4.dut.p.k + 8'b1];
        end


        for (int i = 0; i < 8'h49; i++) begin
           if (exp_pt[i] !== pt[i]) begin 
                $display("PT[%d] ERROR: Expected pt is %h, actual pt is %h", i[7:0], exp_pt[i], pt[i]);
                err = 1'b1;
            end
        end


        #50;
        if (tb_rtl_arc4.dut.done_prga !== 1'b1) begin
            $display("ERROR 12A: Expected done_prga is %d, actual done_prga is %d", 1'b1, tb_rtl_arc4.dut.done_prga);
            err = 1'b1;
        end
        if (tb_rtl_arc4.dut.rdy !== 1'b1) begin
            $display("ERROR 12B: Expected rdy is %d, actual rdy is %d", 1'b1, tb_rtl_arc4.dut.rdy);
            err = 1'b1;
        end




        $readmemh("ksa_res2.txt", exp_ksa);
        $readmemh("pad_res2.txt", exp_pad);
        $readmemh("prga_res2.txt", exp_pt);
        $readmemh("test2.memh", ciphertext);


        #10;
        if (tb_rtl_arc4.dut.rdy !== 1'b1) begin
            $display("ERROR 13A: Expected rdy is %d, actual rdy is %d", 1'b1, tb_rtl_arc4.dut.rdy);
            err = 1'b1;
        end
        if (tb_rtl_arc4.dut.state !== `IDLE) begin
            $display("ERROR 13B: Expected state is %d, actual state is %d", `IDLE, tb_rtl_arc4.dut.state);
            err = 1'b1;
        end


        rst_n = 1'b0; en = 1'b0; key = 24'h000018;
        @(negedge clk);
        if (tb_rtl_arc4.dut.rdy !== 1'b0) begin
            $display("ERROR 14A: Expected rdy is %d, actual rdy is %d", 1'b0, tb_rtl_arc4.dut.rdy);
            err = 1'b1;
        end
        if (tb_rtl_arc4.dut.state !== `IDLE) begin
            $display("ERROR 14B: Expected state is %d, actual state is %d", `IDLE, tb_rtl_arc4.dut.state);
            err = 1'b1;
        end


        rst_n = 1'b1;
        @(posedge clk);
        if (tb_rtl_arc4.dut.rdy !== 1'b0) begin
            $display("ERROR 15A: Expected rdy is %d, actual rdy is %d", 1'b0, tb_rtl_arc4.dut.rdy);
            err = 1'b1;
        end
        if (tb_rtl_arc4.dut.state !== `IDLE) begin
            $display("ERROR 15B: Expected state is %d, actual state is %d", `IDLE, tb_rtl_arc4.dut.state);
            err = 1'b1;
        end


        en = 1'b1; ct_rddata = ciphertext[0];
        @(posedge clk);
        if (tb_rtl_arc4.dut.rdy !== 1'b1) begin
            $display("ERROR 16A: Expected rdy is %d, actual rdy is %d", 1'b1, tb_rtl_arc4.dut.rdy);
            err = 1'b1;
        end
        if (tb_rtl_arc4.dut.state !== `IDLE) begin
            $display("ERROR 16B: Expected state is %d, actual state is %d", `IDLE, tb_rtl_arc4.dut.state);
            err = 1'b1;
        end


        en = 1'b0;
        @(posedge clk);
        if (tb_rtl_arc4.dut.rdy !== 1'b0) begin
            $display("ERROR 17A: Expected rdy is %d, actual rdy is %d", 1'b0, tb_rtl_arc4.dut.rdy);
            err = 1'b1;
        end
        if (tb_rtl_arc4.dut.state !== `START) begin
            $display("ERROR 17B: Expected state is %d, actual state is %d", `START, tb_rtl_arc4.dut.state);
            err = 1'b1;
        end


        wait (tb_rtl_arc4.dut.done_init == 1'b1);
        for (int i = 0; i < 256; i++) begin
            if (tb_rtl_arc4.dut.s.altsyncram_component.m_default.altsyncram_inst.mem_data[i] !== i) begin
                $display("INIT 2 MEM ERR: Expected value is %d, actual value is %d", i, tb_rtl_arc4.dut.s.altsyncram_component.m_default.altsyncram_inst.mem_data[i]);
                err = 1'b1;
            end
        end


        wait (tb_rtl_arc4.dut.done_ksa == 1'b1);
        for (int i = 0; i < 256; i++) begin
            if (tb_rtl_arc4.dut.s.altsyncram_component.m_default.altsyncram_inst.mem_data[i] !== exp_ksa[i]) begin
                $display("KSA 2 MEM ERR: Expected value is %d, actual value is %d", exp_ksa[i], tb_rtl_arc4.dut.s.altsyncram_component.m_default.altsyncram_inst.mem_data[i]);
                err = 1'b1;
            end
        end


        ct_rddata = ciphertext[0];
        @(posedge clk);

        for (int i = 0; i < 8'd53; i++) begin
            @(posedge clk);
            @(posedge clk);
            ct_rddata = ciphertext[tb_rtl_arc4.dut.ct_addr];
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
        end


        @(posedge clk);
        for (int i = 0; i <= 8'd53; i++) begin
            if (tb_rtl_arc4.dut.p.ct_mem[i] !== ciphertext[i]) begin 
                $display("CT 2[%d] ERROR: Expected ct is %h, actual ct is %h", i[7:0], ciphertext[i], tb_rtl_arc4.dut.p.ct_mem[i]);
                err = 1'b1;
            end
        end


        for (int i = 0; i < 8'd53; i++) begin
            if (tb_rtl_arc4.dut.p.pad[i] !== exp_pad[i]) begin 
                $display("PAD 2[%d] ERROR: Expected pad is %h, actual pad is %h", i[7:0], exp_pad[i], tb_rtl_arc4.dut.p.pad[i]);
                err = 1'b1;
            end
        end


        pt[0] = tb_rtl_arc4.dut.p.message_length;
        for (int k = 0; k < 8'd53; k++) begin
            @(posedge clk);
            pt[tb_rtl_arc4.dut.pt_addr] = tb_rtl_arc4.dut.p.pad[tb_rtl_arc4.dut.p.k] ^ ciphertext[tb_rtl_arc4.dut.p.k + 8'b1];
        end


        for (int i = 0; i < 8'd53; i++) begin
           if (exp_pt[i] !== pt[i]) begin 
                $display("PT 2[%d] ERROR: Expected pt is %h, actual pt is %h", i[7:0], exp_pt[i], pt[i]);
                err = 1'b1;
            end
        end


        #50;
        if (tb_rtl_arc4.dut.done_prga !== 1'b1) begin
            $display("ERROR 24A: Expected done_prga is %d, actual done_prga is %d", 1'b1, tb_rtl_arc4.dut.done_prga);
            err = 1'b1;
        end
        if (tb_rtl_arc4.dut.rdy !== 1'b1) begin
            $display("ERROR 24B: Expected rdy is %d, actual rdy is %d", 1'b1, tb_rtl_arc4.dut.rdy);
            err = 1'b1;
        end

        if (~err)
            $display("SUCCESS: All tests passed.");
        $stop;
    end

endmodule