data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_core/auc_mmulfinal.v
data/verilator_xmls/8ded27ed-e4df-4f13-8d4d-d0d04e50341b.xml
module auc_mmulfinal
    (
     clk,
     rst,
     

     final_en,


     final_auvld,
     final_audat,
     final_aurswap,
     

     final_done,


     final_opcode,
     final_auen,
     final_carry,
     final_swapvl,
     final_swapop,
     

     final_ra,
     final_wa,
     final_we,
     final_wd
     );



parameter           WID   = 256;
parameter           CURWID = 255;
parameter           AWID  = 5;
parameter           OPWID = 4;

localparam ZERO = 0;
localparam BYTE = 8;



localparam FA   = 4'b0000;
localparam SUB  = 4'b1000;
localparam MUL  = 4'b0001;
localparam INV  = 4'b0010;
localparam EXP  = 4'b0011;
localparam SWAP = 4'b0100;



localparam          X_G     = 0;
localparam          Y_G     = 1;
localparam          X_3G    = 2;
localparam          Y_3G    = 3;
localparam          Z_3G    = 3;
localparam          X_5G    = 5;
localparam          Y_5G    = 6;
localparam          Z_5G    = 7;
localparam          X_7G    = 8;
localparam          Y_7G    = 9;
localparam          Z_7G    = 10;

localparam          K_NUM   = 11;
localparam          K_INV   = 12;
localparam          R_NUM   = 13;
localparam          S_NUM   = 14;
localparam          X_KG    = 15;
localparam          HASH    = 16;
localparam          PKEY    = 17;
localparam          ZRRAM   = 18;
localparam          ONERAM  = 19;

localparam          TEMP0   = 20;
localparam          TEMP1   = 21;
localparam          TEMP2   = 22;
localparam          TEMP3   = 23;
localparam          TEMP4   = 24;
localparam          TEMP5   = 25;
localparam          TEMP6   = 26;   
localparam          TEMP7   = 27;
localparam          TEMP8   = 28;

localparam          S_RP    = 29;
localparam          S_RPH   = 30;
localparam          BLNK    = 31;

localparam          X2    = 7;
localparam          Z2    = 8;
localparam          X3    = 9;
localparam          Z3    = 10;

localparam          PS2 = 29;
localparam          ACCIDENT   = 30;
localparam          A24   = 31;


localparam          FSWID       = 4;
localparam          F_IDLE      = 4'd0;
localparam          F_SWAPZ2    = 4'd1;
localparam          F_SWAPZ3    = 4'd2;
localparam          F_SWAPZ32   = 4'd3;
localparam          F_SWAPX2    = 4'd4;
localparam          F_SWAPX3    = 4'd5;
localparam          F_SWAPX32   = 4'd6;
localparam          F_SWAPX33   = 4'd7;
localparam          F_POW       = 4'd8;
localparam          F_POW2      = 4'd9;
localparam          F_RSLT      = 4'd10;
localparam          F_DONE      = 4'd11;




input     clk;
input     rst;
     

input     final_en;


input [WID-1:0] final_audat;
input           final_auvld;
input [WID-1:0] final_aurswap;


output          final_done;


output [OPWID-1:0] final_opcode;
output             final_auen;
output             final_carry;
output             final_swapop;
output             final_swapvl;


output [AWID-1:0]  final_ra;
output [AWID-1:0]  final_wa;
output             final_we;
output [WID-1:0]   final_wd;







reg [FSWID-1:0] final_state;
reg             final_done;

wire      finalisidle; 

assign    finalisidle = final_state == F_IDLE;

wire      finalisidlevld; 

assign    finalisidlevld = finalisidle & final_auvld;

wire      finalisswapz2; 

assign    finalisswapz2 = final_state == F_SWAPZ2;

wire      finalisswapz3; 

assign    finalisswapz3 = final_state == F_SWAPZ3;

wire      finalisswapz3vld; 

assign    finalisswapz3vld = finalisswapz3 & final_auvld;

wire      finalisswapz32; 

assign    finalisswapz32 = final_state == F_SWAPZ32;

wire      finalisswapx2; 

assign    finalisswapx2 = final_state == F_SWAPX2;

wire      finalisswapx3; 

assign    finalisswapx3 = final_state == F_SWAPX3;

wire      finalisswapx3vld; 

assign    finalisswapx3vld = finalisswapx3 & final_auvld;

wire      finalisswapx32; 

assign    finalisswapx32 = final_state == F_SWAPX32;

wire      finalisswapx33; 

assign    finalisswapx33 = final_state == F_SWAPX33;

wire      finalispow; 

assign    finalispow = final_state == F_POW;

wire      finalispowvld; 

assign    finalispowvld = finalispow & final_auvld;

wire      finalispow2; 

assign    finalispow2 = final_state == F_POW2;

wire      finalisrslt; 

assign    finalisrslt = final_state == F_RSLT;

wire      finalisrsltvld; 

assign    finalisrsltvld = finalisrslt & final_auvld;

wire      finalisdone; 

assign    finalisdone = final_state == F_DONE;

always@(posedge clk)
    begin
    if(rst)
        begin
        final_state <= F_IDLE;
        final_done <= 1'b0;
        end
    else
        begin
        if(final_en & finalisidle)
            begin
            final_state <= F_SWAPZ2;
            end
        else if(finalisswapz2)
            begin
            final_state <= F_SWAPZ3;
            end
        else if(finalisswapz3vld)
            begin
            final_state <= F_SWAPZ32;
            end
        else if(finalisswapz32)
            begin
            final_state <= F_SWAPX2;
            end
        else if(finalisswapx2)
            begin
            final_state <= F_SWAPX3;
            end
        else if(finalisswapx3vld)
            begin
            final_state <= F_SWAPX32;
            end
        else if(finalisswapx32)
            begin
            final_state <= F_SWAPX33;
            end
        else if(finalisswapx33)
            begin
            final_state <= F_POW;
            end
        else if(finalispowvld)
            begin
            final_state <= F_POW2;
            end
        else if(finalispow2)
            begin
            final_state <= F_RSLT;
            end
        else if(finalisrsltvld)
            begin
            final_state <= F_DONE;
            end
        else if(finalisdone)
            begin
            final_done <= 1'b1;
            final_state <= F_IDLE;
            end
        else
            begin
            final_state <= final_state;
            final_done <= 1'b0;
            end
        end
    end



reg [WID-1:0] final_audat1;

always@(posedge clk)
    begin
    if(rst)
        begin
        final_audat1 <= 256'd0;
        end
    else
        begin
        if(final_auvld)
            begin
            final_audat1 <= final_audat;
            end
        end
    end

reg [WID-1:0] final_aurswap1;

always@(posedge clk)
    begin
    if(rst)
        begin
        final_aurswap1 <= 256'd0;
        end
    else
        begin
        if(final_auvld)
            begin
            final_aurswap1 <= final_aurswap;
            end
        end
    end


wire [WID-1:0] rsltdecode;

assign         rsltdecode[1*BYTE-1:0]      = final_audat1[32*BYTE-1:31*BYTE];
assign         rsltdecode[2*BYTE-1:1*BYTE] = final_audat1[31*BYTE-1:30*BYTE];
assign         rsltdecode[3*BYTE-1:2*BYTE] = final_audat1[30*BYTE-1:29*BYTE];
assign         rsltdecode[4*BYTE-1:3*BYTE] = final_audat1[29*BYTE-1:28*BYTE];
assign         rsltdecode[5*BYTE-1:4*BYTE] = final_audat1[28*BYTE-1:27*BYTE];
assign         rsltdecode[6*BYTE-1:5*BYTE] = final_audat1[27*BYTE-1:26*BYTE];
assign         rsltdecode[7*BYTE-1:6*BYTE] = final_audat1[26*BYTE-1:25*BYTE];
assign         rsltdecode[8*BYTE-1:7*BYTE] = final_audat1[25*BYTE-1:24*BYTE];
assign         rsltdecode[9*BYTE-1:8*BYTE] = final_audat1[24*BYTE-1:23*BYTE];
assign         rsltdecode[10*BYTE-1:9*BYTE] = final_audat1[23*BYTE-1:22*BYTE];
assign         rsltdecode[11*BYTE-1:10*BYTE] = final_audat1[22*BYTE-1:21*BYTE];
assign         rsltdecode[12*BYTE-1:11*BYTE] = final_audat1[21*BYTE-1:20*BYTE];
assign         rsltdecode[13*BYTE-1:12*BYTE] = final_audat1[20*BYTE-1:19*BYTE];
assign         rsltdecode[14*BYTE-1:13*BYTE] = final_audat1[19*BYTE-1:18*BYTE];
assign         rsltdecode[15*BYTE-1:14*BYTE] = final_audat1[18*BYTE-1:17*BYTE];
assign         rsltdecode[16*BYTE-1:15*BYTE] = final_audat1[17*BYTE-1:16*BYTE];
assign         rsltdecode[17*BYTE-1:16*BYTE] = final_audat1[16*BYTE-1:15*BYTE];
assign         rsltdecode[18*BYTE-1:17*BYTE] = final_audat1[15*BYTE-1:14*BYTE];
assign         rsltdecode[19*BYTE-1:18*BYTE] = final_audat1[14*BYTE-1:13*BYTE];
assign         rsltdecode[20*BYTE-1:19*BYTE] = final_audat1[13*BYTE-1:12*BYTE];
assign         rsltdecode[21*BYTE-1:20*BYTE] = final_audat1[12*BYTE-1:11*BYTE];
assign         rsltdecode[22*BYTE-1:21*BYTE] = final_audat1[11*BYTE-1:10*BYTE];
assign         rsltdecode[23*BYTE-1:22*BYTE] = final_audat1[10*BYTE-1:9*BYTE];
assign         rsltdecode[24*BYTE-1:23*BYTE] = final_audat1[9*BYTE-1:8*BYTE];
assign         rsltdecode[25*BYTE-1:24*BYTE] = final_audat1[8*BYTE-1:7*BYTE];
assign         rsltdecode[26*BYTE-1:25*BYTE] = final_audat1[7*BYTE-1:6*BYTE];
assign         rsltdecode[27*BYTE-1:26*BYTE] = final_audat1[6*BYTE-1:5*BYTE];
assign         rsltdecode[28*BYTE-1:27*BYTE] = final_audat1[5*BYTE-1:4*BYTE];
assign         rsltdecode[29*BYTE-1:28*BYTE] = final_audat1[4*BYTE-1:3*BYTE];
assign         rsltdecode[30*BYTE-1:29*BYTE] = final_audat1[3*BYTE-1:2*BYTE];
assign         rsltdecode[31*BYTE-1:30*BYTE] = final_audat1[2*BYTE-1:1*BYTE];
assign         rsltdecode[32*BYTE-1:31*BYTE] = final_audat1[1*BYTE-1:0];


reg [AWID-1:0]  final_ra;
reg [AWID-1:0]  final_wa;
reg             final_we;
reg [WID-1:0]   final_wd;

always@(posedge clk)
    begin
    final_wd <= finalisswapx2? final_aurswap1:
                finalisswapx33? final_aurswap1:
                finalisdone? rsltdecode:
                final_audat1;
    end

always@(posedge clk)
    begin
    final_wa <= finalisswapz32? Z3:
                finalisswapx2? Z2:
                finalisswapx32? X3:
                finalisswapx33? X2:
                finalispow2? X_KG:
                finalisdone? X_KG:
                ACCIDENT;
    end

always@(posedge clk)
    begin
    final_we <= finalisswapz32
                | finalisswapx2
                | finalisswapx3
                | finalisswapx33
                | finalispow2
                | finalisdone;
    end

always@(posedge clk)
    begin
    final_ra <= finalisswapz2? Z2:
                finalisswapz3? Z3:
                finalisswapx2? X2:
                finalisswapx3? X3:
                finalisswapx33? Z2:
                finalispow? Z2:
                finalispow2? X2:
                finalisrslt? X_KG:
                ZRRAM; 
    end



reg [OPWID-1:0] final_opcode;
reg             final_auen;
reg             final_carry;
reg             final_swapop;
wire            final_swapvl;


assign          final_swapvl = 1'b0;



always@(posedge clk)
    begin
    if(rst)
        begin
        final_opcode[1:0] <= ZERO;
        final_opcode[2] <= 1'b1;
        final_opcode[3] <= 1'b0;
        final_swapop <= 1'b0;
        final_carry <= 1'b0;
        end
    else
        begin
        {final_carry,final_swapop,final_opcode[1:0]} <= finalisswapz3? SWAP:
                                                        finalisswapx3? SWAP:
                                                        finalispow? INV:
                                                        finalisrslt? MUL:
                                                        4'b0000; 
        end
    end

always@(posedge clk)
    begin
    if(rst)
        begin
        final_auen <= 1'b0;
        end
    else
        begin
        if(finalisswapz2)
            begin
            final_auen <= 1'b1;    
            end
        else if(finalisswapx2)
            begin
            final_auen <= 1'b1;    
            end
        else if(finalisswapx33)
            begin
            final_auen <= 1'b1;        
            end
        else if(finalispow2)
            begin
            final_auen <= 1'b1;        
            end
        else
            begin
            final_auen <= 1'b0;
            end
        end
    end



endmodule
module auc_mmulfinal
    (
     clk,
     rst,
     

     final_en,


     final_auvld,
     final_audat,
     final_aurswap,
     

     final_done,


     final_opcode,
     final_auen,
     final_carry,
     final_swapvl,
     final_swapop,
     

     final_ra,
     final_wa,
     final_we,
     final_wd
     );




parameter           WID   = 256;
parameter           CURWID = 255;
parameter           AWID  = 5;
parameter           OPWID = 4;

localparam ZERO = 0;
localparam BYTE = 8;



localparam FA   = 4'b0000;
localparam SUB  = 4'b1000;
localparam MUL  = 4'b0001;
localparam INV  = 4'b0010;
localparam EXP  = 4'b0011;
localparam SWAP = 4'b0100;



localparam          X_G     = 0;
localparam          Y_G     = 1;
localparam          X_3G    = 2;
localparam          Y_3G    = 3;
localparam          Z_3G    = 3;
localparam          X_5G    = 5;
localparam          Y_5G    = 6;
localparam          Z_5G    = 7;
localparam          X_7G    = 8;
localparam          Y_7G    = 9;
localparam          Z_7G    = 10;

localparam          K_NUM   = 11;
localparam          K_INV   = 12;
localparam          R_NUM   = 13;
localparam          S_NUM   = 14;
localparam          X_KG    = 15;
localparam          HASH    = 16;
localparam          PKEY    = 17;
localparam          ZRRAM   = 18;
localparam          ONERAM  = 19;

localparam          TEMP0   = 20;
localparam          TEMP1   = 21;
localparam          TEMP2   = 22;
localparam          TEMP3   = 23;
localparam          TEMP4   = 24;
localparam          TEMP5   = 25;
localparam          TEMP6   = 26;   
localparam          TEMP7   = 27;
localparam          TEMP8   = 28;

localparam          S_RP    = 29;
localparam          S_RPH   = 30;
localparam          BLNK    = 31;

localparam          X2    = 7;
localparam          Z2    = 8;
localparam          X3    = 9;
localparam          Z3    = 10;

localparam          PS2 = 29;
localparam          ACCIDENT   = 30;
localparam          A24   = 31;


localparam          FSWID       = 4;
localparam          F_IDLE      = 4'd0;
localparam          F_SWAPZ2    = 4'd1;
localparam          F_SWAPZ3    = 4'd2;
localparam          F_SWAPZ32   = 4'd3;
localparam          F_SWAPX2    = 4'd4;
localparam          F_SWAPX3    = 4'd5;
localparam          F_SWAPX32   = 4'd6;
localparam          F_SWAPX33   = 4'd7;
localparam          F_POW       = 4'd8;
localparam          F_POW2      = 4'd9;
localparam          F_RSLT      = 4'd10;
localparam          F_DONE      = 4'd11;




input     clk;
input     rst;
     

input     final_en;


input [WID-1:0] final_audat;
input           final_auvld;
input [WID-1:0] final_aurswap;


output          final_done;


output [OPWID-1:0] final_opcode;
output             final_auen;
output             final_carry;
output             final_swapop;
output             final_swapvl;


output [AWID-1:0]  final_ra;
output [AWID-1:0]  final_wa;
output             final_we;
output [WID-1:0]   final_wd;







reg [FSWID-1:0] final_state;
reg             final_done;

wire      finalisidle; 

assign    finalisidle = final_state == F_IDLE;

wire      finalisidlevld; 

assign    finalisidlevld = finalisidle & final_auvld;

wire      finalisswapz2; 

assign    finalisswapz2 = final_state == F_SWAPZ2;

wire      finalisswapz3; 

assign    finalisswapz3 = final_state == F_SWAPZ3;

wire      finalisswapz3vld; 

assign    finalisswapz3vld = finalisswapz3 & final_auvld;

wire      finalisswapz32; 

assign    finalisswapz32 = final_state == F_SWAPZ32;

wire      finalisswapx2; 

assign    finalisswapx2 = final_state == F_SWAPX2;

wire      finalisswapx3; 

assign    finalisswapx3 = final_state == F_SWAPX3;

wire      finalisswapx3vld; 

assign    finalisswapx3vld = finalisswapx3 & final_auvld;

wire      finalisswapx32; 

assign    finalisswapx32 = final_state == F_SWAPX32;

wire      finalisswapx33; 

assign    finalisswapx33 = final_state == F_SWAPX33;

wire      finalispow; 

assign    finalispow = final_state == F_POW;

wire      finalispowvld; 

assign    finalispowvld = finalispow & final_auvld;

wire      finalispow2; 

assign    finalispow2 = final_state == F_POW2;

wire      finalisrslt; 

assign    finalisrslt = final_state == F_RSLT;

wire      finalisrsltvld; 

assign    finalisrsltvld = finalisrslt & final_auvld;

wire      finalisdone; 

assign    finalisdone = final_state == F_DONE;

always@(posedge clk)
    begin
    if(rst)
        begin
        final_state <= F_IDLE;
        final_done <= 1'b0;
        end
    else
        begin
        if(final_en & finalisidle)
            begin
            final_state <= F_SWAPZ2;
            end
        else if(finalisswapz2)
            begin
            final_state <= F_SWAPZ3;
            end
        else if(finalisswapz3vld)
            begin
            final_state <= F_SWAPZ32;
            end
        else if(finalisswapz32)
            begin
            final_state <= F_SWAPX2;
            end
        else if(finalisswapx2)
            begin
            final_state <= F_SWAPX3;
            end
        else if(finalisswapx3vld)
            begin
            final_state <= F_SWAPX32;
            end
        else if(finalisswapx32)
            begin
            final_state <= F_SWAPX33;
            end
        else if(finalisswapx33)
            begin
            final_state <= F_POW;
            end
        else if(finalispowvld)
            begin
            final_state <= F_POW2;
            end
        else if(finalispow2)
            begin
            final_state <= F_RSLT;
            end
        else if(finalisrsltvld)
            begin
            final_state <= F_DONE;
            end
        else if(finalisdone)
            begin
            final_done <= 1'b1;
            final_state <= F_IDLE;
            end
        else
            begin
            final_state <= final_state;
            final_done <= 1'b0;
            end
        end
    end



reg [WID-1:0] final_audat1;

always@(posedge clk)
    begin
    if(rst)
        begin
        final_audat1 <= 256'd0;
        end
    else
        begin
        if(final_auvld)
            begin
            final_audat1 <= final_audat;
            end
        end
    end

reg [WID-1:0] final_aurswap1;

always@(posedge clk)
    begin
    if(rst)
        begin
        final_aurswap1 <= 256'd0;
        end
    else
        begin
        if(final_auvld)
            begin
            final_aurswap1 <= final_aurswap;
            end
        end
    end


wire [WID-1:0] rsltdecode;

assign         rsltdecode[1*BYTE-1:0]      = final_audat1[32*BYTE-1:31*BYTE];
assign         rsltdecode[2*BYTE-1:1*BYTE] = final_audat1[31*BYTE-1:30*BYTE];
assign         rsltdecode[3*BYTE-1:2*BYTE] = final_audat1[30*BYTE-1:29*BYTE];
assign         rsltdecode[4*BYTE-1:3*BYTE] = final_audat1[29*BYTE-1:28*BYTE];
assign         rsltdecode[5*BYTE-1:4*BYTE] = final_audat1[28*BYTE-1:27*BYTE];
assign         rsltdecode[6*BYTE-1:5*BYTE] = final_audat1[27*BYTE-1:26*BYTE];
assign         rsltdecode[7*BYTE-1:6*BYTE] = final_audat1[26*BYTE-1:25*BYTE];
assign         rsltdecode[8*BYTE-1:7*BYTE] = final_audat1[25*BYTE-1:24*BYTE];
assign         rsltdecode[9*BYTE-1:8*BYTE] = final_audat1[24*BYTE-1:23*BYTE];
assign         rsltdecode[10*BYTE-1:9*BYTE] = final_audat1[23*BYTE-1:22*BYTE];
assign         rsltdecode[11*BYTE-1:10*BYTE] = final_audat1[22*BYTE-1:21*BYTE];
assign         rsltdecode[12*BYTE-1:11*BYTE] = final_audat1[21*BYTE-1:20*BYTE];
assign         rsltdecode[13*BYTE-1:12*BYTE] = final_audat1[20*BYTE-1:19*BYTE];
assign         rsltdecode[14*BYTE-1:13*BYTE] = final_audat1[19*BYTE-1:18*BYTE];
assign         rsltdecode[15*BYTE-1:14*BYTE] = final_audat1[18*BYTE-1:17*BYTE];
assign         rsltdecode[16*BYTE-1:15*BYTE] = final_audat1[17*BYTE-1:16*BYTE];
assign         rsltdecode[17*BYTE-1:16*BYTE] = final_audat1[16*BYTE-1:15*BYTE];
assign         rsltdecode[18*BYTE-1:17*BYTE] = final_audat1[15*BYTE-1:14*BYTE];
assign         rsltdecode[19*BYTE-1:18*BYTE] = final_audat1[14*BYTE-1:13*BYTE];
assign         rsltdecode[20*BYTE-1:19*BYTE] = final_audat1[13*BYTE-1:12*BYTE];
assign         rsltdecode[21*BYTE-1:20*BYTE] = final_audat1[12*BYTE-1:11*BYTE];
assign         rsltdecode[22*BYTE-1:21*BYTE] = final_audat1[11*BYTE-1:10*BYTE];
assign         rsltdecode[23*BYTE-1:22*BYTE] = final_audat1[10*BYTE-1:9*BYTE];
assign         rsltdecode[24*BYTE-1:23*BYTE] = final_audat1[9*BYTE-1:8*BYTE];
assign         rsltdecode[25*BYTE-1:24*BYTE] = final_audat1[8*BYTE-1:7*BYTE];
assign         rsltdecode[26*BYTE-1:25*BYTE] = final_audat1[7*BYTE-1:6*BYTE];
assign         rsltdecode[27*BYTE-1:26*BYTE] = final_audat1[6*BYTE-1:5*BYTE];
assign         rsltdecode[28*BYTE-1:27*BYTE] = final_audat1[5*BYTE-1:4*BYTE];
assign         rsltdecode[29*BYTE-1:28*BYTE] = final_audat1[4*BYTE-1:3*BYTE];
assign         rsltdecode[30*BYTE-1:29*BYTE] = final_audat1[3*BYTE-1:2*BYTE];
assign         rsltdecode[31*BYTE-1:30*BYTE] = final_audat1[2*BYTE-1:1*BYTE];
assign         rsltdecode[32*BYTE-1:31*BYTE] = final_audat1[1*BYTE-1:0];


reg [AWID-1:0]  final_ra;
reg [AWID-1:0]  final_wa;
reg             final_we;
reg [WID-1:0]   final_wd;

always@(posedge clk)
    begin
    final_wd <= finalisswapx2? final_aurswap1:
                finalisswapx33? final_aurswap1:
                finalisdone? rsltdecode:
                final_audat1;
    end

always@(posedge clk)
    begin
    final_wa <= finalisswapz32? Z3:
                finalisswapx2? Z2:
                finalisswapx32? X3:
                finalisswapx33? X2:
                finalispow2? X_KG:
                finalisdone? X_KG:
                ACCIDENT;
    end

always@(posedge clk)
    begin
    final_we <= finalisswapz32
                | finalisswapx2
                | finalisswapx3
                | finalisswapx33
                | finalispow2
                | finalisdone;
    end

always@(posedge clk)
    begin
    final_ra <= finalisswapz2? Z2:
                finalisswapz3? Z3:
                finalisswapx2? X2:
                finalisswapx3? X3:
                finalisswapx33? Z2:
                finalispow? Z2:
                finalispow2? X2:
                finalisrslt? X_KG:
                ZRRAM; 
    end



reg [OPWID-1:0] final_opcode;
reg             final_auen;
reg             final_carry;
reg             final_swapop;
wire            final_swapvl;


assign          final_swapvl = 1'b0;



always@(posedge clk)
    begin
    if(rst)
        begin
        final_opcode[1:0] <= ZERO;
        final_opcode[2] <= 1'b1;
        final_opcode[3] <= 1'b0;
        final_swapop <= 1'b0;
        final_carry <= 1'b0;
        end
    else
        begin
        {final_carry,final_swapop,final_opcode[1:0]} <= finalisswapz3? SWAP:
                                                        finalisswapx3? SWAP:
                                                        finalispow? INV:
                                                        finalisrslt? MUL:
                                                        4'b0000; 
        end
    end

always@(posedge clk)
    begin
    if(rst)
        begin
        final_auen <= 1'b0;
        end
    else
        begin
        if(finalisswapz2)
            begin
            final_auen <= 1'b1;    
            end
        else if(finalisswapx2)
            begin
            final_auen <= 1'b1;    
            end
        else if(finalisswapx33)
            begin
            final_auen <= 1'b1;        
            end
        else if(finalispow2)
            begin
            final_auen <= 1'b1;        
            end
        else
            begin
            final_auen <= 1'b0;
            end
        end
    end



endmodule