data/full_repos/permissive/509335294/alu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/509335294/alu.v:31: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                             : ... In instance alu\n  4\'b0110 : res <= (in1<in2);  \n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/509335294/alu.v:46: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                             : ... In instance alu\n  4\'b1001 : res <= in1 < in2;  \n                ^~\n%Error: Exiting due to 2 warning(s)\n'
module alu(
					input[15:0] 			in1, in2, 
					input[3:0] 			sel,

					output reg				branch_enable,
					output reg[15:0] 	res
					);

initial begin
branch_enable = 0;
res = 16'b0;
end


always@(*)begin
	case(sel)

		4'b0000 : res <= in1 + in2;
		4'b0001 : res <= in1 - in2;
		4'b0010 : res <= in1 * in2;
		4'b0011 : begin 
						if(in2 == 0)begin
								res <= 0;
						end else res <= in1 / in2;
						end
		

		4'b0100 : res <= in1 & in2;
		4'b0101 : res <= in1 | in2;
		4'b0110 : res <= (in1<in2);
		

		4'b1000 : begin  


							if(in1 == in2) begin
								branch_enable = 1;

							end else begin 
								branch_enable = 0;

							end
							
						end 
		4'b1001 : res <= in1 < in2;
		4'b1010 : res <= in1 + in2;
		

		
	endcase

end

endmodule
module alu(
					input[15:0] 			in1, in2, 
					input[3:0] 			sel,

					output reg				branch_enable,
					output reg[15:0] 	res
					);


initial begin
branch_enable = 0;
res = 16'b0;
end


always@(*)begin
	case(sel)

		4'b0000 : res <= in1 + in2;
		4'b0001 : res <= in1 - in2;
		4'b0010 : res <= in1 * in2;
		4'b0011 : begin 
						if(in2 == 0)begin
								res <= 0;
						end else res <= in1 / in2;
						end
		

		4'b0100 : res <= in1 & in2;
		4'b0101 : res <= in1 | in2;
		4'b0110 : res <= (in1<in2);
		

		4'b1000 : begin  


							if(in1 == in2) begin
								branch_enable = 1;

							end else begin 
								branch_enable = 0;

							end
							
						end 
		4'b1001 : res <= in1 < in2;
		4'b1010 : res <= in1 + in2;
		

		
	endcase

end

endmodule