data/full_repos/permissive/515598112/2_Verilog_Language/03_Modulels_Hierarchy/05_Modules_and_vectors.v
1: b"%Error: data/full_repos/permissive/515598112/2_Verilog_Language/03_Modulels_Hierarchy/05_Modules_and_vectors.v:12: Cannot find file containing module: 'my_dff8'\n    my_dff8 dff1 ( .clk(clk), .d(d),    .q(bus1) );\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/515598112/2_Verilog_Language/03_Modulels_Hierarchy,data/full_repos/permissive/515598112/my_dff8\n             data/full_repos/permissive/515598112/2_Verilog_Language/03_Modulels_Hierarchy,data/full_repos/permissive/515598112/my_dff8.v\n             data/full_repos/permissive/515598112/2_Verilog_Language/03_Modulels_Hierarchy,data/full_repos/permissive/515598112/my_dff8.sv\n             my_dff8\n             my_dff8.v\n             my_dff8.sv\n             obj_dir/my_dff8\n             obj_dir/my_dff8.v\n             obj_dir/my_dff8.sv\n%Error: data/full_repos/permissive/515598112/2_Verilog_Language/03_Modulels_Hierarchy/05_Modules_and_vectors.v:13: Cannot find file containing module: 'my_dff8'\n    my_dff8 dff2 ( .clk(clk), .d(bus1), .q(bus2) );\n    ^~~~~~~\n%Error: data/full_repos/permissive/515598112/2_Verilog_Language/03_Modulels_Hierarchy/05_Modules_and_vectors.v:14: Cannot find file containing module: 'my_dff8'\n    my_dff8 dff3 ( .clk(clk), .d(bus2), .q(bus3) );\n    ^~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module top_module ( 
    input clk, 
    input [7:0] d, 
    input [1:0] sel, 
    output [7:0] q 
);
    
    wire [7:0] bus1;
    wire [7:0] bus2;
    wire [7:0] bus3;
    
    my_dff8 dff1 ( .clk(clk), .d(d),    .q(bus1) );
    my_dff8 dff2 ( .clk(clk), .d(bus1), .q(bus2) );
    my_dff8 dff3 ( .clk(clk), .d(bus2), .q(bus3) );
    
    always @(*) begin
        case(sel)
            2'b00: q = d;
            2'b01: q = bus1;
            2'b10: q = bus2;
            2'b11: q = bus3;
        endcase
    end

endmodule
module top_module ( 
    input clk, 
    input [7:0] d, 
    input [1:0] sel, 
    output [7:0] q 
);

    
    wire [7:0] bus1;
    wire [7:0] bus2;
    wire [7:0] bus3;
    
    my_dff8 dff1 ( .clk(clk), .d(d),    .q(bus1) );
    my_dff8 dff2 ( .clk(clk), .d(bus1), .q(bus2) );
    my_dff8 dff3 ( .clk(clk), .d(bus2), .q(bus3) );
    
    always @(*) begin
        case(sel)
            2'b00: q = d;
            2'b01: q = bus1;
            2'b10: q = bus2;
            2'b11: q = bus3;
        endcase
    end

endmodule