data/full_repos/permissive/480141277/synch.v
1: b"%Error: data/full_repos/permissive/480141277/synch.v:40: Cannot find file containing module: 'counter'\n counter c(.clk(PS2Clk),.clr(Q2),.rst(rst),.count(cout));\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/480141277,data/full_repos/permissive/480141277/counter\n             data/full_repos/permissive/480141277,data/full_repos/permissive/480141277/counter.v\n             data/full_repos/permissive/480141277,data/full_repos/permissive/480141277/counter.sv\n             counter\n             counter.v\n             counter.sv\n             obj_dir/counter\n             obj_dir/counter.v\n             obj_dir/counter.sv\n%Error: Exiting due to 1 error(s)\n"
module synch(
	input PS2Clk,
	input FPGAClk,
	input rst,
	output midout,
	output [5:0] count
	);
	
	reg clr;
	wire comp20;
	wire [5:0]cout;
	reg Q1;
	reg Q2;
	
	counter c(.clk(PS2Clk),.clr(Q2),.rst(rst),.count(cout));
	assign comp20 = (cout == 32) ? 1 : 0;
	assign count = cout;

	

	
	always @(posedge FPGAClk) begin
		if(FPGAClk)
			Q1 <= comp20;
		else 
			Q1 <= Q1;
	end
	
	assign midout = Q1;
	

	
	always @(posedge FPGAClk) begin
		if(FPGAClk)
			Q2 <= Q1;
		else
			Q2 <= Q2;
	end
	
	
endmodule
module synch(
	input PS2Clk,
	input FPGAClk,
	input rst,
	output midout,
	output [5:0] count
	);

	
	reg clr;
	wire comp20;
	wire [5:0]cout;
	reg Q1;
	reg Q2;
	
	counter c(.clk(PS2Clk),.clr(Q2),.rst(rst),.count(cout));
	assign comp20 = (cout == 32) ? 1 : 0;
	assign count = cout;

	

	
	always @(posedge FPGAClk) begin
		if(FPGAClk)
			Q1 <= comp20;
		else 
			Q1 <= Q1;
	end
	
	assign midout = Q1;
	

	
	always @(posedge FPGAClk) begin
		if(FPGAClk)
			Q2 <= Q1;
		else
			Q2 <= Q2;
	end
	
	
endmodule