data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg_porta.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg_porta.v:29: Cannot find include file: sys.h\n`include "sys.h" // system level definition file which contains the  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg_porta.v:31: Cannot find include file: iop.h\n`include        "iop.h" \n                ^~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module iobdg_dbg_porta (

   iob_io_dbg_data, iob_io_dbg_en, iob_io_dbg_ck_p, iob_io_dbg_ck_n, 
   l2_vis_armin, iob_clk_tr, 

   rst_l, clk, src0_data, src1_data, src2_data, src3_data, src4_data, 
   src0_vld, src1_vld, src2_vld, src3_vld, src4_vld, 
   creg_dbg_enet_ctrl, creg_dbg_enet_idleval, io_trigin
   );





   input                                    rst_l;
   input 				    clk;
   


   input [39:0] 			    src0_data;
   input [39:0] 			    src1_data;
   input [39:0] 			    src2_data;
   input [39:0] 			    src3_data;
   input [39:0] 			    src4_data;

   input 				    src0_vld;
   input 				    src1_vld;
   input 				    src2_vld;
   input 				    src3_vld;
   input 				    src4_vld;

   

   output [39:0] 			    iob_io_dbg_data;
   output 				    iob_io_dbg_en;
   output [2:0] 			    iob_io_dbg_ck_p;
   output [2:0] 			    iob_io_dbg_ck_n;
   
			    

   input [63:0] 			    creg_dbg_enet_ctrl;
   input [63:0] 			    creg_dbg_enet_idleval;

   

   input 				    io_trigin;
   
   output 				    l2_vis_armin;
   output 				    iob_clk_tr;
   


   wire 				    dbg_en;
   wire 				    dbg_armin_en;
   wire 				    dbg_trigin_en;
   wire [3:0] 				    dbg_sel;
   wire [39:0] 				    dbg_idleval;
   
   reg [39:0] 				    mux_data;
   reg 					    mux_vld;

   wire [39:0] 				    dbg_data;

   wire 				    iob_io_dbg_ck_p_next;
   
   wire 				    io_trigin_d1;
   wire 				    io_trigin_d2;
   wire 				    io_trigin_d3;
   wire 				    io_trigin_detected;
   wire 				    iob_clk_tr_a1;

		    



   assign 	dbg_en        = creg_dbg_enet_ctrl[8];
   assign 	dbg_armin_en  = creg_dbg_enet_ctrl[6];
   assign 	dbg_trigin_en = creg_dbg_enet_ctrl[5];
   assign 	dbg_sel       = creg_dbg_enet_ctrl[3:0];
   assign 	dbg_idleval   = creg_dbg_enet_idleval[39:0];
   
   always @(dbg_sel or src0_data or src0_vld or src1_data
	    or src1_vld or src2_data or src2_vld or src3_data
	    or src3_vld or src4_data or src4_vld)
     case (dbg_sel)
       4'b0000:  {mux_vld,mux_data} = {src0_vld,src0_data};
       4'b0001:  {mux_vld,mux_data} = {src1_vld,src1_data};
       4'b0010:  {mux_vld,mux_data} = {src2_vld,src2_data};
       4'b0011:  {mux_vld,mux_data} = {src3_vld,src3_data};
       4'b0100:  {mux_vld,mux_data} = {src4_vld,src4_data};
       default:  {mux_vld,mux_data} = {1'b0,40'b0};
     endcase
   
   assign 	dbg_data = mux_vld ? mux_data : dbg_idleval;

   dff_ns #(40) iob_io_dbg_data_ff (.din(dbg_data),
				    .clk(clk),
				    .q(iob_io_dbg_data));

   dff_ns #(1) iob_io_dbg_en_ff (.din(dbg_en),
				 .clk(clk),
				 .q(iob_io_dbg_en));
   


   assign 	iob_io_dbg_ck_p_next = ~iob_io_dbg_ck_p[0] & dbg_en;
   
   dff_ns #(1) iob_io_dbg_ck_p_ff (.din(iob_io_dbg_ck_p_next),
				   .clk(clk),
				   .q(iob_io_dbg_ck_p[0]));

   assign       iob_io_dbg_ck_p[1] = iob_io_dbg_ck_p[0];
   assign       iob_io_dbg_ck_p[2] = iob_io_dbg_ck_p[0];
   
   assign 	iob_io_dbg_ck_n = ~iob_io_dbg_ck_p;
   
   

   dffrl_ns #(1) io_trigin_d1_ff (.din(io_trigin),
				  .clk(clk),
				  .rst_l(rst_l),
				  .q(io_trigin_d1));

   dffrl_ns #(1) io_trigin_d2_ff (.din(io_trigin_d1),
				  .clk(clk),
				  .rst_l(rst_l),
				  .q(io_trigin_d2));

   dffrl_ns #(1) io_trigin_d3_ff (.din(io_trigin_d2),
				  .clk(clk),
				  .rst_l(rst_l),
				  .q(io_trigin_d3));

   assign 	io_trigin_detected = io_trigin_d2 & ~io_trigin_d3;
   

   assign 	l2_vis_armin = dbg_armin_en & io_trigin_detected;
	 

   assign 	iob_clk_tr_a1 = dbg_trigin_en & io_trigin_detected;

   dffrl_ns #(1) iob_clk_tr_ff (.din(iob_clk_tr_a1),
				.clk(clk),
				.rst_l(rst_l),
				.q(iob_clk_tr));
   
endmodule
module iobdg_dbg_porta (

   iob_io_dbg_data, iob_io_dbg_en, iob_io_dbg_ck_p, iob_io_dbg_ck_n, 
   l2_vis_armin, iob_clk_tr, 

   rst_l, clk, src0_data, src1_data, src2_data, src3_data, src4_data, 
   src0_vld, src1_vld, src2_vld, src3_vld, src4_vld, 
   creg_dbg_enet_ctrl, creg_dbg_enet_idleval, io_trigin
   );






   input                                    rst_l;
   input 				    clk;
   


   input [39:0] 			    src0_data;
   input [39:0] 			    src1_data;
   input [39:0] 			    src2_data;
   input [39:0] 			    src3_data;
   input [39:0] 			    src4_data;

   input 				    src0_vld;
   input 				    src1_vld;
   input 				    src2_vld;
   input 				    src3_vld;
   input 				    src4_vld;

   

   output [39:0] 			    iob_io_dbg_data;
   output 				    iob_io_dbg_en;
   output [2:0] 			    iob_io_dbg_ck_p;
   output [2:0] 			    iob_io_dbg_ck_n;
   
			    

   input [63:0] 			    creg_dbg_enet_ctrl;
   input [63:0] 			    creg_dbg_enet_idleval;

   

   input 				    io_trigin;
   
   output 				    l2_vis_armin;
   output 				    iob_clk_tr;
   


   wire 				    dbg_en;
   wire 				    dbg_armin_en;
   wire 				    dbg_trigin_en;
   wire [3:0] 				    dbg_sel;
   wire [39:0] 				    dbg_idleval;
   
   reg [39:0] 				    mux_data;
   reg 					    mux_vld;

   wire [39:0] 				    dbg_data;

   wire 				    iob_io_dbg_ck_p_next;
   
   wire 				    io_trigin_d1;
   wire 				    io_trigin_d2;
   wire 				    io_trigin_d3;
   wire 				    io_trigin_detected;
   wire 				    iob_clk_tr_a1;

		    



   assign 	dbg_en        = creg_dbg_enet_ctrl[8];
   assign 	dbg_armin_en  = creg_dbg_enet_ctrl[6];
   assign 	dbg_trigin_en = creg_dbg_enet_ctrl[5];
   assign 	dbg_sel       = creg_dbg_enet_ctrl[3:0];
   assign 	dbg_idleval   = creg_dbg_enet_idleval[39:0];
   
   always @(dbg_sel or src0_data or src0_vld or src1_data
	    or src1_vld or src2_data or src2_vld or src3_data
	    or src3_vld or src4_data or src4_vld)
     case (dbg_sel)
       4'b0000:  {mux_vld,mux_data} = {src0_vld,src0_data};
       4'b0001:  {mux_vld,mux_data} = {src1_vld,src1_data};
       4'b0010:  {mux_vld,mux_data} = {src2_vld,src2_data};
       4'b0011:  {mux_vld,mux_data} = {src3_vld,src3_data};
       4'b0100:  {mux_vld,mux_data} = {src4_vld,src4_data};
       default:  {mux_vld,mux_data} = {1'b0,40'b0};
     endcase
   
   assign 	dbg_data = mux_vld ? mux_data : dbg_idleval;

   dff_ns #(40) iob_io_dbg_data_ff (.din(dbg_data),
				    .clk(clk),
				    .q(iob_io_dbg_data));

   dff_ns #(1) iob_io_dbg_en_ff (.din(dbg_en),
				 .clk(clk),
				 .q(iob_io_dbg_en));
   


   assign 	iob_io_dbg_ck_p_next = ~iob_io_dbg_ck_p[0] & dbg_en;
   
   dff_ns #(1) iob_io_dbg_ck_p_ff (.din(iob_io_dbg_ck_p_next),
				   .clk(clk),
				   .q(iob_io_dbg_ck_p[0]));

   assign       iob_io_dbg_ck_p[1] = iob_io_dbg_ck_p[0];
   assign       iob_io_dbg_ck_p[2] = iob_io_dbg_ck_p[0];
   
   assign 	iob_io_dbg_ck_n = ~iob_io_dbg_ck_p;
   
   

   dffrl_ns #(1) io_trigin_d1_ff (.din(io_trigin),
				  .clk(clk),
				  .rst_l(rst_l),
				  .q(io_trigin_d1));

   dffrl_ns #(1) io_trigin_d2_ff (.din(io_trigin_d1),
				  .clk(clk),
				  .rst_l(rst_l),
				  .q(io_trigin_d2));

   dffrl_ns #(1) io_trigin_d3_ff (.din(io_trigin_d2),
				  .clk(clk),
				  .rst_l(rst_l),
				  .q(io_trigin_d3));

   assign 	io_trigin_detected = io_trigin_d2 & ~io_trigin_d3;
   

   assign 	l2_vis_armin = dbg_armin_en & io_trigin_detected;
	 

   assign 	iob_clk_tr_a1 = dbg_trigin_en & io_trigin_detected;

   dffrl_ns #(1) iob_clk_tr_ff (.din(iob_clk_tr_a1),
				.clk(clk),
				.rst_l(rst_l),
				.q(iob_clk_tr));
   
endmodule