data/full_repos/permissive/441359809/src/yosys/tests/simple/fiedler-cooley.v
1: b'%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/fiedler-cooley.v:16: Operator SUB expects 10 bits on the RHS, but RHS\'s CONST \'3\'h5\' generates 3 bits.\n                                                                                               : ... In instance up3down5\n cnt_dn = count_out - 3\'b 101;\n                    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/fiedler-cooley.v:17: Operator ADD expects 10 bits on the RHS, but RHS\'s CONST \'2\'h3\' generates 2 bits.\n                                                                                               : ... In instance up3down5\n cnt_up = count_out + 2\'b 11;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/fiedler-cooley.v:21: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'cnt_dn\' generates 10 bits.\n                                                                                               : ... In instance up3down5\n  2\'b 01 : count_nxt = cnt_dn;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/fiedler-cooley.v:22: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'cnt_up\' generates 10 bits.\n                                                                                               : ... In instance up3down5\n  2\'b 10 : count_nxt = cnt_up;\n                     ^\n%Error: Exiting due to 4 warning(s)\n'
module up3down5(clock, data_in, up, down, carry_out, borrow_out, count_out, parity_out);

input [8:0] data_in;
input clock, up, down;

output reg [8:0] count_out;
output reg carry_out, borrow_out, parity_out;

reg [9:0] cnt_up, cnt_dn;
reg [8:0] count_nxt;

always @(posedge clock)
begin
	cnt_dn = count_out - 3'b 101;
	cnt_up = count_out + 2'b 11;

	case ({up,down})
		2'b 00 : count_nxt = data_in;
		2'b 01 : count_nxt = cnt_dn;
		2'b 10 : count_nxt = cnt_up;
		2'b 11 : count_nxt = count_out;
		default : count_nxt = 9'bX;
	endcase

	parity_out  <= ^count_nxt;
	carry_out   <= up & cnt_up[9];
	borrow_out  <= down & cnt_dn[9];
	count_out   <= count_nxt;
end

endmodule
module up3down5(clock, data_in, up, down, carry_out, borrow_out, count_out, parity_out);


input [8:0] data_in;
input clock, up, down;

output reg [8:0] count_out;
output reg carry_out, borrow_out, parity_out;

reg [9:0] cnt_up, cnt_dn;
reg [8:0] count_nxt;

always @(posedge clock)
begin
	cnt_dn = count_out - 3'b 101;
	cnt_up = count_out + 2'b 11;

	case ({up,down})
		2'b 00 : count_nxt = data_in;
		2'b 01 : count_nxt = cnt_dn;
		2'b 10 : count_nxt = cnt_up;
		2'b 11 : count_nxt = count_out;
		default : count_nxt = 9'bX;
	endcase

	parity_out  <= ^count_nxt;
	carry_out   <= up & cnt_up[9];
	borrow_out  <= down & cnt_dn[9];
	count_out   <= count_nxt;
end

endmodule