data/full_repos/permissive/515704782/jk_ff.v
data/verilator_xmls/ad416184-a3d0-41c8-84e8-4a0d8d3831ef.xml
module jk_ff(input j,k,clk,rst,output reg Q);
initial begin
Q=0;
end
always @(negedge clk or negedge rst)
begin
if(rst==0) Q=0;
else begin
case({j,k})
2'b00:begin Q<=Q;end
2'b01:begin Q<=0; end
2'b10:begin Q<=1;end
2'b11:begin Q<=!Q;end
endcase
end
end
endmodule
module jk_ff(input j,k,clk,rst,output reg Q);

initial begin
Q=0;
end
always @(negedge clk or negedge rst)
begin
if(rst==0) Q=0;
else begin
case({j,k})
2'b00:begin Q<=Q;end
2'b01:begin Q<=0; end
2'b10:begin Q<=1;end
2'b11:begin Q<=!Q;end
endcase
end
end
endmodule