data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Polynomial_multiplier_prime/old_codes/s_mul.v
1: b'%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Polynomial_multiplier_prime/old_codes/s_mul.v:50: Cannot find file containing module: \'dsp_mul\'\ndsp_mul mul(clk, a, b, a_mul_s);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Polynomial_multiplier_prime/old_codes,data/full_repos/permissive/428190211/dsp_mul\n             data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Polynomial_multiplier_prime/old_codes,data/full_repos/permissive/428190211/dsp_mul.v\n             data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Polynomial_multiplier_prime/old_codes,data/full_repos/permissive/428190211/dsp_mul.sv\n             dsp_mul\n             dsp_mul.v\n             dsp_mul.sv\n             obj_dir/dsp_mul\n             obj_dir/dsp_mul.v\n             obj_dir/dsp_mul.sv\n%Error: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Polynomial_multiplier_prime/old_codes/s_mul.v:51: Cannot find file containing module: \'mod7681\'\nmod7681 mod (a_mul_s, mod_out);\n^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/428190211/SABER_HW-master/Verilog_src/Polynomial_multiplier_prime/old_codes/s_mul.v:57: Operator ASSIGNW expects 13 bits on the Assign RHS, but Assign RHS\'s COND generates 14 bits.\n                                                                                                                                 : ... In instance small_alu1\nassign result = (sub[13]) ? result_temp : sub;\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module small_alu1(clk, Ri, s, a, result);
input clk;
input [12:0] Ri, a;
input [12:0] s;
output [12:0] result;






















wire [12:0] mod_out;
wire [25:0] a_mul_s ;
dsp_mul mul(clk, a, b, a_mul_s);
mod7681 mod (a_mul_s, mod_out);
			

wire [13:0] result_temp = Ri + mod_out;

wire [13:0] sub = result_temp - 13'd7681;
assign result = (sub[13]) ? result_temp : sub;


endmodule
module small_alu1(clk, Ri, s, a, result);

input clk;
input [12:0] Ri, a;
input [12:0] s;
output [12:0] result;






















wire [12:0] mod_out;
wire [25:0] a_mul_s ;
dsp_mul mul(clk, a, b, a_mul_s);
mod7681 mod (a_mul_s, mod_out);
			

wire [13:0] result_temp = Ri + mod_out;

wire [13:0] sub = result_temp - 13'd7681;
assign result = (sub[13]) ? result_temp : sub;


endmodule