data/full_repos/permissive/43856783/j1_soc/hdl/multiplier/mult_32/comp.v
data/verilator_xmls/d71b9222-4649-4302-ac5c-c996c94e1236.xml
module comp(B, z);
  input [15:0]B;
  output z;
  reg tmp;
  
  initial tmp = 0;
  assign z = tmp;

    always@(*)
      tmp = (B==0) ? 1'b1 : 1'b0;

endmodule
module comp(B, z);

  input [15:0]B;
  output z;
  reg tmp;
  
  initial tmp = 0;
  assign z = tmp;

    always@(*)
      tmp = (B==0) ? 1'b1 : 1'b0;

endmodule