data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/axi_w_buffer.sv
1: b'%Warning-LITENDIAN: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/axi_w_buffer.sv:24: Little bit endian vector: MSB < LSB of bit range: -2:0\n    input logic  [DATA_WIDTH-1:0] slave_data_i,\n                 ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/axi_w_buffer.sv:25: Little bit endian vector: MSB < LSB of bit range: -1:0\n    input logic  [STRB_WIDTH-1:0] slave_strb_i,\n                 ^\n%Warning-LITENDIAN: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/axi_w_buffer.sv:26: Little bit endian vector: MSB < LSB of bit range: -2:0\n    input logic  [USER_WIDTH-1:0] slave_user_i,\n                 ^\n%Warning-LITENDIAN: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/axi_w_buffer.sv:31: Little bit endian vector: MSB < LSB of bit range: -2:0\n    output logic [DATA_WIDTH-1:0] master_data_o,\n                 ^\n%Warning-LITENDIAN: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/axi_w_buffer.sv:32: Little bit endian vector: MSB < LSB of bit range: -1:0\n    output logic [STRB_WIDTH-1:0] master_strb_o,\n                 ^\n%Warning-LITENDIAN: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/axi_w_buffer.sv:33: Little bit endian vector: MSB < LSB of bit range: -2:0\n    output logic [USER_WIDTH-1:0] master_user_o,\n                 ^\n%Warning-LITENDIAN: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/axi_w_buffer.sv:38: Little bit endian vector: MSB < LSB of bit range: -2:0\n    logic [DATA_WIDTH+STRB_WIDTH+USER_WIDTH:0] s_data_in;\n          ^\n%Warning-LITENDIAN: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/axi_w_buffer.sv:39: Little bit endian vector: MSB < LSB of bit range: -2:0\n    logic [DATA_WIDTH+STRB_WIDTH+USER_WIDTH:0] s_data_out;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/axi_w_buffer.sv:41: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 9 bits.\n                                                                                                 : ... In instance axi_w_buffer\n    assign s_data_in = { slave_user_i,  slave_strb_i,  slave_data_i,  slave_last_i  };\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/axi_w_buffer.sv:42: Operator ASSIGNW expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'s_data_out\' generates 3 bits.\n                                                                                                 : ... In instance axi_w_buffer\n    assign             { master_user_o, master_strb_o, master_data_o, master_last_o } = s_data_out;\n                                                                                      ^\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/axi_w_buffer.sv:44: Cannot find file containing module: \'axi_single_slice\'\n    axi_single_slice #(.BUFFER_DEPTH(BUFFER_DEPTH), .DATA_WIDTH(1+DATA_WIDTH+STRB_WIDTH+USER_WIDTH)) i_axi_single_slice (\n    ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl,data/full_repos/permissive/489147019/axi_single_slice\n             data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl,data/full_repos/permissive/489147019/axi_single_slice.v\n             data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl,data/full_repos/permissive/489147019/axi_single_slice.sv\n             axi_single_slice\n             axi_single_slice.v\n             axi_single_slice.sv\n             obj_dir/axi_single_slice\n             obj_dir/axi_single_slice.v\n             obj_dir/axi_single_slice.sv\n%Error: Exiting due to 1 error(s), 10 warning(s)\n'
module axi_w_buffer #(
    parameter int DATA_WIDTH   = -1,
    parameter int USER_WIDTH   = -1,
    parameter int BUFFER_DEPTH = -1,
    parameter int STRB_WIDTH   = DATA_WIDTH/8
)(
    input logic                   clk_i,
    input logic                   rst_ni,
    input logic                   test_en_i,

    input logic                   slave_valid_i,
    input logic  [DATA_WIDTH-1:0] slave_data_i,
    input logic  [STRB_WIDTH-1:0] slave_strb_i,
    input logic  [USER_WIDTH-1:0] slave_user_i,
    input logic                   slave_last_i,
    output logic                  slave_ready_o,

    output logic                  master_valid_o,
    output logic [DATA_WIDTH-1:0] master_data_o,
    output logic [STRB_WIDTH-1:0] master_strb_o,
    output logic [USER_WIDTH-1:0] master_user_o,
    output logic                  master_last_o,
    input  logic                  master_ready_i
);

    logic [DATA_WIDTH+STRB_WIDTH+USER_WIDTH:0] s_data_in;
    logic [DATA_WIDTH+STRB_WIDTH+USER_WIDTH:0] s_data_out;

    assign s_data_in = { slave_user_i,  slave_strb_i,  slave_data_i,  slave_last_i  };
    assign             { master_user_o, master_strb_o, master_data_o, master_last_o } = s_data_out;

    axi_single_slice #(.BUFFER_DEPTH(BUFFER_DEPTH), .DATA_WIDTH(1+DATA_WIDTH+STRB_WIDTH+USER_WIDTH)) i_axi_single_slice (
      .clk_i      ( clk_i          ),
      .rst_ni     ( rst_ni         ),
      .testmode_i ( test_en_i      ),
      .valid_i    ( slave_valid_i  ),
      .ready_o    ( slave_ready_o  ),
      .data_i     ( s_data_in      ),
      .ready_i    ( master_ready_i ),
      .valid_o    ( master_valid_o ),
      .data_o     ( s_data_out     )
    );
endmodule
module axi_w_buffer #(
    parameter int DATA_WIDTH   = -1,
    parameter int USER_WIDTH   = -1,
    parameter int BUFFER_DEPTH = -1,
    parameter int STRB_WIDTH   = DATA_WIDTH/8
)(
    input logic                   clk_i,
    input logic                   rst_ni,
    input logic                   test_en_i,

    input logic                   slave_valid_i,
    input logic  [DATA_WIDTH-1:0] slave_data_i,
    input logic  [STRB_WIDTH-1:0] slave_strb_i,
    input logic  [USER_WIDTH-1:0] slave_user_i,
    input logic                   slave_last_i,
    output logic                  slave_ready_o,

    output logic                  master_valid_o,
    output logic [DATA_WIDTH-1:0] master_data_o,
    output logic [STRB_WIDTH-1:0] master_strb_o,
    output logic [USER_WIDTH-1:0] master_user_o,
    output logic                  master_last_o,
    input  logic                  master_ready_i
);


    logic [DATA_WIDTH+STRB_WIDTH+USER_WIDTH:0] s_data_in;
    logic [DATA_WIDTH+STRB_WIDTH+USER_WIDTH:0] s_data_out;

    assign s_data_in = { slave_user_i,  slave_strb_i,  slave_data_i,  slave_last_i  };
    assign             { master_user_o, master_strb_o, master_data_o, master_last_o } = s_data_out;

    axi_single_slice #(.BUFFER_DEPTH(BUFFER_DEPTH), .DATA_WIDTH(1+DATA_WIDTH+STRB_WIDTH+USER_WIDTH)) i_axi_single_slice (
      .clk_i      ( clk_i          ),
      .rst_ni     ( rst_ni         ),
      .testmode_i ( test_en_i      ),
      .valid_i    ( slave_valid_i  ),
      .ready_o    ( slave_ready_o  ),
      .data_i     ( s_data_in      ),
      .ready_i    ( master_ready_i ),
      .valid_o    ( master_valid_o ),
      .data_o     ( s_data_out     )
    );
endmodule