data/full_repos/permissive/481044442/BDCDrv/rxclk_sync_to_txclk.v
data/verilator_xmls/c1152d3d-aff3-4711-8025-9844cc9f36c9.xml
module rxclk_sync_to_txclk(clk,reset,rx_done,txclk,tx_start);
input clk;
input reset;
input rx_done;
input txclk;

output reg tx_start;


reg [1:0] rx_done_buf;
wire neg_rx_done=rx_done_buf[1]&(~rx_done_buf[0]);
reg neg_rx_done_trigger;


reg [1:0] txclk_buf;
wire neg_txclk=(~txclk_buf[0])&txclk_buf[1];
wire pos_txclk=txclk_buf[0]&(~txclk_buf[1]);

always @(posedge clk or posedge reset)
begin
	if(reset) begin
				rx_done_buf<=2'b00;
				txclk_buf=2'b00;
			  end
	else begin
			rx_done_buf<={rx_done_buf[0],rx_done};
			txclk_buf={txclk_buf[0],txclk};
		 end
end


always @(posedge clk or posedge reset)
begin
	if(reset) begin
				tx_start<=1'b0;	
				neg_rx_done_trigger<=1'b0;
			  end
	else begin
			if(neg_rx_done)
					neg_rx_done_trigger<=1'b1;
			else if(neg_rx_done_trigger==1'b1 && neg_txclk)
					tx_start<=1'b1;
				 else if(neg_rx_done_trigger==1'b1 && pos_txclk ) begin
						 	 										tx_start<=1'b0;
						 	 										neg_rx_done_trigger<=1'b0;
						 	 								     end
					  else
					  		tx_start<=tx_start;
					  		
	     end
end
endmodule
module rxclk_sync_to_txclk(clk,reset,rx_done,txclk,tx_start);

input clk;
input reset;
input rx_done;
input txclk;

output reg tx_start;


reg [1:0] rx_done_buf;
wire neg_rx_done=rx_done_buf[1]&(~rx_done_buf[0]);
reg neg_rx_done_trigger;


reg [1:0] txclk_buf;
wire neg_txclk=(~txclk_buf[0])&txclk_buf[1];
wire pos_txclk=txclk_buf[0]&(~txclk_buf[1]);

always @(posedge clk or posedge reset)
begin
	if(reset) begin
				rx_done_buf<=2'b00;
				txclk_buf=2'b00;
			  end
	else begin
			rx_done_buf<={rx_done_buf[0],rx_done};
			txclk_buf={txclk_buf[0],txclk};
		 end
end


always @(posedge clk or posedge reset)
begin
	if(reset) begin
				tx_start<=1'b0;	
				neg_rx_done_trigger<=1'b0;
			  end
	else begin
			if(neg_rx_done)
					neg_rx_done_trigger<=1'b1;
			else if(neg_rx_done_trigger==1'b1 && neg_txclk)
					tx_start<=1'b1;
				 else if(neg_rx_done_trigger==1'b1 && pos_txclk ) begin
						 	 										tx_start<=1'b0;
						 	 										neg_rx_done_trigger<=1'b0;
						 	 								     end
					  else
					  		tx_start<=tx_start;
					  		
	     end
end
endmodule