data/full_repos/permissive/458737381/src/verilog-parser/tests/std-7.1.6-primitives.v
data/verilator_xmls/7f97c35a-6cd4-423c-8631-4e687f564efe.xml
module busdriver_equiv (busin, bushigh, buslow, enh, enl);
input [15:0] busin;
output [7:0] bushigh, buslow;
input enh, enl;
driver busar[3:0] (.out({bushigh, buslow}), .in(busin),
.en({enh, enh, enl, enl}));
endmodule
module busdriver_equiv (busin, bushigh, buslow, enh, enl);

input [15:0] busin;
output [7:0] bushigh, buslow;
input enh, enl;
driver busar[3:0] (.out({bushigh, buslow}), .in(busin),
.en({enh, enh, enl, enl}));
endmodule