data/full_repos/permissive/476411248/Parallel_Serial_Converter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/476411248/Parallel_Serial_Converter.v:119: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'counter\' generates 8 bits.\n                                                                                    : ... In instance Parallel_Serial_Converter\n                    parallel_regs[i*LENGTH-1 + counter -:2] <= serial_data_in[i*2+1 -:2];\n                                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Parallel_Serial_Converter
 # (parameter SIZE = 4,  parameter MAX_WORD_LENGTH = 32, parameter LENGTH = 32)
(
	clk,  
	reset, 
    mode,
    start,
    finish,
    serial_data_in,
    parallel_data_in,
    serial_data_out,
    parallel_data_out


);

input clk, reset, start;
input[1:0] mode;
input [8*SIZE-1:0] serial_data_in;
input [4*MAX_WORD_LENGTH*SIZE-1:0] parallel_data_in;
output reg finish;
output[8*SIZE-1:0] serial_data_out;
output[4*MAX_WORD_LENGTH*SIZE-1:0] parallel_data_out;




integer i;


reg [4*SIZE*MAX_WORD_LENGTH-1:0] parallel_regs;

reg [7:0] counter;
reg state;
reg counting;










always@(posedge clk) begin
    if(reset==0) begin
        counter <= LENGTH;
        finish <= 0;
        counting    <= 0;
    end
    else begin
        if(start) begin
            counter     <= 0;
            finish      <= 0;
            counting    <= 0;
        end
        else if(counter<LENGTH+1) begin
            counter <= counter + 1;
            counting <= 1;
            if(counter == LENGTH) begin
                finish <= 1;
                counting <= 0;
            end
        end
        else finish <= 0;
    end
end



always@(posedge clk)
begin
    if(reset==0) begin
        parallel_regs <= 0;
        i <= 0;
        state <= 0;
    end
    else
    begin
        if(mode==0)
        begin
            parallel_regs <= parallel_regs;
        end
        if(mode==1) begin

            if(counting) begin
                case(state)
				0: begin
				state <= 1;
				end
				1: begin
				for(i=0; i<SIZE*4; i=i+1) begin
                    parallel_regs[i*LENGTH-1 + counter -:2] <= serial_data_in[i*2+1 -:2];
                end
                state <= 0;
				end
                endcase
            end
        end
        else if(mode==2)
        begin

            parallel_regs <= parallel_data_in;
        end
        
    end
end

assign parallel_data_out = parallel_regs;



genvar gi;
generate
for (gi=0; gi<SIZE*4; gi=gi+1) begin : s
    assign serial_data_out[gi*2+1 -:2] = counting && mode==0? parallel_regs[gi*LENGTH+1 + counter-2 -:2] : 2'hz;
end
endgenerate


endmodule
module Parallel_Serial_Converter
 # (parameter SIZE = 4,  parameter MAX_WORD_LENGTH = 32, parameter LENGTH = 32)
(
	clk,  
	reset, 
    mode,
    start,
    finish,
    serial_data_in,
    parallel_data_in,
    serial_data_out,
    parallel_data_out


);


input clk, reset, start;
input[1:0] mode;
input [8*SIZE-1:0] serial_data_in;
input [4*MAX_WORD_LENGTH*SIZE-1:0] parallel_data_in;
output reg finish;
output[8*SIZE-1:0] serial_data_out;
output[4*MAX_WORD_LENGTH*SIZE-1:0] parallel_data_out;




integer i;


reg [4*SIZE*MAX_WORD_LENGTH-1:0] parallel_regs;

reg [7:0] counter;
reg state;
reg counting;










always@(posedge clk) begin
    if(reset==0) begin
        counter <= LENGTH;
        finish <= 0;
        counting    <= 0;
    end
    else begin
        if(start) begin
            counter     <= 0;
            finish      <= 0;
            counting    <= 0;
        end
        else if(counter<LENGTH+1) begin
            counter <= counter + 1;
            counting <= 1;
            if(counter == LENGTH) begin
                finish <= 1;
                counting <= 0;
            end
        end
        else finish <= 0;
    end
end



always@(posedge clk)
begin
    if(reset==0) begin
        parallel_regs <= 0;
        i <= 0;
        state <= 0;
    end
    else
    begin
        if(mode==0)
        begin
            parallel_regs <= parallel_regs;
        end
        if(mode==1) begin

            if(counting) begin
                case(state)
				0: begin
				state <= 1;
				end
				1: begin
				for(i=0; i<SIZE*4; i=i+1) begin
                    parallel_regs[i*LENGTH-1 + counter -:2] <= serial_data_in[i*2+1 -:2];
                end
                state <= 0;
				end
                endcase
            end
        end
        else if(mode==2)
        begin

            parallel_regs <= parallel_data_in;
        end
        
    end
end

assign parallel_data_out = parallel_regs;



genvar gi;
generate
for (gi=0; gi<SIZE*4; gi=gi+1) begin : s
    assign serial_data_out[gi*2+1 -:2] = counting && mode==0? parallel_regs[gi*LENGTH+1 + counter-2 -:2] : 2'hz;
end
endgenerate


endmodule