data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v
1: b'%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:12: Cannot find include file: pa_chip_param.v\n`include "pa_chip_param.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core,data/full_repos/permissive/485610894/pa_chip_param.v\n             data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core,data/full_repos/permissive/485610894/pa_chip_param.v.v\n             data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core,data/full_repos/permissive/485610894/pa_chip_param.v.sv\n             pa_chip_param.v\n             pa_chip_param.v.v\n             pa_chip_param.v.sv\n             obj_dir/pa_chip_param.v\n             obj_dir/pa_chip_param.v.v\n             obj_dir/pa_chip_param.v.sv\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:18: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    output wire [`DATA_BUS_WIDTH-1:0]   csr_mtvec_o,\n                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:19: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    output wire [`DATA_BUS_WIDTH-1:0]   csr_mepc_o,\n                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:20: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    output wire [`DATA_BUS_WIDTH-1:0]   csr_mstatus_o,\n                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:22: Define or directive not defined: \'`CSR_BUS_WIDTH\'\n    input  wire [`CSR_BUS_WIDTH-1:0]    csr_raddr_i,\n                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:24: Define or directive not defined: \'`CSR_BUS_WIDTH\'\n    input  wire [`CSR_BUS_WIDTH-1:0]    csr_waddr_i,\n                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:27: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    input  wire [`DATA_BUS_WIDTH-1:0]   csr_wdata_i,\n                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:29: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    output wire [`DATA_BUS_WIDTH-1:0]   csr_rdata_o\n                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:32: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nreg  [`DATA_BUS_WIDTH-1:0]              _mtvec;      \n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:33: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nreg  [`DATA_BUS_WIDTH-1:0]              _mepc;       \n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:34: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nreg  [`DATA_BUS_WIDTH-1:0]              _mcause;     \n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:35: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nreg  [`DATA_BUS_WIDTH-1:0]              _mie;        \n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:36: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nreg  [`DATA_BUS_WIDTH-1:0]              _mip;        \n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:37: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nreg  [`DATA_BUS_WIDTH-1:0]              _mtval;      \n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:38: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nreg  [`DATA_BUS_WIDTH-1:0]              _mscratch;   \n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:39: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nreg  [`DATA_BUS_WIDTH-1:0]              _mstatus;    \n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:64: Define or directive not defined: \'`CSR_MTVEC\'\n        `CSR_MTVEC    : _mtvec    <= csr_wdata_i;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:64: syntax error, unexpected \':\', expecting endcase\n        `CSR_MTVEC    : _mtvec    <= csr_wdata_i;\n                      ^\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:65: Define or directive not defined: \'`CSR_MEPC\'\n        `CSR_MEPC     : _mepc     <= csr_wdata_i;\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:66: Define or directive not defined: \'`CSR_MCAUSE\'\n        `CSR_MCAUSE   : _mcause   <= csr_wdata_i;\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:67: Define or directive not defined: \'`CSR_MIE\'\n        `CSR_MIE      : _mie      <= csr_wdata_i;\n        ^~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:68: Define or directive not defined: \'`CSR_MIP\'\n        `CSR_MIP      : _mip      <= csr_wdata_i;\n        ^~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:69: Define or directive not defined: \'`CSR_MTVAL\'\n        `CSR_MTVAL    : _mtval    <= csr_wdata_i;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:70: Define or directive not defined: \'`CSR_MSCRATCH\'\n        `CSR_MSCRATCH : _mscratch <= csr_wdata_i;\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:71: Define or directive not defined: \'`CSR_MSTATUS\'\n        `CSR_MSTATUS  : _mstatus  <= csr_wdata_i;\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:76: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nreg  [`DATA_BUS_WIDTH-1:0]              _csr;\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:79: Define or directive not defined: \'`ZERO_WORD\'\n    _csr = `ZERO_WORD;\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:81: Define or directive not defined: \'`CSR_MTVEC\'\n        `CSR_MTVEC    : _csr = _mtvec;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:81: syntax error, unexpected \':\', expecting endcase\n        `CSR_MTVEC    : _csr = _mtvec;\n                      ^\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:82: Define or directive not defined: \'`CSR_MEPC\'\n        `CSR_MEPC     : _csr = _mepc;\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:83: Define or directive not defined: \'`CSR_MCAUSE\'\n        `CSR_MCAUSE   : _csr = _mcause;\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:84: Define or directive not defined: \'`CSR_MIE\'\n        `CSR_MIE      : _csr = _mie;\n        ^~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:85: Define or directive not defined: \'`CSR_MIP\'\n        `CSR_MIP      : _csr = _mip;\n        ^~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:86: Define or directive not defined: \'`CSR_MTVAL\'\n        `CSR_MTVAL    : _csr = _mtval;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:87: Define or directive not defined: \'`CSR_MSCRATCH\'\n        `CSR_MSCRATCH : _csr = _mscratch;\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:88: Define or directive not defined: \'`CSR_MSTATUS\'\n        `CSR_MSTATUS  : _csr = _mstatus;\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:89: Define or directive not defined: \'`CSR_CYCLEH\'\n        `CSR_CYCLEH   : _csr = _cycle[63:32];\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:90: Define or directive not defined: \'`CSR_CYCLE\'\n        `CSR_CYCLE    : _csr = _cycle[31: 0];\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:94: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nassign csr_mtvec_o[`DATA_BUS_WIDTH-1:0]   = _mtvec[`DATA_BUS_WIDTH-1:0];\n                   ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:94: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nassign csr_mtvec_o[`DATA_BUS_WIDTH-1:0]   = _mtvec[`DATA_BUS_WIDTH-1:0];\n                                                   ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:95: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nassign csr_mepc_o[`DATA_BUS_WIDTH-1:0]    = _mepc[`DATA_BUS_WIDTH-1:0];\n                  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:95: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nassign csr_mepc_o[`DATA_BUS_WIDTH-1:0]    = _mepc[`DATA_BUS_WIDTH-1:0];\n                                                  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:96: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nassign csr_mstatus_o[`DATA_BUS_WIDTH-1:0] = _mstatus[`DATA_BUS_WIDTH-1:0];\n                     ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:96: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nassign csr_mstatus_o[`DATA_BUS_WIDTH-1:0] = _mstatus[`DATA_BUS_WIDTH-1:0];\n                                                     ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:98: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nassign csr_rdata_o[`DATA_BUS_WIDTH-1:0] = _csr[`DATA_BUS_WIDTH-1:0];\n                   ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:98: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nassign csr_rdata_o[`DATA_BUS_WIDTH-1:0] = _csr[`DATA_BUS_WIDTH-1:0];\n                                               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_csr.v:100: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: Cannot continue\n'
module pa_core_csr (
    input  wire                         clk_i,
    input  wire                         rst_n_i,

    output wire [`DATA_BUS_WIDTH-1:0]   csr_mtvec_o,
    output wire [`DATA_BUS_WIDTH-1:0]   csr_mepc_o,
    output wire [`DATA_BUS_WIDTH-1:0]   csr_mstatus_o,

    input  wire [`CSR_BUS_WIDTH-1:0]    csr_raddr_i,

    input  wire [`CSR_BUS_WIDTH-1:0]    csr_waddr_i,
    input  wire                         csr_waddr_vld_i,

    input  wire [`DATA_BUS_WIDTH-1:0]   csr_wdata_i,

    output wire [`DATA_BUS_WIDTH-1:0]   csr_rdata_o
);

reg  [`DATA_BUS_WIDTH-1:0]              _mtvec;
reg  [`DATA_BUS_WIDTH-1:0]              _mepc;
reg  [`DATA_BUS_WIDTH-1:0]              _mcause;
reg  [`DATA_BUS_WIDTH-1:0]              _mie;
reg  [`DATA_BUS_WIDTH-1:0]              _mip;
reg  [`DATA_BUS_WIDTH-1:0]              _mtval;
reg  [`DATA_BUS_WIDTH-1:0]              _mscratch;
reg  [`DATA_BUS_WIDTH-1:0]              _mstatus;
reg  [63:0]                             _cycle;

always @ (posedge clk_i or negedge rst_n_i) begin
    if (!rst_n_i) begin
        _cycle <= 64'h0;
    end
    else begin
        _cycle <= _cycle + 64'h1;
    end
end

always @ (posedge clk_i or negedge rst_n_i) begin
    if (!rst_n_i) begin
        _mtvec    <= 32'h0;
        _mepc     <= 32'h0;
        _mcause   <= 32'h0;
        _mie      <= 32'h0;
        _mip      <= 32'h0;
        _mtval    <= 32'h0;
        _mscratch <= 32'h0;
        _mstatus  <= 32'h0000_0060;
    end
    else if (csr_waddr_vld_i) begin
    case (csr_waddr_i[11:0])
        `CSR_MTVEC    : _mtvec    <= csr_wdata_i;
        `CSR_MEPC     : _mepc     <= csr_wdata_i;
        `CSR_MCAUSE   : _mcause   <= csr_wdata_i;
        `CSR_MIE      : _mie      <= csr_wdata_i;
        `CSR_MIP      : _mip      <= csr_wdata_i;
        `CSR_MTVAL    : _mtval    <= csr_wdata_i;
        `CSR_MSCRATCH : _mscratch <= csr_wdata_i;
        `CSR_MSTATUS  : _mstatus  <= csr_wdata_i;
    endcase
    end
end

reg  [`DATA_BUS_WIDTH-1:0]              _csr;

always @ (*) begin
    _csr = `ZERO_WORD;
    case (csr_raddr_i[11:0])
        `CSR_MTVEC    : _csr = _mtvec;
        `CSR_MEPC     : _csr = _mepc;
        `CSR_MCAUSE   : _csr = _mcause;
        `CSR_MIE      : _csr = _mie;
        `CSR_MIP      : _csr = _mip;
        `CSR_MTVAL    : _csr = _mtval;
        `CSR_MSCRATCH : _csr = _mscratch;
        `CSR_MSTATUS  : _csr = _mstatus;
        `CSR_CYCLEH   : _csr = _cycle[63:32];
        `CSR_CYCLE    : _csr = _cycle[31: 0];
    endcase
end

assign csr_mtvec_o[`DATA_BUS_WIDTH-1:0]   = _mtvec[`DATA_BUS_WIDTH-1:0];
assign csr_mepc_o[`DATA_BUS_WIDTH-1:0]    = _mepc[`DATA_BUS_WIDTH-1:0];
assign csr_mstatus_o[`DATA_BUS_WIDTH-1:0] = _mstatus[`DATA_BUS_WIDTH-1:0];

assign csr_rdata_o[`DATA_BUS_WIDTH-1:0] = _csr[`DATA_BUS_WIDTH-1:0];

endmodule
module pa_core_csr (
    input  wire                         clk_i,
    input  wire                         rst_n_i,

    output wire [`DATA_BUS_WIDTH-1:0]   csr_mtvec_o,
    output wire [`DATA_BUS_WIDTH-1:0]   csr_mepc_o,
    output wire [`DATA_BUS_WIDTH-1:0]   csr_mstatus_o,

    input  wire [`CSR_BUS_WIDTH-1:0]    csr_raddr_i,

    input  wire [`CSR_BUS_WIDTH-1:0]    csr_waddr_i,
    input  wire                         csr_waddr_vld_i,

    input  wire [`DATA_BUS_WIDTH-1:0]   csr_wdata_i,

    output wire [`DATA_BUS_WIDTH-1:0]   csr_rdata_o
);


reg  [`DATA_BUS_WIDTH-1:0]              _mtvec;
reg  [`DATA_BUS_WIDTH-1:0]              _mepc;
reg  [`DATA_BUS_WIDTH-1:0]              _mcause;
reg  [`DATA_BUS_WIDTH-1:0]              _mie;
reg  [`DATA_BUS_WIDTH-1:0]              _mip;
reg  [`DATA_BUS_WIDTH-1:0]              _mtval;
reg  [`DATA_BUS_WIDTH-1:0]              _mscratch;
reg  [`DATA_BUS_WIDTH-1:0]              _mstatus;
reg  [63:0]                             _cycle;

always @ (posedge clk_i or negedge rst_n_i) begin
    if (!rst_n_i) begin
        _cycle <= 64'h0;
    end
    else begin
        _cycle <= _cycle + 64'h1;
    end
end

always @ (posedge clk_i or negedge rst_n_i) begin
    if (!rst_n_i) begin
        _mtvec    <= 32'h0;
        _mepc     <= 32'h0;
        _mcause   <= 32'h0;
        _mie      <= 32'h0;
        _mip      <= 32'h0;
        _mtval    <= 32'h0;
        _mscratch <= 32'h0;
        _mstatus  <= 32'h0000_0060;
    end
    else if (csr_waddr_vld_i) begin
    case (csr_waddr_i[11:0])
        `CSR_MTVEC    : _mtvec    <= csr_wdata_i;
        `CSR_MEPC     : _mepc     <= csr_wdata_i;
        `CSR_MCAUSE   : _mcause   <= csr_wdata_i;
        `CSR_MIE      : _mie      <= csr_wdata_i;
        `CSR_MIP      : _mip      <= csr_wdata_i;
        `CSR_MTVAL    : _mtval    <= csr_wdata_i;
        `CSR_MSCRATCH : _mscratch <= csr_wdata_i;
        `CSR_MSTATUS  : _mstatus  <= csr_wdata_i;
    endcase
    end
end

reg  [`DATA_BUS_WIDTH-1:0]              _csr;

always @ (*) begin
    _csr = `ZERO_WORD;
    case (csr_raddr_i[11:0])
        `CSR_MTVEC    : _csr = _mtvec;
        `CSR_MEPC     : _csr = _mepc;
        `CSR_MCAUSE   : _csr = _mcause;
        `CSR_MIE      : _csr = _mie;
        `CSR_MIP      : _csr = _mip;
        `CSR_MTVAL    : _csr = _mtval;
        `CSR_MSCRATCH : _csr = _mscratch;
        `CSR_MSTATUS  : _csr = _mstatus;
        `CSR_CYCLEH   : _csr = _cycle[63:32];
        `CSR_CYCLE    : _csr = _cycle[31: 0];
    endcase
end

assign csr_mtvec_o[`DATA_BUS_WIDTH-1:0]   = _mtvec[`DATA_BUS_WIDTH-1:0];
assign csr_mepc_o[`DATA_BUS_WIDTH-1:0]    = _mepc[`DATA_BUS_WIDTH-1:0];
assign csr_mstatus_o[`DATA_BUS_WIDTH-1:0] = _mstatus[`DATA_BUS_WIDTH-1:0];

assign csr_rdata_o[`DATA_BUS_WIDTH-1:0] = _csr[`DATA_BUS_WIDTH-1:0];

endmodule