data/full_repos/permissive/418819021/lab-01/task4/fetcher.v
1: b"%Error: data/full_repos/permissive/418819021/lab-01/task4/fetcher.v:85: Cannot find file containing module: 'rom'\n    rom memory (\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/418819021/lab-01/task4,data/full_repos/permissive/418819021/rom\n             data/full_repos/permissive/418819021/lab-01/task4,data/full_repos/permissive/418819021/rom.v\n             data/full_repos/permissive/418819021/lab-01/task4,data/full_repos/permissive/418819021/rom.sv\n             rom\n             rom.v\n             rom.sv\n             obj_dir/rom\n             obj_dir/rom.v\n             obj_dir/rom.sv\n%Error: data/full_repos/permissive/418819021/lab-01/task4/fetcher.v:90: Cannot find file containing module: 'sram'\n    sram cache (\n    ^~~~\n%Error: Exiting due to 2 error(s)\n"
module fetcher (
    output wire [7:0] data,
    input  wire       clk,
    input  wire       rst,
    input  wire [3:0] address
);

    reg [1:0] state;
    reg [7:0] out_buffer;
    

    reg        we, oe, cs;
    wire [7:0] rom_buffer;
    wire [7:0] sram_buffer;

    localparam TRUE                 = 1'b1,
               FALSE                = 1'b0,
               STATE_IDLE           = 2'd0,
               STATE_SRAM_READ      = 2'b01,
               STATE_SRAM_WRITE     = 2'b10;

    task clear_signals;
        begin
            we         <= FALSE; 
            cs         <= FALSE;
            oe         <= FALSE;
            state      <= STATE_IDLE;
            out_buffer <= 8'bz;
        end
    endtask

    always @(posedge clk) begin
        if (rst) begin
            clear_signals;
        end else begin
            case (state)
                STATE_IDLE: begin
                    we <= FALSE;
                    if (address === 4'dz) begin
                        cs    <= FALSE;
                        oe    <= FALSE;
                        state <= STATE_IDLE; 
                    end else begin
                        cs    <= TRUE;
                        oe    <= TRUE;
                        state <= STATE_SRAM_READ;
                    end
                end

                STATE_SRAM_READ: begin
                    oe <= FALSE;
                    if (sram_buffer !== 8'dz) begin                        
                        we         <= FALSE;
                        cs         <= FALSE;
                        state      <= STATE_IDLE;
                        out_buffer <= sram_buffer;
                    end else begin
                        we         <= TRUE; 
                        cs         <= TRUE;
                        state      <= STATE_SRAM_WRITE;
                        out_buffer <= rom_buffer;
                    end
                end

                STATE_SRAM_WRITE: begin
                    we    <= FALSE;
                    cs    <= FALSE;
                    state <= STATE_IDLE;
                end

                default: begin
                    clear_signals;
                end
            endcase
        end
    end


    assign data = out_buffer;
    assign sram_buffer = ((state == STATE_SRAM_WRITE) & we) ? out_buffer : 8'dz;

    rom memory (
        .address(address),
        .data(rom_buffer)
    );
    
    sram cache (
        .clk(clk),
        .reset(rst),
        .oe(oe),
        .cs(cs),
        .we(we),
        .address({3'b000, address}),
        .data(sram_buffer)
    );
endmodule
module fetcher (
    output wire [7:0] data,
    input  wire       clk,
    input  wire       rst,
    input  wire [3:0] address
);


    reg [1:0] state;
    reg [7:0] out_buffer;
    

    reg        we, oe, cs;
    wire [7:0] rom_buffer;
    wire [7:0] sram_buffer;

    localparam TRUE                 = 1'b1,
               FALSE                = 1'b0,
               STATE_IDLE           = 2'd0,
               STATE_SRAM_READ      = 2'b01,
               STATE_SRAM_WRITE     = 2'b10;

    task clear_signals;
        begin
            we         <= FALSE; 
            cs         <= FALSE;
            oe         <= FALSE;
            state      <= STATE_IDLE;
            out_buffer <= 8'bz;
        end
    endtask

    always @(posedge clk) begin
        if (rst) begin
            clear_signals;
        end else begin
            case (state)
                STATE_IDLE: begin
                    we <= FALSE;
                    if (address === 4'dz) begin
                        cs    <= FALSE;
                        oe    <= FALSE;
                        state <= STATE_IDLE; 
                    end else begin
                        cs    <= TRUE;
                        oe    <= TRUE;
                        state <= STATE_SRAM_READ;
                    end
                end

                STATE_SRAM_READ: begin
                    oe <= FALSE;
                    if (sram_buffer !== 8'dz) begin                        
                        we         <= FALSE;
                        cs         <= FALSE;
                        state      <= STATE_IDLE;
                        out_buffer <= sram_buffer;
                    end else begin
                        we         <= TRUE; 
                        cs         <= TRUE;
                        state      <= STATE_SRAM_WRITE;
                        out_buffer <= rom_buffer;
                    end
                end

                STATE_SRAM_WRITE: begin
                    we    <= FALSE;
                    cs    <= FALSE;
                    state <= STATE_IDLE;
                end

                default: begin
                    clear_signals;
                end
            endcase
        end
    end


    assign data = out_buffer;
    assign sram_buffer = ((state == STATE_SRAM_WRITE) & we) ? out_buffer : 8'dz;

    rom memory (
        .address(address),
        .data(rom_buffer)
    );
    
    sram cache (
        .clk(clk),
        .reset(rst),
        .oe(oe),
        .cs(cs),
        .we(we),
        .address({3'b000, address}),
        .data(sram_buffer)
    );
endmodule