data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco/AddressDecoder_Resp.sv
1: b'%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco/AddressDecoder_Resp.sv:44: Cannot find include file: parameters.v\n`include "parameters.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco,data/full_repos/permissive/489147019/parameters.v\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco,data/full_repos/permissive/489147019/parameters.v.v\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/low_latency_interco,data/full_repos/permissive/489147019/parameters.v.sv\n             parameters.v\n             parameters.v.v\n             parameters.v.sv\n             obj_dir/parameters.v\n             obj_dir/parameters.v.v\n             obj_dir/parameters.v.sv\n%Error: Exiting due to 1 error(s)\n'
module AddressDecoder_Resp 
  #(	
	parameter ID_WIDTH	= 20,
	parameter N_MASTER 	= 20
  ) 
  (

	input  logic 				data_r_valid_i,
	input  logic [ID_WIDTH-1:0]		data_ID_i,
	

	output logic [N_MASTER-1:0]		data_r_valid_o
  );

  assign data_r_valid_o = {ID_WIDTH{data_r_valid_i}} & data_ID_i; 
	
endmodule
module AddressDecoder_Resp 
  #(	
	parameter ID_WIDTH	= 20,
	parameter N_MASTER 	= 20
  ) 
  (

	input  logic 				data_r_valid_i,
	input  logic [ID_WIDTH-1:0]		data_ID_i,
	

	output logic [N_MASTER-1:0]		data_r_valid_o
  );


  assign data_r_valid_o = {ID_WIDTH{data_r_valid_i}} & data_ID_i; 
	
endmodule