data/full_repos/permissive/485085993/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/485085993/verilog/rtl/user_proj_example.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/user_proj_example.v:67: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/user_proj_example.v:68: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/user_proj_example.v:76: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_in;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/user_proj_example.v:77: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_out;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/user_proj_example.v:78: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_oeb;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/user_proj_example.v:97: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};\n                      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/user_proj_example.v:115: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [0:`MPRJ_IO_PADS-1] gfpga_pad_GPIO_PAD_OUT;\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/user_proj_example.v:218: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign gfpga_pad_GPIO_PAD_OUT[10:`MPRJ_IO_PADS-1] = gfpga_pad_GPIO_PAD_wire[31];\n                                     ^~~~~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n"
module user_proj_example #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,


    output [2:0] irq
);
    wire clk;
    wire rst;

    wire [`MPRJ_IO_PADS-1:0] io_in;
    wire [`MPRJ_IO_PADS-1:0] io_out;
    wire [`MPRJ_IO_PADS-1:0] io_oeb;

    wire [31:0] rdata; 
    wire [31:0] wdata;
    wire [BITS-1:0] count;

    wire valid;
    wire [3:0] wstrb;
    wire [31:0] la_write;


    assign valid = wbs_cyc_i && wbs_stb_i; 
    assign wstrb = wbs_sel_i & {4{wbs_we_i}};
    assign wbs_dat_o = rdata;
    assign wdata = wbs_dat_i;


    assign io_out = gfpga_pad_GPIO_PAD_OUT;

    assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};


    assign irq = 3'b000;


    assign la_data_out = {{(127-BITS){1'b0}}, count};

    assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};

    assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
    assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;


 
    

    reg [0:31] gfpga_pad_GPIO_PAD_IN;
    wire [0:`MPRJ_IO_PADS-1] gfpga_pad_GPIO_PAD_OUT;
    reg [31:0] wbs_dat_o_reg;


    reg [0:4] bl_address;

    reg [0:4] wl_address;
    reg data_in;




    reg set;
    reg reset;
    reg enable;

    reg ready;



    always @(posedge clk) begin
        if (rst) begin
            ready <= 0;
            set <= 1'b0;
            reset <= 1'b0;
            enable <= 1'b0;
            bl_address <= 1'b0;
            wl_address <= 1'b0;
            data_in <= 1'b0;
            gfpga_pad_GPIO_PAD_IN <= 1'b0;          
        end else begin
            ready <= 1'b0;
        if(wbs_stb_i && wbs_cyc_i && wbs_we_i) begin
            case(wbs_adr_i)
                32'h30000000: begin
                    set <= wbs_dat_i[0];
                    reset <= wbs_dat_i[1];
                    enable <= wbs_dat_i[2];
                end
                32'h30000004: begin
                    bl_address <= wbs_dat_i[4:0];
                    wl_address <= wbs_dat_i[9:5];
                    data_in <= wbs_dat_i[10];           
                end
                32'h30000008: begin
                    gfpga_pad_GPIO_PAD_IN <= wbs_dat_i;

                end
            endcase
            ready <= 1'b1;
        end else if(wbs_stb_i && wbs_cyc_i && !wbs_we_i) begin
            case(wbs_adr_i)
                32'h30000000: begin
                    wbs_dat_o_reg[0] <= set;
                    wbs_dat_o_reg[1] <= reset;
                    wbs_dat_o_reg[2] <= enable;
                end
                32'h30000004: begin
                    wbs_dat_o_reg[4:0] <= bl_address;
                    wbs_dat_o_reg[9:5] <= wl_address;
                    wbs_dat_o_reg[10] <= data_in;           
                end
                32'h30000008: begin
                    wbs_dat_o_reg <= gfpga_pad_GPIO_PAD_IN;
                end
                32'h3000000C: begin
                    wbs_dat_o_reg <= gfpga_pad_GPIO_PAD_OUT;
                end
            endcase
            ready <= 1'b1;
            end
        end
    end

    assign wbs_dat_o = wbs_dat_o_reg;




    wire [0:31] gfpga_pad_GPIO_PAD_wire;


    assign gfpga_pad_GPIO_PAD_wire[26] = gfpga_pad_GPIO_PAD_IN[26];
    assign gfpga_pad_GPIO_PAD_wire[8] = gfpga_pad_GPIO_PAD_IN[8];
    assign gfpga_pad_GPIO_PAD_wire[14] = gfpga_pad_GPIO_PAD_IN[14];
    assign gfpga_pad_GPIO_PAD_wire[6] = gfpga_pad_GPIO_PAD_IN[6];
    assign gfpga_pad_GPIO_PAD_wire[1] = gfpga_pad_GPIO_PAD_IN[1]; 


    assign gfpga_pad_GPIO_PAD_OUT[0:7] = gfpga_pad_GPIO_PAD_wire[7];
    assign gfpga_pad_GPIO_PAD_OUT[10:`MPRJ_IO_PADS-1] = gfpga_pad_GPIO_PAD_wire[31];
    assign gfpga_pad_GPIO_PAD_OUT[8:9] = gfpga_pad_GPIO_PAD_wire[9];
    
    fpga_top ftop(
      	.set(set),
		.reset(reset),
		.clk(clk),
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD_wire),
		.enable(enable),
		.bl_address(bl_address),
		.wl_address(wl_address),
		.data_in(data_in)
    );  
    

    assign wbs_ack_o = ready;



endmodule
module user_proj_example #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,


    output [2:0] irq
);

    wire clk;
    wire rst;

    wire [`MPRJ_IO_PADS-1:0] io_in;
    wire [`MPRJ_IO_PADS-1:0] io_out;
    wire [`MPRJ_IO_PADS-1:0] io_oeb;

    wire [31:0] rdata; 
    wire [31:0] wdata;
    wire [BITS-1:0] count;

    wire valid;
    wire [3:0] wstrb;
    wire [31:0] la_write;


    assign valid = wbs_cyc_i && wbs_stb_i; 
    assign wstrb = wbs_sel_i & {4{wbs_we_i}};
    assign wbs_dat_o = rdata;
    assign wdata = wbs_dat_i;


    assign io_out = gfpga_pad_GPIO_PAD_OUT;

    assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};


    assign irq = 3'b000;


    assign la_data_out = {{(127-BITS){1'b0}}, count};

    assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};

    assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
    assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;


 
    

    reg [0:31] gfpga_pad_GPIO_PAD_IN;
    wire [0:`MPRJ_IO_PADS-1] gfpga_pad_GPIO_PAD_OUT;
    reg [31:0] wbs_dat_o_reg;


    reg [0:4] bl_address;

    reg [0:4] wl_address;
    reg data_in;




    reg set;
    reg reset;
    reg enable;

    reg ready;



    always @(posedge clk) begin
        if (rst) begin
            ready <= 0;
            set <= 1'b0;
            reset <= 1'b0;
            enable <= 1'b0;
            bl_address <= 1'b0;
            wl_address <= 1'b0;
            data_in <= 1'b0;
            gfpga_pad_GPIO_PAD_IN <= 1'b0;          
        end else begin
            ready <= 1'b0;
        if(wbs_stb_i && wbs_cyc_i && wbs_we_i) begin
            case(wbs_adr_i)
                32'h30000000: begin
                    set <= wbs_dat_i[0];
                    reset <= wbs_dat_i[1];
                    enable <= wbs_dat_i[2];
                end
                32'h30000004: begin
                    bl_address <= wbs_dat_i[4:0];
                    wl_address <= wbs_dat_i[9:5];
                    data_in <= wbs_dat_i[10];           
                end
                32'h30000008: begin
                    gfpga_pad_GPIO_PAD_IN <= wbs_dat_i;

                end
            endcase
            ready <= 1'b1;
        end else if(wbs_stb_i && wbs_cyc_i && !wbs_we_i) begin
            case(wbs_adr_i)
                32'h30000000: begin
                    wbs_dat_o_reg[0] <= set;
                    wbs_dat_o_reg[1] <= reset;
                    wbs_dat_o_reg[2] <= enable;
                end
                32'h30000004: begin
                    wbs_dat_o_reg[4:0] <= bl_address;
                    wbs_dat_o_reg[9:5] <= wl_address;
                    wbs_dat_o_reg[10] <= data_in;           
                end
                32'h30000008: begin
                    wbs_dat_o_reg <= gfpga_pad_GPIO_PAD_IN;
                end
                32'h3000000C: begin
                    wbs_dat_o_reg <= gfpga_pad_GPIO_PAD_OUT;
                end
            endcase
            ready <= 1'b1;
            end
        end
    end

    assign wbs_dat_o = wbs_dat_o_reg;




    wire [0:31] gfpga_pad_GPIO_PAD_wire;


    assign gfpga_pad_GPIO_PAD_wire[26] = gfpga_pad_GPIO_PAD_IN[26];
    assign gfpga_pad_GPIO_PAD_wire[8] = gfpga_pad_GPIO_PAD_IN[8];
    assign gfpga_pad_GPIO_PAD_wire[14] = gfpga_pad_GPIO_PAD_IN[14];
    assign gfpga_pad_GPIO_PAD_wire[6] = gfpga_pad_GPIO_PAD_IN[6];
    assign gfpga_pad_GPIO_PAD_wire[1] = gfpga_pad_GPIO_PAD_IN[1]; 


    assign gfpga_pad_GPIO_PAD_OUT[0:7] = gfpga_pad_GPIO_PAD_wire[7];
    assign gfpga_pad_GPIO_PAD_OUT[10:`MPRJ_IO_PADS-1] = gfpga_pad_GPIO_PAD_wire[31];
    assign gfpga_pad_GPIO_PAD_OUT[8:9] = gfpga_pad_GPIO_PAD_wire[9];
    
    fpga_top ftop(
      	.set(set),
		.reset(reset),
		.clk(clk),
		.gfpga_pad_GPIO_PAD(gfpga_pad_GPIO_PAD_wire),
		.enable(enable),
		.bl_address(bl_address),
		.wl_address(wl_address),
		.data_in(data_in)
    );  
    

    assign wbs_ack_o = ready;



endmodule