data/full_repos/permissive/482719158/verilog/dv/microwatt/jtag/jtag_tb.v
1: b'%Error: data/full_repos/permissive/482719158/verilog/dv/microwatt/jtag/jtag_tb.v:24: Cannot find include file: uprj_netlists.v\n`include "uprj_netlists.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/482719158/verilog/dv/microwatt/jtag,data/full_repos/permissive/482719158/uprj_netlists.v\n             data/full_repos/permissive/482719158/verilog/dv/microwatt/jtag,data/full_repos/permissive/482719158/uprj_netlists.v.v\n             data/full_repos/permissive/482719158/verilog/dv/microwatt/jtag,data/full_repos/permissive/482719158/uprj_netlists.v.sv\n             uprj_netlists.v\n             uprj_netlists.v.v\n             uprj_netlists.v.sv\n             obj_dir/uprj_netlists.v\n             obj_dir/uprj_netlists.v.v\n             obj_dir/uprj_netlists.v.sv\n%Error: data/full_repos/permissive/482719158/verilog/dv/microwatt/jtag/jtag_tb.v:25: Cannot find include file: caravel_netlists.v\n`include "caravel_netlists.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/482719158/verilog/dv/microwatt/jtag/jtag_tb.v:26: Cannot find include file: spiflash.v\n`include "spiflash.v" \n         ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/jtag/jtag_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n always #5 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/482719158/verilog/dv/microwatt/jtag/jtag_tb.v:118: syntax error, unexpected \'@\'\n   repeat (10000) @(posedge clock);\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/jtag/jtag_tb.v:127: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/jtag/jtag_tb.v:138: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/jtag/jtag_tb.v:140: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/jtag/jtag_tb.v:142: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/jtag/jtag_tb.v:144: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/jtag/jtag_tb.v:154: Unsupported: Ignoring delay on this delayed statement.\n  #10000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/jtag/jtag_tb.v:158: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/jtag/jtag_tb.v:160: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/jtag/jtag_tb.v:164: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/jtag/jtag_tb.v:166: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/jtag/jtag_tb.v:170: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/jtag/jtag_tb.v:172: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/jtag/jtag_tb.v:176: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/jtag/jtag_tb.v:178: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/jtag/jtag_tb.v:182: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/jtag/jtag_tb.v:184: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/jtag/jtag_tb.v:188: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/jtag/jtag_tb.v:190: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/jtag/jtag_tb.v:195: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/jtag/jtag_tb.v:197: Unsupported: Ignoring delay on this delayed statement.\n  #1000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/jtag/jtag_tb.v:201: Unsupported: Ignoring delay on this delayed statement.\n   #1000;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/482719158/verilog/dv/microwatt/jtag/jtag_tb.v:203: Unsupported: Ignoring delay on this delayed statement.\n   #1000;\n   ^\n%Error: Exiting due to 4 error(s), 23 warning(s)\n'
module jtag_expect_idcode (
	input tdo,
	input tck,
	input en
);
	reg [4:0] recv_state;
	reg [31:0] pattern;

	reg clk;

	initial begin
		recv_state <= 0;
		pattern <= 0;
	end

	always @(posedge tck) begin
	   if (en == 1'b1) begin
	      pattern <= {tdo, pattern[31:1]};
	      recv_state <= recv_state + 1;
	   end
	   case (recv_state)
	     31: begin
		recv_state <= 0;
		$display("Testing: Read %x from JTAG", pattern);

		if (pattern == 32'h14d57048) begin
		   $display("PASSED");
		   $finish;
		end else begin
		   $display("FAILED: should have been 14d57048");
		   $fatal;
		end
	     end
	   endcase
	end
endmodule
module jtag_expect_idcode (
	input tdo,
	input tck,
	input en
);

	reg [4:0] recv_state;
	reg [31:0] pattern;

	reg clk;

	initial begin
		recv_state <= 0;
		pattern <= 0;
	end

	always @(posedge tck) begin
	   if (en == 1'b1) begin
	      pattern <= {tdo, pattern[31:1]};
	      recv_state <= recv_state + 1;
	   end
	   case (recv_state)
	     31: begin
		recv_state <= 0;
		$display("Testing: Read %x from JTAG", pattern);

		if (pattern == 32'h14d57048) begin
		   $display("PASSED");
		   $finish;
		end else begin
		   $display("FAILED: should have been 14d57048");
		   $fatal;
		end
	     end
	   endcase
	end
endmodule