data/full_repos/permissive/515477729/source/dff.v
data/verilator_xmls/e342de2b-5dd2-40ae-ac83-a93c3295bab6.xml
module dff (output reg q, input d, clk, clr);
    
    always @(posedge clk) begin
        if (clr) 
            q <= 0;
        else 
            q <= d;
    end
    
endmodule
module dff (output reg q, input d, clk, clr);

    
    always @(posedge clk) begin
        if (clr) 
            q <= 0;
        else 
            q <= d;
    end
    
endmodule