data/full_repos/permissive/482132588/design/code/dmemory.v
1: b"%Error: data/full_repos/permissive/482132588/design/code/dmemory.v:15: Define or directive not defined: '`LINE_COUNT'\nreg [31:0] temparr[0:`LINE_COUNT - 1];\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/482132588/design/code/dmemory.v:16: Define or directive not defined: '`MEM_DEPTH'\nreg [7:0]memory[0:`MEM_DEPTH - 1];\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/482132588/design/code/dmemory.v:44: Define or directive not defined: '`MEM_PATH'\n      $readmemh (`MEM_PATH,temparr);\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/482132588/design/code/dmemory.v:44: syntax error, unexpected ',', expecting TYPE-IDENTIFIER\n      $readmemh (`MEM_PATH,temparr);\n                          ^\n%Error: data/full_repos/permissive/482132588/design/code/dmemory.v:46: Define or directive not defined: '`LINE_COUNT'\n      for(i=0; i<`LINE_COUNT; i=i+1) begin\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/482132588/design/code/dmemory.v:46: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n      for(i=0; i<`LINE_COUNT; i=i+1) begin\n                            ^\n%Error: data/full_repos/permissive/482132588/design/code/dmemory.v:46: syntax error, unexpected ')', expecting ';'\n      for(i=0; i<`LINE_COUNT; i=i+1) begin\n                                   ^\n%Error: data/full_repos/permissive/482132588/design/code/dmemory.v:58: syntax error, unexpected '[', expecting IDENTIFIER\n        memory[address - 32'h01000000] = data_in[7:0];\n              ^\n%Error: data/full_repos/permissive/482132588/design/code/dmemory.v:60: syntax error, unexpected '[', expecting IDENTIFIER\n          memory[address  - 32'h01000000 + 1] = data_in[15:8];\n                ^\n%Error: data/full_repos/permissive/482132588/design/code/dmemory.v:63: syntax error, unexpected '[', expecting IDENTIFIER\n          memory[address - 32'h01000000 + 2] = data_in[23:16];\n                ^\n%Error: data/full_repos/permissive/482132588/design/code/dmemory.v:77: syntax error, unexpected end\n  end\n  ^~~\n%Error: Cannot continue\n"
module dmemory(
  input  wire clock,
  input wire reset,
  input  wire [31:0] address,
  input  wire [31:0] data_in,
  input  wire read_write,
  input wire [2:0] access_size,
  output wire [31:0] data_out 
);


reg [31:0] temparr[0:`LINE_COUNT - 1];
reg [7:0]memory[0:`MEM_DEPTH - 1];


integer i;


wire [7:0]pad0;
wire[7:0]padsign;

assign pad0 = {8{1'b0}};
assign padsign = (access_size[1:0] == 2'b01) ? {8{memory[address - `offset][7]}} :{8{memory[address - `offset + 1][7]}} ;





assign data_out[7:0] =  memory[address - `offset];

assign data_out[15:8] = (access_size[1:0] != 2'b00) ? memory[address - `offset + 1] : (access_size[2] ? pad0 : padsign) ;

assign data_out[23:16] = (access_size[1:0] == 2'b10) ? memory[address - `offset + 2] : (access_size[2] ? pad0 : padsign) ;
assign data_out[31:24] = (access_size[1:0] == 2'b10) ? memory[address - `offset + 3] : (access_size[2] ? pad0 : padsign) ;


  always @(posedge clock or posedge reset) begin

    if(reset)begin
      
      $readmemh (`MEM_PATH,temparr);
    
      for(i=0; i<`LINE_COUNT; i=i+1) begin

        memory[i*4] = temparr[i][7:0];
        memory[i*4 + 1] = temparr[i][15:8];
        memory[i*4 + 2] = temparr[i][23:16];
        memory[i*4 + 3] = temparr[i][31:24]; 
        
      end

    end

    if (read_write) begin
        memory[address - `offset] = data_in[7:0];
        if(access_size[1:0] != 2'b00)
          memory[address  - `offset + 1] = data_in[15:8];
        if(access_size[1:0] == 2'b10) begin

          memory[address - `offset + 2] = data_in[23:16];
          memory[address  - `offset + 3] = data_in[31:24];     
        
        end 
            
    end


  end
  
endmodule
module dmemory(
  input  wire clock,
  input wire reset,
  input  wire [31:0] address,
  input  wire [31:0] data_in,
  input  wire read_write,
  input wire [2:0] access_size,
  output wire [31:0] data_out 
);



reg [31:0] temparr[0:`LINE_COUNT - 1];
reg [7:0]memory[0:`MEM_DEPTH - 1];


integer i;


wire [7:0]pad0;
wire[7:0]padsign;

assign pad0 = {8{1'b0}};
assign padsign = (access_size[1:0] == 2'b01) ? {8{memory[address - `offset][7]}} :{8{memory[address - `offset + 1][7]}} ;





assign data_out[7:0] =  memory[address - `offset];

assign data_out[15:8] = (access_size[1:0] != 2'b00) ? memory[address - `offset + 1] : (access_size[2] ? pad0 : padsign) ;

assign data_out[23:16] = (access_size[1:0] == 2'b10) ? memory[address - `offset + 2] : (access_size[2] ? pad0 : padsign) ;
assign data_out[31:24] = (access_size[1:0] == 2'b10) ? memory[address - `offset + 3] : (access_size[2] ? pad0 : padsign) ;


  always @(posedge clock or posedge reset) begin

    if(reset)begin
      
      $readmemh (`MEM_PATH,temparr);
    
      for(i=0; i<`LINE_COUNT; i=i+1) begin

        memory[i*4] = temparr[i][7:0];
        memory[i*4 + 1] = temparr[i][15:8];
        memory[i*4 + 2] = temparr[i][23:16];
        memory[i*4 + 3] = temparr[i][31:24]; 
        
      end

    end

    if (read_write) begin
        memory[address - `offset] = data_in[7:0];
        if(access_size[1:0] != 2'b00)
          memory[address  - `offset + 1] = data_in[15:8];
        if(access_size[1:0] == 2'b10) begin

          memory[address - `offset + 2] = data_in[23:16];
          memory[address  - `offset + 3] = data_in[31:24];     
        
        end 
            
    end


  end
  
endmodule