data/full_repos/permissive/43264243/channel.v
1: b'%Error: data/full_repos/permissive/43264243/channel.v:23: Cannot find include file: config.h\n`include "config.h" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43264243,data/full_repos/permissive/43264243/config.h\n             data/full_repos/permissive/43264243,data/full_repos/permissive/43264243/config.h.v\n             data/full_repos/permissive/43264243,data/full_repos/permissive/43264243/config.h.sv\n             config.h\n             config.h.v\n             config.h.sv\n             obj_dir/config.h\n             obj_dir/config.h.v\n             obj_dir/config.h.sv\n%Error: data/full_repos/permissive/43264243/channel.v:124: Define or directive not defined: \'`FIFO_DEPTH\'\n wire [`FIFO_DEPTH-1:0] itemsinfifo;\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/43264243/channel.v:165: Define or directive not defined: \'`FIFO_DEPTH\'\n defparam fifo0.DEPTH = `FIFO_DEPTH;\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/43264243/channel.v:165: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n defparam fifo0.DEPTH = `FIFO_DEPTH;\n                                   ^\n%Error: Exiting due to 4 error(s)\n'
module edgedet(clk, rstn, datain, edgeseen);
	input clk;
	input rstn;
	input datain;
	output reg edgeseen;
	reg lastdata;
	reg [3:0] count;
	
	
	always @(posedge clk or negedge rstn) begin
		if(rstn == 0) begin
			edgeseen <= 0;
			lastdata <= 0; 
			count  <= 4'b0000;
			
		end else begin
			edgeseen <= 0;


			
			if(count < 15) begin
			    lastdata <= datain;
				count <= count + 1'b1;
			end
			
	
			if(count == 13) begin
				edgeseen <= 1;
			end
			
				
	
			if((count == 15)  && (lastdata ^ datain)) begin
				edgeseen <= 1;
				lastdata <= datain;
			end	
		end
	end
endmodule
module edgedet(clk, rstn, datain, edgeseen);

	input clk;
	input rstn;
	input datain;
	output reg edgeseen;
	reg lastdata;
	reg [3:0] count;
	
	
	always @(posedge clk or negedge rstn) begin
		if(rstn == 0) begin
			edgeseen <= 0;
			lastdata <= 0; 
			count  <= 4'b0000;
			
		end else begin
			edgeseen <= 0;


			
			if(count < 15) begin
			    lastdata <= datain;
				count <= count + 1'b1;
			end
			
	
			if(count == 13) begin
				edgeseen <= 1;
			end
			
				
	
			if((count == 15)  && (lastdata ^ datain)) begin
				edgeseen <= 1;
				lastdata <= datain;
			end	
		end
	end
endmodule