data/full_repos/permissive/461000256/new/ID.v
1: b'%Error: data/full_repos/permissive/461000256/new/ID.v:1: Cannot find include file: definitions.v\n`include "definitions.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/461000256/new,data/full_repos/permissive/461000256/definitions.v\n             data/full_repos/permissive/461000256/new,data/full_repos/permissive/461000256/definitions.v.v\n             data/full_repos/permissive/461000256/new,data/full_repos/permissive/461000256/definitions.v.sv\n             definitions.v\n             definitions.v.v\n             definitions.v.sv\n             obj_dir/definitions.v\n             obj_dir/definitions.v.v\n             obj_dir/definitions.v.sv\n%Error: data/full_repos/permissive/461000256/new/ID.v:36: Define or directive not defined: \'`OP\'\n  if     (opcode == `OP) begin\n                    ^~~\n%Error: data/full_repos/permissive/461000256/new/ID.v:36: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  if     (opcode == `OP) begin\n                       ^\n%Error: data/full_repos/permissive/461000256/new/ID.v:42: syntax error, unexpected else\n  else if (opcode == `OP_IMM || opcode == `JALR || opcode == `LOAD || opcode == `SYSTEM) begin\n  ^~~~\n%Error: data/full_repos/permissive/461000256/new/ID.v:42: Define or directive not defined: \'`OP_IMM\'\n  else if (opcode == `OP_IMM || opcode == `JALR || opcode == `LOAD || opcode == `SYSTEM) begin\n                     ^~~~~~~\n%Error: data/full_repos/permissive/461000256/new/ID.v:42: Define or directive not defined: \'`JALR\'\n  else if (opcode == `OP_IMM || opcode == `JALR || opcode == `LOAD || opcode == `SYSTEM) begin\n                                          ^~~~~\n%Error: data/full_repos/permissive/461000256/new/ID.v:42: Define or directive not defined: \'`LOAD\'\n  else if (opcode == `OP_IMM || opcode == `JALR || opcode == `LOAD || opcode == `SYSTEM) begin\n                                                             ^~~~~\n%Error: data/full_repos/permissive/461000256/new/ID.v:42: Define or directive not defined: \'`SYSTEM\'\n  else if (opcode == `OP_IMM || opcode == `JALR || opcode == `LOAD || opcode == `SYSTEM) begin\n                                                                                ^~~~~~~\n%Error: data/full_repos/permissive/461000256/new/ID.v:48: Define or directive not defined: \'`STORE\'\n  else if (opcode == `STORE) begin\n                     ^~~~~~\n%Error: data/full_repos/permissive/461000256/new/ID.v:54: Define or directive not defined: \'`BRANCH\'\n  else if (opcode == `BRANCH) begin\n                     ^~~~~~~\n%Error: data/full_repos/permissive/461000256/new/ID.v:60: Define or directive not defined: \'`LUI\'\n  else if (opcode == `LUI || opcode == `AUIPC) begin\n                     ^~~~\n%Error: data/full_repos/permissive/461000256/new/ID.v:60: Define or directive not defined: \'`AUIPC\'\n  else if (opcode == `LUI || opcode == `AUIPC) begin\n                                       ^~~~~~\n%Error: data/full_repos/permissive/461000256/new/ID.v:66: Define or directive not defined: \'`JAL\'\n  else if (opcode == `JAL) begin\n                     ^~~~\n%Error: Cannot continue\n'
module ID 
#(	parameter RFW = 5,
	parameter IMW = 4,
	parameter DW = 32,
	parameter IW = 32)
(	input wire [IW-1:0] inst,
	output reg [RFW-1:0] addrA,
	output reg [RFW-1:0] addrB,
	output reg [DW-1:0] imm);

	wire [RFW-1:0] rs2, rs1, rd;
	wire [6:0] funct7;
	wire [6:0] opcode;
	wire [2:0] funct3;
	wire [DW-1:0] imm_I, imm_U, imm_S, imm_B, imm_J;

	assign imm_I	= { {20{inst[31]}}, inst[30:20] };
	assign imm_S	= { {20{inst[31]}}, inst[30:25],inst[11:7]};
	assign imm_B	= { {19{inst[31]}},inst[7],inst[30:25],inst[11:8], 1'b0};
	assign imm_U	= { {inst[31:12]}, {12{1'b0}} };
	assign imm_J	= { {11{inst[31]}}, inst[19:12],inst[20],inst[30:21], 1'b0};
	assign funct7 	= inst[31:25];
	assign rs2 		= inst[24:20];
	assign rs1		= inst[19:15];
	assign funct3	= inst[14:12];
	assign rd		= inst[11:7 ];
	assign opcode	= inst[6 :2 ];

	always @(*) begin
		if (inst[1:0] != 2'b11) begin
			$display("ERROR IN INSTRUCTION");
			$display(inst);
		end

		if 	  	(opcode == `OP) begin

			addrA = rs1;
			addrB = rs2;
			imm = 32'hX;
		end
		else if (opcode == `OP_IMM || opcode == `JALR || opcode == `LOAD || opcode == `SYSTEM) begin

			addrA = rs1;
			addrB = 32'hX;
			imm = imm_I;
		end
		else if (opcode == `STORE) begin

			addrA = rs1;
			addrB = rs2;
			imm = imm_S;
		end
		else if (opcode == `BRANCH) begin

			addrA = rs1;
			addrB = rs2;
			imm = imm_B;
		end
		else if (opcode == `LUI || opcode == `AUIPC) begin

			addrA = 32'hX;
			addrB = 32'hX;
			imm = imm_U;
		end
		else if (opcode == `JAL) begin

			addrA = 32'hX;
			addrB = 32'hX;
			imm = imm_J;
		end
	end

endmodule
module ID 
#(	parameter RFW = 5,
	parameter IMW = 4,
	parameter DW = 32,
	parameter IW = 32)
(	input wire [IW-1:0] inst,
	output reg [RFW-1:0] addrA,
	output reg [RFW-1:0] addrB,
	output reg [DW-1:0] imm);


	wire [RFW-1:0] rs2, rs1, rd;
	wire [6:0] funct7;
	wire [6:0] opcode;
	wire [2:0] funct3;
	wire [DW-1:0] imm_I, imm_U, imm_S, imm_B, imm_J;

	assign imm_I	= { {20{inst[31]}}, inst[30:20] };
	assign imm_S	= { {20{inst[31]}}, inst[30:25],inst[11:7]};
	assign imm_B	= { {19{inst[31]}},inst[7],inst[30:25],inst[11:8], 1'b0};
	assign imm_U	= { {inst[31:12]}, {12{1'b0}} };
	assign imm_J	= { {11{inst[31]}}, inst[19:12],inst[20],inst[30:21], 1'b0};
	assign funct7 	= inst[31:25];
	assign rs2 		= inst[24:20];
	assign rs1		= inst[19:15];
	assign funct3	= inst[14:12];
	assign rd		= inst[11:7 ];
	assign opcode	= inst[6 :2 ];

	always @(*) begin
		if (inst[1:0] != 2'b11) begin
			$display("ERROR IN INSTRUCTION");
			$display(inst);
		end

		if 	  	(opcode == `OP) begin

			addrA = rs1;
			addrB = rs2;
			imm = 32'hX;
		end
		else if (opcode == `OP_IMM || opcode == `JALR || opcode == `LOAD || opcode == `SYSTEM) begin

			addrA = rs1;
			addrB = 32'hX;
			imm = imm_I;
		end
		else if (opcode == `STORE) begin

			addrA = rs1;
			addrB = rs2;
			imm = imm_S;
		end
		else if (opcode == `BRANCH) begin

			addrA = rs1;
			addrB = rs2;
			imm = imm_B;
		end
		else if (opcode == `LUI || opcode == `AUIPC) begin

			addrA = 32'hX;
			addrB = 32'hX;
			imm = imm_U;
		end
		else if (opcode == `JAL) begin

			addrA = 32'hX;
			addrB = 32'hX;
			imm = imm_J;
		end
	end

endmodule