data/full_repos/permissive/514217463/front_panel_mapping.sv
1: b'%Warning-LITENDIAN: data/full_repos/permissive/514217463/front_panel_mapping.sv:44: Little bit endian vector: MSB < LSB of bit range: 0:35\n  output [0:35] leds_status,\n         ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/514217463/front_panel_mapping.sv:46: Little bit endian vector: MSB < LSB of bit range: 0:7\n  input [0:7] data,\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/514217463/front_panel_mapping.sv:47: Little bit endian vector: MSB < LSB of bit range: 0:15\n    input [0:15] addr,\n          ^\n%Warning-LITENDIAN: data/full_repos/permissive/514217463/front_panel_mapping.sv:61: Little bit endian vector: MSB < LSB of bit range: 0:7\n  output [0:7] sense_addr_sw,\n         ^\n%Warning-LITENDIAN: data/full_repos/permissive/514217463/front_panel_mapping.sv:62: Little bit endian vector: MSB < LSB of bit range: 0:7\n  output [0:7] data_addr_sw,\n         ^\n%Warning-WIDTH: data/full_repos/permissive/514217463/front_panel_mapping.sv:100: Operator ASSIGN expects 36 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                               : ... In instance front_panel_mapping\n      leds_status = 1\'b000000000000000000000000000000000000;\n                  ^\n%Error-PROCASSWIRE: data/full_repos/permissive/514217463/front_panel_mapping.sv:100: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): \'leds_status\'\n                                                                                   : ... In instance front_panel_mapping\n      leds_status = 1\'b000000000000000000000000000000000000;\n      ^~~~~~~~~~~\n%Error: Exiting due to 1 error(s), 6 warning(s)\n'
module handle_three_pos_sw(
    input clk,
    input [1:0] sw_status,
    output reg o_state_up,
    output reg o_state_down
    );





    always @(posedge clk)
    begin
        if (sw_status == 0) begin o_state_up <= 0; o_state_down <= 0; end
        if (sw_status == 1) begin o_state_up <= 0; o_state_down <= 1; end
        if (sw_status == 2) begin o_state_up <= 1; o_state_down <= 0; end
    end

endmodule
module handle_three_pos_sw(
    input clk,
    input [1:0] sw_status,
    output reg o_state_up,
    output reg o_state_down
    );






    always @(posedge clk)
    begin
        if (sw_status == 0) begin o_state_up <= 0; o_state_down <= 0; end
        if (sw_status == 1) begin o_state_up <= 0; o_state_down <= 1; end
        if (sw_status == 2) begin o_state_up <= 1; o_state_down <= 0; end
    end

endmodule