data/full_repos/permissive/445379100/a3/pc.v
1: b"%Error-ASSIGNIN: data/full_repos/permissive/445379100/a3/pc.v:9: Assigning to input/const variable: 'n_addr'\n    assign n_addr = iaddr ;    \n           ^~~~~~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module pc (
    input [31:0] n_addr ,
    output [31:0] iaddr
);
    assign n_addr = iaddr ;    
endmodule
module pc (
    input [31:0] n_addr ,
    output [31:0] iaddr
);

    assign n_addr = iaddr ;    
endmodule