data/full_repos/permissive/432564927/Lab3 (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new/CPU.v
1: b'%Error: Cannot find file containing module: (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927\n        ... Looked in:\n             data/full_repos/permissive/432564927/Lab3/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927\n             data/full_repos/permissive/432564927/Lab3/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             data/full_repos/permissive/432564927/Lab3/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927\n             (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             obj_dir/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927\n             obj_dir/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             obj_dir/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/432564927/Lab3\n%Error: Cannot find file containing module: (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new/CPU.v\n%Error: Exiting due to 3 error(s)\n'
module IFID(clk, do, op, rd, rs, rt, func, imm);
    input clk;
    input [31:0] do;

    output reg [5:0] op, func;
    output reg [4:0] rd, rs, rt;
    output reg [15:0] imm;
    
    always@(posedge clk) begin
        op <= do[31:26];
        func <= do[5:0];
        rs <= do[25:21];
        rt <= do[20:16];
        rd <= do[15:11];
        imm <= do[15:0];
    end
endmodule
module IFID(clk, do, op, rd, rs, rt, func, imm);

    input clk;
    input [31:0] do;

    output reg [5:0] op, func;
    output reg [4:0] rd, rs, rt;
    output reg [15:0] imm;
    
    always@(posedge clk) begin
        op <= do[31:26];
        func <= do[5:0];
        rs <= do[25:21];
        rt <= do[20:16];
        rd <= do[15:11];
        imm <= do[15:0];
    end
endmodule