data/full_repos/permissive/411457613/Pyverilog/verilogcode/ptr_clock_reset.v
data/verilator_xmls/5c1ee71d-b1e1-4bd9-8913-b69c78e2c515.xml
module TOP(CLK,RST);
  input [3:1] CLK;
  input [1:0] RST;
  reg cnt;
  
  always @(posedge CLK[2] or posedge RST[0]) begin
    if(RST[0]) begin
      cnt <= 'd0;
    end
  end

endmodule
module TOP(CLK,RST);

  input [3:1] CLK;
  input [1:0] RST;
  reg cnt;
  
  always @(posedge CLK[2] or posedge RST[0]) begin
    if(RST[0]) begin
      cnt <= 'd0;
    end
  end

endmodule