data/full_repos/permissive/504478691/MIPS/CPU54/RegFile.v
data/verilator_xmls/5f84f9f1-34c8-4501-bbcc-5fd6ffb2385c.xml
module Reg32(clk, rst, ena, din, dout);
    input clk, rst, ena;
    input [31:0] din;
    output [31:0] dout;

    reg [31:0] data;
    wire clk_ena;
    assign clk_ena = clk & ena;
    assign dout = data;
    always @(posedge clk_ena or posedge rst)
        data = rst ? 32'd0 : din;
endmodule
module Reg32(clk, rst, ena, din, dout);

    input clk, rst, ena;
    input [31:0] din;
    output [31:0] dout;

    reg [31:0] data;
    wire clk_ena;
    assign clk_ena = clk & ena;
    assign dout = data;
    always @(posedge clk_ena or posedge rst)
        data = rst ? 32'd0 : din;
endmodule