data/full_repos/permissive/466874195/verilog/test/tb_find.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/466874195/verilog/test/tb_find.sv:33: Unsupported: Ignoring delay on this delayed statement.\n    always #hperiod clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/466874195/verilog/test/tb_find.sv:36: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("tb_find.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/466874195/verilog/test/tb_find.sv:37: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, tb_find);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/466874195/verilog/test/tb_find.sv:44: Unsupported: Ignoring delay on this delayed statement.\n        #period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/466874195/verilog/test/tb_find.sv:45: Unsupported: Ignoring delay on this delayed statement.\n        #period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/466874195/verilog/test/tb_find.sv:46: Unsupported: Ignoring delay on this delayed statement.\n        #period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/466874195/verilog/test/tb_find.sv:47: Unsupported: Ignoring delay on this delayed statement.\n        #period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/466874195/verilog/test/tb_find.sv:53: Unsupported: Ignoring delay on this delayed statement.\n        #period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/466874195/verilog/test/tb_find.sv:54: Unsupported: Ignoring delay on this delayed statement.\n        #period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/466874195/verilog/test/tb_find.sv:55: Unsupported: Ignoring delay on this delayed statement.\n        #period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/466874195/verilog/test/tb_find.sv:56: Unsupported: Ignoring delay on this delayed statement.\n        #period;\n        ^\n%Error: data/full_repos/permissive/466874195/verilog/test/tb_find.sv:58: Unsupported: wait statements\n        wait (o_done);\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/466874195/verilog/test/tb_find.sv:60: Unsupported: Ignoring delay on this delayed statement.\n        #period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/466874195/verilog/test/tb_find.sv:65: Unsupported: Ignoring delay on this delayed statement.\n            #period;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/466874195/verilog/test/tb_find.sv:70: Unsupported: Ignoring delay on this delayed statement.\n        #period; #period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/466874195/verilog/test/tb_find.sv:70: Unsupported: Ignoring delay on this delayed statement.\n        #period; #period;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/466874195/verilog/test/tb_find.sv:71: Unsupported: Ignoring delay on this delayed statement.\n        #period; #period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/466874195/verilog/test/tb_find.sv:71: Unsupported: Ignoring delay on this delayed statement.\n        #period; #period;\n                 ^\n%Error: data/full_repos/permissive/466874195/verilog/test/tb_find.sv:74: Unsupported: wait statements\n        wait (o_done);\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/466874195/verilog/test/tb_find.sv:76: Unsupported: Ignoring delay on this delayed statement.\n        #period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/466874195/verilog/test/tb_find.sv:81: Unsupported: Ignoring delay on this delayed statement.\n            #period;\n            ^\n%Error: Exiting due to 4 error(s), 17 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_find;

    localparam period = 10;
    localparam hperiod = period/2;

    localparam SEQ_WIDTH = 16;

    integer ii;

    reg clk;
    reg rst;
    wire [SEQ_WIDTH-1:0] o_seq;
    wire [19:0] o_e;
    wire o_done;
    reg [6:0] i_offset;

    find # (
        .SEQ_WIDTH(SEQ_WIDTH),
        .FIX_WIDTH(0)
    ) UUT (
        .clk(clk),
        .rst(rst),
        .i_offset(i_offset),
        .o_seq(o_seq),
        .o_e(o_e),
        .o_done(o_done)
    );

    always #hperiod clk = ~clk;

    initial begin
        $dumpfile("tb_find.vcd");
        $dumpvars(0, tb_find);

        i_offset <= 6'd0;

        clk <= 1'b0;
        rst <= 1'b1;

        #period;
        #period;
        #period;
        #period;

        rst <= 1'b0;

        i_offset <= 6'd0;

        #period;
        #period;
        #period;
        #period;

        wait (o_done);

        #period;
        $display(o_seq);
        $display(o_e);

        for (ii = 0; ii < 100; ii++) begin
            #period;
        end

        i_offset <= 6'd6;
        rst <= 1'b1;
        #period; #period;
        #period; #period;
        rst <= 1'b0;

        wait (o_done);

        #period;
        $display(o_seq);
        $display(o_e);

        for (ii = 0; ii < 100; ii++) begin
            #period;
        end

        $finish();
    end

endmodule
module tb_find;


    localparam period = 10;
    localparam hperiod = period/2;

    localparam SEQ_WIDTH = 16;

    integer ii;

    reg clk;
    reg rst;
    wire [SEQ_WIDTH-1:0] o_seq;
    wire [19:0] o_e;
    wire o_done;
    reg [6:0] i_offset;

    find # (
        .SEQ_WIDTH(SEQ_WIDTH),
        .FIX_WIDTH(0)
    ) UUT (
        .clk(clk),
        .rst(rst),
        .i_offset(i_offset),
        .o_seq(o_seq),
        .o_e(o_e),
        .o_done(o_done)
    );

    always #hperiod clk = ~clk;

    initial begin
        $dumpfile("tb_find.vcd");
        $dumpvars(0, tb_find);

        i_offset <= 6'd0;

        clk <= 1'b0;
        rst <= 1'b1;

        #period;
        #period;
        #period;
        #period;

        rst <= 1'b0;

        i_offset <= 6'd0;

        #period;
        #period;
        #period;
        #period;

        wait (o_done);

        #period;
        $display(o_seq);
        $display(o_e);

        for (ii = 0; ii < 100; ii++) begin
            #period;
        end

        i_offset <= 6'd6;
        rst <= 1'b1;
        #period; #period;
        #period; #period;
        rst <= 1'b0;

        wait (o_done);

        #period;
        $display(o_seq);
        $display(o_e);

        for (ii = 0; ii < 100; ii++) begin
            #period;
        end

        $finish();
    end

endmodule