data/full_repos/permissive/520428138/verilog/rtl/user_module_341353780122485332.v
1: b"%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341353780122485332.v:52: Can't resolve module reference: 'sky130_fd_sc_hd__dlxtp_1'\n    sky130_fd_sc_hd__dlxtp_1 mode_lat_i (\n                             ^~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module user_module_341353780122485332(
  input [7:0] io_in, 
  output [7:0] io_out
);


  wire frame_sr_clk = io_in[1];
  reg [16:0] frame_sr;

  always @(posedge frame_sr_clk)
    frame_sr <= {frame_sr[15:0], io_in[2]};

  lutram_341353780122485332 #(.K(4)) dut (
    .frame_strobe(io_in[0]),
    .frame_data(frame_sr),
    .write_clk(io_in[1]),
    .write_en(io_in[2]),
    .write_data(io_in[3]),
    .write_addr(io_in[7:4]),
    .lut_i(io_in[6:3]),
    .lut_o(io_out[0])
  );

  assign io_out[7:1] = 6'b0;

endmodule
module user_module_341353780122485332(
  input [7:0] io_in, 
  output [7:0] io_out
);



  wire frame_sr_clk = io_in[1];
  reg [16:0] frame_sr;

  always @(posedge frame_sr_clk)
    frame_sr <= {frame_sr[15:0], io_in[2]};

  lutram_341353780122485332 #(.K(4)) dut (
    .frame_strobe(io_in[0]),
    .frame_data(frame_sr),
    .write_clk(io_in[1]),
    .write_en(io_in[2]),
    .write_data(io_in[3]),
    .write_addr(io_in[7:4]),
    .lut_i(io_in[6:3]),
    .lut_o(io_out[0])
  );

  assign io_out[7:1] = 6'b0;

endmodule