data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_mau.v
1: b'%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_mau.v:12: Cannot find include file: pa_chip_param.v\n`include "pa_chip_param.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core,data/full_repos/permissive/485610894/pa_chip_param.v\n             data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core,data/full_repos/permissive/485610894/pa_chip_param.v.v\n             data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core,data/full_repos/permissive/485610894/pa_chip_param.v.sv\n             pa_chip_param.v\n             pa_chip_param.v.v\n             pa_chip_param.v.sv\n             obj_dir/pa_chip_param.v\n             obj_dir/pa_chip_param.v.v\n             obj_dir/pa_chip_param.v.sv\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_mau.v:19: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    input  wire [`DATA_BUS_WIDTH-1:0]   mem_data_i,\n                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_mau.v:22: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    output wire [`DATA_BUS_WIDTH-1:0]   mem_data_o,\n                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_mau.v:25: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    input  wire [`DATA_BUS_WIDTH-1:0]   rbm_data_i,\n                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_mau.v:27: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    output wire [`DATA_BUS_WIDTH-1:0]   rbm_data_o,\n                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_mau.v:56: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nwire [`DATA_BUS_WIDTH-1:0]              mem_data;\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_mau.v:61: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nwire [`DATA_BUS_WIDTH-1:0]              mem_data_b0;\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_mau.v:62: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nwire [`DATA_BUS_WIDTH-1:0]              mem_data_b1;\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_mau.v:63: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nwire [`DATA_BUS_WIDTH-1:0]              mem_data_b2;\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_mau.v:64: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nwire [`DATA_BUS_WIDTH-1:0]              mem_data_b3;\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_mau.v:66: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nwire [`DATA_BUS_WIDTH-1:0]              mem_data_h0;\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_mau.v:67: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nwire [`DATA_BUS_WIDTH-1:0]              mem_data_h1;\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_mau.v:69: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nwire [`DATA_BUS_WIDTH-1:0]              mem_data_b;\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_mau.v:70: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nwire [`DATA_BUS_WIDTH-1:0]              mem_data_h;\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_mau.v:71: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nwire [`DATA_BUS_WIDTH-1:0]              mem_data_w;\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_mau.v:97: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nwire [`DATA_BUS_WIDTH-1:0]              mem_wdata;\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_mau.v:104: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nassign mem_data_o[`DATA_BUS_WIDTH-1:0] = {32{subop_sta2 && op_load }} & mem_wdata[`DATA_BUS_WIDTH-1:0];\n                  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_mau.v:104: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nassign mem_data_o[`DATA_BUS_WIDTH-1:0] = {32{subop_sta2 && op_load }} & mem_wdata[`DATA_BUS_WIDTH-1:0];\n                                                                                  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_mau.v:110: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nassign rbm_data_o[`DATA_BUS_WIDTH-1:0] = {32{subop_sta1 && op_store}} & mem_wdata[`DATA_BUS_WIDTH-1:0];\n                  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/core/pa_core_mau.v:110: Define or directive not defined: \'`DATA_BUS_WIDTH\'\nassign rbm_data_o[`DATA_BUS_WIDTH-1:0] = {32{subop_sta1 && op_store}} & mem_wdata[`DATA_BUS_WIDTH-1:0];\n                                                                                  ^~~~~~~~~~~~~~~\n%Error: Exiting due to 20 error(s)\n'
module pa_core_mau (
    input  wire [5:0]                   inst_func_i,

    input  wire [1:0]                   mem_addr_i,

    input  wire [`DATA_BUS_WIDTH-1:0]   mem_data_i,
    input  wire                         mem_data_vld_i,

    output wire [`DATA_BUS_WIDTH-1:0]   mem_data_o,
    output wire                         mem_data_vld_o,

    input  wire [`DATA_BUS_WIDTH-1:0]   rbm_data_i,

    output wire [`DATA_BUS_WIDTH-1:0]   rbm_data_o,
    output wire [2:0]                   rbm_size_o,
    output wire                         rbm_we_o,
    output wire                         rbm_rd_o
);

wire                                    subop_sta1;
wire                                    subop_sta2;

wire                                    subop_sign;

wire                                    subop_byte;
wire                                    subop_half;
wire                                    subop_word;

assign subop_sta1 = ~inst_func_i[5];
assign subop_sta2 =  inst_func_i[5];
assign subop_sign = ~inst_func_i[4];

assign subop_byte = (inst_func_i[3:2] == 2'b01);
assign subop_half = (inst_func_i[3:2] == 2'b10);
assign subop_word = (inst_func_i[3:2] == 2'b00);

wire                                    op_load;
wire                                    op_store;

assign op_load  = inst_func_i[1];
assign op_store = inst_func_i[0];

wire [`DATA_BUS_WIDTH-1:0]              mem_data;

assign mem_data = {32{subop_sta2 && op_load }} & rbm_data_i
                | {32{subop_sta1 && op_store}} & mem_data_i;

wire [`DATA_BUS_WIDTH-1:0]              mem_data_b0;
wire [`DATA_BUS_WIDTH-1:0]              mem_data_b1;
wire [`DATA_BUS_WIDTH-1:0]              mem_data_b2;
wire [`DATA_BUS_WIDTH-1:0]              mem_data_b3;

wire [`DATA_BUS_WIDTH-1:0]              mem_data_h0;
wire [`DATA_BUS_WIDTH-1:0]              mem_data_h1;

wire [`DATA_BUS_WIDTH-1:0]              mem_data_b;
wire [`DATA_BUS_WIDTH-1:0]              mem_data_h;
wire [`DATA_BUS_WIDTH-1:0]              mem_data_w;

assign mem_data_b0 = op_load ? {24'b0|{24{subop_sign && mem_data[ 7]}}, mem_data[ 7: 0]}
                             : {mem_data[31:0]};
assign mem_data_b1 = op_load ? {24'b0|{24{subop_sign && mem_data[15]}}, mem_data[15: 8]}
                             : {mem_data[23:0], 8'b0 };
assign mem_data_b2 = op_load ? {24'b0|{24{subop_sign && mem_data[23]}}, mem_data[23:16]}
                             : {mem_data[15:0], 16'b0};
assign mem_data_b3 = op_load ? {24'b0|{24{subop_sign && mem_data[31]}}, mem_data[31:24]}
                             : {mem_data[ 7:0], 24'b0};

assign mem_data_b  = {32{mem_addr_i[1:0] == 2'b00}} & mem_data_b0
                   | {32{mem_addr_i[1:0] == 2'b01}} & mem_data_b1
                   | {32{mem_addr_i[1:0] == 2'b10}} & mem_data_b2
                   | {32{mem_addr_i[1:0] == 2'b11}} & mem_data_b3;

assign mem_data_h0 = op_load ? {16'b0|{16{subop_sign && mem_data[15]}}, mem_data[15: 0]}
                             : {mem_data[31:0]};
assign mem_data_h1 = op_load ? {16'b0|{16{subop_sign && mem_data[31]}}, mem_data[31:16]}
                             : {mem_data[15:0], 16'b0};

assign mem_data_h  = {32{mem_addr_i[1] == 1'b0}} & mem_data_h0
                   | {32{mem_addr_i[1] == 1'b1}} & mem_data_h1;

assign mem_data_w  = {mem_data[31:0]};

wire [`DATA_BUS_WIDTH-1:0]              mem_wdata;

assign mem_wdata = {32{subop_byte}} & mem_data_b
                 | {32{subop_half}} & mem_data_h
                 | {32{subop_word}} & mem_data_w;


assign mem_data_o[`DATA_BUS_WIDTH-1:0] = {32{subop_sta2 && op_load }} & mem_wdata[`DATA_BUS_WIDTH-1:0];
assign mem_data_vld_o = subop_sta2 && op_load;


assign rbm_size_o = {subop_word, subop_half, subop_byte};

assign rbm_data_o[`DATA_BUS_WIDTH-1:0] = {32{subop_sta1 && op_store}} & mem_wdata[`DATA_BUS_WIDTH-1:0];
assign rbm_we_o = subop_sta1 && op_store;
assign rbm_rd_o = subop_sta1 && op_load;

endmodule
module pa_core_mau (
    input  wire [5:0]                   inst_func_i,

    input  wire [1:0]                   mem_addr_i,

    input  wire [`DATA_BUS_WIDTH-1:0]   mem_data_i,
    input  wire                         mem_data_vld_i,

    output wire [`DATA_BUS_WIDTH-1:0]   mem_data_o,
    output wire                         mem_data_vld_o,

    input  wire [`DATA_BUS_WIDTH-1:0]   rbm_data_i,

    output wire [`DATA_BUS_WIDTH-1:0]   rbm_data_o,
    output wire [2:0]                   rbm_size_o,
    output wire                         rbm_we_o,
    output wire                         rbm_rd_o
);


wire                                    subop_sta1;
wire                                    subop_sta2;

wire                                    subop_sign;

wire                                    subop_byte;
wire                                    subop_half;
wire                                    subop_word;

assign subop_sta1 = ~inst_func_i[5];
assign subop_sta2 =  inst_func_i[5];
assign subop_sign = ~inst_func_i[4];

assign subop_byte = (inst_func_i[3:2] == 2'b01);
assign subop_half = (inst_func_i[3:2] == 2'b10);
assign subop_word = (inst_func_i[3:2] == 2'b00);

wire                                    op_load;
wire                                    op_store;

assign op_load  = inst_func_i[1];
assign op_store = inst_func_i[0];

wire [`DATA_BUS_WIDTH-1:0]              mem_data;

assign mem_data = {32{subop_sta2 && op_load }} & rbm_data_i
                | {32{subop_sta1 && op_store}} & mem_data_i;

wire [`DATA_BUS_WIDTH-1:0]              mem_data_b0;
wire [`DATA_BUS_WIDTH-1:0]              mem_data_b1;
wire [`DATA_BUS_WIDTH-1:0]              mem_data_b2;
wire [`DATA_BUS_WIDTH-1:0]              mem_data_b3;

wire [`DATA_BUS_WIDTH-1:0]              mem_data_h0;
wire [`DATA_BUS_WIDTH-1:0]              mem_data_h1;

wire [`DATA_BUS_WIDTH-1:0]              mem_data_b;
wire [`DATA_BUS_WIDTH-1:0]              mem_data_h;
wire [`DATA_BUS_WIDTH-1:0]              mem_data_w;

assign mem_data_b0 = op_load ? {24'b0|{24{subop_sign && mem_data[ 7]}}, mem_data[ 7: 0]}
                             : {mem_data[31:0]};
assign mem_data_b1 = op_load ? {24'b0|{24{subop_sign && mem_data[15]}}, mem_data[15: 8]}
                             : {mem_data[23:0], 8'b0 };
assign mem_data_b2 = op_load ? {24'b0|{24{subop_sign && mem_data[23]}}, mem_data[23:16]}
                             : {mem_data[15:0], 16'b0};
assign mem_data_b3 = op_load ? {24'b0|{24{subop_sign && mem_data[31]}}, mem_data[31:24]}
                             : {mem_data[ 7:0], 24'b0};

assign mem_data_b  = {32{mem_addr_i[1:0] == 2'b00}} & mem_data_b0
                   | {32{mem_addr_i[1:0] == 2'b01}} & mem_data_b1
                   | {32{mem_addr_i[1:0] == 2'b10}} & mem_data_b2
                   | {32{mem_addr_i[1:0] == 2'b11}} & mem_data_b3;

assign mem_data_h0 = op_load ? {16'b0|{16{subop_sign && mem_data[15]}}, mem_data[15: 0]}
                             : {mem_data[31:0]};
assign mem_data_h1 = op_load ? {16'b0|{16{subop_sign && mem_data[31]}}, mem_data[31:16]}
                             : {mem_data[15:0], 16'b0};

assign mem_data_h  = {32{mem_addr_i[1] == 1'b0}} & mem_data_h0
                   | {32{mem_addr_i[1] == 1'b1}} & mem_data_h1;

assign mem_data_w  = {mem_data[31:0]};

wire [`DATA_BUS_WIDTH-1:0]              mem_wdata;

assign mem_wdata = {32{subop_byte}} & mem_data_b
                 | {32{subop_half}} & mem_data_h
                 | {32{subop_word}} & mem_data_w;


assign mem_data_o[`DATA_BUS_WIDTH-1:0] = {32{subop_sta2 && op_load }} & mem_wdata[`DATA_BUS_WIDTH-1:0];
assign mem_data_vld_o = subop_sta2 && op_load;


assign rbm_size_o = {subop_word, subop_half, subop_byte};

assign rbm_data_o[`DATA_BUS_WIDTH-1:0] = {32{subop_sta1 && op_store}} & mem_wdata[`DATA_BUS_WIDTH-1:0];
assign rbm_we_o = subop_sta1 && op_store;
assign rbm_rd_o = subop_sta1 && op_load;

endmodule