data/full_repos/permissive/493441306/Verilog Language/procedures/02_alwaysif.v
1: b'%Error: Cannot find file containing module: Language/procedures,data/full_repos/permissive/493441306\n        ... Looked in:\n             data/full_repos/permissive/493441306/Verilog/Language/procedures,data/full_repos/permissive/493441306\n             data/full_repos/permissive/493441306/Verilog/Language/procedures,data/full_repos/permissive/493441306.v\n             data/full_repos/permissive/493441306/Verilog/Language/procedures,data/full_repos/permissive/493441306.sv\n             Language/procedures,data/full_repos/permissive/493441306\n             Language/procedures,data/full_repos/permissive/493441306.v\n             Language/procedures,data/full_repos/permissive/493441306.sv\n             obj_dir/Language/procedures,data/full_repos/permissive/493441306\n             obj_dir/Language/procedures,data/full_repos/permissive/493441306.v\n             obj_dir/Language/procedures,data/full_repos/permissive/493441306.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/493441306/Verilog\n%Error: Cannot find file containing module: Language/procedures/02_alwaysif.v\n%Error: Exiting due to 3 error(s)\n'
module top_module(
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output wire out_assign,
    output reg out_always   ); 
    
    assign out_assign = (sel_b1 & sel_b2) ? b : a;  
    
    always@(*) begin
        if ( sel_b1 & sel_b2 )
            out_always = b;
        else
            out_always = a;
    end

endmodule
module top_module(
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output wire out_assign,
    output reg out_always   );
 
    
    assign out_assign = (sel_b1 & sel_b2) ? b : a;  
    
    always@(*) begin
        if ( sel_b1 & sel_b2 )
            out_always = b;
        else
            out_always = a;
    end

endmodule