data/full_repos/permissive/436064619/tb_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_test.v:22: Unsupported: Ignoring delay on this delayed statement.\nforever #T  clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/436064619/tb_test.v:27: Unsupported: $fopen with multichannel descriptor.  Add ,"w" as second argument to open a file descriptor.\nhandle3 = $fopen ("stim_proj.out");\n          ^~~~~~\n%Error: data/full_repos/permissive/436064619/tb_test.v:28: Unsupported or unknown PLI call: $shm_open\n  $shm_open("shm.db",1);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/436064619/tb_test.v:29: Unsupported or unknown PLI call: $shm_probe\n  $shm_probe(stimulus,"AS");\n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/436064619/tb_test.v:30: Unsupported or unknown PLI call: $shm_close\n  #500  $shm_close();\n        ^~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_test.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #500  $shm_close();\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_test.v:31: Unsupported: Ignoring delay on this delayed statement.\n  #1 $finish;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_test.v:38: Unsupported: Ignoring delay on this delayed statement.\n#1 $fdisplay(desc3, $time,"clk=%b, addressA=%d, addressB=%d, dataIn=%d, opsel=%d, outsel=%d, asel=%d, bsel=%d, oen=%d, OUT=%d", clk, addressA, addressB, dataIn, opsel, outsel,asel, bsel, oen, outPut);\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_test.v:47: Unsupported: Ignoring delay on this delayed statement.\n#T\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_test.v:56: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_test.v:67: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_test.v:78: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_test.v:89: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_test.v:100: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_test.v:111: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_test.v:122: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_test.v:133: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_test.v:144: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_test.v:155: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_test.v:166: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_test.v:177: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_test.v:188: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_test.v:199: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_test.v:210: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_test.v:221: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_test.v:232: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_test.v:243: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_test.v:264: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_test.v:275: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_test.v:286: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_test.v:297: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Warning-STMTDLY: data/full_repos/permissive/436064619/tb_test.v:308: Unsupported: Ignoring delay on this delayed statement.\n#(T*2)\n^\n%Error: Exiting due to 4 error(s), 28 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module stimulus;

parameter T = 20;

reg [31:0] dataIn;
reg [1:0] opsel, outsel;
reg [4:0] addressA, addressB;
reg asel, bsel, oen, clk;

wire [31:0] outPut;
wire over;


integer handle3,desc3;


cpu proj(addressA, addressB, dataIn, asel,bsel, clk, opsel, outsel, oen, outPut, over);
initial
begin
clk = 1'b1;
forever #T  clk = ~clk;
end

initial
 begin
handle3 = $fopen ("stim_proj.out");
  $shm_open("shm.db",1);
  $shm_probe(stimulus,"AS");
  #500  $shm_close();
  #1 $finish;
  end


always
begin
desc3=handle3;
#1 $fdisplay(desc3, $time,"clk=%b, addressA=%d, addressB=%d, dataIn=%d, opsel=%d, outsel=%d, asel=%d, bsel=%d, oen=%d, OUT=%d", clk, addressA, addressB, dataIn, opsel, outsel,asel, bsel, oen, outPut);

end


initial
 begin


#T
addressA = 5'b00000;
addressB = 5'b00000;
dataIn = 32'h0000_0005;
opsel = 2'b01;
outsel =2'b00;
asel = 0;
bsel = 0;
oen = 1;
#(T*2)


addressA=5'b00000;
addressB= 5'b00001;
dataIn = 32'hAAAA_AAAB;
opsel = 2'b01;
outsel = 2'b00;
asel = 0;
bsel = 0;
oen = 1;
#(T*2)


addressA = 5'b00000;
addressB = 5'b00010;
dataIn = 32'h5555_5555;
opsel = 2'b01;
outsel =2'b00;
asel = 0;
bsel = 0;
oen = 1;
#(T*2)


addressA = 5'b00000;
addressB = 5'b00011;
dataIn = 32'h0000_000A;
opsel = 2'b01;
outsel =2'b00;
asel = 0;
bsel = 0;
oen = 1;
#(T*2)


addressA = 5'b00000;
addressB = 5'b00100;
dataIn = 32'h0000_000B;
opsel = 2'b01;
outsel =2'b00;
asel = 0;
bsel = 0;
oen = 1;
#(T*2)


addressA = 5'b00000;
addressB = 5'b00101;
dataIn = 32'hFFFF_FFFF;
opsel = 2'b01;
outsel =2'b00;
asel = 0;
bsel = 0;
oen = 1;
#(T*2)


addressA = 5'b00000;
addressB = 5'b00110;
dataIn = 32'h0000_00C8;
opsel = 2'b01;
outsel =2'b00;
asel = 0;
bsel = 0;
oen = 1;
#(T*2)


addressA = 5'b00000;
addressB = 5'b00111;
dataIn = 32'h0000_012C;
opsel = 2'b01;
outsel =2'b00;
asel = 0;
bsel = 0;
oen = 1;
#(T*2)


addressA = 5'b00000;
addressB = 5'b01000;
dataIn = 32'h0000_0001;
opsel = 2'b01;
outsel =2'b00;
asel = 0;
bsel = 0;
oen = 1;
#(T*2)


addressA = 5'b00000;
addressB = 5'b01001;
dataIn = 32'hAAAA_AAA6;
opsel = 2'b01;
outsel =2'b00;
asel = 0;
bsel = 0;
oen = 1;
#(T*2)


addressA = 5'b00000;
addressB = 5'b01010;
dataIn = 32'h5555_555A;
opsel = 2'b01;
outsel =2'b00;
asel = 0;
bsel = 0;
oen = 1;
#(T*2)


addressA = 5'd2;
addressB = 5'd0;
dataIn = 32'd0;
opsel = 2'b00;
outsel =2'b01;
asel = 1;
bsel = 1;
oen = 1;
#(T*2)


addressA = 5'd1;
addressB = 5'd2;
dataIn = 32'd0;
opsel = 2'b00;
outsel =2'b01;
asel = 1;
bsel = 1;
oen = 1;
#(T*2)


addressA = 5'd6;
addressB = 5'd7;
dataIn = 32'd0;
opsel = 2'b00;
outsel =2'b01;
asel = 1;
bsel = 1;
oen = 1;
#(T*2)


addressA = 5'd5;
addressB = 5'd8;
dataIn = 32'd0;
opsel = 2'b00;
outsel =2'b01;
asel = 1;
bsel = 1;
oen = 1;
#(T*2)


addressA = 5'd2;
addressB = 5'd4;
dataIn = 32'd0;
opsel = 2'b01;
outsel =2'b01;
asel = 1;
bsel = 1;
oen = 1;
#(T*2)


addressA = 5'd8;
addressB = 5'd8;
dataIn = 32'd0;
opsel = 2'b01;
outsel =2'b00;
asel = 1;
bsel = 0;
oen = 1;
#(T*2)


addressA = 5'd4;
addressB = 5'd4;
dataIn = 32'd0;
opsel = 2'b01;
outsel =2'b00;
asel = 1;
bsel = 0;
oen = 1;
#(T*2)


addressA = 5'd2;
addressB = 5'd2;
dataIn = 32'd0;
opsel = 2'b01;
outsel =2'b00;
asel = 1;
bsel = 0;
oen = 1;


addressA = 5'd4;
addressB = 5'd2;
dataIn = 32'd0;
opsel = 2'b00;
outsel =2'b01;
asel = 1;
bsel = 1;
oen = 1;
#(T*2)


addressA = 5'd3;
addressB = 5'd7;
dataIn = 32'd0;
opsel = 2'b01;
outsel =2'b01;
asel = 1;
bsel = 1;
oen = 1;
#(T*2)


addressA = 5'd0;
addressB = 5'd9;
dataIn = 32'd0;
opsel = 2'b00;
outsel =2'b01;
asel = 1;
bsel = 1;
oen = 1;
#(T*2)


addressA = 5'd10;
addressB = 5'd10;
dataIn = 32'd0;
opsel = 2'b01;
outsel =2'b00;
asel = 1;
bsel = 0;
oen = 1;
#(T*2)


addressA = 5'd0;
addressB = 5'd0;
dataIn = 32'd0;
opsel = 2'b01;
outsel =2'b00;
asel = 1;
bsel = 0;
oen = 1;
#(T*2)


addressA = 5'd8;
addressB = 5'd8;
dataIn = 32'd0;
opsel = 2'b01;
outsel =2'b00;
asel = 1;
bsel = 0;
oen = 1;

end


endmodule
module stimulus;


parameter T = 20;

reg [31:0] dataIn;
reg [1:0] opsel, outsel;
reg [4:0] addressA, addressB;
reg asel, bsel, oen, clk;

wire [31:0] outPut;
wire over;


integer handle3,desc3;


cpu proj(addressA, addressB, dataIn, asel,bsel, clk, opsel, outsel, oen, outPut, over);
initial
begin
clk = 1'b1;
forever #T  clk = ~clk;
end

initial
 begin
handle3 = $fopen ("stim_proj.out");
  $shm_open("shm.db",1);
  $shm_probe(stimulus,"AS");
  #500  $shm_close();
  #1 $finish;
  end


always
begin
desc3=handle3;
#1 $fdisplay(desc3, $time,"clk=%b, addressA=%d, addressB=%d, dataIn=%d, opsel=%d, outsel=%d, asel=%d, bsel=%d, oen=%d, OUT=%d", clk, addressA, addressB, dataIn, opsel, outsel,asel, bsel, oen, outPut);

end


initial
 begin


#T
addressA = 5'b00000;
addressB = 5'b00000;
dataIn = 32'h0000_0005;
opsel = 2'b01;
outsel =2'b00;
asel = 0;
bsel = 0;
oen = 1;
#(T*2)


addressA=5'b00000;
addressB= 5'b00001;
dataIn = 32'hAAAA_AAAB;
opsel = 2'b01;
outsel = 2'b00;
asel = 0;
bsel = 0;
oen = 1;
#(T*2)


addressA = 5'b00000;
addressB = 5'b00010;
dataIn = 32'h5555_5555;
opsel = 2'b01;
outsel =2'b00;
asel = 0;
bsel = 0;
oen = 1;
#(T*2)


addressA = 5'b00000;
addressB = 5'b00011;
dataIn = 32'h0000_000A;
opsel = 2'b01;
outsel =2'b00;
asel = 0;
bsel = 0;
oen = 1;
#(T*2)


addressA = 5'b00000;
addressB = 5'b00100;
dataIn = 32'h0000_000B;
opsel = 2'b01;
outsel =2'b00;
asel = 0;
bsel = 0;
oen = 1;
#(T*2)


addressA = 5'b00000;
addressB = 5'b00101;
dataIn = 32'hFFFF_FFFF;
opsel = 2'b01;
outsel =2'b00;
asel = 0;
bsel = 0;
oen = 1;
#(T*2)


addressA = 5'b00000;
addressB = 5'b00110;
dataIn = 32'h0000_00C8;
opsel = 2'b01;
outsel =2'b00;
asel = 0;
bsel = 0;
oen = 1;
#(T*2)


addressA = 5'b00000;
addressB = 5'b00111;
dataIn = 32'h0000_012C;
opsel = 2'b01;
outsel =2'b00;
asel = 0;
bsel = 0;
oen = 1;
#(T*2)


addressA = 5'b00000;
addressB = 5'b01000;
dataIn = 32'h0000_0001;
opsel = 2'b01;
outsel =2'b00;
asel = 0;
bsel = 0;
oen = 1;
#(T*2)


addressA = 5'b00000;
addressB = 5'b01001;
dataIn = 32'hAAAA_AAA6;
opsel = 2'b01;
outsel =2'b00;
asel = 0;
bsel = 0;
oen = 1;
#(T*2)


addressA = 5'b00000;
addressB = 5'b01010;
dataIn = 32'h5555_555A;
opsel = 2'b01;
outsel =2'b00;
asel = 0;
bsel = 0;
oen = 1;
#(T*2)


addressA = 5'd2;
addressB = 5'd0;
dataIn = 32'd0;
opsel = 2'b00;
outsel =2'b01;
asel = 1;
bsel = 1;
oen = 1;
#(T*2)


addressA = 5'd1;
addressB = 5'd2;
dataIn = 32'd0;
opsel = 2'b00;
outsel =2'b01;
asel = 1;
bsel = 1;
oen = 1;
#(T*2)


addressA = 5'd6;
addressB = 5'd7;
dataIn = 32'd0;
opsel = 2'b00;
outsel =2'b01;
asel = 1;
bsel = 1;
oen = 1;
#(T*2)


addressA = 5'd5;
addressB = 5'd8;
dataIn = 32'd0;
opsel = 2'b00;
outsel =2'b01;
asel = 1;
bsel = 1;
oen = 1;
#(T*2)


addressA = 5'd2;
addressB = 5'd4;
dataIn = 32'd0;
opsel = 2'b01;
outsel =2'b01;
asel = 1;
bsel = 1;
oen = 1;
#(T*2)


addressA = 5'd8;
addressB = 5'd8;
dataIn = 32'd0;
opsel = 2'b01;
outsel =2'b00;
asel = 1;
bsel = 0;
oen = 1;
#(T*2)


addressA = 5'd4;
addressB = 5'd4;
dataIn = 32'd0;
opsel = 2'b01;
outsel =2'b00;
asel = 1;
bsel = 0;
oen = 1;
#(T*2)


addressA = 5'd2;
addressB = 5'd2;
dataIn = 32'd0;
opsel = 2'b01;
outsel =2'b00;
asel = 1;
bsel = 0;
oen = 1;


addressA = 5'd4;
addressB = 5'd2;
dataIn = 32'd0;
opsel = 2'b00;
outsel =2'b01;
asel = 1;
bsel = 1;
oen = 1;
#(T*2)


addressA = 5'd3;
addressB = 5'd7;
dataIn = 32'd0;
opsel = 2'b01;
outsel =2'b01;
asel = 1;
bsel = 1;
oen = 1;
#(T*2)


addressA = 5'd0;
addressB = 5'd9;
dataIn = 32'd0;
opsel = 2'b00;
outsel =2'b01;
asel = 1;
bsel = 1;
oen = 1;
#(T*2)


addressA = 5'd10;
addressB = 5'd10;
dataIn = 32'd0;
opsel = 2'b01;
outsel =2'b00;
asel = 1;
bsel = 0;
oen = 1;
#(T*2)


addressA = 5'd0;
addressB = 5'd0;
dataIn = 32'd0;
opsel = 2'b01;
outsel =2'b00;
asel = 1;
bsel = 0;
oen = 1;
#(T*2)


addressA = 5'd8;
addressB = 5'd8;
dataIn = 32'd0;
opsel = 2'b01;
outsel =2'b00;
asel = 1;
bsel = 0;
oen = 1;

end


endmodule