data/full_repos/permissive/519759804/test_delayslot/ForwardingUnit.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/519759804/test_delayslot/ForwardingUnit.v:29: Multiple top level modules\n                                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                          : ... Top module \'RAW_Forwarding\'\nmodule RAW_Forwarding(IDEX_Rs, IDEX_Rt, EXMEM_RegWr, EXMEM_RegWrAddr, MEMWB_RegWr, MEMWB_RegWrAddr, ForwardA, ForwardB);\n       ^~~~~~~~~~~~~~\n                                                                                          : ... Top module \'SAL_Forwarding\'\nmodule SAL_Forwarding(EXMEM_MemWr, EXMEM_Rt, MEMWB_MemRead, MEMWB_RegWrAddr, Forward);\n       ^~~~~~~~~~~~~~\n                                                                                          : ... Top module \'JAW_Forwarding\'\nmodule JAW_Forwarding(ID_OpCode, ID_Funct, ID_Rs, IDEX_RegWr, IDEX_RegWrAddr, EXMEM_MemtoReg, EXMEM_RegWr, EXMEM_RegWrAddr, Forward);\n       ^~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module RAW_Forwarding(IDEX_Rs, IDEX_Rt, EXMEM_RegWr, EXMEM_RegWrAddr, MEMWB_RegWr, MEMWB_RegWrAddr, ForwardA, ForwardB);
	input [4:0] IDEX_Rs;
	input [4:0] IDEX_Rt;
	input EXMEM_RegWr;
	input [4:0] EXMEM_RegWrAddr;
	input MEMWB_RegWr;
	input [4:0] MEMWB_RegWrAddr;
	output [1:0] ForwardA;
	output [1:0] ForwardB;
	

	wire conditionA1=IDEX_Rs != 0 && EXMEM_RegWr && EXMEM_RegWrAddr==IDEX_Rs;
	wire conditionB1=IDEX_Rt != 0 && EXMEM_RegWr && EXMEM_RegWrAddr==IDEX_Rt;

	wire conditionA2=IDEX_Rs != 0 && MEMWB_RegWr && MEMWB_RegWrAddr == IDEX_Rs;
	wire conditionB2=IDEX_Rt != 0 && MEMWB_RegWr && MEMWB_RegWrAddr == IDEX_Rt;
	assign ForwardA=conditionA1?2'b01:
					conditionA2?2'b10:
					2'b00;
	assign ForwardB=conditionB1?2'b01:
					conditionB2?2'b10:
					2'b00;
endmodule
module RAW_Forwarding(IDEX_Rs, IDEX_Rt, EXMEM_RegWr, EXMEM_RegWrAddr, MEMWB_RegWr, MEMWB_RegWrAddr, ForwardA, ForwardB);

	input [4:0] IDEX_Rs;
	input [4:0] IDEX_Rt;
	input EXMEM_RegWr;
	input [4:0] EXMEM_RegWrAddr;
	input MEMWB_RegWr;
	input [4:0] MEMWB_RegWrAddr;
	output [1:0] ForwardA;
	output [1:0] ForwardB;
	

	wire conditionA1=IDEX_Rs != 0 && EXMEM_RegWr && EXMEM_RegWrAddr==IDEX_Rs;
	wire conditionB1=IDEX_Rt != 0 && EXMEM_RegWr && EXMEM_RegWrAddr==IDEX_Rt;

	wire conditionA2=IDEX_Rs != 0 && MEMWB_RegWr && MEMWB_RegWrAddr == IDEX_Rs;
	wire conditionB2=IDEX_Rt != 0 && MEMWB_RegWr && MEMWB_RegWrAddr == IDEX_Rt;
	assign ForwardA=conditionA1?2'b01:
					conditionA2?2'b10:
					2'b00;
	assign ForwardB=conditionB1?2'b01:
					conditionB2?2'b10:
					2'b00;
endmodule