data/full_repos/permissive/526589127/verilog/rtl/b_box/r8_8bit.v
1: b'%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/r8_8bit.v:2: Cannot find include file: ./const/parameters_r8mb8.v\n`include "./const/parameters_r8mb8.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters_r8mb8.v\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters_r8mb8.v.v\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters_r8mb8.v.sv\n             ./const/parameters_r8mb8.v\n             ./const/parameters_r8mb8.v.v\n             ./const/parameters_r8mb8.v.sv\n             obj_dir/./const/parameters_r8mb8.v\n             obj_dir/./const/parameters_r8mb8.v.v\n             obj_dir/./const/parameters_r8mb8.v.sv\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/r8_8bit.v:304: Cannot find include file: ./const/parameters_r8mb8.v\n`include "./const/parameters_r8mb8.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module booth3_encoder (x, single, double, triple, quad, neg, pzero, nzero);

input [3:0]x;

output single;

output  double;

output triple;

output  quad;

output neg;

output pzero;

output nzero;

wire w0;

wire w1;

wire w2;

wire w3;

wire w4;

wire w5;

assign neg=x[3];

assign w0=x[0]^x[1];

assign w1=x[1]^x[2];

assign w2=x[2]^x[3];

assign single=~((~w0)|w2);

assign double=~((~w1)|w0);

assign triple=~((~w2)|(~w0));

assign quad=~((~w2)|(w0|w1));

assign pzero = ~x[0] & ~x[1] & ~x[2] & ~x[3] ;

assign nzero = x[0] & x[1] & x[2]& x[3];

endmodule
module booth3_encoder (x, single, double, triple, quad, neg, pzero, nzero);


input [3:0]x;

output single;

output  double;

output triple;

output  quad;

output neg;

output pzero;

output nzero;

wire w0;

wire w1;

wire w2;

wire w3;

wire w4;

wire w5;

assign neg=x[3];

assign w0=x[0]^x[1];

assign w1=x[1]^x[2];

assign w2=x[2]^x[3];

assign single=~((~w0)|w2);

assign double=~((~w1)|w0);

assign triple=~((~w2)|(~w0));

assign quad=~((~w2)|(w0|w1));

assign pzero = ~x[0] & ~x[1] & ~x[2] & ~x[3] ;

assign nzero = x[0] & x[1] & x[2]& x[3];

endmodule