data/full_repos/permissive/434840709/week14/2/2.v
data/verilator_xmls/e54c6598-2290-4e43-91f7-e2716e3ed068.xml
module top_module(
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    output reg walk_right,
    output reg walk_left,
    output reg aaah 
);

    reg [1:0]state,next_state;
    parameter WL=0,WR=1,FL=2,FR=3;
    always @(*) begin
        case(state)
            WL: next_state = ground? ( bump_left ? WR:WL):FL;
            WR: next_state = ground? ( bump_right? WL:WR):FR;
            FL: next_state = ground? WL : FL;
            FR: next_state = ground? WR : FR;
        endcase
    end

    always @(posedge clk or posedge areset)begin
        if(areset) state <= WL;
        else state <= next_state;
    end

    always @(*) begin
        case(state)
            WL:  {walk_left,walk_right,aaah}=3'b100;
            WR:  {walk_left,walk_right,aaah}=3'b010;
            FL:  {walk_left,walk_right,aaah}=3'b001;
            FR:  {walk_left,walk_right,aaah}=3'b001;
        endcase
    end 
            
endmodule
module top_module(
    input clk,
    input areset,
    input bump_left,
    input bump_right,
    input ground,
    output reg walk_right,
    output reg walk_left,
    output reg aaah 
);


    reg [1:0]state,next_state;
    parameter WL=0,WR=1,FL=2,FR=3;
    always @(*) begin
        case(state)
            WL: next_state = ground? ( bump_left ? WR:WL):FL;
            WR: next_state = ground? ( bump_right? WL:WR):FR;
            FL: next_state = ground? WL : FL;
            FR: next_state = ground? WR : FR;
        endcase
    end

    always @(posedge clk or posedge areset)begin
        if(areset) state <= WL;
        else state <= next_state;
    end

    always @(*) begin
        case(state)
            WL:  {walk_left,walk_right,aaah}=3'b100;
            WR:  {walk_left,walk_right,aaah}=3'b010;
            FL:  {walk_left,walk_right,aaah}=3'b001;
            FR:  {walk_left,walk_right,aaah}=3'b001;
        endcase
    end 
            
endmodule