data/full_repos/permissive/493019833/test/testcase/firrtl/PipeTester/reference/PipeTester.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/PipeTester/reference/PipeTester.v:205: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                               : ... In instance PipeTester.u_pad_5\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/PipeTester/reference/PipeTester.v:205: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 2 bits.\n                                                                                                               : ... In instance PipeTester.u_pad_9\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/PipeTester/reference/PipeTester.v:166: Input port connection \'a\' expects 4 bits on the pin connection, but pin connection\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                               : ... In instance PipeTester.pipe\n        .a(1\'d0),\n         ^\n%Error: Exiting due to 3 warning(s)\n'
module PipeTester(
    input clock,
    input reset
);
    wire _pipe__clock;
    wire _pipe__reset;
    wire [3:0] _pipe__in;
    wire [3:0] _pipe__out;
    Pipe pipe (
        .clock(_pipe__clock),
        .reset(_pipe__reset),
        .in(_pipe__in),
        .out(_pipe__out)
    );
    wire [3:0] _cycle__q;
    wire [3:0] _cycle__d;
    DFF_POSCLK #(.width(4)) cycle (
        .q(_cycle__q),
        .d(_cycle__d),
        .clk(clock)
    );
    wire [3:0] _WTEMP_2;
    MUX_UNSIGNED #(.width(4)) u_mux_4 (
        .y(_cycle__d),
        .sel(reset),
        .a(4'd0),
        .b(_WTEMP_2)
    );
    wire [4:0] _node_0;
    wire [3:0] _WTEMP_3;
    PAD_UNSIGNED #(.width(1), .n(4)) u_pad_5 (
        .y(_WTEMP_3),
        .in(1'd1)
    );
    ADD_UNSIGNED #(.width(4)) u_add_6 (
        .y(_node_0),
        .a(_cycle__q),
        .b(_WTEMP_3)
    );
    wire fail;
    wire _node_1;
    wire [3:0] _WTEMP_4;
    PAD_UNSIGNED #(.width(1), .n(4)) u_pad_7 (
        .y(_WTEMP_4),
        .in(1'd0)
    );
    NEQ_UNSIGNED #(.width(4)) u_neq_8 (
        .y(_node_1),
        .a(_pipe__out),
        .b(_WTEMP_4)
    );
    wire _node_2;
    wire [3:0] _WTEMP_5;
    PAD_UNSIGNED #(.width(2), .n(4)) u_pad_9 (
        .y(_WTEMP_5),
        .in(2'd2)
    );
    LT_UNSIGNED #(.width(4)) u_lt_10 (
        .y(_node_2),
        .a(_cycle__q),
        .b(_WTEMP_5)
    );
    wire _node_3;
    MUX_UNSIGNED #(.width(1)) u_mux_11 (
        .y(_node_3),
        .sel(_node_1),
        .a(1'h1),
        .b(1'h0)
    );
    wire _node_4;
    wire [3:0] _WTEMP_6;
    PAD_UNSIGNED #(.width(2), .n(4)) u_pad_12 (
        .y(_WTEMP_6),
        .in(2'd3)
    );
    NEQ_UNSIGNED #(.width(4)) u_neq_13 (
        .y(_node_4),
        .a(_pipe__out),
        .b(_WTEMP_6)
    );
    wire _node_5;
    MUX_UNSIGNED #(.width(1)) u_mux_14 (
        .y(_node_5),
        .sel(_node_2),
        .a(_node_3),
        .b(1'h0)
    );
    wire _node_6;
    wire [3:0] _WTEMP_7;
    PAD_UNSIGNED #(.width(2), .n(4)) u_pad_15 (
        .y(_WTEMP_7),
        .in(2'd2)
    );
    EQ_UNSIGNED #(.width(4)) u_eq_16 (
        .y(_node_6),
        .a(_cycle__q),
        .b(_WTEMP_7)
    );
    wire _node_7;
    MUX_UNSIGNED #(.width(1)) u_mux_17 (
        .y(_node_7),
        .sel(_node_4),
        .a(1'h1),
        .b(_node_5)
    );
    wire _node_8;
    MUX_UNSIGNED #(.width(1)) u_mux_18 (
        .y(_node_8),
        .sel(_node_2),
        .a(_node_3),
        .b(1'h0)
    );
    wire _node_9;
    BITWISENOT #(.width(1)) bitwisenot_19 (
        .y(_node_9),
        .in(reset)
    );
    wire _node_10;
    MUX_UNSIGNED #(.width(1)) u_mux_20 (
        .y(_node_10),
        .sel(_node_6),
        .a(_node_7),
        .b(_node_8)
    );
    TAIL #(.width(5), .n(1)) tail_21 (
        .y(_WTEMP_2),
        .in(_node_0)
    );
    MUX_UNSIGNED #(.width(1)) u_mux_22 (
        .y(fail),
        .sel(_node_9),
        .a(_node_10),
        .b(1'h0)
    );
    assign _pipe__clock = clock;
    PAD_UNSIGNED #(.width(2), .n(4)) u_pad_23 (
        .y(_pipe__in),
        .in(2'h3)
    );
    assign _pipe__reset = reset;
endmodule
module PipeTester(
    input clock,
    input reset
);

    wire _pipe__clock;
    wire _pipe__reset;
    wire [3:0] _pipe__in;
    wire [3:0] _pipe__out;
    Pipe pipe (
        .clock(_pipe__clock),
        .reset(_pipe__reset),
        .in(_pipe__in),
        .out(_pipe__out)
    );
    wire [3:0] _cycle__q;
    wire [3:0] _cycle__d;
    DFF_POSCLK #(.width(4)) cycle (
        .q(_cycle__q),
        .d(_cycle__d),
        .clk(clock)
    );
    wire [3:0] _WTEMP_2;
    MUX_UNSIGNED #(.width(4)) u_mux_4 (
        .y(_cycle__d),
        .sel(reset),
        .a(4'd0),
        .b(_WTEMP_2)
    );
    wire [4:0] _node_0;
    wire [3:0] _WTEMP_3;
    PAD_UNSIGNED #(.width(1), .n(4)) u_pad_5 (
        .y(_WTEMP_3),
        .in(1'd1)
    );
    ADD_UNSIGNED #(.width(4)) u_add_6 (
        .y(_node_0),
        .a(_cycle__q),
        .b(_WTEMP_3)
    );
    wire fail;
    wire _node_1;
    wire [3:0] _WTEMP_4;
    PAD_UNSIGNED #(.width(1), .n(4)) u_pad_7 (
        .y(_WTEMP_4),
        .in(1'd0)
    );
    NEQ_UNSIGNED #(.width(4)) u_neq_8 (
        .y(_node_1),
        .a(_pipe__out),
        .b(_WTEMP_4)
    );
    wire _node_2;
    wire [3:0] _WTEMP_5;
    PAD_UNSIGNED #(.width(2), .n(4)) u_pad_9 (
        .y(_WTEMP_5),
        .in(2'd2)
    );
    LT_UNSIGNED #(.width(4)) u_lt_10 (
        .y(_node_2),
        .a(_cycle__q),
        .b(_WTEMP_5)
    );
    wire _node_3;
    MUX_UNSIGNED #(.width(1)) u_mux_11 (
        .y(_node_3),
        .sel(_node_1),
        .a(1'h1),
        .b(1'h0)
    );
    wire _node_4;
    wire [3:0] _WTEMP_6;
    PAD_UNSIGNED #(.width(2), .n(4)) u_pad_12 (
        .y(_WTEMP_6),
        .in(2'd3)
    );
    NEQ_UNSIGNED #(.width(4)) u_neq_13 (
        .y(_node_4),
        .a(_pipe__out),
        .b(_WTEMP_6)
    );
    wire _node_5;
    MUX_UNSIGNED #(.width(1)) u_mux_14 (
        .y(_node_5),
        .sel(_node_2),
        .a(_node_3),
        .b(1'h0)
    );
    wire _node_6;
    wire [3:0] _WTEMP_7;
    PAD_UNSIGNED #(.width(2), .n(4)) u_pad_15 (
        .y(_WTEMP_7),
        .in(2'd2)
    );
    EQ_UNSIGNED #(.width(4)) u_eq_16 (
        .y(_node_6),
        .a(_cycle__q),
        .b(_WTEMP_7)
    );
    wire _node_7;
    MUX_UNSIGNED #(.width(1)) u_mux_17 (
        .y(_node_7),
        .sel(_node_4),
        .a(1'h1),
        .b(_node_5)
    );
    wire _node_8;
    MUX_UNSIGNED #(.width(1)) u_mux_18 (
        .y(_node_8),
        .sel(_node_2),
        .a(_node_3),
        .b(1'h0)
    );
    wire _node_9;
    BITWISENOT #(.width(1)) bitwisenot_19 (
        .y(_node_9),
        .in(reset)
    );
    wire _node_10;
    MUX_UNSIGNED #(.width(1)) u_mux_20 (
        .y(_node_10),
        .sel(_node_6),
        .a(_node_7),
        .b(_node_8)
    );
    TAIL #(.width(5), .n(1)) tail_21 (
        .y(_WTEMP_2),
        .in(_node_0)
    );
    MUX_UNSIGNED #(.width(1)) u_mux_22 (
        .y(fail),
        .sel(_node_9),
        .a(_node_10),
        .b(1'h0)
    );
    assign _pipe__clock = clock;
    PAD_UNSIGNED #(.width(2), .n(4)) u_pad_23 (
        .y(_pipe__in),
        .in(2'h3)
    );
    assign _pipe__reset = reset;
endmodule