data/full_repos/permissive/51854321/bcd_decoder.v
1: b'%Warning-WIDTH: data/full_repos/permissive/51854321/bcd_decoder.v:26: Operator SHIFTL expects 9 bits on the LHS, but LHS\'s VARREF \'bcd_bit\' generates 1 bits.\n                                                                    : ... In instance bcd_decoder\n    assign value = (bcd_bit << bcd_bit_idx) * bcd_multiplier;\n                            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module bcd_decoder (
                    input [2:0]      bcd_bit_idx ,
                    input [1:0]      bcd_digit_idx ,
                    input            bcd_bit,
                    output [8:0] value);




    
    reg [6:0]                    bcd_multiplier;
    
    always @(*) begin
        case (bcd_digit_idx)
          2'd0:
            bcd_multiplier = 7'd1;
          2'd1:
            bcd_multiplier = 7'd10;
          2'd2:
            bcd_multiplier = 7'd100;
          default:
            bcd_multiplier = 7'd0;
          endcase
    end

    assign value = (bcd_bit << bcd_bit_idx) * bcd_multiplier;

endmodule
module bcd_decoder (
                    input [2:0]      bcd_bit_idx ,
                    input [1:0]      bcd_digit_idx ,
                    input            bcd_bit,
                    output [8:0] value);





    
    reg [6:0]                    bcd_multiplier;
    
    always @(*) begin
        case (bcd_digit_idx)
          2'd0:
            bcd_multiplier = 7'd1;
          2'd1:
            bcd_multiplier = 7'd10;
          2'd2:
            bcd_multiplier = 7'd100;
          default:
            bcd_multiplier = 7'd0;
          endcase
    end

    assign value = (bcd_bit << bcd_bit_idx) * bcd_multiplier;

endmodule