data/full_repos/permissive/498662723/Verilog Language/Basics/xnorgate.v
1: b'%Error: Cannot find file containing module: Language/Basics,data/full_repos/permissive/498662723\n        ... Looked in:\n             data/full_repos/permissive/498662723/Verilog/Language/Basics,data/full_repos/permissive/498662723\n             data/full_repos/permissive/498662723/Verilog/Language/Basics,data/full_repos/permissive/498662723.v\n             data/full_repos/permissive/498662723/Verilog/Language/Basics,data/full_repos/permissive/498662723.sv\n             Language/Basics,data/full_repos/permissive/498662723\n             Language/Basics,data/full_repos/permissive/498662723.v\n             Language/Basics,data/full_repos/permissive/498662723.sv\n             obj_dir/Language/Basics,data/full_repos/permissive/498662723\n             obj_dir/Language/Basics,data/full_repos/permissive/498662723.v\n             obj_dir/Language/Basics,data/full_repos/permissive/498662723.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/498662723/Verilog\n%Error: Cannot find file containing module: Language/Basics/xnorgate.v\n%Error: Exiting due to 3 error(s)\n'
module top_module( 
    input a, 
    input b, 
    output out );
	
    assign out = (a&b)+((!a)&(!b));
endmodule
module top_module( 
    input a, 
    input b, 
    output out );

	
    assign out = (a&b)+((!a)&(!b));
endmodule