data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td/knns_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td/knns_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td/knns_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #130;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td/knns_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td/knns_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td/knns_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td/knns_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td/knns_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td/knns_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td/knns_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td/knns_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td/knns_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td/knns_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td/knns_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td/knns_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td/knns_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td/knns_tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td/knns_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td/knns_tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td/knns_tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td/knns_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td/knns_tb.v:122: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td/knns_tb.v:128: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td/knns_tb.v:38: Cannot find file containing module: \'k_nns_seq_td\'\n k_nns_seq_td uut (\n ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td,data/full_repos/permissive/486954482/k_nns_seq_td\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td,data/full_repos/permissive/486954482/k_nns_seq_td.v\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/knns_td,data/full_repos/permissive/486954482/k_nns_seq_td.sv\n             k_nns_seq_td\n             k_nns_seq_td.v\n             k_nns_seq_td.sv\n             obj_dir/k_nns_seq_td\n             obj_dir/k_nns_seq_td.v\n             obj_dir/k_nns_seq_td.sv\n%Error: Exiting due to 1 error(s), 22 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module knns_tb;


	reg clk;
	reg rst;
	reg [31:0] x1;
	reg [31:0] y1;
	reg [31:0] x2;
	reg [31:0] y2;


	wire [639:0] min_val_out;


	k_nns_seq_td uut (
		.clk(clk), 
		.rst(rst), 
		.x1(x1), 
		.y1(y1), 
		.x2(x2), 
		.y2(y2), 
		.min_val_out(min_val_out)
	);

	initial begin

		clk = 0;
		rst = 0;
		x1 = 0;
		y1 = 0;
		x2 = 10;
		y2 = 10;


		#100;
        

		
		rst = 1;
		#130;
		rst = 0;
		#20;
		
		x1 = 10;
		y1 = 5;
		x2 = 10;
		y2 = 4;
		#100;
		x2 = 11;
		y2 = 5;
		#100;
		x2 = 11;
		y2 = 5;
		#100;
		x2 = 18;
		y2 = 5;
		#100;
		x2 = 12;
		y2 = 5;
		#100;
		x2 = 14;
		y2 = 25;
		#100;
		x2 = 15;
		y2 = 25;
		#100;
		x2 = 10;
		y2 = 6;
		#100;
		x2 = 10;
		y2 = 7;
		#100;
		x2 = 10;
		y2 = 18;
		#100;
		x2 = 10;
		y2 = 19;
		#100;
		x2 = 20;
		y2 = 10;
		#100;
		x2 = 10;
		y2 = 7;
		#100;
		x2 = 9;
		y2 = 4;
		#100;
		x2 = 10;
		y2 = 4;
		#100;
		x2 = 25;
		y2 = 10;
		#100;
		x2 = 10;
		y2 = 24;
		#100;
		x2 = 11;
		y2 = 5;
		#100;
		x2 = 19;
		y2 = 5;
	end
	
	always begin
		#50;
		clk = ~clk;
	end
	
	always @ (posedge clk) begin
	end
      
endmodule
module knns_tb;



	reg clk;
	reg rst;
	reg [31:0] x1;
	reg [31:0] y1;
	reg [31:0] x2;
	reg [31:0] y2;


	wire [639:0] min_val_out;


	k_nns_seq_td uut (
		.clk(clk), 
		.rst(rst), 
		.x1(x1), 
		.y1(y1), 
		.x2(x2), 
		.y2(y2), 
		.min_val_out(min_val_out)
	);

	initial begin

		clk = 0;
		rst = 0;
		x1 = 0;
		y1 = 0;
		x2 = 10;
		y2 = 10;


		#100;
        

		
		rst = 1;
		#130;
		rst = 0;
		#20;
		
		x1 = 10;
		y1 = 5;
		x2 = 10;
		y2 = 4;
		#100;
		x2 = 11;
		y2 = 5;
		#100;
		x2 = 11;
		y2 = 5;
		#100;
		x2 = 18;
		y2 = 5;
		#100;
		x2 = 12;
		y2 = 5;
		#100;
		x2 = 14;
		y2 = 25;
		#100;
		x2 = 15;
		y2 = 25;
		#100;
		x2 = 10;
		y2 = 6;
		#100;
		x2 = 10;
		y2 = 7;
		#100;
		x2 = 10;
		y2 = 18;
		#100;
		x2 = 10;
		y2 = 19;
		#100;
		x2 = 20;
		y2 = 10;
		#100;
		x2 = 10;
		y2 = 7;
		#100;
		x2 = 9;
		y2 = 4;
		#100;
		x2 = 10;
		y2 = 4;
		#100;
		x2 = 25;
		y2 = 10;
		#100;
		x2 = 10;
		y2 = 24;
		#100;
		x2 = 11;
		y2 = 5;
		#100;
		x2 = 19;
		y2 = 5;
	end
	
	always begin
		#50;
		clk = ~clk;
	end
	
	always @ (posedge clk) begin
	end
      
endmodule