data/full_repos/permissive/421380819/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/421380819/verilog/rtl/user_proj_example.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421380819/verilog/rtl/user_proj_example.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/421380819/verilog/rtl/user_proj_example.v:67: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module user_proj_example #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,


    output [2:0] irq
);

    wire            GPIO_WE;
    wire   [3:0]    GPIO_ADDR;
    wire   [31:0]   GPIO_DATA_IN;
    wire   [31:0]   GPIO_DATA_OUT;

    wire            WB_RAM_CSb;
    wire            WB_RAM_WEb;
    wire    [7:0]   WB_RAM_ADDR;
    wire    [31:0]  WB_RAM_DATA_IN;
    wire    [31:0]  WB_RAM_DATA_OUT;

    wire            GPIO_RAM_CSb;
    wire            GPIO_RAM_WEb;
    wire    [7:0]   GPIO_RAM_ADDR;
    wire    [31:0]  GPIO_RAM_DATA_IN;
    wire    [31:0]  GPIO_RAM_DATA_OUT;

    wire            RAM_CSb[3:0];
    wire            RAM_WEb[3:0];
    wire    [4:0]   RAM_ADDR[3:0];
    wire    [7:0]   RAM_DATA_IN[3:0];
    wire    [7:0]   RAM_DATA_OUT[3:0];


    assign irq = 3'b000;


    assign la_data_out[0]       = GPIO_WE;
    assign la_data_out[1+:2]    = GPIO_ADDR[3:2];
    assign la_data_out[3+:32]   = GPIO_DATA_IN;
    assign la_data_out[35]      = RAM_CSb[0];
    assign la_data_out[36]      = RAM_WEb[0];
    assign la_data_out[37+:5]   = RAM_ADDR[0];
    assign la_data_out[42+:8]   = RAM_DATA_IN[0];
    assign la_data_out[50+:8]   = RAM_DATA_OUT[0];
    assign la_data_out[58]      = RAM_CSb[0];
    assign la_data_out[59]      = RAM_WEb[0];
    assign la_data_out[60+:5]   = RAM_ADDR[0];
    assign la_data_out[65+:8]   = RAM_DATA_IN[0];
    assign la_data_out[73+:8]  = RAM_DATA_OUT[0];
    assign la_data_out[81]     = RAM_CSb[0];
    assign la_data_out[82]     = RAM_WEb[0];
    assign la_data_out[83+:5]  = RAM_ADDR[0];
    assign la_data_out[88+:8]   = RAM_DATA_IN[0];
    assign la_data_out[96+:8]   = RAM_DATA_OUT[0];
    assign la_data_out[104]      = RAM_CSb[0];
    assign la_data_out[105]      = RAM_WEb[0];
    assign la_data_out[106+:5]   = RAM_ADDR[0];
    assign la_data_out[111+:8]   = RAM_DATA_IN[0];
    assign la_data_out[119+:8]   = RAM_DATA_OUT[0];





    wbSlave wbSlave_inst (

        .CLK_I          (wb_clk_i),
        .RST_I          (wb_rst_i),
        .STB_I          (wbs_stb_i),
        .CYC_I          (wbs_cyc_i),
        .WE_I           (wbs_we_i),
        .SEL_I          (wbs_sel_i),
        .DAT_I          (wbs_dat_i),
        .ADR_I          (wbs_adr_i),
        .ACK_O          (wbs_ack_o),
        .DAT_O          (wbs_dat_o),
        .CTRL_WE        (GPIO_WE),
        .CTRL_ADDR      (GPIO_ADDR),
        .CTRL_DATA_IN   (GPIO_DATA_IN),
        .CTRL_DATA_OUT  (GPIO_DATA_OUT),
        .RAM_CSb        (WB_RAM_CSb),
        .RAM_WEb        (WB_RAM_WEb),
        .RAM_ADDR       (WB_RAM_ADDR),
        .RAM_DATA_IN    (WB_RAM_DATA_IN),
        .RAM_DATA_OUT   (WB_RAM_DATA_OUT)
    );


    gpioCtrl gpioCtrl_inst (

        .CLK            (wb_clk_i), 
        .RSTb           (!wb_rst_i),

        .CTRL_WE        (GPIO_WE),
        .CTRL_ADDR      (GPIO_ADDR),
        .CTRL_DATA_IN   (GPIO_DATA_IN),
        .CTRL_DATA_OUT  (GPIO_DATA_OUT),

        .GPIO_IN        (io_in),
        .GPIO_OUT       (io_out),
        .GPIO_OEb       (io_oeb),

        .RAM_CSb        (GPIO_RAM_CSb),
        .RAM_WEb        (GPIO_RAM_WEb),
        .RAM_ADDR       (GPIO_RAM_ADDR),
        .RAM_DATA_IN    (GPIO_RAM_DATA_IN),
        .RAM_DATA_OUT   (GPIO_RAM_DATA_OUT)
    );


    ramArbiter ramArbiter_inst (

        .CLK            (CLK_I_tb),
        .RSTb           (!RST_I_tb),

        .CTRL_CSb1      (WB_RAM_CSb),
        .CTRL_WEb1      (WB_RAM_WEb),
        .CTRL_ADDR1     (WB_RAM_ADDR),
        .CTRL_DATA_IN1  (WB_RAM_DATA_IN),
        .CTRL_DATA_OUT1 (WB_RAM_DATA_OUT),

        .CTRL_CSb2      (GPIO_RAM_CSb),
        .CTRL_WEb2      (GPIO_RAM_WEb),
        .CTRL_ADDR2     (GPIO_RAM_ADDR),
        .CTRL_DATA_IN2  (GPIO_RAM_DATA_IN),
        .CTRL_DATA_OUT2 (GPIO_RAM_DATA_OUT),

        .RAM_CSb0       (RAM_CSb[0]),
        .RAM_WEb0       (RAM_WEb[0]),
        .RAM_ADDR0      (RAM_ADDR[0]),
        .RAM_DATA_IN0   (RAM_DATA_IN[0]),
        .RAM_DATA_OUT0  (RAM_DATA_OUT[0]),

        .RAM_CSb1       (RAM_CSb[1]),
        .RAM_WEb1       (RAM_WEb[1]),
        .RAM_ADDR1      (RAM_ADDR[1]),
        .RAM_DATA_IN1   (RAM_DATA_IN[1]),
        .RAM_DATA_OUT1  (RAM_DATA_OUT[1]),

        .RAM_CSb2       (RAM_CSb[2]),
        .RAM_WEb2       (RAM_WEb[2]),
        .RAM_ADDR2      (RAM_ADDR[2]),
        .RAM_DATA_IN2   (RAM_DATA_IN[2]),
        .RAM_DATA_OUT2  (RAM_DATA_OUT[2]),

        .RAM_CSb3       (RAM_CSb[3]),
        .RAM_WEb3       (RAM_WEb[3]),
        .RAM_ADDR3      (RAM_ADDR[3]),
        .RAM_DATA_IN3   (RAM_DATA_IN[3]),
        .RAM_DATA_OUT3  (RAM_DATA_OUT[3])
    );


    generate
        genvar vRamByte;
        for (vRamByte=0; vRamByte<4; vRamByte=vRamByte+1) begin
            openRam openRam_inst (
                .CLK        (CLK_I_tb),
                .CSb        (RAM_CSb[vRamByte]),
                .WEb        (RAM_WEb[vRamByte]),
                .ADDR       (RAM_ADDR[vRamByte]),
                .DATA_IN    (RAM_DATA_IN[vRamByte]),
                .DATA_OUT   (RAM_DATA_OUT[vRamByte])
            );
        end
    endgenerate
endmodule
module user_proj_example #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,


    output [2:0] irq
);


    wire            GPIO_WE;
    wire   [3:0]    GPIO_ADDR;
    wire   [31:0]   GPIO_DATA_IN;
    wire   [31:0]   GPIO_DATA_OUT;

    wire            WB_RAM_CSb;
    wire            WB_RAM_WEb;
    wire    [7:0]   WB_RAM_ADDR;
    wire    [31:0]  WB_RAM_DATA_IN;
    wire    [31:0]  WB_RAM_DATA_OUT;

    wire            GPIO_RAM_CSb;
    wire            GPIO_RAM_WEb;
    wire    [7:0]   GPIO_RAM_ADDR;
    wire    [31:0]  GPIO_RAM_DATA_IN;
    wire    [31:0]  GPIO_RAM_DATA_OUT;

    wire            RAM_CSb[3:0];
    wire            RAM_WEb[3:0];
    wire    [4:0]   RAM_ADDR[3:0];
    wire    [7:0]   RAM_DATA_IN[3:0];
    wire    [7:0]   RAM_DATA_OUT[3:0];


    assign irq = 3'b000;


    assign la_data_out[0]       = GPIO_WE;
    assign la_data_out[1+:2]    = GPIO_ADDR[3:2];
    assign la_data_out[3+:32]   = GPIO_DATA_IN;
    assign la_data_out[35]      = RAM_CSb[0];
    assign la_data_out[36]      = RAM_WEb[0];
    assign la_data_out[37+:5]   = RAM_ADDR[0];
    assign la_data_out[42+:8]   = RAM_DATA_IN[0];
    assign la_data_out[50+:8]   = RAM_DATA_OUT[0];
    assign la_data_out[58]      = RAM_CSb[0];
    assign la_data_out[59]      = RAM_WEb[0];
    assign la_data_out[60+:5]   = RAM_ADDR[0];
    assign la_data_out[65+:8]   = RAM_DATA_IN[0];
    assign la_data_out[73+:8]  = RAM_DATA_OUT[0];
    assign la_data_out[81]     = RAM_CSb[0];
    assign la_data_out[82]     = RAM_WEb[0];
    assign la_data_out[83+:5]  = RAM_ADDR[0];
    assign la_data_out[88+:8]   = RAM_DATA_IN[0];
    assign la_data_out[96+:8]   = RAM_DATA_OUT[0];
    assign la_data_out[104]      = RAM_CSb[0];
    assign la_data_out[105]      = RAM_WEb[0];
    assign la_data_out[106+:5]   = RAM_ADDR[0];
    assign la_data_out[111+:8]   = RAM_DATA_IN[0];
    assign la_data_out[119+:8]   = RAM_DATA_OUT[0];





    wbSlave wbSlave_inst (

        .CLK_I          (wb_clk_i),
        .RST_I          (wb_rst_i),
        .STB_I          (wbs_stb_i),
        .CYC_I          (wbs_cyc_i),
        .WE_I           (wbs_we_i),
        .SEL_I          (wbs_sel_i),
        .DAT_I          (wbs_dat_i),
        .ADR_I          (wbs_adr_i),
        .ACK_O          (wbs_ack_o),
        .DAT_O          (wbs_dat_o),
        .CTRL_WE        (GPIO_WE),
        .CTRL_ADDR      (GPIO_ADDR),
        .CTRL_DATA_IN   (GPIO_DATA_IN),
        .CTRL_DATA_OUT  (GPIO_DATA_OUT),
        .RAM_CSb        (WB_RAM_CSb),
        .RAM_WEb        (WB_RAM_WEb),
        .RAM_ADDR       (WB_RAM_ADDR),
        .RAM_DATA_IN    (WB_RAM_DATA_IN),
        .RAM_DATA_OUT   (WB_RAM_DATA_OUT)
    );


    gpioCtrl gpioCtrl_inst (

        .CLK            (wb_clk_i), 
        .RSTb           (!wb_rst_i),

        .CTRL_WE        (GPIO_WE),
        .CTRL_ADDR      (GPIO_ADDR),
        .CTRL_DATA_IN   (GPIO_DATA_IN),
        .CTRL_DATA_OUT  (GPIO_DATA_OUT),

        .GPIO_IN        (io_in),
        .GPIO_OUT       (io_out),
        .GPIO_OEb       (io_oeb),

        .RAM_CSb        (GPIO_RAM_CSb),
        .RAM_WEb        (GPIO_RAM_WEb),
        .RAM_ADDR       (GPIO_RAM_ADDR),
        .RAM_DATA_IN    (GPIO_RAM_DATA_IN),
        .RAM_DATA_OUT   (GPIO_RAM_DATA_OUT)
    );


    ramArbiter ramArbiter_inst (

        .CLK            (CLK_I_tb),
        .RSTb           (!RST_I_tb),

        .CTRL_CSb1      (WB_RAM_CSb),
        .CTRL_WEb1      (WB_RAM_WEb),
        .CTRL_ADDR1     (WB_RAM_ADDR),
        .CTRL_DATA_IN1  (WB_RAM_DATA_IN),
        .CTRL_DATA_OUT1 (WB_RAM_DATA_OUT),

        .CTRL_CSb2      (GPIO_RAM_CSb),
        .CTRL_WEb2      (GPIO_RAM_WEb),
        .CTRL_ADDR2     (GPIO_RAM_ADDR),
        .CTRL_DATA_IN2  (GPIO_RAM_DATA_IN),
        .CTRL_DATA_OUT2 (GPIO_RAM_DATA_OUT),

        .RAM_CSb0       (RAM_CSb[0]),
        .RAM_WEb0       (RAM_WEb[0]),
        .RAM_ADDR0      (RAM_ADDR[0]),
        .RAM_DATA_IN0   (RAM_DATA_IN[0]),
        .RAM_DATA_OUT0  (RAM_DATA_OUT[0]),

        .RAM_CSb1       (RAM_CSb[1]),
        .RAM_WEb1       (RAM_WEb[1]),
        .RAM_ADDR1      (RAM_ADDR[1]),
        .RAM_DATA_IN1   (RAM_DATA_IN[1]),
        .RAM_DATA_OUT1  (RAM_DATA_OUT[1]),

        .RAM_CSb2       (RAM_CSb[2]),
        .RAM_WEb2       (RAM_WEb[2]),
        .RAM_ADDR2      (RAM_ADDR[2]),
        .RAM_DATA_IN2   (RAM_DATA_IN[2]),
        .RAM_DATA_OUT2  (RAM_DATA_OUT[2]),

        .RAM_CSb3       (RAM_CSb[3]),
        .RAM_WEb3       (RAM_WEb[3]),
        .RAM_ADDR3      (RAM_ADDR[3]),
        .RAM_DATA_IN3   (RAM_DATA_IN[3]),
        .RAM_DATA_OUT3  (RAM_DATA_OUT[3])
    );


    generate
        genvar vRamByte;
        for (vRamByte=0; vRamByte<4; vRamByte=vRamByte+1) begin
            openRam openRam_inst (
                .CLK        (CLK_I_tb),
                .CSb        (RAM_CSb[vRamByte]),
                .WEb        (RAM_WEb[vRamByte]),
                .ADDR       (RAM_ADDR[vRamByte]),
                .DATA_IN    (RAM_DATA_IN[vRamByte]),
                .DATA_OUT   (RAM_DATA_OUT[vRamByte])
            );
        end
    endgenerate
endmodule