data/full_repos/permissive/423412549/src/rtl/dff_delay.v
data/verilator_xmls/ccf06ba7-73c4-40cc-8e8c-f2e9eb13d571.xml
module dff_delay #(
        DELAY=2,
        DATA_WIDTH=1
    ) (
        input wire                  clk,
        input wire                  rst,
        input wire                  en_i,
        input wire [DATA_WIDTH-1:0] data_i,

        output reg [DATA_WIDTH-1:0] data_o
    );
    reg [DATA_WIDTH-1:0] data_reg [DELAY-1:0];
    genvar i;

    generate
        for(i=1;i<DELAY;i=i+1) begin:DFF_LOOP
            always @(posedge clk or posedge rst) begin
                if(rst) begin
                    data_reg[i] <= 0;
                end
                else if(en_i) begin
                    data_reg[i] <= data_reg[i-1];
                end
                else begin
                    data_reg[i] <= 0;
                end
            end
        end
    endgenerate

    always @(posedge clk or posedge rst) begin
        if(rst) begin
            data_reg[0] <= 0;
            data_o <= 0;
        end
        else if(en_i) begin
            data_reg[0] <= data_i;
            data_o <= data_reg[DELAY-1];
        end
        else begin
            data_reg[0] <= 0;
            data_o <= 0;
        end
    end

endmodule
module dff_delay #(
        DELAY=2,
        DATA_WIDTH=1
    ) (
        input wire                  clk,
        input wire                  rst,
        input wire                  en_i,
        input wire [DATA_WIDTH-1:0] data_i,

        output reg [DATA_WIDTH-1:0] data_o
    );

    reg [DATA_WIDTH-1:0] data_reg [DELAY-1:0];
    genvar i;

    generate
        for(i=1;i<DELAY;i=i+1) begin:DFF_LOOP
            always @(posedge clk or posedge rst) begin
                if(rst) begin
                    data_reg[i] <= 0;
                end
                else if(en_i) begin
                    data_reg[i] <= data_reg[i-1];
                end
                else begin
                    data_reg[i] <= 0;
                end
            end
        end
    endgenerate

    always @(posedge clk or posedge rst) begin
        if(rst) begin
            data_reg[0] <= 0;
            data_o <= 0;
        end
        else if(en_i) begin
            data_reg[0] <= data_i;
            data_o <= data_reg[DELAY-1];
        end
        else begin
            data_reg[0] <= 0;
            data_o <= 0;
        end
    end

endmodule