data/full_repos/permissive/42434302/ivltests/pr542.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr542.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr542.v:31: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h100\' generates 10 bits.\n                                                                       : ... In instance top\n  pm_next_st = 10\'h100;\n             ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;

parameter[3:0] DAC         = 8;

wire        d_pm_in_dac_st;
reg [10:0]  pm_next_st;

assign d_pm_in_dac_st      = (pm_next_st[DAC]);

initial begin
  pm_next_st = 10'h100;
  #1;
  $display("d_pm_in_dac_st = %0b",d_pm_in_dac_st);
  $display("d_pm_in_dac_st = %0b",pm_next_st[DAC]);
  $finish;
end

endmodule
module top;


parameter[3:0] DAC         = 8;

wire        d_pm_in_dac_st;
reg [10:0]  pm_next_st;

assign d_pm_in_dac_st      = (pm_next_st[DAC]);

initial begin
  pm_next_st = 10'h100;
  #1;
  $display("d_pm_in_dac_st = %0b",d_pm_in_dac_st);
  $display("d_pm_in_dac_st = %0b",pm_next_st[DAC]);
  $finish;
end

endmodule