data/full_repos/permissive/480681467/main/testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/480681467/main/testbench.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #100 \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/480681467/main/testbench.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/480681467/main/testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/480681467/main/testbench.v:25: Unsupported: Ignoring delay on this delayed statement.\n      #1000 reset1 = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/480681467/main/testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset1 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/480681467/main/testbench.v:27: Unsupported: Ignoring delay on this delayed statement.\n      #2980 \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/480681467/main/testbench.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/480681467/main/testbench.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/480681467/main/testbench.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #1000 reset1 = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/480681467/main/testbench.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset1 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/480681467/main/testbench.v:43: Unsupported: Ignoring delay on this delayed statement.\n      #2980\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/480681467/main/testbench.v:47: Unsupported: Ignoring delay on this delayed statement.\n      #2980\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/480681467/main/testbench.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/480681467/main/testbench.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/480681467/main/testbench.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #1000 reset1 = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/480681467/main/testbench.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset1 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/480681467/main/testbench.v:58: Unsupported: Ignoring delay on this delayed statement.\n      #2980\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/480681467/main/testbench.v:63: Unsupported: Ignoring delay on this delayed statement.\n       #1000 reset1 = 1;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/480681467/main/testbench.v:61: Unsupported: Ignoring delay on this delayed statement.\n      #2980\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/480681467/main/testbench.v:64: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset1 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/480681467/main/testbench.v:71: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/480681467/main/testbench.v:72: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/480681467/main/testbench.v:73: Unsupported: Ignoring delay on this delayed statement.\n        #1000 reset1 = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/480681467/main/testbench.v:74: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset1 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/480681467/main/testbench.v:75: Unsupported: Ignoring delay on this delayed statement.\n      #2980\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/480681467/main/testbench.v:82: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk = ~clk;\n           ^\n%Error: data/full_repos/permissive/480681467/main/testbench.v:10: Cannot find file containing module: \'control\'\n    control uut(p,q,clk,reset,reset1,encrypt_decrypt,msg_in,msg_out,mod_exp_finish);\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/480681467/main,data/full_repos/permissive/480681467/control\n             data/full_repos/permissive/480681467/main,data/full_repos/permissive/480681467/control.v\n             data/full_repos/permissive/480681467/main,data/full_repos/permissive/480681467/control.sv\n             control\n             control.v\n             control.sv\n             obj_dir/control\n             obj_dir/control.v\n             obj_dir/control.sv\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/testbench.v:14: Operator ASSIGN expects 256 bits on the Assign RHS, but Assign RHS\'s CONST \'128\'h67646582052b\' generates 128 bits.\n                                                                        : ... In instance tb_main\n        p = 128\'d113680897410347;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/testbench.v:15: Operator ASSIGN expects 256 bits on the Assign RHS, but Assign RHS\'s CONST \'128\'h1b1aba396153c5af549\' generates 128 bits.\n                                                                        : ... In instance tb_main\n        q = 128\'d7999808077935876437321;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/testbench.v:33: Operator ASSIGN expects 256 bits on the Assign RHS, but Assign RHS\'s CONST \'128\'h67646582052b\' generates 128 bits.\n                                                                        : ... In instance tb_main\n        p = 128\'d113680897410347;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/testbench.v:34: Operator ASSIGN expects 256 bits on the Assign RHS, but Assign RHS\'s CONST \'128\'h1b1aba396153c5af549\' generates 128 bits.\n                                                                        : ... In instance tb_main\n        q = 128\'d7999808077935876437321;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/testbench.v:48: Operator ASSIGN expects 256 bits on the Assign RHS, but Assign RHS\'s CONST \'128\'h67646582052b\' generates 128 bits.\n                                                                        : ... In instance tb_main\n        p = 128\'d113680897410347;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/testbench.v:49: Operator ASSIGN expects 256 bits on the Assign RHS, but Assign RHS\'s CONST \'128\'h1b1aba396153c5af549\' generates 128 bits.\n                                                                        : ... In instance tb_main\n        q = 128\'d7999808077935876437321;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/testbench.v:65: Operator ASSIGN expects 256 bits on the Assign RHS, but Assign RHS\'s CONST \'128\'h67646582052b\' generates 128 bits.\n                                                                        : ... In instance tb_main\n        p = 128\'d113680897410347;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/testbench.v:66: Operator ASSIGN expects 256 bits on the Assign RHS, but Assign RHS\'s CONST \'128\'h1b1aba396153c5af549\' generates 128 bits.\n                                                                        : ... In instance tb_main\n        q = 128\'d7999808077935876437321;\n          ^\n%Error: Exiting due to 1 error(s), 34 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_main;
    reg [`WIDTH-1:0] p,q;
    reg clk,reset,reset1,encrypt_decrypt;
    reg [`WIDTH-1:0] msg_in;
    wire [`WIDTH-1:0] msg_out;
    wire mod_exp_finish;
    
    control uut(p,q,clk,reset,reset1,encrypt_decrypt,msg_in,msg_out,mod_exp_finish);
    defparam uut.WIDTH = `WIDTH;
    
    initial begin
        p = 128'd113680897410347;
        q = 128'd7999808077935876437321;
        #100 
        $display("\n\nRSA 256-BIT ENCRYPTION/DECRYPTION TESTER\n");
      $display("\nPrime Numbers Used are:\n1.p=%d\n2.q=%d\n",p,q);
        clk = 0;
        reset =0; reset1=0;
        encrypt_decrypt = 0;
        msg_in = 256'h0000000000000000000000000000000000262d806a3e18f03ab37b2857e7e149;
        #10 reset = 1;
        #10 reset = 0;
      #1000 reset1 = 1;
        #10 reset1 = 0;
      #2980 
      $display("Input Message is \t: %h",msg_in);
      $display("Your decrypted Message is:%h\n", msg_out);
        

      
        p = 128'd113680897410347;
        q = 128'd7999808077935876437321;

        reset =0; reset1=0;
        encrypt_decrypt = 1;
        msg_in = 256'h000000000000000000000000000000000000000048656c6c6f20576f726c6421;
        #10 reset = 1;
        #10 reset = 0;
        #1000 reset1 = 1;
        #10 reset1 = 0;
      #2980
      $display("Input Message is \t: %h",msg_in);
      $display("Your Encrypted Message is:%h\n", msg_out);

      #2980
        p = 128'd113680897410347;
        q = 128'd7999808077935876437321;
        clk = 0;
        reset =0; reset1=0;
        encrypt_decrypt = 0;
        msg_in = 256'h8caea22b8f7a6b9dfa6c57896e0ed7bc;
        #10 reset = 1;
        #10 reset = 0;
        #1000 reset1 = 1;
        #10 reset1 = 0;
      #2980
      $display("Input Message is \t: %h",msg_in);
        $display("Your decrypted Message is:%h\n", msg_out);
      #2980
      
       #1000 reset1 = 1;
        #10 reset1 = 0;
        p = 128'd113680897410347;
        q = 128'd7999808077935876437321;

        reset =0; reset1=0;
        encrypt_decrypt = 1;
        msg_in = 256'h8caea22b8f7a6b9dfa6c57896e0ed7bc;
        #10 reset = 1;
        #10 reset = 0;
        #1000 reset1 = 1;
        #10 reset1 = 0;
      #2980
      $display("Input Message is \t: %h",msg_in);
      $display("Your Encrypted Message is:%h\n", msg_out);
      $finish;
    end

    
    always #5 clk = ~clk;

    
endmodule
module tb_main;

    reg [`WIDTH-1:0] p,q;
    reg clk,reset,reset1,encrypt_decrypt;
    reg [`WIDTH-1:0] msg_in;
    wire [`WIDTH-1:0] msg_out;
    wire mod_exp_finish;
    
    control uut(p,q,clk,reset,reset1,encrypt_decrypt,msg_in,msg_out,mod_exp_finish);
    defparam uut.WIDTH = `WIDTH;
    
    initial begin
        p = 128'd113680897410347;
        q = 128'd7999808077935876437321;
        #100 
        $display("\n\nRSA 256-BIT ENCRYPTION/DECRYPTION TESTER\n");
      $display("\nPrime Numbers Used are:\n1.p=%d\n2.q=%d\n",p,q);
        clk = 0;
        reset =0; reset1=0;
        encrypt_decrypt = 0;
        msg_in = 256'h0000000000000000000000000000000000262d806a3e18f03ab37b2857e7e149;
        #10 reset = 1;
        #10 reset = 0;
      #1000 reset1 = 1;
        #10 reset1 = 0;
      #2980 
      $display("Input Message is \t: %h",msg_in);
      $display("Your decrypted Message is:%h\n", msg_out);
        

      
        p = 128'd113680897410347;
        q = 128'd7999808077935876437321;

        reset =0; reset1=0;
        encrypt_decrypt = 1;
        msg_in = 256'h000000000000000000000000000000000000000048656c6c6f20576f726c6421;
        #10 reset = 1;
        #10 reset = 0;
        #1000 reset1 = 1;
        #10 reset1 = 0;
      #2980
      $display("Input Message is \t: %h",msg_in);
      $display("Your Encrypted Message is:%h\n", msg_out);

      #2980
        p = 128'd113680897410347;
        q = 128'd7999808077935876437321;
        clk = 0;
        reset =0; reset1=0;
        encrypt_decrypt = 0;
        msg_in = 256'h8caea22b8f7a6b9dfa6c57896e0ed7bc;
        #10 reset = 1;
        #10 reset = 0;
        #1000 reset1 = 1;
        #10 reset1 = 0;
      #2980
      $display("Input Message is \t: %h",msg_in);
        $display("Your decrypted Message is:%h\n", msg_out);
      #2980
      
       #1000 reset1 = 1;
        #10 reset1 = 0;
        p = 128'd113680897410347;
        q = 128'd7999808077935876437321;

        reset =0; reset1=0;
        encrypt_decrypt = 1;
        msg_in = 256'h8caea22b8f7a6b9dfa6c57896e0ed7bc;
        #10 reset = 1;
        #10 reset = 0;
        #1000 reset1 = 1;
        #10 reset1 = 0;
      #2980
      $display("Input Message is \t: %h",msg_in);
      $display("Your Encrypted Message is:%h\n", msg_out);
      $finish;
    end

    
    always #5 clk = ~clk;

    
endmodule