data/full_repos/permissive/528677531/LAB-1/Q2/q2b_tb.v
1: b'%Error: data/full_repos/permissive/528677531/LAB-1/Q2/q2b_tb.v:2: Cannot find include file: q2b.v\n`include "q2b.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/528677531/LAB-1/Q2,data/full_repos/permissive/528677531/q2b.v\n             data/full_repos/permissive/528677531/LAB-1/Q2,data/full_repos/permissive/528677531/q2b.v.v\n             data/full_repos/permissive/528677531/LAB-1/Q2,data/full_repos/permissive/528677531/q2b.v.sv\n             q2b.v\n             q2b.v.v\n             q2b.v.sv\n             obj_dir/q2b.v\n             obj_dir/q2b.v.v\n             obj_dir/q2b.v.sv\n%Error: data/full_repos/permissive/528677531/LAB-1/Q2/q2b_tb.v:12: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("q2b_tb.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/528677531/LAB-1/Q2/q2b_tb.v:13: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0,q2b_tb);\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-1/Q2/q2b_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\na=1\'b0; b=1\'b0; c=1\'b0; d=1\'b0; #20;\n                                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-1/Q2/q2b_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\na=1\'b0; b=1\'b0; c=1\'b0; d=1\'b1; #20;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-1/Q2/q2b_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\na=1\'b0; b=1\'b0; c=1\'b1; d=1\'b0; #20;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-1/Q2/q2b_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\na=1\'b0; b=1\'b0; c=1\'b1; d=1\'b1; #20;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-1/Q2/q2b_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\na=1\'b0; b=1\'b1; c=1\'b0; d=1\'b0; #20;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-1/Q2/q2b_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\na=1\'b0; b=1\'b1; c=1\'b0; d=1\'b1; #20;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-1/Q2/q2b_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\na=1\'b0; b=1\'b1; c=1\'b1; d=1\'b0; #20;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-1/Q2/q2b_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\na=1\'b0; b=1\'b1; c=1\'b1; d=1\'b1; #20;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-1/Q2/q2b_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\na=1\'b1; b=1\'b0; c=1\'b0; d=1\'b0; #20;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-1/Q2/q2b_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\na=1\'b1; b=1\'b0; c=1\'b0; d=1\'b1; #20;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-1/Q2/q2b_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\na=1\'b1; b=1\'b0; c=1\'b1; d=1\'b0; #20;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-1/Q2/q2b_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\na=1\'b1; b=1\'b0; c=1\'b1; d=1\'b1; #20;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-1/Q2/q2b_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\na=1\'b1; b=1\'b1; c=1\'b0; d=1\'b0; #20;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-1/Q2/q2b_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\na=1\'b1; b=1\'b1; c=1\'b0; d=1\'b1; #20;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-1/Q2/q2b_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\na=1\'b1; b=1\'b1; c=1\'b1; d=1\'b0; #20;\n                                ^\n%Warning-STMTDLY: data/full_repos/permissive/528677531/LAB-1/Q2/q2b_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\na=1\'b1; b=1\'b1; c=1\'b1; d=1\'b1; #20;\n                                ^\n%Error: Exiting due to 3 error(s), 16 warning(s)\n'
module q2b_tb();
reg a,b,c,d;
wire f,g;

q2b q2b(a,b,c,d,f,g);
initial
begin

$dumpfile("q2b_tb.vcd");
$dumpvars(0,q2b_tb);

a=1'b0; b=1'b0; c=1'b0; d=1'b0; #20;
a=1'b0; b=1'b0; c=1'b0; d=1'b1; #20;
a=1'b0; b=1'b0; c=1'b1; d=1'b0; #20;
a=1'b0; b=1'b0; c=1'b1; d=1'b1; #20;
a=1'b0; b=1'b1; c=1'b0; d=1'b0; #20;
a=1'b0; b=1'b1; c=1'b0; d=1'b1; #20;
a=1'b0; b=1'b1; c=1'b1; d=1'b0; #20;
a=1'b0; b=1'b1; c=1'b1; d=1'b1; #20;
a=1'b1; b=1'b0; c=1'b0; d=1'b0; #20;
a=1'b1; b=1'b0; c=1'b0; d=1'b1; #20;
a=1'b1; b=1'b0; c=1'b1; d=1'b0; #20;
a=1'b1; b=1'b0; c=1'b1; d=1'b1; #20;
a=1'b1; b=1'b1; c=1'b0; d=1'b0; #20;
a=1'b1; b=1'b1; c=1'b0; d=1'b1; #20;
a=1'b1; b=1'b1; c=1'b1; d=1'b0; #20;
a=1'b1; b=1'b1; c=1'b1; d=1'b1; #20;

$display("Test Complete");

end

endmodule
module q2b_tb();

reg a,b,c,d;
wire f,g;

q2b q2b(a,b,c,d,f,g);
initial
begin

$dumpfile("q2b_tb.vcd");
$dumpvars(0,q2b_tb);

a=1'b0; b=1'b0; c=1'b0; d=1'b0; #20;
a=1'b0; b=1'b0; c=1'b0; d=1'b1; #20;
a=1'b0; b=1'b0; c=1'b1; d=1'b0; #20;
a=1'b0; b=1'b0; c=1'b1; d=1'b1; #20;
a=1'b0; b=1'b1; c=1'b0; d=1'b0; #20;
a=1'b0; b=1'b1; c=1'b0; d=1'b1; #20;
a=1'b0; b=1'b1; c=1'b1; d=1'b0; #20;
a=1'b0; b=1'b1; c=1'b1; d=1'b1; #20;
a=1'b1; b=1'b0; c=1'b0; d=1'b0; #20;
a=1'b1; b=1'b0; c=1'b0; d=1'b1; #20;
a=1'b1; b=1'b0; c=1'b1; d=1'b0; #20;
a=1'b1; b=1'b0; c=1'b1; d=1'b1; #20;
a=1'b1; b=1'b1; c=1'b0; d=1'b0; #20;
a=1'b1; b=1'b1; c=1'b0; d=1'b1; #20;
a=1'b1; b=1'b1; c=1'b1; d=1'b0; #20;
a=1'b1; b=1'b1; c=1'b1; d=1'b1; #20;

$display("Test Complete");

end

endmodule