data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ippcsge/core/ippcsge_core.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ippcsge/core/ippcsge_core.v:544: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n     .do    (ram_rdat)\n      ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ippcsge/core/ippcsge_core.v:544: syntax error, unexpected '(', expecting ')'\n     .do    (ram_rdat)\n             ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module ippcsge_elasticfifo
    (

     inclk,
     inrst_,
     
     indata,
     invld,


     outclk,
     outrst_,
     
     outdata,
     outvld,





     wrerr,
     rderr,

     upact,
     upflush,
     upthsh
     );



parameter DATD = 9;
parameter RAMA = 4,
          RAML = 16,
          RAMD = DATD+1;




input               inclk;
input               inrst_;


input [DATD-1:0]    indata;
input               invld;



input               outclk;
input               outrst_;

output [DATD-1:0]   outdata;
output              outvld;



     

output              wrerr;
output              rderr;


input               upact;
input               upflush;
input [RAMA-1:0]    upthsh;







wire [RAMA:0]       wrpnt_gray;
wire [RAMA:0]       rdpnt_gray;


wire   [RAMD-1:0]   ram_wdat;
wire                ram_wena;
wire   [RAMA-1:0]   ram_wadd;

wire  [RAMD-1:0]    ram_rdat;
wire                ram_rena;
wire   [RAMA-1:0]   ram_radd;


iarray111x #(RAMA, RAML, RAMD) iram
    (  
     .test  (1'b0),
     .mask  (1'b0),
     .wrst_ (inrst_),
     .wclk  (inclk),
     .wa    (ram_wadd),
     .we    (ram_wena),
     .di    (ram_wdat),
     .rclk  (outclk),
     .rrst_ (outrst_),
     .re    (ram_rena),
     .ra    (ram_radd),
     .do    (ram_rdat)
     );



wire                fifowr;
wire                fifofull;
wire [RAMA:0]       wrfifolen;


convclk_grayffwr #(RAMA) igrayffwr
    (
     .wrclk         (inclk),
     .wrrst_        (inrst_),

     .fifowr        (fifowr),
     .fifoflush     (upflush),
     .fifofull      (fifofull),
     .half_full     (),
     .wrfifolen     (wrfifolen),
     .wrpnt_gray    (wrpnt_gray),
     
     .write         (ram_wena),
     .wraddr        (ram_wadd),


     .rdpnt_gray    (rdpnt_gray)
     );

wire                invld1;

fflopx #(1) ffinvld1 (inclk, inrst_, invld, invld1);

assign              fifowr = (invld | invld1) & upact;

assign              ram_wdat = {invld, indata};



wire                fiford;
wire                fifonemp;
wire [RAMA:0]       rdfifolen;

convclk_grayffrd #(RAMA) igrayffrd
    (
     .rdclk         (outclk),
     .rdrst_        (outrst_),

     .fiford        (fiford),
     .fifoflush     (upflush),
     .fifonemp      (fifonemp),
     .rdfifolen     (rdfifolen),
     .rdpnt_gray    (rdpnt_gray),
     
     .rdaddr        (ram_radd),
     .read          (ram_rena),


     .wrpnt_gray    (wrpnt_gray)
     );


wire                statenew;
assign              statenew = (rdfifolen >= {1'b0, upthsh});


reg                 staterd;
wire                endrd;

always @(posedge outclk or negedge outrst_)
    begin
    if (~outrst_)       staterd <= 1'b0;
    else if (~upact)    staterd <= 1'b0;
    else if (upflush)   staterd <= 1'b0;
    else if (endrd)     staterd <= 1'b0;
    else if (statenew)  staterd <= 1'b1;
    end

wire                fifonemp1;

fflopx #(1) fffifonemp (outclk, outrst_, fifonemp, fifonemp1);

assign fiford = (((~staterd) & statenew)    |
                 ((staterd) & (~endrd))     ) & (fifonemp1 & fifonemp);


wire                ram_rena1;

fflopx #(1) fframrena (outclk, outrst_, ram_rena, ram_rena1);

assign              endrd = ram_rena1 & (~ram_rdat [RAMD-1]);

reg [DATD-1:0]      outdata;
reg                 outvld;

always @(posedge outclk or negedge outrst_)
    begin
    if (~outrst_)
        begin
        outdata     <= {DATD{1'b0}};
        outvld      <= 1'b0;
        end
    else if (~upact | upflush)
        begin
        outdata     <= {DATD{1'b0}};
        outvld      <= 1'b0;
        end
    else if (ram_rena1)
        begin
        outdata     <= ram_rdat [DATD-1:0];
        outvld      <= ram_rdat [RAMD-1];
        end
    else
        begin
        outdata     <= {DATD{1'b0}};
        outvld      <= 1'b0;
        end
    end



wire        werr;
wire        rerr;
assign      werr = fifowr & fifofull;
assign      rerr = staterd & (~fifonemp1);

wire        werr1;
wire        rerr1;

fflopx #(2) ffrderr (outclk, outrst_, {rerr,  (rerr1 | rerr)},
                     {rerr1, rderr});
                     
fflopx #(2) ffwrerr (inclk, inrst_, {werr,  (werr1 | werr)},
                     {werr1, wrerr});



endmodule
module ippcsge_elasticfifo
    (

     inclk,
     inrst_,
     
     indata,
     invld,


     outclk,
     outrst_,
     
     outdata,
     outvld,





     wrerr,
     rderr,

     upact,
     upflush,
     upthsh
     );




parameter DATD = 9;
parameter RAMA = 4,
          RAML = 16,
          RAMD = DATD+1;




input               inclk;
input               inrst_;


input [DATD-1:0]    indata;
input               invld;



input               outclk;
input               outrst_;

output [DATD-1:0]   outdata;
output              outvld;



     

output              wrerr;
output              rderr;


input               upact;
input               upflush;
input [RAMA-1:0]    upthsh;







wire [RAMA:0]       wrpnt_gray;
wire [RAMA:0]       rdpnt_gray;


wire   [RAMD-1:0]   ram_wdat;
wire                ram_wena;
wire   [RAMA-1:0]   ram_wadd;

wire  [RAMD-1:0]    ram_rdat;
wire                ram_rena;
wire   [RAMA-1:0]   ram_radd;


iarray111x #(RAMA, RAML, RAMD) iram
    (  
     .test  (1'b0),
     .mask  (1'b0),
     .wrst_ (inrst_),
     .wclk  (inclk),
     .wa    (ram_wadd),
     .we    (ram_wena),
     .di    (ram_wdat),
     .rclk  (outclk),
     .rrst_ (outrst_),
     .re    (ram_rena),
     .ra    (ram_radd),
     .do    (ram_rdat)
     );



wire                fifowr;
wire                fifofull;
wire [RAMA:0]       wrfifolen;


convclk_grayffwr #(RAMA) igrayffwr
    (
     .wrclk         (inclk),
     .wrrst_        (inrst_),

     .fifowr        (fifowr),
     .fifoflush     (upflush),
     .fifofull      (fifofull),
     .half_full     (),
     .wrfifolen     (wrfifolen),
     .wrpnt_gray    (wrpnt_gray),
     
     .write         (ram_wena),
     .wraddr        (ram_wadd),


     .rdpnt_gray    (rdpnt_gray)
     );

wire                invld1;

fflopx #(1) ffinvld1 (inclk, inrst_, invld, invld1);

assign              fifowr = (invld | invld1) & upact;

assign              ram_wdat = {invld, indata};



wire                fiford;
wire                fifonemp;
wire [RAMA:0]       rdfifolen;

convclk_grayffrd #(RAMA) igrayffrd
    (
     .rdclk         (outclk),
     .rdrst_        (outrst_),

     .fiford        (fiford),
     .fifoflush     (upflush),
     .fifonemp      (fifonemp),
     .rdfifolen     (rdfifolen),
     .rdpnt_gray    (rdpnt_gray),
     
     .rdaddr        (ram_radd),
     .read          (ram_rena),


     .wrpnt_gray    (wrpnt_gray)
     );


wire                statenew;
assign              statenew = (rdfifolen >= {1'b0, upthsh});


reg                 staterd;
wire                endrd;

always @(posedge outclk or negedge outrst_)
    begin
    if (~outrst_)       staterd <= 1'b0;
    else if (~upact)    staterd <= 1'b0;
    else if (upflush)   staterd <= 1'b0;
    else if (endrd)     staterd <= 1'b0;
    else if (statenew)  staterd <= 1'b1;
    end

wire                fifonemp1;

fflopx #(1) fffifonemp (outclk, outrst_, fifonemp, fifonemp1);

assign fiford = (((~staterd) & statenew)    |
                 ((staterd) & (~endrd))     ) & (fifonemp1 & fifonemp);


wire                ram_rena1;

fflopx #(1) fframrena (outclk, outrst_, ram_rena, ram_rena1);

assign              endrd = ram_rena1 & (~ram_rdat [RAMD-1]);

reg [DATD-1:0]      outdata;
reg                 outvld;

always @(posedge outclk or negedge outrst_)
    begin
    if (~outrst_)
        begin
        outdata     <= {DATD{1'b0}};
        outvld      <= 1'b0;
        end
    else if (~upact | upflush)
        begin
        outdata     <= {DATD{1'b0}};
        outvld      <= 1'b0;
        end
    else if (ram_rena1)
        begin
        outdata     <= ram_rdat [DATD-1:0];
        outvld      <= ram_rdat [RAMD-1];
        end
    else
        begin
        outdata     <= {DATD{1'b0}};
        outvld      <= 1'b0;
        end
    end



wire        werr;
wire        rerr;
assign      werr = fifowr & fifofull;
assign      rerr = staterd & (~fifonemp1);

wire        werr1;
wire        rerr1;

fflopx #(2) ffrderr (outclk, outrst_, {rerr,  (rerr1 | rerr)},
                     {rerr1, rderr});
                     
fflopx #(2) ffwrerr (inclk, inrst_, {werr,  (werr1 | werr)},
                     {werr1, wrerr});



endmodule