data/full_repos/permissive/420117502/Basic/6_FSM/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/6_FSM/tb.v:7: Unsupported: Ignoring delay on this delayed statement.\nalways #(10/2) clk<=~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/420117502/Basic/6_FSM/tb.v:20: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("./dumpfile.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/420117502/Basic/6_FSM/tb.v:21: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/6_FSM/tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #10\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/6_FSM/tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_i<=\'haa;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/6_FSM/tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #(10 + 1 )\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/6_FSM/tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_i<=\'hbb;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/6_FSM/tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_i<=\'hcc;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/6_FSM/tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_i<=\'hbb;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/6_FSM/tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_i<=\'haa;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/6_FSM/tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_i<=\'hbb;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/6_FSM/tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_i<=\'hcc;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/6_FSM/tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_i<=\'haa;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/6_FSM/tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_i<=\'hbb;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/6_FSM/tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_i<=\'haa;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/6_FSM/tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_i<=\'hbb;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/6_FSM/tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_i<=\'hcc;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/6_FSM/tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #10 data_i<=\'hcc;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/6_FSM/tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #(10 * 4)\n    ^\n%Error: Exiting due to 2 error(s), 17 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();

reg clk;
reg rst_n;
always #(`CLOCK_PERIOD/2) clk<=~clk;

reg [7:0] data_i;
wire flag;

FSM_Mealy fsm(
    .clk  (clk      ),
    .rst_n(rst_n    ),
    .data (data_i   ),
    .flag (flag     )
);

initial begin
    $dumpfile("./dumpfile.vcd");
    $dumpvars;
    clk<=1'b1;
    rst_n<=1'b0;
    data_i<='hff;
    #`CLOCK_PERIOD
    rst_n<=1'b1;
    #(`CLOCK_PERIOD + 1 )
    #`CLOCK_PERIOD data_i<='haa;
    #`CLOCK_PERIOD data_i<='hbb;
    #`CLOCK_PERIOD data_i<='hcc;
    #`CLOCK_PERIOD data_i<='hbb;
    #`CLOCK_PERIOD data_i<='haa;
    #`CLOCK_PERIOD data_i<='hbb;
    #`CLOCK_PERIOD data_i<='hcc;
    #`CLOCK_PERIOD data_i<='haa;
    #`CLOCK_PERIOD data_i<='hbb;
    #`CLOCK_PERIOD data_i<='haa;
    #`CLOCK_PERIOD data_i<='hbb;
    #`CLOCK_PERIOD data_i<='hcc;
    #`CLOCK_PERIOD data_i<='hcc;
    #(`CLOCK_PERIOD * 4)
    $finish;
end

endmodule
module tb();


reg clk;
reg rst_n;
always #(`CLOCK_PERIOD/2) clk<=~clk;

reg [7:0] data_i;
wire flag;

FSM_Mealy fsm(
    .clk  (clk      ),
    .rst_n(rst_n    ),
    .data (data_i   ),
    .flag (flag     )
);

initial begin
    $dumpfile("./dumpfile.vcd");
    $dumpvars;
    clk<=1'b1;
    rst_n<=1'b0;
    data_i<='hff;
    #`CLOCK_PERIOD
    rst_n<=1'b1;
    #(`CLOCK_PERIOD + 1 )
    #`CLOCK_PERIOD data_i<='haa;
    #`CLOCK_PERIOD data_i<='hbb;
    #`CLOCK_PERIOD data_i<='hcc;
    #`CLOCK_PERIOD data_i<='hbb;
    #`CLOCK_PERIOD data_i<='haa;
    #`CLOCK_PERIOD data_i<='hbb;
    #`CLOCK_PERIOD data_i<='hcc;
    #`CLOCK_PERIOD data_i<='haa;
    #`CLOCK_PERIOD data_i<='hbb;
    #`CLOCK_PERIOD data_i<='haa;
    #`CLOCK_PERIOD data_i<='hbb;
    #`CLOCK_PERIOD data_i<='hcc;
    #`CLOCK_PERIOD data_i<='hcc;
    #(`CLOCK_PERIOD * 4)
    $finish;
end

endmodule