data/full_repos/permissive/479094658/RCA4_testbench.v
1: b'%Error: data/full_repos/permissive/479094658/RCA4_testbench.v:14: Unsupported or unknown PLI call: $monitor\n    $monitor($time, " A=%b, B=%b, Cin=%b, S=%b, Cout=%b", A, B, Cin, S, Cout);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/479094658/RCA4_testbench.v:19: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(1, RCA4_testbench);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/479094658/RCA4_testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #0  Cin=0; A=0; B=0;  \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/479094658/RCA4_testbench.v:23: Unsupported: Ignoring delay on this delayed statement.\n      #50 A <= A + 1; B <= B + 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/479094658/RCA4_testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #50  Cin=1; A=0; B=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/479094658/RCA4_testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n      #50 A <= A + 1; B <= B + 1;\n      ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module RCA4_testbench();
  
  reg [3:0] A, B;
  reg Cin;
  wire [3:0] S;
  wire Cout;
  
  RCA4 DUT ( .A(A), .B(B), .Cin(Cin), .S(S), .Cout(Cout));
  
  initial
  begin
    $monitor($time, " A=%b, B=%b, Cin=%b, S=%b, Cout=%b", A, B, Cin, S, Cout);
  end
  
  initial
  begin
    $dumpvars(1, RCA4_testbench);
    #0  Cin=0; A=0; B=0;
    repeat (15)
    begin
      #50 A <= A + 1; B <= B + 1;
    end
    
    #50  Cin=1; A=0; B=0;
    
    repeat (15)
    begin
      #50 A <= A + 1; B <= B + 1;
    end
  end
  
endmodule
module RCA4_testbench();

  
  reg [3:0] A, B;
  reg Cin;
  wire [3:0] S;
  wire Cout;
  
  RCA4 DUT ( .A(A), .B(B), .Cin(Cin), .S(S), .Cout(Cout));
  
  initial
  begin
    $monitor($time, " A=%b, B=%b, Cin=%b, S=%b, Cout=%b", A, B, Cin, S, Cout);
  end
  
  initial
  begin
    $dumpvars(1, RCA4_testbench);
    #0  Cin=0; A=0; B=0;
    repeat (15)
    begin
      #50 A <= A + 1; B <= B + 1;
    end
    
    #50  Cin=1; A=0; B=0;
    
    repeat (15)
    begin
      #50 A <= A + 1; B <= B + 1;
    end
  end
  
endmodule