data/full_repos/permissive/449370139/verilog_code/VGAtest_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/449370139/verilog_code/VGAtest_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n           #10\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/449370139/verilog_code/VGAtest_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n       #10\n       ^\n%Error: data/full_repos/permissive/449370139/verilog_code/VGAtest_tb.v:31: Cannot find file containing module: \'vga_driver\'\nvga_driver vga(.I_clk(I_clk),.I_rst_n(I_rst_n),.O_red(O_red),.O_green(O_green),.O_blue(O_blue),.O_hs(O_hs),.O_vs(O_vs));\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/449370139/verilog_code,data/full_repos/permissive/449370139/vga_driver\n             data/full_repos/permissive/449370139/verilog_code,data/full_repos/permissive/449370139/vga_driver.v\n             data/full_repos/permissive/449370139/verilog_code,data/full_repos/permissive/449370139/vga_driver.sv\n             vga_driver\n             vga_driver.v\n             vga_driver.sv\n             obj_dir/vga_driver\n             obj_dir/vga_driver.v\n             obj_dir/vga_driver.sv\n%Warning-WIDTH: data/full_repos/permissive/449370139/verilog_code/VGAtest_tb.v:37: Operator LT expects 32 or 24 bits on the LHS, but LHS\'s VARREF \'invect\' generates 8 bits.\n                                                                                 : ... In instance VGAtest_tb\n       for (invect = 0; invect < 9999999; invect = invect + 1)\n                               ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module VGAtest_tb;
    reg I_clk;
    reg I_rst_n;
    wire [3:0] O_red;
    wire [3:0] O_green;
    wire [3:0] O_blue;      
    wire O_hs;
    wire O_vs;
    reg [7:0] invect;
vga_driver vga(.I_clk(I_clk),.I_rst_n(I_rst_n),.O_red(O_red),.O_green(O_green),.O_blue(O_blue),.O_hs(O_hs),.O_vs(O_vs));
initial
begin
       I_clk<=1'b1;
       I_rst_n=1'b0;
       #10
       for (invect = 0; invect < 9999999; invect = invect + 1)
           begin  
           I_rst_n=1'b1;
           #10
           I_clk<=~I_clk;
           end
end   
endmodule
module VGAtest_tb;

    reg I_clk;
    reg I_rst_n;
    wire [3:0] O_red;
    wire [3:0] O_green;
    wire [3:0] O_blue;      
    wire O_hs;
    wire O_vs;
    reg [7:0] invect;
vga_driver vga(.I_clk(I_clk),.I_rst_n(I_rst_n),.O_red(O_red),.O_green(O_green),.O_blue(O_blue),.O_hs(O_hs),.O_vs(O_vs));
initial
begin
       I_clk<=1'b1;
       I_rst_n=1'b0;
       #10
       for (invect = 0; invect < 9999999; invect = invect + 1)
           begin  
           I_rst_n=1'b1;
           #10
           I_clk<=~I_clk;
           end
end   
endmodule