data/full_repos/permissive/481307378/source_files/ProgramCounter/pc.v
data/verilator_xmls/6a2cd00b-ed12-4e84-96e7-cb8ef9374d42.xml
module pc(
    input CLK,
    input RES,
    input ENABLE,
    input MODE,
    input [31 : 0] D,
    
    output reg [31 : 0] PC_OUT
);

    always @(posedge CLK)
    begin
        if(RES == 1'b1) begin
            PC_OUT <= 32'h1A00_0000;
        end

        else if((ENABLE == 1'b1) && (MODE == 1'b0)) begin
            PC_OUT <= PC_OUT + 32'd4;
        end
        
        else if((ENABLE == 1'b1) && (MODE == 1'b1)) begin
            PC_OUT <= D;
        end
    end 
    
endmodule
module pc(
    input CLK,
    input RES,
    input ENABLE,
    input MODE,
    input [31 : 0] D,
    
    output reg [31 : 0] PC_OUT
);


    always @(posedge CLK)
    begin
        if(RES == 1'b1) begin
            PC_OUT <= 32'h1A00_0000;
        end

        else if((ENABLE == 1'b1) && (MODE == 1'b0)) begin
            PC_OUT <= PC_OUT + 32'd4;
        end
        
        else if((ENABLE == 1'b1) && (MODE == 1'b1)) begin
            PC_OUT <= D;
        end
    end 
    
endmodule