data/full_repos/permissive/468066752/rtl/DataMemory.sv
1: b'%Warning-UNSIGNED: data/full_repos/permissive/468066752/rtl/DataMemory.sv:15: Comparison is constant due to unsigned arithmetic\n                                                                            : ... In instance DataMemory\n    if (RDSTB == 1\'b1 && ADDR >= BASEADDRESS && ADDR < (BASEADDRESS + DMSIZE)) begin\n                              ^~\n                   ... Use "/* verilator lint_off UNSIGNED */" and lint_on around source to disable this message.\n%Warning-UNSIGNED: data/full_repos/permissive/468066752/rtl/DataMemory.sv:21: Comparison is constant due to unsigned arithmetic\n                                                                            : ... In instance DataMemory\n    if (WRSTB == 1\'b1 && ADDR >= BASEADDRESS && ADDR < (BASEADDRESS + DMSIZE)) begin\n                              ^~\n%Error: Exiting due to 2 warning(s)\n'
module DataMemory #(
    parameter int DMSIZE=1024,
    parameter int BASEADDRESS = 32'h0000_0000
) (

    input  logic ACLK,
    input  logic RDSTB,
    input  logic WRSTB,
    input  logic [31:0] ADDR,
    input  logic [31:0] DATA_I,
    output logic [31:0] DATA_O
);
  logic [31:0] mem[0:DMSIZE-1];
  always_ff @(posedge ACLK) begin
    if (RDSTB == 1'b1 && ADDR >= BASEADDRESS && ADDR < (BASEADDRESS + DMSIZE)) begin
      DATA_O <= mem[ADDR];
    end
    else begin
      DATA_O <= 32'dz;
    end
    if (WRSTB == 1'b1 && ADDR >= BASEADDRESS && ADDR < (BASEADDRESS + DMSIZE)) begin
      mem[ADDR] <= DATA_I;
    end
  end
endmodule
module DataMemory #(
    parameter int DMSIZE=1024,
    parameter int BASEADDRESS = 32'h0000_0000
) (

    input  logic ACLK,
    input  logic RDSTB,
    input  logic WRSTB,
    input  logic [31:0] ADDR,
    input  logic [31:0] DATA_I,
    output logic [31:0] DATA_O
);

  logic [31:0] mem[0:DMSIZE-1];
  always_ff @(posedge ACLK) begin
    if (RDSTB == 1'b1 && ADDR >= BASEADDRESS && ADDR < (BASEADDRESS + DMSIZE)) begin
      DATA_O <= mem[ADDR];
    end
    else begin
      DATA_O <= 32'dz;
    end
    if (WRSTB == 1'b1 && ADDR >= BASEADDRESS && ADDR < (BASEADDRESS + DMSIZE)) begin
      mem[ADDR] <= DATA_I;
    end
  end
endmodule