data/full_repos/permissive/500128826/HDLBits/Circuits/Building Larger Circuits/review2015_fsmshift/top_module_tb.v
1: b'%Error: Cannot find file containing module: Larger\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Building/Larger\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Building/Larger.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Building/Larger.sv\n             Larger\n             Larger.v\n             Larger.sv\n             obj_dir/Larger\n             obj_dir/Larger.v\n             obj_dir/Larger.sv\n%Error: Cannot find file containing module: Circuits/review2015_fsmshift,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Building\n%Error: Cannot find file containing module: Circuits/review2015_fsmshift/top_module_tb.v\n%Error: Exiting due to 4 error(s)\n'
module top_module_tb ();
  reg  clk = 1'd1;
  reg  reset = 1'd1;
  wire shift_ena;

  localparam ITERATIONS = 100;

  always begin
    #5 clk = clk + 1;
  end

  always begin
    #1;
    #10 reset = 1'b0;
    #9;
  end

  top_module uut (
      .clk(clk),
      .reset(reset),
      .shift_ena(shift_ena)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule
module top_module_tb ();

  reg  clk = 1'd1;
  reg  reset = 1'd1;
  wire shift_ena;

  localparam ITERATIONS = 100;

  always begin
    #5 clk = clk + 1;
  end

  always begin
    #1;
    #10 reset = 1'b0;
    #9;
  end

  top_module uut (
      .clk(clk),
      .reset(reset),
      .shift_ena(shift_ena)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule