data/full_repos/permissive/500326609/a5/control.v
data/verilator_xmls/b022bc63-4f4e-4c51-bb8d-25ce44ef3979.xml
module control (
    input [31:0] idata,
    output  memread,
    output  mem2reg,
    output  [5:0] ALUop,
    output alusrc,
    output regwrite,
    output [3:0] memwrite
);


wire [6:0] opcode;
wire [2:0] funct3;
assign funct3 = idata[14:12];
assign opcode = idata[6:0];


assign regwrite = (opcode == 7'b0000011 || opcode == 7'b0010011 || opcode == 7'b0110011 );

assign memwrite = (opcode == 7'b0100011 && funct3 == 3'b010) ? 4'b1111 :
                  (opcode == 7'b0100011 && funct3 == 3'b001) ? 4'b0011 :
                  (opcode == 7'b0100011 && funct3 == 3'b000) ? 4'b0001 : 4'b0000;


assign mem2reg = (opcode == 7'b0000011);

assign memread = (opcode == 7'b0000011);

assign alusrc = (opcode == 7'b0010011) ;

assign ALUop = {1'b0,idata[5],idata[14:12],idata[30]};

endmodule
module control (
    input [31:0] idata,
    output  memread,
    output  mem2reg,
    output  [5:0] ALUop,
    output alusrc,
    output regwrite,
    output [3:0] memwrite
);



wire [6:0] opcode;
wire [2:0] funct3;
assign funct3 = idata[14:12];
assign opcode = idata[6:0];


assign regwrite = (opcode == 7'b0000011 || opcode == 7'b0010011 || opcode == 7'b0110011 );

assign memwrite = (opcode == 7'b0100011 && funct3 == 3'b010) ? 4'b1111 :
                  (opcode == 7'b0100011 && funct3 == 3'b001) ? 4'b0011 :
                  (opcode == 7'b0100011 && funct3 == 3'b000) ? 4'b0001 : 4'b0000;


assign mem2reg = (opcode == 7'b0000011);

assign memread = (opcode == 7'b0000011);

assign alusrc = (opcode == 7'b0010011) ;

assign ALUop = {1'b0,idata[5],idata[14:12],idata[30]};

endmodule