data/full_repos/permissive/43856783/j1_soc/hdl/Position/div_64.v
1: b"%Error: data/full_repos/permissive/43856783/j1_soc/hdl/Position/div_64.v:21: Cannot find file containing module: 'lsr_div'\n  lsr_div lsr_d ( .clk(clk) , .rst(0), .DV_in(A), .Result(Result_Sub), .INIT(INIT), .SH(SH), .LDA(LDA), .A(Reg_A) );\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43856783/j1_soc/hdl/Position,data/full_repos/permissive/43856783/lsr_div\n             data/full_repos/permissive/43856783/j1_soc/hdl/Position,data/full_repos/permissive/43856783/lsr_div.v\n             data/full_repos/permissive/43856783/j1_soc/hdl/Position,data/full_repos/permissive/43856783/lsr_div.sv\n             lsr_div\n             lsr_div.v\n             lsr_div.sv\n             obj_dir/lsr_div\n             obj_dir/lsr_div.v\n             obj_dir/lsr_div.sv\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/Position/div_64.v:22: Cannot find file containing module: 'subtractor'\n  subtractor sb ( .clk(clk) , .rst(rst), .in_A(Reg_A) , .in_B(B) , .MSB(MSB) , .Result(Result_Sub), .DV0(DV0) );\n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/Position/div_64.v:23: Cannot find file containing module: 'counter_div'\n  counter_div ctr_dv ( .clk(clk) , .rst(INIT) , .DEC(DEC), .z(z) );\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/Position/div_64.v:24: Cannot find file containing module: 'control_div'\n  control_div ctl_dv ( .clk(clk) , .rst(rst) , .start(init_in) , .MSB(MSB) , .z(z) , .INIT(INIT) , .SH(SH) , .DEC(DEC) , .LDA(LDA) , .BUSY(busy), .DV0(DV0) );\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/Position/div_64.v:25: Cannot find file containing module: 'final_result'\n  final_result fr ( .clk(clk), .rst(INIT) , .DEC(DEC) , .MSB(MSB) , .Result(Result));\n  ^~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module div_64(clk , rst , init_in , A , B , Result , busy);
  
  input rst;
  input clk;
  input init_in;
  input [63:0]A;
  input [63:0]B;
  output [63:0] Result;
  output busy;


  wire INIT, SH, LDA;
  
  wire MSB;
  wire [63:0] Result_Sub;
  wire [63:0] Reg_A;

  wire DEC, z, DV0;

  
  lsr_div lsr_d ( .clk(clk) , .rst(0), .DV_in(A), .Result(Result_Sub), .INIT(INIT), .SH(SH), .LDA(LDA), .A(Reg_A) );
  subtractor sb ( .clk(clk) , .rst(rst), .in_A(Reg_A) , .in_B(B) , .MSB(MSB) , .Result(Result_Sub), .DV0(DV0) );
  counter_div ctr_dv ( .clk(clk) , .rst(INIT) , .DEC(DEC), .z(z) );
  control_div ctl_dv ( .clk(clk) , .rst(rst) , .start(init_in) , .MSB(MSB) , .z(z) , .INIT(INIT) , .SH(SH) , .DEC(DEC) , .LDA(LDA) , .BUSY(busy), .DV0(DV0) );
  final_result fr ( .clk(clk), .rst(INIT) , .DEC(DEC) , .MSB(MSB) , .Result(Result));
    
  

endmodule
module div_64(clk , rst , init_in , A , B , Result , busy);

  
  input rst;
  input clk;
  input init_in;
  input [63:0]A;
  input [63:0]B;
  output [63:0] Result;
  output busy;


  wire INIT, SH, LDA;
  
  wire MSB;
  wire [63:0] Result_Sub;
  wire [63:0] Reg_A;

  wire DEC, z, DV0;

  
  lsr_div lsr_d ( .clk(clk) , .rst(0), .DV_in(A), .Result(Result_Sub), .INIT(INIT), .SH(SH), .LDA(LDA), .A(Reg_A) );
  subtractor sb ( .clk(clk) , .rst(rst), .in_A(Reg_A) , .in_B(B) , .MSB(MSB) , .Result(Result_Sub), .DV0(DV0) );
  counter_div ctr_dv ( .clk(clk) , .rst(INIT) , .DEC(DEC), .z(z) );
  control_div ctl_dv ( .clk(clk) , .rst(rst) , .start(init_in) , .MSB(MSB) , .z(z) , .INIT(INIT) , .SH(SH) , .DEC(DEC) , .LDA(LDA) , .BUSY(busy), .DV0(DV0) );
  final_result fr ( .clk(clk), .rst(INIT) , .DEC(DEC) , .MSB(MSB) , .Result(Result));
    
  

endmodule