data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/memory.v
1: b'%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/memory.v:7: Cannot find include file: define.vh\n`include "define.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src,data/full_repos/permissive/413020148/define.vh\n             data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src,data/full_repos/permissive/413020148/define.vh.v\n             data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src,data/full_repos/permissive/413020148/define.vh.sv\n             define.vh\n             define.vh.v\n             define.vh.sv\n             obj_dir/define.vh\n             obj_dir/define.vh.v\n             obj_dir/define.vh.sv\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/memory.v:129: Define or directive not defined: \'`CACHE_SIZE\'\n    m_dram_cache#(28,128,`CACHE_SIZE/16) cache(o_clk, 1\'b1, 1\'b0, c_clr, c_we,\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/memory.v:129: syntax error, unexpected \'/\', expecting \')\'\n    m_dram_cache#(28,128,`CACHE_SIZE/16) cache(o_clk, 1\'b1, 1\'b0, c_clr, c_we,\n                                    ^\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/memory.v:641: Define or directive not defined: \'`CACHE_SIZE\'\n    m_dram_cache#(28,128,`CACHE_SIZE/16) cache(o_clk, 1\'b1, 1\'b0, c_clr, c_we,\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/memory.v:641: syntax error, unexpected \'/\', expecting \')\'\n    m_dram_cache#(28,128,`CACHE_SIZE/16) cache(o_clk, 1\'b1, 1\'b0, c_clr, c_we,\n                                    ^\n%Error: Exiting due to 5 error(s)\n'
module m_bram#(parameter WIDTH=32, ENTRY=256)(CLK, w_we, w_addr, w_idata, r_odata);
  input  wire                     CLK, w_we;
  input  wire [$clog2(ENTRY)-1:0] w_addr;
  input  wire         [WIDTH-1:0] w_idata;
  output reg          [WIDTH-1:0] r_odata;

  reg          [WIDTH-1:0]  mem [0:ENTRY-1];
  
  integer i;
  initial for (i=0;i<ENTRY;i=i+1) mem[i]=0;

  always  @(posedge  CLK)  begin
    if (w_we) mem[w_addr] <= w_idata;
    r_odata <= mem[w_addr];
  end
endmodule
module m_bram#(parameter WIDTH=32, ENTRY=256)(CLK, w_we, w_addr, w_idata, r_odata);

  input  wire                     CLK, w_we;
  input  wire [$clog2(ENTRY)-1:0] w_addr;
  input  wire         [WIDTH-1:0] w_idata;
  output reg          [WIDTH-1:0] r_odata;

  reg          [WIDTH-1:0]  mem [0:ENTRY-1];
  
  integer i;
  initial for (i=0;i<ENTRY;i=i+1) mem[i]=0;

  always  @(posedge  CLK)  begin
    if (w_we) mem[w_addr] <= w_idata;
    r_odata <= mem[w_addr];
  end
endmodule