data/full_repos/permissive/423693009/Modules/Data_Register_Module/Data_Register_Module.v
1: b"%Error: data/full_repos/permissive/423693009/Modules/Data_Register_Module/Data_Register_Module.v:37: Cannot find file containing module: 'Data_write_Decoder_Module'\n  Data_write_Decoder_Module data_write_decoder(\n  ^~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423693009/Modules/Data_Register_Module,data/full_repos/permissive/423693009/Data_write_Decoder_Module\n             data/full_repos/permissive/423693009/Modules/Data_Register_Module,data/full_repos/permissive/423693009/Data_write_Decoder_Module.v\n             data/full_repos/permissive/423693009/Modules/Data_Register_Module,data/full_repos/permissive/423693009/Data_write_Decoder_Module.sv\n             Data_write_Decoder_Module\n             Data_write_Decoder_Module.v\n             Data_write_Decoder_Module.sv\n             obj_dir/Data_write_Decoder_Module\n             obj_dir/Data_write_Decoder_Module.v\n             obj_dir/Data_write_Decoder_Module.sv\n%Error: data/full_repos/permissive/423693009/Modules/Data_Register_Module/Data_Register_Module.v:43: Cannot find file containing module: 'Mul_Reg_Dataout'\n  Mul_Reg_Dataout multiplexer_A(\n  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423693009/Modules/Data_Register_Module/Data_Register_Module.v:57: Cannot find file containing module: 'Mul_Reg_Dataout'\n   Mul_Reg_Dataout multiplexer_B(\n   ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423693009/Modules/Data_Register_Module/Data_Register_Module.v:74: Cannot find file containing module: 'Data_Register'\n  Data_Register register_000(\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423693009/Modules/Data_Register_Module/Data_Register_Module.v:79: Cannot find file containing module: 'Data_Register'\n  Data_Register register_001(\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423693009/Modules/Data_Register_Module/Data_Register_Module.v:84: Cannot find file containing module: 'Data_Register'\n  Data_Register register_010(\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423693009/Modules/Data_Register_Module/Data_Register_Module.v:89: Cannot find file containing module: 'Data_Register'\n  Data_Register register_011(\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423693009/Modules/Data_Register_Module/Data_Register_Module.v:94: Cannot find file containing module: 'Data_Register'\n  Data_Register register_100(\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423693009/Modules/Data_Register_Module/Data_Register_Module.v:99: Cannot find file containing module: 'Data_Register'\n  Data_Register register_101(\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423693009/Modules/Data_Register_Module/Data_Register_Module.v:104: Cannot find file containing module: 'Data_Register'\n  Data_Register register_110(\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423693009/Modules/Data_Register_Module/Data_Register_Module.v:109: Cannot find file containing module: 'Data_Register'\n  Data_Register register_111(\n  ^~~~~~~~~~~~~\n%Error: Exiting due to 11 error(s)\n"
module Data_Register_Module(

	input Enable_write,
	input [7:0]Data_write,
	input [2:0]Data_write_address,
	
	input Enable_Read_Data_B,
	input Enable_Read_Data_A,
	input [2:0] Data_B_address,
	input [2:0] Data_A_address,
	

	output [7:0]Data_out_A,
	output [7:0]Data_out_B,
	output check
    );
	 
	 wire [7:0] enabler;
	 wire [7:0] data_out_000;
	 wire [7:0] data_out_001;
	 wire [7:0] data_out_010;
	 wire [7:0] data_out_011;
	 wire [7:0] data_out_100;
	 wire [7:0] data_out_101;
	 wire [7:0] data_out_110;
	 wire [7:0] data_out_111;
	 reg CHECK;
	 assign check = CHECK;
	 initial
	  begin
		CHECK = 1'b1;
	  end
	 
	 

	 Data_write_Decoder_Module data_write_decoder(
		.Data_write_address_(Data_write_address),
		.Enable_write_(Enable_write),
		.Enabler(enabler)
	 );

	 Mul_Reg_Dataout multiplexer_A(
		.Dataout_address(Data_A_address),
		.Enable_out(Enable_Read_Data_A),
		.out_000(data_out_000),
		.out_001(data_out_001),
		.out_010(data_out_010),
		.out_011(data_out_011),
		.out_100(data_out_100),
		.out_101(data_out_101),
		.out_110(data_out_110),
		.out_111(data_out_111),
		.Dataout(Data_out_A)
		
	 );
	  Mul_Reg_Dataout multiplexer_B(
		.Dataout_address(Data_B_address),
		.Enable_out(Enable_Read_Data_B),
		.out_000(data_out_000),
		.out_001(data_out_001),
		.out_010(data_out_010),
		.out_011(data_out_011),
		.out_100(data_out_100),
		.out_101(data_out_101),
		.out_110(data_out_110),
		.out_111(data_out_111),
		.Dataout(Data_out_B)
		
	 );
	 
	 

	 Data_Register register_000(
		.Enable_write(enabler[0]),
		.Data_write(Data_write),
		.Data(data_out_000)
	 );
	 Data_Register register_001(
		.Enable_write(enabler[1]),
		.Data_write(Data_write),
		.Data(data_out_001)
	 );
	 Data_Register register_010(
		.Enable_write(enabler[2]),
		.Data_write(Data_write),
		.Data(data_out_010)
	 );
	 Data_Register register_011(
		.Enable_write(enabler[3]),
		.Data_write(Data_write),
		.Data(data_out_011)
	 );
	 Data_Register register_100(
		.Enable_write(enabler[4]),
		.Data_write(Data_write),
		.Data(data_out_100)
	 );
	 Data_Register register_101(
		.Enable_write(enabler[5]),
		.Data_write(Data_write),
		.Data(data_out_101)
	 );
	 Data_Register register_110(
		.Enable_write(enabler[6]),
		.Data_write(Data_write),
		.Data(data_out_110)
	 );
	 Data_Register register_111(
		.Enable_write(enabler[7]),
		.Data_write(Data_write),
		.Data(data_out_111)
	 );
endmodule
module Data_Register_Module(

	input Enable_write,
	input [7:0]Data_write,
	input [2:0]Data_write_address,
	
	input Enable_Read_Data_B,
	input Enable_Read_Data_A,
	input [2:0] Data_B_address,
	input [2:0] Data_A_address,
	

	output [7:0]Data_out_A,
	output [7:0]Data_out_B,
	output check
    );

	 
	 wire [7:0] enabler;
	 wire [7:0] data_out_000;
	 wire [7:0] data_out_001;
	 wire [7:0] data_out_010;
	 wire [7:0] data_out_011;
	 wire [7:0] data_out_100;
	 wire [7:0] data_out_101;
	 wire [7:0] data_out_110;
	 wire [7:0] data_out_111;
	 reg CHECK;
	 assign check = CHECK;
	 initial
	  begin
		CHECK = 1'b1;
	  end
	 
	 

	 Data_write_Decoder_Module data_write_decoder(
		.Data_write_address_(Data_write_address),
		.Enable_write_(Enable_write),
		.Enabler(enabler)
	 );

	 Mul_Reg_Dataout multiplexer_A(
		.Dataout_address(Data_A_address),
		.Enable_out(Enable_Read_Data_A),
		.out_000(data_out_000),
		.out_001(data_out_001),
		.out_010(data_out_010),
		.out_011(data_out_011),
		.out_100(data_out_100),
		.out_101(data_out_101),
		.out_110(data_out_110),
		.out_111(data_out_111),
		.Dataout(Data_out_A)
		
	 );
	  Mul_Reg_Dataout multiplexer_B(
		.Dataout_address(Data_B_address),
		.Enable_out(Enable_Read_Data_B),
		.out_000(data_out_000),
		.out_001(data_out_001),
		.out_010(data_out_010),
		.out_011(data_out_011),
		.out_100(data_out_100),
		.out_101(data_out_101),
		.out_110(data_out_110),
		.out_111(data_out_111),
		.Dataout(Data_out_B)
		
	 );
	 
	 

	 Data_Register register_000(
		.Enable_write(enabler[0]),
		.Data_write(Data_write),
		.Data(data_out_000)
	 );
	 Data_Register register_001(
		.Enable_write(enabler[1]),
		.Data_write(Data_write),
		.Data(data_out_001)
	 );
	 Data_Register register_010(
		.Enable_write(enabler[2]),
		.Data_write(Data_write),
		.Data(data_out_010)
	 );
	 Data_Register register_011(
		.Enable_write(enabler[3]),
		.Data_write(Data_write),
		.Data(data_out_011)
	 );
	 Data_Register register_100(
		.Enable_write(enabler[4]),
		.Data_write(Data_write),
		.Data(data_out_100)
	 );
	 Data_Register register_101(
		.Enable_write(enabler[5]),
		.Data_write(Data_write),
		.Data(data_out_101)
	 );
	 Data_Register register_110(
		.Enable_write(enabler[6]),
		.Data_write(Data_write),
		.Data(data_out_110)
	 );
	 Data_Register register_111(
		.Enable_write(enabler[7]),
		.Data_write(Data_write),
		.Data(data_out_111)
	 );
endmodule