data/full_repos/permissive/503973366/RTL/Max_Pooling/MP_core14/Max_Pooling_core.v
data/verilator_xmls/2378f90e-0e30-423a-89c0-7ce7e1d18d34.xml
module Max_Pooling_Core 
# (
    parameter IN_DATA_WIDTH = 8
)
(
    input clk, reset_n,


    input [IN_DATA_WIDTH - 1 : 0] node1_i, node2_i, node3_i, node4_i,
    
    input valid_i,
    input run_i,

    output valid_o,
    output [IN_DATA_WIDTH - 1 : 0] result_o     
);


    reg [1 : 0]                 r_valid;
    reg [IN_DATA_WIDTH - 1 : 0] r_result;
    

    always @(posedge clk or negedge reset_n) begin
        if(!reset_n) begin
            r_valid <= 2'b0;
        end else if (run_i) begin
            r_valid <= 2'b0;
        end else begin
            r_valid <= {r_valid[0], valid_i};
        end
    end

    reg [IN_DATA_WIDTH - 1 : 0] temp1;
    reg [IN_DATA_WIDTH - 1 : 0] temp2;
    always @(posedge clk or negedge reset_n) begin
        if(!reset_n) begin
            r_result    <= {(IN_DATA_WIDTH){1'b0}};
            temp1       <= {(IN_DATA_WIDTH){1'b0}};
            temp2       <= {(IN_DATA_WIDTH){1'b0}};
        end else if (run_i) begin
            r_result <= {(IN_DATA_WIDTH){1'b0}};
        end else if (valid_i) begin
            if(node1_i < node2_i)   temp1 <= node2_i;
            else                    temp1 <= node1_i;  

            if(node3_i < node4_i)   temp2 <= node4_i;
            else                    temp2 <= node3_i;  

            if(temp1 < temp2)       r_result <= temp2;
            else                    r_result <= temp1;

        end
    end

    assign valid_o  = r_valid[1]; 
    assign result_o = r_result;
endmodule
module Max_Pooling_Core 
# (
    parameter IN_DATA_WIDTH = 8
)
(
    input clk, reset_n,


    input [IN_DATA_WIDTH - 1 : 0] node1_i, node2_i, node3_i, node4_i,
    
    input valid_i,
    input run_i,

    output valid_o,
    output [IN_DATA_WIDTH - 1 : 0] result_o     
);



    reg [1 : 0]                 r_valid;
    reg [IN_DATA_WIDTH - 1 : 0] r_result;
    

    always @(posedge clk or negedge reset_n) begin
        if(!reset_n) begin
            r_valid <= 2'b0;
        end else if (run_i) begin
            r_valid <= 2'b0;
        end else begin
            r_valid <= {r_valid[0], valid_i};
        end
    end

    reg [IN_DATA_WIDTH - 1 : 0] temp1;
    reg [IN_DATA_WIDTH - 1 : 0] temp2;
    always @(posedge clk or negedge reset_n) begin
        if(!reset_n) begin
            r_result    <= {(IN_DATA_WIDTH){1'b0}};
            temp1       <= {(IN_DATA_WIDTH){1'b0}};
            temp2       <= {(IN_DATA_WIDTH){1'b0}};
        end else if (run_i) begin
            r_result <= {(IN_DATA_WIDTH){1'b0}};
        end else if (valid_i) begin
            if(node1_i < node2_i)   temp1 <= node2_i;
            else                    temp1 <= node1_i;  

            if(node3_i < node4_i)   temp2 <= node4_i;
            else                    temp2 <= node3_i;  

            if(temp1 < temp2)       r_result <= temp2;
            else                    r_result <= temp1;

        end
    end

    assign valid_o  = r_valid[1]; 
    assign result_o = r_result;
endmodule