data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v
1: b'%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:3: Cannot find include file: useful_tasks.v\n`include "useful_tasks.v"  // some helper tasks \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/45825386/ahb_to_ssram/sim,data/full_repos/permissive/45825386/useful_tasks.v\n             data/full_repos/permissive/45825386/ahb_to_ssram/sim,data/full_repos/permissive/45825386/useful_tasks.v.v\n             data/full_repos/permissive/45825386/ahb_to_ssram/sim,data/full_repos/permissive/45825386/useful_tasks.v.sv\n             useful_tasks.v\n             useful_tasks.v.v\n             useful_tasks.v.sv\n             obj_dir/useful_tasks.v\n             obj_dir/useful_tasks.v.v\n             obj_dir/useful_tasks.v.sv\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:99: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("tb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:100: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,tb);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n      #100;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:114: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n      #3;\n      ^\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:119: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n      #3;\n      ^\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:122: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:124: Unsupported: Ignoring delay on this delayed statement.\n      #3;\n      ^\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:128: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:129: Unsupported: Ignoring delay on this delayed statement.\n      #3;\n      ^\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:132: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:133: Unsupported: Ignoring delay on this delayed statement.\n      #3;\n      ^\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:135: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:136: Unsupported: Ignoring delay on this delayed statement.\n      #3;\n      ^\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:139: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:141: Unsupported: Ignoring delay on this delayed statement.\n      #3;\n      ^\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:143: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:144: Unsupported: Ignoring delay on this delayed statement.\n      #3;\n      ^\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:146: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:147: Unsupported: Ignoring delay on this delayed statement.\n      #3;\n      ^\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:149: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:150: Unsupported: Ignoring delay on this delayed statement.\n      #3;\n      ^\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:153: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:154: Unsupported: Ignoring delay on this delayed statement.\n      #3;\n      ^\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:157: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:158: Unsupported: Ignoring delay on this delayed statement.\n      #3;\n      ^\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:161: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:162: Unsupported: Ignoring delay on this delayed statement.\n      #3;\n      ^\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:165: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:166: Unsupported: Ignoring delay on this delayed statement.\n      #3;\n      ^\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:171: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:172: Unsupported: Ignoring delay on this delayed statement.\n      #3;\n      ^\n%Error: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:177: syntax error, unexpected \'@\'\n      @(posedge clk);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:180: Unsupported: Ignoring delay on this delayed statement.\n      #1000;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/45825386/ahb_to_ssram/sim/tb.v:188: Unsupported: Ignoring delay on this delayed statement.\n      #100000;\n      ^\n%Error: Exiting due to 19 error(s), 18 warning(s)\n'
module tb;
`include "useful_tasks.v"


   reg rst_async;
   wire rst_n;
   wire done_r;
   wire clk;

   parameter AW = 12;





   wire [AW-1:0]        HADDR;
   wire [31:0]          HRDATA;
   wire                 HREADY;
   wire                 HREADYOUT;
   wire                 HRESP;
   wire                 HSEL;
   wire [2:0]           HSIZE;
   wire [1:0]           HTRANS;
   wire [31:0]          HWDATA;
   wire                 HWRITE;




   chip   #(.AW(AW)) U_CHIP
     (
      .HCLK                                (clk),


      .HRDATA                           (HRDATA[31:0]),
      .HREADYOUT                        (HREADYOUT),
      .HRESP                            (HRESP),

      .HADDR                            (HADDR[AW-1:0]),
      .HREADY                           (HREADY),
      .HRESETn                          (rst_n),
      .HSEL                             (HSEL),
      .HSIZE                            (HSIZE[2:0]),
      .HTRANS                           (HTRANS[1:0]),
      .HWDATA                           (HWDATA[31:0]),
      .HWRITE                           (HWRITE));



   ahb_driver  #(.AW(AW)) U_AHB_DRIVER (
                                        .HCLK              (clk),



                                        .HSEL           (HSEL),
                                        .HADDR          (HADDR[AW-1:0]),
                                        .HTRANS         (HTRANS[1:0]),
                                        .HSIZE          (HSIZE[2:0]),
                                        .HWRITE         (HWRITE),
                                        .HWDATA         (HWDATA[31:0]),
                                        .HREADY         (HREADY),

                                        .HRESETn        (rst_n),
                                        .HREADYOUT      (HREADYOUT),
                                        .HRDATA         (HRDATA[31:0]),
                                        .HRESP          (HRESP));




   clock_gen U_CLK_GEN (


                        .clk            (clk));



   reset_generator U_RESET_GEN (


                                .rst_n          (rst_n),

                                .clk            (clk),
                                .rst_async      (rst_async));






   initial
     begin
	$dumpfile("tb.vcd");
	$dumpvars(0,tb);
     end


   reg [31:0] tmp;
   reg [7:0]  tmp8;

   initial begin
      rst_async = 1'b0;



      #100;
      rst_async = 1'b1;
      @(posedge clk);
      @(posedge clk);
      #3;

      U_AHB_DRIVER.t_write32bits_non_seq(12'h010,32'hCAFEBABE);
      @(posedge clk);
      #3;
      U_AHB_DRIVER.t_write32bits_non_seq(12'h014,32'h12345678);
      @(posedge clk);
      @(posedge clk);
      #3;
      U_AHB_DRIVER.t_read32bits_non_seq(12'h010,tmp);
      check_32bits(tmp,32'hCAFEBABE);

      @(posedge clk);
      #3;
      U_AHB_DRIVER.t_read32bits_non_seq(12'h014,tmp);
      check_32bits(tmp,32'h12345678);
      @(posedge clk);
      #3;
      U_AHB_DRIVER.t_write8bits_non_seq(12'h010,8'h55);
      @(posedge clk);
      #3;
      U_AHB_DRIVER.t_read32bits_non_seq(12'h010,tmp);
      check_32bits(tmp,32'hCAFEBA55);
      @(posedge clk);

      #3;
      U_AHB_DRIVER.t_write8bits_non_seq(12'h011,8'hAA);
      @(posedge clk);
      #3;
      U_AHB_DRIVER.t_write8bits_non_seq(12'h012,8'hBB);
      @(posedge clk);
      #3;
      U_AHB_DRIVER.t_write8bits_non_seq(12'h013,8'hCC);
      @(posedge clk);
      #3;
      U_AHB_DRIVER.t_read32bits_non_seq(12'h010,tmp);
      check_32bits(tmp,32'hCCBBAA55);
      @(posedge clk);
      #3;
      U_AHB_DRIVER.t_read8bits_non_seq(12'h010,tmp8);
      check_8bits(tmp8,8'h55);
      @(posedge clk);
      #3;
      U_AHB_DRIVER.t_read8bits_non_seq(12'h011,tmp8);
      check_8bits(tmp8,8'hAA);
      @(posedge clk);
      #3;
      U_AHB_DRIVER.t_read8bits_non_seq(12'h012,tmp8);
      check_8bits(tmp8,8'hBB);
      @(posedge clk);
      #3;
      U_AHB_DRIVER.t_read8bits_non_seq(12'h013,tmp8);
      check_8bits(tmp8,8'hCC);


      @(posedge clk);
      #3;
      U_AHB_DRIVER.t_read_then_write_32bits(12'h010,tmp,12'h014,32'hDEADBEEF);
      check_32bits(tmp,32'hCCBBAA55);
      U_AHB_DRIVER.t_read32bits_non_seq(12'h014,tmp);
      check_32bits(tmp,32'h12345678);
      @(posedge clk);


      #1000;

      $display("-I- Done !");
      $finish;
   end


   initial begin
      #100000;
      $display("-E- Error (watchdog) !");
      $finish;
   end

endmodule
module tb;

`include "useful_tasks.v"


   reg rst_async;
   wire rst_n;
   wire done_r;
   wire clk;

   parameter AW = 12;





   wire [AW-1:0]        HADDR;
   wire [31:0]          HRDATA;
   wire                 HREADY;
   wire                 HREADYOUT;
   wire                 HRESP;
   wire                 HSEL;
   wire [2:0]           HSIZE;
   wire [1:0]           HTRANS;
   wire [31:0]          HWDATA;
   wire                 HWRITE;




   chip   #(.AW(AW)) U_CHIP
     (
      .HCLK                                (clk),


      .HRDATA                           (HRDATA[31:0]),
      .HREADYOUT                        (HREADYOUT),
      .HRESP                            (HRESP),

      .HADDR                            (HADDR[AW-1:0]),
      .HREADY                           (HREADY),
      .HRESETn                          (rst_n),
      .HSEL                             (HSEL),
      .HSIZE                            (HSIZE[2:0]),
      .HTRANS                           (HTRANS[1:0]),
      .HWDATA                           (HWDATA[31:0]),
      .HWRITE                           (HWRITE));



   ahb_driver  #(.AW(AW)) U_AHB_DRIVER (
                                        .HCLK              (clk),



                                        .HSEL           (HSEL),
                                        .HADDR          (HADDR[AW-1:0]),
                                        .HTRANS         (HTRANS[1:0]),
                                        .HSIZE          (HSIZE[2:0]),
                                        .HWRITE         (HWRITE),
                                        .HWDATA         (HWDATA[31:0]),
                                        .HREADY         (HREADY),

                                        .HRESETn        (rst_n),
                                        .HREADYOUT      (HREADYOUT),
                                        .HRDATA         (HRDATA[31:0]),
                                        .HRESP          (HRESP));




   clock_gen U_CLK_GEN (


                        .clk            (clk));



   reset_generator U_RESET_GEN (


                                .rst_n          (rst_n),

                                .clk            (clk),
                                .rst_async      (rst_async));






   initial
     begin
	$dumpfile("tb.vcd");
	$dumpvars(0,tb);
     end


   reg [31:0] tmp;
   reg [7:0]  tmp8;

   initial begin
      rst_async = 1'b0;



      #100;
      rst_async = 1'b1;
      @(posedge clk);
      @(posedge clk);
      #3;

      U_AHB_DRIVER.t_write32bits_non_seq(12'h010,32'hCAFEBABE);
      @(posedge clk);
      #3;
      U_AHB_DRIVER.t_write32bits_non_seq(12'h014,32'h12345678);
      @(posedge clk);
      @(posedge clk);
      #3;
      U_AHB_DRIVER.t_read32bits_non_seq(12'h010,tmp);
      check_32bits(tmp,32'hCAFEBABE);

      @(posedge clk);
      #3;
      U_AHB_DRIVER.t_read32bits_non_seq(12'h014,tmp);
      check_32bits(tmp,32'h12345678);
      @(posedge clk);
      #3;
      U_AHB_DRIVER.t_write8bits_non_seq(12'h010,8'h55);
      @(posedge clk);
      #3;
      U_AHB_DRIVER.t_read32bits_non_seq(12'h010,tmp);
      check_32bits(tmp,32'hCAFEBA55);
      @(posedge clk);

      #3;
      U_AHB_DRIVER.t_write8bits_non_seq(12'h011,8'hAA);
      @(posedge clk);
      #3;
      U_AHB_DRIVER.t_write8bits_non_seq(12'h012,8'hBB);
      @(posedge clk);
      #3;
      U_AHB_DRIVER.t_write8bits_non_seq(12'h013,8'hCC);
      @(posedge clk);
      #3;
      U_AHB_DRIVER.t_read32bits_non_seq(12'h010,tmp);
      check_32bits(tmp,32'hCCBBAA55);
      @(posedge clk);
      #3;
      U_AHB_DRIVER.t_read8bits_non_seq(12'h010,tmp8);
      check_8bits(tmp8,8'h55);
      @(posedge clk);
      #3;
      U_AHB_DRIVER.t_read8bits_non_seq(12'h011,tmp8);
      check_8bits(tmp8,8'hAA);
      @(posedge clk);
      #3;
      U_AHB_DRIVER.t_read8bits_non_seq(12'h012,tmp8);
      check_8bits(tmp8,8'hBB);
      @(posedge clk);
      #3;
      U_AHB_DRIVER.t_read8bits_non_seq(12'h013,tmp8);
      check_8bits(tmp8,8'hCC);


      @(posedge clk);
      #3;
      U_AHB_DRIVER.t_read_then_write_32bits(12'h010,tmp,12'h014,32'hDEADBEEF);
      check_32bits(tmp,32'hCCBBAA55);
      U_AHB_DRIVER.t_read32bits_non_seq(12'h014,tmp);
      check_32bits(tmp,32'h12345678);
      @(posedge clk);


      #1000;

      $display("-I- Done !");
      $finish;
   end


   initial begin
      #100000;
      $display("-E- Error (watchdog) !");
      $finish;
   end

endmodule