data/full_repos/permissive/471533249/matrix_mult_tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/471533249/matrix_mult_tb.sv:22: Unsupported: Ignoring delay on this delayed statement.\n  clock = 0; #20; clock = 1; #20;\n             ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/471533249/matrix_mult_tb.sv:22: Unsupported: Ignoring delay on this delayed statement.\n  clock = 0; #20; clock = 1; #20;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/471533249/matrix_mult_tb.sv:33: Unsupported: Ignoring delay on this delayed statement.\n  #1; {resetn, read, write, address, writedata, readdata_exp} = testvectors[vectornum];\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/471533249/matrix_mult_tb.sv:38: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: data/full_repos/permissive/471533249/matrix_mult_tb.sv:17: Cannot find file containing module: \'matrix_mult\'\n matrix_mult dut(clock, resetn, address, writedata, readdata, write, read);\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/471533249,data/full_repos/permissive/471533249/matrix_mult\n             data/full_repos/permissive/471533249,data/full_repos/permissive/471533249/matrix_mult.v\n             data/full_repos/permissive/471533249,data/full_repos/permissive/471533249/matrix_mult.sv\n             matrix_mult\n             matrix_mult.v\n             matrix_mult.sv\n             obj_dir/matrix_mult\n             obj_dir/matrix_mult.v\n             obj_dir/matrix_mult.sv\n%Warning-WIDTH: data/full_repos/permissive/471533249/matrix_mult_tb.sv:33: Bit extraction of array[400:0] requires 9 bit index, not 16 bits.\n                                                                         : ... In instance matrix_mult_tb\n  #1; {resetn, read, write, address, writedata, readdata_exp} = testvectors[vectornum];\n                                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/471533249/matrix_mult_tb.sv:46: Bit extraction of array[400:0] requires 9 bit index, not 16 bits.\n                                                                         : ... In instance matrix_mult_tb\n  if (testvectors[vectornum] == \'bx) begin\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/471533249/matrix_mult_tb.sv:46: Unsized constant being X/Z extended to 69 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                         : ... In instance matrix_mult_tb\n  if (testvectors[vectornum] == \'bx) begin\n                                ^~~\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module matrix_mult_tb();


	logic clock, resetn, read, write;
	logic [1:0] address;
	logic [31:0] writedata;
	

	logic[31:0] readdata, readdata_exp;
	

	logic [15:0] vectornum, errors;
   logic [68:0] testvectors[400:0];
	

	matrix_mult dut(clock, resetn, address, writedata, readdata, write, read);
	

   always
   begin
		clock = 0; #20; clock = 1; #20;
   end
	
	initial 
	begin
		$readmemb("matrix_mult.tv", testvectors);
		vectornum = 0; errors = 0;
	end
	
	always @(negedge clock)
	begin	
		#1; {resetn, read, write, address, writedata, readdata_exp} = testvectors[vectornum];
	end
	
	always @(posedge clock)
	begin
		#10;
		if (readdata != readdata_exp) begin
			$display("Error: inputs: resetn = %b, read = %b, write = %b, address = %b, writedata = %h", 
						resetn, read, write, address, writedata);
			$display("outputs: = %h (%h expected)", readdata, readdata_exp);
			errors = errors + 1;
		end
		vectornum = vectornum + 1;
		if (testvectors[vectornum] == 'bx) begin
			$display("$d tests completed with $d errors", vectornum, errors);
			$finish;
		end
	end
endmodule
module matrix_mult_tb();



	logic clock, resetn, read, write;
	logic [1:0] address;
	logic [31:0] writedata;
	

	logic[31:0] readdata, readdata_exp;
	

	logic [15:0] vectornum, errors;
   logic [68:0] testvectors[400:0];
	

	matrix_mult dut(clock, resetn, address, writedata, readdata, write, read);
	

   always
   begin
		clock = 0; #20; clock = 1; #20;
   end
	
	initial 
	begin
		$readmemb("matrix_mult.tv", testvectors);
		vectornum = 0; errors = 0;
	end
	
	always @(negedge clock)
	begin	
		#1; {resetn, read, write, address, writedata, readdata_exp} = testvectors[vectornum];
	end
	
	always @(posedge clock)
	begin
		#10;
		if (readdata != readdata_exp) begin
			$display("Error: inputs: resetn = %b, read = %b, write = %b, address = %b, writedata = %h", 
						resetn, read, write, address, writedata);
			$display("outputs: = %h (%h expected)", readdata, readdata_exp);
			errors = errors + 1;
		end
		vectornum = vectornum + 1;
		if (testvectors[vectornum] == 'bx) begin
			$display("$d tests completed with $d errors", vectornum, errors);
			$finish;
		end
	end
endmodule