data/full_repos/permissive/458737381/src/verilog-parser/tests/param_more_then_one.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/param_more_then_one.v:2: Input/output/inout declaration not found for port: 'clk'\nclk         ,  \n^~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/param_more_then_one.v:3: Input/output/inout declaration not found for port: 'address'\naddress     ,  \n^~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/param_more_then_one.v:4: Input/output/inout declaration not found for port: 'data'\ndata        ,  \n^~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/param_more_then_one.v:5: Input/output/inout declaration not found for port: 'cs'\ncs          ,  \n^~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/param_more_then_one.v:6: Input/output/inout declaration not found for port: 'we'\nwe          ,  \n^~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/param_more_then_one.v:7: Input/output/inout declaration not found for port: 'oe'\noe             \n^~\n%Error: Exiting due to 6 error(s)\n"
module  ram_sp_sr_sw ( 
clk         ,
address     ,
data        ,
cs          ,
we          ,
oe
); 

parameter DATA_WIDTH = 8 ;
parameter ADDR_WIDTH = 8 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;


endmodule
module  ram_sp_sr_sw ( 
clk         ,
address     ,
data        ,
cs          ,
we          ,
oe
);
 

parameter DATA_WIDTH = 8 ;
parameter ADDR_WIDTH = 8 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;


endmodule