data/full_repos/permissive/513398397/verilog/register_file.v
data/verilator_xmls/65fec8d8-85a0-4410-ac51-b34c41ea8602.xml
module register_file(
    output [31:0] RD1, RD2,
    input  [4:0] RR1, RR2, WR,
    input  [31:0] WD,
    input  RegWrite, clk, rst
);

reg [31:0] Register_file [0:31];

assign RD1 = Register_file[RR1];
assign RD2 = Register_file[RR2];

always @ (posedge clk) begin
    if (rst) begin
        Register_file[0]  <= 32'b0;
        Register_file[1]  <= 32'b0;
        Register_file[2]  <= 32'b0;
        Register_file[3]  <= 32'b0;
        Register_file[4]  <= 32'b0;
        Register_file[5]  <= 32'b0;
        Register_file[6]  <= 32'b0;
        Register_file[7]  <= 32'b0;
        Register_file[8]  <= 32'b0;
        Register_file[9]  <= 32'b0;
        Register_file[10] <= 32'b0;
        Register_file[11] <= 32'b0;
        Register_file[12] <= 32'b0;
        Register_file[13] <= 32'b0;
        Register_file[14] <= 32'b0;
        Register_file[15] <= 32'b0;
        Register_file[16] <= 32'b0;
        Register_file[17] <= 32'b0;
        Register_file[18] <= 32'b0;
        Register_file[19] <= 32'b0;
        Register_file[20] <= 32'b0;
        Register_file[21] <= 32'b0;
        Register_file[22] <= 32'b0;
        Register_file[23] <= 32'b0;
        Register_file[24] <= 32'b0;
        Register_file[25] <= 32'b0;
        Register_file[26] <= 32'b0;
        Register_file[27] <= 32'b0;
        Register_file[28] <= 32'b0;
        Register_file[29] <= 32'b0;
        Register_file[30] <= 32'b0;
        Register_file[31] <= 32'b0;
    end
    else if (RegWrite) begin
        if (|WR) begin
            Register_file[WR] <= WD;    
        end
    end
end

endmodule
module register_file(
    output [31:0] RD1, RD2,
    input  [4:0] RR1, RR2, WR,
    input  [31:0] WD,
    input  RegWrite, clk, rst
);


reg [31:0] Register_file [0:31];

assign RD1 = Register_file[RR1];
assign RD2 = Register_file[RR2];

always @ (posedge clk) begin
    if (rst) begin
        Register_file[0]  <= 32'b0;
        Register_file[1]  <= 32'b0;
        Register_file[2]  <= 32'b0;
        Register_file[3]  <= 32'b0;
        Register_file[4]  <= 32'b0;
        Register_file[5]  <= 32'b0;
        Register_file[6]  <= 32'b0;
        Register_file[7]  <= 32'b0;
        Register_file[8]  <= 32'b0;
        Register_file[9]  <= 32'b0;
        Register_file[10] <= 32'b0;
        Register_file[11] <= 32'b0;
        Register_file[12] <= 32'b0;
        Register_file[13] <= 32'b0;
        Register_file[14] <= 32'b0;
        Register_file[15] <= 32'b0;
        Register_file[16] <= 32'b0;
        Register_file[17] <= 32'b0;
        Register_file[18] <= 32'b0;
        Register_file[19] <= 32'b0;
        Register_file[20] <= 32'b0;
        Register_file[21] <= 32'b0;
        Register_file[22] <= 32'b0;
        Register_file[23] <= 32'b0;
        Register_file[24] <= 32'b0;
        Register_file[25] <= 32'b0;
        Register_file[26] <= 32'b0;
        Register_file[27] <= 32'b0;
        Register_file[28] <= 32'b0;
        Register_file[29] <= 32'b0;
        Register_file[30] <= 32'b0;
        Register_file[31] <= 32'b0;
    end
    else if (RegWrite) begin
        if (|WR) begin
            Register_file[WR] <= WD;    
        end
    end
end

endmodule