data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/axi_lite_interface.sv
1: b"%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/axi_lite_interface.sv:24: syntax error, unexpected ::, expecting ')' or ','\n    input  ariane_axi::req_t          axi_req_i,\n                     ^~\n                                                                                               : ... Perhaps 'ariane_axi' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/axi_lite_interface.sv:28: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic                      en_o,         \n    ^~~~~~\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/axi_lite_interface.sv:29: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic                      we_o,         \n    ^~~~~~\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/axi_lite_interface.sv:30: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic [AXI_DATA_WIDTH-1:0] data_i,       \n    ^~~~~\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/axi_lite_interface.sv:31: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic [AXI_DATA_WIDTH-1:0] data_o\n    ^~~~~~\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/axi_lite_interface.sv:32: syntax error, unexpected ')', expecting ',' or ';'\n);\n^\n%Error: data/full_repos/permissive/489147019/Flows/ASAP7/ariane136/rtl/axi_lite_interface.sv:42: syntax error, unexpected assign\n    assign axi_resp_o.r.data = data_i;\n    ^~~~~~\n%Error: Exiting due to 7 error(s)\n"
module axi_lite_interface #(
    parameter int unsigned AXI_ADDR_WIDTH = 64,
    parameter int unsigned AXI_DATA_WIDTH = 64,
    parameter int unsigned AXI_ID_WIDTH   = 10
)(
    input logic                       clk_i,
    input logic                       rst_ni,

    input  ariane_axi::req_t          axi_req_i,
    output ariane_axi::resp_t         axi_resp_o,

    output logic [AXI_ADDR_WIDTH-1:0] address_o,
    output logic                      en_o,
    output logic                      we_o,
    input  logic [AXI_DATA_WIDTH-1:0] data_i,
    output logic [AXI_DATA_WIDTH-1:0] data_o
);


    enum logic [1:0] { IDLE, READ, WRITE, WRITE_B} CS, NS;

    logic [AXI_ID_WIDTH-1:0]   trans_id_n, trans_id_q;

    logic [AXI_ADDR_WIDTH-1:0] address_n,  address_q;


    assign axi_resp_o.r.data = data_i;

    assign axi_resp_o.r.id = trans_id_q;
    assign axi_resp_o.b.id = trans_id_q;

    assign axi_resp_o.r.last = 1'b1;

    assign axi_resp_o.b.resp = 2'b0;
    assign axi_resp_o.r.resp = 2'b0;

    assign data_o = axi_req_i.w.data;



    always_comb begin

        NS         = CS;
        address_n  = address_q;
        trans_id_n = trans_id_q;


        axi_resp_o.aw_ready = 1'b0;
        axi_resp_o.w_ready  = 1'b0;
        axi_resp_o.b_valid  = 1'b0;

        axi_resp_o.ar_ready = 1'b1;
        axi_resp_o.r_valid  = 1'b0;

        address_o      = '0;
        we_o           = 1'b0;
        en_o           = 1'b0;

        case (CS)

            IDLE: begin

                if (axi_req_i.aw_valid) begin

                    axi_resp_o.aw_ready = 1'b1;

                    NS = WRITE;

                    address_n = axi_req_i.aw.addr;

                    trans_id_n = axi_req_i.aw.id;


                end else if (axi_req_i.ar_valid) begin
                    NS = READ;
                    address_n = axi_req_i.ar.addr;

                    address_o = axi_req_i.ar.addr;

                    trans_id_n = axi_req_i.ar.id;

                end
            end


            READ: begin

                en_o       = 1'b1;

                axi_resp_o.ar_ready = 1'b0;

                address_o = address_q;

                axi_resp_o.r_valid = 1'b1;

                if (axi_req_i.r_ready)
                    NS = IDLE;
            end


            WRITE: begin
                if (axi_req_i.w_valid) begin

                    axi_resp_o.ar_ready = 1'b0;
                    axi_resp_o.w_ready = 1'b1;

                    address_o = address_q;
                    en_o = 1'b1;
                    we_o = 1'b1;

                    NS = WRITE_B;
                end
            end

            WRITE_B: begin
                axi_resp_o.b_valid  = 1'b1;

                if (axi_req_i.b_ready)
                    NS = IDLE;
            end
            default:;

        endcase
    end




    always_ff @(posedge clk_i or negedge rst_ni) begin
        if (~rst_ni) begin
            CS         <= IDLE;
            address_q  <= '0;
            trans_id_q <= '0;
        end else begin
            CS         <= NS;
            address_q  <= address_n;
            trans_id_q <= trans_id_n;
        end
    end






    `ifndef VERILATOR

    assert property (@(posedge clk_i) axi_req_i.ar_valid |->  ((axi_req_i.ar.len == 8'b0)))
    else begin $error("AXI Lite does not support bursts larger than 1 or byte length unequal to the native bus size"); $stop(); end

    assert property (@(posedge clk_i) axi_req_i.aw_valid |->  ((axi_req_i.aw.len == 8'b0)))
    else begin $error("AXI Lite does not support bursts larger than 1 or byte length unequal to the native bus size"); $stop(); end
    `endif

endmodule
module axi_lite_interface #(
    parameter int unsigned AXI_ADDR_WIDTH = 64,
    parameter int unsigned AXI_DATA_WIDTH = 64,
    parameter int unsigned AXI_ID_WIDTH   = 10
)(
    input logic                       clk_i,
    input logic                       rst_ni,

    input  ariane_axi::req_t          axi_req_i,
    output ariane_axi::resp_t         axi_resp_o,

    output logic [AXI_ADDR_WIDTH-1:0] address_o,
    output logic                      en_o,
    output logic                      we_o,
    input  logic [AXI_DATA_WIDTH-1:0] data_i,
    output logic [AXI_DATA_WIDTH-1:0] data_o
);



    enum logic [1:0] { IDLE, READ, WRITE, WRITE_B} CS, NS;

    logic [AXI_ID_WIDTH-1:0]   trans_id_n, trans_id_q;

    logic [AXI_ADDR_WIDTH-1:0] address_n,  address_q;


    assign axi_resp_o.r.data = data_i;

    assign axi_resp_o.r.id = trans_id_q;
    assign axi_resp_o.b.id = trans_id_q;

    assign axi_resp_o.r.last = 1'b1;

    assign axi_resp_o.b.resp = 2'b0;
    assign axi_resp_o.r.resp = 2'b0;

    assign data_o = axi_req_i.w.data;



    always_comb begin

        NS         = CS;
        address_n  = address_q;
        trans_id_n = trans_id_q;


        axi_resp_o.aw_ready = 1'b0;
        axi_resp_o.w_ready  = 1'b0;
        axi_resp_o.b_valid  = 1'b0;

        axi_resp_o.ar_ready = 1'b1;
        axi_resp_o.r_valid  = 1'b0;

        address_o      = '0;
        we_o           = 1'b0;
        en_o           = 1'b0;

        case (CS)

            IDLE: begin

                if (axi_req_i.aw_valid) begin

                    axi_resp_o.aw_ready = 1'b1;

                    NS = WRITE;

                    address_n = axi_req_i.aw.addr;

                    trans_id_n = axi_req_i.aw.id;


                end else if (axi_req_i.ar_valid) begin
                    NS = READ;
                    address_n = axi_req_i.ar.addr;

                    address_o = axi_req_i.ar.addr;

                    trans_id_n = axi_req_i.ar.id;

                end
            end


            READ: begin

                en_o       = 1'b1;

                axi_resp_o.ar_ready = 1'b0;

                address_o = address_q;

                axi_resp_o.r_valid = 1'b1;

                if (axi_req_i.r_ready)
                    NS = IDLE;
            end


            WRITE: begin
                if (axi_req_i.w_valid) begin

                    axi_resp_o.ar_ready = 1'b0;
                    axi_resp_o.w_ready = 1'b1;

                    address_o = address_q;
                    en_o = 1'b1;
                    we_o = 1'b1;

                    NS = WRITE_B;
                end
            end

            WRITE_B: begin
                axi_resp_o.b_valid  = 1'b1;

                if (axi_req_i.b_ready)
                    NS = IDLE;
            end
            default:;

        endcase
    end




    always_ff @(posedge clk_i or negedge rst_ni) begin
        if (~rst_ni) begin
            CS         <= IDLE;
            address_q  <= '0;
            trans_id_q <= '0;
        end else begin
            CS         <= NS;
            address_q  <= address_n;
            trans_id_q <= trans_id_n;
        end
    end






    `ifndef VERILATOR

    assert property (@(posedge clk_i) axi_req_i.ar_valid |->  ((axi_req_i.ar.len == 8'b0)))
    else begin $error("AXI Lite does not support bursts larger than 1 or byte length unequal to the native bus size"); $stop(); end

    assert property (@(posedge clk_i) axi_req_i.aw_valid |->  ((axi_req_i.aw.len == 8'b0)))
    else begin $error("AXI Lite does not support bursts larger than 1 or byte length unequal to the native bus size"); $stop(); end
    `endif

endmodule