data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v
1: b'%Error: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:121: Unsupported or unknown PLI call: $dumpfile\n                $dumpfile("top_test_gen.vcd");\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:122: Unsupported or unknown PLI call: $dumpvars\n                $dumpvars(0,top_test_gen);\n                ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:125: Unsupported: Ignoring delay on this delayed statement.\n                #PERIOD;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:128: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD/2);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:130: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD/2);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:132: Unsupported: Ignoring delay on this delayed statement.\n                #(PERIOD);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:154: Unsupported: Ignoring delay on this delayed statement.\n#PERIOD;\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:158: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:161: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:164: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:167: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:170: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:173: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:176: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:179: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:182: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:185: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:188: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:191: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:194: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:197: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:200: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:203: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:206: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:209: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:212: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:215: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:218: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:221: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:224: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:227: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:230: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:233: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:236: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:239: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:242: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:245: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:248: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:251: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:254: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:257: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:260: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:263: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:266: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:269: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:272: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:275: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:278: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:281: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:284: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:287: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:290: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:293: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:296: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:299: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:302: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:305: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:308: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:311: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:314: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:317: Unsupported: Ignoring delay on this delayed statement.\n#(PERIOD);\n^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:321: Unsupported: Ignoring delay on this delayed statement.\n            #PERIOD;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:324: Unsupported: Ignoring delay on this delayed statement.\n            #PERIOD;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:331: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD/2);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:333: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD/2);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/gen/top_test_gen.v:357: Unsupported: Ignoring delay on this delayed statement.\n            #TIMEOUT;\n            ^\n%Error: Exiting due to 2 error(s), 64 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_test_gen #(
        parameter DATA_WIDTH = 32,
        parameter MAIN_MEM_ADDR_WIDTH = 32,
        parameter LOCAL_VERTEX_MEM_ADDR_WIDTH = 3,   
        parameter CYCLES_WAIT_FOR_RECIEVE = 4'd1,
        parameter MAIN_MEM_CYCLES_WAIT_FOR_RECIEVE = 'd0,
        
        parameter FIFO_MAX_FRAGMENTS = 16,
        parameter FIFO_MAX_TRIANGLES = 1,

        parameter NUM_T_PIPES = 1,
        
        parameter NOPERSPECTIVE = 'b1,
        parameter FLAT = 'b0,
        parameter PROVOKEMODE = 'b0,
        parameter VERTEXSIZE = 4'd7,
        parameter WINDINGORDER = 1'b1,
        parameter ORIGIN_LOCATION = 1'b1,
        parameter FACE_CULLER_ENABLE = 1'b0,
        parameter MODE = 'b0,
        parameter RESX = 16'd200,
        parameter RESY = 16'd200,
        parameter TOTAL_NUM_TRIS = 32'd2,

        parameter POLY_STORAGE_STRUCTURE = 'b0
    )();
            localparam CLOCKWISE =  1'b1;
        localparam ANTICLOCKWISE = 1'b0;
        localparam TwentyFP = 'h41a00000;
        localparam ThirteenFP = 'h41500000;
        localparam TenFP = 32'h41200000;
        localparam NineFP = 32'h41100000;
        localparam FourFP = 32'h40800000;
        localparam TwoFP = 32'h40000000;
        localparam OneFP = 32'h3f800000;
        localparam ZeroFP = 32'h00000000;
        localparam HalfFP = 32'h3f000000;
        localparam QuarterFP = 32'h3e800000;
        localparam PERIOD = 20;
        localparam TIMEOUT = PERIOD*1000000;
        localparam TRI_MEM_FIFODEPTH = (2**LOCAL_VERTEX_MEM_ADDR_WIDTH)*3*5;
        localparam INDIVIDUAL_TRIANGLES = 1'b0;
        localparam TRIANGLE_STRIP = 1'b1;

        reg clk;
        reg resetn; 
        reg en; 
        reg start;
        wire done;
        wire ready;

        wire [DATA_WIDTH-1:0] tri_mem_rd_data;      
        wire [MAIN_MEM_ADDR_WIDTH-1:0] tri_mem_rd_addr; 
        wire [0:0]            tri_mem_rd_en;
        reg [DATA_WIDTH-1:0] tri_mem_wr_data;      
        reg [MAIN_MEM_ADDR_WIDTH-1:0] tri_mem_wr_addr; 
        reg [0:0]            tri_mem_wr_en;

        wire [DATA_WIDTH-1:0] frag_mem_wr_data;       
        wire [MAIN_MEM_ADDR_WIDTH-1:0] frag_mem_wr_addr; 
        wire [0:0]            frag_mem_wr_en;


        reg [DATA_WIDTH-1:0] i_array_ptr;
        reg [DATA_WIDTH-1:0] v_array_ptr;
        reg [DATA_WIDTH-1:0] f_array_ptr;
        reg [31:0] ctrl_reg0;
        reg [31:0] ctrl_reg1;
        reg [DATA_WIDTH-1:0] res_reg;


        top#(
            DATA_WIDTH,
            MAIN_MEM_ADDR_WIDTH,
            LOCAL_VERTEX_MEM_ADDR_WIDTH, 
            CYCLES_WAIT_FOR_RECIEVE,
            MAIN_MEM_CYCLES_WAIT_FOR_RECIEVE,
            FIFO_MAX_FRAGMENTS,
            FIFO_MAX_TRIANGLES,
            NUM_T_PIPES
        ) DUT (
            clk, resetn, en, 
            start,, ready,

            tri_mem_rd_data, tri_mem_rd_addr, tri_mem_rd_en,
            frag_mem_wr_data, frag_mem_wr_addr, frag_mem_wr_en,


            i_array_ptr,
            v_array_ptr,
            f_array_ptr,
            ctrl_reg0,
            ctrl_reg1,
            res_reg
        );

        tri_ram_dual_clock_32_32 tri_mem(
            .data(tri_mem_wr_data),
            .read_addr(tri_mem_rd_addr),
            .write_addr(tri_mem_wr_addr),
            .we(tri_mem_wr_en),
            .read_clk(clk),
            .write_clk(clk),
            .re(tri_mem_rd_en),
            .q(tri_mem_rd_data)
        );
  
        frag_ram_dual_clock_32_32 frag_mem(
            .data(frag_mem_wr_data),
            .read_addr(),
            .write_addr(frag_mem_wr_addr),
            .we(frag_mem_wr_en),
            .read_clk(clk),
            .write_clk(clk),
            .re(),
            .q()
        );
        initial
            begin
                $dumpfile("top_test_gen.vcd");
                $dumpvars(0,top_test_gen);
                en = 1'b1;
                resetn = 1'b1;
                #PERIOD;
                $display("{\"sim_log\": [");
                
                #(PERIOD/2);
                resetn = 1'b0; 
                #(PERIOD/2);
                resetn = 1'b1;
                #(PERIOD);


                ctrl_reg0[31:LOCAL_VERTEX_MEM_ADDR_WIDTH+8] = 'b0;
                ctrl_reg0[LOCAL_VERTEX_MEM_ADDR_WIDTH+7] = NOPERSPECTIVE;
                ctrl_reg0[LOCAL_VERTEX_MEM_ADDR_WIDTH+6] = FLAT;
                ctrl_reg0[LOCAL_VERTEX_MEM_ADDR_WIDTH+5] = PROVOKEMODE;
                ctrl_reg0[LOCAL_VERTEX_MEM_ADDR_WIDTH+4] = WINDINGORDER;
                ctrl_reg0[LOCAL_VERTEX_MEM_ADDR_WIDTH+3] = FACE_CULLER_ENABLE;
                ctrl_reg0[LOCAL_VERTEX_MEM_ADDR_WIDTH+2] = ORIGIN_LOCATION;
                ctrl_reg0[LOCAL_VERTEX_MEM_ADDR_WIDTH+1:LOCAL_VERTEX_MEM_ADDR_WIDTH] = MODE;
                ctrl_reg0[LOCAL_VERTEX_MEM_ADDR_WIDTH-1:0] = VERTEXSIZE;
             
                ctrl_reg1[16] = POLY_STORAGE_STRUCTURE;


ctrl_reg1[15:0] = TOTAL_NUM_TRIS;
res_reg[31:16] = RESX;
res_reg[15:0] = RESY;
i_array_ptr = 0;
v_array_ptr = 6;
f_array_ptr = 55;
#PERIOD;
tri_mem_wr_en = 1'b1;
tri_mem_wr_data = 'h0;
tri_mem_wr_addr = 'd0;
#(PERIOD);
tri_mem_wr_data = 'h1;
tri_mem_wr_addr = 'd1;
#(PERIOD);
tri_mem_wr_data = 'h2;
tri_mem_wr_addr = 'd2;
#(PERIOD);
tri_mem_wr_data = 'h3;
tri_mem_wr_addr = 'd3;
#(PERIOD);
tri_mem_wr_data = 'h4;
tri_mem_wr_addr = 'd4;
#(PERIOD);
tri_mem_wr_data = 'h5;
tri_mem_wr_addr = 'd5;
#(PERIOD);
tri_mem_wr_data = 'h43104a68;
tri_mem_wr_addr = 'd6;
#(PERIOD);
tri_mem_wr_data = 'h42d2920b;
tri_mem_wr_addr = 'd7;
#(PERIOD);
tri_mem_wr_data = 'h40e00000;
tri_mem_wr_addr = 'd8;
#(PERIOD);
tri_mem_wr_data = 'h3f800000;
tri_mem_wr_addr = 'd9;
#(PERIOD);
tri_mem_wr_data = 'h0;
tri_mem_wr_addr = 'd10;
#(PERIOD);
tri_mem_wr_data = 'h0;
tri_mem_wr_addr = 'd11;
#(PERIOD);
tri_mem_wr_data = 'h43ac8000;
tri_mem_wr_addr = 'd12;
#(PERIOD);
tri_mem_wr_data = 'h123;
tri_mem_wr_addr = 'd13;
#(PERIOD);
tri_mem_wr_data = 'h4320de7b;
tri_mem_wr_addr = 'd14;
#(PERIOD);
tri_mem_wr_data = 'h431cc07c;
tri_mem_wr_addr = 'd15;
#(PERIOD);
tri_mem_wr_data = 'h3f800000;
tri_mem_wr_addr = 'd16;
#(PERIOD);
tri_mem_wr_data = 'h0;
tri_mem_wr_addr = 'd17;
#(PERIOD);
tri_mem_wr_data = 'h3f800000;
tri_mem_wr_addr = 'd18;
#(PERIOD);
tri_mem_wr_data = 'h0;
tri_mem_wr_addr = 'd19;
#(PERIOD);
tri_mem_wr_data = 'h43ac8000;
tri_mem_wr_addr = 'd20;
#(PERIOD);
tri_mem_wr_data = 'h123;
tri_mem_wr_addr = 'd21;
#(PERIOD);
tri_mem_wr_data = 'h42ceeb4e;
tri_mem_wr_addr = 'd22;
#(PERIOD);
tri_mem_wr_data = 'h433d647c;
tri_mem_wr_addr = 'd23;
#(PERIOD);
tri_mem_wr_data = 'h3f800000;
tri_mem_wr_addr = 'd24;
#(PERIOD);
tri_mem_wr_data = 'h0;
tri_mem_wr_addr = 'd25;
#(PERIOD);
tri_mem_wr_data = 'h0;
tri_mem_wr_addr = 'd26;
#(PERIOD);
tri_mem_wr_data = 'h3f800000;
tri_mem_wr_addr = 'd27;
#(PERIOD);
tri_mem_wr_data = 'h43ac8000;
tri_mem_wr_addr = 'd28;
#(PERIOD);
tri_mem_wr_data = 'h123;
tri_mem_wr_addr = 'd29;
#(PERIOD);
tri_mem_wr_data = 'h4205b61c;
tri_mem_wr_addr = 'd30;
#(PERIOD);
tri_mem_wr_data = 'h429cfa1c;
tri_mem_wr_addr = 'd31;
#(PERIOD);
tri_mem_wr_data = 'h3f800000;
tri_mem_wr_addr = 'd32;
#(PERIOD);
tri_mem_wr_data = 'h3f800000;
tri_mem_wr_addr = 'd33;
#(PERIOD);
tri_mem_wr_data = 'h0;
tri_mem_wr_addr = 'd34;
#(PERIOD);
tri_mem_wr_data = 'h0;
tri_mem_wr_addr = 'd35;
#(PERIOD);
tri_mem_wr_data = 'h43ac8000;
tri_mem_wr_addr = 'd36;
#(PERIOD);
tri_mem_wr_data = 'h123;
tri_mem_wr_addr = 'd37;
#(PERIOD);
tri_mem_wr_data = 'h429f9044;
tri_mem_wr_addr = 'd38;
#(PERIOD);
tri_mem_wr_data = 'h42828e57;
tri_mem_wr_addr = 'd39;
#(PERIOD);
tri_mem_wr_data = 'h3f800000;
tri_mem_wr_addr = 'd40;
#(PERIOD);
tri_mem_wr_data = 'h0;
tri_mem_wr_addr = 'd41;
#(PERIOD);
tri_mem_wr_data = 'h3f800000;
tri_mem_wr_addr = 'd42;
#(PERIOD);
tri_mem_wr_data = 'h0;
tri_mem_wr_addr = 'd43;
#(PERIOD);
tri_mem_wr_data = 'h43ac8000;
tri_mem_wr_addr = 'd44;
#(PERIOD);
tri_mem_wr_data = 'h123;
tri_mem_wr_addr = 'd45;
#(PERIOD);
tri_mem_wr_data = 'h429f319d;
tri_mem_wr_addr = 'd46;
#(PERIOD);
tri_mem_wr_data = 'hbf831fbe;
tri_mem_wr_addr = 'd47;
#(PERIOD);
tri_mem_wr_data = 'h40e00000;
tri_mem_wr_addr = 'd48;
#(PERIOD);
tri_mem_wr_data = 'h0;
tri_mem_wr_addr = 'd49;
#(PERIOD);
tri_mem_wr_data = 'h0;
tri_mem_wr_addr = 'd50;
#(PERIOD);
tri_mem_wr_data = 'h3f800000;
tri_mem_wr_addr = 'd51;
#(PERIOD);
tri_mem_wr_data = 'h43ac8000;
tri_mem_wr_addr = 'd52;
#(PERIOD);
tri_mem_wr_data = 'h123;
tri_mem_wr_addr = 'd53;
#(PERIOD);
            $display("{\"time\":\"%0t\",\"label\":\"[res_x]\", \"data\":%0d},", $time,res_reg[31:16]);
            $display("{\"time\":\"%0t\",\"label\":\"[res_y]\", \"data\":%0d},", $time,res_reg[15:0]);
            start = 1'b0;
            #PERIOD;
            tri_mem_wr_en = 1'b0;
            start = 1'b1;
            #PERIOD;
            start = 1'b0;

        end
    always 
        begin
            clk = 1'b1; 
            #(PERIOD/2);
            clk = 1'b0;
            #(PERIOD/2);
        end
    
    reg [31:0] clk_counter; 
    always @(posedge clk or negedge resetn) begin
        if(~resetn) begin
            clk_counter <= 'b0;
        end else begin
            clk_counter <= clk_counter + 'b1;
            if (done == 1'b1) begin
                $display("{\"time\":\"%0t\",\"label\":\"[Total_Cycles]\", \"data\":%0d},", $time, clk_counter);
            end
        end
    end
    always@(negedge clk) begin
        if (done == 1'b1) begin
            $display("{\"time\":\"%0t\",\"label\":\"[message]\", \"data\":\"test finished for input combination\"}", $time);
            $display("]}");
            $finish;
        end
    end

    initial 
        begin
            #TIMEOUT;
            $display("{\"time\":\"%0t\",\"label\":\"[message]\", \"data\":\"Simulation Timed Out :(\"}",  $time);
            $display("]}");
            $finish;
        end
    initial
        begin
        end

endmodule
module top_test_gen #(
        parameter DATA_WIDTH = 32,
        parameter MAIN_MEM_ADDR_WIDTH = 32,
        parameter LOCAL_VERTEX_MEM_ADDR_WIDTH = 3,   
        parameter CYCLES_WAIT_FOR_RECIEVE = 4'd1,
        parameter MAIN_MEM_CYCLES_WAIT_FOR_RECIEVE = 'd0,
        
        parameter FIFO_MAX_FRAGMENTS = 16,
        parameter FIFO_MAX_TRIANGLES = 1,

        parameter NUM_T_PIPES = 1,
        
        parameter NOPERSPECTIVE = 'b1,
        parameter FLAT = 'b0,
        parameter PROVOKEMODE = 'b0,
        parameter VERTEXSIZE = 4'd7,
        parameter WINDINGORDER = 1'b1,
        parameter ORIGIN_LOCATION = 1'b1,
        parameter FACE_CULLER_ENABLE = 1'b0,
        parameter MODE = 'b0,
        parameter RESX = 16'd200,
        parameter RESY = 16'd200,
        parameter TOTAL_NUM_TRIS = 32'd2,

        parameter POLY_STORAGE_STRUCTURE = 'b0
    )();

            localparam CLOCKWISE =  1'b1;
        localparam ANTICLOCKWISE = 1'b0;
        localparam TwentyFP = 'h41a00000;
        localparam ThirteenFP = 'h41500000;
        localparam TenFP = 32'h41200000;
        localparam NineFP = 32'h41100000;
        localparam FourFP = 32'h40800000;
        localparam TwoFP = 32'h40000000;
        localparam OneFP = 32'h3f800000;
        localparam ZeroFP = 32'h00000000;
        localparam HalfFP = 32'h3f000000;
        localparam QuarterFP = 32'h3e800000;
        localparam PERIOD = 20;
        localparam TIMEOUT = PERIOD*1000000;
        localparam TRI_MEM_FIFODEPTH = (2**LOCAL_VERTEX_MEM_ADDR_WIDTH)*3*5;
        localparam INDIVIDUAL_TRIANGLES = 1'b0;
        localparam TRIANGLE_STRIP = 1'b1;

        reg clk;
        reg resetn; 
        reg en; 
        reg start;
        wire done;
        wire ready;

        wire [DATA_WIDTH-1:0] tri_mem_rd_data;      
        wire [MAIN_MEM_ADDR_WIDTH-1:0] tri_mem_rd_addr; 
        wire [0:0]            tri_mem_rd_en;
        reg [DATA_WIDTH-1:0] tri_mem_wr_data;      
        reg [MAIN_MEM_ADDR_WIDTH-1:0] tri_mem_wr_addr; 
        reg [0:0]            tri_mem_wr_en;

        wire [DATA_WIDTH-1:0] frag_mem_wr_data;       
        wire [MAIN_MEM_ADDR_WIDTH-1:0] frag_mem_wr_addr; 
        wire [0:0]            frag_mem_wr_en;


        reg [DATA_WIDTH-1:0] i_array_ptr;
        reg [DATA_WIDTH-1:0] v_array_ptr;
        reg [DATA_WIDTH-1:0] f_array_ptr;
        reg [31:0] ctrl_reg0;
        reg [31:0] ctrl_reg1;
        reg [DATA_WIDTH-1:0] res_reg;


        top#(
            DATA_WIDTH,
            MAIN_MEM_ADDR_WIDTH,
            LOCAL_VERTEX_MEM_ADDR_WIDTH, 
            CYCLES_WAIT_FOR_RECIEVE,
            MAIN_MEM_CYCLES_WAIT_FOR_RECIEVE,
            FIFO_MAX_FRAGMENTS,
            FIFO_MAX_TRIANGLES,
            NUM_T_PIPES
        ) DUT (
            clk, resetn, en, 
            start,, ready,

            tri_mem_rd_data, tri_mem_rd_addr, tri_mem_rd_en,
            frag_mem_wr_data, frag_mem_wr_addr, frag_mem_wr_en,


            i_array_ptr,
            v_array_ptr,
            f_array_ptr,
            ctrl_reg0,
            ctrl_reg1,
            res_reg
        );

        tri_ram_dual_clock_32_32 tri_mem(
            .data(tri_mem_wr_data),
            .read_addr(tri_mem_rd_addr),
            .write_addr(tri_mem_wr_addr),
            .we(tri_mem_wr_en),
            .read_clk(clk),
            .write_clk(clk),
            .re(tri_mem_rd_en),
            .q(tri_mem_rd_data)
        );
  
        frag_ram_dual_clock_32_32 frag_mem(
            .data(frag_mem_wr_data),
            .read_addr(),
            .write_addr(frag_mem_wr_addr),
            .we(frag_mem_wr_en),
            .read_clk(clk),
            .write_clk(clk),
            .re(),
            .q()
        );
        initial
            begin
                $dumpfile("top_test_gen.vcd");
                $dumpvars(0,top_test_gen);
                en = 1'b1;
                resetn = 1'b1;
                #PERIOD;
                $display("{\"sim_log\": [");
                
                #(PERIOD/2);
                resetn = 1'b0; 
                #(PERIOD/2);
                resetn = 1'b1;
                #(PERIOD);


                ctrl_reg0[31:LOCAL_VERTEX_MEM_ADDR_WIDTH+8] = 'b0;
                ctrl_reg0[LOCAL_VERTEX_MEM_ADDR_WIDTH+7] = NOPERSPECTIVE;
                ctrl_reg0[LOCAL_VERTEX_MEM_ADDR_WIDTH+6] = FLAT;
                ctrl_reg0[LOCAL_VERTEX_MEM_ADDR_WIDTH+5] = PROVOKEMODE;
                ctrl_reg0[LOCAL_VERTEX_MEM_ADDR_WIDTH+4] = WINDINGORDER;
                ctrl_reg0[LOCAL_VERTEX_MEM_ADDR_WIDTH+3] = FACE_CULLER_ENABLE;
                ctrl_reg0[LOCAL_VERTEX_MEM_ADDR_WIDTH+2] = ORIGIN_LOCATION;
                ctrl_reg0[LOCAL_VERTEX_MEM_ADDR_WIDTH+1:LOCAL_VERTEX_MEM_ADDR_WIDTH] = MODE;
                ctrl_reg0[LOCAL_VERTEX_MEM_ADDR_WIDTH-1:0] = VERTEXSIZE;
             
                ctrl_reg1[16] = POLY_STORAGE_STRUCTURE;


ctrl_reg1[15:0] = TOTAL_NUM_TRIS;
res_reg[31:16] = RESX;
res_reg[15:0] = RESY;
i_array_ptr = 0;
v_array_ptr = 6;
f_array_ptr = 55;
#PERIOD;
tri_mem_wr_en = 1'b1;
tri_mem_wr_data = 'h0;
tri_mem_wr_addr = 'd0;
#(PERIOD);
tri_mem_wr_data = 'h1;
tri_mem_wr_addr = 'd1;
#(PERIOD);
tri_mem_wr_data = 'h2;
tri_mem_wr_addr = 'd2;
#(PERIOD);
tri_mem_wr_data = 'h3;
tri_mem_wr_addr = 'd3;
#(PERIOD);
tri_mem_wr_data = 'h4;
tri_mem_wr_addr = 'd4;
#(PERIOD);
tri_mem_wr_data = 'h5;
tri_mem_wr_addr = 'd5;
#(PERIOD);
tri_mem_wr_data = 'h43104a68;
tri_mem_wr_addr = 'd6;
#(PERIOD);
tri_mem_wr_data = 'h42d2920b;
tri_mem_wr_addr = 'd7;
#(PERIOD);
tri_mem_wr_data = 'h40e00000;
tri_mem_wr_addr = 'd8;
#(PERIOD);
tri_mem_wr_data = 'h3f800000;
tri_mem_wr_addr = 'd9;
#(PERIOD);
tri_mem_wr_data = 'h0;
tri_mem_wr_addr = 'd10;
#(PERIOD);
tri_mem_wr_data = 'h0;
tri_mem_wr_addr = 'd11;
#(PERIOD);
tri_mem_wr_data = 'h43ac8000;
tri_mem_wr_addr = 'd12;
#(PERIOD);
tri_mem_wr_data = 'h123;
tri_mem_wr_addr = 'd13;
#(PERIOD);
tri_mem_wr_data = 'h4320de7b;
tri_mem_wr_addr = 'd14;
#(PERIOD);
tri_mem_wr_data = 'h431cc07c;
tri_mem_wr_addr = 'd15;
#(PERIOD);
tri_mem_wr_data = 'h3f800000;
tri_mem_wr_addr = 'd16;
#(PERIOD);
tri_mem_wr_data = 'h0;
tri_mem_wr_addr = 'd17;
#(PERIOD);
tri_mem_wr_data = 'h3f800000;
tri_mem_wr_addr = 'd18;
#(PERIOD);
tri_mem_wr_data = 'h0;
tri_mem_wr_addr = 'd19;
#(PERIOD);
tri_mem_wr_data = 'h43ac8000;
tri_mem_wr_addr = 'd20;
#(PERIOD);
tri_mem_wr_data = 'h123;
tri_mem_wr_addr = 'd21;
#(PERIOD);
tri_mem_wr_data = 'h42ceeb4e;
tri_mem_wr_addr = 'd22;
#(PERIOD);
tri_mem_wr_data = 'h433d647c;
tri_mem_wr_addr = 'd23;
#(PERIOD);
tri_mem_wr_data = 'h3f800000;
tri_mem_wr_addr = 'd24;
#(PERIOD);
tri_mem_wr_data = 'h0;
tri_mem_wr_addr = 'd25;
#(PERIOD);
tri_mem_wr_data = 'h0;
tri_mem_wr_addr = 'd26;
#(PERIOD);
tri_mem_wr_data = 'h3f800000;
tri_mem_wr_addr = 'd27;
#(PERIOD);
tri_mem_wr_data = 'h43ac8000;
tri_mem_wr_addr = 'd28;
#(PERIOD);
tri_mem_wr_data = 'h123;
tri_mem_wr_addr = 'd29;
#(PERIOD);
tri_mem_wr_data = 'h4205b61c;
tri_mem_wr_addr = 'd30;
#(PERIOD);
tri_mem_wr_data = 'h429cfa1c;
tri_mem_wr_addr = 'd31;
#(PERIOD);
tri_mem_wr_data = 'h3f800000;
tri_mem_wr_addr = 'd32;
#(PERIOD);
tri_mem_wr_data = 'h3f800000;
tri_mem_wr_addr = 'd33;
#(PERIOD);
tri_mem_wr_data = 'h0;
tri_mem_wr_addr = 'd34;
#(PERIOD);
tri_mem_wr_data = 'h0;
tri_mem_wr_addr = 'd35;
#(PERIOD);
tri_mem_wr_data = 'h43ac8000;
tri_mem_wr_addr = 'd36;
#(PERIOD);
tri_mem_wr_data = 'h123;
tri_mem_wr_addr = 'd37;
#(PERIOD);
tri_mem_wr_data = 'h429f9044;
tri_mem_wr_addr = 'd38;
#(PERIOD);
tri_mem_wr_data = 'h42828e57;
tri_mem_wr_addr = 'd39;
#(PERIOD);
tri_mem_wr_data = 'h3f800000;
tri_mem_wr_addr = 'd40;
#(PERIOD);
tri_mem_wr_data = 'h0;
tri_mem_wr_addr = 'd41;
#(PERIOD);
tri_mem_wr_data = 'h3f800000;
tri_mem_wr_addr = 'd42;
#(PERIOD);
tri_mem_wr_data = 'h0;
tri_mem_wr_addr = 'd43;
#(PERIOD);
tri_mem_wr_data = 'h43ac8000;
tri_mem_wr_addr = 'd44;
#(PERIOD);
tri_mem_wr_data = 'h123;
tri_mem_wr_addr = 'd45;
#(PERIOD);
tri_mem_wr_data = 'h429f319d;
tri_mem_wr_addr = 'd46;
#(PERIOD);
tri_mem_wr_data = 'hbf831fbe;
tri_mem_wr_addr = 'd47;
#(PERIOD);
tri_mem_wr_data = 'h40e00000;
tri_mem_wr_addr = 'd48;
#(PERIOD);
tri_mem_wr_data = 'h0;
tri_mem_wr_addr = 'd49;
#(PERIOD);
tri_mem_wr_data = 'h0;
tri_mem_wr_addr = 'd50;
#(PERIOD);
tri_mem_wr_data = 'h3f800000;
tri_mem_wr_addr = 'd51;
#(PERIOD);
tri_mem_wr_data = 'h43ac8000;
tri_mem_wr_addr = 'd52;
#(PERIOD);
tri_mem_wr_data = 'h123;
tri_mem_wr_addr = 'd53;
#(PERIOD);
            $display("{\"time\":\"%0t\",\"label\":\"[res_x]\", \"data\":%0d},", $time,res_reg[31:16]);
            $display("{\"time\":\"%0t\",\"label\":\"[res_y]\", \"data\":%0d},", $time,res_reg[15:0]);
            start = 1'b0;
            #PERIOD;
            tri_mem_wr_en = 1'b0;
            start = 1'b1;
            #PERIOD;
            start = 1'b0;

        end
    always 
        begin
            clk = 1'b1; 
            #(PERIOD/2);
            clk = 1'b0;
            #(PERIOD/2);
        end
    
    reg [31:0] clk_counter; 
    always @(posedge clk or negedge resetn) begin
        if(~resetn) begin
            clk_counter <= 'b0;
        end else begin
            clk_counter <= clk_counter + 'b1;
            if (done == 1'b1) begin
                $display("{\"time\":\"%0t\",\"label\":\"[Total_Cycles]\", \"data\":%0d},", $time, clk_counter);
            end
        end
    end
    always@(negedge clk) begin
        if (done == 1'b1) begin
            $display("{\"time\":\"%0t\",\"label\":\"[message]\", \"data\":\"test finished for input combination\"}", $time);
            $display("]}");
            $finish;
        end
    end

    initial 
        begin
            #TIMEOUT;
            $display("{\"time\":\"%0t\",\"label\":\"[message]\", \"data\":\"Simulation Timed Out :(\"}",  $time);
            $display("]}");
            $finish;
        end
    initial
        begin
        end

endmodule