data/full_repos/permissive/429462627/mips_pipeline.v
1: b'%Error: data/full_repos/permissive/429462627/mips_pipeline.v:138: Unsupported or unknown PLI call: $monitor\n        $monitor($time, " :A = %b,\\n\\t B = %b,\\n\\t ALU_ctrlerartion = %b,\\n\\t Result = %b,\\n\\t Carry Out = %b,\\n\\t Zero = %b.", A, B, ALU_ctrl, result, carry_out, zero);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:139: Unsupported: Ignoring delay on this delayed statement.\n        #0  A = 32\'ha5a5a5a5; B = 32\'h5a5a5a5a; ALU_ctrl = 4\'b0000;      \n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:140: Unsupported: Ignoring delay on this delayed statement.\n        #10  ALU_ctrl = 4\'b0001;                                         \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:141: Unsupported: Ignoring delay on this delayed statement.\n        #10  ALU_ctrl = 4\'b0010;                                         \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:142: Unsupported: Ignoring delay on this delayed statement.\n        #10  ALU_ctrl = 4\'b0110;                                         \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:143: Unsupported: Ignoring delay on this delayed statement.\n        #10  A = 32\'hA5A5A5A5; B = 32\'hA5A5A5A5; ALU_ctrl = 4\'b0110;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:144: Unsupported: Ignoring delay on this delayed statement.\n        #10  B = 32\'hA5A5A5A5; A = 32\'h5A5A5A5A; ALU_ctrl = 4\'b0111;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:145: Unsupported: Ignoring delay on this delayed statement.\n        #10  B = 32\'hA5A5A5A5; A = 32\'h5A5A5A5A; ALU_ctrl = 4\'b1100;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:146: Unsupported: Ignoring delay on this delayed statement.\n        #20  $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:1090: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk = ~clk;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:1096: Unsupported: Ignoring delay on this delayed statement.\n        #5 reset = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/429462627/mips_pipeline.v:1098: Unsupported: Ignoring delay on this delayed statement.\n        #300 $finish;\n        ^\n%Error: Exiting due to 1 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module forwarding_unit (
    input EX_MEM_RegWrite, MEM_WB_RegWrite,
    input [4:0] IF_ID_register_rs,IF_ID_register_rt,
    input [4:0] ID_EX_register_rs, ID_EX_register_rt,
    input [4:0] EX_MEM_register_rd, MEM_WB_register_rd, 

    output reg [1:0] ForwardA, ForwardB);

    wire equal_EXMEM_rs,equal_EXMEM_rt,equal_MEMWB_rs,equal_MEMWB_rt;
    wire nonzero_EXMEM_rd,nonzero_MEMWB_rd;



    assign equal_EXMEM_rs = (EX_MEM_register_rd == ID_EX_register_rs) ? 1 : 0;
    assign equal_EXMEM_rt = (EX_MEM_register_rd == ID_EX_register_rt)? 1 : 0;



    assign equal_MEMWB_rs = (MEM_WB_register_rd == ID_EX_register_rs) ? 1 : 0;
    assign equal_MEMWB_rt = (MEM_WB_register_rd == ID_EX_register_rt) ? 1 : 0;



    assign nonzero_EXMEM_rd = (EX_MEM_register_rd == 0) ? 0 : 1;
    assign nonzero_MEMWB_rd = (MEM_WB_register_rd == 0) ? 0 : 1;

    always@ (EX_MEM_RegWrite or MEM_WB_RegWrite or nonzero_EXMEM_rd or nonzero_MEMWB_rd or equal_EXMEM_rs
    or equal_EXMEM_rt or equal_MEMWB_rs or equal_MEMWB_rt)
    begin


        if(EX_MEM_RegWrite & nonzero_EXMEM_rd & equal_EXMEM_rs)
            ForwardA <= 2'b10;



        else if (MEM_WB_RegWrite & nonzero_MEMWB_rd & equal_MEMWB_rs)
            ForwardA <= 2'b01;


        else 
            ForwardA <= 2'b00;
	

        if(EX_MEM_RegWrite & nonzero_EXMEM_rd & equal_EXMEM_rt)
            ForwardB <= 2'b10;



        else if (MEM_WB_RegWrite & nonzero_MEMWB_rd & equal_MEMWB_rt)
            ForwardB <= 2'b01;


        else 
            ForwardB <= 2'b00;
	end
endmodule
module forwarding_unit (
    input EX_MEM_RegWrite, MEM_WB_RegWrite,
    input [4:0] IF_ID_register_rs,IF_ID_register_rt,
    input [4:0] ID_EX_register_rs, ID_EX_register_rt,
    input [4:0] EX_MEM_register_rd, MEM_WB_register_rd, 

    output reg [1:0] ForwardA, ForwardB);


    wire equal_EXMEM_rs,equal_EXMEM_rt,equal_MEMWB_rs,equal_MEMWB_rt;
    wire nonzero_EXMEM_rd,nonzero_MEMWB_rd;



    assign equal_EXMEM_rs = (EX_MEM_register_rd == ID_EX_register_rs) ? 1 : 0;
    assign equal_EXMEM_rt = (EX_MEM_register_rd == ID_EX_register_rt)? 1 : 0;



    assign equal_MEMWB_rs = (MEM_WB_register_rd == ID_EX_register_rs) ? 1 : 0;
    assign equal_MEMWB_rt = (MEM_WB_register_rd == ID_EX_register_rt) ? 1 : 0;



    assign nonzero_EXMEM_rd = (EX_MEM_register_rd == 0) ? 0 : 1;
    assign nonzero_MEMWB_rd = (MEM_WB_register_rd == 0) ? 0 : 1;

    always@ (EX_MEM_RegWrite or MEM_WB_RegWrite or nonzero_EXMEM_rd or nonzero_MEMWB_rd or equal_EXMEM_rs
    or equal_EXMEM_rt or equal_MEMWB_rs or equal_MEMWB_rt)
    begin


        if(EX_MEM_RegWrite & nonzero_EXMEM_rd & equal_EXMEM_rs)
            ForwardA <= 2'b10;



        else if (MEM_WB_RegWrite & nonzero_MEMWB_rd & equal_MEMWB_rs)
            ForwardA <= 2'b01;


        else 
            ForwardA <= 2'b00;
	

        if(EX_MEM_RegWrite & nonzero_EXMEM_rd & equal_EXMEM_rt)
            ForwardB <= 2'b10;



        else if (MEM_WB_RegWrite & nonzero_MEMWB_rd & equal_MEMWB_rt)
            ForwardB <= 2'b01;


        else 
            ForwardB <= 2'b00;
	end
endmodule