data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/ALU.v
data/verilator_xmls/f34ee858-26f4-44fb-89a3-4669963ce2a3.xml
module ALU(
    input[3:0] ALUop,
    input [31:0] ina, inb,
    output reg zero,
    output reg [31:0] out
    );
    always@(*) begin 
        if(ALUop == 4'b0010)
            out = ina + inb;
        else if(ALUop == 4'b0110)
            out = ina - inb;
        else if(ALUop == 4'b0000)
            out = ina & inb;
        else if(ALUop == 4'b0001)
            out = ina | inb;
        else if(ALUop == 4'b0011)
            out = ina ^ inb;
        else if(ALUop == 4'b0101)
            out = ina >> inb;
        else if(ALUop == 4'b0100)
            out = ina << inb;
        else if(ALUop == 4'b1001)
            out = ina >>> inb;
        else if(ALUop == 4'b0111) begin
            if(ina < inb) 
                out = 1;
            else
                out = 0;
        end
        else if(ALUop == 4'b1000) begin
            if(ina[31] == 1 && inb[31] == 1 ||
               ina[31] == 0 && inb[31] == 0) begin
                if(ina > inb)
                    out = 1;
                else
                    out = 0;
            end
            if(ina[31] == 1 && inb[31] == 0)
                out = 0;
            
            if(ina[31] == 0 && inb[31] == 1)
                out = 1;
        end 
        if(out == 0)
            zero = 1;
        else
            zero = 0;
    end
endmodule
module ALU(
    input[3:0] ALUop,
    input [31:0] ina, inb,
    output reg zero,
    output reg [31:0] out
    );

    always@(*) begin 
        if(ALUop == 4'b0010)
            out = ina + inb;
        else if(ALUop == 4'b0110)
            out = ina - inb;
        else if(ALUop == 4'b0000)
            out = ina & inb;
        else if(ALUop == 4'b0001)
            out = ina | inb;
        else if(ALUop == 4'b0011)
            out = ina ^ inb;
        else if(ALUop == 4'b0101)
            out = ina >> inb;
        else if(ALUop == 4'b0100)
            out = ina << inb;
        else if(ALUop == 4'b1001)
            out = ina >>> inb;
        else if(ALUop == 4'b0111) begin
            if(ina < inb) 
                out = 1;
            else
                out = 0;
        end
        else if(ALUop == 4'b1000) begin
            if(ina[31] == 1 && inb[31] == 1 ||
               ina[31] == 0 && inb[31] == 0) begin
                if(ina > inb)
                    out = 1;
                else
                    out = 0;
            end
            if(ina[31] == 1 && inb[31] == 0)
                out = 0;
            
            if(ina[31] == 0 && inb[31] == 1)
                out = 1;
        end 
        if(out == 0)
            zero = 1;
        else
            zero = 0;
    end
endmodule