data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/clip.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/clip.v:27: Little bit endian vector: MSB < LSB of bit range: -1:0\n    (input [bits_in-1:0] in,\n           ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/clip.v:28: Little bit endian vector: MSB < LSB of bit range: -1:0\n     output [bits_out-1:0] out);\n            ^\n%Error: Internal Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/clip.v:32: ../V3Width.cpp:3809: Under node REPLICATE has no expected width?? Missing Visitor func?\n                                                                                         : ... In instance clip\n      (in[bits_in-1] ? {1\'b1,{(bits_out-1){1\'b0}}} : {1\'b0,{(bits_out-1){1\'b1}}}) :\n                       ^\n'
module clip
  #(parameter bits_in=0,
    parameter bits_out=0)
    (input [bits_in-1:0] in,
     output [bits_out-1:0] out);
   
   wire 		   overflow = |in[bits_in-1:bits_out-1] & ~(&in[bits_in-1:bits_out-1]);   
   assign 		   out = overflow ? 
			   (in[bits_in-1] ? {1'b1,{(bits_out-1){1'b0}}} : {1'b0,{(bits_out-1){1'b1}}}) :
			   in[bits_out-1:0];
   
endmodule
module clip
  #(parameter bits_in=0,
    parameter bits_out=0)
    (input [bits_in-1:0] in,
     output [bits_out-1:0] out);

   
   wire 		   overflow = |in[bits_in-1:bits_out-1] & ~(&in[bits_in-1:bits_out-1]);   
   assign 		   out = overflow ? 
			   (in[bits_in-1] ? {1'b1,{(bits_out-1){1'b0}}} : {1'b0,{(bits_out-1){1'b1}}}) :
			   in[bits_out-1:0];
   
endmodule