data/full_repos/permissive/408955603/Sesion2/circuitoEj1Tema3.v
1: b'%Error: data/full_repos/permissive/408955603/Sesion2/circuitoEj1Tema3.v:13: Unsupported or unknown PLI call: $monitor\n  $monitor($time, " | %b %b %b %b | %b", r[3], r[2], r[1], r[0], salida);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion2/circuitoEj1Tema3.v:15: Unsupported: Ignoring delay on this delayed statement.\n  while(r != \'b1111) #5 r = r + 1;\n                     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module circuitoEj1T3;
	reg [3:0] r;
	wire n1s, a1s, o1s, salida;


	not n1(n1s, r[3]);
	and a1(a1s, n1s, r[2]);
	and a2(salida, o1s, r[0]);
	or o1(o1s, a1s, r[1]);

	initial
	begin
		$monitor($time, " | %b %b %b %b | %b", r[3], r[2], r[1], r[0], salida);
		r = 0;
		while(r != 'b1111) #5 r = r + 1;
	end
endmodule
module circuitoEj1T3;

	reg [3:0] r;
	wire n1s, a1s, o1s, salida;


	not n1(n1s, r[3]);
	and a1(a1s, n1s, r[2]);
	and a2(salida, o1s, r[0]);
	or o1(o1s, a1s, r[1]);

	initial
	begin
		$monitor($time, " | %b %b %b %b | %b", r[3], r[2], r[1], r[0], salida);
		r = 0;
		while(r != 'b1111) #5 r = r + 1;
	end
endmodule