data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v
1: b'%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:23: Cannot find include file: ../genericIOSateliteEnv.v\n`include "../genericIOSateliteEnv.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/429196919/FPGA/ws2811Encoder,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v\n             data/full_repos/permissive/429196919/FPGA/ws2811Encoder,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v.v\n             data/full_repos/permissive/429196919/FPGA/ws2811Encoder,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v.sv\n             ../genericIOSateliteEnv.v\n             ../genericIOSateliteEnv.v.v\n             ../genericIOSateliteEnv.v.sv\n             obj_dir/../genericIOSateliteEnv.v\n             obj_dir/../genericIOSateliteEnv.v.v\n             obj_dir/../genericIOSateliteEnv.v.sv\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:24: Cannot find include file: ../genericIOSateliteEnv_TB.v\n`include "../genericIOSateliteEnv_TB.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:25: Cannot find include file: ../ws2811Decoder/ws2811Decoder.v\n`include "../ws2811Decoder/ws2811Decoder.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:26: Cannot find include file: ws2811Encoder.v\n`include "ws2811Encoder.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:60: Define or directive not defined: \'`OSCH_FREQ\'\n OSCH #(.NOM_FREQ(`OSCH_FREQ)) internal_oscillator_inst (.STDBY(1\'b0), .OSC(masterClk), .SEDSTDBY ());\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:84: Define or directive not defined: \'`WS2811_GENERATE\'\n  `WS2811_GENERATE(ws2811In, 8\'hF0, 0)       \n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:84: syntax error, unexpected \',\'\n  `WS2811_GENERATE(ws2811In, 8\'hF0, 0)       \n                           ^\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:85: Define or directive not defined: \'`WS2811_GENERATE_END\'\n  `WS2811_GENERATE_END(ws2811In)\n  ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:87: Define or directive not defined: \'`WS2811_GENERATE\'\n  `WS2811_GENERATE(ws2811In, 8\'h55, 0)\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:88: Define or directive not defined: \'`CHECK_ACTIVE\'\n  `CHECK_ACTIVE(active, 1\'b1)\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:89: Define or directive not defined: \'`WS2811_GENERATE\'\n  `WS2811_GENERATE(ws2811In, 8\'hAA, 0)\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:90: Define or directive not defined: \'`CHECK_ACTIVE\'\n  `CHECK_ACTIVE(active, 1\'b1)\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:91: Define or directive not defined: \'`WS2811_GENERATE\'\n  `WS2811_GENERATE(ws2811In, 8\'h00, 0)\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:92: Define or directive not defined: \'`CHECK_ACTIVE\'\n  `CHECK_ACTIVE(active, 1\'b1)\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:93: Define or directive not defined: \'`WS2811_GENERATE\'\n  `WS2811_GENERATE(ws2811In, 8\'hFF, 0)\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:94: Define or directive not defined: \'`CHECK_ACTIVE\'\n  `CHECK_ACTIVE(active, 1\'b1)\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:95: Define or directive not defined: \'`WS2811_GENERATE_END\'\n  `WS2811_GENERATE_END(ws2811In)\n  ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:96: Define or directive not defined: \'`CHECK_ACTIVE\'\n  `CHECK_ACTIVE(active, 1\'b0)\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:99: syntax error, unexpected $display\n  $display("ws2811Encoder: Running simulation for maximum positive dataIn skew timing: + %d ns", `MAX_SKEW);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:99: Define or directive not defined: \'`MAX_SKEW\'\n  $display("ws2811Encoder: Running simulation for maximum positive dataIn skew timing: + %d ns", `MAX_SKEW);\n                                                                                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:100: Define or directive not defined: \'`WS2811_GENERATE\'\n  `WS2811_GENERATE(ws2811In, 8\'h55, `MAX_SKEW)\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:100: Define or directive not defined: \'`MAX_SKEW\'\n  `WS2811_GENERATE(ws2811In, 8\'h55, `MAX_SKEW)\n                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:101: Define or directive not defined: \'`CHECK_ACTIVE\'\n  `CHECK_ACTIVE(active, 1\'b1)\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:102: Define or directive not defined: \'`WS2811_GENERATE\'\n  `WS2811_GENERATE(ws2811In, 8\'hAA, `MAX_SKEW)\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:102: Define or directive not defined: \'`MAX_SKEW\'\n  `WS2811_GENERATE(ws2811In, 8\'hAA, `MAX_SKEW)\n                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:103: Define or directive not defined: \'`CHECK_ACTIVE\'\n  `CHECK_ACTIVE(active, 1\'b1)\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:104: Define or directive not defined: \'`WS2811_GENERATE\'\n  `WS2811_GENERATE(ws2811In, 8\'h00, `MAX_SKEW)\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:104: Define or directive not defined: \'`MAX_SKEW\'\n  `WS2811_GENERATE(ws2811In, 8\'h00, `MAX_SKEW)\n                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:105: Define or directive not defined: \'`CHECK_ACTIVE\'\n  `CHECK_ACTIVE(active, 1\'b1)\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:106: Define or directive not defined: \'`WS2811_GENERATE\'\n  `WS2811_GENERATE(ws2811In, 8\'hFF, `MAX_SKEW)\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:106: Define or directive not defined: \'`MAX_SKEW\'\n  `WS2811_GENERATE(ws2811In, 8\'hFF, `MAX_SKEW)\n                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:107: Define or directive not defined: \'`CHECK_ACTIVE\'\n  `CHECK_ACTIVE(active, 1\'b1)\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:108: Define or directive not defined: \'`WS2811_GENERATE_END\'\n  `WS2811_GENERATE_END(ws2811In)\n  ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:109: Define or directive not defined: \'`CHECK_ACTIVE\'\n  `CHECK_ACTIVE(active, 1\'b0)\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:112: Define or directive not defined: \'`MAX_SKEW\'\n  $display("ws2811Encoder: Running simulation for maximum negative dataIn skew timing: - %d ns", `MAX_SKEW);\n                                                                                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:113: Define or directive not defined: \'`WS2811_GENERATE\'\n  `WS2811_GENERATE(ws2811In, 8\'h55, -`MAX_SKEW)\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:113: Define or directive not defined: \'`MAX_SKEW\'\n  `WS2811_GENERATE(ws2811In, 8\'h55, -`MAX_SKEW)\n                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:114: Define or directive not defined: \'`CHECK_ACTIVE\'\n  `CHECK_ACTIVE(active, 1\'b1)\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:115: Define or directive not defined: \'`WS2811_GENERATE\'\n  `WS2811_GENERATE(ws2811In, 8\'hAA, -`MAX_SKEW)\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:115: Define or directive not defined: \'`MAX_SKEW\'\n  `WS2811_GENERATE(ws2811In, 8\'hAA, -`MAX_SKEW)\n                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:116: Define or directive not defined: \'`CHECK_ACTIVE\'\n  `CHECK_ACTIVE(active, 1\'b1)\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:117: Define or directive not defined: \'`WS2811_GENERATE\'\n  `WS2811_GENERATE(ws2811In, 8\'h00, -`MAX_SKEW)\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:117: Define or directive not defined: \'`MAX_SKEW\'\n  `WS2811_GENERATE(ws2811In, 8\'h00, -`MAX_SKEW)\n                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:118: Define or directive not defined: \'`CHECK_ACTIVE\'\n  `CHECK_ACTIVE(active, 1\'b1)\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:119: Define or directive not defined: \'`WS2811_GENERATE\'\n  `WS2811_GENERATE(ws2811In, 8\'hFF, -`MAX_SKEW)\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:119: Define or directive not defined: \'`MAX_SKEW\'\n  `WS2811_GENERATE(ws2811In, 8\'hFF, -`MAX_SKEW)\n                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:120: Define or directive not defined: \'`CHECK_ACTIVE\'\n  `CHECK_ACTIVE(active, 1\'b1)\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:121: Define or directive not defined: \'`WS2811_GENERATE_END\'\n  `WS2811_GENERATE_END(ws2811In)\n  ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:122: Define or directive not defined: \'`CHECK_ACTIVE\'\n  `CHECK_ACTIVE(active, 1\'b0)\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Encoder/ws2811Encoder_TB.v:125: Define or directive not defined: \'`CHECK_ACTIVE\'\n  `CHECK_ACTIVE(active, 1\'b0)\n  ^~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module ws2811Encoder_TB ();
	wire masterClk;
	reg ws2811In;
	wire unModulatedIn;
	wire dataClkIn;
	wire ws2811Out;
	wire unmodulatedOut;
	wire dataClkOut;
	wire active;

	reg[7:0] result_0;
	reg[7:0] result_1;
	reg[7:0] result_2;
	reg[7:0] result_3;

	integer shiftIndex, valIndex;

	ws2811Decoder GENERATOR(.masterClk(masterClk), .dataIn(ws2811In), .dataOut(unModulatedIn), .dataClk(dataClkIn), .active());
	ws2811Encoder DUT(.masterClk(masterClk), .dataClk(dataClkIn), .dataIn(unModulatedIn), .dataOut(ws2811Out));
	ws2811Decoder RECEIVER(.masterClk(masterClk), .dataIn(ws2811Out), .dataOut(unmodulatedOut), .dataClk(dataClkOut), .active(active));
	OSCH #(.NOM_FREQ(`OSCH_FREQ)) internal_oscillator_inst (.STDBY(1'b0), .OSC(masterClk), .SEDSTDBY ());

	always @(posedge dataClkOut) begin

		for(shiftIndex=7; shiftIndex>=0; shiftIndex=shiftIndex-1) begin
			if(shiftIndex != 0) begin
				result_3[shiftIndex] <= result_3[shiftIndex-1];
				result_2[shiftIndex] <= result_2[shiftIndex-1];
				result_1[shiftIndex] <= result_1[shiftIndex-1];
				result_0[shiftIndex] <= result_0[shiftIndex-1];
			end
			else begin
				result_3[0] <= result_2[7];
				result_2[0] <= result_1[7];
				result_1[0] <= result_0[7];
				result_0[0] <= unmodulatedOut;
			end
		end
	end
	
	initial begin
		$display("ws2811Encoder: Initializing simulation for ws2811Encoder");

		$display("ws2811Encoder: Running simulation for nominal dataIn timing, T1H: %d, T1L %d, T0H: %d, T0L", 600, 1240-600, 250, 1240-250);
		`WS2811_GENERATE(ws2811In, 8'hF0, 0)
		`WS2811_GENERATE_END(ws2811In)

		`WS2811_GENERATE(ws2811In, 8'h55, 0)
		`CHECK_ACTIVE(active, 1'b1)
		`WS2811_GENERATE(ws2811In, 8'hAA, 0)
		`CHECK_ACTIVE(active, 1'b1)
		`WS2811_GENERATE(ws2811In, 8'h00, 0)
		`CHECK_ACTIVE(active, 1'b1)
		`WS2811_GENERATE(ws2811In, 8'hFF, 0)
		`CHECK_ACTIVE(active, 1'b1)
		`WS2811_GENERATE_END(ws2811In)
		`CHECK_ACTIVE(active, 1'b0)
		`CHECK_RES(8'h55, 8'hAA, 8'h00, 8'hFF)

		$display("ws2811Encoder: Running simulation for maximum positive dataIn skew timing: + %d ns", `MAX_SKEW);
		`WS2811_GENERATE(ws2811In, 8'h55, `MAX_SKEW)
		`CHECK_ACTIVE(active, 1'b1)
		`WS2811_GENERATE(ws2811In, 8'hAA, `MAX_SKEW)
		`CHECK_ACTIVE(active, 1'b1)
		`WS2811_GENERATE(ws2811In, 8'h00, `MAX_SKEW)
		`CHECK_ACTIVE(active, 1'b1)
		`WS2811_GENERATE(ws2811In, 8'hFF, `MAX_SKEW)
		`CHECK_ACTIVE(active, 1'b1)
		`WS2811_GENERATE_END(ws2811In)
		`CHECK_ACTIVE(active, 1'b0)
		`CHECK_RES(8'h55, 8'hAA, 8'h00, 8'hFF)
		
		$display("ws2811Encoder: Running simulation for maximum negative dataIn skew timing: - %d ns", `MAX_SKEW);
		`WS2811_GENERATE(ws2811In, 8'h55, -`MAX_SKEW)
		`CHECK_ACTIVE(active, 1'b1)
		`WS2811_GENERATE(ws2811In, 8'hAA, -`MAX_SKEW)
		`CHECK_ACTIVE(active, 1'b1)
		`WS2811_GENERATE(ws2811In, 8'h00, -`MAX_SKEW)
		`CHECK_ACTIVE(active, 1'b1)
		`WS2811_GENERATE(ws2811In, 8'hFF, -`MAX_SKEW)
		`CHECK_ACTIVE(active, 1'b1)
		`WS2811_GENERATE_END(ws2811In)
		`CHECK_ACTIVE(active, 1'b0)
		`CHECK_RES(8'h55, 8'hAA, 8'h00, 8'hFF)
		#50000
		`CHECK_ACTIVE(active, 1'b0)
		`CHECK_RES(8'h55, 8'hAA, 8'h00, 8'hFF)

		$display("ws2811Encoder: Simulation successfull - stopping");
		$stop;
	end
endmodule
module ws2811Encoder_TB ();

	wire masterClk;
	reg ws2811In;
	wire unModulatedIn;
	wire dataClkIn;
	wire ws2811Out;
	wire unmodulatedOut;
	wire dataClkOut;
	wire active;

	reg[7:0] result_0;
	reg[7:0] result_1;
	reg[7:0] result_2;
	reg[7:0] result_3;

	integer shiftIndex, valIndex;

	ws2811Decoder GENERATOR(.masterClk(masterClk), .dataIn(ws2811In), .dataOut(unModulatedIn), .dataClk(dataClkIn), .active());
	ws2811Encoder DUT(.masterClk(masterClk), .dataClk(dataClkIn), .dataIn(unModulatedIn), .dataOut(ws2811Out));
	ws2811Decoder RECEIVER(.masterClk(masterClk), .dataIn(ws2811Out), .dataOut(unmodulatedOut), .dataClk(dataClkOut), .active(active));
	OSCH #(.NOM_FREQ(`OSCH_FREQ)) internal_oscillator_inst (.STDBY(1'b0), .OSC(masterClk), .SEDSTDBY ());

	always @(posedge dataClkOut) begin

		for(shiftIndex=7; shiftIndex>=0; shiftIndex=shiftIndex-1) begin
			if(shiftIndex != 0) begin
				result_3[shiftIndex] <= result_3[shiftIndex-1];
				result_2[shiftIndex] <= result_2[shiftIndex-1];
				result_1[shiftIndex] <= result_1[shiftIndex-1];
				result_0[shiftIndex] <= result_0[shiftIndex-1];
			end
			else begin
				result_3[0] <= result_2[7];
				result_2[0] <= result_1[7];
				result_1[0] <= result_0[7];
				result_0[0] <= unmodulatedOut;
			end
		end
	end
	
	initial begin
		$display("ws2811Encoder: Initializing simulation for ws2811Encoder");

		$display("ws2811Encoder: Running simulation for nominal dataIn timing, T1H: %d, T1L %d, T0H: %d, T0L", 600, 1240-600, 250, 1240-250);
		`WS2811_GENERATE(ws2811In, 8'hF0, 0)
		`WS2811_GENERATE_END(ws2811In)

		`WS2811_GENERATE(ws2811In, 8'h55, 0)
		`CHECK_ACTIVE(active, 1'b1)
		`WS2811_GENERATE(ws2811In, 8'hAA, 0)
		`CHECK_ACTIVE(active, 1'b1)
		`WS2811_GENERATE(ws2811In, 8'h00, 0)
		`CHECK_ACTIVE(active, 1'b1)
		`WS2811_GENERATE(ws2811In, 8'hFF, 0)
		`CHECK_ACTIVE(active, 1'b1)
		`WS2811_GENERATE_END(ws2811In)
		`CHECK_ACTIVE(active, 1'b0)
		`CHECK_RES(8'h55, 8'hAA, 8'h00, 8'hFF)

		$display("ws2811Encoder: Running simulation for maximum positive dataIn skew timing: + %d ns", `MAX_SKEW);
		`WS2811_GENERATE(ws2811In, 8'h55, `MAX_SKEW)
		`CHECK_ACTIVE(active, 1'b1)
		`WS2811_GENERATE(ws2811In, 8'hAA, `MAX_SKEW)
		`CHECK_ACTIVE(active, 1'b1)
		`WS2811_GENERATE(ws2811In, 8'h00, `MAX_SKEW)
		`CHECK_ACTIVE(active, 1'b1)
		`WS2811_GENERATE(ws2811In, 8'hFF, `MAX_SKEW)
		`CHECK_ACTIVE(active, 1'b1)
		`WS2811_GENERATE_END(ws2811In)
		`CHECK_ACTIVE(active, 1'b0)
		`CHECK_RES(8'h55, 8'hAA, 8'h00, 8'hFF)
		
		$display("ws2811Encoder: Running simulation for maximum negative dataIn skew timing: - %d ns", `MAX_SKEW);
		`WS2811_GENERATE(ws2811In, 8'h55, -`MAX_SKEW)
		`CHECK_ACTIVE(active, 1'b1)
		`WS2811_GENERATE(ws2811In, 8'hAA, -`MAX_SKEW)
		`CHECK_ACTIVE(active, 1'b1)
		`WS2811_GENERATE(ws2811In, 8'h00, -`MAX_SKEW)
		`CHECK_ACTIVE(active, 1'b1)
		`WS2811_GENERATE(ws2811In, 8'hFF, -`MAX_SKEW)
		`CHECK_ACTIVE(active, 1'b1)
		`WS2811_GENERATE_END(ws2811In)
		`CHECK_ACTIVE(active, 1'b0)
		`CHECK_RES(8'h55, 8'hAA, 8'h00, 8'hFF)
		#50000
		`CHECK_ACTIVE(active, 1'b0)
		`CHECK_RES(8'h55, 8'hAA, 8'h00, 8'hFF)

		$display("ws2811Encoder: Simulation successfull - stopping");
		$stop;
	end
endmodule