data/full_repos/permissive/418284997/src/blocks/bitwise_mux.v
data/verilator_xmls/7979f209-86ce-4083-966a-1d5fd30340f2.xml
module bitwise_mux
  #(
    parameter LENGTH = 8
  )
  (
    input wire [LENGTH-1:0] data1_i,
    input wire [LENGTH-1:0] data2_i,
    input wire [LENGTH-1:0] select,
    output wire [LENGTH-1:0] data_o
  );

  genvar i;
  generate
    for (i = 0; i < LENGTH; i = i + 1) begin
      assign data_o[i] = select[i] ? data2_i[i] : data1_i[i];
    end
  endgenerate

endmodule
module bitwise_mux
  #(
    parameter LENGTH = 8
  )
  (
    input wire [LENGTH-1:0] data1_i,
    input wire [LENGTH-1:0] data2_i,
    input wire [LENGTH-1:0] select,
    output wire [LENGTH-1:0] data_o
  );


  genvar i;
  generate
    for (i = 0; i < LENGTH; i = i + 1) begin
      assign data_o[i] = select[i] ? data2_i[i] : data1_i[i];
    end
  endgenerate

endmodule