data/full_repos/permissive/496325532/vga_playground/sv/vga_ctrl.sv
1: b'%Error: data/full_repos/permissive/496325532/vga_playground/sv/vga_ctrl.sv:1: Cannot find include file: definitions.sv\n`include "definitions.sv" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/496325532/vga_playground/sv,data/full_repos/permissive/496325532/definitions.sv\n             data/full_repos/permissive/496325532/vga_playground/sv,data/full_repos/permissive/496325532/definitions.sv.v\n             data/full_repos/permissive/496325532/vga_playground/sv,data/full_repos/permissive/496325532/definitions.sv.sv\n             definitions.sv\n             definitions.sv.v\n             definitions.sv.sv\n             obj_dir/definitions.sv\n             obj_dir/definitions.sv.v\n             obj_dir/definitions.sv.sv\n%Error: data/full_repos/permissive/496325532/vga_playground/sv/vga_ctrl.sv:45: Define or directive not defined: \'`MSFF\'\n`MSFF(SampleReset[4:1], SampleReset[3:0], CLK_50)\n^~~~~\n%Error: data/full_repos/permissive/496325532/vga_playground/sv/vga_ctrl.sv:45: syntax error, unexpected \'(\'\n`MSFF(SampleReset[4:1], SampleReset[3:0], CLK_50)\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/496325532/vga_playground/sv/vga_ctrl.sv:74: Define or directive not defined: \'`MSFF\'\n`MSFF( LineQ1    , LineQ0    , CLK_25)\n^~~~~\n%Error: data/full_repos/permissive/496325532/vga_playground/sv/vga_ctrl.sv:74: syntax error, unexpected \'(\'\n`MSFF( LineQ1    , LineQ0    , CLK_25)\n       ^~~~~~\n%Error: data/full_repos/permissive/496325532/vga_playground/sv/vga_ctrl.sv:85: Define or directive not defined: \'`EN_RST_MSFF\'\n`EN_RST_MSFF(CountBitOffsetQ1 , (CountBitOffsetQ1 +1), CLK_25, EnCountBitOffset , RstCountBitOffset )\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/496325532/vga_playground/sv/vga_ctrl.sv:85: syntax error, unexpected \'(\'\n`EN_RST_MSFF(CountBitOffsetQ1 , (CountBitOffsetQ1 +1), CLK_25, EnCountBitOffset , RstCountBitOffset )\n             ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496325532/vga_playground/sv/vga_ctrl.sv:86: Define or directive not defined: \'`EN_RST_MSFF\'\n`EN_RST_MSFF(CountByteOffsetQ1, (CountByteOffsetQ1+1), CLK_25, EnCountByteOffset, RstCountByteOffset)\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/496325532/vga_playground/sv/vga_ctrl.sv:87: Define or directive not defined: \'`EN_RST_MSFF\'\n`EN_RST_MSFF(CountWordOffsetQ1, (CountWordOffsetQ1+1), CLK_25, EnCountWordOffset, RstCountWordOffset)\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/496325532/vga_playground/sv/vga_ctrl.sv:91: Define or directive not defined: \'`MSFF\'\n`MSFF(CountBitOffsetQ2,  CountBitOffsetQ1,  CLK_25)\n^~~~~\n%Error: data/full_repos/permissive/496325532/vga_playground/sv/vga_ctrl.sv:92: Define or directive not defined: \'`MSFF\'\n`MSFF(CountByteOffsetQ2, CountByteOffsetQ1, CLK_25)\n^~~~~\n%Error: data/full_repos/permissive/496325532/vga_playground/sv/vga_ctrl.sv:118: Define or directive not defined: \'`MSFF\'\n`MSFF(RED    , NextRED     , CLK_25)\n^~~~~\n%Error: data/full_repos/permissive/496325532/vga_playground/sv/vga_ctrl.sv:118: syntax error, unexpected \'(\'\n`MSFF(RED    , NextRED     , CLK_25)\n      ^~~\n%Error: data/full_repos/permissive/496325532/vga_playground/sv/vga_ctrl.sv:119: Define or directive not defined: \'`MSFF\'\n`MSFF(GREEN  , NextGREEN   , CLK_25)\n^~~~~\n%Error: data/full_repos/permissive/496325532/vga_playground/sv/vga_ctrl.sv:120: Define or directive not defined: \'`MSFF\'\n`MSFF(BLUE   , NextBLUE    , CLK_25)\n^~~~~\n%Error: data/full_repos/permissive/496325532/vga_playground/sv/vga_ctrl.sv:121: Define or directive not defined: \'`MSFF\'\n`MSFF(h_sync , next_h_sync , CLK_25)\n^~~~~\n%Error: data/full_repos/permissive/496325532/vga_playground/sv/vga_ctrl.sv:122: Define or directive not defined: \'`MSFF\'\n`MSFF(v_sync , next_v_sync , CLK_25)\n^~~~~\n%Error: Cannot continue\n'
module vga_ctrl(
        input  logic        CLK_50,
        input  logic        Reset,

        input  logic [31:0] WrData,
        input  logic [12:0] WrAddress,
        input  logic        WrEn,

        output logic [3:0]  RED,
        output logic [3:0]  GREEN,
        output logic [3:0]  BLUE,
        output logic        h_sync,
        output logic        v_sync
    );

`ifndef SIMULATION_ON
    `define FPGA_ON    
`endif
logic [9:0]  pixel_y;
logic        CLK_25;
logic        inDisplayArea;
logic        next_h_sync;
logic        next_v_sync;
logic [3:0]  NextRED;
logic [3:0]  NextGREEN;
logic [3:0]  NextBLUE;
logic        CurentPixelQ2;

logic [8:0]          LineQ0, LineQ1;
logic [31:0] RdDataQ2;
logic [4:0] SampleReset;
logic [6:0] HEX; 
logic [12:0]WordOffsetQ1;
logic [2:0] CountBitOffsetQ1, CountBitOffsetQ2 ;
logic [1:0] CountByteOffsetQ1, CountByteOffsetQ2;
logic [7:0] CountWordOffsetQ1;
logic       EnCountBitOffset,  EnCountByteOffset,  EnCountWordOffset ;
logic       RstCountBitOffset, RstCountByteOffset, RstCountWordOffset;




assign SampleReset[0] = Reset;
`MSFF(SampleReset[4:1], SampleReset[3:0], CLK_50)



`ifdef SIMULATION_ON
    `RST_MSFF(CLK_25, !CLK_25, CLK_50, Reset)
`elsif FPGA_ON
pll_2 pll_2 (
    .inclk0 (CLK_50),
    .c0     (CLK_25)
); 
`endif




sync_gen sync_inst(
    .CLK_25         (CLK_25),
    .Reset          (SampleReset[4]),
    .vga_h_sync     (next_h_sync),
    .vga_v_sync     (next_v_sync),
    .CounterX       (),
    .CounterY       (pixel_y),
    .inDisplayArea  (inDisplayArea)
);



assign LineQ0   = pixel_y[8:0];
`MSFF( LineQ1    , LineQ0    , CLK_25)




assign EnCountBitOffset   = 1'b1;
assign EnCountByteOffset  = ((CountWordOffsetQ1 == 79) && EnCountWordOffset);
assign EnCountWordOffset  = (CountBitOffsetQ1 == 3'b111);
assign RstCountBitOffset  = SampleReset[4] || (!inDisplayArea);
assign RstCountByteOffset = SampleReset[4];
assign RstCountWordOffset = SampleReset[4] || ((CountWordOffsetQ1 == 79) && EnCountWordOffset);
`EN_RST_MSFF(CountBitOffsetQ1 , (CountBitOffsetQ1 +1), CLK_25, EnCountBitOffset , RstCountBitOffset )
`EN_RST_MSFF(CountByteOffsetQ1, (CountByteOffsetQ1+1), CLK_25, EnCountByteOffset, RstCountByteOffset)
`EN_RST_MSFF(CountWordOffsetQ1, (CountWordOffsetQ1+1), CLK_25, EnCountWordOffset, RstCountWordOffset)

assign WordOffsetQ1 = ((LineQ1[8:2])*80 + CountWordOffsetQ1);

`MSFF(CountBitOffsetQ2,  CountBitOffsetQ1,  CLK_25)
`MSFF(CountByteOffsetQ2, CountByteOffsetQ1, CLK_25)

assign CurentPixelQ2 = RdDataQ2[{CountByteOffsetQ2,CountBitOffsetQ2}];





`ifdef SIMULATION_ON
ram2port_sim ram2port_sim (
`else
ram2port ram2port (
`endif
	.clock     (CLK_25),

	.data      (WrData),
	.wraddress (WrAddress),
	.wren      (WrEn),

    .rdaddress (WordOffsetQ1),
	.q         (RdDataQ2)
);

assign NextRED   = (inDisplayArea) ? {4{CurentPixelQ2}} : '0;
assign NextGREEN = (inDisplayArea) ? {4{CurentPixelQ2}} : '0;
assign NextBLUE  = (inDisplayArea) ? {4{CurentPixelQ2}} : '0;
`MSFF(RED    , NextRED     , CLK_25)
`MSFF(GREEN  , NextGREEN   , CLK_25)
`MSFF(BLUE   , NextBLUE    , CLK_25)
`MSFF(h_sync , next_h_sync , CLK_25)
`MSFF(v_sync , next_v_sync , CLK_25)

endmodule
module vga_ctrl(
        input  logic        CLK_50,
        input  logic        Reset,

        input  logic [31:0] WrData,
        input  logic [12:0] WrAddress,
        input  logic        WrEn,

        output logic [3:0]  RED,
        output logic [3:0]  GREEN,
        output logic [3:0]  BLUE,
        output logic        h_sync,
        output logic        v_sync
    );


`ifndef SIMULATION_ON
    `define FPGA_ON    
`endif
logic [9:0]  pixel_y;
logic        CLK_25;
logic        inDisplayArea;
logic        next_h_sync;
logic        next_v_sync;
logic [3:0]  NextRED;
logic [3:0]  NextGREEN;
logic [3:0]  NextBLUE;
logic        CurentPixelQ2;

logic [8:0]          LineQ0, LineQ1;
logic [31:0] RdDataQ2;
logic [4:0] SampleReset;
logic [6:0] HEX; 
logic [12:0]WordOffsetQ1;
logic [2:0] CountBitOffsetQ1, CountBitOffsetQ2 ;
logic [1:0] CountByteOffsetQ1, CountByteOffsetQ2;
logic [7:0] CountWordOffsetQ1;
logic       EnCountBitOffset,  EnCountByteOffset,  EnCountWordOffset ;
logic       RstCountBitOffset, RstCountByteOffset, RstCountWordOffset;




assign SampleReset[0] = Reset;
`MSFF(SampleReset[4:1], SampleReset[3:0], CLK_50)



`ifdef SIMULATION_ON
    `RST_MSFF(CLK_25, !CLK_25, CLK_50, Reset)
`elsif FPGA_ON
pll_2 pll_2 (
    .inclk0 (CLK_50),
    .c0     (CLK_25)
); 
`endif




sync_gen sync_inst(
    .CLK_25         (CLK_25),
    .Reset          (SampleReset[4]),
    .vga_h_sync     (next_h_sync),
    .vga_v_sync     (next_v_sync),
    .CounterX       (),
    .CounterY       (pixel_y),
    .inDisplayArea  (inDisplayArea)
);



assign LineQ0   = pixel_y[8:0];
`MSFF( LineQ1    , LineQ0    , CLK_25)




assign EnCountBitOffset   = 1'b1;
assign EnCountByteOffset  = ((CountWordOffsetQ1 == 79) && EnCountWordOffset);
assign EnCountWordOffset  = (CountBitOffsetQ1 == 3'b111);
assign RstCountBitOffset  = SampleReset[4] || (!inDisplayArea);
assign RstCountByteOffset = SampleReset[4];
assign RstCountWordOffset = SampleReset[4] || ((CountWordOffsetQ1 == 79) && EnCountWordOffset);
`EN_RST_MSFF(CountBitOffsetQ1 , (CountBitOffsetQ1 +1), CLK_25, EnCountBitOffset , RstCountBitOffset )
`EN_RST_MSFF(CountByteOffsetQ1, (CountByteOffsetQ1+1), CLK_25, EnCountByteOffset, RstCountByteOffset)
`EN_RST_MSFF(CountWordOffsetQ1, (CountWordOffsetQ1+1), CLK_25, EnCountWordOffset, RstCountWordOffset)

assign WordOffsetQ1 = ((LineQ1[8:2])*80 + CountWordOffsetQ1);

`MSFF(CountBitOffsetQ2,  CountBitOffsetQ1,  CLK_25)
`MSFF(CountByteOffsetQ2, CountByteOffsetQ1, CLK_25)

assign CurentPixelQ2 = RdDataQ2[{CountByteOffsetQ2,CountBitOffsetQ2}];





`ifdef SIMULATION_ON
ram2port_sim ram2port_sim (
`else
ram2port ram2port (
`endif
	.clock     (CLK_25),

	.data      (WrData),
	.wraddress (WrAddress),
	.wren      (WrEn),

    .rdaddress (WordOffsetQ1),
	.q         (RdDataQ2)
);

assign NextRED   = (inDisplayArea) ? {4{CurentPixelQ2}} : '0;
assign NextGREEN = (inDisplayArea) ? {4{CurentPixelQ2}} : '0;
assign NextBLUE  = (inDisplayArea) ? {4{CurentPixelQ2}} : '0;
`MSFF(RED    , NextRED     , CLK_25)
`MSFF(GREEN  , NextGREEN   , CLK_25)
`MSFF(BLUE   , NextBLUE    , CLK_25)
`MSFF(h_sync , next_h_sync , CLK_25)
`MSFF(v_sync , next_v_sync , CLK_25)

endmodule