data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:29: Cannot find include file: sys.h\n`include "sys.h" // system level definition file which contains the  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:31: Cannot find include file: iop.h\n`include        "iop.h" \n                ^~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:73: Define or directive not defined: \'`UCB_64PAY_PKT_WIDTH\'\n   input [`UCB_64PAY_PKT_WIDTH-1:0]bounce_ack_packet; \n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:76: Define or directive not defined: \'`CLK_IOB_WIDTH\'\n   input [`CLK_IOB_WIDTH-1:0]clk_iob_data;  \n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:84: Define or directive not defined: \'`IOB_CPU_WIDTH\'\n   input [`IOB_CPU_WIDTH-1:0]cpx_iob_grant_cx2;  \n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:86: Define or directive not defined: \'`IOB_INT_VEC_WIDTH\'\n   input [`IOB_INT_VEC_WIDTH-1:0]creg_jintv_vec; \n          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:87: Define or directive not defined: \'`DRAM_IOB_WIDTH\'\n   input [`DRAM_IOB_WIDTH-1:0]dram02_iob_data;  \n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:89: Define or directive not defined: \'`DRAM_IOB_WIDTH\'\n   input [`DRAM_IOB_WIDTH-1:0]dram13_iob_data;  \n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:91: Define or directive not defined: \'`IOB_CPU_WIDTH\'\n   input [`IOB_CPU_WIDTH-1:0]first_availcore;  \n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:96: Define or directive not defined: \'`UCB_64PAY_PKT_WIDTH\'\n   input [`UCB_64PAY_PKT_WIDTH-1:0]iob_int_ack_packet; \n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:98: Define or directive not defined: \'`UCB_64PAY_PKT_WIDTH\'\n   input [`UCB_64PAY_PKT_WIDTH-1:0]iob_man_ack_packet; \n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:100: Define or directive not defined: \'`UCB_INT_PKT_WIDTH\'\n   input [`UCB_INT_PKT_WIDTH-1:0]iob_man_int_packet; \n          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:102: Define or directive not defined: \'`JBI_IOB_MONDO_BUS_WIDTH\'\n   input [`JBI_IOB_MONDO_BUS_WIDTH-1:0]jbi_iob_mondo_data; \n          ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:104: Define or directive not defined: \'`JBI_IOB_WIDTH\'\n   input [`JBI_IOB_WIDTH-1:0]jbi_iob_pio_data;  \n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:106: Define or directive not defined: \'`SPI_IOB_WIDTH\'\n   input [`SPI_IOB_WIDTH-1:0]jbi_iob_spi_data;  \n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:108: Define or directive not defined: \'`IOB_CPUTHR_WIDTH\'\n   input [`IOB_CPUTHR_WIDTH-1:0]mondo_busy_vec_f; \n          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:109: Define or directive not defined: \'`UCB_NOPAY_PKT_WIDTH\'\n   input [`UCB_NOPAY_PKT_WIDTH-1:0]rd_nack_packet; \n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:116: Define or directive not defined: \'`IOB_IO_BUF_WIDTH\'\n   input [`IOB_IO_BUF_WIDTH-1:0]wr_ack_io_buf_din; \n          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:123: Define or directive not defined: \'`IOB_INT_BUF_INDEX\'\n   output [`IOB_INT_BUF_INDEX-1:0]int_buf_head_ptr; \n           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:125: Define or directive not defined: \'`IOB_INT_BUF_INDEX\'\n   output [`IOB_INT_BUF_INDEX-1:0]int_buf_tail_ptr; \n           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:130: Define or directive not defined: \'`IOB_IO_BUF_INDEX\'\n   output [`IOB_IO_BUF_INDEX-1:0]io_buf_head_ptr; \n           ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:131: Define or directive not defined: \'`IOB_IO_BUF_INDEX\'\n   output [`IOB_IO_BUF_INDEX-1:0]io_buf_tail_ptr; \n           ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:133: Define or directive not defined: \'`IOB_INT_TAB_INDEX\'\n   output [`IOB_INT_TAB_INDEX-1:0]io_intman_addr; \n           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:136: Define or directive not defined: \'`IOB_CPUTHR_INDEX\'\n   output [`IOB_CPUTHR_INDEX-1:0]io_mondo_data_wr_addr_s; \n           ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:138: Define or directive not defined: \'`JBI_IOB_MONDO_SRC_WIDTH\'\n   output [`JBI_IOB_MONDO_SRC_WIDTH-1:0]io_mondo_source_din_s; \n           ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:140: Define or directive not defined: \'`CPX_WIDTH\'\n   output [`CPX_WIDTH-1:0]iob_cpx_data_ca;  \n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:141: Define or directive not defined: \'`IOB_CPU_WIDTH\'\n   output [`IOB_CPU_WIDTH-1:0]iob_cpx_req_cq;  \n           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:151: Define or directive not defined: \'`IOB_TAP_WIDTH\'\n   output [`IOB_TAP_WIDTH-1:0]iob_tap_data;  \n           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:161: Define or directive not defined: \'`UCB_128PAY_PKT_WIDTH\'\n   wire [`UCB_128PAY_PKT_WIDTH-1:0]ack_packet_d1; \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:162: Define or directive not defined: \'`IOB_ACK_AVEC_WIDTH\'\n   wire [`IOB_ACK_AVEC_WIDTH-1:0]ack_sel;  \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:164: Define or directive not defined: \'`UCB_64PAY_PKT_WIDTH\'\n   wire [`UCB_64PAY_PKT_WIDTH-1:0]clk_ack_packet; \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:167: Define or directive not defined: \'`UCB_INT_PKT_WIDTH\'\n   wire [`UCB_INT_PKT_WIDTH-1:0]clk_int_packet;  \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:170: Define or directive not defined: \'`UCB_64PAY_PKT_WIDTH\'\n   wire [`UCB_64PAY_PKT_WIDTH-1:0]dram0_ack_packet; \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:173: Define or directive not defined: \'`UCB_INT_PKT_WIDTH\'\n   wire [`UCB_INT_PKT_WIDTH-1:0]dram0_int_packet; \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:176: Define or directive not defined: \'`UCB_64PAY_PKT_WIDTH\'\n   wire [`UCB_64PAY_PKT_WIDTH-1:0]dram1_ack_packet; \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:179: Define or directive not defined: \'`UCB_INT_PKT_WIDTH\'\n   wire [`UCB_INT_PKT_WIDTH-1:0]dram1_int_packet; \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:182: Define or directive not defined: \'`IOB_CPU_WIDTH\'\n   wire [`IOB_CPU_WIDTH-1:0]int_buf_cpx_req;  \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:185: Define or directive not defined: \'`IOB_INT_AVEC_WIDTH\'\n   wire [`IOB_INT_AVEC_WIDTH-1:0]int_sel;  \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:186: Define or directive not defined: \'`IOB_CPU_WIDTH\'\n   wire [`IOB_CPU_WIDTH-1:0]io_buf_cpx_req;  \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:187: Define or directive not defined: \'`IOB_IO_BUF_INDEX\'\n   wire [`IOB_IO_BUF_INDEX:0]io_buf_head_f;  \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:187: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   wire [`IOB_IO_BUF_INDEX:0]io_buf_head_f;  \n                          ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:190: Define or directive not defined: \'`IOB_IO_BUF_INDEX\'\n   wire [`IOB_IO_BUF_INDEX:0]io_buf_tail_s;  \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:190: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   wire [`IOB_IO_BUF_INDEX:0]io_buf_tail_s;  \n                          ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:191: Define or directive not defined: \'`IOB_CPU_WIDTH\'\n   wire [`IOB_CPU_WIDTH-1:0]iob_cpx_req_next;  \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:192: Define or directive not defined: \'`UCB_64PAY_PKT_WIDTH\'\n   wire [`UCB_64PAY_PKT_WIDTH-1:0]iob_tap_packet; \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:194: Define or directive not defined: \'`UCB_128PAY_PKT_WIDTH\'\n   wire [`UCB_128PAY_PKT_WIDTH-1:0]jbi_ack_packet; \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:197: Define or directive not defined: \'`UCB_INT_PKT_WIDTH\'\n   wire [`UCB_INT_PKT_WIDTH-1:0]jbi_int_packet;  \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:203: Define or directive not defined: \'`JBI_IOB_MONDO_SRC_WIDTH\'\n   wire [`JBI_IOB_MONDO_SRC_WIDTH-1:0]jbi_mondo_source; \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:204: Define or directive not defined: \'`JBI_IOB_MONDO_TRG_WIDTH\'\n   wire [`JBI_IOB_MONDO_TRG_WIDTH-1:0]jbi_mondo_target; \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/i2c.v:207: Define or directive not defined: \'`UCB_64PAY_PKT_WIDTH\'\n   wire [`UCB_64PAY_PKT_WIDTH-1:0]spi_ack_packet; \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module i2c (

   rd_nack_rd, iob_tap_vld, iob_tap_data, iob_man_int_rd, 
   iob_man_ack_rd, iob_jbi_spi_stall, iob_jbi_pio_stall, 
   iob_jbi_mondo_nack, iob_jbi_mondo_ack, iob_int_ack_rd, 
   iob_dram13_stall, iob_dram02_stall, iob_cpx_req_cq, 
   iob_cpx_data_ca, iob_clk_stall, io_mondo_source_din_s, 
   io_mondo_data_wr_s, io_mondo_data_wr_addr_s, io_mondo_data1_din_s, 
   io_mondo_data0_din_s, io_intman_addr, io_buf_wr, io_buf_tail_ptr, 
   io_buf_head_ptr, io_buf_din_raw, io_buf_avail, int_srvcd, 
   int_buf_wr, int_buf_tail_ptr, int_buf_hit_hwm, int_buf_head_ptr, 
   bounce_ack_rd, int_srvcd_d1, 

   wr_ack_io_buf_din, tx_sync, tap_iob_stall, srvc_wr_ack, rx_sync, 
   rst_l, rd_nack_vld, rd_nack_packet, mondo_busy_vec_f, 
   jbi_iob_spi_vld, jbi_iob_spi_data, jbi_iob_pio_vld, 
   jbi_iob_pio_data, jbi_iob_mondo_vld, jbi_iob_mondo_data, 
   iob_man_int_vld, iob_man_int_packet, iob_man_ack_vld, 
   iob_man_ack_packet, iob_int_ack_vld, iob_int_ack_packet, 
   io_buf_dout_raw, int_vec_dout_raw, int_cpu_dout_raw, 
   int_buf_dout_raw, first_availcore, dram13_iob_vld, 
   dram13_iob_data, dram02_iob_vld, dram02_iob_data, creg_jintv_vec, 
   creg_intctrl_mask, cpx_iob_grant_cx2, cpu_rst_l, cpu_mondo_wr_d2, 
   cpu_mondo_rd_d2, cpu_intman_acc, cpu_intctrl_acc, cpu_clk, 
   clk_iob_vld, clk_iob_data, clk, bounce_ack_vld, bounce_ack_packet
   );
   





   input [`UCB_64PAY_PKT_WIDTH-1:0]bounce_ack_packet;
   input		bounce_ack_vld;
   input		clk;
   input [`CLK_IOB_WIDTH-1:0]clk_iob_data;
   input		clk_iob_vld;
   input		cpu_clk;
   input		cpu_intctrl_acc;
   input		cpu_intman_acc;
   input		cpu_mondo_rd_d2;
   input		cpu_mondo_wr_d2;
   input		cpu_rst_l;
   input [`IOB_CPU_WIDTH-1:0]cpx_iob_grant_cx2;
   input		creg_intctrl_mask;
   input [`IOB_INT_VEC_WIDTH-1:0]creg_jintv_vec;
   input [`DRAM_IOB_WIDTH-1:0]dram02_iob_data;
   input		dram02_iob_vld;
   input [`DRAM_IOB_WIDTH-1:0]dram13_iob_data;
   input		dram13_iob_vld;
   input [`IOB_CPU_WIDTH-1:0]first_availcore;
   input [159:0]	int_buf_dout_raw;
   input [14:0]		int_cpu_dout_raw;
   input [14:0]		int_vec_dout_raw;
   input [159:0]	io_buf_dout_raw;
   input [`UCB_64PAY_PKT_WIDTH-1:0]iob_int_ack_packet;
   input		iob_int_ack_vld;
   input [`UCB_64PAY_PKT_WIDTH-1:0]iob_man_ack_packet;
   input		iob_man_ack_vld;
   input [`UCB_INT_PKT_WIDTH-1:0]iob_man_int_packet;
   input		iob_man_int_vld;
   input [`JBI_IOB_MONDO_BUS_WIDTH-1:0]jbi_iob_mondo_data;
   input		jbi_iob_mondo_vld;
   input [`JBI_IOB_WIDTH-1:0]jbi_iob_pio_data;
   input		jbi_iob_pio_vld;
   input [`SPI_IOB_WIDTH-1:0]jbi_iob_spi_data;
   input		jbi_iob_spi_vld;
   input [`IOB_CPUTHR_WIDTH-1:0]mondo_busy_vec_f;
   input [`UCB_NOPAY_PKT_WIDTH-1:0]rd_nack_packet;
   input		rd_nack_vld;
   input		rst_l;
   input		rx_sync;
   input		srvc_wr_ack;
   input		tap_iob_stall;
   input		tx_sync;
   input [`IOB_IO_BUF_WIDTH-1:0]wr_ack_io_buf_din;


   


   output		bounce_ack_rd;
   output [`IOB_INT_BUF_INDEX-1:0]int_buf_head_ptr;
   output		int_buf_hit_hwm;
   output [`IOB_INT_BUF_INDEX-1:0]int_buf_tail_ptr;
   output		int_buf_wr;
   output		int_srvcd;
   output		io_buf_avail;
   output [159:0]	io_buf_din_raw;
   output [`IOB_IO_BUF_INDEX-1:0]io_buf_head_ptr;
   output [`IOB_IO_BUF_INDEX-1:0]io_buf_tail_ptr;
   output		io_buf_wr;
   output [`IOB_INT_TAB_INDEX-1:0]io_intman_addr;
   output [63:0]	io_mondo_data0_din_s;
   output [63:0]	io_mondo_data1_din_s;
   output [`IOB_CPUTHR_INDEX-1:0]io_mondo_data_wr_addr_s;
   output		io_mondo_data_wr_s;
   output [`JBI_IOB_MONDO_SRC_WIDTH-1:0]io_mondo_source_din_s;
   output		iob_clk_stall;
   output [`CPX_WIDTH-1:0]iob_cpx_data_ca;
   output [`IOB_CPU_WIDTH-1:0]iob_cpx_req_cq;
   output		iob_dram02_stall;
   output		iob_dram13_stall;
   output		iob_int_ack_rd;
   output		iob_jbi_mondo_ack;
   output		iob_jbi_mondo_nack;
   output		iob_jbi_pio_stall;
   output		iob_jbi_spi_stall;
   output		iob_man_ack_rd;
   output		iob_man_int_rd;
   output [`IOB_TAP_WIDTH-1:0]iob_tap_data;
   output		iob_tap_vld;
   output		rd_nack_rd;

   

   output 		int_srvcd_d1;
   


   wire [`UCB_128PAY_PKT_WIDTH-1:0]ack_packet_d1;
   wire [`IOB_ACK_AVEC_WIDTH-1:0]ack_sel;
   wire			ack_srvcd_d1;
   wire [`UCB_64PAY_PKT_WIDTH-1:0]clk_ack_packet;
   wire			clk_ack_rd;
   wire			clk_ack_vld;
   wire [`UCB_INT_PKT_WIDTH-1:0]clk_int_packet;
   wire			clk_int_rd;
   wire			clk_int_vld;
   wire [`UCB_64PAY_PKT_WIDTH-1:0]dram0_ack_packet;
   wire			dram0_ack_rd;
   wire			dram0_ack_vld;
   wire [`UCB_INT_PKT_WIDTH-1:0]dram0_int_packet;
   wire			dram0_int_rd;
   wire			dram0_int_vld;
   wire [`UCB_64PAY_PKT_WIDTH-1:0]dram1_ack_packet;
   wire			dram1_ack_rd;
   wire			dram1_ack_vld;
   wire [`UCB_INT_PKT_WIDTH-1:0]dram1_int_packet;
   wire			dram1_int_rd;
   wire			dram1_int_vld;
   wire [`IOB_CPU_WIDTH-1:0]int_buf_cpx_req;
   wire			int_buf_rd;
   wire			int_buf_sel_next;
   wire [`IOB_INT_AVEC_WIDTH-1:0]int_sel;
   wire [`IOB_CPU_WIDTH-1:0]io_buf_cpx_req;
   wire [`IOB_IO_BUF_INDEX:0]io_buf_head_f;
   wire			io_buf_rd;
   wire			io_buf_sel_next;
   wire [`IOB_IO_BUF_INDEX:0]io_buf_tail_s;
   wire [`IOB_CPU_WIDTH-1:0]iob_cpx_req_next;
   wire [`UCB_64PAY_PKT_WIDTH-1:0]iob_tap_packet;
   wire			iob_tap_packet_vld;
   wire [`UCB_128PAY_PKT_WIDTH-1:0]jbi_ack_packet;
   wire			jbi_ack_rd;
   wire			jbi_ack_vld;
   wire [`UCB_INT_PKT_WIDTH-1:0]jbi_int_packet;
   wire			jbi_int_rd;
   wire			jbi_int_vld;
   wire [63:0]		jbi_mondo_data0;
   wire [63:0]		jbi_mondo_data1;
   wire			jbi_mondo_rd;
   wire [`JBI_IOB_MONDO_SRC_WIDTH-1:0]jbi_mondo_source;
   wire [`JBI_IOB_MONDO_TRG_WIDTH-1:0]jbi_mondo_target;
   wire			jbi_mondo_vld;
   wire			mondo_srvcd_d1;
   wire [`UCB_64PAY_PKT_WIDTH-1:0]spi_ack_packet;
   wire			spi_ack_rd;
   wire			spi_ack_vld;
   wire [`UCB_INT_PKT_WIDTH-1:0]spi_int_packet;
   wire			spi_int_rd;
   wire			spi_int_vld;
   wire			tap_iob_busy;


   




   i2c_fctrl i2c_fctrl (


			.int_buf_sel_next(int_buf_sel_next),
			.io_buf_sel_next(io_buf_sel_next),
			.int_buf_rd	(int_buf_rd),
			.io_buf_rd	(io_buf_rd),
			.int_buf_hit_hwm(int_buf_hit_hwm),
			.io_buf_head_f	(io_buf_head_f[`IOB_IO_BUF_INDEX:0]),
			.int_buf_wr	(int_buf_wr),
			.int_buf_tail_ptr(int_buf_tail_ptr[`IOB_INT_BUF_INDEX-1:0]),
			.int_buf_head_ptr(int_buf_head_ptr[`IOB_INT_BUF_INDEX-1:0]),
			.io_buf_head_ptr(io_buf_head_ptr[`IOB_IO_BUF_INDEX-1:0]),

			.cpu_rst_l	(cpu_rst_l),
			.cpu_clk	(cpu_clk),
			.tx_sync	(tx_sync),
			.rx_sync	(rx_sync),
			.cpx_iob_grant_cx2(cpx_iob_grant_cx2[`IOB_CPU_WIDTH-1:0]),
			.int_buf_cpx_req(int_buf_cpx_req[`IOB_CPU_WIDTH-1:0]),
			.io_buf_cpx_req	(io_buf_cpx_req[`IOB_CPU_WIDTH-1:0]),
			.iob_cpx_req_next(iob_cpx_req_next[`IOB_CPU_WIDTH-1:0]),
			.cpu_mondo_rd_d2(cpu_mondo_rd_d2),
			.cpu_mondo_wr_d2(cpu_mondo_wr_d2),
			.io_buf_tail_s	(io_buf_tail_s[`IOB_IO_BUF_INDEX:0]));
   
   

   i2c_fdp i2c_fdp (


		    .iob_cpx_req_cq	(iob_cpx_req_cq[`IOB_CPU_WIDTH-1:0]),
		    .iob_cpx_data_ca	(iob_cpx_data_ca[`CPX_WIDTH-1:0]),
		    .int_buf_cpx_req	(int_buf_cpx_req[`IOB_CPU_WIDTH-1:0]),
		    .io_buf_cpx_req	(io_buf_cpx_req[`IOB_CPU_WIDTH-1:0]),
		    .iob_cpx_req_next	(iob_cpx_req_next[`IOB_CPU_WIDTH-1:0]),

		    .cpu_clk		(cpu_clk),
		    .rx_sync		(rx_sync),
		    .int_buf_sel_next	(int_buf_sel_next),
		    .io_buf_sel_next	(io_buf_sel_next),
		    .int_buf_rd		(int_buf_rd),
		    .io_buf_rd		(io_buf_rd),
		    .int_buf_dout_raw	(int_buf_dout_raw[159:0]),
		    .io_buf_dout_raw	(io_buf_dout_raw[159:0]));
   


   i2c_sctrl i2c_sctrl (

			.jbi_mondo_rd	(jbi_mondo_rd),
			.jbi_int_rd	(jbi_int_rd),
			.clk_int_rd	(clk_int_rd),
			.dram0_int_rd	(dram0_int_rd),
			.dram1_int_rd	(dram1_int_rd),
			.iob_man_int_rd	(iob_man_int_rd),
			.spi_int_rd	(spi_int_rd),
			.jbi_ack_rd	(jbi_ack_rd),
			.clk_ack_rd	(clk_ack_rd),
			.dram0_ack_rd	(dram0_ack_rd),
			.dram1_ack_rd	(dram1_ack_rd),
			.iob_man_ack_rd	(iob_man_ack_rd),
			.iob_int_ack_rd	(iob_int_ack_rd),
			.spi_ack_rd	(spi_ack_rd),
			.bounce_ack_rd	(bounce_ack_rd),
			.rd_nack_rd	(rd_nack_rd),
			.int_sel	(int_sel[`IOB_INT_AVEC_WIDTH-1:0]),
			.ack_sel	(ack_sel[`IOB_ACK_AVEC_WIDTH-1:0]),
			.mondo_srvcd_d1	(mondo_srvcd_d1),
			.int_srvcd_d1	(int_srvcd_d1),
			.ack_srvcd_d1	(ack_srvcd_d1),
			.io_buf_tail_s	(io_buf_tail_s[`IOB_IO_BUF_INDEX:0]),
			.io_mondo_data_wr_s(io_mondo_data_wr_s),
			.io_buf_avail	(io_buf_avail),
			.int_srvcd	(int_srvcd),
			.io_buf_wr	(io_buf_wr),
			.io_buf_tail_ptr(io_buf_tail_ptr[`IOB_IO_BUF_INDEX-1:0]),
			.iob_tap_packet_vld(iob_tap_packet_vld),
			.iob_jbi_mondo_ack(iob_jbi_mondo_ack),
			.iob_jbi_mondo_nack(iob_jbi_mondo_nack),

			.rst_l		(rst_l),
			.clk		(clk),
			.jbi_mondo_vld	(jbi_mondo_vld),
			.jbi_mondo_target(jbi_mondo_target[`IOB_CPUTHR_INDEX-1:0]),
			.spi_int_vld	(spi_int_vld),
			.iob_man_int_vld(iob_man_int_vld),
			.dram1_int_vld	(dram1_int_vld),
			.dram0_int_vld	(dram0_int_vld),
			.clk_int_vld	(clk_int_vld),
			.jbi_int_vld	(jbi_int_vld),
			.rd_nack_vld	(rd_nack_vld),
			.bounce_ack_vld	(bounce_ack_vld),
			.spi_ack_vld	(spi_ack_vld),
			.iob_int_ack_vld(iob_int_ack_vld),
			.iob_man_ack_vld(iob_man_ack_vld),
			.dram1_ack_vld	(dram1_ack_vld),
			.dram0_ack_vld	(dram0_ack_vld),
			.clk_ack_vld	(clk_ack_vld),
			.jbi_ack_vld	(jbi_ack_vld),
			.ack_packet_d1	(ack_packet_d1[`UCB_128PAY_PKT_WIDTH-1:0]),
			.io_buf_head_f	(io_buf_head_f[`IOB_IO_BUF_INDEX:0]),
			.mondo_busy_vec_f(mondo_busy_vec_f[`IOB_CPUTHR_WIDTH-1:0]),
			.srvc_wr_ack	(srvc_wr_ack),
			.cpu_intman_acc	(cpu_intman_acc),
			.cpu_intctrl_acc(cpu_intctrl_acc),
			.creg_intctrl_mask(creg_intctrl_mask),
			.tap_iob_busy	(tap_iob_busy));
   
   

   i2c_sdp i2c_sdp (

		    .io_mondo_data_wr_addr_s(io_mondo_data_wr_addr_s[`IOB_CPUTHR_INDEX-1:0]),
		    .io_mondo_data0_din_s(io_mondo_data0_din_s[63:0]),
		    .io_mondo_data1_din_s(io_mondo_data1_din_s[63:0]),
		    .io_mondo_source_din_s(io_mondo_source_din_s[`JBI_IOB_MONDO_SRC_WIDTH-1:0]),
		    .io_intman_addr	(io_intman_addr[`IOB_INT_TAB_INDEX-1:0]),
		    .ack_packet_d1	(ack_packet_d1[`UCB_128PAY_PKT_WIDTH-1:0]),
		    .io_buf_din_raw	(io_buf_din_raw[159:0]),
		    .iob_tap_packet	(iob_tap_packet[`UCB_64PAY_PKT_WIDTH-1:0]),

		    .clk		(clk),
		    .jbi_mondo_data0	(jbi_mondo_data0[63:0]),
		    .jbi_mondo_data1	(jbi_mondo_data1[63:0]),
		    .jbi_mondo_target	(jbi_mondo_target[`IOB_CPUTHR_INDEX-1:0]),
		    .jbi_mondo_source	(jbi_mondo_source[`JBI_IOB_MONDO_SRC_WIDTH-1:0]),
		    .jbi_int_packet	(jbi_int_packet[`UCB_INT_PKT_WIDTH-1:0]),
		    .clk_int_packet	(clk_int_packet[`UCB_INT_PKT_WIDTH-1:0]),
		    .dram0_int_packet	(dram0_int_packet[`UCB_INT_PKT_WIDTH-1:0]),
		    .dram1_int_packet	(dram1_int_packet[`UCB_INT_PKT_WIDTH-1:0]),
		    .iob_man_int_packet	(iob_man_int_packet[`UCB_INT_PKT_WIDTH-1:0]),
		    .spi_int_packet	(spi_int_packet[`UCB_INT_PKT_WIDTH-1:0]),
		    .jbi_ack_packet	(jbi_ack_packet[`UCB_128PAY_PKT_WIDTH-1:0]),
		    .clk_ack_packet	(clk_ack_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
		    .dram0_ack_packet	(dram0_ack_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
		    .dram1_ack_packet	(dram1_ack_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
		    .iob_man_ack_packet	(iob_man_ack_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
		    .iob_int_ack_packet	(iob_int_ack_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
		    .spi_ack_packet	(spi_ack_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
		    .bounce_ack_packet	(bounce_ack_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
		    .rd_nack_packet	(rd_nack_packet[`UCB_NOPAY_PKT_WIDTH-1:0]),
		    .int_vec_dout_raw	(int_vec_dout_raw[14:0]),
		    .int_cpu_dout_raw	(int_cpu_dout_raw[14:0]),
		    .int_sel		(int_sel[`IOB_INT_AVEC_WIDTH-1:0]),
		    .ack_sel		(ack_sel[`IOB_ACK_AVEC_WIDTH-1:0]),
		    .mondo_srvcd_d1	(mondo_srvcd_d1),
		    .int_srvcd_d1	(int_srvcd_d1),
		    .ack_srvcd_d1	(ack_srvcd_d1),
		    .wr_ack_io_buf_din	(wr_ack_io_buf_din[`IOB_IO_BUF_WIDTH-1:0]),
		    .creg_jintv_vec	(creg_jintv_vec[`IOB_INT_VEC_WIDTH-1:0]),
		    .first_availcore	(first_availcore[`IOB_CPU_WIDTH-1:0]));
   




   ucb_bus_out #(`IOB_TAP_WIDTH,64) tap_ucb_buf
     (


      .vld				(iob_tap_vld),
      .data				(iob_tap_data[`IOB_TAP_WIDTH-1:0]),
      .outdata_buf_busy			(tap_iob_busy),

      .clk				(clk),
      .rst_l				(rst_l),
      .stall				(tap_iob_stall),
      .outdata_buf_in			(iob_tap_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
      .outdata_vec_in			({128/`IOB_TAP_WIDTH{1'b1}}),
      .outdata_buf_wr			(iob_tap_packet_vld));

   



   i2c_buf #(`JBI_IOB_WIDTH,128,`UCB_128PAY_PKT_WIDTH,`UCB_INT_PKT_WIDTH) jbi_ucb_buf
     (


      .iob_ucb_stall			(iob_jbi_pio_stall),
      .req_ack_obj			(jbi_ack_packet[`UCB_128PAY_PKT_WIDTH-1:0]),
      .req_ack_vld			(jbi_ack_vld),
      .int_obj				(jbi_int_packet[`UCB_INT_PKT_WIDTH-1:0]),
      .int_vld				(jbi_int_vld),

      .rst_l				(rst_l),
      .clk				(clk),
      .ucb_iob_vld			(jbi_iob_pio_vld),
      .ucb_iob_data			(jbi_iob_pio_data[`JBI_IOB_WIDTH-1:0]),
      .rd_req_ack_dbl_buf		(jbi_ack_rd),
      .rd_int_dbl_buf			(jbi_int_rd));

   



   i2c_buf #(`CLK_IOB_WIDTH,64,`UCB_64PAY_PKT_WIDTH,`UCB_INT_PKT_WIDTH) clk_ucb_buf
     (


      .iob_ucb_stall			(iob_clk_stall),
      .req_ack_obj			(clk_ack_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
      .req_ack_vld			(clk_ack_vld),
      .int_obj				(clk_int_packet[`UCB_INT_PKT_WIDTH-1:0]),
      .int_vld				(clk_int_vld),

      .rst_l				(rst_l),
      .clk				(clk),
      .ucb_iob_vld			(clk_iob_vld),
      .ucb_iob_data			(clk_iob_data[`CLK_IOB_WIDTH-1:0]),
      .rd_req_ack_dbl_buf		(clk_ack_rd),
      .rd_int_dbl_buf			(clk_int_rd));

   



   i2c_buf #(`DRAM_IOB_WIDTH,64,`UCB_64PAY_PKT_WIDTH,`UCB_INT_PKT_WIDTH) dram0_ucb_buf
     (


      .iob_ucb_stall			(iob_dram02_stall),
      .req_ack_obj			(dram0_ack_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
      .req_ack_vld			(dram0_ack_vld),
      .int_obj				(dram0_int_packet[`UCB_INT_PKT_WIDTH-1:0]),
      .int_vld				(dram0_int_vld),

      .rst_l				(rst_l),
      .clk				(clk),
      .ucb_iob_vld			(dram02_iob_vld),
      .ucb_iob_data			(dram02_iob_data[`DRAM_IOB_WIDTH-1:0]),
      .rd_req_ack_dbl_buf		(dram0_ack_rd),
      .rd_int_dbl_buf			(dram0_int_rd));

   



   i2c_buf #(`DRAM_IOB_WIDTH,64,`UCB_64PAY_PKT_WIDTH,`UCB_INT_PKT_WIDTH) dram1_ucb_buf
     (


      .iob_ucb_stall			(iob_dram13_stall),
      .req_ack_obj			(dram1_ack_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
      .req_ack_vld			(dram1_ack_vld),
      .int_obj				(dram1_int_packet[`UCB_INT_PKT_WIDTH-1:0]),
      .int_vld				(dram1_int_vld),

      .rst_l				(rst_l),
      .clk				(clk),
      .ucb_iob_vld			(dram13_iob_vld),
      .ucb_iob_data			(dram13_iob_data[`DRAM_IOB_WIDTH-1:0]),
      .rd_req_ack_dbl_buf		(dram1_ack_rd),
      .rd_int_dbl_buf			(dram1_int_rd));

   



   i2c_buf #(`SPI_IOB_WIDTH,64,`UCB_64PAY_PKT_WIDTH,`UCB_INT_PKT_WIDTH) spi_ucb_buf
     (


      .iob_ucb_stall			(iob_jbi_spi_stall),
      .req_ack_obj			(spi_ack_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
      .req_ack_vld			(spi_ack_vld),
      .int_obj				(spi_int_packet[`UCB_INT_PKT_WIDTH-1:0]),
      .int_vld				(spi_int_vld),

      .rst_l				(rst_l),
      .clk				(clk),
      .ucb_iob_vld			(jbi_iob_spi_vld),
      .ucb_iob_data			(jbi_iob_spi_data[`SPI_IOB_WIDTH-1:0]),
      .rd_req_ack_dbl_buf		(spi_ack_rd),
      .rd_int_dbl_buf			(spi_int_rd));

   



   iobdg_jbus_mondo_buf jbus_mondo_buf
     (


      .mondo_vld			(jbi_mondo_vld),
      .mondo_data0			(jbi_mondo_data0[63:0]),
      .mondo_data1			(jbi_mondo_data1[63:0]),
      .mondo_target			(jbi_mondo_target[`JBI_IOB_MONDO_TRG_WIDTH-1:0]),
      .mondo_source			(jbi_mondo_source[`JBI_IOB_MONDO_SRC_WIDTH-1:0]),

      .rst_l				(rst_l),
      .clk				(clk),
      .jbi_iob_vld			(jbi_iob_mondo_vld),
      .jbi_iob_data			(jbi_iob_mondo_data[`JBI_IOB_MONDO_BUS_WIDTH-1:0]),
      .rd_mondo_buf			(jbi_mondo_rd));
      
endmodule
module i2c (

   rd_nack_rd, iob_tap_vld, iob_tap_data, iob_man_int_rd, 
   iob_man_ack_rd, iob_jbi_spi_stall, iob_jbi_pio_stall, 
   iob_jbi_mondo_nack, iob_jbi_mondo_ack, iob_int_ack_rd, 
   iob_dram13_stall, iob_dram02_stall, iob_cpx_req_cq, 
   iob_cpx_data_ca, iob_clk_stall, io_mondo_source_din_s, 
   io_mondo_data_wr_s, io_mondo_data_wr_addr_s, io_mondo_data1_din_s, 
   io_mondo_data0_din_s, io_intman_addr, io_buf_wr, io_buf_tail_ptr, 
   io_buf_head_ptr, io_buf_din_raw, io_buf_avail, int_srvcd, 
   int_buf_wr, int_buf_tail_ptr, int_buf_hit_hwm, int_buf_head_ptr, 
   bounce_ack_rd, int_srvcd_d1, 

   wr_ack_io_buf_din, tx_sync, tap_iob_stall, srvc_wr_ack, rx_sync, 
   rst_l, rd_nack_vld, rd_nack_packet, mondo_busy_vec_f, 
   jbi_iob_spi_vld, jbi_iob_spi_data, jbi_iob_pio_vld, 
   jbi_iob_pio_data, jbi_iob_mondo_vld, jbi_iob_mondo_data, 
   iob_man_int_vld, iob_man_int_packet, iob_man_ack_vld, 
   iob_man_ack_packet, iob_int_ack_vld, iob_int_ack_packet, 
   io_buf_dout_raw, int_vec_dout_raw, int_cpu_dout_raw, 
   int_buf_dout_raw, first_availcore, dram13_iob_vld, 
   dram13_iob_data, dram02_iob_vld, dram02_iob_data, creg_jintv_vec, 
   creg_intctrl_mask, cpx_iob_grant_cx2, cpu_rst_l, cpu_mondo_wr_d2, 
   cpu_mondo_rd_d2, cpu_intman_acc, cpu_intctrl_acc, cpu_clk, 
   clk_iob_vld, clk_iob_data, clk, bounce_ack_vld, bounce_ack_packet
   );

   





   input [`UCB_64PAY_PKT_WIDTH-1:0]bounce_ack_packet;
   input		bounce_ack_vld;
   input		clk;
   input [`CLK_IOB_WIDTH-1:0]clk_iob_data;
   input		clk_iob_vld;
   input		cpu_clk;
   input		cpu_intctrl_acc;
   input		cpu_intman_acc;
   input		cpu_mondo_rd_d2;
   input		cpu_mondo_wr_d2;
   input		cpu_rst_l;
   input [`IOB_CPU_WIDTH-1:0]cpx_iob_grant_cx2;
   input		creg_intctrl_mask;
   input [`IOB_INT_VEC_WIDTH-1:0]creg_jintv_vec;
   input [`DRAM_IOB_WIDTH-1:0]dram02_iob_data;
   input		dram02_iob_vld;
   input [`DRAM_IOB_WIDTH-1:0]dram13_iob_data;
   input		dram13_iob_vld;
   input [`IOB_CPU_WIDTH-1:0]first_availcore;
   input [159:0]	int_buf_dout_raw;
   input [14:0]		int_cpu_dout_raw;
   input [14:0]		int_vec_dout_raw;
   input [159:0]	io_buf_dout_raw;
   input [`UCB_64PAY_PKT_WIDTH-1:0]iob_int_ack_packet;
   input		iob_int_ack_vld;
   input [`UCB_64PAY_PKT_WIDTH-1:0]iob_man_ack_packet;
   input		iob_man_ack_vld;
   input [`UCB_INT_PKT_WIDTH-1:0]iob_man_int_packet;
   input		iob_man_int_vld;
   input [`JBI_IOB_MONDO_BUS_WIDTH-1:0]jbi_iob_mondo_data;
   input		jbi_iob_mondo_vld;
   input [`JBI_IOB_WIDTH-1:0]jbi_iob_pio_data;
   input		jbi_iob_pio_vld;
   input [`SPI_IOB_WIDTH-1:0]jbi_iob_spi_data;
   input		jbi_iob_spi_vld;
   input [`IOB_CPUTHR_WIDTH-1:0]mondo_busy_vec_f;
   input [`UCB_NOPAY_PKT_WIDTH-1:0]rd_nack_packet;
   input		rd_nack_vld;
   input		rst_l;
   input		rx_sync;
   input		srvc_wr_ack;
   input		tap_iob_stall;
   input		tx_sync;
   input [`IOB_IO_BUF_WIDTH-1:0]wr_ack_io_buf_din;


   


   output		bounce_ack_rd;
   output [`IOB_INT_BUF_INDEX-1:0]int_buf_head_ptr;
   output		int_buf_hit_hwm;
   output [`IOB_INT_BUF_INDEX-1:0]int_buf_tail_ptr;
   output		int_buf_wr;
   output		int_srvcd;
   output		io_buf_avail;
   output [159:0]	io_buf_din_raw;
   output [`IOB_IO_BUF_INDEX-1:0]io_buf_head_ptr;
   output [`IOB_IO_BUF_INDEX-1:0]io_buf_tail_ptr;
   output		io_buf_wr;
   output [`IOB_INT_TAB_INDEX-1:0]io_intman_addr;
   output [63:0]	io_mondo_data0_din_s;
   output [63:0]	io_mondo_data1_din_s;
   output [`IOB_CPUTHR_INDEX-1:0]io_mondo_data_wr_addr_s;
   output		io_mondo_data_wr_s;
   output [`JBI_IOB_MONDO_SRC_WIDTH-1:0]io_mondo_source_din_s;
   output		iob_clk_stall;
   output [`CPX_WIDTH-1:0]iob_cpx_data_ca;
   output [`IOB_CPU_WIDTH-1:0]iob_cpx_req_cq;
   output		iob_dram02_stall;
   output		iob_dram13_stall;
   output		iob_int_ack_rd;
   output		iob_jbi_mondo_ack;
   output		iob_jbi_mondo_nack;
   output		iob_jbi_pio_stall;
   output		iob_jbi_spi_stall;
   output		iob_man_ack_rd;
   output		iob_man_int_rd;
   output [`IOB_TAP_WIDTH-1:0]iob_tap_data;
   output		iob_tap_vld;
   output		rd_nack_rd;

   

   output 		int_srvcd_d1;
   


   wire [`UCB_128PAY_PKT_WIDTH-1:0]ack_packet_d1;
   wire [`IOB_ACK_AVEC_WIDTH-1:0]ack_sel;
   wire			ack_srvcd_d1;
   wire [`UCB_64PAY_PKT_WIDTH-1:0]clk_ack_packet;
   wire			clk_ack_rd;
   wire			clk_ack_vld;
   wire [`UCB_INT_PKT_WIDTH-1:0]clk_int_packet;
   wire			clk_int_rd;
   wire			clk_int_vld;
   wire [`UCB_64PAY_PKT_WIDTH-1:0]dram0_ack_packet;
   wire			dram0_ack_rd;
   wire			dram0_ack_vld;
   wire [`UCB_INT_PKT_WIDTH-1:0]dram0_int_packet;
   wire			dram0_int_rd;
   wire			dram0_int_vld;
   wire [`UCB_64PAY_PKT_WIDTH-1:0]dram1_ack_packet;
   wire			dram1_ack_rd;
   wire			dram1_ack_vld;
   wire [`UCB_INT_PKT_WIDTH-1:0]dram1_int_packet;
   wire			dram1_int_rd;
   wire			dram1_int_vld;
   wire [`IOB_CPU_WIDTH-1:0]int_buf_cpx_req;
   wire			int_buf_rd;
   wire			int_buf_sel_next;
   wire [`IOB_INT_AVEC_WIDTH-1:0]int_sel;
   wire [`IOB_CPU_WIDTH-1:0]io_buf_cpx_req;
   wire [`IOB_IO_BUF_INDEX:0]io_buf_head_f;
   wire			io_buf_rd;
   wire			io_buf_sel_next;
   wire [`IOB_IO_BUF_INDEX:0]io_buf_tail_s;
   wire [`IOB_CPU_WIDTH-1:0]iob_cpx_req_next;
   wire [`UCB_64PAY_PKT_WIDTH-1:0]iob_tap_packet;
   wire			iob_tap_packet_vld;
   wire [`UCB_128PAY_PKT_WIDTH-1:0]jbi_ack_packet;
   wire			jbi_ack_rd;
   wire			jbi_ack_vld;
   wire [`UCB_INT_PKT_WIDTH-1:0]jbi_int_packet;
   wire			jbi_int_rd;
   wire			jbi_int_vld;
   wire [63:0]		jbi_mondo_data0;
   wire [63:0]		jbi_mondo_data1;
   wire			jbi_mondo_rd;
   wire [`JBI_IOB_MONDO_SRC_WIDTH-1:0]jbi_mondo_source;
   wire [`JBI_IOB_MONDO_TRG_WIDTH-1:0]jbi_mondo_target;
   wire			jbi_mondo_vld;
   wire			mondo_srvcd_d1;
   wire [`UCB_64PAY_PKT_WIDTH-1:0]spi_ack_packet;
   wire			spi_ack_rd;
   wire			spi_ack_vld;
   wire [`UCB_INT_PKT_WIDTH-1:0]spi_int_packet;
   wire			spi_int_rd;
   wire			spi_int_vld;
   wire			tap_iob_busy;


   




   i2c_fctrl i2c_fctrl (


			.int_buf_sel_next(int_buf_sel_next),
			.io_buf_sel_next(io_buf_sel_next),
			.int_buf_rd	(int_buf_rd),
			.io_buf_rd	(io_buf_rd),
			.int_buf_hit_hwm(int_buf_hit_hwm),
			.io_buf_head_f	(io_buf_head_f[`IOB_IO_BUF_INDEX:0]),
			.int_buf_wr	(int_buf_wr),
			.int_buf_tail_ptr(int_buf_tail_ptr[`IOB_INT_BUF_INDEX-1:0]),
			.int_buf_head_ptr(int_buf_head_ptr[`IOB_INT_BUF_INDEX-1:0]),
			.io_buf_head_ptr(io_buf_head_ptr[`IOB_IO_BUF_INDEX-1:0]),

			.cpu_rst_l	(cpu_rst_l),
			.cpu_clk	(cpu_clk),
			.tx_sync	(tx_sync),
			.rx_sync	(rx_sync),
			.cpx_iob_grant_cx2(cpx_iob_grant_cx2[`IOB_CPU_WIDTH-1:0]),
			.int_buf_cpx_req(int_buf_cpx_req[`IOB_CPU_WIDTH-1:0]),
			.io_buf_cpx_req	(io_buf_cpx_req[`IOB_CPU_WIDTH-1:0]),
			.iob_cpx_req_next(iob_cpx_req_next[`IOB_CPU_WIDTH-1:0]),
			.cpu_mondo_rd_d2(cpu_mondo_rd_d2),
			.cpu_mondo_wr_d2(cpu_mondo_wr_d2),
			.io_buf_tail_s	(io_buf_tail_s[`IOB_IO_BUF_INDEX:0]));
   
   

   i2c_fdp i2c_fdp (


		    .iob_cpx_req_cq	(iob_cpx_req_cq[`IOB_CPU_WIDTH-1:0]),
		    .iob_cpx_data_ca	(iob_cpx_data_ca[`CPX_WIDTH-1:0]),
		    .int_buf_cpx_req	(int_buf_cpx_req[`IOB_CPU_WIDTH-1:0]),
		    .io_buf_cpx_req	(io_buf_cpx_req[`IOB_CPU_WIDTH-1:0]),
		    .iob_cpx_req_next	(iob_cpx_req_next[`IOB_CPU_WIDTH-1:0]),

		    .cpu_clk		(cpu_clk),
		    .rx_sync		(rx_sync),
		    .int_buf_sel_next	(int_buf_sel_next),
		    .io_buf_sel_next	(io_buf_sel_next),
		    .int_buf_rd		(int_buf_rd),
		    .io_buf_rd		(io_buf_rd),
		    .int_buf_dout_raw	(int_buf_dout_raw[159:0]),
		    .io_buf_dout_raw	(io_buf_dout_raw[159:0]));
   


   i2c_sctrl i2c_sctrl (

			.jbi_mondo_rd	(jbi_mondo_rd),
			.jbi_int_rd	(jbi_int_rd),
			.clk_int_rd	(clk_int_rd),
			.dram0_int_rd	(dram0_int_rd),
			.dram1_int_rd	(dram1_int_rd),
			.iob_man_int_rd	(iob_man_int_rd),
			.spi_int_rd	(spi_int_rd),
			.jbi_ack_rd	(jbi_ack_rd),
			.clk_ack_rd	(clk_ack_rd),
			.dram0_ack_rd	(dram0_ack_rd),
			.dram1_ack_rd	(dram1_ack_rd),
			.iob_man_ack_rd	(iob_man_ack_rd),
			.iob_int_ack_rd	(iob_int_ack_rd),
			.spi_ack_rd	(spi_ack_rd),
			.bounce_ack_rd	(bounce_ack_rd),
			.rd_nack_rd	(rd_nack_rd),
			.int_sel	(int_sel[`IOB_INT_AVEC_WIDTH-1:0]),
			.ack_sel	(ack_sel[`IOB_ACK_AVEC_WIDTH-1:0]),
			.mondo_srvcd_d1	(mondo_srvcd_d1),
			.int_srvcd_d1	(int_srvcd_d1),
			.ack_srvcd_d1	(ack_srvcd_d1),
			.io_buf_tail_s	(io_buf_tail_s[`IOB_IO_BUF_INDEX:0]),
			.io_mondo_data_wr_s(io_mondo_data_wr_s),
			.io_buf_avail	(io_buf_avail),
			.int_srvcd	(int_srvcd),
			.io_buf_wr	(io_buf_wr),
			.io_buf_tail_ptr(io_buf_tail_ptr[`IOB_IO_BUF_INDEX-1:0]),
			.iob_tap_packet_vld(iob_tap_packet_vld),
			.iob_jbi_mondo_ack(iob_jbi_mondo_ack),
			.iob_jbi_mondo_nack(iob_jbi_mondo_nack),

			.rst_l		(rst_l),
			.clk		(clk),
			.jbi_mondo_vld	(jbi_mondo_vld),
			.jbi_mondo_target(jbi_mondo_target[`IOB_CPUTHR_INDEX-1:0]),
			.spi_int_vld	(spi_int_vld),
			.iob_man_int_vld(iob_man_int_vld),
			.dram1_int_vld	(dram1_int_vld),
			.dram0_int_vld	(dram0_int_vld),
			.clk_int_vld	(clk_int_vld),
			.jbi_int_vld	(jbi_int_vld),
			.rd_nack_vld	(rd_nack_vld),
			.bounce_ack_vld	(bounce_ack_vld),
			.spi_ack_vld	(spi_ack_vld),
			.iob_int_ack_vld(iob_int_ack_vld),
			.iob_man_ack_vld(iob_man_ack_vld),
			.dram1_ack_vld	(dram1_ack_vld),
			.dram0_ack_vld	(dram0_ack_vld),
			.clk_ack_vld	(clk_ack_vld),
			.jbi_ack_vld	(jbi_ack_vld),
			.ack_packet_d1	(ack_packet_d1[`UCB_128PAY_PKT_WIDTH-1:0]),
			.io_buf_head_f	(io_buf_head_f[`IOB_IO_BUF_INDEX:0]),
			.mondo_busy_vec_f(mondo_busy_vec_f[`IOB_CPUTHR_WIDTH-1:0]),
			.srvc_wr_ack	(srvc_wr_ack),
			.cpu_intman_acc	(cpu_intman_acc),
			.cpu_intctrl_acc(cpu_intctrl_acc),
			.creg_intctrl_mask(creg_intctrl_mask),
			.tap_iob_busy	(tap_iob_busy));
   
   

   i2c_sdp i2c_sdp (

		    .io_mondo_data_wr_addr_s(io_mondo_data_wr_addr_s[`IOB_CPUTHR_INDEX-1:0]),
		    .io_mondo_data0_din_s(io_mondo_data0_din_s[63:0]),
		    .io_mondo_data1_din_s(io_mondo_data1_din_s[63:0]),
		    .io_mondo_source_din_s(io_mondo_source_din_s[`JBI_IOB_MONDO_SRC_WIDTH-1:0]),
		    .io_intman_addr	(io_intman_addr[`IOB_INT_TAB_INDEX-1:0]),
		    .ack_packet_d1	(ack_packet_d1[`UCB_128PAY_PKT_WIDTH-1:0]),
		    .io_buf_din_raw	(io_buf_din_raw[159:0]),
		    .iob_tap_packet	(iob_tap_packet[`UCB_64PAY_PKT_WIDTH-1:0]),

		    .clk		(clk),
		    .jbi_mondo_data0	(jbi_mondo_data0[63:0]),
		    .jbi_mondo_data1	(jbi_mondo_data1[63:0]),
		    .jbi_mondo_target	(jbi_mondo_target[`IOB_CPUTHR_INDEX-1:0]),
		    .jbi_mondo_source	(jbi_mondo_source[`JBI_IOB_MONDO_SRC_WIDTH-1:0]),
		    .jbi_int_packet	(jbi_int_packet[`UCB_INT_PKT_WIDTH-1:0]),
		    .clk_int_packet	(clk_int_packet[`UCB_INT_PKT_WIDTH-1:0]),
		    .dram0_int_packet	(dram0_int_packet[`UCB_INT_PKT_WIDTH-1:0]),
		    .dram1_int_packet	(dram1_int_packet[`UCB_INT_PKT_WIDTH-1:0]),
		    .iob_man_int_packet	(iob_man_int_packet[`UCB_INT_PKT_WIDTH-1:0]),
		    .spi_int_packet	(spi_int_packet[`UCB_INT_PKT_WIDTH-1:0]),
		    .jbi_ack_packet	(jbi_ack_packet[`UCB_128PAY_PKT_WIDTH-1:0]),
		    .clk_ack_packet	(clk_ack_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
		    .dram0_ack_packet	(dram0_ack_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
		    .dram1_ack_packet	(dram1_ack_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
		    .iob_man_ack_packet	(iob_man_ack_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
		    .iob_int_ack_packet	(iob_int_ack_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
		    .spi_ack_packet	(spi_ack_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
		    .bounce_ack_packet	(bounce_ack_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
		    .rd_nack_packet	(rd_nack_packet[`UCB_NOPAY_PKT_WIDTH-1:0]),
		    .int_vec_dout_raw	(int_vec_dout_raw[14:0]),
		    .int_cpu_dout_raw	(int_cpu_dout_raw[14:0]),
		    .int_sel		(int_sel[`IOB_INT_AVEC_WIDTH-1:0]),
		    .ack_sel		(ack_sel[`IOB_ACK_AVEC_WIDTH-1:0]),
		    .mondo_srvcd_d1	(mondo_srvcd_d1),
		    .int_srvcd_d1	(int_srvcd_d1),
		    .ack_srvcd_d1	(ack_srvcd_d1),
		    .wr_ack_io_buf_din	(wr_ack_io_buf_din[`IOB_IO_BUF_WIDTH-1:0]),
		    .creg_jintv_vec	(creg_jintv_vec[`IOB_INT_VEC_WIDTH-1:0]),
		    .first_availcore	(first_availcore[`IOB_CPU_WIDTH-1:0]));
   




   ucb_bus_out #(`IOB_TAP_WIDTH,64) tap_ucb_buf
     (


      .vld				(iob_tap_vld),
      .data				(iob_tap_data[`IOB_TAP_WIDTH-1:0]),
      .outdata_buf_busy			(tap_iob_busy),

      .clk				(clk),
      .rst_l				(rst_l),
      .stall				(tap_iob_stall),
      .outdata_buf_in			(iob_tap_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
      .outdata_vec_in			({128/`IOB_TAP_WIDTH{1'b1}}),
      .outdata_buf_wr			(iob_tap_packet_vld));

   



   i2c_buf #(`JBI_IOB_WIDTH,128,`UCB_128PAY_PKT_WIDTH,`UCB_INT_PKT_WIDTH) jbi_ucb_buf
     (


      .iob_ucb_stall			(iob_jbi_pio_stall),
      .req_ack_obj			(jbi_ack_packet[`UCB_128PAY_PKT_WIDTH-1:0]),
      .req_ack_vld			(jbi_ack_vld),
      .int_obj				(jbi_int_packet[`UCB_INT_PKT_WIDTH-1:0]),
      .int_vld				(jbi_int_vld),

      .rst_l				(rst_l),
      .clk				(clk),
      .ucb_iob_vld			(jbi_iob_pio_vld),
      .ucb_iob_data			(jbi_iob_pio_data[`JBI_IOB_WIDTH-1:0]),
      .rd_req_ack_dbl_buf		(jbi_ack_rd),
      .rd_int_dbl_buf			(jbi_int_rd));

   



   i2c_buf #(`CLK_IOB_WIDTH,64,`UCB_64PAY_PKT_WIDTH,`UCB_INT_PKT_WIDTH) clk_ucb_buf
     (


      .iob_ucb_stall			(iob_clk_stall),
      .req_ack_obj			(clk_ack_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
      .req_ack_vld			(clk_ack_vld),
      .int_obj				(clk_int_packet[`UCB_INT_PKT_WIDTH-1:0]),
      .int_vld				(clk_int_vld),

      .rst_l				(rst_l),
      .clk				(clk),
      .ucb_iob_vld			(clk_iob_vld),
      .ucb_iob_data			(clk_iob_data[`CLK_IOB_WIDTH-1:0]),
      .rd_req_ack_dbl_buf		(clk_ack_rd),
      .rd_int_dbl_buf			(clk_int_rd));

   



   i2c_buf #(`DRAM_IOB_WIDTH,64,`UCB_64PAY_PKT_WIDTH,`UCB_INT_PKT_WIDTH) dram0_ucb_buf
     (


      .iob_ucb_stall			(iob_dram02_stall),
      .req_ack_obj			(dram0_ack_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
      .req_ack_vld			(dram0_ack_vld),
      .int_obj				(dram0_int_packet[`UCB_INT_PKT_WIDTH-1:0]),
      .int_vld				(dram0_int_vld),

      .rst_l				(rst_l),
      .clk				(clk),
      .ucb_iob_vld			(dram02_iob_vld),
      .ucb_iob_data			(dram02_iob_data[`DRAM_IOB_WIDTH-1:0]),
      .rd_req_ack_dbl_buf		(dram0_ack_rd),
      .rd_int_dbl_buf			(dram0_int_rd));

   



   i2c_buf #(`DRAM_IOB_WIDTH,64,`UCB_64PAY_PKT_WIDTH,`UCB_INT_PKT_WIDTH) dram1_ucb_buf
     (


      .iob_ucb_stall			(iob_dram13_stall),
      .req_ack_obj			(dram1_ack_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
      .req_ack_vld			(dram1_ack_vld),
      .int_obj				(dram1_int_packet[`UCB_INT_PKT_WIDTH-1:0]),
      .int_vld				(dram1_int_vld),

      .rst_l				(rst_l),
      .clk				(clk),
      .ucb_iob_vld			(dram13_iob_vld),
      .ucb_iob_data			(dram13_iob_data[`DRAM_IOB_WIDTH-1:0]),
      .rd_req_ack_dbl_buf		(dram1_ack_rd),
      .rd_int_dbl_buf			(dram1_int_rd));

   



   i2c_buf #(`SPI_IOB_WIDTH,64,`UCB_64PAY_PKT_WIDTH,`UCB_INT_PKT_WIDTH) spi_ucb_buf
     (


      .iob_ucb_stall			(iob_jbi_spi_stall),
      .req_ack_obj			(spi_ack_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
      .req_ack_vld			(spi_ack_vld),
      .int_obj				(spi_int_packet[`UCB_INT_PKT_WIDTH-1:0]),
      .int_vld				(spi_int_vld),

      .rst_l				(rst_l),
      .clk				(clk),
      .ucb_iob_vld			(jbi_iob_spi_vld),
      .ucb_iob_data			(jbi_iob_spi_data[`SPI_IOB_WIDTH-1:0]),
      .rd_req_ack_dbl_buf		(spi_ack_rd),
      .rd_int_dbl_buf			(spi_int_rd));

   



   iobdg_jbus_mondo_buf jbus_mondo_buf
     (


      .mondo_vld			(jbi_mondo_vld),
      .mondo_data0			(jbi_mondo_data0[63:0]),
      .mondo_data1			(jbi_mondo_data1[63:0]),
      .mondo_target			(jbi_mondo_target[`JBI_IOB_MONDO_TRG_WIDTH-1:0]),
      .mondo_source			(jbi_mondo_source[`JBI_IOB_MONDO_SRC_WIDTH-1:0]),

      .rst_l				(rst_l),
      .clk				(clk),
      .jbi_iob_vld			(jbi_iob_mondo_vld),
      .jbi_iob_data			(jbi_iob_mondo_data[`JBI_IOB_MONDO_BUS_WIDTH-1:0]),
      .rd_mondo_buf			(jbi_mondo_rd));
      
endmodule