data/full_repos/permissive/451853158/MIPS_Multi_Cycle_Processor/reset_en_ff.v
data/verilator_xmls/08ac3818-9942-4ee4-b5a1-01e9e4f7f460.xml
module reset_en_ff (
  input             clk, reset, en,
  input      [31:0] d,
  output reg [31:0] q
);



always @(posedge clk or posedge reset)
  if (reset)   q <= 32'b0;
  else if (en)  q <= d;

endmodule
module reset_en_ff (
  input             clk, reset, en,
  input      [31:0] d,
  output reg [31:0] q
);




always @(posedge clk or posedge reset)
  if (reset)   q <= 32'b0;
  else if (en)  q <= d;

endmodule