data/full_repos/permissive/470590146/testbench/nx_riscv_top_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/470590146/testbench/nx_riscv_top_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #(20/2)  clk = !clk ;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/470590146/testbench/nx_riscv_top_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n            #rt_time;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/470590146/testbench/nx_riscv_top_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n            #20;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/470590146/testbench/nx_riscv_top_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n            #20;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/470590146/testbench/nx_riscv_top_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n            #20;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/470590146/testbench/nx_riscv_top_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n            #(20*10);\n            ^\n%Error: data/full_repos/permissive/470590146/testbench/nx_riscv_top_tb.v:105: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("top_dump.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/470590146/testbench/nx_riscv_top_tb.v:106: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, nx_riscv_top_tb);\n        ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module nx_riscv_top_tb;





reg clk = 0;
reg rst_n = 0;
reg inst_ram_wen;
reg [31:0] inst_ram_waddr;
reg [31:0] inst_ram_wdata;
reg         data_ram_wen_initial;
reg [31:0] data_ram_waddr_initial;
reg [31:0] data_ram_wdata_initial;
reg         regfile_wen_initial;
reg [ 4:0] regfile_waddr_initial;
reg [31:0] regfile_wdata_initial;

    always
        #(`PERIOD/2)  clk = !clk ;


    task sys_reset;
        input [31:0] rt_time;
        begin
            rst_n = 1'b0;
            #rt_time;
            rst_n = 1'b1;
        end
    endtask



    integer i;
    task initial_inst_ram;
        input [31:0] addr;
        input [31:0] data;
        begin

            inst_ram_waddr = addr;

            inst_ram_wdata = data;
            inst_ram_wen = 1'b1;
            #`PERIOD;
            inst_ram_wen = 0;
        end
    endtask
    
    task initial_regfile;
        input  [ 4:0] addr;
        input  [31:0] data;
        begin
            regfile_waddr_initial = addr;
            regfile_wdata_initial = data;
            regfile_wen_initial   = 1;
            #`PERIOD;
            regfile_wen_initial = 0;
        end
    endtask


    task intial_data_ram;
        input [31:0] addr;
        input [31:0] data;
        begin
            data_ram_waddr_initial = addr;
            data_ram_wdata_initial = data;
            data_ram_wen_initial = 1;
            #`PERIOD;
            data_ram_wen_initial = 0;
        end
    endtask

    initial
        begin

            sys_reset(55);

            initial_inst_ram(32'h0000_0008, 32'b0000000_00001_00010_000_00011_0110011);
            initial_regfile(5'b00001, 38);
            initial_regfile(5'b00010, 22);
            sys_reset(55);
            #(`PERIOD*10);
            $finish;
        end

    initial begin
        $dumpfile("top_dump.vcd");
        $dumpvars(0, nx_riscv_top_tb);
    end

    nx_riscv_top 
    nx_riscv_top_dut (
      .clk                    (clk                    ),
      .rst_n                  (rst_n                  ),
      .inst_ram_wen           (inst_ram_wen           ),
      .inst_ram_waddr         (inst_ram_waddr         ),
      .inst_ram_wdata         (inst_ram_wdata         ),
      .data_ram_wen_initial   (data_ram_wen_initial   ),
      .data_ram_waddr_initial (data_ram_waddr_initial ),
      .data_ram_wdata_initial (data_ram_wdata_initial ),
      .regfile_wen_initial    (regfile_wen_initial    ),
      .regfile_waddr_initial  (regfile_waddr_initial  ),
      .regfile_wdata_initial  ( regfile_wdata_initial )
    );
  

endmodule
module nx_riscv_top_tb;






reg clk = 0;
reg rst_n = 0;
reg inst_ram_wen;
reg [31:0] inst_ram_waddr;
reg [31:0] inst_ram_wdata;
reg         data_ram_wen_initial;
reg [31:0] data_ram_waddr_initial;
reg [31:0] data_ram_wdata_initial;
reg         regfile_wen_initial;
reg [ 4:0] regfile_waddr_initial;
reg [31:0] regfile_wdata_initial;

    always
        #(`PERIOD/2)  clk = !clk ;


    task sys_reset;
        input [31:0] rt_time;
        begin
            rst_n = 1'b0;
            #rt_time;
            rst_n = 1'b1;
        end
    endtask



    integer i;
    task initial_inst_ram;
        input [31:0] addr;
        input [31:0] data;
        begin

            inst_ram_waddr = addr;

            inst_ram_wdata = data;
            inst_ram_wen = 1'b1;
            #`PERIOD;
            inst_ram_wen = 0;
        end
    endtask
    
    task initial_regfile;
        input  [ 4:0] addr;
        input  [31:0] data;
        begin
            regfile_waddr_initial = addr;
            regfile_wdata_initial = data;
            regfile_wen_initial   = 1;
            #`PERIOD;
            regfile_wen_initial = 0;
        end
    endtask


    task intial_data_ram;
        input [31:0] addr;
        input [31:0] data;
        begin
            data_ram_waddr_initial = addr;
            data_ram_wdata_initial = data;
            data_ram_wen_initial = 1;
            #`PERIOD;
            data_ram_wen_initial = 0;
        end
    endtask

    initial
        begin

            sys_reset(55);

            initial_inst_ram(32'h0000_0008, 32'b0000000_00001_00010_000_00011_0110011);
            initial_regfile(5'b00001, 38);
            initial_regfile(5'b00010, 22);
            sys_reset(55);
            #(`PERIOD*10);
            $finish;
        end

    initial begin
        $dumpfile("top_dump.vcd");
        $dumpvars(0, nx_riscv_top_tb);
    end

    nx_riscv_top 
    nx_riscv_top_dut (
      .clk                    (clk                    ),
      .rst_n                  (rst_n                  ),
      .inst_ram_wen           (inst_ram_wen           ),
      .inst_ram_waddr         (inst_ram_waddr         ),
      .inst_ram_wdata         (inst_ram_wdata         ),
      .data_ram_wen_initial   (data_ram_wen_initial   ),
      .data_ram_waddr_initial (data_ram_waddr_initial ),
      .data_ram_wdata_initial (data_ram_wdata_initial ),
      .regfile_wen_initial    (regfile_wen_initial    ),
      .regfile_waddr_initial  (regfile_waddr_initial  ),
      .regfile_wdata_initial  ( regfile_wdata_initial )
    );
  

endmodule