data/full_repos/permissive/425175279/MIPS_Pipeline/MEM_WB_Register.v
data/verilator_xmls/d66f1a71-5258-48e2-afd2-5807675e08f5.xml
module MEM_WB_Register(

    input        clk,
    input        rst_n,


    input       [31:0]  ReadDataM,
    input       [31:0]  ALUOutM,
    input       [4:0]   WriteRegM, 

    output  reg [31:0]  ReadDataW,
    output  reg [31:0]  ALUOutW,
    output  reg [4:0]   WriteRegW,


    input               RegWriteM,
    input               MemtoRegM,

    output  reg         RegWriteW,
    output  reg         MemtoRegW
);


    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)begin
            RegWriteW <= 1'b0;
            MemtoRegW <= 1'b0;
        end
        else begin

            ReadDataW <= ReadDataM;
            ALUOutW   <= ALUOutM;
            WriteRegW <= WriteRegM;


            RegWriteW <= RegWriteM;
            MemtoRegW <= MemtoRegM;
        end
    end

endmodule
module MEM_WB_Register(

    input        clk,
    input        rst_n,


    input       [31:0]  ReadDataM,
    input       [31:0]  ALUOutM,
    input       [4:0]   WriteRegM, 

    output  reg [31:0]  ReadDataW,
    output  reg [31:0]  ALUOutW,
    output  reg [4:0]   WriteRegW,


    input               RegWriteM,
    input               MemtoRegM,

    output  reg         RegWriteW,
    output  reg         MemtoRegW
);



    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)begin
            RegWriteW <= 1'b0;
            MemtoRegW <= 1'b0;
        end
        else begin

            ReadDataW <= ReadDataM;
            ALUOutW   <= ALUOutM;
            WriteRegW <= WriteRegM;


            RegWriteW <= RegWriteM;
            MemtoRegW <= MemtoRegM;
        end
    end

endmodule