data/full_repos/permissive/519392866/level3_design/shift_reg.v
data/verilator_xmls/47ed75a1-9dbe-4a55-a0ae-b0f51c5fad12.xml
module d_flip_flop_edge_triggered(Q, Qn, C, D);
   output Q;
   output Qn;
   input  C;
   input  D;

   wire   Cn;
   wire   Cnn;
   wire   DQ;
   wire   DQn;
   
   not(Cn, C);
   not(Cnn, Cn);   
   d_latch dl(DQ, DQn, Cn, D);
   sr_latch_gated sr(Q, Qn, Cnn, DQ, DQn);   
endmodule
module d_flip_flop_edge_triggered(Q, Qn, C, D);

   output Q;
   output Qn;
   input  C;
   input  D;

   wire   Cn;
   wire   Cnn;
   wire   DQ;
   wire   DQn;
   
   not(Cn, C);
   not(Cnn, Cn);   
   d_latch dl(DQ, DQn, Cn, D);
   sr_latch_gated sr(Q, Qn, Cnn, DQ, DQn);   
endmodule