data/full_repos/permissive/428819669/comparator.v
data/verilator_xmls/699b2386-62ae-4d69-b0ca-677703c42b6c.xml
module comparator (output reg [2:0] result, input [15:0] X, Y, input clk);
    always @ (posedge clk) begin
        if (X[15] == 1'b0 && Y[15] == 1'b1)
            result <= 3'b100; 
        else if (X[15] == 1'b1 && Y[15] == 1'b0)
            result <= 3'b010;
        else if (X[14:10] > Y[14:10])
            result <= 3'b100; 
        else if (X[14:10] < Y[14:10])
            result <= 3'b010;
        else if (X[9:0] > Y[9:0])
            result <= 3'b100; 
        else if (X[9:0] < Y[9:0])
            result <= 3'b010;
        else 
            result <= 3'b001;
    end
endmodule
module comparator (output reg [2:0] result, input [15:0] X, Y, input clk);

    always @ (posedge clk) begin
        if (X[15] == 1'b0 && Y[15] == 1'b1)
            result <= 3'b100; 
        else if (X[15] == 1'b1 && Y[15] == 1'b0)
            result <= 3'b010;
        else if (X[14:10] > Y[14:10])
            result <= 3'b100; 
        else if (X[14:10] < Y[14:10])
            result <= 3'b010;
        else if (X[9:0] > Y[9:0])
            result <= 3'b100; 
        else if (X[9:0] < Y[9:0])
            result <= 3'b010;
        else 
            result <= 3'b001;
    end
endmodule