data/full_repos/permissive/529706848/verilog/encoder_8to3.v
data/verilator_xmls/de6145a4-f9e3-4b2a-a769-1f3a7462dd5d.xml
module encoder_8to3_PROJECT_ID(
    input [7:0] in,
    output [2:0] out
);

assign out[0] = in[1] | in[3] | in[5] | in[7];
assign out[1] = in[2] | in[3] | in[6] | in[7];
assign out[2] = in[4] | in[5] | in[6] | in[7];
endmodule
module encoder_8to3_PROJECT_ID(
    input [7:0] in,
    output [2:0] out
);


assign out[0] = in[1] | in[3] | in[5] | in[7];
assign out[1] = in[2] | in[3] | in[6] | in[7];
assign out[2] = in[4] | in[5] | in[6] | in[7];
endmodule