data/full_repos/permissive/477054115/Mips16_singlecycle/fullAdder.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/477054115/Mips16_singlecycle/fullAdder.v:9: Signal definition not found, creating implicitly: \'c1\'\n and #(50) and1(c1,a,b);  \n                ^~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/477054115/Mips16_singlecycle/fullAdder.v:10: Signal definition not found, creating implicitly: \'c2\'\n                                                                                         : ... Suggested alternative: \'c1\'\n or #(50) or1(c2,a,b);  \n              ^~\n%Warning-IMPLICIT: data/full_repos/permissive/477054115/Mips16_singlecycle/fullAdder.v:11: Signal definition not found, creating implicitly: \'c3\'\n                                                                                         : ... Suggested alternative: \'c1\'\n and #(50) and2(c3,c2,cin);  \n                ^~\n%Error: Exiting due to 3 warning(s)\n'
module adder(sum,cout,a,b,cin);  
 input  a,b,cin;  
 output cout,sum;  

 xor #(50) (sum,a,b,cin);  

 and #(50) and1(c1,a,b);  
 or #(50) or1(c2,a,b);  
 and #(50) and2(c3,c2,cin);  
 or #(50) or2(cout,c1,c3);  
 endmodule
module adder(sum,cout,a,b,cin);
  
 input  a,b,cin;  
 output cout,sum;  

 xor #(50) (sum,a,b,cin);  

 and #(50) and1(c1,a,b);  
 or #(50) or1(c2,a,b);  
 and #(50) and2(c3,c2,cin);  
 or #(50) or2(cout,c1,c3);  
 endmodule