data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_dtl_vref.v
data/verilator_xmls/a3f94088-7f89-49f2-98f1-fc8f8fe944e4.xml
module bw_io_dtl_vref (

   vref_impctl, vddo
   );



   output        vref_impctl;
   input         vddo;
assign vref_impctl = 1'b1;
endmodule
module bw_io_dtl_vref (

   vref_impctl, vddo
   );




   output        vref_impctl;
   input         vddo;
assign vref_impctl = 1'b1;
endmodule