data/full_repos/permissive/495988601/ece385_finalproject.sv
1: b"%Error: data/full_repos/permissive/495988601/ece385_finalproject.sv:84: Cannot find file containing module: 'audio_interface'\n  audio_interface music ( .LDATA (music_content),\n  ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/495988601,data/full_repos/permissive/495988601/audio_interface\n             data/full_repos/permissive/495988601,data/full_repos/permissive/495988601/audio_interface.v\n             data/full_repos/permissive/495988601,data/full_repos/permissive/495988601/audio_interface.sv\n             audio_interface\n             audio_interface.v\n             audio_interface.sv\n             obj_dir/audio_interface\n             obj_dir/audio_interface.v\n             obj_dir/audio_interface.sv\n%Error: data/full_repos/permissive/495988601/ece385_finalproject.sv:103: Cannot find file containing module: 'audio'\n  audio Audio_istance (.*, .Reset(Reset_h));\n  ^~~~~\n%Error: data/full_repos/permissive/495988601/ece385_finalproject.sv:105: Cannot find file containing module: 'music'\n  music music_instance(.*);\n  ^~~~~\n%Error: data/full_repos/permissive/495988601/ece385_finalproject.sv:108: Cannot find file containing module: 'hpi_io_intf'\n    hpi_io_intf hpi_io_inst(\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/495988601/ece385_finalproject.sv:129: Cannot find file containing module: 'ece385_finalproject_soc'\n     ece385_finalproject_soc nios_system(\n     ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/495988601/ece385_finalproject.sv:154: Cannot find file containing module: 'vga_clk'\n    vga_clk vga_clk_instance(.inclk0(Clk), .c0(VGA_CLK));\n    ^~~~~~~\n%Error: data/full_repos/permissive/495988601/ece385_finalproject.sv:157: Cannot find file containing module: 'VGA_controller'\n    VGA_controller vga_controller_instance(.Clk, \n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/495988601/ece385_finalproject.sv:177: Cannot find file containing module: 'block_address'\n block_address block_address0( .DrawX, \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/495988601/ece385_finalproject.sv:181: Cannot find file containing module: 'color_mapper'\n    color_mapper color_instance( .color_data,\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/495988601/ece385_finalproject.sv:194: Cannot find file containing module: 'block_state'\n  block_state  block_state0 (  .Clk,                  \n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/495988601/ece385_finalproject.sv:209: Cannot find file containing module: 'block_display'\n  block_display block_display0 ( .Clk,                \n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/495988601/ece385_finalproject.sv:228: Cannot find file containing module: 'random'\n random    random0   ( .Clk,\n ^~~~~~\n%Error: data/full_repos/permissive/495988601/ece385_finalproject.sv:233: Cannot find file containing module: 'rank'\n rank rank0(             .Clk,          \n ^~~~\n%Error: data/full_repos/permissive/495988601/ece385_finalproject.sv:241: Cannot find file containing module: 'frameROM'\n  frameROM   ROM_instance(.address,\n  ^~~~~~~~\n%Error: data/full_repos/permissive/495988601/ece385_finalproject.sv:246: Cannot find file containing module: 'HexDriver'\n    HexDriver hex_inst_0 (score[3:0], HEX0);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/495988601/ece385_finalproject.sv:247: Cannot find file containing module: 'HexDriver'\n    HexDriver hex_inst_1 (score[7:4], HEX1);\n    ^~~~~~~~~\n%Error: Exiting due to 16 error(s)\n"
module ece385_finalproject( input               CLOCK_50,
             input        [3:0]  KEY,
             output logic [6:0]  HEX0, HEX1,

             output logic [7:0]  VGA_R,
                                 VGA_G,
                                 VGA_B,
             output logic        VGA_CLK,
                                 VGA_SYNC_N,
                                 VGA_BLANK_N,
                                 VGA_VS,
                                 VGA_HS,

             inout  wire  [15:0] OTG_DATA,
             output logic [1:0]  OTG_ADDR,
             output logic        OTG_CS_N,
                                 OTG_RD_N,
                                 OTG_WR_N,
                                 OTG_RST_N,
             input               OTG_INT,

             output logic [12:0] DRAM_ADDR,
             inout  wire  [31:0] DRAM_DQ,
             output logic [1:0]  DRAM_BA,
             output logic [3:0]  DRAM_DQM,
             output logic        DRAM_RAS_N,
                                 DRAM_CAS_N,
                                 DRAM_CKE,
                                 DRAM_WE_N,
                                 DRAM_CS_N,
                                 DRAM_CLK,
											
											
				 input AUD_ADCDAT,
				 input AUD_DACLRCK,
				 input AUD_ADCLRCK,
				 input AUD_BCLK,
				 output logic AUD_DACDAT,
				 output logic AUD_XCK,
				 output logic I2C_SCLK,
				 output logic I2C_SDAT
                    );
    
    logic Reset_h, Clk;
    logic [7:0] keycode;
	 int address;
	 logic [23:0] color_data;
    
    assign Clk = CLOCK_50;
    always_ff @ (posedge Clk) begin
        Reset_h <= ~(KEY[0]);
    end
    logic is_block;
	 logic [9:0] DrawX, DrawY;
    logic [1:0] hpi_addr;
    logic [15:0] hpi_data_in, hpi_data_out;
    logic hpi_r, hpi_w, hpi_cs, hpi_reset;
	 logic [19:0][9:0] block_map;
	 logic [2:0] randnum_b;
	 logic new_block, go_down, go_right, go_left, switch, clear, gg, touched, fast_down,go_next,clearall,record;
	 logic [3:0][3:0] block_keep;
	 logic [10:0]        score,score1,score2,score3;
	 
	 logic INIT,data_over,INIT_FINISH;
	 logic [16:0]Add;
	 logic [16:0]music_content;
	 logic adc_full;
	 
	 audio_interface music ( .LDATA (music_content),
									 .RDATA (music_content),
									 .Clk(Clk),
									 .Reset(Reset_h),
									 .INIT(INIT),
									 .INIT_FINISH(INIT_FINISH),
									 .adc_full (adc_full),
									 .data_over(data_over),
									 .AUD_MCLK(AUD_XCK),
									 .AUD_BCLK(AUD_BCLK),
									 .AUD_ADCDAT(AUD_ADCDAT),
									 .AUD_DACDAT(AUD_DACDAT),
									 .AUD_DACLRCK(AUD_DACLRCK),
									 .AUD_ADCLRCK(AUD_ADCLRCK),
									 .I2C_SDAT(I2C_SDAT),
									 .I2C_SCLK(I2C_SCLK),
									 .ADCDATA(ADCDATA),
									 
	 );
	 audio Audio_istance (.*, .Reset(Reset_h));
	 
	 music music_instance(.*);
    

    hpi_io_intf hpi_io_inst(
                            .Clk(Clk),
                            .Reset(Reset_h),

                            .from_sw_address(hpi_addr),
                            .from_sw_data_in(hpi_data_in),
                            .from_sw_data_out(hpi_data_out),
                            .from_sw_r(hpi_r),
                            .from_sw_w(hpi_w),
                            .from_sw_cs(hpi_cs),
                            .from_sw_reset(hpi_reset),

                            .OTG_DATA(OTG_DATA),    
                            .OTG_ADDR(OTG_ADDR),    
                            .OTG_RD_N(OTG_RD_N),    
                            .OTG_WR_N(OTG_WR_N),    
                            .OTG_CS_N(OTG_CS_N),
                            .OTG_RST_N(OTG_RST_N)
    );
     

     ece385_finalproject_soc nios_system(
                             .clk_clk(Clk),         
                             .reset_reset_n(1'b1),
                             .sdram_wire_addr(DRAM_ADDR), 
                             .sdram_wire_ba(DRAM_BA),   
                             .sdram_wire_cas_n(DRAM_CAS_N),
                             .sdram_wire_cke(DRAM_CKE),  
                             .sdram_wire_cs_n(DRAM_CS_N), 
                             .sdram_wire_dq(DRAM_DQ),   
                             .sdram_wire_dqm(DRAM_DQM),  
                             .sdram_wire_ras_n(DRAM_RAS_N),
                             .sdram_wire_we_n(DRAM_WE_N), 
                             .sdram_clk_clk(DRAM_CLK),
                             .keycode_export(keycode),  
                             .otg_hpi_address_export(hpi_addr),
                             .otg_hpi_data_in_port(hpi_data_in),
                             .otg_hpi_data_out_port(hpi_data_out),
                             .otg_hpi_cs_export(hpi_cs),
                             .otg_hpi_r_export(hpi_r),
                             .otg_hpi_w_export(hpi_w),
                             .otg_hpi_reset_export(hpi_reset)
    );
    


    vga_clk vga_clk_instance(.inclk0(Clk), .c0(VGA_CLK));
    

    VGA_controller vga_controller_instance(.Clk, 
														 .Reset(Reset_h), 
														 .VGA_HS, 
														 .VGA_VS,
														 .VGA_CLK,
														 .VGA_BLANK_N,
														 .VGA_SYNC_N,
														 .DrawX,
														 .DrawY);
    

								








	block_address block_address0( .DrawX, 
											.DrawY,
											.address);   
    
    color_mapper color_instance( .color_data,
											.block_map,
											.block_keep,
											.DrawX,
											.DrawY,
											.score,
											.score1,
											.score2,
											.score3,
											.VGA_R,
											.VGA_G,
											.VGA_B);
											
	 block_state  block_state0 (  .Clk,                  
											.Reset(Reset_h),              	
					                  .touched,
											.gg, 
											.keycode,
											.new_block,
											.go_down,
											.fast_down,
											.go_right,
											.go_left,
											.go_next,
											.switch,
											.clear,
											.clearall);
											
	 block_display block_display0 (	.Clk,                
												.Reset(Reset_h),
												.new_block,
												.go_down,
												.fast_down,
												.go_right,
												.go_next,
												.go_left,
												.switch,
												.clear,
												.clearall,
												.gg,
												.touched,
												.record,
												.randnum_b,
												.block_keep,
												.block_map,
												.score);
												
	random 			random0			(	.Clk,
												.frame_clk(VGA_CLK),
												.Reset(Reset_h),
												.randnum_b
	);
	rank rank0(             .Clk,
                           .Reset(Reset_h),
									.score,
									.record,
									.score1,
									.score2,
									.score3);
											
	 frameROM   ROM_instance(.address,
									 .Clk,
									 .color_data);
    

    HexDriver hex_inst_0 (score[3:0], HEX0);
    HexDriver hex_inst_1 (score[7:4], HEX1);

    

endmodule
module ece385_finalproject( input               CLOCK_50,
             input        [3:0]  KEY,
             output logic [6:0]  HEX0, HEX1,

             output logic [7:0]  VGA_R,
                                 VGA_G,
                                 VGA_B,
             output logic        VGA_CLK,
                                 VGA_SYNC_N,
                                 VGA_BLANK_N,
                                 VGA_VS,
                                 VGA_HS,

             inout  wire  [15:0] OTG_DATA,
             output logic [1:0]  OTG_ADDR,
             output logic        OTG_CS_N,
                                 OTG_RD_N,
                                 OTG_WR_N,
                                 OTG_RST_N,
             input               OTG_INT,

             output logic [12:0] DRAM_ADDR,
             inout  wire  [31:0] DRAM_DQ,
             output logic [1:0]  DRAM_BA,
             output logic [3:0]  DRAM_DQM,
             output logic        DRAM_RAS_N,
                                 DRAM_CAS_N,
                                 DRAM_CKE,
                                 DRAM_WE_N,
                                 DRAM_CS_N,
                                 DRAM_CLK,
											
											
				 input AUD_ADCDAT,
				 input AUD_DACLRCK,
				 input AUD_ADCLRCK,
				 input AUD_BCLK,
				 output logic AUD_DACDAT,
				 output logic AUD_XCK,
				 output logic I2C_SCLK,
				 output logic I2C_SDAT
                    );

    
    logic Reset_h, Clk;
    logic [7:0] keycode;
	 int address;
	 logic [23:0] color_data;
    
    assign Clk = CLOCK_50;
    always_ff @ (posedge Clk) begin
        Reset_h <= ~(KEY[0]);
    end
    logic is_block;
	 logic [9:0] DrawX, DrawY;
    logic [1:0] hpi_addr;
    logic [15:0] hpi_data_in, hpi_data_out;
    logic hpi_r, hpi_w, hpi_cs, hpi_reset;
	 logic [19:0][9:0] block_map;
	 logic [2:0] randnum_b;
	 logic new_block, go_down, go_right, go_left, switch, clear, gg, touched, fast_down,go_next,clearall,record;
	 logic [3:0][3:0] block_keep;
	 logic [10:0]        score,score1,score2,score3;
	 
	 logic INIT,data_over,INIT_FINISH;
	 logic [16:0]Add;
	 logic [16:0]music_content;
	 logic adc_full;
	 
	 audio_interface music ( .LDATA (music_content),
									 .RDATA (music_content),
									 .Clk(Clk),
									 .Reset(Reset_h),
									 .INIT(INIT),
									 .INIT_FINISH(INIT_FINISH),
									 .adc_full (adc_full),
									 .data_over(data_over),
									 .AUD_MCLK(AUD_XCK),
									 .AUD_BCLK(AUD_BCLK),
									 .AUD_ADCDAT(AUD_ADCDAT),
									 .AUD_DACDAT(AUD_DACDAT),
									 .AUD_DACLRCK(AUD_DACLRCK),
									 .AUD_ADCLRCK(AUD_ADCLRCK),
									 .I2C_SDAT(I2C_SDAT),
									 .I2C_SCLK(I2C_SCLK),
									 .ADCDATA(ADCDATA),
									 
	 );
	 audio Audio_istance (.*, .Reset(Reset_h));
	 
	 music music_instance(.*);
    

    hpi_io_intf hpi_io_inst(
                            .Clk(Clk),
                            .Reset(Reset_h),

                            .from_sw_address(hpi_addr),
                            .from_sw_data_in(hpi_data_in),
                            .from_sw_data_out(hpi_data_out),
                            .from_sw_r(hpi_r),
                            .from_sw_w(hpi_w),
                            .from_sw_cs(hpi_cs),
                            .from_sw_reset(hpi_reset),

                            .OTG_DATA(OTG_DATA),    
                            .OTG_ADDR(OTG_ADDR),    
                            .OTG_RD_N(OTG_RD_N),    
                            .OTG_WR_N(OTG_WR_N),    
                            .OTG_CS_N(OTG_CS_N),
                            .OTG_RST_N(OTG_RST_N)
    );
     

     ece385_finalproject_soc nios_system(
                             .clk_clk(Clk),         
                             .reset_reset_n(1'b1),
                             .sdram_wire_addr(DRAM_ADDR), 
                             .sdram_wire_ba(DRAM_BA),   
                             .sdram_wire_cas_n(DRAM_CAS_N),
                             .sdram_wire_cke(DRAM_CKE),  
                             .sdram_wire_cs_n(DRAM_CS_N), 
                             .sdram_wire_dq(DRAM_DQ),   
                             .sdram_wire_dqm(DRAM_DQM),  
                             .sdram_wire_ras_n(DRAM_RAS_N),
                             .sdram_wire_we_n(DRAM_WE_N), 
                             .sdram_clk_clk(DRAM_CLK),
                             .keycode_export(keycode),  
                             .otg_hpi_address_export(hpi_addr),
                             .otg_hpi_data_in_port(hpi_data_in),
                             .otg_hpi_data_out_port(hpi_data_out),
                             .otg_hpi_cs_export(hpi_cs),
                             .otg_hpi_r_export(hpi_r),
                             .otg_hpi_w_export(hpi_w),
                             .otg_hpi_reset_export(hpi_reset)
    );
    


    vga_clk vga_clk_instance(.inclk0(Clk), .c0(VGA_CLK));
    

    VGA_controller vga_controller_instance(.Clk, 
														 .Reset(Reset_h), 
														 .VGA_HS, 
														 .VGA_VS,
														 .VGA_CLK,
														 .VGA_BLANK_N,
														 .VGA_SYNC_N,
														 .DrawX,
														 .DrawY);
    

								








	block_address block_address0( .DrawX, 
											.DrawY,
											.address);   
    
    color_mapper color_instance( .color_data,
											.block_map,
											.block_keep,
											.DrawX,
											.DrawY,
											.score,
											.score1,
											.score2,
											.score3,
											.VGA_R,
											.VGA_G,
											.VGA_B);
											
	 block_state  block_state0 (  .Clk,                  
											.Reset(Reset_h),              	
					                  .touched,
											.gg, 
											.keycode,
											.new_block,
											.go_down,
											.fast_down,
											.go_right,
											.go_left,
											.go_next,
											.switch,
											.clear,
											.clearall);
											
	 block_display block_display0 (	.Clk,                
												.Reset(Reset_h),
												.new_block,
												.go_down,
												.fast_down,
												.go_right,
												.go_next,
												.go_left,
												.switch,
												.clear,
												.clearall,
												.gg,
												.touched,
												.record,
												.randnum_b,
												.block_keep,
												.block_map,
												.score);
												
	random 			random0			(	.Clk,
												.frame_clk(VGA_CLK),
												.Reset(Reset_h),
												.randnum_b
	);
	rank rank0(             .Clk,
                           .Reset(Reset_h),
									.score,
									.record,
									.score1,
									.score2,
									.score3);
											
	 frameROM   ROM_instance(.address,
									 .Clk,
									 .color_data);
    

    HexDriver hex_inst_0 (score[3:0], HEX0);
    HexDriver hex_inst_1 (score[7:4], HEX1);

    

endmodule