data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog/noc_arq_mux.v
1: b'%Error: data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog/noc_arq_mux.v:3: Cannot find include file: noc_parameter.vh\n    `include "noc_parameter.vh" \n             ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh\n             data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.v\n             data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.sv\n             noc_parameter.vh\n             noc_parameter.vh.v\n             noc_parameter.vh.sv\n             obj_dir/noc_parameter.vh\n             obj_dir/noc_parameter.vh.v\n             obj_dir/noc_parameter.vh.sv\n%Error: data/full_repos/permissive/463204869/units/noc_arq/source/rtl/verilog/noc_arq_mux.v:127: Cannot find include file: noc_parameter.vh\n    `include "noc_parameter.vh" \n             ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module noc_arq_2to1mux #(
    `include "noc_parameter.vh"
)(
    input  wire                        clk_i,
    input  wire                        reset_q_i,


    input  wire                        wrreq1_i,
    input  wire  [NOC_HEADER_SIZE-1:0] header1_i,
    input  wire [NOC_PAYLOAD_SIZE-1:0] payload1_i,
    output wire                        stall1_o,


    input  wire                        wrreq2_i,
    input  wire  [NOC_HEADER_SIZE-1:0] header2_i,
    input  wire [NOC_PAYLOAD_SIZE-1:0] payload2_i,
    output wire                        stall2_o,


    output reg                         wrreq_o,
    output reg   [NOC_HEADER_SIZE-1:0] header_o,
    output reg  [NOC_PAYLOAD_SIZE-1:0] payload_o,
    input  wire                        stall_i
);

    localparam IN0 = 2'h0;
    localparam IN1 = 2'h1;
    localparam IN2 = 2'h2;

    reg  [1:0] r_arbiter_result, rin_arbiter_result;
    reg        r_burst_active, rin_burst_active;
    reg        stall1;
    reg        stall2;

    wire noc_burst_out = header_o[NOC_HEADER_SIZE-1];
    


    always @(posedge clk_i or negedge reset_q_i) begin
        if (reset_q_i == 1'b0) begin
            r_arbiter_result <= IN0;
            r_burst_active <= 1'b0;
        end
        else begin
            r_arbiter_result <= rin_arbiter_result;
            r_burst_active <= rin_burst_active;
        end
    end



    always @* begin
        rin_arbiter_result = r_arbiter_result;
        stall1 = 1'b0;
        stall2 = 1'b0;


        if (!r_burst_active) begin
            if (wrreq1_i) begin
                rin_arbiter_result = IN1;
                stall2 = 1'b1;
            end
            else if (wrreq2_i) begin
                rin_arbiter_result = IN2;
            end
            else begin
                rin_arbiter_result = IN0;
            end
        end


        else if (r_arbiter_result == IN1) begin
            stall2 = 1'b1;
        end
        else if (r_arbiter_result == IN2) begin
            stall1 = 1'b1;
        end
    end



    always @* begin
        case(rin_arbiter_result)
            IN1: begin
                wrreq_o = wrreq1_i;
                header_o = header1_i;
                payload_o = payload1_i;
            end

            IN2: begin
                wrreq_o = wrreq2_i;
                header_o = header2_i;
                payload_o = payload2_i;
            end

            default: begin
                wrreq_o = 1'b0;
                header_o = {NOC_HEADER_SIZE{1'b0}};
                payload_o = {NOC_PAYLOAD_SIZE{1'b0}};
            end
        endcase
    end



    always @* begin
        rin_burst_active = r_burst_active;
        if (!stall_i && wrreq_o) begin
            if (noc_burst_out) begin
                rin_burst_active = 1'b1;
            end else begin
                rin_burst_active = 1'b0;
            end
        end
    end

    assign stall1_o = stall_i || stall1;
    assign stall2_o = stall_i || stall2;


endmodule
module noc_arq_2to1mux #(
    `include "noc_parameter.vh"
)(
    input  wire                        clk_i,
    input  wire                        reset_q_i,


    input  wire                        wrreq1_i,
    input  wire  [NOC_HEADER_SIZE-1:0] header1_i,
    input  wire [NOC_PAYLOAD_SIZE-1:0] payload1_i,
    output wire                        stall1_o,


    input  wire                        wrreq2_i,
    input  wire  [NOC_HEADER_SIZE-1:0] header2_i,
    input  wire [NOC_PAYLOAD_SIZE-1:0] payload2_i,
    output wire                        stall2_o,


    output reg                         wrreq_o,
    output reg   [NOC_HEADER_SIZE-1:0] header_o,
    output reg  [NOC_PAYLOAD_SIZE-1:0] payload_o,
    input  wire                        stall_i
);


    localparam IN0 = 2'h0;
    localparam IN1 = 2'h1;
    localparam IN2 = 2'h2;

    reg  [1:0] r_arbiter_result, rin_arbiter_result;
    reg        r_burst_active, rin_burst_active;
    reg        stall1;
    reg        stall2;

    wire noc_burst_out = header_o[NOC_HEADER_SIZE-1];
    


    always @(posedge clk_i or negedge reset_q_i) begin
        if (reset_q_i == 1'b0) begin
            r_arbiter_result <= IN0;
            r_burst_active <= 1'b0;
        end
        else begin
            r_arbiter_result <= rin_arbiter_result;
            r_burst_active <= rin_burst_active;
        end
    end



    always @* begin
        rin_arbiter_result = r_arbiter_result;
        stall1 = 1'b0;
        stall2 = 1'b0;


        if (!r_burst_active) begin
            if (wrreq1_i) begin
                rin_arbiter_result = IN1;
                stall2 = 1'b1;
            end
            else if (wrreq2_i) begin
                rin_arbiter_result = IN2;
            end
            else begin
                rin_arbiter_result = IN0;
            end
        end


        else if (r_arbiter_result == IN1) begin
            stall2 = 1'b1;
        end
        else if (r_arbiter_result == IN2) begin
            stall1 = 1'b1;
        end
    end



    always @* begin
        case(rin_arbiter_result)
            IN1: begin
                wrreq_o = wrreq1_i;
                header_o = header1_i;
                payload_o = payload1_i;
            end

            IN2: begin
                wrreq_o = wrreq2_i;
                header_o = header2_i;
                payload_o = payload2_i;
            end

            default: begin
                wrreq_o = 1'b0;
                header_o = {NOC_HEADER_SIZE{1'b0}};
                payload_o = {NOC_PAYLOAD_SIZE{1'b0}};
            end
        endcase
    end



    always @* begin
        rin_burst_active = r_burst_active;
        if (!stall_i && wrreq_o) begin
            if (noc_burst_out) begin
                rin_burst_active = 1'b1;
            end else begin
                rin_burst_active = 1'b0;
            end
        end
    end

    assign stall1_o = stall_i || stall1;
    assign stall2_o = stall_i || stall2;


endmodule