data/full_repos/permissive/447976230/fpga/usrp2/control_lib/clock_control_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/clock_control_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n   initial #1000 reset = 1\'b0;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/clock_control_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n   always #10 aux_clk = ~aux_clk;\n          ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/clock_control_tb.v:47: Unsupported or unknown PLI call: $dumpfile\n   initial $dumpfile("clock_control_tb.vcd");\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/clock_control_tb.v:48: Unsupported or unknown PLI call: $dumpvars\n   initial $dumpvars(0,clock_control_tb);\n           ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/clock_control_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n   initial #10000 $finish;\n           ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module clock_control_tb();
   
  clock_control clock_control
    (.reset(reset),
     .aux_clk(aux_clk),  
     .clk_fpga(clk_fpga),
     .clk_en(clk_en),    
     .clk_sel(clk_sel),  
     .clk_func(clk_func), 
     .clk_status(clk_status),
     
     .sen(sen),   
     .sclk(sclk), 
     .sdi(sdi),
     .sdo(sdo)
     );

   reg reset, aux_clk;
   
   wire [1:0] clk_sel, clk_en;
   
   initial reset = 1'b1;
   initial #1000 reset = 1'b0;
   
   initial aux_clk = 1'b0;
   always #10 aux_clk = ~aux_clk;
   
   initial $dumpfile("clock_control_tb.vcd");
   initial $dumpvars(0,clock_control_tb);
   
   initial #10000 $finish;
   
endmodule
module clock_control_tb();

   
  clock_control clock_control
    (.reset(reset),
     .aux_clk(aux_clk),  
     .clk_fpga(clk_fpga),
     .clk_en(clk_en),    
     .clk_sel(clk_sel),  
     .clk_func(clk_func), 
     .clk_status(clk_status),
     
     .sen(sen),   
     .sclk(sclk), 
     .sdi(sdi),
     .sdo(sdo)
     );

   reg reset, aux_clk;
   
   wire [1:0] clk_sel, clk_en;
   
   initial reset = 1'b1;
   initial #1000 reset = 1'b0;
   
   initial aux_clk = 1'b0;
   always #10 aux_clk = ~aux_clk;
   
   initial $dumpfile("clock_control_tb.vcd");
   initial $dumpvars(0,clock_control_tb);
   
   initial #10000 $finish;
   
endmodule