data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/cswap.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/cswap.v:90: Signal definition not found, creating implicitly: \'arg1\'\n                                                                                                                        : ... Suggested alternative: \'arg\'\nassign         aswap0 = arg1 ^ dummy1;\n                        ^~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/cswap.v:91: Signal definition not found, creating implicitly: \'brg1\'\n                                                                                                                        : ... Suggested alternative: \'arg1\'\nassign         bswap0 = brg1 ^ dummy1;\n                        ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/cswap.v:97: Signal definition not found, creating implicitly: \'aswap1\'\n                                                                                                                        : ... Suggested alternative: \'aswap\'\nassign         aswap = aswap1;\n                       ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/cswap.v:98: Signal definition not found, creating implicitly: \'bswap1\'\n                                                                                                                        : ... Suggested alternative: \'bswap\'\nassign         bswap = bswap1;\n                       ^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/cswap.v:75: Cannot find file containing module: \'full_sub\'\nfull_sub #(256) ifull_sub (DUM,swaprg,dumsub);\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult,data/full_repos/permissive/530013823/full_sub\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult,data/full_repos/permissive/530013823/full_sub.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult,data/full_repos/permissive/530013823/full_sub.sv\n             full_sub\n             full_sub.v\n             full_sub.sv\n             obj_dir/full_sub\n             obj_dir/full_sub.v\n             obj_dir/full_sub.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/cswap.v:83: Cannot find file containing module: \'fflopx\'\nfflopx #(256) ifflopxdm(clk,rst,dummy,dummy1);\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/cswap.v:84: Cannot find file containing module: \'fflopx\'\nfflopx #(256) ifflopxas1(clk,rst,arg,arg1);\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/cswap.v:85: Cannot find file containing module: \'fflopx\'\nfflopx #(256) ifflopxbs1(clk,rst,brg,brg1);  \n^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/cswap.v:90: Operator XOR expects 256 bits on the LHS, but LHS\'s VARREF \'arg1\' generates 1 bits.\n                                                                                                                     : ... In instance cswap\nassign         aswap0 = arg1 ^ dummy1;\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/cswap.v:91: Operator XOR expects 256 bits on the LHS, but LHS\'s VARREF \'brg1\' generates 1 bits.\n                                                                                                                     : ... In instance cswap\nassign         bswap0 = brg1 ^ dummy1;\n                             ^\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/cswap.v:93: Cannot find file containing module: \'fflopx\'\nfflopx #(256) ifflopxas2(clk,rst,aswap0,aswap1);\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/cswap.v:94: Cannot find file containing module: \'fflopx\'\nfflopx #(256) ifflopxbs2(clk,rst,bswap0,bswap1);\n^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/cswap.v:97: Operator ASSIGNW expects 256 bits on the Assign RHS, but Assign RHS\'s VARREF \'aswap1\' generates 1 bits.\n                                                                                                                     : ... In instance cswap\nassign         aswap = aswap1;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/cswap.v:98: Operator ASSIGNW expects 256 bits on the Assign RHS, but Assign RHS\'s VARREF \'bswap1\' generates 1 bits.\n                                                                                                                     : ... In instance cswap\nassign         bswap = bswap1;\n                     ^\n%Error: Exiting due to 6 error(s), 8 warning(s)\n'
module cswap
    (
     clk,
     rst,

     swap,
     a,
     b,
     en,

     aswap,
     bswap,
     vld
     );



parameter WID = 256;
parameter DUM = 256'd57896044618658097711785492504343953926634992332820282019728792003956564819968;
localparam INIT = 0;



input     clk;
input     rst;

input [WID-1:0] swap;
input [WID-1:0] a;
input [WID-1:0] b;
input           en;

output [WID-1:0] aswap;
output [WID-1:0] bswap;
output           vld;





reg [WID-1:0]    arg,brg,swaprg;

always@(posedge clk)
    begin
    if(rst)
        begin
        arg <= INIT;
        brg <= INIT;
        swaprg <= INIT;
        end
    else if(en)
        begin
        arg <= a;
        brg <= b;
        swaprg <= swap;
        end
    end

wire [WID-1:0] dummy;
wire [WID-1:0] dumsub;
wire [WID-1:0] dumxor;

full_sub #(256) ifull_sub (DUM,swaprg,dumsub);

assign         dumxor = arg ^ brg;

assign         dummy = dumsub & dumxor;

wire [WID-1:0] dummy1;

fflopx #(256) ifflopxdm(clk,rst,dummy,dummy1);
fflopx #(256) ifflopxas1(clk,rst,arg,arg1);
fflopx #(256) ifflopxbs1(clk,rst,brg,brg1);

wire [WID-1:0] aswap0;
wire [WID-1:0] bswap0;

assign         aswap0 = arg1 ^ dummy1;
assign         bswap0 = brg1 ^ dummy1;

fflopx #(256) ifflopxas2(clk,rst,aswap0,aswap1);
fflopx #(256) ifflopxbs2(clk,rst,bswap0,bswap1);


assign         aswap = aswap1;
assign         bswap = bswap1;

reg [1:0]      vldcnt;
wire           vldcnt00;
assign         vldcnt00 = !(|vldcnt);
wire           vldcnten;
assign         vldcnten = vldcnt00 & en;

always@(posedge clk)
    begin
    if(rst)
        begin   
        vldcnt <= INIT;

        end
    else
        begin
        if(vldcnten)
            begin
            vldcnt <= vldcnt + 2'b01;

            end
        else if(|vldcnt)
            begin
            vldcnt <= vldcnt + 2'b01;

            end
        else
            begin
            vldcnt <= vldcnt;

            end
        end
    end

assign vld = &vldcnt;

endmodule
module cswap
    (
     clk,
     rst,

     swap,
     a,
     b,
     en,

     aswap,
     bswap,
     vld
     );




parameter WID = 256;
parameter DUM = 256'd57896044618658097711785492504343953926634992332820282019728792003956564819968;
localparam INIT = 0;



input     clk;
input     rst;

input [WID-1:0] swap;
input [WID-1:0] a;
input [WID-1:0] b;
input           en;

output [WID-1:0] aswap;
output [WID-1:0] bswap;
output           vld;





reg [WID-1:0]    arg,brg,swaprg;

always@(posedge clk)
    begin
    if(rst)
        begin
        arg <= INIT;
        brg <= INIT;
        swaprg <= INIT;
        end
    else if(en)
        begin
        arg <= a;
        brg <= b;
        swaprg <= swap;
        end
    end

wire [WID-1:0] dummy;
wire [WID-1:0] dumsub;
wire [WID-1:0] dumxor;

full_sub #(256) ifull_sub (DUM,swaprg,dumsub);

assign         dumxor = arg ^ brg;

assign         dummy = dumsub & dumxor;

wire [WID-1:0] dummy1;

fflopx #(256) ifflopxdm(clk,rst,dummy,dummy1);
fflopx #(256) ifflopxas1(clk,rst,arg,arg1);
fflopx #(256) ifflopxbs1(clk,rst,brg,brg1);

wire [WID-1:0] aswap0;
wire [WID-1:0] bswap0;

assign         aswap0 = arg1 ^ dummy1;
assign         bswap0 = brg1 ^ dummy1;

fflopx #(256) ifflopxas2(clk,rst,aswap0,aswap1);
fflopx #(256) ifflopxbs2(clk,rst,bswap0,bswap1);


assign         aswap = aswap1;
assign         bswap = bswap1;

reg [1:0]      vldcnt;
wire           vldcnt00;
assign         vldcnt00 = !(|vldcnt);
wire           vldcnten;
assign         vldcnten = vldcnt00 & en;

always@(posedge clk)
    begin
    if(rst)
        begin   
        vldcnt <= INIT;

        end
    else
        begin
        if(vldcnten)
            begin
            vldcnt <= vldcnt + 2'b01;

            end
        else if(|vldcnt)
            begin
            vldcnt <= vldcnt + 2'b01;

            end
        else
            begin
            vldcnt <= vldcnt;

            end
        end
    end

assign vld = &vldcnt;

endmodule