data/full_repos/permissive/520452389/source_codes/Execution.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/520452389/source_codes/Execution.v:22: Signal definition not found, creating implicitly: \'zero\'\n                                                                                   : ... Suggested alternative: \'zero_s3\'\n        MemtoReg_s3,MemRead_s3,RegWrite_s2,RegWrite_s3,Branch_s3,write_reg,write_reg_s3,pc_out1_ss,pc_out1_s3,zero,zero_s3);\n                                                                                                              ^~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/520452389/source_codes/Execution.v:18: Cannot find file containing module: \'ksa_add\'\nksa_add kkkk(0,pc_out1_s2,add_in2,pc_out1_ss, pc_carry);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/520452389/source_codes,data/full_repos/permissive/520452389/ksa_add\n             data/full_repos/permissive/520452389/source_codes,data/full_repos/permissive/520452389/ksa_add.v\n             data/full_repos/permissive/520452389/source_codes,data/full_repos/permissive/520452389/ksa_add.sv\n             ksa_add\n             ksa_add.v\n             ksa_add.sv\n             obj_dir/ksa_add\n             obj_dir/ksa_add.v\n             obj_dir/ksa_add.sv\n%Error: data/full_repos/permissive/520452389/source_codes/Execution.v:20: Cannot find file containing module: \'ALU\'\nALU alu(alu1,alu_in2,ALUCtrl,ALU_result,zero);\n^~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module execution(inout clk,input reset,input [4:0]dest_for_I_s2,input [4:0]dest_for_R_s2,input [4:0]source_s2,input [4:0] write_reg_s4,
        input [31:0] write_data_s4,input RegWrite_s4,input [31:0]extended_32_s2,
        input [31:0]read_data1_s2,input [31:0] read_data2_s2,input [31:0] pc_out1_s2,input RegDst_s2,input ALUSrc_s2,
        input MemtoReg_s2,input RegWrite_s2,input MemRead_s2,input MemWrite_s2,input ALUOp1_s2,input ALUOp0_s2,
        input Branch_s2, output [31:0] ALU_result_s3,output [31:0]read_data2_s3,output MemWrite_s3,output MemtoReg_s3,
        output MemRead_s3,output RegWrite_s3,output Branch_s3,output [4:0]write_reg_s3,output [31:0]pc_out1_s3,output zero_s3);
wire [3:0]ALUCtrl;
wire [31:0] pc_out1_ss,alu_in2,add_in2,ALU_result,alu1,alu2;
wire [4:0] write_reg;
wire pc_carry;
wire[1:0] fwa,fwb;
ALU_control ac(extended_32_s2[5:0],ALUOp1_s2,ALUOp0_s2,ALUCtrl);
forward f1(source_s2,dest_for_I_s2,reset,write_reg_s3,RegWrite_s3,fwa,fwb,write_reg_s4,RegWrite_s4);
muxfa mfa1(read_data1_s2,ALU_result_s3,write_data_s4,fwa,alu1);
muxfa mfa2(read_data2_s2,ALU_result_s3,write_data_s4,fwb,alu2);
mux1 m1(dest_for_I_s2,dest_for_R_s2,RegDst_s2,write_reg);
shift_left slt(extended_32_s2[29:0],add_in2);
ksa_add kkkk(0,pc_out1_s2,add_in2,pc_out1_ss, pc_carry);
mux2 m2(alu2,extended_32_s2,ALUSrc_s2,alu_in2);
ALU alu(alu1,alu_in2,ALUCtrl,ALU_result,zero);
dff3 d3(clk,ALU_result,alu2,Branch_s2,MemWrite_s2,MemtoReg_s2,MemRead_s2,ALU_result_s3,read_data2_s3,MemWrite_s3,
        MemtoReg_s3,MemRead_s3,RegWrite_s2,RegWrite_s3,Branch_s3,write_reg,write_reg_s3,pc_out1_ss,pc_out1_s3,zero,zero_s3);
endmodule
module execution(inout clk,input reset,input [4:0]dest_for_I_s2,input [4:0]dest_for_R_s2,input [4:0]source_s2,input [4:0] write_reg_s4,
        input [31:0] write_data_s4,input RegWrite_s4,input [31:0]extended_32_s2,
        input [31:0]read_data1_s2,input [31:0] read_data2_s2,input [31:0] pc_out1_s2,input RegDst_s2,input ALUSrc_s2,
        input MemtoReg_s2,input RegWrite_s2,input MemRead_s2,input MemWrite_s2,input ALUOp1_s2,input ALUOp0_s2,
        input Branch_s2, output [31:0] ALU_result_s3,output [31:0]read_data2_s3,output MemWrite_s3,output MemtoReg_s3,
        output MemRead_s3,output RegWrite_s3,output Branch_s3,output [4:0]write_reg_s3,output [31:0]pc_out1_s3,output zero_s3);

wire [3:0]ALUCtrl;
wire [31:0] pc_out1_ss,alu_in2,add_in2,ALU_result,alu1,alu2;
wire [4:0] write_reg;
wire pc_carry;
wire[1:0] fwa,fwb;
ALU_control ac(extended_32_s2[5:0],ALUOp1_s2,ALUOp0_s2,ALUCtrl);
forward f1(source_s2,dest_for_I_s2,reset,write_reg_s3,RegWrite_s3,fwa,fwb,write_reg_s4,RegWrite_s4);
muxfa mfa1(read_data1_s2,ALU_result_s3,write_data_s4,fwa,alu1);
muxfa mfa2(read_data2_s2,ALU_result_s3,write_data_s4,fwb,alu2);
mux1 m1(dest_for_I_s2,dest_for_R_s2,RegDst_s2,write_reg);
shift_left slt(extended_32_s2[29:0],add_in2);
ksa_add kkkk(0,pc_out1_s2,add_in2,pc_out1_ss, pc_carry);
mux2 m2(alu2,extended_32_s2,ALUSrc_s2,alu_in2);
ALU alu(alu1,alu_in2,ALUCtrl,ALU_result,zero);
dff3 d3(clk,ALU_result,alu2,Branch_s2,MemWrite_s2,MemtoReg_s2,MemRead_s2,ALU_result_s3,read_data2_s3,MemWrite_s3,
        MemtoReg_s3,MemRead_s3,RegWrite_s2,RegWrite_s3,Branch_s3,write_reg,write_reg_s3,pc_out1_ss,pc_out1_s3,zero,zero_s3);
endmodule