data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/rx_dcoffset.v
1: b'%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/rx_dcoffset.v:9: Operator AND expects 16 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                                       : ... In instance rx_dcoffset\n   wire signed [15:0]    scaled_integrator = integrator[31:16] + (integrator[31] & |integrator[15:0]);\n                                                                                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/rx_dcoffset.v:9: Operator AND expects 16 bits on the RHS, but RHS\'s REDOR generates 1 bits.\n                                                                                       : ... In instance rx_dcoffset\n   wire signed [15:0]    scaled_integrator = integrator[31:16] + (integrator[31] & |integrator[15:0]);\n                                                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp1/sdr_lib/rx_dcoffset.v:20: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'adc_out\' generates 16 bits.\n                                                                                        : ... In instance rx_dcoffset\n       integrator <= #1 integrator + adc_out;\n                                   ^\n%Error: Exiting due to 3 warning(s)\n'
module rx_dcoffset (input clock, input enable, input reset, 
		    input signed [15:0] adc_in, output signed [15:0] adc_out,
		    input wire [6:0] serial_addr, input wire [31:0] serial_data, input serial_strobe);
   parameter 		  MYADDR = 0;
   
   reg signed [31:0] 		 integrator;
   wire signed [15:0] 		 scaled_integrator = integrator[31:16] + (integrator[31] & |integrator[15:0]);
   assign 			 adc_out = adc_in - scaled_integrator;



   always @(posedge clock)
     if(reset)
       integrator <= #1 32'd0;
     else if(serial_strobe & (MYADDR == serial_addr))
       integrator <= #1 {serial_data[15:0],16'd0};
     else if(enable)
       integrator <= #1 integrator + adc_out;

endmodule
module rx_dcoffset (input clock, input enable, input reset, 
		    input signed [15:0] adc_in, output signed [15:0] adc_out,
		    input wire [6:0] serial_addr, input wire [31:0] serial_data, input serial_strobe);

   parameter 		  MYADDR = 0;
   
   reg signed [31:0] 		 integrator;
   wire signed [15:0] 		 scaled_integrator = integrator[31:16] + (integrator[31] & |integrator[15:0]);
   assign 			 adc_out = adc_in - scaled_integrator;



   always @(posedge clock)
     if(reset)
       integrator <= #1 32'd0;
     else if(serial_strobe & (MYADDR == serial_addr))
       integrator <= #1 {serial_data[15:0],16'd0};
     else if(enable)
       integrator <= #1 integrator + adc_out;

endmodule