data/full_repos/permissive/50192283/shift_register.sv
data/verilator_xmls/5c3d99bd-1cad-493b-a752-8b4999a1cbed.xml
module shift_register(
  clock,
  in,
  out);

  parameter width = 1;
  input clock;
  input [0:width-1] in;
  output reg [0:width-1] out;

  always @ (posedge clock)
  begin
    out <= in;
  end
endmodule
module shift_register(
  clock,
  in,
  out);


  parameter width = 1;
  input clock;
  input [0:width-1] in;
  output reg [0:width-1] out;

  always @ (posedge clock)
  begin
    out <= in;
  end
endmodule