data/full_repos/permissive/430337995/ReLU_tb/src/top.v
1: b'%Error: data/full_repos/permissive/430337995/ReLU_tb/src/top.v:1: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/430337995/ReLU_tb/src,data/full_repos/permissive/430337995/define.v\n             data/full_repos/permissive/430337995/ReLU_tb/src,data/full_repos/permissive/430337995/define.v.v\n             data/full_repos/permissive/430337995/ReLU_tb/src,data/full_repos/permissive/430337995/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/430337995/ReLU_tb/src/top.v:21: Define or directive not defined: \'`WORD_ADDR_BITS\'\nwire [`WORD_ADDR_BITS-1:0]  addr_A;\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/ReLU_tb/src/top.v:22: Define or directive not defined: \'`WORD_ADDR_BITS\'\nwire [`WORD_ADDR_BITS-1:0]  addr_B;\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/ReLU_tb/src/top.v:24: Define or directive not defined: \'`WORD_SIZE\'\nreg [`WORD_SIZE-1:0]        DI_A;\n     ^~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/ReLU_tb/src/top.v:25: Define or directive not defined: \'`WORD_SIZE\'\nreg [`WORD_SIZE-1:0]        DI_B;\n     ^~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/ReLU_tb/src/top.v:28: Define or directive not defined: \'`WORD_SIZE\'\nwire [`WORD_SIZE-1:0]       DO_A;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/ReLU_tb/src/top.v:29: Define or directive not defined: \'`WORD_SIZE\'\nwire [`WORD_SIZE-1:0]       DO_B;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/ReLU_tb/src/top.v:33: Define or directive not defined: \'`WORD_SIZE\'\nwire [`WORD_SIZE-1:0]       relu_DI;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/ReLU_tb/src/top.v:36: Define or directive not defined: \'`WORD_SIZE\'\nwire [`WORD_SIZE-1:0]       relu_DO;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/ReLU_tb/src/top.v:41: Define or directive not defined: \'`WORD_ADDR_BITS\'\nreg [`WORD_ADDR_BITS-1:0]   DI_index;\n     ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/ReLU_tb/src/top.v:42: Define or directive not defined: \'`WORD_ADDR_BITS\'\nreg [`WORD_ADDR_BITS-1:0]   DO_index;\n     ^~~~~~~~~~~~~~~\n%Error: Exiting due to 11 error(s)\n'
module TOP(
    clk,
    rst,
    n,
    start,
    done
);


input           clk;
input           rst;
input [9:0]     n;
input           start;
output reg      done;


reg wen_A;
reg wen_B;

wire [`WORD_ADDR_BITS-1:0]  addr_A;
wire [`WORD_ADDR_BITS-1:0]  addr_B;

reg [`WORD_SIZE-1:0]        DI_A;
reg [`WORD_SIZE-1:0]        DI_B;


wire [`WORD_SIZE-1:0]       DO_A;
wire [`WORD_SIZE-1:0]       DO_B;


reg                         relu_DI_valid;
wire [`WORD_SIZE-1:0]       relu_DI;

wire                        relu_DO_valid;
wire [`WORD_SIZE-1:0]       relu_DO;


reg [3:0] cur_st;

reg [`WORD_ADDR_BITS-1:0]   DI_index;
reg [`WORD_ADDR_BITS-1:0]   DO_index;

always@(posedge clk or negedge rst) begin
    if(!rst) begin
        cur_st <= 4'd0;
        DI_A <= 0;
        done <= 1'b0;
        wen_A <= 1'b0;
        DI_index <= 10'h3ff;
        relu_DI_valid <= 1'b0;
    end else begin
        case(cur_st)
            4'd0: begin
                done <= 1'b0;
                wen_A <= 1'b0;
                DI_index <= 10'd0;
                cur_st <= (start) ? 4'd1 : 4'd0;
                relu_DI_valid <= 1'b0;
            end
            4'd1: begin
                wen_A <= 1'b0;
                DI_index <= (DI_index == n-1) ? 10'd0 : DI_index + 10'd1;
                relu_DI_valid <= 1'b1;
                cur_st <= (DI_index == n-1) ? 4'd2 : 4'd1;
            end
            4'd2: begin
                relu_DI_valid <= 1'b0;
                done <= (DO_index == n-1) ? 1'b1 : 1'b0;
                cur_st <= 4'd2;
            end
        endcase
    end
end

always@(posedge clk or negedge rst) begin
    if(!rst) begin
        wen_B <= 1'b0;
        DO_index <= 10'h3ff;
    end else begin
        if(relu_DO_valid) begin
            wen_B <= 1'b1;
            DI_B <= relu_DO;
            DO_index <= (DO_index == n-1) ? 10'd0 : DO_index + 10'd1;
        end else begin
            wen_B <= 1'b0;
        end
    end 
end


assign addr_A = DI_index;
assign addr_B = DO_index;

assign relu_DI = DO_A;


    ReLU relu_i(
            .clk        (clk            ),
            .rst        (rst            ),
            .DI_valid   (relu_DI_valid  ),
            .DI         (relu_DI        ),
            .DO_valid   (relu_DO_valid  ),
            .DO         (relu_DO        )
    );

    SRAM GBUFF_A(
        .clk    (clk        ),
        .rst    (rst        ),
        .wen    (wen_A      ),
        .addr   (addr_A     ),
        .DI     (DI_A       ),
        .DO     (DO_A       )
    );


    SRAM GBUFF_B(
        .clk    (clk        ),
        .rst    (rst        ),
        .wen    (wen_B      ),
        .addr   (addr_B     ),
        .DI     (DI_B       ),
        .DO     (DO_B       )      
    );

endmodule
module TOP(
    clk,
    rst,
    n,
    start,
    done
);



input           clk;
input           rst;
input [9:0]     n;
input           start;
output reg      done;


reg wen_A;
reg wen_B;

wire [`WORD_ADDR_BITS-1:0]  addr_A;
wire [`WORD_ADDR_BITS-1:0]  addr_B;

reg [`WORD_SIZE-1:0]        DI_A;
reg [`WORD_SIZE-1:0]        DI_B;


wire [`WORD_SIZE-1:0]       DO_A;
wire [`WORD_SIZE-1:0]       DO_B;


reg                         relu_DI_valid;
wire [`WORD_SIZE-1:0]       relu_DI;

wire                        relu_DO_valid;
wire [`WORD_SIZE-1:0]       relu_DO;


reg [3:0] cur_st;

reg [`WORD_ADDR_BITS-1:0]   DI_index;
reg [`WORD_ADDR_BITS-1:0]   DO_index;

always@(posedge clk or negedge rst) begin
    if(!rst) begin
        cur_st <= 4'd0;
        DI_A <= 0;
        done <= 1'b0;
        wen_A <= 1'b0;
        DI_index <= 10'h3ff;
        relu_DI_valid <= 1'b0;
    end else begin
        case(cur_st)
            4'd0: begin
                done <= 1'b0;
                wen_A <= 1'b0;
                DI_index <= 10'd0;
                cur_st <= (start) ? 4'd1 : 4'd0;
                relu_DI_valid <= 1'b0;
            end
            4'd1: begin
                wen_A <= 1'b0;
                DI_index <= (DI_index == n-1) ? 10'd0 : DI_index + 10'd1;
                relu_DI_valid <= 1'b1;
                cur_st <= (DI_index == n-1) ? 4'd2 : 4'd1;
            end
            4'd2: begin
                relu_DI_valid <= 1'b0;
                done <= (DO_index == n-1) ? 1'b1 : 1'b0;
                cur_st <= 4'd2;
            end
        endcase
    end
end

always@(posedge clk or negedge rst) begin
    if(!rst) begin
        wen_B <= 1'b0;
        DO_index <= 10'h3ff;
    end else begin
        if(relu_DO_valid) begin
            wen_B <= 1'b1;
            DI_B <= relu_DO;
            DO_index <= (DO_index == n-1) ? 10'd0 : DO_index + 10'd1;
        end else begin
            wen_B <= 1'b0;
        end
    end 
end


assign addr_A = DI_index;
assign addr_B = DO_index;

assign relu_DI = DO_A;


    ReLU relu_i(
            .clk        (clk            ),
            .rst        (rst            ),
            .DI_valid   (relu_DI_valid  ),
            .DI         (relu_DI        ),
            .DO_valid   (relu_DO_valid  ),
            .DO         (relu_DO        )
    );

    SRAM GBUFF_A(
        .clk    (clk        ),
        .rst    (rst        ),
        .wen    (wen_A      ),
        .addr   (addr_A     ),
        .DI     (DI_A       ),
        .DO     (DO_A       )
    );


    SRAM GBUFF_B(
        .clk    (clk        ),
        .rst    (rst        ),
        .wen    (wen_B      ),
        .addr   (addr_B     ),
        .DI     (DI_B       ),
        .DO     (DO_B       )      
    );

endmodule