data/full_repos/permissive/422447942/Codebase/clkmodule.v
data/verilator_xmls/2102bd0e-a9d6-4460-b6bc-a971e5cdd564.xml
module clkmodule(clk, second);
	input clk;
	output reg second;
	
	reg [27:0] counter;
	
	always@(posedge clk) begin
		counter <= counter + 1;
		if(counter == 25_000_000)
			begin
				counter <= 0;
				second <= ~second;
			end
	end
	
endmodule
module clkmodule(clk, second);

	input clk;
	output reg second;
	
	reg [27:0] counter;
	
	always@(posedge clk) begin
		counter <= counter + 1;
		if(counter == 25_000_000)
			begin
				counter <= 0;
				second <= ~second;
			end
	end
	
endmodule