data/full_repos/permissive/417288846/List_2/Task_4/pwm_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/417288846/List_2/Task_4/pwm_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #1 rst = 0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_2/Task_4/pwm_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n        repeat (16) #1 clk = ~clk;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_2/Task_4/pwm_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #1 rst = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_2/Task_4/pwm_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n        repeat (32) #1 clk = ~clk;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_2/Task_4/pwm_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #1 rst = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_2/Task_4/pwm_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n        repeat (40) #1 clk = ~clk;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_2/Task_4/pwm_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #1 rst = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_2/Task_4/pwm_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n        repeat (66) #1 clk = ~clk;\n                    ^\n%Error: data/full_repos/permissive/417288846/List_2/Task_4/pwm_tb.v:42: Unsupported or unknown PLI call: $monitor\n    initial $monitor ($time, " out: %b,clk: %b, cnt: %b", out, clk, cnt);\n            ^~~~~~~~\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
    reg [15:0] top, comp;
    reg clk, rst, pol, mode; 
    wire out;
    wire [15:0] cnt;


    pwm pwm1(.top(top), .comp(comp), .clk(clk), .rst(rst), .pol(pol), .mode(mode), .out(out), .out_counter(cnt));
    initial begin
        clk = 0;
        pol = 0;
        mode = 0;
        top = 16'h0003;
        comp = 16'h0001;
        rst = 1;
        #1 rst = 0;
        repeat (16) #1 clk = ~clk;

        $display ("Mode change");
        mode = 1;
        rst = 1;
        #1 rst = 0;
        repeat (32) #1 clk = ~clk;

        $display ("Bigger top value");
        clk = 0;
        pol = 1;
        mode = 0;
        top = 16'h0010;
        comp = 16'h0001;
        rst = 1;
        #1 rst = 0;
        repeat (40) #1 clk = ~clk;

        $display ("Mode change");
        mode = 1;
        rst = 1;
        #1 rst = 0;
        repeat (66) #1 clk = ~clk;
    end

    initial $monitor ($time, " out: %b,clk: %b, cnt: %b", out, clk, cnt);
endmodule
module testbench;

    reg [15:0] top, comp;
    reg clk, rst, pol, mode; 
    wire out;
    wire [15:0] cnt;


    pwm pwm1(.top(top), .comp(comp), .clk(clk), .rst(rst), .pol(pol), .mode(mode), .out(out), .out_counter(cnt));
    initial begin
        clk = 0;
        pol = 0;
        mode = 0;
        top = 16'h0003;
        comp = 16'h0001;
        rst = 1;
        #1 rst = 0;
        repeat (16) #1 clk = ~clk;

        $display ("Mode change");
        mode = 1;
        rst = 1;
        #1 rst = 0;
        repeat (32) #1 clk = ~clk;

        $display ("Bigger top value");
        clk = 0;
        pol = 1;
        mode = 0;
        top = 16'h0010;
        comp = 16'h0001;
        rst = 1;
        #1 rst = 0;
        repeat (40) #1 clk = ~clk;

        $display ("Mode change");
        mode = 1;
        rst = 1;
        #1 rst = 0;
        repeat (66) #1 clk = ~clk;
    end

    initial $monitor ($time, " out: %b,clk: %b, cnt: %b", out, clk, cnt);
endmodule