data/full_repos/permissive/46454310/dsp/firtest.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/46454310/dsp/firtest.v:25: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/46454310/dsp/firtest.v:28: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Warning-STMTDLY: data/full_repos/permissive/46454310/dsp/firtest.v:32: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Warning-STMTDLY: data/full_repos/permissive/46454310/dsp/firtest.v:34: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Warning-STMTDLY: data/full_repos/permissive/46454310/dsp/firtest.v:36: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Warning-STMTDLY: data/full_repos/permissive/46454310/dsp/firtest.v:38: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Warning-STMTDLY: data/full_repos/permissive/46454310/dsp/firtest.v:40: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Warning-STMTDLY: data/full_repos/permissive/46454310/dsp/firtest.v:45: Unsupported: Ignoring delay on this delayed statement.\nalways begin #50 clk=~clk; end \n             ^\n%Error: data/full_repos/permissive/46454310/dsp/firtest.v:13: Cannot find file containing module: \'filterfir\'\nfilterfir uut (\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/46454310/dsp,data/full_repos/permissive/46454310/filterfir\n             data/full_repos/permissive/46454310/dsp,data/full_repos/permissive/46454310/filterfir.v\n             data/full_repos/permissive/46454310/dsp,data/full_repos/permissive/46454310/filterfir.sv\n             filterfir\n             filterfir.v\n             filterfir.sv\n             obj_dir/filterfir\n             obj_dir/filterfir.v\n             obj_dir/filterfir.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tst;


reg clk;
reg rst;
reg [7:0] x;


wire [9:0] dataout;


filterfir uut (
.clk(clk), 
.rst(rst), 
.x(x), 
.dataout(dataout)
);

initial begin

clk = 0;
rst = 0;
x = 0;
#100;

rst = 1;
#100;

rst = 0;
x = 8'd5;
#100;
x = 8'd10;
#100;
x = 8'd12;
#100;
x = 8'd15;
#100;
x = 8'd16;
#100;



end
always begin #50 clk=~clk; end 
endmodule
module tst;



reg clk;
reg rst;
reg [7:0] x;


wire [9:0] dataout;


filterfir uut (
.clk(clk), 
.rst(rst), 
.x(x), 
.dataout(dataout)
);

initial begin

clk = 0;
rst = 0;
x = 0;
#100;

rst = 1;
#100;

rst = 0;
x = 8'd5;
#100;
x = 8'd10;
#100;
x = 8'd12;
#100;
x = 8'd15;
#100;
x = 8'd16;
#100;



end
always begin #50 clk=~clk; end 
endmodule