data/full_repos/permissive/509703511/RTL_Code/sim/UART_Rx_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/509703511/RTL_Code/sim/UART_Rx_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n      #(PERIOD);\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/509703511/RTL_Code/sim/UART_Rx_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n      #1000;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/509703511/RTL_Code/sim/UART_Rx_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n          #(PERIOD);\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/509703511/RTL_Code/sim/UART_Rx_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n      #(PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/509703511/RTL_Code/sim/UART_Rx_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n      #(PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/509703511/RTL_Code/sim/UART_Rx_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n      #1000;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/509703511/RTL_Code/sim/UART_Rx_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n          #(PERIOD);\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/509703511/RTL_Code/sim/UART_Rx_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n      #(PERIOD);\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/509703511/RTL_Code/sim/UART_Rx_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n  always #(CLK_PERIOD/2) Clk <= ~Clk;\n         ^\n%Error: data/full_repos/permissive/509703511/RTL_Code/sim/UART_Rx_tb.v:89: syntax error, unexpected \'@\'\n      @(posedge Clk);\n      ^\n%Error: data/full_repos/permissive/509703511/RTL_Code/sim/UART_Rx_tb.v:91: syntax error, unexpected \'@\'\n      @(posedge Clk);\n      ^\n%Error: Exiting due to 2 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module UART_Rx_tb();

  
  reg Clk = 0;
  reg RX_Serial = 1;
  wire [7:0] Byte_RX;
  
Top_UART_Rx DUT(
 .i_clk(Clk) ,
 .i_Rx_serial(RX_Serial) ,
 .o_RX_DV() ,
 .o_RX(Byte_RX)
 );

  task UART_WRITE_BYTE_1;
    input [7:0] i_data;
    integer     i;
    begin
      

      RX_Serial <= 1'b0;
      #(PERIOD);
      #1000;
      

      for (i=0; i<8; i=i+1)
        begin
          RX_Serial <= i_data[i];
          #(PERIOD);
        end
      

      RX_Serial <= 1'b1;
      #(PERIOD);
     end
  endtask
  
  task UART_WRITE_BYTE_2;
    input [7:0] i_data;
    integer     i;
    begin
      

      RX_Serial <= 1'b0;
      #(PERIOD);
      #1000;
      

      for (i=0; i<8; i=i+1)
        begin
          RX_Serial <= i_data[i];
          #(PERIOD);
        end
      

      RX_Serial <= 1'b1;
      #(PERIOD);
     end
  endtask
 
  
  always #(CLK_PERIOD/2) Clk <= ~Clk;

  
  initial
    begin
      @(posedge Clk);
      UART_WRITE_BYTE_1(8'h56);
      @(posedge Clk);
            

      if (Byte_RX == 8'h56)
        $display("Correct Byte Received");
      else
        $display("Incorrect Byte Received");
    $finish();
    end
    
    
endmodule
module UART_Rx_tb();


  
  reg Clk = 0;
  reg RX_Serial = 1;
  wire [7:0] Byte_RX;
  
Top_UART_Rx DUT(
 .i_clk(Clk) ,
 .i_Rx_serial(RX_Serial) ,
 .o_RX_DV() ,
 .o_RX(Byte_RX)
 );

  task UART_WRITE_BYTE_1;
    input [7:0] i_data;
    integer     i;
    begin
      

      RX_Serial <= 1'b0;
      #(PERIOD);
      #1000;
      

      for (i=0; i<8; i=i+1)
        begin
          RX_Serial <= i_data[i];
          #(PERIOD);
        end
      

      RX_Serial <= 1'b1;
      #(PERIOD);
     end
  endtask
  
  task UART_WRITE_BYTE_2;
    input [7:0] i_data;
    integer     i;
    begin
      

      RX_Serial <= 1'b0;
      #(PERIOD);
      #1000;
      

      for (i=0; i<8; i=i+1)
        begin
          RX_Serial <= i_data[i];
          #(PERIOD);
        end
      

      RX_Serial <= 1'b1;
      #(PERIOD);
     end
  endtask
 
  
  always #(CLK_PERIOD/2) Clk <= ~Clk;

  
  initial
    begin
      @(posedge Clk);
      UART_WRITE_BYTE_1(8'h56);
      @(posedge Clk);
            

      if (Byte_RX == 8'h56)
        $display("Correct Byte Received");
      else
        $display("Incorrect Byte Received");
    $finish();
    end
    
    
endmodule