data/full_repos/permissive/44647742/tb_freqdiv.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/44647742/tb_freqdiv.v:33: Unsupported: Ignoring delay on this delayed statement.\n#1\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/44647742/tb_freqdiv.v:35: Unsupported: Ignoring delay on this delayed statement.\n#4000\n^\n%Warning-STMTDLY: data/full_repos/permissive/44647742/tb_freqdiv.v:41: Unsupported: Ignoring delay on this delayed statement.\n#0.5 clk = ~clk;\n^\n%Error: data/full_repos/permissive/44647742/tb_freqdiv.v:47: Cannot find file containing module: \'freqdiv\'\nfreqdiv freqdiv0(clk,rst_n,clk_out0,2\'b00);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/44647742,data/full_repos/permissive/44647742/freqdiv\n             data/full_repos/permissive/44647742,data/full_repos/permissive/44647742/freqdiv.v\n             data/full_repos/permissive/44647742,data/full_repos/permissive/44647742/freqdiv.sv\n             freqdiv\n             freqdiv.v\n             freqdiv.sv\n             obj_dir/freqdiv\n             obj_dir/freqdiv.v\n             obj_dir/freqdiv.sv\n%Error: data/full_repos/permissive/44647742/tb_freqdiv.v:48: Cannot find file containing module: \'freqdiv\'\nfreqdiv freqdiv1(clk,rst_n,clk_out1,2\'b01);\n^~~~~~~\n%Error: data/full_repos/permissive/44647742/tb_freqdiv.v:49: Cannot find file containing module: \'freqdiv\'\nfreqdiv freqdiv2(clk,rst_n,clk_out2,2\'b10);\n^~~~~~~\n%Error: Exiting due to 3 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_freqdiv(
    );
reg clk;
reg rst_n;
wire clk_out0;
wire clk_out1;
wire clk_out2;


initial begin
clk = 0;
rst_n = 0;
#1
rst_n = 1;
#4000
$finish;
end

always
begin
#0.5 clk = ~clk;

end



freqdiv freqdiv0(clk,rst_n,clk_out0,2'b00);
freqdiv freqdiv1(clk,rst_n,clk_out1,2'b01);
freqdiv freqdiv2(clk,rst_n,clk_out2,2'b10);

endmodule
module tb_freqdiv(
    );

reg clk;
reg rst_n;
wire clk_out0;
wire clk_out1;
wire clk_out2;


initial begin
clk = 0;
rst_n = 0;
#1
rst_n = 1;
#4000
$finish;
end

always
begin
#0.5 clk = ~clk;

end



freqdiv freqdiv0(clk,rst_n,clk_out0,2'b00);
freqdiv freqdiv1(clk,rst_n,clk_out1,2'b01);
freqdiv freqdiv2(clk,rst_n,clk_out2,2'b10);

endmodule