data/full_repos/permissive/458737381/src/verilog-parser/tests/playback_driver.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/playback_driver.v:46: Unsupported: Ignoring delay on this delayed statement.\nforever #418 clock_vector = ~clock_vector;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/playback_driver.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/playback_driver.v:68: syntax error, unexpected \'@\'\n  @(negedge clock_vector);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/playback_driver.v:69: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cmp_top();

playback_driver iop();

`ifdef DUMP_ON

initial
  if($test$plusargs("dump"))
    $fsdbDumpvars(0, cmp_top.iop);

`endif

endmodule
module cmp_top();


playback_driver iop();

`ifdef DUMP_ON

initial
  if($test$plusargs("dump"))
    $fsdbDumpvars(0, cmp_top.iop);

`endif

endmodule