data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v:16: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk_2f = ~clk_2f;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v:19: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile ("prueba_byte_striping.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v:20: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v:25: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v:29: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v:31: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v:33: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v:35: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v:38: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v:43: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v:45: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v:48: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v:52: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v:54: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v:57: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v:61: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v:63: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v:66: syntax error, unexpected \'@\'\n  @(posedge clk_2f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v:77: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n reg [3:0] checker; \n           ^~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v:77: syntax error, unexpected \';\', expecting IDENTIFIER or \'=\' or do or final\n reg [3:0] checker; \n                  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v:79: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  if (lane_0_c == lane_0_e) checker[3] = 1;\n                            ^~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v:79: syntax error, unexpected \'[\'\n  if (lane_0_c == lane_0_e) checker[3] = 1;\n                                   ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v:80: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  else checker[3] = 0;\n       ^~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v:82: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  if (valid_0_c == valid_0_e) checker[2] = 1;\n                              ^~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v:82: syntax error, unexpected \'[\'\n  if (valid_0_c == valid_0_e) checker[2] = 1;\n                                     ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v:83: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  else checker[2] = 0;\n       ^~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v:85: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  if (lane_1_c == lane_1_e) checker[1] = 1;\n                            ^~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v:85: syntax error, unexpected \'[\'\n  if (lane_1_c == lane_1_e) checker[1] = 1;\n                                   ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v:86: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  else checker[1] = 0;\n       ^~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v:88: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  if (valid_1_c == valid_1_e) checker[0] = 1;\n                              ^~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v:88: syntax error, unexpected \'[\'\n  if (valid_1_c == valid_1_e) checker[0] = 1;\n                                     ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/byte-striping/probador_byte_striping.v:89: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  else checker[0] = 0;\n       ^~~~~~~\n%Error: Exiting due to 31 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module probador_byte_striping (
	output reg clk_2f,
	output reg reset,
	output reg valid_in,
	output reg [31:0] Data_in,
	input valid_0_c,
	input [31:0] lane_0_c,
	input valid_1_c,
	input [31:0] lane_1_c,
	input valid_0_e,
	input [31:0] lane_0_e,
	input valid_1_e,
	input [31:0] lane_1_e
);
	initial clk_2f = 0;
	always #1 clk_2f = ~clk_2f;

	initial begin
		$dumpfile ("prueba_byte_striping.vcd");
		$dumpvars;

		reset <= 0;
		valid_in <= 0;
		Data_in <= 32'b0;
		@(posedge clk_2f);
		reset <= 1;
		valid_in <= 1;
		Data_in <= 'hFFFFFFFF;
		@(posedge clk_2f);
		Data_in <= 'hEEEEEEEE;
		@(posedge clk_2f);
		Data_in <= 'hDDDDDDDD;
		@(posedge clk_2f);
		Data_in <= 'hCCCCCCCC;
		@(posedge clk_2f);
		valid_in <= 0;
		Data_in <= 32'b0;
		@(posedge clk_2f);
		@(posedge clk_2f);
		@(posedge clk_2f);
		valid_in <= 1;
		Data_in <= 'h00000003;
		@(posedge clk_2f);
		Data_in <= 'h00000004;
		@(posedge clk_2f);
		valid_in <= 0;
		Data_in <= 32'b0;
		@(posedge clk_2f);
		@(posedge clk_2f);
		valid_in <= 1;
		Data_in <= 'hAAAAAAAA;
		@(posedge clk_2f);
		Data_in <= 'h99999999;
		@(posedge clk_2f);
		valid_in <= 0;
		Data_in <= 32'b0;
		@(posedge clk_2f);
		@(posedge clk_2f);
		valid_in <= 1;
		Data_in <= 'h00000007;
		@(posedge clk_2f);
		Data_in <= 'h00000008;
		@(posedge clk_2f);
		valid_in <= 0;
		Data_in <= 32'b0;
		@(posedge clk_2f);
		@(posedge clk_2f);
		@(posedge clk_2f);
		$finish;
	end






	reg [3:0] checker; 
	always @(*) begin
		if (lane_0_c == lane_0_e) checker[3] = 1;
		else checker[3] = 0;

		if (valid_0_c == valid_0_e) checker[2] = 1;
		else checker[2] = 0;

		if (lane_1_c == lane_1_e) checker[1] = 1;
		else checker[1] = 0;

		if (valid_1_c == valid_1_e) checker[0] = 1;
		else checker[0] = 0;
	end
endmodule
module probador_byte_striping (
	output reg clk_2f,
	output reg reset,
	output reg valid_in,
	output reg [31:0] Data_in,
	input valid_0_c,
	input [31:0] lane_0_c,
	input valid_1_c,
	input [31:0] lane_1_c,
	input valid_0_e,
	input [31:0] lane_0_e,
	input valid_1_e,
	input [31:0] lane_1_e
);

	initial clk_2f = 0;
	always #1 clk_2f = ~clk_2f;

	initial begin
		$dumpfile ("prueba_byte_striping.vcd");
		$dumpvars;

		reset <= 0;
		valid_in <= 0;
		Data_in <= 32'b0;
		@(posedge clk_2f);
		reset <= 1;
		valid_in <= 1;
		Data_in <= 'hFFFFFFFF;
		@(posedge clk_2f);
		Data_in <= 'hEEEEEEEE;
		@(posedge clk_2f);
		Data_in <= 'hDDDDDDDD;
		@(posedge clk_2f);
		Data_in <= 'hCCCCCCCC;
		@(posedge clk_2f);
		valid_in <= 0;
		Data_in <= 32'b0;
		@(posedge clk_2f);
		@(posedge clk_2f);
		@(posedge clk_2f);
		valid_in <= 1;
		Data_in <= 'h00000003;
		@(posedge clk_2f);
		Data_in <= 'h00000004;
		@(posedge clk_2f);
		valid_in <= 0;
		Data_in <= 32'b0;
		@(posedge clk_2f);
		@(posedge clk_2f);
		valid_in <= 1;
		Data_in <= 'hAAAAAAAA;
		@(posedge clk_2f);
		Data_in <= 'h99999999;
		@(posedge clk_2f);
		valid_in <= 0;
		Data_in <= 32'b0;
		@(posedge clk_2f);
		@(posedge clk_2f);
		valid_in <= 1;
		Data_in <= 'h00000007;
		@(posedge clk_2f);
		Data_in <= 'h00000008;
		@(posedge clk_2f);
		valid_in <= 0;
		Data_in <= 32'b0;
		@(posedge clk_2f);
		@(posedge clk_2f);
		@(posedge clk_2f);
		$finish;
	end






	reg [3:0] checker; 
	always @(*) begin
		if (lane_0_c == lane_0_e) checker[3] = 1;
		else checker[3] = 0;

		if (valid_0_c == valid_0_e) checker[2] = 1;
		else checker[2] = 0;

		if (lane_1_c == lane_1_e) checker[1] = 1;
		else checker[1] = 0;

		if (valid_1_c == valid_1_e) checker[0] = 1;
		else checker[0] = 0;
	end
endmodule