data/full_repos/permissive/493019833/test/testcase/firrtl/RealGCD2_1/reference/RealGCD2_1.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/RealGCD2_1/reference/RealGCD2_1.v:213: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                               : ... In instance RealGCD2.u_pad_3\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module ADD_UNSIGNED(y, a, b);
    parameter width = 4;
    output [width:0] y;
    input [width-1:0] a;
    input [width-1:0] b;
    assign y = a + b;
endmodule
module ADD_UNSIGNED(y, a, b);

    parameter width = 4;
    output [width:0] y;
    input [width-1:0] a;
    input [width-1:0] b;
    assign y = a + b;
endmodule