data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/main.v
1: b"%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/main.v:71: syntax error, unexpected output, expecting ')' or ','\nmodule nor5 (input wire i0, i1, i2, i3, i4 output wire o);\n                                           ^~~~~~\n%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/main.v:73: syntax error, unexpected IDENTIFIER\n   or2 or2_0 (i0, i1, t0);\n   ^~~\n%Error: data/full_repos/permissive/443770883/lab8/studentCopy(referRough)/main.v:387: syntax error, unexpected IDENTIFIER, expecting ',' or ';'\n pc_inc = load_ir\n ^~~~~~\n%Error: Cannot continue\n"
module pc_slice0 (input wire clk, reset, cin, load, inc, sub, offset,
  output wire cout, pc);
  wire in;
  or2 or2_0 (offset, inc, t);
  addsub addsub_0 (sub, pc, t, cin, in, cout);
  dfrl dfrl_0 (clk, reset, load, in, pc);
endmodule
module pc_slice0 (input wire clk, reset, cin, load, inc, sub, offset,
  output wire cout, pc);

  wire in;
  or2 or2_0 (offset, inc, t);
  addsub addsub_0 (sub, pc, t, cin, in, cout);
  dfrl dfrl_0 (clk, reset, load, in, pc);
endmodule