data/full_repos/permissive/441359809/src/yosys/tests/simple/process.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/tests/simple/process.v:21: Multiple top level modules\n                                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                           : ... Top module \'blocking_cond\'\nmodule blocking_cond (in, out);\n       ^~~~~~~~~~~~~\n                                                                                           : ... Top module \'uut\'\nmodule uut(clk, arst, a, b, c, d, e, f,  out1);\n       ^~~\n                                                                                           : ... Top module \'uart\'\nmodule uart (reset, txclk, ld_tx_data, tx_empty, tx_cnt);\n       ^~~~\n%Error: Exiting due to 1 warning(s)\n'
module blocking_cond (in, out);

input in;
output reg out;
reg tmp;

always @* begin
	tmp = 1;
	out = 1'b0;
	case (1'b1)
		tmp: out = in;
	endcase
	tmp = 0;
end

endmodule
module blocking_cond (in, out);


input in;
output reg out;
reg tmp;

always @* begin
	tmp = 1;
	out = 1'b0;
	case (1'b1)
		tmp: out = in;
	endcase
	tmp = 0;
end

endmodule