data/full_repos/permissive/413379110/SMPTE274.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/413379110/SMPTE274.v:66: Signal definition not found, creating implicitly: \'go_vb1\'\nassign go_vb1    = (i_EN ^ i_EN_d) | line_cnt_end; \n       ^~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/413379110/SMPTE274.v:68: Signal definition not found, creating implicitly: \'line_cnt_42\'\n                                                                     : ... Suggested alternative: \'line_cnt\'\nassign go_frame  = line_cnt_42; \n                   ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/413379110/SMPTE274.v:68: Signal definition not found, creating implicitly: \'go_frame\'\nassign go_frame  = line_cnt_42; \n       ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/413379110/SMPTE274.v:69: Signal definition not found, creating implicitly: \'line_cnt_1122\'\n                                                                     : ... Suggested alternative: \'line_cnt_42\'\nassign go_vb2    = line_cnt_1122;   \n                   ^~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/413379110/SMPTE274.v:69: Signal definition not found, creating implicitly: \'go_vb2\'\n                                                                     : ... Suggested alternative: \'go_vb1\'\nassign go_vb2    = line_cnt_1122;   \n       ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/413379110/SMPTE274.v:116: Signal definition not found, creating implicitly: \'line_cnt_1\'\n                                                                      : ... Suggested alternative: \'line_cnt\'\nassign line_cnt_1      = line_cnt == 1    - 1;      \n       ^~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/413379110/SMPTE274.v:120: Signal definition not found, creating implicitly: \'pix_EAV0\'\n                                                                      : ... Suggested alternative: \'line_EAV0\'\nassign pix_EAV0 = pix_cnt == 1920 - 1;\n       ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/413379110/SMPTE274.v:121: Signal definition not found, creating implicitly: \'pix_EAV1\'\n                                                                      : ... Suggested alternative: \'pix_EAV0\'\nassign pix_EAV1 = pix_cnt == 1920 - 1 + 1;       \n       ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/413379110/SMPTE274.v:122: Signal definition not found, creating implicitly: \'pix_EAV2\'\n                                                                      : ... Suggested alternative: \'pix_EAV0\'\nassign pix_EAV2 = pix_cnt == 1920 - 1 + 2;       \n       ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/413379110/SMPTE274.v:123: Signal definition not found, creating implicitly: \'pix_EAV3\'\n                                                                      : ... Suggested alternative: \'pix_EAV0\'\nassign pix_EAV3 = pix_cnt == 1920 - 1 + 3;       \n       ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/413379110/SMPTE274.v:124: Signal definition not found, creating implicitly: \'pix_LN0\'\nassign pix_LN0  = pix_cnt == 1920 - 1 + 4;       \n       ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/413379110/SMPTE274.v:125: Signal definition not found, creating implicitly: \'pix_LN1\'\n                                                                      : ... Suggested alternative: \'pix_LN0\'\nassign pix_LN1  = pix_cnt == 1920 - 1 + 5;       \n       ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/413379110/SMPTE274.v:126: Signal definition not found, creating implicitly: \'pix_CRC0\'\n                                                                      : ... Suggested alternative: \'line_CRC0\'\nassign pix_CRC0 = pix_cnt == 1920 - 1 + 6;       \n       ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/413379110/SMPTE274.v:127: Signal definition not found, creating implicitly: \'pix_CRC1\'\n                                                                      : ... Suggested alternative: \'pix_CRC0\'\nassign pix_CRC1 = pix_cnt == 1920 - 1 + 7;       \n       ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/413379110/SMPTE274.v:128: Signal definition not found, creating implicitly: \'pix_BLANK\'\n                                                                      : ... Suggested alternative: \'line_BLANK\'\nassign pix_BLANK = (pix_cnt > 1920 - 1 + 7) && (pix_cnt < 2196 - 1);  \n       ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/413379110/SMPTE274.v:130: Signal definition not found, creating implicitly: \'pix_SAV0\'\n                                                                      : ... Suggested alternative: \'pix_EAV0\'\nassign pix_SAV0 = pix_cnt == 2196 - 1;\n       ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/413379110/SMPTE274.v:131: Signal definition not found, creating implicitly: \'pix_SAV1\'\n                                                                      : ... Suggested alternative: \'pix_EAV1\'\nassign pix_SAV1 = pix_cnt == 2196 - 1 + 1;       \n       ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/413379110/SMPTE274.v:132: Signal definition not found, creating implicitly: \'pix_SAV2\'\n                                                                      : ... Suggested alternative: \'pix_EAV2\'\nassign pix_SAV2 = pix_cnt == 2196 - 1 + 2;       \n       ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/413379110/SMPTE274.v:133: Signal definition not found, creating implicitly: \'pix_SAV3\'\n                                                                      : ... Suggested alternative: \'pix_EAV3\'\nassign pix_SAV3 = pix_cnt == 2196 - 1 + 3;       \n       ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/413379110/SMPTE274.v:66: Operator XOR expects 11 bits on the LHS, but LHS\'s VARREF \'i_EN\' generates 1 bits.\n                                                                  : ... In instance SMPTE274\nassign go_vb1    = (i_EN ^ i_EN_d) | line_cnt_end; \n                         ^\n%Warning-WIDTH: data/full_repos/permissive/413379110/SMPTE274.v:66: Operator XOR expects 11 bits on the RHS, but RHS\'s VARREF \'i_EN_d\' generates 1 bits.\n                                                                  : ... In instance SMPTE274\nassign go_vb1    = (i_EN ^ i_EN_d) | line_cnt_end; \n                         ^\n%Warning-WIDTH: data/full_repos/permissive/413379110/SMPTE274.v:66: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s OR generates 11 bits.\n                                                                  : ... In instance SMPTE274\nassign go_vb1    = (i_EN ^ i_EN_d) | line_cnt_end; \n                 ^\n%Warning-WIDTH: data/full_repos/permissive/413379110/SMPTE274.v:136: Operator ASSIGNW expects 11 bits on the Assign RHS, but Assign RHS\'s EQ generates 1 bits.\n                                                                   : ... In instance SMPTE274\nassign line_cnt_end = line_cnt == 1125; \n                    ^\n%Warning-WIDTH: data/full_repos/permissive/413379110/SMPTE274.v:138: Operator ASSIGNW expects 12 bits on the Assign RHS, but Assign RHS\'s EQ generates 1 bits.\n                                                                   : ... In instance SMPTE274\nassign pix_cnt_end = pix_cnt == 2200 - 1;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/413379110/SMPTE274.v:148: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'pix_cnt_end\' generates 12 bits.\n                                                                   : ... In instance SMPTE274\n  if (pix_cnt_end)\n  ^~\n%Warning-WIDTH: data/full_repos/permissive/413379110/SMPTE274.v:164: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'pix_cnt_end\' generates 12 bits.\n                                                                   : ... In instance SMPTE274\n  else if (pix_cnt_end) \n       ^~\n%Warning-WIDTH: data/full_repos/permissive/413379110/SMPTE274.v:162: Logical Operator IF expects 1 bit on the If, but If\'s VARREF \'line_cnt_end\' generates 11 bits.\n                                                                   : ... In instance SMPTE274\n  if (line_cnt_end)  \n  ^~\n%Error: data/full_repos/permissive/413379110/SMPTE274.v:362: Cannot find file containing module: \'crcSMPTE\'\ncrcSMPTE CRC_Y (\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/413379110,data/full_repos/permissive/413379110/crcSMPTE\n             data/full_repos/permissive/413379110,data/full_repos/permissive/413379110/crcSMPTE.v\n             data/full_repos/permissive/413379110,data/full_repos/permissive/413379110/crcSMPTE.sv\n             crcSMPTE\n             crcSMPTE.v\n             crcSMPTE.sv\n             obj_dir/crcSMPTE\n             obj_dir/crcSMPTE.v\n             obj_dir/crcSMPTE.sv\n%Error: data/full_repos/permissive/413379110/SMPTE274.v:368: Cannot find file containing module: \'crcSMPTE\'\ncrcSMPTE CRC_C (\n^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/413379110/SMPTE274.v:378: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                   : ... In instance SMPTE274\n           crcIn_Y <= 10\'h000;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/413379110/SMPTE274.v:387: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                   : ... In instance SMPTE274\n               crcIn_Y <= 10\'h000;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/413379110/SMPTE274.v:391: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s CONST \'10\'h0\' generates 10 bits.\n                                                                   : ... In instance SMPTE274\n               crcIn_C <= 10\'h000;\n                       ^~\n%Error: Exiting due to 2 error(s), 30 warning(s)\n'
module SMPTE274(

  input 	      i_CLK_74m25,
  input 	      i_RST,
  input           i_EN,

  input  [ 9 : 0] i_data_Y,
  input  [ 9 : 0] i_data_C,
  
  output [11 : 0] PIX_CNT_o,
  output [10 : 0] LINE_CNT_o,

  output          VSYNC_o,
  output          HSYNC_o,
  output          DATA_RQ_o,

  output [ 9 : 0] Y_data_o,
  output [ 9 : 0] C_data_o
  );


reg  [11 : 0] pix_cnt;
reg  [10 : 0] line_cnt;

wire [11 : 0] pix_cnt_end;
wire [10 : 0] line_cnt_end;

reg           i_EN_d;

reg           F; 
reg           V;
reg           H;
reg           line_data_rq; 

reg           line_EAV0; 
reg           line_EAV1;
reg           line_EAV2;
reg           line_EAV3;
reg           line_LN0;
reg           line_LN1;
reg           line_CRC0;
reg           line_CRC1;
reg           line_BLANK;


assign go_vb1    = (i_EN ^ i_EN_d) | line_cnt_end; 

assign go_frame  = line_cnt_42; 
assign go_vb2    = line_cnt_1122;   

localparam    S_IDLE  = 2'b00; 
localparam    S_VB1   = 2'b01; 
localparam    S_FRAME = 2'b10; 
localparam    S_VB2   = 2'b11; 
reg  [ 1 : 0] state;

reg           vsync;
reg           hsync;
 



always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
		state <= S_IDLE; 
	else 
		case (state) 
			S_IDLE : 
				if (go_vb1)
					state <= S_VB1; 
				else 
					state <= S_IDLE;  
			S_VB1 : 
				if (go_frame) 
					state <= S_FRAME;
				else 
					state <= S_VB1; 
			S_FRAME: 
				if (go_vb2) 
					state <= S_VB2;
				else 
					state <= S_FRAME; 
			S_VB2 : 
				if (go_vb1) 
					state <= S_VB1;
				else 
					state <= S_VB2;
			default : 
				state <= S_IDLE;    
		endcase 					 								
end



assign line_cnt_1      = line_cnt == 1    - 1;
assign line_cnt_42     = line_cnt == 42   - 1;
assign line_cnt_1122   = line_cnt == 1122 - 1;

assign pix_EAV0 = pix_cnt == `pixel_EAV0;
assign pix_EAV1 = pix_cnt == `pixel_EAV0 + 1;
assign pix_EAV2 = pix_cnt == `pixel_EAV0 + 2;
assign pix_EAV3 = pix_cnt == `pixel_EAV0 + 3;
assign pix_LN0  = pix_cnt == `pixel_EAV0 + 4;
assign pix_LN1  = pix_cnt == `pixel_EAV0 + 5;
assign pix_CRC0 = pix_cnt == `pixel_EAV0 + 6;
assign pix_CRC1 = pix_cnt == `pixel_EAV0 + 7;
assign pix_BLANK = (pix_cnt > `pixel_EAV0 + 7) && (pix_cnt < `pixel_SAV0);  

assign pix_SAV0 = pix_cnt == `pixel_SAV0;
assign pix_SAV1 = pix_cnt == `pixel_SAV0 + 1;
assign pix_SAV2 = pix_cnt == `pixel_SAV0 + 2;
assign pix_SAV3 = pix_cnt == `pixel_SAV0 + 3;


assign line_cnt_end = line_cnt == 1125; 

assign pix_cnt_end = pix_cnt == `LINE_LENGTH;
    



always @(negedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
		pix_cnt <= 0; 
	else 
		if (pix_cnt_end)
			pix_cnt <= 0;  
		else if (state != S_IDLE) 
			pix_cnt <= pix_cnt + 1'b1;	 				
end   




always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
		line_cnt <= 0; 
	else 
		if (line_cnt_end)
			line_cnt <= 0;
		else if (pix_cnt_end) 
			line_cnt <= line_cnt + 1'b1; 				
end 


always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
		i_EN_d <= 0; 
	else 
		i_EN_d <= i_EN;	 				
end

 

always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
		F <= 0; 
	else 

    F <= 0;

end




always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
		line_data_rq <= 0; 
	else 
		if (pix_cnt < `pixel_EAV0 && state == S_FRAME)  
			line_data_rq <= 1'b1;
		else 
			line_data_rq <= 1'b0; 				
end

 

always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
		V <= 0; 
	else 
		V <= ~(state == S_FRAME);
end


always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
		H <= 0; 
	else 
		if ((pix_cnt < 1920) | (pix_cnt > 2196))
		  H <= 0;
		else
		  H <= 1;
				
end


always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
		vsync <= 0; 
	else 
        if (V) 
            vsync <= 1;
        else
            vsync <= 0;
	

end


always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
		hsync <= 0; 
	else 
		if (line_EAV3 & ~H) 
			hsync <= 1'b0;
		else if (line_EAV0) 
			hsync <= 1'b1;		
end





always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
		line_EAV0 <= 0; 
	else     
	   if (state != S_IDLE && (pix_EAV0 || pix_SAV0)) 
	       line_EAV0 <= 1'b1;
	   else 
	       line_EAV0 <= 1'b0; 				
end

always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
        line_EAV1 <= 0; 
	else
        if (pix_EAV1 || pix_SAV1) 
			line_EAV1 <= 1'b1;
		else 
			line_EAV1 <= 1'b0; 				
end

always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
        line_EAV2 <= 0; 
	else
        if (pix_EAV2 || pix_SAV2) 
			line_EAV2 <= 1'b1;
		else 
			line_EAV2 <= 1'b0; 				
end

always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
        line_EAV3 <= 0; 
	else
        if (pix_EAV3 || pix_SAV3) 
			line_EAV3 <= 1'b1;
		else 
			line_EAV3 <= 1'b0; 				
end


always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
        line_LN0 <= 0; 
	else	
        if (pix_LN0) 
			line_LN0 <= 1'b1;
		else 
			line_LN0 <= 1'b0; 				
end

always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
        line_LN1 <= 0; 
	else
        if (pix_LN1) 
			line_LN1 <= 1'b1;
		else 
			line_LN1 <= 1'b0; 				
end

always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
        line_CRC0 <= 0; 
	else	
        if (pix_CRC0) 
			line_CRC0 <= 1'b1;
		else 
			line_CRC0 <= 1'b0; 				
end


always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
        line_CRC1 <= 0; 
	else
        if (pix_CRC1) 
			line_CRC1 <= 1'b1;
		else 
			line_CRC1 <= 1'b0; 				
end


always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
		line_BLANK <= 0; 
	else 
		if (pix_BLANK) 
			line_BLANK <= 1'b1;
		else 
			line_BLANK <= 1'b0; 				
end


reg  [17:0] crcIn_Y, crcIn_C;
wire [17:0] crcOut_Y, crcOut_C;
reg  [9:0]  CRC0_Y, CRC1_Y, CRC0_C, CRC1_C;   
crcSMPTE CRC_Y (
    .crcIn        (crcIn_Y),
    .data         (pdata_Y),
    .crcOut       (crcOut_Y)
);

crcSMPTE CRC_C (
    .crcIn        (crcIn_C),
    .data         (pdata_C),
    .crcOut       (crcOut_C)
);

always @(posedge i_CLK_74m25 or posedge i_RST) 
begin
    if (i_RST)
        begin
           crcIn_Y <= 10'h000;
           CRC0_Y  <= 10'h000;
           CRC1_Y  <= 10'h000;
           CRC0_C  <= 10'h000;
           CRC1_C  <= 10'h000;
        end	    
	else 
	   if (pix_cnt == 0)
           begin
               crcIn_Y <= 10'h000;
               CRC0_Y  <= 10'h000;
               CRC1_Y  <= 10'h000;
               
               crcIn_C <= 10'h000;
               CRC0_C  <= 10'h000;
               CRC1_C  <= 10'h000;
           end
       else
           begin
               crcIn_Y <= crcOut_Y;
               crcIn_C <= crcOut_C;
               
               CRC0_Y  <= {~crcOut_Y[8] , crcOut_Y[8 :0]};
               CRC1_Y  <= {~crcOut_Y[17], crcOut_Y[17:9]};
                 
               CRC0_C  <= {~crcOut_C[8] , crcOut_C[8 :0]};
               CRC1_C  <= {~crcOut_C[17], crcOut_C[17:9]};
       end
    end


reg  [ 9 : 0] pdata_Y, pdata_C; 


always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
	begin
		pdata_Y <= 0;
		pdata_C <= 0;  
	end
	else
    if (line_EAV0)
      begin 
        pdata_Y <= 10'h3ff; 
        pdata_C <= 10'h3ff;
      end
    else if (line_EAV1)
      begin
        pdata_Y <= 10'h000;
        pdata_C <= 10'h000;
      end
    else if (line_EAV2) 
      begin
        pdata_Y <= 10'h000;	
        pdata_C <= 10'h000;
      end
    else if (line_EAV3)
      begin

        pdata_Y <= {1'b1, F, V, H, V^H, F^H, F^V, F^V^H,1'b0, 1'b0 };
        pdata_C <= {1'b1, F, V, H, V^H, F^H, F^V, F^V^H,1'b0, 1'b0 };
      end
    else if (line_LN0)
      begin 

        pdata_Y <= {~LINE_CNT_o[6], LINE_CNT_o[6:0],1'b0,1'b0};
        pdata_C <= {~LINE_CNT_o[6], LINE_CNT_o[6:0],1'b0,1'b0};
      end
    else if (line_LN1) 
      begin

        pdata_Y <= {1'b1  ,1'b0,1'b0,1'b0,LINE_CNT_o[10:7],1'b0, 1'b0};
        pdata_C <= {1'b1  ,1'b0,1'b0,1'b0,LINE_CNT_o[10:7],1'b0, 1'b0}; 
      end
    else if (line_CRC0)
      begin
        pdata_Y <= CRC0_Y;
        pdata_C <= CRC0_C;
      end
    else if (line_CRC1)
      begin
        pdata_Y <= CRC1_Y;
        pdata_C <= CRC1_C;
      end	            	 	 		
    else if (line_BLANK) 
      begin  

        pdata_Y <= 10'h040;
        pdata_C <= 10'h200;	
      end
    else
      begin  
        pdata_Y <= i_data_Y;
        pdata_C <= i_data_C;
      end						
end 


assign PIX_CNT_o  = pix_cnt; 
assign LINE_CNT_o = line_cnt;
assign Y_data_o   = pdata_Y;
assign C_data_o   = pdata_C;
assign VSYNC_o    = vsync;
assign HSYNC_o    = hsync;
assign DATA_RQ_o  = line_data_rq;
    
endmodule
module SMPTE274(

  input 	      i_CLK_74m25,
  input 	      i_RST,
  input           i_EN,

  input  [ 9 : 0] i_data_Y,
  input  [ 9 : 0] i_data_C,
  
  output [11 : 0] PIX_CNT_o,
  output [10 : 0] LINE_CNT_o,

  output          VSYNC_o,
  output          HSYNC_o,
  output          DATA_RQ_o,

  output [ 9 : 0] Y_data_o,
  output [ 9 : 0] C_data_o
  );



reg  [11 : 0] pix_cnt;
reg  [10 : 0] line_cnt;

wire [11 : 0] pix_cnt_end;
wire [10 : 0] line_cnt_end;

reg           i_EN_d;

reg           F; 
reg           V;
reg           H;
reg           line_data_rq; 

reg           line_EAV0; 
reg           line_EAV1;
reg           line_EAV2;
reg           line_EAV3;
reg           line_LN0;
reg           line_LN1;
reg           line_CRC0;
reg           line_CRC1;
reg           line_BLANK;


assign go_vb1    = (i_EN ^ i_EN_d) | line_cnt_end; 

assign go_frame  = line_cnt_42; 
assign go_vb2    = line_cnt_1122;   

localparam    S_IDLE  = 2'b00; 
localparam    S_VB1   = 2'b01; 
localparam    S_FRAME = 2'b10; 
localparam    S_VB2   = 2'b11; 
reg  [ 1 : 0] state;

reg           vsync;
reg           hsync;
 



always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
		state <= S_IDLE; 
	else 
		case (state) 
			S_IDLE : 
				if (go_vb1)
					state <= S_VB1; 
				else 
					state <= S_IDLE;  
			S_VB1 : 
				if (go_frame) 
					state <= S_FRAME;
				else 
					state <= S_VB1; 
			S_FRAME: 
				if (go_vb2) 
					state <= S_VB2;
				else 
					state <= S_FRAME; 
			S_VB2 : 
				if (go_vb1) 
					state <= S_VB1;
				else 
					state <= S_VB2;
			default : 
				state <= S_IDLE;    
		endcase 					 								
end



assign line_cnt_1      = line_cnt == 1    - 1;
assign line_cnt_42     = line_cnt == 42   - 1;
assign line_cnt_1122   = line_cnt == 1122 - 1;

assign pix_EAV0 = pix_cnt == `pixel_EAV0;
assign pix_EAV1 = pix_cnt == `pixel_EAV0 + 1;
assign pix_EAV2 = pix_cnt == `pixel_EAV0 + 2;
assign pix_EAV3 = pix_cnt == `pixel_EAV0 + 3;
assign pix_LN0  = pix_cnt == `pixel_EAV0 + 4;
assign pix_LN1  = pix_cnt == `pixel_EAV0 + 5;
assign pix_CRC0 = pix_cnt == `pixel_EAV0 + 6;
assign pix_CRC1 = pix_cnt == `pixel_EAV0 + 7;
assign pix_BLANK = (pix_cnt > `pixel_EAV0 + 7) && (pix_cnt < `pixel_SAV0);  

assign pix_SAV0 = pix_cnt == `pixel_SAV0;
assign pix_SAV1 = pix_cnt == `pixel_SAV0 + 1;
assign pix_SAV2 = pix_cnt == `pixel_SAV0 + 2;
assign pix_SAV3 = pix_cnt == `pixel_SAV0 + 3;


assign line_cnt_end = line_cnt == 1125; 

assign pix_cnt_end = pix_cnt == `LINE_LENGTH;
    



always @(negedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
		pix_cnt <= 0; 
	else 
		if (pix_cnt_end)
			pix_cnt <= 0;  
		else if (state != S_IDLE) 
			pix_cnt <= pix_cnt + 1'b1;	 				
end   




always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
		line_cnt <= 0; 
	else 
		if (line_cnt_end)
			line_cnt <= 0;
		else if (pix_cnt_end) 
			line_cnt <= line_cnt + 1'b1; 				
end 


always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
		i_EN_d <= 0; 
	else 
		i_EN_d <= i_EN;	 				
end

 

always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
		F <= 0; 
	else 

    F <= 0;

end




always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
		line_data_rq <= 0; 
	else 
		if (pix_cnt < `pixel_EAV0 && state == S_FRAME)  
			line_data_rq <= 1'b1;
		else 
			line_data_rq <= 1'b0; 				
end

 

always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
		V <= 0; 
	else 
		V <= ~(state == S_FRAME);
end


always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
		H <= 0; 
	else 
		if ((pix_cnt < 1920) | (pix_cnt > 2196))
		  H <= 0;
		else
		  H <= 1;
				
end


always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
		vsync <= 0; 
	else 
        if (V) 
            vsync <= 1;
        else
            vsync <= 0;
	

end


always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
		hsync <= 0; 
	else 
		if (line_EAV3 & ~H) 
			hsync <= 1'b0;
		else if (line_EAV0) 
			hsync <= 1'b1;		
end





always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
		line_EAV0 <= 0; 
	else     
	   if (state != S_IDLE && (pix_EAV0 || pix_SAV0)) 
	       line_EAV0 <= 1'b1;
	   else 
	       line_EAV0 <= 1'b0; 				
end

always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
        line_EAV1 <= 0; 
	else
        if (pix_EAV1 || pix_SAV1) 
			line_EAV1 <= 1'b1;
		else 
			line_EAV1 <= 1'b0; 				
end

always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
        line_EAV2 <= 0; 
	else
        if (pix_EAV2 || pix_SAV2) 
			line_EAV2 <= 1'b1;
		else 
			line_EAV2 <= 1'b0; 				
end

always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
        line_EAV3 <= 0; 
	else
        if (pix_EAV3 || pix_SAV3) 
			line_EAV3 <= 1'b1;
		else 
			line_EAV3 <= 1'b0; 				
end


always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
        line_LN0 <= 0; 
	else	
        if (pix_LN0) 
			line_LN0 <= 1'b1;
		else 
			line_LN0 <= 1'b0; 				
end

always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
        line_LN1 <= 0; 
	else
        if (pix_LN1) 
			line_LN1 <= 1'b1;
		else 
			line_LN1 <= 1'b0; 				
end

always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
        line_CRC0 <= 0; 
	else	
        if (pix_CRC0) 
			line_CRC0 <= 1'b1;
		else 
			line_CRC0 <= 1'b0; 				
end


always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
        line_CRC1 <= 0; 
	else
        if (pix_CRC1) 
			line_CRC1 <= 1'b1;
		else 
			line_CRC1 <= 1'b0; 				
end


always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
		line_BLANK <= 0; 
	else 
		if (pix_BLANK) 
			line_BLANK <= 1'b1;
		else 
			line_BLANK <= 1'b0; 				
end


reg  [17:0] crcIn_Y, crcIn_C;
wire [17:0] crcOut_Y, crcOut_C;
reg  [9:0]  CRC0_Y, CRC1_Y, CRC0_C, CRC1_C;   
crcSMPTE CRC_Y (
    .crcIn        (crcIn_Y),
    .data         (pdata_Y),
    .crcOut       (crcOut_Y)
);

crcSMPTE CRC_C (
    .crcIn        (crcIn_C),
    .data         (pdata_C),
    .crcOut       (crcOut_C)
);

always @(posedge i_CLK_74m25 or posedge i_RST) 
begin
    if (i_RST)
        begin
           crcIn_Y <= 10'h000;
           CRC0_Y  <= 10'h000;
           CRC1_Y  <= 10'h000;
           CRC0_C  <= 10'h000;
           CRC1_C  <= 10'h000;
        end	    
	else 
	   if (pix_cnt == 0)
           begin
               crcIn_Y <= 10'h000;
               CRC0_Y  <= 10'h000;
               CRC1_Y  <= 10'h000;
               
               crcIn_C <= 10'h000;
               CRC0_C  <= 10'h000;
               CRC1_C  <= 10'h000;
           end
       else
           begin
               crcIn_Y <= crcOut_Y;
               crcIn_C <= crcOut_C;
               
               CRC0_Y  <= {~crcOut_Y[8] , crcOut_Y[8 :0]};
               CRC1_Y  <= {~crcOut_Y[17], crcOut_Y[17:9]};
                 
               CRC0_C  <= {~crcOut_C[8] , crcOut_C[8 :0]};
               CRC1_C  <= {~crcOut_C[17], crcOut_C[17:9]};
       end
    end


reg  [ 9 : 0] pdata_Y, pdata_C; 


always @(posedge i_CLK_74m25 or posedge i_RST) 
begin 
	if (i_RST)
	begin
		pdata_Y <= 0;
		pdata_C <= 0;  
	end
	else
    if (line_EAV0)
      begin 
        pdata_Y <= 10'h3ff; 
        pdata_C <= 10'h3ff;
      end
    else if (line_EAV1)
      begin
        pdata_Y <= 10'h000;
        pdata_C <= 10'h000;
      end
    else if (line_EAV2) 
      begin
        pdata_Y <= 10'h000;	
        pdata_C <= 10'h000;
      end
    else if (line_EAV3)
      begin

        pdata_Y <= {1'b1, F, V, H, V^H, F^H, F^V, F^V^H,1'b0, 1'b0 };
        pdata_C <= {1'b1, F, V, H, V^H, F^H, F^V, F^V^H,1'b0, 1'b0 };
      end
    else if (line_LN0)
      begin 

        pdata_Y <= {~LINE_CNT_o[6], LINE_CNT_o[6:0],1'b0,1'b0};
        pdata_C <= {~LINE_CNT_o[6], LINE_CNT_o[6:0],1'b0,1'b0};
      end
    else if (line_LN1) 
      begin

        pdata_Y <= {1'b1  ,1'b0,1'b0,1'b0,LINE_CNT_o[10:7],1'b0, 1'b0};
        pdata_C <= {1'b1  ,1'b0,1'b0,1'b0,LINE_CNT_o[10:7],1'b0, 1'b0}; 
      end
    else if (line_CRC0)
      begin
        pdata_Y <= CRC0_Y;
        pdata_C <= CRC0_C;
      end
    else if (line_CRC1)
      begin
        pdata_Y <= CRC1_Y;
        pdata_C <= CRC1_C;
      end	            	 	 		
    else if (line_BLANK) 
      begin  

        pdata_Y <= 10'h040;
        pdata_C <= 10'h200;	
      end
    else
      begin  
        pdata_Y <= i_data_Y;
        pdata_C <= i_data_C;
      end						
end 


assign PIX_CNT_o  = pix_cnt; 
assign LINE_CNT_o = line_cnt;
assign Y_data_o   = pdata_Y;
assign C_data_o   = pdata_C;
assign VSYNC_o    = vsync;
assign HSYNC_o    = hsync;
assign DATA_RQ_o  = line_data_rq;
    
endmodule