data/full_repos/permissive/432650104/src/csa_32x3.v
data/verilator_xmls/de883f1d-6aad-43e9-8662-102359a29fee.xml
module csa_32x3(
                input wire [31:0]  in1,
                input wire [31:0]  in2,
                input wire [31:0]  in3,
                output wire [31:0] sum,
                output wire [31:0] carry
                );

  assign sum = in1 ^ in2 ^ in3;
  assign carry = in1 & in2 | in1 & in3 | in2 & in3;

endmodule
module csa_32x3(
                input wire [31:0]  in1,
                input wire [31:0]  in2,
                input wire [31:0]  in3,
                output wire [31:0] sum,
                output wire [31:0] carry
                );


  assign sum = in1 ^ in2 ^ in3;
  assign carry = in1 & in2 | in1 & in3 | in2 & in3;

endmodule