data/full_repos/permissive/423547971/Verilog Introductory Tutorial Book/modular_verilog_TB.v
1: b'%Error: Cannot find file containing module: Introductory\n        ... Looked in:\n             data/full_repos/permissive/423547971/Verilog/Introductory\n             data/full_repos/permissive/423547971/Verilog/Introductory.v\n             data/full_repos/permissive/423547971/Verilog/Introductory.sv\n             Introductory\n             Introductory.v\n             Introductory.sv\n             obj_dir/Introductory\n             obj_dir/Introductory.v\n             obj_dir/Introductory.sv\n%Error: Cannot find file containing module: Tutorial\n%Error: Cannot find file containing module: Book,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/Verilog\n%Error: Cannot find file containing module: Book/modular_verilog_TB.v\n%Error: Exiting due to 5 error(s)\n'
module modular_verilog_TB;	

reg CLOCK, ENABLE;				
wire [7:0] OUT;	
	

modular_verilog MV1(.CLOCK(CLOCK), .ENABLE(ENABLE), .OUT(OUT));


always #10 CLOCK = !CLOCK;


initial begin
	CLOCK = 0;
	ENABLE = 0;
	#50 ENABLE = 1;
	
	#500 $finish;	
  end
  

initial begin
    $dumpfile("modular_verilog_TB.vcd");
	$dumpvars(0, modular_verilog_TB);
  end
  
endmodule
module modular_verilog_TB;
	

reg CLOCK, ENABLE;				
wire [7:0] OUT;	
	

modular_verilog MV1(.CLOCK(CLOCK), .ENABLE(ENABLE), .OUT(OUT));


always #10 CLOCK = !CLOCK;


initial begin
	CLOCK = 0;
	ENABLE = 0;
	#50 ENABLE = 1;
	
	#500 $finish;	
  end
  

initial begin
    $dumpfile("modular_verilog_TB.vcd");
	$dumpvars(0, modular_verilog_TB);
  end
  
endmodule