data/full_repos/permissive/477158125/xc7/nand2tetris/nand_gate.v
data/verilator_xmls/dadf556e-a2c1-420f-8ca4-0322bb51a945.xml
module top (input_1,
            input_2,
            and_result);
    
    input  input_1;
    input  input_2;
    output and_result;
    
    wire   and_temp;
    
    assign and_temp   = ~(input_1 & input_2);
    assign and_result = and_temp;
endmodule
module top (input_1,
            input_2,
            and_result);

    
    input  input_1;
    input  input_2;
    output and_result;
    
    wire   and_temp;
    
    assign and_temp   = ~(input_1 & input_2);
    assign and_result = and_temp;
endmodule