data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v
1: b'%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new,data/full_repos/permissive/433174928/defines.vh\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new,data/full_repos/permissive/433174928/defines.vh.v\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new,data/full_repos/permissive/433174928/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:95: Define or directive not defined: \'`LUI\'\n            `LUI: begin                   \n            ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:95: syntax error, unexpected \':\', expecting endcase\n            `LUI: begin                   \n                ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:102: Define or directive not defined: \'`AUIPC\'\n            `AUIPC: begin                \n            ^~~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:102: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `AUIPC: begin                \n                    ^~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:108: Define or directive not defined: \'`ADD\'\n                alu_op <= `ADD;                               \n                          ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:108: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                alu_op <= `ADD;                               \n                              ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:111: Define or directive not defined: \'`JAL\'\n            `JAL: begin                  \n            ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:111: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `JAL: begin                  \n                  ^~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:118: Define or directive not defined: \'`ADD\'\n                alu_op <= `ADD;\n                          ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:118: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                alu_op <= `ADD;\n                              ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:121: Define or directive not defined: \'`JALR\'\n            `JALR: begin                 \n            ^~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:121: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `JALR: begin                 \n                   ^~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:127: Define or directive not defined: \'`ADD\'\n                alu_op <= `ADD;\n                          ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:127: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                alu_op <= `ADD;\n                              ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:130: Define or directive not defined: \'`BRANCH\'\n            `BRANCH: begin               \n            ^~~~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:130: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n            `BRANCH: begin               \n                     ^~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:134: syntax error, unexpected <=, expecting IDENTIFIER\n                branch <=1;\n                       ^~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:137: Define or directive not defined: \'`ADD\'\n                alu_op <= `ADD;\n                          ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:141: Define or directive not defined: \'`LOAD\'\n            `LOAD:begin                  \n            ^~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:145: Define or directive not defined: \'`ADD\'\n                alu_op <= `ADD;\n                          ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:149: Define or directive not defined: \'`STORE\'\n            `STORE:begin                 \n            ^~~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:152: Define or directive not defined: \'`ADD\'\n                alu_op <= `ADD;\n                          ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:154: Define or directive not defined: \'`SB\'\n                    `SB:\n                    ^~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:154: syntax error, unexpected \':\', expecting endcase\n                    `SB:\n                       ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:156: Define or directive not defined: \'`SH\'\n                    `SH:\n                    ^~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:158: Define or directive not defined: \'`SW\'\n                    `SW:\n                    ^~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:163: Define or directive not defined: \'`IMM\'\n            `IMM:begin                   \n            ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:166: syntax error, unexpected <=, expecting IDENTIFIER\n                    alu_op <= {instruction[30], funct3};\n                           ^~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:168: syntax error, unexpected <=, expecting IDENTIFIER\n                    alu_op <= {1\'b0, funct3};\n                           ^~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:171: Define or directive not defined: \'`ALU\'\n            `ALU:begin\n            ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:176: Define or directive not defined: \'`FENCE\'\n            `FENCE:begin\n            ^~~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:180: Define or directive not defined: \'`SYSTEM\'\n            `SYSTEM:begin\n            ^~~~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:193: Define or directive not defined: \'`IF\'\n            state <= `IF;\n                     ^~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:210: Define or directive not defined: \'`IF\'\n            `IF: begin                           \n            ^~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:210: syntax error, unexpected \':\', expecting endcase\n            `IF: begin                           \n               ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:212: Define or directive not defined: \'`ID_EX\'\n                next_state <= `ID_EX;\n                              ^~~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:215: Define or directive not defined: \'`ID_EX\'\n            `ID_EX: begin\n            ^~~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:216: Define or directive not defined: \'`HALT\'\n                if(halt) next_state <= `HALT;\n                                       ^~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:218: Define or directive not defined: \'`MEM\'\n                    next_state <= `MEM;\n                                  ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:220: Define or directive not defined: \'`WB\'\n                    next_state <= `WB;\n                                  ^~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:223: Define or directive not defined: \'`MEM\'\n            `MEM: begin                          \n            ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:225: syntax error, unexpected <=, expecting IDENTIFIER\n                if (store)  dmem_we <= dmem_we_temp;\n                                    ^~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:226: Define or directive not defined: \'`WB\'\n                next_state <= `WB;\n                              ^~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:229: Define or directive not defined: \'`WB\'\n            `WB: begin                           \n            ^~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:232: syntax error, unexpected <=, expecting IDENTIFIER\n                    rf_we <=1;\n                          ^~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:234: syntax error, unexpected <=, expecting IDENTIFIER\n                next_state <= `IF;\n                           ^~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:234: Define or directive not defined: \'`IF\'\n                next_state <= `IF;\n                              ^~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:237: Define or directive not defined: \'`HALT\'\n            `HALT: begin                 \n            ^~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ControlUnit.v:238: Define or directive not defined: \'`HALT\'\n                next_state <= `HALT;\n                              ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module ControlUnit(
    input wire clk, 
    input wire rstn, 
    input wire [31:0] instruction,
 

    output reg pc_we,


    output reg imem_rd,


    output reg rf_we,
    

    output reg [2:0] imm_op,    


    output reg [2:0] data_op,


    input wire bc_out,
    output reg [2:0] bc_op,
    

    output reg [3:0] alu_op,
    

    output reg [3:0] dmem_we,
    output reg dmem_rd,
    

    output reg pc_mux,
    output reg rfile_mux,
    output reg alu_mux1,
    output reg alu_mux2,
    output reg [1:0] op_mux
    
    );
    

    
    reg [6:0] opcode;
    reg [2:0] funct3;
    reg [6:0] funct7;
    

    reg load;
    reg store;
    reg branch;
    reg fence;
    reg [3:0] dmem_we_temp;
    reg halt;
    

     reg [0:2] state;
     reg [0:2] next_state;

     

    always@(*) begin


        opcode <= instruction[6:0];   
        funct3 <= instruction[14:12]; 
        funct7 <= instruction[31:25];   


        load <= 0;
        store <= 0;
        branch <=0;
        fence <=0;
        halt <=0;
        

        pc_mux <= 0;
        rfile_mux <= 0;
        alu_mux1 <= 0;
        alu_mux2 <= 0;
        op_mux <= 0;
        

        imm_op <= 0;
        data_op <= 0;
        bc_op <= 0;
        alu_op <= 0;
        dmem_we_temp <= 0;

        case(opcode)
            `LUI: begin


                op_mux <= 2'd2;
                imm_op <= 3'd4;        
            end
     
            `AUIPC: begin



                alu_mux1 <= 1;
                imm_op <=3'd4;          
                alu_op <= `ADD;                               
            end
            
            `JAL: begin


                pc_mux <= 1;
                rfile_mux <= 1;
                alu_mux1 <= 1;
                imm_op <= 3'd0;                 
                alu_op <= `ADD;
            end
            
            `JALR: begin


                pc_mux <= 1;
                rfile_mux <= 1;
                imm_op <= 3'd1;          
                alu_op <= `ADD;
            end
            
            `BRANCH: begin
                if(bc_out ==1) begin
                    pc_mux <= 1;
                end
                branch <=1;
                alu_mux1 <= 1;
                imm_op <= 3'd2;        
                alu_op <= `ADD;
                bc_op <= funct3;
            end
            
            `LOAD:begin
                load <= 1;
                op_mux <= 2'd1;
                imm_op <= 3'd1;         
                alu_op <= `ADD;
                data_op <= funct3;
            end
            
            `STORE:begin
                store<=1;
                imm_op <= 3'd3;         
                alu_op <= `ADD;
                case (funct3)
                    `SB:
                        dmem_we_temp <= 4'b0001;
                    `SH:
                        dmem_we_temp <= 4'b0011;
                    `SW:
                        dmem_we_temp <= 4'b1111;
                endcase
            end
            
            `IMM:begin
                imm_op <= 3'd1;             
                if (funct3 == 3'b101)
                    alu_op <= {instruction[30], funct3};
                else
                    alu_op <= {1'b0, funct3};
            end
            
            `ALU:begin
                alu_mux2 <= 1;
                alu_op <= {instruction[30], funct3};
            end
            
            `FENCE:begin
                fence <= 1;
            end
            
            `SYSTEM:begin
                halt<=1;
            end
            default: begin

            end
        endcase
    end
    


    always @(posedge clk or negedge rstn) begin
        if(!rstn) begin
            state <= `IF;
        end
        else
            state <= next_state;    
    end
    

    always @(state,halt,load,store,branch,fence,dmem_we_temp) begin
        imem_rd <= 0;
        pc_we <= 0;
        rf_we <= 0;
        dmem_rd <= 0;
        dmem_we <= 4'd0;
        next_state <= 0;
        
        case (state)

            `IF: begin
                imem_rd <= 1;
                next_state <= `ID_EX;
            end

            `ID_EX: begin
                if(halt) next_state <= `HALT;
                else if (load | store)
                    next_state <= `MEM;
                else
                    next_state <= `WB;
            end

            `MEM: begin
                if (load)  dmem_rd <= 1;
                if (store)  dmem_we <= dmem_we_temp;
                next_state <= `WB;
            end

            `WB: begin
                pc_we <= 1;
                if (!(store | branch | fence))  begin
                    rf_we <=1;
                end
                next_state <= `IF;
            end

            `HALT: begin
                next_state <= `HALT;
            end
       endcase
    end
endmodule
module ControlUnit(
    input wire clk, 
    input wire rstn, 
    input wire [31:0] instruction,
 

    output reg pc_we,


    output reg imem_rd,


    output reg rf_we,
    

    output reg [2:0] imm_op,    


    output reg [2:0] data_op,


    input wire bc_out,
    output reg [2:0] bc_op,
    

    output reg [3:0] alu_op,
    

    output reg [3:0] dmem_we,
    output reg dmem_rd,
    

    output reg pc_mux,
    output reg rfile_mux,
    output reg alu_mux1,
    output reg alu_mux2,
    output reg [1:0] op_mux
    
    );

    

    
    reg [6:0] opcode;
    reg [2:0] funct3;
    reg [6:0] funct7;
    

    reg load;
    reg store;
    reg branch;
    reg fence;
    reg [3:0] dmem_we_temp;
    reg halt;
    

     reg [0:2] state;
     reg [0:2] next_state;

     

    always@(*) begin


        opcode <= instruction[6:0];   
        funct3 <= instruction[14:12]; 
        funct7 <= instruction[31:25];   


        load <= 0;
        store <= 0;
        branch <=0;
        fence <=0;
        halt <=0;
        

        pc_mux <= 0;
        rfile_mux <= 0;
        alu_mux1 <= 0;
        alu_mux2 <= 0;
        op_mux <= 0;
        

        imm_op <= 0;
        data_op <= 0;
        bc_op <= 0;
        alu_op <= 0;
        dmem_we_temp <= 0;

        case(opcode)
            `LUI: begin


                op_mux <= 2'd2;
                imm_op <= 3'd4;        
            end
     
            `AUIPC: begin



                alu_mux1 <= 1;
                imm_op <=3'd4;          
                alu_op <= `ADD;                               
            end
            
            `JAL: begin


                pc_mux <= 1;
                rfile_mux <= 1;
                alu_mux1 <= 1;
                imm_op <= 3'd0;                 
                alu_op <= `ADD;
            end
            
            `JALR: begin


                pc_mux <= 1;
                rfile_mux <= 1;
                imm_op <= 3'd1;          
                alu_op <= `ADD;
            end
            
            `BRANCH: begin
                if(bc_out ==1) begin
                    pc_mux <= 1;
                end
                branch <=1;
                alu_mux1 <= 1;
                imm_op <= 3'd2;        
                alu_op <= `ADD;
                bc_op <= funct3;
            end
            
            `LOAD:begin
                load <= 1;
                op_mux <= 2'd1;
                imm_op <= 3'd1;         
                alu_op <= `ADD;
                data_op <= funct3;
            end
            
            `STORE:begin
                store<=1;
                imm_op <= 3'd3;         
                alu_op <= `ADD;
                case (funct3)
                    `SB:
                        dmem_we_temp <= 4'b0001;
                    `SH:
                        dmem_we_temp <= 4'b0011;
                    `SW:
                        dmem_we_temp <= 4'b1111;
                endcase
            end
            
            `IMM:begin
                imm_op <= 3'd1;             
                if (funct3 == 3'b101)
                    alu_op <= {instruction[30], funct3};
                else
                    alu_op <= {1'b0, funct3};
            end
            
            `ALU:begin
                alu_mux2 <= 1;
                alu_op <= {instruction[30], funct3};
            end
            
            `FENCE:begin
                fence <= 1;
            end
            
            `SYSTEM:begin
                halt<=1;
            end
            default: begin

            end
        endcase
    end
    


    always @(posedge clk or negedge rstn) begin
        if(!rstn) begin
            state <= `IF;
        end
        else
            state <= next_state;    
    end
    

    always @(state,halt,load,store,branch,fence,dmem_we_temp) begin
        imem_rd <= 0;
        pc_we <= 0;
        rf_we <= 0;
        dmem_rd <= 0;
        dmem_we <= 4'd0;
        next_state <= 0;
        
        case (state)

            `IF: begin
                imem_rd <= 1;
                next_state <= `ID_EX;
            end

            `ID_EX: begin
                if(halt) next_state <= `HALT;
                else if (load | store)
                    next_state <= `MEM;
                else
                    next_state <= `WB;
            end

            `MEM: begin
                if (load)  dmem_rd <= 1;
                if (store)  dmem_we <= dmem_we_temp;
                next_state <= `WB;
            end

            `WB: begin
                pc_we <= 1;
                if (!(store | branch | fence))  begin
                    rf_we <=1;
                end
                next_state <= `IF;
            end

            `HALT: begin
                next_state <= `HALT;
            end
       endcase
    end
endmodule