data/full_repos/permissive/474721296/full_adder/full_adder.v
data/verilator_xmls/c5377958-c4d4-4115-9f33-15932257bcc4.xml
module full_adder(
		input A, B, Cin,
		output S, Cout
	);

	wire inter;

	assign inter = A ^ B;
	assign S = inter ^ Cin;
	assign Cout = (inter & Cin) + (A & B);
endmodule
module full_adder(
		input A, B, Cin,
		output S, Cout
	);


	wire inter;

	assign inter = A ^ B;
	assign S = inter ^ Cin;
	assign Cout = (inter & Cin) + (A & B);
endmodule