data/full_repos/permissive/441359809/src/yosys/tests/various/constmsk_test.v
1: b'%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/constmsk_test.v:2: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s REDOR generates 1 bits.\n                                                                                              : ... In instance test\n    assign Y1 = |{A[3], 1\'b0, A[1]};\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/constmsk_test.v:3: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s REDOR generates 1 bits.\n                                                                                              : ... In instance test\n    assign Y2 = |{A[2], 1\'b1, A[0]};\n              ^\n%Error: Exiting due to 2 warning(s)\n'
module test(input [3:0] A, output [3:0] Y1, Y2);
    assign Y1 = |{A[3], 1'b0, A[1]};
    assign Y2 = |{A[2], 1'b1, A[0]};
endmodule
module test(input [3:0] A, output [3:0] Y1, Y2);

    assign Y1 = |{A[3], 1'b0, A[1]};
    assign Y2 = |{A[2], 1'b1, A[0]};
endmodule