data/full_repos/permissive/418819021/lab-04/decode_unit.v
1: b'%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:5: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418819021/lab-04,data/full_repos/permissive/418819021/defines.vh\n             data/full_repos/permissive/418819021/lab-04,data/full_repos/permissive/418819021/defines.vh.v\n             data/full_repos/permissive/418819021/lab-04,data/full_repos/permissive/418819021/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:12: Define or directive not defined: \'`OPCODE_COUNT\'\n  output reg   [`OPCODE_COUNT-1:0] opcode_type,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:13: Define or directive not defined: \'`GROUP_COUNT\'\n  output wire  [`GROUP_COUNT-1:0]  opcode_group,\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:30: Define or directive not defined: \'`TYPE_ADD\'\n    opcode_type = `TYPE_ADD;\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:30: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    opcode_type = `TYPE_ADD;\n                           ^\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:35: Define or directive not defined: \'`TYPE_ADC\'\n    opcode_type = `TYPE_ADC;\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:35: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    opcode_type = `TYPE_ADC;\n                           ^\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:40: Define or directive not defined: \'`TYPE_AND\'\n    opcode_type = `TYPE_AND;\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:40: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    opcode_type = `TYPE_AND;\n                           ^\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:46: Define or directive not defined: \'`TYPE_EOR\'\n    opcode_type = `TYPE_EOR;\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:46: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    opcode_type = `TYPE_EOR;\n                           ^\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:51: Define or directive not defined: \'`TYPE_LD_Y\'\n    opcode_type = `TYPE_LD_Y;\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:51: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    opcode_type = `TYPE_LD_Y;\n                            ^\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:58: Define or directive not defined: \'`TYPE_LDI\'\n    opcode_type = `TYPE_LDI;\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:58: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    opcode_type = `TYPE_LDI;\n                           ^\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:65: Define or directive not defined: \'`TYPE_LDS\'\n    opcode_type = `TYPE_LDS;\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:65: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    opcode_type = `TYPE_LDS;\n                           ^\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:74: Define or directive not defined: \'`TYPE_MOV\'\n    opcode_type = `TYPE_MOV;\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:74: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    opcode_type = `TYPE_MOV;\n                           ^\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:81: Define or directive not defined: \'`TYPE_NEG\'\n    opcode_type = `TYPE_NEG;\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:81: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    opcode_type = `TYPE_NEG;\n                           ^\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:86: Define or directive not defined: \'`TYPE_NOP\'\n    opcode_type = `TYPE_NOP;\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:86: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    opcode_type = `TYPE_NOP;\n                           ^\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:92: Define or directive not defined: \'`TYPE_OR\'\n    opcode_type = `TYPE_OR;\n                  ^~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:92: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    opcode_type = `TYPE_OR;\n                          ^\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:98: Define or directive not defined: \'`TYPE_SUB\'\n    opcode_type = `TYPE_SUB;\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:98: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    opcode_type = `TYPE_SUB;\n                           ^\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:104: Define or directive not defined: \'`TYPE_STS\'\n    opcode_type = `TYPE_STS;\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:104: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    opcode_type = `TYPE_STS;\n                           ^\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:121: Define or directive not defined: \'`TYPE_PUSH\'\n    opcode_type = `TYPE_PUSH;\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:121: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    opcode_type = `TYPE_PUSH;\n                            ^\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:130: Define or directive not defined: \'`TYPE_POP\'\n    opcode_type = `TYPE_POP;\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:130: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    opcode_type = `TYPE_POP;\n                           ^\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:139: Define or directive not defined: \'`TYPE_RJMP\'\n    opcode_type = `TYPE_RJMP;\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:139: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    opcode_type = `TYPE_RJMP;\n                            ^\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:148: Define or directive not defined: \'`TYPE_BRBS\'\n    opcode_type = `TYPE_BRBS;\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:148: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    opcode_type = `TYPE_BRBS;\n                            ^\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:157: Define or directive not defined: \'`TYPE_BRBC\'\n    opcode_type = `TYPE_BRBC;\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:157: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    opcode_type = `TYPE_BRBC;\n                            ^\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:166: Define or directive not defined: \'`TYPE_UNKNOWN\'\n    opcode_type = `TYPE_UNKNOWN;\n                  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:166: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    opcode_type = `TYPE_UNKNOWN;\n                               ^\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:174: Define or directive not defined: \'`GROUP_ALU_ONE_OP\'\n assign opcode_group[`GROUP_ALU_ONE_OP] =\n                     ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:174: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign opcode_group[`GROUP_ALU_ONE_OP] =\n                                      ^\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:175: Define or directive not defined: \'`TYPE_NEG\'\n  (opcode_type == `TYPE_NEG);\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:177: Define or directive not defined: \'`GROUP_ALU_TWO_OP\'\n assign opcode_group[`GROUP_ALU_TWO_OP] =\n                     ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:177: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign opcode_group[`GROUP_ALU_TWO_OP] =\n                                      ^\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:178: Define or directive not defined: \'`TYPE_ADD\'\n  (opcode_type == `TYPE_ADD) ||\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:179: Define or directive not defined: \'`TYPE_ADC\'\n  (opcode_type == `TYPE_ADC) ||\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:180: Define or directive not defined: \'`TYPE_SUB\'\n  (opcode_type == `TYPE_SUB) ||\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-04/decode_unit.v:181: Define or directive not defined: \'`TYPE_AND\'\n  (opcode_type == `TYPE_AND) ||\n                  ^~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module decode_unit #(
		parameter  INSTR_WIDTH  = 16,
		parameter  R_ADDR_WIDTH = 5

	)(
		input  wire  [INSTR_WIDTH-1:0]   instruction,
		output reg   [`OPCODE_COUNT-1:0] opcode_type,
		output wire  [`GROUP_COUNT-1:0]  opcode_group,
		output reg   [R_ADDR_WIDTH-1:0]  opcode_rd,
		output reg   [R_ADDR_WIDTH-1:0]  opcode_rr,
		output reg               [11:0]  opcode_imd,
		output reg                [2:0]  opcode_bit
	);



	always @* begin
		  casez (instruction)
			16'b0000_11??_????_????: begin
				opcode_type = `TYPE_ADD;
				opcode_rd   = instruction[8:4];
				opcode_rr   = {instruction[9], instruction[3:0]};
			end
			16'b0001_11??_????_????: begin
				opcode_type = `TYPE_ADC;
				opcode_rd   = instruction[8:4];
				opcode_rr   = {instruction[9], instruction[3:0]};
			end
			16'b0010_00??_????_????: begin
				opcode_type = `TYPE_AND;
				opcode_rd   = instruction[8:4];
				opcode_rr   = {instruction[9], instruction[3:0]};
			end
	
			16'b0010_01??_????_????: begin
				opcode_type = `TYPE_EOR;
				opcode_rd   = instruction[8:4];
				opcode_rr   = {instruction[9], instruction[3:0]};
			end
				16'b1000_000?_????_1000: begin
				opcode_type = `TYPE_LD_Y;
				opcode_rd   = instruction[8:4];
				opcode_rr   = {R_ADDR_WIDTH{1'bx}};
				opcode_bit  = 3'bx;
				opcode_imd  = 12'bx;
			end
			16'b1110_????_????_????: begin
				opcode_type = `TYPE_LDI;
				opcode_rd   = {1'b1, instruction[7:4]};
				opcode_rr   = {R_ADDR_WIDTH{1'bx}};
				opcode_bit  = 3'bx;
				opcode_imd  = {4'b0, instruction[11:8], instruction[3:0]};
			end
			16'b1010_0???_????_????: begin
				opcode_type = `TYPE_LDS;
				opcode_rd   = {1'b1, instruction[7:4]};
				opcode_rr   = {R_ADDR_WIDTH{1'bx}};
				opcode_bit  = 3'bx;

				opcode_imd  = {4'd0, ~instruction[8], instruction[8],
							  instruction[10:9], instruction[3:0]};
			end
				16'b0010_11??_????_????: begin
				opcode_type = `TYPE_MOV;
				opcode_rd   = instruction[8:4];
				opcode_rr   = {instruction[9], instruction[3:0]};
				opcode_bit  = 3'bx;
				opcode_imd  = 12'bx;
			end
				16'b1001_010?_????_0001: begin
				opcode_type = `TYPE_NEG;
				opcode_rd   = instruction[8:4];
				opcode_rr   = {R_ADDR_WIDTH{1'bx}};
			end
			16'b0000_0000_0000_0000: begin
				opcode_type = `TYPE_NOP;
				opcode_rd   = {R_ADDR_WIDTH{1'bx}};
				opcode_rr   = {R_ADDR_WIDTH{1'bx}};
			end
			
			16'b0010_10??_????_????: begin
				opcode_type = `TYPE_OR;
				opcode_rd   = instruction[8:4];
				opcode_rr   = {instruction[9], instruction[3:0]};
			end
			
			16'b0001_10??_????_????: begin
				opcode_type = `TYPE_SUB;
				opcode_rd   = instruction[8:4];
				opcode_rr   = {instruction[9], instruction[3:0]};
			end
			
			16'b1010_1???_????_????: begin
				opcode_type = `TYPE_STS;
				opcode_rd   = {R_ADDR_WIDTH{1'bx}};
				opcode_rr   = {1'b1, instruction[7:4]};
				opcode_bit  = 3'bx;

				opcode_imd  = {4'd0, ~instruction[8], instruction[8],
							  instruction[10:9], instruction[3:0]};
			end
			

			

			

			

			16'b1001_001?_????_1111: begin
				opcode_type = `TYPE_PUSH;
				opcode_rd   = {R_ADDR_WIDTH{1'bx}};
				opcode_rr   = {instruction[8:4]};
				opcode_bit  = 3'bx;

				opcode_imd  = {12'bx};
			end

			16'b1001_000?_????_1111: begin
				opcode_type = `TYPE_POP;
				opcode_rd   = {instruction[8:4]};
				opcode_rr   = {R_ADDR_WIDTH{1'bx}};
				opcode_bit  = 3'bx;

				opcode_imd  = {12'bx};
			end

			16'b1100_????_????_????: begin
				opcode_type = `TYPE_RJMP;
				opcode_rd   = {R_ADDR_WIDTH{1'bx}};
				opcode_rr   = {R_ADDR_WIDTH{1'bx}};
				opcode_bit  = 3'bx;

				opcode_imd  = instruction[11:0];
			end

			16'b1111_00??_????_????: begin
				opcode_type = `TYPE_BRBS;
				opcode_rd   = {R_ADDR_WIDTH{1'bx}};
				opcode_rr   = {R_ADDR_WIDTH{1'bx}};
				opcode_bit  = instruction[2:0];

				opcode_imd  = {5'd0, instruction[9:3]};
			end
			
			16'b1111_01??_????_????: begin
				opcode_type = `TYPE_BRBC;
				opcode_rd   = {R_ADDR_WIDTH{1'bx}};
				opcode_rr   = {R_ADDR_WIDTH{1'bx}};
				opcode_bit  = instruction[2:0];

				opcode_imd  = {5'd0, instruction[9:3]};
			end

			default: begin
				opcode_type = `TYPE_UNKNOWN;
				opcode_rd   = {R_ADDR_WIDTH{1'bx}};
				opcode_rr   = {R_ADDR_WIDTH{1'bx}};
			end
		  endcase
	end
	

	assign opcode_group[`GROUP_ALU_ONE_OP] =
		(opcode_type == `TYPE_NEG);
		
	assign opcode_group[`GROUP_ALU_TWO_OP] =
		(opcode_type == `TYPE_ADD) ||
		(opcode_type == `TYPE_ADC) ||
		(opcode_type == `TYPE_SUB) ||
		(opcode_type == `TYPE_AND) ||
		(opcode_type == `TYPE_EOR) ||
		(opcode_type == `TYPE_OR);
	
	assign opcode_group[`GROUP_ALU] =
		opcode_group[`GROUP_ALU_ONE_OP] ||
		opcode_group[`GROUP_ALU_TWO_OP];


	assign opcode_group[`GROUP_LOAD_DIRECT] =
		(opcode_type == `TYPE_LDS);
	

	assign opcode_group[`GROUP_LOAD_INDIRECT] =
		(opcode_type == `TYPE_LD_Y) ||
		(opcode_type == `TYPE_POP);
	assign opcode_group[`GROUP_STORE_DIRECT] =
		(opcode_type == `TYPE_STS)
		;
		

	assign opcode_group[`GROUP_STORE_INDIRECT] = 
		(opcode_type == `TYPE_PUSH); 


	assign opcode_group[`GROUP_REGISTER] =
		(opcode_type == `TYPE_LDI) ||
		(opcode_type == `TYPE_MOV)
		;
  

    assign opcode_group[`GROUP_CONTROL_FLOW] = 
		(opcode_type == `TYPE_RJMP) ||
		(opcode_type == `TYPE_BRBS) ||
		(opcode_type == `TYPE_BRBC);
		


	assign opcode_group[`GROUP_LOAD] =
		opcode_group[`GROUP_LOAD_DIRECT] ||
		opcode_group[`GROUP_LOAD_INDIRECT];
		
	assign opcode_group[`GROUP_STORE] =
		opcode_group[`GROUP_STORE_DIRECT] ||
		opcode_group[`GROUP_STORE_INDIRECT];
	

	assign opcode_group[`GROUP_STACK]  = 
		(opcode_type == `TYPE_PUSH) ||
		(opcode_type == `TYPE_POP);

	assign opcode_group[`GROUP_MEMORY] =
		(opcode_group[`GROUP_LOAD] ||
		 opcode_group[`GROUP_STORE]);
endmodule
module decode_unit #(
		parameter  INSTR_WIDTH  = 16,
		parameter  R_ADDR_WIDTH = 5

	)(
		input  wire  [INSTR_WIDTH-1:0]   instruction,
		output reg   [`OPCODE_COUNT-1:0] opcode_type,
		output wire  [`GROUP_COUNT-1:0]  opcode_group,
		output reg   [R_ADDR_WIDTH-1:0]  opcode_rd,
		output reg   [R_ADDR_WIDTH-1:0]  opcode_rr,
		output reg               [11:0]  opcode_imd,
		output reg                [2:0]  opcode_bit
	);




	always @* begin
		  casez (instruction)
			16'b0000_11??_????_????: begin
				opcode_type = `TYPE_ADD;
				opcode_rd   = instruction[8:4];
				opcode_rr   = {instruction[9], instruction[3:0]};
			end
			16'b0001_11??_????_????: begin
				opcode_type = `TYPE_ADC;
				opcode_rd   = instruction[8:4];
				opcode_rr   = {instruction[9], instruction[3:0]};
			end
			16'b0010_00??_????_????: begin
				opcode_type = `TYPE_AND;
				opcode_rd   = instruction[8:4];
				opcode_rr   = {instruction[9], instruction[3:0]};
			end
	
			16'b0010_01??_????_????: begin
				opcode_type = `TYPE_EOR;
				opcode_rd   = instruction[8:4];
				opcode_rr   = {instruction[9], instruction[3:0]};
			end
				16'b1000_000?_????_1000: begin
				opcode_type = `TYPE_LD_Y;
				opcode_rd   = instruction[8:4];
				opcode_rr   = {R_ADDR_WIDTH{1'bx}};
				opcode_bit  = 3'bx;
				opcode_imd  = 12'bx;
			end
			16'b1110_????_????_????: begin
				opcode_type = `TYPE_LDI;
				opcode_rd   = {1'b1, instruction[7:4]};
				opcode_rr   = {R_ADDR_WIDTH{1'bx}};
				opcode_bit  = 3'bx;
				opcode_imd  = {4'b0, instruction[11:8], instruction[3:0]};
			end
			16'b1010_0???_????_????: begin
				opcode_type = `TYPE_LDS;
				opcode_rd   = {1'b1, instruction[7:4]};
				opcode_rr   = {R_ADDR_WIDTH{1'bx}};
				opcode_bit  = 3'bx;

				opcode_imd  = {4'd0, ~instruction[8], instruction[8],
							  instruction[10:9], instruction[3:0]};
			end
				16'b0010_11??_????_????: begin
				opcode_type = `TYPE_MOV;
				opcode_rd   = instruction[8:4];
				opcode_rr   = {instruction[9], instruction[3:0]};
				opcode_bit  = 3'bx;
				opcode_imd  = 12'bx;
			end
				16'b1001_010?_????_0001: begin
				opcode_type = `TYPE_NEG;
				opcode_rd   = instruction[8:4];
				opcode_rr   = {R_ADDR_WIDTH{1'bx}};
			end
			16'b0000_0000_0000_0000: begin
				opcode_type = `TYPE_NOP;
				opcode_rd   = {R_ADDR_WIDTH{1'bx}};
				opcode_rr   = {R_ADDR_WIDTH{1'bx}};
			end
			
			16'b0010_10??_????_????: begin
				opcode_type = `TYPE_OR;
				opcode_rd   = instruction[8:4];
				opcode_rr   = {instruction[9], instruction[3:0]};
			end
			
			16'b0001_10??_????_????: begin
				opcode_type = `TYPE_SUB;
				opcode_rd   = instruction[8:4];
				opcode_rr   = {instruction[9], instruction[3:0]};
			end
			
			16'b1010_1???_????_????: begin
				opcode_type = `TYPE_STS;
				opcode_rd   = {R_ADDR_WIDTH{1'bx}};
				opcode_rr   = {1'b1, instruction[7:4]};
				opcode_bit  = 3'bx;

				opcode_imd  = {4'd0, ~instruction[8], instruction[8],
							  instruction[10:9], instruction[3:0]};
			end
			

			

			

			

			16'b1001_001?_????_1111: begin
				opcode_type = `TYPE_PUSH;
				opcode_rd   = {R_ADDR_WIDTH{1'bx}};
				opcode_rr   = {instruction[8:4]};
				opcode_bit  = 3'bx;

				opcode_imd  = {12'bx};
			end

			16'b1001_000?_????_1111: begin
				opcode_type = `TYPE_POP;
				opcode_rd   = {instruction[8:4]};
				opcode_rr   = {R_ADDR_WIDTH{1'bx}};
				opcode_bit  = 3'bx;

				opcode_imd  = {12'bx};
			end

			16'b1100_????_????_????: begin
				opcode_type = `TYPE_RJMP;
				opcode_rd   = {R_ADDR_WIDTH{1'bx}};
				opcode_rr   = {R_ADDR_WIDTH{1'bx}};
				opcode_bit  = 3'bx;

				opcode_imd  = instruction[11:0];
			end

			16'b1111_00??_????_????: begin
				opcode_type = `TYPE_BRBS;
				opcode_rd   = {R_ADDR_WIDTH{1'bx}};
				opcode_rr   = {R_ADDR_WIDTH{1'bx}};
				opcode_bit  = instruction[2:0];

				opcode_imd  = {5'd0, instruction[9:3]};
			end
			
			16'b1111_01??_????_????: begin
				opcode_type = `TYPE_BRBC;
				opcode_rd   = {R_ADDR_WIDTH{1'bx}};
				opcode_rr   = {R_ADDR_WIDTH{1'bx}};
				opcode_bit  = instruction[2:0];

				opcode_imd  = {5'd0, instruction[9:3]};
			end

			default: begin
				opcode_type = `TYPE_UNKNOWN;
				opcode_rd   = {R_ADDR_WIDTH{1'bx}};
				opcode_rr   = {R_ADDR_WIDTH{1'bx}};
			end
		  endcase
	end
	

	assign opcode_group[`GROUP_ALU_ONE_OP] =
		(opcode_type == `TYPE_NEG);
		
	assign opcode_group[`GROUP_ALU_TWO_OP] =
		(opcode_type == `TYPE_ADD) ||
		(opcode_type == `TYPE_ADC) ||
		(opcode_type == `TYPE_SUB) ||
		(opcode_type == `TYPE_AND) ||
		(opcode_type == `TYPE_EOR) ||
		(opcode_type == `TYPE_OR);
	
	assign opcode_group[`GROUP_ALU] =
		opcode_group[`GROUP_ALU_ONE_OP] ||
		opcode_group[`GROUP_ALU_TWO_OP];


	assign opcode_group[`GROUP_LOAD_DIRECT] =
		(opcode_type == `TYPE_LDS);
	

	assign opcode_group[`GROUP_LOAD_INDIRECT] =
		(opcode_type == `TYPE_LD_Y) ||
		(opcode_type == `TYPE_POP);
	assign opcode_group[`GROUP_STORE_DIRECT] =
		(opcode_type == `TYPE_STS)
		;
		

	assign opcode_group[`GROUP_STORE_INDIRECT] = 
		(opcode_type == `TYPE_PUSH); 


	assign opcode_group[`GROUP_REGISTER] =
		(opcode_type == `TYPE_LDI) ||
		(opcode_type == `TYPE_MOV)
		;
  

    assign opcode_group[`GROUP_CONTROL_FLOW] = 
		(opcode_type == `TYPE_RJMP) ||
		(opcode_type == `TYPE_BRBS) ||
		(opcode_type == `TYPE_BRBC);
		


	assign opcode_group[`GROUP_LOAD] =
		opcode_group[`GROUP_LOAD_DIRECT] ||
		opcode_group[`GROUP_LOAD_INDIRECT];
		
	assign opcode_group[`GROUP_STORE] =
		opcode_group[`GROUP_STORE_DIRECT] ||
		opcode_group[`GROUP_STORE_INDIRECT];
	

	assign opcode_group[`GROUP_STACK]  = 
		(opcode_type == `TYPE_PUSH) ||
		(opcode_type == `TYPE_POP);

	assign opcode_group[`GROUP_MEMORY] =
		(opcode_group[`GROUP_LOAD] ||
		 opcode_group[`GROUP_STORE]);
endmodule