data/full_repos/permissive/489980666/vivado_proj/ip_rtl/sdc/sd_cmd_serial_host.v
data/verilator_xmls/feb16571-b9ce-4c1b-8518-e220ebabf137.xml
module sd_crc_7(
   input        BITVAL,
   input        ENABLE,
   input        BITSTRB,
   input        CLEAR,
   output reg [6:0] CRC
);

wire inv;
assign inv = BITVAL ^ CRC[6];

always @(posedge BITSTRB or posedge CLEAR) begin
    if (CLEAR) begin
        CRC <= 0;
    end else if (ENABLE == 1) begin
        CRC[6] <= CRC[5];
        CRC[5] <= CRC[4];
        CRC[4] <= CRC[3];
        CRC[3] <= CRC[2] ^ inv;
        CRC[2] <= CRC[1];
        CRC[1] <= CRC[0];
        CRC[0] <= inv;
    end
end

endmodule
module sd_crc_7(
   input        BITVAL,
   input        ENABLE,
   input        BITSTRB,
   input        CLEAR,
   output reg [6:0] CRC
);


wire inv;
assign inv = BITVAL ^ CRC[6];

always @(posedge BITSTRB or posedge CLEAR) begin
    if (CLEAR) begin
        CRC <= 0;
    end else if (ENABLE == 1) begin
        CRC[6] <= CRC[5];
        CRC[5] <= CRC[4];
        CRC[4] <= CRC[3];
        CRC[3] <= CRC[2] ^ inv;
        CRC[2] <= CRC[1];
        CRC[1] <= CRC[0];
        CRC[0] <= inv;
    end
end

endmodule