data/full_repos/permissive/495056011/cpld/driver_test.v
data/verilator_xmls/1a6404fc-4693-460f-bb1a-54bf28c3f4db.xml
module driver_test (
  input wire clk,
  input wire [7:0] a,
  input wire iorq_n,
  output wire [7:0] d,
  output wire busdir
  );
  
  reg [29:0] cont;
  always @(posedge clk)
    cont <= cont + 30'd1;
  
  wire acceso = |{iorq_n,a[7:1]};
  assign busdir = acceso;
  wire port00 = ~acceso & ~a[0];
  wire port01 = ~acceso &  a[0];
  
  assign d = (port00)? cont[21:14] :
             (port01)? cont[29:22] :
             8'hZZ;
endmodule
module driver_test (
  input wire clk,
  input wire [7:0] a,
  input wire iorq_n,
  output wire [7:0] d,
  output wire busdir
  );

  
  reg [29:0] cont;
  always @(posedge clk)
    cont <= cont + 30'd1;
  
  wire acceso = |{iorq_n,a[7:1]};
  assign busdir = acceso;
  wire port00 = ~acceso & ~a[0];
  wire port01 = ~acceso &  a[0];
  
  assign d = (port00)? cont[21:14] :
             (port01)? cont[29:22] :
             8'hZZ;
endmodule