data/full_repos/permissive/522534105/RTL_files/ADD_SUB.v
data/verilator_xmls/db42493c-06f5-4086-8695-42c5c8ad8891.xml
module FA(a_in,b_in,c_in,o_sum,o_cout);
input a_in,b_in,c_in;
output o_sum,o_cout;

assign o_sum = a_in^b_in^c_in;
assign o_cout = (a_in&b_in)|(b_in&c_in)|(a_in&c_in);
endmodule
module FA(a_in,b_in,c_in,o_sum,o_cout);

input a_in,b_in,c_in;
output o_sum,o_cout;

assign o_sum = a_in^b_in^c_in;
assign o_cout = (a_in&b_in)|(b_in&c_in)|(a_in&c_in);
endmodule