data/full_repos/permissive/515100461/ALU/test_SUB.v
1: b'%Error: data/full_repos/permissive/515100461/ALU/test_SUB.v:10: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("dump.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/515100461/ALU/test_SUB.v:11: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,test);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/515100461/ALU/test_SUB.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #20 $finish;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/515100461/ALU/test_SUB.v:23: Unsupported or unknown PLI call: $monitor\n    $monitor("time = %0t,A = %b,B = %b,result = %b,overflow = %b",$time,A,B,result,carry_overflow);\n    ^~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;

reg signed [63:0]A,B;
wire signed [63:0] result;
wire carry_overflow;

Sub uut(.A(A),.B(B),.result(result),.carry_overflow(carry_overflow));

initial begin
    $dumpfile("dump.vcd");
    $dumpvars(0,test);




    A = 64'd4;
    B = 64'd1;

    #20 $finish;
end

initial 
    $monitor("time = %0t,A = %b,B = %b,result = %b,overflow = %b",$time,A,B,result,carry_overflow);

endmodule
module test;


reg signed [63:0]A,B;
wire signed [63:0] result;
wire carry_overflow;

Sub uut(.A(A),.B(B),.result(result),.carry_overflow(carry_overflow));

initial begin
    $dumpfile("dump.vcd");
    $dumpvars(0,test);




    A = 64'd4;
    B = 64'd1;

    #20 $finish;
end

initial 
    $monitor("time = %0t,A = %b,B = %b,result = %b,overflow = %b",$time,A,B,result,carry_overflow);

endmodule