data/full_repos/permissive/42434302/ivltests/nb_assign.v
1: b'%Error: data/full_repos/permissive/42434302/ivltests/nb_assign.v:3: syntax error, unexpected var, expecting IDENTIFIER or \'=\' or do or final\n  reg [1:0] var = 2\'b0;\n            ^~~\n%Error: data/full_repos/permissive/42434302/ivltests/nb_assign.v:9: syntax error, unexpected <=, expecting IDENTIFIER or \'=\' or do or final\n    var <= #2 2\'b01;\n        ^~\n%Error: data/full_repos/permissive/42434302/ivltests/nb_assign.v:11: syntax error, unexpected var, expecting TYPE-IDENTIFIER\n    #3 if (var !== 2\'b01) begin\n           ^~~\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/nb_assign.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #3 if (var !== 2\'b01) begin\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/42434302/ivltests/nb_assign.v:16: syntax error, unexpected $display\n      $display("FAILED: constant delay (real)");\n      ^~~~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/nb_assign.v:21: syntax error, unexpected <=, expecting IDENTIFIER or \'=\' or do or final\n    var <= #(delay) 2\'b10;\n        ^~\n%Error: Cannot continue\n'
module top;
  reg pass = 1'b1;
  reg [1:0] var = 2'b0;
  real rvar = 0.0;
  integer delay = 3;

  initial begin

    var <= #2 2'b01;
    rvar <= #2 1.0;
    #3 if (var !== 2'b01) begin
      $display("FAILED: constant delay (bits)");
      pass = 1'b0;
    end
    if (rvar != 1.0) begin
      $display("FAILED: constant delay (real)");
      pass = 1'b0;
    end


    var <= #(delay) 2'b10;
    rvar <= #(delay) 2.0;
    #4 if (var !== 2'b10) begin
      $display("FAILED: calculated delay (bits)");
      pass = 1'b0;
    end
    if (rvar != 2.0) begin
      $display("FAILED: calculated delay (real)");
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule
module top;

  reg pass = 1'b1;
  reg [1:0] var = 2'b0;
  real rvar = 0.0;
  integer delay = 3;

  initial begin

    var <= #2 2'b01;
    rvar <= #2 1.0;
    #3 if (var !== 2'b01) begin
      $display("FAILED: constant delay (bits)");
      pass = 1'b0;
    end
    if (rvar != 1.0) begin
      $display("FAILED: constant delay (real)");
      pass = 1'b0;
    end


    var <= #(delay) 2'b10;
    rvar <= #(delay) 2.0;
    #4 if (var !== 2'b10) begin
      $display("FAILED: calculated delay (bits)");
      pass = 1'b0;
    end
    if (rvar != 2.0) begin
      $display("FAILED: calculated delay (real)");
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
  end
endmodule