data/full_repos/permissive/492363527/FirstTest.v
1: b'%Error: data/full_repos/permissive/492363527/FirstTest.v:11: Cannot find file containing module: \'LFSR12bit\'\n LFSR12bit lfsr(clk50M,r[11:0]);\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/492363527,data/full_repos/permissive/492363527/LFSR12bit\n             data/full_repos/permissive/492363527,data/full_repos/permissive/492363527/LFSR12bit.v\n             data/full_repos/permissive/492363527,data/full_repos/permissive/492363527/LFSR12bit.sv\n             LFSR12bit\n             LFSR12bit.v\n             LFSR12bit.sv\n             obj_dir/LFSR12bit\n             obj_dir/LFSR12bit.v\n             obj_dir/LFSR12bit.sv\n%Error: data/full_repos/permissive/492363527/FirstTest.v:12: Cannot find file containing module: \'DownCount\'\n DownCount downc(r[11:0],~key0,clk1k,A);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/492363527/FirstTest.v:13: Cannot find file containing module: \'HighScore\'\n HighScore hscore(b,counter[23:0],hs1[23:0]);\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/492363527/FirstTest.v:21: Operator AND expects 10 bits on the LHS, but LHS\'s VARREF \'b\' generates 1 bits.\n                                                                   : ... In instance FirstTest\n   LED1[9:0] = b & A;\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/492363527/FirstTest.v:21: Operator AND expects 10 bits on the RHS, but RHS\'s VARREF \'A\' generates 1 bits.\n                                                                   : ... In instance FirstTest\n   LED1[9:0] = b & A;\n                 ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module FirstTest(onoff,key0,counter,clk50M,clk1k,hs1,A1,b,LED1);
	input onoff, key0, clk50M, clk1k;
	input [23:0]counter;
	output reg b, A1;
	output reg [9:0] LED1;
	output [23:0]hs1;
	
	wire A;
	wire [11:0]r;
	
	LFSR12bit lfsr(clk50M,r[11:0]);
	DownCount downc(r[11:0],~key0,clk1k,A);
	HighScore hscore(b,counter[23:0],hs1[23:0]);
	
	always@(posedge clk50M) 
	begin
		if (onoff) 
		begin
			A1 = b & A;
			
			LED1[9:0] = b & A;
		end
		else 
		begin
			A1 = 1'b0;
			LED1[9:0] = 10'b0000000000;
		end
	end
	
	always@(posedge key0, negedge onoff) 
	begin
		if (~onoff)
			b <= 1'b0;
		else
			b <= b ^ 1'b1;
	end
	
endmodule
module FirstTest(onoff,key0,counter,clk50M,clk1k,hs1,A1,b,LED1);

	input onoff, key0, clk50M, clk1k;
	input [23:0]counter;
	output reg b, A1;
	output reg [9:0] LED1;
	output [23:0]hs1;
	
	wire A;
	wire [11:0]r;
	
	LFSR12bit lfsr(clk50M,r[11:0]);
	DownCount downc(r[11:0],~key0,clk1k,A);
	HighScore hscore(b,counter[23:0],hs1[23:0]);
	
	always@(posedge clk50M) 
	begin
		if (onoff) 
		begin
			A1 = b & A;
			
			LED1[9:0] = b & A;
		end
		else 
		begin
			A1 = 1'b0;
			LED1[9:0] = 10'b0000000000;
		end
	end
	
	always@(posedge key0, negedge onoff) 
	begin
		if (~onoff)
			b <= 1'b0;
		else
			b <= b ^ 1'b1;
	end
	
endmodule