data/full_repos/permissive/502135797/Lab3_Feb_28_2022/Code/CLKMANAGER_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab3_Feb_28_2022/Code/CLKMANAGER_TB.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk_tb = ~clk_tb;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab3_Feb_28_2022/Code/CLKMANAGER_TB.v:34: Unsupported: Ignoring delay on this delayed statement.\n           #10 \n           ^\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab3_Feb_28_2022/Code/CLKMANAGER_TB.v:36: Unsupported: Ignoring delay on this delayed statement.\n           #100  \n           ^\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab3_Feb_28_2022/Code/CLKMANAGER_TB.v:38: Unsupported: Ignoring delay on this delayed statement.\n           #100 \n           ^\n%Error: data/full_repos/permissive/502135797/Lab3_Feb_28_2022/Code/CLKMANAGER_TB.v:13: Cannot find file containing module: \'CLKMANAGER\'\n    CLKMANAGER COMP(\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502135797/Lab3_Feb_28_2022/Code,data/full_repos/permissive/502135797/CLKMANAGER\n             data/full_repos/permissive/502135797/Lab3_Feb_28_2022/Code,data/full_repos/permissive/502135797/CLKMANAGER.v\n             data/full_repos/permissive/502135797/Lab3_Feb_28_2022/Code,data/full_repos/permissive/502135797/CLKMANAGER.sv\n             CLKMANAGER\n             CLKMANAGER.v\n             CLKMANAGER.sv\n             obj_dir/CLKMANAGER\n             obj_dir/CLKMANAGER.v\n             obj_dir/CLKMANAGER.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module CLKMANAGER_TB (

    );
    
    reg clk_tb,rst_tb;
    reg [4:0] SW_tb;
    wire clkout_tb;

    
    CLKMANAGER COMP(
    .clk(clk_tb),
    .rst(rst_tb),
    .SW(SW_tb),
    .clkout(clkout_tb)       
    );
    
    initial 
        begin
        clk_tb = 1;
        end
        
    always   
        begin
        #5 clk_tb = ~clk_tb;

        end
    initial 
        begin 
            rst_tb = 1;
            SW_tb <= 0;
           #10 
            rst_tb = 0;
           #100  
            SW_tb = 4;
           #100 
           $finish;
        end 
    
endmodule
module CLKMANAGER_TB (

    );

    
    reg clk_tb,rst_tb;
    reg [4:0] SW_tb;
    wire clkout_tb;

    
    CLKMANAGER COMP(
    .clk(clk_tb),
    .rst(rst_tb),
    .SW(SW_tb),
    .clkout(clkout_tb)       
    );
    
    initial 
        begin
        clk_tb = 1;
        end
        
    always   
        begin
        #5 clk_tb = ~clk_tb;

        end
    initial 
        begin 
            rst_tb = 1;
            SW_tb <= 0;
           #10 
            rst_tb = 0;
           #100  
            SW_tb = 4;
           #100 
           $finish;
        end 
    
endmodule