data/full_repos/permissive/477054115/iitb-risc/Stage56_MM2WB.v
data/verilator_xmls/873eaf71-7672-40e6-a830-55bb55b2f8de.xml
module MEM2WB_Pipline_Reg (clk, rst, enable, Control_In, Rd_Addr_In_From_Mem, Rd_Data_In_From_Mem, Instr_In, Control_Out, Rd_Addr_Out_PR, 
							Rd_Data_Out_PR, Instr_Out);
 
	input clk, rst, enable;
	input [15:0] Instr_In, Rd_Data_In_From_Mem;
	input  Control_In;
	input [2:0] Rd_Addr_In_From_Mem ;
	output reg [15:0]  Instr_Out, Rd_Data_Out_PR;
	output reg  Control_Out;
	output reg [2:0] Rd_Addr_Out_PR;

	always @ (posedge clk) begin
		if (rst) begin

			Control_Out <= 0;
			Instr_Out <= 0;


			Rd_Addr_Out_PR <= 0; 
			Rd_Data_Out_PR <= 0; 
		end
		else begin
			if (enable) begin

				Control_Out <= Control_In;
				Instr_Out <= Instr_In;


				Rd_Addr_Out_PR <= Rd_Addr_In_From_Mem; 
				Rd_Data_Out_PR <= Rd_Data_In_From_Mem;
			end
		end
	end
endmodule
module MEM2WB_Pipline_Reg (clk, rst, enable, Control_In, Rd_Addr_In_From_Mem, Rd_Data_In_From_Mem, Instr_In, Control_Out, Rd_Addr_Out_PR, 
							Rd_Data_Out_PR, Instr_Out);

 
	input clk, rst, enable;
	input [15:0] Instr_In, Rd_Data_In_From_Mem;
	input  Control_In;
	input [2:0] Rd_Addr_In_From_Mem ;
	output reg [15:0]  Instr_Out, Rd_Data_Out_PR;
	output reg  Control_Out;
	output reg [2:0] Rd_Addr_Out_PR;

	always @ (posedge clk) begin
		if (rst) begin

			Control_Out <= 0;
			Instr_Out <= 0;


			Rd_Addr_Out_PR <= 0; 
			Rd_Data_Out_PR <= 0; 
		end
		else begin
			if (enable) begin

				Control_Out <= Control_In;
				Instr_Out <= Instr_In;


				Rd_Addr_Out_PR <= Rd_Addr_In_From_Mem; 
				Rd_Data_Out_PR <= Rd_Data_In_From_Mem;
			end
		end
	end
endmodule