data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/lv_2pl/tb_ex_sim.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/lv_2pl/tb_ex_sim.v:59: Unsupported: Ignoring delay on this delayed statement.\n#50 clk =1;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/lv_2pl/tb_ex_sim.v:60: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/lv_2pl/tb_ex_sim.v:153: Unsupported: Ignoring delay on this delayed statement.\n#100 rst = 1\'b1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/lv_2pl/tb_ex_sim.v:154: Unsupported: Ignoring delay on this delayed statement.\n#100 rst = 1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/lv_2pl/tb_ex_sim.v:155: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/lv_2pl/tb_ex_sim.v:166: Unsupported: Ignoring delay on this delayed statement.\n#100 start = 1\'b0;\n^\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/lv_2pl/tb_ex_sim.v:167: Unsupported: wait statements\nwait(vld1)\n^~~~\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/lv_2pl/tb_ex_sim.v:177: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/lv_2pl/tb_ex_sim.v:182: Unsupported: Ignoring delay on this delayed statement.\n#100 rst = 1\'b1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/lv_2pl/tb_ex_sim.v:183: Unsupported: Ignoring delay on this delayed statement.\n#100 rst = 1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/lv_2pl/tb_ex_sim.v:184: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/lv_2pl/tb_ex_sim.v:196: Unsupported: Ignoring delay on this delayed statement.\n#100 start = 1\'b0;\n^\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/lv_2pl/tb_ex_sim.v:197: Unsupported: wait statements\nwait(vld)\n^~~~\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/lv_2pl/tb_ex_sim.v:207: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/lv_2pl/tb_ex_sim.v:212: Unsupported: Ignoring delay on this delayed statement.\n#100 rst = 1\'b1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/lv_2pl/tb_ex_sim.v:213: Unsupported: Ignoring delay on this delayed statement.\n#100 rst = 1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/lv_2pl/tb_ex_sim.v:214: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/lv_2pl/tb_ex_sim.v:222: Unsupported: Ignoring delay on this delayed statement.\n#100 start = 1\'b0;\n^\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/lv_2pl/tb_ex_sim.v:226: Unsupported: wait statements\nwait(vld1)\n^~~~\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/lv_2pl/tb_ex_sim.v:236: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/lv_2pl/tb_ex_sim.v:241: Unsupported: Ignoring delay on this delayed statement.\n#100 rst = 1\'b1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/lv_2pl/tb_ex_sim.v:242: Unsupported: Ignoring delay on this delayed statement.\n#100 rst = 1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/lv_2pl/tb_ex_sim.v:243: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/lv_2pl/tb_ex_sim.v:252: Unsupported: Ignoring delay on this delayed statement.\n#100 start = 1\'b0;\n^\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/lv_2pl/tb_ex_sim.v:269: Unsupported: wait statements\nwait(vld)\n^~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/lv_2pl/tb_ex_sim.v:279: Unsupported: wait statements\nwait(vld1)\n^~~~\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/lv_2pl/tb_ex_sim.v:288: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/lv_2pl/tb_ex_sim.v:289: Unsupported: Ignoring delay on this delayed statement.\n#50000;\n^\n%Error: Exiting due to 5 error(s), 23 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_ex_sim;



parameter           WIDTH   = 256;
parameter           ADDR    = 5;
parameter           WINDOW  = 4;
parameter           CBIT    = 8;
parameter           DEPTH   = 1<<ADDR;



reg               clk;
reg               rst;


reg [3*WIDTH-1:0] din;
reg [2:0]         mode; 
reg               start;
wire [WIDTH-1:0]  dout;
wire [1:0]        status;

reg [WIDTH-1:0]   test_num;
reg [WIDTH-1:0]   expected;
reg [WIDTH-1:0]   expectedr;
reg [WIDTH-1:0]   expecteds;

ecc_core
    #(
      .WIDTH(WIDTH),
      .ADDR(ADDR),
      .WINDOW(WINDOW),
      .CBIT(CBIT),
      .DEPTH(DEPTH)
      ) iecc_core
    (
     .clk(clk),
     .rst(rst),

     .din(din),
     .mode(mode),
     .start(start),
     .dout(dout),
     .status(status),

     .test_num(test_num)
     );

wire              vld;
assign            vld = status[1] == 1'b1;
wire              vld1;
wire              vld2;
fflopx #(1) iffvld1(clk,rst,vld,vld1);
fflopx #(1) iffvld2(clk,rst,vld1,vld2);

always begin
clk = 0;
#50 clk =1;
#50;
end

initial begin




rst = 1'b0;
#100 rst = 1'b1;
#100 rst = 1'b0;
#1000;
din[WIDTH-1:0] = 256'h0900000000000000000000000000000000000000000000000000000000000000;
din[2*WIDTH-1: WIDTH] = 256'd0;
din[3*WIDTH-1:2*WIDTH] = 0;
mode = 3'b101;
start = 1'b1;
test_num = 256'h0900000000000000000000000000000000000000000000000000000000000000 - 256'd1;
expected = 256'h422c8e7a6227d7bca1350b3e2bb7279f7897b87bb6854b783c60e80311ae3079;
$display ("ECDHE GEN X255 begin at %t",$time);
$display ("Input");
$display ("k = %h",test_num + 256'd1);
#100 start = 1'b0;
wait(vld1)
begin
$display ("ECDHE GEN X255 test is done at %t", $time);
$display (" Output: %h", dout);
$display (" Expected : %h", expected);
if(dout == expected)
    $display("ECDHE GEN with X25519 is working");
else
    $display("ECDHE GEN with X25519 is not working");
end
#1000;



rst = 1'b0;
#100 rst = 1'b1;
#100 rst = 1'b0;
#1000;
din[WIDTH-1:0] = 256'he5210f12786811d3f4b7959d0538ae2c31dbe7106fc03c3efc4cd549c715a493;
din[2*WIDTH-1: WIDTH] = 256'h4b66e9d4d1b4673c5ad22691957d6af5c11b6421e0ea01d42ca4169e7918ba0d;
din[3*WIDTH-1:2*WIDTH] = 0;
mode = 3'b110;
start = 1'b1;
test_num = 256'h0;
expected = 256'h95cbde9476e8907d7aade45cb4b873f88b595a68799fa152e6f8f7647aac7957;
$display ("ECDHE COMP X255 begin at %t",$time);
$display ("Input");
$display ("u = %h",din[WIDTH-1:0]);
$display ("k = %h",din[2*WIDTH-1: WIDTH]);
#100 start = 1'b0;
wait(vld)
begin
$display ("ECDHE COMP X255 test is done at %t", $time);
$display (" Output: %h", dout);
$display (" Expected : %h", expected);
if(dout == expected)
    $display("ECDHE COMP with X25519 is working");
else
    $display("ECDHE COMP with X25519 is not working");
end
#1000;



rst = 1'b0;
#100 rst = 1'b1;
#100 rst = 1'b0;
#1000;
din[WIDTH-1:0] = 256'h0;
din[2*WIDTH-1: WIDTH] = 256'd0;
din[3*WIDTH-1:2*WIDTH] = 0;
mode = 3'b001;
start = 1'b1;
test_num = 256'd115792089210356248762697446949407573529996955224135760342422259061068512044353 - 256'd1;
expected = 256'h76A94D138A6B41858B821C629836315FCD28392EFF6CA038A5EB4787E1277C6E;
#100 start = 1'b0;
$display ("ECDHE GEN P256 begin at %t",$time);
$display ("Input");
$display ("k = %h",test_num + 256'd1);
wait(vld1)
begin
$display ("ECDHE GEN P256 test is done at %t", $time);
$display (" Output: %h", dout);
$display (" Expected : %h", expected);
if(dout == expected)
    $display("ECDHE GEN P256 is working");
else
    $display("ECDHE GEN P256 is not working");
end
#1000;



rst = 1'b0;
#100 rst = 1'b1;
#100 rst = 1'b0;
#1000;
din[WIDTH-1:0] = 256'hA41A41A12A799548211C410C65D8133AFDE34D28BDD542E4B680CF2899C8A8C4;
din[2*WIDTH-1: WIDTH] = 256'hC477F9F65C22CCE20657FAA5B2D1D8122336F851A508A1ED04E479C34985BF96;
din[3*WIDTH-1:2*WIDTH] = 0;
mode = 3'b000;
start = 1'b1;
test_num = 256'h7A1A7E52797FC8CAAA435D2A4DACE39158504BF204FBE19F14DBB427FAEE50AE - 256'd1;
expectedr = 256'h2B42F576D07F4165FF65D1F3B1500F81E44C316F1F0B3EF57325B69ACA46104F;
expecteds = 256'hDC42C2122D6392CD3E3A993A89502A8198C1886FE69D262C4B329BDB6B63FAF1;
#100 start = 1'b0;

$display ("ECDSA P256 begin at %t",$time);
$display ("Input");
$display ("hash = %h",din[WIDTH-1:0]);
$display ("private key = %h",din[2*WIDTH-1: WIDTH]);
$display ("k = %h",test_num + 256'd1);
wait(vld)
begin
$display ("ECDSA P256 test is done at %t", $time);
$display (" Output: %h", dout);
$display (" Expected : %h", expectedr);
if(dout == expectedr)
    $display("ECDSA P256 R is working");
else
    $display("ECDSA P256 R is not working");
end
wait(vld1)
begin
$display (" Output: %h", dout);
$display (" Expected : %h", expecteds);
if(dout == expecteds)
    $display("ECDSA P256 S is working");
else
    $display("ECDSA P256 S is not working");
end
#1000;
#50000;
$finish;
end












endmodule
module tb_ex_sim;




parameter           WIDTH   = 256;
parameter           ADDR    = 5;
parameter           WINDOW  = 4;
parameter           CBIT    = 8;
parameter           DEPTH   = 1<<ADDR;



reg               clk;
reg               rst;


reg [3*WIDTH-1:0] din;
reg [2:0]         mode; 
reg               start;
wire [WIDTH-1:0]  dout;
wire [1:0]        status;

reg [WIDTH-1:0]   test_num;
reg [WIDTH-1:0]   expected;
reg [WIDTH-1:0]   expectedr;
reg [WIDTH-1:0]   expecteds;

ecc_core
    #(
      .WIDTH(WIDTH),
      .ADDR(ADDR),
      .WINDOW(WINDOW),
      .CBIT(CBIT),
      .DEPTH(DEPTH)
      ) iecc_core
    (
     .clk(clk),
     .rst(rst),

     .din(din),
     .mode(mode),
     .start(start),
     .dout(dout),
     .status(status),

     .test_num(test_num)
     );

wire              vld;
assign            vld = status[1] == 1'b1;
wire              vld1;
wire              vld2;
fflopx #(1) iffvld1(clk,rst,vld,vld1);
fflopx #(1) iffvld2(clk,rst,vld1,vld2);

always begin
clk = 0;
#50 clk =1;
#50;
end

initial begin




rst = 1'b0;
#100 rst = 1'b1;
#100 rst = 1'b0;
#1000;
din[WIDTH-1:0] = 256'h0900000000000000000000000000000000000000000000000000000000000000;
din[2*WIDTH-1: WIDTH] = 256'd0;
din[3*WIDTH-1:2*WIDTH] = 0;
mode = 3'b101;
start = 1'b1;
test_num = 256'h0900000000000000000000000000000000000000000000000000000000000000 - 256'd1;
expected = 256'h422c8e7a6227d7bca1350b3e2bb7279f7897b87bb6854b783c60e80311ae3079;
$display ("ECDHE GEN X255 begin at %t",$time);
$display ("Input");
$display ("k = %h",test_num + 256'd1);
#100 start = 1'b0;
wait(vld1)
begin
$display ("ECDHE GEN X255 test is done at %t", $time);
$display (" Output: %h", dout);
$display (" Expected : %h", expected);
if(dout == expected)
    $display("ECDHE GEN with X25519 is working");
else
    $display("ECDHE GEN with X25519 is not working");
end
#1000;



rst = 1'b0;
#100 rst = 1'b1;
#100 rst = 1'b0;
#1000;
din[WIDTH-1:0] = 256'he5210f12786811d3f4b7959d0538ae2c31dbe7106fc03c3efc4cd549c715a493;
din[2*WIDTH-1: WIDTH] = 256'h4b66e9d4d1b4673c5ad22691957d6af5c11b6421e0ea01d42ca4169e7918ba0d;
din[3*WIDTH-1:2*WIDTH] = 0;
mode = 3'b110;
start = 1'b1;
test_num = 256'h0;
expected = 256'h95cbde9476e8907d7aade45cb4b873f88b595a68799fa152e6f8f7647aac7957;
$display ("ECDHE COMP X255 begin at %t",$time);
$display ("Input");
$display ("u = %h",din[WIDTH-1:0]);
$display ("k = %h",din[2*WIDTH-1: WIDTH]);
#100 start = 1'b0;
wait(vld)
begin
$display ("ECDHE COMP X255 test is done at %t", $time);
$display (" Output: %h", dout);
$display (" Expected : %h", expected);
if(dout == expected)
    $display("ECDHE COMP with X25519 is working");
else
    $display("ECDHE COMP with X25519 is not working");
end
#1000;



rst = 1'b0;
#100 rst = 1'b1;
#100 rst = 1'b0;
#1000;
din[WIDTH-1:0] = 256'h0;
din[2*WIDTH-1: WIDTH] = 256'd0;
din[3*WIDTH-1:2*WIDTH] = 0;
mode = 3'b001;
start = 1'b1;
test_num = 256'd115792089210356248762697446949407573529996955224135760342422259061068512044353 - 256'd1;
expected = 256'h76A94D138A6B41858B821C629836315FCD28392EFF6CA038A5EB4787E1277C6E;
#100 start = 1'b0;
$display ("ECDHE GEN P256 begin at %t",$time);
$display ("Input");
$display ("k = %h",test_num + 256'd1);
wait(vld1)
begin
$display ("ECDHE GEN P256 test is done at %t", $time);
$display (" Output: %h", dout);
$display (" Expected : %h", expected);
if(dout == expected)
    $display("ECDHE GEN P256 is working");
else
    $display("ECDHE GEN P256 is not working");
end
#1000;



rst = 1'b0;
#100 rst = 1'b1;
#100 rst = 1'b0;
#1000;
din[WIDTH-1:0] = 256'hA41A41A12A799548211C410C65D8133AFDE34D28BDD542E4B680CF2899C8A8C4;
din[2*WIDTH-1: WIDTH] = 256'hC477F9F65C22CCE20657FAA5B2D1D8122336F851A508A1ED04E479C34985BF96;
din[3*WIDTH-1:2*WIDTH] = 0;
mode = 3'b000;
start = 1'b1;
test_num = 256'h7A1A7E52797FC8CAAA435D2A4DACE39158504BF204FBE19F14DBB427FAEE50AE - 256'd1;
expectedr = 256'h2B42F576D07F4165FF65D1F3B1500F81E44C316F1F0B3EF57325B69ACA46104F;
expecteds = 256'hDC42C2122D6392CD3E3A993A89502A8198C1886FE69D262C4B329BDB6B63FAF1;
#100 start = 1'b0;

$display ("ECDSA P256 begin at %t",$time);
$display ("Input");
$display ("hash = %h",din[WIDTH-1:0]);
$display ("private key = %h",din[2*WIDTH-1: WIDTH]);
$display ("k = %h",test_num + 256'd1);
wait(vld)
begin
$display ("ECDSA P256 test is done at %t", $time);
$display (" Output: %h", dout);
$display (" Expected : %h", expectedr);
if(dout == expectedr)
    $display("ECDSA P256 R is working");
else
    $display("ECDSA P256 R is not working");
end
wait(vld1)
begin
$display (" Output: %h", dout);
$display (" Expected : %h", expecteds);
if(dout == expecteds)
    $display("ECDSA P256 S is working");
else
    $display("ECDSA P256 S is not working");
end
#1000;
#50000;
$finish;
end












endmodule