data/full_repos/permissive/429421342/files/renamed_pixelTop_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/429421342/files/renamed_pixelTop_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n   always #clk_period CLK=~CLK;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/429421342/files/renamed_pixelTop_tb.v:124: Unsupported: Ignoring delay on this delayed statement.\n        #clk_period  RESET=0;\n        ^\n%Error: data/full_repos/permissive/429421342/files/renamed_pixelTop_tb.v:126: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("test_shit_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/429421342/files/renamed_pixelTop_tb.v:127: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0,test_shit_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/429421342/files/renamed_pixelTop_tb.v:129: Unsupported: Ignoring delay on this delayed statement.\n        #sim_end\n        ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module MUX_4_TO_1(
                  inout[7:0] a,
                  inout[7:0] b,
                  inout[7:0] c,
                  inout[7:0] d,
                  input[3:0] sel,
                  inout[7:0] out);

   assign out = sel[0] ? a : (sel[1] ? b : (sel[3] ? c: d));

endmodule
module MUX_4_TO_1(
                  inout[7:0] a,
                  inout[7:0] b,
                  inout[7:0] c,
                  inout[7:0] d,
                  input[3:0] sel,
                  inout[7:0] out);


   assign out = sel[0] ? a : (sel[1] ? b : (sel[3] ? c: d));

endmodule