data/full_repos/permissive/450962776/processor/src/Main_Control.v
1: b"%Error: data/full_repos/permissive/450962776/processor/src/Main_Control.v:6: Cannot find file containing module: 'and_R_type'\nand_R_type q0(op,wires[0]);\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/450962776/processor/src,data/full_repos/permissive/450962776/and_R_type\n             data/full_repos/permissive/450962776/processor/src,data/full_repos/permissive/450962776/and_R_type.v\n             data/full_repos/permissive/450962776/processor/src,data/full_repos/permissive/450962776/and_R_type.sv\n             and_R_type\n             and_R_type.v\n             and_R_type.sv\n             obj_dir/and_R_type\n             obj_dir/and_R_type.v\n             obj_dir/and_R_type.sv\n%Error: data/full_repos/permissive/450962776/processor/src/Main_Control.v:7: Cannot find file containing module: 'and_addi_type'\nand_addi_type q1(op,wires[1]);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/450962776/processor/src/Main_Control.v:8: Cannot find file containing module: 'and_andi_type'\nand_andi_type q2(op,wires[2]);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/450962776/processor/src/Main_Control.v:9: Cannot find file containing module: 'and_ori_type'\nand_ori_type q3(op,wires[3]);\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/450962776/processor/src/Main_Control.v:10: Cannot find file containing module: 'and_nori_type'\nand_nori_type q4(op,wires[4]);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/450962776/processor/src/Main_Control.v:11: Cannot find file containing module: 'and_BEQ_type'\nand_BEQ_type q5(op,wires[5]);\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/450962776/processor/src/Main_Control.v:12: Cannot find file containing module: 'and_BNE_type'\nand_BNE_type q6(op,wires[6]);\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/450962776/processor/src/Main_Control.v:13: Cannot find file containing module: 'and_SLTI_type'\nand_SLTI_type q7(op,wires[7]);\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/450962776/processor/src/Main_Control.v:14: Cannot find file containing module: 'and_LW_type'\nand_LW_type q8(op,wires[8]);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/450962776/processor/src/Main_Control.v:15: Cannot find file containing module: 'and_SW_type'\nand_SW_type q9(op,wires[9]);\n^~~~~~~~~~~\n%Error: Exiting due to 10 error(s)\n"
module Main_Control(op,RegDst,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,Branch_not,ALUop0,ALUop1,ALUop2);
input [3:0]op;
output RegDst,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,Branch_not,ALUop0,ALUop1,ALUop2;
wire [9:0]wires;

and_R_type q0(op,wires[0]);
and_addi_type q1(op,wires[1]);
and_andi_type q2(op,wires[2]);
and_ori_type q3(op,wires[3]);
and_nori_type q4(op,wires[4]);
and_BEQ_type q5(op,wires[5]);
and_BNE_type q6(op,wires[6]);
and_SLTI_type q7(op,wires[7]);
and_LW_type q8(op,wires[8]);
and_SW_type q9(op,wires[9]);

or a0(RegDst,wires[0]);
or a1(ALUSrc,wires[1],wires[2],wires[3],wires[4],wires[7],wires[8],wires[9]);
or a2(MemtoReg,wires[8]);
or a3(RegWrite,wires[0],wires[1],wires[2],wires[3],wires[4],wires[7],wires[8]);
or a4(MemRead,wires[8]);
or a5(MemWrite,wires[9]);
or a6(Branch,wires[5]);
or a7(ALUop2,wires[0],wires[5],wires[6],wires[7]);
or a8(ALUop1,wires[0],wires[3],wires[4],wires[7]);
or a9(ALUop0,wires[0],wires[2],wires[4],wires[6]);
or a10(Branch_not,wires[6]);


endmodule
module Main_Control(op,RegDst,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,Branch_not,ALUop0,ALUop1,ALUop2);

input [3:0]op;
output RegDst,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,Branch_not,ALUop0,ALUop1,ALUop2;
wire [9:0]wires;

and_R_type q0(op,wires[0]);
and_addi_type q1(op,wires[1]);
and_andi_type q2(op,wires[2]);
and_ori_type q3(op,wires[3]);
and_nori_type q4(op,wires[4]);
and_BEQ_type q5(op,wires[5]);
and_BNE_type q6(op,wires[6]);
and_SLTI_type q7(op,wires[7]);
and_LW_type q8(op,wires[8]);
and_SW_type q9(op,wires[9]);

or a0(RegDst,wires[0]);
or a1(ALUSrc,wires[1],wires[2],wires[3],wires[4],wires[7],wires[8],wires[9]);
or a2(MemtoReg,wires[8]);
or a3(RegWrite,wires[0],wires[1],wires[2],wires[3],wires[4],wires[7],wires[8]);
or a4(MemRead,wires[8]);
or a5(MemWrite,wires[9]);
or a6(Branch,wires[5]);
or a7(ALUop2,wires[0],wires[5],wires[6],wires[7]);
or a8(ALUop1,wires[0],wires[3],wires[4],wires[7]);
or a9(ALUop0,wires[0],wires[2],wires[4],wires[6]);
or a10(Branch_not,wires[6]);


endmodule