data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/tb/sv/jedro_1_xori_tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/tb/sv/jedro_1_xori_tb.sv:31: Unsupported: Ignoring delay on this delayed statement.\n  always #1 clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/tb/sv/jedro_1_xori_tb.sv:36: syntax error, unexpected \'@\'\n  repeat (3) @ (posedge clk);\n             ^\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/tb/sv/jedro_1_xori_tb.sv:40: syntax error, unexpected \'@\'\n    @(posedge clk);\n    ^\n%Error: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/tb/sv/jedro_1_xori_tb.sv:43: syntax error, unexpected \'@\'\n  repeat (3) @ (posedge clk);  \n             ^\n%Error: Exiting due to 3 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module jedro_1_xori_tb();
  parameter DATA_WIDTH = 32;
  parameter ADDR_WIDTH = 32;

  logic clk;
  logic rstn;
  
  int i;
  
  ram_read_io #(.ADDR_WIDTH(ADDR_WIDTH), 
                .DATA_WIDTH(DATA_WIDTH)) instr_mem_if();

  ram_rw_io data_mem_if();
  bytewrite_ram_wrap data_mem (.clk_i  (clk),                                                                           
                               .rstn_i (rstn),                                                                          
                               .ram_if (data_mem_if.SLAVE));

  jedro_1_top dut(.clk_i       (clk),
                  .rstn_i      (rstn),
                  .instr_mem_if(instr_mem_if.MASTER),
                  .data_mem_if (data_mem_if.MASTER)
                );

  rams_init_file_wrap #(.MEM_INIT_FILE("jedro_1_xori_tb.mem")) rom_mem (.clk_i(clk),
                                                                        .rom_if(instr_mem_if));


  always #1 clk = ~clk;

  initial begin
  clk <= 1'b0;
  rstn <= 1'b0;
  repeat (3) @ (posedge clk);
  rstn <= 1'b1;
  
  while (i < 32 && dut.decoder_inst.illegal_instr_ro == 0) begin
    @(posedge clk);
    i++;
  end
  repeat (3) @ (posedge clk);
 
  assert ( dut.regfile_inst.regfile[7] == 1 + 2 + 4 + 8 ) 
  else $display("ERROR: After executing jedro_1_xori_tb.mem the value in register 7 should be 15, not %d.", 
                dut.regfile_inst.regfile[7]);

  $finish;
  end

endmodule
module jedro_1_xori_tb();

  parameter DATA_WIDTH = 32;
  parameter ADDR_WIDTH = 32;

  logic clk;
  logic rstn;
  
  int i;
  
  ram_read_io #(.ADDR_WIDTH(ADDR_WIDTH), 
                .DATA_WIDTH(DATA_WIDTH)) instr_mem_if();

  ram_rw_io data_mem_if();
  bytewrite_ram_wrap data_mem (.clk_i  (clk),                                                                           
                               .rstn_i (rstn),                                                                          
                               .ram_if (data_mem_if.SLAVE));

  jedro_1_top dut(.clk_i       (clk),
                  .rstn_i      (rstn),
                  .instr_mem_if(instr_mem_if.MASTER),
                  .data_mem_if (data_mem_if.MASTER)
                );

  rams_init_file_wrap #(.MEM_INIT_FILE("jedro_1_xori_tb.mem")) rom_mem (.clk_i(clk),
                                                                        .rom_if(instr_mem_if));


  always #1 clk = ~clk;

  initial begin
  clk <= 1'b0;
  rstn <= 1'b0;
  repeat (3) @ (posedge clk);
  rstn <= 1'b1;
  
  while (i < 32 && dut.decoder_inst.illegal_instr_ro == 0) begin
    @(posedge clk);
    i++;
  end
  repeat (3) @ (posedge clk);
 
  assert ( dut.regfile_inst.regfile[7] == 1 + 2 + 4 + 8 ) 
  else $display("ERROR: After executing jedro_1_xori_tb.mem the value in register 7 should be 15, not %d.", 
                dut.regfile_inst.regfile[7]);

  $finish;
  end

endmodule