data/full_repos/permissive/467394306/rtl/col_output_ctrl.sv
1: b'%Warning-LITENDIAN: data/full_repos/permissive/467394306/rtl/col_output_ctrl.sv:8: Little bit endian vector: MSB < LSB of bit range: 0:7\n    input [0:ROWS-1] in_v,\n          ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module COL_OUTPUT_CTRL #(
    parameter ROWS=8,
    parameter OUTWIDTH=32)
    (
    input clk,
    input rstn,
    input [OUTWIDTH-1 : 0] in_r [0 : ROWS-1],
    input [0:ROWS-1] in_v,
    input rread,
    output [OUTWIDTH-1 : 0] out_r,
    output rvalid);

    integer i;









    reg [OUTWIDTH-1:0] outbuf [0:ROWS-1];

    reg [2:0] icnt, ocnt;



    assign rvalid = (ocnt < icnt);
    assign out_r = outbuf[ocnt];

    always_ff @ (posedge clk) begin
        if (!rstn) begin
            for (i=0; i<ROWS; i=i+1) begin
                outbuf[i] <= 0;
            end
            ocnt <= 0;
            icnt <= 0;
        end else begin


            for (i=0; i<ROWS; i=i+1) begin
                if (in_v[i] == 1) begin
                    outbuf[i] <= in_r[i];
                    icnt <= icnt + 1;
                end
            end


            if (rread) begin
                ocnt <= ocnt + 1;
            end

            if (ocnt == 3'b111 && icnt == 3'b111) begin
                ocnt <= 0;
                icnt <= 0;
            end
        end
    end
endmodule
module COL_OUTPUT_CTRL #(
    parameter ROWS=8,
    parameter OUTWIDTH=32)
    (
    input clk,
    input rstn,
    input [OUTWIDTH-1 : 0] in_r [0 : ROWS-1],
    input [0:ROWS-1] in_v,
    input rread,
    output [OUTWIDTH-1 : 0] out_r,
    output rvalid);


    integer i;









    reg [OUTWIDTH-1:0] outbuf [0:ROWS-1];

    reg [2:0] icnt, ocnt;



    assign rvalid = (ocnt < icnt);
    assign out_r = outbuf[ocnt];

    always_ff @ (posedge clk) begin
        if (!rstn) begin
            for (i=0; i<ROWS; i=i+1) begin
                outbuf[i] <= 0;
            end
            ocnt <= 0;
            icnt <= 0;
        end else begin


            for (i=0; i<ROWS; i=i+1) begin
                if (in_v[i] == 1) begin
                    outbuf[i] <= in_r[i];
                    icnt <= icnt + 1;
                end
            end


            if (rread) begin
                ocnt <= ocnt + 1;
            end

            if (ocnt == 3'b111 && icnt == 3'b111) begin
                ocnt <= 0;
                icnt <= 0;
            end
        end
    end
endmodule