data/full_repos/permissive/489790801/sim/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/489790801/sim/tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/489790801/sim/tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/489790801/sim/tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #10 en = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/489790801/sim/tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n        while(i_top.ctrl.addr != LP_FIN_ADDR) #10;\n                                              ^\n%Warning-STMTDLY: data/full_repos/permissive/489790801/sim/tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/489790801/sim/tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk = !clk;\n           ^\n%Error: data/full_repos/permissive/489790801/sim/tb.v:58: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("./sim.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/489790801/sim/tb.v:59: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;
    
    localparam LP_FIN_ADDR = 9;
    localparam LP_N_TESTS = 15;
    localparam LP_WIDTH = 32;

    reg clk, rst, en;
    reg [LP_WIDTH - 1 : 0] a [LP_N_TESTS - 1 : 0];
    reg [LP_WIDTH - 1 : 0] b [LP_N_TESTS - 1 : 0];
    reg [LP_WIDTH - 1 : 0] g [LP_N_TESTS - 1 : 0];
    integer testnum;

    top #() i_top (
        .rst(rst),
        .clk(clk),
        .en(en));

    task compute_gcd(input [32 - 1 : 0] a, b, g);
        begin
        rst = 1;
        en = 0;
        #10
        rst = 0;
        #10
        i_top.a = a;
        i_top.b = b;
        #10 en = 1;
        while(i_top.ctrl.addr != LP_FIN_ADDR) #10;
        #100;
        if(i_top.a != g) begin
            $display("Test fail!!!!!!!!!!!!!!!!!!!");
            $display("Got %d when expected %d\n", i_top.a, g);
        end
        else begin
            $display("Test passed\n");
        end
        end
    endtask

    always #5 clk = !clk;

    initial begin
        $readmemb("./src/bin/eq_zero_optimized.b", i_top.ctrl.imem);
        $readmemb("./sim/vectors/a.b", a);
        $readmemb("./sim/vectors/b.b", b);
        $readmemb("./sim/vectors/g.b", g);
        clk = 1;
        for(testnum = 0; testnum < LP_N_TESTS; testnum = testnum + 1) begin
            $display("Running test %0d...", testnum);
            compute_gcd(a[testnum],b[testnum],g[testnum]);
        end
        $finish;
    end

    initial begin
        $dumpfile("./sim.vcd");
        $dumpvars;
    end
endmodule
module tb;

    
    localparam LP_FIN_ADDR = 9;
    localparam LP_N_TESTS = 15;
    localparam LP_WIDTH = 32;

    reg clk, rst, en;
    reg [LP_WIDTH - 1 : 0] a [LP_N_TESTS - 1 : 0];
    reg [LP_WIDTH - 1 : 0] b [LP_N_TESTS - 1 : 0];
    reg [LP_WIDTH - 1 : 0] g [LP_N_TESTS - 1 : 0];
    integer testnum;

    top #() i_top (
        .rst(rst),
        .clk(clk),
        .en(en));

    task compute_gcd(input [32 - 1 : 0] a, b, g);
        begin
        rst = 1;
        en = 0;
        #10
        rst = 0;
        #10
        i_top.a = a;
        i_top.b = b;
        #10 en = 1;
        while(i_top.ctrl.addr != LP_FIN_ADDR) #10;
        #100;
        if(i_top.a != g) begin
            $display("Test fail!!!!!!!!!!!!!!!!!!!");
            $display("Got %d when expected %d\n", i_top.a, g);
        end
        else begin
            $display("Test passed\n");
        end
        end
    endtask

    always #5 clk = !clk;

    initial begin
        $readmemb("./src/bin/eq_zero_optimized.b", i_top.ctrl.imem);
        $readmemb("./sim/vectors/a.b", a);
        $readmemb("./sim/vectors/b.b", b);
        $readmemb("./sim/vectors/g.b", g);
        clk = 1;
        for(testnum = 0; testnum < LP_N_TESTS; testnum = testnum + 1) begin
            $display("Running test %0d...", testnum);
            compute_gcd(a[testnum],b[testnum],g[testnum]);
        end
        $finish;
    end

    initial begin
        $dumpfile("./sim.vcd");
        $dumpvars;
    end
endmodule