data/full_repos/permissive/524532083/verilog/rtl/impulse.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/524532083/verilog/rtl/impulse.v:61: Multiple top level modules\n                                                                                : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                : ... Top module \'impulse\'\nmodule impulse(\n       ^~~~~~~\n                                                                                : ... Top module \'impulse_no_reset\'\nmodule impulse_no_reset(\n       ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module impulse_no_reset(
  input clock,
  input trigger,
  output advance
);

  reg [1:0] impulse_gen;

  always@(posedge clock)
  begin
    impulse_gen <= {impulse_gen[0],trigger};
  end

  assign advance = impulse_gen == 2'b01;

endmodule
module impulse_no_reset(
  input clock,
  input trigger,
  output advance
);


  reg [1:0] impulse_gen;

  always@(posedge clock)
  begin
    impulse_gen <= {impulse_gen[0],trigger};
  end

  assign advance = impulse_gen == 2'b01;

endmodule