data/full_repos/permissive/445379100/a1_synthesis/seq_mult.v
1: b'%Warning-WIDTH: data/full_repos/permissive/445379100/a1_synthesis/seq_mult.v:64: Bit extraction of var[15:0] requires 4 bit index, not 5 bits.\n                                                                               : ... In instance seq_mult\n       if ( multiplier[ctr] == 1 )\n                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module seq_mult (

		 p, rdy, 

		 clk, reset, a, b
		 ) ;
   input 		 clk, reset;
   input [`width-1:0] 	 a, b;

   output [15:0] p;
   output 		 rdy;
   

   reg [15:0] p,multiplier,multiplicand;
   reg 			 rdy;
   reg [`ctrwidth:0] 	 ctr;


   always @(posedge clk or posedge reset) begin
     if (reset) begin          



	rdy 		<= 0;
	p 		<= 0;
	ctr 		<= 0;
	multiplier 	<= {{`width{a[`width-1]}}, a};
	multiplicand 	<= {{`width{b[`width-1]}}, b};

     end

     else begin                       
	


	if (ctr < 16 )
	   begin
	

	      if ( multiplier[ctr] == 1 )
                 begin
                    
                    multiplicand <= multiplicand << 1;
                    p <= p + multiplicand;

		    ctr <= ctr + 1;          
	       	 
                 end

              else
                 begin

                    multiplicand <= multiplicand << 1;
                    ctr <= ctr + 1;
                 
                 end

           end
	  
	   else begin
	     
              rdy <= 1;
	  
	   end
     
      end

   end

endmodule
module seq_mult (

		 p, rdy, 

		 clk, reset, a, b
		 ) ;

   input 		 clk, reset;
   input [`width-1:0] 	 a, b;

   output [15:0] p;
   output 		 rdy;
   

   reg [15:0] p,multiplier,multiplicand;
   reg 			 rdy;
   reg [`ctrwidth:0] 	 ctr;


   always @(posedge clk or posedge reset) begin
     if (reset) begin          



	rdy 		<= 0;
	p 		<= 0;
	ctr 		<= 0;
	multiplier 	<= {{`width{a[`width-1]}}, a};
	multiplicand 	<= {{`width{b[`width-1]}}, b};

     end

     else begin                       
	


	if (ctr < 16 )
	   begin
	

	      if ( multiplier[ctr] == 1 )
                 begin
                    
                    multiplicand <= multiplicand << 1;
                    p <= p + multiplicand;

		    ctr <= ctr + 1;          
	       	 
                 end

              else
                 begin

                    multiplicand <= multiplicand << 1;
                    ctr <= ctr + 1;
                 
                 end

           end
	  
	   else begin
	     
              rdy <= 1;
	  
	   end
     
      end

   end

endmodule