data/full_repos/permissive/488739248/rtl/ttl/ttl_74157.v
1: b'%Error: data/full_repos/permissive/488739248/rtl/ttl/ttl_74157.v:2: Cannot find include file: helper.v\n`include "helper.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/488739248/rtl/ttl,data/full_repos/permissive/488739248/helper.v\n             data/full_repos/permissive/488739248/rtl/ttl,data/full_repos/permissive/488739248/helper.v.v\n             data/full_repos/permissive/488739248/rtl/ttl,data/full_repos/permissive/488739248/helper.v.sv\n             helper.v\n             helper.v.v\n             helper.v.sv\n             obj_dir/helper.v\n             obj_dir/helper.v.v\n             obj_dir/helper.v.sv\n%Error: data/full_repos/permissive/488739248/rtl/ttl/ttl_74157.v:32: Define or directive not defined: \'`ASSIGN_UNPACK_ARRAY\'\n`ASSIGN_UNPACK_ARRAY(BLOCKS, WIDTH_IN, A, A_2D)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/488739248/rtl/ttl/ttl_74157.v:32: syntax error, unexpected \'(\'\n`ASSIGN_UNPACK_ARRAY(BLOCKS, WIDTH_IN, A, A_2D)\n                     ^~~~~~\n%Error: Exiting due to 3 error(s)\n'
module ttl_74157 #(parameter BLOCKS = 4, WIDTH_IN = 2, WIDTH_SELECT = $clog2(WIDTH_IN),
                   DELAY_RISE = 12, DELAY_FALL = 13)
(
  input wire Enable_bar,
  input wire [WIDTH_SELECT-1:0] Select,
  input wire [BLOCKS*WIDTH_IN-1:0] A_2D,
  output wire [BLOCKS-1:0] Y
);


wire [WIDTH_IN-1:0] A [0:BLOCKS-1];
reg [BLOCKS-1:0] computed;
integer i;

always @(*)
begin
  for (i = 0; i < BLOCKS; i=i+1)
  begin
    if (!Enable_bar)
      computed[i] = A[i][Select];
    else
      computed[i] = 1'b0;
  end
end


`ASSIGN_UNPACK_ARRAY(BLOCKS, WIDTH_IN, A, A_2D)
assign #(DELAY_RISE, DELAY_FALL) Y = computed;

endmodule
module ttl_74157 #(parameter BLOCKS = 4, WIDTH_IN = 2, WIDTH_SELECT = $clog2(WIDTH_IN),
                   DELAY_RISE = 12, DELAY_FALL = 13)
(
  input wire Enable_bar,
  input wire [WIDTH_SELECT-1:0] Select,
  input wire [BLOCKS*WIDTH_IN-1:0] A_2D,
  output wire [BLOCKS-1:0] Y
);



wire [WIDTH_IN-1:0] A [0:BLOCKS-1];
reg [BLOCKS-1:0] computed;
integer i;

always @(*)
begin
  for (i = 0; i < BLOCKS; i=i+1)
  begin
    if (!Enable_bar)
      computed[i] = A[i][Select];
    else
      computed[i] = 1'b0;
  end
end


`ASSIGN_UNPACK_ARRAY(BLOCKS, WIDTH_IN, A, A_2D)
assign #(DELAY_RISE, DELAY_FALL) Y = computed;

endmodule