data/full_repos/permissive/441359809/src/yosys/examples/smtbmc/demo6.v
data/verilator_xmls/9f2d654b-e496-4f52-86f7-d0722519f3ca.xml
module demo6 (input A, B, C, D, E, output reg Y);
	always @* begin
		Y = 0;
		if (A != B) begin
			(* parallel_case *)
			case (C)
				A: Y = D;
				B: Y = E;
			endcase
		end
	end
endmodule
module demo6 (input A, B, C, D, E, output reg Y);

	always @* begin
		Y = 0;
		if (A != B) begin
			(* parallel_case *)
			case (C)
				A: Y = D;
				B: Y = E;
			endcase
		end
	end
endmodule