data/full_repos/permissive/487568919/basic_verilog/round_robin_enc.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/487568919/basic_verilog/round_robin_enc.sv:56: Operator EQ expects 32 or 6 bits on the LHS, but LHS\'s SEL generates 5 bits.\n                                                                                        : ... In instance round_robin_enc\n    if( priority_bit[WIDTH_W-1:0] == WIDTH-1 ) begin\n                                  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module round_robin_enc #( parameter
  WIDTH = 32,
  WIDTH_W = $clog2(WIDTH)
)(
  input clk,
  input nrst,

  input  [WIDTH-1:0] id,
  output logic od_valid,
  output logic [WIDTH-1:0] od_filt,
  output logic [WIDTH_W-1:0] od_bin
);



logic [WIDTH_W-1:0] priority_bit = '0;
always_ff @(posedge clk) begin
  if( ~nrst ) begin
    priority_bit[WIDTH_W-1:0] <= '0;
  end else begin
    if( priority_bit[WIDTH_W-1:0] == WIDTH-1 ) begin
      priority_bit[WIDTH_W-1:0] <= '0;
    end else begin
      priority_bit[WIDTH_W-1:0] <= priority_bit[WIDTH_W-1:0] + 1'b1;
    end
  end
end

always_comb begin
  if( id[priority_bit[WIDTH_W-1:0]] ) begin
    od_valid = id[priority_bit[WIDTH_W-1:0]];
    od_filt[WIDTH-1:0] = 1'b1 << priority_bit[WIDTH_W-1:0];
    od_bin[WIDTH_W-1:0] = priority_bit[WIDTH_W-1:0];
  end else begin
    od_valid = 1'b0;
    od_filt[WIDTH-1:0] = '0;
    od_bin[WIDTH_W-1:0] = '0;
  end
end

endmodule
module round_robin_enc #( parameter
  WIDTH = 32,
  WIDTH_W = $clog2(WIDTH)
)(
  input clk,
  input nrst,

  input  [WIDTH-1:0] id,
  output logic od_valid,
  output logic [WIDTH-1:0] od_filt,
  output logic [WIDTH_W-1:0] od_bin
);




logic [WIDTH_W-1:0] priority_bit = '0;
always_ff @(posedge clk) begin
  if( ~nrst ) begin
    priority_bit[WIDTH_W-1:0] <= '0;
  end else begin
    if( priority_bit[WIDTH_W-1:0] == WIDTH-1 ) begin
      priority_bit[WIDTH_W-1:0] <= '0;
    end else begin
      priority_bit[WIDTH_W-1:0] <= priority_bit[WIDTH_W-1:0] + 1'b1;
    end
  end
end

always_comb begin
  if( id[priority_bit[WIDTH_W-1:0]] ) begin
    od_valid = id[priority_bit[WIDTH_W-1:0]];
    od_filt[WIDTH-1:0] = 1'b1 << priority_bit[WIDTH_W-1:0];
    od_bin[WIDTH_W-1:0] = priority_bit[WIDTH_W-1:0];
  end else begin
    od_valid = 1'b0;
    od_filt[WIDTH-1:0] = '0;
    od_bin[WIDTH_W-1:0] = '0;
  end
end

endmodule