data/full_repos/permissive/492804614/Group_6_YODA_project/Group_6_YODA_project.srcs/sim_1/new/testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/492804614/Group_6_YODA_project/Group_6_YODA_project.srcs/sim_1/new/testbench.v:81: Unsupported: Ignoring delay on this delayed statement.\n    always #clockRate clk = ~clk;  \n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/492804614/Group_6_YODA_project/Group_6_YODA_project.srcs/sim_1/new/testbench.v:17: Cannot find file containing module: \'audio_gen\'\n    audio_gen baseAudioGen(\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/492804614/Group_6_YODA_project/Group_6_YODA_project.srcs/sim_1/new,data/full_repos/permissive/492804614/audio_gen\n             data/full_repos/permissive/492804614/Group_6_YODA_project/Group_6_YODA_project.srcs/sim_1/new,data/full_repos/permissive/492804614/audio_gen.v\n             data/full_repos/permissive/492804614/Group_6_YODA_project/Group_6_YODA_project.srcs/sim_1/new,data/full_repos/permissive/492804614/audio_gen.sv\n             audio_gen\n             audio_gen.v\n             audio_gen.sv\n             obj_dir/audio_gen\n             obj_dir/audio_gen.v\n             obj_dir/audio_gen.sv\n%Error: data/full_repos/permissive/492804614/Group_6_YODA_project/Group_6_YODA_project.srcs/sim_1/new/testbench.v:28: Cannot find file containing module: \'min_max\'\n    min_max min_max_1(\n    ^~~~~~~\n%Error: data/full_repos/permissive/492804614/Group_6_YODA_project/Group_6_YODA_project.srcs/sim_1/new/testbench.v:37: Cannot find file containing module: \'min_max\'\n    min_max min_max_2(\n    ^~~~~~~\n%Error: data/full_repos/permissive/492804614/Group_6_YODA_project/Group_6_YODA_project.srcs/sim_1/new/testbench.v:46: Cannot find file containing module: \'min_max\'\n     min_max min_max_3(\n     ^~~~~~~\n%Error: data/full_repos/permissive/492804614/Group_6_YODA_project/Group_6_YODA_project.srcs/sim_1/new/testbench.v:55: Cannot find file containing module: \'std_dev\'\n    std_dev std_dev_1(\n    ^~~~~~~\n%Error: Exiting due to 5 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
    reg clk;
    wire [31:0] sine_1, sine_2, sine_3, min_1, max_1, min_2, max_2, min_3, max_3;
    wire enable, done;
    wire [31:0] std_min_1, std_min_2, std_min_3, std_max_1, std_max_2, std_max_3;
    reg [2:0] interval = 1;
    

    audio_gen baseAudioGen(
        .clk(clk),
        .interval(interval),
        .enable(enable),
        .done(done),
        .sine_1(sine_1),
        .sine_2(sine_2),
        .sine_3(sine_3)
    );
    

    min_max min_max_1(
    .clk(clk),
    .enable(enable),
    .sound_Value(sine_1),
    .min(min_1),
    .max(max_1)
    );
    

    min_max min_max_2(
    .clk(clk),
    .enable(enable),
    .sound_Value(sine_2),
    .min(min_2),
    .max(max_2)
    );
    

     min_max min_max_3(
    .clk(clk),
    .enable(enable),
    .sound_Value(sine_3),
    .min(min_3),
    .max(max_3)
    );
    

    std_dev std_dev_1(
    .clk(clk),
    .done(done),
    .interval(interval),
    .min_1(min_1),
    .max_1(max_1),
    .min_2(min_2),
    .max_2(max_2),
    .min_3(min_3),
    .max_3(max_3),
    .std_min_1(std_min_1),
    .std_max_1(std_max_1),
    .std_min_2(std_min_2),
    .std_max_2(std_max_2),
    .std_min_3(std_min_3),
    .std_max_3(std_max_3)
    );
    
    parameter SIZE = 441000;
    parameter clockRate = 0.001;
    

    initial
    begin
    clk = 1'b0;
    end
    always #clockRate clk = ~clk;
    
endmodule
module testbench;

    reg clk;
    wire [31:0] sine_1, sine_2, sine_3, min_1, max_1, min_2, max_2, min_3, max_3;
    wire enable, done;
    wire [31:0] std_min_1, std_min_2, std_min_3, std_max_1, std_max_2, std_max_3;
    reg [2:0] interval = 1;
    

    audio_gen baseAudioGen(
        .clk(clk),
        .interval(interval),
        .enable(enable),
        .done(done),
        .sine_1(sine_1),
        .sine_2(sine_2),
        .sine_3(sine_3)
    );
    

    min_max min_max_1(
    .clk(clk),
    .enable(enable),
    .sound_Value(sine_1),
    .min(min_1),
    .max(max_1)
    );
    

    min_max min_max_2(
    .clk(clk),
    .enable(enable),
    .sound_Value(sine_2),
    .min(min_2),
    .max(max_2)
    );
    

     min_max min_max_3(
    .clk(clk),
    .enable(enable),
    .sound_Value(sine_3),
    .min(min_3),
    .max(max_3)
    );
    

    std_dev std_dev_1(
    .clk(clk),
    .done(done),
    .interval(interval),
    .min_1(min_1),
    .max_1(max_1),
    .min_2(min_2),
    .max_2(max_2),
    .min_3(min_3),
    .max_3(max_3),
    .std_min_1(std_min_1),
    .std_max_1(std_max_1),
    .std_min_2(std_min_2),
    .std_max_2(std_max_2),
    .std_min_3(std_min_3),
    .std_max_3(std_max_3)
    );
    
    parameter SIZE = 441000;
    parameter clockRate = 0.001;
    

    initial
    begin
    clk = 1'b0;
    end
    always #clockRate clk = ~clk;
    
endmodule