data/full_repos/permissive/497604366/cpu/cpu.srcs/sources_1/new/alu.v
data/verilator_xmls/ca07fb69-c154-4ace-995e-2b59e0f4c22e.xml
module alu(
    input [31:0] eqa,
    input [31:0] b,
    input [3:0] ealuc,
    output reg [31:0] r
    );
    always @(*) begin
        if (ealuc == 'b0000) begin
            r <= eqa & b;
        end
        if (ealuc == 'b0001) begin
            r <= eqa | b;
        end
        if (ealuc == 'b0010) begin
            r <= eqa + b;
        end
        if (ealuc == 'b0110) begin
            r <= eqa - b;
        end
        if (ealuc == 'b0011) begin
            r <= eqa ^ b;
        end
    end
endmodule
module alu(
    input [31:0] eqa,
    input [31:0] b,
    input [3:0] ealuc,
    output reg [31:0] r
    );

    always @(*) begin
        if (ealuc == 'b0000) begin
            r <= eqa & b;
        end
        if (ealuc == 'b0001) begin
            r <= eqa | b;
        end
        if (ealuc == 'b0010) begin
            r <= eqa + b;
        end
        if (ealuc == 'b0110) begin
            r <= eqa - b;
        end
        if (ealuc == 'b0011) begin
            r <= eqa ^ b;
        end
    end
endmodule