data/full_repos/permissive/500696213/verilog/rtl/digital_filter.v
data/verilator_xmls/2916bb43-735e-458e-91b5-a0408eb0b131.xml
module digital_filter (
`ifdef USE_POWER_PINS
    inout vdd,
    inout vss,
`endif
    input wire clk,
    input wire rst_n,
    input wire sclk,
    input wire cs_n,
    input wire unsigned data_in,
    output reg [11:0] data_out,
    output reg new_data,
    output reg serial_data_out
);



endmodule
module digital_filter (
`ifdef USE_POWER_PINS
    inout vdd,
    inout vss,
`endif
    input wire clk,
    input wire rst_n,
    input wire sclk,
    input wire cs_n,
    input wire unsigned data_in,
    output reg [11:0] data_out,
    output reg new_data,
    output reg serial_data_out
);




endmodule