data/full_repos/permissive/451853158/MIPS_Pipeline_Processor/reset_en_ff.v
data/verilator_xmls/6a2c37ce-3b24-4633-a83a-57491bb012ab.xml
module reset_en_ff #(
  parameter WIDTH = 32)
(
  input             clk, reset, en, clr,
  input      [WIDTH-1:0] d,
  output reg [WIDTH-1:0] q
);









always @(posedge clk or negedge reset)
  if (!reset)    q <= {WIDTH{1'b0}};
  else if (clr)  q <= {WIDTH{1'b0}};
  else if (!en)  q <= d;

endmodule
module reset_en_ff #(
  parameter WIDTH = 32)
(
  input             clk, reset, en, clr,
  input      [WIDTH-1:0] d,
  output reg [WIDTH-1:0] q
);










always @(posedge clk or negedge reset)
  if (!reset)    q <= {WIDTH{1'b0}};
  else if (clr)  q <= {WIDTH{1'b0}};
  else if (!en)  q <= d;

endmodule