data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v
1: b"%Error: data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v:85: syntax error, unexpected type, expecting IDENTIFIER or '[' or do or final\n input  wire [1:0]           type,     \n                             ^~~~\n%Error: data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v:87: syntax error, unexpected ')', expecting ',' or ';'\n);\n^\n%Error: data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v:90: syntax error, unexpected IDENTIFIER\n    mirror m1(.in(a), .out(ma));\n    ^~~~~~\n%Error: data/full_repos/permissive/462323524/designs/prv32_cpu/arith.v:379: syntax error, unexpected type\n        .type(alufn[1:0]),\n         ^~~~\n%Error: Exiting due to 4 error(s)\n"
module rca #(parameter n=32) ( 
	input  [n-1:0] 	a, b,
	input 			ci,
	output [n-1:0]	s,
	output			co
);
	wire [n:0] c;
	
	assign c[0] = ci;
	assign co = c[n];
	
	generate 
		genvar i;
		for(i=0; i<n; i=i+1) 
			sky130_fd_sc_hd__fa_1 FA ( .COUT(c[i+1]), .CIN(c[i]), .A(a[i]), .B(b[i]), .SUM(s[i]) );

   	endgenerate

endmodule
module rca #(parameter n=32) ( 
	input  [n-1:0] 	a, b,
	input 			ci,
	output [n-1:0]	s,
	output			co
);

	wire [n:0] c;
	
	assign c[0] = ci;
	assign co = c[n];
	
	generate 
		genvar i;
		for(i=0; i<n; i=i+1) 
			sky130_fd_sc_hd__fa_1 FA ( .COUT(c[i+1]), .CIN(c[i]), .A(a[i]), .B(b[i]), .SUM(s[i]) );

   	endgenerate

endmodule