data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/tb/support/rams_init_file.v
1: b'%Warning-WIDTH: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/tb/support/rams_init_file.v:35: Bit extraction of array[4096:0] requires 13 bit index, not 14 bits.\n                                                                                                             : ... In instance rams_init_file\n     ram[addr >> 2] <= din;\n        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/tb/support/rams_init_file.v:36: Bit extraction of array[4096:0] requires 13 bit index, not 14 bits.\n                                                                                                             : ... In instance rams_init_file\n  dout <= ram[addr >> 2];\n             ^\n%Error: Exiting due to 2 warning(s)\n'
module rams_init_file #(
    parameter MEM_INIT_FILE="",
    parameter INIT_FILE_BIN=1,
    parameter MEM_SIZE=2**12) (clk, we, addr, din, dout);

input clk;
input we;
input [$clog2(MEM_SIZE*4)-1:0] addr;
input [31:0] din;
output [31:0] dout;


reg [31:0] ram [0:MEM_SIZE];
reg [31:0] dout;

integer flen;
initial begin
    if (MEM_INIT_FILE != "") begin
        if (INIT_FILE_BIN==1) begin
            $readmemb(MEM_INIT_FILE, ram);
        end
        else begin
            $readmemh(MEM_INIT_FILE, ram);
        end
    end
end

always @(posedge clk)
begin
  if (we)
     ram[addr >> 2] <= din;
  dout <= ram[addr >> 2];
end endmodule
module rams_init_file #(
    parameter MEM_INIT_FILE="",
    parameter INIT_FILE_BIN=1,
    parameter MEM_SIZE=2**12) (clk, we, addr, din, dout);


input clk;
input we;
input [$clog2(MEM_SIZE*4)-1:0] addr;
input [31:0] din;
output [31:0] dout;


reg [31:0] ram [0:MEM_SIZE];
reg [31:0] dout;

integer flen;
initial begin
    if (MEM_INIT_FILE != "") begin
        if (INIT_FILE_BIN==1) begin
            $readmemb(MEM_INIT_FILE, ram);
        end
        else begin
            $readmemh(MEM_INIT_FILE, ram);
        end
    end
end

always @(posedge clk)
begin
  if (we)
     ram[addr >> 2] <= din;
  dout <= ram[addr >> 2];
end endmodule