data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/hdl/AXIOutputRegisters_v1_0.v
1: b"%Error: data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/hdl/AXIOutputRegisters_v1_0.v:62: Cannot find file containing module: 'AXIOutputRegisters_v1_0_S00_AXI'\n AXIOutputRegisters_v1_0_S00_AXI # ( \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/hdl,data/full_repos/permissive/506208052/AXIOutputRegisters_v1_0_S00_AXI\n             data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/hdl,data/full_repos/permissive/506208052/AXIOutputRegisters_v1_0_S00_AXI.v\n             data/full_repos/permissive/506208052/src/hdl/AXIOutputRegisters_1.0/hdl,data/full_repos/permissive/506208052/AXIOutputRegisters_v1_0_S00_AXI.sv\n             AXIOutputRegisters_v1_0_S00_AXI\n             AXIOutputRegisters_v1_0_S00_AXI.v\n             AXIOutputRegisters_v1_0_S00_AXI.sv\n             obj_dir/AXIOutputRegisters_v1_0_S00_AXI\n             obj_dir/AXIOutputRegisters_v1_0_S00_AXI.v\n             obj_dir/AXIOutputRegisters_v1_0_S00_AXI.sv\n%Error: Exiting due to 1 error(s)\n"
module AXIOutputRegisters_v1_0 #
	(







		parameter integer C_S00_AXI_DATA_WIDTH	= 32,
		parameter integer C_S00_AXI_ADDR_WIDTH	= 6
	)
	(


		output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg0_output,
        output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg1_output,
        output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg2_output,
        output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg3_output,
        output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg4_output,
        output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg5_output,
        output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg6_output,
        output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg7_output,
        output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg8_output,
        output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg9_output,
        output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg10_output,
        output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg11_output,
        output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg12_output,
        output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg13_output,
        output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg14_output,
        output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg15_output,




		input wire  s00_axi_aclk,
		input wire  s00_axi_aresetn,
		input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
		input wire [2 : 0] s00_axi_awprot,
		input wire  s00_axi_awvalid,
		output wire  s00_axi_awready,
		input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
		input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
		input wire  s00_axi_wvalid,
		output wire  s00_axi_wready,
		output wire [1 : 0] s00_axi_bresp,
		output wire  s00_axi_bvalid,
		input wire  s00_axi_bready,
		input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
		input wire [2 : 0] s00_axi_arprot,
		input wire  s00_axi_arvalid,
		output wire  s00_axi_arready,
		output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
		output wire [1 : 0] s00_axi_rresp,
		output wire  s00_axi_rvalid,
		input wire  s00_axi_rready
	);

	AXIOutputRegisters_v1_0_S00_AXI # ( 
		.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
		.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
	) AXIOutputRegisters_v1_0_S00_AXI_inst (
        .reg0_output(reg0_output),
        .reg1_output(reg1_output),
        .reg2_output(reg2_output),
        .reg3_output(reg3_output),
        .reg4_output(reg4_output),
        .reg5_output(reg5_output),
        .reg6_output(reg6_output),
        .reg7_output(reg7_output),
        .reg8_output(reg8_output),
        .reg9_output(reg9_output),
        .reg10_output(reg10_output),
        .reg11_output(reg11_output),
        .reg12_output(reg12_output),
        .reg13_output(reg13_output),
        .reg14_output(reg14_output),
        .reg15_output(reg15_output),
		.S_AXI_ACLK(s00_axi_aclk),
		.S_AXI_ARESETN(s00_axi_aresetn),
		.S_AXI_AWADDR(s00_axi_awaddr),
		.S_AXI_AWPROT(s00_axi_awprot),
		.S_AXI_AWVALID(s00_axi_awvalid),
		.S_AXI_AWREADY(s00_axi_awready),
		.S_AXI_WDATA(s00_axi_wdata),
		.S_AXI_WSTRB(s00_axi_wstrb),
		.S_AXI_WVALID(s00_axi_wvalid),
		.S_AXI_WREADY(s00_axi_wready),
		.S_AXI_BRESP(s00_axi_bresp),
		.S_AXI_BVALID(s00_axi_bvalid),
		.S_AXI_BREADY(s00_axi_bready),
		.S_AXI_ARADDR(s00_axi_araddr),
		.S_AXI_ARPROT(s00_axi_arprot),
		.S_AXI_ARVALID(s00_axi_arvalid),
		.S_AXI_ARREADY(s00_axi_arready),
		.S_AXI_RDATA(s00_axi_rdata),
		.S_AXI_RRESP(s00_axi_rresp),
		.S_AXI_RVALID(s00_axi_rvalid),
		.S_AXI_RREADY(s00_axi_rready)
	);





	endmodule
module AXIOutputRegisters_v1_0 #
	(







		parameter integer C_S00_AXI_DATA_WIDTH	= 32,
		parameter integer C_S00_AXI_ADDR_WIDTH	= 6
	)
	(


		output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg0_output,
        output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg1_output,
        output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg2_output,
        output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg3_output,
        output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg4_output,
        output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg5_output,
        output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg6_output,
        output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg7_output,
        output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg8_output,
        output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg9_output,
        output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg10_output,
        output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg11_output,
        output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg12_output,
        output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg13_output,
        output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg14_output,
        output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg15_output,




		input wire  s00_axi_aclk,
		input wire  s00_axi_aresetn,
		input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
		input wire [2 : 0] s00_axi_awprot,
		input wire  s00_axi_awvalid,
		output wire  s00_axi_awready,
		input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
		input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
		input wire  s00_axi_wvalid,
		output wire  s00_axi_wready,
		output wire [1 : 0] s00_axi_bresp,
		output wire  s00_axi_bvalid,
		input wire  s00_axi_bready,
		input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
		input wire [2 : 0] s00_axi_arprot,
		input wire  s00_axi_arvalid,
		output wire  s00_axi_arready,
		output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
		output wire [1 : 0] s00_axi_rresp,
		output wire  s00_axi_rvalid,
		input wire  s00_axi_rready
	);


	AXIOutputRegisters_v1_0_S00_AXI # ( 
		.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
		.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
	) AXIOutputRegisters_v1_0_S00_AXI_inst (
        .reg0_output(reg0_output),
        .reg1_output(reg1_output),
        .reg2_output(reg2_output),
        .reg3_output(reg3_output),
        .reg4_output(reg4_output),
        .reg5_output(reg5_output),
        .reg6_output(reg6_output),
        .reg7_output(reg7_output),
        .reg8_output(reg8_output),
        .reg9_output(reg9_output),
        .reg10_output(reg10_output),
        .reg11_output(reg11_output),
        .reg12_output(reg12_output),
        .reg13_output(reg13_output),
        .reg14_output(reg14_output),
        .reg15_output(reg15_output),
		.S_AXI_ACLK(s00_axi_aclk),
		.S_AXI_ARESETN(s00_axi_aresetn),
		.S_AXI_AWADDR(s00_axi_awaddr),
		.S_AXI_AWPROT(s00_axi_awprot),
		.S_AXI_AWVALID(s00_axi_awvalid),
		.S_AXI_AWREADY(s00_axi_awready),
		.S_AXI_WDATA(s00_axi_wdata),
		.S_AXI_WSTRB(s00_axi_wstrb),
		.S_AXI_WVALID(s00_axi_wvalid),
		.S_AXI_WREADY(s00_axi_wready),
		.S_AXI_BRESP(s00_axi_bresp),
		.S_AXI_BVALID(s00_axi_bvalid),
		.S_AXI_BREADY(s00_axi_bready),
		.S_AXI_ARADDR(s00_axi_araddr),
		.S_AXI_ARPROT(s00_axi_arprot),
		.S_AXI_ARVALID(s00_axi_arvalid),
		.S_AXI_ARREADY(s00_axi_arready),
		.S_AXI_RDATA(s00_axi_rdata),
		.S_AXI_RRESP(s00_axi_rresp),
		.S_AXI_RVALID(s00_axi_rvalid),
		.S_AXI_RREADY(s00_axi_rready)
	);





	endmodule