data/full_repos/permissive/441359809/src/yosys/manual/PRESENTATION_ExAdv/sym_mul_test.v
data/verilator_xmls/8423be9e-69c0-457c-9769-1793685cb172.xml
module test(A, B, C, Y1, Y2);
    input   [7:0] A, B, C;
    output  [7:0] Y1 = A * B;
    output [15:0] Y2 = A * C;
endmodule
module test(A, B, C, Y1, Y2);

    input   [7:0] A, B, C;
    output  [7:0] Y1 = A * B;
    output [15:0] Y2 = A * C;
endmodule