data/full_repos/permissive/427220253/State_Machine_Test/mem_test_sm_tb.sv
1: b'%Error: data/full_repos/permissive/427220253/State_Machine_Test/mem_test_sm_tb.sv:26: Unsupported: Static in this context\n static integer   flipped_bits;\n ^~~~~~\n%Error: data/full_repos/permissive/427220253/State_Machine_Test/mem_test_sm_tb.sv:27: Unsupported: Static in this context\n static integer   read_count;\n ^~~~~~\n%Error: data/full_repos/permissive/427220253/State_Machine_Test/mem_test_sm_tb.sv:28: Unsupported: Static in this context\n static integer   write_count;\n ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/427220253/State_Machine_Test/mem_test_sm_tb.sv:61: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/427220253/State_Machine_Test/mem_test_sm_tb.sv:68: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/427220253/State_Machine_Test/mem_test_sm_tb.sv:86: Unsupported or unknown PLI call: $urandom_range\n  wait_cycles($urandom_range(1,10));\n              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427220253/State_Machine_Test/mem_test_sm_tb.sv:95: Unsupported or unknown PLI call: $urandom_range\n  wait_cycles($urandom_range(1,5));\n              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427220253/State_Machine_Test/mem_test_sm_tb.sv:98: Unsupported or unknown PLI call: $urandom_range\n  if($urandom_range(1,20) == 1) begin\n     ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427220253/State_Machine_Test/mem_test_sm_tb.sv:99: Unsupported or unknown PLI call: $urandom_range\n   automatic integer num_of_flips = $urandom_range(1,1);\n                                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427220253/State_Machine_Test/mem_test_sm_tb.sv:101: Unsupported or unknown PLI call: $urandom_range\n    automatic integer pos = $urandom_range(0,31);\n                            ^~~~~~~~~~~~~~\n%Error: Exiting due to 9 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_top;


	logic clk;
	logic reset;
	logic confirm;
	logic [31:0] pattern;
	logic [31:0] pattern_rb;
	logic [31:0] count;
	logic [31:0] address;
	

	logic [63:0] bit_flip_count;
	logic [31:0] generated_word;
	logic [31:0] generated_address;
	logic [3:0]	 state;
	logic 		 write;
	logic			 read;
	

	logic			 ready;
	

	static integer		 flipped_bits;
	static integer		 read_count;
	static integer		 write_count;
	

	mem_test_sm 	
						#(
							.ADDR_WIDTH(32),
							.WORD_WIDTH(32),
							.ROW_WIDTH (12),
							.ROW_POS   (10),
							.COL_WIDTH (10),
							.COL_POS	  (0 )
						)
						dut(
							.clk(clk),
							.reset(reset),
							.confirm(confirm),
							.pattern(pattern),
							.pattern_rb(pattern_rb),
							.count(count),
							.address(address),
							
							.bit_flip_count(bit_flip_count),
							.gen_word(generated_word),
							.gen_address(generated_address),
							.state(state),
							.write(write),
							.read(read)
						);
						

	initial begin
	clk <= 1'b0;
		forever begin
		#1 clk = ~clk;
		end
	end
	

	task wait_cycles(int cycles);
		repeat(cycles) begin
		@(posedge clk);
		@(negedge clk);
		end
	endtask

	task do_reset();
		reset <= 'b0;
		wait_cycles(5);
		reset <= 'b1;
		wait_cycles(5);
		reset <= 'b0;
		write_count = 0;
		read_count = 0;
		flipped_bits = 0;
	endtask
	
	task do_write();
		confirm <= 'b0;
		wait_cycles($urandom_range(1,10));
		confirm <= 'b1;
		wait_cycles(1);
		confirm <= 'b0;
		write_count++;
	endtask
	
	task do_read();
		confirm <= 'b0;
		wait_cycles($urandom_range(1,5));
		pattern_rb = pattern;

		if($urandom_range(1,20) == 1) begin
			automatic integer num_of_flips = $urandom_range(1,1);
			for(int i = 0; i < num_of_flips; i++) begin
				automatic integer pos = $urandom_range(0,31);
				pattern_rb[pos] = pattern_rb[pos] ^ 1'b1;
				flipped_bits++;
			end
		end
		wait_cycles(1);
		confirm <= 'b1;
		wait_cycles(1);
		confirm <= 'b0;
		read_count++;
	endtask


	initial begin

		pattern <= 32'hffffffff;
		address <= 32'h000aaaaa;
		count	  <= 32'd100000;
		pattern_rb <= 'b0;
		confirm <= 'b0;
		

		do_reset();
		

		while(state != 4'd5) begin
			if(write) begin
				$display("beginning write=%0d time=%0t addr=0x%0h word=0x%0h",write_count, $time, generated_address, generated_word);
				do_write();
			end
			else if(read) begin
				$display("beginning read=%0d time=%0t addr=0x%0h",read_count, $time, generated_address);
				do_read();
			end
			if(state == 4'd7)
				flipped_bits = 0;

			wait_cycles(1);
		end
		$display("finished expected=%0d actual=%0d", flipped_bits, bit_flip_count);
		$finish;
	end
	endmodule
module tb_top;



	logic clk;
	logic reset;
	logic confirm;
	logic [31:0] pattern;
	logic [31:0] pattern_rb;
	logic [31:0] count;
	logic [31:0] address;
	

	logic [63:0] bit_flip_count;
	logic [31:0] generated_word;
	logic [31:0] generated_address;
	logic [3:0]	 state;
	logic 		 write;
	logic			 read;
	

	logic			 ready;
	

	static integer		 flipped_bits;
	static integer		 read_count;
	static integer		 write_count;
	

	mem_test_sm 	
						#(
							.ADDR_WIDTH(32),
							.WORD_WIDTH(32),
							.ROW_WIDTH (12),
							.ROW_POS   (10),
							.COL_WIDTH (10),
							.COL_POS	  (0 )
						)
						dut(
							.clk(clk),
							.reset(reset),
							.confirm(confirm),
							.pattern(pattern),
							.pattern_rb(pattern_rb),
							.count(count),
							.address(address),
							
							.bit_flip_count(bit_flip_count),
							.gen_word(generated_word),
							.gen_address(generated_address),
							.state(state),
							.write(write),
							.read(read)
						);
						

	initial begin
	clk <= 1'b0;
		forever begin
		#1 clk = ~clk;
		end
	end
	

	task wait_cycles(int cycles);
		repeat(cycles) begin
		@(posedge clk);
		@(negedge clk);
		end
	endtask

	task do_reset();
		reset <= 'b0;
		wait_cycles(5);
		reset <= 'b1;
		wait_cycles(5);
		reset <= 'b0;
		write_count = 0;
		read_count = 0;
		flipped_bits = 0;
	endtask
	
	task do_write();
		confirm <= 'b0;
		wait_cycles($urandom_range(1,10));
		confirm <= 'b1;
		wait_cycles(1);
		confirm <= 'b0;
		write_count++;
	endtask
	
	task do_read();
		confirm <= 'b0;
		wait_cycles($urandom_range(1,5));
		pattern_rb = pattern;

		if($urandom_range(1,20) == 1) begin
			automatic integer num_of_flips = $urandom_range(1,1);
			for(int i = 0; i < num_of_flips; i++) begin
				automatic integer pos = $urandom_range(0,31);
				pattern_rb[pos] = pattern_rb[pos] ^ 1'b1;
				flipped_bits++;
			end
		end
		wait_cycles(1);
		confirm <= 'b1;
		wait_cycles(1);
		confirm <= 'b0;
		read_count++;
	endtask


	initial begin

		pattern <= 32'hffffffff;
		address <= 32'h000aaaaa;
		count	  <= 32'd100000;
		pattern_rb <= 'b0;
		confirm <= 'b0;
		

		do_reset();
		

		while(state != 4'd5) begin
			if(write) begin
				$display("beginning write=%0d time=%0t addr=0x%0h word=0x%0h",write_count, $time, generated_address, generated_word);
				do_write();
			end
			else if(read) begin
				$display("beginning read=%0d time=%0t addr=0x%0h",read_count, $time, generated_address);
				do_read();
			end
			if(state == 4'd7)
				flipped_bits = 0;

			wait_cycles(1);
		end
		$display("finished expected=%0d actual=%0d", flipped_bits, bit_flip_count);
		$finish;
	end
	endmodule