data/full_repos/permissive/480681467/main/main.v
1: b'%Warning-WIDTH: data/full_repos/permissive/480681467/main/main.v:25: Operator ASSIGN expects 65 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 64 bits.\n                                                                   : ... In instance control.i.x_mod_y\n           p = {p[WIDTH-2:0],A[WIDTH-1]};\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/main.v:38: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'p\' generates 65 bits.\n                                                                   : ... In instance control.i.x_mod_y\n   assign R = p,Q = A;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/main.v:114: Operator SUB expects 64 bits on the LHS, but LHS\'s VARREF \'p\' generates 32 bits.\n                                                                    : ... In instance control.i\n    wire [WIDTH*2-1:0] totient = (p-1)*(q-1);\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/main.v:114: Operator SUB expects 64 bits on the LHS, but LHS\'s VARREF \'q\' generates 32 bits.\n                                                                    : ... In instance control.i\n    wire [WIDTH*2-1:0] totient = (p-1)*(q-1);\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/main.v:119: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'e_reg\' generates 32 bits.\n                                                                    : ... In instance control.i\n    assign e = e_reg;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/main.v:151: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'e_plus3\' generates 32 bits.\n                                                                    : ... In instance control.i\n                         b <= e_plus3;\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/main.v:77: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h1\' generates 32 bits.\n                                                                   : ... In instance control.m\n            result_reg <= 32\'d1;\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/480681467/main/main.v:190: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s VARREF \'msg_in\' generates 32 bits.\n                                                                    : ... In instance control\n         msg_reg <= msg_in;\n                 ^~\n%Error: Exiting due to 8 warning(s)\n'
module inverter(
    input [WIDTH-1:0] p,
	input [WIDTH-1:0] q,
	input clk,
	input reset,
	output finish,
	output [WIDTH*2-1:0] e,
	output [WIDTH*2-1:0] d
    );
    
    parameter WIDTH = 32;
    
    reg [WIDTH*2-1:0] totient_reg,a,b,y,y_prev;
    reg [2:0] state;
    reg [WIDTH-1:0] e_reg;
    
    wire [WIDTH*2-1:0] totient = (p-1)*(q-1);
    wire [WIDTH*2-1:0] quotient,b_next;
    wire [WIDTH*2-1:0] y_next = y_prev - quotient * y;
    wire [WIDTH-1:0] e_plus3 = e_reg + 2;
    assign finish = (state == `HOLDING) ? 1'b1 : 1'b0;
    assign e = e_reg;
    assign d = y_prev;
    
    mod x_mod_y(a,b,b_next,quotient);
    defparam x_mod_y.WIDTH = WIDTH*2;
    
    always @(posedge clk) begin
        if(reset) begin
            totient_reg <= totient;
            a <= totient;
            b <= 3;
            e_reg <=3;
            y <= 1;
            y_prev <= 0;
            state = `UPDATING;
        end 
              case(state)
                `UPDATING: begin
                    if(b != 64'd0) begin
                        a <= b;
                        b <= b_next;
                        y <= y_next;
                        y_prev <= y;
                        state <= `UPDATING;
                    end
                    else state <= `CHECK;
                 end
                `CHECK: begin
                    if(a == 64'd1 && y_prev[WIDTH*2-1] == 1'b0) 
                        state = `HOLDING;
                    else begin
                         a <= totient_reg;
                         b <= e_plus3;
                         e_reg <= e_plus3;
                         y <= 1;
                         y_prev = 0;
                         state <= `UPDATING;
                   end
                 end
                `HOLDING: begin
                    end
           endcase 
    end
    
endmodule
module inverter(
    input [WIDTH-1:0] p,
	input [WIDTH-1:0] q,
	input clk,
	input reset,
	output finish,
	output [WIDTH*2-1:0] e,
	output [WIDTH*2-1:0] d
    );

    
    parameter WIDTH = 32;
    
    reg [WIDTH*2-1:0] totient_reg,a,b,y,y_prev;
    reg [2:0] state;
    reg [WIDTH-1:0] e_reg;
    
    wire [WIDTH*2-1:0] totient = (p-1)*(q-1);
    wire [WIDTH*2-1:0] quotient,b_next;
    wire [WIDTH*2-1:0] y_next = y_prev - quotient * y;
    wire [WIDTH-1:0] e_plus3 = e_reg + 2;
    assign finish = (state == `HOLDING) ? 1'b1 : 1'b0;
    assign e = e_reg;
    assign d = y_prev;
    
    mod x_mod_y(a,b,b_next,quotient);
    defparam x_mod_y.WIDTH = WIDTH*2;
    
    always @(posedge clk) begin
        if(reset) begin
            totient_reg <= totient;
            a <= totient;
            b <= 3;
            e_reg <=3;
            y <= 1;
            y_prev <= 0;
            state = `UPDATING;
        end 
              case(state)
                `UPDATING: begin
                    if(b != 64'd0) begin
                        a <= b;
                        b <= b_next;
                        y <= y_next;
                        y_prev <= y;
                        state <= `UPDATING;
                    end
                    else state <= `CHECK;
                 end
                `CHECK: begin
                    if(a == 64'd1 && y_prev[WIDTH*2-1] == 1'b0) 
                        state = `HOLDING;
                    else begin
                         a <= totient_reg;
                         b <= e_plus3;
                         e_reg <= e_plus3;
                         y <= 1;
                         y_prev = 0;
                         state <= `UPDATING;
                   end
                 end
                `HOLDING: begin
                    end
           endcase 
    end
    
endmodule