data/full_repos/permissive/461000256/hdl/MEM_WB.v
data/verilator_xmls/04abb817-59e6-4a50-9aca-9c683bbf8577.xml
module MEM_WB (
	input wire 			clk,	
	input wire [`DW-1:0] 	in_data,		
	input wire [`IW-1:0] in_inst,
	output reg [`DW-1:0] 	out_data,
	output reg [`IW-1:0] out_inst
);

	always @(posedge clk) begin
		out_data <= #7 in_data;
		out_inst <= #7 in_inst;
	end


endmodule
module MEM_WB (
	input wire 			clk,	
	input wire [`DW-1:0] 	in_data,		
	input wire [`IW-1:0] in_inst,
	output reg [`DW-1:0] 	out_data,
	output reg [`IW-1:0] out_inst
);


	always @(posedge clk) begin
		out_data <= #7 in_data;
		out_inst <= #7 in_inst;
	end


endmodule