data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/twos_to_ADC_offset_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/twos_to_ADC_offset_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #H_period;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/twos_to_ADC_offset_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #H_period;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/twos_to_ADC_offset_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #H_period;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/twos_to_ADC_offset_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #H_period;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/twos_to_ADC_offset_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #H_period;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/twos_to_ADC_offset_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #H_period;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/twos_to_ADC_offset_tb.v:4: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'14\'h0\' generates 14 bits.\n                                                                                                        : ... In instance twos_to_ADC_offset_tb\nreg [11:0]DATA_IN=14\'h0000;\n                  ^~~~~~~~\n%Error: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/twos_to_ADC_offset_tb.v:7: Cannot find file containing module: \'twos_to_ADC_offset\'\ntwos_to_ADC_offset  #(.WIRE_WIDTH(12)) ADCO0 (.data_in(DATA_IN), .data_out(DATA_OUT));\n^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb,data/full_repos/permissive/503053625/twos_to_ADC_offset\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb,data/full_repos/permissive/503053625/twos_to_ADC_offset.v\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb,data/full_repos/permissive/503053625/twos_to_ADC_offset.sv\n             twos_to_ADC_offset\n             twos_to_ADC_offset.v\n             twos_to_ADC_offset.sv\n             obj_dir/twos_to_ADC_offset\n             obj_dir/twos_to_ADC_offset.v\n             obj_dir/twos_to_ADC_offset.sv\n%Warning-WIDTH: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/twos_to_ADC_offset_tb.v:12: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'14\'hca3\' generates 14 bits.\n                                                                                                         : ... In instance twos_to_ADC_offset_tb\n    DATA_IN = 14\'h0ca3;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/twos_to_ADC_offset_tb.v:14: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'14\'hfff\' generates 14 bits.\n                                                                                                         : ... In instance twos_to_ADC_offset_tb\n    DATA_IN = 14\'h0fff;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/twos_to_ADC_offset_tb.v:16: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'14\'h0\' generates 14 bits.\n                                                                                                         : ... In instance twos_to_ADC_offset_tb\n    DATA_IN = 14\'h0000;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/twos_to_ADC_offset_tb.v:18: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'14\'h1\' generates 14 bits.\n                                                                                                         : ... In instance twos_to_ADC_offset_tb\n    DATA_IN = 14\'h0001;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/twos_to_ADC_offset_tb.v:20: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'14\'h7ff\' generates 14 bits.\n                                                                                                         : ... In instance twos_to_ADC_offset_tb\n    DATA_IN = 14\'h07ff;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/twos_to_ADC_offset_tb.v:22: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'14\'ha10\' generates 14 bits.\n                                                                                                         : ... In instance twos_to_ADC_offset_tb\n    DATA_IN = 14\'h0a10;\n            ^\n%Error: Exiting due to 1 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module twos_to_ADC_offset_tb;
localparam H_period=2;

reg [11:0]DATA_IN=14'h0000;
wire [11:0]DATA_OUT;

twos_to_ADC_offset  #(.WIRE_WIDTH(12)) ADCO0 (.data_in(DATA_IN), .data_out(DATA_OUT));

initial
begin   
    #H_period;
    DATA_IN = 14'h0ca3;
    #H_period;
    DATA_IN = 14'h0fff;
    #H_period;
    DATA_IN = 14'h0000;
    #H_period;
    DATA_IN = 14'h0001;
    #H_period;
    DATA_IN = 14'h07ff;
    #H_period;
    DATA_IN = 14'h0a10;
end
endmodule
module twos_to_ADC_offset_tb;

localparam H_period=2;

reg [11:0]DATA_IN=14'h0000;
wire [11:0]DATA_OUT;

twos_to_ADC_offset  #(.WIRE_WIDTH(12)) ADCO0 (.data_in(DATA_IN), .data_out(DATA_OUT));

initial
begin   
    #H_period;
    DATA_IN = 14'h0ca3;
    #H_period;
    DATA_IN = 14'h0fff;
    #H_period;
    DATA_IN = 14'h0000;
    #H_period;
    DATA_IN = 14'h0001;
    #H_period;
    DATA_IN = 14'h07ff;
    #H_period;
    DATA_IN = 14'h0a10;
end
endmodule