data/full_repos/permissive/515477729/source/counter.v
data/verilator_xmls/50059161-85d8-4309-82c6-88b3175b07f0.xml
module counter (output reg [4:0] count, input dec, clk, ldCnt);

    always @(posedge clk) begin
        if (ldCnt)
            count <= 5'b00101;
            
        else if (count != 0) begin
            if (dec)
                count <= count - 1;
        end

        else
            count <= count;
        
    end

endmodule
module counter (output reg [4:0] count, input dec, clk, ldCnt);


    always @(posedge clk) begin
        if (ldCnt)
            count <= 5'b00101;
            
        else if (count != 0) begin
            if (dec)
                count <= count - 1;
        end

        else
            count <= count;
        
    end

endmodule