data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:10: Cannot find include file: sim_clks_rsts.vh\n`include "sim_clks_rsts.vh" \n         ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback,data/full_repos/permissive/447976230/sim_clks_rsts.vh\n             data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback,data/full_repos/permissive/447976230/sim_clks_rsts.vh.v\n             data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback,data/full_repos/permissive/447976230/sim_clks_rsts.vh.sv\n             sim_clks_rsts.vh\n             sim_clks_rsts.vh.v\n             sim_clks_rsts.vh.sv\n             obj_dir/sim_clks_rsts.vh\n             obj_dir/sim_clks_rsts.vh.v\n             obj_dir/sim_clks_rsts.vh.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:11: Cannot find include file: sim_exec_report.vh\n`include "sim_exec_report.vh" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:12: Cannot find include file: sim_cvita_lib.svh\n`include "sim_cvita_lib.svh" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:13: Cannot find include file: sim_axi4_lib.svh\n`include "sim_axi4_lib.svh" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:14: Cannot find include file: sim_set_rb_lib.svh\n`include "sim_set_rb_lib.svh" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:17: Define or directive not defined: \'`TEST_BENCH_INIT\'\n  `TEST_BENCH_INIT("one_gig_eth_loopback_tb",13,1)\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:17: syntax error, unexpected \'(\'\n  `TEST_BENCH_INIT("one_gig_eth_loopback_tb",13,1)\n                   ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:20: Define or directive not defined: \'`DEFINE_CLK\'\n  `DEFINE_CLK(ETH_CLK_P, 1000/125, 50)   \n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:21: Define or directive not defined: \'`DEFINE_RESET\'\n  `DEFINE_RESET(GSR, 0, 100)               \n  ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:80: Unsupported: Ignoring delay on this delayed statement.\n      #0.5;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:82: Unsupported: Ignoring delay on this delayed statement.\n      #0.5;\n      ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:256: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                        : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Wait for reset");\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:256: syntax error, unexpected \';\'\n    `TEST_CASE_START("Wait for reset");\n                                      ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:257: syntax error, unexpected \'@\'\n    while (GSR) @(posedge ETH_CLK_P);\n                ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:258: Define or directive not defined: \'`TEST_CASE_DONE\'\n    `TEST_CASE_DONE((~GSR));\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:258: syntax error, unexpected \';\'\n    `TEST_CASE_DONE((~GSR));\n                           ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:262: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                        : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Wait for master channel to come up");\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:262: syntax error, unexpected \';\'\n    `TEST_CASE_START("Wait for master channel to come up");\n                                                          ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:263: syntax error, unexpected \'@\'\n    while (m_channel_up !== 1\'b1) @(posedge m_user_clk);\n                                  ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:264: Define or directive not defined: \'`TEST_CASE_DONE\'\n    `TEST_CASE_DONE(1\'b1);\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:264: syntax error, unexpected \';\'\n    `TEST_CASE_DONE(1\'b1);\n                         ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:266: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                        : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Wait for slave channel to come up");\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:266: syntax error, unexpected \';\'\n    `TEST_CASE_START("Wait for slave channel to come up");\n                                                         ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:267: syntax error, unexpected \'@\'\n    while (s_channel_up !== 1\'b1) @(posedge s_user_clk);\n                                  ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:268: Define or directive not defined: \'`TEST_CASE_DONE\'\n    `TEST_CASE_DONE(1\'b1);\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:268: syntax error, unexpected \';\'\n    `TEST_CASE_DONE(1\'b1);\n                         ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:286: syntax error, unexpected \'@\'\n   repeat(1000) @(posedge m_user_clk);\n                ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:292: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                        : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Fill up empty FIFO then drain (short packet)");\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:292: syntax error, unexpected \';\'\n    `TEST_CASE_START("Fill up empty FIFO then drain (short packet)");\n                                                                    ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:297: Define or directive not defined: \'`ASSERT_ERROR\'\n      `ASSERT_ERROR(stats.count==16,            "Bad packet: Length mismatch");\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:297: syntax error, unexpected \',\'\n      `ASSERT_ERROR(stats.count==16,            "Bad packet: Length mismatch");\n                                   ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:298: Define or directive not defined: \'`ASSERT_ERROR\'\n      `ASSERT_ERROR(header.dst_sid==header_out.dst_sid, "Bad packet: Wrong SID");\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:298: syntax error, unexpected \',\'\n      `ASSERT_ERROR(header.dst_sid==header_out.dst_sid, "Bad packet: Wrong SID");\n                                                      ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:299: Define or directive not defined: \'`TEST_CASE_DONE\'\n    `TEST_CASE_DONE(1);\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:299: syntax error, unexpected \';\'\n    `TEST_CASE_DONE(1);\n                      ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:301: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                        : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Fill up empty FIFO then drain (long packet)");\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:301: syntax error, unexpected \';\'\n    `TEST_CASE_START("Fill up empty FIFO then drain (long packet)");\n                                                                   ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:306: Define or directive not defined: \'`ASSERT_ERROR\'\n      `ASSERT_ERROR(stats.count==256,           "Bad packet: Length mismatch");\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:306: syntax error, unexpected \',\'\n      `ASSERT_ERROR(stats.count==256,           "Bad packet: Length mismatch");\n                                    ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:307: Define or directive not defined: \'`ASSERT_ERROR\'\n      `ASSERT_ERROR(header.dst_sid==header_out.dst_sid, "Bad packet: Wrong SID");\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:307: syntax error, unexpected \',\'\n      `ASSERT_ERROR(header.dst_sid==header_out.dst_sid, "Bad packet: Wrong SID");\n                                                      ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:308: Define or directive not defined: \'`TEST_CASE_DONE\'\n    `TEST_CASE_DONE(1);\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:308: syntax error, unexpected \';\'\n    `TEST_CASE_DONE(1);\n                      ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:314: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                        : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Concurrent read and write (single packet)");\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:314: syntax error, unexpected \';\'\n    `TEST_CASE_START("Concurrent read and write (single packet)");\n                                                                 ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:316: Unsupported: fork statements\n      fork\n      ^~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:325: Define or directive not defined: \'`ASSERT_ERROR\'\n    `ASSERT_ERROR(stats.count==1000, "Bad packet: Length mismatch");\n    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:325: syntax error, unexpected \',\'\n    `ASSERT_ERROR(stats.count==1000, "Bad packet: Length mismatch");\n                                   ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:326: Define or directive not defined: \'`TEST_CASE_DONE\'\n    `TEST_CASE_DONE(1);\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:326: syntax error, unexpected \';\'\n    `TEST_CASE_DONE(1);\n                      ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:328: Define or directive not defined: \'`TEST_CASE_START\'\n                                                                                                                        : ... Suggested alternative: \'`SV_COV_START\'\n    `TEST_CASE_START("Concurrent read and write (multiple packets)");\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/n3xx/sim/one_gig_eth_loopback/one_gig_eth_loopback_tb.sv:328: syntax error, unexpected \';\'\n    `TEST_CASE_START("Concurrent read and write (multiple packets)");\n                                                                    ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module one_gig_eth_loopback_tb();
  `TEST_BENCH_INIT("one_gig_eth_loopback_tb",`NUM_TEST_CASES,`NS_PER_TICK)


  `DEFINE_CLK(ETH_CLK_P, 1000/125, 50)
  `DEFINE_RESET(GSR, 0, 100)

  wire ETH_CLK_N = ~ETH_CLK_P;
  wire SFP_LN0_P, SFP_LN0_N, SFP_LN1_P, SFP_LN1_N;


  localparam PORTNUM = 8'd0;












  wire gige_refclk, gige_refclk_bufg;
  wire m_user_clk, s_user_clk;
  wire m_channel_up, s_channel_up;
  wire [7:0]  m_gmii_txd, m_gmii_rxd;
  wire        m_gmii_tx_en, m_gmii_tx_er, m_gmii_rx_dv, m_gmii_rx_er;
  wire        m_gmii_clk;
  wire [7:0]  s_gmii_txd, s_gmii_rxd;
  wire        s_gmii_tx_en, s_gmii_tx_er, s_gmii_rx_dv, s_gmii_rx_er;
  wire        s_gmii_clk;
  wire [15:0] m_phy_status;
  wire [15:0] s_phy_status;
  wire [63:0] loop_tdata;
  wire        loop_tlast, loop_tvalid, loop_tready;


  reg independent_clock;
  assign m_channel_up = m_phy_status[0];
  assign s_channel_up = s_phy_status[0];


  assign m_user_clk = independent_clock;
  assign s_user_clk = independent_clock;
  wire gt0_qplloutclk, gt0_qplloutrefclk, pma_reset;

  one_gige_phy_clk_gen gige_clk_gen_i (
     .areset(GSR),
     .refclk_p(ETH_CLK_P),
     .refclk_n(ETH_CLK_N),
     .refclk(gige_refclk),
     .refclk_bufg(gige_refclk_bufg)
  );

  cvita_master m_tx_chdr (.clk(m_user_clk));
  cvita_slave s_rx_chdr (.clk(s_user_clk));
  initial
  begin
    independent_clock <= 1'b0;
    forever
    begin
      independent_clock <= 1'b0;
      #0.5;
      independent_clock <= 1'b1;
      #0.5;
    end
  end




   wire mdc, mdio_m2s, mdio_s2m;

   mdio_master #(
      .MDC_DIVIDER   (8'd200)
   ) mdio_master_i (
      .clk        (m_user_clk),
      .rst        (GSR),
      .mdc        (mdc),
      .mdio_in    (mdio_s2m),
      .mdio_out   (mdio_m2s),
      .mdio_tri   (),
      .reg_wr_req (),
      .reg_wr_addr(),
      .reg_wr_data(),
      .reg_rd_req (),
      .reg_rd_addr(),
      .reg_rd_data(),
      .reg_rd_resp()
   );


   one_gig_eth_pcs_pma_gt_common core_gt_common_i
   (
    .GTREFCLK0_IN                (gige_refclk) ,
    .QPLLLOCK_OUT                (),
    .QPLLLOCKDETCLK_IN           (independent_clock),
    .QPLLOUTCLK_OUT              (gt0_qplloutclk),
    .QPLLOUTREFCLK_OUT           (gt0_qplloutrefclk),
    .QPLLREFCLKLOST_OUT          (),
    .QPLLRESET_IN                (pma_reset)
   );

  one_gige_phy one_gige_phy_master_i
  (
     .reset(GSR),
     .independent_clock(independent_clock),
     .pma_reset_out(pma_reset),
     .gt0_qplloutclk_in(gt0_qplloutclk),
     .gt0_qplloutrefclk_in(gt0_qplloutrefclk),

     .gtrefclk(gige_refclk),
     .gtrefclk_bufg(gige_refclk_bufg),
     .txp(SFP_LN1_P),
     .txn(SFP_LN1_N),
     .rxp(SFP_LN0_P),
     .rxn(SFP_LN0_N),

     .gmii_clk(m_gmii_clk),
     .gmii_txd(m_gmii_txd),
     .gmii_tx_en(m_gmii_tx_en),
     .gmii_tx_er(m_gmii_tx_er),
     .gmii_rxd(m_gmii_rxd),
     .gmii_rx_dv(m_gmii_rx_dv),
     .gmii_rx_er(m_gmii_rx_er),

     .mdc(mdc),
     .mdio_i(mdio_m2s),
     .mdio_o(mdio_s2m),
     .mdio_t(),
     .configuration_vector(5'd0),
     .configuration_valid(1'b1),

     .status_vector(m_phy_status),
     .signal_detect(1'b1)
  );

      simple_gemac_wrapper #(.RX_FLOW_CTRL(0), .PORTNUM(PORTNUM)) simple_gemac_wrapper_master_i
      (
         .clk125(m_gmii_clk),
         .reset(GSR),

         .GMII_GTX_CLK(),
         .GMII_TX_EN(m_gmii_tx_en),
         .GMII_TX_ER(m_gmii_tx_er),
         .GMII_TXD(m_gmii_txd),
         .GMII_RX_CLK(m_gmii_clk),
         .GMII_RX_DV(m_gmii_rx_dv),
         .GMII_RX_ER(m_gmii_rx_er),
         .GMII_RXD(m_gmii_rxd),

         .sys_clk(m_user_clk),
         .rx_tdata(s_rx_chdr.axis.tdata),
         .rx_tuser(),
         .rx_tlast(s_rx_chdr.axis.tlast),
         .rx_tvalid(s_rx_chdr.axis.tvalid),
         .rx_tready(s_rx_chdr.axis.tready),
         .tx_tdata(m_tx_chdr.axis.tdata),
         .tx_tuser(),
         .tx_tlast(m_tx_chdr.axis.tlast),
         .tx_tvalid(m_tx_chdr.axis.tvalid),
         .tx_tready(m_tx_chdr.axis.tready),

         .debug_tx(), .debug_rx()
      );

  one_gige_phy one_gige_phy_slave_i
  (
     .reset(GSR),
     .independent_clock(independent_clock),
     .pma_reset_out(),
     .gt0_qplloutclk_in(gt0_qplloutclk),
     .gt0_qplloutrefclk_in(gt0_qplloutrefclk),

     .gtrefclk(gige_refclk),
     .gtrefclk_bufg(gige_refclk_bufg),
     .txp(SFP_LN0_P),
     .txn(SFP_LN0_N),
     .rxp(SFP_LN1_P),
     .rxn(SFP_LN1_N),

     .gmii_clk(s_gmii_clk),
     .gmii_txd(s_gmii_txd),
     .gmii_tx_en(s_gmii_tx_en),
     .gmii_tx_er(s_gmii_tx_er),
     .gmii_rxd(s_gmii_rxd),
     .gmii_rx_dv(s_gmii_rx_dv),
     .gmii_rx_er(s_gmii_rx_er),

     .mdc(mdc),
     .mdio_i(mdio_m2s),
     .mdio_o(mdio_s2m),
     .mdio_t(),
     .configuration_vector(5'd0),
     .configuration_valid(1'b1),

     .status_vector(s_phy_status),
     .signal_detect(1'b1)
  );

      simple_gemac_wrapper #(.RX_FLOW_CTRL(0), .PORTNUM(PORTNUM)) simple_gemac_wrapper_slave_i
      (
         .clk125(s_gmii_clk),
         .reset(GSR),

         .GMII_GTX_CLK(),
         .GMII_TX_EN(s_gmii_tx_en),
         .GMII_TX_ER(s_gmii_tx_er),
         .GMII_TXD(s_gmii_txd),
         .GMII_RX_CLK(s_gmii_clk),
         .GMII_RX_DV(s_gmii_rx_dv),
         .GMII_RX_ER(s_gmii_rx_er),
         .GMII_RXD(s_gmii_rxd),

         .sys_clk(s_user_clk),
         .rx_tdata(loop_tdata),
         .rx_tuser(),
         .rx_tlast(loop_tlast),
         .rx_tvalid(loop_tvalid),
         .rx_tready(loop_tready),
         .tx_tdata(loop_tdata),
         .tx_tuser(),
         .tx_tlast(loop_tlast),
         .tx_tvalid(loop_tvalid),
         .tx_tready(loop_tready),

         .debug_tx(), .debug_rx()
      );


  cvita_hdr_t   header, header_out;
  cvita_stats_t stats;
  logic [63:0]  crc_cache;




  initial begin : tb_main
    `TEST_CASE_START("Wait for reset");
    while (GSR) @(posedge ETH_CLK_P);
    `TEST_CASE_DONE((~GSR));

    m_tx_chdr.push_bubble();

    `TEST_CASE_START("Wait for master channel to come up");
    while (m_channel_up !== 1'b1) @(posedge m_user_clk);
    `TEST_CASE_DONE(1'b1);

    `TEST_CASE_START("Wait for slave channel to come up");
    while (s_channel_up !== 1'b1) @(posedge s_user_clk);
    `TEST_CASE_DONE(1'b1);

















   repeat(1000) @(posedge m_user_clk);

   header = '{
      pkt_type:DATA, has_time:0, eob:0, seqnum:12'h666,
      length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0};

    `TEST_CASE_START("Fill up empty FIFO then drain (short packet)");
      s_rx_chdr.axis.tready = 0;
      m_tx_chdr.push_ramp_pkt(16, 64'd0, 64'h100, header);
      s_rx_chdr.axis.tready = 1;
      s_rx_chdr.wait_for_pkt_get_info(header_out, stats);
      `ASSERT_ERROR(stats.count==16,            "Bad packet: Length mismatch");
      `ASSERT_ERROR(header.dst_sid==header_out.dst_sid, "Bad packet: Wrong SID");
    `TEST_CASE_DONE(1);

    `TEST_CASE_START("Fill up empty FIFO then drain (long packet)");
      s_rx_chdr.axis.tready = 0;
      m_tx_chdr.push_ramp_pkt(256, 64'd0, 64'h100, header);
      s_rx_chdr.axis.tready = 1;
      s_rx_chdr.wait_for_pkt_get_info(header_out, stats);
      `ASSERT_ERROR(stats.count==256,           "Bad packet: Length mismatch");
      `ASSERT_ERROR(header.dst_sid==header_out.dst_sid, "Bad packet: Wrong SID");
    `TEST_CASE_DONE(1);

    header = '{
      pkt_type:DATA, has_time:1, eob:0, seqnum:12'h666,
      length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0};

    `TEST_CASE_START("Concurrent read and write (single packet)");
      s_rx_chdr.axis.tready = 1;
      fork
        begin
          m_tx_chdr.push_ramp_pkt(1000, 64'd0, 64'h100, header);
        end
        begin
          s_rx_chdr.wait_for_pkt_get_info(header_out, stats);
        end
      join
    crc_cache = stats.crc;
    `ASSERT_ERROR(stats.count==1000, "Bad packet: Length mismatch");
    `TEST_CASE_DONE(1);

    `TEST_CASE_START("Concurrent read and write (multiple packets)");
      s_rx_chdr.axis.tready = 1;
      fork
        begin
          repeat (20) begin
            m_tx_chdr.push_ramp_pkt(20, 64'd0, 64'h100, header);
            m_tx_chdr.push_bubble();
          end
        end
        begin
          repeat (20) begin
            s_rx_chdr.wait_for_pkt_get_info(header_out, stats);
            `ASSERT_ERROR(stats.count==20,      "Bad packet: Length mismatch");
            `ASSERT_ERROR(crc_cache==stats.crc, "Bad packet: Wrong CRC");
          end
        end
      join
    `TEST_CASE_DONE(1);

































  end

endmodule
module one_gig_eth_loopback_tb();

  `TEST_BENCH_INIT("one_gig_eth_loopback_tb",`NUM_TEST_CASES,`NS_PER_TICK)


  `DEFINE_CLK(ETH_CLK_P, 1000/125, 50)
  `DEFINE_RESET(GSR, 0, 100)

  wire ETH_CLK_N = ~ETH_CLK_P;
  wire SFP_LN0_P, SFP_LN0_N, SFP_LN1_P, SFP_LN1_N;


  localparam PORTNUM = 8'd0;












  wire gige_refclk, gige_refclk_bufg;
  wire m_user_clk, s_user_clk;
  wire m_channel_up, s_channel_up;
  wire [7:0]  m_gmii_txd, m_gmii_rxd;
  wire        m_gmii_tx_en, m_gmii_tx_er, m_gmii_rx_dv, m_gmii_rx_er;
  wire        m_gmii_clk;
  wire [7:0]  s_gmii_txd, s_gmii_rxd;
  wire        s_gmii_tx_en, s_gmii_tx_er, s_gmii_rx_dv, s_gmii_rx_er;
  wire        s_gmii_clk;
  wire [15:0] m_phy_status;
  wire [15:0] s_phy_status;
  wire [63:0] loop_tdata;
  wire        loop_tlast, loop_tvalid, loop_tready;


  reg independent_clock;
  assign m_channel_up = m_phy_status[0];
  assign s_channel_up = s_phy_status[0];


  assign m_user_clk = independent_clock;
  assign s_user_clk = independent_clock;
  wire gt0_qplloutclk, gt0_qplloutrefclk, pma_reset;

  one_gige_phy_clk_gen gige_clk_gen_i (
     .areset(GSR),
     .refclk_p(ETH_CLK_P),
     .refclk_n(ETH_CLK_N),
     .refclk(gige_refclk),
     .refclk_bufg(gige_refclk_bufg)
  );

  cvita_master m_tx_chdr (.clk(m_user_clk));
  cvita_slave s_rx_chdr (.clk(s_user_clk));
  initial
  begin
    independent_clock <= 1'b0;
    forever
    begin
      independent_clock <= 1'b0;
      #0.5;
      independent_clock <= 1'b1;
      #0.5;
    end
  end




   wire mdc, mdio_m2s, mdio_s2m;

   mdio_master #(
      .MDC_DIVIDER   (8'd200)
   ) mdio_master_i (
      .clk        (m_user_clk),
      .rst        (GSR),
      .mdc        (mdc),
      .mdio_in    (mdio_s2m),
      .mdio_out   (mdio_m2s),
      .mdio_tri   (),
      .reg_wr_req (),
      .reg_wr_addr(),
      .reg_wr_data(),
      .reg_rd_req (),
      .reg_rd_addr(),
      .reg_rd_data(),
      .reg_rd_resp()
   );


   one_gig_eth_pcs_pma_gt_common core_gt_common_i
   (
    .GTREFCLK0_IN                (gige_refclk) ,
    .QPLLLOCK_OUT                (),
    .QPLLLOCKDETCLK_IN           (independent_clock),
    .QPLLOUTCLK_OUT              (gt0_qplloutclk),
    .QPLLOUTREFCLK_OUT           (gt0_qplloutrefclk),
    .QPLLREFCLKLOST_OUT          (),
    .QPLLRESET_IN                (pma_reset)
   );

  one_gige_phy one_gige_phy_master_i
  (
     .reset(GSR),
     .independent_clock(independent_clock),
     .pma_reset_out(pma_reset),
     .gt0_qplloutclk_in(gt0_qplloutclk),
     .gt0_qplloutrefclk_in(gt0_qplloutrefclk),

     .gtrefclk(gige_refclk),
     .gtrefclk_bufg(gige_refclk_bufg),
     .txp(SFP_LN1_P),
     .txn(SFP_LN1_N),
     .rxp(SFP_LN0_P),
     .rxn(SFP_LN0_N),

     .gmii_clk(m_gmii_clk),
     .gmii_txd(m_gmii_txd),
     .gmii_tx_en(m_gmii_tx_en),
     .gmii_tx_er(m_gmii_tx_er),
     .gmii_rxd(m_gmii_rxd),
     .gmii_rx_dv(m_gmii_rx_dv),
     .gmii_rx_er(m_gmii_rx_er),

     .mdc(mdc),
     .mdio_i(mdio_m2s),
     .mdio_o(mdio_s2m),
     .mdio_t(),
     .configuration_vector(5'd0),
     .configuration_valid(1'b1),

     .status_vector(m_phy_status),
     .signal_detect(1'b1)
  );

      simple_gemac_wrapper #(.RX_FLOW_CTRL(0), .PORTNUM(PORTNUM)) simple_gemac_wrapper_master_i
      (
         .clk125(m_gmii_clk),
         .reset(GSR),

         .GMII_GTX_CLK(),
         .GMII_TX_EN(m_gmii_tx_en),
         .GMII_TX_ER(m_gmii_tx_er),
         .GMII_TXD(m_gmii_txd),
         .GMII_RX_CLK(m_gmii_clk),
         .GMII_RX_DV(m_gmii_rx_dv),
         .GMII_RX_ER(m_gmii_rx_er),
         .GMII_RXD(m_gmii_rxd),

         .sys_clk(m_user_clk),
         .rx_tdata(s_rx_chdr.axis.tdata),
         .rx_tuser(),
         .rx_tlast(s_rx_chdr.axis.tlast),
         .rx_tvalid(s_rx_chdr.axis.tvalid),
         .rx_tready(s_rx_chdr.axis.tready),
         .tx_tdata(m_tx_chdr.axis.tdata),
         .tx_tuser(),
         .tx_tlast(m_tx_chdr.axis.tlast),
         .tx_tvalid(m_tx_chdr.axis.tvalid),
         .tx_tready(m_tx_chdr.axis.tready),

         .debug_tx(), .debug_rx()
      );

  one_gige_phy one_gige_phy_slave_i
  (
     .reset(GSR),
     .independent_clock(independent_clock),
     .pma_reset_out(),
     .gt0_qplloutclk_in(gt0_qplloutclk),
     .gt0_qplloutrefclk_in(gt0_qplloutrefclk),

     .gtrefclk(gige_refclk),
     .gtrefclk_bufg(gige_refclk_bufg),
     .txp(SFP_LN0_P),
     .txn(SFP_LN0_N),
     .rxp(SFP_LN1_P),
     .rxn(SFP_LN1_N),

     .gmii_clk(s_gmii_clk),
     .gmii_txd(s_gmii_txd),
     .gmii_tx_en(s_gmii_tx_en),
     .gmii_tx_er(s_gmii_tx_er),
     .gmii_rxd(s_gmii_rxd),
     .gmii_rx_dv(s_gmii_rx_dv),
     .gmii_rx_er(s_gmii_rx_er),

     .mdc(mdc),
     .mdio_i(mdio_m2s),
     .mdio_o(mdio_s2m),
     .mdio_t(),
     .configuration_vector(5'd0),
     .configuration_valid(1'b1),

     .status_vector(s_phy_status),
     .signal_detect(1'b1)
  );

      simple_gemac_wrapper #(.RX_FLOW_CTRL(0), .PORTNUM(PORTNUM)) simple_gemac_wrapper_slave_i
      (
         .clk125(s_gmii_clk),
         .reset(GSR),

         .GMII_GTX_CLK(),
         .GMII_TX_EN(s_gmii_tx_en),
         .GMII_TX_ER(s_gmii_tx_er),
         .GMII_TXD(s_gmii_txd),
         .GMII_RX_CLK(s_gmii_clk),
         .GMII_RX_DV(s_gmii_rx_dv),
         .GMII_RX_ER(s_gmii_rx_er),
         .GMII_RXD(s_gmii_rxd),

         .sys_clk(s_user_clk),
         .rx_tdata(loop_tdata),
         .rx_tuser(),
         .rx_tlast(loop_tlast),
         .rx_tvalid(loop_tvalid),
         .rx_tready(loop_tready),
         .tx_tdata(loop_tdata),
         .tx_tuser(),
         .tx_tlast(loop_tlast),
         .tx_tvalid(loop_tvalid),
         .tx_tready(loop_tready),

         .debug_tx(), .debug_rx()
      );


  cvita_hdr_t   header, header_out;
  cvita_stats_t stats;
  logic [63:0]  crc_cache;




  initial begin : tb_main
    `TEST_CASE_START("Wait for reset");
    while (GSR) @(posedge ETH_CLK_P);
    `TEST_CASE_DONE((~GSR));

    m_tx_chdr.push_bubble();

    `TEST_CASE_START("Wait for master channel to come up");
    while (m_channel_up !== 1'b1) @(posedge m_user_clk);
    `TEST_CASE_DONE(1'b1);

    `TEST_CASE_START("Wait for slave channel to come up");
    while (s_channel_up !== 1'b1) @(posedge s_user_clk);
    `TEST_CASE_DONE(1'b1);

















   repeat(1000) @(posedge m_user_clk);

   header = '{
      pkt_type:DATA, has_time:0, eob:0, seqnum:12'h666,
      length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0};

    `TEST_CASE_START("Fill up empty FIFO then drain (short packet)");
      s_rx_chdr.axis.tready = 0;
      m_tx_chdr.push_ramp_pkt(16, 64'd0, 64'h100, header);
      s_rx_chdr.axis.tready = 1;
      s_rx_chdr.wait_for_pkt_get_info(header_out, stats);
      `ASSERT_ERROR(stats.count==16,            "Bad packet: Length mismatch");
      `ASSERT_ERROR(header.dst_sid==header_out.dst_sid, "Bad packet: Wrong SID");
    `TEST_CASE_DONE(1);

    `TEST_CASE_START("Fill up empty FIFO then drain (long packet)");
      s_rx_chdr.axis.tready = 0;
      m_tx_chdr.push_ramp_pkt(256, 64'd0, 64'h100, header);
      s_rx_chdr.axis.tready = 1;
      s_rx_chdr.wait_for_pkt_get_info(header_out, stats);
      `ASSERT_ERROR(stats.count==256,           "Bad packet: Length mismatch");
      `ASSERT_ERROR(header.dst_sid==header_out.dst_sid, "Bad packet: Wrong SID");
    `TEST_CASE_DONE(1);

    header = '{
      pkt_type:DATA, has_time:1, eob:0, seqnum:12'h666,
      length:0, src_sid:$random, dst_sid:$random, timestamp:64'h0};

    `TEST_CASE_START("Concurrent read and write (single packet)");
      s_rx_chdr.axis.tready = 1;
      fork
        begin
          m_tx_chdr.push_ramp_pkt(1000, 64'd0, 64'h100, header);
        end
        begin
          s_rx_chdr.wait_for_pkt_get_info(header_out, stats);
        end
      join
    crc_cache = stats.crc;
    `ASSERT_ERROR(stats.count==1000, "Bad packet: Length mismatch");
    `TEST_CASE_DONE(1);

    `TEST_CASE_START("Concurrent read and write (multiple packets)");
      s_rx_chdr.axis.tready = 1;
      fork
        begin
          repeat (20) begin
            m_tx_chdr.push_ramp_pkt(20, 64'd0, 64'h100, header);
            m_tx_chdr.push_bubble();
          end
        end
        begin
          repeat (20) begin
            s_rx_chdr.wait_for_pkt_get_info(header_out, stats);
            `ASSERT_ERROR(stats.count==20,      "Bad packet: Length mismatch");
            `ASSERT_ERROR(crc_cache==stats.crc, "Bad packet: Wrong CRC");
          end
        end
      join
    `TEST_CASE_DONE(1);

































  end

endmodule