data/full_repos/permissive/455421905/opencl/intelfpga/device/clocktime/clocktime.v
data/verilator_xmls/c4c2d7e7-3d98-4e0d-95d2-f1ca1bd1203f.xml
module clocktime #(
    parameter IDATA_WIDTH = 32,
    parameter TIME_WIDTH = 64,
    parameter ODATA_PADS = 0
) (
    input wire          clock,
    input wire          resetn,
    input wire          ivalid,
    input wire          iready,
    output wire         ovalid,
    output wire         oready,
    input wire [IDATA_WIDTH-1:0]   idata,
    output wire [IDATA_WIDTH + TIME_WIDTH + ODATA_PADS - 1:0] odata
);
    reg [63:0]         count;
    reg                valid;
    reg [IDATA_WIDTH-1:0]         data;

    always @(posedge clock) begin
        if (~resetn) begin
            count <= '0;
        end else begin
            count <= count + 1'd1;
        end
    end

    always @(posedge clock) begin
        if (~resetn) begin
            data <= '0;
            valid <= '0;
        end else begin
            valid <= ivalid;
            data <= idata;
        end
    end

    assign oready = 1'b1;
    assign odata = {data, count, {ODATA_PADS{1'b0}}};
    assign ovalid = valid;
endmodule
module clocktime #(
    parameter IDATA_WIDTH = 32,
    parameter TIME_WIDTH = 64,
    parameter ODATA_PADS = 0
) (
    input wire          clock,
    input wire          resetn,
    input wire          ivalid,
    input wire          iready,
    output wire         ovalid,
    output wire         oready,
    input wire [IDATA_WIDTH-1:0]   idata,
    output wire [IDATA_WIDTH + TIME_WIDTH + ODATA_PADS - 1:0] odata
);

    reg [63:0]         count;
    reg                valid;
    reg [IDATA_WIDTH-1:0]         data;

    always @(posedge clock) begin
        if (~resetn) begin
            count <= '0;
        end else begin
            count <= count + 1'd1;
        end
    end

    always @(posedge clock) begin
        if (~resetn) begin
            data <= '0;
            valid <= '0;
        end else begin
            valid <= ivalid;
            data <= idata;
        end
    end

    assign oready = 1'b1;
    assign odata = {data, count, {ODATA_PADS{1'b0}}};
    assign ovalid = valid;
endmodule