data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/float/float_cmp.v
1: b'%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/float/float_cmp.v:2: Extra underscore in meta-comment; use /*synopsys {...}*/ not /*synopsys_{...}*/\n// synopsys_ template \n^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n'
module float_cmp(g_input, e_input, o);
  parameter sig_width = 23;
  parameter exp_width = 8;
  parameter ieee_compliance = 0;

  input  [sig_width+exp_width:0] g_input;
  input  [sig_width+exp_width:0] e_input;
  output [3:0] o;


  wire aeqb_inst;
  wire altb_inst;
  wire agtb_inst;
  wire unordered_inst;

  assign o = {aeqb_inst, altb_inst, agtb_inst, unordered_inst};



  DW_fp_cmp
  #(
    sig_width,
    exp_width,
    ieee_compliance
  )
  U1
  (
    .a(g_input),
    .b(e_input),
    .zctr(1'b0),
    .aeqb(aeqb_inst),
    .altb(altb_inst),
    .agtb(agtb_inst),
    .unordered(unordered_inst),
    .z0(),
    .z1(),
    .status0(),
	  .status1()
  );

endmodule
module float_cmp(g_input, e_input, o);

  parameter sig_width = 23;
  parameter exp_width = 8;
  parameter ieee_compliance = 0;

  input  [sig_width+exp_width:0] g_input;
  input  [sig_width+exp_width:0] e_input;
  output [3:0] o;


  wire aeqb_inst;
  wire altb_inst;
  wire agtb_inst;
  wire unordered_inst;

  assign o = {aeqb_inst, altb_inst, agtb_inst, unordered_inst};



  DW_fp_cmp
  #(
    sig_width,
    exp_width,
    ieee_compliance
  )
  U1
  (
    .a(g_input),
    .b(e_input),
    .zctr(1'b0),
    .aeqb(aeqb_inst),
    .altb(altb_inst),
    .agtb(agtb_inst),
    .unordered(unordered_inst),
    .z0(),
    .z1(),
    .status0(),
	  .status1()
  );

endmodule