data/full_repos/permissive/514992586/1_Verilog_language/Modules/23_Module_shift.v
1: b"%Error: data/full_repos/permissive/514992586/1_Verilog_language/Modules/23_Module_shift.v:6: Cannot find file containing module: 'my_dff'\n    my_dff d1(.clk(clk), .d(d), .q(w1));\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514992586/1_Verilog_language/Modules,data/full_repos/permissive/514992586/my_dff\n             data/full_repos/permissive/514992586/1_Verilog_language/Modules,data/full_repos/permissive/514992586/my_dff.v\n             data/full_repos/permissive/514992586/1_Verilog_language/Modules,data/full_repos/permissive/514992586/my_dff.sv\n             my_dff\n             my_dff.v\n             my_dff.sv\n             obj_dir/my_dff\n             obj_dir/my_dff.v\n             obj_dir/my_dff.sv\n%Error: data/full_repos/permissive/514992586/1_Verilog_language/Modules/23_Module_shift.v:7: Cannot find file containing module: 'my_dff'\n    my_dff d2(.clk(clk), .d(w1), .q(w2));\n    ^~~~~~\n%Error: data/full_repos/permissive/514992586/1_Verilog_language/Modules/23_Module_shift.v:8: Cannot find file containing module: 'my_dff'\n    my_dff d3(.clk(clk), .d(w2), .q(q));\n    ^~~~~~\n%Error: Exiting due to 3 error(s)\n"
module top_module ( input clk, input d, output q );

    wire w1;
    wire w2;

    my_dff d1(.clk(clk), .d(d), .q(w1));
    my_dff d2(.clk(clk), .d(w1), .q(w2));
    my_dff d3(.clk(clk), .d(w2), .q(q));
endmodule
module top_module ( input clk, input d, output q );


    wire w1;
    wire w2;

    my_dff d1(.clk(clk), .d(d), .q(w1));
    my_dff d2(.clk(clk), .d(w1), .q(w2));
    my_dff d3(.clk(clk), .d(w2), .q(q));
endmodule