data/full_repos/permissive/441359809/src/yosys/tests/simple/realexpr.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/tests/simple/realexpr.v:15: Multiple top level modules\n                                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                            : ... Top module \'demo_001\'\nmodule demo_001(y1, y2, y3, y4);\n       ^~~~~~~~\n                                                                                            : ... Top module \'demo_002\'\nmodule demo_002(y0, y1, y2, y3);\n       ^~~~~~~~\n                                                                                            : ... Top module \'demo_004\'\nmodule demo_004(output A, B, C, D);\n       ^~~~~~~~\n%Warning-REALCVT: data/full_repos/permissive/441359809/src/yosys/tests/simple/realexpr.v:4: Implicit conversion of real to integer\n localparam [7:0] p1 = 123.45;\n                       ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/realexpr.v:27: Operator ITORD expects 32 bits on the LHS, but LHS\'s CONST \'64\'h312e303030303030\' generates 64 bits.\n                                                                                         : ... In instance demo_004.demo_real\n assign B = (p!="1.000000");\n                ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/realexpr.v:18: Operator ITORD expects 32 bits on the LHS, but LHS\'s CONST \'1\'bx\' generates 1 bits.\n                                                                                         : ... In instance demo_002\n assign y0 = 1\'bx >= (-1 * -1.17);\n             ^~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/realexpr.v:18: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS\'s GTED generates 1 bits.\n                                                                                         : ... In instance demo_002\n assign y0 = 1\'bx >= (-1 * -1.17);\n           ^\n%Warning-REALCVT: data/full_repos/permissive/441359809/src/yosys/tests/simple/realexpr.v:19: Implicit conversion of real to integer\n assign y1 = 1 ?  1 ?  -1 : \'d0 : 0.0;\n               ^\n%Warning-REALCVT: data/full_repos/permissive/441359809/src/yosys/tests/simple/realexpr.v:20: Implicit conversion of real to integer\n assign y2 = 1 ? -1 :   1 ? \'d0 : 0.0;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/realexpr.v:4: Operator VAR \'p1\' expects 8 bits on the Initial value, but Initial value\'s CONST \'32\'h7b\' generates 32 bits.\n                                                                                        : ... In instance demo_001\n localparam [7:0] p1 = 123.45;\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/realexpr.v:9: Operator ITORD expects 32 bits on the LHS, but LHS\'s VARREF \'p1\' generates 8 bits.\n                                                                                        : ... In instance demo_001\n assign y1 = p1 + 0.2;\n             ^~\n%Warning-REALCVT: data/full_repos/permissive/441359809/src/yosys/tests/simple/realexpr.v:9: Implicit conversion of real to integer\n assign y1 = p1 + 0.2;\n                ^\n%Warning-REALCVT: data/full_repos/permissive/441359809/src/yosys/tests/simple/realexpr.v:10: Implicit conversion of real to integer\n assign y2 = p2 + 0.2;\n                ^\n%Warning-REALCVT: data/full_repos/permissive/441359809/src/yosys/tests/simple/realexpr.v:11: Implicit conversion of real to integer\n assign y3 = p3 + 0.2;\n                ^\n%Warning-REALCVT: data/full_repos/permissive/441359809/src/yosys/tests/simple/realexpr.v:12: Implicit conversion of real to integer\n assign y4 = p4 + 0.2;\n                ^\n%Error: Internal Error: ../V3Number.cpp:723: toUInt with 4-state 32\'bx\n'
module demo_001(y1, y2, y3, y4);
	output [7:0] y1, y2, y3, y4;

	localparam [7:0] p1 = 123.45;
	localparam real p2 = 123.45;
	localparam real p3 = 123;
	localparam p4 = 123.45;

	assign y1 = p1 + 0.2;
	assign y2 = p2 + 0.2;
	assign y3 = p3 + 0.2;
	assign y4 = p4 + 0.2;
endmodule
module demo_001(y1, y2, y3, y4);

	output [7:0] y1, y2, y3, y4;

	localparam [7:0] p1 = 123.45;
	localparam real p2 = 123.45;
	localparam real p3 = 123;
	localparam p4 = 123.45;

	assign y1 = p1 + 0.2;
	assign y2 = p2 + 0.2;
	assign y3 = p3 + 0.2;
	assign y4 = p4 + 0.2;
endmodule