data/full_repos/permissive/504677412/src/rd_burst_sfifo.v
1: b'%Error: data/full_repos/permissive/504677412/src/rd_burst_sfifo.v:3: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/504677412/src,data/full_repos/permissive/504677412/defines.v\n             data/full_repos/permissive/504677412/src,data/full_repos/permissive/504677412/defines.v.v\n             data/full_repos/permissive/504677412/src,data/full_repos/permissive/504677412/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/504677412/src/rd_burst_sfifo.v:24: Define or directive not defined: \'`DSIZE\'\n  input  wire [`DSIZE-1:0]          wr_data;\n               ^~~~~~\n%Error: data/full_repos/permissive/504677412/src/rd_burst_sfifo.v:28: Define or directive not defined: \'`DSIZE\'\n  output wire [`DSIZE-1:0]          burst_rd_data;\n               ^~~~~~\n%Error: Exiting due to 3 error(s)\n'
module rd_burst_sfifo (

  rst,
  clk,
  afull,
  wr_en,
  wr_data,

  ds_rdy,
  burst_vld,
  burst_rd_data,
  err_bfifo_full
);
  

  input  wire                       rst;
  input  wire                       clk;
  output wire                       afull;
  input  wire                       wr_en;
  input  wire [`DSIZE-1:0]          wr_data;

  input  wire                       ds_rdy;
  output wire                       burst_vld;
  output wire [`DSIZE-1:0]          burst_rd_data;
  output reg                        err_bfifo_full;


  

  wire                              full;
  wire                              empty;

  
  fifo_fwft_36x512 i_fifo_fwft_36x512 (
    .Clk                  (clk),
    .Reset                (rst),
    .WrEn                 (wr_en),
    .Data                 (wr_data),
    .Almost_Full          (afull),
    .Full                 (full),
    .RdEn                 (ds_rdy),
    .Q                    (burst_rd_data),
    .Empty                (empty)
  );
  














  assign burst_vld = ~empty;
  

  always@(posedge clk or posedge rst) begin
    if(rst) begin
      err_bfifo_full <= 1'b0;
    end else if(full & wr_en) begin
      err_bfifo_full <= 1'b1;
      `ifdef SIM_ENABLE
        $display ("ERROR: Read Burst sFIFO full error..!");
        $stop;
      `endif
    end      
  end
  
endmodule
module rd_burst_sfifo (

  rst,
  clk,
  afull,
  wr_en,
  wr_data,

  ds_rdy,
  burst_vld,
  burst_rd_data,
  err_bfifo_full
);

  

  input  wire                       rst;
  input  wire                       clk;
  output wire                       afull;
  input  wire                       wr_en;
  input  wire [`DSIZE-1:0]          wr_data;

  input  wire                       ds_rdy;
  output wire                       burst_vld;
  output wire [`DSIZE-1:0]          burst_rd_data;
  output reg                        err_bfifo_full;


  

  wire                              full;
  wire                              empty;

  
  fifo_fwft_36x512 i_fifo_fwft_36x512 (
    .Clk                  (clk),
    .Reset                (rst),
    .WrEn                 (wr_en),
    .Data                 (wr_data),
    .Almost_Full          (afull),
    .Full                 (full),
    .RdEn                 (ds_rdy),
    .Q                    (burst_rd_data),
    .Empty                (empty)
  );
  














  assign burst_vld = ~empty;
  

  always@(posedge clk or posedge rst) begin
    if(rst) begin
      err_bfifo_full <= 1'b0;
    end else if(full & wr_en) begin
      err_bfifo_full <= 1'b1;
      `ifdef SIM_ENABLE
        $display ("ERROR: Read Burst sFIFO full error..!");
        $stop;
      `endif
    end      
  end
  
endmodule