data/full_repos/permissive/456827310/testbench/compare_tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/456827310/testbench/compare_tb.sv:24: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/456827310/testbench/compare_tb.sv:31: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/456827310/testbench/compare_tb.sv:33: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Error: data/full_repos/permissive/456827310/testbench/compare_tb.sv:39: syntax error, unexpected \'@\'\n                        @(posedge clk);\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/456827310/testbench/compare_tb.sv:40: Unsupported: Ignoring delay on this delayed statement.\n                        #2\n                        ^\n%Error: data/full_repos/permissive/456827310/testbench/compare_tb.sv:45: syntax error, unexpected \'@\'\n       @(posedge clk);\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/456827310/testbench/compare_tb.sv:48: Unsupported: Ignoring delay on this delayed statement.\n       #200 $finish;\n       ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module compare_tb;
parameter DATA_WIDTH = 8;
parameter BUFFER_DEPTH = 256;
parameter FIFO_WIDTH = 8;
parameter LINE_NUM = 3;
parameter IMAGE_WIDTH = 128;

bit clk;
bit arstn;
bit [DATA_WIDTH-1:0]data_in;
bit datain_valid;
bit mode;
wire [DATA_WIDTH*LINE_NUM-1:0]dout_align;
wire align_valid;
wire [DATA_WIDTH-1:0]data_out;
wire dout_valid;

wire [DATA_WIDTH-1:0]data_out0;
wire [DATA_WIDTH-1:0]data_out1;
wire [DATA_WIDTH-1:0]data_out2;
integer i,j;
always #5 clk = ~clk;

initial
    begin
        arstn = 1'b1;
        datain_valid = 1'b0;
        mode = 1'b0;
        #20
        arstn = 1'b0;
        #20
        arstn = 1'b1;
        for(i=1;i<7;i=i+1)
            begin
                for(j=1;j<129;j=j+1)
                    begin
                        @(posedge clk);
                        #2
                            data_in = j;
                            datain_valid = 1'b1;
                    end
            end
       @(posedge clk);

       datain_valid = 1'b0;
       #200 $finish;
    end


assign data_out0[DATA_WIDTH-1:0] = dout_align[DATA_WIDTH-1:0];
assign data_out1[DATA_WIDTH-1:0] = dout_align[2*DATA_WIDTH-1:DATA_WIDTH];
assign data_out2[DATA_WIDTH-1:0] = dout_align[3*DATA_WIDTH-1:2*DATA_WIDTH];
LineAlign #(
    .DATA_WIDTH(DATA_WIDTH),
    .BUFFER_DEPTH(BUFFER_DEPTH),
    .FIFO_WIDTH(FIFO_WIDTH),
    .LINE_NUM(LINE_NUM),
    .IMAGE_WIDTH(IMAGE_WIDTH)
)Inst_LineAlign(
    .clk(clk),
    .arstn(arstn),
    .data_in(data_in),
    .datain_valid(datain_valid),
    .data_out(dout_align),
    .dataout_valid(align_valid));
    













Compare3x3 #(
    .LINE_NUM(LINE_NUM),
    .PIXEL_WIDTH(DATA_WIDTH),
    .KX_WIDTH(LINE_NUM),
    .IMAGE_WIDTH(IMAGE_WIDTH)
)Inst_compare(
    .clk(clk),
    .arstn(arstn),
    .data_in(dout_align),
    .din_valid(align_valid),
    .data_out(data_out),
    .dout_valid(dout_valid),
    .mode(mode));

wire dout_valid_cap;
wire [DATA_WIDTH-1:0]dout_data_cap;

AverageCapture #(
    .PIXEL_WIDTH(DATA_WIDTH)
)Inst_AverageCapture(
    .clk(clk),
    .arstn(arstn),
    .din_data(data_out),
    .din_valid(dout_valid),
    .dout_valid(dout_valid_cap),
    .dout_data(dout_data_cap));

endmodule
module compare_tb;

parameter DATA_WIDTH = 8;
parameter BUFFER_DEPTH = 256;
parameter FIFO_WIDTH = 8;
parameter LINE_NUM = 3;
parameter IMAGE_WIDTH = 128;

bit clk;
bit arstn;
bit [DATA_WIDTH-1:0]data_in;
bit datain_valid;
bit mode;
wire [DATA_WIDTH*LINE_NUM-1:0]dout_align;
wire align_valid;
wire [DATA_WIDTH-1:0]data_out;
wire dout_valid;

wire [DATA_WIDTH-1:0]data_out0;
wire [DATA_WIDTH-1:0]data_out1;
wire [DATA_WIDTH-1:0]data_out2;
integer i,j;
always #5 clk = ~clk;

initial
    begin
        arstn = 1'b1;
        datain_valid = 1'b0;
        mode = 1'b0;
        #20
        arstn = 1'b0;
        #20
        arstn = 1'b1;
        for(i=1;i<7;i=i+1)
            begin
                for(j=1;j<129;j=j+1)
                    begin
                        @(posedge clk);
                        #2
                            data_in = j;
                            datain_valid = 1'b1;
                    end
            end
       @(posedge clk);

       datain_valid = 1'b0;
       #200 $finish;
    end


assign data_out0[DATA_WIDTH-1:0] = dout_align[DATA_WIDTH-1:0];
assign data_out1[DATA_WIDTH-1:0] = dout_align[2*DATA_WIDTH-1:DATA_WIDTH];
assign data_out2[DATA_WIDTH-1:0] = dout_align[3*DATA_WIDTH-1:2*DATA_WIDTH];
LineAlign #(
    .DATA_WIDTH(DATA_WIDTH),
    .BUFFER_DEPTH(BUFFER_DEPTH),
    .FIFO_WIDTH(FIFO_WIDTH),
    .LINE_NUM(LINE_NUM),
    .IMAGE_WIDTH(IMAGE_WIDTH)
)Inst_LineAlign(
    .clk(clk),
    .arstn(arstn),
    .data_in(data_in),
    .datain_valid(datain_valid),
    .data_out(dout_align),
    .dataout_valid(align_valid));
    













Compare3x3 #(
    .LINE_NUM(LINE_NUM),
    .PIXEL_WIDTH(DATA_WIDTH),
    .KX_WIDTH(LINE_NUM),
    .IMAGE_WIDTH(IMAGE_WIDTH)
)Inst_compare(
    .clk(clk),
    .arstn(arstn),
    .data_in(dout_align),
    .din_valid(align_valid),
    .data_out(data_out),
    .dout_valid(dout_valid),
    .mode(mode));

wire dout_valid_cap;
wire [DATA_WIDTH-1:0]dout_data_cap;

AverageCapture #(
    .PIXEL_WIDTH(DATA_WIDTH)
)Inst_AverageCapture(
    .clk(clk),
    .arstn(arstn),
    .din_data(data_out),
    .din_valid(dout_valid),
    .dout_valid(dout_valid_cap),
    .dout_data(dout_data_cap));

endmodule