data/full_repos/permissive/503053625/resources/verilog_source/ADC_shift_reg.v
data/verilator_xmls/11b5ab30-e7fc-4590-9fd7-fb3221b38b85.xml
module ADC_shift_reg
#(
	parameter ADC_WIDTH = 12
)
(
	input ADC_clk,
	input [ADC_WIDTH - 1:0] data_in,
	output [ADC_WIDTH - 1:0] data_out
);
	reg [ADC_WIDTH - 1:0] int_data_reg = {ADC_WIDTH{1'b0}};
	assign data_out = int_data_reg;
	always @(posedge ADC_clk)
	begin
		int_data_reg = data_in;
	end
endmodule
module ADC_shift_reg
#(
	parameter ADC_WIDTH = 12
)
(
	input ADC_clk,
	input [ADC_WIDTH - 1:0] data_in,
	output [ADC_WIDTH - 1:0] data_out
);

	reg [ADC_WIDTH - 1:0] int_data_reg = {ADC_WIDTH{1'b0}};
	assign data_out = int_data_reg;
	always @(posedge ADC_clk)
	begin
		int_data_reg = data_in;
	end
endmodule