data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v
1: b'%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:89: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_A_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_A: next_state = go ? S_LOAD_A_WAIT : S_LOAD_A;  \n                                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:89: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'S_LOAD_A\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_A: next_state = go ? S_LOAD_A_WAIT : S_LOAD_A;  \n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:90: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_A_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_A_WAIT: next_state = go ? S_LOAD_A_WAIT : S_LOAD_B;  \n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:90: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'S_LOAD_B\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_A_WAIT: next_state = go ? S_LOAD_A_WAIT : S_LOAD_B;  \n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:91: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_B_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_B: next_state = go ? S_LOAD_B_WAIT : S_LOAD_B;  \n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:91: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'S_LOAD_B\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_B: next_state = go ? S_LOAD_B_WAIT : S_LOAD_B;  \n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:92: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_B_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_B_WAIT: next_state = go ? S_LOAD_B_WAIT : S_LOAD_C;  \n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:92: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'S_LOAD_C\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_B_WAIT: next_state = go ? S_LOAD_B_WAIT : S_LOAD_C;  \n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:93: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_C_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_C: next_state = go ? S_LOAD_C_WAIT : S_LOAD_C;  \n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:93: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'S_LOAD_C\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_C: next_state = go ? S_LOAD_C_WAIT : S_LOAD_C;  \n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:94: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_C_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_C_WAIT: next_state = go ? S_LOAD_C_WAIT : S_LOAD_X;  \n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:94: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'S_LOAD_X\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_C_WAIT: next_state = go ? S_LOAD_C_WAIT : S_LOAD_X;  \n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:95: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_X_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_X: next_state = go ? S_LOAD_X_WAIT : S_LOAD_X;  \n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:95: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'S_LOAD_X\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_X: next_state = go ? S_LOAD_X_WAIT : S_LOAD_X;  \n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:96: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'S_LOAD_X_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_X_WAIT: next_state = go ? S_LOAD_X_WAIT : S_CYCLE_0;  \n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:96: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'S_CYCLE_0\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_LOAD_X_WAIT: next_state = go ? S_LOAD_X_WAIT : S_CYCLE_0;  \n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:97: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_CYCLE_1\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_CYCLE_0: next_state = S_CYCLE_1;\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:98: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_CYCLE_2\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n                S_CYCLE_1: next_state = S_CYCLE_2;  \n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:99: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_CYCLE_3\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n      S_CYCLE_2: next_state = S_CYCLE_3;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:100: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_LOAD_A\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n      S_CYCLE_3: next_state = S_LOAD_A;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:101: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_LOAD_A\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n            default:     next_state = S_LOAD_A;\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_A\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_A_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_B\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_B_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_C\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_C_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_X\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_X_WAIT\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_CYCLE_0\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_CYCLE_1\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_CYCLE_2\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:88: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_CYCLE_3\' generates 5 bits.\n                                                                                  : ... In instance part2.C0\n            case (current_state)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:120: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_A\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n        case (current_state)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:120: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_B\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n        case (current_state)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:120: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_C\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n        case (current_state)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:120: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_LOAD_X\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n        case (current_state)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:120: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_CYCLE_0\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n        case (current_state)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:120: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_CYCLE_1\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n        case (current_state)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:120: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_CYCLE_2\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n        case (current_state)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:120: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'S_CYCLE_3\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n        case (current_state)\n        ^~~~\n%Warning-WIDTH: data/full_repos/permissive/433640910/PolynomialFSM/polynomial.v:168: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'S_LOAD_A\' generates 5 bits.\n                                                                                   : ... In instance part2.C0\n            current_state <= S_LOAD_A;\n                          ^~\n%Error: Exiting due to 42 warning(s)\n'
module control(
    input clk,
    input resetn,
    input go,

    output reg  ld_a, ld_b, ld_c, ld_x, ld_r,
    output reg  ld_alu_out,
    output reg [1:0]  alu_select_a, alu_select_b,
    output reg alu_op
    );

    reg [5:0] current_state, next_state; 
    
    localparam  S_LOAD_A        = 5'd0,
                S_LOAD_A_WAIT   = 5'd1,
                S_LOAD_B        = 5'd2,
                S_LOAD_B_WAIT   = 5'd3,
                S_LOAD_C        = 5'd4,
                S_LOAD_C_WAIT   = 5'd5,
                S_LOAD_X        = 5'd6,
                S_LOAD_X_WAIT   = 5'd7,
                S_CYCLE_0       = 5'd8,
                S_CYCLE_1       = 5'd9,
                S_CYCLE_2       = 5'd10,
					 S_CYCLE_3       = 5'd11;
    

    always@(*)
    begin: state_table 
            case (current_state)
                S_LOAD_A: next_state = go ? S_LOAD_A_WAIT : S_LOAD_A;
                S_LOAD_A_WAIT: next_state = go ? S_LOAD_A_WAIT : S_LOAD_B;
                S_LOAD_B: next_state = go ? S_LOAD_B_WAIT : S_LOAD_B;
                S_LOAD_B_WAIT: next_state = go ? S_LOAD_B_WAIT : S_LOAD_C;
                S_LOAD_C: next_state = go ? S_LOAD_C_WAIT : S_LOAD_C;
                S_LOAD_C_WAIT: next_state = go ? S_LOAD_C_WAIT : S_LOAD_X;
                S_LOAD_X: next_state = go ? S_LOAD_X_WAIT : S_LOAD_X;
                S_LOAD_X_WAIT: next_state = go ? S_LOAD_X_WAIT : S_CYCLE_0;
                S_CYCLE_0: next_state = S_CYCLE_1;
                S_CYCLE_1: next_state = S_CYCLE_2;
					 S_CYCLE_2: next_state = S_CYCLE_3;
					 S_CYCLE_3: next_state = S_LOAD_A;
            default:     next_state = S_LOAD_A;
        endcase
    end
   


    always @(*)
    begin: enable_signals

        ld_alu_out = 1'b0;
        ld_a = 1'b0;
        ld_b = 1'b0;
        ld_c = 1'b0;
        ld_x = 1'b0;
        ld_r = 1'b0;
        alu_select_a = 2'b0;
        alu_select_b = 2'b0;
        alu_op       = 1'b0;

        case (current_state)
            S_LOAD_A: begin
                ld_a = 1'b1;
                end
            S_LOAD_B: begin
                ld_b = 1'b1;
                end
            S_LOAD_C: begin
                ld_c = 1'b1;
                end
            S_LOAD_X: begin
                ld_x = 1'b1;
                end
            S_CYCLE_0: begin
                ld_alu_out = 1'b1; ld_a = 1'b1;
                alu_select_a = 2'b00;
                alu_select_b = 2'b11;
                alu_op = 1'b1;
            end
            S_CYCLE_1: begin
                ld_r = 1'b1;
					 ld_alu_out = 1'b1; ld_a = 1'b1;
                alu_select_a = 2'b00;
                alu_select_b = 2'b01;
                alu_op = 1'b0;
            end
				S_CYCLE_2: begin
                ld_r = 1'b1;
					 ld_alu_out = 1'b1; ld_a = 1'b1;
                alu_select_a = 2'b00;
                alu_select_b = 2'b11;
                alu_op = 1'b1;
            end
				S_CYCLE_3: begin
                ld_r = 1'b1;
					 ld_alu_out = 1'b1; ld_a = 1'b1;
                alu_select_a = 2'b00;
                alu_select_b = 2'b10;
                alu_op = 1'b0;
            end

        endcase
    end
   

    always@(posedge clk)
    begin: state_FFs
        if(!resetn)
            current_state <= S_LOAD_A;
        else
            current_state <= next_state;
    end
endmodule
module control(
    input clk,
    input resetn,
    input go,

    output reg  ld_a, ld_b, ld_c, ld_x, ld_r,
    output reg  ld_alu_out,
    output reg [1:0]  alu_select_a, alu_select_b,
    output reg alu_op
    );


    reg [5:0] current_state, next_state; 
    
    localparam  S_LOAD_A        = 5'd0,
                S_LOAD_A_WAIT   = 5'd1,
                S_LOAD_B        = 5'd2,
                S_LOAD_B_WAIT   = 5'd3,
                S_LOAD_C        = 5'd4,
                S_LOAD_C_WAIT   = 5'd5,
                S_LOAD_X        = 5'd6,
                S_LOAD_X_WAIT   = 5'd7,
                S_CYCLE_0       = 5'd8,
                S_CYCLE_1       = 5'd9,
                S_CYCLE_2       = 5'd10,
					 S_CYCLE_3       = 5'd11;
    

    always@(*)
    begin: state_table 
            case (current_state)
                S_LOAD_A: next_state = go ? S_LOAD_A_WAIT : S_LOAD_A;
                S_LOAD_A_WAIT: next_state = go ? S_LOAD_A_WAIT : S_LOAD_B;
                S_LOAD_B: next_state = go ? S_LOAD_B_WAIT : S_LOAD_B;
                S_LOAD_B_WAIT: next_state = go ? S_LOAD_B_WAIT : S_LOAD_C;
                S_LOAD_C: next_state = go ? S_LOAD_C_WAIT : S_LOAD_C;
                S_LOAD_C_WAIT: next_state = go ? S_LOAD_C_WAIT : S_LOAD_X;
                S_LOAD_X: next_state = go ? S_LOAD_X_WAIT : S_LOAD_X;
                S_LOAD_X_WAIT: next_state = go ? S_LOAD_X_WAIT : S_CYCLE_0;
                S_CYCLE_0: next_state = S_CYCLE_1;
                S_CYCLE_1: next_state = S_CYCLE_2;
					 S_CYCLE_2: next_state = S_CYCLE_3;
					 S_CYCLE_3: next_state = S_LOAD_A;
            default:     next_state = S_LOAD_A;
        endcase
    end
   


    always @(*)
    begin: enable_signals

        ld_alu_out = 1'b0;
        ld_a = 1'b0;
        ld_b = 1'b0;
        ld_c = 1'b0;
        ld_x = 1'b0;
        ld_r = 1'b0;
        alu_select_a = 2'b0;
        alu_select_b = 2'b0;
        alu_op       = 1'b0;

        case (current_state)
            S_LOAD_A: begin
                ld_a = 1'b1;
                end
            S_LOAD_B: begin
                ld_b = 1'b1;
                end
            S_LOAD_C: begin
                ld_c = 1'b1;
                end
            S_LOAD_X: begin
                ld_x = 1'b1;
                end
            S_CYCLE_0: begin
                ld_alu_out = 1'b1; ld_a = 1'b1;
                alu_select_a = 2'b00;
                alu_select_b = 2'b11;
                alu_op = 1'b1;
            end
            S_CYCLE_1: begin
                ld_r = 1'b1;
					 ld_alu_out = 1'b1; ld_a = 1'b1;
                alu_select_a = 2'b00;
                alu_select_b = 2'b01;
                alu_op = 1'b0;
            end
				S_CYCLE_2: begin
                ld_r = 1'b1;
					 ld_alu_out = 1'b1; ld_a = 1'b1;
                alu_select_a = 2'b00;
                alu_select_b = 2'b11;
                alu_op = 1'b1;
            end
				S_CYCLE_3: begin
                ld_r = 1'b1;
					 ld_alu_out = 1'b1; ld_a = 1'b1;
                alu_select_a = 2'b00;
                alu_select_b = 2'b10;
                alu_op = 1'b0;
            end

        endcase
    end
   

    always@(posedge clk)
    begin: state_FFs
        if(!resetn)
            current_state <= S_LOAD_A;
        else
            current_state <= next_state;
    end
endmodule