data/full_repos/permissive/427885334/rtl/misc/reset_generator.v
data/verilator_xmls/518cc796-b10d-4120-a770-65d363c326b1.xml
module reset_generator(
  clk,
  clk_en,
  async_nrst_i,
  rst_o
);


parameter active_state = 1'b0;
parameter rst_length = 2;

input  clk;
input  clk_en;
input  async_nrst_i;
output reg rst_o = active_state;

integer int_idx;
reg  rst_pl [0:rst_length-2];
initial begin
  for (int_idx = 0; int_idx < rst_length-1; int_idx = int_idx + 1)
    rst_pl[int_idx] <= active_state;
end

always @(posedge clk or negedge async_nrst_i) begin
  if (!async_nrst_i) begin
    rst_o <= active_state;
    for (int_idx = 0; int_idx < rst_length-1; int_idx = int_idx + 1)
      rst_pl[int_idx] <= active_state;
  end else if (clk_en) begin
    rst_o <= rst_pl[rst_length-2];
    for (int_idx = 1; int_idx < rst_length-1; int_idx = int_idx + 1)
      rst_pl[int_idx] <= rst_pl[int_idx-1];
    rst_pl[0] <= ~active_state;
  end
end

endmodule
module reset_generator(
  clk,
  clk_en,
  async_nrst_i,
  rst_o
);



parameter active_state = 1'b0;
parameter rst_length = 2;

input  clk;
input  clk_en;
input  async_nrst_i;
output reg rst_o = active_state;

integer int_idx;
reg  rst_pl [0:rst_length-2];
initial begin
  for (int_idx = 0; int_idx < rst_length-1; int_idx = int_idx + 1)
    rst_pl[int_idx] <= active_state;
end

always @(posedge clk or negedge async_nrst_i) begin
  if (!async_nrst_i) begin
    rst_o <= active_state;
    for (int_idx = 0; int_idx < rst_length-1; int_idx = int_idx + 1)
      rst_pl[int_idx] <= active_state;
  end else if (clk_en) begin
    rst_o <= rst_pl[rst_length-2];
    for (int_idx = 1; int_idx < rst_length-1; int_idx = int_idx + 1)
      rst_pl[int_idx] <= rst_pl[int_idx-1];
    rst_pl[0] <= ~active_state;
  end
end

endmodule