data/full_repos/permissive/489075769/write_response_ms.v
1: b'%Warning-WIDTH: data/full_repos/permissive/489075769/write_response_ms.v:56: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                           : ... In instance write_response_ms.resp_s\no_BRESP <= 1\'b0;\n        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module write_response_ms(ACLK,ARESETn,BREADY, BVALID, i_BRESP, o_BRESP);
input ACLK, ARESETn;
input BVALID, BREADY;
input [1:0] i_BRESP;
output [1:0] o_BRESP;

wire o_BVALID, o_BREADY;
wire [1:0] w_BRESP;

write_response_slave resp_s(ACLK, ARESETn, BVALID, o_BVALID, o_BREADY, i_BRESP, w_BRESP);
write_response_master resp_m(ACLK,ARESETn, o_BVALID, BREADY, o_BREADY, w_BRESP, o_BRESP);

endmodule
module write_response_ms(ACLK,ARESETn,BREADY, BVALID, i_BRESP, o_BRESP);

input ACLK, ARESETn;
input BVALID, BREADY;
input [1:0] i_BRESP;
output [1:0] o_BRESP;

wire o_BVALID, o_BREADY;
wire [1:0] w_BRESP;

write_response_slave resp_s(ACLK, ARESETn, BVALID, o_BVALID, o_BREADY, i_BRESP, w_BRESP);
write_response_master resp_m(ACLK,ARESETn, o_BVALID, BREADY, o_BREADY, w_BRESP, o_BRESP);

endmodule