data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/dir36to8.v
1: b'%Warning-WIDTH: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/dir36to8.v:24: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s COND generates 32 or 7 bits.\n                                                                                               : ... In instance dir36to8\n  assign dir_c=(dir_tmp>0)?(dir_tmp):dir_tmp+36;\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module dir36to8(
		input [5:0] dir_in,
		input [5:0] dir_main,
		output reg [2:0] dir_out
    );
	 
	 wire signed [6:0] dir_tmp;
	 wire [5:0] dir_c;
	 
	 assign dir_tmp=dir_in-dir_main;
	 assign dir_c=(dir_tmp>0)?(dir_tmp):dir_tmp+36;
	 
	 always@(dir_c)
	 begin
		case(dir_c)
		0:dir_out<=0;
		1:dir_out<=0;
		2:dir_out<=0;
		3:dir_out<=1;
		4:dir_out<=1;
		5:dir_out<=1;
		6:dir_out<=1;
		7:dir_out<=2;
		8:dir_out<=2;
		9:dir_out<=2;
		10:dir_out<=2;
		11:dir_out<=2;
		12:dir_out<=3;
		13:dir_out<=3;
		14:dir_out<=3;
		15:dir_out<=3;
		16:dir_out<=4;
		17:dir_out<=4;
		18:dir_out<=4;
		19:dir_out<=4;
		20:dir_out<=4;
		21:dir_out<=5;
		22:dir_out<=5;
		23:dir_out<=5;
		24:dir_out<=5;
		25:dir_out<=6;
		26:dir_out<=6;
		27:dir_out<=6;
		28:dir_out<=6;
		29:dir_out<=6;
		30:dir_out<=7;
		31:dir_out<=7;
		32:dir_out<=7;
		33:dir_out<=7;
		34:dir_out<=0;
		35:dir_out<=0;
		default:dir_out<=3'bzzz;
		endcase
	 end


endmodule
module dir36to8(
		input [5:0] dir_in,
		input [5:0] dir_main,
		output reg [2:0] dir_out
    );

	 
	 wire signed [6:0] dir_tmp;
	 wire [5:0] dir_c;
	 
	 assign dir_tmp=dir_in-dir_main;
	 assign dir_c=(dir_tmp>0)?(dir_tmp):dir_tmp+36;
	 
	 always@(dir_c)
	 begin
		case(dir_c)
		0:dir_out<=0;
		1:dir_out<=0;
		2:dir_out<=0;
		3:dir_out<=1;
		4:dir_out<=1;
		5:dir_out<=1;
		6:dir_out<=1;
		7:dir_out<=2;
		8:dir_out<=2;
		9:dir_out<=2;
		10:dir_out<=2;
		11:dir_out<=2;
		12:dir_out<=3;
		13:dir_out<=3;
		14:dir_out<=3;
		15:dir_out<=3;
		16:dir_out<=4;
		17:dir_out<=4;
		18:dir_out<=4;
		19:dir_out<=4;
		20:dir_out<=4;
		21:dir_out<=5;
		22:dir_out<=5;
		23:dir_out<=5;
		24:dir_out<=5;
		25:dir_out<=6;
		26:dir_out<=6;
		27:dir_out<=6;
		28:dir_out<=6;
		29:dir_out<=6;
		30:dir_out<=7;
		31:dir_out<=7;
		32:dir_out<=7;
		33:dir_out<=7;
		34:dir_out<=0;
		35:dir_out<=0;
		default:dir_out<=3'bzzz;
		endcase
	 end


endmodule