data/full_repos/permissive/418753087/smart_run/logical/common/clk_aligner.v
1: b'%Warning-WIDTH: data/full_repos/permissive/418753087/smart_run/logical/common/clk_aligner.v:147: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s SEL generates 12 bits.\n                                                                                               : ... In instance clk_aligner\n    if (!paddr[11:0] )\n        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/418753087/smart_run/logical/common/clk_aligner.v:152: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s SEL generates 12 bits.\n                                                                                               : ... In instance clk_aligner\nassign clkratio_chg_en = psel && pwrite && penable && !paddr[11:0] \n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/418753087/smart_run/logical/common/clk_aligner.v:163: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s SEL generates 12 bits.\n                                                                                               : ... In instance clk_aligner\n  if(!paddr[11:0] )\n     ^\n%Error: data/full_repos/permissive/418753087/smart_run/logical/common/clk_aligner.v:452: Cannot find file containing module: \'soc_gated_clk_cell\'\nsoc_gated_clk_cell  x_soc_gated_cpuclk_cell (\n^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418753087/smart_run/logical/common,data/full_repos/permissive/418753087/soc_gated_clk_cell\n             data/full_repos/permissive/418753087/smart_run/logical/common,data/full_repos/permissive/418753087/soc_gated_clk_cell.v\n             data/full_repos/permissive/418753087/smart_run/logical/common,data/full_repos/permissive/418753087/soc_gated_clk_cell.sv\n             soc_gated_clk_cell\n             soc_gated_clk_cell.v\n             soc_gated_clk_cell.sv\n             obj_dir/soc_gated_clk_cell\n             obj_dir/soc_gated_clk_cell.v\n             obj_dir/soc_gated_clk_cell.sv\n%Error: data/full_repos/permissive/418753087/smart_run/logical/common/clk_aligner.v:468: Cannot find file containing module: \'soc_gated_clk_cell\'\nsoc_gated_clk_cell  x_soc_gated_sysclk_cell (\n^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module clk_aligner(
  clk_div_1,
  clk_div_2,
  clk_div_3,
  clk_div_4,
  clk_div_5,
  clk_div_6,
  clk_div_7,
  clk_div_8,
  clk_en,
  clk_en_1,
  clk_en_2,
  clk_en_3,
  clk_en_4,
  clk_en_5,
  clk_en_6,
  clk_en_7,
  clk_en_8,
  clkrst_b,
  cpu_clk,
  forever_cpuclk,
  gate_en0,
  gate_en1,
  paddr,
  penable,
  per_clk,
  pmu_clk,
  prdata,
  psel,
  pwdata,
  pwrite,
  wic_clk
);


input           clk_div_1;      
input           clk_div_2;      
input           clk_div_3;      
input           clk_div_4;      
input           clk_div_5;      
input           clk_div_6;      
input           clk_div_7;      
input           clk_div_8;      
input           clk_en_1;       
input           clk_en_2;       
input           clk_en_3;       
input           clk_en_4;       
input           clk_en_5;       
input           clk_en_6;       
input           clk_en_7;       
input           clk_en_8;       
input           clkrst_b;       
input           forever_cpuclk; 
input           gate_en0;       
input           gate_en1;       
input   [11:0]  paddr;          
input           penable;        
input           psel;           
input   [2 :0]  pwdata;         
input           pwrite;         
output          clk_en;         
output          cpu_clk;        
output          per_clk;        
output          pmu_clk;        
output  [31:0]  prdata;         
output          wic_clk;        


reg             clk_en;         
reg             gen_clk_en;     
reg     [2 :0]  input_clkratio; 
reg     [31:0]  prdata;         
reg             pre_clk_en;     
reg             pre_sysclk;     
reg             save_clk_en;    
reg     [2 :0]  save_clkratio;  
reg             save_sysclk;    
reg     [1 :0]  state_c;        
reg     [1 :0]  state_n;        
reg             sysclk;         


wire            clk_div_1;      
wire            clk_div_2;      
wire            clk_div_3;      
wire            clk_div_4;      
wire            clk_div_5;      
wire            clk_div_6;      
wire            clk_div_7;      
wire            clk_div_8;      
wire            clk_en_1;       
wire            clk_en_2;       
wire            clk_en_3;       
wire            clk_en_4;       
wire            clk_en_5;       
wire            clk_en_6;       
wire            clk_en_7;       
wire            clk_en_8;       
wire            clkratio_chg_en; 
wire            clkrst_b;       
wire            cpu_clk;        
wire            forever_cpuclk; 
wire            gate_en0;       
wire            gate_en1;       
wire    [11:0]  paddr;          
wire            penable;        
wire            per_clk;        
wire            pmu_clk;        
wire    [2 :0]  pre_clkratio;   
wire            psel;           
wire    [2 :0]  pwdata;         
wire            pwrite;         
wire            wic_clk;        


parameter IDLE = 2'b00,WAIT_PRE_EN = 2'b01,WAIT_NEXT_EN = 2'b10,MASK_SYSCLK = 2'b11;








always@(posedge per_clk or negedge clkrst_b)
begin
  if (!clkrst_b)
    input_clkratio[2:0] <= 3'b0;
  else if(psel && pwrite && penable)
  begin
    if (!paddr[11:0] )
      input_clkratio[2:0] <= pwdata[2:0];
  end
end

assign clkratio_chg_en = psel && pwrite && penable && !paddr[11:0] 
                      && !(pre_clkratio[2:0] ==pwdata[2:0]);


always @( input_clkratio[2:0]
       or paddr[11:0]
       or psel
       or pwrite)
begin
if(psel && !pwrite)
begin
  if(!paddr[11:0] )
    prdata[31:0] = {29'b0, input_clkratio[2:0]};
  else 
    prdata[31:0] = 32'b0;
end

end

   


always@(posedge forever_cpuclk or negedge clkrst_b)

begin
  if(!clkrst_b)
    state_c[1:0] <= IDLE;
  else
    state_c[1:0] <= state_n[1:0];
end


always @( clkratio_chg_en
       or state_c[1:0]
       or save_clk_en
       or pre_clk_en)
begin
  case(state_c[1:0])
  IDLE:
  begin
    if (clkratio_chg_en)
      state_n[1:0] = WAIT_PRE_EN;
    else
      state_n[1:0] = IDLE;
  end
  WAIT_PRE_EN:
  begin
    if (save_clk_en)
      state_n[1:0] = WAIT_NEXT_EN;
    else
      state_n[1:0] = WAIT_PRE_EN;
  end
  WAIT_NEXT_EN:
  begin

    if(pre_clk_en)
      state_n[1:0] = MASK_SYSCLK;

    else
      state_n[1:0] = WAIT_NEXT_EN;
  end
  MASK_SYSCLK:
  begin
    if(pre_clk_en)
      state_n[1:0] = IDLE;
    else
      state_n[1:0] = MASK_SYSCLK;
  end
  default:
  begin
    state_n[1:0] = IDLE;
  end
  endcase

end




always @( save_sysclk
       or pre_sysclk
       or state_c[1:0]
       or pre_clk_en)
begin
case(state_c[1:0])
  IDLE:
  begin
    gen_clk_en = pre_clk_en;
    sysclk = pre_sysclk;

  end
  WAIT_PRE_EN:
  begin


    gen_clk_en = 0;
    sysclk = save_sysclk;

  end
  WAIT_NEXT_EN:
  begin
    gen_clk_en = 0;
    sysclk = 0;

  end
  MASK_SYSCLK:
  begin
    gen_clk_en = pre_clk_en;
    sysclk = 0;

  end
  default:
  begin
    gen_clk_en = pre_clk_en;
    sysclk = pre_sysclk;

  end
endcase

end





assign pre_clkratio[2:0] = input_clkratio[2:0];


always @(posedge forever_cpuclk or negedge clkrst_b)
begin
  if(!clkrst_b)
    save_clkratio[2:0] <= 3'b0;
  else if(clkratio_chg_en)
    save_clkratio[2:0] <= pre_clkratio[2:0];
end



always @( clk_div_2
       or clk_en_7
       or clk_div_7
       or clk_div_4
       or clk_div_5
       or clk_en_5
       or clk_div_6
       or pre_clkratio[2:0]
       or clk_div_8
       or clk_div_1
       or clk_en_3
       or clk_en_8
       or clk_en_2
       or clk_en_4
       or clk_div_3
       or clk_en_6
       or clk_en_1)
begin
  case (pre_clkratio[2:0])
  3'b000:
  begin 
    pre_clk_en = clk_en_1;
    pre_sysclk = clk_div_1;
  end
  3'b001: 
  begin 
    pre_clk_en = clk_en_2;
    pre_sysclk = clk_div_2;
  end
  3'b010:
  begin 
    pre_clk_en = clk_en_3;
    pre_sysclk = clk_div_3;
  end
  3'b011: 
  begin 
    pre_clk_en = clk_en_4;
    pre_sysclk = clk_div_4;
  end
  3'b100: 
  begin 
    pre_clk_en = clk_en_5;
    pre_sysclk = clk_div_5;
  end
  3'b101: 
  begin 
    pre_clk_en = clk_en_6;
    pre_sysclk = clk_div_6;
  end
  3'b110: 
  begin 
    pre_clk_en = clk_en_7;
    pre_sysclk = clk_div_7;
  end
  3'b111: 
  begin 
    pre_clk_en = clk_en_8;
    pre_sysclk = clk_div_8;
  end
  default:
  begin 
    pre_clk_en = clk_en_1;
    pre_sysclk = clk_div_1;
  end
  endcase

end


always @( clk_div_2
       or clk_en_7
       or clk_div_7
       or clk_div_4
       or clk_en_5
       or clk_div_5
       or clk_div_6
       or clk_div_8
       or clk_en_3
       or clk_div_1
       or clk_en_8
       or save_clkratio[2:0]
       or clk_en_2
       or clk_en_4
       or clk_en_6
       or clk_div_3
       or clk_en_1)
begin
  case (save_clkratio[2:0])
  3'b000:
  begin 
    save_clk_en = clk_en_1;
    save_sysclk = clk_div_1;
  end
  3'b001: 
  begin 
    save_clk_en = clk_en_2;
    save_sysclk = clk_div_2;
  end
  3'b010:
  begin 
    save_clk_en = clk_en_3;
    save_sysclk = clk_div_3;
  end
  3'b011: 
  begin 
    save_clk_en = clk_en_4;
    save_sysclk = clk_div_4;
  end
  3'b100: 
  begin 
    save_clk_en = clk_en_5;
    save_sysclk = clk_div_5;
  end
  3'b101: 
  begin 
    save_clk_en = clk_en_6;
    save_sysclk = clk_div_6;
  end
  3'b110: 
  begin 
    save_clk_en = clk_en_7;
    save_sysclk = clk_div_7;
  end
  3'b111: 
  begin 
    save_clk_en = clk_en_8;
    save_sysclk = clk_div_8;
  end
  default:
  begin 
    save_clk_en = clk_en_1;
    save_sysclk = clk_div_1;
  end
  endcase

end











always @( gen_clk_en)
begin
  case(1'b1)
    1'b1: clk_en <= gen_clk_en;
    1'b0: clk_en <= 1'b0;
  endcase

end


assign wic_clk = forever_cpuclk;
assign pmu_clk = sysclk;



soc_gated_clk_cell  x_soc_gated_cpuclk_cell (
  .SE             (1'b0          ),
  .clk_in         (forever_cpuclk),
  .clk_out        (cpu_clk       ),
  .external_en    (gate_en0      )
);










soc_gated_clk_cell  x_soc_gated_sysclk_cell (
  .SE          (1'b0       ),
  .clk_in      (sysclk     ),
  .clk_out     (per_clk    ),
  .external_en (gate_en1   )
);










endmodule
module clk_aligner(
  clk_div_1,
  clk_div_2,
  clk_div_3,
  clk_div_4,
  clk_div_5,
  clk_div_6,
  clk_div_7,
  clk_div_8,
  clk_en,
  clk_en_1,
  clk_en_2,
  clk_en_3,
  clk_en_4,
  clk_en_5,
  clk_en_6,
  clk_en_7,
  clk_en_8,
  clkrst_b,
  cpu_clk,
  forever_cpuclk,
  gate_en0,
  gate_en1,
  paddr,
  penable,
  per_clk,
  pmu_clk,
  prdata,
  psel,
  pwdata,
  pwrite,
  wic_clk
);



input           clk_div_1;      
input           clk_div_2;      
input           clk_div_3;      
input           clk_div_4;      
input           clk_div_5;      
input           clk_div_6;      
input           clk_div_7;      
input           clk_div_8;      
input           clk_en_1;       
input           clk_en_2;       
input           clk_en_3;       
input           clk_en_4;       
input           clk_en_5;       
input           clk_en_6;       
input           clk_en_7;       
input           clk_en_8;       
input           clkrst_b;       
input           forever_cpuclk; 
input           gate_en0;       
input           gate_en1;       
input   [11:0]  paddr;          
input           penable;        
input           psel;           
input   [2 :0]  pwdata;         
input           pwrite;         
output          clk_en;         
output          cpu_clk;        
output          per_clk;        
output          pmu_clk;        
output  [31:0]  prdata;         
output          wic_clk;        


reg             clk_en;         
reg             gen_clk_en;     
reg     [2 :0]  input_clkratio; 
reg     [31:0]  prdata;         
reg             pre_clk_en;     
reg             pre_sysclk;     
reg             save_clk_en;    
reg     [2 :0]  save_clkratio;  
reg             save_sysclk;    
reg     [1 :0]  state_c;        
reg     [1 :0]  state_n;        
reg             sysclk;         


wire            clk_div_1;      
wire            clk_div_2;      
wire            clk_div_3;      
wire            clk_div_4;      
wire            clk_div_5;      
wire            clk_div_6;      
wire            clk_div_7;      
wire            clk_div_8;      
wire            clk_en_1;       
wire            clk_en_2;       
wire            clk_en_3;       
wire            clk_en_4;       
wire            clk_en_5;       
wire            clk_en_6;       
wire            clk_en_7;       
wire            clk_en_8;       
wire            clkratio_chg_en; 
wire            clkrst_b;       
wire            cpu_clk;        
wire            forever_cpuclk; 
wire            gate_en0;       
wire            gate_en1;       
wire    [11:0]  paddr;          
wire            penable;        
wire            per_clk;        
wire            pmu_clk;        
wire    [2 :0]  pre_clkratio;   
wire            psel;           
wire    [2 :0]  pwdata;         
wire            pwrite;         
wire            wic_clk;        


parameter IDLE = 2'b00,WAIT_PRE_EN = 2'b01,WAIT_NEXT_EN = 2'b10,MASK_SYSCLK = 2'b11;








always@(posedge per_clk or negedge clkrst_b)
begin
  if (!clkrst_b)
    input_clkratio[2:0] <= 3'b0;
  else if(psel && pwrite && penable)
  begin
    if (!paddr[11:0] )
      input_clkratio[2:0] <= pwdata[2:0];
  end
end

assign clkratio_chg_en = psel && pwrite && penable && !paddr[11:0] 
                      && !(pre_clkratio[2:0] ==pwdata[2:0]);


always @( input_clkratio[2:0]
       or paddr[11:0]
       or psel
       or pwrite)
begin
if(psel && !pwrite)
begin
  if(!paddr[11:0] )
    prdata[31:0] = {29'b0, input_clkratio[2:0]};
  else 
    prdata[31:0] = 32'b0;
end

end

   


always@(posedge forever_cpuclk or negedge clkrst_b)

begin
  if(!clkrst_b)
    state_c[1:0] <= IDLE;
  else
    state_c[1:0] <= state_n[1:0];
end


always @( clkratio_chg_en
       or state_c[1:0]
       or save_clk_en
       or pre_clk_en)
begin
  case(state_c[1:0])
  IDLE:
  begin
    if (clkratio_chg_en)
      state_n[1:0] = WAIT_PRE_EN;
    else
      state_n[1:0] = IDLE;
  end
  WAIT_PRE_EN:
  begin
    if (save_clk_en)
      state_n[1:0] = WAIT_NEXT_EN;
    else
      state_n[1:0] = WAIT_PRE_EN;
  end
  WAIT_NEXT_EN:
  begin

    if(pre_clk_en)
      state_n[1:0] = MASK_SYSCLK;

    else
      state_n[1:0] = WAIT_NEXT_EN;
  end
  MASK_SYSCLK:
  begin
    if(pre_clk_en)
      state_n[1:0] = IDLE;
    else
      state_n[1:0] = MASK_SYSCLK;
  end
  default:
  begin
    state_n[1:0] = IDLE;
  end
  endcase

end




always @( save_sysclk
       or pre_sysclk
       or state_c[1:0]
       or pre_clk_en)
begin
case(state_c[1:0])
  IDLE:
  begin
    gen_clk_en = pre_clk_en;
    sysclk = pre_sysclk;

  end
  WAIT_PRE_EN:
  begin


    gen_clk_en = 0;
    sysclk = save_sysclk;

  end
  WAIT_NEXT_EN:
  begin
    gen_clk_en = 0;
    sysclk = 0;

  end
  MASK_SYSCLK:
  begin
    gen_clk_en = pre_clk_en;
    sysclk = 0;

  end
  default:
  begin
    gen_clk_en = pre_clk_en;
    sysclk = pre_sysclk;

  end
endcase

end





assign pre_clkratio[2:0] = input_clkratio[2:0];


always @(posedge forever_cpuclk or negedge clkrst_b)
begin
  if(!clkrst_b)
    save_clkratio[2:0] <= 3'b0;
  else if(clkratio_chg_en)
    save_clkratio[2:0] <= pre_clkratio[2:0];
end



always @( clk_div_2
       or clk_en_7
       or clk_div_7
       or clk_div_4
       or clk_div_5
       or clk_en_5
       or clk_div_6
       or pre_clkratio[2:0]
       or clk_div_8
       or clk_div_1
       or clk_en_3
       or clk_en_8
       or clk_en_2
       or clk_en_4
       or clk_div_3
       or clk_en_6
       or clk_en_1)
begin
  case (pre_clkratio[2:0])
  3'b000:
  begin 
    pre_clk_en = clk_en_1;
    pre_sysclk = clk_div_1;
  end
  3'b001: 
  begin 
    pre_clk_en = clk_en_2;
    pre_sysclk = clk_div_2;
  end
  3'b010:
  begin 
    pre_clk_en = clk_en_3;
    pre_sysclk = clk_div_3;
  end
  3'b011: 
  begin 
    pre_clk_en = clk_en_4;
    pre_sysclk = clk_div_4;
  end
  3'b100: 
  begin 
    pre_clk_en = clk_en_5;
    pre_sysclk = clk_div_5;
  end
  3'b101: 
  begin 
    pre_clk_en = clk_en_6;
    pre_sysclk = clk_div_6;
  end
  3'b110: 
  begin 
    pre_clk_en = clk_en_7;
    pre_sysclk = clk_div_7;
  end
  3'b111: 
  begin 
    pre_clk_en = clk_en_8;
    pre_sysclk = clk_div_8;
  end
  default:
  begin 
    pre_clk_en = clk_en_1;
    pre_sysclk = clk_div_1;
  end
  endcase

end


always @( clk_div_2
       or clk_en_7
       or clk_div_7
       or clk_div_4
       or clk_en_5
       or clk_div_5
       or clk_div_6
       or clk_div_8
       or clk_en_3
       or clk_div_1
       or clk_en_8
       or save_clkratio[2:0]
       or clk_en_2
       or clk_en_4
       or clk_en_6
       or clk_div_3
       or clk_en_1)
begin
  case (save_clkratio[2:0])
  3'b000:
  begin 
    save_clk_en = clk_en_1;
    save_sysclk = clk_div_1;
  end
  3'b001: 
  begin 
    save_clk_en = clk_en_2;
    save_sysclk = clk_div_2;
  end
  3'b010:
  begin 
    save_clk_en = clk_en_3;
    save_sysclk = clk_div_3;
  end
  3'b011: 
  begin 
    save_clk_en = clk_en_4;
    save_sysclk = clk_div_4;
  end
  3'b100: 
  begin 
    save_clk_en = clk_en_5;
    save_sysclk = clk_div_5;
  end
  3'b101: 
  begin 
    save_clk_en = clk_en_6;
    save_sysclk = clk_div_6;
  end
  3'b110: 
  begin 
    save_clk_en = clk_en_7;
    save_sysclk = clk_div_7;
  end
  3'b111: 
  begin 
    save_clk_en = clk_en_8;
    save_sysclk = clk_div_8;
  end
  default:
  begin 
    save_clk_en = clk_en_1;
    save_sysclk = clk_div_1;
  end
  endcase

end











always @( gen_clk_en)
begin
  case(1'b1)
    1'b1: clk_en <= gen_clk_en;
    1'b0: clk_en <= 1'b0;
  endcase

end


assign wic_clk = forever_cpuclk;
assign pmu_clk = sysclk;



soc_gated_clk_cell  x_soc_gated_cpuclk_cell (
  .SE             (1'b0          ),
  .clk_in         (forever_cpuclk),
  .clk_out        (cpu_clk       ),
  .external_en    (gate_en0      )
);










soc_gated_clk_cell  x_soc_gated_sysclk_cell (
  .SE          (1'b0       ),
  .clk_in      (sysclk     ),
  .clk_out     (per_clk    ),
  .external_en (gate_en1   )
);










endmodule