data/full_repos/permissive/493019833/test/testcase/firrtl/EqModule/sbt/EqModule.v
data/verilator_xmls/72a88b20-d49b-462b-b16b-b2b3b966c39b.xml
module EqModule(
  input        clock,
  input        reset,
  input  [9:0] io_in,
  output [9:0] io_out
);
  wire  _T_5 = $signed(io_in) == 10'sh0;
  assign io_out = _T_5 ? $signed(10'sh1) : $signed(io_in);
endmodule
module EqModule(
  input        clock,
  input        reset,
  input  [9:0] io_in,
  output [9:0] io_out
);

  wire  _T_5 = $signed(io_in) == 10'sh0;
  assign io_out = _T_5 ? $signed(10'sh1) : $signed(io_in);
endmodule