data/full_repos/permissive/445695969/src_rtl/protected/dom1/skinny_sbox8_dom1_sni_noncomplete.v
data/verilator_xmls/ba21f3e1-097c-4b5f-ac66-dcf23ad0c9d7.xml
module dom1_sni_sbox8_cfn_nc (

   f,

   x, y, z, cycle, r, clk
   ) ;
   output reg [1:0]        f;
   input [1:0]         x, y, z;
   input [5:0]         cycle;
   input               r, clk;

   wire                s0, s1, s2, s3;
   wire                a0, a1, b0, b1, c0, c1, ri;

   wire                cs0, cs1;
   wire                cw0, cw1;

   reg [1:0]           g, t;

   assign a0 = (cycle[1] || cycle[3]) ? x[0] : 0;
   assign a1 = (cycle[0] || cycle[2]) ? ~x[1] : 0;
   assign b0 = (cycle[1] || cycle[2]) ? y[0] : 0;
   assign b1 = (cycle[0] || cycle[3]) ? ~y[1] : 0;
   assign c0 = cycle [1] ? z[0] : 0;
   assign c1 = cycle [0] ? z[1] : 0;
   assign ri = (cycle[2] || cycle[3]) ? r : 0;

   assign s0 = (cycle[0]) ? (a1 & b1) ^ c1 : 0;
   assign s1 = (cycle[1]) ? (a0 & b0) ^ c0 : 0;
   assign s2 = (cycle[2]) ? (a1 & b0) ^ ri : 0;
   assign s3 = (cycle[3]) ? (a0 & b1) ^ ri : 0;

   assign cw0 = (cycle[4]) ? t[0] ^ g[0] : 0;
   assign cw1 = (cycle[5]) ? t[1] ^ g[1] : 0;

   assign cs0 = (cycle[4]) ? cw0 : 0;
   assign cs1 = (cycle[5]) ? cw1 : 0;



   always @ (posedge clk) begin
      if (cycle[0]) g[1] <= s0;
      if (cycle[1]) g[0] <= s1;

      if (cycle[2]) t[1] <= s2;
      if (cycle[3]) t[0] <= s3;

      if (cycle[4]) f[0] <= cs0;
      if (cycle[5]) f[1] <= cs1;
   end

endmodule
module dom1_sni_sbox8_cfn_nc (

   f,

   x, y, z, cycle, r, clk
   ) ;

   output reg [1:0]        f;
   input [1:0]         x, y, z;
   input [5:0]         cycle;
   input               r, clk;

   wire                s0, s1, s2, s3;
   wire                a0, a1, b0, b1, c0, c1, ri;

   wire                cs0, cs1;
   wire                cw0, cw1;

   reg [1:0]           g, t;

   assign a0 = (cycle[1] || cycle[3]) ? x[0] : 0;
   assign a1 = (cycle[0] || cycle[2]) ? ~x[1] : 0;
   assign b0 = (cycle[1] || cycle[2]) ? y[0] : 0;
   assign b1 = (cycle[0] || cycle[3]) ? ~y[1] : 0;
   assign c0 = cycle [1] ? z[0] : 0;
   assign c1 = cycle [0] ? z[1] : 0;
   assign ri = (cycle[2] || cycle[3]) ? r : 0;

   assign s0 = (cycle[0]) ? (a1 & b1) ^ c1 : 0;
   assign s1 = (cycle[1]) ? (a0 & b0) ^ c0 : 0;
   assign s2 = (cycle[2]) ? (a1 & b0) ^ ri : 0;
   assign s3 = (cycle[3]) ? (a0 & b1) ^ ri : 0;

   assign cw0 = (cycle[4]) ? t[0] ^ g[0] : 0;
   assign cw1 = (cycle[5]) ? t[1] ^ g[1] : 0;

   assign cs0 = (cycle[4]) ? cw0 : 0;
   assign cs1 = (cycle[5]) ? cw1 : 0;



   always @ (posedge clk) begin
      if (cycle[0]) g[1] <= s0;
      if (cycle[1]) g[0] <= s1;

      if (cycle[2]) t[1] <= s2;
      if (cycle[3]) t[0] <= s3;

      if (cycle[4]) f[0] <= cs0;
      if (cycle[5]) f[1] <= cs1;
   end

endmodule