data/full_repos/permissive/46132596/processor/SingleCycleDatapath/Alu.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/46132596/processor/SingleCycleDatapath/Alu.v:30: Multiple top level modules\n                                                                                             : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                             : ... Top module \'Alu\'\nmodule Alu(input[31:0] op1,\n       ^~~\n                                                                                             : ... Top module \'Mult_Div_Alu\'\nmodule Mult_Div_Alu(input[31:0] op1,\n       ^~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module Alu(input[31:0] op1,
		input[31:0] op2,
		input[3:0] f,
		output reg[31:0] result,
		output zero);

	always @(op1, op2, f)
		case (f)
			0: result = op1 + op2;
            1: result = op1 - op2;
            2: result = op1 & op2;
            3: result = op1 | op2;
            4: result = op1 ~| op2;
            5: result = op1 ^ op2;
            6: result = op1 << op2;
            7: result = op1 >> op2;
            8: result = op1 >>> op2;
            9: result = ($signed(op1) < $signed(op2)) ? 1 : 0;
            10: result = (op1 < op2) ? 1 : 0;

        endcase 
	
	assign zero = result == 0;
endmodule
module Alu(input[31:0] op1,
		input[31:0] op2,
		input[3:0] f,
		output reg[31:0] result,
		output zero);


	always @(op1, op2, f)
		case (f)
			0: result = op1 + op2;
            1: result = op1 - op2;
            2: result = op1 & op2;
            3: result = op1 | op2;
            4: result = op1 ~| op2;
            5: result = op1 ^ op2;
            6: result = op1 << op2;
            7: result = op1 >> op2;
            8: result = op1 >>> op2;
            9: result = ($signed(op1) < $signed(op2)) ? 1 : 0;
            10: result = (op1 < op2) ? 1 : 0;

        endcase 
	
	assign zero = result == 0;
endmodule