data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/serial_adder_84.v
1: b"%Error: data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/serial_adder_84.v:160: Cannot find file containing module: 'full_add'\n    full_add inst_adder1 (\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/496096937/verilog/rtl/patently-obvious,data/full_repos/permissive/496096937/full_add\n             data/full_repos/permissive/496096937/verilog/rtl/patently-obvious,data/full_repos/permissive/496096937/full_add.v\n             data/full_repos/permissive/496096937/verilog/rtl/patently-obvious,data/full_repos/permissive/496096937/full_add.sv\n             full_add\n             full_add.v\n             full_add.sv\n             obj_dir/full_add\n             obj_dir/full_add.v\n             obj_dir/full_add.sv\n%Error: data/full_repos/permissive/496096937/verilog/rtl/patently-obvious/serial_adder_84.v:171: Cannot find file containing module: 'full_add'\n    full_add inst_adder2 (\n    ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module serial_adder_84 #(
    parameter   NewArch = 0
)
(

    output      SUM1,
    output      SUM2,
    output reg  USE_SUM2,
    output reg  CARRY,

    input       X_IN,
    input       Y_IN,
    input       C_IN,
    input       FIRST_BIT,
    input       SUB,
    input       T1,
    input       T2,
    input       T4,
    input       PHI2
);

    wire    sum1_int;
    wire    sum2_int;
    wire    co1;
    wire    co2;
        
    reg     ci1 = 1'b0;

    reg     y_in2 = 1'b0;
    reg     co1_r = 1'b0;
    reg     co2_r = 1'b0;
    



    assign SUM1 = sum1_int ^ SUB;
    assign SUM2 = sum2_int ^ SUB;


    always @* begin : proc_carry_in1
        if (FIRST_BIT) 
            ci1 <= C_IN;
        else
            ci1 <= co1_r | co2_r & T1 & ~SUB;
    end
    

    always @* begin : proc_y_in2
        case (1'b1)
            T1 : y_in2 <= 0;
            T2 : y_in2 <= 1;
            T3 : y_in2 <= 1;
            T4 : y_in2 <= 0;
            default : y_in2 <= 0;
        endcase
    end
    

    always @(posedge PHI2) begin : proc_carry_flops
        co1_r <= co1;
        co2_r <= co2;
    end






    always @* begin : proc_carry
        if (SUB) begin
            USE_SUM2 <= T4 & co1;
            CARRY    <= T4 & co1;
        end
        else begin
            USE_SUM2 <= T4 & (co1 | co2);
            CARRY    <= T4 & (co1 | co2);
        end
    end


    full_add inst_adder1 (

        .sum        (sum1_int),
        .co         (co1),

        .x          (X_IN ^ SUB),
        .y          (Y_IN),
        .ci         (ci1)
    );


    full_add inst_adder2 (

        .sum        (sum2_int),
        .co         (co2),

        .x          (sum1_int),
        .y          (y_in2),
        .ci         (co2_r & ~T1)
    );

endmodule
module serial_adder_84 #(
    parameter   NewArch = 0
)
(

    output      SUM1,
    output      SUM2,
    output reg  USE_SUM2,
    output reg  CARRY,

    input       X_IN,
    input       Y_IN,
    input       C_IN,
    input       FIRST_BIT,
    input       SUB,
    input       T1,
    input       T2,
    input       T4,
    input       PHI2
);


    wire    sum1_int;
    wire    sum2_int;
    wire    co1;
    wire    co2;
        
    reg     ci1 = 1'b0;

    reg     y_in2 = 1'b0;
    reg     co1_r = 1'b0;
    reg     co2_r = 1'b0;
    



    assign SUM1 = sum1_int ^ SUB;
    assign SUM2 = sum2_int ^ SUB;


    always @* begin : proc_carry_in1
        if (FIRST_BIT) 
            ci1 <= C_IN;
        else
            ci1 <= co1_r | co2_r & T1 & ~SUB;
    end
    

    always @* begin : proc_y_in2
        case (1'b1)
            T1 : y_in2 <= 0;
            T2 : y_in2 <= 1;
            T3 : y_in2 <= 1;
            T4 : y_in2 <= 0;
            default : y_in2 <= 0;
        endcase
    end
    

    always @(posedge PHI2) begin : proc_carry_flops
        co1_r <= co1;
        co2_r <= co2;
    end






    always @* begin : proc_carry
        if (SUB) begin
            USE_SUM2 <= T4 & co1;
            CARRY    <= T4 & co1;
        end
        else begin
            USE_SUM2 <= T4 & (co1 | co2);
            CARRY    <= T4 & (co1 | co2);
        end
    end


    full_add inst_adder1 (

        .sum        (sum1_int),
        .co         (co1),

        .x          (X_IN ^ SUB),
        .y          (Y_IN),
        .ci         (ci1)
    );


    full_add inst_adder2 (

        .sum        (sum2_int),
        .co         (co2),

        .x          (sum1_int),
        .y          (y_in2),
        .ci         (co2_r & ~T1)
    );

endmodule