data/full_repos/permissive/431682734/LabL/LabL3.v
1: b'%Error: data/full_repos/permissive/431682734/LabL/LabL3.v:3: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n    reg [31:0] a, b, expect;\n                     ^~~~~~\n%Error: data/full_repos/permissive/431682734/LabL/LabL3.v:3: syntax error, unexpected \';\', expecting IDENTIFIER or \'=\' or do or final\n    reg [31:0] a, b, expect;\n                           ^\n%Error: data/full_repos/permissive/431682734/LabL/LabL3.v:19: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n                expect[i] = ((a[i] & ~c) + (b[i] & c));  \n                ^~~~~~\n%Error: data/full_repos/permissive/431682734/LabL/LabL3.v:19: syntax error, unexpected \'[\'\n                expect[i] = ((a[i] & ~c) + (b[i] & c));  \n                      ^\n%Warning-STMTDLY: data/full_repos/permissive/431682734/LabL/LabL3.v:21: Unsupported: Ignoring delay on this delayed statement.\n            #1;  \n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/431682734/LabL/LabL3.v:25: Unsupported: SystemVerilog 2005 reserved word not implemented: \'expect\'\n            if (expect === z)\n                ^~~~~~\n%Error: data/full_repos/permissive/431682734/LabL/LabL3.v:25: syntax error, unexpected ===, expecting TYPE-IDENTIFIER\n            if (expect === z)\n                       ^~~\n%Error: Exiting due to 6 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module labL;
    reg c;
    reg [31:0] a, b, expect;
    wire [31:0] z;
    integer i;


    yMux #(.SIZE(32)) my_mux[31:0](z, a, b, c);


    initial begin
        repeat (10)
        begin
            a = $random;
            b = $random;
            c = $random % 2;
            for (i = 0; i < 32; i = i + 1)
            begin
                expect[i] = ((a[i] & ~c) + (b[i] & c));
            end
            #1;



            if (expect === z)
                $display("PASS: a=%b b=%b c=%b z=%b", a, b, c, z);
            else
                $display("FAIL: a=%b b=%b c=%b z=%b", a, b, c, z);
        end
    $finish;
    end
endmodule
module labL;

    reg c;
    reg [31:0] a, b, expect;
    wire [31:0] z;
    integer i;


    yMux #(.SIZE(32)) my_mux[31:0](z, a, b, c);


    initial begin
        repeat (10)
        begin
            a = $random;
            b = $random;
            c = $random % 2;
            for (i = 0; i < 32; i = i + 1)
            begin
                expect[i] = ((a[i] & ~c) + (b[i] & c));
            end
            #1;



            if (expect === z)
                $display("PASS: a=%b b=%b c=%b z=%b", a, b, c, z);
            else
                $display("FAIL: a=%b b=%b c=%b z=%b", a, b, c, z);
        end
    $finish;
    end
endmodule