data/full_repos/permissive/447976230/fpga/usrp1/megacells/accum32_bb.v
data/verilator_xmls/c919e1b9-69c3-4364-9f7b-cdd33cf77a48.xml
module accum32 (
	data,
	clock,
	clken,
	aclr,
	result);

	input	[31:0]  data;
	input	  clock;
	input	  clken;
	input	  aclr;
	output	[31:0]  result;

endmodule
module accum32 (
	data,
	clock,
	clken,
	aclr,
	result);


	input	[31:0]  data;
	input	  clock;
	input	  clken;
	input	  aclr;
	output	[31:0]  result;

endmodule