data/full_repos/permissive/486812922/src/gpr.v
data/verilator_xmls/a25ae6eb-d89c-40c8-9bcc-50611c670c3e.xml
module gpr(clk, reset, we, addr1, addr2, addr3, inputdata, RD1, RD2);
input clk;
input reset;
input we;
input [4: 0] addr1;
input [4: 0] addr2;
input [4: 0] addr3;
input [31: 0] inputdata;
output [31: 0] RD1;
output [31: 0] RD2;
reg [31: 0] registers [31: 0];
integer i = 0;


assign RD1 = (clk == 1) ? registers[addr1] : RD1;
assign RD2 = (clk == 1) ? registers[addr2] : RD2;


initial begin
    for (i = 0; i < 32; i = i + 1) begin
        registers[i] = 32'h00000000;
    end
end

always @ ( posedge reset or negedge clk) begin

    if (reset) begin
        for (i = 0; i < 32; i = i + 1) begin
            registers[i] = 32'h00000000;
        end
    end
    else if (we & addr3 != 5'h00) begin

        registers[addr3] <= inputdata;

    end
end
endmodule
module gpr(clk, reset, we, addr1, addr2, addr3, inputdata, RD1, RD2);

input clk;
input reset;
input we;
input [4: 0] addr1;
input [4: 0] addr2;
input [4: 0] addr3;
input [31: 0] inputdata;
output [31: 0] RD1;
output [31: 0] RD2;
reg [31: 0] registers [31: 0];
integer i = 0;


assign RD1 = (clk == 1) ? registers[addr1] : RD1;
assign RD2 = (clk == 1) ? registers[addr2] : RD2;


initial begin
    for (i = 0; i < 32; i = i + 1) begin
        registers[i] = 32'h00000000;
    end
end

always @ ( posedge reset or negedge clk) begin

    if (reset) begin
        for (i = 0; i < 32; i = i + 1) begin
            registers[i] = 32'h00000000;
        end
    end
    else if (we & addr3 != 5'h00) begin

        registers[addr3] <= inputdata;

    end
end
endmodule