data/full_repos/permissive/455223995/src/slzw_dict.v
1: b"%Error: data/full_repos/permissive/455223995/src/slzw_dict.v:219: syntax error, unexpected byte\n    .byte                      (match_byte),\n     ^~~~\n%Error: data/full_repos/permissive/455223995/src/slzw_dict.v:226: syntax error, unexpected byte\n    .byte                      (match_byte),\n     ^~~~\n%Error: data/full_repos/permissive/455223995/src/slzw_dict.v:233: syntax error, unexpected byte\n    .byte                      (last_match_byte),\n     ^~~~\n%Error: data/full_repos/permissive/455223995/src/slzw_dict.v:271: Define or directive not defined: '`RESET'\nalways @(posedge clk `RESET)\n                     ^~~~~~\n%Error: data/full_repos/permissive/455223995/src/slzw_dict.v:319: Define or directive not defined: '`RESET'\nalways @(posedge clk `RESET)\n                     ^~~~~~\n%Error: Exiting due to 5 error(s)\n"
module slzw_dict
#(parameter
  MEMSIZE                      = 10240
)
(
  input                        clk,
  input                        reset_n,

  input                        clr,


  input                        compress,


  input                        match,
  input      [11:0]            match_code,
  input       [7:0]            match_byte,
  output reg                   matched,
  output reg                   matched_valid,


  input                        build_entry,
  input      [11:0]            build_code,
  input       [7:0]            build_byte,


  input      [11:0]            dict_decomp_ptr,
  output     [12:0]            dict_code,
  output      [7:0]            dict_byte,

  output reg  [3:0]            op_code_len

);






localparam                     MINCWLEN           = 4'd9;
localparam                     DICTFULL           = 13'h1000;
localparam                     FIRSTCW            = 13'h0100;


localparam                     state_idle         = 3'd0;
localparam                     state_rdmem        = 3'd1;
localparam                     state_rehash       = 3'd2;
localparam                     state_build        = 3'd3;
localparam                     state_rehash_retry = 3'd4;






reg  [2:0]                     state;


reg  [12:0]                    next_avail_code;
reg  [12:0]                    nac_plus_1;


reg  [13:0]                    last_match_addr;
reg  [13:0]                    last_match_code;
reg   [7:0]                    last_match_byte;


reg  [13:0]                    seed;
reg                            rehash;
reg                            cmp_build;
reg                            occ_clr;






wire [12:0]                    nac_cmp;


wire                           wr_dict;
wire [13:0]                    wr_addr;
wire [12:0]                    wr_code;
wire  [7:0]                    wr_byte;


wire [13:0]                    raddr;


wire [13:0]                    raddr1;
wire [13:0]                    raddr2;


wire [12:0]                    hcode;
wire [13:0]                    haddr;
wire [13:0]                    addr1;
wire [13:0]                    addr2;


wire                           dict_full;


wire                           collision;
wire  [1:0]                    occupied;
wire                           occ_busy;
wire                           occ_set;





  slzw_dictmem
  #(.MEMSIZE                   (MEMSIZE),
    .WIDTH                     (8)
  ) dictmem_byte
  (
    .clk                       (clk),

    .write                     (wr_dict),
    .waddr                     (wr_addr),
    .wdata                     (wr_byte),

    .raddr                     (raddr),
    .rdata                     (dict_byte)
  );

  slzw_dictmem
  #(.MEMSIZE                   (MEMSIZE),
    .WIDTH                     (13)
  ) dictmem_code
  (
    .clk                       (clk),

    .write                     (wr_dict),
    .waddr                     (wr_addr),
    .wdata                     (wr_code),

    .raddr                     (raddr),
    .rdata                     (dict_code)
  );

  slzw_mem_occupied
  #(.MEMSIZE                   (MEMSIZE)
  ) mem_occ
  (
    .clk                       (clk),
    .reset_n                   (reset_n),

    .clr                       (occ_clr),

    .waddr                     (haddr),
    .raddr                     (raddr1),
    .set                       (occ_set),

    .occupied                  (occupied[0]),
    .busy                      (occ_busy)
  );

  slzw_mem_occupied
  #(.MEMSIZE                   (MEMSIZE)
  ) mem_occ_aux
  (
    .clk                       (clk),
    .reset_n                   (reset_n),

    .clr                       (occ_clr),

    .waddr                     (haddr),
    .raddr                     (raddr2),
    .set                       (occ_set),

    .occupied                  (occupied[1]),
    .busy                      ()
  );
  




  slzw_hash hash_i
  (
    .code                      (hcode),
    .byte                      (match_byte),
    .haddr                     (haddr)
  );

  slzw_hash seed_hash_1
  (
    .code                      (seed[12:0]),
    .byte                      (match_byte),
    .haddr                     (addr1)
  );

  slzw_hash seed_hash_2
  (
    .code                      (seed[12:0]),
    .byte                      (last_match_byte),
    .haddr                     (addr2)
  );






assign dict_full               = next_avail_code[12];


assign frozen                  = seed[13];



assign wr_dict                 = (~compress & build_entry & ~dict_full) | (compress & cmp_build & ~dict_full & ~frozen);

assign wr_addr                 = ~compress ? {1'b0, next_avail_code} : last_match_addr;
assign wr_code                 = ~compress ? {1'b0, build_code}      : next_avail_code;
assign wr_byte                 = ~compress ? build_byte              : last_match_byte;

assign raddr                   = ~compress ? dict_decomp_ptr         : haddr;
assign raddr1                  = rehash ? addr1                      : haddr;
assign raddr2                  = addr2;




assign nac_cmp                 = ~compress ? nac_plus_1              : next_avail_code;

assign hcode                   = (state == state_idle) ? match_code  : dict_code;
assign collision               = dict_code[12];





always @(posedge clk `RESET)
begin
  if (reset_n == 1'b0)
  begin
    next_avail_code            <= FIRSTCW;
    nac_plus_1                 <= FIRSTCW+1;
    op_code_len                <= MINCWLEN;
    occ_clr                    <= 1'b0;
  end
  else
  begin

    occ_clr                    <= 1'b0;

    if (clr)
    begin
      next_avail_code          <= FIRSTCW;
      nac_plus_1               <= FIRSTCW + 1;
      occ_clr                  <= 1'b1;
    end
    else if (build_entry | cmp_build)
    begin
      if (~dict_full)
      begin
        next_avail_code        <= next_avail_code + 13'h0001;
        nac_plus_1             <= nac_plus_1      + 13'h0001;
      end
      else
      begin
        next_avail_code        <= FIRSTCW;
        nac_plus_1             <= FIRSTCW+1;
        occ_clr                <= 1'b1;
      end

      case (nac_cmp)
        13'h0200 : op_code_len <= MINCWLEN + 1;
        13'h0400 : op_code_len <= MINCWLEN + 2;
        13'h0800 : op_code_len <= MINCWLEN + 3;
        13'h1000 : op_code_len <= MINCWLEN;
      endcase
    end
  end
end





always @(posedge clk `RESET)
begin
  if (reset_n == 1'b0)
  begin
    state                      <= state_idle;
    matched_valid              <= 1'b0;
    matched                    <= 1'b0;
    seed                       <= 14'h0000;

    rehash                     <= 1'b0;
    cmp_build                  <= 1'b0;
  end
  else
  begin

    matched_valid              <= 1'b0;
    matched                    <= 1'b0;
    cmp_build                  <= 1'b0;

    case (state)
      state_idle:
      begin
        if (match && !occ_busy && !occ_clr)
        begin
          state                <= state_rdmem;
        end
      end

      state_rdmem:
      begin


        last_match_addr        <= haddr;
        last_match_code        <= dict_code;
        last_match_byte        <= dict_byte;


        if (~occupied[0])
        begin
          matched_valid        <= 1'b1;
          state                <= state_build;
        end
        else
        begin





          if (!collision)
          begin
            matched_valid      <= 1'b1;



            if (match_byte == dict_byte)
            begin
              state            <= state_idle;
              matched          <= 1'b1;
            end
            else
            begin
              state            <= state_rehash;
              rehash           <= 1'b1;
            end
          end
        end
      end

      state_build:
      begin
        cmp_build              <= 1'b1;
        rehash                 <= 1'b0;
        
        if (dict_full)
        begin
          seed                 <= 14'h0000;
        end
        state                  <= state_idle;
      end

      state_rehash:
      begin
        if (~frozen)
        begin
          state                <= state_rehash_retry;
          seed                 <= seed + 14'd1;
        end
        else
        begin
          rehash               <= 1'b0;
          state                <= state_idle;
        end
      end

      state_rehash_retry:
      begin
        if (~|occupied)
        begin
          state                <= state_build;
        end
        seed                   <= seed + 14'd1;
      end

      default:
        state                  <= state_idle;
    endcase


    if (clr)
    begin
      state                    <= state_idle;
      matched_valid            <= 1'b0;
      matched                  <= 1'b0;
      seed                     <= 14'h0000;
      rehash                   <= 1'b0;
      cmp_build                <= 1'b0;
    end
  end
end

endmodule
module slzw_dict
#(parameter
  MEMSIZE                      = 10240
)
(
  input                        clk,
  input                        reset_n,

  input                        clr,


  input                        compress,


  input                        match,
  input      [11:0]            match_code,
  input       [7:0]            match_byte,
  output reg                   matched,
  output reg                   matched_valid,


  input                        build_entry,
  input      [11:0]            build_code,
  input       [7:0]            build_byte,


  input      [11:0]            dict_decomp_ptr,
  output     [12:0]            dict_code,
  output      [7:0]            dict_byte,

  output reg  [3:0]            op_code_len

);







localparam                     MINCWLEN           = 4'd9;
localparam                     DICTFULL           = 13'h1000;
localparam                     FIRSTCW            = 13'h0100;


localparam                     state_idle         = 3'd0;
localparam                     state_rdmem        = 3'd1;
localparam                     state_rehash       = 3'd2;
localparam                     state_build        = 3'd3;
localparam                     state_rehash_retry = 3'd4;






reg  [2:0]                     state;


reg  [12:0]                    next_avail_code;
reg  [12:0]                    nac_plus_1;


reg  [13:0]                    last_match_addr;
reg  [13:0]                    last_match_code;
reg   [7:0]                    last_match_byte;


reg  [13:0]                    seed;
reg                            rehash;
reg                            cmp_build;
reg                            occ_clr;






wire [12:0]                    nac_cmp;


wire                           wr_dict;
wire [13:0]                    wr_addr;
wire [12:0]                    wr_code;
wire  [7:0]                    wr_byte;


wire [13:0]                    raddr;


wire [13:0]                    raddr1;
wire [13:0]                    raddr2;


wire [12:0]                    hcode;
wire [13:0]                    haddr;
wire [13:0]                    addr1;
wire [13:0]                    addr2;


wire                           dict_full;


wire                           collision;
wire  [1:0]                    occupied;
wire                           occ_busy;
wire                           occ_set;





  slzw_dictmem
  #(.MEMSIZE                   (MEMSIZE),
    .WIDTH                     (8)
  ) dictmem_byte
  (
    .clk                       (clk),

    .write                     (wr_dict),
    .waddr                     (wr_addr),
    .wdata                     (wr_byte),

    .raddr                     (raddr),
    .rdata                     (dict_byte)
  );

  slzw_dictmem
  #(.MEMSIZE                   (MEMSIZE),
    .WIDTH                     (13)
  ) dictmem_code
  (
    .clk                       (clk),

    .write                     (wr_dict),
    .waddr                     (wr_addr),
    .wdata                     (wr_code),

    .raddr                     (raddr),
    .rdata                     (dict_code)
  );

  slzw_mem_occupied
  #(.MEMSIZE                   (MEMSIZE)
  ) mem_occ
  (
    .clk                       (clk),
    .reset_n                   (reset_n),

    .clr                       (occ_clr),

    .waddr                     (haddr),
    .raddr                     (raddr1),
    .set                       (occ_set),

    .occupied                  (occupied[0]),
    .busy                      (occ_busy)
  );

  slzw_mem_occupied
  #(.MEMSIZE                   (MEMSIZE)
  ) mem_occ_aux
  (
    .clk                       (clk),
    .reset_n                   (reset_n),

    .clr                       (occ_clr),

    .waddr                     (haddr),
    .raddr                     (raddr2),
    .set                       (occ_set),

    .occupied                  (occupied[1]),
    .busy                      ()
  );
  




  slzw_hash hash_i
  (
    .code                      (hcode),
    .byte                      (match_byte),
    .haddr                     (haddr)
  );

  slzw_hash seed_hash_1
  (
    .code                      (seed[12:0]),
    .byte                      (match_byte),
    .haddr                     (addr1)
  );

  slzw_hash seed_hash_2
  (
    .code                      (seed[12:0]),
    .byte                      (last_match_byte),
    .haddr                     (addr2)
  );






assign dict_full               = next_avail_code[12];


assign frozen                  = seed[13];



assign wr_dict                 = (~compress & build_entry & ~dict_full) | (compress & cmp_build & ~dict_full & ~frozen);

assign wr_addr                 = ~compress ? {1'b0, next_avail_code} : last_match_addr;
assign wr_code                 = ~compress ? {1'b0, build_code}      : next_avail_code;
assign wr_byte                 = ~compress ? build_byte              : last_match_byte;

assign raddr                   = ~compress ? dict_decomp_ptr         : haddr;
assign raddr1                  = rehash ? addr1                      : haddr;
assign raddr2                  = addr2;




assign nac_cmp                 = ~compress ? nac_plus_1              : next_avail_code;

assign hcode                   = (state == state_idle) ? match_code  : dict_code;
assign collision               = dict_code[12];





always @(posedge clk `RESET)
begin
  if (reset_n == 1'b0)
  begin
    next_avail_code            <= FIRSTCW;
    nac_plus_1                 <= FIRSTCW+1;
    op_code_len                <= MINCWLEN;
    occ_clr                    <= 1'b0;
  end
  else
  begin

    occ_clr                    <= 1'b0;

    if (clr)
    begin
      next_avail_code          <= FIRSTCW;
      nac_plus_1               <= FIRSTCW + 1;
      occ_clr                  <= 1'b1;
    end
    else if (build_entry | cmp_build)
    begin
      if (~dict_full)
      begin
        next_avail_code        <= next_avail_code + 13'h0001;
        nac_plus_1             <= nac_plus_1      + 13'h0001;
      end
      else
      begin
        next_avail_code        <= FIRSTCW;
        nac_plus_1             <= FIRSTCW+1;
        occ_clr                <= 1'b1;
      end

      case (nac_cmp)
        13'h0200 : op_code_len <= MINCWLEN + 1;
        13'h0400 : op_code_len <= MINCWLEN + 2;
        13'h0800 : op_code_len <= MINCWLEN + 3;
        13'h1000 : op_code_len <= MINCWLEN;
      endcase
    end
  end
end





always @(posedge clk `RESET)
begin
  if (reset_n == 1'b0)
  begin
    state                      <= state_idle;
    matched_valid              <= 1'b0;
    matched                    <= 1'b0;
    seed                       <= 14'h0000;

    rehash                     <= 1'b0;
    cmp_build                  <= 1'b0;
  end
  else
  begin

    matched_valid              <= 1'b0;
    matched                    <= 1'b0;
    cmp_build                  <= 1'b0;

    case (state)
      state_idle:
      begin
        if (match && !occ_busy && !occ_clr)
        begin
          state                <= state_rdmem;
        end
      end

      state_rdmem:
      begin


        last_match_addr        <= haddr;
        last_match_code        <= dict_code;
        last_match_byte        <= dict_byte;


        if (~occupied[0])
        begin
          matched_valid        <= 1'b1;
          state                <= state_build;
        end
        else
        begin





          if (!collision)
          begin
            matched_valid      <= 1'b1;



            if (match_byte == dict_byte)
            begin
              state            <= state_idle;
              matched          <= 1'b1;
            end
            else
            begin
              state            <= state_rehash;
              rehash           <= 1'b1;
            end
          end
        end
      end

      state_build:
      begin
        cmp_build              <= 1'b1;
        rehash                 <= 1'b0;
        
        if (dict_full)
        begin
          seed                 <= 14'h0000;
        end
        state                  <= state_idle;
      end

      state_rehash:
      begin
        if (~frozen)
        begin
          state                <= state_rehash_retry;
          seed                 <= seed + 14'd1;
        end
        else
        begin
          rehash               <= 1'b0;
          state                <= state_idle;
        end
      end

      state_rehash_retry:
      begin
        if (~|occupied)
        begin
          state                <= state_build;
        end
        seed                   <= seed + 14'd1;
      end

      default:
        state                  <= state_idle;
    endcase


    if (clr)
    begin
      state                    <= state_idle;
      matched_valid            <= 1'b0;
      matched                  <= 1'b0;
      seed                     <= 14'h0000;
      rehash                   <= 1'b0;
      cmp_build                <= 1'b0;
    end
  end
end

endmodule