data/full_repos/permissive/433640910/RateDivider/ratedivider.v
data/verilator_xmls/57a74fa6-75f9-4eaa-9a52-504b12b5b704.xml
module main	(
	input wire CLOCK_50,
	input wire [9:0] SW,
	input wire [3:0] KEY,
	output wire [6:0] HEX0,
	output wire [6:0] HEX1,         
	output wire [6:0] HEX2,         
	output wire [6:0] HEX3,         
	output wire [6:0] HEX4,         
	output wire [6:0] HEX5,         
	output wire [9:0] LEDR,
	output wire [7:0] x,
	output wire [6:0] y,
	output wire [2:0] colour,
	output wire plot,
	output wire vga_resetn
);    
	
	wire [3:0] CounterValue;
	
	part2 u0(CLOCK_50, SW[9], SW[1:0], CounterValue);
	hex_decoder u1(CounterValue, HEX1);

	

endmodule
module main	(
	input wire CLOCK_50,
	input wire [9:0] SW,
	input wire [3:0] KEY,
	output wire [6:0] HEX0,
	output wire [6:0] HEX1,         
	output wire [6:0] HEX2,         
	output wire [6:0] HEX3,         
	output wire [6:0] HEX4,         
	output wire [6:0] HEX5,         
	output wire [9:0] LEDR,
	output wire [7:0] x,
	output wire [6:0] y,
	output wire [2:0] colour,
	output wire plot,
	output wire vga_resetn
);
    
	
	wire [3:0] CounterValue;
	
	part2 u0(CLOCK_50, SW[9], SW[1:0], CounterValue);
	hex_decoder u1(CounterValue, HEX1);

	

endmodule