data/full_repos/permissive/527176783/Pipeline/IF_ID.v
data/verilator_xmls/721afec0-129f-40ed-9962-fdbeb2357e08.xml
module IF_ID(
    input clk,
    input rst_n,
    input Flush_IF,
    input Stall_ID,
    input [31:0] PC_IF,
    input [31:0] Instruction_IF,

    output reg[31:0] PC_ID,
    output reg[31:0] Instruction_ID
);
    always @(posedge clk,negedge rst_n) begin
        if(~rst_n) begin
            Instruction_ID <= 32'd0;
            PC_ID <= 32'd0;
        end 
        else if(Flush_IF == 1'b1) begin
            Instruction_ID <= 32'hFC00_0000;

        end
        else if(Stall_ID == 1'b0) begin
            Instruction_ID <= Instruction_IF;
            PC_ID <= PC_IF;
            $display(" CurrentPC :0x%x ", PC_IF);
        end

    end

endmodule
module IF_ID(
    input clk,
    input rst_n,
    input Flush_IF,
    input Stall_ID,
    input [31:0] PC_IF,
    input [31:0] Instruction_IF,

    output reg[31:0] PC_ID,
    output reg[31:0] Instruction_ID
);

    always @(posedge clk,negedge rst_n) begin
        if(~rst_n) begin
            Instruction_ID <= 32'd0;
            PC_ID <= 32'd0;
        end 
        else if(Flush_IF == 1'b1) begin
            Instruction_ID <= 32'hFC00_0000;

        end
        else if(Stall_ID == 1'b0) begin
            Instruction_ID <= Instruction_IF;
            PC_ID <= PC_IF;
            $display(" CurrentPC :0x%x ", PC_IF);
        end

    end

endmodule