data/full_repos/permissive/500947188/rtl/sound/Dual_YM3526_Sound.sv
1: b"%Error: data/full_repos/permissive/500947188/rtl/sound/Dual_YM3526_Sound.sv:67: Cannot find file containing module: 'T80pa'\n        T80pa z80_g2 (\n        ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/500947188/rtl/sound,data/full_repos/permissive/500947188/T80pa\n             data/full_repos/permissive/500947188/rtl/sound,data/full_repos/permissive/500947188/T80pa.v\n             data/full_repos/permissive/500947188/rtl/sound,data/full_repos/permissive/500947188/T80pa.sv\n             T80pa\n             T80pa.v\n             T80pa.sv\n             obj_dir/T80pa\n             obj_dir/T80pa.v\n             obj_dir/T80pa.sv\n%Error: data/full_repos/permissive/500947188/rtl/sound/Dual_YM3526_Sound.sv:109: Cannot find file containing module: 'jtopl'\n    jtopl  YM3526_1\n    ^~~~~\n%Error: data/full_repos/permissive/500947188/rtl/sound/Dual_YM3526_Sound.sv:125: Cannot find file containing module: 'jtopl'\n    jtopl  YM3526_2\n    ^~~~~\n%Error: data/full_repos/permissive/500947188/rtl/sound/Dual_YM3526_Sound.sv:146: Cannot find file containing module: 'ttl_74139_nodly'\n    ttl_74139_nodly F4_2(.Enable_bar(1'b0), .A_2D(A[15:14]), .Y_2D({F4_2_Y3n, CS_ROM_2n, CS_ROM_1n, CS_ROM_0n}));\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/sound/Dual_YM3526_Sound.sv:154: Cannot find file containing module: 'ttl_74139_nodly'\n    ttl_74139_nodly F4_1(.Enable_bar(F4_1_Gn), .A_2D(A[12:11]), .Y_2D({SOUND_STATUS,YM3526_RW2,YM3526_RW1,LATCH_MCODEn}));\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/sound/Dual_YM3526_Sound.sv:159: Cannot find file containing module: 'selector_dualYM3526_cpu_snd_rom'\n    selector_dualYM3526_cpu_snd_rom ROM_Sel\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/sound/Dual_YM3526_Sound.sv:166: Cannot find file containing module: 'eprom_16K'\n    eprom_16K ROM0\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/sound/Dual_YM3526_Sound.sv:179: Cannot find file containing module: 'eprom_16K'\n    eprom_16K ROM1\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/sound/Dual_YM3526_Sound.sv:191: Cannot find file containing module: 'eprom_16K'\n    eprom_16K ROM2\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/sound/Dual_YM3526_Sound.sv:207: Cannot find file containing module: 'SRAM_sync_noinit'\n    SRAM_sync_noinit #(.ADDR_WIDTH(11)) f1(.ADDR(A[10:0]), .clk(clk), .cen(~CS_RAMn), .we(~nWR), .DATA(cpu_dout), .Q(RAM_dout));\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/sound/Dual_YM3526_Sound.sv:234: Cannot find file containing module: 'ttl_74107a_sync'\n    ttl_74107a_sync #(.BLOCKS(1)) JK_YM3526_IRQ1ic (.Reset_n(VIDEO_RSTn), .CLRn(JK_YM1_ACK), .J(1'b1), .K(1'b0), .Clk(clk), .Cen(YM3526_IRQn1), .Q(JK_YM3526_IRQ1_STATUS), .Qn(JK_YM3526_IRQ1));\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/sound/Dual_YM3526_Sound.sv:235: Cannot find file containing module: 'ttl_74107a_sync'\n    ttl_74107a_sync #(.BLOCKS(1)) JK_YM3526_IRQ2ic (.Reset_n(VIDEO_RSTn), .CLRn(JK_YM2_ACK), .J(1'b1), .K(1'b0), .Clk(clk), .Cen(YM3526_IRQn2), .Q(JK_YM3526_IRQ2_STATUS), .Qn(JK_YM3526_IRQ2));\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/sound/Dual_YM3526_Sound.sv:242: Cannot find file containing module: 'DFF_pseudoAsyncClrPre2'\n    DFF_pseudoAsyncClrPre2 #(.W(1)) CPU_BUSY_IRQic (\n    ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/sound/Dual_YM3526_Sound.sv:253: Cannot find file containing module: 'DFF_pseudoAsyncClrPre2'\n     DFF_pseudoAsyncClrPre2 #(.W(1)) CMD_IRQic (\n     ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/500947188/rtl/sound/Dual_YM3526_Sound.sv:303: Cannot find file containing module: 'ttl_74273_sync'\n    ttl_74273_sync f8 (.RESETn(VIDEO_RSTn), .CLRn(DFF_CMD_IRQ_ACK), .Clk(clk), .Cen(MCODE), .D(vdin_r), .Q(F8_Q));\n    ^~~~~~~~~~~~~~\n%Error: Exiting due to 15 error(s)\n"
module Dual_YM3526_Sound
(
    input  wire VIDEO_RSTn,
    input  wire clk,
    input wire pause_cpu,
    input  wire CEN_p,
    input  wire CEN_n,
    input  wire RESETn,
    input  wire [7:0] data_in,

	input wire         [24:0] ioctl_addr,
	input wire         [7:0] ioctl_data,
	input wire         ioctl_wr,
    input  wire MCODE,
    output logic MS,

    output  wire signed [15:0] snd1,
    output  wire signed [15:0] snd2,
    output  wire sample
);
    logic [7:0] latch_din;



    logic nM1;
    logic nMREQ;
    logic nIORQ;
    logic nRD;
    logic nWR;
    logic nRFSH;
    logic nHALT;
    logic nBUSACK;

    logic nWAIT = 1'b1;
    logic nINT;
    logic nNMI = 1'b1;
    logic nBUSRQ = 1'b1;
    logic [15:0] A;

    logic  [7:0] cpu_din;
    logic  [7:0] cpu_dout;


    reg reset_n=1'b0;
    reg [4:0] rst_cnt;

    always @(negedge clk) begin
        if( ~RESETn ) begin
            rst_cnt <= 'd0;
            reset_n <= 1'b0;
        end else begin
            if( rst_cnt != ~5'b0 ) begin
                reset_n <= 1'b0;
                rst_cnt <= rst_cnt + 5'd1;
            end else reset_n <= 1'b1;
        end
    end


        T80pa z80_g2 (
        .RESET_n(RESETn),
        .CLK    (clk),
        .CEN_p  (CEN_p & ~pause_cpu),
        .CEN_n  (CEN_n & ~pause_cpu),

        .WAIT_n (1'b1),
        .INT_n  (nINT),
        .NMI_n  (1'b1),
        .RD_n   (nRD),
        .WR_n   (nWR),
        .A      (A),
        .DI     (cpu_din),
        .DO     (cpu_dout),
        .IORQ_n (nIORQ),
        .M1_n   (nM1),
        .MREQ_n (nMREQ),
        .BUSRQ_n(1'b1),
        .BUSAK_n(nBUSACK),
        .OUT0   (1'b0),
        .RFSH_n (nRFSH),
        .HALT_n (nHALT)
    );



    logic YM3526_IRQn1;
    logic YM3526_IRQn2;
    logic YM3526_CSn1, YM3526_RDn1, YM3526_WRn1;
    logic YM3526_CSn2, YM3526_RDn2, YM3526_WRn2;
    logic YM3526_RW1, YM3526_RW2;

    assign YM3526_CSn1 = YM3526_RW1;
    assign YM3526_RDn1 = YM3526_RW1 | nRD;
    assign YM3526_WRn1 = YM3526_RW1 | nWR;

    assign YM3526_CSn2 = YM3526_RW2;
    assign YM3526_RDn2 = YM3526_RW2 | nRD;
    assign YM3526_WRn2 = YM3526_RW2 | nWR;

    logic [7:0] ym3526_dout1;
    logic [7:0] ym3526_dout2;
    jtopl  YM3526_1
    (
        .rst(~RESETn),
        .clk(clk),
        .cen(CEN_p & ~pause_cpu),
        .din(cpu_dout),
        .addr(A[10]),
        .cs_n(YM3526_CSn1),
        .wr_n(YM3526_WRn1),
        .dout(ym3526_dout1),
        .irq_n(YM3526_IRQn1),

        .snd(snd1),
        .sample(sample)
    );

    jtopl  YM3526_2
    (
        .rst(~RESETn),
        .clk(clk),
        .cen(CEN_p & ~pause_cpu),
        .din(cpu_dout),
        .addr(A[10]),
        .cs_n(YM3526_CSn2),
        .wr_n(YM3526_WRn2),
        .dout(ym3526_dout2),
        .irq_n(YM3526_IRQn2),

        .snd(snd2),
        .sample()
    );


    logic CS_ROM_0n, CS_ROM_1n, CS_ROM_2n, CS_RAMn;

  
    logic F4_2_Y3n;
    ttl_74139_nodly F4_2(.Enable_bar(1'b0), .A_2D(A[15:14]), .Y_2D({F4_2_Y3n, CS_ROM_2n, CS_ROM_1n, CS_ROM_0n}));




    logic SOUND_STATUS, LATCH_MCODEn;
    logic F4_1_Gn;
    assign F4_1_Gn = F4_2_Y3n | (~A[13]);
    ttl_74139_nodly F4_1(.Enable_bar(F4_1_Gn), .A_2D(A[12:11]), .Y_2D({SOUND_STATUS,YM3526_RW2,YM3526_RW1,LATCH_MCODEn}));


    logic ROM0_cs, ROM1_cs, ROM2_cs;

    selector_dualYM3526_cpu_snd_rom ROM_Sel
    (.ioctl_addr(ioctl_addr), .ROM0_cs(ROM0_cs), .ROM1_cs(ROM1_cs), .ROM2_cs(ROM2_cs));

    logic [7:0] data_ROM0;
    logic [7:0] data_ROM1;
    logic [7:0] data_ROM2;

    eprom_16K ROM0
    (
        .ADDR(A[13:0]),
        .CLK(clk),
        .DATA(data_ROM0),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data),
        .CS_DL(ROM0_cs),
        .WR(ioctl_wr)
    );
    

    eprom_16K ROM1
    (
        .ADDR({A[13:0]}),
        .CLK(clk),
        .DATA(data_ROM1),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data),
        .CS_DL(ROM1_cs),
        .WR(ioctl_wr)
    );

    eprom_16K ROM2
    (
        .ADDR({A[13:0]}),
        .CLK(clk),
        .DATA(data_ROM2),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data),
        .CS_DL(ROM2_cs),
        .WR(ioctl_wr)
    );



    assign CS_RAMn = A[13] | F4_2_Y3n;
    logic [7:0] RAM_dout;
    SRAM_sync_noinit #(.ADDR_WIDTH(11)) f1(.ADDR(A[10:0]), .clk(clk), .cen(~CS_RAMn), .we(~nWR), .DATA(cpu_dout), .Q(RAM_dout));



    logic SOUND_STATUS_R, SOUND_STATUS_W;

    assign SOUND_STATUS_R = nRD | SOUND_STATUS;
    assign SOUND_STATUS_W = nWR | SOUND_STATUS;

    always @(posedge clk) begin
                 if(!CS_ROM_0n        && !nRD)                  cpu_din <= data_ROM0;
            else if(!CS_ROM_1n        && !nRD)                  cpu_din <= data_ROM1;
            else if(!CS_ROM_2n        && !nRD)                  cpu_din <= data_ROM2;
            else if(!CS_RAMn          && !nRD)                  cpu_din <= RAM_dout;
            else if(!LATCH_MCODEn     && !nRD)                  cpu_din <= latch_din;
            else if(!YM3526_CSn1      && !YM3526_RDn1)          cpu_din <= ym3526_dout1;
            else if(!YM3526_CSn2      && !YM3526_RDn2)          cpu_din <= ym3526_dout2;
            else if(!SOUND_STATUS_R)                            cpu_din <= {4'hf,STATUS_r};
            else                                                cpu_din <= 8'hFF;        

    end




    logic JK_YM1_ACK, JK_YM2_ACK;
    logic JK_YM3526_IRQ1_STATUS, JK_YM3526_IRQ1, JK_YM3526_IRQ2_STATUS, JK_YM3526_IRQ2;
    ttl_74107a_sync #(.BLOCKS(1)) JK_YM3526_IRQ1ic (.Reset_n(VIDEO_RSTn), .CLRn(JK_YM1_ACK), .J(1'b1), .K(1'b0), .Clk(clk), .Cen(YM3526_IRQn1), .Q(JK_YM3526_IRQ1_STATUS), .Qn(JK_YM3526_IRQ1));
    ttl_74107a_sync #(.BLOCKS(1)) JK_YM3526_IRQ2ic (.Reset_n(VIDEO_RSTn), .CLRn(JK_YM2_ACK), .J(1'b1), .K(1'b0), .Clk(clk), .Cen(YM3526_IRQn2), .Q(JK_YM3526_IRQ2_STATUS), .Qn(JK_YM3526_IRQ2));
    
    logic DFF_CPU_BUSY_ACK;
    logic DFF_CMD_IRQ_ACK;
    logic CPU_BUSY, CMD_IRQ;
    logic CPU_BUSY_STATUS, CMD_IRQ_STATUS;

    DFF_pseudoAsyncClrPre2 #(.W(1)) CPU_BUSY_IRQic (
        .clk(clk),
        .rst(~VIDEO_RSTn),
        .din(1'b1),
        .q(CPU_BUSY_STATUS),
        .qn(CPU_BUSY),
        .set(1'b0),
        .clr(~DFF_CPU_BUSY_ACK),
        .cen(MCODE) 
    );

     DFF_pseudoAsyncClrPre2 #(.W(1)) CMD_IRQic (
        .clk(clk),
        .rst(~VIDEO_RSTn),
        .din(1'b1),
        .q(CMD_IRQ_STATUS),
        .qn(CMD_IRQ),
        .set(1'b0),
        .clr(~DFF_CMD_IRQ_ACK),
        .cen(MCODE) 
    );

    assign nINT = (JK_YM3526_IRQ1 & JK_YM3526_IRQ2 & CPU_BUSY & CMD_IRQ);

















    assign {DFF_CMD_IRQ_ACK,DFF_CPU_BUSY_ACK,JK_YM2_ACK,JK_YM1_ACK} = (!SOUND_STATUS_W) ? cpu_dout[7:4] : 4'hf;

    assign MS = CPU_BUSY_STATUS;


    logic [3:0] STATUS_r;
    always @(posedge clk) begin
        if (!SOUND_STATUS_R) STATUS_r <= {CMD_IRQ_STATUS, CPU_BUSY_STATUS, JK_YM3526_IRQ2_STATUS, JK_YM3526_IRQ1_STATUS};
        else                 STATUS_r <= 4'hf;      
    end




    reg [7:0] vdin_r;
    always @(posedge clk) begin
        if(!VIDEO_RSTn) vdin_r <= 8'b0;
        else vdin_r <= data_in;
    end

    logic [7:0] F8_Q;
    ttl_74273_sync f8 (.RESETn(VIDEO_RSTn), .CLRn(DFF_CMD_IRQ_ACK), .Clk(clk), .Cen(MCODE), .D(vdin_r), .Q(F8_Q));






   
    always @(posedge clk) begin
        if(!LATCH_MCODEn) latch_din <= F8_Q;
        else              latch_din <= 8'hFF;
    end     

endmodule
module Dual_YM3526_Sound
(
    input  wire VIDEO_RSTn,
    input  wire clk,
    input wire pause_cpu,
    input  wire CEN_p,
    input  wire CEN_n,
    input  wire RESETn,
    input  wire [7:0] data_in,

	input wire         [24:0] ioctl_addr,
	input wire         [7:0] ioctl_data,
	input wire         ioctl_wr,
    input  wire MCODE,
    output logic MS,

    output  wire signed [15:0] snd1,
    output  wire signed [15:0] snd2,
    output  wire sample
);

    logic [7:0] latch_din;



    logic nM1;
    logic nMREQ;
    logic nIORQ;
    logic nRD;
    logic nWR;
    logic nRFSH;
    logic nHALT;
    logic nBUSACK;

    logic nWAIT = 1'b1;
    logic nINT;
    logic nNMI = 1'b1;
    logic nBUSRQ = 1'b1;
    logic [15:0] A;

    logic  [7:0] cpu_din;
    logic  [7:0] cpu_dout;


    reg reset_n=1'b0;
    reg [4:0] rst_cnt;

    always @(negedge clk) begin
        if( ~RESETn ) begin
            rst_cnt <= 'd0;
            reset_n <= 1'b0;
        end else begin
            if( rst_cnt != ~5'b0 ) begin
                reset_n <= 1'b0;
                rst_cnt <= rst_cnt + 5'd1;
            end else reset_n <= 1'b1;
        end
    end


        T80pa z80_g2 (
        .RESET_n(RESETn),
        .CLK    (clk),
        .CEN_p  (CEN_p & ~pause_cpu),
        .CEN_n  (CEN_n & ~pause_cpu),

        .WAIT_n (1'b1),
        .INT_n  (nINT),
        .NMI_n  (1'b1),
        .RD_n   (nRD),
        .WR_n   (nWR),
        .A      (A),
        .DI     (cpu_din),
        .DO     (cpu_dout),
        .IORQ_n (nIORQ),
        .M1_n   (nM1),
        .MREQ_n (nMREQ),
        .BUSRQ_n(1'b1),
        .BUSAK_n(nBUSACK),
        .OUT0   (1'b0),
        .RFSH_n (nRFSH),
        .HALT_n (nHALT)
    );



    logic YM3526_IRQn1;
    logic YM3526_IRQn2;
    logic YM3526_CSn1, YM3526_RDn1, YM3526_WRn1;
    logic YM3526_CSn2, YM3526_RDn2, YM3526_WRn2;
    logic YM3526_RW1, YM3526_RW2;

    assign YM3526_CSn1 = YM3526_RW1;
    assign YM3526_RDn1 = YM3526_RW1 | nRD;
    assign YM3526_WRn1 = YM3526_RW1 | nWR;

    assign YM3526_CSn2 = YM3526_RW2;
    assign YM3526_RDn2 = YM3526_RW2 | nRD;
    assign YM3526_WRn2 = YM3526_RW2 | nWR;

    logic [7:0] ym3526_dout1;
    logic [7:0] ym3526_dout2;
    jtopl  YM3526_1
    (
        .rst(~RESETn),
        .clk(clk),
        .cen(CEN_p & ~pause_cpu),
        .din(cpu_dout),
        .addr(A[10]),
        .cs_n(YM3526_CSn1),
        .wr_n(YM3526_WRn1),
        .dout(ym3526_dout1),
        .irq_n(YM3526_IRQn1),

        .snd(snd1),
        .sample(sample)
    );

    jtopl  YM3526_2
    (
        .rst(~RESETn),
        .clk(clk),
        .cen(CEN_p & ~pause_cpu),
        .din(cpu_dout),
        .addr(A[10]),
        .cs_n(YM3526_CSn2),
        .wr_n(YM3526_WRn2),
        .dout(ym3526_dout2),
        .irq_n(YM3526_IRQn2),

        .snd(snd2),
        .sample()
    );


    logic CS_ROM_0n, CS_ROM_1n, CS_ROM_2n, CS_RAMn;

  
    logic F4_2_Y3n;
    ttl_74139_nodly F4_2(.Enable_bar(1'b0), .A_2D(A[15:14]), .Y_2D({F4_2_Y3n, CS_ROM_2n, CS_ROM_1n, CS_ROM_0n}));




    logic SOUND_STATUS, LATCH_MCODEn;
    logic F4_1_Gn;
    assign F4_1_Gn = F4_2_Y3n | (~A[13]);
    ttl_74139_nodly F4_1(.Enable_bar(F4_1_Gn), .A_2D(A[12:11]), .Y_2D({SOUND_STATUS,YM3526_RW2,YM3526_RW1,LATCH_MCODEn}));


    logic ROM0_cs, ROM1_cs, ROM2_cs;

    selector_dualYM3526_cpu_snd_rom ROM_Sel
    (.ioctl_addr(ioctl_addr), .ROM0_cs(ROM0_cs), .ROM1_cs(ROM1_cs), .ROM2_cs(ROM2_cs));

    logic [7:0] data_ROM0;
    logic [7:0] data_ROM1;
    logic [7:0] data_ROM2;

    eprom_16K ROM0
    (
        .ADDR(A[13:0]),
        .CLK(clk),
        .DATA(data_ROM0),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data),
        .CS_DL(ROM0_cs),
        .WR(ioctl_wr)
    );
    

    eprom_16K ROM1
    (
        .ADDR({A[13:0]}),
        .CLK(clk),
        .DATA(data_ROM1),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data),
        .CS_DL(ROM1_cs),
        .WR(ioctl_wr)
    );

    eprom_16K ROM2
    (
        .ADDR({A[13:0]}),
        .CLK(clk),
        .DATA(data_ROM2),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data),
        .CS_DL(ROM2_cs),
        .WR(ioctl_wr)
    );



    assign CS_RAMn = A[13] | F4_2_Y3n;
    logic [7:0] RAM_dout;
    SRAM_sync_noinit #(.ADDR_WIDTH(11)) f1(.ADDR(A[10:0]), .clk(clk), .cen(~CS_RAMn), .we(~nWR), .DATA(cpu_dout), .Q(RAM_dout));



    logic SOUND_STATUS_R, SOUND_STATUS_W;

    assign SOUND_STATUS_R = nRD | SOUND_STATUS;
    assign SOUND_STATUS_W = nWR | SOUND_STATUS;

    always @(posedge clk) begin
                 if(!CS_ROM_0n        && !nRD)                  cpu_din <= data_ROM0;
            else if(!CS_ROM_1n        && !nRD)                  cpu_din <= data_ROM1;
            else if(!CS_ROM_2n        && !nRD)                  cpu_din <= data_ROM2;
            else if(!CS_RAMn          && !nRD)                  cpu_din <= RAM_dout;
            else if(!LATCH_MCODEn     && !nRD)                  cpu_din <= latch_din;
            else if(!YM3526_CSn1      && !YM3526_RDn1)          cpu_din <= ym3526_dout1;
            else if(!YM3526_CSn2      && !YM3526_RDn2)          cpu_din <= ym3526_dout2;
            else if(!SOUND_STATUS_R)                            cpu_din <= {4'hf,STATUS_r};
            else                                                cpu_din <= 8'hFF;        

    end




    logic JK_YM1_ACK, JK_YM2_ACK;
    logic JK_YM3526_IRQ1_STATUS, JK_YM3526_IRQ1, JK_YM3526_IRQ2_STATUS, JK_YM3526_IRQ2;
    ttl_74107a_sync #(.BLOCKS(1)) JK_YM3526_IRQ1ic (.Reset_n(VIDEO_RSTn), .CLRn(JK_YM1_ACK), .J(1'b1), .K(1'b0), .Clk(clk), .Cen(YM3526_IRQn1), .Q(JK_YM3526_IRQ1_STATUS), .Qn(JK_YM3526_IRQ1));
    ttl_74107a_sync #(.BLOCKS(1)) JK_YM3526_IRQ2ic (.Reset_n(VIDEO_RSTn), .CLRn(JK_YM2_ACK), .J(1'b1), .K(1'b0), .Clk(clk), .Cen(YM3526_IRQn2), .Q(JK_YM3526_IRQ2_STATUS), .Qn(JK_YM3526_IRQ2));
    
    logic DFF_CPU_BUSY_ACK;
    logic DFF_CMD_IRQ_ACK;
    logic CPU_BUSY, CMD_IRQ;
    logic CPU_BUSY_STATUS, CMD_IRQ_STATUS;

    DFF_pseudoAsyncClrPre2 #(.W(1)) CPU_BUSY_IRQic (
        .clk(clk),
        .rst(~VIDEO_RSTn),
        .din(1'b1),
        .q(CPU_BUSY_STATUS),
        .qn(CPU_BUSY),
        .set(1'b0),
        .clr(~DFF_CPU_BUSY_ACK),
        .cen(MCODE) 
    );

     DFF_pseudoAsyncClrPre2 #(.W(1)) CMD_IRQic (
        .clk(clk),
        .rst(~VIDEO_RSTn),
        .din(1'b1),
        .q(CMD_IRQ_STATUS),
        .qn(CMD_IRQ),
        .set(1'b0),
        .clr(~DFF_CMD_IRQ_ACK),
        .cen(MCODE) 
    );

    assign nINT = (JK_YM3526_IRQ1 & JK_YM3526_IRQ2 & CPU_BUSY & CMD_IRQ);

















    assign {DFF_CMD_IRQ_ACK,DFF_CPU_BUSY_ACK,JK_YM2_ACK,JK_YM1_ACK} = (!SOUND_STATUS_W) ? cpu_dout[7:4] : 4'hf;

    assign MS = CPU_BUSY_STATUS;


    logic [3:0] STATUS_r;
    always @(posedge clk) begin
        if (!SOUND_STATUS_R) STATUS_r <= {CMD_IRQ_STATUS, CPU_BUSY_STATUS, JK_YM3526_IRQ2_STATUS, JK_YM3526_IRQ1_STATUS};
        else                 STATUS_r <= 4'hf;      
    end




    reg [7:0] vdin_r;
    always @(posedge clk) begin
        if(!VIDEO_RSTn) vdin_r <= 8'b0;
        else vdin_r <= data_in;
    end

    logic [7:0] F8_Q;
    ttl_74273_sync f8 (.RESETn(VIDEO_RSTn), .CLRn(DFF_CMD_IRQ_ACK), .Clk(clk), .Cen(MCODE), .D(vdin_r), .Q(F8_Q));






   
    always @(posedge clk) begin
        if(!LATCH_MCODEn) latch_din <= F8_Q;
        else              latch_din <= 8'hFF;
    end     

endmodule