data/full_repos/permissive/410272426/hardware_code_radix-4/tb_top.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/410272426/hardware_code_radix-4/tb_top.v:38: Unsupported: Ignoring delay on this delayed statement.\n    forever #5 clk=~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/410272426/hardware_code_radix-4/tb_top.v:63: Unsupported: Ignoring delay on this delayed statement.\n    # 7 rst = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/410272426/hardware_code_radix-4/tb_top.v:64: Unsupported: Ignoring delay on this delayed statement.\n    # 2 conf = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/410272426/hardware_code_radix-4/tb_top.v:65: Unsupported: Ignoring delay on this delayed statement.\n    # 12801 conf = 4;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/410272426/hardware_code_radix-4/tb_top.v:66: Unsupported: Ignoring delay on this delayed statement.\n    # 250 conf = 3;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/410272426/hardware_code_radix-4/tb_top.v:67: Unsupported: Ignoring delay on this delayed statement.\n    # 12801 conf = 5;\n    ^\n%Error: data/full_repos/permissive/410272426/hardware_code_radix-4/tb_top.v:75: Can\'t find definition of \'bank_0\' in dotted scope/variable: \'tb_top.poly_mul.bank_0\'\n     $readmemb("D:/Xilinx_project/scalable_ntt/radix4_ntt_ring/radix4_ntt_ring_1024p/bank0.txt",tb_top.poly_mul.bank_0.bank);\n                                                                                                                ^~~~~~\n        ... Known scopes under \'tb_top.poly_mul\': <no cells found>\n%Error: data/full_repos/permissive/410272426/hardware_code_radix-4/tb_top.v:76: Can\'t find definition of \'bank_1\' in dotted scope/variable: \'tb_top.poly_mul.bank_1\'\n     $readmemb("D:/Xilinx_project/scalable_ntt/radix4_ntt_ring/radix4_ntt_ring_1024p/bank1.txt",tb_top.poly_mul.bank_1.bank);\n                                                                                                                ^~~~~~\n        ... Known scopes under \'tb_top.poly_mul\': <no cells found>\n%Error: data/full_repos/permissive/410272426/hardware_code_radix-4/tb_top.v:77: Can\'t find definition of \'bank_2\' in dotted scope/variable: \'tb_top.poly_mul.bank_2\'\n     $readmemb("D:/Xilinx_project/scalable_ntt/radix4_ntt_ring/radix4_ntt_ring_1024p/bank2.txt",tb_top.poly_mul.bank_2.bank);\n                                                                                                                ^~~~~~\n        ... Known scopes under \'tb_top.poly_mul\': <no cells found>\n%Error: data/full_repos/permissive/410272426/hardware_code_radix-4/tb_top.v:78: Can\'t find definition of \'bank_3\' in dotted scope/variable: \'tb_top.poly_mul.bank_3\'\n     $readmemb("D:/Xilinx_project/scalable_ntt/radix4_ntt_ring/radix4_ntt_ring_1024p/bank3.txt",tb_top.poly_mul.bank_3.bank);\n                                                                                                                ^~~~~~\n        ... Known scopes under \'tb_top.poly_mul\': <no cells found>\n%Error: data/full_repos/permissive/410272426/hardware_code_radix-4/tb_top.v:79: Can\'t find definition of \'rom0\' in dotted scope/variable: \'tb_top.poly_mul.rom0\'\n     $readmemb("D:/Xilinx_project/scalable_ntt/radix4_ntt_ring/radix4_ntt_ring_1024p/w_ROM.txt",tb_top.poly_mul.rom0.ROM);\n                                                                                                                ^~~~\n        ... Known scopes under \'tb_top.poly_mul\': <no cells found>\n%Error: Exiting due to 5 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_top;
  reg clk,rst;
  reg [2:0] conf;
  wire [2:0] done_flag;
  parameter data_width = 14;
  
  top_poly_mul poly_mul(
      .clk(clk),.rst(rst),
      .conf(conf),
      .done_flag(done_flag)
      );
      
  initial
  begin
    clk=1'b0;
    forever #5 clk=~clk;
  end
  

  
  initial 
  begin
    conf = 0;
    rst = 1;
    # 7 rst = 0;
    # 2 conf = 1;
    # 12801 conf = 4;
    # 250 conf = 3;
    # 12801 conf = 5;
  end
  

   
  initial
  begin 
     $readmemb("D:/Xilinx_project/scalable_ntt/radix4_ntt_ring/radix4_ntt_ring_1024p/bank0.txt",tb_top.poly_mul.bank_0.bank);
     $readmemb("D:/Xilinx_project/scalable_ntt/radix4_ntt_ring/radix4_ntt_ring_1024p/bank1.txt",tb_top.poly_mul.bank_1.bank);
     $readmemb("D:/Xilinx_project/scalable_ntt/radix4_ntt_ring/radix4_ntt_ring_1024p/bank2.txt",tb_top.poly_mul.bank_2.bank);
     $readmemb("D:/Xilinx_project/scalable_ntt/radix4_ntt_ring/radix4_ntt_ring_1024p/bank3.txt",tb_top.poly_mul.bank_3.bank);
     $readmemb("D:/Xilinx_project/scalable_ntt/radix4_ntt_ring/radix4_ntt_ring_1024p/w_ROM.txt",tb_top.poly_mul.rom0.ROM);
  end
   
 endmodule
module tb_top;

  reg clk,rst;
  reg [2:0] conf;
  wire [2:0] done_flag;
  parameter data_width = 14;
  
  top_poly_mul poly_mul(
      .clk(clk),.rst(rst),
      .conf(conf),
      .done_flag(done_flag)
      );
      
  initial
  begin
    clk=1'b0;
    forever #5 clk=~clk;
  end
  

  
  initial 
  begin
    conf = 0;
    rst = 1;
    # 7 rst = 0;
    # 2 conf = 1;
    # 12801 conf = 4;
    # 250 conf = 3;
    # 12801 conf = 5;
  end
  

   
  initial
  begin 
     $readmemb("D:/Xilinx_project/scalable_ntt/radix4_ntt_ring/radix4_ntt_ring_1024p/bank0.txt",tb_top.poly_mul.bank_0.bank);
     $readmemb("D:/Xilinx_project/scalable_ntt/radix4_ntt_ring/radix4_ntt_ring_1024p/bank1.txt",tb_top.poly_mul.bank_1.bank);
     $readmemb("D:/Xilinx_project/scalable_ntt/radix4_ntt_ring/radix4_ntt_ring_1024p/bank2.txt",tb_top.poly_mul.bank_2.bank);
     $readmemb("D:/Xilinx_project/scalable_ntt/radix4_ntt_ring/radix4_ntt_ring_1024p/bank3.txt",tb_top.poly_mul.bank_3.bank);
     $readmemb("D:/Xilinx_project/scalable_ntt/radix4_ntt_ring/radix4_ntt_ring_1024p/w_ROM.txt",tb_top.poly_mul.rom0.ROM);
  end
   
 endmodule