data/full_repos/permissive/475644481/sources/new/Seven_Segment_Decoder.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/475644481/sources/new/Seven_Segment_Decoder.v:25: Little bit endian vector: MSB < LSB of bit range: 0:3\ninput [0:3]E,\n      ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Seven_Segment_Decoder(

input [0:3]E,
output SA,SB,SC,SD,SE,SF,SG
    );


    wire a,b;
    and (a,~E[1],~E[3]);
    and(b,E[1],E[3]);
    or(SA,E[0],E[2],a,b);
    

    wire c,d;
    and(c,~E[2],~E[3]);
    and(d,E[2],E[3]);
    or(SB,~E[1],c,d);
    

    or(SC,E[1],~E[2],E[3]);
    

    wire e,f,g,h;
    and(e,~E[1],~E[3]);
    and(f,~E[1],E[2]);
    and(g,E[2],~E[3]);
    and(h,E[1],~E[2],E[3]);
    or(SD,e,f,g,h);
    

    wire i,j;
    and(i,~E[1],~E[3]);
    and(j,E[2],~E[3]);
    or(SE,i,j);
    

    wire k,l,m;
    and(k,~E[2],~E[3]);
    and(l,E[1],~E[2]);
    and(m,E[1],~E[3]);
    or(SF,E[0],k,l,m);
    

    wire n,o,p;
    and(n,~E[1],E[2]);
    and(o,E[2],~E[3]);
    and(p,E[1],~E[2]);
    or(SG,E[0],n,o,p);
endmodule
module Seven_Segment_Decoder(

input [0:3]E,
output SA,SB,SC,SD,SE,SF,SG
    );



    wire a,b;
    and (a,~E[1],~E[3]);
    and(b,E[1],E[3]);
    or(SA,E[0],E[2],a,b);
    

    wire c,d;
    and(c,~E[2],~E[3]);
    and(d,E[2],E[3]);
    or(SB,~E[1],c,d);
    

    or(SC,E[1],~E[2],E[3]);
    

    wire e,f,g,h;
    and(e,~E[1],~E[3]);
    and(f,~E[1],E[2]);
    and(g,E[2],~E[3]);
    and(h,E[1],~E[2],E[3]);
    or(SD,e,f,g,h);
    

    wire i,j;
    and(i,~E[1],~E[3]);
    and(j,E[2],~E[3]);
    or(SE,i,j);
    

    wire k,l,m;
    and(k,~E[2],~E[3]);
    and(l,E[1],~E[2]);
    and(m,E[1],~E[3]);
    or(SF,E[0],k,l,m);
    

    wire n,o,p;
    and(n,~E[1],E[2]);
    and(o,E[2],~E[3]);
    and(p,E[1],~E[2]);
    or(SG,E[0],n,o,p);
endmodule