data/full_repos/permissive/425529933/Proyecto1Digitales2/phy/phy_e.v
data/verilator_xmls/48a23935-edb4-47cd-985d-3864d06e071d.xml
module phy_tx_e(clk_32f, clk_2f_e, clk_4f_e, reset, valid_in, Data_in, Data_out_1bit_0_c, Data_out_1bit_1_c);
  (* src = "phy_tx_e.v:30" *)
  reg _0_;
  (* src = "phy_tx_e.v:30" *)
  reg _1_;
  (* src = "phy_tx_e.v:11" *)
  input [31:0] Data_in;
  (* src = "phy_tx_e.v:24" *)
  wire [7:0] Data_out_0_c;
  (* src = "phy_tx_e.v:26" *)
  wire [7:0] Data_out_1_c;
  (* src = "phy_tx_e.v:12" *)
  output Data_out_1bit_0_c;
  reg Data_out_1bit_0_c;
  (* src = "phy_tx_e.v:13" *)
  output Data_out_1bit_1_c;
  reg Data_out_1bit_1_c;
  (* src = "phy_tx_e.v:27" *)
  wire Out_0_c;
  (* src = "phy_tx_e.v:28" *)
  wire Out_1_c;
  (* src = "phy_tx_e.v:7" *)
  input clk_2f_e;
  (* src = "phy_tx_e.v:6" *)
  input clk_32f;
  (* src = "phy_tx_e.v:8" *)
  input clk_4f_e;
  (* src = "phy_tx_e.v:20" *)
  wire [31:0] lane_0_c;
  (* src = "phy_tx_e.v:22" *)
  wire [31:0] lane_1_c;
  (* src = "phy_tx_e.v:9" *)
  input reset;
  (* src = "phy_tx_e.v:19" *)
  wire valid_0_c;
  (* src = "phy_tx_e.v:21" *)
  wire valid_1_c;
  (* src = "phy_tx_e.v:10" *)
  input valid_in;
  (* src = "phy_tx_e.v:23" *)
  wire valid_out_0_c;
  (* src = "phy_tx_e.v:25" *)
  wire valid_out_1_c;
  (* module_not_derived = 32'd1 *)
  (* src = "phy_tx_e.v:35" *)
  byte_striping_e byte_striping_1 (
    .Data_in(Data_in),
    .clk_2f_e(clk_2f_e),
    .lane_0_c(lane_0_c),
    .lane_1_c(lane_1_c),
    .reset(reset),
    .valid_0_c(valid_0_c),
    .valid_1_c(valid_1_c),
    .valid_in(valid_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "phy_tx_e.v:70" *)
  parallel_serial_e parallel_serial_e1 (
    .Data_in(Data_out_0_c),
    .Data_out_e(Out_0_c),
    .clk_32f(clk_32f),
    .reset(reset),
    .valid_in(valid_out_0_c)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "phy_tx_e.v:80" *)
  parallel_serial_e parallel_serial_e2 (
    .Data_in(Data_out_1_c),
    .Data_out_e(Out_1_c),
    .clk_32f(clk_32f),
    .reset(reset),
    .valid_in(valid_out_1_c)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "phy_tx_e.v:48" *)
  word32_8bits_e word32_8bits_1 (
    .Data_in(lane_0_c),
    .Data_out_e(Data_out_0_c),
    .clk_4f_e(clk_4f_e),
    .reset(reset),
    .valid_in(valid_0_c),
    .valid_out_e(valid_out_0_c)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "phy_tx_e.v:59" *)
  word32_8bits_e word32_8bits_2 (
    .Data_in(lane_1_c),
    .Data_out_e(Data_out_1_c),
    .clk_4f_e(clk_4f_e),
    .reset(reset),
    .valid_in(valid_1_c),
    .valid_out_e(valid_out_1_c)
  );
  always @* begin
    _0_ = Out_0_c;
    _1_ = Out_1_c;
  end
  always @* begin
      Data_out_1bit_0_c <= _0_;
      Data_out_1bit_1_c <= _1_;
  end
endmodule
module phy_tx_e(clk_32f, clk_2f_e, clk_4f_e, reset, valid_in, Data_in, Data_out_1bit_0_c, Data_out_1bit_1_c);

  (* src = "phy_tx_e.v:30" *)
  reg _0_;
  (* src = "phy_tx_e.v:30" *)
  reg _1_;
  (* src = "phy_tx_e.v:11" *)
  input [31:0] Data_in;
  (* src = "phy_tx_e.v:24" *)
  wire [7:0] Data_out_0_c;
  (* src = "phy_tx_e.v:26" *)
  wire [7:0] Data_out_1_c;
  (* src = "phy_tx_e.v:12" *)
  output Data_out_1bit_0_c;
  reg Data_out_1bit_0_c;
  (* src = "phy_tx_e.v:13" *)
  output Data_out_1bit_1_c;
  reg Data_out_1bit_1_c;
  (* src = "phy_tx_e.v:27" *)
  wire Out_0_c;
  (* src = "phy_tx_e.v:28" *)
  wire Out_1_c;
  (* src = "phy_tx_e.v:7" *)
  input clk_2f_e;
  (* src = "phy_tx_e.v:6" *)
  input clk_32f;
  (* src = "phy_tx_e.v:8" *)
  input clk_4f_e;
  (* src = "phy_tx_e.v:20" *)
  wire [31:0] lane_0_c;
  (* src = "phy_tx_e.v:22" *)
  wire [31:0] lane_1_c;
  (* src = "phy_tx_e.v:9" *)
  input reset;
  (* src = "phy_tx_e.v:19" *)
  wire valid_0_c;
  (* src = "phy_tx_e.v:21" *)
  wire valid_1_c;
  (* src = "phy_tx_e.v:10" *)
  input valid_in;
  (* src = "phy_tx_e.v:23" *)
  wire valid_out_0_c;
  (* src = "phy_tx_e.v:25" *)
  wire valid_out_1_c;
  (* module_not_derived = 32'd1 *)
  (* src = "phy_tx_e.v:35" *)
  byte_striping_e byte_striping_1 (
    .Data_in(Data_in),
    .clk_2f_e(clk_2f_e),
    .lane_0_c(lane_0_c),
    .lane_1_c(lane_1_c),
    .reset(reset),
    .valid_0_c(valid_0_c),
    .valid_1_c(valid_1_c),
    .valid_in(valid_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "phy_tx_e.v:70" *)
  parallel_serial_e parallel_serial_e1 (
    .Data_in(Data_out_0_c),
    .Data_out_e(Out_0_c),
    .clk_32f(clk_32f),
    .reset(reset),
    .valid_in(valid_out_0_c)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "phy_tx_e.v:80" *)
  parallel_serial_e parallel_serial_e2 (
    .Data_in(Data_out_1_c),
    .Data_out_e(Out_1_c),
    .clk_32f(clk_32f),
    .reset(reset),
    .valid_in(valid_out_1_c)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "phy_tx_e.v:48" *)
  word32_8bits_e word32_8bits_1 (
    .Data_in(lane_0_c),
    .Data_out_e(Data_out_0_c),
    .clk_4f_e(clk_4f_e),
    .reset(reset),
    .valid_in(valid_0_c),
    .valid_out_e(valid_out_0_c)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "phy_tx_e.v:59" *)
  word32_8bits_e word32_8bits_2 (
    .Data_in(lane_1_c),
    .Data_out_e(Data_out_1_c),
    .clk_4f_e(clk_4f_e),
    .reset(reset),
    .valid_in(valid_1_c),
    .valid_out_e(valid_out_1_c)
  );
  always @* begin
    _0_ = Out_0_c;
    _1_ = Out_1_c;
  end
  always @* begin
      Data_out_1bit_0_c <= _0_;
      Data_out_1bit_1_c <= _1_;
  end
endmodule