data/full_repos/permissive/527176783/Single/A_Single/PC.v
data/verilator_xmls/a3d7375c-b8b3-45e0-9872-4ebb57d6ace0.xml
module PC(
    input               clk,
    input               rst_n,
    input       [31:0]  next_pc,
    output  reg [31:0]  pc
);


    always @(posedge clk, negedge rst_n) begin
        if(~rst_n)
            pc <= 32'd0;
        else
            pc <= next_pc;
    end

endmodule
module PC(
    input               clk,
    input               rst_n,
    input       [31:0]  next_pc,
    output  reg [31:0]  pc
);



    always @(posedge clk, negedge rst_n) begin
        if(~rst_n)
            pc <= 32'd0;
        else
            pc <= next_pc;
    end

endmodule