data/full_repos/permissive/514217463/core/rtl/sense_switch.v
data/verilator_xmls/59efa601-2ffa-4e57-921a-a143c3f19427.xml
module sense_switch(
  input clk,
  input rd,
  input [7:0] switch_settings,
  output reg [7:0] data_out
);
  
  always @(posedge clk)
    begin
	  if (rd)
	  begin
		 data_out <= switch_settings;
	  end
    end
endmodule
module sense_switch(
  input clk,
  input rd,
  input [7:0] switch_settings,
  output reg [7:0] data_out
);

  
  always @(posedge clk)
    begin
	  if (rd)
	  begin
		 data_out <= switch_settings;
	  end
    end
endmodule