data/full_repos/permissive/432564927/Lab1 (Verilog)/posEdgeDFFTest.v
1: b'%Error: Cannot find file containing module: (Verilog),data/full_repos/permissive/432564927\n        ... Looked in:\n             data/full_repos/permissive/432564927/Lab1/(Verilog),data/full_repos/permissive/432564927\n             data/full_repos/permissive/432564927/Lab1/(Verilog),data/full_repos/permissive/432564927.v\n             data/full_repos/permissive/432564927/Lab1/(Verilog),data/full_repos/permissive/432564927.sv\n             (Verilog),data/full_repos/permissive/432564927\n             (Verilog),data/full_repos/permissive/432564927.v\n             (Verilog),data/full_repos/permissive/432564927.sv\n             obj_dir/(Verilog),data/full_repos/permissive/432564927\n             obj_dir/(Verilog),data/full_repos/permissive/432564927.v\n             obj_dir/(Verilog),data/full_repos/permissive/432564927.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/432564927/Lab1\n%Error: Cannot find file containing module: (Verilog)/posEdgeDFFTest.v\n%Error: Exiting due to 3 error(s)\n'
module posEdgeDFFTest;

    reg D;
    reg clk;
    reg reset;

    wire Q;
    
    posEdgeDFFwCLRN uut(D,clk,reset,Q);
    initial begin
        clk = 0;
            forever #10 clk = ~clk;
    end
    initial begin
        reset=1;
        D <= 0;
        #100;
        reset=0;
        D <= 1;
        #100;
        D <= 0;
        #100;
        D <=1;
    end
endmodule
module posEdgeDFFTest;


    reg D;
    reg clk;
    reg reset;

    wire Q;
    
    posEdgeDFFwCLRN uut(D,clk,reset,Q);
    initial begin
        clk = 0;
            forever #10 clk = ~clk;
    end
    initial begin
        reset=1;
        D <= 0;
        #100;
        reset=0;
        D <= 1;
        #100;
        D <= 0;
        #100;
        D <=1;
    end
endmodule