data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Counters/Count_clock_1/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Counters/Count_clock_1,data/full_repos/permissive/500128826\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/Count_clock_1,data/full_repos/permissive/500128826\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/Count_clock_1,data/full_repos/permissive/500128826.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/Count_clock_1,data/full_repos/permissive/500128826.sv\n             Logic/Counters/Count_clock_1,data/full_repos/permissive/500128826\n             Logic/Counters/Count_clock_1,data/full_repos/permissive/500128826.v\n             Logic/Counters/Count_clock_1,data/full_repos/permissive/500128826.sv\n             obj_dir/Logic/Counters/Count_clock_1,data/full_repos/permissive/500128826\n             obj_dir/Logic/Counters/Count_clock_1,data/full_repos/permissive/500128826.v\n             obj_dir/Logic/Counters/Count_clock_1,data/full_repos/permissive/500128826.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Logic/Counters/Count_clock_1/top_module.v\n%Error: Exiting due to 3 error(s)\n'
module bcdcount24h (
    input wire clk,
    input wire reset,
    input wire enable,
    output reg [23:0] Q
);

  always @(posedge clk) begin
    if (reset) Q = 24'h0;
    else if (enable) begin

      if (Q[23:0] == 24'h235959) Q <= 24'h0;
      else if (Q[19:0] == 20'h95959) Q <= Q + 20'h6A6A7;


      else if (Q[15:0] == 16'h5959) Q <= Q + 16'hA6A7;
      else if (Q[11:0] == 12'h959) Q <= Q + 12'h6A7;


      else if (Q[7:0] == 8'h59) Q <= Q + 8'hA7;
      else if (Q[3:0] == 4'h9) Q <= Q + 4'h7;

      else Q <= Q + 1'h1;
    end
  end

endmodule
module bcdcount24h (
    input wire clk,
    input wire reset,
    input wire enable,
    output reg [23:0] Q
);


  always @(posedge clk) begin
    if (reset) Q = 24'h0;
    else if (enable) begin

      if (Q[23:0] == 24'h235959) Q <= 24'h0;
      else if (Q[19:0] == 20'h95959) Q <= Q + 20'h6A6A7;


      else if (Q[15:0] == 16'h5959) Q <= Q + 16'hA6A7;
      else if (Q[11:0] == 12'h959) Q <= Q + 12'h6A7;


      else if (Q[7:0] == 8'h59) Q <= Q + 8'hA7;
      else if (Q[3:0] == 4'h9) Q <= Q + 4'h7;

      else Q <= Q + 1'h1;
    end
  end

endmodule