data/full_repos/permissive/508059792/mux.v
data/verilator_xmls/e2f40111-0432-4e0f-a662-ef340801d866.xml
module mux(sel, ina, inb, out);

parameter DATA_LENGTH = 8;

input sel;
input [DATA_LENGTH-1 : 0] ina; 
input [(DATA_LENGTH-1) : 0]  inb;
output [DATA_LENGTH-1 : 0] out;

assign out=(sel==0)?ina:inb;

endmodule
module mux(sel, ina, inb, out);


parameter DATA_LENGTH = 8;

input sel;
input [DATA_LENGTH-1 : 0] ina; 
input [(DATA_LENGTH-1) : 0]  inb;
output [DATA_LENGTH-1 : 0] out;

assign out=(sel==0)?ina:inb;

endmodule