data/full_repos/permissive/496266817/tb/tb_scrypt.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/496266817/tb/tb_scrypt.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #0 clk = 1\'b0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/496266817/tb/tb_scrypt.v:29: Unsupported: Ignoring delay on this delayed statement.\n initial forever #(CLK_PULSE) clk = ~clk;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/496266817/tb/tb_scrypt.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #0 start =1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/496266817/tb/tb_scrypt.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #0 out_ready =1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/496266817/tb/tb_scrypt.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #0 valid_in = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/496266817/tb/tb_scrypt.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #0  rst_n = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/496266817/tb/tb_scrypt.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #250  rst_n = 1\'b1; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/496266817/tb/tb_scrypt.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #0  out_ready = 1\'b1; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/496266817/tb/tb_scrypt.v:41: Unsupported: Ignoring delay on this delayed statement.\n  #0   start = 1\'b1; \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/496266817/tb/tb_scrypt.v:83: Unsupported: Ignoring delay on this delayed statement.\n     #1 $finish;\n     ^\n%Warning-STMTDLY: data/full_repos/permissive/496266817/tb/tb_scrypt.v:90: Unsupported: Ignoring delay on this delayed statement.\n  #2 $display("\\n T=%g | rst=%b | clock=%b | start=%b | valid_out=%b",$time,rst_n,clk,start,valid_out);\n  ^\n%Error: data/full_repos/permissive/496266817/tb/tb_scrypt.v:127: Cannot find file containing module: \'scrypt_ipcore\'\n scrypt_ipcore dut(clk, rst_n, blockheader, valid_in, out_ready, scrypt_ready, out, valid_out);\n ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/496266817/tb,data/full_repos/permissive/496266817/scrypt_ipcore\n             data/full_repos/permissive/496266817/tb,data/full_repos/permissive/496266817/scrypt_ipcore.v\n             data/full_repos/permissive/496266817/tb,data/full_repos/permissive/496266817/scrypt_ipcore.sv\n             scrypt_ipcore\n             scrypt_ipcore.v\n             scrypt_ipcore.sv\n             obj_dir/scrypt_ipcore\n             obj_dir/scrypt_ipcore.v\n             obj_dir/scrypt_ipcore.sv\n%Error: Exiting due to 1 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_scrypt;
		parameter	WIDTH_IN		= 640;
		parameter	WIDTH_OUT		= 256;
		parameter	NUM_TESTCASE	= 3;
		parameter	CLK_PULSE		= 5;

		reg								clk, rst_n, start;
		wire 							valid_out, scrypt_ready;
		reg		[WIDTH_IN - 1 :0]		blockheader;

		reg								valid_in, out_ready;
		wire 	[WIDTH_OUT - 1:0] 		out;

		reg 	[WIDTH_IN - 1:0]		SCRYPT_IN		[0:NUM_TESTCASE-1];
		reg 	[WIDTH_OUT - 1:0]		SCRYPT_OUT		[0:NUM_TESTCASE-1];
		integer 						out_count		=	0;
		integer 						num_error		=	0;
		integer 						in_count		=	0;
		integer 						clk_count		=	0;
		integer 						done_count 		= 	0;
		integer 						correct_case 	= 	0;



	initial
		#0 clk = 1'b0;
	initial forever	#(CLK_PULSE) clk = ~clk;

	initial begin
		#0 start =1'b0;
		#0 out_ready =1'b0;
		#0 valid_in = 1'b0;



		#0 	rst_n	=	1'b0;
		#250 	rst_n	=	1'b1;	
		#0 	out_ready	=	1'b1;	
		#0 		start	=	1'b1;	
		in_count <= 0;
			num_error <= 0;
			out_count <= 0;
			done_count <= 0;
			correct_case <= 0;
			clk_count <= 0;
			valid_in <= 0;
	end


	 initial begin
		$readmemh("D:/Proposed Litecoin_20_6/Proposed Litecoin_20_6/Testcases/BlockHeader.txt", SCRYPT_IN);
		$readmemh("D:/Proposed Litecoin_20_6/Proposed Litecoin_20_6/Testcases/ScryptOut.txt", SCRYPT_OUT);
	end


	always@(posedge clk) begin
		if(rst_n == 1'b0) begin
			in_count <= 0;
			num_error <= 0;
			out_count <= 0;
			done_count <= 0;
			correct_case <= 0;
			clk_count <= 0;
			valid_in <= 0;
		end
		else if (scrypt_ready == 1'b1) begin
			blockheader <= SCRYPT_IN[in_count];
			valid_in <= 1'b1;
			in_count <= in_count + 1;
		end	
		else	
			valid_in <= 1'b0;
	end


	always@(valid_out) begin
		if(valid_out == 1'b1) begin
			done_count 	<= 	done_count 	+ 	1;
			if (done_count == NUM_TESTCASE )
				begin
					#1 $finish;
				end
		end		
	end

	always @(posedge valid_out) 
	begin
		#2 $display("\n T=%g | rst=%b | clock=%b | start=%b | valid_out=%b",$time,rst_n,clk,start,valid_out);
		$display("VERILOG_Out= \n%h \n MATLAB_Out=\n%h",out,SCRYPT_OUT[out_count]);
		if (out != SCRYPT_OUT[out_count])
			begin 
				num_error=num_error+1;
				$display("\t\t --Error--");
			end
		else if (out == SCRYPT_OUT[out_count])
			begin 
				correct_case=correct_case+1;
				$display("\t\t --Correct--");
			end
		out_count=out_count+1;
		if ((out_count==NUM_TESTCASE)&&(num_error==0)) 
			begin
				correct_case = done_count + 1;
				$display("\n-------------------------------------- SIMULATION REPORT ----------------------------------------------------");
				$display("\n--- Correct Cases %d of %d. \t Fail Cases : %d \t No fail case found ---",correct_case,NUM_TESTCASE,num_error);
				$display("\n--- Number of cycle: %d                                                ---",clk_count);
				$display("\n------------------------------------- ALL DATA ARE CORRECT --------------------------------------------------");
			end
		else if ((out_count==NUM_TESTCASE)&&(num_error>0)) 
			begin
				$display("\n-------------------------------------- SIMULATION REPORT ----------------------------------------------------");
				$display("\n---  Correct Cases %d of %d . \t Fail Cases : %d \t Fail case found  ---",correct_case,NUM_TESTCASE,num_error);
				$display("\n------------------------------------- ERROR WAS FOUND -------------------------------------------------------");
			end
		clk_count=0;	
	end

	always @(posedge clk) begin
		if(start!=1)
			clk_count=0;
		else
			clk_count=clk_count+1;
	end

	scrypt_ipcore	dut(clk, rst_n, blockheader, valid_in, out_ready, scrypt_ready, out, valid_out);



	endmodule
module tb_scrypt;

		parameter	WIDTH_IN		= 640;
		parameter	WIDTH_OUT		= 256;
		parameter	NUM_TESTCASE	= 3;
		parameter	CLK_PULSE		= 5;

		reg								clk, rst_n, start;
		wire 							valid_out, scrypt_ready;
		reg		[WIDTH_IN - 1 :0]		blockheader;

		reg								valid_in, out_ready;
		wire 	[WIDTH_OUT - 1:0] 		out;

		reg 	[WIDTH_IN - 1:0]		SCRYPT_IN		[0:NUM_TESTCASE-1];
		reg 	[WIDTH_OUT - 1:0]		SCRYPT_OUT		[0:NUM_TESTCASE-1];
		integer 						out_count		=	0;
		integer 						num_error		=	0;
		integer 						in_count		=	0;
		integer 						clk_count		=	0;
		integer 						done_count 		= 	0;
		integer 						correct_case 	= 	0;



	initial
		#0 clk = 1'b0;
	initial forever	#(CLK_PULSE) clk = ~clk;

	initial begin
		#0 start =1'b0;
		#0 out_ready =1'b0;
		#0 valid_in = 1'b0;



		#0 	rst_n	=	1'b0;
		#250 	rst_n	=	1'b1;	
		#0 	out_ready	=	1'b1;	
		#0 		start	=	1'b1;	
		in_count <= 0;
			num_error <= 0;
			out_count <= 0;
			done_count <= 0;
			correct_case <= 0;
			clk_count <= 0;
			valid_in <= 0;
	end


	 initial begin
		$readmemh("D:/Proposed Litecoin_20_6/Proposed Litecoin_20_6/Testcases/BlockHeader.txt", SCRYPT_IN);
		$readmemh("D:/Proposed Litecoin_20_6/Proposed Litecoin_20_6/Testcases/ScryptOut.txt", SCRYPT_OUT);
	end


	always@(posedge clk) begin
		if(rst_n == 1'b0) begin
			in_count <= 0;
			num_error <= 0;
			out_count <= 0;
			done_count <= 0;
			correct_case <= 0;
			clk_count <= 0;
			valid_in <= 0;
		end
		else if (scrypt_ready == 1'b1) begin
			blockheader <= SCRYPT_IN[in_count];
			valid_in <= 1'b1;
			in_count <= in_count + 1;
		end	
		else	
			valid_in <= 1'b0;
	end


	always@(valid_out) begin
		if(valid_out == 1'b1) begin
			done_count 	<= 	done_count 	+ 	1;
			if (done_count == NUM_TESTCASE )
				begin
					#1 $finish;
				end
		end		
	end

	always @(posedge valid_out) 
	begin
		#2 $display("\n T=%g | rst=%b | clock=%b | start=%b | valid_out=%b",$time,rst_n,clk,start,valid_out);
		$display("VERILOG_Out= \n%h \n MATLAB_Out=\n%h",out,SCRYPT_OUT[out_count]);
		if (out != SCRYPT_OUT[out_count])
			begin 
				num_error=num_error+1;
				$display("\t\t --Error--");
			end
		else if (out == SCRYPT_OUT[out_count])
			begin 
				correct_case=correct_case+1;
				$display("\t\t --Correct--");
			end
		out_count=out_count+1;
		if ((out_count==NUM_TESTCASE)&&(num_error==0)) 
			begin
				correct_case = done_count + 1;
				$display("\n-------------------------------------- SIMULATION REPORT ----------------------------------------------------");
				$display("\n--- Correct Cases %d of %d. \t Fail Cases : %d \t No fail case found ---",correct_case,NUM_TESTCASE,num_error);
				$display("\n--- Number of cycle: %d                                                ---",clk_count);
				$display("\n------------------------------------- ALL DATA ARE CORRECT --------------------------------------------------");
			end
		else if ((out_count==NUM_TESTCASE)&&(num_error>0)) 
			begin
				$display("\n-------------------------------------- SIMULATION REPORT ----------------------------------------------------");
				$display("\n---  Correct Cases %d of %d . \t Fail Cases : %d \t Fail case found  ---",correct_case,NUM_TESTCASE,num_error);
				$display("\n------------------------------------- ERROR WAS FOUND -------------------------------------------------------");
			end
		clk_count=0;	
	end

	always @(posedge clk) begin
		if(start!=1)
			clk_count=0;
		else
			clk_count=clk_count+1;
	end

	scrypt_ipcore	dut(clk, rst_n, blockheader, valid_in, out_ready, scrypt_ready, out, valid_out);



	endmodule