data/full_repos/permissive/472586361/machine/register-8.v
data/verilator_xmls/683ef53b-6125-454e-ae27-f97c1b60a1be.xml
module register8(   input clk,
                    input [7:0] data_in,
                    input EI, 

                    output reg [7:0] data_out);
wire CLK;
assign CLK=(clk & EI);
always @(posedge CLK)
begin
    data_out <= data_in;
end
endmodule
module register8(   input clk,
                    input [7:0] data_in,
                    input EI, 

                    output reg [7:0] data_out);

wire CLK;
assign CLK=(clk & EI);
always @(posedge CLK)
begin
    data_out <= data_in;
end
endmodule