data/full_repos/permissive/505761772/code/ModemCore.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/505761772/code/ModemCore.v:204: Multiple top level modules\n                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                            : ... Top module \'DEMODULATOR\'\nmodule DEMODULATOR  ( input             CLK,\n       ^~~~~~~~~~~\n                                                                            : ... Top module \'NCO\'\nmodule NCO( input CLK,\n       ^~~\n                                                                            : ... Top module \'DESERIALIZER\'\nmodule DESERIALIZER(  input CLK,\n       ^~~~~~~~~~~~\n                                                                            : ... Top module \'SERIALIZER\'\nmodule SERIALIZER(  input       CLK,\n       ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/505761772/code/ModemCore.v:34: Operator ASSIGNW expects 18 bits on the Assign RHS, but Assign RHS\'s SHIFTRS generates 36 bits.\n                                                                        : ... In instance DEMODULATOR.MULT8\nassign P = (P36>>>17);\n         ^\n%Error: data/full_repos/permissive/505761772/code/ModemCore.v:35: Cannot find file containing module: \'MULT18X18\'\nMULT18X18 mult ( .P(P36),\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/505761772/code,data/full_repos/permissive/505761772/MULT18X18\n             data/full_repos/permissive/505761772/code,data/full_repos/permissive/505761772/MULT18X18.v\n             data/full_repos/permissive/505761772/code,data/full_repos/permissive/505761772/MULT18X18.sv\n             MULT18X18\n             MULT18X18.v\n             MULT18X18.sv\n             obj_dir/MULT18X18\n             obj_dir/MULT18X18.v\n             obj_dir/MULT18X18.sv\n%Warning-WIDTH: data/full_repos/permissive/505761772/code/ModemCore.v:10: Operator ASSIGN expects 18 bits on the Assign RHS, but Assign RHS\'s CONST \'17\'h1d000\' generates 17 bits.\n                                                                        : ... In instance DEMODULATOR.Osc2\nreg signed [17:0] X = 17\'h1D000;\n                      ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/505761772/code/ModemCore.v:11: Operator ASSIGN expects 18 bits on the Assign RHS, but Assign RHS\'s CONST \'17\'h0\' generates 17 bits.\n                                                                        : ... In instance DEMODULATOR.Osc2\nreg signed [17:0] Y = 17\'h00000;\n                      ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/505761772/code/ModemCore.v:192: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                         : ... In instance DEMODULATOR\n    if(cnt == 4\'h1)\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/505761772/code/ModemCore.v:240: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s CONST \'17\'he800\' generates 17 bits.\n                                                                         : ... In instance NCO\n      X <= 17\'h0E800;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/505761772/code/ModemCore.v:241: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s CONST \'17\'h0\' generates 17 bits.\n                                                                         : ... In instance NCO\n      Y <= 17\'h00000;\n        ^~\n%Error: Exiting due to 1 error(s), 7 warning(s)\n'
module DEMODULATOR  ( input             CLK,
                      input      [17:0] SIG,
                      output reg        DATA,
                      output reg        DET,
                      input      [3:0]  EXTRA_SEL,
                      output reg [17:0] EXTRA);

wire signed [17:0] S1k2;
wire signed [17:0] C1k2;
wire signed [17:0] S2k2;
wire signed [17:0] C2k2;

wire signed [17:0] mixS1k2;
wire signed [17:0] mixC1k2;
wire signed [17:0] mixS2k2;
wire signed [17:0] mixC2k2;

wire signed [17:0] IFS1k2;
wire signed [17:0] IFC1k2;
wire signed [17:0] IFS2k2;
wire signed [17:0] IFC2k2;


wire signed [17:0] BBS1k2;
wire signed [17:0] BBC1k2;
wire signed [17:0] BBS2k2;
wire signed [17:0] BBC2k2;


wire signed [17:0] Simb1k2;
wire signed [17:0] Simb2k2;



reg signed [17:0] DACout;
always @(posedge CLK) begin
	case (EXTRA_SEL)
		4'h0: EXTRA <= S1k2;
		4'h1: EXTRA <= C1k2;
		4'h2: EXTRA <= S2k2;
		4'h3: EXTRA <= C2k2;
		4'h4: EXTRA <= mixS1k2;
		4'h5: EXTRA <= mixC1k2;
		4'h6: EXTRA <= mixS2k2;
		4'h7: EXTRA <= mixC2k2;
		4'h8: EXTRA <= IFS1k2;
		4'h9: EXTRA <= IFC1k2;
		4'hA: EXTRA <= IFS2k2;
		4'hB: EXTRA <= IFC2k2;
		4'hC: EXTRA <= BBS1k2;
		4'hD: EXTRA <= BBC1k2;
		4'hE: EXTRA <= BBS2k2;
		4'hF: EXTRA <= BBC2k2;
	endcase
end



OSC #(.k(8), .Ac(16)) Osc1 (.CLK(CLK),
				 										.S(S1k2),
				 									 	.C(C1k2));


OSC #(.k(26), .Ac(9)) Osc2 (.CLK(CLK),
				 									  .S(S2k2),
				 										.C(C2k2));


MULT MULT1 (	.P(mixS1k2),
							.A(S1k2),
							.B(SIG));

MULT MULT2 (	.P(mixC1k2),
							.A(C1k2),
							.B(SIG));

MULT MULT3 (	.P(mixS2k2),
							.A(S2k2),
							.B(SIG));

MULT MULT4 (	.P(mixC2k2),
							.A(C2k2),
							.B(SIG));


LPF LPF1 ( 	.CLK(CLK),
          	.IN(mixS1k2),
	          .OUT(IFS1k2));

LPF LPF2 ( 	.CLK(CLK),
          	.IN(mixC1k2),
	          .OUT(IFC1k2));

LPF LPF3 ( 	.CLK(CLK),
          	.IN(mixS2k2),
	          .OUT(IFS2k2));

LPF LPF4 ( 	.CLK(CLK),
          	.IN(mixC2k2),
		        .OUT(IFC2k2));


MULT MULT5 (	.P(BBS1k2),
							.A(IFS1k2),
							.B(IFS1k2));

MULT MULT6 (	.P(BBC1k2),
							.A(IFC1k2),
							.B(IFC1k2));

MULT MULT7 (	.P(BBS2k2),
							.A(IFS2k2),
							.B(IFS2k2));

MULT MULT8 (	.P(BBC2k2),
							.A(IFC2k2),
							.B(IFC2k2));


assign Simb1k2 = BBS1k2 + BBC1k2;


assign Simb2k2 = BBS2k2 + BBC2k2;


always @(posedge CLK) DATA <= ((Simb2k2 - Simb1k2) + (DATA ? +18'h0000F : -18'h0000F )) > 0;


wire DET_raw;
assign DET_raw = (Simb1k2 + Simb2k2) > 18'h0004F;



reg [4:0] cnt;
always @(posedge CLK) begin
  if(cnt != 0) begin
    if(cnt == 4'h1)
      DET <= DET_raw;
    cnt <= cnt - 1;
  end else if(DET_raw != DET)
    cnt <= 5'h1F;
end

endmodule
module DEMODULATOR  ( input             CLK,
                      input      [17:0] SIG,
                      output reg        DATA,
                      output reg        DET,
                      input      [3:0]  EXTRA_SEL,
                      output reg [17:0] EXTRA);


wire signed [17:0] S1k2;
wire signed [17:0] C1k2;
wire signed [17:0] S2k2;
wire signed [17:0] C2k2;

wire signed [17:0] mixS1k2;
wire signed [17:0] mixC1k2;
wire signed [17:0] mixS2k2;
wire signed [17:0] mixC2k2;

wire signed [17:0] IFS1k2;
wire signed [17:0] IFC1k2;
wire signed [17:0] IFS2k2;
wire signed [17:0] IFC2k2;


wire signed [17:0] BBS1k2;
wire signed [17:0] BBC1k2;
wire signed [17:0] BBS2k2;
wire signed [17:0] BBC2k2;


wire signed [17:0] Simb1k2;
wire signed [17:0] Simb2k2;



reg signed [17:0] DACout;
always @(posedge CLK) begin
	case (EXTRA_SEL)
		4'h0: EXTRA <= S1k2;
		4'h1: EXTRA <= C1k2;
		4'h2: EXTRA <= S2k2;
		4'h3: EXTRA <= C2k2;
		4'h4: EXTRA <= mixS1k2;
		4'h5: EXTRA <= mixC1k2;
		4'h6: EXTRA <= mixS2k2;
		4'h7: EXTRA <= mixC2k2;
		4'h8: EXTRA <= IFS1k2;
		4'h9: EXTRA <= IFC1k2;
		4'hA: EXTRA <= IFS2k2;
		4'hB: EXTRA <= IFC2k2;
		4'hC: EXTRA <= BBS1k2;
		4'hD: EXTRA <= BBC1k2;
		4'hE: EXTRA <= BBS2k2;
		4'hF: EXTRA <= BBC2k2;
	endcase
end



OSC #(.k(8), .Ac(16)) Osc1 (.CLK(CLK),
				 										.S(S1k2),
				 									 	.C(C1k2));


OSC #(.k(26), .Ac(9)) Osc2 (.CLK(CLK),
				 									  .S(S2k2),
				 										.C(C2k2));


MULT MULT1 (	.P(mixS1k2),
							.A(S1k2),
							.B(SIG));

MULT MULT2 (	.P(mixC1k2),
							.A(C1k2),
							.B(SIG));

MULT MULT3 (	.P(mixS2k2),
							.A(S2k2),
							.B(SIG));

MULT MULT4 (	.P(mixC2k2),
							.A(C2k2),
							.B(SIG));


LPF LPF1 ( 	.CLK(CLK),
          	.IN(mixS1k2),
	          .OUT(IFS1k2));

LPF LPF2 ( 	.CLK(CLK),
          	.IN(mixC1k2),
	          .OUT(IFC1k2));

LPF LPF3 ( 	.CLK(CLK),
          	.IN(mixS2k2),
	          .OUT(IFS2k2));

LPF LPF4 ( 	.CLK(CLK),
          	.IN(mixC2k2),
		        .OUT(IFC2k2));


MULT MULT5 (	.P(BBS1k2),
							.A(IFS1k2),
							.B(IFS1k2));

MULT MULT6 (	.P(BBC1k2),
							.A(IFC1k2),
							.B(IFC1k2));

MULT MULT7 (	.P(BBS2k2),
							.A(IFS2k2),
							.B(IFS2k2));

MULT MULT8 (	.P(BBC2k2),
							.A(IFC2k2),
							.B(IFC2k2));


assign Simb1k2 = BBS1k2 + BBC1k2;


assign Simb2k2 = BBS2k2 + BBC2k2;


always @(posedge CLK) DATA <= ((Simb2k2 - Simb1k2) + (DATA ? +18'h0000F : -18'h0000F )) > 0;


wire DET_raw;
assign DET_raw = (Simb1k2 + Simb2k2) > 18'h0004F;



reg [4:0] cnt;
always @(posedge CLK) begin
  if(cnt != 0) begin
    if(cnt == 4'h1)
      DET <= DET_raw;
    cnt <= cnt - 1;
  end else if(DET_raw != DET)
    cnt <= 5'h1F;
end

endmodule