data/full_repos/permissive/437701438/sys/shadowmask.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/437701438/sys/shadowmask.sv:65: Operator ADD expects 4 bits on the RHS, but RHS\'s VARREF \'mask_2x\' generates 1 bits.\n                                                                         : ... In instance shadowmask\n        if (vcount == (vmax2 + mask_2x)) vcount <= 4\'b0;\n                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/437701438/sys/shadowmask.sv:68: Operator ADD expects 4 bits on the RHS, but RHS\'s VARREF \'mask_2x\' generates 1 bits.\n                                                                         : ... In instance shadowmask\n    if (hcount == (hmax2 + mask_2x)) hcount <= 4\'b0;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/437701438/sys/shadowmask.sv:117: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'r\' generates 8 bits.\n                                                                          : ... In instance shadowmask\n    r2 <= r;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/437701438/sys/shadowmask.sv:118: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'g\' generates 8 bits.\n                                                                          : ... In instance shadowmask\n    g2 <= g;\n       ^~\n%Warning-WIDTH: data/full_repos/permissive/437701438/sys/shadowmask.sv:119: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s VARREF \'b\' generates 8 bits.\n                                                                          : ... In instance shadowmask\n    b2 <= b;\n       ^~\n%Error: Exiting due to 5 warning(s)\n'
module shadowmask
(
    input             clk,
    input             clk_sys,
	 
    input             cmd_wr,
    input      [15:0] cmd_in,

    input      [23:0] din,
    input             hs_in,vs_in,
    input             de_in,
    input             enable,

    output reg [23:0] dout,
    output reg        hs_out,vs_out,
    output reg        de_out
);



parameter MaxPatternWidth = 8;
parameter MaxPatternHeight = 4;

reg [3:0] hcount;
reg [3:0] vcount;

reg [3:0] hmax;
reg [3:0] vmax;
reg [3:0] hmax2;
reg [3:0] vmax2;

reg [2:0] hindex;
reg [2:0] vindex;
reg [2:0] hindex2;
reg [2:0] vindex2;

reg mask_2x;
reg mask_rotate;
reg mask_enable;

always @(posedge clk) begin

    reg old_hs, old_vs;
    old_hs <= hs_in;
    old_vs <= vs_in;
    hcount <= hcount + 4'b1;




    hindex <= mask_2x ? hcount[3:1] : hcount[2:0];
    vindex <= mask_2x ? vcount[3:1] : vcount[2:0];
    hindex2 <= mask_rotate ? vindex : hindex;
    vindex2 <= mask_rotate ? hindex : vindex;



    hmax2 <= mask_rotate ? ( vmax << mask_2x ) : ( hmax << mask_2x );
    vmax2 <= mask_rotate ? ( hmax << mask_2x ) : ( vmax << mask_2x );

    if((old_vs && ~vs_in)) vcount <= 4'b0;
    if(old_hs && ~hs_in) begin
        vcount <= vcount + 4'b1;
        hcount <= 4'b0;
        if (vcount == (vmax2 + mask_2x)) vcount <= 4'b0;
        end

    if (hcount == (hmax2 + mask_2x)) hcount <= 4'b0;
end

wire [7:0] r,g,b;
assign {r,g,b} = din;

reg [23:0] d;



























reg m_enable;
always @(posedge clk) m_enable <= mask_enable & enable;

reg [2:0] mask_lut[64];

always @(posedge clk) begin

    reg rbit, gbit, bbit;
    reg [23:0] dout1, dout2;
    reg de1,de2,vs1,vs2,hs1,hs2;
    reg [8:0] r2, g2, b2;
    reg [8:0] r3, g3, b3;

    {rbit,gbit, bbit} = mask_lut[{vindex2[2:0],hindex2[2:0]}];

    r2 <= r;
    g2 <= g;
    b2 <= b;


    r3 <= r2 + (~m_enable ? 9'd0: {3'b0, r2[8:3]}) - ((~m_enable | rbit) ?  9'b0 : {1'b0, r2[8:1]});
    g3 <= g2 + (~m_enable ? 9'd0: {3'b0, g2[8:3]}) - ((~m_enable | gbit) ?  9'b0 : {1'b0, g2[8:1]});
    b3 <= b2 + (~m_enable ? 9'd0: {3'b0, b2[8:3]}) - ((~m_enable | bbit) ?  9'b0 : {1'b0, b2[8:1]});


    dout <= {{8{r3[8]}} | r3[7:0], {8{g3[8]}} | g3[7:0], {8{b3[8]}} | b3[7:0]};

    vs_out <= vs2;   vs2 <= vs1;   vs1 <= vs_in;
    hs_out <= hs2;   hs2 <= hs1;   hs1 <= hs_in;
    de_out <= de2;   de2 <= de1;   de1 <= de_in;
end


always @(posedge clk_sys) begin
    if (cmd_wr) begin
        case(cmd_in[15:13])
        3'b000: {mask_rotate, mask_2x, mask_enable} <= cmd_in[2:0];
        3'b001: vmax <= cmd_in[3:0];
        3'b010: hmax <= cmd_in[3:0];
        3'b011: mask_lut[cmd_in[9:4]] <= cmd_in[2:0];
        endcase
    end
end

endmodule
module shadowmask
(
    input             clk,
    input             clk_sys,
	 
    input             cmd_wr,
    input      [15:0] cmd_in,

    input      [23:0] din,
    input             hs_in,vs_in,
    input             de_in,
    input             enable,

    output reg [23:0] dout,
    output reg        hs_out,vs_out,
    output reg        de_out
);




parameter MaxPatternWidth = 8;
parameter MaxPatternHeight = 4;

reg [3:0] hcount;
reg [3:0] vcount;

reg [3:0] hmax;
reg [3:0] vmax;
reg [3:0] hmax2;
reg [3:0] vmax2;

reg [2:0] hindex;
reg [2:0] vindex;
reg [2:0] hindex2;
reg [2:0] vindex2;

reg mask_2x;
reg mask_rotate;
reg mask_enable;

always @(posedge clk) begin

    reg old_hs, old_vs;
    old_hs <= hs_in;
    old_vs <= vs_in;
    hcount <= hcount + 4'b1;




    hindex <= mask_2x ? hcount[3:1] : hcount[2:0];
    vindex <= mask_2x ? vcount[3:1] : vcount[2:0];
    hindex2 <= mask_rotate ? vindex : hindex;
    vindex2 <= mask_rotate ? hindex : vindex;



    hmax2 <= mask_rotate ? ( vmax << mask_2x ) : ( hmax << mask_2x );
    vmax2 <= mask_rotate ? ( hmax << mask_2x ) : ( vmax << mask_2x );

    if((old_vs && ~vs_in)) vcount <= 4'b0;
    if(old_hs && ~hs_in) begin
        vcount <= vcount + 4'b1;
        hcount <= 4'b0;
        if (vcount == (vmax2 + mask_2x)) vcount <= 4'b0;
        end

    if (hcount == (hmax2 + mask_2x)) hcount <= 4'b0;
end

wire [7:0] r,g,b;
assign {r,g,b} = din;

reg [23:0] d;



























reg m_enable;
always @(posedge clk) m_enable <= mask_enable & enable;

reg [2:0] mask_lut[64];

always @(posedge clk) begin

    reg rbit, gbit, bbit;
    reg [23:0] dout1, dout2;
    reg de1,de2,vs1,vs2,hs1,hs2;
    reg [8:0] r2, g2, b2;
    reg [8:0] r3, g3, b3;

    {rbit,gbit, bbit} = mask_lut[{vindex2[2:0],hindex2[2:0]}];

    r2 <= r;
    g2 <= g;
    b2 <= b;


    r3 <= r2 + (~m_enable ? 9'd0: {3'b0, r2[8:3]}) - ((~m_enable | rbit) ?  9'b0 : {1'b0, r2[8:1]});
    g3 <= g2 + (~m_enable ? 9'd0: {3'b0, g2[8:3]}) - ((~m_enable | gbit) ?  9'b0 : {1'b0, g2[8:1]});
    b3 <= b2 + (~m_enable ? 9'd0: {3'b0, b2[8:3]}) - ((~m_enable | bbit) ?  9'b0 : {1'b0, b2[8:1]});


    dout <= {{8{r3[8]}} | r3[7:0], {8{g3[8]}} | g3[7:0], {8{b3[8]}} | b3[7:0]};

    vs_out <= vs2;   vs2 <= vs1;   vs1 <= vs_in;
    hs_out <= hs2;   hs2 <= hs1;   hs1 <= hs_in;
    de_out <= de2;   de2 <= de1;   de1 <= de_in;
end


always @(posedge clk_sys) begin
    if (cmd_wr) begin
        case(cmd_in[15:13])
        3'b000: {mask_rotate, mask_2x, mask_enable} <= cmd_in[2:0];
        3'b001: vmax <= cmd_in[3:0];
        3'b010: hmax <= cmd_in[3:0];
        3'b011: mask_lut[cmd_in[9:4]] <= cmd_in[2:0];
        endcase
    end
end

endmodule