data/full_repos/permissive/48250786/test_mixcolumnsall.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/48250786/test_mixcolumnsall.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_mixcolumnsall.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_mixcolumnsall.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #20 mixIn = 128\'ha7be1a6997ad739bd8c9ca451f618b61;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_mixcolumnsall.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #20 mixIn = 128\'h3bd92268fc74fb735767cbe0c0590e2d;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_mixcolumnsall.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #20 mixIn = 128\'h2d6d7ef03f33e334093602dd5bfb12c7;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_mixcolumnsall.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #20 mixIn = 128\'h36339d50f9b539269f2c092dc4406d23;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_mixcolumnsall.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_mixcolumnsall.v:64: Unsupported: Ignoring delay on this delayed statement.\n  #20 mixIn = 128\'hbd6e7c3df2b5779e0b61216e8b10b689;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_mixcolumnsall.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #20 mixIn = 128\'hfde3bad205e5d0d73547964ef1fe37f1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_mixcolumnsall.v:66: Unsupported: Ignoring delay on this delayed statement.\n  #20 mixIn = 128\'hd1876c0f79c4300ab45594add66ff41f;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_mixcolumnsall.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #20 mixIn = 128\'hc62fe109f75eedc3cc79395d84f9cf5d;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_mixcolumnsall.v:68: Unsupported: Ignoring delay on this delayed statement.\n  #20 mixIn = 128\'hc81677bc9b7ac93b25027992b0261996;\n  ^\n%Error: data/full_repos/permissive/48250786/test_mixcolumnsall.v:36: Cannot find file containing module: \'mixColumnsAll\'\n mixColumnsAll uut (\n ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/48250786,data/full_repos/permissive/48250786/mixColumnsAll\n             data/full_repos/permissive/48250786,data/full_repos/permissive/48250786/mixColumnsAll.v\n             data/full_repos/permissive/48250786,data/full_repos/permissive/48250786/mixColumnsAll.sv\n             mixColumnsAll\n             mixColumnsAll.v\n             mixColumnsAll.sv\n             obj_dir/mixColumnsAll\n             obj_dir/mixColumnsAll.v\n             obj_dir/mixColumnsAll.sv\n%Error: Exiting due to 1 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_mixcolumnsall;


	reg [127:0] mixIn;
	reg clk;
	reg inverse;


	wire [127:0] mixOut;


	mixColumnsAll uut (
		.mixOut(mixOut), 
		.mixIn(mixIn), 
		.clk(clk), 
		.inverse(inverse)
	);
	
	always begin
		clk = 0;
		#10;
		clk = 1;
		#10;
	end

	initial begin

		inverse = 0;
		mixIn = 128'h6353e08c0960e104cd70b751bacad0e7;
		
		#20 mixIn = 128'ha7be1a6997ad739bd8c9ca451f618b61;
		#20 mixIn = 128'h3bd92268fc74fb735767cbe0c0590e2d;
		#20 mixIn = 128'h2d6d7ef03f33e334093602dd5bfb12c7;
		#20 mixIn = 128'h36339d50f9b539269f2c092dc4406d23;
		
		#100
		

		inverse = 1;
		#20 mixIn = 128'hbd6e7c3df2b5779e0b61216e8b10b689;
		#20 mixIn = 128'hfde3bad205e5d0d73547964ef1fe37f1;
		#20 mixIn = 128'hd1876c0f79c4300ab45594add66ff41f;
		#20 mixIn = 128'hc62fe109f75eedc3cc79395d84f9cf5d;
		#20 mixIn = 128'hc81677bc9b7ac93b25027992b0261996;

	end
      
endmodule
module test_mixcolumnsall;



	reg [127:0] mixIn;
	reg clk;
	reg inverse;


	wire [127:0] mixOut;


	mixColumnsAll uut (
		.mixOut(mixOut), 
		.mixIn(mixIn), 
		.clk(clk), 
		.inverse(inverse)
	);
	
	always begin
		clk = 0;
		#10;
		clk = 1;
		#10;
	end

	initial begin

		inverse = 0;
		mixIn = 128'h6353e08c0960e104cd70b751bacad0e7;
		
		#20 mixIn = 128'ha7be1a6997ad739bd8c9ca451f618b61;
		#20 mixIn = 128'h3bd92268fc74fb735767cbe0c0590e2d;
		#20 mixIn = 128'h2d6d7ef03f33e334093602dd5bfb12c7;
		#20 mixIn = 128'h36339d50f9b539269f2c092dc4406d23;
		
		#100
		

		inverse = 1;
		#20 mixIn = 128'hbd6e7c3df2b5779e0b61216e8b10b689;
		#20 mixIn = 128'hfde3bad205e5d0d73547964ef1fe37f1;
		#20 mixIn = 128'hd1876c0f79c4300ab45594add66ff41f;
		#20 mixIn = 128'hc62fe109f75eedc3cc79395d84f9cf5d;
		#20 mixIn = 128'hc81677bc9b7ac93b25027992b0261996;

	end
      
endmodule