data/full_repos/permissive/42499417/FreqDiv_1s.v
data/verilator_xmls/b3486a9e-045f-438b-85ec-92674323a998.xml
module FreqDiv_1s(
    output reg div,
    input clk
    );

    reg[24:0] count = 0;
    
    always @(posedge clk) begin

        if(count == 25'd7967400) begin
            count <= 0;
            div = ~div;
        end
        else
            count <= count + 1;
    end

endmodule
module FreqDiv_1s(
    output reg div,
    input clk
    );


    reg[24:0] count = 0;
    
    always @(posedge clk) begin

        if(count == 25'd7967400) begin
            count <= 0;
            div = ~div;
        end
        else
            count <= count + 1;
    end

endmodule