data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_txframing.v
1: b'%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_txframing.v:227: Cannot find file containing module: \'fflopx\'\nfflopx #(1) ffreqval1 (txclk, txrst_, eng_val, eng_val1);\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core,data/full_repos/permissive/530013823/fflopx\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core,data/full_repos/permissive/530013823/fflopx.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core,data/full_repos/permissive/530013823/fflopx.sv\n             fflopx\n             fflopx.v\n             fflopx.sv\n             obj_dir/fflopx\n             obj_dir/fflopx.v\n             obj_dir/fflopx.sv\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_txframing.v:257: Operator SUB expects 6 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                                                                                         : ... In instance ipsmacge_txframing\nassign rdy_en = sttmiipg & (cnt_byte >= (thsh_igap - 2\'d2));\n                                                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_txframing.v:283: Cannot find file containing module: \'ipsmacge_txstatem\'\nipsmacge_txstatem itxstatem\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_txframing.v:312: Cannot find file containing module: \'ipsmacge_paupro\'\nipsmacge_paupro ipaupro\n^~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_txframing.v:341: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n                                                                                                                                                         : ... In instance ipsmacge_txframing\n    if (!txrst_)         cnt_byte <= {THSH_GAP{1\'b0}};\n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_txframing.v:342: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n                                                                                                                                                         : ... In instance ipsmacge_txframing\n    else if (~up_act)    cnt_byte <= {THSH_GAP{1\'b0}};\n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_txframing.v:345: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n                                                                                                                                                         : ... In instance ipsmacge_txframing\n        if (rdy_en)      cnt_byte <= {THSH_GAP{1\'b1}};\n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_txframing.v:346: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n                                                                                                                                                         : ... In instance ipsmacge_txframing\n        else if (prm_en) cnt_byte <= {THSH_GAP{1\'b0}};\n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_txframing.v:347: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n                                                                                                                                                         : ... In instance ipsmacge_txframing\n        else if (sfd_en) cnt_byte <= {THSH_GAP{1\'b0}};    \n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_txframing.v:348: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n                                                                                                                                                         : ... In instance ipsmacge_txframing\n        else if (eop_en) cnt_byte <= {THSH_GAP{1\'b0}};\n                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_txframing.v:349: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n                                                                                                                                                         : ... In instance ipsmacge_txframing\n        else if (eof_en) cnt_byte <= {THSH_GAP{1\'b0}};\n                                  ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_txframing.v:416: Cannot find file containing module: \'ippcrc_crc32_8b\'\nippcrc_crc32_8b icrc32_8b\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_txframing.v:435: Cannot find file containing module: \'ipsmacge_txinsert\'\nipsmacge_txinsert itxinsert\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_txframing.v:458: Cannot find file containing module: \'fflopx\'\nfflopx #(1) ffengval1 (txclk, txrst_, eng_ival, ogval);\n^~~~~~\n%Error: Exiting due to 6 error(s), 8 warning(s)\n'
module ipsmacge_txframing
    (
     txrst_,
     txclk,

     spdstable,

     ogdat,
     ogen,
     oger,
     ogval,

     ma_idat,
     ma_ieop,  
     ma_ierr,
     ma_inew,
     
     ma_oreq,
     ma_paudis,

     pa_ien,
     pa_off,
     pa_idi,
     
     pa_oval,

     isouradd,
     oquanta,

     up_txen,
     up_datstt,
     up_act,
     up_paddis,
     up_fcsins,
     up_paudis,
     up_forcetxer,
     up_mspd,
     up_mprm,
     thsh_igap
     );



parameter DAT_DW = 8;
parameter DAT_EW = 3;
parameter CNT_DW = 6;
parameter MSP_DW = 2;
parameter DAT_PRM = 8'h55,
          DAT_SFD = 8'hD5;


parameter STT_DW = 4;


parameter STT_IGAP = 4'd0,
          STT_IRDY = 4'd1,
          STT_IPRM = 4'd2,
          STT_IPAY = 4'd3,
          STT_IFCS = 4'd4,
          STT_IFCE = 4'd5,
          STT_IPAU = 4'd6,
          STT_IPAD = 4'd7,
          STT_IDIS = 4'd8;

parameter MRESERVE = 2'b11,
          M1000    = 2'b10,
          M100     = 2'b01,
          M10      = 2'b00;

parameter THSH_GAP = 5;













parameter PAU_QW = 16;
parameter PAU_AW = 48;
parameter PAU_DA = 48'h01_80_C2_00_00_01;
parameter PAU_TYPE = 16'h88_08;
parameter PAU_OPCODE = 16'h00_01;

parameter BYTE_DA1 = 6'd0,
          BYTE_DA2 = 6'd1,
          BYTE_DA3 = 6'd2,
          BYTE_DA4 = 6'd3,
          BYTE_DA5 = 6'd4,
          BYTE_DA6 = 6'd5,

          BYTE_SA1 = 6'd6,
          BYTE_SA2 = 6'd7,
          BYTE_SA3 = 6'd8,
          BYTE_SA4 = 6'd9,
          BYTE_SA5 = 6'd10,
          BYTE_SA6 = 6'd11,

          BYTE_TY1 = 6'd12,
          BYTE_TY2 = 6'd13,

          BYTE_OP1 = 6'd14,
          BYTE_OP2 = 6'd15,

          BYTE_QU1 = 6'd16,
          BYTE_QU2 = 6'd17,
          BYTE_END = 6'd59;


input               txrst_;
input               txclk;

input               spdstable;

output [DAT_DW-1:0] ogdat;
output              ogen;
output              oger;
output              ogval;

input  [DAT_DW-1:0] ma_idat;
input               ma_ieop;

input [DAT_EW-1:0]  ma_ierr;




input               ma_inew;

output              ma_oreq;

output              ma_paudis;


output              pa_oval;

input               pa_ien;
input               pa_off;
input               pa_idi;

input [47:0]        isouradd;
input [15:0]        oquanta;

input               up_act;
input               up_txen;

input               up_paddis;
input               up_fcsins;
input               up_paudis;

input               up_forcetxer;
input [DAT_DW-1:0]  up_datstt;

input [3:0]         up_mprm;
input [MSP_DW-1:0]  up_mspd;
input [CNT_DW-2:0]  thsh_igap;



wire                 req_val;
reg                  eng_val;
wire                 eng_val1;
wire                 eng_ival;

wire [STT_DW-1:0]    stt_mach;
wire                 rdy_en;
wire                 prm_en;
wire                 sop_en;
wire                 eop_en;
wire                 eof_en;
wire                 sfd_en;
wire                 pad_en;
wire                 fcs_en;
wire                 fcs_er;


reg [CNT_DW-1:0]     cnt_byte;

reg [31:0]           fcs_dat;
wire [31:0]          crc_dat;
wire                 crc_val;

wire [DAT_DW-1:0]    ogdat;
wire                 ogval;
wire                 ogen;
wire                 oger;




wire                 opauen;
wire                 opaudi;



assign pa_oval = req_val;



always @(posedge txclk or negedge txrst_)
    begin
    if (!txrst_)        eng_val <= 1'b0;
    else if (~up_act)   eng_val <= 1'b0;
    else                eng_val <= (up_mspd [1:0] == 2'b11) ? 1'b0 :
                                   up_mspd [1] ? 1'b1 : ~eng_val;
    end

fflopx #(1) ffreqval1 (txclk, txrst_, eng_val, eng_val1);
assign req_val  = up_mspd [1] ? eng_val : eng_val1;
assign eng_ival = eng_val;




assign fcs_en = (~ma_ierr [0]) & ma_ieop;
assign fcs_er = ( ma_ierr [2]);

wire   sttmiipg;
wire   sttmirdy;
wire   sttmiprm;
wire   sttmipay;
wire   sttmipau;
wire   sttmipad;
wire   sttmifcs;
wire   sttmifce;
wire   sttmidis;

assign sttmiipg = (stt_mach == STT_IGAP);
assign sttmirdy = (stt_mach == STT_IRDY);
assign sttmiprm = (stt_mach == STT_IPRM);
assign sttmipay = (stt_mach == STT_IPAY);
assign sttmipau = (stt_mach == STT_IPAU);
assign sttmipad = (stt_mach == STT_IPAD);
assign sttmifcs = (stt_mach == STT_IFCS);
assign sttmifce = (stt_mach == STT_IFCE);
assign sttmidis = (stt_mach == STT_IDIS);

assign rdy_en = sttmiipg & (cnt_byte >= (thsh_igap - 2'd2));

wire   eop_ar;
assign eop_ar = (~ma_ierr [0]) & ma_ieop;

assign eof_en = ((ma_ierr [0] & ma_ieop)                    |
                 (eop_ar & (~up_fcsins))                    |
                 ((sttmifcs | sttmifce) & (cnt_byte >= 6'd3))
                  );

assign prm_en = ((opauen | (ma_inew & (~opaudi)))
                  ) & sttmirdy;

assign pad_en = (sttmipay & (cnt_byte <= 6'd58)) & (eop_ar & (~up_paddis));
          
assign eop_en = ((sttmipad & (cnt_byte >= 6'd59))                               |
                 (sttmipau & (cnt_byte >= 6'd59))                               |
                 (sttmipay & (cnt_byte <= 6'd58) & eop_ar & up_paddis)          |
                 (sttmipay & (cnt_byte >= 6'd59) & eop_ar)
                 );

assign sfd_en = (((cnt_byte >= {2'b0, up_mprm [3:0]}))
                  ) & sttmiprm & eng_ival;

assign sop_en = sfd_en;

ipsmacge_txstatem itxstatem
    (
     .txrst_    (txrst_),
     .txclk     (txclk),

     .reqvld    (eng_ival), 

     .rdy_en    (rdy_en),
     .prm_en    (prm_en),
     .sop_en    (sop_en),
     .pad_en    (pad_en),
     .eop_en    (eop_en),
     .eof_en    (eof_en),

     .pau_en    (opauen),
     .pau_di    (opaudi),
     
     .fcs_en    (fcs_en),
     .fcs_er    (fcs_er),

     .istable   (1'b1),

     .stt_mach  (stt_mach),
     .stt_mach1 (stt_mach),

     .up_en     (up_act & up_txen)
     );


ipsmacge_paupro ipaupro
    (
     .txrst_    (txrst_),
     .txclk     (txclk),
     .ipauen    (pa_ien),
     .ipaudi    (pa_idi),
     .possfd    (sfd_en),

     .opauen    (opauen),
     .opaudi    (opaudi),

     .ppaudis   (up_paudis)
     );

reg    ma_paudis;
always @(posedge txclk or negedge txrst_)
    begin
    if (!txrst_)    ma_paudis <= 1'b0;
    else            ma_paudis <= 1'b1;

    end



assign ma_oreq = req_val & (((~opauen) & sfd_en & up_mspd [1]) | (sttmipay & (~ma_ieop)));


always @(posedge txclk or negedge txrst_)
    begin
    if (!txrst_)         cnt_byte <= {THSH_GAP{1'b0}};
    else if (~up_act)    cnt_byte <= {THSH_GAP{1'b0}};
    else if (eng_ival)
        begin
        if (rdy_en)      cnt_byte <= {THSH_GAP{1'b1}};
        else if (prm_en) cnt_byte <= {THSH_GAP{1'b0}};
        else if (sfd_en) cnt_byte <= {THSH_GAP{1'b0}};    
        else if (eop_en) cnt_byte <= {THSH_GAP{1'b0}};
        else if (eof_en) cnt_byte <= {THSH_GAP{1'b0}};
        else             cnt_byte <= &cnt_byte ? cnt_byte : cnt_byte + 1'b1;
        end
    end                            
                          


 
wire        pau_off;
assign      pau_off = pa_off;

reg [7:0] ins_dat;
always @(stt_mach or cnt_byte or pau_off or ma_idat or isouradd or oquanta)
    begin
    case (stt_mach)
        STT_IPAD:           ins_dat = {DAT_DW{1'b0}};
        STT_IPAY:           ins_dat = ma_idat;
        STT_IPAU:
            begin
            case (cnt_byte)
                BYTE_DA1:   ins_dat = PAU_DA [47:40];
                BYTE_DA2:   ins_dat = PAU_DA [39:32];
                BYTE_DA3:   ins_dat = PAU_DA [31:24];
                BYTE_DA4:   ins_dat = PAU_DA [23:16];
                BYTE_DA5:   ins_dat = PAU_DA [15:8];
                BYTE_DA6:   ins_dat = PAU_DA [7:0];

                BYTE_SA1:   ins_dat = isouradd [47:40];
                BYTE_SA2:   ins_dat = isouradd [39:32];
                BYTE_SA3:   ins_dat = isouradd [31:24];
                BYTE_SA4:   ins_dat = isouradd [23:16];
                BYTE_SA5:   ins_dat = isouradd [15:8];
                BYTE_SA6:   ins_dat = isouradd [7:0];

                BYTE_TY1:   ins_dat = PAU_TYPE [15:8];    
                BYTE_TY2:   ins_dat = PAU_TYPE [7:0];

                BYTE_OP1:   ins_dat = PAU_OPCODE [15:8];
                BYTE_OP2:   ins_dat = PAU_OPCODE [7:0];

                BYTE_QU1:   ins_dat = pau_off ? {DAT_DW{1'b0}} : oquanta [15:8];
                BYTE_QU2:   ins_dat = pau_off ? {DAT_DW{1'b0}} : oquanta [7:0];
                default:    ins_dat = {DAT_DW{1'b0}};
            endcase
            end
        default:            ins_dat = {DAT_DW{1'b0}};
    endcase
    end





assign crc_val = eng_ival & (sttmipad |
                             sttmipau |
                             sttmipay
                             );


always @(posedge txclk or negedge txrst_)
    begin
    if (!txrst_)      fcs_dat <= {32{1'b1}};
    else if (prm_en)  fcs_dat <= {32{1'b1}};
    else if (crc_val) fcs_dat <= crc_dat;

    end

ippcrc_crc32_8b icrc32_8b
    (
     .ci    (fcs_dat),
     .di    (ins_dat),
     
     .co    (crc_dat)
     );




ipsmacge_txinsert itxinsert
    (
     .txrst_    (txrst_),
     .txclk     (txclk),
     .pena      (eng_ival),

     .idat_stt  (up_datstt),
     .isfd      (sfd_en),
     .isttm     (stt_mach),
     .icnt      (cnt_byte [5:0]),
     .icrc      (fcs_dat),

     .ierr      (ma_ierr [1] | up_forcetxer),
     .idat      (ins_dat),

     .uptxen    (up_txen),
     .spdstable (spdstable),

     .oer       (oger),
     .oen       (ogen),
     .odat      (ogdat)
     );

fflopx #(1) ffengval1 (txclk, txrst_, eng_ival, ogval);

endmodule
module ipsmacge_txframing
    (
     txrst_,
     txclk,

     spdstable,

     ogdat,
     ogen,
     oger,
     ogval,

     ma_idat,
     ma_ieop,  
     ma_ierr,
     ma_inew,
     
     ma_oreq,
     ma_paudis,

     pa_ien,
     pa_off,
     pa_idi,
     
     pa_oval,

     isouradd,
     oquanta,

     up_txen,
     up_datstt,
     up_act,
     up_paddis,
     up_fcsins,
     up_paudis,
     up_forcetxer,
     up_mspd,
     up_mprm,
     thsh_igap
     );




parameter DAT_DW = 8;
parameter DAT_EW = 3;
parameter CNT_DW = 6;
parameter MSP_DW = 2;
parameter DAT_PRM = 8'h55,
          DAT_SFD = 8'hD5;


parameter STT_DW = 4;


parameter STT_IGAP = 4'd0,
          STT_IRDY = 4'd1,
          STT_IPRM = 4'd2,
          STT_IPAY = 4'd3,
          STT_IFCS = 4'd4,
          STT_IFCE = 4'd5,
          STT_IPAU = 4'd6,
          STT_IPAD = 4'd7,
          STT_IDIS = 4'd8;

parameter MRESERVE = 2'b11,
          M1000    = 2'b10,
          M100     = 2'b01,
          M10      = 2'b00;

parameter THSH_GAP = 5;













parameter PAU_QW = 16;
parameter PAU_AW = 48;
parameter PAU_DA = 48'h01_80_C2_00_00_01;
parameter PAU_TYPE = 16'h88_08;
parameter PAU_OPCODE = 16'h00_01;

parameter BYTE_DA1 = 6'd0,
          BYTE_DA2 = 6'd1,
          BYTE_DA3 = 6'd2,
          BYTE_DA4 = 6'd3,
          BYTE_DA5 = 6'd4,
          BYTE_DA6 = 6'd5,

          BYTE_SA1 = 6'd6,
          BYTE_SA2 = 6'd7,
          BYTE_SA3 = 6'd8,
          BYTE_SA4 = 6'd9,
          BYTE_SA5 = 6'd10,
          BYTE_SA6 = 6'd11,

          BYTE_TY1 = 6'd12,
          BYTE_TY2 = 6'd13,

          BYTE_OP1 = 6'd14,
          BYTE_OP2 = 6'd15,

          BYTE_QU1 = 6'd16,
          BYTE_QU2 = 6'd17,
          BYTE_END = 6'd59;


input               txrst_;
input               txclk;

input               spdstable;

output [DAT_DW-1:0] ogdat;
output              ogen;
output              oger;
output              ogval;

input  [DAT_DW-1:0] ma_idat;
input               ma_ieop;

input [DAT_EW-1:0]  ma_ierr;




input               ma_inew;

output              ma_oreq;

output              ma_paudis;


output              pa_oval;

input               pa_ien;
input               pa_off;
input               pa_idi;

input [47:0]        isouradd;
input [15:0]        oquanta;

input               up_act;
input               up_txen;

input               up_paddis;
input               up_fcsins;
input               up_paudis;

input               up_forcetxer;
input [DAT_DW-1:0]  up_datstt;

input [3:0]         up_mprm;
input [MSP_DW-1:0]  up_mspd;
input [CNT_DW-2:0]  thsh_igap;



wire                 req_val;
reg                  eng_val;
wire                 eng_val1;
wire                 eng_ival;

wire [STT_DW-1:0]    stt_mach;
wire                 rdy_en;
wire                 prm_en;
wire                 sop_en;
wire                 eop_en;
wire                 eof_en;
wire                 sfd_en;
wire                 pad_en;
wire                 fcs_en;
wire                 fcs_er;


reg [CNT_DW-1:0]     cnt_byte;

reg [31:0]           fcs_dat;
wire [31:0]          crc_dat;
wire                 crc_val;

wire [DAT_DW-1:0]    ogdat;
wire                 ogval;
wire                 ogen;
wire                 oger;




wire                 opauen;
wire                 opaudi;



assign pa_oval = req_val;



always @(posedge txclk or negedge txrst_)
    begin
    if (!txrst_)        eng_val <= 1'b0;
    else if (~up_act)   eng_val <= 1'b0;
    else                eng_val <= (up_mspd [1:0] == 2'b11) ? 1'b0 :
                                   up_mspd [1] ? 1'b1 : ~eng_val;
    end

fflopx #(1) ffreqval1 (txclk, txrst_, eng_val, eng_val1);
assign req_val  = up_mspd [1] ? eng_val : eng_val1;
assign eng_ival = eng_val;




assign fcs_en = (~ma_ierr [0]) & ma_ieop;
assign fcs_er = ( ma_ierr [2]);

wire   sttmiipg;
wire   sttmirdy;
wire   sttmiprm;
wire   sttmipay;
wire   sttmipau;
wire   sttmipad;
wire   sttmifcs;
wire   sttmifce;
wire   sttmidis;

assign sttmiipg = (stt_mach == STT_IGAP);
assign sttmirdy = (stt_mach == STT_IRDY);
assign sttmiprm = (stt_mach == STT_IPRM);
assign sttmipay = (stt_mach == STT_IPAY);
assign sttmipau = (stt_mach == STT_IPAU);
assign sttmipad = (stt_mach == STT_IPAD);
assign sttmifcs = (stt_mach == STT_IFCS);
assign sttmifce = (stt_mach == STT_IFCE);
assign sttmidis = (stt_mach == STT_IDIS);

assign rdy_en = sttmiipg & (cnt_byte >= (thsh_igap - 2'd2));

wire   eop_ar;
assign eop_ar = (~ma_ierr [0]) & ma_ieop;

assign eof_en = ((ma_ierr [0] & ma_ieop)                    |
                 (eop_ar & (~up_fcsins))                    |
                 ((sttmifcs | sttmifce) & (cnt_byte >= 6'd3))
                  );

assign prm_en = ((opauen | (ma_inew & (~opaudi)))
                  ) & sttmirdy;

assign pad_en = (sttmipay & (cnt_byte <= 6'd58)) & (eop_ar & (~up_paddis));
          
assign eop_en = ((sttmipad & (cnt_byte >= 6'd59))                               |
                 (sttmipau & (cnt_byte >= 6'd59))                               |
                 (sttmipay & (cnt_byte <= 6'd58) & eop_ar & up_paddis)          |
                 (sttmipay & (cnt_byte >= 6'd59) & eop_ar)
                 );

assign sfd_en = (((cnt_byte >= {2'b0, up_mprm [3:0]}))
                  ) & sttmiprm & eng_ival;

assign sop_en = sfd_en;

ipsmacge_txstatem itxstatem
    (
     .txrst_    (txrst_),
     .txclk     (txclk),

     .reqvld    (eng_ival), 

     .rdy_en    (rdy_en),
     .prm_en    (prm_en),
     .sop_en    (sop_en),
     .pad_en    (pad_en),
     .eop_en    (eop_en),
     .eof_en    (eof_en),

     .pau_en    (opauen),
     .pau_di    (opaudi),
     
     .fcs_en    (fcs_en),
     .fcs_er    (fcs_er),

     .istable   (1'b1),

     .stt_mach  (stt_mach),
     .stt_mach1 (stt_mach),

     .up_en     (up_act & up_txen)
     );


ipsmacge_paupro ipaupro
    (
     .txrst_    (txrst_),
     .txclk     (txclk),
     .ipauen    (pa_ien),
     .ipaudi    (pa_idi),
     .possfd    (sfd_en),

     .opauen    (opauen),
     .opaudi    (opaudi),

     .ppaudis   (up_paudis)
     );

reg    ma_paudis;
always @(posedge txclk or negedge txrst_)
    begin
    if (!txrst_)    ma_paudis <= 1'b0;
    else            ma_paudis <= 1'b1;

    end



assign ma_oreq = req_val & (((~opauen) & sfd_en & up_mspd [1]) | (sttmipay & (~ma_ieop)));


always @(posedge txclk or negedge txrst_)
    begin
    if (!txrst_)         cnt_byte <= {THSH_GAP{1'b0}};
    else if (~up_act)    cnt_byte <= {THSH_GAP{1'b0}};
    else if (eng_ival)
        begin
        if (rdy_en)      cnt_byte <= {THSH_GAP{1'b1}};
        else if (prm_en) cnt_byte <= {THSH_GAP{1'b0}};
        else if (sfd_en) cnt_byte <= {THSH_GAP{1'b0}};    
        else if (eop_en) cnt_byte <= {THSH_GAP{1'b0}};
        else if (eof_en) cnt_byte <= {THSH_GAP{1'b0}};
        else             cnt_byte <= &cnt_byte ? cnt_byte : cnt_byte + 1'b1;
        end
    end                            
                          


 
wire        pau_off;
assign      pau_off = pa_off;

reg [7:0] ins_dat;
always @(stt_mach or cnt_byte or pau_off or ma_idat or isouradd or oquanta)
    begin
    case (stt_mach)
        STT_IPAD:           ins_dat = {DAT_DW{1'b0}};
        STT_IPAY:           ins_dat = ma_idat;
        STT_IPAU:
            begin
            case (cnt_byte)
                BYTE_DA1:   ins_dat = PAU_DA [47:40];
                BYTE_DA2:   ins_dat = PAU_DA [39:32];
                BYTE_DA3:   ins_dat = PAU_DA [31:24];
                BYTE_DA4:   ins_dat = PAU_DA [23:16];
                BYTE_DA5:   ins_dat = PAU_DA [15:8];
                BYTE_DA6:   ins_dat = PAU_DA [7:0];

                BYTE_SA1:   ins_dat = isouradd [47:40];
                BYTE_SA2:   ins_dat = isouradd [39:32];
                BYTE_SA3:   ins_dat = isouradd [31:24];
                BYTE_SA4:   ins_dat = isouradd [23:16];
                BYTE_SA5:   ins_dat = isouradd [15:8];
                BYTE_SA6:   ins_dat = isouradd [7:0];

                BYTE_TY1:   ins_dat = PAU_TYPE [15:8];    
                BYTE_TY2:   ins_dat = PAU_TYPE [7:0];

                BYTE_OP1:   ins_dat = PAU_OPCODE [15:8];
                BYTE_OP2:   ins_dat = PAU_OPCODE [7:0];

                BYTE_QU1:   ins_dat = pau_off ? {DAT_DW{1'b0}} : oquanta [15:8];
                BYTE_QU2:   ins_dat = pau_off ? {DAT_DW{1'b0}} : oquanta [7:0];
                default:    ins_dat = {DAT_DW{1'b0}};
            endcase
            end
        default:            ins_dat = {DAT_DW{1'b0}};
    endcase
    end





assign crc_val = eng_ival & (sttmipad |
                             sttmipau |
                             sttmipay
                             );


always @(posedge txclk or negedge txrst_)
    begin
    if (!txrst_)      fcs_dat <= {32{1'b1}};
    else if (prm_en)  fcs_dat <= {32{1'b1}};
    else if (crc_val) fcs_dat <= crc_dat;

    end

ippcrc_crc32_8b icrc32_8b
    (
     .ci    (fcs_dat),
     .di    (ins_dat),
     
     .co    (crc_dat)
     );




ipsmacge_txinsert itxinsert
    (
     .txrst_    (txrst_),
     .txclk     (txclk),
     .pena      (eng_ival),

     .idat_stt  (up_datstt),
     .isfd      (sfd_en),
     .isttm     (stt_mach),
     .icnt      (cnt_byte [5:0]),
     .icrc      (fcs_dat),

     .ierr      (ma_ierr [1] | up_forcetxer),
     .idat      (ins_dat),

     .uptxen    (up_txen),
     .spdstable (spdstable),

     .oer       (oger),
     .oen       (ogen),
     .odat      (ogdat)
     );

fflopx #(1) ffengval1 (txclk, txrst_, eng_ival, ogval);

endmodule