data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v
1: b'%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:7: Cannot find include file: define.vh\n`include "define.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src,data/full_repos/permissive/413020148/define.vh\n             data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src,data/full_repos/permissive/413020148/define.vh.v\n             data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src,data/full_repos/permissive/413020148/define.vh.sv\n             define.vh\n             define.vh.v\n             define.vh.sv\n             obj_dir/define.vh\n             obj_dir/define.vh.v\n             obj_dir/define.vh.sv\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:157: Define or directive not defined: \'`ACCESS_CODE\'\n    wire        w_iscode        = (w_tlb_req == `ACCESS_CODE);\n                                                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:157: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    wire        w_iscode        = (w_tlb_req == `ACCESS_CODE);\n                                                            ^\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:158: Define or directive not defined: \'`ACCESS_READ\'\n    wire        w_isread        = (w_tlb_req == `ACCESS_READ);\n                                                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:158: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    wire        w_isread        = (w_tlb_req == `ACCESS_READ);\n                                                            ^\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:159: Define or directive not defined: \'`ACCESS_WRITE\'\n    wire        w_iswrite       = (w_tlb_req == `ACCESS_WRITE);\n                                                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:159: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    wire        w_iswrite       = (w_tlb_req == `ACCESS_WRITE);\n                                                             ^\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:170: Define or directive not defined: \'`PRIV_S\'\n                                    (w_priv == `PRIV_S && (L1_pte[4] && !w_mstatus[18])) ||\n                                               ^~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:170: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n                                    (w_priv == `PRIV_S && (L1_pte[4] && !w_mstatus[18])) ||\n                                                       ^~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:171: Define or directive not defined: \'`PRIV_U\'\n                                    (w_priv == `PRIV_U && !L1_pte[4]) ||\n                                               ^~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:182: Define or directive not defined: \'`PRIV_S\'\n                                    (w_priv == `PRIV_S && (L0_pte[4] && !w_mstatus[18])) ||\n                                               ^~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:182: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n                                    (w_priv == `PRIV_S && (L0_pte[4] && !w_mstatus[18])) ||\n                                                       ^~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:183: Define or directive not defined: \'`PRIV_U\'\n                                    (w_priv == `PRIV_U && !L0_pte[4]) ||\n                                               ^~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:187: Define or directive not defined: \'`PTE_A_MASK\'\n    wire [31:0] L1_pte_write    = L1_pte | `PTE_A_MASK | (w_iswrite ? `PTE_D_MASK : 0);\n                                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:187: Define or directive not defined: \'`PTE_D_MASK\'\n    wire [31:0] L1_pte_write    = L1_pte | `PTE_A_MASK | (w_iswrite ? `PTE_D_MASK : 0);\n                                                                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:187: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n    wire [31:0] L1_pte_write    = L1_pte | `PTE_A_MASK | (w_iswrite ? `PTE_D_MASK : 0);\n                                                                                  ^\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:188: Define or directive not defined: \'`PTE_A_MASK\'\n    wire [31:0] L0_pte_write    = L0_pte | `PTE_A_MASK | (w_iswrite ? `PTE_D_MASK : 0);\n                                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:188: Define or directive not defined: \'`PTE_D_MASK\'\n    wire [31:0] L0_pte_write    = L0_pte | `PTE_A_MASK | (w_iswrite ? `PTE_D_MASK : 0);\n                                                                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:188: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n    wire [31:0] L0_pte_write    = L0_pte | `PTE_A_MASK | (w_iswrite ? `PTE_D_MASK : 0);\n                                                                                  ^\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:194: Define or directive not defined: \'`CAUSE_FETCH_PAGE_FAULT\'\n    assign w_pagefault          = !page_walk_fail ? ~32\'h0 : (w_iscode) ? `CAUSE_FETCH_PAGE_FAULT :\n                                                                          ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:194: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n    assign w_pagefault          = !page_walk_fail ? ~32\'h0 : (w_iscode) ? `CAUSE_FETCH_PAGE_FAULT :\n                                                                                                  ^\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:195: Define or directive not defined: \'`CAUSE_LOAD_PAGE_FAULT\'\n                                    (w_isread) ? `CAUSE_LOAD_PAGE_FAULT : `CAUSE_STORE_PAGE_FAULT;\n                                                 ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:195: Define or directive not defined: \'`CAUSE_STORE_PAGE_FAULT\'\n                                    (w_isread) ? `CAUSE_LOAD_PAGE_FAULT : `CAUSE_STORE_PAGE_FAULT;\n                                                                          ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:202: Define or directive not defined: \'`PRIV_M\'\n                                          && (!(w_priv == `PRIV_M || w_satp[31] == 0)));\n                                                          ^~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:202: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n                                          && (!(w_priv == `PRIV_M || w_satp[31] == 0)));\n                                                                  ^~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:280: Define or directive not defined: \'`TLB_SIZE\'\n    m_tlb#(20, 22, `TLB_SIZE) TLB_inst_r (CLK, 1\'b1, w_tlb_flush, w_tlb_inst_r_we,\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:284: Define or directive not defined: \'`TLB_SIZE\'\n    m_tlb#(20, 22, `TLB_SIZE) TLB_data_r (CLK, 1\'b1, w_tlb_flush, w_tlb_data_r_we,\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:288: Define or directive not defined: \'`TLB_SIZE\'\n    m_tlb#(20, 22, `TLB_SIZE) TLB_data_w (CLK, 1\'b1, w_tlb_flush, w_tlb_data_w_we,\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:311: Define or directive not defined: \'`PRIV_M\'\n    wire [31:0] w_insn_paddr =  (w_priv == `PRIV_M || w_satp[31] == 0) ? w_insn_addr :\n                                           ^~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:311: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n    wire [31:0] w_insn_paddr =  (w_priv == `PRIV_M || w_satp[31] == 0) ? w_insn_addr :\n                                                   ^~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:315: Define or directive not defined: \'`PRIV_M\'\n                                (w_priv == `PRIV_M || w_satp[31] == 0)  ? w_data_addr   : r_tlb_addr;\n                                           ^~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:315: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n                                (w_priv == `PRIV_M || w_satp[31] == 0)  ? w_data_addr   : r_tlb_addr;\n                                                   ^~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:321: Define or directive not defined: \'`PRIV_M\'\n                                (w_priv == `PRIV_M || w_satp[31] == 0)  ? w_data_ctrl       :\n                                           ^~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:321: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n                                (w_priv == `PRIV_M || w_satp[31] == 0)  ? w_data_ctrl       :\n                                                   ^~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:323: Define or directive not defined: \'`FUNCT3_LW____\'\n                                (r_pw_state == 0)                       ? `FUNCT3_LW____    :\n                                                                          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:324: Define or directive not defined: \'`FUNCT3_LW____\'\n                                (r_pw_state == 2)                       ? `FUNCT3_LW____    :\n                                                                          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:325: Define or directive not defined: \'`FUNCT3_SW____\'\n                                (r_pw_state == 5)                       ? `FUNCT3_SW____    :\n                                                                          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:336: Define or directive not defined: \'`MEM_BASE_TADDR\'\n                                    && (w_dev == `MEM_BASE_TADDR || w_dev == 0));\n                                                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:336: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n                                    && (w_dev == `MEM_BASE_TADDR || w_dev == 0));\n                                                                 ^~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:340: Define or directive not defined: \'`PRIV_M\'\n                                (w_priv == `PRIV_M || w_satp[31] == 0) ? w_data_addr :\n                                           ^~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:340: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n                                (w_priv == `PRIV_M || w_satp[31] == 0) ? w_data_addr :\n                                                   ^~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:344: Define or directive not defined: \'`FUNCT3_LW____\'\n                                (w_iscode && !w_tlb_busy)   ? `FUNCT3_LW____    : w_mem_ctrl;\n                                                              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:344: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n                                (w_iscode && !w_tlb_busy)   ? `FUNCT3_LW____    : w_mem_ctrl;\n                                                                                ^\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:352: Define or directive not defined: \'`ACCESS_READ\'\n                    (r_mc_mode!=0) ? (w_mc_aces==`ACCESS_READ && w_mc_addr[31:28] != 0) :\n                                                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:352: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n                    (r_mc_mode!=0) ? (w_mc_aces==`ACCESS_READ && w_mc_addr[31:28] != 0) :\n                                                              ^~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:353: Define or directive not defined: \'`PRIV_M\'\n                    (w_priv == `PRIV_M || w_satp[31] == 0) ? (w_iscode || w_isread) :\n                               ^~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:360: Define or directive not defined: \'`VIRTIO_BASE_TADDR\'\n                            (w_mem_we && !w_tlb_busy && w_dev == `VIRTIO_BASE_TADDR && w_virt == 0);\n                                                                 ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:360: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n                            (w_mem_we && !w_tlb_busy && w_dev == `VIRTIO_BASE_TADDR && w_virt == 0);\n                                                                                    ^~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:369: Define or directive not defined: \'`VIRTIO_BASE_TADDR\'\n                            (w_mem_we && !w_tlb_busy && w_dev == `VIRTIO_BASE_TADDR && w_virt != 0);\n                                                                 ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/mmu.v:369: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n                            (w_mem_we && !w_tlb_busy && w_dev == `VIRTIO_BASE_TADDR && w_virt != 0);\n                                                                                    ^~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module m_tlb#(parameter ADDR_WIDTH = 20, D_WIDTH = 20, ENTRY = 4)
            (CLK, RST_X, w_flush, w_we, w_waddr, w_raddr, w_idata, w_odata, w_oe);
    input  wire                     CLK, RST_X;
    input  wire                     w_flush, w_we;
    input  wire [ADDR_WIDTH-1:0]    w_waddr, w_raddr;
    input  wire    [D_WIDTH-1:0]    w_idata;
    output wire    [D_WIDTH-1:0]    w_odata;
    output wire                     w_oe;

    reg                               [ENTRY-1:0]   r_valid = 0;
    reg  [(ADDR_WIDTH-$clog2(ENTRY)+D_WIDTH)-1:0]   mem [0:ENTRY-1];
    integer i;
    initial for(i=0; i<ENTRY; i=i+1) mem[i] = 0;


    wire              [$clog2(ENTRY)-1:0]   w_ridx;
    wire [(ADDR_WIDTH-$clog2(ENTRY))-1:0]   w_rtag;
    assign {w_rtag, w_ridx} = w_raddr;

    wire w_tagmatch = (mem[w_ridx][(ADDR_WIDTH-$clog2(ENTRY)+D_WIDTH)-1:D_WIDTH] == w_rtag);

    assign w_odata  = mem[w_ridx][D_WIDTH-1:0];
    assign w_oe     = (w_tagmatch && r_valid[w_ridx]);


    wire              [$clog2(ENTRY)-1:0]   w_widx;
    wire [(ADDR_WIDTH-$clog2(ENTRY))-1:0]   w_wtag;
    assign {w_wtag, w_widx} = w_waddr;

    always  @(posedge  CLK)  begin

        if (!RST_X || w_flush) begin
            r_valid <= 0;
        end
        if (w_we) begin
            mem[w_widx] <= {w_wtag, w_idata};
            r_valid[w_widx] <= 1;
        end
    end
endmodule
module m_tlb#(parameter ADDR_WIDTH = 20, D_WIDTH = 20, ENTRY = 4)
            (CLK, RST_X, w_flush, w_we, w_waddr, w_raddr, w_idata, w_odata, w_oe);

    input  wire                     CLK, RST_X;
    input  wire                     w_flush, w_we;
    input  wire [ADDR_WIDTH-1:0]    w_waddr, w_raddr;
    input  wire    [D_WIDTH-1:0]    w_idata;
    output wire    [D_WIDTH-1:0]    w_odata;
    output wire                     w_oe;

    reg                               [ENTRY-1:0]   r_valid = 0;
    reg  [(ADDR_WIDTH-$clog2(ENTRY)+D_WIDTH)-1:0]   mem [0:ENTRY-1];
    integer i;
    initial for(i=0; i<ENTRY; i=i+1) mem[i] = 0;


    wire              [$clog2(ENTRY)-1:0]   w_ridx;
    wire [(ADDR_WIDTH-$clog2(ENTRY))-1:0]   w_rtag;
    assign {w_rtag, w_ridx} = w_raddr;

    wire w_tagmatch = (mem[w_ridx][(ADDR_WIDTH-$clog2(ENTRY)+D_WIDTH)-1:D_WIDTH] == w_rtag);

    assign w_odata  = mem[w_ridx][D_WIDTH-1:0];
    assign w_oe     = (w_tagmatch && r_valid[w_ridx]);


    wire              [$clog2(ENTRY)-1:0]   w_widx;
    wire [(ADDR_WIDTH-$clog2(ENTRY))-1:0]   w_wtag;
    assign {w_wtag, w_widx} = w_waddr;

    always  @(posedge  CLK)  begin

        if (!RST_X || w_flush) begin
            r_valid <= 0;
        end
        if (w_we) begin
            mem[w_widx] <= {w_wtag, w_idata};
            r_valid[w_widx] <= 1;
        end
    end
endmodule