data/full_repos/permissive/496903659/142 exams#2014_q3fsm.v
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/496903659/142\n        ... Looked in:\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/142\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/142.v\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/142.sv\n             data/full_repos/permissive/496903659/142\n             data/full_repos/permissive/496903659/142.v\n             data/full_repos/permissive/496903659/142.sv\n             obj_dir/data/full_repos/permissive/496903659/142\n             obj_dir/data/full_repos/permissive/496903659/142.v\n             obj_dir/data/full_repos/permissive/496903659/142.sv\n%Error: Cannot find file containing module: exams#2014_q3fsm.v\n%Error: Exiting due to 2 error(s)\n'
module top_module (
    input clk,
    input reset,
    input s,
    input w,
    output z
);
    reg state;
    reg [2:0] bits;
    reg [2:0] counts;
    always @(posedge clk) begin
        if (reset) begin
            state <= 0;
            counts <= 3'b111;
        end
        else begin
            if (~state)
                state <= s;
            else begin
                bits <= {bits[1:0], w};
                if (counts == 0)
                    counts <= 3'b110;
                else
                    counts <= {counts[1:0], 1'b0};
            end
        end
    end
    
    assign z = ((bits[0] + bits[1] + bits[2]) == 2) & (counts == 0);
endmodule
module top_module (
    input clk,
    input reset,
    input s,
    input w,
    output z
);

    reg state;
    reg [2:0] bits;
    reg [2:0] counts;
    always @(posedge clk) begin
        if (reset) begin
            state <= 0;
            counts <= 3'b111;
        end
        else begin
            if (~state)
                state <= s;
            else begin
                bits <= {bits[1:0], w};
                if (counts == 0)
                    counts <= 3'b110;
                else
                    counts <= {counts[1:0], 1'b0};
            end
        end
    end
    
    assign z = ((bits[0] + bits[1] + bits[2]) == 2) & (counts == 0);
endmodule