data/full_repos/permissive/450072296/verilog/rtl/stud_second_order_modulator.v
data/verilator_xmls/fe1ddcd1-7168-4cc4-9e07-25d135ea5275.xml
module stud_second_order_modulator
#(
    parameter BITWIDTH = 16
)
(
    input n_rst_i,
    input clk_i,

    input [BITWIDTH - 1 : 0] data_i,

    output reg [1 : 0] mod_o
);


reg [1 : 0] counter;
reg [1 : 0] counter_next;


reg sampling_strb;
reg sampling_strb_next;


reg [BITWIDTH - 1 : 0] fb1;
reg [BITWIDTH - 1 : 0] fb1_next;


reg [BITWIDTH - 1 : 0] fb2;
reg [BITWIDTH - 1 : 0] fb2_next;


reg [BITWIDTH + 1: 0] acc;
reg [BITWIDTH + 1: 0] acc_next;


reg [1 : 0] mod_next;


always @* begin

    counter_next = counter;
    sampling_strb_next = 1'b0;

    if (counter == 2'd3) begin

        counter_next = 2'b0;
        sampling_strb_next = 1'b1;
    end else begin

        counter_next = counter + 2'd1;
    end
end


always @* begin

    fb1_next = fb1;
    fb2_next = fb2;
    acc_next = acc;
    mod_next = mod_o;


    if (sampling_strb) begin


        fb2_next = fb1;



        fb1_next = acc[BITWIDTH - 1 : 0];



        acc_next = {2'b0, data_i} + ({2'b0, fb1} << 1) + {1'b0, {1'b1, {BITWIDTH {1'b0}}} - {1'b0, fb2}};


        mod_next = acc[BITWIDTH + 1 : BITWIDTH];
    end
end


always @(posedge clk_i) begin
    if (!n_rst_i) begin

        counter <= 2'd3;
        sampling_strb <= 1'b0;

        fb1 <= {BITWIDTH {1'b0}};
        fb2 <= {BITWIDTH {1'b0}};
        acc <= {BITWIDTH + 2 {1'b0}};
        mod_o <= 2'b0;
    end else begin
        counter <= counter_next;
        sampling_strb <= sampling_strb_next;

        fb1 <= fb1_next;
        fb2 <= fb2_next;
        acc <= acc_next;

        mod_o <= mod_next;
    end
end

endmodule
module stud_second_order_modulator
#(
    parameter BITWIDTH = 16
)
(
    input n_rst_i,
    input clk_i,

    input [BITWIDTH - 1 : 0] data_i,

    output reg [1 : 0] mod_o
);



reg [1 : 0] counter;
reg [1 : 0] counter_next;


reg sampling_strb;
reg sampling_strb_next;


reg [BITWIDTH - 1 : 0] fb1;
reg [BITWIDTH - 1 : 0] fb1_next;


reg [BITWIDTH - 1 : 0] fb2;
reg [BITWIDTH - 1 : 0] fb2_next;


reg [BITWIDTH + 1: 0] acc;
reg [BITWIDTH + 1: 0] acc_next;


reg [1 : 0] mod_next;


always @* begin

    counter_next = counter;
    sampling_strb_next = 1'b0;

    if (counter == 2'd3) begin

        counter_next = 2'b0;
        sampling_strb_next = 1'b1;
    end else begin

        counter_next = counter + 2'd1;
    end
end


always @* begin

    fb1_next = fb1;
    fb2_next = fb2;
    acc_next = acc;
    mod_next = mod_o;


    if (sampling_strb) begin


        fb2_next = fb1;



        fb1_next = acc[BITWIDTH - 1 : 0];



        acc_next = {2'b0, data_i} + ({2'b0, fb1} << 1) + {1'b0, {1'b1, {BITWIDTH {1'b0}}} - {1'b0, fb2}};


        mod_next = acc[BITWIDTH + 1 : BITWIDTH];
    end
end


always @(posedge clk_i) begin
    if (!n_rst_i) begin

        counter <= 2'd3;
        sampling_strb <= 1'b0;

        fb1 <= {BITWIDTH {1'b0}};
        fb2 <= {BITWIDTH {1'b0}};
        acc <= {BITWIDTH + 2 {1'b0}};
        mod_o <= 2'b0;
    end else begin
        counter <= counter_next;
        sampling_strb <= sampling_strb_next;

        fb1 <= fb1_next;
        fb2 <= fb2_next;
        acc <= acc_next;

        mod_o <= mod_next;
    end
end

endmodule