data/full_repos/permissive/418819021/lab-07/timer_unit.v
1: b'%Error: data/full_repos/permissive/418819021/lab-07/timer_unit.v:4: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418819021/lab-07,data/full_repos/permissive/418819021/defines.vh\n             data/full_repos/permissive/418819021/lab-07,data/full_repos/permissive/418819021/defines.vh.v\n             data/full_repos/permissive/418819021/lab-07,data/full_repos/permissive/418819021/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/418819021/lab-07/timer_unit.v:82: Define or directive not defined: \'`NORMAL\'\n        (wgm0 == 3\'b000) ? `NORMAL :\n                           ^~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-07/timer_unit.v:82: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n        (wgm0 == 3\'b000) ? `NORMAL :\n                                   ^\n%Error: data/full_repos/permissive/418819021/lab-07/timer_unit.v:83: Define or directive not defined: \'`CTC\'\n        (wgm0 == 3\'b010) ? `CTC :\n                           ^~~~\n%Error: data/full_repos/permissive/418819021/lab-07/timer_unit.v:84: Define or directive not defined: \'`FAST_PWM_MAX\'\n        (wgm0 == 3\'b011) ? `FAST_PWM_MAX :\n                           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-07/timer_unit.v:85: Define or directive not defined: \'`FAST_PWM_OCR\'\n        (wgm0 == 3\'b111) ? `FAST_PWM_OCR :\n                           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-07/timer_unit.v:86: Define or directive not defined: \'`INVALID\'\n        `INVALID;\n        ^~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-07/timer_unit.v:91: Define or directive not defined: \'`NORMAL\'\n        (timer_mode == `NORMAL) ?\n                       ^~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-07/timer_unit.v:91: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        (timer_mode == `NORMAL) ?\n                              ^\n%Error: data/full_repos/permissive/418819021/lab-07/timer_unit.v:93: Define or directive not defined: \'`CTC\'\n            (timer_mode == `CTC) ?\n                           ^~~~\n%Error: data/full_repos/permissive/418819021/lab-07/timer_unit.v:95: Define or directive not defined: \'`FAST_PWM_MAX\'\n                (timer_mode == `FAST_PWM_MAX) ?\n                               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-07/timer_unit.v:97: Define or directive not defined: \'`FAST_PWM_OCR\'\n                    (timer_mode == `FAST_PWM_OCR) ?\n                                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-07/timer_unit.v:130: Define or directive not defined: \'`NORMAL\'\n                `NORMAL, `CTC : begin\n                ^~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-07/timer_unit.v:130: syntax error, unexpected \',\', expecting endcase\n                `NORMAL, `CTC : begin\n                       ^\n%Error: data/full_repos/permissive/418819021/lab-07/timer_unit.v:130: Define or directive not defined: \'`CTC\'\n                `NORMAL, `CTC : begin\n                         ^~~~\n%Error: data/full_repos/permissive/418819021/lab-07/timer_unit.v:147: Define or directive not defined: \'`FAST_PWM_MAX\'\n                `FAST_PWM_MAX, `FAST_PWM_OCR : begin\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-07/timer_unit.v:147: Define or directive not defined: \'`FAST_PWM_OCR\'\n                `FAST_PWM_MAX, `FAST_PWM_OCR : begin\n                               ^~~~~~~~~~~~~\n%Error: Cannot continue\n'
module timer_unit #(parameter DATA_WIDTH = 8) (
    input  wire                      clk       ,
    input  wire                      reset     ,
    input  wire     [DATA_WIDTH-1:0] mem_ocr0a ,
    input  wire     [DATA_WIDTH-1:0] mem_ocr0b ,
    input  wire     [DATA_WIDTH-1:0] mem_tcnt0 ,
    input  wire     [DATA_WIDTH-1:0] mem_tccr0a,
    input  wire     [DATA_WIDTH-1:0] mem_tccr0b,
    output      reg [DATA_WIDTH-1:0] tcnt0     ,
    output      reg                  oc0a      ,
    output      reg                  oc0b
);


    wire clk_t;
    wire clk_io;
    wire clk_io_8;
    wire clk_io_64;
    wire clk_io_256;
    wire clk_io_1024;

    wire [ 7:0] clk_sources;
    reg  [13:0] count      ;

    always @(posedge clk, posedge reset) begin
        if (reset)
            count <= 0;
        else
            count <= count + 1;
    end



    assign clk_io      = clk;
    assign clk_io_8    = count[2];
    assign clk_io_64   = count[5];
    assign clk_io_256  = count[7];
    assign clk_io_1024 = count[9];





    assign clk_sources = {
        1'b0,
        1'b0,
        clk_io_1024,
        clk_io_256,
        clk_io_64,
        clk_io_8,
        clk_io,
        1'b0
    };



    assign clk_t = clk_sources[cs0];


    wire [1:0] com0a;
    wire [1:0] com0b;
    wire [2:0] wgm0 ;
    wire [2:0] cs0  ;



    assign com0a = mem_tccr0a[7:6];
    assign com0b = mem_tccr0a[5:4];
    assign wgm0  = {mem_tccr0b[3], mem_tccr0a[1:0]};
    assign cs0   = mem_tccr0b[2:0];

    wire [           5:0] timer_mode;
    wire [DATA_WIDTH-1:0] top       ;



    assign timer_mode =
        (wgm0 == 3'b000) ? `NORMAL :
        (wgm0 == 3'b010) ? `CTC :
        (wgm0 == 3'b011) ? `FAST_PWM_MAX :
        (wgm0 == 3'b111) ? `FAST_PWM_OCR :
        `INVALID;



    assign top =
        (timer_mode == `NORMAL) ?
            8'd255 :
            (timer_mode == `CTC) ?
                mem_ocr0a :
                (timer_mode == `FAST_PWM_MAX) ?
                    8'd255 :
                    (timer_mode == `FAST_PWM_OCR) ?
                        mem_ocr0a :
                        8'd0;


    always @(posedge clk_t, posedge reset) begin
        if (reset) begin
            tcnt0 <= 0;
        end else begin

            if (mem_tcnt0 == top) begin
                tcnt0 <= {DATA_WIDTH{1'b0}};
            end else begin
                tcnt0 <= mem_tcnt0 + 1;
            end
        end
    end


    always @(posedge clk_t, posedge reset) begin
        if (reset) begin
            oc0a <= 0;
            oc0b <= 0;
        end else begin

            case (timer_mode)
                `NORMAL, `CTC : begin
                    case (com0a)
                        2'b00   : ;
                        2'b01   : if (mem_ocr0a == tcnt0) oc0a <= ~oc0a;
                        2'b10   : if (mem_ocr0a == tcnt0) oc0a <= 0;
                        2'b11   : if (mem_ocr0a == tcnt0) oc0a <= 1;
                        default : ;
                    endcase

                    case (com0b)
                        2'b00   : ;
                        2'b01   : if (mem_ocr0b == tcnt0) oc0b <= ~oc0b;
                        2'b10   : if (mem_ocr0b == tcnt0) oc0b <= 0;
                        2'b11   : if (mem_ocr0b == tcnt0) oc0b <= 1;
                        default : ;
                    endcase
                end
                `FAST_PWM_MAX, `FAST_PWM_OCR : begin
                    case (com0a)
                        2'b00   : ;
                        2'b01   : if (wgm0[2] && mem_ocr0a == tcnt0) oc0a <= ~oc0a;
                        2'b10   : if (mem_ocr0a == tcnt0) oc0a <= 0; else if (tcnt0 == 0) oc0a <= 1;
                        2'b11   : if (mem_ocr0a == tcnt0) oc0a <= 1; else if (tcnt0 == 0) oc0a <= 0;
                        default : ;
                    endcase

                    case (com0b)
                        2'b00   : ;
                        2'b01   : if ( wgm0[2] && mem_ocr0b == tcnt0) oc0b <= ~oc0b;
                        2'b10   : if (mem_ocr0b == tcnt0) oc0b <= 0; else if (tcnt0 == 0) oc0b <= 1;
                        2'b11   : if (mem_ocr0b == tcnt0) oc0b <= 1; else if (tcnt0 == 0) oc0b <= 0;
                        default : ;
                    endcase
                end
                default : begin
                    case (com0a)
                        default : ;
                    endcase

                    case (com0b)
                        default : ;
                    endcase
                end
            endcase
        end
    end

endmodule
module timer_unit #(parameter DATA_WIDTH = 8) (
    input  wire                      clk       ,
    input  wire                      reset     ,
    input  wire     [DATA_WIDTH-1:0] mem_ocr0a ,
    input  wire     [DATA_WIDTH-1:0] mem_ocr0b ,
    input  wire     [DATA_WIDTH-1:0] mem_tcnt0 ,
    input  wire     [DATA_WIDTH-1:0] mem_tccr0a,
    input  wire     [DATA_WIDTH-1:0] mem_tccr0b,
    output      reg [DATA_WIDTH-1:0] tcnt0     ,
    output      reg                  oc0a      ,
    output      reg                  oc0b
);



    wire clk_t;
    wire clk_io;
    wire clk_io_8;
    wire clk_io_64;
    wire clk_io_256;
    wire clk_io_1024;

    wire [ 7:0] clk_sources;
    reg  [13:0] count      ;

    always @(posedge clk, posedge reset) begin
        if (reset)
            count <= 0;
        else
            count <= count + 1;
    end



    assign clk_io      = clk;
    assign clk_io_8    = count[2];
    assign clk_io_64   = count[5];
    assign clk_io_256  = count[7];
    assign clk_io_1024 = count[9];





    assign clk_sources = {
        1'b0,
        1'b0,
        clk_io_1024,
        clk_io_256,
        clk_io_64,
        clk_io_8,
        clk_io,
        1'b0
    };



    assign clk_t = clk_sources[cs0];


    wire [1:0] com0a;
    wire [1:0] com0b;
    wire [2:0] wgm0 ;
    wire [2:0] cs0  ;



    assign com0a = mem_tccr0a[7:6];
    assign com0b = mem_tccr0a[5:4];
    assign wgm0  = {mem_tccr0b[3], mem_tccr0a[1:0]};
    assign cs0   = mem_tccr0b[2:0];

    wire [           5:0] timer_mode;
    wire [DATA_WIDTH-1:0] top       ;



    assign timer_mode =
        (wgm0 == 3'b000) ? `NORMAL :
        (wgm0 == 3'b010) ? `CTC :
        (wgm0 == 3'b011) ? `FAST_PWM_MAX :
        (wgm0 == 3'b111) ? `FAST_PWM_OCR :
        `INVALID;



    assign top =
        (timer_mode == `NORMAL) ?
            8'd255 :
            (timer_mode == `CTC) ?
                mem_ocr0a :
                (timer_mode == `FAST_PWM_MAX) ?
                    8'd255 :
                    (timer_mode == `FAST_PWM_OCR) ?
                        mem_ocr0a :
                        8'd0;


    always @(posedge clk_t, posedge reset) begin
        if (reset) begin
            tcnt0 <= 0;
        end else begin

            if (mem_tcnt0 == top) begin
                tcnt0 <= {DATA_WIDTH{1'b0}};
            end else begin
                tcnt0 <= mem_tcnt0 + 1;
            end
        end
    end


    always @(posedge clk_t, posedge reset) begin
        if (reset) begin
            oc0a <= 0;
            oc0b <= 0;
        end else begin

            case (timer_mode)
                `NORMAL, `CTC : begin
                    case (com0a)
                        2'b00   : ;
                        2'b01   : if (mem_ocr0a == tcnt0) oc0a <= ~oc0a;
                        2'b10   : if (mem_ocr0a == tcnt0) oc0a <= 0;
                        2'b11   : if (mem_ocr0a == tcnt0) oc0a <= 1;
                        default : ;
                    endcase

                    case (com0b)
                        2'b00   : ;
                        2'b01   : if (mem_ocr0b == tcnt0) oc0b <= ~oc0b;
                        2'b10   : if (mem_ocr0b == tcnt0) oc0b <= 0;
                        2'b11   : if (mem_ocr0b == tcnt0) oc0b <= 1;
                        default : ;
                    endcase
                end
                `FAST_PWM_MAX, `FAST_PWM_OCR : begin
                    case (com0a)
                        2'b00   : ;
                        2'b01   : if (wgm0[2] && mem_ocr0a == tcnt0) oc0a <= ~oc0a;
                        2'b10   : if (mem_ocr0a == tcnt0) oc0a <= 0; else if (tcnt0 == 0) oc0a <= 1;
                        2'b11   : if (mem_ocr0a == tcnt0) oc0a <= 1; else if (tcnt0 == 0) oc0a <= 0;
                        default : ;
                    endcase

                    case (com0b)
                        2'b00   : ;
                        2'b01   : if ( wgm0[2] && mem_ocr0b == tcnt0) oc0b <= ~oc0b;
                        2'b10   : if (mem_ocr0b == tcnt0) oc0b <= 0; else if (tcnt0 == 0) oc0b <= 1;
                        2'b11   : if (mem_ocr0b == tcnt0) oc0b <= 1; else if (tcnt0 == 0) oc0b <= 0;
                        default : ;
                    endcase
                end
                default : begin
                    case (com0a)
                        default : ;
                    endcase

                    case (com0b)
                        default : ;
                    endcase
                end
            endcase
        end
    end

endmodule