data/full_repos/permissive/449807379/CPU_design/registry_bank_full.v
1: b"%Error: data/full_repos/permissive/449807379/CPU_design/registry_bank_full.v:14: Cannot find file containing module: 'n_decoder'\nn_decoder d1(d_bits,wire1, ldr, ldr_wire);  \n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/449807379/CPU_design,data/full_repos/permissive/449807379/n_decoder\n             data/full_repos/permissive/449807379/CPU_design,data/full_repos/permissive/449807379/n_decoder.v\n             data/full_repos/permissive/449807379/CPU_design,data/full_repos/permissive/449807379/n_decoder.sv\n             n_decoder\n             n_decoder.v\n             n_decoder.sv\n             obj_dir/n_decoder\n             obj_dir/n_decoder.v\n             obj_dir/n_decoder.sv\n%Error: data/full_repos/permissive/449807379/CPU_design/registry_bank_full.v:15: Cannot find file containing module: 'reg_bank'\nreg_bank r1(ldr,wire1,out1,out2,out3,out4,out5,out6,out7,out8,out9,out10,out11,out12,out13,out14,out15,out16);  \n^~~~~~~~\n%Error: data/full_repos/permissive/449807379/CPU_design/registry_bank_full.v:16: Cannot find file containing module: 'n_mux'\nn_mux m1(out1,out2,out3,out4,out5,out6,out7,out8,out9,out10,out11,out12,out13,out14,out15,out16,s1_bits,out_m1);  \n^~~~~\n%Error: data/full_repos/permissive/449807379/CPU_design/registry_bank_full.v:17: Cannot find file containing module: 'n_mux'\nn_mux m2(out1,out2,out3,out4,out5,out6,out7,out8,out9,out10,out11,out12,out13,out14,out15,out16,s2_bits,out_m2);  \n^~~~~\n%Error: Exiting due to 4 error(s)\n"
module Registry_Bank_Full(ldr,d_bits,s1_bits,s2_bits,out_m1,out_m2);
parameter n = 32;
input [n-1:0] ldr;
input [3:0] d_bits,s1_bits,s2_bits;
output [n-1:0] out_m1,out_m2;
wire [n-1:0] out1,out2,out3,out4,out5,out6,out7,out8,out9,out10,out11,out12,out13,out14,out15,out16;
wire [15:0] wire1;



wire [31:0] ldr_wire;


n_decoder d1(d_bits,wire1, ldr, ldr_wire);
reg_bank r1(ldr,wire1,out1,out2,out3,out4,out5,out6,out7,out8,out9,out10,out11,out12,out13,out14,out15,out16);
n_mux m1(out1,out2,out3,out4,out5,out6,out7,out8,out9,out10,out11,out12,out13,out14,out15,out16,s1_bits,out_m1);
n_mux m2(out1,out2,out3,out4,out5,out6,out7,out8,out9,out10,out11,out12,out13,out14,out15,out16,s2_bits,out_m2);

endmodule
module Registry_Bank_Full(ldr,d_bits,s1_bits,s2_bits,out_m1,out_m2);

parameter n = 32;
input [n-1:0] ldr;
input [3:0] d_bits,s1_bits,s2_bits;
output [n-1:0] out_m1,out_m2;
wire [n-1:0] out1,out2,out3,out4,out5,out6,out7,out8,out9,out10,out11,out12,out13,out14,out15,out16;
wire [15:0] wire1;



wire [31:0] ldr_wire;


n_decoder d1(d_bits,wire1, ldr, ldr_wire);
reg_bank r1(ldr,wire1,out1,out2,out3,out4,out5,out6,out7,out8,out9,out10,out11,out12,out13,out14,out15,out16);
n_mux m1(out1,out2,out3,out4,out5,out6,out7,out8,out9,out10,out11,out12,out13,out14,out15,out16,s1_bits,out_m1);
n_mux m2(out1,out2,out3,out4,out5,out6,out7,out8,out9,out10,out11,out12,out13,out14,out15,out16,s2_bits,out_m2);

endmodule