data/full_repos/permissive/502135797/Lab8_April_20_2022/Code/BSUPDOWN.v
data/verilator_xmls/2b7d5515-01f6-44fa-a2fc-36ba45beb92d.xml
module BSUPDOWN(
    input clk1,
    output [1:0] s0,
    output [1:0] s1
    );
    reg [3:0] tmp;
    always@(posedge clk1)
    begin
          tmp <= tmp+1;
    end 
    assign s0[0] = tmp[0]; 
    assign s0[1] = tmp[2]; 
    assign s1[0] = tmp[1]; 
    assign s1[1] = tmp[3]; 
      
  

endmodule
module BSUPDOWN(
    input clk1,
    output [1:0] s0,
    output [1:0] s1
    );

    reg [3:0] tmp;
    always@(posedge clk1)
    begin
          tmp <= tmp+1;
    end 
    assign s0[0] = tmp[0]; 
    assign s0[1] = tmp[2]; 
    assign s1[0] = tmp[1]; 
    assign s1[1] = tmp[3]; 
      
  

endmodule