data/full_repos/permissive/441359809/src/yosys/tests/simple/graphtest.v
data/verilator_xmls/e4e98946-ac38-45f7-92d3-9b9946488fc8.xml
module graphtest (A,B,X,Y,Z);

input      [3:0] A;
input      [3:0] B;
output reg [3:0] X;
output     [9:0] Y;
output     [7:0] Z;

wire [4:0] t;

assign t[4] = 1'b0;
assign t[2:0] = A[2:0] & { 2'b10, B[3]};
assign t[3] = A[2] ^ B[3];




assign Y = {3'b111, A, t[2:0]};

assign Z[0] = 1'b0;
assign Z[1] = t[3];
assign Z[3:2] = A[2:1];
assign Z[7:4] = {1'b0, B[2:0]};

always @* begin
  if (A == 4'b1111) begin
    X = B;
  end
  else begin
    X = 4'b0000;
  end
end

endmodule
module graphtest (A,B,X,Y,Z);


input      [3:0] A;
input      [3:0] B;
output reg [3:0] X;
output     [9:0] Y;
output     [7:0] Z;

wire [4:0] t;

assign t[4] = 1'b0;
assign t[2:0] = A[2:0] & { 2'b10, B[3]};
assign t[3] = A[2] ^ B[3];




assign Y = {3'b111, A, t[2:0]};

assign Z[0] = 1'b0;
assign Z[1] = t[3];
assign Z[3:2] = A[2:1];
assign Z[7:4] = {1'b0, B[2:0]};

always @* begin
  if (A == 4'b1111) begin
    X = B;
  end
  else begin
    X = 4'b0000;
  end
end

endmodule