data/full_repos/permissive/434886680/al_ip/adc_core.v
1: b"%Error: data/full_repos/permissive/434886680/al_ip/adc_core.v:23: Cannot find file containing module: 'EG_PHY_ADC'\n EG_PHY_ADC #(\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/434886680/al_ip,data/full_repos/permissive/434886680/EG_PHY_ADC\n             data/full_repos/permissive/434886680/al_ip,data/full_repos/permissive/434886680/EG_PHY_ADC.v\n             data/full_repos/permissive/434886680/al_ip,data/full_repos/permissive/434886680/EG_PHY_ADC.sv\n             EG_PHY_ADC\n             EG_PHY_ADC.v\n             EG_PHY_ADC.sv\n             obj_dir/EG_PHY_ADC\n             obj_dir/EG_PHY_ADC.v\n             obj_dir/EG_PHY_ADC.sv\n%Error: Exiting due to 1 error(s)\n"
module adc_core ( eoc, dout, clk, pd, s, soc );
	output 		 eoc;
	output  		[11:0] dout;

	input  		clk;
	input  		pd;
	input  		[2:0] s;
	input  		soc;

	EG_PHY_ADC #(
		.CH0("ENABLE"))
		adc (
		.clk(clk),
		.pd(pd),
		.s(s),
		.soc(soc),
		.eoc(eoc),
		.dout(dout));

endmodule
module adc_core ( eoc, dout, clk, pd, s, soc );

	output 		 eoc;
	output  		[11:0] dout;

	input  		clk;
	input  		pd;
	input  		[2:0] s;
	input  		soc;

	EG_PHY_ADC #(
		.CH0("ENABLE"))
		adc (
		.clk(clk),
		.pd(pd),
		.s(s),
		.soc(soc),
		.eoc(eoc),
		.dout(dout));

endmodule