data/full_repos/permissive/458737381/src/verilog-parser/tests/initial_fork_join.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/initial_fork_join.v:5: Unsupported or unknown PLI call: $monitor\n $monitor("%g clk=%b reset=%b enable=%b data=%b", \n ^~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/initial_fork_join.v:7: Unsupported: fork statements\n fork\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/initial_fork_join.v:8: Unsupported: Ignoring delay on this delayed statement.\n   #1  clk = 0;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/initial_fork_join.v:9: Unsupported: Ignoring delay on this delayed statement.\n   #10 reset = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/initial_fork_join.v:10: Unsupported: Ignoring delay on this delayed statement.\n   #5  enable = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/initial_fork_join.v:11: Unsupported: Ignoring delay on this delayed statement.\n   #3  data = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/initial_fork_join.v:13: Unsupported: Ignoring delay on this delayed statement.\n #1 $display ("%g Terminating simulation", $time);\n ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module initial_fork_join();
reg clk,reset,enable,data;

initial begin
 $monitor("%g clk=%b reset=%b enable=%b data=%b", 
   $time, clk, reset, enable, data);
 fork
   #1  clk = 0;
   #10 reset = 0;
   #5  enable = 0;
   #3  data = 0;
 join
 #1 $display ("%g Terminating simulation", $time);
 $finish;
end

endmodule
module initial_fork_join();

reg clk,reset,enable,data;

initial begin
 $monitor("%g clk=%b reset=%b enable=%b data=%b", 
   $time, clk, reset, enable, data);
 fork
   #1  clk = 0;
   #10 reset = 0;
   #5  enable = 0;
   #3  data = 0;
 join
 #1 $display ("%g Terminating simulation", $time);
 $finish;
end

endmodule