data/full_repos/permissive/450922687/Task 2/Instruction_Memory.v
1: b'%Error: Cannot find file containing module: 2,data/full_repos/permissive/450922687\n        ... Looked in:\n             data/full_repos/permissive/450922687/Task/2,data/full_repos/permissive/450922687\n             data/full_repos/permissive/450922687/Task/2,data/full_repos/permissive/450922687.v\n             data/full_repos/permissive/450922687/Task/2,data/full_repos/permissive/450922687.sv\n             2,data/full_repos/permissive/450922687\n             2,data/full_repos/permissive/450922687.v\n             2,data/full_repos/permissive/450922687.sv\n             obj_dir/2,data/full_repos/permissive/450922687\n             obj_dir/2,data/full_repos/permissive/450922687.v\n             obj_dir/2,data/full_repos/permissive/450922687.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/450922687/Task\n%Error: Cannot find file containing module: 2/Instruction_Memory.v\n%Error: Exiting due to 3 error(s)\n'
module Instruction_Memory(input [63:0] Inst_Address,
                          output reg [31:0] Instruction);
  reg [7:0] registers [15:0];
  initial 
    begin
 







registers[11] = 8'b00000000;
registers[10] = 8'b11000010;
registers[9] = 8'b10000110;
registers[8] = 8'b10110011;
      


registers[7] = 8'b01000000;
registers[6] = 8'b00111001;
registers[5] = 8'b10000110;
registers[4] = 8'b00110011;



registers[3] = 8'b00000000;
registers[2] = 8'b00010000;
registers[1] = 8'b00001001;
registers[0] = 8'b10110011; 





                 
    end                 
  always @(Inst_Address) 
    begin
      assign Instruction = {registers[Inst_Address+3], registers[Inst_Address+2],
       registers[Inst_Address+1], registers[Inst_Address]};
    end
endmodule
module Instruction_Memory(input [63:0] Inst_Address,
                          output reg [31:0] Instruction);

  reg [7:0] registers [15:0];
  initial 
    begin
 







registers[11] = 8'b00000000;
registers[10] = 8'b11000010;
registers[9] = 8'b10000110;
registers[8] = 8'b10110011;
      


registers[7] = 8'b01000000;
registers[6] = 8'b00111001;
registers[5] = 8'b10000110;
registers[4] = 8'b00110011;



registers[3] = 8'b00000000;
registers[2] = 8'b00010000;
registers[1] = 8'b00001001;
registers[0] = 8'b10110011; 





                 
    end                 
  always @(Inst_Address) 
    begin
      assign Instruction = {registers[Inst_Address+3], registers[Inst_Address+2],
       registers[Inst_Address+1], registers[Inst_Address]};
    end
endmodule