data/full_repos/permissive/528677531/LAB-5/Q4/q.v
data/verilator_xmls/77be3bd7-ea99-4cf7-bfb9-12ca711ebb45.xml
module comp2(a,b,aeqb,agtb,altb);
input [1:0]a,b;
output aeqb,agtb,altb;
assign aeqb=(~(a[0]^b[0]))&(~(a[1]^b[1]));
assign agtb=(a[1]&~b[1])|((~(a[1]^b[1]))&a[0]&~b[0]);
assign altb=~(aeqb|agtb);
endmodule
module comp2(a,b,aeqb,agtb,altb);

input [1:0]a,b;
output aeqb,agtb,altb;
assign aeqb=(~(a[0]^b[0]))&(~(a[1]^b[1]));
assign agtb=(a[1]&~b[1])|((~(a[1]^b[1]))&a[0]&~b[0]);
assign altb=~(aeqb|agtb);
endmodule