data/full_repos/permissive/412297935/hdl/xe_host.v
1: b'%Error: data/full_repos/permissive/412297935/hdl/xe_host.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/412297935/hdl,data/full_repos/permissive/412297935/defines.v\n             data/full_repos/permissive/412297935/hdl,data/full_repos/permissive/412297935/defines.v.v\n             data/full_repos/permissive/412297935/hdl,data/full_repos/permissive/412297935/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/412297935/hdl/xe_host.v:297: Define or directive not defined: \'`XIO_CMD_SDRAM_READ\'\n                    xCmd            <= `XIO_CMD_SDRAM_READ;\n                                       ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/412297935/hdl/xe_host.v:297: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n                    xCmd            <= `XIO_CMD_SDRAM_READ;\n                                                          ^\n%Error: Exiting due to 3 error(s)\n'
module xe_host
	#(parameter ANUM=8)
    (

	input				a8_clk,
	input				a8_rd5,
	input				a8_rd4,
	output reg			a8_irq_n,
	output   			a8_mpd_n,
	output   			a8_extsel_n,
    

	input	    [15:0]	a8_a_IN,
    output  reg [15:0]  a8_a_OUT,
    output  reg [15:0]  a8_a_OE,

   	input	    [7:0]   a8_d_IN,
    output  reg [7:0]   a8_d_OUT,
    output  reg [7:0]   a8_d_OE,
  
	input				a8_halt_n_IN,
	output	reg			a8_halt_n_OUT,
	output	reg			a8_halt_n_OE,
  
  	input				a8_ref_n_IN,
  	output	reg			a8_ref_n_OUT,
  	output	reg			a8_ref_n_OE,

    input				a8_rst_n_IN,
    output	reg			a8_rst_n_OUT,
    output	reg			a8_rst_n_OE,

 	input				a8_rw_IN,
	output	reg			a8_rw_OUT,
	output	reg			a8_rw_OE,
   

    output  reg         a8_a_dir,
    output  reg         a8_d_dir,
    output  reg         a8_halt_dir,
    output  reg         a8_ref_dir,
    output  reg         a8_rst_dir,
    output  reg         a8_rw_dir,
 

   	input	    [7:0]   xio_data_IN,
    output      [7:0]   xio_data_OUT,
    output      [7:0]   xio_data_OE,
  
    output              xio_host_clk,
    output              xio_host_rts,
    input               xio_host_cts,
    
    input               xio_box_clk,
    input               xio_box_rts,
    output              xio_box_cts,
 
	input	            sysclk,
    input               pll0_locked
 );




	genvar i;
	



    wire 		a8_addr_strobe;
    wire		a8_read_strobe;
    wire		a8_write_strobe;		
	wire		a8_clk_falling;
	
	BusMonitor busMon
		(
		.clk(sysclk),
		.a8_clk(a8_clk),
		.a8_rst_n(a8_rst_n_IN),
		.a8_addr_strobe(a8_addr_strobe),
		.a8_write_strobe(a8_write_strobe),
		.a8_read_strobe(a8_read_strobe),
		.a8_clk_falling(a8_clk_falling)
		);
	



	wire [ANUM-1:0] inRange;
	wire [7:0] apCfg [0:ANUM-1];
	wire apCfgValid[ANUM-1:0];
	wire [31:0] apBase [0:ANUM-1];
	
	generate for (i=0; i<ANUM; i=i+1)
		begin		
			Aperture aperture
				(
				.clk(sysclk),
				.a8_rst_n(a8_rst_n_IN),
				.a8_rw_n(a8_rw_IN),
				.a8_data(a8_d_IN),
				.a8_addr(a8_a_IN),
				.wValid(a8_write_strobe),
				.aValid(a8_addr_strobe),
				.index(i[3:0]),
				.inRange(inRange[i]),
				.apCfg(apCfg[i]),
				.apCfgValid(apCfgValid[i]),
				.baseAddr(apBase[i])
				);
		end
	endgenerate
	




   	wire [$clog2(ANUM):0] apIndex;
    PriorityEncoder pEnc
    	(
    	.bits(inRange),
    	.index(apIndex)
    	);
    	




	reg 		extAccessValid;
	
	always @(posedge sysclk)
		if (a8_rst_n_IN == 1'b0)
			extAccessValid	<= 1'b0;
		

		else if (apIndex[3] == 1'b0) 
			extAccessValid	<= 1'b1;
 

        else if  (a8_clk_falling == 1'b1)
			extAccessValid	<= 1'b0;
		
    wire sdramRead 	        = (a8_rw_IN == 1'b1) & extAccessValid;
    assign a8_mpd_n		    = ~sdramRead;
    assign a8_extsel_n	    = ~sdramRead;




    reg     [31:0]  sdramBase;
	reg 	    	sdramValid;

	
	always @(posedge sysclk)
		if (a8_rst_n_IN == 1'b0)
			begin
				sdramBase 	<= 32'b0;
				sdramValid	<= 1'b0;
			end
			
		else if (apIndex[3] == 1'b1)
			begin
				if (a8_clk_falling)
					sdramValid		<= 1'b0;
			end
		else
			begin
				sdramValid 	<= 1'b1;
				case (apIndex[2:0])
					3'h0    : sdramBase  <= apBase[0];                        
					3'h1    : sdramBase  <= apBase[1];                        
					3'h2    : sdramBase  <= apBase[2];                        
					3'h3    : sdramBase  <= apBase[3];                        
					3'h4    : sdramBase  <= apBase[4];                        
					3'h5    : sdramBase  <= apBase[5];                        
					3'h6    : sdramBase  <= apBase[6];                        
					3'h7    : sdramBase  <= apBase[7];                        
				endcase
			end
    
    wire [31:0] sdramAddr = sdramBase + {24'b0,a8_a_IN[7:0]};

       



    reg             sdramLast;
    
    always @ (posedge sysclk)
        if (a8_rst_n == 1'b0)
            begin
                sdramLast       <= 1'b0;
            end
        else
            sdramLast <= sdramValid;
     



    reg     [31:0]  xData;
    reg     [3:0]   xCmd;
    reg             xCmdValid;
    
    xio_bus xio
        (
		.clk(sysclk),
		.rst_n(a8_rst_n),
        .rData(xio_data_IN),
        .rRts(xio_box_rts),
        .rClk(xio_box_clk),
        .rCts(xio_box_cts),
        .wData(xio_data_OUT),
        .wEn(xio_data_OE),
        .wRts(xio_host_rts),
        .wClk(xio_host_clk),
        .wCts(xio_host_cts),
        .data(xData),
        .cmd(xCmd),
        .cmdValid(xCmdValid)
        );

     
       



    always @ (posedge sysclk)
        begin
            if (a8_rst_n == 1'b0)
                begin
                    xCmdValid       <= 1'b0;
                    xCmd            <= 4'h0;
                    xData           <= 31'h0;
                end
            else if (xCmdValid == 1'b1)
                xCmdValid <= 1'b0;
            else if ((sdramValid == 1'b1) && (sdramLast == 1'b0))
                begin
                    xCmdValid       <= 1'b1;
                    xData           <= sdramAddr;
                    xCmd            <= `XIO_CMD_SDRAM_READ;
                end
        end
        
endmodule
module xe_host
	#(parameter ANUM=8)
    (

	input				a8_clk,
	input				a8_rd5,
	input				a8_rd4,
	output reg			a8_irq_n,
	output   			a8_mpd_n,
	output   			a8_extsel_n,
    

	input	    [15:0]	a8_a_IN,
    output  reg [15:0]  a8_a_OUT,
    output  reg [15:0]  a8_a_OE,

   	input	    [7:0]   a8_d_IN,
    output  reg [7:0]   a8_d_OUT,
    output  reg [7:0]   a8_d_OE,
  
	input				a8_halt_n_IN,
	output	reg			a8_halt_n_OUT,
	output	reg			a8_halt_n_OE,
  
  	input				a8_ref_n_IN,
  	output	reg			a8_ref_n_OUT,
  	output	reg			a8_ref_n_OE,

    input				a8_rst_n_IN,
    output	reg			a8_rst_n_OUT,
    output	reg			a8_rst_n_OE,

 	input				a8_rw_IN,
	output	reg			a8_rw_OUT,
	output	reg			a8_rw_OE,
   

    output  reg         a8_a_dir,
    output  reg         a8_d_dir,
    output  reg         a8_halt_dir,
    output  reg         a8_ref_dir,
    output  reg         a8_rst_dir,
    output  reg         a8_rw_dir,
 

   	input	    [7:0]   xio_data_IN,
    output      [7:0]   xio_data_OUT,
    output      [7:0]   xio_data_OE,
  
    output              xio_host_clk,
    output              xio_host_rts,
    input               xio_host_cts,
    
    input               xio_box_clk,
    input               xio_box_rts,
    output              xio_box_cts,
 
	input	            sysclk,
    input               pll0_locked
 );





	genvar i;
	



    wire 		a8_addr_strobe;
    wire		a8_read_strobe;
    wire		a8_write_strobe;		
	wire		a8_clk_falling;
	
	BusMonitor busMon
		(
		.clk(sysclk),
		.a8_clk(a8_clk),
		.a8_rst_n(a8_rst_n_IN),
		.a8_addr_strobe(a8_addr_strobe),
		.a8_write_strobe(a8_write_strobe),
		.a8_read_strobe(a8_read_strobe),
		.a8_clk_falling(a8_clk_falling)
		);
	



	wire [ANUM-1:0] inRange;
	wire [7:0] apCfg [0:ANUM-1];
	wire apCfgValid[ANUM-1:0];
	wire [31:0] apBase [0:ANUM-1];
	
	generate for (i=0; i<ANUM; i=i+1)
		begin		
			Aperture aperture
				(
				.clk(sysclk),
				.a8_rst_n(a8_rst_n_IN),
				.a8_rw_n(a8_rw_IN),
				.a8_data(a8_d_IN),
				.a8_addr(a8_a_IN),
				.wValid(a8_write_strobe),
				.aValid(a8_addr_strobe),
				.index(i[3:0]),
				.inRange(inRange[i]),
				.apCfg(apCfg[i]),
				.apCfgValid(apCfgValid[i]),
				.baseAddr(apBase[i])
				);
		end
	endgenerate
	




   	wire [$clog2(ANUM):0] apIndex;
    PriorityEncoder pEnc
    	(
    	.bits(inRange),
    	.index(apIndex)
    	);
    	




	reg 		extAccessValid;
	
	always @(posedge sysclk)
		if (a8_rst_n_IN == 1'b0)
			extAccessValid	<= 1'b0;
		

		else if (apIndex[3] == 1'b0) 
			extAccessValid	<= 1'b1;
 

        else if  (a8_clk_falling == 1'b1)
			extAccessValid	<= 1'b0;
		
    wire sdramRead 	        = (a8_rw_IN == 1'b1) & extAccessValid;
    assign a8_mpd_n		    = ~sdramRead;
    assign a8_extsel_n	    = ~sdramRead;




    reg     [31:0]  sdramBase;
	reg 	    	sdramValid;

	
	always @(posedge sysclk)
		if (a8_rst_n_IN == 1'b0)
			begin
				sdramBase 	<= 32'b0;
				sdramValid	<= 1'b0;
			end
			
		else if (apIndex[3] == 1'b1)
			begin
				if (a8_clk_falling)
					sdramValid		<= 1'b0;
			end
		else
			begin
				sdramValid 	<= 1'b1;
				case (apIndex[2:0])
					3'h0    : sdramBase  <= apBase[0];                        
					3'h1    : sdramBase  <= apBase[1];                        
					3'h2    : sdramBase  <= apBase[2];                        
					3'h3    : sdramBase  <= apBase[3];                        
					3'h4    : sdramBase  <= apBase[4];                        
					3'h5    : sdramBase  <= apBase[5];                        
					3'h6    : sdramBase  <= apBase[6];                        
					3'h7    : sdramBase  <= apBase[7];                        
				endcase
			end
    
    wire [31:0] sdramAddr = sdramBase + {24'b0,a8_a_IN[7:0]};

       



    reg             sdramLast;
    
    always @ (posedge sysclk)
        if (a8_rst_n == 1'b0)
            begin
                sdramLast       <= 1'b0;
            end
        else
            sdramLast <= sdramValid;
     



    reg     [31:0]  xData;
    reg     [3:0]   xCmd;
    reg             xCmdValid;
    
    xio_bus xio
        (
		.clk(sysclk),
		.rst_n(a8_rst_n),
        .rData(xio_data_IN),
        .rRts(xio_box_rts),
        .rClk(xio_box_clk),
        .rCts(xio_box_cts),
        .wData(xio_data_OUT),
        .wEn(xio_data_OE),
        .wRts(xio_host_rts),
        .wClk(xio_host_clk),
        .wCts(xio_host_cts),
        .data(xData),
        .cmd(xCmd),
        .cmdValid(xCmdValid)
        );

     
       



    always @ (posedge sysclk)
        begin
            if (a8_rst_n == 1'b0)
                begin
                    xCmdValid       <= 1'b0;
                    xCmd            <= 4'h0;
                    xData           <= 31'h0;
                end
            else if (xCmdValid == 1'b1)
                xCmdValid <= 1'b0;
            else if ((sdramValid == 1'b1) && (sdramLast == 1'b0))
                begin
                    xCmdValid       <= 1'b1;
                    xData           <= sdramAddr;
                    xCmd            <= `XIO_CMD_SDRAM_READ;
                end
        end
        
endmodule