data/full_repos/permissive/512928021/otp/impl/hw/soc/pwr.v
data/verilator_xmls/19a3e142-60f8-4a73-a62f-b5d38f49b793.xml
module pwr #(
    parameter [31:0] ADDR = 32'hffff_ffff
) (
    input clk,
    input resetn,
    input mem_valid,
    input [31:0] mem_addr,
    input [31:0] mem_wdata,
    input [3:0] mem_wstrb,
    output pwr_ready,
    output pwr_sel,
    output reg poweroff_rq
);




assign pwr_sel = mem_valid && (mem_addr == ADDR);

assign pwr_ready = 1;


always @(posedge clk) begin
    if (!resetn) begin
        poweroff_rq <= 0;
    end else if (pwr_sel && mem_wstrb[0]) begin
        poweroff_rq <= mem_wdata[7:0] != 0;
    end
end

endmodule
module pwr #(
    parameter [31:0] ADDR = 32'hffff_ffff
) (
    input clk,
    input resetn,
    input mem_valid,
    input [31:0] mem_addr,
    input [31:0] mem_wdata,
    input [3:0] mem_wstrb,
    output pwr_ready,
    output pwr_sel,
    output reg poweroff_rq
);





assign pwr_sel = mem_valid && (mem_addr == ADDR);

assign pwr_ready = 1;


always @(posedge clk) begin
    if (!resetn) begin
        poweroff_rq <= 0;
    end else if (pwr_sel && mem_wstrb[0]) begin
        poweroff_rq <= mem_wdata[7:0] != 0;
    end
end

endmodule