data/full_repos/permissive/432564927/Lab3 (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new/CPU.v
1: b'%Error: Cannot find file containing module: (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927\n        ... Looked in:\n             data/full_repos/permissive/432564927/Lab3/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927\n             data/full_repos/permissive/432564927/Lab3/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             data/full_repos/permissive/432564927/Lab3/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927\n             (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             obj_dir/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927\n             obj_dir/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             obj_dir/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/432564927/Lab3\n%Error: Cannot find file containing module: (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new/CPU.v\n%Error: Exiting due to 3 error(s)\n'
module ControlUnit(op, func, aluc, wreg, m2reg, wmem, aluimm, regrt);
    input [5:0] op;
    input [5:0] func;
    output reg [3:0] aluc;
    output reg wreg,m2reg,wmem,aluimm,regrt;
    
    initial begin
        wreg <= 0;
        m2reg <= 0;
        wmem <= 0;
        aluimm <= 0;
        regrt <= 0;
    end
    
    always@(op,func) begin
        if (op == 0)
        begin
            case(func)
                32: aluc <=2;
                34: aluc <= 6;
                    36: aluc <= 0;
                    37: aluc <= 1;
                    39: aluc <= 12;
                    42: aluc <= 7;
                    default aluc <= 15;
            endcase
            wreg <= 1;
            m2reg <= 0;
            wmem <= 0;
            aluimm <= 0;
            regrt <= 1;
        end
    
        if(op == 6'b100011)
        begin
            aluc <= 2;
            wreg <= 1;
            m2reg <= 1;
            wmem <= 0;
            aluimm <= 1;
            regrt <= 0;
        end
        if (op == 6'b101011)
        begin
            aluc <= 2;
            wreg <= 0;
            wmem <= 1;
            aluimm <= 1;
        end
        if (op == 6'b000100)
        begin
            aluc <= 6;
            wreg <= 0;
            wmem <= 0;
            aluimm <= 0;
        end
    end
endmodule
module ControlUnit(op, func, aluc, wreg, m2reg, wmem, aluimm, regrt);

    input [5:0] op;
    input [5:0] func;
    output reg [3:0] aluc;
    output reg wreg,m2reg,wmem,aluimm,regrt;
    
    initial begin
        wreg <= 0;
        m2reg <= 0;
        wmem <= 0;
        aluimm <= 0;
        regrt <= 0;
    end
    
    always@(op,func) begin
        if (op == 0)
        begin
            case(func)
                32: aluc <=2;
                34: aluc <= 6;
                    36: aluc <= 0;
                    37: aluc <= 1;
                    39: aluc <= 12;
                    42: aluc <= 7;
                    default aluc <= 15;
            endcase
            wreg <= 1;
            m2reg <= 0;
            wmem <= 0;
            aluimm <= 0;
            regrt <= 1;
        end
    
        if(op == 6'b100011)
        begin
            aluc <= 2;
            wreg <= 1;
            m2reg <= 1;
            wmem <= 0;
            aluimm <= 1;
            regrt <= 0;
        end
        if (op == 6'b101011)
        begin
            aluc <= 2;
            wreg <= 0;
            wmem <= 1;
            aluimm <= 1;
        end
        if (op == 6'b000100)
        begin
            aluc <= 6;
            wreg <= 0;
            wmem <= 0;
            aluimm <= 0;
        end
    end
endmodule