data/full_repos/permissive/419809304/verilog/rtl/ibex/ibex_register_file_latch.v
1: b'%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/ibex_register_file_latch.v:43: Cannot find file containing module: \'prim_clock_gating\'\n prim_clock_gating cg_we_global(\n ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/419809304/verilog/rtl/ibex,data/full_repos/permissive/419809304/prim_clock_gating\n             data/full_repos/permissive/419809304/verilog/rtl/ibex,data/full_repos/permissive/419809304/prim_clock_gating.v\n             data/full_repos/permissive/419809304/verilog/rtl/ibex,data/full_repos/permissive/419809304/prim_clock_gating.sv\n             prim_clock_gating\n             prim_clock_gating.v\n             prim_clock_gating.sv\n             obj_dir/prim_clock_gating\n             obj_dir/prim_clock_gating.v\n             obj_dir/prim_clock_gating.sv\n%Warning-WIDTH: data/full_repos/permissive/419809304/verilog/rtl/ibex/ibex_register_file_latch.v:51: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'sh0\' generates 1 bits.\n                                                                                                   : ... In instance ibex_register_file_latch\n   wdata_a_q <= 1\'sb0;\n             ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/419809304/verilog/rtl/ibex/ibex_register_file_latch.v:64: Operator FUNCREF \'sv2v_cast_5_signed\' expects 5 bits on the Function Argument, but Function Argument\'s VARREF \'i\' generates 32 bits.\n                                                                                                   : ... In instance ibex_register_file_latch\n     if (we_a_i && (waddr_a_int == sv2v_cast_5_signed(i)))\n                                   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/ibex_register_file_latch.v:74: Cannot find file containing module: \'prim_clock_gating\'\n   prim_clock_gating cg_i(\n   ^~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/419809304/verilog/rtl/ibex/ibex_register_file_latch.v:112: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'sh0\' generates 1 bits.\n                                                                                                    : ... In instance ibex_register_file_latch\n   assign sv2v_tmp_450E3 = 1\'sb0;\n                         ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
function automatic signed [4:0] sv2v_cast_5_signed;
		input reg signed [4:0] inp;
		sv2v_cast_5_signed = inp;
	endfunction
function automatic signed [4:0] sv2v_cast_5_signed;

		input reg signed [4:0] inp;
		sv2v_cast_5_signed = inp;
	endfunction