data/full_repos/permissive/408955603/Sesion3/pruebaModuloComp.v
1: b'%Error: data/full_repos/permissive/408955603/Sesion3/pruebaModuloComp.v:25: Unsupported or unknown PLI call: $monitor\n  $monitor($time, " | %b %b | %b %b %b", a, b, mayor, igual, menor);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion3/pruebaModuloComp.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #5 a = 0; b = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion3/pruebaModuloComp.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #5 a = 1; b = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion3/pruebaModuloComp.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #5 a = 1; b = 1;\n  ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Comp1(output wire mayor, 
	output wire igual, 
	output wire menor,
	input wire a,
	input wire b
);
	wire na, nb;

	not n1(na, a);
	not n2(nb, b);

	and a1(mayor, a, nb);
	and a2(menor, b, na);
	nor no1(igual, mayor, menor);
endmodule
module Comp1(output wire mayor, 
	output wire igual, 
	output wire menor,
	input wire a,
	input wire b
);

	wire na, nb;

	not n1(na, a);
	not n2(nb, b);

	and a1(mayor, a, nb);
	and a2(menor, b, na);
	nor no1(igual, mayor, menor);
endmodule