data/full_repos/permissive/51449864/verilog/seven_segment.v
1: b'%Warning-WIDTH: data/full_repos/permissive/51449864/verilog/seven_segment.v:42: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4f\' generates 7 bits.\n                                                                              : ... In instance seven_segment_mux.decoder\n   4\'h1 : segments = 7\'b1001111;\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/51449864/verilog/seven_segment.v:43: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h12\' generates 7 bits.\n                                                                              : ... In instance seven_segment_mux.decoder\n   4\'h2 : segments = 7\'b0010010;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/51449864/verilog/seven_segment.v:44: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h6\' generates 7 bits.\n                                                                              : ... In instance seven_segment_mux.decoder\n   4\'h3 : segments = 7\'b0000110;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/51449864/verilog/seven_segment.v:45: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4c\' generates 7 bits.\n                                                                              : ... In instance seven_segment_mux.decoder\n   4\'h4 : segments = 7\'b1001100;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/51449864/verilog/seven_segment.v:46: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h24\' generates 7 bits.\n                                                                              : ... In instance seven_segment_mux.decoder\n   4\'h5 : segments = 7\'b0100100;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/51449864/verilog/seven_segment.v:47: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h20\' generates 7 bits.\n                                                                              : ... In instance seven_segment_mux.decoder\n   4\'h6 : segments = 7\'b0100000;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/51449864/verilog/seven_segment.v:48: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'hf\' generates 7 bits.\n                                                                              : ... In instance seven_segment_mux.decoder\n   4\'h7 : segments = 7\'b0001111;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/51449864/verilog/seven_segment.v:49: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n                                                                              : ... In instance seven_segment_mux.decoder\n   4\'h8 : segments = 7\'b0000000;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/51449864/verilog/seven_segment.v:50: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h4\' generates 7 bits.\n                                                                              : ... In instance seven_segment_mux.decoder\n   4\'h9 : segments = 7\'b0000100;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/51449864/verilog/seven_segment.v:51: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h8\' generates 7 bits.\n                                                                              : ... In instance seven_segment_mux.decoder\n   4\'hA : segments = 7\'b0001000; \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/51449864/verilog/seven_segment.v:52: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h60\' generates 7 bits.\n                                                                              : ... In instance seven_segment_mux.decoder\n   4\'hB : segments = 7\'b1100000;  \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/51449864/verilog/seven_segment.v:53: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h31\' generates 7 bits.\n                                                                              : ... In instance seven_segment_mux.decoder\n   4\'hC : segments = 7\'b0110001; \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/51449864/verilog/seven_segment.v:54: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h42\' generates 7 bits.\n                                                                              : ... In instance seven_segment_mux.decoder\n   4\'hD : segments = 7\'b1000010;  \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/51449864/verilog/seven_segment.v:55: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h30\' generates 7 bits.\n                                                                              : ... In instance seven_segment_mux.decoder\n   4\'hE : segments = 7\'b0110000; \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/51449864/verilog/seven_segment.v:56: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h38\' generates 7 bits.\n                                                                              : ... In instance seven_segment_mux.decoder\n   4\'hF : segments = 7\'b0111000; \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/51449864/verilog/seven_segment.v:57: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h1\' generates 7 bits.\n                                                                              : ... In instance seven_segment_mux.decoder\n   4\'h0 : segments = 7\'b0000001;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/51449864/verilog/seven_segment.v:58: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h7f\' generates 7 bits.\n                                                                              : ... In instance seven_segment_mux.decoder\n   default : segments = 7\'b1111111;\n                      ^\n%Error: Exiting due to 17 warning(s)\n'
function integer clog2;
	input integer value;
	begin
		value = value-1;
		for (clog2 = 0; value > 0; clog2 = clog2 + 1)
			value = value >> 1;
		end
	endfunction
function integer clog2;

	input integer value;
	begin
		value = value-1;
		for (clog2 = 0; value > 0; clog2 = clog2 + 1)
			value = value >> 1;
		end
	endfunction