data/full_repos/permissive/434840709/作业/if语句/cg.v
data/verilator_xmls/df80bb01-bcdc-4fe5-a928-205c3d99ed51.xml
module top_module(

                input a,

                input b,

                input sel_b1,

                input sel_b2,

                output wire out_assign,

                output reg out_always   ); 

assign out_assign = (sel_b1&sel_b2)?b:a;

always @(*)
        out_always = (sel_b1&sel_b2)?b:a;

endmodule
module top_module(

                input a,

                input b,

                input sel_b1,

                input sel_b2,

                output wire out_assign,

                output reg out_always   );
 

assign out_assign = (sel_b1&sel_b2)?b:a;

always @(*)
        out_always = (sel_b1&sel_b2)?b:a;

endmodule