data/full_repos/permissive/510695465/ALU.v
data/verilator_xmls/d0dd1762-a11c-4351-8fc2-7c07d8b23bc6.xml
module ALU(input [7:0] A, input [7:0] B, input Control, output reg [7:0] Result, output reg Zero);

always @ (A,B,Control)
begin
	case (Control)
	1'b0: Result = A + B;
	1'b1: Result = A << B;
	endcase
	if (Result == 0) Zero = 1; else Zero = 0;
end
endmodule
module ALU(input [7:0] A, input [7:0] B, input Control, output reg [7:0] Result, output reg Zero);


always @ (A,B,Control)
begin
	case (Control)
	1'b0: Result = A + B;
	1'b1: Result = A << B;
	endcase
	if (Result == 0) Zero = 1; else Zero = 0;
end
endmodule