data/full_repos/permissive/447976230/fpga/usrp2/custom/custom_dsp_rx.v
data/verilator_xmls/ae069690-3e09-46f4-8b78-747737b85cfe.xml
module custom_dsp_rx
#(

    parameter WIDTH = 24
)
(

    input clock,
    input reset,
    input clear,
    input enable,


    input set_stb, input [7:0] set_addr, input [31:0] set_data,


    input [WIDTH-1:0] frontend_i,
    input [WIDTH-1:0] frontend_q,


    output [WIDTH-1:0] ddc_in_i,
    output [WIDTH-1:0] ddc_in_q,


    input [31:0] ddc_out_sample,
    input ddc_out_strobe,
    output ddc_out_enable,


    output [31:0] bb_sample,
    output bb_strobe
);

    assign ddc_in_i = frontend_i;
    assign ddc_in_q = frontend_q;
    assign bb_sample = ddc_out_sample;
    assign bb_strobe = ddc_out_strobe;
    assign ddc_out_enable = enable;

endmodule
module custom_dsp_rx
#(

    parameter WIDTH = 24
)
(

    input clock,
    input reset,
    input clear,
    input enable,


    input set_stb, input [7:0] set_addr, input [31:0] set_data,


    input [WIDTH-1:0] frontend_i,
    input [WIDTH-1:0] frontend_q,


    output [WIDTH-1:0] ddc_in_i,
    output [WIDTH-1:0] ddc_in_q,


    input [31:0] ddc_out_sample,
    input ddc_out_strobe,
    output ddc_out_enable,


    output [31:0] bb_sample,
    output bb_strobe
);


    assign ddc_in_i = frontend_i;
    assign ddc_in_q = frontend_q;
    assign bb_sample = ddc_out_sample;
    assign bb_strobe = ddc_out_strobe;
    assign ddc_out_enable = enable;

endmodule