data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld/ps_power_regs.v
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld/ps_power_regs.v:47: Cannot find include file: regmap/ps_power_regmap_utils.vh\n  `include "regmap/ps_power_regmap_utils.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld,data/full_repos/permissive/447976230/regmap/ps_power_regmap_utils.vh\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld,data/full_repos/permissive/447976230/regmap/ps_power_regmap_utils.vh.v\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld,data/full_repos/permissive/447976230/regmap/ps_power_regmap_utils.vh.sv\n             regmap/ps_power_regmap_utils.vh\n             regmap/ps_power_regmap_utils.vh.v\n             regmap/ps_power_regmap_utils.vh.sv\n             obj_dir/regmap/ps_power_regmap_utils.vh\n             obj_dir/regmap/ps_power_regmap_utils.vh.v\n             obj_dir/regmap/ps_power_regmap_utils.vh.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/cpld/ps_power_regs.v:48: Cannot find include file: ../../../lib/rfnoc/core/ctrlport.vh\n  `include "../../../lib/rfnoc/core/ctrlport.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module ps_power_regs #(
  parameter BASE_ADDRESS  = 0,
  parameter NUM_ADDRESSES = 32
) (
  input wire ctrlport_clk,
  input wire ctrlport_rst,


  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [31:0] s_ctrlport_req_data,

  output reg         s_ctrlport_resp_ack,
  output reg  [ 1:0] s_ctrlport_resp_status,
  output reg  [31:0] s_ctrlport_resp_data,


  output reg         ipass_power_disable = 1'b0,
  input  wire [ 1:0] ipass_power_fault_n,


  output reg         osc_100_en,
  output reg         osc_122_88_en
);

  `include "regmap/ps_power_regmap_utils.vh"
  `include "../../../lib/rfnoc/core/ctrlport.vh"





  wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) &&
                          (s_ctrlport_req_addr < BASE_ADDRESS + NUM_ADDRESSES);





  reg [1:0] ipass_power_sticky = 2'b00;
  reg [1:0] ipass_clear_sticky = 2'b00;





  always @(posedge ctrlport_clk) begin

    if (ctrlport_rst) begin
      ipass_power_disable    <= 1'b0;
      s_ctrlport_resp_ack    <= 1'b0;
      s_ctrlport_resp_status <= CTRL_STS_OKAY;
      s_ctrlport_resp_data   <= {CTRLPORT_ADDR_W {1'bx}};

      osc_100_en    <= 1'b0;
      osc_122_88_en <= 1'b0;

    end else begin

      ipass_clear_sticky <= 2'b00;


      if (s_ctrlport_req_wr) begin

        s_ctrlport_resp_ack    <= 1'b1;
        s_ctrlport_resp_status <= CTRL_STS_OKAY;
        s_ctrlport_resp_data   <= {CTRLPORT_ADDR_W {1'bx}};

        case (s_ctrlport_req_addr)
          BASE_ADDRESS + IPASS_POWER_REG: begin
            ipass_power_disable   <= s_ctrlport_req_data[IPASS_DISABLE_POWER_BIT];
            ipass_clear_sticky[0] <= s_ctrlport_req_data[IPASS_CLEAR_POWER_FAULT0];
            ipass_clear_sticky[1] <= s_ctrlport_req_data[IPASS_CLEAR_POWER_FAULT1];
          end

          BASE_ADDRESS + OSC_POWER_REG: begin
            osc_100_en    <= s_ctrlport_req_data[OSC_100];
            osc_122_88_en <= s_ctrlport_req_data[OSC_122_88];
          end


          default: begin
            if (address_in_range) begin
              s_ctrlport_resp_status <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack <= 1'b0;
            end
          end
        endcase


      end else if (s_ctrlport_req_rd) begin

        s_ctrlport_resp_ack    <= 1'b1;
        s_ctrlport_resp_status <= CTRL_STS_OKAY;
        s_ctrlport_resp_data   <= {CTRLPORT_DATA_W {1'b0}};

        case (s_ctrlport_req_addr)
          BASE_ADDRESS + IPASS_POWER_REG: begin
            s_ctrlport_resp_data[IPASS_DISABLE_POWER_BIT] <= ipass_power_disable;
            s_ctrlport_resp_data[IPASS_POWER_FAULT0]      <= ipass_power_sticky[0];
            s_ctrlport_resp_data[IPASS_POWER_FAULT1]      <= ipass_power_sticky[1];
          end

          BASE_ADDRESS + OSC_POWER_REG: begin
            s_ctrlport_resp_data[OSC_100]    <= osc_100_en;
            s_ctrlport_resp_data[OSC_122_88] <= osc_122_88_en;
          end


          default: begin
            s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'bx}};
            if (address_in_range) begin
              s_ctrlport_resp_status <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack <= 1'b0;
            end
          end
        endcase


      end else begin
        s_ctrlport_resp_ack <= 1'b0;
      end
    end
  end






  wire [1:0] ipass_power_fault_lcl_n;
  synchronizer #(
    .WIDTH            (2),
    .STAGES           (2),
    .INITIAL_VAL      (1'b0),
    .FALSE_PATH_TO_IN (1)
  ) power_fault_sync (
    .clk (ctrlport_clk),
    .rst (ctrlport_rst),
    .in  (ipass_power_fault_n),
    .out (ipass_power_fault_lcl_n)
  );

  always @(posedge ctrlport_clk) begin
    if (ctrlport_rst) begin
      ipass_power_sticky <= 2'b00;
    end else begin

      ipass_power_sticky <= (ipass_power_sticky & ~ipass_clear_sticky) | ~ipass_power_fault_lcl_n;
    end
  end

endmodule
module ps_power_regs #(
  parameter BASE_ADDRESS  = 0,
  parameter NUM_ADDRESSES = 32
) (
  input wire ctrlport_clk,
  input wire ctrlport_rst,


  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [31:0] s_ctrlport_req_data,

  output reg         s_ctrlport_resp_ack,
  output reg  [ 1:0] s_ctrlport_resp_status,
  output reg  [31:0] s_ctrlport_resp_data,


  output reg         ipass_power_disable = 1'b0,
  input  wire [ 1:0] ipass_power_fault_n,


  output reg         osc_100_en,
  output reg         osc_122_88_en
);


  `include "regmap/ps_power_regmap_utils.vh"
  `include "../../../lib/rfnoc/core/ctrlport.vh"





  wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) &&
                          (s_ctrlport_req_addr < BASE_ADDRESS + NUM_ADDRESSES);





  reg [1:0] ipass_power_sticky = 2'b00;
  reg [1:0] ipass_clear_sticky = 2'b00;





  always @(posedge ctrlport_clk) begin

    if (ctrlport_rst) begin
      ipass_power_disable    <= 1'b0;
      s_ctrlport_resp_ack    <= 1'b0;
      s_ctrlport_resp_status <= CTRL_STS_OKAY;
      s_ctrlport_resp_data   <= {CTRLPORT_ADDR_W {1'bx}};

      osc_100_en    <= 1'b0;
      osc_122_88_en <= 1'b0;

    end else begin

      ipass_clear_sticky <= 2'b00;


      if (s_ctrlport_req_wr) begin

        s_ctrlport_resp_ack    <= 1'b1;
        s_ctrlport_resp_status <= CTRL_STS_OKAY;
        s_ctrlport_resp_data   <= {CTRLPORT_ADDR_W {1'bx}};

        case (s_ctrlport_req_addr)
          BASE_ADDRESS + IPASS_POWER_REG: begin
            ipass_power_disable   <= s_ctrlport_req_data[IPASS_DISABLE_POWER_BIT];
            ipass_clear_sticky[0] <= s_ctrlport_req_data[IPASS_CLEAR_POWER_FAULT0];
            ipass_clear_sticky[1] <= s_ctrlport_req_data[IPASS_CLEAR_POWER_FAULT1];
          end

          BASE_ADDRESS + OSC_POWER_REG: begin
            osc_100_en    <= s_ctrlport_req_data[OSC_100];
            osc_122_88_en <= s_ctrlport_req_data[OSC_122_88];
          end


          default: begin
            if (address_in_range) begin
              s_ctrlport_resp_status <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack <= 1'b0;
            end
          end
        endcase


      end else if (s_ctrlport_req_rd) begin

        s_ctrlport_resp_ack    <= 1'b1;
        s_ctrlport_resp_status <= CTRL_STS_OKAY;
        s_ctrlport_resp_data   <= {CTRLPORT_DATA_W {1'b0}};

        case (s_ctrlport_req_addr)
          BASE_ADDRESS + IPASS_POWER_REG: begin
            s_ctrlport_resp_data[IPASS_DISABLE_POWER_BIT] <= ipass_power_disable;
            s_ctrlport_resp_data[IPASS_POWER_FAULT0]      <= ipass_power_sticky[0];
            s_ctrlport_resp_data[IPASS_POWER_FAULT1]      <= ipass_power_sticky[1];
          end

          BASE_ADDRESS + OSC_POWER_REG: begin
            s_ctrlport_resp_data[OSC_100]    <= osc_100_en;
            s_ctrlport_resp_data[OSC_122_88] <= osc_122_88_en;
          end


          default: begin
            s_ctrlport_resp_data <= {CTRLPORT_DATA_W {1'bx}};
            if (address_in_range) begin
              s_ctrlport_resp_status <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack <= 1'b0;
            end
          end
        endcase


      end else begin
        s_ctrlport_resp_ack <= 1'b0;
      end
    end
  end






  wire [1:0] ipass_power_fault_lcl_n;
  synchronizer #(
    .WIDTH            (2),
    .STAGES           (2),
    .INITIAL_VAL      (1'b0),
    .FALSE_PATH_TO_IN (1)
  ) power_fault_sync (
    .clk (ctrlport_clk),
    .rst (ctrlport_rst),
    .in  (ipass_power_fault_n),
    .out (ipass_power_fault_lcl_n)
  );

  always @(posedge ctrlport_clk) begin
    if (ctrlport_rst) begin
      ipass_power_sticky <= 2'b00;
    end else begin

      ipass_power_sticky <= (ipass_power_sticky & ~ipass_clear_sticky) | ~ipass_power_fault_lcl_n;
    end
  end

endmodule