data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:29: Cannot find include file: sys.h\n`include  "sys.h" // system level definition file which contains the  \n          ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:31: Cannot find include file: iop.h\n`include  "iop.h" \n          ^~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:33: Cannot find include file: lsu.h\n`include  "lsu.h" \n          ^~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:88: Define or directive not defined: \'`DFQ_WIDTH\'\ninput [`DFQ_WIDTH:0]        dfq_rdata ;              \n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:88: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\ninput [`DFQ_WIDTH:0]        dfq_rdata ;              \n                 ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:89: Define or directive not defined: \'`CPX_WIDTH\'\ninput [`CPX_WIDTH-1:0]      cpx_spc_data_cx;         \n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:147: Define or directive not defined: \'`DFQ_WIDTH\'\noutput  [`DFQ_WIDTH:0]    dfq_wdata ;\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:147: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\noutput  [`DFQ_WIDTH:0]    dfq_wdata ;\n                   ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:152: Define or directive not defined: \'`CPX_VLD\'\noutput  [`CPX_VLD-1:0]  lsu_ifill_pkt ;\n         ^~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:207: Define or directive not defined: \'`STB_DFQ_WIDTH\'\nwire  [`STB_DFQ_WIDTH-1:0]  stb_dfq_data_in ;\n       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:212: Define or directive not defined: \'`DFQ_WIDTH\'\nwire  [`DFQ_WIDTH:0]  dfq_byp_mx_data ;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:212: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire  [`DFQ_WIDTH:0]  dfq_byp_mx_data ;\n                 ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:213: Define or directive not defined: \'`DFQ_WIDTH\'\nwire  [`DFQ_WIDTH-1:0]    dfq_byp_ff_data ;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:228: Define or directive not defined: \'`STB_DFQ_VLD\'\nwire  [`STB_DFQ_VLD:0]   stb_dcfill_data_mx;\n       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:228: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire  [`STB_DFQ_VLD:0]   stb_dcfill_data_mx;\n                   ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:258: Define or directive not defined: \'`STB_DFQ_WIDTH\'\nassign  stb_dfq_data_in[`STB_DFQ_WIDTH-1:0] =\n                        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:274: Define or directive not defined: \'`STB_DFQ_VLD\'\nwire  [`STB_DFQ_VLD:0]  stb_dfq_pkt_data0,\n       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:274: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire  [`STB_DFQ_VLD:0]  stb_dfq_pkt_data0,\n                   ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:314: Define or directive not defined: \'`STB_DFQ_VLD\'\n           .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]),\n                                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:314: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n           .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]),\n                                              ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:315: Define or directive not defined: \'`STB_DFQ_VLD\'\n           .q    (stb_dfq_pkt_data0[`STB_DFQ_VLD:0]),\n                                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:338: Define or directive not defined: \'`STB_DFQ_VLD\'\n           .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]),\n                                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:338: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n           .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]),\n                                              ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:339: Define or directive not defined: \'`STB_DFQ_VLD\'\n           .q    (stb_dfq_pkt_data1[`STB_DFQ_VLD:0]),\n                                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:362: Define or directive not defined: \'`STB_DFQ_VLD\'\n           .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]),\n                                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:362: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n           .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]),\n                                              ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:363: Define or directive not defined: \'`STB_DFQ_VLD\'\n           .q    (stb_dfq_pkt_data2[`STB_DFQ_VLD:0]),\n                                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:386: Define or directive not defined: \'`STB_DFQ_VLD\'\n           .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]),\n                                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:386: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n           .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]),\n                                              ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:387: Define or directive not defined: \'`STB_DFQ_VLD\'\n           .q    (stb_dfq_pkt_data3[`STB_DFQ_VLD:0]),\n                                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:393: Define or directive not defined: \'`STB_DFQ_VLD\'\nmux4ds  #(`STB_DFQ_VLD+1) stb_data_mx (\n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:394: Define or directive not defined: \'`STB_DFQ_VLD\'\n  .in0  (stb_dfq_pkt_data0[`STB_DFQ_VLD:0]),\n                           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:394: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n  .in0  (stb_dfq_pkt_data0[`STB_DFQ_VLD:0]),\n                                       ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:395: Define or directive not defined: \'`STB_DFQ_VLD\'\n  .in1  (stb_dfq_pkt_data1[`STB_DFQ_VLD:0]),\n                           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:396: Define or directive not defined: \'`STB_DFQ_VLD\'\n  .in2  (stb_dfq_pkt_data2[`STB_DFQ_VLD:0]),\n                           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:397: Define or directive not defined: \'`STB_DFQ_VLD\'\n  .in3  (stb_dfq_pkt_data3[`STB_DFQ_VLD:0]),\n                           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:402: Define or directive not defined: \'`STB_DFQ_VLD\'\n  .dout (stb_dcfill_data_mx[`STB_DFQ_VLD:0])\n                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:454: Define or directive not defined: \'`CPX_NC\'\n  cpx_spc_data_cx[`CPX_NC],  \n                  ^~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:454: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  cpx_spc_data_cx[`CPX_NC],  \n                         ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:533: Define or directive not defined: \'`DFQ_WIDTH\'\nwire  [`DFQ_WIDTH:0]  dfq_st_data,dfq_cpx_raw_wdata;\n       ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:533: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire  [`DFQ_WIDTH:0]  dfq_st_data,dfq_cpx_raw_wdata;\n                 ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:536: Define or directive not defined: \'`DFQ_WIDTH\'\nassign  dfq_cpx_raw_wdata[`DFQ_WIDTH:0] = \n                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:536: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nassign  dfq_cpx_raw_wdata[`DFQ_WIDTH:0] = \n                                    ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:537: Define or directive not defined: \'`CPX_WIDTH\'\n  {lsu_cpx_spc_inv_vld,lsu_cpxpkt_type_dcd_cx[5:0],cpx_spc_data_cx[`CPX_WIDTH-1:0]};\n                                                                   ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:539: Define or directive not defined: \'`DFQ_WIDTH\'\nassign  dfq_st_data[`DFQ_WIDTH:0]  =  \n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:539: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nassign  dfq_st_data[`DFQ_WIDTH:0]  =  \n                              ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:541: Define or directive not defined: \'`CPX_WIDTH\'\n         cpx_spc_data_cx[`CPX_WIDTH-1:87],\n                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:544: Define or directive not defined: \'`STB_DFQ_VLD\'\n         stb_dcfill_data_mx[`STB_DFQ_VLD:0]};   \n                            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:546: Define or directive not defined: \'`DFQ_WIDTH\'\nmux2ds  #(`DFQ_WIDTH+1) dfq_st_data_mx (\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/lsu_qdp2.v:547: Define or directive not defined: \'`DFQ_WIDTH\'\n  .in0  (dfq_st_data[`DFQ_WIDTH:0]),\n                     ^~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module lsu_qdp2 (

   so, lsu_l2fill_data, dfq_wdata, dfq_tid, lsu_dcache_fill_data_e, 
   lsu_ifill_pkt, lsu_pcx_fwd_pkt, lsu_cpx_pkt_strm_ack, 
   lsu_cpx_pkt_vld, lsu_cpx_pkt_atm_st_cmplt, lsu_cpx_pkt_tid, 
   lsu_cpx_pkt_invwy, lsu_cpx_pkt_inv_pa, lsu_cpx_pkt_l2miss, 
   lsu_dfq_byp_invwy_vld, lsu_dfq_byp_type, lsu_dfq_byp_flush, 
   lsu_dfq_byp_tid, lsu_cpu_inv_data_b13to9, lsu_cpu_inv_data_b7to2, 
   lsu_cpu_inv_data_b0, lsu_iobrdge_wr_data, lsu_iobrdge_tap_rq_type, 
   lsu_cpx_pkt_perror_dinv, lsu_cpx_pkt_perror_iinv, 
   lsu_cpx_pkt_perror_set, lsu_cpx_pkt_ld_err, lsu_dfq_byp_binit_st, 
   lsu_cpx_pkt_binit_st, lsu_cpx_pkt_prefetch, lsu_cpx_pkt_prefetch2, 
   lsu_dfq_byp_cpx_inv, lsu_dfq_byp_stack_adr_b54, 
   lsu_dfq_byp_stack_wrway, lsu_dfq_byp_atm, dcache_iob_addr_e, 
   st_dcfill_addr, lsu_st_way_e, lsu_dcache_iob_way_e, 
   lsu_st_dcfill_size_e, lsu_cpx_pkt_ifill_type, lsu_cpx_pkt_atomic, 

   rst_tri_en, rclk, si, se, lsu_dfill_data_sel_hi, dfq_byp_ff_en, 
   dfq_rd_vld_d1, dfq_rdata, cpx_spc_data_cx, stb_rdata_ramd_buf, 
   stb_rdata_ramd_b74_buf, stb_rdata_ramc_buf, lsu_stb_pcx_rvld_d1, 
   lsu_diagnstc_wr_data_e, lsu_diagnstc_dc_prty_invrt_e, 
   mbist_write_data, cpx_fwd_pkt_en_cx, lsu_cpu_dcd_sel, 
   lsu_cpu_uhlf_sel, lsu_cpxpkt_type_dcd_cx, lsu_dc_iob_access_e, 
   lsu_dcfill_data_mx_sel_e, lsu_cpx_spc_inv_vld, lsu_cpx_thrdid, 
   lsu_cpx_stack_dcfill_vld, pcx_rq_for_stb_d1, lsu_dfq_ld_vld, 
   lsu_dfq_st_vld, lsu_dfq_ldst_vld
   ) ;  





   input rst_tri_en;
   
input                     rclk ;
input                     si;
input                     se;
output                    so;

input                       lsu_dfill_data_sel_hi ;

input                       dfq_byp_ff_en ;
input                       dfq_rd_vld_d1 ;
input [`DFQ_WIDTH:0]        dfq_rdata ;
input [`CPX_WIDTH-1:0]      cpx_spc_data_cx;

input [69:0]                stb_rdata_ramd_buf ;
input                       stb_rdata_ramd_b74_buf ;
input [14:9]                stb_rdata_ramc_buf ;
input                       lsu_stb_pcx_rvld_d1 ;






input  [63:0]               lsu_diagnstc_wr_data_e ;
input  [7:0]                lsu_diagnstc_dc_prty_invrt_e ;










input   [7:0]             mbist_write_data ;
   
input                     cpx_fwd_pkt_en_cx ;
input   [7:0]             lsu_cpu_dcd_sel ;
input                     lsu_cpu_uhlf_sel ;
input   [5:0]             lsu_cpxpkt_type_dcd_cx ;





input			  lsu_dc_iob_access_e ;




input                     lsu_dcfill_data_mx_sel_e;

input                     lsu_cpx_spc_inv_vld;
input   [3:0]             lsu_cpx_thrdid;
input                     lsu_cpx_stack_dcfill_vld ;
input   [3:0]             pcx_rq_for_stb_d1;

input                     lsu_dfq_ld_vld ;
input                     lsu_dfq_st_vld ;
input                     lsu_dfq_ldst_vld ;






output  [63:0]            lsu_l2fill_data ;

output  [`DFQ_WIDTH:0]    dfq_wdata ;
output  [1:0]             dfq_tid ;

output  [143:0]           lsu_dcache_fill_data_e ;

output  [`CPX_VLD-1:0]  lsu_ifill_pkt ;
output  [107:0]           lsu_pcx_fwd_pkt ;
output               	  lsu_cpx_pkt_strm_ack ;
output                    lsu_cpx_pkt_vld ;
output                    lsu_cpx_pkt_atm_st_cmplt ;
output  [1:0]             lsu_cpx_pkt_tid ;
output  [1:0]             lsu_cpx_pkt_invwy ;
output  [4:0]             lsu_cpx_pkt_inv_pa ;
output			  lsu_cpx_pkt_l2miss ;
output                    lsu_dfq_byp_invwy_vld ;
output  [5:0]             lsu_dfq_byp_type ;
output                    lsu_dfq_byp_flush ;

output  [1:0]             lsu_dfq_byp_tid ;

output  [13:9]            lsu_cpu_inv_data_b13to9 ;
output  [7:2]             lsu_cpu_inv_data_b7to2 ;
output                    lsu_cpu_inv_data_b0 ;


output  [43:0]            lsu_iobrdge_wr_data ;
output  [8:0]             lsu_iobrdge_tap_rq_type ;


output                    lsu_cpx_pkt_perror_dinv ;
output                    lsu_cpx_pkt_perror_iinv ;
output  [1:0]             lsu_cpx_pkt_perror_set ;
output  [1:0]             lsu_cpx_pkt_ld_err ;
output			  lsu_dfq_byp_binit_st ;
output			  lsu_cpx_pkt_binit_st ;
output			  lsu_cpx_pkt_prefetch;
output			  lsu_cpx_pkt_prefetch2;

output                    lsu_dfq_byp_cpx_inv;

output  [1:0]             lsu_dfq_byp_stack_adr_b54;
output  [1:0]             lsu_dfq_byp_stack_wrway;
output                    lsu_dfq_byp_atm;


   output [7:0]           dcache_iob_addr_e;
   output [10:0]          st_dcfill_addr;

   output [1:0]           lsu_st_way_e;
   output [1:0]           lsu_dcache_iob_way_e;

   output [1:0]           lsu_st_dcfill_size_e;
   



wire  [13:0]      cpx_cpulo_inv_data ;
wire  [13:0]      cpx_cpuhi_inv_data ;


wire  [`STB_DFQ_WIDTH-1:0]  stb_dfq_data_in ;




wire  [`DFQ_WIDTH:0]  dfq_byp_mx_data ;
wire  [`DFQ_WIDTH-1:0]    dfq_byp_ff_data ;

wire  [127:0]   st_dcfill_data ;
wire  [63:0]      dcache_wr_data ;
wire  [127:0]   ldinv_dcfill_data ;


wire  [127:0] lsu_dcfill_data ;
wire  [15:0]      dcache_wr_parity_mod ;

wire  [107:0]     cpx_fwd_pkt_din ;



wire  [1:0]  cpx_st_dcfill_wrway;
wire  [`STB_DFQ_VLD:0]   stb_dcfill_data_mx;
wire           clk;
wire  [13:0]            lsu_cpu_inv_data ;

assign  clk = rclk;

























assign  stb_dfq_data_in[`STB_DFQ_WIDTH-1:0] =
  {lsu_stb_pcx_rvld_d1,
  stb_rdata_ramd_b74_buf,
  2'b00,

  3'b000,
  stb_rdata_ramd_buf[69:68],
  {stb_rdata_ramc_buf[14:9],stb_rdata_ramd_buf[67:64]},
  stb_rdata_ramd_buf[63:0]};






wire  [3:0]   clk_stb_data;
wire  [`STB_DFQ_VLD:0]  stb_dfq_pkt_data0,
                        stb_dfq_pkt_data1,
                        stb_dfq_pkt_data2,
                        stb_dfq_pkt_data3;



















`ifdef FPGA_SYN_CLK_EN
`else
clken_buf stb_dfq_byp0_clken(                
          .clk(clk_stb_data[0]),             
          .rclk(clk),                         
          .enb_l(~pcx_rq_for_stb_d1[0]),           
          .tmb_l(~se));                       
`endif
                                                 
`ifdef FPGA_SYN_CLK_DFF
dffe_s  #(83) stb_dfq_byp0_ff (                       
           .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]),
           .q    (stb_dfq_pkt_data0[`STB_DFQ_VLD:0]),
           .en (~(~pcx_rq_for_stb_d1[0])), .clk(clk), 
           .se   (1'b0),       .si (),          .so ());                                
`else
dff_s  #(83) stb_dfq_byp0_ff (                       
           .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]),
           .q    (stb_dfq_pkt_data0[`STB_DFQ_VLD:0]),
           .clk  (clk_stb_data[0]), 
           .se   (1'b0),       .si (),          .so ());                                
`endif


`ifdef FPGA_SYN_CLK_EN
`else
clken_buf stb_dfq_byp1_clken(                
          .clk(clk_stb_data[1]),             
          .rclk(clk),                         
          .enb_l(~pcx_rq_for_stb_d1[1]),           
          .tmb_l(~se));                       
`endif
                                                 
`ifdef FPGA_SYN_CLK_DFF
dffe_s  #(83) stb_dfq_byp1_ff (                       
           .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]),
           .q    (stb_dfq_pkt_data1[`STB_DFQ_VLD:0]),
           .en (~(~pcx_rq_for_stb_d1[1])), .clk(clk), 
           .se   (1'b0),       .si (),          .so ());                                
`else
dff_s  #(83) stb_dfq_byp1_ff (                       
           .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]),
           .q    (stb_dfq_pkt_data1[`STB_DFQ_VLD:0]),
           .clk  (clk_stb_data[1]), 
           .se   (1'b0),       .si (),          .so ());                                
`endif


`ifdef FPGA_SYN_CLK_EN
`else
clken_buf stb_dfq_byp2_clken(                
          .clk(clk_stb_data[2]),             
          .rclk(clk),                         
          .enb_l(~pcx_rq_for_stb_d1[2]),           
          .tmb_l(~se));                       
`endif
                                                 
`ifdef FPGA_SYN_CLK_DFF
dffe_s  #(83) stb_dfq_byp2_ff (                       
           .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]),
           .q    (stb_dfq_pkt_data2[`STB_DFQ_VLD:0]),
           .en (~(~pcx_rq_for_stb_d1[2])), .clk(clk), 
           .se   (1'b0),       .si (),          .so ());                                
`else
dff_s  #(83) stb_dfq_byp2_ff (                       
           .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]),
           .q    (stb_dfq_pkt_data2[`STB_DFQ_VLD:0]),
           .clk  (clk_stb_data[2]), 
           .se   (1'b0),       .si (),          .so ());                                
`endif


`ifdef FPGA_SYN_CLK_EN
`else
clken_buf stb_dfq_byp3_clken(                
          .clk(clk_stb_data[3]),             
          .rclk(clk),                         
          .enb_l(~pcx_rq_for_stb_d1[3]),           
          .tmb_l(~se));                       
`endif
                                                 
`ifdef FPGA_SYN_CLK_DFF
dffe_s  #(83) stb_dfq_byp3_ff (                       
           .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]),
           .q    (stb_dfq_pkt_data3[`STB_DFQ_VLD:0]),
           .en (~(~pcx_rq_for_stb_d1[3])), .clk(clk), 
           .se   (1'b0),       .si (),          .so ());                                
`else
dff_s  #(83) stb_dfq_byp3_ff (                       
           .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]),
           .q    (stb_dfq_pkt_data3[`STB_DFQ_VLD:0]),
           .clk  (clk_stb_data[3]), 
           .se   (1'b0),       .si (),          .so ());                                
`endif


mux4ds  #(`STB_DFQ_VLD+1) stb_data_mx (
  .in0  (stb_dfq_pkt_data0[`STB_DFQ_VLD:0]),
  .in1  (stb_dfq_pkt_data1[`STB_DFQ_VLD:0]),
  .in2  (stb_dfq_pkt_data2[`STB_DFQ_VLD:0]),
  .in3  (stb_dfq_pkt_data3[`STB_DFQ_VLD:0]),
  .sel0 (lsu_cpx_thrdid[0]),  
  .sel1 (lsu_cpx_thrdid[1]),
  .sel2 (lsu_cpx_thrdid[2]),
  .sel3 (lsu_cpx_thrdid[3]),
  .dout (stb_dcfill_data_mx[`STB_DFQ_VLD:0])
);
















































assign  cpx_fwd_pkt_din[107:0] = 
  {
  cpx_spc_data_cx[`CPX_NC],
  cpx_spc_data_cx[133:131],
  cpx_spc_data_cx[103:0]
  } ;










`ifdef FPGA_SYN_CLK_EN
`else
clken_buf fwdpkt_clken(                             
          .clk(clk_cpx_fwd_pkt_en_cx),               
          .rclk(clk),                                 
          .enb_l(~cpx_fwd_pkt_en_cx),                  
          .tmb_l(~se));                               
`endif
                                                         
`ifdef FPGA_SYN_CLK_DFF
dffe_s  #(108) fwdpkt_ff  (                                  
            .din  (cpx_fwd_pkt_din[107:0]),                
            .q    (lsu_pcx_fwd_pkt[107:0]),                 
            .en (~(~cpx_fwd_pkt_en_cx)), .clk(clk),                   
            .se     (1'b0),       .si (),          .so ());   
`else
dff_s  #(108) fwdpkt_ff  (                                  
            .din  (cpx_fwd_pkt_din[107:0]),                
            .q    (lsu_pcx_fwd_pkt[107:0]),                 
            .clk  (clk_cpx_fwd_pkt_en_cx),                   
            .se     (1'b0),       .si (),          .so ());   
`endif











wire [7:0] dcache_iob_addr_e ;
assign	dcache_iob_addr_e[7:0] = lsu_pcx_fwd_pkt[74:67] ;







assign lsu_dcache_iob_way_e [1:0] =  {lsu_pcx_fwd_pkt[76],  lsu_pcx_fwd_pkt[75]};
  
wire [63:0] dcache_iob_data_e ; 
assign	dcache_iob_data_e[63:0] = lsu_pcx_fwd_pkt[63:0] ;

assign  lsu_iobrdge_wr_data[43:0] = lsu_pcx_fwd_pkt[43:0] ;
assign  lsu_iobrdge_tap_rq_type[8:0] = {lsu_pcx_fwd_pkt[107],lsu_pcx_fwd_pkt[103:96]} ;
















wire  [`DFQ_WIDTH:0]  dfq_st_data,dfq_cpx_raw_wdata;
wire  [1:0]           cpx_st_ack_addr_b54;

assign  dfq_cpx_raw_wdata[`DFQ_WIDTH:0] = 
  {lsu_cpx_spc_inv_vld,lsu_cpxpkt_type_dcd_cx[5:0],cpx_spc_data_cx[`CPX_WIDTH-1:0]};

assign  dfq_st_data[`DFQ_WIDTH:0]  =  
        {lsu_cpx_spc_inv_vld,lsu_cpxpkt_type_dcd_cx[5:0],
         cpx_spc_data_cx[`CPX_WIDTH-1:87],
         cpx_st_ack_addr_b54[1:0],
         cpx_st_dcfill_wrway[1:0],
         stb_dcfill_data_mx[`STB_DFQ_VLD:0]};

mux2ds  #(`DFQ_WIDTH+1) dfq_st_data_mx (
  .in0  (dfq_st_data[`DFQ_WIDTH:0]),
  .in1  (dfq_cpx_raw_wdata[`DFQ_WIDTH:0]),
  .sel0 (lsu_cpx_stack_dcfill_vld),  
  .sel1 (~lsu_cpx_stack_dcfill_vld),
  .dout (dfq_wdata[`DFQ_WIDTH:0])
);




mux2ds  #(`DFQ_WIDTH+1) dfq_byp_mx (
  .in0  (dfq_rdata[`DFQ_WIDTH:0]),
  .in1  (dfq_cpx_raw_wdata[`DFQ_WIDTH:0]),
  .sel0 (dfq_rd_vld_d1),  
  .sel1 (~dfq_rd_vld_d1),
  .dout (dfq_byp_mx_data[`DFQ_WIDTH:0])
);

assign  lsu_dfq_byp_cpx_inv     =   dfq_byp_mx_data[`DFQ_WIDTH];
assign  lsu_dfq_byp_tid[1:0]    =   dfq_byp_mx_data[`CPX_TH_HI:`CPX_TH_LO] ;

assign  lsu_dfq_byp_flush = 	dfq_byp_mx_data[`CPX_NC] ;
assign  lsu_dfq_byp_invwy_vld = dfq_byp_mx_data[`CPX_WYVLD] ;


assign  lsu_dfq_byp_type[5:3]   =   dfq_byp_mx_data[`DFQ_WIDTH-1:`DFQ_WIDTH-3] ;
assign  lsu_dfq_byp_type[2]   =   dfq_byp_mx_data[`DFQ_WIDTH-4] & dfq_rd_vld_d1;
assign  lsu_dfq_byp_type[1:0]   =   dfq_byp_mx_data[`DFQ_WIDTH-5:`DFQ_WIDTH-6] ;


assign  lsu_dfq_byp_binit_st =   dfq_byp_mx_data[125] ;



assign  lsu_dfq_byp_stack_adr_b54[1:0] =   dfq_byp_mx_data[86:85] ;
assign  lsu_dfq_byp_stack_wrway[1:0] =   dfq_byp_mx_data[84:83] ;

assign  lsu_ifill_pkt[`CPX_VLD-1:0] = dfq_byp_mx_data[`CPX_VLD-1:0] ;


assign  lsu_dfq_byp_atm  = dfq_byp_mx_data[129] ;















`ifdef FPGA_SYN_CLK_EN
`else
clken_buf dfq_byp_ff_en_clken(                     
          .clk(clk_dfq_byp_ff_en),                  
          .rclk(clk),                                
          .enb_l(~dfq_byp_ff_en),                     
          .tmb_l(~se));                              
`endif
                                                        
`ifdef FPGA_SYN_CLK_DFF
dffe_s  #(`DFQ_WIDTH) dfq_data_stg (                        
                  .din  (dfq_byp_mx_data[`DFQ_WIDTH-1:0]),
                  .q    (dfq_byp_ff_data[`DFQ_WIDTH-1:0]),
                  .en (~(~dfq_byp_ff_en)), .clk(clk),
                  .se   (1'b0),     .si (),          .so ());
`else
dff_s  #(`DFQ_WIDTH) dfq_data_stg (                        
                  .din  (dfq_byp_mx_data[`DFQ_WIDTH-1:0]),
                  .q    (dfq_byp_ff_data[`DFQ_WIDTH-1:0]),
                  .clk  (clk_dfq_byp_ff_en),
                  .se   (1'b0),     .si (),          .so ());
`endif





assign  dfq_tid[1:0] = dfq_byp_ff_data[`CPX_TH_HI:`CPX_TH_LO] ;

output    lsu_cpx_pkt_ifill_type;
output    lsu_cpx_pkt_atomic ;



assign  lsu_cpx_pkt_ifill_type    = dfq_byp_ff_data[`DFQ_WIDTH-2];
assign  lsu_cpx_pkt_tid[1:0]      = dfq_byp_ff_data[`CPX_TH_HI:`CPX_TH_LO] ;
assign  lsu_cpx_pkt_vld     = dfq_byp_ff_data[`CPX_VLD] ;
assign  lsu_cpx_pkt_atm_st_cmplt  = dfq_byp_ff_data[129] ;
assign  lsu_cpx_pkt_invwy[1:0]    = dfq_byp_ff_data[`CPX_WY_HI:`CPX_WY_LO] ;

assign  lsu_cpx_pkt_strm_ack   = dfq_byp_ff_data[`DFQ_WIDTH-5];

assign  lsu_cpx_pkt_inv_pa[4:0]   = dfq_byp_ff_data[`CPX_INV_PA_HI:`CPX_INV_PA_LO];
assign  lsu_cpx_pkt_atomic    = dfq_byp_ff_data[129]  |
            dfq_byp_ff_data[131]  ;

assign  lsu_cpx_pkt_binit_st   = dfq_byp_ff_data[125] ;
assign  lsu_cpx_pkt_prefetch = dfq_byp_ff_data[128] ;
assign  lsu_cpx_pkt_prefetch2 = dfq_byp_ff_data[128] ;


assign  lsu_cpx_pkt_perror_iinv    = dfq_byp_ff_data[`CPX_PERR_DINV+1] ;
assign  lsu_cpx_pkt_perror_dinv    = dfq_byp_ff_data[`CPX_PERR_DINV] ;
assign  lsu_cpx_pkt_perror_set[1:0] = 
	dfq_byp_ff_data[`CPX_PERR_DINV_AD5:`CPX_PERR_DINV_AD4] ;

assign  lsu_cpx_pkt_ld_err[1:0] = dfq_byp_ff_data[138:137] ;  
assign  lsu_cpx_pkt_l2miss = dfq_byp_ff_data[139] ;  







mux4ds  #(14) invfld_lo_sel (
        .in0    ({dfq_byp_mx_data[`CPX_A11_C0_HI:`CPX_A11_C0_LO],
                  dfq_byp_mx_data[`CPX_A10_C0_HI:`CPX_A10_C0_LO],
                  dfq_byp_mx_data[`CPX_A01_C0_HI:`CPX_A01_C0_LO],
                  dfq_byp_mx_data[`CPX_A00_C0_HI:`CPX_A00_C0_LO]}),
        .in1    ({dfq_byp_mx_data[`CPX_A11_C1_HI:`CPX_A11_C1_LO],
                  dfq_byp_mx_data[`CPX_A10_C1_HI:`CPX_A10_C1_LO],
                  dfq_byp_mx_data[`CPX_A01_C1_HI:`CPX_A01_C1_LO],
                  dfq_byp_mx_data[`CPX_A00_C1_HI:`CPX_A00_C1_LO]}),
        .in2    ({dfq_byp_mx_data[`CPX_A11_C2_HI:`CPX_A11_C2_LO],
                  dfq_byp_mx_data[`CPX_A10_C2_HI:`CPX_A10_C2_LO],
                  dfq_byp_mx_data[`CPX_A01_C2_HI:`CPX_A01_C2_LO],
                  dfq_byp_mx_data[`CPX_A00_C2_HI:`CPX_A00_C2_LO]}),
        .in3    ({dfq_byp_mx_data[`CPX_A11_C3_HI:`CPX_A11_C3_LO],
                  dfq_byp_mx_data[`CPX_A10_C3_HI:`CPX_A10_C3_LO],
                  dfq_byp_mx_data[`CPX_A01_C3_HI:`CPX_A01_C3_LO],
                  dfq_byp_mx_data[`CPX_A00_C3_HI:`CPX_A00_C3_LO]}),
        .sel0   (lsu_cpu_dcd_sel[0]),
        .sel1   (lsu_cpu_dcd_sel[1]),
        .sel2   (lsu_cpu_dcd_sel[2]),
        .sel3   (lsu_cpu_dcd_sel[3]),
        .dout   (cpx_cpulo_inv_data[13:0])
);

mux4ds  #(14) invfld_hi_sel (
        .in0    ({dfq_byp_mx_data[`CPX_A11_C4_HI:`CPX_A11_C4_LO],
                  dfq_byp_mx_data[`CPX_A10_C4_HI:`CPX_A10_C4_LO],
                  dfq_byp_mx_data[`CPX_A01_C4_HI:`CPX_A01_C4_LO],
                  dfq_byp_mx_data[`CPX_A00_C4_HI:`CPX_A00_C4_LO]}),
        .in1    ({dfq_byp_mx_data[`CPX_A11_C5_HI:`CPX_A11_C5_LO],
                  dfq_byp_mx_data[`CPX_A10_C5_HI:`CPX_A10_C5_LO],
                  dfq_byp_mx_data[`CPX_A01_C5_HI:`CPX_A01_C5_LO],
                  dfq_byp_mx_data[`CPX_A00_C5_HI:`CPX_A00_C5_LO]}),
        .in2    ({dfq_byp_mx_data[`CPX_A11_C6_HI:`CPX_A11_C6_LO],
                  dfq_byp_mx_data[`CPX_A10_C6_HI:`CPX_A10_C6_LO],
                  dfq_byp_mx_data[`CPX_A01_C6_HI:`CPX_A01_C6_LO],
                  dfq_byp_mx_data[`CPX_A00_C6_HI:`CPX_A00_C6_LO]}),
        .in3    ({dfq_byp_mx_data[`CPX_A11_C7_HI:`CPX_A11_C7_LO],
                  dfq_byp_mx_data[`CPX_A10_C7_HI:`CPX_A10_C7_LO],
                  dfq_byp_mx_data[`CPX_A01_C7_HI:`CPX_A01_C7_LO],
                  dfq_byp_mx_data[`CPX_A00_C7_HI:`CPX_A00_C7_LO]}),
        .sel0   (lsu_cpu_dcd_sel[4]),
        .sel1   (lsu_cpu_dcd_sel[5]),
        .sel2   (lsu_cpu_dcd_sel[6]),
        .sel3   (lsu_cpu_dcd_sel[7]),
        .dout   (cpx_cpuhi_inv_data[13:0])
);


mux2ds  #(14) invfld_sel (
        .in0    (cpx_cpulo_inv_data[13:0]),
        .in1    (cpx_cpuhi_inv_data[13:0]),
        .sel0   (~lsu_cpu_uhlf_sel),  
        .sel1   (lsu_cpu_uhlf_sel),
        .dout   (lsu_cpu_inv_data[13:0])
);

assign  lsu_cpu_inv_data_b13to9[13:9]  =  lsu_cpu_inv_data[13:9] ;
assign  lsu_cpu_inv_data_b7to2[7:2]  =  lsu_cpu_inv_data[7:2] ;
assign  lsu_cpu_inv_data_b0  =  lsu_cpu_inv_data[0] ;


wire  [13:0] cpx_cpulo_dcfill_wrway,
             cpx_cpuhi_dcfill_wrway,
             cpx_st_dcfill_wrway_sel;
             

mux4ds  #(14) st_dcfill_wrway_lo (
        .in0    ({cpx_spc_data_cx[`CPX_A11_C0_HI:`CPX_A11_C0_LO],
                  cpx_spc_data_cx[`CPX_A10_C0_HI:`CPX_A10_C0_LO],
                  cpx_spc_data_cx[`CPX_A01_C0_HI:`CPX_A01_C0_LO],
                  cpx_spc_data_cx[`CPX_A00_C0_HI:`CPX_A00_C0_LO]}),
        .in1    ({cpx_spc_data_cx[`CPX_A11_C1_HI:`CPX_A11_C1_LO],
                  cpx_spc_data_cx[`CPX_A10_C1_HI:`CPX_A10_C1_LO],
                  cpx_spc_data_cx[`CPX_A01_C1_HI:`CPX_A01_C1_LO],
                  cpx_spc_data_cx[`CPX_A00_C1_HI:`CPX_A00_C1_LO]}),
        .in2    ({cpx_spc_data_cx[`CPX_A11_C2_HI:`CPX_A11_C2_LO],
                  cpx_spc_data_cx[`CPX_A10_C2_HI:`CPX_A10_C2_LO],
                  cpx_spc_data_cx[`CPX_A01_C2_HI:`CPX_A01_C2_LO],
                  cpx_spc_data_cx[`CPX_A00_C2_HI:`CPX_A00_C2_LO]}),
        .in3    ({cpx_spc_data_cx[`CPX_A11_C3_HI:`CPX_A11_C3_LO],
                  cpx_spc_data_cx[`CPX_A10_C3_HI:`CPX_A10_C3_LO],
                  cpx_spc_data_cx[`CPX_A01_C3_HI:`CPX_A01_C3_LO],
                  cpx_spc_data_cx[`CPX_A00_C3_HI:`CPX_A00_C3_LO]}),
        .sel0   (lsu_cpu_dcd_sel[0]),
        .sel1   (lsu_cpu_dcd_sel[1]),
        .sel2   (lsu_cpu_dcd_sel[2]),
        .sel3   (lsu_cpu_dcd_sel[3]),
        .dout   (cpx_cpulo_dcfill_wrway[13:0])
);

mux4ds  #(14) st_dcfill_wrway_hi (
        .in0    ({cpx_spc_data_cx[`CPX_A11_C4_HI:`CPX_A11_C4_LO],
                  cpx_spc_data_cx[`CPX_A10_C4_HI:`CPX_A10_C4_LO],
                  cpx_spc_data_cx[`CPX_A01_C4_HI:`CPX_A01_C4_LO],
                  cpx_spc_data_cx[`CPX_A00_C4_HI:`CPX_A00_C4_LO]}),
        .in1    ({cpx_spc_data_cx[`CPX_A11_C5_HI:`CPX_A11_C5_LO],
                  cpx_spc_data_cx[`CPX_A10_C5_HI:`CPX_A10_C5_LO],
                  cpx_spc_data_cx[`CPX_A01_C5_HI:`CPX_A01_C5_LO],
                  cpx_spc_data_cx[`CPX_A00_C5_HI:`CPX_A00_C5_LO]}),
        .in2    ({cpx_spc_data_cx[`CPX_A11_C6_HI:`CPX_A11_C6_LO],
                  cpx_spc_data_cx[`CPX_A10_C6_HI:`CPX_A10_C6_LO],
                  cpx_spc_data_cx[`CPX_A01_C6_HI:`CPX_A01_C6_LO],
                  cpx_spc_data_cx[`CPX_A00_C6_HI:`CPX_A00_C6_LO]}),
        .in3    ({cpx_spc_data_cx[`CPX_A11_C7_HI:`CPX_A11_C7_LO],
                  cpx_spc_data_cx[`CPX_A10_C7_HI:`CPX_A10_C7_LO],
                  cpx_spc_data_cx[`CPX_A01_C7_HI:`CPX_A01_C7_LO],
                  cpx_spc_data_cx[`CPX_A00_C7_HI:`CPX_A00_C7_LO]}),
        .sel0   (lsu_cpu_dcd_sel[4]),
        .sel1   (lsu_cpu_dcd_sel[5]),
        .sel2   (lsu_cpu_dcd_sel[6]),
        .sel3   (lsu_cpu_dcd_sel[7]),
        .dout   (cpx_cpuhi_dcfill_wrway[13:0])
);



mux2ds  #(14) st_dcfill_wrway_sel (
        .in0    (cpx_cpulo_dcfill_wrway[13:0]),
        .in1    (cpx_cpuhi_dcfill_wrway[13:0]),
        .sel0   (~lsu_cpu_uhlf_sel),
        .sel1   (lsu_cpu_uhlf_sel),
        .dout   (cpx_st_dcfill_wrway_sel[13:0])
);





wire  [3:0]  st_dcfill_wrway_mxsel ;

assign st_dcfill_wrway_mxsel[0] =  (lsu_cpxpkt_type_dcd_cx[2] & cpx_st_dcfill_wrway_sel[0]) & ~rst_tri_en ;
assign st_dcfill_wrway_mxsel[1] =  (lsu_cpxpkt_type_dcd_cx[2] & cpx_st_dcfill_wrway_sel[4]) & ~rst_tri_en ;
assign st_dcfill_wrway_mxsel[2] =  (lsu_cpxpkt_type_dcd_cx[2] & cpx_st_dcfill_wrway_sel[7]) & ~rst_tri_en ;
assign st_dcfill_wrway_mxsel[3] =  ~|st_dcfill_wrway_mxsel[2:0] | rst_tri_en;

mux4ds  #(2) st_dcfill_wrway_sel_b54 (
        .in0    (cpx_st_dcfill_wrway_sel[3:2]),
        .in1    (cpx_st_dcfill_wrway_sel[6:5]),
        .in2    (cpx_st_dcfill_wrway_sel[10:9]),
        .in3    (cpx_st_dcfill_wrway_sel[13:12]),
        .sel0   (st_dcfill_wrway_mxsel[0]),
        .sel1   (st_dcfill_wrway_mxsel[1]),
        .sel2   (st_dcfill_wrway_mxsel[2]),
        .sel3   (st_dcfill_wrway_mxsel[3]),
        .dout   (cpx_st_dcfill_wrway[1:0])
);


assign  cpx_st_ack_addr_b54[0] = cpx_st_dcfill_wrway_sel[4] | cpx_st_dcfill_wrway_sel[11] ;
assign  cpx_st_ack_addr_b54[1] = cpx_st_dcfill_wrway_sel[7] | cpx_st_dcfill_wrway_sel[11] ;

















  



   wire [63:0] diagnstc_wr_data;
   
dff_s  #(64) diagnstc_wr_data_ff (
        .din    (lsu_diagnstc_wr_data_e[63:0]), 
        .q      (diagnstc_wr_data[63:0]),
        .clk    (clk),
        .se     (1'b0),     .si (),          .so ()
        ); 
   
mux2ds  #(64) dcwr_sel (

  .in0  ({dfq_byp_ff_data[`STB_DFQ_DA_HI:`STB_DFQ_DA_LO]}),
  .in1  ({diagnstc_wr_data[63:0]}),
  .sel0 ( lsu_dfq_st_vld),  
  .sel1 (~lsu_dfq_st_vld),


  .dout (dcache_wr_data[63:0])
);






assign st_dcfill_data[127:0] =
  {








   dcache_wr_data[63:0],
   dcache_wr_data[63:0]};

   assign st_dcfill_addr[10:0] =    
   {dfq_byp_ff_data[`CPX_INV_PA_HI:`CPX_INV_PA_LO],
    dfq_byp_ff_data[86:85],
    dfq_byp_ff_data[`STB_DFQ_AD_LO+3:`STB_DFQ_AD_LO]};
   




   assign lsu_st_way_e[1:0] = dfq_byp_ff_data[84:83];
   assign lsu_st_dcfill_size_e [1:0] = dfq_byp_ff_data[`STB_DFQ_SZ_HI:`STB_DFQ_SZ_LO];
       
assign ldinv_dcfill_data[127:0] =
  {







   dfq_byp_ff_data[`DFQ_DA_HI:`DFQ_DA_LO]};






mux2ds  #(128) dfq_pkt_src (
  .in0  (st_dcfill_data[127:0]),    
  .in1  (ldinv_dcfill_data[127:0]), 
  .sel0 (~lsu_dfq_ld_vld),  
  .sel1 (lsu_dfq_ld_vld),
  .dout (lsu_dcfill_data[127:0])
);


wire  [15:0]  dcache_wr_parity ;
lsu_dc_parity_gen parity_gen (
    .data_in  (lsu_dcfill_data[`DCFILL_DA_HI:`DCFILL_DA_LO]),
    .parity_out (dcache_wr_parity[15:0])
  );





wire	ld_unc_error ;
assign	ld_unc_error = (dfq_byp_ff_data[138] & dfq_byp_ff_data[`DFQ_WIDTH-1]);





   wire [15:0] parity_byte_flip;
   assign      parity_byte_flip[15:0] = dcache_wr_parity[15:0] ^ {16{ld_unc_error }};
   





wire  [15:0]  diagnstc_wr_parity;

assign diagnstc_wr_parity[15:0]  =  {lsu_diagnstc_dc_prty_invrt_e[7:0],lsu_diagnstc_dc_prty_invrt_e[7:0]} ^ dcache_wr_parity[15:0];

mux2ds  #(16) dcache_wr_parity_mod_mux (
              .in0(diagnstc_wr_parity[15:0]),

              .in1(parity_byte_flip[15:0]),
              .sel0(~lsu_dfq_ldst_vld),
              .sel1( lsu_dfq_ldst_vld),


              .dout(dcache_wr_parity_mod[15:0])
);










   












wire	[63:0] misc_fill_data_e ;





   wire [7:0] mbist_write_data_d1;

dff_s #(8) mbist_write_data_ff (
   .din (mbist_write_data[7:0]),
   .q   (mbist_write_data_d1[7:0]),
   .clk    (clk),
   .se     (1'b0),     .si (),          .so ()
); 
    

   wire      [3:0] misc_fill_parity_e;
assign    misc_fill_parity_e[3:0] = {4{~lsu_dc_iob_access_e}} & mbist_write_data_d1[3:0];

mux2ds  #(64) misc_fill_data_e_mux (
              .in0(dcache_iob_data_e[63:0]),
              .in1({8{mbist_write_data_d1[7:0]}}),
              .sel0(lsu_dc_iob_access_e),
              .sel1(~lsu_dc_iob_access_e),
              .dout(misc_fill_data_e[63:0])
);

mux2ds  #(144) lsu_dcache_fill_data_e_mux (
               .in0({misc_fill_data_e[63:0],misc_fill_data_e[63:0],{4{misc_fill_parity_e[3:0]}}}),
               .in1({lsu_dcfill_data[`DCFILL_DA_HI:`DCFILL_DA_LO],dcache_wr_parity_mod[15:0]}),
               .sel0(lsu_dcfill_data_mx_sel_e),
               .sel1(~lsu_dcfill_data_mx_sel_e),
               .dout(lsu_dcache_fill_data_e[143:0])
);








   


   






   
 


















































wire [63:0] l2fill_data_e;
 
mux2ds        #(64) half_sel (
      .in0    (lsu_dcfill_data[`DCFILL_DA_HI:`DCFILL_DA_LO+64]),
      .in1    (lsu_dcfill_data[`DCFILL_DA_LO+63:`DCFILL_DA_LO]),
      .sel0   (lsu_dfill_data_sel_hi),  .sel1 (~lsu_dfill_data_sel_hi),
      .dout   (l2fill_data_e[63:0])
);

dff_s #(64) stgm_l2fd (
        .din    (l2fill_data_e[63:0]),
        .q      (lsu_l2fill_data[63:0]),
        .clk    (clk),
        .se     (se),       .si (),          .so ()
        );

endmodule
module lsu_qdp2 (

   so, lsu_l2fill_data, dfq_wdata, dfq_tid, lsu_dcache_fill_data_e, 
   lsu_ifill_pkt, lsu_pcx_fwd_pkt, lsu_cpx_pkt_strm_ack, 
   lsu_cpx_pkt_vld, lsu_cpx_pkt_atm_st_cmplt, lsu_cpx_pkt_tid, 
   lsu_cpx_pkt_invwy, lsu_cpx_pkt_inv_pa, lsu_cpx_pkt_l2miss, 
   lsu_dfq_byp_invwy_vld, lsu_dfq_byp_type, lsu_dfq_byp_flush, 
   lsu_dfq_byp_tid, lsu_cpu_inv_data_b13to9, lsu_cpu_inv_data_b7to2, 
   lsu_cpu_inv_data_b0, lsu_iobrdge_wr_data, lsu_iobrdge_tap_rq_type, 
   lsu_cpx_pkt_perror_dinv, lsu_cpx_pkt_perror_iinv, 
   lsu_cpx_pkt_perror_set, lsu_cpx_pkt_ld_err, lsu_dfq_byp_binit_st, 
   lsu_cpx_pkt_binit_st, lsu_cpx_pkt_prefetch, lsu_cpx_pkt_prefetch2, 
   lsu_dfq_byp_cpx_inv, lsu_dfq_byp_stack_adr_b54, 
   lsu_dfq_byp_stack_wrway, lsu_dfq_byp_atm, dcache_iob_addr_e, 
   st_dcfill_addr, lsu_st_way_e, lsu_dcache_iob_way_e, 
   lsu_st_dcfill_size_e, lsu_cpx_pkt_ifill_type, lsu_cpx_pkt_atomic, 

   rst_tri_en, rclk, si, se, lsu_dfill_data_sel_hi, dfq_byp_ff_en, 
   dfq_rd_vld_d1, dfq_rdata, cpx_spc_data_cx, stb_rdata_ramd_buf, 
   stb_rdata_ramd_b74_buf, stb_rdata_ramc_buf, lsu_stb_pcx_rvld_d1, 
   lsu_diagnstc_wr_data_e, lsu_diagnstc_dc_prty_invrt_e, 
   mbist_write_data, cpx_fwd_pkt_en_cx, lsu_cpu_dcd_sel, 
   lsu_cpu_uhlf_sel, lsu_cpxpkt_type_dcd_cx, lsu_dc_iob_access_e, 
   lsu_dcfill_data_mx_sel_e, lsu_cpx_spc_inv_vld, lsu_cpx_thrdid, 
   lsu_cpx_stack_dcfill_vld, pcx_rq_for_stb_d1, lsu_dfq_ld_vld, 
   lsu_dfq_st_vld, lsu_dfq_ldst_vld
   ) ;
  





   input rst_tri_en;
   
input                     rclk ;
input                     si;
input                     se;
output                    so;

input                       lsu_dfill_data_sel_hi ;

input                       dfq_byp_ff_en ;
input                       dfq_rd_vld_d1 ;
input [`DFQ_WIDTH:0]        dfq_rdata ;
input [`CPX_WIDTH-1:0]      cpx_spc_data_cx;

input [69:0]                stb_rdata_ramd_buf ;
input                       stb_rdata_ramd_b74_buf ;
input [14:9]                stb_rdata_ramc_buf ;
input                       lsu_stb_pcx_rvld_d1 ;






input  [63:0]               lsu_diagnstc_wr_data_e ;
input  [7:0]                lsu_diagnstc_dc_prty_invrt_e ;










input   [7:0]             mbist_write_data ;
   
input                     cpx_fwd_pkt_en_cx ;
input   [7:0]             lsu_cpu_dcd_sel ;
input                     lsu_cpu_uhlf_sel ;
input   [5:0]             lsu_cpxpkt_type_dcd_cx ;





input			  lsu_dc_iob_access_e ;




input                     lsu_dcfill_data_mx_sel_e;

input                     lsu_cpx_spc_inv_vld;
input   [3:0]             lsu_cpx_thrdid;
input                     lsu_cpx_stack_dcfill_vld ;
input   [3:0]             pcx_rq_for_stb_d1;

input                     lsu_dfq_ld_vld ;
input                     lsu_dfq_st_vld ;
input                     lsu_dfq_ldst_vld ;






output  [63:0]            lsu_l2fill_data ;

output  [`DFQ_WIDTH:0]    dfq_wdata ;
output  [1:0]             dfq_tid ;

output  [143:0]           lsu_dcache_fill_data_e ;

output  [`CPX_VLD-1:0]  lsu_ifill_pkt ;
output  [107:0]           lsu_pcx_fwd_pkt ;
output               	  lsu_cpx_pkt_strm_ack ;
output                    lsu_cpx_pkt_vld ;
output                    lsu_cpx_pkt_atm_st_cmplt ;
output  [1:0]             lsu_cpx_pkt_tid ;
output  [1:0]             lsu_cpx_pkt_invwy ;
output  [4:0]             lsu_cpx_pkt_inv_pa ;
output			  lsu_cpx_pkt_l2miss ;
output                    lsu_dfq_byp_invwy_vld ;
output  [5:0]             lsu_dfq_byp_type ;
output                    lsu_dfq_byp_flush ;

output  [1:0]             lsu_dfq_byp_tid ;

output  [13:9]            lsu_cpu_inv_data_b13to9 ;
output  [7:2]             lsu_cpu_inv_data_b7to2 ;
output                    lsu_cpu_inv_data_b0 ;


output  [43:0]            lsu_iobrdge_wr_data ;
output  [8:0]             lsu_iobrdge_tap_rq_type ;


output                    lsu_cpx_pkt_perror_dinv ;
output                    lsu_cpx_pkt_perror_iinv ;
output  [1:0]             lsu_cpx_pkt_perror_set ;
output  [1:0]             lsu_cpx_pkt_ld_err ;
output			  lsu_dfq_byp_binit_st ;
output			  lsu_cpx_pkt_binit_st ;
output			  lsu_cpx_pkt_prefetch;
output			  lsu_cpx_pkt_prefetch2;

output                    lsu_dfq_byp_cpx_inv;

output  [1:0]             lsu_dfq_byp_stack_adr_b54;
output  [1:0]             lsu_dfq_byp_stack_wrway;
output                    lsu_dfq_byp_atm;


   output [7:0]           dcache_iob_addr_e;
   output [10:0]          st_dcfill_addr;

   output [1:0]           lsu_st_way_e;
   output [1:0]           lsu_dcache_iob_way_e;

   output [1:0]           lsu_st_dcfill_size_e;
   



wire  [13:0]      cpx_cpulo_inv_data ;
wire  [13:0]      cpx_cpuhi_inv_data ;


wire  [`STB_DFQ_WIDTH-1:0]  stb_dfq_data_in ;




wire  [`DFQ_WIDTH:0]  dfq_byp_mx_data ;
wire  [`DFQ_WIDTH-1:0]    dfq_byp_ff_data ;

wire  [127:0]   st_dcfill_data ;
wire  [63:0]      dcache_wr_data ;
wire  [127:0]   ldinv_dcfill_data ;


wire  [127:0] lsu_dcfill_data ;
wire  [15:0]      dcache_wr_parity_mod ;

wire  [107:0]     cpx_fwd_pkt_din ;



wire  [1:0]  cpx_st_dcfill_wrway;
wire  [`STB_DFQ_VLD:0]   stb_dcfill_data_mx;
wire           clk;
wire  [13:0]            lsu_cpu_inv_data ;

assign  clk = rclk;

























assign  stb_dfq_data_in[`STB_DFQ_WIDTH-1:0] =
  {lsu_stb_pcx_rvld_d1,
  stb_rdata_ramd_b74_buf,
  2'b00,

  3'b000,
  stb_rdata_ramd_buf[69:68],
  {stb_rdata_ramc_buf[14:9],stb_rdata_ramd_buf[67:64]},
  stb_rdata_ramd_buf[63:0]};






wire  [3:0]   clk_stb_data;
wire  [`STB_DFQ_VLD:0]  stb_dfq_pkt_data0,
                        stb_dfq_pkt_data1,
                        stb_dfq_pkt_data2,
                        stb_dfq_pkt_data3;



















`ifdef FPGA_SYN_CLK_EN
`else
clken_buf stb_dfq_byp0_clken(                
          .clk(clk_stb_data[0]),             
          .rclk(clk),                         
          .enb_l(~pcx_rq_for_stb_d1[0]),           
          .tmb_l(~se));                       
`endif
                                                 
`ifdef FPGA_SYN_CLK_DFF
dffe_s  #(83) stb_dfq_byp0_ff (                       
           .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]),
           .q    (stb_dfq_pkt_data0[`STB_DFQ_VLD:0]),
           .en (~(~pcx_rq_for_stb_d1[0])), .clk(clk), 
           .se   (1'b0),       .si (),          .so ());                                
`else
dff_s  #(83) stb_dfq_byp0_ff (                       
           .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]),
           .q    (stb_dfq_pkt_data0[`STB_DFQ_VLD:0]),
           .clk  (clk_stb_data[0]), 
           .se   (1'b0),       .si (),          .so ());                                
`endif


`ifdef FPGA_SYN_CLK_EN
`else
clken_buf stb_dfq_byp1_clken(                
          .clk(clk_stb_data[1]),             
          .rclk(clk),                         
          .enb_l(~pcx_rq_for_stb_d1[1]),           
          .tmb_l(~se));                       
`endif
                                                 
`ifdef FPGA_SYN_CLK_DFF
dffe_s  #(83) stb_dfq_byp1_ff (                       
           .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]),
           .q    (stb_dfq_pkt_data1[`STB_DFQ_VLD:0]),
           .en (~(~pcx_rq_for_stb_d1[1])), .clk(clk), 
           .se   (1'b0),       .si (),          .so ());                                
`else
dff_s  #(83) stb_dfq_byp1_ff (                       
           .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]),
           .q    (stb_dfq_pkt_data1[`STB_DFQ_VLD:0]),
           .clk  (clk_stb_data[1]), 
           .se   (1'b0),       .si (),          .so ());                                
`endif


`ifdef FPGA_SYN_CLK_EN
`else
clken_buf stb_dfq_byp2_clken(                
          .clk(clk_stb_data[2]),             
          .rclk(clk),                         
          .enb_l(~pcx_rq_for_stb_d1[2]),           
          .tmb_l(~se));                       
`endif
                                                 
`ifdef FPGA_SYN_CLK_DFF
dffe_s  #(83) stb_dfq_byp2_ff (                       
           .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]),
           .q    (stb_dfq_pkt_data2[`STB_DFQ_VLD:0]),
           .en (~(~pcx_rq_for_stb_d1[2])), .clk(clk), 
           .se   (1'b0),       .si (),          .so ());                                
`else
dff_s  #(83) stb_dfq_byp2_ff (                       
           .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]),
           .q    (stb_dfq_pkt_data2[`STB_DFQ_VLD:0]),
           .clk  (clk_stb_data[2]), 
           .se   (1'b0),       .si (),          .so ());                                
`endif


`ifdef FPGA_SYN_CLK_EN
`else
clken_buf stb_dfq_byp3_clken(                
          .clk(clk_stb_data[3]),             
          .rclk(clk),                         
          .enb_l(~pcx_rq_for_stb_d1[3]),           
          .tmb_l(~se));                       
`endif
                                                 
`ifdef FPGA_SYN_CLK_DFF
dffe_s  #(83) stb_dfq_byp3_ff (                       
           .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]),
           .q    (stb_dfq_pkt_data3[`STB_DFQ_VLD:0]),
           .en (~(~pcx_rq_for_stb_d1[3])), .clk(clk), 
           .se   (1'b0),       .si (),          .so ());                                
`else
dff_s  #(83) stb_dfq_byp3_ff (                       
           .din  (stb_dfq_data_in[`STB_DFQ_VLD:0]),
           .q    (stb_dfq_pkt_data3[`STB_DFQ_VLD:0]),
           .clk  (clk_stb_data[3]), 
           .se   (1'b0),       .si (),          .so ());                                
`endif


mux4ds  #(`STB_DFQ_VLD+1) stb_data_mx (
  .in0  (stb_dfq_pkt_data0[`STB_DFQ_VLD:0]),
  .in1  (stb_dfq_pkt_data1[`STB_DFQ_VLD:0]),
  .in2  (stb_dfq_pkt_data2[`STB_DFQ_VLD:0]),
  .in3  (stb_dfq_pkt_data3[`STB_DFQ_VLD:0]),
  .sel0 (lsu_cpx_thrdid[0]),  
  .sel1 (lsu_cpx_thrdid[1]),
  .sel2 (lsu_cpx_thrdid[2]),
  .sel3 (lsu_cpx_thrdid[3]),
  .dout (stb_dcfill_data_mx[`STB_DFQ_VLD:0])
);
















































assign  cpx_fwd_pkt_din[107:0] = 
  {
  cpx_spc_data_cx[`CPX_NC],
  cpx_spc_data_cx[133:131],
  cpx_spc_data_cx[103:0]
  } ;










`ifdef FPGA_SYN_CLK_EN
`else
clken_buf fwdpkt_clken(                             
          .clk(clk_cpx_fwd_pkt_en_cx),               
          .rclk(clk),                                 
          .enb_l(~cpx_fwd_pkt_en_cx),                  
          .tmb_l(~se));                               
`endif
                                                         
`ifdef FPGA_SYN_CLK_DFF
dffe_s  #(108) fwdpkt_ff  (                                  
            .din  (cpx_fwd_pkt_din[107:0]),                
            .q    (lsu_pcx_fwd_pkt[107:0]),                 
            .en (~(~cpx_fwd_pkt_en_cx)), .clk(clk),                   
            .se     (1'b0),       .si (),          .so ());   
`else
dff_s  #(108) fwdpkt_ff  (                                  
            .din  (cpx_fwd_pkt_din[107:0]),                
            .q    (lsu_pcx_fwd_pkt[107:0]),                 
            .clk  (clk_cpx_fwd_pkt_en_cx),                   
            .se     (1'b0),       .si (),          .so ());   
`endif











wire [7:0] dcache_iob_addr_e ;
assign	dcache_iob_addr_e[7:0] = lsu_pcx_fwd_pkt[74:67] ;







assign lsu_dcache_iob_way_e [1:0] =  {lsu_pcx_fwd_pkt[76],  lsu_pcx_fwd_pkt[75]};
  
wire [63:0] dcache_iob_data_e ; 
assign	dcache_iob_data_e[63:0] = lsu_pcx_fwd_pkt[63:0] ;

assign  lsu_iobrdge_wr_data[43:0] = lsu_pcx_fwd_pkt[43:0] ;
assign  lsu_iobrdge_tap_rq_type[8:0] = {lsu_pcx_fwd_pkt[107],lsu_pcx_fwd_pkt[103:96]} ;
















wire  [`DFQ_WIDTH:0]  dfq_st_data,dfq_cpx_raw_wdata;
wire  [1:0]           cpx_st_ack_addr_b54;

assign  dfq_cpx_raw_wdata[`DFQ_WIDTH:0] = 
  {lsu_cpx_spc_inv_vld,lsu_cpxpkt_type_dcd_cx[5:0],cpx_spc_data_cx[`CPX_WIDTH-1:0]};

assign  dfq_st_data[`DFQ_WIDTH:0]  =  
        {lsu_cpx_spc_inv_vld,lsu_cpxpkt_type_dcd_cx[5:0],
         cpx_spc_data_cx[`CPX_WIDTH-1:87],
         cpx_st_ack_addr_b54[1:0],
         cpx_st_dcfill_wrway[1:0],
         stb_dcfill_data_mx[`STB_DFQ_VLD:0]};

mux2ds  #(`DFQ_WIDTH+1) dfq_st_data_mx (
  .in0  (dfq_st_data[`DFQ_WIDTH:0]),
  .in1  (dfq_cpx_raw_wdata[`DFQ_WIDTH:0]),
  .sel0 (lsu_cpx_stack_dcfill_vld),  
  .sel1 (~lsu_cpx_stack_dcfill_vld),
  .dout (dfq_wdata[`DFQ_WIDTH:0])
);




mux2ds  #(`DFQ_WIDTH+1) dfq_byp_mx (
  .in0  (dfq_rdata[`DFQ_WIDTH:0]),
  .in1  (dfq_cpx_raw_wdata[`DFQ_WIDTH:0]),
  .sel0 (dfq_rd_vld_d1),  
  .sel1 (~dfq_rd_vld_d1),
  .dout (dfq_byp_mx_data[`DFQ_WIDTH:0])
);

assign  lsu_dfq_byp_cpx_inv     =   dfq_byp_mx_data[`DFQ_WIDTH];
assign  lsu_dfq_byp_tid[1:0]    =   dfq_byp_mx_data[`CPX_TH_HI:`CPX_TH_LO] ;

assign  lsu_dfq_byp_flush = 	dfq_byp_mx_data[`CPX_NC] ;
assign  lsu_dfq_byp_invwy_vld = dfq_byp_mx_data[`CPX_WYVLD] ;


assign  lsu_dfq_byp_type[5:3]   =   dfq_byp_mx_data[`DFQ_WIDTH-1:`DFQ_WIDTH-3] ;
assign  lsu_dfq_byp_type[2]   =   dfq_byp_mx_data[`DFQ_WIDTH-4] & dfq_rd_vld_d1;
assign  lsu_dfq_byp_type[1:0]   =   dfq_byp_mx_data[`DFQ_WIDTH-5:`DFQ_WIDTH-6] ;


assign  lsu_dfq_byp_binit_st =   dfq_byp_mx_data[125] ;



assign  lsu_dfq_byp_stack_adr_b54[1:0] =   dfq_byp_mx_data[86:85] ;
assign  lsu_dfq_byp_stack_wrway[1:0] =   dfq_byp_mx_data[84:83] ;

assign  lsu_ifill_pkt[`CPX_VLD-1:0] = dfq_byp_mx_data[`CPX_VLD-1:0] ;


assign  lsu_dfq_byp_atm  = dfq_byp_mx_data[129] ;















`ifdef FPGA_SYN_CLK_EN
`else
clken_buf dfq_byp_ff_en_clken(                     
          .clk(clk_dfq_byp_ff_en),                  
          .rclk(clk),                                
          .enb_l(~dfq_byp_ff_en),                     
          .tmb_l(~se));                              
`endif
                                                        
`ifdef FPGA_SYN_CLK_DFF
dffe_s  #(`DFQ_WIDTH) dfq_data_stg (                        
                  .din  (dfq_byp_mx_data[`DFQ_WIDTH-1:0]),
                  .q    (dfq_byp_ff_data[`DFQ_WIDTH-1:0]),
                  .en (~(~dfq_byp_ff_en)), .clk(clk),
                  .se   (1'b0),     .si (),          .so ());
`else
dff_s  #(`DFQ_WIDTH) dfq_data_stg (                        
                  .din  (dfq_byp_mx_data[`DFQ_WIDTH-1:0]),
                  .q    (dfq_byp_ff_data[`DFQ_WIDTH-1:0]),
                  .clk  (clk_dfq_byp_ff_en),
                  .se   (1'b0),     .si (),          .so ());
`endif





assign  dfq_tid[1:0] = dfq_byp_ff_data[`CPX_TH_HI:`CPX_TH_LO] ;

output    lsu_cpx_pkt_ifill_type;
output    lsu_cpx_pkt_atomic ;



assign  lsu_cpx_pkt_ifill_type    = dfq_byp_ff_data[`DFQ_WIDTH-2];
assign  lsu_cpx_pkt_tid[1:0]      = dfq_byp_ff_data[`CPX_TH_HI:`CPX_TH_LO] ;
assign  lsu_cpx_pkt_vld     = dfq_byp_ff_data[`CPX_VLD] ;
assign  lsu_cpx_pkt_atm_st_cmplt  = dfq_byp_ff_data[129] ;
assign  lsu_cpx_pkt_invwy[1:0]    = dfq_byp_ff_data[`CPX_WY_HI:`CPX_WY_LO] ;

assign  lsu_cpx_pkt_strm_ack   = dfq_byp_ff_data[`DFQ_WIDTH-5];

assign  lsu_cpx_pkt_inv_pa[4:0]   = dfq_byp_ff_data[`CPX_INV_PA_HI:`CPX_INV_PA_LO];
assign  lsu_cpx_pkt_atomic    = dfq_byp_ff_data[129]  |
            dfq_byp_ff_data[131]  ;

assign  lsu_cpx_pkt_binit_st   = dfq_byp_ff_data[125] ;
assign  lsu_cpx_pkt_prefetch = dfq_byp_ff_data[128] ;
assign  lsu_cpx_pkt_prefetch2 = dfq_byp_ff_data[128] ;


assign  lsu_cpx_pkt_perror_iinv    = dfq_byp_ff_data[`CPX_PERR_DINV+1] ;
assign  lsu_cpx_pkt_perror_dinv    = dfq_byp_ff_data[`CPX_PERR_DINV] ;
assign  lsu_cpx_pkt_perror_set[1:0] = 
	dfq_byp_ff_data[`CPX_PERR_DINV_AD5:`CPX_PERR_DINV_AD4] ;

assign  lsu_cpx_pkt_ld_err[1:0] = dfq_byp_ff_data[138:137] ;  
assign  lsu_cpx_pkt_l2miss = dfq_byp_ff_data[139] ;  







mux4ds  #(14) invfld_lo_sel (
        .in0    ({dfq_byp_mx_data[`CPX_A11_C0_HI:`CPX_A11_C0_LO],
                  dfq_byp_mx_data[`CPX_A10_C0_HI:`CPX_A10_C0_LO],
                  dfq_byp_mx_data[`CPX_A01_C0_HI:`CPX_A01_C0_LO],
                  dfq_byp_mx_data[`CPX_A00_C0_HI:`CPX_A00_C0_LO]}),
        .in1    ({dfq_byp_mx_data[`CPX_A11_C1_HI:`CPX_A11_C1_LO],
                  dfq_byp_mx_data[`CPX_A10_C1_HI:`CPX_A10_C1_LO],
                  dfq_byp_mx_data[`CPX_A01_C1_HI:`CPX_A01_C1_LO],
                  dfq_byp_mx_data[`CPX_A00_C1_HI:`CPX_A00_C1_LO]}),
        .in2    ({dfq_byp_mx_data[`CPX_A11_C2_HI:`CPX_A11_C2_LO],
                  dfq_byp_mx_data[`CPX_A10_C2_HI:`CPX_A10_C2_LO],
                  dfq_byp_mx_data[`CPX_A01_C2_HI:`CPX_A01_C2_LO],
                  dfq_byp_mx_data[`CPX_A00_C2_HI:`CPX_A00_C2_LO]}),
        .in3    ({dfq_byp_mx_data[`CPX_A11_C3_HI:`CPX_A11_C3_LO],
                  dfq_byp_mx_data[`CPX_A10_C3_HI:`CPX_A10_C3_LO],
                  dfq_byp_mx_data[`CPX_A01_C3_HI:`CPX_A01_C3_LO],
                  dfq_byp_mx_data[`CPX_A00_C3_HI:`CPX_A00_C3_LO]}),
        .sel0   (lsu_cpu_dcd_sel[0]),
        .sel1   (lsu_cpu_dcd_sel[1]),
        .sel2   (lsu_cpu_dcd_sel[2]),
        .sel3   (lsu_cpu_dcd_sel[3]),
        .dout   (cpx_cpulo_inv_data[13:0])
);

mux4ds  #(14) invfld_hi_sel (
        .in0    ({dfq_byp_mx_data[`CPX_A11_C4_HI:`CPX_A11_C4_LO],
                  dfq_byp_mx_data[`CPX_A10_C4_HI:`CPX_A10_C4_LO],
                  dfq_byp_mx_data[`CPX_A01_C4_HI:`CPX_A01_C4_LO],
                  dfq_byp_mx_data[`CPX_A00_C4_HI:`CPX_A00_C4_LO]}),
        .in1    ({dfq_byp_mx_data[`CPX_A11_C5_HI:`CPX_A11_C5_LO],
                  dfq_byp_mx_data[`CPX_A10_C5_HI:`CPX_A10_C5_LO],
                  dfq_byp_mx_data[`CPX_A01_C5_HI:`CPX_A01_C5_LO],
                  dfq_byp_mx_data[`CPX_A00_C5_HI:`CPX_A00_C5_LO]}),
        .in2    ({dfq_byp_mx_data[`CPX_A11_C6_HI:`CPX_A11_C6_LO],
                  dfq_byp_mx_data[`CPX_A10_C6_HI:`CPX_A10_C6_LO],
                  dfq_byp_mx_data[`CPX_A01_C6_HI:`CPX_A01_C6_LO],
                  dfq_byp_mx_data[`CPX_A00_C6_HI:`CPX_A00_C6_LO]}),
        .in3    ({dfq_byp_mx_data[`CPX_A11_C7_HI:`CPX_A11_C7_LO],
                  dfq_byp_mx_data[`CPX_A10_C7_HI:`CPX_A10_C7_LO],
                  dfq_byp_mx_data[`CPX_A01_C7_HI:`CPX_A01_C7_LO],
                  dfq_byp_mx_data[`CPX_A00_C7_HI:`CPX_A00_C7_LO]}),
        .sel0   (lsu_cpu_dcd_sel[4]),
        .sel1   (lsu_cpu_dcd_sel[5]),
        .sel2   (lsu_cpu_dcd_sel[6]),
        .sel3   (lsu_cpu_dcd_sel[7]),
        .dout   (cpx_cpuhi_inv_data[13:0])
);


mux2ds  #(14) invfld_sel (
        .in0    (cpx_cpulo_inv_data[13:0]),
        .in1    (cpx_cpuhi_inv_data[13:0]),
        .sel0   (~lsu_cpu_uhlf_sel),  
        .sel1   (lsu_cpu_uhlf_sel),
        .dout   (lsu_cpu_inv_data[13:0])
);

assign  lsu_cpu_inv_data_b13to9[13:9]  =  lsu_cpu_inv_data[13:9] ;
assign  lsu_cpu_inv_data_b7to2[7:2]  =  lsu_cpu_inv_data[7:2] ;
assign  lsu_cpu_inv_data_b0  =  lsu_cpu_inv_data[0] ;


wire  [13:0] cpx_cpulo_dcfill_wrway,
             cpx_cpuhi_dcfill_wrway,
             cpx_st_dcfill_wrway_sel;
             

mux4ds  #(14) st_dcfill_wrway_lo (
        .in0    ({cpx_spc_data_cx[`CPX_A11_C0_HI:`CPX_A11_C0_LO],
                  cpx_spc_data_cx[`CPX_A10_C0_HI:`CPX_A10_C0_LO],
                  cpx_spc_data_cx[`CPX_A01_C0_HI:`CPX_A01_C0_LO],
                  cpx_spc_data_cx[`CPX_A00_C0_HI:`CPX_A00_C0_LO]}),
        .in1    ({cpx_spc_data_cx[`CPX_A11_C1_HI:`CPX_A11_C1_LO],
                  cpx_spc_data_cx[`CPX_A10_C1_HI:`CPX_A10_C1_LO],
                  cpx_spc_data_cx[`CPX_A01_C1_HI:`CPX_A01_C1_LO],
                  cpx_spc_data_cx[`CPX_A00_C1_HI:`CPX_A00_C1_LO]}),
        .in2    ({cpx_spc_data_cx[`CPX_A11_C2_HI:`CPX_A11_C2_LO],
                  cpx_spc_data_cx[`CPX_A10_C2_HI:`CPX_A10_C2_LO],
                  cpx_spc_data_cx[`CPX_A01_C2_HI:`CPX_A01_C2_LO],
                  cpx_spc_data_cx[`CPX_A00_C2_HI:`CPX_A00_C2_LO]}),
        .in3    ({cpx_spc_data_cx[`CPX_A11_C3_HI:`CPX_A11_C3_LO],
                  cpx_spc_data_cx[`CPX_A10_C3_HI:`CPX_A10_C3_LO],
                  cpx_spc_data_cx[`CPX_A01_C3_HI:`CPX_A01_C3_LO],
                  cpx_spc_data_cx[`CPX_A00_C3_HI:`CPX_A00_C3_LO]}),
        .sel0   (lsu_cpu_dcd_sel[0]),
        .sel1   (lsu_cpu_dcd_sel[1]),
        .sel2   (lsu_cpu_dcd_sel[2]),
        .sel3   (lsu_cpu_dcd_sel[3]),
        .dout   (cpx_cpulo_dcfill_wrway[13:0])
);

mux4ds  #(14) st_dcfill_wrway_hi (
        .in0    ({cpx_spc_data_cx[`CPX_A11_C4_HI:`CPX_A11_C4_LO],
                  cpx_spc_data_cx[`CPX_A10_C4_HI:`CPX_A10_C4_LO],
                  cpx_spc_data_cx[`CPX_A01_C4_HI:`CPX_A01_C4_LO],
                  cpx_spc_data_cx[`CPX_A00_C4_HI:`CPX_A00_C4_LO]}),
        .in1    ({cpx_spc_data_cx[`CPX_A11_C5_HI:`CPX_A11_C5_LO],
                  cpx_spc_data_cx[`CPX_A10_C5_HI:`CPX_A10_C5_LO],
                  cpx_spc_data_cx[`CPX_A01_C5_HI:`CPX_A01_C5_LO],
                  cpx_spc_data_cx[`CPX_A00_C5_HI:`CPX_A00_C5_LO]}),
        .in2    ({cpx_spc_data_cx[`CPX_A11_C6_HI:`CPX_A11_C6_LO],
                  cpx_spc_data_cx[`CPX_A10_C6_HI:`CPX_A10_C6_LO],
                  cpx_spc_data_cx[`CPX_A01_C6_HI:`CPX_A01_C6_LO],
                  cpx_spc_data_cx[`CPX_A00_C6_HI:`CPX_A00_C6_LO]}),
        .in3    ({cpx_spc_data_cx[`CPX_A11_C7_HI:`CPX_A11_C7_LO],
                  cpx_spc_data_cx[`CPX_A10_C7_HI:`CPX_A10_C7_LO],
                  cpx_spc_data_cx[`CPX_A01_C7_HI:`CPX_A01_C7_LO],
                  cpx_spc_data_cx[`CPX_A00_C7_HI:`CPX_A00_C7_LO]}),
        .sel0   (lsu_cpu_dcd_sel[4]),
        .sel1   (lsu_cpu_dcd_sel[5]),
        .sel2   (lsu_cpu_dcd_sel[6]),
        .sel3   (lsu_cpu_dcd_sel[7]),
        .dout   (cpx_cpuhi_dcfill_wrway[13:0])
);



mux2ds  #(14) st_dcfill_wrway_sel (
        .in0    (cpx_cpulo_dcfill_wrway[13:0]),
        .in1    (cpx_cpuhi_dcfill_wrway[13:0]),
        .sel0   (~lsu_cpu_uhlf_sel),
        .sel1   (lsu_cpu_uhlf_sel),
        .dout   (cpx_st_dcfill_wrway_sel[13:0])
);





wire  [3:0]  st_dcfill_wrway_mxsel ;

assign st_dcfill_wrway_mxsel[0] =  (lsu_cpxpkt_type_dcd_cx[2] & cpx_st_dcfill_wrway_sel[0]) & ~rst_tri_en ;
assign st_dcfill_wrway_mxsel[1] =  (lsu_cpxpkt_type_dcd_cx[2] & cpx_st_dcfill_wrway_sel[4]) & ~rst_tri_en ;
assign st_dcfill_wrway_mxsel[2] =  (lsu_cpxpkt_type_dcd_cx[2] & cpx_st_dcfill_wrway_sel[7]) & ~rst_tri_en ;
assign st_dcfill_wrway_mxsel[3] =  ~|st_dcfill_wrway_mxsel[2:0] | rst_tri_en;

mux4ds  #(2) st_dcfill_wrway_sel_b54 (
        .in0    (cpx_st_dcfill_wrway_sel[3:2]),
        .in1    (cpx_st_dcfill_wrway_sel[6:5]),
        .in2    (cpx_st_dcfill_wrway_sel[10:9]),
        .in3    (cpx_st_dcfill_wrway_sel[13:12]),
        .sel0   (st_dcfill_wrway_mxsel[0]),
        .sel1   (st_dcfill_wrway_mxsel[1]),
        .sel2   (st_dcfill_wrway_mxsel[2]),
        .sel3   (st_dcfill_wrway_mxsel[3]),
        .dout   (cpx_st_dcfill_wrway[1:0])
);


assign  cpx_st_ack_addr_b54[0] = cpx_st_dcfill_wrway_sel[4] | cpx_st_dcfill_wrway_sel[11] ;
assign  cpx_st_ack_addr_b54[1] = cpx_st_dcfill_wrway_sel[7] | cpx_st_dcfill_wrway_sel[11] ;

















  



   wire [63:0] diagnstc_wr_data;
   
dff_s  #(64) diagnstc_wr_data_ff (
        .din    (lsu_diagnstc_wr_data_e[63:0]), 
        .q      (diagnstc_wr_data[63:0]),
        .clk    (clk),
        .se     (1'b0),     .si (),          .so ()
        ); 
   
mux2ds  #(64) dcwr_sel (

  .in0  ({dfq_byp_ff_data[`STB_DFQ_DA_HI:`STB_DFQ_DA_LO]}),
  .in1  ({diagnstc_wr_data[63:0]}),
  .sel0 ( lsu_dfq_st_vld),  
  .sel1 (~lsu_dfq_st_vld),


  .dout (dcache_wr_data[63:0])
);






assign st_dcfill_data[127:0] =
  {








   dcache_wr_data[63:0],
   dcache_wr_data[63:0]};

   assign st_dcfill_addr[10:0] =    
   {dfq_byp_ff_data[`CPX_INV_PA_HI:`CPX_INV_PA_LO],
    dfq_byp_ff_data[86:85],
    dfq_byp_ff_data[`STB_DFQ_AD_LO+3:`STB_DFQ_AD_LO]};
   




   assign lsu_st_way_e[1:0] = dfq_byp_ff_data[84:83];
   assign lsu_st_dcfill_size_e [1:0] = dfq_byp_ff_data[`STB_DFQ_SZ_HI:`STB_DFQ_SZ_LO];
       
assign ldinv_dcfill_data[127:0] =
  {







   dfq_byp_ff_data[`DFQ_DA_HI:`DFQ_DA_LO]};






mux2ds  #(128) dfq_pkt_src (
  .in0  (st_dcfill_data[127:0]),    
  .in1  (ldinv_dcfill_data[127:0]), 
  .sel0 (~lsu_dfq_ld_vld),  
  .sel1 (lsu_dfq_ld_vld),
  .dout (lsu_dcfill_data[127:0])
);


wire  [15:0]  dcache_wr_parity ;
lsu_dc_parity_gen parity_gen (
    .data_in  (lsu_dcfill_data[`DCFILL_DA_HI:`DCFILL_DA_LO]),
    .parity_out (dcache_wr_parity[15:0])
  );





wire	ld_unc_error ;
assign	ld_unc_error = (dfq_byp_ff_data[138] & dfq_byp_ff_data[`DFQ_WIDTH-1]);





   wire [15:0] parity_byte_flip;
   assign      parity_byte_flip[15:0] = dcache_wr_parity[15:0] ^ {16{ld_unc_error }};
   





wire  [15:0]  diagnstc_wr_parity;

assign diagnstc_wr_parity[15:0]  =  {lsu_diagnstc_dc_prty_invrt_e[7:0],lsu_diagnstc_dc_prty_invrt_e[7:0]} ^ dcache_wr_parity[15:0];

mux2ds  #(16) dcache_wr_parity_mod_mux (
              .in0(diagnstc_wr_parity[15:0]),

              .in1(parity_byte_flip[15:0]),
              .sel0(~lsu_dfq_ldst_vld),
              .sel1( lsu_dfq_ldst_vld),


              .dout(dcache_wr_parity_mod[15:0])
);










   












wire	[63:0] misc_fill_data_e ;





   wire [7:0] mbist_write_data_d1;

dff_s #(8) mbist_write_data_ff (
   .din (mbist_write_data[7:0]),
   .q   (mbist_write_data_d1[7:0]),
   .clk    (clk),
   .se     (1'b0),     .si (),          .so ()
); 
    

   wire      [3:0] misc_fill_parity_e;
assign    misc_fill_parity_e[3:0] = {4{~lsu_dc_iob_access_e}} & mbist_write_data_d1[3:0];

mux2ds  #(64) misc_fill_data_e_mux (
              .in0(dcache_iob_data_e[63:0]),
              .in1({8{mbist_write_data_d1[7:0]}}),
              .sel0(lsu_dc_iob_access_e),
              .sel1(~lsu_dc_iob_access_e),
              .dout(misc_fill_data_e[63:0])
);

mux2ds  #(144) lsu_dcache_fill_data_e_mux (
               .in0({misc_fill_data_e[63:0],misc_fill_data_e[63:0],{4{misc_fill_parity_e[3:0]}}}),
               .in1({lsu_dcfill_data[`DCFILL_DA_HI:`DCFILL_DA_LO],dcache_wr_parity_mod[15:0]}),
               .sel0(lsu_dcfill_data_mx_sel_e),
               .sel1(~lsu_dcfill_data_mx_sel_e),
               .dout(lsu_dcache_fill_data_e[143:0])
);








   


   






   
 


















































wire [63:0] l2fill_data_e;
 
mux2ds        #(64) half_sel (
      .in0    (lsu_dcfill_data[`DCFILL_DA_HI:`DCFILL_DA_LO+64]),
      .in1    (lsu_dcfill_data[`DCFILL_DA_LO+63:`DCFILL_DA_LO]),
      .sel0   (lsu_dfill_data_sel_hi),  .sel1 (~lsu_dfill_data_sel_hi),
      .dout   (l2fill_data_e[63:0])
);

dff_s #(64) stgm_l2fd (
        .din    (l2fill_data_e[63:0]),
        .q      (lsu_l2fill_data[63:0]),
        .clk    (clk),
        .se     (se),       .si (),          .so ()
        );

endmodule