data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v
1: b'%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:33: Cannot find include file: nf_sume_blueswitch_register_define.v\n`include "nf_sume_blueswitch_register_define.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog,data/full_repos/permissive/498471995/nf_sume_blueswitch_register_define.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog,data/full_repos/permissive/498471995/nf_sume_blueswitch_register_define.v.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog,data/full_repos/permissive/498471995/nf_sume_blueswitch_register_define.v.sv\n             nf_sume_blueswitch_register_define.v\n             nf_sume_blueswitch_register_define.v.v\n             nf_sume_blueswitch_register_define.v.sv\n             obj_dir/nf_sume_blueswitch_register_define.v\n             obj_dir/nf_sume_blueswitch_register_define.v.v\n             obj_dir/nf_sume_blueswitch_register_define.v.sv\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:34: Cannot find include file: nf_sume_blueswitch_parameter_define.v\n`include "nf_sume_blueswitch_parameter_define.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:60: Define or directive not defined: \'`DEF_SW_TAG_VAL\'\n   output   reg   [`DEF_SW_TAG_VAL-1:0]               bus_sw_tag_val,\n                   ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:74: Define or directive not defined: \'`CLR_COUNT\'\nwire  wren_0010 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `CLR_COUNT)) & ~Bus2IP_RNW;\n                                                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:74: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nwire  wren_0010 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `CLR_COUNT)) & ~Bus2IP_RNW;\n                                                                                 ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:77: Define or directive not defined: \'`TS_POSITION\'\nwire  wren_0014 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `TS_POSITION)) & ~Bus2IP_RNW;\n                                                                       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:77: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nwire  wren_0014 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `TS_POSITION)) & ~Bus2IP_RNW;\n                                                                                   ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:78: Define or directive not defined: \'`TS_POSITION\'\nwire  rden_0014 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `TS_POSITION)) & Bus2IP_RNW;\n                                                                       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:78: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nwire  rden_0014 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `TS_POSITION)) & Bus2IP_RNW;\n                                                                                   ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:84: Define or directive not defined: \'`MISS_FWD\'\nwire  wren_0018 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `MISS_FWD)) & ~Bus2IP_RNW;\n                                                                       ^~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:84: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nwire  wren_0018 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `MISS_FWD)) & ~Bus2IP_RNW;\n                                                                                ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:85: Define or directive not defined: \'`MISS_FWD\'\nwire  rden_0018 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `MISS_FWD)) & Bus2IP_RNW;\n                                                                       ^~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:85: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nwire  rden_0018 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `MISS_FWD)) & Bus2IP_RNW;\n                                                                                ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:89: Define or directive not defined: \'`RX_BYTE_COUNT\'\nwire  rden_0020 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `RX_BYTE_COUNT)) & Bus2IP_RNW;\n                                                                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:89: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nwire  rden_0020 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `RX_BYTE_COUNT)) & Bus2IP_RNW;\n                                                                                     ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:91: Define or directive not defined: \'`RX_PKT_COUNT\'\nwire  rden_0024 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `RX_PKT_COUNT)) & Bus2IP_RNW;\n                                                                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:91: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nwire  rden_0024 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `RX_PKT_COUNT)) & Bus2IP_RNW;\n                                                                                    ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:93: Define or directive not defined: \'`TX_BYTE_COUNT\'\nwire  rden_0028 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `TX_BYTE_COUNT)) & Bus2IP_RNW;\n                                                                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:93: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nwire  rden_0028 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `TX_BYTE_COUNT)) & Bus2IP_RNW;\n                                                                                     ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:95: Define or directive not defined: \'`TX_PKT_COUNT\'\nwire  rden_002c = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `TX_PKT_COUNT)) & Bus2IP_RNW;\n                                                                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:95: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nwire  rden_002c = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `TX_PKT_COUNT)) & Bus2IP_RNW;\n                                                                                    ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:98: Define or directive not defined: \'`RX_FIFO_DEPTH\'\nwire  rden_0060 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `RX_FIFO_DEPTH)) & Bus2IP_RNW;\n                                                                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:98: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nwire  rden_0060 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `RX_FIFO_DEPTH)) & Bus2IP_RNW;\n                                                                                     ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:100: Define or directive not defined: \'`RX_FIFO_DEPTH_MAX\'\nwire  rden_0064 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `RX_FIFO_DEPTH_MAX)) & Bus2IP_RNW;\n                                                                       ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:100: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nwire  rden_0064 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `RX_FIFO_DEPTH_MAX)) & Bus2IP_RNW;\n                                                                                         ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:103: Define or directive not defined: \'`SW_TAG_VAL\'\nwire  wren_SW_TAG_VAL = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `SW_TAG_VAL)) & ~Bus2IP_RNW;\n                                                                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:103: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nwire  wren_SW_TAG_VAL = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `SW_TAG_VAL)) & ~Bus2IP_RNW;\n                                                                                        ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:105: Define or directive not defined: \'`SW_TAG\'\nwire  wren_SW_TAG = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `SW_TAG)) & ~Bus2IP_RNW;\n                                                                         ^~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:105: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nwire  wren_SW_TAG = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `SW_TAG)) & ~Bus2IP_RNW;\n                                                                                ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:106: Define or directive not defined: \'`SW_TAG\'\nwire  rden_SW_TAG = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `SW_TAG)) &  Bus2IP_RNW;\n                                                                         ^~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:106: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nwire  rden_SW_TAG = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `SW_TAG)) &  Bus2IP_RNW;\n                                                                                ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:150: Define or directive not defined: \'`DEF_SW_TAG_VAL\'\n      bus_sw_tag_val <= Bus2IP_Data[0+:`DEF_SW_TAG_VAL];\n                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/data_processor_controller.v:150: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n      bus_sw_tag_val <= Bus2IP_Data[0+:`DEF_SW_TAG_VAL];\n                                                      ^\n%Error: Exiting due to 33 error(s)\n'
module data_processor_controller
#(
   parameter   C_S_AXI_ADDR_WIDTH      = 32,
   parameter   C_S_AXI_DATA_WIDTH      = 32,
   parameter   BASEADDR_OFFSET         = 16'h0
)
(
   input                                              Bus2IP_Clk,
   input                                              Bus2IP_Resetn,
   input          [C_S_AXI_ADDR_WIDTH-1:0]            Bus2IP_Addr,
   input          [0:0]                               Bus2IP_CS,
   input                                              Bus2IP_RNW,
   input          [C_S_AXI_DATA_WIDTH-1:0]            Bus2IP_Data,
   input          [C_S_AXI_DATA_WIDTH/8-1:0]          Bus2IP_BE,
   output   reg   [C_S_AXI_DATA_WIDTH-1:0]            IP2Bus_Data,
   output   reg                                       IP2Bus_RdAck,
   output   reg                                       IP2Bus_WrAck,

   output   reg                                       bus_clear_cnt,
   output   reg   [7:0]                               bus_miss_fwd_port_map,
   output   reg                                       bus_ts_valid,
   output   reg   [7:0]                               bus_slave_ts_position,
   output   reg   [7:0]                               bus_master_ts_position,
   output   reg   [C_S_AXI_DATA_WIDTH-1:0]            bus_sw_tag,
   output   reg   [`DEF_SW_TAG_VAL-1:0]               bus_sw_tag_val,
   input                                              clear_sw_tag_val,

   input          [C_S_AXI_DATA_WIDTH-1:0]            bus_rx_byte_cnt,
   input          [C_S_AXI_DATA_WIDTH-1:0]            bus_rx_pkt_cnt,
   input          [C_S_AXI_DATA_WIDTH-1:0]            bus_tx_byte_cnt,
   input          [C_S_AXI_DATA_WIDTH-1:0]            bus_tx_pkt_cnt,
   input          [C_S_AXI_DATA_WIDTH-1:0]            bus_rx_fifo_depth,
   input          [C_S_AXI_DATA_WIDTH-1:0]            bus_rx_fifo_depth_max
);

reg   [7:0]    RdAckCnt;


wire  wren_0010 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `CLR_COUNT)) & ~Bus2IP_RNW;


wire  wren_0014 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `TS_POSITION)) & ~Bus2IP_RNW;
wire  rden_0014 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `TS_POSITION)) & Bus2IP_RNW;
wire  wren_0030 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + 16'h0030)) & ~Bus2IP_RNW;
wire  rden_0030 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + 16'h0030)) & Bus2IP_RNW;



wire  wren_0018 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `MISS_FWD)) & ~Bus2IP_RNW;
wire  rden_0018 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `MISS_FWD)) & Bus2IP_RNW;



wire  rden_0020 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `RX_BYTE_COUNT)) & Bus2IP_RNW;

wire  rden_0024 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `RX_PKT_COUNT)) & Bus2IP_RNW;

wire  rden_0028 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `TX_BYTE_COUNT)) & Bus2IP_RNW;

wire  rden_002c = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `TX_PKT_COUNT)) & Bus2IP_RNW;


wire  rden_0060 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `RX_FIFO_DEPTH)) & Bus2IP_RNW;

wire  rden_0064 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `RX_FIFO_DEPTH_MAX)) & Bus2IP_RNW;


wire  wren_SW_TAG_VAL = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `SW_TAG_VAL)) & ~Bus2IP_RNW;

wire  wren_SW_TAG = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `SW_TAG)) & ~Bus2IP_RNW;
wire  rden_SW_TAG = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `SW_TAG)) &  Bus2IP_RNW;


always @(posedge Bus2IP_Clk)
   if (~Bus2IP_Resetn)
      bus_clear_cnt  <= 0;
   else
      bus_clear_cnt  <= wren_0010;


always @(posedge Bus2IP_Clk)
   if (~Bus2IP_Resetn) begin
      bus_slave_ts_position    <= 0;
      bus_master_ts_position   <= 0;
   end
   else begin
      bus_slave_ts_position    <= (wren_0014) ? Bus2IP_Data[0+:8]  : bus_slave_ts_position;
      bus_master_ts_position   <= (wren_0014) ? Bus2IP_Data[16+:8] : bus_master_ts_position;
   end

always @(posedge Bus2IP_Clk)
   if (~Bus2IP_Resetn) begin
      bus_ts_valid   <= 0;
   end
   else if (wren_0030) begin
      bus_ts_valid   <= Bus2IP_Data[0];
   end

always @(posedge Bus2IP_Clk)
   if (~Bus2IP_Resetn) begin
      bus_miss_fwd_port_map   <= 0;
   end
   else if (wren_0018) begin
      bus_miss_fwd_port_map   <= Bus2IP_Data[0+:8];
   end

always @(posedge Bus2IP_Clk)
   if (~Bus2IP_Resetn) begin
      bus_sw_tag_val <= 0;
   end
   else if (clear_sw_tag_val) begin
      bus_sw_tag_val <= 0;
   end
   else if (wren_SW_TAG_VAL) begin
      bus_sw_tag_val <= Bus2IP_Data[0+:`DEF_SW_TAG_VAL];
   end

always @(posedge Bus2IP_Clk)
   if (~Bus2IP_Resetn) begin
      bus_sw_tag  <= 32'h0123abcd;
   end
   else if (wren_SW_TAG) begin
      bus_sw_tag  <= Bus2IP_Data;
   end

always @(posedge Bus2IP_Clk)
   if (~Bus2IP_Resetn) begin
      IP2Bus_WrAck   <= 0;
   end
   else if (IP2Bus_WrAck) begin
      IP2Bus_WrAck   <= (Bus2IP_CS) ? 1 : 0;
   end
   else if (Bus2IP_CS & ~Bus2IP_RNW) begin
      IP2Bus_WrAck   <= 1;
   end


always @(posedge Bus2IP_Clk)
   if (~Bus2IP_Resetn) begin
      RdAckCnt       <= 0;
      IP2Bus_RdAck   <= 0;
      IP2Bus_Data    <= 0;
   end
   else if (IP2Bus_RdAck) begin
      RdAckCnt       <= 0;
      IP2Bus_RdAck   <= (Bus2IP_CS) ? 1 : 0;
   end
   else if (RdAckCnt == 7) begin
      RdAckCnt       <= 0;
      IP2Bus_RdAck   <= 1;
      begin
         if      (rden_0014)  IP2Bus_Data <= {8'h0, bus_master_ts_position, 8'h0, bus_slave_ts_position};
         else if (rden_0018)  IP2Bus_Data <= {24'h0, bus_miss_fwd_port_map};
         else if (rden_0020)  IP2Bus_Data <= bus_rx_byte_cnt;
         else if (rden_0024)  IP2Bus_Data <= bus_rx_pkt_cnt;
         else if (rden_0028)  IP2Bus_Data <= bus_tx_byte_cnt;
         else if (rden_002c)  IP2Bus_Data <= bus_tx_pkt_cnt;
         else if (rden_0030)  IP2Bus_Data <= {31'h0, bus_ts_valid};
         else if (rden_0060)  IP2Bus_Data <= bus_rx_fifo_depth;
         else if (rden_0064)  IP2Bus_Data <= bus_rx_fifo_depth_max;
         else if (rden_SW_TAG)   IP2Bus_Data <= bus_sw_tag;
      end
   end
   else if (RdAckCnt > 0) begin
      RdAckCnt       <= RdAckCnt + 1;
      IP2Bus_RdAck   <= 0;
   end
   else if (Bus2IP_CS & Bus2IP_RNW) begin
      RdAckCnt       <= 1;
      IP2Bus_RdAck   <= 0;
   end

endmodule
module data_processor_controller
#(
   parameter   C_S_AXI_ADDR_WIDTH      = 32,
   parameter   C_S_AXI_DATA_WIDTH      = 32,
   parameter   BASEADDR_OFFSET         = 16'h0
)
(
   input                                              Bus2IP_Clk,
   input                                              Bus2IP_Resetn,
   input          [C_S_AXI_ADDR_WIDTH-1:0]            Bus2IP_Addr,
   input          [0:0]                               Bus2IP_CS,
   input                                              Bus2IP_RNW,
   input          [C_S_AXI_DATA_WIDTH-1:0]            Bus2IP_Data,
   input          [C_S_AXI_DATA_WIDTH/8-1:0]          Bus2IP_BE,
   output   reg   [C_S_AXI_DATA_WIDTH-1:0]            IP2Bus_Data,
   output   reg                                       IP2Bus_RdAck,
   output   reg                                       IP2Bus_WrAck,

   output   reg                                       bus_clear_cnt,
   output   reg   [7:0]                               bus_miss_fwd_port_map,
   output   reg                                       bus_ts_valid,
   output   reg   [7:0]                               bus_slave_ts_position,
   output   reg   [7:0]                               bus_master_ts_position,
   output   reg   [C_S_AXI_DATA_WIDTH-1:0]            bus_sw_tag,
   output   reg   [`DEF_SW_TAG_VAL-1:0]               bus_sw_tag_val,
   input                                              clear_sw_tag_val,

   input          [C_S_AXI_DATA_WIDTH-1:0]            bus_rx_byte_cnt,
   input          [C_S_AXI_DATA_WIDTH-1:0]            bus_rx_pkt_cnt,
   input          [C_S_AXI_DATA_WIDTH-1:0]            bus_tx_byte_cnt,
   input          [C_S_AXI_DATA_WIDTH-1:0]            bus_tx_pkt_cnt,
   input          [C_S_AXI_DATA_WIDTH-1:0]            bus_rx_fifo_depth,
   input          [C_S_AXI_DATA_WIDTH-1:0]            bus_rx_fifo_depth_max
);


reg   [7:0]    RdAckCnt;


wire  wren_0010 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `CLR_COUNT)) & ~Bus2IP_RNW;


wire  wren_0014 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `TS_POSITION)) & ~Bus2IP_RNW;
wire  rden_0014 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `TS_POSITION)) & Bus2IP_RNW;
wire  wren_0030 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + 16'h0030)) & ~Bus2IP_RNW;
wire  rden_0030 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + 16'h0030)) & Bus2IP_RNW;



wire  wren_0018 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `MISS_FWD)) & ~Bus2IP_RNW;
wire  rden_0018 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `MISS_FWD)) & Bus2IP_RNW;



wire  rden_0020 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `RX_BYTE_COUNT)) & Bus2IP_RNW;

wire  rden_0024 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `RX_PKT_COUNT)) & Bus2IP_RNW;

wire  rden_0028 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `TX_BYTE_COUNT)) & Bus2IP_RNW;

wire  rden_002c = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `TX_PKT_COUNT)) & Bus2IP_RNW;


wire  rden_0060 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `RX_FIFO_DEPTH)) & Bus2IP_RNW;

wire  rden_0064 = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `RX_FIFO_DEPTH_MAX)) & Bus2IP_RNW;


wire  wren_SW_TAG_VAL = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `SW_TAG_VAL)) & ~Bus2IP_RNW;

wire  wren_SW_TAG = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `SW_TAG)) & ~Bus2IP_RNW;
wire  rden_SW_TAG = Bus2IP_CS & (Bus2IP_Addr[15:0] == (BASEADDR_OFFSET + `SW_TAG)) &  Bus2IP_RNW;


always @(posedge Bus2IP_Clk)
   if (~Bus2IP_Resetn)
      bus_clear_cnt  <= 0;
   else
      bus_clear_cnt  <= wren_0010;


always @(posedge Bus2IP_Clk)
   if (~Bus2IP_Resetn) begin
      bus_slave_ts_position    <= 0;
      bus_master_ts_position   <= 0;
   end
   else begin
      bus_slave_ts_position    <= (wren_0014) ? Bus2IP_Data[0+:8]  : bus_slave_ts_position;
      bus_master_ts_position   <= (wren_0014) ? Bus2IP_Data[16+:8] : bus_master_ts_position;
   end

always @(posedge Bus2IP_Clk)
   if (~Bus2IP_Resetn) begin
      bus_ts_valid   <= 0;
   end
   else if (wren_0030) begin
      bus_ts_valid   <= Bus2IP_Data[0];
   end

always @(posedge Bus2IP_Clk)
   if (~Bus2IP_Resetn) begin
      bus_miss_fwd_port_map   <= 0;
   end
   else if (wren_0018) begin
      bus_miss_fwd_port_map   <= Bus2IP_Data[0+:8];
   end

always @(posedge Bus2IP_Clk)
   if (~Bus2IP_Resetn) begin
      bus_sw_tag_val <= 0;
   end
   else if (clear_sw_tag_val) begin
      bus_sw_tag_val <= 0;
   end
   else if (wren_SW_TAG_VAL) begin
      bus_sw_tag_val <= Bus2IP_Data[0+:`DEF_SW_TAG_VAL];
   end

always @(posedge Bus2IP_Clk)
   if (~Bus2IP_Resetn) begin
      bus_sw_tag  <= 32'h0123abcd;
   end
   else if (wren_SW_TAG) begin
      bus_sw_tag  <= Bus2IP_Data;
   end

always @(posedge Bus2IP_Clk)
   if (~Bus2IP_Resetn) begin
      IP2Bus_WrAck   <= 0;
   end
   else if (IP2Bus_WrAck) begin
      IP2Bus_WrAck   <= (Bus2IP_CS) ? 1 : 0;
   end
   else if (Bus2IP_CS & ~Bus2IP_RNW) begin
      IP2Bus_WrAck   <= 1;
   end


always @(posedge Bus2IP_Clk)
   if (~Bus2IP_Resetn) begin
      RdAckCnt       <= 0;
      IP2Bus_RdAck   <= 0;
      IP2Bus_Data    <= 0;
   end
   else if (IP2Bus_RdAck) begin
      RdAckCnt       <= 0;
      IP2Bus_RdAck   <= (Bus2IP_CS) ? 1 : 0;
   end
   else if (RdAckCnt == 7) begin
      RdAckCnt       <= 0;
      IP2Bus_RdAck   <= 1;
      begin
         if      (rden_0014)  IP2Bus_Data <= {8'h0, bus_master_ts_position, 8'h0, bus_slave_ts_position};
         else if (rden_0018)  IP2Bus_Data <= {24'h0, bus_miss_fwd_port_map};
         else if (rden_0020)  IP2Bus_Data <= bus_rx_byte_cnt;
         else if (rden_0024)  IP2Bus_Data <= bus_rx_pkt_cnt;
         else if (rden_0028)  IP2Bus_Data <= bus_tx_byte_cnt;
         else if (rden_002c)  IP2Bus_Data <= bus_tx_pkt_cnt;
         else if (rden_0030)  IP2Bus_Data <= {31'h0, bus_ts_valid};
         else if (rden_0060)  IP2Bus_Data <= bus_rx_fifo_depth;
         else if (rden_0064)  IP2Bus_Data <= bus_rx_fifo_depth_max;
         else if (rden_SW_TAG)   IP2Bus_Data <= bus_sw_tag;
      end
   end
   else if (RdAckCnt > 0) begin
      RdAckCnt       <= RdAckCnt + 1;
      IP2Bus_RdAck   <= 0;
   end
   else if (Bus2IP_CS & Bus2IP_RNW) begin
      RdAckCnt       <= 1;
      IP2Bus_RdAck   <= 0;
   end

endmodule