data/full_repos/permissive/530451077/src/user_module_341193419111006803_tb.v
1: b'%Error: data/full_repos/permissive/530451077/src/user_module_341193419111006803_tb.v:17: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("user_module_341193419111006803_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/530451077/src/user_module_341193419111006803_tb.v:18: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, user_module_341193419111006803_tb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/530451077/src/user_module_341193419111006803_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n   #100_000_000;  \n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/530451077/src/user_module_341193419111006803_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #(CLK_HALF_PERIOD);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/530451077/src/user_module_341193419111006803_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #(CLK_HALF_PERIOD);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/530451077/src/user_module_341193419111006803_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #20\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/530451077/src/user_module_341193419111006803_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #(CLK_HALF_PERIOD);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/530451077/src/user_module_341193419111006803_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #(CLK_HALF_PERIOD);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/530451077/src/user_module_341193419111006803_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #(5*TCLK)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/530451077/src/user_module_341193419111006803_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #(TCLK);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/530451077/src/user_module_341193419111006803_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #(63*TCLK);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/530451077/src/user_module_341193419111006803_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #(TCLK);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/530451077/src/user_module_341193419111006803_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n    #(63*TCLK);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/530451077/src/user_module_341193419111006803_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n    #(64*TCLK);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/530451077/src/user_module_341193419111006803_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n    #(64*TCLK);\n    ^\n%Error: Exiting due to 2 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module user_module_341193419111006803_tb;

wire [7:0] io_in;
wire [7:0] io_out;

reg clk, reset, write_en;
reg [4:0] pdm_input;

assign io_in = {pdm_input, write_en, reset, clk};

user_module_341193419111006803 UUT (.io_in(io_in), .io_out(io_out));

initial begin
  $dumpfile("user_module_341193419111006803_tb.vcd");
  $dumpvars(0, user_module_341193419111006803_tb);
end

initial begin
   #100_000_000;
   $display("Caught by trap");
   $finish;
 end

parameter CLK_HALF_PERIOD = 5;
parameter TCLK = 2*CLK_HALF_PERIOD;
always begin
    clk = 1'b1;
    #(CLK_HALF_PERIOD);
    clk = 1'b0;
    #(CLK_HALF_PERIOD);
end

initial 
begin
    #20
    reset = 1;
    #(CLK_HALF_PERIOD);
    reset = 0;
end

initial begin
    write_en = 0;
    pdm_input = 5'h00;
    #(CLK_HALF_PERIOD);
    #(5*TCLK)
    write_en = 1;
    pdm_input= 5'h08;
    #(TCLK);
    write_en = 0;
    #(63*TCLK);
    write_en = 1;
    pdm_input= 5'h1a;
    #(TCLK);
    write_en = 0;
    #(63*TCLK);
    write_en = 1;
    pdm_input= 5'h0f;
    #(64*TCLK);
    pdm_input= 5'h04;
    #(64*TCLK);
    $finish;
end

endmodule
module user_module_341193419111006803_tb;


wire [7:0] io_in;
wire [7:0] io_out;

reg clk, reset, write_en;
reg [4:0] pdm_input;

assign io_in = {pdm_input, write_en, reset, clk};

user_module_341193419111006803 UUT (.io_in(io_in), .io_out(io_out));

initial begin
  $dumpfile("user_module_341193419111006803_tb.vcd");
  $dumpvars(0, user_module_341193419111006803_tb);
end

initial begin
   #100_000_000;
   $display("Caught by trap");
   $finish;
 end

parameter CLK_HALF_PERIOD = 5;
parameter TCLK = 2*CLK_HALF_PERIOD;
always begin
    clk = 1'b1;
    #(CLK_HALF_PERIOD);
    clk = 1'b0;
    #(CLK_HALF_PERIOD);
end

initial 
begin
    #20
    reset = 1;
    #(CLK_HALF_PERIOD);
    reset = 0;
end

initial begin
    write_en = 0;
    pdm_input = 5'h00;
    #(CLK_HALF_PERIOD);
    #(5*TCLK)
    write_en = 1;
    pdm_input= 5'h08;
    #(TCLK);
    write_en = 0;
    #(63*TCLK);
    write_en = 1;
    pdm_input= 5'h1a;
    #(TCLK);
    write_en = 0;
    #(63*TCLK);
    write_en = 1;
    pdm_input= 5'h0f;
    #(64*TCLK);
    pdm_input= 5'h04;
    #(64*TCLK);
    $finish;
end

endmodule