data/full_repos/permissive/469804105/RTL/Project_files/Top_level_design.v
1: b"%Error: data/full_repos/permissive/469804105/RTL/Project_files/Top_level_design.v:27: Pin is not an in/out/inout/interface: 'done'\ni_clk , data_in_1 , data_in_2 , start , p_STATE , o_reg_Q , o_reg_R  , o_reg_B ,Count_out , done );\n                                                                                            ^~~~\n%Error: Exiting due to 1 error(s)\n"
module Top_level_design(
i_clk , data_in_1 , data_in_2 , start , p_STATE , o_reg_Q , o_reg_R  , o_reg_B ,Count_out , done );

input i_clk ;
input [`WIDTH1-1:0] data_in_1 ;

input start ;
input [`WIDTH1-1:0] data_in_2 ;
output [`WIDTH1-1:0] o_reg_B ;
output [`WIDTH1-1:0] o_reg_R ;
output [`WIDTH1-1:0] o_reg_Q ;
output [`WIDTH3-1:0] p_STATE ; 
wire R_out , add_enable  , load_b , load_r, load_q, clr_nn;
wire  enable_q  , done , shift_en_q , clr_Reg_r , clr_ADD , clr_d, z_cnt,load_cnt ;
output [`WIDTH4-1:0] Count_out ;
output done ;
 DATAPATH DU(
i_clk ,
clr_d , 
clr_nn ,   
shift_en_q , 
enable_q , 
enable_r ,
data_in_1 ,
data_in_2 , 
o_reg_B , 
o_reg_R ,
o_reg_Q  ,
load_b ,
load_cnt,
load_r , 
load_q  , 
add_enable ,
R_out , 
clr_ADD ,
clr_Reg_r, 
z_cnt , 
Count_out 
);


CONTROLLER CU(
i_clk,
clr_d , 
start,
load_r ,
load_b ,
load_q ,
R_out, 
enable_r ,
enable_q , 
p_STATE ,
add_enable , 
done , 
shift_en_q ,
clr_ADD , 
clr_Reg_r , 
load_cnt , 
z_cnt , 
clr_nn);






endmodule
module Top_level_design(
i_clk , data_in_1 , data_in_2 , start , p_STATE , o_reg_Q , o_reg_R  , o_reg_B ,Count_out , done );


input i_clk ;
input [`WIDTH1-1:0] data_in_1 ;

input start ;
input [`WIDTH1-1:0] data_in_2 ;
output [`WIDTH1-1:0] o_reg_B ;
output [`WIDTH1-1:0] o_reg_R ;
output [`WIDTH1-1:0] o_reg_Q ;
output [`WIDTH3-1:0] p_STATE ; 
wire R_out , add_enable  , load_b , load_r, load_q, clr_nn;
wire  enable_q  , done , shift_en_q , clr_Reg_r , clr_ADD , clr_d, z_cnt,load_cnt ;
output [`WIDTH4-1:0] Count_out ;
output done ;
 DATAPATH DU(
i_clk ,
clr_d , 
clr_nn ,   
shift_en_q , 
enable_q , 
enable_r ,
data_in_1 ,
data_in_2 , 
o_reg_B , 
o_reg_R ,
o_reg_Q  ,
load_b ,
load_cnt,
load_r , 
load_q  , 
add_enable ,
R_out , 
clr_ADD ,
clr_Reg_r, 
z_cnt , 
Count_out 
);


CONTROLLER CU(
i_clk,
clr_d , 
start,
load_r ,
load_b ,
load_q ,
R_out, 
enable_r ,
enable_q , 
p_STATE ,
add_enable , 
done , 
shift_en_q ,
clr_ADD , 
clr_Reg_r , 
load_cnt , 
z_cnt , 
clr_nn);






endmodule