data/full_repos/permissive/45272408/buildCONNECT4x4/testbench_sample.v
1: b'%Error: data/full_repos/permissive/45272408/buildCONNECT4x4/testbench_sample.v:50: Cannot find include file: connect_parameters.v\n`include "connect_parameters.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/45272408/buildCONNECT4x4,data/full_repos/permissive/45272408/connect_parameters.v\n             data/full_repos/permissive/45272408/buildCONNECT4x4,data/full_repos/permissive/45272408/connect_parameters.v.v\n             data/full_repos/permissive/45272408/buildCONNECT4x4,data/full_repos/permissive/45272408/connect_parameters.v.sv\n             connect_parameters.v\n             connect_parameters.v.v\n             connect_parameters.v.sv\n             obj_dir/connect_parameters.v\n             obj_dir/connect_parameters.v.v\n             obj_dir/connect_parameters.v.sv\n%Error: data/full_repos/permissive/45272408/buildCONNECT4x4/testbench_sample.v:58: Define or directive not defined: \'`NUM_VCS\'\n  localparam vc_bits = (`NUM_VCS > 1) ? $clog2(`NUM_VCS) : 1;\n                        ^~~~~~~~\n%Error: data/full_repos/permissive/45272408/buildCONNECT4x4/testbench_sample.v:58: syntax error, unexpected \'>\', expecting TYPE-IDENTIFIER\n  localparam vc_bits = (`NUM_VCS > 1) ? $clog2(`NUM_VCS) : 1;\n                                 ^\n%Error: data/full_repos/permissive/45272408/buildCONNECT4x4/testbench_sample.v:58: Define or directive not defined: \'`NUM_VCS\'\n  localparam vc_bits = (`NUM_VCS > 1) ? $clog2(`NUM_VCS) : 1;\n                                               ^~~~~~~~\n%Error: data/full_repos/permissive/45272408/buildCONNECT4x4/testbench_sample.v:59: Define or directive not defined: \'`NUM_USER_RECV_PORTS\'\n  localparam dest_bits = $clog2(`NUM_USER_RECV_PORTS);\n                                ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/45272408/buildCONNECT4x4/testbench_sample.v:59: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  localparam dest_bits = $clog2(`NUM_USER_RECV_PORTS);\n                                                    ^\n%Error: data/full_repos/permissive/45272408/buildCONNECT4x4/testbench_sample.v:60: Define or directive not defined: \'`FLIT_DATA_WIDTH\'\n  localparam flit_port_width = 2  + `FLIT_DATA_WIDTH + dest_bits + vc_bits;\n                                    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/45272408/buildCONNECT4x4/testbench_sample.v:68: Define or directive not defined: \'`NUM_USER_SEND_PORTS\'\n  reg send_flit [0:`NUM_USER_SEND_PORTS-1];  \n                   ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/45272408/buildCONNECT4x4/testbench_sample.v:69: Define or directive not defined: \'`NUM_USER_SEND_PORTS\'\n  reg [flit_port_width-1:0] flit_in [0:`NUM_USER_SEND_PORTS-1];  \n                                       ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/45272408/buildCONNECT4x4/testbench_sample.v:71: Define or directive not defined: \'`NUM_USER_RECV_PORTS\'\n  reg send_credit [0:`NUM_USER_RECV_PORTS-1];  \n                     ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/45272408/buildCONNECT4x4/testbench_sample.v:72: Define or directive not defined: \'`NUM_USER_RECV_PORTS\'\n  reg [credit_port_width-1:0] credit_in [0:`NUM_USER_RECV_PORTS-1];  \n                                           ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/45272408/buildCONNECT4x4/testbench_sample.v:75: Define or directive not defined: \'`NUM_USER_SEND_PORTS\'\n  wire [credit_port_width-1:0] credit_out [0:`NUM_USER_SEND_PORTS-1];\n                                             ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/45272408/buildCONNECT4x4/testbench_sample.v:76: Define or directive not defined: \'`NUM_USER_RECV_PORTS\'\n  wire [flit_port_width-1:0] flit_out [0:`NUM_USER_RECV_PORTS-1];\n                                         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/45272408/buildCONNECT4x4/testbench_sample.v:86: Define or directive not defined: \'`FLIT_DATA_WIDTH\'\n  reg [`FLIT_DATA_WIDTH-1:0] data;\n       ^~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/45272408/buildCONNECT4x4/testbench_sample.v:90: Unsupported: Ignoring delay on this delayed statement.\n  always #(HalfClkPeriod) Clk = ~Clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/45272408/buildCONNECT4x4/testbench_sample.v:95: Define or directive not defined: \'`NUM_USER_SEND_PORTS\'\n    for(i = 0; i < `NUM_USER_SEND_PORTS; i = i + 1) begin flit_in[i] = 0; send_flit[i] = 0; end\n                   ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/45272408/buildCONNECT4x4/testbench_sample.v:95: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    for(i = 0; i < `NUM_USER_SEND_PORTS; i = i + 1) begin flit_in[i] = 0; send_flit[i] = 0; end\n                                       ^\n%Error: data/full_repos/permissive/45272408/buildCONNECT4x4/testbench_sample.v:95: syntax error, unexpected \')\', expecting \';\'\n    for(i = 0; i < `NUM_USER_SEND_PORTS; i = i + 1) begin flit_in[i] = 0; send_flit[i] = 0; end\n                                                  ^\n%Error: data/full_repos/permissive/45272408/buildCONNECT4x4/testbench_sample.v:96: Define or directive not defined: \'`NUM_USER_RECV_PORTS\'\n    for(i = 0; i < `NUM_USER_RECV_PORTS; i = i + 1) begin credit_in[i] = 0; send_credit[i] = 0; end\n                   ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/45272408/buildCONNECT4x4/testbench_sample.v:96: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    for(i = 0; i < `NUM_USER_RECV_PORTS; i = i + 1) begin credit_in[i] = 0; send_credit[i] = 0; end\n                                       ^\n%Error: data/full_repos/permissive/45272408/buildCONNECT4x4/testbench_sample.v:129: Define or directive not defined: \'`NUM_USER_RECV_PORTS\'\n    for(i = 0; i < `NUM_USER_RECV_PORTS; i = i + 1) begin\n                   ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/45272408/buildCONNECT4x4/testbench_sample.v:129: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    for(i = 0; i < `NUM_USER_RECV_PORTS; i = i + 1) begin\n                                       ^\n%Error: Exiting due to 21 error(s), 1 warning(s)\n'
module CONNECT_testbench_sample();
  parameter HalfClkPeriod = 5;
  localparam ClkPeriod = 2*HalfClkPeriod;


  localparam vc_bits = (`NUM_VCS > 1) ? $clog2(`NUM_VCS) : 1;
  localparam dest_bits = $clog2(`NUM_USER_RECV_PORTS);
  localparam flit_port_width = 2+ `FLIT_DATA_WIDTH + dest_bits + vc_bits;
  localparam credit_port_width = 1 + vc_bits;
  localparam test_cycles = 20;

  reg Clk;
  reg Rst_n;


  reg send_flit [0:`NUM_USER_SEND_PORTS-1];
  reg [flit_port_width-1:0] flit_in [0:`NUM_USER_SEND_PORTS-1];

  reg send_credit [0:`NUM_USER_RECV_PORTS-1];
  reg [credit_port_width-1:0] credit_in [0:`NUM_USER_RECV_PORTS-1];


  wire [credit_port_width-1:0] credit_out [0:`NUM_USER_SEND_PORTS-1];
  wire [flit_port_width-1:0] flit_out [0:`NUM_USER_RECV_PORTS-1];

  reg [31:0] cycle;
  integer i;


  reg is_valid;
  reg is_tail;
  reg [dest_bits-1:0] dest;
  reg [vc_bits-1:0]   vc;
  reg [`FLIT_DATA_WIDTH-1:0] data;


  initial Clk = 0;
  always #(HalfClkPeriod) Clk = ~Clk;


  initial begin 
    cycle = 0;
    for(i = 0; i < `NUM_USER_SEND_PORTS; i = i + 1) begin flit_in[i] = 0; send_flit[i] = 0; end
    for(i = 0; i < `NUM_USER_RECV_PORTS; i = i + 1) begin credit_in[i] = 0; send_credit[i] = 0; end
    
    $display("---- Performing Reset ----");
    Rst_n = 0;
    #(5*ClkPeriod+HalfClkPeriod); 
    Rst_n = 1; 
    #(HalfClkPeriod);


    send_flit[0] = 1'b1;
    dest = 1;
    vc = 0;
    data = 'ha;
    flit_in[0] = {1'b1, 1'b0, dest, vc, data};
    $display("@%3d: Injecting flit %x into send port %0d", cycle, flit_in[0], 0);

    #(ClkPeriod);

    send_flit[0] = 1'b1;
    data = 'hb;
    flit_in[0] = {1'b1, 1'b1, dest, vc, data};
    $display("@%3d: Injecting flit %x into send port %0d", cycle, flit_in[0], 0);
    
    #(ClkPeriod);

    send_flit[0] = 1'b0;
    flit_in[0] = 'b0;
  end



  always @ (posedge Clk) begin
    cycle <= cycle + 1;
    for(i = 0; i < `NUM_USER_RECV_PORTS; i = i + 1) begin
      if(flit_out[i][flit_port_width-1]) begin
        $display("@%3d: Ejecting flit %x at receive port %0d", cycle, flit_out[i], i);
      end
    end


    if (cycle > test_cycles) begin
      $finish();
    end
  end




  mkNetwork dut
  (.CLK(Clk)
   ,.RST_N(Rst_n)

   ,.send_ports_0_putFlit_flit_in(flit_in[0])
   ,.EN_send_ports_0_putFlit(send_flit[0])

   ,.EN_send_ports_0_getCredits(1'b1)
   ,.send_ports_0_getCredits(credit_out[0])

   ,.send_ports_1_putFlit_flit_in(flit_in[1])
   ,.EN_send_ports_1_putFlit(send_flit[1])

   ,.EN_send_ports_1_getCredits(1'b1)
   ,.send_ports_1_getCredits(credit_out[1])




   ,.EN_recv_ports_0_getFlit(1'b1)
   ,.recv_ports_0_getFlit(flit_out[0])

   ,.recv_ports_0_putCredits_cr_in(credit_in[0])
   ,.EN_recv_ports_0_putCredits(send_credit[0])

   ,.EN_recv_ports_1_getFlit(1'b1)
   ,.recv_ports_1_getFlit(flit_out[1])

   ,.recv_ports_1_putCredits_cr_in(credit_in[1])
   ,.EN_recv_ports_1_putCredits(send_credit[1])




   );


endmodule
module CONNECT_testbench_sample();

  parameter HalfClkPeriod = 5;
  localparam ClkPeriod = 2*HalfClkPeriod;


  localparam vc_bits = (`NUM_VCS > 1) ? $clog2(`NUM_VCS) : 1;
  localparam dest_bits = $clog2(`NUM_USER_RECV_PORTS);
  localparam flit_port_width = 2+ `FLIT_DATA_WIDTH + dest_bits + vc_bits;
  localparam credit_port_width = 1 + vc_bits;
  localparam test_cycles = 20;

  reg Clk;
  reg Rst_n;


  reg send_flit [0:`NUM_USER_SEND_PORTS-1];
  reg [flit_port_width-1:0] flit_in [0:`NUM_USER_SEND_PORTS-1];

  reg send_credit [0:`NUM_USER_RECV_PORTS-1];
  reg [credit_port_width-1:0] credit_in [0:`NUM_USER_RECV_PORTS-1];


  wire [credit_port_width-1:0] credit_out [0:`NUM_USER_SEND_PORTS-1];
  wire [flit_port_width-1:0] flit_out [0:`NUM_USER_RECV_PORTS-1];

  reg [31:0] cycle;
  integer i;


  reg is_valid;
  reg is_tail;
  reg [dest_bits-1:0] dest;
  reg [vc_bits-1:0]   vc;
  reg [`FLIT_DATA_WIDTH-1:0] data;


  initial Clk = 0;
  always #(HalfClkPeriod) Clk = ~Clk;


  initial begin 
    cycle = 0;
    for(i = 0; i < `NUM_USER_SEND_PORTS; i = i + 1) begin flit_in[i] = 0; send_flit[i] = 0; end
    for(i = 0; i < `NUM_USER_RECV_PORTS; i = i + 1) begin credit_in[i] = 0; send_credit[i] = 0; end
    
    $display("---- Performing Reset ----");
    Rst_n = 0;
    #(5*ClkPeriod+HalfClkPeriod); 
    Rst_n = 1; 
    #(HalfClkPeriod);


    send_flit[0] = 1'b1;
    dest = 1;
    vc = 0;
    data = 'ha;
    flit_in[0] = {1'b1, 1'b0, dest, vc, data};
    $display("@%3d: Injecting flit %x into send port %0d", cycle, flit_in[0], 0);

    #(ClkPeriod);

    send_flit[0] = 1'b1;
    data = 'hb;
    flit_in[0] = {1'b1, 1'b1, dest, vc, data};
    $display("@%3d: Injecting flit %x into send port %0d", cycle, flit_in[0], 0);
    
    #(ClkPeriod);

    send_flit[0] = 1'b0;
    flit_in[0] = 'b0;
  end



  always @ (posedge Clk) begin
    cycle <= cycle + 1;
    for(i = 0; i < `NUM_USER_RECV_PORTS; i = i + 1) begin
      if(flit_out[i][flit_port_width-1]) begin
        $display("@%3d: Ejecting flit %x at receive port %0d", cycle, flit_out[i], i);
      end
    end


    if (cycle > test_cycles) begin
      $finish();
    end
  end




  mkNetwork dut
  (.CLK(Clk)
   ,.RST_N(Rst_n)

   ,.send_ports_0_putFlit_flit_in(flit_in[0])
   ,.EN_send_ports_0_putFlit(send_flit[0])

   ,.EN_send_ports_0_getCredits(1'b1)
   ,.send_ports_0_getCredits(credit_out[0])

   ,.send_ports_1_putFlit_flit_in(flit_in[1])
   ,.EN_send_ports_1_putFlit(send_flit[1])

   ,.EN_send_ports_1_getCredits(1'b1)
   ,.send_ports_1_getCredits(credit_out[1])




   ,.EN_recv_ports_0_getFlit(1'b1)
   ,.recv_ports_0_getFlit(flit_out[0])

   ,.recv_ports_0_putCredits_cr_in(credit_in[0])
   ,.EN_recv_ports_0_putCredits(send_credit[0])

   ,.EN_recv_ports_1_getFlit(1'b1)
   ,.recv_ports_1_getFlit(flit_out[1])

   ,.recv_ports_1_putCredits_cr_in(credit_in[1])
   ,.EN_recv_ports_1_putCredits(send_credit[1])




   );


endmodule