data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/hazard_detection.v
data/verilator_xmls/810d1ae4-1eb6-43ae-9509-4ab08a240616.xml
module hazard_detection(input [4:0] rd,
                        input [4:0] rs1,
                        input [4:0] rs2,
                        input MemRead,
                        output reg PCwrite,
                        output reg IF_IDwrite,
                        output reg control_sel);
    always @(*) begin
        if(MemRead == 1 && ((rd == rs1) || rd == rs2)) begin
            control_sel = 1;
            PCwrite = 0;
            IF_IDwrite = 0;
        end
        else begin
            control_sel = 0;
            PCwrite = 1;
            IF_IDwrite = 1;
        end
    end
endmodule
module hazard_detection(input [4:0] rd,
                        input [4:0] rs1,
                        input [4:0] rs2,
                        input MemRead,
                        output reg PCwrite,
                        output reg IF_IDwrite,
                        output reg control_sel);

    always @(*) begin
        if(MemRead == 1 && ((rd == rs1) || rd == rs2)) begin
            control_sel = 1;
            PCwrite = 0;
            IF_IDwrite = 0;
        end
        else begin
            control_sel = 0;
            PCwrite = 1;
            IF_IDwrite = 1;
        end
    end
endmodule