data/full_repos/permissive/510160664/Adders/src/cla_adder.v
data/verilator_xmls/eae75da4-e3c2-49bf-979b-c4e8078d6508.xml
module cla_submodule
(
			input 	A_i,
			input 	B_i,
			input		C_i,

			output 	S_o,
			output 	C_o
);


wire P_w, G_w;

assign P_w = A_i ^ B_i;
assign G_w = A_i & B_i;


assign S_o = P_w ^ C_i;
assign C_o = G_w | (P_w & C_i);

endmodule
module cla_submodule
(
			input 	A_i,
			input 	B_i,
			input		C_i,

			output 	S_o,
			output 	C_o
);



wire P_w, G_w;

assign P_w = A_i ^ B_i;
assign G_w = A_i & B_i;


assign S_o = P_w ^ C_i;
assign C_o = G_w | (P_w & C_i);

endmodule