data/full_repos/permissive/515598112/3_Circuits/02_Sequential_Logic/01_Latches_and_Flip-Flops/06_DFF_with_byte_enable.v
data/verilator_xmls/34b0de76-4ea6-499b-b07f-9179b472d9d1.xml
module top_module (
    input clk,
    input resetn,
    input [1:0] byteena,
    input [15:0] d,
    output reg [15:0] q
);
    
    always @(posedge clk) begin
        q[15:8] <= resetn ? (byteena[1] ? d[15:8] : q[15:8]) : 8'h00;
        q[7:0] <= resetn ? (byteena[0] ? d[7:0] : q[7:0]) : 8'h00;
    end

endmodule
module top_module (
    input clk,
    input resetn,
    input [1:0] byteena,
    input [15:0] d,
    output reg [15:0] q
);

    
    always @(posedge clk) begin
        q[15:8] <= resetn ? (byteena[1] ? d[15:8] : q[15:8]) : 8'h00;
        q[7:0] <= resetn ? (byteena[0] ? d[7:0] : q[7:0]) : 8'h00;
    end

endmodule