data/full_repos/permissive/464991782/HalfAdder.v
data/verilator_xmls/3af91004-ef2b-43b6-853b-683578cd4aca.xml
module HalfAdder(S, CO, A, B);
input A,B;
output S, CO;

assign S = A ^ B;
assign CO = A & B;
endmodule
module HalfAdder(S, CO, A, B);

input A,B;
output S, CO;

assign S = A ^ B;
assign CO = A & B;
endmodule