data/full_repos/permissive/443770883/lab2/c1testBench.v
1: b'%Error: data/full_repos/permissive/443770883/lab2/c1testBench.v:7: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("dump.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/443770883/lab2/c1testBench.v:8: Unsupported or unknown PLI call: $dumpvars\n$dumpvars(0, TB);\n^~~~~~~~~\n%Error: data/full_repos/permissive/443770883/lab2/c1testBench.v:11: Unsupported or unknown PLI call: $monitor\ninitial begin $monitor(aa,bb,cc,ss,cy);\n              ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/443770883/lab2/c1testBench.v:15: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/443770883/lab2/c1testBench.v:19: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/443770883/lab2/c1testBench.v:23: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Warning-STMTDLY: data/full_repos/permissive/443770883/lab2/c1testBench.v:27: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n%Error: Exiting due to 3 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TB;
reg aa,bb,cc;
wire ss,cy;
fulladd add1(.a(aa), .b(bb), .cin(cc), .sum(ss), .cout(cy));
initial
begin
$dumpfile("dump.vcd");
$dumpvars(0, TB);
end

initial begin $monitor(aa,bb,cc,ss,cy);
aa = 1'b0;
bb = 1'b0;
cc=1'b0;
#5
aa = 1'b0;
bb = 1'b1;
cc=1'b1;
#5
aa = 1'b1;
bb = 1'b0;
cc=1'b0;
#5
aa = 1'b1;
bb = 1'b1;
cc=1'b0;
#5
aa = 1'b0;
bb = 1'b0;
cc=1'b1;
end
endmodule
module TB;

reg aa,bb,cc;
wire ss,cy;
fulladd add1(.a(aa), .b(bb), .cin(cc), .sum(ss), .cout(cy));
initial
begin
$dumpfile("dump.vcd");
$dumpvars(0, TB);
end

initial begin $monitor(aa,bb,cc,ss,cy);
aa = 1'b0;
bb = 1'b0;
cc=1'b0;
#5
aa = 1'b0;
bb = 1'b1;
cc=1'b1;
#5
aa = 1'b1;
bb = 1'b0;
cc=1'b0;
#5
aa = 1'b1;
bb = 1'b1;
cc=1'b0;
#5
aa = 1'b0;
bb = 1'b0;
cc=1'b1;
end
endmodule