data/full_repos/permissive/412289941/change.v
data/verilator_xmls/f2fdd257-36f8-4bfb-8fa8-54281add77b0.xml
module change(rst,data_inP,data_inN,data_out,clk);


input rst,clk,data_inP,data_inN;
output [7:0]data_out;
reg [7:0]data_out;

always@(posedge clk or negedge rst)    begin
    if(!rst)
        data_out <= 8'b10000000;
    else if(data_inP == 1 && data_inN == 0) begin
        data_out <= 8'b11111111;
    end
    else if(data_inP == 0 && data_inN ==1) begin
        data_out <= 8'b00000000;
    end
    else if(data_inP == 0 && data_inN ==0) begin
        data_out <= 8'b10000000;
    end
end

endmodule
module change(rst,data_inP,data_inN,data_out,clk);



input rst,clk,data_inP,data_inN;
output [7:0]data_out;
reg [7:0]data_out;

always@(posedge clk or negedge rst)    begin
    if(!rst)
        data_out <= 8'b10000000;
    else if(data_inP == 1 && data_inN == 0) begin
        data_out <= 8'b11111111;
    end
    else if(data_inP == 0 && data_inN ==1) begin
        data_out <= 8'b00000000;
    end
    else if(data_inP == 0 && data_inN ==0) begin
        data_out <= 8'b10000000;
    end
end

endmodule