data/full_repos/permissive/510695465/ControlUnit.v
data/verilator_xmls/5b35d292-4fbb-445b-861e-c58041163683.xml
module ControlUnit(opcode,ALUctrl,ALUsrc,RegWrite,jump,ImmSel);
input [1:0] opcode;
output reg RegWrite,ALUctrl,ALUsrc,jump,ImmSel;

always @ ( opcode )
begin  
    case (opcode)
    2'b00: {ALUctrl,ALUsrc,RegWrite,jump,ImmSel} = 5'b01100;
    2'b01: {ALUctrl,ALUsrc,RegWrite,jump,ImmSel} = 5'b11100;
    2'b11: {ALUctrl,ALUsrc,RegWrite,jump,ImmSel} = 5'bxx011;
    endcase
end
endmodule
module ControlUnit(opcode,ALUctrl,ALUsrc,RegWrite,jump,ImmSel);

input [1:0] opcode;
output reg RegWrite,ALUctrl,ALUsrc,jump,ImmSel;

always @ ( opcode )
begin  
    case (opcode)
    2'b00: {ALUctrl,ALUsrc,RegWrite,jump,ImmSel} = 5'b01100;
    2'b01: {ALUctrl,ALUsrc,RegWrite,jump,ImmSel} = 5'b11100;
    2'b11: {ALUctrl,ALUsrc,RegWrite,jump,ImmSel} = 5'bxx011;
    endcase
end
endmodule