data/full_repos/permissive/446939020/risc-v/next_pc.v
data/verilator_xmls/0086e36c-1859-4ce4-8e7b-c9b78926310c.xml
module next_pc(output reg [31:0] pc, input [31:0] PCnext ,input clk,reset,StallF);
 
  
  always @(posedge clk) begin
    if(StallF==0) begin
      pc=PCnext;
    end
    if (reset==1) begin
    	pc=0;
    end
  end
  
endmodule
module next_pc(output reg [31:0] pc, input [31:0] PCnext ,input clk,reset,StallF);

 
  
  always @(posedge clk) begin
    if(StallF==0) begin
      pc=PCnext;
    end
    if (reset==1) begin
    	pc=0;
    end
  end
  
endmodule