data/full_repos/permissive/418819021/lab-03/control_unit.v
1: b'%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:5: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418819021/lab-03,data/full_repos/permissive/418819021/defines.vh\n             data/full_repos/permissive/418819021/lab-03,data/full_repos/permissive/418819021/defines.vh.v\n             data/full_repos/permissive/418819021/lab-03,data/full_repos/permissive/418819021/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:20: Define or directive not defined: \'`STAGE_COUNT\'\n        output wire [`STAGE_COUNT-1:0] pipeline_stage,\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:34: Define or directive not defined: \'`OPSEL_COUNT\'\n        output reg  [`OPSEL_COUNT-1:0] alu_opsel,\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:56: Define or directive not defined: \'`SIGNAL_COUNT\'\n    wire [`SIGNAL_COUNT-1:0] signals;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:57: Define or directive not defined: \'`OPCODE_COUNT\'\n    wire [`OPCODE_COUNT-1:0] opcode_type;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:59: Define or directive not defined: \'`GROUP_COUNT\'\n    wire [`GROUP_COUNT-1:0] opcode_group;\n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:150: Define or directive not defined: \'`GROUP_LOAD_INDIRECT\'\n        (opcode_group[`GROUP_LOAD_INDIRECT] ||\n                      ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:150: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n        (opcode_group[`GROUP_LOAD_INDIRECT] ||\n                                          ^\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:151: Define or directive not defined: \'`GROUP_STORE_INDIRECT\'\n         opcode_group[`GROUP_STORE_INDIRECT]) ?\n                      ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:158: Define or directive not defined: \'`CONTROL_MEM_WRITE\'\n        signals[`CONTROL_MEM_WRITE] ?\n                ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:158: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n        signals[`CONTROL_MEM_WRITE] ?\n                                  ^\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:166: Define or directive not defined: \'`STAGE_WB\'\n        end else if (pipeline_stage == `STAGE_WB) begin\n                                       ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:166: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        end else if (pipeline_stage == `STAGE_WB) begin\n                                                ^\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:184: Define or directive not defined: \'`GROUP_ALU\'\n        else if (opcode_group[`GROUP_ALU])\n                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:184: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n        else if (opcode_group[`GROUP_ALU])\n                                        ^\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:186: Define or directive not defined: \'`TYPE_LDI\'\n        else if (opcode_type == `TYPE_LDI)\n                                ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:188: Define or directive not defined: \'`GROUP_LOAD\'\n        else if (opcode_group[`GROUP_LOAD])\n                              ^~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:190: Define or directive not defined: \'`TYPE_MOV\'\n        else if (opcode_type == `TYPE_MOV)\n                                ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:198: Define or directive not defined: \'`STAGE_IF\'\n        else if (pipeline_stage == `STAGE_IF)\n                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:198: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        else if (pipeline_stage == `STAGE_IF)\n                                            ^\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:205: Define or directive not defined: \'`STAGE_EX\'\n        else if (pipeline_stage == `STAGE_EX)\n                                   ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:205: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        else if (pipeline_stage == `STAGE_EX)\n                                            ^\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:213: Define or directive not defined: \'`STAGE_ID\'\n        end else if (pipeline_stage == `STAGE_ID) begin\n                                       ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:213: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        end else if (pipeline_stage == `STAGE_ID) begin\n                                                ^\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:218: Define or directive not defined: \'`STAGE_EX\'\n    assign alu_enable = (pipeline_stage == `STAGE_EX);\n                                           ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:224: Define or directive not defined: \'`OPSEL_COUNT\'\n            alu_opsel = `OPSEL_COUNT\'bx;\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:227: Define or directive not defined: \'`TYPE_ADD\'\n            `TYPE_ADD:\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:227: syntax error, unexpected \':\', expecting endcase\n            `TYPE_ADD:\n                     ^\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:228: Define or directive not defined: \'`OPSEL_ADD\'\n                alu_opsel = `OPSEL_ADD;\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:229: Define or directive not defined: \'`TYPE_ADC\'\n            `TYPE_ADC:\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:230: Define or directive not defined: \'`OPSEL_ADC\'\n                alu_opsel = `OPSEL_ADC;\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:231: Define or directive not defined: \'`TYPE_SUB\'\n            `TYPE_SUB:\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:232: Define or directive not defined: \'`OPSEL_SUB\'\n                alu_opsel = `OPSEL_SUB;\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:233: Define or directive not defined: \'`TYPE_AND\'\n            `TYPE_AND:\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:234: Define or directive not defined: \'`OPSEL_AND\'\n                alu_opsel = `OPSEL_AND;\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:235: Define or directive not defined: \'`TYPE_EOR\'\n            `TYPE_EOR:\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:236: Define or directive not defined: \'`OPSEL_EOR\'\n                alu_opsel = `OPSEL_EOR;\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:237: Define or directive not defined: \'`TYPE_OR\'\n            `TYPE_OR:\n            ^~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:238: Define or directive not defined: \'`OPSEL_OR\'\n                alu_opsel = `OPSEL_OR;\n                            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:239: Define or directive not defined: \'`TYPE_NEG\'\n            `TYPE_NEG:\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:240: Define or directive not defined: \'`OPSEL_NEG\'\n                alu_opsel = `OPSEL_NEG;\n                            ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-03/control_unit.v:242: Define or directive not defined: \'`OPSEL_NONE\'\n                alu_opsel = `OPSEL_NONE;\n                            ^~~~~~~~~~~\n%Error: Cannot continue\n'
module control_unit #(
        parameter  INSTR_WIDTH = 16,
        parameter   DATA_WIDTH = 8,
        parameter I_ADDR_WIDTH = 10,
        parameter   ADDR_WIDTH = 16,
        parameter R_ADDR_WIDTH = 5
    )(
        input  wire                    clk,
        input  wire                    reset,

        output reg  [I_ADDR_WIDTH-1:0] program_counter,
        input  wire [INSTR_WIDTH-1:0]  instruction,


        output wire [`STAGE_COUNT-1:0] pipeline_stage,

        output wire [R_ADDR_WIDTH-1:0] rr_addr,
        output wire [R_ADDR_WIDTH-1:0] rd_addr,
        inout  wire [DATA_WIDTH-1:0]   rr_data,
        inout  wire [DATA_WIDTH-1:0]   rd_data,
        output wire                    rr_cs,
        output wire                    rd_cs,
        output wire                    rr_we,
        output wire                    rd_we,
        output wire                    rr_oe,
        output wire                    rd_oe,

        output wire                    alu_enable,
        output reg  [`OPSEL_COUNT-1:0] alu_opsel,
        output wire [DATA_WIDTH-1:0]   alu_flags_in,
        input  wire [DATA_WIDTH-1:0]   alu_flags_out,
        output reg  [DATA_WIDTH-1:0]   alu_rr,
        output reg  [DATA_WIDTH-1:0]   alu_rd,
        input  wire [DATA_WIDTH-1:0]   alu_out,

        output wire [ADDR_WIDTH-1:0] bus_addr,
        inout  wire [DATA_WIDTH-1:0] bus_data,
        output wire                  mem_cs,
        output wire                  mem_we,
        output wire                  mem_oe
`ifdef DEBUG
        ,
        output wire [`OPCODE_COUNT-1:0] debug_opcode_type,
        output wire [`GROUP_COUNT-1:0]  debug_opcode_group,
        output wire [11:0]              debug_opcode_imd,
        output wire [DATA_WIDTH-1:0]    debug_writeback_value,
        output wire [`SIGNAL_COUNT-1:0] debug_signals
`endif
    );

    wire [`SIGNAL_COUNT-1:0] signals;
    wire [`OPCODE_COUNT-1:0] opcode_type;

    wire [`GROUP_COUNT-1:0] opcode_group;

    wire [R_ADDR_WIDTH-1:0] opcode_rd;
    wire [R_ADDR_WIDTH-1:0] opcode_rr;
    wire [11:0]             opcode_imd;

    wire [2:0]              opcode_bit;


    reg  [INSTR_WIDTH-1:0] instr_buffer;
    reg  [DATA_WIDTH-1:0]  alu_out_buffer;
    reg  [DATA_WIDTH-1:0]  writeback_value;
    wire [ADDR_WIDTH-1:0]  indirect_addr;
    wire [DATA_WIDTH-1:0]  data_to_store;
    reg  [DATA_WIDTH-1:0]  sreg;

`ifdef DEBUG
    assign debug_opcode_type     = opcode_type;
    assign debug_opcode_group    = opcode_group;
    assign debug_opcode_imd      = opcode_imd;
    assign debug_writeback_value = writeback_value;
    assign debug_signals         = signals;
`endif


     state_machine fsm (
        .pipeline_stage(pipeline_stage),
        .clk           (clk),
        .reset         (reset)
    );

    decode_unit #(
        .INSTR_WIDTH(INSTR_WIDTH)
    ) decode (
        .instruction (instr_buffer),
        .opcode_type (opcode_type),
        .opcode_group(opcode_group),
        .opcode_imd  (opcode_imd),
        .opcode_rd   (opcode_rd),
        .opcode_rr   (opcode_rr),
        .opcode_bit  (opcode_bit)
    );

    signal_generation_unit sig (
        .pipeline_stage(pipeline_stage),
        .signals       (signals),
        .opcode_type   (opcode_type),
        .opcode_group  (opcode_group)
    );

    reg_file_interface_unit #(
        .DATA_WIDTH  (DATA_WIDTH),
        .INSTR_WIDTH (INSTR_WIDTH),
        .R_ADDR_WIDTH(R_ADDR_WIDTH)
    ) rf_int (
        .opcode_type    (opcode_type),
        .writeback_value(writeback_value),
        .signals        (signals),
        .rr_addr        (rr_addr),
        .rd_addr        (rd_addr),
        .rr_data        (rr_data),
        .rd_data        (rd_data),
        .rr_cs          (rr_cs),
        .rd_cs          (rd_cs),
        .rr_we          (rr_we),
        .rd_we          (rd_we),
        .rr_oe          (rr_oe),
        .rd_oe          (rd_oe),
        .opcode_rd		(opcode_rd),
        .opcode_rr		(opcode_rr)
    );

    bus_interface_unit #(
        .MEM_START_ADDR(8'h40),
        .MEM_STOP_ADDR (8'hBF),
        .DATA_WIDTH    (DATA_WIDTH),
        .ADDR_WIDTH    (ADDR_WIDTH)
    ) bus_int (
        .opcode_group (opcode_group),
        .opcode_imd   (opcode_imd),
        .signals      (signals),
        .bus_addr     (bus_addr),
        .bus_data     (bus_data),
        .mem_cs       (mem_cs),
        .mem_we       (mem_we),
        .mem_oe       (mem_oe),
        .indirect_addr(indirect_addr),
        .data_to_store(data_to_store)
    );

     assign indirect_addr =
        (opcode_group[`GROUP_LOAD_INDIRECT] ||
         opcode_group[`GROUP_STORE_INDIRECT]) ?

                 {alu_rr, alu_rd} :

                 {ADDR_WIDTH{1'bx}};

    assign data_to_store =
        signals[`CONTROL_MEM_WRITE] ?
            alu_rr :
            {DATA_WIDTH{1'bx}};


    always @(posedge clk, posedge reset) begin
        if (reset) begin
            program_counter <= 0;
        end else if (pipeline_stage == `STAGE_WB) begin
            program_counter <= program_counter + 1;
        end
    end

    assign alu_flags_in = sreg;

    always @(posedge clk, posedge reset)
        if (reset)
            sreg <= 0;
        else sreg <= alu_flags_out;


    always @(posedge clk, posedge reset) begin
        if (reset)
            writeback_value <= {DATA_WIDTH{1'b0}};
        else if (opcode_group[`GROUP_ALU])
            writeback_value <= alu_out_buffer;
        else if (opcode_type == `TYPE_LDI)
            writeback_value <= opcode_imd[7:0];
        else if (opcode_group[`GROUP_LOAD])
            writeback_value <= bus_data;
        else if (opcode_type == `TYPE_MOV)
            writeback_value <= alu_rr;
    end


    always @(posedge clk, posedge reset)
        if (reset)
            instr_buffer <= 0;
        else if (pipeline_stage == `STAGE_IF)
             instr_buffer <= instruction;


    always @(posedge clk, posedge reset)
        if (reset)
            alu_out_buffer <= 0;
        else if (pipeline_stage == `STAGE_EX)
             alu_out_buffer <= alu_out;


    always @(posedge clk, posedge reset)
        if (reset) begin
            alu_rd <= 0;
            alu_rr <= 0;
        end else if (pipeline_stage == `STAGE_ID) begin
            alu_rd <= rd_data;
            alu_rr <= rr_data;
        end

    assign alu_enable = (pipeline_stage == `STAGE_EX);


    always @* begin
        if (alu_enable == 0)
            alu_opsel = `OPSEL_COUNT'bx;
        else begin
            case (opcode_type)
            `TYPE_ADD:
                alu_opsel = `OPSEL_ADD;
            `TYPE_ADC:
                alu_opsel = `OPSEL_ADC;
            `TYPE_SUB:
                alu_opsel = `OPSEL_SUB;
            `TYPE_AND:
                alu_opsel = `OPSEL_AND;
            `TYPE_EOR:
                alu_opsel = `OPSEL_EOR;
            `TYPE_OR:
                alu_opsel = `OPSEL_OR;
            `TYPE_NEG:
                alu_opsel = `OPSEL_NEG;
            default:
                alu_opsel = `OPSEL_NONE;
            endcase
        end
    end

endmodule
module control_unit #(
        parameter  INSTR_WIDTH = 16,
        parameter   DATA_WIDTH = 8,
        parameter I_ADDR_WIDTH = 10,
        parameter   ADDR_WIDTH = 16,
        parameter R_ADDR_WIDTH = 5
    )(
        input  wire                    clk,
        input  wire                    reset,

        output reg  [I_ADDR_WIDTH-1:0] program_counter,
        input  wire [INSTR_WIDTH-1:0]  instruction,


        output wire [`STAGE_COUNT-1:0] pipeline_stage,

        output wire [R_ADDR_WIDTH-1:0] rr_addr,
        output wire [R_ADDR_WIDTH-1:0] rd_addr,
        inout  wire [DATA_WIDTH-1:0]   rr_data,
        inout  wire [DATA_WIDTH-1:0]   rd_data,
        output wire                    rr_cs,
        output wire                    rd_cs,
        output wire                    rr_we,
        output wire                    rd_we,
        output wire                    rr_oe,
        output wire                    rd_oe,

        output wire                    alu_enable,
        output reg  [`OPSEL_COUNT-1:0] alu_opsel,
        output wire [DATA_WIDTH-1:0]   alu_flags_in,
        input  wire [DATA_WIDTH-1:0]   alu_flags_out,
        output reg  [DATA_WIDTH-1:0]   alu_rr,
        output reg  [DATA_WIDTH-1:0]   alu_rd,
        input  wire [DATA_WIDTH-1:0]   alu_out,

        output wire [ADDR_WIDTH-1:0] bus_addr,
        inout  wire [DATA_WIDTH-1:0] bus_data,
        output wire                  mem_cs,
        output wire                  mem_we,
        output wire                  mem_oe
`ifdef DEBUG
        ,
        output wire [`OPCODE_COUNT-1:0] debug_opcode_type,
        output wire [`GROUP_COUNT-1:0]  debug_opcode_group,
        output wire [11:0]              debug_opcode_imd,
        output wire [DATA_WIDTH-1:0]    debug_writeback_value,
        output wire [`SIGNAL_COUNT-1:0] debug_signals
`endif
    );


    wire [`SIGNAL_COUNT-1:0] signals;
    wire [`OPCODE_COUNT-1:0] opcode_type;

    wire [`GROUP_COUNT-1:0] opcode_group;

    wire [R_ADDR_WIDTH-1:0] opcode_rd;
    wire [R_ADDR_WIDTH-1:0] opcode_rr;
    wire [11:0]             opcode_imd;

    wire [2:0]              opcode_bit;


    reg  [INSTR_WIDTH-1:0] instr_buffer;
    reg  [DATA_WIDTH-1:0]  alu_out_buffer;
    reg  [DATA_WIDTH-1:0]  writeback_value;
    wire [ADDR_WIDTH-1:0]  indirect_addr;
    wire [DATA_WIDTH-1:0]  data_to_store;
    reg  [DATA_WIDTH-1:0]  sreg;

`ifdef DEBUG
    assign debug_opcode_type     = opcode_type;
    assign debug_opcode_group    = opcode_group;
    assign debug_opcode_imd      = opcode_imd;
    assign debug_writeback_value = writeback_value;
    assign debug_signals         = signals;
`endif


     state_machine fsm (
        .pipeline_stage(pipeline_stage),
        .clk           (clk),
        .reset         (reset)
    );

    decode_unit #(
        .INSTR_WIDTH(INSTR_WIDTH)
    ) decode (
        .instruction (instr_buffer),
        .opcode_type (opcode_type),
        .opcode_group(opcode_group),
        .opcode_imd  (opcode_imd),
        .opcode_rd   (opcode_rd),
        .opcode_rr   (opcode_rr),
        .opcode_bit  (opcode_bit)
    );

    signal_generation_unit sig (
        .pipeline_stage(pipeline_stage),
        .signals       (signals),
        .opcode_type   (opcode_type),
        .opcode_group  (opcode_group)
    );

    reg_file_interface_unit #(
        .DATA_WIDTH  (DATA_WIDTH),
        .INSTR_WIDTH (INSTR_WIDTH),
        .R_ADDR_WIDTH(R_ADDR_WIDTH)
    ) rf_int (
        .opcode_type    (opcode_type),
        .writeback_value(writeback_value),
        .signals        (signals),
        .rr_addr        (rr_addr),
        .rd_addr        (rd_addr),
        .rr_data        (rr_data),
        .rd_data        (rd_data),
        .rr_cs          (rr_cs),
        .rd_cs          (rd_cs),
        .rr_we          (rr_we),
        .rd_we          (rd_we),
        .rr_oe          (rr_oe),
        .rd_oe          (rd_oe),
        .opcode_rd		(opcode_rd),
        .opcode_rr		(opcode_rr)
    );

    bus_interface_unit #(
        .MEM_START_ADDR(8'h40),
        .MEM_STOP_ADDR (8'hBF),
        .DATA_WIDTH    (DATA_WIDTH),
        .ADDR_WIDTH    (ADDR_WIDTH)
    ) bus_int (
        .opcode_group (opcode_group),
        .opcode_imd   (opcode_imd),
        .signals      (signals),
        .bus_addr     (bus_addr),
        .bus_data     (bus_data),
        .mem_cs       (mem_cs),
        .mem_we       (mem_we),
        .mem_oe       (mem_oe),
        .indirect_addr(indirect_addr),
        .data_to_store(data_to_store)
    );

     assign indirect_addr =
        (opcode_group[`GROUP_LOAD_INDIRECT] ||
         opcode_group[`GROUP_STORE_INDIRECT]) ?

                 {alu_rr, alu_rd} :

                 {ADDR_WIDTH{1'bx}};

    assign data_to_store =
        signals[`CONTROL_MEM_WRITE] ?
            alu_rr :
            {DATA_WIDTH{1'bx}};


    always @(posedge clk, posedge reset) begin
        if (reset) begin
            program_counter <= 0;
        end else if (pipeline_stage == `STAGE_WB) begin
            program_counter <= program_counter + 1;
        end
    end

    assign alu_flags_in = sreg;

    always @(posedge clk, posedge reset)
        if (reset)
            sreg <= 0;
        else sreg <= alu_flags_out;


    always @(posedge clk, posedge reset) begin
        if (reset)
            writeback_value <= {DATA_WIDTH{1'b0}};
        else if (opcode_group[`GROUP_ALU])
            writeback_value <= alu_out_buffer;
        else if (opcode_type == `TYPE_LDI)
            writeback_value <= opcode_imd[7:0];
        else if (opcode_group[`GROUP_LOAD])
            writeback_value <= bus_data;
        else if (opcode_type == `TYPE_MOV)
            writeback_value <= alu_rr;
    end


    always @(posedge clk, posedge reset)
        if (reset)
            instr_buffer <= 0;
        else if (pipeline_stage == `STAGE_IF)
             instr_buffer <= instruction;


    always @(posedge clk, posedge reset)
        if (reset)
            alu_out_buffer <= 0;
        else if (pipeline_stage == `STAGE_EX)
             alu_out_buffer <= alu_out;


    always @(posedge clk, posedge reset)
        if (reset) begin
            alu_rd <= 0;
            alu_rr <= 0;
        end else if (pipeline_stage == `STAGE_ID) begin
            alu_rd <= rd_data;
            alu_rr <= rr_data;
        end

    assign alu_enable = (pipeline_stage == `STAGE_EX);


    always @* begin
        if (alu_enable == 0)
            alu_opsel = `OPSEL_COUNT'bx;
        else begin
            case (opcode_type)
            `TYPE_ADD:
                alu_opsel = `OPSEL_ADD;
            `TYPE_ADC:
                alu_opsel = `OPSEL_ADC;
            `TYPE_SUB:
                alu_opsel = `OPSEL_SUB;
            `TYPE_AND:
                alu_opsel = `OPSEL_AND;
            `TYPE_EOR:
                alu_opsel = `OPSEL_EOR;
            `TYPE_OR:
                alu_opsel = `OPSEL_OR;
            `TYPE_NEG:
                alu_opsel = `OPSEL_NEG;
            default:
                alu_opsel = `OPSEL_NONE;
            endcase
        end
    end

endmodule