data/full_repos/permissive/446997925/hw4/mux_2_to_1_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/446997925/hw4/mux_2_to_1_testbench.v:15: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/446997925/hw4/mux_2_to_1_testbench.v:17: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Error: data/full_repos/permissive/446997925/hw4/mux_2_to_1_testbench.v:22: Unsupported or unknown PLI call: $monitor\n$monitor("time = %2d, a =%32b, b=%32b, sel=%1b, out=%32b", $time, a, b, sel, out);\n^~~~~~~~\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mux_2_to_1_testbench();

reg [31:0] a, b;
reg sel;
wire [31:0] out;

mux_2_to_1_32bit mux_test(a [31:0],b [31:0],sel,out[31:0]);

initial begin
a = 32'b00110000_00000000_00000000_10101010;
b = 32'b00000000_00000000_11111111_11111111;
sel = 1'b0;
#`DELAY;
sel = 1'b1;
#`DELAY;
end

initial
begin
$monitor("time = %2d, a =%32b, b=%32b, sel=%1b, out=%32b", $time, a, b, sel, out);
end


endmodule
module mux_2_to_1_testbench();


reg [31:0] a, b;
reg sel;
wire [31:0] out;

mux_2_to_1_32bit mux_test(a [31:0],b [31:0],sel,out[31:0]);

initial begin
a = 32'b00110000_00000000_00000000_10101010;
b = 32'b00000000_00000000_11111111_11111111;
sel = 1'b0;
#`DELAY;
sel = 1'b1;
#`DELAY;
end

initial
begin
$monitor("time = %2d, a =%32b, b=%32b, sel=%1b, out=%32b", $time, a, b, sel, out);
end


endmodule