data/full_repos/permissive/514992586/2_Circuits/Combinational_Logic/Multiplexers/62_Mux2to1v.v
data/verilator_xmls/1ed2f283-82d0-48a3-af45-ebb40fdf2f3e.xml
module top_module( 
    input [99:0] a, b,
    input sel,
    output [99:0] out );
	
    assign out = sel ? b : a;
endmodule
module top_module( 
    input [99:0] a, b,
    input sel,
    output [99:0] out );

	
    assign out = sel ? b : a;
endmodule