data/full_repos/permissive/43856783/j1_soc/hdl/Ultrasonico/Ultrasonico_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Ultrasonico/Ultrasonico_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n    repeat ( 4 ) #5 clk = ~clk ;\n                 ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Ultrasonico/Ultrasonico_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    forever #5 clk = ~clk ;  \n            ^\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/Ultrasonico/Ultrasonico_tb.v:24: syntax error, unexpected \'@\'\n        @ ( posedge rst_n )\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Ultrasonico/Ultrasonico_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #50_000 ;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Ultrasonico/Ultrasonico_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #100_000 ;\n        ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Ultrasonico_tb ( 
    ) ;

    reg clk , signal , rst_n ;
    wire [15:0] value ;

    ultrasonico dut ( 
        .clk ( clk ) , 
        .signal ( signal ) , 
        .rst_n ( rst_n ) , 
        .value ( value )
        ) ;

    initial begin
    clk = 0 ;
    rst_n = 0 ;
    repeat ( 4 ) #5 clk = ~clk ;
    rst_n = 1 ;
    forever #5 clk = ~clk ;
    end

    initial begin 
        signal = 0 ;
        @ ( posedge rst_n )
	signal = 1 ;
        #50_000 ;

        signal = 0 ; 
        #100_000 ;
        
        $finish ;
    end
endmodule
module Ultrasonico_tb ( 
    ) ;


    reg clk , signal , rst_n ;
    wire [15:0] value ;

    ultrasonico dut ( 
        .clk ( clk ) , 
        .signal ( signal ) , 
        .rst_n ( rst_n ) , 
        .value ( value )
        ) ;

    initial begin
    clk = 0 ;
    rst_n = 0 ;
    repeat ( 4 ) #5 clk = ~clk ;
    rst_n = 1 ;
    forever #5 clk = ~clk ;
    end

    initial begin 
        signal = 0 ;
        @ ( posedge rst_n )
	signal = 1 ;
        #50_000 ;

        signal = 0 ; 
        #100_000 ;
        
        $finish ;
    end
endmodule