data/full_repos/permissive/497604366/cpu/cpu.srcs/sim_1/new/testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/497604366/cpu/cpu.srcs/sim_1/new/testbench.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/497604366/cpu/cpu.srcs/sim_1/new/testbench.v:35: Cannot find file containing module: \'datapath\'\n    datapath datapath(clk,wwreg,wdestReg,wdo,wm2reg,wr);\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/497604366/cpu/cpu.srcs/sim_1/new,data/full_repos/permissive/497604366/datapath\n             data/full_repos/permissive/497604366/cpu/cpu.srcs/sim_1/new,data/full_repos/permissive/497604366/datapath.v\n             data/full_repos/permissive/497604366/cpu/cpu.srcs/sim_1/new,data/full_repos/permissive/497604366/datapath.sv\n             datapath\n             datapath.v\n             datapath.sv\n             obj_dir/datapath\n             obj_dir/datapath.v\n             obj_dir/datapath.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();
    reg clk;
    wire wwreg;
    wire [4:0] wdestReg;
    wire [31:0] wdo;
    wire wm2reg;
    wire [31:0] wr;

    initial begin
    clk = 0;
    end
    
    datapath datapath(clk,wwreg,wdestReg,wdo,wm2reg,wr);

    always begin
        #5;
        clk = ~clk;
    end

endmodule
module testbench();

    reg clk;
    wire wwreg;
    wire [4:0] wdestReg;
    wire [31:0] wdo;
    wire wm2reg;
    wire [31:0] wr;

    initial begin
    clk = 0;
    end
    
    datapath datapath(clk,wwreg,wdestReg,wdo,wm2reg,wr);

    always begin
        #5;
        clk = ~clk;
    end

endmodule