data/full_repos/permissive/452305748/L5/s_counter/s_counter.v
data/verilator_xmls/92f0ddb5-6689-4f14-8547-629d01fdf456.xml
module s_counter (clk,
                  res,
                  s_num);
    
    input clk;
    input res;
    output[3:0] s_num;
    
    parameter frequency_clk = 24 ;
    
    reg[24:0] con_t;
    reg s_pulse;
    reg [3:0] s_num;
    
    always @(posedge clk or negedge res)
    begin
        if (~res)
        begin
            con_t   <= 0;
            s_pulse <= 0;
            s_num   <= 0;
        end
        else
        begin


            if (con_t == frequency_clk - 1)
            begin
                con_t <= 0;

            end
            else
            begin
                con_t <= con_t+1;
            end
            

            if (con_t == 0)
            begin
                s_pulse <= 1;
            end
            else
            begin
                s_pulse <= 0;
            end
            

            if (s_pulse == 1)
            begin
                if (s_num == 9)
                begin
                    s_num <= 0;
                end
                else
                begin
                    s_num <= s_num+1;
                end
            end
        end
    end
endmodule
module s_counter (clk,
                  res,
                  s_num);

    
    input clk;
    input res;
    output[3:0] s_num;
    
    parameter frequency_clk = 24 ;
    
    reg[24:0] con_t;
    reg s_pulse;
    reg [3:0] s_num;
    
    always @(posedge clk or negedge res)
    begin
        if (~res)
        begin
            con_t   <= 0;
            s_pulse <= 0;
            s_num   <= 0;
        end
        else
        begin


            if (con_t == frequency_clk - 1)
            begin
                con_t <= 0;

            end
            else
            begin
                con_t <= con_t+1;
            end
            

            if (con_t == 0)
            begin
                s_pulse <= 1;
            end
            else
            begin
                s_pulse <= 0;
            end
            

            if (s_pulse == 1)
            begin
                if (s_num == 9)
                begin
                    s_num <= 0;
                end
                else
                begin
                    s_num <= s_num+1;
                end
            end
        end
    end
endmodule