data/full_repos/permissive/499137621/CheckPoint4_CPU_Sub-main/processor.v
1: b"%Error: data/full_repos/permissive/499137621/CheckPoint4_CPU_Sub-main/processor.v:162: Cannot find file containing module: 'pc'\n pc my_pc1(.clock(clock), .reset(reset), .en(1'b1), .address_in(pc_in), .address_out(pc_out));\n ^~\n        ... Looked in:\n             data/full_repos/permissive/499137621/CheckPoint4_CPU_Sub-main,data/full_repos/permissive/499137621/pc\n             data/full_repos/permissive/499137621/CheckPoint4_CPU_Sub-main,data/full_repos/permissive/499137621/pc.v\n             data/full_repos/permissive/499137621/CheckPoint4_CPU_Sub-main,data/full_repos/permissive/499137621/pc.sv\n             pc\n             pc.v\n             pc.sv\n             obj_dir/pc\n             obj_dir/pc.v\n             obj_dir/pc.sv\n%Error: data/full_repos/permissive/499137621/CheckPoint4_CPU_Sub-main/processor.v:177: Cannot find file containing module: 'Control_flow'\n Control_flow my_control(.opcode(Opcode), .ALUopcode(ALUop), .Rd(rd), .isOverflow(is_Overflow), \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/499137621/CheckPoint4_CPU_Sub-main/processor.v:185: Cannot find file containing module: 'sign_extension'\n sign_extension my_SE(.immediate(Immediate ), .sx_out(sx_data));\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499137621/CheckPoint4_CPU_Sub-main/processor.v:190: Cannot find file containing module: 'alu'\n alu myALU(.data_operandA(data_readRegA), .data_operandB(real_operandB), .ctrl_ALUopcode(ctrl_ALU_opcode),\n ^~~\n%Error: Exiting due to 4 error(s)\n"
module processor(

    clock,
    reset,


    address_imem,
    q_imem,


    address_dmem,
    data,
    wren,
    q_dmem,


    ctrl_writeEnable,
    ctrl_writeReg,
    ctrl_readRegA,
    ctrl_readRegB,
    data_writeReg,
    data_readRegA,
    data_readRegB
);

    input clock, reset;


    output [11:0] address_imem;
    input [31:0] q_imem;


    output [11:0] address_dmem;
    output [31:0] data;
    output wren;
    input [31:0] q_dmem;


    output ctrl_writeEnable;
    output [4:0] ctrl_writeReg, ctrl_readRegA, ctrl_readRegB;
    output [31:0] data_writeReg;
    input [31:0] data_readRegA, data_readRegB;




	wire [11:0]pc_in;
	wire [11:0]pc_out;
	

	wire [4:0] rd, rs, rt, shamt, Opcode, ALUop;
	reg [4:0]ctrl_rt;
	wire [16:0] Immediate;
	wire[31:0]sx_data;
	

	wire writeEn;
	wire [4: 0]ctrl_ALU_opcode;
	wire is_Overflow;
	wire [4: 0]ctrl_WriteReg;
	wire ctrl_ALUinB;
	wire [31:0]ctrl_exception;

	wire [31:0]alu_result;
	wire [31:0]real_operandB;
	wire alu_isNotEqual;
	wire alu_isLessThan;


	wire [31:0] q_dmem_wire;
	
	wire [11:0] Address_dmem_wire;
	wire [31:0] Data_dmem_wire;
	wire Dwe_wire;
	

	wire Rwd;

	reg [31:0] processor_data_write;


	assign Opcode = q_imem[31:27];
	assign rd = q_imem[26:22];
	assign rs = q_imem[21:17];
	assign rt = q_imem[16:12];
	assign Immediate = q_imem[16:0];
	assign shamt = q_imem[11:7];
	assign ALUop = q_imem[6:2];
	






	always@(*)begin
		if (Opcode == 5'b00111)
			ctrl_rt <= rd;

		else if(Opcode == 5'b00101 ||(Opcode == 5'b00000 &&(ALUop == 5'b00100 
		|| ALUop == 5'b00101))||(Opcode == 5'b01000))
			ctrl_rt <= 5'bz;
		else
			ctrl_rt <= rt;
	end 
	

	assign ctrl_writeEnable = writeEn;
	assign ctrl_readRegA = rs;
	assign ctrl_readRegB = ctrl_rt;
	

	pc my_pc1(.clock(clock), .reset(reset), .en(1'b1), .address_in(pc_in), .address_out(pc_out));
	assign pc_in = pc_out + 12'b1;

	assign address_imem = pc_out;
	

	
	assign Data_dmem_wire = data_readRegB;
	assign data = Data_dmem_wire;
	assign Address_dmem_wire = alu_result[11:0];
	assign address_dmem = Address_dmem_wire;
	assign q_dmem_wire = q_dmem;
	
	

	Control_flow my_control(.opcode(Opcode), .ALUopcode(ALUop), .Rd(rd), .isOverflow(is_Overflow), 
	.Rwe(writeEn), .ctrl_writeReg(ctrl_WriteReg), .ALUinB(ctrl_ALUinB), .preALUopcode(ctrl_ALU_opcode), 
	.exception(ctrl_exception), .Dwe_wire(Dwe_wire), .Rwd(Rwd));
	
	assign wren=Dwe_wire;

	

	sign_extension my_SE(.immediate(Immediate ), .sx_out(sx_data));

	assign real_operandB = ctrl_ALUinB? sx_data: data_readRegB;
	

	alu myALU(.data_operandA(data_readRegA), .data_operandB(real_operandB), .ctrl_ALUopcode(ctrl_ALU_opcode),
			.ctrl_shiftamt(shamt), .data_result(alu_result), .isNotEqual(alu_isNotEqual), .isLessThan(alu_isLessThan)
			, .overflow(is_Overflow));
	


	always@(*)begin

		if (is_Overflow && ((Opcode == 5'b00000 && ALUop == 5'b00000) ||(Opcode == 5'b00000 && ALUop == 5'b00001) 
		|| (Opcode == 5'b00101)))
			processor_data_write <= ctrl_exception;
		else
			processor_data_write <= alu_result;
	end 
	
	

	assign ctrl_writeReg = ctrl_WriteReg;
	assign data_writeReg = Rwd?q_dmem_wire:processor_data_write;
	
endmodule
module processor(

    clock,
    reset,


    address_imem,
    q_imem,


    address_dmem,
    data,
    wren,
    q_dmem,


    ctrl_writeEnable,
    ctrl_writeReg,
    ctrl_readRegA,
    ctrl_readRegB,
    data_writeReg,
    data_readRegA,
    data_readRegB
);


    input clock, reset;


    output [11:0] address_imem;
    input [31:0] q_imem;


    output [11:0] address_dmem;
    output [31:0] data;
    output wren;
    input [31:0] q_dmem;


    output ctrl_writeEnable;
    output [4:0] ctrl_writeReg, ctrl_readRegA, ctrl_readRegB;
    output [31:0] data_writeReg;
    input [31:0] data_readRegA, data_readRegB;




	wire [11:0]pc_in;
	wire [11:0]pc_out;
	

	wire [4:0] rd, rs, rt, shamt, Opcode, ALUop;
	reg [4:0]ctrl_rt;
	wire [16:0] Immediate;
	wire[31:0]sx_data;
	

	wire writeEn;
	wire [4: 0]ctrl_ALU_opcode;
	wire is_Overflow;
	wire [4: 0]ctrl_WriteReg;
	wire ctrl_ALUinB;
	wire [31:0]ctrl_exception;

	wire [31:0]alu_result;
	wire [31:0]real_operandB;
	wire alu_isNotEqual;
	wire alu_isLessThan;


	wire [31:0] q_dmem_wire;
	
	wire [11:0] Address_dmem_wire;
	wire [31:0] Data_dmem_wire;
	wire Dwe_wire;
	

	wire Rwd;

	reg [31:0] processor_data_write;


	assign Opcode = q_imem[31:27];
	assign rd = q_imem[26:22];
	assign rs = q_imem[21:17];
	assign rt = q_imem[16:12];
	assign Immediate = q_imem[16:0];
	assign shamt = q_imem[11:7];
	assign ALUop = q_imem[6:2];
	






	always@(*)begin
		if (Opcode == 5'b00111)
			ctrl_rt <= rd;

		else if(Opcode == 5'b00101 ||(Opcode == 5'b00000 &&(ALUop == 5'b00100 
		|| ALUop == 5'b00101))||(Opcode == 5'b01000))
			ctrl_rt <= 5'bz;
		else
			ctrl_rt <= rt;
	end 
	

	assign ctrl_writeEnable = writeEn;
	assign ctrl_readRegA = rs;
	assign ctrl_readRegB = ctrl_rt;
	

	pc my_pc1(.clock(clock), .reset(reset), .en(1'b1), .address_in(pc_in), .address_out(pc_out));
	assign pc_in = pc_out + 12'b1;

	assign address_imem = pc_out;
	

	
	assign Data_dmem_wire = data_readRegB;
	assign data = Data_dmem_wire;
	assign Address_dmem_wire = alu_result[11:0];
	assign address_dmem = Address_dmem_wire;
	assign q_dmem_wire = q_dmem;
	
	

	Control_flow my_control(.opcode(Opcode), .ALUopcode(ALUop), .Rd(rd), .isOverflow(is_Overflow), 
	.Rwe(writeEn), .ctrl_writeReg(ctrl_WriteReg), .ALUinB(ctrl_ALUinB), .preALUopcode(ctrl_ALU_opcode), 
	.exception(ctrl_exception), .Dwe_wire(Dwe_wire), .Rwd(Rwd));
	
	assign wren=Dwe_wire;

	

	sign_extension my_SE(.immediate(Immediate ), .sx_out(sx_data));

	assign real_operandB = ctrl_ALUinB? sx_data: data_readRegB;
	

	alu myALU(.data_operandA(data_readRegA), .data_operandB(real_operandB), .ctrl_ALUopcode(ctrl_ALU_opcode),
			.ctrl_shiftamt(shamt), .data_result(alu_result), .isNotEqual(alu_isNotEqual), .isLessThan(alu_isLessThan)
			, .overflow(is_Overflow));
	


	always@(*)begin

		if (is_Overflow && ((Opcode == 5'b00000 && ALUop == 5'b00000) ||(Opcode == 5'b00000 && ALUop == 5'b00001) 
		|| (Opcode == 5'b00101)))
			processor_data_write <= ctrl_exception;
		else
			processor_data_write <= alu_result;
	end 
	
	

	assign ctrl_writeReg = ctrl_WriteReg;
	assign data_writeReg = Rwd?q_dmem_wire:processor_data_write;
	
endmodule