data/full_repos/permissive/487039227/src/delayer.v
data/verilator_xmls/a8d84ae7-4091-44ff-b266-0cac783214e8.xml
module delayer
#(parameter WIDTH=16,
  parameter DELAY=10)(
    input clk,
    input rstn,
    input stall,
    input [WIDTH-1:0] in,
    output [WIDTH-1:0] out
);

    integer i = 0;
    integer j = 0;


    reg [WIDTH-1:0] delayReg [DELAY-1:0];

    always@(posedge clk or negedge rstn)begin
        if(!rstn)begin
            for(i=0; i<DELAY; i=i+1)begin
                delayReg[i] <= 'b0;
            end
        end
        else if(!stall)begin
            delayReg[0] <= in;
            for(j=0; j<DELAY; j=j+1)begin
                delayReg[j+1] <= delayReg[j];
            end
        end
    end

    assign out = delayReg[DELAY-1];
endmodule
module delayer
#(parameter WIDTH=16,
  parameter DELAY=10)(
    input clk,
    input rstn,
    input stall,
    input [WIDTH-1:0] in,
    output [WIDTH-1:0] out
);


    integer i = 0;
    integer j = 0;


    reg [WIDTH-1:0] delayReg [DELAY-1:0];

    always@(posedge clk or negedge rstn)begin
        if(!rstn)begin
            for(i=0; i<DELAY; i=i+1)begin
                delayReg[i] <= 'b0;
            end
        end
        else if(!stall)begin
            delayReg[0] <= in;
            for(j=0; j<DELAY; j=j+1)begin
                delayReg[j+1] <= delayReg[j];
            end
        end
    end

    assign out = delayReg[DELAY-1];
endmodule