data/full_repos/permissive/412284801/adders/fullsubtractor/d_fullsub.v
data/verilator_xmls/860434e8-f76d-41cb-a5c6-d73e2b22ecef.xml
module d_fullsub(a,b,bin,bout,d);
    input a,b,bin;
    output bout,d;
    wire w,d1,b1,b2;
    assign d = (a^b)^bin;
    assign bout = ((~a)&bin)|((~a)&b)|(b&bin);
endmodule
module d_fullsub(a,b,bin,bout,d);

    input a,b,bin;
    output bout,d;
    wire w,d1,b1,b2;
    assign d = (a^b)^bin;
    assign bout = ((~a)&bin)|((~a)&b)|(b&bin);
endmodule