data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_ctu_clk_sync_mux.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_ctu_clk_sync_mux.v:238: Cannot find file containing module: 'bw_u1_soffi_4x'\nbw_u1_soffi_4x xf0 (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_soffi_4x\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_soffi_4x.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_soffi_4x.sv\n             bw_u1_soffi_4x\n             bw_u1_soffi_4x.v\n             bw_u1_soffi_4x.sv\n             obj_dir/bw_u1_soffi_4x\n             obj_dir/bw_u1_soffi_4x.v\n             obj_dir/bw_u1_soffi_4x.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_ctu_clk_sync_mux.v:246: Cannot find file containing module: 'bw_u1_soffi_4x'\nbw_u1_soffi_4x xf1 (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_ctu_clk_sync_mux.v:254: Cannot find file containing module: 'bw_u1_muxi21_4x'\nbw_u1_muxi21_4x xmux (\n^~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module bw_ctu_clk_sync_mux(jbus_div0 ,jbus_clk_mux_0 ,tcu_sel_jbus ,
     jbus_div1 ,dram_clk_mux_0 ,dram_div0 ,dram_div1 ,tcu_sel_dram ,
     tcu_sel_cpu ,pll_clk_out ,cmp_div1 ,cmp_div0 ,cmp_clk_mux_0 ,
     cmp_gclk_byp ,dram_gclk_byp ,jbus_gclk_byp ,pll_clk_out_l ,
     cmp_gclk_out ,dram_gclk_out ,jbus_gclk_out ,jbus_gclk_dup_byp ,
     jbus_gclk_dup_out ,jbus_gclk_dupl_mux_0 ,jbus_dup_div0 ,
     jbus_dup_div1 ,tcu_sel_jbus_dup );
input [0:0]	tcu_sel_jbus ;
input [0:0]	tcu_sel_dram ;
input [0:0]	tcu_sel_cpu ;
input [0:0]	tcu_sel_jbus_dup ;
output		cmp_gclk_byp ;
output		dram_gclk_byp ;
output		jbus_gclk_byp ;
output		cmp_gclk_out ;
output		dram_gclk_out ;
output		jbus_gclk_out ;
output		jbus_gclk_dup_byp ;
output		jbus_gclk_dup_out ;
input		jbus_div0 ;
input		jbus_clk_mux_0 ;
input		jbus_div1 ;
input		dram_clk_mux_0 ;
input		dram_div0 ;
input		dram_div1 ;
input		pll_clk_out ;
input		cmp_div1 ;
input		cmp_div0 ;
input		cmp_clk_mux_0 ;
input		pll_clk_out_l ;
input		jbus_gclk_dupl_mux_0 ;
input		jbus_dup_div0 ;
input		jbus_dup_div1 ;
 
 


 
bw_ctu_clk_sync_mux_1path x2 (
     .pll_clk_out_l   (pll_clk_out_l ),
     .muxin0          (jbus_gclk_dupl_mux_0 ),
     .mux_out_l       (jbus_gclk_dup_byp ),
     .in1             (jbus_dup_div1 ),
     .selg            (tcu_sel_jbus_dup[0] ),
     .in0             (jbus_dup_div0 ),
     .pll_clk_out     (pll_clk_out ),
     .clk_out         (jbus_gclk_dup_out ) );
bw_ctu_clk_sync_mux_1path xcsm1 (
     .pll_clk_out_l   (pll_clk_out_l ),
     .muxin0          (cmp_clk_mux_0 ),
     .mux_out_l       (cmp_gclk_byp ),
     .in1             (cmp_div1 ),
     .selg            (tcu_sel_cpu[0] ),
     .in0             (cmp_div0 ),
     .pll_clk_out     (pll_clk_out ),
     .clk_out         (cmp_gclk_out ) );
bw_ctu_clk_sync_mux_1path x0 (
     .pll_clk_out_l   (pll_clk_out_l ),
     .muxin0          (dram_clk_mux_0 ),
     .mux_out_l       (dram_gclk_byp ),
     .in1             (dram_div1 ),
     .selg            (tcu_sel_dram[0] ),
     .in0             (dram_div0 ),
     .pll_clk_out     (pll_clk_out ),
     .clk_out         (dram_gclk_out ) );
bw_ctu_clk_sync_mux_1path x1 (
     .pll_clk_out_l   (pll_clk_out_l ),
     .muxin0          (jbus_clk_mux_0 ),
     .mux_out_l       (jbus_gclk_byp ),
     .in1             (jbus_div1 ),
     .selg            (tcu_sel_jbus[0] ),
     .in0             (jbus_div0 ),
     .pll_clk_out     (pll_clk_out ),
     .clk_out         (jbus_gclk_out ) );


endmodule
module bw_ctu_clk_sync_mux(jbus_div0 ,jbus_clk_mux_0 ,tcu_sel_jbus ,
     jbus_div1 ,dram_clk_mux_0 ,dram_div0 ,dram_div1 ,tcu_sel_dram ,
     tcu_sel_cpu ,pll_clk_out ,cmp_div1 ,cmp_div0 ,cmp_clk_mux_0 ,
     cmp_gclk_byp ,dram_gclk_byp ,jbus_gclk_byp ,pll_clk_out_l ,
     cmp_gclk_out ,dram_gclk_out ,jbus_gclk_out ,jbus_gclk_dup_byp ,
     jbus_gclk_dup_out ,jbus_gclk_dupl_mux_0 ,jbus_dup_div0 ,
     jbus_dup_div1 ,tcu_sel_jbus_dup );

input [0:0]	tcu_sel_jbus ;
input [0:0]	tcu_sel_dram ;
input [0:0]	tcu_sel_cpu ;
input [0:0]	tcu_sel_jbus_dup ;
output		cmp_gclk_byp ;
output		dram_gclk_byp ;
output		jbus_gclk_byp ;
output		cmp_gclk_out ;
output		dram_gclk_out ;
output		jbus_gclk_out ;
output		jbus_gclk_dup_byp ;
output		jbus_gclk_dup_out ;
input		jbus_div0 ;
input		jbus_clk_mux_0 ;
input		jbus_div1 ;
input		dram_clk_mux_0 ;
input		dram_div0 ;
input		dram_div1 ;
input		pll_clk_out ;
input		cmp_div1 ;
input		cmp_div0 ;
input		cmp_clk_mux_0 ;
input		pll_clk_out_l ;
input		jbus_gclk_dupl_mux_0 ;
input		jbus_dup_div0 ;
input		jbus_dup_div1 ;
 
 


 
bw_ctu_clk_sync_mux_1path x2 (
     .pll_clk_out_l   (pll_clk_out_l ),
     .muxin0          (jbus_gclk_dupl_mux_0 ),
     .mux_out_l       (jbus_gclk_dup_byp ),
     .in1             (jbus_dup_div1 ),
     .selg            (tcu_sel_jbus_dup[0] ),
     .in0             (jbus_dup_div0 ),
     .pll_clk_out     (pll_clk_out ),
     .clk_out         (jbus_gclk_dup_out ) );
bw_ctu_clk_sync_mux_1path xcsm1 (
     .pll_clk_out_l   (pll_clk_out_l ),
     .muxin0          (cmp_clk_mux_0 ),
     .mux_out_l       (cmp_gclk_byp ),
     .in1             (cmp_div1 ),
     .selg            (tcu_sel_cpu[0] ),
     .in0             (cmp_div0 ),
     .pll_clk_out     (pll_clk_out ),
     .clk_out         (cmp_gclk_out ) );
bw_ctu_clk_sync_mux_1path x0 (
     .pll_clk_out_l   (pll_clk_out_l ),
     .muxin0          (dram_clk_mux_0 ),
     .mux_out_l       (dram_gclk_byp ),
     .in1             (dram_div1 ),
     .selg            (tcu_sel_dram[0] ),
     .in0             (dram_div0 ),
     .pll_clk_out     (pll_clk_out ),
     .clk_out         (dram_gclk_out ) );
bw_ctu_clk_sync_mux_1path x1 (
     .pll_clk_out_l   (pll_clk_out_l ),
     .muxin0          (jbus_clk_mux_0 ),
     .mux_out_l       (jbus_gclk_byp ),
     .in1             (jbus_div1 ),
     .selg            (tcu_sel_jbus[0] ),
     .in0             (jbus_div0 ),
     .pll_clk_out     (pll_clk_out ),
     .clk_out         (jbus_gclk_out ) );


endmodule