data/full_repos/permissive/441359809/src/yosys/examples/intel/asicworld_lfsr/lfsr_updown.v
1: b'%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/examples/intel/asicworld_lfsr/lfsr_updown.v:26: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 7 bits.\n                                                                                                             : ... In instance lfsr_updown\n    count <= {7{1\'b0}};\n          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/examples/intel/asicworld_lfsr/lfsr_updown.v:31: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 7 bits.\n                                                                                                             : ... In instance lfsr_updown\n      count <= {count[5:0],~(^(count &  8\'b10110001))};\n            ^~\n%Error: Exiting due to 2 warning(s)\n'
module lfsr_updown (
clk       ,
reset     ,
enable    ,
up_down   ,
count     ,
overflow
);

 input clk;
 input reset;
 input enable; 
 input up_down;

 output [7 : 0] count;
 output overflow;

 reg [7 : 0] count;

 assign overflow = (up_down) ? (count == {{7{1'b0}}, 1'b1}) : 
                               (count == {1'b1, {7{1'b0}}}) ;

 always @(posedge clk)
 if (reset) 
    count <= {7{1'b0}};
 else if (enable) begin
    if (up_down) begin
      count <= {~(^(count & 8'b01100011)),count[7:1]};
    end else begin
      count <= {count[5:0],~(^(count &  8'b10110001))};
    end
 end

endmodule
module lfsr_updown (
clk       ,
reset     ,
enable    ,
up_down   ,
count     ,
overflow
);


 input clk;
 input reset;
 input enable; 
 input up_down;

 output [7 : 0] count;
 output overflow;

 reg [7 : 0] count;

 assign overflow = (up_down) ? (count == {{7{1'b0}}, 1'b1}) : 
                               (count == {1'b1, {7{1'b0}}}) ;

 always @(posedge clk)
 if (reset) 
    count <= {7{1'b0}};
 else if (enable) begin
    if (up_down) begin
      count <= {~(^(count & 8'b01100011)),count[7:1]};
    end else begin
      count <= {count[5:0],~(^(count &  8'b10110001))};
    end
 end

endmodule