data/full_repos/permissive/51896788/ip/rcn/rtl/rcn_fifo.v
1: b'%Warning-WIDTH: data/full_repos/permissive/51896788/ip/rcn/rtl/rcn_fifo.v:57: Bit extraction of array[3:0] requires 2 bit index, not 5 bits.\n                                                                            : ... In instance rcn_fifo\n            fifo[head] <= rcn_in[67:0];\n                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/51896788/ip/rcn/rtl/rcn_fifo.v:62: Bit extraction of array[3:0] requires 2 bit index, not 5 bits.\n                                                                            : ... In instance rcn_fifo\n    assign rcn_out = {!fifo_empty, fifo[tail]};\n                                       ^\n%Error: Exiting due to 2 warning(s)\n'
module rcn_fifo
(
    input rst,
    input clk,

    input [68:0] rcn_in,
    input push,
    output full,

    output [68:0] rcn_out,
    input pop,
    output empty
);
    parameter DEPTH = 4;

    reg [4:0] head;
    reg [4:0] tail;
    reg [5:0] cnt;

    wire fifo_full = (cnt == DEPTH);
    wire fifo_empty = (cnt == 0);

    always @ (posedge clk or posedge rst)
        if (rst)
        begin
            head <= 5'd0;
            tail <= 5'd0;
            cnt <= 6'd0;
        end
        else
        begin
            if (push)
                head <= (head == (DEPTH - 1)) ? 5'd0 : head + 5'd1;

            if (pop)
                tail <= (tail == (DEPTH - 1)) ? 5'd0 : tail + 5'd1;

            case ({push, pop})
            2'b10: cnt <= cnt + 6'd1;
            2'b01: cnt <= cnt - 6'd1;
            default: ;
            endcase
        end

    reg [67:0] fifo[(DEPTH - 1):0];

    always @ (posedge clk)
        if (push)
            fifo[head] <= rcn_in[67:0];

    assign full = fifo_full;
    assign empty = fifo_empty;

    assign rcn_out = {!fifo_empty, fifo[tail]};

endmodule
module rcn_fifo
(
    input rst,
    input clk,

    input [68:0] rcn_in,
    input push,
    output full,

    output [68:0] rcn_out,
    input pop,
    output empty
);

    parameter DEPTH = 4;

    reg [4:0] head;
    reg [4:0] tail;
    reg [5:0] cnt;

    wire fifo_full = (cnt == DEPTH);
    wire fifo_empty = (cnt == 0);

    always @ (posedge clk or posedge rst)
        if (rst)
        begin
            head <= 5'd0;
            tail <= 5'd0;
            cnt <= 6'd0;
        end
        else
        begin
            if (push)
                head <= (head == (DEPTH - 1)) ? 5'd0 : head + 5'd1;

            if (pop)
                tail <= (tail == (DEPTH - 1)) ? 5'd0 : tail + 5'd1;

            case ({push, pop})
            2'b10: cnt <= cnt + 6'd1;
            2'b01: cnt <= cnt - 6'd1;
            default: ;
            endcase
        end

    reg [67:0] fifo[(DEPTH - 1):0];

    always @ (posedge clk)
        if (push)
            fifo[head] <= rcn_in[67:0];

    assign full = fifo_full;
    assign empty = fifo_empty;

    assign rcn_out = {!fifo_empty, fifo[tail]};

endmodule