data/full_repos/permissive/515545375/new/RTL/Top_UART_Rx.v
1: b"%Error: data/full_repos/permissive/515545375/new/RTL/Top_UART_Rx.v:44: Cannot find file containing module: 'UART_TX'\nUART_TX Transmitter(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/515545375/new/RTL,data/full_repos/permissive/515545375/UART_TX\n             data/full_repos/permissive/515545375/new/RTL,data/full_repos/permissive/515545375/UART_TX.v\n             data/full_repos/permissive/515545375/new/RTL,data/full_repos/permissive/515545375/UART_TX.sv\n             UART_TX\n             UART_TX.v\n             UART_TX.sv\n             obj_dir/UART_TX\n             obj_dir/UART_TX.v\n             obj_dir/UART_TX.sv\n%Error: Exiting due to 1 error(s)\n"
module Top_UART_Rx(
input i_clk ,
input i_Rx_serial ,
output o_RX_DV ,
output [`DATA_WIDTH-1:0] o_RX,
input i_TX_valid ,
input [`DATA_WIDTH-1:0] data_TX ,
output o_TX_Serial ,
output o_TX_active ,
output o_TX
);

UART_TX Transmitter(
.i_clk(i_clk) ,
.i_TX_valid(i_TX_valid) ,
.i_TX_DATA(data_TX) ,
.o_TX_Serial(o_TX_Serial) ,
.o_TX_active(o_TX_active) ,
.o_TX(o_TX)
);


parameter IDLE = 3'b000;
parameter RX_START_BIT = 3'b001;
parameter RX_DATA_BITS = 3'b010;
parameter RX_STOP_BIT = 3'b011;
parameter CLEAN_BITS = 3'b100;


reg[`WIDTH_CLK_CNT-1:0] clk_count = 0 ;
reg[`CNT_BYTE-1:0] rx_cnt = 0;
reg[`DATA_WIDTH-1:0] rx_BYTE = 0 ;
reg [`STATE_WIDTH-1:0] p_STATE = 0;
reg o_RX_byte = 0;




always @(posedge i_clk)
begin
case (p_STATE)
IDLE :
begin
rx_cnt <= 0;
o_RX_byte <= 0;
clk_count <= 0;
if (i_Rx_serial==1'b0)
p_STATE <= RX_START_BIT ;
else
p_STATE <= IDLE ;
end



RX_START_BIT :
begin
if (clk_count == (`CLK_PER_BIT-1)/2)
begin
if (i_Rx_serial == 1'b0)
begin
p_STATE <= RX_DATA_BITS ;
clk_count <= 0;
end
else
p_STATE <= IDLE ;
end

else
begin
clk_count <= clk_count + 1;
p_STATE <= RX_START_BIT;
end
end



RX_DATA_BITS :
begin
if (clk_count < `CLK_PER_BIT-1)
begin
clk_count <= clk_count + 1;
p_STATE <= RX_DATA_BITS;
end
else
begin
clk_count <= 0;
rx_BYTE [rx_cnt] <= i_Rx_serial ;

if (rx_cnt<7)
begin
rx_cnt <= rx_cnt + 1 ;
p_STATE <= RX_DATA_BITS ;
end
else
begin
rx_cnt <= 0;
p_STATE <= RX_STOP_BIT;
end
end
end


RX_STOP_BIT :
begin
if (clk_count < `CLK_PER_BIT-1)
begin
clk_count <= clk_count + 1;
p_STATE <= RX_STOP_BIT ;
end
else
begin
o_RX_byte <= 1'b1 ;
clk_count <= 0;
p_STATE <= CLEAN_BITS ;
end
end

CLEAN_BITS : begin
p_STATE <= IDLE ;
o_RX_byte <= 1'b0;
end
default: p_STATE <= IDLE ;
endcase
end


assign o_RX = rx_BYTE ;
assign o_RX_DV = o_RX_byte ;

endmodule
module Top_UART_Rx(
input i_clk ,
input i_Rx_serial ,
output o_RX_DV ,
output [`DATA_WIDTH-1:0] o_RX,
input i_TX_valid ,
input [`DATA_WIDTH-1:0] data_TX ,
output o_TX_Serial ,
output o_TX_active ,
output o_TX
);


UART_TX Transmitter(
.i_clk(i_clk) ,
.i_TX_valid(i_TX_valid) ,
.i_TX_DATA(data_TX) ,
.o_TX_Serial(o_TX_Serial) ,
.o_TX_active(o_TX_active) ,
.o_TX(o_TX)
);


parameter IDLE = 3'b000;
parameter RX_START_BIT = 3'b001;
parameter RX_DATA_BITS = 3'b010;
parameter RX_STOP_BIT = 3'b011;
parameter CLEAN_BITS = 3'b100;


reg[`WIDTH_CLK_CNT-1:0] clk_count = 0 ;
reg[`CNT_BYTE-1:0] rx_cnt = 0;
reg[`DATA_WIDTH-1:0] rx_BYTE = 0 ;
reg [`STATE_WIDTH-1:0] p_STATE = 0;
reg o_RX_byte = 0;




always @(posedge i_clk)
begin
case (p_STATE)
IDLE :
begin
rx_cnt <= 0;
o_RX_byte <= 0;
clk_count <= 0;
if (i_Rx_serial==1'b0)
p_STATE <= RX_START_BIT ;
else
p_STATE <= IDLE ;
end



RX_START_BIT :
begin
if (clk_count == (`CLK_PER_BIT-1)/2)
begin
if (i_Rx_serial == 1'b0)
begin
p_STATE <= RX_DATA_BITS ;
clk_count <= 0;
end
else
p_STATE <= IDLE ;
end

else
begin
clk_count <= clk_count + 1;
p_STATE <= RX_START_BIT;
end
end



RX_DATA_BITS :
begin
if (clk_count < `CLK_PER_BIT-1)
begin
clk_count <= clk_count + 1;
p_STATE <= RX_DATA_BITS;
end
else
begin
clk_count <= 0;
rx_BYTE [rx_cnt] <= i_Rx_serial ;

if (rx_cnt<7)
begin
rx_cnt <= rx_cnt + 1 ;
p_STATE <= RX_DATA_BITS ;
end
else
begin
rx_cnt <= 0;
p_STATE <= RX_STOP_BIT;
end
end
end


RX_STOP_BIT :
begin
if (clk_count < `CLK_PER_BIT-1)
begin
clk_count <= clk_count + 1;
p_STATE <= RX_STOP_BIT ;
end
else
begin
o_RX_byte <= 1'b1 ;
clk_count <= 0;
p_STATE <= CLEAN_BITS ;
end
end

CLEAN_BITS : begin
p_STATE <= IDLE ;
o_RX_byte <= 1'b0;
end
default: p_STATE <= IDLE ;
endcase
end


assign o_RX = rx_BYTE ;
assign o_RX_DV = o_RX_byte ;

endmodule