data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:187: Multiple top level modules\n                                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                    : ... Top module \'CPU\'\nmodule CPU(\n       ^~~\n                                                                                    : ... Top module \'toRAMCollect\'\nmodule toRAMCollect(\n       ^~~~~~~~~~~~\n                                                                                    : ... Top module \'toMem\'\nmodule toMem(\n       ^~~~~\n%Error: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:104: Cannot find file containing module: \'core\'\ncore QDP(.clk(clk),\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/521337848/Hardware/procesor,data/full_repos/permissive/521337848/core\n             data/full_repos/permissive/521337848/Hardware/procesor,data/full_repos/permissive/521337848/core.v\n             data/full_repos/permissive/521337848/Hardware/procesor,data/full_repos/permissive/521337848/core.sv\n             core\n             core.v\n             core.sv\n             obj_dir/core\n             obj_dir/core.v\n             obj_dir/core.sv\n%Error: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:147: Cannot find file containing module: \'memCont\'\nmemCont mCa(\n^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:235: Operator OR expects 2 bits on the LHS, but LHS\'s SEL generates 1 bits.\n                                                                                 : ... In instance toMem\n status = addrMemory[12] | addrMemory[11];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:235: Operator OR expects 2 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                 : ... In instance toMem\n status = addrMemory[12] | addrMemory[11];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:243: Operator AND expects 2 bits on the LHS, but LHS\'s VARREF \'startRead\' generates 1 bits.\n                                                                                 : ... In instance toMem\n startReadRAM <= startRead & status;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:243: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s AND generates 2 bits.\n                                                                                 : ... In instance toMem\n startReadRAM <= startRead & status;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:244: Operator AND expects 2 bits on the LHS, but LHS\'s VARREF \'startRead\' generates 1 bits.\n                                                                                 : ... In instance toMem\n startReadROM <= startRead & (~status);\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:244: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s AND generates 2 bits.\n                                                                                 : ... In instance toMem\n startReadROM <= startRead & (~status);\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:249: Operator ASSIGNDLY expects 15 bits on the Assign RHS, but Assign RHS\'s SEL generates 11 bits.\n                                                                                 : ... In instance toMem\n if(status == 0) addrROM <= addrMemory[10:0];\n                         ^~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:257: Operator ASSIGNDLY expects 15 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 12 bits.\n                                                                                 : ... In instance toMem\n  if(addrMemory[12:11] == 2\'b10) addrRAM8 <= {1\'b1,addrMemory[10:0]};\n                                          ^~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/procesor/CPU2.v:258: Operator ASSIGNDLY expects 15 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                                 : ... In instance toMem\n  else addrRAM8 <= {addrMemory[10:0]};\n                ^~\n%Error: Exiting due to 2 error(s), 10 warning(s)\n'
module toRAMCollect(
	input[31:0] toCPURAM8,
	
	input[31:0] toCPUROM,
	input selector,
	
	output[31:0] toCPU
);

assign toCPU = selector ? toCPURAM8 : toCPUROM;
endmodule
module toRAMCollect(
	input[31:0] toCPURAM8,
	
	input[31:0] toCPUROM,
	input selector,
	
	output[31:0] toCPU
);


assign toCPU = selector ? toCPURAM8 : toCPUROM;
endmodule