data/full_repos/permissive/441359809/src/yosys/manual/PRESENTATION_ExAdv/macc_simple_xmap.v
data/verilator_xmls/302efa16-9105-43f7-8c76-69f62256b499.xml
module macc_16_16_32(a, b, c, y);
input [15:0] a, b;
input [31:0] c;
output [31:0] y;
assign y = a*b + c;
endmodule
module macc_16_16_32(a, b, c, y);

input [15:0] a, b;
input [31:0] c;
output [31:0] y;
assign y = a*b + c;
endmodule