data/full_repos/permissive/476477303/verilog/rtl/Art/Art_top.v
data/verilator_xmls/75c0cc18-470f-4b54-b509-b2a76aa14883.xml
module Art (
`ifdef USE_POWER_PINS
		inout vccd1,
		inout vssd1
`endif

	);
	
endmodule
module Art (
`ifdef USE_POWER_PINS
		inout vccd1,
		inout vssd1
`endif

	);

	
endmodule