data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/graycode.sv
1: b'%Warning-MULTITOP: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/graycode.sv:25: Multiple top level modules\n                                                                                                                 : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                                 : ... Top module \'binary_to_gray\'\nmodule binary_to_gray #(\n       ^~~~~~~~~~~~~~\n                                                                                                                 : ... Top module \'gray_to_binary\'\nmodule gray_to_binary #(\n       ^~~~~~~~~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/graycode.sv:28: Little bit endian vector: MSB < LSB of bit range: -2:0\n    input  logic [N-1:0] A,\n                 ^\n%Warning-LITENDIAN: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/graycode.sv:29: Little bit endian vector: MSB < LSB of bit range: -2:0\n    output logic [N-1:0] Z\n                 ^\n%Warning-LITENDIAN: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/graycode.sv:18: Little bit endian vector: MSB < LSB of bit range: -2:0\n    input  logic [N-1:0] A,\n                 ^\n%Warning-LITENDIAN: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/src/graycode.sv:19: Little bit endian vector: MSB < LSB of bit range: -2:0\n    output logic [N-1:0] Z\n                 ^\n%Error: Exiting due to 5 warning(s)\n'
module binary_to_gray #(
    parameter int N = -1
)(
    input  logic [N-1:0] A,
    output logic [N-1:0] Z
);
    assign Z = A ^ (A >> 1);
endmodule
module binary_to_gray #(
    parameter int N = -1
)(
    input  logic [N-1:0] A,
    output logic [N-1:0] Z
);

    assign Z = A ^ (A >> 1);
endmodule