data/full_repos/permissive/436037353/src/ALU.v
data/verilator_xmls/dab9eb57-d420-4478-8944-6b1c9638660d.xml
module ALU(
	clock,
	readData1,
	ALUInput2,
	ALUOP,
	inPort,
	ALUResult,
	zero,
	negative,
	outPort);
	
	input clock;
	input [7:0]	readData1;
	input [7:0] ALUInput2;
	input [3:0] ALUOP;
	input [7:0]	inPort;
	
	output reg [7:0]	ALUResult;
	output reg 			zero;
	output reg			negative;
	output reg [7:0]	outPort;
	
	
	always@(*) begin
	
		case(ALUOP)
	
			4'b0000:
				begin

				end
			
			4'b0001:
				begin
				
					ALUResult = readData1 + ALUInput2;
				
				end
			
			4'b0010:
				begin
				
					ALUResult = readData1 - ALUInput2;
				
				end
			
			4'b0011:
				begin
				
					ALUResult = ~(readData1 & ALUInput2);
					
				
				end
			
			4'b0100:
				begin
				
					ALUResult = readData1 << 1;

				end
			
			4'b0101:
				begin
			
					ALUResult = readData1 >> 1;
					
				end
			
			4'b0111:
				begin
			
					ALUResult = inPort;
				
				end
			
			4'b1000:
				begin
			
					ALUResult = ALUInput2;
			
				end
			
			
			4'b1001:
				begin
					

					
				end
			
			4'b1010:
				begin
					

					
				end
			
			4'b1011:
				begin
					

					
				end
			
			4'b1100:
				begin
					

					
				end
			
			4'b1101:
				begin
			
					ALUResult = ALUInput2;
			
				end
			
			4'b1110:
				begin
			
					ALUResult = ALUInput2;
			
				end
			
			4'b1111:
				begin
			
					ALUResult = ALUInput2;
			
				end
	
		endcase
	end
	
	always@(posedge clock) begin
	
		case(ALUOP)
		
			4'b0110:
			begin
		
				outPort = readData1;
			
			end
			4'b0001:
				begin
				
					zero = (ALUResult == 0);
				
					negative = ALUResult[7];
				
				end
			
			4'b0010:
				begin
				
					zero = (ALUResult == 0);
				
					negative = ALUResult[7];
				
				end
			
			4'b0011:
				begin
				
					zero = (ALUResult == 0);
				
					negative = ALUResult[7];
						
				end
			
			4'b0100:
				begin
				
					zero = readData1[7];

				end
			
			4'b0101:
				begin
			
					zero = readData1[0];
					
				end
			
		endcase
		
	end

endmodule
module ALU(
	clock,
	readData1,
	ALUInput2,
	ALUOP,
	inPort,
	ALUResult,
	zero,
	negative,
	outPort);

	
	input clock;
	input [7:0]	readData1;
	input [7:0] ALUInput2;
	input [3:0] ALUOP;
	input [7:0]	inPort;
	
	output reg [7:0]	ALUResult;
	output reg 			zero;
	output reg			negative;
	output reg [7:0]	outPort;
	
	
	always@(*) begin
	
		case(ALUOP)
	
			4'b0000:
				begin

				end
			
			4'b0001:
				begin
				
					ALUResult = readData1 + ALUInput2;
				
				end
			
			4'b0010:
				begin
				
					ALUResult = readData1 - ALUInput2;
				
				end
			
			4'b0011:
				begin
				
					ALUResult = ~(readData1 & ALUInput2);
					
				
				end
			
			4'b0100:
				begin
				
					ALUResult = readData1 << 1;

				end
			
			4'b0101:
				begin
			
					ALUResult = readData1 >> 1;
					
				end
			
			4'b0111:
				begin
			
					ALUResult = inPort;
				
				end
			
			4'b1000:
				begin
			
					ALUResult = ALUInput2;
			
				end
			
			
			4'b1001:
				begin
					

					
				end
			
			4'b1010:
				begin
					

					
				end
			
			4'b1011:
				begin
					

					
				end
			
			4'b1100:
				begin
					

					
				end
			
			4'b1101:
				begin
			
					ALUResult = ALUInput2;
			
				end
			
			4'b1110:
				begin
			
					ALUResult = ALUInput2;
			
				end
			
			4'b1111:
				begin
			
					ALUResult = ALUInput2;
			
				end
	
		endcase
	end
	
	always@(posedge clock) begin
	
		case(ALUOP)
		
			4'b0110:
			begin
		
				outPort = readData1;
			
			end
			4'b0001:
				begin
				
					zero = (ALUResult == 0);
				
					negative = ALUResult[7];
				
				end
			
			4'b0010:
				begin
				
					zero = (ALUResult == 0);
				
					negative = ALUResult[7];
				
				end
			
			4'b0011:
				begin
				
					zero = (ALUResult == 0);
				
					negative = ALUResult[7];
						
				end
			
			4'b0100:
				begin
				
					zero = readData1[7];

				end
			
			4'b0101:
				begin
			
					zero = readData1[0];
					
				end
			
		endcase
		
	end

endmodule