data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_tidbits_reg_combo_example.v
data/verilator_xmls/20dfd592-0750-4dc2-8f3e-aca35da4dad9.xml
module reg_combo_example( a, b, y);
input a, b;
output y;

reg   y;
wire a, b;

always @ ( a or b)
begin	
  y = a & b;
end

endmodule
module reg_combo_example( a, b, y);

input a, b;
output y;

reg   y;
wire a, b;

always @ ( a or b)
begin	
  y = a & b;
end

endmodule