data/full_repos/permissive/493019833/test/testcase/firrtl/RouterUnitTester/sbt/RouterUnitTester.v
data/verilator_xmls/35375d76-eb02-426c-89cf-ead9fb3ebb2d.xml
module Router(
  input         clock,
  input         reset,
  output        io_read_routing_table_request_ready,
  input         io_read_routing_table_request_valid,
  input  [31:0] io_read_routing_table_request_bits_addr,
  input         io_read_routing_table_response_ready,
  output        io_read_routing_table_response_valid,
  output [31:0] io_read_routing_table_response_bits,
  output        io_load_routing_table_request_ready,
  input         io_load_routing_table_request_valid,
  input  [31:0] io_load_routing_table_request_bits_addr,
  input  [31:0] io_load_routing_table_request_bits_data,
  output        io_in_ready,
  input         io_in_valid,
  input  [7:0]  io_in_bits_header,
  input  [63:0] io_in_bits_body,
  input         io_outs_0_ready,
  output        io_outs_0_valid,
  output [63:0] io_outs_0_bits_body,
  input         io_outs_1_ready,
  output        io_outs_1_valid,
  output [63:0] io_outs_1_bits_body,
  input         io_outs_2_ready,
  output        io_outs_2_valid,
  output [63:0] io_outs_2_bits_body,
  input         io_outs_3_ready,
  output        io_outs_3_valid,
  output [63:0] io_outs_3_bits_body
);
`ifdef RANDOMIZE_GARBAGE_ASSIGN
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
`endif
  reg [2:0] tbl [0:14];
  wire  tbl__T_74_en;
  wire [3:0] tbl__T_74_addr;
  wire [2:0] tbl__T_74_data;
  wire  tbl__T_92_en;
  wire [3:0] tbl__T_92_addr;
  wire [2:0] tbl__T_92_data;
  wire  tbl__T_104_en;
  wire [3:0] tbl__T_104_addr;
  wire [2:0] tbl__T_104_data;
  wire [2:0] tbl__T_81_data;
  wire [3:0] tbl__T_81_addr;
  wire  tbl__T_81_mask;
  wire  tbl__T_81_en;
  wire  _T_77 = ~(io_read_routing_table_request_valid & io_read_routing_table_response_ready);
  wire  _T_78 = _T_77 & io_load_routing_table_request_valid;
  wire  _T_83 = ~reset;
  wire  _T_88 = _T_77 & ~io_load_routing_table_request_valid;
  wire  _T_89 = _T_88 & io_in_valid;
  wire  _GEN_22 = 2'h1 == tbl__T_92_data[1:0] ? io_outs_1_ready : io_outs_0_ready;
  wire  _GEN_23 = 2'h2 == tbl__T_92_data[1:0] ? io_outs_2_ready : _GEN_22;
  wire  _GEN_24 = 2'h3 == tbl__T_92_data[1:0] ? io_outs_3_ready : _GEN_23;
  wire  _GEN_25 = 2'h0 == tbl__T_92_data[1:0];
  wire  _GEN_26 = 2'h1 == tbl__T_92_data[1:0];
  wire  _GEN_27 = 2'h2 == tbl__T_92_data[1:0];
  wire  _GEN_28 = 2'h3 == tbl__T_92_data[1:0];
  wire [63:0] _GEN_29 = 2'h0 == tbl__T_92_data[1:0] ? io_in_bits_body : 64'h0;
  wire [63:0] _GEN_30 = 2'h1 == tbl__T_92_data[1:0] ? io_in_bits_body : 64'h0;
  wire [63:0] _GEN_31 = 2'h2 == tbl__T_92_data[1:0] ? io_in_bits_body : 64'h0;
  wire [63:0] _GEN_32 = 2'h3 == tbl__T_92_data[1:0] ? io_in_bits_body : 64'h0;
  wire  _GEN_38 = _GEN_24 & _GEN_25;
  wire  _GEN_39 = _GEN_24 & _GEN_26;
  wire  _GEN_40 = _GEN_24 & _GEN_27;
  wire  _GEN_41 = _GEN_24 & _GEN_28;
  wire [63:0] _GEN_42 = _GEN_24 ? _GEN_29 : 64'h0;
  wire [63:0] _GEN_43 = _GEN_24 ? _GEN_30 : 64'h0;
  wire [63:0] _GEN_44 = _GEN_24 ? _GEN_31 : 64'h0;
  wire [63:0] _GEN_45 = _GEN_24 ? _GEN_32 : 64'h0;
  wire  _GEN_56 = _T_88 & io_in_valid & _GEN_24;
  assign tbl__T_74_en = io_read_routing_table_request_valid & io_read_routing_table_response_ready;
  assign tbl__T_74_addr = io_read_routing_table_request_bits_addr[3:0];
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign tbl__T_74_data = tbl[tbl__T_74_addr];
  `else
  assign tbl__T_74_data = tbl__T_74_addr >= 4'hf ? _RAND_1[2:0] : tbl[tbl__T_74_addr];
  `endif
  assign tbl__T_92_en = _T_88 & io_in_valid;
  assign tbl__T_92_addr = io_in_bits_header[3:0];
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign tbl__T_92_data = tbl[tbl__T_92_addr];
  `else
  assign tbl__T_92_data = tbl__T_92_addr >= 4'hf ? _RAND_2[2:0] : tbl[tbl__T_92_addr];
  `endif
  assign tbl__T_104_en = _T_89 & _GEN_24;
  assign tbl__T_104_addr = io_in_bits_header[3:0];
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign tbl__T_104_data = tbl[tbl__T_104_addr];
  `else
  assign tbl__T_104_data = tbl__T_104_addr >= 4'hf ? _RAND_3[2:0] : tbl[tbl__T_104_addr];
  `endif
  assign tbl__T_81_data = io_load_routing_table_request_bits_data[2:0];
  assign tbl__T_81_addr = io_load_routing_table_request_bits_addr[3:0];
  assign tbl__T_81_mask = 1'h1;
  assign tbl__T_81_en = _T_77 & io_load_routing_table_request_valid;
  assign io_read_routing_table_request_ready = io_read_routing_table_request_valid &
    io_read_routing_table_response_ready;
  assign io_read_routing_table_response_valid = io_read_routing_table_request_valid &
    io_read_routing_table_response_ready;
  assign io_read_routing_table_response_bits = io_read_routing_table_request_valid &
    io_read_routing_table_response_ready ? {{29'd0}, tbl__T_74_data} : 32'h0;
  assign io_load_routing_table_request_ready = _T_77 & io_load_routing_table_request_valid;
  assign io_in_ready = _T_88 & io_in_valid & _GEN_24;
  assign io_outs_0_valid = _T_88 & io_in_valid & _GEN_38;
  assign io_outs_0_bits_body = _T_88 & io_in_valid ? _GEN_42 : 64'h0;
  assign io_outs_1_valid = _T_88 & io_in_valid & _GEN_39;
  assign io_outs_1_bits_body = _T_88 & io_in_valid ? _GEN_43 : 64'h0;
  assign io_outs_2_valid = _T_88 & io_in_valid & _GEN_40;
  assign io_outs_2_bits_body = _T_88 & io_in_valid ? _GEN_44 : 64'h0;
  assign io_outs_3_valid = _T_88 & io_in_valid & _GEN_41;
  assign io_outs_3_bits_body = _T_88 & io_in_valid ? _GEN_45 : 64'h0;
  always @(posedge clock) begin
    if (tbl__T_81_en & tbl__T_81_mask) begin
      tbl[tbl__T_81_addr] <= tbl__T_81_data;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_78 & ~reset) begin
          $fwrite(32'h80000002,"setting tbl(%d) to %d\n",io_load_routing_table_request_bits_addr,
            io_load_routing_table_request_bits_data);
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_56 & _T_83) begin
          $fwrite(32'h80000002,"got packet to route header %d, data %d, being routed to out(%d)\n",io_in_bits_header,
            io_in_bits_body,tbl__T_104_data);
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_GARBAGE_ASSIGN
  _RAND_1 = {1{`RANDOM}};
  _RAND_2 = {1{`RANDOM}};
  _RAND_3 = {1{`RANDOM}};
`endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 15; initvar = initvar+1)
    tbl[initvar] = _RAND_0[2:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module Router(
  input         clock,
  input         reset,
  output        io_read_routing_table_request_ready,
  input         io_read_routing_table_request_valid,
  input  [31:0] io_read_routing_table_request_bits_addr,
  input         io_read_routing_table_response_ready,
  output        io_read_routing_table_response_valid,
  output [31:0] io_read_routing_table_response_bits,
  output        io_load_routing_table_request_ready,
  input         io_load_routing_table_request_valid,
  input  [31:0] io_load_routing_table_request_bits_addr,
  input  [31:0] io_load_routing_table_request_bits_data,
  output        io_in_ready,
  input         io_in_valid,
  input  [7:0]  io_in_bits_header,
  input  [63:0] io_in_bits_body,
  input         io_outs_0_ready,
  output        io_outs_0_valid,
  output [63:0] io_outs_0_bits_body,
  input         io_outs_1_ready,
  output        io_outs_1_valid,
  output [63:0] io_outs_1_bits_body,
  input         io_outs_2_ready,
  output        io_outs_2_valid,
  output [63:0] io_outs_2_bits_body,
  input         io_outs_3_ready,
  output        io_outs_3_valid,
  output [63:0] io_outs_3_bits_body
);

`ifdef RANDOMIZE_GARBAGE_ASSIGN
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
`endif
  reg [2:0] tbl [0:14];
  wire  tbl__T_74_en;
  wire [3:0] tbl__T_74_addr;
  wire [2:0] tbl__T_74_data;
  wire  tbl__T_92_en;
  wire [3:0] tbl__T_92_addr;
  wire [2:0] tbl__T_92_data;
  wire  tbl__T_104_en;
  wire [3:0] tbl__T_104_addr;
  wire [2:0] tbl__T_104_data;
  wire [2:0] tbl__T_81_data;
  wire [3:0] tbl__T_81_addr;
  wire  tbl__T_81_mask;
  wire  tbl__T_81_en;
  wire  _T_77 = ~(io_read_routing_table_request_valid & io_read_routing_table_response_ready);
  wire  _T_78 = _T_77 & io_load_routing_table_request_valid;
  wire  _T_83 = ~reset;
  wire  _T_88 = _T_77 & ~io_load_routing_table_request_valid;
  wire  _T_89 = _T_88 & io_in_valid;
  wire  _GEN_22 = 2'h1 == tbl__T_92_data[1:0] ? io_outs_1_ready : io_outs_0_ready;
  wire  _GEN_23 = 2'h2 == tbl__T_92_data[1:0] ? io_outs_2_ready : _GEN_22;
  wire  _GEN_24 = 2'h3 == tbl__T_92_data[1:0] ? io_outs_3_ready : _GEN_23;
  wire  _GEN_25 = 2'h0 == tbl__T_92_data[1:0];
  wire  _GEN_26 = 2'h1 == tbl__T_92_data[1:0];
  wire  _GEN_27 = 2'h2 == tbl__T_92_data[1:0];
  wire  _GEN_28 = 2'h3 == tbl__T_92_data[1:0];
  wire [63:0] _GEN_29 = 2'h0 == tbl__T_92_data[1:0] ? io_in_bits_body : 64'h0;
  wire [63:0] _GEN_30 = 2'h1 == tbl__T_92_data[1:0] ? io_in_bits_body : 64'h0;
  wire [63:0] _GEN_31 = 2'h2 == tbl__T_92_data[1:0] ? io_in_bits_body : 64'h0;
  wire [63:0] _GEN_32 = 2'h3 == tbl__T_92_data[1:0] ? io_in_bits_body : 64'h0;
  wire  _GEN_38 = _GEN_24 & _GEN_25;
  wire  _GEN_39 = _GEN_24 & _GEN_26;
  wire  _GEN_40 = _GEN_24 & _GEN_27;
  wire  _GEN_41 = _GEN_24 & _GEN_28;
  wire [63:0] _GEN_42 = _GEN_24 ? _GEN_29 : 64'h0;
  wire [63:0] _GEN_43 = _GEN_24 ? _GEN_30 : 64'h0;
  wire [63:0] _GEN_44 = _GEN_24 ? _GEN_31 : 64'h0;
  wire [63:0] _GEN_45 = _GEN_24 ? _GEN_32 : 64'h0;
  wire  _GEN_56 = _T_88 & io_in_valid & _GEN_24;
  assign tbl__T_74_en = io_read_routing_table_request_valid & io_read_routing_table_response_ready;
  assign tbl__T_74_addr = io_read_routing_table_request_bits_addr[3:0];
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign tbl__T_74_data = tbl[tbl__T_74_addr];
  `else
  assign tbl__T_74_data = tbl__T_74_addr >= 4'hf ? _RAND_1[2:0] : tbl[tbl__T_74_addr];
  `endif
  assign tbl__T_92_en = _T_88 & io_in_valid;
  assign tbl__T_92_addr = io_in_bits_header[3:0];
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign tbl__T_92_data = tbl[tbl__T_92_addr];
  `else
  assign tbl__T_92_data = tbl__T_92_addr >= 4'hf ? _RAND_2[2:0] : tbl[tbl__T_92_addr];
  `endif
  assign tbl__T_104_en = _T_89 & _GEN_24;
  assign tbl__T_104_addr = io_in_bits_header[3:0];
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign tbl__T_104_data = tbl[tbl__T_104_addr];
  `else
  assign tbl__T_104_data = tbl__T_104_addr >= 4'hf ? _RAND_3[2:0] : tbl[tbl__T_104_addr];
  `endif
  assign tbl__T_81_data = io_load_routing_table_request_bits_data[2:0];
  assign tbl__T_81_addr = io_load_routing_table_request_bits_addr[3:0];
  assign tbl__T_81_mask = 1'h1;
  assign tbl__T_81_en = _T_77 & io_load_routing_table_request_valid;
  assign io_read_routing_table_request_ready = io_read_routing_table_request_valid &
    io_read_routing_table_response_ready;
  assign io_read_routing_table_response_valid = io_read_routing_table_request_valid &
    io_read_routing_table_response_ready;
  assign io_read_routing_table_response_bits = io_read_routing_table_request_valid &
    io_read_routing_table_response_ready ? {{29'd0}, tbl__T_74_data} : 32'h0;
  assign io_load_routing_table_request_ready = _T_77 & io_load_routing_table_request_valid;
  assign io_in_ready = _T_88 & io_in_valid & _GEN_24;
  assign io_outs_0_valid = _T_88 & io_in_valid & _GEN_38;
  assign io_outs_0_bits_body = _T_88 & io_in_valid ? _GEN_42 : 64'h0;
  assign io_outs_1_valid = _T_88 & io_in_valid & _GEN_39;
  assign io_outs_1_bits_body = _T_88 & io_in_valid ? _GEN_43 : 64'h0;
  assign io_outs_2_valid = _T_88 & io_in_valid & _GEN_40;
  assign io_outs_2_bits_body = _T_88 & io_in_valid ? _GEN_44 : 64'h0;
  assign io_outs_3_valid = _T_88 & io_in_valid & _GEN_41;
  assign io_outs_3_bits_body = _T_88 & io_in_valid ? _GEN_45 : 64'h0;
  always @(posedge clock) begin
    if (tbl__T_81_en & tbl__T_81_mask) begin
      tbl[tbl__T_81_addr] <= tbl__T_81_data;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_78 & ~reset) begin
          $fwrite(32'h80000002,"setting tbl(%d) to %d\n",io_load_routing_table_request_bits_addr,
            io_load_routing_table_request_bits_data);
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_56 & _T_83) begin
          $fwrite(32'h80000002,"got packet to route header %d, data %d, being routed to out(%d)\n",io_in_bits_header,
            io_in_bits_body,tbl__T_104_data);
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_GARBAGE_ASSIGN
  _RAND_1 = {1{`RANDOM}};
  _RAND_2 = {1{`RANDOM}};
  _RAND_3 = {1{`RANDOM}};
`endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 15; initvar = initvar+1)
    tbl[initvar] = _RAND_0[2:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule