data/full_repos/permissive/458737381/src/verilog-parser/tests/udp_body_tb.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/udp_body_tb.v:1: Cannot find include file: udp_body.v\n`include "udp_body.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/udp_body.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/udp_body.v.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/udp_body.v.sv\n             udp_body.v\n             udp_body.v.v\n             udp_body.v.sv\n             obj_dir/udp_body.v\n             obj_dir/udp_body.v.v\n             obj_dir/udp_body.v.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/udp_body_tb.v:10: Unsupported or unknown PLI call: $monitor\n  $monitor(" B = %b C = %b  A = %b",b,c,a);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/udp_body_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n  #1 b = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/udp_body_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #1 b = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/udp_body_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #1 c = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/udp_body_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #1 b = 1\'bx;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/udp_body_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #1 c = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/udp_body_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #1 b = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/udp_body_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #1 c = 1\'bx;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/udp_body_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #1 b = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/udp_body_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #1 $finish;\n  ^\n%Error: Exiting due to 2 error(s), 9 warning(s)\n'
module udp_body_tb();

reg b,c;
wire a;

udp_body udp (a,b,c);

initial begin
  $monitor(" B = %b C = %b  A = %b",b,c,a);
  b = 0;
  c = 0;
  #1 b = 1;
  #1 b = 0;
  #1 c = 1;
  #1 b = 1'bx;
  #1 c = 0;
  #1 b = 1;
  #1 c = 1'bx;
  #1 b = 0;
  #1 $finish;
end  

endmodule
module udp_body_tb();


reg b,c;
wire a;

udp_body udp (a,b,c);

initial begin
  $monitor(" B = %b C = %b  A = %b",b,c,a);
  b = 0;
  c = 0;
  #1 b = 1;
  #1 b = 0;
  #1 c = 1;
  #1 b = 1'bx;
  #1 c = 0;
  #1 b = 1;
  #1 c = 1'bx;
  #1 b = 0;
  #1 $finish;
end  

endmodule