data/full_repos/permissive/524713879/verilog/dv/wb_port/clk_gate.v
1: b'%Error: data/full_repos/permissive/524713879/verilog/dv/wb_port/clk_gate.v:28: Cannot find include file: sp_verilog.vh\n`include "sp_verilog.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/524713879/verilog/dv/wb_port,data/full_repos/permissive/524713879/sp_verilog.vh\n             data/full_repos/permissive/524713879/verilog/dv/wb_port,data/full_repos/permissive/524713879/sp_verilog.vh.v\n             data/full_repos/permissive/524713879/verilog/dv/wb_port,data/full_repos/permissive/524713879/sp_verilog.vh.sv\n             sp_verilog.vh\n             sp_verilog.vh.v\n             sp_verilog.vh.sv\n             obj_dir/sp_verilog.vh\n             obj_dir/sp_verilog.vh.v\n             obj_dir/sp_verilog.vh.sv\n%Error: data/full_repos/permissive/524713879/verilog/dv/wb_port/clk_gate.v:37: Define or directive not defined: \'`TLV_BLATCH\'\n   `TLV_BLATCH(latched_clk_en, clk_en, free_clk)\n   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/524713879/verilog/dv/wb_port/clk_gate.v:37: syntax error, unexpected \'(\'\n   `TLV_BLATCH(latched_clk_en, clk_en, free_clk)\n               ^~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module clk_gate (output gated_clk, input free_clk, func_en, pwr_en, gating_override);
   wire clk_en;
   reg latched_clk_en;
   assign clk_en = func_en & (pwr_en | gating_override);
   `TLV_BLATCH(latched_clk_en, clk_en, free_clk)
   assign gated_clk = latched_clk_en & free_clk;
endmodule
module clk_gate (output gated_clk, input free_clk, func_en, pwr_en, gating_override);

   wire clk_en;
   reg latched_clk_en;
   assign clk_en = func_en & (pwr_en | gating_override);
   `TLV_BLATCH(latched_clk_en, clk_en, free_clk)
   assign gated_clk = latched_clk_en & free_clk;
endmodule