data/full_repos/permissive/531279620/resource/src/enc_4b5b.v
data/verilator_xmls/6fea75f0-417c-4384-8f7f-c1a21c21263a.xml
module enc_4b5b(
	
	input	[3 : 0]		din,
	input				ext_sel,
	output	[4 : 0]		dout
);
	
	reg		[4 : 0]		lut_4b5b	[0 : 21];
	
	initial begin
		lut_4b5b[0]  <= 5'b11110;
		lut_4b5b[1]  <= 5'b01001;
		lut_4b5b[2]  <= 5'b10100;
		lut_4b5b[3]  <= 5'b10101;
		lut_4b5b[4]  <= 5'b01010;
		lut_4b5b[5]  <= 5'b01011;
		lut_4b5b[6]  <= 5'b01110;
		lut_4b5b[7]  <= 5'b01111;
		lut_4b5b[8]  <= 5'b10010;
		lut_4b5b[9]  <= 5'b10011;
		lut_4b5b[10] <= 5'b10110;
		lut_4b5b[11] <= 5'b10111;
		lut_4b5b[12] <= 5'b11010;
		lut_4b5b[13] <= 5'b11011;
		lut_4b5b[14] <= 5'b11100;
		lut_4b5b[15] <= 5'b11101;

		lut_4b5b[16] <= 5'b11000;
		lut_4b5b[17] <= 5'b10001;
		lut_4b5b[18] <= 5'b00111;
		lut_4b5b[19] <= 5'b11001;
		lut_4b5b[20] <= 5'b01101;
		lut_4b5b[21] <= 5'b00110;
	end
	
	assign dout = lut_4b5b[{ext_sel, din}];
	
endmodule
module enc_4b5b(
	
	input	[3 : 0]		din,
	input				ext_sel,
	output	[4 : 0]		dout
);

	
	reg		[4 : 0]		lut_4b5b	[0 : 21];
	
	initial begin
		lut_4b5b[0]  <= 5'b11110;
		lut_4b5b[1]  <= 5'b01001;
		lut_4b5b[2]  <= 5'b10100;
		lut_4b5b[3]  <= 5'b10101;
		lut_4b5b[4]  <= 5'b01010;
		lut_4b5b[5]  <= 5'b01011;
		lut_4b5b[6]  <= 5'b01110;
		lut_4b5b[7]  <= 5'b01111;
		lut_4b5b[8]  <= 5'b10010;
		lut_4b5b[9]  <= 5'b10011;
		lut_4b5b[10] <= 5'b10110;
		lut_4b5b[11] <= 5'b10111;
		lut_4b5b[12] <= 5'b11010;
		lut_4b5b[13] <= 5'b11011;
		lut_4b5b[14] <= 5'b11100;
		lut_4b5b[15] <= 5'b11101;

		lut_4b5b[16] <= 5'b11000;
		lut_4b5b[17] <= 5'b10001;
		lut_4b5b[18] <= 5'b00111;
		lut_4b5b[19] <= 5'b11001;
		lut_4b5b[20] <= 5'b01101;
		lut_4b5b[21] <= 5'b00110;
	end
	
	assign dout = lut_4b5b[{ext_sel, din}];
	
endmodule