data/full_repos/permissive/425855877/mux_2_to_1.v
data/verilator_xmls/53e32760-8d16-46a1-923c-2779c65b104d.xml
module mux_2_to_1 (SW, LEDR);
  
input [9:0]SW;
output[9:0]LEDR;

wire S;
	wire [2:0] X, Y, M;
  
assign S = SW[9];
assign X = SW[2:0];   	
assign Y = SW[5:3];  
  
assign LEDR[8:6] = M;
assign LEDR[9] = SW[9];  
assign LEDR[2:0] = SW[2:0];
assign LEDR[5:3] = SW[5:3];

assign M = (S == 0) ? X : Y;
  
endmodule
module mux_2_to_1 (SW, LEDR);

  
input [9:0]SW;
output[9:0]LEDR;

wire S;
	wire [2:0] X, Y, M;
  
assign S = SW[9];
assign X = SW[2:0];   	
assign Y = SW[5:3];  
  
assign LEDR[8:6] = M;
assign LEDR[9] = SW[9];  
assign LEDR[2:0] = SW[2:0];
assign LEDR[5:3] = SW[5:3];

assign M = (S == 0) ? X : Y;
  
endmodule