data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/ADC/offset_ADC_to_AXIS.v
1: b'%Warning-WIDTH: data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/ADC/offset_ADC_to_AXIS.v:22: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 20 bits.\n                                                                                                           : ... In instance offset_ADC_to_AXIS\n wire zero_pad = {PAD_WIDTH{1\'b0}};\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/ADC/offset_ADC_to_AXIS.v:28: Cannot find file containing module: \'twos_to_ADC_offset\'\n twos_to_ADC_offset #(.DATA_WIDTH(12)) twos_0(.data_in(offset_adc_a), .data_out(off_a_out));\n ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/ADC,data/full_repos/permissive/503053625/twos_to_ADC_offset\n             data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/ADC,data/full_repos/permissive/503053625/twos_to_ADC_offset.v\n             data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/ADC,data/full_repos/permissive/503053625/twos_to_ADC_offset.sv\n             twos_to_ADC_offset\n             twos_to_ADC_offset.v\n             twos_to_ADC_offset.sv\n             obj_dir/twos_to_ADC_offset\n             obj_dir/twos_to_ADC_offset.v\n             obj_dir/twos_to_ADC_offset.sv\n%Error: data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/ADC/offset_ADC_to_AXIS.v:29: Cannot find file containing module: \'twos_to_ADC_offset\'\n twos_to_ADC_offset #(.DATA_WIDTH(12)) twos_1(.data_in(offset_adc_b), .data_out(off_b_out));\n ^~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/ADC/offset_ADC_to_AXIS.v:34: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 13 bits.\n                                                                                                           : ... In instance offset_ADC_to_AXIS\n assign m_axis_a_tdata = {zero_pad, off_a_out};\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/ADC/offset_ADC_to_AXIS.v:35: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 13 bits.\n                                                                                                           : ... In instance offset_ADC_to_AXIS\n assign m_axis_b_tdata = {zero_pad, off_b_out};\n                       ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module offset_ADC_to_AXIS
#(
	parameter ADC_WIDTH = 12,
	parameter AXIS_TDATA_WIDTH = 32
)
(
	(* X_INTERFACE_PARAMETER = "FREQ_HZ 250000000" *)
	input [ADC_WIDTH - 1:0] offset_adc_a,
	input [ADC_WIDTH - 1:0] offset_adc_b,
	output m_axis_a_tvalid,
	output [AXIS_TDATA_WIDTH - 1:0] m_axis_a_tdata,
	output m_axis_b_tvalid,
	output [AXIS_TDATA_WIDTH - 1:0] m_axis_b_tdata
);
	localparam PAD_WIDTH = AXIS_TDATA_WIDTH - ADC_WIDTH;
	wire zero_pad = {PAD_WIDTH{1'b0}};


	wire [ADC_WIDTH - 1:0] off_a_out;
	wire [ADC_WIDTH - 1:0] off_b_out;

	twos_to_ADC_offset #(.DATA_WIDTH(12)) twos_0(.data_in(offset_adc_a), .data_out(off_a_out));
	twos_to_ADC_offset #(.DATA_WIDTH(12)) twos_1(.data_in(offset_adc_b), .data_out(off_b_out));

	assign m_axis_a_tvalid = 1'b1;
	assign m_axis_b_tvalid = 1'b1;

	assign m_axis_a_tdata = {zero_pad, off_a_out};
	assign m_axis_b_tdata = {zero_pad, off_b_out};
endmodule
module offset_ADC_to_AXIS
#(
	parameter ADC_WIDTH = 12,
	parameter AXIS_TDATA_WIDTH = 32
)
(
	(* X_INTERFACE_PARAMETER = "FREQ_HZ 250000000" *)
	input [ADC_WIDTH - 1:0] offset_adc_a,
	input [ADC_WIDTH - 1:0] offset_adc_b,
	output m_axis_a_tvalid,
	output [AXIS_TDATA_WIDTH - 1:0] m_axis_a_tdata,
	output m_axis_b_tvalid,
	output [AXIS_TDATA_WIDTH - 1:0] m_axis_b_tdata
);

	localparam PAD_WIDTH = AXIS_TDATA_WIDTH - ADC_WIDTH;
	wire zero_pad = {PAD_WIDTH{1'b0}};


	wire [ADC_WIDTH - 1:0] off_a_out;
	wire [ADC_WIDTH - 1:0] off_b_out;

	twos_to_ADC_offset #(.DATA_WIDTH(12)) twos_0(.data_in(offset_adc_a), .data_out(off_a_out));
	twos_to_ADC_offset #(.DATA_WIDTH(12)) twos_1(.data_in(offset_adc_b), .data_out(off_b_out));

	assign m_axis_a_tvalid = 1'b1;
	assign m_axis_b_tvalid = 1'b1;

	assign m_axis_a_tdata = {zero_pad, off_a_out};
	assign m_axis_b_tdata = {zero_pad, off_b_out};
endmodule