data/full_repos/permissive/473363095/square_root.v
1: b'%Warning-WIDTH: data/full_repos/permissive/473363095/square_root.v:33: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'in\' generates 8 bits.\n                                                                     : ... In instance square_root\n  in_aux = in << 16; \n              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module square_root(
	output [15:0] out,
   input [7:0] in
   );
	
	reg [31:0] in_aux;
	reg [15:0] base;
	reg [15:0] result;
	
	always@(*) begin


		in_aux = in << 16; 
		base = 1 << 15;
		result = 0;
		repeat(16) begin 
			result = result + base;
			if(result * result > in_aux) begin
				result = result - base;
			end
			base = base >> 1;
		end
	end
	

	assign out = result;

endmodule
module square_root(
	output [15:0] out,
   input [7:0] in
   );

	
	reg [31:0] in_aux;
	reg [15:0] base;
	reg [15:0] result;
	
	always@(*) begin


		in_aux = in << 16; 
		base = 1 << 15;
		result = 0;
		repeat(16) begin 
			result = result + base;
			if(result * result > in_aux) begin
				result = result - base;
			end
			base = base >> 1;
		end
	end
	

	assign out = result;

endmodule