data/full_repos/permissive/489642764/src/wb_ctrl/wb_ctrl.v
data/verilator_xmls/d81146d8-0c44-41d5-aa47-fc2049552096.xml
function [31:0] data_f;
		input [3:0]  curr_inst_type_arg;
		input [31:0] curr_data_arg;
		input [31:0] curr_inst_value_arg;
		input [31:0] wb_dat_i_arg;
		input        wb_ack_i_arg;
		input        start_curr_inst_arg;
		case (curr_inst_type_arg)
			INST_READ : begin
				if (wb_ack_i_arg) begin
					data_f = wb_dat_i_arg;
				end else begin
					data_f = curr_data_arg;
				end
			end
			INST_WRITE_IMD : begin
				if (start_curr_inst_arg) begin
					data_f = curr_inst_value_arg;
				end else begin
					data_f = curr_data_arg;
				end
			end
			default : begin
				data_f = curr_data_arg;
			end
		endcase
	endfunction
function [31:0] data_f;

		input [3:0]  curr_inst_type_arg;
		input [31:0] curr_data_arg;
		input [31:0] curr_inst_value_arg;
		input [31:0] wb_dat_i_arg;
		input        wb_ack_i_arg;
		input        start_curr_inst_arg;
		case (curr_inst_type_arg)
			INST_READ : begin
				if (wb_ack_i_arg) begin
					data_f = wb_dat_i_arg;
				end else begin
					data_f = curr_data_arg;
				end
			end
			INST_WRITE_IMD : begin
				if (start_curr_inst_arg) begin
					data_f = curr_inst_value_arg;
				end else begin
					data_f = curr_data_arg;
				end
			end
			default : begin
				data_f = curr_data_arg;
			end
		endcase
	endfunction