data/full_repos/permissive/423958267/lab04_2/lab04_2.srcs/sim_1/new/test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/423958267/lab04_2/lab04_2.srcs/sim_1/new/test.v:35: Unsupported: Ignoring delay on this delayed statement.\n    always #10 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab04_2/lab04_2.srcs/sim_1/new/test.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #5 addr <= 4\'d15;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab04_2/lab04_2.srcs/sim_1/new/test.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #100 $finish;\n        ^\n%Error: data/full_repos/permissive/423958267/lab04_2/lab04_2.srcs/sim_1/new/test.v:26: Cannot find file containing module: \'ROM\'\n    ROM r(out,addr,clk);\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/423958267/lab04_2/lab04_2.srcs/sim_1/new,data/full_repos/permissive/423958267/ROM\n             data/full_repos/permissive/423958267/lab04_2/lab04_2.srcs/sim_1/new,data/full_repos/permissive/423958267/ROM.v\n             data/full_repos/permissive/423958267/lab04_2/lab04_2.srcs/sim_1/new,data/full_repos/permissive/423958267/ROM.sv\n             ROM\n             ROM.v\n             ROM.sv\n             obj_dir/ROM\n             obj_dir/ROM.v\n             obj_dir/ROM.sv\n%Warning-WIDTH: data/full_repos/permissive/423958267/lab04_2/lab04_2.srcs/sim_1/new/test.v:39: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'hf\' generates 4 bits.\n                                                                                             : ... In instance test\n        #5 addr <= 4\'d15;\n                ^~\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test(

);
    ROM r(out,addr,clk);
    wire [7:0] out;
    reg [4:0] addr;
    reg clk;
    initial
    begin
        clk <= 0;
        addr <= 0;
    end
    always #10 clk = ~clk;

    initial
    begin
        #5 addr <= 4'd15;
        #100 $finish;

    end
endmodule
module test(

);

    ROM r(out,addr,clk);
    wire [7:0] out;
    reg [4:0] addr;
    reg clk;
    initial
    begin
        clk <= 0;
        addr <= 0;
    end
    always #10 clk = ~clk;

    initial
    begin
        #5 addr <= 4'd15;
        #100 $finish;

    end
endmodule