data/full_repos/permissive/497804965/fpga/air_blank_top/air_blank_top.v
data/verilator_xmls/d47f057a-2751-4334-bab3-046734e12fea.xml
module air_blank_top(

	input wire			CLOCK_50,
	input wire			RESET_N,


	output wire			EPCS_CSO_N,
	output wire			EPCS_DCLK,
	output wire			EPCS_ASDO,
	input wire			EPCS_DATA0,


	output wire			SD_DAT3,
	output wire			SD_CLK,
	output wire			SD_CMD,
	input wire			SD_DAT0,


	output wire			SD_PWR_N,


	input wire			SW_CD_N,


	output wire			SDRCLK_OUT,
	output wire			SDR_CKE,
	output wire			SDR_CS_N,
	output wire			SDR_RAS_N,
	output wire			SDR_CAS_N,
	output wire			SDR_WE_N,
	output wire [12:0]	SDR_A,
	output wire [1:0]	SDR_BA,
	inout wire  [15:0]	SDR_DQ,
	output wire [1:0]	SDR_DQM,


	inout wire  [27:0]	D,


	output wire [1:0]	USER_LED
);













	wire			reset_sig = ~RESET_N;


	wire			clock_sig = CLOCK_50;











	assign {EPCS_DCLK,EPCS_ASDO,EPCS_CSO_N} = 3'b001;
	assign {SD_CLK,SD_CMD,SD_DAT3,SD_PWR_N} = 4'bzzz1;
	assign {SDRCLK_OUT,SDR_CKE} = 2'b00;






endmodule
module air_blank_top(

	input wire			CLOCK_50,
	input wire			RESET_N,


	output wire			EPCS_CSO_N,
	output wire			EPCS_DCLK,
	output wire			EPCS_ASDO,
	input wire			EPCS_DATA0,


	output wire			SD_DAT3,
	output wire			SD_CLK,
	output wire			SD_CMD,
	input wire			SD_DAT0,


	output wire			SD_PWR_N,


	input wire			SW_CD_N,


	output wire			SDRCLK_OUT,
	output wire			SDR_CKE,
	output wire			SDR_CS_N,
	output wire			SDR_RAS_N,
	output wire			SDR_CAS_N,
	output wire			SDR_WE_N,
	output wire [12:0]	SDR_A,
	output wire [1:0]	SDR_BA,
	inout wire  [15:0]	SDR_DQ,
	output wire [1:0]	SDR_DQM,


	inout wire  [27:0]	D,


	output wire [1:0]	USER_LED
);














	wire			reset_sig = ~RESET_N;


	wire			clock_sig = CLOCK_50;











	assign {EPCS_DCLK,EPCS_ASDO,EPCS_CSO_N} = 3'b001;
	assign {SD_CLK,SD_CMD,SD_DAT3,SD_PWR_N} = 4'bzzz1;
	assign {SDRCLK_OUT,SDR_CKE} = 2'b00;






endmodule