data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v
1: b'%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:32: Cannot find include file: syn_tb_defines.vh\n`include "syn_tb_defines.vh" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb,data/full_repos/permissive/509468557/syn_tb_defines.vh\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb,data/full_repos/permissive/509468557/syn_tb_defines.vh.v\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb,data/full_repos/permissive/509468557/syn_tb_defines.vh.sv\n             syn_tb_defines.vh\n             syn_tb_defines.vh.v\n             syn_tb_defines.vh.sv\n             obj_dir/syn_tb_defines.vh\n             obj_dir/syn_tb_defines.vh.v\n             obj_dir/syn_tb_defines.vh.sv\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:65: Define or directive not defined: \'`AXI_SLAVE_BID_WIDTH\'\n    wire [`AXI_SLAVE_BID_WIDTH-1:0] axi_slave0_bid             ;\n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:68: Define or directive not defined: \'`DATABUS2MEM_WIDTH\'\n    wire   [`DATABUS2MEM_WIDTH-1:0] axi_slave0_rdata           ;\n            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:69: Define or directive not defined: \'`AXI_SLAVE_RID_WIDTH\'\n    wire [`AXI_SLAVE_RID_WIDTH-1:0] axi_slave0_rid             ;\n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:76: Define or directive not defined: \'`AXI_SLAVE_BID_WIDTH\'\n    wire [`AXI_SLAVE_BID_WIDTH-1:0] axi_slave1_bid             ;\n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:79: Define or directive not defined: \'`DATABUS2MEM_WIDTH\'\n    wire   [`DATABUS2MEM_WIDTH-1:0] axi_slave1_rdata           ;\n            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:80: Define or directive not defined: \'`AXI_SLAVE_RID_WIDTH\'\n    wire [`AXI_SLAVE_RID_WIDTH-1:0] axi_slave1_rid             ;\n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:85: Define or directive not defined: \'`AXI_ADDR_WIDTH\'\n    wire                     [`AXI_ADDR_WIDTH-1:0] axi_slave0_araddr          ;\n                              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:88: Define or directive not defined: \'`AXI_SLAVE_RID_WIDTH\'\n    wire [`AXI_SLAVE_RID_WIDTH-1:0] axi_slave0_arid            ;\n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:94: Define or directive not defined: \'`AXI_ADDR_WIDTH\'\n    wire                     [`AXI_ADDR_WIDTH-1:0] axi_slave0_awaddr          ;\n                              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:97: Define or directive not defined: \'`AXI_SLAVE_WID_WIDTH\'\n    wire [`AXI_SLAVE_WID_WIDTH-1:0] axi_slave0_awid            ;\n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:105: Define or directive not defined: \'`DATABUS2MEM_WIDTH\'\n    wire   [`DATABUS2MEM_WIDTH-1:0] axi_slave0_wdata           ;\n            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:107: Define or directive not defined: \'`DATABUS2MEM_WIDTH\'\n    wire [(`DATABUS2MEM_WIDTH/8)-1:0] axi_slave0_wstrb           ;\n           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:107: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n    wire [(`DATABUS2MEM_WIDTH/8)-1:0] axi_slave0_wstrb           ;\n                             ^\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:110: Define or directive not defined: \'`AXI_ADDR_WIDTH\'\n    wire                     [`AXI_ADDR_WIDTH-1:0] axi_slave1_araddr          ;\n                              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:113: Define or directive not defined: \'`AXI_SLAVE_RID_WIDTH\'\n    wire [`AXI_SLAVE_RID_WIDTH-1:0] axi_slave1_arid            ;\n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:119: Define or directive not defined: \'`AXI_ADDR_WIDTH\'\n    wire                     [`AXI_ADDR_WIDTH-1:0] axi_slave1_awaddr          ;\n                              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:122: Define or directive not defined: \'`AXI_SLAVE_WID_WIDTH\'\n    wire [`AXI_SLAVE_WID_WIDTH-1:0] axi_slave1_awid            ;\n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:130: Define or directive not defined: \'`DATABUS2MEM_WIDTH\'\n    wire                    [`DATABUS2MEM_WIDTH-1:0] axi_slave1_wdata           ;\n                             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:132: Define or directive not defined: \'`DATABUS2MEM_WIDTH\'\n    wire [(`DATABUS2MEM_WIDTH/8)-1:0] axi_slave1_wstrb           ;\n           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:132: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n    wire [(`DATABUS2MEM_WIDTH/8)-1:0] axi_slave1_wstrb           ;\n                             ^\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:325: syntax error, unexpected \'@\'\n  repeat (1000) @ (clk);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:330: Unsupported: Ignoring delay on this delayed statement.\n always #(simulation_cycle/2) msc_clk_ip = ~msc_clk_ip;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:331: Unsupported: Ignoring delay on this delayed statement.\n always #(simulation_cycle_mem/2) mem_clk_fast = ~mem_clk_fast;\n        ^\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:686: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("bench_pk_pass.vcd");\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:744: Unsupported: Ignoring delay on this delayed statement.\n           #(dump_start_time);\n           ^\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:751: Unsupported or unknown PLI call: $vcdplusfile\n            $vcdplusfile (vpd_dump_name);\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:752: Unsupported or unknown PLI call: $vcdpluson\n            $vcdpluson;\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:781: Unsupported or unknown PLI call: $set_gate_level_monitoring\n           $set_gate_level_monitoring("rtl_on");\n           ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:785: Unsupported or unknown PLI call: $set_toggle_region\n           $set_toggle_region("nvdla_top");\n           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:791: Unsupported: wait statements\n           wait (trans_count !== {32{1\'bx}});\n           ^~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:793: Unsupported: wait statements\n           wait (trans_count >= saif_start_trans);\n           ^~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:798: Unsupported or unknown PLI call: $toggle_start\n           #10 $toggle_start;\n               ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:798: Unsupported: Ignoring delay on this delayed statement.\n           #10 $toggle_start;\n           ^\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:804: Unsupported: wait statements\n           wait (trans_count !== {32{1\'bx}});\n           ^~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:806: Unsupported: wait statements\n           wait (trans_count >= saif_end_trans);\n           ^~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:810: Unsupported or unknown PLI call: $toggle_stop\n             $toggle_stop;\n             ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:812: Unsupported: Ignoring delay on this delayed statement.\n           #10;\n           ^\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:820: Unsupported or unknown PLI call: $psprintf\n             full_saif_filename = $psprintf("%0s/smm0.snps.saif",input_dir);\n                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:825: Unsupported or unknown PLI call: $psprintf\n             full_saif_filename = $psprintf("%0s/top0.snps.saif",input_dir);\n                                  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:850: Unsupported: Ignoring delay on this delayed statement.\n           #(dump_start_time);\n           ^\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:854: Unsupported: wait statements\n           wait (trans_count !== {32{1\'bx}});\n           ^~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:856: Unsupported: wait statements\n           wait (trans_count >= dump_start_trans);\n           ^~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:865: Unsupported or unknown PLI call: $fsdbAutoSwitchDumpfile\n                $fsdbAutoSwitchDumpfile( 1000, dump_name, 20 );\n                ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:866: Unsupported or unknown PLI call: $fsdbDumpvars\n                $fsdbDumpvars("level=",0,top);\n                ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:873: Unsupported: Ignoring delay on this delayed statement.\n              #1;\n              ^\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:986: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  $display( "(%0d) NVDLA_IP_ERROR : mem_bandwidth_window must be less than 1000)", $stime, );\n                                                                                           ^\n%Error: Exiting due to 40 error(s), 7 warning(s)\n'
module top;

`ifdef ZEBU
    reg dollar_finish;
`endif





    parameter simulation_cycle = 20;


    parameter simulation_cycle_mem = 20;





    wire      clk;
    reg       reset;
    reg       half_speed_clk;
    wire      mem_clk;
    reg       mem_clk_fast;





    wire                            axi_slave0_arready         ;
    wire                            axi_slave0_awready         ;
    wire [`AXI_SLAVE_BID_WIDTH-1:0] axi_slave0_bid             ;
    wire                      [1:0] axi_slave0_bresp           ;
    wire                            axi_slave0_bvalid          ;
    wire   [`DATABUS2MEM_WIDTH-1:0] axi_slave0_rdata           ;
    wire [`AXI_SLAVE_RID_WIDTH-1:0] axi_slave0_rid             ;
    wire                            axi_slave0_rlast           ;
    wire                            axi_slave0_rvalid          ;
    wire                            axi_slave0_wready          ;

    wire                            axi_slave1_arready         ;
    wire                            axi_slave1_awready         ;
    wire [`AXI_SLAVE_BID_WIDTH-1:0] axi_slave1_bid             ;
    wire                      [1:0] axi_slave1_bresp           ;
    wire                            axi_slave1_bvalid          ;
    wire   [`DATABUS2MEM_WIDTH-1:0] axi_slave1_rdata           ;
    wire [`AXI_SLAVE_RID_WIDTH-1:0] axi_slave1_rid             ;
    wire                            axi_slave1_rlast           ;
    wire                            axi_slave1_rvalid          ;
    wire                            axi_slave1_wready          ;
                
    wire                     [`AXI_ADDR_WIDTH-1:0] axi_slave0_araddr          ;


    wire [`AXI_SLAVE_RID_WIDTH-1:0] axi_slave0_arid            ;
    wire                      [3:0] axi_slave0_arlen           ;



    wire                            axi_slave0_arvalid         ;
    wire                     [`AXI_ADDR_WIDTH-1:0] axi_slave0_awaddr          ;


    wire [`AXI_SLAVE_WID_WIDTH-1:0] axi_slave0_awid            ;
    wire                      [3:0] axi_slave0_awlen           ;



    wire                            axi_slave0_awvalid         ;
    wire                            axi_slave0_bready          ;
    wire                            axi_slave0_rready          ;
    wire   [`DATABUS2MEM_WIDTH-1:0] axi_slave0_wdata           ;
    wire                            axi_slave0_wlast           ;
    wire [(`DATABUS2MEM_WIDTH/8)-1:0] axi_slave0_wstrb           ;
    wire                            axi_slave0_wvalid          ;

    wire                     [`AXI_ADDR_WIDTH-1:0] axi_slave1_araddr          ;


    wire [`AXI_SLAVE_RID_WIDTH-1:0] axi_slave1_arid            ;
    wire                      [3:0] axi_slave1_arlen           ;



    wire                            axi_slave1_arvalid         ;
    wire                     [`AXI_ADDR_WIDTH-1:0] axi_slave1_awaddr          ;


    wire [`AXI_SLAVE_WID_WIDTH-1:0] axi_slave1_awid            ;
    wire                      [3:0] axi_slave1_awlen           ;



    wire                            axi_slave1_awvalid         ;
    wire                            axi_slave1_bready          ;
    wire                            axi_slave1_rready          ;
    wire                    [`DATABUS2MEM_WIDTH-1:0] axi_slave1_wdata           ;
    wire                            axi_slave1_wlast           ;
    wire [(`DATABUS2MEM_WIDTH/8)-1:0] axi_slave1_wstrb           ;
    wire                            axi_slave1_wvalid          ;


    wire axi_slave0_wvalid_vip    ;
    wire axi_slave0_rready_vip    ;
    wire axi_slave1_wvalid_vip    ;
    wire axi_slave1_rready_vip    ;
    wire axi_slave0_rvalid_vip    ;
    wire axi_slave0_wready_vip    ;
    wire axi_slave1_rvalid_vip    ;
    wire axi_slave1_wready_vip    ;
    wire axi_slave0_awvalid_vip    ;
    wire axi_slave0_arready_vip    ;
    wire axi_slave1_awvalid_vip    ;
    wire axi_slave1_arready_vip    ;
    wire axi_slave0_arvalid_vip    ;
    wire axi_slave0_awready_vip    ;
    wire axi_slave1_arvalid_vip    ;
    wire axi_slave1_awready_vip    ;

    wire mem_holdoff;
    wire dla_intr;


    wire        mseq2tb_test_done;
    wire        mcsb2scsb_pvld;
    wire        mcsb2scsb_prdy;
    wire [62:0] mcsb2scsb_pd;

    wire        scsb2mcsb_valid;
    wire [31:0] scsb2mcsb_pd;
    wire        scsb2mcsb_error;
    wire        scsb2mcsb_wr_complete;
    wire        scsb2mcsb_wr_err;
    wire        scsb2mcsb_wr_rdat;

    wire        mseq_pending_req;
    wire [62:0] mseq2mcsb_pd;
    wire        mcsb2mseq_consumed_req;
    wire [31:0] mcsb2mseq_rdata; 
    wire        mcsb2mseq_rvalid;


    csb_master_seq csb_mseq(

        .clk                    (half_speed_clk) 
       ,.reset                  (reset)

       ,.mseq_pending_req       (mseq_pending_req)
       ,.mseq2mcsb_pd           (mseq2mcsb_pd)
       ,.mcsb2mseq_consumed_req (mcsb2mseq_consumed_req)
       ,.mcsb2mseq_rdata        (mcsb2mseq_rdata)
       ,.mcsb2mseq_rvalid       (mcsb2mseq_rvalid)

       ,.dut2mseq_intr0         (dla_intr)
       ,.mseq2tb_test_done      (mseq2tb_test_done)

    );


    syn_csb_master csb_master(

        .clk                    (half_speed_clk)
       ,.reset                  (reset)

       ,.mcsb2scsb_pvld         (mcsb2scsb_pvld)
       ,.mcsb2scsb_prdy         (mcsb2scsb_prdy)
       ,.mcsb2scsb_pd           (mcsb2scsb_pd)

       ,.scsb2mcsb_valid        (scsb2mcsb_valid)
       ,.scsb2mcsb_pd           (scsb2mcsb_pd)
       ,.scsb2mcsb_error        (scsb2mcsb_error)
       ,.scsb2mcsb_wr_complete  (scsb2mcsb_wr_complete)
       ,.scsb2mcsb_wr_err       (scsb2mcsb_wr_err)
       ,.scsb2mcsb_wr_rdat      (scsb2mcsb_wr_rdat)

       ,.mseq_pending_req       (mseq_pending_req)
       ,.mseq2mcsb_pd           (mseq2mcsb_pd)
       ,.mcsb2mseq_consumed_req (mcsb2mseq_consumed_req)
       ,.mcsb2mseq_rdata        (mcsb2mseq_rdata)
       ,.mcsb2mseq_rvalid       (mcsb2mseq_rvalid)

    );


    syn_slave_mem_wrap slave_mem_wrap (
        .clk                                        (mem_clk)
       ,.fast_clk                                   (mem_clk_fast)
       ,.reset                                      (reset)
       ,.saxi2nvdla_axi_slave0_arready                (axi_slave0_arready_vip     )
       ,.saxi2nvdla_axi_slave0_awready                (axi_slave0_awready_vip     )
       ,.saxi2nvdla_axi_slave0_bid                    (axi_slave0_bid             )
       ,.saxi2nvdla_axi_slave0_bresp                  (axi_slave0_bresp           )
       ,.saxi2nvdla_axi_slave0_bvalid                 (axi_slave0_bvalid          )
       ,.saxi2nvdla_axi_slave0_rdata                  (axi_slave0_rdata           )
       ,.saxi2nvdla_axi_slave0_rid                    (axi_slave0_rid             )
       ,.saxi2nvdla_axi_slave0_rlast                  (axi_slave0_rlast           )
       ,.saxi2nvdla_axi_slave0_rvalid                 (axi_slave0_rvalid_vip      )
       ,.saxi2nvdla_axi_slave0_wready                 (axi_slave0_wready_vip      )

       ,.saxi2nvdla_axi_slave1_arready                (axi_slave1_arready_vip     )
       ,.saxi2nvdla_axi_slave1_awready                (axi_slave1_awready_vip     )
       ,.saxi2nvdla_axi_slave1_bid                    (axi_slave1_bid             )
       ,.saxi2nvdla_axi_slave1_bresp                  (axi_slave1_bresp           )
       ,.saxi2nvdla_axi_slave1_bvalid                 (axi_slave1_bvalid          )
       ,.saxi2nvdla_axi_slave1_rdata                  (axi_slave1_rdata           )
       ,.saxi2nvdla_axi_slave1_rid                    (axi_slave1_rid             )
       ,.saxi2nvdla_axi_slave1_rlast                  (axi_slave1_rlast           )
       ,.saxi2nvdla_axi_slave1_rvalid                 (axi_slave1_rvalid_vip      )
       ,.saxi2nvdla_axi_slave1_wready                 (axi_slave1_wready_vip      )
                                                                                
       ,.nvdla2saxi_axi_slave0_araddr                 (axi_slave0_araddr          )
       ,.nvdla2saxi_axi_slave0_arburst                (2'b01)
       ,.nvdla2saxi_axi_slave0_arcache                (4'b0)
       ,.nvdla2saxi_axi_slave0_arid                   (axi_slave0_arid            )
       ,.nvdla2saxi_axi_slave0_arlen                  (axi_slave0_arlen           )
       ,.nvdla2saxi_axi_slave0_arlock                 (2'b0)
       ,.nvdla2saxi_axi_slave0_arprot                 (3'b0)
       ,.nvdla2saxi_axi_slave0_arsize                 (3'b110)
       ,.nvdla2saxi_axi_slave0_arvalid                (axi_slave0_arvalid_vip     )
       ,.nvdla2saxi_axi_slave0_awaddr                 (axi_slave0_awaddr          )
       ,.nvdla2saxi_axi_slave0_awburst                (2'b01)
       ,.nvdla2saxi_axi_slave0_awcache                (4'b0)
       ,.nvdla2saxi_axi_slave0_awid                   (axi_slave0_awid            )
       ,.nvdla2saxi_axi_slave0_awlen                  (axi_slave0_awlen           )
       ,.nvdla2saxi_axi_slave0_awlock                 (2'b0)
       ,.nvdla2saxi_axi_slave0_awprot                 (3'b0)
       ,.nvdla2saxi_axi_slave0_awsize                 (3'b110)
       ,.nvdla2saxi_axi_slave0_awvalid                (axi_slave0_awvalid_vip     )
       ,.nvdla2saxi_axi_slave0_bready                 (axi_slave0_bready          )
       ,.nvdla2saxi_axi_slave0_rready                 (axi_slave0_rready_vip      )
       ,.nvdla2saxi_axi_slave0_wdata                  (axi_slave0_wdata           )
       ,.nvdla2saxi_axi_slave0_wlast                  (axi_slave0_wlast           )
       ,.nvdla2saxi_axi_slave0_wstrb                  (axi_slave0_wstrb           )
       ,.nvdla2saxi_axi_slave0_wvalid                 (axi_slave0_wvalid_vip      )
                                                                                
       ,.nvdla2saxi_axi_slave1_araddr                 (axi_slave1_araddr          )
       ,.nvdla2saxi_axi_slave1_arburst                (2'b01)
       ,.nvdla2saxi_axi_slave1_arcache                (4'b0)
       ,.nvdla2saxi_axi_slave1_arid                   (axi_slave1_arid            )
       ,.nvdla2saxi_axi_slave1_arlen                  (axi_slave1_arlen           )
       ,.nvdla2saxi_axi_slave1_arlock                 (2'b0)
       ,.nvdla2saxi_axi_slave1_arprot                 (3'b0)
       ,.nvdla2saxi_axi_slave1_arsize                 (3'b110)
       ,.nvdla2saxi_axi_slave1_arvalid                (axi_slave1_arvalid_vip     )
       ,.nvdla2saxi_axi_slave1_awaddr                 (axi_slave1_awaddr          )
       ,.nvdla2saxi_axi_slave1_awburst                (2'b01)
       ,.nvdla2saxi_axi_slave1_awcache                (4'b0)
       ,.nvdla2saxi_axi_slave1_awid                   (axi_slave1_awid            )
       ,.nvdla2saxi_axi_slave1_awlen                  (axi_slave1_awlen           )
       ,.nvdla2saxi_axi_slave1_awlock                 (2'b0)
       ,.nvdla2saxi_axi_slave1_awprot                 (3'b0)
       ,.nvdla2saxi_axi_slave1_awsize                 (3'b110)
       ,.nvdla2saxi_axi_slave1_awvalid                (axi_slave1_awvalid_vip     )
       ,.nvdla2saxi_axi_slave1_bready                 (axi_slave1_bready          )
       ,.nvdla2saxi_axi_slave1_rready                 (axi_slave1_rready_vip      )
       ,.nvdla2saxi_axi_slave1_wdata                  (axi_slave1_wdata           )
       ,.nvdla2saxi_axi_slave1_wlast                  (axi_slave1_wlast           )
       ,.nvdla2saxi_axi_slave1_wstrb                  (axi_slave1_wstrb           )
       ,.nvdla2saxi_axi_slave1_wvalid                 (axi_slave1_wvalid_vip      )
    );




   reg  [31:0] trans_count;




  
   wire nvdlarstn;
   assign nvdlarstn = reset; 






   reg        msc_clk_ip;
	reg turn_off_assert_clk_tp;

`ifdef EMU_TB

`else
 	initial begin
		turn_off_assert_clk_tp = $test$plusargs("turn_off_assert_clk");
		reset = 1'b0;
		half_speed_clk = 1'b0;
		msc_clk_ip = 1'b0;
		mem_clk_fast = 1'b0;

		repeat (1000) @ (clk);
		reset = 1'b1;
	end


	always #(simulation_cycle/2) msc_clk_ip = ~msc_clk_ip;
	always #(simulation_cycle_mem/2) mem_clk_fast = ~mem_clk_fast;

	assign clk = (turn_off_assert_clk_tp) ? 0 : msc_clk_ip;

	always @ (posedge clk) begin
		half_speed_clk <= ~half_speed_clk;
	end
`endif






   wire         nvdla2soc_intr0n;
   wire         nvdla2soc_intr1n;
   

   wire   [26:0] soc2nvdla_time0_gray;
   wire   [28:0] soc2nvdla_time1_gray;
   wire   [55:0] soc2nvdla_time_gray;
   wire          soc2nvdla_time_tick;
   assign soc2nvdla_time_gray = {soc2nvdla_time1_gray,soc2nvdla_time0_gray};




   
   NV_nvdla nvdla_top (

        .dla_core_clk (half_speed_clk)
        ,.dla_csb_clk (half_speed_clk)
        ,.global_clk_ovr_on (1'b0)
        ,.tmc2slcg_disable_clock_gating (1'b0)
        ,.dla_reset_rstn (reset)
        ,.direct_reset_ (reset)
        ,.test_mode (1'b0)
        ,.csb2nvdla_valid (mcsb2scsb_pvld)
        ,.csb2nvdla_ready (mcsb2scsb_prdy)
        ,.csb2nvdla_addr (mcsb2scsb_pd[15:0])
        ,.csb2nvdla_wdat (mcsb2scsb_pd[53:22])
        ,.csb2nvdla_write (mcsb2scsb_pd[54:54])
        ,.csb2nvdla_nposted (mcsb2scsb_pd[55:55])
        ,.nvdla2csb_valid (scsb2mcsb_valid)
        ,.nvdla2csb_data (scsb2mcsb_pd)
        ,.nvdla2csb_wr_complete (scsb2mcsb_wr_complete)
        ,.nvdla_core2dbb_aw_awvalid (axi_slave0_awvalid)
        ,.nvdla_core2dbb_aw_awready (axi_slave0_awready)
        ,.nvdla_core2dbb_aw_awaddr (axi_slave0_awaddr)
        ,.nvdla_core2dbb_aw_awid (axi_slave0_awid)
        ,.nvdla_core2dbb_aw_awlen (axi_slave0_awlen)
        ,.nvdla_core2dbb_w_wvalid (axi_slave0_wvalid)
        ,.nvdla_core2dbb_w_wready (axi_slave0_wready)
        ,.nvdla_core2dbb_w_wdata (axi_slave0_wdata)
        ,.nvdla_core2dbb_w_wstrb (axi_slave0_wstrb)
        ,.nvdla_core2dbb_w_wlast (axi_slave0_wlast)
        ,.nvdla_core2dbb_b_bvalid (axi_slave0_bvalid)
        ,.nvdla_core2dbb_b_bready (axi_slave0_bready)
        ,.nvdla_core2dbb_b_bid (axi_slave0_bid)
        ,.nvdla_core2dbb_ar_arvalid (axi_slave0_arvalid)
        ,.nvdla_core2dbb_ar_arready (axi_slave0_arready)
        ,.nvdla_core2dbb_ar_araddr (axi_slave0_araddr)
        ,.nvdla_core2dbb_ar_arid (axi_slave0_arid)
        ,.nvdla_core2dbb_ar_arlen (axi_slave0_arlen)
        ,.nvdla_core2dbb_r_rvalid (axi_slave0_rvalid)
        ,.nvdla_core2dbb_r_rready (axi_slave0_rready)
        ,.nvdla_core2dbb_r_rid (axi_slave0_rid)
        ,.nvdla_core2dbb_r_rlast (axi_slave0_rlast)
        ,.nvdla_core2dbb_r_rdata (axi_slave0_rdata)
        ,.nvdla_core2cvsram_aw_awvalid (axi_slave1_awvalid)
        ,.nvdla_core2cvsram_aw_awready (axi_slave1_awready)
        ,.nvdla_core2cvsram_aw_awaddr (axi_slave1_awaddr)
        ,.nvdla_core2cvsram_aw_awid (axi_slave1_awid)
        ,.nvdla_core2cvsram_aw_awlen (axi_slave1_awlen)
        ,.nvdla_core2cvsram_w_wvalid (axi_slave1_wvalid)
        ,.nvdla_core2cvsram_w_wready (axi_slave1_wready)
        ,.nvdla_core2cvsram_w_wdata (axi_slave1_wdata)
        ,.nvdla_core2cvsram_w_wstrb (axi_slave1_wstrb)
        ,.nvdla_core2cvsram_w_wlast (axi_slave1_wlast)
        ,.nvdla_core2cvsram_b_bvalid (axi_slave1_bvalid)
        ,.nvdla_core2cvsram_b_bready (axi_slave1_bready)
        ,.nvdla_core2cvsram_b_bid (axi_slave1_bid)
        ,.nvdla_core2cvsram_ar_arvalid (axi_slave1_arvalid)
        ,.nvdla_core2cvsram_ar_arready (axi_slave1_arready)
        ,.nvdla_core2cvsram_ar_araddr (axi_slave1_araddr)
        ,.nvdla_core2cvsram_ar_arid (axi_slave1_arid)
        ,.nvdla_core2cvsram_ar_arlen (axi_slave1_arlen)
        ,.nvdla_core2cvsram_r_rvalid (axi_slave1_rvalid)
        ,.nvdla_core2cvsram_r_rready (axi_slave1_rready)
        ,.nvdla_core2cvsram_r_rid (axi_slave1_rid)
        ,.nvdla_core2cvsram_r_rlast (axi_slave1_rlast)
        ,.nvdla_core2cvsram_r_rdata (axi_slave1_rdata)
        ,.dla_intr (dla_intr)
        ,.nvdla_pwrbus_ram_c_pd (32'b0)
        ,.nvdla_pwrbus_ram_ma_pd (32'b0)
        ,.nvdla_pwrbus_ram_mb_pd (32'b0)
        ,.nvdla_pwrbus_ram_p_pd (32'b0)
        ,.nvdla_pwrbus_ram_o_pd (32'b0)
        ,.nvdla_pwrbus_ram_a_pd (32'b0)

   );





   soc2nvdla_time_gen soc2nvdla_time_gen0 (

       .clk                                 (msc_clk_ip                        )

      ,.reset_                              (nvdlarstn                           )
      ,.soc2nvdla_time1_gray                  (soc2nvdla_time1_gray                )
      ,.soc2nvdla_time0_gray                  (soc2nvdla_time0_gray                )
      ,.soc2nvdla_time_tick                   (soc2nvdla_time_tick                 )

   );

  clk_divider mem_clk_gen (
     .clk                                   (mem_clk_fast)
    ,.reset                                 (reset)
    ,.slow_clk                              (mem_clk)
  );
  
 



    reg [31:0] max_txn_outstanding;
    reg [31:0] max_rd_outstanding;
    reg [31:0] max_wr_outstanding;
    reg [31:0] slv0_rd_outstanding;
    reg [31:0] slv0_wr_outstanding;
    reg [31:0] slv1_rd_outstanding;
    reg [31:0] slv1_wr_outstanding;

    initial begin
`ifdef ZEBU

        max_txn_outstanding = 512;
        max_wr_outstanding = 512;
        max_rd_outstanding = 512;
`else
	`ifdef VIVADO
	max_txn_outstanding = $value$plusargs("max_txn_outstanding_per_channel=%d");
	if(!max_txn_outstanding) begin
            max_txn_outstanding = 512;
        end
        max_wr_outstanding = $value$plusargs("max_wr_outstanding_per_channel=%d");
        if(!max_wr_outstanding) begin
            max_wr_outstanding = 512;
        end
        max_rd_outstanding = $value$plusargs("max_rd_outstanding_per_channel=%d");
        if(!max_rd_outstanding) begin
            max_rd_outstanding = 512;
        end
	`else
        if(!($value$plusargs("max_txn_outstanding_per_channel=%d", max_txn_outstanding))) begin
            max_txn_outstanding = 512;
        end
        if(!($value$plusargs("max_wr_outstanding_per_channel=%d",  max_wr_outstanding))) begin
            max_wr_outstanding = 512;
        end
        if(!($value$plusargs("max_rd_outstanding_per_channel=%d",  max_rd_outstanding))) begin
            max_rd_outstanding = 512;
        end
	`endif
`endif
    end


    reg mem0_txn_rd_holdoff;
    reg mem1_txn_rd_holdoff;
    reg mem0_txn_wr_holdoff;
    reg mem1_txn_wr_holdoff;
    reg [31:0] slv0_txn_outstanding; 
    reg [31:0] slv1_txn_outstanding;
    reg carry_out0, carry_out1;
    reg [31:0] slv0_outstanding;
    reg [31:0] slv1_outstanding;

    wire mem0_wr_cnt_incr;
    wire mem0_rd_cnt_incr;
    wire mem1_wr_cnt_incr;
    wire mem1_rd_cnt_incr;
    wire mem0_wr_cnt_decr;
    wire mem0_rd_cnt_decr;
    wire mem1_wr_cnt_decr;
    wire mem1_rd_cnt_decr;




    always @(*) begin   
      {carry_out0,slv0_txn_outstanding} = slv0_rd_outstanding + slv0_wr_outstanding;
      {carry_out1,slv1_txn_outstanding} = slv1_rd_outstanding + slv1_wr_outstanding;
    end
       
 
    always @ (negedge mem_clk or negedge reset) begin
        if(!reset) begin
            mem0_txn_wr_holdoff <= 0; 
            mem1_txn_wr_holdoff <= 0; 
            mem0_txn_rd_holdoff <= 0; 
            mem1_txn_rd_holdoff <= 0; 
        end else begin
            mem0_txn_wr_holdoff <= slv0_txn_outstanding >= max_txn_outstanding || slv0_wr_outstanding >= max_wr_outstanding;
            mem1_txn_wr_holdoff <= slv1_txn_outstanding >= max_txn_outstanding || slv1_wr_outstanding >= max_wr_outstanding;
            mem0_txn_rd_holdoff <= slv0_txn_outstanding >= max_txn_outstanding || slv0_rd_outstanding >= max_rd_outstanding;
            mem1_txn_rd_holdoff <= slv1_txn_outstanding >= max_txn_outstanding || slv1_rd_outstanding >= max_rd_outstanding;
        end
    end

    assign mem0_wr_cnt_incr = axi_slave0_awvalid && axi_slave0_awready;
    assign mem0_rd_cnt_incr = axi_slave0_arvalid && axi_slave0_arready;
    assign mem1_wr_cnt_incr = axi_slave1_awvalid && axi_slave1_awready;
    assign mem1_rd_cnt_incr = axi_slave1_arvalid && axi_slave1_arready;
    assign mem0_wr_cnt_decr = axi_slave0_bvalid && axi_slave0_bready; 
    assign mem0_rd_cnt_decr = axi_slave0_rvalid && axi_slave0_rready && axi_slave0_rlast; 
    assign mem1_wr_cnt_decr = axi_slave1_bvalid && axi_slave1_bready; 
    assign mem1_rd_cnt_decr = axi_slave1_rvalid && axi_slave1_rready && axi_slave1_rlast; 

    always @ (posedge mem_clk or negedge reset) begin
        if(!reset) begin
            slv0_rd_outstanding <= 0;
            slv0_wr_outstanding <= 0;
            slv1_rd_outstanding <= 0;
            slv1_wr_outstanding <= 0;
        end else begin
            slv0_rd_outstanding <= (mem0_rd_cnt_incr && !mem0_rd_cnt_decr) ? slv0_rd_outstanding + 1 :
                                   (!mem0_rd_cnt_incr && mem0_rd_cnt_decr) ? slv0_rd_outstanding - 1 :
                                                                             slv0_rd_outstanding;
            slv0_wr_outstanding <= (mem0_wr_cnt_incr && !mem0_wr_cnt_decr) ? slv0_wr_outstanding + 1 :
                                   (!mem0_wr_cnt_incr && mem0_wr_cnt_decr) ? slv0_wr_outstanding - 1 :
                                                                             slv0_wr_outstanding;
            slv1_rd_outstanding <= (mem1_rd_cnt_incr && !mem1_rd_cnt_decr) ? slv1_rd_outstanding + 1 :
                                   (!mem1_rd_cnt_incr && mem1_rd_cnt_decr) ? slv1_rd_outstanding - 1 :
                                                                             slv1_rd_outstanding;
            slv1_wr_outstanding <= (mem1_wr_cnt_incr && !mem1_wr_cnt_decr) ? slv1_wr_outstanding + 1 :
                                   (!mem1_wr_cnt_incr && mem1_wr_cnt_decr) ? slv1_wr_outstanding - 1 :
                                                                             slv1_wr_outstanding;
        end
    end


`ifdef EMU_TB
   bandwidth_mon bw_mon (
   .clk         (mem_clk),
   .event0      (1'b0),
   .event1      (axi_slave0_rvalid && axi_slave0_rready),
   .event2      (axi_slave1_wvalid && axi_slave1_wready),
   .event3      (axi_slave1_rvalid && axi_slave1_rready),
   .holdoff     (mem_holdoff)
   );
`else
   bandwidth_mon bw_mon (
   .clk         (mem_clk),
   .event0      (axi_slave0_wvalid && axi_slave0_wready),
   .event1      (axi_slave0_rvalid && axi_slave0_rready),
   .event2      (axi_slave1_wvalid && axi_slave1_wready),
   .event3      (axi_slave1_rvalid && axi_slave1_rready),
   .holdoff     (mem_holdoff)
   );
`endif

   assert_module a0 (
    .clk		(clk)
    ,.test		(carry_out0 || carry_out1)
   );

 
   bandwidth_throttle mem0_wradr_throttle (
    .clk        (mem_clk),
    .holdoff    (mem0_txn_wr_holdoff),
    .valid_in   (axi_slave0_awvalid),
    .ready_out  (axi_slave0_awready),

    .valid_out  (axi_slave0_awvalid_vip),
    .ready_in   (axi_slave0_awready_vip)
   );

   bandwidth_throttle mem1_wradr_throttle (
    .clk        (mem_clk),
    .holdoff    (mem1_txn_wr_holdoff),
    .valid_in   (axi_slave1_awvalid),
    .ready_out  (axi_slave1_awready),

    .valid_out  (axi_slave1_awvalid_vip),
    .ready_in   (axi_slave1_awready_vip)
   );

    bandwidth_throttle mem0_rdadr_throttle (
    .clk        (mem_clk),
    .holdoff    (mem0_txn_rd_holdoff),
    .valid_in   (axi_slave0_arvalid),
    .ready_out  (axi_slave0_arready),

    .valid_out  (axi_slave0_arvalid_vip),
    .ready_in   (axi_slave0_arready_vip)
   );

   bandwidth_throttle mem1_rdadr_throttle (
    .clk        (mem_clk),
    .holdoff    (mem1_txn_rd_holdoff),
    .valid_in   (axi_slave1_arvalid),
    .ready_out  (axi_slave1_arready),

    .valid_out  (axi_slave1_arvalid_vip),
    .ready_in   (axi_slave1_arready_vip)
   );

   bandwidth_throttle mem0_wr_bw_mon (
    .clk        (mem_clk),
    .holdoff    (mem_holdoff),
    .valid_in   (axi_slave0_wvalid),
    .ready_out  (axi_slave0_wready),

    .valid_out  (axi_slave0_wvalid_vip),
    .ready_in   (axi_slave0_wready_vip)
   );
   bandwidth_throttle mem1_wr_bw_mon (
    .clk        (mem_clk),
    .holdoff    (mem_holdoff),
    .valid_in   (axi_slave1_wvalid),
    .ready_out  (axi_slave1_wready),

    .valid_out  (axi_slave1_wvalid_vip),
    .ready_in   (axi_slave1_wready_vip)
   );
   bandwidth_throttle mem0_rd_bw_mon (
    .clk        (mem_clk),
    .holdoff    (mem_holdoff),
    .valid_out  (axi_slave0_rvalid),
    .ready_in   (axi_slave0_rready),

    .valid_in   (axi_slave0_rvalid_vip),
    .ready_out  (axi_slave0_rready_vip)

   );
   bandwidth_throttle mem1_rd_bw_mon (
    .clk        (mem_clk),
    .holdoff    (mem_holdoff),
    .valid_out  (axi_slave1_rvalid),
    .ready_in   (axi_slave1_rready),

    .valid_in   (axi_slave1_rvalid_vip),
    .ready_out  (axi_slave1_rready_vip)
   );





`ifndef ZEBU
`ifndef EMU_TB
initial begin
$dumpfile("bench_pk_pass.vcd");
`ifdef VCS
    $vcdpluson (0,

	top.slave_mem_wrap.axi_slave0,
	top.slave_mem_wrap.axi_slave1,
	top.slave_mem_wrap.dbb_mem,
	top.slave_mem_wrap.cvsram_mem,
	top.mem_clk_gen,top.clk, top.msc_clk_ip, top.reset, top.mem_clk_fast, top.mem_clk);
`endif

end


  `ifdef NO_DUMPS
  `else

    reg [31:0]        dump_start_trans;
    reg [63:0]        dump_start_time;
    reg [63:0]        dump_stop_time;
    reg [(256*8)-1:0] vpd_dump_name;


    `ifndef VIVADO
    string            input_dir, full_saif_filename ;
    `endif

    reg [31:0]        saif_start_trans;
    reg [31:0]        saif_end_trans;


    initial begin




       `ifdef VIVADO
	 vpd_dump_name = $value$plusargs("vpd_dump_name=%s");
         if(!vpd_dump_name)  vpd_dump_name = "vpdplus.vpd";

         dump_start_time = $value$plusargs("dump_start_time=%d");
         if(!dump_start_time)  dump_start_time = 0;
       `else
         if(!$value$plusargs("vpd_dump_name=%s", vpd_dump_name))  vpd_dump_name = "vpdplus.vpd";
         if(!$value$plusargs("dump_start_time=%d", dump_start_time))  dump_start_time = 0;
       `endif

       if ( dump_start_time != 0 ) begin
           #(dump_start_time);
       end
       if ($test$plusargs("dump_vpd") || $test$plusargs("dump_vcd")) begin



	  `ifndef VIVADO
            $vcdplusfile (vpd_dump_name);
            $vcdpluson;
          `endif
        `ifdef WAVES      
          $dumpvars;
        `endif
       end
    end

    reg [(256*8)-1:0] saif_name;
    initial begin
       if ($test$plusargs("dump_saif")) begin

         `ifdef VIVADO
           saif_name = $value$plusargs("saif_name=%s");
           if(!saif_name)  saif_name = "out.saif";

           saif_start_trans = $value$plusargs("saif_start_trans=%d");
           if(!saif_start_trans)  saif_start_trans = 0;

           saif_end_trans = $value$plusargs("saif_end_trans=%d");
           if(!saif_end_trans)  saif_end_trans = 9999999;
	 `else
           if(!$value$plusargs("saif_name=%s", saif_name))  saif_name = "out.saif";
           if(!$value$plusargs("saif_start_trans=%d", saif_start_trans))  saif_start_trans = 0;
           if(!$value$plusargs("saif_end_trans=%d", saif_end_trans))  saif_end_trans = 9999999;
	 `endif

         $display( "(%0d) NVDLA_IP_INFO : monitoring with rtl_on for saif", $stime );
	 `ifndef VIVADO
           $set_gate_level_monitoring("rtl_on");
         `endif
         $display( "(%0d) NVDLA_IP_INFO : setting toggle region for saif", $stime );
	 `ifndef VIVADO
           $set_toggle_region("nvdla_top");
         `endif


         if ( saif_start_trans != 0 ) begin
           $display( "(%0d) NVDLA_IP_INFO : saif_start_trans enabled in file %0s", $stime, saif_name );
           wait (trans_count !== {32{1'bx}});
           $display( "(%0d) NVDLA_IP_INFO : start waiting for saif trans_count == %d", $stime, saif_start_trans );
           wait (trans_count >= saif_start_trans);
           $display( "(%0d) NVDLA_IP_INFO : starting saif, trans_count == %d", $stime, trans_count );
         end

	 `ifndef VIVADO
           #10 $toggle_start;
	 `endif
         $display( "(%0d) NVDLA_IP_INFO : toggle start for saif", $stime );

         if ( saif_end_trans != 0 ) begin
           $display( "(%0d) NVDLA_IP_INFO : saif_end_trans enabled in file %0s", $stime, saif_name );
           wait (trans_count !== {32{1'bx}});
           $display( "(%0d) NVDLA_IP_INFO : end waiting for trans_count == %d", $stime, saif_end_trans );
           wait (trans_count >= saif_end_trans);
           $display( "(%0d) NVDLA_IP_INFO : ending saif, trans_count == %d", $stime, trans_count );

	   `ifndef VIVADO
             $toggle_stop;
	   `endif
           #10;




`ifndef VIVADO
           if($value$plusargs("input_dir=%s", input_dir)) begin
            if ($test$plusargs("dump_smm_saif")) begin
             full_saif_filename = $psprintf("%0s/smm0.snps.saif",input_dir);
             $display( "(%0d) NVDLA_IP_INFO : creating toggle report for smmmio (%0s)", $stime, full_saif_filename );

            end
            if ($test$plusargs("dump_top_saif")) begin
             full_saif_filename = $psprintf("%0s/top0.snps.saif",input_dir);


            end
           end
`endif
         end

       end
    end


    reg [(256*8)-1:0] dump_name;
    reg [(256*8)-1:0] dump_cone;
    reg [(256*8)-1:0] esa_path;
    reg [(256*8)-1:0] tb_dir;
    integer           esa_fhandle;

    initial begin
       if(!$value$plusargs("dump_name=%s", dump_name))  dump_name = "debussy.fsdb";
       if(!$value$plusargs("dump_start_time=%d", dump_start_time))  dump_start_time = 1;
       if(!$value$plusargs("dump_start_trans=%d", dump_start_trans))  dump_start_trans = 0;
       dump_stop_time = 0;
       
       if ( dump_start_time != 0 ) begin
           #(dump_start_time);
       end
       if ( dump_start_trans != 0 ) begin
           $display( "(%0d) NVDLA_IP_INFO : dump_start_trans enabled in file %0s", $stime, dump_name );
           wait (trans_count !== {32{1'bx}});
           $display( "(%0d) NVDLA_IP_INFO : waiting for trans_count == %d", $stime, dump_start_trans );
           wait (trans_count >= dump_start_trans);
           $display( "(%0d) NVDLA_IP_INFO : starting fsdb dump, trans_count == %d", $stime, trans_count );
       end
       if ( $test$plusargs("dump_fsdb") || $test$plusargs("fsdb_dump")) begin
              $display( "(%0d) NVDLA_IP_INFO : Turning on fsdb dump to file %0s", $stime, dump_name );
             `ifdef VERILINT
             `else
             `endif
	      `ifndef VIVADO
                $fsdbAutoSwitchDumpfile( 1000, dump_name, 20 );
                $fsdbDumpvars("level=",0,top);
	      `endif





              #1;
              $display( "(%0d) NVDLA_IP_INFO : fsdb dumping enabled. %0s", $stime, dump_name );
       end

    end
  `endif
`endif
`endif

endmodule
module top;


`ifdef ZEBU
    reg dollar_finish;
`endif





    parameter simulation_cycle = 20;


    parameter simulation_cycle_mem = 20;





    wire      clk;
    reg       reset;
    reg       half_speed_clk;
    wire      mem_clk;
    reg       mem_clk_fast;





    wire                            axi_slave0_arready         ;
    wire                            axi_slave0_awready         ;
    wire [`AXI_SLAVE_BID_WIDTH-1:0] axi_slave0_bid             ;
    wire                      [1:0] axi_slave0_bresp           ;
    wire                            axi_slave0_bvalid          ;
    wire   [`DATABUS2MEM_WIDTH-1:0] axi_slave0_rdata           ;
    wire [`AXI_SLAVE_RID_WIDTH-1:0] axi_slave0_rid             ;
    wire                            axi_slave0_rlast           ;
    wire                            axi_slave0_rvalid          ;
    wire                            axi_slave0_wready          ;

    wire                            axi_slave1_arready         ;
    wire                            axi_slave1_awready         ;
    wire [`AXI_SLAVE_BID_WIDTH-1:0] axi_slave1_bid             ;
    wire                      [1:0] axi_slave1_bresp           ;
    wire                            axi_slave1_bvalid          ;
    wire   [`DATABUS2MEM_WIDTH-1:0] axi_slave1_rdata           ;
    wire [`AXI_SLAVE_RID_WIDTH-1:0] axi_slave1_rid             ;
    wire                            axi_slave1_rlast           ;
    wire                            axi_slave1_rvalid          ;
    wire                            axi_slave1_wready          ;
                
    wire                     [`AXI_ADDR_WIDTH-1:0] axi_slave0_araddr          ;


    wire [`AXI_SLAVE_RID_WIDTH-1:0] axi_slave0_arid            ;
    wire                      [3:0] axi_slave0_arlen           ;



    wire                            axi_slave0_arvalid         ;
    wire                     [`AXI_ADDR_WIDTH-1:0] axi_slave0_awaddr          ;


    wire [`AXI_SLAVE_WID_WIDTH-1:0] axi_slave0_awid            ;
    wire                      [3:0] axi_slave0_awlen           ;



    wire                            axi_slave0_awvalid         ;
    wire                            axi_slave0_bready          ;
    wire                            axi_slave0_rready          ;
    wire   [`DATABUS2MEM_WIDTH-1:0] axi_slave0_wdata           ;
    wire                            axi_slave0_wlast           ;
    wire [(`DATABUS2MEM_WIDTH/8)-1:0] axi_slave0_wstrb           ;
    wire                            axi_slave0_wvalid          ;

    wire                     [`AXI_ADDR_WIDTH-1:0] axi_slave1_araddr          ;


    wire [`AXI_SLAVE_RID_WIDTH-1:0] axi_slave1_arid            ;
    wire                      [3:0] axi_slave1_arlen           ;



    wire                            axi_slave1_arvalid         ;
    wire                     [`AXI_ADDR_WIDTH-1:0] axi_slave1_awaddr          ;


    wire [`AXI_SLAVE_WID_WIDTH-1:0] axi_slave1_awid            ;
    wire                      [3:0] axi_slave1_awlen           ;



    wire                            axi_slave1_awvalid         ;
    wire                            axi_slave1_bready          ;
    wire                            axi_slave1_rready          ;
    wire                    [`DATABUS2MEM_WIDTH-1:0] axi_slave1_wdata           ;
    wire                            axi_slave1_wlast           ;
    wire [(`DATABUS2MEM_WIDTH/8)-1:0] axi_slave1_wstrb           ;
    wire                            axi_slave1_wvalid          ;


    wire axi_slave0_wvalid_vip    ;
    wire axi_slave0_rready_vip    ;
    wire axi_slave1_wvalid_vip    ;
    wire axi_slave1_rready_vip    ;
    wire axi_slave0_rvalid_vip    ;
    wire axi_slave0_wready_vip    ;
    wire axi_slave1_rvalid_vip    ;
    wire axi_slave1_wready_vip    ;
    wire axi_slave0_awvalid_vip    ;
    wire axi_slave0_arready_vip    ;
    wire axi_slave1_awvalid_vip    ;
    wire axi_slave1_arready_vip    ;
    wire axi_slave0_arvalid_vip    ;
    wire axi_slave0_awready_vip    ;
    wire axi_slave1_arvalid_vip    ;
    wire axi_slave1_awready_vip    ;

    wire mem_holdoff;
    wire dla_intr;


    wire        mseq2tb_test_done;
    wire        mcsb2scsb_pvld;
    wire        mcsb2scsb_prdy;
    wire [62:0] mcsb2scsb_pd;

    wire        scsb2mcsb_valid;
    wire [31:0] scsb2mcsb_pd;
    wire        scsb2mcsb_error;
    wire        scsb2mcsb_wr_complete;
    wire        scsb2mcsb_wr_err;
    wire        scsb2mcsb_wr_rdat;

    wire        mseq_pending_req;
    wire [62:0] mseq2mcsb_pd;
    wire        mcsb2mseq_consumed_req;
    wire [31:0] mcsb2mseq_rdata; 
    wire        mcsb2mseq_rvalid;


    csb_master_seq csb_mseq(

        .clk                    (half_speed_clk) 
       ,.reset                  (reset)

       ,.mseq_pending_req       (mseq_pending_req)
       ,.mseq2mcsb_pd           (mseq2mcsb_pd)
       ,.mcsb2mseq_consumed_req (mcsb2mseq_consumed_req)
       ,.mcsb2mseq_rdata        (mcsb2mseq_rdata)
       ,.mcsb2mseq_rvalid       (mcsb2mseq_rvalid)

       ,.dut2mseq_intr0         (dla_intr)
       ,.mseq2tb_test_done      (mseq2tb_test_done)

    );


    syn_csb_master csb_master(

        .clk                    (half_speed_clk)
       ,.reset                  (reset)

       ,.mcsb2scsb_pvld         (mcsb2scsb_pvld)
       ,.mcsb2scsb_prdy         (mcsb2scsb_prdy)
       ,.mcsb2scsb_pd           (mcsb2scsb_pd)

       ,.scsb2mcsb_valid        (scsb2mcsb_valid)
       ,.scsb2mcsb_pd           (scsb2mcsb_pd)
       ,.scsb2mcsb_error        (scsb2mcsb_error)
       ,.scsb2mcsb_wr_complete  (scsb2mcsb_wr_complete)
       ,.scsb2mcsb_wr_err       (scsb2mcsb_wr_err)
       ,.scsb2mcsb_wr_rdat      (scsb2mcsb_wr_rdat)

       ,.mseq_pending_req       (mseq_pending_req)
       ,.mseq2mcsb_pd           (mseq2mcsb_pd)
       ,.mcsb2mseq_consumed_req (mcsb2mseq_consumed_req)
       ,.mcsb2mseq_rdata        (mcsb2mseq_rdata)
       ,.mcsb2mseq_rvalid       (mcsb2mseq_rvalid)

    );


    syn_slave_mem_wrap slave_mem_wrap (
        .clk                                        (mem_clk)
       ,.fast_clk                                   (mem_clk_fast)
       ,.reset                                      (reset)
       ,.saxi2nvdla_axi_slave0_arready                (axi_slave0_arready_vip     )
       ,.saxi2nvdla_axi_slave0_awready                (axi_slave0_awready_vip     )
       ,.saxi2nvdla_axi_slave0_bid                    (axi_slave0_bid             )
       ,.saxi2nvdla_axi_slave0_bresp                  (axi_slave0_bresp           )
       ,.saxi2nvdla_axi_slave0_bvalid                 (axi_slave0_bvalid          )
       ,.saxi2nvdla_axi_slave0_rdata                  (axi_slave0_rdata           )
       ,.saxi2nvdla_axi_slave0_rid                    (axi_slave0_rid             )
       ,.saxi2nvdla_axi_slave0_rlast                  (axi_slave0_rlast           )
       ,.saxi2nvdla_axi_slave0_rvalid                 (axi_slave0_rvalid_vip      )
       ,.saxi2nvdla_axi_slave0_wready                 (axi_slave0_wready_vip      )

       ,.saxi2nvdla_axi_slave1_arready                (axi_slave1_arready_vip     )
       ,.saxi2nvdla_axi_slave1_awready                (axi_slave1_awready_vip     )
       ,.saxi2nvdla_axi_slave1_bid                    (axi_slave1_bid             )
       ,.saxi2nvdla_axi_slave1_bresp                  (axi_slave1_bresp           )
       ,.saxi2nvdla_axi_slave1_bvalid                 (axi_slave1_bvalid          )
       ,.saxi2nvdla_axi_slave1_rdata                  (axi_slave1_rdata           )
       ,.saxi2nvdla_axi_slave1_rid                    (axi_slave1_rid             )
       ,.saxi2nvdla_axi_slave1_rlast                  (axi_slave1_rlast           )
       ,.saxi2nvdla_axi_slave1_rvalid                 (axi_slave1_rvalid_vip      )
       ,.saxi2nvdla_axi_slave1_wready                 (axi_slave1_wready_vip      )
                                                                                
       ,.nvdla2saxi_axi_slave0_araddr                 (axi_slave0_araddr          )
       ,.nvdla2saxi_axi_slave0_arburst                (2'b01)
       ,.nvdla2saxi_axi_slave0_arcache                (4'b0)
       ,.nvdla2saxi_axi_slave0_arid                   (axi_slave0_arid            )
       ,.nvdla2saxi_axi_slave0_arlen                  (axi_slave0_arlen           )
       ,.nvdla2saxi_axi_slave0_arlock                 (2'b0)
       ,.nvdla2saxi_axi_slave0_arprot                 (3'b0)
       ,.nvdla2saxi_axi_slave0_arsize                 (3'b110)
       ,.nvdla2saxi_axi_slave0_arvalid                (axi_slave0_arvalid_vip     )
       ,.nvdla2saxi_axi_slave0_awaddr                 (axi_slave0_awaddr          )
       ,.nvdla2saxi_axi_slave0_awburst                (2'b01)
       ,.nvdla2saxi_axi_slave0_awcache                (4'b0)
       ,.nvdla2saxi_axi_slave0_awid                   (axi_slave0_awid            )
       ,.nvdla2saxi_axi_slave0_awlen                  (axi_slave0_awlen           )
       ,.nvdla2saxi_axi_slave0_awlock                 (2'b0)
       ,.nvdla2saxi_axi_slave0_awprot                 (3'b0)
       ,.nvdla2saxi_axi_slave0_awsize                 (3'b110)
       ,.nvdla2saxi_axi_slave0_awvalid                (axi_slave0_awvalid_vip     )
       ,.nvdla2saxi_axi_slave0_bready                 (axi_slave0_bready          )
       ,.nvdla2saxi_axi_slave0_rready                 (axi_slave0_rready_vip      )
       ,.nvdla2saxi_axi_slave0_wdata                  (axi_slave0_wdata           )
       ,.nvdla2saxi_axi_slave0_wlast                  (axi_slave0_wlast           )
       ,.nvdla2saxi_axi_slave0_wstrb                  (axi_slave0_wstrb           )
       ,.nvdla2saxi_axi_slave0_wvalid                 (axi_slave0_wvalid_vip      )
                                                                                
       ,.nvdla2saxi_axi_slave1_araddr                 (axi_slave1_araddr          )
       ,.nvdla2saxi_axi_slave1_arburst                (2'b01)
       ,.nvdla2saxi_axi_slave1_arcache                (4'b0)
       ,.nvdla2saxi_axi_slave1_arid                   (axi_slave1_arid            )
       ,.nvdla2saxi_axi_slave1_arlen                  (axi_slave1_arlen           )
       ,.nvdla2saxi_axi_slave1_arlock                 (2'b0)
       ,.nvdla2saxi_axi_slave1_arprot                 (3'b0)
       ,.nvdla2saxi_axi_slave1_arsize                 (3'b110)
       ,.nvdla2saxi_axi_slave1_arvalid                (axi_slave1_arvalid_vip     )
       ,.nvdla2saxi_axi_slave1_awaddr                 (axi_slave1_awaddr          )
       ,.nvdla2saxi_axi_slave1_awburst                (2'b01)
       ,.nvdla2saxi_axi_slave1_awcache                (4'b0)
       ,.nvdla2saxi_axi_slave1_awid                   (axi_slave1_awid            )
       ,.nvdla2saxi_axi_slave1_awlen                  (axi_slave1_awlen           )
       ,.nvdla2saxi_axi_slave1_awlock                 (2'b0)
       ,.nvdla2saxi_axi_slave1_awprot                 (3'b0)
       ,.nvdla2saxi_axi_slave1_awsize                 (3'b110)
       ,.nvdla2saxi_axi_slave1_awvalid                (axi_slave1_awvalid_vip     )
       ,.nvdla2saxi_axi_slave1_bready                 (axi_slave1_bready          )
       ,.nvdla2saxi_axi_slave1_rready                 (axi_slave1_rready_vip      )
       ,.nvdla2saxi_axi_slave1_wdata                  (axi_slave1_wdata           )
       ,.nvdla2saxi_axi_slave1_wlast                  (axi_slave1_wlast           )
       ,.nvdla2saxi_axi_slave1_wstrb                  (axi_slave1_wstrb           )
       ,.nvdla2saxi_axi_slave1_wvalid                 (axi_slave1_wvalid_vip      )
    );




   reg  [31:0] trans_count;




  
   wire nvdlarstn;
   assign nvdlarstn = reset; 






   reg        msc_clk_ip;
	reg turn_off_assert_clk_tp;

`ifdef EMU_TB

`else
 	initial begin
		turn_off_assert_clk_tp = $test$plusargs("turn_off_assert_clk");
		reset = 1'b0;
		half_speed_clk = 1'b0;
		msc_clk_ip = 1'b0;
		mem_clk_fast = 1'b0;

		repeat (1000) @ (clk);
		reset = 1'b1;
	end


	always #(simulation_cycle/2) msc_clk_ip = ~msc_clk_ip;
	always #(simulation_cycle_mem/2) mem_clk_fast = ~mem_clk_fast;

	assign clk = (turn_off_assert_clk_tp) ? 0 : msc_clk_ip;

	always @ (posedge clk) begin
		half_speed_clk <= ~half_speed_clk;
	end
`endif






   wire         nvdla2soc_intr0n;
   wire         nvdla2soc_intr1n;
   

   wire   [26:0] soc2nvdla_time0_gray;
   wire   [28:0] soc2nvdla_time1_gray;
   wire   [55:0] soc2nvdla_time_gray;
   wire          soc2nvdla_time_tick;
   assign soc2nvdla_time_gray = {soc2nvdla_time1_gray,soc2nvdla_time0_gray};




   
   NV_nvdla nvdla_top (

        .dla_core_clk (half_speed_clk)
        ,.dla_csb_clk (half_speed_clk)
        ,.global_clk_ovr_on (1'b0)
        ,.tmc2slcg_disable_clock_gating (1'b0)
        ,.dla_reset_rstn (reset)
        ,.direct_reset_ (reset)
        ,.test_mode (1'b0)
        ,.csb2nvdla_valid (mcsb2scsb_pvld)
        ,.csb2nvdla_ready (mcsb2scsb_prdy)
        ,.csb2nvdla_addr (mcsb2scsb_pd[15:0])
        ,.csb2nvdla_wdat (mcsb2scsb_pd[53:22])
        ,.csb2nvdla_write (mcsb2scsb_pd[54:54])
        ,.csb2nvdla_nposted (mcsb2scsb_pd[55:55])
        ,.nvdla2csb_valid (scsb2mcsb_valid)
        ,.nvdla2csb_data (scsb2mcsb_pd)
        ,.nvdla2csb_wr_complete (scsb2mcsb_wr_complete)
        ,.nvdla_core2dbb_aw_awvalid (axi_slave0_awvalid)
        ,.nvdla_core2dbb_aw_awready (axi_slave0_awready)
        ,.nvdla_core2dbb_aw_awaddr (axi_slave0_awaddr)
        ,.nvdla_core2dbb_aw_awid (axi_slave0_awid)
        ,.nvdla_core2dbb_aw_awlen (axi_slave0_awlen)
        ,.nvdla_core2dbb_w_wvalid (axi_slave0_wvalid)
        ,.nvdla_core2dbb_w_wready (axi_slave0_wready)
        ,.nvdla_core2dbb_w_wdata (axi_slave0_wdata)
        ,.nvdla_core2dbb_w_wstrb (axi_slave0_wstrb)
        ,.nvdla_core2dbb_w_wlast (axi_slave0_wlast)
        ,.nvdla_core2dbb_b_bvalid (axi_slave0_bvalid)
        ,.nvdla_core2dbb_b_bready (axi_slave0_bready)
        ,.nvdla_core2dbb_b_bid (axi_slave0_bid)
        ,.nvdla_core2dbb_ar_arvalid (axi_slave0_arvalid)
        ,.nvdla_core2dbb_ar_arready (axi_slave0_arready)
        ,.nvdla_core2dbb_ar_araddr (axi_slave0_araddr)
        ,.nvdla_core2dbb_ar_arid (axi_slave0_arid)
        ,.nvdla_core2dbb_ar_arlen (axi_slave0_arlen)
        ,.nvdla_core2dbb_r_rvalid (axi_slave0_rvalid)
        ,.nvdla_core2dbb_r_rready (axi_slave0_rready)
        ,.nvdla_core2dbb_r_rid (axi_slave0_rid)
        ,.nvdla_core2dbb_r_rlast (axi_slave0_rlast)
        ,.nvdla_core2dbb_r_rdata (axi_slave0_rdata)
        ,.nvdla_core2cvsram_aw_awvalid (axi_slave1_awvalid)
        ,.nvdla_core2cvsram_aw_awready (axi_slave1_awready)
        ,.nvdla_core2cvsram_aw_awaddr (axi_slave1_awaddr)
        ,.nvdla_core2cvsram_aw_awid (axi_slave1_awid)
        ,.nvdla_core2cvsram_aw_awlen (axi_slave1_awlen)
        ,.nvdla_core2cvsram_w_wvalid (axi_slave1_wvalid)
        ,.nvdla_core2cvsram_w_wready (axi_slave1_wready)
        ,.nvdla_core2cvsram_w_wdata (axi_slave1_wdata)
        ,.nvdla_core2cvsram_w_wstrb (axi_slave1_wstrb)
        ,.nvdla_core2cvsram_w_wlast (axi_slave1_wlast)
        ,.nvdla_core2cvsram_b_bvalid (axi_slave1_bvalid)
        ,.nvdla_core2cvsram_b_bready (axi_slave1_bready)
        ,.nvdla_core2cvsram_b_bid (axi_slave1_bid)
        ,.nvdla_core2cvsram_ar_arvalid (axi_slave1_arvalid)
        ,.nvdla_core2cvsram_ar_arready (axi_slave1_arready)
        ,.nvdla_core2cvsram_ar_araddr (axi_slave1_araddr)
        ,.nvdla_core2cvsram_ar_arid (axi_slave1_arid)
        ,.nvdla_core2cvsram_ar_arlen (axi_slave1_arlen)
        ,.nvdla_core2cvsram_r_rvalid (axi_slave1_rvalid)
        ,.nvdla_core2cvsram_r_rready (axi_slave1_rready)
        ,.nvdla_core2cvsram_r_rid (axi_slave1_rid)
        ,.nvdla_core2cvsram_r_rlast (axi_slave1_rlast)
        ,.nvdla_core2cvsram_r_rdata (axi_slave1_rdata)
        ,.dla_intr (dla_intr)
        ,.nvdla_pwrbus_ram_c_pd (32'b0)
        ,.nvdla_pwrbus_ram_ma_pd (32'b0)
        ,.nvdla_pwrbus_ram_mb_pd (32'b0)
        ,.nvdla_pwrbus_ram_p_pd (32'b0)
        ,.nvdla_pwrbus_ram_o_pd (32'b0)
        ,.nvdla_pwrbus_ram_a_pd (32'b0)

   );





   soc2nvdla_time_gen soc2nvdla_time_gen0 (

       .clk                                 (msc_clk_ip                        )

      ,.reset_                              (nvdlarstn                           )
      ,.soc2nvdla_time1_gray                  (soc2nvdla_time1_gray                )
      ,.soc2nvdla_time0_gray                  (soc2nvdla_time0_gray                )
      ,.soc2nvdla_time_tick                   (soc2nvdla_time_tick                 )

   );

  clk_divider mem_clk_gen (
     .clk                                   (mem_clk_fast)
    ,.reset                                 (reset)
    ,.slow_clk                              (mem_clk)
  );
  
 



    reg [31:0] max_txn_outstanding;
    reg [31:0] max_rd_outstanding;
    reg [31:0] max_wr_outstanding;
    reg [31:0] slv0_rd_outstanding;
    reg [31:0] slv0_wr_outstanding;
    reg [31:0] slv1_rd_outstanding;
    reg [31:0] slv1_wr_outstanding;

    initial begin
`ifdef ZEBU

        max_txn_outstanding = 512;
        max_wr_outstanding = 512;
        max_rd_outstanding = 512;
`else
	`ifdef VIVADO
	max_txn_outstanding = $value$plusargs("max_txn_outstanding_per_channel=%d");
	if(!max_txn_outstanding) begin
            max_txn_outstanding = 512;
        end
        max_wr_outstanding = $value$plusargs("max_wr_outstanding_per_channel=%d");
        if(!max_wr_outstanding) begin
            max_wr_outstanding = 512;
        end
        max_rd_outstanding = $value$plusargs("max_rd_outstanding_per_channel=%d");
        if(!max_rd_outstanding) begin
            max_rd_outstanding = 512;
        end
	`else
        if(!($value$plusargs("max_txn_outstanding_per_channel=%d", max_txn_outstanding))) begin
            max_txn_outstanding = 512;
        end
        if(!($value$plusargs("max_wr_outstanding_per_channel=%d",  max_wr_outstanding))) begin
            max_wr_outstanding = 512;
        end
        if(!($value$plusargs("max_rd_outstanding_per_channel=%d",  max_rd_outstanding))) begin
            max_rd_outstanding = 512;
        end
	`endif
`endif
    end


    reg mem0_txn_rd_holdoff;
    reg mem1_txn_rd_holdoff;
    reg mem0_txn_wr_holdoff;
    reg mem1_txn_wr_holdoff;
    reg [31:0] slv0_txn_outstanding; 
    reg [31:0] slv1_txn_outstanding;
    reg carry_out0, carry_out1;
    reg [31:0] slv0_outstanding;
    reg [31:0] slv1_outstanding;

    wire mem0_wr_cnt_incr;
    wire mem0_rd_cnt_incr;
    wire mem1_wr_cnt_incr;
    wire mem1_rd_cnt_incr;
    wire mem0_wr_cnt_decr;
    wire mem0_rd_cnt_decr;
    wire mem1_wr_cnt_decr;
    wire mem1_rd_cnt_decr;




    always @(*) begin   
      {carry_out0,slv0_txn_outstanding} = slv0_rd_outstanding + slv0_wr_outstanding;
      {carry_out1,slv1_txn_outstanding} = slv1_rd_outstanding + slv1_wr_outstanding;
    end
       
 
    always @ (negedge mem_clk or negedge reset) begin
        if(!reset) begin
            mem0_txn_wr_holdoff <= 0; 
            mem1_txn_wr_holdoff <= 0; 
            mem0_txn_rd_holdoff <= 0; 
            mem1_txn_rd_holdoff <= 0; 
        end else begin
            mem0_txn_wr_holdoff <= slv0_txn_outstanding >= max_txn_outstanding || slv0_wr_outstanding >= max_wr_outstanding;
            mem1_txn_wr_holdoff <= slv1_txn_outstanding >= max_txn_outstanding || slv1_wr_outstanding >= max_wr_outstanding;
            mem0_txn_rd_holdoff <= slv0_txn_outstanding >= max_txn_outstanding || slv0_rd_outstanding >= max_rd_outstanding;
            mem1_txn_rd_holdoff <= slv1_txn_outstanding >= max_txn_outstanding || slv1_rd_outstanding >= max_rd_outstanding;
        end
    end

    assign mem0_wr_cnt_incr = axi_slave0_awvalid && axi_slave0_awready;
    assign mem0_rd_cnt_incr = axi_slave0_arvalid && axi_slave0_arready;
    assign mem1_wr_cnt_incr = axi_slave1_awvalid && axi_slave1_awready;
    assign mem1_rd_cnt_incr = axi_slave1_arvalid && axi_slave1_arready;
    assign mem0_wr_cnt_decr = axi_slave0_bvalid && axi_slave0_bready; 
    assign mem0_rd_cnt_decr = axi_slave0_rvalid && axi_slave0_rready && axi_slave0_rlast; 
    assign mem1_wr_cnt_decr = axi_slave1_bvalid && axi_slave1_bready; 
    assign mem1_rd_cnt_decr = axi_slave1_rvalid && axi_slave1_rready && axi_slave1_rlast; 

    always @ (posedge mem_clk or negedge reset) begin
        if(!reset) begin
            slv0_rd_outstanding <= 0;
            slv0_wr_outstanding <= 0;
            slv1_rd_outstanding <= 0;
            slv1_wr_outstanding <= 0;
        end else begin
            slv0_rd_outstanding <= (mem0_rd_cnt_incr && !mem0_rd_cnt_decr) ? slv0_rd_outstanding + 1 :
                                   (!mem0_rd_cnt_incr && mem0_rd_cnt_decr) ? slv0_rd_outstanding - 1 :
                                                                             slv0_rd_outstanding;
            slv0_wr_outstanding <= (mem0_wr_cnt_incr && !mem0_wr_cnt_decr) ? slv0_wr_outstanding + 1 :
                                   (!mem0_wr_cnt_incr && mem0_wr_cnt_decr) ? slv0_wr_outstanding - 1 :
                                                                             slv0_wr_outstanding;
            slv1_rd_outstanding <= (mem1_rd_cnt_incr && !mem1_rd_cnt_decr) ? slv1_rd_outstanding + 1 :
                                   (!mem1_rd_cnt_incr && mem1_rd_cnt_decr) ? slv1_rd_outstanding - 1 :
                                                                             slv1_rd_outstanding;
            slv1_wr_outstanding <= (mem1_wr_cnt_incr && !mem1_wr_cnt_decr) ? slv1_wr_outstanding + 1 :
                                   (!mem1_wr_cnt_incr && mem1_wr_cnt_decr) ? slv1_wr_outstanding - 1 :
                                                                             slv1_wr_outstanding;
        end
    end


`ifdef EMU_TB
   bandwidth_mon bw_mon (
   .clk         (mem_clk),
   .event0      (1'b0),
   .event1      (axi_slave0_rvalid && axi_slave0_rready),
   .event2      (axi_slave1_wvalid && axi_slave1_wready),
   .event3      (axi_slave1_rvalid && axi_slave1_rready),
   .holdoff     (mem_holdoff)
   );
`else
   bandwidth_mon bw_mon (
   .clk         (mem_clk),
   .event0      (axi_slave0_wvalid && axi_slave0_wready),
   .event1      (axi_slave0_rvalid && axi_slave0_rready),
   .event2      (axi_slave1_wvalid && axi_slave1_wready),
   .event3      (axi_slave1_rvalid && axi_slave1_rready),
   .holdoff     (mem_holdoff)
   );
`endif

   assert_module a0 (
    .clk		(clk)
    ,.test		(carry_out0 || carry_out1)
   );

 
   bandwidth_throttle mem0_wradr_throttle (
    .clk        (mem_clk),
    .holdoff    (mem0_txn_wr_holdoff),
    .valid_in   (axi_slave0_awvalid),
    .ready_out  (axi_slave0_awready),

    .valid_out  (axi_slave0_awvalid_vip),
    .ready_in   (axi_slave0_awready_vip)
   );

   bandwidth_throttle mem1_wradr_throttle (
    .clk        (mem_clk),
    .holdoff    (mem1_txn_wr_holdoff),
    .valid_in   (axi_slave1_awvalid),
    .ready_out  (axi_slave1_awready),

    .valid_out  (axi_slave1_awvalid_vip),
    .ready_in   (axi_slave1_awready_vip)
   );

    bandwidth_throttle mem0_rdadr_throttle (
    .clk        (mem_clk),
    .holdoff    (mem0_txn_rd_holdoff),
    .valid_in   (axi_slave0_arvalid),
    .ready_out  (axi_slave0_arready),

    .valid_out  (axi_slave0_arvalid_vip),
    .ready_in   (axi_slave0_arready_vip)
   );

   bandwidth_throttle mem1_rdadr_throttle (
    .clk        (mem_clk),
    .holdoff    (mem1_txn_rd_holdoff),
    .valid_in   (axi_slave1_arvalid),
    .ready_out  (axi_slave1_arready),

    .valid_out  (axi_slave1_arvalid_vip),
    .ready_in   (axi_slave1_arready_vip)
   );

   bandwidth_throttle mem0_wr_bw_mon (
    .clk        (mem_clk),
    .holdoff    (mem_holdoff),
    .valid_in   (axi_slave0_wvalid),
    .ready_out  (axi_slave0_wready),

    .valid_out  (axi_slave0_wvalid_vip),
    .ready_in   (axi_slave0_wready_vip)
   );
   bandwidth_throttle mem1_wr_bw_mon (
    .clk        (mem_clk),
    .holdoff    (mem_holdoff),
    .valid_in   (axi_slave1_wvalid),
    .ready_out  (axi_slave1_wready),

    .valid_out  (axi_slave1_wvalid_vip),
    .ready_in   (axi_slave1_wready_vip)
   );
   bandwidth_throttle mem0_rd_bw_mon (
    .clk        (mem_clk),
    .holdoff    (mem_holdoff),
    .valid_out  (axi_slave0_rvalid),
    .ready_in   (axi_slave0_rready),

    .valid_in   (axi_slave0_rvalid_vip),
    .ready_out  (axi_slave0_rready_vip)

   );
   bandwidth_throttle mem1_rd_bw_mon (
    .clk        (mem_clk),
    .holdoff    (mem_holdoff),
    .valid_out  (axi_slave1_rvalid),
    .ready_in   (axi_slave1_rready),

    .valid_in   (axi_slave1_rvalid_vip),
    .ready_out  (axi_slave1_rready_vip)
   );





`ifndef ZEBU
`ifndef EMU_TB
initial begin
$dumpfile("bench_pk_pass.vcd");
`ifdef VCS
    $vcdpluson (0,

	top.slave_mem_wrap.axi_slave0,
	top.slave_mem_wrap.axi_slave1,
	top.slave_mem_wrap.dbb_mem,
	top.slave_mem_wrap.cvsram_mem,
	top.mem_clk_gen,top.clk, top.msc_clk_ip, top.reset, top.mem_clk_fast, top.mem_clk);
`endif

end


  `ifdef NO_DUMPS
  `else

    reg [31:0]        dump_start_trans;
    reg [63:0]        dump_start_time;
    reg [63:0]        dump_stop_time;
    reg [(256*8)-1:0] vpd_dump_name;


    `ifndef VIVADO
    string            input_dir, full_saif_filename ;
    `endif

    reg [31:0]        saif_start_trans;
    reg [31:0]        saif_end_trans;


    initial begin




       `ifdef VIVADO
	 vpd_dump_name = $value$plusargs("vpd_dump_name=%s");
         if(!vpd_dump_name)  vpd_dump_name = "vpdplus.vpd";

         dump_start_time = $value$plusargs("dump_start_time=%d");
         if(!dump_start_time)  dump_start_time = 0;
       `else
         if(!$value$plusargs("vpd_dump_name=%s", vpd_dump_name))  vpd_dump_name = "vpdplus.vpd";
         if(!$value$plusargs("dump_start_time=%d", dump_start_time))  dump_start_time = 0;
       `endif

       if ( dump_start_time != 0 ) begin
           #(dump_start_time);
       end
       if ($test$plusargs("dump_vpd") || $test$plusargs("dump_vcd")) begin



	  `ifndef VIVADO
            $vcdplusfile (vpd_dump_name);
            $vcdpluson;
          `endif
        `ifdef WAVES      
          $dumpvars;
        `endif
       end
    end

    reg [(256*8)-1:0] saif_name;
    initial begin
       if ($test$plusargs("dump_saif")) begin

         `ifdef VIVADO
           saif_name = $value$plusargs("saif_name=%s");
           if(!saif_name)  saif_name = "out.saif";

           saif_start_trans = $value$plusargs("saif_start_trans=%d");
           if(!saif_start_trans)  saif_start_trans = 0;

           saif_end_trans = $value$plusargs("saif_end_trans=%d");
           if(!saif_end_trans)  saif_end_trans = 9999999;
	 `else
           if(!$value$plusargs("saif_name=%s", saif_name))  saif_name = "out.saif";
           if(!$value$plusargs("saif_start_trans=%d", saif_start_trans))  saif_start_trans = 0;
           if(!$value$plusargs("saif_end_trans=%d", saif_end_trans))  saif_end_trans = 9999999;
	 `endif

         $display( "(%0d) NVDLA_IP_INFO : monitoring with rtl_on for saif", $stime );
	 `ifndef VIVADO
           $set_gate_level_monitoring("rtl_on");
         `endif
         $display( "(%0d) NVDLA_IP_INFO : setting toggle region for saif", $stime );
	 `ifndef VIVADO
           $set_toggle_region("nvdla_top");
         `endif


         if ( saif_start_trans != 0 ) begin
           $display( "(%0d) NVDLA_IP_INFO : saif_start_trans enabled in file %0s", $stime, saif_name );
           wait (trans_count !== {32{1'bx}});
           $display( "(%0d) NVDLA_IP_INFO : start waiting for saif trans_count == %d", $stime, saif_start_trans );
           wait (trans_count >= saif_start_trans);
           $display( "(%0d) NVDLA_IP_INFO : starting saif, trans_count == %d", $stime, trans_count );
         end

	 `ifndef VIVADO
           #10 $toggle_start;
	 `endif
         $display( "(%0d) NVDLA_IP_INFO : toggle start for saif", $stime );

         if ( saif_end_trans != 0 ) begin
           $display( "(%0d) NVDLA_IP_INFO : saif_end_trans enabled in file %0s", $stime, saif_name );
           wait (trans_count !== {32{1'bx}});
           $display( "(%0d) NVDLA_IP_INFO : end waiting for trans_count == %d", $stime, saif_end_trans );
           wait (trans_count >= saif_end_trans);
           $display( "(%0d) NVDLA_IP_INFO : ending saif, trans_count == %d", $stime, trans_count );

	   `ifndef VIVADO
             $toggle_stop;
	   `endif
           #10;




`ifndef VIVADO
           if($value$plusargs("input_dir=%s", input_dir)) begin
            if ($test$plusargs("dump_smm_saif")) begin
             full_saif_filename = $psprintf("%0s/smm0.snps.saif",input_dir);
             $display( "(%0d) NVDLA_IP_INFO : creating toggle report for smmmio (%0s)", $stime, full_saif_filename );

            end
            if ($test$plusargs("dump_top_saif")) begin
             full_saif_filename = $psprintf("%0s/top0.snps.saif",input_dir);


            end
           end
`endif
         end

       end
    end


    reg [(256*8)-1:0] dump_name;
    reg [(256*8)-1:0] dump_cone;
    reg [(256*8)-1:0] esa_path;
    reg [(256*8)-1:0] tb_dir;
    integer           esa_fhandle;

    initial begin
       if(!$value$plusargs("dump_name=%s", dump_name))  dump_name = "debussy.fsdb";
       if(!$value$plusargs("dump_start_time=%d", dump_start_time))  dump_start_time = 1;
       if(!$value$plusargs("dump_start_trans=%d", dump_start_trans))  dump_start_trans = 0;
       dump_stop_time = 0;
       
       if ( dump_start_time != 0 ) begin
           #(dump_start_time);
       end
       if ( dump_start_trans != 0 ) begin
           $display( "(%0d) NVDLA_IP_INFO : dump_start_trans enabled in file %0s", $stime, dump_name );
           wait (trans_count !== {32{1'bx}});
           $display( "(%0d) NVDLA_IP_INFO : waiting for trans_count == %d", $stime, dump_start_trans );
           wait (trans_count >= dump_start_trans);
           $display( "(%0d) NVDLA_IP_INFO : starting fsdb dump, trans_count == %d", $stime, trans_count );
       end
       if ( $test$plusargs("dump_fsdb") || $test$plusargs("fsdb_dump")) begin
              $display( "(%0d) NVDLA_IP_INFO : Turning on fsdb dump to file %0s", $stime, dump_name );
             `ifdef VERILINT
             `else
             `endif
	      `ifndef VIVADO
                $fsdbAutoSwitchDumpfile( 1000, dump_name, 20 );
                $fsdbDumpvars("level=",0,top);
	      `endif





              #1;
              $display( "(%0d) NVDLA_IP_INFO : fsdb dumping enabled. %0s", $stime, dump_name );
       end

    end
  `endif
`endif
`endif

endmodule