data/full_repos/permissive/415103295/verilog/synth/fwvexrisc_rv32im_i4k_d4k_wb/fwvexrisc_rv32im_i4k_d4k_wb_top.v
1: b'%Error: data/full_repos/permissive/415103295/verilog/synth/fwvexrisc_rv32im_i4k_d4k_wb/fwvexrisc_rv32im_i4k_d4k_wb_top.v:4: Cannot find include file: wishbone_macros.svh\n`include "wishbone_macros.svh" \n         ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/415103295/verilog/synth/fwvexrisc_rv32im_i4k_d4k_wb,data/full_repos/permissive/415103295/wishbone_macros.svh\n             data/full_repos/permissive/415103295/verilog/synth/fwvexrisc_rv32im_i4k_d4k_wb,data/full_repos/permissive/415103295/wishbone_macros.svh.v\n             data/full_repos/permissive/415103295/verilog/synth/fwvexrisc_rv32im_i4k_d4k_wb,data/full_repos/permissive/415103295/wishbone_macros.svh.sv\n             wishbone_macros.svh\n             wishbone_macros.svh.v\n             wishbone_macros.svh.sv\n             obj_dir/wishbone_macros.svh\n             obj_dir/wishbone_macros.svh.v\n             obj_dir/wishbone_macros.svh.sv\n%Error: data/full_repos/permissive/415103295/verilog/synth/fwvexrisc_rv32im_i4k_d4k_wb/fwvexrisc_rv32im_i4k_d4k_wb_top.v:17: Define or directive not defined: \'`WB_WIRES\'\n `WB_WIRES(c2s_, 32, 32);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/415103295/verilog/synth/fwvexrisc_rv32im_i4k_d4k_wb/fwvexrisc_rv32im_i4k_d4k_wb_top.v:17: syntax error, unexpected \'(\'\n `WB_WIRES(c2s_, 32, 32);\n           ^~~~\n%Error: data/full_repos/permissive/415103295/verilog/synth/fwvexrisc_rv32im_i4k_d4k_wb/fwvexrisc_rv32im_i4k_d4k_wb_top.v:24: Define or directive not defined: \'`WB_CONNECT\'\n   `WB_CONNECT(i_, c2s_),\n   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/415103295/verilog/synth/fwvexrisc_rv32im_i4k_d4k_wb/fwvexrisc_rv32im_i4k_d4k_wb_top.v:24: syntax error, unexpected \',\'\n   `WB_CONNECT(i_, c2s_),\n                 ^\n%Error: data/full_repos/permissive/415103295/verilog/synth/fwvexrisc_rv32im_i4k_d4k_wb/fwvexrisc_rv32im_i4k_d4k_wb_top.v:34: Define or directive not defined: \'`WB_CONNECT\'\n   `WB_CONNECT(i_, c2s_)\n   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/415103295/verilog/synth/fwvexrisc_rv32im_i4k_d4k_wb/fwvexrisc_rv32im_i4k_d4k_wb_top.v:34: syntax error, unexpected \',\'\n   `WB_CONNECT(i_, c2s_)\n                 ^\n%Error: Exiting due to 7 error(s)\n'
module fwvexrisc_rv32im_i4k_d4k_wb_top(
		input 			clock,
		input 			reset,
		input 			irq,
		output[31:0]	dat_w);
	
	`WB_WIRES(c2s_, 32, 32);
	
	assign dat_w = c2s_dat_w;
	
	fwvexrisc_rv32im_i4k_d4k_wb u_core(
			.clock(			clock),
			.reset(			reset),
			`WB_CONNECT(i_, c2s_),
			.irq(			irq)
			);	

	wb_target_synth_stub #(
			.ADDR_WIDTH(32),
			.DATA_WIDTH(32)
			) u_stub (
			.clock(			clock),
			.reset(			reset),
			`WB_CONNECT(i_, c2s_)
			);


endmodule
module fwvexrisc_rv32im_i4k_d4k_wb_top(
		input 			clock,
		input 			reset,
		input 			irq,
		output[31:0]	dat_w);

	
	`WB_WIRES(c2s_, 32, 32);
	
	assign dat_w = c2s_dat_w;
	
	fwvexrisc_rv32im_i4k_d4k_wb u_core(
			.clock(			clock),
			.reset(			reset),
			`WB_CONNECT(i_, c2s_),
			.irq(			irq)
			);	

	wb_target_synth_stub #(
			.ADDR_WIDTH(32),
			.DATA_WIDTH(32)
			) u_stub (
			.clock(			clock),
			.reset(			reset),
			`WB_CONNECT(i_, c2s_)
			);


endmodule