data/full_repos/permissive/419538859/lab7/18/m18.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/419538859/lab7/18/m18.v:71: Cell has missing pin: \'column_green\'\nrom_char_yellow M18(idx_cnt, column_out_yellow);\n                ^~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab7/18/m18.v:380: Operator ADD expects 7 bits on the RHS, but RHS\'s VARREF \'cnt\' generates 3 bits.\n                                                                      : ... In instance m18.M20.M17\n  idx_cnt = idx+cnt;   \n               ^\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab7/18/m18.v:83: Output port connection \'idx\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'idx\' generates 8 bits.\n                                                                     : ... In instance m18.M16\nidx_gen    M13(clk_shift, rst, idx); \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab7/18/m18.v:84: Input port connection \'idx\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'idx\' generates 8 bits.\n                                                                     : ... In instance m18.M16\nrow_gen    M14(clk_scan, rst, idx, row, idx_cnt);\n                              ^~~\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab7/18/m18.v:84: Output port connection \'idx_cnt\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'idx_cnt\' generates 8 bits.\n                                                                     : ... In instance m18.M16\nrow_gen    M14(clk_scan, rst, idx, row, idx_cnt);\n                                        ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab7/18/m18.v:85: Input port connection \'addr\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'idx_cnt\' generates 8 bits.\n                                                                     : ... In instance m18.M16\nrom_char_green  M15(idx_cnt, column_out_green);\n                    ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab7/18/m18.v:69: Output port connection \'idx\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'idx\' generates 8 bits.\n                                                                     : ... In instance m18.M20\nidx_gen    M19(clk_shift, rst, idx); \n                               ^~~\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab7/18/m18.v:70: Input port connection \'idx\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'idx\' generates 8 bits.\n                                                                     : ... In instance m18.M20\nrow_gen    M17(clk_scan, rst, idx, row, idx_cnt);\n                              ^~~\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab7/18/m18.v:70: Output port connection \'idx_cnt\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'idx_cnt\' generates 8 bits.\n                                                                     : ... In instance m18.M20\nrow_gen    M17(clk_scan, rst, idx, row, idx_cnt);\n                                        ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab7/18/m18.v:71: Input port connection \'addr\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'idx_cnt\' generates 8 bits.\n                                                                     : ... In instance m18.M20\nrom_char_yellow M18(idx_cnt, column_out_yellow);\n                    ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab7/18/m18.v:55: Output port connection \'idx\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'idx\' generates 8 bits.\n                                                                     : ... In instance m18.M9\nidx_gen   M10(clk_shift, rst, idx); \n                              ^~~\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab7/18/m18.v:56: Input port connection \'idx\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'idx\' generates 8 bits.\n                                                                     : ... In instance m18.M9\nrow_gen    M11(clk_scan, rst, idx, row, idx_cnt);\n                              ^~~\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab7/18/m18.v:56: Output port connection \'idx_cnt\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'idx_cnt\' generates 8 bits.\n                                                                     : ... In instance m18.M9\nrow_gen    M11(clk_scan, rst, idx, row, idx_cnt);\n                                        ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab7/18/m18.v:57: Input port connection \'addr\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'idx_cnt\' generates 8 bits.\n                                                                     : ... In instance m18.M9\nrom_char_red  M12(idx_cnt, column_out_red);\n                  ^~~~~~~\n%Error: Exiting due to 14 warning(s)\n'
module lab1016_green(clk_shift,clk_scan, rst, row, column_out_green);

input clk_shift,clk_scan,rst;
output[7:0] row, column_out_green;
wire[7:0] idx, idx_cnt;

idx_gen  		M13(clk_shift, rst, idx); 
row_gen  		M14(clk_scan, rst, idx, row, idx_cnt);
rom_char_green  M15(idx_cnt, column_out_green);

endmodule
module lab1016_green(clk_shift,clk_scan, rst, row, column_out_green);


input clk_shift,clk_scan,rst;
output[7:0] row, column_out_green;
wire[7:0] idx, idx_cnt;

idx_gen  		M13(clk_shift, rst, idx); 
row_gen  		M14(clk_scan, rst, idx, row, idx_cnt);
rom_char_green  M15(idx_cnt, column_out_green);

endmodule