data/full_repos/permissive/484799296/verilog/fetch/top_tb.v
1: b'%Error: data/full_repos/permissive/484799296/verilog/fetch/top_tb.v:18: Unsupported or unknown PLI call: $monitor\n        $monitor("%d\\t%d\\t%d\\t%h\\t%h\\t", clk, enabled, reset, in_data, out_data);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/fetch/top_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #1 enabled=0; reset=0; in_data=8\'h3f;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/fetch/top_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #4 enabled=1; reset=0; in_data=8\'ha2;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/fetch/top_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #4 enabled=1; reset=0; in_data=8\'h34;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/fetch/top_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #4 enabled=1; reset=1; in_data=8\'h83;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/fetch/top_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #4 $finish;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/fetch/top_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #2 clk = ~clk;\n        ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();

    reg clk;
    reg enabled;
    reg reset;
    reg [7:0] in_data;
    wire [7:0] out_data;

    fetch Fetch(clk, enabled, reset, in_data, out_data);

    initial begin
        clk=0;
        enabled=0; reset=0; in_data=0;

        $display("clk\tenabled\treset\tin_data\tout_data");
        $monitor("%d\t%d\t%d\t%h\t%h\t", clk, enabled, reset, in_data, out_data);

        #1 enabled=0; reset=0; in_data=8'h3f;
        #4 enabled=1; reset=0; in_data=8'ha2;
        #4 enabled=1; reset=0; in_data=8'h34;
        #4 enabled=1; reset=1; in_data=8'h83;
        #4 $finish;
    end

    always begin
        #2 clk = ~clk;
    end


endmodule
module testbench();


    reg clk;
    reg enabled;
    reg reset;
    reg [7:0] in_data;
    wire [7:0] out_data;

    fetch Fetch(clk, enabled, reset, in_data, out_data);

    initial begin
        clk=0;
        enabled=0; reset=0; in_data=0;

        $display("clk\tenabled\treset\tin_data\tout_data");
        $monitor("%d\t%d\t%d\t%h\t%h\t", clk, enabled, reset, in_data, out_data);

        #1 enabled=0; reset=0; in_data=8'h3f;
        #4 enabled=1; reset=0; in_data=8'ha2;
        #4 enabled=1; reset=0; in_data=8'h34;
        #4 enabled=1; reset=1; in_data=8'h83;
        #4 $finish;
    end

    always begin
        #2 clk = ~clk;
    end


endmodule