data/full_repos/permissive/441359809/src/yosys/tests/opt/opt_rmdff_sat.v
data/verilator_xmls/87fd8c01-d4a8-41a4-89f0-46f7328b17fb.xml
module top (
	input clk,
	output reg [7:0] cnt
);
	initial cnt = 0;
	always @(posedge clk) begin
		if (cnt < 20)
			cnt <= cnt + 1;
		else
			cnt <= 0;
	end
endmodule
module top (
	input clk,
	output reg [7:0] cnt
);

	initial cnt = 0;
	always @(posedge clk) begin
		if (cnt < 20)
			cnt <= cnt + 1;
		else
			cnt <= 0;
	end
endmodule