data/full_repos/permissive/491022697/verilog/rtl/yonga_can_controller.v
data/verilator_xmls/7424074d-515d-4d47-b25f-db9ef41dd5bb.xml
module yonga_can_controller(
    input	wire	i_controller_clk,
    input  	wire 	i_controller_rst,

	input  	wire 	i_pulse_gen_synced,
    input  	wire 	i_packetizer_rdy,
    input  	wire   	i_ack_slot,
	output 	reg  	o_packetizer_en,
    output 	reg  	o_pulse_gen_en,
		
	input  	wire 	i_packetizer_message_bit,
	input  	wire   	i_message_bit,
	output 	reg   	o_message_bit,

	input  	wire	i_drive_pulse,
	input  	wire	i_sample_pulse,

	input  	wire	i_config_enable,
	input  	wire	i_sys_ctrl_sts_send,
	output 	reg 	[2:0] o_sts_code
);

	parameter STATE_IDLE = 0, STATE_SYNC = 1 , STATE_DRIVE_DATA = 2, STATE_SAMPLE_DATA = 3, STATE_UPDATE_STS = 4;

  	reg [2:0] state_reg;
	reg bit_transmitted;

	always @(posedge i_controller_clk) begin
  		if(i_controller_rst) begin
      		state_reg <= STATE_IDLE;
      		o_packetizer_en <= 1'b0;
      		o_pulse_gen_en <= 1'b0;
			o_sts_code <= 3'b0;
			o_message_bit <= 1'b1;
    	end
    	else begin
      		case(state_reg)
        		
        		STATE_IDLE: begin
					o_sts_code <= 3'b0;
					o_message_bit <= 1'b1;
          			if((i_config_enable == 0) && (i_sys_ctrl_sts_send == 1)) begin
            			state_reg <= STATE_SYNC;
						o_pulse_gen_en <= 1'b1;
					end
          		end
        		
        		STATE_SYNC: begin
          			if(i_pulse_gen_synced) begin
            			o_packetizer_en <= 1'b1;
						if(i_drive_pulse == 1)
						state_reg <= STATE_DRIVE_DATA;
						
          			end
          		end
				
				STATE_DRIVE_DATA: begin
					if(i_drive_pulse == 1) begin
						state_reg <= STATE_SAMPLE_DATA;
						bit_transmitted <= i_packetizer_message_bit;
						o_message_bit <= i_packetizer_message_bit;
					end
				end
		
				STATE_SAMPLE_DATA: begin
					if(i_sample_pulse == 1) begin
						if(bit_transmitted == i_message_bit) begin
							if(i_ack_slot) begin
								o_sts_code <= 3'h3;
								o_packetizer_en <= 0;
								state_reg <= STATE_UPDATE_STS;
							end
							else if(i_packetizer_rdy) begin
								o_packetizer_en <= 0;
								state_reg <= STATE_UPDATE_STS;
							end
							else begin
								state_reg <= STATE_DRIVE_DATA;
							end
						end
						else begin
							if(i_ack_slot == 1) begin
								o_sts_code <= 3'h1;
								state_reg <= STATE_DRIVE_DATA;
							end
							else begin
								o_sts_code <= 3'h2;
								o_packetizer_en <= 0;
								state_reg <= STATE_UPDATE_STS;
							end
						end
					end
				end
		
				STATE_UPDATE_STS: begin
					state_reg <= STATE_IDLE;
				end	
			endcase
    	end
  	end
endmodule
module yonga_can_controller(
    input	wire	i_controller_clk,
    input  	wire 	i_controller_rst,

	input  	wire 	i_pulse_gen_synced,
    input  	wire 	i_packetizer_rdy,
    input  	wire   	i_ack_slot,
	output 	reg  	o_packetizer_en,
    output 	reg  	o_pulse_gen_en,
		
	input  	wire 	i_packetizer_message_bit,
	input  	wire   	i_message_bit,
	output 	reg   	o_message_bit,

	input  	wire	i_drive_pulse,
	input  	wire	i_sample_pulse,

	input  	wire	i_config_enable,
	input  	wire	i_sys_ctrl_sts_send,
	output 	reg 	[2:0] o_sts_code
);


	parameter STATE_IDLE = 0, STATE_SYNC = 1 , STATE_DRIVE_DATA = 2, STATE_SAMPLE_DATA = 3, STATE_UPDATE_STS = 4;

  	reg [2:0] state_reg;
	reg bit_transmitted;

	always @(posedge i_controller_clk) begin
  		if(i_controller_rst) begin
      		state_reg <= STATE_IDLE;
      		o_packetizer_en <= 1'b0;
      		o_pulse_gen_en <= 1'b0;
			o_sts_code <= 3'b0;
			o_message_bit <= 1'b1;
    	end
    	else begin
      		case(state_reg)
        		
        		STATE_IDLE: begin
					o_sts_code <= 3'b0;
					o_message_bit <= 1'b1;
          			if((i_config_enable == 0) && (i_sys_ctrl_sts_send == 1)) begin
            			state_reg <= STATE_SYNC;
						o_pulse_gen_en <= 1'b1;
					end
          		end
        		
        		STATE_SYNC: begin
          			if(i_pulse_gen_synced) begin
            			o_packetizer_en <= 1'b1;
						if(i_drive_pulse == 1)
						state_reg <= STATE_DRIVE_DATA;
						
          			end
          		end
				
				STATE_DRIVE_DATA: begin
					if(i_drive_pulse == 1) begin
						state_reg <= STATE_SAMPLE_DATA;
						bit_transmitted <= i_packetizer_message_bit;
						o_message_bit <= i_packetizer_message_bit;
					end
				end
		
				STATE_SAMPLE_DATA: begin
					if(i_sample_pulse == 1) begin
						if(bit_transmitted == i_message_bit) begin
							if(i_ack_slot) begin
								o_sts_code <= 3'h3;
								o_packetizer_en <= 0;
								state_reg <= STATE_UPDATE_STS;
							end
							else if(i_packetizer_rdy) begin
								o_packetizer_en <= 0;
								state_reg <= STATE_UPDATE_STS;
							end
							else begin
								state_reg <= STATE_DRIVE_DATA;
							end
						end
						else begin
							if(i_ack_slot == 1) begin
								o_sts_code <= 3'h1;
								state_reg <= STATE_DRIVE_DATA;
							end
							else begin
								o_sts_code <= 3'h2;
								o_packetizer_en <= 0;
								state_reg <= STATE_UPDATE_STS;
							end
						end
					end
				end
		
				STATE_UPDATE_STS: begin
					state_reg <= STATE_IDLE;
				end	
			endcase
    	end
  	end
endmodule