data/full_repos/permissive/432564927/Lab4 (Verilog)/Lab4_Unal/Lab4.srcs/sim_1/new/CPU_Test.v
1: b'%Error: Cannot find file containing module: (Verilog)/Lab4_Unal/Lab4.srcs/sim_1/new,data/full_repos/permissive/432564927\n        ... Looked in:\n             data/full_repos/permissive/432564927/Lab4/(Verilog)/Lab4_Unal/Lab4.srcs/sim_1/new,data/full_repos/permissive/432564927\n             data/full_repos/permissive/432564927/Lab4/(Verilog)/Lab4_Unal/Lab4.srcs/sim_1/new,data/full_repos/permissive/432564927.v\n             data/full_repos/permissive/432564927/Lab4/(Verilog)/Lab4_Unal/Lab4.srcs/sim_1/new,data/full_repos/permissive/432564927.sv\n             (Verilog)/Lab4_Unal/Lab4.srcs/sim_1/new,data/full_repos/permissive/432564927\n             (Verilog)/Lab4_Unal/Lab4.srcs/sim_1/new,data/full_repos/permissive/432564927.v\n             (Verilog)/Lab4_Unal/Lab4.srcs/sim_1/new,data/full_repos/permissive/432564927.sv\n             obj_dir/(Verilog)/Lab4_Unal/Lab4.srcs/sim_1/new,data/full_repos/permissive/432564927\n             obj_dir/(Verilog)/Lab4_Unal/Lab4.srcs/sim_1/new,data/full_repos/permissive/432564927.v\n             obj_dir/(Verilog)/Lab4_Unal/Lab4.srcs/sim_1/new,data/full_repos/permissive/432564927.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/432564927/Lab4\n%Error: Cannot find file containing module: (Verilog)/Lab4_Unal/Lab4.srcs/sim_1/new/CPU_Test.v\n%Error: Exiting due to 3 error(s)\n'
module CPU_Test();

    reg clk;
    wire [31:0] pcin, pcout, im_out, if_idout, qawire, qbwire, sign_extendedout,
                eqawire, eqbwire, eimmnext_out, alumux_out, alu_out, e2mALU, qb2DM, dm_out;
    wire [3:0] aluc_out, ealuc_out;
    wire wregwire, m2regwire, wmemwire, aluimmwire, regrtwire, ewregwire, 
         em2regwire, ewmemwire, ealuimmwire, e2mwreg, e2mM2reg, wmemDM;
    wire [4:0] muxwire, emuxwire, e2mMux;
    

    PC PC(clk, pcin, pcout);
    PCAdder adder(pcout, pcin);
    InstructMem instmem(pcout, im_out);
    IFID ifid(clk, im_out, if_idout);
    ControlUnit ctrunit(if_idout, wregwire, m2regwire, wmemwire,
                        aluc_out, aluimmwire, regrtwire);
    ControlMux ctrmux(if_idout, regrtwire, muxwire);
    RegFile regfile(if_idout, qawire, qbwire);
    SignExtend extender(if_idout, sign_extendedout);
    IDEXE idexe(clk, wregwire, m2regwire, wmemwire, aluc_out, aluimmwire, muxwire, qawire, qbwire,
                sign_extendedout, ewregwire, em2regwire, ewmemwire, ealuc_out, ealuimmwire, emuxwire, eqawire, eqbwire, eimmnext_out);
    ALUMux alumux(ealuimmwire, eqbwire, eimmnext_out, alumux_out);
    ALU alu(ealuc_out, eqawire, alumux_out, alu_out);
    EXEMEM exemem(clk, ewregwire, em2regwire, ewmemwire, emuxwire, alu_out, eqbwire, 
                  e2mwreg, e2mM2reg, wmemDM, e2mMux, e2mALU, qb2DM);
    DataMemory datamem(wmemDM, e2mALU, qb2DM, dm_out);
    MemWB memwb(clk, e2mwreg, e2mM2reg, e2mMux, e2mALU, dm_out);
    
    initial begin
        clk = 0;
    end            
    always begin
        #5 clk = !clk;
    end
endmodule
module CPU_Test();


    reg clk;
    wire [31:0] pcin, pcout, im_out, if_idout, qawire, qbwire, sign_extendedout,
                eqawire, eqbwire, eimmnext_out, alumux_out, alu_out, e2mALU, qb2DM, dm_out;
    wire [3:0] aluc_out, ealuc_out;
    wire wregwire, m2regwire, wmemwire, aluimmwire, regrtwire, ewregwire, 
         em2regwire, ewmemwire, ealuimmwire, e2mwreg, e2mM2reg, wmemDM;
    wire [4:0] muxwire, emuxwire, e2mMux;
    

    PC PC(clk, pcin, pcout);
    PCAdder adder(pcout, pcin);
    InstructMem instmem(pcout, im_out);
    IFID ifid(clk, im_out, if_idout);
    ControlUnit ctrunit(if_idout, wregwire, m2regwire, wmemwire,
                        aluc_out, aluimmwire, regrtwire);
    ControlMux ctrmux(if_idout, regrtwire, muxwire);
    RegFile regfile(if_idout, qawire, qbwire);
    SignExtend extender(if_idout, sign_extendedout);
    IDEXE idexe(clk, wregwire, m2regwire, wmemwire, aluc_out, aluimmwire, muxwire, qawire, qbwire,
                sign_extendedout, ewregwire, em2regwire, ewmemwire, ealuc_out, ealuimmwire, emuxwire, eqawire, eqbwire, eimmnext_out);
    ALUMux alumux(ealuimmwire, eqbwire, eimmnext_out, alumux_out);
    ALU alu(ealuc_out, eqawire, alumux_out, alu_out);
    EXEMEM exemem(clk, ewregwire, em2regwire, ewmemwire, emuxwire, alu_out, eqbwire, 
                  e2mwreg, e2mM2reg, wmemDM, e2mMux, e2mALU, qb2DM);
    DataMemory datamem(wmemDM, e2mALU, qb2DM, dm_out);
    MemWB memwb(clk, e2mwreg, e2mM2reg, e2mMux, e2mALU, dm_out);
    
    initial begin
        clk = 0;
    end            
    always begin
        #5 clk = !clk;
    end
endmodule