data/full_repos/permissive/498662723/Circuits/Sequential Logic/Latches and Flip flops/ece241 2014 q4 (DFF and gates).v
1: b'%Error: Cannot find file containing module: Logic/Latches\n        ... Looked in:\n             data/full_repos/permissive/498662723/Circuits/Sequential/Logic/Latches\n             data/full_repos/permissive/498662723/Circuits/Sequential/Logic/Latches.v\n             data/full_repos/permissive/498662723/Circuits/Sequential/Logic/Latches.sv\n             Logic/Latches\n             Logic/Latches.v\n             Logic/Latches.sv\n             obj_dir/Logic/Latches\n             obj_dir/Logic/Latches.v\n             obj_dir/Logic/Latches.sv\n%Error: Cannot find file containing module: and\n%Error: Cannot find file containing module: Flip\n%Error: Cannot find file containing module: flops,data/full_repos/permissive/498662723\n%Error: Cannot find file containing module: data/full_repos/permissive/498662723/Circuits/Sequential\n%Error: Cannot find file containing module: flops/ece241\n%Error: Cannot find file containing module: 2014\n%Error: Cannot find file containing module: q4\n%Error: Cannot find file containing module: (DFF\n%Error: Cannot find file containing module: gates).v\n%Error: Exiting due to 10 error(s)\n'
module top_module (
    input clk,
    input x,
    output z
); 
    wire [2:0]d;
    reg [2:0]q = 3'b000;
    
    assign d[0] = q[0]^x;
    assign d[1] = x&~q[1];
    assign d[2] = x|~q[2];
    flip_flop dff1 (d[0],clk,q[0]);
    flip_flop dff2 (d[1],clk,q[1]);
    flip_flop dff3 (d[2],clk,q[2]);
    assign z = ~(q[0]|q[1]|q[2]);
endmodule
module top_module (
    input clk,
    input x,
    output z
);
 
    wire [2:0]d;
    reg [2:0]q = 3'b000;
    
    assign d[0] = q[0]^x;
    assign d[1] = x&~q[1];
    assign d[2] = x|~q[2];
    flip_flop dff1 (d[0],clk,q[0]);
    flip_flop dff2 (d[1],clk,q[1]);
    flip_flop dff3 (d[2],clk,q[2]);
    assign z = ~(q[0]|q[1]|q[2]);
endmodule