data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_request.v
1: b'%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_request.v:3: Cannot find include file: noc_parameter.vh\n    `include "noc_parameter.vh" \n             ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh\n             data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.v\n             data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.sv\n             noc_parameter.vh\n             noc_parameter.vh.v\n             noc_parameter.vh.sv\n             obj_dir/noc_parameter.vh\n             obj_dir/noc_parameter.vh.v\n             obj_dir/noc_parameter.vh.sv\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_request.v:4: Cannot find include file: tcu_parameter.vh\n    ,`include "tcu_parameter.vh" \n              ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_request.v:4: syntax error, unexpected \',\', expecting \'[\'\n    , \n    ^\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_request.v:6: syntax error, unexpected \')\', expecting \';\'\n)(\n^\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_request.v:8: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          reset_n_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_request.v:10: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          noc_stall_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_request.v:11: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg                           noc_wrreq_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_request.v:12: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output reg       [NOC_DATA_SIZE-1:0] noc_data0_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_request.v:13: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output wire      [NOC_ADDR_SIZE-1:0] noc_addr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_request.v:14: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire    [NOC_CHIPID_SIZE-1:0] noc_chipid_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_request.v:15: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire     [NOC_MODID_SIZE-1:0] noc_modid_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_request.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          noc_rsp_recv_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_request.v:17: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire     [TCU_ERROR_SIZE-1:0] noc_rsp_error_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_request.v:18: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                   [31:0] noc_rsp_size_i,     \n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_request.v:22: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          marq_start_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_request.v:23: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire    [TCU_OPCODE_SIZE-1:0] marq_opcode_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_request.v:24: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                   [31:0] marq_laddr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_request.v:25: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                   [31:0] marq_raddr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_request.v:26: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                   [31:0] marq_size_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_request.v:27: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire    [NOC_CHIPID_SIZE-1:0] marq_chipid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_request.v:28: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire     [NOC_MODID_SIZE-1:0] marq_modid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_request.v:29: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                          marq_abort_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_request.v:30: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                          marq_read_wait_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_request.v:31: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                          marq_active_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_request.v:32: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                          marq_noc_active_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_request.v:33: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                          marq_done_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_request.v:34: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire     [TCU_ERROR_SIZE-1:0] marq_error_o\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_request.v:35: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/463204869/units/tcu/source/rtl/verilog/tcu_ctrl_mem_access_request.v:64: syntax error, unexpected always\n    always @(posedge clk_i) begin\n    ^~~~~~\n%Error: Exiting due to 29 error(s)\n'
module tcu_ctrl_mem_access_request #(
    `include "noc_parameter.vh"
    ,`include "tcu_parameter.vh"
    ,parameter [31:0] TIMEOUT_SEND_CYCLES = 0
)(
    input  wire                          clk_i,
    input  wire                          reset_n_i,

    input  wire                          noc_stall_i,
    output reg                           noc_wrreq_o,
    output reg       [NOC_DATA_SIZE-1:0] noc_data0_o,
    output wire      [NOC_ADDR_SIZE-1:0] noc_addr_o,
    output wire    [NOC_CHIPID_SIZE-1:0] noc_chipid_o,
    output wire     [NOC_MODID_SIZE-1:0] noc_modid_o,
    input  wire                          noc_rsp_recv_i,
    input  wire     [TCU_ERROR_SIZE-1:0] noc_rsp_error_i,
    input  wire                   [31:0] noc_rsp_size_i,
    


    input  wire                          marq_start_i,
    input  wire    [TCU_OPCODE_SIZE-1:0] marq_opcode_i,
    input  wire                   [31:0] marq_laddr_i,
    input  wire                   [31:0] marq_raddr_i,
    input  wire                   [31:0] marq_size_i,
    input  wire    [NOC_CHIPID_SIZE-1:0] marq_chipid_i,
    input  wire     [NOC_MODID_SIZE-1:0] marq_modid_i,
    input  wire                          marq_abort_i,
    output wire                          marq_read_wait_o,
    output wire                          marq_active_o,
    output wire                          marq_noc_active_o,
    output wire                          marq_done_o,
    output wire     [TCU_ERROR_SIZE-1:0] marq_error_o
);

    localparam CTRL_MARQ_STATES_SIZE = 2;
    localparam S_CTRL_MARQ_IDLE      = 2'h0;
    localparam S_CTRL_MARQ_SEND_REQ  = 2'h1;
    localparam S_CTRL_MARQ_WAIT      = 2'h2;
    localparam S_CTRL_MARQ_FINISH    = 2'h3;

    reg [CTRL_MARQ_STATES_SIZE-1:0] ctrl_marq_state, next_ctrl_marq_state;



    reg                [31:0] r_laddr, rin_laddr;
    reg                [31:0] r_size, rin_size;
    reg                [31:0] r_raddr, rin_raddr;
    reg [NOC_CHIPID_SIZE-1:0] r_chipid, rin_chipid;
    reg  [NOC_MODID_SIZE-1:0] r_modid, rin_modid;


    reg [31:0] r_rsp_size, rin_rsp_size;


    reg [TCU_ERROR_SIZE-1:0] r_marq_error, rin_marq_error;


    reg [31:0] r_marq_timeout, rin_marq_timeout;



    always @(posedge clk_i) begin
        if (reset_n_i == 1'b0) begin
            ctrl_marq_state <= S_CTRL_MARQ_IDLE;
            
            r_laddr    <= 32'h0;
            r_raddr    <= 32'h0;
            r_size     <= 32'h0;
            r_chipid   <= {NOC_CHIPID_SIZE{1'b0}};
            r_modid    <= {NOC_MODID_SIZE{1'b0}};

            r_rsp_size <= 32'h0;
            r_marq_error <= {TCU_ERROR_SIZE{1'b0}};
            r_marq_timeout <= 32'h0;
        end
        else begin
            ctrl_marq_state <= next_ctrl_marq_state;
            
            r_laddr    <= rin_laddr;
            r_raddr    <= rin_raddr;
            r_size     <= rin_size;
            r_chipid   <= rin_chipid;
            r_modid    <= rin_modid;

            r_rsp_size <= rin_rsp_size;
            r_marq_error <= rin_marq_error;
            r_marq_timeout <= rin_marq_timeout;
        end
    end






    always @* begin
        next_ctrl_marq_state = ctrl_marq_state;

        rin_rsp_size = r_rsp_size;
        rin_marq_error = r_marq_error;
        rin_marq_timeout = 32'h0;

        noc_wrreq_o = 1'b0;
        noc_data0_o = {NOC_DATA_SIZE{1'b0}};

        rin_laddr = r_laddr;
        rin_size = r_size;
        rin_raddr = r_raddr;
        rin_chipid = r_chipid;
        rin_modid = r_modid;


        case (ctrl_marq_state)



            S_CTRL_MARQ_IDLE: begin
                if (marq_start_i && (marq_opcode_i == TCU_OPCODE_READ)) begin
                    rin_rsp_size = 'h0;
                    rin_marq_error = TCU_ERROR_NONE;
                    
                    rin_laddr  = marq_laddr_i;
                    rin_raddr  = marq_raddr_i;
                    rin_size   = marq_size_i;
                    rin_chipid = marq_chipid_i;
                    rin_modid  = marq_modid_i;

                    next_ctrl_marq_state = S_CTRL_MARQ_SEND_REQ;
                end
            end




            S_CTRL_MARQ_SEND_REQ: begin

                if (marq_abort_i) begin
                    rin_marq_error = TCU_ERROR_ABORT;
                    next_ctrl_marq_state = S_CTRL_MARQ_FINISH;
                end
                else begin
                    noc_wrreq_o = 1'b1;
                    noc_data0_o = {r_size, r_laddr};

                    if (!noc_stall_i) begin

                        next_ctrl_marq_state = S_CTRL_MARQ_WAIT;
                    end
                end
            end



            S_CTRL_MARQ_WAIT: begin

                if (noc_rsp_recv_i) begin

                    if (noc_rsp_error_i == TCU_ERROR_NONE) begin
                        rin_rsp_size = r_rsp_size + noc_rsp_size_i;


                        if (rin_rsp_size >= r_size) begin
                            next_ctrl_marq_state = S_CTRL_MARQ_FINISH;
                        end
                    end
                    else begin
                        rin_marq_error = noc_rsp_error_i;
                        next_ctrl_marq_state = S_CTRL_MARQ_FINISH;
                    end
                end


                else if (TIMEOUT_SEND_CYCLES != 32'h0) begin
                    rin_marq_timeout = r_marq_timeout + 32'd1;
                    if (r_marq_timeout > TIMEOUT_SEND_CYCLES) begin
                        rin_marq_error = TCU_ERROR_TIMEOUT_NOC;
                        next_ctrl_marq_state = S_CTRL_MARQ_FINISH;
                    end
                end
            end


            S_CTRL_MARQ_FINISH: begin
                next_ctrl_marq_state = S_CTRL_MARQ_IDLE;
            end

        endcase
    end




    assign marq_read_wait_o = (ctrl_marq_state == S_CTRL_MARQ_WAIT);
    assign marq_active_o = (ctrl_marq_state != S_CTRL_MARQ_IDLE);
    assign marq_noc_active_o = marq_active_o && (ctrl_marq_state < S_CTRL_MARQ_WAIT);
    assign marq_done_o = (ctrl_marq_state == S_CTRL_MARQ_FINISH);
    assign marq_error_o = r_marq_error;

    assign noc_addr_o = r_raddr;
    assign noc_chipid_o = r_chipid;
    assign noc_modid_o = r_modid;
    

endmodule
module tcu_ctrl_mem_access_request #(
    `include "noc_parameter.vh"
    ,`include "tcu_parameter.vh"
    ,parameter [31:0] TIMEOUT_SEND_CYCLES = 0
)(
    input  wire                          clk_i,
    input  wire                          reset_n_i,

    input  wire                          noc_stall_i,
    output reg                           noc_wrreq_o,
    output reg       [NOC_DATA_SIZE-1:0] noc_data0_o,
    output wire      [NOC_ADDR_SIZE-1:0] noc_addr_o,
    output wire    [NOC_CHIPID_SIZE-1:0] noc_chipid_o,
    output wire     [NOC_MODID_SIZE-1:0] noc_modid_o,
    input  wire                          noc_rsp_recv_i,
    input  wire     [TCU_ERROR_SIZE-1:0] noc_rsp_error_i,
    input  wire                   [31:0] noc_rsp_size_i,
    


    input  wire                          marq_start_i,
    input  wire    [TCU_OPCODE_SIZE-1:0] marq_opcode_i,
    input  wire                   [31:0] marq_laddr_i,
    input  wire                   [31:0] marq_raddr_i,
    input  wire                   [31:0] marq_size_i,
    input  wire    [NOC_CHIPID_SIZE-1:0] marq_chipid_i,
    input  wire     [NOC_MODID_SIZE-1:0] marq_modid_i,
    input  wire                          marq_abort_i,
    output wire                          marq_read_wait_o,
    output wire                          marq_active_o,
    output wire                          marq_noc_active_o,
    output wire                          marq_done_o,
    output wire     [TCU_ERROR_SIZE-1:0] marq_error_o
);


    localparam CTRL_MARQ_STATES_SIZE = 2;
    localparam S_CTRL_MARQ_IDLE      = 2'h0;
    localparam S_CTRL_MARQ_SEND_REQ  = 2'h1;
    localparam S_CTRL_MARQ_WAIT      = 2'h2;
    localparam S_CTRL_MARQ_FINISH    = 2'h3;

    reg [CTRL_MARQ_STATES_SIZE-1:0] ctrl_marq_state, next_ctrl_marq_state;



    reg                [31:0] r_laddr, rin_laddr;
    reg                [31:0] r_size, rin_size;
    reg                [31:0] r_raddr, rin_raddr;
    reg [NOC_CHIPID_SIZE-1:0] r_chipid, rin_chipid;
    reg  [NOC_MODID_SIZE-1:0] r_modid, rin_modid;


    reg [31:0] r_rsp_size, rin_rsp_size;


    reg [TCU_ERROR_SIZE-1:0] r_marq_error, rin_marq_error;


    reg [31:0] r_marq_timeout, rin_marq_timeout;



    always @(posedge clk_i) begin
        if (reset_n_i == 1'b0) begin
            ctrl_marq_state <= S_CTRL_MARQ_IDLE;
            
            r_laddr    <= 32'h0;
            r_raddr    <= 32'h0;
            r_size     <= 32'h0;
            r_chipid   <= {NOC_CHIPID_SIZE{1'b0}};
            r_modid    <= {NOC_MODID_SIZE{1'b0}};

            r_rsp_size <= 32'h0;
            r_marq_error <= {TCU_ERROR_SIZE{1'b0}};
            r_marq_timeout <= 32'h0;
        end
        else begin
            ctrl_marq_state <= next_ctrl_marq_state;
            
            r_laddr    <= rin_laddr;
            r_raddr    <= rin_raddr;
            r_size     <= rin_size;
            r_chipid   <= rin_chipid;
            r_modid    <= rin_modid;

            r_rsp_size <= rin_rsp_size;
            r_marq_error <= rin_marq_error;
            r_marq_timeout <= rin_marq_timeout;
        end
    end






    always @* begin
        next_ctrl_marq_state = ctrl_marq_state;

        rin_rsp_size = r_rsp_size;
        rin_marq_error = r_marq_error;
        rin_marq_timeout = 32'h0;

        noc_wrreq_o = 1'b0;
        noc_data0_o = {NOC_DATA_SIZE{1'b0}};

        rin_laddr = r_laddr;
        rin_size = r_size;
        rin_raddr = r_raddr;
        rin_chipid = r_chipid;
        rin_modid = r_modid;


        case (ctrl_marq_state)



            S_CTRL_MARQ_IDLE: begin
                if (marq_start_i && (marq_opcode_i == TCU_OPCODE_READ)) begin
                    rin_rsp_size = 'h0;
                    rin_marq_error = TCU_ERROR_NONE;
                    
                    rin_laddr  = marq_laddr_i;
                    rin_raddr  = marq_raddr_i;
                    rin_size   = marq_size_i;
                    rin_chipid = marq_chipid_i;
                    rin_modid  = marq_modid_i;

                    next_ctrl_marq_state = S_CTRL_MARQ_SEND_REQ;
                end
            end




            S_CTRL_MARQ_SEND_REQ: begin

                if (marq_abort_i) begin
                    rin_marq_error = TCU_ERROR_ABORT;
                    next_ctrl_marq_state = S_CTRL_MARQ_FINISH;
                end
                else begin
                    noc_wrreq_o = 1'b1;
                    noc_data0_o = {r_size, r_laddr};

                    if (!noc_stall_i) begin

                        next_ctrl_marq_state = S_CTRL_MARQ_WAIT;
                    end
                end
            end



            S_CTRL_MARQ_WAIT: begin

                if (noc_rsp_recv_i) begin

                    if (noc_rsp_error_i == TCU_ERROR_NONE) begin
                        rin_rsp_size = r_rsp_size + noc_rsp_size_i;


                        if (rin_rsp_size >= r_size) begin
                            next_ctrl_marq_state = S_CTRL_MARQ_FINISH;
                        end
                    end
                    else begin
                        rin_marq_error = noc_rsp_error_i;
                        next_ctrl_marq_state = S_CTRL_MARQ_FINISH;
                    end
                end


                else if (TIMEOUT_SEND_CYCLES != 32'h0) begin
                    rin_marq_timeout = r_marq_timeout + 32'd1;
                    if (r_marq_timeout > TIMEOUT_SEND_CYCLES) begin
                        rin_marq_error = TCU_ERROR_TIMEOUT_NOC;
                        next_ctrl_marq_state = S_CTRL_MARQ_FINISH;
                    end
                end
            end


            S_CTRL_MARQ_FINISH: begin
                next_ctrl_marq_state = S_CTRL_MARQ_IDLE;
            end

        endcase
    end




    assign marq_read_wait_o = (ctrl_marq_state == S_CTRL_MARQ_WAIT);
    assign marq_active_o = (ctrl_marq_state != S_CTRL_MARQ_IDLE);
    assign marq_noc_active_o = marq_active_o && (ctrl_marq_state < S_CTRL_MARQ_WAIT);
    assign marq_done_o = (ctrl_marq_state == S_CTRL_MARQ_FINISH);
    assign marq_error_o = r_marq_error;

    assign noc_addr_o = r_raddr;
    assign noc_chipid_o = r_chipid;
    assign noc_modid_o = r_modid;
    

endmodule