data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/custom_gen/custom_gen_counter.v
data/verilator_xmls/c1f3ad63-0f42-4dc1-a39e-7e6c2d5c0af8.xml
module custom_gen_counter
#(
	parameter DATA_WIDTH = 5
)
(
	input clk,
	input en,
	output [DATA_WIDTH - 1:0] count
);

	reg [DATA_WIDTH - 1:0] int_count = {DATA_WIDTH{1'b0}};

	always @(posedge clk)
	begin
		if(!en)
		begin
			int_count = 0;
		end
		else
		begin
			int_count = int_count + 1;
		end
	end

	assign count = int_count;
endmodule
module custom_gen_counter
#(
	parameter DATA_WIDTH = 5
)
(
	input clk,
	input en,
	output [DATA_WIDTH - 1:0] count
);


	reg [DATA_WIDTH - 1:0] int_count = {DATA_WIDTH{1'b0}};

	always @(posedge clk)
	begin
		if(!en)
		begin
			int_count = 0;
		end
		else
		begin
			int_count = int_count + 1;
		end
	end

	assign count = int_count;
endmodule