data/full_repos/permissive/484799296/verilog/buffer_tri/top_tb.v
1: b'%Error: data/full_repos/permissive/484799296/verilog/buffer_tri/top_tb.v:14: Unsupported or unknown PLI call: $monitor\n        $monitor("%b\\t%b\\t%b\\t", enable, in, out);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/buffer_tri/top_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=0; in=4\'b0101;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/buffer_tri/top_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=1; in=4\'b0101;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/484799296/verilog/buffer_tri/top_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #2 enable=1; in=4\'b1010;\n        ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();

    reg enable;
    reg [3:0] in;
    wire [3:0] out;

    buffer_tri BUFFER(enable, in, out);

    initial begin

        $display("enable\tin\tout");
        $monitor("%b\t%b\t%b\t", enable, in, out);

           enable=0; in=0;

        #2 enable=0; in=4'b0101;
        #2 enable=1; in=4'b0101;
        #2 enable=1; in=4'b1010;


    end

endmodule
module testbench();


    reg enable;
    reg [3:0] in;
    wire [3:0] out;

    buffer_tri BUFFER(enable, in, out);

    initial begin

        $display("enable\tin\tout");
        $monitor("%b\t%b\t%b\t", enable, in, out);

           enable=0; in=0;

        #2 enable=0; in=4'b0101;
        #2 enable=1; in=4'b0101;
        #2 enable=1; in=4'b1010;


    end

endmodule