data/full_repos/permissive/446312960/Verilog_Simulation/14_fsm_rtl/LIGHT.v
data/verilator_xmls/105ec086-c89a-465c-9db4-4b736a3d55bb.xml
module LIGHT(   CLK, RESETB,
                TA, TB, 
                LA1, LA0,
                LB1, LB0
);

input CLK, RESETB, TA, TB;

output LA1;
output LA0;
wire   [1:0] LA;
assign LA1 = LA[1];
assign LA0 = LA[0];


output LB1;
output LB0;
wire   [1:0] LB;
assign LB1 = LB[1];
assign LB0 = LB[0];


reg     [1:0]   S;
reg     [1:0]   NEXT_S;




always @ ( TA or TB or S )
        case ( S )
        `S0 :
            if( ~TA )
                NEXT_S  <= `S1;
            else
                NEXT_S  <= S;
        `S1 :
            NEXT_S  <= `S2;
        `S2 :
            if ( ~TB )
                NEXT_S  <= `S3;
            else  
                NEXT_S  <= S;
        `S3 :
            NEXT_S  <= `S0;
        
        endcase


always @( negedge RESETB or posedge CLK)
    if (~RESETB)
        S <= 2'b00;
    else
        S <= NEXT_S;






assign LA = S == `S0 ? `G:
            S == `S1 ? `Y:
            S == `S2 ? `R:
            S == `S3 ? `R: `G;

assign LB = S == `S0 ? `R:
            S == `S1 ? `R:
            S == `S2 ? `G:
            S == `S3 ? `Y: `R;

endmodule
module LIGHT(   CLK, RESETB,
                TA, TB, 
                LA1, LA0,
                LB1, LB0
);


input CLK, RESETB, TA, TB;

output LA1;
output LA0;
wire   [1:0] LA;
assign LA1 = LA[1];
assign LA0 = LA[0];


output LB1;
output LB0;
wire   [1:0] LB;
assign LB1 = LB[1];
assign LB0 = LB[0];


reg     [1:0]   S;
reg     [1:0]   NEXT_S;




always @ ( TA or TB or S )
        case ( S )
        `S0 :
            if( ~TA )
                NEXT_S  <= `S1;
            else
                NEXT_S  <= S;
        `S1 :
            NEXT_S  <= `S2;
        `S2 :
            if ( ~TB )
                NEXT_S  <= `S3;
            else  
                NEXT_S  <= S;
        `S3 :
            NEXT_S  <= `S0;
        
        endcase


always @( negedge RESETB or posedge CLK)
    if (~RESETB)
        S <= 2'b00;
    else
        S <= NEXT_S;






assign LA = S == `S0 ? `G:
            S == `S1 ? `Y:
            S == `S2 ? `R:
            S == `S3 ? `R: `G;

assign LB = S == `S0 ? `R:
            S == `S1 ? `R:
            S == `S2 ? `G:
            S == `S3 ? `Y: `R;

endmodule