data/full_repos/permissive/465239880/RTL/and_gate.v
data/verilator_xmls/d994d29c-d391-4dd9-9674-11bb2694429c.xml
module and_gate(
    input in_1,
    input in_2,
    output out_and
    );
assign out_and = in_1 & in_2 ;

endmodule
module and_gate(
    input in_1,
    input in_2,
    output out_and
    );

assign out_and = in_1 & in_2 ;

endmodule