data/full_repos/permissive/41989639/american_put_cyclone/src/DE2_70_Default.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/41989639/american_put_cyclone/src/DE2_70_Default.v:456: Signal definition not found, creating implicitly: \'FL_DQ\'\n                                                                                                    : ... Suggested alternative: \'FLASH_DQ\'\nassign FL_DQ  = 8\'hzz;\n       ^~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/41989639/american_put_cyclone/src/DE2_70_Default.v:458: Signal definition not found, creating implicitly: \'OTG_DATA\'\n                                                                                                    : ... Suggested alternative: \'OTG_D\'\nassign OTG_DATA = 16\'hzzzz;\n       ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/41989639/american_put_cyclone/src/DE2_70_Default.v:460: Signal definition not found, creating implicitly: \'ENET_DATA\'\n                                                                                                    : ... Suggested alternative: \'ENET_D\'\nassign ENET_DATA = 16\'hzzzz;\n       ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/41989639/american_put_cyclone/src/DE2_70_Default.v:475: Signal definition not found, creating implicitly: \'PS2_DAT\'\n                                                                                                    : ... Suggested alternative: \'PS2_KBDAT\'\nassign PS2_DAT    = 1\'bz;        \n       ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/41989639/american_put_cyclone/src/DE2_70_Default.v:476: Signal definition not found, creating implicitly: \'PS2_CLK\'\n                                                                                                    : ... Suggested alternative: \'PS2_KBCLK\'\nassign PS2_CLK    = 1\'bz;           \n       ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/41989639/american_put_cyclone/src/DE2_70_Default.v:455: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'bzzzzzzzzzzzzzzzz\' generates 16 bits.\n                                                                                                 : ... In instance DE2_70_Default\nassign DRAM_DQ  = 16\'hzzzz;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/41989639/american_put_cyclone/src/DE2_70_Default.v:456: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'bzzzzzzzz\' generates 8 bits.\n                                                                                                 : ... In instance DE2_70_Default\nassign FL_DQ  = 8\'hzz;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/41989639/american_put_cyclone/src/DE2_70_Default.v:457: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'bzzzzzzzzzzzzzzzz\' generates 16 bits.\n                                                                                                 : ... In instance DE2_70_Default\nassign SRAM_DQ  = 16\'hzzzz;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/41989639/american_put_cyclone/src/DE2_70_Default.v:458: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'bzzzzzzzzzzzzzzzz\' generates 16 bits.\n                                                                                                 : ... In instance DE2_70_Default\nassign OTG_DATA = 16\'hzzzz;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/41989639/american_put_cyclone/src/DE2_70_Default.v:460: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'bzzzzzzzzzzzzzzzz\' generates 16 bits.\n                                                                                                 : ... In instance DE2_70_Default\nassign ENET_DATA = 16\'hzzzz;\n                 ^\n%Error: data/full_repos/permissive/41989639/american_put_cyclone/src/DE2_70_Default.v:498: Cannot find file containing module: \'Reset_Delay\'\nReset_Delay   r0 ( .iCLK(iCLK_50),.oRESET(DLY_RST) );\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/41989639/american_put_cyclone/src,data/full_repos/permissive/41989639/Reset_Delay\n             data/full_repos/permissive/41989639/american_put_cyclone/src,data/full_repos/permissive/41989639/Reset_Delay.v\n             data/full_repos/permissive/41989639/american_put_cyclone/src,data/full_repos/permissive/41989639/Reset_Delay.sv\n             Reset_Delay\n             Reset_Delay.v\n             Reset_Delay.sv\n             obj_dir/Reset_Delay\n             obj_dir/Reset_Delay.v\n             obj_dir/Reset_Delay.sv\n%Error: data/full_repos/permissive/41989639/american_put_cyclone/src/DE2_70_Default.v:502: Cannot find file containing module: \'flash_default_tester\'\nflash_default_tester flash1(\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/41989639/american_put_cyclone/src/DE2_70_Default.v:539: Cannot find file containing module: \'LCD_TEST\'\nLCD_TEST    u5 (  \n^~~~~~~~\n%Error: data/full_repos/permissive/41989639/american_put_cyclone/src/DE2_70_Default.v:556: Cannot find file containing module: \'SEG7_LUT_8\'\nSEG7_LUT_8    u0 ( .oSEG0(oHEX0_D),\n^~~~~~~~~~\n%Error: data/full_repos/permissive/41989639/american_put_cyclone/src/DE2_70_Default.v:580: Cannot find file containing module: \'amer_put\'\namer_put i1(\n^~~~~~~~\n%Error: Exiting due to 5 error(s), 10 warning(s)\n'
module DE2_70_Default
	(

		iCLK_28,
		iCLK_50,
		iCLK_50_2,
		iCLK_50_3,
		iCLK_50_4,
		iEXT_CLOCK,

		iKEY,

		iSW,

		oHEX0_D,
		oHEX0_DP,
		oHEX1_D,
		oHEX1_DP,
		oHEX2_D,
		oHEX2_DP,
		oHEX3_D,
		oHEX3_DP,
		oHEX4_D,
		oHEX4_DP,
		oHEX5_D,
		oHEX5_DP,
		oHEX6_D,
		oHEX6_DP,
		oHEX7_D,
		oHEX7_DP,

		oLEDG,
		oLEDR,

		oUART_TXD,
		iUART_RXD,
		oUART_CTS,
		iUART_RTS,

		oIRDA_TXD,
		iIRDA_RXD,

		DRAM_DQ,
		oDRAM0_A,
		oDRAM1_A,
		oDRAM0_LDQM0,
		oDRAM1_LDQM0,
		oDRAM0_UDQM1,
		oDRAM1_UDQM1,
		oDRAM0_WE_N,
		oDRAM1_WE_N,
		oDRAM0_CAS_N,
		oDRAM1_CAS_N,
		oDRAM0_RAS_N,
		oDRAM1_RAS_N,
		oDRAM0_CS_N,
		oDRAM1_CS_N,
		oDRAM0_BA,
		oDRAM1_BA,
		oDRAM0_CLK,
		oDRAM1_CLK,
		oDRAM0_CKE,
		oDRAM1_CKE,

		FLASH_DQ,
		FLASH_DQ15_AM1,
		oFLASH_A,
		oFLASH_WE_N,
		oFLASH_RST_N,
		oFLASH_WP_N,
		iFLASH_RY_N,
		oFLASH_BYTE_N,
		oFLASH_OE_N,
		oFLASH_CE_N,

		SRAM_DQ,
		SRAM_DPA,
		oSRAM_A,
		oSRAM_ADSC_N,
		oSRAM_ADSP_N,
		oSRAM_ADV_N,
		oSRAM_BE_N,
		oSRAM_CE1_N,
		oSRAM_CE2,
		oSRAM_CE3_N,
		oSRAM_CLK,
		oSRAM_GW_N,
		oSRAM_OE_N,
		oSRAM_WE_N,

		OTG_D,
		oOTG_A,
		oOTG_CS_N,
		oOTG_OE_N,
		oOTG_WE_N,
		oOTG_RESET_N,
		OTG_FSPEED,
		OTG_LSPEED,
		iOTG_INT0,
		iOTG_INT1,
		iOTG_DREQ0,
		iOTG_DREQ1,
		oOTG_DACK0_N,
		oOTG_DACK1_N,

		oLCD_ON,
		oLCD_BLON,
		oLCD_RW,
		oLCD_EN,
		oLCD_RS,
		LCD_D,

		SD_DAT,
		SD_DAT3,
		SD_CMD,
		oSD_CLK,

		I2C_SDAT,
		oI2C_SCLK,

		PS2_KBDAT,
		PS2_KBCLK,
		PS2_MSDAT,
		PS2_MSCLK,

		oVGA_CLOCK,
		oVGA_HS,
		oVGA_VS,
		oVGA_BLANK_N,
		oVGA_SYNC_N,
		oVGA_R,
		oVGA_G,
		oVGA_B,

		ENET_D,
		oENET_CMD,
		oENET_CS_N,
		oENET_IOW_N,
		oENET_IOR_N,
		oENET_RESET_N,
		iENET_INT,
		oENET_CLK,

		AUD_ADCLRCK,
		iAUD_ADCDAT,
		AUD_DACLRCK,
		oAUD_DACDAT,
		AUD_BCLK,
		oAUD_XCK,

		iTD1_CLK27,
		iTD1_D,
		iTD1_HS,
		iTD1_VS,
		oTD1_RESET_N,
		iTD2_CLK27,
		iTD2_D,
		iTD2_HS,
		iTD2_VS,
		oTD2_RESET_N,

		GPIO_0,
		GPIO_CLKIN_N0,
		GPIO_CLKIN_P0,
		GPIO_CLKOUT_N0,
		GPIO_CLKOUT_P0,
		GPIO_1,
		GPIO_CLKIN_N1,
		GPIO_CLKIN_P1,
		GPIO_CLKOUT_N1,
		GPIO_CLKOUT_P1
	   
	);










input			iCLK_28;
input			iCLK_50;
input			iCLK_50_2;
input           iCLK_50_3;
input           iCLK_50_4;
input           iEXT_CLOCK;

input	[3:0]	iKEY;

input	[17:0]	iSW;

output	[6:0]	oHEX0_D;
output			oHEX0_DP;
output	[6:0]	oHEX1_D;
output			oHEX1_DP;
output	[6:0]	oHEX2_D;
output			oHEX2_DP;
output	[6:0]	oHEX3_D;
output			oHEX3_DP;
output	[6:0]	oHEX4_D;
output			oHEX4_DP;
output	[6:0]	oHEX5_D;
output			oHEX5_DP;
output	[6:0]	oHEX6_D;
output			oHEX6_DP;
output	[6:0]	oHEX7_D;
output			oHEX7_DP;

output	[8:0]	oLEDG;
output	[17:0]	oLEDR;

output			oUART_TXD;
input			iUART_RXD;
output			oUART_CTS;
input			iUART_RTS;

output			oIRDA_TXD;
input			iIRDA_RXD;

inout	[31:0]	DRAM_DQ;
output	[12:0]	oDRAM0_A;
output	[12:0]	oDRAM1_A;
output			oDRAM0_LDQM0;
output			oDRAM1_LDQM0;
output			oDRAM0_UDQM1;
output			oDRAM1_UDQM1;
output			oDRAM0_WE_N;
output			oDRAM1_WE_N;
output			oDRAM0_CAS_N;
output			oDRAM1_CAS_N;
output			oDRAM0_RAS_N;
output			oDRAM1_RAS_N;
output			oDRAM0_CS_N;
output			oDRAM1_CS_N;
output	[1:0]	oDRAM0_BA;
output	[1:0]	oDRAM1_BA;
output			oDRAM0_CLK;
output			oDRAM1_CLK;
output			oDRAM0_CKE;
output			oDRAM1_CKE;

inout	[14:0]	FLASH_DQ;
inout			FLASH_DQ15_AM1;
output	[21:0]	oFLASH_A;
output			oFLASH_WE_N;
output			oFLASH_RST_N;
output			oFLASH_WP_N;
input			iFLASH_RY_N;
output			oFLASH_BYTE_N;
output			oFLASH_OE_N;
output			oFLASH_CE_N;

inout	[31:0]	SRAM_DQ;
inout	[3:0]	SRAM_DPA;
output	[18:0]	oSRAM_A;
output			oSRAM_ADSC_N;
output			oSRAM_ADSP_N;
output			oSRAM_ADV_N;
output	[3:0]	oSRAM_BE_N;
output			oSRAM_CE1_N;
output			oSRAM_CE2;
output			oSRAM_CE3_N;
output			oSRAM_CLK;
output			oSRAM_GW_N;
output			oSRAM_OE_N;
output			oSRAM_WE_N;

inout	[15:0]	OTG_D;
output	[1:0]	oOTG_A;
output			oOTG_CS_N;
output			oOTG_OE_N;
output			oOTG_WE_N;
output			oOTG_RESET_N;
inout			OTG_FSPEED;
inout			OTG_LSPEED;
input			iOTG_INT0;
input			iOTG_INT1;
input			iOTG_DREQ0;
input			iOTG_DREQ1;
output			oOTG_DACK0_N;
output			oOTG_DACK1_N;

inout	[7:0]	LCD_D;
output			oLCD_ON;
output			oLCD_BLON;
output			oLCD_RW;
output			oLCD_EN;
output			oLCD_RS;

inout			SD_DAT;
inout			SD_DAT3;
inout			SD_CMD;
output			oSD_CLK;

inout			I2C_SDAT;
output			oI2C_SCLK;

inout		 	PS2_KBDAT;
inout			PS2_KBCLK;
inout		 	PS2_MSDAT;
inout			PS2_MSCLK;

output			oVGA_CLOCK;
output			oVGA_HS;
output			oVGA_VS;
output			oVGA_BLANK_N;
output			oVGA_SYNC_N;
output	[9:0]	oVGA_R;
output	[9:0]	oVGA_G;
output	[9:0]	oVGA_B;

inout	[15:0]	ENET_D;
output			oENET_CMD;
output			oENET_CS_N;
output			oENET_IOW_N;
output			oENET_IOR_N;
output			oENET_RESET_N;
input			iENET_INT;
output			oENET_CLK;

inout			AUD_ADCLRCK;
input			iAUD_ADCDAT;
inout			AUD_DACLRCK;
output			oAUD_DACDAT;
inout			AUD_BCLK;
output			oAUD_XCK;

input			iTD1_CLK27;
input	[7:0]	iTD1_D;
input			iTD1_HS;
input			iTD1_VS;
output			oTD1_RESET_N;
input			iTD2_CLK27;
input	[7:0]	iTD2_D;
input			iTD2_HS;
input			iTD2_VS;
output			oTD2_RESET_N;


output	[31:0]	GPIO_0;
input			GPIO_CLKIN_N0;
input			GPIO_CLKIN_P0;
inout			GPIO_CLKOUT_N0;
inout			GPIO_CLKOUT_P0;
input	[31:0]	GPIO_1;
input			GPIO_CLKIN_N1;
input			GPIO_CLKIN_P1;
inout			GPIO_CLKOUT_N1;
inout			GPIO_CLKOUT_P1;





wire [63:0] result;

wire	CPU_CLK;
wire	CPU_RESET;
wire	CLK_18_4;
wire	CLK_25;


wire		AUD_CTRL_CLK;

wire  [31:0]	mSEG7_DIG;
reg	 [31:0]	Cont;
wire		VGA_CTRL_CLK;
wire [9:0]	mVGA_R;
wire [9:0]	mVGA_G;
wire [9:0]	mVGA_B;
wire [19:0]	mVGA_ADDR;
wire		DLY_RST;


wire	[9:0]	mRed;
wire	[9:0]	mGreen;
wire	[9:0]	mBlue;
wire			VGA_Read;


wire	[3:0]	Remain;
wire	[9:0]	Quotient;

wire			mDVAL;

reg  [3:0]      DP;
assign oHEX0_DP = 1'b1;
assign oHEX1_DP = 1'b1;
assign oHEX2_DP = 1'b1;
assign oHEX3_DP = 1'b1;
assign oHEX4_DP = 1'b1;
assign oHEX5_DP = 1'b1;
assign oHEX6_DP = 1'b1;
assign oHEX7_DP = 1'b1;



wire      LCD_ON_1  ;
wire      LCD_BLON_1;
wire [7:0]LCD_D_1   ;
wire      LCD_RW_1  ;
wire      LCD_EN_1  ;
wire      LCD_RS_1  ;






assign	DRAM_DQ		=	16'hzzzz;
assign	FL_DQ		=	8'hzz;
assign	SRAM_DQ		=	16'hzzzz;
assign	OTG_DATA	=	16'hzzzz;
assign	SD_DAT		=	1'bz;
assign	ENET_DATA	=	16'hzzzz;
assign	OTG_FSPEED	=	1'bz;
assign	OTG_LSPEED	=	1'bz;
assign	SD_DAT		=	1'bz;
assign DRAM_DQ 			= 32'hzzzzzzzz;
assign GPIO_CLKOUT_N0 	= 1'bz;     		  	
assign GPIO_CLKOUT_P0 	= 1'bz;     		                
assign GPIO_CLKOUT_N1 	= 1'bz;     		         
assign GPIO_CLKOUT_P1  	= 1'bz;     		         
assign AUD_ADCLRCK    	= 1'bz;     					 					
assign AUD_DACLRCK 		= 1'bz;   
assign oAUD_DACDAT 		= 1'bz;     					
assign AUD_BCLK 		= 1'bz;     						
assign oAUD_XCK 		= 1'bz;     				
assign ENET_D 			= 16'hzzzz;			
assign PS2_DAT 			= 1'bz;     			
assign PS2_CLK 			= 1'bz;     						
assign I2C_SDAT 		= 1'bz;     						
assign oI2C_SCLK 		= 1'bz;     						
assign SD_DAT 			= 1'bz;     							
assign SD_DAT3 			= 1'bz;     						
assign SD_CMD 			= 1'bz;     						
assign oSD_CLK 			= 1'bz;     						
assign OTG_D   			= 16'hzzzz;	
assign SRAM_DQ 			= 32'hzzzzzzzz;				

assign LCD_ON_1 = 1'b1;
assign LCD_BLON_1 = 1'b1;

always@(posedge iCLK_50 or negedge iKEY[0])
    begin
        if(!iKEY[0])
        Cont	<=	0;
        else
        Cont	<=	Cont+1;
    end
    

Reset_Delay			r0	(	.iCLK(iCLK_50),.oRESET(DLY_RST)	);



flash_default_tester flash1(

	.iDEFAULT    (iIRDA_RXD ),
	.iBUSSW      (iKEY[0]  ),
	.iTRIKEY     (iKEY[3]|iKEY[1]  ),
	.iCLK_28     (iCLK_28  ),


	.FLASH_DQ      (FLASH_DQ      ),		
	.FLASH_DQ15_AM1(FLASH_DQ15_AM1),	
	.oFLASH_A      (oFLASH_A      ),
	.iFLASH_RY_N   (iFLASH_RY_N   ),
	.oFLASH_WE_N   (oFLASH_WE_N   ),	
	.oFLASH_RST_N  (oFLASH_RST_N  ),	
	.oFLASH_WP_N   (oFLASH_WP_N   ),	
	.oFLASH_BYTE_N (oFLASH_BYTE_N ),	
	.oFLASH_OE_N   (oFLASH_OE_N   ),	
	.oFLASH_CE_N   (oFLASH_CE_N   ),	
             

	.oLCD_ON  (oLCD_ON  ),
	.oLCD_BLON(oLCD_BLON),
	.LCD_D    (LCD_D    ),
	.oLCD_RW  (oLCD_RW  ),
	.oLCD_EN  (oLCD_EN  ),
	.oLCD_RS  (oLCD_RS  ),


	.iLCD_ON_1  (LCD_ON_1  ),
	.iLCD_BLON_1(LCD_BLON_1),
	.LCD_D_1    (LCD_D_1    ),
	.iLCD_RW_1  (LCD_RW_1  ),
	.iLCD_EN_1  (LCD_EN_1  ),
	.iLCD_RS_1  (LCD_RS_1  ),

);        

LCD_TEST 			u5	(
							.iCLK(iCLK_50),
							.iRST_N(DLY_RST),

							.LCD_DATA(LCD_D_1),
							.LCD_RW(LCD_RW_1),
							.LCD_EN(LCD_EN_1),
							.LCD_RS(LCD_RS_1)	);


assign	mSEG7_DIG	=	iKEY[3] ? result[63:32] : result[31:0];
assign	oLEDR		=	{	Cont[25:23],Cont[25:23],Cont[25:23],
							Cont[25:23],Cont[25:23],Cont[25:23]	};
assign	oLEDG		=	{	Cont[25:23],Cont[25:23],Cont[25:23]	};



SEG7_LUT_8 			u0	(	.oSEG0(oHEX0_D),
							.oSEG1(oHEX1_D),
							.oSEG2(oHEX2_D),
							.oSEG3(oHEX3_D),
							.oSEG4(oHEX4_D),
							.oSEG5(oHEX5_D),
							.oSEG6(oHEX6_D),
							.oSEG7(oHEX7_D),
							.iDIG(mSEG7_DIG) );







wire [63:0] K_over_S = 64'h3ff0000000000000;
wire [63:0]	plus     = 64'h3f8030dc4ea03a72;
wire [63:0] minus    = 64'hbf8030dc4ea03a72;
wire [63:0] p_up     = 64'h3fdfe9e61a77116f;
wire [63:0] p_down   = 64'h3fe00af7fa15cd9b;



amer_put i1(
  .clk_fast(iCLK_50),
  .clk_slow(iCLK_50),
  .nrst(iKEY[0]),
  .start_s1(~iKEY[1]),
  .start_s2(~iKEY[2]),
  .p_up(p_up),
  .p_down(p_down),
  .log_lambda_up(plus),
  .log_lambda_down(minus),
  .K_over_S(K_over_S),
  .result(result),
);



endmodule
module DE2_70_Default
	(

		iCLK_28,
		iCLK_50,
		iCLK_50_2,
		iCLK_50_3,
		iCLK_50_4,
		iEXT_CLOCK,

		iKEY,

		iSW,

		oHEX0_D,
		oHEX0_DP,
		oHEX1_D,
		oHEX1_DP,
		oHEX2_D,
		oHEX2_DP,
		oHEX3_D,
		oHEX3_DP,
		oHEX4_D,
		oHEX4_DP,
		oHEX5_D,
		oHEX5_DP,
		oHEX6_D,
		oHEX6_DP,
		oHEX7_D,
		oHEX7_DP,

		oLEDG,
		oLEDR,

		oUART_TXD,
		iUART_RXD,
		oUART_CTS,
		iUART_RTS,

		oIRDA_TXD,
		iIRDA_RXD,

		DRAM_DQ,
		oDRAM0_A,
		oDRAM1_A,
		oDRAM0_LDQM0,
		oDRAM1_LDQM0,
		oDRAM0_UDQM1,
		oDRAM1_UDQM1,
		oDRAM0_WE_N,
		oDRAM1_WE_N,
		oDRAM0_CAS_N,
		oDRAM1_CAS_N,
		oDRAM0_RAS_N,
		oDRAM1_RAS_N,
		oDRAM0_CS_N,
		oDRAM1_CS_N,
		oDRAM0_BA,
		oDRAM1_BA,
		oDRAM0_CLK,
		oDRAM1_CLK,
		oDRAM0_CKE,
		oDRAM1_CKE,

		FLASH_DQ,
		FLASH_DQ15_AM1,
		oFLASH_A,
		oFLASH_WE_N,
		oFLASH_RST_N,
		oFLASH_WP_N,
		iFLASH_RY_N,
		oFLASH_BYTE_N,
		oFLASH_OE_N,
		oFLASH_CE_N,

		SRAM_DQ,
		SRAM_DPA,
		oSRAM_A,
		oSRAM_ADSC_N,
		oSRAM_ADSP_N,
		oSRAM_ADV_N,
		oSRAM_BE_N,
		oSRAM_CE1_N,
		oSRAM_CE2,
		oSRAM_CE3_N,
		oSRAM_CLK,
		oSRAM_GW_N,
		oSRAM_OE_N,
		oSRAM_WE_N,

		OTG_D,
		oOTG_A,
		oOTG_CS_N,
		oOTG_OE_N,
		oOTG_WE_N,
		oOTG_RESET_N,
		OTG_FSPEED,
		OTG_LSPEED,
		iOTG_INT0,
		iOTG_INT1,
		iOTG_DREQ0,
		iOTG_DREQ1,
		oOTG_DACK0_N,
		oOTG_DACK1_N,

		oLCD_ON,
		oLCD_BLON,
		oLCD_RW,
		oLCD_EN,
		oLCD_RS,
		LCD_D,

		SD_DAT,
		SD_DAT3,
		SD_CMD,
		oSD_CLK,

		I2C_SDAT,
		oI2C_SCLK,

		PS2_KBDAT,
		PS2_KBCLK,
		PS2_MSDAT,
		PS2_MSCLK,

		oVGA_CLOCK,
		oVGA_HS,
		oVGA_VS,
		oVGA_BLANK_N,
		oVGA_SYNC_N,
		oVGA_R,
		oVGA_G,
		oVGA_B,

		ENET_D,
		oENET_CMD,
		oENET_CS_N,
		oENET_IOW_N,
		oENET_IOR_N,
		oENET_RESET_N,
		iENET_INT,
		oENET_CLK,

		AUD_ADCLRCK,
		iAUD_ADCDAT,
		AUD_DACLRCK,
		oAUD_DACDAT,
		AUD_BCLK,
		oAUD_XCK,

		iTD1_CLK27,
		iTD1_D,
		iTD1_HS,
		iTD1_VS,
		oTD1_RESET_N,
		iTD2_CLK27,
		iTD2_D,
		iTD2_HS,
		iTD2_VS,
		oTD2_RESET_N,

		GPIO_0,
		GPIO_CLKIN_N0,
		GPIO_CLKIN_P0,
		GPIO_CLKOUT_N0,
		GPIO_CLKOUT_P0,
		GPIO_1,
		GPIO_CLKIN_N1,
		GPIO_CLKIN_P1,
		GPIO_CLKOUT_N1,
		GPIO_CLKOUT_P1
	   
	);











input			iCLK_28;
input			iCLK_50;
input			iCLK_50_2;
input           iCLK_50_3;
input           iCLK_50_4;
input           iEXT_CLOCK;

input	[3:0]	iKEY;

input	[17:0]	iSW;

output	[6:0]	oHEX0_D;
output			oHEX0_DP;
output	[6:0]	oHEX1_D;
output			oHEX1_DP;
output	[6:0]	oHEX2_D;
output			oHEX2_DP;
output	[6:0]	oHEX3_D;
output			oHEX3_DP;
output	[6:0]	oHEX4_D;
output			oHEX4_DP;
output	[6:0]	oHEX5_D;
output			oHEX5_DP;
output	[6:0]	oHEX6_D;
output			oHEX6_DP;
output	[6:0]	oHEX7_D;
output			oHEX7_DP;

output	[8:0]	oLEDG;
output	[17:0]	oLEDR;

output			oUART_TXD;
input			iUART_RXD;
output			oUART_CTS;
input			iUART_RTS;

output			oIRDA_TXD;
input			iIRDA_RXD;

inout	[31:0]	DRAM_DQ;
output	[12:0]	oDRAM0_A;
output	[12:0]	oDRAM1_A;
output			oDRAM0_LDQM0;
output			oDRAM1_LDQM0;
output			oDRAM0_UDQM1;
output			oDRAM1_UDQM1;
output			oDRAM0_WE_N;
output			oDRAM1_WE_N;
output			oDRAM0_CAS_N;
output			oDRAM1_CAS_N;
output			oDRAM0_RAS_N;
output			oDRAM1_RAS_N;
output			oDRAM0_CS_N;
output			oDRAM1_CS_N;
output	[1:0]	oDRAM0_BA;
output	[1:0]	oDRAM1_BA;
output			oDRAM0_CLK;
output			oDRAM1_CLK;
output			oDRAM0_CKE;
output			oDRAM1_CKE;

inout	[14:0]	FLASH_DQ;
inout			FLASH_DQ15_AM1;
output	[21:0]	oFLASH_A;
output			oFLASH_WE_N;
output			oFLASH_RST_N;
output			oFLASH_WP_N;
input			iFLASH_RY_N;
output			oFLASH_BYTE_N;
output			oFLASH_OE_N;
output			oFLASH_CE_N;

inout	[31:0]	SRAM_DQ;
inout	[3:0]	SRAM_DPA;
output	[18:0]	oSRAM_A;
output			oSRAM_ADSC_N;
output			oSRAM_ADSP_N;
output			oSRAM_ADV_N;
output	[3:0]	oSRAM_BE_N;
output			oSRAM_CE1_N;
output			oSRAM_CE2;
output			oSRAM_CE3_N;
output			oSRAM_CLK;
output			oSRAM_GW_N;
output			oSRAM_OE_N;
output			oSRAM_WE_N;

inout	[15:0]	OTG_D;
output	[1:0]	oOTG_A;
output			oOTG_CS_N;
output			oOTG_OE_N;
output			oOTG_WE_N;
output			oOTG_RESET_N;
inout			OTG_FSPEED;
inout			OTG_LSPEED;
input			iOTG_INT0;
input			iOTG_INT1;
input			iOTG_DREQ0;
input			iOTG_DREQ1;
output			oOTG_DACK0_N;
output			oOTG_DACK1_N;

inout	[7:0]	LCD_D;
output			oLCD_ON;
output			oLCD_BLON;
output			oLCD_RW;
output			oLCD_EN;
output			oLCD_RS;

inout			SD_DAT;
inout			SD_DAT3;
inout			SD_CMD;
output			oSD_CLK;

inout			I2C_SDAT;
output			oI2C_SCLK;

inout		 	PS2_KBDAT;
inout			PS2_KBCLK;
inout		 	PS2_MSDAT;
inout			PS2_MSCLK;

output			oVGA_CLOCK;
output			oVGA_HS;
output			oVGA_VS;
output			oVGA_BLANK_N;
output			oVGA_SYNC_N;
output	[9:0]	oVGA_R;
output	[9:0]	oVGA_G;
output	[9:0]	oVGA_B;

inout	[15:0]	ENET_D;
output			oENET_CMD;
output			oENET_CS_N;
output			oENET_IOW_N;
output			oENET_IOR_N;
output			oENET_RESET_N;
input			iENET_INT;
output			oENET_CLK;

inout			AUD_ADCLRCK;
input			iAUD_ADCDAT;
inout			AUD_DACLRCK;
output			oAUD_DACDAT;
inout			AUD_BCLK;
output			oAUD_XCK;

input			iTD1_CLK27;
input	[7:0]	iTD1_D;
input			iTD1_HS;
input			iTD1_VS;
output			oTD1_RESET_N;
input			iTD2_CLK27;
input	[7:0]	iTD2_D;
input			iTD2_HS;
input			iTD2_VS;
output			oTD2_RESET_N;


output	[31:0]	GPIO_0;
input			GPIO_CLKIN_N0;
input			GPIO_CLKIN_P0;
inout			GPIO_CLKOUT_N0;
inout			GPIO_CLKOUT_P0;
input	[31:0]	GPIO_1;
input			GPIO_CLKIN_N1;
input			GPIO_CLKIN_P1;
inout			GPIO_CLKOUT_N1;
inout			GPIO_CLKOUT_P1;





wire [63:0] result;

wire	CPU_CLK;
wire	CPU_RESET;
wire	CLK_18_4;
wire	CLK_25;


wire		AUD_CTRL_CLK;

wire  [31:0]	mSEG7_DIG;
reg	 [31:0]	Cont;
wire		VGA_CTRL_CLK;
wire [9:0]	mVGA_R;
wire [9:0]	mVGA_G;
wire [9:0]	mVGA_B;
wire [19:0]	mVGA_ADDR;
wire		DLY_RST;


wire	[9:0]	mRed;
wire	[9:0]	mGreen;
wire	[9:0]	mBlue;
wire			VGA_Read;


wire	[3:0]	Remain;
wire	[9:0]	Quotient;

wire			mDVAL;

reg  [3:0]      DP;
assign oHEX0_DP = 1'b1;
assign oHEX1_DP = 1'b1;
assign oHEX2_DP = 1'b1;
assign oHEX3_DP = 1'b1;
assign oHEX4_DP = 1'b1;
assign oHEX5_DP = 1'b1;
assign oHEX6_DP = 1'b1;
assign oHEX7_DP = 1'b1;



wire      LCD_ON_1  ;
wire      LCD_BLON_1;
wire [7:0]LCD_D_1   ;
wire      LCD_RW_1  ;
wire      LCD_EN_1  ;
wire      LCD_RS_1  ;






assign	DRAM_DQ		=	16'hzzzz;
assign	FL_DQ		=	8'hzz;
assign	SRAM_DQ		=	16'hzzzz;
assign	OTG_DATA	=	16'hzzzz;
assign	SD_DAT		=	1'bz;
assign	ENET_DATA	=	16'hzzzz;
assign	OTG_FSPEED	=	1'bz;
assign	OTG_LSPEED	=	1'bz;
assign	SD_DAT		=	1'bz;
assign DRAM_DQ 			= 32'hzzzzzzzz;
assign GPIO_CLKOUT_N0 	= 1'bz;     		  	
assign GPIO_CLKOUT_P0 	= 1'bz;     		                
assign GPIO_CLKOUT_N1 	= 1'bz;     		         
assign GPIO_CLKOUT_P1  	= 1'bz;     		         
assign AUD_ADCLRCK    	= 1'bz;     					 					
assign AUD_DACLRCK 		= 1'bz;   
assign oAUD_DACDAT 		= 1'bz;     					
assign AUD_BCLK 		= 1'bz;     						
assign oAUD_XCK 		= 1'bz;     				
assign ENET_D 			= 16'hzzzz;			
assign PS2_DAT 			= 1'bz;     			
assign PS2_CLK 			= 1'bz;     						
assign I2C_SDAT 		= 1'bz;     						
assign oI2C_SCLK 		= 1'bz;     						
assign SD_DAT 			= 1'bz;     							
assign SD_DAT3 			= 1'bz;     						
assign SD_CMD 			= 1'bz;     						
assign oSD_CLK 			= 1'bz;     						
assign OTG_D   			= 16'hzzzz;	
assign SRAM_DQ 			= 32'hzzzzzzzz;				

assign LCD_ON_1 = 1'b1;
assign LCD_BLON_1 = 1'b1;

always@(posedge iCLK_50 or negedge iKEY[0])
    begin
        if(!iKEY[0])
        Cont	<=	0;
        else
        Cont	<=	Cont+1;
    end
    

Reset_Delay			r0	(	.iCLK(iCLK_50),.oRESET(DLY_RST)	);



flash_default_tester flash1(

	.iDEFAULT    (iIRDA_RXD ),
	.iBUSSW      (iKEY[0]  ),
	.iTRIKEY     (iKEY[3]|iKEY[1]  ),
	.iCLK_28     (iCLK_28  ),


	.FLASH_DQ      (FLASH_DQ      ),		
	.FLASH_DQ15_AM1(FLASH_DQ15_AM1),	
	.oFLASH_A      (oFLASH_A      ),
	.iFLASH_RY_N   (iFLASH_RY_N   ),
	.oFLASH_WE_N   (oFLASH_WE_N   ),	
	.oFLASH_RST_N  (oFLASH_RST_N  ),	
	.oFLASH_WP_N   (oFLASH_WP_N   ),	
	.oFLASH_BYTE_N (oFLASH_BYTE_N ),	
	.oFLASH_OE_N   (oFLASH_OE_N   ),	
	.oFLASH_CE_N   (oFLASH_CE_N   ),	
             

	.oLCD_ON  (oLCD_ON  ),
	.oLCD_BLON(oLCD_BLON),
	.LCD_D    (LCD_D    ),
	.oLCD_RW  (oLCD_RW  ),
	.oLCD_EN  (oLCD_EN  ),
	.oLCD_RS  (oLCD_RS  ),


	.iLCD_ON_1  (LCD_ON_1  ),
	.iLCD_BLON_1(LCD_BLON_1),
	.LCD_D_1    (LCD_D_1    ),
	.iLCD_RW_1  (LCD_RW_1  ),
	.iLCD_EN_1  (LCD_EN_1  ),
	.iLCD_RS_1  (LCD_RS_1  ),

);        

LCD_TEST 			u5	(
							.iCLK(iCLK_50),
							.iRST_N(DLY_RST),

							.LCD_DATA(LCD_D_1),
							.LCD_RW(LCD_RW_1),
							.LCD_EN(LCD_EN_1),
							.LCD_RS(LCD_RS_1)	);


assign	mSEG7_DIG	=	iKEY[3] ? result[63:32] : result[31:0];
assign	oLEDR		=	{	Cont[25:23],Cont[25:23],Cont[25:23],
							Cont[25:23],Cont[25:23],Cont[25:23]	};
assign	oLEDG		=	{	Cont[25:23],Cont[25:23],Cont[25:23]	};



SEG7_LUT_8 			u0	(	.oSEG0(oHEX0_D),
							.oSEG1(oHEX1_D),
							.oSEG2(oHEX2_D),
							.oSEG3(oHEX3_D),
							.oSEG4(oHEX4_D),
							.oSEG5(oHEX5_D),
							.oSEG6(oHEX6_D),
							.oSEG7(oHEX7_D),
							.iDIG(mSEG7_DIG) );







wire [63:0] K_over_S = 64'h3ff0000000000000;
wire [63:0]	plus     = 64'h3f8030dc4ea03a72;
wire [63:0] minus    = 64'hbf8030dc4ea03a72;
wire [63:0] p_up     = 64'h3fdfe9e61a77116f;
wire [63:0] p_down   = 64'h3fe00af7fa15cd9b;



amer_put i1(
  .clk_fast(iCLK_50),
  .clk_slow(iCLK_50),
  .nrst(iKEY[0]),
  .start_s1(~iKEY[1]),
  .start_s2(~iKEY[2]),
  .p_up(p_up),
  .p_down(p_down),
  .log_lambda_up(plus),
  .log_lambda_down(minus),
  .K_over_S(K_over_S),
  .result(result),
);



endmodule