data/full_repos/permissive/421450529/MEM_module.v
1: b"%Error: data/full_repos/permissive/421450529/MEM_module.v:39: Cannot find file containing module: 'Controller'\n  Controller Controller_M(.func(Instr[5:0]),.op(Instr[31:26]),.MemWrite(MemWrite),.s_l_op(s_l_op));\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/421450529,data/full_repos/permissive/421450529/Controller\n             data/full_repos/permissive/421450529,data/full_repos/permissive/421450529/Controller.v\n             data/full_repos/permissive/421450529,data/full_repos/permissive/421450529/Controller.sv\n             Controller\n             Controller.v\n             Controller.sv\n             obj_dir/Controller\n             obj_dir/Controller.v\n             obj_dir/Controller.sv\n%Error: data/full_repos/permissive/421450529/MEM_module.v:40: Cannot find file containing module: 'ByteEnable'\n  ByteEnable ByteEnable(s_l_op,ALUout_M,BE);\n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/421450529/MEM_module.v:41: Cannot find file containing module: 'DM'\n    DM DM(clk,reset,PC_M,ALUout_M,MemWrite,Write_data_trans,BE,DMout);\n    ^~\n%Error: data/full_repos/permissive/421450529/MEM_module.v:42: Cannot find file containing module: 'mux2_32'\n  mux2_32 MFRTM(WD,Write_data_W,ForwardRTM,Write_data_trans);   \n  ^~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module MEM_module(
     input clk,
     input reset,
	  input[31:0] PC_M,
     input[31:0] Instr,
     input[31:0] ALUout_M,
     input[31:0] WD,
	  input ForwardRTM,
	  input[31:0] Write_data_W,
     output[31:0] DMout,
	  output[3:0] BE
    );
	 
	 wire MemWrite,ext_op;
	 wire[31:0] Write_data_trans;
	 wire[1:0] s_l_op;
	 
	 
	 Controller Controller_M(.func(Instr[5:0]),.op(Instr[31:26]),.MemWrite(MemWrite),.s_l_op(s_l_op));
	 ByteEnable ByteEnable(s_l_op,ALUout_M,BE);
    DM DM(clk,reset,PC_M,ALUout_M,MemWrite,Write_data_trans,BE,DMout);
	 mux2_32 MFRTM(WD,Write_data_W,ForwardRTM,Write_data_trans);

endmodule
module MEM_module(
     input clk,
     input reset,
	  input[31:0] PC_M,
     input[31:0] Instr,
     input[31:0] ALUout_M,
     input[31:0] WD,
	  input ForwardRTM,
	  input[31:0] Write_data_W,
     output[31:0] DMout,
	  output[3:0] BE
    );

	 
	 wire MemWrite,ext_op;
	 wire[31:0] Write_data_trans;
	 wire[1:0] s_l_op;
	 
	 
	 Controller Controller_M(.func(Instr[5:0]),.op(Instr[31:26]),.MemWrite(MemWrite),.s_l_op(s_l_op));
	 ByteEnable ByteEnable(s_l_op,ALUout_M,BE);
    DM DM(clk,reset,PC_M,ALUout_M,MemWrite,Write_data_trans,BE,DMout);
	 mux2_32 MFRTM(WD,Write_data_W,ForwardRTM,Write_data_trans);

endmodule