data/full_repos/permissive/487568919/generic_systemverilog_designs_library/binary_counter/binary_counter.sv
data/verilator_xmls/5a7b8fe7-09e6-4ba2-aafe-998ac44ae391.xml
module binary_counter
  #(parameter WIDTH=4)
  (input  logic clk, 
                reset, 
   output logic [WIDTH-1:0] q);    
  
  always_ff @ (posedge clk or posedge reset) 
    if (reset == 1) q <= 'b0;
    else            q <= q + 1; 
  
endmodule
module binary_counter
  #(parameter WIDTH=4)
  (input  logic clk, 
                reset, 
   output logic [WIDTH-1:0] q);
    
  
  always_ff @ (posedge clk or posedge reset) 
    if (reset == 1) q <= 'b0;
    else            q <= q + 1; 
  
endmodule