data/full_repos/permissive/445695969/src_rtl/protected/dom1/skinny_sbox8_dom1_dep_non_pipelined_de.v
data/verilator_xmls/359e6ae9-e87c-4890-a1c3-98b86ef114b5.xml
module dom1_dep_sbox8_cfn_fr_ne (

			         f,

			         a, b, z, r, clk
			      ) ;

   output [1:0]        f;

   input [1:0] 	       a, b, z;

   input [1:0] 	       r;

   input               clk;


   (*equivalent_register_removal = "no" *) wire [1:0]           x, y;

   (*equivalent_register_removal = "no" *)reg [1:0]            g, t;


   assign x = {a[1],~a[0]};

   assign y = {b[1],~b[0]};


      always @ (negedge clk) begin
	 g[1] <= y[1] ^ r[0];

	 g[0] <= y[0] ^ r[0];

      end

      always @(negedge clk) begin
	 t[1] <= (x[1]&r[0])^r[1]^z[1];

	 t[0] <= (x[0]&r[0])^r[1]^z[0];

      end

   assign f[1] = x[1]&(y[1]^g[0])^t[1];

   assign f[0] = x[0]&(y[0]^g[1])^t[0];
   

endmodule
module dom1_dep_sbox8_cfn_fr_ne (

			         f,

			         a, b, z, r, clk
			      ) ;


   output [1:0]        f;

   input [1:0] 	       a, b, z;

   input [1:0] 	       r;

   input               clk;


   (*equivalent_register_removal = "no" *) wire [1:0]           x, y;

   (*equivalent_register_removal = "no" *)reg [1:0]            g, t;


   assign x = {a[1],~a[0]};

   assign y = {b[1],~b[0]};


      always @ (negedge clk) begin
	 g[1] <= y[1] ^ r[0];

	 g[0] <= y[0] ^ r[0];

      end

      always @(negedge clk) begin
	 t[1] <= (x[1]&r[0])^r[1]^z[1];

	 t[0] <= (x[0]&r[0])^r[1]^z[0];

      end

   assign f[1] = x[1]&(y[1]^g[0])^t[1];

   assign f[0] = x[0]&(y[0]^g[1])^t[0];
   

endmodule