data/full_repos/permissive/507506290/RTL_Files/MUX_ALU.v
data/verilator_xmls/35e39c83-4dda-4c1f-9b22-87bec0fa94ce.xml
module MUX_ALU(i_m1 , i_m2 , i_sel  , o_mux );
input [`WIDTH_MUX_ALU-1:0] i_m1 , i_m2 ;
input i_sel ;
output [`WIDTH_MUX_ALU -1:0] o_mux ;

assign o_mux = i_sel? i_m2 : i_m1 ;

endmodule
module MUX_ALU(i_m1 , i_m2 , i_sel  , o_mux );

input [`WIDTH_MUX_ALU-1:0] i_m1 , i_m2 ;
input i_sel ;
output [`WIDTH_MUX_ALU -1:0] o_mux ;

assign o_mux = i_sel? i_m2 : i_m1 ;

endmodule