data/full_repos/permissive/40580763/zpu_core_rom.v
1: b'%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:2: Cannot find include file: zpu_core_defines.v\n`include "zpu_core_defines.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/40580763,data/full_repos/permissive/40580763/zpu_core_defines.v\n             data/full_repos/permissive/40580763,data/full_repos/permissive/40580763/zpu_core_defines.v.v\n             data/full_repos/permissive/40580763,data/full_repos/permissive/40580763/zpu_core_defines.v.sv\n             zpu_core_defines.v\n             zpu_core_defines.v.v\n             zpu_core_defines.v.sv\n             obj_dir/zpu_core_defines.v\n             obj_dir/zpu_core_defines.v.v\n             obj_dir/zpu_core_defines.v.sv\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:39: Define or directive not defined: \'`MC_MEM_BITS\'\ninput [`MC_MEM_BITS-1:0] addr;\n       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:40: Define or directive not defined: \'`MC_BITS\'\noutput [`MC_BITS-1:0]  data;\n        ^~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:43: Define or directive not defined: \'`MC_MEM_BITS\'\nwire [`MC_MEM_BITS-1:0]  addr;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:44: Define or directive not defined: \'`MC_BITS\'\nreg  [`MC_BITS-1:0]  data;\n      ^~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:45: Define or directive not defined: \'`MC_BITS\'\nreg  [`MC_BITS-1:0]  memory[(1<<`MC_MEM_BITS)-1:0];\n      ^~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:45: Define or directive not defined: \'`MC_MEM_BITS\'\nreg  [`MC_BITS-1:0]  memory[(1<<`MC_MEM_BITS)-1:0];\n                                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:45: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nreg  [`MC_BITS-1:0]  memory[(1<<`MC_MEM_BITS)-1:0];\n                                            ^\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:71: Define or directive not defined: \'`MC_ALU_NOP_B\'\nmemory[0] <= `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) |   \n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:71: Define or directive not defined: \'`MC_SEL_ALU_MC_CONST\'\nmemory[0] <= `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) |   \n                             ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:71: Define or directive not defined: \'`P_ADDR\'\nmemory[0] <= `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) |   \n                                                          ^~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:71: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nmemory[0] <= `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) |   \n                                                                 ^\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:72: Define or directive not defined: \'`MC_W_B\'\n  `MC_W_B;\n  ^~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:73: Define or directive not defined: \'`MC_EMULATE\'\nmemory[1] <= `MC_EMULATE;             \n             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:73: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nmemory[1] <= `MC_EMULATE;             \n                        ^\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:76: Define or directive not defined: \'`MC_GO_BREAKPOINT\'\nmemory[4] <= `MC_GO_BREAKPOINT;\n             ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:76: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nmemory[4] <= `MC_GO_BREAKPOINT;\n                              ^\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:81: Define or directive not defined: \'`MC_CLEAR_IDIM\'\nmemory[8] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR |    \n             ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:81: Define or directive not defined: \'`MC_SEL_ADDR_SP\'\nmemory[8] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR |    \n                              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:81: Define or directive not defined: \'`MC_SEL_READ_ADDR\'\nmemory[8] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR |    \n                                                ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:82: Define or directive not defined: \'`MC_ALU_NOP\'\n  `MC_ALU_NOP | `MC_W_A;\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:82: Define or directive not defined: \'`MC_W_A\'\n  `MC_ALU_NOP | `MC_W_A;\n                ^~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:82: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  `MC_ALU_NOP | `MC_W_A;\n                       ^\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:83: Define or directive not defined: \'`MC_SP_MINUS_4\'\nmemory[9] <= `MC_SP_MINUS_4;             \n             ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:83: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nmemory[9] <= `MC_SP_MINUS_4;             \n                           ^\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:84: Define or directive not defined: \'`MC_SEL_ADDR_SP\'\nmemory[10] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;      \n              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:84: Define or directive not defined: \'`MC_MEM_W\'\nmemory[10] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;      \n                                ^~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:84: Define or directive not defined: \'`MC_GO_NEXT\'\nmemory[10] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;      \n                                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:84: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nmemory[10] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;      \n                                                       ^\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:100: Define or directive not defined: \'`MC_GO_BREAKPOINT\'\nmemory[12] <= `MC_GO_BREAKPOINT;\n              ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:100: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nmemory[12] <= `MC_GO_BREAKPOINT;\n                               ^\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:106: Define or directive not defined: \'`MC_CLEAR_IDIM\'\nmemory[16] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |   \n              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:106: Define or directive not defined: \'`MC_SEL_ADDR_SP\'\nmemory[16] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |   \n                               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:106: Define or directive not defined: \'`MC_SEL_READ_DATA\'\nmemory[16] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |   \n                                                 ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:107: Define or directive not defined: \'`MC_MEM_R\'\n  `MC_MEM_R | `MC_W_PC;  \n  ^~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:107: Define or directive not defined: \'`MC_W_PC\'\n  `MC_MEM_R | `MC_W_PC;  \n              ^~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:107: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  `MC_MEM_R | `MC_W_PC;  \n                      ^\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:108: Define or directive not defined: \'`MC_SP_PLUS_4\'\nmemory[17] <= `MC_SP_PLUS_4;             \n              ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:108: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nmemory[17] <= `MC_SP_PLUS_4;             \n                           ^\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:109: Define or directive not defined: \'`MC_FETCH\'\nmemory[18] <= `MC_FETCH;              \n              ^~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:109: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\nmemory[18] <= `MC_FETCH;              \n                       ^\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:114: Define or directive not defined: \'`MC_CLEAR_IDIM\'\nmemory[20] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |     \n              ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:114: Define or directive not defined: \'`MC_SEL_ADDR_SP\'\nmemory[20] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |     \n                               ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:114: Define or directive not defined: \'`MC_MEM_R\'\nmemory[20] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |     \n                                                 ^~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:115: Define or directive not defined: \'`MC_W_A_MEM\'\n  `MC_W_A_MEM | `MC_SP_PLUS_4;\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:115: Define or directive not defined: \'`MC_SP_PLUS_4\'\n  `MC_W_A_MEM | `MC_SP_PLUS_4;\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:115: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  `MC_W_A_MEM | `MC_SP_PLUS_4;\n                             ^\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:116: Define or directive not defined: \'`MC_SEL_ADDR_SP\'\nmemory[21] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |    \n              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:116: Define or directive not defined: \'`MC_SEL_READ_DATA\'\nmemory[21] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |    \n                                ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/40580763/zpu_core_rom.v:116: Define or directive not defined: \'`MC_MEM_R\'\nmemory[21] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |    \n                                                    ^~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module zpu_core_rom (
	clk,
	addr,
	data
);

input [`MC_MEM_BITS-1:0]	addr;
output [`MC_BITS-1:0]		data;
input 				clk;

wire [`MC_MEM_BITS-1:0]		addr;
reg  [`MC_BITS-1:0]		data;
reg  [`MC_BITS-1:0]		memory[(1<<`MC_MEM_BITS)-1:0];

initial data <= 0;
always @(posedge clk) data <= memory[addr];



integer n;
initial begin

















memory[0] <= `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) |
		`MC_W_B;
memory[1] <= `MC_EMULATE;


memory[4] <= `MC_GO_BREAKPOINT;




memory[8] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR |
		`MC_ALU_NOP | `MC_W_A;
memory[9] <= `MC_SP_MINUS_4;
memory[10] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;


`ifdef ENABLE_CPU_INTERRUPTS





memory[12] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		`MC_MEM_R | `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | 
		((-1 & 127) << `P_ADDR) | `MC_W_PC;
memory[13] <= `MC_SEL_ADDR_PC | `MC_SEL_READ_DATA | `MC_MEM_R |
		 `MC_W_OPCODE; 
memory[14] <= `MC_SP_PLUS_4 | `MC_DECODE | `MC_EXIT_INTERRUPT;
`else
memory[12] <= `MC_GO_BREAKPOINT;
`endif




memory[16] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		`MC_MEM_R | `MC_W_PC; 	
memory[17] <= `MC_SP_PLUS_4;
memory[18] <= `MC_FETCH;




memory[20] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |
		`MC_W_A_MEM | `MC_SP_PLUS_4;
memory[21] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		 `MC_ALU_PLUS | `MC_SEL_ALU_A | `MC_W_A;
memory[22] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;




memory[24] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |
		 `MC_W_A_MEM | `MC_SP_PLUS_4;
memory[25] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		 `MC_ALU_AND |`MC_SEL_ALU_A | `MC_W_A;
memory[26] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;




memory[28] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |
		 `MC_W_A_MEM | `MC_SP_PLUS_4;
memory[29] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		`MC_ALU_OR | `MC_SEL_ALU_A | `MC_W_A;
memory[30] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;



memory[32] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		 `MC_MEM_R | `MC_W_A;
memory[33] <= `MC_SEL_ADDR_A | `MC_SEL_READ_DATA | `MC_MEM_R | `MC_W_A;
memory[34] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;



memory[36] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		 `MC_MEM_R | `MC_ALU_NOT | `MC_W_A; 							
memory[37] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;



memory[40] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		 `MC_MEM_R | `MC_ALU_FLIP | `MC_W_A; 							
memory[41] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;


memory[44] <= `MC_CLEAR_IDIM | `MC_PC_PLUS_1;
memory[45] <= `MC_FETCH;




memory[48] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		 `MC_MEM_R | `MC_W_B;
memory[49] <= `MC_SP_PLUS_4;
memory[50] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM | `MC_SP_PLUS_4;
memory[51] <= `MC_SEL_ADDR_B | `MC_MEM_W | `MC_GO_NEXT;



memory[52] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |
		 `MC_W_SP | `MC_GO_NEXT;







`ifdef ENABLE_BYTE_SELECT
memory[56] <= `MC_CLEAR_IDIM | `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST |
		(0 << `P_ADDR) | `MC_W_B;
memory[57] <= `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
memory[58] <= `MC_SEL_ADDR_B | `MC_MEM_W | `MC_ALU_NOP_B | `MC_W_B |
		`MC_SEL_ALU_MC_CONST | (4 << `P_ADDR);
memory[59] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_W_A |
		`MC_BRANCH | ((116 >> 2) << `P_ADDR);
`else
memory[56] <= `MC_GO_BREAKPOINT;
`endif







`ifdef ENABLE_BYTE_SELECT
memory[60] <= `MC_CLEAR_IDIM | `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST |
		(0 << `P_ADDR) | `MC_W_B;
memory[61] <= `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
memory[62] <= `MC_SEL_ADDR_B | `MC_MEM_W | `MC_ALU_NOP_B | `MC_W_B |
		`MC_SEL_ALU_MC_CONST | (4 << `P_ADDR);
memory[63] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_W_A |
		`MC_BRANCH | ((100 >> 2) << `P_ADDR);
`else
memory[60] <= `MC_GO_BREAKPOINT;
`endif



memory[64] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | (12 << `P_ADDR) | `MC_W_A;
memory[65] <= `MC_SEL_ADDR_B | `MC_MEM_W;
memory[66] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_PC;
memory[67] <= `MC_SP_PLUS_4;
memory[68] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_B;
memory[69] <= `MC_SP_PLUS_4;
memory[70] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_SP;
memory[71] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A;

memory[72] <= `MC_BRANCHIF_A_ZERO | ( (80 >> 2) << `P_ADDR);
memory[73] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | ((-1 & 127) << `P_ADDR) | `MC_W_B;
memory[74] <= `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_W_A;
memory[75] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_SP_PLUS_4;
memory[76] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A |
		`MC_BRANCH | ((72 >> 2) << `P_ADDR);

memory[80] <= `MC_SEL_ADDR_A | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_PC;
memory[81] <= `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) |
		`MC_W_B;
memory[82] <= `MC_SEL_ADDR_B | `MC_MEM_R | `MC_SEL_READ_DATA |
		`MC_W_SP | `MC_FETCH;
		

memory[84] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | (12 << `P_ADDR) | `MC_W_A;
memory[85] <= `MC_SEL_ADDR_B | `MC_MEM_W;
memory[86] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_B;
memory[87] <= `MC_SP_PLUS_4;
memory[88] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_PC;
memory[89] <= `MC_SP_PLUS_4;
memory[90] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_SP;
memory[91] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A;

memory[92] <= `MC_BRANCHIF_A_ZERO | ( (80 >> 2) << `P_ADDR);
memory[93] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | ((-1 & 127) << `P_ADDR) | `MC_W_B;
memory[94] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM |
		`MC_SP_PLUS_4;
memory[95] <= `MC_SEL_ADDR_PC | `MC_MEM_W | `MC_SEL_READ_ADDR |
		`MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) | `MC_W_PC;
memory[96] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A |
		`MC_BRANCH | ((92 >> 2) << `P_ADDR);

`ifdef ENABLE_BYTE_SELECT

memory[100] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | (12 << `P_ADDR) | `MC_W_A;
memory[101] <= `MC_SEL_ADDR_B | `MC_MEM_W;
memory[102] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_B;
memory[103] <= `MC_SP_PLUS_4;
memory[104] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_PC;
memory[105] <= `MC_SP_PLUS_4;
memory[106] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_SP;
memory[107] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A;

memory[108] <= `MC_BRANCHIF_A_ZERO | ( (80 >> 2) << `P_ADDR);
memory[109] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_BYTE | `MC_W_A_MEM |
		`MC_SEL_READ_ADDR | `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | 
		(1 << `P_ADDR) | `MC_W_SP;
memory[110] <= `MC_SEL_ADDR_PC | `MC_MEM_W | `MC_SEL_READ_ADDR |
		`MC_BYTE | `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | 
		(1 << `P_ADDR) | `MC_W_PC;
memory[111] <= `MC_BRANCHIF_A_ZERO | ( (80 >> 2) << `P_ADDR);
memory[112] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | ((-1 & 127) << `P_ADDR) | `MC_W_B;
memory[113] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A |
		`MC_BRANCH | ((108 >> 2) << `P_ADDR);


memory[116] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) | `MC_W_A;
memory[117] <= `MC_SEL_ADDR_B | `MC_MEM_W;
memory[118] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA |
		`MC_W_PC;
memory[119] <= `MC_SP_PLUS_4;
memory[120] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA |
		`MC_W_SP;
memory[121] <= `MC_SEL_ALU_MC_CONST | (0 << `P_ADDR) | `MC_W_B |
		`MC_ALU_NOP_B;
memory[122] <= `MC_SEL_ADDR_PC | `MC_SEL_READ_DATA | `MC_W_A;

memory[124] <= `MC_BRANCHIF_A_ZERO | ((392 >> 2) << `P_ADDR);
		
memory[125] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_HALFWORD |
		`MC_SEL_READ_DATA | `MC_ALU_PLUS | `MC_SEL_ALU_B | `MC_W_B;
memory[126] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | (2 << `P_ADDR) | `MC_W_SP;
memory[127] <= `MC_BRANCH | ((408 >> 2) << `P_ADDR);
`endif






memory[128] <= `MC_CLEAR_IDIM | `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST |
		(0 << `P_ADDR) | `MC_W_B;
memory[129] <= `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
memory[130] <= `MC_SEL_ADDR_B | `MC_MEM_W | `MC_ALU_NOP_B | `MC_W_B |
		`MC_SEL_ALU_MC_CONST | (4 << `P_ADDR);
memory[131] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_W_A |
		`MC_BRANCH | ((84 >> 2) << `P_ADDR);




memory[132] <= `MC_CLEAR_IDIM | `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST |
		(0 << `P_ADDR) | `MC_W_B;
memory[133] <= `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
memory[134] <= `MC_SEL_ADDR_B | `MC_MEM_W | `MC_ALU_NOP_B | `MC_W_B |
		`MC_SEL_ALU_MC_CONST | (4 << `P_ADDR);
memory[135] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_W_A |
		`MC_BRANCH | ((64 >> 2) << `P_ADDR);


`ifdef ENABLE_BYTE_SELECT

memory[136] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		 `MC_MEM_R | `MC_W_A;
memory[137] <= `MC_SEL_ADDR_A | `MC_SEL_READ_DATA | `MC_MEM_R |
		 `MC_W_A | `MC_HALFWORD; 
memory[138] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;
`else
memory[136] <= `MC_GO_BREAKPOINT;
`endif


`ifdef ENABLE_BYTE_SELECT


memory[140] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		 `MC_MEM_R | `MC_W_B; 
memory[141] <= `MC_SP_PLUS_4;
memory[142] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM |
		 `MC_SP_PLUS_4; 
memory[143] <= `MC_SEL_ADDR_B | `MC_MEM_W | `MC_HALFWORD | `MC_GO_NEXT;
`else
memory[140] <= `MC_GO_BREAKPOINT;
`endif




`ifdef ENABLE_CMP
memory[144] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM |
	`MC_SP_PLUS_4;
memory[145] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | `MC_W_B;
memory[146] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B |
	`MC_ALU_CMP_SIGNED | `MC_W_A | ((424>>2) << `P_ADDR) | `MC_BRANCH;
`else
memory[144] <= `MC_GO_BREAKPOINT;
`endif




`ifdef ENABLE_CMP
memory[148] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM |
	`MC_SP_PLUS_4;
memory[149] <= `MC_SEL_ADDR_SP | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_B;
memory[150] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B |
	`MC_ALU_CMP_SIGNED | `MC_W_A | ((420>>2) << `P_ADDR) | `MC_BRANCH;
`else
memory[148] <= `MC_GO_BREAKPOINT;
`endif






`ifdef ENABLE_CMP
memory[152] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM |
	`MC_SP_PLUS_4;
memory[153] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | `MC_W_B;
memory[154] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B |
	`MC_ALU_CMP_UNSIGNED | `MC_W_A | ((424>>2) << `P_ADDR) | `MC_BRANCH;
`else
memory[152] <= `MC_GO_BREAKPOINT;
`endif




`ifdef ENABLE_CMP
memory[156] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM |
	`MC_SP_PLUS_4;
memory[157] <= `MC_SEL_ADDR_SP | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_B;
memory[158] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B |
	`MC_ALU_CMP_UNSIGNED | `MC_W_A | ((420>>2) << `P_ADDR) | `MC_BRANCH;
`else
memory[156] <= `MC_GO_BREAKPOINT;
`endif


memory[160] <= `MC_GO_BREAKPOINT;


`ifdef ENABLE_MULT


memory[164] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |
		 `MC_W_A_MEM | `MC_SP_PLUS_4;
memory[165] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		  `MC_W_B;
memory[166] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B |
		  `MC_ALU_MULT | `MC_W_A;
memory[167] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;
`else
memory[164] <= `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (8 << `P_ADDR) |
		`MC_W_B;
memory[165] <= `MC_EMULATE;
`endif


`ifdef ENABLE_BARREL






memory[168] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		`MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST | (31 << `P_ADDR) | `MC_W_B;
memory[169] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_OR |
		`MC_SEL_ALU_MC_CONST | (32 << `P_ADDR) | `MC_W_B;
memory[170] <= `MC_SP_PLUS_4;
memory[171] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		`MC_W_A_MEM | `MC_BRANCH | ((432 >> 2) << `P_ADDR);
`else
 `ifdef ENABLE_A_SHIFT








memory[168] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		`MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST | 
		(31 << `P_ADDR) | `MC_W_A;
memory[169] <= `MC_SP_PLUS_4;
memory[170] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		`MC_ALU_FLIP | `MC_W_B;
memory[171] <= `MC_BRANCH | ((448 >> 2) << `P_ADDR);
 `else
 memory[168] <= `MC_GO_BREAKPOINT;
 `endif
`endif


`ifdef ENABLE_BARREL






memory[172] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		`MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST |  (31 << `P_ADDR) | `MC_W_B;
memory[173] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_OR |
		`MC_SEL_ALU_MC_CONST | (64 << `P_ADDR) | `MC_W_B;
memory[174] <= `MC_SP_PLUS_4;
memory[175] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		`MC_W_A_MEM | `MC_BRANCH | ((432 >> 2) << `P_ADDR);	
`else








memory[172] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		`MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST | 
		(31 << `P_ADDR) | `MC_W_A;
memory[173] <= `MC_SP_PLUS_4;
memory[174] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		`MC_W_B;
memory[175] <= `MC_BRANCH | ((440 >> 2) << `P_ADDR);
`endif


`ifdef ENABLE_BARREL






memory[176] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		`MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST |  (31 << `P_ADDR) | `MC_W_B;
memory[177] <= `MC_SP_PLUS_4;
memory[178] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		`MC_W_A_MEM | `MC_BRANCH | ((432 >> 2) << `P_ADDR);
`else
 `ifdef ENABLE_A_SHIFT








memory[176] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		`MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST | 
		(31 << `P_ADDR) | `MC_W_A;
memory[177] <= `MC_SP_PLUS_4;
memory[178] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		`MC_ALU_FLIP | `MC_W_B;
memory[179] <= `MC_BRANCH | ((432 >> 2) << `P_ADDR);
 `else
memory[176] <= `MC_GO_BREAKPOINT;
 `endif
`endif





memory[180] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		`MC_MEM_R | `MC_W_B;
memory[181] <= `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | 
		`MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
memory[182] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_ALU_NOP_B |
		`MC_SEL_ALU_B | `MC_W_PC;
memory[183] <= `MC_FETCH;





memory[184] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |
		`MC_SEL_READ_DATA | `MC_ALU_NOT | `MC_W_A;
memory[185] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR |`MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
memory[186] <= `MC_SP_PLUS_4;
memory[187] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		`MC_ALU_PLUS |`MC_SEL_ALU_A | `MC_W_A | 
		( (416 >> 2) << `P_ADDR) | `MC_BRANCH;





memory[188] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		`MC_MEM_R | `MC_ALU_NOT | `MC_W_A;
memory[189] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR |`MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
memory[190] <= `MC_SP_PLUS_4;
memory[191] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		`MC_ALU_PLUS | `MC_SEL_ALU_A | `MC_W_A | 
		( (412 >> 2) << `P_ADDR) | `MC_BRANCH;





memory[192] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		 `MC_MEM_R | `MC_ALU_NOT | `MC_W_A;
memory[193] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		 (1 << `P_ADDR) | `MC_SEL_ALU_MC_CONST | `MC_W_A; 				
memory[194] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;




memory[196] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		`MC_MEM_R | `MC_ALU_NOT | `MC_W_A;
memory[197] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
memory[198] <= `MC_SP_PLUS_4;
memory[199] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		`MC_ALU_PLUS | `MC_SEL_ALU_A | `MC_W_A | ((400>>2) << `P_ADDR) |
		`MC_BRANCH;


`ifdef ENABLE_XOR


memory[200] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |
		 `MC_W_A_MEM | `MC_SP_PLUS_4;
memory[201] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		 `MC_ALU_XOR |`MC_SEL_ALU_A | `MC_W_A;
memory[202] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;
`else








memory[200] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		`MC_ALU_NOT	| `MC_W_A;
memory[201] <= `MC_SP_PLUS_4;
memory[202] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		`MC_ALU_AND | `MC_SEL_ALU_A | `MC_W_A;
memory[203] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_NOT |
		`MC_W_B | `MC_BRANCH | ((428 >> 2) << `P_ADDR);
`endif


`ifdef ENABLE_BYTE_SELECT

memory[204] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		 `MC_MEM_R | `MC_W_A;
memory[205] <= `MC_SEL_ADDR_A | `MC_SEL_READ_DATA | `MC_MEM_R |
		 `MC_W_A | `MC_BYTE;
memory[206] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;
`else







memory[204] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR |
		`MC_W_B;
memory[205] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		`MC_W_PC;
memory[206] <= `MC_SEL_ADDR_PC | `MC_SEL_READ_DATA | `MC_MEM_R |
		`MC_W_OPCODE;
memory[207] <= `MC_SEL_ALU_OPCODE | `MC_ALU_NOP_B | `MC_W_A |
		`MC_BRANCH | ( (396 >> 2) << `P_ADDR);
`endif


`ifdef ENABLE_BYTE_SELECT


memory[208] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		 `MC_MEM_R | `MC_W_B; 
memory[209] <= `MC_SP_PLUS_4;
memory[210] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM |
		 `MC_SP_PLUS_4; 
memory[211] <= `MC_SEL_ADDR_B | `MC_MEM_W | `MC_BYTE | `MC_GO_NEXT;
`else
memory[208] <= `MC_GO_BREAKPOINT;
`endif


`ifdef ENABLE_DIV



memory[212] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |
		 `MC_W_A_MEM | `MC_SP_PLUS_4;
memory[213] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		  `MC_W_B;
memory[214] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B |
		  `MC_ALU_DIV | `MC_W_A;
memory[215] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;
`else
memory[212] <= `MC_GO_BREAKPOINT;
`endif


`ifdef ENABLE_DIV


memory[216] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |
		 `MC_W_A_MEM | `MC_SP_PLUS_4;
memory[217] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		  `MC_W_B;
memory[218] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B |
		  `MC_ALU_MOD | `MC_W_A;
memory[219] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;
`else
memory[216] <= `MC_GO_BREAKPOINT;
`endif






memory[220] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR |
		  `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) |
		  `MC_W_A;
memory[221] <= `MC_SEL_ADDR_A | `MC_MEM_R | `MC_W_A;
memory[222] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A |
		 `MC_BRANCHIF_A_ZERO | ((456>>2) << `P_ADDR);
memory[223] <= `MC_BRANCH | ((460>>2) << `P_ADDR);






memory[224] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR |
		  `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) | 
		  `MC_W_A;				
memory[225] <= `MC_SEL_ADDR_A | `MC_MEM_R | `MC_W_A;
memory[226] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A |
		 `MC_BRANCHIF_A_ZERO | ((460>>2) << `P_ADDR);	
memory[227] <= `MC_BRANCH | ((456>>2) << `P_ADDR);





memory[228] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |
		 `MC_W_A_MEM | `MC_SP_PLUS_4; 
memory[229] <= `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A |
		 `MC_ALU_PLUS | `MC_W_PC; 
memory[230] <= `MC_FETCH;


memory[232] <= `MC_GO_BREAKPOINT;




memory[236] <= `MC_CLEAR_IDIM | `MC_SP_MINUS_4 | `MC_W_A;
memory[237] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;


memory[240] <= `MC_GO_BREAKPOINT;




`ifdef ENABLE_BARREL
memory[244] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |
		`MC_W_A_MEM;
memory[245] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_BARREL |
		`MC_SEL_ALU_MC_CONST | ( 66 << `P_ADDR) | `MC_W_A;
memory[246] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A |
		 `MC_ALU_PLUS | `MC_W_A; 
memory[247] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;
`else
memory[244] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM;
memory[245] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A |
		`MC_ALU_PLUS | `MC_W_A;
memory[246] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A |
		`MC_ALU_PLUS | `MC_W_A;
memory[247] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A |
		 `MC_ALU_PLUS | `MC_W_A | ((400>>2) << `P_ADDR) | `MC_BRANCH;
`endif


memory[248] <= `MC_GO_BREAKPOINT;





memory[252] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		`MC_MEM_R | `MC_W_B; 
memory[253] <= `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;				
memory[254] <= `MC_SEL_ADDR_SP | `MC_MEM_W;
memory[255] <= `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B |
		 `MC_ALU_PLUS | `MC_W_PC | `MC_GO_FETCH;








`ifdef ENABLE_BYTE_SELECT

memory[392] <= `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (0 << `P_ADDR) |
		`MC_W_SP;
memory[393] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA |
		`MC_W_PC;
memory[394] <= `MC_SP_PLUS_4;
memory[395] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA |
		`MC_W_SP;
memory[396] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A;
memory[397] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_FETCH;
`endif

`ifndef ENABLE_BYTE_SELECT



memory[396] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_SEL_ALU_B |
		`MC_ALU_NOP_B | `MC_W_PC;
memory[397] <= `MC_SEL_ADDR_PC | `MC_MEM_R | `MC_W_OPCODE | `MC_GO_NEXT;
`endif


memory[400] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;



`ifdef ENABLE_BYTE_SELECT

memory[408] <= `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | ((-1 & 127) << `P_ADDR) | `MC_W_PC |
		`MC_W_A;
memory[409] <= `MC_BRANCH | ((124 >> 2) << `P_ADDR);
`endif


memory[412] <= `MC_BRANCHIF_A_ZERO | ((468 >> 2) << `P_ADDR);
memory[413] <= `MC_BRANCH | ((464 >> 2) << `P_ADDR);


memory[416] <= `MC_BRANCHIF_A_ZERO | ((464 >> 2) << `P_ADDR);
memory[417] <= `MC_BRANCH | ((468 >> 2) << `P_ADDR);


memory[420] <= `MC_BRANCHIF_A_ZERO | `MC_BRANCHIF_A_NEG | ((464 >> 2) << `P_ADDR);
memory[421] <= `MC_BRANCH | ((468 >> 2) << `P_ADDR);


memory[424] <= `MC_BRANCHIF_A_NEG | ((464 >> 2) << `P_ADDR);
memory[425] <= `MC_BRANCH | ((468 >> 2) << `P_ADDR);


`ifndef ENABLE_XOR
memory[428] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_OR |
		`MC_SEL_ALU_B | `MC_W_A;
memory[429] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;
`endif


`ifdef ENABLE_BARREL
memory[432] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_BARREL |
		`MC_SEL_ALU_B | `MC_W_A;
memory[433] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;
`else
 `ifdef ENABLE_A_SHIFT
memory[432] <= `MC_BRANCHIF_A_ZERO | `MC_BRANCHIF_A_NEG | ((436 >> 2) << `P_ADDR);
memory[433] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | ( (-1 & 127) << `P_ADDR) | `MC_W_A;
memory[434] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_B | `MC_W_B | `MC_BRANCH | ((432 >>2) << `P_ADDR);

memory[436] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_FLIP |
		`MC_W_A;
memory[437] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;
 `endif
`endif


`ifndef ENABLE_BARREL
memory[440] <= `MC_BRANCHIF_A_ZERO | `MC_BRANCHIF_A_NEG | ((444 >> 2) << `P_ADDR);
memory[441] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | ( (-1 & 127) << `P_ADDR) | `MC_W_A;
memory[442] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_B | `MC_W_B | `MC_BRANCH | ((440 >>2) << `P_ADDR);

memory[444] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_NOP |
		`MC_W_A;
memory[445] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;
`endif


`ifdef ENABLE_A_SHIFT
memory[448] <= `MC_BRANCHIF_A_ZERO | `MC_BRANCHIF_A_NEG | ((452 >> 2) << `P_ADDR);
memory[449] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | ( (-1 & 127) << `P_ADDR) | `MC_W_A;
memory[450] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_B | `MC_W_B | `MC_BRANCH | ((448 >>2) << `P_ADDR);

memory[452] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_FLIP |
		`MC_W_A;
memory[453] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;
`endif




memory[456] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | (8 << `P_ADDR) | `MC_W_SP;				
memory[457] <= `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A |
		 `MC_ALU_PLUS | `MC_W_PC; 
memory[458] <= `MC_FETCH;




memory[460] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | (8 << `P_ADDR) | `MC_W_SP; 				
memory[461] <= `MC_PC_PLUS_1;
memory[462] <= `MC_FETCH;



memory[464] <= `MC_SEL_ALU_MC_CONST | `MC_ALU_NOP_B | (1 << `P_ADDR) |
		 `MC_W_A; 
memory[465] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;



memory[468] <= `MC_SEL_ALU_MC_CONST | `MC_ALU_NOP_B | (0 << `P_ADDR) |
		 `MC_W_A; 
memory[469] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;





memory[473] <= 0;
memory[474] <= `MC_CLEAR_IDIM |`MC_SEL_ALU_MC_CONST | `MC_ALU_NOP_B |
		(`SP_START << `P_ADDR) | `MC_W_SP;
memory[475] <= `MC_SEL_ALU_MC_CONST | `MC_ALU_NOP_B | `MC_W_PC |
		(`RESET_VECTOR << `P_ADDR) | `MC_EXIT_INTERRUPT;





memory[476] <= `MC_SEL_ADDR_PC | `MC_SEL_READ_DATA | `MC_MEM_R |
		 `MC_W_OPCODE; 
memory[477] <= `MC_DECODE;




memory[480] <= `MC_PC_PLUS_1;
memory[481] <= `MC_FETCH;





memory[484] <= `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (0 << `P_ADDR) |
		`MC_W_B | `MC_ENTER_INTERRUPT;
memory[485] <= `MC_EMULATE;







memory[488] <= `MC_SP_MINUS_4;
memory[489] <= `MC_SEL_ALU_OPCODE | `MC_ALU_IM | `MC_W_A;
memory[490] <= `MC_SET_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_W |
	 `MC_GO_NEXT;



memory[491] <= `MC_SET_IDIM | `MC_SEL_READ_DATA | `MC_SEL_ADDR_SP |
		 `MC_MEM_R | `MC_SEL_ALU_OPCODE | `MC_ALU_IM | `MC_W_A; 		
memory[492] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;




memory[493] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR |
		 `MC_ALU_PLUS_OFFSET | `MC_SEL_ALU_OPCODE | `MC_W_B;		
memory[494] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM |
		 `MC_SP_PLUS_4; 
memory[495] <= `MC_SEL_ADDR_B | `MC_MEM_W | `MC_GO_NEXT;




memory[496] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR |
		 `MC_ALU_PLUS_OFFSET | `MC_SEL_ALU_OPCODE | `MC_W_A; 			
memory[497] <= `MC_SEL_ADDR_A | `MC_SEL_READ_DATA | `MC_MEM_R | `MC_W_A;
memory[498] <= `MC_SP_MINUS_4;
memory[499] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;



memory[500] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR |
		 `MC_ALU_PLUS_OFFSET | `MC_SEL_ALU_OPCODE | `MC_W_A; 			
memory[501] <= `MC_SEL_ADDR_A | `MC_SEL_READ_DATA | `MC_MEM_R | `MC_W_A;
memory[502] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		 `MC_ALU_PLUS | `MC_SEL_ALU_A | `MC_W_A;
memory[503] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;








memory[504] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR |
		`MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
memory[505] <= `MC_SP_MINUS_4;
memory[506] <= `MC_SEL_ADDR_SP | `MC_MEM_W;
memory[507] <= `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | `MC_W_A |
		(`EMULATION_VECTOR << `P_ADDR);
memory[508] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_B | `MC_W_A;
memory[509] <= `MC_SEL_ADDR_A | `MC_MEM_R | `MC_SEL_READ_DATA |
		`MC_ALU_NOP | `MC_W_PC;
memory[510] <= `MC_FETCH;


end

endmodule
module zpu_core_rom (
	clk,
	addr,
	data
);


input [`MC_MEM_BITS-1:0]	addr;
output [`MC_BITS-1:0]		data;
input 				clk;

wire [`MC_MEM_BITS-1:0]		addr;
reg  [`MC_BITS-1:0]		data;
reg  [`MC_BITS-1:0]		memory[(1<<`MC_MEM_BITS)-1:0];

initial data <= 0;
always @(posedge clk) data <= memory[addr];



integer n;
initial begin

















memory[0] <= `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) |
		`MC_W_B;
memory[1] <= `MC_EMULATE;


memory[4] <= `MC_GO_BREAKPOINT;




memory[8] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR |
		`MC_ALU_NOP | `MC_W_A;
memory[9] <= `MC_SP_MINUS_4;
memory[10] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;


`ifdef ENABLE_CPU_INTERRUPTS





memory[12] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		`MC_MEM_R | `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | 
		((-1 & 127) << `P_ADDR) | `MC_W_PC;
memory[13] <= `MC_SEL_ADDR_PC | `MC_SEL_READ_DATA | `MC_MEM_R |
		 `MC_W_OPCODE; 
memory[14] <= `MC_SP_PLUS_4 | `MC_DECODE | `MC_EXIT_INTERRUPT;
`else
memory[12] <= `MC_GO_BREAKPOINT;
`endif




memory[16] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		`MC_MEM_R | `MC_W_PC; 	
memory[17] <= `MC_SP_PLUS_4;
memory[18] <= `MC_FETCH;




memory[20] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |
		`MC_W_A_MEM | `MC_SP_PLUS_4;
memory[21] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		 `MC_ALU_PLUS | `MC_SEL_ALU_A | `MC_W_A;
memory[22] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;




memory[24] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |
		 `MC_W_A_MEM | `MC_SP_PLUS_4;
memory[25] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		 `MC_ALU_AND |`MC_SEL_ALU_A | `MC_W_A;
memory[26] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;




memory[28] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |
		 `MC_W_A_MEM | `MC_SP_PLUS_4;
memory[29] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		`MC_ALU_OR | `MC_SEL_ALU_A | `MC_W_A;
memory[30] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;



memory[32] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		 `MC_MEM_R | `MC_W_A;
memory[33] <= `MC_SEL_ADDR_A | `MC_SEL_READ_DATA | `MC_MEM_R | `MC_W_A;
memory[34] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;



memory[36] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		 `MC_MEM_R | `MC_ALU_NOT | `MC_W_A; 							
memory[37] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;



memory[40] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		 `MC_MEM_R | `MC_ALU_FLIP | `MC_W_A; 							
memory[41] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;


memory[44] <= `MC_CLEAR_IDIM | `MC_PC_PLUS_1;
memory[45] <= `MC_FETCH;




memory[48] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		 `MC_MEM_R | `MC_W_B;
memory[49] <= `MC_SP_PLUS_4;
memory[50] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM | `MC_SP_PLUS_4;
memory[51] <= `MC_SEL_ADDR_B | `MC_MEM_W | `MC_GO_NEXT;



memory[52] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |
		 `MC_W_SP | `MC_GO_NEXT;







`ifdef ENABLE_BYTE_SELECT
memory[56] <= `MC_CLEAR_IDIM | `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST |
		(0 << `P_ADDR) | `MC_W_B;
memory[57] <= `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
memory[58] <= `MC_SEL_ADDR_B | `MC_MEM_W | `MC_ALU_NOP_B | `MC_W_B |
		`MC_SEL_ALU_MC_CONST | (4 << `P_ADDR);
memory[59] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_W_A |
		`MC_BRANCH | ((116 >> 2) << `P_ADDR);
`else
memory[56] <= `MC_GO_BREAKPOINT;
`endif







`ifdef ENABLE_BYTE_SELECT
memory[60] <= `MC_CLEAR_IDIM | `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST |
		(0 << `P_ADDR) | `MC_W_B;
memory[61] <= `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
memory[62] <= `MC_SEL_ADDR_B | `MC_MEM_W | `MC_ALU_NOP_B | `MC_W_B |
		`MC_SEL_ALU_MC_CONST | (4 << `P_ADDR);
memory[63] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_W_A |
		`MC_BRANCH | ((100 >> 2) << `P_ADDR);
`else
memory[60] <= `MC_GO_BREAKPOINT;
`endif



memory[64] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | (12 << `P_ADDR) | `MC_W_A;
memory[65] <= `MC_SEL_ADDR_B | `MC_MEM_W;
memory[66] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_PC;
memory[67] <= `MC_SP_PLUS_4;
memory[68] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_B;
memory[69] <= `MC_SP_PLUS_4;
memory[70] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_SP;
memory[71] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A;

memory[72] <= `MC_BRANCHIF_A_ZERO | ( (80 >> 2) << `P_ADDR);
memory[73] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | ((-1 & 127) << `P_ADDR) | `MC_W_B;
memory[74] <= `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_W_A;
memory[75] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_SP_PLUS_4;
memory[76] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A |
		`MC_BRANCH | ((72 >> 2) << `P_ADDR);

memory[80] <= `MC_SEL_ADDR_A | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_PC;
memory[81] <= `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) |
		`MC_W_B;
memory[82] <= `MC_SEL_ADDR_B | `MC_MEM_R | `MC_SEL_READ_DATA |
		`MC_W_SP | `MC_FETCH;
		

memory[84] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | (12 << `P_ADDR) | `MC_W_A;
memory[85] <= `MC_SEL_ADDR_B | `MC_MEM_W;
memory[86] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_B;
memory[87] <= `MC_SP_PLUS_4;
memory[88] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_PC;
memory[89] <= `MC_SP_PLUS_4;
memory[90] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_SP;
memory[91] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A;

memory[92] <= `MC_BRANCHIF_A_ZERO | ( (80 >> 2) << `P_ADDR);
memory[93] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | ((-1 & 127) << `P_ADDR) | `MC_W_B;
memory[94] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM |
		`MC_SP_PLUS_4;
memory[95] <= `MC_SEL_ADDR_PC | `MC_MEM_W | `MC_SEL_READ_ADDR |
		`MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) | `MC_W_PC;
memory[96] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A |
		`MC_BRANCH | ((92 >> 2) << `P_ADDR);

`ifdef ENABLE_BYTE_SELECT

memory[100] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | (12 << `P_ADDR) | `MC_W_A;
memory[101] <= `MC_SEL_ADDR_B | `MC_MEM_W;
memory[102] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_B;
memory[103] <= `MC_SP_PLUS_4;
memory[104] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_PC;
memory[105] <= `MC_SP_PLUS_4;
memory[106] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA | `MC_W_SP;
memory[107] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A;

memory[108] <= `MC_BRANCHIF_A_ZERO | ( (80 >> 2) << `P_ADDR);
memory[109] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_BYTE | `MC_W_A_MEM |
		`MC_SEL_READ_ADDR | `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | 
		(1 << `P_ADDR) | `MC_W_SP;
memory[110] <= `MC_SEL_ADDR_PC | `MC_MEM_W | `MC_SEL_READ_ADDR |
		`MC_BYTE | `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | 
		(1 << `P_ADDR) | `MC_W_PC;
memory[111] <= `MC_BRANCHIF_A_ZERO | ( (80 >> 2) << `P_ADDR);
memory[112] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | ((-1 & 127) << `P_ADDR) | `MC_W_B;
memory[113] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A |
		`MC_BRANCH | ((108 >> 2) << `P_ADDR);


memory[116] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) | `MC_W_A;
memory[117] <= `MC_SEL_ADDR_B | `MC_MEM_W;
memory[118] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA |
		`MC_W_PC;
memory[119] <= `MC_SP_PLUS_4;
memory[120] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA |
		`MC_W_SP;
memory[121] <= `MC_SEL_ALU_MC_CONST | (0 << `P_ADDR) | `MC_W_B |
		`MC_ALU_NOP_B;
memory[122] <= `MC_SEL_ADDR_PC | `MC_SEL_READ_DATA | `MC_W_A;

memory[124] <= `MC_BRANCHIF_A_ZERO | ((392 >> 2) << `P_ADDR);
		
memory[125] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_HALFWORD |
		`MC_SEL_READ_DATA | `MC_ALU_PLUS | `MC_SEL_ALU_B | `MC_W_B;
memory[126] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | (2 << `P_ADDR) | `MC_W_SP;
memory[127] <= `MC_BRANCH | ((408 >> 2) << `P_ADDR);
`endif






memory[128] <= `MC_CLEAR_IDIM | `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST |
		(0 << `P_ADDR) | `MC_W_B;
memory[129] <= `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
memory[130] <= `MC_SEL_ADDR_B | `MC_MEM_W | `MC_ALU_NOP_B | `MC_W_B |
		`MC_SEL_ALU_MC_CONST | (4 << `P_ADDR);
memory[131] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_W_A |
		`MC_BRANCH | ((84 >> 2) << `P_ADDR);




memory[132] <= `MC_CLEAR_IDIM | `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST |
		(0 << `P_ADDR) | `MC_W_B;
memory[133] <= `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
memory[134] <= `MC_SEL_ADDR_B | `MC_MEM_W | `MC_ALU_NOP_B | `MC_W_B |
		`MC_SEL_ALU_MC_CONST | (4 << `P_ADDR);
memory[135] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_W_A |
		`MC_BRANCH | ((64 >> 2) << `P_ADDR);


`ifdef ENABLE_BYTE_SELECT

memory[136] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		 `MC_MEM_R | `MC_W_A;
memory[137] <= `MC_SEL_ADDR_A | `MC_SEL_READ_DATA | `MC_MEM_R |
		 `MC_W_A | `MC_HALFWORD; 
memory[138] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;
`else
memory[136] <= `MC_GO_BREAKPOINT;
`endif


`ifdef ENABLE_BYTE_SELECT


memory[140] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		 `MC_MEM_R | `MC_W_B; 
memory[141] <= `MC_SP_PLUS_4;
memory[142] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM |
		 `MC_SP_PLUS_4; 
memory[143] <= `MC_SEL_ADDR_B | `MC_MEM_W | `MC_HALFWORD | `MC_GO_NEXT;
`else
memory[140] <= `MC_GO_BREAKPOINT;
`endif




`ifdef ENABLE_CMP
memory[144] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM |
	`MC_SP_PLUS_4;
memory[145] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | `MC_W_B;
memory[146] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B |
	`MC_ALU_CMP_SIGNED | `MC_W_A | ((424>>2) << `P_ADDR) | `MC_BRANCH;
`else
memory[144] <= `MC_GO_BREAKPOINT;
`endif




`ifdef ENABLE_CMP
memory[148] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM |
	`MC_SP_PLUS_4;
memory[149] <= `MC_SEL_ADDR_SP | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_B;
memory[150] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B |
	`MC_ALU_CMP_SIGNED | `MC_W_A | ((420>>2) << `P_ADDR) | `MC_BRANCH;
`else
memory[148] <= `MC_GO_BREAKPOINT;
`endif






`ifdef ENABLE_CMP
memory[152] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM |
	`MC_SP_PLUS_4;
memory[153] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R | `MC_W_B;
memory[154] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B |
	`MC_ALU_CMP_UNSIGNED | `MC_W_A | ((424>>2) << `P_ADDR) | `MC_BRANCH;
`else
memory[152] <= `MC_GO_BREAKPOINT;
`endif




`ifdef ENABLE_CMP
memory[156] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM |
	`MC_SP_PLUS_4;
memory[157] <= `MC_SEL_ADDR_SP | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_B;
memory[158] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B |
	`MC_ALU_CMP_UNSIGNED | `MC_W_A | ((420>>2) << `P_ADDR) | `MC_BRANCH;
`else
memory[156] <= `MC_GO_BREAKPOINT;
`endif


memory[160] <= `MC_GO_BREAKPOINT;


`ifdef ENABLE_MULT


memory[164] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |
		 `MC_W_A_MEM | `MC_SP_PLUS_4;
memory[165] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		  `MC_W_B;
memory[166] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B |
		  `MC_ALU_MULT | `MC_W_A;
memory[167] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;
`else
memory[164] <= `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (8 << `P_ADDR) |
		`MC_W_B;
memory[165] <= `MC_EMULATE;
`endif


`ifdef ENABLE_BARREL






memory[168] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		`MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST | (31 << `P_ADDR) | `MC_W_B;
memory[169] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_OR |
		`MC_SEL_ALU_MC_CONST | (32 << `P_ADDR) | `MC_W_B;
memory[170] <= `MC_SP_PLUS_4;
memory[171] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		`MC_W_A_MEM | `MC_BRANCH | ((432 >> 2) << `P_ADDR);
`else
 `ifdef ENABLE_A_SHIFT








memory[168] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		`MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST | 
		(31 << `P_ADDR) | `MC_W_A;
memory[169] <= `MC_SP_PLUS_4;
memory[170] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		`MC_ALU_FLIP | `MC_W_B;
memory[171] <= `MC_BRANCH | ((448 >> 2) << `P_ADDR);
 `else
 memory[168] <= `MC_GO_BREAKPOINT;
 `endif
`endif


`ifdef ENABLE_BARREL






memory[172] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		`MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST |  (31 << `P_ADDR) | `MC_W_B;
memory[173] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_OR |
		`MC_SEL_ALU_MC_CONST | (64 << `P_ADDR) | `MC_W_B;
memory[174] <= `MC_SP_PLUS_4;
memory[175] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		`MC_W_A_MEM | `MC_BRANCH | ((432 >> 2) << `P_ADDR);	
`else








memory[172] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		`MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST | 
		(31 << `P_ADDR) | `MC_W_A;
memory[173] <= `MC_SP_PLUS_4;
memory[174] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		`MC_W_B;
memory[175] <= `MC_BRANCH | ((440 >> 2) << `P_ADDR);
`endif


`ifdef ENABLE_BARREL






memory[176] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		`MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST |  (31 << `P_ADDR) | `MC_W_B;
memory[177] <= `MC_SP_PLUS_4;
memory[178] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		`MC_W_A_MEM | `MC_BRANCH | ((432 >> 2) << `P_ADDR);
`else
 `ifdef ENABLE_A_SHIFT








memory[176] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		`MC_MEM_R | `MC_ALU_AND | `MC_SEL_ALU_MC_CONST | 
		(31 << `P_ADDR) | `MC_W_A;
memory[177] <= `MC_SP_PLUS_4;
memory[178] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		`MC_ALU_FLIP | `MC_W_B;
memory[179] <= `MC_BRANCH | ((432 >> 2) << `P_ADDR);
 `else
memory[176] <= `MC_GO_BREAKPOINT;
 `endif
`endif





memory[180] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		`MC_MEM_R | `MC_W_B;
memory[181] <= `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS | 
		`MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
memory[182] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_ALU_NOP_B |
		`MC_SEL_ALU_B | `MC_W_PC;
memory[183] <= `MC_FETCH;





memory[184] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |
		`MC_SEL_READ_DATA | `MC_ALU_NOT | `MC_W_A;
memory[185] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR |`MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
memory[186] <= `MC_SP_PLUS_4;
memory[187] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		`MC_ALU_PLUS |`MC_SEL_ALU_A | `MC_W_A | 
		( (416 >> 2) << `P_ADDR) | `MC_BRANCH;





memory[188] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		`MC_MEM_R | `MC_ALU_NOT | `MC_W_A;
memory[189] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR |`MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
memory[190] <= `MC_SP_PLUS_4;
memory[191] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		`MC_ALU_PLUS | `MC_SEL_ALU_A | `MC_W_A | 
		( (412 >> 2) << `P_ADDR) | `MC_BRANCH;





memory[192] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		 `MC_MEM_R | `MC_ALU_NOT | `MC_W_A;
memory[193] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		 (1 << `P_ADDR) | `MC_SEL_ALU_MC_CONST | `MC_W_A; 				
memory[194] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;




memory[196] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		`MC_MEM_R | `MC_ALU_NOT | `MC_W_A;
memory[197] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
memory[198] <= `MC_SP_PLUS_4;
memory[199] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		`MC_ALU_PLUS | `MC_SEL_ALU_A | `MC_W_A | ((400>>2) << `P_ADDR) |
		`MC_BRANCH;


`ifdef ENABLE_XOR


memory[200] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |
		 `MC_W_A_MEM | `MC_SP_PLUS_4;
memory[201] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		 `MC_ALU_XOR |`MC_SEL_ALU_A | `MC_W_A;
memory[202] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;
`else








memory[200] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		`MC_ALU_NOT	| `MC_W_A;
memory[201] <= `MC_SP_PLUS_4;
memory[202] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		`MC_ALU_AND | `MC_SEL_ALU_A | `MC_W_A;
memory[203] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_NOT |
		`MC_W_B | `MC_BRANCH | ((428 >> 2) << `P_ADDR);
`endif


`ifdef ENABLE_BYTE_SELECT

memory[204] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		 `MC_MEM_R | `MC_W_A;
memory[205] <= `MC_SEL_ADDR_A | `MC_SEL_READ_DATA | `MC_MEM_R |
		 `MC_W_A | `MC_BYTE;
memory[206] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;
`else







memory[204] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR |
		`MC_W_B;
memory[205] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		`MC_W_PC;
memory[206] <= `MC_SEL_ADDR_PC | `MC_SEL_READ_DATA | `MC_MEM_R |
		`MC_W_OPCODE;
memory[207] <= `MC_SEL_ALU_OPCODE | `MC_ALU_NOP_B | `MC_W_A |
		`MC_BRANCH | ( (396 >> 2) << `P_ADDR);
`endif


`ifdef ENABLE_BYTE_SELECT


memory[208] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		 `MC_MEM_R | `MC_W_B; 
memory[209] <= `MC_SP_PLUS_4;
memory[210] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM |
		 `MC_SP_PLUS_4; 
memory[211] <= `MC_SEL_ADDR_B | `MC_MEM_W | `MC_BYTE | `MC_GO_NEXT;
`else
memory[208] <= `MC_GO_BREAKPOINT;
`endif


`ifdef ENABLE_DIV



memory[212] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |
		 `MC_W_A_MEM | `MC_SP_PLUS_4;
memory[213] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		  `MC_W_B;
memory[214] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B |
		  `MC_ALU_DIV | `MC_W_A;
memory[215] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;
`else
memory[212] <= `MC_GO_BREAKPOINT;
`endif


`ifdef ENABLE_DIV


memory[216] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |
		 `MC_W_A_MEM | `MC_SP_PLUS_4;
memory[217] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		  `MC_W_B;
memory[218] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B |
		  `MC_ALU_MOD | `MC_W_A;
memory[219] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;
`else
memory[216] <= `MC_GO_BREAKPOINT;
`endif






memory[220] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR |
		  `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) |
		  `MC_W_A;
memory[221] <= `MC_SEL_ADDR_A | `MC_MEM_R | `MC_W_A;
memory[222] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A |
		 `MC_BRANCHIF_A_ZERO | ((456>>2) << `P_ADDR);
memory[223] <= `MC_BRANCH | ((460>>2) << `P_ADDR);






memory[224] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR |
		  `MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | (4 << `P_ADDR) | 
		  `MC_W_A;				
memory[225] <= `MC_SEL_ADDR_A | `MC_MEM_R | `MC_W_A;
memory[226] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A |
		 `MC_BRANCHIF_A_ZERO | ((460>>2) << `P_ADDR);	
memory[227] <= `MC_BRANCH | ((456>>2) << `P_ADDR);





memory[228] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |
		 `MC_W_A_MEM | `MC_SP_PLUS_4; 
memory[229] <= `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A |
		 `MC_ALU_PLUS | `MC_W_PC; 
memory[230] <= `MC_FETCH;


memory[232] <= `MC_GO_BREAKPOINT;




memory[236] <= `MC_CLEAR_IDIM | `MC_SP_MINUS_4 | `MC_W_A;
memory[237] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;


memory[240] <= `MC_GO_BREAKPOINT;




`ifdef ENABLE_BARREL
memory[244] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R |
		`MC_W_A_MEM;
memory[245] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_BARREL |
		`MC_SEL_ALU_MC_CONST | ( 66 << `P_ADDR) | `MC_W_A;
memory[246] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A |
		 `MC_ALU_PLUS | `MC_W_A; 
memory[247] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;
`else
memory[244] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM;
memory[245] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A |
		`MC_ALU_PLUS | `MC_W_A;
memory[246] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A |
		`MC_ALU_PLUS | `MC_W_A;
memory[247] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A |
		 `MC_ALU_PLUS | `MC_W_A | ((400>>2) << `P_ADDR) | `MC_BRANCH;
`endif


memory[248] <= `MC_GO_BREAKPOINT;





memory[252] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA |
		`MC_MEM_R | `MC_W_B; 
memory[253] <= `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;				
memory[254] <= `MC_SEL_ADDR_SP | `MC_MEM_W;
memory[255] <= `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_SEL_ALU_B |
		 `MC_ALU_PLUS | `MC_W_PC | `MC_GO_FETCH;








`ifdef ENABLE_BYTE_SELECT

memory[392] <= `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (0 << `P_ADDR) |
		`MC_W_SP;
memory[393] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA |
		`MC_W_PC;
memory[394] <= `MC_SP_PLUS_4;
memory[395] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_SEL_READ_DATA |
		`MC_W_SP;
memory[396] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_W_A;
memory[397] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_FETCH;
`endif

`ifndef ENABLE_BYTE_SELECT



memory[396] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_SEL_ALU_B |
		`MC_ALU_NOP_B | `MC_W_PC;
memory[397] <= `MC_SEL_ADDR_PC | `MC_MEM_R | `MC_W_OPCODE | `MC_GO_NEXT;
`endif


memory[400] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;



`ifdef ENABLE_BYTE_SELECT

memory[408] <= `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | ((-1 & 127) << `P_ADDR) | `MC_W_PC |
		`MC_W_A;
memory[409] <= `MC_BRANCH | ((124 >> 2) << `P_ADDR);
`endif


memory[412] <= `MC_BRANCHIF_A_ZERO | ((468 >> 2) << `P_ADDR);
memory[413] <= `MC_BRANCH | ((464 >> 2) << `P_ADDR);


memory[416] <= `MC_BRANCHIF_A_ZERO | ((464 >> 2) << `P_ADDR);
memory[417] <= `MC_BRANCH | ((468 >> 2) << `P_ADDR);


memory[420] <= `MC_BRANCHIF_A_ZERO | `MC_BRANCHIF_A_NEG | ((464 >> 2) << `P_ADDR);
memory[421] <= `MC_BRANCH | ((468 >> 2) << `P_ADDR);


memory[424] <= `MC_BRANCHIF_A_NEG | ((464 >> 2) << `P_ADDR);
memory[425] <= `MC_BRANCH | ((468 >> 2) << `P_ADDR);


`ifndef ENABLE_XOR
memory[428] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_OR |
		`MC_SEL_ALU_B | `MC_W_A;
memory[429] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;
`endif


`ifdef ENABLE_BARREL
memory[432] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_BARREL |
		`MC_SEL_ALU_B | `MC_W_A;
memory[433] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;
`else
 `ifdef ENABLE_A_SHIFT
memory[432] <= `MC_BRANCHIF_A_ZERO | `MC_BRANCHIF_A_NEG | ((436 >> 2) << `P_ADDR);
memory[433] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | ( (-1 & 127) << `P_ADDR) | `MC_W_A;
memory[434] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_B | `MC_W_B | `MC_BRANCH | ((432 >>2) << `P_ADDR);

memory[436] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_FLIP |
		`MC_W_A;
memory[437] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;
 `endif
`endif


`ifndef ENABLE_BARREL
memory[440] <= `MC_BRANCHIF_A_ZERO | `MC_BRANCHIF_A_NEG | ((444 >> 2) << `P_ADDR);
memory[441] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | ( (-1 & 127) << `P_ADDR) | `MC_W_A;
memory[442] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_B | `MC_W_B | `MC_BRANCH | ((440 >>2) << `P_ADDR);

memory[444] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_NOP |
		`MC_W_A;
memory[445] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;
`endif


`ifdef ENABLE_A_SHIFT
memory[448] <= `MC_BRANCHIF_A_ZERO | `MC_BRANCHIF_A_NEG | ((452 >> 2) << `P_ADDR);
memory[449] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | ( (-1 & 127) << `P_ADDR) | `MC_W_A;
memory[450] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_B | `MC_W_B | `MC_BRANCH | ((448 >>2) << `P_ADDR);

memory[452] <= `MC_SEL_ADDR_B | `MC_SEL_READ_ADDR | `MC_ALU_FLIP |
		`MC_W_A;
memory[453] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;
`endif




memory[456] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | (8 << `P_ADDR) | `MC_W_SP;				
memory[457] <= `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR | `MC_SEL_ALU_A |
		 `MC_ALU_PLUS | `MC_W_PC; 
memory[458] <= `MC_FETCH;




memory[460] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_MC_CONST | (8 << `P_ADDR) | `MC_W_SP; 				
memory[461] <= `MC_PC_PLUS_1;
memory[462] <= `MC_FETCH;



memory[464] <= `MC_SEL_ALU_MC_CONST | `MC_ALU_NOP_B | (1 << `P_ADDR) |
		 `MC_W_A; 
memory[465] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;



memory[468] <= `MC_SEL_ALU_MC_CONST | `MC_ALU_NOP_B | (0 << `P_ADDR) |
		 `MC_W_A; 
memory[469] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;





memory[473] <= 0;
memory[474] <= `MC_CLEAR_IDIM |`MC_SEL_ALU_MC_CONST | `MC_ALU_NOP_B |
		(`SP_START << `P_ADDR) | `MC_W_SP;
memory[475] <= `MC_SEL_ALU_MC_CONST | `MC_ALU_NOP_B | `MC_W_PC |
		(`RESET_VECTOR << `P_ADDR) | `MC_EXIT_INTERRUPT;





memory[476] <= `MC_SEL_ADDR_PC | `MC_SEL_READ_DATA | `MC_MEM_R |
		 `MC_W_OPCODE; 
memory[477] <= `MC_DECODE;




memory[480] <= `MC_PC_PLUS_1;
memory[481] <= `MC_FETCH;





memory[484] <= `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | (0 << `P_ADDR) |
		`MC_W_B | `MC_ENTER_INTERRUPT;
memory[485] <= `MC_EMULATE;







memory[488] <= `MC_SP_MINUS_4;
memory[489] <= `MC_SEL_ALU_OPCODE | `MC_ALU_IM | `MC_W_A;
memory[490] <= `MC_SET_IDIM | `MC_SEL_ADDR_SP | `MC_MEM_W |
	 `MC_GO_NEXT;



memory[491] <= `MC_SET_IDIM | `MC_SEL_READ_DATA | `MC_SEL_ADDR_SP |
		 `MC_MEM_R | `MC_SEL_ALU_OPCODE | `MC_ALU_IM | `MC_W_A; 		
memory[492] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;




memory[493] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR |
		 `MC_ALU_PLUS_OFFSET | `MC_SEL_ALU_OPCODE | `MC_W_B;		
memory[494] <= `MC_SEL_ADDR_SP | `MC_MEM_R | `MC_W_A_MEM |
		 `MC_SP_PLUS_4; 
memory[495] <= `MC_SEL_ADDR_B | `MC_MEM_W | `MC_GO_NEXT;




memory[496] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR |
		 `MC_ALU_PLUS_OFFSET | `MC_SEL_ALU_OPCODE | `MC_W_A; 			
memory[497] <= `MC_SEL_ADDR_A | `MC_SEL_READ_DATA | `MC_MEM_R | `MC_W_A;
memory[498] <= `MC_SP_MINUS_4;
memory[499] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;



memory[500] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_SP | `MC_SEL_READ_ADDR |
		 `MC_ALU_PLUS_OFFSET | `MC_SEL_ALU_OPCODE | `MC_W_A; 			
memory[501] <= `MC_SEL_ADDR_A | `MC_SEL_READ_DATA | `MC_MEM_R | `MC_W_A;
memory[502] <= `MC_SEL_ADDR_SP | `MC_SEL_READ_DATA | `MC_MEM_R |
		 `MC_ALU_PLUS | `MC_SEL_ALU_A | `MC_W_A;
memory[503] <= `MC_SEL_ADDR_SP | `MC_MEM_W | `MC_GO_NEXT;








memory[504] <= `MC_CLEAR_IDIM | `MC_SEL_ADDR_PC | `MC_SEL_READ_ADDR |
		`MC_ALU_PLUS | `MC_SEL_ALU_MC_CONST | (1 << `P_ADDR) | `MC_W_A;
memory[505] <= `MC_SP_MINUS_4;
memory[506] <= `MC_SEL_ADDR_SP | `MC_MEM_W;
memory[507] <= `MC_ALU_NOP_B | `MC_SEL_ALU_MC_CONST | `MC_W_A |
		(`EMULATION_VECTOR << `P_ADDR);
memory[508] <= `MC_SEL_ADDR_A | `MC_SEL_READ_ADDR | `MC_ALU_PLUS |
		`MC_SEL_ALU_B | `MC_W_A;
memory[509] <= `MC_SEL_ADDR_A | `MC_MEM_R | `MC_SEL_READ_DATA |
		`MC_ALU_NOP | `MC_W_PC;
memory[510] <= `MC_FETCH;


end

endmodule