data/full_repos/permissive/489642764/src/wb_ctrl/tb.v
1: b'%Error: data/full_repos/permissive/489642764/src/wb_ctrl/tb.v:53: syntax error, unexpected \'@\'\n  @ (negedge arst_n);\n  ^\n%Error: data/full_repos/permissive/489642764/src/wb_ctrl/tb.v:56: syntax error, unexpected \'@\'\n  @ (posedge arst_n);\n  ^\n%Error: data/full_repos/permissive/489642764/src/wb_ctrl/tb.v:59: syntax error, unexpected \'@\'\n   @ ( posedge clk50 );\n   ^\n%Error: data/full_repos/permissive/489642764/src/wb_ctrl/tb.v:66: syntax error, unexpected \'@\'\n    @ (posedge clk50);\n    ^\n%Error: data/full_repos/permissive/489642764/src/wb_ctrl/tb.v:70: syntax error, unexpected \'@\'\n    @ (posedge clk50);\n    ^\n%Error: data/full_repos/permissive/489642764/src/wb_ctrl/tb.v:73: syntax error, unexpected \'@\'\n   @ (posedge clk50);\n   ^\n%Error: data/full_repos/permissive/489642764/src/wb_ctrl/tb.v:80: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("dump.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/489642764/src/wb_ctrl/tb.v:81: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(1, dut);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/489642764/src/wb_ctrl/tb.v:83: syntax error, unexpected \'@\'\n   @ ( posedge clk50 );\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/489642764/src/wb_ctrl/tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n  #(1.24 * 2000);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/489642764/src/wb_ctrl/tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n  #(18.9 * 2000);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489642764/src/wb_ctrl/tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n  #(2000/2);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489642764/src/wb_ctrl/tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n  #(2000/2);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489642764/src/wb_ctrl/tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n  #(800/2);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/489642764/src/wb_ctrl/tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n  #(800/2);\n  ^\n%Error: Exiting due to 9 error(s), 6 warning(s)\n'
module tb;
	wire            arst_n;
	wire            clk50;
	wire            clk125;
	wire            clk50_srst_n;
	wire            clk125_srst_n;

	wire    [11:0]  wb_adr_dut2tb;
	wire    [31:0]  wb_dat_tb2dut;
	wire    [31:0]  wb_dat_dut2tb;
	wire            wb_we_dut2tb;
	wire    [3:0]   wb_sel_dut2tb;
	wire            wb_stb_dut2tb;
	wire            wb_ack_tb2dut;
	wire            wb_cyc_dut2tb;

	reg     [31:0]  wb_dat_tb2dut_r;
	reg             wb_ack_tb2dut_r;
	assign wb_dat_tb2dut = wb_dat_tb2dut_r;
	assign wb_ack_tb2dut = wb_ack_tb2dut_r;


	clk_gen clk_gen_inst(
		.arst_n       (arst_n),
		.clk50        (clk50),
		.clk125       (clk125),
		.clk50_srst_n (clk50_srst_n),
		.clk125_srst_n(clk125_srst_n)
	);


	wb_ctrl dut(
		.wb_rst_i (arst_n),
		.wb_clk_i (clk50),
		.wb_adr_o (wb_adr_dut2tb),
		.wb_dat_i (wb_dat_tb2dut),
		.wb_dat_o (wb_dat_dut2tb),
		.wb_we_o  (wb_we_dut2tb),
		.wb_sel_o (wb_sel_dut2tb),
		.wb_stb_o (wb_stb_dut2tb),
		.wb_ack_i (wb_ack_tb2dut),
		.wb_cyc_o (wb_cyc_dut2tb)
	);


	integer i;
	initial begin
		@ (negedge arst_n);
		wb_dat_tb2dut_r = 32'd0;
		wb_ack_tb2dut_r = 1'b0;
		@ (posedge arst_n);

		for ( i = 0 ; i < 30 ; i = i + 1 ) begin
			@ ( posedge clk50 );
		end

		@ (posedge clk50);

		while (1'b1) begin
			if (wb_stb_dut2tb | wb_we_dut2tb) begin
				@ (posedge clk50);
				@ (posedge clk50);
				@ (posedge clk50);
				wb_ack_tb2dut_r = 1'b1;
				@ (posedge clk50);
				wb_ack_tb2dut_r = 1'b0;
			end
			@ (posedge clk50);
		end
	end


	integer k;
	initial begin
		$dumpfile("dump.vcd");
		$dumpvars(1, dut);
		for ( k = 0 ; k < 1000 ; k = k + 1 ) begin
			@ ( posedge clk50 );
		end
		$finish;
	end
endmodule
module tb;

	wire            arst_n;
	wire            clk50;
	wire            clk125;
	wire            clk50_srst_n;
	wire            clk125_srst_n;

	wire    [11:0]  wb_adr_dut2tb;
	wire    [31:0]  wb_dat_tb2dut;
	wire    [31:0]  wb_dat_dut2tb;
	wire            wb_we_dut2tb;
	wire    [3:0]   wb_sel_dut2tb;
	wire            wb_stb_dut2tb;
	wire            wb_ack_tb2dut;
	wire            wb_cyc_dut2tb;

	reg     [31:0]  wb_dat_tb2dut_r;
	reg             wb_ack_tb2dut_r;
	assign wb_dat_tb2dut = wb_dat_tb2dut_r;
	assign wb_ack_tb2dut = wb_ack_tb2dut_r;


	clk_gen clk_gen_inst(
		.arst_n       (arst_n),
		.clk50        (clk50),
		.clk125       (clk125),
		.clk50_srst_n (clk50_srst_n),
		.clk125_srst_n(clk125_srst_n)
	);


	wb_ctrl dut(
		.wb_rst_i (arst_n),
		.wb_clk_i (clk50),
		.wb_adr_o (wb_adr_dut2tb),
		.wb_dat_i (wb_dat_tb2dut),
		.wb_dat_o (wb_dat_dut2tb),
		.wb_we_o  (wb_we_dut2tb),
		.wb_sel_o (wb_sel_dut2tb),
		.wb_stb_o (wb_stb_dut2tb),
		.wb_ack_i (wb_ack_tb2dut),
		.wb_cyc_o (wb_cyc_dut2tb)
	);


	integer i;
	initial begin
		@ (negedge arst_n);
		wb_dat_tb2dut_r = 32'd0;
		wb_ack_tb2dut_r = 1'b0;
		@ (posedge arst_n);

		for ( i = 0 ; i < 30 ; i = i + 1 ) begin
			@ ( posedge clk50 );
		end

		@ (posedge clk50);

		while (1'b1) begin
			if (wb_stb_dut2tb | wb_we_dut2tb) begin
				@ (posedge clk50);
				@ (posedge clk50);
				@ (posedge clk50);
				wb_ack_tb2dut_r = 1'b1;
				@ (posedge clk50);
				wb_ack_tb2dut_r = 1'b0;
			end
			@ (posedge clk50);
		end
	end


	integer k;
	initial begin
		$dumpfile("dump.vcd");
		$dumpvars(1, dut);
		for ( k = 0 ; k < 1000 ; k = k + 1 ) begin
			@ ( posedge clk50 );
		end
		$finish;
	end
endmodule