data/full_repos/permissive/441359809/src/yosys/manual/PRESENTATION_ExAdv/macc_simple_test_02.v
data/verilator_xmls/7686e577-d8b4-47e2-b4c6-a20d88417d4d.xml
module test(a, b, c, d, x, y);
input [15:0] a, b, c, d;
input [31:0] x;
output [31:0] y;
assign y = a*b + (c*d + x);
endmodule
module test(a, b, c, d, x, y);

input [15:0] a, b, c, d;
input [31:0] x;
output [31:0] y;
assign y = a*b + (c*d + x);
endmodule