data/full_repos/permissive/468612001/Week03/full_adder/full_adder.v
data/verilator_xmls/1a44e04c-c63f-415c-907f-ac10657b9f44.xml
module full_adder(a, b, cin, sum, cout);
	input a, b, cin;
	output sum, cout;
	wire s1, c1, c2;
	
	half_adder ha1(a, b, s1, c1);
	half_adder ha2(cin, s1, sum, c2);
	or(cout, c1, c2);
	
endmodule
module full_adder(a, b, cin, sum, cout);

	input a, b, cin;
	output sum, cout;
	wire s1, c1, c2;
	
	half_adder ha1(a, b, s1, c1);
	half_adder ha2(cin, s1, sum, c2);
	or(cout, c1, c2);
	
endmodule