data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/MemIntrControl.v
1: b"%Error: data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/MemIntrControl.v:54: Cannot find file containing module: 'InputNormalizer'\n  InputNormalizer inorm(\n  ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new,data/full_repos/permissive/42815087/InputNormalizer\n             data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new,data/full_repos/permissive/42815087/InputNormalizer.v\n             data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new,data/full_repos/permissive/42815087/InputNormalizer.sv\n             InputNormalizer\n             InputNormalizer.v\n             InputNormalizer.sv\n             obj_dir/InputNormalizer\n             obj_dir/InputNormalizer.v\n             obj_dir/InputNormalizer.sv\n%Error: data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/MemIntrControl.v:81: Cannot find file containing module: 'MemoryInterface'\n  MemoryInterface memInt(\n  ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/MemIntrControl.v:101: Cannot find file containing module: 'SyzMem'\n  SyzMem bram(\n  ^~~~~~\n%Error: Exiting due to 3 error(s)\n"
module MemIntrControl(
    input clk,
    input [15:0] sw,
    input btnL,
    input btnU,
    input btnC,
    input btnD,
    input btnR,
    inout [3:0] JB,
    output [15:0] led,
    output [6:0] seg,
    output [3:0] an,
    output dp
  );




  
  reg [3:0] regNum;
  reg [15:0] regData;
  reg intrRdEn;
  reg intrWrEn;
  
  wire [15:0] switches;
  wire buttonLeft;
  wire buttonUp;
  wire buttonCenter;
  wire buttonDown;
  wire buttonRight;
  wire wBusy;
  InputNormalizer inorm(
    .clk(clk),
    .switchIn(sw[15:0]),
    .btnLIn(btnL),
    .btnUIn(btnU),
    .btnCIn(btnC),
    .btnDIn(btnD),
    .btnRIn(btnR),
    .segsIn(regData[15:0]),
    .dpIn(),
    .switchOut(switches[15:0]),
    .btnLOut(buttonLeft),
    .btnUOut(buttonUp),
    .btnCOut(buttonCenter),
    .btnDOut(buttonDown),
    .btnROut(buttonRight),
    .segsOut(seg[6:0]),
    .anOut(an[3:0]),
    .dpOut(dp)
  );
  
  wire [15:0] wDataMemToIntr;
  wire [15:0] wDataIntrToMem;
  wire [15:0] wAddrIntrToMem;
  wire [15:0] wDataIntrToSegs;
  wire wMemRdEn;
  wire wMemWrEn;
  MemoryInterface memInt(
    .cpuClock(clk),
    .periphSelect(1'b1),
    .dIn(regData[15:0]),
    .regSelect(regNum[3:0]),
    .readEn(intrRdEn),
    .writeEn(intrWrEn),
    .reset(1'b0),
    .exec(buttonCenter),
    .dataFromMem(wDataMemToIntr[15:0]),
    .debugRegSelect(),
    .memStatus(wBusy),
    .dOut(wDataIntrToSegs[15:0]),
    .dataToMem(wDataIntrToMem[15:0]),
    .addrToMem(wAddrIntrToMem[15:0]),
    .memReadEn(wMemRdEn),
    .memWriteEn(wMemWrEn),
    .debugOut()
  );
  
  SyzMem bram(
    .memClk(clk),
    .addr(wAddrIntrToMem[15:0]),
    .dIn(wDataIntrToMem[15:0]),
    .en(1'b1),
    .readEn(wMemRdEn),
    .writeEn(wMemWrEn),
    .dOut(wDataMemToIntr[15:0]),
    .busy(wBusy)
  );
  
  always @ (posedge clk) begin
    if(buttonUp == 1'b1) begin
      regNum[3:0] = switches[3:0];
    end
    
    if(buttonDown == 1'b1) begin
      regData[15:0] = switches[15:0];
    end
    
    if(buttonLeft == 1'b1) begin
      intrRdEn = 1'b1;
      regData[15:0] = wDataIntrToSegs[15:0];
    end else begin
      intrRdEn = 1'b0;
    end
    
    if(buttonRight == 1'b1) begin
      intrWrEn = 1'b1;
    end else begin
      intrWrEn = 1'b0;
    end
  end
  
  assign led[15:0] = switches[15:0];
  
endmodule
module MemIntrControl(
    input clk,
    input [15:0] sw,
    input btnL,
    input btnU,
    input btnC,
    input btnD,
    input btnR,
    inout [3:0] JB,
    output [15:0] led,
    output [6:0] seg,
    output [3:0] an,
    output dp
  );





  
  reg [3:0] regNum;
  reg [15:0] regData;
  reg intrRdEn;
  reg intrWrEn;
  
  wire [15:0] switches;
  wire buttonLeft;
  wire buttonUp;
  wire buttonCenter;
  wire buttonDown;
  wire buttonRight;
  wire wBusy;
  InputNormalizer inorm(
    .clk(clk),
    .switchIn(sw[15:0]),
    .btnLIn(btnL),
    .btnUIn(btnU),
    .btnCIn(btnC),
    .btnDIn(btnD),
    .btnRIn(btnR),
    .segsIn(regData[15:0]),
    .dpIn(),
    .switchOut(switches[15:0]),
    .btnLOut(buttonLeft),
    .btnUOut(buttonUp),
    .btnCOut(buttonCenter),
    .btnDOut(buttonDown),
    .btnROut(buttonRight),
    .segsOut(seg[6:0]),
    .anOut(an[3:0]),
    .dpOut(dp)
  );
  
  wire [15:0] wDataMemToIntr;
  wire [15:0] wDataIntrToMem;
  wire [15:0] wAddrIntrToMem;
  wire [15:0] wDataIntrToSegs;
  wire wMemRdEn;
  wire wMemWrEn;
  MemoryInterface memInt(
    .cpuClock(clk),
    .periphSelect(1'b1),
    .dIn(regData[15:0]),
    .regSelect(regNum[3:0]),
    .readEn(intrRdEn),
    .writeEn(intrWrEn),
    .reset(1'b0),
    .exec(buttonCenter),
    .dataFromMem(wDataMemToIntr[15:0]),
    .debugRegSelect(),
    .memStatus(wBusy),
    .dOut(wDataIntrToSegs[15:0]),
    .dataToMem(wDataIntrToMem[15:0]),
    .addrToMem(wAddrIntrToMem[15:0]),
    .memReadEn(wMemRdEn),
    .memWriteEn(wMemWrEn),
    .debugOut()
  );
  
  SyzMem bram(
    .memClk(clk),
    .addr(wAddrIntrToMem[15:0]),
    .dIn(wDataIntrToMem[15:0]),
    .en(1'b1),
    .readEn(wMemRdEn),
    .writeEn(wMemWrEn),
    .dOut(wDataMemToIntr[15:0]),
    .busy(wBusy)
  );
  
  always @ (posedge clk) begin
    if(buttonUp == 1'b1) begin
      regNum[3:0] = switches[3:0];
    end
    
    if(buttonDown == 1'b1) begin
      regData[15:0] = switches[15:0];
    end
    
    if(buttonLeft == 1'b1) begin
      intrRdEn = 1'b1;
      regData[15:0] = wDataIntrToSegs[15:0];
    end else begin
      intrRdEn = 1'b0;
    end
    
    if(buttonRight == 1'b1) begin
      intrWrEn = 1'b1;
    end else begin
      intrWrEn = 1'b0;
    end
  end
  
  assign led[15:0] = switches[15:0];
  
endmodule