data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro/convclk_grayffrd.v
data/verilator_xmls/91050d54-5691-42ab-8b22-0715e2d68135.xml
module convclk_grayffrd
    (
     rdclk,
     rdrst_,

     fiford,
     fifoflush,
     fifonemp,
     rdfifolen,
     rdpnt_gray,
     
     rdaddr,
     read,


     wrpnt_gray
     );



parameter   ADDRB = 4;



input               rdclk;
input               rdrst_;

input               fiford;
input               fifoflush;
output              fifonemp;
output [ADDRB:0]    rdfifolen;
output [ADDRB:0]    rdpnt_gray;

output [ADDRB-1:0]  rdaddr;
output              read;

input [ADDRB:0]     wrpnt_gray;







reg [ADDRB:0]       wrpnt_gray1,wrpnt_gray2;
always @ ( posedge rdclk or negedge rdrst_ )
    if(~rdrst_)
        begin
        wrpnt_gray1  <= {(ADDRB+1){1'b0}};
        wrpnt_gray2  <= {(ADDRB+1){1'b0}};
        end
    else
        begin
        wrpnt_gray1  <= wrpnt_gray;
        wrpnt_gray2  <= wrpnt_gray1;      
        end

reg [ADDRB:0] wrpnt_bin;
integer       i;
always @ (wrpnt_gray2)
    begin
    for (i=0;i<(ADDRB+1);i=i+1)
    wrpnt_bin[i] = ^(wrpnt_gray2[ADDRB:0]>>i);
    end


reg     [ADDRB:0]   rdpnt_bin;

wire                fifonemp;
assign              fifonemp    = ~ (wrpnt_bin[ADDRB:0] == rdpnt_bin[ADDRB:0]);

wire                read;
assign              read        = fiford & fifonemp;

wire [ADDRB-1:0]    rdaddr;
assign              rdaddr      = rdpnt_bin[ADDRB-1:0];

wire [ADDRB:0]      rdfifolen;
assign              rdfifolen   = wrpnt_bin[ADDRB:0] - rdpnt_bin[ADDRB:0];

always @ ( posedge rdclk or negedge rdrst_ )
    if(~rdrst_)
        begin
        rdpnt_bin   <= {(ADDRB+1){1'b0}};
        end
    else
        begin
        if (fifoflush) rdpnt_bin <= {(ADDRB+1){1'b0}};
        else if (read) rdpnt_bin <= rdpnt_bin + 1'b1;      
        end

reg [ADDRB:0]       rdpnt_gray;
always @ ( posedge rdclk or negedge rdrst_ )
    if(~rdrst_)
        begin
        rdpnt_gray   <= {(ADDRB+1){1'b0}};
        end
    else
        begin
        rdpnt_gray  <= rdpnt_bin ^ {1'b0,rdpnt_bin[ADDRB:1]};
        end

endmodule
module convclk_grayffrd
    (
     rdclk,
     rdrst_,

     fiford,
     fifoflush,
     fifonemp,
     rdfifolen,
     rdpnt_gray,
     
     rdaddr,
     read,


     wrpnt_gray
     );




parameter   ADDRB = 4;



input               rdclk;
input               rdrst_;

input               fiford;
input               fifoflush;
output              fifonemp;
output [ADDRB:0]    rdfifolen;
output [ADDRB:0]    rdpnt_gray;

output [ADDRB-1:0]  rdaddr;
output              read;

input [ADDRB:0]     wrpnt_gray;







reg [ADDRB:0]       wrpnt_gray1,wrpnt_gray2;
always @ ( posedge rdclk or negedge rdrst_ )
    if(~rdrst_)
        begin
        wrpnt_gray1  <= {(ADDRB+1){1'b0}};
        wrpnt_gray2  <= {(ADDRB+1){1'b0}};
        end
    else
        begin
        wrpnt_gray1  <= wrpnt_gray;
        wrpnt_gray2  <= wrpnt_gray1;      
        end

reg [ADDRB:0] wrpnt_bin;
integer       i;
always @ (wrpnt_gray2)
    begin
    for (i=0;i<(ADDRB+1);i=i+1)
    wrpnt_bin[i] = ^(wrpnt_gray2[ADDRB:0]>>i);
    end


reg     [ADDRB:0]   rdpnt_bin;

wire                fifonemp;
assign              fifonemp    = ~ (wrpnt_bin[ADDRB:0] == rdpnt_bin[ADDRB:0]);

wire                read;
assign              read        = fiford & fifonemp;

wire [ADDRB-1:0]    rdaddr;
assign              rdaddr      = rdpnt_bin[ADDRB-1:0];

wire [ADDRB:0]      rdfifolen;
assign              rdfifolen   = wrpnt_bin[ADDRB:0] - rdpnt_bin[ADDRB:0];

always @ ( posedge rdclk or negedge rdrst_ )
    if(~rdrst_)
        begin
        rdpnt_bin   <= {(ADDRB+1){1'b0}};
        end
    else
        begin
        if (fifoflush) rdpnt_bin <= {(ADDRB+1){1'b0}};
        else if (read) rdpnt_bin <= rdpnt_bin + 1'b1;      
        end

reg [ADDRB:0]       rdpnt_gray;
always @ ( posedge rdclk or negedge rdrst_ )
    if(~rdrst_)
        begin
        rdpnt_gray   <= {(ADDRB+1){1'b0}};
        end
    else
        begin
        rdpnt_gray  <= rdpnt_bin ^ {1'b0,rdpnt_bin[ADDRB:1]};
        end

endmodule