data/full_repos/permissive/432564927/Lab3 (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new/CPU.v
1: b'%Error: Cannot find file containing module: (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927\n        ... Looked in:\n             data/full_repos/permissive/432564927/Lab3/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927\n             data/full_repos/permissive/432564927/Lab3/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             data/full_repos/permissive/432564927/Lab3/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927\n             (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             obj_dir/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927\n             obj_dir/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             obj_dir/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/432564927/Lab3\n%Error: Cannot find file containing module: (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new/CPU.v\n%Error: Exiting due to 3 error(s)\n'
module IDEXE(
    input clk, wreg, m2reg, wmem, aluimm,
    input [3:0] aluc,
    input [31:0] qa, qb,
    input [4:0] mux,
    input [31:0] extend,
    
    output reg ewreg, em2reg, ewmem, ealuimm,
    output reg [3:0] ealuc,
    output reg [31:0] eqa, eqb,
    output reg [4:0] emux,
    output reg [31:0] eextend
    );
    always@(posedge clk) begin
        ewreg = wreg;
        em2reg = m2reg;
        ewmem = wmem;
        ealuimm = aluimm;
        emux = mux;
        ealuc = aluc;
        eqa = qa;
        eqb = qb;
        eextend = extend;
    end
endmodule
module IDEXE(
    input clk, wreg, m2reg, wmem, aluimm,
    input [3:0] aluc,
    input [31:0] qa, qb,
    input [4:0] mux,
    input [31:0] extend,
    
    output reg ewreg, em2reg, ewmem, ealuimm,
    output reg [3:0] ealuc,
    output reg [31:0] eqa, eqb,
    output reg [4:0] emux,
    output reg [31:0] eextend
    );

    always@(posedge clk) begin
        ewreg = wreg;
        em2reg = m2reg;
        ewmem = wmem;
        ealuimm = aluimm;
        emux = mux;
        ealuc = aluc;
        eqa = qa;
        eqb = qb;
        eextend = extend;
    end
endmodule