data/full_repos/permissive/427221126/src/ConvLayer.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/427221126/src/ConvLayer.v:459: Multiple top level modules\n                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                           : ... Top module \'ConvLayer\'\nmodule ConvLayer\n       ^~~~~~~~~\n                                                                           : ... Top module \'ConvCore_nC\'\nmodule ConvCore_nC\n       ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/ConvLayer.v:129: Operator ASSIGNDLY expects 41 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 32 bits.\n                                                                        : ... In instance ConvCore_nC.vecdots[19].U_vd9.U_core\n      psum[0] <= mul[0];\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/ConvLayer.v:140: Operator ADD expects 41 bits on the LHS, but LHS\'s ARRAYSEL generates 32 bits.\n                                                                        : ... In instance ConvCore_nC.vecdots[19].U_vd9.U_core\n          psum[ii] <= mul[ii] + psum[ii-1];\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/ConvLayer.v:423: Operator ASSIGNDLY expects 48 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 32 bits.\n                                                                        : ... In instance ConvCore_nC.U_casadd\n            psum[g] <= din_mult_scale[g] ;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/ConvLayer.v:425: Operator ADD expects 48 bits on the LHS, but LHS\'s ARRAYSEL generates 32 bits.\n                                                                        : ... In instance ConvCore_nC.U_casadd\n            psum[g] <= din_mult_scale[g]  + psum[g-1];\n                                          ^\n%Error: data/full_repos/permissive/427221126/src/ConvLayer.v:243: Cannot find file containing module: \'ShiftRegSIPOnB\'\n  ShiftRegSIPOnB #(\n  ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/ShiftRegSIPOnB\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/ShiftRegSIPOnB.v\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/ShiftRegSIPOnB.sv\n             ShiftRegSIPOnB\n             ShiftRegSIPOnB.v\n             ShiftRegSIPOnB.sv\n             obj_dir/ShiftRegSIPOnB\n             obj_dir/ShiftRegSIPOnB.v\n             obj_dir/ShiftRegSIPOnB.sv\n%Error: data/full_repos/permissive/427221126/src/ConvLayer.v:255: Cannot find file containing module: \'ShiftRegSIPOnB\'\n  ShiftRegSIPOnB #(\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/427221126/src/ConvLayer.v:290: Cannot find file containing module: \'FRound\'\n  FRound #(\n  ^~~~~~\n%Error: data/full_repos/permissive/427221126/src/ConvLayer.v:623: Cannot find file containing module: \'FRound\'\n  FRound #(\n  ^~~~~~\n%Error: data/full_repos/permissive/427221126/src/ConvLayer.v:639: Cannot find file containing module: \'FIFOsync\'\n  FIFOsync #(.INWIDTH(INWIDTH), .DEPTH(4)) U_fifo_cas (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/427221126/src/ConvLayer.v:651: Cannot find file containing module: \'FIFOpi\'\n  FIFOpi #(.INWIDTH(INWIDTH), .INDEPTH(NUM_CHANNELS)) U_fifopi (\n  ^~~~~~\n%Error: Exiting due to 6 error(s), 5 warning(s)\n'
module ConvLayer
  (

  );
endmodule
module ConvLayer
  (

  );

endmodule