data/full_repos/permissive/499944578/rtl/test/utils/delaySignal_Test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/utils/delaySignal_Test.v:15: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD/2);\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/utils/delaySignal_Test.v:17: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD/2);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/utils/delaySignal_Test.v:23: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD/2);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/utils/delaySignal_Test.v:25: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD/2);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/utils/delaySignal_Test.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #TIMEOUT;\n        ^\n%Error: data/full_repos/permissive/499944578/rtl/test/utils/delaySignal_Test.v:43: Unsupported or unknown PLI call: $dumpfile\n            $dumpfile("delaySignal_Test.vcd");\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/test/utils/delaySignal_Test.v:44: Unsupported or unknown PLI call: $dumpvars\n            $dumpvars(0,delaySignal_Test);\n            ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/utils/delaySignal_Test.v:45: Unsupported: Ignoring delay on this delayed statement.\n            #1;\n            ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module delaySignal_Test();
    localparam OneFP = 32'h3f800000;
    localparam ZeroFP = 32'h00000000;
    localparam HalfFP = 32'h3f000000;
    localparam QuarterFP = 32'h3e800000;
    localparam PERIOD = 20;
    localparam TIMEOUT = PERIOD*1000;
    reg in, clk,resetn;
    wire out;
    delaySignal#(4,1) DUT (clk,resetn,in,out);
    
    initial
        begin
            resetn = 1'b1;
            #(PERIOD/2);
            resetn = 1'b0; 
            #(PERIOD/2);
            resetn = 1'b1;
        end
    always 
        begin
            clk = 1'b1; 
            #(PERIOD/2);
            clk = 1'b0;
            #(PERIOD/2);
        end
    
    initial
        begin

            in = 1;
            
        
    end

    initial begin
        #TIMEOUT;
        $display("Simulation Timed Out :(");
        $finish;
    end
    initial
        begin
            $dumpfile("delaySignal_Test.vcd");
            $dumpvars(0,delaySignal_Test);
            #1;
        end
endmodule
module delaySignal_Test();

    localparam OneFP = 32'h3f800000;
    localparam ZeroFP = 32'h00000000;
    localparam HalfFP = 32'h3f000000;
    localparam QuarterFP = 32'h3e800000;
    localparam PERIOD = 20;
    localparam TIMEOUT = PERIOD*1000;
    reg in, clk,resetn;
    wire out;
    delaySignal#(4,1) DUT (clk,resetn,in,out);
    
    initial
        begin
            resetn = 1'b1;
            #(PERIOD/2);
            resetn = 1'b0; 
            #(PERIOD/2);
            resetn = 1'b1;
        end
    always 
        begin
            clk = 1'b1; 
            #(PERIOD/2);
            clk = 1'b0;
            #(PERIOD/2);
        end
    
    initial
        begin

            in = 1;
            
        
    end

    initial begin
        #TIMEOUT;
        $display("Simulation Timed Out :(");
        $finish;
    end
    initial
        begin
            $dumpfile("delaySignal_Test.vcd");
            $dumpvars(0,delaySignal_Test);
            #1;
        end
endmodule