data/full_repos/permissive/504677412/src/data_up_conv.v
1: b'%Warning-WIDTH: data/full_repos/permissive/504677412/src/data_up_conv.v:32: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                          : ... In instance data_up_conv\n        data_cntr <= 1\'b0;\n                  ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module data_up_conv (
  clk,
  rst,

  vld_i,
  data_i,

  vld_o,
  data_o
);


  

  input  wire                       rst;
  input  wire                       clk;
  input  wire                       vld_i;
  input  wire [7:0]                 data_i;
  output wire                       vld_o;
  output wire [31:0]                data_o;
  
  reg  [31:0]                       data_shreg;
  reg  [1:0]                        data_cntr;
  wire                              cnt_done;
  
  
  always @(posedge clk) begin
    if (rst) begin
      data_cntr <= 2'b0;
    end else if (vld_i) begin
      if (cnt_done) begin
        data_cntr <= 1'b0;
      end else begin
        data_cntr <= data_cntr + 2'b1;
      end
    end
  end  

  assign cnt_done = data_cntr == 2'b11 ? 1'b1 : 1'b0;
  
  assign vld_o = vld_i & cnt_done;
  
  always @(posedge clk) begin
    if (rst) begin
      data_shreg <= 32'h0;
    end else if (vld_i) begin
      data_shreg[data_cntr*8+:8] <= data_i;
    end
  end 
  
  assign data_o = {data_shreg[23:0], data_i};
  
endmodule
module data_up_conv (
  clk,
  rst,

  vld_i,
  data_i,

  vld_o,
  data_o
);



  

  input  wire                       rst;
  input  wire                       clk;
  input  wire                       vld_i;
  input  wire [7:0]                 data_i;
  output wire                       vld_o;
  output wire [31:0]                data_o;
  
  reg  [31:0]                       data_shreg;
  reg  [1:0]                        data_cntr;
  wire                              cnt_done;
  
  
  always @(posedge clk) begin
    if (rst) begin
      data_cntr <= 2'b0;
    end else if (vld_i) begin
      if (cnt_done) begin
        data_cntr <= 1'b0;
      end else begin
        data_cntr <= data_cntr + 2'b1;
      end
    end
  end  

  assign cnt_done = data_cntr == 2'b11 ? 1'b1 : 1'b0;
  
  assign vld_o = vld_i & cnt_done;
  
  always @(posedge clk) begin
    if (rst) begin
      data_shreg <= 32'h0;
    end else if (vld_i) begin
      data_shreg[data_cntr*8+:8] <= data_i;
    end
  end 
  
  assign data_o = {data_shreg[23:0], data_i};
  
endmodule