data/full_repos/permissive/456528918/RTL/YD_core.v
1: b"%Error: data/full_repos/permissive/456528918/RTL/YD_core.v:394: Cannot find file containing module: 'YD_reg'\nYD_reg u_YD_reg \n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/456528918/RTL,data/full_repos/permissive/456528918/YD_reg\n             data/full_repos/permissive/456528918/RTL,data/full_repos/permissive/456528918/YD_reg.v\n             data/full_repos/permissive/456528918/RTL,data/full_repos/permissive/456528918/YD_reg.sv\n             YD_reg\n             YD_reg.v\n             YD_reg.sv\n             obj_dir/YD_reg\n             obj_dir/YD_reg.v\n             obj_dir/YD_reg.sv\n%Error: data/full_repos/permissive/456528918/RTL/YD_core.v:416: Cannot find file containing module: 'YD_int'\nYD_int u_YD_int \n^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module YD_core
(
	input		wire	clk,
	input		wire	rst,

	output 	wire[15:0]	i_addr,
	input 	wire[15:0]	i_dout,

	output	reg[15:0]	d_din,
	output 	reg[15:0]	d_addr,
	output	reg 		d_we,
	input 	wire[15:0]	d_dout,

	input 	wire int_vld,
	output 	wire int_rdy
);

reg rst_r;
reg jpc,jpc_r;
reg dwi;
reg dsv_0;
reg dsv_1;
reg dsw;
reg dsw_r;
reg [15:0]idata;
reg [15:0]idata_r;
reg [15:0]din0;
reg [3:0]waddr0;
reg we0;
reg [15:0]din1;
reg [3:0]waddr1;
reg we1;
reg [3:0]raddr0;
reg [3:0]raddr1;
reg [15:0]d_addr_d0;
reg [15:0]d_addr_d1;
reg [15:0]d_addr_z0;
reg [15:0]d_addr_z1;
reg [15:0]d_din_z0;
reg [15:0]d_din_z1;
reg d_we_z0;
reg d_we_z1;


wire [15:0]dout0;
wire [15:0]dout1;
wire [15:0]DKD;
wire inp;
wire [15:0]int_din0;
wire [3:0]int_waddr0;
wire int_we0;
wire [15:0]int_din1;
wire [3:0]int_waddr1;
wire int_we1;




localparam NF=4'b0000;
localparam LD=4'b0001;
localparam SV=4'b0010;
localparam IN=4'b0011;
localparam SW=4'b0100;
localparam WR=4'b0101;
localparam CR=4'b0110;
localparam LA=4'b0111;
localparam LO=4'b1000;
localparam AD=4'b1001;
localparam SB=4'b1010;
localparam JW=4'b1011;
localparam JA=4'b1100;
localparam LL=4'b1101;
localparam LR=4'b1110;
localparam TL=4'b1111;


localparam ZEA=4'b0000;
localparam DKA=4'b0001;
localparam R0A=4'b0010;

localparam PCA=4'b1111;


always @(*) begin
	if(jpc|jpc_r|dwi|inp)
		idata=16'h0;
	else
		idata=i_dout;
end


always @(posedge clk) begin
	if(rst_r)
		idata_r <= 16'h0;
	else
		idata_r <= idata;
end

always @(posedge clk) rst_r <= rst;


always @(*) begin
	raddr0=4'h0;
	d_addr_d0=16'h0;
	dsv_0=1'b0;
	dsv_1=1'b0;
	raddr1=4'h0;
	d_addr_d1=16'h0;
	case (idata[15:12])
		NF:begin
			dsw=1'b1;
			raddr0=idata[11:8];
			end
		LD:begin
			dsw=1'b1;
			d_addr_d0=DKD;
			end
		SV:begin
			dsw=1'b1;
			raddr0=idata[11:8];
			dsv_0=1'b1;
			end
		IN:begin
			dsw=1'b1;
			raddr0=idata[11:8];
			end
		SW:begin
			dsw=1'b1;
			raddr0=idata[11:8];
			end
		WR:begin
			dsw=1'b0;
			raddr0=idata[11:8];
			raddr1=idata[7:4];
			end
		CR:begin
			dsw=1'b0;
			raddr0=idata[11:8];
			raddr1=idata[7:4];
			end
		LA:begin
			dsw=1'b0;
			raddr0=idata[11:8];
			raddr1=idata[7:4];
			end
		LO:begin
			dsw=1'b0;
			raddr0=idata[11:8];
			raddr1=idata[7:4];
			end
		AD:begin
			dsw=1'b0;
			raddr0=idata[11:8];
			raddr1=DKA;
			end
		SB:begin
			dsw=1'b0;
			raddr0=idata[11:8];
			raddr1=DKA;
			end
		JW:begin
			dsw=1'b0;
			raddr0=idata[11:8];
			raddr1=DKA;
			end
		JA:begin
			dsw=1'b0;
			raddr0=idata[11:8];
			end
		LL:begin
			dsw=1'b0;
			raddr0=idata[11:8];
			raddr1=DKA;
			end
		LR:begin
			dsw=1'b0;
			raddr0=idata[11:8];
			raddr1=DKA;
			end
		TL:begin
			dsw=1'b0;
			raddr0=idata[11:8];
			raddr1=DKA;
			end
	endcase

	if(dsw) begin
		case (idata[7:4])
			NF:raddr1=idata[3:0];
			LD:d_addr_d1=DKD;
			SV: begin raddr1=idata[3:0]; dsv_1=1'b1; end
			IN:raddr1=idata[3:0];
			SW:raddr1=idata[3:0];
		endcase
		end
end


always @(*) begin
	d_din_z0=16'h0;
	d_addr_z0=16'h0;
	d_we_z0=1'b0;
	d_din_z1=16'h0;
	d_addr_z1=16'h0;
	d_we_z1=1'b0;
	din0=16'h0;
	waddr0=4'h0;
	we0=1'b0;
	din1=16'h0;
	waddr1=4'h0;
	we1=1'b0;
	case (idata_r[15:12])
		NF:begin
			dsw_r=1'b1;
			din0=~dout0;
			waddr0=idata_r[11:8];
			we0=1'b1;
			end
		LD:begin
			dsw_r=1'b1;
			din0=d_dout;
			waddr0=idata_r[11:8];
			we0=1'b1;
			end
		SV:begin
			dsw_r=1'b1;
			d_din_z0=dout0;
			d_addr_z0=DKD;
			d_we_z0=1'b1;
			end
		IN:begin
			dsw_r=1'b1;
			din0=dout0+1;
			waddr0=idata_r[11:8];
			we0=1'b1;
			end
		SW:begin
			dsw_r=1'b1;
			din0={dout0[7:0],dout0[15:8]};
			waddr0=idata_r[11:8];
			we0=1'b1;
			end
		WR:begin
			dsw_r=1'b0;
			din0=dout0;
			waddr0=idata_r[7:4];
			we0=1'b1;
			end
		CR:begin
			dsw_r=1'b0;
			din0=dout0>dout1?16'h1:16'h0;
			waddr0=DKA;
			we0=1'b1;
			end
		LA:begin
			dsw_r=1'b0;
			din0=dout0&dout1;
			waddr0=DKA;
			we0=1'b1;
			end
		LO:begin
			dsw_r=1'b0;
			din0=dout0|dout1;
			waddr0=DKA;
			we0=1'b1;
			end
		AD:begin
			dsw_r=1'b0;
			din0=dout1+dout0+{8'h0,idata_r[7:0]};
			waddr0=DKA;
			we0=1'b1;
			end
		SB:begin
			dsw_r=1'b0;
			din0=dout1-dout0-{8'h0,idata_r[7:0]};
			waddr0=DKA;
			we0=1'b1;
			end
		JW:begin
			dsw_r=1'b0;
			din0=(dout1!=16'h0)?dout0+{8'h0,idata_r[7:0]}:16'h0;
			waddr0=(dout1!=16'h0)?PCA:4'h0;
			we0=(dout1!=16'h0)?1'b1:1'b0;
			end
		JA:begin
			dsw_r=1'b0;
			din0=dout0+{8'h0,idata_r[7:0]};
			waddr0=PCA;
			we0=1'b1;
			end
		LL:begin
			dsw_r=1'b0;
			din0=dout1<<(dout0[3:0]+idata_r[3:0]);
			waddr0=DKA;
			we0=1'b1;
			end
		LR:begin
			dsw_r=1'b0;
			din0=dout1>>(dout0[3:0]+idata_r[3:0]);
			waddr0=DKA;
			we0=1'b1;
			end
		TL:begin
			dsw_r=1'b0;
			if(idata_r[0])
				if(idata_r[1]==1'b0)
					din0={dout1[14:0],dout1[15]};
				else
					din0={dout1[0],dout1[15:1]};
			else
				if(dout0==16'h0)
					din0={dout1[14:0],dout1[15]};
				else
					din0={dout1[0],dout1[15:1]};
			waddr0=DKA;
			we0=1'b1;
			end
	endcase

	if(dsw_r) begin
		case (idata[7:4])
			NF:begin
				din1=~dout1;
				waddr1=idata_r[3:0];
				we1=1'b1;
				end
			LD:begin
				din1=d_dout;
				waddr1=idata_r[3:0];
				we0=1'b1;
				end
			SV:begin
				d_din_z1=dout1;
				d_addr_z1=DKD;
				d_we_z1=1'b1;
				end
			IN:begin
				din1=dout1+1;
				waddr1=idata_r[3:0];
				we1=1'b1;
				end
			SW:begin
				din1={dout1[7:0],dout1[15:8]};
				waddr1=idata_r[3:0];
				we1=1'b1;
				end
		endcase
	end
end


always @(posedge clk) begin
	if(rst_r) begin
		dwi <= 1'b0;
		jpc <= 1'b0;
		jpc_r <= 1'b0;
		end 
	else begin
		jpc_r <= jpc;
		if(idata[15:12]==JA || idata[15:12]==JW)
			jpc <= 1'b1;
		else
			jpc <= 1'b0;
		if((idata[15:12]==SV || idata[7:4]==SV) && dsw)
			dwi <= 1'b1;
		else
			dwi <= 1'b0;
		end
end


always @(*) begin
	if(rst) begin
		d_din = 16'h0;
		d_addr = 16'h0;
		d_we = 1'b0;
		end
	else begin
		if(dwi) begin
			d_addr = d_addr_z1 | d_addr_z0;
			d_din = d_din_z1 | d_din_z0;
			d_we = d_we_z1 | d_we_z0;
			end
		else begin
			d_din = 16'h0;
			d_addr = d_addr_d0 | d_addr_d1;
			d_we =1'b0;
			end
		end
end

wire [15:0]PC;
assign i_addr=PC;
YD_reg u_YD_reg
(
	.clk    (clk),
	.rst    (rst),
	.jpc    (int_jpc),
	.dsv	(dsv_0 | dsv_1),
	.din0   (int_din0),
	.waddr0 (int_waddr0),
	.we0    (int_we0),
	.din1   (int_din1),
	.waddr1 (int_waddr1),
	.we1    (int_we1),
	.raddr0 (raddr0),
	.dout0  (dout0),
	.raddr1 (raddr1),
	.dout1  (dout1),
	.PC     (PC),
	.DKD	(DKD)
);



YD_int u_YD_int
(
	.clk        (clk),
	.rst        (rst),
	.int_vld    (int_vld),
	.int_rdy    (int_rdy),
	.PC         (PC),
	.jpc        (jpc),
	.int_jpc    (int_jpc),
	.inp        (inp),
	.din0       (din0),
	.waddr0     (waddr0),
	.we0        (we0),
	.din1       (din1),
	.waddr1     (waddr1),
	.we1        (we1),
	.int_din0   (int_din0),
	.int_waddr0 (int_waddr0),
	.int_we0    (int_we0),
	.int_din1   (int_din1),
	.int_waddr1 (int_waddr1),
	.int_we1    (int_we1)
);

endmodule
module YD_core
(
	input		wire	clk,
	input		wire	rst,

	output 	wire[15:0]	i_addr,
	input 	wire[15:0]	i_dout,

	output	reg[15:0]	d_din,
	output 	reg[15:0]	d_addr,
	output	reg 		d_we,
	input 	wire[15:0]	d_dout,

	input 	wire int_vld,
	output 	wire int_rdy
);


reg rst_r;
reg jpc,jpc_r;
reg dwi;
reg dsv_0;
reg dsv_1;
reg dsw;
reg dsw_r;
reg [15:0]idata;
reg [15:0]idata_r;
reg [15:0]din0;
reg [3:0]waddr0;
reg we0;
reg [15:0]din1;
reg [3:0]waddr1;
reg we1;
reg [3:0]raddr0;
reg [3:0]raddr1;
reg [15:0]d_addr_d0;
reg [15:0]d_addr_d1;
reg [15:0]d_addr_z0;
reg [15:0]d_addr_z1;
reg [15:0]d_din_z0;
reg [15:0]d_din_z1;
reg d_we_z0;
reg d_we_z1;


wire [15:0]dout0;
wire [15:0]dout1;
wire [15:0]DKD;
wire inp;
wire [15:0]int_din0;
wire [3:0]int_waddr0;
wire int_we0;
wire [15:0]int_din1;
wire [3:0]int_waddr1;
wire int_we1;




localparam NF=4'b0000;
localparam LD=4'b0001;
localparam SV=4'b0010;
localparam IN=4'b0011;
localparam SW=4'b0100;
localparam WR=4'b0101;
localparam CR=4'b0110;
localparam LA=4'b0111;
localparam LO=4'b1000;
localparam AD=4'b1001;
localparam SB=4'b1010;
localparam JW=4'b1011;
localparam JA=4'b1100;
localparam LL=4'b1101;
localparam LR=4'b1110;
localparam TL=4'b1111;


localparam ZEA=4'b0000;
localparam DKA=4'b0001;
localparam R0A=4'b0010;

localparam PCA=4'b1111;


always @(*) begin
	if(jpc|jpc_r|dwi|inp)
		idata=16'h0;
	else
		idata=i_dout;
end


always @(posedge clk) begin
	if(rst_r)
		idata_r <= 16'h0;
	else
		idata_r <= idata;
end

always @(posedge clk) rst_r <= rst;


always @(*) begin
	raddr0=4'h0;
	d_addr_d0=16'h0;
	dsv_0=1'b0;
	dsv_1=1'b0;
	raddr1=4'h0;
	d_addr_d1=16'h0;
	case (idata[15:12])
		NF:begin
			dsw=1'b1;
			raddr0=idata[11:8];
			end
		LD:begin
			dsw=1'b1;
			d_addr_d0=DKD;
			end
		SV:begin
			dsw=1'b1;
			raddr0=idata[11:8];
			dsv_0=1'b1;
			end
		IN:begin
			dsw=1'b1;
			raddr0=idata[11:8];
			end
		SW:begin
			dsw=1'b1;
			raddr0=idata[11:8];
			end
		WR:begin
			dsw=1'b0;
			raddr0=idata[11:8];
			raddr1=idata[7:4];
			end
		CR:begin
			dsw=1'b0;
			raddr0=idata[11:8];
			raddr1=idata[7:4];
			end
		LA:begin
			dsw=1'b0;
			raddr0=idata[11:8];
			raddr1=idata[7:4];
			end
		LO:begin
			dsw=1'b0;
			raddr0=idata[11:8];
			raddr1=idata[7:4];
			end
		AD:begin
			dsw=1'b0;
			raddr0=idata[11:8];
			raddr1=DKA;
			end
		SB:begin
			dsw=1'b0;
			raddr0=idata[11:8];
			raddr1=DKA;
			end
		JW:begin
			dsw=1'b0;
			raddr0=idata[11:8];
			raddr1=DKA;
			end
		JA:begin
			dsw=1'b0;
			raddr0=idata[11:8];
			end
		LL:begin
			dsw=1'b0;
			raddr0=idata[11:8];
			raddr1=DKA;
			end
		LR:begin
			dsw=1'b0;
			raddr0=idata[11:8];
			raddr1=DKA;
			end
		TL:begin
			dsw=1'b0;
			raddr0=idata[11:8];
			raddr1=DKA;
			end
	endcase

	if(dsw) begin
		case (idata[7:4])
			NF:raddr1=idata[3:0];
			LD:d_addr_d1=DKD;
			SV: begin raddr1=idata[3:0]; dsv_1=1'b1; end
			IN:raddr1=idata[3:0];
			SW:raddr1=idata[3:0];
		endcase
		end
end


always @(*) begin
	d_din_z0=16'h0;
	d_addr_z0=16'h0;
	d_we_z0=1'b0;
	d_din_z1=16'h0;
	d_addr_z1=16'h0;
	d_we_z1=1'b0;
	din0=16'h0;
	waddr0=4'h0;
	we0=1'b0;
	din1=16'h0;
	waddr1=4'h0;
	we1=1'b0;
	case (idata_r[15:12])
		NF:begin
			dsw_r=1'b1;
			din0=~dout0;
			waddr0=idata_r[11:8];
			we0=1'b1;
			end
		LD:begin
			dsw_r=1'b1;
			din0=d_dout;
			waddr0=idata_r[11:8];
			we0=1'b1;
			end
		SV:begin
			dsw_r=1'b1;
			d_din_z0=dout0;
			d_addr_z0=DKD;
			d_we_z0=1'b1;
			end
		IN:begin
			dsw_r=1'b1;
			din0=dout0+1;
			waddr0=idata_r[11:8];
			we0=1'b1;
			end
		SW:begin
			dsw_r=1'b1;
			din0={dout0[7:0],dout0[15:8]};
			waddr0=idata_r[11:8];
			we0=1'b1;
			end
		WR:begin
			dsw_r=1'b0;
			din0=dout0;
			waddr0=idata_r[7:4];
			we0=1'b1;
			end
		CR:begin
			dsw_r=1'b0;
			din0=dout0>dout1?16'h1:16'h0;
			waddr0=DKA;
			we0=1'b1;
			end
		LA:begin
			dsw_r=1'b0;
			din0=dout0&dout1;
			waddr0=DKA;
			we0=1'b1;
			end
		LO:begin
			dsw_r=1'b0;
			din0=dout0|dout1;
			waddr0=DKA;
			we0=1'b1;
			end
		AD:begin
			dsw_r=1'b0;
			din0=dout1+dout0+{8'h0,idata_r[7:0]};
			waddr0=DKA;
			we0=1'b1;
			end
		SB:begin
			dsw_r=1'b0;
			din0=dout1-dout0-{8'h0,idata_r[7:0]};
			waddr0=DKA;
			we0=1'b1;
			end
		JW:begin
			dsw_r=1'b0;
			din0=(dout1!=16'h0)?dout0+{8'h0,idata_r[7:0]}:16'h0;
			waddr0=(dout1!=16'h0)?PCA:4'h0;
			we0=(dout1!=16'h0)?1'b1:1'b0;
			end
		JA:begin
			dsw_r=1'b0;
			din0=dout0+{8'h0,idata_r[7:0]};
			waddr0=PCA;
			we0=1'b1;
			end
		LL:begin
			dsw_r=1'b0;
			din0=dout1<<(dout0[3:0]+idata_r[3:0]);
			waddr0=DKA;
			we0=1'b1;
			end
		LR:begin
			dsw_r=1'b0;
			din0=dout1>>(dout0[3:0]+idata_r[3:0]);
			waddr0=DKA;
			we0=1'b1;
			end
		TL:begin
			dsw_r=1'b0;
			if(idata_r[0])
				if(idata_r[1]==1'b0)
					din0={dout1[14:0],dout1[15]};
				else
					din0={dout1[0],dout1[15:1]};
			else
				if(dout0==16'h0)
					din0={dout1[14:0],dout1[15]};
				else
					din0={dout1[0],dout1[15:1]};
			waddr0=DKA;
			we0=1'b1;
			end
	endcase

	if(dsw_r) begin
		case (idata[7:4])
			NF:begin
				din1=~dout1;
				waddr1=idata_r[3:0];
				we1=1'b1;
				end
			LD:begin
				din1=d_dout;
				waddr1=idata_r[3:0];
				we0=1'b1;
				end
			SV:begin
				d_din_z1=dout1;
				d_addr_z1=DKD;
				d_we_z1=1'b1;
				end
			IN:begin
				din1=dout1+1;
				waddr1=idata_r[3:0];
				we1=1'b1;
				end
			SW:begin
				din1={dout1[7:0],dout1[15:8]};
				waddr1=idata_r[3:0];
				we1=1'b1;
				end
		endcase
	end
end


always @(posedge clk) begin
	if(rst_r) begin
		dwi <= 1'b0;
		jpc <= 1'b0;
		jpc_r <= 1'b0;
		end 
	else begin
		jpc_r <= jpc;
		if(idata[15:12]==JA || idata[15:12]==JW)
			jpc <= 1'b1;
		else
			jpc <= 1'b0;
		if((idata[15:12]==SV || idata[7:4]==SV) && dsw)
			dwi <= 1'b1;
		else
			dwi <= 1'b0;
		end
end


always @(*) begin
	if(rst) begin
		d_din = 16'h0;
		d_addr = 16'h0;
		d_we = 1'b0;
		end
	else begin
		if(dwi) begin
			d_addr = d_addr_z1 | d_addr_z0;
			d_din = d_din_z1 | d_din_z0;
			d_we = d_we_z1 | d_we_z0;
			end
		else begin
			d_din = 16'h0;
			d_addr = d_addr_d0 | d_addr_d1;
			d_we =1'b0;
			end
		end
end

wire [15:0]PC;
assign i_addr=PC;
YD_reg u_YD_reg
(
	.clk    (clk),
	.rst    (rst),
	.jpc    (int_jpc),
	.dsv	(dsv_0 | dsv_1),
	.din0   (int_din0),
	.waddr0 (int_waddr0),
	.we0    (int_we0),
	.din1   (int_din1),
	.waddr1 (int_waddr1),
	.we1    (int_we1),
	.raddr0 (raddr0),
	.dout0  (dout0),
	.raddr1 (raddr1),
	.dout1  (dout1),
	.PC     (PC),
	.DKD	(DKD)
);



YD_int u_YD_int
(
	.clk        (clk),
	.rst        (rst),
	.int_vld    (int_vld),
	.int_rdy    (int_rdy),
	.PC         (PC),
	.jpc        (jpc),
	.int_jpc    (int_jpc),
	.inp        (inp),
	.din0       (din0),
	.waddr0     (waddr0),
	.we0        (we0),
	.din1       (din1),
	.waddr1     (waddr1),
	.we1        (we1),
	.int_din0   (int_din0),
	.int_waddr0 (int_waddr0),
	.int_we0    (int_we0),
	.int_din1   (int_din1),
	.int_waddr1 (int_waddr1),
	.int_we1    (int_we1)
);

endmodule