data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/rtu/rtl/aq_rtu_int.v
data/verilator_xmls/fc9b6d5b-5c37-4715-9dbb-23ab7b2b6f99.xml
module aq_rtu_int(
  cp0_rtu_int_vld,
  dp_int_ex2_inst_split,
  dtu_rtu_int_mask,
  int_retire_int_vec,
  int_retire_int_vld
);



input   [14:0]  cp0_rtu_int_vld;      
input           dp_int_ex2_inst_split; 
input           dtu_rtu_int_mask;     
output  [4 :0]  int_retire_int_vec;   
output          int_retire_int_vld;   


reg     [4 :0]  int_vec;              


wire    [14:0]  cp0_rtu_int_vld;      
wire            dp_int_ex2_inst_split; 
wire            dtu_rtu_int_mask;     
wire    [4 :0]  int_retire_int_vec;   
wire            int_retire_int_vld;   
wire            int_vld;              
wire    [14:0]  int_vld_raw;          






assign int_vld_raw[14:0] = cp0_rtu_int_vld[14:0];


always @( int_vld_raw[14:0])
begin
casez(int_vld_raw[14:0])
  15'b1?????????????? : int_vec[4:0] = 5'd16;
  15'b01????????????? : int_vec[4:0] = 5'd18;
  15'b001???????????? : int_vec[4:0] = 5'd11;
  15'b0001??????????? : int_vec[4:0] = 5'd3;
  15'b00001?????????? : int_vec[4:0] = 5'd7;
  15'b000001????????? : int_vec[4:0] = 5'd9;
  15'b0000001???????? : int_vec[4:0] = 5'd1;
  15'b00000001??????? : int_vec[4:0] = 5'd5;
  15'b000000001?????? : int_vec[4:0] = 5'd17;
  15'b0000000001????? : int_vec[4:0] = 5'd16;
  15'b00000000001???? : int_vec[4:0] = 5'd18;
  15'b000000000001??? : int_vec[4:0] = 5'd9;
  15'b0000000000001?? : int_vec[4:0] = 5'd1;
  15'b00000000000001? : int_vec[4:0] = 5'd5;
  15'b000000000000001 : int_vec[4:0] = 5'd17;
  default      : int_vec[4:0] = {5{1'bx}};
endcase

end




assign int_vld = |int_vld_raw[14:0]
                 && !dtu_rtu_int_mask
                 && !dp_int_ex2_inst_split;




assign int_retire_int_vld     = int_vld;
assign int_retire_int_vec[4:0] = int_vec[4:0];


endmodule
module aq_rtu_int(
  cp0_rtu_int_vld,
  dp_int_ex2_inst_split,
  dtu_rtu_int_mask,
  int_retire_int_vec,
  int_retire_int_vld
);




input   [14:0]  cp0_rtu_int_vld;      
input           dp_int_ex2_inst_split; 
input           dtu_rtu_int_mask;     
output  [4 :0]  int_retire_int_vec;   
output          int_retire_int_vld;   


reg     [4 :0]  int_vec;              


wire    [14:0]  cp0_rtu_int_vld;      
wire            dp_int_ex2_inst_split; 
wire            dtu_rtu_int_mask;     
wire    [4 :0]  int_retire_int_vec;   
wire            int_retire_int_vld;   
wire            int_vld;              
wire    [14:0]  int_vld_raw;          






assign int_vld_raw[14:0] = cp0_rtu_int_vld[14:0];


always @( int_vld_raw[14:0])
begin
casez(int_vld_raw[14:0])
  15'b1?????????????? : int_vec[4:0] = 5'd16;
  15'b01????????????? : int_vec[4:0] = 5'd18;
  15'b001???????????? : int_vec[4:0] = 5'd11;
  15'b0001??????????? : int_vec[4:0] = 5'd3;
  15'b00001?????????? : int_vec[4:0] = 5'd7;
  15'b000001????????? : int_vec[4:0] = 5'd9;
  15'b0000001???????? : int_vec[4:0] = 5'd1;
  15'b00000001??????? : int_vec[4:0] = 5'd5;
  15'b000000001?????? : int_vec[4:0] = 5'd17;
  15'b0000000001????? : int_vec[4:0] = 5'd16;
  15'b00000000001???? : int_vec[4:0] = 5'd18;
  15'b000000000001??? : int_vec[4:0] = 5'd9;
  15'b0000000000001?? : int_vec[4:0] = 5'd1;
  15'b00000000000001? : int_vec[4:0] = 5'd5;
  15'b000000000000001 : int_vec[4:0] = 5'd17;
  default      : int_vec[4:0] = {5{1'bx}};
endcase

end




assign int_vld = |int_vld_raw[14:0]
                 && !dtu_rtu_int_mask
                 && !dp_int_ex2_inst_split;




assign int_retire_int_vld     = int_vld;
assign int_retire_int_vec[4:0] = int_vec[4:0];


endmodule