data/full_repos/permissive/515624136/rtl/IMM_GEN.v
data/verilator_xmls/bfeb03d9-ca2a-4d3a-9536-c80a1f5999c9.xml
module IMM_GEN(

input [31:0] IMM_GEN_ins_InBUS,
output [31:0] IMM_GEN_Inmediate_OutBUS

);






parameter I_TYPE_0 = 7'b00?0011;
											
										
parameter JALR_TYPE	= 7'b1100111;
parameter S_TYPE   = 7'b0100011;
parameter B_TYPE   = 7'b1100011;
parameter U_TYPE   = 7'b0?10111;
parameter J_TYPE   = 7'b1101111;



localparam SLTIU = 3'b011;
			 




wire [6:0] Opcode; 
wire [2:0] Funct3; 
reg  [31:0] Tmp_Imm;





always@(*)
begin 
	
	casex(Opcode)
	
		I_TYPE_0: if(Funct3 != SLTIU) begin
						Tmp_Imm = {{21{IMM_GEN_ins_InBUS[31]}},
									 IMM_GEN_ins_InBUS[30:20]};
						end
					 else begin
						Tmp_Imm= {{20{1'b0}},
					   IMM_GEN_ins_InBUS[31:20]};
					 end	 
									
		S_TYPE:	 Tmp_Imm = {{21{IMM_GEN_ins_InBUS[31]}},
									IMM_GEN_ins_InBUS[30:25],
									IMM_GEN_ins_InBUS[11:7]};
	
		B_TYPE: Tmp_Imm = {{20{IMM_GEN_ins_InBUS[31]}},
								 IMM_GEN_ins_InBUS[7],
		                   IMM_GEN_ins_InBUS[30:25],
								 IMM_GEN_ins_InBUS[11:8],
		                   1'b0};
		
		U_TYPE: Tmp_Imm = {IMM_GEN_ins_InBUS[31:12],
								{12{1'b0}}};
								
		J_TYPE: Tmp_Imm = { {12{IMM_GEN_ins_InBUS[31]}},
		                    IMM_GEN_ins_InBUS[19:12],
								  IMM_GEN_ins_InBUS[20],
								  IMM_GEN_ins_InBUS[30:21],
								  1'b0};
								  
								  
		JALR_TYPE: Tmp_Imm = {{21{IMM_GEN_ins_InBUS[31]}},
									 IMM_GEN_ins_InBUS[30:20]};
		
		default: Tmp_Imm= 32'h00000000;
	
	endcase


end 


assign Opcode = IMM_GEN_ins_InBUS[6:0];
assign Funct3 =  IMM_GEN_ins_InBUS[14:12];
assign IMM_GEN_Inmediate_OutBUS= Tmp_Imm; 


endmodule
module IMM_GEN(

input [31:0] IMM_GEN_ins_InBUS,
output [31:0] IMM_GEN_Inmediate_OutBUS

);







parameter I_TYPE_0 = 7'b00?0011;
											
										
parameter JALR_TYPE	= 7'b1100111;
parameter S_TYPE   = 7'b0100011;
parameter B_TYPE   = 7'b1100011;
parameter U_TYPE   = 7'b0?10111;
parameter J_TYPE   = 7'b1101111;



localparam SLTIU = 3'b011;
			 




wire [6:0] Opcode; 
wire [2:0] Funct3; 
reg  [31:0] Tmp_Imm;





always@(*)
begin 
	
	casex(Opcode)
	
		I_TYPE_0: if(Funct3 != SLTIU) begin
						Tmp_Imm = {{21{IMM_GEN_ins_InBUS[31]}},
									 IMM_GEN_ins_InBUS[30:20]};
						end
					 else begin
						Tmp_Imm= {{20{1'b0}},
					   IMM_GEN_ins_InBUS[31:20]};
					 end	 
									
		S_TYPE:	 Tmp_Imm = {{21{IMM_GEN_ins_InBUS[31]}},
									IMM_GEN_ins_InBUS[30:25],
									IMM_GEN_ins_InBUS[11:7]};
	
		B_TYPE: Tmp_Imm = {{20{IMM_GEN_ins_InBUS[31]}},
								 IMM_GEN_ins_InBUS[7],
		                   IMM_GEN_ins_InBUS[30:25],
								 IMM_GEN_ins_InBUS[11:8],
		                   1'b0};
		
		U_TYPE: Tmp_Imm = {IMM_GEN_ins_InBUS[31:12],
								{12{1'b0}}};
								
		J_TYPE: Tmp_Imm = { {12{IMM_GEN_ins_InBUS[31]}},
		                    IMM_GEN_ins_InBUS[19:12],
								  IMM_GEN_ins_InBUS[20],
								  IMM_GEN_ins_InBUS[30:21],
								  1'b0};
								  
								  
		JALR_TYPE: Tmp_Imm = {{21{IMM_GEN_ins_InBUS[31]}},
									 IMM_GEN_ins_InBUS[30:20]};
		
		default: Tmp_Imm= 32'h00000000;
	
	endcase


end 


assign Opcode = IMM_GEN_ins_InBUS[6:0];
assign Funct3 =  IMM_GEN_ins_InBUS[14:12];
assign IMM_GEN_Inmediate_OutBUS= Tmp_Imm; 


endmodule