data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_yosys.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/simlib_yosys.v:34: Multiple top level modules\n                                                                                                                : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                                : ... Top module \'_NOT_\'\nmodule _NOT_(A, Y);\n       ^~~~~\n                                                                                                                : ... Top module \'_AND_\'\nmodule _AND_(A, B, Y);\n       ^~~~~\n                                                                                                                : ... Top module \'_OR_\'\nmodule _OR_(A, B, Y);\n       ^~~~\n                                                                                                                : ... Top module \'_XOR_\'\nmodule _XOR_(A, B, Y);\n       ^~~~~\n                                                                                                                : ... Top module \'_MUX_\'\nmodule _MUX_(A, B, S, Y);\n       ^~~~~\n                                                                                                                : ... Top module \'_DFF_N_\'\nmodule _DFF_N_(D, Q, C);\n       ^~~~~~~\n                                                                                                                : ... Top module \'_DFF_P_\'\nmodule _DFF_P_(D, Q, C);\n       ^~~~~~~\n                                                                                                                : ... Top module \'_DFF_NN0_\'\nmodule _DFF_NN0_(D, Q, C, R);\n       ^~~~~~~~~\n                                                                                                                : ... Top module \'_DFF_NN1_\'\nmodule _DFF_NN1_(D, Q, C, R);\n       ^~~~~~~~~\n                                                                                                                : ... Top module \'_DFF_NP0_\'\nmodule _DFF_NP0_(D, Q, C, R);\n       ^~~~~~~~~\n                                                                                                                : ... Top module \'_DFF_NP1_\'\nmodule _DFF_NP1_(D, Q, C, R);\n       ^~~~~~~~~\n                                                                                                                : ... Top module \'_DFF_PN0_\'\nmodule _DFF_PN0_(D, Q, C, R);\n       ^~~~~~~~~\n                                                                                                                : ... Top module \'_DFF_PN1_\'\nmodule _DFF_PN1_(D, Q, C, R);\n       ^~~~~~~~~\n                                                                                                                : ... Top module \'_DFF_PP0_\'\nmodule _DFF_PP0_(D, Q, C, R);\n       ^~~~~~~~~\n                                                                                                                : ... Top module \'_DFF_PP1_\'\nmodule _DFF_PP1_(D, Q, C, R);\n       ^~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module _DFF_PN0_(D, Q, C, R);
input D, C, R;
output reg Q;
always @(posedge C or negedge R) begin
	if (R == 0)
		Q <= 0;
	else
		Q <= D;
end
endmodule
module _DFF_PN0_(D, Q, C, R);

input D, C, R;
output reg Q;
always @(posedge C or negedge R) begin
	if (R == 0)
		Q <= 0;
	else
		Q <= D;
end
endmodule