data/full_repos/permissive/414822257/ip/third_party/picorv32_wb/gpio32_wb.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/414822257/ip/third_party/picorv32_wb/gpio32_wb.v:46: Cell has missing pin: \'gpio_in_pad\'\n    ) gpio_ctrl (\n      ^~~~~~~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/414822257/ip/third_party/picorv32_wb/gpio32_wb.v:87: Duplicate declaration of signal: \'gpio_out\'\n    reg [31:0] gpio_out;   \n               ^~~~~~~~\n        data/full_repos/permissive/414822257/ip/third_party/picorv32_wb/gpio32_wb.v:83: ... Location of original declaration\n    output [31:0] gpio_out,\n                  ^~~~~~~~\n%Error: data/full_repos/permissive/414822257/ip/third_party/picorv32_wb/gpio32_wb.v:90: Duplicate declaration of signal: \'gpio_oeb\'\n    reg [31:0] gpio_oeb;     \n               ^~~~~~~~\n        data/full_repos/permissive/414822257/ip/third_party/picorv32_wb/gpio32_wb.v:84: ... Location of original declaration\n    output [31:0] gpio_oeb\n                  ^~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module gpio32 #(
    parameter GPIO_DATA = 8'h 00,
    parameter GPIO_ENA  = 8'h 04,
    parameter GPIO_PU   = 8'h 08,
    parameter GPIO_PD   = 8'h 0c
) (
    input clk,
    input resetn,

    input gpio_in_pad,

    input [31:0] iomem_addr,
    input iomem_valid,
    input iomem_wstrb,
    input [31:0] iomem_wdata,
    output reg [31:0] iomem_rdata,
    output reg iomem_ready,

    input [31:0]  gpio_in,
    output [31:0] gpio_out,
    output [31:0] gpio_oeb
);

    reg [31:0] gpio_out;
    reg [31:0] gpio_pu;
    reg [31:0] gpio_pd;
    reg [31:0] gpio_oeb;

    wire gpio_sel;
    wire gpio_oeb_sel;
    wire gpio_pu_sel;
    wire gpio_pd_sel;

    assign gpio_sel     = (iomem_addr[7:0] == GPIO_DATA);
    assign gpio_oeb_sel = (iomem_addr[7:0] == GPIO_ENA);
    assign gpio_pu_sel  = (iomem_addr[7:0] == GPIO_PU);
    assign gpio_pd_sel  = (iomem_addr[7:0] == GPIO_PD);

    always @(posedge clk) begin
        if (!resetn) begin
            gpio_out <= 32'h0;
            gpio_oeb <= 32'hffff_ffff;
        end else begin
            iomem_ready <= 0;
            if (iomem_valid && !iomem_ready) begin
                iomem_ready <= 1'b 1;

                if (gpio_sel) begin
                    iomem_rdata <= gpio_in;
                    if (iomem_wstrb) gpio_out <= iomem_wdata;

                end else if (gpio_oeb_sel) begin
                    iomem_rdata <= ~gpio_oeb;
                    if (iomem_wstrb) gpio_oeb <= ~iomem_wdata;

                end else if (gpio_pu_sel) begin
                    iomem_rdata <= gpio_pu;
                    if (iomem_wstrb) gpio_pu <= iomem_wdata;

                end else if (gpio_pd_sel) begin
                    iomem_rdata <= gpio_pd;
                    if (iomem_wstrb) gpio_pd <= iomem_wdata;

                end

            end
        end
    end

endmodule
module gpio32 #(
    parameter GPIO_DATA = 8'h 00,
    parameter GPIO_ENA  = 8'h 04,
    parameter GPIO_PU   = 8'h 08,
    parameter GPIO_PD   = 8'h 0c
) (
    input clk,
    input resetn,

    input gpio_in_pad,

    input [31:0] iomem_addr,
    input iomem_valid,
    input iomem_wstrb,
    input [31:0] iomem_wdata,
    output reg [31:0] iomem_rdata,
    output reg iomem_ready,

    input [31:0]  gpio_in,
    output [31:0] gpio_out,
    output [31:0] gpio_oeb
);


    reg [31:0] gpio_out;
    reg [31:0] gpio_pu;
    reg [31:0] gpio_pd;
    reg [31:0] gpio_oeb;

    wire gpio_sel;
    wire gpio_oeb_sel;
    wire gpio_pu_sel;
    wire gpio_pd_sel;

    assign gpio_sel     = (iomem_addr[7:0] == GPIO_DATA);
    assign gpio_oeb_sel = (iomem_addr[7:0] == GPIO_ENA);
    assign gpio_pu_sel  = (iomem_addr[7:0] == GPIO_PU);
    assign gpio_pd_sel  = (iomem_addr[7:0] == GPIO_PD);

    always @(posedge clk) begin
        if (!resetn) begin
            gpio_out <= 32'h0;
            gpio_oeb <= 32'hffff_ffff;
        end else begin
            iomem_ready <= 0;
            if (iomem_valid && !iomem_ready) begin
                iomem_ready <= 1'b 1;

                if (gpio_sel) begin
                    iomem_rdata <= gpio_in;
                    if (iomem_wstrb) gpio_out <= iomem_wdata;

                end else if (gpio_oeb_sel) begin
                    iomem_rdata <= ~gpio_oeb;
                    if (iomem_wstrb) gpio_oeb <= ~iomem_wdata;

                end else if (gpio_pu_sel) begin
                    iomem_rdata <= gpio_pu;
                    if (iomem_wstrb) gpio_pu <= iomem_wdata;

                end else if (gpio_pd_sel) begin
                    iomem_rdata <= gpio_pd;
                    if (iomem_wstrb) gpio_pd <= iomem_wdata;

                end

            end
        end
    end

endmodule