data/full_repos/permissive/450205124/Assignment4/Q2-Eight-Bit-Adder-Subtractor/A4Q2_eight_bit_adder_subtractor_tb.v
1: b'%Error: data/full_repos/permissive/450205124/Assignment4/Q2-Eight-Bit-Adder-Subtractor/A4Q2_eight_bit_adder_subtractor_tb.v:1: Cannot find include file: A4Q2_eight_bit_adder_subtractor.v\n`include "A4Q2_eight_bit_adder_subtractor.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/450205124/Assignment4/Q2-Eight-Bit-Adder-Subtractor,data/full_repos/permissive/450205124/A4Q2_eight_bit_adder_subtractor.v\n             data/full_repos/permissive/450205124/Assignment4/Q2-Eight-Bit-Adder-Subtractor,data/full_repos/permissive/450205124/A4Q2_eight_bit_adder_subtractor.v.v\n             data/full_repos/permissive/450205124/Assignment4/Q2-Eight-Bit-Adder-Subtractor,data/full_repos/permissive/450205124/A4Q2_eight_bit_adder_subtractor.v.sv\n             A4Q2_eight_bit_adder_subtractor.v\n             A4Q2_eight_bit_adder_subtractor.v.v\n             A4Q2_eight_bit_adder_subtractor.v.sv\n             obj_dir/A4Q2_eight_bit_adder_subtractor.v\n             obj_dir/A4Q2_eight_bit_adder_subtractor.v.v\n             obj_dir/A4Q2_eight_bit_adder_subtractor.v.sv\n%Error: data/full_repos/permissive/450205124/Assignment4/Q2-Eight-Bit-Adder-Subtractor/A4Q2_eight_bit_adder_subtractor_tb.v:68: Unsupported or unknown PLI call: $monitor\n $monitor("%4d | %d | %d  |   %b    | %d | %b        | %b | %b | %b", $time, final_a, final_b, opcode, final_sum_or_diff, overflow, a, b, sum);\n ^~~~~~~~\n%Error: data/full_repos/permissive/450205124/Assignment4/Q2-Eight-Bit-Adder-Subtractor/A4Q2_eight_bit_adder_subtractor_tb.v:71: Unsupported or unknown PLI call: $urandom\n  a = $urandom % 256; b = $urandom % 256; opcode = $urandom % 2;\n      ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/450205124/Assignment4/Q2-Eight-Bit-Adder-Subtractor/A4Q2_eight_bit_adder_subtractor_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/450205124/Assignment4/Q2-Eight-Bit-Adder-Subtractor/A4Q2_eight_bit_adder_subtractor_tb.v:71: Unsupported or unknown PLI call: $urandom\n  a = $urandom % 256; b = $urandom % 256; opcode = $urandom % 2;\n                          ^~~~~~~~\n%Error: data/full_repos/permissive/450205124/Assignment4/Q2-Eight-Bit-Adder-Subtractor/A4Q2_eight_bit_adder_subtractor_tb.v:71: Unsupported or unknown PLI call: $urandom\n  a = $urandom % 256; b = $urandom % 256; opcode = $urandom % 2;\n                                                   ^~~~~~~~\n%Error: Exiting due to 5 error(s), 1 warning(s)\n'
module eight_bit_adder_subtractor_tb();
reg [7:0] a;
reg [7:0] b;
reg opcode;
wire [7:0] sum;
wire overflow;
eight_bit_adder_subtractor EBAS (
    .sum(sum), 
    .overflow(overflow), 
    .a(a), 
    .b(b), 
    .opcode(opcode)
    ); 

integer final_sum_or_diff;
integer first_bits;
integer msb;
integer final_a;
integer final_b;
integer first_bits_a;
integer first_bits_b;
integer msb_a;
integer msb_b;

always @(*) begin
    first_bits_a = a[6:0];

end
always @(*) begin
    msb_a = 2*2*2*2*2*2*2*a[7];
 
end
always @(*) begin
    final_a = first_bits_a - msb_a;
end


always @(*) begin
    first_bits_b = b[6:0];

end
always @(*) begin
    msb_b = 2*2*2*2*2*2*2*b[7];
 
end
always @(*) begin
    final_b = first_bits_b - msb_b;
end


always @(*) begin
    first_bits = sum[6:0];

end
always @(*) begin
    msb = 2*2*2*2*2*2*2*sum[7];
 
end
always @(*) begin
    final_sum_or_diff = first_bits - msb;
end

initial begin

    $display("Time |     final_a |      final_b | opcode | sum/diff    | overflow | a        |        b | sum");
	$monitor("%4d | %d | %d  |   %b    | %d | %b        | %b | %b | %b", $time, final_a, final_b, opcode, final_sum_or_diff, overflow, a, b, sum);
	repeat(15) begin
		#5
		a = $urandom % 256; b = $urandom % 256; opcode = $urandom % 2;
	end
end
endmodule
module eight_bit_adder_subtractor_tb();

reg [7:0] a;
reg [7:0] b;
reg opcode;
wire [7:0] sum;
wire overflow;
eight_bit_adder_subtractor EBAS (
    .sum(sum), 
    .overflow(overflow), 
    .a(a), 
    .b(b), 
    .opcode(opcode)
    ); 

integer final_sum_or_diff;
integer first_bits;
integer msb;
integer final_a;
integer final_b;
integer first_bits_a;
integer first_bits_b;
integer msb_a;
integer msb_b;

always @(*) begin
    first_bits_a = a[6:0];

end
always @(*) begin
    msb_a = 2*2*2*2*2*2*2*a[7];
 
end
always @(*) begin
    final_a = first_bits_a - msb_a;
end


always @(*) begin
    first_bits_b = b[6:0];

end
always @(*) begin
    msb_b = 2*2*2*2*2*2*2*b[7];
 
end
always @(*) begin
    final_b = first_bits_b - msb_b;
end


always @(*) begin
    first_bits = sum[6:0];

end
always @(*) begin
    msb = 2*2*2*2*2*2*2*sum[7];
 
end
always @(*) begin
    final_sum_or_diff = first_bits - msb;
end

initial begin

    $display("Time |     final_a |      final_b | opcode | sum/diff    | overflow | a        |        b | sum");
	$monitor("%4d | %d | %d  |   %b    | %d | %b        | %b | %b | %b", $time, final_a, final_b, opcode, final_sum_or_diff, overflow, a, b, sum);
	repeat(15) begin
		#5
		a = $urandom % 256; b = $urandom % 256; opcode = $urandom % 2;
	end
end
endmodule