data/full_repos/permissive/516830490/RTL/clk_div.v
data/verilator_xmls/19b28c32-6589-468b-972e-bcc1a96e2525.xml
module clk_div(i_clk , clk_o);
input i_clk ;
output clk_o ;


parameter CLK_COUNT = 50_000_000;
reg [`CLK_CNT_WIDTH-1:0] clk_cnt = 0;

reg toggle_1HZ = 0;


always @(posedge i_clk)
     begin
          if (clk_cnt == CLK_COUNT-1)
              begin
                  toggle_1HZ <= ~toggle_1HZ ;
                  clk_cnt    <= 0;
               end
          else
                begin          
                  clk_cnt <= clk_cnt + 1'b1 ;
                  toggle_1HZ <= 1'b0 ;
                  end
     end             
   
  assign clk_o = toggle_1HZ ; 
         
endmodule
module clk_div(i_clk , clk_o);

input i_clk ;
output clk_o ;


parameter CLK_COUNT = 50_000_000;
reg [`CLK_CNT_WIDTH-1:0] clk_cnt = 0;

reg toggle_1HZ = 0;


always @(posedge i_clk)
     begin
          if (clk_cnt == CLK_COUNT-1)
              begin
                  toggle_1HZ <= ~toggle_1HZ ;
                  clk_cnt    <= 0;
               end
          else
                begin          
                  clk_cnt <= clk_cnt + 1'b1 ;
                  toggle_1HZ <= 1'b0 ;
                  end
     end             
   
  assign clk_o = toggle_1HZ ; 
         
endmodule