data/full_repos/permissive/422178762/verilog/rtl/apbled.v
data/verilator_xmls/46b98d49-588a-458e-bbdf-9394d91f6a5b.xml
module Queue_led(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [23:0] io_enq_bits,
  input         io_deq_ready,
  output        io_deq_valid,
  output [23:0] io_deq_bits
);
  reg [23:0] ram [0:3];
  reg [31:0] _RAND_0;
  wire [23:0] ram__T_63_data;
  wire [1:0] ram__T_63_addr;
  wire [23:0] ram__T_49_data;
  wire [1:0] ram__T_49_addr;
  wire  ram__T_49_mask;
  wire  ram__T_49_en;
  reg [1:0] value;
  reg [31:0] _RAND_1;
  reg [1:0] value_1;
  reg [31:0] _RAND_2;
  reg  maybe_full;
  reg [31:0] _RAND_3;
  wire  _T_41;
  wire  _T_43;
  wire  empty;
  wire  _T_44;
  wire  do_enq;
  wire  do_deq;
  wire [2:0] _T_52;
  wire [1:0] _T_53;
  wire [1:0] _GEN_5;
  wire [2:0] _T_56;
  wire [1:0] _T_57;
  wire [1:0] _GEN_6;
  wire  _T_58;
  wire  _GEN_7;
  assign ram__T_63_addr = value_1;
  assign ram__T_63_data = ram[ram__T_63_addr];
  assign ram__T_49_data = io_enq_bits;
  assign ram__T_49_addr = value;
  assign ram__T_49_mask = 1'h1;
  assign ram__T_49_en = io_enq_ready & io_enq_valid;
  assign _T_41 = value == value_1;
  assign _T_43 = maybe_full == 1'h0;
  assign empty = _T_41 & _T_43;
  assign _T_44 = _T_41 & maybe_full;
  assign do_enq = io_enq_ready & io_enq_valid;
  assign do_deq = io_deq_ready & io_deq_valid;
  assign _T_52 = value + 2'h1;
  assign _T_53 = _T_52[1:0];
  assign _GEN_5 = do_enq ? _T_53 : value;
  assign _T_56 = value_1 + 2'h1;
  assign _T_57 = _T_56[1:0];
  assign _GEN_6 = do_deq ? _T_57 : value_1;
  assign _T_58 = do_enq != do_deq;
  assign _GEN_7 = _T_58 ? do_enq : maybe_full;
  assign io_enq_ready = _T_44 == 1'h0;
  assign io_deq_valid = empty == 1'h0;
  assign io_deq_bits = ram__T_63_data;
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
  integer initvar;
  initial begin
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
  _RAND_0 = {1{`RANDOM}};
  `ifdef RANDOMIZE_MEM_INIT
  for (initvar = 0; initvar < 4; initvar = initvar+1)
    ram[initvar] = _RAND_0[23:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_1 = {1{`RANDOM}};
  value = _RAND_1[1:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_2 = {1{`RANDOM}};
  value_1 = _RAND_2[1:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_3 = {1{`RANDOM}};
  maybe_full = _RAND_3[0:0];
  `endif
  end
`endif
  always @(posedge clock) begin
    if(ram__T_49_en & ram__T_49_mask) begin
      ram[ram__T_49_addr] <= ram__T_49_data;
    end
    if (reset) begin
      value <= 2'h0;
    end else begin
      if (do_enq) begin
        value <= _T_53;
      end
    end
    if (reset) begin
      value_1 <= 2'h0;
    end else begin
      if (do_deq) begin
        value_1 <= _T_57;
      end
    end
    if (reset) begin
      maybe_full <= 1'h0;
    end else begin
      if (_T_58) begin
        maybe_full <= do_enq;
      end
    end
  end
endmodule
module Queue_led(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [23:0] io_enq_bits,
  input         io_deq_ready,
  output        io_deq_valid,
  output [23:0] io_deq_bits
);

  reg [23:0] ram [0:3];
  reg [31:0] _RAND_0;
  wire [23:0] ram__T_63_data;
  wire [1:0] ram__T_63_addr;
  wire [23:0] ram__T_49_data;
  wire [1:0] ram__T_49_addr;
  wire  ram__T_49_mask;
  wire  ram__T_49_en;
  reg [1:0] value;
  reg [31:0] _RAND_1;
  reg [1:0] value_1;
  reg [31:0] _RAND_2;
  reg  maybe_full;
  reg [31:0] _RAND_3;
  wire  _T_41;
  wire  _T_43;
  wire  empty;
  wire  _T_44;
  wire  do_enq;
  wire  do_deq;
  wire [2:0] _T_52;
  wire [1:0] _T_53;
  wire [1:0] _GEN_5;
  wire [2:0] _T_56;
  wire [1:0] _T_57;
  wire [1:0] _GEN_6;
  wire  _T_58;
  wire  _GEN_7;
  assign ram__T_63_addr = value_1;
  assign ram__T_63_data = ram[ram__T_63_addr];
  assign ram__T_49_data = io_enq_bits;
  assign ram__T_49_addr = value;
  assign ram__T_49_mask = 1'h1;
  assign ram__T_49_en = io_enq_ready & io_enq_valid;
  assign _T_41 = value == value_1;
  assign _T_43 = maybe_full == 1'h0;
  assign empty = _T_41 & _T_43;
  assign _T_44 = _T_41 & maybe_full;
  assign do_enq = io_enq_ready & io_enq_valid;
  assign do_deq = io_deq_ready & io_deq_valid;
  assign _T_52 = value + 2'h1;
  assign _T_53 = _T_52[1:0];
  assign _GEN_5 = do_enq ? _T_53 : value;
  assign _T_56 = value_1 + 2'h1;
  assign _T_57 = _T_56[1:0];
  assign _GEN_6 = do_deq ? _T_57 : value_1;
  assign _T_58 = do_enq != do_deq;
  assign _GEN_7 = _T_58 ? do_enq : maybe_full;
  assign io_enq_ready = _T_44 == 1'h0;
  assign io_deq_valid = empty == 1'h0;
  assign io_deq_bits = ram__T_63_data;
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
  integer initvar;
  initial begin
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
  _RAND_0 = {1{`RANDOM}};
  `ifdef RANDOMIZE_MEM_INIT
  for (initvar = 0; initvar < 4; initvar = initvar+1)
    ram[initvar] = _RAND_0[23:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_1 = {1{`RANDOM}};
  value = _RAND_1[1:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_2 = {1{`RANDOM}};
  value_1 = _RAND_2[1:0];
  `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_3 = {1{`RANDOM}};
  maybe_full = _RAND_3[0:0];
  `endif
  end
`endif
  always @(posedge clock) begin
    if(ram__T_49_en & ram__T_49_mask) begin
      ram[ram__T_49_addr] <= ram__T_49_data;
    end
    if (reset) begin
      value <= 2'h0;
    end else begin
      if (do_enq) begin
        value <= _T_53;
      end
    end
    if (reset) begin
      value_1 <= 2'h0;
    end else begin
      if (do_deq) begin
        value_1 <= _T_57;
      end
    end
    if (reset) begin
      maybe_full <= 1'h0;
    end else begin
      if (_T_58) begin
        maybe_full <= do_enq;
      end
    end
  end
endmodule