data/full_repos/permissive/485085993/verilog/rtl/arch_encoder.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/485085993/verilog/rtl/arch_encoder.v:88: Multiple top level modules\n                                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                     : ... Top module \'decoder_with_data_in_5to29\'\nmodule decoder_with_data_in_5to29(enable,\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                     : ... Top module \'decoder5to29\'\nmodule decoder5to29(enable,\n       ^~~~~~~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/arch_encoder.v:94: Little bit endian vector: MSB < LSB of bit range: 0:4\ninput [0:4] address;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/arch_encoder.v:96: Little bit endian vector: MSB < LSB of bit range: 0:28\noutput [0:28] data_out;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/arch_encoder.v:22: Little bit endian vector: MSB < LSB of bit range: 0:4\ninput [0:4] address;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/arch_encoder.v:26: Little bit endian vector: MSB < LSB of bit range: 0:28\noutput [0:28] data_out;\n       ^\n%Error: Exiting due to 5 warning(s)\n'
module decoder5to29(enable,
                    address,
                    data_out);

input [0:0] enable;

input [0:4] address;

output [0:28] data_out;






reg [0:28] data_out;



always@(address[0:4] or enable[0]) begin
	if (enable[0] == 1'b1) begin
		case (address[0:4])
			{5{1'b0}} : data_out[0:28] = 29'b10000000000000000000000000000;
			5'b10000 : data_out[0:28] = 29'b01000000000000000000000000000;
			5'b01000 : data_out[0:28] = 29'b00100000000000000000000000000;
			5'b11000 : data_out[0:28] = 29'b00010000000000000000000000000;
			5'b00100 : data_out[0:28] = 29'b00001000000000000000000000000;
			5'b10100 : data_out[0:28] = 29'b00000100000000000000000000000;
			5'b01100 : data_out[0:28] = 29'b00000010000000000000000000000;
			5'b11100 : data_out[0:28] = 29'b00000001000000000000000000000;
			5'b00010 : data_out[0:28] = 29'b00000000100000000000000000000;
			5'b10010 : data_out[0:28] = 29'b00000000010000000000000000000;
			5'b01010 : data_out[0:28] = 29'b00000000001000000000000000000;
			5'b11010 : data_out[0:28] = 29'b00000000000100000000000000000;
			5'b00110 : data_out[0:28] = 29'b00000000000010000000000000000;
			5'b10110 : data_out[0:28] = 29'b00000000000001000000000000000;
			5'b01110 : data_out[0:28] = 29'b00000000000000100000000000000;
			5'b11110 : data_out[0:28] = 29'b00000000000000010000000000000;
			5'b00001 : data_out[0:28] = 29'b00000000000000001000000000000;
			5'b10001 : data_out[0:28] = 29'b00000000000000000100000000000;
			5'b01001 : data_out[0:28] = 29'b00000000000000000010000000000;
			5'b11001 : data_out[0:28] = 29'b00000000000000000001000000000;
			5'b00101 : data_out[0:28] = 29'b00000000000000000000100000000;
			5'b10101 : data_out[0:28] = 29'b00000000000000000000010000000;
			5'b01101 : data_out[0:28] = 29'b00000000000000000000001000000;
			5'b11101 : data_out[0:28] = 29'b00000000000000000000000100000;
			5'b00011 : data_out[0:28] = 29'b00000000000000000000000010000;
			5'b10011 : data_out[0:28] = 29'b00000000000000000000000001000;
			5'b01011 : data_out[0:28] = 29'b00000000000000000000000000100;
			5'b11011 : data_out[0:28] = 29'b00000000000000000000000000010;
			5'b00111 : data_out[0:28] = 29'b00000000000000000000000000001;
			default : data_out[0:28] = {29{1'b0}};
		endcase
	end
	else begin
		data_out[0:28] = {29{1'b0}};
	end
end

endmodule
module decoder5to29(enable,
                    address,
                    data_out);


input [0:0] enable;

input [0:4] address;

output [0:28] data_out;






reg [0:28] data_out;



always@(address[0:4] or enable[0]) begin
	if (enable[0] == 1'b1) begin
		case (address[0:4])
			{5{1'b0}} : data_out[0:28] = 29'b10000000000000000000000000000;
			5'b10000 : data_out[0:28] = 29'b01000000000000000000000000000;
			5'b01000 : data_out[0:28] = 29'b00100000000000000000000000000;
			5'b11000 : data_out[0:28] = 29'b00010000000000000000000000000;
			5'b00100 : data_out[0:28] = 29'b00001000000000000000000000000;
			5'b10100 : data_out[0:28] = 29'b00000100000000000000000000000;
			5'b01100 : data_out[0:28] = 29'b00000010000000000000000000000;
			5'b11100 : data_out[0:28] = 29'b00000001000000000000000000000;
			5'b00010 : data_out[0:28] = 29'b00000000100000000000000000000;
			5'b10010 : data_out[0:28] = 29'b00000000010000000000000000000;
			5'b01010 : data_out[0:28] = 29'b00000000001000000000000000000;
			5'b11010 : data_out[0:28] = 29'b00000000000100000000000000000;
			5'b00110 : data_out[0:28] = 29'b00000000000010000000000000000;
			5'b10110 : data_out[0:28] = 29'b00000000000001000000000000000;
			5'b01110 : data_out[0:28] = 29'b00000000000000100000000000000;
			5'b11110 : data_out[0:28] = 29'b00000000000000010000000000000;
			5'b00001 : data_out[0:28] = 29'b00000000000000001000000000000;
			5'b10001 : data_out[0:28] = 29'b00000000000000000100000000000;
			5'b01001 : data_out[0:28] = 29'b00000000000000000010000000000;
			5'b11001 : data_out[0:28] = 29'b00000000000000000001000000000;
			5'b00101 : data_out[0:28] = 29'b00000000000000000000100000000;
			5'b10101 : data_out[0:28] = 29'b00000000000000000000010000000;
			5'b01101 : data_out[0:28] = 29'b00000000000000000000001000000;
			5'b11101 : data_out[0:28] = 29'b00000000000000000000000100000;
			5'b00011 : data_out[0:28] = 29'b00000000000000000000000010000;
			5'b10011 : data_out[0:28] = 29'b00000000000000000000000001000;
			5'b01011 : data_out[0:28] = 29'b00000000000000000000000000100;
			5'b11011 : data_out[0:28] = 29'b00000000000000000000000000010;
			5'b00111 : data_out[0:28] = 29'b00000000000000000000000000001;
			default : data_out[0:28] = {29{1'b0}};
		endcase
	end
	else begin
		data_out[0:28] = {29{1'b0}};
	end
end

endmodule