data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_sstl_pad.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_sstl_pad.v:77: Cannot find file containing module: 'bw_io_ddr_pad_txrx'\nbw_io_ddr_pad_txrx bw_io_ddr_pad_txrx( \n^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_io_ddr_pad_txrx\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_io_ddr_pad_txrx.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_io_ddr_pad_txrx.sv\n             bw_io_ddr_pad_txrx\n             bw_io_ddr_pad_txrx.v\n             bw_io_ddr_pad_txrx.sv\n             obj_dir/bw_io_ddr_pad_txrx\n             obj_dir/bw_io_ddr_pad_txrx.v\n             obj_dir/bw_io_ddr_pad_txrx.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_sstl_pad.v:102: Cannot find file containing module: 'bw_io_sstl_bscan'\nbw_io_sstl_bscan bw_io_sstl_bscan( \n^~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module dram_sstl_pad(

   to_core, bso, 

   pad, 

   vrefcode, vdd_h, update_dr, shift_dr, oe, odt_enable_mask, 
   mode_ctrl, hiz_n, data_in, clock_dr, cbu, cbd, bsi
   );

inout			pad;



output			bso;
output			to_core;




input			bsi;
input [8:1]		cbd;
input [8:1]		cbu;
input			clock_dr;
input			data_in;
input			hiz_n;
input			mode_ctrl;
input			odt_enable_mask;
input			oe;
input			shift_dr;
input			update_dr;
input			vdd_h;
input [7:0]		vrefcode;




wire			bscan_oe;
wire			data_out;
wire			odt_enable;
wire			rx_out;









bw_io_ddr_pad_txrx bw_io_ddr_pad_txrx(

				      .out(rx_out),

				      .pad(pad),

				      .vrefcode(vrefcode[7:0]),
				      .odt_enable(odt_enable),
				      .vdd_h(vdd_h),
				      .cbu(cbu[8:1]),
				      .cbd(cbd[8:1]),
				      .data(data_out),
				      .oe(bscan_oe));






bw_io_sstl_bscan	bw_io_sstl_bscan(

					   .to_core(to_core),
					   .data_out(data_out),
					   .oe(bscan_oe),
					   .bso(bso),
					   .odt_enable(odt_enable),

					   .bsi(bsi),
					   .mode_ctrl(mode_ctrl),
					   .clock_dr(clock_dr),
					   .shift_dr(shift_dr),
					   .update_dr(update_dr),
					   .hiz_l(hiz_n),
					   .rcv_in(rx_out),
					   .data_in(data_in),
					   .drv_oe(oe),
					   .odt_enable_mask(odt_enable_mask));
endmodule
module dram_sstl_pad(

   to_core, bso, 

   pad, 

   vrefcode, vdd_h, update_dr, shift_dr, oe, odt_enable_mask, 
   mode_ctrl, hiz_n, data_in, clock_dr, cbu, cbd, bsi
   );


inout			pad;



output			bso;
output			to_core;




input			bsi;
input [8:1]		cbd;
input [8:1]		cbu;
input			clock_dr;
input			data_in;
input			hiz_n;
input			mode_ctrl;
input			odt_enable_mask;
input			oe;
input			shift_dr;
input			update_dr;
input			vdd_h;
input [7:0]		vrefcode;




wire			bscan_oe;
wire			data_out;
wire			odt_enable;
wire			rx_out;









bw_io_ddr_pad_txrx bw_io_ddr_pad_txrx(

				      .out(rx_out),

				      .pad(pad),

				      .vrefcode(vrefcode[7:0]),
				      .odt_enable(odt_enable),
				      .vdd_h(vdd_h),
				      .cbu(cbu[8:1]),
				      .cbd(cbd[8:1]),
				      .data(data_out),
				      .oe(bscan_oe));






bw_io_sstl_bscan	bw_io_sstl_bscan(

					   .to_core(to_core),
					   .data_out(data_out),
					   .oe(bscan_oe),
					   .bso(bso),
					   .odt_enable(odt_enable),

					   .bsi(bsi),
					   .mode_ctrl(mode_ctrl),
					   .clock_dr(clock_dr),
					   .shift_dr(shift_dr),
					   .update_dr(update_dr),
					   .hiz_l(hiz_n),
					   .rcv_in(rx_out),
					   .data_in(data_in),
					   .drv_oe(oe),
					   .odt_enable_mask(odt_enable_mask));
endmodule