data/full_repos/permissive/524522105/async_mem/src/async_mem_test.v
1: b"%Error: data/full_repos/permissive/524522105/async_mem/src/async_mem_test.v:17: Cannot find file containing module: 'Gowin_CLKDIV'\n  Gowin_CLKDIV slow_clock ( .clkout(test_clock),\n  ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/524522105/async_mem/src,data/full_repos/permissive/524522105/Gowin_CLKDIV\n             data/full_repos/permissive/524522105/async_mem/src,data/full_repos/permissive/524522105/Gowin_CLKDIV.v\n             data/full_repos/permissive/524522105/async_mem/src,data/full_repos/permissive/524522105/Gowin_CLKDIV.sv\n             Gowin_CLKDIV\n             Gowin_CLKDIV.v\n             Gowin_CLKDIV.sv\n             obj_dir/Gowin_CLKDIV\n             obj_dir/Gowin_CLKDIV.v\n             obj_dir/Gowin_CLKDIV.sv\n%Error: data/full_repos/permissive/524522105/async_mem/src/async_mem_test.v:24: Cannot find file containing module: 'pulse_gen'\n  pulse_gen #( .CTR_WIDTH(8),\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/524522105/async_mem/src/async_mem_test.v:29: Cannot find file containing module: 'pulse_gen'\n  pulse_gen #( .CTR_WIDTH(9),\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/524522105/async_mem/src/async_mem_test.v:34: Cannot find file containing module: 'async_mem_2'\n  async_mem_2 mem ( .on(on_sig),\n  ^~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module async_mem_test ( input  clock,
                        output on_sig,
                        output off_sig,
                        output mem_out );

  wire ref_sig;

  wire on_pulse;
  wire off_pulse;
  wire feedback;
  wire test_clock;

  Gowin_CLKDIV slow_clock ( .clkout(test_clock),
                            .hclkin(clock),
                            .resetn(1'b1) );




  pulse_gen #( .CTR_WIDTH(8),
               .PLS_WIDTH(7) )
     on_pls  ( .clock(test_clock),
               .pulse(on_sig) );

  pulse_gen #( .CTR_WIDTH(9),
               .PLS_WIDTH(7) )
    off_pls  ( .clock(test_clock),
               .pulse(off_sig) );

  async_mem_2 mem ( .on(on_sig),
                    .off(off_sig),
                    .q(mem_out) );

endmodule
module async_mem_test ( input  clock,
                        output on_sig,
                        output off_sig,
                        output mem_out );


  wire ref_sig;

  wire on_pulse;
  wire off_pulse;
  wire feedback;
  wire test_clock;

  Gowin_CLKDIV slow_clock ( .clkout(test_clock),
                            .hclkin(clock),
                            .resetn(1'b1) );




  pulse_gen #( .CTR_WIDTH(8),
               .PLS_WIDTH(7) )
     on_pls  ( .clock(test_clock),
               .pulse(on_sig) );

  pulse_gen #( .CTR_WIDTH(9),
               .PLS_WIDTH(7) )
    off_pls  ( .clock(test_clock),
               .pulse(off_sig) );

  async_mem_2 mem ( .on(on_sig),
                    .off(off_sig),
                    .q(mem_out) );

endmodule