data/full_repos/permissive/458870430/rtl/eraser.v
1: b"%Error: data/full_repos/permissive/458870430/rtl/eraser.v:20: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'START_RAM'\n                                                            : ... In instance eraser\nparameter [24:0] START_RAM;\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/458870430/rtl/eraser.v:21: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'END_RAM'\n                                                            : ... In instance eraser\nparameter [24:0] END_RAM;\n                 ^~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module eraser(	
	input 			   clk,
	input             ena,
	input             trigger,
	
	output reg        erasing,


	output reg        wr,
	output reg [24:0] addr,
	output reg [7:0]  data
);

reg [24:0] pos;

parameter [24:0] START_RAM;
parameter [24:0] END_RAM;


always @(posedge clk) begin
	if(ena) begin
		if(trigger && !erasing) begin
			erasing <= 1;		
			pos <= START_RAM;		
		end
		
		if(erasing) begin
			wr <= 1;
			addr <= pos;
			data <= 'hff;			
			pos  <= pos + 1;
			if(pos == END_RAM + 1) begin
				erasing <= 0;
				wr <= 0;
			end				
		end		
	end
end

endmodule
module eraser(	
	input 			   clk,
	input             ena,
	input             trigger,
	
	output reg        erasing,


	output reg        wr,
	output reg [24:0] addr,
	output reg [7:0]  data
);


reg [24:0] pos;

parameter [24:0] START_RAM;
parameter [24:0] END_RAM;


always @(posedge clk) begin
	if(ena) begin
		if(trigger && !erasing) begin
			erasing <= 1;		
			pos <= START_RAM;		
		end
		
		if(erasing) begin
			wr <= 1;
			addr <= pos;
			data <= 'hff;			
			pos  <= pos + 1;
			if(pos == END_RAM + 1) begin
				erasing <= 0;
				wr <= 0;
			end				
		end		
	end
end

endmodule