data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/ATDFF.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/ATDFF.v:14: Cannot find file containing module: 'fflopx'\nfflopx #(1) FF(CK,RST_,D,Out);\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim,data/full_repos/permissive/530013823/fflopx\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim,data/full_repos/permissive/530013823/fflopx.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim,data/full_repos/permissive/530013823/fflopx.sv\n             fflopx\n             fflopx.v\n             fflopx.sv\n             obj_dir/fflopx\n             obj_dir/fflopx.v\n             obj_dir/fflopx.sv\n%Error: Exiting due to 1 error(s)\n"
module ATDFF
    (
     D,
     CK,
     RST_,
     Q
     );
input D;
input CK;
input RST_;
output Q;

wire   Out;
fflopx #(1) FF(CK,RST_,D,Out);

reg    Q;
always @(Out)
    begin

    Q = Out;
    end

endmodule
module ATDFF
    (
     D,
     CK,
     RST_,
     Q
     );

input D;
input CK;
input RST_;
output Q;

wire   Out;
fflopx #(1) FF(CK,RST_,D,Out);

reg    Q;
always @(Out)
    begin

    Q = Out;
    end

endmodule