data/full_repos/permissive/500128826/HDLBits/Modules/Module_addsub/add16.v
1: b'%Warning-WIDTH: data/full_repos/permissive/500128826/HDLBits/Modules/Module_addsub/add16.v:18: Operator ADD expects 17 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                                             : ... In instance add16\n  assign {cout, sum} = a + b + cin;\n                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module add16 (
    input wire [15:0] a,
    input wire [15:0] b,
    input wire cin,
    output wire [15:0] sum,
    output wire cout
);

  assign {cout, sum} = a + b + cin;
endmodule
module add16 (
    input wire [15:0] a,
    input wire [15:0] b,
    input wire cin,
    output wire [15:0] sum,
    output wire cout
);


  assign {cout, sum} = a + b + cin;
endmodule