data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/macro/rdygen_cc.v
data/verilator_xmls/4d51f30d-e8cc-4045-9dfd-59236dfedd20.xml
module rdygen_cc
    (
     clk,
     pce_,
     rdyin,
     rdyout_ccxxx
     );




input   clk;
input   pce_;
input   rdyin;
output  rdyout_ccxxx;

wire        cerst;
assign      cerst = pce_;

reg     rdyout_ccxxx = 1'b0;
always @ (posedge clk)
    begin
    if (cerst)    rdyout_ccxxx <= 1'b0;
    else
        case (rdyin)
            1'b1:       rdyout_ccxxx <= rdyin;
            default:    rdyout_ccxxx <= rdyout_ccxxx;
        endcase
    end

endmodule
module rdygen_cc
    (
     clk,
     pce_,
     rdyin,
     rdyout_ccxxx
     );





input   clk;
input   pce_;
input   rdyin;
output  rdyout_ccxxx;

wire        cerst;
assign      cerst = pce_;

reg     rdyout_ccxxx = 1'b0;
always @ (posedge clk)
    begin
    if (cerst)    rdyout_ccxxx <= 1'b0;
    else
        case (rdyin)
            1'b1:       rdyout_ccxxx <= rdyin;
            default:    rdyout_ccxxx <= rdyout_ccxxx;
        endcase
    end

endmodule