data/full_repos/permissive/431550602/sources_1/uart.v
1: b"%Error: data/full_repos/permissive/431550602/sources_1/uart.v:17: Cannot find file containing module: 'uart_baudrate_generator'\n uart_baudrate_generator #(.divisior(baud_gen_divisior)) baud_gen(.clk(clk), .reset(reset), .uart_tick(baud_tick));\n ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/431550602/sources_1,data/full_repos/permissive/431550602/uart_baudrate_generator\n             data/full_repos/permissive/431550602/sources_1,data/full_repos/permissive/431550602/uart_baudrate_generator.v\n             data/full_repos/permissive/431550602/sources_1,data/full_repos/permissive/431550602/uart_baudrate_generator.sv\n             uart_baudrate_generator\n             uart_baudrate_generator.v\n             uart_baudrate_generator.sv\n             obj_dir/uart_baudrate_generator\n             obj_dir/uart_baudrate_generator.v\n             obj_dir/uart_baudrate_generator.sv\n%Error: data/full_repos/permissive/431550602/sources_1/uart.v:19: Cannot find file containing module: 'uart_tx'\n uart_tx #(.DBIT(data_bits), .S_TICK_LIM(bit_ticks), .STOP_BITS_LIM(stop_ticks)) \n ^~~~~~~\n%Error: data/full_repos/permissive/431550602/sources_1/uart.v:22: Cannot find file containing module: 'uart_rx'\n uart_rx #(.DBIT(data_bits), .S_TICK_LIM(bit_ticks), .STOP_BITS_LIM(stop_ticks)) \n ^~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module uart(
	input clk, reset, rx, tx_start,
	output tx, rx_done, tx_done,
	input [7:0] t_data,
	output [7:0] r_data
	);

	wire baud_tick;
	
	localparam baud_gen_divisior = 54,
                   data_bits = 8,
                   stop_ticks = 16,
	           bit_ticks = 16;
	
	uart_baudrate_generator #(.divisior(baud_gen_divisior)) baud_gen(.clk(clk), .reset(reset), .uart_tick(baud_tick));
	
	uart_tx #(.DBIT(data_bits), .S_TICK_LIM(bit_ticks), .STOP_BITS_LIM(stop_ticks)) 
	uart_transmit(.clk(clk), .reset(reset), .tx_start(tx_start), .tx(tx), .s_tick(baud_tick), .tx_done_tick(tx_done), .data_in(t_data));
	
	uart_rx #(.DBIT(data_bits), .S_TICK_LIM(bit_ticks), .STOP_BITS_LIM(stop_ticks)) 
	uart_receive(.clk(clk), .reset(reset), .rx(rx), .s_tick(baud_tick), .rx_done_tick(rx_done), .data_out(r_data));

endmodule
module uart(
	input clk, reset, rx, tx_start,
	output tx, rx_done, tx_done,
	input [7:0] t_data,
	output [7:0] r_data
	);


	wire baud_tick;
	
	localparam baud_gen_divisior = 54,
                   data_bits = 8,
                   stop_ticks = 16,
	           bit_ticks = 16;
	
	uart_baudrate_generator #(.divisior(baud_gen_divisior)) baud_gen(.clk(clk), .reset(reset), .uart_tick(baud_tick));
	
	uart_tx #(.DBIT(data_bits), .S_TICK_LIM(bit_ticks), .STOP_BITS_LIM(stop_ticks)) 
	uart_transmit(.clk(clk), .reset(reset), .tx_start(tx_start), .tx(tx), .s_tick(baud_tick), .tx_done_tick(tx_done), .data_in(t_data));
	
	uart_rx #(.DBIT(data_bits), .S_TICK_LIM(bit_ticks), .STOP_BITS_LIM(stop_ticks)) 
	uart_receive(.clk(clk), .reset(reset), .rx(rx), .s_tick(baud_tick), .rx_done_tick(rx_done), .data_out(r_data));

endmodule