data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/rubik/NV_NVDLA_rubik.v
1: b"%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/rubik/NV_NVDLA_rubik.v:179: Cannot find file containing module: 'NV_NVDLA_RUBIK_regfile'\nNV_NVDLA_RUBIK_regfile u_regfile (\n^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/rubik,data/full_repos/permissive/509468557/NV_NVDLA_RUBIK_regfile\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/rubik,data/full_repos/permissive/509468557/NV_NVDLA_RUBIK_regfile.v\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/rubik,data/full_repos/permissive/509468557/NV_NVDLA_RUBIK_regfile.sv\n             NV_NVDLA_RUBIK_regfile\n             NV_NVDLA_RUBIK_regfile.v\n             NV_NVDLA_RUBIK_regfile.sv\n             obj_dir/NV_NVDLA_RUBIK_regfile\n             obj_dir/NV_NVDLA_RUBIK_regfile.v\n             obj_dir/NV_NVDLA_RUBIK_regfile.sv\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/rubik/NV_NVDLA_rubik.v:220: Cannot find file containing module: 'NV_NVDLA_RUBIK_intr'\nNV_NVDLA_RUBIK_intr u_intr (\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/rubik/NV_NVDLA_rubik.v:231: Cannot find file containing module: 'NV_NVDLA_RUBIK_dma'\nNV_NVDLA_RUBIK_dma u_dma (\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/rubik/NV_NVDLA_rubik.v:271: Cannot find file containing module: 'NV_NVDLA_RUBIK_seq_gen'\nNV_NVDLA_RUBIK_seq_gen u_seq_gen (\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/rubik/NV_NVDLA_rubik.v:318: Cannot find file containing module: 'NV_NVDLA_RUBIK_wr_req'\nNV_NVDLA_RUBIK_wr_req u_wr_req (\n^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/rubik/NV_NVDLA_rubik.v:340: Cannot find file containing module: 'NV_NVDLA_RUBIK_rf_ctrl'\nNV_NVDLA_RUBIK_rf_ctrl u_rf_ctrl (\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/rubik/NV_NVDLA_rubik.v:369: Cannot find file containing module: 'NV_NVDLA_RUBIK_dr2drc'\nNV_NVDLA_RUBIK_dr2drc u_dr2drc (\n^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/rubik/NV_NVDLA_rubik.v:382: Cannot find file containing module: 'NV_NVDLA_RUBIK_rf_core'\nNV_NVDLA_RUBIK_rf_core u_rf_core (\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/rubik/NV_NVDLA_rubik.v:404: Cannot find file containing module: 'NV_NVDLA_RUBIK_slcg'\nNV_NVDLA_RUBIK_slcg u_slcg_op_0 (\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/rubik/NV_NVDLA_rubik.v:414: Cannot find file containing module: 'NV_NVDLA_RUBIK_slcg'\nNV_NVDLA_RUBIK_slcg u_slcg_op_1 (\n^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/rubik/NV_NVDLA_rubik.v:424: Cannot find file containing module: 'NV_NVDLA_RUBIK_slcg'\nNV_NVDLA_RUBIK_slcg u_slcg_op_2 (\n^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 11 error(s)\n"
module NV_NVDLA_rubik (
   nvdla_core_clk
  ,nvdla_core_rstn
  ,csb2rbk_req_pvld
  ,csb2rbk_req_prdy
  ,csb2rbk_req_pd
  ,rbk2csb_resp_valid
  ,rbk2csb_resp_pd
  ,pwrbus_ram_pd
  ,rbk2mcif_rd_req_valid
  ,rbk2mcif_rd_req_ready
  ,rbk2mcif_rd_req_pd
  ,rbk2cvif_rd_req_valid
  ,rbk2cvif_rd_req_ready
  ,rbk2cvif_rd_req_pd
  ,mcif2rbk_rd_rsp_valid
  ,mcif2rbk_rd_rsp_ready
  ,mcif2rbk_rd_rsp_pd
  ,cvif2rbk_rd_rsp_valid
  ,cvif2rbk_rd_rsp_ready
  ,cvif2rbk_rd_rsp_pd
  ,rbk2mcif_wr_req_valid
  ,rbk2mcif_wr_req_ready
  ,rbk2mcif_wr_req_pd
  ,mcif2rbk_wr_rsp_complete
  ,rbk2cvif_wr_req_valid
  ,rbk2cvif_wr_req_ready
  ,rbk2cvif_wr_req_pd
  ,cvif2rbk_wr_rsp_complete
  ,rbk2mcif_rd_cdt_lat_fifo_pop
  ,rbk2cvif_rd_cdt_lat_fifo_pop
  ,rubik2glb_done_intr_pd
  ,dla_clk_ovr_on_sync
  ,global_clk_ovr_on_sync
  ,tmc2slcg_disable_clock_gating
  );





input  nvdla_core_clk;
input  nvdla_core_rstn;

input         csb2rbk_req_pvld;
output        csb2rbk_req_prdy;
input  [62:0] csb2rbk_req_pd;

output        rbk2csb_resp_valid;
output [33:0] rbk2csb_resp_pd;

input [31:0] pwrbus_ram_pd;

output        rbk2mcif_rd_req_valid;
input         rbk2mcif_rd_req_ready;
output [78:0] rbk2mcif_rd_req_pd;

output        rbk2cvif_rd_req_valid;
input         rbk2cvif_rd_req_ready;
output [78:0] rbk2cvif_rd_req_pd;

input          mcif2rbk_rd_rsp_valid;
output         mcif2rbk_rd_rsp_ready;
input  [513:0] mcif2rbk_rd_rsp_pd;

input          cvif2rbk_rd_rsp_valid;
output         cvif2rbk_rd_rsp_ready;
input  [513:0] cvif2rbk_rd_rsp_pd;

output         rbk2mcif_wr_req_valid;
input          rbk2mcif_wr_req_ready;
output [514:0] rbk2mcif_wr_req_pd;

input  mcif2rbk_wr_rsp_complete;

output         rbk2cvif_wr_req_valid;
input          rbk2cvif_wr_req_ready;
output [514:0] rbk2cvif_wr_req_pd;

input  cvif2rbk_wr_rsp_complete;

output  rbk2mcif_rd_cdt_lat_fifo_pop;

output  rbk2cvif_rd_cdt_lat_fifo_pop;

output [1:0] rubik2glb_done_intr_pd;

input   dla_clk_ovr_on_sync;
input   global_clk_ovr_on_sync;
input   tmc2slcg_disable_clock_gating;



wire         contract_lit_dx;
wire [511:0] data_fifo_pd;
wire         data_fifo_rdy;
wire         data_fifo_vld;
wire  [77:0] dma_wr_cmd_pd;
wire         dma_wr_cmd_rdy;
wire         dma_wr_cmd_vld;
wire [513:0] dma_wr_data_pd;
wire         dma_wr_data_rdy;
wire         dma_wr_data_vld;
wire         dp2reg_consumer;
wire  [31:0] dp2reg_d0_rd_stall_cnt;
wire  [31:0] dp2reg_d0_wr_stall_cnt;
wire  [31:0] dp2reg_d1_rd_stall_cnt;
wire  [31:0] dp2reg_d1_wr_stall_cnt;
wire         dp2reg_done;
wire  [13:0] inwidth;
wire         nvdla_op_gated_clk_0;
wire         nvdla_op_gated_clk_1;
wire         nvdla_op_gated_clk_2;
wire         rd_cdt_lat_fifo_pop;
wire  [78:0] rd_req_pd;
wire         rd_req_rdy;
wire         rd_req_type;
wire         rd_req_vld;
wire [513:0] rd_rsp_pd;
wire         rd_rsp_rdy;
wire         rd_rsp_vld;
wire  [26:0] reg2dp_contract_stride_0;
wire  [26:0] reg2dp_contract_stride_1;
wire  [31:0] reg2dp_dain_addr_high;
wire  [26:0] reg2dp_dain_addr_low;
wire  [26:0] reg2dp_dain_line_stride;
wire  [26:0] reg2dp_dain_planar_stride;
wire  [26:0] reg2dp_dain_surf_stride;
wire  [31:0] reg2dp_daout_addr_high;
wire  [26:0] reg2dp_daout_addr_low;
wire  [26:0] reg2dp_daout_line_stride;
wire  [26:0] reg2dp_daout_planar_stride;
wire  [26:0] reg2dp_daout_surf_stride;
wire  [12:0] reg2dp_datain_channel;
wire  [12:0] reg2dp_datain_height;
wire         reg2dp_datain_ram_type;
wire  [12:0] reg2dp_datain_width;
wire  [12:0] reg2dp_dataout_channel;
wire         reg2dp_dataout_ram_type;
wire   [4:0] reg2dp_deconv_x_stride;
wire   [4:0] reg2dp_deconv_y_stride;
wire   [1:0] reg2dp_in_precision;
wire         reg2dp_op_en;
wire         reg2dp_perf_en;
wire   [1:0] reg2dp_rubik_mode;
wire   [4:0] rf_rd_addr;
wire  [11:0] rf_rd_cmd_pd;
wire         rf_rd_cmd_rdy;
wire         rf_rd_cmd_vld;
wire         rf_rd_done;
wire  [11:0] rf_rd_mask;
wire         rf_rd_rdy;
wire         rf_rd_vld;
wire   [4:0] rf_wr_addr;
wire  [10:0] rf_wr_cmd_pd;
wire         rf_wr_cmd_rdy;
wire         rf_wr_cmd_vld;
wire [511:0] rf_wr_data;
wire         rf_wr_done;
wire         rf_wr_rdy;
wire         rf_wr_vld;
wire   [2:0] slcg_op_en;
wire [514:0] wr_req_pd;
wire         wr_req_rdy;
wire         wr_req_type;
wire         wr_req_vld;
wire         wr_rsp_complete;

NV_NVDLA_RUBIK_regfile u_regfile (
   .nvdla_core_clk                (nvdla_core_clk)
  ,.nvdla_core_rstn               (nvdla_core_rstn)
  ,.csb2rbk_req_pd                (csb2rbk_req_pd[62:0])
  ,.csb2rbk_req_pvld              (csb2rbk_req_pvld)
  ,.dp2reg_d0_rd_stall_cnt        (dp2reg_d0_rd_stall_cnt[31:0])
  ,.dp2reg_d0_wr_stall_cnt        (dp2reg_d0_wr_stall_cnt[31:0])
  ,.dp2reg_d1_rd_stall_cnt        (dp2reg_d1_rd_stall_cnt[31:0])
  ,.dp2reg_d1_wr_stall_cnt        (dp2reg_d1_wr_stall_cnt[31:0])
  ,.dp2reg_done                   (dp2reg_done)
  ,.csb2rbk_req_prdy              (csb2rbk_req_prdy)
  ,.dp2reg_consumer               (dp2reg_consumer)
  ,.rbk2csb_resp_pd               (rbk2csb_resp_pd[33:0])
  ,.rbk2csb_resp_valid            (rbk2csb_resp_valid)
  ,.reg2dp_contract_stride_0      (reg2dp_contract_stride_0[26:0])
  ,.reg2dp_contract_stride_1      (reg2dp_contract_stride_1[26:0])
  ,.reg2dp_dain_addr_high         (reg2dp_dain_addr_high[31:0])
  ,.reg2dp_dain_addr_low          (reg2dp_dain_addr_low[26:0])
  ,.reg2dp_dain_line_stride       (reg2dp_dain_line_stride[26:0])
  ,.reg2dp_dain_planar_stride     (reg2dp_dain_planar_stride[26:0])
  ,.reg2dp_dain_surf_stride       (reg2dp_dain_surf_stride[26:0])
  ,.reg2dp_daout_addr_high        (reg2dp_daout_addr_high[31:0])
  ,.reg2dp_daout_addr_low         (reg2dp_daout_addr_low[26:0])
  ,.reg2dp_daout_line_stride      (reg2dp_daout_line_stride[26:0])
  ,.reg2dp_daout_planar_stride    (reg2dp_daout_planar_stride[26:0])
  ,.reg2dp_daout_surf_stride      (reg2dp_daout_surf_stride[26:0])
  ,.reg2dp_datain_channel         (reg2dp_datain_channel[12:0])
  ,.reg2dp_datain_height          (reg2dp_datain_height[12:0])
  ,.reg2dp_datain_ram_type        (reg2dp_datain_ram_type)
  ,.reg2dp_datain_width           (reg2dp_datain_width[12:0])
  ,.reg2dp_dataout_channel        (reg2dp_dataout_channel[12:0])
  ,.reg2dp_dataout_ram_type       (reg2dp_dataout_ram_type)
  ,.reg2dp_deconv_x_stride        (reg2dp_deconv_x_stride[4:0])
  ,.reg2dp_deconv_y_stride        (reg2dp_deconv_y_stride[4:0])
  ,.reg2dp_in_precision           (reg2dp_in_precision[1:0])
  ,.reg2dp_op_en                  (reg2dp_op_en)
  ,.reg2dp_perf_en                (reg2dp_perf_en)
  ,.reg2dp_rubik_mode             (reg2dp_rubik_mode[1:0])
  ,.slcg_op_en                    (slcg_op_en[2:0])
  );

NV_NVDLA_RUBIK_intr u_intr (
   .nvdla_core_clk                (nvdla_core_clk)
  ,.nvdla_core_rstn               (nvdla_core_rstn)
  ,.dp2reg_consumer               (dp2reg_consumer)
  ,.dp2reg_done                   (dp2reg_done)
  ,.pwrbus_ram_pd                 (pwrbus_ram_pd[31:0])
  ,.reg2dp_op_en                  (reg2dp_op_en)
  ,.wr_rsp_complete               (wr_rsp_complete)
  ,.rubik2glb_done_intr_pd        (rubik2glb_done_intr_pd[1:0])
  );

NV_NVDLA_RUBIK_dma u_dma (
   .nvdla_core_clk                (nvdla_core_clk)
  ,.nvdla_core_rstn               (nvdla_core_rstn)
  ,.cvif2rbk_rd_rsp_pd            (cvif2rbk_rd_rsp_pd[513:0])
  ,.cvif2rbk_rd_rsp_valid         (cvif2rbk_rd_rsp_valid)
  ,.cvif2rbk_wr_rsp_complete      (cvif2rbk_wr_rsp_complete)
  ,.mcif2rbk_rd_rsp_pd            (mcif2rbk_rd_rsp_pd[513:0])
  ,.mcif2rbk_rd_rsp_valid         (mcif2rbk_rd_rsp_valid)
  ,.mcif2rbk_wr_rsp_complete      (mcif2rbk_wr_rsp_complete)
  ,.rbk2cvif_rd_req_ready         (rbk2cvif_rd_req_ready)
  ,.rbk2cvif_wr_req_ready         (rbk2cvif_wr_req_ready)
  ,.rbk2mcif_rd_req_ready         (rbk2mcif_rd_req_ready)
  ,.rbk2mcif_wr_req_ready         (rbk2mcif_wr_req_ready)
  ,.rd_cdt_lat_fifo_pop           (rd_cdt_lat_fifo_pop)
  ,.rd_req_pd                     (rd_req_pd[78:0])
  ,.rd_req_type                   (rd_req_type)
  ,.rd_req_vld                    (rd_req_vld)
  ,.rd_rsp_rdy                    (rd_rsp_rdy)
  ,.wr_req_pd                     (wr_req_pd[514:0])
  ,.wr_req_type                   (wr_req_type)
  ,.wr_req_vld                    (wr_req_vld)
  ,.cvif2rbk_rd_rsp_ready         (cvif2rbk_rd_rsp_ready)
  ,.mcif2rbk_rd_rsp_ready         (mcif2rbk_rd_rsp_ready)
  ,.rbk2cvif_rd_cdt_lat_fifo_pop  (rbk2cvif_rd_cdt_lat_fifo_pop)
  ,.rbk2cvif_rd_req_pd            (rbk2cvif_rd_req_pd[78:0])
  ,.rbk2cvif_rd_req_valid         (rbk2cvif_rd_req_valid)
  ,.rbk2cvif_wr_req_pd            (rbk2cvif_wr_req_pd[514:0])
  ,.rbk2cvif_wr_req_valid         (rbk2cvif_wr_req_valid)
  ,.rbk2mcif_rd_cdt_lat_fifo_pop  (rbk2mcif_rd_cdt_lat_fifo_pop)
  ,.rbk2mcif_rd_req_pd            (rbk2mcif_rd_req_pd[78:0])
  ,.rbk2mcif_rd_req_valid         (rbk2mcif_rd_req_valid)
  ,.rbk2mcif_wr_req_pd            (rbk2mcif_wr_req_pd[514:0])
  ,.rbk2mcif_wr_req_valid         (rbk2mcif_wr_req_valid)
  ,.rd_req_rdy                    (rd_req_rdy)
  ,.rd_rsp_pd                     (rd_rsp_pd[513:0])
  ,.rd_rsp_vld                    (rd_rsp_vld)
  ,.wr_req_rdy                    (wr_req_rdy)
  ,.wr_rsp_complete               (wr_rsp_complete)
  );

NV_NVDLA_RUBIK_seq_gen u_seq_gen (
   .nvdla_core_clk                (nvdla_op_gated_clk_0)
  ,.nvdla_core_rstn               (nvdla_core_rstn)
  ,.dp2reg_consumer               (dp2reg_consumer)
  ,.reg2dp_perf_en                (reg2dp_perf_en)
  ,.dp2reg_d0_rd_stall_cnt        (dp2reg_d0_rd_stall_cnt[31:0])
  ,.dp2reg_d1_rd_stall_cnt        (dp2reg_d1_rd_stall_cnt[31:0])
  ,.reg2dp_op_en                  (reg2dp_op_en)
  ,.reg2dp_datain_ram_type        (reg2dp_datain_ram_type)
  ,.reg2dp_rubik_mode             (reg2dp_rubik_mode[1:0])
  ,.reg2dp_in_precision           (reg2dp_in_precision[1:0])
  ,.reg2dp_dain_addr_high         (reg2dp_dain_addr_high[31:0])
  ,.reg2dp_dain_addr_low          (reg2dp_dain_addr_low[26:0])
  ,.reg2dp_datain_channel         (reg2dp_datain_channel[12:0])
  ,.reg2dp_datain_height          (reg2dp_datain_height[12:0])
  ,.reg2dp_datain_width           (reg2dp_datain_width[12:0])
  ,.reg2dp_deconv_x_stride        (reg2dp_deconv_x_stride[4:0])
  ,.reg2dp_deconv_y_stride        (reg2dp_deconv_y_stride[4:0])
  ,.reg2dp_dain_line_stride       (reg2dp_dain_line_stride[26:0])
  ,.reg2dp_dain_planar_stride     (reg2dp_dain_planar_stride[26:0])
  ,.reg2dp_dain_surf_stride       (reg2dp_dain_surf_stride[26:0])
  ,.reg2dp_contract_stride_0      (reg2dp_contract_stride_0[26:0])
  ,.reg2dp_contract_stride_1      (reg2dp_contract_stride_1[26:0])
  ,.reg2dp_daout_addr_high        (reg2dp_daout_addr_high[31:0])
  ,.reg2dp_daout_addr_low         (reg2dp_daout_addr_low[26:0])
  ,.reg2dp_daout_line_stride      (reg2dp_daout_line_stride[26:0])
  ,.reg2dp_daout_planar_stride    (reg2dp_daout_planar_stride[26:0])
  ,.reg2dp_daout_surf_stride      (reg2dp_daout_surf_stride[26:0])
  ,.reg2dp_dataout_channel        (reg2dp_dataout_channel[12:0])
  ,.dp2reg_done                   (dp2reg_done)
  ,.rd_req_type                   (rd_req_type)
  ,.rd_req_vld                    (rd_req_vld)
  ,.rd_req_rdy                    (rd_req_rdy)
  ,.rd_req_pd                     (rd_req_pd[78:0])
  ,.rf_wr_cmd_vld                 (rf_wr_cmd_vld)
  ,.rf_wr_cmd_rdy                 (rf_wr_cmd_rdy)
  ,.rf_wr_cmd_pd                  (rf_wr_cmd_pd[10:0])
  ,.rf_rd_cmd_vld                 (rf_rd_cmd_vld)
  ,.rf_rd_cmd_rdy                 (rf_rd_cmd_rdy)
  ,.rf_rd_cmd_pd                  (rf_rd_cmd_pd[11:0])
  ,.dma_wr_cmd_vld                (dma_wr_cmd_vld)
  ,.dma_wr_cmd_rdy                (dma_wr_cmd_rdy)
  ,.dma_wr_cmd_pd                 (dma_wr_cmd_pd[77:0])
  ,.contract_lit_dx               (contract_lit_dx)
  ,.inwidth                       (inwidth[13:0])
  );

NV_NVDLA_RUBIK_wr_req u_wr_req (
   .nvdla_core_clk                (nvdla_op_gated_clk_0)
  ,.nvdla_core_rstn               (nvdla_core_rstn)
  ,.dp2reg_consumer               (dp2reg_consumer)
  ,.pwrbus_ram_pd                 (pwrbus_ram_pd[31:0])
  ,.reg2dp_dataout_ram_type       (reg2dp_dataout_ram_type)
  ,.reg2dp_perf_en                (reg2dp_perf_en)
  ,.dp2reg_d0_wr_stall_cnt        (dp2reg_d0_wr_stall_cnt[31:0])
  ,.dp2reg_d1_wr_stall_cnt        (dp2reg_d1_wr_stall_cnt[31:0])
  ,.wr_req_type                   (wr_req_type)
  ,.wr_req_vld                    (wr_req_vld)
  ,.wr_req_pd                     (wr_req_pd[514:0])
  ,.wr_req_rdy                    (wr_req_rdy)
  ,.dma_wr_cmd_vld                (dma_wr_cmd_vld)
  ,.dma_wr_cmd_pd                 (dma_wr_cmd_pd[77:0])
  ,.dma_wr_cmd_rdy                (dma_wr_cmd_rdy)
  ,.dma_wr_data_vld               (dma_wr_data_vld)
  ,.dma_wr_data_pd                (dma_wr_data_pd[513:0])
  ,.dma_wr_data_rdy               (dma_wr_data_rdy)
  ,.dp2reg_done                   (dp2reg_done)
  );

NV_NVDLA_RUBIK_rf_ctrl u_rf_ctrl (
   .nvdla_core_clk                (nvdla_op_gated_clk_0)
  ,.nvdla_core_rstn               (nvdla_core_rstn)
  ,.contract_lit_dx               (contract_lit_dx)
  ,.inwidth                       (inwidth[13:0])
  ,.pwrbus_ram_pd                 (pwrbus_ram_pd[31:0])
  ,.rf_wr_cmd_vld                 (rf_wr_cmd_vld)
  ,.rf_wr_cmd_pd                  (rf_wr_cmd_pd[10:0])
  ,.rf_wr_cmd_rdy                 (rf_wr_cmd_rdy)
  ,.rf_rd_cmd_vld                 (rf_rd_cmd_vld)
  ,.rf_rd_cmd_pd                  (rf_rd_cmd_pd[11:0])
  ,.rf_rd_cmd_rdy                 (rf_rd_cmd_rdy)
  ,.data_fifo_vld                 (data_fifo_vld)
  ,.data_fifo_pd                  (data_fifo_pd[511:0])
  ,.data_fifo_rdy                 (data_fifo_rdy)
  ,.rf_wr_vld                     (rf_wr_vld)
  ,.rf_wr_done                    (rf_wr_done)
  ,.rf_wr_addr                    (rf_wr_addr[4:0])
  ,.rf_wr_data                    (rf_wr_data[511:0])
  ,.rf_wr_rdy                     (rf_wr_rdy)
  ,.rf_rd_vld                     (rf_rd_vld)
  ,.rf_rd_done                    (rf_rd_done)
  ,.rf_rd_mask                    (rf_rd_mask[11:0])
  ,.rf_rd_addr                    (rf_rd_addr[4:0])
  ,.rf_rd_rdy                     (rf_rd_rdy)
  ,.reg2dp_rubik_mode             (reg2dp_rubik_mode[1:0])
  ,.reg2dp_in_precision           (reg2dp_in_precision[1:0])
  );

NV_NVDLA_RUBIK_dr2drc u_dr2drc (
   .nvdla_core_clk                (nvdla_op_gated_clk_1)
  ,.nvdla_core_rstn               (nvdla_core_rstn)
  ,.pwrbus_ram_pd                 (pwrbus_ram_pd[31:0])
  ,.rd_rsp_vld                    (rd_rsp_vld)
  ,.rd_rsp_pd                     (rd_rsp_pd[513:0])
  ,.rd_rsp_rdy                    (rd_rsp_rdy)
  ,.rd_cdt_lat_fifo_pop           (rd_cdt_lat_fifo_pop)
  ,.data_fifo_vld                 (data_fifo_vld)
  ,.data_fifo_pd                  (data_fifo_pd[511:0])
  ,.data_fifo_rdy                 (data_fifo_rdy)
  );

NV_NVDLA_RUBIK_rf_core u_rf_core (
   .nvdla_core_clk                (nvdla_op_gated_clk_2)
  ,.nvdla_core_rstn               (nvdla_core_rstn)
  ,.pwrbus_ram_pd                 (pwrbus_ram_pd[31:0])
  ,.rf_wr_vld                     (rf_wr_vld)
  ,.rf_wr_done                    (rf_wr_done)
  ,.rf_wr_addr                    (rf_wr_addr[4:0])
  ,.rf_wr_data                    (rf_wr_data[511:0])
  ,.rf_wr_rdy                     (rf_wr_rdy)
  ,.rf_rd_vld                     (rf_rd_vld)
  ,.rf_rd_done                    (rf_rd_done)
  ,.rf_rd_addr                    (rf_rd_addr[4:0])
  ,.rf_rd_mask                    (rf_rd_mask[11:0])
  ,.rf_rd_rdy                     (rf_rd_rdy)
  ,.dma_wr_data_vld               (dma_wr_data_vld)
  ,.dma_wr_data_pd                (dma_wr_data_pd[513:0])
  ,.dma_wr_data_rdy               (dma_wr_data_rdy)
  ,.reg2dp_rubik_mode             (reg2dp_rubik_mode[1:0])
  ,.reg2dp_in_precision           (reg2dp_in_precision[1:0])
  );


NV_NVDLA_RUBIK_slcg u_slcg_op_0 (
   .dla_clk_ovr_on_sync           (dla_clk_ovr_on_sync)
  ,.enable                        (slcg_op_en[0])
  ,.global_clk_ovr_on_sync        (global_clk_ovr_on_sync)
  ,.nvdla_core_clk                (nvdla_core_clk)
  ,.nvdla_core_rstn               (nvdla_core_rstn)
  ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating)
  ,.nvdla_core_gated_clk          (nvdla_op_gated_clk_0)
  );

NV_NVDLA_RUBIK_slcg u_slcg_op_1 (
   .dla_clk_ovr_on_sync           (dla_clk_ovr_on_sync)
  ,.enable                        (slcg_op_en[1])
  ,.global_clk_ovr_on_sync        (global_clk_ovr_on_sync)
  ,.nvdla_core_clk                (nvdla_core_clk)
  ,.nvdla_core_rstn               (nvdla_core_rstn)
  ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating)
  ,.nvdla_core_gated_clk          (nvdla_op_gated_clk_1)
  );

NV_NVDLA_RUBIK_slcg u_slcg_op_2 (
   .dla_clk_ovr_on_sync           (dla_clk_ovr_on_sync)
  ,.enable                        (slcg_op_en[2])
  ,.global_clk_ovr_on_sync        (global_clk_ovr_on_sync)
  ,.nvdla_core_clk                (nvdla_core_clk)
  ,.nvdla_core_rstn               (nvdla_core_rstn)
  ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating)
  ,.nvdla_core_gated_clk          (nvdla_op_gated_clk_2)
  );
































endmodule
module NV_NVDLA_rubik (
   nvdla_core_clk
  ,nvdla_core_rstn
  ,csb2rbk_req_pvld
  ,csb2rbk_req_prdy
  ,csb2rbk_req_pd
  ,rbk2csb_resp_valid
  ,rbk2csb_resp_pd
  ,pwrbus_ram_pd
  ,rbk2mcif_rd_req_valid
  ,rbk2mcif_rd_req_ready
  ,rbk2mcif_rd_req_pd
  ,rbk2cvif_rd_req_valid
  ,rbk2cvif_rd_req_ready
  ,rbk2cvif_rd_req_pd
  ,mcif2rbk_rd_rsp_valid
  ,mcif2rbk_rd_rsp_ready
  ,mcif2rbk_rd_rsp_pd
  ,cvif2rbk_rd_rsp_valid
  ,cvif2rbk_rd_rsp_ready
  ,cvif2rbk_rd_rsp_pd
  ,rbk2mcif_wr_req_valid
  ,rbk2mcif_wr_req_ready
  ,rbk2mcif_wr_req_pd
  ,mcif2rbk_wr_rsp_complete
  ,rbk2cvif_wr_req_valid
  ,rbk2cvif_wr_req_ready
  ,rbk2cvif_wr_req_pd
  ,cvif2rbk_wr_rsp_complete
  ,rbk2mcif_rd_cdt_lat_fifo_pop
  ,rbk2cvif_rd_cdt_lat_fifo_pop
  ,rubik2glb_done_intr_pd
  ,dla_clk_ovr_on_sync
  ,global_clk_ovr_on_sync
  ,tmc2slcg_disable_clock_gating
  );






input  nvdla_core_clk;
input  nvdla_core_rstn;

input         csb2rbk_req_pvld;
output        csb2rbk_req_prdy;
input  [62:0] csb2rbk_req_pd;

output        rbk2csb_resp_valid;
output [33:0] rbk2csb_resp_pd;

input [31:0] pwrbus_ram_pd;

output        rbk2mcif_rd_req_valid;
input         rbk2mcif_rd_req_ready;
output [78:0] rbk2mcif_rd_req_pd;

output        rbk2cvif_rd_req_valid;
input         rbk2cvif_rd_req_ready;
output [78:0] rbk2cvif_rd_req_pd;

input          mcif2rbk_rd_rsp_valid;
output         mcif2rbk_rd_rsp_ready;
input  [513:0] mcif2rbk_rd_rsp_pd;

input          cvif2rbk_rd_rsp_valid;
output         cvif2rbk_rd_rsp_ready;
input  [513:0] cvif2rbk_rd_rsp_pd;

output         rbk2mcif_wr_req_valid;
input          rbk2mcif_wr_req_ready;
output [514:0] rbk2mcif_wr_req_pd;

input  mcif2rbk_wr_rsp_complete;

output         rbk2cvif_wr_req_valid;
input          rbk2cvif_wr_req_ready;
output [514:0] rbk2cvif_wr_req_pd;

input  cvif2rbk_wr_rsp_complete;

output  rbk2mcif_rd_cdt_lat_fifo_pop;

output  rbk2cvif_rd_cdt_lat_fifo_pop;

output [1:0] rubik2glb_done_intr_pd;

input   dla_clk_ovr_on_sync;
input   global_clk_ovr_on_sync;
input   tmc2slcg_disable_clock_gating;



wire         contract_lit_dx;
wire [511:0] data_fifo_pd;
wire         data_fifo_rdy;
wire         data_fifo_vld;
wire  [77:0] dma_wr_cmd_pd;
wire         dma_wr_cmd_rdy;
wire         dma_wr_cmd_vld;
wire [513:0] dma_wr_data_pd;
wire         dma_wr_data_rdy;
wire         dma_wr_data_vld;
wire         dp2reg_consumer;
wire  [31:0] dp2reg_d0_rd_stall_cnt;
wire  [31:0] dp2reg_d0_wr_stall_cnt;
wire  [31:0] dp2reg_d1_rd_stall_cnt;
wire  [31:0] dp2reg_d1_wr_stall_cnt;
wire         dp2reg_done;
wire  [13:0] inwidth;
wire         nvdla_op_gated_clk_0;
wire         nvdla_op_gated_clk_1;
wire         nvdla_op_gated_clk_2;
wire         rd_cdt_lat_fifo_pop;
wire  [78:0] rd_req_pd;
wire         rd_req_rdy;
wire         rd_req_type;
wire         rd_req_vld;
wire [513:0] rd_rsp_pd;
wire         rd_rsp_rdy;
wire         rd_rsp_vld;
wire  [26:0] reg2dp_contract_stride_0;
wire  [26:0] reg2dp_contract_stride_1;
wire  [31:0] reg2dp_dain_addr_high;
wire  [26:0] reg2dp_dain_addr_low;
wire  [26:0] reg2dp_dain_line_stride;
wire  [26:0] reg2dp_dain_planar_stride;
wire  [26:0] reg2dp_dain_surf_stride;
wire  [31:0] reg2dp_daout_addr_high;
wire  [26:0] reg2dp_daout_addr_low;
wire  [26:0] reg2dp_daout_line_stride;
wire  [26:0] reg2dp_daout_planar_stride;
wire  [26:0] reg2dp_daout_surf_stride;
wire  [12:0] reg2dp_datain_channel;
wire  [12:0] reg2dp_datain_height;
wire         reg2dp_datain_ram_type;
wire  [12:0] reg2dp_datain_width;
wire  [12:0] reg2dp_dataout_channel;
wire         reg2dp_dataout_ram_type;
wire   [4:0] reg2dp_deconv_x_stride;
wire   [4:0] reg2dp_deconv_y_stride;
wire   [1:0] reg2dp_in_precision;
wire         reg2dp_op_en;
wire         reg2dp_perf_en;
wire   [1:0] reg2dp_rubik_mode;
wire   [4:0] rf_rd_addr;
wire  [11:0] rf_rd_cmd_pd;
wire         rf_rd_cmd_rdy;
wire         rf_rd_cmd_vld;
wire         rf_rd_done;
wire  [11:0] rf_rd_mask;
wire         rf_rd_rdy;
wire         rf_rd_vld;
wire   [4:0] rf_wr_addr;
wire  [10:0] rf_wr_cmd_pd;
wire         rf_wr_cmd_rdy;
wire         rf_wr_cmd_vld;
wire [511:0] rf_wr_data;
wire         rf_wr_done;
wire         rf_wr_rdy;
wire         rf_wr_vld;
wire   [2:0] slcg_op_en;
wire [514:0] wr_req_pd;
wire         wr_req_rdy;
wire         wr_req_type;
wire         wr_req_vld;
wire         wr_rsp_complete;

NV_NVDLA_RUBIK_regfile u_regfile (
   .nvdla_core_clk                (nvdla_core_clk)
  ,.nvdla_core_rstn               (nvdla_core_rstn)
  ,.csb2rbk_req_pd                (csb2rbk_req_pd[62:0])
  ,.csb2rbk_req_pvld              (csb2rbk_req_pvld)
  ,.dp2reg_d0_rd_stall_cnt        (dp2reg_d0_rd_stall_cnt[31:0])
  ,.dp2reg_d0_wr_stall_cnt        (dp2reg_d0_wr_stall_cnt[31:0])
  ,.dp2reg_d1_rd_stall_cnt        (dp2reg_d1_rd_stall_cnt[31:0])
  ,.dp2reg_d1_wr_stall_cnt        (dp2reg_d1_wr_stall_cnt[31:0])
  ,.dp2reg_done                   (dp2reg_done)
  ,.csb2rbk_req_prdy              (csb2rbk_req_prdy)
  ,.dp2reg_consumer               (dp2reg_consumer)
  ,.rbk2csb_resp_pd               (rbk2csb_resp_pd[33:0])
  ,.rbk2csb_resp_valid            (rbk2csb_resp_valid)
  ,.reg2dp_contract_stride_0      (reg2dp_contract_stride_0[26:0])
  ,.reg2dp_contract_stride_1      (reg2dp_contract_stride_1[26:0])
  ,.reg2dp_dain_addr_high         (reg2dp_dain_addr_high[31:0])
  ,.reg2dp_dain_addr_low          (reg2dp_dain_addr_low[26:0])
  ,.reg2dp_dain_line_stride       (reg2dp_dain_line_stride[26:0])
  ,.reg2dp_dain_planar_stride     (reg2dp_dain_planar_stride[26:0])
  ,.reg2dp_dain_surf_stride       (reg2dp_dain_surf_stride[26:0])
  ,.reg2dp_daout_addr_high        (reg2dp_daout_addr_high[31:0])
  ,.reg2dp_daout_addr_low         (reg2dp_daout_addr_low[26:0])
  ,.reg2dp_daout_line_stride      (reg2dp_daout_line_stride[26:0])
  ,.reg2dp_daout_planar_stride    (reg2dp_daout_planar_stride[26:0])
  ,.reg2dp_daout_surf_stride      (reg2dp_daout_surf_stride[26:0])
  ,.reg2dp_datain_channel         (reg2dp_datain_channel[12:0])
  ,.reg2dp_datain_height          (reg2dp_datain_height[12:0])
  ,.reg2dp_datain_ram_type        (reg2dp_datain_ram_type)
  ,.reg2dp_datain_width           (reg2dp_datain_width[12:0])
  ,.reg2dp_dataout_channel        (reg2dp_dataout_channel[12:0])
  ,.reg2dp_dataout_ram_type       (reg2dp_dataout_ram_type)
  ,.reg2dp_deconv_x_stride        (reg2dp_deconv_x_stride[4:0])
  ,.reg2dp_deconv_y_stride        (reg2dp_deconv_y_stride[4:0])
  ,.reg2dp_in_precision           (reg2dp_in_precision[1:0])
  ,.reg2dp_op_en                  (reg2dp_op_en)
  ,.reg2dp_perf_en                (reg2dp_perf_en)
  ,.reg2dp_rubik_mode             (reg2dp_rubik_mode[1:0])
  ,.slcg_op_en                    (slcg_op_en[2:0])
  );

NV_NVDLA_RUBIK_intr u_intr (
   .nvdla_core_clk                (nvdla_core_clk)
  ,.nvdla_core_rstn               (nvdla_core_rstn)
  ,.dp2reg_consumer               (dp2reg_consumer)
  ,.dp2reg_done                   (dp2reg_done)
  ,.pwrbus_ram_pd                 (pwrbus_ram_pd[31:0])
  ,.reg2dp_op_en                  (reg2dp_op_en)
  ,.wr_rsp_complete               (wr_rsp_complete)
  ,.rubik2glb_done_intr_pd        (rubik2glb_done_intr_pd[1:0])
  );

NV_NVDLA_RUBIK_dma u_dma (
   .nvdla_core_clk                (nvdla_core_clk)
  ,.nvdla_core_rstn               (nvdla_core_rstn)
  ,.cvif2rbk_rd_rsp_pd            (cvif2rbk_rd_rsp_pd[513:0])
  ,.cvif2rbk_rd_rsp_valid         (cvif2rbk_rd_rsp_valid)
  ,.cvif2rbk_wr_rsp_complete      (cvif2rbk_wr_rsp_complete)
  ,.mcif2rbk_rd_rsp_pd            (mcif2rbk_rd_rsp_pd[513:0])
  ,.mcif2rbk_rd_rsp_valid         (mcif2rbk_rd_rsp_valid)
  ,.mcif2rbk_wr_rsp_complete      (mcif2rbk_wr_rsp_complete)
  ,.rbk2cvif_rd_req_ready         (rbk2cvif_rd_req_ready)
  ,.rbk2cvif_wr_req_ready         (rbk2cvif_wr_req_ready)
  ,.rbk2mcif_rd_req_ready         (rbk2mcif_rd_req_ready)
  ,.rbk2mcif_wr_req_ready         (rbk2mcif_wr_req_ready)
  ,.rd_cdt_lat_fifo_pop           (rd_cdt_lat_fifo_pop)
  ,.rd_req_pd                     (rd_req_pd[78:0])
  ,.rd_req_type                   (rd_req_type)
  ,.rd_req_vld                    (rd_req_vld)
  ,.rd_rsp_rdy                    (rd_rsp_rdy)
  ,.wr_req_pd                     (wr_req_pd[514:0])
  ,.wr_req_type                   (wr_req_type)
  ,.wr_req_vld                    (wr_req_vld)
  ,.cvif2rbk_rd_rsp_ready         (cvif2rbk_rd_rsp_ready)
  ,.mcif2rbk_rd_rsp_ready         (mcif2rbk_rd_rsp_ready)
  ,.rbk2cvif_rd_cdt_lat_fifo_pop  (rbk2cvif_rd_cdt_lat_fifo_pop)
  ,.rbk2cvif_rd_req_pd            (rbk2cvif_rd_req_pd[78:0])
  ,.rbk2cvif_rd_req_valid         (rbk2cvif_rd_req_valid)
  ,.rbk2cvif_wr_req_pd            (rbk2cvif_wr_req_pd[514:0])
  ,.rbk2cvif_wr_req_valid         (rbk2cvif_wr_req_valid)
  ,.rbk2mcif_rd_cdt_lat_fifo_pop  (rbk2mcif_rd_cdt_lat_fifo_pop)
  ,.rbk2mcif_rd_req_pd            (rbk2mcif_rd_req_pd[78:0])
  ,.rbk2mcif_rd_req_valid         (rbk2mcif_rd_req_valid)
  ,.rbk2mcif_wr_req_pd            (rbk2mcif_wr_req_pd[514:0])
  ,.rbk2mcif_wr_req_valid         (rbk2mcif_wr_req_valid)
  ,.rd_req_rdy                    (rd_req_rdy)
  ,.rd_rsp_pd                     (rd_rsp_pd[513:0])
  ,.rd_rsp_vld                    (rd_rsp_vld)
  ,.wr_req_rdy                    (wr_req_rdy)
  ,.wr_rsp_complete               (wr_rsp_complete)
  );

NV_NVDLA_RUBIK_seq_gen u_seq_gen (
   .nvdla_core_clk                (nvdla_op_gated_clk_0)
  ,.nvdla_core_rstn               (nvdla_core_rstn)
  ,.dp2reg_consumer               (dp2reg_consumer)
  ,.reg2dp_perf_en                (reg2dp_perf_en)
  ,.dp2reg_d0_rd_stall_cnt        (dp2reg_d0_rd_stall_cnt[31:0])
  ,.dp2reg_d1_rd_stall_cnt        (dp2reg_d1_rd_stall_cnt[31:0])
  ,.reg2dp_op_en                  (reg2dp_op_en)
  ,.reg2dp_datain_ram_type        (reg2dp_datain_ram_type)
  ,.reg2dp_rubik_mode             (reg2dp_rubik_mode[1:0])
  ,.reg2dp_in_precision           (reg2dp_in_precision[1:0])
  ,.reg2dp_dain_addr_high         (reg2dp_dain_addr_high[31:0])
  ,.reg2dp_dain_addr_low          (reg2dp_dain_addr_low[26:0])
  ,.reg2dp_datain_channel         (reg2dp_datain_channel[12:0])
  ,.reg2dp_datain_height          (reg2dp_datain_height[12:0])
  ,.reg2dp_datain_width           (reg2dp_datain_width[12:0])
  ,.reg2dp_deconv_x_stride        (reg2dp_deconv_x_stride[4:0])
  ,.reg2dp_deconv_y_stride        (reg2dp_deconv_y_stride[4:0])
  ,.reg2dp_dain_line_stride       (reg2dp_dain_line_stride[26:0])
  ,.reg2dp_dain_planar_stride     (reg2dp_dain_planar_stride[26:0])
  ,.reg2dp_dain_surf_stride       (reg2dp_dain_surf_stride[26:0])
  ,.reg2dp_contract_stride_0      (reg2dp_contract_stride_0[26:0])
  ,.reg2dp_contract_stride_1      (reg2dp_contract_stride_1[26:0])
  ,.reg2dp_daout_addr_high        (reg2dp_daout_addr_high[31:0])
  ,.reg2dp_daout_addr_low         (reg2dp_daout_addr_low[26:0])
  ,.reg2dp_daout_line_stride      (reg2dp_daout_line_stride[26:0])
  ,.reg2dp_daout_planar_stride    (reg2dp_daout_planar_stride[26:0])
  ,.reg2dp_daout_surf_stride      (reg2dp_daout_surf_stride[26:0])
  ,.reg2dp_dataout_channel        (reg2dp_dataout_channel[12:0])
  ,.dp2reg_done                   (dp2reg_done)
  ,.rd_req_type                   (rd_req_type)
  ,.rd_req_vld                    (rd_req_vld)
  ,.rd_req_rdy                    (rd_req_rdy)
  ,.rd_req_pd                     (rd_req_pd[78:0])
  ,.rf_wr_cmd_vld                 (rf_wr_cmd_vld)
  ,.rf_wr_cmd_rdy                 (rf_wr_cmd_rdy)
  ,.rf_wr_cmd_pd                  (rf_wr_cmd_pd[10:0])
  ,.rf_rd_cmd_vld                 (rf_rd_cmd_vld)
  ,.rf_rd_cmd_rdy                 (rf_rd_cmd_rdy)
  ,.rf_rd_cmd_pd                  (rf_rd_cmd_pd[11:0])
  ,.dma_wr_cmd_vld                (dma_wr_cmd_vld)
  ,.dma_wr_cmd_rdy                (dma_wr_cmd_rdy)
  ,.dma_wr_cmd_pd                 (dma_wr_cmd_pd[77:0])
  ,.contract_lit_dx               (contract_lit_dx)
  ,.inwidth                       (inwidth[13:0])
  );

NV_NVDLA_RUBIK_wr_req u_wr_req (
   .nvdla_core_clk                (nvdla_op_gated_clk_0)
  ,.nvdla_core_rstn               (nvdla_core_rstn)
  ,.dp2reg_consumer               (dp2reg_consumer)
  ,.pwrbus_ram_pd                 (pwrbus_ram_pd[31:0])
  ,.reg2dp_dataout_ram_type       (reg2dp_dataout_ram_type)
  ,.reg2dp_perf_en                (reg2dp_perf_en)
  ,.dp2reg_d0_wr_stall_cnt        (dp2reg_d0_wr_stall_cnt[31:0])
  ,.dp2reg_d1_wr_stall_cnt        (dp2reg_d1_wr_stall_cnt[31:0])
  ,.wr_req_type                   (wr_req_type)
  ,.wr_req_vld                    (wr_req_vld)
  ,.wr_req_pd                     (wr_req_pd[514:0])
  ,.wr_req_rdy                    (wr_req_rdy)
  ,.dma_wr_cmd_vld                (dma_wr_cmd_vld)
  ,.dma_wr_cmd_pd                 (dma_wr_cmd_pd[77:0])
  ,.dma_wr_cmd_rdy                (dma_wr_cmd_rdy)
  ,.dma_wr_data_vld               (dma_wr_data_vld)
  ,.dma_wr_data_pd                (dma_wr_data_pd[513:0])
  ,.dma_wr_data_rdy               (dma_wr_data_rdy)
  ,.dp2reg_done                   (dp2reg_done)
  );

NV_NVDLA_RUBIK_rf_ctrl u_rf_ctrl (
   .nvdla_core_clk                (nvdla_op_gated_clk_0)
  ,.nvdla_core_rstn               (nvdla_core_rstn)
  ,.contract_lit_dx               (contract_lit_dx)
  ,.inwidth                       (inwidth[13:0])
  ,.pwrbus_ram_pd                 (pwrbus_ram_pd[31:0])
  ,.rf_wr_cmd_vld                 (rf_wr_cmd_vld)
  ,.rf_wr_cmd_pd                  (rf_wr_cmd_pd[10:0])
  ,.rf_wr_cmd_rdy                 (rf_wr_cmd_rdy)
  ,.rf_rd_cmd_vld                 (rf_rd_cmd_vld)
  ,.rf_rd_cmd_pd                  (rf_rd_cmd_pd[11:0])
  ,.rf_rd_cmd_rdy                 (rf_rd_cmd_rdy)
  ,.data_fifo_vld                 (data_fifo_vld)
  ,.data_fifo_pd                  (data_fifo_pd[511:0])
  ,.data_fifo_rdy                 (data_fifo_rdy)
  ,.rf_wr_vld                     (rf_wr_vld)
  ,.rf_wr_done                    (rf_wr_done)
  ,.rf_wr_addr                    (rf_wr_addr[4:0])
  ,.rf_wr_data                    (rf_wr_data[511:0])
  ,.rf_wr_rdy                     (rf_wr_rdy)
  ,.rf_rd_vld                     (rf_rd_vld)
  ,.rf_rd_done                    (rf_rd_done)
  ,.rf_rd_mask                    (rf_rd_mask[11:0])
  ,.rf_rd_addr                    (rf_rd_addr[4:0])
  ,.rf_rd_rdy                     (rf_rd_rdy)
  ,.reg2dp_rubik_mode             (reg2dp_rubik_mode[1:0])
  ,.reg2dp_in_precision           (reg2dp_in_precision[1:0])
  );

NV_NVDLA_RUBIK_dr2drc u_dr2drc (
   .nvdla_core_clk                (nvdla_op_gated_clk_1)
  ,.nvdla_core_rstn               (nvdla_core_rstn)
  ,.pwrbus_ram_pd                 (pwrbus_ram_pd[31:0])
  ,.rd_rsp_vld                    (rd_rsp_vld)
  ,.rd_rsp_pd                     (rd_rsp_pd[513:0])
  ,.rd_rsp_rdy                    (rd_rsp_rdy)
  ,.rd_cdt_lat_fifo_pop           (rd_cdt_lat_fifo_pop)
  ,.data_fifo_vld                 (data_fifo_vld)
  ,.data_fifo_pd                  (data_fifo_pd[511:0])
  ,.data_fifo_rdy                 (data_fifo_rdy)
  );

NV_NVDLA_RUBIK_rf_core u_rf_core (
   .nvdla_core_clk                (nvdla_op_gated_clk_2)
  ,.nvdla_core_rstn               (nvdla_core_rstn)
  ,.pwrbus_ram_pd                 (pwrbus_ram_pd[31:0])
  ,.rf_wr_vld                     (rf_wr_vld)
  ,.rf_wr_done                    (rf_wr_done)
  ,.rf_wr_addr                    (rf_wr_addr[4:0])
  ,.rf_wr_data                    (rf_wr_data[511:0])
  ,.rf_wr_rdy                     (rf_wr_rdy)
  ,.rf_rd_vld                     (rf_rd_vld)
  ,.rf_rd_done                    (rf_rd_done)
  ,.rf_rd_addr                    (rf_rd_addr[4:0])
  ,.rf_rd_mask                    (rf_rd_mask[11:0])
  ,.rf_rd_rdy                     (rf_rd_rdy)
  ,.dma_wr_data_vld               (dma_wr_data_vld)
  ,.dma_wr_data_pd                (dma_wr_data_pd[513:0])
  ,.dma_wr_data_rdy               (dma_wr_data_rdy)
  ,.reg2dp_rubik_mode             (reg2dp_rubik_mode[1:0])
  ,.reg2dp_in_precision           (reg2dp_in_precision[1:0])
  );


NV_NVDLA_RUBIK_slcg u_slcg_op_0 (
   .dla_clk_ovr_on_sync           (dla_clk_ovr_on_sync)
  ,.enable                        (slcg_op_en[0])
  ,.global_clk_ovr_on_sync        (global_clk_ovr_on_sync)
  ,.nvdla_core_clk                (nvdla_core_clk)
  ,.nvdla_core_rstn               (nvdla_core_rstn)
  ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating)
  ,.nvdla_core_gated_clk          (nvdla_op_gated_clk_0)
  );

NV_NVDLA_RUBIK_slcg u_slcg_op_1 (
   .dla_clk_ovr_on_sync           (dla_clk_ovr_on_sync)
  ,.enable                        (slcg_op_en[1])
  ,.global_clk_ovr_on_sync        (global_clk_ovr_on_sync)
  ,.nvdla_core_clk                (nvdla_core_clk)
  ,.nvdla_core_rstn               (nvdla_core_rstn)
  ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating)
  ,.nvdla_core_gated_clk          (nvdla_op_gated_clk_1)
  );

NV_NVDLA_RUBIK_slcg u_slcg_op_2 (
   .dla_clk_ovr_on_sync           (dla_clk_ovr_on_sync)
  ,.enable                        (slcg_op_en[2])
  ,.global_clk_ovr_on_sync        (global_clk_ovr_on_sync)
  ,.nvdla_core_clk                (nvdla_core_clk)
  ,.nvdla_core_rstn               (nvdla_core_rstn)
  ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating)
  ,.nvdla_core_gated_clk          (nvdla_op_gated_clk_2)
  );
































endmodule