data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/gen/gen_mult_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/gen/gen_mult_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #H_period;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/gen/gen_mult_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #H_period;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/gen/gen_mult_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #F_period;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/gen/gen_mult_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #F_period;\n        ^\n%Error: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/gen/gen_mult_tb.v:14: Cannot find file containing module: \'gen_mult\'\ngen_mult #(\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/gen,data/full_repos/permissive/503053625/gen_mult\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/gen,data/full_repos/permissive/503053625/gen_mult.v\n             data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/gen,data/full_repos/permissive/503053625/gen_mult.sv\n             gen_mult\n             gen_mult.v\n             gen_mult.sv\n             obj_dir/gen_mult\n             obj_dir/gen_mult.v\n             obj_dir/gen_mult.sv\n%Warning-WIDTH: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/gen/gen_mult_tb.v:32: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                                   : ... In instance gen_mult_tb\n        A = $random;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/503053625/fpga_projects/SPGD/src/tb/gen/gen_mult_tb.v:34: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                                   : ... In instance gen_mult_tb\n        B = $random;\n          ^\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module gen_mult_tb;
localparam NUM_SAMPS = 10;
localparam F_period=4;
localparam H_period=F_period/2;
localparam DATA_WIDTH = 64;
localparam  ON = 1'b1;
localparam  OFF = 1'b0;

reg  ADC_CLK = OFF;
reg	 [DATA_WIDTH	- 1	: 0] A = {DATA_WIDTH{1'b0}};
reg  [DATA_WIDTH 	- 1	: 0] B = {DATA_WIDTH{1'b0}};
wire [DATA_WIDTH*2	- 1	: 0] PRODUCT;

gen_mult #(
	.DATA_WIDTH(DATA_WIDTH)
) MUL0 (
	.a(A),
	.b(B),
	.p(PRODUCT)
);

always begin
    ADC_CLK = OFF;
    #H_period;
    ADC_CLK = ON;
    #H_period;
end
initial
begin
    repeat(NUM_SAMPS) begin
        #F_period;
        A = $random;
        #F_period;
        B = $random;
    end
    $finish;
end
endmodule
module gen_mult_tb;

localparam NUM_SAMPS = 10;
localparam F_period=4;
localparam H_period=F_period/2;
localparam DATA_WIDTH = 64;
localparam  ON = 1'b1;
localparam  OFF = 1'b0;

reg  ADC_CLK = OFF;
reg	 [DATA_WIDTH	- 1	: 0] A = {DATA_WIDTH{1'b0}};
reg  [DATA_WIDTH 	- 1	: 0] B = {DATA_WIDTH{1'b0}};
wire [DATA_WIDTH*2	- 1	: 0] PRODUCT;

gen_mult #(
	.DATA_WIDTH(DATA_WIDTH)
) MUL0 (
	.a(A),
	.b(B),
	.p(PRODUCT)
);

always begin
    ADC_CLK = OFF;
    #H_period;
    ADC_CLK = ON;
    #H_period;
end
initial
begin
    repeat(NUM_SAMPS) begin
        #F_period;
        A = $random;
        #F_period;
        B = $random;
    end
    $finish;
end
endmodule