data/full_repos/permissive/441359809/src/yosys/manual/PRESENTATION_ExAdv/macc_simple_test.v
data/verilator_xmls/5d47a064-178a-43c9-8643-fca1938a4623.xml
module test(a, b, c, d, y);
input [15:0] a, b;
input [31:0] c, d;
output [31:0] y;
assign y = a * b + c + d;
endmodule
module test(a, b, c, d, y);

input [15:0] a, b;
input [31:0] c, d;
output [31:0] y;
assign y = a * b + c + d;
endmodule