data/full_repos/permissive/508059792/alucontrol.v
1: b'%Warning-WIDTH: data/full_repos/permissive/508059792/alucontrol.v:54: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'bxxxx\' generates 4 bits.\n                                                                    : ... In instance alucontrol\n        default:AluCtrl=4\'bxxxx;\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module alucontrol(AluOp,FnField,AluCtrl);


input [3:0] AluOp;
input [5:0] FnField;


output reg [4:0] AluCtrl;


always@(AluOp or FnField)begin
    casex({AluOp,FnField})
    

        10'b1000_100100:AluCtrl=5'b00000;
        10'b1000_100101:AluCtrl=5'b00010;
        10'b1000_100110:AluCtrl=5'b00110;
        10'b1000_100111:AluCtrl=5'b11000;

        10'b1000_100000:AluCtrl=5'b00100;
        10'b1000_100010:AluCtrl=5'b01100;
        10'b1000_011000:AluCtrl=5'b01000;
        10'b1000_011010:AluCtrl=5'b01010;

        10'b1000_000000:AluCtrl=5'b10000;
        10'b1000_000010:AluCtrl=5'b10010;
        10'b1000_000011:AluCtrl=5'b10100;
        10'b1000_000100:AluCtrl=5'b10110;
        10'b1000_000110:AluCtrl=5'b11001;

        10'b1000_101010:AluCtrl=5'b01110;
        10'b1000_010000:AluCtrl=5'b1111;
        10'b1000_010010:AluCtrl=5'b0001;



        10'b0001_xxxxxx:AluCtrl=5'b00000;
        10'b0010_xxxxxx:AluCtrl=5'b00010;
        10'b0011_xxxxxx:AluCtrl=5'b00110;

        10'b0000_xxxxxx:AluCtrl=5'b00100;

        10'b0001_xxxxxx:AluCtrl=5'b01100;
        10'b0110_xxxxxx:AluCtrl=5'b11010;
        10'b0111_xxxxxx:AluCtrl=5'b11100;
        10'b1001_xxxxxx:AluCtrl=5'b11110;

        10'b1010_xxxxxx:AluCtrl=5'b00011;
        10'b1011_xxxxxx:AluCtrl=5'b00111;

        10'b0000_xxxxxx:AluCtrl=5'b00100;
    

        default:AluCtrl=4'bxxxx;
    
    endcase

end


endmodule
module alucontrol(AluOp,FnField,AluCtrl);



input [3:0] AluOp;
input [5:0] FnField;


output reg [4:0] AluCtrl;


always@(AluOp or FnField)begin
    casex({AluOp,FnField})
    

        10'b1000_100100:AluCtrl=5'b00000;
        10'b1000_100101:AluCtrl=5'b00010;
        10'b1000_100110:AluCtrl=5'b00110;
        10'b1000_100111:AluCtrl=5'b11000;

        10'b1000_100000:AluCtrl=5'b00100;
        10'b1000_100010:AluCtrl=5'b01100;
        10'b1000_011000:AluCtrl=5'b01000;
        10'b1000_011010:AluCtrl=5'b01010;

        10'b1000_000000:AluCtrl=5'b10000;
        10'b1000_000010:AluCtrl=5'b10010;
        10'b1000_000011:AluCtrl=5'b10100;
        10'b1000_000100:AluCtrl=5'b10110;
        10'b1000_000110:AluCtrl=5'b11001;

        10'b1000_101010:AluCtrl=5'b01110;
        10'b1000_010000:AluCtrl=5'b1111;
        10'b1000_010010:AluCtrl=5'b0001;



        10'b0001_xxxxxx:AluCtrl=5'b00000;
        10'b0010_xxxxxx:AluCtrl=5'b00010;
        10'b0011_xxxxxx:AluCtrl=5'b00110;

        10'b0000_xxxxxx:AluCtrl=5'b00100;

        10'b0001_xxxxxx:AluCtrl=5'b01100;
        10'b0110_xxxxxx:AluCtrl=5'b11010;
        10'b0111_xxxxxx:AluCtrl=5'b11100;
        10'b1001_xxxxxx:AluCtrl=5'b11110;

        10'b1010_xxxxxx:AluCtrl=5'b00011;
        10'b1011_xxxxxx:AluCtrl=5'b00111;

        10'b0000_xxxxxx:AluCtrl=5'b00100;
    

        default:AluCtrl=4'bxxxx;
    
    endcase

end


endmodule