data/full_repos/permissive/515245706/milestone1/numberDrawer/number14.v
1: b'%Error: data/full_repos/permissive/515245706/milestone1/numberDrawer/number14.v:47: Cannot find file containing module: \'horizontalLine\'\n horizontalLine h0(\n ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/515245706/milestone1/numberDrawer,data/full_repos/permissive/515245706/horizontalLine\n             data/full_repos/permissive/515245706/milestone1/numberDrawer,data/full_repos/permissive/515245706/horizontalLine.v\n             data/full_repos/permissive/515245706/milestone1/numberDrawer,data/full_repos/permissive/515245706/horizontalLine.sv\n             horizontalLine\n             horizontalLine.v\n             horizontalLine.sv\n             obj_dir/horizontalLine\n             obj_dir/horizontalLine.v\n             obj_dir/horizontalLine.sv\n%Error: data/full_repos/permissive/515245706/milestone1/numberDrawer/number14.v:58: Cannot find file containing module: \'verticalLine\'\n verticalLine v0(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/515245706/milestone1/numberDrawer/number14.v:69: Cannot find file containing module: \'verticalLine\'\n verticalLine v1(\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/515245706/milestone1/numberDrawer/number14.v:80: Cannot find file containing module: \'verticalLine\'\n verticalLine v2(\n ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/515245706/milestone1/numberDrawer/number14.v:115: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'x\' generates 5 bits.\n                                                                                           : ... In instance number14\n assign xOut = xIn + x;\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/515245706/milestone1/numberDrawer/number14.v:116: Operator ADD expects 7 bits on the RHS, but RHS\'s VARREF \'y\' generates 5 bits.\n                                                                                           : ... In instance number14\n assign yOut = yIn + y;\n                   ^\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module number14(xIn, yIn, clk, enable, resetn, xOut, yOut);
	input [7: 0] xIn;
	input [6: 0] yIn;
	input clk, enable, resetn;
	output [7: 0] xOut;
	output [6: 0] yOut;
	
	wire [4:0]x0, y0, x1, y1, x2, y2, x3, y3;
	reg [7:0]counter;
	reg [2:0]ld;
	reg [4:0]x,y;
	
	always @(posedge clk)
	begin
		if (resetn == 0)
			begin
				counter <= 0;
				ld <= 0;
			end				
		else if (enable == 1'b1)
			begin
				if (counter == 8'd120)
					begin
						counter <= 0;
						ld <= 3'd0;
					end
				else if (counter == 8'd20)
					begin
						ld <= 3'd1;
						counter <= counter + 1;
					end
				else if (counter == 8'd60)
					begin
						ld <= 3'd2;
						counter <= counter + 1;
					end
				else if (counter == 8'd80)
					begin
						ld <= 3'd3;
						counter <= counter + 1;
					end
				else 
					counter <= counter + 1;
			end
	end
	
	horizontalLine h0(
		.x(5'd17),
		.y(5'd14),
		.distance(5'd5),
		.clk(clk),
		.enable(enable),
		.resetn(resetn),
		.xOut(x0),
		.yOut(y0)
	);
	
	verticalLine v0(
		.x(5'd8),
		.y(5'd7),
		.distance(5'd15),
		.clk(clk),
		.enable(enable),
		.resetn(resetn),
		.xOut(x1),
		.yOut(y1)
	);
	
	verticalLine v1(
		.x(5'd17),
		.y(5'd7),
		.distance(5'd6),
		.clk(clk),
		.enable(enable),
		.resetn(resetn),
		.xOut(x2),
		.yOut(y2)
	);
	
	verticalLine v2(
		.x(5'd23),
		.y(5'd7),
		.distance(5'd15),
		.clk(clk),
		.enable(enable),
		.resetn(resetn),
		.xOut(x3),
		.yOut(y3)
	);
	
	
	
	always @(*)
	begin
		case (ld)
			3'd0: begin
						x = x0;
						y = y0;
					end
			3'd1: begin
						x = x1;
						y = y1;
					end
			3'd2: begin
						x = x2;
						y = y2;
					end
			3'd3: begin
						x = x3;
						y = y3;
					end
		endcase
	end
	
	assign xOut = xIn + x;
	assign yOut = yIn + y;

endmodule
module number14(xIn, yIn, clk, enable, resetn, xOut, yOut);

	input [7: 0] xIn;
	input [6: 0] yIn;
	input clk, enable, resetn;
	output [7: 0] xOut;
	output [6: 0] yOut;
	
	wire [4:0]x0, y0, x1, y1, x2, y2, x3, y3;
	reg [7:0]counter;
	reg [2:0]ld;
	reg [4:0]x,y;
	
	always @(posedge clk)
	begin
		if (resetn == 0)
			begin
				counter <= 0;
				ld <= 0;
			end				
		else if (enable == 1'b1)
			begin
				if (counter == 8'd120)
					begin
						counter <= 0;
						ld <= 3'd0;
					end
				else if (counter == 8'd20)
					begin
						ld <= 3'd1;
						counter <= counter + 1;
					end
				else if (counter == 8'd60)
					begin
						ld <= 3'd2;
						counter <= counter + 1;
					end
				else if (counter == 8'd80)
					begin
						ld <= 3'd3;
						counter <= counter + 1;
					end
				else 
					counter <= counter + 1;
			end
	end
	
	horizontalLine h0(
		.x(5'd17),
		.y(5'd14),
		.distance(5'd5),
		.clk(clk),
		.enable(enable),
		.resetn(resetn),
		.xOut(x0),
		.yOut(y0)
	);
	
	verticalLine v0(
		.x(5'd8),
		.y(5'd7),
		.distance(5'd15),
		.clk(clk),
		.enable(enable),
		.resetn(resetn),
		.xOut(x1),
		.yOut(y1)
	);
	
	verticalLine v1(
		.x(5'd17),
		.y(5'd7),
		.distance(5'd6),
		.clk(clk),
		.enable(enable),
		.resetn(resetn),
		.xOut(x2),
		.yOut(y2)
	);
	
	verticalLine v2(
		.x(5'd23),
		.y(5'd7),
		.distance(5'd15),
		.clk(clk),
		.enable(enable),
		.resetn(resetn),
		.xOut(x3),
		.yOut(y3)
	);
	
	
	
	always @(*)
	begin
		case (ld)
			3'd0: begin
						x = x0;
						y = y0;
					end
			3'd1: begin
						x = x1;
						y = y1;
					end
			3'd2: begin
						x = x2;
						y = y2;
					end
			3'd3: begin
						x = x3;
						y = y3;
					end
		endcase
	end
	
	assign xOut = xIn + x;
	assign yOut = yIn + y;

endmodule