data/full_repos/permissive/493019833/test/testcase/firrtl/FixedPointDivide.lo/sbt/FixedPointDivide.lo.v
data/verilator_xmls/dd0aa55d-6cb7-4e6c-8ab0-706f1e51880a.xml
module FixedPointDivide(
  input        clock,
  input        reset,
  input  [9:0] io_in,
  output [9:0] io_out
);
  wire [9:0] _T_2 = io_in;
  wire [7:0] _T_4 = _T_2[9:2];
  assign io_out = {{2{_T_4[7]}},_T_4};
endmodule
module FixedPointDivide(
  input        clock,
  input        reset,
  input  [9:0] io_in,
  output [9:0] io_out
);

  wire [9:0] _T_2 = io_in;
  wire [7:0] _T_4 = _T_2[9:2];
  assign io_out = {{2{_T_4[7]}},_T_4};
endmodule