data/full_repos/permissive/472097485/Lib/BoardTest.v
data/verilator_xmls/376ccbb1-2ba4-41ea-9d90-c87be157093c.xml
module BoardTest( input wire clk, input wire [4:0] bt, input wire [7:0] dp, output wire [7:0] ss, output wire [2:0] en );


endmodule
module BoardTest( input wire clk, input wire [4:0] bt, input wire [7:0] dp, output wire [7:0] ss, output wire [2:0] en );



endmodule