data/full_repos/permissive/460468583/data/yosys/achronix/speedster22i/cells_sim.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/460468583/data/yosys/achronix/speedster22i/cells_sim.v:30: Multiple top level modules\n                                                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                       : ... Top module \'PADIN\'\nmodule PADIN (output padout, input padin);\n       ^~~~~\n                                                                                                       : ... Top module \'PADOUT\'\nmodule PADOUT (output padout, input padin, input oe);\n       ^~~~~~\n                                                                                                       : ... Top module \'LUT4\'\nmodule LUT4 (output dout,\n       ^~~~\n                                                                                                       : ... Top module \'DFF\'\nmodule DFF (output q,\n       ^~~\n%Error: data/full_repos/permissive/460468583/data/yosys/achronix/speedster22i/cells_sim.v:73: Duplicate declaration of signal: \'q\'\n                                                                                            : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n   reg             q;\n                   ^\n        data/full_repos/permissive/460468583/data/yosys/achronix/speedster22i/cells_sim.v:71: ... Location of original declaration\nmodule DFF (output q,\n                   ^\n%Error-ASSIGNIN: data/full_repos/permissive/460468583/data/yosys/achronix/speedster22i/cells_sim.v:32: Assigning to input/const variable: \'oe\'\n   assign oe = oe;\n          ^~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module LUT4 (output dout,
             input  din0, din1, din2, din3);

parameter [15:0] lut_function = 16'hFFFF;
reg combout_rt;
wire dataa_w;
wire datab_w;
wire datac_w;
wire datad_w;

assign dataa_w = din0;
assign datab_w = din1;
assign datac_w = din2;
assign datad_w = din3;

function lut_data;
input [15:0] mask;
input        dataa, datab, datac, datad;
reg [7:0]   s3;
reg [3:0]   s2;
reg [1:0]   s1;
  begin
       s3 = datad ? mask[15:8] : mask[7:0];
       s2 = datac ?   s3[7:4]  :   s3[3:0];
       s1 = datab ?   s2[3:2]  :   s2[1:0];
       lut_data = dataa ? s1[1] : s1[0];
  end
endfunction

always @(dataa_w or datab_w or datac_w or datad_w) begin
   combout_rt = lut_data(lut_function, dataa_w, datab_w,
                         datac_w, datad_w);
end
assign dout = combout_rt & 1'b1;
endmodule
module LUT4 (output dout,
             input  din0, din1, din2, din3);


parameter [15:0] lut_function = 16'hFFFF;
reg combout_rt;
wire dataa_w;
wire datab_w;
wire datac_w;
wire datad_w;

assign dataa_w = din0;
assign datab_w = din1;
assign datac_w = din2;
assign datad_w = din3;

function lut_data;
input [15:0] mask;
input        dataa, datab, datac, datad;
reg [7:0]   s3;
reg [3:0]   s2;
reg [1:0]   s1;
  begin
       s3 = datad ? mask[15:8] : mask[7:0];
       s2 = datac ?   s3[7:4]  :   s3[3:0];
       s1 = datab ?   s2[3:2]  :   s2[1:0];
       lut_data = dataa ? s1[1] : s1[0];
  end
endfunction

always @(dataa_w or datab_w or datac_w or datad_w) begin
   combout_rt = lut_data(lut_function, dataa_w, datab_w,
                         datac_w, datad_w);
end
assign dout = combout_rt & 1'b1;
endmodule