data/full_repos/permissive/514862365/MY_TEST.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/514862365/MY_TEST.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/514862365/MY_TEST.v:47: Unsupported: Ignoring delay on this delayed statement.\n      #20;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/514862365/MY_TEST.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/514862365/MY_TEST.v:65: Unsupported: Ignoring delay on this delayed statement.\n      #20;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/514862365/MY_TEST.v:69: Unsupported: Ignoring delay on this delayed statement.\n      #20;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/514862365/MY_TEST.v:73: Unsupported: Ignoring delay on this delayed statement.\n      #20;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/514862365/MY_TEST.v:77: Unsupported: Ignoring delay on this delayed statement.\n      #20;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/514862365/MY_TEST.v:82: Unsupported: Ignoring delay on this delayed statement.\n      #20;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/514862365/MY_TEST.v:86: Unsupported: Ignoring delay on this delayed statement.\n      #20;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/514862365/MY_TEST.v:92: Unsupported: Ignoring delay on this delayed statement.\n      #20;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/514862365/MY_TEST.v:97: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/514862365/MY_TEST.v:103: Unsupported: Ignoring delay on this delayed statement.\n  #190\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/514862365/MY_TEST.v:106: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/514862365/MY_TEST.v:110: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/514862365/MY_TEST.v:112: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/514862365/MY_TEST.v:117: Unsupported: Ignoring delay on this delayed statement.\n  #300\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/514862365/MY_TEST.v:120: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/514862365/MY_TEST.v:124: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/514862365/MY_TEST.v:129: Unsupported: Ignoring delay on this delayed statement.\n  #900000\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/514862365/MY_TEST.v:133: Unsupported: Ignoring delay on this delayed statement.\n   always #10 clock = ~clock; \n          ^\n%Error: data/full_repos/permissive/514862365/MY_TEST.v:135: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("FIFO_BUFFER_MEMORY.vcd"); \n        ^~~~~~~~~\n%Error: data/full_repos/permissive/514862365/MY_TEST.v:136: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0,MY_TEST);\n  ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 20 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module MY_TEST;


	reg clock;
	reg [31:0] data_in;
	reg read;
	reg write;
	reg enable;
	reg reset;


	wire [31:0] data_out;
	wire empty;
	


	FIFO_BUFFER_MEMORY uut (
		.clock(clock), 
		.data_in(data_in), 
		.read(read), 
		.write(write), 
		.enable(enable), 
		.data_out(data_out), 
		.reset(reset), 
		.empty(empty)
		);

	initial begin

		clock = 1'b0;
		data_in = 32'hx;
		read = 0;
		write = 0;
		enable = 0;
		reset = 1;


		#100;
        

      enable  = 1'b1;

      reset  = 1'b1;

      #20;

      reset  = 1'b0;
		

		
		read=1'b1;

		#20;
		
		read=1'b0;
		

		
		write  = 1'b1;
		
		data_in  = 32'h0;

      #20;

      data_in  = 32'h1;

      #20;

      data_in  = 32'h2;

      #20;

      data_in  = 32'h3;

      #20;

      data_in  = 32'h4;
		
		
      #20;

      data_in  = 32'h5;

      #20;

      data_in  = 32'h6;
      
		

      #20;

      data_in  = 32'h7; 

     
		#20
		
		write=1'b0;  
		
		read=1'b1;
		
		#190
		read=1'b0;
		
		#20
		write=1'b1;
		data_in=32'h8;
		
		#20
		write=1'b0;
		#20
		read=1'b1;
		
		
		
		#300
		read=1'b0;
		
		#20
		write=1'b1;
		data_in=32'h9;
		
		#20
		write=1'b0;

		read=1'b1;
		
		#900000
		$finish;
		
	end
   always #10 clock = ~clock; 
        initial begin
        $dumpfile("FIFO_BUFFER_MEMORY.vcd"); 
		$dumpvars(0,MY_TEST);
       end
endmodule
module MY_TEST;



	reg clock;
	reg [31:0] data_in;
	reg read;
	reg write;
	reg enable;
	reg reset;


	wire [31:0] data_out;
	wire empty;
	


	FIFO_BUFFER_MEMORY uut (
		.clock(clock), 
		.data_in(data_in), 
		.read(read), 
		.write(write), 
		.enable(enable), 
		.data_out(data_out), 
		.reset(reset), 
		.empty(empty)
		);

	initial begin

		clock = 1'b0;
		data_in = 32'hx;
		read = 0;
		write = 0;
		enable = 0;
		reset = 1;


		#100;
        

      enable  = 1'b1;

      reset  = 1'b1;

      #20;

      reset  = 1'b0;
		

		
		read=1'b1;

		#20;
		
		read=1'b0;
		

		
		write  = 1'b1;
		
		data_in  = 32'h0;

      #20;

      data_in  = 32'h1;

      #20;

      data_in  = 32'h2;

      #20;

      data_in  = 32'h3;

      #20;

      data_in  = 32'h4;
		
		
      #20;

      data_in  = 32'h5;

      #20;

      data_in  = 32'h6;
      
		

      #20;

      data_in  = 32'h7; 

     
		#20
		
		write=1'b0;  
		
		read=1'b1;
		
		#190
		read=1'b0;
		
		#20
		write=1'b1;
		data_in=32'h8;
		
		#20
		write=1'b0;
		#20
		read=1'b1;
		
		
		
		#300
		read=1'b0;
		
		#20
		write=1'b1;
		data_in=32'h9;
		
		#20
		write=1'b0;

		read=1'b1;
		
		#900000
		$finish;
		
	end
   always #10 clock = ~clock; 
        initial begin
        $dumpfile("FIFO_BUFFER_MEMORY.vcd"); 
		$dumpvars(0,MY_TEST);
       end
endmodule