data/full_repos/permissive/431605717/Code/RV32IM/MEM.v
data/verilator_xmls/65d38ca2-2a6c-4ac4-b832-28aeeffd5bad.xml
module risc_v_32_mem(m_addr,d_f_mem,inst_decode,mem_out);
								 
	input  [31:0] m_addr;
    input  [31:0] d_f_mem;
    input  [36:0] inst_decode;
	
	output reg [31:0] mem_out;


    wire          i_lb    = inst_decode[10];
    wire          i_lh    = inst_decode[11];
    wire          i_lw    = inst_decode[12];
    wire          i_lbu   = inst_decode[13];
    wire          i_lhu   = inst_decode[14];



	always @(*) begin
        mem_out = 0;
        case (1'b1)
            i_lw: begin
                mem_out = d_f_mem;end
            i_lbu: begin
                case(m_addr[1:0])
                  2'b00: mem_out = {24'h0,d_f_mem[ 7: 0]};
                  2'b01: mem_out = {24'h0,d_f_mem[15: 8]};
                  2'b10: mem_out = {24'h0,d_f_mem[23:16]};
                  2'b11: mem_out = {24'h0,d_f_mem[31:24]};
                endcase end
            i_lb: begin
                case(m_addr[1:0])
                  2'b00: mem_out = {{24{d_f_mem[ 7]}},d_f_mem[ 7: 0]};
                  2'b01: mem_out = {{24{d_f_mem[15]}},d_f_mem[15: 8]};
                  2'b10: mem_out = {{24{d_f_mem[23]}},d_f_mem[23:16]};
                  2'b11: mem_out = {{24{d_f_mem[31]}},d_f_mem[31:24]};
                endcase end
            i_lhu: begin
                case(m_addr[1])
                  1'b0: mem_out = {16'h0,d_f_mem[15: 0]};
                  1'b1: mem_out = {16'h0,d_f_mem[31:16]};
                endcase end
            i_lh: begin
                case(m_addr[1])
                  1'b0: mem_out = {{16{d_f_mem[15]}},d_f_mem[15: 0]};
                  1'b1: mem_out = {{16{d_f_mem[31]}},d_f_mem[31:16]};
                endcase end
            default: ;
        endcase
    end

	
endmodule
module risc_v_32_mem(m_addr,d_f_mem,inst_decode,mem_out);

								 
	input  [31:0] m_addr;
    input  [31:0] d_f_mem;
    input  [36:0] inst_decode;
	
	output reg [31:0] mem_out;


    wire          i_lb    = inst_decode[10];
    wire          i_lh    = inst_decode[11];
    wire          i_lw    = inst_decode[12];
    wire          i_lbu   = inst_decode[13];
    wire          i_lhu   = inst_decode[14];



	always @(*) begin
        mem_out = 0;
        case (1'b1)
            i_lw: begin
                mem_out = d_f_mem;end
            i_lbu: begin
                case(m_addr[1:0])
                  2'b00: mem_out = {24'h0,d_f_mem[ 7: 0]};
                  2'b01: mem_out = {24'h0,d_f_mem[15: 8]};
                  2'b10: mem_out = {24'h0,d_f_mem[23:16]};
                  2'b11: mem_out = {24'h0,d_f_mem[31:24]};
                endcase end
            i_lb: begin
                case(m_addr[1:0])
                  2'b00: mem_out = {{24{d_f_mem[ 7]}},d_f_mem[ 7: 0]};
                  2'b01: mem_out = {{24{d_f_mem[15]}},d_f_mem[15: 8]};
                  2'b10: mem_out = {{24{d_f_mem[23]}},d_f_mem[23:16]};
                  2'b11: mem_out = {{24{d_f_mem[31]}},d_f_mem[31:24]};
                endcase end
            i_lhu: begin
                case(m_addr[1])
                  1'b0: mem_out = {16'h0,d_f_mem[15: 0]};
                  1'b1: mem_out = {16'h0,d_f_mem[31:16]};
                endcase end
            i_lh: begin
                case(m_addr[1])
                  1'b0: mem_out = {{16{d_f_mem[15]}},d_f_mem[15: 0]};
                  1'b1: mem_out = {{16{d_f_mem[31]}},d_f_mem[31:16]};
                endcase end
            default: ;
        endcase
    end

	
endmodule