data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/rtldb1chcnt.v
1: b'%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/rtldb1chcnt.v:56: Operator AND expects 9 bits on the LHS, but LHS\'s REPLICATE generates 8 bits.\n                                                                                                                                  : ... In instance rtldb1chcnt\nwire [NUM:0]        numadd = {NUM{vld}}&num + vld;\n                                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/rtldb1chcnt.v:56: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'vld\' generates 1 bits.\n                                                                                                                                  : ... In instance rtldb1chcnt\nwire [NUM:0]        numadd = {NUM{vld}}&num + vld;\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/rtldb1chcnt.v:60: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'numadd\' generates 9 bits.\n                                                                                                                                  : ... In instance rtldb1chcnt\n    else if (upen_r2c && uprs)    cnt <= numadd;\n                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/rtldb1chcnt.v:61: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'numadd\' generates 9 bits.\n                                                                                                                                  : ... In instance rtldb1chcnt\n    else    cnt <= &cnt ? cnt : numadd + cnt;\n                                       ^\n%Error: Exiting due to 4 warning(s)\n'
module rtldb1chcnt
    (
     clk,
     rst,
     
     vld,
     num,
     upen_ro,
     upen_r2c,
     uprs,
     uprdy,
     updo,
     out
     );



parameter           WIDTH = 32;
parameter           NUM = 8;



input               clk;
input               rst;

input               vld;
input [NUM-1:0]     num;
input               upen_ro;
input               upen_r2c;
input               uprs;
output              uprdy;
output [WIDTH-1:0]  updo;
output [WIDTH-1:0]  out;







reg [WIDTH-1:0]     cnt;
tri0 [NUM-1:0]      num;
wire [NUM:0]        numadd = {NUM{vld}}&num + vld;
always @ (posedge clk or posedge rst)
    begin
    if (rst)  cnt <= {WIDTH{1'b0}};
    else if (upen_r2c && uprs)    cnt <= numadd;
    else    cnt <= &cnt ? cnt : numadd + cnt;
    end

wire            uprdy;
assign          uprdy = (upen_r2c || upen_ro) && uprs;

wire [WIDTH-1:0] updo;
assign           updo = (upen_r2c | upen_ro) ? cnt : {WIDTH{1'b0}};

wire [WIDTH-1:0] out  = cnt;

endmodule
module rtldb1chcnt
    (
     clk,
     rst,
     
     vld,
     num,
     upen_ro,
     upen_r2c,
     uprs,
     uprdy,
     updo,
     out
     );




parameter           WIDTH = 32;
parameter           NUM = 8;



input               clk;
input               rst;

input               vld;
input [NUM-1:0]     num;
input               upen_ro;
input               upen_r2c;
input               uprs;
output              uprdy;
output [WIDTH-1:0]  updo;
output [WIDTH-1:0]  out;







reg [WIDTH-1:0]     cnt;
tri0 [NUM-1:0]      num;
wire [NUM:0]        numadd = {NUM{vld}}&num + vld;
always @ (posedge clk or posedge rst)
    begin
    if (rst)  cnt <= {WIDTH{1'b0}};
    else if (upen_r2c && uprs)    cnt <= numadd;
    else    cnt <= &cnt ? cnt : numadd + cnt;
    end

wire            uprdy;
assign          uprdy = (upen_r2c || upen_ro) && uprs;

wire [WIDTH-1:0] updo;
assign           updo = (upen_r2c | upen_ro) ? cnt : {WIDTH{1'b0}};

wire [WIDTH-1:0] out  = cnt;

endmodule