data/full_repos/permissive/497571993/vending_machine_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/497571993/vending_machine_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\nforever #10 clk=~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/497571993/vending_machine_tb.v:20: syntax error, unexpected \'@\'\n@(negedge clk)\n^\n%Warning-STMTDLY: data/full_repos/permissive/497571993/vending_machine_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/497571993/vending_machine_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n#30;\n^\n%Warning-STMTDLY: data/full_repos/permissive/497571993/vending_machine_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/497571993/vending_machine_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n#30;\n^\n%Warning-STMTDLY: data/full_repos/permissive/497571993/vending_machine_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/497571993/vending_machine_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n#30;\n^\n%Warning-STMTDLY: data/full_repos/permissive/497571993/vending_machine_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n#30\n^\n%Error: data/full_repos/permissive/497571993/vending_machine_tb.v:64: Unsupported or unknown PLI call: $monitor\n$monitor ("Input clk=%b,rst=%b,in=%b, Output out=%b,change=%b",clk,rst,in,out,change);\n^~~~~~~~\n%Error: Exiting due to 2 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module vending_machine_tb();
reg clk,rst;
reg [1:0]in;

wire out;
wire [1:0]change;

parameter zero= 2'b00 , one = 2'b01, two = 2'b10;

vending_machine DUT(clk,rst,in,out,change);

initial
begin
clk =1'b0;
forever #10 clk=~clk;
end

task reset;
begin
@(negedge clk)
rst= 1'b1;
@(negedge clk)
rst= 1'b0;
end
endtask

task initialize;
begin
in=0;
end
endtask


task enter (input [1:0]i);
begin
in = i;
end
endtask

initial
begin
initialize;
reset;
enter (one);
#20;
enter (zero);
#30;
reset;
enter (two);
#20;
enter(one);
#30;
reset;
enter (two);
#20;
enter(two);
#30;
reset;
#30
$finish;
end

initial
$monitor ("Input clk=%b,rst=%b,in=%b, Output out=%b,change=%b",clk,rst,in,out,change);

endmodule
module vending_machine_tb();

reg clk,rst;
reg [1:0]in;

wire out;
wire [1:0]change;

parameter zero= 2'b00 , one = 2'b01, two = 2'b10;

vending_machine DUT(clk,rst,in,out,change);

initial
begin
clk =1'b0;
forever #10 clk=~clk;
end

task reset;
begin
@(negedge clk)
rst= 1'b1;
@(negedge clk)
rst= 1'b0;
end
endtask

task initialize;
begin
in=0;
end
endtask


task enter (input [1:0]i);
begin
in = i;
end
endtask

initial
begin
initialize;
reset;
enter (one);
#20;
enter (zero);
#30;
reset;
enter (two);
#20;
enter(one);
#30;
reset;
enter (two);
#20;
enter(two);
#30;
reset;
#30
$finish;
end

initial
$monitor ("Input clk=%b,rst=%b,in=%b, Output out=%b,change=%b",clk,rst,in,out,change);

endmodule