data/full_repos/permissive/426864978/midterm3/task1/tb_rtl_reverse.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/426864978/midterm3/task1/tb_rtl_reverse.sv:12: Unsupported: Ignoring delay on this delayed statement.\n  always #5 clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/426864978/midterm3/task1/tb_rtl_reverse.sv:22: Unsupported: Ignoring delay on this delayed statement.\n    #2 rst_n = 0;\n    ^\n%Error: data/full_repos/permissive/426864978/midterm3/task1/tb_rtl_reverse.sv:23: syntax error, unexpected \'@\'\n    @(posedge clk);  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/midterm3/task1/tb_rtl_reverse.sv:26: Unsupported: Ignoring delay on this delayed statement.\n    #2 rst_n = 1;\n    ^\n%Error: data/full_repos/permissive/426864978/midterm3/task1/tb_rtl_reverse.sv:30: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/midterm3/task1/tb_rtl_reverse.sv:34: syntax error, unexpected \'@\'\n    din = 17;  @(negedge clk);\n               ^\n%Error: data/full_repos/permissive/426864978/midterm3/task1/tb_rtl_reverse.sv:37: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/midterm3/task1/tb_rtl_reverse.sv:40: syntax error, unexpected \'@\'\n    din = 18;  @(negedge clk);\n               ^\n%Error: data/full_repos/permissive/426864978/midterm3/task1/tb_rtl_reverse.sv:41: syntax error, unexpected \'@\'\n    din = 19;  @(negedge clk);\n               ^\n%Error: data/full_repos/permissive/426864978/midterm3/task1/tb_rtl_reverse.sv:42: syntax error, unexpected \'@\'\n    din = 20;  @(negedge clk);\n               ^\n%Error: data/full_repos/permissive/426864978/midterm3/task1/tb_rtl_reverse.sv:43: syntax error, unexpected \'@\'\n    din = 255; @(negedge clk);\n               ^\n%Error: data/full_repos/permissive/426864978/midterm3/task1/tb_rtl_reverse.sv:46: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/midterm3/task1/tb_rtl_reverse.sv:49: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/midterm3/task1/tb_rtl_reverse.sv:57: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/midterm3/task1/tb_rtl_reverse.sv:63: Unsupported: Ignoring delay on this delayed statement.\n    #200;\n    ^\n%Error: Exiting due to 11 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_reverse();

  logic clk=0;
  logic rst_n;

  logic [7:0] din, dout;
  logic din_valid;
  logic rdy, ena;

  always #5 clk = ~clk;

  reverse dut( .* );

  initial
  begin

    din_valid = 0;
    rdy = 0;

    #2 rst_n = 0;
    @(posedge clk);
    @(negedge clk);

    #2 rst_n = 1;
    rdy = 1;


        @(negedge clk);
        @(negedge clk);

    din_valid = 1;
    din = 17;  @(negedge clk);
    din_valid = 0;
    din = 255;
        @(negedge clk);
        @(negedge clk);
    din_valid = 1;
    din = 18;  @(negedge clk);
    din = 19;  @(negedge clk);
    din = 20;  @(negedge clk);
    din = 255; @(negedge clk);
        @(negedge clk);
    rdy = 0;
        @(negedge clk);
        @(negedge clk);
    rdy = 1;
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
    rdy = 0;
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
    din_valid = 0;

    #200;

    $finish;
  end

endmodule
module tb_reverse();


  logic clk=0;
  logic rst_n;

  logic [7:0] din, dout;
  logic din_valid;
  logic rdy, ena;

  always #5 clk = ~clk;

  reverse dut( .* );

  initial
  begin

    din_valid = 0;
    rdy = 0;

    #2 rst_n = 0;
    @(posedge clk);
    @(negedge clk);

    #2 rst_n = 1;
    rdy = 1;


        @(negedge clk);
        @(negedge clk);

    din_valid = 1;
    din = 17;  @(negedge clk);
    din_valid = 0;
    din = 255;
        @(negedge clk);
        @(negedge clk);
    din_valid = 1;
    din = 18;  @(negedge clk);
    din = 19;  @(negedge clk);
    din = 20;  @(negedge clk);
    din = 255; @(negedge clk);
        @(negedge clk);
    rdy = 0;
        @(negedge clk);
        @(negedge clk);
    rdy = 1;
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
    rdy = 0;
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
        @(negedge clk);
    din_valid = 0;

    #200;

    $finish;
  end

endmodule