data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:137: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD/2);\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:139: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD/2);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:141: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD/2);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:149: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD) tri_fifo_wr_data = ZeroFP; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:150: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD) tri_fifo_wr_data = OneFP; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:151: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD) tri_fifo_wr_data = OneFP; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:152: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD) tri_fifo_wr_data = ZeroFP; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:153: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD) tri_fifo_wr_data = ZeroFP; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:154: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD) tri_fifo_wr_data = ZeroFP; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:155: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD) tri_fifo_wr_data = ZeroFP; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:157: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD) tri_fifo_wr_data = ZeroFP; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:158: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD) tri_fifo_wr_data = TwoFP; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:159: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD) tri_fifo_wr_data = OneFP; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:160: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD) tri_fifo_wr_data = ZeroFP; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:161: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD) tri_fifo_wr_data = OneFP; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:162: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD) tri_fifo_wr_data = ZeroFP; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:163: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD) tri_fifo_wr_data = ZeroFP; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:164: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD) tri_fifo_wr_data = ZeroFP; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:166: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD) tri_fifo_wr_data = FourFP; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:167: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD) tri_fifo_wr_data = ZeroFP; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:168: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD) tri_fifo_wr_data = OneFP; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:169: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD) tri_fifo_wr_data = ZeroFP; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:170: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD) tri_fifo_wr_data = ZeroFP; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:171: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD) tri_fifo_wr_data = OneFP; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:172: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD) tri_fifo_wr_data = ZeroFP; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:173: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD) tri_fifo_wr_data = ZeroFP; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:176: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD) start = 1\'b1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:190: Unsupported: Ignoring delay on this delayed statement.\n            #PERIOD;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:197: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD/2);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:199: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD/2);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:222: Unsupported: Ignoring delay on this delayed statement.\n            #TIMEOUT;\n            ^\n%Error: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:229: Unsupported or unknown PLI call: $dumpfile\n            $dumpfile("triangle_pipe_Test.vcd");\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:230: Unsupported or unknown PLI call: $dumpvars\n            $dumpvars(0,triangle_pipe_Test);\n            ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/triangle_pipe/triangle_pipe_Test.v:231: Unsupported: Ignoring delay on this delayed statement.\n            #1;\n            ^\n%Error: Exiting due to 2 error(s), 32 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module triangle_pipe_Test#(
    parameter NOPERSPECTIVE = 'b0,
    parameter FLAT = 'b0,
    parameter PROVOKEMODE = 'b0,
    parameter VERTEXSIZE = 4'd7,
    parameter WINDINGORDER = 1'b0,
    parameter ORIGIN_LOCATION = 1'b0,
    parameter FACE_CULLER_ENABLE = 1'b1,
    parameter MODE = 'b00,
    parameter RESX = 32'd1920,
    parameter RESY = 32'd1080
)();
    
    
    localparam DATA_WIDTH = 32;
    localparam ADDR_WIDTH = 4;
    localparam FRAG_FIFODEPTH = (2**ADDR_WIDTH)*20;
    localparam TRI_FIFODEPTH = (2**ADDR_WIDTH)*3*1;

    localparam CYCLES_WAIT_FOR_RECIEVE = 4'b0001;
    localparam CLOCKWISE =  1'b1;
    localparam ANTICLOCKWISE = 1'b0;
    localparam FourFP = 32'h40800000;
    localparam TwoFP = 32'h40000000;
    localparam OneFP = 32'h3f800000;
    localparam ZeroFP = 32'h00000000;
    localparam HalfFP = 32'h3f000000;
    localparam QuarterFP = 32'h3e800000;
    localparam PERIOD = 20;
    localparam TIMEOUT = PERIOD*10000;

    reg clk;
    reg resetn, en, start;
    wire done, ready;


    wire [DATA_WIDTH-1:0] tri_fifo_rd_data;
    wire tri_fifo_rd_en;   
    reg [DATA_WIDTH-1:0] tri_fifo_wr_data;
    reg tri_fifo_wr_en; 
    
    wire tri_fifo_full; 
    wire tri_fifo_empty;
    wire tri_fifo_threshold; 
    wire tri_fifo_overflow; 
    wire tri_fifo_underflow;


    wire [DATA_WIDTH-1:0] frag_fifo_wr_data;
    wire frag_fifo_wr_en; 

    wire frag_fifo_full; 
    wire frag_fifo_empty;
    wire frag_fifo_threshold; 
    wire frag_fifo_overflow; 
    wire frag_fifo_underflow;

    reg noPerspective, flat, provokeMode, windingOrder, faceCullerEnable, origin_location;
    reg [ADDR_WIDTH-1:0] vertexSize;
    reg [1:0] Mode;
    reg [31:0] resx,resy;

triangle_pipe#(
    DATA_WIDTH,
    ADDR_WIDTH,      
    CYCLES_WAIT_FOR_RECIEVE
) DUT (
    clk, resetn, en, start, ready, done,


    frag_fifo_wr_data,
    frag_fifo_wr_en, 


    frag_fifo_full, 
    frag_fifo_empty, 
    frag_fifo_threshold, 
    frag_fifo_overflow, 
    frag_fifo_underflow,


    tri_fifo_rd_data,
    tri_fifo_rd_en, 


    tri_fifo_full, 
    tri_fifo_empty, 
    tri_fifo_threshold, 
    tri_fifo_overflow, 
    tri_fifo_underflow,


    noPerspective, flat, provokeMode, 
    windingOrder, vertexSize, faceCullerEnable, 
    Mode, origin_location,
    resx, resy
);

FIFO #(
    DATA_WIDTH,
    TRI_FIFODEPTH
) tri_FIFO (
    .data_out(tri_fifo_rd_data),
    .fifo_full(tri_fifo_full), 
    .fifo_empty(tri_fifo_empty), 
    .fifo_threshold(tri_fifo_threshold), 
    .fifo_overflow(tri_fifo_overflow), 
    .fifo_underflow(tri_fifo_underflow),
    .clk(clk), 
    .resetn(resetn), 
    .wr(tri_fifo_wr_en), 
    .rd(tri_fifo_rd_en), 
    .data_in(tri_fifo_wr_data)
);  

FIFO #(
    DATA_WIDTH,
    FRAG_FIFODEPTH
) frag_FIFO (
    .data_out(),
    .fifo_full(frag_fifo_full), 
    .fifo_empty(frag_fifo_empty), 
    .fifo_threshold(frag_fifo_threshold), 
    .fifo_overflow(frag_fifo_overflow), 
    .fifo_underflow(frag_fifo_underflow),
    .clk(clk), 
    .resetn(resetn), 
    .wr(frag_fifo_wr_en), 
    .rd(), 
    .data_in(frag_fifo_wr_data)
);  
    initial
        begin
            $display("{\"sim_log\": [");
            en = 1'b1;
            resetn = 1'b1;
            #(PERIOD/2);
            resetn = 1'b0; 
            #(PERIOD/2);
            resetn = 1'b1;
            #(PERIOD/2);
            



            
            tri_fifo_wr_en = 1'b1;
            tri_fifo_wr_data = ZeroFP;
            #(PERIOD) tri_fifo_wr_data = ZeroFP;
            #(PERIOD) tri_fifo_wr_data = OneFP;
            #(PERIOD) tri_fifo_wr_data = OneFP;
            #(PERIOD) tri_fifo_wr_data = ZeroFP;
            #(PERIOD) tri_fifo_wr_data = ZeroFP;
            #(PERIOD) tri_fifo_wr_data = ZeroFP;
            #(PERIOD) tri_fifo_wr_data = ZeroFP;

            #(PERIOD) tri_fifo_wr_data = ZeroFP;
            #(PERIOD) tri_fifo_wr_data = TwoFP;
            #(PERIOD) tri_fifo_wr_data = OneFP;
            #(PERIOD) tri_fifo_wr_data = ZeroFP;
            #(PERIOD) tri_fifo_wr_data = OneFP;
            #(PERIOD) tri_fifo_wr_data = ZeroFP;
            #(PERIOD) tri_fifo_wr_data = ZeroFP;
            #(PERIOD) tri_fifo_wr_data = ZeroFP;

            #(PERIOD) tri_fifo_wr_data = FourFP;
            #(PERIOD) tri_fifo_wr_data = ZeroFP;
            #(PERIOD) tri_fifo_wr_data = OneFP;
            #(PERIOD) tri_fifo_wr_data = ZeroFP;
            #(PERIOD) tri_fifo_wr_data = ZeroFP;
            #(PERIOD) tri_fifo_wr_data = OneFP;
            #(PERIOD) tri_fifo_wr_data = ZeroFP;
            #(PERIOD) tri_fifo_wr_data = ZeroFP;


            #(PERIOD) start = 1'b1;
            tri_fifo_wr_en = 1'b0;
            

            noPerspective = NOPERSPECTIVE;
            flat = FLAT;
            provokeMode = PROVOKEMODE;
            vertexSize = VERTEXSIZE;
            windingOrder = WINDINGORDER;
            faceCullerEnable = FACE_CULLER_ENABLE;
            Mode = MODE;
            origin_location = ORIGIN_LOCATION;
            resx = RESX;
            resy = RESY;
            #PERIOD;
            start = 1'b0;

        end
    always 
        begin
            clk = 1'b1; 
            #(PERIOD/2);
            clk = 1'b0;
            #(PERIOD/2);
        end
    
    always @(posedge clk) begin
        if(frag_fifo_wr_en) begin
            $display("{\"label\":\"[fragment_write]\", \"data\":\"0x%0h\"},", frag_fifo_wr_data);
        end
    end
    always @(posedge clk) begin
        if(tri_fifo_rd_en) begin
            $display("{\"label\":\"[triangle_read]\", \"data\":\"0x%0h\"},", tri_fifo_rd_data);
        end
    end
    always@(negedge clk) begin
        if (done == 1'b1) begin
            $display("{\"label\":\"[message]\", \"data\":\"test finished for input combination\"}");
            $display("]}");
            $finish;
        end
    end

    initial 
        begin
            #TIMEOUT;
            $display("{\"label\":\"[message]\", \"data\":\"Simulation Timed Out :(\"}");
            $display("]}");
            $finish;
        end
    initial
        begin
            $dumpfile("triangle_pipe_Test.vcd");
            $dumpvars(0,triangle_pipe_Test);
            #1;
        end
endmodule
module triangle_pipe_Test#(
    parameter NOPERSPECTIVE = 'b0,
    parameter FLAT = 'b0,
    parameter PROVOKEMODE = 'b0,
    parameter VERTEXSIZE = 4'd7,
    parameter WINDINGORDER = 1'b0,
    parameter ORIGIN_LOCATION = 1'b0,
    parameter FACE_CULLER_ENABLE = 1'b1,
    parameter MODE = 'b00,
    parameter RESX = 32'd1920,
    parameter RESY = 32'd1080
)();

    
    
    localparam DATA_WIDTH = 32;
    localparam ADDR_WIDTH = 4;
    localparam FRAG_FIFODEPTH = (2**ADDR_WIDTH)*20;
    localparam TRI_FIFODEPTH = (2**ADDR_WIDTH)*3*1;

    localparam CYCLES_WAIT_FOR_RECIEVE = 4'b0001;
    localparam CLOCKWISE =  1'b1;
    localparam ANTICLOCKWISE = 1'b0;
    localparam FourFP = 32'h40800000;
    localparam TwoFP = 32'h40000000;
    localparam OneFP = 32'h3f800000;
    localparam ZeroFP = 32'h00000000;
    localparam HalfFP = 32'h3f000000;
    localparam QuarterFP = 32'h3e800000;
    localparam PERIOD = 20;
    localparam TIMEOUT = PERIOD*10000;

    reg clk;
    reg resetn, en, start;
    wire done, ready;


    wire [DATA_WIDTH-1:0] tri_fifo_rd_data;
    wire tri_fifo_rd_en;   
    reg [DATA_WIDTH-1:0] tri_fifo_wr_data;
    reg tri_fifo_wr_en; 
    
    wire tri_fifo_full; 
    wire tri_fifo_empty;
    wire tri_fifo_threshold; 
    wire tri_fifo_overflow; 
    wire tri_fifo_underflow;


    wire [DATA_WIDTH-1:0] frag_fifo_wr_data;
    wire frag_fifo_wr_en; 

    wire frag_fifo_full; 
    wire frag_fifo_empty;
    wire frag_fifo_threshold; 
    wire frag_fifo_overflow; 
    wire frag_fifo_underflow;

    reg noPerspective, flat, provokeMode, windingOrder, faceCullerEnable, origin_location;
    reg [ADDR_WIDTH-1:0] vertexSize;
    reg [1:0] Mode;
    reg [31:0] resx,resy;

triangle_pipe#(
    DATA_WIDTH,
    ADDR_WIDTH,      
    CYCLES_WAIT_FOR_RECIEVE
) DUT (
    clk, resetn, en, start, ready, done,


    frag_fifo_wr_data,
    frag_fifo_wr_en, 


    frag_fifo_full, 
    frag_fifo_empty, 
    frag_fifo_threshold, 
    frag_fifo_overflow, 
    frag_fifo_underflow,


    tri_fifo_rd_data,
    tri_fifo_rd_en, 


    tri_fifo_full, 
    tri_fifo_empty, 
    tri_fifo_threshold, 
    tri_fifo_overflow, 
    tri_fifo_underflow,


    noPerspective, flat, provokeMode, 
    windingOrder, vertexSize, faceCullerEnable, 
    Mode, origin_location,
    resx, resy
);

FIFO #(
    DATA_WIDTH,
    TRI_FIFODEPTH
) tri_FIFO (
    .data_out(tri_fifo_rd_data),
    .fifo_full(tri_fifo_full), 
    .fifo_empty(tri_fifo_empty), 
    .fifo_threshold(tri_fifo_threshold), 
    .fifo_overflow(tri_fifo_overflow), 
    .fifo_underflow(tri_fifo_underflow),
    .clk(clk), 
    .resetn(resetn), 
    .wr(tri_fifo_wr_en), 
    .rd(tri_fifo_rd_en), 
    .data_in(tri_fifo_wr_data)
);  

FIFO #(
    DATA_WIDTH,
    FRAG_FIFODEPTH
) frag_FIFO (
    .data_out(),
    .fifo_full(frag_fifo_full), 
    .fifo_empty(frag_fifo_empty), 
    .fifo_threshold(frag_fifo_threshold), 
    .fifo_overflow(frag_fifo_overflow), 
    .fifo_underflow(frag_fifo_underflow),
    .clk(clk), 
    .resetn(resetn), 
    .wr(frag_fifo_wr_en), 
    .rd(), 
    .data_in(frag_fifo_wr_data)
);  
    initial
        begin
            $display("{\"sim_log\": [");
            en = 1'b1;
            resetn = 1'b1;
            #(PERIOD/2);
            resetn = 1'b0; 
            #(PERIOD/2);
            resetn = 1'b1;
            #(PERIOD/2);
            



            
            tri_fifo_wr_en = 1'b1;
            tri_fifo_wr_data = ZeroFP;
            #(PERIOD) tri_fifo_wr_data = ZeroFP;
            #(PERIOD) tri_fifo_wr_data = OneFP;
            #(PERIOD) tri_fifo_wr_data = OneFP;
            #(PERIOD) tri_fifo_wr_data = ZeroFP;
            #(PERIOD) tri_fifo_wr_data = ZeroFP;
            #(PERIOD) tri_fifo_wr_data = ZeroFP;
            #(PERIOD) tri_fifo_wr_data = ZeroFP;

            #(PERIOD) tri_fifo_wr_data = ZeroFP;
            #(PERIOD) tri_fifo_wr_data = TwoFP;
            #(PERIOD) tri_fifo_wr_data = OneFP;
            #(PERIOD) tri_fifo_wr_data = ZeroFP;
            #(PERIOD) tri_fifo_wr_data = OneFP;
            #(PERIOD) tri_fifo_wr_data = ZeroFP;
            #(PERIOD) tri_fifo_wr_data = ZeroFP;
            #(PERIOD) tri_fifo_wr_data = ZeroFP;

            #(PERIOD) tri_fifo_wr_data = FourFP;
            #(PERIOD) tri_fifo_wr_data = ZeroFP;
            #(PERIOD) tri_fifo_wr_data = OneFP;
            #(PERIOD) tri_fifo_wr_data = ZeroFP;
            #(PERIOD) tri_fifo_wr_data = ZeroFP;
            #(PERIOD) tri_fifo_wr_data = OneFP;
            #(PERIOD) tri_fifo_wr_data = ZeroFP;
            #(PERIOD) tri_fifo_wr_data = ZeroFP;


            #(PERIOD) start = 1'b1;
            tri_fifo_wr_en = 1'b0;
            

            noPerspective = NOPERSPECTIVE;
            flat = FLAT;
            provokeMode = PROVOKEMODE;
            vertexSize = VERTEXSIZE;
            windingOrder = WINDINGORDER;
            faceCullerEnable = FACE_CULLER_ENABLE;
            Mode = MODE;
            origin_location = ORIGIN_LOCATION;
            resx = RESX;
            resy = RESY;
            #PERIOD;
            start = 1'b0;

        end
    always 
        begin
            clk = 1'b1; 
            #(PERIOD/2);
            clk = 1'b0;
            #(PERIOD/2);
        end
    
    always @(posedge clk) begin
        if(frag_fifo_wr_en) begin
            $display("{\"label\":\"[fragment_write]\", \"data\":\"0x%0h\"},", frag_fifo_wr_data);
        end
    end
    always @(posedge clk) begin
        if(tri_fifo_rd_en) begin
            $display("{\"label\":\"[triangle_read]\", \"data\":\"0x%0h\"},", tri_fifo_rd_data);
        end
    end
    always@(negedge clk) begin
        if (done == 1'b1) begin
            $display("{\"label\":\"[message]\", \"data\":\"test finished for input combination\"}");
            $display("]}");
            $finish;
        end
    end

    initial 
        begin
            #TIMEOUT;
            $display("{\"label\":\"[message]\", \"data\":\"Simulation Timed Out :(\"}");
            $display("]}");
            $finish;
        end
    initial
        begin
            $dumpfile("triangle_pipe_Test.vcd");
            $dumpvars(0,triangle_pipe_Test);
            #1;
        end
endmodule