data/full_repos/permissive/493694849/rtl/AES_128_Encipher_Block.v
data/verilator_xmls/89c7a316-fdaf-416d-b2dc-4d38e9b56c10.xml
function [31:0] mixw;
    input [31:0] w;

    reg [7:0] b0, b1, b2, b3;
    reg [7:0] mb0, mb1, mb2, mb3;





    begin
        b0 = w[31:24];
        b1 = w[23:16];
        b2 = w[15:8];
        b3 = w[7:0];

        mb0 = gm02(b0) ^ gm03(b1) ^ b2 ^ b3;
        mb1 = b0 ^ gm02(b1) ^ gm03(b2) ^ b3;
        mb2 = b0 ^ b1 ^ gm02(b2) ^ gm03(b3);
        mb3 = gm03(b0) ^ b1 ^ b2 ^ gm02(b3);

        mixw = {mb0, mb1, mb2, mb3};
    end
endfunction
function [31:0] mixw;

    input [31:0] w;

    reg [7:0] b0, b1, b2, b3;
    reg [7:0] mb0, mb1, mb2, mb3;





    begin
        b0 = w[31:24];
        b1 = w[23:16];
        b2 = w[15:8];
        b3 = w[7:0];

        mb0 = gm02(b0) ^ gm03(b1) ^ b2 ^ b3;
        mb1 = b0 ^ gm02(b1) ^ gm03(b2) ^ b3;
        mb2 = b0 ^ b1 ^ gm02(b2) ^ gm03(b3);
        mb3 = gm03(b0) ^ b1 ^ b2 ^ gm02(b3);

        mixw = {mb0, mb1, mb2, mb3};
    end
endfunction