data/full_repos/permissive/502135797/Lab10_April_27_2022/Code/UPCOUNT.v
1: b"%Error-ASSIGNIN: data/full_repos/permissive/502135797/Lab10_April_27_2022/Code/UPCOUNT.v:8: Assigning to input/const variable: 'en'\n    assign en = 1; \n           ^~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module UPCOUNT (
    input clk, 
    input rst, 
    input en,
    output reg [3:0] count
    );
    assign en = 1; 
    reg [3:0] tmp = 0;
    always@(posedge rst or posedge clk)
    begin
        if(rst)
            begin
                tmp <= 4'b1111;
            end
        else
            begin
                if(en)
                    begin
                        tmp <= tmp+1;
                    end
            end
        count <= tmp;
    end
endmodule
module UPCOUNT (
    input clk, 
    input rst, 
    input en,
    output reg [3:0] count
    );

    assign en = 1; 
    reg [3:0] tmp = 0;
    always@(posedge rst or posedge clk)
    begin
        if(rst)
            begin
                tmp <= 4'b1111;
            end
        else
            begin
                if(en)
                    begin
                        tmp <= tmp+1;
                    end
            end
        count <= tmp;
    end
endmodule