data/full_repos/permissive/513398397/verilog/BranchComp.v
1: b"%Error: data/full_repos/permissive/513398397/verilog/BranchComp.v:16: Cannot find file containing module: 'COMP32b'\nCOMP32b COMPARE(BrLT, RD1, RD2, BrUn);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/513398397/verilog,data/full_repos/permissive/513398397/COMP32b\n             data/full_repos/permissive/513398397/verilog,data/full_repos/permissive/513398397/COMP32b.v\n             data/full_repos/permissive/513398397/verilog,data/full_repos/permissive/513398397/COMP32b.sv\n             COMP32b\n             COMP32b.v\n             COMP32b.sv\n             obj_dir/COMP32b\n             obj_dir/COMP32b.v\n             obj_dir/COMP32b.sv\n%Error: Exiting due to 1 error(s)\n"
module BranchComp(
    output BrEq, BrLT,
    input [31:0] RD1, RD2,
    input BrUn
);

wire NotEqual;
wire [31:0] XORResult;

assign XORResult = (RD1 ^ RD2);
assign NotEqual = |XORResult;

assign BrEq = ~NotEqual;


COMP32b COMPARE(BrLT, RD1, RD2, BrUn);

endmodule
module BranchComp(
    output BrEq, BrLT,
    input [31:0] RD1, RD2,
    input BrUn
);


wire NotEqual;
wire [31:0] XORResult;

assign XORResult = (RD1 ^ RD2);
assign NotEqual = |XORResult;

assign BrEq = ~NotEqual;


COMP32b COMPARE(BrLT, RD1, RD2, BrUn);

endmodule