data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ALU.v
1: b'%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ALU.v:2: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new,data/full_repos/permissive/433174928/defines.vh\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new,data/full_repos/permissive/433174928/defines.vh.v\n             data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new,data/full_repos/permissive/433174928/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ALU.v:17: Define or directive not defined: \'`ADD\'\n            `ADD: \n            ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ALU.v:17: syntax error, unexpected \':\', expecting endcase\n            `ADD: \n                ^\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ALU.v:19: Define or directive not defined: \'`SUB\'\n            `SUB:\n            ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ALU.v:21: Define or directive not defined: \'`SLL\'\n            `SLL:\n            ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ALU.v:23: Define or directive not defined: \'`SLT\'\n            `SLT:\n            ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ALU.v:25: Define or directive not defined: \'`SLTU\'\n            `SLTU:\n            ^~~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ALU.v:27: Define or directive not defined: \'`XOR\'\n            `XOR:\n            ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ALU.v:29: Define or directive not defined: \'`SRL\'\n            `SRL:\n            ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ALU.v:31: Define or directive not defined: \'`SRA\'\n            `SRA:\n            ^~~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ALU.v:33: Define or directive not defined: \'`OR\'\n            `OR:\n            ^~~\n%Error: data/full_repos/permissive/433174928/Project_Vivado/Project_Vivado.srcs/sources_1/new/ALU.v:35: Define or directive not defined: \'`AND\'\n            `AND:\n            ^~~~\n%Error: Cannot continue\n'
module ALU(
    input wire [31:0] operand1,
    input wire [31:0] operand2,
    input wire [3:0] operation,
    output wire [31:0] ALUresult
    );
    
    reg [31:0] result = 0;
    
    always @(*) begin
        case (operation)
            `ADD: 
                result <= operand1 + operand2;
            `SUB:
                result <= operand1 - operand2;
            `SLL:
                result <= operand1 << operand2[4:0];
            `SLT:
                result <= ($signed(operand1) < $signed(operand2)) ? 1 : 0;
            `SLTU:
                result <= (operand1 < operand2) ? 1 : 0;
            `XOR:
                result <= operand1 ^ operand2;
            `SRL:
                result <= operand1 >> operand2[4:0];
            `SRA:
                result <= $signed(operand1) >>> operand2[4:0];
            `OR:
                result <= operand1 | operand2;
            `AND:
                result <= operand1 & operand2;
            default:    
                result <= result;
        endcase        
    end
    
    assign ALUresult = result;
    
endmodule
module ALU(
    input wire [31:0] operand1,
    input wire [31:0] operand2,
    input wire [3:0] operation,
    output wire [31:0] ALUresult
    );

    
    reg [31:0] result = 0;
    
    always @(*) begin
        case (operation)
            `ADD: 
                result <= operand1 + operand2;
            `SUB:
                result <= operand1 - operand2;
            `SLL:
                result <= operand1 << operand2[4:0];
            `SLT:
                result <= ($signed(operand1) < $signed(operand2)) ? 1 : 0;
            `SLTU:
                result <= (operand1 < operand2) ? 1 : 0;
            `XOR:
                result <= operand1 ^ operand2;
            `SRL:
                result <= operand1 >> operand2[4:0];
            `SRA:
                result <= $signed(operand1) >>> operand2[4:0];
            `OR:
                result <= operand1 | operand2;
            `AND:
                result <= operand1 & operand2;
            default:    
                result <= result;
        endcase        
    end
    
    assign ALUresult = result;
    
endmodule