data/full_repos/permissive/472097485/Lang0/_Not00/TestMe.v
data/verilator_xmls/d136103c-8aaf-48be-821b-63fc79f0f6ba.xml
module TestMe(
    input wire A,
    output wire B
    );

	assign B=!A;

endmodule
module TestMe(
    input wire A,
    output wire B
    );


	assign B=!A;

endmodule