data/full_repos/permissive/426864978/lab3/task3/tb_syn_prga.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task3/tb_syn_prga.sv:20: Unsupported: Ignoring delay on this delayed statement.\n        forever #5 clk = ~clk;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_syn_prga.sv:77: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_syn_prga.sv:82: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_syn_prga.sv:87: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_syn_prga.sv:94: syntax error, unexpected \'@\'\n            @(posedge clk);   \n            ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_syn_prga.sv:98: syntax error, unexpected \'@\'\n            @(posedge clk);   \n            ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_syn_prga.sv:101: syntax error, unexpected \'@\'\n            @(posedge clk);   \n            ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_syn_prga.sv:105: syntax error, unexpected \'@\'\n            @(posedge clk);   \n            ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_syn_prga.sv:107: syntax error, unexpected \'@\'\n            @(posedge clk);   \n            ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_syn_prga.sv:109: syntax error, unexpected \'@\'\n            @(posedge clk);   \n            ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_syn_prga.sv:120: syntax error, unexpected \'@\'\n            @(posedge clk);   \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task3/tb_syn_prga.sv:133: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Error: Exiting due to 10 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_syn_prga();

    logic clk, rst_n, en, rdy, s_wren, pt_wren, err;
    logic [23:0] key;
    logic [7:0] s_addr, s_rddata, s_wrdata, ct_addr, ct_rddata, pt_addr, pt_rddata, pt_wrdata, pad_i;


    logic [7:0] s [255:0];
    logic [7:0] ct [255:0];
    logic [7:0] exp_pt [255:0];
    logic [7:0] pt [255:0];
    logic [7:0] exp_pad [255:0];

    prga dut(.*);

    initial begin
        clk = 1;
        forever #5 clk = ~clk;
    end

    task validator;
        input [31:0] index;
        input exp_rdy;
        input [7:0] exp_s_addr, exp_s_wrdata;
        input exp_s_wren;
        input [7:0] exp_ct_addr, exp_pt_addr, exp_pt_wrdata;
        input exp_pt_wren;
        begin
            $display("CASE %d", index);
            if (tb_syn_prga.dut.rdy !== exp_rdy) begin
                $display("ERROR B: Expected rdy is %d, actual rdy is %d", exp_rdy, tb_syn_prga.dut.rdy);
                err = 1'b1;
            end
            if (tb_syn_prga.dut.s_addr !== exp_s_addr) begin
                $display("ERROR C: Expected s_addr is %d, actual s_addr is %d", exp_s_addr, tb_syn_prga.dut.s_addr);
                err = 1'b1;
            end
            if (tb_syn_prga.dut.s_wrdata !== exp_s_wrdata) begin
                $display("ERROR D: Expected s_wrdata is %d, actual s_wrdata is %d", exp_s_wrdata, tb_syn_prga.dut.s_wrdata);
                err = 1'b1;
            end
            if (tb_syn_prga.dut.s_wren !== exp_s_wren) begin
                $display("ERROR E: Expected s_wren is %d, actual s_wren is %d", exp_s_wren, tb_syn_prga.dut.s_wren);
                err = 1'b1;
            end
            if (tb_syn_prga.dut.ct_addr !== exp_ct_addr) begin
                $display("ERROR F: Expected ct_addr is %d, actual ct_addr is %d", exp_ct_addr, tb_syn_prga.dut.ct_addr);
                err = 1'b1;
            end
            if (tb_syn_prga.dut.pt_addr !== exp_pt_addr) begin
                $display("ERROR G: Expected pt_addr is %d, actual pt_addr is %d", exp_pt_addr, tb_syn_prga.dut.pt_addr);
                err = 1'b1;
            end
            if (tb_syn_prga.dut.pt_wrdata !== exp_pt_wrdata) begin
                $display("ERROR H: Expected pt_wrdata is %d, actual pt_wrdata is %d", exp_pt_wrdata, tb_syn_prga.dut.pt_wrdata);
                err = 1'b1;
            end
            if (tb_syn_prga.dut.pt_wren !== exp_pt_wren) begin
                $display("ERROR I: Expected pt_wren is %d, actual pt_wren is %d", exp_pt_wren, tb_syn_prga.dut.pt_wren);
                err = 1'b1;
            end
        end
    endtask

    initial begin
        err = 0;


        $readmemh("ksa_res.txt", s);
        $readmemh("test1.memh", ct);
        $readmemh("prga_res.txt", exp_pt);


        rst_n = 1'b0; en = 1'b0; key = 24'h1E4600;
        @(negedge clk);
        validator(1, 1'b0, 8'b0, 8'b0, 1'b0, 8'b0, 8'b0, 8'b0, 1'b0);


        rst_n = 1'b1;
        @(posedge clk);
        validator(2, 1'b0, 8'b0, 8'b0, 1'b0, 8'b0, 8'b0, 8'b0, 1'b0);


        en = 1'b1; ct_rddata = ct[0];
        @(posedge clk);
        validator(3, 1'b1, 8'b0, 8'b0, 1'b0, 8'b0, 8'b0, 8'b0, 1'b0);


        en = 1'b0; s_rddata = 8'b0; ct_rddata = 8'b0; pt_rddata = 8'b0;

        for (int i = 0; i < 8'h49; i++) begin
            @(posedge clk);
            @(posedge clk);
            ct_rddata = ct[tb_syn_prga.dut.ct_addr];
            s_rddata = s[tb_syn_prga.dut.s_addr];
            @(posedge clk);
            pad_i = s_rddata;
            s_rddata = s[tb_syn_prga.dut.s_addr + s_rddata];
            @(posedge clk);
            @(posedge clk);
            pad_i += s_rddata;
            s[tb_syn_prga.dut.s_addr] = s_rddata;
            @(posedge clk);
            s[tb_syn_prga.dut.s_addr] = tb_syn_prga.dut.s_wrdata;
            @(posedge clk);
            s_rddata = s[pad_i];
            @(posedge clk);
            @(posedge clk);
        end

        @(posedge clk);
        @(posedge clk);
        validator(6, 1'b0, 8'b0, 8'b0, 1'b0, 8'b0, 8'b0, 8'h49, 1'b1);


        pt[0] = tb_syn_prga.dut.message_length;
        for (int k = 0; k < 8'h49; k++) begin
            @(posedge clk);
            pt[tb_syn_prga.dut.pt_addr] = tb_syn_prga.dut.pt_wrdata;
        end


        for (int i = 0; i < 8'h49; i++) begin
           if (exp_pt[i] !== pt[i + 1]) begin 
                $display("PT MEM[%d] ERROR: Expected pt is %h, actual pt is %h", i[7:0], exp_pt[i], pt[i + 1]);
                err = 1'b1;
            end
        end


        #20;
        if (tb_syn_prga.dut.rdy !== 1'b1) begin
            $display("ERROR 7: Expected rdy is %d, actual rdy is %d", 1'b1, tb_syn_prga.dut.rdy);
            err = 1'b1;
        end






























































        if (~err)
            $display("SUCCESS: All tests passed.");
        $stop;
    end

endmodule
module tb_syn_prga();


    logic clk, rst_n, en, rdy, s_wren, pt_wren, err;
    logic [23:0] key;
    logic [7:0] s_addr, s_rddata, s_wrdata, ct_addr, ct_rddata, pt_addr, pt_rddata, pt_wrdata, pad_i;


    logic [7:0] s [255:0];
    logic [7:0] ct [255:0];
    logic [7:0] exp_pt [255:0];
    logic [7:0] pt [255:0];
    logic [7:0] exp_pad [255:0];

    prga dut(.*);

    initial begin
        clk = 1;
        forever #5 clk = ~clk;
    end

    task validator;
        input [31:0] index;
        input exp_rdy;
        input [7:0] exp_s_addr, exp_s_wrdata;
        input exp_s_wren;
        input [7:0] exp_ct_addr, exp_pt_addr, exp_pt_wrdata;
        input exp_pt_wren;
        begin
            $display("CASE %d", index);
            if (tb_syn_prga.dut.rdy !== exp_rdy) begin
                $display("ERROR B: Expected rdy is %d, actual rdy is %d", exp_rdy, tb_syn_prga.dut.rdy);
                err = 1'b1;
            end
            if (tb_syn_prga.dut.s_addr !== exp_s_addr) begin
                $display("ERROR C: Expected s_addr is %d, actual s_addr is %d", exp_s_addr, tb_syn_prga.dut.s_addr);
                err = 1'b1;
            end
            if (tb_syn_prga.dut.s_wrdata !== exp_s_wrdata) begin
                $display("ERROR D: Expected s_wrdata is %d, actual s_wrdata is %d", exp_s_wrdata, tb_syn_prga.dut.s_wrdata);
                err = 1'b1;
            end
            if (tb_syn_prga.dut.s_wren !== exp_s_wren) begin
                $display("ERROR E: Expected s_wren is %d, actual s_wren is %d", exp_s_wren, tb_syn_prga.dut.s_wren);
                err = 1'b1;
            end
            if (tb_syn_prga.dut.ct_addr !== exp_ct_addr) begin
                $display("ERROR F: Expected ct_addr is %d, actual ct_addr is %d", exp_ct_addr, tb_syn_prga.dut.ct_addr);
                err = 1'b1;
            end
            if (tb_syn_prga.dut.pt_addr !== exp_pt_addr) begin
                $display("ERROR G: Expected pt_addr is %d, actual pt_addr is %d", exp_pt_addr, tb_syn_prga.dut.pt_addr);
                err = 1'b1;
            end
            if (tb_syn_prga.dut.pt_wrdata !== exp_pt_wrdata) begin
                $display("ERROR H: Expected pt_wrdata is %d, actual pt_wrdata is %d", exp_pt_wrdata, tb_syn_prga.dut.pt_wrdata);
                err = 1'b1;
            end
            if (tb_syn_prga.dut.pt_wren !== exp_pt_wren) begin
                $display("ERROR I: Expected pt_wren is %d, actual pt_wren is %d", exp_pt_wren, tb_syn_prga.dut.pt_wren);
                err = 1'b1;
            end
        end
    endtask

    initial begin
        err = 0;


        $readmemh("ksa_res.txt", s);
        $readmemh("test1.memh", ct);
        $readmemh("prga_res.txt", exp_pt);


        rst_n = 1'b0; en = 1'b0; key = 24'h1E4600;
        @(negedge clk);
        validator(1, 1'b0, 8'b0, 8'b0, 1'b0, 8'b0, 8'b0, 8'b0, 1'b0);


        rst_n = 1'b1;
        @(posedge clk);
        validator(2, 1'b0, 8'b0, 8'b0, 1'b0, 8'b0, 8'b0, 8'b0, 1'b0);


        en = 1'b1; ct_rddata = ct[0];
        @(posedge clk);
        validator(3, 1'b1, 8'b0, 8'b0, 1'b0, 8'b0, 8'b0, 8'b0, 1'b0);


        en = 1'b0; s_rddata = 8'b0; ct_rddata = 8'b0; pt_rddata = 8'b0;

        for (int i = 0; i < 8'h49; i++) begin
            @(posedge clk);
            @(posedge clk);
            ct_rddata = ct[tb_syn_prga.dut.ct_addr];
            s_rddata = s[tb_syn_prga.dut.s_addr];
            @(posedge clk);
            pad_i = s_rddata;
            s_rddata = s[tb_syn_prga.dut.s_addr + s_rddata];
            @(posedge clk);
            @(posedge clk);
            pad_i += s_rddata;
            s[tb_syn_prga.dut.s_addr] = s_rddata;
            @(posedge clk);
            s[tb_syn_prga.dut.s_addr] = tb_syn_prga.dut.s_wrdata;
            @(posedge clk);
            s_rddata = s[pad_i];
            @(posedge clk);
            @(posedge clk);
        end

        @(posedge clk);
        @(posedge clk);
        validator(6, 1'b0, 8'b0, 8'b0, 1'b0, 8'b0, 8'b0, 8'h49, 1'b1);


        pt[0] = tb_syn_prga.dut.message_length;
        for (int k = 0; k < 8'h49; k++) begin
            @(posedge clk);
            pt[tb_syn_prga.dut.pt_addr] = tb_syn_prga.dut.pt_wrdata;
        end


        for (int i = 0; i < 8'h49; i++) begin
           if (exp_pt[i] !== pt[i + 1]) begin 
                $display("PT MEM[%d] ERROR: Expected pt is %h, actual pt is %h", i[7:0], exp_pt[i], pt[i + 1]);
                err = 1'b1;
            end
        end


        #20;
        if (tb_syn_prga.dut.rdy !== 1'b1) begin
            $display("ERROR 7: Expected rdy is %d, actual rdy is %d", 1'b1, tb_syn_prga.dut.rdy);
            err = 1'b1;
        end






























































        if (~err)
            $display("SUCCESS: All tests passed.");
        $stop;
    end

endmodule