data/full_repos/permissive/414867793/Universal_Gates/Nor_Gate/NOR_G.v
data/verilator_xmls/12192872-f252-445e-890b-2e68c7c5c9e0.xml
module NOR_G(A,B,C);

input A,B;
output C;

assign C=(~(A|B));


endmodule
module NOR_G(A,B,C);


input A,B;
output C;

assign C=(~(A|B));


endmodule