data/full_repos/permissive/446312960/Verilog_Simulation/10_sr_latch/sr.v
data/verilator_xmls/adbfa0b1-c337-403d-8251-a393299f3101.xml
module sr(R, S, Q, Qb);

input R, S;
output Q, Qb;

reg Q;
assign Qb = ~Q;

always @ ( posedge R  or posedge S ) 
    if  ( R  )
        Q <= 1'b0; 
    else if ( S  )
        Q <= 1'b1;



endmodule
module sr(R, S, Q, Qb);


input R, S;
output Q, Qb;

reg Q;
assign Qb = ~Q;

always @ ( posedge R  or posedge S ) 
    if  ( R  )
        Q <= 1'b0; 
    else if ( S  )
        Q <= 1'b1;



endmodule