data/full_repos/permissive/415491487/design_src/regfile_bus.v
data/verilator_xmls/89743955-4d39-441d-a33a-47438706956b.xml
module regfile_bus(
    input clk,
    input [31:0] op_sel,
    inout [23:0] bus
);

    reg [23:0] regfile[31:0];
    
    always @(posedge clk) begin
        case (op_sel)

            default: begin
                $write("invalid case for regfile_bus!");
            end
        endcase
    end
endmodule
module regfile_bus(
    input clk,
    input [31:0] op_sel,
    inout [23:0] bus
);


    reg [23:0] regfile[31:0];
    
    always @(posedge clk) begin
        case (op_sel)

            default: begin
                $write("invalid case for regfile_bus!");
            end
        endcase
    end
endmodule