data/full_repos/permissive/527176783/Pipeline/PCAdd.v
data/verilator_xmls/5ebee00a-1151-41aa-8892-d8a2a65a22c6.xml
module PCAdd(
    input       [31:0]  pc,
    output      [31:0]  pc_add4
);
    assign pc_add4 = pc + 32'd4;
endmodule
module PCAdd(
    input       [31:0]  pc,
    output      [31:0]  pc_add4
);

    assign pc_add4 = pc + 32'd4;
endmodule