data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v
1: b'%Error: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:3: Cannot find include file: inc/Defines.vh\n`include "inc/Defines.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/521867481/testbench,data/full_repos/permissive/521867481/inc/Defines.vh\n             data/full_repos/permissive/521867481/testbench,data/full_repos/permissive/521867481/inc/Defines.vh.v\n             data/full_repos/permissive/521867481/testbench,data/full_repos/permissive/521867481/inc/Defines.vh.sv\n             inc/Defines.vh\n             inc/Defines.vh.v\n             inc/Defines.vh.sv\n             obj_dir/inc/Defines.vh\n             obj_dir/inc/Defines.vh.v\n             obj_dir/inc/Defines.vh.sv\n%Error: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:4: Cannot find include file: src/Uart8Transmitter.v\n`include "src/Uart8Transmitter.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:8: Define or directive not defined: \'`CLOCK_RATE_100MHZ\'\n parameter CLOCK_RATE   = `CLOCK_RATE_100MHZ;\n                          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:8: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter CLOCK_RATE   = `CLOCK_RATE_100MHZ;\n                                            ^\n%Error: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:9: Define or directive not defined: \'`BAUD_RATE_115200\'\n parameter BAUD_RATE    = `BAUD_RATE_115200;\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:9: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter BAUD_RATE    = `BAUD_RATE_115200;\n                                           ^\n%Error: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:10: Define or directive not defined: \'`DATA_BITS_8\'\n parameter DATA_BITS    = `DATA_BITS_8;\n                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:10: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter DATA_BITS    = `DATA_BITS_8;\n                                      ^\n%Error: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:37: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("test.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:38: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(-1, test);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:43: Define or directive not defined: \'`DATA_BITS_8\'\n   in <= `DATA_BITS_8\'h55;\n         ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX start <= 1\'b1;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX start <= 1\'b0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;  \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;  \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;  \n   ^\n%Error: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:61: Define or directive not defined: \'`DATA_BITS_8\'\n   in <= `DATA_BITS_8\'h96;\n         ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX start <= 1\'b1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX start <= 1\'b0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;  \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;  \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_TX;  \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n  #MAX_RATE_TX txClk = ~txClk;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Transmitter_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n  #25000 $finish;\n  ^\n%Error: Exiting due to 12 error(s), 26 warning(s)\n'
module tbUart8Transmitter();

	parameter CLOCK_RATE   = `CLOCK_RATE_100MHZ;
	parameter BAUD_RATE    = `BAUD_RATE_115200;
	parameter DATA_BITS    = `DATA_BITS_8;

    localparam MAX_RATE_TX = CLOCK_RATE / (2 * BAUD_RATE);
	localparam CLOCK_TX = MAX_RATE_TX * 2;

	reg                   txClk = 0;
	reg                   en    = 1;
	reg                   start = 0;
	reg [DATA_BITS - 1:0] in    = 0;

	wire out;
	wire done;
	wire busy;

	Uart8Transmitter #(
        .DATA_BITS(DATA_BITS)
    ) test (
		.clk(txClk),
        .en(en),
        .start(start),
        .in(in),
        .out(out),
        .done(done),
        .busy(busy)
    );

	initial begin
		$dumpfile("test.vcd");
		$dumpvars(-1, test);
    end

	initial begin
		begin
			in <= `DATA_BITS_8'h55;

			#CLOCK_TX start <= 1'b1;
			#CLOCK_TX start <= 1'b0;

			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
		end

		begin
			in <= `DATA_BITS_8'h96;

			#CLOCK_TX start <= 1'b1;
			#CLOCK_TX start <= 1'b0;

			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
		end
	end

	always begin
		#MAX_RATE_TX txClk = ~txClk;

	end

	initial begin
		#25000 $finish;
	end

endmodule
module tbUart8Transmitter();


	parameter CLOCK_RATE   = `CLOCK_RATE_100MHZ;
	parameter BAUD_RATE    = `BAUD_RATE_115200;
	parameter DATA_BITS    = `DATA_BITS_8;

    localparam MAX_RATE_TX = CLOCK_RATE / (2 * BAUD_RATE);
	localparam CLOCK_TX = MAX_RATE_TX * 2;

	reg                   txClk = 0;
	reg                   en    = 1;
	reg                   start = 0;
	reg [DATA_BITS - 1:0] in    = 0;

	wire out;
	wire done;
	wire busy;

	Uart8Transmitter #(
        .DATA_BITS(DATA_BITS)
    ) test (
		.clk(txClk),
        .en(en),
        .start(start),
        .in(in),
        .out(out),
        .done(done),
        .busy(busy)
    );

	initial begin
		$dumpfile("test.vcd");
		$dumpvars(-1, test);
    end

	initial begin
		begin
			in <= `DATA_BITS_8'h55;

			#CLOCK_TX start <= 1'b1;
			#CLOCK_TX start <= 1'b0;

			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
		end

		begin
			in <= `DATA_BITS_8'h96;

			#CLOCK_TX start <= 1'b1;
			#CLOCK_TX start <= 1'b0;

			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
			#CLOCK_TX;
		end
	end

	always begin
		#MAX_RATE_TX txClk = ~txClk;

	end

	initial begin
		#25000 $finish;
	end

endmodule