data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/ATCKMUX2.v
data/verilator_xmls/6ae61498-e55f-48c1-b71c-8f28243a1731.xml
module ATCKMUX2
    (
     SEL,
     CKIN0,
     CKIN1,
     CKOUT
     );
input SEL;
input CKIN0;
input CKIN1;
output CKOUT;

reg    CKOUT;
always @(CKIN0 or CKIN1 or SEL)
    begin

    CKOUT = SEL ? CKIN1 : CKIN0;
    end
endmodule
module ATCKMUX2
    (
     SEL,
     CKIN0,
     CKIN1,
     CKOUT
     );

input SEL;
input CKIN0;
input CKIN1;
output CKOUT;

reg    CKOUT;
always @(CKIN0 or CKIN1 or SEL)
    begin

    CKOUT = SEL ? CKIN1 : CKIN0;
    end
endmodule