data/full_repos/permissive/437204475/pipeline/cpu.v
1: b'%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:3: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/437204475/pipeline,data/full_repos/permissive/437204475/defines.v\n             data/full_repos/permissive/437204475/pipeline,data/full_repos/permissive/437204475/defines.v.v\n             data/full_repos/permissive/437204475/pipeline,data/full_repos/permissive/437204475/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:6: Define or directive not defined: \'`WORD_WIDTH\'\n    parameter W = `WORD_WIDTH\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:7: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n) (\n^\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:11: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire[W-1:0] pc,\n ^~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:12: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[W-1:0] read_inst,\n ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:14: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire load_clk, load_en,\n    ^~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:15: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire[W-1:0] l_addr,\n    ^~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n input wire[W-1:0] l_data,\n ^~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:18: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire store_clk, store_en,\n ^~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:19: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire[W-1:0] s_addr,\n    ^~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:20: syntax error, unexpected output, expecting IDENTIFIER or do or final\n output wire[W-1:0] s_data\n ^~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:21: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:31: syntax error, unexpected IDENTIFIER\n    pc_assume_not_take pc_inst(\n    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:47: Define or directive not defined: \'`REG_ADDR_W\'\n    wire[`REG_ADDR_W-1:0] rs_addr, rt_addr, rd_addr;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:48: Define or directive not defined: \'`WORD_INDEX_W\'\n    wire[`WORD_INDEX_W-1:0] shamt;\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:53: Define or directive not defined: \'`ALUOP_WIDTH\'\n    wire[`ALUOP_WIDTH-1:0] alu_op;\n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:54: Define or directive not defined: \'`ALU_SRC_WIDTH\'\n    wire[`ALU_SRC_WIDTH-1:0] alu_op1_src, alu_op2_src;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:56: Define or directive not defined: \'`REG_W_SRC_WIDTH\'\n    wire[`REG_W_SRC_WIDTH-1:0] reg_write_src;\n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:57: Define or directive not defined: \'`REG_ADDR_W\'\n    wire[`REG_ADDR_W-1:0] reg_write_addr;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:59: Define or directive not defined: \'`L_S_MODE_W\'\n    wire[`L_S_MODE_W-1:0] l_s_mode;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:66: syntax error, unexpected IDENTIFIER\n    decoder decoder_inst(\n    ^~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:93: Define or directive not defined: \'`REG_ADDR_W\'\n    wire[`REG_ADDR_W-1:0] wb_reg_write_addr;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:95: syntax error, unexpected IDENTIFIER\n    regfile regfile_inst(\n    ^~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:112: syntax error, unexpected IDENTIFIER\n    ctrl_regs #(32) id_ex (\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:114: Define or directive not defined: \'`FALSE\'\n        .stall(`FALSE), .bubble(id_ex_bubble),\n               ^~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:124: syntax error, unexpected IDENTIFIER\n    alu_with_src_mux alu_inst(\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:127: Define or directive not defined: \'`FALSE\'\n        .stall(`FALSE),\n               ^~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:140: Define or directive not defined: \'`L_S_MODE_W\'\n    wire[`L_S_MODE_W-1:0] mem_l_s_mode;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:142: Define or directive not defined: \'`REG_W_SRC_WIDTH\'\n    wire[`REG_W_SRC_WIDTH-1:0] mem_reg_write_src;\n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:143: Define or directive not defined: \'`REG_ADDR_W\'\n    wire[`REG_ADDR_W-1:0] mem_reg_write_addr;\n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:147: syntax error, unexpected IDENTIFIER\n    ctrl_regs #(144) ex_mem (\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:149: Define or directive not defined: \'`FALSE\'\n        .stall(`FALSE), .bubble(`FALSE),  \n               ^~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:149: Define or directive not defined: \'`FALSE\'\n        .stall(`FALSE), .bubble(`FALSE),  \n                                ^~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:168: syntax error, unexpected IDENTIFIER\n    mem mem_inst(\n    ^~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:187: Define or directive not defined: \'`REG_W_SRC_WIDTH\'\n    wire[`REG_W_SRC_WIDTH-1:0] wb_reg_write_src;\n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:193: syntax error, unexpected IDENTIFIER\n    ctrl_regs #(104) mem_wb (\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:195: Define or directive not defined: \'`FALSE\'\n        .stall(`FALSE), .bubble(`FALSE),  \n               ^~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:195: Define or directive not defined: \'`FALSE\'\n        .stall(`FALSE), .bubble(`FALSE),  \n                                ^~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:222: syntax error, unexpected IDENTIFIER\n    forward_detection forward_detection_inst(\n    ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:239: syntax error, unexpected IDENTIFIER\n    alu_forward_mux alu_forward_mux_inst(\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437204475/pipeline/cpu.v:260: syntax error, unexpected IDENTIFIER\n    hazard hazard_inst(\n    ^~~~~~\n%Error: Exiting due to 41 error(s)\n'
module cpu #(
    parameter W = `WORD_WIDTH
) (

	input wire clk, rst,

	output wire[W-1:0] pc,
	input wire[W-1:0] read_inst,

    output wire load_clk, load_en,
    output wire[W-1:0] l_addr,
	input wire[W-1:0] l_data,

	output wire store_clk, store_en,
    output wire[W-1:0] s_addr,
	output wire[W-1:0] s_data
);






    wire pc_stall, pc_flush;
    wire[W-1:0] flush_addr;

    pc_assume_not_take pc_inst(
        .clk(clk), .rst(rst),
        .flush(pc_flush), .stall(pc_stall),
        .flush_addr(flush_addr),

        .pc(pc),
        .read_inst(read_inst),
        .inst(inst)
    );






    wire[W-1:0] inst, rs_val, rt_val, rd_val, imm;
    wire[`REG_ADDR_W-1:0] rs_addr, rt_addr, rd_addr;
    wire[`WORD_INDEX_W-1:0] shamt;

    wire rs_read_en, rt_read_en;

    wire can_branch, jump, targ_else_offset, pc_addr_src_reg;
    wire[`ALUOP_WIDTH-1:0] alu_op;
    wire[`ALU_SRC_WIDTH-1:0] alu_op1_src, alu_op2_src;
    wire reg_write;
    wire[`REG_W_SRC_WIDTH-1:0] reg_write_src;
    wire[`REG_ADDR_W-1:0] reg_write_addr;
    wire mem_read_en, mem_write_en;
    wire[`L_S_MODE_W-1:0] l_s_mode;


    wire id_stall;

    wire id_ex_bubble;

    decoder decoder_inst(
        .clk(clk), .rst(rst),
        .stall(id_stall), .bubble(id_ex_bubble),
        .inst(inst),

        .rs(rs_addr), .rt(rt_addr),
        .imm(imm),
        .rd(rd_addr),
        .shamt(shamt),

        .alu_op(alu_op),
        .alu_op1_src(alu_op1_src),
        .alu_op2_src(alu_op2_src),
        .can_branch(can_branch),
        .jump(jump),
        .targ_else_offset(targ_else_offset),
        .pc_addr_src_reg(pc_addr_src_reg),
        .rs_read_en(rs_read_en), .rt_read_en(rt_read_en), .reg_write(reg_write),
        .reg_write_src(reg_write_src),
        .reg_write_addr(reg_write_addr),
        .mem_read_en(mem_read_en), .mem_write_en(mem_write_en),
        .l_s_mode(l_s_mode)
    );
    

    wire reg_write_en;
    wire[W-1:0] reg_write_data;
    wire[`REG_ADDR_W-1:0] wb_reg_write_addr;

    regfile regfile_inst(
        .clk(clk), .rst(rst),
        .rs_en(rs_read_en),
        .rs_addr(rs_addr),
        .rs_data(rs_val),
        .rt_en(rt_read_en),
        .rt_addr(rt_addr),
        .rt_data(rt_val),
        .write_en(reg_write_en),
        .write_addr(wb_reg_write_addr),
        .write_data(reg_write_data)
    );



    wire[W-1:0] ex_pc;

    ctrl_regs #(32) id_ex (
        .clk(clk), .rst(rst),
        .stall(`FALSE), .bubble(id_ex_bubble),
        .ctrl_in(pc),
        .ctrl_out(ex_pc)
    );



    wire[W-1:0] rs_forward_val, rt_forward_val;
    wire[W-1:0] alu_result;

    alu_with_src_mux alu_inst(
        .clk(clk),

        .stall(`FALSE),
        .alu_op1_src(alu_op1_src), .alu_op2_src(alu_op2_src),
        .rs_val(rs_forward_val), .rt_val(rt_forward_val), .imm(imm), .pc(ex_pc),
        .alu_op(alu_op),
        .result(alu_result)
    );




    wire mem_can_branch, mem_targ_else_offset, mem_pc_addr_src_reg;

    wire mem_mem_read_en, mem_mem_write_en;
    wire[`L_S_MODE_W-1:0] mem_l_s_mode;
    wire mem_reg_write;
    wire[`REG_W_SRC_WIDTH-1:0] mem_reg_write_src;
    wire[`REG_ADDR_W-1:0] mem_reg_write_addr;

    wire[W-1:0] mem_pc, mem_imm, mem_rs_val, mem_rt_val;

    ctrl_regs #(144) ex_mem (
        .clk(clk), .rst(rst),
        .stall(`FALSE), .bubble(`FALSE),
        .ctrl_in({
            can_branch, targ_else_offset, pc_addr_src_reg,
            mem_read_en, mem_write_en, l_s_mode,
            reg_write, reg_write_src, reg_write_addr,
            ex_pc, imm, rs_val, rt_forward_val
        }),
        .ctrl_out({
            mem_can_branch, mem_targ_else_offset, mem_pc_addr_src_reg,
            mem_mem_read_en, mem_mem_write_en, mem_l_s_mode,
            mem_reg_write, mem_reg_write_src, mem_reg_write_addr,
            mem_pc, mem_imm, mem_rs_val, mem_rt_val
        })
    );



    wire[W-1:0] mem_write_data, mem_read_data;

    mem mem_inst(
        .clk(clk), .rst(rst),

        .mem_read_en(mem_mem_read_en), .mem_write_en(mem_mem_write_en),
        .mem_addr(alu_result),
        .l_s_mode(mem_l_s_mode),
        .mem_write_data(mem_rt_val), .mem_read_data(mem_read_data),

        .load_en(load_en),
        .l_addr(l_addr),
        .l_data(l_data),
        .store_en(store_en),
        .s_addr(s_addr),
        .s_data(s_data)
    );



    wire wb_reg_write;
    wire[`REG_W_SRC_WIDTH-1:0] wb_reg_write_src;



    wire[W-1:0] wb_pc, wb_imm, wb_alu_result;

    ctrl_regs #(104) mem_wb (
        .clk(clk), .rst(rst),
        .stall(`FALSE), .bubble(`FALSE),
        .ctrl_in({
            mem_reg_write, mem_reg_write_src, mem_reg_write_addr,
            mem_pc, mem_imm, alu_result
        }),
        .ctrl_out({
            wb_reg_write, wb_reg_write_src, wb_reg_write_addr,
            wb_pc, wb_imm, wb_alu_result
        })
    );




    writeback wb_inst(
        .reg_write(wb_reg_write),
        .alu_result(wb_alu_result), .mem_data(mem_read_data), .pc(wb_pc), .imm(wb_imm),
        .reg_write_src(wb_reg_write_src),

        .write_en(reg_write_en),
        .reg_write_data(reg_write_data)
    );



    wire ex_rs_forward, ex_rt_forward, mem_rs_forward, mem_rt_forward;

    forward_detection forward_detection_inst(
        .idex_rs_reg_read(rs_read_en), .idex_rt_reg_read(rt_read_en),
        .idex_rs_addr(rs_addr), .idex_rt_addr(rt_addr),

        .exmem_reg_write(mem_reg_write),
        .exmem_reg_write_addr(mem_reg_write_addr),
        .ex_rs_forward(ex_rs_forward), .ex_rt_forward(ex_rt_forward),

        .memwb_reg_write(wb_reg_write),
        .memwb_reg_write_addr(wb_reg_write_addr),
        .mem_rs_forward(mem_rs_forward), .mem_rt_forward(mem_rt_forward)
    );



    wire mem_ex_hazard;

    alu_forward_mux alu_forward_mux_inst(

        .rs_val(rs_val), .rt_val(rt_val),

        .mem_alu_result(alu_result), .mem_pc(mem_pc), .mem_imm(mem_imm),
        .mem_reg_write_src(mem_reg_write_src),

        .wb_alu_result(wb_alu_result), .mem_read_data(mem_read_data), .wb_pc(wb_pc), .wb_imm(wb_imm),
        .wb_reg_write_src(wb_reg_write_src),

        .ex_rs_forward(ex_rs_forward), .ex_rt_forward(ex_rt_forward),
        .mem_rs_forward(mem_rs_forward), .mem_rt_forward(mem_rt_forward),

        .rs_forward_val(rs_forward_val), .rt_forward_val(rt_forward_val),
        .mem_ex_hazard(mem_ex_hazard)
    );



    wire j_ctrl_hazard, branch_ctrl_hazard;

    hazard hazard_inst(
        .rst(rst),
        .mem_ex_hazard(mem_ex_hazard),
        .j_ctrl_hazard(j_ctrl_hazard),
        .branch_ctrl_hazard(branch_ctrl_hazard),
        .pc_stall(pc_stall),
        .pc_flush(pc_flush),
        .id_stall(id_stall),
        .id_ex_bubble(id_ex_bubble)
    );

    ctrl_hazard_detect_assume_not_take ctrl_hazard_inst(
        .exmem_can_branch(mem_can_branch),
        .exmem_branch_take(alu_result[0]),
        .idex_jump(jump),
        .j_ctrl_hazard(j_ctrl_hazard),
        .branch_ctrl_hazard(branch_ctrl_hazard)
    );
    
    flush_addr_gen flush_addr_gen_inst(
        .j_ctrl_hazard(j_ctrl_hazard),
        .branch_ctrl_hazard(branch_ctrl_hazard),

        .idex_pc(ex_pc), .exmem_pc(mem_pc),
        .idex_targ_else_offset(targ_else_offset), .exmem_targ_else_offset(mem_targ_else_offset),

        .idex_pc_addr_src_reg(pc_addr_src_reg),
        .idex_rs_val(rs_val),
        .idex_imm(imm),
        
        .exmem_pc_addr_src_reg(mem_pc_addr_src_reg),
        .exmem_rs_val(mem_rs_val),
        .exmem_imm(mem_imm),

        .flush_addr(flush_addr)
    );
endmodule
module cpu #(
    parameter W = `WORD_WIDTH
) (

	input wire clk, rst,

	output wire[W-1:0] pc,
	input wire[W-1:0] read_inst,

    output wire load_clk, load_en,
    output wire[W-1:0] l_addr,
	input wire[W-1:0] l_data,

	output wire store_clk, store_en,
    output wire[W-1:0] s_addr,
	output wire[W-1:0] s_data
);







    wire pc_stall, pc_flush;
    wire[W-1:0] flush_addr;

    pc_assume_not_take pc_inst(
        .clk(clk), .rst(rst),
        .flush(pc_flush), .stall(pc_stall),
        .flush_addr(flush_addr),

        .pc(pc),
        .read_inst(read_inst),
        .inst(inst)
    );






    wire[W-1:0] inst, rs_val, rt_val, rd_val, imm;
    wire[`REG_ADDR_W-1:0] rs_addr, rt_addr, rd_addr;
    wire[`WORD_INDEX_W-1:0] shamt;

    wire rs_read_en, rt_read_en;

    wire can_branch, jump, targ_else_offset, pc_addr_src_reg;
    wire[`ALUOP_WIDTH-1:0] alu_op;
    wire[`ALU_SRC_WIDTH-1:0] alu_op1_src, alu_op2_src;
    wire reg_write;
    wire[`REG_W_SRC_WIDTH-1:0] reg_write_src;
    wire[`REG_ADDR_W-1:0] reg_write_addr;
    wire mem_read_en, mem_write_en;
    wire[`L_S_MODE_W-1:0] l_s_mode;


    wire id_stall;

    wire id_ex_bubble;

    decoder decoder_inst(
        .clk(clk), .rst(rst),
        .stall(id_stall), .bubble(id_ex_bubble),
        .inst(inst),

        .rs(rs_addr), .rt(rt_addr),
        .imm(imm),
        .rd(rd_addr),
        .shamt(shamt),

        .alu_op(alu_op),
        .alu_op1_src(alu_op1_src),
        .alu_op2_src(alu_op2_src),
        .can_branch(can_branch),
        .jump(jump),
        .targ_else_offset(targ_else_offset),
        .pc_addr_src_reg(pc_addr_src_reg),
        .rs_read_en(rs_read_en), .rt_read_en(rt_read_en), .reg_write(reg_write),
        .reg_write_src(reg_write_src),
        .reg_write_addr(reg_write_addr),
        .mem_read_en(mem_read_en), .mem_write_en(mem_write_en),
        .l_s_mode(l_s_mode)
    );
    

    wire reg_write_en;
    wire[W-1:0] reg_write_data;
    wire[`REG_ADDR_W-1:0] wb_reg_write_addr;

    regfile regfile_inst(
        .clk(clk), .rst(rst),
        .rs_en(rs_read_en),
        .rs_addr(rs_addr),
        .rs_data(rs_val),
        .rt_en(rt_read_en),
        .rt_addr(rt_addr),
        .rt_data(rt_val),
        .write_en(reg_write_en),
        .write_addr(wb_reg_write_addr),
        .write_data(reg_write_data)
    );



    wire[W-1:0] ex_pc;

    ctrl_regs #(32) id_ex (
        .clk(clk), .rst(rst),
        .stall(`FALSE), .bubble(id_ex_bubble),
        .ctrl_in(pc),
        .ctrl_out(ex_pc)
    );



    wire[W-1:0] rs_forward_val, rt_forward_val;
    wire[W-1:0] alu_result;

    alu_with_src_mux alu_inst(
        .clk(clk),

        .stall(`FALSE),
        .alu_op1_src(alu_op1_src), .alu_op2_src(alu_op2_src),
        .rs_val(rs_forward_val), .rt_val(rt_forward_val), .imm(imm), .pc(ex_pc),
        .alu_op(alu_op),
        .result(alu_result)
    );




    wire mem_can_branch, mem_targ_else_offset, mem_pc_addr_src_reg;

    wire mem_mem_read_en, mem_mem_write_en;
    wire[`L_S_MODE_W-1:0] mem_l_s_mode;
    wire mem_reg_write;
    wire[`REG_W_SRC_WIDTH-1:0] mem_reg_write_src;
    wire[`REG_ADDR_W-1:0] mem_reg_write_addr;

    wire[W-1:0] mem_pc, mem_imm, mem_rs_val, mem_rt_val;

    ctrl_regs #(144) ex_mem (
        .clk(clk), .rst(rst),
        .stall(`FALSE), .bubble(`FALSE),
        .ctrl_in({
            can_branch, targ_else_offset, pc_addr_src_reg,
            mem_read_en, mem_write_en, l_s_mode,
            reg_write, reg_write_src, reg_write_addr,
            ex_pc, imm, rs_val, rt_forward_val
        }),
        .ctrl_out({
            mem_can_branch, mem_targ_else_offset, mem_pc_addr_src_reg,
            mem_mem_read_en, mem_mem_write_en, mem_l_s_mode,
            mem_reg_write, mem_reg_write_src, mem_reg_write_addr,
            mem_pc, mem_imm, mem_rs_val, mem_rt_val
        })
    );



    wire[W-1:0] mem_write_data, mem_read_data;

    mem mem_inst(
        .clk(clk), .rst(rst),

        .mem_read_en(mem_mem_read_en), .mem_write_en(mem_mem_write_en),
        .mem_addr(alu_result),
        .l_s_mode(mem_l_s_mode),
        .mem_write_data(mem_rt_val), .mem_read_data(mem_read_data),

        .load_en(load_en),
        .l_addr(l_addr),
        .l_data(l_data),
        .store_en(store_en),
        .s_addr(s_addr),
        .s_data(s_data)
    );



    wire wb_reg_write;
    wire[`REG_W_SRC_WIDTH-1:0] wb_reg_write_src;



    wire[W-1:0] wb_pc, wb_imm, wb_alu_result;

    ctrl_regs #(104) mem_wb (
        .clk(clk), .rst(rst),
        .stall(`FALSE), .bubble(`FALSE),
        .ctrl_in({
            mem_reg_write, mem_reg_write_src, mem_reg_write_addr,
            mem_pc, mem_imm, alu_result
        }),
        .ctrl_out({
            wb_reg_write, wb_reg_write_src, wb_reg_write_addr,
            wb_pc, wb_imm, wb_alu_result
        })
    );




    writeback wb_inst(
        .reg_write(wb_reg_write),
        .alu_result(wb_alu_result), .mem_data(mem_read_data), .pc(wb_pc), .imm(wb_imm),
        .reg_write_src(wb_reg_write_src),

        .write_en(reg_write_en),
        .reg_write_data(reg_write_data)
    );



    wire ex_rs_forward, ex_rt_forward, mem_rs_forward, mem_rt_forward;

    forward_detection forward_detection_inst(
        .idex_rs_reg_read(rs_read_en), .idex_rt_reg_read(rt_read_en),
        .idex_rs_addr(rs_addr), .idex_rt_addr(rt_addr),

        .exmem_reg_write(mem_reg_write),
        .exmem_reg_write_addr(mem_reg_write_addr),
        .ex_rs_forward(ex_rs_forward), .ex_rt_forward(ex_rt_forward),

        .memwb_reg_write(wb_reg_write),
        .memwb_reg_write_addr(wb_reg_write_addr),
        .mem_rs_forward(mem_rs_forward), .mem_rt_forward(mem_rt_forward)
    );



    wire mem_ex_hazard;

    alu_forward_mux alu_forward_mux_inst(

        .rs_val(rs_val), .rt_val(rt_val),

        .mem_alu_result(alu_result), .mem_pc(mem_pc), .mem_imm(mem_imm),
        .mem_reg_write_src(mem_reg_write_src),

        .wb_alu_result(wb_alu_result), .mem_read_data(mem_read_data), .wb_pc(wb_pc), .wb_imm(wb_imm),
        .wb_reg_write_src(wb_reg_write_src),

        .ex_rs_forward(ex_rs_forward), .ex_rt_forward(ex_rt_forward),
        .mem_rs_forward(mem_rs_forward), .mem_rt_forward(mem_rt_forward),

        .rs_forward_val(rs_forward_val), .rt_forward_val(rt_forward_val),
        .mem_ex_hazard(mem_ex_hazard)
    );



    wire j_ctrl_hazard, branch_ctrl_hazard;

    hazard hazard_inst(
        .rst(rst),
        .mem_ex_hazard(mem_ex_hazard),
        .j_ctrl_hazard(j_ctrl_hazard),
        .branch_ctrl_hazard(branch_ctrl_hazard),
        .pc_stall(pc_stall),
        .pc_flush(pc_flush),
        .id_stall(id_stall),
        .id_ex_bubble(id_ex_bubble)
    );

    ctrl_hazard_detect_assume_not_take ctrl_hazard_inst(
        .exmem_can_branch(mem_can_branch),
        .exmem_branch_take(alu_result[0]),
        .idex_jump(jump),
        .j_ctrl_hazard(j_ctrl_hazard),
        .branch_ctrl_hazard(branch_ctrl_hazard)
    );
    
    flush_addr_gen flush_addr_gen_inst(
        .j_ctrl_hazard(j_ctrl_hazard),
        .branch_ctrl_hazard(branch_ctrl_hazard),

        .idex_pc(ex_pc), .exmem_pc(mem_pc),
        .idex_targ_else_offset(targ_else_offset), .exmem_targ_else_offset(mem_targ_else_offset),

        .idex_pc_addr_src_reg(pc_addr_src_reg),
        .idex_rs_val(rs_val),
        .idex_imm(imm),
        
        .exmem_pc_addr_src_reg(mem_pc_addr_src_reg),
        .exmem_rs_val(mem_rs_val),
        .exmem_imm(mem_imm),

        .flush_addr(flush_addr)
    );
endmodule