data/full_repos/permissive/472097485/Chu03/FpG8er_04/FpG8er.v
data/verilator_xmls/b41e749e-ab3e-4905-90c3-eb382545d0ff.xml
module FpG8er( input [12:0] a, input [12:0] b, output reg g );

always @*
begin
	if( a[12] )
		g = b[12] ? a[11:0] < b[11:0] : 0;
	else
		g = b[12] ? 1 : a[11:0] > b[11:0];
end

endmodule
module FpG8er( input [12:0] a, input [12:0] b, output reg g );


always @*
begin
	if( a[12] )
		g = b[12] ? a[11:0] < b[11:0] : 0;
	else
		g = b[12] ? 1 : a[11:0] > b[11:0];
end

endmodule