data/full_repos/permissive/509809169/Circuits/Sequential Logic/Latches and Flip Flops/Dual edge triggered FF.v
1: b'%Error: Cannot find file containing module: Logic/Latches\n        ... Looked in:\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Latches\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Latches.v\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Latches.sv\n             Logic/Latches\n             Logic/Latches.v\n             Logic/Latches.sv\n             obj_dir/Logic/Latches\n             obj_dir/Logic/Latches.v\n             obj_dir/Logic/Latches.sv\n%Error: Cannot find file containing module: and\n%Error: Cannot find file containing module: Flip\n%Error: Cannot find file containing module: Flops,data/full_repos/permissive/509809169\n%Error: Cannot find file containing module: data/full_repos/permissive/509809169/Circuits/Sequential\n%Error: Cannot find file containing module: Flops/Dual\n%Error: Cannot find file containing module: edge\n%Error: Cannot find file containing module: triggered\n%Error: Cannot find file containing module: FF.v\n%Error: Exiting due to 9 error(s)\n'
module top_module (
    input clk,
    input d,
    output q
);
    reg r1,r2;
    always @(posedge clk)
        r1<=d;
    always @(negedge clk)
        r2<=d;
    always @(clk) begin
		if(clk)
			q = r1;
		else
			q = r2;
	 end 
endmodule
module top_module (
    input clk,
    input d,
    output q
);

    reg r1,r2;
    always @(posedge clk)
        r1<=d;
    always @(negedge clk)
        r2<=d;
    always @(clk) begin
		if(clk)
			q = r1;
		else
			q = r2;
	 end 
endmodule