data/full_repos/permissive/458870430/rtl/downloader.sv
1: b"%Error: data/full_repos/permissive/458870430/rtl/downloader.sv:63: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'ROM_START_ADDR'\n                                                                 : ... In instance downloader\nparameter ROM_START_ADDR;    \n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458870430/rtl/downloader.sv:64: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'PRG_START_ADDR'\n                                                                 : ... In instance downloader\nparameter PRG_START_ADDR;    \n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458870430/rtl/downloader.sv:65: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'PTR_PROGND'\n                                                                 : ... In instance downloader\nparameter PTR_PROGND;        \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458870430/rtl/downloader.sv:66: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'PTR_END_BASE'\n                                                                 : ... In instance downloader\nparameter PTR_END_BASE;      \n          ^~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module downloader (	


   input SPI_DO,
	input SPI_DI,
   input SPI_SCK,
   input SPI_SS2,
   input SPI_SS3,
   input SPI_SS4,
	
	input 			   clk,
	input             clk_ena,
	output reg        wr,
	output reg [24:0] addr,
	output reg [7:0]  data,

	output reg        downloading,
	output            ROM_done
);

wire        dio_dowloading;
wire [7:0]  dio_index;      
wire        dio_wr;
wire [24:0] dio_addr;
wire [7:0]  dio_data;

data_io data_io (
	.clk_sys ( clk      ),
	.clkref_n( ~clk_ena ),
	

	.SPI_SCK( SPI_SCK ),
	.SPI_SS2( SPI_SS2 ),
	.SPI_SS4( SPI_SS4 ),
	.SPI_DI ( SPI_DI  ),
	.SPI_DO ( SPI_DO  ), 	  
	
	.ioctl_download ( dio_dowloading ),
	.ioctl_index    ( dio_index      ),
   .ioctl_addr     ( dio_addr       ),
   .ioctl_dout     ( dio_data       ),
	.ioctl_wr       ( dio_wr         )
);

assign ROM_done = ROM_loaded;

reg ROM_loaded = 0;

reg dio_dowloading_old = 0;
reg [2:0] state = 0;   






wire menu_index      = dio_index[5:0];
wire extension_index = dio_index[7:6];

wire is_rom_download = menu_index == 0;
wire is_prg_download = menu_index == 1;

parameter ROM_START_ADDR;
parameter PRG_START_ADDR;
parameter PTR_PROGND;
parameter PTR_END_BASE;

wire [24:0] PRG_END_ADDR     = PRG_START_ADDR + dio_addr;
wire [15:0] PTR_PROGND_VALUE = PTR_END_BASE + dio_addr + 1;


always @(posedge clk) begin	
	

	dio_dowloading_old <= dio_dowloading;	
		
	if(dio_dowloading == 1) begin

		downloading <= 1;
		wr          <= dio_wr;
		data        <= dio_data;
		state       <= 0;
		
		     if(is_rom_download) addr <= ROM_START_ADDR + dio_addr;				
		else if(is_prg_download) addr <= PRG_START_ADDR + dio_addr;		
								
	end
	else if(dio_dowloading_old == 1 && dio_dowloading == 0) begin

		if(is_prg_download) state <= 1;
		else                state <= 3;
		
		wr <= 0;
	end 
	else if(dio_dowloading == 0 && dio_dowloading_old == 0) begin
		if(state == 1) begin

			wr    <= 1;
			addr  <= PTR_PROGND;
			data  <= PTR_PROGND_VALUE[ 7:0];
			state <= 2;			
		end
		if(state == 2) begin

			wr    <= 1;
			addr  <= PTR_PROGND+1;
			data  <= PTR_PROGND_VALUE[15:8];
			state <= 3;			
		end
		if(state == 3) begin

			wr    <= 0;			
			state <= 4;
			if(is_rom_download) ROM_loaded <= 1;
		end		
		if(state == 4) begin

			state <= 5;			
		end		
		if(state == 5) begin

			downloading <= 0;			
			state       <= 0;			
		end		
	end	
end

endmodule
module downloader (	


   input SPI_DO,
	input SPI_DI,
   input SPI_SCK,
   input SPI_SS2,
   input SPI_SS3,
   input SPI_SS4,
	
	input 			   clk,
	input             clk_ena,
	output reg        wr,
	output reg [24:0] addr,
	output reg [7:0]  data,

	output reg        downloading,
	output            ROM_done
);


wire        dio_dowloading;
wire [7:0]  dio_index;      
wire        dio_wr;
wire [24:0] dio_addr;
wire [7:0]  dio_data;

data_io data_io (
	.clk_sys ( clk      ),
	.clkref_n( ~clk_ena ),
	

	.SPI_SCK( SPI_SCK ),
	.SPI_SS2( SPI_SS2 ),
	.SPI_SS4( SPI_SS4 ),
	.SPI_DI ( SPI_DI  ),
	.SPI_DO ( SPI_DO  ), 	  
	
	.ioctl_download ( dio_dowloading ),
	.ioctl_index    ( dio_index      ),
   .ioctl_addr     ( dio_addr       ),
   .ioctl_dout     ( dio_data       ),
	.ioctl_wr       ( dio_wr         )
);

assign ROM_done = ROM_loaded;

reg ROM_loaded = 0;

reg dio_dowloading_old = 0;
reg [2:0] state = 0;   






wire menu_index      = dio_index[5:0];
wire extension_index = dio_index[7:6];

wire is_rom_download = menu_index == 0;
wire is_prg_download = menu_index == 1;

parameter ROM_START_ADDR;
parameter PRG_START_ADDR;
parameter PTR_PROGND;
parameter PTR_END_BASE;

wire [24:0] PRG_END_ADDR     = PRG_START_ADDR + dio_addr;
wire [15:0] PTR_PROGND_VALUE = PTR_END_BASE + dio_addr + 1;


always @(posedge clk) begin	
	

	dio_dowloading_old <= dio_dowloading;	
		
	if(dio_dowloading == 1) begin

		downloading <= 1;
		wr          <= dio_wr;
		data        <= dio_data;
		state       <= 0;
		
		     if(is_rom_download) addr <= ROM_START_ADDR + dio_addr;				
		else if(is_prg_download) addr <= PRG_START_ADDR + dio_addr;		
								
	end
	else if(dio_dowloading_old == 1 && dio_dowloading == 0) begin

		if(is_prg_download) state <= 1;
		else                state <= 3;
		
		wr <= 0;
	end 
	else if(dio_dowloading == 0 && dio_dowloading_old == 0) begin
		if(state == 1) begin

			wr    <= 1;
			addr  <= PTR_PROGND;
			data  <= PTR_PROGND_VALUE[ 7:0];
			state <= 2;			
		end
		if(state == 2) begin

			wr    <= 1;
			addr  <= PTR_PROGND+1;
			data  <= PTR_PROGND_VALUE[15:8];
			state <= 3;			
		end
		if(state == 3) begin

			wr    <= 0;			
			state <= 4;
			if(is_rom_download) ROM_loaded <= 1;
		end		
		if(state == 4) begin

			state <= 5;			
		end		
		if(state == 5) begin

			downloading <= 0;			
			state       <= 0;			
		end		
	end	
end

endmodule