data/full_repos/permissive/460328193/ipa_proj_seq/Memory_tb.v
1: b'%Error: data/full_repos/permissive/460328193/ipa_proj_seq/Memory_tb.v:1: Cannot find include file: Memory.v\n`include"Memory.v" \n        ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/460328193/ipa_proj_seq,data/full_repos/permissive/460328193/Memory.v\n             data/full_repos/permissive/460328193/ipa_proj_seq,data/full_repos/permissive/460328193/Memory.v.v\n             data/full_repos/permissive/460328193/ipa_proj_seq,data/full_repos/permissive/460328193/Memory.v.sv\n             Memory.v\n             Memory.v.v\n             Memory.v.sv\n             obj_dir/Memory.v\n             obj_dir/Memory.v.v\n             obj_dir/Memory.v.sv\n%Error: data/full_repos/permissive/460328193/ipa_proj_seq/Memory_tb.v:19: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("Memory.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/460328193/ipa_proj_seq/Memory_tb.v:20: Unsupported or unknown PLI call: $dumpvars\n     $dumpvars(0,icode,valE,valA,valP,instr_valid,valM,clk,stat,imem_error);\n     ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/460328193/ipa_proj_seq/Memory_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/460328193/ipa_proj_seq/Memory_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module testbench;
reg [3:0] icode;
reg [63:0] valE;
reg [63:0] valP;
reg clk;
reg imem_error=1'b0;
reg instr_valid=1'b1;
reg [63:0] valA;
wire [63:0] valM;
wire [1:0]stat;


	integer i,k,j;
	Memory DUT(icode,valE,valA,valP,instr_valid,imem_error,valM,clk,stat);
	initial begin

	$dumpfile("Memory.vcd");
    	$dumpvars(0,icode,valE,valA,valP,instr_valid,valM,clk,stat,imem_error);
	clk=0;
	icode=4'h4;
	valE='h6;
	valP='h312;


	for(j=0;j<4;j++) begin 
	valE=j+'h10;
	valA=j+1;
	clk=1;
	#10;
	clk=0;
	#10;
	end


end
endmodule
module testbench;

reg [3:0] icode;
reg [63:0] valE;
reg [63:0] valP;
reg clk;
reg imem_error=1'b0;
reg instr_valid=1'b1;
reg [63:0] valA;
wire [63:0] valM;
wire [1:0]stat;


	integer i,k,j;
	Memory DUT(icode,valE,valA,valP,instr_valid,imem_error,valM,clk,stat);
	initial begin

	$dumpfile("Memory.vcd");
    	$dumpvars(0,icode,valE,valA,valP,instr_valid,valM,clk,stat,imem_error);
	clk=0;
	icode=4'h4;
	valE='h6;
	valP='h312;


	for(j=0;j<4;j++) begin 
	valE=j+'h10;
	valA=j+1;
	clk=1;
	#10;
	clk=0;
	#10;
	end


end
endmodule