data/full_repos/permissive/447283927/ALU.v
1: b'%Warning-WIDTH: data/full_repos/permissive/447283927/ALU.v:18: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s EQ generates 1 bits.\n                                                             : ... In instance ALU\n            4\'d13: Result = A==B;  \n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/447283927/ALU.v:19: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s NEQ generates 1 bits.\n                                                             : ... In instance ALU\n            4\'d14: Result = A!=B;  \n                          ^\n%Error: Exiting due to 2 warning(s)\n'
module ALU(output reg [31:0] Result,output reg alu_z,input [31:0] A,input [31:0] B,input [3:0] Function);
	always @ (Function,A,B) begin
        case (Function)
            4'd00: Result = A+B;
            4'd01: Result = A-B;
            4'd02: Result = A+B;
            4'd03: Result = A*B;
            4'd04: Result = A/B;
            4'd05: Result = A%B;
            4'd06: Result = A<<B;
            4'd07: Result = A>>B;
            4'd08: Result = A&B;
            4'd09: Result = A|B;
            4'd10: Result = A^B;
            4'd11: Result = A+B;
            4'd12: Result = A+B;
            4'd13: Result = A==B;
            4'd14: Result = A!=B;
            default: Result = A+B;
        endcase
    alu_z = Result==0;
    end
	
endmodule
module ALU(output reg [31:0] Result,output reg alu_z,input [31:0] A,input [31:0] B,input [3:0] Function);

	always @ (Function,A,B) begin
        case (Function)
            4'd00: Result = A+B;
            4'd01: Result = A-B;
            4'd02: Result = A+B;
            4'd03: Result = A*B;
            4'd04: Result = A/B;
            4'd05: Result = A%B;
            4'd06: Result = A<<B;
            4'd07: Result = A>>B;
            4'd08: Result = A&B;
            4'd09: Result = A|B;
            4'd10: Result = A^B;
            4'd11: Result = A+B;
            4'd12: Result = A+B;
            4'd13: Result = A==B;
            4'd14: Result = A!=B;
            default: Result = A+B;
        endcase
    alu_z = Result==0;
    end
	
endmodule