data/full_repos/permissive/47037127/cpu_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/47037127/cpu_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk<=!clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/47037127/cpu_tb.v:45: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("cpu.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/47037127/cpu_tb.v:46: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/47037127/cpu_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #4096 $finish;\n  ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cpu_tb();

reg clk;
wire [31:0] addr;
wire [15:0] memOut;
wire memWrite;
wire memReady;

wire [15:0] memDat;


reg [15:0] memoryArray[511:0]; 
reg [3:0] memSel;

wire [8:0] realAddr=addr%512;
assign memDat=memoryArray[realAddr];


cpu cp(clk, memDat, memReady, addr, memOut, memWrite);


initial begin

  clk=0;
  memSel=0;
  $readmemb("memory.list", memoryArray);
end

always begin
  #1 clk<=!clk;
  if(clk) begin
    if(memWrite) begin
      memoryArray[realAddr]<=memOut;
    end
      



  end
end

initial begin
  $dumpfile("cpu.vcd");
  $dumpvars;
end

initial 
  #4096 $finish;
  
  
endmodule
module cpu_tb();


reg clk;
wire [31:0] addr;
wire [15:0] memOut;
wire memWrite;
wire memReady;

wire [15:0] memDat;


reg [15:0] memoryArray[511:0]; 
reg [3:0] memSel;

wire [8:0] realAddr=addr%512;
assign memDat=memoryArray[realAddr];


cpu cp(clk, memDat, memReady, addr, memOut, memWrite);


initial begin

  clk=0;
  memSel=0;
  $readmemb("memory.list", memoryArray);
end

always begin
  #1 clk<=!clk;
  if(clk) begin
    if(memWrite) begin
      memoryArray[realAddr]<=memOut;
    end
      



  end
end

initial begin
  $dumpfile("cpu.vcd");
  $dumpvars;
end

initial 
  #4096 $finish;
  
  
endmodule