data/full_repos/permissive/458737381/src/verilog-parser/tests/dbginit_inst.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dbginit_inst.v:134: syntax error, unexpected '@'\n  @(posedge clk);\n  ^\n%Error: Exiting due to 1 error(s)\n"
module dbginit_inst (
 rst,
 clk,
 dbginit,
 actual,
 expected,
 cnt_val,
 mon_num

);

   parameter CMP_SZ = 1;


  input rst;
  input clk;
  input dbginit;
  input [CMP_SZ-1:0]  actual;
  input [CMP_SZ-1:0]  expected;
  input [10:0] cnt_val;
  input [31:0] mon_num;

  reg same;
  reg sig_same;
  reg diff;
  reg [31:0]  cntr;
  reg check_done;
  reg start_mon;

initial 
 begin 
  same = 0;
  diff = 0;
  cntr = 0;
  check_done = 0;
  sig_same  = 0;
  start_mon  = 0;
 end

always @(dbginit)
begin
if ( !$test$plusargs("dbginit_mon_off")) begin

if (rst & !dbginit) begin 
 same <= 0;
 diff <= 0;
 start_mon <= 1;
 
 if (actual == expected)
  same <= 1;
 else 
  diff <= 1;
end else begin 
 same <= 0;
 diff <= 0;
 start_mon <= 0;

end

end
end

always @(posedge clk)
begin
if ( !$test$plusargs("dbginit_mon_off")) begin

if (rst & start_mon) begin 
  cntr <= (!dbginit) ?  cntr +1 : 0;
 if ((cntr == cnt_val) & !check_done) begin 
   check_done <= 1;

     if ((actual != expected) && (!sig_same)) begin 
        $display("ERROR : Signal value not as expected after dbginit ; expected= %h ,actual=%h \n", expected,actual);
        finish_test("RTL doesnt reset signals on DBGINIT", mon_num);
     end else begin 
       if (same == 1'b1) 
        $display("****NOTE : Value did not change before and after debuginit for Monitor#%d ******\n",mon_num);
     end
  end


  if (same || diff ) begin 
     if (actual == expected) 
       sig_same <= 1;
   end
end else begin 
  cntr       <= 0;
  check_done <= 0;
  sig_same   <= 0;
end

end
end








task finish_test;
input [512:0] message;
input [31:0]   id;

begin
  $display("%0d ERROR: DBGINIT Monitor : %s MONITOR NUMBER : %d", $time, message,mon_num);
  @(posedge clk);
  $error ("dbginit_inst", "DBGINIT monitor exited") ;
end
endtask


endmodule
module dbginit_inst (
 rst,
 clk,
 dbginit,
 actual,
 expected,
 cnt_val,
 mon_num

);


   parameter CMP_SZ = 1;


  input rst;
  input clk;
  input dbginit;
  input [CMP_SZ-1:0]  actual;
  input [CMP_SZ-1:0]  expected;
  input [10:0] cnt_val;
  input [31:0] mon_num;

  reg same;
  reg sig_same;
  reg diff;
  reg [31:0]  cntr;
  reg check_done;
  reg start_mon;

initial 
 begin 
  same = 0;
  diff = 0;
  cntr = 0;
  check_done = 0;
  sig_same  = 0;
  start_mon  = 0;
 end

always @(dbginit)
begin
if ( !$test$plusargs("dbginit_mon_off")) begin

if (rst & !dbginit) begin 
 same <= 0;
 diff <= 0;
 start_mon <= 1;
 
 if (actual == expected)
  same <= 1;
 else 
  diff <= 1;
end else begin 
 same <= 0;
 diff <= 0;
 start_mon <= 0;

end

end
end

always @(posedge clk)
begin
if ( !$test$plusargs("dbginit_mon_off")) begin

if (rst & start_mon) begin 
  cntr <= (!dbginit) ?  cntr +1 : 0;
 if ((cntr == cnt_val) & !check_done) begin 
   check_done <= 1;

     if ((actual != expected) && (!sig_same)) begin 
        $display("ERROR : Signal value not as expected after dbginit ; expected= %h ,actual=%h \n", expected,actual);
        finish_test("RTL doesnt reset signals on DBGINIT", mon_num);
     end else begin 
       if (same == 1'b1) 
        $display("****NOTE : Value did not change before and after debuginit for Monitor#%d ******\n",mon_num);
     end
  end


  if (same || diff ) begin 
     if (actual == expected) 
       sig_same <= 1;
   end
end else begin 
  cntr       <= 0;
  check_done <= 0;
  sig_same   <= 0;
end

end
end








task finish_test;
input [512:0] message;
input [31:0]   id;

begin
  $display("%0d ERROR: DBGINIT Monitor : %s MONITOR NUMBER : %d", $time, message,mon_num);
  @(posedge clk);
  $error ("dbginit_inst", "DBGINIT monitor exited") ;
end
endtask


endmodule