data/full_repos/permissive/52682338/neogeo.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/52682338/neogeo.v:124: Signal definition not found, creating implicitly: \'nBITW0\'\n assign nBITWD0 = |{nBITW0, M68K_ADDR[6:5]};\n                    ^~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/neogeo.v:124: Signal definition not found, creating implicitly: \'nBITWD0\'\n                                                                   : ... Suggested alternative: \'nBITW0\'\n assign nBITWD0 = |{nBITW0, M68K_ADDR[6:5]};\n        ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/neogeo.v:125: Signal definition not found, creating implicitly: \'nCOUNTOUT\'\n assign nCOUNTOUT = |{nBITW0, ~M68K_ADDR[6:5]};\n        ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/neogeo.v:150: Signal definition not found, creating implicitly: \'SDRD0\'\n                                                                   : ... Suggested alternative: \'SDD\'\n assign SDD = (SDRD0 & SDRD1) ? 8\'bzzzzzzzz : 8\'b00000000;\n               ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/neogeo.v:150: Signal definition not found, creating implicitly: \'SDRD1\'\n                                                                   : ... Suggested alternative: \'SDRD0\'\n assign SDD = (SDRD0 & SDRD1) ? 8\'bzzzzzzzz : 8\'b00000000;\n                       ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/neogeo.v:165: Signal definition not found, creating implicitly: \'DOTA\'\n assign {DOTA, DOTB} = {|GAD, |GBD};\n         ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/neogeo.v:165: Signal definition not found, creating implicitly: \'DOTB\'\n                                                                   : ... Suggested alternative: \'DOTA\'\n assign {DOTA, DOTB} = {|GAD, |GBD};\n               ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/neogeo.v:173: Signal definition not found, creating implicitly: \'EVEN1\'\n                                                                   : ... Suggested alternative: \'EVEN\'\n assign EVEN = EVEN1;\n               ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/neogeo.v:189: Signal definition not found, creating implicitly: \'nSYSTEM\'\n assign FIXD = nSYSTEM ? FIXD_CART : FIXD_SFIX;\n               ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/neogeo.v:207: Signal definition not found, creating implicitly: \'nSRAMCS\'\n assign nSRAMCS = 1\'b0;\n        ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/neogeo.v:209: Signal definition not found, creating implicitly: \'nSRAMWEN\'\n assign nSWE = nSRAMWEN | nSRAMCS;\n               ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/neogeo.v:209: Signal definition not found, creating implicitly: \'nSWE\'\n                                                                   : ... Suggested alternative: \'WE\'\n assign nSWE = nSRAMWEN | nSRAMCS;\n        ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/neogeo.v:210: Signal definition not found, creating implicitly: \'nSRAMWEL\'\n                                                                   : ... Suggested alternative: \'nSRAMWEN\'\n assign nBWL = nSRAMWEL | nSWE;\n               ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/neogeo.v:210: Signal definition not found, creating implicitly: \'nBWL\'\n assign nBWL = nSRAMWEL | nSWE;\n        ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/neogeo.v:211: Signal definition not found, creating implicitly: \'nSRAMWEU\'\n                                                                   : ... Suggested alternative: \'nSRAMWEL\'\n assign nBWU = nSRAMWEU | nSWE;\n               ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/neogeo.v:211: Signal definition not found, creating implicitly: \'nBWU\'\n                                                                   : ... Suggested alternative: \'nBWL\'\n assign nBWU = nSRAMWEU | nSWE;\n        ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/neogeo.v:214: Signal definition not found, creating implicitly: \'PCK1\'\n                                                                   : ... Suggested alternative: \'PCK1B\'\n assign PCK1B = ~PCK1;\n                 ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/neogeo.v:215: Signal definition not found, creating implicitly: \'PCK2\'\n                                                                   : ... Suggested alternative: \'PCK1\'\n assign PCK2B = ~PCK2;\n                 ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/neogeo.v:216: Signal definition not found, creating implicitly: \'nPAL\'\n                                                                   : ... Suggested alternative: \'PA\'\n assign nPALWE = M68K_RW | nPAL;\n                           ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/neogeo.v:216: Signal definition not found, creating implicitly: \'nPALWE\'\n                                                                   : ... Suggested alternative: \'nPAL\'\n assign nPALWE = M68K_RW | nPAL;\n        ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/neogeo.v:217: Signal definition not found, creating implicitly: \'SYSTEMB\'\n                                                                   : ... Suggested alternative: \'nSYSTEM\'\n assign SYSTEMB = ~nSYSTEM;\n        ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/neogeo.v:218: Signal definition not found, creating implicitly: \'nROMOEU\'\n                                                                   : ... Suggested alternative: \'nROMOE\'\n assign nROMOE = nROMOEU & nROMOEL;\n                 ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/neogeo.v:218: Signal definition not found, creating implicitly: \'nROMOEL\'\n                                                                   : ... Suggested alternative: \'nROMOE\'\n assign nROMOE = nROMOEU & nROMOEL;\n                           ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/neogeo.v:221: Signal definition not found, creating implicitly: \'nCARDWEN\'\n assign CARD_PIN_nWE = |{nCARDWEN, ~CARDWENB, nCRDW};\n                         ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/neogeo.v:221: Signal definition not found, creating implicitly: \'CARDWENB\'\n                                                                   : ... Suggested alternative: \'nCARDWEN\'\n assign CARD_PIN_nWE = |{nCARDWEN, ~CARDWENB, nCRDW};\n                                    ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/neogeo.v:221: Signal definition not found, creating implicitly: \'nCRDW\'\n                                                                   : ... Suggested alternative: \'nCRDC\'\n assign CARD_PIN_nWE = |{nCARDWEN, ~CARDWENB, nCRDW};\n                                              ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/52682338/neogeo.v:222: Signal definition not found, creating implicitly: \'nREGEN\'\n assign CARD_PIN_nREG = nREGEN | nCRDO;\n                        ^~~~~~\n%Error: data/full_repos/permissive/52682338/neogeo.v:128: Cannot find file containing module: \'cpu_68k\'\n cpu_68k M68KCPU(CLK_68KCLK, nRESET, IPL1, IPL0, nDTACK, M68K_ADDR, M68K_DATA, nLDS, nUDS, nAS, M68K_RW);\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52682338,data/full_repos/permissive/52682338/cpu_68k\n             data/full_repos/permissive/52682338,data/full_repos/permissive/52682338/cpu_68k.v\n             data/full_repos/permissive/52682338,data/full_repos/permissive/52682338/cpu_68k.sv\n             cpu_68k\n             cpu_68k.v\n             cpu_68k.sv\n             obj_dir/cpu_68k\n             obj_dir/cpu_68k.v\n             obj_dir/cpu_68k.sv\n%Error: data/full_repos/permissive/52682338/neogeo.v:136: Cannot find file containing module: \'cpu_z80\'\n cpu_z80 Z80CPU(CLK_4M, nRESET, SDD, SDA, nIORQ, nMREQ, nSDRD, nSDWR, nZ80INT, nZ80NMI);\n ^~~~~~~\n%Error: data/full_repos/permissive/52682338/neogeo.v:138: Cannot find file containing module: \'neo_c1\'\n neo_c1 C1(M68K_ADDR[21:17], M68K_DATA[15:8], A22Z, A23Z, nLDS, nUDS, M68K_RW, nAS, nROMOEL, nROMOEU,\n ^~~~~~\n%Error: data/full_repos/permissive/52682338/neogeo.v:144: Cannot find file containing module: \'neo_d0\'\n neo_d0 D0(CLK_24M, nRESET, nRESETP, CLK_12M, CLK_68KCLK, CLK_68KCLKB, CLK_6MB, CLK_1MB, M68K_ADDR[4],\n ^~~~~~\n%Error: data/full_repos/permissive/52682338/neogeo.v:152: Cannot find file containing module: \'neo_e0\'\n neo_e0 E0(M68K_ADDR[23:1], BNK[2:0], nSROMOEU, nSROMOEL, nSROMOE,\n ^~~~~~\n%Error: data/full_repos/permissive/52682338/neogeo.v:155: Cannot find file containing module: \'neo_f0\'\n neo_f0 F0(nRESET, nDIPRD0, nDIPRD1, nBITWD0, DIPSW, M68K_ADDR[7:4], M68K_DATA[7:0], SYSTEMB, nSLOT, SLOTA,\n ^~~~~~\n%Error: data/full_repos/permissive/52682338/neogeo.v:158: Cannot find file containing module: \'neo_i0\'\n neo_i0 I0(nRESET, nCOUNTOUT, M68K_ADDR[3:1], M68K_ADDR[7], COUNTER1, COUNTER2, LOCKOUT1, LOCKOUT2,\n ^~~~~~\n%Error: data/full_repos/permissive/52682338/neogeo.v:161: Cannot find file containing module: \'syslatch\'\n syslatch SL(M68K_ADDR[4:1], nBITW1, nRESET,\n ^~~~~~~~\n%Error: data/full_repos/permissive/52682338/neogeo.v:169: Cannot find file containing module: \'lspc2_a2\'\n lspc2_a2 LSPC2(CLK_24M, nRESET, PBUS[15:0], PBUS[23:16], M68K_ADDR[3:1], M68K_DATA, nLSPOE, nLSPWE, DOTA, DOTB, CA4, S2H1,\n ^~~~~~~~\n%Error: data/full_repos/permissive/52682338/neogeo.v:175: Cannot find file containing module: \'neo_b1\'\n neo_b1 B1(CLK_6MB, CLK_1MB, PBUS, FIXD, PCK1, PCK2, CHBL, nBNKB, GAD, GBD, WE[0], WE[1], WE[2], WE[3],\n ^~~~~~\n%Error: data/full_repos/permissive/52682338/neogeo.v:179: Cannot find file containing module: \'ram_68k\'\n ram_68k M68KRAM(M68K_ADDR[15:1], M68K_DATA, nWWL, nWWU, nWRL, nWRU);\n ^~~~~~~\n%Error: data/full_repos/permissive/52682338/neogeo.v:180: Cannot find file containing module: \'z80ram\'\n z80ram ZRAM(SDA[10:0], SDD, nZRAMCS, nSDMRD, nSDMWR);\n ^~~~~~\n%Error: data/full_repos/permissive/52682338/neogeo.v:181: Cannot find file containing module: \'palram\'\n palram PALRAM({PALBNK, PA}, PC, nPALWE);\n ^~~~~~\n%Error: data/full_repos/permissive/52682338/neogeo.v:184: Cannot find file containing module: \'rom_sps2\'\n rom_sps2 SP(M68K_ADDR[16:1], {M68K_DATA[7:0], M68K_DATA[15:8]}, nSROMOE);\n ^~~~~~~~\n%Error: data/full_repos/permissive/52682338/neogeo.v:185: Cannot find file containing module: \'rom_l0\'\n rom_l0 L0(PBUS[15:0], PBUS[23:16], nVCS);\n ^~~~~~\n%Error: data/full_repos/permissive/52682338/neogeo.v:186: Cannot find file containing module: \'rom_sfix\'\n rom_sfix SFIX({G[15:3], S2H1, G[2:0]}, FIXD_SFIX, nSYSTEM);\n ^~~~~~~~\n%Error: data/full_repos/permissive/52682338/neogeo.v:191: Cannot find file containing module: \'ym2610\'\n ym2610 YM(CLK_8M, nRESET, SDD, SDA[1:0], nZ80INT, n2610CS, n2610WR, n2610RD, SDRAD, {SDRA_U, SDRA_L}, SDRMPX,\n ^~~~~~\n%Error: data/full_repos/permissive/52682338/neogeo.v:194: Cannot find file containing module: \'ym2i2s\'\n ym2i2s YM2I2S(nRESET, CLK_I2S, ANA, SH1, SH2, OP0, PHI_S, I2S_MCLK, I2S_BICK, I2S_SDTI, I2S_LRCK);\n ^~~~~~\n%Error: data/full_repos/permissive/52682338/neogeo.v:197: Cannot find file containing module: \'upd4990\'\n upd4990 RTC(CLK_RTC, 1\'b1, 1\'b1, RTC_CLK, RTC_DIN, RTC_STROBE, RTC_TP, RTC_DOUT);\n ^~~~~~~\n%Error: data/full_repos/permissive/52682338/neogeo.v:199: Cannot find file containing module: \'videout\'\n videout VOUT(CLK_6MB, nBNKB, SHADOW, PC, VIDEO_R, VIDEO_G, VIDEO_B);\n ^~~~~~~\n%Error: data/full_repos/permissive/52682338/neogeo.v:204: Cannot find file containing module: \'logger\'\n logger LOGGER(CLK_6MB, nBNKB, SHADOW, COUNTER1, COUNTER2, LOCKOUT1, LOCKOUT2);\n ^~~~~~\n%Error: data/full_repos/permissive/52682338/neogeo.v:208: Cannot find file containing module: \'sram\'\n sram SRAM(M68K_DATA, M68K_ADDR[15:1], nBWL, nBWU, nSRAMOEL, nSRAMOEU, nSRAMCS);\n ^~~~\n%Error: Exiting due to 22 error(s), 27 warning(s)\n'
module neogeo(
	input nRESET_BTN,
	

	input [9:0] P1_IN,
	input [9:0] P2_IN,
	
	input [7:0] DIPSW,
	

	inout [15:0] M68K_DATA,
	output [23:1] M68K_ADDR,
	output M68K_RW, nAS, nLDS, nUDS,
	output [2:0] LED_LATCH,
	output [7:0] LED_DATA,


	output CLK_68KCLKB, CLK_8M, CLK_4MB,
	

	output nROMOE, nSLOTCS,
	input nROMWAIT, nPWAIT0, nPWAIT1, PDTACK,
	output nPORTOEL, nPORTOEU,
	output nPORTWEL, nPORTWEU,
	output nPORTADRS,
	

	input [7:0] SDRAD,
	output [9:8] SDRA_L,
	output [23:20] SDRA_U,
	output SDRMPX, nSDROE,
	input [7:0] SDPAD,
	output [11:8] SDPA,
	output SDPMPX, nSDPOE,
	

	output nSDROM, nSDMRD,
	output [15:0] SDA,
	inout [7:0] SDD,
	

	inout [23:0] PBUS,
	output nVCS,
	output S2H1, CA4,
	output PCK1B, PCK2B,
	

	output CLK_12M, EVEN, LOAD, H,
	input [3:0] GAD, GBD,
	input [7:0] FIXD_CART,
	

	output [4:0] CDA_U,
	output nCRDC, nCRDO, CARD_PIN_nWE, CARD_PIN_nREG,
	input nCD1, nCD2, nWP,
	
	output [6:0] VIDEO_R,
	output [6:0] VIDEO_G,
	output [6:0] VIDEO_B,
	output VIDEO_SYNC
	


	


);

	parameter SYSTEM_MODE = 1'b1;
	
	
	wire [7:0] FIXD;
	wire [7:0] FIXD_SFIX;
	wire [15:0] G;
	
	wire [23:0] CDA;
	wire [2:0] BNK;
	
	wire [11:0] PA;
	wire [15:0] PC;
	
	wire [3:0] WE;
	wire [3:0] CK;
	
	wire [5:0] nSLOT;
	
	wire [2:0] P1_OUT;
	wire [2:0] P2_OUT;
	
	wire [5:0] ANA;

	

	assign nSLOTCS = nSLOT[0];
	

	assign nBITWD0 = |{nBITW0, M68K_ADDR[6:5]};
	assign nCOUNTOUT = |{nBITW0, ~M68K_ADDR[6:5]};
	

	cpu_68k M68KCPU(CLK_68KCLK, nRESET, IPL1, IPL0, nDTACK, M68K_ADDR, M68K_DATA, nLDS, nUDS, nAS, M68K_RW);

	
	cpu_z80 Z80CPU(CLK_4M, nRESET, SDD, SDA, nIORQ, nMREQ, nSDRD, nSDWR, nZ80INT, nZ80NMI);
	
	neo_c1 C1(M68K_ADDR[21:17], M68K_DATA[15:8], A22Z, A23Z, nLDS, nUDS, M68K_RW, nAS, nROMOEL, nROMOEU,
				nPORTOEL, nPORTOEU, nPORTWEL, nPORTWEU, nPORTADRS, nWRL, nWRU, nWWL, nWWU, nSROMOEL, nSROMOEU, 
				nSRAMOEL, nSRAMOEU, nSRAMWEL, nSRAMWEU, nLSPOE, nLSPWE, nCRDO, nCRDW, nCRDC, nSDW, P1_IN, P2_IN,
				nCD1, nCD2, nWP, nROMWAIT, nPWAIT0, nPWAIT1, PDTACK, SDD, nSDZ80R, nSDZ80W, nSDZ80CLR, CLK_68KCLK,
				nDTACK, nBITW0, nBITW1, nDIPRD0, nDIPRD1, nPAL, SYSTEM_MODE);
	
	neo_d0 D0(CLK_24M, nRESET, nRESETP, CLK_12M, CLK_68KCLK, CLK_68KCLKB, CLK_6MB, CLK_1MB, M68K_ADDR[4],
				nBITWD0, M68K_DATA[5:0], SDA[15:11], SDA[4:2], nSDRD, nSDWR, nMREQ, nIORQ, nZ80NMI, nSDW, nSDZ80R,
				nSDZ80W, nSDZ80CLR, nSDROM, nSDMRD, nSDMWR, SDRD0, SDRD1, n2610CS, n2610RD, n2610WR, nZRAMCS,
				BNK, P1_OUT, P2_OUT);
	

	assign SDD = (SDRD0 & SDRD1) ? 8'bzzzzzzzz : 8'b00000000;
	
	neo_e0 E0(M68K_ADDR[23:1], BNK[2:0], nSROMOEU, nSROMOEL, nSROMOE,
				nVEC, A23Z, A22Z, CDA);
	
	neo_f0 F0(nRESET, nDIPRD0, nDIPRD1, nBITWD0, DIPSW, M68K_ADDR[7:4], M68K_DATA[7:0], SYSTEMB, nSLOT, SLOTA,
				SLOTB, SLOTC, LED_LATCH, LED_DATA, RTC_DOUT, RTC_TP, RTC_DIN, RTC_CLK, RTC_STROBE);
	
	neo_i0 I0(nRESET, nCOUNTOUT, M68K_ADDR[3:1], M68K_ADDR[7], COUNTER1, COUNTER2, LOCKOUT1, LOCKOUT2,
				PBUS[15:0], PCK2B, G);
	
	syslatch SL(M68K_ADDR[4:1], nBITW1, nRESET,
				SHADOW, nVEC, nCARDWEN, CARDWENB, nREGEN, nSYSTEM, nSRAMWEN, PALBNK);


	assign {DOTA, DOTB} = {|GAD, |GBD};
	
	assign CDA_U = CDA[23:19];
	
	lspc2_a2 LSPC2(CLK_24M, nRESET, PBUS[15:0], PBUS[23:16], M68K_ADDR[3:1], M68K_DATA, nLSPOE, nLSPWE, DOTA, DOTB, CA4, S2H1,
				S1H1, LOAD, H, EVEN1, EVEN2, IPL0, IPL1, TMS0, LD1, LD2, PCK1, PCK2, WE[3:0], CK[3:0], SS1,
				SS2, nRESETP, VIDEO_SYNC, CHBL, nBNKB, nVCS, CLK_8M, CLK_4M);
	
	assign EVEN = EVEN1;
	
	neo_b1 B1(CLK_6MB, CLK_1MB, PBUS, FIXD, PCK1, PCK2, CHBL, nBNKB, GAD, GBD, WE[0], WE[1], WE[2], WE[3],
				CK[0], CK[1], CK[2], CK[3], TMS0, LD1, LD2, SS1, SS2, S1H1, A23Z, A22Z, PA, nLDS, M68K_RW, nAS,
				M68K_ADDR[21:17], M68K_ADDR[12:1], nHALT, nRESET, nRESET_BTN);
	
	ram_68k M68KRAM(M68K_ADDR[15:1], M68K_DATA, nWWL, nWWU, nWRL, nWRU);
	z80ram ZRAM(SDA[10:0], SDD, nZRAMCS, nSDMRD, nSDMWR);
	palram PALRAM({PALBNK, PA}, PC, nPALWE);
	

	rom_sps2 SP(M68K_ADDR[16:1], {M68K_DATA[7:0], M68K_DATA[15:8]}, nSROMOE);
	rom_l0 L0(PBUS[15:0], PBUS[23:16], nVCS);
	rom_sfix SFIX({G[15:3], S2H1, G[2:0]}, FIXD_SFIX, nSYSTEM);


	assign FIXD = nSYSTEM ? FIXD_CART : FIXD_SFIX;
	
	ym2610 YM(CLK_8M, nRESET, SDD, SDA[1:0], nZ80INT, n2610CS, n2610WR, n2610RD, SDRAD, {SDRA_U, SDRA_L}, SDRMPX,
				nSDROE, SDPAD, SDPA, SDPMPX, nSDPOE, ANA, SH1, SH2, OP0, PHI_S);
	
	ym2i2s YM2I2S(nRESET, CLK_I2S, ANA, SH1, SH2, OP0, PHI_S, I2S_MCLK, I2S_BICK, I2S_SDTI, I2S_LRCK);
	

	upd4990 RTC(CLK_RTC, 1'b1, 1'b1, RTC_CLK, RTC_DIN, RTC_STROBE, RTC_TP, RTC_DOUT);

	videout VOUT(CLK_6MB, nBNKB, SHADOW, PC, VIDEO_R, VIDEO_G, VIDEO_B);

						

	logger LOGGER(CLK_6MB, nBNKB, SHADOW, COUNTER1, COUNTER2, LOCKOUT1, LOCKOUT2);
	

	assign nSRAMCS = 1'b0;
	sram SRAM(M68K_DATA, M68K_ADDR[15:1], nBWL, nBWU, nSRAMOEL, nSRAMOEU, nSRAMCS);
	assign nSWE = nSRAMWEN | nSRAMCS;
	assign nBWL = nSRAMWEL | nSWE;
	assign nBWU = nSRAMWEU | nSWE;
	

	assign PCK1B = ~PCK1;
	assign PCK2B = ~PCK2;
	assign nPALWE = M68K_RW | nPAL;
	assign SYSTEMB = ~nSYSTEM;
	assign nROMOE = nROMOEU & nROMOEL;
	

	assign CARD_PIN_nWE = |{nCARDWEN, ~CARDWENB, nCRDW};
	assign CARD_PIN_nREG = nREGEN | nCRDO;


	assign M68K_DATA = (nPAL | ~M68K_RW) ? 16'bzzzzzzzzzzzzzzzz : PC;
	assign PC = nPALWE ? 16'bzzzzzzzzzzzzzzzz : M68K_DATA;

endmodule
module neogeo(
	input nRESET_BTN,
	

	input [9:0] P1_IN,
	input [9:0] P2_IN,
	
	input [7:0] DIPSW,
	

	inout [15:0] M68K_DATA,
	output [23:1] M68K_ADDR,
	output M68K_RW, nAS, nLDS, nUDS,
	output [2:0] LED_LATCH,
	output [7:0] LED_DATA,


	output CLK_68KCLKB, CLK_8M, CLK_4MB,
	

	output nROMOE, nSLOTCS,
	input nROMWAIT, nPWAIT0, nPWAIT1, PDTACK,
	output nPORTOEL, nPORTOEU,
	output nPORTWEL, nPORTWEU,
	output nPORTADRS,
	

	input [7:0] SDRAD,
	output [9:8] SDRA_L,
	output [23:20] SDRA_U,
	output SDRMPX, nSDROE,
	input [7:0] SDPAD,
	output [11:8] SDPA,
	output SDPMPX, nSDPOE,
	

	output nSDROM, nSDMRD,
	output [15:0] SDA,
	inout [7:0] SDD,
	

	inout [23:0] PBUS,
	output nVCS,
	output S2H1, CA4,
	output PCK1B, PCK2B,
	

	output CLK_12M, EVEN, LOAD, H,
	input [3:0] GAD, GBD,
	input [7:0] FIXD_CART,
	

	output [4:0] CDA_U,
	output nCRDC, nCRDO, CARD_PIN_nWE, CARD_PIN_nREG,
	input nCD1, nCD2, nWP,
	
	output [6:0] VIDEO_R,
	output [6:0] VIDEO_G,
	output [6:0] VIDEO_B,
	output VIDEO_SYNC
	


	


);


	parameter SYSTEM_MODE = 1'b1;
	
	
	wire [7:0] FIXD;
	wire [7:0] FIXD_SFIX;
	wire [15:0] G;
	
	wire [23:0] CDA;
	wire [2:0] BNK;
	
	wire [11:0] PA;
	wire [15:0] PC;
	
	wire [3:0] WE;
	wire [3:0] CK;
	
	wire [5:0] nSLOT;
	
	wire [2:0] P1_OUT;
	wire [2:0] P2_OUT;
	
	wire [5:0] ANA;

	

	assign nSLOTCS = nSLOT[0];
	

	assign nBITWD0 = |{nBITW0, M68K_ADDR[6:5]};
	assign nCOUNTOUT = |{nBITW0, ~M68K_ADDR[6:5]};
	

	cpu_68k M68KCPU(CLK_68KCLK, nRESET, IPL1, IPL0, nDTACK, M68K_ADDR, M68K_DATA, nLDS, nUDS, nAS, M68K_RW);

	
	cpu_z80 Z80CPU(CLK_4M, nRESET, SDD, SDA, nIORQ, nMREQ, nSDRD, nSDWR, nZ80INT, nZ80NMI);
	
	neo_c1 C1(M68K_ADDR[21:17], M68K_DATA[15:8], A22Z, A23Z, nLDS, nUDS, M68K_RW, nAS, nROMOEL, nROMOEU,
				nPORTOEL, nPORTOEU, nPORTWEL, nPORTWEU, nPORTADRS, nWRL, nWRU, nWWL, nWWU, nSROMOEL, nSROMOEU, 
				nSRAMOEL, nSRAMOEU, nSRAMWEL, nSRAMWEU, nLSPOE, nLSPWE, nCRDO, nCRDW, nCRDC, nSDW, P1_IN, P2_IN,
				nCD1, nCD2, nWP, nROMWAIT, nPWAIT0, nPWAIT1, PDTACK, SDD, nSDZ80R, nSDZ80W, nSDZ80CLR, CLK_68KCLK,
				nDTACK, nBITW0, nBITW1, nDIPRD0, nDIPRD1, nPAL, SYSTEM_MODE);
	
	neo_d0 D0(CLK_24M, nRESET, nRESETP, CLK_12M, CLK_68KCLK, CLK_68KCLKB, CLK_6MB, CLK_1MB, M68K_ADDR[4],
				nBITWD0, M68K_DATA[5:0], SDA[15:11], SDA[4:2], nSDRD, nSDWR, nMREQ, nIORQ, nZ80NMI, nSDW, nSDZ80R,
				nSDZ80W, nSDZ80CLR, nSDROM, nSDMRD, nSDMWR, SDRD0, SDRD1, n2610CS, n2610RD, n2610WR, nZRAMCS,
				BNK, P1_OUT, P2_OUT);
	

	assign SDD = (SDRD0 & SDRD1) ? 8'bzzzzzzzz : 8'b00000000;
	
	neo_e0 E0(M68K_ADDR[23:1], BNK[2:0], nSROMOEU, nSROMOEL, nSROMOE,
				nVEC, A23Z, A22Z, CDA);
	
	neo_f0 F0(nRESET, nDIPRD0, nDIPRD1, nBITWD0, DIPSW, M68K_ADDR[7:4], M68K_DATA[7:0], SYSTEMB, nSLOT, SLOTA,
				SLOTB, SLOTC, LED_LATCH, LED_DATA, RTC_DOUT, RTC_TP, RTC_DIN, RTC_CLK, RTC_STROBE);
	
	neo_i0 I0(nRESET, nCOUNTOUT, M68K_ADDR[3:1], M68K_ADDR[7], COUNTER1, COUNTER2, LOCKOUT1, LOCKOUT2,
				PBUS[15:0], PCK2B, G);
	
	syslatch SL(M68K_ADDR[4:1], nBITW1, nRESET,
				SHADOW, nVEC, nCARDWEN, CARDWENB, nREGEN, nSYSTEM, nSRAMWEN, PALBNK);


	assign {DOTA, DOTB} = {|GAD, |GBD};
	
	assign CDA_U = CDA[23:19];
	
	lspc2_a2 LSPC2(CLK_24M, nRESET, PBUS[15:0], PBUS[23:16], M68K_ADDR[3:1], M68K_DATA, nLSPOE, nLSPWE, DOTA, DOTB, CA4, S2H1,
				S1H1, LOAD, H, EVEN1, EVEN2, IPL0, IPL1, TMS0, LD1, LD2, PCK1, PCK2, WE[3:0], CK[3:0], SS1,
				SS2, nRESETP, VIDEO_SYNC, CHBL, nBNKB, nVCS, CLK_8M, CLK_4M);
	
	assign EVEN = EVEN1;
	
	neo_b1 B1(CLK_6MB, CLK_1MB, PBUS, FIXD, PCK1, PCK2, CHBL, nBNKB, GAD, GBD, WE[0], WE[1], WE[2], WE[3],
				CK[0], CK[1], CK[2], CK[3], TMS0, LD1, LD2, SS1, SS2, S1H1, A23Z, A22Z, PA, nLDS, M68K_RW, nAS,
				M68K_ADDR[21:17], M68K_ADDR[12:1], nHALT, nRESET, nRESET_BTN);
	
	ram_68k M68KRAM(M68K_ADDR[15:1], M68K_DATA, nWWL, nWWU, nWRL, nWRU);
	z80ram ZRAM(SDA[10:0], SDD, nZRAMCS, nSDMRD, nSDMWR);
	palram PALRAM({PALBNK, PA}, PC, nPALWE);
	

	rom_sps2 SP(M68K_ADDR[16:1], {M68K_DATA[7:0], M68K_DATA[15:8]}, nSROMOE);
	rom_l0 L0(PBUS[15:0], PBUS[23:16], nVCS);
	rom_sfix SFIX({G[15:3], S2H1, G[2:0]}, FIXD_SFIX, nSYSTEM);


	assign FIXD = nSYSTEM ? FIXD_CART : FIXD_SFIX;
	
	ym2610 YM(CLK_8M, nRESET, SDD, SDA[1:0], nZ80INT, n2610CS, n2610WR, n2610RD, SDRAD, {SDRA_U, SDRA_L}, SDRMPX,
				nSDROE, SDPAD, SDPA, SDPMPX, nSDPOE, ANA, SH1, SH2, OP0, PHI_S);
	
	ym2i2s YM2I2S(nRESET, CLK_I2S, ANA, SH1, SH2, OP0, PHI_S, I2S_MCLK, I2S_BICK, I2S_SDTI, I2S_LRCK);
	

	upd4990 RTC(CLK_RTC, 1'b1, 1'b1, RTC_CLK, RTC_DIN, RTC_STROBE, RTC_TP, RTC_DOUT);

	videout VOUT(CLK_6MB, nBNKB, SHADOW, PC, VIDEO_R, VIDEO_G, VIDEO_B);

						

	logger LOGGER(CLK_6MB, nBNKB, SHADOW, COUNTER1, COUNTER2, LOCKOUT1, LOCKOUT2);
	

	assign nSRAMCS = 1'b0;
	sram SRAM(M68K_DATA, M68K_ADDR[15:1], nBWL, nBWU, nSRAMOEL, nSRAMOEU, nSRAMCS);
	assign nSWE = nSRAMWEN | nSRAMCS;
	assign nBWL = nSRAMWEL | nSWE;
	assign nBWU = nSRAMWEU | nSWE;
	

	assign PCK1B = ~PCK1;
	assign PCK2B = ~PCK2;
	assign nPALWE = M68K_RW | nPAL;
	assign SYSTEMB = ~nSYSTEM;
	assign nROMOE = nROMOEU & nROMOEL;
	

	assign CARD_PIN_nWE = |{nCARDWEN, ~CARDWENB, nCRDW};
	assign CARD_PIN_nREG = nREGEN | nCRDO;


	assign M68K_DATA = (nPAL | ~M68K_RW) ? 16'bzzzzzzzzzzzzzzzz : PC;
	assign PC = nPALWE ? 16'bzzzzzzzzzzzzzzzz : M68K_DATA;

endmodule