data/full_repos/permissive/454430637/project_files/Controller.v
data/verilator_xmls/b7c69457-68ae-43bb-96e7-aaae427c5bea.xml
module Controller(
i_clk  , load_ACC , load_B , load_A ,
 shift_A_reg , clr_ACC_reg , Lsb_out  , Msb_out,sel_SUM ,
A_out, start , done , p_STATE
);

input i_clk ;
input start ;
input A_out ;
output load_ACC ;
output load_B ;
output load_A ;
output shift_A_reg ;
output clr_ACC_reg ;
output done ;
output Lsb_out ;
output Msb_out ;
output sel_SUM ;

output reg [3:0] p_STATE ;

reg [8:0] CV ;

assign load_A      =  CV[8] ;
assign load_ACC    =  CV[7] ;
assign load_B      =  CV[6] ;
assign clr_ACC_reg =  CV[5] ;
assign shift_A_reg =  CV[4] ;
assign Lsb_out     =  CV[3] ;
assign Msb_out     =  CV[2] ;
assign sel_SUM     =  CV[1] ;
assign done        =  CV[0] ;





always @ (posedge i_clk)
  begin
   case (p_STATE )
   `idle : begin
    if (start)
              p_STATE <= `init ;
               else
               p_STATE <= `idle ;
               end
   `init : begin
               p_STATE <= `s2 ;
               end
    `s2 , `s3, `s4, `s5, `s6, `s7, `s8  : begin
                                     p_STATE <= p_STATE + 1'b1 ;
                                      end 
    `rslt_1 : begin
                p_STATE <= `rslt_2 ;
                end  
    `rslt_2 : begin
                 p_STATE <= `idle ;
                  end 
                  
          default : begin
                      p_STATE <= `idle ;
                      end          
                  endcase 
                   end    
                   
       always @ (p_STATE or A_out or start )
        begin
         case (p_STATE)
        `idle : begin 
                 if (start==1'b0)
                   CV   = 9'b00000_0001 ;
                   else 
                   CV = 9'b11010_0000;
                   end
         `init : begin   
                     CV = 9'b00100_0000;
                     end 
                     
                     
 `s2 , `s3 , `s4 , `s5 , `s6  , `s7 , `s8 , `s9 : begin 
                                                  if (A_out) 
                                                  CV = 9'b01001_0010;
                                                  else
                                                  CV = 9'b01001_0000;
                                                  end 
          `rslt_1 : begin
                     CV = 9'b00000_1000;
                      end                                                                                              
           `rslt_2 : begin 
                     CV = 9'b00000_0100;
                     end 
             default : begin  
                       CV = 9'b00000_0000;
                       end        
                    endcase 
                    end        



endmodule
module Controller(
i_clk  , load_ACC , load_B , load_A ,
 shift_A_reg , clr_ACC_reg , Lsb_out  , Msb_out,sel_SUM ,
A_out, start , done , p_STATE
);


input i_clk ;
input start ;
input A_out ;
output load_ACC ;
output load_B ;
output load_A ;
output shift_A_reg ;
output clr_ACC_reg ;
output done ;
output Lsb_out ;
output Msb_out ;
output sel_SUM ;

output reg [3:0] p_STATE ;

reg [8:0] CV ;

assign load_A      =  CV[8] ;
assign load_ACC    =  CV[7] ;
assign load_B      =  CV[6] ;
assign clr_ACC_reg =  CV[5] ;
assign shift_A_reg =  CV[4] ;
assign Lsb_out     =  CV[3] ;
assign Msb_out     =  CV[2] ;
assign sel_SUM     =  CV[1] ;
assign done        =  CV[0] ;





always @ (posedge i_clk)
  begin
   case (p_STATE )
   `idle : begin
    if (start)
              p_STATE <= `init ;
               else
               p_STATE <= `idle ;
               end
   `init : begin
               p_STATE <= `s2 ;
               end
    `s2 , `s3, `s4, `s5, `s6, `s7, `s8  : begin
                                     p_STATE <= p_STATE + 1'b1 ;
                                      end 
    `rslt_1 : begin
                p_STATE <= `rslt_2 ;
                end  
    `rslt_2 : begin
                 p_STATE <= `idle ;
                  end 
                  
          default : begin
                      p_STATE <= `idle ;
                      end          
                  endcase 
                   end    
                   
       always @ (p_STATE or A_out or start )
        begin
         case (p_STATE)
        `idle : begin 
                 if (start==1'b0)
                   CV   = 9'b00000_0001 ;
                   else 
                   CV = 9'b11010_0000;
                   end
         `init : begin   
                     CV = 9'b00100_0000;
                     end 
                     
                     
 `s2 , `s3 , `s4 , `s5 , `s6  , `s7 , `s8 , `s9 : begin 
                                                  if (A_out) 
                                                  CV = 9'b01001_0010;
                                                  else
                                                  CV = 9'b01001_0000;
                                                  end 
          `rslt_1 : begin
                     CV = 9'b00000_1000;
                      end                                                                                              
           `rslt_2 : begin 
                     CV = 9'b00000_0100;
                     end 
             default : begin  
                       CV = 9'b00000_0000;
                       end        
                    endcase 
                    end        



endmodule