data/full_repos/permissive/527176783/Single/A_Single/SingleCycleCPU.v
1: b'%Error: data/full_repos/permissive/527176783/Single/A_Single/SingleCycleCPU.v:2: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/527176783/Single/A_Single,data/full_repos/permissive/527176783/define.v\n             data/full_repos/permissive/527176783/Single/A_Single,data/full_repos/permissive/527176783/define.v.v\n             data/full_repos/permissive/527176783/Single/A_Single,data/full_repos/permissive/527176783/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/527176783/Single/A_Single/SingleCycleCPU.v:207: Define or directive not defined: \'`funcJR\'\n    assign pc_jump = (func == `funcJR)? pc_jr : pc_j_jal;\n                              ^~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/SingleCycleCPU.v:207: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    assign pc_jump = (func == `funcJR)? pc_jr : pc_j_jal;\n                                     ^\n%Error: Exiting due to 3 error(s)\n'
module SingleCycleCPU(
    input wire clk,
    input wire rst_n
);

    wire [31:0] pc;
    wire [31:0] next_pc;
    wire [31:0] pc_add4;
    wire [31:0] pc_branch;
    wire [31:0] pc_jump;



    wire [31:0] inst;
    wire [5:0] op;
    wire [5:0] func;
    wire [4:0] sa;
    wire [4:0] rs;
    wire [4:0] rt;
    wire [4:0] rd;
    wire [15:0] immd16;
    wire [25:0] immd26;


    wire regWr;
    wire [4:0] WriteReg;

    wire [31:0] WriteData;



    wire [31:0] RD1;
    wire [31:0] RD2;




    wire  Zero;
    wire        Sign;
    wire  [3:0] Aluc;
    wire  AluSrcA;
    wire  AluSrcB;
    wire  [1:0] PcSrc;
    wire  Wrback;
    wire  RegDst;
    wire  ExtSe;
    wire  memWr;


    wire  [31:0] Extendimmd;
    wire  [31:0] immd_pc;
    wire  [31:0] alu_in_a;
    wire  [31:0] alu_in_b;
    wire  [31:0] alu_out;
    wire  [31:0] data_mem_out;
    wire  [31:0] sa_immd;
   
    PC pc_instance(
        .clk(clk),
        .rst_n(rst_n),
        .next_pc(next_pc),
        .pc(pc)
    );

    PCAdd pc_add4_instance(
        .pc(pc),
        .pc_add4(pc_add4)
    );

    instMEM instMEM_instance(
        .pc(pc),
	    .inst(inst)
    );

    decoder decoder_instance(
        .ins(inst),
        .op(op),
        .func(func),
        .sa(sa),
        .rs(rs),
        .rt(rt),
        .rd(rd),
        .immd16(immd16),
        .immd26(immd26)
    );

    wire [31:0] pc_jr;
    RegFile RegFile_instance(
        .clk(clk),
        .rst_n(rst_n),
        .regWr(regWr),
        .RdReg1(rs),
        .RdReg2(rt),
        .WrReg(WriteReg),
        .WriteData(WriteData),
        .RD1(RD1),
        .RD2(RD2)
    );
    assign pc_jr = RD1;

    mux2 mux2_instance(
        .rd(rd),
        .rt(rt),
        .sel(RegDst),
        .result(WriteReg)
    );

    Extend Extend_instance(
        .ExtSe(ExtSe),
        .immd16(immd16),
        .Extout(Extendimmd)
    );

    Lshift Lshift_instance(
        .in(Extendimmd),
        .shift(immd_pc)
    );

    PC_branch PC_branch_instance(
        .immd_pc(immd_pc),
        .pc_add4(pc_add4),
        .pc_branch(pc_branch)
    );

    mux2x32 mux2x32_instance_1(
        .Qb(RD2),
        .im(Extendimmd),
        .sel(AluSrcB),
        .result(alu_in_b)
    );

    wire [31:0] pc_j_jal;
    Jshift Jshift_instance(
        .inst(immd26),
        .pc_add4(pc_add4),
        .sh(pc_j_jal)
    );

    ALU ALU_instance(
        .Aluc(Aluc),
        .a(alu_in_a),
        .b(alu_in_b),
        .out(alu_out),
        .zero(Zero),
        .sign(Sign)
    );
   
    dataMEM dataMEM_instance(
        .clk(clk),
        .w_en(memWr),
        .wdata(RD2),
        .address(alu_out),
        .data_out(data_mem_out)
    );


    mux2x32 mux2x32_instance_2(
        .Qb(alu_out),
        .im(data_mem_out),
        .sel(Wrback),
        .result(WriteData)
    );


    wire [15:0] SA;
    assign SA = {{11{1'b0}},sa};
    ZeroExt Zeroext_instance_1(
        .im(SA),
        .extend(sa_immd)
    );
    mux2x32 mux2x32_instance_3(
        .Qb(RD1),
        .im(sa_immd),
        .sel(AluSrcA),
        .result(alu_in_a)
    );

    Conunit Conunit_instance(
        .Func(func),
        .Op(op),
        .rt(rt),
        .Zero(Zero),
        .Sign(Sign),
        .Aluc(Aluc),
        .AluSrcA(AluSrcA),
        .AluSrcB(AluSrcB),
        .PcSrc(PcSrc),
        .Wrback(Wrback),
        .RegDst(RegDst),
        .ExtSe(ExtSe),
        .memWr(memWr),
        .regWr(regWr)
    );

    mux4 mux4(
        .pc_add4(pc_add4),
        .zero(Zero),
        .branch(pc_branch),
        .pc_jump(pc_jump),
        .sel(PcSrc),
        .result(next_pc)
    );

    assign pc_jump = (func == `funcJR)? pc_jr : pc_j_jal;

endmodule
module SingleCycleCPU(
    input wire clk,
    input wire rst_n
);


    wire [31:0] pc;
    wire [31:0] next_pc;
    wire [31:0] pc_add4;
    wire [31:0] pc_branch;
    wire [31:0] pc_jump;



    wire [31:0] inst;
    wire [5:0] op;
    wire [5:0] func;
    wire [4:0] sa;
    wire [4:0] rs;
    wire [4:0] rt;
    wire [4:0] rd;
    wire [15:0] immd16;
    wire [25:0] immd26;


    wire regWr;
    wire [4:0] WriteReg;

    wire [31:0] WriteData;



    wire [31:0] RD1;
    wire [31:0] RD2;




    wire  Zero;
    wire        Sign;
    wire  [3:0] Aluc;
    wire  AluSrcA;
    wire  AluSrcB;
    wire  [1:0] PcSrc;
    wire  Wrback;
    wire  RegDst;
    wire  ExtSe;
    wire  memWr;


    wire  [31:0] Extendimmd;
    wire  [31:0] immd_pc;
    wire  [31:0] alu_in_a;
    wire  [31:0] alu_in_b;
    wire  [31:0] alu_out;
    wire  [31:0] data_mem_out;
    wire  [31:0] sa_immd;
   
    PC pc_instance(
        .clk(clk),
        .rst_n(rst_n),
        .next_pc(next_pc),
        .pc(pc)
    );

    PCAdd pc_add4_instance(
        .pc(pc),
        .pc_add4(pc_add4)
    );

    instMEM instMEM_instance(
        .pc(pc),
	    .inst(inst)
    );

    decoder decoder_instance(
        .ins(inst),
        .op(op),
        .func(func),
        .sa(sa),
        .rs(rs),
        .rt(rt),
        .rd(rd),
        .immd16(immd16),
        .immd26(immd26)
    );

    wire [31:0] pc_jr;
    RegFile RegFile_instance(
        .clk(clk),
        .rst_n(rst_n),
        .regWr(regWr),
        .RdReg1(rs),
        .RdReg2(rt),
        .WrReg(WriteReg),
        .WriteData(WriteData),
        .RD1(RD1),
        .RD2(RD2)
    );
    assign pc_jr = RD1;

    mux2 mux2_instance(
        .rd(rd),
        .rt(rt),
        .sel(RegDst),
        .result(WriteReg)
    );

    Extend Extend_instance(
        .ExtSe(ExtSe),
        .immd16(immd16),
        .Extout(Extendimmd)
    );

    Lshift Lshift_instance(
        .in(Extendimmd),
        .shift(immd_pc)
    );

    PC_branch PC_branch_instance(
        .immd_pc(immd_pc),
        .pc_add4(pc_add4),
        .pc_branch(pc_branch)
    );

    mux2x32 mux2x32_instance_1(
        .Qb(RD2),
        .im(Extendimmd),
        .sel(AluSrcB),
        .result(alu_in_b)
    );

    wire [31:0] pc_j_jal;
    Jshift Jshift_instance(
        .inst(immd26),
        .pc_add4(pc_add4),
        .sh(pc_j_jal)
    );

    ALU ALU_instance(
        .Aluc(Aluc),
        .a(alu_in_a),
        .b(alu_in_b),
        .out(alu_out),
        .zero(Zero),
        .sign(Sign)
    );
   
    dataMEM dataMEM_instance(
        .clk(clk),
        .w_en(memWr),
        .wdata(RD2),
        .address(alu_out),
        .data_out(data_mem_out)
    );


    mux2x32 mux2x32_instance_2(
        .Qb(alu_out),
        .im(data_mem_out),
        .sel(Wrback),
        .result(WriteData)
    );


    wire [15:0] SA;
    assign SA = {{11{1'b0}},sa};
    ZeroExt Zeroext_instance_1(
        .im(SA),
        .extend(sa_immd)
    );
    mux2x32 mux2x32_instance_3(
        .Qb(RD1),
        .im(sa_immd),
        .sel(AluSrcA),
        .result(alu_in_a)
    );

    Conunit Conunit_instance(
        .Func(func),
        .Op(op),
        .rt(rt),
        .Zero(Zero),
        .Sign(Sign),
        .Aluc(Aluc),
        .AluSrcA(AluSrcA),
        .AluSrcB(AluSrcB),
        .PcSrc(PcSrc),
        .Wrback(Wrback),
        .RegDst(RegDst),
        .ExtSe(ExtSe),
        .memWr(memWr),
        .regWr(regWr)
    );

    mux4 mux4(
        .pc_add4(pc_add4),
        .zero(Zero),
        .branch(pc_branch),
        .pc_jump(pc_jump),
        .sel(PcSrc),
        .result(next_pc)
    );

    assign pc_jump = (func == `funcJR)? pc_jr : pc_j_jal;

endmodule