data/full_repos/permissive/50724111/vga/rtl/verilog/vga_controller.v
1: b"%Error: data/full_repos/permissive/50724111/vga/rtl/verilog/vga_controller.v:24: Cannot find file containing module: 'vga_sync_generator'\n    vga_sync_generator vga_sync(\n    ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/50724111/vga/rtl/verilog,data/full_repos/permissive/50724111/vga_sync_generator\n             data/full_repos/permissive/50724111/vga/rtl/verilog,data/full_repos/permissive/50724111/vga_sync_generator.v\n             data/full_repos/permissive/50724111/vga/rtl/verilog,data/full_repos/permissive/50724111/vga_sync_generator.sv\n             vga_sync_generator\n             vga_sync_generator.v\n             vga_sync_generator.sv\n             obj_dir/vga_sync_generator\n             obj_dir/vga_sync_generator.v\n             obj_dir/vga_sync_generator.sv\n%Error: data/full_repos/permissive/50724111/vga/rtl/verilog/vga_controller.v:37: Cannot find file containing module: 'img_data'\n    img_data img_data_inst (\n    ^~~~~~~~\n%Error: data/full_repos/permissive/50724111/vga/rtl/verilog/vga_controller.v:47: Cannot find file containing module: 'img_index'\n    img_index img_index_inst (\n    ^~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module vga_controller(
    input reset,
    input sys_clk,
    input vga_clk,
    output blank_n,
    output HS,
    output VS,
    output [7:0] red,
    output [7:0] green,  
    output [7:0] blue
);

    wire [10:0] pixel_h;
    wire [10:0] pixel_v;
    reg [7:0] r_red;
    reg [7:0] r_green;
    reg [7:0] r_blue;
    
    wire [7:0] colour_index;
    wire [23:0] rgb;
    reg [18:0] img_read_address;
    wire [31:0] next_pixel_addr;

    vga_sync_generator vga_sync(
        .reset(reset),
        .vga_clk(vga_clk),
        .blank_n(blank_n),
        .next_pixel_h(pixel_h),
        .next_pixel_v(pixel_v),
        .next_pixel_addr(next_pixel_addr),
        .HS(HS),
        .VS(VS)
    );
    
    

    img_data img_data_inst (
        .q (colour_index),
        .d(8'b0),
        .read_address(img_read_address),
        .write_address(19'b0),
        .we(1'b0),
        .clk(sys_clk)
    );
    

    img_index img_index_inst (
        .q (rgb),
        .d(8'b0),
        .read_address(colour_index),
        .write_address(8'b0),
        .we(1'b0),
        .clk(sys_clk)
    );
    
    
    always@(posedge vga_clk) begin

        img_read_address <= next_pixel_addr[18:0];
    end
    
    
    assign red   = rgb[23:16];
    assign green = rgb[15:8];
    assign blue  = rgb[7:0];
    

    
endmodule
module vga_controller(
    input reset,
    input sys_clk,
    input vga_clk,
    output blank_n,
    output HS,
    output VS,
    output [7:0] red,
    output [7:0] green,  
    output [7:0] blue
);


    wire [10:0] pixel_h;
    wire [10:0] pixel_v;
    reg [7:0] r_red;
    reg [7:0] r_green;
    reg [7:0] r_blue;
    
    wire [7:0] colour_index;
    wire [23:0] rgb;
    reg [18:0] img_read_address;
    wire [31:0] next_pixel_addr;

    vga_sync_generator vga_sync(
        .reset(reset),
        .vga_clk(vga_clk),
        .blank_n(blank_n),
        .next_pixel_h(pixel_h),
        .next_pixel_v(pixel_v),
        .next_pixel_addr(next_pixel_addr),
        .HS(HS),
        .VS(VS)
    );
    
    

    img_data img_data_inst (
        .q (colour_index),
        .d(8'b0),
        .read_address(img_read_address),
        .write_address(19'b0),
        .we(1'b0),
        .clk(sys_clk)
    );
    

    img_index img_index_inst (
        .q (rgb),
        .d(8'b0),
        .read_address(colour_index),
        .write_address(8'b0),
        .we(1'b0),
        .clk(sys_clk)
    );
    
    
    always@(posedge vga_clk) begin

        img_read_address <= next_pixel_addr[18:0];
    end
    
    
    assign red   = rgb[23:16];
    assign green = rgb[15:8];
    assign blue  = rgb[7:0];
    

    
endmodule