data/full_repos/permissive/515100461/sequential/execute_tb.v
1: b'%Error: data/full_repos/permissive/515100461/sequential/execute_tb.v:1: Cannot find include file: fetch.v\n`include"fetch.v" \n        ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/515100461/sequential,data/full_repos/permissive/515100461/fetch.v\n             data/full_repos/permissive/515100461/sequential,data/full_repos/permissive/515100461/fetch.v.v\n             data/full_repos/permissive/515100461/sequential,data/full_repos/permissive/515100461/fetch.v.sv\n             fetch.v\n             fetch.v.v\n             fetch.v.sv\n             obj_dir/fetch.v\n             obj_dir/fetch.v.v\n             obj_dir/fetch.v.sv\n%Error: data/full_repos/permissive/515100461/sequential/execute_tb.v:2: Cannot find include file: decode.v\n`include "decode.v" \n         ^~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/execute_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/execute_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;PC=valP;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/515100461/sequential/execute_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #10 clk=~clk;\n    ^\n%Error: data/full_repos/permissive/515100461/sequential/execute_tb.v:56: Unsupported or unknown PLI call: $monitor\n  $monitor("clk=%d PC = %d icode=%b ifun=%b rA=%b rB=%b valA=%d valB=%d valE=%d\\n",clk,PC,icode,ifun,rA,rB,valA,valB,valE);\n  ^~~~~~~~\n%Error: Exiting due to 3 error(s), 3 warning(s)\n'
module fetchdecodetb;
  reg clk;
  wire cnd;
  reg [63:0] PC;
  reg [63:0] reg_mem[0:14];

  wire [3:0] icode,ifun,rA,rB;

  wire signed [63:0] valC,valP,valA,valB,valE;


fetch uut1(clk,PC,icode,ifun,rA,rB,valP,valC);

decode uut2(icode,clk,rA,rB,reg_mem[rA],reg_mem[rB],reg_mem[4],valA,valB);

execute uut3(icode,ifun,clk,valA,valB,valC,valE,cnd);

  initial begin
    reg_mem[0]=64'd0;
    reg_mem[1]=64'd1;
    reg_mem[2]=64'd2;
    reg_mem[3]=64'd3;
    reg_mem[4]=64'd4;
    reg_mem[5]=64'd5;
    reg_mem[6]=64'd6;
    reg_mem[7]=64'd7;
    reg_mem[8]=64'd8;
    reg_mem[9]=64'd9;
    reg_mem[10]=64'd10;
    reg_mem[11]=64'd11;
    reg_mem[12]=64'd12;
    reg_mem[13]=64'd13;
    reg_mem[14]=64'd14;



    clk=1;PC=64'd19;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;










  end 

  initial 
		$monitor("clk=%d PC = %d icode=%b ifun=%b rA=%b rB=%b valA=%d valB=%d valE=%d\n",clk,PC,icode,ifun,rA,rB,valA,valB,valE);
endmodule
module fetchdecodetb;

  reg clk;
  wire cnd;
  reg [63:0] PC;
  reg [63:0] reg_mem[0:14];

  wire [3:0] icode,ifun,rA,rB;

  wire signed [63:0] valC,valP,valA,valB,valE;


fetch uut1(clk,PC,icode,ifun,rA,rB,valP,valC);

decode uut2(icode,clk,rA,rB,reg_mem[rA],reg_mem[rB],reg_mem[4],valA,valB);

execute uut3(icode,ifun,clk,valA,valB,valC,valE,cnd);

  initial begin
    reg_mem[0]=64'd0;
    reg_mem[1]=64'd1;
    reg_mem[2]=64'd2;
    reg_mem[3]=64'd3;
    reg_mem[4]=64'd4;
    reg_mem[5]=64'd5;
    reg_mem[6]=64'd6;
    reg_mem[7]=64'd7;
    reg_mem[8]=64'd8;
    reg_mem[9]=64'd9;
    reg_mem[10]=64'd10;
    reg_mem[11]=64'd11;
    reg_mem[12]=64'd12;
    reg_mem[13]=64'd13;
    reg_mem[14]=64'd14;



    clk=1;PC=64'd19;
    #10 clk=~clk;
    #10 clk=~clk;PC=valP;
    #10 clk=~clk;










  end 

  initial 
		$monitor("clk=%d PC = %d icode=%b ifun=%b rA=%b rB=%b valA=%d valB=%d valE=%d\n",clk,PC,icode,ifun,rA,rB,valA,valB,valE);
endmodule