data/full_repos/permissive/522401967/verilog/rtl/user_project_wrapper.v
1: b"%Error: data/full_repos/permissive/522401967/verilog/rtl/user_project_wrapper.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/522401967/verilog/rtl/user_project_wrapper.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/522401967/verilog/rtl/user_project_wrapper.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/522401967/verilog/rtl/user_project_wrapper.v:72: Define or directive not defined: '`MPRJ_IO_PADS'\n    inout [`MPRJ_IO_PADS-10:0] analog_io,\n           ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module user_project_wrapper #(
    parameter BITS = 32
) (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,





    inout [`MPRJ_IO_PADS-10:0] analog_io,


    input   user_clock2,


    output [2:0] user_irq
);

    wire            rx_data_vb;
    wire    [7:0]   rx_data;
    wire    [7:0]   rx_mem_out;
    wire    [9:0]   rx_addr;
    wire            wmask0;
    wire            csb1;
    wire    [7:0]   dout0;

    Vthernet_MAC Vthernet_MAC(
    `ifdef USE_POWER_PINS
        .vccd1  (vccd1          ),
        .vssd1  (vssd1          ),
    `endif
        .rst        (wb_rst_i   ),

        .wb_clk_i   (wb_clk_i   ),
        .wb_rst_i   (wb_rst_i   ),
        .wbs_stb_i  (wbs_stb_i  ),
        .wbs_cyc_i  (wbs_cyc_i  ),
        .wbs_we_i   (wbs_we_i   ),
        .wbs_sel_i  (wbs_sel_i  ),
        .wbs_dat_i  (wbs_dat_i  ),
        .wbs_adr_i  (wbs_adr_i  ),
        .wbs_ack_o  (wbs_ack_o  ),
        .wbs_dat_o  (wbs_dat_o  ),

        .GTX_CLK    (io_out[0]  ),
        .TX_EN      (io_out[1]  ),
        .TXD        (io_out[9:2]),
        .TX_ER      (io_out[10] ),
        .RX_CLK     (io_in[11]  ),
        .RX_DV      (io_in[12]  ),
        .RXD        (io_in[20:13]),
        .RX_ER      (io_in[21]  ),
        .MDC        (io_in[22]  ),
        .MDIO       (io_in[23]  ),

        .rx_irq     (user_irq[0]),

        .rx_data_vb (rx_data_vb ),
        .rx_data    (rx_data    ),
        .rx_mem_out (rx_mem_out ),
        .rx_addr    (rx_addr    ),
        .wmask0     (wmask0     ),
        .csb1       (csb1       ),
        .io_oeb     (io_oeb[23:0]),
        .dout0      (dout0      )
    );




    sky130_sram_1kbyte_1rw1r_8x1024_8 #(.NUM_WMASKS(2)) rx_mem(
    `ifdef USE_POWER_PINS
        .vccd1  (vccd1          ),
        .vssd1  (vssd1          ),
    `endif

        .clk0   (RX_CLK         ),
        .csb0   (rx_data_vb     ),
        .web0   (rx_data_vb     ),
        .wmask0 ({wmask0, wmask0}),
        .addr0  (rx_addr        ),
        .din0   (rx_data        ),
        .dout0  (dout0          ),

        .clk1   (wb_clk_i       ),
        .csb1   (csb1           ),
        .addr1  (wbs_adr_i[9:0] ),
        .dout1  (rx_mem_out     )
    );

endmodule
module user_project_wrapper #(
    parameter BITS = 32
) (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,





    inout [`MPRJ_IO_PADS-10:0] analog_io,


    input   user_clock2,


    output [2:0] user_irq
);


    wire            rx_data_vb;
    wire    [7:0]   rx_data;
    wire    [7:0]   rx_mem_out;
    wire    [9:0]   rx_addr;
    wire            wmask0;
    wire            csb1;
    wire    [7:0]   dout0;

    Vthernet_MAC Vthernet_MAC(
    `ifdef USE_POWER_PINS
        .vccd1  (vccd1          ),
        .vssd1  (vssd1          ),
    `endif
        .rst        (wb_rst_i   ),

        .wb_clk_i   (wb_clk_i   ),
        .wb_rst_i   (wb_rst_i   ),
        .wbs_stb_i  (wbs_stb_i  ),
        .wbs_cyc_i  (wbs_cyc_i  ),
        .wbs_we_i   (wbs_we_i   ),
        .wbs_sel_i  (wbs_sel_i  ),
        .wbs_dat_i  (wbs_dat_i  ),
        .wbs_adr_i  (wbs_adr_i  ),
        .wbs_ack_o  (wbs_ack_o  ),
        .wbs_dat_o  (wbs_dat_o  ),

        .GTX_CLK    (io_out[0]  ),
        .TX_EN      (io_out[1]  ),
        .TXD        (io_out[9:2]),
        .TX_ER      (io_out[10] ),
        .RX_CLK     (io_in[11]  ),
        .RX_DV      (io_in[12]  ),
        .RXD        (io_in[20:13]),
        .RX_ER      (io_in[21]  ),
        .MDC        (io_in[22]  ),
        .MDIO       (io_in[23]  ),

        .rx_irq     (user_irq[0]),

        .rx_data_vb (rx_data_vb ),
        .rx_data    (rx_data    ),
        .rx_mem_out (rx_mem_out ),
        .rx_addr    (rx_addr    ),
        .wmask0     (wmask0     ),
        .csb1       (csb1       ),
        .io_oeb     (io_oeb[23:0]),
        .dout0      (dout0      )
    );




    sky130_sram_1kbyte_1rw1r_8x1024_8 #(.NUM_WMASKS(2)) rx_mem(
    `ifdef USE_POWER_PINS
        .vccd1  (vccd1          ),
        .vssd1  (vssd1          ),
    `endif

        .clk0   (RX_CLK         ),
        .csb0   (rx_data_vb     ),
        .web0   (rx_data_vb     ),
        .wmask0 ({wmask0, wmask0}),
        .addr0  (rx_addr        ),
        .din0   (rx_data        ),
        .dout0  (dout0          ),

        .clk1   (wb_clk_i       ),
        .csb1   (csb1           ),
        .addr1  (wbs_adr_i[9:0] ),
        .dout1  (rx_mem_out     )
    );

endmodule