data/full_repos/permissive/434840709/lab5/code/top.v
1: b"%Error: data/full_repos/permissive/434840709/lab5/code/top.v:27: Cannot find file containing module: 'clkDiv'\n    clkDiv u1(clk100mhz, clk190hz, clk3hz);\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/434840709/lab5/code,data/full_repos/permissive/434840709/clkDiv\n             data/full_repos/permissive/434840709/lab5/code,data/full_repos/permissive/434840709/clkDiv.v\n             data/full_repos/permissive/434840709/lab5/code,data/full_repos/permissive/434840709/clkDiv.sv\n             clkDiv\n             clkDiv.v\n             clkDiv.sv\n             obj_dir/clkDiv\n             obj_dir/clkDiv.v\n             obj_dir/clkDiv.sv\n%Error: data/full_repos/permissive/434840709/lab5/code/top.v:30: Cannot find file containing module: 'read'\n    read  u2(clk190hz, rst_, sel_, but1, but2, but3, but4, but5, but6, but7, but8, pos1, seg1); \n    ^~~~\n%Error: data/full_repos/permissive/434840709/lab5/code/top.v:33: Cannot find file containing module: 'calculate'\n    calculate  u3(clk190hz, rst_, sel_, but1, but2, but3, but4, but5, but6, but7, but8, pos2, seg2);\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/434840709/lab5/code/top.v:35: Cannot find file containing module: 'press'\n    press  c1(clk190hz, rst, rst_);\n    ^~~~~\n%Error: data/full_repos/permissive/434840709/lab5/code/top.v:36: Cannot find file containing module: 'press'\n    press  c2(clk190hz, sel, sel_);\n    ^~~~~\n%Error: Exiting due to 5 error(s)\n"
module top(
    input clk100mhz,
    input rst,
    input sel,

    input but1,
    input but2,
    input but3,
    input but4,

    input but5,
    input but6,
    input but7,
    input but8,

    output [3:0] pos1,
    output [7:0] seg1,

    output [3:0] pos2,
    output [7:0] seg2
);
    wire clk190hz, clk3hz;
    wire rst_, sel_;
    
    clkDiv u1(clk100mhz, clk190hz, clk3hz);


    read  u2(clk190hz, rst_, sel_, but1, but2, but3, but4, but5, but6, but7, but8, pos1, seg1); 
    

    calculate  u3(clk190hz, rst_, sel_, but1, but2, but3, but4, but5, but6, but7, but8, pos2, seg2);
    
    press  c1(clk190hz, rst, rst_);
    press  c2(clk190hz, sel, sel_);
endmodule
module top(
    input clk100mhz,
    input rst,
    input sel,

    input but1,
    input but2,
    input but3,
    input but4,

    input but5,
    input but6,
    input but7,
    input but8,

    output [3:0] pos1,
    output [7:0] seg1,

    output [3:0] pos2,
    output [7:0] seg2
);

    wire clk190hz, clk3hz;
    wire rst_, sel_;
    
    clkDiv u1(clk100mhz, clk190hz, clk3hz);


    read  u2(clk190hz, rst_, sel_, but1, but2, but3, but4, but5, but6, but7, but8, pos1, seg1); 
    

    calculate  u3(clk190hz, rst_, sel_, but1, but2, but3, but4, but5, but6, but7, but8, pos2, seg2);
    
    press  c1(clk190hz, rst, rst_);
    press  c2(clk190hz, sel, sel_);
endmodule