data/full_repos/permissive/475371394/generators/cgra2x2/src/main/resources/register_32b.v
data/verilator_xmls/a2e93f2c-5587-41f4-9d52-85f4de7be195.xml
module register_32b(CGRA_Clock, CGRA_Reset, in, out);
    parameter size = 32;

    input CGRA_Clock, CGRA_Reset;
    input [size-1:0] in;
    output reg [size-1:0] out;
    always @(posedge CGRA_Clock, posedge CGRA_Reset)
        if (CGRA_Reset == 1)
            out <= 0;
        else
            out <= in;
endmodule
module register_32b(CGRA_Clock, CGRA_Reset, in, out);

    parameter size = 32;

    input CGRA_Clock, CGRA_Reset;
    input [size-1:0] in;
    output reg [size-1:0] out;
    always @(posedge CGRA_Clock, posedge CGRA_Reset)
        if (CGRA_Reset == 1)
            out <= 0;
        else
            out <= in;
endmodule