data/full_repos/permissive/509809169/Circuits/Sequential Logic/Latches and Flip Flops/DFFs and gates.v
1: b'%Error: Cannot find file containing module: Logic/Latches\n        ... Looked in:\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Latches\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Latches.v\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Latches.sv\n             Logic/Latches\n             Logic/Latches.v\n             Logic/Latches.sv\n             obj_dir/Logic/Latches\n             obj_dir/Logic/Latches.v\n             obj_dir/Logic/Latches.sv\n%Error: Cannot find file containing module: and\n%Error: Cannot find file containing module: Flip\n%Error: Cannot find file containing module: Flops,data/full_repos/permissive/509809169\n%Error: Cannot find file containing module: data/full_repos/permissive/509809169/Circuits/Sequential\n%Error: Cannot find file containing module: Flops/DFFs\n%Error: Cannot find file containing module: gates.v\n%Error: Exiting due to 7 error(s)\n'
module top_module (
    input clk,
    input x,
    output z
); 
    reg [2:0]w;



    always @(posedge clk) begin
        w[0]<=x^w[0];
        w[1] <= x & ~w[1];
        w[2] <= x | ~w[2];
        
    end
    assign z = ~(w[0]|w[1]|w[2]);
endmodule
module top_module (
    input clk,
    input x,
    output z
);
 
    reg [2:0]w;



    always @(posedge clk) begin
        w[0]<=x^w[0];
        w[1] <= x & ~w[1];
        w[2] <= x | ~w[2];
        
    end
    assign z = ~(w[0]|w[1]|w[2]);
endmodule