data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:111: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_in;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:112: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_out;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:113: Define or directive not defined: '`MPRJ_IO_PADS'\n    wire [`MPRJ_IO_PADS-1:0] io_oeb;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:125: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_out = {user_gpio_out, pwmA_q0, pwmB_q0, pwmC_q0, pwmA_n0, pwmB_n0, pwmC_n0, user_halt, {(`MPRJ_IO_PADS-1-8-6-1){1'b0}}};\n                                                                                                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501415069/verilog/rtl/user_proj_example.v:126: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_oeb = {user_gpio_en,  {(`MPRJ_IO_PADS-1-8){rst}}};\n                                      ^~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module user_proj_example #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,


    output [2:0] irq
);
    
    wire [7:0] inAddress, inRom, inRam, inPage, inValue;
    wire       masterWrite, writeRom, writeRam, writePage;
    wire [7:0] user_abus, user_dfor;
    wire       user_romce  = (user_abus[7:6] == 2'b00);
    wire       user_ramce  = (user_abus[7:6] == 2'b01);
    wire       user_pagece = (user_abus[7:6] == 2'b10);
    wire       user_ioce   = (user_abus[7:6] == 2'b11);
    wire [3:0] user_masce  = {user_romce, user_ramce, user_pagece, user_ioce};
    
    wire       user_halt, user_rd, user_wr;
    wire [7:0] user_rom, user_ram, user_page;
    wire [7:0] user_dback = (user_romce)  ? user_rom   : 
                            (user_ramce)  ? user_ram   : 
                            (user_pagece) ? user_page  : 
                            (user_ioce)   ? user_iobus : 8'h00;
    
    wire [2:0] pstate;
    wire [7:0] regR0, regR1, regR2, regR3;
    wire       pwmA_q0, pwmA_n0;
    wire       pwmB_q0, pwmB_n0;
    wire       pwmC_q0, pwmC_n0;
    wire [7:0] user_gpio_in, user_gpio_en, user_gpio_out;
    wire [7:0] user_ioGPIO;
    wire [7:0] user_ioPWMA;
    wire [7:0] user_ioPWMB;
    wire [7:0] user_ioPWMC;
    wire       user_ioGPIOce = user_ioce & (user_abus[5:4] == 2'b00);
    wire       user_ioPWMAce = user_ioce & (user_abus[5:4] == 2'b01);
    wire       user_ioPWMBce = user_ioce & (user_abus[5:4] == 2'b10);
    wire       user_ioPWMCce = user_ioce & (user_abus[5:4] == 2'b11);
    wire [3:0] user_iomasce  = {user_ioGPIOce, user_ioPWMAce, user_ioPWMBce, user_ioPWMCce};
    wire [7:0] user_iobus    = (user_ioGPIOce) ? user_ioGPIO: 
                               (user_ioPWMAce) ? user_ioPWMA: 
                               (user_ioPWMBce) ? user_ioPWMB: 
                               (user_ioPWMCce) ? user_ioPWMC: 8'h00;
    
    wire clk;
    wire rst;

    wire [`MPRJ_IO_PADS-1:0] io_in;
    wire [`MPRJ_IO_PADS-1:0] io_out;
    wire [`MPRJ_IO_PADS-1:0] io_oeb;

    wire valid;
    wire [3:0] wstrb;








    assign io_out = {user_gpio_out, pwmA_q0, pwmB_q0, pwmC_q0, pwmA_n0, pwmB_n0, pwmC_n0, user_halt, {(`MPRJ_IO_PADS-1-8-6-1){1'b0}}};
    assign io_oeb = {user_gpio_en,  {(`MPRJ_IO_PADS-1-8){rst}}};


    assign irq = 3'b000;
    

    assign la_data_out = {pstate, regR0, regR1, regR2, regR3, user_halt, user_gpio_out, user_rd, user_wr, user_abus, user_dfor, user_dback, user_masce, user_iomasce, 1'b0, masterWrite, clk, rst, inRom, inRam, inPage};

    
    assign         clk =  (~la_oenb[0])  ? la_data_in[0]     :  wb_clk_i;
    assign         rst =  (~la_oenb[1])  ? la_data_in[1]     : irst ^ wb_rst_i;
    wire          irst =  (~la_oenb[2])  ? la_data_in[2]     : 1'b1;
    assign masterWrite =  (~la_oenb[3])  ? la_data_in[3]     : 1'b0;
    assign writePage   =  (~la_oenb[4])  ? la_data_in[4]     : 1'b0;
    assign writeRam    =  (~la_oenb[5])  ? la_data_in[5]     : 1'b0;
    assign writeRom    =  (~la_oenb[6])  ? la_data_in[6]     : 1'b0;
    assign inValue     = ~la_oenb[15:7]  ? la_data_in[15:7]  : 8'h00;
    assign inAddress   = ~la_oenb[23:16] ? la_data_in[23:16] : 8'h00;
    
    MinxTop processor (
      .clk(clk)
    , .clr(rst)
    , .pstate(pstate)
    , .regR0(regR0)
    , .regR1(regR1)
    , .regR2(regR2)
    , .regR3(regR3)
    , .abus(user_abus)
    , .dbuso(user_dfor)
    , .dbusi(user_dback)
    , .rd(user_rd)
    , .wr(user_wr)
    , .sig_halt(user_halt)
    );
    
    rom_unit #(6, 8) ROM (
      .address(user_abus)
    , .dbuso(user_rom)
    
    , .clk(clk)
    , .addressw(inAddress)
    , .dbusr(inRom)
    , .dbusw(inValue)
    , .we(writeRom)
    );
    
    ram_unit #(6, 8) RAM (
      .clk(clk)
    , .address(user_abus)
    , .dbuso(user_ram)
    , .dbusi(user_dfor)
    , .ce(user_ramce)
    , .we(user_wr)
    
    , .iaddress(inAddress)
    , .idbuso(inRam)
    , .idbusi(inValue)
    , .ice(masterWrite)
    , .iwe(writePage)
    );
    
    ram_unit #(6, 8) PAGERAM (
      .clk(clk)
    , .address(user_abus)
    , .dbuso(user_page)
    , .dbusi(user_dfor)
    , .ce(user_pagece)
    , .we(user_wr)
    
    , .iaddress(inAddress)
    , .idbuso(inPage)
    , .idbusi(inValue)
    , .ice(masterWrite)
    , .iwe(writeRam)
    );
    
    pwm pmodA (
      .clk(clk)
    , .rst(rst)
    , .address(user_abus[2:0])
    , .databi(user_dfor)
    , .databo(user_ioPWMA)
    , .cen(user_ioPWMAce)
    , .wr(user_wr)
    , .q0(pwmA_q0)
    , .n0(pwmA_n0)
    );

    pwm pmodB (
      .clk(clk)
    , .rst(rst)
    , .address(user_abus[2:0])
    , .databi(user_dfor)
    , .databo(user_ioPWMB)
    , .cen(user_ioPWMBce)
    , .wr(user_wr)
    , .q0(pwmB_q0)
    , .n0(pwmB_n0)
    );

    pwm pmodC (
      .clk(clk)
    , .rst(rst)
    , .address(user_abus[2:0])
    , .databi(user_dfor)
    , .databo(user_ioPWMC)
    , .cen(user_ioPWMCce)
    , .wr(user_wr)
    , .q0(pwmC_q0)
    , .n0(pwmC_n0)
    );
    
    GPIO gpioblock (
      .clk(clk)
    , .rst(rst)
    
    , .address(user_abus[1:0])
    , .databi(user_dfor)
    , .databo(user_ioGPIO)
    , .cen(user_ioGPIOce)
    
    , .wr(user_wr)
    , .port_in (user_gpio_in)
    , .port_en (user_gpio_en)
    , .port_out(user_gpio_out)
    );
    
endmodule
module user_proj_example #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,


    output [2:0] irq
);

    
    wire [7:0] inAddress, inRom, inRam, inPage, inValue;
    wire       masterWrite, writeRom, writeRam, writePage;
    wire [7:0] user_abus, user_dfor;
    wire       user_romce  = (user_abus[7:6] == 2'b00);
    wire       user_ramce  = (user_abus[7:6] == 2'b01);
    wire       user_pagece = (user_abus[7:6] == 2'b10);
    wire       user_ioce   = (user_abus[7:6] == 2'b11);
    wire [3:0] user_masce  = {user_romce, user_ramce, user_pagece, user_ioce};
    
    wire       user_halt, user_rd, user_wr;
    wire [7:0] user_rom, user_ram, user_page;
    wire [7:0] user_dback = (user_romce)  ? user_rom   : 
                            (user_ramce)  ? user_ram   : 
                            (user_pagece) ? user_page  : 
                            (user_ioce)   ? user_iobus : 8'h00;
    
    wire [2:0] pstate;
    wire [7:0] regR0, regR1, regR2, regR3;
    wire       pwmA_q0, pwmA_n0;
    wire       pwmB_q0, pwmB_n0;
    wire       pwmC_q0, pwmC_n0;
    wire [7:0] user_gpio_in, user_gpio_en, user_gpio_out;
    wire [7:0] user_ioGPIO;
    wire [7:0] user_ioPWMA;
    wire [7:0] user_ioPWMB;
    wire [7:0] user_ioPWMC;
    wire       user_ioGPIOce = user_ioce & (user_abus[5:4] == 2'b00);
    wire       user_ioPWMAce = user_ioce & (user_abus[5:4] == 2'b01);
    wire       user_ioPWMBce = user_ioce & (user_abus[5:4] == 2'b10);
    wire       user_ioPWMCce = user_ioce & (user_abus[5:4] == 2'b11);
    wire [3:0] user_iomasce  = {user_ioGPIOce, user_ioPWMAce, user_ioPWMBce, user_ioPWMCce};
    wire [7:0] user_iobus    = (user_ioGPIOce) ? user_ioGPIO: 
                               (user_ioPWMAce) ? user_ioPWMA: 
                               (user_ioPWMBce) ? user_ioPWMB: 
                               (user_ioPWMCce) ? user_ioPWMC: 8'h00;
    
    wire clk;
    wire rst;

    wire [`MPRJ_IO_PADS-1:0] io_in;
    wire [`MPRJ_IO_PADS-1:0] io_out;
    wire [`MPRJ_IO_PADS-1:0] io_oeb;

    wire valid;
    wire [3:0] wstrb;








    assign io_out = {user_gpio_out, pwmA_q0, pwmB_q0, pwmC_q0, pwmA_n0, pwmB_n0, pwmC_n0, user_halt, {(`MPRJ_IO_PADS-1-8-6-1){1'b0}}};
    assign io_oeb = {user_gpio_en,  {(`MPRJ_IO_PADS-1-8){rst}}};


    assign irq = 3'b000;
    

    assign la_data_out = {pstate, regR0, regR1, regR2, regR3, user_halt, user_gpio_out, user_rd, user_wr, user_abus, user_dfor, user_dback, user_masce, user_iomasce, 1'b0, masterWrite, clk, rst, inRom, inRam, inPage};

    
    assign         clk =  (~la_oenb[0])  ? la_data_in[0]     :  wb_clk_i;
    assign         rst =  (~la_oenb[1])  ? la_data_in[1]     : irst ^ wb_rst_i;
    wire          irst =  (~la_oenb[2])  ? la_data_in[2]     : 1'b1;
    assign masterWrite =  (~la_oenb[3])  ? la_data_in[3]     : 1'b0;
    assign writePage   =  (~la_oenb[4])  ? la_data_in[4]     : 1'b0;
    assign writeRam    =  (~la_oenb[5])  ? la_data_in[5]     : 1'b0;
    assign writeRom    =  (~la_oenb[6])  ? la_data_in[6]     : 1'b0;
    assign inValue     = ~la_oenb[15:7]  ? la_data_in[15:7]  : 8'h00;
    assign inAddress   = ~la_oenb[23:16] ? la_data_in[23:16] : 8'h00;
    
    MinxTop processor (
      .clk(clk)
    , .clr(rst)
    , .pstate(pstate)
    , .regR0(regR0)
    , .regR1(regR1)
    , .regR2(regR2)
    , .regR3(regR3)
    , .abus(user_abus)
    , .dbuso(user_dfor)
    , .dbusi(user_dback)
    , .rd(user_rd)
    , .wr(user_wr)
    , .sig_halt(user_halt)
    );
    
    rom_unit #(6, 8) ROM (
      .address(user_abus)
    , .dbuso(user_rom)
    
    , .clk(clk)
    , .addressw(inAddress)
    , .dbusr(inRom)
    , .dbusw(inValue)
    , .we(writeRom)
    );
    
    ram_unit #(6, 8) RAM (
      .clk(clk)
    , .address(user_abus)
    , .dbuso(user_ram)
    , .dbusi(user_dfor)
    , .ce(user_ramce)
    , .we(user_wr)
    
    , .iaddress(inAddress)
    , .idbuso(inRam)
    , .idbusi(inValue)
    , .ice(masterWrite)
    , .iwe(writePage)
    );
    
    ram_unit #(6, 8) PAGERAM (
      .clk(clk)
    , .address(user_abus)
    , .dbuso(user_page)
    , .dbusi(user_dfor)
    , .ce(user_pagece)
    , .we(user_wr)
    
    , .iaddress(inAddress)
    , .idbuso(inPage)
    , .idbusi(inValue)
    , .ice(masterWrite)
    , .iwe(writeRam)
    );
    
    pwm pmodA (
      .clk(clk)
    , .rst(rst)
    , .address(user_abus[2:0])
    , .databi(user_dfor)
    , .databo(user_ioPWMA)
    , .cen(user_ioPWMAce)
    , .wr(user_wr)
    , .q0(pwmA_q0)
    , .n0(pwmA_n0)
    );

    pwm pmodB (
      .clk(clk)
    , .rst(rst)
    , .address(user_abus[2:0])
    , .databi(user_dfor)
    , .databo(user_ioPWMB)
    , .cen(user_ioPWMBce)
    , .wr(user_wr)
    , .q0(pwmB_q0)
    , .n0(pwmB_n0)
    );

    pwm pmodC (
      .clk(clk)
    , .rst(rst)
    , .address(user_abus[2:0])
    , .databi(user_dfor)
    , .databo(user_ioPWMC)
    , .cen(user_ioPWMCce)
    , .wr(user_wr)
    , .q0(pwmC_q0)
    , .n0(pwmC_n0)
    );
    
    GPIO gpioblock (
      .clk(clk)
    , .rst(rst)
    
    , .address(user_abus[1:0])
    , .databi(user_dfor)
    , .databo(user_ioGPIO)
    , .cen(user_ioGPIOce)
    
    , .wr(user_wr)
    , .port_in (user_gpio_in)
    , .port_en (user_gpio_en)
    , .port_out(user_gpio_out)
    );
    
endmodule