data/full_repos/permissive/509335294/regmem.v
data/verilator_xmls/d394f2c7-3511-4459-a2cb-b57e18ad5291.xml
module regmem(
	input[15:0] wdata, 						
	input[2:0] r_addr1, r_addr2, w_addr,
	input clk,rst,we,	 							
	output[15:0] out_port1, out_port2 
	);
	
	integer i;
	reg [15:0] registry [0:6];



always@(posedge clk) begin
	
	registry[0] <= 16'b0;
	registry[6] <= 16'b0;
	

	if(~rst) begin
	for(i=0; i<6; i=i+1)
			registry[i] <= 16'b0;
	end
		
	if (we) begin
		if(w_addr == 0)begin

		end 
		else registry[w_addr] <= wdata;
	end
		

end

assign out_port1 = (r_addr1 == 0) ? 16'b0 : registry[r_addr1];
assign out_port2 = (r_addr2 == 0) ? 16'b0 : registry[r_addr2];

endmodule
module regmem(
	input[15:0] wdata, 						
	input[2:0] r_addr1, r_addr2, w_addr,
	input clk,rst,we,	 							
	output[15:0] out_port1, out_port2 
	);

	
	integer i;
	reg [15:0] registry [0:6];



always@(posedge clk) begin
	
	registry[0] <= 16'b0;
	registry[6] <= 16'b0;
	

	if(~rst) begin
	for(i=0; i<6; i=i+1)
			registry[i] <= 16'b0;
	end
		
	if (we) begin
		if(w_addr == 0)begin

		end 
		else registry[w_addr] <= wdata;
	end
		

end

assign out_port1 = (r_addr1 == 0) ? 16'b0 : registry[r_addr1];
assign out_port2 = (r_addr2 == 0) ? 16'b0 : registry[r_addr2];

endmodule