data/full_repos/permissive/423852699/tb/bram_test.v
data/verilator_xmls/cc7421ab-e11e-45a8-bd32-c62b87be1591.xml
module bram (
    input wire clka,
    input wire ena,
    input wire wea,
    input wire[13:0] addra,
    input wire[31:0] dina,
    output wire[31:0] douta
);
    reg[31:0] component[0:8191];

    assign douta = component[addra[12:0]];

    always @(posedge clka) begin
        if (wea) begin
            component[addra[12:0]] <= dina;
        end
    end
endmodule
module bram (
    input wire clka,
    input wire ena,
    input wire wea,
    input wire[13:0] addra,
    input wire[31:0] dina,
    output wire[31:0] douta
);

    reg[31:0] component[0:8191];

    assign douta = component[addra[12:0]];

    always @(posedge clka) begin
        if (wea) begin
            component[addra[12:0]] <= dina;
        end
    end
endmodule