data/full_repos/permissive/525152535/RAM16S1.v
data/verilator_xmls/66f58be3-066e-414e-a20b-9680dd9cb59d.xml
module RAM16S1
#(
    parameter [15:0] INIT_0 = 16'h0
)
(
    input        CLK,
    input        WRE,
    input  [3:0] AD,
    input        DI,
    output       DO
);

    reg [15:0] _r_mem;
    
    initial begin
    
        _r_mem = INIT_0;
    end
    
    always @(posedge CLK) begin
    
        if (WRE) begin
            _r_mem[AD] <= DI;
        end
    end
    
    assign DO = _r_mem[AD];

endmodule
module RAM16S1
#(
    parameter [15:0] INIT_0 = 16'h0
)
(
    input        CLK,
    input        WRE,
    input  [3:0] AD,
    input        DI,
    output       DO
);


    reg [15:0] _r_mem;
    
    initial begin
    
        _r_mem = INIT_0;
    end
    
    always @(posedge CLK) begin
    
        if (WRE) begin
            _r_mem[AD] <= DI;
        end
    end
    
    assign DO = _r_mem[AD];

endmodule