data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_ddr_pad_txrx_zctl.v
data/verilator_xmls/f31f92e5-cbc6-408f-8133-a8a196c5c6a3.xml
module bw_io_ddr_pad_txrx_zctl(

   out, 

   pad, 

   vrefcode, vdd_h, cbu, cbd, data, oe, odt_enable
   );


input [7:0]     vrefcode;
input           odt_enable;
input           vdd_h;
input [8:1]     cbu;
input [8:1]     cbd;
input           data;
input           oe;

inout           pad;


output          out;





assign pad = oe ? data : 1'bz;
assign out = pad;






endmodule
module bw_io_ddr_pad_txrx_zctl(

   out, 

   pad, 

   vrefcode, vdd_h, cbu, cbd, data, oe, odt_enable
   );



input [7:0]     vrefcode;
input           odt_enable;
input           vdd_h;
input [8:1]     cbu;
input [8:1]     cbd;
input           data;
input           oe;

inout           pad;


output          out;





assign pad = oe ? data : 1'bz;
assign out = pad;






endmodule