data/full_repos/permissive/507564148/code/expand/7_led.v
1: b"%Error: data/full_repos/permissive/507564148/code/expand/7_led.v:21: Cannot find file containing module: 'Binary_To_7Segment'\nBinary_To_7Segment L1(.Binary(act_time[15:12]),.r_Hex_Encoding(LE1));\n^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507564148/code/expand,data/full_repos/permissive/507564148/Binary_To_7Segment\n             data/full_repos/permissive/507564148/code/expand,data/full_repos/permissive/507564148/Binary_To_7Segment.v\n             data/full_repos/permissive/507564148/code/expand,data/full_repos/permissive/507564148/Binary_To_7Segment.sv\n             Binary_To_7Segment\n             Binary_To_7Segment.v\n             Binary_To_7Segment.sv\n             obj_dir/Binary_To_7Segment\n             obj_dir/Binary_To_7Segment.v\n             obj_dir/Binary_To_7Segment.sv\n%Error: data/full_repos/permissive/507564148/code/expand/7_led.v:22: Cannot find file containing module: 'Binary_To_7Segment'\nBinary_To_7Segment L2(.Binary(act_time[11:8]),.r_Hex_Encoding(LE2));\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/507564148/code/expand/7_led.v:23: Cannot find file containing module: 'Binary_To_7Segment'\nBinary_To_7Segment L3(.Binary(act_time[7:4]),.r_Hex_Encoding(LE3));\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/507564148/code/expand/7_led.v:24: Cannot find file containing module: 'Binary_To_7Segment'\nBinary_To_7Segment L4(.Binary(act_time[3:0]),.r_Hex_Encoding(LE4));\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/507564148/code/expand/7_led.v:26: Cannot find file containing module: 'Binary_To_7Segment'\nBinary_To_7Segment L5(.Binary(max_result[15:12]),.r_Hex_Encoding(LE5));\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/507564148/code/expand/7_led.v:27: Cannot find file containing module: 'Binary_To_7Segment'\nBinary_To_7Segment L6(.Binary(max_result[11:8]),.r_Hex_Encoding(LE6));\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/507564148/code/expand/7_led.v:28: Cannot find file containing module: 'Binary_To_7Segment'\nBinary_To_7Segment L7(.Binary(max_result[7:4]),.r_Hex_Encoding(LE7));\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/507564148/code/expand/7_led.v:29: Cannot find file containing module: 'Binary_To_7Segment'\nBinary_To_7Segment L8(.Binary(max_result[3:0]),.r_Hex_Encoding(LE8));\n^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module seven_led (
    input [2:0] state,
    input [15:0] act_time,
    input [15:0] max_result,
    input clk,
    output reg[6:0] LED1,
    output reg[6:0] LED2,
    output reg[6:0] LED3,
    output reg[6:0] LED4
);

wire[6:0] LE1;
wire[6:0] LE2;
wire[6:0] LE3;
wire[6:0] LE4;

wire[6:0] LE5;
wire[6:0] LE6;
wire[6:0] LE7;
wire[6:0] LE8;
Binary_To_7Segment L1(.Binary(act_time[15:12]),.r_Hex_Encoding(LE1));
Binary_To_7Segment L2(.Binary(act_time[11:8]),.r_Hex_Encoding(LE2));
Binary_To_7Segment L3(.Binary(act_time[7:4]),.r_Hex_Encoding(LE3));
Binary_To_7Segment L4(.Binary(act_time[3:0]),.r_Hex_Encoding(LE4));

Binary_To_7Segment L5(.Binary(max_result[15:12]),.r_Hex_Encoding(LE5));
Binary_To_7Segment L6(.Binary(max_result[11:8]),.r_Hex_Encoding(LE6));
Binary_To_7Segment L7(.Binary(max_result[7:4]),.r_Hex_Encoding(LE7));
Binary_To_7Segment L8(.Binary(max_result[3:0]),.r_Hex_Encoding(LE8));
parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b111, S5 = 3'b110;

always @(posedge clk) begin
   case (state)

    S0:
    begin
        LED1 <= 7'b0000000;
        LED2 <= 7'b1110001;
        LED3 <= 7'b0111111;
        LED4 <= 7'b0111110;
    end

    S1:
    begin
        LED1 <= 7'b1000000;
        LED2 <= 7'b1000000;
        LED3 <= 7'b1000000;
        LED4 <= 7'b1000000;
    end

    S3:
    begin
        LED1 <= 7'b0000110;
        LED2 <= 7'b0000110;
        LED3 <= 7'b0000110;
        LED4 <= 7'b0000110;
    end

    S2:
    begin
        LED1 <= 7'b1110001;
        LED2 <= 7'b1110111;
        LED3 <= 7'b0000110;
        LED4 <= 7'b0111000;
    end

    S4:
    begin
        LED1 <= LE1;
        LED2 <= LE2;
        LED3 <= LE3;
        LED4 <= LE4;
    end
    S5:
    begin
        LED1 <= LE5;
        LED2 <= LE6;
        LED3 <= LE7;
        LED4 <= LE8;
    end
    default:
    begin
        LED1 <= 7'b0111111;
        LED2 <= 7'b0111111;
        LED3 <= 7'b0111111;
        LED4 <= 7'b0111111;
    end
endcase 
end
endmodule
module seven_led (
    input [2:0] state,
    input [15:0] act_time,
    input [15:0] max_result,
    input clk,
    output reg[6:0] LED1,
    output reg[6:0] LED2,
    output reg[6:0] LED3,
    output reg[6:0] LED4
);


wire[6:0] LE1;
wire[6:0] LE2;
wire[6:0] LE3;
wire[6:0] LE4;

wire[6:0] LE5;
wire[6:0] LE6;
wire[6:0] LE7;
wire[6:0] LE8;
Binary_To_7Segment L1(.Binary(act_time[15:12]),.r_Hex_Encoding(LE1));
Binary_To_7Segment L2(.Binary(act_time[11:8]),.r_Hex_Encoding(LE2));
Binary_To_7Segment L3(.Binary(act_time[7:4]),.r_Hex_Encoding(LE3));
Binary_To_7Segment L4(.Binary(act_time[3:0]),.r_Hex_Encoding(LE4));

Binary_To_7Segment L5(.Binary(max_result[15:12]),.r_Hex_Encoding(LE5));
Binary_To_7Segment L6(.Binary(max_result[11:8]),.r_Hex_Encoding(LE6));
Binary_To_7Segment L7(.Binary(max_result[7:4]),.r_Hex_Encoding(LE7));
Binary_To_7Segment L8(.Binary(max_result[3:0]),.r_Hex_Encoding(LE8));
parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b111, S5 = 3'b110;

always @(posedge clk) begin
   case (state)

    S0:
    begin
        LED1 <= 7'b0000000;
        LED2 <= 7'b1110001;
        LED3 <= 7'b0111111;
        LED4 <= 7'b0111110;
    end

    S1:
    begin
        LED1 <= 7'b1000000;
        LED2 <= 7'b1000000;
        LED3 <= 7'b1000000;
        LED4 <= 7'b1000000;
    end

    S3:
    begin
        LED1 <= 7'b0000110;
        LED2 <= 7'b0000110;
        LED3 <= 7'b0000110;
        LED4 <= 7'b0000110;
    end

    S2:
    begin
        LED1 <= 7'b1110001;
        LED2 <= 7'b1110111;
        LED3 <= 7'b0000110;
        LED4 <= 7'b0111000;
    end

    S4:
    begin
        LED1 <= LE1;
        LED2 <= LE2;
        LED3 <= LE3;
        LED4 <= LE4;
    end
    S5:
    begin
        LED1 <= LE5;
        LED2 <= LE6;
        LED3 <= LE7;
        LED4 <= LE8;
    end
    default:
    begin
        LED1 <= 7'b0111111;
        LED2 <= 7'b0111111;
        LED3 <= 7'b0111111;
        LED4 <= 7'b0111111;
    end
endcase 
end
endmodule