data/full_repos/permissive/435885222/sources/id.v
data/verilator_xmls/a02f617d-427f-4e14-a7b0-0c345ec506cd.xml
module id(
    input rst,
    input [31:0] pc_in,
    input [31:0] inst_in,
    input [31:0] reg1_data_in,
    input [31:0] reg2_data_in,
    input ex_wreg_in,
    input [31:0] ex_wdata_in,
    input [4:0] ex_wd_in,
    input mem_wreg_in,
    input [31:0] mem_wdata_in,
    input [4:0] mem_wd_in,
    output reg reg1_read_out,
    output reg reg2_read_out,
    output reg[4:0] reg1_addr_out,
    output reg[4:0] reg2_addr_out,
    output reg[7:0] aluop_out,
    output reg[2:0] alusel_out,
    output reg[31:0] reg1_out,
    output reg[31:0] reg2_out,
    output reg[4:0] wd_out,
    output reg wreg_out,
    output wire[31:0] inst_out,
    output reg branch_flag_out,
    output reg[31:0] branch_target_address_out,
    output reg[31:0] link_addr_out
    );
    wire[5:0] op=inst_in[31:26];
    wire[4:0] op2=inst_in[10:6];
    wire[5:0] op3=inst_in[5:0];
    wire[4:0] op4=inst_in[20:16];
    reg[31:0] imm;
    wire[31:0] pc_plus_8;
    wire[31:0] pc_plus_4;
    wire[31:0] imm_sll2_signedext;
    assign pc_plus_8=pc_in+8;
    assign pc_plus_4=pc_in+4;
    assign imm_sll2_signedext={{14{inst_in[15]}},inst_in[15:0],2'b00};
    assign inst_out=inst_in;
    always @(*)begin
        if(rst==1'b1)begin
            aluop_out<=8'b00000000;
            alusel_out<=3'b000;
            wd_out<=5'b00000;
            wreg_out<=1'b0;
            reg1_read_out<=1'b0;
            reg2_read_out<=1'b0;
            reg1_addr_out<=5'b00000;
            reg2_addr_out<=5'b00000;
            imm<=32'h00000000;
            link_addr_out<=32'h00000000;
            branch_target_address_out<=32'h00000000;
            branch_flag_out<=1'b0;
        end else begin
            aluop_out<=8'b00000000;
            alusel_out<=3'b000;
            wd_out<=inst_in[15:11];
            wreg_out<=1'b0;
            reg1_read_out<=1'b0;
            reg2_read_out<=1'b0;
            reg1_addr_out<=inst_in[25:21];
            reg2_addr_out<=inst_in[20:16];
            imm<=32'h00000000;
            link_addr_out<=32'h00000000;
            branch_target_address_out<=32'h00000000;
            branch_flag_out<=1'b0;
            case(op)
                6'b000000:begin
                    case(op2)
                        5'b00000:begin
                            case(op3)
                                6'b100101:begin
                                    wreg_out<=1'b1;
                                    aluop_out<=8'b00100101;
                                    alusel_out<=3'b001;
                                    reg1_read_out<=1'b1;
                                    reg2_read_out<=1'b1;
                                end
                                6'b100100:begin
                                    wreg_out<=1'b1;
                                    aluop_out<=8'b00100100;
                                    alusel_out<=3'b001;
                                    reg1_read_out<=1'b1;
                                    reg2_read_out<=1'b1;
                                end
                                6'b100110:begin
                                    wreg_out<=1'b1;
                                    aluop_out<=8'b00100110;
                                    alusel_out<=3'b001;
                                    reg1_read_out<=1'b1;
                                    reg2_read_out<=1'b1;
                                end
                                6'b100111:begin
                                    wreg_out<=1'b1;
                                    aluop_out<=8'b00100111;
                                    alusel_out<=3'b001;
                                    reg1_read_out<=1'b1;
                                    reg2_read_out<=1'b1;
                                end
                                6'b000100:begin
                                    wreg_out<=1'b1;
                                    aluop_out<=8'b01111100;
                                    alusel_out<=3'b010;
                                    reg1_read_out<=1'b1;
                                    reg2_read_out<=1'b1;
                                end
                                6'b000110:begin
                                    wreg_out<=1'b1;
                                    aluop_out<=8'b00000010;
                                    alusel_out<=3'b010;
                                    reg1_read_out<=1'b1;
                                    reg2_read_out<=1'b1;
                                end
                                6'b000111:begin
                                    wreg_out<=1'b1;
                                    aluop_out<=8'b00000011;
                                    alusel_out<=3'b010;
                                    reg1_read_out<=1'b1;
                                    reg2_read_out<=1'b1;
                                end
                                6'b101010:begin
                                    wreg_out<=1'b1;
                                    aluop_out<=8'b00101010;
                                    alusel_out<=3'b011;
                                    reg1_read_out<=1'b1;
                                    reg2_read_out<=1'b1;
                                end
                                6'b101011:begin
                                    wreg_out<=1'b1;
                                    aluop_out<=8'b00101011;
                                    alusel_out<=3'b011;
                                    reg1_read_out<=1'b1;
                                    reg2_read_out<=1'b1;
                                end
                                6'b100000:begin
                                    wreg_out<=1'b1;
                                    aluop_out<=8'b00100000;
                                    alusel_out<=3'b011;
                                    reg1_read_out<=1'b1;
                                    reg2_read_out<=1'b1;
                                end
                                6'b100001:begin
                                    wreg_out<=1'b1;
                                    aluop_out<=8'b00100001;
                                    alusel_out<=3'b011;
                                    reg1_read_out<=1'b1;
                                    reg2_read_out<=1'b1;
                                end
                                6'b100010:begin
                                    wreg_out<=1'b1;
                                    aluop_out<=8'b00100010;
                                    alusel_out<=3'b011;
                                    reg1_read_out<=1'b1;
                                    reg2_read_out<=1'b1;
                                end
                                6'b100011:begin
                                    wreg_out<=1'b1;
                                    aluop_out<=8'b00100011;
                                    alusel_out<=3'b011;
                                    reg1_read_out<=1'b1;
                                    reg2_read_out<=1'b1;
                                end
                                6'b001000:begin
                                    reg1_read_out<=1'b1;
                                    branch_target_address_out<=reg1_out;
                                    branch_flag_out<=1'b1;
                                end
                                default:begin
                                end
                            endcase
                        end
                        default:begin
                        end
                    endcase
                end
                6'b001101:begin
                    wreg_out<=1'b1;
                    aluop_out<=8'b00100101;
                    alusel_out<=3'b001;
                    reg1_read_out<=1'b1;
                    imm<={16'h0,inst_in[15:0]};
                    wd_out<=inst_in[20:16];
                end
                6'b001100:begin
                    wreg_out<=1'b1;
                    aluop_out<=8'b00100100;
                    alusel_out<=3'b001;
                    reg1_read_out<=1'b1;
                    imm<={16'h0,inst_in[15:0]};
                    wd_out<=inst_in[20:16];
                end
                6'b001110:begin
                    wreg_out<=1'b1;
                    aluop_out<=8'b00100110;
                    alusel_out<=3'b001;
                    reg1_read_out<=1'b1;
                    imm<={16'h0,inst_in[15:0]};
                    wd_out<=inst_in[20:16];
                end
                6'b001111:begin
                    wreg_out<=1'b1;
                    aluop_out<=8'b00100101;
                    alusel_out<=3'b001;
                    reg1_read_out<=1'b1;
                    imm<={inst_in[15:0],16'h0};
                    wd_out<=inst_in[20:16];
                end
                6'b001010:begin
                    wreg_out<=1'b1;
                    aluop_out<=8'b00101010;
                    alusel_out<=3'b011;
                    reg1_read_out<=1'b1;
                    imm<={{16{inst_in[15]}},inst_in[15:0]};
                    wd_out<=inst_in[20:16];
                end
                6'b001011:begin
                    wreg_out<=1'b1;
                    aluop_out<=8'b00101011;
                    alusel_out<=3'b011;
                    reg1_read_out<=1'b1;
                    imm<={16'h0,inst_in[15:0]};
                    wd_out<=inst_in[20:16];
                end
                6'b001000:begin
                    wreg_out<=1'b1;
                    aluop_out<=8'b00100000;
                    alusel_out<=3'b011;
                    reg1_read_out<=1'b1;
                    imm<={{16{inst_in[15]}},inst_in[15:0]};
                    wd_out<=inst_in[20:16];
                end
                6'b001001:begin
                    wreg_out<=1'b1;
                    aluop_out<=8'b00100001;
                    alusel_out<=3'b011;
                    reg1_read_out<=1'b1;
                    imm<={{16{inst_in[15]}},inst_in[15:0]};
                    wd_out<=inst_in[20:16];
                end
                6'b000010:begin
                    branch_target_address_out<={4'h0,inst_in[25:0],2'b00};
                    branch_flag_out<=1'b1;
                end
                6'b000011:begin
                    wreg_out<=1'b1;
                    alusel_out<=3'b000;
                    wd_out<=5'b11111;
                    link_addr_out<=pc_plus_8;
                    branch_target_address_out<={4'h0,inst_in[25:0],2'b00};
                    branch_flag_out<=1'b1;
                end
                6'b000100:begin
                    reg1_read_out<=1'b1;
                    reg2_read_out<=1'b1;
                    if(reg1_out==reg2_out)begin
                        branch_target_address_out<=pc_plus_4+imm_sll2_signedext;
                        branch_flag_out<=1'b1;
                    end
                end
                6'b000101:begin
                    reg1_read_out<=1'b1;
                    reg2_read_out<=1'b1;
                    if(reg1_out!=reg2_out)begin
                        branch_target_address_out<=pc_plus_4+imm_sll2_signedext;
                        branch_flag_out<=1'b1;
                    end
                end
                6'b100011:begin
                    wreg_out<=1'b1;
                    aluop_out<=8'b11100011;
                    reg1_read_out<=1'b1;
                    wd_out<=inst_in[20:16];
                end
                6'b101011:begin
                    aluop_out<=8'b11101011;
                    reg1_read_out<=1'b1;
                    reg2_read_out<=1'b1;
                end
                default:begin
                end
            endcase
            if(inst_in[31:21]==11'b00000000000)begin
                if(op3==6'b000000)begin
                    wreg_out<=1'b1;
                    aluop_out<=8'b01111100;
                    alusel_out<=3'b010;
                    reg2_read_out<=1'b1;
                    imm[4:0]<=inst_in[10:6];
                end else if(op3==6'b000010)begin
                    wreg_out<=1'b1;
                    aluop_out<=8'b00000010;
                    alusel_out<=3'b010;
                    reg2_read_out<=1'b1;
                    imm[4:0]<=inst_in[10:6];
                end else if(op3==6'b000011)begin
                    wreg_out<=1'b1;
                    aluop_out<=8'b00000011;
                    alusel_out<=3'b010;
                    reg2_read_out<=1'b1;
                    imm[4:0]<=inst_in[10:6];
                end
            end
        end
    end
    always @(*)begin
        if(rst==1'b1) reg1_out<=32'h00000000;
        else if((reg1_read_out==1'b1)&&(ex_wreg_in==1'b1)&&(ex_wd_in==reg1_addr_out)) reg1_out<=ex_wdata_in;
        else if((reg1_read_out==1'b1)&&(mem_wreg_in==1'b1)&&(mem_wd_in==reg1_addr_out)) reg1_out<=mem_wdata_in;
        else if(reg1_read_out==1'b1) reg1_out<=reg1_data_in;
        else if(reg1_read_out==1'b0) reg1_out<=imm;
        else reg1_out<=32'h00000000;
    end
    always @(*)begin
        if(rst==1'b1) reg2_out<=32'h00000000;
        else if((reg2_read_out==1'b1)&&(ex_wreg_in==1'b1)&&(ex_wd_in==reg2_addr_out)) reg2_out<=ex_wdata_in;
        else if((reg2_read_out==1'b1)&&(mem_wreg_in==1'b1)&&(mem_wd_in==reg2_addr_out)) reg2_out<=mem_wdata_in;
        else if(reg2_read_out==1'b1) reg2_out<=reg2_data_in;
        else if(reg2_read_out==1'b0) reg2_out<=imm;
        else reg2_out<=32'h00000000;
    end
endmodule
module id(
    input rst,
    input [31:0] pc_in,
    input [31:0] inst_in,
    input [31:0] reg1_data_in,
    input [31:0] reg2_data_in,
    input ex_wreg_in,
    input [31:0] ex_wdata_in,
    input [4:0] ex_wd_in,
    input mem_wreg_in,
    input [31:0] mem_wdata_in,
    input [4:0] mem_wd_in,
    output reg reg1_read_out,
    output reg reg2_read_out,
    output reg[4:0] reg1_addr_out,
    output reg[4:0] reg2_addr_out,
    output reg[7:0] aluop_out,
    output reg[2:0] alusel_out,
    output reg[31:0] reg1_out,
    output reg[31:0] reg2_out,
    output reg[4:0] wd_out,
    output reg wreg_out,
    output wire[31:0] inst_out,
    output reg branch_flag_out,
    output reg[31:0] branch_target_address_out,
    output reg[31:0] link_addr_out
    );

    wire[5:0] op=inst_in[31:26];
    wire[4:0] op2=inst_in[10:6];
    wire[5:0] op3=inst_in[5:0];
    wire[4:0] op4=inst_in[20:16];
    reg[31:0] imm;
    wire[31:0] pc_plus_8;
    wire[31:0] pc_plus_4;
    wire[31:0] imm_sll2_signedext;
    assign pc_plus_8=pc_in+8;
    assign pc_plus_4=pc_in+4;
    assign imm_sll2_signedext={{14{inst_in[15]}},inst_in[15:0],2'b00};
    assign inst_out=inst_in;
    always @(*)begin
        if(rst==1'b1)begin
            aluop_out<=8'b00000000;
            alusel_out<=3'b000;
            wd_out<=5'b00000;
            wreg_out<=1'b0;
            reg1_read_out<=1'b0;
            reg2_read_out<=1'b0;
            reg1_addr_out<=5'b00000;
            reg2_addr_out<=5'b00000;
            imm<=32'h00000000;
            link_addr_out<=32'h00000000;
            branch_target_address_out<=32'h00000000;
            branch_flag_out<=1'b0;
        end else begin
            aluop_out<=8'b00000000;
            alusel_out<=3'b000;
            wd_out<=inst_in[15:11];
            wreg_out<=1'b0;
            reg1_read_out<=1'b0;
            reg2_read_out<=1'b0;
            reg1_addr_out<=inst_in[25:21];
            reg2_addr_out<=inst_in[20:16];
            imm<=32'h00000000;
            link_addr_out<=32'h00000000;
            branch_target_address_out<=32'h00000000;
            branch_flag_out<=1'b0;
            case(op)
                6'b000000:begin
                    case(op2)
                        5'b00000:begin
                            case(op3)
                                6'b100101:begin
                                    wreg_out<=1'b1;
                                    aluop_out<=8'b00100101;
                                    alusel_out<=3'b001;
                                    reg1_read_out<=1'b1;
                                    reg2_read_out<=1'b1;
                                end
                                6'b100100:begin
                                    wreg_out<=1'b1;
                                    aluop_out<=8'b00100100;
                                    alusel_out<=3'b001;
                                    reg1_read_out<=1'b1;
                                    reg2_read_out<=1'b1;
                                end
                                6'b100110:begin
                                    wreg_out<=1'b1;
                                    aluop_out<=8'b00100110;
                                    alusel_out<=3'b001;
                                    reg1_read_out<=1'b1;
                                    reg2_read_out<=1'b1;
                                end
                                6'b100111:begin
                                    wreg_out<=1'b1;
                                    aluop_out<=8'b00100111;
                                    alusel_out<=3'b001;
                                    reg1_read_out<=1'b1;
                                    reg2_read_out<=1'b1;
                                end
                                6'b000100:begin
                                    wreg_out<=1'b1;
                                    aluop_out<=8'b01111100;
                                    alusel_out<=3'b010;
                                    reg1_read_out<=1'b1;
                                    reg2_read_out<=1'b1;
                                end
                                6'b000110:begin
                                    wreg_out<=1'b1;
                                    aluop_out<=8'b00000010;
                                    alusel_out<=3'b010;
                                    reg1_read_out<=1'b1;
                                    reg2_read_out<=1'b1;
                                end
                                6'b000111:begin
                                    wreg_out<=1'b1;
                                    aluop_out<=8'b00000011;
                                    alusel_out<=3'b010;
                                    reg1_read_out<=1'b1;
                                    reg2_read_out<=1'b1;
                                end
                                6'b101010:begin
                                    wreg_out<=1'b1;
                                    aluop_out<=8'b00101010;
                                    alusel_out<=3'b011;
                                    reg1_read_out<=1'b1;
                                    reg2_read_out<=1'b1;
                                end
                                6'b101011:begin
                                    wreg_out<=1'b1;
                                    aluop_out<=8'b00101011;
                                    alusel_out<=3'b011;
                                    reg1_read_out<=1'b1;
                                    reg2_read_out<=1'b1;
                                end
                                6'b100000:begin
                                    wreg_out<=1'b1;
                                    aluop_out<=8'b00100000;
                                    alusel_out<=3'b011;
                                    reg1_read_out<=1'b1;
                                    reg2_read_out<=1'b1;
                                end
                                6'b100001:begin
                                    wreg_out<=1'b1;
                                    aluop_out<=8'b00100001;
                                    alusel_out<=3'b011;
                                    reg1_read_out<=1'b1;
                                    reg2_read_out<=1'b1;
                                end
                                6'b100010:begin
                                    wreg_out<=1'b1;
                                    aluop_out<=8'b00100010;
                                    alusel_out<=3'b011;
                                    reg1_read_out<=1'b1;
                                    reg2_read_out<=1'b1;
                                end
                                6'b100011:begin
                                    wreg_out<=1'b1;
                                    aluop_out<=8'b00100011;
                                    alusel_out<=3'b011;
                                    reg1_read_out<=1'b1;
                                    reg2_read_out<=1'b1;
                                end
                                6'b001000:begin
                                    reg1_read_out<=1'b1;
                                    branch_target_address_out<=reg1_out;
                                    branch_flag_out<=1'b1;
                                end
                                default:begin
                                end
                            endcase
                        end
                        default:begin
                        end
                    endcase
                end
                6'b001101:begin
                    wreg_out<=1'b1;
                    aluop_out<=8'b00100101;
                    alusel_out<=3'b001;
                    reg1_read_out<=1'b1;
                    imm<={16'h0,inst_in[15:0]};
                    wd_out<=inst_in[20:16];
                end
                6'b001100:begin
                    wreg_out<=1'b1;
                    aluop_out<=8'b00100100;
                    alusel_out<=3'b001;
                    reg1_read_out<=1'b1;
                    imm<={16'h0,inst_in[15:0]};
                    wd_out<=inst_in[20:16];
                end
                6'b001110:begin
                    wreg_out<=1'b1;
                    aluop_out<=8'b00100110;
                    alusel_out<=3'b001;
                    reg1_read_out<=1'b1;
                    imm<={16'h0,inst_in[15:0]};
                    wd_out<=inst_in[20:16];
                end
                6'b001111:begin
                    wreg_out<=1'b1;
                    aluop_out<=8'b00100101;
                    alusel_out<=3'b001;
                    reg1_read_out<=1'b1;
                    imm<={inst_in[15:0],16'h0};
                    wd_out<=inst_in[20:16];
                end
                6'b001010:begin
                    wreg_out<=1'b1;
                    aluop_out<=8'b00101010;
                    alusel_out<=3'b011;
                    reg1_read_out<=1'b1;
                    imm<={{16{inst_in[15]}},inst_in[15:0]};
                    wd_out<=inst_in[20:16];
                end
                6'b001011:begin
                    wreg_out<=1'b1;
                    aluop_out<=8'b00101011;
                    alusel_out<=3'b011;
                    reg1_read_out<=1'b1;
                    imm<={16'h0,inst_in[15:0]};
                    wd_out<=inst_in[20:16];
                end
                6'b001000:begin
                    wreg_out<=1'b1;
                    aluop_out<=8'b00100000;
                    alusel_out<=3'b011;
                    reg1_read_out<=1'b1;
                    imm<={{16{inst_in[15]}},inst_in[15:0]};
                    wd_out<=inst_in[20:16];
                end
                6'b001001:begin
                    wreg_out<=1'b1;
                    aluop_out<=8'b00100001;
                    alusel_out<=3'b011;
                    reg1_read_out<=1'b1;
                    imm<={{16{inst_in[15]}},inst_in[15:0]};
                    wd_out<=inst_in[20:16];
                end
                6'b000010:begin
                    branch_target_address_out<={4'h0,inst_in[25:0],2'b00};
                    branch_flag_out<=1'b1;
                end
                6'b000011:begin
                    wreg_out<=1'b1;
                    alusel_out<=3'b000;
                    wd_out<=5'b11111;
                    link_addr_out<=pc_plus_8;
                    branch_target_address_out<={4'h0,inst_in[25:0],2'b00};
                    branch_flag_out<=1'b1;
                end
                6'b000100:begin
                    reg1_read_out<=1'b1;
                    reg2_read_out<=1'b1;
                    if(reg1_out==reg2_out)begin
                        branch_target_address_out<=pc_plus_4+imm_sll2_signedext;
                        branch_flag_out<=1'b1;
                    end
                end
                6'b000101:begin
                    reg1_read_out<=1'b1;
                    reg2_read_out<=1'b1;
                    if(reg1_out!=reg2_out)begin
                        branch_target_address_out<=pc_plus_4+imm_sll2_signedext;
                        branch_flag_out<=1'b1;
                    end
                end
                6'b100011:begin
                    wreg_out<=1'b1;
                    aluop_out<=8'b11100011;
                    reg1_read_out<=1'b1;
                    wd_out<=inst_in[20:16];
                end
                6'b101011:begin
                    aluop_out<=8'b11101011;
                    reg1_read_out<=1'b1;
                    reg2_read_out<=1'b1;
                end
                default:begin
                end
            endcase
            if(inst_in[31:21]==11'b00000000000)begin
                if(op3==6'b000000)begin
                    wreg_out<=1'b1;
                    aluop_out<=8'b01111100;
                    alusel_out<=3'b010;
                    reg2_read_out<=1'b1;
                    imm[4:0]<=inst_in[10:6];
                end else if(op3==6'b000010)begin
                    wreg_out<=1'b1;
                    aluop_out<=8'b00000010;
                    alusel_out<=3'b010;
                    reg2_read_out<=1'b1;
                    imm[4:0]<=inst_in[10:6];
                end else if(op3==6'b000011)begin
                    wreg_out<=1'b1;
                    aluop_out<=8'b00000011;
                    alusel_out<=3'b010;
                    reg2_read_out<=1'b1;
                    imm[4:0]<=inst_in[10:6];
                end
            end
        end
    end
    always @(*)begin
        if(rst==1'b1) reg1_out<=32'h00000000;
        else if((reg1_read_out==1'b1)&&(ex_wreg_in==1'b1)&&(ex_wd_in==reg1_addr_out)) reg1_out<=ex_wdata_in;
        else if((reg1_read_out==1'b1)&&(mem_wreg_in==1'b1)&&(mem_wd_in==reg1_addr_out)) reg1_out<=mem_wdata_in;
        else if(reg1_read_out==1'b1) reg1_out<=reg1_data_in;
        else if(reg1_read_out==1'b0) reg1_out<=imm;
        else reg1_out<=32'h00000000;
    end
    always @(*)begin
        if(rst==1'b1) reg2_out<=32'h00000000;
        else if((reg2_read_out==1'b1)&&(ex_wreg_in==1'b1)&&(ex_wd_in==reg2_addr_out)) reg2_out<=ex_wdata_in;
        else if((reg2_read_out==1'b1)&&(mem_wreg_in==1'b1)&&(mem_wd_in==reg2_addr_out)) reg2_out<=mem_wdata_in;
        else if(reg2_read_out==1'b1) reg2_out<=reg2_data_in;
        else if(reg2_read_out==1'b0) reg2_out<=imm;
        else reg2_out<=32'h00000000;
    end
endmodule