data/full_repos/permissive/443867168/Verilog/CLA_testbench.v
1: b'%Error: data/full_repos/permissive/443867168/Verilog/CLA_testbench.v:14: Unsupported or unknown PLI call: $dumpfile\n     $dumpfile("CLA.vcd");\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/443867168/Verilog/CLA_testbench.v:15: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(0,CLA_testbench);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/443867168/Verilog/CLA_testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n     #10 a = 4\'d6; b = 4\'d2;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/443867168/Verilog/CLA_testbench.v:21: Unsupported or unknown PLI call: $monitor\n     $monitor( "a = %b, b = %b , Cin = %b , carry[3] = %b, sum = %b",a,b,Cin,carry[3],sum);\n     ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/443867168/Verilog/CLA_testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #20 a = 4\'d3; b = 4\'d10;\n        ^\n%Error: data/full_repos/permissive/443867168/Verilog/CLA_testbench.v:23: Unsupported or unknown PLI call: $monitor\n        $monitor( "a = %d, b = %d , Cin = %b , carry[3] = %b, sum = %d",a,b,Cin,carry[3],sum);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/443867168/Verilog/CLA_testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #20 a = 4\'d11; b = 4\'d10; Cin = 1;\n        ^\n%Error: data/full_repos/permissive/443867168/Verilog/CLA_testbench.v:25: Unsupported or unknown PLI call: $monitor\n        $monitor( "a = %d, b = %d , Cin = %b , carry[3] = %b, sum = %d",a,b,Cin,carry[3],sum);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/443867168/Verilog/CLA_testbench.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #20 a = 4\'d0; b = 4\'d0; Cin = 0;\n        ^\n%Error: data/full_repos/permissive/443867168/Verilog/CLA_testbench.v:27: Unsupported or unknown PLI call: $monitor\n        $monitor( "a = %d, b = %d , Cin = %b , carry[3] = %b, sum = %d",a,b,Cin,carry[3],sum);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/443867168/Verilog/CLA_testbench.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #20 a = 4\'d9; b = 4\'d0; Cin = 1;\n        ^\n%Error: data/full_repos/permissive/443867168/Verilog/CLA_testbench.v:29: Unsupported or unknown PLI call: $monitor\n        $monitor( "a = %d, b = %d , Cin = %b , carry[3] = %b, sum = %d",a,b,Cin,carry[3],sum);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/443867168/Verilog/CLA_testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #20 a = 4\'d15; b = 4\'d15; Cin = 1;\n        ^\n%Error: data/full_repos/permissive/443867168/Verilog/CLA_testbench.v:31: Unsupported or unknown PLI call: $monitor\n        $monitor( "a = %d, b = %d , Cin = %b , carry[3] = %b, sum = %d",a,b,Cin,carry[3],sum);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/443867168/Verilog/CLA_testbench.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #20 a = 4\'d6; b = 4\'d2; Cin = 0;\n        ^\n%Error: data/full_repos/permissive/443867168/Verilog/CLA_testbench.v:33: Unsupported or unknown PLI call: $monitor\n        $monitor( "a = %d, b = %d , Cin = %b , carry[3] = %b, sum = %d",a,b,Cin,carry[3],sum);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/443867168/Verilog/CLA_testbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Error: Exiting due to 9 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module CLA_testbench();
    reg [3:0] a;
    reg [3:0] b;
    reg Cin;

    output [3:0] sum;
    output [3:0] carry;

    CLA abc(.a(a),.b(b),.Cin(Cin),.sum(sum),.carry(carry));

    initial begin

	    $dumpfile("CLA.vcd");
     	$dumpvars(0,CLA_testbench);

        a = 0;
        b = 0;
        Cin = 0;
	    #10 a = 4'd6; b = 4'd2;
	    $monitor( "a = %b, b = %b , Cin = %b , carry[3] = %b, sum = %b",a,b,Cin,carry[3],sum);
        #20 a = 4'd3; b = 4'd10;
        $monitor( "a = %d, b = %d , Cin = %b , carry[3] = %b, sum = %d",a,b,Cin,carry[3],sum);
        #20 a = 4'd11; b = 4'd10; Cin = 1;
        $monitor( "a = %d, b = %d , Cin = %b , carry[3] = %b, sum = %d",a,b,Cin,carry[3],sum);
        #20 a = 4'd0; b = 4'd0; Cin = 0;
        $monitor( "a = %d, b = %d , Cin = %b , carry[3] = %b, sum = %d",a,b,Cin,carry[3],sum);
        #20 a = 4'd9; b = 4'd0; Cin = 1;
        $monitor( "a = %d, b = %d , Cin = %b , carry[3] = %b, sum = %d",a,b,Cin,carry[3],sum);
        #20 a = 4'd15; b = 4'd15; Cin = 1;
        $monitor( "a = %d, b = %d , Cin = %b , carry[3] = %b, sum = %d",a,b,Cin,carry[3],sum);
        #20 a = 4'd6; b = 4'd2; Cin = 0;
        $monitor( "a = %d, b = %d , Cin = %b , carry[3] = %b, sum = %d",a,b,Cin,carry[3],sum);
        #20;
        $finish;

    end
endmodule
module CLA_testbench();

    reg [3:0] a;
    reg [3:0] b;
    reg Cin;

    output [3:0] sum;
    output [3:0] carry;

    CLA abc(.a(a),.b(b),.Cin(Cin),.sum(sum),.carry(carry));

    initial begin

	    $dumpfile("CLA.vcd");
     	$dumpvars(0,CLA_testbench);

        a = 0;
        b = 0;
        Cin = 0;
	    #10 a = 4'd6; b = 4'd2;
	    $monitor( "a = %b, b = %b , Cin = %b , carry[3] = %b, sum = %b",a,b,Cin,carry[3],sum);
        #20 a = 4'd3; b = 4'd10;
        $monitor( "a = %d, b = %d , Cin = %b , carry[3] = %b, sum = %d",a,b,Cin,carry[3],sum);
        #20 a = 4'd11; b = 4'd10; Cin = 1;
        $monitor( "a = %d, b = %d , Cin = %b , carry[3] = %b, sum = %d",a,b,Cin,carry[3],sum);
        #20 a = 4'd0; b = 4'd0; Cin = 0;
        $monitor( "a = %d, b = %d , Cin = %b , carry[3] = %b, sum = %d",a,b,Cin,carry[3],sum);
        #20 a = 4'd9; b = 4'd0; Cin = 1;
        $monitor( "a = %d, b = %d , Cin = %b , carry[3] = %b, sum = %d",a,b,Cin,carry[3],sum);
        #20 a = 4'd15; b = 4'd15; Cin = 1;
        $monitor( "a = %d, b = %d , Cin = %b , carry[3] = %b, sum = %d",a,b,Cin,carry[3],sum);
        #20 a = 4'd6; b = 4'd2; Cin = 0;
        $monitor( "a = %d, b = %d , Cin = %b , carry[3] = %b, sum = %d",a,b,Cin,carry[3],sum);
        #20;
        $finish;

    end
endmodule