data/full_repos/permissive/493019833/test/testcase/firrtl/RemoveMantissa.lo/reference/RemoveMantissa.lo.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/RemoveMantissa.lo/reference/RemoveMantissa.lo.v:34: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s SEL generates 1 bits.\n                                                                                                                            : ... In instance RemoveMantissa.s_shr_1\n    assign y = n < width ? in[width-1:n] : in[width-1:width-1];\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module DFF_POSCLK(q, d, clk);
    parameter width = 4;
    output reg [width-1:0] q;
    input [width-1:0] d;
    input clk;
    always @(posedge clk) begin
        q <= d;
    end
endmodule
module DFF_POSCLK(q, d, clk);

    parameter width = 4;
    output reg [width-1:0] q;
    input [width-1:0] d;
    input clk;
    always @(posedge clk) begin
        q <= d;
    end
endmodule