data/full_repos/permissive/509335294/prog_count.v
data/verilator_xmls/aac1a4cc-eb2c-42bf-954b-ef94d7875cb8.xml
module prog_count(		
								input[12:0] 			next_pc, 
								input 					clk, rst,
								output reg[12:0] 	curr_pc
								);
reg count_zero_flag;

initial begin
	count_zero_flag = 1;
	curr_pc <= 0;
end



always@(posedge clk)begin
	
	if(rst)begin 
		if(count_zero_flag)begin
			curr_pc <= 13'b0;
			count_zero_flag <= 0;
		end else curr_pc <= next_pc;
		
	end else begin
		curr_pc <= 13'b0;
		count_zero_flag <= 1;
	end
end

endmodule
module prog_count(		
								input[12:0] 			next_pc, 
								input 					clk, rst,
								output reg[12:0] 	curr_pc
								);

reg count_zero_flag;

initial begin
	count_zero_flag = 1;
	curr_pc <= 0;
end



always@(posedge clk)begin
	
	if(rst)begin 
		if(count_zero_flag)begin
			curr_pc <= 13'b0;
			count_zero_flag <= 0;
		end else curr_pc <= next_pc;
		
	end else begin
		curr_pc <= 13'b0;
		count_zero_flag <= 1;
	end
end

endmodule