data/full_repos/permissive/40989439/AdiHDLLib/library/common/ad_lvds_clk.v
1: b"%Error: data/full_repos/permissive/40989439/AdiHDLLib/library/common/ad_lvds_clk.v:62: Cannot find file containing module: 'IBUFGDS'\n  IBUFGDS i_rx_clk_ibuf (\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/40989439/AdiHDLLib/library/common,data/full_repos/permissive/40989439/IBUFGDS\n             data/full_repos/permissive/40989439/AdiHDLLib/library/common,data/full_repos/permissive/40989439/IBUFGDS.v\n             data/full_repos/permissive/40989439/AdiHDLLib/library/common,data/full_repos/permissive/40989439/IBUFGDS.sv\n             IBUFGDS\n             IBUFGDS.v\n             IBUFGDS.sv\n             obj_dir/IBUFGDS\n             obj_dir/IBUFGDS.v\n             obj_dir/IBUFGDS.sv\n%Error: data/full_repos/permissive/40989439/AdiHDLLib/library/common/ad_lvds_clk.v:75: Cannot find file containing module: 'BUFG'\n  BUFG i_clk_gbuf (\n  ^~~~\n%Error: Exiting due to 2 error(s)\n"
module ad_lvds_clk (

  clk_in_p,
  clk_in_n,
  clk);

  parameter   DEVICE_TYPE       = 0;
  localparam  SERIES7       = 0;
  localparam  VIRTEX6       = 1;

  input     clk_in_p;
  input     clk_in_n;
  output    clk;



  wire      clk_ibuf_s;



  IBUFGDS i_rx_clk_ibuf (
    .I (clk_in_p),
    .IB (clk_in_n),
    .O (clk_ibuf_s));

  generate
  if (DEVICE_TYPE == VIRTEX6) begin
  BUFR #(.BUFR_DIVIDE("BYPASS")) i_clk_rbuf (
    .CLR (1'b0),
    .CE (1'b1),
    .I (clk_ibuf_s),
    .O (clk));
  end else begin
  BUFG i_clk_gbuf (
    .I (clk_ibuf_s),
    .O (clk));
  end
  endgenerate



endmodule
module ad_lvds_clk (

  clk_in_p,
  clk_in_n,
  clk);


  parameter   DEVICE_TYPE       = 0;
  localparam  SERIES7       = 0;
  localparam  VIRTEX6       = 1;

  input     clk_in_p;
  input     clk_in_n;
  output    clk;



  wire      clk_ibuf_s;



  IBUFGDS i_rx_clk_ibuf (
    .I (clk_in_p),
    .IB (clk_in_n),
    .O (clk_ibuf_s));

  generate
  if (DEVICE_TYPE == VIRTEX6) begin
  BUFR #(.BUFR_DIVIDE("BYPASS")) i_clk_rbuf (
    .CLR (1'b0),
    .CE (1'b1),
    .I (clk_ibuf_s),
    .O (clk));
  end else begin
  BUFG i_clk_gbuf (
    .I (clk_ibuf_s),
    .O (clk));
  end
  endgenerate



endmodule