data/full_repos/permissive/43856783/j1_soc/hdl/Timer_Counter/Peripheral_clk_interruptor.v
1: b'%Warning-WIDTH: data/full_repos/permissive/43856783/j1_soc/hdl/Timer_Counter/Peripheral_clk_interruptor.v:61: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'d_in\' generates 16 bits.\n                                                                                                            : ... In instance Peripheral_clk_interruptor\nlimit    = (s[0]) ? d_in : limit;  \n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/43856783/j1_soc/hdl/Timer_Counter/Peripheral_clk_interruptor.v:62: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'d_in\' generates 16 bits.\n                                                                                                            : ... In instance Peripheral_clk_interruptor\ncount    = (s[1]) ? d_in : count;  \n                  ^\n%Warning-WIDTH: data/full_repos/permissive/43856783/j1_soc/hdl/Timer_Counter/Peripheral_clk_interruptor.v:73: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'int_0\' generates 1 bits.\n                                                                                                            : ... In instance Peripheral_clk_interruptor\n3\'b010: d_out    = int_0 ;\n                 ^\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/Timer_Counter/Peripheral_clk_interruptor.v:80: Cannot find file containing module: \'clk_interruptor\'\nclk_interruptor c_i ( .clk(clk), .rst(rst), .limit(limit), .count(count), .en(en), .int_0(int_0), .done(done) );\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43856783/j1_soc/hdl/Timer_Counter,data/full_repos/permissive/43856783/clk_interruptor\n             data/full_repos/permissive/43856783/j1_soc/hdl/Timer_Counter,data/full_repos/permissive/43856783/clk_interruptor.v\n             data/full_repos/permissive/43856783/j1_soc/hdl/Timer_Counter,data/full_repos/permissive/43856783/clk_interruptor.sv\n             clk_interruptor\n             clk_interruptor.v\n             clk_interruptor.sv\n             obj_dir/clk_interruptor\n             obj_dir/clk_interruptor.v\n             obj_dir/clk_interruptor.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module Peripheral_clk_interruptor(
    input clk,
    input rst,
    input [15:0] d_in,
    input cs,
    input [3:0] addr,
    input rd,
    input wr,
    output reg [15:0] d_out
    );



	reg [5:0] s;

	reg [31:0] limit;
	reg [31:0] count;
	reg en=0;

	wire int_0;
	wire done;



always @(*) begin
case (addr)
4'h0:begin s = (cs && wr) ? 6'b000001 : 6'b000000 ;end
4'h2:begin s = (cs && wr) ? 6'b000010 : 6'b000000 ;end
4'h4:begin s = (cs && wr) ? 6'b000100 : 6'b000000 ;end

4'h6:begin s = (cs && rd) ? 6'b001000 : 6'b000000 ;end
4'h8:begin s = (cs && rd) ? 6'b010000 : 6'b000000 ;end
default:begin s = 6'b000000 ; end
endcase
end



always @(negedge clk) begin

limit    = (s[0]) ? d_in : limit;
count    = (s[1]) ? d_in : count;
en = s[2] ;

end




always @(negedge clk) begin
case (s[5:3])
3'b001: d_out[0] = done ;
3'b010: d_out    = int_0 ;
default: d_out   = 0 ;
endcase
end



clk_interruptor c_i ( .clk(clk), .rst(rst), .limit(limit), .count(count), .en(en), .int_0(int_0), .done(done) );


endmodule
module Peripheral_clk_interruptor(
    input clk,
    input rst,
    input [15:0] d_in,
    input cs,
    input [3:0] addr,
    input rd,
    input wr,
    output reg [15:0] d_out
    );




	reg [5:0] s;

	reg [31:0] limit;
	reg [31:0] count;
	reg en=0;

	wire int_0;
	wire done;



always @(*) begin
case (addr)
4'h0:begin s = (cs && wr) ? 6'b000001 : 6'b000000 ;end
4'h2:begin s = (cs && wr) ? 6'b000010 : 6'b000000 ;end
4'h4:begin s = (cs && wr) ? 6'b000100 : 6'b000000 ;end

4'h6:begin s = (cs && rd) ? 6'b001000 : 6'b000000 ;end
4'h8:begin s = (cs && rd) ? 6'b010000 : 6'b000000 ;end
default:begin s = 6'b000000 ; end
endcase
end



always @(negedge clk) begin

limit    = (s[0]) ? d_in : limit;
count    = (s[1]) ? d_in : count;
en = s[2] ;

end




always @(negedge clk) begin
case (s[5:3])
3'b001: d_out[0] = done ;
3'b010: d_out    = int_0 ;
default: d_out   = 0 ;
endcase
end



clk_interruptor c_i ( .clk(clk), .rst(rst), .limit(limit), .count(count), .en(en), .int_0(int_0), .done(done) );


endmodule