data/full_repos/permissive/452305748/L9/UART_TXer/UART_TXer.v
data/verilator_xmls/dda64971-7a18-4276-a457-27b51c4e83c9.xml
module UART_TXer (input wire clk,
                  input wire rst,
                  input wire en_data_in,
                  input wire [7:0] data_in,
                  output wire TX,
                  output reg rdy);
    
    reg state;
    reg [9:0] send_buff;
    
    assign TX = send_buff[0];
    
    reg [9:0] send_flag;
    
    reg [12:0] con;
    
    always @(posedge clk or negedge rst) begin
        if (~rst) begin
            state     <= 0;
            send_buff <= 1;
            send_flag <= 10'b10_0000_0000;
            con       <= 0;
            rdy       <= 0;
        end
        else begin
            case (state)
                0 :
                begin
                    if (en_data_in) begin
                        send_buff <= {1'b1,data_in,1'b0};
                        send_flag <= 10'b10_0000_0000;
                        rdy       <= 1;
                        state     <= 1;
                    end
                end
                1 :
                begin
                    if (con == 5000 - 1) begin
                        send_buff[8:0] <= send_buff[9:1];
                        send_flag[8:0] <= send_flag[9:1];
                        con <= 0;
                    end
                    else begin
                        con <= con + 1;
                    end

                    if (send_flag[0] == 1'b1) begin
                        rdy   <= 0;
                        state <= 0;
                    end
                end
            endcase
        end
    end
endmodule
module UART_TXer (input wire clk,
                  input wire rst,
                  input wire en_data_in,
                  input wire [7:0] data_in,
                  output wire TX,
                  output reg rdy);

    
    reg state;
    reg [9:0] send_buff;
    
    assign TX = send_buff[0];
    
    reg [9:0] send_flag;
    
    reg [12:0] con;
    
    always @(posedge clk or negedge rst) begin
        if (~rst) begin
            state     <= 0;
            send_buff <= 1;
            send_flag <= 10'b10_0000_0000;
            con       <= 0;
            rdy       <= 0;
        end
        else begin
            case (state)
                0 :
                begin
                    if (en_data_in) begin
                        send_buff <= {1'b1,data_in,1'b0};
                        send_flag <= 10'b10_0000_0000;
                        rdy       <= 1;
                        state     <= 1;
                    end
                end
                1 :
                begin
                    if (con == 5000 - 1) begin
                        send_buff[8:0] <= send_buff[9:1];
                        send_flag[8:0] <= send_flag[9:1];
                        con <= 0;
                    end
                    else begin
                        con <= con + 1;
                    end

                    if (send_flag[0] == 1'b1) begin
                        rdy   <= 0;
                        state <= 0;
                    end
                end
            endcase
        end
    end
endmodule