data/full_repos/permissive/418819021/lab-07/gpio_sram.v
1: b'%Error: data/full_repos/permissive/418819021/lab-07/gpio_sram.v:4: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418819021/lab-07,data/full_repos/permissive/418819021/defines.vh\n             data/full_repos/permissive/418819021/lab-07,data/full_repos/permissive/418819021/defines.vh.v\n             data/full_repos/permissive/418819021/lab-07,data/full_repos/permissive/418819021/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/418819021/lab-07/gpio_sram.v:47: Define or directive not defined: \'`PINA\'\n            memory[`PINA] <= pa;  \n                   ^~~~~\n%Error: data/full_repos/permissive/418819021/lab-07/gpio_sram.v:47: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n            memory[`PINA] <= pa;  \n                        ^\n%Error: data/full_repos/permissive/418819021/lab-07/gpio_sram.v:48: Define or directive not defined: \'`PINB\'\n            memory[`PINB] <= pb;  \n                   ^~~~~\n%Error: data/full_repos/permissive/418819021/lab-07/gpio_sram.v:48: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n            memory[`PINB] <= pb;  \n                        ^\n%Error: data/full_repos/permissive/418819021/lab-07/gpio_sram.v:51: Define or directive not defined: \'`TCNT0\'\n            if (address == `TCNT0 && cs && we)\n                           ^~~~~~\n%Error: data/full_repos/permissive/418819021/lab-07/gpio_sram.v:51: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n            if (address == `TCNT0 && cs && we)\n                                  ^~\n%Error: data/full_repos/permissive/418819021/lab-07/gpio_sram.v:52: Define or directive not defined: \'`TCNT0\'\n                memory[`TCNT0] <= data;  \n                       ^~~~~~\n%Error: data/full_repos/permissive/418819021/lab-07/gpio_sram.v:54: Define or directive not defined: \'`TCNT0\'\n                memory[`TCNT0] <= tcnt0;  \n                       ^~~~~~\n%Error: data/full_repos/permissive/418819021/lab-07/gpio_sram.v:58: Define or directive not defined: \'`PINA\'\n    assign readonly = (address == `PINA || address == `PINB);\n                                  ^~~~~\n%Error: data/full_repos/permissive/418819021/lab-07/gpio_sram.v:58: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n    assign readonly = (address == `PINA || address == `PINB);\n                                        ^~\n%Error: data/full_repos/permissive/418819021/lab-07/gpio_sram.v:58: Define or directive not defined: \'`PINB\'\n    assign readonly = (address == `PINA || address == `PINB);\n                                                      ^~~~~\n%Error: data/full_repos/permissive/418819021/lab-07/gpio_sram.v:66: Define or directive not defined: \'`DDRA\'\n        .mem_ddra (memory[`DDRA] ),\n                          ^~~~~\n%Error: data/full_repos/permissive/418819021/lab-07/gpio_sram.v:66: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n        .mem_ddra (memory[`DDRA] ),\n                               ^\n%Error: data/full_repos/permissive/418819021/lab-07/gpio_sram.v:67: Define or directive not defined: \'`DDRB\'\n        .mem_ddrb (memory[`DDRB] ),\n                          ^~~~~\n%Error: data/full_repos/permissive/418819021/lab-07/gpio_sram.v:68: Define or directive not defined: \'`PORTA\'\n        .mem_porta(memory[`PORTA]),\n                          ^~~~~~\n%Error: data/full_repos/permissive/418819021/lab-07/gpio_sram.v:69: Define or directive not defined: \'`PORTB\'\n        .mem_portb(memory[`PORTB]),\n                          ^~~~~~\n%Error: data/full_repos/permissive/418819021/lab-07/gpio_sram.v:77: Define or directive not defined: \'`TCNT0\'\n        .mem_tcnt0 (memory[`TCNT0] ),\n                           ^~~~~~\n%Error: data/full_repos/permissive/418819021/lab-07/gpio_sram.v:77: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n        .mem_tcnt0 (memory[`TCNT0] ),\n                                 ^\n%Error: data/full_repos/permissive/418819021/lab-07/gpio_sram.v:78: Define or directive not defined: \'`TCCR0A\'\n        .mem_tccr0a(memory[`TCCR0A]),\n                           ^~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-07/gpio_sram.v:79: Define or directive not defined: \'`TCCR0B\'\n        .mem_tccr0b(memory[`TCCR0B]),\n                           ^~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-07/gpio_sram.v:80: Define or directive not defined: \'`OCR0A\'\n        .mem_ocr0a (memory[`OCR0A] ),\n                           ^~~~~~\n%Error: data/full_repos/permissive/418819021/lab-07/gpio_sram.v:81: Define or directive not defined: \'`OCR0B\'\n        .mem_ocr0b (memory[`OCR0B] ),\n                           ^~~~~~\n%Error: Exiting due to 23 error(s)\n'
module gpio_sram #(
    parameter DATA_WIDTH   = 8 ,
    parameter ADDR_WIDTH   = 6 ,
    parameter I_ADDR_WIDTH = 10
) (

    input  wire                  clk    ,
    input  wire                  reset  ,
    input  wire                  oe     ,
    input  wire                  cs     ,
    input  wire                  we     ,
    input  wire [ADDR_WIDTH-1:0] address,
    inout  wire [DATA_WIDTH-1:0] data   ,

    inout  wire [DATA_WIDTH-1:0] pa     ,
    inout  wire [DATA_WIDTH-1:0] pb     ,
    output wire                  oc0a   ,
    output wire                  oc0b
);

    reg  [DATA_WIDTH-1:0] memory  [0:(1<<ADDR_WIDTH)-1];
    reg  [ADDR_WIDTH-1:0] addr_buf                     ;
    wire                  readonly                     ;
    wire [DATA_WIDTH-1:0] pa_buf                       ;
    wire [DATA_WIDTH-1:0] pb_buf                       ;
    wire [DATA_WIDTH-1:0] tcnt0                        ;
    reg  [  ADDR_WIDTH:0] i                            ;

    always @(negedge clk)
        begin
            if (reset) begin
                for (i = 0; i < (1<<ADDR_WIDTH); i = i + 1) begin
                    memory[i[ADDR_WIDTH-1:0]] <= 0;
                end
            end
            else if (cs) begin
                if (we && !readonly) begin
                    memory[address] <= data;
                end else begin
                    addr_buf <= address;
                end
            end
            memory[`PINA] <= pa;
            memory[`PINB] <= pb;


            if (address == `TCNT0 && cs && we)
                memory[`TCNT0] <= data;
            else
                memory[`TCNT0] <= tcnt0;
        end

    assign data     = (cs && oe && !we) ? memory[addr_buf] : {DATA_WIDTH{1'bz}};
    assign readonly = (address == `PINA || address == `PINB);

    assign pa = pa_buf;
    assign pb = pb_buf;

    gpio_unit #(.DATA_WIDTH(DATA_WIDTH)) gpio (
        .clk      (clk           ),
        .reset    (reset         ),
        .mem_ddra (memory[`DDRA] ),
        .mem_ddrb (memory[`DDRB] ),
        .mem_porta(memory[`PORTA]),
        .mem_portb(memory[`PORTB]),
        .pa_buf   (pa_buf        ),
        .pb_buf   (pb_buf        )
    );

    timer_unit #(.DATA_WIDTH(DATA_WIDTH)) timer0 (
        .clk       (clk            ),
        .reset     (reset          ),
        .mem_tcnt0 (memory[`TCNT0] ),
        .mem_tccr0a(memory[`TCCR0A]),
        .mem_tccr0b(memory[`TCCR0B]),
        .mem_ocr0a (memory[`OCR0A] ),
        .mem_ocr0b (memory[`OCR0B] ),
        .tcnt0     (tcnt0          ),
        .oc0a      (oc0a           ),
        .oc0b      (oc0b           )
    );

endmodule
module gpio_sram #(
    parameter DATA_WIDTH   = 8 ,
    parameter ADDR_WIDTH   = 6 ,
    parameter I_ADDR_WIDTH = 10
) (

    input  wire                  clk    ,
    input  wire                  reset  ,
    input  wire                  oe     ,
    input  wire                  cs     ,
    input  wire                  we     ,
    input  wire [ADDR_WIDTH-1:0] address,
    inout  wire [DATA_WIDTH-1:0] data   ,

    inout  wire [DATA_WIDTH-1:0] pa     ,
    inout  wire [DATA_WIDTH-1:0] pb     ,
    output wire                  oc0a   ,
    output wire                  oc0b
);


    reg  [DATA_WIDTH-1:0] memory  [0:(1<<ADDR_WIDTH)-1];
    reg  [ADDR_WIDTH-1:0] addr_buf                     ;
    wire                  readonly                     ;
    wire [DATA_WIDTH-1:0] pa_buf                       ;
    wire [DATA_WIDTH-1:0] pb_buf                       ;
    wire [DATA_WIDTH-1:0] tcnt0                        ;
    reg  [  ADDR_WIDTH:0] i                            ;

    always @(negedge clk)
        begin
            if (reset) begin
                for (i = 0; i < (1<<ADDR_WIDTH); i = i + 1) begin
                    memory[i[ADDR_WIDTH-1:0]] <= 0;
                end
            end
            else if (cs) begin
                if (we && !readonly) begin
                    memory[address] <= data;
                end else begin
                    addr_buf <= address;
                end
            end
            memory[`PINA] <= pa;
            memory[`PINB] <= pb;


            if (address == `TCNT0 && cs && we)
                memory[`TCNT0] <= data;
            else
                memory[`TCNT0] <= tcnt0;
        end

    assign data     = (cs && oe && !we) ? memory[addr_buf] : {DATA_WIDTH{1'bz}};
    assign readonly = (address == `PINA || address == `PINB);

    assign pa = pa_buf;
    assign pb = pb_buf;

    gpio_unit #(.DATA_WIDTH(DATA_WIDTH)) gpio (
        .clk      (clk           ),
        .reset    (reset         ),
        .mem_ddra (memory[`DDRA] ),
        .mem_ddrb (memory[`DDRB] ),
        .mem_porta(memory[`PORTA]),
        .mem_portb(memory[`PORTB]),
        .pa_buf   (pa_buf        ),
        .pb_buf   (pb_buf        )
    );

    timer_unit #(.DATA_WIDTH(DATA_WIDTH)) timer0 (
        .clk       (clk            ),
        .reset     (reset          ),
        .mem_tcnt0 (memory[`TCNT0] ),
        .mem_tccr0a(memory[`TCCR0A]),
        .mem_tccr0b(memory[`TCCR0B]),
        .mem_ocr0a (memory[`OCR0A] ),
        .mem_ocr0b (memory[`OCR0B] ),
        .tcnt0     (tcnt0          ),
        .oc0a      (oc0a           ),
        .oc0b      (oc0b           )
    );

endmodule