data/full_repos/permissive/405799749/amg_new2/adder/FSA_16_64_Carry_select_adder.v
data/verilator_xmls/a1e22f4f-1bee-4d86-a007-eae88622d5c2.xml
module UBCSlB_55_46(Co, S, X, Y, Ci);
  output Co;
  output [55:46] S;
  input Ci;
  input [55:46] X;
  input [55:46] Y;
  wire Ci_0;
  wire Ci_1;
  wire Co_0;
  wire Co_1;
  wire [55:46] S_0;
  wire [55:46] S_1;
  assign S[46] = ( S_0[46] & ( ~ Ci ) ) | ( S_1[46] & Ci );
  assign S[47] = ( S_0[47] & ( ~ Ci ) ) | ( S_1[47] & Ci );
  assign S[48] = ( S_0[48] & ( ~ Ci ) ) | ( S_1[48] & Ci );
  assign S[49] = ( S_0[49] & ( ~ Ci ) ) | ( S_1[49] & Ci );
  assign S[50] = ( S_0[50] & ( ~ Ci ) ) | ( S_1[50] & Ci );
  assign S[51] = ( S_0[51] & ( ~ Ci ) ) | ( S_1[51] & Ci );
  assign S[52] = ( S_0[52] & ( ~ Ci ) ) | ( S_1[52] & Ci );
  assign S[53] = ( S_0[53] & ( ~ Ci ) ) | ( S_1[53] & Ci );
  assign S[54] = ( S_0[54] & ( ~ Ci ) ) | ( S_1[54] & Ci );
  assign S[55] = ( S_0[55] & ( ~ Ci ) ) | ( S_1[55] & Ci );
  assign Co = ( Co_0 & ( ~ Ci ) ) | ( Co_1 & Ci );
  UBOne_46 U0 (Ci_1);
  UBZero_46_46 U1 (Ci_0);
  UBRCB_55_46 U2 (Co_0, S_0, X, Y, Ci_0);
  UBRCB_55_46 U3 (Co_1, S_1, X, Y, Ci_1);
endmodule
module UBCSlB_55_46(Co, S, X, Y, Ci);

  output Co;
  output [55:46] S;
  input Ci;
  input [55:46] X;
  input [55:46] Y;
  wire Ci_0;
  wire Ci_1;
  wire Co_0;
  wire Co_1;
  wire [55:46] S_0;
  wire [55:46] S_1;
  assign S[46] = ( S_0[46] & ( ~ Ci ) ) | ( S_1[46] & Ci );
  assign S[47] = ( S_0[47] & ( ~ Ci ) ) | ( S_1[47] & Ci );
  assign S[48] = ( S_0[48] & ( ~ Ci ) ) | ( S_1[48] & Ci );
  assign S[49] = ( S_0[49] & ( ~ Ci ) ) | ( S_1[49] & Ci );
  assign S[50] = ( S_0[50] & ( ~ Ci ) ) | ( S_1[50] & Ci );
  assign S[51] = ( S_0[51] & ( ~ Ci ) ) | ( S_1[51] & Ci );
  assign S[52] = ( S_0[52] & ( ~ Ci ) ) | ( S_1[52] & Ci );
  assign S[53] = ( S_0[53] & ( ~ Ci ) ) | ( S_1[53] & Ci );
  assign S[54] = ( S_0[54] & ( ~ Ci ) ) | ( S_1[54] & Ci );
  assign S[55] = ( S_0[55] & ( ~ Ci ) ) | ( S_1[55] & Ci );
  assign Co = ( Co_0 & ( ~ Ci ) ) | ( Co_1 & Ci );
  UBOne_46 U0 (Ci_1);
  UBZero_46_46 U1 (Ci_0);
  UBRCB_55_46 U2 (Co_0, S_0, X, Y, Ci_0);
  UBRCB_55_46 U3 (Co_1, S_1, X, Y, Ci_1);
endmodule