data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/switch_control.v
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/switch_control.v:125: Cannot find include file: ../regmap/switch_setup_regmap_utils.vh\n  `include "../regmap/switch_setup_regmap_utils.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints,data/full_repos/permissive/447976230/../regmap/switch_setup_regmap_utils.vh\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints,data/full_repos/permissive/447976230/../regmap/switch_setup_regmap_utils.vh.v\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints,data/full_repos/permissive/447976230/../regmap/switch_setup_regmap_utils.vh.sv\n             ../regmap/switch_setup_regmap_utils.vh\n             ../regmap/switch_setup_regmap_utils.vh.v\n             ../regmap/switch_setup_regmap_utils.vh.sv\n             obj_dir/../regmap/switch_setup_regmap_utils.vh\n             obj_dir/../regmap/switch_setup_regmap_utils.vh.v\n             obj_dir/../regmap/switch_setup_regmap_utils.vh.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/switch_control.v:126: Cannot find include file: ../../../../../../lib/rfnoc/core/ctrlport.vh\n  `include "../../../../../../lib/rfnoc/core/ctrlport.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module switch_control #(
  parameter [19:0]  BASE_ADDRESS = 0,
  parameter [19:0]  SIZE_ADDRESS = 0
) (

  input  wire        ctrlport_clk,
  input  wire        ctrlport_rst,


  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [31:0] s_ctrlport_req_data,


  output reg         s_ctrlport_resp_ack,
  output reg  [ 1:0] s_ctrlport_resp_status = 2'b0,
  output reg  [31:0] s_ctrlport_resp_data = 32'b0,


  input  wire [ 7:0] atr_config_rf0,
  input  wire [ 7:0] atr_config_rf1,


  output wire tx0_sw1_sw2_ctrl,
  output wire tx0_sw3_a,
  output wire tx0_sw3_b,
  output wire tx0_sw4_a,
  output wire tx0_sw4_b,
  output wire tx0_sw5_a,
  output wire tx0_sw5_b,
  output wire tx0_sw6_a,
  output wire tx0_sw6_b,
  output wire tx0_sw7_a,
  output wire tx0_sw7_b,
  output wire tx0_sw8_v1,
  output wire tx0_sw8_v2,
  output wire tx0_sw8_v3,
  output wire tx0_sw9_a,
  output wire tx0_sw9_b,
  output wire tx0_sw10_a,
  output wire tx0_sw10_b,
  output wire tx0_sw11_a,
  output wire tx0_sw11_b,
  output wire tx0_sw13_v1,
  output wire tx0_sw14_v1,


  output wire tx1_sw1_sw2_ctrl,
  output wire tx1_sw3_a,
  output wire tx1_sw3_b,
  output wire tx1_sw4_a,
  output wire tx1_sw4_b,
  output wire tx1_sw5_a,
  output wire tx1_sw5_b,
  output wire tx1_sw6_a,
  output wire tx1_sw6_b,
  output wire tx1_sw7_a,
  output wire tx1_sw7_b,
  output wire tx1_sw8_v1,
  output wire tx1_sw8_v2,
  output wire tx1_sw8_v3,
  output wire tx1_sw9_a,
  output wire tx1_sw9_b,
  output wire tx1_sw10_a,
  output wire tx1_sw10_b,
  output wire tx1_sw11_a,
  output wire tx1_sw11_b,
  output wire tx1_sw13_v1,
  output wire tx1_sw14_v1,


  output wire rx0_sw1_a,
  output wire rx0_sw1_b,
  output wire rx0_sw2_a,
  output wire rx0_sw3_v1,
  output wire rx0_sw3_v2,
  output wire rx0_sw3_v3,
  output wire rx0_sw4_a,
  output wire rx0_sw5_a,
  output wire rx0_sw5_b,
  output wire rx0_sw6_a,
  output wire rx0_sw6_b,
  output wire rx0_sw7_sw8_ctrl,
  output wire rx0_sw9_v1,
  output wire rx0_sw10_v1,
  output wire rx0_sw11_v3,
  output wire rx0_sw11_v2,
  output wire rx0_sw11_v1,


  output wire rx1_sw1_a,
  output wire rx1_sw1_b,
  output wire rx1_sw2_a,
  output wire rx1_sw3_v1,
  output wire rx1_sw3_v2,
  output wire rx1_sw3_v3,
  output wire rx1_sw4_a,
  output wire rx1_sw5_a,
  output wire rx1_sw5_b,
  output wire rx1_sw6_a,
  output wire rx1_sw6_b,
  output wire rx1_sw7_sw8_ctrl,
  output wire rx1_sw9_v1,
  output wire rx1_sw10_v1,
  output wire rx1_sw11_v3,
  output wire rx1_sw11_v2,
  output wire rx1_sw11_v1
);

  `include "../regmap/switch_setup_regmap_utils.vh"
  `include "../../../../../../lib/rfnoc/core/ctrlport.vh"





  reg [ TX_SWITCH_1_2_SIZE-1:0] tx0_switch_1_2_reg;
  reg [   TX_SWITCH_3_SIZE-1:0] tx0_switch_3_reg;
  reg [   TX_SWITCH_4_SIZE-1:0] tx0_switch_4_reg;
  reg [   TX_SWITCH_5_SIZE-1:0] tx0_switch_5_reg;
  reg [   TX_SWITCH_6_SIZE-1:0] tx0_switch_6_reg;
  reg [   TX_SWITCH_7_SIZE-1:0] tx0_switch_7_reg;
  reg [   TX_SWITCH_8_SIZE-1:0] tx0_switch_8_reg;
  reg [   TX_SWITCH_9_SIZE-1:0] tx0_switch_9_reg;
  reg [  TX_SWITCH_10_SIZE-1:0] tx0_switch_10_reg;
  reg [  TX_SWITCH_11_SIZE-1:0] tx0_switch_11_reg;
  reg [  TX_SWITCH_13_SIZE-1:0] tx0_switch_13_reg;
  reg [  TX_SWITCH_14_SIZE-1:0] tx0_switch_14_reg;


  reg [ TX_SWITCH_1_2_SIZE-1:0] tx1_switch_1_2_reg;
  reg [   TX_SWITCH_3_SIZE-1:0] tx1_switch_3_reg;
  reg [   TX_SWITCH_4_SIZE-1:0] tx1_switch_4_reg;
  reg [   TX_SWITCH_5_SIZE-1:0] tx1_switch_5_reg;
  reg [   TX_SWITCH_6_SIZE-1:0] tx1_switch_6_reg;
  reg [   TX_SWITCH_7_SIZE-1:0] tx1_switch_7_reg;
  reg [   TX_SWITCH_8_SIZE-1:0] tx1_switch_8_reg;
  reg [   TX_SWITCH_9_SIZE-1:0] tx1_switch_9_reg;
  reg [  TX_SWITCH_10_SIZE-1:0] tx1_switch_10_reg;
  reg [  TX_SWITCH_11_SIZE-1:0] tx1_switch_11_reg;
  reg [  TX_SWITCH_13_SIZE-1:0] tx1_switch_13_reg;
  reg [  TX_SWITCH_14_SIZE-1:0] tx1_switch_14_reg;


  reg [   RX_SWITCH_1_SIZE-1:0] rx0_switch_1_reg;
  reg [   RX_SWITCH_2_SIZE-1:0] rx0_switch_2_reg;
  reg [   RX_SWITCH_3_SIZE-1:0] rx0_switch_3_reg;
  reg [   RX_SWITCH_4_SIZE-1:0] rx0_switch_4_reg;
  reg [   RX_SWITCH_5_SIZE-1:0] rx0_switch_5_reg;
  reg [   RX_SWITCH_6_SIZE-1:0] rx0_switch_6_reg;
  reg [ RX_SWITCH_7_8_SIZE-1:0] rx0_switch_7_8_reg;
  reg [   RX_SWITCH_9_SIZE-1:0] rx0_switch_9_reg;
  reg [  RX_SWITCH_10_SIZE-1:0] rx0_switch_10_reg;
  reg [  RX_SWITCH_11_SIZE-1:0] rx0_switch_11_reg;


  reg [   RX_SWITCH_1_SIZE-1:0] rx1_switch_1_reg;
  reg [   RX_SWITCH_2_SIZE-1:0] rx1_switch_2_reg;
  reg [   RX_SWITCH_3_SIZE-1:0] rx1_switch_3_reg;
  reg [   RX_SWITCH_4_SIZE-1:0] rx1_switch_4_reg;
  reg [   RX_SWITCH_5_SIZE-1:0] rx1_switch_5_reg;
  reg [   RX_SWITCH_6_SIZE-1:0] rx1_switch_6_reg;
  reg [ RX_SWITCH_7_8_SIZE-1:0] rx1_switch_7_8_reg;
  reg [   RX_SWITCH_9_SIZE-1:0] rx1_switch_9_reg;
  reg [  RX_SWITCH_10_SIZE-1:0] rx1_switch_10_reg;
  reg [  RX_SWITCH_11_SIZE-1:0] rx1_switch_11_reg;




  reg         ram_rx0_wea;
  wire [31:0] ram_rx0_doa;
  wire [31:0] ram_rx0_dob;

  reg         ram_rx1_wea;
  wire [31:0] ram_rx1_doa;
  wire [31:0] ram_rx1_dob;

  reg         ram_tx0_wea;
  wire [31:0] ram_tx0_doa;
  wire [31:0] ram_tx0_dob;

  reg         ram_tx1_wea;
  wire [31:0] ram_tx1_doa;
  wire [31:0] ram_tx1_dob;






  wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + SIZE_ADDRESS);

  reg  [ 1:0] read_req_shift_reg = 2'b0;


  wire [31:0] register_base_address = {s_ctrlport_req_addr[19:10], 8'b0, s_ctrlport_req_addr[1:0]};


  wire [ 7:0] register_index = s_ctrlport_req_addr[9:2];

  always @(posedge ctrlport_clk) begin

    if (ctrlport_rst) begin
      s_ctrlport_resp_ack <= 1'b0;

      read_req_shift_reg <= 2'b0;

      ram_tx0_wea <= 1'b0;
      ram_tx1_wea <= 1'b0;
      ram_rx0_wea <= 1'b0;
      ram_rx1_wea <= 1'b0;

    end else begin

      read_req_shift_reg <= {read_req_shift_reg[0], s_ctrlport_req_rd};

      ram_tx0_wea <= 1'b0;
      ram_tx1_wea <= 1'b0;
      ram_rx0_wea <= 1'b0;
      ram_rx1_wea <= 1'b0;


      if (s_ctrlport_req_wr) begin

        s_ctrlport_resp_ack     <= 1'b1;
        s_ctrlport_resp_data    <= {32{1'bx}};
        s_ctrlport_resp_status  <= CTRL_STS_OKAY;

        case (register_base_address)
          BASE_ADDRESS + TX0_PATH_CONTROL(0): begin
            ram_tx0_wea <= 1'b1;
          end

          BASE_ADDRESS + TX1_PATH_CONTROL(0): begin
            ram_tx1_wea <= 1'b1;
          end

          BASE_ADDRESS + RX0_PATH_CONTROL(0): begin
            ram_rx0_wea <= 1'b1;
          end

          BASE_ADDRESS + RX1_PATH_CONTROL(0): begin
            ram_rx1_wea <= 1'b1;
          end


          default: begin
            if (address_in_range) begin
              s_ctrlport_resp_status <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack <= 1'b0;
            end
          end
        endcase




      end else if (read_req_shift_reg[1]) begin

        s_ctrlport_resp_ack     <= 1'b1;
        s_ctrlport_resp_status  <= CTRL_STS_OKAY;
        s_ctrlport_resp_data    <= {32{1'b0}};

        case (register_base_address)
          BASE_ADDRESS + TX0_PATH_CONTROL(0): begin
            s_ctrlport_resp_data <= ram_tx0_doa & TX_PATH_CONTROL_MASK;
          end
          BASE_ADDRESS + TX1_PATH_CONTROL(0): begin
            s_ctrlport_resp_data <= ram_tx1_doa & TX_PATH_CONTROL_MASK;
          end
          BASE_ADDRESS + RX0_PATH_CONTROL(0): begin
            s_ctrlport_resp_data <= ram_rx0_doa & RX_PATH_CONTROL_MASK;
          end
          BASE_ADDRESS + RX1_PATH_CONTROL(0): begin
            s_ctrlport_resp_data <= ram_rx1_doa & RX_PATH_CONTROL_MASK;
          end

          default: begin
            if (address_in_range) begin
              s_ctrlport_resp_status <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack <= 1'b0;
            end
          end
        endcase


      end else begin
        s_ctrlport_resp_ack <= 1'b0;
      end
    end
  end


  reg [ 7:0] ram_addr   =  8'b0;
  reg [31:0] ram_datain = 32'b0;
  always @(posedge ctrlport_clk) begin

    ram_addr   <= register_index;
    ram_datain <= s_ctrlport_req_data;


    tx0_switch_1_2_reg <= ram_tx0_dob[TX_SWITCH_1_2];
    tx0_switch_3_reg   <= ram_tx0_dob[TX_SWITCH_3_MSB  : TX_SWITCH_3];
    tx0_switch_4_reg   <= ram_tx0_dob[TX_SWITCH_4_MSB  : TX_SWITCH_4];
    tx0_switch_5_reg   <= ram_tx0_dob[TX_SWITCH_5_MSB  : TX_SWITCH_5];
    tx0_switch_6_reg   <= ram_tx0_dob[TX_SWITCH_6_MSB  : TX_SWITCH_6];
    tx0_switch_7_reg   <= ram_tx0_dob[TX_SWITCH_7_MSB  : TX_SWITCH_7];
    tx0_switch_8_reg   <= ram_tx0_dob[TX_SWITCH_8_MSB  : TX_SWITCH_8];
    tx0_switch_9_reg   <= ram_tx0_dob[TX_SWITCH_9_MSB  : TX_SWITCH_9];
    tx0_switch_10_reg  <= ram_tx0_dob[TX_SWITCH_10_MSB : TX_SWITCH_10];
    tx0_switch_11_reg  <= ram_tx0_dob[TX_SWITCH_11_MSB : TX_SWITCH_11];
    tx0_switch_13_reg  <= ram_tx0_dob[TX_SWITCH_13];
    tx0_switch_14_reg  <= ram_tx0_dob[TX_SWITCH_14];

    tx1_switch_1_2_reg <= ram_tx1_dob[TX_SWITCH_1_2];
    tx1_switch_3_reg   <= ram_tx1_dob[TX_SWITCH_3_MSB  : TX_SWITCH_3];
    tx1_switch_4_reg   <= ram_tx1_dob[TX_SWITCH_4_MSB  : TX_SWITCH_4];
    tx1_switch_5_reg   <= ram_tx1_dob[TX_SWITCH_5_MSB  : TX_SWITCH_5];
    tx1_switch_6_reg   <= ram_tx1_dob[TX_SWITCH_6_MSB  : TX_SWITCH_6];
    tx1_switch_7_reg   <= ram_tx1_dob[TX_SWITCH_7_MSB  : TX_SWITCH_7];
    tx1_switch_8_reg   <= ram_tx1_dob[TX_SWITCH_8_MSB  : TX_SWITCH_8];
    tx1_switch_9_reg   <= ram_tx1_dob[TX_SWITCH_9_MSB  : TX_SWITCH_9];
    tx1_switch_10_reg  <= ram_tx1_dob[TX_SWITCH_10_MSB : TX_SWITCH_10];
    tx1_switch_11_reg  <= ram_tx1_dob[TX_SWITCH_11_MSB : TX_SWITCH_11];
    tx1_switch_13_reg  <= ram_tx1_dob[TX_SWITCH_13];
    tx1_switch_14_reg  <= ram_tx1_dob[TX_SWITCH_14];

    rx0_switch_1_reg   <= ram_rx0_dob[RX_SWITCH_1_MSB : RX_SWITCH_1];
    rx0_switch_2_reg   <= ram_rx0_dob[RX_SWITCH_2];
    rx0_switch_3_reg   <= ram_rx0_dob[RX_SWITCH_3_MSB : RX_SWITCH_3];
    rx0_switch_4_reg   <= ram_rx0_dob[RX_SWITCH_4];
    rx0_switch_5_reg   <= ram_rx0_dob[RX_SWITCH_5_MSB : RX_SWITCH_5];
    rx0_switch_6_reg   <= ram_rx0_dob[RX_SWITCH_6_MSB : RX_SWITCH_6];
    rx0_switch_7_8_reg <= ram_rx0_dob[RX_SWITCH_7_8];
    rx0_switch_9_reg   <= ram_rx0_dob[RX_SWITCH_9];
    rx0_switch_10_reg  <= ram_rx0_dob[RX_SWITCH_10];
    rx0_switch_11_reg  <= ram_rx0_dob[RX_SWITCH_11_MSB: RX_SWITCH_11];

    rx1_switch_1_reg   <= ram_rx1_dob[RX_SWITCH_1_MSB : RX_SWITCH_1];
    rx1_switch_2_reg   <= ram_rx1_dob[RX_SWITCH_2];
    rx1_switch_3_reg   <= ram_rx1_dob[RX_SWITCH_3_MSB : RX_SWITCH_3];
    rx1_switch_4_reg   <= ram_rx1_dob[RX_SWITCH_4];
    rx1_switch_5_reg   <= ram_rx1_dob[RX_SWITCH_5_MSB : RX_SWITCH_5];
    rx1_switch_6_reg   <= ram_rx1_dob[RX_SWITCH_6_MSB : RX_SWITCH_6];
    rx1_switch_7_8_reg <= ram_rx1_dob[RX_SWITCH_7_8];
    rx1_switch_9_reg   <= ram_rx1_dob[RX_SWITCH_9];
    rx1_switch_10_reg  <= ram_rx1_dob[RX_SWITCH_10];
    rx1_switch_11_reg  <= ram_rx1_dob[RX_SWITCH_11_MSB: RX_SWITCH_11];
  end

  ram_2port #(
    .DWIDTH     (32),
    .AWIDTH     (8),
    .RW_MODE    ("READ-FIRST"),
    .RAM_TYPE   ("AUTOMATIC"),
    .OUT_REG    (0),
    .INIT_FILE  ("register_endpoints/memory_init_files/tx0_path_defaults.hex")
  ) ram_tx0_i (
    .clka   (ctrlport_clk),
    .ena    (1'b1),
    .wea    (ram_tx0_wea),
    .addra  (ram_addr),
    .dia    (ram_datain),
    .doa    (ram_tx0_doa),
    .clkb   (ctrlport_clk),
    .enb    (1'b1),
    .web    (1'b0),
    .addrb  (atr_config_rf0),
    .dib    (0),
    .dob    (ram_tx0_dob));

  ram_2port #(
    .DWIDTH     (32),
    .AWIDTH     (8),
    .RW_MODE    ("READ-FIRST"),
    .RAM_TYPE   ("AUTOMATIC"),
    .OUT_REG    (0),
    .INIT_FILE  ("register_endpoints/memory_init_files/tx1_path_defaults.hex")
  ) ram_tx1_i (
    .clka   (ctrlport_clk),
    .ena    (1'b1),
    .wea    (ram_tx1_wea),
    .addra  (ram_addr),
    .dia    (ram_datain),
    .doa    (ram_tx1_doa),
    .clkb   (ctrlport_clk),
    .enb    (1'b1),
    .web    (1'b0),
    .addrb  (atr_config_rf1),
    .dib    (0),
    .dob    (ram_tx1_dob));

  ram_2port #(
    .DWIDTH     (32),
    .AWIDTH     (8),
    .RW_MODE    ("READ-FIRST"),
    .RAM_TYPE   ("AUTOMATIC"),
    .OUT_REG    (0),
    .INIT_FILE  ("register_endpoints/memory_init_files/rx0_path_defaults.hex")
  ) ram_rx0_i (
    .clka   (ctrlport_clk),
    .ena    (1'b1),
    .wea    (ram_rx0_wea),
    .addra  (ram_addr),
    .dia    (ram_datain),
    .doa    (ram_rx0_doa),
    .clkb   (ctrlport_clk),
    .enb    (1'b1),
    .web    (1'b0),
    .addrb  (atr_config_rf0),
    .dib    (0),
    .dob    (ram_rx0_dob));

  ram_2port #(
    .DWIDTH     (32),
    .AWIDTH     (8),
    .RW_MODE    ("READ-FIRST"),
    .RAM_TYPE   ("AUTOMATIC"),
    .OUT_REG    (0),
    .INIT_FILE  ("register_endpoints/memory_init_files/rx1_path_defaults.hex")
  ) ram_rx1_i (
    .clka   (ctrlport_clk),
    .ena    (1'b1),
    .wea    (ram_rx1_wea),
    .addra  (ram_addr),
    .dia    (ram_datain),
    .doa    (ram_rx1_doa),
    .clkb   (ctrlport_clk),
    .enb    (1'b1),
    .web    (1'b0),
    .addrb  (atr_config_rf1),
    .dib    (0),
    .dob    (ram_rx1_dob));

  assign tx0_sw1_sw2_ctrl = tx0_switch_1_2_reg;
  assign tx0_sw3_a        = tx0_switch_3_reg[0];
  assign tx0_sw3_b        = tx0_switch_3_reg[1];
  assign tx0_sw4_a        = tx0_switch_4_reg[0];
  assign tx0_sw4_b        = tx0_switch_4_reg[1];
  assign tx0_sw5_a        = tx0_switch_5_reg[0];
  assign tx0_sw5_b        = tx0_switch_5_reg[1];
  assign tx0_sw6_a        = tx0_switch_6_reg[0];
  assign tx0_sw6_b        = tx0_switch_6_reg[1];
  assign tx0_sw7_a        = tx0_switch_7_reg[0];
  assign tx0_sw7_b        = tx0_switch_7_reg[1];
  assign tx0_sw8_v1       = tx0_switch_8_reg[0];
  assign tx0_sw8_v2       = tx0_switch_8_reg[1];
  assign tx0_sw8_v3       = tx0_switch_8_reg[2];
  assign tx0_sw9_a        = tx0_switch_9_reg[0];
  assign tx0_sw9_b        = tx0_switch_9_reg[1];
  assign tx0_sw10_a       = tx0_switch_10_reg[0];
  assign tx0_sw10_b       = tx0_switch_10_reg[1];
  assign tx0_sw11_a       = tx0_switch_11_reg[0];
  assign tx0_sw11_b       = tx0_switch_11_reg[1];
  assign tx0_sw13_v1      = tx0_switch_13_reg;
  assign tx0_sw14_v1      = tx0_switch_14_reg;

  assign tx1_sw1_sw2_ctrl = tx1_switch_1_2_reg;
  assign tx1_sw3_a        = tx1_switch_3_reg[0];
  assign tx1_sw3_b        = tx1_switch_3_reg[1];
  assign tx1_sw4_a        = tx1_switch_4_reg[0];
  assign tx1_sw4_b        = tx1_switch_4_reg[1];
  assign tx1_sw5_a        = tx1_switch_5_reg[0];
  assign tx1_sw5_b        = tx1_switch_5_reg[1];
  assign tx1_sw6_a        = tx1_switch_6_reg[0];
  assign tx1_sw6_b        = tx1_switch_6_reg[1];
  assign tx1_sw7_a        = tx1_switch_7_reg[0];
  assign tx1_sw7_b        = tx1_switch_7_reg[1];
  assign tx1_sw8_v1       = tx1_switch_8_reg[0];
  assign tx1_sw8_v2       = tx1_switch_8_reg[1];
  assign tx1_sw8_v3       = tx1_switch_8_reg[2];
  assign tx1_sw9_a        = tx1_switch_9_reg[0];
  assign tx1_sw9_b        = tx1_switch_9_reg[1];
  assign tx1_sw10_a       = tx1_switch_10_reg[0];
  assign tx1_sw10_b       = tx1_switch_10_reg[1];
  assign tx1_sw11_a       = tx1_switch_11_reg[0];
  assign tx1_sw11_b       = tx1_switch_11_reg[1];
  assign tx1_sw13_v1      = tx1_switch_13_reg;
  assign tx1_sw14_v1      = tx1_switch_14_reg;

  assign rx0_sw1_a        = rx0_switch_1_reg[0];
  assign rx0_sw1_b        = rx0_switch_1_reg[1];
  assign rx0_sw2_a        = rx0_switch_2_reg;
  assign rx0_sw3_v1       = rx0_switch_3_reg[0];
  assign rx0_sw3_v2       = rx0_switch_3_reg[1];
  assign rx0_sw3_v3       = rx0_switch_3_reg[2];
  assign rx0_sw4_a        = rx0_switch_4_reg;
  assign rx0_sw5_a        = rx0_switch_5_reg[0];
  assign rx0_sw5_b        = rx0_switch_5_reg[1];
  assign rx0_sw6_a        = rx0_switch_6_reg[0];
  assign rx0_sw6_b        = rx0_switch_6_reg[1];
  assign rx0_sw7_sw8_ctrl = rx0_switch_7_8_reg;
  assign rx0_sw9_v1       = rx0_switch_9_reg;
  assign rx0_sw10_v1      = rx0_switch_10_reg;
  assign rx0_sw11_v1      = rx0_switch_11_reg[0];
  assign rx0_sw11_v2      = rx0_switch_11_reg[1];
  assign rx0_sw11_v3      = rx0_switch_11_reg[2];

  assign rx1_sw1_a        = rx1_switch_1_reg[0];
  assign rx1_sw1_b        = rx1_switch_1_reg[1];
  assign rx1_sw2_a        = rx1_switch_2_reg;
  assign rx1_sw3_v1       = rx1_switch_3_reg[0];
  assign rx1_sw3_v2       = rx1_switch_3_reg[1];
  assign rx1_sw3_v3       = rx1_switch_3_reg[2];
  assign rx1_sw4_a        = rx1_switch_4_reg;
  assign rx1_sw5_a        = rx1_switch_5_reg[0];
  assign rx1_sw5_b        = rx1_switch_5_reg[1];
  assign rx1_sw6_a        = rx1_switch_6_reg[0];
  assign rx1_sw6_b        = rx1_switch_6_reg[1];
  assign rx1_sw7_sw8_ctrl = rx1_switch_7_8_reg;
  assign rx1_sw9_v1       = rx1_switch_9_reg;
  assign rx1_sw10_v1      = rx1_switch_10_reg;
  assign rx1_sw11_v1      = rx1_switch_11_reg[0];
  assign rx1_sw11_v2      = rx1_switch_11_reg[1];
  assign rx1_sw11_v3      = rx1_switch_11_reg[2];

endmodule
module switch_control #(
  parameter [19:0]  BASE_ADDRESS = 0,
  parameter [19:0]  SIZE_ADDRESS = 0
) (

  input  wire        ctrlport_clk,
  input  wire        ctrlport_rst,


  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [31:0] s_ctrlport_req_data,


  output reg         s_ctrlport_resp_ack,
  output reg  [ 1:0] s_ctrlport_resp_status = 2'b0,
  output reg  [31:0] s_ctrlport_resp_data = 32'b0,


  input  wire [ 7:0] atr_config_rf0,
  input  wire [ 7:0] atr_config_rf1,


  output wire tx0_sw1_sw2_ctrl,
  output wire tx0_sw3_a,
  output wire tx0_sw3_b,
  output wire tx0_sw4_a,
  output wire tx0_sw4_b,
  output wire tx0_sw5_a,
  output wire tx0_sw5_b,
  output wire tx0_sw6_a,
  output wire tx0_sw6_b,
  output wire tx0_sw7_a,
  output wire tx0_sw7_b,
  output wire tx0_sw8_v1,
  output wire tx0_sw8_v2,
  output wire tx0_sw8_v3,
  output wire tx0_sw9_a,
  output wire tx0_sw9_b,
  output wire tx0_sw10_a,
  output wire tx0_sw10_b,
  output wire tx0_sw11_a,
  output wire tx0_sw11_b,
  output wire tx0_sw13_v1,
  output wire tx0_sw14_v1,


  output wire tx1_sw1_sw2_ctrl,
  output wire tx1_sw3_a,
  output wire tx1_sw3_b,
  output wire tx1_sw4_a,
  output wire tx1_sw4_b,
  output wire tx1_sw5_a,
  output wire tx1_sw5_b,
  output wire tx1_sw6_a,
  output wire tx1_sw6_b,
  output wire tx1_sw7_a,
  output wire tx1_sw7_b,
  output wire tx1_sw8_v1,
  output wire tx1_sw8_v2,
  output wire tx1_sw8_v3,
  output wire tx1_sw9_a,
  output wire tx1_sw9_b,
  output wire tx1_sw10_a,
  output wire tx1_sw10_b,
  output wire tx1_sw11_a,
  output wire tx1_sw11_b,
  output wire tx1_sw13_v1,
  output wire tx1_sw14_v1,


  output wire rx0_sw1_a,
  output wire rx0_sw1_b,
  output wire rx0_sw2_a,
  output wire rx0_sw3_v1,
  output wire rx0_sw3_v2,
  output wire rx0_sw3_v3,
  output wire rx0_sw4_a,
  output wire rx0_sw5_a,
  output wire rx0_sw5_b,
  output wire rx0_sw6_a,
  output wire rx0_sw6_b,
  output wire rx0_sw7_sw8_ctrl,
  output wire rx0_sw9_v1,
  output wire rx0_sw10_v1,
  output wire rx0_sw11_v3,
  output wire rx0_sw11_v2,
  output wire rx0_sw11_v1,


  output wire rx1_sw1_a,
  output wire rx1_sw1_b,
  output wire rx1_sw2_a,
  output wire rx1_sw3_v1,
  output wire rx1_sw3_v2,
  output wire rx1_sw3_v3,
  output wire rx1_sw4_a,
  output wire rx1_sw5_a,
  output wire rx1_sw5_b,
  output wire rx1_sw6_a,
  output wire rx1_sw6_b,
  output wire rx1_sw7_sw8_ctrl,
  output wire rx1_sw9_v1,
  output wire rx1_sw10_v1,
  output wire rx1_sw11_v3,
  output wire rx1_sw11_v2,
  output wire rx1_sw11_v1
);


  `include "../regmap/switch_setup_regmap_utils.vh"
  `include "../../../../../../lib/rfnoc/core/ctrlport.vh"





  reg [ TX_SWITCH_1_2_SIZE-1:0] tx0_switch_1_2_reg;
  reg [   TX_SWITCH_3_SIZE-1:0] tx0_switch_3_reg;
  reg [   TX_SWITCH_4_SIZE-1:0] tx0_switch_4_reg;
  reg [   TX_SWITCH_5_SIZE-1:0] tx0_switch_5_reg;
  reg [   TX_SWITCH_6_SIZE-1:0] tx0_switch_6_reg;
  reg [   TX_SWITCH_7_SIZE-1:0] tx0_switch_7_reg;
  reg [   TX_SWITCH_8_SIZE-1:0] tx0_switch_8_reg;
  reg [   TX_SWITCH_9_SIZE-1:0] tx0_switch_9_reg;
  reg [  TX_SWITCH_10_SIZE-1:0] tx0_switch_10_reg;
  reg [  TX_SWITCH_11_SIZE-1:0] tx0_switch_11_reg;
  reg [  TX_SWITCH_13_SIZE-1:0] tx0_switch_13_reg;
  reg [  TX_SWITCH_14_SIZE-1:0] tx0_switch_14_reg;


  reg [ TX_SWITCH_1_2_SIZE-1:0] tx1_switch_1_2_reg;
  reg [   TX_SWITCH_3_SIZE-1:0] tx1_switch_3_reg;
  reg [   TX_SWITCH_4_SIZE-1:0] tx1_switch_4_reg;
  reg [   TX_SWITCH_5_SIZE-1:0] tx1_switch_5_reg;
  reg [   TX_SWITCH_6_SIZE-1:0] tx1_switch_6_reg;
  reg [   TX_SWITCH_7_SIZE-1:0] tx1_switch_7_reg;
  reg [   TX_SWITCH_8_SIZE-1:0] tx1_switch_8_reg;
  reg [   TX_SWITCH_9_SIZE-1:0] tx1_switch_9_reg;
  reg [  TX_SWITCH_10_SIZE-1:0] tx1_switch_10_reg;
  reg [  TX_SWITCH_11_SIZE-1:0] tx1_switch_11_reg;
  reg [  TX_SWITCH_13_SIZE-1:0] tx1_switch_13_reg;
  reg [  TX_SWITCH_14_SIZE-1:0] tx1_switch_14_reg;


  reg [   RX_SWITCH_1_SIZE-1:0] rx0_switch_1_reg;
  reg [   RX_SWITCH_2_SIZE-1:0] rx0_switch_2_reg;
  reg [   RX_SWITCH_3_SIZE-1:0] rx0_switch_3_reg;
  reg [   RX_SWITCH_4_SIZE-1:0] rx0_switch_4_reg;
  reg [   RX_SWITCH_5_SIZE-1:0] rx0_switch_5_reg;
  reg [   RX_SWITCH_6_SIZE-1:0] rx0_switch_6_reg;
  reg [ RX_SWITCH_7_8_SIZE-1:0] rx0_switch_7_8_reg;
  reg [   RX_SWITCH_9_SIZE-1:0] rx0_switch_9_reg;
  reg [  RX_SWITCH_10_SIZE-1:0] rx0_switch_10_reg;
  reg [  RX_SWITCH_11_SIZE-1:0] rx0_switch_11_reg;


  reg [   RX_SWITCH_1_SIZE-1:0] rx1_switch_1_reg;
  reg [   RX_SWITCH_2_SIZE-1:0] rx1_switch_2_reg;
  reg [   RX_SWITCH_3_SIZE-1:0] rx1_switch_3_reg;
  reg [   RX_SWITCH_4_SIZE-1:0] rx1_switch_4_reg;
  reg [   RX_SWITCH_5_SIZE-1:0] rx1_switch_5_reg;
  reg [   RX_SWITCH_6_SIZE-1:0] rx1_switch_6_reg;
  reg [ RX_SWITCH_7_8_SIZE-1:0] rx1_switch_7_8_reg;
  reg [   RX_SWITCH_9_SIZE-1:0] rx1_switch_9_reg;
  reg [  RX_SWITCH_10_SIZE-1:0] rx1_switch_10_reg;
  reg [  RX_SWITCH_11_SIZE-1:0] rx1_switch_11_reg;




  reg         ram_rx0_wea;
  wire [31:0] ram_rx0_doa;
  wire [31:0] ram_rx0_dob;

  reg         ram_rx1_wea;
  wire [31:0] ram_rx1_doa;
  wire [31:0] ram_rx1_dob;

  reg         ram_tx0_wea;
  wire [31:0] ram_tx0_doa;
  wire [31:0] ram_tx0_dob;

  reg         ram_tx1_wea;
  wire [31:0] ram_tx1_doa;
  wire [31:0] ram_tx1_dob;






  wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + SIZE_ADDRESS);

  reg  [ 1:0] read_req_shift_reg = 2'b0;


  wire [31:0] register_base_address = {s_ctrlport_req_addr[19:10], 8'b0, s_ctrlport_req_addr[1:0]};


  wire [ 7:0] register_index = s_ctrlport_req_addr[9:2];

  always @(posedge ctrlport_clk) begin

    if (ctrlport_rst) begin
      s_ctrlport_resp_ack <= 1'b0;

      read_req_shift_reg <= 2'b0;

      ram_tx0_wea <= 1'b0;
      ram_tx1_wea <= 1'b0;
      ram_rx0_wea <= 1'b0;
      ram_rx1_wea <= 1'b0;

    end else begin

      read_req_shift_reg <= {read_req_shift_reg[0], s_ctrlport_req_rd};

      ram_tx0_wea <= 1'b0;
      ram_tx1_wea <= 1'b0;
      ram_rx0_wea <= 1'b0;
      ram_rx1_wea <= 1'b0;


      if (s_ctrlport_req_wr) begin

        s_ctrlport_resp_ack     <= 1'b1;
        s_ctrlport_resp_data    <= {32{1'bx}};
        s_ctrlport_resp_status  <= CTRL_STS_OKAY;

        case (register_base_address)
          BASE_ADDRESS + TX0_PATH_CONTROL(0): begin
            ram_tx0_wea <= 1'b1;
          end

          BASE_ADDRESS + TX1_PATH_CONTROL(0): begin
            ram_tx1_wea <= 1'b1;
          end

          BASE_ADDRESS + RX0_PATH_CONTROL(0): begin
            ram_rx0_wea <= 1'b1;
          end

          BASE_ADDRESS + RX1_PATH_CONTROL(0): begin
            ram_rx1_wea <= 1'b1;
          end


          default: begin
            if (address_in_range) begin
              s_ctrlport_resp_status <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack <= 1'b0;
            end
          end
        endcase




      end else if (read_req_shift_reg[1]) begin

        s_ctrlport_resp_ack     <= 1'b1;
        s_ctrlport_resp_status  <= CTRL_STS_OKAY;
        s_ctrlport_resp_data    <= {32{1'b0}};

        case (register_base_address)
          BASE_ADDRESS + TX0_PATH_CONTROL(0): begin
            s_ctrlport_resp_data <= ram_tx0_doa & TX_PATH_CONTROL_MASK;
          end
          BASE_ADDRESS + TX1_PATH_CONTROL(0): begin
            s_ctrlport_resp_data <= ram_tx1_doa & TX_PATH_CONTROL_MASK;
          end
          BASE_ADDRESS + RX0_PATH_CONTROL(0): begin
            s_ctrlport_resp_data <= ram_rx0_doa & RX_PATH_CONTROL_MASK;
          end
          BASE_ADDRESS + RX1_PATH_CONTROL(0): begin
            s_ctrlport_resp_data <= ram_rx1_doa & RX_PATH_CONTROL_MASK;
          end

          default: begin
            if (address_in_range) begin
              s_ctrlport_resp_status <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack <= 1'b0;
            end
          end
        endcase


      end else begin
        s_ctrlport_resp_ack <= 1'b0;
      end
    end
  end


  reg [ 7:0] ram_addr   =  8'b0;
  reg [31:0] ram_datain = 32'b0;
  always @(posedge ctrlport_clk) begin

    ram_addr   <= register_index;
    ram_datain <= s_ctrlport_req_data;


    tx0_switch_1_2_reg <= ram_tx0_dob[TX_SWITCH_1_2];
    tx0_switch_3_reg   <= ram_tx0_dob[TX_SWITCH_3_MSB  : TX_SWITCH_3];
    tx0_switch_4_reg   <= ram_tx0_dob[TX_SWITCH_4_MSB  : TX_SWITCH_4];
    tx0_switch_5_reg   <= ram_tx0_dob[TX_SWITCH_5_MSB  : TX_SWITCH_5];
    tx0_switch_6_reg   <= ram_tx0_dob[TX_SWITCH_6_MSB  : TX_SWITCH_6];
    tx0_switch_7_reg   <= ram_tx0_dob[TX_SWITCH_7_MSB  : TX_SWITCH_7];
    tx0_switch_8_reg   <= ram_tx0_dob[TX_SWITCH_8_MSB  : TX_SWITCH_8];
    tx0_switch_9_reg   <= ram_tx0_dob[TX_SWITCH_9_MSB  : TX_SWITCH_9];
    tx0_switch_10_reg  <= ram_tx0_dob[TX_SWITCH_10_MSB : TX_SWITCH_10];
    tx0_switch_11_reg  <= ram_tx0_dob[TX_SWITCH_11_MSB : TX_SWITCH_11];
    tx0_switch_13_reg  <= ram_tx0_dob[TX_SWITCH_13];
    tx0_switch_14_reg  <= ram_tx0_dob[TX_SWITCH_14];

    tx1_switch_1_2_reg <= ram_tx1_dob[TX_SWITCH_1_2];
    tx1_switch_3_reg   <= ram_tx1_dob[TX_SWITCH_3_MSB  : TX_SWITCH_3];
    tx1_switch_4_reg   <= ram_tx1_dob[TX_SWITCH_4_MSB  : TX_SWITCH_4];
    tx1_switch_5_reg   <= ram_tx1_dob[TX_SWITCH_5_MSB  : TX_SWITCH_5];
    tx1_switch_6_reg   <= ram_tx1_dob[TX_SWITCH_6_MSB  : TX_SWITCH_6];
    tx1_switch_7_reg   <= ram_tx1_dob[TX_SWITCH_7_MSB  : TX_SWITCH_7];
    tx1_switch_8_reg   <= ram_tx1_dob[TX_SWITCH_8_MSB  : TX_SWITCH_8];
    tx1_switch_9_reg   <= ram_tx1_dob[TX_SWITCH_9_MSB  : TX_SWITCH_9];
    tx1_switch_10_reg  <= ram_tx1_dob[TX_SWITCH_10_MSB : TX_SWITCH_10];
    tx1_switch_11_reg  <= ram_tx1_dob[TX_SWITCH_11_MSB : TX_SWITCH_11];
    tx1_switch_13_reg  <= ram_tx1_dob[TX_SWITCH_13];
    tx1_switch_14_reg  <= ram_tx1_dob[TX_SWITCH_14];

    rx0_switch_1_reg   <= ram_rx0_dob[RX_SWITCH_1_MSB : RX_SWITCH_1];
    rx0_switch_2_reg   <= ram_rx0_dob[RX_SWITCH_2];
    rx0_switch_3_reg   <= ram_rx0_dob[RX_SWITCH_3_MSB : RX_SWITCH_3];
    rx0_switch_4_reg   <= ram_rx0_dob[RX_SWITCH_4];
    rx0_switch_5_reg   <= ram_rx0_dob[RX_SWITCH_5_MSB : RX_SWITCH_5];
    rx0_switch_6_reg   <= ram_rx0_dob[RX_SWITCH_6_MSB : RX_SWITCH_6];
    rx0_switch_7_8_reg <= ram_rx0_dob[RX_SWITCH_7_8];
    rx0_switch_9_reg   <= ram_rx0_dob[RX_SWITCH_9];
    rx0_switch_10_reg  <= ram_rx0_dob[RX_SWITCH_10];
    rx0_switch_11_reg  <= ram_rx0_dob[RX_SWITCH_11_MSB: RX_SWITCH_11];

    rx1_switch_1_reg   <= ram_rx1_dob[RX_SWITCH_1_MSB : RX_SWITCH_1];
    rx1_switch_2_reg   <= ram_rx1_dob[RX_SWITCH_2];
    rx1_switch_3_reg   <= ram_rx1_dob[RX_SWITCH_3_MSB : RX_SWITCH_3];
    rx1_switch_4_reg   <= ram_rx1_dob[RX_SWITCH_4];
    rx1_switch_5_reg   <= ram_rx1_dob[RX_SWITCH_5_MSB : RX_SWITCH_5];
    rx1_switch_6_reg   <= ram_rx1_dob[RX_SWITCH_6_MSB : RX_SWITCH_6];
    rx1_switch_7_8_reg <= ram_rx1_dob[RX_SWITCH_7_8];
    rx1_switch_9_reg   <= ram_rx1_dob[RX_SWITCH_9];
    rx1_switch_10_reg  <= ram_rx1_dob[RX_SWITCH_10];
    rx1_switch_11_reg  <= ram_rx1_dob[RX_SWITCH_11_MSB: RX_SWITCH_11];
  end

  ram_2port #(
    .DWIDTH     (32),
    .AWIDTH     (8),
    .RW_MODE    ("READ-FIRST"),
    .RAM_TYPE   ("AUTOMATIC"),
    .OUT_REG    (0),
    .INIT_FILE  ("register_endpoints/memory_init_files/tx0_path_defaults.hex")
  ) ram_tx0_i (
    .clka   (ctrlport_clk),
    .ena    (1'b1),
    .wea    (ram_tx0_wea),
    .addra  (ram_addr),
    .dia    (ram_datain),
    .doa    (ram_tx0_doa),
    .clkb   (ctrlport_clk),
    .enb    (1'b1),
    .web    (1'b0),
    .addrb  (atr_config_rf0),
    .dib    (0),
    .dob    (ram_tx0_dob));

  ram_2port #(
    .DWIDTH     (32),
    .AWIDTH     (8),
    .RW_MODE    ("READ-FIRST"),
    .RAM_TYPE   ("AUTOMATIC"),
    .OUT_REG    (0),
    .INIT_FILE  ("register_endpoints/memory_init_files/tx1_path_defaults.hex")
  ) ram_tx1_i (
    .clka   (ctrlport_clk),
    .ena    (1'b1),
    .wea    (ram_tx1_wea),
    .addra  (ram_addr),
    .dia    (ram_datain),
    .doa    (ram_tx1_doa),
    .clkb   (ctrlport_clk),
    .enb    (1'b1),
    .web    (1'b0),
    .addrb  (atr_config_rf1),
    .dib    (0),
    .dob    (ram_tx1_dob));

  ram_2port #(
    .DWIDTH     (32),
    .AWIDTH     (8),
    .RW_MODE    ("READ-FIRST"),
    .RAM_TYPE   ("AUTOMATIC"),
    .OUT_REG    (0),
    .INIT_FILE  ("register_endpoints/memory_init_files/rx0_path_defaults.hex")
  ) ram_rx0_i (
    .clka   (ctrlport_clk),
    .ena    (1'b1),
    .wea    (ram_rx0_wea),
    .addra  (ram_addr),
    .dia    (ram_datain),
    .doa    (ram_rx0_doa),
    .clkb   (ctrlport_clk),
    .enb    (1'b1),
    .web    (1'b0),
    .addrb  (atr_config_rf0),
    .dib    (0),
    .dob    (ram_rx0_dob));

  ram_2port #(
    .DWIDTH     (32),
    .AWIDTH     (8),
    .RW_MODE    ("READ-FIRST"),
    .RAM_TYPE   ("AUTOMATIC"),
    .OUT_REG    (0),
    .INIT_FILE  ("register_endpoints/memory_init_files/rx1_path_defaults.hex")
  ) ram_rx1_i (
    .clka   (ctrlport_clk),
    .ena    (1'b1),
    .wea    (ram_rx1_wea),
    .addra  (ram_addr),
    .dia    (ram_datain),
    .doa    (ram_rx1_doa),
    .clkb   (ctrlport_clk),
    .enb    (1'b1),
    .web    (1'b0),
    .addrb  (atr_config_rf1),
    .dib    (0),
    .dob    (ram_rx1_dob));

  assign tx0_sw1_sw2_ctrl = tx0_switch_1_2_reg;
  assign tx0_sw3_a        = tx0_switch_3_reg[0];
  assign tx0_sw3_b        = tx0_switch_3_reg[1];
  assign tx0_sw4_a        = tx0_switch_4_reg[0];
  assign tx0_sw4_b        = tx0_switch_4_reg[1];
  assign tx0_sw5_a        = tx0_switch_5_reg[0];
  assign tx0_sw5_b        = tx0_switch_5_reg[1];
  assign tx0_sw6_a        = tx0_switch_6_reg[0];
  assign tx0_sw6_b        = tx0_switch_6_reg[1];
  assign tx0_sw7_a        = tx0_switch_7_reg[0];
  assign tx0_sw7_b        = tx0_switch_7_reg[1];
  assign tx0_sw8_v1       = tx0_switch_8_reg[0];
  assign tx0_sw8_v2       = tx0_switch_8_reg[1];
  assign tx0_sw8_v3       = tx0_switch_8_reg[2];
  assign tx0_sw9_a        = tx0_switch_9_reg[0];
  assign tx0_sw9_b        = tx0_switch_9_reg[1];
  assign tx0_sw10_a       = tx0_switch_10_reg[0];
  assign tx0_sw10_b       = tx0_switch_10_reg[1];
  assign tx0_sw11_a       = tx0_switch_11_reg[0];
  assign tx0_sw11_b       = tx0_switch_11_reg[1];
  assign tx0_sw13_v1      = tx0_switch_13_reg;
  assign tx0_sw14_v1      = tx0_switch_14_reg;

  assign tx1_sw1_sw2_ctrl = tx1_switch_1_2_reg;
  assign tx1_sw3_a        = tx1_switch_3_reg[0];
  assign tx1_sw3_b        = tx1_switch_3_reg[1];
  assign tx1_sw4_a        = tx1_switch_4_reg[0];
  assign tx1_sw4_b        = tx1_switch_4_reg[1];
  assign tx1_sw5_a        = tx1_switch_5_reg[0];
  assign tx1_sw5_b        = tx1_switch_5_reg[1];
  assign tx1_sw6_a        = tx1_switch_6_reg[0];
  assign tx1_sw6_b        = tx1_switch_6_reg[1];
  assign tx1_sw7_a        = tx1_switch_7_reg[0];
  assign tx1_sw7_b        = tx1_switch_7_reg[1];
  assign tx1_sw8_v1       = tx1_switch_8_reg[0];
  assign tx1_sw8_v2       = tx1_switch_8_reg[1];
  assign tx1_sw8_v3       = tx1_switch_8_reg[2];
  assign tx1_sw9_a        = tx1_switch_9_reg[0];
  assign tx1_sw9_b        = tx1_switch_9_reg[1];
  assign tx1_sw10_a       = tx1_switch_10_reg[0];
  assign tx1_sw10_b       = tx1_switch_10_reg[1];
  assign tx1_sw11_a       = tx1_switch_11_reg[0];
  assign tx1_sw11_b       = tx1_switch_11_reg[1];
  assign tx1_sw13_v1      = tx1_switch_13_reg;
  assign tx1_sw14_v1      = tx1_switch_14_reg;

  assign rx0_sw1_a        = rx0_switch_1_reg[0];
  assign rx0_sw1_b        = rx0_switch_1_reg[1];
  assign rx0_sw2_a        = rx0_switch_2_reg;
  assign rx0_sw3_v1       = rx0_switch_3_reg[0];
  assign rx0_sw3_v2       = rx0_switch_3_reg[1];
  assign rx0_sw3_v3       = rx0_switch_3_reg[2];
  assign rx0_sw4_a        = rx0_switch_4_reg;
  assign rx0_sw5_a        = rx0_switch_5_reg[0];
  assign rx0_sw5_b        = rx0_switch_5_reg[1];
  assign rx0_sw6_a        = rx0_switch_6_reg[0];
  assign rx0_sw6_b        = rx0_switch_6_reg[1];
  assign rx0_sw7_sw8_ctrl = rx0_switch_7_8_reg;
  assign rx0_sw9_v1       = rx0_switch_9_reg;
  assign rx0_sw10_v1      = rx0_switch_10_reg;
  assign rx0_sw11_v1      = rx0_switch_11_reg[0];
  assign rx0_sw11_v2      = rx0_switch_11_reg[1];
  assign rx0_sw11_v3      = rx0_switch_11_reg[2];

  assign rx1_sw1_a        = rx1_switch_1_reg[0];
  assign rx1_sw1_b        = rx1_switch_1_reg[1];
  assign rx1_sw2_a        = rx1_switch_2_reg;
  assign rx1_sw3_v1       = rx1_switch_3_reg[0];
  assign rx1_sw3_v2       = rx1_switch_3_reg[1];
  assign rx1_sw3_v3       = rx1_switch_3_reg[2];
  assign rx1_sw4_a        = rx1_switch_4_reg;
  assign rx1_sw5_a        = rx1_switch_5_reg[0];
  assign rx1_sw5_b        = rx1_switch_5_reg[1];
  assign rx1_sw6_a        = rx1_switch_6_reg[0];
  assign rx1_sw6_b        = rx1_switch_6_reg[1];
  assign rx1_sw7_sw8_ctrl = rx1_switch_7_8_reg;
  assign rx1_sw9_v1       = rx1_switch_9_reg;
  assign rx1_sw10_v1      = rx1_switch_10_reg;
  assign rx1_sw11_v1      = rx1_switch_11_reg[0];
  assign rx1_sw11_v2      = rx1_switch_11_reg[1];
  assign rx1_sw11_v3      = rx1_switch_11_reg[2];

endmodule