data/full_repos/permissive/493019833/test/testcase/firrtl/SmallOdds5.lo/reference/SmallOdds5.lo.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/SmallOdds5.lo/reference/SmallOdds5.lo.v:167: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 4 bits.\n                                                                                                                     : ... In instance SmallOdds5.smalls.u_pad_1\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/SmallOdds5.lo/reference/SmallOdds5.lo.v:167: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                                     : ... In instance SmallOdds5.odds.u_pad_34\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n%Error: Exiting due to 2 warning(s)\n'
module SmallOdds5Filter_1(
    input clock,
    input reset,
    output io_in_ready,
    input io_in_valid,
    input [31:0] io_in_bits,
    input io_out_ready,
    output io_out_valid,
    output [31:0] io_out_bits
);
    wire _valid__q;
    wire _valid__d;
    DFF_POSCLK #(.width(1)) valid (
        .q(_valid__q),
        .d(_valid__d),
        .clk(clock)
    );
    wire [31:0] _result__q;
    wire [31:0] _result__d;
    DFF_POSCLK #(.width(32)) result (
        .q(_result__q),
        .d(_result__d),
        .clk(clock)
    );
    wire [31:0] _T_17;
    wire [31:0] _WTEMP_1;
    PAD_UNSIGNED #(.width(1), .n(32)) u_pad_34 (
        .y(_WTEMP_1),
        .in(1'h1)
    );
    BITWISEAND #(.width(32)) bitwiseand_35 (
        .y(_T_17),
        .a(io_in_bits),
        .b(_WTEMP_1)
    );
    wire _T_19;
    wire [31:0] _WTEMP_2;
    PAD_UNSIGNED #(.width(1), .n(32)) u_pad_36 (
        .y(_WTEMP_2),
        .in(1'h1)
    );
    EQ_UNSIGNED #(.width(32)) u_eq_37 (
        .y(_T_19),
        .a(_T_17),
        .b(_WTEMP_2)
    );
    wire _T_20;
    BITWISEAND #(.width(1)) bitwiseand_38 (
        .y(_T_20),
        .a(io_in_valid),
        .b(_T_19)
    );
    wire [31:0] _GEN_0;
    MUX_UNSIGNED #(.width(32)) u_mux_39 (
        .y(_GEN_0),
        .sel(_T_20),
        .a(io_in_bits),
        .b(_result__q)
    );
    wire _GEN_1;
    MUX_UNSIGNED #(.width(1)) u_mux_40 (
        .y(_GEN_1),
        .sel(_T_20),
        .a(1'h1),
        .b(1'h0)
    );
    wire _T_23;
    BITWISEAND #(.width(1)) bitwiseand_41 (
        .y(_T_23),
        .a(io_out_ready),
        .b(_valid__q)
    );
    assign io_in_ready = io_out_ready;
    assign io_out_bits = _result__q;
    assign io_out_valid = _T_23;
    assign _result__d = _GEN_0;
    assign _valid__d = _GEN_1;
endmodule
module SmallOdds5Filter_1(
    input clock,
    input reset,
    output io_in_ready,
    input io_in_valid,
    input [31:0] io_in_bits,
    input io_out_ready,
    output io_out_valid,
    output [31:0] io_out_bits
);

    wire _valid__q;
    wire _valid__d;
    DFF_POSCLK #(.width(1)) valid (
        .q(_valid__q),
        .d(_valid__d),
        .clk(clock)
    );
    wire [31:0] _result__q;
    wire [31:0] _result__d;
    DFF_POSCLK #(.width(32)) result (
        .q(_result__q),
        .d(_result__d),
        .clk(clock)
    );
    wire [31:0] _T_17;
    wire [31:0] _WTEMP_1;
    PAD_UNSIGNED #(.width(1), .n(32)) u_pad_34 (
        .y(_WTEMP_1),
        .in(1'h1)
    );
    BITWISEAND #(.width(32)) bitwiseand_35 (
        .y(_T_17),
        .a(io_in_bits),
        .b(_WTEMP_1)
    );
    wire _T_19;
    wire [31:0] _WTEMP_2;
    PAD_UNSIGNED #(.width(1), .n(32)) u_pad_36 (
        .y(_WTEMP_2),
        .in(1'h1)
    );
    EQ_UNSIGNED #(.width(32)) u_eq_37 (
        .y(_T_19),
        .a(_T_17),
        .b(_WTEMP_2)
    );
    wire _T_20;
    BITWISEAND #(.width(1)) bitwiseand_38 (
        .y(_T_20),
        .a(io_in_valid),
        .b(_T_19)
    );
    wire [31:0] _GEN_0;
    MUX_UNSIGNED #(.width(32)) u_mux_39 (
        .y(_GEN_0),
        .sel(_T_20),
        .a(io_in_bits),
        .b(_result__q)
    );
    wire _GEN_1;
    MUX_UNSIGNED #(.width(1)) u_mux_40 (
        .y(_GEN_1),
        .sel(_T_20),
        .a(1'h1),
        .b(1'h0)
    );
    wire _T_23;
    BITWISEAND #(.width(1)) bitwiseand_41 (
        .y(_T_23),
        .a(io_out_ready),
        .b(_valid__q)
    );
    assign io_in_ready = io_out_ready;
    assign io_out_bits = _result__q;
    assign io_out_valid = _T_23;
    assign _result__d = _GEN_0;
    assign _valid__d = _GEN_1;
endmodule