data/full_repos/permissive/431474762/IF.v
1: b'%Error: data/full_repos/permissive/431474762/IF.v:1: Cannot find include file: lib/defines.vh\n`include "lib/defines.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/431474762,data/full_repos/permissive/431474762/lib/defines.vh\n             data/full_repos/permissive/431474762,data/full_repos/permissive/431474762/lib/defines.vh.v\n             data/full_repos/permissive/431474762,data/full_repos/permissive/431474762/lib/defines.vh.sv\n             lib/defines.vh\n             lib/defines.vh.v\n             lib/defines.vh.sv\n             obj_dir/lib/defines.vh\n             obj_dir/lib/defines.vh.v\n             obj_dir/lib/defines.vh.sv\n%Error: data/full_repos/permissive/431474762/IF.v:5: Define or directive not defined: \'`StallBus\'\n    input wire [`StallBus-1:0] stall,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/431474762/IF.v:10: Define or directive not defined: \'`BR_WD\'\n    input wire [`BR_WD-1:0] br_bus, \n                ^~~~~~\n%Error: data/full_repos/permissive/431474762/IF.v:11: Define or directive not defined: \'`IF_TO_ID_WD\'\n    output wire [`IF_TO_ID_WD-1:0] if_to_id_bus,\n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/431474762/IF.v:33: Define or directive not defined: \'`NoStop\'\n        else if (stall[0]==`NoStop) begin\n                           ^~~~~~~\n%Error: data/full_repos/permissive/431474762/IF.v:33: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        else if (stall[0]==`NoStop) begin\n                                  ^\n%Error: data/full_repos/permissive/431474762/IF.v:42: Define or directive not defined: \'`NoStop\'\n        else if (stall[0]==`NoStop) begin\n                           ^~~~~~~\n%Error: Exiting due to 7 error(s)\n'
module IF(
    input wire clk,
    input wire rst,
    input wire [`StallBus-1:0] stall,




    input wire [`BR_WD-1:0] br_bus,
    output wire [`IF_TO_ID_WD-1:0] if_to_id_bus,
    output wire inst_sram_en,
    output wire [3:0] inst_sram_wen,
    output wire [31:0] inst_sram_addr,
    output wire [31:0] inst_sram_wdata
);
    reg [31:0] pc_reg;
    reg ce_reg;
    wire [31:0] next_pc;
    wire br_e;
    wire [31:0] br_addr;

    assign {
        br_e,
        br_addr
    } = br_bus;


    always @ (posedge clk) begin
        if (rst) begin
            pc_reg <= 32'hbfbf_fffc;
        end
        else if (stall[0]==`NoStop) begin
            pc_reg <= next_pc;
        end
        
    end
    always @ (posedge clk) begin
        if (rst) begin
            ce_reg <= 1'b0;
        end
        else if (stall[0]==`NoStop) begin
            ce_reg <= 1'b1;
        end
    end


    assign next_pc = br_e ? br_addr 
                   : pc_reg + 32'h4;

    assign inst_sram_en = ce_reg;
    assign inst_sram_wen = 4'b0;
    assign inst_sram_addr = pc_reg;
    assign inst_sram_wdata = 32'b0;
    assign if_to_id_bus = {
        ce_reg,
        pc_reg
    };
endmodule
module IF(
    input wire clk,
    input wire rst,
    input wire [`StallBus-1:0] stall,




    input wire [`BR_WD-1:0] br_bus,
    output wire [`IF_TO_ID_WD-1:0] if_to_id_bus,
    output wire inst_sram_en,
    output wire [3:0] inst_sram_wen,
    output wire [31:0] inst_sram_addr,
    output wire [31:0] inst_sram_wdata
);

    reg [31:0] pc_reg;
    reg ce_reg;
    wire [31:0] next_pc;
    wire br_e;
    wire [31:0] br_addr;

    assign {
        br_e,
        br_addr
    } = br_bus;


    always @ (posedge clk) begin
        if (rst) begin
            pc_reg <= 32'hbfbf_fffc;
        end
        else if (stall[0]==`NoStop) begin
            pc_reg <= next_pc;
        end
        
    end
    always @ (posedge clk) begin
        if (rst) begin
            ce_reg <= 1'b0;
        end
        else if (stall[0]==`NoStop) begin
            ce_reg <= 1'b1;
        end
    end


    assign next_pc = br_e ? br_addr 
                   : pc_reg + 32'h4;

    assign inst_sram_en = ce_reg;
    assign inst_sram_wen = 4'b0;
    assign inst_sram_addr = pc_reg;
    assign inst_sram_wdata = 32'b0;
    assign if_to_id_bus = {
        ce_reg,
        pc_reg
    };
endmodule