data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select.v
1: b'%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select.v:15: Operator LTE expects 5 bits on the RHS, but RHS\'s CONST \'4\'hf\' generates 4 bits.\n                                                                                                                    : ... In instance forloop_select\n           for (sel = 0; sel <= 4\'hf; sel=sel+1\'b1)\n                             ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select.v:16: Bit extraction of var[15:0] requires 4 bit index, not 5 bits.\n                                                                                                                    : ... In instance forloop_select\n             dout[(ctrl*sel)+:SLICE] <= din;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/various/dynamic_part_select/forloop_select.v:16: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'din\' generates 16 bits.\n                                                                                                                    : ... In instance forloop_select\n             dout[(ctrl*sel)+:SLICE] <= din;\n                                     ^~\n%Error: Exiting due to 3 warning(s)\n'
module forloop_select #(parameter WIDTH=16, SELW=4, CTRLW=$clog2(WIDTH), DINW=2**SELW)
   (input wire             clk,
    input wire [CTRLW-1:0] ctrl,
    input wire [DINW-1:0]  din,
    input wire             en,
    output reg [WIDTH-1:0] dout);

   reg [SELW:0]            sel;
   localparam SLICE = WIDTH/(SELW**2);

   always @(posedge clk)
     begin
        if (en) begin
           for (sel = 0; sel <= 4'hf; sel=sel+1'b1)
             dout[(ctrl*sel)+:SLICE] <= din;
        end
     end
endmodule
module forloop_select #(parameter WIDTH=16, SELW=4, CTRLW=$clog2(WIDTH), DINW=2**SELW)
   (input wire             clk,
    input wire [CTRLW-1:0] ctrl,
    input wire [DINW-1:0]  din,
    input wire             en,
    output reg [WIDTH-1:0] dout);


   reg [SELW:0]            sel;
   localparam SLICE = WIDTH/(SELW**2);

   always @(posedge clk)
     begin
        if (en) begin
           for (sel = 0; sel <= 4'hf; sel=sel+1'b1)
             dout[(ctrl*sel)+:SLICE] <= din;
        end
     end
endmodule