data/full_repos/permissive/43264243/channel.v
1: b'%Error: data/full_repos/permissive/43264243/channel.v:23: Cannot find include file: config.h\n`include "config.h" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43264243,data/full_repos/permissive/43264243/config.h\n             data/full_repos/permissive/43264243,data/full_repos/permissive/43264243/config.h.v\n             data/full_repos/permissive/43264243,data/full_repos/permissive/43264243/config.h.sv\n             config.h\n             config.h.v\n             config.h.sv\n             obj_dir/config.h\n             obj_dir/config.h.v\n             obj_dir/config.h.sv\n%Error: data/full_repos/permissive/43264243/channel.v:124: Define or directive not defined: \'`FIFO_DEPTH\'\n wire [`FIFO_DEPTH-1:0] itemsinfifo;\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/43264243/channel.v:165: Define or directive not defined: \'`FIFO_DEPTH\'\n defparam fifo0.DEPTH = `FIFO_DEPTH;\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/43264243/channel.v:165: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n defparam fifo0.DEPTH = `FIFO_DEPTH;\n                                   ^\n%Error: Exiting due to 4 error(s)\n'
module digitalfilter(out, clk, rstn, in);
	output reg out;
	input clk;
	input rstn;
	input in;
	reg [4:0] taps;
	reg result;
	
 
	always @(posedge clk or negedge rstn) begin
		if(rstn == 0) begin
			taps <= 0;
			out <= 0;
		end else begin
			taps[4] <= taps[3];
			taps[3] <= taps[2];
			taps[2] <= taps[1];
			taps[1] <= taps[0];
			taps[0] <= in;
			if(taps[2] & taps[3] & taps[4])
				out <= 1;
			if(~taps[2] & ~taps[3] & ~taps[4])
				out <= 0;
		end
	end
endmodule
module digitalfilter(out, clk, rstn, in);

	output reg out;
	input clk;
	input rstn;
	input in;
	reg [4:0] taps;
	reg result;
	
 
	always @(posedge clk or negedge rstn) begin
		if(rstn == 0) begin
			taps <= 0;
			out <= 0;
		end else begin
			taps[4] <= taps[3];
			taps[3] <= taps[2];
			taps[2] <= taps[1];
			taps[1] <= taps[0];
			taps[0] <= in;
			if(taps[2] & taps[3] & taps[4])
				out <= 1;
			if(~taps[2] & ~taps[3] & ~taps[4])
				out <= 0;
		end
	end
endmodule