data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/a23/a23_execute.v
1: b'%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/a23/a23_execute.v:44: Cannot find include file: a23_config_defines.vh\n`include "a23_config_defines.vh" \n         ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/a23,data/full_repos/permissive/486954482/a23_config_defines.vh\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/a23,data/full_repos/permissive/486954482/a23_config_defines.vh.v\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/a23,data/full_repos/permissive/486954482/a23_config_defines.vh.sv\n             a23_config_defines.vh\n             a23_config_defines.vh.v\n             a23_config_defines.vh.sv\n             obj_dir/a23_config_defines.vh\n             obj_dir/a23_config_defines.vh.v\n             obj_dir/a23_config_defines.vh.sv\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/a23/a23_execute.v:95: Cannot find include file: a23_localparams.vh\n`include "a23_localparams.vh" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/a23/a23_execute.v:96: Cannot find include file: a23_functions.vh\n`include "a23_functions.vh" \n         ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module a23_execute (

input                       i_clk,
input                       i_rst,
input       [31:0]          i_read_data,
input       [4:0]           i_read_data_alignment,

output reg  [31:0]          o_write_data,
output wire [31:0]          o_address,

output      [31:0]          o_address_nxt,

output reg                  o_write_enable,
output reg  [3:0]           o_byte_enable,

output                      o_multiply_done,





input      [31:0]           i_imm32,
input      [4:0]            i_imm_shift_amount,
input      [3:0]            i_condition,
input                       i_use_carry_in,

input      [3:0]            i_rm_sel,
input      [3:0]            i_rds_sel,
input      [3:0]            i_rn_sel,
input      [3:0]            i_rm_sel_nxt,
input      [3:0]            i_rds_sel_nxt,
input      [3:0]            i_rn_sel_nxt,
input      [1:0]            i_barrel_shift_amount_sel,
input      [1:0]            i_barrel_shift_data_sel,
input      [1:0]            i_barrel_shift_function,
input      [8:0]            i_alu_function,
input      [1:0]            i_multiply_function,
input      [3:0]            i_address_sel,
input      [1:0]            i_pc_sel,
input      [1:0]            i_byte_enable_sel,
input      [2:0]            i_status_bits_sel,
input      [2:0]            i_reg_write_sel,
input                       i_write_data_wen,

input                       i_pc_wen,
input      [14:0]           i_reg_bank_wen,
input                       i_status_bits_flags_wen
);

`include "a23_localparams.vh"
`include "a23_functions.vh"




wire [31:0]         write_data_nxt;
wire [3:0]          byte_enable_nxt;
wire [31:0]         pc_plus4;
wire [31:0]         pc_minus4;
wire [31:0]         address_plus4;
wire [31:0]         alu_plus4;
wire [31:0]         rn_plus4;
wire [31:0]         alu_out;
wire [3:0]          alu_flags;
wire [31:0]         rm;
wire [31:0]         rs;
wire [31:0]         rd;
wire [31:0]         rn;
wire [31:0]         pc;
wire [31:0]         pc_nxt;
wire [31:0]         branch_pc_nxt;
wire                write_enable_nxt;
wire [7:0]          shift_amount;
wire [31:0]         barrel_shift_in;
wire [31:0]         barrel_shift_out;
wire                barrel_shift_carry;
wire                barrel_shift_carry_alu;

wire [3:0]          status_bits_flags_nxt;
reg  [3:0]          status_bits_flags;

wire                execute;
wire [31:0]         reg_write_nxt;
wire                pc_wen;
wire [14:0]         reg_bank_wen;
wire [3:0]          reg_bank_wsel;
wire [31:0]         multiply_out;
wire [1:0]          multiply_flags;

wire                address_update;
wire                write_data_update;
wire                byte_enable_update;
wire                write_enable_update;
wire                status_bits_flags_update;

wire [31:0]         alu_out_pc_filtered;
wire [31:0]         branch_address_nxt;

wire                carry_in;

reg  [31:0]         address_r;





assign status_bits_flags_nxt     = i_status_bits_sel == 3'd0 ? alu_flags                           :
                                   i_status_bits_sel == 3'd1 ? alu_out          [31:28]            :


                                   i_status_bits_sel == 3'd4 ? { multiply_flags, status_bits_flags[1:0] } :

                                   i_status_bits_sel == 3'd5 ? { alu_flags[3:1], status_bits_flags[0] } :
                                                               4'b1111 ;




assign pc_plus4      = pc        + 32'd4;
assign pc_minus4     = pc        - 32'd4;
assign address_plus4 = address_r + 32'd4;
assign alu_plus4     = alu_out   + 32'd4;
assign rn_plus4      = rn        + 32'd4;






assign shift_amount = i_barrel_shift_amount_sel == 2'd0 ? 8'd0                           :
                      i_barrel_shift_amount_sel == 2'd1 ? rs[7:0]                        :
                      i_barrel_shift_amount_sel == 2'd2 ? {3'd0, i_imm_shift_amount    } :
                                                          {3'd0, i_read_data_alignment } ;




assign barrel_shift_in = i_barrel_shift_data_sel == 2'd0 ? i_imm32       :
                         i_barrel_shift_data_sel == 2'd1 ? i_read_data   :
                                                           rm            ;
                            






assign alu_out_pc_filtered = pc_wen && i_pc_sel == 2'd1 ? pcf(alu_out) : alu_out;


assign branch_address_nxt = (!execute) ? pc_minus4 : alu_out_pc_filtered;



assign o_address_nxt = (i_address_sel == 4'd0) ? pc_plus4              :
                       (i_address_sel == 4'd1) ? alu_out_pc_filtered   :
                       (i_address_sel == 4'd3) ? pc                    :
                       (i_address_sel == 4'd4) ? rn                    :
                       (i_address_sel == 4'd5) ? address_plus4         :
                       (i_address_sel == 4'd6) ? alu_plus4             :
                       (i_address_sel == 4'd7) ? rn_plus4              :
                                                 branch_address_nxt    ;





assign branch_pc_nxt = (!execute) ? pc_minus4 : alu_out;



assign pc_nxt = i_pc_sel == 2'd0 ? pc_plus4              :
                i_pc_sel == 2'd1 ? alu_out               :
                                   branch_pc_nxt         ;





wire [31:0] save_int_pc_m4;

assign save_int_pc_m4 = { status_bits_flags, 
                          1'b1, 
                          1'b1, 
                          pc_minus4[25:2], 
                          2'b0      };

assign reg_write_nxt = i_reg_write_sel == 3'd0 ? alu_out               :

                       i_reg_write_sel == 3'd1 ? save_int_pc_m4        :
                                                 multiply_out          ;  





assign byte_enable_nxt = i_byte_enable_sel == 2'd0  ? 4'b1111 :
                         i_byte_enable_sel == 2'd2  ?
                         ( o_address_nxt[1] == 1'd0 ? 4'b0011 : 
                                                      4'b1100  ) :
                           
                         o_address_nxt[1:0] == 2'd0 ? 4'b0001 :
                         o_address_nxt[1:0] == 2'd1 ? 4'b0010 :
                         o_address_nxt[1:0] == 2'd2 ? 4'b0100 :
                                                      4'b1000 ;





assign write_data_nxt = i_byte_enable_sel == 2'd0 ? rd            :
                                                    {4{rd[ 7:0]}} ;





assign execute = conditional_execute ( i_condition, status_bits_flags );
            


assign pc_wen       = i_pc_wen ;


assign reg_bank_wen = {{15{execute}} & i_reg_bank_wen};





assign write_enable_nxt = execute && i_write_data_wen;






assign status_bits_flags_update        = execute && i_status_bits_flags_wen;

always @( posedge i_clk or posedge i_rst)
    if(i_rst) begin
      o_write_enable          <= 'd0;
      o_write_data            <= 'd0;
      address_r               <= 'd0;
      o_byte_enable           <= 'd0;
      status_bits_flags       <= 'd0;
    end else begin
      o_write_enable          <= write_enable_nxt;
      o_write_data            <= write_data_nxt; 
      address_r               <= o_address_nxt;
      o_byte_enable           <= byte_enable_nxt;
      status_bits_flags       <= status_bits_flags_update       ? status_bits_flags_nxt        : status_bits_flags;
    end

assign o_address = address_r;






assign carry_in = i_use_carry_in ? status_bits_flags[1] : 1'd0;

a23_barrel_shift u_barrel_shift  (
    .i_in             ( barrel_shift_in           ),
    .i_carry_in       ( carry_in                  ),
    .i_shift_amount   ( shift_amount              ),
    .i_function       ( i_barrel_shift_function   ),
    .o_out            ( barrel_shift_out          ),
    .o_carry_out      ( barrel_shift_carry        )
    );






assign barrel_shift_carry_alu =  i_barrel_shift_data_sel == 2'd0 ? 
                                  (i_imm_shift_amount[4:1] == 0 ? status_bits_flags[1] : i_imm32[31]) : 
                                   barrel_shift_carry;

a23_alu u_alu (
    .i_a_in                  ( rn                      ),
    .i_b_in                  ( barrel_shift_out        ),
    .i_barrel_shift_carry    ( barrel_shift_carry_alu  ),
    .i_status_bits_carry     ( status_bits_flags[1]    ),
    .i_function              ( i_alu_function          ),
    .o_out                   ( alu_out                 ),
    .o_flags                 ( alu_flags               )
    );




a23_multiply u_multiply (
    .i_clk          ( i_clk                 ),
    .i_rst          ( i_rst                 ),
    .i_a_in         ( rs                    ),
    .i_b_in         ( rm                    ),
    .i_function     ( i_multiply_function   ),
    .i_execute      ( execute               ),
    .o_out          ( multiply_out          ),
    .o_flags        ( multiply_flags        ),
    .o_done         ( o_multiply_done       )
    );





a23_register_bank u_register_bank(
    .i_clk                   ( i_clk                     ),
    .i_rst                   ( i_rst                     ),
    .i_rm_sel                ( i_rm_sel                  ),
    .i_rds_sel               ( i_rds_sel                 ),
    .i_rn_sel                ( i_rn_sel                  ),
    .i_pc_wen                ( pc_wen                    ),
    .i_reg_bank_wen          ( reg_bank_wen              ),
    .i_pc                    ( pc_nxt[25:2]              ),
    .i_reg                   ( reg_write_nxt             ),
    .i_status_bits_flags     ( status_bits_flags         ),
    .o_rm                    ( rm                        ),
    .o_rs                    ( rs                        ),
    .o_rd                    ( rd                        ),
    .o_rn                    ( rn                        ),
    .o_pc                    ( pc                        )
    );

endmodule
module a23_execute (

input                       i_clk,
input                       i_rst,
input       [31:0]          i_read_data,
input       [4:0]           i_read_data_alignment,

output reg  [31:0]          o_write_data,
output wire [31:0]          o_address,

output      [31:0]          o_address_nxt,

output reg                  o_write_enable,
output reg  [3:0]           o_byte_enable,

output                      o_multiply_done,





input      [31:0]           i_imm32,
input      [4:0]            i_imm_shift_amount,
input      [3:0]            i_condition,
input                       i_use_carry_in,

input      [3:0]            i_rm_sel,
input      [3:0]            i_rds_sel,
input      [3:0]            i_rn_sel,
input      [3:0]            i_rm_sel_nxt,
input      [3:0]            i_rds_sel_nxt,
input      [3:0]            i_rn_sel_nxt,
input      [1:0]            i_barrel_shift_amount_sel,
input      [1:0]            i_barrel_shift_data_sel,
input      [1:0]            i_barrel_shift_function,
input      [8:0]            i_alu_function,
input      [1:0]            i_multiply_function,
input      [3:0]            i_address_sel,
input      [1:0]            i_pc_sel,
input      [1:0]            i_byte_enable_sel,
input      [2:0]            i_status_bits_sel,
input      [2:0]            i_reg_write_sel,
input                       i_write_data_wen,

input                       i_pc_wen,
input      [14:0]           i_reg_bank_wen,
input                       i_status_bits_flags_wen
);


`include "a23_localparams.vh"
`include "a23_functions.vh"




wire [31:0]         write_data_nxt;
wire [3:0]          byte_enable_nxt;
wire [31:0]         pc_plus4;
wire [31:0]         pc_minus4;
wire [31:0]         address_plus4;
wire [31:0]         alu_plus4;
wire [31:0]         rn_plus4;
wire [31:0]         alu_out;
wire [3:0]          alu_flags;
wire [31:0]         rm;
wire [31:0]         rs;
wire [31:0]         rd;
wire [31:0]         rn;
wire [31:0]         pc;
wire [31:0]         pc_nxt;
wire [31:0]         branch_pc_nxt;
wire                write_enable_nxt;
wire [7:0]          shift_amount;
wire [31:0]         barrel_shift_in;
wire [31:0]         barrel_shift_out;
wire                barrel_shift_carry;
wire                barrel_shift_carry_alu;

wire [3:0]          status_bits_flags_nxt;
reg  [3:0]          status_bits_flags;

wire                execute;
wire [31:0]         reg_write_nxt;
wire                pc_wen;
wire [14:0]         reg_bank_wen;
wire [3:0]          reg_bank_wsel;
wire [31:0]         multiply_out;
wire [1:0]          multiply_flags;

wire                address_update;
wire                write_data_update;
wire                byte_enable_update;
wire                write_enable_update;
wire                status_bits_flags_update;

wire [31:0]         alu_out_pc_filtered;
wire [31:0]         branch_address_nxt;

wire                carry_in;

reg  [31:0]         address_r;





assign status_bits_flags_nxt     = i_status_bits_sel == 3'd0 ? alu_flags                           :
                                   i_status_bits_sel == 3'd1 ? alu_out          [31:28]            :


                                   i_status_bits_sel == 3'd4 ? { multiply_flags, status_bits_flags[1:0] } :

                                   i_status_bits_sel == 3'd5 ? { alu_flags[3:1], status_bits_flags[0] } :
                                                               4'b1111 ;




assign pc_plus4      = pc        + 32'd4;
assign pc_minus4     = pc        - 32'd4;
assign address_plus4 = address_r + 32'd4;
assign alu_plus4     = alu_out   + 32'd4;
assign rn_plus4      = rn        + 32'd4;






assign shift_amount = i_barrel_shift_amount_sel == 2'd0 ? 8'd0                           :
                      i_barrel_shift_amount_sel == 2'd1 ? rs[7:0]                        :
                      i_barrel_shift_amount_sel == 2'd2 ? {3'd0, i_imm_shift_amount    } :
                                                          {3'd0, i_read_data_alignment } ;




assign barrel_shift_in = i_barrel_shift_data_sel == 2'd0 ? i_imm32       :
                         i_barrel_shift_data_sel == 2'd1 ? i_read_data   :
                                                           rm            ;
                            






assign alu_out_pc_filtered = pc_wen && i_pc_sel == 2'd1 ? pcf(alu_out) : alu_out;


assign branch_address_nxt = (!execute) ? pc_minus4 : alu_out_pc_filtered;



assign o_address_nxt = (i_address_sel == 4'd0) ? pc_plus4              :
                       (i_address_sel == 4'd1) ? alu_out_pc_filtered   :
                       (i_address_sel == 4'd3) ? pc                    :
                       (i_address_sel == 4'd4) ? rn                    :
                       (i_address_sel == 4'd5) ? address_plus4         :
                       (i_address_sel == 4'd6) ? alu_plus4             :
                       (i_address_sel == 4'd7) ? rn_plus4              :
                                                 branch_address_nxt    ;





assign branch_pc_nxt = (!execute) ? pc_minus4 : alu_out;



assign pc_nxt = i_pc_sel == 2'd0 ? pc_plus4              :
                i_pc_sel == 2'd1 ? alu_out               :
                                   branch_pc_nxt         ;





wire [31:0] save_int_pc_m4;

assign save_int_pc_m4 = { status_bits_flags, 
                          1'b1, 
                          1'b1, 
                          pc_minus4[25:2], 
                          2'b0      };

assign reg_write_nxt = i_reg_write_sel == 3'd0 ? alu_out               :

                       i_reg_write_sel == 3'd1 ? save_int_pc_m4        :
                                                 multiply_out          ;  





assign byte_enable_nxt = i_byte_enable_sel == 2'd0  ? 4'b1111 :
                         i_byte_enable_sel == 2'd2  ?
                         ( o_address_nxt[1] == 1'd0 ? 4'b0011 : 
                                                      4'b1100  ) :
                           
                         o_address_nxt[1:0] == 2'd0 ? 4'b0001 :
                         o_address_nxt[1:0] == 2'd1 ? 4'b0010 :
                         o_address_nxt[1:0] == 2'd2 ? 4'b0100 :
                                                      4'b1000 ;





assign write_data_nxt = i_byte_enable_sel == 2'd0 ? rd            :
                                                    {4{rd[ 7:0]}} ;





assign execute = conditional_execute ( i_condition, status_bits_flags );
            


assign pc_wen       = i_pc_wen ;


assign reg_bank_wen = {{15{execute}} & i_reg_bank_wen};





assign write_enable_nxt = execute && i_write_data_wen;






assign status_bits_flags_update        = execute && i_status_bits_flags_wen;

always @( posedge i_clk or posedge i_rst)
    if(i_rst) begin
      o_write_enable          <= 'd0;
      o_write_data            <= 'd0;
      address_r               <= 'd0;
      o_byte_enable           <= 'd0;
      status_bits_flags       <= 'd0;
    end else begin
      o_write_enable          <= write_enable_nxt;
      o_write_data            <= write_data_nxt; 
      address_r               <= o_address_nxt;
      o_byte_enable           <= byte_enable_nxt;
      status_bits_flags       <= status_bits_flags_update       ? status_bits_flags_nxt        : status_bits_flags;
    end

assign o_address = address_r;






assign carry_in = i_use_carry_in ? status_bits_flags[1] : 1'd0;

a23_barrel_shift u_barrel_shift  (
    .i_in             ( barrel_shift_in           ),
    .i_carry_in       ( carry_in                  ),
    .i_shift_amount   ( shift_amount              ),
    .i_function       ( i_barrel_shift_function   ),
    .o_out            ( barrel_shift_out          ),
    .o_carry_out      ( barrel_shift_carry        )
    );






assign barrel_shift_carry_alu =  i_barrel_shift_data_sel == 2'd0 ? 
                                  (i_imm_shift_amount[4:1] == 0 ? status_bits_flags[1] : i_imm32[31]) : 
                                   barrel_shift_carry;

a23_alu u_alu (
    .i_a_in                  ( rn                      ),
    .i_b_in                  ( barrel_shift_out        ),
    .i_barrel_shift_carry    ( barrel_shift_carry_alu  ),
    .i_status_bits_carry     ( status_bits_flags[1]    ),
    .i_function              ( i_alu_function          ),
    .o_out                   ( alu_out                 ),
    .o_flags                 ( alu_flags               )
    );




a23_multiply u_multiply (
    .i_clk          ( i_clk                 ),
    .i_rst          ( i_rst                 ),
    .i_a_in         ( rs                    ),
    .i_b_in         ( rm                    ),
    .i_function     ( i_multiply_function   ),
    .i_execute      ( execute               ),
    .o_out          ( multiply_out          ),
    .o_flags        ( multiply_flags        ),
    .o_done         ( o_multiply_done       )
    );





a23_register_bank u_register_bank(
    .i_clk                   ( i_clk                     ),
    .i_rst                   ( i_rst                     ),
    .i_rm_sel                ( i_rm_sel                  ),
    .i_rds_sel               ( i_rds_sel                 ),
    .i_rn_sel                ( i_rn_sel                  ),
    .i_pc_wen                ( pc_wen                    ),
    .i_reg_bank_wen          ( reg_bank_wen              ),
    .i_pc                    ( pc_nxt[25:2]              ),
    .i_reg                   ( reg_write_nxt             ),
    .i_status_bits_flags     ( status_bits_flags         ),
    .o_rm                    ( rm                        ),
    .o_rs                    ( rs                        ),
    .o_rd                    ( rd                        ),
    .o_rn                    ( rn                        ),
    .o_pc                    ( pc                        )
    );

endmodule