data/full_repos/permissive/506186384/project-files/lab6/Ctr.v
data/verilator_xmls/e5adff9e-75ef-447b-9694-e2e1e223fb85.xml
module Ctr(
    input [5:0] OpCode,
    output [1:0] RegDst,
    output [1:0] ALUSrc1,
    output [1:0] ALUSrc2,
    output MemToReg, 
    output RegWrite,
    output MemRead,
    output MemWrite,
    output [1:0] Branch,
    output [3:0] ALUOp,

    output Jump,
    output [1:0] MByte
    );
    
    reg [1:0] regDst;
    reg [1:0] aluSrc1;
    reg [1:0] aluSrc2;
    reg memtoReg;
    reg regWrite;
    reg memRead;
    reg memWrite;
    reg [1:0] branch;
    reg [3:0] aluOp;
    reg jump;
    reg [1:0] mbyte;
    
    always @ (OpCode)
    begin
        case(OpCode)
            6'b000000:
            begin
                regDst = 2'b01;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b00;
                memtoReg = 0;
                regWrite = 1;
                memRead = 0;
                memWrite = 0;
                branch = 2'b00;
                aluOp = 4'b0010;
                jump = 0;
                mbyte = 0;
            end
            
            6'b100011:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b01;
                memtoReg = 1;
                regWrite = 1;
                memRead = 1;
                memWrite = 0;
                branch = 2'b00;
                aluOp = 4'b0000;
                jump = 0;
                mbyte = 2'b00;
            end
            
            6'b100100:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b01;
                memtoReg = 1;
                regWrite = 1;
                memRead = 1;
                memWrite = 0;
                branch = 2'b00;
                aluOp = 4'b0000;
                jump = 0;
                mbyte = 2'b10;
            end
            6'b100101:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b01;
                memtoReg = 1;
                regWrite = 1;
                memRead = 1;
                memWrite = 0;
                branch = 2'b00;
                aluOp = 4'b0000;
                jump = 0;
                mbyte = 2'b01;
            end
            
            6'b101011:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b01;
                memtoReg = 0;
                regWrite = 0;
                memRead = 0;
                memWrite = 1;
                branch = 2'b00;
                aluOp = 4'b0000;
                jump = 0;
                mbyte = 0;
            end
            
            6'b101000:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b01;
                memtoReg = 0;
                regWrite = 0;
                memRead = 0;
                memWrite = 1;
                branch = 2'b00;
                aluOp = 4'b0000;
                jump = 0;
                mbyte = 2'b10;
            end
            
            6'b101001:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b01;
                memtoReg = 0;
                regWrite = 0;
                memRead = 0;
                memWrite = 1;
                branch = 2'b00;
                aluOp = 4'b0000;
                jump = 0;
                mbyte = 2'b01;
            end
            
            6'b000100:
            begin
                regDst = 0;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b00;
                memtoReg = 0;
                regWrite = 0;
                memRead = 0;
                memWrite = 0;
                branch = 2'b01;
                aluOp = 4'b0001;
                jump = 0;
                mbyte = 0;
            end
            
            6'b000101:
            begin
                regDst = 0;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b00;
                memtoReg = 0;
                regWrite = 0;
                memRead = 0;
                memWrite = 0;
                branch = 2'b10;
                aluOp = 4'b0001;
                jump = 0;
                mbyte = 0;
            end
            
            6'b000010:
            begin
                regDst = 0;
                aluSrc1 = 0;
                aluSrc2 = 0;
                memtoReg = 0;
                regWrite = 0;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 4'b0000;
                jump = 1;
                mbyte = 0;
            end
            
            6'b001000:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b01;
                memtoReg = 0;
                regWrite = 1;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 4'b0000;
                jump = 0;
                mbyte = 0;
            end
            
            6'b001001:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b01;
                memtoReg = 0;
                regWrite = 1;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 4'b0110;
                jump = 0;
                mbyte = 0;
            end
            
            6'b001100:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b10;
                memtoReg = 0;
                regWrite = 1;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 4'b0011;
                jump = 0;
                mbyte = 0;
            end
            
            6'b001101:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b10;
                memtoReg = 0;
                regWrite = 1;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 4'b0100;
                jump = 0;
                mbyte = 0;
            end
            
            6'b001110:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b10;
                memtoReg = 0;
                regWrite = 1;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 4'b1001;
                jump = 0;
                mbyte = 0;
            end
            
            6'b000011:
            begin
                regDst = 2'b10;
                aluSrc1 = 2'b10;
                aluSrc2 = 2'b11;
                memtoReg = 0;
                regWrite = 1;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 4'b0000;
                jump = 1;
                mbyte = 0;
            end
            
            6'b001010:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b01;
                memtoReg = 0;
                regWrite = 1;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 4'b0101;
                jump = 0;
                mbyte = 0;
            end
            
            6'b001011:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b01;
                memtoReg = 0;
                regWrite = 1;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 4'b0111;
                jump = 0;
                mbyte = 0;
            end
            
            6'b001111:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b01;
                memtoReg = 0;
                regWrite = 1;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 4'b1000;
                jump = 0;
                mbyte = 0;
            end
            
            default:
            begin
                regDst = 0;
                aluSrc1 = 0;
                aluSrc2 = 0;
                memtoReg = 0;
                regWrite = 0;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 0;
                jump = 0;
                mbyte = 0;
            end
        endcase
    end
   
   assign RegDst = regDst;
   assign ALUSrc1 = aluSrc1;
   assign ALUSrc2 = aluSrc2;
   assign MemToReg = memtoReg;
   assign RegWrite = regWrite;
   assign MemRead = memRead;
   assign MemWrite = memWrite;
   assign Branch = branch;
   assign ALUOp = aluOp;
   assign Jump = jump;
   assign MByte = mbyte;
   
endmodule
module Ctr(
    input [5:0] OpCode,
    output [1:0] RegDst,
    output [1:0] ALUSrc1,
    output [1:0] ALUSrc2,
    output MemToReg, 
    output RegWrite,
    output MemRead,
    output MemWrite,
    output [1:0] Branch,
    output [3:0] ALUOp,

    output Jump,
    output [1:0] MByte
    );

    
    reg [1:0] regDst;
    reg [1:0] aluSrc1;
    reg [1:0] aluSrc2;
    reg memtoReg;
    reg regWrite;
    reg memRead;
    reg memWrite;
    reg [1:0] branch;
    reg [3:0] aluOp;
    reg jump;
    reg [1:0] mbyte;
    
    always @ (OpCode)
    begin
        case(OpCode)
            6'b000000:
            begin
                regDst = 2'b01;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b00;
                memtoReg = 0;
                regWrite = 1;
                memRead = 0;
                memWrite = 0;
                branch = 2'b00;
                aluOp = 4'b0010;
                jump = 0;
                mbyte = 0;
            end
            
            6'b100011:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b01;
                memtoReg = 1;
                regWrite = 1;
                memRead = 1;
                memWrite = 0;
                branch = 2'b00;
                aluOp = 4'b0000;
                jump = 0;
                mbyte = 2'b00;
            end
            
            6'b100100:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b01;
                memtoReg = 1;
                regWrite = 1;
                memRead = 1;
                memWrite = 0;
                branch = 2'b00;
                aluOp = 4'b0000;
                jump = 0;
                mbyte = 2'b10;
            end
            6'b100101:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b01;
                memtoReg = 1;
                regWrite = 1;
                memRead = 1;
                memWrite = 0;
                branch = 2'b00;
                aluOp = 4'b0000;
                jump = 0;
                mbyte = 2'b01;
            end
            
            6'b101011:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b01;
                memtoReg = 0;
                regWrite = 0;
                memRead = 0;
                memWrite = 1;
                branch = 2'b00;
                aluOp = 4'b0000;
                jump = 0;
                mbyte = 0;
            end
            
            6'b101000:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b01;
                memtoReg = 0;
                regWrite = 0;
                memRead = 0;
                memWrite = 1;
                branch = 2'b00;
                aluOp = 4'b0000;
                jump = 0;
                mbyte = 2'b10;
            end
            
            6'b101001:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b01;
                memtoReg = 0;
                regWrite = 0;
                memRead = 0;
                memWrite = 1;
                branch = 2'b00;
                aluOp = 4'b0000;
                jump = 0;
                mbyte = 2'b01;
            end
            
            6'b000100:
            begin
                regDst = 0;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b00;
                memtoReg = 0;
                regWrite = 0;
                memRead = 0;
                memWrite = 0;
                branch = 2'b01;
                aluOp = 4'b0001;
                jump = 0;
                mbyte = 0;
            end
            
            6'b000101:
            begin
                regDst = 0;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b00;
                memtoReg = 0;
                regWrite = 0;
                memRead = 0;
                memWrite = 0;
                branch = 2'b10;
                aluOp = 4'b0001;
                jump = 0;
                mbyte = 0;
            end
            
            6'b000010:
            begin
                regDst = 0;
                aluSrc1 = 0;
                aluSrc2 = 0;
                memtoReg = 0;
                regWrite = 0;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 4'b0000;
                jump = 1;
                mbyte = 0;
            end
            
            6'b001000:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b01;
                memtoReg = 0;
                regWrite = 1;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 4'b0000;
                jump = 0;
                mbyte = 0;
            end
            
            6'b001001:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b01;
                memtoReg = 0;
                regWrite = 1;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 4'b0110;
                jump = 0;
                mbyte = 0;
            end
            
            6'b001100:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b10;
                memtoReg = 0;
                regWrite = 1;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 4'b0011;
                jump = 0;
                mbyte = 0;
            end
            
            6'b001101:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b10;
                memtoReg = 0;
                regWrite = 1;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 4'b0100;
                jump = 0;
                mbyte = 0;
            end
            
            6'b001110:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b10;
                memtoReg = 0;
                regWrite = 1;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 4'b1001;
                jump = 0;
                mbyte = 0;
            end
            
            6'b000011:
            begin
                regDst = 2'b10;
                aluSrc1 = 2'b10;
                aluSrc2 = 2'b11;
                memtoReg = 0;
                regWrite = 1;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 4'b0000;
                jump = 1;
                mbyte = 0;
            end
            
            6'b001010:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b01;
                memtoReg = 0;
                regWrite = 1;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 4'b0101;
                jump = 0;
                mbyte = 0;
            end
            
            6'b001011:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b01;
                memtoReg = 0;
                regWrite = 1;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 4'b0111;
                jump = 0;
                mbyte = 0;
            end
            
            6'b001111:
            begin
                regDst = 2'b00;
                aluSrc1 = 2'b00;
                aluSrc2 = 2'b01;
                memtoReg = 0;
                regWrite = 1;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 4'b1000;
                jump = 0;
                mbyte = 0;
            end
            
            default:
            begin
                regDst = 0;
                aluSrc1 = 0;
                aluSrc2 = 0;
                memtoReg = 0;
                regWrite = 0;
                memRead = 0;
                memWrite = 0;
                branch = 0;
                aluOp = 0;
                jump = 0;
                mbyte = 0;
            end
        endcase
    end
   
   assign RegDst = regDst;
   assign ALUSrc1 = aluSrc1;
   assign ALUSrc2 = aluSrc2;
   assign MemToReg = memtoReg;
   assign RegWrite = regWrite;
   assign MemRead = memRead;
   assign MemWrite = memWrite;
   assign Branch = branch;
   assign ALUOp = aluOp;
   assign Jump = jump;
   assign MByte = mbyte;
   
endmodule