data/full_repos/permissive/437632408/NVDLA/nvdla/sdp/NV_NVDLA_SDP_erdma.v
1: b"%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/sdp/NV_NVDLA_SDP_erdma.v:133: Cannot find file containing module: 'NV_NVDLA_SDP_ERDMA_gate'\nNV_NVDLA_SDP_ERDMA_gate u_gate (\n^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/437632408/NVDLA/nvdla/sdp,data/full_repos/permissive/437632408/NV_NVDLA_SDP_ERDMA_gate\n             data/full_repos/permissive/437632408/NVDLA/nvdla/sdp,data/full_repos/permissive/437632408/NV_NVDLA_SDP_ERDMA_gate.v\n             data/full_repos/permissive/437632408/NVDLA/nvdla/sdp,data/full_repos/permissive/437632408/NV_NVDLA_SDP_ERDMA_gate.sv\n             NV_NVDLA_SDP_ERDMA_gate\n             NV_NVDLA_SDP_ERDMA_gate.v\n             NV_NVDLA_SDP_ERDMA_gate.sv\n             obj_dir/NV_NVDLA_SDP_ERDMA_gate\n             obj_dir/NV_NVDLA_SDP_ERDMA_gate.v\n             obj_dir/NV_NVDLA_SDP_ERDMA_gate.sv\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/sdp/NV_NVDLA_SDP_erdma.v:143: Cannot find file containing module: 'NV_NVDLA_SDP_ERDMA_ig'\nNV_NVDLA_SDP_ERDMA_ig u_ig (\n^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/sdp/NV_NVDLA_SDP_erdma.v:173: Cannot find file containing module: 'NV_NVDLA_SDP_ERDMA_cq'\nNV_NVDLA_SDP_ERDMA_cq u_cq (\n^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/sdp/NV_NVDLA_SDP_erdma.v:184: Cannot find file containing module: 'NV_NVDLA_SDP_ERDMA_eg'\nNV_NVDLA_SDP_ERDMA_eg u_eg (\n^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module NV_NVDLA_SDP_erdma (
   nvdla_core_clk
  ,nvdla_core_rstn
  ,cvif2sdp_e_rd_rsp_pd
  ,cvif2sdp_e_rd_rsp_valid
  ,dla_clk_ovr_on_sync
  ,erdma_disable
  ,erdma_slcg_op_en
  ,global_clk_ovr_on_sync
  ,mcif2sdp_e_rd_rsp_pd
  ,mcif2sdp_e_rd_rsp_valid
  ,pwrbus_ram_pd
  ,reg2dp_batch_number
  ,reg2dp_channel
  ,reg2dp_erdma_data_mode
  ,reg2dp_erdma_data_size
  ,reg2dp_erdma_data_use
  ,reg2dp_erdma_ram_type
  ,reg2dp_ew_base_addr_high
  ,reg2dp_ew_base_addr_low
  ,reg2dp_ew_line_stride
  ,reg2dp_ew_surface_stride
  ,reg2dp_height
  ,reg2dp_op_en
  ,reg2dp_out_precision
  ,reg2dp_perf_dma_en
  ,reg2dp_proc_precision
  ,reg2dp_width
  ,reg2dp_winograd
  ,sdp_e2cvif_rd_req_ready
  ,sdp_e2mcif_rd_req_ready
  ,sdp_erdma2dp_alu_ready
  ,sdp_erdma2dp_mul_ready
  ,tmc2slcg_disable_clock_gating
  ,cvif2sdp_e_rd_rsp_ready
  ,dp2reg_done
  ,dp2reg_erdma_stall
  ,mcif2sdp_e_rd_rsp_ready
  ,sdp_e2cvif_rd_cdt_lat_fifo_pop
  ,sdp_e2cvif_rd_req_pd
  ,sdp_e2cvif_rd_req_valid
  ,sdp_e2mcif_rd_cdt_lat_fifo_pop
  ,sdp_e2mcif_rd_req_pd
  ,sdp_e2mcif_rd_req_valid
  ,sdp_erdma2dp_alu_pd
  ,sdp_erdma2dp_alu_valid
  ,sdp_erdma2dp_mul_pd
  ,sdp_erdma2dp_mul_valid
  );



 input nvdla_core_clk;
 input nvdla_core_rstn;
 input cvif2sdp_e_rd_rsp_valid;
 output cvif2sdp_e_rd_rsp_ready;
 input [513:0] cvif2sdp_e_rd_rsp_pd;
 input mcif2sdp_e_rd_rsp_valid;
 output mcif2sdp_e_rd_rsp_ready;
 input [513:0] mcif2sdp_e_rd_rsp_pd;
 input [31:0] pwrbus_ram_pd;
 output sdp_e2cvif_rd_cdt_lat_fifo_pop;
 output sdp_e2cvif_rd_req_valid;
 input sdp_e2cvif_rd_req_ready;
 output [78:0] sdp_e2cvif_rd_req_pd;
 output sdp_e2mcif_rd_cdt_lat_fifo_pop;
 output sdp_e2mcif_rd_req_valid;
 input sdp_e2mcif_rd_req_ready;
 output [78:0] sdp_e2mcif_rd_req_pd;
 output sdp_erdma2dp_alu_valid;
 input sdp_erdma2dp_alu_ready;
 output [256:0] sdp_erdma2dp_alu_pd;
 output sdp_erdma2dp_mul_valid;
 input sdp_erdma2dp_mul_ready;
 output [256:0] sdp_erdma2dp_mul_pd;
 input [4:0] reg2dp_batch_number;
 input [12:0] reg2dp_channel;
 input reg2dp_erdma_data_mode;
 input reg2dp_erdma_data_size;
 input [1:0] reg2dp_erdma_data_use;
 input reg2dp_erdma_ram_type;
 input [31:0] reg2dp_ew_base_addr_high;
 input [26:0] reg2dp_ew_base_addr_low;
 input [26:0] reg2dp_ew_line_stride;
 input [26:0] reg2dp_ew_surface_stride;
 input [12:0] reg2dp_height;
 input reg2dp_op_en;
 input [1:0] reg2dp_out_precision;
 input reg2dp_perf_dma_en;
 input [1:0] reg2dp_proc_precision;
 input [12:0] reg2dp_width;
 input reg2dp_winograd;
 output dp2reg_done;
 output [31:0] dp2reg_erdma_stall;
 input dla_clk_ovr_on_sync;
 input global_clk_ovr_on_sync;
 input tmc2slcg_disable_clock_gating;
 input erdma_slcg_op_en;
 input erdma_disable;
 reg layer_process;
 wire [15:0] cq2eg_pd;
 wire cq2eg_prdy;
 wire cq2eg_pvld;
 wire eg_done;
 wire [15:0] ig2cq_pd;
 wire ig2cq_prdy;
 wire ig2cq_pvld;
 wire nvdla_gated_clk;
 wire op_load;

assign op_load = reg2dp_op_en & !layer_process;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    layer_process <= 1'b0;
  end else begin
    if (op_load) begin
        layer_process <= 1'b1;
    end else if (eg_done) begin
        layer_process <= 1'b0;
    end
  end
end
assign dp2reg_done = eg_done;

NV_NVDLA_SDP_ERDMA_gate u_gate (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync)
  ,.erdma_disable (erdma_disable)
  ,.erdma_slcg_op_en (erdma_slcg_op_en)
  ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync)
  ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating)
  ,.nvdla_gated_clk (nvdla_gated_clk)
  );
NV_NVDLA_SDP_ERDMA_ig u_ig (
   .reg2dp_channel (reg2dp_channel[12:0])
  ,.reg2dp_erdma_data_mode (reg2dp_erdma_data_mode)
  ,.reg2dp_erdma_data_size (reg2dp_erdma_data_size)
  ,.reg2dp_erdma_data_use (reg2dp_erdma_data_use[1:0])
  ,.reg2dp_erdma_ram_type (reg2dp_erdma_ram_type)
  ,.reg2dp_ew_base_addr_high (reg2dp_ew_base_addr_high[31:0])
  ,.reg2dp_ew_base_addr_low (reg2dp_ew_base_addr_low[26:0])
  ,.reg2dp_ew_line_stride (reg2dp_ew_line_stride[26:0])
  ,.reg2dp_ew_surface_stride (reg2dp_ew_surface_stride[26:0])
  ,.reg2dp_height (reg2dp_height[12:0])
  ,.reg2dp_op_en (reg2dp_op_en)
  ,.reg2dp_perf_dma_en (reg2dp_perf_dma_en)
  ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0])
  ,.reg2dp_width (reg2dp_width[12:0])
  ,.reg2dp_winograd (reg2dp_winograd)
  ,.dp2reg_erdma_stall (dp2reg_erdma_stall[31:0])
  ,.op_load (op_load)
  ,.nvdla_core_clk (nvdla_gated_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.sdp_e2mcif_rd_req_valid (sdp_e2mcif_rd_req_valid)
  ,.sdp_e2mcif_rd_req_ready (sdp_e2mcif_rd_req_ready)
  ,.sdp_e2mcif_rd_req_pd (sdp_e2mcif_rd_req_pd[78:0])
  ,.sdp_e2cvif_rd_req_valid (sdp_e2cvif_rd_req_valid)
  ,.sdp_e2cvif_rd_req_ready (sdp_e2cvif_rd_req_ready)
  ,.sdp_e2cvif_rd_req_pd (sdp_e2cvif_rd_req_pd[78:0])
  ,.ig2cq_pvld (ig2cq_pvld)
  ,.ig2cq_prdy (ig2cq_prdy)
  ,.ig2cq_pd (ig2cq_pd[15:0])
  );
NV_NVDLA_SDP_ERDMA_cq u_cq (
   .nvdla_core_clk (nvdla_gated_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.ig2cq_prdy (ig2cq_prdy)
  ,.ig2cq_pvld (ig2cq_pvld)
  ,.ig2cq_pd (ig2cq_pd[15:0])
  ,.cq2eg_prdy (cq2eg_prdy)
  ,.cq2eg_pvld (cq2eg_pvld)
  ,.cq2eg_pd (cq2eg_pd[15:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  );
NV_NVDLA_SDP_ERDMA_eg u_eg (
   .nvdla_core_clk (nvdla_gated_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.mcif2sdp_e_rd_rsp_valid (mcif2sdp_e_rd_rsp_valid)
  ,.mcif2sdp_e_rd_rsp_ready (mcif2sdp_e_rd_rsp_ready)
  ,.mcif2sdp_e_rd_rsp_pd (mcif2sdp_e_rd_rsp_pd[513:0])
  ,.cvif2sdp_e_rd_rsp_valid (cvif2sdp_e_rd_rsp_valid)
  ,.cvif2sdp_e_rd_rsp_ready (cvif2sdp_e_rd_rsp_ready)
  ,.cvif2sdp_e_rd_rsp_pd (cvif2sdp_e_rd_rsp_pd[513:0])
  ,.sdp_e2mcif_rd_cdt_lat_fifo_pop (sdp_e2mcif_rd_cdt_lat_fifo_pop)
  ,.sdp_e2cvif_rd_cdt_lat_fifo_pop (sdp_e2cvif_rd_cdt_lat_fifo_pop)
  ,.cq2eg_pvld (cq2eg_pvld)
  ,.cq2eg_prdy (cq2eg_prdy)
  ,.cq2eg_pd (cq2eg_pd[15:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  ,.sdp_erdma2dp_alu_valid (sdp_erdma2dp_alu_valid)
  ,.sdp_erdma2dp_alu_ready (sdp_erdma2dp_alu_ready)
  ,.sdp_erdma2dp_alu_pd (sdp_erdma2dp_alu_pd[256:0])
  ,.sdp_erdma2dp_mul_valid (sdp_erdma2dp_mul_valid)
  ,.sdp_erdma2dp_mul_ready (sdp_erdma2dp_mul_ready)
  ,.sdp_erdma2dp_mul_pd (sdp_erdma2dp_mul_pd[256:0])
  ,.reg2dp_batch_number (reg2dp_batch_number[4:0])
  ,.reg2dp_channel (reg2dp_channel[12:0])
  ,.reg2dp_erdma_data_mode (reg2dp_erdma_data_mode)
  ,.reg2dp_erdma_data_size (reg2dp_erdma_data_size)
  ,.reg2dp_erdma_data_use (reg2dp_erdma_data_use[1:0])
  ,.reg2dp_erdma_ram_type (reg2dp_erdma_ram_type)
  ,.reg2dp_height (reg2dp_height[12:0])
  ,.reg2dp_out_precision (reg2dp_out_precision[1:0])
  ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0])
  ,.reg2dp_width (reg2dp_width[12:0])
  ,.op_load (op_load)
  ,.eg_done (eg_done)
  );


endmodule
module NV_NVDLA_SDP_erdma (
   nvdla_core_clk
  ,nvdla_core_rstn
  ,cvif2sdp_e_rd_rsp_pd
  ,cvif2sdp_e_rd_rsp_valid
  ,dla_clk_ovr_on_sync
  ,erdma_disable
  ,erdma_slcg_op_en
  ,global_clk_ovr_on_sync
  ,mcif2sdp_e_rd_rsp_pd
  ,mcif2sdp_e_rd_rsp_valid
  ,pwrbus_ram_pd
  ,reg2dp_batch_number
  ,reg2dp_channel
  ,reg2dp_erdma_data_mode
  ,reg2dp_erdma_data_size
  ,reg2dp_erdma_data_use
  ,reg2dp_erdma_ram_type
  ,reg2dp_ew_base_addr_high
  ,reg2dp_ew_base_addr_low
  ,reg2dp_ew_line_stride
  ,reg2dp_ew_surface_stride
  ,reg2dp_height
  ,reg2dp_op_en
  ,reg2dp_out_precision
  ,reg2dp_perf_dma_en
  ,reg2dp_proc_precision
  ,reg2dp_width
  ,reg2dp_winograd
  ,sdp_e2cvif_rd_req_ready
  ,sdp_e2mcif_rd_req_ready
  ,sdp_erdma2dp_alu_ready
  ,sdp_erdma2dp_mul_ready
  ,tmc2slcg_disable_clock_gating
  ,cvif2sdp_e_rd_rsp_ready
  ,dp2reg_done
  ,dp2reg_erdma_stall
  ,mcif2sdp_e_rd_rsp_ready
  ,sdp_e2cvif_rd_cdt_lat_fifo_pop
  ,sdp_e2cvif_rd_req_pd
  ,sdp_e2cvif_rd_req_valid
  ,sdp_e2mcif_rd_cdt_lat_fifo_pop
  ,sdp_e2mcif_rd_req_pd
  ,sdp_e2mcif_rd_req_valid
  ,sdp_erdma2dp_alu_pd
  ,sdp_erdma2dp_alu_valid
  ,sdp_erdma2dp_mul_pd
  ,sdp_erdma2dp_mul_valid
  );




 input nvdla_core_clk;
 input nvdla_core_rstn;
 input cvif2sdp_e_rd_rsp_valid;
 output cvif2sdp_e_rd_rsp_ready;
 input [513:0] cvif2sdp_e_rd_rsp_pd;
 input mcif2sdp_e_rd_rsp_valid;
 output mcif2sdp_e_rd_rsp_ready;
 input [513:0] mcif2sdp_e_rd_rsp_pd;
 input [31:0] pwrbus_ram_pd;
 output sdp_e2cvif_rd_cdt_lat_fifo_pop;
 output sdp_e2cvif_rd_req_valid;
 input sdp_e2cvif_rd_req_ready;
 output [78:0] sdp_e2cvif_rd_req_pd;
 output sdp_e2mcif_rd_cdt_lat_fifo_pop;
 output sdp_e2mcif_rd_req_valid;
 input sdp_e2mcif_rd_req_ready;
 output [78:0] sdp_e2mcif_rd_req_pd;
 output sdp_erdma2dp_alu_valid;
 input sdp_erdma2dp_alu_ready;
 output [256:0] sdp_erdma2dp_alu_pd;
 output sdp_erdma2dp_mul_valid;
 input sdp_erdma2dp_mul_ready;
 output [256:0] sdp_erdma2dp_mul_pd;
 input [4:0] reg2dp_batch_number;
 input [12:0] reg2dp_channel;
 input reg2dp_erdma_data_mode;
 input reg2dp_erdma_data_size;
 input [1:0] reg2dp_erdma_data_use;
 input reg2dp_erdma_ram_type;
 input [31:0] reg2dp_ew_base_addr_high;
 input [26:0] reg2dp_ew_base_addr_low;
 input [26:0] reg2dp_ew_line_stride;
 input [26:0] reg2dp_ew_surface_stride;
 input [12:0] reg2dp_height;
 input reg2dp_op_en;
 input [1:0] reg2dp_out_precision;
 input reg2dp_perf_dma_en;
 input [1:0] reg2dp_proc_precision;
 input [12:0] reg2dp_width;
 input reg2dp_winograd;
 output dp2reg_done;
 output [31:0] dp2reg_erdma_stall;
 input dla_clk_ovr_on_sync;
 input global_clk_ovr_on_sync;
 input tmc2slcg_disable_clock_gating;
 input erdma_slcg_op_en;
 input erdma_disable;
 reg layer_process;
 wire [15:0] cq2eg_pd;
 wire cq2eg_prdy;
 wire cq2eg_pvld;
 wire eg_done;
 wire [15:0] ig2cq_pd;
 wire ig2cq_prdy;
 wire ig2cq_pvld;
 wire nvdla_gated_clk;
 wire op_load;

assign op_load = reg2dp_op_en & !layer_process;
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    layer_process <= 1'b0;
  end else begin
    if (op_load) begin
        layer_process <= 1'b1;
    end else if (eg_done) begin
        layer_process <= 1'b0;
    end
  end
end
assign dp2reg_done = eg_done;

NV_NVDLA_SDP_ERDMA_gate u_gate (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync)
  ,.erdma_disable (erdma_disable)
  ,.erdma_slcg_op_en (erdma_slcg_op_en)
  ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync)
  ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating)
  ,.nvdla_gated_clk (nvdla_gated_clk)
  );
NV_NVDLA_SDP_ERDMA_ig u_ig (
   .reg2dp_channel (reg2dp_channel[12:0])
  ,.reg2dp_erdma_data_mode (reg2dp_erdma_data_mode)
  ,.reg2dp_erdma_data_size (reg2dp_erdma_data_size)
  ,.reg2dp_erdma_data_use (reg2dp_erdma_data_use[1:0])
  ,.reg2dp_erdma_ram_type (reg2dp_erdma_ram_type)
  ,.reg2dp_ew_base_addr_high (reg2dp_ew_base_addr_high[31:0])
  ,.reg2dp_ew_base_addr_low (reg2dp_ew_base_addr_low[26:0])
  ,.reg2dp_ew_line_stride (reg2dp_ew_line_stride[26:0])
  ,.reg2dp_ew_surface_stride (reg2dp_ew_surface_stride[26:0])
  ,.reg2dp_height (reg2dp_height[12:0])
  ,.reg2dp_op_en (reg2dp_op_en)
  ,.reg2dp_perf_dma_en (reg2dp_perf_dma_en)
  ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0])
  ,.reg2dp_width (reg2dp_width[12:0])
  ,.reg2dp_winograd (reg2dp_winograd)
  ,.dp2reg_erdma_stall (dp2reg_erdma_stall[31:0])
  ,.op_load (op_load)
  ,.nvdla_core_clk (nvdla_gated_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.sdp_e2mcif_rd_req_valid (sdp_e2mcif_rd_req_valid)
  ,.sdp_e2mcif_rd_req_ready (sdp_e2mcif_rd_req_ready)
  ,.sdp_e2mcif_rd_req_pd (sdp_e2mcif_rd_req_pd[78:0])
  ,.sdp_e2cvif_rd_req_valid (sdp_e2cvif_rd_req_valid)
  ,.sdp_e2cvif_rd_req_ready (sdp_e2cvif_rd_req_ready)
  ,.sdp_e2cvif_rd_req_pd (sdp_e2cvif_rd_req_pd[78:0])
  ,.ig2cq_pvld (ig2cq_pvld)
  ,.ig2cq_prdy (ig2cq_prdy)
  ,.ig2cq_pd (ig2cq_pd[15:0])
  );
NV_NVDLA_SDP_ERDMA_cq u_cq (
   .nvdla_core_clk (nvdla_gated_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.ig2cq_prdy (ig2cq_prdy)
  ,.ig2cq_pvld (ig2cq_pvld)
  ,.ig2cq_pd (ig2cq_pd[15:0])
  ,.cq2eg_prdy (cq2eg_prdy)
  ,.cq2eg_pvld (cq2eg_pvld)
  ,.cq2eg_pd (cq2eg_pd[15:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  );
NV_NVDLA_SDP_ERDMA_eg u_eg (
   .nvdla_core_clk (nvdla_gated_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.mcif2sdp_e_rd_rsp_valid (mcif2sdp_e_rd_rsp_valid)
  ,.mcif2sdp_e_rd_rsp_ready (mcif2sdp_e_rd_rsp_ready)
  ,.mcif2sdp_e_rd_rsp_pd (mcif2sdp_e_rd_rsp_pd[513:0])
  ,.cvif2sdp_e_rd_rsp_valid (cvif2sdp_e_rd_rsp_valid)
  ,.cvif2sdp_e_rd_rsp_ready (cvif2sdp_e_rd_rsp_ready)
  ,.cvif2sdp_e_rd_rsp_pd (cvif2sdp_e_rd_rsp_pd[513:0])
  ,.sdp_e2mcif_rd_cdt_lat_fifo_pop (sdp_e2mcif_rd_cdt_lat_fifo_pop)
  ,.sdp_e2cvif_rd_cdt_lat_fifo_pop (sdp_e2cvif_rd_cdt_lat_fifo_pop)
  ,.cq2eg_pvld (cq2eg_pvld)
  ,.cq2eg_prdy (cq2eg_prdy)
  ,.cq2eg_pd (cq2eg_pd[15:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  ,.sdp_erdma2dp_alu_valid (sdp_erdma2dp_alu_valid)
  ,.sdp_erdma2dp_alu_ready (sdp_erdma2dp_alu_ready)
  ,.sdp_erdma2dp_alu_pd (sdp_erdma2dp_alu_pd[256:0])
  ,.sdp_erdma2dp_mul_valid (sdp_erdma2dp_mul_valid)
  ,.sdp_erdma2dp_mul_ready (sdp_erdma2dp_mul_ready)
  ,.sdp_erdma2dp_mul_pd (sdp_erdma2dp_mul_pd[256:0])
  ,.reg2dp_batch_number (reg2dp_batch_number[4:0])
  ,.reg2dp_channel (reg2dp_channel[12:0])
  ,.reg2dp_erdma_data_mode (reg2dp_erdma_data_mode)
  ,.reg2dp_erdma_data_size (reg2dp_erdma_data_size)
  ,.reg2dp_erdma_data_use (reg2dp_erdma_data_use[1:0])
  ,.reg2dp_erdma_ram_type (reg2dp_erdma_ram_type)
  ,.reg2dp_height (reg2dp_height[12:0])
  ,.reg2dp_out_precision (reg2dp_out_precision[1:0])
  ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0])
  ,.reg2dp_width (reg2dp_width[12:0])
  ,.op_load (op_load)
  ,.eg_done (eg_done)
  );


endmodule