data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_cclk_inv_64x.v
data/verilator_xmls/e1cc6ba7-4edb-406f-8fb1-343cd74cf745.xml
module bw_clk_cclk_inv_64x (
    clkout,
    clkin );

    output clkout;
    input  clkin;
 
    assign clkout = ~( clkin );

endmodule
module bw_clk_cclk_inv_64x (
    clkout,
    clkin );


    output clkout;
    input  clkin;
 
    assign clkout = ~( clkin );

endmodule