data/full_repos/permissive/407433468/PRJ0_EJEMPLO_1 (1)/PRJ0_EJEMPLO_1/rtl/CC_BIN2BCD1.v
1: b'%Error: Cannot find file containing module: (1)/PRJ0_EJEMPLO_1/rtl,data/full_repos/permissive/407433468\n        ... Looked in:\n             data/full_repos/permissive/407433468/PRJ0_EJEMPLO_1/(1)/PRJ0_EJEMPLO_1/rtl,data/full_repos/permissive/407433468\n             data/full_repos/permissive/407433468/PRJ0_EJEMPLO_1/(1)/PRJ0_EJEMPLO_1/rtl,data/full_repos/permissive/407433468.v\n             data/full_repos/permissive/407433468/PRJ0_EJEMPLO_1/(1)/PRJ0_EJEMPLO_1/rtl,data/full_repos/permissive/407433468.sv\n             (1)/PRJ0_EJEMPLO_1/rtl,data/full_repos/permissive/407433468\n             (1)/PRJ0_EJEMPLO_1/rtl,data/full_repos/permissive/407433468.v\n             (1)/PRJ0_EJEMPLO_1/rtl,data/full_repos/permissive/407433468.sv\n             obj_dir/(1)/PRJ0_EJEMPLO_1/rtl,data/full_repos/permissive/407433468\n             obj_dir/(1)/PRJ0_EJEMPLO_1/rtl,data/full_repos/permissive/407433468.v\n             obj_dir/(1)/PRJ0_EJEMPLO_1/rtl,data/full_repos/permissive/407433468.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/407433468/PRJ0_EJEMPLO_1\n%Error: Cannot find file containing module: (1)/PRJ0_EJEMPLO_1/rtl/CC_BIN2BCD1.v\n%Error: Exiting due to 3 error(s)\n'
module CC_BIN2BCD1 (
	CC_BIN2BCD_bcd_OutBUS,
	CC_BIN2BCD_bin_InBUS
);
   

input [7:0] CC_BIN2BCD_bin_InBUS;

output [11:0] CC_BIN2BCD_bcd_OutBUS;

reg [11 : 0] CC_BIN2BCD_bcd_OutBUS; 
reg [3:0] i;   
     

     always @(CC_BIN2BCD_bin_InBUS)
        begin
            CC_BIN2BCD_bcd_OutBUS = 0;
            for (i = 0; i < 8; i = i+1)
            begin
                CC_BIN2BCD_bcd_OutBUS = {CC_BIN2BCD_bcd_OutBUS[10:0],CC_BIN2BCD_bin_InBUS[7-i]};
                    

                if(i < 7 && CC_BIN2BCD_bcd_OutBUS[3:0] > 4) 
                    CC_BIN2BCD_bcd_OutBUS[3:0] = CC_BIN2BCD_bcd_OutBUS[3:0] + 3;
                if(i < 7 && CC_BIN2BCD_bcd_OutBUS[7:4] > 4)
                    CC_BIN2BCD_bcd_OutBUS[7:4] = CC_BIN2BCD_bcd_OutBUS[7:4] + 3;
                if(i < 7 && CC_BIN2BCD_bcd_OutBUS[11:8] > 4)
                    CC_BIN2BCD_bcd_OutBUS[11:8] = CC_BIN2BCD_bcd_OutBUS[11:8] + 3;  
            end
        end     
                
endmodule
module CC_BIN2BCD1 (
	CC_BIN2BCD_bcd_OutBUS,
	CC_BIN2BCD_bin_InBUS
);

   

input [7:0] CC_BIN2BCD_bin_InBUS;

output [11:0] CC_BIN2BCD_bcd_OutBUS;

reg [11 : 0] CC_BIN2BCD_bcd_OutBUS; 
reg [3:0] i;   
     

     always @(CC_BIN2BCD_bin_InBUS)
        begin
            CC_BIN2BCD_bcd_OutBUS = 0;
            for (i = 0; i < 8; i = i+1)
            begin
                CC_BIN2BCD_bcd_OutBUS = {CC_BIN2BCD_bcd_OutBUS[10:0],CC_BIN2BCD_bin_InBUS[7-i]};
                    

                if(i < 7 && CC_BIN2BCD_bcd_OutBUS[3:0] > 4) 
                    CC_BIN2BCD_bcd_OutBUS[3:0] = CC_BIN2BCD_bcd_OutBUS[3:0] + 3;
                if(i < 7 && CC_BIN2BCD_bcd_OutBUS[7:4] > 4)
                    CC_BIN2BCD_bcd_OutBUS[7:4] = CC_BIN2BCD_bcd_OutBUS[7:4] + 3;
                if(i < 7 && CC_BIN2BCD_bcd_OutBUS[11:8] > 4)
                    CC_BIN2BCD_bcd_OutBUS[11:8] = CC_BIN2BCD_bcd_OutBUS[11:8] + 3;  
            end
        end     
                
endmodule