data/full_repos/permissive/410822585/axscr_3_exact.v
1: b"%Error: data/full_repos/permissive/410822585/axscr_3_exact.v:3: syntax error, unexpected output, expecting ')' or ','\n    output xor\n    ^~~~~~\n%Error: data/full_repos/permissive/410822585/axscr_3_exact.v:8: syntax error, unexpected pmos\n    pmos t1 (xb, vdd, x);\n    ^~~~\n%Error: data/full_repos/permissive/410822585/axscr_3_exact.v:16: syntax error, unexpected output, expecting ')' or ','\n    output x_nor\n    ^~~~~~\n%Error: data/full_repos/permissive/410822585/axscr_3_exact.v:21: syntax error, unexpected pmos\n    pmos t1 (xb, vdd, x);\n    ^~~~\n%Error: data/full_repos/permissive/410822585/axscr_3_exact.v:29: syntax error, unexpected output, expecting ')' or ','\n    output xor\n    ^~~~~~\n%Error: data/full_repos/permissive/410822585/axscr_3_exact.v:32: syntax error, unexpected pmos\n    pmos t1 (xor, y, x);\n    ^~~~\n%Error: data/full_repos/permissive/410822585/axscr_3_exact.v:39: syntax error, unexpected output, expecting ')' or ','\n    output d, bout\n    ^~~~~~\n%Error: data/full_repos/permissive/410822585/axscr_3_exact.v:42: syntax error, unexpected IDENTIFIER\n    xnor_4t(.x(x), .y(y), .x_nor(t1));\n    ^~~~~~~\n%Error: data/full_repos/permissive/410822585/axscr_3_exact.v:50: syntax error, unexpected output, expecting ')' or ','\n    output d, bout\n    ^~~~~~\n%Error: data/full_repos/permissive/410822585/axscr_3_exact.v:53: syntax error, unexpected IDENTIFIER\n    xor_3t(.x(x), .y(y), .x_nor(t1));\n    ^~~~~~\n%Error: data/full_repos/permissive/410822585/axscr_3_exact.v:61: syntax error, unexpected output, expecting ')' or ','\n    output d, bout\n    ^~~~~~\n%Error: data/full_repos/permissive/410822585/axscr_3_exact.v:64: syntax error, unexpected IDENTIFIER\n    xor_4t(.x(x), .y(y), .xor(t1));\n    ^~~~~~\n%Error: data/full_repos/permissive/410822585/axscr_3_exact.v:73: syntax error, unexpected output, expecting ')' or ','\n    output d, bout\n    ^~~~~~\n%Error: data/full_repos/permissive/410822585/axscr_3_exact.v:76: syntax error, unexpected IDENTIFIER\n    xnor_4t (.x(x), .y(y), .x_nor(t1));\n    ^~~~~~~\n%Error: data/full_repos/permissive/410822585/axscr_3_exact.v:83: syntax error, unexpected output, expecting ')' or ','\n    output d, bout\n    ^~~~~~\n%Error: data/full_repos/permissive/410822585/axscr_3_exact.v:86: syntax error, unexpected IDENTIFIER\n    xnor_4t(.x(x), .y(y), .x_nor(t1));\n    ^~~~~~~\n%Error: data/full_repos/permissive/410822585/axscr_3_exact.v:94: syntax error, unexpected output, expecting ')' or ','\n    output bout, diff \n    ^~~~~~\n%Error: data/full_repos/permissive/410822585/axscr_3_exact.v:103: syntax error, unexpected output, expecting ')' or ','\n    output bout, diff \n    ^~~~~~\n%Error: data/full_repos/permissive/410822585/axscr_3_exact.v:106: syntax error, unexpected IDENTIFIER\n    axsc1(.x(x), .y(y), .d(diff), .bout(bout), .bin(bin));\n    ^~~~~\n%Error: data/full_repos/permissive/410822585/axscr_3_exact.v:113: syntax error, unexpected output, expecting ')' or ','\n    output bout, diff \n    ^~~~~~\n%Error: data/full_repos/permissive/410822585/axscr_3_exact.v:116: syntax error, unexpected IDENTIFIER\n    axsc2(.x(x), .y(y), .d(diff), .bout(bout), .bin(bin));\n    ^~~~~\n%Error: data/full_repos/permissive/410822585/axscr_3_exact.v:123: syntax error, unexpected output, expecting ')' or ','\n    output bout, diff \n    ^~~~~~\n%Error: data/full_repos/permissive/410822585/axscr_3_exact.v:126: syntax error, unexpected IDENTIFIER\n    axsc3(.x(x), .y(y), .d(diff), .bout(bout), .bin(bin));\n    ^~~~~\n%Error: Exiting due to 23 error(s)\n"
module app_1 (
    input [8:0]x, 
    input bin,
    input [7:0]y,
    output qs,
    output [7:0]rout
);
    wire i1, i2, i3, i4, i5, i6, i7, i8;
    wire d1, d2, d3, d4, d5, d6, d7, d8;
    axscr_3 mut1 (.x(x[0]), .y(y[0]), .bin(bin), .bout(i1), .diff(d1));
    exdcr mut2 (.x(x[1]), .y(y[1]), .bin(i1), .bout(i2), .diff(d2));
    exdcr mut3 (.x(x[2]), .y(y[2]), .bin(i2), .bout(i3), .diff(d3));
    exdcr mut4 (.x(x[3]), .y(y[3]), .bin(i3), .bout(i4), .diff(d4));
    exdcr mut5 (.x(x[4]), .y(y[4]), .bin(i4), .bout(i5), .diff(d5));
    exdcr mut6 (.x(x[5]), .y(y[5]), .bin(i5), .bout(i6), .diff(d6));
    exdcr mut7 (.x(x[6]), .y(y[6]), .bin(i6), .bout(i7), .diff(d7));
    exdcr mut8 (.x(x[7]), .y(y[7]), .bin(i7), .bout(i8), .diff(d8));
    assign qs = ~i8 | x[8];
    nmos t1 (rout[0], d1, qs);
    pmos t2 (rout[0], x[0], qs);
    nmos t3 (rout[1], d2, qs);
    pmos t4 (rout[1], x[1], qs);
    nmos t5 (rout[2], d3, qs);
    pmos t6 (rout[2], x[2], qs);
    nmos t7 (rout[3], d4, qs);
    pmos t8 (rout[3], x[3], qs);
    nmos t9 (rout[4], d5, qs);
    pmos t10 (rout[4], x[4], qs);
    nmos t11 (rout[5], d6, qs);
    pmos t12 (rout[5], x[5], qs);
    nmos t13 (rout[6], d7, qs);
    pmos t14 (rout[6], x[6], qs);
    nmos t15 (rout[7], d8, qs);
    pmos t16 (rout[7], x[7], qs);
endmodule
module app_1 (
    input [8:0]x, 
    input bin,
    input [7:0]y,
    output qs,
    output [7:0]rout
);

    wire i1, i2, i3, i4, i5, i6, i7, i8;
    wire d1, d2, d3, d4, d5, d6, d7, d8;
    axscr_3 mut1 (.x(x[0]), .y(y[0]), .bin(bin), .bout(i1), .diff(d1));
    exdcr mut2 (.x(x[1]), .y(y[1]), .bin(i1), .bout(i2), .diff(d2));
    exdcr mut3 (.x(x[2]), .y(y[2]), .bin(i2), .bout(i3), .diff(d3));
    exdcr mut4 (.x(x[3]), .y(y[3]), .bin(i3), .bout(i4), .diff(d4));
    exdcr mut5 (.x(x[4]), .y(y[4]), .bin(i4), .bout(i5), .diff(d5));
    exdcr mut6 (.x(x[5]), .y(y[5]), .bin(i5), .bout(i6), .diff(d6));
    exdcr mut7 (.x(x[6]), .y(y[6]), .bin(i6), .bout(i7), .diff(d7));
    exdcr mut8 (.x(x[7]), .y(y[7]), .bin(i7), .bout(i8), .diff(d8));
    assign qs = ~i8 | x[8];
    nmos t1 (rout[0], d1, qs);
    pmos t2 (rout[0], x[0], qs);
    nmos t3 (rout[1], d2, qs);
    pmos t4 (rout[1], x[1], qs);
    nmos t5 (rout[2], d3, qs);
    pmos t6 (rout[2], x[2], qs);
    nmos t7 (rout[3], d4, qs);
    pmos t8 (rout[3], x[3], qs);
    nmos t9 (rout[4], d5, qs);
    pmos t10 (rout[4], x[4], qs);
    nmos t11 (rout[5], d6, qs);
    pmos t12 (rout[5], x[5], qs);
    nmos t13 (rout[6], d7, qs);
    pmos t14 (rout[6], x[6], qs);
    nmos t15 (rout[7], d8, qs);
    pmos t16 (rout[7], x[7], qs);
endmodule