data/full_repos/permissive/458737381/src/verilog-parser/tests/param_more_then_one1.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/param_more_then_one1.v:5: Cannot find file containing module: 'ram_sp_sr_sw'\nram_sp_sr_sw #(16,8,256)  ram(clk,address,data,cs,we,oe);\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/ram_sp_sr_sw\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/ram_sp_sr_sw.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/ram_sp_sr_sw.sv\n             ram_sp_sr_sw\n             ram_sp_sr_sw.v\n             ram_sp_sr_sw.sv\n             obj_dir/ram_sp_sr_sw\n             obj_dir/ram_sp_sr_sw.v\n             obj_dir/ram_sp_sr_sw.sv\n%Error: Exiting due to 1 error(s)\n"
module  ram_controller ();


 
ram_sp_sr_sw #(16,8,256)  ram(clk,address,data,cs,we,oe);
 
endmodule
module  ram_controller ();



 
ram_sp_sr_sw #(16,8,256)  ram(clk,address,data,cs,we,oe);
 
endmodule