data/full_repos/permissive/482975152/PipelinedProcessor.srcs/sources_1/new/IM.v
data/verilator_xmls/04ab685f-3daa-4ab7-88d1-7f7793f1c6e0.xml
module IM(
    input [31:0] IMA,
    output reg [31:0] IMRD
    );
    
    reg [31:0] Instruction [31:0];
    
    initial begin
        $readmemb("InstructionsE.mem", Instruction);
    end
    
    always @ (IMA) begin
        IMRD <= Instruction[IMA];
    end
endmodule
module IM(
    input [31:0] IMA,
    output reg [31:0] IMRD
    );

    
    reg [31:0] Instruction [31:0];
    
    initial begin
        $readmemb("InstructionsE.mem", Instruction);
    end
    
    always @ (IMA) begin
        IMRD <= Instruction[IMA];
    end
endmodule