data/full_repos/permissive/509809169/Circuits/Sequential Logic/Shift Registers/Left_right arithmetic shift by 8.v
1: b'%Error: Cannot find file containing module: Logic/Shift\n        ... Looked in:\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Shift\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Shift.v\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Shift.sv\n             Logic/Shift\n             Logic/Shift.v\n             Logic/Shift.sv\n             obj_dir/Logic/Shift\n             obj_dir/Logic/Shift.v\n             obj_dir/Logic/Shift.sv\n%Error: Cannot find file containing module: Registers,data/full_repos/permissive/509809169\n%Error: Cannot find file containing module: data/full_repos/permissive/509809169/Circuits/Sequential\n%Error: Cannot find file containing module: Registers/Left_right\n%Error: Cannot find file containing module: arithmetic\n%Error: Cannot find file containing module: shift\n%Error: Cannot find file containing module: by\n%Error: Cannot find file containing module: 8.v\n%Error: Exiting due to 8 error(s)\n'
module top_module(
    input clk,
    input load,
    input ena,
    input [1:0] amount,
    input [63:0] data,
    output reg [63:0] q); 
    wire w=0;
    always @(posedge clk) begin
        if(load) q<=data;
        else begin
            if(ena) begin
                case(amount)
                    2'b00: q<= {q[62:0],w};
                    2'b01: q<= {q[55:0],{8{w}}};
                    2'b10: q<= {q[63],q[63:1]};
                    2'b11: q<= {{8{q[63]}},q[63:8]};
                endcase
            end
        end
    end
endmodule
module top_module(
    input clk,
    input load,
    input ena,
    input [1:0] amount,
    input [63:0] data,
    output reg [63:0] q);
 
    wire w=0;
    always @(posedge clk) begin
        if(load) q<=data;
        else begin
            if(ena) begin
                case(amount)
                    2'b00: q<= {q[62:0],w};
                    2'b01: q<= {q[55:0],{8{w}}};
                    2'b10: q<= {q[63],q[63:1]};
                    2'b11: q<= {{8{q[63]}},q[63:8]};
                endcase
            end
        end
    end
endmodule