data/full_repos/permissive/505918157/control_logic.v
1: b'%Error: data/full_repos/permissive/505918157/control_logic.v:21: Cannot find include file: INSTRUCTIONS.v\n`include "INSTRUCTIONS.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/505918157,data/full_repos/permissive/505918157/INSTRUCTIONS.v\n             data/full_repos/permissive/505918157,data/full_repos/permissive/505918157/INSTRUCTIONS.v.v\n             data/full_repos/permissive/505918157,data/full_repos/permissive/505918157/INSTRUCTIONS.v.sv\n             INSTRUCTIONS.v\n             INSTRUCTIONS.v.v\n             INSTRUCTIONS.v.sv\n             obj_dir/INSTRUCTIONS.v\n             obj_dir/INSTRUCTIONS.v.v\n             obj_dir/INSTRUCTIONS.v.sv\n%Error: data/full_repos/permissive/505918157/control_logic.v:76: Define or directive not defined: \'`BUS_mode_WRITE\'\n            BUS_mode = `BUS_mode_WRITE;\n                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/control_logic.v:76: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            BUS_mode = `BUS_mode_WRITE;\n                                      ^\n%Error: data/full_repos/permissive/505918157/control_logic.v:79: Define or directive not defined: \'`BUS_mode_READ\'\n            BUS_mode = `BUS_mode_READ;\n                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/control_logic.v:79: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            BUS_mode = `BUS_mode_READ;\n                                     ^\n%Error: data/full_repos/permissive/505918157/control_logic.v:144: Define or directive not defined: \'`reg_CS_ALU\'\n        reg_CS = `reg_CS_ALU;\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/control_logic.v:144: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        reg_CS = `reg_CS_ALU;\n                            ^\n%Error: data/full_repos/permissive/505918157/control_logic.v:146: Define or directive not defined: \'`reg_CS_ALU\'\n            reg_CS = `reg_CS_ALU;\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/control_logic.v:146: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            reg_CS = `reg_CS_ALU;\n                                ^\n%Error: data/full_repos/permissive/505918157/control_logic.v:149: Define or directive not defined: \'`reg_CS_BUS\'\n            reg_CS = `reg_CS_BUS;\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/control_logic.v:149: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            reg_CS = `reg_CS_BUS;\n                                ^\n%Error: data/full_repos/permissive/505918157/control_logic.v:152: Define or directive not defined: \'`reg_CS_IM\'\n            reg_CS = `reg_CS_IM;\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/control_logic.v:152: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            reg_CS = `reg_CS_IM;\n                               ^\n%Error: data/full_repos/permissive/505918157/control_logic.v:155: Define or directive not defined: \'`reg_CS_PC\'\n            reg_CS = `reg_CS_PC;\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/control_logic.v:155: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            reg_CS = `reg_CS_PC;\n                               ^\n%Error: data/full_repos/permissive/505918157/control_logic.v:166: Define or directive not defined: \'`PC_CS_IM\'\n            PC_CS = `PC_CS_IM;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/505918157/control_logic.v:166: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            PC_CS = `PC_CS_IM;\n                             ^\n%Error: data/full_repos/permissive/505918157/control_logic.v:174: Define or directive not defined: \'`PC_mode_inc\'\n        PC_mode = `PC_mode_inc;\n                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/control_logic.v:174: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        PC_mode = `PC_mode_inc;\n                              ^\n%Error: data/full_repos/permissive/505918157/control_logic.v:176: Define or directive not defined: \'`PC_mode_inc\'\n            PC_mode = `PC_mode_inc;\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/control_logic.v:176: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            PC_mode = `PC_mode_inc;\n                                  ^\n%Error: data/full_repos/permissive/505918157/control_logic.v:179: Define or directive not defined: \'`PC_mode_jal\'\n            PC_mode = `PC_mode_jal;\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/control_logic.v:179: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            PC_mode = `PC_mode_jal;\n                                  ^\n%Error: data/full_repos/permissive/505918157/control_logic.v:182: Define or directive not defined: \'`PC_mode_inc\'\n            PC_mode = `PC_mode_inc;\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/control_logic.v:182: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            PC_mode = `PC_mode_inc;\n                                  ^\n%Error: data/full_repos/permissive/505918157/control_logic.v:200: Define or directive not defined: \'`ALU_mode_ADD\'\n        ALU_mode = `ALU_mode_ADD;\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/control_logic.v:200: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        ALU_mode = `ALU_mode_ADD;\n                                ^\n%Error: data/full_repos/permissive/505918157/control_logic.v:202: Define or directive not defined: \'`ALU_mode_ADD\'\n            ALU_mode = `ALU_mode_ADD;\n                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/control_logic.v:202: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            ALU_mode = `ALU_mode_ADD;\n                                    ^\n%Error: data/full_repos/permissive/505918157/control_logic.v:205: Define or directive not defined: \'`ALU_mode_SUB\'\n            ALU_mode = `ALU_mode_SUB;\n                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/control_logic.v:205: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            ALU_mode = `ALU_mode_SUB;\n                                    ^\n%Error: data/full_repos/permissive/505918157/control_logic.v:209: Define or directive not defined: \'`ALU_CS1_reg0\'\n   assign ALU_CS1 = `ALU_CS1_reg0;\n                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/control_logic.v:209: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   assign ALU_CS1 = `ALU_CS1_reg0;\n                                 ^\n%Error: data/full_repos/permissive/505918157/control_logic.v:212: Define or directive not defined: \'`ALU_CS2_reg1\'\n        ALU_CS2 = `ALU_CS2_reg1;\n                  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/control_logic.v:212: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        ALU_CS2 = `ALU_CS2_reg1;\n                               ^\n%Error: data/full_repos/permissive/505918157/control_logic.v:214: Define or directive not defined: \'`ALU_CS2_IM\'\n            ALU_CS2 = `ALU_CS2_IM;\n                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/control_logic.v:214: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            ALU_CS2 = `ALU_CS2_IM;\n                                 ^\n%Error: data/full_repos/permissive/505918157/control_logic.v:217: Define or directive not defined: \'`ALU_CS2_reg1\'\n            ALU_CS2 = `ALU_CS2_reg1;\n                      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/control_logic.v:217: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            ALU_CS2 = `ALU_CS2_reg1;\n                                   ^\n%Error: data/full_repos/permissive/505918157/control_logic.v:222: Define or directive not defined: \'`BUS_ADDR_CS_PC\'\n        BUS_ADDR_CS = `BUS_ADDR_CS_PC;\n                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/control_logic.v:222: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        BUS_ADDR_CS = `BUS_ADDR_CS_PC;\n                                     ^\n%Error: data/full_repos/permissive/505918157/control_logic.v:224: Define or directive not defined: \'`BUS_ADDR_CS_PC\'\n            BUS_ADDR_CS = `BUS_ADDR_CS_PC;\n                          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/control_logic.v:224: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            BUS_ADDR_CS = `BUS_ADDR_CS_PC;\n                                         ^\n%Error: data/full_repos/permissive/505918157/control_logic.v:227: Define or directive not defined: \'`BUS_ADDR_CS_ALU\'\n            BUS_ADDR_CS = `BUS_ADDR_CS_ALU;\n                          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/control_logic.v:227: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            BUS_ADDR_CS = `BUS_ADDR_CS_ALU;\n                                          ^\n%Error: data/full_repos/permissive/505918157/control_logic.v:230: Define or directive not defined: \'`BUS_ADDR_CS_ALU\'\n            BUS_ADDR_CS = `BUS_ADDR_CS_ALU;\n                          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/control_logic.v:230: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            BUS_ADDR_CS = `BUS_ADDR_CS_ALU;\n                                          ^\n%Error: data/full_repos/permissive/505918157/control_logic.v:233: Define or directive not defined: \'`BUS_ADDR_CS_PC\'\n            BUS_ADDR_CS = `BUS_ADDR_CS_PC;\n                          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/505918157/control_logic.v:233: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n            BUS_ADDR_CS = `BUS_ADDR_CS_PC;\n                                         ^\n%Error: data/full_repos/permissive/505918157/control_logic.v:237: Define or directive not defined: \'`BUS_DATA_CS_reg0\'\n    assign BUS_DATA_CS = `BUS_DATA_CS_reg0;\n                         ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module control_logic(
    input BUS_rdata_valid,
    input BUS_write_done,
    input Mif,
    input Mex,
    input T1,
    input T2,
    input T3,
    input T4,
    input T1_Mif,
    input T2_Mif,
    input [2:0] cur_state,

    output reg output_done,
    output wire ins_reg_en,
    output reg reg_wen,
    output reg [2:0] reg_CS,
    output reg [1:0] PC_CS,
    output reg PC_EN,
    output reg PC_mode,
    output reg ALU_mode,
    output wire [1:0] ALU_CS1,
    output reg [1:0] ALU_CS2,
    output reg [2:0] BUS_ADDR_CS,
    output wire [2:0] BUS_DATA_CS,
    output reg BUS_mode,
    output reg BUS_start_transaction,
    
    input ins_ADD,
    input ins_SUB,
    input ins_SW,
    input ins_LW,
    input ins_ADDI,
    input ins_LUI,
    input ins_JAL
    );

    localparam [2:0] IDLE = 3'd0,
        IF1 = 3'd1,
        IF2 = 3'd2,
        EX1 = 3'd3,
        EX2 = 3'd4,
        EX3 = 3'd5,
        EX4 = 3'd6;

    assign ins_reg_en = BUS_rdata_valid && Mif;

    always @(*) begin
        BUS_mode = 1'b0;
        if (Mif) begin
            BUS_mode = 1'b0; 
        end
        else if (Mex && ins_SW) begin
            BUS_mode = `BUS_mode_WRITE;
        end
        else if (Mex && ins_LW) begin
            BUS_mode = `BUS_mode_READ;
        end
        else begin
            BUS_mode = 1'b0;
        end
    end

    always @(*) begin
        BUS_start_transaction = 1'b0;
        if (Mif && T1_Mif) begin
            BUS_start_transaction = 1'b1;
        end
        else if (Mex && ins_SW && T2) begin
            BUS_start_transaction = 1'b1;
        end
        else if (Mex && ins_LW && T2) begin
            BUS_start_transaction = 1'b1;
        end
        else begin
            BUS_start_transaction = 1'b0;
        end
    end

    always @(*) begin
        output_done = 1'b0;
        if (Mif) begin
            output_done = BUS_rdata_valid;
        end
        else if (Mex && ins_SW && cur_state == EX2) begin
            output_done = BUS_write_done;
        end
        else if (Mex && ins_LW && cur_state == EX2) begin
            output_done = BUS_rdata_valid;
        end
        else begin
            output_done = T1 || T2 || T3 || T4;
        end
    end

    always @(*) begin
        reg_wen = 1'b0;
        if (Mex && ins_ADD && T1) begin
            reg_wen = 1'b1;
        end
        else if (Mex && ins_ADDI && T1) begin
            reg_wen = 1'b1;
        end
        else if (Mex && ins_SUB && T1) begin
            reg_wen = 1'b1;
        end
        else if (Mex && ins_LW && T3) begin
            reg_wen = 1'b1;
        end
        else if (Mex && ins_LUI && T1) begin
            reg_wen = 1'b1;
        end
        else if (Mex && ins_JAL && T1) begin
            reg_wen = 1'b1;
        end
        else begin
            reg_wen = 1'b0;
        end
    end

    always @(*) begin
        reg_CS = `reg_CS_ALU;
        if (Mex && (ins_ADD || ins_ADDI || ins_SUB)) begin
            reg_CS = `reg_CS_ALU;
        end
        else if (Mex && ins_LW) begin
            reg_CS = `reg_CS_BUS;
        end
        else if (Mex && ins_LUI) begin
            reg_CS = `reg_CS_IM;
        end
        else if (Mex && ins_JAL) begin
            reg_CS = `reg_CS_PC;
        end
    end

    always @(*) begin
        PC_CS = 2'd0;




        if (ins_JAL) begin
            PC_CS = `PC_CS_IM;
        end
        else begin
            PC_CS = 2'd0;
        end
    end

    always @(*) begin
        PC_mode = `PC_mode_inc;
        if (Mif) begin
            PC_mode = `PC_mode_inc;
        end
        else if (ins_JAL) begin
            PC_mode = `PC_mode_jal;
        end
        else begin
            PC_mode = `PC_mode_inc;
        end
    end

    always @(*) begin
        PC_EN = 1'b0;
        if (Mif && T1_Mif) begin
            PC_EN = 1'b1;
        end
        else if (Mex && ins_JAL) begin
            PC_EN = 1'b1;
        end
        else begin
            PC_EN = 1'b0;
        end
    end

    always @(*) begin
        ALU_mode = `ALU_mode_ADD;
        if (ins_ADD || ins_ADDI) begin
            ALU_mode = `ALU_mode_ADD;
        end
        else if (ins_SUB) begin
            ALU_mode = `ALU_mode_SUB;
        end
    end

   assign ALU_CS1 = `ALU_CS1_reg0;

    always @(*) begin
        ALU_CS2 = `ALU_CS2_reg1;
        if (ins_ADDI || ins_SW || ins_LW) begin
            ALU_CS2 = `ALU_CS2_IM;
        end
        else begin
            ALU_CS2 = `ALU_CS2_reg1;
        end
    end

    always @(*) begin
        BUS_ADDR_CS = `BUS_ADDR_CS_PC;
        if (Mif) begin
            BUS_ADDR_CS = `BUS_ADDR_CS_PC;
        end
        else if (Mex && ins_SW) begin
            BUS_ADDR_CS = `BUS_ADDR_CS_ALU;
        end
        else if (Mex && ins_LW) begin
            BUS_ADDR_CS = `BUS_ADDR_CS_ALU;
        end
        else begin
            BUS_ADDR_CS = `BUS_ADDR_CS_PC;
        end
    end
    
    assign BUS_DATA_CS = `BUS_DATA_CS_reg0;

endmodule
module control_logic(
    input BUS_rdata_valid,
    input BUS_write_done,
    input Mif,
    input Mex,
    input T1,
    input T2,
    input T3,
    input T4,
    input T1_Mif,
    input T2_Mif,
    input [2:0] cur_state,

    output reg output_done,
    output wire ins_reg_en,
    output reg reg_wen,
    output reg [2:0] reg_CS,
    output reg [1:0] PC_CS,
    output reg PC_EN,
    output reg PC_mode,
    output reg ALU_mode,
    output wire [1:0] ALU_CS1,
    output reg [1:0] ALU_CS2,
    output reg [2:0] BUS_ADDR_CS,
    output wire [2:0] BUS_DATA_CS,
    output reg BUS_mode,
    output reg BUS_start_transaction,
    
    input ins_ADD,
    input ins_SUB,
    input ins_SW,
    input ins_LW,
    input ins_ADDI,
    input ins_LUI,
    input ins_JAL
    );


    localparam [2:0] IDLE = 3'd0,
        IF1 = 3'd1,
        IF2 = 3'd2,
        EX1 = 3'd3,
        EX2 = 3'd4,
        EX3 = 3'd5,
        EX4 = 3'd6;

    assign ins_reg_en = BUS_rdata_valid && Mif;

    always @(*) begin
        BUS_mode = 1'b0;
        if (Mif) begin
            BUS_mode = 1'b0; 
        end
        else if (Mex && ins_SW) begin
            BUS_mode = `BUS_mode_WRITE;
        end
        else if (Mex && ins_LW) begin
            BUS_mode = `BUS_mode_READ;
        end
        else begin
            BUS_mode = 1'b0;
        end
    end

    always @(*) begin
        BUS_start_transaction = 1'b0;
        if (Mif && T1_Mif) begin
            BUS_start_transaction = 1'b1;
        end
        else if (Mex && ins_SW && T2) begin
            BUS_start_transaction = 1'b1;
        end
        else if (Mex && ins_LW && T2) begin
            BUS_start_transaction = 1'b1;
        end
        else begin
            BUS_start_transaction = 1'b0;
        end
    end

    always @(*) begin
        output_done = 1'b0;
        if (Mif) begin
            output_done = BUS_rdata_valid;
        end
        else if (Mex && ins_SW && cur_state == EX2) begin
            output_done = BUS_write_done;
        end
        else if (Mex && ins_LW && cur_state == EX2) begin
            output_done = BUS_rdata_valid;
        end
        else begin
            output_done = T1 || T2 || T3 || T4;
        end
    end

    always @(*) begin
        reg_wen = 1'b0;
        if (Mex && ins_ADD && T1) begin
            reg_wen = 1'b1;
        end
        else if (Mex && ins_ADDI && T1) begin
            reg_wen = 1'b1;
        end
        else if (Mex && ins_SUB && T1) begin
            reg_wen = 1'b1;
        end
        else if (Mex && ins_LW && T3) begin
            reg_wen = 1'b1;
        end
        else if (Mex && ins_LUI && T1) begin
            reg_wen = 1'b1;
        end
        else if (Mex && ins_JAL && T1) begin
            reg_wen = 1'b1;
        end
        else begin
            reg_wen = 1'b0;
        end
    end

    always @(*) begin
        reg_CS = `reg_CS_ALU;
        if (Mex && (ins_ADD || ins_ADDI || ins_SUB)) begin
            reg_CS = `reg_CS_ALU;
        end
        else if (Mex && ins_LW) begin
            reg_CS = `reg_CS_BUS;
        end
        else if (Mex && ins_LUI) begin
            reg_CS = `reg_CS_IM;
        end
        else if (Mex && ins_JAL) begin
            reg_CS = `reg_CS_PC;
        end
    end

    always @(*) begin
        PC_CS = 2'd0;




        if (ins_JAL) begin
            PC_CS = `PC_CS_IM;
        end
        else begin
            PC_CS = 2'd0;
        end
    end

    always @(*) begin
        PC_mode = `PC_mode_inc;
        if (Mif) begin
            PC_mode = `PC_mode_inc;
        end
        else if (ins_JAL) begin
            PC_mode = `PC_mode_jal;
        end
        else begin
            PC_mode = `PC_mode_inc;
        end
    end

    always @(*) begin
        PC_EN = 1'b0;
        if (Mif && T1_Mif) begin
            PC_EN = 1'b1;
        end
        else if (Mex && ins_JAL) begin
            PC_EN = 1'b1;
        end
        else begin
            PC_EN = 1'b0;
        end
    end

    always @(*) begin
        ALU_mode = `ALU_mode_ADD;
        if (ins_ADD || ins_ADDI) begin
            ALU_mode = `ALU_mode_ADD;
        end
        else if (ins_SUB) begin
            ALU_mode = `ALU_mode_SUB;
        end
    end

   assign ALU_CS1 = `ALU_CS1_reg0;

    always @(*) begin
        ALU_CS2 = `ALU_CS2_reg1;
        if (ins_ADDI || ins_SW || ins_LW) begin
            ALU_CS2 = `ALU_CS2_IM;
        end
        else begin
            ALU_CS2 = `ALU_CS2_reg1;
        end
    end

    always @(*) begin
        BUS_ADDR_CS = `BUS_ADDR_CS_PC;
        if (Mif) begin
            BUS_ADDR_CS = `BUS_ADDR_CS_PC;
        end
        else if (Mex && ins_SW) begin
            BUS_ADDR_CS = `BUS_ADDR_CS_ALU;
        end
        else if (Mex && ins_LW) begin
            BUS_ADDR_CS = `BUS_ADDR_CS_ALU;
        end
        else begin
            BUS_ADDR_CS = `BUS_ADDR_CS_PC;
        end
    end
    
    assign BUS_DATA_CS = `BUS_DATA_CS_reg0;

endmodule