data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_rxshift.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_rxshift.v:128: Cannot find file containing module: 'fflopx'\nfflopx #(MAC_BW) ffoutnob (rxclk, rxrst_, bvld_cnt, out_nob);\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core,data/full_repos/permissive/530013823/fflopx\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core,data/full_repos/permissive/530013823/fflopx.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core,data/full_repos/permissive/530013823/fflopx.sv\n             fflopx\n             fflopx.v\n             fflopx.sv\n             obj_dir/fflopx\n             obj_dir/fflopx.v\n             obj_dir/fflopx.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_rxshift.v:152: Cannot find file containing module: 'fflopx'\nfflopx #(1) ovld (rxclk, rxrst_, shift_out, out_vld);\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_rxshift.v:153: Cannot find file containing module: 'fflopx'\nfflopx #(1) oeop (rxclk, rxrst_, rx_ieop, out_eop);\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_rxshift.v:154: Cannot find file containing module: 'fflopx'\nfflopx #(1) osop (rxclk, rxrst_, (shift_out & shift_sop), out_sop);\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_rxshift.v:155: Cannot find file containing module: 'fflopx'\nfflopx #(DAT_EW) oerr (rxclk, rxrst_, (rx_ieop ? rx_ierr : shift_err), out_err);\n^~~~~~\n%Error: Exiting due to 5 error(s)\n"
module ipsmacge_rxshift
    (
     rxclk,
     rxrst_,

     rx_idat, 
     rx_isop,  
     rx_ieop,  
     rx_ivld,  
     rx_ierr,

     out_dat,
     out_nob,
     out_sop,  
     out_eop,  
     out_vld,  
     out_err
     );



parameter DAT_DW = 8;
parameter DAT_EW = 4;

parameter MAC_DW = 32;
parameter MAC_BW = 2;

parameter SHIFT_DW = MAC_DW - DAT_DW;
parameter VLD_1B = 2'h0,
          VLD_2B = 2'h1,
          VLD_3B = 2'h2,
          VLD_4B = 2'h3;


input     rxrst_;
input     rxclk;

input  [DAT_DW-1:0] rx_idat;
input               rx_ivld;
input               rx_isop;
input               rx_ieop;
input  [DAT_EW-1:0] rx_ierr;

output [MAC_DW-1:0] out_dat;
output [MAC_BW-1:0] out_nob;

output              out_vld;
output              out_sop;
output              out_eop;
output [DAT_EW-1:0] out_err;



reg  [MAC_DW-1:0]   out_dat;
wire [MAC_BW-1:0]   out_nob;

reg [MAC_BW-1:0]    bvld_cnt;
reg [SHIFT_DW-1:0]  shift_dat;
reg                 shift_sop;
reg [DAT_EW-1:0]    shift_err;
wire                shift_out;







always @(posedge rxclk or negedge rxrst_)
    begin
    if (!rxrst_)            bvld_cnt <= {(MAC_BW){1'b0}};
    else if (rx_ivld)
        begin
        if (rx_isop)        bvld_cnt <= {(MAC_BW){1'b0}} + 1'b1;
        else if (shift_out) bvld_cnt <= {(MAC_BW){1'b0}};
        else                bvld_cnt <= bvld_cnt + 1'b1;
        end
    end

integer i;

always @(posedge rxclk or negedge rxrst_)
    begin
    if (!rxrst_)
        begin
        shift_sop <= 1'b0;
        shift_err <= {DAT_EW{1'b0}};
        end
    else if (rx_ivld)
        begin
        if (rx_isop)         shift_sop <= 1'b1;
        else if (shift_out)  shift_sop <= 1'b0;
        else                 shift_sop <= shift_sop;

        if (rx_isop)         shift_err <= rx_ierr;
        else if (shift_out)  shift_err <= rx_ierr;
        else
            begin
            for (i = 0; i < DAT_EW; i = i + 1)
                shift_err [i] <= rx_ierr [i] ? 1'b1 : shift_err [i];
            end
        end
    end

always @(posedge rxclk or negedge rxrst_)
    begin
    if (!rxrst_)        shift_dat <= {SHIFT_DW{1'b0}};
    else if (rx_ivld)   shift_dat <= {shift_dat [SHIFT_DW-DAT_DW-1:0], rx_idat};
    end



assign shift_out = rx_ivld & (rx_ieop | (bvld_cnt == {MAC_BW{1'b1}}));

fflopx #(MAC_BW) ffoutnob (rxclk, rxrst_, bvld_cnt, out_nob);
always @(posedge rxclk or negedge rxrst_)
    begin
    if (!rxrst_)      out_dat <= {(MAC_DW){1'b0}};
    else if (shift_out)
        begin
        case (bvld_cnt)
            VLD_1B: out_dat <= {rx_idat, {SHIFT_DW{1'b0}}};
            VLD_2B: out_dat <= {shift_dat [1*DAT_DW-1:0], rx_idat, {2*DAT_DW{1'b0}}};
            VLD_3B: out_dat <= {shift_dat [2*DAT_DW-1:0], rx_idat, {1*DAT_DW{1'b0}}};
            VLD_4B: out_dat <= {shift_dat, rx_idat};
            default:out_dat <= {shift_dat, rx_idat};
        endcase
        end
    end









fflopx #(1) ovld (rxclk, rxrst_, shift_out, out_vld);
fflopx #(1) oeop (rxclk, rxrst_, rx_ieop, out_eop);
fflopx #(1) osop (rxclk, rxrst_, (shift_out & shift_sop), out_sop);
fflopx #(DAT_EW) oerr (rxclk, rxrst_, (rx_ieop ? rx_ierr : shift_err), out_err);

endmodule
module ipsmacge_rxshift
    (
     rxclk,
     rxrst_,

     rx_idat, 
     rx_isop,  
     rx_ieop,  
     rx_ivld,  
     rx_ierr,

     out_dat,
     out_nob,
     out_sop,  
     out_eop,  
     out_vld,  
     out_err
     );




parameter DAT_DW = 8;
parameter DAT_EW = 4;

parameter MAC_DW = 32;
parameter MAC_BW = 2;

parameter SHIFT_DW = MAC_DW - DAT_DW;
parameter VLD_1B = 2'h0,
          VLD_2B = 2'h1,
          VLD_3B = 2'h2,
          VLD_4B = 2'h3;


input     rxrst_;
input     rxclk;

input  [DAT_DW-1:0] rx_idat;
input               rx_ivld;
input               rx_isop;
input               rx_ieop;
input  [DAT_EW-1:0] rx_ierr;

output [MAC_DW-1:0] out_dat;
output [MAC_BW-1:0] out_nob;

output              out_vld;
output              out_sop;
output              out_eop;
output [DAT_EW-1:0] out_err;



reg  [MAC_DW-1:0]   out_dat;
wire [MAC_BW-1:0]   out_nob;

reg [MAC_BW-1:0]    bvld_cnt;
reg [SHIFT_DW-1:0]  shift_dat;
reg                 shift_sop;
reg [DAT_EW-1:0]    shift_err;
wire                shift_out;







always @(posedge rxclk or negedge rxrst_)
    begin
    if (!rxrst_)            bvld_cnt <= {(MAC_BW){1'b0}};
    else if (rx_ivld)
        begin
        if (rx_isop)        bvld_cnt <= {(MAC_BW){1'b0}} + 1'b1;
        else if (shift_out) bvld_cnt <= {(MAC_BW){1'b0}};
        else                bvld_cnt <= bvld_cnt + 1'b1;
        end
    end

integer i;

always @(posedge rxclk or negedge rxrst_)
    begin
    if (!rxrst_)
        begin
        shift_sop <= 1'b0;
        shift_err <= {DAT_EW{1'b0}};
        end
    else if (rx_ivld)
        begin
        if (rx_isop)         shift_sop <= 1'b1;
        else if (shift_out)  shift_sop <= 1'b0;
        else                 shift_sop <= shift_sop;

        if (rx_isop)         shift_err <= rx_ierr;
        else if (shift_out)  shift_err <= rx_ierr;
        else
            begin
            for (i = 0; i < DAT_EW; i = i + 1)
                shift_err [i] <= rx_ierr [i] ? 1'b1 : shift_err [i];
            end
        end
    end

always @(posedge rxclk or negedge rxrst_)
    begin
    if (!rxrst_)        shift_dat <= {SHIFT_DW{1'b0}};
    else if (rx_ivld)   shift_dat <= {shift_dat [SHIFT_DW-DAT_DW-1:0], rx_idat};
    end



assign shift_out = rx_ivld & (rx_ieop | (bvld_cnt == {MAC_BW{1'b1}}));

fflopx #(MAC_BW) ffoutnob (rxclk, rxrst_, bvld_cnt, out_nob);
always @(posedge rxclk or negedge rxrst_)
    begin
    if (!rxrst_)      out_dat <= {(MAC_DW){1'b0}};
    else if (shift_out)
        begin
        case (bvld_cnt)
            VLD_1B: out_dat <= {rx_idat, {SHIFT_DW{1'b0}}};
            VLD_2B: out_dat <= {shift_dat [1*DAT_DW-1:0], rx_idat, {2*DAT_DW{1'b0}}};
            VLD_3B: out_dat <= {shift_dat [2*DAT_DW-1:0], rx_idat, {1*DAT_DW{1'b0}}};
            VLD_4B: out_dat <= {shift_dat, rx_idat};
            default:out_dat <= {shift_dat, rx_idat};
        endcase
        end
    end









fflopx #(1) ovld (rxclk, rxrst_, shift_out, out_vld);
fflopx #(1) oeop (rxclk, rxrst_, rx_ieop, out_eop);
fflopx #(1) osop (rxclk, rxrst_, (shift_out & shift_sop), out_sop);
fflopx #(DAT_EW) oerr (rxclk, rxrst_, (rx_ieop ? rx_ierr : shift_err), out_err);

endmodule