data/full_repos/permissive/486216880/main.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/486216880/main.v:23: Unsupported: Ignoring delay on this delayed statement.\n  always begin #5 clk = ~clk; end\n               ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/486216880/main.v:33: Cannot find file containing module: \'core\'\n  core #(.RAM_DEPTH(RAM_DEPTH)) \n  ^~~~\n        ... Looked in:\n             data/full_repos/permissive/486216880,data/full_repos/permissive/486216880/core\n             data/full_repos/permissive/486216880,data/full_repos/permissive/486216880/core.v\n             data/full_repos/permissive/486216880,data/full_repos/permissive/486216880/core.sv\n             core\n             core.v\n             core.sv\n             obj_dir/core\n             obj_dir/core.v\n             obj_dir/core.sv\n%Error: data/full_repos/permissive/486216880/main.v:45: Cannot find file containing module: \'ROM\'\n  ROM inst_rom(\n  ^~~\n%Error: data/full_repos/permissive/486216880/main.v:51: Cannot find file containing module: \'RAM\'\n  RAM #(.RAM_DEPTH(RAM_DEPTH))\n  ^~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main(


  );
  



function integer clogb2;
input integer depth;
	for (clogb2=0; depth>0; clogb2=clogb2+1)
		depth = depth >> 1;
endfunction


  reg clk = 0;
  reg reset = 0;
  
  localparam RAM_DEPTH = 16;

  always begin #5 clk = ~clk; end

  wire [31:0] inst_rom_addr;
  wire [31:0] instruction;

  wire [clogb2(RAM_DEPTH-1)-1:0] data_ram_addr;
  wire [31:0] data_ram_in_from_cpu;
  wire data_ram_we;
  wire [31:0] data_ram_out_to_cpu;

  core #(.RAM_DEPTH(RAM_DEPTH)) 
	cpu(
         .inst_rom_addr_o(inst_rom_addr),
         .instruction_i(instruction),
         .clk(clk),
         .data_ram_addr_o(data_ram_addr),
         .data_ram_i(data_ram_out_to_cpu),
         .data_ram_we_reg_o(data_ram_we),
         .data_ram_o(data_ram_in_from_cpu),
         .reset_i(reset)
       );

  ROM inst_rom(
        .clk(clk),
        .address_i(inst_rom_addr),
        .data_o(instruction)
      );

  RAM #(.RAM_DEPTH(RAM_DEPTH))
	data_ram(
        .address_i(data_ram_addr),
        .data_i(data_ram_in_from_cpu),
        .we_i(data_ram_we),
        .clk(clk),
        .reset_i(reset),
        .data_o(data_ram_out_to_cpu)
      );

endmodule
module main(


  );

  



function integer clogb2;
input integer depth;
	for (clogb2=0; depth>0; clogb2=clogb2+1)
		depth = depth >> 1;
endfunction


  reg clk = 0;
  reg reset = 0;
  
  localparam RAM_DEPTH = 16;

  always begin #5 clk = ~clk; end

  wire [31:0] inst_rom_addr;
  wire [31:0] instruction;

  wire [clogb2(RAM_DEPTH-1)-1:0] data_ram_addr;
  wire [31:0] data_ram_in_from_cpu;
  wire data_ram_we;
  wire [31:0] data_ram_out_to_cpu;

  core #(.RAM_DEPTH(RAM_DEPTH)) 
	cpu(
         .inst_rom_addr_o(inst_rom_addr),
         .instruction_i(instruction),
         .clk(clk),
         .data_ram_addr_o(data_ram_addr),
         .data_ram_i(data_ram_out_to_cpu),
         .data_ram_we_reg_o(data_ram_we),
         .data_ram_o(data_ram_in_from_cpu),
         .reset_i(reset)
       );

  ROM inst_rom(
        .clk(clk),
        .address_i(inst_rom_addr),
        .data_o(instruction)
      );

  RAM #(.RAM_DEPTH(RAM_DEPTH))
	data_ram(
        .address_i(data_ram_addr),
        .data_i(data_ram_in_from_cpu),
        .we_i(data_ram_we),
        .clk(clk),
        .reset_i(reset),
        .data_o(data_ram_out_to_cpu)
      );

endmodule