data/full_repos/permissive/493019833/test/testcase/firrtl/RealAdder.lo/reference/RealAdder.lo.v
1: b"%Error: data/full_repos/permissive/493019833/test/testcase/firrtl/RealAdder.lo/reference/RealAdder.lo.v:18: Cannot find file containing module: 'BBFAdd'\n    BBFAdd BBFAdd (\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/493019833/test/testcase/firrtl/RealAdder.lo/reference,data/full_repos/permissive/493019833/BBFAdd\n             data/full_repos/permissive/493019833/test/testcase/firrtl/RealAdder.lo/reference,data/full_repos/permissive/493019833/BBFAdd.v\n             data/full_repos/permissive/493019833/test/testcase/firrtl/RealAdder.lo/reference,data/full_repos/permissive/493019833/BBFAdd.sv\n             BBFAdd\n             BBFAdd.v\n             BBFAdd.sv\n             obj_dir/BBFAdd\n             obj_dir/BBFAdd.v\n             obj_dir/BBFAdd.sv\n%Error: Exiting due to 1 error(s)\n"
module RealAdder(
    input clock,
    input reset,
    input [63:0] io_a1_node,
    input [63:0] io_a2_node,
    output [63:0] io_c_node
);
    wire [63:0] _register1_node__q;
    wire [63:0] _register1_node__d;
    DFF_POSCLK #(.width(64)) register1_node (
        .q(_register1_node__q),
        .d(_register1_node__d),
        .clk(clock)
    );
    wire [63:0] _BBFAdd__out;
    wire [63:0] _BBFAdd__in2;
    wire [63:0] _BBFAdd__in1;
    BBFAdd BBFAdd (
        .out(_BBFAdd__out),
        .in2(_BBFAdd__in2),
        .in1(_BBFAdd__in1)
    );
    wire [63:0] _T_16_node;
    assign _BBFAdd__in1 = io_a1_node;
    assign _BBFAdd__in2 = io_a2_node;
    assign _T_16_node = _BBFAdd__out;
    assign io_c_node = _register1_node__q;
    assign _register1_node__d = _T_16_node;
endmodule
module RealAdder(
    input clock,
    input reset,
    input [63:0] io_a1_node,
    input [63:0] io_a2_node,
    output [63:0] io_c_node
);

    wire [63:0] _register1_node__q;
    wire [63:0] _register1_node__d;
    DFF_POSCLK #(.width(64)) register1_node (
        .q(_register1_node__q),
        .d(_register1_node__d),
        .clk(clock)
    );
    wire [63:0] _BBFAdd__out;
    wire [63:0] _BBFAdd__in2;
    wire [63:0] _BBFAdd__in1;
    BBFAdd BBFAdd (
        .out(_BBFAdd__out),
        .in2(_BBFAdd__in2),
        .in1(_BBFAdd__in1)
    );
    wire [63:0] _T_16_node;
    assign _BBFAdd__in1 = io_a1_node;
    assign _BBFAdd__in2 = io_a2_node;
    assign _T_16_node = _BBFAdd__out;
    assign io_c_node = _register1_node__q;
    assign _register1_node__d = _T_16_node;
endmodule