data/full_repos/permissive/454159683/alu44/alu44.v
1: b'%Warning-WIDTH: data/full_repos/permissive/454159683/alu44/alu44.v:8: Operator OR expects 5 bits on the LHS, but LHS\'s VARREF \'a\' generates 4 bits.\n                                                                    : ... In instance alu44\n assign or_op = a | b;\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/454159683/alu44/alu44.v:8: Operator OR expects 5 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n                                                                    : ... In instance alu44\n assign or_op = a | b;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/454159683/alu44/alu44.v:9: Operator AND expects 5 bits on the LHS, but LHS\'s VARREF \'a\' generates 4 bits.\n                                                                    : ... In instance alu44\n assign and_op = a & b;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/454159683/alu44/alu44.v:9: Operator AND expects 5 bits on the RHS, but RHS\'s VARREF \'b\' generates 4 bits.\n                                                                    : ... In instance alu44\n assign and_op = a & b;\n                   ^\n%Error: Exiting due to 4 warning(s)\n'
module alu44(input[1:0] ope, input[3:0] a, b, output reg[4:0] out);
	wire[4:0] or_op, and_op, not_op, plus_op;
	assign or_op = a | b;
	assign and_op = a & b;
	assign not_op = ~{1'b1, a};
	assign plus_op = a + b;
	
	always @(*)
	begin
		case(ope)
			0: out = or_op;
			1: out = and_op;
			2: out = not_op;
			3: out = plus_op;
		endcase
	end

endmodule
module alu44(input[1:0] ope, input[3:0] a, b, output reg[4:0] out);

	wire[4:0] or_op, and_op, not_op, plus_op;
	assign or_op = a | b;
	assign and_op = a & b;
	assign not_op = ~{1'b1, a};
	assign plus_op = a + b;
	
	always @(*)
	begin
		case(ope)
			0: out = or_op;
			1: out = and_op;
			2: out = not_op;
			3: out = plus_op;
		endcase
	end

endmodule