data/full_repos/permissive/472097485/Chu04/Stack_07/Stack.v
data/verilator_xmls/6e465fc6-a800-47ce-a33c-d40295cbf6f1.xml
module Stack #( parameter DATA_BITS=8, ADDRESS_BITS=4 )( input wire clk, reset, input wire push, pop, input wire [DATA_BITS-1:0] w_data
	, output wire empty, full, output wire [DATA_BITS-1:0] r_data );


   reg [DATA_BITS-1:0] stack [2**ADDRESS_BITS-1:0];
   reg [ADDRESS_BITS-1:0] top;
	reg isFull;
	
	wire [DATA_BITS-1:0] top_value;
	

	reg [ADDRESS_BITS-1:0] next_top;
	reg nextFull;
	reg [DATA_BITS-1:0] next;
	



	always @( posedge clk, posedge reset )
	begin
		if( reset )
		begin
			top = 0;
			isFull = 1'b0;
		end
		else if( push )
		begin
			top = next_top;
			stack[ next_top - 1 ] = next;
			isFull = nextFull;
		end
		else if ( pop )
		begin
			top = next_top;
			isFull = nextFull;
		end	
	end


	assign top_value = stack[ top - 1 ];


   always @*
   begin

		next_top = top;
		next = top_value;
		nextFull = isFull;
      case ( { push, pop } )

         2'b01:
				begin
					if ( top != 0 || isFull )
						next_top = top - 1;
					nextFull = 1'b0;
				end
         2'b10:
            if ( ~isFull )
               begin
						next_top = top + 1;
						next = w_data;
						nextFull = next_top == 0;
					end
         2'b11:
            begin
					next = w_data;
            end
      endcase
   end
	

	assign empty = top == 0 && !isFull;
	assign full = isFull;
	assign r_data = stack[top - 1];

endmodule
module Stack #( parameter DATA_BITS=8, ADDRESS_BITS=4 )( input wire clk, reset, input wire push, pop, input wire [DATA_BITS-1:0] w_data
	, output wire empty, full, output wire [DATA_BITS-1:0] r_data );



   reg [DATA_BITS-1:0] stack [2**ADDRESS_BITS-1:0];
   reg [ADDRESS_BITS-1:0] top;
	reg isFull;
	
	wire [DATA_BITS-1:0] top_value;
	

	reg [ADDRESS_BITS-1:0] next_top;
	reg nextFull;
	reg [DATA_BITS-1:0] next;
	



	always @( posedge clk, posedge reset )
	begin
		if( reset )
		begin
			top = 0;
			isFull = 1'b0;
		end
		else if( push )
		begin
			top = next_top;
			stack[ next_top - 1 ] = next;
			isFull = nextFull;
		end
		else if ( pop )
		begin
			top = next_top;
			isFull = nextFull;
		end	
	end


	assign top_value = stack[ top - 1 ];


   always @*
   begin

		next_top = top;
		next = top_value;
		nextFull = isFull;
      case ( { push, pop } )

         2'b01:
				begin
					if ( top != 0 || isFull )
						next_top = top - 1;
					nextFull = 1'b0;
				end
         2'b10:
            if ( ~isFull )
               begin
						next_top = top + 1;
						next = w_data;
						nextFull = next_top == 0;
					end
         2'b11:
            begin
					next = w_data;
            end
      endcase
   end
	

	assign empty = top == 0 && !isFull;
	assign full = isFull;
	assign r_data = stack[top - 1];

endmodule