data/full_repos/permissive/422139337/src/hdmi_device.v
1: b'%Error: data/full_repos/permissive/422139337/src/hdmi_device.v:46: Cannot find file containing module: \'tmds_encoder\'\ntmds_encoder tmsds_encoder_i0(pclk, ~in_vga_blank, in_vga_red,   0,          0,              tmds_red);\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/422139337/src,data/full_repos/permissive/422139337/tmds_encoder\n             data/full_repos/permissive/422139337/src,data/full_repos/permissive/422139337/tmds_encoder.v\n             data/full_repos/permissive/422139337/src,data/full_repos/permissive/422139337/tmds_encoder.sv\n             tmds_encoder\n             tmds_encoder.v\n             tmds_encoder.sv\n             obj_dir/tmds_encoder\n             obj_dir/tmds_encoder.v\n             obj_dir/tmds_encoder.sv\n%Error: data/full_repos/permissive/422139337/src/hdmi_device.v:47: Cannot find file containing module: \'tmds_encoder\'\ntmds_encoder tmsds_encoder_i1(pclk, ~in_vga_blank, in_vga_green, 0,          0,              tmds_green);\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/422139337/src/hdmi_device.v:48: Cannot find file containing module: \'tmds_encoder\'\ntmds_encoder tmsds_encoder_i2(pclk, ~in_vga_blank, in_vga_blue,  in_vga_vsync, in_vga_hsync, tmds_blue);\n^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/422139337/src/hdmi_device.v:66: Operator COND expects 2 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                         : ... In instance hdmi_device\n    tmds_shift_red    <= tmds_shift_load ? tmds_red       : {DDR_ENABLED ? 2\'b00 : 1\'b0, tmds_shift_red   [9: DDR_ENABLED ? 2 : 1]};\n                                                                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/422139337/src/hdmi_device.v:66: Operator COND expects 11 bits on the Conditional True, but Conditional True\'s VARREF \'tmds_red\' generates 10 bits.\n                                                                         : ... In instance hdmi_device\n    tmds_shift_red    <= tmds_shift_load ? tmds_red       : {DDR_ENABLED ? 2\'b00 : 1\'b0, tmds_shift_red   [9: DDR_ENABLED ? 2 : 1]};\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/422139337/src/hdmi_device.v:66: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s COND generates 11 bits.\n                                                                         : ... In instance hdmi_device\n    tmds_shift_red    <= tmds_shift_load ? tmds_red       : {DDR_ENABLED ? 2\'b00 : 1\'b0, tmds_shift_red   [9: DDR_ENABLED ? 2 : 1]};\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/422139337/src/hdmi_device.v:67: Operator COND expects 2 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                         : ... In instance hdmi_device\n    tmds_shift_green  <= tmds_shift_load ? tmds_green     : {DDR_ENABLED ? 2\'b00 : 1\'b0, tmds_shift_green [9: DDR_ENABLED ? 2 : 1]};\n                                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/422139337/src/hdmi_device.v:67: Operator COND expects 11 bits on the Conditional True, but Conditional True\'s VARREF \'tmds_green\' generates 10 bits.\n                                                                         : ... In instance hdmi_device\n    tmds_shift_green  <= tmds_shift_load ? tmds_green     : {DDR_ENABLED ? 2\'b00 : 1\'b0, tmds_shift_green [9: DDR_ENABLED ? 2 : 1]};\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/422139337/src/hdmi_device.v:67: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s COND generates 11 bits.\n                                                                         : ... In instance hdmi_device\n    tmds_shift_green  <= tmds_shift_load ? tmds_green     : {DDR_ENABLED ? 2\'b00 : 1\'b0, tmds_shift_green [9: DDR_ENABLED ? 2 : 1]};\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/422139337/src/hdmi_device.v:68: Operator COND expects 2 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                         : ... In instance hdmi_device\n    tmds_shift_blue   <= tmds_shift_load ? tmds_blue      : {DDR_ENABLED ? 2\'b00 : 1\'b0, tmds_shift_blue  [9: DDR_ENABLED ? 2 : 1]};\n                                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/422139337/src/hdmi_device.v:68: Operator COND expects 11 bits on the Conditional True, but Conditional True\'s VARREF \'tmds_blue\' generates 10 bits.\n                                                                         : ... In instance hdmi_device\n    tmds_shift_blue   <= tmds_shift_load ? tmds_blue      : {DDR_ENABLED ? 2\'b00 : 1\'b0, tmds_shift_blue  [9: DDR_ENABLED ? 2 : 1]};\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/422139337/src/hdmi_device.v:68: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s COND generates 11 bits.\n                                                                         : ... In instance hdmi_device\n    tmds_shift_blue   <= tmds_shift_load ? tmds_blue      : {DDR_ENABLED ? 2\'b00 : 1\'b0, tmds_shift_blue  [9: DDR_ENABLED ? 2 : 1]};\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/422139337/src/hdmi_device.v:69: Operator COND expects 2 bits on the Conditional False, but Conditional False\'s CONST \'1\'h0\' generates 1 bits.\n                                                                         : ... In instance hdmi_device\n    tmds_shift_clk    <= tmds_shift_load ? tmds_pixel_clk : {DDR_ENABLED ? 2\'b00 : 1\'b0, tmds_shift_clk   [9: DDR_ENABLED ? 2 : 1]};\n                                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/422139337/src/hdmi_device.v:69: Operator COND expects 11 bits on the Conditional True, but Conditional True\'s VARREF \'tmds_pixel_clk\' generates 10 bits.\n                                                                         : ... In instance hdmi_device\n    tmds_shift_clk    <= tmds_shift_load ? tmds_pixel_clk : {DDR_ENABLED ? 2\'b00 : 1\'b0, tmds_shift_clk   [9: DDR_ENABLED ? 2 : 1]};\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/422139337/src/hdmi_device.v:69: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s COND generates 11 bits.\n                                                                         : ... In instance hdmi_device\n    tmds_shift_clk    <= tmds_shift_load ? tmds_pixel_clk : {DDR_ENABLED ? 2\'b00 : 1\'b0, tmds_shift_clk   [9: DDR_ENABLED ? 2 : 1]};\n                      ^~\n%Error: Exiting due to 3 error(s), 12 warning(s)\n'
module hdmi_device
	#(parameter DDR_ENABLED = 0)

	(
           input pclk,
           input tmds_clk,

           input [7:0] in_vga_red,
           input [7:0] in_vga_green,
           input [7:0] in_vga_blue,

           input in_vga_blank,
           input in_vga_vsync,
           input in_vga_hsync,

           output [DDR_ENABLED:0] out_tmds_red,
           output [DDR_ENABLED:0] out_tmds_green,
           output [DDR_ENABLED:0] out_tmds_blue,
           output [DDR_ENABLED:0] out_tmds_clk
       );


localparam OUT_TMDS_MSB = DDR_ENABLED ? 1 : 0;


wire [9:0] tmds_red;
wire [9:0] tmds_green;
wire [9:0] tmds_blue;
tmds_encoder tmsds_encoder_i0(pclk, ~in_vga_blank, in_vga_red,   0,          0,              tmds_red);
tmds_encoder tmsds_encoder_i1(pclk, ~in_vga_blank, in_vga_green, 0,          0,              tmds_green);
tmds_encoder tmsds_encoder_i2(pclk, ~in_vga_blank, in_vga_blue,  in_vga_vsync, in_vga_hsync, tmds_blue);


reg       tmds_shift_load   = 0;
reg [3:0] tmds_modulo       = 0;
reg [9:0] tmds_shift_red    = 0;
reg [9:0] tmds_shift_green  = 0;
reg [9:0] tmds_shift_blue   = 0;
reg [9:0] tmds_shift_clk    = 0;

wire [9:0] tmds_pixel_clk = 10'b00000_11111;


wire max_shifts_reached = tmds_modulo == (DDR_ENABLED ? 4 : 9);
always @(posedge tmds_clk) tmds_modulo      <= max_shifts_reached ? 0 : tmds_modulo + 1;
always @(posedge tmds_clk) tmds_shift_load  <= max_shifts_reached;

always @(posedge tmds_clk) begin
    tmds_shift_red    <= tmds_shift_load ? tmds_red       : {DDR_ENABLED ? 2'b00 : 1'b0, tmds_shift_red   [9: DDR_ENABLED ? 2 : 1]};
    tmds_shift_green  <= tmds_shift_load ? tmds_green     : {DDR_ENABLED ? 2'b00 : 1'b0, tmds_shift_green [9: DDR_ENABLED ? 2 : 1]};
    tmds_shift_blue   <= tmds_shift_load ? tmds_blue      : {DDR_ENABLED ? 2'b00 : 1'b0, tmds_shift_blue  [9: DDR_ENABLED ? 2 : 1]};
    tmds_shift_clk    <= tmds_shift_load ? tmds_pixel_clk : {DDR_ENABLED ? 2'b00 : 1'b0, tmds_shift_clk   [9: DDR_ENABLED ? 2 : 1]};
end

assign out_tmds_clk   = tmds_shift_clk    [ OUT_TMDS_MSB : 0 ];
assign out_tmds_red   = tmds_shift_red    [ OUT_TMDS_MSB : 0 ];
assign out_tmds_green = tmds_shift_green  [ OUT_TMDS_MSB : 0 ];
assign out_tmds_blue  = tmds_shift_blue   [ OUT_TMDS_MSB : 0 ];

endmodule
module hdmi_device
	#(parameter DDR_ENABLED = 0)

	(
           input pclk,
           input tmds_clk,

           input [7:0] in_vga_red,
           input [7:0] in_vga_green,
           input [7:0] in_vga_blue,

           input in_vga_blank,
           input in_vga_vsync,
           input in_vga_hsync,

           output [DDR_ENABLED:0] out_tmds_red,
           output [DDR_ENABLED:0] out_tmds_green,
           output [DDR_ENABLED:0] out_tmds_blue,
           output [DDR_ENABLED:0] out_tmds_clk
       );



localparam OUT_TMDS_MSB = DDR_ENABLED ? 1 : 0;


wire [9:0] tmds_red;
wire [9:0] tmds_green;
wire [9:0] tmds_blue;
tmds_encoder tmsds_encoder_i0(pclk, ~in_vga_blank, in_vga_red,   0,          0,              tmds_red);
tmds_encoder tmsds_encoder_i1(pclk, ~in_vga_blank, in_vga_green, 0,          0,              tmds_green);
tmds_encoder tmsds_encoder_i2(pclk, ~in_vga_blank, in_vga_blue,  in_vga_vsync, in_vga_hsync, tmds_blue);


reg       tmds_shift_load   = 0;
reg [3:0] tmds_modulo       = 0;
reg [9:0] tmds_shift_red    = 0;
reg [9:0] tmds_shift_green  = 0;
reg [9:0] tmds_shift_blue   = 0;
reg [9:0] tmds_shift_clk    = 0;

wire [9:0] tmds_pixel_clk = 10'b00000_11111;


wire max_shifts_reached = tmds_modulo == (DDR_ENABLED ? 4 : 9);
always @(posedge tmds_clk) tmds_modulo      <= max_shifts_reached ? 0 : tmds_modulo + 1;
always @(posedge tmds_clk) tmds_shift_load  <= max_shifts_reached;

always @(posedge tmds_clk) begin
    tmds_shift_red    <= tmds_shift_load ? tmds_red       : {DDR_ENABLED ? 2'b00 : 1'b0, tmds_shift_red   [9: DDR_ENABLED ? 2 : 1]};
    tmds_shift_green  <= tmds_shift_load ? tmds_green     : {DDR_ENABLED ? 2'b00 : 1'b0, tmds_shift_green [9: DDR_ENABLED ? 2 : 1]};
    tmds_shift_blue   <= tmds_shift_load ? tmds_blue      : {DDR_ENABLED ? 2'b00 : 1'b0, tmds_shift_blue  [9: DDR_ENABLED ? 2 : 1]};
    tmds_shift_clk    <= tmds_shift_load ? tmds_pixel_clk : {DDR_ENABLED ? 2'b00 : 1'b0, tmds_shift_clk   [9: DDR_ENABLED ? 2 : 1]};
end

assign out_tmds_clk   = tmds_shift_clk    [ OUT_TMDS_MSB : 0 ];
assign out_tmds_red   = tmds_shift_red    [ OUT_TMDS_MSB : 0 ];
assign out_tmds_green = tmds_shift_green  [ OUT_TMDS_MSB : 0 ];
assign out_tmds_blue  = tmds_shift_blue   [ OUT_TMDS_MSB : 0 ];

endmodule