data/full_repos/permissive/447976230/fpga/usrp2/opencores/i2c/bench/verilog/spi_slave_model.v
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/i2c/bench/verilog/spi_slave_model.v:57: Cannot find include file: timescale.v\n`include "timescale.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp2/opencores/i2c/bench/verilog,data/full_repos/permissive/447976230/timescale.v\n             data/full_repos/permissive/447976230/fpga/usrp2/opencores/i2c/bench/verilog,data/full_repos/permissive/447976230/timescale.v.v\n             data/full_repos/permissive/447976230/fpga/usrp2/opencores/i2c/bench/verilog,data/full_repos/permissive/447976230/timescale.v.sv\n             timescale.v\n             timescale.v.v\n             timescale.v.sv\n             obj_dir/timescale.v\n             obj_dir/timescale.v.v\n             obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/i2c/bench/verilog/spi_slave_model.v:60: syntax error, unexpected \';\', expecting \')\' or \',\'\n input  wire csn;\n                ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/i2c/bench/verilog/spi_slave_model.v:63: syntax error, unexpected output\n output wire do\n ^~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/i2c/bench/verilog/spi_slave_model.v:63: Unexpected \'do\': \'do\' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n output wire do\n             ^~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/opencores/i2c/bench/verilog/spi_slave_model.v:89: syntax error, unexpected assign\n assign clk = cpol ^ cpha ^ sck;\n ^~~~~~\n%Error: Exiting due to 5 error(s)\n'
module spi_slave_model (
	input  wire csn;
	input  wire sck
	input  wire di;
	output wire do
);




	wire debug = 1'b1;

	wire cpol = 1'b0;
	wire cpha  = 1'b0;

	reg [7:0] mem [7:0];
	reg [2:0] mem_adr;
	reg [7:0] mem_do;

	reg [7:0] sri, sro;

	reg [2:0] bit_cnt;
	reg       ld;

	wire clk;





	assign clk = cpol ^ cpha ^ sck;


	always @(posedge clk)
	  sri <= #1 {sri[6:0],di};

	always @(posedge clk)
	  if (&bit_cnt)
	    sro <= #1 mem[mem_adr];
	  else
	    sro <= #1 {sro[6:0],1'bx};

	assign do = sro[7];


	always @(posedge clk, posedge csn)
	  if(csn)
	    bit_cnt <= #1 3'b111;
	  else
	    bit_cnt <= #1 bit_cnt - 3'h1;


        always @(posedge clk)
	  ld <= #1 ~(|bit_cnt);

	always @(negedge clk)
          if (ld) begin
	    mem[mem_adr] <= #1 sri;
	    mem_adr      <= #1 mem_adr + 1'b1;
	  end

	initial
	begin
	  bit_cnt=3'b111;
	  mem_adr = 0;
	  sro = mem[mem_adr];
	end
endmodule
module spi_slave_model (
	input  wire csn;

	input  wire sck
	input  wire di;
	output wire do
);




	wire debug = 1'b1;

	wire cpol = 1'b0;
	wire cpha  = 1'b0;

	reg [7:0] mem [7:0];
	reg [2:0] mem_adr;
	reg [7:0] mem_do;

	reg [7:0] sri, sro;

	reg [2:0] bit_cnt;
	reg       ld;

	wire clk;





	assign clk = cpol ^ cpha ^ sck;


	always @(posedge clk)
	  sri <= #1 {sri[6:0],di};

	always @(posedge clk)
	  if (&bit_cnt)
	    sro <= #1 mem[mem_adr];
	  else
	    sro <= #1 {sro[6:0],1'bx};

	assign do = sro[7];


	always @(posedge clk, posedge csn)
	  if(csn)
	    bit_cnt <= #1 3'b111;
	  else
	    bit_cnt <= #1 bit_cnt - 3'h1;


        always @(posedge clk)
	  ld <= #1 ~(|bit_cnt);

	always @(negedge clk)
          if (ld) begin
	    mem[mem_adr] <= #1 sri;
	    mem_adr      <= #1 mem_adr + 1'b1;
	  end

	initial
	begin
	  bit_cnt=3'b111;
	  mem_adr = 0;
	  sro = mem[mem_adr];
	end
endmodule