data/full_repos/permissive/515641908/U_S_R_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/515641908/U_S_R_testbench.v:12: Unsupported: Ignoring delay on this delayed statement.\n    reset = 1; #10; reset = 0; #10;\n               ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/515641908/U_S_R_testbench.v:12: Unsupported: Ignoring delay on this delayed statement.\n    reset = 1; #10; reset = 0; #10;\n                               ^\n%Warning-STMTDLY: data/full_repos/permissive/515641908/U_S_R_testbench.v:16: Unsupported: Ignoring delay on this delayed statement.\n    MODE = 2\'b00; reset = 1; #10; reset = 0; #10;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/515641908/U_S_R_testbench.v:16: Unsupported: Ignoring delay on this delayed statement.\n    MODE = 2\'b00; reset = 1; #10; reset = 0; #10;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/515641908/U_S_R_testbench.v:17: Unsupported: Ignoring delay on this delayed statement.\n    MODE = 2\'b01; DataIn = 4\'b0011; #10;\n                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/515641908/U_S_R_testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n    MODE = 2\'b01; DataIn = 4\'b0011; #10;\n                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/515641908/U_S_R_testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n    MODE = 2\'b00; reset = 1; #10; reset = 0; #10;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/515641908/U_S_R_testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n    MODE = 2\'b00; reset = 1; #10; reset = 0; #10;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/515641908/U_S_R_testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n    MODE = 2\'b10; DataIn = 4\'b0111; #10;\n                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/515641908/U_S_R_testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n    MODE = 2\'b10; DataIn = 4\'b0111; #10;\n                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/515641908/U_S_R_testbench.v:45: Unsupported: Ignoring delay on this delayed statement.\n    MODE = 2\'b00; reset = 1; #10; reset = 0; #10;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/515641908/U_S_R_testbench.v:45: Unsupported: Ignoring delay on this delayed statement.\n    MODE = 2\'b00; reset = 1; #10; reset = 0; #10;\n                                             ^\n%Warning-STMTDLY: data/full_repos/permissive/515641908/U_S_R_testbench.v:46: Unsupported: Ignoring delay on this delayed statement.\n    MODE = 2\'b11; DataIn = 4\'b1010; #10;\n                                    ^\n%Warning-STMTDLY: data/full_repos/permissive/515641908/U_S_R_testbench.v:52: Unsupported: Ignoring delay on this delayed statement.\n    #20;\n    ^\n%Error: data/full_repos/permissive/515641908/U_S_R_testbench.v:59: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("dump.vcd"); $dumpvars;\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/515641908/U_S_R_testbench.v:59: Unsupported or unknown PLI call: $dumpvars\n    $dumpfile("dump.vcd"); $dumpvars;\n                           ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/515641908/U_S_R_testbench.v:63: Unsupported: Ignoring delay on this delayed statement.\n  always #5 clock = ~clock;\n         ^\n%Error: Exiting due to 2 error(s), 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Universal_Shift_RegisterTb;
  wire [3:0] DataOut;
  reg clock, reset;
  reg [1:0] MODE;
  reg [3:0] DataIn;
  
  Universal_Shift_Register jusr(DataOut, clock, reset, MODE, DataIn);
  
  initial
  begin
    clock =0; MODE = 2'b00; DataIn = 4'b0000;
    reset = 1; #10; reset = 0; #10;
    
    $display("RSLT\tD == DOUT");
    
    MODE = 2'b00; reset = 1; #10; reset = 0; #10;
    MODE = 2'b01; DataIn = 4'b0011; #10;
    if ( DataOut === 4'b1000 )
      $display("PASS\t%p is %p with %p", DataIn, MODE, DataOut);
    else
      $display("FAIL\t%p is %p with %p", DataIn, MODE, DataOut);
    MODE = 2'b01; DataIn = 4'b0011; #10;
    if ( DataOut === 4'b1100 ) 
      $display("PASS\t%p is %p with %p", DataIn, MODE, DataOut);
    else
      $display("FAIL\t%p is %p with %p", DataIn, MODE, DataOut);
    
    
    
    MODE = 2'b00; reset = 1; #10; reset = 0; #10;
    MODE = 2'b10; DataIn = 4'b0111; #10;
    if ( DataOut === 4'b0001 ) 
      $display("PASS\t%p is %p with %p", DataIn, MODE, DataOut);
    else
      $display("FAIL\t%p is %p with %p", DataIn, MODE, DataOut);
    
    MODE = 2'b10; DataIn = 4'b0111; #10;
    if ( DataOut === 4'b0011 )
      $display("PASS\t%p is %p with %p", DataIn, MODE, DataOut);
    else
      $display("FAIL\t%p is %p with %p", DataIn, MODE, DataOut);


    
    MODE = 2'b00; reset = 1; #10; reset = 0; #10;
    MODE = 2'b11; DataIn = 4'b1010; #10;
    if ( DataOut === 4'b1010 )
      $display("PASS\t%p is %p with %p", DataIn, MODE, DataOut);
    else
      $display("FAIL\t%p is %p with %p", DataIn, MODE, DataOut);

    #20;
    $finish;
  end
  
    
 
  initial begin 
    $dumpfile("dump.vcd"); $dumpvars;
  end

  
  always #5 clock = ~clock;
  
endmodule
module Universal_Shift_RegisterTb;

  wire [3:0] DataOut;
  reg clock, reset;
  reg [1:0] MODE;
  reg [3:0] DataIn;
  
  Universal_Shift_Register jusr(DataOut, clock, reset, MODE, DataIn);
  
  initial
  begin
    clock =0; MODE = 2'b00; DataIn = 4'b0000;
    reset = 1; #10; reset = 0; #10;
    
    $display("RSLT\tD == DOUT");
    
    MODE = 2'b00; reset = 1; #10; reset = 0; #10;
    MODE = 2'b01; DataIn = 4'b0011; #10;
    if ( DataOut === 4'b1000 )
      $display("PASS\t%p is %p with %p", DataIn, MODE, DataOut);
    else
      $display("FAIL\t%p is %p with %p", DataIn, MODE, DataOut);
    MODE = 2'b01; DataIn = 4'b0011; #10;
    if ( DataOut === 4'b1100 ) 
      $display("PASS\t%p is %p with %p", DataIn, MODE, DataOut);
    else
      $display("FAIL\t%p is %p with %p", DataIn, MODE, DataOut);
    
    
    
    MODE = 2'b00; reset = 1; #10; reset = 0; #10;
    MODE = 2'b10; DataIn = 4'b0111; #10;
    if ( DataOut === 4'b0001 ) 
      $display("PASS\t%p is %p with %p", DataIn, MODE, DataOut);
    else
      $display("FAIL\t%p is %p with %p", DataIn, MODE, DataOut);
    
    MODE = 2'b10; DataIn = 4'b0111; #10;
    if ( DataOut === 4'b0011 )
      $display("PASS\t%p is %p with %p", DataIn, MODE, DataOut);
    else
      $display("FAIL\t%p is %p with %p", DataIn, MODE, DataOut);


    
    MODE = 2'b00; reset = 1; #10; reset = 0; #10;
    MODE = 2'b11; DataIn = 4'b1010; #10;
    if ( DataOut === 4'b1010 )
      $display("PASS\t%p is %p with %p", DataIn, MODE, DataOut);
    else
      $display("FAIL\t%p is %p with %p", DataIn, MODE, DataOut);

    #20;
    $finish;
  end
  
    
 
  initial begin 
    $dumpfile("dump.vcd"); $dumpvars;
  end

  
  always #5 clock = ~clock;
  
endmodule