data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/basic_regs.v
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/basic_regs.v:33: Cannot find include file: ../regmap/basic_regs_regmap_utils.vh\n  `include "../regmap/basic_regs_regmap_utils.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints,data/full_repos/permissive/447976230/../regmap/basic_regs_regmap_utils.vh\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints,data/full_repos/permissive/447976230/../regmap/basic_regs_regmap_utils.vh.v\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints,data/full_repos/permissive/447976230/../regmap/basic_regs_regmap_utils.vh.sv\n             ../regmap/basic_regs_regmap_utils.vh\n             ../regmap/basic_regs_regmap_utils.vh.v\n             ../regmap/basic_regs_regmap_utils.vh.sv\n             obj_dir/../regmap/basic_regs_regmap_utils.vh\n             obj_dir/../regmap/basic_regs_regmap_utils.vh.v\n             obj_dir/../regmap/basic_regs_regmap_utils.vh.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/basic_regs.v:34: Cannot find include file: ../../../../../../lib/rfnoc/core/ctrlport.vh\n  `include "../../../../../../lib/rfnoc/core/ctrlport.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module basic_regs #(
  parameter [19:0]  BASE_ADDRESS = 0,
  parameter [19:0]  SIZE_ADDRESS = 0
) (

  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [31:0] s_ctrlport_req_data,

  output reg         s_ctrlport_resp_ack,
  output reg  [ 1:0] s_ctrlport_resp_status,
  output reg  [31:0] s_ctrlport_resp_data,


  input  wire        ctrlport_clk,
  input  wire        ctrlport_rst
);

  `include "../regmap/basic_regs_regmap_utils.vh"
  `include "../../../../../../lib/rfnoc/core/ctrlport.vh"




  reg [SCRATCH_REG_SIZE-1:0]  scratch_reg = {SCRATCH_REG_SIZE   {1'b0}};




  wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + SIZE_ADDRESS);

  always @(posedge ctrlport_clk) begin

    if (ctrlport_rst) begin
      scratch_reg             <= {SCRATCH_REG_SIZE {1'b0}};

      s_ctrlport_resp_ack     <= 1'b0;
      s_ctrlport_resp_data    <= {32{1'bx}};
      s_ctrlport_resp_status  <= CTRL_STS_OKAY;

    end else begin


      if (s_ctrlport_req_wr) begin

        s_ctrlport_resp_ack     <= 1'b1;
        s_ctrlport_resp_data    <= {32{1'bx}};
        s_ctrlport_resp_status  <= CTRL_STS_OKAY;

        case (s_ctrlport_req_addr)
          BASE_ADDRESS + SLAVE_SCRATCH: begin
            scratch_reg <= s_ctrlport_req_data[ SCRATCH_REG_MSB : SCRATCH_REG];
          end


          default: begin
            if (address_in_range) begin
              s_ctrlport_resp_status  <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack     <= 1'b0;
            end
          end
        endcase


      end else if (s_ctrlport_req_rd) begin

        s_ctrlport_resp_ack     <= 1'b1;
        s_ctrlport_resp_status  <= CTRL_STS_OKAY;
        s_ctrlport_resp_data    <= {32{1'b0}};

        case (s_ctrlport_req_addr)
          BASE_ADDRESS + SLAVE_SIGNATURE: begin
            s_ctrlport_resp_data[BOARD_ID_MSB : BOARD_ID]
                                    <= BOARD_ID_VALUE[BOARD_ID_SIZE-1:0];
          end

          BASE_ADDRESS + SLAVE_REVISION: begin
            s_ctrlport_resp_data[REVISION_REG_MSB : REVISION_REG]
                                    <= CPLD_REVISION[REVISION_REG_SIZE-1:0];
          end

          BASE_ADDRESS + SLAVE_OLDEST_REVISION: begin
            s_ctrlport_resp_data[OLDEST_REVISION_REG_MSB : OLDEST_REVISION_REG]
                                    <= OLDEST_CPLD_REVISION[OLDEST_REVISION_REG_SIZE-1:0];
          end

          BASE_ADDRESS + SLAVE_SCRATCH: begin
            s_ctrlport_resp_data[SCRATCH_REG_MSB : SCRATCH_REG] <= scratch_reg;
          end


          BASE_ADDRESS + GIT_HASH_REGISTER: begin
            `ifdef GIT_HASH
              s_ctrlport_resp_data <= `GIT_HASH;
            `else
              s_ctrlport_resp_data <= 32'hDEADBEEF;
            `endif
          end


          default: begin
            s_ctrlport_resp_data <= {32{1'b0}};
            if (address_in_range) begin
              s_ctrlport_resp_status <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack <= 1'b0;
            end
          end
        endcase


      end else begin
        s_ctrlport_resp_ack <= 1'b0;
      end
    end
  end

endmodule
module basic_regs #(
  parameter [19:0]  BASE_ADDRESS = 0,
  parameter [19:0]  SIZE_ADDRESS = 0
) (

  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [31:0] s_ctrlport_req_data,

  output reg         s_ctrlport_resp_ack,
  output reg  [ 1:0] s_ctrlport_resp_status,
  output reg  [31:0] s_ctrlport_resp_data,


  input  wire        ctrlport_clk,
  input  wire        ctrlport_rst
);


  `include "../regmap/basic_regs_regmap_utils.vh"
  `include "../../../../../../lib/rfnoc/core/ctrlport.vh"




  reg [SCRATCH_REG_SIZE-1:0]  scratch_reg = {SCRATCH_REG_SIZE   {1'b0}};




  wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + SIZE_ADDRESS);

  always @(posedge ctrlport_clk) begin

    if (ctrlport_rst) begin
      scratch_reg             <= {SCRATCH_REG_SIZE {1'b0}};

      s_ctrlport_resp_ack     <= 1'b0;
      s_ctrlport_resp_data    <= {32{1'bx}};
      s_ctrlport_resp_status  <= CTRL_STS_OKAY;

    end else begin


      if (s_ctrlport_req_wr) begin

        s_ctrlport_resp_ack     <= 1'b1;
        s_ctrlport_resp_data    <= {32{1'bx}};
        s_ctrlport_resp_status  <= CTRL_STS_OKAY;

        case (s_ctrlport_req_addr)
          BASE_ADDRESS + SLAVE_SCRATCH: begin
            scratch_reg <= s_ctrlport_req_data[ SCRATCH_REG_MSB : SCRATCH_REG];
          end


          default: begin
            if (address_in_range) begin
              s_ctrlport_resp_status  <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack     <= 1'b0;
            end
          end
        endcase


      end else if (s_ctrlport_req_rd) begin

        s_ctrlport_resp_ack     <= 1'b1;
        s_ctrlport_resp_status  <= CTRL_STS_OKAY;
        s_ctrlport_resp_data    <= {32{1'b0}};

        case (s_ctrlport_req_addr)
          BASE_ADDRESS + SLAVE_SIGNATURE: begin
            s_ctrlport_resp_data[BOARD_ID_MSB : BOARD_ID]
                                    <= BOARD_ID_VALUE[BOARD_ID_SIZE-1:0];
          end

          BASE_ADDRESS + SLAVE_REVISION: begin
            s_ctrlport_resp_data[REVISION_REG_MSB : REVISION_REG]
                                    <= CPLD_REVISION[REVISION_REG_SIZE-1:0];
          end

          BASE_ADDRESS + SLAVE_OLDEST_REVISION: begin
            s_ctrlport_resp_data[OLDEST_REVISION_REG_MSB : OLDEST_REVISION_REG]
                                    <= OLDEST_CPLD_REVISION[OLDEST_REVISION_REG_SIZE-1:0];
          end

          BASE_ADDRESS + SLAVE_SCRATCH: begin
            s_ctrlport_resp_data[SCRATCH_REG_MSB : SCRATCH_REG] <= scratch_reg;
          end


          BASE_ADDRESS + GIT_HASH_REGISTER: begin
            `ifdef GIT_HASH
              s_ctrlport_resp_data <= `GIT_HASH;
            `else
              s_ctrlport_resp_data <= 32'hDEADBEEF;
            `endif
          end


          default: begin
            s_ctrlport_resp_data <= {32{1'b0}};
            if (address_in_range) begin
              s_ctrlport_resp_status <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack <= 1'b0;
            end
          end
        endcase


      end else begin
        s_ctrlport_resp_ack <= 1'b0;
      end
    end
  end

endmodule