data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/fpga/src/apb_node/src/apb_node.sv
data/verilator_xmls/5b6fe469-f3ec-4658-a1f9-7d9505fd5b71.xml
module apb_node #(
        parameter int unsigned NB_MASTER      = 8,
        parameter int unsigned APB_DATA_WIDTH = 32,
        parameter int unsigned APB_ADDR_WIDTH = 32
)(

        input logic 					 penable_i,
        input logic 					 pwrite_i,
        input logic [APB_ADDR_WIDTH-1:0] 		 paddr_i,
        input logic                                      psel_i,
        input logic [APB_DATA_WIDTH-1:0] 		 pwdata_i,
        output logic [APB_DATA_WIDTH-1:0] 		 prdata_o,
        output logic 					 pready_o,
        output logic 					 pslverr_o,


        output logic [NB_MASTER-1:0] 			 penable_o,
        output logic [NB_MASTER-1:0] 			 pwrite_o,
        output logic [NB_MASTER-1:0][APB_ADDR_WIDTH-1:0] paddr_o,
        output logic [NB_MASTER-1:0] 			 psel_o,
        output logic [NB_MASTER-1:0][APB_DATA_WIDTH-1:0] pwdata_o,
        input logic [NB_MASTER-1:0][APB_DATA_WIDTH-1:0]  prdata_i,
        input logic [NB_MASTER-1:0] 			 pready_i,
        input logic [NB_MASTER-1:0] 			 pslverr_i,


        input logic [NB_MASTER-1:0][APB_ADDR_WIDTH-1:0]  START_ADDR_i,
        input logic [NB_MASTER-1:0][APB_ADDR_WIDTH-1:0]  END_ADDR_i
    );

    always_comb begin : match_address
        psel_o = '0;


        for (int unsigned i = 0; i < NB_MASTER; i++)
            psel_o[i]  =  psel_i & (paddr_i >= START_ADDR_i[i]) && (paddr_i <= END_ADDR_i[i]);
    end

    always_comb begin

        penable_o = '0;
        pwrite_o  = '0;
        paddr_o   = '0;
        pwdata_o  = '0;
        prdata_o  = '0;
        pready_o  = 1'b0;
        pslverr_o = 1'b0;

        for (int unsigned i = 0; i < NB_MASTER; i++) begin

            if (psel_o[i]) begin

                penable_o[i] = penable_i;
                pwrite_o[i]  = pwrite_i;
                paddr_o[i]   = paddr_i;
                pwdata_o[i]  = pwdata_i;

                prdata_o     = prdata_i[i];
                pready_o     = pready_i[i];
                pslverr_o    = pslverr_i[i];
            end
        end
    end
endmodule
module apb_node #(
        parameter int unsigned NB_MASTER      = 8,
        parameter int unsigned APB_DATA_WIDTH = 32,
        parameter int unsigned APB_ADDR_WIDTH = 32
)(

        input logic 					 penable_i,
        input logic 					 pwrite_i,
        input logic [APB_ADDR_WIDTH-1:0] 		 paddr_i,
        input logic                                      psel_i,
        input logic [APB_DATA_WIDTH-1:0] 		 pwdata_i,
        output logic [APB_DATA_WIDTH-1:0] 		 prdata_o,
        output logic 					 pready_o,
        output logic 					 pslverr_o,


        output logic [NB_MASTER-1:0] 			 penable_o,
        output logic [NB_MASTER-1:0] 			 pwrite_o,
        output logic [NB_MASTER-1:0][APB_ADDR_WIDTH-1:0] paddr_o,
        output logic [NB_MASTER-1:0] 			 psel_o,
        output logic [NB_MASTER-1:0][APB_DATA_WIDTH-1:0] pwdata_o,
        input logic [NB_MASTER-1:0][APB_DATA_WIDTH-1:0]  prdata_i,
        input logic [NB_MASTER-1:0] 			 pready_i,
        input logic [NB_MASTER-1:0] 			 pslverr_i,


        input logic [NB_MASTER-1:0][APB_ADDR_WIDTH-1:0]  START_ADDR_i,
        input logic [NB_MASTER-1:0][APB_ADDR_WIDTH-1:0]  END_ADDR_i
    );


    always_comb begin : match_address
        psel_o = '0;


        for (int unsigned i = 0; i < NB_MASTER; i++)
            psel_o[i]  =  psel_i & (paddr_i >= START_ADDR_i[i]) && (paddr_i <= END_ADDR_i[i]);
    end

    always_comb begin

        penable_o = '0;
        pwrite_o  = '0;
        paddr_o   = '0;
        pwdata_o  = '0;
        prdata_o  = '0;
        pready_o  = 1'b0;
        pslverr_o = 1'b0;

        for (int unsigned i = 0; i < NB_MASTER; i++) begin

            if (psel_o[i]) begin

                penable_o[i] = penable_i;
                pwrite_o[i]  = pwrite_i;
                paddr_o[i]   = paddr_i;
                pwdata_o[i]  = pwdata_i;

                prdata_o     = prdata_i[i];
                pready_o     = pready_i[i];
                pslverr_o    = pslverr_i[i];
            end
        end
    end
endmodule