data/full_repos/permissive/484316383/rtl/Next186/Next186_ALU.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/484316383/rtl/Next186/Next186_ALU.v:297: Multiple top level modules\n                                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                     : ... Top module \'Next186_ALU\'\nmodule Next186_ALU(\n       ^~~~~~~~~~~\n                                                                                     : ... Top module \'Next186_EA\'\nmodule Next186_EA(\n       ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/484316383/rtl/Next186/Next186_ALU.v:119: Operator ADD expects 5 bits on the RHS, but RHS\'s VARREF \'SCIN\' generates 1 bits.\n                                                                                  : ... In instance Next186_ALU\n assign {AF, SUMOUT[3:0]} = SUMOP1[3:0] + SUMOP2[3:0] + SCIN;\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/484316383/rtl/Next186/Next186_ALU.v:120: Operator ADD expects 5 bits on the RHS, but RHS\'s VARREF \'AF\' generates 1 bits.\n                                                                                  : ... In instance Next186_ALU\n assign {SC8OUT, SUMOUT[7:4]} = SUMOP1[7:4] + SUMOP2[7:4] + AF;\n                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/484316383/rtl/Next186/Next186_ALU.v:121: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'SC8OUT\' generates 1 bits.\n                                                                                  : ... In instance Next186_ALU\n assign {SC16OUT, SUMOUT[15:8]} = SUMOP1[15:8] + SUMOP2[15:8] + SC8OUT;\n                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/484316383/rtl/Next186/Next186_ALU.v:132: Operator ASSIGNW expects 18 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 25 bits.\n                                                                                  : ... In instance Next186_ALU\n wire [17:0]SHBAR = (EXOP[0] ? {1\'bx, SHEX, WORD ? RA[15:8]: SHEX, RA[7:0]} : {RA, SHEX, 1\'bx}) >> SCOUNT;\n                  ^\n%Error: Exiting due to 5 warning(s)\n'
module Next186_EA(
    input [15:0] SP,
    input [15:0] BX,
    input [15:0] BP,
    input [15:0] SI,
    input [15:0] DI,
	 input [15:0] TMP16,
	 input [7:0]  AL,
    input [15:0] AIMM,
	 input [3:0]EAC,
    output [15:0] ADDR16
    );

	reg [15:0]OP1;
	reg [15:0]OP2;
	reg [15:0]OP3;
		
	always @* begin
		case(EAC)
			4'b0000, 4'b0001, 4'b0111, 4'b1010: OP1 = BX;
			4'b0010, 4'b0011, 4'b0110:  OP1 = BP; 
			4'b1000, 4'b1001, 4'b1101: OP1 = SP;
			4'b1011: OP1 = TMP16;
			default: OP1 = 16'h0000;
		endcase
		case(EAC)
			4'b0000, 4'b0010, 4'b0100: OP2 = SI;
			4'b0001, 4'b0011, 4'b0101: OP2 = DI;
			4'b1001, 4'b1011, 4'b1101:	OP2 = 16'h0002;
			default: OP2 = 16'h0000;
		endcase
		case(EAC)
			4'b1000: OP3 = 16'hfffe;
			4'b1010: OP3 = {8'b00000000, AL};
			4'b1001, 4'b1011:	OP3 = 16'h0000;
			4'b1110: OP3 = {6'b000000, AIMM[7:0], 2'b00};
			default: OP3 = AIMM;
		endcase
	end
	
	assign ADDR16 = OP1 + OP2 + OP3;
endmodule
module Next186_EA(
    input [15:0] SP,
    input [15:0] BX,
    input [15:0] BP,
    input [15:0] SI,
    input [15:0] DI,
	 input [15:0] TMP16,
	 input [7:0]  AL,
    input [15:0] AIMM,
	 input [3:0]EAC,
    output [15:0] ADDR16
    );


	reg [15:0]OP1;
	reg [15:0]OP2;
	reg [15:0]OP3;
		
	always @* begin
		case(EAC)
			4'b0000, 4'b0001, 4'b0111, 4'b1010: OP1 = BX;
			4'b0010, 4'b0011, 4'b0110:  OP1 = BP; 
			4'b1000, 4'b1001, 4'b1101: OP1 = SP;
			4'b1011: OP1 = TMP16;
			default: OP1 = 16'h0000;
		endcase
		case(EAC)
			4'b0000, 4'b0010, 4'b0100: OP2 = SI;
			4'b0001, 4'b0011, 4'b0101: OP2 = DI;
			4'b1001, 4'b1011, 4'b1101:	OP2 = 16'h0002;
			default: OP2 = 16'h0000;
		endcase
		case(EAC)
			4'b1000: OP3 = 16'hfffe;
			4'b1010: OP3 = {8'b00000000, AL};
			4'b1001, 4'b1011:	OP3 = 16'h0000;
			4'b1110: OP3 = {6'b000000, AIMM[7:0], 2'b00};
			default: OP3 = AIMM;
		endcase
	end
	
	assign ADDR16 = OP1 + OP2 + OP3;
endmodule