data/full_repos/permissive/432564927/Lab1 (Verilog)/Lab1_Unal (Verilog)/Unal_Lab1.srcs/sim_1/new/testbench.v
1: b'%Error: Cannot find file containing module: (Verilog)/Lab1_Unal\n        ... Looked in:\n             data/full_repos/permissive/432564927/Lab1/(Verilog)/Lab1_Unal\n             data/full_repos/permissive/432564927/Lab1/(Verilog)/Lab1_Unal.v\n             data/full_repos/permissive/432564927/Lab1/(Verilog)/Lab1_Unal.sv\n             (Verilog)/Lab1_Unal\n             (Verilog)/Lab1_Unal.v\n             (Verilog)/Lab1_Unal.sv\n             obj_dir/(Verilog)/Lab1_Unal\n             obj_dir/(Verilog)/Lab1_Unal.v\n             obj_dir/(Verilog)/Lab1_Unal.sv\n%Error: Cannot find file containing module: (Verilog)/Unal_Lab1.srcs/sim_1/new,data/full_repos/permissive/432564927\n%Error: Cannot find file containing module: data/full_repos/permissive/432564927/Lab1\n%Error: Cannot find file containing module: (Verilog)/Unal_Lab1.srcs/sim_1/new/testbench.v\n%Error: Exiting due to 4 error(s)\n'
module testbench;

    wire [2:0] currentState;
    reg clk;
    reg clrn;
    reg u;

    wire [2:0] nextState;
    wire [6:0] led;
   
    lab1 lab1(
        .u(u),
        .currentState(currentState),
        .clrn(clrn),
        .nextState(nextState),
        .led(led)
    );
    posEdgeDFF posEdgeDFF(
        .currentState(currentState),
        .clk(clk),
        .clrn(clrn),
        .nextState(nextState)
    );
    
    initial begin
        clk = 1;
        u = 1;
        clrn = 0;
        #1 clrn = 1;
        #15 u = 0;
        end
always
begin
 #1 clk = ~clk;
  end
  
endmodule
module testbench;


    wire [2:0] currentState;
    reg clk;
    reg clrn;
    reg u;

    wire [2:0] nextState;
    wire [6:0] led;
   
    lab1 lab1(
        .u(u),
        .currentState(currentState),
        .clrn(clrn),
        .nextState(nextState),
        .led(led)
    );
    posEdgeDFF posEdgeDFF(
        .currentState(currentState),
        .clk(clk),
        .clrn(clrn),
        .nextState(nextState)
    );
    
    initial begin
        clk = 1;
        u = 1;
        clrn = 0;
        #1 clrn = 1;
        #15 u = 0;
        end
always
begin
 #1 clk = ~clk;
  end
  
endmodule