data/full_repos/permissive/501138203/verilog/rtl/puf_super_behavioral.v
1: b"%Error: data/full_repos/permissive/501138203/verilog/rtl/puf_super_behavioral.v:55: Cannot find file containing module: 'ChalShiftReg'\n  ChalShiftReg ChalShiftReg_inst (\n  ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/501138203/verilog/rtl,data/full_repos/permissive/501138203/ChalShiftReg\n             data/full_repos/permissive/501138203/verilog/rtl,data/full_repos/permissive/501138203/ChalShiftReg.v\n             data/full_repos/permissive/501138203/verilog/rtl,data/full_repos/permissive/501138203/ChalShiftReg.sv\n             ChalShiftReg\n             ChalShiftReg.v\n             ChalShiftReg.sv\n             obj_dir/ChalShiftReg\n             obj_dir/ChalShiftReg.v\n             obj_dir/ChalShiftReg.sv\n%Error: data/full_repos/permissive/501138203/verilog/rtl/puf_super_behavioral.v:63: Cannot find file containing module: 'puf'\n  puf puf1_inst (\n  ^~~\n%Error: data/full_repos/permissive/501138203/verilog/rtl/puf_super_behavioral.v:70: Cannot find file containing module: 'puf'\n  puf puf2_inst (\n  ^~~\n%Error: data/full_repos/permissive/501138203/verilog/rtl/puf_super_behavioral.v:77: Cannot find file containing module: 'puf'\n  puf puf3_inst (\n  ^~~\n%Error: data/full_repos/permissive/501138203/verilog/rtl/puf_super_behavioral.v:84: Cannot find file containing module: 'puf'\n  puf puf4_inst (\n  ^~~\n%Error: Exiting due to 5 error(s)\n"
module puf_super #(
    parameter BITS = 32
) (
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif

    input wire reset,
    input wire clk,
    input wire si,
    input wire rstn,
    input wire [1:0] puf_sel,
    input wire [1:0] length,
    output reg out,
    output wire so
);




  reg [3:0] reset_puf;
  reg [127:0] c;
  wire out_1;
  wire out_2;
  wire out_3;
  wire out_4;


  always @ (*) begin
    case(puf_sel)
      2'b00: begin 
               reset_puf <= {3'b111, reset};
               out <= out_1;
             end
      2'b01: begin
               reset_puf <= {2'b11, reset, 1'b1};
               out <= out_2; 
             end  
      2'b10: begin
               reset_puf <= {1'b1, reset, 2'b11};
               out <= out_3;
             end  
      2'b11: begin
               reset_puf <= {reset, 3'b111};
               out <= out_4;
             end
    endcase
  end


  ChalShiftReg ChalShiftReg_inst (
    .clk(clk),
    .si(si),
    .rstn(rstn),
    .c(c),
    .so(so)
  );

  puf puf1_inst (
    .reset(reset_puf[0]),
    .length(length),
    .c(c),
    .out(out_1)
  );

  puf puf2_inst (
    .reset(reset_puf[1]),
    .length(length),
    .c(c),
    .out(out_2)
  );

  puf puf3_inst (
    .reset(reset_puf[2]),
    .length(length),
    .c(c),
    .out(out_3)
  );

  puf puf4_inst (
    .reset(reset_puf[3]),
    .length(length),
    .c(c),
    .out(out_4)
  );



endmodule
module puf_super #(
    parameter BITS = 32
) (
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif

    input wire reset,
    input wire clk,
    input wire si,
    input wire rstn,
    input wire [1:0] puf_sel,
    input wire [1:0] length,
    output reg out,
    output wire so
);





  reg [3:0] reset_puf;
  reg [127:0] c;
  wire out_1;
  wire out_2;
  wire out_3;
  wire out_4;


  always @ (*) begin
    case(puf_sel)
      2'b00: begin 
               reset_puf <= {3'b111, reset};
               out <= out_1;
             end
      2'b01: begin
               reset_puf <= {2'b11, reset, 1'b1};
               out <= out_2; 
             end  
      2'b10: begin
               reset_puf <= {1'b1, reset, 2'b11};
               out <= out_3;
             end  
      2'b11: begin
               reset_puf <= {reset, 3'b111};
               out <= out_4;
             end
    endcase
  end


  ChalShiftReg ChalShiftReg_inst (
    .clk(clk),
    .si(si),
    .rstn(rstn),
    .c(c),
    .so(so)
  );

  puf puf1_inst (
    .reset(reset_puf[0]),
    .length(length),
    .c(c),
    .out(out_1)
  );

  puf puf2_inst (
    .reset(reset_puf[1]),
    .length(length),
    .c(c),
    .out(out_2)
  );

  puf puf3_inst (
    .reset(reset_puf[2]),
    .length(length),
    .c(c),
    .out(out_3)
  );

  puf puf4_inst (
    .reset(reset_puf[3]),
    .length(length),
    .c(c),
    .out(out_4)
  );



endmodule