data/full_repos/permissive/452183855/lab3/Lab3_Pos_Edge_D_FF_gatelevel.v
1: b"%Error: data/full_repos/permissive/452183855/lab3/Lab3_Pos_Edge_D_FF_gatelevel.v:8: Cannot find file containing module: 'Lab3_SbRb_Latch_gatelevel'\n    Lab3_SbRb_Latch_gatelevel M0(Q, NQ, Sb, Rb);\n    ^~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/452183855/lab3,data/full_repos/permissive/452183855/Lab3_SbRb_Latch_gatelevel\n             data/full_repos/permissive/452183855/lab3,data/full_repos/permissive/452183855/Lab3_SbRb_Latch_gatelevel.v\n             data/full_repos/permissive/452183855/lab3,data/full_repos/permissive/452183855/Lab3_SbRb_Latch_gatelevel.sv\n             Lab3_SbRb_Latch_gatelevel\n             Lab3_SbRb_Latch_gatelevel.v\n             Lab3_SbRb_Latch_gatelevel.sv\n             obj_dir/Lab3_SbRb_Latch_gatelevel\n             obj_dir/Lab3_SbRb_Latch_gatelevel.v\n             obj_dir/Lab3_SbRb_Latch_gatelevel.sv\n%Error: Exiting due to 1 error(s)\n"
module Lab3_Pos_Edge_D_FF_gatelevel(output Q, NQ, 
                                    input D, clock);

    wire Sb, Rb;
    wire a1, a2;

    Lab3_SbRb_Latch_gatelevel M0(Q, NQ, Sb, Rb);
 
    nand #(2) (a1, a2, Sb);
    nand #(2) (Sb, a1, clock);
    nand #(2) (Rb, Sb, clock, a2);
    nand #(2) (a2, Rb, D);




endmodule
module Lab3_Pos_Edge_D_FF_gatelevel(output Q, NQ, 
                                    input D, clock);


    wire Sb, Rb;
    wire a1, a2;

    Lab3_SbRb_Latch_gatelevel M0(Q, NQ, Sb, Rb);
 
    nand #(2) (a1, a2, Sb);
    nand #(2) (Sb, a1, clock);
    nand #(2) (Rb, Sb, clock, a2);
    nand #(2) (a2, Rb, D);




endmodule