data/full_repos/permissive/517427004/CA4 - Multi-Cycle/Verilog/Memory.v
1: b'%Error: Invalid Option: -\n'
module Memory (memAdr, writeData, memRead, memWrite, clk, readData);
    input [15:0] writeData;
    input [11:0] memAdr;
    input memRead, memWrite, clk;
    output [15:0] readData;
    reg [15:0] readData;

    reg [15:0] mem [0:$pow(2, 12)-1];

    initial $readmemb("data.mem", mem);

    always @(posedge clk) begin
        if (memWrite)
            mem[memAdr] <= writeData;
    end

    always @(memRead or memAdr) begin
        if (memRead)
            readData = mem[memAdr];
    end
endmodule
module Memory (memAdr, writeData, memRead, memWrite, clk, readData);

    input [15:0] writeData;
    input [11:0] memAdr;
    input memRead, memWrite, clk;
    output [15:0] readData;
    reg [15:0] readData;

    reg [15:0] mem [0:$pow(2, 12)-1];

    initial $readmemb("data.mem", mem);

    always @(posedge clk) begin
        if (memWrite)
            mem[memAdr] <= writeData;
    end

    always @(memRead or memAdr) begin
        if (memRead)
            readData = mem[memAdr];
    end
endmodule