data/full_repos/permissive/435108851/openlane/user_proj/src/user_proj.v
1: b"%Error: data/full_repos/permissive/435108851/openlane/user_proj/src/user_proj.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/435108851/openlane/user_proj/src/user_proj.v:67: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/435108851/openlane/user_proj/src/user_proj.v:68: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module user_proj #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif
    input clk_i,
    input rst_i,


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,


    output [2:0] irq,


    output [3:0] o_wmask0,
    output [8:0] o_waddr0,
    output [31:0] o_din0,
    input [31:0] i_dout0,
    output o_web0,
    output o_csb0,


    output [3:0] o_wmask0_1,
    output [8:0] o_waddr0_1,
    output [31:0] o_din0_1,
    input [31:0] i_dout0_1,
    output o_web0_1,
    output o_csb0_1
);




assign irq = 3'b0;


assign io_oeb[12] = 1'b1;


assign io_oeb[13] = 1'b0;


assign io_oeb[19] = 1'b1;


assign io_oeb[20] = 1'b1;


assign io_oeb[21] = 1'b1;


assign io_oeb[22] = 1'b0;


assign io_oeb[23] = 1'b1;


assign io_oeb[24] = 1'b1;


assign io_oeb[25] = 1'b0;
assign io_oeb[26] = 1'b0;
assign io_oeb[27] = 1'b0;
assign io_oeb[28] = 1'b0;
assign io_oeb[29] = 1'b0;
assign io_oeb[30] = 1'b0;
assign io_oeb[31] = 1'b0;
assign io_oeb[32] = 1'b0;

soc soc(
`ifdef USE_POWER_PINS
    .vccd1(vccd1),
    .vssd1(vssd1),
`endif
    .clk(clk_i),
    .rst(rst_i | ~io_oeb[19]),

    .wb_clk(wb_clk_i),
    .wb_rst(wb_rst_i),

    .LEDS(io_out[32:25]),
    .MCU_UART_TX(io_out[13]),
    .MCU_UART_RX(io_in[12]),

    .jtag_trst(~io_in[20]),
    .jtag_tms(io_in[21]),
    .jtag_tdi(io_in[23]),
    .jtag_tdo(io_out[22]),
    .jtag_tck(io_in[24]),


    .mprj_cyc_i(wbs_cyc_i),
    .mprj_stb_i(wbs_stb_i),
    .mprj_we_i(wbs_we_i),
    .mprj_sel_i(wbs_sel_i),
    .mprj_adr_i(wbs_adr_i),
    .mprj_dat_i(wbs_dat_i),
    .mprj_ack_o(wbs_ack_o),
    .mprj_dat_o(wbs_dat_o),


    .o_wmask0(o_wmask0),
    .o_waddr0(o_waddr0),
    .o_din0(o_din0),
    .i_dout0(i_dout0),
    .o_web0(o_web0),
    .o_csb0(o_csb0),


    .o_wmask0_1(o_wmask0_1),
    .o_waddr0_1(o_waddr0_1),
    .o_din0_1(o_din0_1),
    .i_dout0_1(i_dout0_1),
    .o_web0_1(o_web0_1),
    .o_csb0_1(o_csb0_1)
);

endmodule
module user_proj #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif
    input clk_i,
    input rst_i,


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,


    output [2:0] irq,


    output [3:0] o_wmask0,
    output [8:0] o_waddr0,
    output [31:0] o_din0,
    input [31:0] i_dout0,
    output o_web0,
    output o_csb0,


    output [3:0] o_wmask0_1,
    output [8:0] o_waddr0_1,
    output [31:0] o_din0_1,
    input [31:0] i_dout0_1,
    output o_web0_1,
    output o_csb0_1
);





assign irq = 3'b0;


assign io_oeb[12] = 1'b1;


assign io_oeb[13] = 1'b0;


assign io_oeb[19] = 1'b1;


assign io_oeb[20] = 1'b1;


assign io_oeb[21] = 1'b1;


assign io_oeb[22] = 1'b0;


assign io_oeb[23] = 1'b1;


assign io_oeb[24] = 1'b1;


assign io_oeb[25] = 1'b0;
assign io_oeb[26] = 1'b0;
assign io_oeb[27] = 1'b0;
assign io_oeb[28] = 1'b0;
assign io_oeb[29] = 1'b0;
assign io_oeb[30] = 1'b0;
assign io_oeb[31] = 1'b0;
assign io_oeb[32] = 1'b0;

soc soc(
`ifdef USE_POWER_PINS
    .vccd1(vccd1),
    .vssd1(vssd1),
`endif
    .clk(clk_i),
    .rst(rst_i | ~io_oeb[19]),

    .wb_clk(wb_clk_i),
    .wb_rst(wb_rst_i),

    .LEDS(io_out[32:25]),
    .MCU_UART_TX(io_out[13]),
    .MCU_UART_RX(io_in[12]),

    .jtag_trst(~io_in[20]),
    .jtag_tms(io_in[21]),
    .jtag_tdi(io_in[23]),
    .jtag_tdo(io_out[22]),
    .jtag_tck(io_in[24]),


    .mprj_cyc_i(wbs_cyc_i),
    .mprj_stb_i(wbs_stb_i),
    .mprj_we_i(wbs_we_i),
    .mprj_sel_i(wbs_sel_i),
    .mprj_adr_i(wbs_adr_i),
    .mprj_dat_i(wbs_dat_i),
    .mprj_ack_o(wbs_ack_o),
    .mprj_dat_o(wbs_dat_o),


    .o_wmask0(o_wmask0),
    .o_waddr0(o_waddr0),
    .o_din0(o_din0),
    .i_dout0(i_dout0),
    .o_web0(o_web0),
    .o_csb0(o_csb0),


    .o_wmask0_1(o_wmask0_1),
    .o_waddr0_1(o_waddr0_1),
    .o_din0_1(o_din0_1),
    .i_dout0_1(i_dout0_1),
    .o_web0_1(o_web0_1),
    .o_csb0_1(o_csb0_1)
);

endmodule