data/full_repos/permissive/456551361/vivado/finn_full_ip/finn_full_ip.gen/sources_1/bd/finn_stitched/ipshared/209a/hdl/memstream_singleblock.v
1: b"%Error: data/full_repos/permissive/456551361/vivado/finn_full_ip/finn_full_ip.gen/sources_1/bd/finn_stitched/ipshared/209a/hdl/memstream_singleblock.v:161: Cannot find file containing module: 'ramb18_wf_dualport'\nramb18_wf_dualport\n^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/456551361/vivado/finn_full_ip/finn_full_ip.gen/sources_1/bd/finn_stitched/ipshared/209a/hdl,data/full_repos/permissive/456551361/ramb18_wf_dualport\n             data/full_repos/permissive/456551361/vivado/finn_full_ip/finn_full_ip.gen/sources_1/bd/finn_stitched/ipshared/209a/hdl,data/full_repos/permissive/456551361/ramb18_wf_dualport.v\n             data/full_repos/permissive/456551361/vivado/finn_full_ip/finn_full_ip.gen/sources_1/bd/finn_stitched/ipshared/209a/hdl,data/full_repos/permissive/456551361/ramb18_wf_dualport.sv\n             ramb18_wf_dualport\n             ramb18_wf_dualport.v\n             ramb18_wf_dualport.sv\n             obj_dir/ramb18_wf_dualport\n             obj_dir/ramb18_wf_dualport.v\n             obj_dir/ramb18_wf_dualport.sv\n%Error: Exiting due to 1 error(s)\n"
module memstream_singleblock
#(
    parameter CONFIG_EN = 1,
    parameter NSTREAMS = 2,

    parameter MEM_DEPTH = 512,
    parameter MEM_WIDTH = 32,
    parameter MEM_INIT = "./",
    parameter RAM_STYLE = "auto",


	parameter STRM0_WIDTH = 32,
	parameter STRM1_WIDTH = 32,


	parameter STRM0_DEPTH = 256,
	parameter STRM1_DEPTH = 256,


	parameter STRM0_OFFSET = 0,
	parameter STRM1_OFFSET = 256
)

(
    input aclk,
    input aresetn,


	input [31:0] config_address,
	input config_ce,
	input config_we,
	input [MEM_WIDTH-1:0] config_d0,
	output [MEM_WIDTH-1:0] config_q0,
    output config_rack,


    input m_axis_0_tready,
    output m_axis_0_tvalid,
    output [((STRM0_WIDTH+7)/8)*8-1:0] m_axis_0_tdata,

    input m_axis_1_tready,
    output m_axis_1_tvalid,
    output [((STRM1_WIDTH+7)/8)*8-1:0] m_axis_1_tdata

);




initial begin
    if((NSTREAMS < 1) | (NSTREAMS > 2)) begin
        $display("Invalid setting for NSTREAMS, please set in range [1,2]");
        $finish();
    end
end


wire rst;
assign rst = ~aresetn;

wire strm0_incr_en;
wire strm1_incr_en;

assign strm0_incr_en = m_axis_0_tready | ~m_axis_0_tvalid;
assign strm1_incr_en = m_axis_1_tready | ~m_axis_1_tvalid;

reg rack_shift[1:0];

generate
if(MEM_DEPTH > 1) begin: use_ram


localparam BLOCKADRWIDTH = $clog2(MEM_DEPTH);

reg [BLOCKADRWIDTH-1:0] strm0_addr = STRM0_OFFSET;
wire strm0_rst;
assign strm0_rst = strm0_incr_en & (strm0_addr == (STRM0_OFFSET + STRM0_DEPTH-1));


always @(posedge aclk) begin
    if(strm0_rst | rst)
        strm0_addr <= STRM0_OFFSET;
    else if(strm0_incr_en)
        strm0_addr <= strm0_addr + 1;
end

if(NSTREAMS == 1) begin: sdp

ramb18_sdp
#(
    .ID(0),
	.DWIDTH(MEM_WIDTH),
	.AWIDTH(BLOCKADRWIDTH),
    .DEPTH(MEM_DEPTH),
	.MEM_INIT(MEM_INIT),
    .RAM_STYLE(RAM_STYLE)
)
ram
(
	.clk(aclk),

    .ena(config_ce),
	.wea(config_we),
	.addra(config_address[BLOCKADRWIDTH-1:0]),
    .wdataa(config_d0),

    .enb(strm0_incr_en | config_ce),
    .enqb(strm0_incr_en | rack_shift[0]),
	.addrb(config_ce ? config_address[BLOCKADRWIDTH-1:0] : strm0_addr),
	.rdqb(m_axis_0_tdata)
);


end else begin: tdp

reg [BLOCKADRWIDTH-1:0] strm1_addr = STRM1_OFFSET;
wire strm1_rst;
assign strm1_rst = strm1_incr_en & (strm1_addr == (STRM1_OFFSET + STRM1_DEPTH-1));

always @(posedge aclk) begin
    if(strm1_rst | rst)
        strm1_addr <= STRM1_OFFSET;
    else if(strm1_incr_en)
        strm1_addr <= strm1_addr + 1;
end

ramb18_wf_dualport
#(
    .ID(0),
	.DWIDTH(MEM_WIDTH),
	.AWIDTH(BLOCKADRWIDTH),
    .DEPTH(MEM_DEPTH),
	.MEM_INIT(MEM_INIT),
    .RAM_STYLE(RAM_STYLE)
)
ram
(
	.clk(aclk),

	.wea(config_we),
    .ena(strm0_incr_en | config_ce),
    .enqa(strm0_incr_en | config_ce_r),
	.addra(config_we ? config_address[BLOCKADRWIDTH-1:0] : strm0_addr),
	.wdataa(config_d0),
	.rdqa(m_axis_0_tdata),

	.web(1'b0),
    .enb(strm1_incr_en),
    .enqb(strm1_incr_en),
	.addrb(strm1_addr),
	.wdatab('d0),
	.rdqb(m_axis_1_tdata)
);

end

end else begin: bypass

reg [MEM_WIDTH-1:0] singleval[0:0];
initial begin
    $readmemh({MEM_INIT,"memblock_0.dat"}, singleval, 0, 0);
end

always @(posedge aclk)
    if(config_ce & config_we)
        singleval[0] <= config_d0;

assign m_axis_0_tdata = singleval[0];
assign m_axis_1_tdata = singleval[0];

end
endgenerate



reg [1:0] tvalid_pipe0 = 2'd0;
reg [1:0] tvalid_pipe1 = 2'd0;

assign m_axis_0_tvalid = tvalid_pipe0[1];
assign m_axis_1_tvalid = tvalid_pipe1[1];

always @(posedge aclk) begin
    if(rst) begin
        tvalid_pipe0 <= 0;
    end else if(strm0_incr_en) begin
        tvalid_pipe0[0] <= 1;
        tvalid_pipe0[1] <= tvalid_pipe0[0];
    end
end

always @(posedge aclk) begin
    if(rst) begin
        tvalid_pipe1 <= 0;
    end else if(strm1_incr_en) begin
        tvalid_pipe1[0] <= 1;
        tvalid_pipe1[1] <= tvalid_pipe1[0];
    end
end

always @(posedge aclk) begin
    rack_shift[0] <= config_ce & ~config_we;
    rack_shift[1] <= rack_shift[0];
end

assign config_rack = rack_shift[1];
assign config_q0 = m_axis_0_tdata;

endmodule
module memstream_singleblock
#(
    parameter CONFIG_EN = 1,
    parameter NSTREAMS = 2,

    parameter MEM_DEPTH = 512,
    parameter MEM_WIDTH = 32,
    parameter MEM_INIT = "./",
    parameter RAM_STYLE = "auto",


	parameter STRM0_WIDTH = 32,
	parameter STRM1_WIDTH = 32,


	parameter STRM0_DEPTH = 256,
	parameter STRM1_DEPTH = 256,


	parameter STRM0_OFFSET = 0,
	parameter STRM1_OFFSET = 256
)

(
    input aclk,
    input aresetn,


	input [31:0] config_address,
	input config_ce,
	input config_we,
	input [MEM_WIDTH-1:0] config_d0,
	output [MEM_WIDTH-1:0] config_q0,
    output config_rack,


    input m_axis_0_tready,
    output m_axis_0_tvalid,
    output [((STRM0_WIDTH+7)/8)*8-1:0] m_axis_0_tdata,

    input m_axis_1_tready,
    output m_axis_1_tvalid,
    output [((STRM1_WIDTH+7)/8)*8-1:0] m_axis_1_tdata

);





initial begin
    if((NSTREAMS < 1) | (NSTREAMS > 2)) begin
        $display("Invalid setting for NSTREAMS, please set in range [1,2]");
        $finish();
    end
end


wire rst;
assign rst = ~aresetn;

wire strm0_incr_en;
wire strm1_incr_en;

assign strm0_incr_en = m_axis_0_tready | ~m_axis_0_tvalid;
assign strm1_incr_en = m_axis_1_tready | ~m_axis_1_tvalid;

reg rack_shift[1:0];

generate
if(MEM_DEPTH > 1) begin: use_ram


localparam BLOCKADRWIDTH = $clog2(MEM_DEPTH);

reg [BLOCKADRWIDTH-1:0] strm0_addr = STRM0_OFFSET;
wire strm0_rst;
assign strm0_rst = strm0_incr_en & (strm0_addr == (STRM0_OFFSET + STRM0_DEPTH-1));


always @(posedge aclk) begin
    if(strm0_rst | rst)
        strm0_addr <= STRM0_OFFSET;
    else if(strm0_incr_en)
        strm0_addr <= strm0_addr + 1;
end

if(NSTREAMS == 1) begin: sdp

ramb18_sdp
#(
    .ID(0),
	.DWIDTH(MEM_WIDTH),
	.AWIDTH(BLOCKADRWIDTH),
    .DEPTH(MEM_DEPTH),
	.MEM_INIT(MEM_INIT),
    .RAM_STYLE(RAM_STYLE)
)
ram
(
	.clk(aclk),

    .ena(config_ce),
	.wea(config_we),
	.addra(config_address[BLOCKADRWIDTH-1:0]),
    .wdataa(config_d0),

    .enb(strm0_incr_en | config_ce),
    .enqb(strm0_incr_en | rack_shift[0]),
	.addrb(config_ce ? config_address[BLOCKADRWIDTH-1:0] : strm0_addr),
	.rdqb(m_axis_0_tdata)
);


end else begin: tdp

reg [BLOCKADRWIDTH-1:0] strm1_addr = STRM1_OFFSET;
wire strm1_rst;
assign strm1_rst = strm1_incr_en & (strm1_addr == (STRM1_OFFSET + STRM1_DEPTH-1));

always @(posedge aclk) begin
    if(strm1_rst | rst)
        strm1_addr <= STRM1_OFFSET;
    else if(strm1_incr_en)
        strm1_addr <= strm1_addr + 1;
end

ramb18_wf_dualport
#(
    .ID(0),
	.DWIDTH(MEM_WIDTH),
	.AWIDTH(BLOCKADRWIDTH),
    .DEPTH(MEM_DEPTH),
	.MEM_INIT(MEM_INIT),
    .RAM_STYLE(RAM_STYLE)
)
ram
(
	.clk(aclk),

	.wea(config_we),
    .ena(strm0_incr_en | config_ce),
    .enqa(strm0_incr_en | config_ce_r),
	.addra(config_we ? config_address[BLOCKADRWIDTH-1:0] : strm0_addr),
	.wdataa(config_d0),
	.rdqa(m_axis_0_tdata),

	.web(1'b0),
    .enb(strm1_incr_en),
    .enqb(strm1_incr_en),
	.addrb(strm1_addr),
	.wdatab('d0),
	.rdqb(m_axis_1_tdata)
);

end

end else begin: bypass

reg [MEM_WIDTH-1:0] singleval[0:0];
initial begin
    $readmemh({MEM_INIT,"memblock_0.dat"}, singleval, 0, 0);
end

always @(posedge aclk)
    if(config_ce & config_we)
        singleval[0] <= config_d0;

assign m_axis_0_tdata = singleval[0];
assign m_axis_1_tdata = singleval[0];

end
endgenerate



reg [1:0] tvalid_pipe0 = 2'd0;
reg [1:0] tvalid_pipe1 = 2'd0;

assign m_axis_0_tvalid = tvalid_pipe0[1];
assign m_axis_1_tvalid = tvalid_pipe1[1];

always @(posedge aclk) begin
    if(rst) begin
        tvalid_pipe0 <= 0;
    end else if(strm0_incr_en) begin
        tvalid_pipe0[0] <= 1;
        tvalid_pipe0[1] <= tvalid_pipe0[0];
    end
end

always @(posedge aclk) begin
    if(rst) begin
        tvalid_pipe1 <= 0;
    end else if(strm1_incr_en) begin
        tvalid_pipe1[0] <= 1;
        tvalid_pipe1[1] <= tvalid_pipe1[0];
    end
end

always @(posedge aclk) begin
    rack_shift[0] <= config_ce & ~config_we;
    rack_shift[1] <= rack_shift[0];
end

assign config_rack = rack_shift[1];
assign config_q0 = m_axis_0_tdata;

endmodule