data/full_repos/permissive/494696040/Sign_Extension.v
data/verilator_xmls/34c87716-f9aa-41a8-89a2-6a4e1fc92c59.xml
module Sign_Extension(
    input [15:0] num_in,
    output reg [31:0] num_out
    );


    always @(num_in)
    begin

        if (num_in[15]) num_out <= {16'hffff, num_in};
        

        else num_out <= {16'h0000, num_in};
    end
endmodule
module Sign_Extension(
    input [15:0] num_in,
    output reg [31:0] num_out
    );



    always @(num_in)
    begin

        if (num_in[15]) num_out <= {16'hffff, num_in};
        

        else num_out <= {16'h0000, num_in};
    end
endmodule