data/full_repos/permissive/499056536/mod_m_counter.v
data/verilator_xmls/32e1c7ae-1f24-41d1-8564-73708ddd6f45.xml
module mod_m_counter
    #(parameter N = 4,
                MAX = 10
                )
    (
        input wire clk, rst_n,
        output wire max_tick,
        output wire [N-1:0] counter
    );


    reg     [N-1:0] r_reg;
    wire    [N-1:0] r_next;





    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)
            r_reg   <= 0;
        else
            r_reg   <= r_next;
    end


    assign r_next = (r_reg == (MAX-1)) ? 0 : (r_reg+1);


    assign max_tick = (r_reg == (MAX-1)) ? 1'b1 : 1'b0;
    assign counter = r_reg;
    
endmodule
module mod_m_counter
    #(parameter N = 4,
                MAX = 10
                )
    (
        input wire clk, rst_n,
        output wire max_tick,
        output wire [N-1:0] counter
    );



    reg     [N-1:0] r_reg;
    wire    [N-1:0] r_next;





    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)
            r_reg   <= 0;
        else
            r_reg   <= r_next;
    end


    assign r_next = (r_reg == (MAX-1)) ? 0 : (r_reg+1);


    assign max_tick = (r_reg == (MAX-1)) ? 1'b1 : 1'b0;
    assign counter = r_reg;
    
endmodule