data/full_repos/permissive/439731184/counter.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/439731184/counter.v:8: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clock <= !clock;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/439731184/counter.v:12: Unsupported or unknown PLI call: $monitor\n    $monitor("%b\\t%h", clock, c);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/439731184/counter.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #10 $finish;\n    ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module simple_counter(); 

reg [3:0] c = 0;
reg clock = 0;

always @ (posedge clock) c <= c + 1;

always #1 clock <= !clock;

initial begin
    $display("clock\tc");
    $monitor("%b\t%h", clock, c);
    #10 $finish;
end

endmodule
module simple_counter();
 

reg [3:0] c = 0;
reg clock = 0;

always @ (posedge clock) c <= c + 1;

always #1 clock <= !clock;

initial begin
    $display("clock\tc");
    $monitor("%b\t%h", clock, c);
    #10 $finish;
end

endmodule