data/full_repos/permissive/526754936/accdnn/build_cifar10_quantized_parallel/src/ip1_layer.v
1: b"%Error: data/full_repos/permissive/526754936/accdnn/build_cifar10_quantized_parallel/src/ip1_layer.v:57: Cannot find file containing module: 'controller_v2'\ncontroller_v2 #(\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/526754936/accdnn/build_cifar10_quantized_parallel/src,data/full_repos/permissive/526754936/controller_v2\n             data/full_repos/permissive/526754936/accdnn/build_cifar10_quantized_parallel/src,data/full_repos/permissive/526754936/controller_v2.v\n             data/full_repos/permissive/526754936/accdnn/build_cifar10_quantized_parallel/src,data/full_repos/permissive/526754936/controller_v2.sv\n             controller_v2\n             controller_v2.v\n             controller_v2.sv\n             obj_dir/controller_v2\n             obj_dir/controller_v2.v\n             obj_dir/controller_v2.sv\n%Error: data/full_repos/permissive/526754936/accdnn/build_cifar10_quantized_parallel/src/ip1_layer.v:113: Cannot find file containing module: 'ip1_rm_ram'\nip1_rm_ram u_ip1_rm_ram_0(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/526754936/accdnn/build_cifar10_quantized_parallel/src/ip1_layer.v:122: Cannot find file containing module: 'ip1_wm_ram'\nip1_wm_ram u_ip1_wm_ram(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/526754936/accdnn/build_cifar10_quantized_parallel/src/ip1_layer.v:131: Cannot find file containing module: 'ip1_bm_ram'\nip1_bm_ram u_ip1_bm_ram(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/526754936/accdnn/build_cifar10_quantized_parallel/src/ip1_layer.v:136: Cannot find file containing module: 'vector_muladd'\nvector_muladd #(.CPF(4),\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526754936/accdnn/build_cifar10_quantized_parallel/src/ip1_layer.v:161: Cannot find file containing module: 'vector_muladd'\nvector_muladd #(.CPF(4),\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526754936/accdnn/build_cifar10_quantized_parallel/src/ip1_layer.v:186: Cannot find file containing module: 'vector_muladd'\nvector_muladd #(.CPF(4),\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526754936/accdnn/build_cifar10_quantized_parallel/src/ip1_layer.v:211: Cannot find file containing module: 'vector_muladd'\nvector_muladd #(.CPF(4),\n^~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module ip1_layer(
    clk,
    rst,
    dma_engineer_dout_eop,
    blob_din_rdy,
    dma_engineer_dout,
    blob_din_en,
    dma_engineer_req,
    dma_engineer_ack,
    blob_dout_en,
    dma_engineer_dout_en,
    dma_engineer_start_addr,
    dma_engineer_length,
    blob_dout_rdy,
    blob_dout_eop,
    blob_dout,
    blob_din_eop,
    blob_din);

input clk;
input rst;
input	dma_engineer_dout_eop;
output	blob_din_rdy;
input[511:0]	dma_engineer_dout;
input	blob_din_en;
output	dma_engineer_req;
input	dma_engineer_ack;
output	blob_dout_en;
input	dma_engineer_dout_en;
output[26:0]	dma_engineer_start_addr;
output[26:0]	dma_engineer_length;
input	blob_dout_rdy;
output	blob_dout_eop;
output[63:0]	blob_dout;
input	blob_din_eop;
input[511:0]	blob_din;


wire[3:0]	bm_rd_addr;
wire[63:0]	op_weight;
wire[15:0]	op_dout_0_0;
wire[63:0]	op_data_0;
wire[5:0]	double_buf_wr_addr;
wire[15:0]	op_bias;
wire	op_din_en;
wire[8:0]	rm_rd_addr;
wire[15:0]	op_dout_0_3;
wire[8:0]	double_buf_rd_addr;
wire	double_buf_wr_en;
wire[15:0]	op_dout_0_2;
wire	rm_wr_en;
wire[15:0]	op_dout_0_1;
wire[5:0]	rm_wr_addr;
wire	op_din_eop;


controller_v2 #(
.DB_W_IN (1),
.DB_H_IN (1),
.DB_C_IN (1024),
.DB_W_OUT (1),
.DB_H_OUT (1),
.DB_C_OUT (64),
.WB_W (1),
.WB_H (1),
.WB_C (1024),
.WB_K (64),
.GROUP (1),
.RM_WR_ADDR_WIDTH (6),
.RM_WR_NUM_PER_CHANNEL (32),
.RM_WR_STRIDE (1),
.RM_RING_LENGTH (2),
.RM_RD_PHY_ADDR_JUMP (1),
.RM_RD_ADDR_WIDTH (9),
.DOUBLE_BUF_WR_DEPTH (64),
.DOUBLE_BUF_RD_DEPTH (512),
.DOUBLE_BUF_WR_ADDR_WIDTH (6),
.DOUBLE_BUF_RD_ADDR_WIDTH (9),
.START_ADDR (1252),
.LENGTH (32),
.BM_RD_ADDR_WIDTH (4),
.CPF (4),
.KPF (4),
.STRIDE_H (0),
.STRIDE_W (0),
.PAD (0),
.OP_DELAY (5))
u_controller(
.clk(clk),
.rst(rst),
.rm_wr_en(rm_wr_en), 
.rm_wr_addr(rm_wr_addr),
.rm_rd_addr(rm_rd_addr),
.op_din_eop(op_din_eop),
.op_din_en(op_din_en),
.double_buf_wr_en(double_buf_wr_en),
.double_buf_wr_addr(double_buf_wr_addr),
.double_buf_rd_addr(double_buf_rd_addr),
.bm_rd_addr(bm_rd_addr),
.dma_engineer_req(dma_engineer_req),
.dma_engineer_ack(dma_engineer_ack),
.dma_engineer_dout_en(dma_engineer_dout_en),
.dma_engineer_dout_eop(dma_engineer_dout_eop),
.dma_engineer_start_addr(dma_engineer_start_addr),
.dma_engineer_length(dma_engineer_length),
.blob_din_rdy(blob_din_rdy),
.blob_din_en(blob_din_en), 
.blob_din_eop(blob_din_eop),
.blob_dout_rdy(blob_dout_rdy),
.blob_dout_en(blob_dout_en),
.blob_dout_eop(blob_dout_eop));

ip1_rm_ram u_ip1_rm_ram_0(
.clka(clk),
.wea(rm_wr_en),
.addra(rm_wr_addr),
.dina(blob_din[511:0]),
.clkb(clk),
.addrb(rm_rd_addr),
.doutb(op_data_0));

ip1_wm_ram u_ip1_wm_ram(
.clka(clk),
.wea(double_buf_wr_en),
.addra(double_buf_wr_addr),
.dina(dma_engineer_dout),
.clkb(clk),
.addrb(double_buf_rd_addr),
.doutb(op_weight));

ip1_bm_ram u_ip1_bm_ram(
.clka(clk),
.addra(bm_rd_addr),
.douta(op_bias));

vector_muladd #(.CPF(4),
.RELU(0),
.BN(0),
.DIN_Q(10),
.DOUT_Q(10),
.BN_SCALE_Q(6),
.BN_BIAS_Q(6),
.MID_Q(6),
.BIAS_DW(8),
.Q(4),
.DIN_DW(16), 
.DOUT_DW(16), 
.DATA_CHANNEL(1), 
.ACC_WIDTH(40), 
.WW(16))
u_vector_muladd_0_0(
.clk(clk),
.rst(rst),
.op_din_en(op_din_en),
.op_din_eop(op_din_eop),
.op_din(op_data_0), 
.op_weight({{{12{op_weight[15]}},op_weight[15:12]},{{12{op_weight[11]}},op_weight[11:8]},{{12{op_weight[7]}},op_weight[7:4]},{{12{op_weight[3]}},op_weight[3:0]}}),
.op_bias({{12{op_bias[3]}},op_bias[3:0]}),
.op_dout(op_dout_0_0));

vector_muladd #(.CPF(4),
.RELU(0),
.BN(0),
.DIN_Q(10),
.DOUT_Q(10),
.BN_SCALE_Q(6),
.BN_BIAS_Q(6),
.MID_Q(6),
.BIAS_DW(8),
.Q(4),
.DIN_DW(16), 
.DOUT_DW(16), 
.DATA_CHANNEL(1), 
.ACC_WIDTH(40), 
.WW(16))
u_vector_muladd_0_1(
.clk(clk),
.rst(rst),
.op_din_en(op_din_en),
.op_din_eop(op_din_eop),
.op_din(op_data_0), 
.op_weight({{{12{op_weight[31]}},op_weight[31:28]},{{12{op_weight[27]}},op_weight[27:24]},{{12{op_weight[23]}},op_weight[23:20]},{{12{op_weight[19]}},op_weight[19:16]}}),
.op_bias({{12{op_bias[7]}},op_bias[7:4]}),
.op_dout(op_dout_0_1));

vector_muladd #(.CPF(4),
.RELU(0),
.BN(0),
.DIN_Q(10),
.DOUT_Q(10),
.BN_SCALE_Q(6),
.BN_BIAS_Q(6),
.MID_Q(6),
.BIAS_DW(8),
.Q(4),
.DIN_DW(16), 
.DOUT_DW(16), 
.DATA_CHANNEL(1), 
.ACC_WIDTH(40), 
.WW(16))
u_vector_muladd_0_2(
.clk(clk),
.rst(rst),
.op_din_en(op_din_en),
.op_din_eop(op_din_eop),
.op_din(op_data_0), 
.op_weight({{{12{op_weight[47]}},op_weight[47:44]},{{12{op_weight[43]}},op_weight[43:40]},{{12{op_weight[39]}},op_weight[39:36]},{{12{op_weight[35]}},op_weight[35:32]}}),
.op_bias({{12{op_bias[11]}},op_bias[11:8]}),
.op_dout(op_dout_0_2));

vector_muladd #(.CPF(4),
.RELU(0),
.BN(0),
.DIN_Q(10),
.DOUT_Q(10),
.BN_SCALE_Q(6),
.BN_BIAS_Q(6),
.MID_Q(6),
.BIAS_DW(8),
.Q(4),
.DIN_DW(16), 
.DOUT_DW(16), 
.DATA_CHANNEL(1), 
.ACC_WIDTH(40), 
.WW(16))
u_vector_muladd_0_3(
.clk(clk),
.rst(rst),
.op_din_en(op_din_en),
.op_din_eop(op_din_eop),
.op_din(op_data_0), 
.op_weight({{{12{op_weight[63]}},op_weight[63:60]},{{12{op_weight[59]}},op_weight[59:56]},{{12{op_weight[55]}},op_weight[55:52]},{{12{op_weight[51]}},op_weight[51:48]}}),
.op_bias({{12{op_bias[15]}},op_bias[15:12]}),
.op_dout(op_dout_0_3));

assign blob_dout = {op_dout_0_3,op_dout_0_2,op_dout_0_1,op_dout_0_0};

endmodule
module ip1_layer(
    clk,
    rst,
    dma_engineer_dout_eop,
    blob_din_rdy,
    dma_engineer_dout,
    blob_din_en,
    dma_engineer_req,
    dma_engineer_ack,
    blob_dout_en,
    dma_engineer_dout_en,
    dma_engineer_start_addr,
    dma_engineer_length,
    blob_dout_rdy,
    blob_dout_eop,
    blob_dout,
    blob_din_eop,
    blob_din);


input clk;
input rst;
input	dma_engineer_dout_eop;
output	blob_din_rdy;
input[511:0]	dma_engineer_dout;
input	blob_din_en;
output	dma_engineer_req;
input	dma_engineer_ack;
output	blob_dout_en;
input	dma_engineer_dout_en;
output[26:0]	dma_engineer_start_addr;
output[26:0]	dma_engineer_length;
input	blob_dout_rdy;
output	blob_dout_eop;
output[63:0]	blob_dout;
input	blob_din_eop;
input[511:0]	blob_din;


wire[3:0]	bm_rd_addr;
wire[63:0]	op_weight;
wire[15:0]	op_dout_0_0;
wire[63:0]	op_data_0;
wire[5:0]	double_buf_wr_addr;
wire[15:0]	op_bias;
wire	op_din_en;
wire[8:0]	rm_rd_addr;
wire[15:0]	op_dout_0_3;
wire[8:0]	double_buf_rd_addr;
wire	double_buf_wr_en;
wire[15:0]	op_dout_0_2;
wire	rm_wr_en;
wire[15:0]	op_dout_0_1;
wire[5:0]	rm_wr_addr;
wire	op_din_eop;


controller_v2 #(
.DB_W_IN (1),
.DB_H_IN (1),
.DB_C_IN (1024),
.DB_W_OUT (1),
.DB_H_OUT (1),
.DB_C_OUT (64),
.WB_W (1),
.WB_H (1),
.WB_C (1024),
.WB_K (64),
.GROUP (1),
.RM_WR_ADDR_WIDTH (6),
.RM_WR_NUM_PER_CHANNEL (32),
.RM_WR_STRIDE (1),
.RM_RING_LENGTH (2),
.RM_RD_PHY_ADDR_JUMP (1),
.RM_RD_ADDR_WIDTH (9),
.DOUBLE_BUF_WR_DEPTH (64),
.DOUBLE_BUF_RD_DEPTH (512),
.DOUBLE_BUF_WR_ADDR_WIDTH (6),
.DOUBLE_BUF_RD_ADDR_WIDTH (9),
.START_ADDR (1252),
.LENGTH (32),
.BM_RD_ADDR_WIDTH (4),
.CPF (4),
.KPF (4),
.STRIDE_H (0),
.STRIDE_W (0),
.PAD (0),
.OP_DELAY (5))
u_controller(
.clk(clk),
.rst(rst),
.rm_wr_en(rm_wr_en), 
.rm_wr_addr(rm_wr_addr),
.rm_rd_addr(rm_rd_addr),
.op_din_eop(op_din_eop),
.op_din_en(op_din_en),
.double_buf_wr_en(double_buf_wr_en),
.double_buf_wr_addr(double_buf_wr_addr),
.double_buf_rd_addr(double_buf_rd_addr),
.bm_rd_addr(bm_rd_addr),
.dma_engineer_req(dma_engineer_req),
.dma_engineer_ack(dma_engineer_ack),
.dma_engineer_dout_en(dma_engineer_dout_en),
.dma_engineer_dout_eop(dma_engineer_dout_eop),
.dma_engineer_start_addr(dma_engineer_start_addr),
.dma_engineer_length(dma_engineer_length),
.blob_din_rdy(blob_din_rdy),
.blob_din_en(blob_din_en), 
.blob_din_eop(blob_din_eop),
.blob_dout_rdy(blob_dout_rdy),
.blob_dout_en(blob_dout_en),
.blob_dout_eop(blob_dout_eop));

ip1_rm_ram u_ip1_rm_ram_0(
.clka(clk),
.wea(rm_wr_en),
.addra(rm_wr_addr),
.dina(blob_din[511:0]),
.clkb(clk),
.addrb(rm_rd_addr),
.doutb(op_data_0));

ip1_wm_ram u_ip1_wm_ram(
.clka(clk),
.wea(double_buf_wr_en),
.addra(double_buf_wr_addr),
.dina(dma_engineer_dout),
.clkb(clk),
.addrb(double_buf_rd_addr),
.doutb(op_weight));

ip1_bm_ram u_ip1_bm_ram(
.clka(clk),
.addra(bm_rd_addr),
.douta(op_bias));

vector_muladd #(.CPF(4),
.RELU(0),
.BN(0),
.DIN_Q(10),
.DOUT_Q(10),
.BN_SCALE_Q(6),
.BN_BIAS_Q(6),
.MID_Q(6),
.BIAS_DW(8),
.Q(4),
.DIN_DW(16), 
.DOUT_DW(16), 
.DATA_CHANNEL(1), 
.ACC_WIDTH(40), 
.WW(16))
u_vector_muladd_0_0(
.clk(clk),
.rst(rst),
.op_din_en(op_din_en),
.op_din_eop(op_din_eop),
.op_din(op_data_0), 
.op_weight({{{12{op_weight[15]}},op_weight[15:12]},{{12{op_weight[11]}},op_weight[11:8]},{{12{op_weight[7]}},op_weight[7:4]},{{12{op_weight[3]}},op_weight[3:0]}}),
.op_bias({{12{op_bias[3]}},op_bias[3:0]}),
.op_dout(op_dout_0_0));

vector_muladd #(.CPF(4),
.RELU(0),
.BN(0),
.DIN_Q(10),
.DOUT_Q(10),
.BN_SCALE_Q(6),
.BN_BIAS_Q(6),
.MID_Q(6),
.BIAS_DW(8),
.Q(4),
.DIN_DW(16), 
.DOUT_DW(16), 
.DATA_CHANNEL(1), 
.ACC_WIDTH(40), 
.WW(16))
u_vector_muladd_0_1(
.clk(clk),
.rst(rst),
.op_din_en(op_din_en),
.op_din_eop(op_din_eop),
.op_din(op_data_0), 
.op_weight({{{12{op_weight[31]}},op_weight[31:28]},{{12{op_weight[27]}},op_weight[27:24]},{{12{op_weight[23]}},op_weight[23:20]},{{12{op_weight[19]}},op_weight[19:16]}}),
.op_bias({{12{op_bias[7]}},op_bias[7:4]}),
.op_dout(op_dout_0_1));

vector_muladd #(.CPF(4),
.RELU(0),
.BN(0),
.DIN_Q(10),
.DOUT_Q(10),
.BN_SCALE_Q(6),
.BN_BIAS_Q(6),
.MID_Q(6),
.BIAS_DW(8),
.Q(4),
.DIN_DW(16), 
.DOUT_DW(16), 
.DATA_CHANNEL(1), 
.ACC_WIDTH(40), 
.WW(16))
u_vector_muladd_0_2(
.clk(clk),
.rst(rst),
.op_din_en(op_din_en),
.op_din_eop(op_din_eop),
.op_din(op_data_0), 
.op_weight({{{12{op_weight[47]}},op_weight[47:44]},{{12{op_weight[43]}},op_weight[43:40]},{{12{op_weight[39]}},op_weight[39:36]},{{12{op_weight[35]}},op_weight[35:32]}}),
.op_bias({{12{op_bias[11]}},op_bias[11:8]}),
.op_dout(op_dout_0_2));

vector_muladd #(.CPF(4),
.RELU(0),
.BN(0),
.DIN_Q(10),
.DOUT_Q(10),
.BN_SCALE_Q(6),
.BN_BIAS_Q(6),
.MID_Q(6),
.BIAS_DW(8),
.Q(4),
.DIN_DW(16), 
.DOUT_DW(16), 
.DATA_CHANNEL(1), 
.ACC_WIDTH(40), 
.WW(16))
u_vector_muladd_0_3(
.clk(clk),
.rst(rst),
.op_din_en(op_din_en),
.op_din_eop(op_din_eop),
.op_din(op_data_0), 
.op_weight({{{12{op_weight[63]}},op_weight[63:60]},{{12{op_weight[59]}},op_weight[59:56]},{{12{op_weight[55]}},op_weight[55:52]},{{12{op_weight[51]}},op_weight[51:48]}}),
.op_bias({{12{op_bias[15]}},op_bias[15:12]}),
.op_dout(op_dout_0_3));

assign blob_dout = {op_dout_0_3,op_dout_0_2,op_dout_0_1,op_dout_0_0};

endmodule