data/full_repos/permissive/427221126/src/RAM.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/427221126/src/RAM.v:68: Multiple top level modules\n                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                    : ... Top module \'RAM1P\'\nmodule RAM1P\n       ^~~~~\n                                                                    : ... Top module \'RAM2P_WF_RO\'\nmodule RAM2P_WF_RO \n       ^~~~~~~~~~~\n                                                                    : ... Top module \'RAM_GLB\'\nmodule RAM_GLB \n       ^~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module RAM_GLB 
  #(
    parameter INWIDTH = 16,
              NUM_ELEM = 295160,
              ADDR_WIDTH = $clog2(NUM_ELEM)
  )
  (
    input                   clk   , 
    input                   reset , 
    input                   en    ,
    input                   we1   ,
    input                   we2   ,
    input  [ADDR_WIDTH-1:0] addr1 ,
    input  [ADDR_WIDTH-1:0] addr2 ,
    input  [INWIDTH-1:0]    di1   ,
    input  [INWIDTH-1:0]    di2   ,
    output [INWIDTH-1:0]    do1   ,
    output [INWIDTH-1:0]    do2 
  );
  reg [INWIDTH-1:0] ram_glb [0:NUM_ELEM-1];
  
  reg [INWIDTH-1:0] dout1, dout1_d;
  reg [INWIDTH-1:0] dout2, dout2_d;

  integer i;
  
  initial begin
    for (i = 0; i < NUM_ELEM; i = i + 1) begin
      ram_glb[i] = {INWIDTH{1'b0}};
    end
  end

  always @(posedge clk) begin
    if (reset) begin
      dout1 <= 0;
    end
    else if (en) begin
      dout1 <= ram_glb[addr1];
      if (we1) begin
        ram_glb[addr1] <= di1;
      end
    end
  end
  
  always @(posedge clk) begin
    if (reset) begin
      dout2 <= 0;
    end
    else if (en) begin
      dout2 <= ram_glb[addr2];
      if (we2) begin
        ram_glb[addr2] <= di2;
      end
    end
  end

  always @(posedge clk) begin
    dout1_d <= dout1;
    dout2_d <= dout2;
  end

  assign do1 = dout1_d;
  assign do2 = dout2_d;
endmodule
module RAM_GLB 
  #(
    parameter INWIDTH = 16,
              NUM_ELEM = 295160,
              ADDR_WIDTH = $clog2(NUM_ELEM)
  )
  (
    input                   clk   , 
    input                   reset , 
    input                   en    ,
    input                   we1   ,
    input                   we2   ,
    input  [ADDR_WIDTH-1:0] addr1 ,
    input  [ADDR_WIDTH-1:0] addr2 ,
    input  [INWIDTH-1:0]    di1   ,
    input  [INWIDTH-1:0]    di2   ,
    output [INWIDTH-1:0]    do1   ,
    output [INWIDTH-1:0]    do2 
  );

  reg [INWIDTH-1:0] ram_glb [0:NUM_ELEM-1];
  
  reg [INWIDTH-1:0] dout1, dout1_d;
  reg [INWIDTH-1:0] dout2, dout2_d;

  integer i;
  
  initial begin
    for (i = 0; i < NUM_ELEM; i = i + 1) begin
      ram_glb[i] = {INWIDTH{1'b0}};
    end
  end

  always @(posedge clk) begin
    if (reset) begin
      dout1 <= 0;
    end
    else if (en) begin
      dout1 <= ram_glb[addr1];
      if (we1) begin
        ram_glb[addr1] <= di1;
      end
    end
  end
  
  always @(posedge clk) begin
    if (reset) begin
      dout2 <= 0;
    end
    else if (en) begin
      dout2 <= ram_glb[addr2];
      if (we2) begin
        ram_glb[addr2] <= di2;
      end
    end
  end

  always @(posedge clk) begin
    dout1_d <= dout1;
    dout2_d <= dout2;
  end

  assign do1 = dout1_d;
  assign do2 = dout2_d;
endmodule