data/full_repos/permissive/514437299/digital/rtl/rng.v
1: b"%Error: data/full_repos/permissive/514437299/digital/rtl/rng.v:125: Cannot find file containing module: 'INVLONG_OSC23'\n  INVLONG_OSC23 U_RNG_OSC(\n  ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514437299/digital/rtl,data/full_repos/permissive/514437299/INVLONG_OSC23\n             data/full_repos/permissive/514437299/digital/rtl,data/full_repos/permissive/514437299/INVLONG_OSC23.v\n             data/full_repos/permissive/514437299/digital/rtl,data/full_repos/permissive/514437299/INVLONG_OSC23.sv\n             INVLONG_OSC23\n             INVLONG_OSC23.v\n             INVLONG_OSC23.sv\n             obj_dir/INVLONG_OSC23\n             obj_dir/INVLONG_OSC23.v\n             obj_dir/INVLONG_OSC23.sv\n%Error: data/full_repos/permissive/514437299/digital/rtl/rng.v:131: Cannot find file containing module: 'INVD2'\n  INVD2 U_RNG_OSC_DRV(\n  ^~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/rng.v:135: Cannot find file containing module: 'clkdiv'\n  clkdiv U_CLKDIV_RNG(\n  ^~~~~~\n%Error: Exiting due to 3 error(s)\n"
module rng
  #(parameter NINVERTER = 66)
  (
   input  wire                 clk_rng,
   input  wire                 clk_smp,
   input  wire                 rst_n,
   input  wire                 i_rng_psd_en,
   input  wire                 i_rng_osc_en,
   input  wire                 i_rng_osc_jit_en,
   input  wire [2:0]           i_rng_osc_jit_div,
   input  wire                 i_rng_ptb_en,
   input  wire                 i_rng_use_seed,
   input  wire [79:0]          i_rng_seed,
   output wire                 o_rng_osc_jit,
   output wire [79:0]          o_rng_state,
   output reg                  o_rng_initdone);

  reg       rndbit_sample;
  reg [1:0] rndbit_meta;
  reg       rndbit_valid;
  wire      rndbit;

  wire      clk_osc;
  wire      clk_osc_pre;

  reg [1:0] clk_smp_trn;

  wire      rndbit_lfsr_out;

  reg [6:0] cnter;





  INVLONG_OSC23 U_RNG_OSC(
    .EN  ( i_rng_osc_en ) ,
    .OUT ( clk_osc_pre  ) );


  INVD2 U_RNG_OSC_DRV(
    .I  ( clk_osc_pre ),
    .ZN ( clk_osc     ) );

  clkdiv U_CLKDIV_RNG(
    .clk        ( clk_osc           ) ,
    .rst_n      ( rst_n             ) ,
    .i_en       ( i_rng_osc_jit_en  ) ,
    .i_div      ( i_rng_osc_jit_div ) ,
    .o_clk_div  ( o_rng_osc_jit     ) ,
    .o_clk_all  () );

  always @(posedge clk_smp or negedge rst_n)
    if (!rst_n) rndbit_sample <= 1'b0;
    else        rndbit_sample <= clk_osc;

  always @(posedge clk_rng or negedge rst_n)
    if (!rst_n) clk_smp_trn <= 2'b0;
    else        clk_smp_trn <= { clk_smp_trn[0], clk_smp };

  always @(posedge clk_rng or negedge rst_n)
    if (!rst_n) begin
      rndbit_meta  <= 2'b0;
      rndbit_valid <= 1'b0;
    end else begin
      rndbit_meta  <= {rndbit_meta[0], rndbit_sample};
      rndbit_valid <= (clk_smp_trn == 2'b01) & i_rng_osc_en;
    end
  
  assign rndbit = rndbit_meta[1];





  lfsr43 U_LFSR43(
    .clk          ( clk_rng                          ) ,
    .rst_n        ( rst_n                            ) ,
    .i_en         ( i_rng_psd_en & o_rng_initdone    ) ,
    .i_ptb        ( rndbit                           ) ,
    .i_ptb_valid  ( rndbit_valid & i_rng_ptb_en      ) ,
    .i_si         ( rndbit                           ) ,
    .i_sr_valid   ( rndbit_valid & (~i_rng_use_seed) ) ,
    .i_state      ( i_rng_seed[42:0]                 ) ,
    .i_load_state ( i_rng_use_seed                   ) ,
    .o_so         ( rndbit_lfsr_out                  ) ,
    .o_state      ( o_rng_state[42:0]               ) );

  casr37 U_CASR37(
    .clk          ( clk_rng                          ) ,
    .rst_n        ( rst_n                            ) ,
    .i_en         ( i_rng_psd_en & o_rng_initdone    ) ,
    .i_ptb        ( rndbit                           ) ,
    .i_ptb_valid  ( rndbit_valid & i_rng_ptb_en      ) ,
    .i_si         ( rndbit_lfsr_out                  ) ,
    .i_sr_valid   ( rndbit_valid & (~i_rng_use_seed) ) ,
    .i_state      ( i_rng_seed[79:43]                 ) ,
    .i_load_state ( i_rng_use_seed                   ) ,
    .o_so         () ,
    .o_state      ( o_rng_state[79:43]                ) );


  always @(posedge clk_rng or negedge rst_n)
    if (!rst_n)                                 cnter <= 7'b0;
    else if (rndbit_valid && (!o_rng_initdone)) cnter <= cnter + 1'b1;

  always @(posedge clk_rng or negedge rst_n)
    if (!rst_n)                                  o_rng_initdone <= 1'b0;
    else if ((cnter >= 7'd80) || i_rng_use_seed) o_rng_initdone <= 1'b1;
  
endmodule
module rng
  #(parameter NINVERTER = 66)
  (
   input  wire                 clk_rng,
   input  wire                 clk_smp,
   input  wire                 rst_n,
   input  wire                 i_rng_psd_en,
   input  wire                 i_rng_osc_en,
   input  wire                 i_rng_osc_jit_en,
   input  wire [2:0]           i_rng_osc_jit_div,
   input  wire                 i_rng_ptb_en,
   input  wire                 i_rng_use_seed,
   input  wire [79:0]          i_rng_seed,
   output wire                 o_rng_osc_jit,
   output wire [79:0]          o_rng_state,
   output reg                  o_rng_initdone);


  reg       rndbit_sample;
  reg [1:0] rndbit_meta;
  reg       rndbit_valid;
  wire      rndbit;

  wire      clk_osc;
  wire      clk_osc_pre;

  reg [1:0] clk_smp_trn;

  wire      rndbit_lfsr_out;

  reg [6:0] cnter;





  INVLONG_OSC23 U_RNG_OSC(
    .EN  ( i_rng_osc_en ) ,
    .OUT ( clk_osc_pre  ) );


  INVD2 U_RNG_OSC_DRV(
    .I  ( clk_osc_pre ),
    .ZN ( clk_osc     ) );

  clkdiv U_CLKDIV_RNG(
    .clk        ( clk_osc           ) ,
    .rst_n      ( rst_n             ) ,
    .i_en       ( i_rng_osc_jit_en  ) ,
    .i_div      ( i_rng_osc_jit_div ) ,
    .o_clk_div  ( o_rng_osc_jit     ) ,
    .o_clk_all  () );

  always @(posedge clk_smp or negedge rst_n)
    if (!rst_n) rndbit_sample <= 1'b0;
    else        rndbit_sample <= clk_osc;

  always @(posedge clk_rng or negedge rst_n)
    if (!rst_n) clk_smp_trn <= 2'b0;
    else        clk_smp_trn <= { clk_smp_trn[0], clk_smp };

  always @(posedge clk_rng or negedge rst_n)
    if (!rst_n) begin
      rndbit_meta  <= 2'b0;
      rndbit_valid <= 1'b0;
    end else begin
      rndbit_meta  <= {rndbit_meta[0], rndbit_sample};
      rndbit_valid <= (clk_smp_trn == 2'b01) & i_rng_osc_en;
    end
  
  assign rndbit = rndbit_meta[1];





  lfsr43 U_LFSR43(
    .clk          ( clk_rng                          ) ,
    .rst_n        ( rst_n                            ) ,
    .i_en         ( i_rng_psd_en & o_rng_initdone    ) ,
    .i_ptb        ( rndbit                           ) ,
    .i_ptb_valid  ( rndbit_valid & i_rng_ptb_en      ) ,
    .i_si         ( rndbit                           ) ,
    .i_sr_valid   ( rndbit_valid & (~i_rng_use_seed) ) ,
    .i_state      ( i_rng_seed[42:0]                 ) ,
    .i_load_state ( i_rng_use_seed                   ) ,
    .o_so         ( rndbit_lfsr_out                  ) ,
    .o_state      ( o_rng_state[42:0]               ) );

  casr37 U_CASR37(
    .clk          ( clk_rng                          ) ,
    .rst_n        ( rst_n                            ) ,
    .i_en         ( i_rng_psd_en & o_rng_initdone    ) ,
    .i_ptb        ( rndbit                           ) ,
    .i_ptb_valid  ( rndbit_valid & i_rng_ptb_en      ) ,
    .i_si         ( rndbit_lfsr_out                  ) ,
    .i_sr_valid   ( rndbit_valid & (~i_rng_use_seed) ) ,
    .i_state      ( i_rng_seed[79:43]                 ) ,
    .i_load_state ( i_rng_use_seed                   ) ,
    .o_so         () ,
    .o_state      ( o_rng_state[79:43]                ) );


  always @(posedge clk_rng or negedge rst_n)
    if (!rst_n)                                 cnter <= 7'b0;
    else if (rndbit_valid && (!o_rng_initdone)) cnter <= cnter + 1'b1;

  always @(posedge clk_rng or negedge rst_n)
    if (!rst_n)                                  o_rng_initdone <= 1'b0;
    else if ((cnter >= 7'd80) || i_rng_use_seed) o_rng_initdone <= 1'b1;
  
endmodule