data/full_repos/permissive/47037127/dispatchu.v
1: b'%Error: data/full_repos/permissive/47037127/dispatchu.v:47: Cannot find file containing module: \'pointer\'\npointer stackPointer(CLK, stkpInc, stkpDec, ABBus, stkpWrite, stkPtrBus);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/47037127,data/full_repos/permissive/47037127/pointer\n             data/full_repos/permissive/47037127,data/full_repos/permissive/47037127/pointer.v\n             data/full_repos/permissive/47037127,data/full_repos/permissive/47037127/pointer.sv\n             pointer\n             pointer.v\n             pointer.sv\n             obj_dir/pointer\n             obj_dir/pointer.v\n             obj_dir/pointer.sv\n%Error: data/full_repos/permissive/47037127/dispatchu.v:59: Cannot find file containing module: \'pointer\'\npointer programCounter(CLK, pcInc, pcDec, pcInputBus[pcInputSel], pcWrite, PCBus);\n^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/47037127/dispatchu.v:97: Operator ASSIGNW expects 16 bits on the Assign RHS, but Assign RHS\'s SEL generates 15 bits.\n                                                                  : ... In instance dispatchu\nassign cOutMux[1]=curVals[14:0];\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/47037127/dispatchu.v:103: Cannot find file containing module: \'optyper\'\noptyper ot(op, load, store, branch, cmp, stack, ldl); \n^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/47037127/dispatchu.v:110: Bit extraction of array[3:0] requires 2 bit index, not 1 bits.\n                                                                   : ... In instance dispatchu\nassign intPipeOp=intPipeOpSelector[intOp];\n                                  ^\n%Error: data/full_repos/permissive/47037127/dispatchu.v:118: Cannot find file containing module: \'comparator\'\ncomparator comp(ADAT, BDAT, greater, less, same);\n^~~~~~~~~~\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module dispatchu(
  CLK,
  MEMDAT,
  ADAT,
  BDAT,
  CDAT,
  addr,
  memOut,
  memWrite,
  Cout,
  cWrite,
  Asel,
  Bsel,
  Csel,
  intPipeOp,
  intPipeA,
  intPipeB,
  intPipeC
  );
  
input CLK;
input [15:0] MEMDAT;
input [15:0] ADAT;
input [15:0] BDAT;
input [15:0] CDAT;
output [31:0] addr;
output [15:0] memOut;
output memWrite;
output [15:0] Cout;
output cWrite;
output [2:0] Asel;
output [2:0] Bsel;
output [2:0] Csel;
output [3:0] intPipeOp;
output [2:0] intPipeA;
output [2:0] intPipeB;
output [2:0] intPipeC;
  
reg stkpInc, stkpDec, stkpWrite;
wire [31:0] ABBus;
wire [31:0] stkPtrBus;
pointer stackPointer(CLK, stkpInc, stkpDec, ABBus, stkpWrite, stkPtrBus);

reg pcWrite;
wire pcInc, pcDec;
wire [31:0] PCBus;
wire [31:0] pcInputBus [1:0];
wire [31:0] extendedMemoryInputBus;
assign extendedMemoryInputBus[31:16]=0;
assign extendedMemoryInputBus[15:0]=MEMDAT;
assign pcInputBus[0]=ABBus;
assign pcInputBus[1]=extendedMemoryInputBus;
reg pcInputSel;
pointer programCounter(CLK, pcInc, pcDec, pcInputBus[pcInputSel], pcWrite, PCBus);

assign ABBus[31:16]=ADAT;
assign ABBus[15:0]=BDAT;

reg [15:0] memOutReg;
assign memOut=memOutReg;

wire [31:0] addrMux[0:2];




assign addrMux[0]=PCBus;
assign addrMux[1]=ABBus;
assign addrMux[2]=stkPtrBus;
reg [1:0] addrMuxSelector;
assign addr=addrMux[addrMuxSelector];

reg [15:0] curVals;
wire [6:0] op;
wire [2:0] a;
wire [2:0] b;
wire [2:0] c;
assign op=curVals[15:9];
assign a=curVals[8:6];
assign b=curVals[5:3];
assign c=curVals[2:0];
assign Asel=a;
assign Bsel=b;
assign Csel=c;
assign intPipeA=a;
assign intPipeB=b;
assign intPipeC=c;

wire [15:0] cOutMux[2:0];
reg [1:0] cSelector;
assign cOutMux[0]=MEMDAT;
assign cOutMux[1]=curVals[14:0];
assign cOutMux[2]=stkPtrBus[15:0];
assign Cout=cOutMux[cSelector];


wire load, store, branch, cmp, stack, ldl, call, intOp;
optyper ot(op, load, store, branch, cmp, stack, ldl);
assign intOp=(~load)&&(~store)&&(~branch)&&(~cmp)&&(~stack)&&(~ldl);


wire [3:0] intPipeOpSelector[3:0];
assign intPipeOpSelector[0]=0;
assign intPipeOpSelector[1]=op[3:0];
assign intPipeOp=intPipeOpSelector[intOp];

wire fetchNextOp;
assign fetchNextOp=intOp;



wire greater, less, same;
comparator comp(ADAT, BDAT, greater, less, same);

reg gFlag, lFlag, sFlag;

reg memWriteReg;
assign memWrite=memWriteReg;

reg stateReg;
reg cWriteReg;
assign cWrite=cWriteReg;
assign pcInc=~stateReg&&fetchNextOp;
assign pcDec=0;



always@(posedge CLK) begin
  if(stateReg) begin
    stateReg<=1'b0;

    addrMuxSelector<=0;
    
    if(op!=44&&op!=45) begin
      curVals<=0;
    end
    
    if(op==44) begin
      
    end
    
    else if(op==45) begin
      pcWrite<=0;
    end
    
    else if(stack) begin
      if(store) begin
	memWriteReg<=0;
	stkpDec<=0;
      end
      else begin
	stkpInc<=0;
	cWriteReg<=1;
      end
    end
    
    else if(~stack) begin
      if(store) begin
	memWriteReg<=0;
      end
      
      else begin
	cWriteReg<=0;
      end
    end
    
  end
  

  else begin 
    if(fetchNextOp) begin
      addrMuxSelector<=2'b00;
      curVals<=MEMDAT;
      cWriteReg<=0;
      stkpWrite<=0;

      pcInputSel<=0;
    end
    
    else if(ldl) begin
      curVals<=0;
      cSelector<=1;
      cWriteReg<=1;
    end
    
    else if(cmp) begin
      curVals<=0;
      gFlag<=greater;
      lFlag<=less;
      sFlag<=same;
    end
    

    else if(branch) begin
      if(op==51) begin
	pcWrite<=1;

	curVals<=0;
      end
      
      else if(op==52) begin
	if(same) begin
	  pcWrite<=1;
	  curVals<=0;
	end
	
	else begin
	  curVals<=MEMDAT;
	end
	
      end
      
      else if(op==53) begin
	if(greater) begin
	  pcWrite<=1;
	  curVals<=0;
	end
	
	else begin
	  curVals<=MEMDAT;
	end
      end
      
      else if(op==54) begin
	if(less) begin
	  pcWrite<=1;
	  curVals<=0;
	end
	
	else begin
	  curVals<=MEMDAT;
	end
      end
    end
    

    else if(op==40) begin
      cSelector<=2;
      cWriteReg<=1;
      curVals<=0;
    end
    
    else if(op==41) begin
      stkpWrite<=1;
      curVals<=0;
    end
    
    else if(op==44) begin

      addrMuxSelector<=2'b10;
      stkpDec<=1;

      memOutReg<=PCBus[15:0];
      memWriteReg<=1;
    end
    
    else if(op==55) begin
      stkpInc<=1;
      addrMuxSelector<=2'b10;
      pcInputSel<=1;
      pcWrite<=1;
      curVals<=MEMDAT;
    end
    

    else if(stack) begin
      stateReg<=1;
      addrMuxSelector<=2'b10;
      if(store) begin
	memWriteReg<=1'b1;
	stkpDec<=1;
	memOutReg<=CDAT;
      end
      
      else begin
	stkpInc<=1;
      end
    end
    
    else if(~stack) begin
      stateReg<=1;
      addrMuxSelector<=2'b01;
      
      if(store) begin
	memWriteReg<=1'b1;
	memOutReg<=CDAT;
      end
      
      else begin
	cSelector<=0;
	cWriteReg<=1;
      end
    end
  end
end

initial begin
  curVals<=0;
  addrMuxSelector<=0;
  stateReg<=0;
  memWriteReg<=0;
  memOutReg<=0;
  cSelector<=0;
  cWriteReg<=0;
  pcWrite<=0;
end

endmodule
module dispatchu(
  CLK,
  MEMDAT,
  ADAT,
  BDAT,
  CDAT,
  addr,
  memOut,
  memWrite,
  Cout,
  cWrite,
  Asel,
  Bsel,
  Csel,
  intPipeOp,
  intPipeA,
  intPipeB,
  intPipeC
  );

  
input CLK;
input [15:0] MEMDAT;
input [15:0] ADAT;
input [15:0] BDAT;
input [15:0] CDAT;
output [31:0] addr;
output [15:0] memOut;
output memWrite;
output [15:0] Cout;
output cWrite;
output [2:0] Asel;
output [2:0] Bsel;
output [2:0] Csel;
output [3:0] intPipeOp;
output [2:0] intPipeA;
output [2:0] intPipeB;
output [2:0] intPipeC;
  
reg stkpInc, stkpDec, stkpWrite;
wire [31:0] ABBus;
wire [31:0] stkPtrBus;
pointer stackPointer(CLK, stkpInc, stkpDec, ABBus, stkpWrite, stkPtrBus);

reg pcWrite;
wire pcInc, pcDec;
wire [31:0] PCBus;
wire [31:0] pcInputBus [1:0];
wire [31:0] extendedMemoryInputBus;
assign extendedMemoryInputBus[31:16]=0;
assign extendedMemoryInputBus[15:0]=MEMDAT;
assign pcInputBus[0]=ABBus;
assign pcInputBus[1]=extendedMemoryInputBus;
reg pcInputSel;
pointer programCounter(CLK, pcInc, pcDec, pcInputBus[pcInputSel], pcWrite, PCBus);

assign ABBus[31:16]=ADAT;
assign ABBus[15:0]=BDAT;

reg [15:0] memOutReg;
assign memOut=memOutReg;

wire [31:0] addrMux[0:2];




assign addrMux[0]=PCBus;
assign addrMux[1]=ABBus;
assign addrMux[2]=stkPtrBus;
reg [1:0] addrMuxSelector;
assign addr=addrMux[addrMuxSelector];

reg [15:0] curVals;
wire [6:0] op;
wire [2:0] a;
wire [2:0] b;
wire [2:0] c;
assign op=curVals[15:9];
assign a=curVals[8:6];
assign b=curVals[5:3];
assign c=curVals[2:0];
assign Asel=a;
assign Bsel=b;
assign Csel=c;
assign intPipeA=a;
assign intPipeB=b;
assign intPipeC=c;

wire [15:0] cOutMux[2:0];
reg [1:0] cSelector;
assign cOutMux[0]=MEMDAT;
assign cOutMux[1]=curVals[14:0];
assign cOutMux[2]=stkPtrBus[15:0];
assign Cout=cOutMux[cSelector];


wire load, store, branch, cmp, stack, ldl, call, intOp;
optyper ot(op, load, store, branch, cmp, stack, ldl);
assign intOp=(~load)&&(~store)&&(~branch)&&(~cmp)&&(~stack)&&(~ldl);


wire [3:0] intPipeOpSelector[3:0];
assign intPipeOpSelector[0]=0;
assign intPipeOpSelector[1]=op[3:0];
assign intPipeOp=intPipeOpSelector[intOp];

wire fetchNextOp;
assign fetchNextOp=intOp;



wire greater, less, same;
comparator comp(ADAT, BDAT, greater, less, same);

reg gFlag, lFlag, sFlag;

reg memWriteReg;
assign memWrite=memWriteReg;

reg stateReg;
reg cWriteReg;
assign cWrite=cWriteReg;
assign pcInc=~stateReg&&fetchNextOp;
assign pcDec=0;



always@(posedge CLK) begin
  if(stateReg) begin
    stateReg<=1'b0;

    addrMuxSelector<=0;
    
    if(op!=44&&op!=45) begin
      curVals<=0;
    end
    
    if(op==44) begin
      
    end
    
    else if(op==45) begin
      pcWrite<=0;
    end
    
    else if(stack) begin
      if(store) begin
	memWriteReg<=0;
	stkpDec<=0;
      end
      else begin
	stkpInc<=0;
	cWriteReg<=1;
      end
    end
    
    else if(~stack) begin
      if(store) begin
	memWriteReg<=0;
      end
      
      else begin
	cWriteReg<=0;
      end
    end
    
  end
  

  else begin 
    if(fetchNextOp) begin
      addrMuxSelector<=2'b00;
      curVals<=MEMDAT;
      cWriteReg<=0;
      stkpWrite<=0;

      pcInputSel<=0;
    end
    
    else if(ldl) begin
      curVals<=0;
      cSelector<=1;
      cWriteReg<=1;
    end
    
    else if(cmp) begin
      curVals<=0;
      gFlag<=greater;
      lFlag<=less;
      sFlag<=same;
    end
    

    else if(branch) begin
      if(op==51) begin
	pcWrite<=1;

	curVals<=0;
      end
      
      else if(op==52) begin
	if(same) begin
	  pcWrite<=1;
	  curVals<=0;
	end
	
	else begin
	  curVals<=MEMDAT;
	end
	
      end
      
      else if(op==53) begin
	if(greater) begin
	  pcWrite<=1;
	  curVals<=0;
	end
	
	else begin
	  curVals<=MEMDAT;
	end
      end
      
      else if(op==54) begin
	if(less) begin
	  pcWrite<=1;
	  curVals<=0;
	end
	
	else begin
	  curVals<=MEMDAT;
	end
      end
    end
    

    else if(op==40) begin
      cSelector<=2;
      cWriteReg<=1;
      curVals<=0;
    end
    
    else if(op==41) begin
      stkpWrite<=1;
      curVals<=0;
    end
    
    else if(op==44) begin

      addrMuxSelector<=2'b10;
      stkpDec<=1;

      memOutReg<=PCBus[15:0];
      memWriteReg<=1;
    end
    
    else if(op==55) begin
      stkpInc<=1;
      addrMuxSelector<=2'b10;
      pcInputSel<=1;
      pcWrite<=1;
      curVals<=MEMDAT;
    end
    

    else if(stack) begin
      stateReg<=1;
      addrMuxSelector<=2'b10;
      if(store) begin
	memWriteReg<=1'b1;
	stkpDec<=1;
	memOutReg<=CDAT;
      end
      
      else begin
	stkpInc<=1;
      end
    end
    
    else if(~stack) begin
      stateReg<=1;
      addrMuxSelector<=2'b01;
      
      if(store) begin
	memWriteReg<=1'b1;
	memOutReg<=CDAT;
      end
      
      else begin
	cSelector<=0;
	cWriteReg<=1;
      end
    end
  end
end

initial begin
  curVals<=0;
  addrMuxSelector<=0;
  stateReg<=0;
  memWriteReg<=0;
  memOutReg<=0;
  cSelector<=0;
  cWriteReg<=0;
  pcWrite<=0;
end

endmodule