data/full_repos/permissive/519893543/verilog/rtl/biquad/multb.v
data/verilator_xmls/50680b70-dec0-49cf-97ee-fe25a3aa56cb.xml
module multb #(
    parameter	DATAWIDTH = 12,
    parameter	COEFWIDTH = 16
)
	(
    `ifdef USE_POWER_PINS
		inout vccd1,
		inout vssd1,
    `endif 
	input clk,
	input nreset,
	input	[COEFWIDTH-2:0] a,
	input	[DATAWIDTH-2:0] b,
	output	[DATAWIDTH + COEFWIDTH - 3:0] r
	);

assign r = a*b;


endmodule
module multb #(
    parameter	DATAWIDTH = 12,
    parameter	COEFWIDTH = 16
)
	(
    `ifdef USE_POWER_PINS
		inout vccd1,
		inout vssd1,
    `endif 
	input clk,
	input nreset,
	input	[COEFWIDTH-2:0] a,
	input	[DATAWIDTH-2:0] b,
	output	[DATAWIDTH + COEFWIDTH - 3:0] r
	);


assign r = a*b;


endmodule