data/full_repos/permissive/516759878/RTL/Sim/testbench.v
1: b'%Error: data/full_repos/permissive/516759878/RTL/Sim/testbench.v:22: syntax error, unexpected \'/\'\n /\n ^\n%Warning-STMTDLY: data/full_repos/permissive/516759878/RTL/Sim/testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n    always #5 i_clk = ~i_clk ; \n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/516759878/RTL/Sim/testbench.v:42: Unsupported: Ignoring delay on this delayed statement.\n           #50000 data_in = 16\'b0100_0001_0110_0110;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/516759878/RTL/Sim/testbench.v:43: Unsupported: Ignoring delay on this delayed statement.\n           #50000 data_in = 16\'b0010_0011_0101_1110;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/516759878/RTL/Sim/testbench.v:44: Unsupported: Ignoring delay on this delayed statement.\n           #50000 data_in = 16\'b1010_1001_0110_0111;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/516759878/RTL/Sim/testbench.v:45: Unsupported: Ignoring delay on this delayed statement.\n           #50000 data_in = 16\'b0000_0001_0100_1010;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/516759878/RTL/Sim/testbench.v:46: Unsupported: Ignoring delay on this delayed statement.\n           #50000 data_in = 16\'b1111_0001_0111_1000;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/516759878/RTL/Sim/testbench.v:47: Unsupported: Ignoring delay on this delayed statement.\n           #50000 data_in = 16\'b0010_0011_0101_1011;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/516759878/RTL/Sim/testbench.v:48: Unsupported: Ignoring delay on this delayed statement.\n           #50000 data_in = 16\'b1100_1001_0111_0011;\n           ^\n%Error: Exiting due to 1 error(s), 8 warning(s)\n'
module testbench();
reg i_clk ;
reg [15:0] data_in ;
wire [3:0] an_seg ;
wire [6:0] Sseg_out ;


Top_Design DUT(i_clk  , data_in , an_seg , Sseg_out);
    
    
   initial
        begin
          i_clk = 1'b0;
           end
    always #5 i_clk = ~i_clk ; 
    
    initial 
        begin
            data_in = 16'b0000_0001_0100_0110;
           #50000 data_in = 16'b0100_0001_0110_0110;
           #50000 data_in = 16'b0010_0011_0101_1110;
           #50000 data_in = 16'b1010_1001_0110_0111;
           #50000 data_in = 16'b0000_0001_0100_1010;
           #50000 data_in = 16'b1111_0001_0111_1000;
           #50000 data_in = 16'b0010_0011_0101_1011;
           #50000 data_in = 16'b1100_1001_0111_0011;
           

           
          

           end
                
endmodule
module testbench();

reg i_clk ;
reg [15:0] data_in ;
wire [3:0] an_seg ;
wire [6:0] Sseg_out ;


Top_Design DUT(i_clk  , data_in , an_seg , Sseg_out);
    
    
   initial
        begin
          i_clk = 1'b0;
           end
    always #5 i_clk = ~i_clk ; 
    
    initial 
        begin
            data_in = 16'b0000_0001_0100_0110;
           #50000 data_in = 16'b0100_0001_0110_0110;
           #50000 data_in = 16'b0010_0011_0101_1110;
           #50000 data_in = 16'b1010_1001_0110_0111;
           #50000 data_in = 16'b0000_0001_0100_1010;
           #50000 data_in = 16'b1111_0001_0111_1000;
           #50000 data_in = 16'b0010_0011_0101_1011;
           #50000 data_in = 16'b1100_1001_0111_0011;
           

           
          

           end
                
endmodule