data/full_repos/permissive/441359809/src/yosys/tests/techmap/mem_simple_4x1_uut.v
1: b'%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/techmap/mem_simple_4x1_uut.v:11: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'counter\' generates 5 bits.\n                                                                                                    : ... In instance uut\n memory[counter] <= counter;\n                 ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module uut (clk, rst, out, counter);

input clk, rst;
output reg [7:0] out;
output reg [4:0] counter;

reg [7:0] memory [0:19];

always @(posedge clk) begin
	counter <= rst || counter == 19 ? 0 : counter+1;
	memory[counter] <= counter;
	out <= memory[counter];
end

endmodule
module uut (clk, rst, out, counter);


input clk, rst;
output reg [7:0] out;
output reg [4:0] counter;

reg [7:0] memory [0:19];

always @(posedge clk) begin
	counter <= rst || counter == 19 ? 0 : counter+1;
	memory[counter] <= counter;
	out <= memory[counter];
end

endmodule