data/full_repos/permissive/43858668/final_verilog/src/clib/c_regfile.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_regfile.v:36: Cannot find include file: c_functions.v\n`include "c_functions.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v.sv\n             c_functions.v\n             c_functions.v.v\n             c_functions.v.sv\n             obj_dir/c_functions.v\n             obj_dir/c_functions.v.v\n             obj_dir/c_functions.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_regfile.v:37: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_regfile.v:52: Define or directive not defined: \'`REGFILE_TYPE_FF_2D\'\n   parameter regfile_type = `REGFILE_TYPE_FF_2D;\n                            ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_regfile.v:52: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter regfile_type = `REGFILE_TYPE_FF_2D;\n                                               ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_regfile.v:84: Define or directive not defined: \'`REGFILE_TYPE_FF_2D\'\n `REGFILE_TYPE_FF_2D:\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_regfile.v:84: syntax error, unexpected \':\', expecting endcase\n `REGFILE_TYPE_FF_2D:\n                    ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_regfile.v:114: syntax error, unexpected end\n        end\n        ^~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_regfile.v:132: Define or directive not defined: \'`REGFILE_TYPE_FF_1D_MUX\'\n `REGFILE_TYPE_FF_1D_MUX, `REGFILE_TYPE_FF_1D_SEL:\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_regfile.v:132: Define or directive not defined: \'`REGFILE_TYPE_FF_1D_SEL\'\n `REGFILE_TYPE_FF_1D_MUX, `REGFILE_TYPE_FF_1D_SEL:\n                          ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_regfile.v:218: Define or directive not defined: \'`REGFILE_TYPE_FF_1D_SEL\'\n      `REGFILE_TYPE_FF_1D_SEL:\n      ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_regfile.v:218: syntax error, unexpected \':\', expecting endcase\n      `REGFILE_TYPE_FF_1D_SEL:\n                             ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_regfile.v:238: Define or directive not defined: \'`REGFILE_TYPE_FF_1D_MUX\'\n      `REGFILE_TYPE_FF_1D_MUX:\n      ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_regfile.v:239: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n        begin\n        ^~~~~\n%Error: Cannot continue\n'
module c_regfile
  (clk, write_active, write_enable, write_address, write_data, read_address, 
   read_data);
   
`include "c_functions.v"
`include "c_constants.v"
   

   parameter depth = 8;
   

   parameter width = 64;
   

   parameter num_write_ports = 1;
   

   parameter num_read_ports = 1;
   

   parameter regfile_type = `REGFILE_TYPE_FF_2D;
   

   localparam addr_width = clogb(depth);
   
   input clk;
   
   input write_active;
   

   input [0:num_write_ports-1] write_enable;
   

   input [0:num_write_ports*addr_width-1] write_address;
   

   input [0:num_write_ports*width-1] 	  write_data;
   

   input [0:num_read_ports*addr_width-1]  read_address;
   

   output [0:num_read_ports*width-1] 	  read_data;
   wire [0:num_read_ports*width-1] 	  read_data;
   
   genvar 				  read_port;
   genvar 				  write_port;
   
   generate
      
      case(regfile_type)
	
	`REGFILE_TYPE_FF_2D:
	  begin
	     
	     if(num_write_ports == 1)
	       begin
		  
		  reg [0:width-1] storage_2d [0:depth-1];
		  
		  always @(posedge clk)
		    if(write_active)
		      if(write_enable)
			storage_2d[write_address] <= write_data;
		  
		  for(read_port = 0; read_port < num_read_ports; 
		      read_port = read_port + 1)
		    begin:read_ports_2d
		       
		       wire [0:addr_width-1] port_read_address;
		       assign port_read_address
			 = read_address[read_port*addr_width:
					(read_port+1)*addr_width-1];
		       
		       wire [0:width-1]      port_read_data;
		       assign port_read_data = storage_2d[port_read_address];
		       
		       assign read_data[read_port*width:(read_port+1)*width-1]
			 = port_read_data;
		       
		    end
		  
	       end
	     else
	       begin
		  

		  initial
		    begin
		       $display({"ERROR: Register file %m does not support ",
				 "2D FF array register file models with %d ",
				 "write ports."}, num_write_ports);
		       $stop;
		    end

		  
	       end
	     
	  end
	
	`REGFILE_TYPE_FF_1D_MUX, `REGFILE_TYPE_FF_1D_SEL:
	  begin
	     
	     wire [0:num_write_ports*depth-1] write_sel_by_port;

	     for(write_port = 0; write_port < num_write_ports;
		 write_port = write_port + 1)
	       begin:write_ports_1d
		  
		  wire [0:addr_width-1] port_write_address;
		  assign port_write_address
		    = write_address[write_port*addr_width:
				    (write_port+1)*addr_width-1];
		  
		  wire [0:depth-1] 	port_write_sel;
		  c_decode
		    #(.num_ports(depth))
		  port_write_sel_dec
		    (.data_in(port_write_address),
		     .data_out(port_write_sel));
		  
		  assign write_sel_by_port[write_port*depth:
					   (write_port+1)*depth-1]
		    = port_write_sel;
		  
	       end
	     
	     wire [0:depth*num_write_ports-1] write_sel_by_level;
	     c_interleave
	       #(.width(num_write_ports*depth),
		 .num_blocks(num_write_ports))
	     write_sel_by_level_intl
	       (.data_in(write_sel_by_port),
		.data_out(write_sel_by_level));
	     
	     wire [0:depth*width-1] 	      storage_1d;
	     
	     genvar 			      level;
	     
	     for(level = 0; level < depth; level = level + 1)
	       begin:levels
		  
		  wire [0:num_write_ports-1] lvl_write_sel;
		  assign lvl_write_sel
		    = write_sel_by_level[level*num_write_ports:
					 (level+1)*num_write_ports-1];
		  
		  wire [0:num_write_ports-1] lvl_port_write;
		  assign lvl_port_write = write_enable & lvl_write_sel;
		  
		  wire 			     lvl_write_enable;
		  assign lvl_write_enable = |lvl_port_write;
		  
		  wire [0:width-1] 	     lvl_write_data;
		  c_select_1ofn
		    #(.num_ports(num_write_ports),
		      .width(width))
		  lvl_write_data_sel
		    (.select(lvl_port_write),
		     .data_in(write_data),
		     .data_out(lvl_write_data));
		  
		  reg [0:width-1] 	     storage;
		  
		  always @(posedge clk)
		    if(write_active)
		      if(lvl_write_enable)
			storage <= lvl_write_data;
		  
		  assign storage_1d[level*width:(level+1)*width-1] = storage;
		  
	       end
	     
	     for(read_port = 0; read_port < num_read_ports; 
		 read_port = read_port + 1)
	       begin:read_ports_1d
		  
		  wire [0:addr_width-1] port_read_address;
		  assign port_read_address
		    = read_address[read_port*addr_width:
				   (read_port+1)*addr_width-1];
		  
		  wire [0:width-1] 	port_read_data;
		  
		  case(regfile_type)
		    
		    `REGFILE_TYPE_FF_1D_SEL:
		      begin
			 
			 wire [0:depth-1] port_read_sel;
			 c_decode
			   #(.num_ports(depth))
			 port_read_sel_dec
			   (.data_in(port_read_address),
			    .data_out(port_read_sel));
			 
			 c_select_1ofn
			   #(.num_ports(depth),
			     .width(width))
			 port_read_data_sel
			   (.select(port_read_sel),
			    .data_in(storage_1d),
			    .data_out(port_read_data));
			 
		      end
		    
		    `REGFILE_TYPE_FF_1D_MUX:
		      begin
			 
			 assign port_read_data
			   = storage_1d[port_read_address*width +: width];
			 
		      end
		    
		  endcase
		  
		  assign read_data[read_port*width:(read_port+1)*width-1]
		    = port_read_data;
		  
	       end
	     
	  end
	
      endcase
      
      



      

      
      if(depth < 2)
	begin
	   initial
	     begin
		$display({"ERROR: Register file module %m requires a depth ", 
			  "of two or more entries."});
		$stop;
	     end
	end
      

      
   endgenerate
   
endmodule
module c_regfile
  (clk, write_active, write_enable, write_address, write_data, read_address, 
   read_data);

   
`include "c_functions.v"
`include "c_constants.v"
   

   parameter depth = 8;
   

   parameter width = 64;
   

   parameter num_write_ports = 1;
   

   parameter num_read_ports = 1;
   

   parameter regfile_type = `REGFILE_TYPE_FF_2D;
   

   localparam addr_width = clogb(depth);
   
   input clk;
   
   input write_active;
   

   input [0:num_write_ports-1] write_enable;
   

   input [0:num_write_ports*addr_width-1] write_address;
   

   input [0:num_write_ports*width-1] 	  write_data;
   

   input [0:num_read_ports*addr_width-1]  read_address;
   

   output [0:num_read_ports*width-1] 	  read_data;
   wire [0:num_read_ports*width-1] 	  read_data;
   
   genvar 				  read_port;
   genvar 				  write_port;
   
   generate
      
      case(regfile_type)
	
	`REGFILE_TYPE_FF_2D:
	  begin
	     
	     if(num_write_ports == 1)
	       begin
		  
		  reg [0:width-1] storage_2d [0:depth-1];
		  
		  always @(posedge clk)
		    if(write_active)
		      if(write_enable)
			storage_2d[write_address] <= write_data;
		  
		  for(read_port = 0; read_port < num_read_ports; 
		      read_port = read_port + 1)
		    begin:read_ports_2d
		       
		       wire [0:addr_width-1] port_read_address;
		       assign port_read_address
			 = read_address[read_port*addr_width:
					(read_port+1)*addr_width-1];
		       
		       wire [0:width-1]      port_read_data;
		       assign port_read_data = storage_2d[port_read_address];
		       
		       assign read_data[read_port*width:(read_port+1)*width-1]
			 = port_read_data;
		       
		    end
		  
	       end
	     else
	       begin
		  

		  initial
		    begin
		       $display({"ERROR: Register file %m does not support ",
				 "2D FF array register file models with %d ",
				 "write ports."}, num_write_ports);
		       $stop;
		    end

		  
	       end
	     
	  end
	
	`REGFILE_TYPE_FF_1D_MUX, `REGFILE_TYPE_FF_1D_SEL:
	  begin
	     
	     wire [0:num_write_ports*depth-1] write_sel_by_port;

	     for(write_port = 0; write_port < num_write_ports;
		 write_port = write_port + 1)
	       begin:write_ports_1d
		  
		  wire [0:addr_width-1] port_write_address;
		  assign port_write_address
		    = write_address[write_port*addr_width:
				    (write_port+1)*addr_width-1];
		  
		  wire [0:depth-1] 	port_write_sel;
		  c_decode
		    #(.num_ports(depth))
		  port_write_sel_dec
		    (.data_in(port_write_address),
		     .data_out(port_write_sel));
		  
		  assign write_sel_by_port[write_port*depth:
					   (write_port+1)*depth-1]
		    = port_write_sel;
		  
	       end
	     
	     wire [0:depth*num_write_ports-1] write_sel_by_level;
	     c_interleave
	       #(.width(num_write_ports*depth),
		 .num_blocks(num_write_ports))
	     write_sel_by_level_intl
	       (.data_in(write_sel_by_port),
		.data_out(write_sel_by_level));
	     
	     wire [0:depth*width-1] 	      storage_1d;
	     
	     genvar 			      level;
	     
	     for(level = 0; level < depth; level = level + 1)
	       begin:levels
		  
		  wire [0:num_write_ports-1] lvl_write_sel;
		  assign lvl_write_sel
		    = write_sel_by_level[level*num_write_ports:
					 (level+1)*num_write_ports-1];
		  
		  wire [0:num_write_ports-1] lvl_port_write;
		  assign lvl_port_write = write_enable & lvl_write_sel;
		  
		  wire 			     lvl_write_enable;
		  assign lvl_write_enable = |lvl_port_write;
		  
		  wire [0:width-1] 	     lvl_write_data;
		  c_select_1ofn
		    #(.num_ports(num_write_ports),
		      .width(width))
		  lvl_write_data_sel
		    (.select(lvl_port_write),
		     .data_in(write_data),
		     .data_out(lvl_write_data));
		  
		  reg [0:width-1] 	     storage;
		  
		  always @(posedge clk)
		    if(write_active)
		      if(lvl_write_enable)
			storage <= lvl_write_data;
		  
		  assign storage_1d[level*width:(level+1)*width-1] = storage;
		  
	       end
	     
	     for(read_port = 0; read_port < num_read_ports; 
		 read_port = read_port + 1)
	       begin:read_ports_1d
		  
		  wire [0:addr_width-1] port_read_address;
		  assign port_read_address
		    = read_address[read_port*addr_width:
				   (read_port+1)*addr_width-1];
		  
		  wire [0:width-1] 	port_read_data;
		  
		  case(regfile_type)
		    
		    `REGFILE_TYPE_FF_1D_SEL:
		      begin
			 
			 wire [0:depth-1] port_read_sel;
			 c_decode
			   #(.num_ports(depth))
			 port_read_sel_dec
			   (.data_in(port_read_address),
			    .data_out(port_read_sel));
			 
			 c_select_1ofn
			   #(.num_ports(depth),
			     .width(width))
			 port_read_data_sel
			   (.select(port_read_sel),
			    .data_in(storage_1d),
			    .data_out(port_read_data));
			 
		      end
		    
		    `REGFILE_TYPE_FF_1D_MUX:
		      begin
			 
			 assign port_read_data
			   = storage_1d[port_read_address*width +: width];
			 
		      end
		    
		  endcase
		  
		  assign read_data[read_port*width:(read_port+1)*width-1]
		    = port_read_data;
		  
	       end
	     
	  end
	
      endcase
      
      



      

      
      if(depth < 2)
	begin
	   initial
	     begin
		$display({"ERROR: Register file module %m requires a depth ", 
			  "of two or more entries."});
		$stop;
	     end
	end
      

      
   endgenerate
   
endmodule