data/full_repos/permissive/488739248/rtl/ttl/ttl_74245_2dly.v
data/verilator_xmls/f4867916-d630-440b-bed9-3baa92458b2e.xml
module ttl_74245_2dly #(parameter DELAY_AB = 12, DELAY_BA = 12)
(
    input wire DIR,
    input wire Enable_bar,
    inout wire [7:0] A,
    inout wire [7:0] B
);
    assign #DELAY_BA A = (Enable_bar ||  DIR) ? 8'hzz : B;
    assign #DELAY_AB B = (Enable_bar || !DIR) ? 8'hzz : A;
endmodule
module ttl_74245_2dly #(parameter DELAY_AB = 12, DELAY_BA = 12)
(
    input wire DIR,
    input wire Enable_bar,
    inout wire [7:0] A,
    inout wire [7:0] B
);

    assign #DELAY_BA A = (Enable_bar ||  DIR) ? 8'hzz : B;
    assign #DELAY_AB B = (Enable_bar || !DIR) ? 8'hzz : A;
endmodule