data/full_repos/permissive/468755927/verilog/rtl/step_motor_controller.v
1: b'%Warning-WIDTH: data/full_repos/permissive/468755927/verilog/rtl/step_motor_controller.v:345: Operator SUB expects 24 bits on the LHS, but LHS\'s VARREF \'cycles\' generates 16 bits.\n                                                                                            : ... In instance step_motor_controller.i_step_motor_controller_registers\n  assign next_cycles = cycles - 1\'b1;\n                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/468755927/verilog/rtl/step_motor_controller.v:372: Operator ASSIGNDLY expects 21 bits on the Assign RHS, but Assign RHS\'s CONST \'11\'h0\' generates 11 bits.\n                                                                                            : ... In instance step_motor_controller.i_step_motor_controller_registers\n            wbs_dat_o[28:8] <= 11\'b0;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/468755927/verilog/rtl/step_motor_controller.v:432: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'next_cycles\' generates 24 bits.\n                                                                                            : ... In instance step_motor_controller.i_step_motor_controller_registers\n        cycles <= next_cycles;\n               ^~\n%Error: data/full_repos/permissive/468755927/verilog/rtl/step_motor_controller.v:60: Cannot find file containing module: \'prescaler\'\n  prescaler #(\n  ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/468755927/verilog/rtl,data/full_repos/permissive/468755927/prescaler\n             data/full_repos/permissive/468755927/verilog/rtl,data/full_repos/permissive/468755927/prescaler.v\n             data/full_repos/permissive/468755927/verilog/rtl,data/full_repos/permissive/468755927/prescaler.sv\n             prescaler\n             prescaler.v\n             prescaler.sv\n             obj_dir/prescaler\n             obj_dir/prescaler.v\n             obj_dir/prescaler.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module motor_sequencer #(
  parameter DSIZE = 32
)(
  input  wire             rst_n         ,
  input  wire             clk           ,
  input  wire             clear_n       ,
  input  wire             ptype         ,
  input  wire             mode          ,
  input  wire             direction     ,
  input  wire [DSIZE-1:0] period        ,
  input  wire             run           ,
  output reg              step_strobe   ,


  input  wire             start         ,
  input  wire             pwm           ,


  output reg              motor_a1      ,
  output reg              motor_a2      ,
  output reg              motor_b1      ,
  output reg              motor_b2
);

  reg  [2:0]       motor_state;
  reg  [DSIZE-1:0] counter;
  reg              pwmo;

  wire [DSIZE-1:0] next_counter;
  wire [3:0]       motor_values[7:0];

  assign next_counter = counter + 1'b1;
  assign motor_values[0] = 4'b1_0_0_1;
  assign motor_values[1] = 4'b0_0_0_1;
  assign motor_values[2] = 4'b0_0_1_1;
  assign motor_values[3] = 4'b0_0_1_0;
  assign motor_values[4] = 4'b0_1_1_0;
  assign motor_values[5] = 4'b0_1_0_0;
  assign motor_values[6] = 4'b1_1_0_0;
  assign motor_values[7] = 4'b1_0_0_0;



  always @(negedge rst_n or posedge clk) begin
    if (rst_n == 1'b0) begin
      counter     <= {(DSIZE){1'b0}};
      step_strobe <= 1'b0;
      pwmo        <= 1'b0;
      motor_state <= 3'b000;
      motor_a1    <= 1'b0;
      motor_a2    <= 1'b0;
      motor_b1    <= 1'b0;
      motor_b2    <= 1'b0;
    end else begin

      if (clear_n == 1'b0) begin
        counter     <= {(DSIZE){1'b0}};
        step_strobe <= 1'b0;
        pwmo        <= 1'b0;
        motor_state <= 3'b000;
        motor_a1    <= 1'b0;
        motor_a2    <= 1'b0;
        motor_b1    <= 1'b0;
        motor_b2    <= 1'b0;
      end else begin

        if (run == 1'b0) begin
          counter <= {(DSIZE){1'b0}};
        end else if (start == 1'b1) begin
          if (counter < period) begin
            counter <= next_counter;
          end else begin
            counter <= {(DSIZE){1'b0}};
            if (direction == 1'b0) begin
              motor_state <= motor_state + 1'b1;
            end else begin
              motor_state <= motor_state - 1'b1;
            end
          end
        end

        if ((run == 1'b1) && (start == 1'b1) && (counter >= period)) begin
          step_strobe <= 1'b1;
        end else begin
          step_strobe <= 1'b0;
        end

        pwmo <= pwm;

        if (ptype == 1'b0) begin
          motor_a1 <= motor_values[motor_state & {2'b11, mode}][0] & pwmo ;
          motor_a2 <= motor_values[motor_state & {2'b11, mode}][1] & pwmo ;
          motor_b1 <= motor_values[motor_state & {2'b11, mode}][2] & pwmo ;
          motor_b2 <= motor_values[motor_state & {2'b11, mode}][3] & pwmo ;
        end else begin
          motor_a1 <= motor_values[motor_state & {2'b11, mode}][0] & pwmo ;
          motor_a2 <= motor_values[motor_state & {2'b11, mode}][2] & pwmo ;
          motor_b1 <= motor_values[motor_state & {2'b11, mode}][1] & pwmo ;
          motor_b2 <= motor_values[motor_state & {2'b11, mode}][3] & pwmo ;
        end

      end
    end
  end

endmodule
module motor_sequencer #(
  parameter DSIZE = 32
)(
  input  wire             rst_n         ,
  input  wire             clk           ,
  input  wire             clear_n       ,
  input  wire             ptype         ,
  input  wire             mode          ,
  input  wire             direction     ,
  input  wire [DSIZE-1:0] period        ,
  input  wire             run           ,
  output reg              step_strobe   ,


  input  wire             start         ,
  input  wire             pwm           ,


  output reg              motor_a1      ,
  output reg              motor_a2      ,
  output reg              motor_b1      ,
  output reg              motor_b2
);


  reg  [2:0]       motor_state;
  reg  [DSIZE-1:0] counter;
  reg              pwmo;

  wire [DSIZE-1:0] next_counter;
  wire [3:0]       motor_values[7:0];

  assign next_counter = counter + 1'b1;
  assign motor_values[0] = 4'b1_0_0_1;
  assign motor_values[1] = 4'b0_0_0_1;
  assign motor_values[2] = 4'b0_0_1_1;
  assign motor_values[3] = 4'b0_0_1_0;
  assign motor_values[4] = 4'b0_1_1_0;
  assign motor_values[5] = 4'b0_1_0_0;
  assign motor_values[6] = 4'b1_1_0_0;
  assign motor_values[7] = 4'b1_0_0_0;



  always @(negedge rst_n or posedge clk) begin
    if (rst_n == 1'b0) begin
      counter     <= {(DSIZE){1'b0}};
      step_strobe <= 1'b0;
      pwmo        <= 1'b0;
      motor_state <= 3'b000;
      motor_a1    <= 1'b0;
      motor_a2    <= 1'b0;
      motor_b1    <= 1'b0;
      motor_b2    <= 1'b0;
    end else begin

      if (clear_n == 1'b0) begin
        counter     <= {(DSIZE){1'b0}};
        step_strobe <= 1'b0;
        pwmo        <= 1'b0;
        motor_state <= 3'b000;
        motor_a1    <= 1'b0;
        motor_a2    <= 1'b0;
        motor_b1    <= 1'b0;
        motor_b2    <= 1'b0;
      end else begin

        if (run == 1'b0) begin
          counter <= {(DSIZE){1'b0}};
        end else if (start == 1'b1) begin
          if (counter < period) begin
            counter <= next_counter;
          end else begin
            counter <= {(DSIZE){1'b0}};
            if (direction == 1'b0) begin
              motor_state <= motor_state + 1'b1;
            end else begin
              motor_state <= motor_state - 1'b1;
            end
          end
        end

        if ((run == 1'b1) && (start == 1'b1) && (counter >= period)) begin
          step_strobe <= 1'b1;
        end else begin
          step_strobe <= 1'b0;
        end

        pwmo <= pwm;

        if (ptype == 1'b0) begin
          motor_a1 <= motor_values[motor_state & {2'b11, mode}][0] & pwmo ;
          motor_a2 <= motor_values[motor_state & {2'b11, mode}][1] & pwmo ;
          motor_b1 <= motor_values[motor_state & {2'b11, mode}][2] & pwmo ;
          motor_b2 <= motor_values[motor_state & {2'b11, mode}][3] & pwmo ;
        end else begin
          motor_a1 <= motor_values[motor_state & {2'b11, mode}][0] & pwmo ;
          motor_a2 <= motor_values[motor_state & {2'b11, mode}][2] & pwmo ;
          motor_b1 <= motor_values[motor_state & {2'b11, mode}][1] & pwmo ;
          motor_b2 <= motor_values[motor_state & {2'b11, mode}][3] & pwmo ;
        end

      end
    end
  end

endmodule