data/full_repos/permissive/420819839/Basics/Inverter.v
data/verilator_xmls/a53abd01-9e25-45e2-b346-56458b49d260.xml
module top_module( input in, output out );

    assign out = !in;

endmodule
module top_module( input in, output out );


    assign out = !in;

endmodule