data/full_repos/permissive/422317798/alu.v
data/verilator_xmls/c1a88ba6-4589-44ac-b2e0-4ab39463cb73.xml
module alu( clk, operand_a, operand_b, opcode, result);
    parameter DATA_WIDTH = 8;

    input clk;
    input[DATA_WIDTH-1:0]operand_a,operand_b;
    input [3:0] opcode;
    output reg[DATA_WIDTH-1:0] result;
    
  always@(posedge clk)
    begin
     case(opcode)
        4'b0000:
           result <= operand_a + operand_b ; 
        4'b0001:
           result <= operand_a - operand_b;
        default: result <= 8'bx; 
     endcase
     
    end
endmodule
module alu( clk, operand_a, operand_b, opcode, result);

    parameter DATA_WIDTH = 8;

    input clk;
    input[DATA_WIDTH-1:0]operand_a,operand_b;
    input [3:0] opcode;
    output reg[DATA_WIDTH-1:0] result;
    
  always@(posedge clk)
    begin
     case(opcode)
        4'b0000:
           result <= operand_a + operand_b ; 
        4'b0001:
           result <= operand_a - operand_b;
        default: result <= 8'bx; 
     endcase
     
    end
endmodule