data/full_repos/permissive/487368624/Lab M/cpu.v
1: b'%Error: Cannot find file containing module: M,data/full_repos/permissive/487368624\n        ... Looked in:\n             data/full_repos/permissive/487368624/Lab/M,data/full_repos/permissive/487368624\n             data/full_repos/permissive/487368624/Lab/M,data/full_repos/permissive/487368624.v\n             data/full_repos/permissive/487368624/Lab/M,data/full_repos/permissive/487368624.sv\n             M,data/full_repos/permissive/487368624\n             M,data/full_repos/permissive/487368624.v\n             M,data/full_repos/permissive/487368624.sv\n             obj_dir/M,data/full_repos/permissive/487368624\n             obj_dir/M,data/full_repos/permissive/487368624.v\n             obj_dir/M,data/full_repos/permissive/487368624.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/487368624/Lab\n%Error: Cannot find file containing module: M/cpu.v\n%Error: Exiting due to 3 error(s)\n'
module yPC(PCin, PC, PCp4,INT,entryPoint,branchImm,jImm,zero,isbranch,isjump);
    output [31:0] PCin;
    input [31:0] PC, PCp4, entryPoint, branchImm;
    input [31:0] jImm;
    input INT, zero, isbranch, isjump;
	wire [31:0] branchImmX4, jImmX4, jImmX4PPCp4, bTarget, choiceA, choiceB;
    wire doBranch, zf;


    assign branchImmX4[31:2] = branchImm[29:0];
    assign branchImmX4[1:0] = 2'b00;


    assign jImmX4[31:2] = jImm[29:0];
    assign jImmX4[1:0] = 2'b00;




    yAlu bALU(bTarget, zf, PC, branchImmX4, 3'b010);



    yAlu jALU(jImmX4PPCp4, zf, PC, jImmX4, 3'b010);


    and decide_do(doBranch, isbranch, zero);
    yMux #(32) mux1(choiceA, PCp4, bTarget, doBranch);
    yMux #(32) mux2(choiceB, choiceA, jImmX4PPCp4, isjump);
    yMux #(32) mux3(PCin, choiceB, entryPoint, INT);

endmodule
module yPC(PCin, PC, PCp4,INT,entryPoint,branchImm,jImm,zero,isbranch,isjump);

    output [31:0] PCin;
    input [31:0] PC, PCp4, entryPoint, branchImm;
    input [31:0] jImm;
    input INT, zero, isbranch, isjump;
	wire [31:0] branchImmX4, jImmX4, jImmX4PPCp4, bTarget, choiceA, choiceB;
    wire doBranch, zf;


    assign branchImmX4[31:2] = branchImm[29:0];
    assign branchImmX4[1:0] = 2'b00;


    assign jImmX4[31:2] = jImm[29:0];
    assign jImmX4[1:0] = 2'b00;




    yAlu bALU(bTarget, zf, PC, branchImmX4, 3'b010);



    yAlu jALU(jImmX4PPCp4, zf, PC, jImmX4, 3'b010);


    and decide_do(doBranch, isbranch, zero);
    yMux #(32) mux1(choiceA, PCp4, bTarget, doBranch);
    yMux #(32) mux2(choiceB, choiceA, jImmX4PPCp4, isjump);
    yMux #(32) mux3(PCin, choiceB, entryPoint, INT);

endmodule