data/full_repos/permissive/444555755/mp4/hdl/given_cache/array.sv
data/verilator_xmls/da7c1b47-3815-4be8-9537-5965b15f50ee.xml
module array #(parameter width = 1, parameter s_index = 3, parameter num_sets = 2**s_index)
(
  input clk,
  input logic load,
  input logic [s_index - 1:0] rindex,
  input logic [s_index - 1:0] windex,
  input logic [width-1:0] datain,
  output logic [width-1:0] dataout
);

logic [width-1:0] data [num_sets] = '{default: '0};












always_comb begin
  dataout = data[rindex];
end

always_ff @(posedge clk)
begin
    if(load)
        data[windex] <= datain;
end

endmodule
module array #(parameter width = 1, parameter s_index = 3, parameter num_sets = 2**s_index)
(
  input clk,
  input logic load,
  input logic [s_index - 1:0] rindex,
  input logic [s_index - 1:0] windex,
  input logic [width-1:0] datain,
  output logic [width-1:0] dataout
);


logic [width-1:0] data [num_sets] = '{default: '0};












always_comb begin
  dataout = data[rindex];
end

always_ff @(posedge clk)
begin
    if(load)
        data[windex] <= datain;
end

endmodule