data/full_repos/permissive/509809169/Circuits/Sequential Logic/Counters/4 digit decimal counter.v
1: b'%Error: Cannot find file containing module: Logic/Counters,data/full_repos/permissive/509809169\n        ... Looked in:\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/509809169\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/509809169.v\n             data/full_repos/permissive/509809169/Circuits/Sequential/Logic/Counters,data/full_repos/permissive/509809169.sv\n             Logic/Counters,data/full_repos/permissive/509809169\n             Logic/Counters,data/full_repos/permissive/509809169.v\n             Logic/Counters,data/full_repos/permissive/509809169.sv\n             obj_dir/Logic/Counters,data/full_repos/permissive/509809169\n             obj_dir/Logic/Counters,data/full_repos/permissive/509809169.v\n             obj_dir/Logic/Counters,data/full_repos/permissive/509809169.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/509809169/Circuits/Sequential\n%Error: Cannot find file containing module: Logic/Counters/4\n%Error: Cannot find file containing module: digit\n%Error: Cannot find file containing module: decimal\n%Error: Cannot find file containing module: counter.v\n%Error: Exiting due to 6 error(s)\n'
module top_module (
    input clk,
    input reset,
    output [3:1] ena,
    output [15:0] q);

    always @(*) begin
        ena[1] <= {q[3:0]==4'd9};
        ena[2] <= {q[7:4]==4'd9 && q[3:0] == 4'd9};
        ena[3] <= {q[11:8]==4'd9 && q[7:4] == 4'd9 && q[3:0] == 4'd9};
    end
    
    always @(posedge clk ) begin
        if(reset) begin
            q[15:0] <= 15'd0;
        end
        else begin
            if(q[3:0]<9) q[3:0]<=q[3:0]+1;
            else q[3:0]<=0;
            if(ena[1]) begin
                if(q[7:4]<9) q[7:4]<=q[7:4]+1;
                else q[7:0] <= 0;
            end
            if(ena[2]) begin
                if(q[11:8]<9) q[11:8]<=q[11:8]+1;
                else q[11:8] <= 0;
            end
            if(ena[3]) begin
                if(q[15:12]<9) q[15:12]<=q[15:12]+1;
                else q[15:12] <= 0;
            end
        end
    end
endmodule
module top_module (
    input clk,
    input reset,
    output [3:1] ena,
    output [15:0] q);


    always @(*) begin
        ena[1] <= {q[3:0]==4'd9};
        ena[2] <= {q[7:4]==4'd9 && q[3:0] == 4'd9};
        ena[3] <= {q[11:8]==4'd9 && q[7:4] == 4'd9 && q[3:0] == 4'd9};
    end
    
    always @(posedge clk ) begin
        if(reset) begin
            q[15:0] <= 15'd0;
        end
        else begin
            if(q[3:0]<9) q[3:0]<=q[3:0]+1;
            else q[3:0]<=0;
            if(ena[1]) begin
                if(q[7:4]<9) q[7:4]<=q[7:4]+1;
                else q[7:0] <= 0;
            end
            if(ena[2]) begin
                if(q[11:8]<9) q[11:8]<=q[11:8]+1;
                else q[11:8] <= 0;
            end
            if(ena[3]) begin
                if(q[15:12]<9) q[15:12]<=q[15:12]+1;
                else q[15:12] <= 0;
            end
        end
    end
endmodule