data/full_repos/permissive/459497172/verilog/rtl/sar_adc/sar_adc.sv
1: b"%Error: data/full_repos/permissive/459497172/verilog/rtl/sar_adc/sar_adc.sv:57: Cannot find file containing module: 'adc_reg'\nadc_reg u_adc_reg (\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/459497172/verilog/rtl/sar_adc,data/full_repos/permissive/459497172/adc_reg\n             data/full_repos/permissive/459497172/verilog/rtl/sar_adc,data/full_repos/permissive/459497172/adc_reg.v\n             data/full_repos/permissive/459497172/verilog/rtl/sar_adc,data/full_repos/permissive/459497172/adc_reg.sv\n             adc_reg\n             adc_reg.v\n             adc_reg.sv\n             obj_dir/adc_reg\n             obj_dir/adc_reg.v\n             obj_dir/adc_reg.sv\n%Error: data/full_repos/permissive/459497172/verilog/rtl/sar_adc/sar_adc.sv:82: Cannot find file containing module: 'ACMP'\n    ACMP COMP_0 (\n    ^~~~\n%Error: data/full_repos/permissive/459497172/verilog/rtl/sar_adc/sar_adc.sv:95: Cannot find file containing module: 'ACMP'\n    ACMP COMP_1 (\n    ^~~~\n%Error: data/full_repos/permissive/459497172/verilog/rtl/sar_adc/sar_adc.sv:108: Cannot find file containing module: 'ACMP'\n    ACMP COMP_2 (\n    ^~~~\n%Error: data/full_repos/permissive/459497172/verilog/rtl/sar_adc/sar_adc.sv:121: Cannot find file containing module: 'ACMP'\n    ACMP COMP_3 (\n    ^~~~\n%Error: data/full_repos/permissive/459497172/verilog/rtl/sar_adc/sar_adc.sv:133: Cannot find file containing module: 'ACMP'\n    ACMP COMP_4 (\n    ^~~~\n%Error: data/full_repos/permissive/459497172/verilog/rtl/sar_adc/sar_adc.sv:145: Cannot find file containing module: 'ACMP'\n    ACMP COMP_5 (\n    ^~~~\n%Error: data/full_repos/permissive/459497172/verilog/rtl/sar_adc/sar_adc.sv:158: Cannot find file containing module: 'SAR'\n    SAR CTRL ( \n    ^~~\n%Error: Exiting due to 8 error(s)\n"
module sar_adc(
`ifdef USE_POWER_PINS
    input logic             vccd1         ,
    input logic             vssd1         ,
    input logic             vccd2         ,
    input logic             vssd2         ,
`endif

    
    input  logic            clk           ,
    input  logic            reset_n       ,


    input logic             reg_cs        ,
    input logic             reg_wr        ,
    input logic [7:0]       reg_addr      ,
    input logic [31:0]      reg_wdata     ,
    input logic [3:0]       reg_be        ,


    output logic [31:0]     reg_rdata     ,
    output logic            reg_ack       ,

    input  logic            pulse1m_mclk  ,
    output  logic [7:0]     sar2dac       ,

    input   logic           analog_dac_out,


    input   logic    [5:0]  analog_din

);

    logic        clkn;
    logic [5:0]  sar_cmp;
    logic        sar_cmp_int;
    logic [2:0]  adc_ch_no;
    logic        start_conv    ;
    logic        conv_done     ;
    logic [7:0]  adc_result    ;
  
always_comb 
begin
   sar_cmp_int = 0;
   case(adc_ch_no)
   3'b000 :  sar_cmp_int = sar_cmp[0];
   3'b001 :  sar_cmp_int = sar_cmp[1];
   3'b010 :  sar_cmp_int = sar_cmp[2];
   3'b011 :  sar_cmp_int = sar_cmp[3];
   3'b100 :  sar_cmp_int = sar_cmp[4];
   3'b101 :  sar_cmp_int = sar_cmp[5];
   endcase


end

adc_reg u_adc_reg (
        .mclk        (mclk),
        .reset_n     (reset_n),


        .reg_cs      (reg_cs),
        .reg_wr      (reg_wr),
        .reg_addr    (reg_addr),
        .reg_wdata   (reg_wdata),
        .reg_be      (reg_be),


        .reg_rdata   (reg_rdata),
        .reg_ack     (reg_ack),

	.pulse1m_mclk  (pulse1m_mclk),

       .start_conv   (start_conv),
       .adc_ch_no    (adc_ch_no),           
       .conv_done    (conv_done),
       .adc_result   (adc_result)

       );


    ACMP COMP_0 (
    `ifdef USE_POWER_PINS
        .vccd2   (vccd2           ),
        .vssd2   (vssd2           ),
        .VDD     (vccd2           ),
        .VSS     (vssd2           ),
    `endif
        .clk     (clk             ),
        .INP     (analog_din[0]   ),
        .INN     (analog_dac_out  ),
        .Q       (sar_cmp[0]      )    
    );

    ACMP COMP_1 (
    `ifdef USE_POWER_PINS
        .vccd2   (vccd2           ),
        .vssd2   (vssd2           ),
        .VDD     (vccd2           ),
        .VSS     (vssd2           ),
    `endif
        .clk     (clk             ),
        .INP     (analog_din[1]   ),
        .INN     (analog_dac_out  ),
        .Q       (sar_cmp[1]      )    
    );

    ACMP COMP_2 (
    `ifdef USE_POWER_PINS
        .vccd2   (vccd2           ),
        .vssd2   (vssd2           ),
        .VDD     (vccd2           ),
        .VSS     (vssd2           ),
    `endif
        .clk     (clk             ),
        .INP     (analog_din[2]   ),
        .INN     (analog_dac_out  ),
        .Q       (sar_cmp[2]      )    
    );

    ACMP COMP_3 (
    `ifdef USE_POWER_PINS
        .vccd2   (vccd2           ),
        .vssd2   (vssd2           ),
        .VDD     (vccd2           ),
        .VSS     (vssd2           ),
    `endif
        .clk     (clk             ),
        .INP     (analog_din[3]   ),
        .INN     (analog_dac_out  ),
        .Q       (sar_cmp[3]      )    
    );
    ACMP COMP_4 (
    `ifdef USE_POWER_PINS
        .vccd2   (vccd2           ),
        .vssd2   (vssd2           ),
        .VDD     (vccd2           ),
        .VSS     (vssd2           ),
    `endif
        .clk     (clk             ),
        .INP     (analog_din[4]   ),
        .INN     (analog_dac_out  ),
        .Q       (sar_cmp[4]      )    
    );
    ACMP COMP_5 (
    `ifdef USE_POWER_PINS
        .vccd2   (vccd2           ),
        .vssd2   (vssd2           ),
        .VDD     (vccd2           ),
        .VSS     (vssd2           ),
    `endif
        .clk     (clk             ),
        .INP     (analog_din[5]   ),
        .INN     (analog_dac_out  ),
        .Q       (sar_cmp[5]      )    
    );

    SAR CTRL ( 
        .clk     (clk             ),   
        .reset_n (reset_n         ),  
        .start   (start_conv      ),
        .cmp     (sar_cmp_int     ),
        .out     (adc_result      ),    
        .done    (conv_done       ),
        .outn    (sar2dac         ),
        .clkn    (clkn            ) 
    );


endmodule
module sar_adc(
`ifdef USE_POWER_PINS
    input logic             vccd1         ,
    input logic             vssd1         ,
    input logic             vccd2         ,
    input logic             vssd2         ,
`endif

    
    input  logic            clk           ,
    input  logic            reset_n       ,


    input logic             reg_cs        ,
    input logic             reg_wr        ,
    input logic [7:0]       reg_addr      ,
    input logic [31:0]      reg_wdata     ,
    input logic [3:0]       reg_be        ,


    output logic [31:0]     reg_rdata     ,
    output logic            reg_ack       ,

    input  logic            pulse1m_mclk  ,
    output  logic [7:0]     sar2dac       ,

    input   logic           analog_dac_out,


    input   logic    [5:0]  analog_din

);


    logic        clkn;
    logic [5:0]  sar_cmp;
    logic        sar_cmp_int;
    logic [2:0]  adc_ch_no;
    logic        start_conv    ;
    logic        conv_done     ;
    logic [7:0]  adc_result    ;
  
always_comb 
begin
   sar_cmp_int = 0;
   case(adc_ch_no)
   3'b000 :  sar_cmp_int = sar_cmp[0];
   3'b001 :  sar_cmp_int = sar_cmp[1];
   3'b010 :  sar_cmp_int = sar_cmp[2];
   3'b011 :  sar_cmp_int = sar_cmp[3];
   3'b100 :  sar_cmp_int = sar_cmp[4];
   3'b101 :  sar_cmp_int = sar_cmp[5];
   endcase


end

adc_reg u_adc_reg (
        .mclk        (mclk),
        .reset_n     (reset_n),


        .reg_cs      (reg_cs),
        .reg_wr      (reg_wr),
        .reg_addr    (reg_addr),
        .reg_wdata   (reg_wdata),
        .reg_be      (reg_be),


        .reg_rdata   (reg_rdata),
        .reg_ack     (reg_ack),

	.pulse1m_mclk  (pulse1m_mclk),

       .start_conv   (start_conv),
       .adc_ch_no    (adc_ch_no),           
       .conv_done    (conv_done),
       .adc_result   (adc_result)

       );


    ACMP COMP_0 (
    `ifdef USE_POWER_PINS
        .vccd2   (vccd2           ),
        .vssd2   (vssd2           ),
        .VDD     (vccd2           ),
        .VSS     (vssd2           ),
    `endif
        .clk     (clk             ),
        .INP     (analog_din[0]   ),
        .INN     (analog_dac_out  ),
        .Q       (sar_cmp[0]      )    
    );

    ACMP COMP_1 (
    `ifdef USE_POWER_PINS
        .vccd2   (vccd2           ),
        .vssd2   (vssd2           ),
        .VDD     (vccd2           ),
        .VSS     (vssd2           ),
    `endif
        .clk     (clk             ),
        .INP     (analog_din[1]   ),
        .INN     (analog_dac_out  ),
        .Q       (sar_cmp[1]      )    
    );

    ACMP COMP_2 (
    `ifdef USE_POWER_PINS
        .vccd2   (vccd2           ),
        .vssd2   (vssd2           ),
        .VDD     (vccd2           ),
        .VSS     (vssd2           ),
    `endif
        .clk     (clk             ),
        .INP     (analog_din[2]   ),
        .INN     (analog_dac_out  ),
        .Q       (sar_cmp[2]      )    
    );

    ACMP COMP_3 (
    `ifdef USE_POWER_PINS
        .vccd2   (vccd2           ),
        .vssd2   (vssd2           ),
        .VDD     (vccd2           ),
        .VSS     (vssd2           ),
    `endif
        .clk     (clk             ),
        .INP     (analog_din[3]   ),
        .INN     (analog_dac_out  ),
        .Q       (sar_cmp[3]      )    
    );
    ACMP COMP_4 (
    `ifdef USE_POWER_PINS
        .vccd2   (vccd2           ),
        .vssd2   (vssd2           ),
        .VDD     (vccd2           ),
        .VSS     (vssd2           ),
    `endif
        .clk     (clk             ),
        .INP     (analog_din[4]   ),
        .INN     (analog_dac_out  ),
        .Q       (sar_cmp[4]      )    
    );
    ACMP COMP_5 (
    `ifdef USE_POWER_PINS
        .vccd2   (vccd2           ),
        .vssd2   (vssd2           ),
        .VDD     (vccd2           ),
        .VSS     (vssd2           ),
    `endif
        .clk     (clk             ),
        .INP     (analog_din[5]   ),
        .INN     (analog_dac_out  ),
        .Q       (sar_cmp[5]      )    
    );

    SAR CTRL ( 
        .clk     (clk             ),   
        .reset_n (reset_n         ),  
        .start   (start_conv      ),
        .cmp     (sar_cmp_int     ),
        .out     (adc_result      ),    
        .done    (conv_done       ),
        .outn    (sar2dac         ),
        .clkn    (clkn            ) 
    );


endmodule