data/full_repos/permissive/423547971/FPGA Projects/VGA Projects/Pong pt2/m100_counter.v
1: b'%Error: Cannot find file containing module: Projects/VGA\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/VGA\n             data/full_repos/permissive/423547971/FPGA/Projects/VGA.v\n             data/full_repos/permissive/423547971/FPGA/Projects/VGA.sv\n             Projects/VGA\n             Projects/VGA.v\n             Projects/VGA.sv\n             obj_dir/Projects/VGA\n             obj_dir/Projects/VGA.v\n             obj_dir/Projects/VGA.sv\n%Error: Cannot find file containing module: Projects/Pong\n%Error: Cannot find file containing module: pt2,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: pt2/m100_counter.v\n%Error: Exiting due to 5 error(s)\n'
module m100_counter(
    input clk,
    input reset,
    input d_inc, d_clr,
    output [3:0] dig0, dig1
    );
    

    reg [3:0] r_dig0, r_dig1, dig0_next, dig1_next;
    

    always @(posedge clk or posedge reset)
        if(reset) begin
            r_dig1 <= 0;
            r_dig0 <= 0;
        end
        
        else begin
            r_dig1 <= dig1_next;
            r_dig0 <= dig0_next;
        end
    

    always @* begin
        dig0_next = r_dig0;
        dig1_next = r_dig1;
        
        if(d_clr) begin
            dig0_next <= 0;
            dig1_next <= 0;
        end
        
        else if(d_inc)
            if(r_dig0 == 9) begin
                dig0_next = 0;
                
                if(r_dig1 == 9)
                    dig1_next = 0;
                else
                    dig1_next = r_dig1 + 1;
            end
        
            else
                dig0_next = r_dig0 + 1;
    end
    

    assign dig0 = r_dig0;
    assign dig1 = r_dig1;
    
endmodule
module m100_counter(
    input clk,
    input reset,
    input d_inc, d_clr,
    output [3:0] dig0, dig1
    );

    

    reg [3:0] r_dig0, r_dig1, dig0_next, dig1_next;
    

    always @(posedge clk or posedge reset)
        if(reset) begin
            r_dig1 <= 0;
            r_dig0 <= 0;
        end
        
        else begin
            r_dig1 <= dig1_next;
            r_dig0 <= dig0_next;
        end
    

    always @* begin
        dig0_next = r_dig0;
        dig1_next = r_dig1;
        
        if(d_clr) begin
            dig0_next <= 0;
            dig1_next <= 0;
        end
        
        else if(d_inc)
            if(r_dig0 == 9) begin
                dig0_next = 0;
                
                if(r_dig1 == 9)
                    dig1_next = 0;
                else
                    dig1_next = r_dig1 + 1;
            end
        
            else
                dig0_next = r_dig0 + 1;
    end
    

    assign dig0 = r_dig0;
    assign dig1 = r_dig1;
    
endmodule