data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/alg_awb.v
1: b"%Error: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/alg_awb.v:34: Cannot find file containing module: 'shift_div'\n shift_div #(32) div_rgain(pclk, rst_n, stat_done, sum_g, {4'd0,sum_r[31:4]}, r_gain0, r_remain, r_div_done);\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite,data/full_repos/permissive/514313792/shift_div\n             data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite,data/full_repos/permissive/514313792/shift_div.v\n             data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite,data/full_repos/permissive/514313792/shift_div.sv\n             shift_div\n             shift_div.v\n             shift_div.sv\n             obj_dir/shift_div\n             obj_dir/shift_div.v\n             obj_dir/shift_div.sv\n%Error: data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/alg_awb.v:49: Cannot find file containing module: 'shift_div'\n shift_div #(32) div_bgain(pclk, rst_n, stat_done, sum_g, {4'd0,sum_b[31:4]}, b_gain0, b_remain, b_div_done);\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module alg_awb
#(
	parameter BITS = 8
)
(
	input pclk,
	input rst_n,

	input stat_done,
	input [31:0] pix_cnt,
	input [31:0] sum_r,
	input [31:0] sum_g,
	input [31:0] sum_b,

	output reg [7:0] r_gain,
	output reg [7:0] g_gain,
	output reg [7:0] b_gain
);

`define AWB_USE_SHIFT_DIV 1

	always @ (*) g_gain = 8'h10;

`ifdef AWB_USE_SHIFT_DIV
	wire [31:0] r_gain0, r_remain;
	wire r_div_done;
	shift_div #(32) div_rgain(pclk, rst_n, stat_done, sum_g, {4'd0,sum_r[31:4]}, r_gain0, r_remain, r_div_done);
	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n) begin
			r_gain <= 8'h10;
		end
		else if (r_div_done) begin
			r_gain <= r_gain0 > 32'd255 ? 8'd255 : r_gain0[7:0];
		end
		else begin
			r_gain <= r_gain;
		end
	end
	
	wire [31:0] b_gain0, b_remain;
	wire b_div_done;
	shift_div #(32) div_bgain(pclk, rst_n, stat_done, sum_g, {4'd0,sum_b[31:4]}, b_gain0, b_remain, b_div_done);
	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n) begin
			b_gain <= 8'h10;
		end
		else if (b_div_done) begin
			b_gain <= b_gain0 > 32'd255 ? 8'd255 : b_gain0[7:0];
		end
		else begin
			b_gain <= b_gain;
		end
	end
`else

	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n) begin
			r_gain <= 8'h10;
			b_gain <= 8'h10;
		end
		else if (stat_done) begin
			r_gain <= sum_g / sum_r[31:4];
			b_gain <= sum_g / sum_b[31:4];
		end
		else begin
			r_gain <= r_gain;
			b_gain <= b_gain;
		end
	end
`endif
endmodule
module alg_awb
#(
	parameter BITS = 8
)
(
	input pclk,
	input rst_n,

	input stat_done,
	input [31:0] pix_cnt,
	input [31:0] sum_r,
	input [31:0] sum_g,
	input [31:0] sum_b,

	output reg [7:0] r_gain,
	output reg [7:0] g_gain,
	output reg [7:0] b_gain
);


`define AWB_USE_SHIFT_DIV 1

	always @ (*) g_gain = 8'h10;

`ifdef AWB_USE_SHIFT_DIV
	wire [31:0] r_gain0, r_remain;
	wire r_div_done;
	shift_div #(32) div_rgain(pclk, rst_n, stat_done, sum_g, {4'd0,sum_r[31:4]}, r_gain0, r_remain, r_div_done);
	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n) begin
			r_gain <= 8'h10;
		end
		else if (r_div_done) begin
			r_gain <= r_gain0 > 32'd255 ? 8'd255 : r_gain0[7:0];
		end
		else begin
			r_gain <= r_gain;
		end
	end
	
	wire [31:0] b_gain0, b_remain;
	wire b_div_done;
	shift_div #(32) div_bgain(pclk, rst_n, stat_done, sum_g, {4'd0,sum_b[31:4]}, b_gain0, b_remain, b_div_done);
	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n) begin
			b_gain <= 8'h10;
		end
		else if (b_div_done) begin
			b_gain <= b_gain0 > 32'd255 ? 8'd255 : b_gain0[7:0];
		end
		else begin
			b_gain <= b_gain;
		end
	end
`else

	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n) begin
			r_gain <= 8'h10;
			b_gain <= 8'h10;
		end
		else if (stat_done) begin
			r_gain <= sum_g / sum_r[31:4];
			b_gain <= sum_g / sum_b[31:4];
		end
		else begin
			r_gain <= r_gain;
			b_gain <= b_gain;
		end
	end
`endif
endmodule