data/full_repos/permissive/446997925/hw3/or.v
data/verilator_xmls/91d6b0c7-80e9-4fd8-b698-4e241996a499.xml
module or_8(out, a, b);
input [7:0] a, b;
output [7:0] out;

or_4 f(out[3:0], a[3:0], b[3:0]),
          s(out[7:4], a[7:4], b[7:4]);
endmodule
module or_8(out, a, b);

input [7:0] a, b;
output [7:0] out;

or_4 f(out[3:0], a[3:0], b[3:0]),
          s(out[7:4], a[7:4], b[7:4]);
endmodule