data/full_repos/permissive/494696040/mux_2_to_1_5bit.v
data/verilator_xmls/0abd00a6-a77a-4eb5-abf0-f187ded7a986.xml
module mux_2_to_1_5bit(
    input wire [4:0] zero,
    input wire [4:0] one,
    input select,
    output reg [4:0] out
    );
    

    always @(zero, one, select) begin
        if (select) out <= one;
        else out <= zero;
    end
endmodule
module mux_2_to_1_5bit(
    input wire [4:0] zero,
    input wire [4:0] one,
    input select,
    output reg [4:0] out
    );

    

    always @(zero, one, select) begin
        if (select) out <= one;
        else out <= zero;
    end
endmodule