data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/riscv-dbg/src/dm_sba.sv
1: b'%Warning-LITENDIAN: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/riscv-dbg/src/dm_sba.sv:26: Little bit endian vector: MSB < LSB of bit range: -2:0\n    output logic [BusWidth-1:0]    master_add_o,\n                 ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/riscv-dbg/src/dm_sba.sv:28: Little bit endian vector: MSB < LSB of bit range: -2:0\n    output logic [BusWidth-1:0]    master_wdata_o,\n                 ^\n%Warning-LITENDIAN: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/riscv-dbg/src/dm_sba.sv:29: Little bit endian vector: MSB < LSB of bit range: -1:0\n    output logic [BusWidth/8-1:0]  master_be_o,\n                 ^\n%Warning-LITENDIAN: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/riscv-dbg/src/dm_sba.sv:32: Little bit endian vector: MSB < LSB of bit range: -2:0\n    input  logic [BusWidth-1:0]    master_r_rdata_i,\n                 ^\n%Warning-LITENDIAN: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/riscv-dbg/src/dm_sba.sv:34: Little bit endian vector: MSB < LSB of bit range: -2:0\n    input  logic [BusWidth-1:0]    sbaddress_i,\n                 ^\n%Warning-LITENDIAN: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/riscv-dbg/src/dm_sba.sv:38: Little bit endian vector: MSB < LSB of bit range: -2:0\n    output logic [BusWidth-1:0]    sbaddress_o,\n                 ^\n%Warning-LITENDIAN: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/riscv-dbg/src/dm_sba.sv:43: Little bit endian vector: MSB < LSB of bit range: -2:0\n    input  logic [BusWidth-1:0]    sbdata_i,\n                 ^\n%Warning-LITENDIAN: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/riscv-dbg/src/dm_sba.sv:47: Little bit endian vector: MSB < LSB of bit range: -2:0\n    output logic [BusWidth-1:0]    sbdata_o,\n                 ^\n%Warning-LITENDIAN: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/riscv-dbg/src/dm_sba.sv:58: Little bit endian vector: MSB < LSB of bit range: -2:0\n    logic [BusWidth-1:0]   address;\n          ^\n%Warning-LITENDIAN: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/riscv-dbg/src/dm_sba.sv:62: Little bit endian vector: MSB < LSB of bit range: -1:0\n    logic [BusWidth/8-1:0] be;\n          ^\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/riscv-dbg/src/dm_sba.sv:99: [0:2] Range extract has backward bit ordering, perhaps you wanted [2:0]\n                                                                                                                        : ... In instance dm_sba\n                        if (BusWidth == 64) be[ sbaddress_i[2:0]] = \'1;\n                                                           ^\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/riscv-dbg/src/dm_sba.sv:100: [0:1] Range extract has backward bit ordering, perhaps you wanted [1:0]\n                                                                                                                         : ... In instance dm_sba\n                        else                be[ sbaddress_i[1:0]] = \'1;\n                                                           ^\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/riscv-dbg/src/dm_sba.sv:103: [1:2] Range extract has backward bit ordering, perhaps you wanted [2:1]\n                                                                                                                         : ... In instance dm_sba\n                        if (BusWidth == 64) be[{sbaddress_i[2:1], 1\'b0} +: 2] = \'1;\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/riscv-dbg/src/dm_sba.sv:103: Operator SUB expects 32 bits on the RHS, but RHS\'s REPLICATE generates 3 bits.\n                                                                                                                                 : ... In instance dm_sba\n                        if (BusWidth == 64) be[{sbaddress_i[2:1], 1\'b0} +: 2] = \'1;\n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/riscv-dbg/src/dm_sba.sv:104: Operator SUB expects 32 bits on the RHS, but RHS\'s REPLICATE generates 2 bits.\n                                                                                                                                 : ... In instance dm_sba\n                        else                be[{sbaddress_i[1:1], 1\'b0} +: 2] = \'1;\n                                               ^\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/riscv-dbg/src/dm_sba.sv:107: Extracting 4 bits from only 2 bit number\n                                                                                                                         : ... In instance dm_sba\n                        if (BusWidth == 64) be[{sbaddress_i[2:2], 2\'b0} +: 4] = \'1;\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/riscv-dbg/src/dm_sba.sv:107: Operator SUB expects 32 bits on the RHS, but RHS\'s REPLICATE generates 3 bits.\n                                                                                                                                 : ... In instance dm_sba\n                        if (BusWidth == 64) be[{sbaddress_i[2:2], 2\'b0} +: 4] = \'1;\n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/riscv-dbg/src/dm_sba.sv:120: Operator SHIFTL expects 3 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                                                                 : ... In instance dm_sba\n                    if (sbautoincrement_i) sbaddress_o = sbaddress_i + (1\'b1 << sbaccess_i);\n                                                                             ^~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/riscv-dbg/src/dm_sba.sv:128: Operator SHIFTL expects 3 bits on the LHS, but LHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                                                                 : ... In instance dm_sba\n                    if (sbautoincrement_i) sbaddress_o = sbaddress_i + (1\'b1 << sbaccess_i);\n                                                                             ^~\n%Error: Exiting due to 4 error(s), 15 warning(s)\n'
module dm_sba #(
    parameter int BusWidth = -1
) (
    input  logic                   clk_i,
    input  logic                   rst_ni,
    input  logic                   dmactive_i,

    output logic                   master_req_o,
    output logic [BusWidth-1:0]    master_add_o,
    output logic                   master_we_o,
    output logic [BusWidth-1:0]    master_wdata_o,
    output logic [BusWidth/8-1:0]  master_be_o,
    input  logic                   master_gnt_i,
    input  logic                   master_r_valid_i,
    input  logic [BusWidth-1:0]    master_r_rdata_i,

    input  logic [BusWidth-1:0]    sbaddress_i,
    input  logic                   sbaddress_write_valid_i,

    input  logic                   sbreadonaddr_i,
    output logic [BusWidth-1:0]    sbaddress_o,
    input  logic                   sbautoincrement_i,
    input  logic [2:0]             sbaccess_i,

    input  logic                   sbreadondata_i,
    input  logic [BusWidth-1:0]    sbdata_i,
    input  logic                   sbdata_read_valid_i,
    input  logic                   sbdata_write_valid_i,

    output logic [BusWidth-1:0]    sbdata_o,
    output logic                   sbdata_valid_o,

    output logic                   sbbusy_o,
    output logic                   sberror_valid_o,
    output logic [2:0]             sberror_o
);

    typedef enum logic [2:0] { Idle, Read, Write, WaitRead, WaitWrite } state_e;
    state_e state_d, state_q;

    logic [BusWidth-1:0]   address;
    logic                  req;
    logic                  gnt;
    logic                  we;
    logic [BusWidth/8-1:0] be;

    assign sbbusy_o = (state_q != Idle) ? 1'b1 : 1'b0;

    always_comb begin
        req     = 1'b0;
        address = sbaddress_i;
        we      = 1'b0;
        be      = '0;

        sberror_o       = '0;
        sberror_valid_o = 1'b0;
        sbaddress_o     = sbaddress_i;

        state_d = state_q;

        case (state_q)
            Idle: begin

                if (sbaddress_write_valid_i && sbreadonaddr_i)  state_d = Read;

                if (sbdata_write_valid_i) state_d = Write;

                if (sbdata_read_valid_i && sbreadondata_i) state_d = Read;
            end

            Read: begin
                req = 1'b1;
                if (gnt) state_d = WaitRead;
            end

            Write: begin
                req = 1'b1;
                we  = 1'b1;

                case (sbaccess_i)
                    3'b000: begin
                        if (BusWidth == 64) be[ sbaddress_i[2:0]] = '1;
                        else                be[ sbaddress_i[1:0]] = '1;
                    end
                    3'b001: begin
                        if (BusWidth == 64) be[{sbaddress_i[2:1], 1'b0} +: 2] = '1;
                        else                be[{sbaddress_i[1:1], 1'b0} +: 2] = '1;
                    end
                    3'b010: begin
                        if (BusWidth == 64) be[{sbaddress_i[2:2], 2'b0} +: 4] = '1;
                        else                be = '1;
                    end
                    3'b011: be = '1;
                    default:;
                endcase
                if (gnt) state_d = WaitWrite;
            end

            WaitRead: begin
                if (sbdata_valid_o) begin
                    state_d = Idle;

                    if (sbautoincrement_i) sbaddress_o = sbaddress_i + (1'b1 << sbaccess_i);
                end
            end

            WaitWrite: begin
                if (sbdata_valid_o) begin
                    state_d = Idle;

                    if (sbautoincrement_i) sbaddress_o = sbaddress_i + (1'b1 << sbaccess_i);
                end
            end

            default:;
        endcase


        if (sbaccess_i > 3 && state_q != Idle) begin
            req             = 1'b0;
            state_d         = Idle;
            sberror_valid_o = 1'b1;
            sberror_o       = 3'd3;
        end

    end

    always_ff @(posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            state_q <= Idle;
        end else begin
            state_q <= state_d;
        end
    end

    assign master_req_o    = req;
    assign master_add_o    = address[BusWidth-1:0];
    assign master_we_o     = we;
    assign master_wdata_o  = sbdata_i[BusWidth-1:0];
    assign master_be_o     = be[BusWidth/8-1:0];
    assign gnt             = master_gnt_i;
    assign sbdata_valid_o  = master_r_valid_i;
    assign sbdata_o        = master_r_rdata_i[BusWidth-1:0];



    `ifndef VERILATOR

        dm_sba_access_size: assert property(@(posedge clk_i) disable iff (dmactive_i !== 1'b0)
            (state_d != Idle) |-> (sbaccess_i < 4))
        else
            $warning ("accesses > 8 byte not supported at the moment");
    `endif


endmodule
module dm_sba #(
    parameter int BusWidth = -1
) (
    input  logic                   clk_i,
    input  logic                   rst_ni,
    input  logic                   dmactive_i,

    output logic                   master_req_o,
    output logic [BusWidth-1:0]    master_add_o,
    output logic                   master_we_o,
    output logic [BusWidth-1:0]    master_wdata_o,
    output logic [BusWidth/8-1:0]  master_be_o,
    input  logic                   master_gnt_i,
    input  logic                   master_r_valid_i,
    input  logic [BusWidth-1:0]    master_r_rdata_i,

    input  logic [BusWidth-1:0]    sbaddress_i,
    input  logic                   sbaddress_write_valid_i,

    input  logic                   sbreadonaddr_i,
    output logic [BusWidth-1:0]    sbaddress_o,
    input  logic                   sbautoincrement_i,
    input  logic [2:0]             sbaccess_i,

    input  logic                   sbreadondata_i,
    input  logic [BusWidth-1:0]    sbdata_i,
    input  logic                   sbdata_read_valid_i,
    input  logic                   sbdata_write_valid_i,

    output logic [BusWidth-1:0]    sbdata_o,
    output logic                   sbdata_valid_o,

    output logic                   sbbusy_o,
    output logic                   sberror_valid_o,
    output logic [2:0]             sberror_o
);


    typedef enum logic [2:0] { Idle, Read, Write, WaitRead, WaitWrite } state_e;
    state_e state_d, state_q;

    logic [BusWidth-1:0]   address;
    logic                  req;
    logic                  gnt;
    logic                  we;
    logic [BusWidth/8-1:0] be;

    assign sbbusy_o = (state_q != Idle) ? 1'b1 : 1'b0;

    always_comb begin
        req     = 1'b0;
        address = sbaddress_i;
        we      = 1'b0;
        be      = '0;

        sberror_o       = '0;
        sberror_valid_o = 1'b0;
        sbaddress_o     = sbaddress_i;

        state_d = state_q;

        case (state_q)
            Idle: begin

                if (sbaddress_write_valid_i && sbreadonaddr_i)  state_d = Read;

                if (sbdata_write_valid_i) state_d = Write;

                if (sbdata_read_valid_i && sbreadondata_i) state_d = Read;
            end

            Read: begin
                req = 1'b1;
                if (gnt) state_d = WaitRead;
            end

            Write: begin
                req = 1'b1;
                we  = 1'b1;

                case (sbaccess_i)
                    3'b000: begin
                        if (BusWidth == 64) be[ sbaddress_i[2:0]] = '1;
                        else                be[ sbaddress_i[1:0]] = '1;
                    end
                    3'b001: begin
                        if (BusWidth == 64) be[{sbaddress_i[2:1], 1'b0} +: 2] = '1;
                        else                be[{sbaddress_i[1:1], 1'b0} +: 2] = '1;
                    end
                    3'b010: begin
                        if (BusWidth == 64) be[{sbaddress_i[2:2], 2'b0} +: 4] = '1;
                        else                be = '1;
                    end
                    3'b011: be = '1;
                    default:;
                endcase
                if (gnt) state_d = WaitWrite;
            end

            WaitRead: begin
                if (sbdata_valid_o) begin
                    state_d = Idle;

                    if (sbautoincrement_i) sbaddress_o = sbaddress_i + (1'b1 << sbaccess_i);
                end
            end

            WaitWrite: begin
                if (sbdata_valid_o) begin
                    state_d = Idle;

                    if (sbautoincrement_i) sbaddress_o = sbaddress_i + (1'b1 << sbaccess_i);
                end
            end

            default:;
        endcase


        if (sbaccess_i > 3 && state_q != Idle) begin
            req             = 1'b0;
            state_d         = Idle;
            sberror_valid_o = 1'b1;
            sberror_o       = 3'd3;
        end

    end

    always_ff @(posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            state_q <= Idle;
        end else begin
            state_q <= state_d;
        end
    end

    assign master_req_o    = req;
    assign master_add_o    = address[BusWidth-1:0];
    assign master_we_o     = we;
    assign master_wdata_o  = sbdata_i[BusWidth-1:0];
    assign master_be_o     = be[BusWidth/8-1:0];
    assign gnt             = master_gnt_i;
    assign sbdata_valid_o  = master_r_valid_i;
    assign sbdata_o        = master_r_rdata_i[BusWidth-1:0];



    `ifndef VERILATOR

        dm_sba_access_size: assert property(@(posedge clk_i) disable iff (dmactive_i !== 1'b0)
            (state_d != Idle) |-> (sbaccess_i < 4))
        else
            $warning ("accesses > 8 byte not supported at the moment");
    `endif


endmodule