data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/macro/rwsgen.v
data/verilator_xmls/bc0294c7-395a-4588-9aca-0ba2fbef445e.xml
module rwsgen
    (
     clk,
     rst,
     pce_,
     prnw,
     pws,
     prs,
     scanmode
     );




input   clk,
        rst,
        pce_,
        prnw;
input   scanmode;
output  pws,
        prs;










wire    cerst;
assign  cerst = rst | pce_;


 


reg [7:0]   rin;
always @(posedge clk or posedge cerst)
    begin
    if(cerst) rin <= {8{1'b1}};



    else rin <= {rin[6:0],pce_};
    end


reg pul = 1'b0;
always @(posedge clk)
    begin

    pul <= (rin[7:4] == 4'b1100);
    end

reg [1:0] rprnw = 2'd0;
always @(posedge clk)
    begin

    rprnw <= {rprnw[0],prnw};
    end

reg     pws = 1'b0;
reg     prs = 1'b0;
always @(posedge clk)
    begin







        pws <= ~rprnw[1] & pul;
        prs <= rprnw[1] & pul;

    end

endmodule
module rwsgen
    (
     clk,
     rst,
     pce_,
     prnw,
     pws,
     prs,
     scanmode
     );





input   clk,
        rst,
        pce_,
        prnw;
input   scanmode;
output  pws,
        prs;










wire    cerst;
assign  cerst = rst | pce_;


 


reg [7:0]   rin;
always @(posedge clk or posedge cerst)
    begin
    if(cerst) rin <= {8{1'b1}};



    else rin <= {rin[6:0],pce_};
    end


reg pul = 1'b0;
always @(posedge clk)
    begin

    pul <= (rin[7:4] == 4'b1100);
    end

reg [1:0] rprnw = 2'd0;
always @(posedge clk)
    begin

    rprnw <= {rprnw[0],prnw};
    end

reg     pws = 1'b0;
reg     prs = 1'b0;
always @(posedge clk)
    begin







        pws <= ~rprnw[1] & pul;
        prs <= rprnw[1] & pul;

    end

endmodule