data/full_repos/permissive/52196097/DSP/PLL_ADF4158/PLL_ADF4158/tb_PLL_ADF4158.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/52196097/DSP/PLL_ADF4158/PLL_ADF4158/tb_PLL_ADF4158.v:18: Unsupported: Ignoring delay on this delayed statement.\n  forever #25 Clock = ~Clock;  \n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/52196097/DSP/PLL_ADF4158/PLL_ADF4158/tb_PLL_ADF4158.v:14: Cannot find file containing module: \'PLL_ADF4158\'\n PLL_ADF4158 pll (.clk(Clock), .reset_n(1), .writeData(writeData), .loadEnable(loadEnable), .pll_clk(pll_clk));\n ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52196097/DSP/PLL_ADF4158/PLL_ADF4158,data/full_repos/permissive/52196097/PLL_ADF4158\n             data/full_repos/permissive/52196097/DSP/PLL_ADF4158/PLL_ADF4158,data/full_repos/permissive/52196097/PLL_ADF4158.v\n             data/full_repos/permissive/52196097/DSP/PLL_ADF4158/PLL_ADF4158,data/full_repos/permissive/52196097/PLL_ADF4158.sv\n             PLL_ADF4158\n             PLL_ADF4158.v\n             PLL_ADF4158.sv\n             obj_dir/PLL_ADF4158\n             obj_dir/PLL_ADF4158.v\n             obj_dir/PLL_ADF4158.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pll_testbench;
	reg Clock;
	wire writeData;
	wire loadEnable;
	wire pll_clk;
	
	PLL_ADF4158 pll (.clk(Clock), .reset_n(1), .writeData(writeData), .loadEnable(loadEnable), .pll_clk(pll_clk));

	initial begin
		Clock = 0;
		forever #25 Clock = ~Clock;
	end
endmodule
module pll_testbench;

	reg Clock;
	wire writeData;
	wire loadEnable;
	wire pll_clk;
	
	PLL_ADF4158 pll (.clk(Clock), .reset_n(1), .writeData(writeData), .loadEnable(loadEnable), .pll_clk(pll_clk));

	initial begin
		Clock = 0;
		forever #25 Clock = ~Clock;
	end
endmodule