data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess/OnChipDataMemory.v
1: b'%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess/OnChipDataMemory.v:50: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 8 bits.\n                                                                                                                               : ... In instance OnChipDataMemory\n                        readData = $signed(bramDataOut[7:0]);\n                                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess/OnChipDataMemory.v:52: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 8 bits.\n                                                                                                                               : ... In instance OnChipDataMemory\n                        readData = $unsigned(bramDataOut[7:0]);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess/OnChipDataMemory.v:57: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 8 bits.\n                                                                                                                               : ... In instance OnChipDataMemory\n                        readData = $signed(bramDataOut[15:8]);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess/OnChipDataMemory.v:59: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 8 bits.\n                                                                                                                               : ... In instance OnChipDataMemory\n                        readData = $unsigned(bramDataOut[15:8]);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess/OnChipDataMemory.v:64: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 8 bits.\n                                                                                                                               : ... In instance OnChipDataMemory\n                        readData = $signed(bramDataOut[23:16]);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess/OnChipDataMemory.v:66: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 8 bits.\n                                                                                                                               : ... In instance OnChipDataMemory\n                        readData = $unsigned(bramDataOut[23:16]);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess/OnChipDataMemory.v:71: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 8 bits.\n                                                                                                                               : ... In instance OnChipDataMemory\n                        readData = $signed(bramDataOut[31:24]);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess/OnChipDataMemory.v:73: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 8 bits.\n                                                                                                                               : ... In instance OnChipDataMemory\n                        readData = $unsigned(bramDataOut[31:24]);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess/OnChipDataMemory.v:78: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 8 bits.\n                                                                                                                               : ... In instance OnChipDataMemory\n                        readData = $signed(bramDataOut[39:32]);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess/OnChipDataMemory.v:80: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 8 bits.\n                                                                                                                               : ... In instance OnChipDataMemory\n                        readData = $unsigned(bramDataOut[39:32]);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess/OnChipDataMemory.v:85: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 8 bits.\n                                                                                                                               : ... In instance OnChipDataMemory\n                        readData = $signed(bramDataOut[47:40]);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess/OnChipDataMemory.v:87: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 8 bits.\n                                                                                                                               : ... In instance OnChipDataMemory\n                        readData = $unsigned(bramDataOut[47:40]);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess/OnChipDataMemory.v:92: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 8 bits.\n                                                                                                                               : ... In instance OnChipDataMemory\n                        readData = $signed(bramDataOut[55:48]);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess/OnChipDataMemory.v:94: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 8 bits.\n                                                                                                                               : ... In instance OnChipDataMemory\n                        readData = $unsigned(bramDataOut[55:48]);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess/OnChipDataMemory.v:99: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 8 bits.\n                                                                                                                               : ... In instance OnChipDataMemory\n                        readData = $signed(bramDataOut[63:56]);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess/OnChipDataMemory.v:101: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 8 bits.\n                                                                                                                                : ... In instance OnChipDataMemory\n                        readData = $unsigned(bramDataOut[63:56]);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess/OnChipDataMemory.v:112: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 16 bits.\n                                                                                                                                : ... In instance OnChipDataMemory\n                        readData = $signed(bramDataOut[15:0]);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess/OnChipDataMemory.v:114: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 16 bits.\n                                                                                                                                : ... In instance OnChipDataMemory\n                        readData = $unsigned(bramDataOut[15:0]);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess/OnChipDataMemory.v:119: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 16 bits.\n                                                                                                                                : ... In instance OnChipDataMemory\n                        readData = $signed(bramDataOut[31:16]);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess/OnChipDataMemory.v:121: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 16 bits.\n                                                                                                                                : ... In instance OnChipDataMemory\n                        readData = $unsigned(bramDataOut[31:16]);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess/OnChipDataMemory.v:126: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 16 bits.\n                                                                                                                                : ... In instance OnChipDataMemory\n                        readData = $signed(bramDataOut[47:32]);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess/OnChipDataMemory.v:128: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 16 bits.\n                                                                                                                                : ... In instance OnChipDataMemory\n                        readData = $unsigned(bramDataOut[47:32]);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess/OnChipDataMemory.v:133: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 16 bits.\n                                                                                                                                : ... In instance OnChipDataMemory\n                        readData = $signed(bramDataOut[63:48]);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess/OnChipDataMemory.v:135: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 16 bits.\n                                                                                                                                : ... In instance OnChipDataMemory\n                        readData = $unsigned(bramDataOut[63:48]);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess/OnChipDataMemory.v:146: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 32 bits.\n                                                                                                                                : ... In instance OnChipDataMemory\n                        readData = $signed(bramDataOut[31:0]);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess/OnChipDataMemory.v:148: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                                : ... In instance OnChipDataMemory\n                        readData = $unsigned(bramDataOut[31:0]);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess/OnChipDataMemory.v:153: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 32 bits.\n                                                                                                                                : ... In instance OnChipDataMemory\n                        readData = $signed(bramDataOut[63:32]);\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/MemoryAccess/OnChipDataMemory.v:155: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                                : ... In instance OnChipDataMemory\n                        readData = $unsigned(bramDataOut[63:32]);\n                                 ^\n%Error: Exiting due to 28 warning(s)\n'
module OnChipDataMemory (
    input [10:0] address,
    input [63:0] writeData,
    input signExtended,
    input [1:0] size,
    input writeEnable,
    input clk,

    output reg [63:0] readData
);


    reg [63:0] bramDataIn;
    reg [63:0] bramDataOut;


    reg [63:0] memory [0:255];

    integer i;
    initial begin
        for (i = 0; i < 256; i = i + 1)
            memory[i] = 64'b0;
    end


    always @(*) begin
        case (size)
            2'b00: begin
            case (address[2:0])
                3'b000: begin
                    if (signExtended)
                        readData = $signed(bramDataOut[7:0]);
                    else
                        readData = $unsigned(bramDataOut[7:0]);
                    bramDataIn = {bramDataOut[63:8], writeData[7:0]};
                end
                3'b001: begin
                    if (signExtended)
                        readData = $signed(bramDataOut[15:8]);
                    else
                        readData = $unsigned(bramDataOut[15:8]);
                    bramDataIn = {bramDataOut[63:16], writeData[15:8], bramDataOut[7:0]};
                end
                3'b010: begin
                    if (signExtended)
                        readData = $signed(bramDataOut[23:16]);
                    else
                        readData = $unsigned(bramDataOut[23:16]);
                    bramDataIn = {bramDataOut[63:24], writeData[23:16], bramDataOut[15:0]};
                end
                3'b011: begin
                    if (signExtended)
                        readData = $signed(bramDataOut[31:24]);
                    else
                        readData = $unsigned(bramDataOut[31:24]);
                    bramDataIn = {bramDataOut[63:32], writeData[31:24], bramDataOut[23:0]};
                end
                3'b100: begin
                    if (signExtended)
                        readData = $signed(bramDataOut[39:32]);
                    else
                        readData = $unsigned(bramDataOut[39:32]);
                    bramDataIn = {bramDataOut[63:40], writeData[39:32], bramDataOut[31:0]};
                end
                3'b101: begin
                    if (signExtended)
                        readData = $signed(bramDataOut[47:40]);
                    else
                        readData = $unsigned(bramDataOut[47:40]);
                    bramDataIn = {bramDataOut[63:48], writeData[47:40], bramDataOut[39:0]};
                end
                3'b110: begin
                    if (signExtended)
                        readData = $signed(bramDataOut[55:48]);
                    else
                        readData = $unsigned(bramDataOut[55:48]);
                    bramDataIn = {bramDataOut[63:56], writeData[55:48], bramDataOut[47:0]};
                end
                3'b111: begin
                    if (signExtended)
                        readData = $signed(bramDataOut[63:56]);
                    else
                        readData = $unsigned(bramDataOut[63:56]);
                    bramDataIn = {writeData[63:56], bramDataOut[55:0]};
                end
            endcase 
            end
            2'b01: begin


            case (address[2:1])
                2'b00: begin
                    if (signExtended)
                        readData = $signed(bramDataOut[15:0]);
                    else
                        readData = $unsigned(bramDataOut[15:0]);
                    bramDataIn = {bramDataOut[63:16], writeData[15:0]};
                end
                2'b01: begin
                    if (signExtended)
                        readData = $signed(bramDataOut[31:16]);
                    else
                        readData = $unsigned(bramDataOut[31:16]);
                    bramDataIn = {bramDataOut[63:32], writeData[31:16], bramDataOut[15:0]};
                end
                2'b10: begin
                    if (signExtended)
                        readData = $signed(bramDataOut[47:32]);
                    else
                        readData = $unsigned(bramDataOut[47:32]);
                    bramDataIn = {bramDataOut[63:48], writeData[47:32], bramDataOut[31:0]};
                end
                2'b11: begin
                    if (signExtended)
                        readData = $signed(bramDataOut[63:48]);
                    else
                        readData = $unsigned(bramDataOut[63:48]);
                    bramDataIn = {writeData[63:48], bramDataOut[47:0]};
                end
            endcase 
            end
            2'b10: begin


            case (address[2])
                1'b0: begin
                    if (signExtended)
                        readData = $signed(bramDataOut[31:0]);
                    else
                        readData = $unsigned(bramDataOut[31:0]);
                    bramDataIn = {bramDataOut[63:32], writeData[31:0]};
                end
                1'b1: begin
                    if (signExtended)
                        readData = $signed(bramDataOut[63:32]);
                    else
                        readData = $unsigned(bramDataOut[63:32]);
                    bramDataIn = {writeData[63:32], bramDataOut[31:0]};
                end
            endcase 
            end
            2'b11: begin
                readData = bramDataOut;
                bramDataIn = writeData;
            end
        endcase
    end

    always @(negedge clk) begin
        if (writeEnable == 1'b1)
            memory[address[10:3]] = bramDataIn;
        bramDataOut = memory[address[10:3]];
    end

endmodule
module OnChipDataMemory (
    input [10:0] address,
    input [63:0] writeData,
    input signExtended,
    input [1:0] size,
    input writeEnable,
    input clk,

    output reg [63:0] readData
);



    reg [63:0] bramDataIn;
    reg [63:0] bramDataOut;


    reg [63:0] memory [0:255];

    integer i;
    initial begin
        for (i = 0; i < 256; i = i + 1)
            memory[i] = 64'b0;
    end


    always @(*) begin
        case (size)
            2'b00: begin
            case (address[2:0])
                3'b000: begin
                    if (signExtended)
                        readData = $signed(bramDataOut[7:0]);
                    else
                        readData = $unsigned(bramDataOut[7:0]);
                    bramDataIn = {bramDataOut[63:8], writeData[7:0]};
                end
                3'b001: begin
                    if (signExtended)
                        readData = $signed(bramDataOut[15:8]);
                    else
                        readData = $unsigned(bramDataOut[15:8]);
                    bramDataIn = {bramDataOut[63:16], writeData[15:8], bramDataOut[7:0]};
                end
                3'b010: begin
                    if (signExtended)
                        readData = $signed(bramDataOut[23:16]);
                    else
                        readData = $unsigned(bramDataOut[23:16]);
                    bramDataIn = {bramDataOut[63:24], writeData[23:16], bramDataOut[15:0]};
                end
                3'b011: begin
                    if (signExtended)
                        readData = $signed(bramDataOut[31:24]);
                    else
                        readData = $unsigned(bramDataOut[31:24]);
                    bramDataIn = {bramDataOut[63:32], writeData[31:24], bramDataOut[23:0]};
                end
                3'b100: begin
                    if (signExtended)
                        readData = $signed(bramDataOut[39:32]);
                    else
                        readData = $unsigned(bramDataOut[39:32]);
                    bramDataIn = {bramDataOut[63:40], writeData[39:32], bramDataOut[31:0]};
                end
                3'b101: begin
                    if (signExtended)
                        readData = $signed(bramDataOut[47:40]);
                    else
                        readData = $unsigned(bramDataOut[47:40]);
                    bramDataIn = {bramDataOut[63:48], writeData[47:40], bramDataOut[39:0]};
                end
                3'b110: begin
                    if (signExtended)
                        readData = $signed(bramDataOut[55:48]);
                    else
                        readData = $unsigned(bramDataOut[55:48]);
                    bramDataIn = {bramDataOut[63:56], writeData[55:48], bramDataOut[47:0]};
                end
                3'b111: begin
                    if (signExtended)
                        readData = $signed(bramDataOut[63:56]);
                    else
                        readData = $unsigned(bramDataOut[63:56]);
                    bramDataIn = {writeData[63:56], bramDataOut[55:0]};
                end
            endcase 
            end
            2'b01: begin


            case (address[2:1])
                2'b00: begin
                    if (signExtended)
                        readData = $signed(bramDataOut[15:0]);
                    else
                        readData = $unsigned(bramDataOut[15:0]);
                    bramDataIn = {bramDataOut[63:16], writeData[15:0]};
                end
                2'b01: begin
                    if (signExtended)
                        readData = $signed(bramDataOut[31:16]);
                    else
                        readData = $unsigned(bramDataOut[31:16]);
                    bramDataIn = {bramDataOut[63:32], writeData[31:16], bramDataOut[15:0]};
                end
                2'b10: begin
                    if (signExtended)
                        readData = $signed(bramDataOut[47:32]);
                    else
                        readData = $unsigned(bramDataOut[47:32]);
                    bramDataIn = {bramDataOut[63:48], writeData[47:32], bramDataOut[31:0]};
                end
                2'b11: begin
                    if (signExtended)
                        readData = $signed(bramDataOut[63:48]);
                    else
                        readData = $unsigned(bramDataOut[63:48]);
                    bramDataIn = {writeData[63:48], bramDataOut[47:0]};
                end
            endcase 
            end
            2'b10: begin


            case (address[2])
                1'b0: begin
                    if (signExtended)
                        readData = $signed(bramDataOut[31:0]);
                    else
                        readData = $unsigned(bramDataOut[31:0]);
                    bramDataIn = {bramDataOut[63:32], writeData[31:0]};
                end
                1'b1: begin
                    if (signExtended)
                        readData = $signed(bramDataOut[63:32]);
                    else
                        readData = $unsigned(bramDataOut[63:32]);
                    bramDataIn = {writeData[63:32], bramDataOut[31:0]};
                end
            endcase 
            end
            2'b11: begin
                readData = bramDataOut;
                bramDataIn = writeData;
            end
        endcase
    end

    always @(negedge clk) begin
        if (writeEnable == 1'b1)
            memory[address[10:3]] = bramDataIn;
        bramDataOut = memory[address[10:3]];
    end

endmodule