data/full_repos/permissive/492363527/clockin.v
1: b"%Error: data/full_repos/permissive/492363527/clockin.v:1: Unsupported: SystemVerilog 2005 reserved word not implemented: 'dist'\nmodule clockin(input clock50m, input [32:0] dist, output reg uu);\n                                            ^~~~\n%Error: data/full_repos/permissive/492363527/clockin.v:1: syntax error, unexpected ',', expecting IDENTIFIER or '[' or do or final\nmodule clockin(input clock50m, input [32:0] dist, output reg uu);\n                                                ^\n%Error: data/full_repos/permissive/492363527/clockin.v:2: Unsupported: SystemVerilog 2005 reserved word not implemented: 'dist'\nwire so = (dist == 33'b000000000000000000000000000001110);\n           ^~~~\n%Error: data/full_repos/permissive/492363527/clockin.v:2: syntax error, unexpected ==, expecting TYPE-IDENTIFIER\nwire so = (dist == 33'b000000000000000000000000000001110);\n                ^~\n%Error: Exiting due to 4 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module clockin(input clock50m, input [32:0] dist, output reg uu);
wire so = (dist == 33'b000000000000000000000000000001110);
 

	always@(posedge clk50M) 
	begin
	if(so)
	begin
	uu <= 1;
	end
	else
	begin
	uu <= 0;
	end
	end
	end
	
	
	
endmodule
module clockin(input clock50m, input [32:0] dist, output reg uu);

wire so = (dist == 33'b000000000000000000000000000001110);
 

	always@(posedge clk50M) 
	begin
	if(so)
	begin
	uu <= 1;
	end
	else
	begin
	uu <= 0;
	end
	end
	end
	
	
	
endmodule