data/full_repos/permissive/47037127/dispatchu_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/47037127/dispatchu_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #1 clk<=!clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/47037127/dispatchu_tb.v:58: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("dispatchu_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/47037127/dispatchu_tb.v:59: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/47037127/dispatchu_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n  #128 $finish;\n  ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module dispatchu_tb(
  );

reg clk;
reg [15:0] aDat;
reg [15:0] bDat;
reg [15:0] cDat;
wire [31:0] addr;
wire [15:0] memOut;
wire memWrite;
wire [15:0] cOut;
wire cWrite;
wire [2:0] aSel;
wire [2:0] bSel;
wire [2:0] cSel;
wire [3:0] intOp;
wire [2:0] intA;
wire [2:0] intB;
wire [2:0] intC;

wire [15:0] memDat;


reg [15:0] memoryArray[15:0]; 
reg [3:0] memSel;
assign memDat=memoryArray[memSel];

dispatchu du(clk, memDat, aDat, bDat, cDat, addr, memOut, memWrite, cOut, cWrite, aSel, bSel, cSel, intOp, intA, intB, intC);


initial begin

  clk=0;
  aDat=0;
  bDat=0;
  cDat=0;
  memSel=0;
  memoryArray[0]=16'h000a;
  memoryArray[1]=16'h8007;
  memoryArray[2]=16'h6638;
end

always begin
  #1 clk<=!clk;
  if(clk) begin
    if(memWrite) begin
      memoryArray[addr%16]<=memOut;
    end
      
    else begin
      memSel<=addr%16;
    end
  end
end

initial begin
  $dumpfile("dispatchu_tb.vcd");
  $dumpvars;
end

initial 
  #128 $finish;
endmodule
module dispatchu_tb(
  );


reg clk;
reg [15:0] aDat;
reg [15:0] bDat;
reg [15:0] cDat;
wire [31:0] addr;
wire [15:0] memOut;
wire memWrite;
wire [15:0] cOut;
wire cWrite;
wire [2:0] aSel;
wire [2:0] bSel;
wire [2:0] cSel;
wire [3:0] intOp;
wire [2:0] intA;
wire [2:0] intB;
wire [2:0] intC;

wire [15:0] memDat;


reg [15:0] memoryArray[15:0]; 
reg [3:0] memSel;
assign memDat=memoryArray[memSel];

dispatchu du(clk, memDat, aDat, bDat, cDat, addr, memOut, memWrite, cOut, cWrite, aSel, bSel, cSel, intOp, intA, intB, intC);


initial begin

  clk=0;
  aDat=0;
  bDat=0;
  cDat=0;
  memSel=0;
  memoryArray[0]=16'h000a;
  memoryArray[1]=16'h8007;
  memoryArray[2]=16'h6638;
end

always begin
  #1 clk<=!clk;
  if(clk) begin
    if(memWrite) begin
      memoryArray[addr%16]<=memOut;
    end
      
    else begin
      memSel<=addr%16;
    end
  end
end

initial begin
  $dumpfile("dispatchu_tb.vcd");
  $dumpvars;
end

initial 
  #128 $finish;
endmodule