data/full_repos/permissive/437632408/NVDLA/nvdla/sdp/NV_NVDLA_SDP_MRDMA_eg.v
1: b'%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/sdp/NV_NVDLA_SDP_MRDMA_eg.v:9: Cannot find include file: simulate_x_tick.vh\n`include "simulate_x_tick.vh" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/437632408/NVDLA/nvdla/sdp,data/full_repos/permissive/437632408/simulate_x_tick.vh\n             data/full_repos/permissive/437632408/NVDLA/nvdla/sdp,data/full_repos/permissive/437632408/simulate_x_tick.vh.v\n             data/full_repos/permissive/437632408/NVDLA/nvdla/sdp,data/full_repos/permissive/437632408/simulate_x_tick.vh.sv\n             simulate_x_tick.vh\n             simulate_x_tick.vh.v\n             simulate_x_tick.vh.sv\n             obj_dir/simulate_x_tick.vh\n             obj_dir/simulate_x_tick.vh.v\n             obj_dir/simulate_x_tick.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module NV_NVDLA_SDP_MRDMA_eg (
   cq2eg_pd
  ,cq2eg_pvld
  ,cvif2sdp_rd_rsp_pd
  ,cvif2sdp_rd_rsp_valid
  ,mcif2sdp_rd_rsp_pd
  ,mcif2sdp_rd_rsp_valid
  ,nvdla_core_clk
  ,nvdla_core_rstn
  ,op_load
  ,pwrbus_ram_pd
  ,reg2dp_height
  ,reg2dp_in_precision
  ,reg2dp_perf_nan_inf_count_en
  ,reg2dp_proc_precision
  ,reg2dp_src_ram_type
  ,reg2dp_width
  ,sdp_mrdma2cmux_ready
  ,cq2eg_prdy
  ,cvif2sdp_rd_rsp_ready
  ,dp2reg_status_inf_input_num
  ,dp2reg_status_nan_input_num
  ,eg_done
  ,mcif2sdp_rd_rsp_ready
  ,sdp2cvif_rd_cdt_lat_fifo_pop
  ,sdp2mcif_rd_cdt_lat_fifo_pop
  ,sdp_mrdma2cmux_pd
  ,sdp_mrdma2cmux_valid
  );



input nvdla_core_clk;
input nvdla_core_rstn;
input cq2eg_pvld;
output cq2eg_prdy;
input [13:0] cq2eg_pd;
input cvif2sdp_rd_rsp_valid;
output cvif2sdp_rd_rsp_ready;
input [513:0] cvif2sdp_rd_rsp_pd;
input mcif2sdp_rd_rsp_valid;
output mcif2sdp_rd_rsp_ready;
input [513:0] mcif2sdp_rd_rsp_pd;
input [31:0] pwrbus_ram_pd;
output sdp2cvif_rd_cdt_lat_fifo_pop;
output sdp2mcif_rd_cdt_lat_fifo_pop;
output sdp_mrdma2cmux_valid;
input sdp_mrdma2cmux_ready;
output [513:0] sdp_mrdma2cmux_pd;
input op_load;
output eg_done;
input [12:0] reg2dp_height;
input [1:0] reg2dp_in_precision;
input reg2dp_perf_nan_inf_count_en;
input [1:0] reg2dp_proc_precision;
input reg2dp_src_ram_type;
input [12:0] reg2dp_width;
output [31:0] dp2reg_status_inf_input_num;
output [31:0] dp2reg_status_nan_input_num;
wire [14:0] cmd2dat_dma_pd;
wire cmd2dat_dma_prdy;
wire cmd2dat_dma_pvld;
wire [12:0] cmd2dat_spt_pd;
wire cmd2dat_spt_prdy;
wire cmd2dat_spt_pvld;
wire [127:0] pfifo0_rd_pd;
wire pfifo0_rd_prdy;
wire pfifo0_rd_pvld;
wire [127:0] pfifo1_rd_pd;
wire pfifo1_rd_prdy;
wire pfifo1_rd_pvld;
wire [127:0] pfifo2_rd_pd;
wire pfifo2_rd_prdy;
wire pfifo2_rd_pvld;
wire [127:0] pfifo3_rd_pd;
wire pfifo3_rd_prdy;
wire pfifo3_rd_pvld;
wire [255:0] sfifo0_rd_pd;
wire sfifo0_rd_prdy;
wire sfifo0_rd_pvld;
wire [255:0] sfifo1_rd_pd;
wire sfifo1_rd_prdy;
wire sfifo1_rd_pvld;
NV_NVDLA_SDP_MRDMA_EG_cmd u_cmd (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.cq2eg_pvld (cq2eg_pvld)
  ,.cq2eg_prdy (cq2eg_prdy)
  ,.cq2eg_pd (cq2eg_pd[13:0])
  ,.cmd2dat_spt_pvld (cmd2dat_spt_pvld)
  ,.cmd2dat_spt_prdy (cmd2dat_spt_prdy)
  ,.cmd2dat_spt_pd (cmd2dat_spt_pd[12:0])
  ,.cmd2dat_dma_pvld (cmd2dat_dma_pvld)
  ,.cmd2dat_dma_prdy (cmd2dat_dma_prdy)
  ,.cmd2dat_dma_pd (cmd2dat_dma_pd[14:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  ,.eg_done (eg_done)
  ,.reg2dp_height (reg2dp_height[12:0])
  ,.reg2dp_in_precision (reg2dp_in_precision[1:0])
  ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0])
  ,.reg2dp_width (reg2dp_width[12:0])
  );
NV_NVDLA_SDP_MRDMA_EG_din u_din (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.cmd2dat_spt_pvld (cmd2dat_spt_pvld)
  ,.cmd2dat_spt_prdy (cmd2dat_spt_prdy)
  ,.cmd2dat_spt_pd (cmd2dat_spt_pd[12:0])
  ,.pfifo0_rd_pvld (pfifo0_rd_pvld)
  ,.pfifo0_rd_prdy (pfifo0_rd_prdy)
  ,.pfifo0_rd_pd (pfifo0_rd_pd[127:0])
  ,.pfifo1_rd_pvld (pfifo1_rd_pvld)
  ,.pfifo1_rd_prdy (pfifo1_rd_prdy)
  ,.pfifo1_rd_pd (pfifo1_rd_pd[127:0])
  ,.pfifo2_rd_pvld (pfifo2_rd_pvld)
  ,.pfifo2_rd_prdy (pfifo2_rd_prdy)
  ,.pfifo2_rd_pd (pfifo2_rd_pd[127:0])
  ,.pfifo3_rd_pvld (pfifo3_rd_pvld)
  ,.pfifo3_rd_prdy (pfifo3_rd_prdy)
  ,.pfifo3_rd_pd (pfifo3_rd_pd[127:0])
  ,.sfifo0_rd_pvld (sfifo0_rd_pvld)
  ,.sfifo0_rd_prdy (sfifo0_rd_prdy)
  ,.sfifo0_rd_pd (sfifo0_rd_pd[255:0])
  ,.sfifo1_rd_pvld (sfifo1_rd_pvld)
  ,.sfifo1_rd_prdy (sfifo1_rd_prdy)
  ,.sfifo1_rd_pd (sfifo1_rd_pd[255:0])
  ,.mcif2sdp_rd_rsp_valid (mcif2sdp_rd_rsp_valid)
  ,.mcif2sdp_rd_rsp_ready (mcif2sdp_rd_rsp_ready)
  ,.mcif2sdp_rd_rsp_pd (mcif2sdp_rd_rsp_pd[513:0])
  ,.cvif2sdp_rd_rsp_valid (cvif2sdp_rd_rsp_valid)
  ,.cvif2sdp_rd_rsp_ready (cvif2sdp_rd_rsp_ready)
  ,.cvif2sdp_rd_rsp_pd (cvif2sdp_rd_rsp_pd[513:0])
  ,.sdp2mcif_rd_cdt_lat_fifo_pop (sdp2mcif_rd_cdt_lat_fifo_pop)
  ,.sdp2cvif_rd_cdt_lat_fifo_pop (sdp2cvif_rd_cdt_lat_fifo_pop)
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  ,.reg2dp_src_ram_type (reg2dp_src_ram_type)
  );
NV_NVDLA_SDP_MRDMA_EG_dout u_dout (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.cmd2dat_dma_pvld (cmd2dat_dma_pvld)
  ,.cmd2dat_dma_prdy (cmd2dat_dma_prdy)
  ,.cmd2dat_dma_pd (cmd2dat_dma_pd[14:0])
  ,.pfifo0_rd_pvld (pfifo0_rd_pvld)
  ,.pfifo0_rd_prdy (pfifo0_rd_prdy)
  ,.pfifo0_rd_pd (pfifo0_rd_pd[127:0])
  ,.pfifo1_rd_pvld (pfifo1_rd_pvld)
  ,.pfifo1_rd_prdy (pfifo1_rd_prdy)
  ,.pfifo1_rd_pd (pfifo1_rd_pd[127:0])
  ,.pfifo2_rd_pvld (pfifo2_rd_pvld)
  ,.pfifo2_rd_prdy (pfifo2_rd_prdy)
  ,.pfifo2_rd_pd (pfifo2_rd_pd[127:0])
  ,.pfifo3_rd_pvld (pfifo3_rd_pvld)
  ,.pfifo3_rd_prdy (pfifo3_rd_prdy)
  ,.pfifo3_rd_pd (pfifo3_rd_pd[127:0])
  ,.sfifo0_rd_pvld (sfifo0_rd_pvld)
  ,.sfifo0_rd_prdy (sfifo0_rd_prdy)
  ,.sfifo0_rd_pd (sfifo0_rd_pd[255:0])
  ,.sfifo1_rd_pvld (sfifo1_rd_pvld)
  ,.sfifo1_rd_prdy (sfifo1_rd_prdy)
  ,.sfifo1_rd_pd (sfifo1_rd_pd[255:0])
  ,.sdp_mrdma2cmux_valid (sdp_mrdma2cmux_valid)
  ,.sdp_mrdma2cmux_ready (sdp_mrdma2cmux_ready)
  ,.sdp_mrdma2cmux_pd (sdp_mrdma2cmux_pd[513:0])
  ,.op_load (op_load)
  ,.eg_done (eg_done)
  ,.reg2dp_height (reg2dp_height[12:0])
  ,.reg2dp_in_precision (reg2dp_in_precision[1:0])
  ,.reg2dp_perf_nan_inf_count_en (reg2dp_perf_nan_inf_count_en)
  ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0])
  ,.reg2dp_width (reg2dp_width[12:0])
  ,.dp2reg_status_inf_input_num (dp2reg_status_inf_input_num[31:0])
  ,.dp2reg_status_nan_input_num (dp2reg_status_nan_input_num[31:0])
  );
endmodule
module NV_NVDLA_SDP_MRDMA_eg (
   cq2eg_pd
  ,cq2eg_pvld
  ,cvif2sdp_rd_rsp_pd
  ,cvif2sdp_rd_rsp_valid
  ,mcif2sdp_rd_rsp_pd
  ,mcif2sdp_rd_rsp_valid
  ,nvdla_core_clk
  ,nvdla_core_rstn
  ,op_load
  ,pwrbus_ram_pd
  ,reg2dp_height
  ,reg2dp_in_precision
  ,reg2dp_perf_nan_inf_count_en
  ,reg2dp_proc_precision
  ,reg2dp_src_ram_type
  ,reg2dp_width
  ,sdp_mrdma2cmux_ready
  ,cq2eg_prdy
  ,cvif2sdp_rd_rsp_ready
  ,dp2reg_status_inf_input_num
  ,dp2reg_status_nan_input_num
  ,eg_done
  ,mcif2sdp_rd_rsp_ready
  ,sdp2cvif_rd_cdt_lat_fifo_pop
  ,sdp2mcif_rd_cdt_lat_fifo_pop
  ,sdp_mrdma2cmux_pd
  ,sdp_mrdma2cmux_valid
  );




input nvdla_core_clk;
input nvdla_core_rstn;
input cq2eg_pvld;
output cq2eg_prdy;
input [13:0] cq2eg_pd;
input cvif2sdp_rd_rsp_valid;
output cvif2sdp_rd_rsp_ready;
input [513:0] cvif2sdp_rd_rsp_pd;
input mcif2sdp_rd_rsp_valid;
output mcif2sdp_rd_rsp_ready;
input [513:0] mcif2sdp_rd_rsp_pd;
input [31:0] pwrbus_ram_pd;
output sdp2cvif_rd_cdt_lat_fifo_pop;
output sdp2mcif_rd_cdt_lat_fifo_pop;
output sdp_mrdma2cmux_valid;
input sdp_mrdma2cmux_ready;
output [513:0] sdp_mrdma2cmux_pd;
input op_load;
output eg_done;
input [12:0] reg2dp_height;
input [1:0] reg2dp_in_precision;
input reg2dp_perf_nan_inf_count_en;
input [1:0] reg2dp_proc_precision;
input reg2dp_src_ram_type;
input [12:0] reg2dp_width;
output [31:0] dp2reg_status_inf_input_num;
output [31:0] dp2reg_status_nan_input_num;
wire [14:0] cmd2dat_dma_pd;
wire cmd2dat_dma_prdy;
wire cmd2dat_dma_pvld;
wire [12:0] cmd2dat_spt_pd;
wire cmd2dat_spt_prdy;
wire cmd2dat_spt_pvld;
wire [127:0] pfifo0_rd_pd;
wire pfifo0_rd_prdy;
wire pfifo0_rd_pvld;
wire [127:0] pfifo1_rd_pd;
wire pfifo1_rd_prdy;
wire pfifo1_rd_pvld;
wire [127:0] pfifo2_rd_pd;
wire pfifo2_rd_prdy;
wire pfifo2_rd_pvld;
wire [127:0] pfifo3_rd_pd;
wire pfifo3_rd_prdy;
wire pfifo3_rd_pvld;
wire [255:0] sfifo0_rd_pd;
wire sfifo0_rd_prdy;
wire sfifo0_rd_pvld;
wire [255:0] sfifo1_rd_pd;
wire sfifo1_rd_prdy;
wire sfifo1_rd_pvld;
NV_NVDLA_SDP_MRDMA_EG_cmd u_cmd (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.cq2eg_pvld (cq2eg_pvld)
  ,.cq2eg_prdy (cq2eg_prdy)
  ,.cq2eg_pd (cq2eg_pd[13:0])
  ,.cmd2dat_spt_pvld (cmd2dat_spt_pvld)
  ,.cmd2dat_spt_prdy (cmd2dat_spt_prdy)
  ,.cmd2dat_spt_pd (cmd2dat_spt_pd[12:0])
  ,.cmd2dat_dma_pvld (cmd2dat_dma_pvld)
  ,.cmd2dat_dma_prdy (cmd2dat_dma_prdy)
  ,.cmd2dat_dma_pd (cmd2dat_dma_pd[14:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  ,.eg_done (eg_done)
  ,.reg2dp_height (reg2dp_height[12:0])
  ,.reg2dp_in_precision (reg2dp_in_precision[1:0])
  ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0])
  ,.reg2dp_width (reg2dp_width[12:0])
  );
NV_NVDLA_SDP_MRDMA_EG_din u_din (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.cmd2dat_spt_pvld (cmd2dat_spt_pvld)
  ,.cmd2dat_spt_prdy (cmd2dat_spt_prdy)
  ,.cmd2dat_spt_pd (cmd2dat_spt_pd[12:0])
  ,.pfifo0_rd_pvld (pfifo0_rd_pvld)
  ,.pfifo0_rd_prdy (pfifo0_rd_prdy)
  ,.pfifo0_rd_pd (pfifo0_rd_pd[127:0])
  ,.pfifo1_rd_pvld (pfifo1_rd_pvld)
  ,.pfifo1_rd_prdy (pfifo1_rd_prdy)
  ,.pfifo1_rd_pd (pfifo1_rd_pd[127:0])
  ,.pfifo2_rd_pvld (pfifo2_rd_pvld)
  ,.pfifo2_rd_prdy (pfifo2_rd_prdy)
  ,.pfifo2_rd_pd (pfifo2_rd_pd[127:0])
  ,.pfifo3_rd_pvld (pfifo3_rd_pvld)
  ,.pfifo3_rd_prdy (pfifo3_rd_prdy)
  ,.pfifo3_rd_pd (pfifo3_rd_pd[127:0])
  ,.sfifo0_rd_pvld (sfifo0_rd_pvld)
  ,.sfifo0_rd_prdy (sfifo0_rd_prdy)
  ,.sfifo0_rd_pd (sfifo0_rd_pd[255:0])
  ,.sfifo1_rd_pvld (sfifo1_rd_pvld)
  ,.sfifo1_rd_prdy (sfifo1_rd_prdy)
  ,.sfifo1_rd_pd (sfifo1_rd_pd[255:0])
  ,.mcif2sdp_rd_rsp_valid (mcif2sdp_rd_rsp_valid)
  ,.mcif2sdp_rd_rsp_ready (mcif2sdp_rd_rsp_ready)
  ,.mcif2sdp_rd_rsp_pd (mcif2sdp_rd_rsp_pd[513:0])
  ,.cvif2sdp_rd_rsp_valid (cvif2sdp_rd_rsp_valid)
  ,.cvif2sdp_rd_rsp_ready (cvif2sdp_rd_rsp_ready)
  ,.cvif2sdp_rd_rsp_pd (cvif2sdp_rd_rsp_pd[513:0])
  ,.sdp2mcif_rd_cdt_lat_fifo_pop (sdp2mcif_rd_cdt_lat_fifo_pop)
  ,.sdp2cvif_rd_cdt_lat_fifo_pop (sdp2cvif_rd_cdt_lat_fifo_pop)
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  ,.reg2dp_src_ram_type (reg2dp_src_ram_type)
  );
NV_NVDLA_SDP_MRDMA_EG_dout u_dout (
   .nvdla_core_clk (nvdla_core_clk)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.cmd2dat_dma_pvld (cmd2dat_dma_pvld)
  ,.cmd2dat_dma_prdy (cmd2dat_dma_prdy)
  ,.cmd2dat_dma_pd (cmd2dat_dma_pd[14:0])
  ,.pfifo0_rd_pvld (pfifo0_rd_pvld)
  ,.pfifo0_rd_prdy (pfifo0_rd_prdy)
  ,.pfifo0_rd_pd (pfifo0_rd_pd[127:0])
  ,.pfifo1_rd_pvld (pfifo1_rd_pvld)
  ,.pfifo1_rd_prdy (pfifo1_rd_prdy)
  ,.pfifo1_rd_pd (pfifo1_rd_pd[127:0])
  ,.pfifo2_rd_pvld (pfifo2_rd_pvld)
  ,.pfifo2_rd_prdy (pfifo2_rd_prdy)
  ,.pfifo2_rd_pd (pfifo2_rd_pd[127:0])
  ,.pfifo3_rd_pvld (pfifo3_rd_pvld)
  ,.pfifo3_rd_prdy (pfifo3_rd_prdy)
  ,.pfifo3_rd_pd (pfifo3_rd_pd[127:0])
  ,.sfifo0_rd_pvld (sfifo0_rd_pvld)
  ,.sfifo0_rd_prdy (sfifo0_rd_prdy)
  ,.sfifo0_rd_pd (sfifo0_rd_pd[255:0])
  ,.sfifo1_rd_pvld (sfifo1_rd_pvld)
  ,.sfifo1_rd_prdy (sfifo1_rd_prdy)
  ,.sfifo1_rd_pd (sfifo1_rd_pd[255:0])
  ,.sdp_mrdma2cmux_valid (sdp_mrdma2cmux_valid)
  ,.sdp_mrdma2cmux_ready (sdp_mrdma2cmux_ready)
  ,.sdp_mrdma2cmux_pd (sdp_mrdma2cmux_pd[513:0])
  ,.op_load (op_load)
  ,.eg_done (eg_done)
  ,.reg2dp_height (reg2dp_height[12:0])
  ,.reg2dp_in_precision (reg2dp_in_precision[1:0])
  ,.reg2dp_perf_nan_inf_count_en (reg2dp_perf_nan_inf_count_en)
  ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0])
  ,.reg2dp_width (reg2dp_width[12:0])
  ,.dp2reg_status_inf_input_num (dp2reg_status_inf_input_num[31:0])
  ,.dp2reg_status_nan_input_num (dp2reg_status_nan_input_num[31:0])
  );
endmodule