data/full_repos/permissive/460328193/ipa_proj_seq/execute_tb.v
1: b'%Error: data/full_repos/permissive/460328193/ipa_proj_seq/execute_tb.v:1: Cannot find include file: execute.v\n`include "execute.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/460328193/ipa_proj_seq,data/full_repos/permissive/460328193/execute.v\n             data/full_repos/permissive/460328193/ipa_proj_seq,data/full_repos/permissive/460328193/execute.v.v\n             data/full_repos/permissive/460328193/ipa_proj_seq,data/full_repos/permissive/460328193/execute.v.sv\n             execute.v\n             execute.v.v\n             execute.v.sv\n             obj_dir/execute.v\n             obj_dir/execute.v.v\n             obj_dir/execute.v.sv\n%Error: data/full_repos/permissive/460328193/ipa_proj_seq/execute_tb.v:18: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("execute.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/460328193/ipa_proj_seq/execute_tb.v:19: Unsupported or unknown PLI call: $dumpvars\n     $dumpvars(0,icode,ifun,valC,valA,valB,valE,Cnd,clk);\n     ^~~~~~~~~\n%Error: data/full_repos/permissive/460328193/ipa_proj_seq/execute_tb.v:22: Too many digits for 32 bit number: \'hFFFFFFFFFFFFFFFF\n valA=\'hFFFFFFFFFFFFFFFF;\n      ^~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/460328193/ipa_proj_seq/execute_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/460328193/ipa_proj_seq/execute_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module testbench;
reg [3:0] icode;
reg [3:0] ifun;
reg [63:0] valC;
reg [63:0] valA;
reg [63:0] valB;
reg clk;
wire Cnd;
wire [63:0] valE;
integer i,j,k;
execute DUT(icode,ifun,valC,valA,valB,valE,Cnd,clk);


initial begin

	$dumpfile("execute.vcd");
    	$dumpvars(0,icode,ifun,valC,valA,valB,valE,Cnd,clk);
	clk=0;
	icode=4'h6;
	valA='hFFFFFFFFFFFFFFFF;
    ifun=4'h0;
	valC='h4;


	for(j=0;j<3;j++) begin 

    valB=j+1;

	clk=1;
	#10;
	clk=0;
	#10;
	end


end
endmodule
module testbench;

reg [3:0] icode;
reg [3:0] ifun;
reg [63:0] valC;
reg [63:0] valA;
reg [63:0] valB;
reg clk;
wire Cnd;
wire [63:0] valE;
integer i,j,k;
execute DUT(icode,ifun,valC,valA,valB,valE,Cnd,clk);


initial begin

	$dumpfile("execute.vcd");
    	$dumpvars(0,icode,ifun,valC,valA,valB,valE,Cnd,clk);
	clk=0;
	icode=4'h6;
	valA='hFFFFFFFFFFFFFFFF;
    ifun=4'h0;
	valC='h4;


	for(j=0;j<3;j++) begin 

    valB=j+1;

	clk=1;
	#10;
	clk=0;
	#10;
	end


end
endmodule