data/full_repos/permissive/488894374/src/cache.sv
1: b"%Error: data/full_repos/permissive/488894374/src/cache.sv:109: Cannot find file containing module: 'main_mem'\n    main_mem #(     \n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/488894374/src,data/full_repos/permissive/488894374/main_mem\n             data/full_repos/permissive/488894374/src,data/full_repos/permissive/488894374/main_mem.v\n             data/full_repos/permissive/488894374/src,data/full_repos/permissive/488894374/main_mem.sv\n             main_mem\n             main_mem.v\n             main_mem.sv\n             obj_dir/main_mem\n             obj_dir/main_mem.v\n             obj_dir/main_mem.sv\n%Error: Exiting due to 1 error(s)\n"
module cache #(
        parameter  LINE_ADDR_LEN = 3,
        parameter  SET_ADDR_LEN  = 3,
        parameter  TAG_ADDR_LEN  = 6
    )(
        input  clk,
        output miss,
        input  [31:0] addr,
        input  rd_req,
        output reg [31:0] rd_data,
        input  wr_req,
        input  [31:0] wr_data
    );

    localparam MEM_ADDR_LEN    = TAG_ADDR_LEN + SET_ADDR_LEN ;
    localparam UNUSED_ADDR_LEN = 32 - TAG_ADDR_LEN - SET_ADDR_LEN - LINE_ADDR_LEN - 2 ;

    localparam LINE_SIZE       = 1 << LINE_ADDR_LEN  ;
    localparam SET_SIZE        = 1 << SET_ADDR_LEN   ;

    reg [            31:0] cache_mem    [SET_SIZE][LINE_SIZE];
    reg [TAG_ADDR_LEN-1:0] cache_tags   [SET_SIZE];
    reg                    valid        [SET_SIZE];
    reg                    dirty        [SET_SIZE];

    assign rd_data = cache_mem[set_addr][line_addr];

    wire [              2-1 :0]   word_addr;
    wire [  LINE_ADDR_LEN-1 :0]   line_addr;
    wire [   SET_ADDR_LEN-1 :0]    set_addr;
    wire [   TAG_ADDR_LEN-1 :0]    tag_addr;
    wire [UNUSED_ADDR_LEN-1 :0] unused_addr;

    enum  {IDLE, SWAP_OUT, SWAP_IN, SWAP_IN_OK} cache_stat;


    reg [   SET_ADDR_LEN-1 :0] mem_rd_set_addr = 0;
    reg [   TAG_ADDR_LEN-1 :0] mem_rd_tag_addr = 0;
    wire[   MEM_ADDR_LEN-1 :0] mem_rd_addr = {mem_rd_tag_addr, mem_rd_set_addr};
    reg [   MEM_ADDR_LEN-1 :0] mem_wr_addr = 0;

    reg  [31:0] mem_wr_line [LINE_SIZE];
    wire [31:0] mem_rd_line [LINE_SIZE];

    wire mem_gnt;

    assign {unused_addr, tag_addr, set_addr, line_addr, word_addr} = addr;

    reg cache_hit = 1'b0;
    always @ (*) begin
        if(valid[set_addr] && cache_tags[set_addr] == tag_addr)
            cache_hit = 1'b1;
        else
            cache_hit = 1'b0;
    end

    always @ (posedge clk) begin
        case(cache_stat)
            IDLE:       begin
                if(cache_hit) begin
                    if(wr_req) begin
                        cache_mem[set_addr][line_addr] <= wr_data;
                        dirty[set_addr] <= 1'b1;
                    end
                end
                else begin
                    if(wr_req | rd_req) begin
                        if(valid[set_addr] & dirty[set_addr]) begin
                            cache_stat  <= SWAP_OUT;
                            mem_wr_addr <= { cache_tags[set_addr], set_addr };
                            mem_wr_line <= cache_mem[set_addr];
                        end
                        else begin
                            cache_stat  <= SWAP_IN;
                        end
                        {mem_rd_tag_addr, mem_rd_set_addr} <= {tag_addr, set_addr};
                    end
                end
            end
            SWAP_OUT:   begin
                if(mem_gnt) begin
                    cache_stat <= SWAP_IN;
                end
            end
            SWAP_IN:    begin
                if(mem_gnt) begin
                    cache_stat <= SWAP_IN_OK;
                end
            end
            SWAP_IN_OK: begin
                for(integer i=0; i<LINE_SIZE; i++)
                    cache_mem[mem_rd_set_addr][i] <= mem_rd_line[i];
                cache_tags[mem_rd_set_addr] <= mem_rd_tag_addr;
                valid     [mem_rd_set_addr] <= 1'b1;
                dirty     [mem_rd_set_addr] <= 1'b0;
                cache_stat <= IDLE;
            end
        endcase
    end

    wire mem_rd_req = (cache_stat == SWAP_IN);
    wire mem_wr_req = (cache_stat == SWAP_OUT);
    wire [   MEM_ADDR_LEN-1 :0] mem_addr = mem_rd_req ? mem_rd_addr : (mem_wr_req ? mem_wr_addr : 0);

    assign miss = (rd_req | wr_req) & ~(cache_hit && cache_stat == IDLE) ;

    main_mem #(
                 .LINE_ADDR_LEN  ( LINE_ADDR_LEN         ),
                 .ADDR_LEN       ( MEM_ADDR_LEN          )
             ) main_mem_instance (
                 .clk            ( clk                   ),
                 .rst            ( 0                     ),
                 .gnt            ( mem_gnt               ),
                 .addr           ( mem_addr              ),
                 .rd_req         ( mem_rd_req            ),
                 .rd_line        ( mem_rd_line           ),
                 .wr_req         ( mem_wr_req            ),
                 .wr_line        ( mem_wr_line           )
             );

endmodule
module cache #(
        parameter  LINE_ADDR_LEN = 3,
        parameter  SET_ADDR_LEN  = 3,
        parameter  TAG_ADDR_LEN  = 6
    )(
        input  clk,
        output miss,
        input  [31:0] addr,
        input  rd_req,
        output reg [31:0] rd_data,
        input  wr_req,
        input  [31:0] wr_data
    );


    localparam MEM_ADDR_LEN    = TAG_ADDR_LEN + SET_ADDR_LEN ;
    localparam UNUSED_ADDR_LEN = 32 - TAG_ADDR_LEN - SET_ADDR_LEN - LINE_ADDR_LEN - 2 ;

    localparam LINE_SIZE       = 1 << LINE_ADDR_LEN  ;
    localparam SET_SIZE        = 1 << SET_ADDR_LEN   ;

    reg [            31:0] cache_mem    [SET_SIZE][LINE_SIZE];
    reg [TAG_ADDR_LEN-1:0] cache_tags   [SET_SIZE];
    reg                    valid        [SET_SIZE];
    reg                    dirty        [SET_SIZE];

    assign rd_data = cache_mem[set_addr][line_addr];

    wire [              2-1 :0]   word_addr;
    wire [  LINE_ADDR_LEN-1 :0]   line_addr;
    wire [   SET_ADDR_LEN-1 :0]    set_addr;
    wire [   TAG_ADDR_LEN-1 :0]    tag_addr;
    wire [UNUSED_ADDR_LEN-1 :0] unused_addr;

    enum  {IDLE, SWAP_OUT, SWAP_IN, SWAP_IN_OK} cache_stat;


    reg [   SET_ADDR_LEN-1 :0] mem_rd_set_addr = 0;
    reg [   TAG_ADDR_LEN-1 :0] mem_rd_tag_addr = 0;
    wire[   MEM_ADDR_LEN-1 :0] mem_rd_addr = {mem_rd_tag_addr, mem_rd_set_addr};
    reg [   MEM_ADDR_LEN-1 :0] mem_wr_addr = 0;

    reg  [31:0] mem_wr_line [LINE_SIZE];
    wire [31:0] mem_rd_line [LINE_SIZE];

    wire mem_gnt;

    assign {unused_addr, tag_addr, set_addr, line_addr, word_addr} = addr;

    reg cache_hit = 1'b0;
    always @ (*) begin
        if(valid[set_addr] && cache_tags[set_addr] == tag_addr)
            cache_hit = 1'b1;
        else
            cache_hit = 1'b0;
    end

    always @ (posedge clk) begin
        case(cache_stat)
            IDLE:       begin
                if(cache_hit) begin
                    if(wr_req) begin
                        cache_mem[set_addr][line_addr] <= wr_data;
                        dirty[set_addr] <= 1'b1;
                    end
                end
                else begin
                    if(wr_req | rd_req) begin
                        if(valid[set_addr] & dirty[set_addr]) begin
                            cache_stat  <= SWAP_OUT;
                            mem_wr_addr <= { cache_tags[set_addr], set_addr };
                            mem_wr_line <= cache_mem[set_addr];
                        end
                        else begin
                            cache_stat  <= SWAP_IN;
                        end
                        {mem_rd_tag_addr, mem_rd_set_addr} <= {tag_addr, set_addr};
                    end
                end
            end
            SWAP_OUT:   begin
                if(mem_gnt) begin
                    cache_stat <= SWAP_IN;
                end
            end
            SWAP_IN:    begin
                if(mem_gnt) begin
                    cache_stat <= SWAP_IN_OK;
                end
            end
            SWAP_IN_OK: begin
                for(integer i=0; i<LINE_SIZE; i++)
                    cache_mem[mem_rd_set_addr][i] <= mem_rd_line[i];
                cache_tags[mem_rd_set_addr] <= mem_rd_tag_addr;
                valid     [mem_rd_set_addr] <= 1'b1;
                dirty     [mem_rd_set_addr] <= 1'b0;
                cache_stat <= IDLE;
            end
        endcase
    end

    wire mem_rd_req = (cache_stat == SWAP_IN);
    wire mem_wr_req = (cache_stat == SWAP_OUT);
    wire [   MEM_ADDR_LEN-1 :0] mem_addr = mem_rd_req ? mem_rd_addr : (mem_wr_req ? mem_wr_addr : 0);

    assign miss = (rd_req | wr_req) & ~(cache_hit && cache_stat == IDLE) ;

    main_mem #(
                 .LINE_ADDR_LEN  ( LINE_ADDR_LEN         ),
                 .ADDR_LEN       ( MEM_ADDR_LEN          )
             ) main_mem_instance (
                 .clk            ( clk                   ),
                 .rst            ( 0                     ),
                 .gnt            ( mem_gnt               ),
                 .addr           ( mem_addr              ),
                 .rd_req         ( mem_rd_req            ),
                 .rd_line        ( mem_rd_line           ),
                 .wr_req         ( mem_wr_req            ),
                 .wr_line        ( mem_wr_line           )
             );

endmodule