data/full_repos/permissive/469509877/rtl/libs/m8_1e.v
data/verilator_xmls/f1228297-9ee7-42f0-ba11-81a7fbeed48c.xml
module m8_1e(
    input [7:0] in,
    input [2:0] sel,
    input e,
    output o
    );
    
    assign o = e & ((in[0] & (~sel[2] & ~sel[1] & ~sel[0])) | 
                    (in[1] & (~sel[2] & ~sel[1] &  sel[0])) |
                    (in[2] & (~sel[2] &  sel[1] & ~sel[0])) | 
                    (in[3] & (~sel[2] &  sel[1] &  sel[0])) |
                    (in[4] & ( sel[2] & ~sel[1] & ~sel[0])) |
                    (in[5] & ( sel[2] & ~sel[1] &  sel[0])) |
                    (in[6] & ( sel[2] &  sel[1] & ~sel[0])) | 
                    (in[7] & ( sel[2] &  sel[1] &  sel[0])));
                    
endmodule
module m8_1e(
    input [7:0] in,
    input [2:0] sel,
    input e,
    output o
    );

    
    assign o = e & ((in[0] & (~sel[2] & ~sel[1] & ~sel[0])) | 
                    (in[1] & (~sel[2] & ~sel[1] &  sel[0])) |
                    (in[2] & (~sel[2] &  sel[1] & ~sel[0])) | 
                    (in[3] & (~sel[2] &  sel[1] &  sel[0])) |
                    (in[4] & ( sel[2] & ~sel[1] & ~sel[0])) |
                    (in[5] & ( sel[2] & ~sel[1] &  sel[0])) |
                    (in[6] & ( sel[2] &  sel[1] & ~sel[0])) | 
                    (in[7] & ( sel[2] &  sel[1] &  sel[0])));
                    
endmodule