data/full_repos/permissive/435890256/my_riscv/riscv_id.sv
data/verilator_xmls/4cf42f70-43c1-48bb-a2c1-554eff0eb211.xml
module riscv_id(
  input logic [31:0] i_instr,

  output logic [6:0] o_opcode,
  output logic [6:0] o_funct7,
  output logic [2:0] o_funct3,
  output logic [31:0] o_imm_num,


  output logic o_src1_reg_en,
  output logic o_src2_reg_en,
  output logic [4:0] o_src1_reg_addr, 
  output logic [4:0] o_src2_reg_addr,


  output logic o_jal,




  output logic o_alures2reg,


  output logic o_memory2reg,


  output logic o_mem_write,


  output logic [4:0] o_dst_reg_addr


);






parameter OP_LUI    = 7'b0110111;
parameter OP_AUIPC  = 7'b0010111;
parameter OP_JAL    = 7'b1101111;
parameter OP_JALR   = 7'b1100111;
parameter OP_BRANCH = 7'b1100011;
parameter OP_LOAD   = 7'b0000011;
parameter OP_STORE  = 7'b0100011;
parameter OP_ALI    = 7'b0010011;
parameter OP_ALR    = 7'b0110011;



assign {o_funct7, o_src2_reg_addr, o_src1_reg_addr, o_funct3, o_dst_reg_addr, o_opcode} = i_instr;


enum {UKNOWN_TYPE, R_TYPE, I_TYPE, S_TYPE, B_TYPE, U_TYPE, J_TYPE} instr_type;

assign o_jal = (o_opcode == OP_JAL);
assign o_memory2reg = (o_opcode == OP_LOAD);
assign o_mem_write = (o_opcode == OP_STORE);
assign o_alures2reg = (o_opcode == OP_LUI || o_opcode == OP_AUIPC ||
                       o_opcode == OP_JAL || o_opcode == OP_JALR ||
                       o_opcode == OP_ALI || o_opcode == OP_ALR );



always_comb begin
  case(o_opcode)
    OP_LUI : instr_type <= U_TYPE;
    OP_AUIPC : instr_type <= U_TYPE;
    OP_JAL : instr_type <= J_TYPE;
    OP_JALR : instr_type <= I_TYPE;
    OP_BRANCH : instr_type <= B_TYPE;
    OP_LOAD : instr_type <= I_TYPE;
    OP_STORE : instr_type <= S_TYPE;
    OP_ALI : instr_type <= I_TYPE;
    OP_ALR : instr_type <= R_TYPE;
  endcase
end


always_comb begin
  case(instr_type)
    I_TYPE : o_imm_num <= {{20{i_instr[31]}}, i_instr[31:20]};
    S_TYPE : o_imm_num <= {{20{i_instr[31]}}, i_instr[31:25], i_instr[11:7]};
    B_TYPE : o_imm_num <= {{20{i_instr[31]}}, i_instr[7], i_instr[30:25], i_instr[11:8], 1'b0};
    U_TYPE : o_imm_num <= {i_instr[31:12], 12'h0};
    J_TYPE : o_imm_num <= {{12{i_instr[31]}}, i_instr[19:12], i_instr[20], i_instr[30:21], 1'b0};
    default: o_imm_num <= 0;
  endcase
end


always_comb begin
  case(instr_type)
    R_TYPE : {o_src2_reg_en, o_src1_reg_en} <= 2'b11;
    I_TYPE : {o_src2_reg_en, o_src1_reg_en} <= 2'b01;
    S_TYPE : {o_src2_reg_en, o_src1_reg_en} <= 2'b11;
    B_TYPE : {o_src2_reg_en, o_src1_reg_en} <= 2'b11;
    default: {o_src2_reg_en, o_src1_reg_en} <= 2'b00;
  endcase
end
  
endmodule
module riscv_id(
  input logic [31:0] i_instr,

  output logic [6:0] o_opcode,
  output logic [6:0] o_funct7,
  output logic [2:0] o_funct3,
  output logic [31:0] o_imm_num,


  output logic o_src1_reg_en,
  output logic o_src2_reg_en,
  output logic [4:0] o_src1_reg_addr, 
  output logic [4:0] o_src2_reg_addr,


  output logic o_jal,




  output logic o_alures2reg,


  output logic o_memory2reg,


  output logic o_mem_write,


  output logic [4:0] o_dst_reg_addr


);







parameter OP_LUI    = 7'b0110111;
parameter OP_AUIPC  = 7'b0010111;
parameter OP_JAL    = 7'b1101111;
parameter OP_JALR   = 7'b1100111;
parameter OP_BRANCH = 7'b1100011;
parameter OP_LOAD   = 7'b0000011;
parameter OP_STORE  = 7'b0100011;
parameter OP_ALI    = 7'b0010011;
parameter OP_ALR    = 7'b0110011;



assign {o_funct7, o_src2_reg_addr, o_src1_reg_addr, o_funct3, o_dst_reg_addr, o_opcode} = i_instr;


enum {UKNOWN_TYPE, R_TYPE, I_TYPE, S_TYPE, B_TYPE, U_TYPE, J_TYPE} instr_type;

assign o_jal = (o_opcode == OP_JAL);
assign o_memory2reg = (o_opcode == OP_LOAD);
assign o_mem_write = (o_opcode == OP_STORE);
assign o_alures2reg = (o_opcode == OP_LUI || o_opcode == OP_AUIPC ||
                       o_opcode == OP_JAL || o_opcode == OP_JALR ||
                       o_opcode == OP_ALI || o_opcode == OP_ALR );



always_comb begin
  case(o_opcode)
    OP_LUI : instr_type <= U_TYPE;
    OP_AUIPC : instr_type <= U_TYPE;
    OP_JAL : instr_type <= J_TYPE;
    OP_JALR : instr_type <= I_TYPE;
    OP_BRANCH : instr_type <= B_TYPE;
    OP_LOAD : instr_type <= I_TYPE;
    OP_STORE : instr_type <= S_TYPE;
    OP_ALI : instr_type <= I_TYPE;
    OP_ALR : instr_type <= R_TYPE;
  endcase
end


always_comb begin
  case(instr_type)
    I_TYPE : o_imm_num <= {{20{i_instr[31]}}, i_instr[31:20]};
    S_TYPE : o_imm_num <= {{20{i_instr[31]}}, i_instr[31:25], i_instr[11:7]};
    B_TYPE : o_imm_num <= {{20{i_instr[31]}}, i_instr[7], i_instr[30:25], i_instr[11:8], 1'b0};
    U_TYPE : o_imm_num <= {i_instr[31:12], 12'h0};
    J_TYPE : o_imm_num <= {{12{i_instr[31]}}, i_instr[19:12], i_instr[20], i_instr[30:21], 1'b0};
    default: o_imm_num <= 0;
  endcase
end


always_comb begin
  case(instr_type)
    R_TYPE : {o_src2_reg_en, o_src1_reg_en} <= 2'b11;
    I_TYPE : {o_src2_reg_en, o_src1_reg_en} <= 2'b01;
    S_TYPE : {o_src2_reg_en, o_src1_reg_en} <= 2'b11;
    B_TYPE : {o_src2_reg_en, o_src1_reg_en} <= 2'b11;
    default: {o_src2_reg_en, o_src1_reg_en} <= 2'b00;
  endcase
end
  
endmodule