data/full_repos/permissive/425816165/rtl/videogen.v
1: b'%Warning-WIDTH: data/full_repos/permissive/425816165/rtl/videogen.v:70: Operator ASSIGNW expects 11 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 10 bits.\n                                                                      : ... In instance videogen\n wire [10:0] charaddr = {membuf[6:0], charY[3:1]};\n                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/425816165/rtl/videogen.v:71: Bit extraction of array[1023:0] requires 10 bit index, not 11 bits.\n                                                                      : ... In instance videogen\n wire [8:0] charline = charY[4] ? 0 : {1\'b0, chars[charaddr], 1\'b0};\n                                                  ^\n%Error: Exiting due to 2 warning(s)\n'
module videogen(
	input clock, reset,

	input wire [6:0] curX,
	input wire [4:0] curY,
	input wire [4:0] topline,
	input wire invert,
	output wire [10:0] screenmem_addr,
	input wire [6:0] screenmem_data,

	output wire hsync, vsync,
	output wire dataEnable,
	output reg vclk,
	output [23:0] RGBchannel
);

	reg [10:0] pixelH;
	reg [9:0] pixelV;

	initial begin
		pixelH     = 0;
		pixelV     = 0;
	end
	always @(posedge clock or posedge reset) begin
		if(reset) begin
			pixelH <= 0;
			pixelV <= 0;
		end else if(~vclk) begin
			if(pixelH==857) begin
				pixelH <= 0;
				if(pixelV==524)
					pixelV <= 0;
				else
					pixelV <= pixelV + 1;
			end else
				pixelH <= pixelH + 1;
		end
	end
	assign hsync = pixelH>=736 && pixelH<798;
	assign vsync = pixelV>=489 && pixelV<495;
	wire validH = pixelH<720;
	wire validV = pixelV<480;
	assign dataEnable = validH && validV;

	initial vclk = 0;
	always @(posedge clock or posedge reset) begin
		if(reset) vclk <= 0;
		else      vclk <= ~vclk;
	end

	addressmap addrmap(screenX, screenY, screenmem_addr);

	reg [6:0] chars[0:1024-1];
	reg [8:0] vsr;

	reg [6:0] lastX;
	reg [6:0] screenX;
	reg [4:0] screenY;
	reg [3:0] charX;
	reg [4:0] charY;
	reg [6:0] membuf;
	wire hsync_start = pixelH == 736;
	wire hsync_mid = pixelH == 760;
	wire hsync_end = pixelH == 790;
	initial $readmemh("vt52char.rom", chars);
	wire [10:0] charaddr = {membuf[6:0], charY[3:1]};
	wire [8:0] charline = charY[4] ? 0 : {1'b0, chars[charaddr], 1'b0};
	wire fetch = dataEnable && charX==8 || hsync_mid || hsync_end;
	wire doblink = blinkcnt[4] && (charY[4:1] == 8) && lastX == curX && screenY == curY;
	reg [4:0] blinkcnt;
	always @(posedge clock or posedge reset) begin
		if(reset) begin
			charX <= 0;
			charY <= 0;
			screenX <= 0;
			screenY <= 0;
			blinkcnt <= 0;
		end else if(~vclk) begin
			if(dataEnable) begin
				if(~fetch) begin
					charX <= charX + 1;
					vsr <= {vsr[7:0], 1'b0};
				end
			end


			if(hsync_start) begin
				screenX <= 0;
				if(validV) begin

					if(charY == 19) begin
						charY <= 0;
						if(screenY == 23)
							screenY <= 0;
						else
							screenY <= screenY + 1;
					end else begin
						charY <= charY + 1;
					end
				end else begin
					charY <= 0;
					screenY <= topline;
				end

				if(pixelV == 480)
					blinkcnt <= blinkcnt + 1;
			end

			if(fetch) begin
				charX <= 0;
				if(doblink)
					vsr <= 9'b011111111;
				else
					vsr <= charline;
				membuf <= screenmem_data;
				lastX <= screenX;
				screenX <= screenX + 1;
			end
		end
	end

	assign RGBchannel[23:16] = vsr[8]==invert ? 0 : 255;
	assign RGBchannel [15:8] = vsr[8]==invert ? 0 : 255;
	assign RGBchannel  [7:0] = vsr[8]==invert ? 0 : 255;
endmodule
module videogen(
	input clock, reset,

	input wire [6:0] curX,
	input wire [4:0] curY,
	input wire [4:0] topline,
	input wire invert,
	output wire [10:0] screenmem_addr,
	input wire [6:0] screenmem_data,

	output wire hsync, vsync,
	output wire dataEnable,
	output reg vclk,
	output [23:0] RGBchannel
);


	reg [10:0] pixelH;
	reg [9:0] pixelV;

	initial begin
		pixelH     = 0;
		pixelV     = 0;
	end
	always @(posedge clock or posedge reset) begin
		if(reset) begin
			pixelH <= 0;
			pixelV <= 0;
		end else if(~vclk) begin
			if(pixelH==857) begin
				pixelH <= 0;
				if(pixelV==524)
					pixelV <= 0;
				else
					pixelV <= pixelV + 1;
			end else
				pixelH <= pixelH + 1;
		end
	end
	assign hsync = pixelH>=736 && pixelH<798;
	assign vsync = pixelV>=489 && pixelV<495;
	wire validH = pixelH<720;
	wire validV = pixelV<480;
	assign dataEnable = validH && validV;

	initial vclk = 0;
	always @(posedge clock or posedge reset) begin
		if(reset) vclk <= 0;
		else      vclk <= ~vclk;
	end

	addressmap addrmap(screenX, screenY, screenmem_addr);

	reg [6:0] chars[0:1024-1];
	reg [8:0] vsr;

	reg [6:0] lastX;
	reg [6:0] screenX;
	reg [4:0] screenY;
	reg [3:0] charX;
	reg [4:0] charY;
	reg [6:0] membuf;
	wire hsync_start = pixelH == 736;
	wire hsync_mid = pixelH == 760;
	wire hsync_end = pixelH == 790;
	initial $readmemh("vt52char.rom", chars);
	wire [10:0] charaddr = {membuf[6:0], charY[3:1]};
	wire [8:0] charline = charY[4] ? 0 : {1'b0, chars[charaddr], 1'b0};
	wire fetch = dataEnable && charX==8 || hsync_mid || hsync_end;
	wire doblink = blinkcnt[4] && (charY[4:1] == 8) && lastX == curX && screenY == curY;
	reg [4:0] blinkcnt;
	always @(posedge clock or posedge reset) begin
		if(reset) begin
			charX <= 0;
			charY <= 0;
			screenX <= 0;
			screenY <= 0;
			blinkcnt <= 0;
		end else if(~vclk) begin
			if(dataEnable) begin
				if(~fetch) begin
					charX <= charX + 1;
					vsr <= {vsr[7:0], 1'b0};
				end
			end


			if(hsync_start) begin
				screenX <= 0;
				if(validV) begin

					if(charY == 19) begin
						charY <= 0;
						if(screenY == 23)
							screenY <= 0;
						else
							screenY <= screenY + 1;
					end else begin
						charY <= charY + 1;
					end
				end else begin
					charY <= 0;
					screenY <= topline;
				end

				if(pixelV == 480)
					blinkcnt <= blinkcnt + 1;
			end

			if(fetch) begin
				charX <= 0;
				if(doblink)
					vsr <= 9'b011111111;
				else
					vsr <= charline;
				membuf <= screenmem_data;
				lastX <= screenX;
				screenX <= screenX + 1;
			end
		end
	end

	assign RGBchannel[23:16] = vsr[8]==invert ? 0 : 255;
	assign RGBchannel [15:8] = vsr[8]==invert ? 0 : 255;
	assign RGBchannel  [7:0] = vsr[8]==invert ? 0 : 255;
endmodule