data/full_repos/permissive/509335294/ctu.v
data/verilator_xmls/e2ed49dc-6518-43af-8b8e-9bb2b63f9948.xml
module ctu(	input [2:0] 		opcode,
					input  				clk,
					output reg [1:0] 	regdst,
					output reg					jump,
					output reg					branch,
					output reg					memread,
					output reg [1:0]		memtoreg,
					output reg [1:0]		aluop,
					output reg					memwrite,
					output reg					alusrc,
					output reg					regwrite			
					);

initial begin
regdst <= 0;
jump <= 0;
branch <= 0;
memread <= 0;
memtoreg <= 0;
aluop <= 0;
memwrite <= 0;
alusrc <= 0;
regwrite <= 0;
end

always@(*) begin
	case(opcode)
		3'b000 :	begin

							$display("Curr. instruction: R/JR type instruction");
							regdst 		<= 1;
							jump 			<= 0;
							branch 		<= 0; 
							memread 	<= 0;
							memtoreg 	<= 0;
							aluop 		<= 0;
							memwrite 	<= 0;
							alusrc 		<= 0;
							regwrite 	<= 1;
						end
						
		3'b001 :	begin 

							$display("Curr. instruction: SLTI instruction");
							regdst 		<= 0;
							jump 			<= 0;
							branch 		<= 0;
							memread 	<= 0;
							memtoreg 	<= 0;
							aluop 		<= 2;
							memwrite 	<= 0;
							alusrc 		<= 1;
							regwrite 	<= 1;
						end
						
		3'b010 :	begin 

							$display("Curr. instruction: J instruction");
							regdst 		<= 0;
							jump 			<= 1;
							branch 		<= 0;
							memread 	<= 0;
							memtoreg 	<= 0;
							aluop 		<= 0;
							memwrite 	<= 0;
							alusrc 		<= 0; 
							regwrite 	<= 0;
						end
						
		3'b011 :	begin 

							$display("Curr. instruction: JAL instruction");
							regdst 		<= 2;
							jump 			<= 1;
							branch 		<= 0;
							memread 	<= 0;
							memtoreg 	<= 2;
							aluop 		<= 0;
							memwrite 	<= 0;
							alusrc 		<= 0;
							regwrite 	<= 1;
						end
						
		3'b100 :	begin 

							$display("Curr. instruction: LW instruction");
							regdst 		<= 0;
							jump 			<= 0;
							branch 		<= 0;
							memread 	<= 1;
							memtoreg 	<= 1;
							aluop 		<= 3;
							memwrite 	<= 0;
							alusrc 		<= 1; 
							regwrite 	<= 1;
						end
						
		3'b101 :	begin 

							$display("Curr. instruction: SW instruction");
							regdst 		<= 0;
							jump 			<= 0;
							branch 		<= 0;
							memread 	<= 0;
							memtoreg 	<= 0;
							aluop 		<= 3;
							memwrite 	<= 1;
							alusrc 		<= 1; 
							regwrite 	<= 0;
						end
						
		3'b110 :	begin 

							$display("Curr. instruction: BEQ instruction");
							regdst 		<= 0;
							jump 			<= 0;
							branch 		<= 1;
							memread 	<= 0;
							memtoreg 	<= 0;
							aluop 		<= 1;
							memwrite 	<= 0;
							alusrc 		<= 0;
							regwrite 	<= 0;
						end
						
		3'b111 :	begin 

							$display("Curr. instruction: ADDI instruction");
							regdst 		<= 0;
							jump 			<= 0;
							branch 		<= 0; 
							memread 	<= 0;
							memtoreg 	<= 0;
							aluop 		<= 3;
							memwrite 	<= 0;
							alusrc 		<= 1;
							regwrite 	<= 1;
						end
						
	endcase
	
end

endmodule
module ctu(	input [2:0] 		opcode,
					input  				clk,
					output reg [1:0] 	regdst,
					output reg					jump,
					output reg					branch,
					output reg					memread,
					output reg [1:0]		memtoreg,
					output reg [1:0]		aluop,
					output reg					memwrite,
					output reg					alusrc,
					output reg					regwrite			
					);


initial begin
regdst <= 0;
jump <= 0;
branch <= 0;
memread <= 0;
memtoreg <= 0;
aluop <= 0;
memwrite <= 0;
alusrc <= 0;
regwrite <= 0;
end

always@(*) begin
	case(opcode)
		3'b000 :	begin

							$display("Curr. instruction: R/JR type instruction");
							regdst 		<= 1;
							jump 			<= 0;
							branch 		<= 0; 
							memread 	<= 0;
							memtoreg 	<= 0;
							aluop 		<= 0;
							memwrite 	<= 0;
							alusrc 		<= 0;
							regwrite 	<= 1;
						end
						
		3'b001 :	begin 

							$display("Curr. instruction: SLTI instruction");
							regdst 		<= 0;
							jump 			<= 0;
							branch 		<= 0;
							memread 	<= 0;
							memtoreg 	<= 0;
							aluop 		<= 2;
							memwrite 	<= 0;
							alusrc 		<= 1;
							regwrite 	<= 1;
						end
						
		3'b010 :	begin 

							$display("Curr. instruction: J instruction");
							regdst 		<= 0;
							jump 			<= 1;
							branch 		<= 0;
							memread 	<= 0;
							memtoreg 	<= 0;
							aluop 		<= 0;
							memwrite 	<= 0;
							alusrc 		<= 0; 
							regwrite 	<= 0;
						end
						
		3'b011 :	begin 

							$display("Curr. instruction: JAL instruction");
							regdst 		<= 2;
							jump 			<= 1;
							branch 		<= 0;
							memread 	<= 0;
							memtoreg 	<= 2;
							aluop 		<= 0;
							memwrite 	<= 0;
							alusrc 		<= 0;
							regwrite 	<= 1;
						end
						
		3'b100 :	begin 

							$display("Curr. instruction: LW instruction");
							regdst 		<= 0;
							jump 			<= 0;
							branch 		<= 0;
							memread 	<= 1;
							memtoreg 	<= 1;
							aluop 		<= 3;
							memwrite 	<= 0;
							alusrc 		<= 1; 
							regwrite 	<= 1;
						end
						
		3'b101 :	begin 

							$display("Curr. instruction: SW instruction");
							regdst 		<= 0;
							jump 			<= 0;
							branch 		<= 0;
							memread 	<= 0;
							memtoreg 	<= 0;
							aluop 		<= 3;
							memwrite 	<= 1;
							alusrc 		<= 1; 
							regwrite 	<= 0;
						end
						
		3'b110 :	begin 

							$display("Curr. instruction: BEQ instruction");
							regdst 		<= 0;
							jump 			<= 0;
							branch 		<= 1;
							memread 	<= 0;
							memtoreg 	<= 0;
							aluop 		<= 1;
							memwrite 	<= 0;
							alusrc 		<= 0;
							regwrite 	<= 0;
						end
						
		3'b111 :	begin 

							$display("Curr. instruction: ADDI instruction");
							regdst 		<= 0;
							jump 			<= 0;
							branch 		<= 0; 
							memread 	<= 0;
							memtoreg 	<= 0;
							aluop 		<= 3;
							memwrite 	<= 0;
							alusrc 		<= 1;
							regwrite 	<= 1;
						end
						
	endcase
	
end

endmodule