data/full_repos/permissive/502764644/mpeg_audio_video/tb_MP2_Decode_16_fill.v
1: b'%Error: data/full_repos/permissive/502764644/mpeg_audio_video/tb_MP2_Decode_16_fill.v:17: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502764644/mpeg_audio_video,data/full_repos/permissive/502764644/defines.v\n             data/full_repos/permissive/502764644/mpeg_audio_video,data/full_repos/permissive/502764644/defines.v.v\n             data/full_repos/permissive/502764644/mpeg_audio_video,data/full_repos/permissive/502764644/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/tb_MP2_Decode_16_fill.v:94: syntax error, unexpected \'@\'\n @(posedge active);\n ^\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/tb_MP2_Decode_16_fill.v:98: syntax error, unexpected \'@\'\n  counter = counter + 1; @(posedge audio_decoder_clock); \n                         ^\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/tb_MP2_Decode_16_fill.v:100: syntax error, unexpected \'@\'\n  counter = counter + 1; @(posedge audio_decoder_clock);\n                         ^\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/tb_MP2_Decode_16_fill.v:103: syntax error, unexpected \'@\'\n    counter = counter + 1; @(posedge audio_decoder_clock);\n                           ^\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/tb_MP2_Decode_16_fill.v:107: syntax error, unexpected \'@\'\n   counter = counter + 1; @(posedge audio_decoder_clock);\n                          ^\n%Error: Exiting due to 6 error(s)\n'
module MP2_Decode_16(
	resetn,
	audio_decoder_clock,

	Decode_Start_I,
	Decode_Done_O,

	Bitstream_Byte_Allign_I,
	Bitstream_Data_I,
	Shift_Busy_I,
	Shift_En_O,

	AC97_RESETN_I,
	AC97_BIT_CLOCK_I,
	SAMPLE_FREQUENCY_I,
	SOURCE_SELECT_I,
	AC97_SYNCH_O,
	AC97_DATA_IN_I,
	AC97_DATA_OUT_O,
	AC97_BEEP_TONE_O,
	STARTUP_O,
Header_found,
	Audio_Sync_I,
	Audio_Sync_O
);
output reg Header_found;

input 				resetn;
input 				audio_decoder_clock;

input 				Decode_Start_I;
output 				Decode_Done_O;

input 				Bitstream_Byte_Allign_I;
input 	[15:0]	Bitstream_Data_I;
input 				Shift_Busy_I;
output reg [4:0]	Shift_En_O;

input 				AC97_RESETN_I;
input 				AC97_BIT_CLOCK_I;
input 	[1:0] 	SAMPLE_FREQUENCY_I;
input 				SOURCE_SELECT_I;
output 				AC97_SYNCH_O;
input 				AC97_DATA_IN_I;
output 				AC97_DATA_OUT_O;
output 				AC97_BEEP_TONE_O;
output 				STARTUP_O;

input 				Audio_Sync_I;
output 				Audio_Sync_O;

reg active, shift1, shift8;
wire frame_start;
integer counter;

assign Decode_Done_O = 1'b1;
assign Shift_En_O[4:2] = 3'h0;
assign Shift_En_O[1] = Audio_Sync_I & shift8;
assign Shift_En_O[0] = Audio_Sync_I & shift1 & ~frame_start;
assign AC97_SYNCH_O = 1'b0;
assign AC97_DATA_OUT_O = 1'b0;
assign AC97_BEEP_TONE_O = 1'b0;
assign STARTUP_O = 1'b1;
assign Audio_Sync_O = 1'b1;

assign frame_start = Bitstream_Byte_Allign_I & (Bitstream_Data_I == 16'hFFFD);

always @(negedge resetn) if (~resetn) Header_found <= 1'b0;

always @(posedge audio_decoder_clock or negedge resetn) begin
	if (~resetn) active <= 1'b0;
	else active <= Decode_Start_I;
end

initial begin
	counter = 0; shift1 = 1'b0; shift8 = 1'b0;
	@(posedge active);
	while (1) begin
		counter = 0;
		shift8 = 1'b1; 
		counter = counter + 1; @(posedge audio_decoder_clock); 
		shift1 = 1'b1; shift8 = 1'b0; 
		counter = counter + 1; @(posedge audio_decoder_clock);
		if (Audio_Sync_I)
			while (~frame_start) begin
				counter = counter + 1; @(posedge audio_decoder_clock);
			end
		shift1 = 1'b0;
		while (counter < 648000) begin
			counter = counter + 1; @(posedge audio_decoder_clock);
		end
	end
end	

endmodule
module MP2_Decode_16(
	resetn,
	audio_decoder_clock,

	Decode_Start_I,
	Decode_Done_O,

	Bitstream_Byte_Allign_I,
	Bitstream_Data_I,
	Shift_Busy_I,
	Shift_En_O,

	AC97_RESETN_I,
	AC97_BIT_CLOCK_I,
	SAMPLE_FREQUENCY_I,
	SOURCE_SELECT_I,
	AC97_SYNCH_O,
	AC97_DATA_IN_I,
	AC97_DATA_OUT_O,
	AC97_BEEP_TONE_O,
	STARTUP_O,
Header_found,
	Audio_Sync_I,
	Audio_Sync_O
);

output reg Header_found;

input 				resetn;
input 				audio_decoder_clock;

input 				Decode_Start_I;
output 				Decode_Done_O;

input 				Bitstream_Byte_Allign_I;
input 	[15:0]	Bitstream_Data_I;
input 				Shift_Busy_I;
output reg [4:0]	Shift_En_O;

input 				AC97_RESETN_I;
input 				AC97_BIT_CLOCK_I;
input 	[1:0] 	SAMPLE_FREQUENCY_I;
input 				SOURCE_SELECT_I;
output 				AC97_SYNCH_O;
input 				AC97_DATA_IN_I;
output 				AC97_DATA_OUT_O;
output 				AC97_BEEP_TONE_O;
output 				STARTUP_O;

input 				Audio_Sync_I;
output 				Audio_Sync_O;

reg active, shift1, shift8;
wire frame_start;
integer counter;

assign Decode_Done_O = 1'b1;
assign Shift_En_O[4:2] = 3'h0;
assign Shift_En_O[1] = Audio_Sync_I & shift8;
assign Shift_En_O[0] = Audio_Sync_I & shift1 & ~frame_start;
assign AC97_SYNCH_O = 1'b0;
assign AC97_DATA_OUT_O = 1'b0;
assign AC97_BEEP_TONE_O = 1'b0;
assign STARTUP_O = 1'b1;
assign Audio_Sync_O = 1'b1;

assign frame_start = Bitstream_Byte_Allign_I & (Bitstream_Data_I == 16'hFFFD);

always @(negedge resetn) if (~resetn) Header_found <= 1'b0;

always @(posedge audio_decoder_clock or negedge resetn) begin
	if (~resetn) active <= 1'b0;
	else active <= Decode_Start_I;
end

initial begin
	counter = 0; shift1 = 1'b0; shift8 = 1'b0;
	@(posedge active);
	while (1) begin
		counter = 0;
		shift8 = 1'b1; 
		counter = counter + 1; @(posedge audio_decoder_clock); 
		shift1 = 1'b1; shift8 = 1'b0; 
		counter = counter + 1; @(posedge audio_decoder_clock);
		if (Audio_Sync_I)
			while (~frame_start) begin
				counter = counter + 1; @(posedge audio_decoder_clock);
			end
		shift1 = 1'b0;
		while (counter < 648000) begin
			counter = counter + 1; @(posedge audio_decoder_clock);
		end
	end
end	

endmodule