data/full_repos/permissive/515245706/milestone3/countDown/countDown.v
1: b'%Warning-WIDTH: data/full_repos/permissive/515245706/milestone3/countDown/countDown.v:23: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'minuteOut\' generates 4 bits.\n                                                                                        : ... In instance countDown\n    secondOut <= minuteOut;\n              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module rateDivider(load, enable, clk, resetn, out);
	input enable, clk, resetn;
	input [25: 0] load;
	output out;
	
	reg [25: 0] cnt;
	
	
	always @(posedge clk)
	begin
		if (resetn == 1'b0)
			cnt <= load;
		else if (enable == 1'b1)
			begin
				if (cnt == 0)
					cnt <= load;
				else
					cnt <= cnt - 1;
			end
	end
	assign out = (cnt == 0)? 1: 0;
endmodule
module rateDivider(load, enable, clk, resetn, out);

	input enable, clk, resetn;
	input [25: 0] load;
	output out;
	
	reg [25: 0] cnt;
	
	
	always @(posedge clk)
	begin
		if (resetn == 1'b0)
			cnt <= load;
		else if (enable == 1'b1)
			begin
				if (cnt == 0)
					cnt <= load;
				else
					cnt <= cnt - 1;
			end
	end
	assign out = (cnt == 0)? 1: 0;
endmodule