data/full_repos/permissive/424312442/lab_6_digital clock/sources_1/new/clock.v
1: b'%Error: Cannot find file containing module: clock/sources_1/new,data/full_repos/permissive/424312442\n        ... Looked in:\n             data/full_repos/permissive/424312442/lab_6_digital/clock/sources_1/new,data/full_repos/permissive/424312442\n             data/full_repos/permissive/424312442/lab_6_digital/clock/sources_1/new,data/full_repos/permissive/424312442.v\n             data/full_repos/permissive/424312442/lab_6_digital/clock/sources_1/new,data/full_repos/permissive/424312442.sv\n             clock/sources_1/new,data/full_repos/permissive/424312442\n             clock/sources_1/new,data/full_repos/permissive/424312442.v\n             clock/sources_1/new,data/full_repos/permissive/424312442.sv\n             obj_dir/clock/sources_1/new,data/full_repos/permissive/424312442\n             obj_dir/clock/sources_1/new,data/full_repos/permissive/424312442.v\n             obj_dir/clock/sources_1/new,data/full_repos/permissive/424312442.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/424312442/lab_6_digital\n%Error: Cannot find file containing module: clock/sources_1/new/clock.v\n%Error: Exiting due to 3 error(s)\n'
module dig_cont(clk, an);
input clk;
output [3:0] an;

reg [3:0] an;
reg [31:0] counter0 = 0;
reg [31:0] counter1 = 0;

parameter refresh_ms = 16;
parameter num_digits = 4;
parameter rate = refresh_ms * 100000;


always @(posedge (clk)) begin
    counter0 = counter0 + 1;
    if (counter0 >= (rate / num_digits)) begin    
        counter0 = 0;
        counter1 = counter1 + 1;
    end 
    if (counter1 >= (num_digits)) counter1 = 0;
end


always @(posedge(clk)) begin
    if (counter1 == 0) an = 4'b0111;
    else if (counter1 == 1) an = 4'b1011;
    else if (counter1 == 2) an = 4'b1101;
    else if (counter1 == 3) an = 4'b1110;
    else an <= 4'b1111;
end
endmodule
module dig_cont(clk, an);

input clk;
output [3:0] an;

reg [3:0] an;
reg [31:0] counter0 = 0;
reg [31:0] counter1 = 0;

parameter refresh_ms = 16;
parameter num_digits = 4;
parameter rate = refresh_ms * 100000;


always @(posedge (clk)) begin
    counter0 = counter0 + 1;
    if (counter0 >= (rate / num_digits)) begin    
        counter0 = 0;
        counter1 = counter1 + 1;
    end 
    if (counter1 >= (num_digits)) counter1 = 0;
end


always @(posedge(clk)) begin
    if (counter1 == 0) an = 4'b0111;
    else if (counter1 == 1) an = 4'b1011;
    else if (counter1 == 2) an = 4'b1101;
    else if (counter1 == 3) an = 4'b1110;
    else an <= 4'b1111;
end
endmodule