data/full_repos/permissive/427221126/workspace/mult_booth.sv
data/verilator_xmls/8c0f0c4b-8478-4475-9fde-3cb583000ab9.xml
module gen_prod (
	input [15:0] A_com,
	input neg,
	input zero,
	input one,
	input two,
	output [31:0] prod
);

reg [31:0] prod_pre;

always @ (*) begin
	prod_pre = 32'd0;
	if (zero)
		prod_pre = 32'd0; 
	else if (one)
		prod_pre = { { 16{A_com[15]} }, A_com};
	else if (two)
		prod_pre = { { 15{A_com[15]} }, A_com, 1'b0};
end

assign prod = neg ? ( ~prod_pre+1'b1 ) : prod_pre;
		
endmodule
module gen_prod (
	input [15:0] A_com,
	input neg,
	input zero,
	input one,
	input two,
	output [31:0] prod
);


reg [31:0] prod_pre;

always @ (*) begin
	prod_pre = 32'd0;
	if (zero)
		prod_pre = 32'd0; 
	else if (one)
		prod_pre = { { 16{A_com[15]} }, A_com};
	else if (two)
		prod_pre = { { 15{A_com[15]} }, A_com, 1'b0};
end

assign prod = neg ? ( ~prod_pre+1'b1 ) : prod_pre;
		
endmodule