data/full_repos/permissive/412297935/hdl/aperture.v
1: b'%Error: data/full_repos/permissive/412297935/hdl/aperture.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/412297935/hdl,data/full_repos/permissive/412297935/defines.v\n             data/full_repos/permissive/412297935/hdl,data/full_repos/permissive/412297935/defines.v.v\n             data/full_repos/permissive/412297935/hdl,data/full_repos/permissive/412297935/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/412297935/hdl/aperture.v:51: Define or directive not defined: \'`CFG_PAGE\'\n assign cfgMatch = (a8_addr[7:4] == index) & (a8_addr[15:8] == `CFG_PAGE);\n                                                               ^~~~~~~~~\n%Error: data/full_repos/permissive/412297935/hdl/aperture.v:51: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n assign cfgMatch = (a8_addr[7:4] == index) & (a8_addr[15:8] == `CFG_PAGE);\n                                                                        ^\n%Error: Exiting due to 3 error(s)\n'
module Aperture
	(
    input	wire			clk,
	input	wire			a8_rst_n,
	input	wire			a8_rw_n,
	input 	wire [7:0]		a8_data,
	input	wire [15:0]		a8_addr,
	input	wire [3:0]		index,
	input	wire			aValid,
	input 	wire			wValid,
	
	output 	wire			inRange,
	output 	reg [7:0]		apCfg,
	output 	reg 			apCfgValid,
	output	wire [31:0]		baseAddr
	);




    reg		[31:0]		sramAddr;
	reg		[7:0]		lo;
	reg		[7:0]		hi;
	reg		[7:0]		stride;




	wire loMatch 		= (lo <= a8_addr[15:8]);
	wire hiMatch		= (hi >= a8_addr[15:8]);
	assign inRange		= loMatch & hiMatch & aValid;





	assign cfgMatch	= (a8_addr[7:4] == index) & (a8_addr[15:8] == `CFG_PAGE);




	assign baseAddr		= sramAddr;
	
	always @ (posedge clk)
		if (a8_rst_n == 1'b0)
			begin
				sramAddr		<= 32'b0;
				lo				<= 8'b0;
				hi				<= 8'b0;
				apCfgValid		<= 1'b0;
				apCfg			<= 8'hff;
			end
			
		else if (a8_rw_n == 1'b0)
			begin



				if (wValid && cfgMatch)
					case (a8_addr[3:0])
						4'h0:		sramAddr[31:24] <= a8_data;
						4'h1:		sramAddr[23:16]	<= a8_data;
						4'h2:		sramAddr[15:8]	<= a8_data;
						4'h3:		sramAddr[7:0]	<= a8_data;
						4'h4:		lo 				<= a8_data;
						4'h5:		hi				<= a8_data;
						4'h6:		stride			<= a8_data;
						default:	lo				<= lo;
					endcase
			end
		else
			begin



				if (aValid && cfgMatch)
					begin
						case (a8_addr[3:0])
							4'h0:		apCfg <= 	sramAddr[31:24];
							4'h1:		apCfg <= 	sramAddr[23:16];
							4'h2:		apCfg <= 	sramAddr[15:8];
							4'h3:		apCfg <= 	sramAddr[7:0];
							4'h4:		apCfg <= 	lo;
							4'h5:		apCfg <= 	hi;
							4'h6:		apCfg <= 	stride;
							default:	apCfg <=	8'hff;
						endcase
						apCfgValid 			  <= 1'b1;
					end
				else
					apCfgValid <= 1'b0;
			end

			
endmodule
module Aperture
	(
    input	wire			clk,
	input	wire			a8_rst_n,
	input	wire			a8_rw_n,
	input 	wire [7:0]		a8_data,
	input	wire [15:0]		a8_addr,
	input	wire [3:0]		index,
	input	wire			aValid,
	input 	wire			wValid,
	
	output 	wire			inRange,
	output 	reg [7:0]		apCfg,
	output 	reg 			apCfgValid,
	output	wire [31:0]		baseAddr
	);





    reg		[31:0]		sramAddr;
	reg		[7:0]		lo;
	reg		[7:0]		hi;
	reg		[7:0]		stride;




	wire loMatch 		= (lo <= a8_addr[15:8]);
	wire hiMatch		= (hi >= a8_addr[15:8]);
	assign inRange		= loMatch & hiMatch & aValid;





	assign cfgMatch	= (a8_addr[7:4] == index) & (a8_addr[15:8] == `CFG_PAGE);




	assign baseAddr		= sramAddr;
	
	always @ (posedge clk)
		if (a8_rst_n == 1'b0)
			begin
				sramAddr		<= 32'b0;
				lo				<= 8'b0;
				hi				<= 8'b0;
				apCfgValid		<= 1'b0;
				apCfg			<= 8'hff;
			end
			
		else if (a8_rw_n == 1'b0)
			begin



				if (wValid && cfgMatch)
					case (a8_addr[3:0])
						4'h0:		sramAddr[31:24] <= a8_data;
						4'h1:		sramAddr[23:16]	<= a8_data;
						4'h2:		sramAddr[15:8]	<= a8_data;
						4'h3:		sramAddr[7:0]	<= a8_data;
						4'h4:		lo 				<= a8_data;
						4'h5:		hi				<= a8_data;
						4'h6:		stride			<= a8_data;
						default:	lo				<= lo;
					endcase
			end
		else
			begin



				if (aValid && cfgMatch)
					begin
						case (a8_addr[3:0])
							4'h0:		apCfg <= 	sramAddr[31:24];
							4'h1:		apCfg <= 	sramAddr[23:16];
							4'h2:		apCfg <= 	sramAddr[15:8];
							4'h3:		apCfg <= 	sramAddr[7:0];
							4'h4:		apCfg <= 	lo;
							4'h5:		apCfg <= 	hi;
							4'h6:		apCfg <= 	stride;
							default:	apCfg <=	8'hff;
						endcase
						apCfgValid 			  <= 1'b1;
					end
				else
					apCfgValid <= 1'b0;
			end

			
endmodule