data/full_repos/permissive/441359809/src/yosys/manual/CHAPTER_StateOfTheArt/always02_pub.v
data/verilator_xmls/0db8e187-1b92-4fa9-b318-e9ce14467a67.xml
module uut_always02(clock,
		reset, count);

input clock, reset;
output [3:0] count;
reg [3:0] count;

always @(posedge clock) begin
	count <= count + 1;
	if (reset)
		count <= 0;
end

endmodule
module uut_always02(clock,
		reset, count);


input clock, reset;
output [3:0] count;
reg [3:0] count;

always @(posedge clock) begin
	count <= count + 1;
	if (reset)
		count <= 0;
end

endmodule