data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:41: Cannot find include file: iop.h\n`include "iop.h" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/iop.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/iop.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/iop.h.sv\n             iop.h\n             iop.h.v\n             iop.h.sv\n             obj_dir/iop.h\n             obj_dir/iop.h.v\n             obj_dir/iop.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:42: Cannot find include file: ifu.h\n`include "ifu.h" \n         ^~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:82: Define or directive not defined: \'`CPX_WIDTH\'\n   input [`CPX_WIDTH-1:0] lsu_ifu_cpxpkt_i1;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:134: Define or directive not defined: \'`CPX_WIDTH\'\n   output [`CPX_WIDTH-1:0] ifd_inv_ifqop_i2;\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:136: Define or directive not defined: \'`IC_IDX_HI\'\n   output [`IC_IDX_HI:2]  ifq_icd_index_bf;    \n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:136: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   output [`IC_IDX_HI:2]  ifq_icd_index_bf;    \n                     ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:139: Define or directive not defined: \'`IC_TAG_SZ\'\n   output [`IC_TAG_SZ:0]  ifq_ict_wrtag_f;       \n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:139: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   output [`IC_TAG_SZ:0]  ifq_ict_wrtag_f;       \n                     ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:141: Define or directive not defined: \'`IC_IDX_HI\'\n   output [`IC_IDX_HI:4]   ifq_erb_wrindex_f;\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:141: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   output [`IC_IDX_HI:4]   ifq_erb_wrindex_f;\n                     ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:154: Define or directive not defined: \'`CPX_RQ_SIZE\'\n   output [`CPX_RQ_SIZE:0] ifd_ifc_cpxreq_i1;     \n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:154: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   output [`CPX_RQ_SIZE:0] ifd_ifc_cpxreq_i1;     \n                       ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:219: Define or directive not defined: \'`CPX_WIDTH\'\n   wire [`CPX_WIDTH-1:0]   inq_cpxpkt_i1,    \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:297: Define or directive not defined: \'`ICT_FILL_BITS\'\n   sparc_ifu_par32 tag_par(.in  ({{`ICT_FILL_BITS{1\'b0}}, \n                                   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:298: Define or directive not defined: \'`IC_TAG_HI\'\n                                  imiss_paddr_s[`IC_TAG_HI:`IC_TAG_LO]}),\n                                                ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:298: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n                                  imiss_paddr_s[`IC_TAG_HI:`IC_TAG_LO]}),\n                                                          ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:298: Define or directive not defined: \'`IC_TAG_LO\'\n                                  imiss_paddr_s[`IC_TAG_HI:`IC_TAG_LO]}),\n                                                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:414: Define or directive not defined: \'`BANK_ID_HI\'\n                              imiss_paddr_s[`BANK_ID_HI:`BANK_ID_LO]};\n                                            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:414: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n                              imiss_paddr_s[`BANK_ID_HI:`BANK_ID_LO]};\n                                                       ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:414: Define or directive not defined: \'`BANK_ID_LO\'\n                              imiss_paddr_s[`BANK_ID_HI:`BANK_ID_LO]};\n                                                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:416: Define or directive not defined: \'`BANK_ID_HI\'\n                           mil_entry0[`BANK_ID_HI:`BANK_ID_LO]};\n                                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:416: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n                           mil_entry0[`BANK_ID_HI:`BANK_ID_LO]};\n                                                 ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:416: Define or directive not defined: \'`BANK_ID_LO\'\n                           mil_entry0[`BANK_ID_HI:`BANK_ID_LO]};\n                                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:418: Define or directive not defined: \'`BANK_ID_HI\'\n                           mil_entry1[`BANK_ID_HI:`BANK_ID_LO]};\n                                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:418: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n                           mil_entry1[`BANK_ID_HI:`BANK_ID_LO]};\n                                                 ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:418: Define or directive not defined: \'`BANK_ID_LO\'\n                           mil_entry1[`BANK_ID_HI:`BANK_ID_LO]};\n                                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:420: Define or directive not defined: \'`BANK_ID_HI\'\n                           mil_entry2[`BANK_ID_HI:`BANK_ID_LO]};\n                                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:420: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n                           mil_entry2[`BANK_ID_HI:`BANK_ID_LO]};\n                                                 ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:420: Define or directive not defined: \'`BANK_ID_LO\'\n                           mil_entry2[`BANK_ID_HI:`BANK_ID_LO]};\n                                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:422: Define or directive not defined: \'`BANK_ID_HI\'\n                           mil_entry3[`BANK_ID_HI:`BANK_ID_LO]};\n                                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:422: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n                           mil_entry3[`BANK_ID_HI:`BANK_ID_LO]};\n                                                 ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:422: Define or directive not defined: \'`BANK_ID_LO\'\n                           mil_entry3[`BANK_ID_HI:`BANK_ID_LO]};\n                                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:475: Define or directive not defined: \'`IMISS_RQ\'\n                             {`IMISS_RQ},           \n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:475: Unsupported: empty queues ("{ }")\n                             {`IMISS_RQ},           \n                             ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:536: Define or directive not defined: \'`IC_IDX_HI\'\n   assign  ifq_erb_wrindex_f = wraddr_f[`IC_IDX_HI:4];\n                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:536: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   assign  ifq_erb_wrindex_f = wraddr_f[`IC_IDX_HI:4];\n                                                  ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:537: Define or directive not defined: \'`IC_TAG_HI\'\n   assign  ifq_ict_wrtag_f = {wraddr_f[42], wraddr_f[`IC_TAG_HI:`IC_TAG_LO]};\n                                                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:537: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   assign  ifq_ict_wrtag_f = {wraddr_f[42], wraddr_f[`IC_TAG_HI:`IC_TAG_LO]};\n                                                               ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:537: Define or directive not defined: \'`IC_TAG_LO\'\n   assign  ifq_ict_wrtag_f = {wraddr_f[42], wraddr_f[`IC_TAG_HI:`IC_TAG_LO]};\n                                                                ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:539: Define or directive not defined: \'`IC_IDX_HI\'\n   assign  ifq_icd_index_bf = icaddr_i2[`IC_IDX_HI:2];\n                                        ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:539: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n   assign  ifq_icd_index_bf = icaddr_i2[`IC_IDX_HI:2];\n                                                  ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:570: Define or directive not defined: \'`CPX_WIDTH\'\n   dff_s #(`CPX_WIDTH) ibuf(.din (lsu_ifu_cpxpkt_i1),\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:576: Define or directive not defined: \'`CPX_VLD\'\n   assign  ifd_ifc_cpxreq_i1 = {inq_cpxpkt_i1[`CPX_VLD], \n                                              ^~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:576: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   assign  ifd_ifc_cpxreq_i1 = {inq_cpxpkt_i1[`CPX_VLD], \n                                                      ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:577: Define or directive not defined: \'`CPX_REQFIELD\'\n                             inq_cpxpkt_i1[`CPX_REQFIELD]};\n                                           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:581: Define or directive not defined: \'`CPX_WIDTH\'\n   dp_mux4ds  #(`CPX_WIDTH)  ifq_bypmux(.dout (ifqop_i1),\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:606: Define or directive not defined: \'`CPX_WIDTH\'\n   dff_s #(`CPX_WIDTH)  ifqop_reg(.din (ifqop_i1), \n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:652: Define or directive not defined: \'`CPX_REQFIELD\'\n   assign ifd_ifc_cpxreq_nxt   = ifqop_i1[`CPX_REQFIELD];\n                                          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:652: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   assign ifd_ifc_cpxreq_nxt   = ifqop_i1[`CPX_REQFIELD];\n                                                       ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_ifqdp.v:653: Define or directive not defined: \'`CPX_THRFIELD\'\n   assign ifd_ifc_cpxthr_nxt   = ifqop_i1[`CPX_THRFIELD];\n                                          ^~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module sparc_ifu_ifqdp(

   so, ifu_lsu_pcxpkt_e, ifq_fdp_fill_inst, ifq_erb_asidata_i2, 
   ifd_inv_ifqop_i2, ifq_icd_index_bf, ifq_icd_wrdata_i2, 
   ifq_ict_wrtag_f, ifq_erb_wrindex_f, ifq_icd_wrway_bf, 
   ifd_ifc_milhit_s, ifd_ifc_instoffset0, ifd_ifc_instoffset1, 
   ifd_ifc_instoffset2, ifd_ifc_instoffset3, ifd_ifc_cpxthr_nxt, 
   ifd_ifc_cpxreq_nxt, ifd_ifc_cpxreq_i1, ifd_ifc_destid0, 
   ifd_ifc_destid1, ifd_ifc_destid2, ifd_ifc_destid3, 
   ifd_ifc_newdestid_s, ifd_ifc_pcxline_d, ifd_ifc_asi_vachklo_i2, 
   ifd_ifc_cpxvld_i2, ifd_ifc_asiaddr_i2, ifd_ifc_iobpkt_i2, 
   ifd_ifc_fwd2ic_i2, ifd_ifc_4bpkt_i2, ifd_ifc_cpxnc_i2, 
   ifd_ifc_cpxce_i2, ifd_ifc_cpxue_i2, ifd_ifc_cpxms_i2, 
   ifd_ifc_miladdr4_i2, ifd_inv_wrway_i2, 

   rclk, se, si, lsu_ifu_cpxpkt_i1, lsu_ifu_asi_addr, 
   lsu_ifu_stxa_data, itlb_ifq_paddr_s, fdp_ifq_paddr_f, 
   ifc_ifd_reqvalid_e, ifc_ifd_filladdr4_i2, ifc_ifd_repway_s, 
   ifc_ifd_uncached_e, ifc_ifd_thrid_e, ifc_ifd_pcxline_adj_d, 
   ifc_ifd_errinv_e, ifc_ifd_ldmil_sel_new, ifc_ifd_ld_inq_i1, 
   ifc_ifd_idx_sel_fwd_i2, ifc_ifd_milreq_sel_d_l, 
   ifc_ifd_milfill_sel_i2_l, ifc_ifd_finst_sel_l, 
   ifc_ifd_ifqbyp_sel_fwd_l, ifc_ifd_ifqbyp_sel_inq_l, 
   ifc_ifd_ifqbyp_sel_asi_l, ifc_ifd_ifqbyp_sel_lsu_l, 
   ifc_ifd_ifqbyp_en_l, ifc_ifd_addr_sel_bist_i2_l, 
   ifc_ifd_addr_sel_asi_i2_l, ifc_ifd_addr_sel_old_i2_l, 
   ifc_ifd_addr_sel_fill_i2_l, mbist_icache_way, mbist_icache_word, 
   mbist_icache_index
   );

   input 	 rclk, 
           se, 
           si;
   
   input [`CPX_WIDTH-1:0] lsu_ifu_cpxpkt_i1;
   input [17:0]   lsu_ifu_asi_addr;
   input [47:0]   lsu_ifu_stxa_data;
   
   input [39:10]  itlb_ifq_paddr_s;
   input [9:2]    fdp_ifq_paddr_f;
   

   input         ifc_ifd_reqvalid_e;
   input         ifc_ifd_filladdr4_i2;
   input [1:0]   ifc_ifd_repway_s;
   input         ifc_ifd_uncached_e;
   input [1:0]   ifc_ifd_thrid_e;
   input [4:2]   ifc_ifd_pcxline_adj_d;
   
   input         ifc_ifd_errinv_e;
   

   input [3:0]   ifc_ifd_ldmil_sel_new;
   
   input        ifc_ifd_ld_inq_i1;
   input        ifc_ifd_idx_sel_fwd_i2;
   

   input [3:0]  ifc_ifd_milreq_sel_d_l,
		            ifc_ifd_milfill_sel_i2_l;


   input [3:0]  ifc_ifd_finst_sel_l;

   input        ifc_ifd_ifqbyp_sel_fwd_l,
		            ifc_ifd_ifqbyp_sel_inq_l,
		            ifc_ifd_ifqbyp_sel_asi_l,
		            ifc_ifd_ifqbyp_sel_lsu_l;
	 input        ifc_ifd_ifqbyp_en_l;   

   input        ifc_ifd_addr_sel_bist_i2_l,
		            ifc_ifd_addr_sel_asi_i2_l,
                ifc_ifd_addr_sel_old_i2_l,
		            ifc_ifd_addr_sel_fill_i2_l;
   
   input [1:0]  mbist_icache_way;
   input        mbist_icache_word;
   input [7:0]  mbist_icache_index;
   
   output       so;
   
   output [51:0] ifu_lsu_pcxpkt_e;

   output [32:0] ifq_fdp_fill_inst;
   output [47:0] ifq_erb_asidata_i2;

   output [`CPX_WIDTH-1:0] ifd_inv_ifqop_i2;

   output [`IC_IDX_HI:2]  ifq_icd_index_bf;
   
   output [135:0]         ifq_icd_wrdata_i2;
   output [`IC_TAG_SZ:0]  ifq_ict_wrtag_f;

   output [`IC_IDX_HI:4]   ifq_erb_wrindex_f;
   output [1:0]            ifq_icd_wrway_bf;
   
   output [3:0]           ifd_ifc_milhit_s;

   
   output [1:0]           ifd_ifc_instoffset0;
   output [1:0]           ifd_ifc_instoffset1;
   output [1:0]           ifd_ifc_instoffset2;
   output [1:0]           ifd_ifc_instoffset3;

   output [1:0]            ifd_ifc_cpxthr_nxt;
   output [3:0]            ifd_ifc_cpxreq_nxt;
   output [`CPX_RQ_SIZE:0] ifd_ifc_cpxreq_i1;

   
   output [2:0]            ifd_ifc_destid0,
		                       ifd_ifc_destid1,
		                       ifd_ifc_destid2,
		                       ifd_ifc_destid3,
		                       ifd_ifc_newdestid_s;

   output [4:2]            ifd_ifc_pcxline_d;

   output                  ifd_ifc_asi_vachklo_i2;
                         
   output                  ifd_ifc_cpxvld_i2;
   output [3:2]            ifd_ifc_asiaddr_i2;   
   output                  ifd_ifc_iobpkt_i2;
   output                  ifd_ifc_fwd2ic_i2;
   output                  ifd_ifc_4bpkt_i2;
   output                  ifd_ifc_cpxnc_i2;
   output                  ifd_ifc_cpxce_i2,
		                       ifd_ifc_cpxue_i2,
                           ifd_ifc_cpxms_i2;
   
   output [3:0]            ifd_ifc_miladdr4_i2;
   
   output [1:0]            ifd_inv_wrway_i2;

   
 	 





   wire [39:0]             imiss_paddr_s;
   wire [9:2]              lcl_paddr_s;
   
   wire [42:2]             mil_entry0,
		                       mil_entry1,
		                       mil_entry2,
		                       mil_entry3;






   wire                    tag_par_s,
		                       tag_par_i2;

   wire [42:2]             newmil_entry_s;
   
   wire [42:2]             mil_pcxreq_d,
		                       pcxreq_d,
		                       pcxreq_e;

   wire [42:2]             fill_addr_i2,
		                       fill_addr_adj,
		                       icaddr_i2,
		                       asi_addr_i2,
		                       bist_addr_i2;

   wire [42:4]             wraddr_f;


   wire [`CPX_WIDTH-1:0]   inq_cpxpkt_i1,

			                     stxa_data_pkt,
                           fwd_data_pkt,
			                     ifqop_i1,
			                     ifqop_i2;

   wire [3:0]              swc_i2;
   
   wire [135:0]            icdata_i2;
   
   wire [3:0]              parity_i2,
		                       par_i2;

   wire [17:0]             asi_va_i2,
                           asi_va_i1;
   wire [13:2]             asi_fwd_index;
   wire                    clk;
   
   

   




   assign                  clk = rclk;
   





   dff_s #(8) pcs_reg(.din (fdp_ifq_paddr_f[9:2]),
                    .q   (lcl_paddr_s[9:2]),
                    .clk (clk), .se(se), .si(), .so());
                    


   assign  imiss_paddr_s = {itlb_ifq_paddr_s[39:10], 
                            lcl_paddr_s[9:2],
                            2'b0};
   




   sparc_ifu_cmp35 milcmp0 (.hit (ifd_ifc_milhit_s[0]),
			                      .a (imiss_paddr_s[39:5]),
			                      .b (mil_entry0[39:5]),
			                      .valid (1'b1)
			                      );
   
   sparc_ifu_cmp35 milcmp1 (.hit (ifd_ifc_milhit_s[1]),
			                      .a (imiss_paddr_s[39:5]),
			                      .b (mil_entry1[39:5]),
			                      .valid (1'b1)
			                      );
   
   sparc_ifu_cmp35 milcmp2 (.hit (ifd_ifc_milhit_s[2]),
			                      .a (imiss_paddr_s[39:5]),
			                      .b (mil_entry2[39:5]),
			                      .valid (1'b1)
			                      );
   sparc_ifu_cmp35 milcmp3 (.hit (ifd_ifc_milhit_s[3]),
			                      .a (imiss_paddr_s[39:5]),
			                      .b (mil_entry3[39:5]),
			                      .valid (1'b1)
			                      );









   sparc_ifu_par32 tag_par(.in  ({{`ICT_FILL_BITS{1'b0}}, 
                                  imiss_paddr_s[`IC_TAG_HI:`IC_TAG_LO]}),
			                     .out (tag_par_s));









   assign  newmil_entry_s = {tag_par_s,
			                       ifc_ifd_repway_s,			    
			                       imiss_paddr_s[39:2]};



















   wire    clk_mil0;
`ifdef FPGA_SYN_CLK_EN
`else
   bw_u1_ckenbuf_6x  ckenmil0(.rclk (rclk),
                              .clk  (clk_mil0),
                              .en_l (~ifc_ifd_ldmil_sel_new[0]),
                              .tm_l (~se));
`endif
   wire    clk_mil1;
`ifdef FPGA_SYN_CLK_EN
`else
   bw_u1_ckenbuf_6x  ckenmil1(.rclk (rclk),
                              .clk  (clk_mil1),
                              .en_l (~ifc_ifd_ldmil_sel_new[1]),
                              .tm_l (~se));
`endif
   wire    clk_mil2;
`ifdef FPGA_SYN_CLK_EN
`else
   bw_u1_ckenbuf_6x  ckenmil2(.rclk (rclk),
                              .clk  (clk_mil2),
                              .en_l (~ifc_ifd_ldmil_sel_new[2]),
                              .tm_l (~se));
`endif
   wire    clk_mil3;
`ifdef FPGA_SYN_CLK_EN
`else
   bw_u1_ckenbuf_6x  ckenmil3(.rclk (rclk),
                              .clk  (clk_mil3),
                              .en_l (~ifc_ifd_ldmil_sel_new[3]),
                              .tm_l (~se));
`endif
   

`ifdef FPGA_SYN_CLK_DFF
   dffe_s #(41)   mil0(.din  (newmil_entry_s), 
		                .en (~(~ifc_ifd_ldmil_sel_new[0])), .clk(rclk), 
		                .q    (mil_entry0), 
		                .se   (se), .si(), .so());
`else
   dff_s #(41)   mil0(.din  (newmil_entry_s), 
		                .clk  (clk_mil0), 
		                .q    (mil_entry0), 
		                .se   (se), .si(), .so());
`endif

`ifdef FPGA_SYN_CLK_DFF
   dffe_s #(41)   mil1(.din (newmil_entry_s), 
		                .en (~(~ifc_ifd_ldmil_sel_new[1])), .clk(rclk), 
		                .q   (mil_entry1), 
		                .se  (se), .si(), .so());
`else
   dff_s #(41)   mil1(.din (newmil_entry_s), 
		                .clk (clk_mil1), 
		                .q   (mil_entry1), 
		                .se  (se), .si(), .so());
`endif

`ifdef FPGA_SYN_CLK_DFF
   dffe_s #(41)   mil2(.din (newmil_entry_s), 
		                .en (~(~ifc_ifd_ldmil_sel_new[2])), .clk(rclk), 
		                .q   (mil_entry2), 
		                .se  (se), .si(), .so());
`else
   dff_s #(41)   mil2(.din (newmil_entry_s), 
		                .clk (clk_mil2), 
		                .q   (mil_entry2), 
		                .se  (se), .si(), .so());
`endif

`ifdef FPGA_SYN_CLK_DFF
   dffe_s #(41)   mil3(.din (newmil_entry_s), 
		                .en (~(~ifc_ifd_ldmil_sel_new[3])), .clk(rclk), 
		                .q   (mil_entry3), 
		                .se  (se), .si(), .so());
`else
   dff_s #(41)   mil3(.din (newmil_entry_s), 
		                .clk (clk_mil3), 
		                .q   (mil_entry3), 
		                .se  (se), .si(), .so());
`endif

   assign  ifd_ifc_newdestid_s = {imiss_paddr_s[39], 
				                          imiss_paddr_s[`BANK_ID_HI:`BANK_ID_LO]};
   assign  ifd_ifc_destid0 = {mil_entry0[39], 
			                        mil_entry0[`BANK_ID_HI:`BANK_ID_LO]};
   assign  ifd_ifc_destid1 = {mil_entry1[39], 
			                        mil_entry1[`BANK_ID_HI:`BANK_ID_LO]};
   assign  ifd_ifc_destid2 = {mil_entry2[39], 
			                        mil_entry2[`BANK_ID_HI:`BANK_ID_LO]};
   assign  ifd_ifc_destid3 = {mil_entry3[39], 
			                        mil_entry3[`BANK_ID_HI:`BANK_ID_LO]};

   assign  ifd_ifc_instoffset0 = mil_entry0[3:2];
   assign  ifd_ifc_instoffset1 = mil_entry1[3:2];
   assign  ifd_ifc_instoffset2 = mil_entry2[3:2];
   assign  ifd_ifc_instoffset3 = mil_entry3[3:2];
   
   

   dp_mux4ds  #(41)  milreq_mux (.dout (mil_pcxreq_d),
			                         .in0  ({mil_entry0[42:2]}),
			                         .in1  ({mil_entry1[42:2]}),
			                         .in2  ({mil_entry2[42:2]}),
			                         .in3  ({mil_entry3[42:2]}),
			                         .sel0_l  (ifc_ifd_milreq_sel_d_l[0]),
			                         .sel1_l  (ifc_ifd_milreq_sel_d_l[1]),
			                         .sel2_l  (ifc_ifd_milreq_sel_d_l[2]),
			                         .sel3_l  (ifc_ifd_milreq_sel_d_l[3]));
   












   assign  ifd_ifc_pcxline_d[4:2] = mil_pcxreq_d[4:2];
   
   assign  pcxreq_d[42:5] = mil_pcxreq_d[42:5];
   assign  pcxreq_d[4:2] = ifc_ifd_pcxline_adj_d[4:2];


   dff_s #(41) pcxreq_reg (.din  (pcxreq_d),
			                    .clk  (clk),
			                    .q    (pcxreq_e),
			                    .se   (se), .si(), .so());







   

   assign   ifu_lsu_pcxpkt_e = {ifc_ifd_reqvalid_e,
			                          ifc_ifd_errinv_e,
                                ifc_ifd_uncached_e,
			                          {`IMISS_RQ},
			                          pcxreq_e[41:40],
			                          ifc_ifd_thrid_e[1:0],
			                          pcxreq_e[39:2],
			                          2'b0};
   






   dp_mux4ds  #(41)  milfill_mux(.dout (fill_addr_i2),
			                         .in0 ( mil_entry0),
			                         .in1 ( mil_entry1),
			                         .in2 ( mil_entry2),
			                         .in3 ( mil_entry3),
			                         .sel0_l (ifc_ifd_milfill_sel_i2_l[0]),
			                         .sel1_l (ifc_ifd_milfill_sel_i2_l[1]),
			                         .sel2_l (ifc_ifd_milfill_sel_i2_l[2]),
			                         .sel3_l (ifc_ifd_milfill_sel_i2_l[3]));

   assign   ifd_ifc_miladdr4_i2[3:0]  = {mil_entry3[4],
                                         mil_entry2[4],
                                         mil_entry1[4],
                                         mil_entry0[4]};
   
   assign   ifd_ifc_iobpkt_i2 = fill_addr_i2[39];
   assign   fill_addr_adj = {fill_addr_i2[42:5], 
			                       ifc_ifd_filladdr4_i2,
			                       fill_addr_i2[3:2]};





   dp_mux4ds #(41) icadr_mux(.dout (icaddr_i2),
			                       .in0  (fill_addr_adj),
			                       .in1  (asi_addr_i2),
			                       .in2  (bist_addr_i2),
                             .in3  ({wraddr_f[42:4], 2'b0}),
			                       .sel0_l (ifc_ifd_addr_sel_fill_i2_l),
			                       .sel1_l (ifc_ifd_addr_sel_asi_i2_l),
			                       .sel2_l (ifc_ifd_addr_sel_bist_i2_l),
                             .sel3_l (ifc_ifd_addr_sel_old_i2_l));
   

   assign ifd_inv_wrway_i2 =  icaddr_i2[41:40];






   
   dff_s #(39) wraddr_reg(.din  (icaddr_i2[42:4]),
		                    .clk  (clk),
		                    .q    (wraddr_f[42:4]),
		                    .se   (se), .si(), .so());


   assign  ifq_erb_wrindex_f = wraddr_f[`IC_IDX_HI:4];
   assign  ifq_ict_wrtag_f = {wraddr_f[42], wraddr_f[`IC_TAG_HI:`IC_TAG_LO]};

   assign  ifq_icd_index_bf = icaddr_i2[`IC_IDX_HI:2];
   assign  ifq_icd_wrway_bf = icaddr_i2[41:40];














   wire    clk_ibuf1;
`ifdef FPGA_SYN_CLK_EN
`else
   bw_u1_ckenbuf_6x  ckenibuf(.rclk (rclk),
                              .clk  (clk_ibuf1),
                              .en_l (~ifc_ifd_ld_inq_i1),
                              .tm_l (~se));
`endif
                             
`ifdef FPGA_SYN_CLK_DFF
   dffe_s #(`CPX_WIDTH) ibuf(.din (lsu_ifu_cpxpkt_i1),
			                  .q   (inq_cpxpkt_i1),
			                  .en (~(~ifc_ifd_ld_inq_i1)), .clk(rclk),
			                  .se  (se), .si(), .so());
`else
   dff_s #(`CPX_WIDTH) ibuf(.din (lsu_ifu_cpxpkt_i1),
			                  .q   (inq_cpxpkt_i1),
			                  .clk (clk_ibuf1),
			                  .se  (se), .si(), .so());
`endif

   assign  ifd_ifc_cpxreq_i1 = {inq_cpxpkt_i1[`CPX_VLD], 
			                          inq_cpxpkt_i1[`CPX_REQFIELD]};



   dp_mux4ds  #(`CPX_WIDTH)  ifq_bypmux(.dout (ifqop_i1),
				                              .in0 (fwd_data_pkt), 
				                              .in1 (inq_cpxpkt_i1),
				                              .in2 (stxa_data_pkt),
				                              .in3 (lsu_ifu_cpxpkt_i1),
				                              .sel0_l (ifc_ifd_ifqbyp_sel_fwd_l),
				                              .sel1_l (ifc_ifd_ifqbyp_sel_inq_l),
				                              .sel2_l (ifc_ifd_ifqbyp_sel_asi_l),
				                              .sel3_l (ifc_ifd_ifqbyp_sel_lsu_l));
   
   wire    clk_ifqop;
`ifdef FPGA_SYN_CLK_EN
`else
   bw_u1_ckenbuf_6x  ckenifop(.rclk (rclk),
                              .clk  (clk_ifqop),
                              .en_l (ifc_ifd_ifqbyp_en_l),
                              .tm_l (~se));
`endif
   
`ifdef FPGA_SYN_CLK_DFF
   dffe_s #(`CPX_WIDTH)  ifqop_reg(.din (ifqop_i1), 
			                        .q   (ifqop_i2), 
			                        .en (~(ifc_ifd_ifqbyp_en_l)), .clk(rclk), 
			                        .se  (se), .si(), .so());
`else
   dff_s #(`CPX_WIDTH)  ifqop_reg(.din (ifqop_i1), 
			                        .q   (ifqop_i2), 
			                        .clk (clk_ifqop), 
			                        .se  (se), .si(), .so());
`endif
   assign  ifd_inv_ifqop_i2 = ifqop_i2;
   

   sparc_ifu_swpla  swpla0(.in  (ifqop_i2[31:0]),
			                     .out (swc_i2[0]));
   sparc_ifu_swpla  swpla1(.in  (ifqop_i2[63:32]),
			                     .out (swc_i2[1]));
   sparc_ifu_swpla  swpla2(.in  (ifqop_i2[95:64]),
			                     .out (swc_i2[2]));
   sparc_ifu_swpla  swpla3(.in  (ifqop_i2[127:96]),
			                     .out (swc_i2[3]));


   sparc_ifu_par32 par0(.in  (ifqop_i2[31:0]),
			                  .out (par_i2[0]));
   sparc_ifu_par32 par1(.in  (ifqop_i2[63:32]),
			                  .out (par_i2[1]));
   sparc_ifu_par32 par2(.in  (ifqop_i2[95:64]),
			                  .out (par_i2[2]));
   sparc_ifu_par32 par3(.in  (ifqop_i2[127:96]),
			                  .out (par_i2[3]));






   assign   parity_i2 = par_i2 ^ swc_i2 ^ {4{ifd_ifc_cpxue_i2}};
   assign   tag_par_i2 = par_i2[0] ^ ifd_ifc_cpxue_i2;
   

   assign   icdata_i2 = {parity_i2[3], ifqop_i2[127:96], swc_i2[3],
		                     parity_i2[2], ifqop_i2[95:64],  swc_i2[2],
		                     parity_i2[1], ifqop_i2[63:32],  swc_i2[1],
		                     parity_i2[0], ifqop_i2[31:0],   swc_i2[0]};


   assign ifq_icd_wrdata_i2 = icdata_i2;



   assign ifd_ifc_cpxreq_nxt   = ifqop_i1[`CPX_REQFIELD];
   assign ifd_ifc_cpxthr_nxt   = ifqop_i1[`CPX_THRFIELD];

   assign ifd_ifc_cpxvld_i2   = ifqop_i2[`CPX_VLD];
   assign ifd_ifc_4bpkt_i2    = ifqop_i2[`CPX_IF4B];
   assign ifd_ifc_cpxce_i2    = ifqop_i2[`CPX_ERR_LO];
   assign ifd_ifc_cpxue_i2    = ifqop_i2[(`CPX_ERR_LO + 1)];
   assign ifd_ifc_cpxms_i2    = ifqop_i2[(`CPX_ERR_LO + 2)];
   assign ifd_ifc_cpxnc_i2    = ifqop_i2[`CPX_NC];
   assign ifd_ifc_fwd2ic_i2   = ifqop_i2[103];



   dp_mux4ds  #(33)  fillinst_mux(.dout (ifq_fdp_fill_inst),
				                        .in0 (icdata_i2[134:102]),
				                        .in1 (icdata_i2[100:68]),
				                        .in2 (icdata_i2[66:34]),
				                        .in3 (icdata_i2[32:0]),
				                        .sel0_l (ifc_ifd_finst_sel_l[0]),
				                        .sel1_l (ifc_ifd_finst_sel_l[1]),
				                        .sel2_l (ifc_ifd_finst_sel_l[2]),
				                        .sel3_l (ifc_ifd_finst_sel_l[3]));













   
   









   assign  stxa_data_pkt[`CPX_VLD] = 1'b0;

   assign  stxa_data_pkt[`CPX_REQFIELD] = {1'b1, lsu_ifu_stxa_data[34:32]}; 

   assign  stxa_data_pkt[`CPX_THRFIELD] = 2'b0;   

   assign  stxa_data_pkt[(`CPX_ERR_LO + 1)] = lsu_ifu_stxa_data[32];   
   assign  stxa_data_pkt[127:0] = {4{lsu_ifu_stxa_data[31:0]}};


   assign  stxa_data_pkt[133:128] = 6'b0;   
   assign  stxa_data_pkt[137:136] = 2'b0;   
   assign  stxa_data_pkt[139] = 1'b0;


   assign  fwd_data_pkt[`CPX_VLD:(`CPX_ERR_LO + 2)] = ifqop_i2[`CPX_VLD:(`CPX_ERR_LO + 2)];
   assign  fwd_data_pkt[(`CPX_ERR_LO + 1)] = ifqop_i2[32];   
   assign  fwd_data_pkt[`CPX_ERR_LO:128] = ifqop_i2[`CPX_ERR_LO:128];
   assign  fwd_data_pkt[127:0] = {4{ifqop_i2[31:0]}};
   

   
   dff_s #(16) stxa_ff(.din (lsu_ifu_stxa_data[47:32]),
		                 .q   (ifq_erb_asidata_i2[47:32]), 
		                 .clk (clk), .se(se), .si(), .so());
   assign  ifq_erb_asidata_i2[31:0] = ifqop_i2[31:0];








   dp_mux2es #(12) asifwd_mx(.dout (asi_fwd_index[13:2]),
                             .in0  ({lsu_ifu_asi_addr[17:16],
                                     lsu_ifu_asi_addr[12:3]}),
                             .in1  ({ifqop_i2[81:80],
                                     ifqop_i2[76:67]}),
                             .sel  (ifc_ifd_idx_sel_fwd_i2));

   assign asi_va_i1 = {asi_fwd_index[13:12],
                       lsu_ifu_asi_addr[15:13],
                       asi_fwd_index[11:2],
                       lsu_ifu_asi_addr[2:0]};
   
   dff_s #(18) asi_addr_reg(.din (asi_va_i1[17:0]),
			                    .q   (asi_va_i2[17:0]),
			                    .clk (clk),
			                    .se  (se), .si(), .so());


   assign  ifd_ifc_asi_vachklo_i2 = (|asi_va_i2[16:4]) | (|asi_va_i2[2:0]);



   assign    ifd_ifc_asiaddr_i2[3:2] = asi_va_i2[4:3];

   assign    asi_addr_i2 = {tag_par_i2,
			                      asi_va_i2[17:16],
			                      ifqop_i2[27:0],
			                      asi_va_i2[12:3]
                            };                 



   assign    bist_addr_i2 = {1'b0,
			                       mbist_icache_way[1:0],
			                       28'b0,
			                       mbist_icache_index[7:0],
                             mbist_icache_word,
			                       1'b0
			                       };


   sink #(2) s0(.in (imiss_paddr_s[1:0]));
   sink s1(.in (pcxreq_e[42]));
   sink s2(.in (fill_addr_i2[4]));
   
   
endmodule
module sparc_ifu_ifqdp(

   so, ifu_lsu_pcxpkt_e, ifq_fdp_fill_inst, ifq_erb_asidata_i2, 
   ifd_inv_ifqop_i2, ifq_icd_index_bf, ifq_icd_wrdata_i2, 
   ifq_ict_wrtag_f, ifq_erb_wrindex_f, ifq_icd_wrway_bf, 
   ifd_ifc_milhit_s, ifd_ifc_instoffset0, ifd_ifc_instoffset1, 
   ifd_ifc_instoffset2, ifd_ifc_instoffset3, ifd_ifc_cpxthr_nxt, 
   ifd_ifc_cpxreq_nxt, ifd_ifc_cpxreq_i1, ifd_ifc_destid0, 
   ifd_ifc_destid1, ifd_ifc_destid2, ifd_ifc_destid3, 
   ifd_ifc_newdestid_s, ifd_ifc_pcxline_d, ifd_ifc_asi_vachklo_i2, 
   ifd_ifc_cpxvld_i2, ifd_ifc_asiaddr_i2, ifd_ifc_iobpkt_i2, 
   ifd_ifc_fwd2ic_i2, ifd_ifc_4bpkt_i2, ifd_ifc_cpxnc_i2, 
   ifd_ifc_cpxce_i2, ifd_ifc_cpxue_i2, ifd_ifc_cpxms_i2, 
   ifd_ifc_miladdr4_i2, ifd_inv_wrway_i2, 

   rclk, se, si, lsu_ifu_cpxpkt_i1, lsu_ifu_asi_addr, 
   lsu_ifu_stxa_data, itlb_ifq_paddr_s, fdp_ifq_paddr_f, 
   ifc_ifd_reqvalid_e, ifc_ifd_filladdr4_i2, ifc_ifd_repway_s, 
   ifc_ifd_uncached_e, ifc_ifd_thrid_e, ifc_ifd_pcxline_adj_d, 
   ifc_ifd_errinv_e, ifc_ifd_ldmil_sel_new, ifc_ifd_ld_inq_i1, 
   ifc_ifd_idx_sel_fwd_i2, ifc_ifd_milreq_sel_d_l, 
   ifc_ifd_milfill_sel_i2_l, ifc_ifd_finst_sel_l, 
   ifc_ifd_ifqbyp_sel_fwd_l, ifc_ifd_ifqbyp_sel_inq_l, 
   ifc_ifd_ifqbyp_sel_asi_l, ifc_ifd_ifqbyp_sel_lsu_l, 
   ifc_ifd_ifqbyp_en_l, ifc_ifd_addr_sel_bist_i2_l, 
   ifc_ifd_addr_sel_asi_i2_l, ifc_ifd_addr_sel_old_i2_l, 
   ifc_ifd_addr_sel_fill_i2_l, mbist_icache_way, mbist_icache_word, 
   mbist_icache_index
   );


   input 	 rclk, 
           se, 
           si;
   
   input [`CPX_WIDTH-1:0] lsu_ifu_cpxpkt_i1;
   input [17:0]   lsu_ifu_asi_addr;
   input [47:0]   lsu_ifu_stxa_data;
   
   input [39:10]  itlb_ifq_paddr_s;
   input [9:2]    fdp_ifq_paddr_f;
   

   input         ifc_ifd_reqvalid_e;
   input         ifc_ifd_filladdr4_i2;
   input [1:0]   ifc_ifd_repway_s;
   input         ifc_ifd_uncached_e;
   input [1:0]   ifc_ifd_thrid_e;
   input [4:2]   ifc_ifd_pcxline_adj_d;
   
   input         ifc_ifd_errinv_e;
   

   input [3:0]   ifc_ifd_ldmil_sel_new;
   
   input        ifc_ifd_ld_inq_i1;
   input        ifc_ifd_idx_sel_fwd_i2;
   

   input [3:0]  ifc_ifd_milreq_sel_d_l,
		            ifc_ifd_milfill_sel_i2_l;


   input [3:0]  ifc_ifd_finst_sel_l;

   input        ifc_ifd_ifqbyp_sel_fwd_l,
		            ifc_ifd_ifqbyp_sel_inq_l,
		            ifc_ifd_ifqbyp_sel_asi_l,
		            ifc_ifd_ifqbyp_sel_lsu_l;
	 input        ifc_ifd_ifqbyp_en_l;   

   input        ifc_ifd_addr_sel_bist_i2_l,
		            ifc_ifd_addr_sel_asi_i2_l,
                ifc_ifd_addr_sel_old_i2_l,
		            ifc_ifd_addr_sel_fill_i2_l;
   
   input [1:0]  mbist_icache_way;
   input        mbist_icache_word;
   input [7:0]  mbist_icache_index;
   
   output       so;
   
   output [51:0] ifu_lsu_pcxpkt_e;

   output [32:0] ifq_fdp_fill_inst;
   output [47:0] ifq_erb_asidata_i2;

   output [`CPX_WIDTH-1:0] ifd_inv_ifqop_i2;

   output [`IC_IDX_HI:2]  ifq_icd_index_bf;
   
   output [135:0]         ifq_icd_wrdata_i2;
   output [`IC_TAG_SZ:0]  ifq_ict_wrtag_f;

   output [`IC_IDX_HI:4]   ifq_erb_wrindex_f;
   output [1:0]            ifq_icd_wrway_bf;
   
   output [3:0]           ifd_ifc_milhit_s;

   
   output [1:0]           ifd_ifc_instoffset0;
   output [1:0]           ifd_ifc_instoffset1;
   output [1:0]           ifd_ifc_instoffset2;
   output [1:0]           ifd_ifc_instoffset3;

   output [1:0]            ifd_ifc_cpxthr_nxt;
   output [3:0]            ifd_ifc_cpxreq_nxt;
   output [`CPX_RQ_SIZE:0] ifd_ifc_cpxreq_i1;

   
   output [2:0]            ifd_ifc_destid0,
		                       ifd_ifc_destid1,
		                       ifd_ifc_destid2,
		                       ifd_ifc_destid3,
		                       ifd_ifc_newdestid_s;

   output [4:2]            ifd_ifc_pcxline_d;

   output                  ifd_ifc_asi_vachklo_i2;
                         
   output                  ifd_ifc_cpxvld_i2;
   output [3:2]            ifd_ifc_asiaddr_i2;   
   output                  ifd_ifc_iobpkt_i2;
   output                  ifd_ifc_fwd2ic_i2;
   output                  ifd_ifc_4bpkt_i2;
   output                  ifd_ifc_cpxnc_i2;
   output                  ifd_ifc_cpxce_i2,
		                       ifd_ifc_cpxue_i2,
                           ifd_ifc_cpxms_i2;
   
   output [3:0]            ifd_ifc_miladdr4_i2;
   
   output [1:0]            ifd_inv_wrway_i2;

   
 	 





   wire [39:0]             imiss_paddr_s;
   wire [9:2]              lcl_paddr_s;
   
   wire [42:2]             mil_entry0,
		                       mil_entry1,
		                       mil_entry2,
		                       mil_entry3;






   wire                    tag_par_s,
		                       tag_par_i2;

   wire [42:2]             newmil_entry_s;
   
   wire [42:2]             mil_pcxreq_d,
		                       pcxreq_d,
		                       pcxreq_e;

   wire [42:2]             fill_addr_i2,
		                       fill_addr_adj,
		                       icaddr_i2,
		                       asi_addr_i2,
		                       bist_addr_i2;

   wire [42:4]             wraddr_f;


   wire [`CPX_WIDTH-1:0]   inq_cpxpkt_i1,

			                     stxa_data_pkt,
                           fwd_data_pkt,
			                     ifqop_i1,
			                     ifqop_i2;

   wire [3:0]              swc_i2;
   
   wire [135:0]            icdata_i2;
   
   wire [3:0]              parity_i2,
		                       par_i2;

   wire [17:0]             asi_va_i2,
                           asi_va_i1;
   wire [13:2]             asi_fwd_index;
   wire                    clk;
   
   

   




   assign                  clk = rclk;
   





   dff_s #(8) pcs_reg(.din (fdp_ifq_paddr_f[9:2]),
                    .q   (lcl_paddr_s[9:2]),
                    .clk (clk), .se(se), .si(), .so());
                    


   assign  imiss_paddr_s = {itlb_ifq_paddr_s[39:10], 
                            lcl_paddr_s[9:2],
                            2'b0};
   




   sparc_ifu_cmp35 milcmp0 (.hit (ifd_ifc_milhit_s[0]),
			                      .a (imiss_paddr_s[39:5]),
			                      .b (mil_entry0[39:5]),
			                      .valid (1'b1)
			                      );
   
   sparc_ifu_cmp35 milcmp1 (.hit (ifd_ifc_milhit_s[1]),
			                      .a (imiss_paddr_s[39:5]),
			                      .b (mil_entry1[39:5]),
			                      .valid (1'b1)
			                      );
   
   sparc_ifu_cmp35 milcmp2 (.hit (ifd_ifc_milhit_s[2]),
			                      .a (imiss_paddr_s[39:5]),
			                      .b (mil_entry2[39:5]),
			                      .valid (1'b1)
			                      );
   sparc_ifu_cmp35 milcmp3 (.hit (ifd_ifc_milhit_s[3]),
			                      .a (imiss_paddr_s[39:5]),
			                      .b (mil_entry3[39:5]),
			                      .valid (1'b1)
			                      );









   sparc_ifu_par32 tag_par(.in  ({{`ICT_FILL_BITS{1'b0}}, 
                                  imiss_paddr_s[`IC_TAG_HI:`IC_TAG_LO]}),
			                     .out (tag_par_s));









   assign  newmil_entry_s = {tag_par_s,
			                       ifc_ifd_repway_s,			    
			                       imiss_paddr_s[39:2]};



















   wire    clk_mil0;
`ifdef FPGA_SYN_CLK_EN
`else
   bw_u1_ckenbuf_6x  ckenmil0(.rclk (rclk),
                              .clk  (clk_mil0),
                              .en_l (~ifc_ifd_ldmil_sel_new[0]),
                              .tm_l (~se));
`endif
   wire    clk_mil1;
`ifdef FPGA_SYN_CLK_EN
`else
   bw_u1_ckenbuf_6x  ckenmil1(.rclk (rclk),
                              .clk  (clk_mil1),
                              .en_l (~ifc_ifd_ldmil_sel_new[1]),
                              .tm_l (~se));
`endif
   wire    clk_mil2;
`ifdef FPGA_SYN_CLK_EN
`else
   bw_u1_ckenbuf_6x  ckenmil2(.rclk (rclk),
                              .clk  (clk_mil2),
                              .en_l (~ifc_ifd_ldmil_sel_new[2]),
                              .tm_l (~se));
`endif
   wire    clk_mil3;
`ifdef FPGA_SYN_CLK_EN
`else
   bw_u1_ckenbuf_6x  ckenmil3(.rclk (rclk),
                              .clk  (clk_mil3),
                              .en_l (~ifc_ifd_ldmil_sel_new[3]),
                              .tm_l (~se));
`endif
   

`ifdef FPGA_SYN_CLK_DFF
   dffe_s #(41)   mil0(.din  (newmil_entry_s), 
		                .en (~(~ifc_ifd_ldmil_sel_new[0])), .clk(rclk), 
		                .q    (mil_entry0), 
		                .se   (se), .si(), .so());
`else
   dff_s #(41)   mil0(.din  (newmil_entry_s), 
		                .clk  (clk_mil0), 
		                .q    (mil_entry0), 
		                .se   (se), .si(), .so());
`endif

`ifdef FPGA_SYN_CLK_DFF
   dffe_s #(41)   mil1(.din (newmil_entry_s), 
		                .en (~(~ifc_ifd_ldmil_sel_new[1])), .clk(rclk), 
		                .q   (mil_entry1), 
		                .se  (se), .si(), .so());
`else
   dff_s #(41)   mil1(.din (newmil_entry_s), 
		                .clk (clk_mil1), 
		                .q   (mil_entry1), 
		                .se  (se), .si(), .so());
`endif

`ifdef FPGA_SYN_CLK_DFF
   dffe_s #(41)   mil2(.din (newmil_entry_s), 
		                .en (~(~ifc_ifd_ldmil_sel_new[2])), .clk(rclk), 
		                .q   (mil_entry2), 
		                .se  (se), .si(), .so());
`else
   dff_s #(41)   mil2(.din (newmil_entry_s), 
		                .clk (clk_mil2), 
		                .q   (mil_entry2), 
		                .se  (se), .si(), .so());
`endif

`ifdef FPGA_SYN_CLK_DFF
   dffe_s #(41)   mil3(.din (newmil_entry_s), 
		                .en (~(~ifc_ifd_ldmil_sel_new[3])), .clk(rclk), 
		                .q   (mil_entry3), 
		                .se  (se), .si(), .so());
`else
   dff_s #(41)   mil3(.din (newmil_entry_s), 
		                .clk (clk_mil3), 
		                .q   (mil_entry3), 
		                .se  (se), .si(), .so());
`endif

   assign  ifd_ifc_newdestid_s = {imiss_paddr_s[39], 
				                          imiss_paddr_s[`BANK_ID_HI:`BANK_ID_LO]};
   assign  ifd_ifc_destid0 = {mil_entry0[39], 
			                        mil_entry0[`BANK_ID_HI:`BANK_ID_LO]};
   assign  ifd_ifc_destid1 = {mil_entry1[39], 
			                        mil_entry1[`BANK_ID_HI:`BANK_ID_LO]};
   assign  ifd_ifc_destid2 = {mil_entry2[39], 
			                        mil_entry2[`BANK_ID_HI:`BANK_ID_LO]};
   assign  ifd_ifc_destid3 = {mil_entry3[39], 
			                        mil_entry3[`BANK_ID_HI:`BANK_ID_LO]};

   assign  ifd_ifc_instoffset0 = mil_entry0[3:2];
   assign  ifd_ifc_instoffset1 = mil_entry1[3:2];
   assign  ifd_ifc_instoffset2 = mil_entry2[3:2];
   assign  ifd_ifc_instoffset3 = mil_entry3[3:2];
   
   

   dp_mux4ds  #(41)  milreq_mux (.dout (mil_pcxreq_d),
			                         .in0  ({mil_entry0[42:2]}),
			                         .in1  ({mil_entry1[42:2]}),
			                         .in2  ({mil_entry2[42:2]}),
			                         .in3  ({mil_entry3[42:2]}),
			                         .sel0_l  (ifc_ifd_milreq_sel_d_l[0]),
			                         .sel1_l  (ifc_ifd_milreq_sel_d_l[1]),
			                         .sel2_l  (ifc_ifd_milreq_sel_d_l[2]),
			                         .sel3_l  (ifc_ifd_milreq_sel_d_l[3]));
   












   assign  ifd_ifc_pcxline_d[4:2] = mil_pcxreq_d[4:2];
   
   assign  pcxreq_d[42:5] = mil_pcxreq_d[42:5];
   assign  pcxreq_d[4:2] = ifc_ifd_pcxline_adj_d[4:2];


   dff_s #(41) pcxreq_reg (.din  (pcxreq_d),
			                    .clk  (clk),
			                    .q    (pcxreq_e),
			                    .se   (se), .si(), .so());







   

   assign   ifu_lsu_pcxpkt_e = {ifc_ifd_reqvalid_e,
			                          ifc_ifd_errinv_e,
                                ifc_ifd_uncached_e,
			                          {`IMISS_RQ},
			                          pcxreq_e[41:40],
			                          ifc_ifd_thrid_e[1:0],
			                          pcxreq_e[39:2],
			                          2'b0};
   






   dp_mux4ds  #(41)  milfill_mux(.dout (fill_addr_i2),
			                         .in0 ( mil_entry0),
			                         .in1 ( mil_entry1),
			                         .in2 ( mil_entry2),
			                         .in3 ( mil_entry3),
			                         .sel0_l (ifc_ifd_milfill_sel_i2_l[0]),
			                         .sel1_l (ifc_ifd_milfill_sel_i2_l[1]),
			                         .sel2_l (ifc_ifd_milfill_sel_i2_l[2]),
			                         .sel3_l (ifc_ifd_milfill_sel_i2_l[3]));

   assign   ifd_ifc_miladdr4_i2[3:0]  = {mil_entry3[4],
                                         mil_entry2[4],
                                         mil_entry1[4],
                                         mil_entry0[4]};
   
   assign   ifd_ifc_iobpkt_i2 = fill_addr_i2[39];
   assign   fill_addr_adj = {fill_addr_i2[42:5], 
			                       ifc_ifd_filladdr4_i2,
			                       fill_addr_i2[3:2]};





   dp_mux4ds #(41) icadr_mux(.dout (icaddr_i2),
			                       .in0  (fill_addr_adj),
			                       .in1  (asi_addr_i2),
			                       .in2  (bist_addr_i2),
                             .in3  ({wraddr_f[42:4], 2'b0}),
			                       .sel0_l (ifc_ifd_addr_sel_fill_i2_l),
			                       .sel1_l (ifc_ifd_addr_sel_asi_i2_l),
			                       .sel2_l (ifc_ifd_addr_sel_bist_i2_l),
                             .sel3_l (ifc_ifd_addr_sel_old_i2_l));
   

   assign ifd_inv_wrway_i2 =  icaddr_i2[41:40];






   
   dff_s #(39) wraddr_reg(.din  (icaddr_i2[42:4]),
		                    .clk  (clk),
		                    .q    (wraddr_f[42:4]),
		                    .se   (se), .si(), .so());


   assign  ifq_erb_wrindex_f = wraddr_f[`IC_IDX_HI:4];
   assign  ifq_ict_wrtag_f = {wraddr_f[42], wraddr_f[`IC_TAG_HI:`IC_TAG_LO]};

   assign  ifq_icd_index_bf = icaddr_i2[`IC_IDX_HI:2];
   assign  ifq_icd_wrway_bf = icaddr_i2[41:40];














   wire    clk_ibuf1;
`ifdef FPGA_SYN_CLK_EN
`else
   bw_u1_ckenbuf_6x  ckenibuf(.rclk (rclk),
                              .clk  (clk_ibuf1),
                              .en_l (~ifc_ifd_ld_inq_i1),
                              .tm_l (~se));
`endif
                             
`ifdef FPGA_SYN_CLK_DFF
   dffe_s #(`CPX_WIDTH) ibuf(.din (lsu_ifu_cpxpkt_i1),
			                  .q   (inq_cpxpkt_i1),
			                  .en (~(~ifc_ifd_ld_inq_i1)), .clk(rclk),
			                  .se  (se), .si(), .so());
`else
   dff_s #(`CPX_WIDTH) ibuf(.din (lsu_ifu_cpxpkt_i1),
			                  .q   (inq_cpxpkt_i1),
			                  .clk (clk_ibuf1),
			                  .se  (se), .si(), .so());
`endif

   assign  ifd_ifc_cpxreq_i1 = {inq_cpxpkt_i1[`CPX_VLD], 
			                          inq_cpxpkt_i1[`CPX_REQFIELD]};



   dp_mux4ds  #(`CPX_WIDTH)  ifq_bypmux(.dout (ifqop_i1),
				                              .in0 (fwd_data_pkt), 
				                              .in1 (inq_cpxpkt_i1),
				                              .in2 (stxa_data_pkt),
				                              .in3 (lsu_ifu_cpxpkt_i1),
				                              .sel0_l (ifc_ifd_ifqbyp_sel_fwd_l),
				                              .sel1_l (ifc_ifd_ifqbyp_sel_inq_l),
				                              .sel2_l (ifc_ifd_ifqbyp_sel_asi_l),
				                              .sel3_l (ifc_ifd_ifqbyp_sel_lsu_l));
   
   wire    clk_ifqop;
`ifdef FPGA_SYN_CLK_EN
`else
   bw_u1_ckenbuf_6x  ckenifop(.rclk (rclk),
                              .clk  (clk_ifqop),
                              .en_l (ifc_ifd_ifqbyp_en_l),
                              .tm_l (~se));
`endif
   
`ifdef FPGA_SYN_CLK_DFF
   dffe_s #(`CPX_WIDTH)  ifqop_reg(.din (ifqop_i1), 
			                        .q   (ifqop_i2), 
			                        .en (~(ifc_ifd_ifqbyp_en_l)), .clk(rclk), 
			                        .se  (se), .si(), .so());
`else
   dff_s #(`CPX_WIDTH)  ifqop_reg(.din (ifqop_i1), 
			                        .q   (ifqop_i2), 
			                        .clk (clk_ifqop), 
			                        .se  (se), .si(), .so());
`endif
   assign  ifd_inv_ifqop_i2 = ifqop_i2;
   

   sparc_ifu_swpla  swpla0(.in  (ifqop_i2[31:0]),
			                     .out (swc_i2[0]));
   sparc_ifu_swpla  swpla1(.in  (ifqop_i2[63:32]),
			                     .out (swc_i2[1]));
   sparc_ifu_swpla  swpla2(.in  (ifqop_i2[95:64]),
			                     .out (swc_i2[2]));
   sparc_ifu_swpla  swpla3(.in  (ifqop_i2[127:96]),
			                     .out (swc_i2[3]));


   sparc_ifu_par32 par0(.in  (ifqop_i2[31:0]),
			                  .out (par_i2[0]));
   sparc_ifu_par32 par1(.in  (ifqop_i2[63:32]),
			                  .out (par_i2[1]));
   sparc_ifu_par32 par2(.in  (ifqop_i2[95:64]),
			                  .out (par_i2[2]));
   sparc_ifu_par32 par3(.in  (ifqop_i2[127:96]),
			                  .out (par_i2[3]));






   assign   parity_i2 = par_i2 ^ swc_i2 ^ {4{ifd_ifc_cpxue_i2}};
   assign   tag_par_i2 = par_i2[0] ^ ifd_ifc_cpxue_i2;
   

   assign   icdata_i2 = {parity_i2[3], ifqop_i2[127:96], swc_i2[3],
		                     parity_i2[2], ifqop_i2[95:64],  swc_i2[2],
		                     parity_i2[1], ifqop_i2[63:32],  swc_i2[1],
		                     parity_i2[0], ifqop_i2[31:0],   swc_i2[0]};


   assign ifq_icd_wrdata_i2 = icdata_i2;



   assign ifd_ifc_cpxreq_nxt   = ifqop_i1[`CPX_REQFIELD];
   assign ifd_ifc_cpxthr_nxt   = ifqop_i1[`CPX_THRFIELD];

   assign ifd_ifc_cpxvld_i2   = ifqop_i2[`CPX_VLD];
   assign ifd_ifc_4bpkt_i2    = ifqop_i2[`CPX_IF4B];
   assign ifd_ifc_cpxce_i2    = ifqop_i2[`CPX_ERR_LO];
   assign ifd_ifc_cpxue_i2    = ifqop_i2[(`CPX_ERR_LO + 1)];
   assign ifd_ifc_cpxms_i2    = ifqop_i2[(`CPX_ERR_LO + 2)];
   assign ifd_ifc_cpxnc_i2    = ifqop_i2[`CPX_NC];
   assign ifd_ifc_fwd2ic_i2   = ifqop_i2[103];



   dp_mux4ds  #(33)  fillinst_mux(.dout (ifq_fdp_fill_inst),
				                        .in0 (icdata_i2[134:102]),
				                        .in1 (icdata_i2[100:68]),
				                        .in2 (icdata_i2[66:34]),
				                        .in3 (icdata_i2[32:0]),
				                        .sel0_l (ifc_ifd_finst_sel_l[0]),
				                        .sel1_l (ifc_ifd_finst_sel_l[1]),
				                        .sel2_l (ifc_ifd_finst_sel_l[2]),
				                        .sel3_l (ifc_ifd_finst_sel_l[3]));













   
   









   assign  stxa_data_pkt[`CPX_VLD] = 1'b0;

   assign  stxa_data_pkt[`CPX_REQFIELD] = {1'b1, lsu_ifu_stxa_data[34:32]}; 

   assign  stxa_data_pkt[`CPX_THRFIELD] = 2'b0;   

   assign  stxa_data_pkt[(`CPX_ERR_LO + 1)] = lsu_ifu_stxa_data[32];   
   assign  stxa_data_pkt[127:0] = {4{lsu_ifu_stxa_data[31:0]}};


   assign  stxa_data_pkt[133:128] = 6'b0;   
   assign  stxa_data_pkt[137:136] = 2'b0;   
   assign  stxa_data_pkt[139] = 1'b0;


   assign  fwd_data_pkt[`CPX_VLD:(`CPX_ERR_LO + 2)] = ifqop_i2[`CPX_VLD:(`CPX_ERR_LO + 2)];
   assign  fwd_data_pkt[(`CPX_ERR_LO + 1)] = ifqop_i2[32];   
   assign  fwd_data_pkt[`CPX_ERR_LO:128] = ifqop_i2[`CPX_ERR_LO:128];
   assign  fwd_data_pkt[127:0] = {4{ifqop_i2[31:0]}};
   

   
   dff_s #(16) stxa_ff(.din (lsu_ifu_stxa_data[47:32]),
		                 .q   (ifq_erb_asidata_i2[47:32]), 
		                 .clk (clk), .se(se), .si(), .so());
   assign  ifq_erb_asidata_i2[31:0] = ifqop_i2[31:0];








   dp_mux2es #(12) asifwd_mx(.dout (asi_fwd_index[13:2]),
                             .in0  ({lsu_ifu_asi_addr[17:16],
                                     lsu_ifu_asi_addr[12:3]}),
                             .in1  ({ifqop_i2[81:80],
                                     ifqop_i2[76:67]}),
                             .sel  (ifc_ifd_idx_sel_fwd_i2));

   assign asi_va_i1 = {asi_fwd_index[13:12],
                       lsu_ifu_asi_addr[15:13],
                       asi_fwd_index[11:2],
                       lsu_ifu_asi_addr[2:0]};
   
   dff_s #(18) asi_addr_reg(.din (asi_va_i1[17:0]),
			                    .q   (asi_va_i2[17:0]),
			                    .clk (clk),
			                    .se  (se), .si(), .so());


   assign  ifd_ifc_asi_vachklo_i2 = (|asi_va_i2[16:4]) | (|asi_va_i2[2:0]);



   assign    ifd_ifc_asiaddr_i2[3:2] = asi_va_i2[4:3];

   assign    asi_addr_i2 = {tag_par_i2,
			                      asi_va_i2[17:16],
			                      ifqop_i2[27:0],
			                      asi_va_i2[12:3]
                            };                 



   assign    bist_addr_i2 = {1'b0,
			                       mbist_icache_way[1:0],
			                       28'b0,
			                       mbist_icache_index[7:0],
                             mbist_icache_word,
			                       1'b0
			                       };


   sink #(2) s0(.in (imiss_paddr_s[1:0]));
   sink s1(.in (pcxreq_e[42]));
   sink s2(.in (fill_addr_i2[4]));
   
   
endmodule