data/full_repos/permissive/471424795/designs/def_test/src/def_test.v
data/verilator_xmls/6c95e7d5-af89-409a-8c37-17ba6f27306d.xml
module def_test (
    input wire in,
    output out );

    assign out = !in;

endmodule
module def_test (
    input wire in,
    output out );


    assign out = !in;

endmodule