data/full_repos/permissive/42434302/ivltests/case5.v
1: b'%Error: data/full_repos/permissive/42434302/ivltests/case5.v:6: syntax error, unexpected bit, expecting IDENTIFIER or \'=\' or do or final\n   reg clk, bit, foo, clr;\n            ^~~\n%Error: data/full_repos/permissive/42434302/ivltests/case5.v:11: syntax error, unexpected \')\', expecting "\'{"\n     else case (bit)\n                   ^\n%Error: data/full_repos/permissive/42434302/ivltests/case5.v:25: syntax error, unexpected INTEGER NUMBER, expecting new or new-then-paren\n      bit = 0;\n            ^\n%Error: data/full_repos/permissive/42434302/ivltests/case5.v:28: syntax error, unexpected !==, expecting "\'{"\n      if (bit !== 0 || foo !== 0) begin\n              ^~~\n%Error: data/full_repos/permissive/42434302/ivltests/case5.v:35: syntax error, unexpected !==, expecting "\'{"\n      if (bit !== 0 || foo !== 0) begin\n              ^~~\n%Error: data/full_repos/permissive/42434302/ivltests/case5.v:42: syntax error, unexpected !==, expecting "\'{"\n      if (bit !== 1 || foo !== 1) begin\n              ^~~\n%Error: data/full_repos/permissive/42434302/ivltests/case5.v:48: syntax error, unexpected !==, expecting "\'{"\n      if (bit !== 1 || foo !== 0) begin\n              ^~~\n%Error: Cannot continue\n'
module main;

   reg clk, bit, foo, clr;


   always @(posedge clk or posedge clr)
     if (clr) foo = 0;
     else case (bit)
       1'b0: ;
       1'b1: foo <= ~foo;
     endcase

   (* ivl_synthesis_off *)
   always begin
      #5 clk = 1;
      #5 clk = 0;
   end

   (* ivl_synthesis_off *)
   initial begin
      clk = 0;
      bit = 0;
      clr = 1;
      # 6 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo);
      if (bit !== 0 || foo !== 0) begin
	 $display("FAILED");
	 $finish;
      end
      clr = 0;

      #10 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo);
      if (bit !== 0 || foo !== 0) begin
	 $display("FAILED");
	 $finish;
      end

      bit <= 1;
      #10 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo);
      if (bit !== 1 || foo !== 1) begin
	 $display("FAILED");
	 $finish;
      end

      #10 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo);
      if (bit !== 1 || foo !== 0) begin
	 $display("FAILED");
	 $finish;
      end

      $display("PASSED");
      $finish;
   end

endmodule
module main;


   reg clk, bit, foo, clr;


   always @(posedge clk or posedge clr)
     if (clr) foo = 0;
     else case (bit)
       1'b0: ;
       1'b1: foo <= ~foo;
     endcase

   (* ivl_synthesis_off *)
   always begin
      #5 clk = 1;
      #5 clk = 0;
   end

   (* ivl_synthesis_off *)
   initial begin
      clk = 0;
      bit = 0;
      clr = 1;
      # 6 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo);
      if (bit !== 0 || foo !== 0) begin
	 $display("FAILED");
	 $finish;
      end
      clr = 0;

      #10 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo);
      if (bit !== 0 || foo !== 0) begin
	 $display("FAILED");
	 $finish;
      end

      bit <= 1;
      #10 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo);
      if (bit !== 1 || foo !== 1) begin
	 $display("FAILED");
	 $finish;
      end

      #10 $display("clk=%b, bit=%b, foo=%b", clk, bit, foo);
      if (bit !== 1 || foo !== 0) begin
	 $display("FAILED");
	 $finish;
      end

      $display("PASSED");
      $finish;
   end

endmodule