data/full_repos/permissive/458737381/src/verilog-parser/tests/std-4.4.3-expressions.v
1: b'%Warning-WIDTH: data/full_repos/permissive/458737381/src/verilog-parser/tests/std-4.4.3-expressions.v:10: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n                                                                                                        : ... In instance test\nc = {a**b};\n  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/458737381/src/verilog-parser/tests/std-4.4.3-expressions.v:12: Operator POW expects 16 bits on the LHS, but LHS\'s VARREF \'a\' generates 4 bits.\n                                                                                                        : ... In instance test\nc = a**b;\n     ^~\n%Error: Exiting due to 2 warning(s)\n'
module test;
reg [3:0] a;
reg [5:0] b;
reg [15:0] c;
initial begin
a = 4'hF;
b = 6'ha;
$display("a*b=%x",
a*b);
c = {a**b};
$display("a**b=%x", c);
c = a**b;
$display("c=%x", c);
end
endmodule
module test;

reg [3:0] a;
reg [5:0] b;
reg [15:0] c;
initial begin
a = 4'hF;
b = 6'ha;
$display("a*b=%x",
a*b);
c = {a**b};
$display("a**b=%x", c);
c = a**b;
$display("c=%x", c);
end
endmodule