data/full_repos/permissive/421223411/verilog/rtl/accelerator/CoreTop.v
data/verilator_xmls/0e0a0b45-d48b-4011-aaf8-3dc66ac7878c.xml
module RegFile(
  input         clock,
  input  [2:0]  io_rs1,
  input  [2:0]  io_rs2,
  output [15:0] io_rs1_dat,
  output [15:0] io_rs2_dat,
  input  [2:0]  io_rd,
  input  [15:0] io_rd_dat,
  input         io_rd_en,
  input         io_cc_in_z,
  input         io_cc_in_c,
  input         io_cc_in_n,
  input         io_cc_in_v,
  input         io_cc_en,
  output        io_cc_out_z,
  output        io_cc_out_c,
  output        io_cc_out_n,
  output        io_cc_out_v
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
`endif
  reg [15:0] rf_0;
  reg [15:0] rf_1;
  reg [15:0] rf_2;
  reg [15:0] rf_3;
  reg [15:0] rf_4;
  reg [15:0] rf_5;
  reg [15:0] rf_6;
  reg [15:0] rf_7;
  wire [15:0] _GEN_1 = 3'h1 == io_rs1 ? rf_1 : rf_0;
  wire [15:0] _GEN_2 = 3'h2 == io_rs1 ? rf_2 : _GEN_1;
  wire [15:0] _GEN_3 = 3'h3 == io_rs1 ? rf_3 : _GEN_2;
  wire [15:0] _GEN_4 = 3'h4 == io_rs1 ? rf_4 : _GEN_3;
  wire [15:0] _GEN_5 = 3'h5 == io_rs1 ? rf_5 : _GEN_4;
  wire [15:0] _GEN_6 = 3'h6 == io_rs1 ? rf_6 : _GEN_5;
  wire [15:0] _GEN_7 = 3'h7 == io_rs1 ? rf_7 : _GEN_6;
  wire [15:0] _GEN_9 = 3'h1 == io_rs2 ? rf_1 : rf_0;
  wire [15:0] _GEN_10 = 3'h2 == io_rs2 ? rf_2 : _GEN_9;
  wire [15:0] _GEN_11 = 3'h3 == io_rs2 ? rf_3 : _GEN_10;
  wire [15:0] _GEN_12 = 3'h4 == io_rs2 ? rf_4 : _GEN_11;
  wire [15:0] _GEN_13 = 3'h5 == io_rs2 ? rf_5 : _GEN_12;
  wire [15:0] _GEN_14 = 3'h6 == io_rs2 ? rf_6 : _GEN_13;
  wire [15:0] _GEN_15 = 3'h7 == io_rs2 ? rf_7 : _GEN_14;
  reg  cc_reg_z;
  reg  cc_reg_c;
  reg  cc_reg_n;
  reg  cc_reg_v;
  assign io_rs1_dat = io_rs1 == 3'h0 ? 16'h0 : _GEN_7;
  assign io_rs2_dat = io_rs2 == 3'h0 ? 16'h0 : _GEN_15;
  assign io_cc_out_z = cc_reg_z;
  assign io_cc_out_c = cc_reg_c;
  assign io_cc_out_n = cc_reg_n;
  assign io_cc_out_v = cc_reg_v;
  always @(posedge clock) begin
    if (io_rd_en) begin
      if (3'h0 == io_rd) begin
        rf_0 <= io_rd_dat;
      end
    end
    if (io_rd_en) begin
      if (3'h1 == io_rd) begin
        rf_1 <= io_rd_dat;
      end
    end
    if (io_rd_en) begin
      if (3'h2 == io_rd) begin
        rf_2 <= io_rd_dat;
      end
    end
    if (io_rd_en) begin
      if (3'h3 == io_rd) begin
        rf_3 <= io_rd_dat;
      end
    end
    if (io_rd_en) begin
      if (3'h4 == io_rd) begin
        rf_4 <= io_rd_dat;
      end
    end
    if (io_rd_en) begin
      if (3'h5 == io_rd) begin
        rf_5 <= io_rd_dat;
      end
    end
    if (io_rd_en) begin
      if (3'h6 == io_rd) begin
        rf_6 <= io_rd_dat;
      end
    end
    if (io_rd_en) begin
      if (3'h7 == io_rd) begin
        rf_7 <= io_rd_dat;
      end
    end
    if (io_cc_en) begin
      cc_reg_z <= io_cc_in_z;
    end
    if (io_cc_en) begin
      cc_reg_c <= io_cc_in_c;
    end
    if (io_cc_en) begin
      cc_reg_n <= io_cc_in_n;
    end
    if (io_cc_en) begin
      cc_reg_v <= io_cc_in_v;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  rf_0 = _RAND_0[15:0];
  _RAND_1 = {1{`RANDOM}};
  rf_1 = _RAND_1[15:0];
  _RAND_2 = {1{`RANDOM}};
  rf_2 = _RAND_2[15:0];
  _RAND_3 = {1{`RANDOM}};
  rf_3 = _RAND_3[15:0];
  _RAND_4 = {1{`RANDOM}};
  rf_4 = _RAND_4[15:0];
  _RAND_5 = {1{`RANDOM}};
  rf_5 = _RAND_5[15:0];
  _RAND_6 = {1{`RANDOM}};
  rf_6 = _RAND_6[15:0];
  _RAND_7 = {1{`RANDOM}};
  rf_7 = _RAND_7[15:0];
  _RAND_8 = {1{`RANDOM}};
  cc_reg_z = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  cc_reg_c = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  cc_reg_n = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  cc_reg_v = _RAND_11[0:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module RegFile(
  input         clock,
  input  [2:0]  io_rs1,
  input  [2:0]  io_rs2,
  output [15:0] io_rs1_dat,
  output [15:0] io_rs2_dat,
  input  [2:0]  io_rd,
  input  [15:0] io_rd_dat,
  input         io_rd_en,
  input         io_cc_in_z,
  input         io_cc_in_c,
  input         io_cc_in_n,
  input         io_cc_in_v,
  input         io_cc_en,
  output        io_cc_out_z,
  output        io_cc_out_c,
  output        io_cc_out_n,
  output        io_cc_out_v
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
`endif
  reg [15:0] rf_0;
  reg [15:0] rf_1;
  reg [15:0] rf_2;
  reg [15:0] rf_3;
  reg [15:0] rf_4;
  reg [15:0] rf_5;
  reg [15:0] rf_6;
  reg [15:0] rf_7;
  wire [15:0] _GEN_1 = 3'h1 == io_rs1 ? rf_1 : rf_0;
  wire [15:0] _GEN_2 = 3'h2 == io_rs1 ? rf_2 : _GEN_1;
  wire [15:0] _GEN_3 = 3'h3 == io_rs1 ? rf_3 : _GEN_2;
  wire [15:0] _GEN_4 = 3'h4 == io_rs1 ? rf_4 : _GEN_3;
  wire [15:0] _GEN_5 = 3'h5 == io_rs1 ? rf_5 : _GEN_4;
  wire [15:0] _GEN_6 = 3'h6 == io_rs1 ? rf_6 : _GEN_5;
  wire [15:0] _GEN_7 = 3'h7 == io_rs1 ? rf_7 : _GEN_6;
  wire [15:0] _GEN_9 = 3'h1 == io_rs2 ? rf_1 : rf_0;
  wire [15:0] _GEN_10 = 3'h2 == io_rs2 ? rf_2 : _GEN_9;
  wire [15:0] _GEN_11 = 3'h3 == io_rs2 ? rf_3 : _GEN_10;
  wire [15:0] _GEN_12 = 3'h4 == io_rs2 ? rf_4 : _GEN_11;
  wire [15:0] _GEN_13 = 3'h5 == io_rs2 ? rf_5 : _GEN_12;
  wire [15:0] _GEN_14 = 3'h6 == io_rs2 ? rf_6 : _GEN_13;
  wire [15:0] _GEN_15 = 3'h7 == io_rs2 ? rf_7 : _GEN_14;
  reg  cc_reg_z;
  reg  cc_reg_c;
  reg  cc_reg_n;
  reg  cc_reg_v;
  assign io_rs1_dat = io_rs1 == 3'h0 ? 16'h0 : _GEN_7;
  assign io_rs2_dat = io_rs2 == 3'h0 ? 16'h0 : _GEN_15;
  assign io_cc_out_z = cc_reg_z;
  assign io_cc_out_c = cc_reg_c;
  assign io_cc_out_n = cc_reg_n;
  assign io_cc_out_v = cc_reg_v;
  always @(posedge clock) begin
    if (io_rd_en) begin
      if (3'h0 == io_rd) begin
        rf_0 <= io_rd_dat;
      end
    end
    if (io_rd_en) begin
      if (3'h1 == io_rd) begin
        rf_1 <= io_rd_dat;
      end
    end
    if (io_rd_en) begin
      if (3'h2 == io_rd) begin
        rf_2 <= io_rd_dat;
      end
    end
    if (io_rd_en) begin
      if (3'h3 == io_rd) begin
        rf_3 <= io_rd_dat;
      end
    end
    if (io_rd_en) begin
      if (3'h4 == io_rd) begin
        rf_4 <= io_rd_dat;
      end
    end
    if (io_rd_en) begin
      if (3'h5 == io_rd) begin
        rf_5 <= io_rd_dat;
      end
    end
    if (io_rd_en) begin
      if (3'h6 == io_rd) begin
        rf_6 <= io_rd_dat;
      end
    end
    if (io_rd_en) begin
      if (3'h7 == io_rd) begin
        rf_7 <= io_rd_dat;
      end
    end
    if (io_cc_en) begin
      cc_reg_z <= io_cc_in_z;
    end
    if (io_cc_en) begin
      cc_reg_c <= io_cc_in_c;
    end
    if (io_cc_en) begin
      cc_reg_n <= io_cc_in_n;
    end
    if (io_cc_en) begin
      cc_reg_v <= io_cc_in_v;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  rf_0 = _RAND_0[15:0];
  _RAND_1 = {1{`RANDOM}};
  rf_1 = _RAND_1[15:0];
  _RAND_2 = {1{`RANDOM}};
  rf_2 = _RAND_2[15:0];
  _RAND_3 = {1{`RANDOM}};
  rf_3 = _RAND_3[15:0];
  _RAND_4 = {1{`RANDOM}};
  rf_4 = _RAND_4[15:0];
  _RAND_5 = {1{`RANDOM}};
  rf_5 = _RAND_5[15:0];
  _RAND_6 = {1{`RANDOM}};
  rf_6 = _RAND_6[15:0];
  _RAND_7 = {1{`RANDOM}};
  rf_7 = _RAND_7[15:0];
  _RAND_8 = {1{`RANDOM}};
  cc_reg_z = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  cc_reg_c = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  cc_reg_n = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  cc_reg_v = _RAND_11[0:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule