data/full_repos/permissive/458208177/hdl/32_bit_add_cla_tree.v
data/verilator_xmls/58351226-0f93-46d8-8a2a-3b95175c06b8.xml
module gp(G_hl, P_hl, G_h, P_h, G_l, P_l);
    output G_hl, P_hl;
    input G_h, P_h, G_l, P_l;

    wire w1;







    and(w1, P_h, G_l);
    or(G_hl, w1, G_h);

    and(P_hl, P_h, P_l);
endmodule
module gp(G_hl, P_hl, G_h, P_h, G_l, P_l);

    output G_hl, P_hl;
    input G_h, P_h, G_l, P_l;

    wire w1;







    and(w1, P_h, G_l);
    or(G_hl, w1, G_h);

    and(P_hl, P_h, P_l);
endmodule