data/full_repos/permissive/509783883/adderSubtractor/addSubTester.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/509783883/adderSubtractor/addSubTester.v:28: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/509783883/adderSubtractor/addSubTester.v:34: Unsupported: Ignoring delay on this delayed statement.\n #50;\n ^\n%Error: data/full_repos/permissive/509783883/adderSubtractor/addSubTester.v:12: Cannot find file containing module: \'eightBitAdderSubtractor\'\neightBitAdderSubtractor uut\n^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/509783883/adderSubtractor,data/full_repos/permissive/509783883/eightBitAdderSubtractor\n             data/full_repos/permissive/509783883/adderSubtractor,data/full_repos/permissive/509783883/eightBitAdderSubtractor.v\n             data/full_repos/permissive/509783883/adderSubtractor,data/full_repos/permissive/509783883/eightBitAdderSubtractor.sv\n             eightBitAdderSubtractor\n             eightBitAdderSubtractor.v\n             eightBitAdderSubtractor.sv\n             obj_dir/eightBitAdderSubtractor\n             obj_dir/eightBitAdderSubtractor.v\n             obj_dir/eightBitAdderSubtractor.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module addSubTester;

reg [7:0] A;
reg [7:0] B;
reg M;

wire [7:0] C;
wire Cout;

eightBitAdderSubtractor uut
(
.A(A),
.B(B),
.M(M),
.Cin(M),
.S(C),
.Cout(Cout)
);

initial
begin
	A = 8'd0;
	B = 8'd0;
	M = 0;
	
	#50;
	
	A = 8'h3A;
	B = 8'h38;
	M = 0;
	
	#50;
	
	M = 1;
end

endmodule
module addSubTester;


reg [7:0] A;
reg [7:0] B;
reg M;

wire [7:0] C;
wire Cout;

eightBitAdderSubtractor uut
(
.A(A),
.B(B),
.M(M),
.Cin(M),
.S(C),
.Cout(Cout)
);

initial
begin
	A = 8'd0;
	B = 8'd0;
	M = 0;
	
	#50;
	
	A = 8'h3A;
	B = 8'h38;
	M = 0;
	
	#50;
	
	M = 1;
end

endmodule