data/full_repos/permissive/47537295/src/super_display.v
1: b'%Warning-WIDTH: data/full_repos/permissive/47537295/src/super_display.v:54: Operator CASE expects 4 bits on the Case expression, but Case expression\'s SEL generates 2 bits.\n                                                                          : ... In instance super_display\n  case (state[1:0])\n  ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/47537295/src/super_display.v:54: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'2\'h0\' generates 2 bits.\n                                                                          : ... In instance super_display\n  case (state[1:0])\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/47537295/src/super_display.v:54: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'2\'h1\' generates 2 bits.\n                                                                          : ... In instance super_display\n  case (state[1:0])\n  ^~~~\n%Warning-WIDTH: data/full_repos/permissive/47537295/src/super_display.v:54: Operator CASE expects 4 bits on the Case Item, but Case Item\'s CONST \'3\'h2\' generates 3 bits.\n                                                                          : ... In instance super_display\n  case (state[1:0])\n  ^~~~\n%Error: data/full_repos/permissive/47537295/src/super_display.v:62: Cannot find file containing module: \'display\'\n display display1(.d (temp_data[3:0]), .c (c[7:0]));\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/47537295/src,data/full_repos/permissive/47537295/display\n             data/full_repos/permissive/47537295/src,data/full_repos/permissive/47537295/display.v\n             data/full_repos/permissive/47537295/src,data/full_repos/permissive/47537295/display.sv\n             display\n             display.v\n             display.sv\n             obj_dir/display\n             obj_dir/display.v\n             obj_dir/display.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n'
module super_display(
    input clk,
    input rst,
	 input [3:0] sel_in,
	 input [15:0] dat,
    output [3:0] sel,
    output [7:0] c
    );

	 integer counter;
	 reg [3:0] temp_data;
	 reg [3:0] temp_sel;
	 reg [1:0] state;
	 parameter freq=10000000;
	 localparam bond=freq/1000;
	always @(posedge clk)
	begin
		if (rst) begin
			counter<=0;
			state <= 0;

		end
		else begin
			counter <= counter+1'b1;
			if (counter == bond) begin
				counter <= 0;
				state <= state + 2'b1;
			end
			
		end
	end
	
	always @(*) begin
		case (state[1:0])
			2'b00: begin temp_sel[3:0] <= 4'b1110; temp_data[3:0] <= dat[3:0]; end
			2'b01: begin temp_sel[3:0] <= 4'b1101; temp_data[3:0] <= dat[7:4]; end
			3'b10: begin temp_sel[3:0] <= 4'b1011; temp_data[3:0] <= dat[11:8]; end
			4'b11: begin temp_sel[3:0] <= 4'b0111; temp_data[3:0] <= dat[15:12]; end
		endcase
	end
	assign sel[3:0] = temp_sel[3:0] | ~sel_in[3:0];
	display display1(.d (temp_data[3:0]), .c (c[7:0]));
endmodule
module super_display(
    input clk,
    input rst,
	 input [3:0] sel_in,
	 input [15:0] dat,
    output [3:0] sel,
    output [7:0] c
    );


	 integer counter;
	 reg [3:0] temp_data;
	 reg [3:0] temp_sel;
	 reg [1:0] state;
	 parameter freq=10000000;
	 localparam bond=freq/1000;
	always @(posedge clk)
	begin
		if (rst) begin
			counter<=0;
			state <= 0;

		end
		else begin
			counter <= counter+1'b1;
			if (counter == bond) begin
				counter <= 0;
				state <= state + 2'b1;
			end
			
		end
	end
	
	always @(*) begin
		case (state[1:0])
			2'b00: begin temp_sel[3:0] <= 4'b1110; temp_data[3:0] <= dat[3:0]; end
			2'b01: begin temp_sel[3:0] <= 4'b1101; temp_data[3:0] <= dat[7:4]; end
			3'b10: begin temp_sel[3:0] <= 4'b1011; temp_data[3:0] <= dat[11:8]; end
			4'b11: begin temp_sel[3:0] <= 4'b0111; temp_data[3:0] <= dat[15:12]; end
		endcase
	end
	assign sel[3:0] = temp_sel[3:0] | ~sel_in[3:0];
	display display1(.d (temp_data[3:0]), .c (c[7:0]));
endmodule