data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_async_edgelogic.v
data/verilator_xmls/6de74e64-68d8-4edf-815e-e38a87421eb1.xml
module dram_async_edgelogic(

   to_pad, 

   data
   );




input			data;




output			to_pad;






wire n0 = data;

assign to_pad  = n0;

endmodule
module dram_async_edgelogic(

   to_pad, 

   data
   );





input			data;




output			to_pad;






wire n0 = data;

assign to_pad  = n0;

endmodule