data/full_repos/permissive/477367510/impl1/source/count.v
data/verilator_xmls/776a281d-9726-4bb8-add7-82770955c7c9.xml
module first_counter(
 clock,
 reset,
 counter_out
 );
 input clock;
 input reset; 

 output [31:0] counter_out;

 wire clock;
 wire reset;

 reg [31:0] counter_out;

 always @ ( posedge clock)
 begin : COUNTER

   if (reset == 1'b1) 
   begin
     counter_out <= #1 32'b0000;
   end
   else
   begin
     counter_out <= #1 counter_out + 1;
   end
 end

endmodule
module first_counter(
 clock,
 reset,
 counter_out
 );

 input clock;
 input reset; 

 output [31:0] counter_out;

 wire clock;
 wire reset;

 reg [31:0] counter_out;

 always @ ( posedge clock)
 begin : COUNTER

   if (reset == 1'b1) 
   begin
     counter_out <= #1 32'b0000;
   end
   else
   begin
     counter_out <= #1 counter_out + 1;
   end
 end

endmodule