data/full_repos/permissive/437632408/NVDLA/nvdla/cacc/NV_NVDLA_CACC_CALC_fp_48b.v
1: b'%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/cacc/NV_NVDLA_CACC_CALC_fp_48b.v:292: Cannot find file containing module: \'DW_lsd\'\nDW_lsd #(.a_width(36 )) u0_dw_lsd(.a(di_mant), .enc(di_lead_num[5:0]), .dec());\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/437632408/NVDLA/nvdla/cacc,data/full_repos/permissive/437632408/DW_lsd\n             data/full_repos/permissive/437632408/NVDLA/nvdla/cacc,data/full_repos/permissive/437632408/DW_lsd.v\n             data/full_repos/permissive/437632408/NVDLA/nvdla/cacc,data/full_repos/permissive/437632408/DW_lsd.sv\n             DW_lsd\n             DW_lsd.v\n             DW_lsd.sv\n             obj_dir/DW_lsd\n             obj_dir/DW_lsd.v\n             obj_dir/DW_lsd.sv\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/cacc/NV_NVDLA_CACC_CALC_fp_48b.v:322: Unsized constant being X/Z extended to 40 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                     : ... In instance NV_NVDLA_CACC_CALC_fp_48b\n    di_aligned_mant <= \'bx;  \n                       ^~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/cacc/NV_NVDLA_CACC_CALC_fp_48b.v:332: Unsized constant being X/Z extended to 40 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                     : ... In instance NV_NVDLA_CACC_CALC_fp_48b\n    oi_aligned_mant <= \'bx;  \n                       ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/cacc/NV_NVDLA_CACC_CALC_fp_48b.v:342: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                                     : ... In instance NV_NVDLA_CACC_CALC_fp_48b\n    in_mant_cut <= \'bx;  \n                ^~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/cacc/NV_NVDLA_CACC_CALC_fp_48b.v:352: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                                     : ... In instance NV_NVDLA_CACC_CALC_fp_48b\n    in_aligned_expo <= \'bx;  \n                    ^~\n%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/cacc/NV_NVDLA_CACC_CALC_fp_48b.v:364: Cannot find file containing module: \'DW_lsd\'\nDW_lsd #(.a_width(40 +4)) u1_dw_lsd(.a(mant_sum_total), .enc(msum_lead_num[5:0]), .dec());\n^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/cacc/NV_NVDLA_CACC_CALC_fp_48b.v:366: Operator SUB expects 32 or 9 bits on the RHS, but RHS\'s VARREF \'msum_lead_num\' generates 6 bits.\n                                                                                                     : ... In instance NV_NVDLA_CACC_CALC_fp_48b\nassign {mon_expo_nrml_c,expo_nrml[7:0]} = in_aligned_expo + 1 - msum_lead_num;\n                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/cacc/NV_NVDLA_CACC_CALC_fp_48b.v:376: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                                     : ... In instance NV_NVDLA_CACC_CALC_fp_48b\n    expo_trans <= \'bx;  \n               ^~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/cacc/NV_NVDLA_CACC_CALC_fp_48b.v:386: Unsized constant being X/Z extended to 42 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                     : ... In instance NV_NVDLA_CACC_CALC_fp_48b\n    mant_sum_trans <= \'bx;  \n                      ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/cacc/NV_NVDLA_CACC_CALC_fp_48b.v:437: Operator ADD expects 41 bits on the RHS, but RHS\'s SIGNED generates 2 bits.\n                                                                                                     : ... In instance NV_NVDLA_CACC_CALC_fp_48b\nassign mant_sum_round[40:0] = $signed(mant_sum_effect) + $signed({1\'b0,mant_sum_point5});\n                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/cacc/NV_NVDLA_CACC_CALC_fp_48b.v:443: Operator SUB expects 9 bits on the RHS, but RHS\'s VARREF \'mant_sum_carry_neg\' generates 1 bits.\n                                                                                                     : ... In instance NV_NVDLA_CACC_CALC_fp_48b\nassign {mon_partial_expo_nmlz_nc,partial_expo_nmlz_neg[7:0]} = expo_trans - mant_sum_carry_neg;\n                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/cacc/NV_NVDLA_CACC_CALC_fp_48b.v:444: Operator ADD expects 9 bits on the RHS, but RHS\'s VARREF \'mant_sum_carry_pos\' generates 1 bits.\n                                                                                                     : ... In instance NV_NVDLA_CACC_CALC_fp_48b\nassign {mon_partial_expo_nmlz_pc,partial_expo_nmlz_pos[7:0]} = expo_trans + mant_sum_carry_pos;\n                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/cacc/NV_NVDLA_CACC_CALC_fp_48b.v:454: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                                     : ... In instance NV_NVDLA_CACC_CALC_fp_48b\n    partial_result_expo <= \'bx;  \n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/cacc/NV_NVDLA_CACC_CALC_fp_48b.v:464: Unsized constant being X/Z extended to 40 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                     : ... In instance NV_NVDLA_CACC_CALC_fp_48b\n    partial_result_mant <= \'bx;  \n                           ^~~\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/cacc/NV_NVDLA_CACC_CALC_fp_48b.v:566: Operator ADD expects 25 bits on the RHS, but RHS\'s VARREF \'fp32_mant_point5\' generates 1 bits.\n                                                                                                     : ... In instance NV_NVDLA_CACC_CALC_fp_48b\nassign fp32_mant_round[24:0] = fp32_mant_effect + fp32_mant_point5;\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/cacc/NV_NVDLA_CACC_CALC_fp_48b.v:568: Operator ADD expects 9 bits on the RHS, but RHS\'s CONST \'7\'h40\' generates 7 bits.\n                                                                                                     : ... In instance NV_NVDLA_CACC_CALC_fp_48b\nassign {mon_fp32_expo_round_c,fp32_expo_round[7:0]} = fp32_expo_raw + 7\'d64 + (fp32_mant_carry | partial_neg2);\n                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/cacc/NV_NVDLA_CACC_CALC_fp_48b.v:568: Operator OR expects 9 bits on the LHS, but LHS\'s VARREF \'fp32_mant_carry\' generates 1 bits.\n                                                                                                     : ... In instance NV_NVDLA_CACC_CALC_fp_48b\nassign {mon_fp32_expo_round_c,fp32_expo_round[7:0]} = fp32_expo_raw + 7\'d64 + (fp32_mant_carry | partial_neg2);\n                                                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/437632408/NVDLA/nvdla/cacc/NV_NVDLA_CACC_CALC_fp_48b.v:568: Operator OR expects 9 bits on the RHS, but RHS\'s VARREF \'partial_neg2\' generates 1 bits.\n                                                                                                     : ... In instance NV_NVDLA_CACC_CALC_fp_48b\nassign {mon_fp32_expo_round_c,fp32_expo_round[7:0]} = fp32_expo_raw + 7\'d64 + (fp32_mant_carry | partial_neg2);\n                                                                                               ^\n%Error: Exiting due to 2 error(s), 16 warning(s)\n'
module NV_NVDLA_CACC_CALC_fp_48b (
   nvdla_core_clk
  ,nvdla_core_rstn
  ,in_data
  ,in_op
  ,in_op_valid
  ,in_sel
  ,in_valid
  ,out_final_data
  ,out_final_valid
  ,out_partial_data
  ,out_partial_valid
  );
input [43:0] in_data;
input [47:0] in_op;
input in_op_valid;
input in_sel;
input in_valid;
output [31:0] out_final_data;
output out_final_valid;
output [47:0] out_partial_data;
output out_partial_valid;
input nvdla_core_clk;
input nvdla_core_rstn;
reg [39:0] di_aligned_mant;
reg [7:0] expo_trans;
reg final_sel;
reg final_vld;
reg [7:0] in_aligned_expo;
reg [2:0] in_mant_cut;
reg in_nan_2d;
reg in_nan_d;
reg [41:0] mant_sum_trans;
reg msum_sel;
reg msum_vld;
reg [39:0] oi_aligned_mant;
reg [31:0] out_final_data;
reg out_final_valid;
reg out_partial_valid;
reg [7:0] partial_result_expo;
reg [39:0] partial_result_mant;
reg shift_sel;
reg shift_vld;
wire [39:0] di_aligned_mant_nxt;
wire [6:0] di_expm;
wire [5:0] di_expn;
wire [7:0] di_expo;
wire [7:0] di_expo_shift;
wire [5:0] di_lead_num;
wire [35:0] di_manm;
wire [35:0] di_mans;
wire [35:0] di_mant;
wire [2:0] di_mant_cut;
wire [39:0] di_mant_cutt;
wire [39:0] di_mant_ext;
wire [37:0] di_mant_pre;
wire [39:0] di_mant_shift;
wire di_nan;
wire [43:0] di_pd;
wire di_sign;
wire di_zero;
wire [7:0] expo_nrml;
wire [7:0] fp32_expo_nmlz;
wire [7:0] fp32_expo_raw;
wire [7:0] fp32_expo_round;
wire fp32_mant_carry;
wire [14:0] fp32_mant_cut;
wire [23:0] fp32_mant_effect;
wire [22:0] fp32_mant_nmlz;
wire [24:0] fp32_mant_nmlz_tmp;
wire fp32_mant_point5;
wire [24:0] fp32_mant_round;
wire [31:0] fp32_result;
wire [2:0] in_mant_cut_nxt;
wire [47:0] in_mask_op;
wire in_nan;
wire [40:0] mant_sum;
wire mant_sum_carry_neg;
wire mant_sum_carry_pos;
wire [44:0] mant_sum_comp;
wire [39:0] mant_sum_effect;
wire mant_sum_guard;
wire [41:0] mant_sum_ncmp;
wire mant_sum_point5;
wire [40:0] mant_sum_round;
wire [44:0] mant_sum_scmp;
wire mant_sum_sign;
wire mant_sum_stick;
wire [43:0] mant_sum_total;
wire [7:0] max_expo;
wire mon_di_expo_shift_c;
wire mon_expo_nrml_c;
wire mon_fp32_expo_round_c;
wire mon_oi_expo_shift_c;
wire mon_partial_expo_nmlz_nc;
wire mon_partial_expo_nmlz_pc;
wire [5:0] msum_lead_num;
wire [39:0] oi_aligned_mant_nxt;
wire [7:0] oi_expn;
wire [7:0] oi_expo;
wire [7:0] oi_expo_shift;
wire [39:0] oi_mans;
wire [39:0] oi_mant;
wire [2:0] oi_mant_cut;
wire [39:0] oi_mant_cutt;
wire [39:0] oi_mant_ext;
wire [39:0] oi_mant_shift;
wire oi_nan;
wire [47:0] oi_pd;
wire oi_sign;
wire oi_zero;
wire [7:0] partial_expo;
wire [7:0] partial_expo_nmlz;
wire [7:0] partial_expo_nmlz_neg;
wire [7:0] partial_expo_nmlz_pos;
wire [7:0] partial_expo_nxt;
wire [39:0] partial_mant;
wire [38:0] partial_mant_abs;
wire [39:0] partial_mant_nmlz;
wire [40:0] partial_mant_nmlz_tmp;
wire [39:0] partial_mant_nxt;
wire partial_mant_zero;
wire partial_nan;
wire partial_neg2;
wire [47:0] partial_result;
wire [47:0] partial_result_out;
wire partial_sign;
wire [38:0] partial_umant;
wire [9:0] partial_umant_nan;
wire partial_zero;











`ifdef DESIGNWARE_NOEXIST
NV_DW_lsd #(.a_width(36 )) u0_dw_lsd(.a(di_mant), .enc(di_lead_num[5:0]), .dec());
`else
DW_lsd #(.a_width(36 )) u0_dw_lsd(.a(di_mant), .enc(di_lead_num[5:0]), .dec());
`endif
assign di_expm[6:0] = di_expn + 6'd47 - di_lead_num;
assign di_manm[35:0] = ($signed(di_mant)) <<< di_lead_num;
assign di_mans[35:0] = oi_nan ? {36'b0} : di_nan ? {di_mant_pre[37:27],25'b0} : di_manm;
assign oi_mans[39:0] = oi_nan ? {oi_mant[39:29],29'b0} : di_nan ? {40'b0} : oi_mant;
assign di_expo = in_nan ? {8{1'b1}} : di_zero ? {8'b0} : ({{1{1'b0}}, di_expm});
assign oi_expo = in_nan ? {8{1'b1}} : oi_zero ? {8'b0} : (oi_expn);

assign max_expo[7:0] = (di_expo > oi_expo) ? di_expo : oi_expo;

assign {mon_di_expo_shift_c, di_expo_shift[7:0]} = max_expo - di_expo;
assign {mon_oi_expo_shift_c, oi_expo_shift[7:0]} = max_expo - oi_expo;

assign di_mant_ext[39:0] = {di_mans,{4{1'b0}}};
assign oi_mant_ext[39:0] = oi_mans;

assign {di_mant_shift[39:0],di_mant_cutt[39:0]} = ($signed({di_mant_ext,{40'b0}})) >>> di_expo_shift;
assign {oi_mant_shift[39:0],oi_mant_cutt[39:0]} = ($signed({oi_mant_ext,{40'b0}})) >>> oi_expo_shift;
assign di_aligned_mant_nxt = (di_expo_shift >= 40 ) ? {40{di_sign}} : di_mant_shift;
assign oi_aligned_mant_nxt = (oi_expo_shift >= 40 ) ? {40{oi_sign}} : oi_mant_shift;
assign di_mant_cut = {di_mant_cutt[39:38],|di_mant_cutt[37:0]};
assign oi_mant_cut = {oi_mant_cutt[39:38],|oi_mant_cutt[37:0]};
assign in_mant_cut_nxt = (di_expo > oi_expo) ? oi_mant_cut : (di_expo < oi_expo) ? di_mant_cut : 3'b0;
always @(posedge nvdla_core_clk) begin
  if ((in_valid) == 1'b1) begin
    di_aligned_mant <= di_aligned_mant_nxt;

  end else if ((in_valid) == 1'b0) begin
  end else begin
    di_aligned_mant <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((in_valid) == 1'b1) begin
    oi_aligned_mant <= oi_aligned_mant_nxt;

  end else if ((in_valid) == 1'b0) begin
  end else begin
    oi_aligned_mant <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((in_valid & ~in_nan) == 1'b1) begin
    in_mant_cut <= in_mant_cut_nxt;

  end else if ((in_valid & ~in_nan) == 1'b0) begin
  end else begin
    in_mant_cut <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((in_valid & ~in_nan) == 1'b1) begin
    in_aligned_expo <= max_expo;

  end else if ((in_valid & ~in_nan) == 1'b0) begin
  end else begin
    in_aligned_expo <= 'bx;

  end
end



assign mant_sum[40:0] = $signed(di_aligned_mant) + $signed(oi_aligned_mant);
assign mant_sum_total[43:0] = {mant_sum,in_mant_cut};
`ifdef DESIGNWARE_NOEXIST
NV_DW_lsd #(.a_width(40 +4)) u1_dw_lsd(.a(mant_sum_total), .enc(msum_lead_num[5:0]), .dec());
`else
DW_lsd #(.a_width(40 +4)) u1_dw_lsd(.a(mant_sum_total), .enc(msum_lead_num[5:0]), .dec());
`endif
assign {mon_expo_nrml_c,expo_nrml[7:0]} = in_aligned_expo + 1 - msum_lead_num;
assign mant_sum_comp[44:0] = {mant_sum_total,1'b0};
assign mant_sum_scmp[44:0] = |msum_lead_num ? ($signed(mant_sum_comp)) <<< (msum_lead_num-1) : ($signed(mant_sum_comp)) >>> 1;
assign mant_sum_ncmp[41:0] = in_nan_d ? {mant_sum[39:0],2'b0} : {mant_sum_scmp[43:3],|mant_sum_scmp[2:0]};
always @(posedge nvdla_core_clk) begin
  if ((shift_vld & ~in_nan_d) == 1'b1) begin
    expo_trans <= expo_nrml;

  end else if ((shift_vld & ~in_nan_d) == 1'b0) begin
  end else begin
    expo_trans <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((shift_vld) == 1'b1) begin
    mant_sum_trans <= mant_sum_ncmp[41:0];

  end else if ((shift_vld) == 1'b0) begin
  end else begin
    mant_sum_trans <= 'bx;

  end
end
assign mant_sum_sign = mant_sum_trans[40 +1];
assign mant_sum_effect = mant_sum_trans[41:2];
assign mant_sum_guard = mant_sum_trans[1];
assign mant_sum_stick = mant_sum_trans[0];

`ifndef DISABLE_FUNCPOINT
  `ifdef ENABLE_FUNCPOINT
    property cacc_calc_fp48__mant_sum_zero__4_cov;
        disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
        @(posedge nvdla_core_clk)
        (~(|mant_sum));
    endproperty

    FUNCPOINT_cacc_calc_fp48__mant_sum_zero__4_COV : cover property (cacc_calc_fp48__mant_sum_zero__4_cov);
  `endif
`endif


`ifndef DISABLE_FUNCPOINT
  `ifdef ENABLE_FUNCPOINT
    property cacc_calc_fp48__mant_sum_carry__5_cov;
        disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
        @(posedge nvdla_core_clk)
        (mant_sum[40 ]);
    endproperty

    FUNCPOINT_cacc_calc_fp48__mant_sum_carry__5_COV : cover property (cacc_calc_fp48__mant_sum_carry__5_cov);
  `endif
`endif


`ifndef DISABLE_FUNCPOINT
  `ifdef ENABLE_FUNCPOINT
    property cacc_calc_fp48__mant_sum_little__6_cov;
        disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
        @(posedge nvdla_core_clk)
        (msum_lead_num>=6'h4);
    endproperty

    FUNCPOINT_cacc_calc_fp48__mant_sum_little__6_COV : cover property (cacc_calc_fp48__mant_sum_little__6_cov);
  `endif
`endif




assign mant_sum_point5 = mant_sum_guard & (~mant_sum_sign | mant_sum_stick);
assign mant_sum_round[40:0] = $signed(mant_sum_effect) + $signed({1'b0,mant_sum_point5});
assign mant_sum_carry_pos = ~mant_sum_sign & (&mant_sum_effect[38:0]) & mant_sum_point5;
assign mant_sum_carry_neg = mant_sum_sign & ~mant_sum_effect[40 -2] & (&mant_sum_effect[37:0]) & mant_sum_point5;
assign partial_mant_nmlz_tmp[40:0] = mant_sum_carry_neg ? {mant_sum_round[39:0], 1'b0} : ($signed(mant_sum_round)) >>> mant_sum_carry_pos;
assign partial_mant_nmlz[39:0] = partial_mant_nmlz_tmp[39:0];
assign partial_mant_zero = ~(|partial_mant_nmlz);
assign {mon_partial_expo_nmlz_nc,partial_expo_nmlz_neg[7:0]} = expo_trans - mant_sum_carry_neg;
assign {mon_partial_expo_nmlz_pc,partial_expo_nmlz_pos[7:0]} = expo_trans + mant_sum_carry_pos;
assign partial_expo_nmlz[7:0] = mant_sum_carry_neg ? partial_expo_nmlz_neg : partial_expo_nmlz_pos;
assign partial_expo_nxt[7:0] = in_nan_2d ? {8{1'b1}} : partial_mant_zero ? {8'b0} : (partial_expo_nmlz);
assign partial_mant_nxt[39:0] = partial_mant_nmlz;
always @(posedge nvdla_core_clk) begin
  if ((msum_vld) == 1'b1) begin
    partial_result_expo <= partial_expo_nxt;

  end else if ((msum_vld) == 1'b0) begin
  end else begin
    partial_result_expo <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((msum_vld) == 1'b1) begin
    partial_result_mant <= partial_mant_nxt;

  end else if ((msum_vld) == 1'b0) begin
  end else begin
    partial_result_mant <= 'bx;

  end
end
assign partial_result_out = {partial_result_expo,partial_result_mant};
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    out_partial_valid <= 1'b0;
  end else begin
  out_partial_valid <= msum_vld & ~msum_sel;
  end
end
assign out_partial_data = partial_result_out;
assign partial_result = final_sel & final_vld ? partial_result_out : 0;
assign partial_sign = partial_result[40 -1];
assign partial_mant[39:0] = partial_result[39:0];
assign partial_umant[38:0] = partial_result[38:0];
assign partial_umant_nan[9:0] = partial_result[38:29];
assign partial_expo[7:0] = partial_result[47:40];
assign partial_neg2 = partial_sign & ~(|partial_umant);
assign partial_nan = &partial_expo;
assign partial_zero = ~(|partial_mant);

`ifndef DISABLE_FUNCPOINT
  `ifdef ENABLE_FUNCPOINT
    property cacc_calc_fp48__mant_sum_round_carry_pos__7_cov;
        disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
        @(posedge nvdla_core_clk)
        mant_sum_carry_pos;
    endproperty

    FUNCPOINT_cacc_calc_fp48__mant_sum_round_carry_pos__7_COV : cover property (cacc_calc_fp48__mant_sum_round_carry_pos__7_cov);
  `endif
`endif


`ifndef DISABLE_FUNCPOINT
  `ifdef ENABLE_FUNCPOINT
    property cacc_calc_fp48__mant_sum_round_carry_neg__8_cov;
        disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
        @(posedge nvdla_core_clk)
        mant_sum_carry_neg;
    endproperty

    FUNCPOINT_cacc_calc_fp48__mant_sum_round_carry_neg__8_COV : cover property (cacc_calc_fp48__mant_sum_round_carry_neg__8_cov);
  `endif
`endif


`ifndef DISABLE_FUNCPOINT
  `ifdef ENABLE_FUNCPOINT
    property cacc_calc_fp48__partial_sum_zero__9_cov;
        disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
        @(posedge nvdla_core_clk)
        partial_zero;
    endproperty

    FUNCPOINT_cacc_calc_fp48__partial_sum_zero__9_COV : cover property (cacc_calc_fp48__partial_sum_zero__9_cov);
  `endif
`endif


`ifndef DISABLE_FUNCPOINT
  `ifdef ENABLE_FUNCPOINT
    property cacc_calc_fp48__partial_sum_nan__10_cov;
        disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
        @(posedge nvdla_core_clk)
        partial_nan;
    endproperty

    FUNCPOINT_cacc_calc_fp48__partial_sum_nan__10_COV : cover property (cacc_calc_fp48__partial_sum_nan__10_cov);
  `endif
`endif


`ifndef DISABLE_FUNCPOINT
  `ifdef ENABLE_FUNCPOINT
    property cacc_calc_fp48__partial_sum_neg2__11_cov;
        disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
        @(posedge nvdla_core_clk)
        partial_neg2;
    endproperty

    FUNCPOINT_cacc_calc_fp48__partial_sum_neg2__11_COV : cover property (cacc_calc_fp48__partial_sum_neg2__11_cov);
  `endif
`endif









assign partial_mant_abs[38:0] = partial_sign ? (~partial_umant+1) : partial_umant;
assign fp32_mant_cut = partial_mant_abs[14:0];
assign fp32_mant_effect = partial_mant_abs[38:15];
assign fp32_expo_raw = partial_expo;

assign fp32_mant_point5 = fp32_mant_cut[15 -1];
assign fp32_mant_carry = (&fp32_mant_effect) & fp32_mant_point5;
assign fp32_mant_round[24:0] = fp32_mant_effect + fp32_mant_point5;
assign fp32_mant_nmlz_tmp[24:0] = ($signed(fp32_mant_round)) >>> fp32_mant_carry;
assign {mon_fp32_expo_round_c,fp32_expo_round[7:0]} = fp32_expo_raw + 7'd64 + (fp32_mant_carry | partial_neg2);
assign fp32_mant_nmlz[22:0] = partial_nan ? {{13'b0},partial_umant_nan} : fp32_mant_nmlz_tmp[22:0];
assign fp32_expo_nmlz = partial_zero ? {8'b0} : partial_nan ? {8{1'b1}} : fp32_expo_round;
assign fp32_result = {partial_sign,fp32_expo_nmlz,fp32_mant_nmlz};
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    out_final_valid <= 1'b0;
  end else begin
  out_final_valid <= final_vld & final_sel;
  end
end
always @(posedge nvdla_core_clk) begin
  if ((final_vld & final_sel) == 1'b1) begin
    out_final_data <= fp32_result;

  end else if ((final_vld & final_sel) == 1'b0) begin
  end else begin
    out_final_data <= 'bx;

  end
end

`ifndef DISABLE_FUNCPOINT
  `ifdef ENABLE_FUNCPOINT
    property cacc_calc_fp48__fp32_mant_carry__12_cov;
        disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
        @(posedge nvdla_core_clk)
        fp32_mant_carry;
    endproperty

    FUNCPOINT_cacc_calc_fp48__fp32_mant_carry__12_COV : cover property (cacc_calc_fp48__fp32_mant_carry__12_cov);
  `endif
`endif


`ifndef DISABLE_FUNCPOINT
  `ifdef ENABLE_FUNCPOINT
    property cacc_calc_fp48__fp32_mant_zero__13_cov;
        disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
        @(posedge nvdla_core_clk)
        ~(|fp32_mant_nmlz);
    endproperty

    FUNCPOINT_cacc_calc_fp48__fp32_mant_zero__13_COV : cover property (cacc_calc_fp48__fp32_mant_zero__13_cov);
  `endif
`endif


`ifndef DISABLE_FUNCPOINT
  `ifdef ENABLE_FUNCPOINT
    property cacc_calc_fp48__fp32_mant_nan__14_cov;
        disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
        @(posedge nvdla_core_clk)
        &fp32_expo_nmlz;
    endproperty

    FUNCPOINT_cacc_calc_fp48__fp32_mant_nan__14_COV : cover property (cacc_calc_fp48__fp32_mant_nan__14_cov);
  `endif
`endif

`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_never #(0,0,"Error! in_data_44b highest three bits is not same!") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, (in_valid & ~di_nan & ~(di_mant_pre[37:35]==3'b111 || di_mant_pre[37:35]==3'b0)));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_never #(0,0,"Error! in_data_44b is illegal,NAN and zero happen simultaneously!") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (in_valid & di_nan & di_zero));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_never #(0,0,"Error! in_op_48b is illegal,NAN and zero happen simultaneously!") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (in_valid & oi_nan & oi_zero));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_never #(0,0,"Error! out partial sum is not normalized!") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, (final_vld & ~partial_nan & ~partial_zero & ~(partial_mant[40 -1]^partial_mant[40 -2])));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_never #(0,0,"Error! out fp32 is not illegal!") zzz_assert_never_5x (nvdla_core_clk, `ASSERT_RESET, (final_vld & final_sel & (~(|fp32_expo_nmlz) & (|fp32_mant_nmlz) || (&fp32_expo_nmlz) & ~(|fp32_mant_nmlz))));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
endmodule
module NV_NVDLA_CACC_CALC_fp_48b (
   nvdla_core_clk
  ,nvdla_core_rstn
  ,in_data
  ,in_op
  ,in_op_valid
  ,in_sel
  ,in_valid
  ,out_final_data
  ,out_final_valid
  ,out_partial_data
  ,out_partial_valid
  );

input [43:0] in_data;
input [47:0] in_op;
input in_op_valid;
input in_sel;
input in_valid;
output [31:0] out_final_data;
output out_final_valid;
output [47:0] out_partial_data;
output out_partial_valid;
input nvdla_core_clk;
input nvdla_core_rstn;
reg [39:0] di_aligned_mant;
reg [7:0] expo_trans;
reg final_sel;
reg final_vld;
reg [7:0] in_aligned_expo;
reg [2:0] in_mant_cut;
reg in_nan_2d;
reg in_nan_d;
reg [41:0] mant_sum_trans;
reg msum_sel;
reg msum_vld;
reg [39:0] oi_aligned_mant;
reg [31:0] out_final_data;
reg out_final_valid;
reg out_partial_valid;
reg [7:0] partial_result_expo;
reg [39:0] partial_result_mant;
reg shift_sel;
reg shift_vld;
wire [39:0] di_aligned_mant_nxt;
wire [6:0] di_expm;
wire [5:0] di_expn;
wire [7:0] di_expo;
wire [7:0] di_expo_shift;
wire [5:0] di_lead_num;
wire [35:0] di_manm;
wire [35:0] di_mans;
wire [35:0] di_mant;
wire [2:0] di_mant_cut;
wire [39:0] di_mant_cutt;
wire [39:0] di_mant_ext;
wire [37:0] di_mant_pre;
wire [39:0] di_mant_shift;
wire di_nan;
wire [43:0] di_pd;
wire di_sign;
wire di_zero;
wire [7:0] expo_nrml;
wire [7:0] fp32_expo_nmlz;
wire [7:0] fp32_expo_raw;
wire [7:0] fp32_expo_round;
wire fp32_mant_carry;
wire [14:0] fp32_mant_cut;
wire [23:0] fp32_mant_effect;
wire [22:0] fp32_mant_nmlz;
wire [24:0] fp32_mant_nmlz_tmp;
wire fp32_mant_point5;
wire [24:0] fp32_mant_round;
wire [31:0] fp32_result;
wire [2:0] in_mant_cut_nxt;
wire [47:0] in_mask_op;
wire in_nan;
wire [40:0] mant_sum;
wire mant_sum_carry_neg;
wire mant_sum_carry_pos;
wire [44:0] mant_sum_comp;
wire [39:0] mant_sum_effect;
wire mant_sum_guard;
wire [41:0] mant_sum_ncmp;
wire mant_sum_point5;
wire [40:0] mant_sum_round;
wire [44:0] mant_sum_scmp;
wire mant_sum_sign;
wire mant_sum_stick;
wire [43:0] mant_sum_total;
wire [7:0] max_expo;
wire mon_di_expo_shift_c;
wire mon_expo_nrml_c;
wire mon_fp32_expo_round_c;
wire mon_oi_expo_shift_c;
wire mon_partial_expo_nmlz_nc;
wire mon_partial_expo_nmlz_pc;
wire [5:0] msum_lead_num;
wire [39:0] oi_aligned_mant_nxt;
wire [7:0] oi_expn;
wire [7:0] oi_expo;
wire [7:0] oi_expo_shift;
wire [39:0] oi_mans;
wire [39:0] oi_mant;
wire [2:0] oi_mant_cut;
wire [39:0] oi_mant_cutt;
wire [39:0] oi_mant_ext;
wire [39:0] oi_mant_shift;
wire oi_nan;
wire [47:0] oi_pd;
wire oi_sign;
wire oi_zero;
wire [7:0] partial_expo;
wire [7:0] partial_expo_nmlz;
wire [7:0] partial_expo_nmlz_neg;
wire [7:0] partial_expo_nmlz_pos;
wire [7:0] partial_expo_nxt;
wire [39:0] partial_mant;
wire [38:0] partial_mant_abs;
wire [39:0] partial_mant_nmlz;
wire [40:0] partial_mant_nmlz_tmp;
wire [39:0] partial_mant_nxt;
wire partial_mant_zero;
wire partial_nan;
wire partial_neg2;
wire [47:0] partial_result;
wire [47:0] partial_result_out;
wire partial_sign;
wire [38:0] partial_umant;
wire [9:0] partial_umant_nan;
wire partial_zero;











`ifdef DESIGNWARE_NOEXIST
NV_DW_lsd #(.a_width(36 )) u0_dw_lsd(.a(di_mant), .enc(di_lead_num[5:0]), .dec());
`else
DW_lsd #(.a_width(36 )) u0_dw_lsd(.a(di_mant), .enc(di_lead_num[5:0]), .dec());
`endif
assign di_expm[6:0] = di_expn + 6'd47 - di_lead_num;
assign di_manm[35:0] = ($signed(di_mant)) <<< di_lead_num;
assign di_mans[35:0] = oi_nan ? {36'b0} : di_nan ? {di_mant_pre[37:27],25'b0} : di_manm;
assign oi_mans[39:0] = oi_nan ? {oi_mant[39:29],29'b0} : di_nan ? {40'b0} : oi_mant;
assign di_expo = in_nan ? {8{1'b1}} : di_zero ? {8'b0} : ({{1{1'b0}}, di_expm});
assign oi_expo = in_nan ? {8{1'b1}} : oi_zero ? {8'b0} : (oi_expn);

assign max_expo[7:0] = (di_expo > oi_expo) ? di_expo : oi_expo;

assign {mon_di_expo_shift_c, di_expo_shift[7:0]} = max_expo - di_expo;
assign {mon_oi_expo_shift_c, oi_expo_shift[7:0]} = max_expo - oi_expo;

assign di_mant_ext[39:0] = {di_mans,{4{1'b0}}};
assign oi_mant_ext[39:0] = oi_mans;

assign {di_mant_shift[39:0],di_mant_cutt[39:0]} = ($signed({di_mant_ext,{40'b0}})) >>> di_expo_shift;
assign {oi_mant_shift[39:0],oi_mant_cutt[39:0]} = ($signed({oi_mant_ext,{40'b0}})) >>> oi_expo_shift;
assign di_aligned_mant_nxt = (di_expo_shift >= 40 ) ? {40{di_sign}} : di_mant_shift;
assign oi_aligned_mant_nxt = (oi_expo_shift >= 40 ) ? {40{oi_sign}} : oi_mant_shift;
assign di_mant_cut = {di_mant_cutt[39:38],|di_mant_cutt[37:0]};
assign oi_mant_cut = {oi_mant_cutt[39:38],|oi_mant_cutt[37:0]};
assign in_mant_cut_nxt = (di_expo > oi_expo) ? oi_mant_cut : (di_expo < oi_expo) ? di_mant_cut : 3'b0;
always @(posedge nvdla_core_clk) begin
  if ((in_valid) == 1'b1) begin
    di_aligned_mant <= di_aligned_mant_nxt;

  end else if ((in_valid) == 1'b0) begin
  end else begin
    di_aligned_mant <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((in_valid) == 1'b1) begin
    oi_aligned_mant <= oi_aligned_mant_nxt;

  end else if ((in_valid) == 1'b0) begin
  end else begin
    oi_aligned_mant <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((in_valid & ~in_nan) == 1'b1) begin
    in_mant_cut <= in_mant_cut_nxt;

  end else if ((in_valid & ~in_nan) == 1'b0) begin
  end else begin
    in_mant_cut <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((in_valid & ~in_nan) == 1'b1) begin
    in_aligned_expo <= max_expo;

  end else if ((in_valid & ~in_nan) == 1'b0) begin
  end else begin
    in_aligned_expo <= 'bx;

  end
end



assign mant_sum[40:0] = $signed(di_aligned_mant) + $signed(oi_aligned_mant);
assign mant_sum_total[43:0] = {mant_sum,in_mant_cut};
`ifdef DESIGNWARE_NOEXIST
NV_DW_lsd #(.a_width(40 +4)) u1_dw_lsd(.a(mant_sum_total), .enc(msum_lead_num[5:0]), .dec());
`else
DW_lsd #(.a_width(40 +4)) u1_dw_lsd(.a(mant_sum_total), .enc(msum_lead_num[5:0]), .dec());
`endif
assign {mon_expo_nrml_c,expo_nrml[7:0]} = in_aligned_expo + 1 - msum_lead_num;
assign mant_sum_comp[44:0] = {mant_sum_total,1'b0};
assign mant_sum_scmp[44:0] = |msum_lead_num ? ($signed(mant_sum_comp)) <<< (msum_lead_num-1) : ($signed(mant_sum_comp)) >>> 1;
assign mant_sum_ncmp[41:0] = in_nan_d ? {mant_sum[39:0],2'b0} : {mant_sum_scmp[43:3],|mant_sum_scmp[2:0]};
always @(posedge nvdla_core_clk) begin
  if ((shift_vld & ~in_nan_d) == 1'b1) begin
    expo_trans <= expo_nrml;

  end else if ((shift_vld & ~in_nan_d) == 1'b0) begin
  end else begin
    expo_trans <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((shift_vld) == 1'b1) begin
    mant_sum_trans <= mant_sum_ncmp[41:0];

  end else if ((shift_vld) == 1'b0) begin
  end else begin
    mant_sum_trans <= 'bx;

  end
end
assign mant_sum_sign = mant_sum_trans[40 +1];
assign mant_sum_effect = mant_sum_trans[41:2];
assign mant_sum_guard = mant_sum_trans[1];
assign mant_sum_stick = mant_sum_trans[0];

`ifndef DISABLE_FUNCPOINT
  `ifdef ENABLE_FUNCPOINT
    property cacc_calc_fp48__mant_sum_zero__4_cov;
        disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
        @(posedge nvdla_core_clk)
        (~(|mant_sum));
    endproperty

    FUNCPOINT_cacc_calc_fp48__mant_sum_zero__4_COV : cover property (cacc_calc_fp48__mant_sum_zero__4_cov);
  `endif
`endif


`ifndef DISABLE_FUNCPOINT
  `ifdef ENABLE_FUNCPOINT
    property cacc_calc_fp48__mant_sum_carry__5_cov;
        disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
        @(posedge nvdla_core_clk)
        (mant_sum[40 ]);
    endproperty

    FUNCPOINT_cacc_calc_fp48__mant_sum_carry__5_COV : cover property (cacc_calc_fp48__mant_sum_carry__5_cov);
  `endif
`endif


`ifndef DISABLE_FUNCPOINT
  `ifdef ENABLE_FUNCPOINT
    property cacc_calc_fp48__mant_sum_little__6_cov;
        disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
        @(posedge nvdla_core_clk)
        (msum_lead_num>=6'h4);
    endproperty

    FUNCPOINT_cacc_calc_fp48__mant_sum_little__6_COV : cover property (cacc_calc_fp48__mant_sum_little__6_cov);
  `endif
`endif




assign mant_sum_point5 = mant_sum_guard & (~mant_sum_sign | mant_sum_stick);
assign mant_sum_round[40:0] = $signed(mant_sum_effect) + $signed({1'b0,mant_sum_point5});
assign mant_sum_carry_pos = ~mant_sum_sign & (&mant_sum_effect[38:0]) & mant_sum_point5;
assign mant_sum_carry_neg = mant_sum_sign & ~mant_sum_effect[40 -2] & (&mant_sum_effect[37:0]) & mant_sum_point5;
assign partial_mant_nmlz_tmp[40:0] = mant_sum_carry_neg ? {mant_sum_round[39:0], 1'b0} : ($signed(mant_sum_round)) >>> mant_sum_carry_pos;
assign partial_mant_nmlz[39:0] = partial_mant_nmlz_tmp[39:0];
assign partial_mant_zero = ~(|partial_mant_nmlz);
assign {mon_partial_expo_nmlz_nc,partial_expo_nmlz_neg[7:0]} = expo_trans - mant_sum_carry_neg;
assign {mon_partial_expo_nmlz_pc,partial_expo_nmlz_pos[7:0]} = expo_trans + mant_sum_carry_pos;
assign partial_expo_nmlz[7:0] = mant_sum_carry_neg ? partial_expo_nmlz_neg : partial_expo_nmlz_pos;
assign partial_expo_nxt[7:0] = in_nan_2d ? {8{1'b1}} : partial_mant_zero ? {8'b0} : (partial_expo_nmlz);
assign partial_mant_nxt[39:0] = partial_mant_nmlz;
always @(posedge nvdla_core_clk) begin
  if ((msum_vld) == 1'b1) begin
    partial_result_expo <= partial_expo_nxt;

  end else if ((msum_vld) == 1'b0) begin
  end else begin
    partial_result_expo <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((msum_vld) == 1'b1) begin
    partial_result_mant <= partial_mant_nxt;

  end else if ((msum_vld) == 1'b0) begin
  end else begin
    partial_result_mant <= 'bx;

  end
end
assign partial_result_out = {partial_result_expo,partial_result_mant};
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    out_partial_valid <= 1'b0;
  end else begin
  out_partial_valid <= msum_vld & ~msum_sel;
  end
end
assign out_partial_data = partial_result_out;
assign partial_result = final_sel & final_vld ? partial_result_out : 0;
assign partial_sign = partial_result[40 -1];
assign partial_mant[39:0] = partial_result[39:0];
assign partial_umant[38:0] = partial_result[38:0];
assign partial_umant_nan[9:0] = partial_result[38:29];
assign partial_expo[7:0] = partial_result[47:40];
assign partial_neg2 = partial_sign & ~(|partial_umant);
assign partial_nan = &partial_expo;
assign partial_zero = ~(|partial_mant);

`ifndef DISABLE_FUNCPOINT
  `ifdef ENABLE_FUNCPOINT
    property cacc_calc_fp48__mant_sum_round_carry_pos__7_cov;
        disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
        @(posedge nvdla_core_clk)
        mant_sum_carry_pos;
    endproperty

    FUNCPOINT_cacc_calc_fp48__mant_sum_round_carry_pos__7_COV : cover property (cacc_calc_fp48__mant_sum_round_carry_pos__7_cov);
  `endif
`endif


`ifndef DISABLE_FUNCPOINT
  `ifdef ENABLE_FUNCPOINT
    property cacc_calc_fp48__mant_sum_round_carry_neg__8_cov;
        disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
        @(posedge nvdla_core_clk)
        mant_sum_carry_neg;
    endproperty

    FUNCPOINT_cacc_calc_fp48__mant_sum_round_carry_neg__8_COV : cover property (cacc_calc_fp48__mant_sum_round_carry_neg__8_cov);
  `endif
`endif


`ifndef DISABLE_FUNCPOINT
  `ifdef ENABLE_FUNCPOINT
    property cacc_calc_fp48__partial_sum_zero__9_cov;
        disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
        @(posedge nvdla_core_clk)
        partial_zero;
    endproperty

    FUNCPOINT_cacc_calc_fp48__partial_sum_zero__9_COV : cover property (cacc_calc_fp48__partial_sum_zero__9_cov);
  `endif
`endif


`ifndef DISABLE_FUNCPOINT
  `ifdef ENABLE_FUNCPOINT
    property cacc_calc_fp48__partial_sum_nan__10_cov;
        disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
        @(posedge nvdla_core_clk)
        partial_nan;
    endproperty

    FUNCPOINT_cacc_calc_fp48__partial_sum_nan__10_COV : cover property (cacc_calc_fp48__partial_sum_nan__10_cov);
  `endif
`endif


`ifndef DISABLE_FUNCPOINT
  `ifdef ENABLE_FUNCPOINT
    property cacc_calc_fp48__partial_sum_neg2__11_cov;
        disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
        @(posedge nvdla_core_clk)
        partial_neg2;
    endproperty

    FUNCPOINT_cacc_calc_fp48__partial_sum_neg2__11_COV : cover property (cacc_calc_fp48__partial_sum_neg2__11_cov);
  `endif
`endif









assign partial_mant_abs[38:0] = partial_sign ? (~partial_umant+1) : partial_umant;
assign fp32_mant_cut = partial_mant_abs[14:0];
assign fp32_mant_effect = partial_mant_abs[38:15];
assign fp32_expo_raw = partial_expo;

assign fp32_mant_point5 = fp32_mant_cut[15 -1];
assign fp32_mant_carry = (&fp32_mant_effect) & fp32_mant_point5;
assign fp32_mant_round[24:0] = fp32_mant_effect + fp32_mant_point5;
assign fp32_mant_nmlz_tmp[24:0] = ($signed(fp32_mant_round)) >>> fp32_mant_carry;
assign {mon_fp32_expo_round_c,fp32_expo_round[7:0]} = fp32_expo_raw + 7'd64 + (fp32_mant_carry | partial_neg2);
assign fp32_mant_nmlz[22:0] = partial_nan ? {{13'b0},partial_umant_nan} : fp32_mant_nmlz_tmp[22:0];
assign fp32_expo_nmlz = partial_zero ? {8'b0} : partial_nan ? {8{1'b1}} : fp32_expo_round;
assign fp32_result = {partial_sign,fp32_expo_nmlz,fp32_mant_nmlz};
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    out_final_valid <= 1'b0;
  end else begin
  out_final_valid <= final_vld & final_sel;
  end
end
always @(posedge nvdla_core_clk) begin
  if ((final_vld & final_sel) == 1'b1) begin
    out_final_data <= fp32_result;

  end else if ((final_vld & final_sel) == 1'b0) begin
  end else begin
    out_final_data <= 'bx;

  end
end

`ifndef DISABLE_FUNCPOINT
  `ifdef ENABLE_FUNCPOINT
    property cacc_calc_fp48__fp32_mant_carry__12_cov;
        disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
        @(posedge nvdla_core_clk)
        fp32_mant_carry;
    endproperty

    FUNCPOINT_cacc_calc_fp48__fp32_mant_carry__12_COV : cover property (cacc_calc_fp48__fp32_mant_carry__12_cov);
  `endif
`endif


`ifndef DISABLE_FUNCPOINT
  `ifdef ENABLE_FUNCPOINT
    property cacc_calc_fp48__fp32_mant_zero__13_cov;
        disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
        @(posedge nvdla_core_clk)
        ~(|fp32_mant_nmlz);
    endproperty

    FUNCPOINT_cacc_calc_fp48__fp32_mant_zero__13_COV : cover property (cacc_calc_fp48__fp32_mant_zero__13_cov);
  `endif
`endif


`ifndef DISABLE_FUNCPOINT
  `ifdef ENABLE_FUNCPOINT
    property cacc_calc_fp48__fp32_mant_nan__14_cov;
        disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off)
        @(posedge nvdla_core_clk)
        &fp32_expo_nmlz;
    endproperty

    FUNCPOINT_cacc_calc_fp48__fp32_mant_nan__14_COV : cover property (cacc_calc_fp48__fp32_mant_nan__14_cov);
  `endif
`endif

`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_never #(0,0,"Error! in_data_44b highest three bits is not same!") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, (in_valid & ~di_nan & ~(di_mant_pre[37:35]==3'b111 || di_mant_pre[37:35]==3'b0)));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_never #(0,0,"Error! in_data_44b is illegal,NAN and zero happen simultaneously!") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (in_valid & di_nan & di_zero));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_never #(0,0,"Error! in_op_48b is illegal,NAN and zero happen simultaneously!") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (in_valid & oi_nan & oi_zero));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_never #(0,0,"Error! out partial sum is not normalized!") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, (final_vld & ~partial_nan & ~partial_zero & ~(partial_mant[40 -1]^partial_mant[40 -2])));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_never #(0,0,"Error! out fp32 is not illegal!") zzz_assert_never_5x (nvdla_core_clk, `ASSERT_RESET, (final_vld & final_sel & (~(|fp32_expo_nmlz) & (|fp32_mant_nmlz) || (&fp32_expo_nmlz) & ~(|fp32_mant_nmlz))));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif
endmodule