data/full_repos/permissive/467394306/qsim_rtl/pe/pe_tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/467394306/qsim_rtl/pe/pe_tb.sv:20: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/467394306/qsim_rtl/pe/pe_tb.sv:51: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: data/full_repos/permissive/467394306/qsim_rtl/pe/pe_tb.sv:59: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/467394306/qsim_rtl/pe/pe_tb.sv:62: syntax error, unexpected \'@\'\n  @(negedge clk);\n  ^\n%Error: data/full_repos/permissive/467394306/qsim_rtl/pe/pe_tb.sv:64: syntax error, unexpected \'@\'\n  @(posedge clk);\n  ^\n%Error: Exiting due to 4 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module PE_TB();
	reg clk, rstn, fire;
	reg [7:0] w, a;
	wire [11:0] out;
	wire out_f;
	wire [7:0] out_a, out_w;
	reg [7:0] cnt;

	integer i;
	integer input_file;
	integer output_file;
	integer ret_read;

	always begin
		`HALF_CLOCK_PERIOD;
		clk = ~clk;
	end

	always @(posedge clk) begin
		cnt <= cnt + 1'b1;
	end

	PE dut(clk, rstn, fire, w, a, out_f, out_a, out_w, out);

	initial begin
		clk <= 0;
		rstn <= 0;
		cnt <= 0;
		w <= 0;
		a <= 0;
		fire <= 0;

		$display("Initialized");


		output_file = $fopen(`OUTPUT_FN,"w");
		if (!output_file) begin
			$display("Couldn't open the output file.");
			$finish;
		end
		input_file = $fopen(`INPUT_FN,"r");
		if (!input_file) begin
			$display("Couldn't open the input file.");
			$finish;
		end
		@(posedge clk);
		@(posedge clk);
		@(negedge clk);
		rstn <= 1;
		fire <= 1;
		for (i=0; i<16; i=i+1) begin
			ret_read = $fscanf(input_file, "%d %d", w, a);
			$fwrite(output_file, "w = %0d, a = %0d\n", w, a);
			@(posedge clk);
			$display("i=%d\tout=%d", i, out);
		end
		@(negedge clk);
		fire <= 0;
		@(posedge clk);
		@(posedge clk);
		$finish;
	end
endmodule
module PE_TB();

	reg clk, rstn, fire;
	reg [7:0] w, a;
	wire [11:0] out;
	wire out_f;
	wire [7:0] out_a, out_w;
	reg [7:0] cnt;

	integer i;
	integer input_file;
	integer output_file;
	integer ret_read;

	always begin
		`HALF_CLOCK_PERIOD;
		clk = ~clk;
	end

	always @(posedge clk) begin
		cnt <= cnt + 1'b1;
	end

	PE dut(clk, rstn, fire, w, a, out_f, out_a, out_w, out);

	initial begin
		clk <= 0;
		rstn <= 0;
		cnt <= 0;
		w <= 0;
		a <= 0;
		fire <= 0;

		$display("Initialized");


		output_file = $fopen(`OUTPUT_FN,"w");
		if (!output_file) begin
			$display("Couldn't open the output file.");
			$finish;
		end
		input_file = $fopen(`INPUT_FN,"r");
		if (!input_file) begin
			$display("Couldn't open the input file.");
			$finish;
		end
		@(posedge clk);
		@(posedge clk);
		@(negedge clk);
		rstn <= 1;
		fire <= 1;
		for (i=0; i<16; i=i+1) begin
			ret_read = $fscanf(input_file, "%d %d", w, a);
			$fwrite(output_file, "w = %0d, a = %0d\n", w, a);
			@(posedge clk);
			$display("i=%d\tout=%d", i, out);
		end
		@(negedge clk);
		fire <= 0;
		@(posedge clk);
		@(posedge clk);
		$finish;
	end
endmodule