data/full_repos/permissive/43856783/j1_soc/hdl/Position/RAM_Block.v
data/verilator_xmls/1b7bacf0-a457-4859-9af2-cc57244fca1d.xml
module RAM_Block(
	 input clk,
    input [7:0] Address_w,
	 input W_ref,
	 input [7:0] Address,
    input W,
    input [31:0] Data_I,
    output reg [31:0] Data_O,
 (* KEEP = "TRUE" *)   output reg [15:0] Ref
    );
	 
	 reg [31:0] Mem [255:0];
	 
	 always@(negedge clk) begin
		if(W) Mem[Address_w] <= Data_I;
		else Data_O <= Mem[Address];
	 end
	 
	 always@(negedge clk) begin
		if(W_ref) Ref <= Data_I[15:0];
		else Ref <= Ref;
	 end
	 
endmodule
module RAM_Block(
	 input clk,
    input [7:0] Address_w,
	 input W_ref,
	 input [7:0] Address,
    input W,
    input [31:0] Data_I,
    output reg [31:0] Data_O,
 (* KEEP = "TRUE" *)   output reg [15:0] Ref
    );

	 
	 reg [31:0] Mem [255:0];
	 
	 always@(negedge clk) begin
		if(W) Mem[Address_w] <= Data_I;
		else Data_O <= Mem[Address];
	 end
	 
	 always@(negedge clk) begin
		if(W_ref) Ref <= Data_I[15:0];
		else Ref <= Ref;
	 end
	 
endmodule