data/full_repos/permissive/521337848/Hardware/IO/keyboard.v
data/verilator_xmls/64949a45-08a7-4adc-9ae7-834cd7c14722.xml
module keyController(
	input clk,
	input rst,
	
	input[7:0] in,
	
	output reg irq,
	
	output reg[31:0] out
);

reg[31:0] f_out;
reg[7:0] mem;
reg[7:0] f_mem;

reg[3:0] tim;
reg[3:0] f_tim;

always@(posedge clk or posedge rst)
	if(rst) f_mem <= 0;
	else f_mem <= mem;

	
always@(posedge clk or posedge rst)
	if(rst) f_tim <= 0;
	else f_tim <= tim;


	
always@(posedge clk or posedge rst)
	if(rst) f_out <= 0;
	else f_out <= out;

reg decy;

always@(*)begin
	out = f_out;
	irq = 0;
	mem = f_mem;
	
	tim = f_tim;
	
	if(f_tim == 0) begin
		
		if(in != f_mem)begin
					irq = 1;
					out = {8'd2,8'b0,8'b0,in};
					mem = in;
					
				end
		
		
		tim = 15;
	end
	
	if(tim!=0)begin
		tim = f_tim - 1;
	end
end

endmodule
module keyController(
	input clk,
	input rst,
	
	input[7:0] in,
	
	output reg irq,
	
	output reg[31:0] out
);


reg[31:0] f_out;
reg[7:0] mem;
reg[7:0] f_mem;

reg[3:0] tim;
reg[3:0] f_tim;

always@(posedge clk or posedge rst)
	if(rst) f_mem <= 0;
	else f_mem <= mem;

	
always@(posedge clk or posedge rst)
	if(rst) f_tim <= 0;
	else f_tim <= tim;


	
always@(posedge clk or posedge rst)
	if(rst) f_out <= 0;
	else f_out <= out;

reg decy;

always@(*)begin
	out = f_out;
	irq = 0;
	mem = f_mem;
	
	tim = f_tim;
	
	if(f_tim == 0) begin
		
		if(in != f_mem)begin
					irq = 1;
					out = {8'd2,8'b0,8'b0,in};
					mem = in;
					
				end
		
		
		tim = 15;
	end
	
	if(tim!=0)begin
		tim = f_tim - 1;
	end
end

endmodule