data/full_repos/permissive/523038000/lab9/add_4.v
data/verilator_xmls/4456445e-ade1-4fd1-8e13-dc9dc5762c93.xml
module add_4  (out , in);
output  [31:0] out;
input   [31:0] in;

assign out= in + 4;
endmodule
module add_4  (out , in);

output  [31:0] out;
input   [31:0] in;

assign out= in + 4;
endmodule