data/full_repos/permissive/522312766/verilog/rtl/core/ALU.v
1: b'%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/ALU.v:15: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LTS generates 1 bits.\n                                                                              : ... In instance alu\n   4\'b0010: result = $signed(operandA) < $signed(operandB);\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/ALU.v:16: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                                              : ... In instance alu\n   4\'b0011: result = operandA < operandB;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/ALU.v:22: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s GTS generates 1 bits.\n                                                                              : ... In instance alu\n   4\'b1001: result = $signed(operandA) > $signed(operandB);\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/522312766/verilog/rtl/core/ALU.v:23: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s GT generates 1 bits.\n                                                                              : ... In instance alu\n   4\'b1010: result = operandA > operandB;\n                   ^\n%Error: Exiting due to 4 warning(s)\n'
module alu (
	input wire bneq,
	input wire btype,
	input wire [3:0] alu_fn,
	input wire [31:0] operandA,
	input wire [31:0] operandB,
	output reg btaken,
	output reg [31:0] result
);

	always @(*) begin
		case (alu_fn)
			4'b0000: result = $signed(operandA) + $signed(operandB);
			4'b0001: result = $signed(operandA) << $signed(operandB[4:0]);
			4'b0010: result = $signed(operandA) < $signed(operandB);
			4'b0011: result = operandA < operandB;
			4'b0100: result = $signed(operandA) ^ $signed(operandB);
			4'b0101: result = $signed(operandA) >> $signed(operandB[4:0]);
			4'b0110: result = $signed(operandA) | $signed(operandB);
			4'b0111: result = $signed(operandA) & $signed(operandB);
			4'b1000: result = $signed(operandA) - $signed(operandB);
			4'b1001: result = $signed(operandA) > $signed(operandB);
			4'b1010: result = operandA > operandB;
			4'b1101: result = $signed(operandA) >>> $signed(operandB[4:0]);
			default: result = 0;
		endcase
		if (btype)
			case (alu_fn)
				4'b1000:
					if (bneq)
						btaken = (|result ? 1'b1 : 1'b0);
					else
						btaken = (~|result ? 1'b1 : 1'b0);
				4'b0010: btaken = (|result ? 1'b1 : 1'b0);
				4'b0011: btaken = (|result ? 1'b1 : 1'b0);
				4'b1001: btaken = (|result ? 1'b1 : (operandA == operandB ? 1'b1 : 1'b0));
				4'b1010: btaken = (|result ? 1'b1 : (operandA == operandB ? 1'b1 : 1'b0));
				default: btaken = 0;
			endcase
		else
			btaken = 0;
	end
endmodule
module alu (
	input wire bneq,
	input wire btype,
	input wire [3:0] alu_fn,
	input wire [31:0] operandA,
	input wire [31:0] operandB,
	output reg btaken,
	output reg [31:0] result
);


	always @(*) begin
		case (alu_fn)
			4'b0000: result = $signed(operandA) + $signed(operandB);
			4'b0001: result = $signed(operandA) << $signed(operandB[4:0]);
			4'b0010: result = $signed(operandA) < $signed(operandB);
			4'b0011: result = operandA < operandB;
			4'b0100: result = $signed(operandA) ^ $signed(operandB);
			4'b0101: result = $signed(operandA) >> $signed(operandB[4:0]);
			4'b0110: result = $signed(operandA) | $signed(operandB);
			4'b0111: result = $signed(operandA) & $signed(operandB);
			4'b1000: result = $signed(operandA) - $signed(operandB);
			4'b1001: result = $signed(operandA) > $signed(operandB);
			4'b1010: result = operandA > operandB;
			4'b1101: result = $signed(operandA) >>> $signed(operandB[4:0]);
			default: result = 0;
		endcase
		if (btype)
			case (alu_fn)
				4'b1000:
					if (bneq)
						btaken = (|result ? 1'b1 : 1'b0);
					else
						btaken = (~|result ? 1'b1 : 1'b0);
				4'b0010: btaken = (|result ? 1'b1 : 1'b0);
				4'b0011: btaken = (|result ? 1'b1 : 1'b0);
				4'b1001: btaken = (|result ? 1'b1 : (operandA == operandB ? 1'b1 : 1'b0));
				4'b1010: btaken = (|result ? 1'b1 : (operandA == operandB ? 1'b1 : 1'b0));
				default: btaken = 0;
			endcase
		else
			btaken = 0;
	end
endmodule