data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/mag_calc.v
1: b"%Error: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/mag_calc.v:32: Cannot find file containing module: 'block3x3'\n  block3x3 blk3_mag_1(.clk(clk), .rst(rst), .din(din), .dout1(d1_1), .dout2(d2_1), .dout3(d3_1),\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift,data/full_repos/permissive/507203156/block3x3\n             data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift,data/full_repos/permissive/507203156/block3x3.v\n             data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift,data/full_repos/permissive/507203156/block3x3.sv\n             block3x3\n             block3x3.v\n             block3x3.sv\n             obj_dir/block3x3\n             obj_dir/block3x3.v\n             obj_dir/block3x3.sv\n%Error: data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/src/sift/mag_calc.v:35: Cannot find file containing module: 'block3x3_2'\n  block3x3_2 blk3_mag_2(.clk(clk), .rst(rst), .din(din), .dout1(d1_2), .dout2(d2_2), .dout3(d3_2),\n  ^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module mag_calc(
    input clk,
    input rst,
	input complete1,
    input [7:0] din,
    output signed [7:0] dx,
    output signed [7:0] dy,
    output out_en
);
	 
	 wire [7:0] d1,d2,d3,d4,d5,d6,d7,d8,d9;
	 reg signed [8:0] tmp_x1,tmp_y1;
	 
	 wire [7:0] d1_1,d2_1,d3_1,d4_1,d5_1,d6_1,d7_1,d8_1,d9_1;
	 wire [7:0] d1_2,d2_2,d3_2,d4_2,d5_2,d6_2,d7_2,d8_2,d9_2;
	 
	 wire out_en_1;
	 wire out_en_2;
	 
	 block3x3 blk3_mag_1(.clk(clk), .rst(rst), .din(din), .dout1(d1_1), .dout2(d2_1), .dout3(d3_1),
				 .dout4(d4_1), .dout5(d5_1), .dout6(d6_1), .dout7(d7_1),.dout8(d8_1),.dout9(d9_1), .start_flag(out_en_1));
				 
	 block3x3_2 blk3_mag_2(.clk(clk), .rst(rst), .din(din), .dout1(d1_2), .dout2(d2_2), .dout3(d3_2),
				 .dout4(d4_2), .dout5(d5_2), .dout6(d6_2), .dout7(d7_2),.dout8(d8_2),.dout9(d9_2), .start_flag(out_en_2));
				 
	 assign out_en=complete1?out_en_2:out_en_1;				
	
	 assign d1=complete1?d1_2:d1_1;
	 assign d2=complete1?d2_2:d2_1;
	 assign d3=complete1?d3_2:d3_1;
	 assign d4=complete1?d4_2:d4_1;
	 assign d5=complete1?d5_2:d5_1;
	 assign d6=complete1?d6_2:d6_1;
	 assign d7=complete1?d7_2:d7_1;
	 assign d8=complete1?d8_2:d8_1;
	 assign d9=complete1?d9_2:d9_1;
	


	always @(posedge clk or negedge rst)
	 begin
		if(!rst)
		begin
			tmp_x1<=0;
			tmp_y1<=0;
		end
		else
		begin
			tmp_x1<=d8-d2;
			tmp_y1<=d6-d4;
		end
	 end
	 
	 assign dx=tmp_x1[7:0];
	 assign dy=tmp_y1[7:0];
	 

endmodule
module mag_calc(
    input clk,
    input rst,
	input complete1,
    input [7:0] din,
    output signed [7:0] dx,
    output signed [7:0] dy,
    output out_en
);

	 
	 wire [7:0] d1,d2,d3,d4,d5,d6,d7,d8,d9;
	 reg signed [8:0] tmp_x1,tmp_y1;
	 
	 wire [7:0] d1_1,d2_1,d3_1,d4_1,d5_1,d6_1,d7_1,d8_1,d9_1;
	 wire [7:0] d1_2,d2_2,d3_2,d4_2,d5_2,d6_2,d7_2,d8_2,d9_2;
	 
	 wire out_en_1;
	 wire out_en_2;
	 
	 block3x3 blk3_mag_1(.clk(clk), .rst(rst), .din(din), .dout1(d1_1), .dout2(d2_1), .dout3(d3_1),
				 .dout4(d4_1), .dout5(d5_1), .dout6(d6_1), .dout7(d7_1),.dout8(d8_1),.dout9(d9_1), .start_flag(out_en_1));
				 
	 block3x3_2 blk3_mag_2(.clk(clk), .rst(rst), .din(din), .dout1(d1_2), .dout2(d2_2), .dout3(d3_2),
				 .dout4(d4_2), .dout5(d5_2), .dout6(d6_2), .dout7(d7_2),.dout8(d8_2),.dout9(d9_2), .start_flag(out_en_2));
				 
	 assign out_en=complete1?out_en_2:out_en_1;				
	
	 assign d1=complete1?d1_2:d1_1;
	 assign d2=complete1?d2_2:d2_1;
	 assign d3=complete1?d3_2:d3_1;
	 assign d4=complete1?d4_2:d4_1;
	 assign d5=complete1?d5_2:d5_1;
	 assign d6=complete1?d6_2:d6_1;
	 assign d7=complete1?d7_2:d7_1;
	 assign d8=complete1?d8_2:d8_1;
	 assign d9=complete1?d9_2:d9_1;
	


	always @(posedge clk or negedge rst)
	 begin
		if(!rst)
		begin
			tmp_x1<=0;
			tmp_y1<=0;
		end
		else
		begin
			tmp_x1<=d8-d2;
			tmp_y1<=d6-d4;
		end
	 end
	 
	 assign dx=tmp_x1[7:0];
	 assign dy=tmp_y1[7:0];
	 

endmodule