data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg.v
1: b'%Error: data/full_repos/permissive/429196919/FPGA/shiftReg/shiftReg.v:35: Cannot find include file: ../genericIOSateliteEnv.v\n `include "../genericIOSateliteEnv.v" \n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/429196919/FPGA/shiftReg,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v\n             data/full_repos/permissive/429196919/FPGA/shiftReg,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v.v\n             data/full_repos/permissive/429196919/FPGA/shiftReg,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v.sv\n             ../genericIOSateliteEnv.v\n             ../genericIOSateliteEnv.v.v\n             ../genericIOSateliteEnv.v.sv\n             obj_dir/../genericIOSateliteEnv.v\n             obj_dir/../genericIOSateliteEnv.v.v\n             obj_dir/../genericIOSateliteEnv.v.sv\n%Error: Exiting due to 1 error(s)\n'
module shiftReg 	#(parameter WIDTH = 8)
					(input[WIDTH-1:0] parallelInput,
				     input serialInput,
					 input clk,
					 input load,
					 input enableShift,
					 input masterClk,
					 output	reg[WIDTH-1:0] parallelOutput,
					 output wire serialOutput,
					 output reg loaded);

	reg [WIDTH-1:0] internal;
	integer i;




	reg prevClk;
	reg prevEnableShift;

	always @ (posedge masterClk) begin
		prevClk <= clk;
		prevEnableShift <= enableShift;
	end
	`define SHIFT_CLK_POSEDGE (clk && !prevClk)
	`define SHIFT_CLK_NEGEDGE (!clk && prevClk)
	`define SHIFT_EN_SHIFT_POSEDGE (enableShift && !prevEnableShift)
	`define SHIFT_EN_SHIFT_NEGEDGE (!enableShift && prevEnableShift)





	assign serialOutput = internal[WIDTH-1];

	always @ (posedge masterClk) begin
		if(load && `SHIFT_EN_SHIFT_POSEDGE) begin
			internal <= parallelInput;
			loaded <= 1;
		end
		else if(`SHIFT_CLK_POSEDGE && enableShift) begin
			if (WIDTH > 1) begin
				for (i=WIDTH-1; i>0; i=i-1) begin
					internal[i] <= internal[i-1];
				end
			end
			internal[0] <= serialInput;
		end
		else if (`SHIFT_EN_SHIFT_NEGEDGE) begin
			parallelOutput <= internal;
			loaded <= 0;
		end
	end

endmodule
module shiftReg 	#(parameter WIDTH = 8)
					(input[WIDTH-1:0] parallelInput,
				     input serialInput,
					 input clk,
					 input load,
					 input enableShift,
					 input masterClk,
					 output	reg[WIDTH-1:0] parallelOutput,
					 output wire serialOutput,
					 output reg loaded);


	reg [WIDTH-1:0] internal;
	integer i;




	reg prevClk;
	reg prevEnableShift;

	always @ (posedge masterClk) begin
		prevClk <= clk;
		prevEnableShift <= enableShift;
	end
	`define SHIFT_CLK_POSEDGE (clk && !prevClk)
	`define SHIFT_CLK_NEGEDGE (!clk && prevClk)
	`define SHIFT_EN_SHIFT_POSEDGE (enableShift && !prevEnableShift)
	`define SHIFT_EN_SHIFT_NEGEDGE (!enableShift && prevEnableShift)





	assign serialOutput = internal[WIDTH-1];

	always @ (posedge masterClk) begin
		if(load && `SHIFT_EN_SHIFT_POSEDGE) begin
			internal <= parallelInput;
			loaded <= 1;
		end
		else if(`SHIFT_CLK_POSEDGE && enableShift) begin
			if (WIDTH > 1) begin
				for (i=WIDTH-1; i>0; i=i-1) begin
					internal[i] <= internal[i-1];
				end
			end
			internal[0] <= serialInput;
		end
		else if (`SHIFT_EN_SHIFT_NEGEDGE) begin
			parallelOutput <= internal;
			loaded <= 0;
		end
	end

endmodule