data/full_repos/permissive/490649362/pipeline/src/PC.v
data/verilator_xmls/b2792409-e8b2-474b-9b8f-510bbb92e409.xml
module PC(clk, in, out, PCWrite);

    parameter size = 32;

    input PCWrite;
    input [size-1:0] in;
    output [size-1:0] out;
    input clk;

    reg [size-1:0] out;

    initial begin
        out = 32'b0;
    end

    always @(posedge clk) begin
        if (PCWrite)
            out <= in;
    end

endmodule
module PC(clk, in, out, PCWrite);


    parameter size = 32;

    input PCWrite;
    input [size-1:0] in;
    output [size-1:0] out;
    input clk;

    reg [size-1:0] out;

    initial begin
        out = 32'b0;
    end

    always @(posedge clk) begin
        if (PCWrite)
            out <= in;
    end

endmodule