data/full_repos/permissive/476411617/BitSliced_ALU.v
1: b'%Warning-WIDTH: data/full_repos/permissive/476411617/BitSliced_ALU.v:72: Operator ADD expects 5 bits on the RHS, but RHS\'s VARREF \'carry_borrow\' generates 1 bits.\n                                                                       : ... In instance BitSliced_ALU\n        {carry_borrow, rd_d} = rs1_d + rs2_d + carry_borrow;\n                                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/476411617/BitSliced_ALU.v:80: Operator ADD expects 5 bits on the RHS, but RHS\'s VARREF \'carry_borrow\' generates 1 bits.\n                                                                       : ... In instance BitSliced_ALU\n        {carry_borrow, rd_d} = rs1_d - rs2_d + carry_borrow;\n                                             ^\n%Warning-WIDTH: data/full_repos/permissive/476411617/BitSliced_ALU.v:100: Operator SHIFTL expects 64 bits on the LHS, but LHS\'s VARREF \'mult_tmp\' generates 8 bits.\n                                                                        : ... In instance BitSliced_ALU\n     acc_tmp = acc_tmp + (mult_tmp << (Slice_Size * ((rs1_cnt + rs2_cnt + (LENGTH/Slice_Size-3)))));  \n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/476411617/BitSliced_ALU.v:104: Operator SHIFTL expects 64 bits on the LHS, but LHS\'s VARREF \'mult_tmp\' generates 8 bits.\n                                                                        : ... In instance BitSliced_ALU\n     acc_tmp = acc_tmp + (mult_tmp << (Slice_Size * ((rs1_cnt + rs2_cnt - 2))));  \n                                   ^~\n%Error: Exiting due to 4 warning(s)\n'
module BitSliced_ALU #(parameter LENGTH = 32, parameter Slice_Size = 4)
    (
        input clk,  
        input reset, 
        output reg [Slice_Size-1:0] rd_d,
        input[Slice_Size-1:0] rs1_d,
        input[Slice_Size-1:0] rs2_d,
        input[3:0] alu_op,
        input[9:0] count,
        input reg_write,
        input[1:0] Q,
		input [31:0] rs1_cnt,
		input [31:0] rs2_cnt

    );
reg carry_borrow = 0;
reg [LENGTH * 2 - 1:0] acc_tmp = 0;
reg [2 * Slice_Size - 1 :0] mult_tmp = 0;


always @(posedge clk)
begin
    if(alu_op == 0 && count % 3 == 2)
    begin
        {carry_borrow, rd_d} = rs1_d + rs2_d + carry_borrow;
        if(count == 3*(LENGTH/Slice_Size)+1)
        begin
            carry_borrow = 0;
        end
    end
    else if(alu_op == 1 && count % 3 == 2)
    begin
        {carry_borrow, rd_d} = rs1_d - rs2_d + carry_borrow;
        if(count == 3*(LENGTH/Slice_Size)+1)
        begin
            carry_borrow = 0;
        end
    end
    else if(alu_op == 2)
    begin
		if(count >= 2*(LENGTH/Slice_Size)*(LENGTH/Slice_Size)+2)
		begin
			rd_d = acc_tmp[LENGTH/2 + Slice_Size - 1 -: Slice_Size];
			acc_tmp = acc_tmp >> Slice_Size;
		end
		else
		begin
			if(count % 2 == 1)
			begin
				mult_tmp = (rs1_d * rs2_d);
				if(rs1_cnt == 0 || rs1_cnt == 1)
				begin
					acc_tmp = acc_tmp + (mult_tmp << (Slice_Size * ((rs1_cnt + rs2_cnt + (LENGTH/Slice_Size-3)))));
				end
				else
				begin
					acc_tmp = acc_tmp + (mult_tmp << (Slice_Size * ((rs1_cnt + rs2_cnt - 2))));
				end
				
			end
		end
		if(rs1_cnt == 0 && rs2_cnt == 0)
		begin
			acc_tmp = 0;
		end
	end
end


endmodule
module BitSliced_ALU #(parameter LENGTH = 32, parameter Slice_Size = 4)
    (
        input clk,  
        input reset, 
        output reg [Slice_Size-1:0] rd_d,
        input[Slice_Size-1:0] rs1_d,
        input[Slice_Size-1:0] rs2_d,
        input[3:0] alu_op,
        input[9:0] count,
        input reg_write,
        input[1:0] Q,
		input [31:0] rs1_cnt,
		input [31:0] rs2_cnt

    );

reg carry_borrow = 0;
reg [LENGTH * 2 - 1:0] acc_tmp = 0;
reg [2 * Slice_Size - 1 :0] mult_tmp = 0;


always @(posedge clk)
begin
    if(alu_op == 0 && count % 3 == 2)
    begin
        {carry_borrow, rd_d} = rs1_d + rs2_d + carry_borrow;
        if(count == 3*(LENGTH/Slice_Size)+1)
        begin
            carry_borrow = 0;
        end
    end
    else if(alu_op == 1 && count % 3 == 2)
    begin
        {carry_borrow, rd_d} = rs1_d - rs2_d + carry_borrow;
        if(count == 3*(LENGTH/Slice_Size)+1)
        begin
            carry_borrow = 0;
        end
    end
    else if(alu_op == 2)
    begin
		if(count >= 2*(LENGTH/Slice_Size)*(LENGTH/Slice_Size)+2)
		begin
			rd_d = acc_tmp[LENGTH/2 + Slice_Size - 1 -: Slice_Size];
			acc_tmp = acc_tmp >> Slice_Size;
		end
		else
		begin
			if(count % 2 == 1)
			begin
				mult_tmp = (rs1_d * rs2_d);
				if(rs1_cnt == 0 || rs1_cnt == 1)
				begin
					acc_tmp = acc_tmp + (mult_tmp << (Slice_Size * ((rs1_cnt + rs2_cnt + (LENGTH/Slice_Size-3)))));
				end
				else
				begin
					acc_tmp = acc_tmp + (mult_tmp << (Slice_Size * ((rs1_cnt + rs2_cnt - 2))));
				end
				
			end
		end
		if(rs1_cnt == 0 && rs2_cnt == 0)
		begin
			acc_tmp = 0;
		end
	end
end


endmodule