data/full_repos/permissive/515890445/ARM_MultiCycle/MultiCycle/MultiCycle_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/515890445/ARM_MultiCycle/MultiCycle/MultiCycle_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n   #period;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/515890445/ARM_MultiCycle/MultiCycle/MultiCycle_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n   #period;\n   ^\n%Error: data/full_repos/permissive/515890445/ARM_MultiCycle/MultiCycle/MultiCycle_tb.v:11: Cannot find file containing module: \'MultiCycle\'\n    MultiCycle  DUT( \n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/515890445/ARM_MultiCycle/MultiCycle,data/full_repos/permissive/515890445/MultiCycle\n             data/full_repos/permissive/515890445/ARM_MultiCycle/MultiCycle,data/full_repos/permissive/515890445/MultiCycle.v\n             data/full_repos/permissive/515890445/ARM_MultiCycle/MultiCycle,data/full_repos/permissive/515890445/MultiCycle.sv\n             MultiCycle\n             MultiCycle.v\n             MultiCycle.sv\n             obj_dir/MultiCycle\n             obj_dir/MultiCycle.v\n             obj_dir/MultiCycle.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module MultiCycle_tb (
	output wire [3:0] state,
	output wire [7:0] out
);

    localparam period = 1;
	 reg CLK, RESET_N;

    MultiCycle 	DUT(	
		.CLK(CLK) ,	
		.RESET_N(RESET_N) ,
		.STATE(state) ,
		.OUT(out) 
	); 

	always 
		begin
			#period;
			CLK = 1'b0; 

			#period;
			CLK = 1'b1;
			$stop;
		end
    
    initial 
        begin
				CLK = 0;
				RESET_N = 1;
        end
		  
	 
endmodule
module MultiCycle_tb (
	output wire [3:0] state,
	output wire [7:0] out
);


    localparam period = 1;
	 reg CLK, RESET_N;

    MultiCycle 	DUT(	
		.CLK(CLK) ,	
		.RESET_N(RESET_N) ,
		.STATE(state) ,
		.OUT(out) 
	); 

	always 
		begin
			#period;
			CLK = 1'b0; 

			#period;
			CLK = 1'b1;
			$stop;
		end
    
    initial 
        begin
				CLK = 0;
				RESET_N = 1;
        end
		  
	 
endmodule