data/full_repos/permissive/441359809/src/yosys/tests/various/attrib05_port_conn.v
data/verilator_xmls/caff8835-28ec-49b6-8a44-cd8681eb773a.xml
module foo(clk, rst, inp, out);
  input  wire clk;
  input  wire rst;
  input  wire inp;
  output wire out;

  bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out);
endmodule
module foo(clk, rst, inp, out);

  input  wire clk;
  input  wire rst;
  input  wire inp;
  output wire out;

  bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out);
endmodule