data/full_repos/permissive/446997925/hw3/and.v
data/verilator_xmls/e2b82ace-9d56-43df-a68f-94f4fe8a4f8c.xml
module and_16(out, a, b);
input [15:0] a, b;
output [15:0] out;

and_8 f(out[7:0], a[7:0], b[7:0]),
          s(out[15:8], a[15:8], b[15:8]);
endmodule
module and_16(out, a, b);

input [15:0] a, b;
output [15:0] out;

and_8 f(out[7:0], a[7:0], b[7:0]),
          s(out[15:8], a[15:8], b[15:8]);
endmodule