data/full_repos/permissive/426864978/lab1/task4/statemachine.sv
data/verilator_xmls/18f9d8ab-737d-410f-9236-94624c11c5d9.xml
module vDFF(clk,D,Q);
  parameter n=1;
  input clk;
  input [n-1:0] D;
  output reg [n-1:0] Q;
  always @(posedge clk)
    Q <= D;
endmodule
module vDFF(clk,D,Q);

  parameter n=1;
  input clk;
  input [n-1:0] D;
  output reg [n-1:0] Q;
  always @(posedge clk)
    Q <= D;
endmodule