data/full_repos/permissive/517935866/alarm_test.v
1: b'%Error: data/full_repos/permissive/517935866/alarm_test.v:1: Cannot find include file: alarm.v\n`include "alarm.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/517935866,data/full_repos/permissive/517935866/alarm.v\n             data/full_repos/permissive/517935866,data/full_repos/permissive/517935866/alarm.v.v\n             data/full_repos/permissive/517935866,data/full_repos/permissive/517935866/alarm.v.sv\n             alarm.v\n             alarm.v.v\n             alarm.v.sv\n             obj_dir/alarm.v\n             obj_dir/alarm.v.v\n             obj_dir/alarm.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/517935866/alarm_test.v:20: Unsupported: Ignoring delay on this delayed statement.\nalways #10 clk=~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/517935866/alarm_test.v:23: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("alarm_test.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/517935866/alarm_test.v:24: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,alarm_test);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/517935866/alarm_test.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #40;clr=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/517935866/alarm_test.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #300;\n    ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n'
module alarm_test;


reg clk,clr;


wire [7:0] hr,min,sec;
wire alarm;


alarm uut(
    .clk(clk),
    .clr(clr),
    .hr(hr),
    .min(min),
    .sec(sec)
);

always #10 clk=~clk;

initial begin
    $dumpfile("alarm_test.vcd");
    $dumpvars(0,alarm_test);

    clk=0;clr=1;uut.hr_alm=8'd0;uut.min_alm=8'd0;uut.sec_alm=8'd7;
  	


    #40;clr=0;
    #300;
    $finish();


end
endmodule
module alarm_test;



reg clk,clr;


wire [7:0] hr,min,sec;
wire alarm;


alarm uut(
    .clk(clk),
    .clr(clr),
    .hr(hr),
    .min(min),
    .sec(sec)
);

always #10 clk=~clk;

initial begin
    $dumpfile("alarm_test.vcd");
    $dumpvars(0,alarm_test);

    clk=0;clr=1;uut.hr_alm=8'd0;uut.min_alm=8'd0;uut.sec_alm=8'd7;
  	


    #40;clr=0;
    #300;
    $finish();


end
endmodule