data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_drive_pat/rtl/wfg_drive_pat_wishbone_reg.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_drive_pat/rtl/wfg_drive_pat_wishbone_reg.sv:67: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'4\'h4\' generates 4 bits.\n                                                                                                                       : ... In instance wfg_drive_pat_wishbone_reg\n            case (wbs_adr_i)\n            ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_drive_pat/rtl/wfg_drive_pat_wishbone_reg.sv:67: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                                                       : ... In instance wfg_drive_pat_wishbone_reg\n            case (wbs_adr_i)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_drive_pat/rtl/wfg_drive_pat_wishbone_reg.sv:67: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'4\'h8\' generates 4 bits.\n                                                                                                                       : ... In instance wfg_drive_pat_wishbone_reg\n            case (wbs_adr_i)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_drive_pat/rtl/wfg_drive_pat_wishbone_reg.sv:67: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'4\'hc\' generates 4 bits.\n                                                                                                                       : ... In instance wfg_drive_pat_wishbone_reg\n            case (wbs_adr_i)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_drive_pat/rtl/wfg_drive_pat_wishbone_reg.sv:96: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'4\'h4\' generates 4 bits.\n                                                                                                                       : ... In instance wfg_drive_pat_wishbone_reg\n                case (wbs_adr_i)\n                ^~~~\n%Warning-WIDTH: data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_drive_pat/rtl/wfg_drive_pat_wishbone_reg.sv:96: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                                                       : ... In instance wfg_drive_pat_wishbone_reg\n                case (wbs_adr_i)\n                ^~~~\n%Warning-WIDTH: data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_drive_pat/rtl/wfg_drive_pat_wishbone_reg.sv:96: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'4\'h8\' generates 4 bits.\n                                                                                                                       : ... In instance wfg_drive_pat_wishbone_reg\n                case (wbs_adr_i)\n                ^~~~\n%Warning-WIDTH: data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_drive_pat/rtl/wfg_drive_pat_wishbone_reg.sv:96: Operator CASE expects 32 bits on the Case Item, but Case Item\'s CONST \'4\'hc\' generates 4 bits.\n                                                                                                                       : ... In instance wfg_drive_pat_wishbone_reg\n                case (wbs_adr_i)\n                ^~~~\n%Error: Exiting due to 8 warning(s)\n'
module wfg_drive_pat_wishbone_reg #(
    parameter int BUSW = 32
) (

    input                       wb_clk_i,
    input                       wb_rst_i,
    input                       wbs_stb_i,
    input                       wbs_cyc_i,
    input                       wbs_we_i,
    input        [(BUSW/8-1):0] wbs_sel_i,
    input        [  (BUSW-1):0] wbs_dat_i,
    input        [  (BUSW-1):0] wbs_adr_i,
    output logic                wbs_ack_o,
    output logic [  (BUSW-1):0] wbs_dat_o,







    output logic [ 7:0] cfg_begin_q_o,
    output logic        cfg_core_sel_q_o,
    output logic [15:8] cfg_end_q_o,
    output logic [31:0] ctrl_en_q_o,
    output logic [31:0] patsel0_low_q_o,
    output logic [31:0] patsel1_high_q_o


);






    logic [ 7: 0] cfg_begin_ff;
    logic         cfg_core_sel_ff;
    logic [15: 8] cfg_end_ff;
    logic [31: 0] ctrl_en_ff;
    logic [31: 0] patsel0_low_ff;
    logic [31: 0] patsel1_high_ff;




    always_ff @(posedge wb_clk_i) begin
        if (wb_rst_i) begin





            cfg_begin_ff    <= 0;
            cfg_core_sel_ff <= 1'b0;
            cfg_end_ff      <= 0;
            ctrl_en_ff      <= 0;
            patsel0_low_ff  <= 0;
            patsel1_high_ff <= 0;


        end else if (wbs_stb_i && wbs_we_i && wbs_cyc_i) begin
            case (wbs_adr_i)





                4'h4: begin
                    cfg_begin_ff    <= wbs_dat_i[7:0];
                    cfg_core_sel_ff <= wbs_dat_i[16:16];
                    cfg_end_ff      <= wbs_dat_i[15:8];
                end
                4'h0:       ctrl_en_ff               <= wbs_dat_i[31: 0];
                4'h8:       patsel0_low_ff           <= wbs_dat_i[31: 0];
                4'hC:       patsel1_high_ff          <= wbs_dat_i[31: 0];


                default: begin
                end
            endcase
        end
    end


    always_ff @(posedge wb_clk_i) begin
        if (wb_rst_i) begin
            wbs_dat_o <= '0;
        end else begin
            if (wbs_stb_i && !wbs_we_i && wbs_cyc_i) begin
                wbs_dat_o <= '0;
                case (wbs_adr_i)





                    4'h4: begin
                        wbs_dat_o[7:0]   <= cfg_begin_ff;
                        wbs_dat_o[16:16] <= cfg_core_sel_ff;
                        wbs_dat_o[15:8]  <= cfg_end_ff;
                    end
                    4'h0:       wbs_dat_o[31: 0] <= ctrl_en_ff;
                    4'h8:       wbs_dat_o[31: 0] <= patsel0_low_ff;
                    4'hC:       wbs_dat_o[31: 0] <= patsel1_high_ff;


                    default:    wbs_dat_o <= 'X;
                endcase
            end
        end
    end


    always_ff @(posedge wb_clk_i) begin
        if (wb_rst_i) wbs_ack_o <= 1'b0;
        else wbs_ack_o <= wbs_stb_i && wbs_cyc_i & !wbs_ack_o;
    end






    assign cfg_begin_q_o    = cfg_begin_ff;
    assign cfg_core_sel_q_o = cfg_core_sel_ff;
    assign cfg_end_q_o      = cfg_end_ff;
    assign ctrl_en_q_o      = ctrl_en_ff;
    assign patsel0_low_q_o  = patsel0_low_ff;
    assign patsel1_high_q_o = patsel1_high_ff;


endmodule
module wfg_drive_pat_wishbone_reg #(
    parameter int BUSW = 32
) (

    input                       wb_clk_i,
    input                       wb_rst_i,
    input                       wbs_stb_i,
    input                       wbs_cyc_i,
    input                       wbs_we_i,
    input        [(BUSW/8-1):0] wbs_sel_i,
    input        [  (BUSW-1):0] wbs_dat_i,
    input        [  (BUSW-1):0] wbs_adr_i,
    output logic                wbs_ack_o,
    output logic [  (BUSW-1):0] wbs_dat_o,







    output logic [ 7:0] cfg_begin_q_o,
    output logic        cfg_core_sel_q_o,
    output logic [15:8] cfg_end_q_o,
    output logic [31:0] ctrl_en_q_o,
    output logic [31:0] patsel0_low_q_o,
    output logic [31:0] patsel1_high_q_o


);







    logic [ 7: 0] cfg_begin_ff;
    logic         cfg_core_sel_ff;
    logic [15: 8] cfg_end_ff;
    logic [31: 0] ctrl_en_ff;
    logic [31: 0] patsel0_low_ff;
    logic [31: 0] patsel1_high_ff;




    always_ff @(posedge wb_clk_i) begin
        if (wb_rst_i) begin





            cfg_begin_ff    <= 0;
            cfg_core_sel_ff <= 1'b0;
            cfg_end_ff      <= 0;
            ctrl_en_ff      <= 0;
            patsel0_low_ff  <= 0;
            patsel1_high_ff <= 0;


        end else if (wbs_stb_i && wbs_we_i && wbs_cyc_i) begin
            case (wbs_adr_i)





                4'h4: begin
                    cfg_begin_ff    <= wbs_dat_i[7:0];
                    cfg_core_sel_ff <= wbs_dat_i[16:16];
                    cfg_end_ff      <= wbs_dat_i[15:8];
                end
                4'h0:       ctrl_en_ff               <= wbs_dat_i[31: 0];
                4'h8:       patsel0_low_ff           <= wbs_dat_i[31: 0];
                4'hC:       patsel1_high_ff          <= wbs_dat_i[31: 0];


                default: begin
                end
            endcase
        end
    end


    always_ff @(posedge wb_clk_i) begin
        if (wb_rst_i) begin
            wbs_dat_o <= '0;
        end else begin
            if (wbs_stb_i && !wbs_we_i && wbs_cyc_i) begin
                wbs_dat_o <= '0;
                case (wbs_adr_i)





                    4'h4: begin
                        wbs_dat_o[7:0]   <= cfg_begin_ff;
                        wbs_dat_o[16:16] <= cfg_core_sel_ff;
                        wbs_dat_o[15:8]  <= cfg_end_ff;
                    end
                    4'h0:       wbs_dat_o[31: 0] <= ctrl_en_ff;
                    4'h8:       wbs_dat_o[31: 0] <= patsel0_low_ff;
                    4'hC:       wbs_dat_o[31: 0] <= patsel1_high_ff;


                    default:    wbs_dat_o <= 'X;
                endcase
            end
        end
    end


    always_ff @(posedge wb_clk_i) begin
        if (wb_rst_i) wbs_ack_o <= 1'b0;
        else wbs_ack_o <= wbs_stb_i && wbs_cyc_i & !wbs_ack_o;
    end






    assign cfg_begin_q_o    = cfg_begin_ff;
    assign cfg_core_sel_q_o = cfg_core_sel_ff;
    assign cfg_end_q_o      = cfg_end_ff;
    assign ctrl_en_q_o      = ctrl_en_ff;
    assign patsel0_low_q_o  = patsel0_low_ff;
    assign patsel1_high_q_o = patsel1_high_ff;


endmodule