data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/tc141_fflopx.v
data/verilator_xmls/fc82489e-fcde-4803-898c-1199add8dde7.xml
module tc141_fflopx
    (
     clk,
     rst_,
     idat,
     odat
     );

parameter WIDTH = 8;
parameter RESET_VALUE = {WIDTH{1'b0}};
parameter RESET_ENB   = 0;

input   clk, rst_;

input  [WIDTH-1:0] idat;

output [WIDTH-1:0] odat;


generate
if(RESET_ENB==1)
    begin : enb_rst
    (* keep = "true" *)reg    [WIDTH-1:0] iodat = RESET_VALUE;
    assign             odat = iodat;
    
    always @ (posedge clk or posedge rst_)
        begin
        if(rst_)iodat <= RESET_VALUE;
        else    iodat <= idat;
        end
    end
else
    begin : dis_rst
    (* keep = "true" *)reg    [WIDTH-1:0] iodat = RESET_VALUE;
    assign             odat = iodat;
    
    always @ (posedge clk)
        begin
        iodat <= idat;
        end
    end
endgenerate

endmodule
module tc141_fflopx
    (
     clk,
     rst_,
     idat,
     odat
     );


parameter WIDTH = 8;
parameter RESET_VALUE = {WIDTH{1'b0}};
parameter RESET_ENB   = 0;

input   clk, rst_;

input  [WIDTH-1:0] idat;

output [WIDTH-1:0] odat;


generate
if(RESET_ENB==1)
    begin : enb_rst
    (* keep = "true" *)reg    [WIDTH-1:0] iodat = RESET_VALUE;
    assign             odat = iodat;
    
    always @ (posedge clk or posedge rst_)
        begin
        if(rst_)iodat <= RESET_VALUE;
        else    iodat <= idat;
        end
    end
else
    begin : dis_rst
    (* keep = "true" *)reg    [WIDTH-1:0] iodat = RESET_VALUE;
    assign             odat = iodat;
    
    always @ (posedge clk)
        begin
        iodat <= idat;
        end
    end
endgenerate

endmodule