data/full_repos/permissive/449071180/tb_clk_drivers.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_clk_drivers.v:33: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_clk_drivers.v:35: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_clk_drivers.v:42: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_clk_drivers.v:44: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_clk_drivers.v:51: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_clk_drivers.v:53: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_clk_drivers.v:60: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_clk_drivers.v:62: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_clk_drivers.v:71: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_clk_drivers.v:73: Unsupported: Ignoring delay on this delayed statement.\n#5;\n^\n%Error: data/full_repos/permissive/449071180/tb_clk_drivers.v:9: Cannot find file containing module: \'clk_drivers\'\nclk_drivers port_map(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/clk_drivers\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/clk_drivers.v\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/clk_drivers.sv\n             clk_drivers\n             clk_drivers.v\n             clk_drivers.sv\n             obj_dir/clk_drivers\n             obj_dir/clk_drivers.v\n             obj_dir/clk_drivers.sv\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_clk_drivers();

reg reset_test,food_collision_test,clk_master_test,food_collision_replace_test;

wire clk_load_move_test,clk_load_move_register_test,set_eightbyeight_test,update_counters_test,clk_eightxeight_test,set_collide_test,load_test,snake_increment_test,clk_food_test,display_test;

integer count;

clk_drivers port_map(

.reset(reset_test),
.food_collision(food_collision_test),
.clk_master(clk_master_test),
.clk_load_move(clk_load_move_test),
.clk_load_move_register(clk_load_move_register_test),
.set_eightbyeight(set_eightbyeight_test),
.update_counters(update_counters_test),
.clk_eightxeight(clk_eightxeight_test),
.set_collide(set_collide_test),
.load(load_test),
.snake_increment(snake_increment_test),
.clk_food(clk_food_test),
.display(display_test),
.food_collision_replace(food_collision_replace_test)

);

initial begin
reset_test = 0;
food_collision_test = 0;
clk_master_test = 0;
food_collision_replace_test = 0;
#5;
reset_test = 1;
#5;
reset_test = 0;
end

always begin
for(count = 0; count < 16; count = count + 1) begin
clk_master_test = 0;
#5;
clk_master_test = 1;
#5;
end

food_collision_test = 1;
food_collision_replace_test = 0;
for(count = 0; count < 16; count = count + 1) begin
clk_master_test = 0;
#5;
clk_master_test = 1;
#5;
end

food_collision_test = 1;
food_collision_replace_test = 1;
for(count = 0; count < 16; count = count + 1) begin
clk_master_test = 0;
#5;
clk_master_test = 1;
#5;
end



food_collision_test = 0;
food_collision_replace_test = 1;
for(count = 0; count < 16; count = count + 1) begin
clk_master_test = 0;
#5;
clk_master_test = 1;
#5;
end
end


endmodule
module tb_clk_drivers();


reg reset_test,food_collision_test,clk_master_test,food_collision_replace_test;

wire clk_load_move_test,clk_load_move_register_test,set_eightbyeight_test,update_counters_test,clk_eightxeight_test,set_collide_test,load_test,snake_increment_test,clk_food_test,display_test;

integer count;

clk_drivers port_map(

.reset(reset_test),
.food_collision(food_collision_test),
.clk_master(clk_master_test),
.clk_load_move(clk_load_move_test),
.clk_load_move_register(clk_load_move_register_test),
.set_eightbyeight(set_eightbyeight_test),
.update_counters(update_counters_test),
.clk_eightxeight(clk_eightxeight_test),
.set_collide(set_collide_test),
.load(load_test),
.snake_increment(snake_increment_test),
.clk_food(clk_food_test),
.display(display_test),
.food_collision_replace(food_collision_replace_test)

);

initial begin
reset_test = 0;
food_collision_test = 0;
clk_master_test = 0;
food_collision_replace_test = 0;
#5;
reset_test = 1;
#5;
reset_test = 0;
end

always begin
for(count = 0; count < 16; count = count + 1) begin
clk_master_test = 0;
#5;
clk_master_test = 1;
#5;
end

food_collision_test = 1;
food_collision_replace_test = 0;
for(count = 0; count < 16; count = count + 1) begin
clk_master_test = 0;
#5;
clk_master_test = 1;
#5;
end

food_collision_test = 1;
food_collision_replace_test = 1;
for(count = 0; count < 16; count = count + 1) begin
clk_master_test = 0;
#5;
clk_master_test = 1;
#5;
end



food_collision_test = 0;
food_collision_replace_test = 1;
for(count = 0; count < 16; count = count + 1) begin
clk_master_test = 0;
#5;
clk_master_test = 1;
#5;
end
end


endmodule