data/full_repos/permissive/508059792/tb_mips.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/508059792/tb_mips.v:10: Unsupported: Ignoring delay on this delayed statement.\n forever #5 clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/508059792/tb_mips.v:15: Unsupported: Ignoring delay on this delayed statement.\n #10 res = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/508059792/tb_mips.v:17: Unsupported: Ignoring delay on this delayed statement.\n #3000 $finish;\n ^\n%Error: data/full_repos/permissive/508059792/tb_mips.v:7: Cannot find file containing module: \'mips\'\nmips mips_DUT(clk, res);\n^~~~\n        ... Looked in:\n             data/full_repos/permissive/508059792,data/full_repos/permissive/508059792/mips\n             data/full_repos/permissive/508059792,data/full_repos/permissive/508059792/mips.v\n             data/full_repos/permissive/508059792,data/full_repos/permissive/508059792/mips.sv\n             mips\n             mips.v\n             mips.sv\n             obj_dir/mips\n             obj_dir/mips.v\n             obj_dir/mips.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_mips;


reg clk;
reg res;

mips mips_DUT(clk, res);

initial
	forever #5 clk = ~clk;

initial begin
	clk = 0;
	res = 1;
	#10 res = 0;

	#3000 $finish;

end

endmodule
module tb_mips;



reg clk;
reg res;

mips mips_DUT(clk, res);

initial
	forever #5 clk = ~clk;

initial begin
	clk = 0;
	res = 1;
	#10 res = 0;

	#3000 $finish;

end

endmodule