data/full_repos/permissive/507506290/RTL_Files/Instr_mem.v
1: b'%Warning-WIDTH: data/full_repos/permissive/507506290/RTL_Files/Instr_mem.v:26: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 33 bits.\n                                                                             : ... In instance instr_mem\n  assign  o_instr =  rom[pc_addr[31:0]] ;  \n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/507506290/RTL_Files/Instr_mem.v:31: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h226020\' generates 32 bits.\n                                                                             : ... In instance instr_mem\n  rom[0] = 32\'b000000_00001_00010_01100_00000_100000;   \n         ^\n%Warning-WIDTH: data/full_repos/permissive/507506290/RTL_Files/Instr_mem.v:32: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'ha35825\' generates 32 bits.\n                                                                             : ... In instance instr_mem\n  rom[1] = 32\'b000000_00101_00011_01011_00000_100101;   \n         ^\n%Warning-WIDTH: data/full_repos/permissive/507506290/RTL_Files/Instr_mem.v:33: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h1056824\' generates 32 bits.\n                                                                             : ... In instance instr_mem\n  rom[2] = 32\'b000000_01000_00101_01101_00000_100100;  \n         ^\n%Warning-WIDTH: data/full_repos/permissive/507506290/RTL_Files/Instr_mem.v:34: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h1056824\' generates 32 bits.\n                                                                             : ... In instance instr_mem\n  rom[3] = 32\'b000000_01000_00101_01101_00000_100100;  \n         ^\n%Warning-WIDTH: data/full_repos/permissive/507506290/RTL_Files/Instr_mem.v:35: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h1056824\' generates 32 bits.\n                                                                             : ... In instance instr_mem\n  rom[4] = 32\'b000000_01000_00101_01101_00000_100100;   \n         ^\n%Warning-WIDTH: data/full_repos/permissive/507506290/RTL_Files/Instr_mem.v:36: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                             : ... In instance instr_mem\n  rom[5] = 32\'b000000_00000_00000_00000_00000_000000; \n         ^\n%Warning-WIDTH: data/full_repos/permissive/507506290/RTL_Files/Instr_mem.v:37: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                             : ... In instance instr_mem\n  rom[6] = 32\'b00000000000000000000000000000000; \n         ^\n%Warning-WIDTH: data/full_repos/permissive/507506290/RTL_Files/Instr_mem.v:38: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                             : ... In instance instr_mem\n  rom[7] = 32\'b00000000000000000000000000000000;  \n         ^\n%Warning-WIDTH: data/full_repos/permissive/507506290/RTL_Files/Instr_mem.v:39: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'ha5c0047c\' generates 32 bits.\n                                                                             : ... In instance instr_mem\n  rom[8] = 32\'b101001_01110_00000_0000010001111100;   \n         ^\n%Warning-WIDTH: data/full_repos/permissive/507506290/RTL_Files/Instr_mem.v:40: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                             : ... In instance instr_mem\n  rom[9] = 32\'b00000000000000000000000000000000; \n         ^\n%Warning-WIDTH: data/full_repos/permissive/507506290/RTL_Files/Instr_mem.v:41: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                             : ... In instance instr_mem\n  rom[10] = 32\'b00000000000000000000000000000000;  \n          ^\n%Warning-WIDTH: data/full_repos/permissive/507506290/RTL_Files/Instr_mem.v:42: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                             : ... In instance instr_mem\n  rom[11] = 32\'b00000000000000000000000000000000;  \n          ^\n%Warning-WIDTH: data/full_repos/permissive/507506290/RTL_Files/Instr_mem.v:43: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'haca40001\' generates 32 bits.\n                                                                             : ... In instance instr_mem\n  rom[12] = 32\'b101011_00101_00100_0000000000000001;  \n          ^\n%Warning-WIDTH: data/full_repos/permissive/507506290/RTL_Files/Instr_mem.v:44: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                             : ... In instance instr_mem\n  rom[13] = 32\'b00000000000000000000000000000000;  \n          ^\n%Warning-WIDTH: data/full_repos/permissive/507506290/RTL_Files/Instr_mem.v:45: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                             : ... In instance instr_mem\n  rom[14] = 32\'b00000000000000000000000000000000;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/507506290/RTL_Files/Instr_mem.v:46: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                             : ... In instance instr_mem\n  rom[15] = 32\'b00000000000000000000000000000000;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/507506290/RTL_Files/Instr_mem.v:47: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h8f020002\' generates 32 bits.\n                                                                             : ... In instance instr_mem\n  rom[16] = 32\'b100011_11000_00010_0000000000000010;  \n          ^\n%Warning-WIDTH: data/full_repos/permissive/507506290/RTL_Files/Instr_mem.v:48: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                             : ... In instance instr_mem\n  rom[17] = 32\'b00000000000000000000000000000000;  \n          ^\n%Warning-WIDTH: data/full_repos/permissive/507506290/RTL_Files/Instr_mem.v:49: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                             : ... In instance instr_mem\n  rom[18] = 32\'b00000000000000000000000000000000;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/507506290/RTL_Files/Instr_mem.v:50: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                             : ... In instance instr_mem\n  rom[19] = 32\'b00000000000000000000000000000000;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/507506290/RTL_Files/Instr_mem.v:51: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h40c820\' generates 32 bits.\n                                                                             : ... In instance instr_mem\n  rom[20] = 32\'b000000_00010_00000_11001_00000_100000;  \n          ^\n%Warning-WIDTH: data/full_repos/permissive/507506290/RTL_Files/Instr_mem.v:52: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h8f020002\' generates 32 bits.\n                                                                             : ... In instance instr_mem\n  rom[21] = 32\'b100011_11000_00010_0000000000000010;  \n          ^\n%Warning-WIDTH: data/full_repos/permissive/507506290/RTL_Files/Instr_mem.v:53: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                             : ... In instance instr_mem\n  rom[22] = 32\'b00000000000000000000000000000000;  \n          ^\n%Warning-WIDTH: data/full_repos/permissive/507506290/RTL_Files/Instr_mem.v:54: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                             : ... In instance instr_mem\n  rom[23] = 32\'b00000000000000000000000000000000;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/507506290/RTL_Files/Instr_mem.v:55: Operator ASSIGN expects 33 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h8000002\' generates 32 bits.\n                                                                             : ... In instance instr_mem\n  rom[24] = 32\'b000010_00000000000000000000000010;\n          ^\n%Error: Exiting due to 26 warning(s)\n'
module instr_mem( input [31:0] pc_addr, 
                  output [31:0] o_instr); 
	
	reg [32:0] rom[24:0];
	
		assign  o_instr =  rom[pc_addr[31:0]] ;

	initial 
		begin 

		rom[0] = 32'b000000_00001_00010_01100_00000_100000;
		rom[1] = 32'b000000_00101_00011_01011_00000_100101;
		rom[2] = 32'b000000_01000_00101_01101_00000_100100;
		rom[3] = 32'b000000_01000_00101_01101_00000_100100;
		rom[4] = 32'b000000_01000_00101_01101_00000_100100;
		rom[5] = 32'b000000_00000_00000_00000_00000_000000;	
		rom[6] = 32'b00000000000000000000000000000000; 
		rom[7] = 32'b00000000000000000000000000000000;  
		rom[8] = 32'b101001_01110_00000_0000010001111100;
		rom[9] = 32'b00000000000000000000000000000000; 
		rom[10] = 32'b00000000000000000000000000000000;  
		rom[11] = 32'b00000000000000000000000000000000;  
		rom[12] = 32'b101011_00101_00100_0000000000000001;
		rom[13] = 32'b00000000000000000000000000000000;  
		rom[14] = 32'b00000000000000000000000000000000;
		rom[15] = 32'b00000000000000000000000000000000;
		rom[16] = 32'b100011_11000_00010_0000000000000010;
		rom[17] = 32'b00000000000000000000000000000000;  
		rom[18] = 32'b00000000000000000000000000000000;
		rom[19] = 32'b00000000000000000000000000000000;
		rom[20] = 32'b000000_00010_00000_11001_00000_100000;
		rom[21] = 32'b100011_11000_00010_0000000000000010;
		rom[22] = 32'b00000000000000000000000000000000;  
		rom[23] = 32'b00000000000000000000000000000000;
		rom[24] = 32'b000010_00000000000000000000000010;

		
		end 
	
endmodule
module instr_mem( input [31:0] pc_addr, 
                  output [31:0] o_instr);
 
	
	reg [32:0] rom[24:0];
	
		assign  o_instr =  rom[pc_addr[31:0]] ;

	initial 
		begin 

		rom[0] = 32'b000000_00001_00010_01100_00000_100000;
		rom[1] = 32'b000000_00101_00011_01011_00000_100101;
		rom[2] = 32'b000000_01000_00101_01101_00000_100100;
		rom[3] = 32'b000000_01000_00101_01101_00000_100100;
		rom[4] = 32'b000000_01000_00101_01101_00000_100100;
		rom[5] = 32'b000000_00000_00000_00000_00000_000000;	
		rom[6] = 32'b00000000000000000000000000000000; 
		rom[7] = 32'b00000000000000000000000000000000;  
		rom[8] = 32'b101001_01110_00000_0000010001111100;
		rom[9] = 32'b00000000000000000000000000000000; 
		rom[10] = 32'b00000000000000000000000000000000;  
		rom[11] = 32'b00000000000000000000000000000000;  
		rom[12] = 32'b101011_00101_00100_0000000000000001;
		rom[13] = 32'b00000000000000000000000000000000;  
		rom[14] = 32'b00000000000000000000000000000000;
		rom[15] = 32'b00000000000000000000000000000000;
		rom[16] = 32'b100011_11000_00010_0000000000000010;
		rom[17] = 32'b00000000000000000000000000000000;  
		rom[18] = 32'b00000000000000000000000000000000;
		rom[19] = 32'b00000000000000000000000000000000;
		rom[20] = 32'b000000_00010_00000_11001_00000_100000;
		rom[21] = 32'b100011_11000_00010_0000000000000010;
		rom[22] = 32'b00000000000000000000000000000000;  
		rom[23] = 32'b00000000000000000000000000000000;
		rom[24] = 32'b000010_00000000000000000000000010;

		
		end 
	
endmodule