data/full_repos/permissive/435885222/sources/data_ram.v
data/verilator_xmls/483c778a-f455-4c68-a0b1-cd01aff79926.xml
module data_ram(
    input clk,
    input ce,
    input we,
    input [31:0] addr,
    input [31:0] data_in,
    output reg[31:0] data_out
    );
    reg[31:0] data_mem[0:131070];
    always @(posedge clk)begin
        if((ce!=1'b0)&&(we==1'b1)) data_mem[addr[18:2]]<=data_in;

    end
    always @(*)begin
        if(ce==1'b0) data_out<=32'h00000000;
        else if(we==1'b0) data_out<=data_mem[addr[18:2]];
        else data_out<=32'h00000000;
    end
endmodule
module data_ram(
    input clk,
    input ce,
    input we,
    input [31:0] addr,
    input [31:0] data_in,
    output reg[31:0] data_out
    );

    reg[31:0] data_mem[0:131070];
    always @(posedge clk)begin
        if((ce!=1'b0)&&(we==1'b1)) data_mem[addr[18:2]]<=data_in;

    end
    always @(*)begin
        if(ce==1'b0) data_out<=32'h00000000;
        else if(we==1'b0) data_out<=data_mem[addr[18:2]];
        else data_out<=32'h00000000;
    end
endmodule