data/full_repos/permissive/461569093/CodesForFSM/A2_RawatA.srcs/sources_1/imports/new/lfsr.v
data/verilator_xmls/66a87059-6872-4779-afef-43c9152fe078.xml
module lfsr #(
    parameter seed = 21'b11110100101100100000









    )
    (
    input clk, rst_n,
    output [20:0] Q_out,
    output reg max_tick_reg


    );


    reg [20:0] Q_state;
    wire [20:0] Q_ns;
    wire Q_fb;


    
     always @ (posedge clk)
        begin
        if (rst_n)
            begin
            Q_state <= seed; 

            end
        else
            begin
            Q_state <= Q_ns;

            end
        end

    assign Q_fb = ~(Q_state[20] ^ Q_state[18]);
    assign Q_ns = {Q_state[19:0], Q_fb};
    assign Q_out = Q_state;


    
    always @ (posedge clk)

    begin
        if (Q_out == seed)max_tick_reg = 1;
        else max_tick_reg = 0;
    end


    
endmodule
module lfsr #(
    parameter seed = 21'b11110100101100100000









    )
    (
    input clk, rst_n,
    output [20:0] Q_out,
    output reg max_tick_reg


    );



    reg [20:0] Q_state;
    wire [20:0] Q_ns;
    wire Q_fb;


    
     always @ (posedge clk)
        begin
        if (rst_n)
            begin
            Q_state <= seed; 

            end
        else
            begin
            Q_state <= Q_ns;

            end
        end

    assign Q_fb = ~(Q_state[20] ^ Q_state[18]);
    assign Q_ns = {Q_state[19:0], Q_fb};
    assign Q_out = Q_state;


    
    always @ (posedge clk)

    begin
        if (Q_out == seed)max_tick_reg = 1;
        else max_tick_reg = 0;
    end


    
endmodule