data/full_repos/permissive/480141277/shiftreg.v
data/verilator_xmls/0d2cd0a1-9880-48e2-a37d-d0b0c486500e.xml
module shiftreg (
	input 		clk,
	input 		rst,
	input 		shren,
	input 		din,
	output [10:0] dout
	);

	reg [10:0] ShiftRegister;
	
	always @ (posedge clk or posedge rst) begin
		if (rst)
			ShiftRegister <= 0;
		else if (shren)
			ShiftRegister[10:0] <= {din,ShiftRegister[10:1]};
	end
	

	assign dout = ShiftRegister[10:0];
	
endmodule
module shiftreg (
	input 		clk,
	input 		rst,
	input 		shren,
	input 		din,
	output [10:0] dout
	);


	reg [10:0] ShiftRegister;
	
	always @ (posedge clk or posedge rst) begin
		if (rst)
			ShiftRegister <= 0;
		else if (shren)
			ShiftRegister[10:0] <= {din,ShiftRegister[10:1]};
	end
	

	assign dout = ShiftRegister[10:0];
	
endmodule