data/full_repos/permissive/423547971/10 Verilog Projects Book/Section_7/ram_TB.v
1: b'%Error: Cannot find file containing module: Verilog\n        ... Looked in:\n             data/full_repos/permissive/423547971/10/Verilog\n             data/full_repos/permissive/423547971/10/Verilog.v\n             data/full_repos/permissive/423547971/10/Verilog.sv\n             Verilog\n             Verilog.v\n             Verilog.sv\n             obj_dir/Verilog\n             obj_dir/Verilog.v\n             obj_dir/Verilog.sv\n%Error: Cannot find file containing module: Projects\n%Error: Cannot find file containing module: Book/Section_7,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/10\n%Error: Cannot find file containing module: Book/Section_7/ram_TB.v\n%Error: Exiting due to 5 error(s)\n'
module ram_TB;
	reg        clock;
	reg  	   write_enable;
	reg  [3:0] address;
	reg  [7:0] data_in;
	wire [7:0] data_out;
	
	ram DUT(.clock(clock), .write_enable(write_enable), 
			.address(address), 
			.data_in(data_in), .data_out(data_out));
	
	always #2 clock = ~clock;
	
	initial begin
		$dumpfile("ram_TB.vcd");
		$dumpvars(0, ram_TB);
	end
	
	integer i;
	
	initial begin
		clock = 0;
		write_enable = 0;
		address = 4'h0;
		data_in = 8'h00;
		#9 write_enable = 1;
		
		for(i = 0; i < 16; i = i + 1) begin
			address = i;
			data_in = i * 16;
			#4;
		end
		
		write_enable = 0;
		
		for(i = 0; i < 16; i = i + 1) begin
			address = i;
			#4;
		end
		
		#4 $finish;
		
	end
	
endmodule
module ram_TB;

	reg        clock;
	reg  	   write_enable;
	reg  [3:0] address;
	reg  [7:0] data_in;
	wire [7:0] data_out;
	
	ram DUT(.clock(clock), .write_enable(write_enable), 
			.address(address), 
			.data_in(data_in), .data_out(data_out));
	
	always #2 clock = ~clock;
	
	initial begin
		$dumpfile("ram_TB.vcd");
		$dumpvars(0, ram_TB);
	end
	
	integer i;
	
	initial begin
		clock = 0;
		write_enable = 0;
		address = 4'h0;
		data_in = 8'h00;
		#9 write_enable = 1;
		
		for(i = 0; i < 16; i = i + 1) begin
			address = i;
			data_in = i * 16;
			#4;
		end
		
		write_enable = 0;
		
		for(i = 0; i < 16; i = i + 1) begin
			address = i;
			#4;
		end
		
		#4 $finish;
		
	end
	
endmodule