data/full_repos/permissive/406635962/src/rtl/cpu.v
1: b'%Error: data/full_repos/permissive/406635962/src/rtl/cpu.v:6: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/406635962/src/rtl/cpu.v:9: Define or directive not defined: \'`PC_SIZE\'\n    input [`PC_SIZE-1:0] pc_rtvec,\n           ^~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/cpu.v:12: Define or directive not defined: \'`ITCM_RAM_AW\'\n    output [`ITCM_RAM_AW-1:0] itcm_ram_addr,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/cpu.v:13: Define or directive not defined: \'`ITCM_RAM_DW\'\n    input [`ITCM_RAM_DW-1:0] itcm_ram_dout,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/cpu.v:16: Define or directive not defined: \'`DTCM_RAM_AW\'\n    output [`DTCM_RAM_AW-1:0] dtcm_ram_addr,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/cpu.v:17: Define or directive not defined: \'`DTCM_RAM_DW\'\n    output [`DTCM_RAM_DW-1:0] dtcm_ram_din,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/cpu.v:18: Define or directive not defined: \'`DTCM_RAM_MW\'\n    output [`DTCM_RAM_MW-1:0] dtcm_ram_wem,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/cpu.v:19: Define or directive not defined: \'`DTCM_RAM_DW\'\n    input [`DTCM_RAM_DW-1:0] dtcm_ram_dout,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/cpu.v:26: Define or directive not defined: \'`ITCM_ADDR_WIDTH\'\nwire [`ITCM_ADDR_WIDTH-1:0] ifu2itcm_cmd_addr;\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/cpu.v:29: Define or directive not defined: \'`ITCM_RAM_DW\'\nwire [`ITCM_RAM_DW-1:0] ifu2itcm_rsp_rdata;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/cpu.v:34: Define or directive not defined: \'`DTCM_ADDR_WIDTH\'\nwire [`DTCM_ADDR_WIDTH-1:0] lsu2dtcm_cmd_addr;\n      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/cpu.v:35: Define or directive not defined: \'`DTCM_RAM_DW\'\nwire [`DTCM_RAM_DW-1:0] lsu2dtcm_cmd_wdata;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/cpu.v:36: Define or directive not defined: \'`DTCM_RAM_MW\'\nwire [`DTCM_RAM_MW-1:0] lsu2dtcm_cmd_wmask;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/cpu.v:39: Define or directive not defined: \'`DTCM_RAM_DW\'\nwire [`DTCM_RAM_DW-1:0] lsu2dtcm_rsp_rdata;\n      ^~~~~~~~~~~~\n%Error: Exiting due to 14 error(s)\n'
module cpu (
    input [`PC_SIZE-1:0] pc_rtvec,


    output [`ITCM_RAM_AW-1:0] itcm_ram_addr,
    input [`ITCM_RAM_DW-1:0] itcm_ram_dout,

    output dtcm_ram_we,
    output [`DTCM_RAM_AW-1:0] dtcm_ram_addr,
    output [`DTCM_RAM_DW-1:0] dtcm_ram_din,
    output [`DTCM_RAM_MW-1:0] dtcm_ram_wem,
    input [`DTCM_RAM_DW-1:0] dtcm_ram_dout,
    
    input clk,
    input rst_n
);
wire ifu2itcm_cmd_valid;
wire ifu2itcm_cmd_ready;
wire [`ITCM_ADDR_WIDTH-1:0] ifu2itcm_cmd_addr;
wire ifu2itcm_rsp_valid;
wire ifu2itcm_rsp_ready;
wire [`ITCM_RAM_DW-1:0] ifu2itcm_rsp_rdata;

wire lsu2dtcm_cmd_valid;
wire lsu2dtcm_cmd_ready;
wire lsu2dtcm_cmd_read;
wire [`DTCM_ADDR_WIDTH-1:0] lsu2dtcm_cmd_addr;
wire [`DTCM_RAM_DW-1:0] lsu2dtcm_cmd_wdata;
wire [`DTCM_RAM_MW-1:0] lsu2dtcm_cmd_wmask;
wire lsu2dtcm_rsp_valid;
wire lsu2dtcm_rsp_ready;
wire [`DTCM_RAM_DW-1:0] lsu2dtcm_rsp_rdata;

core u_core (
    .pc_rtvec(pc_rtvec),
    .ifu2itcm_cmd_valid(ifu2itcm_cmd_valid),
    .ifu2itcm_cmd_ready(ifu2itcm_cmd_ready),
    .ifu2itcm_cmd_addr(ifu2itcm_cmd_addr),
    .ifu2itcm_rsp_valid(ifu2itcm_rsp_valid),
    .ifu2itcm_rsp_ready(ifu2itcm_rsp_ready),
    .ifu2itcm_rsp_rdata(ifu2itcm_rsp_rdata),
    .lsu2dtcm_cmd_valid(lsu2dtcm_cmd_valid),
    .lsu2dtcm_cmd_ready(lsu2dtcm_cmd_ready),
    .lsu2dtcm_cmd_read(lsu2dtcm_cmd_read),
    .lsu2dtcm_cmd_addr(lsu2dtcm_cmd_addr),
    .lsu2dtcm_cmd_wdata(lsu2dtcm_cmd_wdata),
    .lsu2dtcm_cmd_wmask(lsu2dtcm_cmd_wmask),
    .lsu2dtcm_rsp_valid(lsu2dtcm_rsp_valid),
    .lsu2dtcm_rsp_ready(lsu2dtcm_rsp_ready),
    .lsu2dtcm_rsp_rdata(lsu2dtcm_rsp_rdata),
    .clk(clk),
    .rst_n(rst_n)
);


itcm_ctrl u_itcm_ctrl (
    .ifu2itcm_cmd_valid(ifu2itcm_cmd_valid),
    .ifu2itcm_cmd_ready(ifu2itcm_cmd_ready),
    .ifu2itcm_cmd_addr(ifu2itcm_cmd_addr),
    .ifu2itcm_rsp_valid(ifu2itcm_rsp_valid),
    .ifu2itcm_rsp_ready(ifu2itcm_rsp_ready),
    .ifu2itcm_rsp_rdata(ifu2itcm_rsp_rdata),
    .itcm_ram_addr(itcm_ram_addr),
    .itcm_ram_dout(itcm_ram_dout),
    .clk(clk),
    .rst_n(rst_n)
);


dtcm_ctrl u_dtcm_ctrl (
    .lsu2dtcm_cmd_valid(lsu2dtcm_cmd_valid),
    .lsu2dtcm_cmd_ready(lsu2dtcm_cmd_ready),
    .lsu2dtcm_cmd_read(lsu2dtcm_cmd_read),
    .lsu2dtcm_cmd_addr(lsu2dtcm_cmd_addr),
    .lsu2dtcm_cmd_wmask(lsu2dtcm_cmd_wmask),
    .lsu2dtcm_cmd_wdata(lsu2dtcm_cmd_wdata),
    .lsu2dtcm_rsp_valid(lsu2dtcm_rsp_valid),
    .lsu2dtcm_rsp_ready(lsu2dtcm_rsp_ready),
    .lsu2dtcm_rsp_rdata(lsu2dtcm_rsp_rdata),
    .dtcm_ram_we(dtcm_ram_we),
    .dtcm_ram_addr(dtcm_ram_addr),
    .dtcm_ram_wem(dtcm_ram_wem),
    .dtcm_ram_din(dtcm_ram_din),
    .dtcm_ram_dout(dtcm_ram_dout),
    .clk(clk),
    .rst_n(rst_n)
);
endmodule
module cpu (
    input [`PC_SIZE-1:0] pc_rtvec,


    output [`ITCM_RAM_AW-1:0] itcm_ram_addr,
    input [`ITCM_RAM_DW-1:0] itcm_ram_dout,

    output dtcm_ram_we,
    output [`DTCM_RAM_AW-1:0] dtcm_ram_addr,
    output [`DTCM_RAM_DW-1:0] dtcm_ram_din,
    output [`DTCM_RAM_MW-1:0] dtcm_ram_wem,
    input [`DTCM_RAM_DW-1:0] dtcm_ram_dout,
    
    input clk,
    input rst_n
);

wire ifu2itcm_cmd_valid;
wire ifu2itcm_cmd_ready;
wire [`ITCM_ADDR_WIDTH-1:0] ifu2itcm_cmd_addr;
wire ifu2itcm_rsp_valid;
wire ifu2itcm_rsp_ready;
wire [`ITCM_RAM_DW-1:0] ifu2itcm_rsp_rdata;

wire lsu2dtcm_cmd_valid;
wire lsu2dtcm_cmd_ready;
wire lsu2dtcm_cmd_read;
wire [`DTCM_ADDR_WIDTH-1:0] lsu2dtcm_cmd_addr;
wire [`DTCM_RAM_DW-1:0] lsu2dtcm_cmd_wdata;
wire [`DTCM_RAM_MW-1:0] lsu2dtcm_cmd_wmask;
wire lsu2dtcm_rsp_valid;
wire lsu2dtcm_rsp_ready;
wire [`DTCM_RAM_DW-1:0] lsu2dtcm_rsp_rdata;

core u_core (
    .pc_rtvec(pc_rtvec),
    .ifu2itcm_cmd_valid(ifu2itcm_cmd_valid),
    .ifu2itcm_cmd_ready(ifu2itcm_cmd_ready),
    .ifu2itcm_cmd_addr(ifu2itcm_cmd_addr),
    .ifu2itcm_rsp_valid(ifu2itcm_rsp_valid),
    .ifu2itcm_rsp_ready(ifu2itcm_rsp_ready),
    .ifu2itcm_rsp_rdata(ifu2itcm_rsp_rdata),
    .lsu2dtcm_cmd_valid(lsu2dtcm_cmd_valid),
    .lsu2dtcm_cmd_ready(lsu2dtcm_cmd_ready),
    .lsu2dtcm_cmd_read(lsu2dtcm_cmd_read),
    .lsu2dtcm_cmd_addr(lsu2dtcm_cmd_addr),
    .lsu2dtcm_cmd_wdata(lsu2dtcm_cmd_wdata),
    .lsu2dtcm_cmd_wmask(lsu2dtcm_cmd_wmask),
    .lsu2dtcm_rsp_valid(lsu2dtcm_rsp_valid),
    .lsu2dtcm_rsp_ready(lsu2dtcm_rsp_ready),
    .lsu2dtcm_rsp_rdata(lsu2dtcm_rsp_rdata),
    .clk(clk),
    .rst_n(rst_n)
);


itcm_ctrl u_itcm_ctrl (
    .ifu2itcm_cmd_valid(ifu2itcm_cmd_valid),
    .ifu2itcm_cmd_ready(ifu2itcm_cmd_ready),
    .ifu2itcm_cmd_addr(ifu2itcm_cmd_addr),
    .ifu2itcm_rsp_valid(ifu2itcm_rsp_valid),
    .ifu2itcm_rsp_ready(ifu2itcm_rsp_ready),
    .ifu2itcm_rsp_rdata(ifu2itcm_rsp_rdata),
    .itcm_ram_addr(itcm_ram_addr),
    .itcm_ram_dout(itcm_ram_dout),
    .clk(clk),
    .rst_n(rst_n)
);


dtcm_ctrl u_dtcm_ctrl (
    .lsu2dtcm_cmd_valid(lsu2dtcm_cmd_valid),
    .lsu2dtcm_cmd_ready(lsu2dtcm_cmd_ready),
    .lsu2dtcm_cmd_read(lsu2dtcm_cmd_read),
    .lsu2dtcm_cmd_addr(lsu2dtcm_cmd_addr),
    .lsu2dtcm_cmd_wmask(lsu2dtcm_cmd_wmask),
    .lsu2dtcm_cmd_wdata(lsu2dtcm_cmd_wdata),
    .lsu2dtcm_rsp_valid(lsu2dtcm_rsp_valid),
    .lsu2dtcm_rsp_ready(lsu2dtcm_rsp_ready),
    .lsu2dtcm_rsp_rdata(lsu2dtcm_rsp_rdata),
    .dtcm_ram_we(dtcm_ram_we),
    .dtcm_ram_addr(dtcm_ram_addr),
    .dtcm_ram_wem(dtcm_ram_wem),
    .dtcm_ram_din(dtcm_ram_din),
    .dtcm_ram_dout(dtcm_ram_dout),
    .clk(clk),
    .rst_n(rst_n)
);
endmodule