data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/cpu/rtl/ct_rmu_top_dummy.v
data/verilator_xmls/06717de2-a5a4-4d0a-ac7c-1f4a2b1d2d6d.xml
module ct_rmu_top_dummy(
  apb_clk,
  apbrst_b,
  penable,
  perr_rmr,
  prdata_rmr,
  pready_rmr,
  psel_rmr
);


input           apb_clk;   
input           apbrst_b;  
input           penable;   
input           psel_rmr;  
output          perr_rmr;  
output  [31:0]  prdata_rmr; 
output          pready_rmr; 


reg             perr_rmr;  
reg             pready_rmr; 


wire            acc_err;   
wire            apb_clk;   
wire            apbrst_b;  
wire    [31:0]  data_out;  
wire            penable;   
wire    [31:0]  prdata_rmr; 
wire            priv_err;  
wire            psel_rmr;  


always @(posedge apb_clk or negedge apbrst_b)
begin
  if(~apbrst_b)
    pready_rmr <= 1'b0;
  else if (psel_rmr & !penable)
    pready_rmr <= 1'b1;
  else 
    pready_rmr <= 1'b0;
end

always @(posedge apb_clk or negedge apbrst_b)
begin
  if(~apbrst_b)
    perr_rmr <= 1'b0;
  else if (psel_rmr & !penable & (acc_err | priv_err))
    perr_rmr <= 1'b1;
  else
    perr_rmr <= 1'b0;
end

assign prdata_rmr[31:0] = data_out[31:0];

assign acc_err  = 1'b1;
assign priv_err = 1'b1;

assign data_out[31:0] = 32'b0;


endmodule
module ct_rmu_top_dummy(
  apb_clk,
  apbrst_b,
  penable,
  perr_rmr,
  prdata_rmr,
  pready_rmr,
  psel_rmr
);



input           apb_clk;   
input           apbrst_b;  
input           penable;   
input           psel_rmr;  
output          perr_rmr;  
output  [31:0]  prdata_rmr; 
output          pready_rmr; 


reg             perr_rmr;  
reg             pready_rmr; 


wire            acc_err;   
wire            apb_clk;   
wire            apbrst_b;  
wire    [31:0]  data_out;  
wire            penable;   
wire    [31:0]  prdata_rmr; 
wire            priv_err;  
wire            psel_rmr;  


always @(posedge apb_clk or negedge apbrst_b)
begin
  if(~apbrst_b)
    pready_rmr <= 1'b0;
  else if (psel_rmr & !penable)
    pready_rmr <= 1'b1;
  else 
    pready_rmr <= 1'b0;
end

always @(posedge apb_clk or negedge apbrst_b)
begin
  if(~apbrst_b)
    perr_rmr <= 1'b0;
  else if (psel_rmr & !penable & (acc_err | priv_err))
    perr_rmr <= 1'b1;
  else
    perr_rmr <= 1'b0;
end

assign prdata_rmr[31:0] = data_out[31:0];

assign acc_err  = 1'b1;
assign priv_err = 1'b1;

assign data_out[31:0] = 32'b0;


endmodule