data/full_repos/permissive/454430637/project_files/ADD_B_ACC.v
data/verilator_xmls/8a96d13c-9937-4e85-b076-d334eb8ee469.xml
module ADD_B_ACC(
b_in , acc_in , sum , c_o 
    );
 input [`WIDTH_5-1:0] b_in ;
 input [`WIDTH_5-1:0] acc_in ;
 output [`WIDTH_5-1:0] sum ;
 output c_o ;
 
 assign {c_o , sum } = b_in + acc_in ;
    
endmodule
module ADD_B_ACC(
b_in , acc_in , sum , c_o 
    );

 input [`WIDTH_5-1:0] b_in ;
 input [`WIDTH_5-1:0] acc_in ;
 output [`WIDTH_5-1:0] sum ;
 output c_o ;
 
 assign {c_o , sum } = b_in + acc_in ;
    
endmodule