data/full_repos/permissive/423852699/verilog/MEM_WB_reg.v
1: b"%Error: data/full_repos/permissive/423852699/verilog/MEM_WB_reg.v:21: Cannot find file containing module: 'Mux4'\n    Mux4 gpr_wdata_select_inst(\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/423852699/verilog,data/full_repos/permissive/423852699/Mux4\n             data/full_repos/permissive/423852699/verilog,data/full_repos/permissive/423852699/Mux4.v\n             data/full_repos/permissive/423852699/verilog,data/full_repos/permissive/423852699/Mux4.sv\n             Mux4\n             Mux4.v\n             Mux4.sv\n             obj_dir/Mux4\n             obj_dir/Mux4.v\n             obj_dir/Mux4.sv\n%Error: Exiting due to 1 error(s)\n"
module MEM_WB_reg (
    input wire clk,
    input wire reset,
    input wire ena,

    input wire[31:0] mem_instr_in,
    input wire[31:0] mem_pc_in,
    input wire[31:0] mem_dmem_rdata_in,
    input wire[31:0] mem_alu_result_in,

    input wire mem_GPR_we_in,
    input wire[4:0] mem_GPR_waddr_in,
    input wire[1:0] mem_GPR_wdata_select_in,

    output reg wb_GPR_we,
    output reg[4:0] wb_GPR_waddr,
    output reg[31:0] wb_GPR_wdata
);
    wire[31:0] gpr_wdata;

    Mux4 gpr_wdata_select_inst(
        .in0(mem_dmem_rdata_in),
        .in1(mem_alu_result_in),
        .in2(mem_pc_in + 8),
        .in3(32'hffffffff),
        .sel(mem_GPR_wdata_select_in),

        .out(gpr_wdata)
    );

    always @(posedge clk or negedge reset) begin
        if (!reset) begin
            wb_GPR_we <= 0;
            wb_GPR_waddr <= 0;
            wb_GPR_wdata <= 0;
        end
        else if (ena) begin
            wb_GPR_we <= ena & mem_GPR_we_in;
            wb_GPR_waddr <= mem_GPR_waddr_in;
            wb_GPR_wdata <= gpr_wdata;
        end
    end
endmodule
module MEM_WB_reg (
    input wire clk,
    input wire reset,
    input wire ena,

    input wire[31:0] mem_instr_in,
    input wire[31:0] mem_pc_in,
    input wire[31:0] mem_dmem_rdata_in,
    input wire[31:0] mem_alu_result_in,

    input wire mem_GPR_we_in,
    input wire[4:0] mem_GPR_waddr_in,
    input wire[1:0] mem_GPR_wdata_select_in,

    output reg wb_GPR_we,
    output reg[4:0] wb_GPR_waddr,
    output reg[31:0] wb_GPR_wdata
);

    wire[31:0] gpr_wdata;

    Mux4 gpr_wdata_select_inst(
        .in0(mem_dmem_rdata_in),
        .in1(mem_alu_result_in),
        .in2(mem_pc_in + 8),
        .in3(32'hffffffff),
        .sel(mem_GPR_wdata_select_in),

        .out(gpr_wdata)
    );

    always @(posedge clk or negedge reset) begin
        if (!reset) begin
            wb_GPR_we <= 0;
            wb_GPR_waddr <= 0;
            wb_GPR_wdata <= 0;
        end
        else if (ena) begin
            wb_GPR_we <= ena & mem_GPR_we_in;
            wb_GPR_waddr <= mem_GPR_waddr_in;
            wb_GPR_wdata <= gpr_wdata;
        end
    end
endmodule