data/full_repos/permissive/471424795/designs/picorv32_sram/runs/RUN_2022.03.18_20.46.21/results/synthesis/picorv32_sram.v
1: b"%Error: data/full_repos/permissive/471424795/designs/picorv32_sram/runs/RUN_2022.03.18_20.46.21/results/synthesis/picorv32_sram.v:130: Can't resolve module reference: 'sky130_fd_sc_hd__conb_1'\n  sky130_fd_sc_hd__conb_1 _0_ (\n                          ^~~\n%Error: Exiting due to 1 error(s)\n"
module picorv32_sram(clk, resetn, trap, sram_csb0, sram_csb1, mem_la_read, mem_la_write, mem_la_addr, mem_la_wdata, mem_la_wstrb, mem_rdata1, mem_instr, pcpi_valid, pcpi_insn, pcpi_rs1, pcpi_rs2, pcpi_wr, pcpi_rd, pcpi_wait, pcpi_ready, irq
, eoi, trace_valid, trace_data);
  input clk;
  output [31:0] eoi;
  input [31:0] irq;
  wire \mem_addr[0] ;
  wire \mem_addr[10] ;
  wire \mem_addr[11] ;
  wire \mem_addr[12] ;
  wire \mem_addr[13] ;
  wire \mem_addr[14] ;
  wire \mem_addr[15] ;
  wire \mem_addr[16] ;
  wire \mem_addr[17] ;
  wire \mem_addr[18] ;
  wire \mem_addr[19] ;
  wire \mem_addr[1] ;
  wire \mem_addr[20] ;
  wire \mem_addr[21] ;
  wire \mem_addr[22] ;
  wire \mem_addr[23] ;
  wire \mem_addr[24] ;
  wire \mem_addr[25] ;
  wire \mem_addr[26] ;
  wire \mem_addr[27] ;
  wire \mem_addr[28] ;
  wire \mem_addr[29] ;
  wire \mem_addr[2] ;
  wire \mem_addr[30] ;
  wire \mem_addr[31] ;
  wire \mem_addr[3] ;
  wire \mem_addr[4] ;
  wire \mem_addr[5] ;
  wire \mem_addr[6] ;
  wire \mem_addr[7] ;
  wire \mem_addr[8] ;
  wire \mem_addr[9] ;
  output mem_instr;
  output [31:0] mem_la_addr;
  output mem_la_read;
  output [31:0] mem_la_wdata;
  output mem_la_write;
  output [3:0] mem_la_wstrb;
  output [31:0] mem_rdata1;
  wire \mem_rdata[0] ;
  wire \mem_rdata[10] ;
  wire \mem_rdata[11] ;
  wire \mem_rdata[12] ;
  wire \mem_rdata[13] ;
  wire \mem_rdata[14] ;
  wire \mem_rdata[15] ;
  wire \mem_rdata[16] ;
  wire \mem_rdata[17] ;
  wire \mem_rdata[18] ;
  wire \mem_rdata[19] ;
  wire \mem_rdata[1] ;
  wire \mem_rdata[20] ;
  wire \mem_rdata[21] ;
  wire \mem_rdata[22] ;
  wire \mem_rdata[23] ;
  wire \mem_rdata[24] ;
  wire \mem_rdata[25] ;
  wire \mem_rdata[26] ;
  wire \mem_rdata[27] ;
  wire \mem_rdata[28] ;
  wire \mem_rdata[29] ;
  wire \mem_rdata[2] ;
  wire \mem_rdata[30] ;
  wire \mem_rdata[31] ;
  wire \mem_rdata[3] ;
  wire \mem_rdata[4] ;
  wire \mem_rdata[5] ;
  wire \mem_rdata[6] ;
  wire \mem_rdata[7] ;
  wire \mem_rdata[8] ;
  wire \mem_rdata[9] ;
  wire mem_valid;
  wire \mem_wdata[0] ;
  wire \mem_wdata[10] ;
  wire \mem_wdata[11] ;
  wire \mem_wdata[12] ;
  wire \mem_wdata[13] ;
  wire \mem_wdata[14] ;
  wire \mem_wdata[15] ;
  wire \mem_wdata[16] ;
  wire \mem_wdata[17] ;
  wire \mem_wdata[18] ;
  wire \mem_wdata[19] ;
  wire \mem_wdata[1] ;
  wire \mem_wdata[20] ;
  wire \mem_wdata[21] ;
  wire \mem_wdata[22] ;
  wire \mem_wdata[23] ;
  wire \mem_wdata[24] ;
  wire \mem_wdata[25] ;
  wire \mem_wdata[26] ;
  wire \mem_wdata[27] ;
  wire \mem_wdata[28] ;
  wire \mem_wdata[29] ;
  wire \mem_wdata[2] ;
  wire \mem_wdata[30] ;
  wire \mem_wdata[31] ;
  wire \mem_wdata[3] ;
  wire \mem_wdata[4] ;
  wire \mem_wdata[5] ;
  wire \mem_wdata[6] ;
  wire \mem_wdata[7] ;
  wire \mem_wdata[8] ;
  wire \mem_wdata[9] ;
  wire \mem_wstrb[0] ;
  wire \mem_wstrb[1] ;
  wire \mem_wstrb[2] ;
  wire \mem_wstrb[3] ;
  output [31:0] pcpi_insn;
  input [31:0] pcpi_rd;
  input pcpi_ready;
  output [31:0] pcpi_rs1;
  output [31:0] pcpi_rs2;
  output pcpi_valid;
  input pcpi_wait;
  input pcpi_wr;
  input resetn;
  input sram_csb0;
  input sram_csb1;
  output [35:0] trace_data;
  output trace_valid;
  output trap;
  sky130_fd_sc_hd__conb_1 _0_ (
    .LO(mem_instr)
  );
  picorv32_woready cpu (
    .clk(clk),
    .eoi(eoi),
    .irq(irq),
    .mem_addr({ \mem_addr[31] , \mem_addr[30] , \mem_addr[29] , \mem_addr[28] , \mem_addr[27] , \mem_addr[26] , \mem_addr[25] , \mem_addr[24] , \mem_addr[23] , \mem_addr[22] , \mem_addr[21] , \mem_addr[20] , \mem_addr[19] , \mem_addr[18] , \mem_addr[17] , \mem_addr[16] , \mem_addr[15] , \mem_addr[14] , \mem_addr[13] , \mem_addr[12] , \mem_addr[11] , \mem_addr[10] , \mem_addr[9] , \mem_addr[8] , \mem_addr[7] , \mem_addr[6] , \mem_addr[5] , \mem_addr[4] , \mem_addr[3] , \mem_addr[2] , \mem_addr[1] , \mem_addr[0]  }),
    .mem_la_addr(mem_la_addr),
    .mem_la_read(mem_la_read),
    .mem_la_wdata(mem_la_wdata),
    .mem_la_write(mem_la_write),
    .mem_la_wstrb(mem_la_wstrb),
    .mem_rdata({ \mem_rdata[31] , \mem_rdata[30] , \mem_rdata[29] , \mem_rdata[28] , \mem_rdata[27] , \mem_rdata[26] , \mem_rdata[25] , \mem_rdata[24] , \mem_rdata[23] , \mem_rdata[22] , \mem_rdata[21] , \mem_rdata[20] , \mem_rdata[19] , \mem_rdata[18] , \mem_rdata[17] , \mem_rdata[16] , \mem_rdata[15] , \mem_rdata[14] , \mem_rdata[13] , \mem_rdata[12] , \mem_rdata[11] , \mem_rdata[10] , \mem_rdata[9] , \mem_rdata[8] , \mem_rdata[7] , \mem_rdata[6] , \mem_rdata[5] , \mem_rdata[4] , \mem_rdata[3] , \mem_rdata[2] , \mem_rdata[1] , \mem_rdata[0]  }),
    .mem_valid(mem_valid),
    .mem_wdata({ \mem_wdata[31] , \mem_wdata[30] , \mem_wdata[29] , \mem_wdata[28] , \mem_wdata[27] , \mem_wdata[26] , \mem_wdata[25] , \mem_wdata[24] , \mem_wdata[23] , \mem_wdata[22] , \mem_wdata[21] , \mem_wdata[20] , \mem_wdata[19] , \mem_wdata[18] , \mem_wdata[17] , \mem_wdata[16] , \mem_wdata[15] , \mem_wdata[14] , \mem_wdata[13] , \mem_wdata[12] , \mem_wdata[11] , \mem_wdata[10] , \mem_wdata[9] , \mem_wdata[8] , \mem_wdata[7] , \mem_wdata[6] , \mem_wdata[5] , \mem_wdata[4] , \mem_wdata[3] , \mem_wdata[2] , \mem_wdata[1] , \mem_wdata[0]  }),
    .mem_wstrb({ \mem_wstrb[3] , \mem_wstrb[2] , \mem_wstrb[1] , \mem_wstrb[0]  }),
    .pcpi_insn(pcpi_insn),
    .pcpi_rd(pcpi_rd),
    .pcpi_ready(pcpi_ready),
    .pcpi_rs1(pcpi_rs1),
    .pcpi_rs2(pcpi_rs2),
    .pcpi_valid(pcpi_valid),
    .pcpi_wait(pcpi_wait),
    .pcpi_wr(pcpi_wr),
    .resetn(resetn),
    .trace_data(trace_data),
    .trace_valid(trace_valid),
    .trap(trap)
  );
  sky130_sram_2kbyte_1rw1r_32x512_8 sram (
    .addr0({ \mem_addr[8] , \mem_addr[7] , \mem_addr[6] , \mem_addr[5] , \mem_addr[4] , \mem_addr[3] , \mem_addr[2] , \mem_addr[1] , \mem_addr[0]  }),
    .addr1({ \mem_addr[17] , \mem_addr[16] , \mem_addr[15] , \mem_addr[14] , \mem_addr[13] , \mem_addr[12] , \mem_addr[11] , \mem_addr[10] , \mem_addr[9]  }),
    .clk0(clk),
    .clk1(clk),
    .csb0(sram_csb0),
    .csb1(sram_csb1),
    .din0({ \mem_wdata[31] , \mem_wdata[30] , \mem_wdata[29] , \mem_wdata[28] , \mem_wdata[27] , \mem_wdata[26] , \mem_wdata[25] , \mem_wdata[24] , \mem_wdata[23] , \mem_wdata[22] , \mem_wdata[21] , \mem_wdata[20] , \mem_wdata[19] , \mem_wdata[18] , \mem_wdata[17] , \mem_wdata[16] , \mem_wdata[15] , \mem_wdata[14] , \mem_wdata[13] , \mem_wdata[12] , \mem_wdata[11] , \mem_wdata[10] , \mem_wdata[9] , \mem_wdata[8] , \mem_wdata[7] , \mem_wdata[6] , \mem_wdata[5] , \mem_wdata[4] , \mem_wdata[3] , \mem_wdata[2] , \mem_wdata[1] , \mem_wdata[0]  }),
    .dout0({ \mem_rdata[31] , \mem_rdata[30] , \mem_rdata[29] , \mem_rdata[28] , \mem_rdata[27] , \mem_rdata[26] , \mem_rdata[25] , \mem_rdata[24] , \mem_rdata[23] , \mem_rdata[22] , \mem_rdata[21] , \mem_rdata[20] , \mem_rdata[19] , \mem_rdata[18] , \mem_rdata[17] , \mem_rdata[16] , \mem_rdata[15] , \mem_rdata[14] , \mem_rdata[13] , \mem_rdata[12] , \mem_rdata[11] , \mem_rdata[10] , \mem_rdata[9] , \mem_rdata[8] , \mem_rdata[7] , \mem_rdata[6] , \mem_rdata[5] , \mem_rdata[4] , \mem_rdata[3] , \mem_rdata[2] , \mem_rdata[1] , \mem_rdata[0]  }),
    .dout1(mem_rdata1),
    .web0(mem_valid),
    .wmask0({ \mem_wstrb[3] , \mem_wstrb[2] , \mem_wstrb[1] , \mem_wstrb[0]  })
  );
endmodule
module picorv32_sram(clk, resetn, trap, sram_csb0, sram_csb1, mem_la_read, mem_la_write, mem_la_addr, mem_la_wdata, mem_la_wstrb, mem_rdata1, mem_instr, pcpi_valid, pcpi_insn, pcpi_rs1, pcpi_rs2, pcpi_wr, pcpi_rd, pcpi_wait, pcpi_ready, irq
, eoi, trace_valid, trace_data);

  input clk;
  output [31:0] eoi;
  input [31:0] irq;
  wire \mem_addr[0] ;
  wire \mem_addr[10] ;
  wire \mem_addr[11] ;
  wire \mem_addr[12] ;
  wire \mem_addr[13] ;
  wire \mem_addr[14] ;
  wire \mem_addr[15] ;
  wire \mem_addr[16] ;
  wire \mem_addr[17] ;
  wire \mem_addr[18] ;
  wire \mem_addr[19] ;
  wire \mem_addr[1] ;
  wire \mem_addr[20] ;
  wire \mem_addr[21] ;
  wire \mem_addr[22] ;
  wire \mem_addr[23] ;
  wire \mem_addr[24] ;
  wire \mem_addr[25] ;
  wire \mem_addr[26] ;
  wire \mem_addr[27] ;
  wire \mem_addr[28] ;
  wire \mem_addr[29] ;
  wire \mem_addr[2] ;
  wire \mem_addr[30] ;
  wire \mem_addr[31] ;
  wire \mem_addr[3] ;
  wire \mem_addr[4] ;
  wire \mem_addr[5] ;
  wire \mem_addr[6] ;
  wire \mem_addr[7] ;
  wire \mem_addr[8] ;
  wire \mem_addr[9] ;
  output mem_instr;
  output [31:0] mem_la_addr;
  output mem_la_read;
  output [31:0] mem_la_wdata;
  output mem_la_write;
  output [3:0] mem_la_wstrb;
  output [31:0] mem_rdata1;
  wire \mem_rdata[0] ;
  wire \mem_rdata[10] ;
  wire \mem_rdata[11] ;
  wire \mem_rdata[12] ;
  wire \mem_rdata[13] ;
  wire \mem_rdata[14] ;
  wire \mem_rdata[15] ;
  wire \mem_rdata[16] ;
  wire \mem_rdata[17] ;
  wire \mem_rdata[18] ;
  wire \mem_rdata[19] ;
  wire \mem_rdata[1] ;
  wire \mem_rdata[20] ;
  wire \mem_rdata[21] ;
  wire \mem_rdata[22] ;
  wire \mem_rdata[23] ;
  wire \mem_rdata[24] ;
  wire \mem_rdata[25] ;
  wire \mem_rdata[26] ;
  wire \mem_rdata[27] ;
  wire \mem_rdata[28] ;
  wire \mem_rdata[29] ;
  wire \mem_rdata[2] ;
  wire \mem_rdata[30] ;
  wire \mem_rdata[31] ;
  wire \mem_rdata[3] ;
  wire \mem_rdata[4] ;
  wire \mem_rdata[5] ;
  wire \mem_rdata[6] ;
  wire \mem_rdata[7] ;
  wire \mem_rdata[8] ;
  wire \mem_rdata[9] ;
  wire mem_valid;
  wire \mem_wdata[0] ;
  wire \mem_wdata[10] ;
  wire \mem_wdata[11] ;
  wire \mem_wdata[12] ;
  wire \mem_wdata[13] ;
  wire \mem_wdata[14] ;
  wire \mem_wdata[15] ;
  wire \mem_wdata[16] ;
  wire \mem_wdata[17] ;
  wire \mem_wdata[18] ;
  wire \mem_wdata[19] ;
  wire \mem_wdata[1] ;
  wire \mem_wdata[20] ;
  wire \mem_wdata[21] ;
  wire \mem_wdata[22] ;
  wire \mem_wdata[23] ;
  wire \mem_wdata[24] ;
  wire \mem_wdata[25] ;
  wire \mem_wdata[26] ;
  wire \mem_wdata[27] ;
  wire \mem_wdata[28] ;
  wire \mem_wdata[29] ;
  wire \mem_wdata[2] ;
  wire \mem_wdata[30] ;
  wire \mem_wdata[31] ;
  wire \mem_wdata[3] ;
  wire \mem_wdata[4] ;
  wire \mem_wdata[5] ;
  wire \mem_wdata[6] ;
  wire \mem_wdata[7] ;
  wire \mem_wdata[8] ;
  wire \mem_wdata[9] ;
  wire \mem_wstrb[0] ;
  wire \mem_wstrb[1] ;
  wire \mem_wstrb[2] ;
  wire \mem_wstrb[3] ;
  output [31:0] pcpi_insn;
  input [31:0] pcpi_rd;
  input pcpi_ready;
  output [31:0] pcpi_rs1;
  output [31:0] pcpi_rs2;
  output pcpi_valid;
  input pcpi_wait;
  input pcpi_wr;
  input resetn;
  input sram_csb0;
  input sram_csb1;
  output [35:0] trace_data;
  output trace_valid;
  output trap;
  sky130_fd_sc_hd__conb_1 _0_ (
    .LO(mem_instr)
  );
  picorv32_woready cpu (
    .clk(clk),
    .eoi(eoi),
    .irq(irq),
    .mem_addr({ \mem_addr[31] , \mem_addr[30] , \mem_addr[29] , \mem_addr[28] , \mem_addr[27] , \mem_addr[26] , \mem_addr[25] , \mem_addr[24] , \mem_addr[23] , \mem_addr[22] , \mem_addr[21] , \mem_addr[20] , \mem_addr[19] , \mem_addr[18] , \mem_addr[17] , \mem_addr[16] , \mem_addr[15] , \mem_addr[14] , \mem_addr[13] , \mem_addr[12] , \mem_addr[11] , \mem_addr[10] , \mem_addr[9] , \mem_addr[8] , \mem_addr[7] , \mem_addr[6] , \mem_addr[5] , \mem_addr[4] , \mem_addr[3] , \mem_addr[2] , \mem_addr[1] , \mem_addr[0]  }),
    .mem_la_addr(mem_la_addr),
    .mem_la_read(mem_la_read),
    .mem_la_wdata(mem_la_wdata),
    .mem_la_write(mem_la_write),
    .mem_la_wstrb(mem_la_wstrb),
    .mem_rdata({ \mem_rdata[31] , \mem_rdata[30] , \mem_rdata[29] , \mem_rdata[28] , \mem_rdata[27] , \mem_rdata[26] , \mem_rdata[25] , \mem_rdata[24] , \mem_rdata[23] , \mem_rdata[22] , \mem_rdata[21] , \mem_rdata[20] , \mem_rdata[19] , \mem_rdata[18] , \mem_rdata[17] , \mem_rdata[16] , \mem_rdata[15] , \mem_rdata[14] , \mem_rdata[13] , \mem_rdata[12] , \mem_rdata[11] , \mem_rdata[10] , \mem_rdata[9] , \mem_rdata[8] , \mem_rdata[7] , \mem_rdata[6] , \mem_rdata[5] , \mem_rdata[4] , \mem_rdata[3] , \mem_rdata[2] , \mem_rdata[1] , \mem_rdata[0]  }),
    .mem_valid(mem_valid),
    .mem_wdata({ \mem_wdata[31] , \mem_wdata[30] , \mem_wdata[29] , \mem_wdata[28] , \mem_wdata[27] , \mem_wdata[26] , \mem_wdata[25] , \mem_wdata[24] , \mem_wdata[23] , \mem_wdata[22] , \mem_wdata[21] , \mem_wdata[20] , \mem_wdata[19] , \mem_wdata[18] , \mem_wdata[17] , \mem_wdata[16] , \mem_wdata[15] , \mem_wdata[14] , \mem_wdata[13] , \mem_wdata[12] , \mem_wdata[11] , \mem_wdata[10] , \mem_wdata[9] , \mem_wdata[8] , \mem_wdata[7] , \mem_wdata[6] , \mem_wdata[5] , \mem_wdata[4] , \mem_wdata[3] , \mem_wdata[2] , \mem_wdata[1] , \mem_wdata[0]  }),
    .mem_wstrb({ \mem_wstrb[3] , \mem_wstrb[2] , \mem_wstrb[1] , \mem_wstrb[0]  }),
    .pcpi_insn(pcpi_insn),
    .pcpi_rd(pcpi_rd),
    .pcpi_ready(pcpi_ready),
    .pcpi_rs1(pcpi_rs1),
    .pcpi_rs2(pcpi_rs2),
    .pcpi_valid(pcpi_valid),
    .pcpi_wait(pcpi_wait),
    .pcpi_wr(pcpi_wr),
    .resetn(resetn),
    .trace_data(trace_data),
    .trace_valid(trace_valid),
    .trap(trap)
  );
  sky130_sram_2kbyte_1rw1r_32x512_8 sram (
    .addr0({ \mem_addr[8] , \mem_addr[7] , \mem_addr[6] , \mem_addr[5] , \mem_addr[4] , \mem_addr[3] , \mem_addr[2] , \mem_addr[1] , \mem_addr[0]  }),
    .addr1({ \mem_addr[17] , \mem_addr[16] , \mem_addr[15] , \mem_addr[14] , \mem_addr[13] , \mem_addr[12] , \mem_addr[11] , \mem_addr[10] , \mem_addr[9]  }),
    .clk0(clk),
    .clk1(clk),
    .csb0(sram_csb0),
    .csb1(sram_csb1),
    .din0({ \mem_wdata[31] , \mem_wdata[30] , \mem_wdata[29] , \mem_wdata[28] , \mem_wdata[27] , \mem_wdata[26] , \mem_wdata[25] , \mem_wdata[24] , \mem_wdata[23] , \mem_wdata[22] , \mem_wdata[21] , \mem_wdata[20] , \mem_wdata[19] , \mem_wdata[18] , \mem_wdata[17] , \mem_wdata[16] , \mem_wdata[15] , \mem_wdata[14] , \mem_wdata[13] , \mem_wdata[12] , \mem_wdata[11] , \mem_wdata[10] , \mem_wdata[9] , \mem_wdata[8] , \mem_wdata[7] , \mem_wdata[6] , \mem_wdata[5] , \mem_wdata[4] , \mem_wdata[3] , \mem_wdata[2] , \mem_wdata[1] , \mem_wdata[0]  }),
    .dout0({ \mem_rdata[31] , \mem_rdata[30] , \mem_rdata[29] , \mem_rdata[28] , \mem_rdata[27] , \mem_rdata[26] , \mem_rdata[25] , \mem_rdata[24] , \mem_rdata[23] , \mem_rdata[22] , \mem_rdata[21] , \mem_rdata[20] , \mem_rdata[19] , \mem_rdata[18] , \mem_rdata[17] , \mem_rdata[16] , \mem_rdata[15] , \mem_rdata[14] , \mem_rdata[13] , \mem_rdata[12] , \mem_rdata[11] , \mem_rdata[10] , \mem_rdata[9] , \mem_rdata[8] , \mem_rdata[7] , \mem_rdata[6] , \mem_rdata[5] , \mem_rdata[4] , \mem_rdata[3] , \mem_rdata[2] , \mem_rdata[1] , \mem_rdata[0]  }),
    .dout1(mem_rdata1),
    .web0(mem_valid),
    .wmask0({ \mem_wstrb[3] , \mem_wstrb[2] , \mem_wstrb[1] , \mem_wstrb[0]  })
  );
endmodule