data/full_repos/permissive/505278364/Control.v
data/verilator_xmls/dae9de59-6b37-4fb4-9637-4fb8e7969e53.xml
module Control(OpCode, Funct,
	PCSrc, Branch, RegWrite, RegDst, 
	MemRead, MemWrite, MemtoReg, 
	ALUSrc1, ALUSrc2, ExtOp, LuOp);
	input [5:0] OpCode;
	input [5:0] Funct;
	output [1:0] PCSrc;
	output Branch;
	output RegWrite;
	output [1:0] RegDst;
	output MemRead;
	output MemWrite;
	output [1:0] MemtoReg;
	output ALUSrc1;
	output ALUSrc2;
	output ExtOp;
	output LuOp;
	


	assign PCSrc=  (OpCode==6'b00_0010)?(2'b01):
				   (OpCode==6'b00_0011)?(2'b01):
				   (OpCode==6'b0)?(
						(Funct==6'b00_1000)?(2'b10):
						(Funct==6'b00_1001)?(2'b10):
						2'b00
						):2'b00;
	assign Branch= (OpCode==6'b00_0100)?(1'b1):
				   1'b0;
	assign RegWrite=   (OpCode==6'b10_1011)?(1'b0):
					   (OpCode==6'b00_0100)?(1'b0):
					   (OpCode==6'b00_0010)?(1'b0):
					   (OpCode==6'b0)?(
							(Funct==6'b00_1000)?(1'b0):
							1'b1
							):1'b1;
	assign RegDst= (OpCode==6'b10_0011)?(2'b00):
				   (OpCode==6'b00_1111)?(2'b00):
				   (OpCode==6'b00_1000)?(2'b00):
				   (OpCode==6'b00_1001)?(2'b00):
				   (OpCode==6'b00_1100)?(2'b00):
				   (OpCode==6'b00_1010)?(2'b00):
				   (OpCode==6'b00_1011)?(2'b00):
				   (OpCode==6'b00_0011)?(2'b10):
				   2'b01;
	assign MemRead=(OpCode==6'b10_0011)?(1'b1):
				   1'b0;
    assign MemWrite=(OpCode==6'b10_1011)?(1'b1):
					1'b0;
	assign MemtoReg=   (OpCode==6'b10_0011)?(2'b01):
					   (OpCode==6'b00_0011)?(2'b10):
					   (OpCode==6'b0)?(
							(Funct==6'b00_1001)?(2'b10):
							2'b00
							):2'b00;
	assign ALUSrc1=(OpCode==6'b0)?(
						(Funct==6'b0)?(1'b1):
						(Funct==6'b00_0010)?(1'b1):
						(Funct==6'b00_0011)?(1'b1):
						1'b0
						):1'b0;
	assign ALUSrc2=(OpCode==6'b10_0011)?(1'b1):
				   (OpCode==6'b10_1011)?(1'b1):
				   (OpCode==6'b00_1111)?(1'b1):
				   (OpCode==6'b00_1000)?(1'b1):
				   (OpCode==6'b00_1001)?(1'b1):
				   (OpCode==6'b00_1100)?(1'b1):
				   (OpCode==6'b00_1010)?(1'b1):
				   (OpCode==6'b00_1011)?(1'b1):
				   1'b0;
	assign ExtOp=  (OpCode==6'b00_1100)?(1'b0):
				   1'b1;
	assign LuOp=   (OpCode==6'b00_1111)?(1'b1):
				   1'b0;
	     


	
endmodule
module Control(OpCode, Funct,
	PCSrc, Branch, RegWrite, RegDst, 
	MemRead, MemWrite, MemtoReg, 
	ALUSrc1, ALUSrc2, ExtOp, LuOp);

	input [5:0] OpCode;
	input [5:0] Funct;
	output [1:0] PCSrc;
	output Branch;
	output RegWrite;
	output [1:0] RegDst;
	output MemRead;
	output MemWrite;
	output [1:0] MemtoReg;
	output ALUSrc1;
	output ALUSrc2;
	output ExtOp;
	output LuOp;
	


	assign PCSrc=  (OpCode==6'b00_0010)?(2'b01):
				   (OpCode==6'b00_0011)?(2'b01):
				   (OpCode==6'b0)?(
						(Funct==6'b00_1000)?(2'b10):
						(Funct==6'b00_1001)?(2'b10):
						2'b00
						):2'b00;
	assign Branch= (OpCode==6'b00_0100)?(1'b1):
				   1'b0;
	assign RegWrite=   (OpCode==6'b10_1011)?(1'b0):
					   (OpCode==6'b00_0100)?(1'b0):
					   (OpCode==6'b00_0010)?(1'b0):
					   (OpCode==6'b0)?(
							(Funct==6'b00_1000)?(1'b0):
							1'b1
							):1'b1;
	assign RegDst= (OpCode==6'b10_0011)?(2'b00):
				   (OpCode==6'b00_1111)?(2'b00):
				   (OpCode==6'b00_1000)?(2'b00):
				   (OpCode==6'b00_1001)?(2'b00):
				   (OpCode==6'b00_1100)?(2'b00):
				   (OpCode==6'b00_1010)?(2'b00):
				   (OpCode==6'b00_1011)?(2'b00):
				   (OpCode==6'b00_0011)?(2'b10):
				   2'b01;
	assign MemRead=(OpCode==6'b10_0011)?(1'b1):
				   1'b0;
    assign MemWrite=(OpCode==6'b10_1011)?(1'b1):
					1'b0;
	assign MemtoReg=   (OpCode==6'b10_0011)?(2'b01):
					   (OpCode==6'b00_0011)?(2'b10):
					   (OpCode==6'b0)?(
							(Funct==6'b00_1001)?(2'b10):
							2'b00
							):2'b00;
	assign ALUSrc1=(OpCode==6'b0)?(
						(Funct==6'b0)?(1'b1):
						(Funct==6'b00_0010)?(1'b1):
						(Funct==6'b00_0011)?(1'b1):
						1'b0
						):1'b0;
	assign ALUSrc2=(OpCode==6'b10_0011)?(1'b1):
				   (OpCode==6'b10_1011)?(1'b1):
				   (OpCode==6'b00_1111)?(1'b1):
				   (OpCode==6'b00_1000)?(1'b1):
				   (OpCode==6'b00_1001)?(1'b1):
				   (OpCode==6'b00_1100)?(1'b1):
				   (OpCode==6'b00_1010)?(1'b1):
				   (OpCode==6'b00_1011)?(1'b1):
				   1'b0;
	assign ExtOp=  (OpCode==6'b00_1100)?(1'b0):
				   1'b1;
	assign LuOp=   (OpCode==6'b00_1111)?(1'b1):
				   1'b0;
	     


	
endmodule