data/full_repos/permissive/521337848/Hardware/procesor/memoryModule.v
1: b"%Error: data/full_repos/permissive/521337848/Hardware/procesor/memoryModule.v:65: Cannot find file containing module: 'toMem'\ntoMem tM(\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/521337848/Hardware/procesor,data/full_repos/permissive/521337848/toMem\n             data/full_repos/permissive/521337848/Hardware/procesor,data/full_repos/permissive/521337848/toMem.v\n             data/full_repos/permissive/521337848/Hardware/procesor,data/full_repos/permissive/521337848/toMem.sv\n             toMem\n             toMem.v\n             toMem.sv\n             obj_dir/toMem\n             obj_dir/toMem.v\n             obj_dir/toMem.sv\n%Error: data/full_repos/permissive/521337848/Hardware/procesor/memoryModule.v:89: Cannot find file containing module: 'toRAMCollect'\ntoRAMCollect trC(\n^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module outbuffer(
	input clk,
	input rst,
	
	input[31:0] in,
	output reg[31:0] out1,
	output reg[31:0] out2,
	output reg[31:0] out3,
	output reg[31:0] out4
);

reg[31:0] r_out1;
reg[31:0] r_out2;
reg[31:0] r_out3;
reg[31:0] r_out4;

always@(posedge clk or posedge rst)begin
	if(rst) out1 <= 0;
	else out1 <= r_out1;
end

always@(posedge clk or posedge rst)begin
	if(rst) out2 <= 0;
	else out2 <= r_out2;
end

always@(posedge clk or posedge rst)begin
	if(rst) out3 <= 0;
	else out3 <= r_out3;
end

always@(posedge clk or posedge rst)begin
	if(rst) out4 <= 0;
	else out4 <= r_out4;
end

always@(*)begin
	r_out1 = 0;
	r_out2 = 0;
	r_out3 = 0;
	r_out4 = 0;
	
	case(in[31:30]) 
		0: r_out4 = in;
		1: r_out1 = in;
		2: r_out2 = in;
		3: r_out3 = in;
	endcase
end

endmodule
module outbuffer(
	input clk,
	input rst,
	
	input[31:0] in,
	output reg[31:0] out1,
	output reg[31:0] out2,
	output reg[31:0] out3,
	output reg[31:0] out4
);


reg[31:0] r_out1;
reg[31:0] r_out2;
reg[31:0] r_out3;
reg[31:0] r_out4;

always@(posedge clk or posedge rst)begin
	if(rst) out1 <= 0;
	else out1 <= r_out1;
end

always@(posedge clk or posedge rst)begin
	if(rst) out2 <= 0;
	else out2 <= r_out2;
end

always@(posedge clk or posedge rst)begin
	if(rst) out3 <= 0;
	else out3 <= r_out3;
end

always@(posedge clk or posedge rst)begin
	if(rst) out4 <= 0;
	else out4 <= r_out4;
end

always@(*)begin
	r_out1 = 0;
	r_out2 = 0;
	r_out3 = 0;
	r_out4 = 0;
	
	case(in[31:30]) 
		0: r_out4 = in;
		1: r_out1 = in;
		2: r_out2 = in;
		3: r_out3 = in;
	endcase
end

endmodule