data/full_repos/permissive/493019833/test/testcase/firrtl/ZeroWidthIOModule/reference/ZeroWidthIOModule.v
data/verilator_xmls/c87e0b4a-aaad-4548-bf78-837cbb6b1a20.xml
module ZeroWidthIOModule(
    input clock,
    input reset,
    input [2:0] io_otherIn,
    output [2:0] io_otherOut
);
    assign io_otherOut = io_otherIn;
endmodule
module ZeroWidthIOModule(
    input clock,
    input reset,
    input [2:0] io_otherIn,
    output [2:0] io_otherOut
);

    assign io_otherOut = io_otherIn;
endmodule