data/full_repos/permissive/450962776/processor/src/and_SLTI_type.v
data/verilator_xmls/034398c7-e8bf-4a6f-8b63-40f079400f61.xml
module and_SLTI_type(op,F);
input [3:0] op;
output F;
wire a;

not(a,op[3]);
and(F,a,op[2],op[1],op[0]);
endmodule
module and_SLTI_type(op,F);

input [3:0] op;
output F;
wire a;

not(a,op[3]);
and(F,a,op[2],op[1],op[0]);
endmodule