data/full_repos/permissive/506562943/HDLBits/Circuits/Sequential Logic/Latches and Flip-Flops/exams_ece241_2014_q4.v
1: b'%Error: Cannot find file containing module: Logic/Latches\n        ... Looked in:\n             data/full_repos/permissive/506562943/HDLBits/Circuits/Sequential/Logic/Latches\n             data/full_repos/permissive/506562943/HDLBits/Circuits/Sequential/Logic/Latches.v\n             data/full_repos/permissive/506562943/HDLBits/Circuits/Sequential/Logic/Latches.sv\n             Logic/Latches\n             Logic/Latches.v\n             Logic/Latches.sv\n             obj_dir/Logic/Latches\n             obj_dir/Logic/Latches.v\n             obj_dir/Logic/Latches.sv\n%Error: Cannot find file containing module: and\n%Error: Cannot find file containing module: Flip-Flops,data/full_repos/permissive/506562943\n%Error: Cannot find file containing module: data/full_repos/permissive/506562943/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Flip-Flops/exams_ece241_2014_q4.v\n%Error: Exiting due to 5 error(s)\n'
module top_module (
    input clk,
    input x,
    output z
);

    wire q1, q2, q3;
    assign z = !(q1 | q2 | q3);
    
    mydff u_mydff_1(q1 ^ x, clk, q1);
    mydff u_mydff_2(!q2 & x, clk, q2);
    mydff u_mydff_3(!q3 | x, clk, q3);

endmodule
module top_module (
    input clk,
    input x,
    output z
);


    wire q1, q2, q3;
    assign z = !(q1 | q2 | q3);
    
    mydff u_mydff_1(q1 ^ x, clk, q1);
    mydff u_mydff_2(!q2 & x, clk, q2);
    mydff u_mydff_3(!q3 | x, clk, q3);

endmodule