data/full_repos/permissive/433621701/generic_CB_array/generic_CB_array.v
data/verilator_xmls/fd06e278-bb93-4e8c-8afc-57a7fd90af91.xml
module two_in_and_gate(input a, b, output reg z);
    always @(a or b)
    begin
        z = a & b;
    end
endmodule
module two_in_and_gate(input a, b, output reg z);

    always @(a or b)
    begin
        z = a & b;
    end
endmodule