data/full_repos/permissive/468755927/verilog/rtl/step_motor_controller.v
1: b'%Warning-WIDTH: data/full_repos/permissive/468755927/verilog/rtl/step_motor_controller.v:345: Operator SUB expects 24 bits on the LHS, but LHS\'s VARREF \'cycles\' generates 16 bits.\n                                                                                            : ... In instance step_motor_controller.i_step_motor_controller_registers\n  assign next_cycles = cycles - 1\'b1;\n                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/468755927/verilog/rtl/step_motor_controller.v:372: Operator ASSIGNDLY expects 21 bits on the Assign RHS, but Assign RHS\'s CONST \'11\'h0\' generates 11 bits.\n                                                                                            : ... In instance step_motor_controller.i_step_motor_controller_registers\n            wbs_dat_o[28:8] <= 11\'b0;\n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/468755927/verilog/rtl/step_motor_controller.v:432: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'next_cycles\' generates 24 bits.\n                                                                                            : ... In instance step_motor_controller.i_step_motor_controller_registers\n        cycles <= next_cycles;\n               ^~\n%Error: data/full_repos/permissive/468755927/verilog/rtl/step_motor_controller.v:60: Cannot find file containing module: \'prescaler\'\n  prescaler #(\n  ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/468755927/verilog/rtl,data/full_repos/permissive/468755927/prescaler\n             data/full_repos/permissive/468755927/verilog/rtl,data/full_repos/permissive/468755927/prescaler.v\n             data/full_repos/permissive/468755927/verilog/rtl,data/full_repos/permissive/468755927/prescaler.sv\n             prescaler\n             prescaler.v\n             prescaler.sv\n             obj_dir/prescaler\n             obj_dir/prescaler.v\n             obj_dir/prescaler.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module pwm_generator (
  input  wire        rst_n      ,
  input  wire        clk        ,
  input  wire        clear_n    ,
  input  wire [7:0]  duty_cycle ,
  input  wire        tick       ,
  output reg         start      ,
  output reg         pwm
);

  wire [7:0] next_counter;
  reg  [7:0] counter;

  assign next_counter = counter + 1'b1;

  always @(negedge rst_n or posedge clk) begin
    if (rst_n == 1'b0) begin
      counter <= 8'h00;
      start   <= 1'b0;
      pwm     <= 1'b0;
    end else begin
      if (clear_n == 1'b0) begin
        counter <= 8'h00;
        start   <= 1'b0;
        pwm     <= 1'b0;
      end else begin
        if (tick == 1'b1) begin
          counter <= next_counter;
        end
        if ((tick == 1'b1) && (counter[7] == 1'b1) && (next_counter[7] == 1'b0)) begin
          start <= 1'b1;
        end else begin
          start <= 1'b0;
        end
        if (counter <= duty_cycle) begin
          pwm <= 1'b1;
        end else begin
          pwm <= 1'b0;
        end
      end
    end
  end

endmodule
module pwm_generator (
  input  wire        rst_n      ,
  input  wire        clk        ,
  input  wire        clear_n    ,
  input  wire [7:0]  duty_cycle ,
  input  wire        tick       ,
  output reg         start      ,
  output reg         pwm
);


  wire [7:0] next_counter;
  reg  [7:0] counter;

  assign next_counter = counter + 1'b1;

  always @(negedge rst_n or posedge clk) begin
    if (rst_n == 1'b0) begin
      counter <= 8'h00;
      start   <= 1'b0;
      pwm     <= 1'b0;
    end else begin
      if (clear_n == 1'b0) begin
        counter <= 8'h00;
        start   <= 1'b0;
        pwm     <= 1'b0;
      end else begin
        if (tick == 1'b1) begin
          counter <= next_counter;
        end
        if ((tick == 1'b1) && (counter[7] == 1'b1) && (next_counter[7] == 1'b0)) begin
          start <= 1'b1;
        end else begin
          start <= 1'b0;
        end
        if (counter <= duty_cycle) begin
          pwm <= 1'b1;
        end else begin
          pwm <= 1'b0;
        end
      end
    end
  end

endmodule