data/full_repos/permissive/428158935/sources_1/new/AdderModule.v
data/verilator_xmls/dff4d8a6-ea7a-49c3-a5fc-75c71889658f.xml
module CLA_Add_4bit(
    input[3:0] A,
    input[3:0] B,
    input CI_0,
    output[3:0] S,
    output Gm,
    output Pm
);

wire[3:0] G;
wire[3:0] P;
wire[4:1] CI;
    
Add_1bit u1(
    .A (A[0]),
    .B (B[0]),
    .CI (CI_0),
    .S (S[0]),
    .G (G[0]),
    .P (P[0])
);
    
Add_1bit u2(
    .A (A[1]),
    .B (B[1]),
    .CI (CI[1]),
    .S (S[1]),
    .G (G[1]),
    .P (P[1])
);
    
Add_1bit u3(
    .A (A[2]),
    .B (B[2]),
    .CI (CI[2]),
    .S (S[2]),
    .G (G[2]),
    .P (P[2])
);
    
Add_1bit u4(
    .A (A[3]),
    .B (B[3]),
    .CI (CI[3]),
    .S (S[3]),
    .G (G[3]),
    .P (P[3])
);

CLA_4bit U(
    .P (P),
    .G (G),
    .CI_0 (CI_0),
    .CI (CI),
    .Gm (Gm),
    .Pm (Pm)
);
    
endmodule
module CLA_Add_4bit(
    input[3:0] A,
    input[3:0] B,
    input CI_0,
    output[3:0] S,
    output Gm,
    output Pm
);


wire[3:0] G;
wire[3:0] P;
wire[4:1] CI;
    
Add_1bit u1(
    .A (A[0]),
    .B (B[0]),
    .CI (CI_0),
    .S (S[0]),
    .G (G[0]),
    .P (P[0])
);
    
Add_1bit u2(
    .A (A[1]),
    .B (B[1]),
    .CI (CI[1]),
    .S (S[1]),
    .G (G[1]),
    .P (P[1])
);
    
Add_1bit u3(
    .A (A[2]),
    .B (B[2]),
    .CI (CI[2]),
    .S (S[2]),
    .G (G[2]),
    .P (P[2])
);
    
Add_1bit u4(
    .A (A[3]),
    .B (B[3]),
    .CI (CI[3]),
    .S (S[3]),
    .G (G[3]),
    .P (P[3])
);

CLA_4bit U(
    .P (P),
    .G (G),
    .CI_0 (CI_0),
    .CI (CI),
    .Gm (Gm),
    .Pm (Pm)
);
    
endmodule