data/full_repos/permissive/48250786/addKey.v
data/verilator_xmls/a279ecb4-efb7-432b-8d63-096bb76884a1.xml
module addKey(
    output [127:0] keyedOut,
    input [127:0] keyedIn,
    input [127:0] key
    );

	 assign keyedOut = (keyedIn ^ key);

endmodule
module addKey(
    output [127:0] keyedOut,
    input [127:0] keyedIn,
    input [127:0] key
    );


	 assign keyedOut = (keyedIn ^ key);

endmodule