data/full_repos/permissive/512928021/pin-protected-backup/impl/hw/fpga.v
1: b'%Error: data/full_repos/permissive/512928021/pin-protected-backup/impl/hw/fpga.v:26: syntax error, unexpected int\n    .int (btn_n_internal)\n     ^~~\n%Error: data/full_repos/permissive/512928021/pin-protected-backup/impl/hw/fpga.v:35: syntax error, unexpected int\n    .int (rx_internal)\n     ^~~\n%Error: data/full_repos/permissive/512928021/pin-protected-backup/impl/hw/fpga.v:42: syntax error, unexpected int\n    .int (cts_internal)\n     ^~~\n%Error: Exiting due to 3 error(s)\n'
module fpga (
    input CLK,
    input BTN_N,
    input RX,
    input CTS,
    output TX,
    output RTS
);

reg [1:0] power_on_resetn_ctr;

initial begin
    power_on_resetn_ctr = 2'b11;
end

always @(posedge CLK) begin
    if (power_on_resetn_ctr != 2'b00) begin
        power_on_resetn_ctr <= power_on_resetn_ctr - 1;
    end
end

wire btn_n_internal;
sync sync_btn(
    .clk (CLK),
    .ext (BTN_N),
    .int (btn_n_internal)
);

wire resetn = btn_n_internal & (power_on_resetn_ctr == 2'b00);

wire rx_internal;
sync sync_rx(
    .clk (CLK),
    .ext (RX),
    .int (rx_internal)
);

wire cts_internal;
sync sync_cts(
    .clk (CLK),
    .ext (CTS),
    .int (cts_internal)
);

pin pin(
    .clk (CLK),
    .resetn (resetn),
    .rx (rx_internal),
    .cts (cts_internal),
    .tx (TX),
    .rts (RTS)
);

endmodule
module fpga (
    input CLK,
    input BTN_N,
    input RX,
    input CTS,
    output TX,
    output RTS
);


reg [1:0] power_on_resetn_ctr;

initial begin
    power_on_resetn_ctr = 2'b11;
end

always @(posedge CLK) begin
    if (power_on_resetn_ctr != 2'b00) begin
        power_on_resetn_ctr <= power_on_resetn_ctr - 1;
    end
end

wire btn_n_internal;
sync sync_btn(
    .clk (CLK),
    .ext (BTN_N),
    .int (btn_n_internal)
);

wire resetn = btn_n_internal & (power_on_resetn_ctr == 2'b00);

wire rx_internal;
sync sync_rx(
    .clk (CLK),
    .ext (RX),
    .int (rx_internal)
);

wire cts_internal;
sync sync_cts(
    .clk (CLK),
    .ext (CTS),
    .int (cts_internal)
);

pin pin(
    .clk (CLK),
    .resetn (resetn),
    .rx (rx_internal),
    .cts (cts_internal),
    .tx (TX),
    .rts (RTS)
);

endmodule