data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:29: Cannot find include file: sys.h\n`include "sys.h" // system level definition file which contains the  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:32: Cannot find include file: iop.h\n`include "iop.h" \n         ^~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:60: Define or directive not defined: \'`PCX_WIDTH\'\n   output [`PCX_WIDTH-1:0]pcx_fpio_data_px_l;  \n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:61: Define or directive not defined: \'`PCX_WIDTH\'\n   output [`PCX_WIDTH-1:0]pcx_scache1_data_px_l; \n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:62: Define or directive not defined: \'`PCX_WIDTH\'\n   output [`PCX_WIDTH-1:0]pcx_scache3_data_px_l; \n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:84: Define or directive not defined: \'`PCX_WIDTH\'\n   input [`PCX_WIDTH-1:0]spc0_pcx_data_pa;  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:85: Define or directive not defined: \'`PCX_WIDTH\'\n   input [`PCX_WIDTH-1:0]spc1_pcx_data_pa;  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:86: Define or directive not defined: \'`PCX_WIDTH\'\n   input [`PCX_WIDTH-1:0]spc2_pcx_data_pa;  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:87: Define or directive not defined: \'`PCX_WIDTH\'\n   input [`PCX_WIDTH-1:0]spc3_pcx_data_pa;  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:88: Define or directive not defined: \'`PCX_WIDTH\'\n   input [`PCX_WIDTH-1:0]spc4_pcx_data_pa;  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:89: Define or directive not defined: \'`PCX_WIDTH\'\n   input [`PCX_WIDTH-1:0]spc5_pcx_data_pa;  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:90: Define or directive not defined: \'`PCX_WIDTH\'\n   input [`PCX_WIDTH-1:0]spc6_pcx_data_pa;  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:91: Define or directive not defined: \'`PCX_WIDTH\'\n   input [`PCX_WIDTH-1:0]spc7_pcx_data_pa;  \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:110: Define or directive not defined: \'`PCX_WIDTH\'\n     .pcx_scache1_data_px_l(pcx_scache1_data_px_l[`PCX_WIDTH-1:0]),\n                                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:120: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc0_pcx_data_pa (spc0_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:121: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc1_pcx_data_pa (spc1_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:122: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc2_pcx_data_pa (spc2_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:123: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc3_pcx_data_pa (spc3_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:124: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc4_pcx_data_pa (spc4_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:125: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc5_pcx_data_pa (spc5_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:126: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc6_pcx_data_pa (spc6_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:127: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc7_pcx_data_pa (spc7_pcx_data_pa[`PCX_WIDTH-1:0]));\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:138: Define or directive not defined: \'`PCX_WIDTH\'\n     .pcx_scache3_data_px_l(pcx_scache3_data_px_l[`PCX_WIDTH-1:0]),\n                                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:148: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc0_pcx_data_pa (spc0_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:149: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc1_pcx_data_pa (spc1_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:150: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc2_pcx_data_pa (spc2_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:151: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc3_pcx_data_pa (spc3_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:152: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc4_pcx_data_pa (spc4_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:153: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc5_pcx_data_pa (spc5_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:154: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc6_pcx_data_pa (spc6_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:155: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc7_pcx_data_pa (spc7_pcx_data_pa[`PCX_WIDTH-1:0]));\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:167: Define or directive not defined: \'`PCX_WIDTH\'\n     .pcx_io_data_px_l (pcx_fpio_data_px_l[`PCX_WIDTH-1:0]),  \n                                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:177: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc0_pcx_data_pa (spc0_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:178: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc1_pcx_data_pa (spc1_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:179: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc2_pcx_data_pa (spc2_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:180: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc3_pcx_data_pa (spc3_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:181: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc4_pcx_data_pa (spc4_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:182: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc5_pcx_data_pa (spc5_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:183: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc6_pcx_data_pa (spc6_pcx_data_pa[`PCX_WIDTH-1:0]),\n                                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/pcx_dp_array134.v:184: Define or directive not defined: \'`PCX_WIDTH\'\n     .spc7_pcx_data_pa (spc7_pcx_data_pa[`PCX_WIDTH-1:0]));\n                                         ^~~~~~~~~~\n%Error: Exiting due to 40 error(s)\n'
module pcx_dp_array134(

   pcx_scache3_data_px_l, pcx_scache1_data_px_l, pcx_fpio_data_px_l, 
   scan_out, 

   spc7_pcx_data_pa, spc6_pcx_data_pa, spc5_pcx_data_pa, 
   spc4_pcx_data_pa, spc3_pcx_data_pa, spc2_pcx_data_pa, 
   spc1_pcx_data_pa, spc0_pcx_data_pa, shiftenable, rclk, 
   arbpc4_pcxdp_shift_px, arbpc4_pcxdp_qsel1_pa, 
   arbpc4_pcxdp_qsel0_pa, arbpc4_pcxdp_q0_hold_pa, 
   arbpc4_pcxdp_grant_pa, arbpc3_pcxdp_shift_px, 
   arbpc3_pcxdp_qsel1_pa, arbpc3_pcxdp_qsel0_pa, 
   arbpc3_pcxdp_q0_hold_pa, arbpc3_pcxdp_grant_pa, 
   arbpc1_pcxdp_shift_px, arbpc1_pcxdp_qsel1_pa, 
   arbpc1_pcxdp_qsel0_pa, arbpc1_pcxdp_q0_hold_pa, 
   arbpc1_pcxdp_grant_pa, scan_in
   );



   output [`PCX_WIDTH-1:0]pcx_fpio_data_px_l;
   output [`PCX_WIDTH-1:0]pcx_scache1_data_px_l;
   output [`PCX_WIDTH-1:0]pcx_scache3_data_px_l;




   input [7:0]		arbpc1_pcxdp_grant_pa;
   input [7:0]		arbpc1_pcxdp_q0_hold_pa;
   input [7:0]		arbpc1_pcxdp_qsel0_pa;
   input [7:0]		arbpc1_pcxdp_qsel1_pa;
   input [7:0]		arbpc1_pcxdp_shift_px;
   input [7:0]		arbpc3_pcxdp_grant_pa;
   input [7:0]		arbpc3_pcxdp_q0_hold_pa;
   input [7:0]		arbpc3_pcxdp_qsel0_pa;
   input [7:0]		arbpc3_pcxdp_qsel1_pa;
   input [7:0]		arbpc3_pcxdp_shift_px;
   input [7:0]		arbpc4_pcxdp_grant_pa;
   input [7:0]		arbpc4_pcxdp_q0_hold_pa;
   input [7:0]		arbpc4_pcxdp_qsel0_pa;
   input [7:0]		arbpc4_pcxdp_qsel1_pa;
   input [7:0]		arbpc4_pcxdp_shift_px;
   input		rclk;
   input		shiftenable;
   input [`PCX_WIDTH-1:0]spc0_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc1_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc2_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc3_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc4_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc5_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc6_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc7_pcx_data_pa;






   input  scan_in;
   output scan_out;
   


   pcx_dp1 pcx_dp1(

		   .scan_out		(),
		   .pcx_scache1_data_px_l(pcx_scache1_data_px_l[`PCX_WIDTH-1:0]),

		   .arbpc1_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[7:0]),
		   .arbpc1_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[7:0]),
		   .arbpc1_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[7:0]),
		   .arbpc1_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[7:0]),
		   .arbpc1_pcxdp_shift_px(arbpc1_pcxdp_shift_px[7:0]),
		   .rclk		(rclk),
		   .scan_in		(),
		   .shiftenable		(shiftenable),
		   .spc0_pcx_data_pa	(spc0_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc1_pcx_data_pa	(spc1_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc2_pcx_data_pa	(spc2_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc3_pcx_data_pa	(spc3_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc4_pcx_data_pa	(spc4_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc5_pcx_data_pa	(spc5_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc6_pcx_data_pa	(spc6_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc7_pcx_data_pa	(spc7_pcx_data_pa[`PCX_WIDTH-1:0]));



   pcx_dp3 pcx_dp3(

		   .scan_out		(),
		   .pcx_scache3_data_px_l(pcx_scache3_data_px_l[`PCX_WIDTH-1:0]),

		   .arbpc3_pcxdp_grant_pa(arbpc3_pcxdp_grant_pa[7:0]),
		   .arbpc3_pcxdp_q0_hold_pa(arbpc3_pcxdp_q0_hold_pa[7:0]),
		   .arbpc3_pcxdp_qsel0_pa(arbpc3_pcxdp_qsel0_pa[7:0]),
		   .arbpc3_pcxdp_qsel1_pa(arbpc3_pcxdp_qsel1_pa[7:0]),
		   .arbpc3_pcxdp_shift_px(arbpc3_pcxdp_shift_px[7:0]),
		   .rclk		(rclk),
		   .scan_in		(),
		   .shiftenable		(shiftenable),
		   .spc0_pcx_data_pa	(spc0_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc1_pcx_data_pa	(spc1_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc2_pcx_data_pa	(spc2_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc3_pcx_data_pa	(spc3_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc4_pcx_data_pa	(spc4_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc5_pcx_data_pa	(spc5_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc6_pcx_data_pa	(spc6_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc7_pcx_data_pa	(spc7_pcx_data_pa[`PCX_WIDTH-1:0]));



   pcx_dp4 pcx_dp4(

		   .scan_out		(),
		   .pcx_io_data_px_l	(pcx_fpio_data_px_l[`PCX_WIDTH-1:0]),

		   .arbpc4_pcxdp_grant_pa(arbpc4_pcxdp_grant_pa[7:0]),
		   .arbpc4_pcxdp_q0_hold_pa(arbpc4_pcxdp_q0_hold_pa[7:0]),
		   .arbpc4_pcxdp_qsel0_pa(arbpc4_pcxdp_qsel0_pa[7:0]),
		   .arbpc4_pcxdp_qsel1_pa(arbpc4_pcxdp_qsel1_pa[7:0]),
		   .arbpc4_pcxdp_shift_px(arbpc4_pcxdp_shift_px[7:0]),
		   .rclk		(rclk),
		   .scan_in		(),
		   .shiftenable		(shiftenable),
		   .spc0_pcx_data_pa	(spc0_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc1_pcx_data_pa	(spc1_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc2_pcx_data_pa	(spc2_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc3_pcx_data_pa	(spc3_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc4_pcx_data_pa	(spc4_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc5_pcx_data_pa	(spc5_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc6_pcx_data_pa	(spc6_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc7_pcx_data_pa	(spc7_pcx_data_pa[`PCX_WIDTH-1:0]));

endmodule
module pcx_dp_array134(

   pcx_scache3_data_px_l, pcx_scache1_data_px_l, pcx_fpio_data_px_l, 
   scan_out, 

   spc7_pcx_data_pa, spc6_pcx_data_pa, spc5_pcx_data_pa, 
   spc4_pcx_data_pa, spc3_pcx_data_pa, spc2_pcx_data_pa, 
   spc1_pcx_data_pa, spc0_pcx_data_pa, shiftenable, rclk, 
   arbpc4_pcxdp_shift_px, arbpc4_pcxdp_qsel1_pa, 
   arbpc4_pcxdp_qsel0_pa, arbpc4_pcxdp_q0_hold_pa, 
   arbpc4_pcxdp_grant_pa, arbpc3_pcxdp_shift_px, 
   arbpc3_pcxdp_qsel1_pa, arbpc3_pcxdp_qsel0_pa, 
   arbpc3_pcxdp_q0_hold_pa, arbpc3_pcxdp_grant_pa, 
   arbpc1_pcxdp_shift_px, arbpc1_pcxdp_qsel1_pa, 
   arbpc1_pcxdp_qsel0_pa, arbpc1_pcxdp_q0_hold_pa, 
   arbpc1_pcxdp_grant_pa, scan_in
   );




   output [`PCX_WIDTH-1:0]pcx_fpio_data_px_l;
   output [`PCX_WIDTH-1:0]pcx_scache1_data_px_l;
   output [`PCX_WIDTH-1:0]pcx_scache3_data_px_l;




   input [7:0]		arbpc1_pcxdp_grant_pa;
   input [7:0]		arbpc1_pcxdp_q0_hold_pa;
   input [7:0]		arbpc1_pcxdp_qsel0_pa;
   input [7:0]		arbpc1_pcxdp_qsel1_pa;
   input [7:0]		arbpc1_pcxdp_shift_px;
   input [7:0]		arbpc3_pcxdp_grant_pa;
   input [7:0]		arbpc3_pcxdp_q0_hold_pa;
   input [7:0]		arbpc3_pcxdp_qsel0_pa;
   input [7:0]		arbpc3_pcxdp_qsel1_pa;
   input [7:0]		arbpc3_pcxdp_shift_px;
   input [7:0]		arbpc4_pcxdp_grant_pa;
   input [7:0]		arbpc4_pcxdp_q0_hold_pa;
   input [7:0]		arbpc4_pcxdp_qsel0_pa;
   input [7:0]		arbpc4_pcxdp_qsel1_pa;
   input [7:0]		arbpc4_pcxdp_shift_px;
   input		rclk;
   input		shiftenable;
   input [`PCX_WIDTH-1:0]spc0_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc1_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc2_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc3_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc4_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc5_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc6_pcx_data_pa;
   input [`PCX_WIDTH-1:0]spc7_pcx_data_pa;






   input  scan_in;
   output scan_out;
   


   pcx_dp1 pcx_dp1(

		   .scan_out		(),
		   .pcx_scache1_data_px_l(pcx_scache1_data_px_l[`PCX_WIDTH-1:0]),

		   .arbpc1_pcxdp_grant_pa(arbpc1_pcxdp_grant_pa[7:0]),
		   .arbpc1_pcxdp_q0_hold_pa(arbpc1_pcxdp_q0_hold_pa[7:0]),
		   .arbpc1_pcxdp_qsel0_pa(arbpc1_pcxdp_qsel0_pa[7:0]),
		   .arbpc1_pcxdp_qsel1_pa(arbpc1_pcxdp_qsel1_pa[7:0]),
		   .arbpc1_pcxdp_shift_px(arbpc1_pcxdp_shift_px[7:0]),
		   .rclk		(rclk),
		   .scan_in		(),
		   .shiftenable		(shiftenable),
		   .spc0_pcx_data_pa	(spc0_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc1_pcx_data_pa	(spc1_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc2_pcx_data_pa	(spc2_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc3_pcx_data_pa	(spc3_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc4_pcx_data_pa	(spc4_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc5_pcx_data_pa	(spc5_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc6_pcx_data_pa	(spc6_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc7_pcx_data_pa	(spc7_pcx_data_pa[`PCX_WIDTH-1:0]));



   pcx_dp3 pcx_dp3(

		   .scan_out		(),
		   .pcx_scache3_data_px_l(pcx_scache3_data_px_l[`PCX_WIDTH-1:0]),

		   .arbpc3_pcxdp_grant_pa(arbpc3_pcxdp_grant_pa[7:0]),
		   .arbpc3_pcxdp_q0_hold_pa(arbpc3_pcxdp_q0_hold_pa[7:0]),
		   .arbpc3_pcxdp_qsel0_pa(arbpc3_pcxdp_qsel0_pa[7:0]),
		   .arbpc3_pcxdp_qsel1_pa(arbpc3_pcxdp_qsel1_pa[7:0]),
		   .arbpc3_pcxdp_shift_px(arbpc3_pcxdp_shift_px[7:0]),
		   .rclk		(rclk),
		   .scan_in		(),
		   .shiftenable		(shiftenable),
		   .spc0_pcx_data_pa	(spc0_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc1_pcx_data_pa	(spc1_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc2_pcx_data_pa	(spc2_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc3_pcx_data_pa	(spc3_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc4_pcx_data_pa	(spc4_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc5_pcx_data_pa	(spc5_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc6_pcx_data_pa	(spc6_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc7_pcx_data_pa	(spc7_pcx_data_pa[`PCX_WIDTH-1:0]));



   pcx_dp4 pcx_dp4(

		   .scan_out		(),
		   .pcx_io_data_px_l	(pcx_fpio_data_px_l[`PCX_WIDTH-1:0]),

		   .arbpc4_pcxdp_grant_pa(arbpc4_pcxdp_grant_pa[7:0]),
		   .arbpc4_pcxdp_q0_hold_pa(arbpc4_pcxdp_q0_hold_pa[7:0]),
		   .arbpc4_pcxdp_qsel0_pa(arbpc4_pcxdp_qsel0_pa[7:0]),
		   .arbpc4_pcxdp_qsel1_pa(arbpc4_pcxdp_qsel1_pa[7:0]),
		   .arbpc4_pcxdp_shift_px(arbpc4_pcxdp_shift_px[7:0]),
		   .rclk		(rclk),
		   .scan_in		(),
		   .shiftenable		(shiftenable),
		   .spc0_pcx_data_pa	(spc0_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc1_pcx_data_pa	(spc1_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc2_pcx_data_pa	(spc2_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc3_pcx_data_pa	(spc3_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc4_pcx_data_pa	(spc4_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc5_pcx_data_pa	(spc5_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc6_pcx_data_pa	(spc6_pcx_data_pa[`PCX_WIDTH-1:0]),
		   .spc7_pcx_data_pa	(spc7_pcx_data_pa[`PCX_WIDTH-1:0]));

endmodule