data/full_repos/permissive/523492216/verilog/mixcolumn.v
data/verilator_xmls/0e4913ad-3291-4885-b523-d16682008a8b.xml
function automatic [7:0] mult;
    input [1:0] x;
    input [7:0] y;
    reg [7:0] t1;
    reg [7:0] t2;
    reg [7:0] xtime;
    begin
      xtime = y[7] ? {y[6:0], 1'b0} ^ 8'h1b : {y[6:0], 1'b0};
      t1 = x[0] ? y : 8'h00;
      t2 = x[1] ? xtime : 8'h00;
      mult = t1 ^ t2;
    end
  endfunction
function automatic [7:0] mult;

    input [1:0] x;
    input [7:0] y;
    reg [7:0] t1;
    reg [7:0] t2;
    reg [7:0] xtime;
    begin
      xtime = y[7] ? {y[6:0], 1'b0} ^ 8'h1b : {y[6:0], 1'b0};
      t1 = x[0] ? y : 8'h00;
      t2 = x[1] ? xtime : 8'h00;
      mult = t1 ^ t2;
    end
  endfunction