data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/ONEDCONV_STATEMACHINE.v
data/verilator_xmls/aac11312-eb0c-4b57-85a9-388a9f52ff01.xml
module ONEDCONV_STATEMACHINE(



ONEDCONV_STATEMACHINE_Clk,
ONEDCONV_STATEMACHINE_Start,
ONEDCONV_STATEMACHINE_En,
ONEDCONV_STATEMACHINE_Reset,

ONEDCONV_STATEMACHINE_Next_Row_Clr,
ONEDCONV_STATEMACHINE_SetEn_En,
ONEDCONV_STATEMACHINE_SetEn_clr,
ONEDCONV_STATEMACHINE_OEn_En,
ONEDCONV_STATEMACHINE_OEn_clr

);





localparam State_reset = 0;
localparam State_Wait_Start = 1;
localparam State_Started = 2;





input ONEDCONV_STATEMACHINE_Clk;
input ONEDCONV_STATEMACHINE_Start;
input ONEDCONV_STATEMACHINE_En;
input ONEDCONV_STATEMACHINE_Reset;
output reg ONEDCONV_STATEMACHINE_Next_Row_Clr;
output reg ONEDCONV_STATEMACHINE_SetEn_En;
output reg ONEDCONV_STATEMACHINE_SetEn_clr;
output reg ONEDCONV_STATEMACHINE_OEn_En;
output reg ONEDCONV_STATEMACHINE_OEn_clr;




reg [2:0] State_Register;
reg [2:0] State_Signal;



always @(*)
begin
	case (State_Register)
	
	State_reset: if(ONEDCONV_STATEMACHINE_En)
						State_Signal=State_Wait_Start;
					 else
						State_Signal=State_reset;
		
	State_Wait_Start: if(ONEDCONV_STATEMACHINE_Start)
								State_Signal=State_Started;
							else 
								State_Signal=State_Wait_Start;
			
								
	State_Started: if(!ONEDCONV_STATEMACHINE_Reset)
							State_Signal=State_reset;
						else
							State_Signal=State_Started;
							
	default : State_Signal = State_reset;
	
	endcase
	
end



always @ (posedge ONEDCONV_STATEMACHINE_Clk , negedge ONEDCONV_STATEMACHINE_Reset)
begin
	if (!ONEDCONV_STATEMACHINE_Reset)
		State_Register <= State_reset;
	else
		State_Register <= State_Signal;
end




always @ (*)
begin
	
	case(State_Register)
		
		State_reset:
		begin
		ONEDCONV_STATEMACHINE_Next_Row_Clr=0;
		ONEDCONV_STATEMACHINE_SetEn_En=0;
		ONEDCONV_STATEMACHINE_OEn_En=0;
		ONEDCONV_STATEMACHINE_SetEn_clr=0;
		ONEDCONV_STATEMACHINE_OEn_clr=0;
		end
		
		State_Wait_Start:
		begin
			ONEDCONV_STATEMACHINE_Next_Row_Clr=1;
			ONEDCONV_STATEMACHINE_SetEn_En=0;
			ONEDCONV_STATEMACHINE_OEn_En=0;
			ONEDCONV_STATEMACHINE_SetEn_clr=1;
			ONEDCONV_STATEMACHINE_OEn_clr=1;
		end
		
		State_Started:
		begin
			ONEDCONV_STATEMACHINE_Next_Row_Clr=1;
			ONEDCONV_STATEMACHINE_SetEn_En=1;
			ONEDCONV_STATEMACHINE_OEn_En=1;
			ONEDCONV_STATEMACHINE_SetEn_clr=1;
			ONEDCONV_STATEMACHINE_OEn_clr=1;
		end
		
		default:
		begin
			ONEDCONV_STATEMACHINE_Next_Row_Clr=0;
			ONEDCONV_STATEMACHINE_SetEn_En=0;
			ONEDCONV_STATEMACHINE_OEn_En=0;
			ONEDCONV_STATEMACHINE_SetEn_clr=0;
			ONEDCONV_STATEMACHINE_OEn_clr=0;	
		end
		
	endcase

end

endmodule
module ONEDCONV_STATEMACHINE(



ONEDCONV_STATEMACHINE_Clk,
ONEDCONV_STATEMACHINE_Start,
ONEDCONV_STATEMACHINE_En,
ONEDCONV_STATEMACHINE_Reset,

ONEDCONV_STATEMACHINE_Next_Row_Clr,
ONEDCONV_STATEMACHINE_SetEn_En,
ONEDCONV_STATEMACHINE_SetEn_clr,
ONEDCONV_STATEMACHINE_OEn_En,
ONEDCONV_STATEMACHINE_OEn_clr

);






localparam State_reset = 0;
localparam State_Wait_Start = 1;
localparam State_Started = 2;





input ONEDCONV_STATEMACHINE_Clk;
input ONEDCONV_STATEMACHINE_Start;
input ONEDCONV_STATEMACHINE_En;
input ONEDCONV_STATEMACHINE_Reset;
output reg ONEDCONV_STATEMACHINE_Next_Row_Clr;
output reg ONEDCONV_STATEMACHINE_SetEn_En;
output reg ONEDCONV_STATEMACHINE_SetEn_clr;
output reg ONEDCONV_STATEMACHINE_OEn_En;
output reg ONEDCONV_STATEMACHINE_OEn_clr;




reg [2:0] State_Register;
reg [2:0] State_Signal;



always @(*)
begin
	case (State_Register)
	
	State_reset: if(ONEDCONV_STATEMACHINE_En)
						State_Signal=State_Wait_Start;
					 else
						State_Signal=State_reset;
		
	State_Wait_Start: if(ONEDCONV_STATEMACHINE_Start)
								State_Signal=State_Started;
							else 
								State_Signal=State_Wait_Start;
			
								
	State_Started: if(!ONEDCONV_STATEMACHINE_Reset)
							State_Signal=State_reset;
						else
							State_Signal=State_Started;
							
	default : State_Signal = State_reset;
	
	endcase
	
end



always @ (posedge ONEDCONV_STATEMACHINE_Clk , negedge ONEDCONV_STATEMACHINE_Reset)
begin
	if (!ONEDCONV_STATEMACHINE_Reset)
		State_Register <= State_reset;
	else
		State_Register <= State_Signal;
end




always @ (*)
begin
	
	case(State_Register)
		
		State_reset:
		begin
		ONEDCONV_STATEMACHINE_Next_Row_Clr=0;
		ONEDCONV_STATEMACHINE_SetEn_En=0;
		ONEDCONV_STATEMACHINE_OEn_En=0;
		ONEDCONV_STATEMACHINE_SetEn_clr=0;
		ONEDCONV_STATEMACHINE_OEn_clr=0;
		end
		
		State_Wait_Start:
		begin
			ONEDCONV_STATEMACHINE_Next_Row_Clr=1;
			ONEDCONV_STATEMACHINE_SetEn_En=0;
			ONEDCONV_STATEMACHINE_OEn_En=0;
			ONEDCONV_STATEMACHINE_SetEn_clr=1;
			ONEDCONV_STATEMACHINE_OEn_clr=1;
		end
		
		State_Started:
		begin
			ONEDCONV_STATEMACHINE_Next_Row_Clr=1;
			ONEDCONV_STATEMACHINE_SetEn_En=1;
			ONEDCONV_STATEMACHINE_OEn_En=1;
			ONEDCONV_STATEMACHINE_SetEn_clr=1;
			ONEDCONV_STATEMACHINE_OEn_clr=1;
		end
		
		default:
		begin
			ONEDCONV_STATEMACHINE_Next_Row_Clr=0;
			ONEDCONV_STATEMACHINE_SetEn_En=0;
			ONEDCONV_STATEMACHINE_OEn_En=0;
			ONEDCONV_STATEMACHINE_SetEn_clr=0;
			ONEDCONV_STATEMACHINE_OEn_clr=0;	
		end
		
	endcase

end

endmodule