data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_stim_sine/rtl/wfg_stim_sine.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_stim_sine/rtl/wfg_stim_sine.sv:98: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s VARREF \'K\' generates 16 bits.\n                                                                                                          : ... In instance wfg_stim_sine\n            x            <= K;\n                         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_stim_sine/rtl/wfg_stim_sine.sv:119: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s VARREF \'K\' generates 16 bits.\n                                                                                                           : ... In instance wfg_stim_sine\n                    x <= K;\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_stim_sine/rtl/wfg_stim_sine.sv:194: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'sin_18\' generates 18 bits.\n                                                                                                           : ... In instance wfg_stim_sine\n    assign wfg_axis_tdata_o  = sin_18;\n                             ^\n%Error: Exiting due to 3 warning(s)\n'
module wfg_stim_sine (
    input  wire               clk,
    input  wire               rst_n,
    input  wire               wfg_axis_tready_i,
    output wire               wfg_axis_tvalid_o,
    output wire signed [31:0] wfg_axis_tdata_o,
    input  wire               ctrl_en_q_i,
    input  wire        [15:0] inc_val_q_i,
    input  wire        [15:0] gain_val_q_i,
    input  wire signed [17:0] offset_val_q_i
);

    parameter bit [15:0] K = 16'h9b74;


    logic signed [16:0] sin_17;
    logic signed [17:0] sin_18;


    logic signed [16:0] x;
    logic signed [16:0] y;
    logic signed [16:0] z;


    logic [1:0]  quadrant;


    logic [15:0] rot[0:15];
    logic [3:0] iteration;
    logic signed [34:0] temp;

    logic valid;
    logic [15:0] phase_in;
    logic [15:0] increment;
    logic signed [17:0] overflow_chk;

    typedef enum {
        ST_IDLE,
        ST_CALC,
        ST_QUADRANT,
        ST_GAIN,
        ST_OFFSET,
        ST_DONE
    } wfg_stim_sine_states_t;

    wfg_stim_sine_states_t cur_state;
    wfg_stim_sine_states_t next_state;

    always_ff @(posedge clk, negedge rst_n) begin
        if (!rst_n) cur_state <= ST_IDLE;
        else cur_state <= next_state;
    end

    always_comb begin
        next_state = cur_state;
        case (cur_state)
            ST_IDLE: begin
                if (ctrl_en_q_i == 1'b1) next_state = ST_CALC;
            end
            ST_CALC: begin
                if (iteration == 15) next_state = ST_QUADRANT;
            end
            ST_QUADRANT:    next_state = ST_GAIN;
            ST_GAIN:        next_state = ST_OFFSET;
            ST_OFFSET:      next_state = ST_DONE;
            ST_DONE: begin
                if (wfg_axis_tready_i == 1'b1) next_state = ST_IDLE;
            end
            default: next_state = ST_IDLE;
        endcase
    end

    assign increment = inc_val_q_i + phase_in;

    always_ff @(posedge clk, negedge rst_n) begin
        if (!rst_n) begin
            rot[0]       <= 16'h2000;
            rot[1]       <= 16'h12e4;
            rot[2]       <= 16'h09fb;
            rot[3]       <= 16'h0511;
            rot[4]       <= 16'h028b;
            rot[5]       <= 16'h0145;
            rot[6]       <= 16'h00a3;
            rot[7]       <= 16'h0051;
            rot[8]       <= 16'h0028;
            rot[9]       <= 16'h0014;
            rot[10]      <= 16'h000a;
            rot[11]      <= 16'h0005;
            rot[12]      <= 16'h0003;
            rot[13]      <= 16'h0001;
            rot[14]      <= 16'h0001;
            rot[15]      <= 16'h0000;

            x            <= K;
            y            <= '0;
            z            <= '0;

            iteration    <= '0;
            phase_in     <= '0;

            valid        <= '0;
            sin_17       <= '0;

            quadrant     <= '0;
            sin_18       <= '0;
            temp         <= '0;
            overflow_chk <= '0;

        end else begin
            valid <= 0;

            case (cur_state)
                ST_IDLE: begin
                    iteration <= 0;
                    x <= K;
                    y <= '0;


                    quadrant <= phase_in[15:14];

                    z <= {3'b0, phase_in[13:0]};
                end
                ST_CALC: begin
                    iteration <= iteration + 1;

                    if (z[16] == 1'b1) begin
                        x <= x + (y >>> (iteration));
                        y <= y - (x >>> (iteration));
                        z <= z + rot[iteration];
                    end else begin
                        x <= x - (y >>> (iteration));
                        y <= y + (x >>> (iteration));
                        z <= z - rot[iteration];
                    end


                end
                ST_QUADRANT: begin
                    case (quadrant)
                        2'b00: begin
                            sin_17 <= y;
                        end
                        2'b01: begin
                            sin_17 <= x;
                        end
                        2'b10: begin
                            sin_17 <= ~(y) + 1'b1;
                        end
                        2'b11: begin
                            sin_17 <= ~(x) + 1'b1;
                        end
                        default: begin
                            sin_17 <= 'x;
                        end
                    endcase
                end
                ST_GAIN: begin

                    if (gain_val_q_i[15:0] > 16'h7FFF) begin
                        temp[34:0] <= {{16{sin_17[16]}}, sin_17[15:0]} * {{16{1'b0}}, 16'h7FFF};
                    end else begin
                        temp[34:0] <=   {{16{sin_17[16]}}, sin_17[15:0]} *
                                        {{16{1'b0}}, gain_val_q_i[15:0]};
                    end
                end
                ST_OFFSET: begin

                    overflow_chk[17:0] <= temp[31:14] + offset_val_q_i[17:0];
                end
                ST_DONE: begin
                    valid <= 1;

                    if (temp[31] && offset_val_q_i[17] && !overflow_chk[17]) begin
                        sin_18 <= 18'b100000000000000000;

                    end else if (!temp[31] && !offset_val_q_i[17] && overflow_chk[17]) begin
                        sin_18 <= 18'b011111111111111111;
                    end else begin
                        sin_18 <= overflow_chk;
                    end

                    if (wfg_axis_tready_i == 1'b1) phase_in <= increment;
                end
                default: valid <= 'x;
            endcase
        end
    end


    assign wfg_axis_tdata_o  = sin_18;
    assign wfg_axis_tvalid_o = valid;

endmodule
module wfg_stim_sine (
    input  wire               clk,
    input  wire               rst_n,
    input  wire               wfg_axis_tready_i,
    output wire               wfg_axis_tvalid_o,
    output wire signed [31:0] wfg_axis_tdata_o,
    input  wire               ctrl_en_q_i,
    input  wire        [15:0] inc_val_q_i,
    input  wire        [15:0] gain_val_q_i,
    input  wire signed [17:0] offset_val_q_i
);


    parameter bit [15:0] K = 16'h9b74;


    logic signed [16:0] sin_17;
    logic signed [17:0] sin_18;


    logic signed [16:0] x;
    logic signed [16:0] y;
    logic signed [16:0] z;


    logic [1:0]  quadrant;


    logic [15:0] rot[0:15];
    logic [3:0] iteration;
    logic signed [34:0] temp;

    logic valid;
    logic [15:0] phase_in;
    logic [15:0] increment;
    logic signed [17:0] overflow_chk;

    typedef enum {
        ST_IDLE,
        ST_CALC,
        ST_QUADRANT,
        ST_GAIN,
        ST_OFFSET,
        ST_DONE
    } wfg_stim_sine_states_t;

    wfg_stim_sine_states_t cur_state;
    wfg_stim_sine_states_t next_state;

    always_ff @(posedge clk, negedge rst_n) begin
        if (!rst_n) cur_state <= ST_IDLE;
        else cur_state <= next_state;
    end

    always_comb begin
        next_state = cur_state;
        case (cur_state)
            ST_IDLE: begin
                if (ctrl_en_q_i == 1'b1) next_state = ST_CALC;
            end
            ST_CALC: begin
                if (iteration == 15) next_state = ST_QUADRANT;
            end
            ST_QUADRANT:    next_state = ST_GAIN;
            ST_GAIN:        next_state = ST_OFFSET;
            ST_OFFSET:      next_state = ST_DONE;
            ST_DONE: begin
                if (wfg_axis_tready_i == 1'b1) next_state = ST_IDLE;
            end
            default: next_state = ST_IDLE;
        endcase
    end

    assign increment = inc_val_q_i + phase_in;

    always_ff @(posedge clk, negedge rst_n) begin
        if (!rst_n) begin
            rot[0]       <= 16'h2000;
            rot[1]       <= 16'h12e4;
            rot[2]       <= 16'h09fb;
            rot[3]       <= 16'h0511;
            rot[4]       <= 16'h028b;
            rot[5]       <= 16'h0145;
            rot[6]       <= 16'h00a3;
            rot[7]       <= 16'h0051;
            rot[8]       <= 16'h0028;
            rot[9]       <= 16'h0014;
            rot[10]      <= 16'h000a;
            rot[11]      <= 16'h0005;
            rot[12]      <= 16'h0003;
            rot[13]      <= 16'h0001;
            rot[14]      <= 16'h0001;
            rot[15]      <= 16'h0000;

            x            <= K;
            y            <= '0;
            z            <= '0;

            iteration    <= '0;
            phase_in     <= '0;

            valid        <= '0;
            sin_17       <= '0;

            quadrant     <= '0;
            sin_18       <= '0;
            temp         <= '0;
            overflow_chk <= '0;

        end else begin
            valid <= 0;

            case (cur_state)
                ST_IDLE: begin
                    iteration <= 0;
                    x <= K;
                    y <= '0;


                    quadrant <= phase_in[15:14];

                    z <= {3'b0, phase_in[13:0]};
                end
                ST_CALC: begin
                    iteration <= iteration + 1;

                    if (z[16] == 1'b1) begin
                        x <= x + (y >>> (iteration));
                        y <= y - (x >>> (iteration));
                        z <= z + rot[iteration];
                    end else begin
                        x <= x - (y >>> (iteration));
                        y <= y + (x >>> (iteration));
                        z <= z - rot[iteration];
                    end


                end
                ST_QUADRANT: begin
                    case (quadrant)
                        2'b00: begin
                            sin_17 <= y;
                        end
                        2'b01: begin
                            sin_17 <= x;
                        end
                        2'b10: begin
                            sin_17 <= ~(y) + 1'b1;
                        end
                        2'b11: begin
                            sin_17 <= ~(x) + 1'b1;
                        end
                        default: begin
                            sin_17 <= 'x;
                        end
                    endcase
                end
                ST_GAIN: begin

                    if (gain_val_q_i[15:0] > 16'h7FFF) begin
                        temp[34:0] <= {{16{sin_17[16]}}, sin_17[15:0]} * {{16{1'b0}}, 16'h7FFF};
                    end else begin
                        temp[34:0] <=   {{16{sin_17[16]}}, sin_17[15:0]} *
                                        {{16{1'b0}}, gain_val_q_i[15:0]};
                    end
                end
                ST_OFFSET: begin

                    overflow_chk[17:0] <= temp[31:14] + offset_val_q_i[17:0];
                end
                ST_DONE: begin
                    valid <= 1;

                    if (temp[31] && offset_val_q_i[17] && !overflow_chk[17]) begin
                        sin_18 <= 18'b100000000000000000;

                    end else if (!temp[31] && !offset_val_q_i[17] && overflow_chk[17]) begin
                        sin_18 <= 18'b011111111111111111;
                    end else begin
                        sin_18 <= overflow_chk;
                    end

                    if (wfg_axis_tready_i == 1'b1) phase_in <= increment;
                end
                default: valid <= 'x;
            endcase
        end
    end


    assign wfg_axis_tdata_o  = sin_18;
    assign wfg_axis_tvalid_o = valid;

endmodule