data/full_repos/permissive/46804359/2_Reg_Async_Reset_Enable.v
data/verilator_xmls/c917ae8d-af6b-4cd8-9614-f94edc86876f.xml
module Reg_Async_Reset_Enable (reset, enable, clk, in, out);

input reset, enable, clk;
input wire [31:0] in;
wire clk;

output reg [31:0] out;

always@(posedge clk)
    begin
    if (reset)
	out <= 0;
    else if (enable)
	out <= in;
    end

endmodule
module Reg_Async_Reset_Enable (reset, enable, clk, in, out);


input reset, enable, clk;
input wire [31:0] in;
wire clk;

output reg [31:0] out;

always@(posedge clk)
    begin
    if (reset)
	out <= 0;
    else if (enable)
	out <= in;
    end

endmodule