data/full_repos/permissive/414867793/Logic_Circuits/Full_Substrator/F_SUBS_tb.v
1: b'%Error: data/full_repos/permissive/414867793/Logic_Circuits/Full_Substrator/F_SUBS_tb.v:2: Cannot find include file: F_SUBS.v\n`include "F_SUBS.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/414867793/Logic_Circuits/Full_Substrator,data/full_repos/permissive/414867793/F_SUBS.v\n             data/full_repos/permissive/414867793/Logic_Circuits/Full_Substrator,data/full_repos/permissive/414867793/F_SUBS.v.v\n             data/full_repos/permissive/414867793/Logic_Circuits/Full_Substrator,data/full_repos/permissive/414867793/F_SUBS.v.sv\n             F_SUBS.v\n             F_SUBS.v.v\n             F_SUBS.v.sv\n             obj_dir/F_SUBS.v\n             obj_dir/F_SUBS.v.v\n             obj_dir/F_SUBS.v.sv\n%Error: data/full_repos/permissive/414867793/Logic_Circuits/Full_Substrator/F_SUBS_tb.v:11: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("F_SUBS_tb.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/414867793/Logic_Circuits/Full_Substrator/F_SUBS_tb.v:12: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(1,F_SUBS_tb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Logic_Circuits/Full_Substrator/F_SUBS_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Logic_Circuits/Full_Substrator/F_SUBS_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Logic_Circuits/Full_Substrator/F_SUBS_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Logic_Circuits/Full_Substrator/F_SUBS_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Logic_Circuits/Full_Substrator/F_SUBS_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Logic_Circuits/Full_Substrator/F_SUBS_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Logic_Circuits/Full_Substrator/F_SUBS_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/414867793/Logic_Circuits/Full_Substrator/F_SUBS_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Error: Exiting due to 3 error(s), 8 warning(s)\n'
module F_SUBS_tb();

reg A,B,C;
wire D,E;

F_SUBS uut(A,B,C,D,E);
initial begin
  $dumpfile("F_SUBS_tb.vcd");
  $dumpvars(1,F_SUBS_tb);
  A=0;
  B=0;
  C=0;
  #20
  A=0;
  B=0;
  C=1;
  #20
  A=0;
  B=1;
  C=0;
  #20
  A=0;
  B=1;
  C=1;
  #20
  A=1;
  B=0;
  C=0;
  #20
  A=1;
  B=0;
  C=1;
  #20
  A=1;
  B=1;
  C=0;
  #20
  A=1;
  B=1;
  C=1;
  #20
  $display("Done testing");
end

endmodule
module F_SUBS_tb();


reg A,B,C;
wire D,E;

F_SUBS uut(A,B,C,D,E);
initial begin
  $dumpfile("F_SUBS_tb.vcd");
  $dumpvars(1,F_SUBS_tb);
  A=0;
  B=0;
  C=0;
  #20
  A=0;
  B=0;
  C=1;
  #20
  A=0;
  B=1;
  C=0;
  #20
  A=0;
  B=1;
  C=1;
  #20
  A=1;
  B=0;
  C=0;
  #20
  A=1;
  B=0;
  C=1;
  #20
  A=1;
  B=1;
  C=0;
  #20
  A=1;
  B=1;
  C=1;
  #20
  $display("Done testing");
end

endmodule