data/full_repos/permissive/516809949/digital/rtl/tst.v
1: b'%Error: data/full_repos/permissive/516809949/digital/rtl/tst.v:17: Cannot find include file: tst_params.vh\n  `include "tst_params.vh" \n           ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/516809949/digital/rtl,data/full_repos/permissive/516809949/tst_params.vh\n             data/full_repos/permissive/516809949/digital/rtl,data/full_repos/permissive/516809949/tst_params.vh.v\n             data/full_repos/permissive/516809949/digital/rtl,data/full_repos/permissive/516809949/tst_params.vh.sv\n             tst_params.vh\n             tst_params.vh.v\n             tst_params.vh.sv\n             obj_dir/tst_params.vh\n             obj_dir/tst_params.vh.v\n             obj_dir/tst_params.vh.sv\n%Error: data/full_repos/permissive/516809949/digital/rtl/tst.v:148: Cannot find include file: tst_params.vh\n  `include "tst_params.vh" \n           ^~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module jtag_fsm(
  input wire tck,
  input wire tms,
  input wire rst_n,
  output wire state_tlr,
  output wire state_capturedr,
  output wire state_captureir,
  output wire state_shiftdr,
  output wire state_shiftir,
  output wire state_updatedr,
  output wire state_updateir,
  output wire state_runidle
);

  `include "tst_params.vh"

  reg[3:0] state;

  always @(posedge tck or negedge rst_n) begin
    if(!rst_n) begin
      state <= TEST_LOGIC_RESET;
    end else begin
      case(state)
        TEST_LOGIC_RESET: state <= tms ? TEST_LOGIC_RESET : RUN_TEST_IDLE;
        RUN_TEST_IDLE:    state <= tms ? SELECT_DR        : RUN_TEST_IDLE;
        SELECT_DR:        state <= tms ? SELECT_IR        : CAPTURE_DR;
        CAPTURE_DR:       state <= tms ? EXIT1_DR         : SHIFT_DR;
        SHIFT_DR:         state <= tms ? EXIT1_DR         : SHIFT_DR;
        EXIT1_DR:         state <= tms ? UPDATE_DR        : PAUSE_DR;
        PAUSE_DR:         state <= tms ? EXIT2_DR         : PAUSE_DR;
        EXIT2_DR:         state <= tms ? UPDATE_DR        : SHIFT_DR;
        UPDATE_DR:        state <= tms ? SELECT_DR        : RUN_TEST_IDLE;
        SELECT_IR:        state <= tms ? TEST_LOGIC_RESET : CAPTURE_IR;
        CAPTURE_IR:       state <= tms ? EXIT1_IR         : SHIFT_IR;
        SHIFT_IR:         state <= tms ? EXIT1_IR         : SHIFT_IR;
        EXIT1_IR:         state <= tms ? UPDATE_IR        : PAUSE_IR;
        PAUSE_IR:         state <= tms ? EXIT2_IR         : PAUSE_IR;
        EXIT2_IR:         state <= tms ? UPDATE_IR        : SHIFT_IR;
        UPDATE_IR:        state <= tms ? SELECT_DR        : RUN_TEST_IDLE;
      endcase
    end
  end

  assign state_tlr       = (state == TEST_LOGIC_RESET);
  assign state_capturedr = (state == CAPTURE_DR);
  assign state_captureir = (state == CAPTURE_IR);
  assign state_shiftdr   = (state == SHIFT_DR);
  assign state_shiftir   = (state == SHIFT_IR);
  assign state_updatedr  = (state == UPDATE_DR);
  assign state_updateir  = (state == UPDATE_IR);
  assign state_runidle   = (state == RUN_TEST_IDLE);

endmodule
module jtag_fsm(
  input wire tck,
  input wire tms,
  input wire rst_n,
  output wire state_tlr,
  output wire state_capturedr,
  output wire state_captureir,
  output wire state_shiftdr,
  output wire state_shiftir,
  output wire state_updatedr,
  output wire state_updateir,
  output wire state_runidle
);


  `include "tst_params.vh"

  reg[3:0] state;

  always @(posedge tck or negedge rst_n) begin
    if(!rst_n) begin
      state <= TEST_LOGIC_RESET;
    end else begin
      case(state)
        TEST_LOGIC_RESET: state <= tms ? TEST_LOGIC_RESET : RUN_TEST_IDLE;
        RUN_TEST_IDLE:    state <= tms ? SELECT_DR        : RUN_TEST_IDLE;
        SELECT_DR:        state <= tms ? SELECT_IR        : CAPTURE_DR;
        CAPTURE_DR:       state <= tms ? EXIT1_DR         : SHIFT_DR;
        SHIFT_DR:         state <= tms ? EXIT1_DR         : SHIFT_DR;
        EXIT1_DR:         state <= tms ? UPDATE_DR        : PAUSE_DR;
        PAUSE_DR:         state <= tms ? EXIT2_DR         : PAUSE_DR;
        EXIT2_DR:         state <= tms ? UPDATE_DR        : SHIFT_DR;
        UPDATE_DR:        state <= tms ? SELECT_DR        : RUN_TEST_IDLE;
        SELECT_IR:        state <= tms ? TEST_LOGIC_RESET : CAPTURE_IR;
        CAPTURE_IR:       state <= tms ? EXIT1_IR         : SHIFT_IR;
        SHIFT_IR:         state <= tms ? EXIT1_IR         : SHIFT_IR;
        EXIT1_IR:         state <= tms ? UPDATE_IR        : PAUSE_IR;
        PAUSE_IR:         state <= tms ? EXIT2_IR         : PAUSE_IR;
        EXIT2_IR:         state <= tms ? UPDATE_IR        : SHIFT_IR;
        UPDATE_IR:        state <= tms ? SELECT_DR        : RUN_TEST_IDLE;
      endcase
    end
  end

  assign state_tlr       = (state == TEST_LOGIC_RESET);
  assign state_capturedr = (state == CAPTURE_DR);
  assign state_captureir = (state == CAPTURE_IR);
  assign state_shiftdr   = (state == SHIFT_DR);
  assign state_shiftir   = (state == SHIFT_IR);
  assign state_updatedr  = (state == UPDATE_DR);
  assign state_updateir  = (state == UPDATE_IR);
  assign state_runidle   = (state == RUN_TEST_IDLE);

endmodule