data/full_repos/permissive/441359809/src/yosys/techlibs/anlogic/cells_map.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/techlibs/anlogic/cells_map.v:2: Multiple top level modules\n                                                                                                : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                : ... Top module \'$_DFFE_PN0P_\'\nmodule  \\$_DFFE_PN0P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C) ,.ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1\'b1; endmodule\n        ^~~~~~~~~~~~~\n                                                                                                : ... Top module \'$_DFFE_PN1P_\'\nmodule  \\$_DFFE_PN1P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1\'b1; endmodule\n        ^~~~~~~~~~~~~\n                                                                                                : ... Top module \'$_DFFE_PP0P_\'\nmodule  \\$_DFFE_PP0P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"),  .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1\'b1; endmodule\n        ^~~~~~~~~~~~~\n                                                                                                : ... Top module \'$_DFFE_PP1P_\'\nmodule  \\$_DFFE_PP1P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"), .SRMUX("SR"), . SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1\'b1; endmodule\n        ^~~~~~~~~~~~~\n                                                                                                : ... Top module \'$_SDFFE_PN0P_\'\nmodule  \\$_SDFFE_PN0P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C) ,.ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1\'b1; endmodule\n        ^~~~~~~~~~~~~~\n                                                                                                : ... Top module \'$_SDFFE_PN1P_\'\nmodule  \\$_SDFFE_PN1P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1\'b1; endmodule\n        ^~~~~~~~~~~~~~\n                                                                                                : ... Top module \'$_SDFFE_PP0P_\'\nmodule  \\$_SDFFE_PP0P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"),  .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1\'b1; endmodule\n        ^~~~~~~~~~~~~~\n                                                                                                : ... Top module \'$_SDFFE_PP1P_\'\nmodule  \\$_SDFFE_PP1P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"), .SRMUX("SR"), . SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1\'b1; endmodule\n        ^~~~~~~~~~~~~~\n                                                                                                : ... Top module \'$_DLATCH_NN0_\'\nmodule  \\$_DLATCH_NN0_ (input D, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("LATCH"), .REGSET("RESET"), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(E) ,.ce(1\'b1), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1\'b1; endmodule\n        ^~~~~~~~~~~~~~\n                                                                                                : ... Top module \'$_DLATCH_NN1_\'\nmodule  \\$_DLATCH_NN1_ (input D, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("LATCH"), .REGSET("SET"), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(E), .ce(1\'b1), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1\'b1; endmodule\n        ^~~~~~~~~~~~~~\n                                                                                                : ... Top module \'$_DLATCH_NP0_\'\nmodule  \\$_DLATCH_NP0_ (input D, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("LATCH"), .REGSET("RESET"), .SRMUX("SR"),  .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(E), .ce(1\'b1), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1\'b1; endmodule\n        ^~~~~~~~~~~~~~\n                                                                                                : ... Top module \'$_DLATCH_NP1_\'\nmodule  \\$_DLATCH_NP1_ (input D, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("LATCH"), .REGSET("SET"), .SRMUX("SR"), . SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(E), .ce(1\'b1), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1\'b1; endmodule\n        ^~~~~~~~~~~~~~\n                                                                                                : ... Top module \'$lut\'\nmodule \\$lut (A, Y);\n       ^~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/441359809/src/yosys/techlibs/anlogic/cells_map.v:22: Little bit endian vector: MSB < LSB of bit range: -1:0\n  input [WIDTH-1:0] A;\n        ^\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/anlogic/cells_map.v:14: Cannot find file containing module: \'AL_MAP_SEQ\'\nmodule  \\$_DLATCH_NP1_ (input D, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("LATCH"), .REGSET("SET"), .SRMUX("SR"), . SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(E), .ce(1\'b1), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1\'b1; endmodule\n                                                  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/441359809/src/yosys/techlibs/anlogic,data/full_repos/permissive/441359809/AL_MAP_SEQ\n             data/full_repos/permissive/441359809/src/yosys/techlibs/anlogic,data/full_repos/permissive/441359809/AL_MAP_SEQ.v\n             data/full_repos/permissive/441359809/src/yosys/techlibs/anlogic,data/full_repos/permissive/441359809/AL_MAP_SEQ.sv\n             AL_MAP_SEQ\n             AL_MAP_SEQ.v\n             AL_MAP_SEQ.sv\n             obj_dir/AL_MAP_SEQ\n             obj_dir/AL_MAP_SEQ.v\n             obj_dir/AL_MAP_SEQ.sv\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/anlogic/cells_map.v:13: Cannot find file containing module: \'AL_MAP_SEQ\'\nmodule  \\$_DLATCH_NP0_ (input D, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("LATCH"), .REGSET("RESET"), .SRMUX("SR"),  .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(E), .ce(1\'b1), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1\'b1; endmodule\n                                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/anlogic/cells_map.v:12: Cannot find file containing module: \'AL_MAP_SEQ\'\nmodule  \\$_DLATCH_NN1_ (input D, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("LATCH"), .REGSET("SET"), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(E), .ce(1\'b1), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1\'b1; endmodule\n                                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/anlogic/cells_map.v:11: Cannot find file containing module: \'AL_MAP_SEQ\'\nmodule  \\$_DLATCH_NN0_ (input D, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("LATCH"), .REGSET("RESET"), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(E) ,.ce(1\'b1), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1\'b1; endmodule\n                                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/anlogic/cells_map.v:9: Cannot find file containing module: \'AL_MAP_SEQ\'\nmodule  \\$_SDFFE_PP1P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"), .SRMUX("SR"), . SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1\'b1; endmodule\n                                                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/anlogic/cells_map.v:8: Cannot find file containing module: \'AL_MAP_SEQ\'\nmodule  \\$_SDFFE_PP0P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"),  .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1\'b1; endmodule\n                                                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/anlogic/cells_map.v:7: Cannot find file containing module: \'AL_MAP_SEQ\'\nmodule  \\$_SDFFE_PN1P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1\'b1; endmodule\n                                                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/anlogic/cells_map.v:6: Cannot find file containing module: \'AL_MAP_SEQ\'\nmodule  \\$_SDFFE_PN0P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C) ,.ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1\'b1; endmodule\n                                                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/anlogic/cells_map.v:4: Cannot find file containing module: \'AL_MAP_SEQ\'\nmodule  \\$_DFFE_PP1P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"), .SRMUX("SR"), . SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1\'b1; endmodule\n                                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/anlogic/cells_map.v:3: Cannot find file containing module: \'AL_MAP_SEQ\'\nmodule  \\$_DFFE_PP0P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"),  .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1\'b1; endmodule\n                                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/anlogic/cells_map.v:2: Cannot find file containing module: \'AL_MAP_SEQ\'\nmodule  \\$_DFFE_PN1P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1\'b1; endmodule\n                                                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/anlogic/cells_map.v:1: Cannot find file containing module: \'AL_MAP_SEQ\'\nmodule  \\$_DFFE_PN0P_ (input D, C, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C) ,.ce(E), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1\'b1; endmodule\n                                                    ^~~~~~~~~~\n%Error: Exiting due to 12 error(s), 2 warning(s)\n'
module  \$_DLATCH_NN1_ (input D, R, E, output Q); AL_MAP_SEQ #(.DFFMODE("LATCH"), .REGSET("SET"), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(E), .ce(1'b1), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
module  \$_DLATCH_NN1_ (input D, R, E, output Q);
 AL_MAP_SEQ #(.DFFMODE("LATCH"), .REGSET("SET"), .SRMUX("INV"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(E), .ce(1'b1), .sr(R)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule