data/full_repos/permissive/505451992/so_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/505451992/so_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n               reset = 1;#250 \n                         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/505451992/so_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n               reset = 0;#250;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/so_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n              forever #125 clk=~clk;\n                      ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/so_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n              #4000\n              ^\n%Error: data/full_repos/permissive/505451992/so_tb.v:34: Cannot find file containing module: \'serial_output\'\n    serial_output utt(\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/505451992,data/full_repos/permissive/505451992/serial_output\n             data/full_repos/permissive/505451992,data/full_repos/permissive/505451992/serial_output.v\n             data/full_repos/permissive/505451992,data/full_repos/permissive/505451992/serial_output.sv\n             serial_output\n             serial_output.v\n             serial_output.sv\n             obj_dir/serial_output\n             obj_dir/serial_output.v\n             obj_dir/serial_output.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module so_tb(

    );
    
    
    reg clk;
    reg reset;
    reg [9:0] Position;
    wire SCL;
    wire SDA;
    
    serial_output utt(
     .clk(clk),
    .reset(reset),
   .Position(Position),
    .SCL(SCL),
    .SDA(SDA)
        );
        
               initial begin
               reset = 1;#250 
               reset = 0;#250;
               

               end
               
              initial begin
              clk=0;
              forever #125 clk=~clk;
              end   
              
              initial begin
             
              Position = 1023;
              #4000
              Position = 681;
              end
    endmodule
module so_tb(

    );

    
    
    reg clk;
    reg reset;
    reg [9:0] Position;
    wire SCL;
    wire SDA;
    
    serial_output utt(
     .clk(clk),
    .reset(reset),
   .Position(Position),
    .SCL(SCL),
    .SDA(SDA)
        );
        
               initial begin
               reset = 1;#250 
               reset = 0;#250;
               

               end
               
              initial begin
              clk=0;
              forever #125 clk=~clk;
              end   
              
              initial begin
             
              Position = 1023;
              #4000
              Position = 681;
              end
    endmodule