data/full_repos/permissive/490649362/single-cycle/src/Adder2_1.v
data/verilator_xmls/b054c8d5-9ee5-474e-92e0-caf46ea306ab.xml
module Adder2_1(in_0, in_1, out);

    input  [31:0] in_0, in_1;
    output [31:0] out;

    assign out = in_0 + in_1;

endmodule
module Adder2_1(in_0, in_1, out);


    input  [31:0] in_0, in_1;
    output [31:0] out;

    assign out = in_0 + in_1;

endmodule