data/full_repos/permissive/521337848/Hardware/SPISD/diskcontroller.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/521337848/Hardware/SPISD/diskcontroller.v:163: Cell has missing pin: \'crc1\'\ninsideconnector ica(\n                ^~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/521337848/Hardware/SPISD/diskcontroller.v:163: Cell has missing pin: \'crc2\'\ninsideconnector ica(\n                ^~~\n%Warning-PINMISSING: data/full_repos/permissive/521337848/Hardware/SPISD/diskcontroller.v:163: Cell has missing pin: \'crc\'\ninsideconnector ica(\n                ^~~\n%Error: data/full_repos/permissive/521337848/Hardware/SPISD/diskcontroller.v:187: Duplicate pin connection: \'__pinNumber21\'\n);\n^\n        data/full_repos/permissive/521337848/Hardware/SPISD/diskcontroller.v:184: ... Location of original pin connection\n .sta40(sta4011),\n  ^~~~~\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module insideconnector(
	input clk,
	input rst,
	
	input [5:0] cmd1,
	input [31:0] arg1,
	input [6:0] crc1,
	input sta1,
	input sta401,
	input readit1,
	input init1,
	
	input [5:0] cmd2,
	input [31:0] arg2,
	input [6:0] crc2,
	input sta2,
	input sta402,
	input readit2,
	input init2,
	
	output reg [5:0] cmd,
	output reg [31:0] arg,
	output reg [6:0] crc,
	output reg sta,
	output reg sta40,
	output reg readit,
	output reg init
);

always@(posedge clk or posedge rst)begin
	if(rst)begin
		cmd <= 0;
		arg <= 0;
		crc <= 0;
		sta <= 0;
		sta40 <= 0;
		readit <= 0;
		init <= 0;
	end else
	begin
		cmd <= cmd1 | cmd2;
		arg <= arg1 | arg2;
		crc <= crc1 | crc2;
		sta <= sta1 | sta2;
		sta40 <= sta401 | sta402;
		readit <= readit1 | readit2;
		init <= init1 | init2;
	end
end

endmodule
module insideconnector(
	input clk,
	input rst,
	
	input [5:0] cmd1,
	input [31:0] arg1,
	input [6:0] crc1,
	input sta1,
	input sta401,
	input readit1,
	input init1,
	
	input [5:0] cmd2,
	input [31:0] arg2,
	input [6:0] crc2,
	input sta2,
	input sta402,
	input readit2,
	input init2,
	
	output reg [5:0] cmd,
	output reg [31:0] arg,
	output reg [6:0] crc,
	output reg sta,
	output reg sta40,
	output reg readit,
	output reg init
);


always@(posedge clk or posedge rst)begin
	if(rst)begin
		cmd <= 0;
		arg <= 0;
		crc <= 0;
		sta <= 0;
		sta40 <= 0;
		readit <= 0;
		init <= 0;
	end else
	begin
		cmd <= cmd1 | cmd2;
		arg <= arg1 | arg2;
		crc <= crc1 | crc2;
		sta <= sta1 | sta2;
		sta40 <= sta401 | sta402;
		readit <= readit1 | readit2;
		init <= init1 | init2;
	end
end

endmodule