data/full_repos/permissive/46132596/processor/SingleCycleDatapath/Mux.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/46132596/processor/SingleCycleDatapath/Mux.v:10: Multiple top level modules\n                                                                                             : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                             : ... Top module \'Mux32Bit2To1\'\nmodule Mux32Bit2To1(input[31:0] in0,\n       ^~~~~~~~~~~~\n                                                                                             : ... Top module \'Mux5Bit2To1\'\nmodule Mux5Bit2To1(input[4:0] in0,\n       ^~~~~~~~~~~\n                                                                                             : ... Top module \'Mux32Bit4To1\'\nmodule Mux32Bit4To1(input[31:0] in0,\n       ^~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module Mux32Bit4To1(input[31:0] in0,
                    input[31:0] in1,
                    input[31:0] in2,
                    input[31:0] in3,
                    input[1:0] sel,
                    output reg[31:0] out);

    always @(sel, in0, in1, in2, in3)
        case (sel)
            0: out = in0;
            1: out = in1;
            2: out = in2;
            3: out = in3;
        endcase

endmodule
module Mux32Bit4To1(input[31:0] in0,
                    input[31:0] in1,
                    input[31:0] in2,
                    input[31:0] in3,
                    input[1:0] sel,
                    output reg[31:0] out);


    always @(sel, in0, in1, in2, in3)
        case (sel)
            0: out = in0;
            1: out = in1;
            2: out = in2;
            3: out = in3;
        endcase

endmodule