data/full_repos/permissive/527176783/Single/A_Single/mux4.v
1: b'%Error: data/full_repos/permissive/527176783/Single/A_Single/mux4.v:2: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/527176783/Single/A_Single,data/full_repos/permissive/527176783/define.v\n             data/full_repos/permissive/527176783/Single/A_Single,data/full_repos/permissive/527176783/define.v.v\n             data/full_repos/permissive/527176783/Single/A_Single,data/full_repos/permissive/527176783/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/527176783/Single/A_Single/mux4.v:17: Define or directive not defined: \'`NextIns\'\n            `NextIns: result = pc_add4;\n            ^~~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/mux4.v:17: syntax error, unexpected \':\', expecting endcase\n            `NextIns: result = pc_add4;\n                    ^\n%Error: data/full_repos/permissive/527176783/Single/A_Single/mux4.v:18: Define or directive not defined: \'`Jump\'\n            `Jump: result = pc_jump;\n            ^~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/mux4.v:19: Define or directive not defined: \'`Branch\'\n            `Branch: result = branch;\n            ^~~~~~~\n%Error: data/full_repos/permissive/527176783/Single/A_Single/mux4.v:20: Define or directive not defined: \'`Zero\'\n            `Zero: result = zero;\n            ^~~~~\n%Error: Cannot continue\n'
module mux4(
    input   [31:0] pc_add4,
    input   [31:0] zero,
    input   [31:0] branch,
    input   [31:0] pc_jump,
    input   [1:0]  sel,
    output  reg [31:0] result
);
    initial begin
        result = 0;
    end
    always @(*) begin
        case (sel)
            `NextIns: result = pc_add4;
            `Jump: result = pc_jump;
            `Branch: result = branch;
            `Zero: result = zero;
            default: result = pc_add4;
        endcase
    end
endmodule
module mux4(
    input   [31:0] pc_add4,
    input   [31:0] zero,
    input   [31:0] branch,
    input   [31:0] pc_jump,
    input   [1:0]  sel,
    output  reg [31:0] result
);

    initial begin
        result = 0;
    end
    always @(*) begin
        case (sel)
            `NextIns: result = pc_add4;
            `Jump: result = pc_jump;
            `Branch: result = branch;
            `Zero: result = zero;
            default: result = pc_add4;
        endcase
    end
endmodule