data/full_repos/permissive/440264724/hdl/peri/gpio/gpio_regs.v
data/verilator_xmls/fff5a336-e1ca-4ead-8cd3-2d3afa4241fd.xml
module gpio_regs (
	input wire clk,
	input wire rst_n,
	

	input wire apbs_psel,
	input wire apbs_penable,
	input wire apbs_pwrite,
	input wire [15:0] apbs_paddr,
	input wire [31:0] apbs_pwdata,
	output wire [31:0] apbs_prdata,
	output wire apbs_pready,
	output wire apbs_pslverr,
	

	output reg [7:0] o_o,
	output reg [7:0] oe_o,
	input wire [7:0] i_i
);


wire [31:0] wdata = apbs_pwdata;
reg [31:0] rdata;
wire wen = apbs_psel && apbs_penable && apbs_pwrite;
wire ren = apbs_psel && apbs_penable && !apbs_pwrite;
wire [15:0] addr = apbs_paddr & 16'hc;
assign apbs_prdata = rdata;
assign apbs_pready = 1'b1;
assign apbs_pslverr = 1'b0;

localparam ADDR_O = 0;
localparam ADDR_OE = 4;
localparam ADDR_I = 8;

wire __o_wen = wen && addr == ADDR_O;
wire __o_ren = ren && addr == ADDR_O;
wire __oe_wen = wen && addr == ADDR_OE;
wire __oe_ren = ren && addr == ADDR_OE;
wire __i_wen = wen && addr == ADDR_I;
wire __i_ren = ren && addr == ADDR_I;

wire [7:0] o_wdata = wdata[7:0];
wire [7:0] o_rdata;
wire [31:0] __o_rdata = {24'h0, o_rdata};
assign o_rdata = o_o;

wire [7:0] oe_wdata = wdata[7:0];
wire [7:0] oe_rdata;
wire [31:0] __oe_rdata = {24'h0, oe_rdata};
assign oe_rdata = oe_o;

wire [7:0] i_wdata = wdata[7:0];
wire [7:0] i_rdata;
wire [31:0] __i_rdata = {24'h0, i_rdata};
assign i_rdata = i_i;

always @ (*) begin
	case (addr)
		ADDR_O: rdata = __o_rdata;
		ADDR_OE: rdata = __oe_rdata;
		ADDR_I: rdata = __i_rdata;
		default: rdata = 32'h0;
	endcase
end

always @ (posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		o_o <= 8'h0;
		oe_o <= 8'h0;
	end else begin
		if (__o_wen)
			o_o <= o_wdata;
		if (__oe_wen)
			oe_o <= oe_wdata;
	end
end

endmodule
module gpio_regs (
	input wire clk,
	input wire rst_n,
	

	input wire apbs_psel,
	input wire apbs_penable,
	input wire apbs_pwrite,
	input wire [15:0] apbs_paddr,
	input wire [31:0] apbs_pwdata,
	output wire [31:0] apbs_prdata,
	output wire apbs_pready,
	output wire apbs_pslverr,
	

	output reg [7:0] o_o,
	output reg [7:0] oe_o,
	input wire [7:0] i_i
);



wire [31:0] wdata = apbs_pwdata;
reg [31:0] rdata;
wire wen = apbs_psel && apbs_penable && apbs_pwrite;
wire ren = apbs_psel && apbs_penable && !apbs_pwrite;
wire [15:0] addr = apbs_paddr & 16'hc;
assign apbs_prdata = rdata;
assign apbs_pready = 1'b1;
assign apbs_pslverr = 1'b0;

localparam ADDR_O = 0;
localparam ADDR_OE = 4;
localparam ADDR_I = 8;

wire __o_wen = wen && addr == ADDR_O;
wire __o_ren = ren && addr == ADDR_O;
wire __oe_wen = wen && addr == ADDR_OE;
wire __oe_ren = ren && addr == ADDR_OE;
wire __i_wen = wen && addr == ADDR_I;
wire __i_ren = ren && addr == ADDR_I;

wire [7:0] o_wdata = wdata[7:0];
wire [7:0] o_rdata;
wire [31:0] __o_rdata = {24'h0, o_rdata};
assign o_rdata = o_o;

wire [7:0] oe_wdata = wdata[7:0];
wire [7:0] oe_rdata;
wire [31:0] __oe_rdata = {24'h0, oe_rdata};
assign oe_rdata = oe_o;

wire [7:0] i_wdata = wdata[7:0];
wire [7:0] i_rdata;
wire [31:0] __i_rdata = {24'h0, i_rdata};
assign i_rdata = i_i;

always @ (*) begin
	case (addr)
		ADDR_O: rdata = __o_rdata;
		ADDR_OE: rdata = __oe_rdata;
		ADDR_I: rdata = __i_rdata;
		default: rdata = 32'h0;
	endcase
end

always @ (posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		o_o <= 8'h0;
		oe_o <= 8'h0;
	end else begin
		if (__o_wen)
			o_o <= o_wdata;
		if (__oe_wen)
			oe_o <= oe_wdata;
	end
end

endmodule