data/full_repos/permissive/484316383/rtl/common/multiboot.v
1: b'%Error: data/full_repos/permissive/484316383/rtl/common/multiboot.v:71: Cannot find file containing module: \'ICAP_SPARTAN6\'\n  ICAP_SPARTAN6 ICAP_SPARTAN6_inst (\n  ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/484316383/rtl/common,data/full_repos/permissive/484316383/ICAP_SPARTAN6\n             data/full_repos/permissive/484316383/rtl/common,data/full_repos/permissive/484316383/ICAP_SPARTAN6.v\n             data/full_repos/permissive/484316383/rtl/common,data/full_repos/permissive/484316383/ICAP_SPARTAN6.sv\n             ICAP_SPARTAN6\n             ICAP_SPARTAN6.v\n             ICAP_SPARTAN6.sv\n             obj_dir/ICAP_SPARTAN6\n             obj_dir/ICAP_SPARTAN6.v\n             obj_dir/ICAP_SPARTAN6.sv\n%Warning-WIDTH: data/full_repos/permissive/484316383/rtl/common/multiboot.v:20: Operator SUB expects 32 or 24 bits on the LHS, but LHS\'s VARREF \'corenn\' generates 8 bits.\n                                                                              : ... In instance bootcore\n   else if (corenn < 46) reset_spi_addr <= (24\'h054000 * (corenn - 10)) + 24\'h400000;\n                                                                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module bootcore (
    input wire clk_icap,
    input wire coldreset,
	 input wire masterreset,
	 input wire we,
	 input wire [7:0] corenn,
	 output reg coreset = 1'b0
    );
    
	 reg [23:0] reset_spi_addr;
    reg [4:0] q1 = 5'b00000;
	 reg [4:0] q2 = 5'b00000;
    reg reboot_ff = 1'b0;
    always @(posedge clk_icap) begin

		if (we) begin			
			coreset <= 1'b1;
			if (corenn == 0) reset_spi_addr <= 0;
			else if (corenn < 10) reset_spi_addr <= (24'h054000 * corenn) + 24'h004000;
			else if (corenn < 46) reset_spi_addr <= (24'h054000 * (corenn - 10)) + 24'h400000;
			else reset_spi_addr <= 0;			
		end
		if (coreset) begin
			q1[0] <= coldreset;
			q1[1] <= q1[0];
			q1[2] <= q1[1];
			q1[3] <= q1[2];
			q1[4] <= q1[3];
		end

		q2[0] <= masterreset;
		q2[1] <= q2[0];
		q2[2] <= q2[1];
		q2[3] <= q2[2];
		q2[4] <= q2[3];
		
		if (q1[4] && (!q1[3]) && (!q1[2]) && (!q1[1]) ) reboot_ff <= 1'b1;
			
		else if (q2[4] && (!q2[3]) && (!q2[2]) && (!q2[1]) ) begin
			reboot_ff <= 1'b1;
			reset_spi_addr <= 24'h000000;
		end
		
    end	 
	 
	 multiboot_spartan6 multiboot (
      .CLK(clk_icap),
		.MBT_RESET(1'b0),
		.MBT_REBOOT(reboot_ff),
		.spi_addr(reset_spi_addr)
    );
	 
endmodule
module bootcore (
    input wire clk_icap,
    input wire coldreset,
	 input wire masterreset,
	 input wire we,
	 input wire [7:0] corenn,
	 output reg coreset = 1'b0
    );

    
	 reg [23:0] reset_spi_addr;
    reg [4:0] q1 = 5'b00000;
	 reg [4:0] q2 = 5'b00000;
    reg reboot_ff = 1'b0;
    always @(posedge clk_icap) begin

		if (we) begin			
			coreset <= 1'b1;
			if (corenn == 0) reset_spi_addr <= 0;
			else if (corenn < 10) reset_spi_addr <= (24'h054000 * corenn) + 24'h004000;
			else if (corenn < 46) reset_spi_addr <= (24'h054000 * (corenn - 10)) + 24'h400000;
			else reset_spi_addr <= 0;			
		end
		if (coreset) begin
			q1[0] <= coldreset;
			q1[1] <= q1[0];
			q1[2] <= q1[1];
			q1[3] <= q1[2];
			q1[4] <= q1[3];
		end

		q2[0] <= masterreset;
		q2[1] <= q2[0];
		q2[2] <= q2[1];
		q2[3] <= q2[2];
		q2[4] <= q2[3];
		
		if (q1[4] && (!q1[3]) && (!q1[2]) && (!q1[1]) ) reboot_ff <= 1'b1;
			
		else if (q2[4] && (!q2[3]) && (!q2[2]) && (!q2[1]) ) begin
			reboot_ff <= 1'b1;
			reset_spi_addr <= 24'h000000;
		end
		
    end	 
	 
	 multiboot_spartan6 multiboot (
      .CLK(clk_icap),
		.MBT_RESET(1'b0),
		.MBT_REBOOT(reboot_ff),
		.spi_addr(reset_spi_addr)
    );
	 
endmodule