data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new/uart_main.v
1: b"%Error: data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new/uart_main.v:35: Cannot find file containing module: 'baudrate_gen'\n    baudrate_gen baudgen(baud, clk);\n    ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new,data/full_repos/permissive/423958267/baudrate_gen\n             data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new,data/full_repos/permissive/423958267/baudrate_gen.v\n             data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new,data/full_repos/permissive/423958267/baudrate_gen.sv\n             baudrate_gen\n             baudrate_gen.v\n             baudrate_gen.sv\n             obj_dir/baudrate_gen\n             obj_dir/baudrate_gen.v\n             obj_dir/baudrate_gen.sv\n%Error: data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new/uart_main.v:36: Cannot find file containing module: 'transmitter'\n    transmitter t(RsTx, sent, data_send, en, baud);\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/423958267/lab06/lab06.srcs/sources_1/new/uart_main.v:37: Cannot find file containing module: 'receiver'\n    receiver r(data_receive, received, RsRx, baud);\n    ^~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module uart_main(
    output RsTx,
    input RsRx,
    input clk
);
    
    wire baud;
    wire received, sent;
    wire [7:0] data_receive;
    reg [7:0] data_send;
    reg en;

    baudrate_gen baudgen(baud, clk);
    transmitter t(RsTx, sent, data_send, en, baud);
    receiver r(data_receive, received, RsRx, baud);

    initial begin
        en <= 1;
    end

    reg oldre;

    always @(posedge baud) begin
        if(en == 1) en <= 0;

        if(!oldre && received) begin
            data_send <= data_receive + 1;
            en <= 1;
        end
        
        oldre <= received;
    end

endmodule
module uart_main(
    output RsTx,
    input RsRx,
    input clk
);

    
    wire baud;
    wire received, sent;
    wire [7:0] data_receive;
    reg [7:0] data_send;
    reg en;

    baudrate_gen baudgen(baud, clk);
    transmitter t(RsTx, sent, data_send, en, baud);
    receiver r(data_receive, received, RsRx, baud);

    initial begin
        en <= 1;
    end

    reg oldre;

    always @(posedge baud) begin
        if(en == 1) en <= 0;

        if(!oldre && received) begin
            data_send <= data_receive + 1;
            en <= 1;
        end
        
        oldre <= received;
    end

endmodule