data/full_repos/permissive/430189947/sim_1/imports/tb_debouncer.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/430189947/sim_1/imports/tb_debouncer.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #(clock_period / 2); \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/430189947/sim_1/imports/tb_debouncer.v:28: Unsupported: Ignoring delay on this delayed statement.\n  # (2*(10**6));     \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/430189947/sim_1/imports/tb_debouncer.v:31: Unsupported: Ignoring delay on this delayed statement.\n  # (100*(10**3));   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/430189947/sim_1/imports/tb_debouncer.v:33: Unsupported: Ignoring delay on this delayed statement.\n  # (200*(10**3));   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/430189947/sim_1/imports/tb_debouncer.v:35: Unsupported: Ignoring delay on this delayed statement.\n  # (100*(10**3));   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/430189947/sim_1/imports/tb_debouncer.v:37: Unsupported: Ignoring delay on this delayed statement.\n  # (100*(10**3));   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/430189947/sim_1/imports/tb_debouncer.v:39: Unsupported: Ignoring delay on this delayed statement.\n  # (800*(10**3));   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/430189947/sim_1/imports/tb_debouncer.v:41: Unsupported: Ignoring delay on this delayed statement.\n  # (50*(10**3));    \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/430189947/sim_1/imports/tb_debouncer.v:43: Unsupported: Ignoring delay on this delayed statement.\n  # (3*(10**6));     \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/430189947/sim_1/imports/tb_debouncer.v:46: Unsupported: Ignoring delay on this delayed statement.\n  # (100*(10**3));   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/430189947/sim_1/imports/tb_debouncer.v:48: Unsupported: Ignoring delay on this delayed statement.\n  # (200*(10**3));   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/430189947/sim_1/imports/tb_debouncer.v:50: Unsupported: Ignoring delay on this delayed statement.\n  # (950*(10**3));   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/430189947/sim_1/imports/tb_debouncer.v:52: Unsupported: Ignoring delay on this delayed statement.\n  # (150*(10**3));   \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/430189947/sim_1/imports/tb_debouncer.v:54: Unsupported: Ignoring delay on this delayed statement.\n  # (2*(10**6));     \n  ^\n%Error: data/full_repos/permissive/430189947/sim_1/imports/tb_debouncer.v:23: Cannot find file containing module: \'debouncer\'\n debouncer #(.clock_freq(clock_freq), .debounce_time(debounce_time), .initial_value(initial_value)) uut(.clk(clk), .signal_i(signal_i), .signal_o(signal_o));\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/430189947/sim_1/imports,data/full_repos/permissive/430189947/debouncer\n             data/full_repos/permissive/430189947/sim_1/imports,data/full_repos/permissive/430189947/debouncer.v\n             data/full_repos/permissive/430189947/sim_1/imports,data/full_repos/permissive/430189947/debouncer.sv\n             debouncer\n             debouncer.v\n             debouncer.sv\n             obj_dir/debouncer\n             obj_dir/debouncer.v\n             obj_dir/debouncer.sv\n%Error: Exiting due to 1 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_debouncer;

	reg clk;
	reg signal_i;
	wire signal_o;
	
	localparam clock_freq = 100_000_000,
			   clock_period = 10,
			   debounce_time = 1000,	
		       initial_value = 1'b0;
	
	initial begin	
		clk = 1'b0;    	
	end
	
	always begin 
		clk <= ~clk; 
		#(clock_period / 2); 
	end
	
	debouncer #(.clock_freq(clock_freq), .debounce_time(debounce_time), .initial_value(initial_value)) uut(.clk(clk), .signal_i(signal_i), .signal_o(signal_o));
	
	always begin
	
		signal_i = 0;
		# (2*(10**6));
		
		signal_i = 1;
		# (100*(10**3));
		signal_i = 0;
		# (200*(10**3));
		signal_i = 1;
		# (100*(10**3));
		signal_i = 0;
		# (100*(10**3));
		signal_i = 1;
		# (800*(10**3));
		signal_i = 0;
		# (50*(10**3));
		signal_i = 1;
		# (3*(10**6));
		
		signal_i = 0;
		# (100*(10**3));
		signal_i = 1;
		# (200*(10**3));
		signal_i = 0;
		# (950*(10**3));
		signal_i = 1;
		# (150*(10**3));
		signal_i = 0;
		# (2*(10**6));
		
		$display("Simulasyon Tamamlandi");
		$finish;

	end
	
	

endmodule
module tb_debouncer;


	reg clk;
	reg signal_i;
	wire signal_o;
	
	localparam clock_freq = 100_000_000,
			   clock_period = 10,
			   debounce_time = 1000,	
		       initial_value = 1'b0;
	
	initial begin	
		clk = 1'b0;    	
	end
	
	always begin 
		clk <= ~clk; 
		#(clock_period / 2); 
	end
	
	debouncer #(.clock_freq(clock_freq), .debounce_time(debounce_time), .initial_value(initial_value)) uut(.clk(clk), .signal_i(signal_i), .signal_o(signal_o));
	
	always begin
	
		signal_i = 0;
		# (2*(10**6));
		
		signal_i = 1;
		# (100*(10**3));
		signal_i = 0;
		# (200*(10**3));
		signal_i = 1;
		# (100*(10**3));
		signal_i = 0;
		# (100*(10**3));
		signal_i = 1;
		# (800*(10**3));
		signal_i = 0;
		# (50*(10**3));
		signal_i = 1;
		# (3*(10**6));
		
		signal_i = 0;
		# (100*(10**3));
		signal_i = 1;
		# (200*(10**3));
		signal_i = 0;
		# (950*(10**3));
		signal_i = 1;
		# (150*(10**3));
		signal_i = 0;
		# (2*(10**6));
		
		$display("Simulasyon Tamamlandi");
		$finish;

	end
	
	

endmodule