data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ram/tb_alram112x.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ram/tb_alram112x.v:12: Unsupported: Ignoring delay on this delayed statement.\n#100 clk=1;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ram/tb_alram112x.v:13: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ram/tb_alram112x.v:42: Unsupported: Ignoring delay on this delayed statement.\n#100 rst = 0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ram/tb_alram112x.v:47: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ram/tb_alram112x.v:49: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ram/tb_alram112x.v:54: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ram/tb_alram112x.v:56: Unsupported: Ignoring delay on this delayed statement.\n#1000;\n^\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ram/tb_alram112x.v:25: Cannot find file containing module: \'alram112x\'\nalram112x ialram112x\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ram,data/full_repos/permissive/530013823/alram112x\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ram,data/full_repos/permissive/530013823/alram112x.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ram,data/full_repos/permissive/530013823/alram112x.sv\n             alram112x\n             alram112x.v\n             alram112x.sv\n             obj_dir/alram112x\n             obj_dir/alram112x.v\n             obj_dir/alram112x.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_alram112x;
`define RWSAMECLK
parameter WID = 256;
parameter AWID = 5;
parameter DEP = 1<<AWID;

reg       clk;
reg       rst;

always begin
clk = 0;
#100 clk=1;
#100;
end


reg [AWID-1:0] ra;
reg [AWID-1:0] wa;
reg [WID-1:0] wdi;
reg           we;

wire [WID-1:0] rdo;


alram112x ialram112x
    (
     .clkw(clk),
     .clkr(clk),
     .rst(rst),
     
     .rdo(rdo),
     .ra(ra),
     
     .wdi(wdi),
     .wa(wa),
     .we(we)
     );


initial begin
rst = 1;
#100 rst = 0;
we = 1;
wa = 5'd12;
wdi = 256'd1230;
ra = 5'd12;
#100;
we = 0;
#100;
ra = 5'd13;
we = 1;
wa = 5'd13;
wdi = 256'd1330;
#100;
we = 0;
#1000;
$stop;
end
endmodule
module tb_alram112x;

`define RWSAMECLK
parameter WID = 256;
parameter AWID = 5;
parameter DEP = 1<<AWID;

reg       clk;
reg       rst;

always begin
clk = 0;
#100 clk=1;
#100;
end


reg [AWID-1:0] ra;
reg [AWID-1:0] wa;
reg [WID-1:0] wdi;
reg           we;

wire [WID-1:0] rdo;


alram112x ialram112x
    (
     .clkw(clk),
     .clkr(clk),
     .rst(rst),
     
     .rdo(rdo),
     .ra(ra),
     
     .wdi(wdi),
     .wa(wa),
     .we(we)
     );


initial begin
rst = 1;
#100 rst = 0;
we = 1;
wa = 5'd12;
wdi = 256'd1230;
ra = 5'd12;
#100;
we = 0;
#100;
ra = 5'd13;
we = 1;
wa = 5'd13;
wdi = 256'd1330;
#100;
we = 0;
#1000;
$stop;
end
endmodule