data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/InstructionFetch/ProgramCounter.v
data/verilator_xmls/d5358c9c-415f-4538-9701-24f581bfe022.xml
module ProgramCounter(
    input [63:0] nextPc,
    input clk,
    input stall, 
    
    output reg [63:0] pc
);

    initial pc = 64'h0;

    always @(posedge clk)
        if (stall == 0)
            pc <= nextPc;

endmodule
module ProgramCounter(
    input [63:0] nextPc,
    input clk,
    input stall, 
    
    output reg [63:0] pc
);


    initial pc = 64'h0;

    always @(posedge clk)
        if (stall == 0)
            pc <= nextPc;

endmodule