data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_drive_spi/rtl/wfg_drive_spi_top.sv
1: b"%Error: data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_drive_spi/rtl/wfg_drive_spi_top.sv:56: Cannot find file containing module: 'wfg_drive_spi_wishbone_reg'\n    wfg_drive_spi_wishbone_reg wfg_drive_spi_wishbone_reg (\n    ^~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_drive_spi/rtl,data/full_repos/permissive/500717851/wfg_drive_spi_wishbone_reg\n             data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_drive_spi/rtl,data/full_repos/permissive/500717851/wfg_drive_spi_wishbone_reg.v\n             data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_drive_spi/rtl,data/full_repos/permissive/500717851/wfg_drive_spi_wishbone_reg.sv\n             wfg_drive_spi_wishbone_reg\n             wfg_drive_spi_wishbone_reg.v\n             wfg_drive_spi_wishbone_reg.sv\n             obj_dir/wfg_drive_spi_wishbone_reg\n             obj_dir/wfg_drive_spi_wishbone_reg.v\n             obj_dir/wfg_drive_spi_wishbone_reg.sv\n%Error: data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_drive_spi/rtl/wfg_drive_spi_top.sv:84: Cannot find file containing module: 'wfg_drive_spi'\n    wfg_drive_spi wfg_drive_spi (\n    ^~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module wfg_drive_spi_top #(
    parameter int BUSW = 32,
    parameter int AXIS_DATA_WIDTH = 32
) (

    input                 wb_clk_i,
    input                 wb_rst_i,
    input                 wbs_stb_i,
    input                 wbs_cyc_i,
    input                 wbs_we_i,
    input  [(BUSW/8-1):0] wbs_sel_i,
    input  [  (BUSW-1):0] wbs_dat_i,
    input  [  (BUSW-1):0] wbs_adr_i,
    output                wbs_ack_o,
    output [  (BUSW-1):0] wbs_dat_o,


    input wire wfg_core_sync_i,
    input wire wfg_core_subcycle_i,


    input logic wfg_subcore_sync_i,
    input logic wfg_subcore_subcycle_i,


    output wire wfg_axis_tready_o,
    input wire [AXIS_DATA_WIDTH-1:0] wfg_axis_tdata_i,
    input wire wfg_axis_tlast_i,
    input wire wfg_axis_tvalid_i,


    output wire wfg_drive_spi_sclk_o,
    output wire wfg_drive_spi_cs_no,
    output wire wfg_drive_spi_sdo_o
);






    logic         cfg_core_sel_q;
    logic         cfg_cpol_q;
    logic [ 3: 2] cfg_dff_q;
    logic         cfg_lsbfirst_q;
    logic         cfg_sspol_q;
    logic [ 7: 0] clkcfg_div_q;
    logic         ctrl_en_q;



    wfg_drive_spi_wishbone_reg wfg_drive_spi_wishbone_reg (
        .wb_clk_i (wb_clk_i),
        .wb_rst_i (wb_rst_i),
        .wbs_stb_i(wbs_stb_i),
        .wbs_cyc_i(wbs_cyc_i),
        .wbs_we_i (wbs_we_i),
        .wbs_sel_i(wbs_sel_i),
        .wbs_dat_i(wbs_dat_i),
        .wbs_adr_i(wbs_adr_i),
        .wbs_ack_o(wbs_ack_o),
        .wbs_dat_o(wbs_dat_o),






        .cfg_core_sel_q_o(cfg_core_sel_q),
        .cfg_cpol_q_o    (cfg_cpol_q),
        .cfg_dff_q_o     (cfg_dff_q),
        .cfg_lsbfirst_q_o(cfg_lsbfirst_q),
        .cfg_sspol_q_o   (cfg_sspol_q),
        .clkcfg_div_q_o  (clkcfg_div_q),
        .ctrl_en_q_o     (ctrl_en_q)


    );

    wfg_drive_spi wfg_drive_spi (
        .clk  (wb_clk_i),
        .rst_n(!wb_rst_i),


        .wfg_core_sync_i    (wfg_core_sync_i),
        .wfg_core_subcycle_i(wfg_core_subcycle_i),


        .wfg_subcore_sync_i    (wfg_subcore_sync_i),
        .wfg_subcore_subcycle_i(wfg_subcore_subcycle_i),


        .wfg_axis_tready_o(wfg_axis_tready_o),
        .wfg_axis_tvalid_i(wfg_axis_tvalid_i),
        .wfg_axis_tlast_i (wfg_axis_tlast_i),
        .wfg_axis_tdata_i (wfg_axis_tdata_i),


        .ctrl_en_q_i(ctrl_en_q),


        .clkcfg_div_q_i  (clkcfg_div_q),
        .cfg_cpol_q_i    (cfg_cpol_q),
        .cfg_lsbfirst_q_i(cfg_lsbfirst_q),
        .cfg_dff_q_i     (cfg_dff_q),
        .cfg_sspol_q_i   (cfg_sspol_q),
        .cfg_core_sel_q_i(cfg_core_sel_q),


        .wfg_drive_spi_sclk_o(wfg_drive_spi_sclk_o),
        .wfg_drive_spi_cs_no (wfg_drive_spi_cs_no),
        .wfg_drive_spi_sdo_o (wfg_drive_spi_sdo_o)
    );

endmodule
module wfg_drive_spi_top #(
    parameter int BUSW = 32,
    parameter int AXIS_DATA_WIDTH = 32
) (

    input                 wb_clk_i,
    input                 wb_rst_i,
    input                 wbs_stb_i,
    input                 wbs_cyc_i,
    input                 wbs_we_i,
    input  [(BUSW/8-1):0] wbs_sel_i,
    input  [  (BUSW-1):0] wbs_dat_i,
    input  [  (BUSW-1):0] wbs_adr_i,
    output                wbs_ack_o,
    output [  (BUSW-1):0] wbs_dat_o,


    input wire wfg_core_sync_i,
    input wire wfg_core_subcycle_i,


    input logic wfg_subcore_sync_i,
    input logic wfg_subcore_subcycle_i,


    output wire wfg_axis_tready_o,
    input wire [AXIS_DATA_WIDTH-1:0] wfg_axis_tdata_i,
    input wire wfg_axis_tlast_i,
    input wire wfg_axis_tvalid_i,


    output wire wfg_drive_spi_sclk_o,
    output wire wfg_drive_spi_cs_no,
    output wire wfg_drive_spi_sdo_o
);







    logic         cfg_core_sel_q;
    logic         cfg_cpol_q;
    logic [ 3: 2] cfg_dff_q;
    logic         cfg_lsbfirst_q;
    logic         cfg_sspol_q;
    logic [ 7: 0] clkcfg_div_q;
    logic         ctrl_en_q;



    wfg_drive_spi_wishbone_reg wfg_drive_spi_wishbone_reg (
        .wb_clk_i (wb_clk_i),
        .wb_rst_i (wb_rst_i),
        .wbs_stb_i(wbs_stb_i),
        .wbs_cyc_i(wbs_cyc_i),
        .wbs_we_i (wbs_we_i),
        .wbs_sel_i(wbs_sel_i),
        .wbs_dat_i(wbs_dat_i),
        .wbs_adr_i(wbs_adr_i),
        .wbs_ack_o(wbs_ack_o),
        .wbs_dat_o(wbs_dat_o),






        .cfg_core_sel_q_o(cfg_core_sel_q),
        .cfg_cpol_q_o    (cfg_cpol_q),
        .cfg_dff_q_o     (cfg_dff_q),
        .cfg_lsbfirst_q_o(cfg_lsbfirst_q),
        .cfg_sspol_q_o   (cfg_sspol_q),
        .clkcfg_div_q_o  (clkcfg_div_q),
        .ctrl_en_q_o     (ctrl_en_q)


    );

    wfg_drive_spi wfg_drive_spi (
        .clk  (wb_clk_i),
        .rst_n(!wb_rst_i),


        .wfg_core_sync_i    (wfg_core_sync_i),
        .wfg_core_subcycle_i(wfg_core_subcycle_i),


        .wfg_subcore_sync_i    (wfg_subcore_sync_i),
        .wfg_subcore_subcycle_i(wfg_subcore_subcycle_i),


        .wfg_axis_tready_o(wfg_axis_tready_o),
        .wfg_axis_tvalid_i(wfg_axis_tvalid_i),
        .wfg_axis_tlast_i (wfg_axis_tlast_i),
        .wfg_axis_tdata_i (wfg_axis_tdata_i),


        .ctrl_en_q_i(ctrl_en_q),


        .clkcfg_div_q_i  (clkcfg_div_q),
        .cfg_cpol_q_i    (cfg_cpol_q),
        .cfg_lsbfirst_q_i(cfg_lsbfirst_q),
        .cfg_dff_q_i     (cfg_dff_q),
        .cfg_sspol_q_i   (cfg_sspol_q),
        .cfg_core_sel_q_i(cfg_core_sel_q),


        .wfg_drive_spi_sclk_o(wfg_drive_spi_sclk_o),
        .wfg_drive_spi_cs_no (wfg_drive_spi_cs_no),
        .wfg_drive_spi_sdo_o (wfg_drive_spi_sdo_o)
    );

endmodule