data/full_repos/permissive/493019833/test/testcase/firrtl/DspComplexExamplesTester/reference/DspComplexExamplesTester.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/DspComplexExamplesTester/reference/DspComplexExamplesTester.v:452: Operator COND expects 5 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                                                           : ... In instance DspComplexExamplesTester.s_pad_39\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/DspComplexExamplesTester/reference/DspComplexExamplesTester.v:452: Operator COND expects 5 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 2 bits.\n                                                                                                                                           : ... In instance DspComplexExamplesTester.s_pad_44\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/DspComplexExamplesTester/reference/DspComplexExamplesTester.v:452: Operator COND expects 5 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 4 bits.\n                                                                                                                                           : ... In instance DspComplexExamplesTester.s_pad_49\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/DspComplexExamplesTester/reference/DspComplexExamplesTester.v:452: Operator COND expects 5 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 3 bits.\n                                                                                                                                           : ... In instance DspComplexExamplesTester.s_pad_71\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/DspComplexExamplesTester/reference/DspComplexExamplesTester.v:452: Operator COND expects 2 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                                                           : ... In instance DspComplexExamplesTester.dut.s_pad_1\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/DspComplexExamplesTester/reference/DspComplexExamplesTester.v:452: Operator COND expects 7 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 6 bits.\n                                                                                                                                           : ... In instance DspComplexExamplesTester.dut.s_pad_17\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Error: Exiting due to 6 warning(s)\n'
module DspComplexExamples(
    input clock,
    input reset,
    input [4:0] io_in_real,
    input [4:0] io_in_imag,
    output [4:0] io_outJ_real,
    output [4:0] io_outJ_imag,
    output [4:0] io_inByJ_real,
    output [4:0] io_inByJ_imag,
    output [4:0] io_inByJShortcut_real,
    output [4:0] io_inByJShortcut_imag
);
    wire _T_39_real;
    wire [1:0] _T_39_imag;
    wire _T_49_real;
    wire [1:0] _T_49_imag;
    wire [2:0] _T_50;
    wire [1:0] _WTEMP_0;
    PAD_SIGNED #(.width(1), .n(2)) s_pad_1 (
        .y(_WTEMP_0),
        .in(_T_49_real)
    );
    ADD_SIGNED #(.width(2)) s_add_2 (
        .y(_T_50),
        .a(_WTEMP_0),
        .b(_T_49_imag)
    );
    wire [1:0] _T_51;
    TAIL #(.width(3), .n(1)) tail_3 (
        .y(_T_51),
        .in(_T_50)
    );
    wire [1:0] _T_52;
    ASSINT #(.width(2)) assint_4 (
        .y(_T_52),
        .in(_T_51)
    );
    wire [5:0] _T_53;
    ADD_SIGNED #(.width(5)) s_add_5 (
        .y(_T_53),
        .a(io_in_real),
        .b(io_in_imag)
    );
    wire [4:0] _T_54;
    TAIL #(.width(6), .n(1)) tail_6 (
        .y(_T_54),
        .in(_T_53)
    );
    wire [4:0] _T_55;
    ASSINT #(.width(5)) assint_7 (
        .y(_T_55),
        .in(_T_54)
    );
    wire [5:0] _T_56;
    SUB_SIGNED #(.width(5)) s_sub_8 (
        .y(_T_56),
        .a(io_in_imag),
        .b(io_in_real)
    );
    wire [4:0] _T_57;
    TAIL #(.width(6), .n(1)) tail_9 (
        .y(_T_57),
        .in(_T_56)
    );
    wire [4:0] _T_58;
    ASSINT #(.width(5)) assint_10 (
        .y(_T_58),
        .in(_T_57)
    );
    wire [6:0] _T_59;
    MUL2_SIGNED #(.width_a(5), .width_b(2)) s_mul2_11 (
        .y(_T_59),
        .a(io_in_real),
        .b(_T_52)
    );
    wire [6:0] _T_60;
    MUL2_SIGNED #(.width_a(5), .width_b(2)) s_mul2_12 (
        .y(_T_60),
        .a(_T_55),
        .b(_T_49_imag)
    );
    wire [5:0] _T_61;
    MUL2_SIGNED #(.width_a(5), .width_b(1)) s_mul2_13 (
        .y(_T_61),
        .a(_T_58),
        .b(_T_49_real)
    );
    wire [7:0] _T_62;
    SUB_SIGNED #(.width(7)) s_sub_14 (
        .y(_T_62),
        .a(_T_59),
        .b(_T_60)
    );
    wire [6:0] _T_63;
    TAIL #(.width(8), .n(1)) tail_15 (
        .y(_T_63),
        .in(_T_62)
    );
    wire [6:0] _T_64;
    ASSINT #(.width(7)) assint_16 (
        .y(_T_64),
        .in(_T_63)
    );
    wire [7:0] _T_65;
    wire [6:0] _WTEMP_1;
    PAD_SIGNED #(.width(6), .n(7)) s_pad_17 (
        .y(_WTEMP_1),
        .in(_T_61)
    );
    ADD_SIGNED #(.width(7)) s_add_18 (
        .y(_T_65),
        .a(_T_59),
        .b(_WTEMP_1)
    );
    wire [6:0] _T_66;
    TAIL #(.width(8), .n(1)) tail_19 (
        .y(_T_66),
        .in(_T_65)
    );
    wire [6:0] _T_67;
    ASSINT #(.width(7)) assint_20 (
        .y(_T_67),
        .in(_T_66)
    );
    wire [6:0] _T_75_real;
    wire [6:0] _T_75_imag;
    wire [5:0] _T_77;
    wire [4:0] _WTEMP_2;
    PAD_SIGNED #(.width(1), .n(5)) s_pad_21 (
        .y(_WTEMP_2),
        .in(1'sh0)
    );
    SUB_SIGNED #(.width(5)) s_sub_22 (
        .y(_T_77),
        .a(_WTEMP_2),
        .b(io_in_imag)
    );
    wire [4:0] _T_78;
    TAIL #(.width(6), .n(1)) tail_23 (
        .y(_T_78),
        .in(_T_77)
    );
    wire [4:0] _T_79;
    ASSINT #(.width(5)) assint_24 (
        .y(_T_79),
        .in(_T_78)
    );
    wire [4:0] _T_87_real;
    wire [4:0] _T_87_imag;
    assign _T_39_imag = 2'sh1;
    assign _T_39_real = 1'sh0;
    assign _T_49_imag = 2'sh1;
    assign _T_49_real = 1'sh0;
    assign _T_75_imag = _T_67;
    assign _T_75_real = _T_64;
    assign _T_87_imag = io_in_real;
    assign _T_87_real = _T_79;
    wire [4:0] _WTEMP_3;
    BITS #(.width(7), .high(4), .low(0)) bits_25 (
        .y(_WTEMP_3),
        .in(_T_75_imag)
    );
    ASSINT #(.width(5)) assint_26 (
        .y(io_inByJ_imag),
        .in(_WTEMP_3)
    );
    wire [4:0] _WTEMP_4;
    BITS #(.width(7), .high(4), .low(0)) bits_27 (
        .y(_WTEMP_4),
        .in(_T_75_real)
    );
    ASSINT #(.width(5)) assint_28 (
        .y(io_inByJ_real),
        .in(_WTEMP_4)
    );
    assign io_inByJShortcut_imag = _T_87_imag;
    assign io_inByJShortcut_real = _T_87_real;
    PAD_SIGNED #(.width(2), .n(5)) s_pad_29 (
        .y(io_outJ_imag),
        .in(_T_39_imag)
    );
    PAD_SIGNED #(.width(1), .n(5)) s_pad_30 (
        .y(io_outJ_real),
        .in(_T_39_real)
    );
endmodule
module DspComplexExamples(
    input clock,
    input reset,
    input [4:0] io_in_real,
    input [4:0] io_in_imag,
    output [4:0] io_outJ_real,
    output [4:0] io_outJ_imag,
    output [4:0] io_inByJ_real,
    output [4:0] io_inByJ_imag,
    output [4:0] io_inByJShortcut_real,
    output [4:0] io_inByJShortcut_imag
);

    wire _T_39_real;
    wire [1:0] _T_39_imag;
    wire _T_49_real;
    wire [1:0] _T_49_imag;
    wire [2:0] _T_50;
    wire [1:0] _WTEMP_0;
    PAD_SIGNED #(.width(1), .n(2)) s_pad_1 (
        .y(_WTEMP_0),
        .in(_T_49_real)
    );
    ADD_SIGNED #(.width(2)) s_add_2 (
        .y(_T_50),
        .a(_WTEMP_0),
        .b(_T_49_imag)
    );
    wire [1:0] _T_51;
    TAIL #(.width(3), .n(1)) tail_3 (
        .y(_T_51),
        .in(_T_50)
    );
    wire [1:0] _T_52;
    ASSINT #(.width(2)) assint_4 (
        .y(_T_52),
        .in(_T_51)
    );
    wire [5:0] _T_53;
    ADD_SIGNED #(.width(5)) s_add_5 (
        .y(_T_53),
        .a(io_in_real),
        .b(io_in_imag)
    );
    wire [4:0] _T_54;
    TAIL #(.width(6), .n(1)) tail_6 (
        .y(_T_54),
        .in(_T_53)
    );
    wire [4:0] _T_55;
    ASSINT #(.width(5)) assint_7 (
        .y(_T_55),
        .in(_T_54)
    );
    wire [5:0] _T_56;
    SUB_SIGNED #(.width(5)) s_sub_8 (
        .y(_T_56),
        .a(io_in_imag),
        .b(io_in_real)
    );
    wire [4:0] _T_57;
    TAIL #(.width(6), .n(1)) tail_9 (
        .y(_T_57),
        .in(_T_56)
    );
    wire [4:0] _T_58;
    ASSINT #(.width(5)) assint_10 (
        .y(_T_58),
        .in(_T_57)
    );
    wire [6:0] _T_59;
    MUL2_SIGNED #(.width_a(5), .width_b(2)) s_mul2_11 (
        .y(_T_59),
        .a(io_in_real),
        .b(_T_52)
    );
    wire [6:0] _T_60;
    MUL2_SIGNED #(.width_a(5), .width_b(2)) s_mul2_12 (
        .y(_T_60),
        .a(_T_55),
        .b(_T_49_imag)
    );
    wire [5:0] _T_61;
    MUL2_SIGNED #(.width_a(5), .width_b(1)) s_mul2_13 (
        .y(_T_61),
        .a(_T_58),
        .b(_T_49_real)
    );
    wire [7:0] _T_62;
    SUB_SIGNED #(.width(7)) s_sub_14 (
        .y(_T_62),
        .a(_T_59),
        .b(_T_60)
    );
    wire [6:0] _T_63;
    TAIL #(.width(8), .n(1)) tail_15 (
        .y(_T_63),
        .in(_T_62)
    );
    wire [6:0] _T_64;
    ASSINT #(.width(7)) assint_16 (
        .y(_T_64),
        .in(_T_63)
    );
    wire [7:0] _T_65;
    wire [6:0] _WTEMP_1;
    PAD_SIGNED #(.width(6), .n(7)) s_pad_17 (
        .y(_WTEMP_1),
        .in(_T_61)
    );
    ADD_SIGNED #(.width(7)) s_add_18 (
        .y(_T_65),
        .a(_T_59),
        .b(_WTEMP_1)
    );
    wire [6:0] _T_66;
    TAIL #(.width(8), .n(1)) tail_19 (
        .y(_T_66),
        .in(_T_65)
    );
    wire [6:0] _T_67;
    ASSINT #(.width(7)) assint_20 (
        .y(_T_67),
        .in(_T_66)
    );
    wire [6:0] _T_75_real;
    wire [6:0] _T_75_imag;
    wire [5:0] _T_77;
    wire [4:0] _WTEMP_2;
    PAD_SIGNED #(.width(1), .n(5)) s_pad_21 (
        .y(_WTEMP_2),
        .in(1'sh0)
    );
    SUB_SIGNED #(.width(5)) s_sub_22 (
        .y(_T_77),
        .a(_WTEMP_2),
        .b(io_in_imag)
    );
    wire [4:0] _T_78;
    TAIL #(.width(6), .n(1)) tail_23 (
        .y(_T_78),
        .in(_T_77)
    );
    wire [4:0] _T_79;
    ASSINT #(.width(5)) assint_24 (
        .y(_T_79),
        .in(_T_78)
    );
    wire [4:0] _T_87_real;
    wire [4:0] _T_87_imag;
    assign _T_39_imag = 2'sh1;
    assign _T_39_real = 1'sh0;
    assign _T_49_imag = 2'sh1;
    assign _T_49_real = 1'sh0;
    assign _T_75_imag = _T_67;
    assign _T_75_real = _T_64;
    assign _T_87_imag = io_in_real;
    assign _T_87_real = _T_79;
    wire [4:0] _WTEMP_3;
    BITS #(.width(7), .high(4), .low(0)) bits_25 (
        .y(_WTEMP_3),
        .in(_T_75_imag)
    );
    ASSINT #(.width(5)) assint_26 (
        .y(io_inByJ_imag),
        .in(_WTEMP_3)
    );
    wire [4:0] _WTEMP_4;
    BITS #(.width(7), .high(4), .low(0)) bits_27 (
        .y(_WTEMP_4),
        .in(_T_75_real)
    );
    ASSINT #(.width(5)) assint_28 (
        .y(io_inByJ_real),
        .in(_WTEMP_4)
    );
    assign io_inByJShortcut_imag = _T_87_imag;
    assign io_inByJShortcut_real = _T_87_real;
    PAD_SIGNED #(.width(2), .n(5)) s_pad_29 (
        .y(io_outJ_imag),
        .in(_T_39_imag)
    );
    PAD_SIGNED #(.width(1), .n(5)) s_pad_30 (
        .y(io_outJ_real),
        .in(_T_39_real)
    );
endmodule