data/full_repos/permissive/458737381/src/verilog-parser/tests/named_block_disable.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/named_block_disable.v:24: Unsupported or unknown PLI call: $monitor\n  $monitor(" INPUT = %b  MIN_POSITION = %d", bit_detect, bit_position);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/named_block_disable.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #1 bit_detect = 32\'h1000_1000;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/named_block_disable.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #1 bit_detect = 32\'h1100_0000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/named_block_disable.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #1 bit_detect = 32\'h1000_1010;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/named_block_disable.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #10 $finish;\n  ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module named_block_disable();

reg [31:0] bit_detect;
reg [5:0]  bit_position;
integer i;

always @ (bit_detect)
begin : BIT_DETECT
  for (i = 0; i < 32 ; i = i + 1) begin


     if (bit_detect[i] == 1) begin
        bit_position = i;
        disable BIT_DETECT;
     end  else begin
        bit_position = 32;
     end
  end
end


initial begin
  $monitor(" INPUT = %b  MIN_POSITION = %d", bit_detect, bit_position);
  #1 bit_detect = 32'h1000_1000;
  #1 bit_detect = 32'h1100_0000;
  #1 bit_detect = 32'h1000_1010;
  #10 $finish;
end

endmodule
module named_block_disable();


reg [31:0] bit_detect;
reg [5:0]  bit_position;
integer i;

always @ (bit_detect)
begin : BIT_DETECT
  for (i = 0; i < 32 ; i = i + 1) begin


     if (bit_detect[i] == 1) begin
        bit_position = i;
        disable BIT_DETECT;
     end  else begin
        bit_position = 32;
     end
  end
end


initial begin
  $monitor(" INPUT = %b  MIN_POSITION = %d", bit_detect, bit_position);
  #1 bit_detect = 32'h1000_1000;
  #1 bit_detect = 32'h1100_0000;
  #1 bit_detect = 32'h1000_1010;
  #10 $finish;
end

endmodule