data/full_repos/permissive/437157208/src/Wrapper_MIPS.v
1: b"%Error: data/full_repos/permissive/437157208/src/Wrapper_MIPS.v:10: Cannot find file containing module: 'PLL'\nPLL PLL_inst (.inclk0( MAX10_CLK1_50 ), .c0(clk));\n^~~\n        ... Looked in:\n             data/full_repos/permissive/437157208/src,data/full_repos/permissive/437157208/PLL\n             data/full_repos/permissive/437157208/src,data/full_repos/permissive/437157208/PLL.v\n             data/full_repos/permissive/437157208/src,data/full_repos/permissive/437157208/PLL.sv\n             PLL\n             PLL.v\n             PLL.sv\n             obj_dir/PLL\n             obj_dir/PLL.v\n             obj_dir/PLL.sv\n%Error: data/full_repos/permissive/437157208/src/Wrapper_MIPS.v:12: Cannot find file containing module: 'cont_1s_RCO'\ncont_1s_RCO Clock(.mclk(clk), .reset(SW), .RCO(clk_hz));\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/437157208/src/Wrapper_MIPS.v:14: Cannot find file containing module: 'Data_Path'\nData_Path MIPS(.clk(clk_hz), .reset(SW), .GPIO_o(LEDR));\n^~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module Wrapper_MIPS
(
	input MAX10_CLK1_50,
	input [9:9] SW,
	output [7:0] LEDR
);

wire clk, clk_hz;

PLL	PLL_inst (.inclk0( MAX10_CLK1_50 ), .c0(clk));

cont_1s_RCO Clock(.mclk(clk), .reset(SW), .RCO(clk_hz));

Data_Path MIPS(.clk(clk_hz), .reset(SW), .GPIO_o(LEDR));


endmodule
module Wrapper_MIPS
(
	input MAX10_CLK1_50,
	input [9:9] SW,
	output [7:0] LEDR
);


wire clk, clk_hz;

PLL	PLL_inst (.inclk0( MAX10_CLK1_50 ), .c0(clk));

cont_1s_RCO Clock(.mclk(clk), .reset(SW), .RCO(clk_hz));

Data_Path MIPS(.clk(clk_hz), .reset(SW), .GPIO_o(LEDR));


endmodule