data/full_repos/permissive/491135068/equalityModule.v
data/verilator_xmls/bb9fccea-da09-4a60-8580-55991b3fcad1.xml
module equalityModule(
    input [31:0] AvalIn, BvalIn,
    output reg [31:0] AvalOut, BvalOut,
    input eq, eqType, clk,
    output reg eqResult
    );
    
    always@(AvalIn, BvalIn, clk, eq, eqType) begin
        if(eq == 1'b1)
            case(eqType)
                1'b0: begin
                    if(AvalIn == BvalIn)
                        eqResult = 1'b1;
                end
                1'b1: begin
                    if(AvalIn != BvalIn)
                        eqResult = 1'b1;
                end
            endcase
        else begin
            AvalOut = AvalIn;
            BvalOut = BvalIn;
            eqResult = 1'b0;
        end    
    end
    
    
endmodule
module equalityModule(
    input [31:0] AvalIn, BvalIn,
    output reg [31:0] AvalOut, BvalOut,
    input eq, eqType, clk,
    output reg eqResult
    );

    
    always@(AvalIn, BvalIn, clk, eq, eqType) begin
        if(eq == 1'b1)
            case(eqType)
                1'b0: begin
                    if(AvalIn == BvalIn)
                        eqResult = 1'b1;
                end
                1'b1: begin
                    if(AvalIn != BvalIn)
                        eqResult = 1'b1;
                end
            endcase
        else begin
            AvalOut = AvalIn;
            BvalOut = BvalIn;
            eqResult = 1'b0;
        end    
    end
    
    
endmodule