data/full_repos/permissive/515598112/3_Circuits/02_Sequential_Logic/01_Latches_and_Flip-Flops/07_D_Latch.v
data/verilator_xmls/61d88d5b-8dd3-4ee2-9f14-8598670049a5.xml
module top_module (
    input d, 
    input ena,
    output reg q
);
    
    always @(ena) begin
        q <= ena ? d : q;
    end

endmodule
module top_module (
    input d, 
    input ena,
    output reg q
);

    
    always @(ena) begin
        q <= ena ? d : q;
    end

endmodule