data/full_repos/permissive/452305748/L7/tir_gen/tri_gen.v
data/verilator_xmls/427c1b29-e5a3-44cb-9c2e-cd4b74973530.xml
module tri_gen (input wire clk,
                input wire rstn,
                output reg[8:0] d_out);
    reg[1:0] state;
    reg[7:0] con;
    
    always @(posedge clk or negedge rstn) begin
        if (~rstn) begin
            state <= 0;
            d_out <= 0;
            con   <= 0;
        end
        else begin
            case (state)
                0 : begin
                    d_out <= d_out+1;
                    if (d_out == 299) begin
                        state <= 1;
                    end
                end
                1 : begin
                    if (con == 200) begin
                        con   <= 0;
                        state <= 2;
                    end
                    else begin
                        con <= con + 1;
                    end
                end
                2 : begin
                    d_out <= d_out-1;
                    if (d_out == 1) begin
                        state <= 3;
                    end
                end
                3 : begin
                     if (con == 200) begin
                        con   <= 0;
                        state <= 0;
                    end
                    else begin
                        con <= con + 1;
                    end
                end
            endcase
        end
    end
endmodule
module tri_gen (input wire clk,
                input wire rstn,
                output reg[8:0] d_out);

    reg[1:0] state;
    reg[7:0] con;
    
    always @(posedge clk or negedge rstn) begin
        if (~rstn) begin
            state <= 0;
            d_out <= 0;
            con   <= 0;
        end
        else begin
            case (state)
                0 : begin
                    d_out <= d_out+1;
                    if (d_out == 299) begin
                        state <= 1;
                    end
                end
                1 : begin
                    if (con == 200) begin
                        con   <= 0;
                        state <= 2;
                    end
                    else begin
                        con <= con + 1;
                    end
                end
                2 : begin
                    d_out <= d_out-1;
                    if (d_out == 1) begin
                        state <= 3;
                    end
                end
                3 : begin
                     if (con == 200) begin
                        con   <= 0;
                        state <= 0;
                    end
                    else begin
                        con <= con + 1;
                    end
                end
            endcase
        end
    end
endmodule