data/full_repos/permissive/460468583/data/yosys/nexus/cells_sim.v
1: b'%Error: data/full_repos/permissive/460468583/data/yosys/nexus/cells_sim.v:4: Cannot find include file: parse_init.vh\n`include "parse_init.vh" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/460468583/data/yosys/nexus,data/full_repos/permissive/460468583/parse_init.vh\n             data/full_repos/permissive/460468583/data/yosys/nexus,data/full_repos/permissive/460468583/parse_init.vh.v\n             data/full_repos/permissive/460468583/data/yosys/nexus,data/full_repos/permissive/460468583/parse_init.vh.sv\n             parse_init.vh\n             parse_init.vh.v\n             parse_init.vh.sv\n             obj_dir/parse_init.vh\n             obj_dir/parse_init.vh.v\n             obj_dir/parse_init.vh.sv\n%Error: data/full_repos/permissive/460468583/data/yosys/nexus/cells_sim.v:182: Cannot find include file: parse_init.vh\n`include "parse_init.vh" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/nexus/cells_sim.v:365: Cannot find include file: parse_init.vh\n`include "parse_init.vh" \n         ^~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module WIDEFN9(input A0, B0, C0, D0, A1, B1, C1, D1, SEL, output Z);
	parameter INIT0 = "0x0000";
	parameter INIT1 = "0x0000";
	wire z0, z1;
	LUT4 #(.INIT(INIT0)) lut4_0 (.A(A0), .B(B0), .C(C0), .D(D0), .Z(z0));
	LUT4 #(.INIT(INIT1)) lut4_1 (.A(A1), .B(B1), .C(C1), .D(D1), .Z(z1));
	assign Z = SEL ? z1 : z0;
endmodule
module WIDEFN9(input A0, B0, C0, D0, A1, B1, C1, D1, SEL, output Z);

	parameter INIT0 = "0x0000";
	parameter INIT1 = "0x0000";
	wire z0, z1;
	LUT4 #(.INIT(INIT0)) lut4_0 (.A(A0), .B(B0), .C(C0), .D(D0), .Z(z0));
	LUT4 #(.INIT(INIT1)) lut4_1 (.A(A1), .B(B1), .C(C1), .D(D1), .Z(z1));
	assign Z = SEL ? z1 : z0;
endmodule