data/full_repos/permissive/423539813/source_files/alu.v
data/verilator_xmls/49f0f1a2-63c8-4d51-aacb-a118f79c39f4.xml
module alu(
           input [31:0] A,B,
           input [3:0] ALU_Sel,
           output [31:0] ALU_Out,
           output CarryOut,
		   output ZeroOut
    );
    reg [31:0] ALU_Result;
    wire [31:0] tmp;
    assign ALU_Out = ALU_Result;
    assign tmp = A - B;
    assign CarryOut = tmp[31];
	assign ZeroOut = ( ALU_Result == 0);
    always @(*)
    begin
        case(ALU_Sel)
        4'b0000:
           ALU_Result = A + B ;
        4'b0001:
           ALU_Result = A - B ;
        4'b0010:
           ALU_Result = A * B;
        4'b0011:
           ALU_Result = A/B;
        4'b0100:
           ALU_Result = A<<B;
         4'b0101:
           ALU_Result = A>>B;
         4'b0110:
           ALU_Result = {A[30:0],A[31]};
         4'b0111:
           ALU_Result = {A[0],A[31:1]};
          4'b1000:
           ALU_Result = A & B;
          4'b1001:
           ALU_Result = A | B;
          4'b1010:
           ALU_Result = A ^ B;
          4'b1011:
           ALU_Result = ~(A | B);
          4'b1100:
           ALU_Result = ~(A & B);
          4'b1101:
           ALU_Result = ~(A ^ B);
          4'b1110:
           ALU_Result = (A<B)?32'd0:32'd1 ;
          4'b1111:
            ALU_Result = (A==B)?32'd1:32'd0 ;
          default: ALU_Result = A + B ;
        endcase
    end

endmodule
module alu(
           input [31:0] A,B,
           input [3:0] ALU_Sel,
           output [31:0] ALU_Out,
           output CarryOut,
		   output ZeroOut
    );

    reg [31:0] ALU_Result;
    wire [31:0] tmp;
    assign ALU_Out = ALU_Result;
    assign tmp = A - B;
    assign CarryOut = tmp[31];
	assign ZeroOut = ( ALU_Result == 0);
    always @(*)
    begin
        case(ALU_Sel)
        4'b0000:
           ALU_Result = A + B ;
        4'b0001:
           ALU_Result = A - B ;
        4'b0010:
           ALU_Result = A * B;
        4'b0011:
           ALU_Result = A/B;
        4'b0100:
           ALU_Result = A<<B;
         4'b0101:
           ALU_Result = A>>B;
         4'b0110:
           ALU_Result = {A[30:0],A[31]};
         4'b0111:
           ALU_Result = {A[0],A[31:1]};
          4'b1000:
           ALU_Result = A & B;
          4'b1001:
           ALU_Result = A | B;
          4'b1010:
           ALU_Result = A ^ B;
          4'b1011:
           ALU_Result = ~(A | B);
          4'b1100:
           ALU_Result = ~(A & B);
          4'b1101:
           ALU_Result = ~(A ^ B);
          4'b1110:
           ALU_Result = (A<B)?32'd0:32'd1 ;
          4'b1111:
            ALU_Result = (A==B)?32'd1:32'd0 ;
          default: ALU_Result = A + B ;
        endcase
    end

endmodule