data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/dsa_control.v
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/dsa_control.v:73: Cannot find include file: ../regmap/dsa_setup_regmap_utils.vh\n  `include "../regmap/dsa_setup_regmap_utils.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints,data/full_repos/permissive/447976230/../regmap/dsa_setup_regmap_utils.vh\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints,data/full_repos/permissive/447976230/../regmap/dsa_setup_regmap_utils.vh.v\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints,data/full_repos/permissive/447976230/../regmap/dsa_setup_regmap_utils.vh.sv\n             ../regmap/dsa_setup_regmap_utils.vh\n             ../regmap/dsa_setup_regmap_utils.vh.v\n             ../regmap/dsa_setup_regmap_utils.vh.sv\n             obj_dir/../regmap/dsa_setup_regmap_utils.vh\n             obj_dir/../regmap/dsa_setup_regmap_utils.vh.v\n             obj_dir/../regmap/dsa_setup_regmap_utils.vh.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/dsa_control.v:74: Cannot find include file: ../../../../../../lib/rfnoc/core/ctrlport.vh\n  `include "../../../../../../lib/rfnoc/core/ctrlport.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module dsa_control #(
  parameter [19:0]  BASE_ADDRESS = 0,
  parameter [19:0]  SIZE_ADDRESS = 0
) (

  input  wire        ctrlport_clk,
  input  wire        ctrlport_rst,


  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [31:0] s_ctrlport_req_data,


  output reg         s_ctrlport_resp_ack,
  output reg  [ 1:0] s_ctrlport_resp_status = 2'b0,
  output reg  [31:0] s_ctrlport_resp_data = 32'b0,


  input  wire [ 7:0] atr_config_rf0,
  input  wire [ 7:0] atr_config_rf1,







  output wire [6:2] tx0_dsa1,
  output wire [6:2] tx0_dsa2,


  output wire [6:2] tx1_dsa1,
  output wire [6:2] tx1_dsa2,







  output wire [1:4] rx0_dsa1_n,
  output wire [1:4] rx0_dsa2_n,
  output wire [1:4] rx0_dsa3_a_n,
  output wire [1:4] rx0_dsa3_b_n,


  output wire [1:4] rx1_dsa1_n,
  output wire [1:4] rx1_dsa2_n,
  output wire [1:4] rx1_dsa3_a_n,
  output wire [1:4] rx1_dsa3_b_n
);

  `include "../regmap/dsa_setup_regmap_utils.vh"
  `include "../../../../../../lib/rfnoc/core/ctrlport.vh"




  reg [TX_DSA1_SIZE -1:0]   tx0_dsa_1_reg   = {TX_DSA1_SIZE{1'b1}};
  reg [TX_DSA2_SIZE -1:0]   tx0_dsa_2_reg   = {TX_DSA2_SIZE{1'b1}};

  reg [TX_DSA1_SIZE -1:0]   tx1_dsa_1_reg   = {TX_DSA1_SIZE{1'b1}};
  reg [TX_DSA2_SIZE -1:0]   tx1_dsa_2_reg   = {TX_DSA2_SIZE{1'b1}};

  reg [RX_DSA1_SIZE -1:0]   rx0_dsa_1_reg   = {RX_DSA1_SIZE{1'b1}};
  reg [RX_DSA2_SIZE -1:0]   rx0_dsa_2_reg   = {RX_DSA2_SIZE{1'b1}};
  reg [RX_DSA3_A_SIZE -1:0] rx0_dsa_3_a_reg = {RX_DSA3_A_SIZE{1'b1}};
  reg [RX_DSA3_B_SIZE -1:0] rx0_dsa_3_b_reg = {RX_DSA3_B_SIZE{1'b1}};

  reg [RX_DSA1_SIZE -1:0]   rx1_dsa_1_reg   = {RX_DSA1_SIZE{1'b1}};
  reg [RX_DSA2_SIZE -1:0]   rx1_dsa_2_reg   = {RX_DSA2_SIZE{1'b1}};
  reg [RX_DSA3_A_SIZE -1:0] rx1_dsa_3_a_reg = {RX_DSA3_A_SIZE{1'b1}};
  reg [RX_DSA3_B_SIZE -1:0] rx1_dsa_3_b_reg = {RX_DSA3_B_SIZE{1'b1}};




  reg         ram_tx0_wea = 1'b0;
  wire [31:0] ram_tx0_doa;
  wire [31:0] ram_tx0_dob;
  reg         ram_tx1_wea = 1'b0;
  wire [31:0] ram_tx1_doa;
  wire [31:0] ram_tx1_dob;
  reg         ram_rx0_wea = 1'b0;
  wire [31:0] ram_rx0_doa;
  wire [31:0] ram_rx0_dob;
  reg         ram_rx1_wea = 1'b0;
  wire [31:0] ram_rx1_doa;
  wire [31:0] ram_rx1_dob;

  reg         table_tx0_wea = 1'b0;
  wire [31:0] table_tx0_doa;
  reg         table_tx1_wea = 1'b0;
  wire [31:0] table_tx1_doa;
  reg         table_rx0_wea = 1'b0;
  wire [31:0] table_rx0_doa;
  reg         table_rx1_wea = 1'b0;
  wire [31:0] table_rx1_doa;





  wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + SIZE_ADDRESS);

  reg  [ 1:0] read_req_shift_reg = 2'b0;


  reg  [ 1:0] write_req_shift_reg = 2'b0;


  wire [31:0] register_base_address = {s_ctrlport_req_addr[19:10], 8'b0, s_ctrlport_req_addr[1:0]};


  wire [ 7:0] register_index = s_ctrlport_req_addr[9:2];

  reg select_gain_table = 1'b0;

  always @(posedge ctrlport_clk) begin

    if (ctrlport_rst) begin
      s_ctrlport_resp_ack <= 1'b0;

      read_req_shift_reg  <= 2'b0;
      write_req_shift_reg <= 2'b0;

      ram_tx0_wea <= 1'b0;
      ram_tx1_wea <= 1'b0;
      ram_rx0_wea <= 1'b0;
      ram_rx1_wea <= 1'b0;

      table_tx0_wea <= 1'b0;
      table_tx1_wea <= 1'b0;
      table_rx0_wea <= 1'b0;
      table_rx1_wea <= 1'b0;

      select_gain_table <= 1'b0;

    end else begin

      read_req_shift_reg  <= { read_req_shift_reg[0], s_ctrlport_req_rd};
      write_req_shift_reg <= {write_req_shift_reg[0], s_ctrlport_req_wr};

      ram_tx0_wea <= 1'b0;
      ram_tx1_wea <= 1'b0;
      ram_rx0_wea <= 1'b0;
      ram_rx1_wea <= 1'b0;

      table_tx0_wea <= 1'b0;
      table_tx1_wea <= 1'b0;
      table_rx0_wea <= 1'b0;
      table_rx1_wea <= 1'b0;

      select_gain_table <= 1'b0;




      if (write_req_shift_reg[1]) begin

        s_ctrlport_resp_ack     <= 1'b1;
        s_ctrlport_resp_data    <= {32{1'bx}};
        s_ctrlport_resp_status  <= CTRL_STS_OKAY;

        case (register_base_address)
          BASE_ADDRESS + TX0_DSA_ATR(0): begin
            ram_tx0_wea <= 1'b1;
          end
          BASE_ADDRESS + TX1_DSA_ATR(0): begin
            ram_tx1_wea <= 1'b1;
          end
          BASE_ADDRESS + RX0_DSA_ATR(0): begin
            ram_rx0_wea <= 1'b1;
          end
          BASE_ADDRESS + RX1_DSA_ATR(0): begin
            ram_rx1_wea <= 1'b1;
          end

          BASE_ADDRESS + TX0_DSA_TABLE(0): begin
            table_tx0_wea <= 1'b1;
          end
          BASE_ADDRESS + TX1_DSA_TABLE(0): begin
            table_tx1_wea <= 1'b1;
          end
          BASE_ADDRESS + RX0_DSA_TABLE(0): begin
            table_rx0_wea <= 1'b1;
          end
          BASE_ADDRESS + RX1_DSA_TABLE(0): begin
            table_rx1_wea <= 1'b1;
          end

          BASE_ADDRESS + TX0_DSA_TABLE_SELECT(0): begin
            ram_tx0_wea       <= 1'b1;
            select_gain_table <= 1'b1;
          end
          BASE_ADDRESS + TX1_DSA_TABLE_SELECT(0): begin
            ram_tx1_wea       <= 1'b1;
            select_gain_table <= 1'b1;
          end
          BASE_ADDRESS + RX0_DSA_TABLE_SELECT(0): begin
            ram_rx0_wea       <= 1'b1;
            select_gain_table <= 1'b1;
          end
          BASE_ADDRESS + RX1_DSA_TABLE_SELECT(0): begin
            ram_rx1_wea       <= 1'b1;
            select_gain_table <= 1'b1;
          end


          default: begin
            if (address_in_range) begin
              s_ctrlport_resp_status <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack <= 1'b0;
            end
          end
        endcase




      end else if (read_req_shift_reg[1]) begin

        s_ctrlport_resp_ack     <= 1'b1;
        s_ctrlport_resp_status  <= CTRL_STS_OKAY;
        s_ctrlport_resp_data    <= {32{1'b0}};

        case (register_base_address)
          BASE_ADDRESS + TX0_DSA_ATR(0): begin
            s_ctrlport_resp_data <= ram_tx0_doa & TX_DSA_CONTROL_MASK;
          end
          BASE_ADDRESS + TX1_DSA_ATR(0): begin
            s_ctrlport_resp_data <= ram_tx1_doa & TX_DSA_CONTROL_MASK;
          end
          BASE_ADDRESS + RX0_DSA_ATR(0): begin
            s_ctrlport_resp_data <= ram_rx0_doa & RX_DSA_CONTROL_MASK;
          end
          BASE_ADDRESS + RX1_DSA_ATR(0): begin
            s_ctrlport_resp_data <= ram_rx1_doa & RX_DSA_CONTROL_MASK;
          end
          BASE_ADDRESS + TX0_DSA_TABLE(0): begin
            s_ctrlport_resp_data <= table_tx0_doa & TX_DSA_CONTROL_MASK;
          end
          BASE_ADDRESS + TX1_DSA_TABLE(0): begin
            s_ctrlport_resp_data <= table_tx1_doa & TX_DSA_CONTROL_MASK;
          end
          BASE_ADDRESS + RX0_DSA_TABLE(0): begin
            s_ctrlport_resp_data <= table_rx0_doa & RX_DSA_CONTROL_MASK;
          end
          BASE_ADDRESS + RX1_DSA_TABLE(0): begin
            s_ctrlport_resp_data <= table_rx1_doa & RX_DSA_CONTROL_MASK;
          end

          default: begin
            if (address_in_range) begin
              s_ctrlport_resp_status <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack <= 1'b0;
            end
          end
        endcase


      end else begin
        s_ctrlport_resp_ack <= 1'b0;
      end
    end
  end


  reg [ 7:0] ram_addr        =  8'b0;
  reg [ 7:0] gain_table_addr =  8'b0;
  reg [31:0] ram_datain      = 32'b0;
  always @(posedge ctrlport_clk) begin


    if (s_ctrlport_req_wr || s_ctrlport_req_rd) begin
      ram_addr        <= register_index;
      ram_datain      <= s_ctrlport_req_data;

      case (register_base_address)
        BASE_ADDRESS + TX0_DSA_TABLE_SELECT(0),
        BASE_ADDRESS + TX1_DSA_TABLE_SELECT(0),
        BASE_ADDRESS + RX0_DSA_TABLE_SELECT(0),
        BASE_ADDRESS + RX1_DSA_TABLE_SELECT(0): begin
          gain_table_addr <= s_ctrlport_req_data[TABLE_INDEX_MSB:TABLE_INDEX];
        end
        default: begin
          gain_table_addr <= register_index;
        end
      endcase
    end


    tx0_dsa_1_reg   <= ram_tx0_dob[  TX_DSA1_MSB :   TX_DSA1];
    tx0_dsa_2_reg   <= ram_tx0_dob[  TX_DSA2_MSB :   TX_DSA2];

    tx1_dsa_1_reg   <= ram_tx1_dob[  TX_DSA1_MSB :   TX_DSA1];
    tx1_dsa_2_reg   <= ram_tx1_dob[  TX_DSA2_MSB :   TX_DSA2];

    rx0_dsa_1_reg   <= ram_rx0_dob[  RX_DSA1_MSB :   RX_DSA1];
    rx0_dsa_2_reg   <= ram_rx0_dob[  RX_DSA2_MSB :   RX_DSA2];
    rx0_dsa_3_a_reg <= ram_rx0_dob[RX_DSA3_A_MSB : RX_DSA3_A];
    rx0_dsa_3_b_reg <= ram_rx0_dob[RX_DSA3_B_MSB : RX_DSA3_B];

    rx1_dsa_1_reg   <= ram_rx1_dob[  RX_DSA1_MSB :   RX_DSA1];
    rx1_dsa_2_reg   <= ram_rx1_dob[  RX_DSA2_MSB :   RX_DSA2];
    rx1_dsa_3_a_reg <= ram_rx1_dob[RX_DSA3_A_MSB : RX_DSA3_A];
    rx1_dsa_3_b_reg <= ram_rx1_dob[RX_DSA3_B_MSB : RX_DSA3_B];
  end

  assign tx0_dsa1[6:2] = tx0_dsa_1_reg;
  assign tx0_dsa2[6:2] = tx0_dsa_2_reg;

  assign tx1_dsa1[6:2] = tx1_dsa_1_reg;
  assign tx1_dsa2[6:2] = tx1_dsa_2_reg;




  genvar vi;


  generate
    for (vi=1; vi<=4; vi=vi+1) begin : reverselogic

      assign rx0_dsa1_n[vi]    = !rx0_dsa_1_reg[4-vi];
      assign rx0_dsa2_n[vi]    = !rx0_dsa_2_reg[4-vi];
      assign rx0_dsa3_a_n[vi]  = !rx0_dsa_3_a_reg[4-vi];
      assign rx0_dsa3_b_n[vi]  = !rx0_dsa_3_b_reg[4-vi];

      assign rx1_dsa1_n[vi]    = !rx1_dsa_1_reg[4-vi];
      assign rx1_dsa2_n[vi]    = !rx1_dsa_2_reg[4-vi];
      assign rx1_dsa3_a_n[vi]  = !rx1_dsa_3_a_reg[4-vi];
      assign rx1_dsa3_b_n[vi]  = !rx1_dsa_3_b_reg[4-vi];
    end
  endgenerate





  wire [31:0] ram_rx0_dia = select_gain_table ? table_rx0_doa : ram_datain;
  wire [31:0] ram_rx1_dia = select_gain_table ? table_rx1_doa : ram_datain;
  wire [31:0] ram_tx0_dia = select_gain_table ? table_tx0_doa : ram_datain;
  wire [31:0] ram_tx1_dia = select_gain_table ? table_tx1_doa : ram_datain;

  ram_2port #(
    .DWIDTH     (32),
    .AWIDTH     (8),
    .RW_MODE    ("READ-FIRST"),
    .RAM_TYPE   ("AUTOMATIC"),
    .OUT_REG    (0),
    .INIT_FILE  ("register_endpoints/memory_init_files/tx_dsa_defaults.hex")
  ) ram_tx0_i (
    .clka   (ctrlport_clk),
    .ena    (1'b1),
    .wea    (ram_tx0_wea),
    .addra  (ram_addr),
    .dia    (ram_tx0_dia),
    .doa    (ram_tx0_doa),
    .clkb   (ctrlport_clk),
    .enb    (1'b1),
    .web    (1'b0),
    .addrb  (atr_config_rf0),
    .dib    (0),
    .dob    (ram_tx0_dob)
  );

  ram_2port #(
    .DWIDTH     (32),
    .AWIDTH     (8),
    .RW_MODE    ("READ-FIRST"),
    .RAM_TYPE   ("AUTOMATIC"),
    .OUT_REG    (0),
    .INIT_FILE  ("register_endpoints/memory_init_files/tx_dsa_defaults.hex")
  ) ram_tx1_i (
    .clka   (ctrlport_clk),
    .ena    (1'b1),
    .wea    (ram_tx1_wea),
    .addra  (ram_addr),
    .dia    (ram_tx1_dia),
    .doa    (ram_tx1_doa),
    .clkb   (ctrlport_clk),
    .enb    (1'b1),
    .web    (1'b0),
    .addrb  (atr_config_rf1),
    .dib    (0),
    .dob    (ram_tx1_dob)
  );

  ram_2port #(
    .DWIDTH     (32),
    .AWIDTH     (8),
    .RW_MODE    ("READ-FIRST"),
    .RAM_TYPE   ("AUTOMATIC"),
    .OUT_REG    (0),
    .INIT_FILE  ("register_endpoints/memory_init_files/rx_dsa_defaults.hex")
  ) ram_rx0_i (
    .clka   (ctrlport_clk),
    .ena    (1'b1),
    .wea    (ram_rx0_wea),
    .addra  (ram_addr),
    .dia    (ram_rx0_dia),
    .doa    (ram_rx0_doa),
    .clkb   (ctrlport_clk),
    .enb    (1'b1),
    .web    (1'b0),
    .addrb  (atr_config_rf0),
    .dib    (0),
    .dob    (ram_rx0_dob)
  );

  ram_2port #(
    .DWIDTH     (32),
    .AWIDTH     (8),
    .RW_MODE    ("READ-FIRST"),
    .RAM_TYPE   ("AUTOMATIC"),
    .OUT_REG    (0),
    .INIT_FILE  ("register_endpoints/memory_init_files/rx_dsa_defaults.hex")
  ) ram_rx1_i (
    .clka   (ctrlport_clk),
    .ena    (1'b1),
    .wea    (ram_rx1_wea),
    .addra  (ram_addr),
    .dia    (ram_rx1_dia),
    .doa    (ram_rx1_doa),
    .clkb   (ctrlport_clk),
    .enb    (1'b1),
    .web    (1'b0),
    .addrb  (atr_config_rf1),
    .dib    (0),
    .dob    (ram_rx1_dob)
  );





  ram_2port #(
    .DWIDTH     (32),
    .AWIDTH     (8),
    .RW_MODE    ("READ-FIRST"),
    .RAM_TYPE   ("AUTOMATIC"),
    .OUT_REG    (0),
    .INIT_FILE  ("register_endpoints/memory_init_files/tx_dsa_defaults.hex")
  ) table_tx0_i (
    .clka   (ctrlport_clk),
    .ena    (1'b1),
    .wea    (table_tx0_wea),
    .addra  (gain_table_addr),
    .dia    (ram_datain),
    .doa    (table_tx0_doa),
    .clkb   (ctrlport_clk),
    .enb    (1'b1),
    .web    (1'b0),
    .addrb  (8'b0),
    .dib    (32'b0),
    .dob    ()
  );

  ram_2port #(
    .DWIDTH     (32),
    .AWIDTH     (8),
    .RW_MODE    ("READ-FIRST"),
    .RAM_TYPE   ("AUTOMATIC"),
    .OUT_REG    (0),
    .INIT_FILE  ("register_endpoints/memory_init_files/tx_dsa_defaults.hex")
  ) table_tx1_i (
    .clka   (ctrlport_clk),
    .ena    (1'b1),
    .wea    (table_tx1_wea),
    .addra  (gain_table_addr),
    .dia    (ram_datain),
    .doa    (table_tx1_doa),
    .clkb   (ctrlport_clk),
    .enb    (1'b1),
    .web    (1'b0),
    .addrb  (8'b0),
    .dib    (32'b0),
    .dob    ()
  );

  ram_2port #(
    .DWIDTH     (32),
    .AWIDTH     (8),
    .RW_MODE    ("READ-FIRST"),
    .RAM_TYPE   ("AUTOMATIC"),
    .OUT_REG    (0),
    .INIT_FILE  ("register_endpoints/memory_init_files/rx_dsa_defaults.hex")
  ) table_rx0_i (
    .clka   (ctrlport_clk),
    .ena    (1'b1),
    .wea    (table_rx0_wea),
    .addra  (gain_table_addr),
    .dia    (ram_datain),
    .doa    (table_rx0_doa),
    .clkb   (ctrlport_clk),
    .enb    (1'b1),
    .web    (1'b0),
    .addrb  (8'b0),
    .dib    (32'b0),
    .dob    ()
  );

  ram_2port #(
    .DWIDTH     (32),
    .AWIDTH     (8),
    .RW_MODE    ("READ-FIRST"),
    .RAM_TYPE   ("AUTOMATIC"),
    .OUT_REG    (0),
    .INIT_FILE  ("register_endpoints/memory_init_files/rx_dsa_defaults.hex")
  ) table_rx1_i (
    .clka   (ctrlport_clk),
    .ena    (1'b1),
    .wea    (table_rx1_wea),
    .addra  (gain_table_addr),
    .dia    (ram_datain),
    .doa    (table_rx1_doa),
    .clkb   (ctrlport_clk),
    .enb    (1'b1),
    .web    (1'b0),
    .addrb  (8'b0),
    .dib    (32'b0),
    .dob    ()
  );

endmodule
module dsa_control #(
  parameter [19:0]  BASE_ADDRESS = 0,
  parameter [19:0]  SIZE_ADDRESS = 0
) (

  input  wire        ctrlport_clk,
  input  wire        ctrlport_rst,


  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [31:0] s_ctrlport_req_data,


  output reg         s_ctrlport_resp_ack,
  output reg  [ 1:0] s_ctrlport_resp_status = 2'b0,
  output reg  [31:0] s_ctrlport_resp_data = 32'b0,


  input  wire [ 7:0] atr_config_rf0,
  input  wire [ 7:0] atr_config_rf1,







  output wire [6:2] tx0_dsa1,
  output wire [6:2] tx0_dsa2,


  output wire [6:2] tx1_dsa1,
  output wire [6:2] tx1_dsa2,







  output wire [1:4] rx0_dsa1_n,
  output wire [1:4] rx0_dsa2_n,
  output wire [1:4] rx0_dsa3_a_n,
  output wire [1:4] rx0_dsa3_b_n,


  output wire [1:4] rx1_dsa1_n,
  output wire [1:4] rx1_dsa2_n,
  output wire [1:4] rx1_dsa3_a_n,
  output wire [1:4] rx1_dsa3_b_n
);


  `include "../regmap/dsa_setup_regmap_utils.vh"
  `include "../../../../../../lib/rfnoc/core/ctrlport.vh"




  reg [TX_DSA1_SIZE -1:0]   tx0_dsa_1_reg   = {TX_DSA1_SIZE{1'b1}};
  reg [TX_DSA2_SIZE -1:0]   tx0_dsa_2_reg   = {TX_DSA2_SIZE{1'b1}};

  reg [TX_DSA1_SIZE -1:0]   tx1_dsa_1_reg   = {TX_DSA1_SIZE{1'b1}};
  reg [TX_DSA2_SIZE -1:0]   tx1_dsa_2_reg   = {TX_DSA2_SIZE{1'b1}};

  reg [RX_DSA1_SIZE -1:0]   rx0_dsa_1_reg   = {RX_DSA1_SIZE{1'b1}};
  reg [RX_DSA2_SIZE -1:0]   rx0_dsa_2_reg   = {RX_DSA2_SIZE{1'b1}};
  reg [RX_DSA3_A_SIZE -1:0] rx0_dsa_3_a_reg = {RX_DSA3_A_SIZE{1'b1}};
  reg [RX_DSA3_B_SIZE -1:0] rx0_dsa_3_b_reg = {RX_DSA3_B_SIZE{1'b1}};

  reg [RX_DSA1_SIZE -1:0]   rx1_dsa_1_reg   = {RX_DSA1_SIZE{1'b1}};
  reg [RX_DSA2_SIZE -1:0]   rx1_dsa_2_reg   = {RX_DSA2_SIZE{1'b1}};
  reg [RX_DSA3_A_SIZE -1:0] rx1_dsa_3_a_reg = {RX_DSA3_A_SIZE{1'b1}};
  reg [RX_DSA3_B_SIZE -1:0] rx1_dsa_3_b_reg = {RX_DSA3_B_SIZE{1'b1}};




  reg         ram_tx0_wea = 1'b0;
  wire [31:0] ram_tx0_doa;
  wire [31:0] ram_tx0_dob;
  reg         ram_tx1_wea = 1'b0;
  wire [31:0] ram_tx1_doa;
  wire [31:0] ram_tx1_dob;
  reg         ram_rx0_wea = 1'b0;
  wire [31:0] ram_rx0_doa;
  wire [31:0] ram_rx0_dob;
  reg         ram_rx1_wea = 1'b0;
  wire [31:0] ram_rx1_doa;
  wire [31:0] ram_rx1_dob;

  reg         table_tx0_wea = 1'b0;
  wire [31:0] table_tx0_doa;
  reg         table_tx1_wea = 1'b0;
  wire [31:0] table_tx1_doa;
  reg         table_rx0_wea = 1'b0;
  wire [31:0] table_rx0_doa;
  reg         table_rx1_wea = 1'b0;
  wire [31:0] table_rx1_doa;





  wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + SIZE_ADDRESS);

  reg  [ 1:0] read_req_shift_reg = 2'b0;


  reg  [ 1:0] write_req_shift_reg = 2'b0;


  wire [31:0] register_base_address = {s_ctrlport_req_addr[19:10], 8'b0, s_ctrlport_req_addr[1:0]};


  wire [ 7:0] register_index = s_ctrlport_req_addr[9:2];

  reg select_gain_table = 1'b0;

  always @(posedge ctrlport_clk) begin

    if (ctrlport_rst) begin
      s_ctrlport_resp_ack <= 1'b0;

      read_req_shift_reg  <= 2'b0;
      write_req_shift_reg <= 2'b0;

      ram_tx0_wea <= 1'b0;
      ram_tx1_wea <= 1'b0;
      ram_rx0_wea <= 1'b0;
      ram_rx1_wea <= 1'b0;

      table_tx0_wea <= 1'b0;
      table_tx1_wea <= 1'b0;
      table_rx0_wea <= 1'b0;
      table_rx1_wea <= 1'b0;

      select_gain_table <= 1'b0;

    end else begin

      read_req_shift_reg  <= { read_req_shift_reg[0], s_ctrlport_req_rd};
      write_req_shift_reg <= {write_req_shift_reg[0], s_ctrlport_req_wr};

      ram_tx0_wea <= 1'b0;
      ram_tx1_wea <= 1'b0;
      ram_rx0_wea <= 1'b0;
      ram_rx1_wea <= 1'b0;

      table_tx0_wea <= 1'b0;
      table_tx1_wea <= 1'b0;
      table_rx0_wea <= 1'b0;
      table_rx1_wea <= 1'b0;

      select_gain_table <= 1'b0;




      if (write_req_shift_reg[1]) begin

        s_ctrlport_resp_ack     <= 1'b1;
        s_ctrlport_resp_data    <= {32{1'bx}};
        s_ctrlport_resp_status  <= CTRL_STS_OKAY;

        case (register_base_address)
          BASE_ADDRESS + TX0_DSA_ATR(0): begin
            ram_tx0_wea <= 1'b1;
          end
          BASE_ADDRESS + TX1_DSA_ATR(0): begin
            ram_tx1_wea <= 1'b1;
          end
          BASE_ADDRESS + RX0_DSA_ATR(0): begin
            ram_rx0_wea <= 1'b1;
          end
          BASE_ADDRESS + RX1_DSA_ATR(0): begin
            ram_rx1_wea <= 1'b1;
          end

          BASE_ADDRESS + TX0_DSA_TABLE(0): begin
            table_tx0_wea <= 1'b1;
          end
          BASE_ADDRESS + TX1_DSA_TABLE(0): begin
            table_tx1_wea <= 1'b1;
          end
          BASE_ADDRESS + RX0_DSA_TABLE(0): begin
            table_rx0_wea <= 1'b1;
          end
          BASE_ADDRESS + RX1_DSA_TABLE(0): begin
            table_rx1_wea <= 1'b1;
          end

          BASE_ADDRESS + TX0_DSA_TABLE_SELECT(0): begin
            ram_tx0_wea       <= 1'b1;
            select_gain_table <= 1'b1;
          end
          BASE_ADDRESS + TX1_DSA_TABLE_SELECT(0): begin
            ram_tx1_wea       <= 1'b1;
            select_gain_table <= 1'b1;
          end
          BASE_ADDRESS + RX0_DSA_TABLE_SELECT(0): begin
            ram_rx0_wea       <= 1'b1;
            select_gain_table <= 1'b1;
          end
          BASE_ADDRESS + RX1_DSA_TABLE_SELECT(0): begin
            ram_rx1_wea       <= 1'b1;
            select_gain_table <= 1'b1;
          end


          default: begin
            if (address_in_range) begin
              s_ctrlport_resp_status <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack <= 1'b0;
            end
          end
        endcase




      end else if (read_req_shift_reg[1]) begin

        s_ctrlport_resp_ack     <= 1'b1;
        s_ctrlport_resp_status  <= CTRL_STS_OKAY;
        s_ctrlport_resp_data    <= {32{1'b0}};

        case (register_base_address)
          BASE_ADDRESS + TX0_DSA_ATR(0): begin
            s_ctrlport_resp_data <= ram_tx0_doa & TX_DSA_CONTROL_MASK;
          end
          BASE_ADDRESS + TX1_DSA_ATR(0): begin
            s_ctrlport_resp_data <= ram_tx1_doa & TX_DSA_CONTROL_MASK;
          end
          BASE_ADDRESS + RX0_DSA_ATR(0): begin
            s_ctrlport_resp_data <= ram_rx0_doa & RX_DSA_CONTROL_MASK;
          end
          BASE_ADDRESS + RX1_DSA_ATR(0): begin
            s_ctrlport_resp_data <= ram_rx1_doa & RX_DSA_CONTROL_MASK;
          end
          BASE_ADDRESS + TX0_DSA_TABLE(0): begin
            s_ctrlport_resp_data <= table_tx0_doa & TX_DSA_CONTROL_MASK;
          end
          BASE_ADDRESS + TX1_DSA_TABLE(0): begin
            s_ctrlport_resp_data <= table_tx1_doa & TX_DSA_CONTROL_MASK;
          end
          BASE_ADDRESS + RX0_DSA_TABLE(0): begin
            s_ctrlport_resp_data <= table_rx0_doa & RX_DSA_CONTROL_MASK;
          end
          BASE_ADDRESS + RX1_DSA_TABLE(0): begin
            s_ctrlport_resp_data <= table_rx1_doa & RX_DSA_CONTROL_MASK;
          end

          default: begin
            if (address_in_range) begin
              s_ctrlport_resp_status <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack <= 1'b0;
            end
          end
        endcase


      end else begin
        s_ctrlport_resp_ack <= 1'b0;
      end
    end
  end


  reg [ 7:0] ram_addr        =  8'b0;
  reg [ 7:0] gain_table_addr =  8'b0;
  reg [31:0] ram_datain      = 32'b0;
  always @(posedge ctrlport_clk) begin


    if (s_ctrlport_req_wr || s_ctrlport_req_rd) begin
      ram_addr        <= register_index;
      ram_datain      <= s_ctrlport_req_data;

      case (register_base_address)
        BASE_ADDRESS + TX0_DSA_TABLE_SELECT(0),
        BASE_ADDRESS + TX1_DSA_TABLE_SELECT(0),
        BASE_ADDRESS + RX0_DSA_TABLE_SELECT(0),
        BASE_ADDRESS + RX1_DSA_TABLE_SELECT(0): begin
          gain_table_addr <= s_ctrlport_req_data[TABLE_INDEX_MSB:TABLE_INDEX];
        end
        default: begin
          gain_table_addr <= register_index;
        end
      endcase
    end


    tx0_dsa_1_reg   <= ram_tx0_dob[  TX_DSA1_MSB :   TX_DSA1];
    tx0_dsa_2_reg   <= ram_tx0_dob[  TX_DSA2_MSB :   TX_DSA2];

    tx1_dsa_1_reg   <= ram_tx1_dob[  TX_DSA1_MSB :   TX_DSA1];
    tx1_dsa_2_reg   <= ram_tx1_dob[  TX_DSA2_MSB :   TX_DSA2];

    rx0_dsa_1_reg   <= ram_rx0_dob[  RX_DSA1_MSB :   RX_DSA1];
    rx0_dsa_2_reg   <= ram_rx0_dob[  RX_DSA2_MSB :   RX_DSA2];
    rx0_dsa_3_a_reg <= ram_rx0_dob[RX_DSA3_A_MSB : RX_DSA3_A];
    rx0_dsa_3_b_reg <= ram_rx0_dob[RX_DSA3_B_MSB : RX_DSA3_B];

    rx1_dsa_1_reg   <= ram_rx1_dob[  RX_DSA1_MSB :   RX_DSA1];
    rx1_dsa_2_reg   <= ram_rx1_dob[  RX_DSA2_MSB :   RX_DSA2];
    rx1_dsa_3_a_reg <= ram_rx1_dob[RX_DSA3_A_MSB : RX_DSA3_A];
    rx1_dsa_3_b_reg <= ram_rx1_dob[RX_DSA3_B_MSB : RX_DSA3_B];
  end

  assign tx0_dsa1[6:2] = tx0_dsa_1_reg;
  assign tx0_dsa2[6:2] = tx0_dsa_2_reg;

  assign tx1_dsa1[6:2] = tx1_dsa_1_reg;
  assign tx1_dsa2[6:2] = tx1_dsa_2_reg;




  genvar vi;


  generate
    for (vi=1; vi<=4; vi=vi+1) begin : reverselogic

      assign rx0_dsa1_n[vi]    = !rx0_dsa_1_reg[4-vi];
      assign rx0_dsa2_n[vi]    = !rx0_dsa_2_reg[4-vi];
      assign rx0_dsa3_a_n[vi]  = !rx0_dsa_3_a_reg[4-vi];
      assign rx0_dsa3_b_n[vi]  = !rx0_dsa_3_b_reg[4-vi];

      assign rx1_dsa1_n[vi]    = !rx1_dsa_1_reg[4-vi];
      assign rx1_dsa2_n[vi]    = !rx1_dsa_2_reg[4-vi];
      assign rx1_dsa3_a_n[vi]  = !rx1_dsa_3_a_reg[4-vi];
      assign rx1_dsa3_b_n[vi]  = !rx1_dsa_3_b_reg[4-vi];
    end
  endgenerate





  wire [31:0] ram_rx0_dia = select_gain_table ? table_rx0_doa : ram_datain;
  wire [31:0] ram_rx1_dia = select_gain_table ? table_rx1_doa : ram_datain;
  wire [31:0] ram_tx0_dia = select_gain_table ? table_tx0_doa : ram_datain;
  wire [31:0] ram_tx1_dia = select_gain_table ? table_tx1_doa : ram_datain;

  ram_2port #(
    .DWIDTH     (32),
    .AWIDTH     (8),
    .RW_MODE    ("READ-FIRST"),
    .RAM_TYPE   ("AUTOMATIC"),
    .OUT_REG    (0),
    .INIT_FILE  ("register_endpoints/memory_init_files/tx_dsa_defaults.hex")
  ) ram_tx0_i (
    .clka   (ctrlport_clk),
    .ena    (1'b1),
    .wea    (ram_tx0_wea),
    .addra  (ram_addr),
    .dia    (ram_tx0_dia),
    .doa    (ram_tx0_doa),
    .clkb   (ctrlport_clk),
    .enb    (1'b1),
    .web    (1'b0),
    .addrb  (atr_config_rf0),
    .dib    (0),
    .dob    (ram_tx0_dob)
  );

  ram_2port #(
    .DWIDTH     (32),
    .AWIDTH     (8),
    .RW_MODE    ("READ-FIRST"),
    .RAM_TYPE   ("AUTOMATIC"),
    .OUT_REG    (0),
    .INIT_FILE  ("register_endpoints/memory_init_files/tx_dsa_defaults.hex")
  ) ram_tx1_i (
    .clka   (ctrlport_clk),
    .ena    (1'b1),
    .wea    (ram_tx1_wea),
    .addra  (ram_addr),
    .dia    (ram_tx1_dia),
    .doa    (ram_tx1_doa),
    .clkb   (ctrlport_clk),
    .enb    (1'b1),
    .web    (1'b0),
    .addrb  (atr_config_rf1),
    .dib    (0),
    .dob    (ram_tx1_dob)
  );

  ram_2port #(
    .DWIDTH     (32),
    .AWIDTH     (8),
    .RW_MODE    ("READ-FIRST"),
    .RAM_TYPE   ("AUTOMATIC"),
    .OUT_REG    (0),
    .INIT_FILE  ("register_endpoints/memory_init_files/rx_dsa_defaults.hex")
  ) ram_rx0_i (
    .clka   (ctrlport_clk),
    .ena    (1'b1),
    .wea    (ram_rx0_wea),
    .addra  (ram_addr),
    .dia    (ram_rx0_dia),
    .doa    (ram_rx0_doa),
    .clkb   (ctrlport_clk),
    .enb    (1'b1),
    .web    (1'b0),
    .addrb  (atr_config_rf0),
    .dib    (0),
    .dob    (ram_rx0_dob)
  );

  ram_2port #(
    .DWIDTH     (32),
    .AWIDTH     (8),
    .RW_MODE    ("READ-FIRST"),
    .RAM_TYPE   ("AUTOMATIC"),
    .OUT_REG    (0),
    .INIT_FILE  ("register_endpoints/memory_init_files/rx_dsa_defaults.hex")
  ) ram_rx1_i (
    .clka   (ctrlport_clk),
    .ena    (1'b1),
    .wea    (ram_rx1_wea),
    .addra  (ram_addr),
    .dia    (ram_rx1_dia),
    .doa    (ram_rx1_doa),
    .clkb   (ctrlport_clk),
    .enb    (1'b1),
    .web    (1'b0),
    .addrb  (atr_config_rf1),
    .dib    (0),
    .dob    (ram_rx1_dob)
  );





  ram_2port #(
    .DWIDTH     (32),
    .AWIDTH     (8),
    .RW_MODE    ("READ-FIRST"),
    .RAM_TYPE   ("AUTOMATIC"),
    .OUT_REG    (0),
    .INIT_FILE  ("register_endpoints/memory_init_files/tx_dsa_defaults.hex")
  ) table_tx0_i (
    .clka   (ctrlport_clk),
    .ena    (1'b1),
    .wea    (table_tx0_wea),
    .addra  (gain_table_addr),
    .dia    (ram_datain),
    .doa    (table_tx0_doa),
    .clkb   (ctrlport_clk),
    .enb    (1'b1),
    .web    (1'b0),
    .addrb  (8'b0),
    .dib    (32'b0),
    .dob    ()
  );

  ram_2port #(
    .DWIDTH     (32),
    .AWIDTH     (8),
    .RW_MODE    ("READ-FIRST"),
    .RAM_TYPE   ("AUTOMATIC"),
    .OUT_REG    (0),
    .INIT_FILE  ("register_endpoints/memory_init_files/tx_dsa_defaults.hex")
  ) table_tx1_i (
    .clka   (ctrlport_clk),
    .ena    (1'b1),
    .wea    (table_tx1_wea),
    .addra  (gain_table_addr),
    .dia    (ram_datain),
    .doa    (table_tx1_doa),
    .clkb   (ctrlport_clk),
    .enb    (1'b1),
    .web    (1'b0),
    .addrb  (8'b0),
    .dib    (32'b0),
    .dob    ()
  );

  ram_2port #(
    .DWIDTH     (32),
    .AWIDTH     (8),
    .RW_MODE    ("READ-FIRST"),
    .RAM_TYPE   ("AUTOMATIC"),
    .OUT_REG    (0),
    .INIT_FILE  ("register_endpoints/memory_init_files/rx_dsa_defaults.hex")
  ) table_rx0_i (
    .clka   (ctrlport_clk),
    .ena    (1'b1),
    .wea    (table_rx0_wea),
    .addra  (gain_table_addr),
    .dia    (ram_datain),
    .doa    (table_rx0_doa),
    .clkb   (ctrlport_clk),
    .enb    (1'b1),
    .web    (1'b0),
    .addrb  (8'b0),
    .dib    (32'b0),
    .dob    ()
  );

  ram_2port #(
    .DWIDTH     (32),
    .AWIDTH     (8),
    .RW_MODE    ("READ-FIRST"),
    .RAM_TYPE   ("AUTOMATIC"),
    .OUT_REG    (0),
    .INIT_FILE  ("register_endpoints/memory_init_files/rx_dsa_defaults.hex")
  ) table_rx1_i (
    .clka   (ctrlport_clk),
    .ena    (1'b1),
    .wea    (table_rx1_wea),
    .addra  (gain_table_addr),
    .dia    (ram_datain),
    .doa    (table_rx1_doa),
    .clkb   (ctrlport_clk),
    .enb    (1'b1),
    .web    (1'b0),
    .addrb  (8'b0),
    .dib    (32'b0),
    .dob    ()
  );

endmodule