data/full_repos/permissive/441359809/src/yosys/tests/sva/extnets.sv
data/verilator_xmls/9718adf1-bd25-495b-9904-2a3765982913.xml
module A;
	wire i, y;
`ifdef FAIL
	assign B.x = i;
`else
	assign B.x = !i;
`endif
	assign y = !B.y;
endmodule
module A;

	wire i, y;
`ifdef FAIL
	assign B.x = i;
`else
	assign B.x = !i;
`endif
	assign y = !B.y;
endmodule