data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v
1: b'%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:52: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 11 bits.\n                                                                                                : ... In instance rendering\nwire [7:0] flooraddr = haddr+scrolladdr;\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:66: Operator ADD expects 32 or 10 bits on the RHS, but RHS\'s VARREF \'jump_pos\' generates 7 bits.\n                                                                                                : ... In instance rendering\n                    layers[0] <= dinospritedead[(vaddr-155+jump_pos) >> 1][(haddr-30) >> 1];\n                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:70: Operator ADD expects 32 or 10 bits on the RHS, but RHS\'s VARREF \'jump_pos\' generates 7 bits.\n                                                                                                : ... In instance rendering\n                        layers[0] <= dinosprite1[(vaddr-155+jump_pos) >> 1][(haddr-30) >> 1];\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:73: Operator ADD expects 32 or 10 bits on the RHS, but RHS\'s VARREF \'jump_pos\' generates 7 bits.\n                                                                                                : ... In instance rendering\n                        layers[0] <= dinosprite2[(vaddr-155+jump_pos) >> 1][(haddr-30) >> 1];\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:63: Operator ADD expects 32 or 10 bits on the RHS, but RHS\'s VARREF \'jump_pos\' generates 7 bits.\n                                                                                                : ... In instance rendering\n            if (haddr > 30 && haddr < 75 && (vaddr + jump_pos) > 155 && (vaddr + jump_pos) < 248 && game_start_blink) begin\n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:63: Operator ADD expects 32 or 10 bits on the RHS, but RHS\'s VARREF \'jump_pos\' generates 7 bits.\n                                                                                                : ... In instance rendering\n            if (haddr > 30 && haddr < 75 && (vaddr + jump_pos) > 155 && (vaddr + jump_pos) < 248 && game_start_blink) begin\n                                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:140: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[0]  = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:141: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[1]  = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:142: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[2]  = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:143: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[3]  = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:144: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[4]  = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:145: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[5]  = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:146: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[6]  = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:147: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[7]  = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:148: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[8]  = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:149: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[9]  = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:150: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[10] = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:151: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[11] = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:152: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[12] = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:153: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[13] = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:154: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[14] = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:155: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[15] = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:156: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[16] = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:157: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[17] = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:158: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[18] = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:159: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[19] = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:160: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[20] = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:161: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[21] = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:162: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[22] = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:163: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'hff000\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[23] = 22\'b0011111111000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:164: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h1ff800\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[24] = 22\'b0111111111100000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:165: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h1fd800\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[25] = 22\'b0111111101100000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:166: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h1ff800\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[26] = 22\'b0111111111100000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:167: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h1ff800\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[27] = 22\'b0111111111100000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:168: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h1ff800\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[28] = 22\'b0111111111100000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:169: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'hf800\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[29] = 22\'b0000001111100000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:170: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h7f800\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[30] = 22\'b0001111111100000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:171: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h7c02\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[31] = 22\'b0000000111110000000010;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:172: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h7f02\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[32] = 22\'b0000000111111100000010;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:173: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h1ff86\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[33] = 22\'b0000011111111110000110;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:174: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h17fce\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[34] = 22\'b0000010111111111001110;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:175: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h7ffe\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[35] = 22\'b0000000111111111111110;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:176: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h7ffe\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[36] = 22\'b0000000111111111111110;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:177: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h3ffc\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[37] = 22\'b0000000011111111111100;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:178: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h3ff8\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[38] = 22\'b0000000011111111111000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:179: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h1ff0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[39] = 22\'b0000000001111111110000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:180: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'hfe0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[40] = 22\'b0000000000111111100000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:181: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'hcc0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[41] = 22\'b0000000000110011000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:182: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h980\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[42] = 22\'b0000000000100110000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:183: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h800\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[43] = 22\'b0000000000100000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:184: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h1800\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[44] = 22\'b0000000001100000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:185: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[45] = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:186: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite1[46] = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:190: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[0]  = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:191: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[1]  = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:192: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[2]  = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:193: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[3]  = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:194: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[4]  = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:195: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[5]  = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:196: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[6]  = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:197: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[7]  = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:198: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[8]  = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:199: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[9]  = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:200: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[10] = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:201: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[11] = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:202: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[12] = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:203: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[13] = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:204: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[14] = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:205: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[15] = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:206: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[16] = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:207: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[17] = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:208: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[18] = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:209: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[19] = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:210: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[20] = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:211: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[21] = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:212: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[22] = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:213: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'hff000\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[23] = 22\'b0011111111000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:214: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h1ff800\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[24] = 22\'b0111111111100000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:215: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h1fd800\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[25] = 22\'b0111111101100000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:216: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h1ff800\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[26] = 22\'b0111111111100000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:217: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h1ff800\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[27] = 22\'b0111111111100000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:218: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h1ff800\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[28] = 22\'b0111111111100000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:219: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'hf800\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[29] = 22\'b0000001111100000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:220: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h7f800\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[30] = 22\'b0001111111100000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:221: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h7c02\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[31] = 22\'b0000000111110000000010;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:222: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h7f02\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[32] = 22\'b0000000111111100000010;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:223: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h1ff86\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[33] = 22\'b0000011111111110000110;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:224: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h17fce\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[34] = 22\'b0000010111111111001110;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:225: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h7ffe\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[35] = 22\'b0000000111111111111110;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:226: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h7ffe\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[36] = 22\'b0000000111111111111110;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:227: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h3ffc\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[37] = 22\'b0000000011111111111100;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:228: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h3ff8\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[38] = 22\'b0000000011111111111000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:229: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h1ff0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[39] = 22\'b0000000001111111110000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:230: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'hfe0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[40] = 22\'b0000000000111111100000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:231: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h19c0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[41] = 22\'b0000000001100111000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:232: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'hc0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[42] = 22\'b0000000000000011000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:233: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'hc0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[43] = 22\'b0000000000000011000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:234: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'hc0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[44] = 22\'b0000000000000011000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:235: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[45] = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:236: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinosprite2[46] = 22\'b0000000000000000000000;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:240: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[0]  = 22\'b0000000000000000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:241: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[1]  = 22\'b0000000000000000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:242: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[2]  = 22\'b0000000000000000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:243: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[3]  = 22\'b0000000000000000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:244: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[4]  = 22\'b0000000000000000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:245: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[5]  = 22\'b0000000000000000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:246: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[6]  = 22\'b0000000000000000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:247: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[7]  = 22\'b0000000000000000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:248: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[8]  = 22\'b0000000000000000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:249: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[9]  = 22\'b0000000000000000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:250: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[10] = 22\'b0000000000000000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:251: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[11] = 22\'b0000000000000000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:252: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[12] = 22\'b0000000000000000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:253: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[13] = 22\'b0000000000000000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:254: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[14] = 22\'b0000000000000000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:255: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[15] = 22\'b0000000000000000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:256: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[16] = 22\'b0000000000000000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:257: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[17] = 22\'b0000000000000000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:258: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[18] = 22\'b0000000000000000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:259: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[19] = 22\'b0000000000000000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:260: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[20] = 22\'b0000000000000000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:261: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[21] = 22\'b0000000000000000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:262: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[22] = 22\'b0000000000000000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:263: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'hff000\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[23] = 22\'b0011111111000000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:264: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h1ff800\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[24] = 22\'b0111111111100000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:265: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h1fd800\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[25] = 22\'b0111111101100000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:266: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h1ff800\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[26] = 22\'b0111111111100000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:267: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h1ff800\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[27] = 22\'b0111111111100000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:268: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h1ff800\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[28] = 22\'b0111111111100000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:269: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h1ff800\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[29] = 22\'b0111111111100000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:270: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h7f800\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[30] = 22\'b0001111111100000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:271: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h7c02\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[31] = 22\'b0000000111110000000010;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:272: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h7f02\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[32] = 22\'b0000000111111100000010;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:273: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h1ff86\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[33] = 22\'b0000011111111110000110;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:274: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h17fce\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[34] = 22\'b0000010111111111001110;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:275: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h7ffe\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[35] = 22\'b0000000111111111111110;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:276: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h7ffe\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[36] = 22\'b0000000111111111111110;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:277: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h3ffc\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[37] = 22\'b0000000011111111111100;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:278: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h3ff8\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[38] = 22\'b0000000011111111111000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:279: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h1ff0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[39] = 22\'b0000000001111111110000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:280: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'hfe0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[40] = 22\'b0000000000111111100000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:281: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'hdc0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[41] = 22\'b0000000000110111000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:282: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h8c0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[42] = 22\'b0000000000100011000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:283: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h840\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[43] = 22\'b0000000000100001000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:284: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h18c0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[44] = 22\'b0000000001100011000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:285: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[45] = 22\'b0000000000000000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:286: Operator ASSIGN expects 23 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                 : ... In instance rendering\n    dinospritedead[46] = 22\'b0000000000000000000000;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:290: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'hc0\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[0]  = 26\'b00000000000000000011000000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:291: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'he0\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[1]  = 26\'b00000000000000000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:292: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h2000e0\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[2]  = 26\'b00001000000000000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:293: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h3000e0\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[3]  = 26\'b00001100000000000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:294: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h3000e0\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[4]  = 26\'b00001100000000000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:295: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h3000e0\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[5]  = 26\'b00001100000000000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:296: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h3008e0\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[6]  = 26\'b00001100000000100011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:297: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h300ce0\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[7]  = 26\'b00001100000000110011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:298: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h320ce0\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[8]  = 26\'b00001100100000110011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:299: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h320ce0\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[9]  = 26\'b00001100100000110011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:300: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h320ce0\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[10] = 26\'b00001100100000110011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:301: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h320ce4\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[11] = 26\'b00001100100000110011100100;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:302: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h320ce6\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[12] = 26\'b00001100100000110011100110;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:303: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h320ce6\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[13] = 26\'b00001100100000110011100110;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:304: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h320ce6\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[14] = 26\'b00001100100000110011100110;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:305: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h320ce6\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[15] = 26\'b00001100100000110011100110;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:306: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h1320ce6\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[16] = 26\'b01001100100000110011100110;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:307: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h13e0ce6\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[17] = 26\'b01001111100000110011100110;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:308: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h13c0ce6\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[18] = 26\'b01001111000000110011100110;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:309: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h13c0ce6\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[19] = 26\'b01001111000000110011100110;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:310: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h1308fe6\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[20] = 26\'b01001100001000111111100110;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:311: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h1308fe6\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[21] = 26\'b01001100001000111111100110;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:312: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h1308fe6\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[22] = 26\'b01001100001000111111100110;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:313: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h13087e6\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[23] = 26\'b01001100001000011111100110;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:314: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h13087e6\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[24] = 26\'b01001100001000011111100110;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:315: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h13290e6\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[25] = 26\'b01001100101001000011100110;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:316: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h13290e4\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[26] = 26\'b01001100101001000011100100;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:317: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h13290fc\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[27] = 26\'b01001100101001000011111100;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:318: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h13290f8\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[28] = 26\'b01001100101001000011111000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:319: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h1f290f8\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[29] = 26\'b01111100101001000011111000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:320: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h1f290e0\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[30] = 26\'b01111100101001000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:321: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'hf290e0\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[31] = 26\'b00111100101001000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:322: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'hf290e0\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[32] = 26\'b00111100101001000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:323: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h3290e0\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[33] = 26\'b00001100101001000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:324: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h33e0e0\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[34] = 26\'b00001100111110000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:325: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h31e0e0\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[35] = 26\'b00001100011110000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:326: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h3180e0\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[36] = 26\'b00001100011000000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:327: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h3080e0\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[37] = 26\'b00001100001000000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:328: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h3080e0\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[38] = 26\'b00001100001000000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:329: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h3080e0\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[39] = 26\'b00001100001000000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:330: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h3080e0\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[40] = 26\'b00001100001000000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:331: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h3080e0\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[41] = 26\'b00001100001000000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:332: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h3080e0\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[42] = 26\'b00001100001000000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:333: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h3080e0\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[43] = 26\'b00001100001000000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:334: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h3080e0\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[44] = 26\'b00001100001000000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:335: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h3080e0\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[45] = 26\'b00001100001000000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:336: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'26\'h3081e0\' generates 26 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite1[46] = 26\'b00001100001000000111100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:340: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h0\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[0]  = 13\'b0000000000000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:341: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h40\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[1]  = 13\'b0000001000000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:342: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'he0\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[2]  = 13\'b0000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:343: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'he0\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[3]  = 13\'b0000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:344: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'he0\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[4]  = 13\'b0000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:345: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'he0\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[5]  = 13\'b0000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:346: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h8e0\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[6]  = 13\'b0100011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:347: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'hce0\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[7]  = 13\'b0110011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:348: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'hce0\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[8]  = 13\'b0110011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:349: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'hce0\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[9]  = 13\'b0110011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:350: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'hce0\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[10] = 13\'b0110011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:351: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'hce4\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[11] = 13\'b0110011100100;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:352: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'hce6\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[12] = 13\'b0110011100110;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:353: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'hce6\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[13] = 13\'b0110011100110;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:354: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'hce6\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[14] = 13\'b0110011100110;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:355: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'hce6\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[15] = 13\'b0110011100110;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:356: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'hce6\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[16] = 13\'b0110011100110;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:357: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'hce6\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[17] = 13\'b0110011100110;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:358: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'hce6\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[18] = 13\'b0110011100110;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:359: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'hce6\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[19] = 13\'b0110011100110;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:360: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'hce6\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[20] = 13\'b0110011100110;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:361: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'hfe6\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[21] = 13\'b0111111100110;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:362: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'hfe6\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[22] = 13\'b0111111100110;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:363: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h7e6\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[23] = 13\'b0011111100110;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:364: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h7e6\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[24] = 13\'b0011111100110;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:365: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h3e6\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[25] = 13\'b0001111100110;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:366: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'he6\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[26] = 13\'b0000011100110;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:367: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'hfc\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[27] = 13\'b0000011111100;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:368: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'hfc\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[28] = 13\'b0000011111100;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:369: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'hf8\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[29] = 13\'b0000011111000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:370: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'hf8\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[30] = 13\'b0000011111000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:371: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'he0\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[31] = 13\'b0000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:372: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'he0\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[32] = 13\'b0000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:373: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'he0\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[33] = 13\'b0000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:374: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'he0\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[34] = 13\'b0000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:375: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'he0\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[35] = 13\'b0000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:376: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'he0\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[36] = 13\'b0000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:377: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'he0\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[37] = 13\'b0000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:378: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'he0\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[38] = 13\'b0000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:379: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'he0\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[39] = 13\'b0000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:380: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'he0\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[40] = 13\'b0000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:381: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'he0\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[41] = 13\'b0000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:382: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'he0\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[42] = 13\'b0000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:383: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'he0\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[43] = 13\'b0000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:384: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'he0\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[44] = 13\'b0000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:385: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'he0\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[45] = 13\'b0000011100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:386: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h1e0\' generates 13 bits.\n                                                                                                 : ... In instance rendering\n    cactussprite2[46] = 13\'b0000111100000;\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:442: Operator ASSIGN expects 256 bits on the Assign RHS, but Assign RHS\'s CONST \'255\'h70000000000000000000000000000000700000000000\' generates 255 bits.\n                                                                                                 : ... In instance rendering\n    floor[0] = 255\'b000000000000000000000000000000000000000000000000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011100000000000000000000000000000000000000000000;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:443: Operator ASSIGN expects 256 bits on the Assign RHS, but Assign RHS\'s CONST \'255\'h7fffffffffffffffffff9f1fffffffffffffffffffffffffffff9f1fffffffff\' generates 255 bits.\n                                                                                                 : ... In instance rendering\n    floor[1] = 255\'b111111111111111111111111111111111111111111111111111111111111111111111111111111110011111000111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100111110001111111111111111111111111111111111111;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:444: Operator ASSIGN expects 256 bits on the Assign RHS, but Assign RHS\'s CONST \'255\'h1f0000000000000000000000000000001f000000000\' generates 255 bits.\n                                                                                                 : ... In instance rendering\n    floor[2] = 255\'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111000000000000000000000000000000000000;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:445: Operator ASSIGN expects 256 bits on the Assign RHS, but Assign RHS\'s CONST \'255\'h40010001b0200200000204008000010040010001b020020000020400800001\' generates 255 bits.\n                                                                                                 : ... In instance rendering\n    floor[3] = 255\'b000000001000000000000010000000000000001101100000010000000000010000000000000000000000010000001000000000010000000000000000000000100000000010000000000000100000000000000011011000000100000000000100000000000000000000000100000010000000000100000000000000000000001;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:446: Operator ASSIGN expects 256 bits on the Assign RHS, but Assign RHS\'s CONST \'255\'h2001000800000000210020010040222020010008000000002100200100402220\' generates 255 bits.\n                                                                                                 : ... In instance rendering\n    floor[4] = 255\'b010000000000001000000000000100000000000000000000000000000000000001000010000000000100000000000010000000001000000001000100010000000100000000000010000000000001000000000000000000000000000000000000010000100000000001000000000000100000000010000000010001000100000;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:447: Operator ASSIGN expects 256 bits on the Assign RHS, but Assign RHS\'s CONST \'255\'h180000020000480c0000000000000000180000020000480c0000000000000000\' generates 255 bits.\n                                                                                                 : ... In instance rendering\n    floor[5] = 255\'b001100000000000000000000000001000000000000000000100100000001100000000000000000000000000000000000000000000000000000000000000000000011000000000000000000000000010000000000000000001001000000011000000000000000000000000000000000000000000000000000000000000000000;\n             ^\n%Warning-UNSIGNED: data/full_repos/permissive/421223411/verilog/rtl/accelerator/dino/rendering.v:114: Comparison is constant due to unsigned arithmetic\n                                                                                                    : ... In instance rendering\n            if (scrolladdr[9:0] >= 0 && scrolladdr[9:0] < 10) begin\n                                ^~\n%Error: Exiting due to 248 warning(s)\n'
module rendering (
    output wire pixel,
    output wire collision,
    output reg [2:0] cactus_select,

    input wire game_over,
    input wire game_start_blink,
    input wire score_pixel,
    input wire dinosprite_num,

    input wire [2:0] cactus_type,
    input wire [6:0] jump_pos,
    input wire [9:0] vaddr,
    input wire [9:0] haddr,
    input wire [10:0] scrolladdr,

    input wire clk,
    input wire sys_rst
);


reg [22:0]  dinosprite1[46:0];
reg [22:0]  dinosprite2[46:0];
reg [22:0]  dinospritedead[46:0];
reg [255:0] floor[5:0];
reg [26:0]  cactussprite1[46:0];
reg [26:0]  cactussprite2[46:0];
reg [12:0]  cactussprite3[48:0];

reg [4:0] layers;

assign pixel = |{score_pixel, layers};
assign collision = layers[0] & (layers[1] | layers[3] | layers[4]);

wire [7:0] flooraddr = haddr+scrolladdr;

always @(posedge clk) begin
    if (sys_rst) begin
        layers <= 0;
        cactus_select <= 0;
    end
    else begin
        layers <= 0;

        if (vaddr < 480 && haddr < 640) begin
            if (haddr > 30 && haddr < 75 && (vaddr + jump_pos) > 155 && (vaddr + jump_pos) < 248 && game_start_blink) begin

                if (game_over) begin
                    layers[0] <= dinospritedead[(vaddr-155+jump_pos) >> 1][(haddr-30) >> 1];
                end
                else begin
                    if (dinosprite_num) begin
                        layers[0] <= dinosprite1[(vaddr-155+jump_pos) >> 1][(haddr-30) >> 1];
                    end
                    else begin
                        layers[0] <= dinosprite2[(vaddr-155+jump_pos) >> 1][(haddr-30) >> 1];
                    end
                end
            end
            if (vaddr > 244 && vaddr < 251) begin
                layers[2] <= floor[vaddr-245][flooraddr];
            end
            if (vaddr > 203 && vaddr < 250) begin
                if (cactus_select[0]) begin
                    if (cactus_type[0]) begin
                        if ((haddr + scrolladdr[9:0]) > 640 && (haddr + scrolladdr[9:0]) < 667) begin
                            layers[1] <= cactussprite1[vaddr-203][haddr-640+scrolladdr[9:0]];
                        end
                    end
                    else begin
                        if ((haddr + scrolladdr[9:0]) > 640 && (haddr + scrolladdr[9:0]) < 667) begin
                            layers[1] <= cactussprite2[vaddr-203][haddr-640+scrolladdr[9:0]];
                        end
                    end
                end
                if (cactus_select[1]) begin
                    if (cactus_type[1]) begin
                        if ((haddr + scrolladdr[9:0]-250) > 640 && (haddr + scrolladdr[9:0]-250) < 667) begin
                            layers[3] <= cactussprite2[vaddr-203][haddr-640+scrolladdr[9:0]-250];
                        end
                    end
                end
                if (cactus_select[2]) begin
                    if (cactus_type[2]) begin
                        if ((haddr + scrolladdr[10:0]-450) > 640 && (haddr + scrolladdr[10:0]-450) < 667) begin
                            layers[4] <= cactussprite1[vaddr-203][haddr-640+scrolladdr[10:0]-450];
                        end
                    end
                    else begin
                        if ((haddr + scrolladdr[10:0]-450) > 640 && (haddr + scrolladdr[10:0]-450) < 667) begin
                            layers[4] <= cactussprite3[vaddr-203][haddr-640+scrolladdr[10:0]-450];
                        end
                    end
                end
            end

            if (scrolladdr[9:0] >= 0 && scrolladdr[9:0] < 10) begin
                cactus_select[0] <= 1;
            end
            else if (scrolladdr[9:0] > 667) begin
                cactus_select[0] <= 0;
            end

            if (scrolladdr[9:0] >= 250 && scrolladdr[9:0] < 260) begin
                cactus_select[1] <= 1;
            end
            else if (scrolladdr[9:0] > 917) begin
                cactus_select[1] <= 0;
            end

            if (scrolladdr[9:0] >= 450 && scrolladdr[9:0] < 460) begin
                cactus_select[2] <= 1;
            end
            else if (scrolladdr[10:0] > 1117) begin
                cactus_select[2] <= 0;
            end

        end
    end
end

initial begin
    dinosprite1[0]  = 22'b0000000000000000000000;
    dinosprite1[1]  = 22'b0000000000000000000000;
    dinosprite1[2]  = 22'b0000000000000000000000;
    dinosprite1[3]  = 22'b0000000000000000000000;
    dinosprite1[4]  = 22'b0000000000000000000000;
    dinosprite1[5]  = 22'b0000000000000000000000;
    dinosprite1[6]  = 22'b0000000000000000000000;
    dinosprite1[7]  = 22'b0000000000000000000000;
    dinosprite1[8]  = 22'b0000000000000000000000;
    dinosprite1[9]  = 22'b0000000000000000000000;
    dinosprite1[10] = 22'b0000000000000000000000;
    dinosprite1[11] = 22'b0000000000000000000000;
    dinosprite1[12] = 22'b0000000000000000000000;
    dinosprite1[13] = 22'b0000000000000000000000;
    dinosprite1[14] = 22'b0000000000000000000000;
    dinosprite1[15] = 22'b0000000000000000000000;
    dinosprite1[16] = 22'b0000000000000000000000;
    dinosprite1[17] = 22'b0000000000000000000000;
    dinosprite1[18] = 22'b0000000000000000000000;
    dinosprite1[19] = 22'b0000000000000000000000;
    dinosprite1[20] = 22'b0000000000000000000000;
    dinosprite1[21] = 22'b0000000000000000000000;
    dinosprite1[22] = 22'b0000000000000000000000;
    dinosprite1[23] = 22'b0011111111000000000000;
    dinosprite1[24] = 22'b0111111111100000000000;
    dinosprite1[25] = 22'b0111111101100000000000;
    dinosprite1[26] = 22'b0111111111100000000000;
    dinosprite1[27] = 22'b0111111111100000000000;
    dinosprite1[28] = 22'b0111111111100000000000;
    dinosprite1[29] = 22'b0000001111100000000000;
    dinosprite1[30] = 22'b0001111111100000000000;
    dinosprite1[31] = 22'b0000000111110000000010;
    dinosprite1[32] = 22'b0000000111111100000010;
    dinosprite1[33] = 22'b0000011111111110000110;
    dinosprite1[34] = 22'b0000010111111111001110;
    dinosprite1[35] = 22'b0000000111111111111110;
    dinosprite1[36] = 22'b0000000111111111111110;
    dinosprite1[37] = 22'b0000000011111111111100;
    dinosprite1[38] = 22'b0000000011111111111000;
    dinosprite1[39] = 22'b0000000001111111110000;
    dinosprite1[40] = 22'b0000000000111111100000;
    dinosprite1[41] = 22'b0000000000110011000000;
    dinosprite1[42] = 22'b0000000000100110000000;
    dinosprite1[43] = 22'b0000000000100000000000;
    dinosprite1[44] = 22'b0000000001100000000000;
    dinosprite1[45] = 22'b0000000000000000000000;
    dinosprite1[46] = 22'b0000000000000000000000;
end

initial begin
    dinosprite2[0]  = 22'b0000000000000000000000;
    dinosprite2[1]  = 22'b0000000000000000000000;
    dinosprite2[2]  = 22'b0000000000000000000000;
    dinosprite2[3]  = 22'b0000000000000000000000;
    dinosprite2[4]  = 22'b0000000000000000000000;
    dinosprite2[5]  = 22'b0000000000000000000000;
    dinosprite2[6]  = 22'b0000000000000000000000;
    dinosprite2[7]  = 22'b0000000000000000000000;
    dinosprite2[8]  = 22'b0000000000000000000000;
    dinosprite2[9]  = 22'b0000000000000000000000;
    dinosprite2[10] = 22'b0000000000000000000000;
    dinosprite2[11] = 22'b0000000000000000000000;
    dinosprite2[12] = 22'b0000000000000000000000;
    dinosprite2[13] = 22'b0000000000000000000000;
    dinosprite2[14] = 22'b0000000000000000000000;
    dinosprite2[15] = 22'b0000000000000000000000;
    dinosprite2[16] = 22'b0000000000000000000000;
    dinosprite2[17] = 22'b0000000000000000000000;
    dinosprite2[18] = 22'b0000000000000000000000;
    dinosprite2[19] = 22'b0000000000000000000000;
    dinosprite2[20] = 22'b0000000000000000000000;
    dinosprite2[21] = 22'b0000000000000000000000;
    dinosprite2[22] = 22'b0000000000000000000000;
    dinosprite2[23] = 22'b0011111111000000000000;
    dinosprite2[24] = 22'b0111111111100000000000;
    dinosprite2[25] = 22'b0111111101100000000000;
    dinosprite2[26] = 22'b0111111111100000000000;
    dinosprite2[27] = 22'b0111111111100000000000;
    dinosprite2[28] = 22'b0111111111100000000000;
    dinosprite2[29] = 22'b0000001111100000000000;
    dinosprite2[30] = 22'b0001111111100000000000;
    dinosprite2[31] = 22'b0000000111110000000010;
    dinosprite2[32] = 22'b0000000111111100000010;
    dinosprite2[33] = 22'b0000011111111110000110;
    dinosprite2[34] = 22'b0000010111111111001110;
    dinosprite2[35] = 22'b0000000111111111111110;
    dinosprite2[36] = 22'b0000000111111111111110;
    dinosprite2[37] = 22'b0000000011111111111100;
    dinosprite2[38] = 22'b0000000011111111111000;
    dinosprite2[39] = 22'b0000000001111111110000;
    dinosprite2[40] = 22'b0000000000111111100000;
    dinosprite2[41] = 22'b0000000001100111000000;
    dinosprite2[42] = 22'b0000000000000011000000;
    dinosprite2[43] = 22'b0000000000000011000000;
    dinosprite2[44] = 22'b0000000000000011000000;
    dinosprite2[45] = 22'b0000000000000000000000;
    dinosprite2[46] = 22'b0000000000000000000000;
end

initial begin
    dinospritedead[0]  = 22'b0000000000000000000000;
    dinospritedead[1]  = 22'b0000000000000000000000;
    dinospritedead[2]  = 22'b0000000000000000000000;
    dinospritedead[3]  = 22'b0000000000000000000000;
    dinospritedead[4]  = 22'b0000000000000000000000;
    dinospritedead[5]  = 22'b0000000000000000000000;
    dinospritedead[6]  = 22'b0000000000000000000000;
    dinospritedead[7]  = 22'b0000000000000000000000;
    dinospritedead[8]  = 22'b0000000000000000000000;
    dinospritedead[9]  = 22'b0000000000000000000000;
    dinospritedead[10] = 22'b0000000000000000000000;
    dinospritedead[11] = 22'b0000000000000000000000;
    dinospritedead[12] = 22'b0000000000000000000000;
    dinospritedead[13] = 22'b0000000000000000000000;
    dinospritedead[14] = 22'b0000000000000000000000;
    dinospritedead[15] = 22'b0000000000000000000000;
    dinospritedead[16] = 22'b0000000000000000000000;
    dinospritedead[17] = 22'b0000000000000000000000;
    dinospritedead[18] = 22'b0000000000000000000000;
    dinospritedead[19] = 22'b0000000000000000000000;
    dinospritedead[20] = 22'b0000000000000000000000;
    dinospritedead[21] = 22'b0000000000000000000000;
    dinospritedead[22] = 22'b0000000000000000000000;
    dinospritedead[23] = 22'b0011111111000000000000;
    dinospritedead[24] = 22'b0111111111100000000000;
    dinospritedead[25] = 22'b0111111101100000000000;
    dinospritedead[26] = 22'b0111111111100000000000;
    dinospritedead[27] = 22'b0111111111100000000000;
    dinospritedead[28] = 22'b0111111111100000000000;
    dinospritedead[29] = 22'b0111111111100000000000;
    dinospritedead[30] = 22'b0001111111100000000000;
    dinospritedead[31] = 22'b0000000111110000000010;
    dinospritedead[32] = 22'b0000000111111100000010;
    dinospritedead[33] = 22'b0000011111111110000110;
    dinospritedead[34] = 22'b0000010111111111001110;
    dinospritedead[35] = 22'b0000000111111111111110;
    dinospritedead[36] = 22'b0000000111111111111110;
    dinospritedead[37] = 22'b0000000011111111111100;
    dinospritedead[38] = 22'b0000000011111111111000;
    dinospritedead[39] = 22'b0000000001111111110000;
    dinospritedead[40] = 22'b0000000000111111100000;
    dinospritedead[41] = 22'b0000000000110111000000;
    dinospritedead[42] = 22'b0000000000100011000000;
    dinospritedead[43] = 22'b0000000000100001000000;
    dinospritedead[44] = 22'b0000000001100011000000;
    dinospritedead[45] = 22'b0000000000000000000000;
    dinospritedead[46] = 22'b0000000000000000000000;
end

initial begin
    cactussprite1[0]  = 26'b00000000000000000011000000;
    cactussprite1[1]  = 26'b00000000000000000011100000;
    cactussprite1[2]  = 26'b00001000000000000011100000;
    cactussprite1[3]  = 26'b00001100000000000011100000;
    cactussprite1[4]  = 26'b00001100000000000011100000;
    cactussprite1[5]  = 26'b00001100000000000011100000;
    cactussprite1[6]  = 26'b00001100000000100011100000;
    cactussprite1[7]  = 26'b00001100000000110011100000;
    cactussprite1[8]  = 26'b00001100100000110011100000;
    cactussprite1[9]  = 26'b00001100100000110011100000;
    cactussprite1[10] = 26'b00001100100000110011100000;
    cactussprite1[11] = 26'b00001100100000110011100100;
    cactussprite1[12] = 26'b00001100100000110011100110;
    cactussprite1[13] = 26'b00001100100000110011100110;
    cactussprite1[14] = 26'b00001100100000110011100110;
    cactussprite1[15] = 26'b00001100100000110011100110;
    cactussprite1[16] = 26'b01001100100000110011100110;
    cactussprite1[17] = 26'b01001111100000110011100110;
    cactussprite1[18] = 26'b01001111000000110011100110;
    cactussprite1[19] = 26'b01001111000000110011100110;
    cactussprite1[20] = 26'b01001100001000111111100110;
    cactussprite1[21] = 26'b01001100001000111111100110;
    cactussprite1[22] = 26'b01001100001000111111100110;
    cactussprite1[23] = 26'b01001100001000011111100110;
    cactussprite1[24] = 26'b01001100001000011111100110;
    cactussprite1[25] = 26'b01001100101001000011100110;
    cactussprite1[26] = 26'b01001100101001000011100100;
    cactussprite1[27] = 26'b01001100101001000011111100;
    cactussprite1[28] = 26'b01001100101001000011111000;
    cactussprite1[29] = 26'b01111100101001000011111000;
    cactussprite1[30] = 26'b01111100101001000011100000;
    cactussprite1[31] = 26'b00111100101001000011100000;
    cactussprite1[32] = 26'b00111100101001000011100000;
    cactussprite1[33] = 26'b00001100101001000011100000;
    cactussprite1[34] = 26'b00001100111110000011100000;
    cactussprite1[35] = 26'b00001100011110000011100000;
    cactussprite1[36] = 26'b00001100011000000011100000;
    cactussprite1[37] = 26'b00001100001000000011100000;
    cactussprite1[38] = 26'b00001100001000000011100000;
    cactussprite1[39] = 26'b00001100001000000011100000;
    cactussprite1[40] = 26'b00001100001000000011100000;
    cactussprite1[41] = 26'b00001100001000000011100000;
    cactussprite1[42] = 26'b00001100001000000011100000;
    cactussprite1[43] = 26'b00001100001000000011100000;
    cactussprite1[44] = 26'b00001100001000000011100000;
    cactussprite1[45] = 26'b00001100001000000011100000;
    cactussprite1[46] = 26'b00001100001000000111100000;
end

initial begin
    cactussprite2[0]  = 13'b0000000000000;
    cactussprite2[1]  = 13'b0000001000000;
    cactussprite2[2]  = 13'b0000011100000;
    cactussprite2[3]  = 13'b0000011100000;
    cactussprite2[4]  = 13'b0000011100000;
    cactussprite2[5]  = 13'b0000011100000;
    cactussprite2[6]  = 13'b0100011100000;
    cactussprite2[7]  = 13'b0110011100000;
    cactussprite2[8]  = 13'b0110011100000;
    cactussprite2[9]  = 13'b0110011100000;
    cactussprite2[10] = 13'b0110011100000;
    cactussprite2[11] = 13'b0110011100100;
    cactussprite2[12] = 13'b0110011100110;
    cactussprite2[13] = 13'b0110011100110;
    cactussprite2[14] = 13'b0110011100110;
    cactussprite2[15] = 13'b0110011100110;
    cactussprite2[16] = 13'b0110011100110;
    cactussprite2[17] = 13'b0110011100110;
    cactussprite2[18] = 13'b0110011100110;
    cactussprite2[19] = 13'b0110011100110;
    cactussprite2[20] = 13'b0110011100110;
    cactussprite2[21] = 13'b0111111100110;
    cactussprite2[22] = 13'b0111111100110;
    cactussprite2[23] = 13'b0011111100110;
    cactussprite2[24] = 13'b0011111100110;
    cactussprite2[25] = 13'b0001111100110;
    cactussprite2[26] = 13'b0000011100110;
    cactussprite2[27] = 13'b0000011111100;
    cactussprite2[28] = 13'b0000011111100;
    cactussprite2[29] = 13'b0000011111000;
    cactussprite2[30] = 13'b0000011111000;
    cactussprite2[31] = 13'b0000011100000;
    cactussprite2[32] = 13'b0000011100000;
    cactussprite2[33] = 13'b0000011100000;
    cactussprite2[34] = 13'b0000011100000;
    cactussprite2[35] = 13'b0000011100000;
    cactussprite2[36] = 13'b0000011100000;
    cactussprite2[37] = 13'b0000011100000;
    cactussprite2[38] = 13'b0000011100000;
    cactussprite2[39] = 13'b0000011100000;
    cactussprite2[40] = 13'b0000011100000;
    cactussprite2[41] = 13'b0000011100000;
    cactussprite2[42] = 13'b0000011100000;
    cactussprite2[43] = 13'b0000011100000;
    cactussprite2[44] = 13'b0000011100000;
    cactussprite2[45] = 13'b0000011100000;
    cactussprite2[46] = 13'b0000111100000;
end

initial begin
    cactussprite3[0]  = 13'b0000000000000;
    cactussprite3[1]  = 13'b0000001100000;
    cactussprite3[2]  = 13'b0000011100000;
    cactussprite3[3]  = 13'b0000011100000;
    cactussprite3[4]  = 13'b0000011100000;
    cactussprite3[5]  = 13'b0000011100000;
    cactussprite3[6]  = 13'b0000011100000;
    cactussprite3[7]  = 13'b0000011100000;
    cactussprite3[8]  = 13'b0000011100000;
    cactussprite3[9]  = 13'b0000011100000;
    cactussprite3[10] = 13'b0000011100000;
    cactussprite3[11] = 13'b0000011100110;
    cactussprite3[12] = 13'b0000011100110;
    cactussprite3[13] = 13'b0110011100110;
    cactussprite3[14] = 13'b0110011100110;
    cactussprite3[15] = 13'b0110011100110;
    cactussprite3[16] = 13'b0110011100110;
    cactussprite3[17] = 13'b0110011100110;
    cactussprite3[18] = 13'b0110011100110;
    cactussprite3[19] = 13'b0110011100110;
    cactussprite3[20] = 13'b0110011100110;
    cactussprite3[21] = 13'b0110011100110;
    cactussprite3[22] = 13'b0110011100110;
    cactussprite3[23] = 13'b0110011100110;
    cactussprite3[24] = 13'b0110011100110;
    cactussprite3[25] = 13'b0110011100110;
    cactussprite3[26] = 13'b0110011100110;
    cactussprite3[27] = 13'b0111111111110;
    cactussprite3[28] = 13'b0111111111100;
    cactussprite3[29] = 13'b0111111111100;
    cactussprite3[30] = 13'b0011111111000;
    cactussprite3[31] = 13'b0011111100000;
    cactussprite3[32] = 13'b0000011100000;
    cactussprite3[33] = 13'b0000011100000;
    cactussprite3[34] = 13'b0000011100000;
    cactussprite3[35] = 13'b0000011100000;
    cactussprite3[36] = 13'b0000011100000;
    cactussprite3[37] = 13'b0000011100000;
    cactussprite3[38] = 13'b0000011100000;
    cactussprite3[39] = 13'b0000011100000;
    cactussprite3[40] = 13'b0000011100000;
    cactussprite3[41] = 13'b0000011100000;
    cactussprite3[42] = 13'b0000011100000;
    cactussprite3[43] = 13'b0000011100000;
    cactussprite3[44] = 13'b0000011100000;
    cactussprite3[45] = 13'b0000011100000;
    cactussprite3[46] = 13'b0000111100000;
    cactussprite3[47] = 13'b0000000000000;
    cactussprite3[48] = 13'b0000000010000;
end

initial begin
    floor[0] = 255'b000000000000000000000000000000000000000000000000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011100000000000000000000000000000000000000000000;
    floor[1] = 255'b111111111111111111111111111111111111111111111111111111111111111111111111111111110011111000111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100111110001111111111111111111111111111111111111;
    floor[2] = 255'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111000000000000000000000000000000000000;
    floor[3] = 255'b000000001000000000000010000000000000001101100000010000000000010000000000000000000000010000001000000000010000000000000000000000100000000010000000000000100000000000000011011000000100000000000100000000000000000000000100000010000000000100000000000000000000001;
    floor[4] = 255'b010000000000001000000000000100000000000000000000000000000000000001000010000000000100000000000010000000001000000001000100010000000100000000000010000000000001000000000000000000000000000000000000010000100000000001000000000000100000000010000000010001000100000;
    floor[5] = 255'b001100000000000000000000000001000000000000000000100100000001100000000000000000000000000000000000000000000000000000000000000000000011000000000000000000000000010000000000000000001001000000011000000000000000000000000000000000000000000000000000000000000000000;
end

endmodule
module rendering (
    output wire pixel,
    output wire collision,
    output reg [2:0] cactus_select,

    input wire game_over,
    input wire game_start_blink,
    input wire score_pixel,
    input wire dinosprite_num,

    input wire [2:0] cactus_type,
    input wire [6:0] jump_pos,
    input wire [9:0] vaddr,
    input wire [9:0] haddr,
    input wire [10:0] scrolladdr,

    input wire clk,
    input wire sys_rst
);



reg [22:0]  dinosprite1[46:0];
reg [22:0]  dinosprite2[46:0];
reg [22:0]  dinospritedead[46:0];
reg [255:0] floor[5:0];
reg [26:0]  cactussprite1[46:0];
reg [26:0]  cactussprite2[46:0];
reg [12:0]  cactussprite3[48:0];

reg [4:0] layers;

assign pixel = |{score_pixel, layers};
assign collision = layers[0] & (layers[1] | layers[3] | layers[4]);

wire [7:0] flooraddr = haddr+scrolladdr;

always @(posedge clk) begin
    if (sys_rst) begin
        layers <= 0;
        cactus_select <= 0;
    end
    else begin
        layers <= 0;

        if (vaddr < 480 && haddr < 640) begin
            if (haddr > 30 && haddr < 75 && (vaddr + jump_pos) > 155 && (vaddr + jump_pos) < 248 && game_start_blink) begin

                if (game_over) begin
                    layers[0] <= dinospritedead[(vaddr-155+jump_pos) >> 1][(haddr-30) >> 1];
                end
                else begin
                    if (dinosprite_num) begin
                        layers[0] <= dinosprite1[(vaddr-155+jump_pos) >> 1][(haddr-30) >> 1];
                    end
                    else begin
                        layers[0] <= dinosprite2[(vaddr-155+jump_pos) >> 1][(haddr-30) >> 1];
                    end
                end
            end
            if (vaddr > 244 && vaddr < 251) begin
                layers[2] <= floor[vaddr-245][flooraddr];
            end
            if (vaddr > 203 && vaddr < 250) begin
                if (cactus_select[0]) begin
                    if (cactus_type[0]) begin
                        if ((haddr + scrolladdr[9:0]) > 640 && (haddr + scrolladdr[9:0]) < 667) begin
                            layers[1] <= cactussprite1[vaddr-203][haddr-640+scrolladdr[9:0]];
                        end
                    end
                    else begin
                        if ((haddr + scrolladdr[9:0]) > 640 && (haddr + scrolladdr[9:0]) < 667) begin
                            layers[1] <= cactussprite2[vaddr-203][haddr-640+scrolladdr[9:0]];
                        end
                    end
                end
                if (cactus_select[1]) begin
                    if (cactus_type[1]) begin
                        if ((haddr + scrolladdr[9:0]-250) > 640 && (haddr + scrolladdr[9:0]-250) < 667) begin
                            layers[3] <= cactussprite2[vaddr-203][haddr-640+scrolladdr[9:0]-250];
                        end
                    end
                end
                if (cactus_select[2]) begin
                    if (cactus_type[2]) begin
                        if ((haddr + scrolladdr[10:0]-450) > 640 && (haddr + scrolladdr[10:0]-450) < 667) begin
                            layers[4] <= cactussprite1[vaddr-203][haddr-640+scrolladdr[10:0]-450];
                        end
                    end
                    else begin
                        if ((haddr + scrolladdr[10:0]-450) > 640 && (haddr + scrolladdr[10:0]-450) < 667) begin
                            layers[4] <= cactussprite3[vaddr-203][haddr-640+scrolladdr[10:0]-450];
                        end
                    end
                end
            end

            if (scrolladdr[9:0] >= 0 && scrolladdr[9:0] < 10) begin
                cactus_select[0] <= 1;
            end
            else if (scrolladdr[9:0] > 667) begin
                cactus_select[0] <= 0;
            end

            if (scrolladdr[9:0] >= 250 && scrolladdr[9:0] < 260) begin
                cactus_select[1] <= 1;
            end
            else if (scrolladdr[9:0] > 917) begin
                cactus_select[1] <= 0;
            end

            if (scrolladdr[9:0] >= 450 && scrolladdr[9:0] < 460) begin
                cactus_select[2] <= 1;
            end
            else if (scrolladdr[10:0] > 1117) begin
                cactus_select[2] <= 0;
            end

        end
    end
end

initial begin
    dinosprite1[0]  = 22'b0000000000000000000000;
    dinosprite1[1]  = 22'b0000000000000000000000;
    dinosprite1[2]  = 22'b0000000000000000000000;
    dinosprite1[3]  = 22'b0000000000000000000000;
    dinosprite1[4]  = 22'b0000000000000000000000;
    dinosprite1[5]  = 22'b0000000000000000000000;
    dinosprite1[6]  = 22'b0000000000000000000000;
    dinosprite1[7]  = 22'b0000000000000000000000;
    dinosprite1[8]  = 22'b0000000000000000000000;
    dinosprite1[9]  = 22'b0000000000000000000000;
    dinosprite1[10] = 22'b0000000000000000000000;
    dinosprite1[11] = 22'b0000000000000000000000;
    dinosprite1[12] = 22'b0000000000000000000000;
    dinosprite1[13] = 22'b0000000000000000000000;
    dinosprite1[14] = 22'b0000000000000000000000;
    dinosprite1[15] = 22'b0000000000000000000000;
    dinosprite1[16] = 22'b0000000000000000000000;
    dinosprite1[17] = 22'b0000000000000000000000;
    dinosprite1[18] = 22'b0000000000000000000000;
    dinosprite1[19] = 22'b0000000000000000000000;
    dinosprite1[20] = 22'b0000000000000000000000;
    dinosprite1[21] = 22'b0000000000000000000000;
    dinosprite1[22] = 22'b0000000000000000000000;
    dinosprite1[23] = 22'b0011111111000000000000;
    dinosprite1[24] = 22'b0111111111100000000000;
    dinosprite1[25] = 22'b0111111101100000000000;
    dinosprite1[26] = 22'b0111111111100000000000;
    dinosprite1[27] = 22'b0111111111100000000000;
    dinosprite1[28] = 22'b0111111111100000000000;
    dinosprite1[29] = 22'b0000001111100000000000;
    dinosprite1[30] = 22'b0001111111100000000000;
    dinosprite1[31] = 22'b0000000111110000000010;
    dinosprite1[32] = 22'b0000000111111100000010;
    dinosprite1[33] = 22'b0000011111111110000110;
    dinosprite1[34] = 22'b0000010111111111001110;
    dinosprite1[35] = 22'b0000000111111111111110;
    dinosprite1[36] = 22'b0000000111111111111110;
    dinosprite1[37] = 22'b0000000011111111111100;
    dinosprite1[38] = 22'b0000000011111111111000;
    dinosprite1[39] = 22'b0000000001111111110000;
    dinosprite1[40] = 22'b0000000000111111100000;
    dinosprite1[41] = 22'b0000000000110011000000;
    dinosprite1[42] = 22'b0000000000100110000000;
    dinosprite1[43] = 22'b0000000000100000000000;
    dinosprite1[44] = 22'b0000000001100000000000;
    dinosprite1[45] = 22'b0000000000000000000000;
    dinosprite1[46] = 22'b0000000000000000000000;
end

initial begin
    dinosprite2[0]  = 22'b0000000000000000000000;
    dinosprite2[1]  = 22'b0000000000000000000000;
    dinosprite2[2]  = 22'b0000000000000000000000;
    dinosprite2[3]  = 22'b0000000000000000000000;
    dinosprite2[4]  = 22'b0000000000000000000000;
    dinosprite2[5]  = 22'b0000000000000000000000;
    dinosprite2[6]  = 22'b0000000000000000000000;
    dinosprite2[7]  = 22'b0000000000000000000000;
    dinosprite2[8]  = 22'b0000000000000000000000;
    dinosprite2[9]  = 22'b0000000000000000000000;
    dinosprite2[10] = 22'b0000000000000000000000;
    dinosprite2[11] = 22'b0000000000000000000000;
    dinosprite2[12] = 22'b0000000000000000000000;
    dinosprite2[13] = 22'b0000000000000000000000;
    dinosprite2[14] = 22'b0000000000000000000000;
    dinosprite2[15] = 22'b0000000000000000000000;
    dinosprite2[16] = 22'b0000000000000000000000;
    dinosprite2[17] = 22'b0000000000000000000000;
    dinosprite2[18] = 22'b0000000000000000000000;
    dinosprite2[19] = 22'b0000000000000000000000;
    dinosprite2[20] = 22'b0000000000000000000000;
    dinosprite2[21] = 22'b0000000000000000000000;
    dinosprite2[22] = 22'b0000000000000000000000;
    dinosprite2[23] = 22'b0011111111000000000000;
    dinosprite2[24] = 22'b0111111111100000000000;
    dinosprite2[25] = 22'b0111111101100000000000;
    dinosprite2[26] = 22'b0111111111100000000000;
    dinosprite2[27] = 22'b0111111111100000000000;
    dinosprite2[28] = 22'b0111111111100000000000;
    dinosprite2[29] = 22'b0000001111100000000000;
    dinosprite2[30] = 22'b0001111111100000000000;
    dinosprite2[31] = 22'b0000000111110000000010;
    dinosprite2[32] = 22'b0000000111111100000010;
    dinosprite2[33] = 22'b0000011111111110000110;
    dinosprite2[34] = 22'b0000010111111111001110;
    dinosprite2[35] = 22'b0000000111111111111110;
    dinosprite2[36] = 22'b0000000111111111111110;
    dinosprite2[37] = 22'b0000000011111111111100;
    dinosprite2[38] = 22'b0000000011111111111000;
    dinosprite2[39] = 22'b0000000001111111110000;
    dinosprite2[40] = 22'b0000000000111111100000;
    dinosprite2[41] = 22'b0000000001100111000000;
    dinosprite2[42] = 22'b0000000000000011000000;
    dinosprite2[43] = 22'b0000000000000011000000;
    dinosprite2[44] = 22'b0000000000000011000000;
    dinosprite2[45] = 22'b0000000000000000000000;
    dinosprite2[46] = 22'b0000000000000000000000;
end

initial begin
    dinospritedead[0]  = 22'b0000000000000000000000;
    dinospritedead[1]  = 22'b0000000000000000000000;
    dinospritedead[2]  = 22'b0000000000000000000000;
    dinospritedead[3]  = 22'b0000000000000000000000;
    dinospritedead[4]  = 22'b0000000000000000000000;
    dinospritedead[5]  = 22'b0000000000000000000000;
    dinospritedead[6]  = 22'b0000000000000000000000;
    dinospritedead[7]  = 22'b0000000000000000000000;
    dinospritedead[8]  = 22'b0000000000000000000000;
    dinospritedead[9]  = 22'b0000000000000000000000;
    dinospritedead[10] = 22'b0000000000000000000000;
    dinospritedead[11] = 22'b0000000000000000000000;
    dinospritedead[12] = 22'b0000000000000000000000;
    dinospritedead[13] = 22'b0000000000000000000000;
    dinospritedead[14] = 22'b0000000000000000000000;
    dinospritedead[15] = 22'b0000000000000000000000;
    dinospritedead[16] = 22'b0000000000000000000000;
    dinospritedead[17] = 22'b0000000000000000000000;
    dinospritedead[18] = 22'b0000000000000000000000;
    dinospritedead[19] = 22'b0000000000000000000000;
    dinospritedead[20] = 22'b0000000000000000000000;
    dinospritedead[21] = 22'b0000000000000000000000;
    dinospritedead[22] = 22'b0000000000000000000000;
    dinospritedead[23] = 22'b0011111111000000000000;
    dinospritedead[24] = 22'b0111111111100000000000;
    dinospritedead[25] = 22'b0111111101100000000000;
    dinospritedead[26] = 22'b0111111111100000000000;
    dinospritedead[27] = 22'b0111111111100000000000;
    dinospritedead[28] = 22'b0111111111100000000000;
    dinospritedead[29] = 22'b0111111111100000000000;
    dinospritedead[30] = 22'b0001111111100000000000;
    dinospritedead[31] = 22'b0000000111110000000010;
    dinospritedead[32] = 22'b0000000111111100000010;
    dinospritedead[33] = 22'b0000011111111110000110;
    dinospritedead[34] = 22'b0000010111111111001110;
    dinospritedead[35] = 22'b0000000111111111111110;
    dinospritedead[36] = 22'b0000000111111111111110;
    dinospritedead[37] = 22'b0000000011111111111100;
    dinospritedead[38] = 22'b0000000011111111111000;
    dinospritedead[39] = 22'b0000000001111111110000;
    dinospritedead[40] = 22'b0000000000111111100000;
    dinospritedead[41] = 22'b0000000000110111000000;
    dinospritedead[42] = 22'b0000000000100011000000;
    dinospritedead[43] = 22'b0000000000100001000000;
    dinospritedead[44] = 22'b0000000001100011000000;
    dinospritedead[45] = 22'b0000000000000000000000;
    dinospritedead[46] = 22'b0000000000000000000000;
end

initial begin
    cactussprite1[0]  = 26'b00000000000000000011000000;
    cactussprite1[1]  = 26'b00000000000000000011100000;
    cactussprite1[2]  = 26'b00001000000000000011100000;
    cactussprite1[3]  = 26'b00001100000000000011100000;
    cactussprite1[4]  = 26'b00001100000000000011100000;
    cactussprite1[5]  = 26'b00001100000000000011100000;
    cactussprite1[6]  = 26'b00001100000000100011100000;
    cactussprite1[7]  = 26'b00001100000000110011100000;
    cactussprite1[8]  = 26'b00001100100000110011100000;
    cactussprite1[9]  = 26'b00001100100000110011100000;
    cactussprite1[10] = 26'b00001100100000110011100000;
    cactussprite1[11] = 26'b00001100100000110011100100;
    cactussprite1[12] = 26'b00001100100000110011100110;
    cactussprite1[13] = 26'b00001100100000110011100110;
    cactussprite1[14] = 26'b00001100100000110011100110;
    cactussprite1[15] = 26'b00001100100000110011100110;
    cactussprite1[16] = 26'b01001100100000110011100110;
    cactussprite1[17] = 26'b01001111100000110011100110;
    cactussprite1[18] = 26'b01001111000000110011100110;
    cactussprite1[19] = 26'b01001111000000110011100110;
    cactussprite1[20] = 26'b01001100001000111111100110;
    cactussprite1[21] = 26'b01001100001000111111100110;
    cactussprite1[22] = 26'b01001100001000111111100110;
    cactussprite1[23] = 26'b01001100001000011111100110;
    cactussprite1[24] = 26'b01001100001000011111100110;
    cactussprite1[25] = 26'b01001100101001000011100110;
    cactussprite1[26] = 26'b01001100101001000011100100;
    cactussprite1[27] = 26'b01001100101001000011111100;
    cactussprite1[28] = 26'b01001100101001000011111000;
    cactussprite1[29] = 26'b01111100101001000011111000;
    cactussprite1[30] = 26'b01111100101001000011100000;
    cactussprite1[31] = 26'b00111100101001000011100000;
    cactussprite1[32] = 26'b00111100101001000011100000;
    cactussprite1[33] = 26'b00001100101001000011100000;
    cactussprite1[34] = 26'b00001100111110000011100000;
    cactussprite1[35] = 26'b00001100011110000011100000;
    cactussprite1[36] = 26'b00001100011000000011100000;
    cactussprite1[37] = 26'b00001100001000000011100000;
    cactussprite1[38] = 26'b00001100001000000011100000;
    cactussprite1[39] = 26'b00001100001000000011100000;
    cactussprite1[40] = 26'b00001100001000000011100000;
    cactussprite1[41] = 26'b00001100001000000011100000;
    cactussprite1[42] = 26'b00001100001000000011100000;
    cactussprite1[43] = 26'b00001100001000000011100000;
    cactussprite1[44] = 26'b00001100001000000011100000;
    cactussprite1[45] = 26'b00001100001000000011100000;
    cactussprite1[46] = 26'b00001100001000000111100000;
end

initial begin
    cactussprite2[0]  = 13'b0000000000000;
    cactussprite2[1]  = 13'b0000001000000;
    cactussprite2[2]  = 13'b0000011100000;
    cactussprite2[3]  = 13'b0000011100000;
    cactussprite2[4]  = 13'b0000011100000;
    cactussprite2[5]  = 13'b0000011100000;
    cactussprite2[6]  = 13'b0100011100000;
    cactussprite2[7]  = 13'b0110011100000;
    cactussprite2[8]  = 13'b0110011100000;
    cactussprite2[9]  = 13'b0110011100000;
    cactussprite2[10] = 13'b0110011100000;
    cactussprite2[11] = 13'b0110011100100;
    cactussprite2[12] = 13'b0110011100110;
    cactussprite2[13] = 13'b0110011100110;
    cactussprite2[14] = 13'b0110011100110;
    cactussprite2[15] = 13'b0110011100110;
    cactussprite2[16] = 13'b0110011100110;
    cactussprite2[17] = 13'b0110011100110;
    cactussprite2[18] = 13'b0110011100110;
    cactussprite2[19] = 13'b0110011100110;
    cactussprite2[20] = 13'b0110011100110;
    cactussprite2[21] = 13'b0111111100110;
    cactussprite2[22] = 13'b0111111100110;
    cactussprite2[23] = 13'b0011111100110;
    cactussprite2[24] = 13'b0011111100110;
    cactussprite2[25] = 13'b0001111100110;
    cactussprite2[26] = 13'b0000011100110;
    cactussprite2[27] = 13'b0000011111100;
    cactussprite2[28] = 13'b0000011111100;
    cactussprite2[29] = 13'b0000011111000;
    cactussprite2[30] = 13'b0000011111000;
    cactussprite2[31] = 13'b0000011100000;
    cactussprite2[32] = 13'b0000011100000;
    cactussprite2[33] = 13'b0000011100000;
    cactussprite2[34] = 13'b0000011100000;
    cactussprite2[35] = 13'b0000011100000;
    cactussprite2[36] = 13'b0000011100000;
    cactussprite2[37] = 13'b0000011100000;
    cactussprite2[38] = 13'b0000011100000;
    cactussprite2[39] = 13'b0000011100000;
    cactussprite2[40] = 13'b0000011100000;
    cactussprite2[41] = 13'b0000011100000;
    cactussprite2[42] = 13'b0000011100000;
    cactussprite2[43] = 13'b0000011100000;
    cactussprite2[44] = 13'b0000011100000;
    cactussprite2[45] = 13'b0000011100000;
    cactussprite2[46] = 13'b0000111100000;
end

initial begin
    cactussprite3[0]  = 13'b0000000000000;
    cactussprite3[1]  = 13'b0000001100000;
    cactussprite3[2]  = 13'b0000011100000;
    cactussprite3[3]  = 13'b0000011100000;
    cactussprite3[4]  = 13'b0000011100000;
    cactussprite3[5]  = 13'b0000011100000;
    cactussprite3[6]  = 13'b0000011100000;
    cactussprite3[7]  = 13'b0000011100000;
    cactussprite3[8]  = 13'b0000011100000;
    cactussprite3[9]  = 13'b0000011100000;
    cactussprite3[10] = 13'b0000011100000;
    cactussprite3[11] = 13'b0000011100110;
    cactussprite3[12] = 13'b0000011100110;
    cactussprite3[13] = 13'b0110011100110;
    cactussprite3[14] = 13'b0110011100110;
    cactussprite3[15] = 13'b0110011100110;
    cactussprite3[16] = 13'b0110011100110;
    cactussprite3[17] = 13'b0110011100110;
    cactussprite3[18] = 13'b0110011100110;
    cactussprite3[19] = 13'b0110011100110;
    cactussprite3[20] = 13'b0110011100110;
    cactussprite3[21] = 13'b0110011100110;
    cactussprite3[22] = 13'b0110011100110;
    cactussprite3[23] = 13'b0110011100110;
    cactussprite3[24] = 13'b0110011100110;
    cactussprite3[25] = 13'b0110011100110;
    cactussprite3[26] = 13'b0110011100110;
    cactussprite3[27] = 13'b0111111111110;
    cactussprite3[28] = 13'b0111111111100;
    cactussprite3[29] = 13'b0111111111100;
    cactussprite3[30] = 13'b0011111111000;
    cactussprite3[31] = 13'b0011111100000;
    cactussprite3[32] = 13'b0000011100000;
    cactussprite3[33] = 13'b0000011100000;
    cactussprite3[34] = 13'b0000011100000;
    cactussprite3[35] = 13'b0000011100000;
    cactussprite3[36] = 13'b0000011100000;
    cactussprite3[37] = 13'b0000011100000;
    cactussprite3[38] = 13'b0000011100000;
    cactussprite3[39] = 13'b0000011100000;
    cactussprite3[40] = 13'b0000011100000;
    cactussprite3[41] = 13'b0000011100000;
    cactussprite3[42] = 13'b0000011100000;
    cactussprite3[43] = 13'b0000011100000;
    cactussprite3[44] = 13'b0000011100000;
    cactussprite3[45] = 13'b0000011100000;
    cactussprite3[46] = 13'b0000111100000;
    cactussprite3[47] = 13'b0000000000000;
    cactussprite3[48] = 13'b0000000010000;
end

initial begin
    floor[0] = 255'b000000000000000000000000000000000000000000000000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011100000000000000000000000000000000000000000000;
    floor[1] = 255'b111111111111111111111111111111111111111111111111111111111111111111111111111111110011111000111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100111110001111111111111111111111111111111111111;
    floor[2] = 255'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111000000000000000000000000000000000000;
    floor[3] = 255'b000000001000000000000010000000000000001101100000010000000000010000000000000000000000010000001000000000010000000000000000000000100000000010000000000000100000000000000011011000000100000000000100000000000000000000000100000010000000000100000000000000000000001;
    floor[4] = 255'b010000000000001000000000000100000000000000000000000000000000000001000010000000000100000000000010000000001000000001000100010000000100000000000010000000000001000000000000000000000000000000000000010000100000000001000000000000100000000010000000010001000100000;
    floor[5] = 255'b001100000000000000000000000001000000000000000000100100000001100000000000000000000000000000000000000000000000000000000000000000000011000000000000000000000000010000000000000000001001000000011000000000000000000000000000000000000000000000000000000000000000000;
end

endmodule