data/full_repos/permissive/423547971/College Coursework/Digital Design II Final Project/light_fsm2.v
1: b'%Error: Cannot find file containing module: Coursework/Digital\n        ... Looked in:\n             data/full_repos/permissive/423547971/College/Coursework/Digital\n             data/full_repos/permissive/423547971/College/Coursework/Digital.v\n             data/full_repos/permissive/423547971/College/Coursework/Digital.sv\n             Coursework/Digital\n             Coursework/Digital.v\n             Coursework/Digital.sv\n             obj_dir/Coursework/Digital\n             obj_dir/Coursework/Digital.v\n             obj_dir/Coursework/Digital.sv\n%Error: Cannot find file containing module: Design\n%Error: Cannot find file containing module: II\n%Error: Cannot find file containing module: Final\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/College\n%Error: Cannot find file containing module: Project/light_fsm2.v\n%Error: Exiting due to 7 error(s)\n'
module light_fsm2(
	output A,
	output B,
	output C,
	output en_countdown_Ms,

	input RESET,
	input ENABLE,
	input CLOCK
);

reg [2:0] current_state = 0 ;
reg [2:0] next_state ;
reg en_countdown_Ms;

wire A, B, C ;

parameter S0=3'b000, S1=3'b001, S2=3'b010, S3=3'b011, S4=3'b100;
	  

always @(posedge CLOCK or posedge RESET)
 begin
  if(RESET)
	begin
		current_state <= S0 ;
	end
  else if(ENABLE == 0)
	begin
		current_state <= current_state ;
	end	
  else
	begin
		current_state <= next_state ;
	end	
end

assign A = current_state[0] ;
assign B = current_state[1] ;
assign C = current_state[2] ;
 

always @(*) 
begin
	
	case (current_state)
		S0: begin
			en_countdown_Ms = 0;
			next_state = S1 ;
			end
		   
		S1: begin
			en_countdown_Ms = 0;
			next_state = S2 ;
			end	
			
		S2: begin
			en_countdown_Ms = 0;
			next_state = S3 ;
			end
			
		S3: begin
			en_countdown_Ms = 1;
			next_state = S4 ;
			end
	
		S4: begin
			en_countdown_Ms = 1;
			next_state = S0 ;
			end

		default:
			begin
			en_countdown_Ms = 0;
	        next_state = S0 ;
			end
	endcase
end 
endmodule
module light_fsm2(
	output A,
	output B,
	output C,
	output en_countdown_Ms,

	input RESET,
	input ENABLE,
	input CLOCK
);


reg [2:0] current_state = 0 ;
reg [2:0] next_state ;
reg en_countdown_Ms;

wire A, B, C ;

parameter S0=3'b000, S1=3'b001, S2=3'b010, S3=3'b011, S4=3'b100;
	  

always @(posedge CLOCK or posedge RESET)
 begin
  if(RESET)
	begin
		current_state <= S0 ;
	end
  else if(ENABLE == 0)
	begin
		current_state <= current_state ;
	end	
  else
	begin
		current_state <= next_state ;
	end	
end

assign A = current_state[0] ;
assign B = current_state[1] ;
assign C = current_state[2] ;
 

always @(*) 
begin
	
	case (current_state)
		S0: begin
			en_countdown_Ms = 0;
			next_state = S1 ;
			end
		   
		S1: begin
			en_countdown_Ms = 0;
			next_state = S2 ;
			end	
			
		S2: begin
			en_countdown_Ms = 0;
			next_state = S3 ;
			end
			
		S3: begin
			en_countdown_Ms = 1;
			next_state = S4 ;
			end
	
		S4: begin
			en_countdown_Ms = 1;
			next_state = S0 ;
			end

		default:
			begin
			en_countdown_Ms = 0;
	        next_state = S0 ;
			end
	endcase
end 
endmodule