data/full_repos/permissive/504478691/sound/square/sound.v
data/verilator_xmls/643549cd-455f-4e74-80f0-b8be87cac068.xml
module sound(input [31:0] f_dHz, input clk, output reg soundbit = 0);
reg [31:0] n = 0;

always @(posedge clk)
begin
    n = n + 1;
    if (n >= 500_000_000 / f_dHz)
    begin
        n = 1;
        soundbit = ~soundbit;
    end
end
endmodule
module sound(input [31:0] f_dHz, input clk, output reg soundbit = 0);

reg [31:0] n = 0;

always @(posedge clk)
begin
    n = n + 1;
    if (n >= 500_000_000 / f_dHz)
    begin
        n = 1;
        soundbit = ~soundbit;
    end
end
endmodule