data/full_repos/permissive/486367830/debug/core_debug/deb_src/comp_mult_ref_model.v
1: b'%Warning-WIDTH: data/full_repos/permissive/486367830/debug/core_debug/deb_src/comp_mult_ref_model.v:44: Unsized constant being X/Z extended to 36 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                      : ... In instance comp_mult_ref_model\n  res_data <= \'bx;\n              ^~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module comp_mult_ref_model (
input                        clk       ,
input                        rst_n     ,

input                        op_val    ,
output reg                   op_rdy    ,
input      [2 * 2 * 8 - 1:0] op_data   ,

output reg                   res_val   ,
input                        res_rdy   ,
output reg [2 * 18    - 1:0] res_data
);

wire signed [8  - 1:0] x1, y1, x2, y2 ;
wire signed [18 - 1:0] re;
wire signed [18 - 1:0] im;
assign {x1, y1, x2, y2} = op_data;
assign re = x1 * x2 - y1 * y2;
assign im = x1 * y2 + y1 * x2;
  
always @(posedge clk)
op_rdy <= 1'b1;

always @(posedge clk)
if (op_val & op_rdy) begin
  res_val <= 1'b1;
  res_data <= {re, im};
end
else begin
  res_val <= 1'b0;
  res_data <= 'bx;
end

endmodule
module comp_mult_ref_model (
input                        clk       ,
input                        rst_n     ,

input                        op_val    ,
output reg                   op_rdy    ,
input      [2 * 2 * 8 - 1:0] op_data   ,

output reg                   res_val   ,
input                        res_rdy   ,
output reg [2 * 18    - 1:0] res_data
);


wire signed [8  - 1:0] x1, y1, x2, y2 ;
wire signed [18 - 1:0] re;
wire signed [18 - 1:0] im;
assign {x1, y1, x2, y2} = op_data;
assign re = x1 * x2 - y1 * y2;
assign im = x1 * y2 + y1 * x2;
  
always @(posedge clk)
op_rdy <= 1'b1;

always @(posedge clk)
if (op_val & op_rdy) begin
  res_val <= 1'b1;
  res_data <= {re, im};
end
else begin
  res_val <= 1'b0;
  res_data <= 'bx;
end

endmodule