data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/controller.sv
1: b"%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/controller.sv:16: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER\nmodule controller import ariane_pkg::*; (\n                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/controller.sv:18: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic            rst_ni,\n    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/controller.sv:19: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic            set_pc_commit_o,         \n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/controller.sv:20: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic            flush_if_o,              \n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/controller.sv:21: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic            flush_unissued_instr_o,  \n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/controller.sv:22: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic            flush_id_o,              \n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/controller.sv:23: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic            flush_ex_o,              \n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/controller.sv:24: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic            flush_bp_o,              \n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/controller.sv:25: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic            flush_icache_o,          \n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/controller.sv:26: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic            flush_dcache_o,          \n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/controller.sv:27: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic            flush_dcache_ack_i,      \n    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/controller.sv:28: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic            flush_tlb_o,             \n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/controller.sv:30: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic            halt_csr_i,              \n    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/controller.sv:31: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic            halt_o,                  \n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/controller.sv:32: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic            eret_i,                  \n    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/controller.sv:33: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic            ex_valid_i,              \n    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/controller.sv:34: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic            set_debug_pc_i,          \n    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/controller.sv:35: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  bp_resolve_t     resolved_branch_i,       \n    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/controller.sv:37: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic            fence_i_i,               \n    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/controller.sv:38: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic            fence_i,                 \n    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/controller.sv:39: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic            sfence_vma_i,            \n    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/controller.sv:40: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic            flush_commit_i           \n    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/controller.sv:50: syntax error, unexpected always_comb\n    always_comb begin : flush_ctrl\n    ^~~~~~~~~~~\n%Error: Exiting due to 23 error(s)\n"
module controller import ariane_pkg::*; (
    input  logic            clk_i,
    input  logic            rst_ni,
    output logic            set_pc_commit_o,
    output logic            flush_if_o,
    output logic            flush_unissued_instr_o,
    output logic            flush_id_o,
    output logic            flush_ex_o,
    output logic            flush_bp_o,
    output logic            flush_icache_o,
    output logic            flush_dcache_o,
    input  logic            flush_dcache_ack_i,
    output logic            flush_tlb_o,

    input  logic            halt_csr_i,
    output logic            halt_o,
    input  logic            eret_i,
    input  logic            ex_valid_i,
    input  logic            set_debug_pc_i,
    input  bp_resolve_t     resolved_branch_i,
    input  logic            flush_csr_i,
    input  logic            fence_i_i,
    input  logic            fence_i,
    input  logic            sfence_vma_i,
    input  logic            flush_commit_i
);


    logic fence_active_d, fence_active_q;
    logic flush_dcache;




    always_comb begin : flush_ctrl
        fence_active_d         = fence_active_q;
        set_pc_commit_o        = 1'b0;
        flush_if_o             = 1'b0;
        flush_unissued_instr_o = 1'b0;
        flush_id_o             = 1'b0;
        flush_ex_o             = 1'b0;
        flush_dcache           = 1'b0;
        flush_icache_o         = 1'b0;
        flush_tlb_o            = 1'b0;
        flush_bp_o             = 1'b0;




        if (resolved_branch_i.is_mispredict) begin

            flush_unissued_instr_o = 1'b1;

            flush_if_o             = 1'b1;
        end




        if (fence_i) begin

            set_pc_commit_o        = 1'b1;
            flush_if_o             = 1'b1;
            flush_unissued_instr_o = 1'b1;
            flush_id_o             = 1'b1;
            flush_ex_o             = 1'b1;


`ifndef WT_DCACHE
            flush_dcache           = 1'b1;
            fence_active_d         = 1'b1;
`endif
        end




        if (fence_i_i) begin
            set_pc_commit_o        = 1'b1;
            flush_if_o             = 1'b1;
            flush_unissued_instr_o = 1'b1;
            flush_id_o             = 1'b1;
            flush_ex_o             = 1'b1;
            flush_icache_o         = 1'b1;


`ifndef WT_DCACHE
            flush_dcache           = 1'b1;
            fence_active_d         = 1'b1;
`endif
        end



`ifndef WT_DCACHE

        if (flush_dcache_ack_i && fence_active_q) begin
            fence_active_d = 1'b0;

        end else if (fence_active_q) begin
            flush_dcache = 1'b1;
        end
`endif



        if (sfence_vma_i) begin
            set_pc_commit_o        = 1'b1;
            flush_if_o             = 1'b1;
            flush_unissued_instr_o = 1'b1;
            flush_id_o             = 1'b1;
            flush_ex_o             = 1'b1;

            flush_tlb_o            = 1'b1;
        end


        if (flush_csr_i || flush_commit_i) begin
            set_pc_commit_o        = 1'b1;
            flush_if_o             = 1'b1;
            flush_unissued_instr_o = 1'b1;
            flush_id_o             = 1'b1;
            flush_ex_o             = 1'b1;
        end





        if (ex_valid_i || eret_i || set_debug_pc_i) begin


            set_pc_commit_o        = 1'b0;
            flush_if_o             = 1'b1;
            flush_unissued_instr_o = 1'b1;
            flush_id_o             = 1'b1;
            flush_ex_o             = 1'b1;




            flush_bp_o             = 1'b1;
        end
    end




    always_comb begin

        halt_o = halt_csr_i || fence_active_q;
    end




    always_ff @(posedge clk_i or negedge rst_ni) begin
        if (~rst_ni) begin
            fence_active_q <= 1'b0;
            flush_dcache_o <= 1'b0;
        end else begin
            fence_active_q <= fence_active_d;

            flush_dcache_o <= flush_dcache;
        end
    end
endmodule
module controller import ariane_pkg::*;
 (
    input  logic            clk_i,
    input  logic            rst_ni,
    output logic            set_pc_commit_o,
    output logic            flush_if_o,
    output logic            flush_unissued_instr_o,
    output logic            flush_id_o,
    output logic            flush_ex_o,
    output logic            flush_bp_o,
    output logic            flush_icache_o,
    output logic            flush_dcache_o,
    input  logic            flush_dcache_ack_i,
    output logic            flush_tlb_o,

    input  logic            halt_csr_i,
    output logic            halt_o,
    input  logic            eret_i,
    input  logic            ex_valid_i,
    input  logic            set_debug_pc_i,
    input  bp_resolve_t     resolved_branch_i,
    input  logic            flush_csr_i,
    input  logic            fence_i_i,
    input  logic            fence_i,
    input  logic            sfence_vma_i,
    input  logic            flush_commit_i
);


    logic fence_active_d, fence_active_q;
    logic flush_dcache;




    always_comb begin : flush_ctrl
        fence_active_d         = fence_active_q;
        set_pc_commit_o        = 1'b0;
        flush_if_o             = 1'b0;
        flush_unissued_instr_o = 1'b0;
        flush_id_o             = 1'b0;
        flush_ex_o             = 1'b0;
        flush_dcache           = 1'b0;
        flush_icache_o         = 1'b0;
        flush_tlb_o            = 1'b0;
        flush_bp_o             = 1'b0;




        if (resolved_branch_i.is_mispredict) begin

            flush_unissued_instr_o = 1'b1;

            flush_if_o             = 1'b1;
        end




        if (fence_i) begin

            set_pc_commit_o        = 1'b1;
            flush_if_o             = 1'b1;
            flush_unissued_instr_o = 1'b1;
            flush_id_o             = 1'b1;
            flush_ex_o             = 1'b1;


`ifndef WT_DCACHE
            flush_dcache           = 1'b1;
            fence_active_d         = 1'b1;
`endif
        end




        if (fence_i_i) begin
            set_pc_commit_o        = 1'b1;
            flush_if_o             = 1'b1;
            flush_unissued_instr_o = 1'b1;
            flush_id_o             = 1'b1;
            flush_ex_o             = 1'b1;
            flush_icache_o         = 1'b1;


`ifndef WT_DCACHE
            flush_dcache           = 1'b1;
            fence_active_d         = 1'b1;
`endif
        end



`ifndef WT_DCACHE

        if (flush_dcache_ack_i && fence_active_q) begin
            fence_active_d = 1'b0;

        end else if (fence_active_q) begin
            flush_dcache = 1'b1;
        end
`endif



        if (sfence_vma_i) begin
            set_pc_commit_o        = 1'b1;
            flush_if_o             = 1'b1;
            flush_unissued_instr_o = 1'b1;
            flush_id_o             = 1'b1;
            flush_ex_o             = 1'b1;

            flush_tlb_o            = 1'b1;
        end


        if (flush_csr_i || flush_commit_i) begin
            set_pc_commit_o        = 1'b1;
            flush_if_o             = 1'b1;
            flush_unissued_instr_o = 1'b1;
            flush_id_o             = 1'b1;
            flush_ex_o             = 1'b1;
        end





        if (ex_valid_i || eret_i || set_debug_pc_i) begin


            set_pc_commit_o        = 1'b0;
            flush_if_o             = 1'b1;
            flush_unissued_instr_o = 1'b1;
            flush_id_o             = 1'b1;
            flush_ex_o             = 1'b1;




            flush_bp_o             = 1'b1;
        end
    end




    always_comb begin

        halt_o = halt_csr_i || fence_active_q;
    end




    always_ff @(posedge clk_i or negedge rst_ni) begin
        if (~rst_ni) begin
            fence_active_q <= 1'b0;
            flush_dcache_o <= 1'b0;
        end else begin
            fence_active_q <= fence_active_d;

            flush_dcache_o <= flush_dcache;
        end
    end
endmodule