data/full_repos/permissive/423412549/src/rtl/enemy_top.v
1: b'%Error: data/full_repos/permissive/423412549/src/rtl/enemy_top.v:9: Cannot find include file: ../header/define.v\n`include "../header/define.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423412549/src/rtl,data/full_repos/permissive/423412549/../header/define.v\n             data/full_repos/permissive/423412549/src/rtl,data/full_repos/permissive/423412549/../header/define.v.v\n             data/full_repos/permissive/423412549/src/rtl,data/full_repos/permissive/423412549/../header/define.v.sv\n             ../header/define.v\n             ../header/define.v.v\n             ../header/define.v.sv\n             obj_dir/../header/define.v\n             obj_dir/../header/define.v.v\n             obj_dir/../header/define.v.sv\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy_top.v:15: Define or directive not defined: \'`RAND_WIDTH\'\n    input  wire [         `RAND_WIDTH-1:0] rand_i,\n                          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy_top.v:17: Define or directive not defined: \'`H_DISP_LEN\'\n    input  wire [         `H_DISP_LEN-1:0] req_x_addr_i,\n                          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy_top.v:18: Define or directive not defined: \'`V_DISP_LEN\'\n    input  wire [         `V_DISP_LEN-1:0] req_y_addr_i,\n                          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy_top.v:24: Define or directive not defined: \'`COLOR_RGB_DEPTH\'\n    output wire [    `COLOR_RGB_DEPTH-1:0] vga_rgb_o,\n                     ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy_top.v:25: Define or directive not defined: \'`ADD_SCORE_BIT_WIDTH\'\n    output wire [`ADD_SCORE_BIT_WIDTH-1:0] add_score_o\n                 ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy_top.v:29: Define or directive not defined: \'`COLOR_RGB_DEPTH\'\n    wire [`COLOR_RGB_DEPTH-1:0] vga_rgb_enemy1_slow;\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy_top.v:31: Define or directive not defined: \'`COLOR_RGB_DEPTH\'\n    wire [`COLOR_RGB_DEPTH-1:0] vga_rgb_enemy2;\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy_top.v:33: Define or directive not defined: \'`COLOR_RGB_DEPTH\'\n    wire [`COLOR_RGB_DEPTH-1:0] vga_rgb_enemy3;\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy_top.v:34: Define or directive not defined: \'`ADD_SCORE_BIT_WIDTH\'\n    wire [`ADD_SCORE_BIT_WIDTH-1:0] add_score_enemy1_slow;\n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy_top.v:35: Define or directive not defined: \'`ADD_SCORE_BIT_WIDTH\'\n    wire [`ADD_SCORE_BIT_WIDTH-1:0] add_score_enemy2;\n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/enemy_top.v:36: Define or directive not defined: \'`ADD_SCORE_BIT_WIDTH\'\n    wire [`ADD_SCORE_BIT_WIDTH-1:0] add_score_enemy3;\n          ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 12 error(s)\n'
module enemy_top (
    input  wire                            clk_run,
    input  wire                            clk_vga,
    input  wire                            rst,
    input  wire                            en_i,
    input  wire [         `RAND_WIDTH-1:0] rand_i,
    input  wire                            v_sync_i,
    input  wire [         `H_DISP_LEN-1:0] req_x_addr_i,
    input  wire [         `V_DISP_LEN-1:0] req_y_addr_i,
    input  wire                            crash_enemy_bullet_i,
    input  wire                            crash_me_enemy_i,
    input  wire                            bomb_i,

    output wire                            vga_alpha_o,
    output wire [    `COLOR_RGB_DEPTH-1:0] vga_rgb_o,
    output wire [`ADD_SCORE_BIT_WIDTH-1:0] add_score_o
);

    wire                        vga_alpha_enemy1_slow;
    wire [`COLOR_RGB_DEPTH-1:0] vga_rgb_enemy1_slow;
    wire                        vga_alpha_enemy2;
    wire [`COLOR_RGB_DEPTH-1:0] vga_rgb_enemy2;
    wire                        vga_alpha_enemy3;
    wire [`COLOR_RGB_DEPTH-1:0] vga_rgb_enemy3;
    wire [`ADD_SCORE_BIT_WIDTH-1:0] add_score_enemy1_slow;
    wire [`ADD_SCORE_BIT_WIDTH-1:0] add_score_enemy2;
    wire [`ADD_SCORE_BIT_WIDTH-1:0] add_score_enemy3;

    enemy1_slow enemy1_slow_dut
    (
        .clk_run(clk_run),
        .clk_vga(clk_vga),
        .rst(rst),
        .en_i(en_i),
        .rand_i(rand_i),
        .v_sync_i(v_sync_i),
        .req_x_addr_i(req_x_addr_i),
        .req_y_addr_i(req_y_addr_i),
        .crash_enemy_bullet_i(crash_enemy_bullet_i & vga_alpha_enemy1_slow),
        .crash_me_enemy_i(crash_me_enemy_i & vga_alpha_enemy1_slow),
        .bomb_i(bomb_i),
        .vga_alpha_o(vga_alpha_enemy1_slow),
        .vga_rgb_o(vga_rgb_enemy1_slow),
        .add_score_o(add_score_enemy1_slow)
    );

    enemy2 enemy2_dut
    (
        .clk_run(clk_run),
        .clk_vga(clk_vga),
        .rst(rst),
        .en_i(en_i),
        .rand_i(rand_i),
        .v_sync_i(v_sync_i),
        .req_x_addr_i(req_x_addr_i),
        .req_y_addr_i(req_y_addr_i),
        .crash_enemy_bullet_i(crash_enemy_bullet_i & vga_alpha_enemy2),
        .crash_me_enemy_i(crash_me_enemy_i & vga_alpha_enemy2),
        .bomb_i(bomb_i),
        .vga_alpha_o(vga_alpha_enemy2),
        .vga_rgb_o(vga_rgb_enemy2),
        .add_score_o(add_score_enemy2)
    );

    enemy3 enemy3_dut
    (
        .clk_run(clk_run),
        .clk_vga(clk_vga),
        .rst(rst),
        .en_i(en_i),
        .rand_i(rand_i),
        .v_sync_i(v_sync_i),
        .req_x_addr_i(req_x_addr_i),
        .req_y_addr_i(req_y_addr_i),
        .crash_enemy_bullet_i(crash_enemy_bullet_i & vga_alpha_enemy3),
        .crash_me_enemy_i(crash_me_enemy_i & vga_alpha_enemy3),
        .bomb_i(bomb_i),
        .vga_alpha_o(vga_alpha_enemy3),
        .vga_rgb_o(vga_rgb_enemy3),
        .add_score_o(add_score_enemy3)
    );

    assign vga_alpha_o = vga_alpha_enemy1_slow | vga_alpha_enemy2 | vga_alpha_enemy3;
    assign vga_rgb_o = vga_alpha_enemy1_slow ? vga_rgb_enemy1_slow : 
                       vga_alpha_enemy2 ? vga_rgb_enemy2 : 
                       vga_alpha_enemy3 ? vga_rgb_enemy3 : 0;
    assign add_score_o = ~crash_me_enemy_i? add_score_enemy1_slow + add_score_enemy2 + add_score_enemy3 : 0;
endmodule
module enemy_top (
    input  wire                            clk_run,
    input  wire                            clk_vga,
    input  wire                            rst,
    input  wire                            en_i,
    input  wire [         `RAND_WIDTH-1:0] rand_i,
    input  wire                            v_sync_i,
    input  wire [         `H_DISP_LEN-1:0] req_x_addr_i,
    input  wire [         `V_DISP_LEN-1:0] req_y_addr_i,
    input  wire                            crash_enemy_bullet_i,
    input  wire                            crash_me_enemy_i,
    input  wire                            bomb_i,

    output wire                            vga_alpha_o,
    output wire [    `COLOR_RGB_DEPTH-1:0] vga_rgb_o,
    output wire [`ADD_SCORE_BIT_WIDTH-1:0] add_score_o
);


    wire                        vga_alpha_enemy1_slow;
    wire [`COLOR_RGB_DEPTH-1:0] vga_rgb_enemy1_slow;
    wire                        vga_alpha_enemy2;
    wire [`COLOR_RGB_DEPTH-1:0] vga_rgb_enemy2;
    wire                        vga_alpha_enemy3;
    wire [`COLOR_RGB_DEPTH-1:0] vga_rgb_enemy3;
    wire [`ADD_SCORE_BIT_WIDTH-1:0] add_score_enemy1_slow;
    wire [`ADD_SCORE_BIT_WIDTH-1:0] add_score_enemy2;
    wire [`ADD_SCORE_BIT_WIDTH-1:0] add_score_enemy3;

    enemy1_slow enemy1_slow_dut
    (
        .clk_run(clk_run),
        .clk_vga(clk_vga),
        .rst(rst),
        .en_i(en_i),
        .rand_i(rand_i),
        .v_sync_i(v_sync_i),
        .req_x_addr_i(req_x_addr_i),
        .req_y_addr_i(req_y_addr_i),
        .crash_enemy_bullet_i(crash_enemy_bullet_i & vga_alpha_enemy1_slow),
        .crash_me_enemy_i(crash_me_enemy_i & vga_alpha_enemy1_slow),
        .bomb_i(bomb_i),
        .vga_alpha_o(vga_alpha_enemy1_slow),
        .vga_rgb_o(vga_rgb_enemy1_slow),
        .add_score_o(add_score_enemy1_slow)
    );

    enemy2 enemy2_dut
    (
        .clk_run(clk_run),
        .clk_vga(clk_vga),
        .rst(rst),
        .en_i(en_i),
        .rand_i(rand_i),
        .v_sync_i(v_sync_i),
        .req_x_addr_i(req_x_addr_i),
        .req_y_addr_i(req_y_addr_i),
        .crash_enemy_bullet_i(crash_enemy_bullet_i & vga_alpha_enemy2),
        .crash_me_enemy_i(crash_me_enemy_i & vga_alpha_enemy2),
        .bomb_i(bomb_i),
        .vga_alpha_o(vga_alpha_enemy2),
        .vga_rgb_o(vga_rgb_enemy2),
        .add_score_o(add_score_enemy2)
    );

    enemy3 enemy3_dut
    (
        .clk_run(clk_run),
        .clk_vga(clk_vga),
        .rst(rst),
        .en_i(en_i),
        .rand_i(rand_i),
        .v_sync_i(v_sync_i),
        .req_x_addr_i(req_x_addr_i),
        .req_y_addr_i(req_y_addr_i),
        .crash_enemy_bullet_i(crash_enemy_bullet_i & vga_alpha_enemy3),
        .crash_me_enemy_i(crash_me_enemy_i & vga_alpha_enemy3),
        .bomb_i(bomb_i),
        .vga_alpha_o(vga_alpha_enemy3),
        .vga_rgb_o(vga_rgb_enemy3),
        .add_score_o(add_score_enemy3)
    );

    assign vga_alpha_o = vga_alpha_enemy1_slow | vga_alpha_enemy2 | vga_alpha_enemy3;
    assign vga_rgb_o = vga_alpha_enemy1_slow ? vga_rgb_enemy1_slow : 
                       vga_alpha_enemy2 ? vga_rgb_enemy2 : 
                       vga_alpha_enemy3 ? vga_rgb_enemy3 : 0;
    assign add_score_o = ~crash_me_enemy_i? add_score_enemy1_slow + add_score_enemy2 + add_score_enemy3 : 0;
endmodule