data/full_repos/permissive/459838989/rtl/f2m/f2m_inv.v
1: b'%Warning-WIDTH: data/full_repos/permissive/459838989/rtl/f2m/f2m_inv.v:53: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                         : ... In instance f2m_inv\n        cnt <= 1\'b0;\n            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/459838989/rtl/f2m/f2m_inv.v:55: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                         : ... In instance f2m_inv\n        cnt <= 1\'b0;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/459838989/rtl/f2m/f2m_inv.v:82: Operator ASSIGNDLY expects 164 bits on the Assign RHS, but Assign RHS\'s VARREF \'a\' generates 163 bits.\n                                                                         : ... In instance f2m_inv\n        r_r <= a;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/459838989/rtl/f2m/f2m_inv.v:96: Operator ASSIGNDLY expects 164 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                         : ... In instance f2m_inv\n        u_r <= 1\'b1;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/459838989/rtl/f2m/f2m_inv.v:103: Operator ASSIGNDLY expects 164 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                          : ... In instance f2m_inv\n        v_r <= 1\'b0;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/459838989/rtl/f2m/f2m_inv.v:110: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                          : ... In instance f2m_inv\n        d_r <= 1\'b0;\n            ^~\n%Error: data/full_repos/permissive/459838989/rtl/f2m/f2m_inv.v:119: Cannot find file containing module: \'f2m_inv_dp\'\nf2m_inv_dp #(\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/459838989/rtl/f2m,data/full_repos/permissive/459838989/f2m_inv_dp\n             data/full_repos/permissive/459838989/rtl/f2m,data/full_repos/permissive/459838989/f2m_inv_dp.v\n             data/full_repos/permissive/459838989/rtl/f2m,data/full_repos/permissive/459838989/f2m_inv_dp.sv\n             f2m_inv_dp\n             f2m_inv_dp.v\n             f2m_inv_dp.sv\n             obj_dir/f2m_inv_dp\n             obj_dir/f2m_inv_dp.v\n             obj_dir/f2m_inv_dp.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n'
module f2m_inv #(
    parameter M = 163,
    parameter FX = 163'hc9
)
(

    input clk,
    input rst_n,
    input clr,


    input start,
    input [M-1:0] a,
    output reg done,
    output [M-1:0] z
);


localparam CNT_WIDTH = $clog2(M);
localparam D_WIDTH = $clog2(2*M+1);



reg en;
reg [CNT_WIDTH-1:0] cnt;
reg [M:0] r_r;
reg [M:0] s_r;
reg [M:0] u_r;
reg [M:0] v_r;
reg [D_WIDTH-1:0] d_r;
wire [M:0] r;
wire [M:0] s;
wire [M:0] u;
wire [M:0] v;
wire [D_WIDTH-1:0] d;



always @ (posedge clk or negedge rst_n) begin
    if (!rst_n)
        cnt <= 1'b0;
    else if (clr | start)
        cnt <= 1'b0;
    else if (en)
        cnt <= cnt + 1'b1;
end

always @ (posedge clk or negedge rst_n) begin
    if (!rst_n)
        en <= 1'b0;
    else if (clr)
        en <= 1'b0;
    else if (start)
        en <= 1'b1;
    else if (cnt == M - 1)
        en <= 1'b0;
end

always @ (posedge clk or negedge rst_n) begin
    if (!rst_n)
        done <= 1'b0;
    else if (clr | start)
        done <= 1'b0;
    else if (cnt == M - 1)
        done <= 1'b1;
end

always @ (posedge clk) begin
    if (start)
        r_r <= a;
    else if (en)
        r_r <= r;
end

always @ (posedge clk) begin
    if (start)
        s_r <= {1'b1, FX};
    else if (en)
        s_r <= s;
end

always @ (posedge clk) begin
    if (start)
        u_r <= 1'b1;
    else if (en)
        u_r <= u;
end

always @ (posedge clk) begin
    if (start)
        v_r <= 1'b0;
    else if (en)
        v_r <= v;
end

always @ (posedge clk) begin
    if (start)
        d_r <= 1'b0;
    else if (en)
        d_r <= d;
end

assign z = u_r[M-1:0];



f2m_inv_dp #(
    .M              (M),
    .D_WIDTH        (D_WIDTH)
) u_f2m_inv_dp (
    .r_i            (r_r),
    .s_i            (s_r),
    .u_i            (u_r),
    .v_i            (v_r),
    .d_i            (d_r),
    .r_o            (r),
    .s_o            (s),
    .u_o            (u),
    .v_o            (v),
    .d_o            (d)
);


endmodule
module f2m_inv #(
    parameter M = 163,
    parameter FX = 163'hc9
)
(

    input clk,
    input rst_n,
    input clr,


    input start,
    input [M-1:0] a,
    output reg done,
    output [M-1:0] z
);



localparam CNT_WIDTH = $clog2(M);
localparam D_WIDTH = $clog2(2*M+1);



reg en;
reg [CNT_WIDTH-1:0] cnt;
reg [M:0] r_r;
reg [M:0] s_r;
reg [M:0] u_r;
reg [M:0] v_r;
reg [D_WIDTH-1:0] d_r;
wire [M:0] r;
wire [M:0] s;
wire [M:0] u;
wire [M:0] v;
wire [D_WIDTH-1:0] d;



always @ (posedge clk or negedge rst_n) begin
    if (!rst_n)
        cnt <= 1'b0;
    else if (clr | start)
        cnt <= 1'b0;
    else if (en)
        cnt <= cnt + 1'b1;
end

always @ (posedge clk or negedge rst_n) begin
    if (!rst_n)
        en <= 1'b0;
    else if (clr)
        en <= 1'b0;
    else if (start)
        en <= 1'b1;
    else if (cnt == M - 1)
        en <= 1'b0;
end

always @ (posedge clk or negedge rst_n) begin
    if (!rst_n)
        done <= 1'b0;
    else if (clr | start)
        done <= 1'b0;
    else if (cnt == M - 1)
        done <= 1'b1;
end

always @ (posedge clk) begin
    if (start)
        r_r <= a;
    else if (en)
        r_r <= r;
end

always @ (posedge clk) begin
    if (start)
        s_r <= {1'b1, FX};
    else if (en)
        s_r <= s;
end

always @ (posedge clk) begin
    if (start)
        u_r <= 1'b1;
    else if (en)
        u_r <= u;
end

always @ (posedge clk) begin
    if (start)
        v_r <= 1'b0;
    else if (en)
        v_r <= v;
end

always @ (posedge clk) begin
    if (start)
        d_r <= 1'b0;
    else if (en)
        d_r <= d;
end

assign z = u_r[M-1:0];



f2m_inv_dp #(
    .M              (M),
    .D_WIDTH        (D_WIDTH)
) u_f2m_inv_dp (
    .r_i            (r_r),
    .s_i            (s_r),
    .u_i            (u_r),
    .v_i            (v_r),
    .d_i            (d_r),
    .r_o            (r),
    .s_o            (s),
    .u_o            (u),
    .v_o            (v),
    .d_o            (d)
);


endmodule