data/full_repos/permissive/464991782/ALU1.v
1: b"%Error: data/full_repos/permissive/464991782/ALU1.v:24: Cannot find file containing module: 'HalfAdder'\nHalfAdder HA1(wireOutput[2], wireCarryOut[2], WireCarryIn, A);\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/464991782,data/full_repos/permissive/464991782/HalfAdder\n             data/full_repos/permissive/464991782,data/full_repos/permissive/464991782/HalfAdder.v\n             data/full_repos/permissive/464991782,data/full_repos/permissive/464991782/HalfAdder.sv\n             HalfAdder\n             HalfAdder.v\n             HalfAdder.sv\n             obj_dir/HalfAdder\n             obj_dir/HalfAdder.v\n             obj_dir/HalfAdder.sv\n%Error: data/full_repos/permissive/464991782/ALU1.v:25: Cannot find file containing module: 'FullAdder'\nFullAdder FA1(wireOutput[3], wireCarryOut[3], A, B, WireCarryIn);\n^~~~~~~~~\n%Error: data/full_repos/permissive/464991782/ALU1.v:35: Cannot find file containing module: 'Dual4to1Mux'\nDual4to1Mux Mux1(F, CarryOut, {S1, S0}, wireOutput, wireCarryOut);\n^~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module ALU1(F, CarryOut, S1, S0, A, B, CarryIn);
input S1, S0, A, B, CarryIn;
output CarryOut, F;

wire WireCarryIn;
wire [3:0] wireOutput;
wire [3:0] wireCarryOut;


HalfAdder HA1(wireOutput[2], wireCarryOut[2], WireCarryIn, A);
FullAdder FA1(wireOutput[3], wireCarryOut[3], A, B, WireCarryIn);
assign wireOutput[0] = A & ~B;
assign wireOutput[1] = ~A;

assign wireCarryOut[1:0] = 0;


assign WireCarryIn = S1 & ~S0 | CarryIn;


Dual4to1Mux Mux1(F, CarryOut, {S1, S0}, wireOutput, wireCarryOut);
endmodule
module ALU1(F, CarryOut, S1, S0, A, B, CarryIn);

input S1, S0, A, B, CarryIn;
output CarryOut, F;

wire WireCarryIn;
wire [3:0] wireOutput;
wire [3:0] wireCarryOut;


HalfAdder HA1(wireOutput[2], wireCarryOut[2], WireCarryIn, A);
FullAdder FA1(wireOutput[3], wireCarryOut[3], A, B, WireCarryIn);
assign wireOutput[0] = A & ~B;
assign wireOutput[1] = ~A;

assign wireCarryOut[1:0] = 0;


assign WireCarryIn = S1 & ~S0 | CarryIn;


Dual4to1Mux Mux1(F, CarryOut, {S1, S0}, wireOutput, wireCarryOut);
endmodule