data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/IDCT/bram.v
1: b'%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/IDCT/bram.v:17: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/IDCT,data/full_repos/permissive/502764644/defines.v\n             data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/IDCT,data/full_repos/permissive/502764644/defines.v.v\n             data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/IDCT,data/full_repos/permissive/502764644/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/IDCT/bram.v:22: Define or directive not defined: \'`IDCT_ADDR_WIDTH\'\ninput [`IDCT_ADDR_WIDTH-1:0] address_a, address_b;\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/IDCT/bram.v:23: Define or directive not defined: \'`IDCT_DATA_WIDTH\'\ninput [`IDCT_DATA_WIDTH-1:0] data_in_a, data_in_b;\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/IDCT/bram.v:24: Define or directive not defined: \'`IDCT_DATA_WIDTH\'\noutput [`IDCT_DATA_WIDTH-1:0] data_out_a, data_out_b;\n        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/IDCT/bram.v:28: Define or directive not defined: \'`IDCT_DATA_WIDTH\'\nassign data_out_a = dummy_a[`IDCT_DATA_WIDTH-1:0];\n                            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/Sequence_Decode/IDCT/bram.v:29: Define or directive not defined: \'`IDCT_DATA_WIDTH\'\nassign data_out_b = dummy_b[`IDCT_DATA_WIDTH-1:0];\n                            ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n'
module bram(clock, wren_a, wren_b, address_a, address_b, data_in_a, data_in_b, data_out_a, data_out_b);

input clock;
input wren_a, wren_b;
input [`IDCT_ADDR_WIDTH-1:0] address_a, address_b;
input [`IDCT_DATA_WIDTH-1:0] data_in_a, data_in_b;
output [`IDCT_DATA_WIDTH-1:0] data_out_a, data_out_b;

wire [31:0] dummy_a, dummy_b;

assign data_out_a = dummy_a[`IDCT_DATA_WIDTH-1:0];
assign data_out_b = dummy_b[`IDCT_DATA_WIDTH-1:0];


RAMB16_S36_S36 instance_bram (
      .DOA(dummy_a),     
      .DOB(dummy_b),     
      .DOPA(),		   		 
      .DOPB(),					
      .ADDRA({2'b00,address_a}),
      .ADDRB({2'b00,address_b}),
      .CLKA(clock),  
      .CLKB(clock),  
      .DIA({8'h00,data_in_a}),    
      .DIB({8'h00,data_in_b}),    
      .DIPA(4'h0),  
      .DIPB(4'h0),  
      .ENA(1'b1),
      .ENB(1'b1),
      .SSRA(1'b0),  
      .SSRB(1'b0),  
      .WEA(wren_a),    
      .WEB(wren_b)     
   );






































































endmodule
module bram(clock, wren_a, wren_b, address_a, address_b, data_in_a, data_in_b, data_out_a, data_out_b);


input clock;
input wren_a, wren_b;
input [`IDCT_ADDR_WIDTH-1:0] address_a, address_b;
input [`IDCT_DATA_WIDTH-1:0] data_in_a, data_in_b;
output [`IDCT_DATA_WIDTH-1:0] data_out_a, data_out_b;

wire [31:0] dummy_a, dummy_b;

assign data_out_a = dummy_a[`IDCT_DATA_WIDTH-1:0];
assign data_out_b = dummy_b[`IDCT_DATA_WIDTH-1:0];


RAMB16_S36_S36 instance_bram (
      .DOA(dummy_a),     
      .DOB(dummy_b),     
      .DOPA(),		   		 
      .DOPB(),					
      .ADDRA({2'b00,address_a}),
      .ADDRB({2'b00,address_b}),
      .CLKA(clock),  
      .CLKB(clock),  
      .DIA({8'h00,data_in_a}),    
      .DIB({8'h00,data_in_b}),    
      .DIPA(4'h0),  
      .DIPB(4'h0),  
      .ENA(1'b1),
      .ENB(1'b1),
      .SSRA(1'b0),  
      .SSRB(1'b0),  
      .WEA(wren_a),    
      .WEB(wren_b)     
   );






































































endmodule