data/full_repos/permissive/461141714/src/Multi Cycle CPU/cpu.v
1: b'%Error: Cannot find file containing module: Cycle\n        ... Looked in:\n             data/full_repos/permissive/461141714/src/Multi/Cycle\n             data/full_repos/permissive/461141714/src/Multi/Cycle.v\n             data/full_repos/permissive/461141714/src/Multi/Cycle.sv\n             Cycle\n             Cycle.v\n             Cycle.sv\n             obj_dir/Cycle\n             obj_dir/Cycle.v\n             obj_dir/Cycle.sv\n%Error: Cannot find file containing module: CPU,data/full_repos/permissive/461141714\n%Error: Cannot find file containing module: data/full_repos/permissive/461141714/src/Multi\n%Error: Cannot find file containing module: CPU/cpu.v\n%Error: Exiting due to 4 error(s)\n'
module cpu (
    output readM,
    output writeM,
    output [`WORD_SIZE-1:0] address,
    inout [`WORD_SIZE-1:0] data,
    input inputReady,
    input reset_n,
    input clk,
    

    output [`WORD_SIZE-1:0] num_inst,
    output [`WORD_SIZE-1:0] output_port,
    output is_halted
);

    reg [`WORD_SIZE-1:0] memory_register;
    reg [`WORD_SIZE-1:0] num_inst;
    

    wire [`WORD_SIZE-1:0] instruction;
    wire pcWrite;
    wire pcWriteCond;
    wire [1:0] pcSrc;
    wire getI;
    wire readM_w;
    wire writeM_w;
    wire IRWrite;
    wire [1:0] regSrc;
    wire [1:0] regData;
    wire regWrite;
    wire srcA;
    wire [1:0] srcB;
    wire [5:0] ALUoper;
    wire isWWD;
    wire bEqual;
    wire bAGZ;
    wire bALZ;
    

    wire new_inst;
    
    assign readM = readM_w;
    assign writeM = writeM_w;
    
    datapath DP(
        .clk(clk),
        .reset_n(reset_n),
        .memory_data(data),
        .memory_addr(address),
        .inputReady(inputReady),
        .output_port(output_port),
        .instruction(instruction),
        .pcWrite(pcWrite),
        .pcWriteCond(pcWriteCond),
        .pcSrc(pcSrc),
        .getI(getI),
        .readM(readM_w),
        .writeM(writeM_w),
        .IRWrite(IRWrite),
        .regSrc(regSrc),
        .regData(regData),
        .regWrite(regWrite),
        .srcA(srcA),
        .srcB(srcB),
        .ALUoper(ALUoper),
        .isWWD(isWWD),
        .bEqual(bEqual),
        .bAGZ(bAGZ),
        .bALZ(bALZ)
    );
    
    control CU(
        .clk(clk),
        .reset_n(reset_n),
        .instruction(instruction),

        .pcWrite(pcWrite),
        .pcWriteCond(pcWriteCond),
        .pcSrc(pcSrc),
        .getI(getI),
        .readM(readM_w),
        .writeM(writeM_w),
        .IRWrite(IRWrite),
        .regSrc(regSrc),
        .regData(regData),
        .regWrite(regWrite),
        .srcA(srcA),
        .srcB(srcB),
        .ALUoper(ALUoper),
        .isWWD(isWWD),
        .bEqual(bEqual),
        .bAGZ(bAGZ),
        .bALZ(bALZ),
        .halted(is_halted),
        .new_inst(new_inst)
    );
    
    always @(reset_n) begin
        if(reset_n == 0) begin
            num_inst = `WORD_SIZE'b0;
        end
    end
    
    always @(data) begin
        if(readM == 1'b1) memory_register = data; 
    end
    
    always @(posedge new_inst) begin
        num_inst = num_inst + 1;
    end
    
endmodule
module cpu (
    output readM,
    output writeM,
    output [`WORD_SIZE-1:0] address,
    inout [`WORD_SIZE-1:0] data,
    input inputReady,
    input reset_n,
    input clk,
    

    output [`WORD_SIZE-1:0] num_inst,
    output [`WORD_SIZE-1:0] output_port,
    output is_halted
);


    reg [`WORD_SIZE-1:0] memory_register;
    reg [`WORD_SIZE-1:0] num_inst;
    

    wire [`WORD_SIZE-1:0] instruction;
    wire pcWrite;
    wire pcWriteCond;
    wire [1:0] pcSrc;
    wire getI;
    wire readM_w;
    wire writeM_w;
    wire IRWrite;
    wire [1:0] regSrc;
    wire [1:0] regData;
    wire regWrite;
    wire srcA;
    wire [1:0] srcB;
    wire [5:0] ALUoper;
    wire isWWD;
    wire bEqual;
    wire bAGZ;
    wire bALZ;
    

    wire new_inst;
    
    assign readM = readM_w;
    assign writeM = writeM_w;
    
    datapath DP(
        .clk(clk),
        .reset_n(reset_n),
        .memory_data(data),
        .memory_addr(address),
        .inputReady(inputReady),
        .output_port(output_port),
        .instruction(instruction),
        .pcWrite(pcWrite),
        .pcWriteCond(pcWriteCond),
        .pcSrc(pcSrc),
        .getI(getI),
        .readM(readM_w),
        .writeM(writeM_w),
        .IRWrite(IRWrite),
        .regSrc(regSrc),
        .regData(regData),
        .regWrite(regWrite),
        .srcA(srcA),
        .srcB(srcB),
        .ALUoper(ALUoper),
        .isWWD(isWWD),
        .bEqual(bEqual),
        .bAGZ(bAGZ),
        .bALZ(bALZ)
    );
    
    control CU(
        .clk(clk),
        .reset_n(reset_n),
        .instruction(instruction),

        .pcWrite(pcWrite),
        .pcWriteCond(pcWriteCond),
        .pcSrc(pcSrc),
        .getI(getI),
        .readM(readM_w),
        .writeM(writeM_w),
        .IRWrite(IRWrite),
        .regSrc(regSrc),
        .regData(regData),
        .regWrite(regWrite),
        .srcA(srcA),
        .srcB(srcB),
        .ALUoper(ALUoper),
        .isWWD(isWWD),
        .bEqual(bEqual),
        .bAGZ(bAGZ),
        .bALZ(bALZ),
        .halted(is_halted),
        .new_inst(new_inst)
    );
    
    always @(reset_n) begin
        if(reset_n == 0) begin
            num_inst = `WORD_SIZE'b0;
        end
    end
    
    always @(data) begin
        if(readM == 1'b1) memory_register = data; 
    end
    
    always @(posedge new_inst) begin
        num_inst = num_inst + 1;
    end
    
endmodule