data/full_repos/permissive/420726213/verilog/rtl/wb_mux.v
1: b"%Error: data/full_repos/permissive/420726213/verilog/rtl/wb_mux.v:31: Define or directive not defined: '`WB_WIDTH'\n   input [`WB_WIDTH-1:0] wbs_adr_i,        \n          ^~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/wb_mux.v:32: Define or directive not defined: '`WB_WIDTH'\n   input [`WB_WIDTH-1:0] wbs_dat_i,        \n          ^~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/wb_mux.v:34: Define or directive not defined: '`WB_WIDTH'\n   output [`WB_WIDTH-1:0] wbs_dat_o,       \n           ^~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/wb_mux.v:37: Define or directive not defined: '`LOG_CORES'\n   output [`LOG_CORES-1:0] prog_sel,\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/wb_mux.v:38: Define or directive not defined: '`PC_WIDTH'\n   output [`PC_WIDTH-1:0] prog_waddr,\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/wb_mux.v:39: Define or directive not defined: '`INSTR_WIDTH'\n   output [`INSTR_WIDTH-1:0] prog_wdata,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/wb_mux.v:43: Define or directive not defined: '`IO_PINS'\n   output [`IO_PINS-1:0] pads_wdata,\n           ^~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/wb_mux.v:45: Define or directive not defined: '`LOG_CORES'\n   output [`LOG_CORES-1:0] debug_sel,\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/wb_mux.v:48: Define or directive not defined: '`DATA_WIDTH'\n   output [`DATA_WIDTH-1:0] debug_wdata,\n           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/wb_mux.v:49: Define or directive not defined: '`DATA_WIDTH'\n   input [`DATA_WIDTH-1:0] debug_rdata,\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/wb_mux.v:51: Define or directive not defined: '`WB_WIDTH'\n   output[`WB_WIDTH-1:0] entropy_word\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/wb_mux.v:59: Define or directive not defined: '`WB_WIDTH'\nwire[1:0] iface = wbs_adr_i[`WB_WIDTH-2 +: 2];\n                            ^~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/wb_mux.v:67: Define or directive not defined: '`WB_WIDTH'\nassign {prog_sel, prog_waddr} = prog_we ? wbs_adr_i[`WB_WIDTH-3:0] : 0;\n                                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/wb_mux.v:72: Define or directive not defined: '`WB_WIDTH'\nassign pads_waddr = pads_we ? wbs_adr_i[`WB_WIDTH-3:0] : 0;\n                                        ^~~~~~~~~\n%Error: data/full_repos/permissive/420726213/verilog/rtl/wb_mux.v:76: Define or directive not defined: '`WB_WIDTH'\nassign {debug_sel, debug_addr} = if_debug ? wbs_adr_i[`WB_WIDTH-3:0] : 0;\n                                                      ^~~~~~~~~\n%Error: Exiting due to 15 error(s)\n"
module wb_mux (



   input wbs_stb_i,
   input wbs_cyc_i,
   input wbs_we_i,
   input [`WB_WIDTH-1:0] wbs_adr_i,
   input [`WB_WIDTH-1:0] wbs_dat_i,
   output wbs_ack_o,
   output [`WB_WIDTH-1:0] wbs_dat_o,

   output prog_we,
   output [`LOG_CORES-1:0] prog_sel,
   output [`PC_WIDTH-1:0] prog_waddr,
   output [`INSTR_WIDTH-1:0] prog_wdata,

   output pads_we,
   output pads_waddr,
   output [`IO_PINS-1:0] pads_wdata,

   output [`LOG_CORES-1:0] debug_sel,
   output [4:0] debug_addr,
   output debug_we,
   output [`DATA_WIDTH-1:0] debug_wdata,
   input [`DATA_WIDTH-1:0] debug_rdata,

   output[`WB_WIDTH-1:0] entropy_word
);


wire valid = wbs_stb_i && wbs_cyc_i;
assign wbs_ack_o = valid;


wire[1:0] iface = wbs_adr_i[`WB_WIDTH-2 +: 2];
wire if_prog = valid && iface == 2'b00;
wire if_pads = valid && iface == 2'b01;
wire if_debug = valid && iface == 2'b10;
wire if_entropy = valid && iface == 2'b11;


assign prog_we = if_prog && wbs_we_i;
assign {prog_sel, prog_waddr} = prog_we ? wbs_adr_i[`WB_WIDTH-3:0] : 0;
assign prog_wdata = prog_we ? wbs_dat_i : 0;


assign pads_we = if_pads && wbs_we_i;
assign pads_waddr = pads_we ? wbs_adr_i[`WB_WIDTH-3:0] : 0;
assign pads_wdata = pads_we ? wbs_dat_i : 0;


assign {debug_sel, debug_addr} = if_debug ? wbs_adr_i[`WB_WIDTH-3:0] : 0;
assign debug_we = if_debug && wbs_we_i;
assign debug_wdata = debug_we ? wbs_dat_i : 0;


assign wbs_dat_o = (if_debug && !wbs_we_i) ? debug_rdata : 0;


assign entropy_word = (if_entropy && wbs_we_i) ? wbs_dat_i : 0;

endmodule
module wb_mux (



   input wbs_stb_i,
   input wbs_cyc_i,
   input wbs_we_i,
   input [`WB_WIDTH-1:0] wbs_adr_i,
   input [`WB_WIDTH-1:0] wbs_dat_i,
   output wbs_ack_o,
   output [`WB_WIDTH-1:0] wbs_dat_o,

   output prog_we,
   output [`LOG_CORES-1:0] prog_sel,
   output [`PC_WIDTH-1:0] prog_waddr,
   output [`INSTR_WIDTH-1:0] prog_wdata,

   output pads_we,
   output pads_waddr,
   output [`IO_PINS-1:0] pads_wdata,

   output [`LOG_CORES-1:0] debug_sel,
   output [4:0] debug_addr,
   output debug_we,
   output [`DATA_WIDTH-1:0] debug_wdata,
   input [`DATA_WIDTH-1:0] debug_rdata,

   output[`WB_WIDTH-1:0] entropy_word
);



wire valid = wbs_stb_i && wbs_cyc_i;
assign wbs_ack_o = valid;


wire[1:0] iface = wbs_adr_i[`WB_WIDTH-2 +: 2];
wire if_prog = valid && iface == 2'b00;
wire if_pads = valid && iface == 2'b01;
wire if_debug = valid && iface == 2'b10;
wire if_entropy = valid && iface == 2'b11;


assign prog_we = if_prog && wbs_we_i;
assign {prog_sel, prog_waddr} = prog_we ? wbs_adr_i[`WB_WIDTH-3:0] : 0;
assign prog_wdata = prog_we ? wbs_dat_i : 0;


assign pads_we = if_pads && wbs_we_i;
assign pads_waddr = pads_we ? wbs_adr_i[`WB_WIDTH-3:0] : 0;
assign pads_wdata = pads_we ? wbs_dat_i : 0;


assign {debug_sel, debug_addr} = if_debug ? wbs_adr_i[`WB_WIDTH-3:0] : 0;
assign debug_we = if_debug && wbs_we_i;
assign debug_wdata = debug_we ? wbs_dat_i : 0;


assign wbs_dat_o = (if_debug && !wbs_we_i) ? debug_rdata : 0;


assign entropy_word = (if_entropy && wbs_we_i) ? wbs_dat_i : 0;

endmodule