data/full_repos/permissive/441359809/src/yosys/tests/sat/initval.v
1: b"%Error: data/full_repos/permissive/441359809/src/yosys/tests/sat/initval.v:2: Duplicate declaration of signal: 'foo'\n                                                                            : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n  reg [3:0] foo = 0;\n            ^~~\n        data/full_repos/permissive/441359809/src/yosys/tests/sat/initval.v:1: ... Location of original declaration\nmodule test(input clk, input [3:0] bar, output [3:0] foo, asdf);\n                                                     ^~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/sat/initval.v:4: Duplicate declaration of signal: 'asdf'\n  reg [3:0] asdf = 4'b1xxx;\n            ^~~~\n        data/full_repos/permissive/441359809/src/yosys/tests/sat/initval.v:1: ... Location of original declaration\nmodule test(input clk, input [3:0] bar, output [3:0] foo, asdf);\n                                                          ^~~~\n%Error: Exiting due to 2 error(s)\n"
module test(input clk, input [3:0] bar, output [3:0] foo, asdf);
  reg [3:0] foo = 0;
  reg [3:0] last_bar = 0;
  reg [3:0] asdf = 4'b1xxx;

  always @*
    foo[1:0] <= bar[1:0];

  always @(posedge clk)
    foo[3:2] <= bar[3:2];

  always @(posedge clk)
    last_bar <= bar;

  always @(posedge clk)
    asdf[3] <= bar[3];
  always @*
    asdf[2:0] = 3'b111;

  assert property (foo == {last_bar[3:2], bar[1:0]});
endmodule
module test(input clk, input [3:0] bar, output [3:0] foo, asdf);

  reg [3:0] foo = 0;
  reg [3:0] last_bar = 0;
  reg [3:0] asdf = 4'b1xxx;

  always @*
    foo[1:0] <= bar[1:0];

  always @(posedge clk)
    foo[3:2] <= bar[3:2];

  always @(posedge clk)
    last_bar <= bar;

  always @(posedge clk)
    asdf[3] <= bar[3];
  always @*
    asdf[2:0] = 3'b111;

  assert property (foo == {last_bar[3:2], bar[1:0]});
endmodule