data/full_repos/permissive/439731184/example_begin_fork.v
1: b'%Error: data/full_repos/permissive/439731184/example_begin_fork.v:9: Unsupported or unknown PLI call: $monitor\n    $monitor("%h\\t%b\\t%b\\t%b\\t%b", $time, a, b, c, d);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/439731184/example_begin_fork.v:12: Unsupported: Ignoring delay on this delayed statement.\n    #1 a <= 0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/439731184/example_begin_fork.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #2 b <= 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/example_begin_fork.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #3 c <= 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/example_begin_fork.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #4 d <= 0;\n    ^\n%Error: data/full_repos/permissive/439731184/example_begin_fork.v:18: Unsupported: fork statements\n    fork: F\n    ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/439731184/example_begin_fork.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #1 a <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/example_begin_fork.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #2 b <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/example_begin_fork.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #3 c <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/example_begin_fork.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #4 d <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/example_begin_fork.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #1 $display("\\nTerminating simulation");\n    ^\n%Error: Exiting due to 2 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fork_join();

reg a, b, c, d;

initial begin

    $display("Starting simulation\n");
    $display("time\ta\tb\tc\td\n");
    $monitor("%h\t%b\t%b\t%b\t%b", $time, a, b, c, d);
   

    #1 a <= 0;
    #2 b <= 0;
    #3 c <= 0;
    #4 d <= 0;


    fork: F
        #1 a <= 1;
        #2 b <= 1;
        #3 c <= 1;
        #4 d <= 1;
    join

    #1 $display("\nTerminating simulation");

end

endmodule
module fork_join();


reg a, b, c, d;

initial begin

    $display("Starting simulation\n");
    $display("time\ta\tb\tc\td\n");
    $monitor("%h\t%b\t%b\t%b\t%b", $time, a, b, c, d);
   

    #1 a <= 0;
    #2 b <= 0;
    #3 c <= 0;
    #4 d <= 0;


    fork: F
        #1 a <= 1;
        #2 b <= 1;
        #3 c <= 1;
        #4 d <= 1;
    join

    #1 $display("\nTerminating simulation");

end

endmodule