data/full_repos/permissive/488739248/rtl/ttl/ttl_74174_sync.v
data/verilator_xmls/fc62e045-0f85-459d-9ac6-2626d0421264.xml
module ttl_74174_sync
( 
    input wire Reset_n,
    input wire Clk,

    input wire Cen,
    input wire Clr_n,
    input wire [5:0] D,
    output wire [5:0] Q
);

    reg [5:0] Q_current;
    reg last_cen;

    initial Q_current = 6'h00;
    always @(posedge Clk)
    begin
        if (!Reset_n) begin
            Q_current = 6'h00;
            last_cen <= 1'b1;
        end
        else begin
            last_cen <= Cen;

            if (!Clr_n)
                Q_current <= 6'h00;
            else
            if (Cen && !last_cen)
            begin
                Q_current <= D;
            end
            else begin
                Q_current <= Q_current;
            end
        end
    end

    assign Q = Q_current;
endmodule
module ttl_74174_sync
( 
    input wire Reset_n,
    input wire Clk,

    input wire Cen,
    input wire Clr_n,
    input wire [5:0] D,
    output wire [5:0] Q
);


    reg [5:0] Q_current;
    reg last_cen;

    initial Q_current = 6'h00;
    always @(posedge Clk)
    begin
        if (!Reset_n) begin
            Q_current = 6'h00;
            last_cen <= 1'b1;
        end
        else begin
            last_cen <= Cen;

            if (!Clr_n)
                Q_current <= 6'h00;
            else
            if (Cen && !last_cen)
            begin
                Q_current <= D;
            end
            else begin
                Q_current <= Q_current;
            end
        end
    end

    assign Q = Q_current;
endmodule