data/full_repos/permissive/515648441/true_dpram_dclk.v
data/verilator_xmls/779b2ca5-e601-4539-84c5-0c56a691dad6.xml
module true_dpram_dclk(
	input [WIDTH - 1:0] data_in_A, data_in_B, 
	input [ADDRESS - 1:0] addr_A, addr_B,
	input wr_en_A, wr_en_B, clk_A, clk_B,
	output reg [WIDTH - 1:0] data_out_A, data_out_B);

	reg [WIDTH - 1:0] ram[DEPTH - 1:0];

	
	always @ (posedge clk_A)
	begin
		if (!wr_en_A)
		begin
			data_out_A <= ram[addr_A];
		end
		else
			ram[addr_A] <= data_in_A;
			data_out_A <= ram[addr_A];
	end
	
	always @ (posedge clk_B)
	begin
		if (!wr_en_B)
		begin
			data_out_B <= ram[addr_B];
		end
		else
			ram[addr_B] <= data_in_B;
			data_out_B <= ram[addr_B];
	end
endmodule
module true_dpram_dclk(
	input [WIDTH - 1:0] data_in_A, data_in_B, 
	input [ADDRESS - 1:0] addr_A, addr_B,
	input wr_en_A, wr_en_B, clk_A, clk_B,
	output reg [WIDTH - 1:0] data_out_A, data_out_B);


	reg [WIDTH - 1:0] ram[DEPTH - 1:0];

	
	always @ (posedge clk_A)
	begin
		if (!wr_en_A)
		begin
			data_out_A <= ram[addr_A];
		end
		else
			ram[addr_A] <= data_in_A;
			data_out_A <= ram[addr_A];
	end
	
	always @ (posedge clk_B)
	begin
		if (!wr_en_B)
		begin
			data_out_B <= ram[addr_B];
		end
		else
			ram[addr_B] <= data_in_B;
			data_out_B <= ram[addr_B];
	end
endmodule