data/full_repos/permissive/518305321/iiitb_sipo_tb.v
1: b'%Error: data/full_repos/permissive/518305321/iiitb_sipo_tb.v:10: Unsupported or unknown PLI call: $dumpfile\n$dumpfile ("sipo.vcd");\n^~~~~~~~~\n%Error: data/full_repos/permissive/518305321/iiitb_sipo_tb.v:11: Unsupported or unknown PLI call: $dumpvars\n $dumpvars (0,iiitb_sipo_tb);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/518305321/iiitb_sipo_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\nforever #5 clk=~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/518305321/iiitb_sipo_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n#10 rst = 0; d=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/518305321/iiitb_sipo_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n#10 d=0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/518305321/iiitb_sipo_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n#10 d=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/518305321/iiitb_sipo_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n#10 d=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/518305321/iiitb_sipo_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n#50 $finish;\n^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module iiitb_sipo_tb();
reg d,clk,rst;
wire [3:0]q;
iiitb_sipo a(d, rst, clk, q);
 
initial
begin
$dumpfile ("sipo.vcd");
 $dumpvars (0,iiitb_sipo_tb);

clk=1'b0;
forever #5 clk=~clk;
end
initial
begin
rst = 1;d=1;
#10 rst = 0; d=1;
#10 d=0;
#10 d=1;
#10 d=1;
#50 $finish;
end 
endmodule
module iiitb_sipo_tb();

reg d,clk,rst;
wire [3:0]q;
iiitb_sipo a(d, rst, clk, q);
 
initial
begin
$dumpfile ("sipo.vcd");
 $dumpvars (0,iiitb_sipo_tb);

clk=1'b0;
forever #5 clk=~clk;
end
initial
begin
rst = 1;d=1;
#10 rst = 0; d=1;
#10 d=0;
#10 d=1;
#10 d=1;
#50 $finish;
end 
endmodule