data/full_repos/permissive/472586361/humanmachine/RAM.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/472586361/humanmachine/RAM.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #delaytime Memory[address][0] <= data[0];\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/472586361/humanmachine/RAM.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #delaytime Memory[address][1] <= data[1];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/472586361/humanmachine/RAM.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #delaytime Memory[address][2] <= data[2];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/472586361/humanmachine/RAM.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #delaytime Memory[address][3] <= data[3];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/472586361/humanmachine/RAM.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #delaytime Memory[address][4] <= data[4];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/472586361/humanmachine/RAM.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #delaytime Memory[address][5] <= data[5];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/472586361/humanmachine/RAM.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #delaytime Memory[address][6] <= data[6];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/472586361/humanmachine/RAM.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #delaytime Memory[address][7] <= data[7];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/472586361/humanmachine/RAM.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #delaytime buffer[0] <= Memory[address][0];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/472586361/humanmachine/RAM.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #delaytime buffer[1] <= Memory[address][1];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/472586361/humanmachine/RAM.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #delaytime buffer[2] <= Memory[address][2];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/472586361/humanmachine/RAM.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #delaytime buffer[3] <= Memory[address][3];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/472586361/humanmachine/RAM.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #delaytime buffer[4] <= Memory[address][4];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/472586361/humanmachine/RAM.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #delaytime buffer[5] <= Memory[address][5];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/472586361/humanmachine/RAM.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #delaytime buffer[6] <= Memory[address][6];\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/472586361/humanmachine/RAM.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #delaytime buffer[7] <= Memory[address][7];\n        ^\n%Error: Exiting due to 16 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module RAM(input clk, input [3:0] address, input write_enable, input read_enable, inout [7:0] data);
reg [7:0] Memory[15:0];
reg [7:0] buffer;
parameter delaytime =5;
initial begin
    Memory[0] <= 8'b0001_1010;
    Memory[1] <= 8'b0010_1011;
    Memory[2] <= 8'b0100_0110;
    Memory[3] <= 8'b0011_1100;
    Memory[4] <= 8'b0010_1101;
    Memory[5] <= 8'b1110_0000;
    Memory[6] <= 8'b0001_1110;
    Memory[7] <= 8'b0010_1111;
    Memory[8] <= 8'b1110_0000;
    Memory[9] <= 8'b1111_0000;
    Memory[10] <= 8'b0000_0011;
    Memory[11] <= 8'b0000_0010;
    Memory[12] <= 8'b0000_0001;
    Memory[13] <= 8'b0000_0101;
    Memory[14] <= 8'b0000_1010;
    Memory[15] <= 8'b0000_1011;
end


always @(posedge clk)
begin
    if(write_enable & ~read_enable)
    begin
        #delaytime Memory[address][0] <= data[0];
        #delaytime Memory[address][1] <= data[1];
        #delaytime Memory[address][2] <= data[2];
        #delaytime Memory[address][3] <= data[3];

        #delaytime Memory[address][4] <= data[4];
        #delaytime Memory[address][5] <= data[5];
        #delaytime Memory[address][6] <= data[6];
        #delaytime Memory[address][7] <= data[7];
    end
    else
    begin
        #delaytime buffer[0] <= Memory[address][0];
        #delaytime buffer[1] <= Memory[address][1];
        #delaytime buffer[2] <= Memory[address][2];
        #delaytime buffer[3] <= Memory[address][3];
        #delaytime buffer[4] <= Memory[address][4];
        #delaytime buffer[5] <= Memory[address][5];
        #delaytime buffer[6] <= Memory[address][6];
        #delaytime buffer[7] <= Memory[address][7];

    end
end

assign data = (read_enable & ~write_enable) ? buffer : 8'bzzzzzzzz;

endmodule
module RAM(input clk, input [3:0] address, input write_enable, input read_enable, inout [7:0] data);

reg [7:0] Memory[15:0];
reg [7:0] buffer;
parameter delaytime =5;
initial begin
    Memory[0] <= 8'b0001_1010;
    Memory[1] <= 8'b0010_1011;
    Memory[2] <= 8'b0100_0110;
    Memory[3] <= 8'b0011_1100;
    Memory[4] <= 8'b0010_1101;
    Memory[5] <= 8'b1110_0000;
    Memory[6] <= 8'b0001_1110;
    Memory[7] <= 8'b0010_1111;
    Memory[8] <= 8'b1110_0000;
    Memory[9] <= 8'b1111_0000;
    Memory[10] <= 8'b0000_0011;
    Memory[11] <= 8'b0000_0010;
    Memory[12] <= 8'b0000_0001;
    Memory[13] <= 8'b0000_0101;
    Memory[14] <= 8'b0000_1010;
    Memory[15] <= 8'b0000_1011;
end


always @(posedge clk)
begin
    if(write_enable & ~read_enable)
    begin
        #delaytime Memory[address][0] <= data[0];
        #delaytime Memory[address][1] <= data[1];
        #delaytime Memory[address][2] <= data[2];
        #delaytime Memory[address][3] <= data[3];

        #delaytime Memory[address][4] <= data[4];
        #delaytime Memory[address][5] <= data[5];
        #delaytime Memory[address][6] <= data[6];
        #delaytime Memory[address][7] <= data[7];
    end
    else
    begin
        #delaytime buffer[0] <= Memory[address][0];
        #delaytime buffer[1] <= Memory[address][1];
        #delaytime buffer[2] <= Memory[address][2];
        #delaytime buffer[3] <= Memory[address][3];
        #delaytime buffer[4] <= Memory[address][4];
        #delaytime buffer[5] <= Memory[address][5];
        #delaytime buffer[6] <= Memory[address][6];
        #delaytime buffer[7] <= Memory[address][7];

    end
end

assign data = (read_enable & ~write_enable) ? buffer : 8'bzzzzzzzz;

endmodule