data/full_repos/permissive/42414927/memory/testbench_4.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42414927/memory/testbench_4.v:90: Unsupported: Ignoring delay on this delayed statement.\n  #5 clk = !clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/42414927/memory/testbench_4.v:18: Cannot find file containing module: \'mips_memory2\'\n mips_memory2    test_memory(.clk(clk), \n ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/42414927/memory,data/full_repos/permissive/42414927/mips_memory2\n             data/full_repos/permissive/42414927/memory,data/full_repos/permissive/42414927/mips_memory2.v\n             data/full_repos/permissive/42414927/memory,data/full_repos/permissive/42414927/mips_memory2.sv\n             mips_memory2\n             mips_memory2.v\n             mips_memory2.sv\n             obj_dir/mips_memory2\n             obj_dir/mips_memory2.v\n             obj_dir/mips_memory2.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench_4 ();
	
	parameter START_ADDR = 32'h8002_0000;

	reg 		clk;
	reg   [31:0]	addr;
	reg   [31:0]	din;
	reg		enable;
	reg		rw;
	reg   [1:0]	access_size;
	
	reg		test_mode;
	reg   [31:0]	int_addr;

	wire  [31:0]	dout;
	wire 		busy;

	mips_memory2    test_memory(.clk(clk), 
			            .addr(addr), 
			            .din(din), 
			            .dout(dout), 
			            .access_size(access_size), 
			            .rw(rw), 
			            .busy(busy), 
			            .enable(enable));

	reg    [7:0]  mem[0:256];

	initial
	begin
		clk = 1'b0;
		enable = 1'b0;
		addr = 32'h8002_0000;
		din =  32'b0000_0000;
		rw = 1'b1;
		access_size = 2'b01;
		test_mode = 0;
		int_addr = 0;
		$readmemh("SumArray.x", mem);
	end

	always @(negedge clk)
	begin
		if ((addr + int_addr) > 32'h8002_00b4 & test_mode == 0)
		begin
			enable = 0;
			if (busy == 0)
			begin
				enable = 1;
				test_mode = 1;
				addr = 32'h8002_0000;
				rw = 1'b0;	
				int_addr = 4;
			end
		end
		else
		begin
			if (test_mode == 0)
			begin
				enable = 1'b1;
				din[31:24] = mem[addr + int_addr - START_ADDR];
				din[23:16] = mem[addr + int_addr + 1 - START_ADDR];
				din[15:8] = mem[addr + int_addr + 2 - START_ADDR];
				din[7:0] = mem[addr + int_addr + 3 - START_ADDR];
		
				int_addr = int_addr + 32'h0000_0004;
	
				if (int_addr == 20)
				begin
					addr = addr + 32'h0000_0010;
					int_addr = 4;
				end
			end
			else
			begin
				enable = 1'b1;
				int_addr = int_addr + 32'h0000_0004;
	
				if (int_addr == 20)
				begin
					addr = addr + 32'h0000_0010;
					int_addr = 4;
				end					
			end
		end
						
	end

	always
		#5 clk = !clk;

endmodule
module testbench_4 ();

	
	parameter START_ADDR = 32'h8002_0000;

	reg 		clk;
	reg   [31:0]	addr;
	reg   [31:0]	din;
	reg		enable;
	reg		rw;
	reg   [1:0]	access_size;
	
	reg		test_mode;
	reg   [31:0]	int_addr;

	wire  [31:0]	dout;
	wire 		busy;

	mips_memory2    test_memory(.clk(clk), 
			            .addr(addr), 
			            .din(din), 
			            .dout(dout), 
			            .access_size(access_size), 
			            .rw(rw), 
			            .busy(busy), 
			            .enable(enable));

	reg    [7:0]  mem[0:256];

	initial
	begin
		clk = 1'b0;
		enable = 1'b0;
		addr = 32'h8002_0000;
		din =  32'b0000_0000;
		rw = 1'b1;
		access_size = 2'b01;
		test_mode = 0;
		int_addr = 0;
		$readmemh("SumArray.x", mem);
	end

	always @(negedge clk)
	begin
		if ((addr + int_addr) > 32'h8002_00b4 & test_mode == 0)
		begin
			enable = 0;
			if (busy == 0)
			begin
				enable = 1;
				test_mode = 1;
				addr = 32'h8002_0000;
				rw = 1'b0;	
				int_addr = 4;
			end
		end
		else
		begin
			if (test_mode == 0)
			begin
				enable = 1'b1;
				din[31:24] = mem[addr + int_addr - START_ADDR];
				din[23:16] = mem[addr + int_addr + 1 - START_ADDR];
				din[15:8] = mem[addr + int_addr + 2 - START_ADDR];
				din[7:0] = mem[addr + int_addr + 3 - START_ADDR];
		
				int_addr = int_addr + 32'h0000_0004;
	
				if (int_addr == 20)
				begin
					addr = addr + 32'h0000_0010;
					int_addr = 4;
				end
			end
			else
			begin
				enable = 1'b1;
				int_addr = int_addr + 32'h0000_0004;
	
				if (int_addr == 20)
				begin
					addr = addr + 32'h0000_0010;
					int_addr = 4;
				end					
			end
		end
						
	end

	always
		#5 clk = !clk;

endmodule