data/full_repos/permissive/443556793/lab_4/rtl/hilo_reg.v
data/verilator_xmls/b12df28e-bfe6-40f1-b3f1-b6210340a73c.xml
module hilo_reg(
	input wire clk,rst,we,
	input wire[31:0] hi_i,lo_i,
	output reg[31:0] hi_o,lo_o
    );
	
	always @(negedge clk) begin
		if(rst) begin
			hi_o <= 32'h0000_0000;
			lo_o <= 32'h0000_0000;
		end else if (we) begin
			hi_o <= hi_i;
			lo_o <= lo_i;
		end
	end
endmodule
module hilo_reg(
	input wire clk,rst,we,
	input wire[31:0] hi_i,lo_i,
	output reg[31:0] hi_o,lo_o
    );

	
	always @(negedge clk) begin
		if(rst) begin
			hi_o <= 32'h0000_0000;
			lo_o <= 32'h0000_0000;
		end else if (we) begin
			hi_o <= hi_i;
			lo_o <= lo_i;
		end
	end
endmodule