data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Shift Registers/ece241_2013_q12/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Shift\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Shift\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Shift.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Shift.sv\n             Logic/Shift\n             Logic/Shift.v\n             Logic/Shift.sv\n             obj_dir/Logic/Shift\n             obj_dir/Logic/Shift.v\n             obj_dir/Logic/Shift.sv\n%Error: Cannot find file containing module: Registers/ece241_2013_q12,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Registers/ece241_2013_q12/top_module.v\n%Error: Exiting due to 4 error(s)\n'
module top_module (
    input  wire clk,
    input  wire enable,
    input  wire S,
    input  wire A,
    input  wire B,
    input  wire C,
    output wire Z
);

  reg [7:0] Q = 8'h0;
  assign Z = Q[{A, B, C}];

  always @(posedge clk) begin
    if (enable) begin
      Q <= Q << 1'h1;
      Q[0] <= S;
    end
  end

endmodule
module top_module (
    input  wire clk,
    input  wire enable,
    input  wire S,
    input  wire A,
    input  wire B,
    input  wire C,
    output wire Z
);


  reg [7:0] Q = 8'h0;
  assign Z = Q[{A, B, C}];

  always @(posedge clk) begin
    if (enable) begin
      Q <= Q << 1'h1;
      Q[0] <= S;
    end
  end

endmodule