data/full_repos/permissive/425966734/verilog/rtl/clk_div.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/425966734/verilog/rtl/clk_div.v:59: Multiple top level modules\n                                                                                : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                : ... Top module \'micclk\'\nmodule micclk(clk, rst, mclk, ce_pdm);\n       ^~~~~~\n                                                                                : ... Top module \'pcm_clk\'\nmodule pcm_clk(clk, rst, prescaler, ce_pcm); \n       ^~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module pcm_clk(clk, rst, prescaler, ce_pcm); 

  input clk, rst;
  input [9:0] prescaler;
  output reg ce_pcm;
  
  reg [9:0] count;
  
  always@(posedge clk) begin 
    if(rst)begin 
      ce_pcm <=0;
      count <= 0;
    end
    else if(count == prescaler) begin
        ce_pcm <= 1;
        count <=0;
    end
    else begin
    	count <= count + 1;
        ce_pcm <= 0;
    end
    
  end

endmodule
module pcm_clk(clk, rst, prescaler, ce_pcm);
 

  input clk, rst;
  input [9:0] prescaler;
  output reg ce_pcm;
  
  reg [9:0] count;
  
  always@(posedge clk) begin 
    if(rst)begin 
      ce_pcm <=0;
      count <= 0;
    end
    else if(count == prescaler) begin
        ce_pcm <= 1;
        count <=0;
    end
    else begin
    	count <= count + 1;
        ce_pcm <= 0;
    end
    
  end

endmodule