data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v
1: b'%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:77: Cannot find include file: sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v\n`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/504248338/verilog/dv/user_uart1,data/full_repos/permissive/504248338/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v\n             data/full_repos/permissive/504248338/verilog/dv/user_uart1,data/full_repos/permissive/504248338/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v.v\n             data/full_repos/permissive/504248338/verilog/dv/user_uart1,data/full_repos/permissive/504248338/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v.sv\n             sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v\n             sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v.v\n             sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v.sv\n             obj_dir/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v\n             obj_dir/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v.v\n             obj_dir/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v.sv\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:78: Cannot find include file: uart_agent.v\n`include "uart_agent.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:461: Cannot find include file: s25fl256s.sv\n`include "s25fl256s.sv" \n         ^~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:134: Unsupported: Ignoring delay on this delayed statement.\n always #12.5 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:155: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:171: Unsupported: Ignoring delay on this delayed statement.\n   #200;  \n   ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:172: syntax error, unexpected \'@\'\n   repeat (10) @(posedge clock);\n               ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:176: Define or directive not defined: \'`ADDR_SPACE_WBHOST\'\n   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,\'h1);\n                      ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:176: Define or directive not defined: \'`WBHOST_GLBL_CFG\'\n   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,\'h1);\n                                         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:176: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,\'h1);\n                                                         ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:179: Define or directive not defined: \'`ADDR_SPACE_PINMUX\'\n   wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,\'h200);\n                      ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:179: Define or directive not defined: \'`PINMUX_GPIO_MULTI_FUNC\'\n   wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,\'h200);\n                                         ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:179: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n   wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,\'h200);\n                                                                ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:181: syntax error, unexpected \'@\'\n   repeat (2) @(posedge clock);\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:182: Unsupported: Ignoring delay on this delayed statement.\n   #1;\n   ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:186: Define or directive not defined: \'`ADDR_SPACE_PINMUX\'\n wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h143);\n                    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:186: Define or directive not defined: \'`PINMUX_GBL_CFG0\'\n wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h143);\n                                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:186: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h143);\n                                                       ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:189: Define or directive not defined: \'`ADDR_SPACE_PINMUX\'\n wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h243);\n                    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:189: Define or directive not defined: \'`PINMUX_GBL_CFG0\'\n wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h243);\n                                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:189: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h243);\n                                                       ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:192: Define or directive not defined: \'`ADDR_SPACE_PINMUX\'\n wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h443);\n                    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:192: Define or directive not defined: \'`PINMUX_GBL_CFG0\'\n wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h443);\n                                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:192: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h443);\n                                                       ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:195: Define or directive not defined: \'`ADDR_SPACE_PINMUX\'\n wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h84F);\n                    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:195: Define or directive not defined: \'`PINMUX_GBL_CFG0\'\n wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h84F);\n                                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:195: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h84F);\n                                                       ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:198: syntax error, unexpected \'@\'\n   repeat (100) @(posedge clock);   \n                ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:201: Define or directive not defined: \'`ADDR_SPACE_UART1\'\n   wb_user_core_write(`ADDR_SPACE_UART1+8\'h0,{3\'h0,2\'b00,1\'b1,1\'b1,1\'b1});  \n                      ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:205: syntax error, unexpected \'@\'\n   repeat (30000) @(posedge clock);   \n                  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:213: Unsupported: fork statements\n   fork\n   ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:230: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:258: Unsupported: Ignoring delay on this delayed statement.\n      #100\n      ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:370: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:371: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:378: Unsupported: wait statements\n  wait(wbd_ext_ack_o == 1);\n  ^~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:379: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:380: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:388: syntax error, unexpected \'@\'\n  repeat (2) @(posedge clock);\n             ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:397: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:398: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:405: Unsupported: wait statements\n  wait(wbd_ext_ack_o == 1);\n  ^~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:406: syntax error, unexpected \'@\'\n  repeat (1) @(negedge clock);\n             ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:408: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:409: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_uart1/user_uart1_tb.v:417: syntax error, unexpected \'@\'\n  repeat (2) @(posedge clock);\n             ^\n%Error: Exiting due to 36 error(s), 10 warning(s)\n'
module user_uart1_tb;

reg            clock         ;
reg            wb_rst_i      ;
reg            power1, power2;
reg            power3, power4;

reg            wbd_ext_cyc_i;
reg            wbd_ext_stb_i;
reg [31:0]     wbd_ext_adr_i;
reg            wbd_ext_we_i;
reg [31:0]     wbd_ext_dat_i;
reg [3:0]      wbd_ext_sel_i;

wire [31:0]    wbd_ext_dat_o;
wire           wbd_ext_ack_o;
wire           wbd_ext_err_o;


wire [37:0]    io_oeb        ;
wire [37:0]    io_out        ;
wire [37:0]    io_in         ;

wire [37:0]    mprj_io       ;
wire [7:0]     mprj_io_0     ;
reg            test_fail     ;
reg [31:0]     read_data     ;



reg [1:0]      uart_data_bit        ;
reg	       uart_stop_bits       ;
reg	       uart_stick_parity    ;
reg	       uart_parity_en       ;
reg	       uart_even_odd_parity ;

reg [7:0]      uart_data            ;
reg [15:0]     uart_divisor         ;
reg [15:0]     uart_timeout         ;

reg [15:0]     uart_rx_nu           ;
reg [15:0]     uart_tx_nu           ;
reg [7:0]      uart_write_data [0:39];
reg 	       uart_fifo_enable     ;

	integer    d_risc_id;

integer i,j;





	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
                wbd_ext_cyc_i ='h0;
                wbd_ext_stb_i ='h0;
                wbd_ext_adr_i ='h0;
                wbd_ext_we_i  ='h0;
                wbd_ext_dat_i ='h0;
                wbd_ext_sel_i ='h0;
	end

	`ifdef WFDUMP
	   initial begin
	   	$dumpfile("simx.vcd");
	   	$dumpvars(0, user_uart1_tb);
	   end
       `endif

	initial begin
		wb_rst_i <= 1'b1;
		#100;
		wb_rst_i <= 1'b0;
	end
initial
begin
   uart_data_bit           = 2'b11;
   uart_stop_bits          = 0;
   uart_stick_parity       = 0;
   uart_parity_en          = 0;
   uart_even_odd_parity    = 1;
   uart_divisor            = 15;
   uart_timeout            = 500;
   uart_fifo_enable        = 0;

   $value$plusargs("risc_core_id=%d", d_risc_id);

   #200;
   repeat (10) @(posedge clock);
   $display("Monitor: Standalone User Uart Test Started");
   

   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);


   wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h200);
   
   repeat (2) @(posedge clock);
   #1;

   if(d_risc_id == 0) begin
	$display("STATUS: Working with Risc core 0");
	wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h143);
   end else if(d_risc_id == 1) begin
	$display("STATUS: Working with Risc core 1");
	wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h243);
   end else if(d_risc_id == 2) begin
	$display("STATUS: Working with Risc core 2");
	wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h443);
   end else if(d_risc_id == 3) begin
	$display("STATUS: Working with Risc core 2");
	wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h84F);
   end

   repeat (100) @(posedge clock);

   tb_uart.uart_init;
   wb_user_core_write(`ADDR_SPACE_UART1+8'h0,{3'h0,2'b00,1'b1,1'b1,1'b1});  
   tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, 
	                          uart_stick_parity, uart_timeout, uart_divisor);

   repeat (30000) @(posedge clock);
   
   
   for (i=0; i<40; i=i+1)
   	uart_write_data[i] = $random;
   
   
   
   fork
      begin
         for (i=0; i<40; i=i+1)
         begin
           $display ("\n... UART Agent Writing char %x ...", uart_write_data[i]);
            tb_uart.write_char (uart_write_data[i]);
         end
      end
   
      begin
         for (j=0; j<40; j=j+1)
         begin
           tb_uart.read_char_chk(uart_write_data[j]);
         end
      end
      join
   
      #100
      tb_uart.report_status(uart_rx_nu, uart_tx_nu);
   
      test_fail = 0;





      if(uart_tx_nu != 40) test_fail = 1;
      if(uart_rx_nu != 40) test_fail = 1;
      if(tb_uart.err_cnt != 0) test_fail = 1;

      $display("###################################################");
      if(test_fail == 0) begin
         `ifdef GL
             $display("Monitor: Standalone User UART Test (GL) Passed");
         `else
             $display("Monitor: Standalone User UART Test (RTL) Passed");
         `endif
      end else begin
          `ifdef GL
              $display("Monitor: Standalone User UART Test (GL) Failed");
          `else
              $display("Monitor: Standalone User UART Test (RTL) Failed");
          `endif
       end
      $display("###################################################");
      #100
      $finish;
end


wire USER_VDD1V8 = 1'b1;
wire VSS = 1'b0;


user_project_wrapper u_top(
`ifdef USE_POWER_PINS
    .vccd1(USER_VDD1V8),
    .vssd1(VSS),
`endif
    .wb_clk_i        (clock),
    .user_clock2     (1'b1),
    .wb_rst_i        (wb_rst_i),

    .wbs_cyc_i   (wbd_ext_cyc_i),
    .wbs_stb_i   (wbd_ext_stb_i),
    .wbs_adr_i   (wbd_ext_adr_i),
    .wbs_we_i    (wbd_ext_we_i),
    .wbs_dat_i   (wbd_ext_dat_i),
    .wbs_sel_i   (wbd_ext_sel_i),

    .wbs_dat_o   (wbd_ext_dat_o),
    .wbs_ack_o   (wbd_ext_ack_o),

 

    .la_data_in      ('1) ,
    .la_data_out     (),
    .la_oenb         ('0),
 


    .io_in          (io_in)  ,
    .io_out         (io_out) ,
    .io_oeb         (io_oeb) ,

    .user_irq       () 

);

`ifndef GL

    initial begin
    end
`endif    







   wire flash_clk = io_out[24];
   wire flash_csb = io_out[25];

   wire #1 io_oeb_29 = io_oeb[29];
   wire #1 io_oeb_30 = io_oeb[30];
   wire #1 io_oeb_31 = io_oeb[31];
   wire #1 io_oeb_32 = io_oeb[32];
   tri  #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz;
   tri  #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz;
   tri  #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz;
   tri  #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz;

   assign io_in[29] = flash_io0;
   assign io_in[30] = flash_io1;
   assign io_in[31] = flash_io2;
   assign io_in[32] = flash_io3;



     s25fl256s #(.mem_file_name("user_uart.hex"),
	         .otp_file_name("none"), 
                 .TimingModel("S25FL512SAGMFI010_F_30pF")) 
		 u_spi_flash_256mb
       (

       .SI      (flash_io0),
       .SO      (flash_io1),

       .SCK     (flash_clk),
       .CSNeg   (flash_csb),
       .WPNeg   (flash_io2),
       .HOLDNeg (flash_io3),
       .RSTNeg  (!wb_rst_i)

       );





wire uart_txd,uart_rxd;

assign uart_txd   = io_out[5];
assign io_in[3]  = uart_rxd ;
 
uart_agent tb_uart(
	.mclk                (clock              ),
	.txd                 (uart_rxd           ),
	.rxd                 (uart_txd           )
	);


task wb_user_core_write;
input [31:0] address;
input [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h1;
  wbd_ext_dat_i =data;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read;
input [31:0] address;
output [31:0] data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(negedge clock);
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
  repeat (2) @(posedge clock);
end
endtask

`ifdef GL

wire        wbd_spi_stb_i   = u_top.u_qspi_master.wbd_stb_i;
wire        wbd_spi_ack_o   = u_top.u_qspi_master.wbd_ack_o;
wire        wbd_spi_we_i    = u_top.u_qspi_master.wbd_we_i;
wire [31:0] wbd_spi_adr_i   = u_top.u_qspi_master.wbd_adr_i;
wire [31:0] wbd_spi_dat_i   = u_top.u_qspi_master.wbd_dat_i;
wire [31:0] wbd_spi_dat_o   = u_top.u_qspi_master.wbd_dat_o;
wire [3:0]  wbd_spi_sel_i   = u_top.u_qspi_master.wbd_sel_i;

wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb_spi.reg_cs;
wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb_spi.reg_ack;
wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb_spi.reg_wr;
wire [8:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb_spi.reg_addr;
wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb_spi.reg_wdata;
wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb_spi.reg_rdata;
wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb_spi.reg_be;

`endif


endmodule
module user_uart1_tb;


reg            clock         ;
reg            wb_rst_i      ;
reg            power1, power2;
reg            power3, power4;

reg            wbd_ext_cyc_i;
reg            wbd_ext_stb_i;
reg [31:0]     wbd_ext_adr_i;
reg            wbd_ext_we_i;
reg [31:0]     wbd_ext_dat_i;
reg [3:0]      wbd_ext_sel_i;

wire [31:0]    wbd_ext_dat_o;
wire           wbd_ext_ack_o;
wire           wbd_ext_err_o;


wire [37:0]    io_oeb        ;
wire [37:0]    io_out        ;
wire [37:0]    io_in         ;

wire [37:0]    mprj_io       ;
wire [7:0]     mprj_io_0     ;
reg            test_fail     ;
reg [31:0]     read_data     ;



reg [1:0]      uart_data_bit        ;
reg	       uart_stop_bits       ;
reg	       uart_stick_parity    ;
reg	       uart_parity_en       ;
reg	       uart_even_odd_parity ;

reg [7:0]      uart_data            ;
reg [15:0]     uart_divisor         ;
reg [15:0]     uart_timeout         ;

reg [15:0]     uart_rx_nu           ;
reg [15:0]     uart_tx_nu           ;
reg [7:0]      uart_write_data [0:39];
reg 	       uart_fifo_enable     ;

	integer    d_risc_id;

integer i,j;





	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
                wbd_ext_cyc_i ='h0;
                wbd_ext_stb_i ='h0;
                wbd_ext_adr_i ='h0;
                wbd_ext_we_i  ='h0;
                wbd_ext_dat_i ='h0;
                wbd_ext_sel_i ='h0;
	end

	`ifdef WFDUMP
	   initial begin
	   	$dumpfile("simx.vcd");
	   	$dumpvars(0, user_uart1_tb);
	   end
       `endif

	initial begin
		wb_rst_i <= 1'b1;
		#100;
		wb_rst_i <= 1'b0;
	end
initial
begin
   uart_data_bit           = 2'b11;
   uart_stop_bits          = 0;
   uart_stick_parity       = 0;
   uart_parity_en          = 0;
   uart_even_odd_parity    = 1;
   uart_divisor            = 15;
   uart_timeout            = 500;
   uart_fifo_enable        = 0;

   $value$plusargs("risc_core_id=%d", d_risc_id);

   #200;
   repeat (10) @(posedge clock);
   $display("Monitor: Standalone User Uart Test Started");
   

   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);


   wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h200);
   
   repeat (2) @(posedge clock);
   #1;

   if(d_risc_id == 0) begin
	$display("STATUS: Working with Risc core 0");
	wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h143);
   end else if(d_risc_id == 1) begin
	$display("STATUS: Working with Risc core 1");
	wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h243);
   end else if(d_risc_id == 2) begin
	$display("STATUS: Working with Risc core 2");
	wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h443);
   end else if(d_risc_id == 3) begin
	$display("STATUS: Working with Risc core 2");
	wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h84F);
   end

   repeat (100) @(posedge clock);

   tb_uart.uart_init;
   wb_user_core_write(`ADDR_SPACE_UART1+8'h0,{3'h0,2'b00,1'b1,1'b1,1'b1});  
   tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, 
	                          uart_stick_parity, uart_timeout, uart_divisor);

   repeat (30000) @(posedge clock);
   
   
   for (i=0; i<40; i=i+1)
   	uart_write_data[i] = $random;
   
   
   
   fork
      begin
         for (i=0; i<40; i=i+1)
         begin
           $display ("\n... UART Agent Writing char %x ...", uart_write_data[i]);
            tb_uart.write_char (uart_write_data[i]);
         end
      end
   
      begin
         for (j=0; j<40; j=j+1)
         begin
           tb_uart.read_char_chk(uart_write_data[j]);
         end
      end
      join
   
      #100
      tb_uart.report_status(uart_rx_nu, uart_tx_nu);
   
      test_fail = 0;





      if(uart_tx_nu != 40) test_fail = 1;
      if(uart_rx_nu != 40) test_fail = 1;
      if(tb_uart.err_cnt != 0) test_fail = 1;

      $display("###################################################");
      if(test_fail == 0) begin
         `ifdef GL
             $display("Monitor: Standalone User UART Test (GL) Passed");
         `else
             $display("Monitor: Standalone User UART Test (RTL) Passed");
         `endif
      end else begin
          `ifdef GL
              $display("Monitor: Standalone User UART Test (GL) Failed");
          `else
              $display("Monitor: Standalone User UART Test (RTL) Failed");
          `endif
       end
      $display("###################################################");
      #100
      $finish;
end


wire USER_VDD1V8 = 1'b1;
wire VSS = 1'b0;


user_project_wrapper u_top(
`ifdef USE_POWER_PINS
    .vccd1(USER_VDD1V8),
    .vssd1(VSS),
`endif
    .wb_clk_i        (clock),
    .user_clock2     (1'b1),
    .wb_rst_i        (wb_rst_i),

    .wbs_cyc_i   (wbd_ext_cyc_i),
    .wbs_stb_i   (wbd_ext_stb_i),
    .wbs_adr_i   (wbd_ext_adr_i),
    .wbs_we_i    (wbd_ext_we_i),
    .wbs_dat_i   (wbd_ext_dat_i),
    .wbs_sel_i   (wbd_ext_sel_i),

    .wbs_dat_o   (wbd_ext_dat_o),
    .wbs_ack_o   (wbd_ext_ack_o),

 

    .la_data_in      ('1) ,
    .la_data_out     (),
    .la_oenb         ('0),
 


    .io_in          (io_in)  ,
    .io_out         (io_out) ,
    .io_oeb         (io_oeb) ,

    .user_irq       () 

);

`ifndef GL

    initial begin
    end
`endif    







   wire flash_clk = io_out[24];
   wire flash_csb = io_out[25];

   wire #1 io_oeb_29 = io_oeb[29];
   wire #1 io_oeb_30 = io_oeb[30];
   wire #1 io_oeb_31 = io_oeb[31];
   wire #1 io_oeb_32 = io_oeb[32];
   tri  #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz;
   tri  #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz;
   tri  #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz;
   tri  #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz;

   assign io_in[29] = flash_io0;
   assign io_in[30] = flash_io1;
   assign io_in[31] = flash_io2;
   assign io_in[32] = flash_io3;



     s25fl256s #(.mem_file_name("user_uart.hex"),
	         .otp_file_name("none"), 
                 .TimingModel("S25FL512SAGMFI010_F_30pF")) 
		 u_spi_flash_256mb
       (

       .SI      (flash_io0),
       .SO      (flash_io1),

       .SCK     (flash_clk),
       .CSNeg   (flash_csb),
       .WPNeg   (flash_io2),
       .HOLDNeg (flash_io3),
       .RSTNeg  (!wb_rst_i)

       );





wire uart_txd,uart_rxd;

assign uart_txd   = io_out[5];
assign io_in[3]  = uart_rxd ;
 
uart_agent tb_uart(
	.mclk                (clock              ),
	.txd                 (uart_rxd           ),
	.rxd                 (uart_txd           )
	);


task wb_user_core_write;
input [31:0] address;
input [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h1;
  wbd_ext_dat_i =data;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read;
input [31:0] address;
output [31:0] data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(negedge clock);
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
  repeat (2) @(posedge clock);
end
endtask

`ifdef GL

wire        wbd_spi_stb_i   = u_top.u_qspi_master.wbd_stb_i;
wire        wbd_spi_ack_o   = u_top.u_qspi_master.wbd_ack_o;
wire        wbd_spi_we_i    = u_top.u_qspi_master.wbd_we_i;
wire [31:0] wbd_spi_adr_i   = u_top.u_qspi_master.wbd_adr_i;
wire [31:0] wbd_spi_dat_i   = u_top.u_qspi_master.wbd_dat_i;
wire [31:0] wbd_spi_dat_o   = u_top.u_qspi_master.wbd_dat_o;
wire [3:0]  wbd_spi_sel_i   = u_top.u_qspi_master.wbd_sel_i;

wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb_spi.reg_cs;
wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb_spi.reg_ack;
wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb_spi.reg_wr;
wire [8:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb_spi.reg_addr;
wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb_spi.reg_wdata;
wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb_spi.reg_rdata;
wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb_spi.reg_be;

`endif


endmodule