data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v
1: b'%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:46: Cannot find include file: usb_agents.v\n`include "usb_agents.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/504248338/verilog/dv/user_usb,data/full_repos/permissive/504248338/usb_agents.v\n             data/full_repos/permissive/504248338/verilog/dv/user_usb,data/full_repos/permissive/504248338/usb_agents.v.v\n             data/full_repos/permissive/504248338/verilog/dv/user_usb,data/full_repos/permissive/504248338/usb_agents.v.sv\n             usb_agents.v\n             usb_agents.v.v\n             usb_agents.v.sv\n             obj_dir/usb_agents.v\n             obj_dir/usb_agents.v.v\n             obj_dir/usb_agents.v.sv\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:47: Cannot find include file: test_control.v\n`include "test_control.v" \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:48: Cannot find include file: usb1d_defines.v\n`include "usb1d_defines.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:49: Cannot find include file: usbd_files.v\n`include "usbd_files.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:51: Cannot find include file: sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v\n`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:552: Cannot find include file: tests/usb_test1.v\n`include "tests/usb_test1.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:553: Cannot find include file: tests/usb_test2.v\n`include "tests/usb_test2.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n always #12.5 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n          #USB_HPER     usb_48mhz_clk = 1\'b0;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:111: Unsupported: Ignoring delay on this delayed statement.\n          #USB_HPER     usb_48mhz_clk = 1\'b1;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:116: Unsupported: Ignoring delay on this delayed statement.\n          #USER2_HPER     user_clock2 = 1\'b0;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n          #USER2_HPER     user_clock2 = 1\'b1;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:131: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:168: Unsupported or unknown PLI call: $dumpon\n  $dumpon;\n  ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:170: Unsupported: Ignoring delay on this delayed statement.\n  #200;  \n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:171: syntax error, unexpected \'@\'\n         repeat (10) @(posedge clock);\n                     ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:176: Define or directive not defined: \'`ADDR_SPACE_WBHOST\'\n                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,\'h1);\n                                   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:176: Define or directive not defined: \'`WBHOST_GLBL_CFG\'\n                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,\'h1);\n                                                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:176: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,\'h1);\n                                                                      ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:179: Define or directive not defined: \'`ADDR_SPACE_PINMUX\'\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,\'h400);\n                                   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:179: Define or directive not defined: \'`PINMUX_GPIO_MULTI_FUNC\'\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,\'h400);\n                                                      ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:179: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,\'h400);\n                                                                             ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:181: syntax error, unexpected \'@\'\n         repeat (2) @(posedge clock);\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:182: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:185: Define or directive not defined: \'`ADDR_SPACE_WBHOST\'\n                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,\'h1);\n                                   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:185: Define or directive not defined: \'`WBHOST_GLBL_CFG\'\n                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,\'h1);\n                                                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:185: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,\'h1);\n                                                                      ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:187: Define or directive not defined: \'`ADDR_SPACE_WBHOST\'\n                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h0,8\'h61,8\'h0,8\'h0});\n                                   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:187: Define or directive not defined: \'`WBHOST_CLK_CTRL2\'\n                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h0,8\'h61,8\'h0,8\'h0});\n                                                      ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:187: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8\'h0,8\'h61,8\'h0,8\'h0});\n                                                                       ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:191: Define or directive not defined: \'`ADDR_SPACE_PINMUX\'\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h03F);\n                                   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:191: Define or directive not defined: \'`PINMUX_GBL_CFG0\'\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h03F);\n                                                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:191: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h03F);\n                                                                      ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:195: syntax error, unexpected \'@\'\n         repeat (200) @(posedge clock);\n                      ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:196: Define or directive not defined: \'`ADDR_SPACE_WBHOST\'\n                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,\'h1000);  \n                                   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:196: Define or directive not defined: \'`WBHOST_BANK_SEL\'\n                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,\'h1000);  \n                                                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:196: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,\'h1000);  \n                                                                      ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:203: syntax error, unexpected \'@\'\n  repeat (100) @(posedge clock);\n               ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:313: Define or directive not defined: \'`ISO\'\n .ep1_cfg         ( `ISO  | `IN  | 14\'d0256  ),\n                    ^~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:313: Define or directive not defined: \'`IN\'\n .ep1_cfg         ( `ISO  | `IN  | 14\'d0256  ),\n                            ^~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:326: Define or directive not defined: \'`ISO\'\n .ep2_cfg         ( `ISO  | `OUT | 14\'d0256  ),\n                    ^~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:326: Define or directive not defined: \'`OUT\'\n .ep2_cfg         ( `ISO  | `OUT | 14\'d0256  ),\n                            ^~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:339: Define or directive not defined: \'`BULK\'\n .ep3_cfg         ( `BULK | `IN  | 14\'d064  ),\n                    ^~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:339: Define or directive not defined: \'`IN\'\n .ep3_cfg         ( `BULK | `IN  | 14\'d064  ),\n                            ^~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:352: Define or directive not defined: \'`BULK\'\n .ep4_cfg         ( `BULK | `OUT | 14\'d064  ),\n                    ^~~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:352: Define or directive not defined: \'`OUT\'\n .ep4_cfg         ( `BULK | `OUT | 14\'d064  ),\n                            ^~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:365: Define or directive not defined: \'`INT\'\n .ep5_cfg         ( `INT  | `IN  | 14\'d064  ),\n                    ^~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:365: Define or directive not defined: \'`IN\'\n .ep5_cfg         ( `INT  | `IN  | 14\'d064  ),\n                            ^~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:427: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:428: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:435: Unsupported: wait statements\n  wait(wbd_ext_ack_o == 1);\n  ^~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:436: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:437: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:445: syntax error, unexpected \'@\'\n  repeat (2) @(posedge clock);\n             ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:454: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:455: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:462: Unsupported: wait statements\n  wait(wbd_ext_ack_o == 1);\n  ^~~~\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:463: syntax error, unexpected \'@\'\n  repeat (1) @(negedge clock);\n             ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:465: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:466: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:474: syntax error, unexpected \'@\'\n  repeat (2) @(posedge clock);\n             ^\n%Error: data/full_repos/permissive/504248338/verilog/dv/user_usb/user_usb_tb.v:484: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module user_usb_tb;

parameter  USB_HPER   = 10.4167;
parameter  USER2_HPER = 2.7777;

	reg clock;
	reg user_clock2;
	reg usb_48mhz_clk;
	reg wb_rst_i;
	reg power1, power2;
	reg power3, power4;

        reg        wbd_ext_cyc_i;
        reg        wbd_ext_stb_i;
        reg [31:0] wbd_ext_adr_i;
        reg        wbd_ext_we_i;
        reg [31:0] wbd_ext_dat_i;
        reg [3:0]  wbd_ext_sel_i;

        wire [31:0] wbd_ext_dat_o;
        wire        wbd_ext_ack_o;
        wire        wbd_ext_err_o;


	wire [37:0] io_oeb;
	wire [37:0] io_out;
	wire [37:0] io_in;


	reg [1:0] spi_chip_no;

	wire gpio;
	wire [37:0] mprj_io;
	wire [7:0] mprj_io_0;
	reg        test_fail;
	reg [31:0] read_data;




        wire [31:0]   usbd_reg_addr;
       	wire 	      usbd_reg_rdwrn;
       	wire 	      usbd_reg_req;
        wire [31:0]   usbd_reg_wdata;
        reg [31:0]    usbd_reg_rdata;
        reg           usbd_reg_ack = 1'b1;

	reg  [31:0]   RegBank [0:15];





	always #12.5 clock <= (clock === 1'b0);


	always begin
          #USB_HPER     usb_48mhz_clk = 1'b0;
          #USB_HPER     usb_48mhz_clk = 1'b1;
        end


	always begin
          #USER2_HPER     user_clock2 = 1'b0;
          #USER2_HPER     user_clock2 = 1'b1;
        end

	initial begin
		clock = 0;
                wbd_ext_cyc_i ='h0;
                wbd_ext_stb_i ='h0;
                wbd_ext_adr_i ='h0;
                wbd_ext_we_i  ='h0;
                wbd_ext_dat_i ='h0;
                wbd_ext_sel_i ='h0;
	end
	initial begin
		wb_rst_i <= 1'b1;
		#100;
		wb_rst_i <= 1'b0;
	end

	`ifdef WFDUMP
	   initial begin
	   	$dumpfile("simx.vcd");
	   	$dumpvars(0, user_usb_tb);





	   end
       `endif

        always@(posedge wb_rst_i  or posedge usb_48mhz_clk)
	begin
	   if(wb_rst_i == 1'b1) begin
              usbd_reg_rdata = 'h0;
              usbd_reg_ack   = 'h0;
	   end else begin
	      if(usbd_reg_req && usbd_reg_rdwrn == 1'b0 && !usbd_reg_ack) begin
                 usbd_reg_ack = 'h1;
		 RegBank[usbd_reg_addr[5:2]] = usbd_reg_wdata;
		 $display("STATUS: Write Access Address : %x Data: %x",usbd_reg_addr[7:0],usbd_reg_wdata);
	      end else if(usbd_reg_req && usbd_reg_rdwrn == 1'b1 && !usbd_reg_ack) begin
                 usbd_reg_ack = 'h1;
		 usbd_reg_rdata = RegBank[usbd_reg_addr[5:2]];
		 $display("STATUS: Read Access Address : %x Data: %x",usbd_reg_addr[7:0],usbd_reg_rdata);
	      end else begin
                 usbd_reg_ack = 'h0;
	      end
	   end
	end

	initial begin
		$dumpon;

		#200;
	        repeat (10) @(posedge clock);
		$display("Monitor: Standalone User Risc Boot Test Started");

         

                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);


                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h400);

	        repeat (2) @(posedge clock);
		#1;
         

                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);

                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h0,8'h61,8'h0,8'h0});



                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h03F);


		test_fail = 0;
	        repeat (200) @(posedge clock);
                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000);



		usb_test2;


		repeat (100) @(posedge clock);


          	if(test_control.error_count == 0) begin
		   `ifdef GL
	    	       $display("Monitor: USB Mode (GL) Passed");
		   `else
		       $display("Monitor: USB Mode (RTL) Passed");
		   `endif
	        end else begin
		    `ifdef GL
	    	        $display("Monitor: USB Mode (GL) Failed");
		    `else
		        $display("Monitor: USB Mode (RTL) Failed");
		    `endif
		 end
	    	$display("###################################################");
	        $finish;
	end

wire USER_VDD1V8 = 1'b1;
wire VSS = 1'b0;

user_project_wrapper u_top(
`ifdef USE_POWER_PINS
    .vccd1(USER_VDD1V8),
    .vssd1(VSS),
`endif
    .wb_clk_i    (clock       ),
    .user_clock2 (user_clock2 ),
    .wb_rst_i    (wb_rst_i    ),

    .wbs_cyc_i   (wbd_ext_cyc_i),
    .wbs_stb_i   (wbd_ext_stb_i),
    .wbs_adr_i   (wbd_ext_adr_i),
    .wbs_we_i    (wbd_ext_we_i),
    .wbs_dat_i   (wbd_ext_dat_i),
    .wbs_sel_i   (wbd_ext_sel_i),

    .wbs_dat_o   (wbd_ext_dat_o),
    .wbs_ack_o   (wbd_ext_ack_o),

 

    .la_data_in      ('1) ,
    .la_data_out     (),
    .la_oenb         ('0),
 


    .io_in          (io_in)  ,
    .io_out         (io_out) ,
    .io_oeb         (io_oeb) ,

    .user_irq       () 

);
    usb_agent u_usb_agent();
    test_control test_control();

`ifndef GL

    initial begin

    end
`endif  



tri usbd_txdp = (io_oeb[36] == 1'b0) ? io_out[36] : 1'bz;
tri usbd_txdn = (io_oeb[37] == 1'b0) ? io_out[37] : 1'bz;

assign io_in[36] = usbd_txdp;
assign io_in[37] = usbd_txdn;



pullup(usbd_txdp); 
pulldown(usbd_txdn);

usb1d_top u_usb_top(

	.clk_i           (usb_48mhz_clk), 
	.rstn_i          (!wb_rst_i),
 

	.usb_dp          (usbd_txdp), 
	.usb_dn          (usbd_txdn), 
 

	.phy_tx_mode     (1'b1), 
        .usb_rst         (),
 

	.dropped_frame   (), 
	.misaligned_frame(),
	.crc16_err       (),
 

	.v_set_int       (), 
	.v_set_feature   (), 
	.wValue          (),
	.wIndex          (), 
	.vendor_data     (),
 

	.usb_busy        (), 
	.ep_sel          (),
 

	.ep1_cfg         (	`ISO  | `IN  | 14'd0256		),

	.ep1_dout        (					),
	.ep1_we          (					),
	.ep1_full        (		1'b0			),

	.ep1_din         (		8'h0		        ),
	.ep1_re          (		   		        ),
	.ep1_empty       (		1'b0     		),
	.ep1_bf_en       (		1'b0			),
	.ep1_bf_size     (		7'h0			),
 

	.ep2_cfg         (	`ISO  | `OUT | 14'd0256		),

	.ep2_dout        (				        ),
	.ep2_we          (				        ),
	.ep2_full        (		1'b0     		),

	.ep2_din         (		8'h0			),
	.ep2_re          (					),
	.ep2_empty       (		1'b0			),
	.ep2_bf_en       (		1'b0			),
	.ep2_bf_size     (		7'h0			),
 

	.ep3_cfg         (	`BULK | `IN  | 14'd064		),

	.ep3_dout        (					),
	.ep3_we          (					),
	.ep3_full        (		1'b0			),

	.ep3_din         (		8'h0      		),
	.ep3_re          (		        		),
	.ep3_empty       (		1'b0    		),
	.ep3_bf_en       (		1'b0			),
	.ep3_bf_size     (		7'h0			),
 

	.ep4_cfg         (	`BULK | `OUT | 14'd064		),

	.ep4_dout        (		        		),
	.ep4_we          (		        		),
	.ep4_full        (		1'b0     		),

	.ep4_din         (		8'h0			),
	.ep4_re          (					),
	.ep4_empty       (		1'b0			),
	.ep4_bf_en       (		1'b0			),
	.ep4_bf_size     (		7'h0			),
 

	.ep5_cfg         (	`INT  | `IN  | 14'd064		),

	.ep5_dout        (					),
	.ep5_we          (					),
	.ep5_full        (		1'b0			),

	.ep5_din         (		8'h0     		),
	.ep5_re          (				        ),
	.ep5_empty       (		1'b0     		),
	.ep5_bf_en       (		1'b0			),
	.ep5_bf_size     (		7'h0			),
 

	.ep6_cfg         (		14'h00			),

	.ep6_dout        (					),
	.ep6_we          (					),
	.ep6_full        (		1'b0			),

	.ep6_din         (		8'h0			),
	.ep6_re          (					),
	.ep6_empty       (		1'b0			),
	.ep6_bf_en       (		1'b0			),
	.ep6_bf_size     (		7'h0			),
 

	.ep7_cfg         (		14'h00			),

	.ep7_dout        (					),
	.ep7_we          (					),
	.ep7_full        (		1'b0			),

	.ep7_din         (		8'h0			),
	.ep7_re          (					),
	.ep7_empty       (		1'b0			),
	.ep7_bf_en       (		1'b0			),
	.ep7_bf_size     (		7'h0			),
 

	.reg_addr        (usbd_reg_addr),
	.reg_rdwrn       (usbd_reg_rdwrn),
	.reg_req         (usbd_reg_req),
	.reg_wdata       (usbd_reg_wdata),
	.reg_rdata       (usbd_reg_rdata),
	.reg_ack         (usbd_reg_ack)
 
	);





task test_err;
begin
     test_fail = 1;
end
endtask

task wb_user_core_write;
input [31:0] address;
input [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h1;
  wbd_ext_dat_i =data;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  $display("STATUS: WB USER ACCESS WRITE Address : 0x%x, Data : 0x%x",address,data);
  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read;
input [31:0] address;
output [31:0] data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(negedge clock);
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;

  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read_check;
input [31:0] address;
output [31:0] data;
input [31:0] cmp_data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  if(data !== cmp_data) begin
     $display("ERROR : WB USER ACCESS READ  Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
     user_usb_tb.test_fail = 1;
  end else begin
     $display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,data);
  end
  repeat (2) @(posedge clock);
end
endtask


`ifdef GL

wire        wbd_spi_stb_i   = u_top.u_qspi_master.wbd_stb_i;
wire        wbd_spi_ack_o   = u_top.u_qspi_master.wbd_ack_o;
wire        wbd_spi_we_i    = u_top.u_qspi_master.wbd_we_i;
wire [31:0] wbd_spi_adr_i   = u_top.u_qspi_master.wbd_adr_i;
wire [31:0] wbd_spi_dat_i   = u_top.u_qspi_master.wbd_dat_i;
wire [31:0] wbd_spi_dat_o   = u_top.u_qspi_master.wbd_dat_o;
wire [3:0]  wbd_spi_sel_i   = u_top.u_qspi_master.wbd_sel_i;

wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb_spi.reg_cs;
wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb_spi.reg_ack;
wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb_spi.reg_wr;
wire [8:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb_spi.reg_addr;
wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb_spi.reg_wdata;
wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb_spi.reg_rdata;
wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb_spi.reg_be;

`endif


`include "tests/usb_test1.v"
`include "tests/usb_test2.v"

endmodule
module user_usb_tb;


parameter  USB_HPER   = 10.4167;
parameter  USER2_HPER = 2.7777;

	reg clock;
	reg user_clock2;
	reg usb_48mhz_clk;
	reg wb_rst_i;
	reg power1, power2;
	reg power3, power4;

        reg        wbd_ext_cyc_i;
        reg        wbd_ext_stb_i;
        reg [31:0] wbd_ext_adr_i;
        reg        wbd_ext_we_i;
        reg [31:0] wbd_ext_dat_i;
        reg [3:0]  wbd_ext_sel_i;

        wire [31:0] wbd_ext_dat_o;
        wire        wbd_ext_ack_o;
        wire        wbd_ext_err_o;


	wire [37:0] io_oeb;
	wire [37:0] io_out;
	wire [37:0] io_in;


	reg [1:0] spi_chip_no;

	wire gpio;
	wire [37:0] mprj_io;
	wire [7:0] mprj_io_0;
	reg        test_fail;
	reg [31:0] read_data;




        wire [31:0]   usbd_reg_addr;
       	wire 	      usbd_reg_rdwrn;
       	wire 	      usbd_reg_req;
        wire [31:0]   usbd_reg_wdata;
        reg [31:0]    usbd_reg_rdata;
        reg           usbd_reg_ack = 1'b1;

	reg  [31:0]   RegBank [0:15];





	always #12.5 clock <= (clock === 1'b0);


	always begin
          #USB_HPER     usb_48mhz_clk = 1'b0;
          #USB_HPER     usb_48mhz_clk = 1'b1;
        end


	always begin
          #USER2_HPER     user_clock2 = 1'b0;
          #USER2_HPER     user_clock2 = 1'b1;
        end

	initial begin
		clock = 0;
                wbd_ext_cyc_i ='h0;
                wbd_ext_stb_i ='h0;
                wbd_ext_adr_i ='h0;
                wbd_ext_we_i  ='h0;
                wbd_ext_dat_i ='h0;
                wbd_ext_sel_i ='h0;
	end
	initial begin
		wb_rst_i <= 1'b1;
		#100;
		wb_rst_i <= 1'b0;
	end

	`ifdef WFDUMP
	   initial begin
	   	$dumpfile("simx.vcd");
	   	$dumpvars(0, user_usb_tb);





	   end
       `endif

        always@(posedge wb_rst_i  or posedge usb_48mhz_clk)
	begin
	   if(wb_rst_i == 1'b1) begin
              usbd_reg_rdata = 'h0;
              usbd_reg_ack   = 'h0;
	   end else begin
	      if(usbd_reg_req && usbd_reg_rdwrn == 1'b0 && !usbd_reg_ack) begin
                 usbd_reg_ack = 'h1;
		 RegBank[usbd_reg_addr[5:2]] = usbd_reg_wdata;
		 $display("STATUS: Write Access Address : %x Data: %x",usbd_reg_addr[7:0],usbd_reg_wdata);
	      end else if(usbd_reg_req && usbd_reg_rdwrn == 1'b1 && !usbd_reg_ack) begin
                 usbd_reg_ack = 'h1;
		 usbd_reg_rdata = RegBank[usbd_reg_addr[5:2]];
		 $display("STATUS: Read Access Address : %x Data: %x",usbd_reg_addr[7:0],usbd_reg_rdata);
	      end else begin
                 usbd_reg_ack = 'h0;
	      end
	   end
	end

	initial begin
		$dumpon;

		#200;
	        repeat (10) @(posedge clock);
		$display("Monitor: Standalone User Risc Boot Test Started");

         

                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);


                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h400);

	        repeat (2) @(posedge clock);
		#1;
         

                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);

                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h0,8'h61,8'h0,8'h0});



                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h03F);


		test_fail = 0;
	        repeat (200) @(posedge clock);
                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000);



		usb_test2;


		repeat (100) @(posedge clock);


          	if(test_control.error_count == 0) begin
		   `ifdef GL
	    	       $display("Monitor: USB Mode (GL) Passed");
		   `else
		       $display("Monitor: USB Mode (RTL) Passed");
		   `endif
	        end else begin
		    `ifdef GL
	    	        $display("Monitor: USB Mode (GL) Failed");
		    `else
		        $display("Monitor: USB Mode (RTL) Failed");
		    `endif
		 end
	    	$display("###################################################");
	        $finish;
	end

wire USER_VDD1V8 = 1'b1;
wire VSS = 1'b0;

user_project_wrapper u_top(
`ifdef USE_POWER_PINS
    .vccd1(USER_VDD1V8),
    .vssd1(VSS),
`endif
    .wb_clk_i    (clock       ),
    .user_clock2 (user_clock2 ),
    .wb_rst_i    (wb_rst_i    ),

    .wbs_cyc_i   (wbd_ext_cyc_i),
    .wbs_stb_i   (wbd_ext_stb_i),
    .wbs_adr_i   (wbd_ext_adr_i),
    .wbs_we_i    (wbd_ext_we_i),
    .wbs_dat_i   (wbd_ext_dat_i),
    .wbs_sel_i   (wbd_ext_sel_i),

    .wbs_dat_o   (wbd_ext_dat_o),
    .wbs_ack_o   (wbd_ext_ack_o),

 

    .la_data_in      ('1) ,
    .la_data_out     (),
    .la_oenb         ('0),
 


    .io_in          (io_in)  ,
    .io_out         (io_out) ,
    .io_oeb         (io_oeb) ,

    .user_irq       () 

);
    usb_agent u_usb_agent();
    test_control test_control();

`ifndef GL

    initial begin

    end
`endif  



tri usbd_txdp = (io_oeb[36] == 1'b0) ? io_out[36] : 1'bz;
tri usbd_txdn = (io_oeb[37] == 1'b0) ? io_out[37] : 1'bz;

assign io_in[36] = usbd_txdp;
assign io_in[37] = usbd_txdn;



pullup(usbd_txdp); 
pulldown(usbd_txdn);

usb1d_top u_usb_top(

	.clk_i           (usb_48mhz_clk), 
	.rstn_i          (!wb_rst_i),
 

	.usb_dp          (usbd_txdp), 
	.usb_dn          (usbd_txdn), 
 

	.phy_tx_mode     (1'b1), 
        .usb_rst         (),
 

	.dropped_frame   (), 
	.misaligned_frame(),
	.crc16_err       (),
 

	.v_set_int       (), 
	.v_set_feature   (), 
	.wValue          (),
	.wIndex          (), 
	.vendor_data     (),
 

	.usb_busy        (), 
	.ep_sel          (),
 

	.ep1_cfg         (	`ISO  | `IN  | 14'd0256		),

	.ep1_dout        (					),
	.ep1_we          (					),
	.ep1_full        (		1'b0			),

	.ep1_din         (		8'h0		        ),
	.ep1_re          (		   		        ),
	.ep1_empty       (		1'b0     		),
	.ep1_bf_en       (		1'b0			),
	.ep1_bf_size     (		7'h0			),
 

	.ep2_cfg         (	`ISO  | `OUT | 14'd0256		),

	.ep2_dout        (				        ),
	.ep2_we          (				        ),
	.ep2_full        (		1'b0     		),

	.ep2_din         (		8'h0			),
	.ep2_re          (					),
	.ep2_empty       (		1'b0			),
	.ep2_bf_en       (		1'b0			),
	.ep2_bf_size     (		7'h0			),
 

	.ep3_cfg         (	`BULK | `IN  | 14'd064		),

	.ep3_dout        (					),
	.ep3_we          (					),
	.ep3_full        (		1'b0			),

	.ep3_din         (		8'h0      		),
	.ep3_re          (		        		),
	.ep3_empty       (		1'b0    		),
	.ep3_bf_en       (		1'b0			),
	.ep3_bf_size     (		7'h0			),
 

	.ep4_cfg         (	`BULK | `OUT | 14'd064		),

	.ep4_dout        (		        		),
	.ep4_we          (		        		),
	.ep4_full        (		1'b0     		),

	.ep4_din         (		8'h0			),
	.ep4_re          (					),
	.ep4_empty       (		1'b0			),
	.ep4_bf_en       (		1'b0			),
	.ep4_bf_size     (		7'h0			),
 

	.ep5_cfg         (	`INT  | `IN  | 14'd064		),

	.ep5_dout        (					),
	.ep5_we          (					),
	.ep5_full        (		1'b0			),

	.ep5_din         (		8'h0     		),
	.ep5_re          (				        ),
	.ep5_empty       (		1'b0     		),
	.ep5_bf_en       (		1'b0			),
	.ep5_bf_size     (		7'h0			),
 

	.ep6_cfg         (		14'h00			),

	.ep6_dout        (					),
	.ep6_we          (					),
	.ep6_full        (		1'b0			),

	.ep6_din         (		8'h0			),
	.ep6_re          (					),
	.ep6_empty       (		1'b0			),
	.ep6_bf_en       (		1'b0			),
	.ep6_bf_size     (		7'h0			),
 

	.ep7_cfg         (		14'h00			),

	.ep7_dout        (					),
	.ep7_we          (					),
	.ep7_full        (		1'b0			),

	.ep7_din         (		8'h0			),
	.ep7_re          (					),
	.ep7_empty       (		1'b0			),
	.ep7_bf_en       (		1'b0			),
	.ep7_bf_size     (		7'h0			),
 

	.reg_addr        (usbd_reg_addr),
	.reg_rdwrn       (usbd_reg_rdwrn),
	.reg_req         (usbd_reg_req),
	.reg_wdata       (usbd_reg_wdata),
	.reg_rdata       (usbd_reg_rdata),
	.reg_ack         (usbd_reg_ack)
 
	);





task test_err;
begin
     test_fail = 1;
end
endtask

task wb_user_core_write;
input [31:0] address;
input [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h1;
  wbd_ext_dat_i =data;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  $display("STATUS: WB USER ACCESS WRITE Address : 0x%x, Data : 0x%x",address,data);
  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read;
input [31:0] address;
output [31:0] data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(negedge clock);
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;

  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read_check;
input [31:0] address;
output [31:0] data;
input [31:0] cmp_data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  if(data !== cmp_data) begin
     $display("ERROR : WB USER ACCESS READ  Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
     user_usb_tb.test_fail = 1;
  end else begin
     $display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,data);
  end
  repeat (2) @(posedge clock);
end
endtask


`ifdef GL

wire        wbd_spi_stb_i   = u_top.u_qspi_master.wbd_stb_i;
wire        wbd_spi_ack_o   = u_top.u_qspi_master.wbd_ack_o;
wire        wbd_spi_we_i    = u_top.u_qspi_master.wbd_we_i;
wire [31:0] wbd_spi_adr_i   = u_top.u_qspi_master.wbd_adr_i;
wire [31:0] wbd_spi_dat_i   = u_top.u_qspi_master.wbd_dat_i;
wire [31:0] wbd_spi_dat_o   = u_top.u_qspi_master.wbd_dat_o;
wire [3:0]  wbd_spi_sel_i   = u_top.u_qspi_master.wbd_sel_i;

wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb_spi.reg_cs;
wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb_spi.reg_ack;
wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb_spi.reg_wr;
wire [8:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb_spi.reg_addr;
wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb_spi.reg_wdata;
wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb_spi.reg_rdata;
wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb_spi.reg_be;

`endif


`include "tests/usb_test1.v"
`include "tests/usb_test2.v"

endmodule