data/full_repos/permissive/508266496/sources/CPU.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/508266496/sources/CPU.v:42: Signal definition not found, creating implicitly: \'Jump\'\nassign PC = (Jump) ? JUMPPC : BEQPC;  \n             ^~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/508266496/sources/CPU.v:45: Cannot find file containing module: \'InstructionMemory\'\nInstructionMemory IM(PC, Instruction);\n^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/508266496/sources,data/full_repos/permissive/508266496/InstructionMemory\n             data/full_repos/permissive/508266496/sources,data/full_repos/permissive/508266496/InstructionMemory.v\n             data/full_repos/permissive/508266496/sources,data/full_repos/permissive/508266496/InstructionMemory.sv\n             InstructionMemory\n             InstructionMemory.v\n             InstructionMemory.sv\n             obj_dir/InstructionMemory\n             obj_dir/InstructionMemory.v\n             obj_dir/InstructionMemory.sv\n%Error: data/full_repos/permissive/508266496/sources/CPU.v:47: Cannot find file containing module: \'DataPath\'\nDataPath DP(Clock, PC, RegDst,\n^~~~~~~~\n%Error: data/full_repos/permissive/508266496/sources/CPU.v:58: Cannot find file containing module: \'ControlUnit\'\nControlUnit CU(Instruction[15:10],RegDst,\n^~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module CPU(input Clock);

reg[15:0] PC_Initial;
reg[15:0] PCPlus4;
reg[15:0] PC;
reg[15:0] PC_CURRENT;
reg[15:0] PC_BEQ;
reg[15:0] PC_JUMP;
wire[15:0] Instruction;
wire[15:0] BEQPC;
wire[15:0] JUMPPC;

initial
begin
assign PC_Initial = 16'd0;
end

always@(posedge Clock)
begin
assign PC = (Jump) ? JUMPPC : BEQPC;
end

InstructionMemory IM(PC, Instruction);

DataPath DP(Clock, PC, RegDst,
Jump,
Branch,
MemRead,
MemWrite,
MemToReg,
ALUSrc,
RegWrite,
ALUOp,
Instruction, BEQPC, JUMPPC);

ControlUnit CU(Instruction[15:10],RegDst,
Jump,
Branch,
MemRead,
MemWrite,
MemToReg,
ALUSrc,
RegWrite,
ALUOp);

endmodule
module CPU(input Clock);


reg[15:0] PC_Initial;
reg[15:0] PCPlus4;
reg[15:0] PC;
reg[15:0] PC_CURRENT;
reg[15:0] PC_BEQ;
reg[15:0] PC_JUMP;
wire[15:0] Instruction;
wire[15:0] BEQPC;
wire[15:0] JUMPPC;

initial
begin
assign PC_Initial = 16'd0;
end

always@(posedge Clock)
begin
assign PC = (Jump) ? JUMPPC : BEQPC;
end

InstructionMemory IM(PC, Instruction);

DataPath DP(Clock, PC, RegDst,
Jump,
Branch,
MemRead,
MemWrite,
MemToReg,
ALUSrc,
RegWrite,
ALUOp,
Instruction, BEQPC, JUMPPC);

ControlUnit CU(Instruction[15:10],RegDst,
Jump,
Branch,
MemRead,
MemWrite,
MemToReg,
ALUSrc,
RegWrite,
ALUOp);

endmodule