data/full_repos/permissive/410272426/hardware_code_radix-2/common_lib.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/410272426/hardware_code_radix-2/common_lib.v:36: Multiple top level modules\n                                                                                             : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                             : ... Top module \'DFF\'\nmodule DFF #(parameter data_width = 14)(\n       ^~~\n                                                                                             : ... Top module \'shift_8\'\nmodule shift_8 #(parameter data_width = 14)(\n       ^~~~~~~\n                                                                                             : ... Top module \'shift_7\'\nmodule shift_7 #(parameter data_width = 14)(\n       ^~~~~~~\n                                                                                             : ... Top module \'shift_4\'\nmodule shift_4 #(parameter data_width = 14)(\n       ^~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module shift_4 #(parameter data_width = 14)(
    input [data_width-1:0] din,
	input rst,clk,
	output wire [data_width-1:0] dout
	);
	
	reg [data_width-1:0] t0,t1,t2,t3;
	
	always@(posedge clk or posedge rst)
	begin
	  if(rst) begin
	    t0 <= 0; t1 <= 0; t2 <= 0; t3 <= 0;
	    end
	  else begin
	    t0 <= din;
	    t1 <= t0; t2 <= t1; t3 <= t2;
	  end
	end
	
	assign dout = t3;
endmodule
module shift_4 #(parameter data_width = 14)(
    input [data_width-1:0] din,
	input rst,clk,
	output wire [data_width-1:0] dout
	);

	
	reg [data_width-1:0] t0,t1,t2,t3;
	
	always@(posedge clk or posedge rst)
	begin
	  if(rst) begin
	    t0 <= 0; t1 <= 0; t2 <= 0; t3 <= 0;
	    end
	  else begin
	    t0 <= din;
	    t1 <= t0; t2 <= t1; t3 <= t2;
	  end
	end
	
	assign dout = t3;
endmodule