data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_1r2w_vec.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_1r2w_vec.v:29: Cannot find include file: sys.h\n`include "sys.h" // system level definition file which contains the  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: Exiting due to 1 error(s)\n'
module iobdg_1r2w_vec (

   dout, dout_vec, 

   clk, rst_l, tx_en, rd_a, wr1_a, wr2_a, din1, din2, wen1, wen2
   );

   parameter WIDTH = 32;
   parameter INDEX = 5;
   
   



   input                     clk;
   input 		     rst_l;
   input 		     tx_en;
   
   input [INDEX-1:0] 	     rd_a;
   input [INDEX-1:0] 	     wr1_a;
   input [INDEX-1:0] 	     wr2_a;
   input 		     din1;
   input 		     din2;
   input 		     wen1;
   input 		     wen2;
   
   output 		     dout;
   output [WIDTH-1:0] 	     dout_vec;
   
   wire [INDEX-1:0] 	     wr1_a_d1;
   wire [INDEX-1:0] 	     wr2_a_d1;
   wire 		     din1_d1;
   wire 		     din2_d1;
   wire 		     wen1_d1;
   wire 		     wen2_d1;
   wire [WIDTH-1:0] 	     wr1_a_dec_d1;
   wire [WIDTH-1:0] 	     wr2_a_dec_d1;
   wire [WIDTH-1:0] 	     wen1_dec_d1;
   wire [WIDTH-1:0] 	     wen2_dec_d1;
   wire [WIDTH-1:0] 	     vec;
   reg [WIDTH-1:0] 	     vec_next;
   wire [INDEX-1:0] 	     rd_a_d1;
   wire [WIDTH-1:0] 	     rd_a_dec_d1;
   wire 		     dout;
   
   integer 		     i;

   




   dff_ns #(INDEX) wr1_a_d1_ff (.din(wr1_a),
			   	.clk(clk),
			   	.q(wr1_a_d1));

   dff_ns #(INDEX) wr2_a_d1_ff (.din(wr2_a),
			   	.clk(clk),
			   	.q(wr2_a_d1));

   dff_ns #(1) din1_d1_ff (.din(din1),
			   .clk(clk),
			   .q(din1_d1));

   dff_ns #(1) din2_d1_ff (.din(din2),
			   .clk(clk),
			   .q(din2_d1));

   dff_ns #(1) wen1_d1_ff (.din(wen1),
			   .clk(clk),
			   .q(wen1_d1));

   dff_ns #(1) wen2_d1_ff (.din(wen2),
			   .clk(clk),
			   .q(wen2_d1));

   assign 	     wr1_a_dec_d1 = 1'b1 << wr1_a_d1;
   
   assign 	     wr2_a_dec_d1 = 1'b1 << wr2_a_d1;
   
   assign 	     wen1_dec_d1 = {WIDTH{wen1_d1}} & wr1_a_dec_d1;

   assign 	     wen2_dec_d1 = {WIDTH{wen2_d1}} & wr2_a_dec_d1;

   always @(din1_d1 or din2_d1 or rst_l or vec
	    or wen1_dec_d1 or wen2_dec_d1)
     begin
   	for (i=0; i<WIDTH; i=i+1)
	  begin
	     vec_next[i] = ~rst_l         ? 1'b0    :
			   wen1_dec_d1[i] ? din1_d1 :
			   wen2_dec_d1[i] ? din2_d1 :
			                    vec[i];
	  end
     end


   dff_ns #(WIDTH) vec_ff (.din(vec_next),
			   .clk(clk),
			   .q(vec));
   

   dffe_ns #(WIDTH) dout_vec_ff (.din(vec),
				 .en(tx_en),
				 .clk(clk),
				 .q(dout_vec));
   


   dff_ns #(INDEX) rd_a_d1_ff (.din(rd_a),
			       .clk(clk),
			       .q(rd_a_d1));

   assign            rd_a_dec_d1 = 1'b1 << rd_a_d1;
   
   assign 	     dout = |(vec & rd_a_dec_d1);

   
endmodule
module iobdg_1r2w_vec (

   dout, dout_vec, 

   clk, rst_l, tx_en, rd_a, wr1_a, wr2_a, din1, din2, wen1, wen2
   );


   parameter WIDTH = 32;
   parameter INDEX = 5;
   
   



   input                     clk;
   input 		     rst_l;
   input 		     tx_en;
   
   input [INDEX-1:0] 	     rd_a;
   input [INDEX-1:0] 	     wr1_a;
   input [INDEX-1:0] 	     wr2_a;
   input 		     din1;
   input 		     din2;
   input 		     wen1;
   input 		     wen2;
   
   output 		     dout;
   output [WIDTH-1:0] 	     dout_vec;
   
   wire [INDEX-1:0] 	     wr1_a_d1;
   wire [INDEX-1:0] 	     wr2_a_d1;
   wire 		     din1_d1;
   wire 		     din2_d1;
   wire 		     wen1_d1;
   wire 		     wen2_d1;
   wire [WIDTH-1:0] 	     wr1_a_dec_d1;
   wire [WIDTH-1:0] 	     wr2_a_dec_d1;
   wire [WIDTH-1:0] 	     wen1_dec_d1;
   wire [WIDTH-1:0] 	     wen2_dec_d1;
   wire [WIDTH-1:0] 	     vec;
   reg [WIDTH-1:0] 	     vec_next;
   wire [INDEX-1:0] 	     rd_a_d1;
   wire [WIDTH-1:0] 	     rd_a_dec_d1;
   wire 		     dout;
   
   integer 		     i;

   




   dff_ns #(INDEX) wr1_a_d1_ff (.din(wr1_a),
			   	.clk(clk),
			   	.q(wr1_a_d1));

   dff_ns #(INDEX) wr2_a_d1_ff (.din(wr2_a),
			   	.clk(clk),
			   	.q(wr2_a_d1));

   dff_ns #(1) din1_d1_ff (.din(din1),
			   .clk(clk),
			   .q(din1_d1));

   dff_ns #(1) din2_d1_ff (.din(din2),
			   .clk(clk),
			   .q(din2_d1));

   dff_ns #(1) wen1_d1_ff (.din(wen1),
			   .clk(clk),
			   .q(wen1_d1));

   dff_ns #(1) wen2_d1_ff (.din(wen2),
			   .clk(clk),
			   .q(wen2_d1));

   assign 	     wr1_a_dec_d1 = 1'b1 << wr1_a_d1;
   
   assign 	     wr2_a_dec_d1 = 1'b1 << wr2_a_d1;
   
   assign 	     wen1_dec_d1 = {WIDTH{wen1_d1}} & wr1_a_dec_d1;

   assign 	     wen2_dec_d1 = {WIDTH{wen2_d1}} & wr2_a_dec_d1;

   always @(din1_d1 or din2_d1 or rst_l or vec
	    or wen1_dec_d1 or wen2_dec_d1)
     begin
   	for (i=0; i<WIDTH; i=i+1)
	  begin
	     vec_next[i] = ~rst_l         ? 1'b0    :
			   wen1_dec_d1[i] ? din1_d1 :
			   wen2_dec_d1[i] ? din2_d1 :
			                    vec[i];
	  end
     end


   dff_ns #(WIDTH) vec_ff (.din(vec_next),
			   .clk(clk),
			   .q(vec));
   

   dffe_ns #(WIDTH) dout_vec_ff (.din(vec),
				 .en(tx_en),
				 .clk(clk),
				 .q(dout_vec));
   


   dff_ns #(INDEX) rd_a_d1_ff (.din(rd_a),
			       .clk(clk),
			       .q(rd_a_d1));

   assign            rd_a_dec_d1 = 1'b1 << rd_a_d1;
   
   assign 	     dout = |(vec & rd_a_dec_d1);

   
endmodule