data/full_repos/permissive/481307378/source_files/unalign_mem_access/dp_cu_for_unalign_mem_access/proc.v
1: b'%Warning-WIDTH: data/full_repos/permissive/481307378/source_files/unalign_mem_access/dp_cu_for_unalign_mem_access/proc.v:102: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'irq_id\' generates 5 bits.\n                                                                                                                            : ... In instance proc\n assign irq_adr = (irq_id << 2) + 32\'h1C00_8000; \n                          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/481307378/source_files/unalign_mem_access/dp_cu_for_unalign_mem_access/proc.v:120: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n                                                                                                                            : ... In instance proc\n assign n = ALU_result % 4;\n          ^\n%Error: data/full_repos/permissive/481307378/source_files/unalign_mem_access/dp_cu_for_unalign_mem_access/proc.v:125: Cannot find file containing module: \'MUX_2x1_32\'\n MUX_2x1_32 JMP_ADR_SELECT(.I0(instr_adr + imm_gen_output), .I1(Read_data_1 + imm_gen_output), .S(reg_pc_select), .Y(Jmp_adr));  \n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/481307378/source_files/unalign_mem_access/dp_cu_for_unalign_mem_access,data/full_repos/permissive/481307378/MUX_2x1_32\n             data/full_repos/permissive/481307378/source_files/unalign_mem_access/dp_cu_for_unalign_mem_access,data/full_repos/permissive/481307378/MUX_2x1_32.v\n             data/full_repos/permissive/481307378/source_files/unalign_mem_access/dp_cu_for_unalign_mem_access,data/full_repos/permissive/481307378/MUX_2x1_32.sv\n             MUX_2x1_32\n             MUX_2x1_32.v\n             MUX_2x1_32.sv\n             obj_dir/MUX_2x1_32\n             obj_dir/MUX_2x1_32.v\n             obj_dir/MUX_2x1_32.sv\n%Error: data/full_repos/permissive/481307378/source_files/unalign_mem_access/dp_cu_for_unalign_mem_access/proc.v:126: Cannot find file containing module: \'REG_DRE_32\'\n REG_DRE_32 Instruction_Backup_Reg(.D(instr_adr), .Q(ret_adr), .CLK(clk), .RES(res), .ENABLE(bckup_reg));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/481307378/source_files/unalign_mem_access/dp_cu_for_unalign_mem_access/proc.v:127: Cannot find file containing module: \'MUX_2x1_32\'\n MUX_2x1_32 Instruction_Select_1(.I0(Jmp_adr), .I1(irq_adr), .S(irq_addr_sel), .Y(j_adr_1));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/481307378/source_files/unalign_mem_access/dp_cu_for_unalign_mem_access/proc.v:128: Cannot find file containing module: \'MUX_2x1_32\'\n MUX_2x1_32 Instruction_Select_2(.I0(j_adr_1), .I1(ret_adr), .S(mret_sel), .Y(j_adr_2));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/481307378/source_files/unalign_mem_access/dp_cu_for_unalign_mem_access/proc.v:129: Cannot find file containing module: \'pc\'\n pc PC(.CLK(clk), .RES(res), .ENABLE(pc_enable), .MODE(PCSrc), .D(j_adr_2), .PC_OUT(instr_adr));  \n ^~\n%Error: data/full_repos/permissive/481307378/source_files/unalign_mem_access/dp_cu_for_unalign_mem_access/proc.v:134: Cannot find file containing module: \'REG_DRE_32\'\n REG_DRE_32 INSTR_PIPELINE_REG(.D(instr_read_in), .Q(instr_read), .CLK(clk), .RES(res), .ENABLE(instr_r_valid));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/481307378/source_files/unalign_mem_access/dp_cu_for_unalign_mem_access/proc.v:163: Cannot find file containing module: \'ctrl\'\n ctrl CU(.RES(res), .CLK(clk), .opcode(Opcode), .MODE(Branch), \n ^~~~\n%Error: data/full_repos/permissive/481307378/source_files/unalign_mem_access/dp_cu_for_unalign_mem_access/proc.v:179: Cannot find file containing module: \'regset\'\n regset Register_Set(.D(Write_data), .A_D(Write_register), .A_Q0(Read_register_1), .A_Q1(Read_register_2),  \n ^~~~~~\n%Error: data/full_repos/permissive/481307378/source_files/unalign_mem_access/dp_cu_for_unalign_mem_access/proc.v:204: Cannot find file containing module: \'MUX_2x1_32\'\n MUX_2x1_32 MUX_ALU_1(.I0(Read_data_1), .I1(instr_adr), .S(ALUSrc1), .Y(ALU_A_1));  \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/481307378/source_files/unalign_mem_access/dp_cu_for_unalign_mem_access/proc.v:205: Cannot find file containing module: \'MUX_2x1_32\'\n MUX_2x1_32 MUX_ALU_1_5(.I0(ALU_A_1), .I1(32\'d0), .S(ALUSrc1_5), .Y(ALU_A));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/481307378/source_files/unalign_mem_access/dp_cu_for_unalign_mem_access/proc.v:207: Cannot find file containing module: \'MUX_2x1_32\'\n MUX_2x1_32 MUX_ALU_2(.I0(Read_data_2), .I1(imm_gen_output), .S(ALUSrc2), .Y(ALU_B_1));  \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/481307378/source_files/unalign_mem_access/dp_cu_for_unalign_mem_access/proc.v:208: Cannot find file containing module: \'MUX_2x1_32\'\n MUX_2x1_32 MUX_ALU_2_5(.I0(ALU_B_1), .I1(32\'d4), .S(ALUSrc2_5), .Y(ALU_B));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/481307378/source_files/unalign_mem_access/dp_cu_for_unalign_mem_access/proc.v:210: Cannot find file containing module: \'alu_ctrl\'\n alu_ctrl alu_ctrl(.Instr(instr_read), .AluOp(ALU_control));\n ^~~~~~~~\n%Error: data/full_repos/permissive/481307378/source_files/unalign_mem_access/dp_cu_for_unalign_mem_access/proc.v:211: Cannot find file containing module: \'alu\'\n alu ALU(.S(ALU_control), .A(ALU_A), .B(ALU_B), .CMP(Zero), .Q(ALU_result));  \n ^~~\n%Error: data/full_repos/permissive/481307378/source_files/unalign_mem_access/dp_cu_for_unalign_mem_access/proc.v:220: Cannot find file containing module: \'MUX_2x1_32\'\n MUX_2x1_32 MUX_DM_ADDR_SELECT(.I0(ALU_result), .I1(ALU_result + 32\'d4), .S(dm_addr_select), .Y(data_adr));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/481307378/source_files/unalign_mem_access/dp_cu_for_unalign_mem_access/proc.v:221: Cannot find file containing module: \'REG_DRE_32\'\n REG_DRE_32 before_data_merge_reg(.D(data_read), .Q(before_data_merge_wire), .CLK(clk), .RES(res), .ENABLE(merge_reg_write_enable));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/481307378/source_files/unalign_mem_access/dp_cu_for_unalign_mem_access/proc.v:223: Cannot find file containing module: \'MUX_2x1_32\'\n MUX_2x1_32 MUX_DATA(.I0(ALU_result), .I1(data_read), .S(MemtoReg), .Y(Write_data_pre));  \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/481307378/source_files/unalign_mem_access/dp_cu_for_unalign_mem_access/proc.v:224: Cannot find file containing module: \'MUX_2x1_32\'\n MUX_2x1_32 MUX_ALU_DM_UNALIGN_SELECT(.I0(Write_data_pre), .I1(after_data_merge_wire), .S(alu_dm_unalign_select), .Y(Write_data));\n ^~~~~~~~~~\n%Error: Exiting due to 18 error(s), 2 warning(s)\n'
module proc(
	input clk,
	input res,
	input [31 : 0] instr_read_in,
	input instr_gnt,
	input instr_r_valid,
	input [31 : 0] data_read,
	input data_gnt,
	input data_r_valid,
	input irq,
	input [4 : 0] irq_id,
	
	output [31 : 0] instr_adr,
	output instr_req,
    output [31 : 0] data_write,
	output [31 : 0] data_adr,
	output data_req,
	output data_write_enable,
	output [3 : 0] data_be,
	output irq_ack,
	output [4 : 0] irq_ack_id
);




	wire PCSrc;
	wire pc_enable;
	wire [31 : 0] Jmp_adr;
	wire [31 : 0] irq_adr;
	wire [31 : 0] ret_adr;
	wire [31 : 0] j_adr_1;
	wire irq_addr_sel;
	wire [31 : 0] j_adr_2;
	wire mret_sel;
	wire bckup_reg;
	wire reg_pc_select; 
	wire irq_pc_mode;


	wire [31 : 0] instr_read;
	wire [31 : 0] instr_reg;


	wire [6 : 0] Opcode;
	wire Branch;
	wire MemtoReg;
	wire ALUSrc1;
	wire ALUSrc2;
	wire ALUSrc1_5;
	wire ALUSrc2_5;
	wire RegWrite;

	wire irq_context;
	wire irq_status_update;
	reg irq_status_reg;
	reg [4 : 0] irq_ack_id_reg;

	wire[2 : 0] funct3;
	wire [1 : 0] n;
	wire merge_reg_write_enable;
    wire dm_addr_select;
    wire alu_dm_unalign_select;


	wire [4 : 0] Read_register_1;
	wire [4 : 0] Read_register_2;
	wire [4 : 0] Write_register;
	wire [31 : 0] Write_data;
	wire [31 : 0]Read_data_1;
	wire [31 : 0] Read_data_2;


	reg [31 : 0] imm_gen_output;
	wire [31 : 0] imm_gen_output_lshifted;


	wire[4 : 0] ALU_control;
	wire [31 : 0] ALU_A;
	wire [31 : 0] ALU_A_1;
	wire [31 : 0] ALU_B;
	wire [31 : 0] ALU_B_1;
	wire [31 : 0] ALU_result;
	wire Zero;




	assign PCSrc = (Branch & Zero) | irq_pc_mode;
	assign irq_adr = (irq_id << 2) + 32'h1C00_8000; 


	assign Opcode = instr_read[6 : 0];


	assign Read_register_1 = instr_read[19 : 15];
	assign Read_register_2 = instr_read[24 : 20];
	assign Write_register = instr_read[11 : 7];



	

	assign irq_ack_id = irq_ack_id_reg;


	assign funct3 = instr_read[14 : 12];
	assign n = ALU_result % 4;




	MUX_2x1_32 JMP_ADR_SELECT(.I0(instr_adr + imm_gen_output), .I1(Read_data_1 + imm_gen_output), .S(reg_pc_select), .Y(Jmp_adr));
	REG_DRE_32 Instruction_Backup_Reg(.D(instr_adr), .Q(ret_adr), .CLK(clk), .RES(res), .ENABLE(bckup_reg));
	MUX_2x1_32 Instruction_Select_1(.I0(Jmp_adr), .I1(irq_adr), .S(irq_addr_sel), .Y(j_adr_1));
	MUX_2x1_32 Instruction_Select_2(.I0(j_adr_1), .I1(ret_adr), .S(mret_sel), .Y(j_adr_2));
	pc PC(.CLK(clk), .RES(res), .ENABLE(pc_enable), .MODE(PCSrc), .D(j_adr_2), .PC_OUT(instr_adr));




	REG_DRE_32 INSTR_PIPELINE_REG(.D(instr_read_in), .Q(instr_read), .CLK(clk), .RES(res), .ENABLE(instr_r_valid));




	always @(posedge clk, posedge res)
	begin
	    if(res == 1'b1)
        begin
            irq_status_reg <= 1'b0;
        end
		else if(irq_status_update)
		begin
        	irq_status_reg <= irq_context;
        end
	end

	always @(posedge clk, posedge res)
	begin
	    if(res == 1'b1)
        begin
            irq_ack_id_reg <= 5'b00000;
        end
        else if(irq_status_update)
        begin
        	irq_ack_id_reg <= irq_id;
        end
	end

	ctrl CU(.RES(res), .CLK(clk), .opcode(Opcode), .MODE(Branch), 
			.instr_req(instr_req), .instr_gnt(instr_gnt), .instr_r_valid(instr_r_valid),
			.write_enable(RegWrite), .ALUSrcMux1(ALUSrc1), .ALUSrcMux1_S(ALUSrc1_5), .ALUSrcMux2(ALUSrc2), 
			.ALUSrcMux2_S(ALUSrc2_5), .reg_pc_select(reg_pc_select),
			.alu_dm_select(MemtoReg),
			.data_write_enable(data_write_enable), .data_req(data_req), .data_gnt(data_gnt),
			.data_r_valid(data_r_valid), .bckup_reg(bckup_reg),
			.irq_addr_sel(irq_addr_sel), .mret_sel(mret_sel), .irq(irq), .irq_ack(irq_ack), .irq_context(irq_context), .irq_status(irq_status_reg),
			.irq_status_update(irq_status_update),.pc_enable(pc_enable),
			.irq_pc_mode(irq_pc_mode), .funct3(funct3), .n(n), data_be(data_be),
			.merge_reg_write_enable(merge_reg_write_enable), .dm_addr_select(dm_addr_select),
			.alu_dm_unalign_select(alu_dm_unalign_select));




	regset Register_Set(.D(Write_data), .A_D(Write_register), .A_Q0(Read_register_1), .A_Q1(Read_register_2),
	                    .write_enable(RegWrite), .RES(res), .CLK(clk), .Q0(Read_data_1), .Q1(Read_data_2));


	always @(instr_read)
	begin
	   imm_gen_output <= 32'd0;
	   
		casez(instr_read[6 : 0])
			`OPCODE_OPIMM, `OPCODE_CSRRS: imm_gen_output <= { {20{instr_read[31]}}, instr_read[31 : 20] };
			`OPCODE_STORE: imm_gen_output <= { {20{instr_read[31]}}, instr_read[31 : 25], instr_read[11 : 7] };
			`OPCODE_LOAD: imm_gen_output <= { {20{instr_read[31]}}, instr_read[31 : 20] };
			`OPCODE_BRANCH: imm_gen_output <= { {19{instr_read[31]}} ,instr_read[31], instr_read[7], instr_read[30 : 25], instr_read[11 : 8], 1'b0};
			`OPCODE_JALR: imm_gen_output <= { {20{instr_read[31]}}, instr_read[31 : 20] };
			`OPCODE_JAL: imm_gen_output <= { {11{instr_read[31]}}, instr_read[31], instr_read[19 : 12], instr_read[20], instr_read[30 : 21], 1'b0};
			`OPCODE_AUIPC: imm_gen_output <= {instr_read[31 : 12], {12{1'b0}} };
			`OPCODE_LUI: imm_gen_output <= {instr_read[31 : 12], {12{1'b0}} };

			default: imm_gen_output <= 32'd0;

		endcase
	end
	


	MUX_2x1_32 MUX_ALU_1(.I0(Read_data_1), .I1(instr_adr), .S(ALUSrc1), .Y(ALU_A_1));
	MUX_2x1_32 MUX_ALU_1_5(.I0(ALU_A_1), .I1(32'd0), .S(ALUSrc1_5), .Y(ALU_A));
	
	MUX_2x1_32 MUX_ALU_2(.I0(Read_data_2), .I1(imm_gen_output), .S(ALUSrc2), .Y(ALU_B_1));
	MUX_2x1_32 MUX_ALU_2_5(.I0(ALU_B_1), .I1(32'd4), .S(ALUSrc2_5), .Y(ALU_B));
	
	alu_ctrl alu_ctrl(.Instr(instr_read), .AluOp(ALU_control));
	alu ALU(.S(ALU_control), .A(ALU_A), .B(ALU_B), .CMP(Zero), .Q(ALU_result));
	




	wire [31 : 0] before_data_merge_wire;
	wire [31 : 0] after_data_merge_wire;
	wire [31 : 0] Write_data_pre;
	MUX_2x1_32 MUX_DM_ADDR_SELECT(.I0(ALU_result), .I1(ALU_result + 32'd4), .S(dm_addr_select), .Y(data_adr));
	REG_DRE_32 before_data_merge_reg(.D(data_read), .Q(before_data_merge_wire), .CLK(clk), .RES(res), .ENABLE(merge_reg_write_enable));
	assign after_data_merge_wire = before_data_merge_wire | data_read;
	MUX_2x1_32 MUX_DATA(.I0(ALU_result), .I1(data_read), .S(MemtoReg), .Y(Write_data_pre));
	MUX_2x1_32 MUX_ALU_DM_UNALIGN_SELECT(.I0(Write_data_pre), .I1(after_data_merge_wire), .S(alu_dm_unalign_select), .Y(Write_data));

	assign data_write = Read_data_2;




	

endmodule
module proc(
	input clk,
	input res,
	input [31 : 0] instr_read_in,
	input instr_gnt,
	input instr_r_valid,
	input [31 : 0] data_read,
	input data_gnt,
	input data_r_valid,
	input irq,
	input [4 : 0] irq_id,
	
	output [31 : 0] instr_adr,
	output instr_req,
    output [31 : 0] data_write,
	output [31 : 0] data_adr,
	output data_req,
	output data_write_enable,
	output [3 : 0] data_be,
	output irq_ack,
	output [4 : 0] irq_ack_id
);





	wire PCSrc;
	wire pc_enable;
	wire [31 : 0] Jmp_adr;
	wire [31 : 0] irq_adr;
	wire [31 : 0] ret_adr;
	wire [31 : 0] j_adr_1;
	wire irq_addr_sel;
	wire [31 : 0] j_adr_2;
	wire mret_sel;
	wire bckup_reg;
	wire reg_pc_select; 
	wire irq_pc_mode;


	wire [31 : 0] instr_read;
	wire [31 : 0] instr_reg;


	wire [6 : 0] Opcode;
	wire Branch;
	wire MemtoReg;
	wire ALUSrc1;
	wire ALUSrc2;
	wire ALUSrc1_5;
	wire ALUSrc2_5;
	wire RegWrite;

	wire irq_context;
	wire irq_status_update;
	reg irq_status_reg;
	reg [4 : 0] irq_ack_id_reg;

	wire[2 : 0] funct3;
	wire [1 : 0] n;
	wire merge_reg_write_enable;
    wire dm_addr_select;
    wire alu_dm_unalign_select;


	wire [4 : 0] Read_register_1;
	wire [4 : 0] Read_register_2;
	wire [4 : 0] Write_register;
	wire [31 : 0] Write_data;
	wire [31 : 0]Read_data_1;
	wire [31 : 0] Read_data_2;


	reg [31 : 0] imm_gen_output;
	wire [31 : 0] imm_gen_output_lshifted;


	wire[4 : 0] ALU_control;
	wire [31 : 0] ALU_A;
	wire [31 : 0] ALU_A_1;
	wire [31 : 0] ALU_B;
	wire [31 : 0] ALU_B_1;
	wire [31 : 0] ALU_result;
	wire Zero;




	assign PCSrc = (Branch & Zero) | irq_pc_mode;
	assign irq_adr = (irq_id << 2) + 32'h1C00_8000; 


	assign Opcode = instr_read[6 : 0];


	assign Read_register_1 = instr_read[19 : 15];
	assign Read_register_2 = instr_read[24 : 20];
	assign Write_register = instr_read[11 : 7];



	

	assign irq_ack_id = irq_ack_id_reg;


	assign funct3 = instr_read[14 : 12];
	assign n = ALU_result % 4;




	MUX_2x1_32 JMP_ADR_SELECT(.I0(instr_adr + imm_gen_output), .I1(Read_data_1 + imm_gen_output), .S(reg_pc_select), .Y(Jmp_adr));
	REG_DRE_32 Instruction_Backup_Reg(.D(instr_adr), .Q(ret_adr), .CLK(clk), .RES(res), .ENABLE(bckup_reg));
	MUX_2x1_32 Instruction_Select_1(.I0(Jmp_adr), .I1(irq_adr), .S(irq_addr_sel), .Y(j_adr_1));
	MUX_2x1_32 Instruction_Select_2(.I0(j_adr_1), .I1(ret_adr), .S(mret_sel), .Y(j_adr_2));
	pc PC(.CLK(clk), .RES(res), .ENABLE(pc_enable), .MODE(PCSrc), .D(j_adr_2), .PC_OUT(instr_adr));




	REG_DRE_32 INSTR_PIPELINE_REG(.D(instr_read_in), .Q(instr_read), .CLK(clk), .RES(res), .ENABLE(instr_r_valid));




	always @(posedge clk, posedge res)
	begin
	    if(res == 1'b1)
        begin
            irq_status_reg <= 1'b0;
        end
		else if(irq_status_update)
		begin
        	irq_status_reg <= irq_context;
        end
	end

	always @(posedge clk, posedge res)
	begin
	    if(res == 1'b1)
        begin
            irq_ack_id_reg <= 5'b00000;
        end
        else if(irq_status_update)
        begin
        	irq_ack_id_reg <= irq_id;
        end
	end

	ctrl CU(.RES(res), .CLK(clk), .opcode(Opcode), .MODE(Branch), 
			.instr_req(instr_req), .instr_gnt(instr_gnt), .instr_r_valid(instr_r_valid),
			.write_enable(RegWrite), .ALUSrcMux1(ALUSrc1), .ALUSrcMux1_S(ALUSrc1_5), .ALUSrcMux2(ALUSrc2), 
			.ALUSrcMux2_S(ALUSrc2_5), .reg_pc_select(reg_pc_select),
			.alu_dm_select(MemtoReg),
			.data_write_enable(data_write_enable), .data_req(data_req), .data_gnt(data_gnt),
			.data_r_valid(data_r_valid), .bckup_reg(bckup_reg),
			.irq_addr_sel(irq_addr_sel), .mret_sel(mret_sel), .irq(irq), .irq_ack(irq_ack), .irq_context(irq_context), .irq_status(irq_status_reg),
			.irq_status_update(irq_status_update),.pc_enable(pc_enable),
			.irq_pc_mode(irq_pc_mode), .funct3(funct3), .n(n), data_be(data_be),
			.merge_reg_write_enable(merge_reg_write_enable), .dm_addr_select(dm_addr_select),
			.alu_dm_unalign_select(alu_dm_unalign_select));




	regset Register_Set(.D(Write_data), .A_D(Write_register), .A_Q0(Read_register_1), .A_Q1(Read_register_2),
	                    .write_enable(RegWrite), .RES(res), .CLK(clk), .Q0(Read_data_1), .Q1(Read_data_2));


	always @(instr_read)
	begin
	   imm_gen_output <= 32'd0;
	   
		casez(instr_read[6 : 0])
			`OPCODE_OPIMM, `OPCODE_CSRRS: imm_gen_output <= { {20{instr_read[31]}}, instr_read[31 : 20] };
			`OPCODE_STORE: imm_gen_output <= { {20{instr_read[31]}}, instr_read[31 : 25], instr_read[11 : 7] };
			`OPCODE_LOAD: imm_gen_output <= { {20{instr_read[31]}}, instr_read[31 : 20] };
			`OPCODE_BRANCH: imm_gen_output <= { {19{instr_read[31]}} ,instr_read[31], instr_read[7], instr_read[30 : 25], instr_read[11 : 8], 1'b0};
			`OPCODE_JALR: imm_gen_output <= { {20{instr_read[31]}}, instr_read[31 : 20] };
			`OPCODE_JAL: imm_gen_output <= { {11{instr_read[31]}}, instr_read[31], instr_read[19 : 12], instr_read[20], instr_read[30 : 21], 1'b0};
			`OPCODE_AUIPC: imm_gen_output <= {instr_read[31 : 12], {12{1'b0}} };
			`OPCODE_LUI: imm_gen_output <= {instr_read[31 : 12], {12{1'b0}} };

			default: imm_gen_output <= 32'd0;

		endcase
	end
	


	MUX_2x1_32 MUX_ALU_1(.I0(Read_data_1), .I1(instr_adr), .S(ALUSrc1), .Y(ALU_A_1));
	MUX_2x1_32 MUX_ALU_1_5(.I0(ALU_A_1), .I1(32'd0), .S(ALUSrc1_5), .Y(ALU_A));
	
	MUX_2x1_32 MUX_ALU_2(.I0(Read_data_2), .I1(imm_gen_output), .S(ALUSrc2), .Y(ALU_B_1));
	MUX_2x1_32 MUX_ALU_2_5(.I0(ALU_B_1), .I1(32'd4), .S(ALUSrc2_5), .Y(ALU_B));
	
	alu_ctrl alu_ctrl(.Instr(instr_read), .AluOp(ALU_control));
	alu ALU(.S(ALU_control), .A(ALU_A), .B(ALU_B), .CMP(Zero), .Q(ALU_result));
	




	wire [31 : 0] before_data_merge_wire;
	wire [31 : 0] after_data_merge_wire;
	wire [31 : 0] Write_data_pre;
	MUX_2x1_32 MUX_DM_ADDR_SELECT(.I0(ALU_result), .I1(ALU_result + 32'd4), .S(dm_addr_select), .Y(data_adr));
	REG_DRE_32 before_data_merge_reg(.D(data_read), .Q(before_data_merge_wire), .CLK(clk), .RES(res), .ENABLE(merge_reg_write_enable));
	assign after_data_merge_wire = before_data_merge_wire | data_read;
	MUX_2x1_32 MUX_DATA(.I0(ALU_result), .I1(data_read), .S(MemtoReg), .Y(Write_data_pre));
	MUX_2x1_32 MUX_ALU_DM_UNALIGN_SELECT(.I0(Write_data_pre), .I1(after_data_merge_wire), .S(alu_dm_unalign_select), .Y(Write_data));

	assign data_write = Read_data_2;




	

endmodule