data/full_repos/permissive/504478691/oscilloscope/tb_I2C.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/504478691/oscilloscope/tb_I2C.v:14: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/504478691/oscilloscope/tb_I2C.v:6: Cannot find file containing module: \'ADC\'\nADC inst(.clk(clk), .sw(),\n^~~\n        ... Looked in:\n             data/full_repos/permissive/504478691/oscilloscope,data/full_repos/permissive/504478691/ADC\n             data/full_repos/permissive/504478691/oscilloscope,data/full_repos/permissive/504478691/ADC.v\n             data/full_repos/permissive/504478691/oscilloscope,data/full_repos/permissive/504478691/ADC.sv\n             ADC\n             ADC.v\n             ADC.sv\n             obj_dir/ADC\n             obj_dir/ADC.v\n             obj_dir/ADC.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb2();
reg clk = 0, chg_ena = 0;
wire scl, sda;
integer i;
ADC inst(.clk(clk), .sw(),
    .sda(sda), .scl(scl),
    .main(), .start(), .ch(), .on(), .level(), .offset(), .data(), .chg_ena(chg_ena), .chg_fns());
initial
begin;
    for (i = 1; i <= 100000; i = i + 1)
    begin
        clk = ~clk;
        #1;
        if (i > 3)
            chg_ena = 1;
    end
end
endmodule
module tb2();

reg clk = 0, chg_ena = 0;
wire scl, sda;
integer i;
ADC inst(.clk(clk), .sw(),
    .sda(sda), .scl(scl),
    .main(), .start(), .ch(), .on(), .level(), .offset(), .data(), .chg_ena(chg_ena), .chg_fns());
initial
begin;
    for (i = 1; i <= 100000; i = i + 1)
    begin
        clk = ~clk;
        #1;
        if (i > 3)
            chg_ena = 1;
    end
end
endmodule