data/full_repos/permissive/423924606/caravel/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/423924606/caravel/verilog/rtl/user_proj_example.v:90: syntax error, unexpected class\nDeepSAC_sleep DS(.class(wbs_ack_o), .clk(wb_clk_i), .rst(wb_rst_i), .x1(wbs_dat_i[15:0]), .x2(wbs_adr_i[15:0]));\n                  ^~~~~\n%Error: data/full_repos/permissive/423924606/caravel/verilog/rtl/user_proj_example.v:98: syntax error, unexpected class, expecting '['\noutput class,\n       ^~~~~\n%Error: data/full_repos/permissive/423924606/caravel/verilog/rtl/user_proj_example.v:202: syntax error, unexpected IDENTIFIER\ncomplement_rejfdb CP_L1_x1 (x1, x1c);\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423924606/caravel/verilog/rtl/user_proj_example.v:545: syntax error, unexpected begin\nbegin\n^~~~~\n%Error: data/full_repos/permissive/423924606/caravel/verilog/rtl/user_proj_example.v:553: syntax error, unexpected end\nend\n^~~\n%Error: data/full_repos/permissive/423924606/caravel/verilog/rtl/user_proj_example.v:752: syntax error, unexpected class, expecting '['\nmodule convert16_to_1(sig_out, class);\n                               ^~~~~\n%Error: Exiting due to 6 error(s)\n"
module ifstatement(x,y);

input [15:0] x;
output reg [1:0] y;

always @(x)
if (x > 16'b000000000000000 &&  x< 16'b0000010000000000) y <= 2'b00 ;
else if (x == 16'b0000000000000000) y <= 2'b00 ; 
else if (x > 16'b0000010000000000 &&  x< 16'b0000100110000000) y <= 2'b01 ;
else if (x > 16'b0000100110000000 &&  x< 16'b0001010000000000) y <= 2'b10 ;
else if (x > 16'b0001010000000000) y <= 2'b11 ;

endmodule
module ifstatement(x,y);


input [15:0] x;
output reg [1:0] y;

always @(x)
if (x > 16'b000000000000000 &&  x< 16'b0000010000000000) y <= 2'b00 ;
else if (x == 16'b0000000000000000) y <= 2'b00 ; 
else if (x > 16'b0000010000000000 &&  x< 16'b0000100110000000) y <= 2'b01 ;
else if (x > 16'b0000100110000000 &&  x< 16'b0001010000000000) y <= 2'b10 ;
else if (x > 16'b0001010000000000) y <= 2'b11 ;

endmodule