data/full_repos/permissive/459277146/divider.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/459277146/divider.v:90: Unsupported: Ignoring delay on this delayed statement.\n    always #(CLK_PERIOD / 2) clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/459277146/divider.v:93: Unsupported or unknown PLI call: $monitor\n        $monitor("\\t%d:\\t%d /%d =%d (r =) (V=) (DBZ=)",\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/459277146/divider.v:100: Unsupported: Ignoring delay on this delayed statement.\n        #100    x = 4\'b0000;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/divider.v:103: Unsupported: Ignoring delay on this delayed statement.\n        #10     start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/divider.v:105: Unsupported: Ignoring delay on this delayed statement.\n        #50     x = 4\'b0010;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/divider.v:108: Unsupported: Ignoring delay on this delayed statement.\n        #10     start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/divider.v:110: Unsupported: Ignoring delay on this delayed statement.\n        #50     x = 4\'b0111;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/divider.v:113: Unsupported: Ignoring delay on this delayed statement.\n        #10     start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/divider.v:115: Unsupported: Ignoring delay on this delayed statement.\n        #50     x = 4\'b1111;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/divider.v:118: Unsupported: Ignoring delay on this delayed statement.\n        #10     start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/divider.v:120: Unsupported: Ignoring delay on this delayed statement.\n        #50     x = 4\'b0001;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/divider.v:123: Unsupported: Ignoring delay on this delayed statement.\n        #10     start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/divider.v:125: Unsupported: Ignoring delay on this delayed statement.\n        #50     x = 4\'b1000;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/divider.v:128: Unsupported: Ignoring delay on this delayed statement.\n        #10     start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/divider.v:132: Unsupported: Ignoring delay on this delayed statement.\n        #50     $finish;\n        ^\n%Error: data/full_repos/permissive/459277146/divider.v:135: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("div.vcd"); \n  ^~~~~~~~~\n%Error: data/full_repos/permissive/459277146/divider.v:136: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars; \n  ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module divider #(parameter DWIDTH=8) (
    input wire logic clk,
    input wire logic start,
    input wire logic [DWIDTH-1:0] x,
    input wire logic [DWIDTH-1:0] y,


    output     logic [(DWIDTH<<1)-1:0] dout
    );
    
    reg  busy;
    reg  valid;
    reg  dbz;
    reg [DWIDTH-1:0] q;
    reg [DWIDTH-1:0] r;
    assign dout = {q,r};
    logic [DWIDTH-1:0] y1;
    logic [DWIDTH-1:0] q1, q1_next;
    logic [DWIDTH:0] ac, ac_next;
  logic [clogb2(DWIDTH)-1:0] i;

  always @(*) begin
        if (ac >= {1'b0,y1}) begin
            ac_next = ac - y1;
            {ac_next, q1_next} = {ac_next[DWIDTH-1:0], q1, 1'b1};
        end else begin
            {ac_next, q1_next} = {ac, q1} << 1;
        end
    end

    always @(posedge clk) begin
        if (start) begin
            valid <= 0;
            i <= 0;
            if (y == 0) begin
                busy <= 0;
                dbz <= 1;
            end else begin
                busy <= 1;
                dbz <= 0;
                y1 <= y;
                {ac, q1} <= {{DWIDTH{1'b0}}, x, 1'b0};
            end
        end else if (busy) begin
            if (i == DWIDTH-1) begin
                busy <= 0;
                valid <= 1;
                q <= q1_next;
                r <= ac_next[DWIDTH:1];
            end else begin
                i <= i + 1;
                ac <= ac_next;
                q1 <= q1_next;
            end
        end
    end


function integer clogb2;
   input [31:0] value;
   integer  i;
   begin
      clogb2 = 0;
      for(i = 0; 2**i < value; i = i + 1)
    clogb2 = i + 1;
   end
endfunction
endmodule
module divider #(parameter DWIDTH=8) (
    input wire logic clk,
    input wire logic start,
    input wire logic [DWIDTH-1:0] x,
    input wire logic [DWIDTH-1:0] y,


    output     logic [(DWIDTH<<1)-1:0] dout
    );

    
    reg  busy;
    reg  valid;
    reg  dbz;
    reg [DWIDTH-1:0] q;
    reg [DWIDTH-1:0] r;
    assign dout = {q,r};
    logic [DWIDTH-1:0] y1;
    logic [DWIDTH-1:0] q1, q1_next;
    logic [DWIDTH:0] ac, ac_next;
  logic [clogb2(DWIDTH)-1:0] i;

  always @(*) begin
        if (ac >= {1'b0,y1}) begin
            ac_next = ac - y1;
            {ac_next, q1_next} = {ac_next[DWIDTH-1:0], q1, 1'b1};
        end else begin
            {ac_next, q1_next} = {ac, q1} << 1;
        end
    end

    always @(posedge clk) begin
        if (start) begin
            valid <= 0;
            i <= 0;
            if (y == 0) begin
                busy <= 0;
                dbz <= 1;
            end else begin
                busy <= 1;
                dbz <= 0;
                y1 <= y;
                {ac, q1} <= {{DWIDTH{1'b0}}, x, 1'b0};
            end
        end else if (busy) begin
            if (i == DWIDTH-1) begin
                busy <= 0;
                valid <= 1;
                q <= q1_next;
                r <= ac_next[DWIDTH:1];
            end else begin
                i <= i + 1;
                ac <= ac_next;
                q1 <= q1_next;
            end
        end
    end


function integer clogb2;
   input [31:0] value;
   integer  i;
   begin
      clogb2 = 0;
      for(i = 0; 2**i < value; i = i + 1)
    clogb2 = i + 1;
   end
endfunction
endmodule