data/full_repos/permissive/506562943/HDLBits/Verilog Language/More Verilog Features/popcount255.v
1: b'%Error: Cannot find file containing module: Language/More\n        ... Looked in:\n             data/full_repos/permissive/506562943/HDLBits/Verilog/Language/More\n             data/full_repos/permissive/506562943/HDLBits/Verilog/Language/More.v\n             data/full_repos/permissive/506562943/HDLBits/Verilog/Language/More.sv\n             Language/More\n             Language/More.v\n             Language/More.sv\n             obj_dir/Language/More\n             obj_dir/Language/More.v\n             obj_dir/Language/More.sv\n%Error: Cannot find file containing module: Verilog\n%Error: Cannot find file containing module: Features,data/full_repos/permissive/506562943\n%Error: Cannot find file containing module: data/full_repos/permissive/506562943/HDLBits/Verilog\n%Error: Cannot find file containing module: Features/popcount255.v\n%Error: Exiting due to 5 error(s)\n'
module top_module( 
    input [254:0] in,
    output [7:0] out );

    integer i;
    reg[7:0] cnt;
    
    assign out = cnt;
    
    always @(*) begin
        cnt = 7'd0;
        for(i = 0; i < 255; i++)
            if (in[i])
                cnt += 1'b1;
    end
    
endmodule
module top_module( 
    input [254:0] in,
    output [7:0] out );


    integer i;
    reg[7:0] cnt;
    
    assign out = cnt;
    
    always @(*) begin
        cnt = 7'd0;
        for(i = 0; i < 255; i++)
            if (in[i])
                cnt += 1'b1;
    end
    
endmodule