data/full_repos/permissive/429782749/rtl/mips_cpu/sign_extension.v
1: b"%Error: data/full_repos/permissive/429782749/rtl/mips_cpu/sign_extension.v:11: Can't find definition of variable: 'OPCODE_ANDI'\n        if(opcode == OPCODE_ANDI || opcode == OPCODE_ORI || opcode == OPCODE_XORI) begin\n                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/429782749/rtl/mips_cpu/sign_extension.v:11: Can't find definition of variable: 'OPCODE_ORI'\n                                                                             : ... Suggested alternative: 'OPCODE_ANDI'\n        if(opcode == OPCODE_ANDI || opcode == OPCODE_ORI || opcode == OPCODE_XORI) begin\n                                              ^~~~~~~~~~\n%Error: data/full_repos/permissive/429782749/rtl/mips_cpu/sign_extension.v:11: Can't find definition of variable: 'OPCODE_XORI'\n                                                                             : ... Suggested alternative: 'OPCODE_ORI'\n        if(opcode == OPCODE_ANDI || opcode == OPCODE_ORI || opcode == OPCODE_XORI) begin\n                                                                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/429782749/rtl/mips_cpu/sign_extension.v:14: Can't find definition of variable: 'OPCODE_LUI'\n                                                                             : ... Suggested alternative: 'OPCODE_ORI'\n        else if(opcode == OPCODE_LUI) begin\n                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/429782749/rtl/mips_cpu/sign_extension.v:17: Can't find definition of variable: 'OPCODE_BNE'\n                                                                             : ... Suggested alternative: 'OPCODE_ANDI'\n        else if(opcode == OPCODE_BNE || opcode == OPCODE_BEQ || opcode == OPCODE_REGIMM || opcode == OPCODE_BGTZ || opcode == OPCODE_BLEZ) begin\n                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/429782749/rtl/mips_cpu/sign_extension.v:17: Can't find definition of variable: 'OPCODE_BEQ'\n                                                                             : ... Suggested alternative: 'OPCODE_BNE'\n        else if(opcode == OPCODE_BNE || opcode == OPCODE_BEQ || opcode == OPCODE_REGIMM || opcode == OPCODE_BGTZ || opcode == OPCODE_BLEZ) begin\n                                                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/429782749/rtl/mips_cpu/sign_extension.v:17: Can't find definition of variable: 'OPCODE_REGIMM'\n                                                                             : ... Suggested alternative: 'OPCODE_ANDI'\n        else if(opcode == OPCODE_BNE || opcode == OPCODE_BEQ || opcode == OPCODE_REGIMM || opcode == OPCODE_BGTZ || opcode == OPCODE_BLEZ) begin\n                                                                          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429782749/rtl/mips_cpu/sign_extension.v:17: Can't find definition of variable: 'OPCODE_BGTZ'\n                                                                             : ... Suggested alternative: 'OPCODE_BEQ'\n        else if(opcode == OPCODE_BNE || opcode == OPCODE_BEQ || opcode == OPCODE_REGIMM || opcode == OPCODE_BGTZ || opcode == OPCODE_BLEZ) begin\n                                                                                                     ^~~~~~~~~~~\n%Error: data/full_repos/permissive/429782749/rtl/mips_cpu/sign_extension.v:17: Can't find definition of variable: 'OPCODE_BLEZ'\n                                                                             : ... Suggested alternative: 'OPCODE_BEQ'\n        else if(opcode == OPCODE_BNE || opcode == OPCODE_BEQ || opcode == OPCODE_REGIMM || opcode == OPCODE_BGTZ || opcode == OPCODE_BLEZ) begin\n                                                                                                                              ^~~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n"
module sign_extension(
    input logic[15:0] itype_immediate,
    input logic[5:0] opcode,
    output logic[31:0] signed_itype_immediate
);
    logic msb;
    assign msb = itype_immediate[15];

    always_comb begin
        
        if(opcode == OPCODE_ANDI || opcode == OPCODE_ORI || opcode == OPCODE_XORI) begin
            signed_itype_immediate = {16'b0, itype_immediate}; 
        end
        else if(opcode == OPCODE_LUI) begin
            signed_itype_immediate = {itype_immediate, 16'b0};
        end
        else if(opcode == OPCODE_BNE || opcode == OPCODE_BEQ || opcode == OPCODE_REGIMM || opcode == OPCODE_BGTZ || opcode == OPCODE_BLEZ) begin
            signed_itype_immediate = msb ? {14'h3FFF, itype_immediate, 2'b0} : {14'b0, itype_immediate, 2'b0};
        end
        else begin
            signed_itype_immediate = msb ? {16'hFFFF, itype_immediate} : {16'b0, itype_immediate};
        end
        
    end

endmodule
module sign_extension(
    input logic[15:0] itype_immediate,
    input logic[5:0] opcode,
    output logic[31:0] signed_itype_immediate
);

    logic msb;
    assign msb = itype_immediate[15];

    always_comb begin
        
        if(opcode == OPCODE_ANDI || opcode == OPCODE_ORI || opcode == OPCODE_XORI) begin
            signed_itype_immediate = {16'b0, itype_immediate}; 
        end
        else if(opcode == OPCODE_LUI) begin
            signed_itype_immediate = {itype_immediate, 16'b0};
        end
        else if(opcode == OPCODE_BNE || opcode == OPCODE_BEQ || opcode == OPCODE_REGIMM || opcode == OPCODE_BGTZ || opcode == OPCODE_BLEZ) begin
            signed_itype_immediate = msb ? {14'h3FFF, itype_immediate, 2'b0} : {14'b0, itype_immediate, 2'b0};
        end
        else begin
            signed_itype_immediate = msb ? {16'hFFFF, itype_immediate} : {16'b0, itype_immediate};
        end
        
    end

endmodule