data/full_repos/permissive/441359809/src/yosys/tests/svtypes/typedef_scopes.sv
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/tests/svtypes/typedef_scopes.sv:38: Multiple top level modules\n                                                                                                    : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                    : ... Top module \'top\'\nmodule top;\n       ^~~\n                                                                                                    : ... Top module \'other\'\nmodule other;\n       ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/svtypes/typedef_scopes.sv:7: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'ha5\' generates 8 bits.\n                                                                                                : ... In instance top\n outer_uint4_t u4_i = 8\'hA5;\n                      ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/svtypes/typedef_scopes.sv:14: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h5a\' generates 8 bits.\n                                                                                                 : ... In instance top\n inner_type inner_i1 = 8\'h5A;\n                       ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/svtypes/typedef_scopes.sv:29: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h42\' generates 8 bits.\n                                                                                                 : ... In instance top\n inner_type inner_i2 = 8\'h42;\n                       ^~~~~\n%Error: Exiting due to 4 warning(s)\n'
module other;
	between_t a = 8'h42;
	always @(*) assert(a == 8'h42);
endmodule
module other;

	between_t a = 8'h42;
	always @(*) assert(a == 8'h42);
endmodule