data/full_repos/permissive/441259215/caravel_binary_mult/bin_mult_tb.v
1: b'%Error: data/full_repos/permissive/441259215/caravel_binary_mult/bin_mult_tb.v:20: Cannot find include file: uprj_netlists.v\n`include "uprj_netlists.v" // this file gets created automatically by multi_project_tools from the source section of info.yaml \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/441259215/caravel_binary_mult,data/full_repos/permissive/441259215/uprj_netlists.v\n             data/full_repos/permissive/441259215/caravel_binary_mult,data/full_repos/permissive/441259215/uprj_netlists.v.v\n             data/full_repos/permissive/441259215/caravel_binary_mult,data/full_repos/permissive/441259215/uprj_netlists.v.sv\n             uprj_netlists.v\n             uprj_netlists.v.v\n             uprj_netlists.v.sv\n             obj_dir/uprj_netlists.v\n             obj_dir/uprj_netlists.v.v\n             obj_dir/uprj_netlists.v.sv\n%Error: data/full_repos/permissive/441259215/caravel_binary_mult/bin_mult_tb.v:21: Cannot find include file: caravel_netlists.v\n`include "caravel_netlists.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/441259215/caravel_binary_mult/bin_mult_tb.v:22: Cannot find include file: spiflash.v\n`include "spiflash.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/441259215/caravel_binary_mult/bin_mult_tb.v:26: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile ("bin_mult.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/441259215/caravel_binary_mult/bin_mult_tb.v:27: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars (0, bin_mult_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/441259215/caravel_binary_mult/bin_mult_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 5 error(s), 1 warning(s)\n'
module bin_mult_tb;
    initial begin
        $dumpfile ("bin_mult.vcd");
        $dumpvars (0, bin_mult_tb);
        #1;
    end

    reg clk;
    reg RSTB;
    reg power1, power2;
    reg power3, power4;

    wire gpio;
    wire [37:0] mprj_io;


    wire [6:0] be_out = mprj_io[14:8];
    wire dbg_caravel_wb_stb = mprj_io[20];
    wire dbg_active         = mprj_io[21];



    wire flash_csb;
    wire flash_clk;
    wire flash_io0;
    wire flash_io1;

    wire VDD3V3 = power1;
    wire VDD1V8 = power2;
    wire USER_VDD3V3 = power3;
    wire USER_VDD1V8 = power4;
    wire VSS = 1'b0;

    caravel uut (
        .vddio    (VDD3V3),
        .vssio    (VSS),
        .vdda     (VDD3V3),
        .vssa     (VSS),
        .vccd     (VDD1V8),
        .vssd     (VSS),
        .vdda1    (USER_VDD3V3),
        .vdda2    (USER_VDD3V3),
        .vssa1    (VSS),
        .vssa2    (VSS),
        .vccd1    (USER_VDD1V8),
        .vccd2    (USER_VDD1V8),
        .vssd1    (VSS),
        .vssd2    (VSS),
        .clock    (clk),
        .gpio     (gpio),
        .mprj_io  (mprj_io),
        .flash_csb(flash_csb),
        .flash_clk(flash_clk),
        .flash_io0(flash_io0),
        .flash_io1(flash_io1),
        .resetb   (RSTB)
    );

    spiflash #(
        .FILENAME("bin_mult.hex")
    ) spiflash (
        .csb(flash_csb),
        .clk(flash_clk),
        .io0(flash_io0),
        .io1(flash_io1),
        .io2(),
        .io3()
    );

endmodule
module bin_mult_tb;

    initial begin
        $dumpfile ("bin_mult.vcd");
        $dumpvars (0, bin_mult_tb);
        #1;
    end

    reg clk;
    reg RSTB;
    reg power1, power2;
    reg power3, power4;

    wire gpio;
    wire [37:0] mprj_io;


    wire [6:0] be_out = mprj_io[14:8];
    wire dbg_caravel_wb_stb = mprj_io[20];
    wire dbg_active         = mprj_io[21];



    wire flash_csb;
    wire flash_clk;
    wire flash_io0;
    wire flash_io1;

    wire VDD3V3 = power1;
    wire VDD1V8 = power2;
    wire USER_VDD3V3 = power3;
    wire USER_VDD1V8 = power4;
    wire VSS = 1'b0;

    caravel uut (
        .vddio    (VDD3V3),
        .vssio    (VSS),
        .vdda     (VDD3V3),
        .vssa     (VSS),
        .vccd     (VDD1V8),
        .vssd     (VSS),
        .vdda1    (USER_VDD3V3),
        .vdda2    (USER_VDD3V3),
        .vssa1    (VSS),
        .vssa2    (VSS),
        .vccd1    (USER_VDD1V8),
        .vccd2    (USER_VDD1V8),
        .vssd1    (VSS),
        .vssd2    (VSS),
        .clock    (clk),
        .gpio     (gpio),
        .mprj_io  (mprj_io),
        .flash_csb(flash_csb),
        .flash_clk(flash_clk),
        .flash_io0(flash_io0),
        .flash_io1(flash_io1),
        .resetb   (RSTB)
    );

    spiflash #(
        .FILENAME("bin_mult.hex")
    ) spiflash (
        .csb(flash_csb),
        .clk(flash_clk),
        .io0(flash_io0),
        .io1(flash_io1),
        .io2(),
        .io3()
    );

endmodule