data/full_repos/permissive/504248338/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv
1: b"%Error: data/full_repos/permissive/504248338/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv:132: Cannot find file containing module: 'clk_skew_adjust'\nclk_skew_adjust u_skew_uart\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/504248338/verilog/rtl/uart_i2c_usb_spi/src,data/full_repos/permissive/504248338/clk_skew_adjust\n             data/full_repos/permissive/504248338/verilog/rtl/uart_i2c_usb_spi/src,data/full_repos/permissive/504248338/clk_skew_adjust.v\n             data/full_repos/permissive/504248338/verilog/rtl/uart_i2c_usb_spi/src,data/full_repos/permissive/504248338/clk_skew_adjust.sv\n             clk_skew_adjust\n             clk_skew_adjust.v\n             clk_skew_adjust.sv\n             obj_dir/clk_skew_adjust\n             obj_dir/clk_skew_adjust.v\n             obj_dir/clk_skew_adjust.sv\n%Error: data/full_repos/permissive/504248338/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv:181: Cannot find file containing module: 'uart_core'\nuart_core  u_uart0_core (  \n^~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv:202: Cannot find file containing module: 'uart_core'\nuart_core  u_uart1_core (  \n^~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv:223: Cannot find file containing module: 'i2cm_top'\ni2cm_top  u_i2cm (\n^~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv:251: Cannot find file containing module: 'usb1_host'\nusb1_host u_usb_host (\n^~~~~~~~~\n%Error: data/full_repos/permissive/504248338/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv:280: Cannot find file containing module: 'sspim_top'\nsspim_top u_sspim (\n^~~~~~~~~\n%Error: Exiting due to 6 error(s)\n"
module uart_i2c_usb_spi_top 

     (  
`ifdef USE_POWER_PINS
   input logic         vccd1,
   input logic         vssd1,
`endif

   input logic [3:0]   cfg_cska_uart,
   input logic	       wbd_clk_int,
   output logic	       wbd_clk_uart,

   input logic  [1:0]  uart_rstn  ,
   input logic         i2c_rstn    ,
   input logic         usb_rstn    ,
   input logic         spi_rstn    ,
   input logic         app_clk     ,
   input logic         usb_clk     ,


   input logic         reg_cs,
   input logic         reg_wr,
   input logic [8:0]   reg_addr,
   input logic [31:0]  reg_wdata,
   input logic [3:0]   reg_be,


   output logic [31:0] reg_rdata,
   output logic        reg_ack,



   input logic         scl_pad_i              ,
   output logic        scl_pad_o              ,
   output logic        scl_pad_oen_o          ,
   
   input logic         sda_pad_i              ,
   output logic        sda_pad_o              ,
   output logic        sda_padoen_o           ,

   output logic        i2cm_intr_o            ,


   input  logic  [1:0] uart_rxd               , 
   output logic  [1:0] uart_txd               ,


   input  logic        usb_in_dp              ,
   input  logic        usb_in_dn              ,

   output logic        usb_out_dp             ,
   output logic        usb_out_dn             ,
   output logic        usb_out_tx_oen         ,
   
   output logic        usb_intr_o            ,


   output logic        sspim_sck,
   output logic        sspim_so,
   input  logic        sspim_si,
   output logic [3:0]  sspim_ssn

     );


clk_skew_adjust u_skew_uart
       (
`ifdef USE_POWER_PINS
               .vccd1      (vccd1                      ),
               .vssd1      (vssd1                      ),
`endif
	       .clk_in     (wbd_clk_int                 ), 
	       .sel        (cfg_cska_uart               ), 
	       .clk_out    (wbd_clk_uart                ) 
       );

`define SEL_UART0 3'b000
`define SEL_I2C   3'b001
`define SEL_USB   3'b010
`define SEL_SPI   3'b011
`define SEL_UART1 3'b100






logic [7:0]   reg_uart0_rdata;
logic [7:0]   reg_uart1_rdata;
logic [7:0]   reg_i2c_rdata;
logic [31:0]  reg_usb_rdata;
logic [31:0]  reg_spim_rdata;
logic         reg_uart0_ack;
logic         reg_uart1_ack;
logic         reg_i2c_ack;
logic         reg_usb_ack;
logic         reg_spim_ack;


assign reg_rdata = (reg_addr[8:6] == `SEL_UART0) ? {24'h0,reg_uart0_rdata} : 
	           (reg_addr[8:6] == `SEL_UART1) ? {24'h0,reg_uart1_rdata} :
	           (reg_addr[8:6] == `SEL_I2C) ? {24'h0,reg_i2c_rdata} :
	           (reg_addr[8:6] == `SEL_USB) ? reg_usb_rdata : reg_spim_rdata;
assign reg_ack   = (reg_addr[8:6] == `SEL_UART0) ? reg_uart0_ack   : 
	           (reg_addr[8:6] == `SEL_UART1) ? reg_uart1_ack   : 
	           (reg_addr[8:6] == `SEL_I2C)   ? reg_i2c_ack     : 
	           (reg_addr[8:6] == `SEL_USB)   ? reg_usb_ack     : reg_spim_ack;

wire reg_uart0_cs  = (reg_addr[8:6] == `SEL_UART0) ? reg_cs : 1'b0;
wire reg_uart1_cs  = (reg_addr[8:6] == `SEL_UART1) ? reg_cs : 1'b0;
wire reg_i2cm_cs   = (reg_addr[8:6] == `SEL_I2C)   ? reg_cs : 1'b0;
wire reg_usb_cs    = (reg_addr[8:6] == `SEL_USB)   ? reg_cs : 1'b0;
wire reg_spim_cs   = (reg_addr[8:6] == `SEL_SPI)   ? reg_cs : 1'b0;

uart_core  u_uart0_core (  

        .arst_n      (uart_rstn[0]     ),
        .app_clk     (app_clk          ),


        .reg_cs      (reg_uart0_cs     ),
        .reg_wr      (reg_wr           ),
        .reg_addr    (reg_addr[5:2]    ),
        .reg_wdata   (reg_wdata[7:0]   ),
        .reg_be      (reg_be[0]        ),


        .reg_rdata   (reg_uart0_rdata[7:0]),
        .reg_ack     (reg_uart0_ack    ),


        .rxd          (uart_rxd[0]     ),
        .txd          (uart_txd[0]     )
     );

uart_core  u_uart1_core (  

        .arst_n      (uart_rstn[1]     ),
        .app_clk     (app_clk          ),


        .reg_cs      (reg_uart1_cs     ),
        .reg_wr      (reg_wr           ),
        .reg_addr    (reg_addr[5:2]    ),
        .reg_wdata   (reg_wdata[7:0]   ),
        .reg_be      (reg_be[0]        ),


        .reg_rdata   (reg_uart1_rdata[7:0]),
        .reg_ack     (reg_uart1_ack    ),


        .rxd          (uart_rxd[1]     ),
        .txd          (uart_txd[1]     )
     );

i2cm_top  u_i2cm (

	.wb_clk_i      (app_clk        ),
	.sresetn       (1'b1           ),
	.aresetn       (i2c_rstn       ),
	.wb_adr_i      (reg_addr[4:2]  ),
	.wb_dat_i      (reg_wdata[7:0] ),
	.wb_dat_o      (reg_i2c_rdata  ),
	.wb_we_i       (reg_wr         ),
	.wb_stb_i      (reg_i2cm_cs    ),
	.wb_cyc_i      (reg_i2cm_cs    ),
	.wb_ack_o      (reg_i2c_ack    ),
	.wb_inta_o     (i2cm_intr_o    ),



	.scl_pad_i     (scl_pad_i      ),
	.scl_pad_o     (scl_pad_o      ),
	.scl_padoen_o  (scl_pad_oen_o  ),


	.sda_pad_i     (sda_pad_i      ),
	.sda_pad_o     (sda_pad_o      ),
	.sda_padoen_o  (sda_padoen_o   )

         );


usb1_host u_usb_host (
    .usb_clk_i      (usb_clk       ),
    .usb_rstn_i     (usb_rstn      ),


    .in_dp          (usb_in_dp     ),
    .in_dn          (usb_in_dn     ),

    .out_dp         (usb_out_dp    ),
    .out_dn         (usb_out_dn    ),
    .out_tx_oen     (usb_out_tx_oen),


    .wbm_rst_n      (usb_rstn      ),
    .wbm_clk_i      (app_clk       ),
    .wbm_stb_i      (reg_usb_cs    ),
    .wbm_adr_i      (reg_addr[5:0]),
    .wbm_we_i       (reg_wr        ),
    .wbm_dat_i      (reg_wdata     ),
    .wbm_sel_i      (reg_be        ),
    .wbm_dat_o      (reg_usb_rdata ),
    .wbm_ack_o      (reg_usb_ack   ),
    .wbm_err_o      (              ),


    .usb_intr_o    ( usb_intr_o    )

    );

sspim_top u_sspim (
     .clk          (app_clk         ),
     .reset_n      (spi_rstn        ),          
           
           



     .reg_cs      (reg_spim_cs      ),
     .reg_wr      (reg_wr           ),
     .reg_addr    ({2'b0,reg_addr[5:0]} ),
     .reg_wdata   (reg_wdata        ),
     .reg_be      (reg_be           ),


     .reg_rdata   (reg_spim_rdata   ),
     .reg_ack     (reg_spim_ack     ),
           



           
      .sck           (sspim_sck),
      .so            (sspim_so),
      .si            (sspim_si),
      .ssn           (sspim_ssn)

           );

endmodule
module uart_i2c_usb_spi_top 

     (  
`ifdef USE_POWER_PINS
   input logic         vccd1,
   input logic         vssd1,
`endif

   input logic [3:0]   cfg_cska_uart,
   input logic	       wbd_clk_int,
   output logic	       wbd_clk_uart,

   input logic  [1:0]  uart_rstn  ,
   input logic         i2c_rstn    ,
   input logic         usb_rstn    ,
   input logic         spi_rstn    ,
   input logic         app_clk     ,
   input logic         usb_clk     ,


   input logic         reg_cs,
   input logic         reg_wr,
   input logic [8:0]   reg_addr,
   input logic [31:0]  reg_wdata,
   input logic [3:0]   reg_be,


   output logic [31:0] reg_rdata,
   output logic        reg_ack,



   input logic         scl_pad_i              ,
   output logic        scl_pad_o              ,
   output logic        scl_pad_oen_o          ,
   
   input logic         sda_pad_i              ,
   output logic        sda_pad_o              ,
   output logic        sda_padoen_o           ,

   output logic        i2cm_intr_o            ,


   input  logic  [1:0] uart_rxd               , 
   output logic  [1:0] uart_txd               ,


   input  logic        usb_in_dp              ,
   input  logic        usb_in_dn              ,

   output logic        usb_out_dp             ,
   output logic        usb_out_dn             ,
   output logic        usb_out_tx_oen         ,
   
   output logic        usb_intr_o            ,


   output logic        sspim_sck,
   output logic        sspim_so,
   input  logic        sspim_si,
   output logic [3:0]  sspim_ssn

     );



clk_skew_adjust u_skew_uart
       (
`ifdef USE_POWER_PINS
               .vccd1      (vccd1                      ),
               .vssd1      (vssd1                      ),
`endif
	       .clk_in     (wbd_clk_int                 ), 
	       .sel        (cfg_cska_uart               ), 
	       .clk_out    (wbd_clk_uart                ) 
       );

`define SEL_UART0 3'b000
`define SEL_I2C   3'b001
`define SEL_USB   3'b010
`define SEL_SPI   3'b011
`define SEL_UART1 3'b100






logic [7:0]   reg_uart0_rdata;
logic [7:0]   reg_uart1_rdata;
logic [7:0]   reg_i2c_rdata;
logic [31:0]  reg_usb_rdata;
logic [31:0]  reg_spim_rdata;
logic         reg_uart0_ack;
logic         reg_uart1_ack;
logic         reg_i2c_ack;
logic         reg_usb_ack;
logic         reg_spim_ack;


assign reg_rdata = (reg_addr[8:6] == `SEL_UART0) ? {24'h0,reg_uart0_rdata} : 
	           (reg_addr[8:6] == `SEL_UART1) ? {24'h0,reg_uart1_rdata} :
	           (reg_addr[8:6] == `SEL_I2C) ? {24'h0,reg_i2c_rdata} :
	           (reg_addr[8:6] == `SEL_USB) ? reg_usb_rdata : reg_spim_rdata;
assign reg_ack   = (reg_addr[8:6] == `SEL_UART0) ? reg_uart0_ack   : 
	           (reg_addr[8:6] == `SEL_UART1) ? reg_uart1_ack   : 
	           (reg_addr[8:6] == `SEL_I2C)   ? reg_i2c_ack     : 
	           (reg_addr[8:6] == `SEL_USB)   ? reg_usb_ack     : reg_spim_ack;

wire reg_uart0_cs  = (reg_addr[8:6] == `SEL_UART0) ? reg_cs : 1'b0;
wire reg_uart1_cs  = (reg_addr[8:6] == `SEL_UART1) ? reg_cs : 1'b0;
wire reg_i2cm_cs   = (reg_addr[8:6] == `SEL_I2C)   ? reg_cs : 1'b0;
wire reg_usb_cs    = (reg_addr[8:6] == `SEL_USB)   ? reg_cs : 1'b0;
wire reg_spim_cs   = (reg_addr[8:6] == `SEL_SPI)   ? reg_cs : 1'b0;

uart_core  u_uart0_core (  

        .arst_n      (uart_rstn[0]     ),
        .app_clk     (app_clk          ),


        .reg_cs      (reg_uart0_cs     ),
        .reg_wr      (reg_wr           ),
        .reg_addr    (reg_addr[5:2]    ),
        .reg_wdata   (reg_wdata[7:0]   ),
        .reg_be      (reg_be[0]        ),


        .reg_rdata   (reg_uart0_rdata[7:0]),
        .reg_ack     (reg_uart0_ack    ),


        .rxd          (uart_rxd[0]     ),
        .txd          (uart_txd[0]     )
     );

uart_core  u_uart1_core (  

        .arst_n      (uart_rstn[1]     ),
        .app_clk     (app_clk          ),


        .reg_cs      (reg_uart1_cs     ),
        .reg_wr      (reg_wr           ),
        .reg_addr    (reg_addr[5:2]    ),
        .reg_wdata   (reg_wdata[7:0]   ),
        .reg_be      (reg_be[0]        ),


        .reg_rdata   (reg_uart1_rdata[7:0]),
        .reg_ack     (reg_uart1_ack    ),


        .rxd          (uart_rxd[1]     ),
        .txd          (uart_txd[1]     )
     );

i2cm_top  u_i2cm (

	.wb_clk_i      (app_clk        ),
	.sresetn       (1'b1           ),
	.aresetn       (i2c_rstn       ),
	.wb_adr_i      (reg_addr[4:2]  ),
	.wb_dat_i      (reg_wdata[7:0] ),
	.wb_dat_o      (reg_i2c_rdata  ),
	.wb_we_i       (reg_wr         ),
	.wb_stb_i      (reg_i2cm_cs    ),
	.wb_cyc_i      (reg_i2cm_cs    ),
	.wb_ack_o      (reg_i2c_ack    ),
	.wb_inta_o     (i2cm_intr_o    ),



	.scl_pad_i     (scl_pad_i      ),
	.scl_pad_o     (scl_pad_o      ),
	.scl_padoen_o  (scl_pad_oen_o  ),


	.sda_pad_i     (sda_pad_i      ),
	.sda_pad_o     (sda_pad_o      ),
	.sda_padoen_o  (sda_padoen_o   )

         );


usb1_host u_usb_host (
    .usb_clk_i      (usb_clk       ),
    .usb_rstn_i     (usb_rstn      ),


    .in_dp          (usb_in_dp     ),
    .in_dn          (usb_in_dn     ),

    .out_dp         (usb_out_dp    ),
    .out_dn         (usb_out_dn    ),
    .out_tx_oen     (usb_out_tx_oen),


    .wbm_rst_n      (usb_rstn      ),
    .wbm_clk_i      (app_clk       ),
    .wbm_stb_i      (reg_usb_cs    ),
    .wbm_adr_i      (reg_addr[5:0]),
    .wbm_we_i       (reg_wr        ),
    .wbm_dat_i      (reg_wdata     ),
    .wbm_sel_i      (reg_be        ),
    .wbm_dat_o      (reg_usb_rdata ),
    .wbm_ack_o      (reg_usb_ack   ),
    .wbm_err_o      (              ),


    .usb_intr_o    ( usb_intr_o    )

    );

sspim_top u_sspim (
     .clk          (app_clk         ),
     .reset_n      (spi_rstn        ),          
           
           



     .reg_cs      (reg_spim_cs      ),
     .reg_wr      (reg_wr           ),
     .reg_addr    ({2'b0,reg_addr[5:0]} ),
     .reg_wdata   (reg_wdata        ),
     .reg_be      (reg_be           ),


     .reg_rdata   (reg_spim_rdata   ),
     .reg_ack     (reg_spim_ack     ),
           



           
      .sck           (sspim_sck),
      .so            (sspim_so),
      .si            (sspim_si),
      .ssn           (sspim_ssn)

           );

endmodule