data/full_repos/permissive/418284997/src/blocks/bram_init_rom.v
data/verilator_xmls/c05980fc-4f62-443f-bc3a-4b1a9724d04d.xml
module bram_init_rom
  #(
    parameter memSize_p = 8,
    parameter dataWidth_p = 16,
    parameter initFile_p = ""
  )
  (
    input wire clk_i,
    input wire [(memSize_p - 1):0]  addr_i,

    output reg [(dataWidth_p - 1):0] data_o
  );

  reg [(dataWidth_p - 1):0] memory [2**memSize_p-1:0];

  initial if (initFile_p) $readmemh(initFile_p, memory);

  always @(posedge clk_i) begin
    data_o <= memory[addr_i];
  end

endmodule
module bram_init_rom
  #(
    parameter memSize_p = 8,
    parameter dataWidth_p = 16,
    parameter initFile_p = ""
  )
  (
    input wire clk_i,
    input wire [(memSize_p - 1):0]  addr_i,

    output reg [(dataWidth_p - 1):0] data_o
  );


  reg [(dataWidth_p - 1):0] memory [2**memSize_p-1:0];

  initial if (initFile_p) $readmemh(initFile_p, memory);

  always @(posedge clk_i) begin
    data_o <= memory[addr_i];
  end

endmodule