data/full_repos/permissive/418897317/verilog/rtl/lfsr.v
1: b'%Warning-WIDTH: data/full_repos/permissive/418897317/verilog/rtl/lfsr.v:304: Operator COND expects 72 bits on the Conditional False, but Conditional False\'s VARREF \'STYLE\' generates 32 bits.\n                                                                           : ... In instance lfsr\nparameter STYLE_INT = (STYLE == "AUTO") ? "REDUCTION" : STYLE;\n                                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module lfsr #
(

    parameter LFSR_WIDTH = 32,

    parameter LFSR_POLY = 31'h10000001,

    parameter LFSR_CONFIG = "FIBONACCI",

    parameter LFSR_FEED_FORWARD = 0,

    parameter REVERSE = 0,

    parameter DATA_WIDTH = 8,

    parameter STYLE = "AUTO"
)
(
    input  wire [DATA_WIDTH-1:0] data_in,
    input  wire [LFSR_WIDTH-1:0] state_in,
    output wire [DATA_WIDTH-1:0] data_out,
    output wire [LFSR_WIDTH-1:0] state_out
);



wire [LFSR_WIDTH-1:0] lfsr_mask_state[LFSR_WIDTH-1:0];
wire [DATA_WIDTH-1:0] lfsr_mask_data[LFSR_WIDTH-1:0];
wire [LFSR_WIDTH-1:0] output_mask_state[DATA_WIDTH-1:0];
wire [DATA_WIDTH-1:0] output_mask_data[DATA_WIDTH-1:0];

wire [LFSR_WIDTH-1:0] state_val;
wire [DATA_WIDTH-1:0] data_val;

integer i, j;

assign lfsr_mask_state[31] = 32'h00000082;
assign lfsr_mask_state[30] = 32'h000000c3;
assign lfsr_mask_state[29] = 32'h000000e3;
assign lfsr_mask_state[28] = 32'h00000071;
assign lfsr_mask_state[27] = 32'h000000ba;
assign lfsr_mask_state[26] = 32'h000000df;
assign lfsr_mask_state[25] = 32'h0000006f;
assign lfsr_mask_state[24] = 32'h000000b5;
assign lfsr_mask_state[23] = 32'h800000d8;
assign lfsr_mask_state[22] = 32'h4000006c;
assign lfsr_mask_state[21] = 32'h200000b4;
assign lfsr_mask_state[20] = 32'h100000d8;
assign lfsr_mask_state[19] = 32'h080000ee;
assign lfsr_mask_state[18] = 32'h04000077;
assign lfsr_mask_state[17] = 32'h0200003b;
assign lfsr_mask_state[16] = 32'h0100001d;
assign lfsr_mask_state[15] = 32'h0080008c;
assign lfsr_mask_state[14] = 32'h00400046;
assign lfsr_mask_state[13] = 32'h00200023;
assign lfsr_mask_state[12] = 32'h00100011;
assign lfsr_mask_state[11] = 32'h00080008;
assign lfsr_mask_state[10] = 32'h00040004;
assign lfsr_mask_state[9] = 32'h00020080;
assign lfsr_mask_state[8] = 32'h000100c2;
assign lfsr_mask_state[7] = 32'h00008061;
assign lfsr_mask_state[6] = 32'h00004030;
assign lfsr_mask_state[5] = 32'h0000209a;
assign lfsr_mask_state[4] = 32'h0000104d;
assign lfsr_mask_state[3] = 32'h00000826;
assign lfsr_mask_state[2] = 32'h00000413;
assign lfsr_mask_state[1] = 32'h00000209;
assign lfsr_mask_state[0] = 32'h00000104;

assign lfsr_mask_data[31] = 8'h82;
assign lfsr_mask_data[30] = 8'hc3;
assign lfsr_mask_data[29] = 8'he3;
assign lfsr_mask_data[28] = 8'h71;
assign lfsr_mask_data[27] = 8'hba;
assign lfsr_mask_data[26] = 8'hdf;
assign lfsr_mask_data[25] = 8'h6f;
assign lfsr_mask_data[24] = 8'hb5;
assign lfsr_mask_data[23] = 8'hd8;
assign lfsr_mask_data[22] = 8'h6c;
assign lfsr_mask_data[21] = 8'hb4;
assign lfsr_mask_data[20] = 8'hd8;
assign lfsr_mask_data[19] = 8'hee;
assign lfsr_mask_data[18] = 8'h77;
assign lfsr_mask_data[17] = 8'h3b;
assign lfsr_mask_data[16] = 8'h1d;
assign lfsr_mask_data[15] = 8'h8c;
assign lfsr_mask_data[14] = 8'h46;
assign lfsr_mask_data[13] = 8'h23;
assign lfsr_mask_data[12] = 8'h11;
assign lfsr_mask_data[11] = 8'h08;
assign lfsr_mask_data[10] = 8'h04;
assign lfsr_mask_data[9] = 8'h80;
assign lfsr_mask_data[8] = 8'hc2;
assign lfsr_mask_data[7] = 8'h61;
assign lfsr_mask_data[6] = 8'h30;
assign lfsr_mask_data[5] = 8'h9a;
assign lfsr_mask_data[4] = 8'h4d;
assign lfsr_mask_data[3] = 8'h26;
assign lfsr_mask_data[2] = 8'h13;
assign lfsr_mask_data[1] = 8'h09;
assign lfsr_mask_data[0] = 8'h04;

assign output_mask_state[7] = 32'h00000082;
assign output_mask_state[6] = 32'h00000041;
assign output_mask_state[5] = 32'h00000020;
assign output_mask_state[4] = 32'h00000010;
assign output_mask_state[3] = 32'h00000008;
assign output_mask_state[2] = 32'h00000004;
assign output_mask_state[1] = 32'h00000002;
assign output_mask_state[0] = 32'h00000001;

assign output_mask_data[7] = 8'h82;
assign output_mask_data[6] = 8'h41;
assign output_mask_data[5] = 8'h20;
assign output_mask_data[4] = 8'h10;
assign output_mask_data[3] = 8'h08;
assign output_mask_data[2] = 8'h04;
assign output_mask_data[1] = 8'h02;
assign output_mask_data[0] = 8'h01;

assign state_val = 32'h00000082;
assign data_val = 8'h82;


`define SIMULATION


`ifdef SIMULATION

parameter STYLE_INT = (STYLE == "AUTO") ? "REDUCTION" : STYLE;
`else

parameter STYLE_INT = (STYLE == "AUTO") ? "LOOP" : STYLE;
`endif

genvar n;

generate

if (STYLE_INT == "REDUCTION") begin







    for (n = 0; n < LFSR_WIDTH; n = n + 1) begin : loop1
        assign state_out[n] = ^{(state_in & lfsr_mask_state[n]), (data_in & lfsr_mask_data[n])};
    end
    for (n = 0; n < DATA_WIDTH; n = n + 1) begin : loop2
        assign data_out[n] = ^{(state_in & output_mask_state[n]), (data_in & output_mask_data[n])};
    end

end else if (STYLE_INT == "LOOP") begin







    reg [LFSR_WIDTH-1:0] state_out_reg = 0;
    reg [DATA_WIDTH-1:0] data_out_reg = 0;

    assign state_out = state_out_reg;
    assign data_out = data_out_reg;

    always @* begin
        for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
            state_out_reg[i] = 0;
            for (j = 0; j < LFSR_WIDTH; j = j + 1) begin
                if (lfsr_mask_state[i][j]) begin
                    state_out_reg[i] = state_out_reg[i] ^ state_in[j];
                end
            end
            for (j = 0; j < DATA_WIDTH; j = j + 1) begin
                if (lfsr_mask_data[i][j]) begin
                    state_out_reg[i] = state_out_reg[i] ^ data_in[j];
                end
            end
        end
        for (i = 0; i < DATA_WIDTH; i = i + 1) begin
            data_out_reg[i] = 0;
            for (j = 0; j < LFSR_WIDTH; j = j + 1) begin
                if (output_mask_state[i][j]) begin
                    data_out_reg[i] = data_out_reg[i] ^ state_in[j];
                end
            end
            for (j = 0; j < DATA_WIDTH; j = j + 1) begin
                if (output_mask_data[i][j]) begin
                    data_out_reg[i] = data_out_reg[i] ^ data_in[j];
                end
            end
        end
    end

end else begin

    initial begin
        $error("Error: unknown style setting!");
        $finish;
    end

end

endgenerate

endmodule
module lfsr #
(

    parameter LFSR_WIDTH = 32,

    parameter LFSR_POLY = 31'h10000001,

    parameter LFSR_CONFIG = "FIBONACCI",

    parameter LFSR_FEED_FORWARD = 0,

    parameter REVERSE = 0,

    parameter DATA_WIDTH = 8,

    parameter STYLE = "AUTO"
)
(
    input  wire [DATA_WIDTH-1:0] data_in,
    input  wire [LFSR_WIDTH-1:0] state_in,
    output wire [DATA_WIDTH-1:0] data_out,
    output wire [LFSR_WIDTH-1:0] state_out
);




wire [LFSR_WIDTH-1:0] lfsr_mask_state[LFSR_WIDTH-1:0];
wire [DATA_WIDTH-1:0] lfsr_mask_data[LFSR_WIDTH-1:0];
wire [LFSR_WIDTH-1:0] output_mask_state[DATA_WIDTH-1:0];
wire [DATA_WIDTH-1:0] output_mask_data[DATA_WIDTH-1:0];

wire [LFSR_WIDTH-1:0] state_val;
wire [DATA_WIDTH-1:0] data_val;

integer i, j;

assign lfsr_mask_state[31] = 32'h00000082;
assign lfsr_mask_state[30] = 32'h000000c3;
assign lfsr_mask_state[29] = 32'h000000e3;
assign lfsr_mask_state[28] = 32'h00000071;
assign lfsr_mask_state[27] = 32'h000000ba;
assign lfsr_mask_state[26] = 32'h000000df;
assign lfsr_mask_state[25] = 32'h0000006f;
assign lfsr_mask_state[24] = 32'h000000b5;
assign lfsr_mask_state[23] = 32'h800000d8;
assign lfsr_mask_state[22] = 32'h4000006c;
assign lfsr_mask_state[21] = 32'h200000b4;
assign lfsr_mask_state[20] = 32'h100000d8;
assign lfsr_mask_state[19] = 32'h080000ee;
assign lfsr_mask_state[18] = 32'h04000077;
assign lfsr_mask_state[17] = 32'h0200003b;
assign lfsr_mask_state[16] = 32'h0100001d;
assign lfsr_mask_state[15] = 32'h0080008c;
assign lfsr_mask_state[14] = 32'h00400046;
assign lfsr_mask_state[13] = 32'h00200023;
assign lfsr_mask_state[12] = 32'h00100011;
assign lfsr_mask_state[11] = 32'h00080008;
assign lfsr_mask_state[10] = 32'h00040004;
assign lfsr_mask_state[9] = 32'h00020080;
assign lfsr_mask_state[8] = 32'h000100c2;
assign lfsr_mask_state[7] = 32'h00008061;
assign lfsr_mask_state[6] = 32'h00004030;
assign lfsr_mask_state[5] = 32'h0000209a;
assign lfsr_mask_state[4] = 32'h0000104d;
assign lfsr_mask_state[3] = 32'h00000826;
assign lfsr_mask_state[2] = 32'h00000413;
assign lfsr_mask_state[1] = 32'h00000209;
assign lfsr_mask_state[0] = 32'h00000104;

assign lfsr_mask_data[31] = 8'h82;
assign lfsr_mask_data[30] = 8'hc3;
assign lfsr_mask_data[29] = 8'he3;
assign lfsr_mask_data[28] = 8'h71;
assign lfsr_mask_data[27] = 8'hba;
assign lfsr_mask_data[26] = 8'hdf;
assign lfsr_mask_data[25] = 8'h6f;
assign lfsr_mask_data[24] = 8'hb5;
assign lfsr_mask_data[23] = 8'hd8;
assign lfsr_mask_data[22] = 8'h6c;
assign lfsr_mask_data[21] = 8'hb4;
assign lfsr_mask_data[20] = 8'hd8;
assign lfsr_mask_data[19] = 8'hee;
assign lfsr_mask_data[18] = 8'h77;
assign lfsr_mask_data[17] = 8'h3b;
assign lfsr_mask_data[16] = 8'h1d;
assign lfsr_mask_data[15] = 8'h8c;
assign lfsr_mask_data[14] = 8'h46;
assign lfsr_mask_data[13] = 8'h23;
assign lfsr_mask_data[12] = 8'h11;
assign lfsr_mask_data[11] = 8'h08;
assign lfsr_mask_data[10] = 8'h04;
assign lfsr_mask_data[9] = 8'h80;
assign lfsr_mask_data[8] = 8'hc2;
assign lfsr_mask_data[7] = 8'h61;
assign lfsr_mask_data[6] = 8'h30;
assign lfsr_mask_data[5] = 8'h9a;
assign lfsr_mask_data[4] = 8'h4d;
assign lfsr_mask_data[3] = 8'h26;
assign lfsr_mask_data[2] = 8'h13;
assign lfsr_mask_data[1] = 8'h09;
assign lfsr_mask_data[0] = 8'h04;

assign output_mask_state[7] = 32'h00000082;
assign output_mask_state[6] = 32'h00000041;
assign output_mask_state[5] = 32'h00000020;
assign output_mask_state[4] = 32'h00000010;
assign output_mask_state[3] = 32'h00000008;
assign output_mask_state[2] = 32'h00000004;
assign output_mask_state[1] = 32'h00000002;
assign output_mask_state[0] = 32'h00000001;

assign output_mask_data[7] = 8'h82;
assign output_mask_data[6] = 8'h41;
assign output_mask_data[5] = 8'h20;
assign output_mask_data[4] = 8'h10;
assign output_mask_data[3] = 8'h08;
assign output_mask_data[2] = 8'h04;
assign output_mask_data[1] = 8'h02;
assign output_mask_data[0] = 8'h01;

assign state_val = 32'h00000082;
assign data_val = 8'h82;


`define SIMULATION


`ifdef SIMULATION

parameter STYLE_INT = (STYLE == "AUTO") ? "REDUCTION" : STYLE;
`else

parameter STYLE_INT = (STYLE == "AUTO") ? "LOOP" : STYLE;
`endif

genvar n;

generate

if (STYLE_INT == "REDUCTION") begin







    for (n = 0; n < LFSR_WIDTH; n = n + 1) begin : loop1
        assign state_out[n] = ^{(state_in & lfsr_mask_state[n]), (data_in & lfsr_mask_data[n])};
    end
    for (n = 0; n < DATA_WIDTH; n = n + 1) begin : loop2
        assign data_out[n] = ^{(state_in & output_mask_state[n]), (data_in & output_mask_data[n])};
    end

end else if (STYLE_INT == "LOOP") begin







    reg [LFSR_WIDTH-1:0] state_out_reg = 0;
    reg [DATA_WIDTH-1:0] data_out_reg = 0;

    assign state_out = state_out_reg;
    assign data_out = data_out_reg;

    always @* begin
        for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
            state_out_reg[i] = 0;
            for (j = 0; j < LFSR_WIDTH; j = j + 1) begin
                if (lfsr_mask_state[i][j]) begin
                    state_out_reg[i] = state_out_reg[i] ^ state_in[j];
                end
            end
            for (j = 0; j < DATA_WIDTH; j = j + 1) begin
                if (lfsr_mask_data[i][j]) begin
                    state_out_reg[i] = state_out_reg[i] ^ data_in[j];
                end
            end
        end
        for (i = 0; i < DATA_WIDTH; i = i + 1) begin
            data_out_reg[i] = 0;
            for (j = 0; j < LFSR_WIDTH; j = j + 1) begin
                if (output_mask_state[i][j]) begin
                    data_out_reg[i] = data_out_reg[i] ^ state_in[j];
                end
            end
            for (j = 0; j < DATA_WIDTH; j = j + 1) begin
                if (output_mask_data[i][j]) begin
                    data_out_reg[i] = data_out_reg[i] ^ data_in[j];
                end
            end
        end
    end

end else begin

    initial begin
        $error("Error: unknown style setting!");
        $finish;
    end

end

endgenerate

endmodule