data/full_repos/permissive/515599642/Simple CPU module using Verilog/R_Register.v
1: b'%Error: Cannot find file containing module: CPU\n        ... Looked in:\n             data/full_repos/permissive/515599642/Simple/CPU\n             data/full_repos/permissive/515599642/Simple/CPU.v\n             data/full_repos/permissive/515599642/Simple/CPU.sv\n             CPU\n             CPU.v\n             CPU.sv\n             obj_dir/CPU\n             obj_dir/CPU.v\n             obj_dir/CPU.sv\n%Error: Cannot find file containing module: module\n%Error: Cannot find file containing module: using\n%Error: Cannot find file containing module: Verilog,data/full_repos/permissive/515599642\n%Error: Cannot find file containing module: data/full_repos/permissive/515599642/Simple\n%Error: Cannot find file containing module: Verilog/R_Register.v\n%Error: Exiting due to 6 error(s)\n'
module R_Reg(S, clk, R_EN, R); 
input [3:0] S;
input clk;
input R_EN;
output reg [3:0] R;

always@(posedge clk)begin
	if (R_EN==1)
		R=S;
	else
		R=R;
	end
endmodule
module R_Reg(S, clk, R_EN, R);
 
input [3:0] S;
input clk;
input R_EN;
output reg [3:0] R;

always@(posedge clk)begin
	if (R_EN==1)
		R=S;
	else
		R=R;
	end
endmodule