data/full_repos/permissive/443770883/lab6/Lab5-Student copy/reg_alu.v
1: b'%Error: Cannot find file containing module: copy,data/full_repos/permissive/443770883\n        ... Looked in:\n             data/full_repos/permissive/443770883/lab6/Lab5-Student/copy,data/full_repos/permissive/443770883\n             data/full_repos/permissive/443770883/lab6/Lab5-Student/copy,data/full_repos/permissive/443770883.v\n             data/full_repos/permissive/443770883/lab6/Lab5-Student/copy,data/full_repos/permissive/443770883.sv\n             copy,data/full_repos/permissive/443770883\n             copy,data/full_repos/permissive/443770883.v\n             copy,data/full_repos/permissive/443770883.sv\n             obj_dir/copy,data/full_repos/permissive/443770883\n             obj_dir/copy,data/full_repos/permissive/443770883.v\n             obj_dir/copy,data/full_repos/permissive/443770883.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/443770883/lab6/Lab5-Student\n%Error: Cannot find file containing module: copy/reg_alu.v\n%Error: Exiting due to 3 error(s)\n'
module mux2_16(input wire [15:0] din_regular, alu_out, input wire i, output wire [15:0]din_final);
	mux2 m0(din_regular[0], alu_out[0], i, din_final[0]);
	mux2 m1(din_regular[1], alu_out[1], i, din_final[1]);
	mux2 m2(din_regular[2], alu_out[2], i, din_final[2]);
	mux2 m3(din_regular[3], alu_out[3], i, din_final[3]);
	mux2 m4(din_regular[4], alu_out[4], i, din_final[4]);
	mux2 m5(din_regular[5], alu_out[5], i, din_final[5]);
	mux2 m6(din_regular[6], alu_out[6], i, din_final[6]);
	mux2 m7(din_regular[7], alu_out[7], i, din_final[7]);
	mux2 m8(din_regular[8], alu_out[8], i, din_final[8]);
	mux2 m9(din_regular[9], alu_out[9], i, din_final[9]);
	mux2 m10(din_regular[10], alu_out[10], i, din_final[10]);
	mux2 m11(din_regular[11], alu_out[11], i, din_final[11]);
	mux2 m12(din_regular[12], alu_out[12], i, din_final[12]);
	mux2 m13(din_regular[13], alu_out[13], i, din_final[13]);
	mux2 m14(din_regular[14], alu_out[14], i, din_final[14]);
	mux2 m15(din_regular[15], alu_out[15], i, din_final[15]);
endmodule
module mux2_16(input wire [15:0] din_regular, alu_out, input wire i, output wire [15:0]din_final);

	mux2 m0(din_regular[0], alu_out[0], i, din_final[0]);
	mux2 m1(din_regular[1], alu_out[1], i, din_final[1]);
	mux2 m2(din_regular[2], alu_out[2], i, din_final[2]);
	mux2 m3(din_regular[3], alu_out[3], i, din_final[3]);
	mux2 m4(din_regular[4], alu_out[4], i, din_final[4]);
	mux2 m5(din_regular[5], alu_out[5], i, din_final[5]);
	mux2 m6(din_regular[6], alu_out[6], i, din_final[6]);
	mux2 m7(din_regular[7], alu_out[7], i, din_final[7]);
	mux2 m8(din_regular[8], alu_out[8], i, din_final[8]);
	mux2 m9(din_regular[9], alu_out[9], i, din_final[9]);
	mux2 m10(din_regular[10], alu_out[10], i, din_final[10]);
	mux2 m11(din_regular[11], alu_out[11], i, din_final[11]);
	mux2 m12(din_regular[12], alu_out[12], i, din_final[12]);
	mux2 m13(din_regular[13], alu_out[13], i, din_final[13]);
	mux2 m14(din_regular[14], alu_out[14], i, din_final[14]);
	mux2 m15(din_regular[15], alu_out[15], i, din_final[15]);
endmodule