data/full_repos/permissive/407433468/PRJ0_EJEMPLO_1 (1)/PRJ0_EJEMPLO_1/rtl/CC_SEVENSEG1.v
1: b'%Error: Cannot find file containing module: (1)/PRJ0_EJEMPLO_1/rtl,data/full_repos/permissive/407433468\n        ... Looked in:\n             data/full_repos/permissive/407433468/PRJ0_EJEMPLO_1/(1)/PRJ0_EJEMPLO_1/rtl,data/full_repos/permissive/407433468\n             data/full_repos/permissive/407433468/PRJ0_EJEMPLO_1/(1)/PRJ0_EJEMPLO_1/rtl,data/full_repos/permissive/407433468.v\n             data/full_repos/permissive/407433468/PRJ0_EJEMPLO_1/(1)/PRJ0_EJEMPLO_1/rtl,data/full_repos/permissive/407433468.sv\n             (1)/PRJ0_EJEMPLO_1/rtl,data/full_repos/permissive/407433468\n             (1)/PRJ0_EJEMPLO_1/rtl,data/full_repos/permissive/407433468.v\n             (1)/PRJ0_EJEMPLO_1/rtl,data/full_repos/permissive/407433468.sv\n             obj_dir/(1)/PRJ0_EJEMPLO_1/rtl,data/full_repos/permissive/407433468\n             obj_dir/(1)/PRJ0_EJEMPLO_1/rtl,data/full_repos/permissive/407433468.v\n             obj_dir/(1)/PRJ0_EJEMPLO_1/rtl,data/full_repos/permissive/407433468.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/407433468/PRJ0_EJEMPLO_1\n%Error: Cannot find file containing module: (1)/PRJ0_EJEMPLO_1/rtl/CC_SEVENSEG1.v\n%Error: Exiting due to 3 error(s)\n'
module CC_SEVENSEG1(
 input CC_SEVENSEG1_CLOCK_50, CC_SEVENSEG1_RESET_InHigh,
 input [3:0] CC_SEVENSEG1_in0, CC_SEVENSEG1_in1, CC_SEVENSEG1_in2, CC_SEVENSEG1_in3,
 output CC_SEVENSEG1_a, CC_SEVENSEG1_b, CC_SEVENSEG1_c, CC_SEVENSEG1_d, CC_SEVENSEG1_e, CC_SEVENSEG1_f, CC_SEVENSEG1_g, CC_SEVENSEG1_dp,
 output [3:0] CC_SEVENSEG1_an
 );
 
localparam N = 15;
 
reg [N-1:0]count;
 
always @ (posedge CC_SEVENSEG1_CLOCK_50 or posedge CC_SEVENSEG1_RESET_InHigh)
 begin
  if (CC_SEVENSEG1_RESET_InHigh==1)
   count <= 0;
  else
   count <= count + 1;
 end
 
reg [6:0]sseg;
reg [3:0]an_temp;
 
always @ (*)
 begin
  case(count[N-1:N-2])
    
   2'b00 :
    begin
     sseg = CC_SEVENSEG1_in0;
     an_temp = 4'b0001;
    end
    
   2'b01:
    begin
     sseg = CC_SEVENSEG1_in1;
     an_temp = 4'b0010;
    end
    
   2'b10:
    begin
     sseg = CC_SEVENSEG1_in2;
     an_temp = 4'b0100;
    end
     
   2'b11:
    begin
     sseg = CC_SEVENSEG1_in3;
     an_temp = 4'b1000;
    end
  endcase
 end
assign CC_SEVENSEG1_an = an_temp;
 
 
reg [6:0] sseg_temp;
 
always @ (*)
 begin
  case(sseg)

   4'd0 : sseg_temp = 7'b1000000;

	4'd1 : sseg_temp = 7'b1111001;
   4'd2 : sseg_temp = 7'b0100100;
   4'd3 : sseg_temp = 7'b0110000;
   4'd4 : sseg_temp = 7'b0011001;
   4'd5 : sseg_temp = 7'b0010010;
   4'd6 : sseg_temp = 7'b0000010;
   4'd7 : sseg_temp = 7'b1111000;
   4'd8 : sseg_temp = 7'b0000000;
   4'd9 : sseg_temp = 7'b0010000;
   default : sseg_temp = 7'b0111111;
  endcase
 end
assign {CC_SEVENSEG1_g, CC_SEVENSEG1_f, CC_SEVENSEG1_e, CC_SEVENSEG1_d, CC_SEVENSEG1_c, CC_SEVENSEG1_b, CC_SEVENSEG1_a} = sseg_temp;


 
assign CC_SEVENSEG1_dp = 1'b0;
 
 
endmodule
module CC_SEVENSEG1(
 input CC_SEVENSEG1_CLOCK_50, CC_SEVENSEG1_RESET_InHigh,
 input [3:0] CC_SEVENSEG1_in0, CC_SEVENSEG1_in1, CC_SEVENSEG1_in2, CC_SEVENSEG1_in3,
 output CC_SEVENSEG1_a, CC_SEVENSEG1_b, CC_SEVENSEG1_c, CC_SEVENSEG1_d, CC_SEVENSEG1_e, CC_SEVENSEG1_f, CC_SEVENSEG1_g, CC_SEVENSEG1_dp,
 output [3:0] CC_SEVENSEG1_an
 );

 
localparam N = 15;
 
reg [N-1:0]count;
 
always @ (posedge CC_SEVENSEG1_CLOCK_50 or posedge CC_SEVENSEG1_RESET_InHigh)
 begin
  if (CC_SEVENSEG1_RESET_InHigh==1)
   count <= 0;
  else
   count <= count + 1;
 end
 
reg [6:0]sseg;
reg [3:0]an_temp;
 
always @ (*)
 begin
  case(count[N-1:N-2])
    
   2'b00 :
    begin
     sseg = CC_SEVENSEG1_in0;
     an_temp = 4'b0001;
    end
    
   2'b01:
    begin
     sseg = CC_SEVENSEG1_in1;
     an_temp = 4'b0010;
    end
    
   2'b10:
    begin
     sseg = CC_SEVENSEG1_in2;
     an_temp = 4'b0100;
    end
     
   2'b11:
    begin
     sseg = CC_SEVENSEG1_in3;
     an_temp = 4'b1000;
    end
  endcase
 end
assign CC_SEVENSEG1_an = an_temp;
 
 
reg [6:0] sseg_temp;
 
always @ (*)
 begin
  case(sseg)

   4'd0 : sseg_temp = 7'b1000000;

	4'd1 : sseg_temp = 7'b1111001;
   4'd2 : sseg_temp = 7'b0100100;
   4'd3 : sseg_temp = 7'b0110000;
   4'd4 : sseg_temp = 7'b0011001;
   4'd5 : sseg_temp = 7'b0010010;
   4'd6 : sseg_temp = 7'b0000010;
   4'd7 : sseg_temp = 7'b1111000;
   4'd8 : sseg_temp = 7'b0000000;
   4'd9 : sseg_temp = 7'b0010000;
   default : sseg_temp = 7'b0111111;
  endcase
 end
assign {CC_SEVENSEG1_g, CC_SEVENSEG1_f, CC_SEVENSEG1_e, CC_SEVENSEG1_d, CC_SEVENSEG1_c, CC_SEVENSEG1_b, CC_SEVENSEG1_a} = sseg_temp;


 
assign CC_SEVENSEG1_dp = 1'b0;
 
 
endmodule