data/full_repos/permissive/524509242/Audio Recorder/debouncer.v
1: b'%Error: Cannot find file containing module: Recorder,data/full_repos/permissive/524509242\n        ... Looked in:\n             data/full_repos/permissive/524509242/Audio/Recorder,data/full_repos/permissive/524509242\n             data/full_repos/permissive/524509242/Audio/Recorder,data/full_repos/permissive/524509242.v\n             data/full_repos/permissive/524509242/Audio/Recorder,data/full_repos/permissive/524509242.sv\n             Recorder,data/full_repos/permissive/524509242\n             Recorder,data/full_repos/permissive/524509242.v\n             Recorder,data/full_repos/permissive/524509242.sv\n             obj_dir/Recorder,data/full_repos/permissive/524509242\n             obj_dir/Recorder,data/full_repos/permissive/524509242.v\n             obj_dir/Recorder,data/full_repos/permissive/524509242.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/524509242/Audio\n%Error: Cannot find file containing module: Recorder/debouncer.v\n%Error: Exiting due to 3 error(s)\n'
module debouncer(
    input clk,
    input i_btn,
    output reg o_state,
    output o_ondn,
    output o_onup
    );


    reg sync_0, sync_1;
    always @(posedge clk) sync_0 <= i_btn;
    always @(posedge clk) sync_1 <= sync_0;


    reg [18:0] counter;
    wire idle = (o_state == sync_1);
    wire max = &counter;

    always @(posedge clk)
    begin
        if (idle)
            counter <= 0;
        else
        begin
            counter <= counter + 1;
            if (max)
                o_state <= ~o_state;
        end
    end

    assign o_ondn = ~idle & max & ~o_state;
    assign o_onup = ~idle & max & o_state;
endmodule
module debouncer(
    input clk,
    input i_btn,
    output reg o_state,
    output o_ondn,
    output o_onup
    );



    reg sync_0, sync_1;
    always @(posedge clk) sync_0 <= i_btn;
    always @(posedge clk) sync_1 <= sync_0;


    reg [18:0] counter;
    wire idle = (o_state == sync_1);
    wire max = &counter;

    always @(posedge clk)
    begin
        if (idle)
            counter <= 0;
        else
        begin
            counter <= counter + 1;
            if (max)
                o_state <= ~o_state;
        end
    end

    assign o_ondn = ~idle & max & ~o_state;
    assign o_onup = ~idle & max & o_state;
endmodule