data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v
1: b'%Error: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:3: Cannot find include file: inc/Defines.vh\n`include "inc/Defines.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/521867481/testbench,data/full_repos/permissive/521867481/inc/Defines.vh\n             data/full_repos/permissive/521867481/testbench,data/full_repos/permissive/521867481/inc/Defines.vh.v\n             data/full_repos/permissive/521867481/testbench,data/full_repos/permissive/521867481/inc/Defines.vh.sv\n             inc/Defines.vh\n             inc/Defines.vh.v\n             inc/Defines.vh.sv\n             obj_dir/inc/Defines.vh\n             obj_dir/inc/Defines.vh.v\n             obj_dir/inc/Defines.vh.sv\n%Error: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:4: Cannot find include file: src/Uart8Receiver.v\n`include "src/Uart8Receiver.v" \n         ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:8: Define or directive not defined: \'`CLOCK_RATE_100MHZ\'\n parameter CLOCK_RATE   = `CLOCK_RATE_100MHZ;\n                          ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:8: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter CLOCK_RATE   = `CLOCK_RATE_100MHZ;\n                                            ^\n%Error: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:9: Define or directive not defined: \'`BAUD_RATE_115200\'\n parameter BAUD_RATE    = `BAUD_RATE_115200;\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:9: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter BAUD_RATE    = `BAUD_RATE_115200;\n                                           ^\n%Error: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:10: Define or directive not defined: \'`OVERSAMPLING_16\'\n parameter OVERSAMPLING = `OVERSAMPLING_16;\n                          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:10: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter OVERSAMPLING = `OVERSAMPLING_16;\n                                          ^\n%Error: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:11: Define or directive not defined: \'`DATA_BITS_8\'\n parameter DATA_BITS    = `DATA_BITS_8;\n                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:11: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter DATA_BITS    = `DATA_BITS_8;\n                                      ^\n%Error: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:39: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("test.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:40: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(-1, test);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX in = 0;  \n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX in = 1;  \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX in = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX in = 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX in = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX in = 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX in = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX in = 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX in = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX in = 1;  \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX in = 0;  \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX in = 0;  \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX in = 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX in = 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX in = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX in = 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX in = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX in = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX in = 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n   #CLOCK_RX in = 1;  \n   ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n  #MAX_RATE_RX rxClk = ~rxClk;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/521867481/testbench/Uart8Receiver_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n  #25000 $finish;\n  ^\n%Error: Exiting due to 12 error(s), 22 warning(s)\n'
module tbUart8Receiver();

	parameter CLOCK_RATE   = `CLOCK_RATE_100MHZ;
	parameter BAUD_RATE    = `BAUD_RATE_115200;
	parameter OVERSAMPLING = `OVERSAMPLING_16;
	parameter DATA_BITS    = `DATA_BITS_8;

    localparam MAX_RATE_RX = CLOCK_RATE / (2 * BAUD_RATE * OVERSAMPLING);
	localparam CLOCK_RX = MAX_RATE_RX * OVERSAMPLING * 2;

	reg rxClk = 0;
	reg en	  = 1;
	reg in    = 1;

	wire [DATA_BITS - 1:0] out;
	wire                   done;
	wire                   busy;
	wire                   err;

	Uart8Receiver #(
        .OVERSAMPLING(OVERSAMPLING),
        .DATA_BITS(DATA_BITS)
	) test (
		.clk(rxClk),
        .en(en),
        .in(in),
        .out(out),
        .done(done),
        .busy(busy),
        .err(err)
    );

	initial begin
		$dumpfile("test.vcd");
		$dumpvars(-1, test);
    end

	initial begin
		begin
			#CLOCK_RX in = 0;

			#CLOCK_RX in = 1;
			#CLOCK_RX in = 0;
			#CLOCK_RX in = 1;
			#CLOCK_RX in = 0;
			#CLOCK_RX in = 1;
			#CLOCK_RX in = 0;
			#CLOCK_RX in = 1;
			#CLOCK_RX in = 0;

			#CLOCK_RX in = 1;
		end

		begin
			#CLOCK_RX in = 0;

			#CLOCK_RX in = 0;
			#CLOCK_RX in = 1;
			#CLOCK_RX in = 1;
			#CLOCK_RX in = 0;
			#CLOCK_RX in = 1;
			#CLOCK_RX in = 0;
			#CLOCK_RX in = 0;
			#CLOCK_RX in = 1;

			#CLOCK_RX in = 1;
		end
	end

	always begin
		#MAX_RATE_RX rxClk = ~rxClk;

	end

	initial begin
		#25000 $finish;
	end

endmodule
module tbUart8Receiver();


	parameter CLOCK_RATE   = `CLOCK_RATE_100MHZ;
	parameter BAUD_RATE    = `BAUD_RATE_115200;
	parameter OVERSAMPLING = `OVERSAMPLING_16;
	parameter DATA_BITS    = `DATA_BITS_8;

    localparam MAX_RATE_RX = CLOCK_RATE / (2 * BAUD_RATE * OVERSAMPLING);
	localparam CLOCK_RX = MAX_RATE_RX * OVERSAMPLING * 2;

	reg rxClk = 0;
	reg en	  = 1;
	reg in    = 1;

	wire [DATA_BITS - 1:0] out;
	wire                   done;
	wire                   busy;
	wire                   err;

	Uart8Receiver #(
        .OVERSAMPLING(OVERSAMPLING),
        .DATA_BITS(DATA_BITS)
	) test (
		.clk(rxClk),
        .en(en),
        .in(in),
        .out(out),
        .done(done),
        .busy(busy),
        .err(err)
    );

	initial begin
		$dumpfile("test.vcd");
		$dumpvars(-1, test);
    end

	initial begin
		begin
			#CLOCK_RX in = 0;

			#CLOCK_RX in = 1;
			#CLOCK_RX in = 0;
			#CLOCK_RX in = 1;
			#CLOCK_RX in = 0;
			#CLOCK_RX in = 1;
			#CLOCK_RX in = 0;
			#CLOCK_RX in = 1;
			#CLOCK_RX in = 0;

			#CLOCK_RX in = 1;
		end

		begin
			#CLOCK_RX in = 0;

			#CLOCK_RX in = 0;
			#CLOCK_RX in = 1;
			#CLOCK_RX in = 1;
			#CLOCK_RX in = 0;
			#CLOCK_RX in = 1;
			#CLOCK_RX in = 0;
			#CLOCK_RX in = 0;
			#CLOCK_RX in = 1;

			#CLOCK_RX in = 1;
		end
	end

	always begin
		#MAX_RATE_RX rxClk = ~rxClk;

	end

	initial begin
		#25000 $finish;
	end

endmodule