data/full_repos/permissive/518429303/iiitb_usr_tb.v
1: b'%Error: data/full_repos/permissive/518429303/iiitb_usr_tb.v:13: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("iiitb_usr_out.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/518429303/iiitb_usr_tb.v:14: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0,iiitb_usr_tb);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/518429303/iiitb_usr_tb.v:15: Unsupported or unknown PLI call: $monitor\n        $monitor($time," clear=%b, select=%b , data_in=%b , data_out=%b \\n",clear,select,data_in,data_out);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/518429303/iiitb_usr_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #6\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/518429303/iiitb_usr_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #30 select=2\'b00;    \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/518429303/iiitb_usr_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #30 select=2\'b10;    \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/518429303/iiitb_usr_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #30 select=2\'b11;    \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/518429303/iiitb_usr_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #20 clear=1;     \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/518429303/iiitb_usr_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #20 clear=0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/518429303/iiitb_usr_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #5 clock=!clock;\n        ^\n%Error: Exiting due to 3 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module iiitb_usr_tb;
    reg [7:0] data_in;
    wire [7:0] data_out;
    reg clear,clock,sl_ser,sr_ser;
    reg [1:0] select;
    
    iiitb_usr usr(data_in,data_out,clock,clear,select,sl_ser,sr_ser);
    
    initial
    begin
        $dumpfile("iiitb_usr_out.vcd");
        $dumpvars(0,iiitb_usr_tb);
        $monitor($time," clear=%b, select=%b , data_in=%b , data_out=%b \n",clear,select,data_in,data_out);
        clock=0;
        clear=1;
        data_in=8'b10101011;
        sl_ser=1'b1;
        sr_ser=1'b1;
        select=2'b01;
        #6
        clear=0;
        #30 select=2'b00;
        #30 select=2'b10;
        #30 select=2'b11;
            data_in=8'b11110000;
        #20 clear=1;
        #20 clear=0;
            select=2'b10;
    end
    
    always
        #5 clock=!clock;
        
endmodule
module iiitb_usr_tb;

    reg [7:0] data_in;
    wire [7:0] data_out;
    reg clear,clock,sl_ser,sr_ser;
    reg [1:0] select;
    
    iiitb_usr usr(data_in,data_out,clock,clear,select,sl_ser,sr_ser);
    
    initial
    begin
        $dumpfile("iiitb_usr_out.vcd");
        $dumpvars(0,iiitb_usr_tb);
        $monitor($time," clear=%b, select=%b , data_in=%b , data_out=%b \n",clear,select,data_in,data_out);
        clock=0;
        clear=1;
        data_in=8'b10101011;
        sl_ser=1'b1;
        sr_ser=1'b1;
        select=2'b01;
        #6
        clear=0;
        #30 select=2'b00;
        #30 select=2'b10;
        #30 select=2'b11;
            data_in=8'b11110000;
        #20 clear=1;
        #20 clear=0;
            select=2'b10;
    end
    
    always
        #5 clock=!clock;
        
endmodule