data/full_repos/permissive/507506290/RTL_Files/ALU_DECODER.v
data/verilator_xmls/436d208d-82dd-458a-8e70-a38de5dc91cc.xml
module ALU_DECODER(i_func, i_ALUOp , o_ALU_control);
input [`WIDTH_FUNC-1:0] i_func ;
input [`WIDTH_ALU_OP-1:0] i_ALUOp;
output  [`WIDTH_Alu_cntrl-1:0] o_ALU_control;

reg [`WIDTH_Alu_cntrl-1:0] ALU_control ;

parameter ADD = 6'b10_0000,
          SUB = 6'b10_0010,
          AND = 6'b10_0100,
          OR = 6'b10_0101,
          SLT = 6'b10_1010,
          NOR = 6'b10_0011;
          
 
 always @(*)
    begin
        case (i_ALUOp)
        2'b00  : ALU_control = 4'b0010;
        2'b01  : ALU_control = 4'b0110;
        2'b10  : 
                case (i_func)
             ADD : ALU_control = 4'b0010;
             SUB : ALU_control = 4'b0110;
             AND : ALU_control = 4'b0000;
             OR  : ALU_control = 4'b0001;
             SLT : ALU_control = 4'b0111;
             NOR : ALU_control = 4'b1100;
             default : ALU_control = 4'bx; 
         endcase
         default : ALU_control = 4'bx;
      endcase    
   end   
 
 
 assign o_ALU_control = ALU_control ;
 
 
endmodule
module ALU_DECODER(i_func, i_ALUOp , o_ALU_control);

input [`WIDTH_FUNC-1:0] i_func ;
input [`WIDTH_ALU_OP-1:0] i_ALUOp;
output  [`WIDTH_Alu_cntrl-1:0] o_ALU_control;

reg [`WIDTH_Alu_cntrl-1:0] ALU_control ;

parameter ADD = 6'b10_0000,
          SUB = 6'b10_0010,
          AND = 6'b10_0100,
          OR = 6'b10_0101,
          SLT = 6'b10_1010,
          NOR = 6'b10_0011;
          
 
 always @(*)
    begin
        case (i_ALUOp)
        2'b00  : ALU_control = 4'b0010;
        2'b01  : ALU_control = 4'b0110;
        2'b10  : 
                case (i_func)
             ADD : ALU_control = 4'b0010;
             SUB : ALU_control = 4'b0110;
             AND : ALU_control = 4'b0000;
             OR  : ALU_control = 4'b0001;
             SLT : ALU_control = 4'b0111;
             NOR : ALU_control = 4'b1100;
             default : ALU_control = 4'bx; 
         endcase
         default : ALU_control = 4'bx;
      endcase    
   end   
 
 
 assign o_ALU_control = ALU_control ;
 
 
endmodule