data/full_repos/permissive/446997925/hw3/and.v
data/verilator_xmls/e2b82ace-9d56-43df-a68f-94f4fe8a4f8c.xml
module and_8(out, a, b);
input [7:0] a, b;
output [7:0] out;

and_4 f(out[3:0], a[3:0], b[3:0]),
          s(out[7:4], a[7:4], b[7:4]);
endmodule
module and_8(out, a, b);

input [7:0] a, b;
output [7:0] out;

and_4 f(out[3:0], a[3:0], b[3:0]),
          s(out[7:4], a[7:4], b[7:4]);
endmodule