data/full_repos/permissive/426864978/midterm2/task1/drawline.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/426864978/midterm2/task1/drawline.sv:42: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'x1\' generates 8 bits.\n                                                                                  : ... In instance drawline\n                    tmp_dx = x1 - x0;\n                                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/426864978/midterm2/task1/drawline.sv:42: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'x0\' generates 8 bits.\n                                                                                  : ... In instance drawline\n                    tmp_dx = x1 - x0;\n                                ^\n%Warning-WIDTH: data/full_repos/permissive/426864978/midterm2/task1/drawline.sv:43: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'y1\' generates 7 bits.\n                                                                                  : ... In instance drawline\n                    tmp_dy = -1 * (y1 - y0);\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/426864978/midterm2/task1/drawline.sv:43: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'y0\' generates 7 bits.\n                                                                                  : ... In instance drawline\n                    tmp_dy = -1 * (y1 - y0);\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/426864978/midterm2/task1/drawline.sv:61: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'x\' generates 8 bits.\n                                                                                  : ... In instance drawline\n                            x = x + sx;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/426864978/midterm2/task1/drawline.sv:61: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                  : ... In instance drawline\n                            x = x + sx;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/426864978/midterm2/task1/drawline.sv:65: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'y\' generates 7 bits.\n                                                                                  : ... In instance drawline\n                            y = y + sy;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/426864978/midterm2/task1/drawline.sv:65: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                  : ... In instance drawline\n                            y = y + sy;\n                              ^\n%Warning-UNSIGNED: data/full_repos/permissive/426864978/midterm2/task1/drawline.sv:67: Comparison is constant due to unsigned arithmetic\n                                                                                     : ... In instance drawline\n                        out = (x < 0 || x > 159 || y < 0 || y > 119) ? 2\'b0 : 2\'b10;\n                                 ^\n%Warning-UNSIGNED: data/full_repos/permissive/426864978/midterm2/task1/drawline.sv:67: Comparison is constant due to unsigned arithmetic\n                                                                                     : ... In instance drawline\n                        out = (x < 0 || x > 159 || y < 0 || y > 119) ? 2\'b0 : 2\'b10;\n                                                     ^\n%Error: Exiting due to 10 warning(s)\n'
module drawline(
        input logic clk, input logic rst_n,
        input logic [2:0] colour,
        input logic [7:0] x0, input logic [6:0] y0,
        input logic [7:0] x1, input logic [6:0] y1,
        input logic start, output logic done,
        output logic [7:0] vga_x, output logic [6:0] vga_y,
        output logic [2:0] vga_colour, output logic vga_plot
    );


    `define IDLE 2'b00 
    `define CALC 2'b01
    `define DRAW 2'b10 
    `define DONE 2'b11

    `define X_BOUND 159
    `define Y_BOUND 119

    reg [31:0] dx, dy, sx, sy, err, tmp_dx, tmp_dy, e2;
    reg [1:0] state, out;
    reg [2:0] str_colour;
    reg [7:0] max_x, min_x, x;
    reg [6:0] max_y, min_y, y;

    assign { vga_x, vga_y, vga_colour } = { x, y, str_colour };
    assign { vga_plot, done } = out;


    always @(posedge clk) begin
        if (rst_n == 1'b0) begin
            state = `IDLE;
            x = 8'b0;
            y = 7'b0;
            str_colour = 3'b0;
            out = 2'b0;
        end else begin
            case ({state, start})
                {`IDLE, 1'b1}: begin
                    state = `DRAW;
                    str_colour = colour;
                    tmp_dx = x1 - x0;
                    tmp_dy = -1 * (y1 - y0);
                    dx = (tmp_dx[31] == 1'b1) ? -1 * tmp_dx : tmp_dx;
                    dy = (tmp_dy[31] == 1'b1) ? tmp_dy : -1 * tmp_dy;
                    sx = (x0 < x1) ? 1 : -1;
                    sy = (y0 < y1) ? 1 : -1;
                    err = dx + dy;
                    x = x0;
                    y = y0;
                    out = 2'b10;
                end
                {`DRAW, 1'b1}: begin
                   if (x == x1 && y == y1) begin
                       state = `DONE;
                       out = 2'b01;
                   end else begin
                       e2 = 2 * err;
                        if ( e2 >= dy ) begin
                            err = err + dy;
                            x = x + sx;
                        end
                        if( e2 <= dx ) begin
                            err = err + dx;
                            y = y + sy;
                        end
                        out = (x < 0 || x > `X_BOUND || y < 0 || y > `Y_BOUND) ? 2'b0 : 2'b10;
                   end
                end
                {`DONE, 1'b1}: begin
                    out = 2'b01;
                end
                default: begin
                    state = `IDLE;
                    x = 8'b0;
                    y = 7'b0;
                    str_colour = 3'b0;
                    out = 2'b0;
                end
            endcase
        end
    end

endmodule
module drawline(
        input logic clk, input logic rst_n,
        input logic [2:0] colour,
        input logic [7:0] x0, input logic [6:0] y0,
        input logic [7:0] x1, input logic [6:0] y1,
        input logic start, output logic done,
        output logic [7:0] vga_x, output logic [6:0] vga_y,
        output logic [2:0] vga_colour, output logic vga_plot
    );



    `define IDLE 2'b00 
    `define CALC 2'b01
    `define DRAW 2'b10 
    `define DONE 2'b11

    `define X_BOUND 159
    `define Y_BOUND 119

    reg [31:0] dx, dy, sx, sy, err, tmp_dx, tmp_dy, e2;
    reg [1:0] state, out;
    reg [2:0] str_colour;
    reg [7:0] max_x, min_x, x;
    reg [6:0] max_y, min_y, y;

    assign { vga_x, vga_y, vga_colour } = { x, y, str_colour };
    assign { vga_plot, done } = out;


    always @(posedge clk) begin
        if (rst_n == 1'b0) begin
            state = `IDLE;
            x = 8'b0;
            y = 7'b0;
            str_colour = 3'b0;
            out = 2'b0;
        end else begin
            case ({state, start})
                {`IDLE, 1'b1}: begin
                    state = `DRAW;
                    str_colour = colour;
                    tmp_dx = x1 - x0;
                    tmp_dy = -1 * (y1 - y0);
                    dx = (tmp_dx[31] == 1'b1) ? -1 * tmp_dx : tmp_dx;
                    dy = (tmp_dy[31] == 1'b1) ? tmp_dy : -1 * tmp_dy;
                    sx = (x0 < x1) ? 1 : -1;
                    sy = (y0 < y1) ? 1 : -1;
                    err = dx + dy;
                    x = x0;
                    y = y0;
                    out = 2'b10;
                end
                {`DRAW, 1'b1}: begin
                   if (x == x1 && y == y1) begin
                       state = `DONE;
                       out = 2'b01;
                   end else begin
                       e2 = 2 * err;
                        if ( e2 >= dy ) begin
                            err = err + dy;
                            x = x + sx;
                        end
                        if( e2 <= dx ) begin
                            err = err + dx;
                            y = y + sy;
                        end
                        out = (x < 0 || x > `X_BOUND || y < 0 || y > `Y_BOUND) ? 2'b0 : 2'b10;
                   end
                end
                {`DONE, 1'b1}: begin
                    out = 2'b01;
                end
                default: begin
                    state = `IDLE;
                    x = 8'b0;
                    y = 7'b0;
                    str_colour = 3'b0;
                    out = 2'b0;
                end
            endcase
        end
    end

endmodule