data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/macro/fflopx.v
data/verilator_xmls/bf12b674-6691-4242-9f47-26241ea36342.xml
module fflopx
    (
     clk,
     rst,
     idat,
     odat
     );

parameter WIDTH = 8;
parameter RESET_VALUE = {WIDTH{1'b0}};
parameter RESET_ON = 0;

input   clk, rst;

input  [WIDTH-1:0] idat;

output [WIDTH-1:0] odat;


generate
if (RESET_ON == 0)
    begin: no_reset



    reg    [WIDTH-1:0] iodat = RESET_VALUE;
    assign             odat = iodat;
    always @ (posedge clk)
        begin
        iodat <= idat;
        end

    end
else
    begin:with_reset    



    reg    [WIDTH-1:0] iodat = RESET_VALUE;
    assign             odat = iodat;
    always @ (posedge clk)
        begin
        if (rst) iodat <= RESET_VALUE;
        else iodat <= idat;
        end

    end
endgenerate

endmodule
module fflopx
    (
     clk,
     rst,
     idat,
     odat
     );


parameter WIDTH = 8;
parameter RESET_VALUE = {WIDTH{1'b0}};
parameter RESET_ON = 0;

input   clk, rst;

input  [WIDTH-1:0] idat;

output [WIDTH-1:0] odat;


generate
if (RESET_ON == 0)
    begin: no_reset



    reg    [WIDTH-1:0] iodat = RESET_VALUE;
    assign             odat = iodat;
    always @ (posedge clk)
        begin
        iodat <= idat;
        end

    end
else
    begin:with_reset    



    reg    [WIDTH-1:0] iodat = RESET_VALUE;
    assign             odat = iodat;
    always @ (posedge clk)
        begin
        if (rst) iodat <= RESET_VALUE;
        else iodat <= idat;
        end

    end
endgenerate

endmodule