data/full_repos/permissive/527578197/v1/testbench/top_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/527578197/v1/testbench/top_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\nalways #10 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/527578197/v1/testbench/top_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #2 rst_n <= 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/527578197/v1/testbench/top_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #5 data_in <= {16\'d1,16\'d2,16\'d3,16\'d4,16\'d5,16\'d6,16\'d7,16\'d8,16\'d9,16\'d10,  16\'d1,16\'d1,16\'d1,16\'d1,16\'d1,16\'d6,16\'d6,16\'d6,16\'d6,16\'d6};\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/527578197/v1/testbench/top_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #160 data_in <= {16\'d2,16\'d2,16\'d2,16\'d2,16\'d2,16\'d2,16\'d2,16\'d2,16\'d2,16\'d2,  16\'d2,16\'d2,16\'d2,16\'d2,16\'d2,16\'d2,16\'d2,16\'d2,16\'d2,16\'d2}; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/527578197/v1/testbench/top_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #160 data_in <= {16\'d3,16\'d3,16\'d3,16\'d3,16\'d3,16\'d3,16\'d3,16\'d3,16\'d3,16\'d3,  16\'d3,16\'d3,16\'d3,16\'d3,16\'d3,16\'d3,16\'d3,16\'d3,16\'d3,16\'d3}; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/527578197/v1/testbench/top_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #160 data_in <= {16\'d4,16\'d4,16\'d4,16\'d4,16\'d4,16\'d4,16\'d4,16\'d4,16\'d4,16\'d4,  16\'d4,16\'d4,16\'d4,16\'d4,16\'d4,16\'d4,16\'d4,16\'d4,16\'d4,16\'d4}; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/527578197/v1/testbench/top_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #160 data_in <= {16\'d5,16\'d5,16\'d5,16\'d5,16\'d5,16\'d5,16\'d5,16\'d5,16\'d5,16\'d5,  16\'d5,16\'d5,16\'d5,16\'d5,16\'d5,16\'d5,16\'d5,16\'d5,16\'d5,16\'d5}; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/527578197/v1/testbench/top_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #160 data_in <= {16\'d6,16\'d6,16\'d6,16\'d6,16\'d6,16\'d6,16\'d6,16\'d6,16\'d6,16\'d6,  16\'d6,16\'d6,16\'d6,16\'d6,16\'d6,16\'d6,16\'d6,16\'d6,16\'d6,16\'d6}; \n    ^\n%Error: data/full_repos/permissive/527578197/v1/testbench/top_tb.v:46: Unsupported or unknown PLI call: $fsdbDumpfile\n $fsdbDumpfile("wave.fsdb");\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/527578197/v1/testbench/top_tb.v:47: Unsupported or unknown PLI call: $fsdbDumpvars\n $fsdbDumpvars("+all");\n ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/527578197/v1/testbench/top_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n#1000000 $finish;\n^\n%Error: Exiting due to 2 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_tb ();
reg                 clk               ,
                    rst_n             ,
                    read_en           ;
reg   [15:0]        data_in[1:20]     ;
reg                 empty             ;
wire  [1:0]         result            ;

always #10 clk = ~clk;
always @(negedge clk) read_en = (empty==1)? 1 : 0;
initial begin
    clk     <= 0;
    rst_n   <= 0;
    #2 rst_n <= 1;

    #5 data_in <= {16'd1,16'd2,16'd3,16'd4,16'd5,16'd6,16'd7,16'd8,16'd9,16'd10,  16'd1,16'd1,16'd1,16'd1,16'd1,16'd6,16'd6,16'd6,16'd6,16'd6};
    #160 data_in <= {16'd2,16'd2,16'd2,16'd2,16'd2,16'd2,16'd2,16'd2,16'd2,16'd2,  16'd2,16'd2,16'd2,16'd2,16'd2,16'd2,16'd2,16'd2,16'd2,16'd2};
    #160 data_in <= {16'd3,16'd3,16'd3,16'd3,16'd3,16'd3,16'd3,16'd3,16'd3,16'd3,  16'd3,16'd3,16'd3,16'd3,16'd3,16'd3,16'd3,16'd3,16'd3,16'd3};

    #160 data_in <= {16'd4,16'd4,16'd4,16'd4,16'd4,16'd4,16'd4,16'd4,16'd4,16'd4,  16'd4,16'd4,16'd4,16'd4,16'd4,16'd4,16'd4,16'd4,16'd4,16'd4};
    #160 data_in <= {16'd5,16'd5,16'd5,16'd5,16'd5,16'd5,16'd5,16'd5,16'd5,16'd5,  16'd5,16'd5,16'd5,16'd5,16'd5,16'd5,16'd5,16'd5,16'd5,16'd5};
    #160 data_in <= {16'd6,16'd6,16'd6,16'd6,16'd6,16'd6,16'd6,16'd6,16'd6,16'd6,  16'd6,16'd6,16'd6,16'd6,16'd6,16'd6,16'd6,16'd6,16'd6,16'd6};

end

top top_u1(
    .clk         (clk),
    .rst_n       (rst_n),
    .read_en     (read_en),
    .data_in     (data_in),
    .empty       (empty),
    .result      (result)    
);

initial begin
	$fsdbDumpfile("wave.fsdb");
	$fsdbDumpvars("+all");
end
initial begin
#1000000	$finish;
end

endmodule
module top_tb ();

reg                 clk               ,
                    rst_n             ,
                    read_en           ;
reg   [15:0]        data_in[1:20]     ;
reg                 empty             ;
wire  [1:0]         result            ;

always #10 clk = ~clk;
always @(negedge clk) read_en = (empty==1)? 1 : 0;
initial begin
    clk     <= 0;
    rst_n   <= 0;
    #2 rst_n <= 1;

    #5 data_in <= {16'd1,16'd2,16'd3,16'd4,16'd5,16'd6,16'd7,16'd8,16'd9,16'd10,  16'd1,16'd1,16'd1,16'd1,16'd1,16'd6,16'd6,16'd6,16'd6,16'd6};
    #160 data_in <= {16'd2,16'd2,16'd2,16'd2,16'd2,16'd2,16'd2,16'd2,16'd2,16'd2,  16'd2,16'd2,16'd2,16'd2,16'd2,16'd2,16'd2,16'd2,16'd2,16'd2};
    #160 data_in <= {16'd3,16'd3,16'd3,16'd3,16'd3,16'd3,16'd3,16'd3,16'd3,16'd3,  16'd3,16'd3,16'd3,16'd3,16'd3,16'd3,16'd3,16'd3,16'd3,16'd3};

    #160 data_in <= {16'd4,16'd4,16'd4,16'd4,16'd4,16'd4,16'd4,16'd4,16'd4,16'd4,  16'd4,16'd4,16'd4,16'd4,16'd4,16'd4,16'd4,16'd4,16'd4,16'd4};
    #160 data_in <= {16'd5,16'd5,16'd5,16'd5,16'd5,16'd5,16'd5,16'd5,16'd5,16'd5,  16'd5,16'd5,16'd5,16'd5,16'd5,16'd5,16'd5,16'd5,16'd5,16'd5};
    #160 data_in <= {16'd6,16'd6,16'd6,16'd6,16'd6,16'd6,16'd6,16'd6,16'd6,16'd6,  16'd6,16'd6,16'd6,16'd6,16'd6,16'd6,16'd6,16'd6,16'd6,16'd6};

end

top top_u1(
    .clk         (clk),
    .rst_n       (rst_n),
    .read_en     (read_en),
    .data_in     (data_in),
    .empty       (empty),
    .result      (result)    
);

initial begin
	$fsdbDumpfile("wave.fsdb");
	$fsdbDumpvars("+all");
end
initial begin
#1000000	$finish;
end

endmodule