data/full_repos/permissive/419538859/lab7/lab7_1/sim/lab7_1_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/419538859/lab7/lab7_1/sim/lab7_1_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n #(clkper / 2)  clk = ~clk;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab7/lab7_1/sim/lab7_1_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n #20;    \n ^\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab7/lab7_1/sim/lab7_1_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n #3110;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab7/lab7_1/sim/lab7_1_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n #32\n ^\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab7/lab7_1/sim/lab7_1_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n #3110;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/419538859/lab7/lab7_1/sim/lab7_1_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n #3110;\n ^\n%Error: data/full_repos/permissive/419538859/lab7/lab7_1/sim/lab7_1_tb.v:15: Cannot find file containing module: \'lab7_1\'\nlab7_1 lab7_1_instance(\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/419538859/lab7/lab7_1/sim,data/full_repos/permissive/419538859/lab7_1\n             data/full_repos/permissive/419538859/lab7/lab7_1/sim,data/full_repos/permissive/419538859/lab7_1.v\n             data/full_repos/permissive/419538859/lab7/lab7_1/sim,data/full_repos/permissive/419538859/lab7_1.sv\n             lab7_1\n             lab7_1.v\n             lab7_1.sv\n             obj_dir/lab7_1\n             obj_dir/lab7_1.v\n             obj_dir/lab7_1.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module 	testbench;
reg		clk, reset, enable, day_night;
wire	[5:0]light_led;
wire	led_com;
wire	[6:0]seg7;
wire	[2:0]seg7_sel;
wire	[7:0]g1_cnt;
wire	clk_cnt, clk_sel;
wire	[3:0]count_out;
wire	[1:0]light_mode;


lab7_1 lab7_1_instance(
		.clk(clk),
		.reset(reset),
		.day_night(day_night),
		.light_led(light_led),
		.led_com(led_com),
		.seg7(seg7),
		.seg7_sel(seg7_sel));
parameter	exp = 1; 
parameter clkper = 5;
initial
begin
	clk = 1;
end

always 
begin
	#(clkper / 2)  clk = ~clk;
end

initial
begin
 reset = 1'b1;
 day_night=1'b1;
 #20;
 reset = 1'b0;
 #32
 #3110;
 #3110;
 #3110;
end
endmodule
module 	testbench;

reg		clk, reset, enable, day_night;
wire	[5:0]light_led;
wire	led_com;
wire	[6:0]seg7;
wire	[2:0]seg7_sel;
wire	[7:0]g1_cnt;
wire	clk_cnt, clk_sel;
wire	[3:0]count_out;
wire	[1:0]light_mode;


lab7_1 lab7_1_instance(
		.clk(clk),
		.reset(reset),
		.day_night(day_night),
		.light_led(light_led),
		.led_com(led_com),
		.seg7(seg7),
		.seg7_sel(seg7_sel));
parameter	exp = 1; 
parameter clkper = 5;
initial
begin
	clk = 1;
end

always 
begin
	#(clkper / 2)  clk = ~clk;
end

initial
begin
 reset = 1'b1;
 day_night=1'b1;
 #20;
 reset = 1'b0;
 #32
 #3110;
 #3110;
 #3110;
end
endmodule