data/full_repos/permissive/433621701/generic_CB_array/generic_CB_array.v
data/verilator_xmls/fd06e278-bb93-4e8c-8afc-57a7fd90af91.xml
module Full_Adder_LR_four_in(input in0, in1, in2, in3, carry_in, output reg sum, carry_out);
    always @(in0 or in1 or in2 or in3 or carry_in)
    begin
        sum = (in0&in1) ^ (in2&in3) ^ carry_in;
        carry_out = (in0&in1) & (in2&in3) | ((in0&in1)^(in2&in3)) & carry_in;
    end
endmodule
module Full_Adder_LR_four_in(input in0, in1, in2, in3, carry_in, output reg sum, carry_out);

    always @(in0 or in1 or in2 or in3 or carry_in)
    begin
        sum = (in0&in1) ^ (in2&in3) ^ carry_in;
        carry_out = (in0&in1) & (in2&in3) | ((in0&in1)^(in2&in3)) & carry_in;
    end
endmodule