data/full_repos/permissive/49670587/full-fpga-testing/custom_ms/multi_consumer/multi_consumer_fpga_tb.v
1: b'%Error: data/full_repos/permissive/49670587/full-fpga-testing/custom_ms/multi_consumer/multi_consumer_fpga_tb.v:16: Unsupported: wait statements\n        wait ( rdy == 1\'b1 );\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/49670587/full-fpga-testing/custom_ms/multi_consumer/multi_consumer_fpga_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #30\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/49670587/full-fpga-testing/custom_ms/multi_consumer/multi_consumer_fpga_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/49670587/full-fpga-testing/custom_ms/multi_consumer/multi_consumer_fpga_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #40\n        ^\n%Error: data/full_repos/permissive/49670587/full-fpga-testing/custom_ms/multi_consumer/multi_consumer_fpga_tb.v:34: Unsupported or unknown PLI call: $monitor\n        $monitor($time, ", clock = %b, rst = %b, d_in = %h, d_out_1 = %h, d_out_2 = %h d_out_4 = %h d_out_7 = %h",\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/49670587/full-fpga-testing/custom_ms/multi_consumer/multi_consumer_fpga_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #20 rst = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/49670587/full-fpga-testing/custom_ms/multi_consumer/multi_consumer_fpga_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #10 clock = ~clock;\n        ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module multi_consumer_tb();

    reg clock, rst;
    reg [15:0] d_in;
    wire [15:0] d_out_1, d_out_2, d_out_4, d_out_7;
    wire rdy;

    initial
    begin
        $display($time, " << Starting the Simulation >>");
    
        d_in = 16'b0;

        wait ( rdy == 1'b1 );
        begin
            d_in = 16'hffff;
        end

        #30
        d_in = 16'h00ff;

        #20
        d_in = 16'h0000;

        #40
        $display($time, " << Simulation Complete >>");
        $finish;
    end

    initial
    begin
        $monitor($time, ", clock = %b, rst = %b, d_in = %h, d_out_1 = %h, d_out_2 = %h d_out_4 = %h d_out_7 = %h",
                           clock, rst, d_in, d_out_1, d_out_2, d_out_4, d_out_7);
    end

    initial
    begin
        clock = 1'b1;
        rst = 1'b1;
        #20 rst = 1'b0;
    end

    always
    begin
        #10 clock = ~clock;
    end


    multi_consumer dut ( .d_in(d_in),
                         .d_out_1(d_out_1),
                         .d_out_2(d_out_2),
                         .d_out_4(d_out_4),
                         .d_out_7(d_out_7),
                         .clock(clock),
                         .rst(rst),
                         .rdy(rdy)
                        );

endmodule
module multi_consumer_tb();


    reg clock, rst;
    reg [15:0] d_in;
    wire [15:0] d_out_1, d_out_2, d_out_4, d_out_7;
    wire rdy;

    initial
    begin
        $display($time, " << Starting the Simulation >>");
    
        d_in = 16'b0;

        wait ( rdy == 1'b1 );
        begin
            d_in = 16'hffff;
        end

        #30
        d_in = 16'h00ff;

        #20
        d_in = 16'h0000;

        #40
        $display($time, " << Simulation Complete >>");
        $finish;
    end

    initial
    begin
        $monitor($time, ", clock = %b, rst = %b, d_in = %h, d_out_1 = %h, d_out_2 = %h d_out_4 = %h d_out_7 = %h",
                           clock, rst, d_in, d_out_1, d_out_2, d_out_4, d_out_7);
    end

    initial
    begin
        clock = 1'b1;
        rst = 1'b1;
        #20 rst = 1'b0;
    end

    always
    begin
        #10 clock = ~clock;
    end


    multi_consumer dut ( .d_in(d_in),
                         .d_out_1(d_out_1),
                         .d_out_2(d_out_2),
                         .d_out_4(d_out_4),
                         .d_out_7(d_out_7),
                         .clock(clock),
                         .rst(rst),
                         .rdy(rdy)
                        );

endmodule