data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/InstructionReg.v
data/verilator_xmls/f156182a-a649-4f33-9b82-2700a9095613.xml
module InstructionReg(
    input clk,
    input [3:0] addr,
    input [15:0] dIn,
    output [15:0] dOut
  );
    
  reg [15:0] mem [0:15];
  
  always @ (posedge clk) begin
    mem[addr] = dIn;
  end
  
  assign dOut[15:0] = mem[addr];
  
endmodule
module InstructionReg(
    input clk,
    input [3:0] addr,
    input [15:0] dIn,
    output [15:0] dOut
  );

    
  reg [15:0] mem [0:15];
  
  always @ (posedge clk) begin
    mem[addr] = dIn;
  end
  
  assign dOut[15:0] = mem[addr];
  
endmodule