data/full_repos/permissive/441359809/src/yosys/tests/simple/retime.v
data/verilator_xmls/b3a735a2-820a-4c79-a26c-f369fad913bd.xml
module retime_test(input clk, input [7:0] a, output z);
    reg [7:0] ff = 8'hF5;
    always @(posedge clk)
        ff <= {ff[6:0], ^a};
    assign z = ff[7];
endmodule
module retime_test(input clk, input [7:0] a, output z);

    reg [7:0] ff = 8'hF5;
    always @(posedge clk)
        ff <= {ff[6:0], ^a};
    assign z = ff[7];
endmodule