data/full_repos/permissive/46454310/dsp/dff.v
data/verilator_xmls/811332b0-6aa3-400c-a531-3322aa2b9ed8.xml
module dff(clk,rst,d,q);
input clk,rst;
input [7:0]d;
output [7:0]q;
reg [7:0]q;
always@(posedge clk)
begin
if(rst==1)
begin
q=0;
end
else
begin
q=d;
end
end

endmodule
module dff(clk,rst,d,q);

input clk,rst;
input [7:0]d;
output [7:0]q;
reg [7:0]q;
always@(posedge clk)
begin
if(rst==1)
begin
q=0;
end
else
begin
q=d;
end
end

endmodule