data/full_repos/permissive/450205124/Assignment3/Q2-parity-checker/A3Q2_t_flip_flop.v
data/verilator_xmls/423ef679-c33a-4932-83b3-643344c19211.xml
module t_flip_flop(q,t,clk,reset);
    output reg q=1'b1;
    input reset;
    input t,clk;

    always@(reset) begin
        q=1;
    end

    always @(posedge clk) begin
        if(t==1'b1) begin
            q=~q;
        end
    end
endmodule
module t_flip_flop(q,t,clk,reset);

    output reg q=1'b1;
    input reset;
    input t,clk;

    always@(reset) begin
        q=1;
    end

    always @(posedge clk) begin
        if(t==1'b1) begin
            q=~q;
        end
    end
endmodule