data/full_repos/permissive/488093047/Verilog Codes/Mux_2x1.v
1: b'%Error: Cannot find file containing module: Codes,data/full_repos/permissive/488093047\n        ... Looked in:\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.v\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.sv\n             Codes,data/full_repos/permissive/488093047\n             Codes,data/full_repos/permissive/488093047.v\n             Codes,data/full_repos/permissive/488093047.sv\n             obj_dir/Codes,data/full_repos/permissive/488093047\n             obj_dir/Codes,data/full_repos/permissive/488093047.v\n             obj_dir/Codes,data/full_repos/permissive/488093047.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/488093047/Verilog\n%Error: Cannot find file containing module: Codes/Mux_2x1.v\n%Error: Exiting due to 3 error(s)\n'
module Mux_2x1 #(parameter N = 32) (a,b,s,y);
input [N-1:0]a;
input [N-1:0]b;
input s;
output [N-1:0]y;
wire [N-1:0]S;
wire [N-1:0]F1,F2,F3;
assign S={(N){s}};
AND #(.N(N)) DUT1(.A(b),.B(S),.AND(F1));
NOT #(.N(N)) DUT2(.A(S),.NOT(F2));
AND #(.N(N)) DUT3(.A(a),.B(F2),.AND(F3));
OR  #(.N(N)) DUT4(.A(F1),.B(F3),.OR(y));


endmodule
module Mux_2x1 #(parameter N = 32) (a,b,s,y);

input [N-1:0]a;
input [N-1:0]b;
input s;
output [N-1:0]y;
wire [N-1:0]S;
wire [N-1:0]F1,F2,F3;
assign S={(N){s}};
AND #(.N(N)) DUT1(.A(b),.B(S),.AND(F1));
NOT #(.N(N)) DUT2(.A(S),.NOT(F2));
AND #(.N(N)) DUT3(.A(a),.B(F2),.AND(F3));
OR  #(.N(N)) DUT4(.A(F1),.B(F3),.OR(y));


endmodule