data/full_repos/permissive/423693009/Modules/Data_Register_Module/includes/Data_Register.v
data/verilator_xmls/1e82f84d-7c49-4068-9a19-607a7c6d82dd.xml
module Data_Register(
	input Enable_write,
	input [7:0]Data_write,
	output [7:0]Data
    );
	 

	 reg[7:0] data;
	 assign Data = data;
	 always@(*)
		if(Enable_write)
			data <= Data_write;


endmodule
module Data_Register(
	input Enable_write,
	input [7:0]Data_write,
	output [7:0]Data
    );

	 

	 reg[7:0] data;
	 assign Data = data;
	 always@(*)
		if(Enable_write)
			data <= Data_write;


endmodule