data/full_repos/permissive/499137621/CheckPoint5-main/mux_2_1bit.v
data/verilator_xmls/d641b8a4-7446-48d6-933c-ac670be379dc.xml
module mux_2_1bit(a, b, sel, out);

    input a, b;
    input sel;
    output out;
    
    assign out = sel ? b : a;

endmodule
module mux_2_1bit(a, b, sel, out);


    input a, b;
    input sel;
    output out;
    
    assign out = sel ? b : a;

endmodule