data/full_repos/permissive/529642835/rtl/SupportChips.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/529642835/rtl/SupportChips.v:25: Multiple top level modules\n                                                                             : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                             : ... Top module \'rom2764\'\nmodule rom2764 # ( parameter INIT_FILE = "rom.txt" )\n       ^~~~~~~\n                                                                             : ... Top module \'dram\'\nmodule dram\n       ^~~~\n                                                                             : ... Top module \'sram\'\nmodule sram\n       ^~~~\n                                                                             : ... Top module \'nvram\'\nmodule nvram \n       ^~~~~\n                                                                             : ... Top module \'moram\'\nmodule moram\n       ^~~~~\n                                                                             : ... Top module \'cram82S09\'\nmodule cram82S09\n       ^~~~~~~~~\n                                                                             : ... Top module \'PokeyW\'\nmodule PokeyW\n       ^~~~~~\n                                                                             : ... Top module \'LETA\'\nmodule LETA\n       ^~~~\n%Error: data/full_repos/permissive/529642835/rtl/SupportChips.v:207: Cannot find file containing module: \'pokey\'\npokey core \n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/529642835/rtl,data/full_repos/permissive/529642835/pokey\n             data/full_repos/permissive/529642835/rtl,data/full_repos/permissive/529642835/pokey.v\n             data/full_repos/permissive/529642835/rtl,data/full_repos/permissive/529642835/pokey.sv\n             pokey\n             pokey.v\n             pokey.sv\n             obj_dir/pokey\n             obj_dir/pokey.v\n             obj_dir/pokey.sv\n%Warning-WIDTH: data/full_repos/permissive/529642835/rtl/SupportChips.v:181: Bit extraction of array[32:0] requires 6 bit index, not 5 bits.\n                                                                           : ... In instance cram82S09\n      mem[addr] <= din;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/529642835/rtl/SupportChips.v:183: Bit extraction of array[32:0] requires 6 bit index, not 5 bits.\n                                                                           : ... In instance cram82S09\n      dout <= mem[addr];\n                 ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n'
module nvram 
(
   input clk, we, reset_n,
   input store, recall,
   input [7:0] addr,
   input [7:0] din,
   output [7:0] dout
);

reg [7:0] mem1 [0:255];
reg [7:0] mem2 [0:255];
reg bank, store_d, recall_d, storing;
reg [8:0] counter;

always @(posedge clk or negedge reset_n) 
begin
   if (~reset_n)
   begin
      bank <= #1 0;
      storing <= #1 0;
      counter <= #1 9'b000000000;
   end
   else
   begin
      store_d <= #1 store;
      recall_d <= #1 recall;
      
      if (~recall_d && recall) bank <= #1 ~bank;
      if (~storing & ~store_d && store) storing <= #1 1'b1;
      if (storing) counter <= #1 counter + 9'b000000001;
      if (counter == 9'b111111111) storing <= #1 1'b0;
   end
end




reg [7:0] dout1, dout2;
wire [7:0] a = storing ? counter[8:1] : addr;
assign dout = bank ? dout2 : dout1;
wire we1 = storing ? bank & counter[0] : ~bank & we;
wire [7:0] din1 = storing ? dout2 : din;
wire we2 = storing ? ~bank & counter[0] : bank & we;
wire [7:0] din2 = storing ? dout1 : din;

always @(posedge clk) 
begin
   if (we1) mem1[a] <= din1;
   else dout1 <= mem1[a];
end

always @(posedge clk) 
begin
   if (we2) mem2[a] <= din2;
   else dout2 <= mem2[a];
end

initial begin
   $readmemh("nvram.rom", mem2);
end

endmodule
module nvram 
(
   input clk, we, reset_n,
   input store, recall,
   input [7:0] addr,
   input [7:0] din,
   output [7:0] dout
);


reg [7:0] mem1 [0:255];
reg [7:0] mem2 [0:255];
reg bank, store_d, recall_d, storing;
reg [8:0] counter;

always @(posedge clk or negedge reset_n) 
begin
   if (~reset_n)
   begin
      bank <= #1 0;
      storing <= #1 0;
      counter <= #1 9'b000000000;
   end
   else
   begin
      store_d <= #1 store;
      recall_d <= #1 recall;
      
      if (~recall_d && recall) bank <= #1 ~bank;
      if (~storing & ~store_d && store) storing <= #1 1'b1;
      if (storing) counter <= #1 counter + 9'b000000001;
      if (counter == 9'b111111111) storing <= #1 1'b0;
   end
end




reg [7:0] dout1, dout2;
wire [7:0] a = storing ? counter[8:1] : addr;
assign dout = bank ? dout2 : dout1;
wire we1 = storing ? bank & counter[0] : ~bank & we;
wire [7:0] din1 = storing ? dout2 : din;
wire we2 = storing ? ~bank & counter[0] : bank & we;
wire [7:0] din2 = storing ? dout1 : din;

always @(posedge clk) 
begin
   if (we1) mem1[a] <= din1;
   else dout1 <= mem1[a];
end

always @(posedge clk) 
begin
   if (we2) mem2[a] <= din2;
   else dout2 <= mem2[a];
end

initial begin
   $readmemh("nvram.rom", mem2);
end

endmodule