data/full_repos/permissive/445357518/datapath.v
1: b"%Error: data/full_repos/permissive/445357518/datapath.v:17: Cannot find file containing module: 'regfile'\n  regfile REGFILE(data_in, writenum, write, readnum, clk, data_out);\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/regfile\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/regfile.v\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/regfile.sv\n             regfile\n             regfile.v\n             regfile.sv\n             obj_dir/regfile\n             obj_dir/regfile.v\n             obj_dir/regfile.sv\n%Error: data/full_repos/permissive/445357518/datapath.v:20: Cannot find file containing module: 'vDFF1'\n  vDFF1 #(16)loadA(clk, data_out, loada, aout);\n  ^~~~~\n%Error: data/full_repos/permissive/445357518/datapath.v:22: Cannot find file containing module: 'vDFF1'\n  vDFF1 #(16)loadB(clk, data_out, loadb, in);\n  ^~~~~\n%Error: data/full_repos/permissive/445357518/datapath.v:25: Cannot find file containing module: 'shifter'\n  shifter SHIFTER(in, shift, sout);\n  ^~~~~~~\n%Error: data/full_repos/permissive/445357518/datapath.v:32: Cannot find file containing module: 'ALU'\n  ALU U2(Ain,Bin,ALUop,out,N,V,Z);\n  ^~~\n%Error: data/full_repos/permissive/445357518/datapath.v:34: Cannot find file containing module: 'vDFF1'\n  vDFF1 #(16) C(clk,out,loadc,datapath_out);\n  ^~~~~\n%Error: data/full_repos/permissive/445357518/datapath.v:36: Cannot find file containing module: 'vDFF1'\n  vDFF1 #(1) statusN(clk,N,loads,N_out);\n  ^~~~~\n%Error: data/full_repos/permissive/445357518/datapath.v:38: Cannot find file containing module: 'vDFF1'\n  vDFF1 #(1) statusV(clk,V,loads,V_out);\n  ^~~~~\n%Error: data/full_repos/permissive/445357518/datapath.v:40: Cannot find file containing module: 'vDFF1'\n  vDFF1 #(1) statusZ(clk,Z,loads,Z_out);\n  ^~~~~\n%Error: Exiting due to 9 error(s)\n"
module writeBackMux (a,b,c,d,e,select);
  input [15:0] a, b, c, d;
  input [1:0] select;
  output [15:0] e;
  reg [15:0] e;

 	always @* begin
		case (select)
			2'b00: e = a;
			2'b01: e = b;
			2'b10: e = c;
			2'b11: e = d;

			default: e = e;
		endcase
	end
endmodule
module writeBackMux (a,b,c,d,e,select);

  input [15:0] a, b, c, d;
  input [1:0] select;
  output [15:0] e;
  reg [15:0] e;

 	always @* begin
		case (select)
			2'b00: e = a;
			2'b01: e = b;
			2'b10: e = c;
			2'b11: e = d;

			default: e = e;
		endcase
	end
endmodule