data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v
1: b'%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:1: Cannot find include file: ./global.vh\n`include "./global.vh" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/434840709/USTB_verilog_elevator/src,data/full_repos/permissive/434840709/./global.vh\n             data/full_repos/permissive/434840709/USTB_verilog_elevator/src,data/full_repos/permissive/434840709/./global.vh.v\n             data/full_repos/permissive/434840709/USTB_verilog_elevator/src,data/full_repos/permissive/434840709/./global.vh.sv\n             ./global.vh\n             ./global.vh.v\n             ./global.vh.sv\n             obj_dir/./global.vh\n             obj_dir/./global.vh.v\n             obj_dir/./global.vh.sv\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:12: Define or directive not defined: \'`F_N\'\n    input  [`F_N-1:0] floor_in,           \n            ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:13: Define or directive not defined: \'`F_N\'\n    input  [`F_N-1:0] up_in,              \n            ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:14: Define or directive not defined: \'`F_N\'\n    input  [`F_N-1:0] down_in,            \n            ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:15: Define or directive not defined: \'`F_N\'\n    output [2*`F_N-1:0] demand_state,     \n              ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:20: Define or directive not defined: \'`F_N\'\n    reg [`F_N-1:0] floor = 0, \n         ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:24: Define or directive not defined: \'`F_N\'\n    assign demand_state = {up[`F_N-1:0], down[`F_N-1:0]};\n                              ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:24: Define or directive not defined: \'`F_N\'\n    assign demand_state = {up[`F_N-1:0], down[`F_N-1:0]};\n                                              ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:27: Define or directive not defined: \'`F_N\'\n    wire [`F_N-1:0] floor_add, up_add, down_add;\n          ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:30: Define or directive not defined: \'`F_N\'\n    key_input #(`F_N) ki_up    (clk10hz, {1\'b0, up_in[`F_N-2:0]}, up_add);\n                ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:30: Define or directive not defined: \'`F_N\'\n    key_input #(`F_N) ki_up    (clk10hz, {1\'b0, up_in[`F_N-2:0]}, up_add);\n                                                      ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:31: Define or directive not defined: \'`F_N\'\n    key_input #(`F_N) ki_down  (clk10hz, {down_in[`F_N-1:1], 1\'b0}, down_add);\n                ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:31: Define or directive not defined: \'`F_N\'\n    key_input #(`F_N) ki_down  (clk10hz, {down_in[`F_N-1:1], 1\'b0}, down_add);\n                                                  ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:43: Define or directive not defined: \'`DS_OPEN\'\n               if(door_state == `DS_OPEN) begin\n                                ^~~~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:43: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n               if(door_state == `DS_OPEN) begin\n                                        ^\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:49: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:52: Define or directive not defined: \'`F_N\'\n    wire [3*`F_N-1:0] w_floor, w_up, w_down;\n            ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:58: Define or directive not defined: \'`F_N\'\n    assign w_floor = {{`F_N{1\'b0}}, floor[`F_N-1:0], {`F_N{1\'b0}}},\n                       ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:58: Define or directive not defined: \'`F_N\'\n    assign w_floor = {{`F_N{1\'b0}}, floor[`F_N-1:0], {`F_N{1\'b0}}},\n                                          ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:58: Define or directive not defined: \'`F_N\'\n    assign w_floor = {{`F_N{1\'b0}}, floor[`F_N-1:0], {`F_N{1\'b0}}},\n                                                      ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:59: Define or directive not defined: \'`F_N\'\n           w_up    = {{(`F_N+1){1\'b0}}, up[`F_N-2:0], {`F_N{1\'b0}}},\n                        ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:59: Define or directive not defined: \'`F_N\'\n           w_up    = {{(`F_N+1){1\'b0}}, up[`F_N-2:0], {`F_N{1\'b0}}},\n                                           ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:59: Define or directive not defined: \'`F_N\'\n           w_up    = {{(`F_N+1){1\'b0}}, up[`F_N-2:0], {`F_N{1\'b0}}},\n                                                       ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:60: Define or directive not defined: \'`F_N\'\n           w_down  = {{`F_N{1\'b0}}, down[`F_N-1:1], {(`F_N+1){1\'b0}}};\n                       ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:60: Define or directive not defined: \'`F_N\'\n           w_down  = {{`F_N{1\'b0}}, down[`F_N-1:1], {(`F_N+1){1\'b0}}};\n                                         ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:60: Define or directive not defined: \'`F_N\'\n           w_down  = {{`F_N{1\'b0}}, down[`F_N-1:1], {(`F_N+1){1\'b0}}};\n                                                      ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:61: Define or directive not defined: \'`F_N\'\n    assign w_curr_floor = curr_floor + `F_N;\n                                       ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:61: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    assign w_curr_floor = curr_floor + `F_N;\n                                           ^\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:72: Define or directive not defined: \'`F_N\'\n    assign up_req =                curr_floor != `F_N - 1 &&    \n                                                 ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:73: Define or directive not defined: \'`F_N\'\n                    w_floor[(w_curr_floor + 1) +: `F_N] > 0 ||  \n                                                  ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:73: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n                    w_floor[(w_curr_floor + 1) +: `F_N] > 0 ||  \n                                                      ^\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:74: Define or directive not defined: \'`F_N\'\n                       w_up[(w_curr_floor + 1) +: `F_N] > 0 ||  \n                                                  ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:75: Define or directive not defined: \'`F_N\'\n                     w_down[(w_curr_floor + 1) +: `F_N] > 0;    \n                                                  ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:79: Define or directive not defined: \'`F_N\'\n                    w_floor[(w_curr_floor - 1) -: `F_N] > 0 ||\n                                                  ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:79: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n                    w_floor[(w_curr_floor - 1) -: `F_N] > 0 ||\n                                                      ^\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:80: Define or directive not defined: \'`F_N\'\n                       w_up[(w_curr_floor - 1) -: `F_N] > 0 ||\n                                                  ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:81: Define or directive not defined: \'`F_N\'\n                     w_down[(w_curr_floor - 1) -: `F_N] > 0;\n                                                  ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:84: Define or directive not defined: \'`RS_UP\'\n    assign go_up = (running_state == `RS_UP && up_req) ||                \n                                     ^~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:84: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n    assign go_up = (running_state == `RS_UP && up_req) ||                \n                                            ^~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:85: Define or directive not defined: \'`RS_DOWN\'\n                   (running_state == `RS_DOWN && !down_req && up_req);   \n                                     ^~~~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:88: Define or directive not defined: \'`RS_DOWN\'\n    assign go_down = (running_state == `RS_DOWN && down_req) ||\n                                       ^~~~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:88: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n    assign go_down = (running_state == `RS_DOWN && down_req) ||\n                                                ^~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:89: Define or directive not defined: \'`RS_UP\'\n                     (running_state == `RS_UP  && !up_req && down_req);\n                                       ^~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:94: Define or directive not defined: \'`F_N\'\n                            curr_floor != `F_N-1 &&                                       \n                                          ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:95: Define or directive not defined: \'`RS_UP\'\n                            ((running_state == `RS_UP && up[curr_floor] == 1) ||          \n                                               ^~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:95: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n                            ((running_state == `RS_UP && up[curr_floor] == 1) ||          \n                                                      ^~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/src/request.v:100: Define or directive not defined: \'`RS_DOWN\'\n                            ((running_state == `RS_DOWN && down[curr_floor] == 1) ||\n                                               ^~~~~~~~\n%Error: Exiting due to 47 error(s)\n'
module request(
    input clk380hz,
    input clk10hz,
    input clk1hz,
    input rst,

    input [7:0] curr_floor,
    input [3:0] running_state,
    input [3:0] door_state,

    input  [`F_N-1:0] floor_in,
    input  [`F_N-1:0] up_in,
    input  [`F_N-1:0] down_in,
    output [2*`F_N-1:0] demand_state,
    output [2:0] req
);


    reg [`F_N-1:0] floor = 0,
                      up = 0,
                    down = 0;

    assign demand_state = {up[`F_N-1:0], down[`F_N-1:0]};


    wire [`F_N-1:0] floor_add, up_add, down_add;


    key_input #(`F_N) ki_up    (clk10hz, {1'b0, up_in[`F_N-2:0]}, up_add);
    key_input #(`F_N) ki_down  (clk10hz, {down_in[`F_N-1:1], 1'b0}, down_add);

    always @(posedge clk380hz) begin
         if(rst == 1) {floor, up, down} <= 0;
         else begin

               begin
                    floor <= floor | floor_in;
                    up    <= up    | up_add;
                    down  <= down  | down_add;
               end

               if(door_state == `DS_OPEN) begin
                    floor[curr_floor] <= 0;
                    up   [curr_floor] <= 0;
                    down [curr_floor] <= 0;
               end  
         end
    end
  

    wire [3*`F_N-1:0] w_floor, w_up, w_down;
    wire [7:0] w_curr_floor;
 



    assign w_floor = {{`F_N{1'b0}}, floor[`F_N-1:0], {`F_N{1'b0}}},
           w_up    = {{(`F_N+1){1'b0}}, up[`F_N-2:0], {`F_N{1'b0}}},
           w_down  = {{`F_N{1'b0}}, down[`F_N-1:1], {(`F_N+1){1'b0}}};
    assign w_curr_floor = curr_floor + `F_N;
    

    wire up_req,
         down_req,
         go_up,
         go_down,
         open_door;



    assign up_req =                curr_floor != `F_N - 1 &&
                    w_floor[(w_curr_floor + 1) +: `F_N] > 0 ||
                       w_up[(w_curr_floor + 1) +: `F_N] > 0 ||
                     w_down[(w_curr_floor + 1) +: `F_N] > 0;


    assign down_req =                     curr_floor != 0 &&
                    w_floor[(w_curr_floor - 1) -: `F_N] > 0 ||
                       w_up[(w_curr_floor - 1) -: `F_N] > 0 ||
                     w_down[(w_curr_floor - 1) -: `F_N] > 0;


    assign go_up = (running_state == `RS_UP && up_req) ||
                   (running_state == `RS_DOWN && !down_req && up_req);


    assign go_down = (running_state == `RS_DOWN && down_req) ||
                     (running_state == `RS_UP  && !up_req && down_req);


    assign open_door = floor[curr_floor] == 1 ||
                       (
                            curr_floor != `F_N-1 &&
                            ((running_state == `RS_UP && up[curr_floor] == 1) ||
                            (!up_req && (down[curr_floor] == 1 || up[curr_floor] == 1)))
                       ) ||
                       (
                            curr_floor != 0 &&
                            ((running_state == `RS_DOWN && down[curr_floor] == 1) ||
                            (!down_req && (down[curr_floor] == 1 || up[curr_floor] == 1)))
                       );

     assign req = rst == 1 ? 0 : {go_up, go_down, open_door};

endmodule
module request(
    input clk380hz,
    input clk10hz,
    input clk1hz,
    input rst,

    input [7:0] curr_floor,
    input [3:0] running_state,
    input [3:0] door_state,

    input  [`F_N-1:0] floor_in,
    input  [`F_N-1:0] up_in,
    input  [`F_N-1:0] down_in,
    output [2*`F_N-1:0] demand_state,
    output [2:0] req
);



    reg [`F_N-1:0] floor = 0,
                      up = 0,
                    down = 0;

    assign demand_state = {up[`F_N-1:0], down[`F_N-1:0]};


    wire [`F_N-1:0] floor_add, up_add, down_add;


    key_input #(`F_N) ki_up    (clk10hz, {1'b0, up_in[`F_N-2:0]}, up_add);
    key_input #(`F_N) ki_down  (clk10hz, {down_in[`F_N-1:1], 1'b0}, down_add);

    always @(posedge clk380hz) begin
         if(rst == 1) {floor, up, down} <= 0;
         else begin

               begin
                    floor <= floor | floor_in;
                    up    <= up    | up_add;
                    down  <= down  | down_add;
               end

               if(door_state == `DS_OPEN) begin
                    floor[curr_floor] <= 0;
                    up   [curr_floor] <= 0;
                    down [curr_floor] <= 0;
               end  
         end
    end
  

    wire [3*`F_N-1:0] w_floor, w_up, w_down;
    wire [7:0] w_curr_floor;
 



    assign w_floor = {{`F_N{1'b0}}, floor[`F_N-1:0], {`F_N{1'b0}}},
           w_up    = {{(`F_N+1){1'b0}}, up[`F_N-2:0], {`F_N{1'b0}}},
           w_down  = {{`F_N{1'b0}}, down[`F_N-1:1], {(`F_N+1){1'b0}}};
    assign w_curr_floor = curr_floor + `F_N;
    

    wire up_req,
         down_req,
         go_up,
         go_down,
         open_door;



    assign up_req =                curr_floor != `F_N - 1 &&
                    w_floor[(w_curr_floor + 1) +: `F_N] > 0 ||
                       w_up[(w_curr_floor + 1) +: `F_N] > 0 ||
                     w_down[(w_curr_floor + 1) +: `F_N] > 0;


    assign down_req =                     curr_floor != 0 &&
                    w_floor[(w_curr_floor - 1) -: `F_N] > 0 ||
                       w_up[(w_curr_floor - 1) -: `F_N] > 0 ||
                     w_down[(w_curr_floor - 1) -: `F_N] > 0;


    assign go_up = (running_state == `RS_UP && up_req) ||
                   (running_state == `RS_DOWN && !down_req && up_req);


    assign go_down = (running_state == `RS_DOWN && down_req) ||
                     (running_state == `RS_UP  && !up_req && down_req);


    assign open_door = floor[curr_floor] == 1 ||
                       (
                            curr_floor != `F_N-1 &&
                            ((running_state == `RS_UP && up[curr_floor] == 1) ||
                            (!up_req && (down[curr_floor] == 1 || up[curr_floor] == 1)))
                       ) ||
                       (
                            curr_floor != 0 &&
                            ((running_state == `RS_DOWN && down[curr_floor] == 1) ||
                            (!down_req && (down[curr_floor] == 1 || up[curr_floor] == 1)))
                       );

     assign req = rst == 1 ? 0 : {go_up, go_down, open_door};

endmodule