data/full_repos/permissive/441359809/src/yosys/tests/simple/memory.v
1: b"%Error: data/full_repos/permissive/441359809/src/yosys/tests/simple/memory.v:39: syntax error, unexpected ',', expecting IDENTIFIER or do or final\nmodule memtest02(clk, setA, setB, addr, bit, y1, y2, y3, y4);\n                                           ^\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/simple/memory.v:45: syntax error, unexpected output\noutput y3, y4;\n^~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/simple/memory.v:52: syntax error, unexpected always\nalways @(posedge clk) begin\n^~~~~~\n%Error: Exiting due to 3 error(s)\n"
module memtest05(clk, addr, wdata, rdata, wen);

input clk;
input [1:0] addr;
input [7:0] wdata;
output reg [7:0] rdata;
input [3:0] wen;

reg [7:0] mem [0:3];

integer i;
always @(posedge clk) begin
	for (i = 0; i < 4; i = i+1)
		if (wen[i]) mem[addr][i*2 +: 2] <= wdata[i*2 +: 2];
	rdata <= mem[addr];
end

endmodule
module memtest05(clk, addr, wdata, rdata, wen);


input clk;
input [1:0] addr;
input [7:0] wdata;
output reg [7:0] rdata;
input [3:0] wen;

reg [7:0] mem [0:3];

integer i;
always @(posedge clk) begin
	for (i = 0; i < 4; i = i+1)
		if (wen[i]) mem[addr][i*2 +: 2] <= wdata[i*2 +: 2];
	rdata <= mem[addr];
end

endmodule