data/full_repos/permissive/41334298/tests/elementary/t4.v
data/verilator_xmls/d21abeff-066f-4252-8031-b7b452a1924c.xml
module top (a, b, c, y);
input a, b, c;
output y;

wire k, l, m;

or (k, a, b, c);
and (l, a, b, c);
xor (m, a, b, c);

and (y, k, l, m);

endmodule
module top (a, b, c, y);

input a, b, c;
output y;

wire k, l, m;

or (k, a, b, c);
and (l, a, b, c);
xor (m, a, b, c);

and (y, k, l, m);

endmodule