data/full_repos/permissive/443556793/lab_4/rtl/alu.v
1: b'%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:22: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/443556793/lab_4/rtl,data/full_repos/permissive/443556793/defines.vh\n             data/full_repos/permissive/443556793/lab_4/rtl,data/full_repos/permissive/443556793/defines.vh.v\n             data/full_repos/permissive/443556793/lab_4/rtl,data/full_repos/permissive/443556793/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:51: Define or directive not defined: \'`EXE_ADD_OP\'\n        `EXE_ADD_OP:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:51: syntax error, unexpected \':\', expecting endcase\n        `EXE_ADD_OP:\n                   ^\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:53: Define or directive not defined: \'`EXE_ADDU_OP\'\n        `EXE_ADDU_OP:\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:55: Define or directive not defined: \'`EXE_SUB_OP\'\n        `EXE_SUB_OP:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:57: Define or directive not defined: \'`EXE_SUBU_OP\'\n        `EXE_SUBU_OP:\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:59: Define or directive not defined: \'`EXE_AND_OP\'\n        `EXE_AND_OP:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:61: Define or directive not defined: \'`EXE_OR_OP\'\n        `EXE_OR_OP:\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:63: Define or directive not defined: \'`EXE_XOR_OP\'\n        `EXE_XOR_OP:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:65: Define or directive not defined: \'`EXE_NOR_OP\'\n        `EXE_NOR_OP:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:67: Define or directive not defined: \'`EXE_SLT_OP\'\n        `EXE_SLT_OP:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:69: Define or directive not defined: \'`EXE_SLTU_OP\'\n        `EXE_SLTU_OP:\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:71: Define or directive not defined: \'`EXE_LUI_OP\'\n        `EXE_LUI_OP:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:73: Define or directive not defined: \'`EXE_SLL_OP\'\n        `EXE_SLL_OP:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:75: Define or directive not defined: \'`EXE_SRL_OP\'\n        `EXE_SRL_OP:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:77: Define or directive not defined: \'`EXE_SRA_OP\'\n        `EXE_SRA_OP:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:79: Define or directive not defined: \'`EXE_SLLV_OP\'\n        `EXE_SLLV_OP:\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:81: Define or directive not defined: \'`EXE_SRLV_OP\'\n        `EXE_SRLV_OP:\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:83: Define or directive not defined: \'`EXE_SRAV_OP\'\n        `EXE_SRAV_OP:\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:95: Define or directive not defined: \'`EXE_ADD_OP\'\n        `EXE_ADD_OP:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:97: Define or directive not defined: \'`EXE_SUB_OP\'\n        `EXE_SUB_OP:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:105: Define or directive not defined: \'`EXE_MULT_OP\'\nassign mul_sign = (op == `EXE_MULT_OP);\n                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:105: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign mul_sign = (op == `EXE_MULT_OP);\n                                     ^\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:107: Define or directive not defined: \'`EXE_MULT_OP\'\nassign mul_valid = (op == `EXE_MULT_OP || op == `EXE_MULTU_OP);\n                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:107: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\nassign mul_valid = (op == `EXE_MULT_OP || op == `EXE_MULTU_OP);\n                                       ^~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:107: Define or directive not defined: \'`EXE_MULTU_OP\'\nassign mul_valid = (op == `EXE_MULT_OP || op == `EXE_MULTU_OP);\n                                                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:119: Define or directive not defined: \'`EXE_DIV_OP\'\nassign div_sign  = (op == `EXE_DIV_OP);\n                          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:119: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign div_sign  = (op == `EXE_DIV_OP);\n                                     ^\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:120: Define or directive not defined: \'`EXE_DIV_OP\'\nassign div_valid = (op == `EXE_DIV_OP || op == `EXE_DIVU_OP);\n                          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:120: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\nassign div_valid = (op == `EXE_DIV_OP || op == `EXE_DIVU_OP);\n                                      ^~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:120: Define or directive not defined: \'`EXE_DIVU_OP\'\nassign div_valid = (op == `EXE_DIV_OP || op == `EXE_DIVU_OP);\n                                               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:130: Define or directive not defined: \'`EXE_MULT_OP\'\n        `EXE_MULT_OP,`EXE_MULTU_OP:\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:130: syntax error, unexpected \',\', expecting endcase\n        `EXE_MULT_OP,`EXE_MULTU_OP:\n                    ^\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:130: Define or directive not defined: \'`EXE_MULTU_OP\'\n        `EXE_MULT_OP,`EXE_MULTU_OP:\n                     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:132: Define or directive not defined: \'`EXE_DIV_OP\'\n        `EXE_DIV_OP,`EXE_DIVU_OP:\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/443556793/lab_4/rtl/alu.v:132: Define or directive not defined: \'`EXE_DIVU_OP\'\n        `EXE_DIV_OP,`EXE_DIVU_OP:\n                    ^~~~~~~~~~~~\n%Error: Cannot continue\n'
module alu(
           input wire clk,rst,
           input wire[31:0] a,b,
           input wire[4:0] sa,
           input wire[7:0] op,
           input wire flush_endE,

           output wire[31:0] ans,
           output reg overflow,
           output reg[63:0]hilo_out,
           output wire zero,
           output wire div_stallE
       );

wire[31:0] addr,subr,nb;
reg[31:0] y;
wire[63:0] tem1,tem2;
reg[63:0] hilo_out_mul;
wire[63:0] hilo_out_div;
reg [63:0] hilo_out_move;
assign nb = ~b;
assign subr = a + nb + 1;
assign addr =a + b;
always @(*)
begin
    case (op)
        8'b11111111:
            y <= a[31] ? (~a + 1) : a;
        `EXE_ADD_OP:
            y <= addr;
        `EXE_ADDU_OP:
            y <= addr;
        `EXE_SUB_OP:
            y <= subr;
        `EXE_SUBU_OP:
            y <= subr;
        `EXE_AND_OP:
            y <= a & b;
        `EXE_OR_OP:
            y <= a | b;
        `EXE_XOR_OP:
            y <= a ^ b;
        `EXE_NOR_OP:
            y <= ~(a | b);
        `EXE_SLT_OP:
            y <= ((a[31] && !b[31])||(subr[31] && !(!a[31] && b[31])));
        `EXE_SLTU_OP:
            y <= (a<b);
        `EXE_LUI_OP:
            y <= {b[15:0],16'h0000};
        `EXE_SLL_OP:
            y <= (b << sa);
        `EXE_SRL_OP:
            y <= (b >> sa);
        `EXE_SRA_OP:
            y <= ({32{b[31]}} << (6'd32-{1'b0,sa})) | b >> sa;
        `EXE_SLLV_OP:
            y <= (b << a[4:0]);
        `EXE_SRLV_OP:
            y <= (b >> a[4:0]);
        `EXE_SRAV_OP:
            y <= ({32{b[31]}} << (6'd32-{1'b0,a[4:0]})) | b >> a[4:0];
        default:
            y <= 32'b0;
    endcase
end

assign zero = (y == 32'b0);

always @(*)
begin
    case (op)
        `EXE_ADD_OP:
            overflow <= a[31] & b[31] & ~addr[31] | ~a[31] & ~b[31] & addr[31];
        `EXE_SUB_OP:
            overflow <= ~a[31] & b[31] & subr[31] | a[31] & ~b[31] & ~subr[31];
        default :
            overflow <= 1'b0;
    endcase
end
assign ans = overflow ? 0 : y;
wire mul_sign;
assign mul_sign = (op == `EXE_MULT_OP);
wire mul_valid;
assign mul_valid = (op == `EXE_MULT_OP || op == `EXE_MULTU_OP);
mult_gen_0 mul1(a,b,tem1);
mult_gen_1 mul2(a,b,tem2);
always @(*)
begin
    if(mul_sign)
        hilo_out_mul <= tem1;
    else
        hilo_out_mul <= tem2;
end
wire div_sign;
wire div_valid;
assign div_sign  = (op == `EXE_DIV_OP);
assign div_valid = (op == `EXE_DIV_OP || op == `EXE_DIVU_OP);
wire div_res_valid;
wire div_res_cancle;
assign div_res_cancle = 1'b0;
assign div_stallE = div_valid & ~div_res_valid;
div div(clk,(rst | flush_endE),a,b,div_sign,div_valid,div_res_cancle,div_res_valid,hilo_out_div);

always@(*)
begin
    case (op)
        `EXE_MULT_OP,`EXE_MULTU_OP:
            hilo_out <= hilo_out_mul;
        `EXE_DIV_OP,`EXE_DIVU_OP:
            hilo_out <= hilo_out_div;
    endcase
end

endmodule
module alu(
           input wire clk,rst,
           input wire[31:0] a,b,
           input wire[4:0] sa,
           input wire[7:0] op,
           input wire flush_endE,

           output wire[31:0] ans,
           output reg overflow,
           output reg[63:0]hilo_out,
           output wire zero,
           output wire div_stallE
       );


wire[31:0] addr,subr,nb;
reg[31:0] y;
wire[63:0] tem1,tem2;
reg[63:0] hilo_out_mul;
wire[63:0] hilo_out_div;
reg [63:0] hilo_out_move;
assign nb = ~b;
assign subr = a + nb + 1;
assign addr =a + b;
always @(*)
begin
    case (op)
        8'b11111111:
            y <= a[31] ? (~a + 1) : a;
        `EXE_ADD_OP:
            y <= addr;
        `EXE_ADDU_OP:
            y <= addr;
        `EXE_SUB_OP:
            y <= subr;
        `EXE_SUBU_OP:
            y <= subr;
        `EXE_AND_OP:
            y <= a & b;
        `EXE_OR_OP:
            y <= a | b;
        `EXE_XOR_OP:
            y <= a ^ b;
        `EXE_NOR_OP:
            y <= ~(a | b);
        `EXE_SLT_OP:
            y <= ((a[31] && !b[31])||(subr[31] && !(!a[31] && b[31])));
        `EXE_SLTU_OP:
            y <= (a<b);
        `EXE_LUI_OP:
            y <= {b[15:0],16'h0000};
        `EXE_SLL_OP:
            y <= (b << sa);
        `EXE_SRL_OP:
            y <= (b >> sa);
        `EXE_SRA_OP:
            y <= ({32{b[31]}} << (6'd32-{1'b0,sa})) | b >> sa;
        `EXE_SLLV_OP:
            y <= (b << a[4:0]);
        `EXE_SRLV_OP:
            y <= (b >> a[4:0]);
        `EXE_SRAV_OP:
            y <= ({32{b[31]}} << (6'd32-{1'b0,a[4:0]})) | b >> a[4:0];
        default:
            y <= 32'b0;
    endcase
end

assign zero = (y == 32'b0);

always @(*)
begin
    case (op)
        `EXE_ADD_OP:
            overflow <= a[31] & b[31] & ~addr[31] | ~a[31] & ~b[31] & addr[31];
        `EXE_SUB_OP:
            overflow <= ~a[31] & b[31] & subr[31] | a[31] & ~b[31] & ~subr[31];
        default :
            overflow <= 1'b0;
    endcase
end
assign ans = overflow ? 0 : y;
wire mul_sign;
assign mul_sign = (op == `EXE_MULT_OP);
wire mul_valid;
assign mul_valid = (op == `EXE_MULT_OP || op == `EXE_MULTU_OP);
mult_gen_0 mul1(a,b,tem1);
mult_gen_1 mul2(a,b,tem2);
always @(*)
begin
    if(mul_sign)
        hilo_out_mul <= tem1;
    else
        hilo_out_mul <= tem2;
end
wire div_sign;
wire div_valid;
assign div_sign  = (op == `EXE_DIV_OP);
assign div_valid = (op == `EXE_DIV_OP || op == `EXE_DIVU_OP);
wire div_res_valid;
wire div_res_cancle;
assign div_res_cancle = 1'b0;
assign div_stallE = div_valid & ~div_res_valid;
div div(clk,(rst | flush_endE),a,b,div_sign,div_valid,div_res_cancle,div_res_valid,hilo_out_div);

always@(*)
begin
    case (op)
        `EXE_MULT_OP,`EXE_MULTU_OP:
            hilo_out <= hilo_out_mul;
        `EXE_DIV_OP,`EXE_DIVU_OP:
            hilo_out <= hilo_out_div;
    endcase
end

endmodule