data/full_repos/permissive/511127056/prj2-simple_CPU/shifter.v
data/verilator_xmls/791897d2-ea63-414e-8eba-a9631d03bd92.xml
module shifter (
	input  [`DATA_WIDTH - 1:0] A,
	input  [              4:0] B,
	input  [              1:0] Shiftop,
	output [`DATA_WIDTH - 1:0] Result
);

	
	assign Result =	{(`DATA_WIDTH){~Shiftop[1] & ~Shiftop[0]}} & (A<<B)
				  |	{(`DATA_WIDTH){ Shiftop[1] & ~Shiftop[0]}} & (A>>B)
				  |	{(`DATA_WIDTH){ Shiftop[1] &  Shiftop[0]}} & (
					  (A>>B) | ~((~32'b0)>>B) & {(32){A[31]}}
				  );
endmodule
module shifter (
	input  [`DATA_WIDTH - 1:0] A,
	input  [              4:0] B,
	input  [              1:0] Shiftop,
	output [`DATA_WIDTH - 1:0] Result
);


	
	assign Result =	{(`DATA_WIDTH){~Shiftop[1] & ~Shiftop[0]}} & (A<<B)
				  |	{(`DATA_WIDTH){ Shiftop[1] & ~Shiftop[0]}} & (A>>B)
				  |	{(`DATA_WIDTH){ Shiftop[1] &  Shiftop[0]}} & (
					  (A>>B) | ~((~32'b0)>>B) & {(32){A[31]}}
				  );
endmodule