data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/PS2Controller.v
1: b"%Error: data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/PS2Controller.v:57: Cannot find file containing module: 'PS2Receiver'\n  PS2Receiver ps2rec (\n  ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new,data/full_repos/permissive/42815087/PS2Receiver\n             data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new,data/full_repos/permissive/42815087/PS2Receiver.v\n             data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new,data/full_repos/permissive/42815087/PS2Receiver.sv\n             PS2Receiver\n             PS2Receiver.v\n             PS2Receiver.sv\n             obj_dir/PS2Receiver\n             obj_dir/PS2Receiver.v\n             obj_dir/PS2Receiver.sv\n%Error: Exiting due to 1 error(s)\n"
module PS2Controller(
    input ps2CtrlClk,
    input ps2clk,
    input ps2data,
    output reg [15:0] keycode,
    output writeEn,
    output [15:0] debugOut
  );
  









  
  assign writeEn = 1'b1;
  
  wire [15:0] wKeycode;
  assign debugOut[15:0] = keycode[15:0];
  
  wire flag;
  
  reg intrWrite;
  reg [7:0] data;
  reg clk50MHz;
  reg start = 0;
  reg [2:0] bcount = 0;
  reg cn = 0;
  

  PS2Receiver ps2rec (
    .clk(clk50MHz),
    .kclk(ps2clk),
    .kdata(ps2data),
    .keycode(wKeycode),
    .oflag(flag)
  );
  

  always @ (posedge ps2CtrlClk) begin
    clk50MHz <= ~clk50MHz;
  end
  
  always @ (wKeycode or keycode)
    if (wKeycode[7:0] == 8'hf0) begin
      cn <= 1'b0;
      bcount <= 3'd0;
    end else if (wKeycode[15:8] == 8'hf0) begin
      cn <= wKeycode != keycode;
      bcount <= 3'd5;
    end else begin
      cn <= wKeycode[7:0] != keycode[7:0] || keycode[15:8] == 8'hf0;
      bcount <= 3'd2;
    end
    
  always @ (posedge ps2CtrlClk) begin
    if (flag == 1'b1 && cn == 1'b1) begin
      start <= 1'b1;
      keycode <= wKeycode;
    end else begin
      start <= 1'b0;
    end
  end
    
endmodule
module PS2Controller(
    input ps2CtrlClk,
    input ps2clk,
    input ps2data,
    output reg [15:0] keycode,
    output writeEn,
    output [15:0] debugOut
  );

  









  
  assign writeEn = 1'b1;
  
  wire [15:0] wKeycode;
  assign debugOut[15:0] = keycode[15:0];
  
  wire flag;
  
  reg intrWrite;
  reg [7:0] data;
  reg clk50MHz;
  reg start = 0;
  reg [2:0] bcount = 0;
  reg cn = 0;
  

  PS2Receiver ps2rec (
    .clk(clk50MHz),
    .kclk(ps2clk),
    .kdata(ps2data),
    .keycode(wKeycode),
    .oflag(flag)
  );
  

  always @ (posedge ps2CtrlClk) begin
    clk50MHz <= ~clk50MHz;
  end
  
  always @ (wKeycode or keycode)
    if (wKeycode[7:0] == 8'hf0) begin
      cn <= 1'b0;
      bcount <= 3'd0;
    end else if (wKeycode[15:8] == 8'hf0) begin
      cn <= wKeycode != keycode;
      bcount <= 3'd5;
    end else begin
      cn <= wKeycode[7:0] != keycode[7:0] || keycode[15:8] == 8'hf0;
      bcount <= 3'd2;
    end
    
  always @ (posedge ps2CtrlClk) begin
    if (flag == 1'b1 && cn == 1'b1) begin
      start <= 1'b1;
      keycode <= wKeycode;
    end else begin
      start <= 1'b0;
    end
  end
    
endmodule