data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/montinv.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/montinv.v:53: Cannot find file containing module: 'montinvp1'\nmontinvp1   #(WIDTH, CWID) phase1\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl,data/full_repos/permissive/530013823/montinvp1\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl,data/full_repos/permissive/530013823/montinvp1.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl,data/full_repos/permissive/530013823/montinvp1.sv\n             montinvp1\n             montinvp1.v\n             montinvp1.sv\n             obj_dir/montinvp1\n             obj_dir/montinvp1.v\n             obj_dir/montinvp1.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/montinv.v:65: Cannot find file containing module: 'montinvp2'\nmontinvp2   #(WIDTH, CWID) phase2\n^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module montinv
    (
     clk,
     rst,
     din,
     mod,
     en,
     inv,
     vld
     );




parameter WIDTH = 256;
parameter CWID  = 10;




input     clk;
input     rst;
input [WIDTH-1:0] din;
input [WIDTH-1:0] mod;
input             en;

output [WIDTH-1:0] inv;
output             vld;







wire [WIDTH-1:0]   ainv;
wire [CWID-1:0]    exp;
wire               p1vld;

montinvp1   #(WIDTH, CWID) phase1
    (
     .clk(clk),
     .rst(rst),
     .din(din),
     .mod(mod),
     .en(en),
     .ainv(ainv),
     .exp(exp),
     .vld(p1vld)
     );

montinvp2   #(WIDTH, CWID) phase2
    (
     .clk(clk),
     .rst(rst),
     .ainv(ainv),
     .mod(mod),
     .exp(exp),
     .en(p1vld),
     .inv(inv),
     .vld(vld)
     );

endmodule
module montinv
    (
     clk,
     rst,
     din,
     mod,
     en,
     inv,
     vld
     );





parameter WIDTH = 256;
parameter CWID  = 10;




input     clk;
input     rst;
input [WIDTH-1:0] din;
input [WIDTH-1:0] mod;
input             en;

output [WIDTH-1:0] inv;
output             vld;







wire [WIDTH-1:0]   ainv;
wire [CWID-1:0]    exp;
wire               p1vld;

montinvp1   #(WIDTH, CWID) phase1
    (
     .clk(clk),
     .rst(rst),
     .din(din),
     .mod(mod),
     .en(en),
     .ainv(ainv),
     .exp(exp),
     .vld(p1vld)
     );

montinvp2   #(WIDTH, CWID) phase2
    (
     .clk(clk),
     .rst(rst),
     .ainv(ainv),
     .mod(mod),
     .exp(exp),
     .en(p1vld),
     .inv(inv),
     .vld(vld)
     );

endmodule