data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/multiplier.v
1: b'%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/multiplier.v:17: syntax error, unexpected bit, expecting IDENTIFIER or \'=\' or do or final\n    reg[7:0] bit = 0;\n             ^~~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/multiplier.v:22: syntax error, unexpected ==, expecting "\'{"\n    assign done = enabled ? (~last_cycle_enabled ? 0 : (bit == (bits+1)) || !multiplier || !multiplicand_intermediate) : 1;\n                                                            ^~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/multiplier.v:31: syntax error, unexpected <=, expecting "\'{"\n                bit <= 0;\n                    ^~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/multiplier.v:35: syntax error, unexpected \']\', expecting "\'{"\n                if (multiplier[bit] == 1) begin\n                                  ^\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/multiplier.v:37: syntax error, unexpected \']\', expecting "\'{"\n                    multiplier[bit] <= 0;\n                                  ^\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/multiplier.v:41: syntax error, unexpected <=, expecting "\'{"\n                bit <= bit + 1;\n                    ^~\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sources_1/new/multiplier.v:44: syntax error, unexpected end\n    end\n    ^~~\n%Error: Cannot continue\n'
module multiplier#(parameter bits=15)(
    input clk,
    input enabled,
    input [bits:0] a, 
    input [bits:0] b, 
    output reg[bits*2+1:0] result = 0,
    output done
);

    reg last_cycle_enabled = 0;
    
    reg[bits:0] multiplier = 0;
    reg[bits*2+1:0] multiplicand_intermediate;
    reg[7:0] bit = 0;
    

    assign done = enabled ? (~last_cycle_enabled ? 0 : (bit == (bits+1)) || !multiplier || !multiplicand_intermediate) : 1;

    always@(posedge clk) begin
        last_cycle_enabled <= enabled;
            
        if (enabled) begin
            if (~last_cycle_enabled) begin
                multiplicand_intermediate <= a;
                multiplier <= b;
                bit <= 0;
                result <= 0;
                
            end else if (~done) begin
                if (multiplier[bit] == 1) begin
                    result <= result + multiplicand_intermediate;
                    multiplier[bit] <= 0;
                end
                
                multiplicand_intermediate <= multiplicand_intermediate << 1;
                bit <= bit + 1;
            end
        end    
    end
endmodule
module multiplier#(parameter bits=15)(
    input clk,
    input enabled,
    input [bits:0] a, 
    input [bits:0] b, 
    output reg[bits*2+1:0] result = 0,
    output done
);


    reg last_cycle_enabled = 0;
    
    reg[bits:0] multiplier = 0;
    reg[bits*2+1:0] multiplicand_intermediate;
    reg[7:0] bit = 0;
    

    assign done = enabled ? (~last_cycle_enabled ? 0 : (bit == (bits+1)) || !multiplier || !multiplicand_intermediate) : 1;

    always@(posedge clk) begin
        last_cycle_enabled <= enabled;
            
        if (enabled) begin
            if (~last_cycle_enabled) begin
                multiplicand_intermediate <= a;
                multiplier <= b;
                bit <= 0;
                result <= 0;
                
            end else if (~done) begin
                if (multiplier[bit] == 1) begin
                    result <= result + multiplicand_intermediate;
                    multiplier[bit] <= 0;
                end
                
                multiplicand_intermediate <= multiplicand_intermediate << 1;
                bit <= bit + 1;
            end
        end    
    end
endmodule