data/full_repos/permissive/441359809/src/yosys/tests/sva/basic03.sv
1: b"%Error: data/full_repos/permissive/441359809/src/yosys/tests/sva/basic03.sv:7: syntax error, unexpected |=>, expecting ')'\n check_selA: assert property ( @(posedge clk) selA |=> Q == $past(QA) );\n                                                   ^~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/sva/basic03.sv:8: syntax error, unexpected |=>, expecting ')'\n check_selB: assert property ( @(posedge clk) selB |=> Q == $past(QB) );\n                                                   ^~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/sva/basic03.sv:10: syntax error, unexpected property, expecting '#' or final\n assume_not_11: assume property ( @(posedge clk) !(selA & selB) );\n                       ^~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module top (input logic clk, input logic selA, selB, QA, QB, output logic Q);
	always @(posedge clk) begin
		if (selA) Q <= QA;
		if (selB) Q <= QB;
	end

	check_selA: assert property ( @(posedge clk) selA |=> Q == $past(QA) );
	check_selB: assert property ( @(posedge clk) selB |=> Q == $past(QB) );
`ifndef FAIL
	assume_not_11: assume property ( @(posedge clk) !(selA & selB) );
`endif
endmodule
module top (input logic clk, input logic selA, selB, QA, QB, output logic Q);

	always @(posedge clk) begin
		if (selA) Q <= QA;
		if (selB) Q <= QB;
	end

	check_selA: assert property ( @(posedge clk) selA |=> Q == $past(QA) );
	check_selB: assert property ( @(posedge clk) selB |=> Q == $past(QB) );
`ifndef FAIL
	assume_not_11: assume property ( @(posedge clk) !(selA & selB) );
`endif
endmodule