data/full_repos/permissive/449370139/verilog_code/uart_transimitter.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/449370139/verilog_code/uart_transimitter.v:71: Signal definition not found, creating implicitly: \'clkw\'\n                                                                                           : ... Suggested alternative: \'clk\'\nassign clkw = cnt[3];\n       ^~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module uart_transmitter (
    input clk,
    input clrn,
    input wrn,
    input [7:0] d_in,
    input [3:0] cnt,
    output reg txd,
    output reg t_empty
);

parameter bits=4'b1010;

reg [3:0] no_bits;
reg [7:0] t_buffer;
reg sending;
reg [7:0] d_buffer;
reg load_t_buffer;




always @(posedge clk or negedge clrn or negedge wrn) begin
    if(clrn == 0)begin
        sending <= 1'b0;
        t_empty <= 1'b1;
        load_t_buffer <= 1'b0;
    end
    else begin
        if(!wrn)begin
            d_buffer <= d_in;
            t_empty <= 1'b0;
            load_t_buffer <= 1'b1;
        end
        else begin
            if(!sending)begin
                if(load_t_buffer)begin
                    sending <= 1'b1;
                    t_buffer <= d_buffer;
                    t_empty <= 1'b1;
                    load_t_buffer <= 1'b0;
                end
            end
            else begin
                if(no_bits == bits)
                sending <= 1'b0;
            end
        end
    end
end
assign clkw = cnt[3];




always @(posedge clkw or negedge sending) begin
    if(!sending)begin
        no_bits<=4'b0000;
        txd <= 1'b1;
    end
    else begin
        case (no_bits)
             0:txd <= 1'b0;
             1:txd <= t_buffer[0];
             2:txd <= t_buffer[1];
             3:txd <= t_buffer[2];
             4:txd <= t_buffer[3];
             5:txd <= t_buffer[4];
             6:txd <= t_buffer[5];
             7:txd <= t_buffer[6];
             8:txd <= t_buffer[7];

             default: txd <= 1'b0;
        endcase
        no_bits <= no_bits+4'b0001;
    end
end

endmodule
module uart_transmitter (
    input clk,
    input clrn,
    input wrn,
    input [7:0] d_in,
    input [3:0] cnt,
    output reg txd,
    output reg t_empty
);


parameter bits=4'b1010;

reg [3:0] no_bits;
reg [7:0] t_buffer;
reg sending;
reg [7:0] d_buffer;
reg load_t_buffer;




always @(posedge clk or negedge clrn or negedge wrn) begin
    if(clrn == 0)begin
        sending <= 1'b0;
        t_empty <= 1'b1;
        load_t_buffer <= 1'b0;
    end
    else begin
        if(!wrn)begin
            d_buffer <= d_in;
            t_empty <= 1'b0;
            load_t_buffer <= 1'b1;
        end
        else begin
            if(!sending)begin
                if(load_t_buffer)begin
                    sending <= 1'b1;
                    t_buffer <= d_buffer;
                    t_empty <= 1'b1;
                    load_t_buffer <= 1'b0;
                end
            end
            else begin
                if(no_bits == bits)
                sending <= 1'b0;
            end
        end
    end
end
assign clkw = cnt[3];




always @(posedge clkw or negedge sending) begin
    if(!sending)begin
        no_bits<=4'b0000;
        txd <= 1'b1;
    end
    else begin
        case (no_bits)
             0:txd <= 1'b0;
             1:txd <= t_buffer[0];
             2:txd <= t_buffer[1];
             3:txd <= t_buffer[2];
             4:txd <= t_buffer[3];
             5:txd <= t_buffer[4];
             6:txd <= t_buffer[5];
             7:txd <= t_buffer[6];
             8:txd <= t_buffer[7];

             default: txd <= 1'b0;
        endcase
        no_bits <= no_bits+4'b0001;
    end
end

endmodule