data/full_repos/permissive/479923049/top.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/479923049/top.v:37: Signal definition not found, creating implicitly: \'tri_state_enable\'\n                                                                : ... Suggested alternative: \'tristate_enable\'\n  assign tri_state_enable = (2\'d1 == mem_cmd) & (1\'b0 == mem_addr[8]);    \n         ^~~~~~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/479923049/top.v:41: Signal definition not found, creating implicitly: \'tri_state_switch_enable\'\n                                                                : ... Suggested alternative: \'tri_state_enable\'\n  assign tri_state_switch_enable = ((mem_addr == 9\'h140) && (mem_cmd == 2\'d1));\n         ^~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/479923049/top.v:48: Signal definition not found, creating implicitly: \'led_enable\'\n  assign led_enable = ((mem_addr == 9\'h100) && (mem_cmd == 2\'d2));\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/479923049/top.v:17: Cannot find file containing module: \'cpu\'\n  cpu CPU ( .clk          (~KEY[0]),\n  ^~~\n        ... Looked in:\n             data/full_repos/permissive/479923049,data/full_repos/permissive/479923049/cpu\n             data/full_repos/permissive/479923049,data/full_repos/permissive/479923049/cpu.v\n             data/full_repos/permissive/479923049,data/full_repos/permissive/479923049/cpu.sv\n             cpu\n             cpu.v\n             cpu.sv\n             obj_dir/cpu\n             obj_dir/cpu.v\n             obj_dir/cpu.sv\n%Error: data/full_repos/permissive/479923049/top.v:50: Cannot find file containing module: \'vDFFE\'\n  vDFFE #(8) ledr_register(.clk (KEY[0]), .en (led_enable), .in (write_data[7:0]), .out (LEDR[7:0]));\n  ^~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module top(KEY,SW,LEDR,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5);
  input [3:0] KEY;
  input [9:0] SW;
  output [9:0] LEDR;
  output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;

  wire [1:0]  mem_cmd;
  wire [8:0]  mem_addr;
  wire [15:0] read_data, write_data, dout; 
  wire N, V, Z, write_RAM, tristate_enable; 

  cpu CPU ( .clk          (~KEY[0]),
            .reset        (~KEY[1]),
            .N            (N),
            .V            (V),
            .Z            (Z),
            .mem_cmd      (mem_cmd), 
            .mem_addr     (mem_addr),   
            .write_data   (write_data), 
            .read_data    (read_data)
          );
  RAM MEM ( .clk              (~KEY[0]),
            .read_address     (mem_addr[7:0]),
            .write_address    (mem_addr[7:0]),
            .write            (write_RAM),
            .din              (write_data),
            .dout             (dout)
          );


  assign write_RAM = (`MWRITE == mem_cmd) & (1'b0 == mem_addr[8]);
  assign tri_state_enable = (`MREAD == mem_cmd) & (1'b0 == mem_addr[8]);
  assign read_data = tri_state_enable ? dout : {16{1'bz}};
  

  assign tri_state_switch_enable = ((mem_addr == 9'h140) && (mem_cmd == `MREAD));

  assign read_data[15:8] = tri_state_switch_enable ? 8'h00 : {8{1'bz}};

  assign read_data[7:0] = tri_state_switch_enable ? SW[7:0] : {8{1'bz}};
  

  assign led_enable = ((mem_addr == 9'h100) && (mem_cmd == `MWRITE));

  vDFFE #(8) ledr_register(.clk (KEY[0]), .en (led_enable), .in (write_data[7:0]), .out (LEDR[7:0]));



endmodule
module top(KEY,SW,LEDR,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5);

  input [3:0] KEY;
  input [9:0] SW;
  output [9:0] LEDR;
  output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;

  wire [1:0]  mem_cmd;
  wire [8:0]  mem_addr;
  wire [15:0] read_data, write_data, dout; 
  wire N, V, Z, write_RAM, tristate_enable; 

  cpu CPU ( .clk          (~KEY[0]),
            .reset        (~KEY[1]),
            .N            (N),
            .V            (V),
            .Z            (Z),
            .mem_cmd      (mem_cmd), 
            .mem_addr     (mem_addr),   
            .write_data   (write_data), 
            .read_data    (read_data)
          );
  RAM MEM ( .clk              (~KEY[0]),
            .read_address     (mem_addr[7:0]),
            .write_address    (mem_addr[7:0]),
            .write            (write_RAM),
            .din              (write_data),
            .dout             (dout)
          );


  assign write_RAM = (`MWRITE == mem_cmd) & (1'b0 == mem_addr[8]);
  assign tri_state_enable = (`MREAD == mem_cmd) & (1'b0 == mem_addr[8]);
  assign read_data = tri_state_enable ? dout : {16{1'bz}};
  

  assign tri_state_switch_enable = ((mem_addr == 9'h140) && (mem_cmd == `MREAD));

  assign read_data[15:8] = tri_state_switch_enable ? 8'h00 : {8{1'bz}};

  assign read_data[7:0] = tri_state_switch_enable ? SW[7:0] : {8{1'bz}};
  

  assign led_enable = ((mem_addr == 9'h100) && (mem_cmd == `MWRITE));

  vDFFE #(8) ledr_register(.clk (KEY[0]), .en (led_enable), .in (write_data[7:0]), .out (LEDR[7:0]));



endmodule