data/full_repos/permissive/411457613/Pyverilog/verilogcode/count.v
data/verilator_xmls/deda1c09-2486-478d-b234-0647a849a3b6.xml
module TOP(CLK, RST_X);
  input CLK;
  input RST_X;
  reg [3:0] cnt;

  always @(posedge CLK or negedge RST_X) begin
    if(!RST_X) begin
      cnt <= 0;
    end else begin
      cnt <= cnt + 1;
    end
  end
  
endmodule
module TOP(CLK, RST_X);

  input CLK;
  input RST_X;
  reg [3:0] cnt;

  always @(posedge CLK or negedge RST_X) begin
    if(!RST_X) begin
      cnt <= 0;
    end else begin
      cnt <= cnt + 1;
    end
  end
  
endmodule