data/full_repos/permissive/461000256/hdl/ID_EXE.v
data/verilator_xmls/b554e666-b133-4c6b-a25d-7240aa7996ec.xml
module ID_EXE(
	input wire 				clk,	
	input wire [`DW-1:0] 		in_r1,	
	input wire [`DW-1:0] 		in_r2,
	input wire [`IW-1:0] 	in_inst,		
	output reg [`DW-1:0] 		out_r1,	
	output reg [`DW-1:0] 		out_r2,
	output reg [`IW-1:0] 	out_inst
	
);

	always @(posedge clk) begin
		out_r1 	<= #5 in_r1;
		out_r2 	<= #5 in_r2;
		out_inst <= #5 in_inst;
	end

endmodule
module ID_EXE(
	input wire 				clk,	
	input wire [`DW-1:0] 		in_r1,	
	input wire [`DW-1:0] 		in_r2,
	input wire [`IW-1:0] 	in_inst,		
	output reg [`DW-1:0] 		out_r1,	
	output reg [`DW-1:0] 		out_r2,
	output reg [`IW-1:0] 	out_inst
	
);


	always @(posedge clk) begin
		out_r1 	<= #5 in_r1;
		out_r2 	<= #5 in_r2;
		out_inst <= #5 in_inst;
	end

endmodule