data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v
1: b'%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:5: Cannot find include file: define.vh\n`include "define.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src,data/full_repos/permissive/413020148/define.vh\n             data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src,data/full_repos/permissive/413020148/define.vh.v\n             data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src,data/full_repos/permissive/413020148/define.vh.sv\n             define.vh\n             define.vh.v\n             define.vh.sv\n             obj_dir/define.vh\n             obj_dir/define.vh.v\n             obj_dir/define.vh.sv\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:50: Define or directive not defined: \'`OPCODE_STORE___\'\n    wire        w_we = (r_opcode==`OPCODE_STORE___ && r_state==2);\n                                  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:50: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n    wire        w_we = (r_opcode==`OPCODE_STORE___ && r_state==2);\n                                                   ^~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:52: Define or directive not defined: \'`OPCODE_LOAD____\'\n    wire [31:0] w_reg_d  = (r_opcode==`OPCODE_LOAD____) ? w_mem_rdata : r_rslt;\n                                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:52: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    wire [31:0] w_reg_d  = (r_opcode==`OPCODE_LOAD____) ? w_mem_rdata : r_rslt;\n                                                      ^\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:53: Define or directive not defined: \'`OPCODE_LOAD____\'\n    wire        w_reg_we = (r_opcode==`OPCODE_LOAD____) ? 1 :\n                                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:53: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    wire        w_reg_we = (r_opcode==`OPCODE_LOAD____) ? 1 :\n                                                      ^\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:54: Define or directive not defined: \'`OPCODE_LUI_____\'\n                           (r_opcode==`OPCODE_LUI_____) ? 1 :\n                                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:55: Define or directive not defined: \'`OPCODE_AUIPC___\'\n                           (r_opcode==`OPCODE_AUIPC___) ? 1 :\n                                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:56: Define or directive not defined: \'`OPCODE_JAL_____\'\n                           (r_opcode==`OPCODE_JAL_____) ? 1 :\n                                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:57: Define or directive not defined: \'`OPCODE_JALR____\'\n                           (r_opcode==`OPCODE_JALR____) ? 1 :\n                                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:58: Define or directive not defined: \'`OPCODE_OP______\'\n                           (r_opcode==`OPCODE_OP______) ? 1 :\n                                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:59: Define or directive not defined: \'`OPCODE_OP_IMM__\'\n                           (r_opcode==`OPCODE_OP_IMM__) ? 1 : 0;\n                                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:61: Define or directive not defined: \'`ACCESS_CODE\'\n    assign w_mic_req = (r_state==0)                            ? `ACCESS_CODE  :\n                                                                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:61: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n    assign w_mic_req = (r_state==0)                            ? `ACCESS_CODE  :\n                                                                               ^\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:62: Define or directive not defined: \'`ACCESS_WRITE\'\n                   (r_state==2 && w_we)                        ? `ACCESS_WRITE :\n                                                                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:63: Define or directive not defined: \'`OPCODE_LOAD____\'\n                   (r_state==2 && r_opcode==`OPCODE_LOAD____)  ? `ACCESS_READ  : 3;\n                                            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:63: Define or directive not defined: \'`ACCESS_READ\'\n                   (r_state==2 && r_opcode==`OPCODE_LOAD____)  ? `ACCESS_READ  : 3;\n                                                                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:102: Define or directive not defined: \'`OPCODE_OP_IMM__\'\n    wire  [6:0] w_alu_fn7 = (r_opcode==`OPCODE_OP_IMM__) ? \n                                       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:102: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    wire  [6:0] w_alu_fn7 = (r_opcode==`OPCODE_OP_IMM__) ? \n                                                       ^\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:103: Define or directive not defined: \'`FUNCT3_ADD___\'\n                            ((r_funct3==`FUNCT3_ADD___) ? 0 : r_funct7 & 7\'h20) : r_funct7;\n                                        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:105: Define or directive not defined: \'`OPCODE_OP_IMM__\'\n    wire [31:0] w_in2 = (r_opcode==`OPCODE_OP_IMM__) ? r_imm : r_rrs2;\n                                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:105: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    wire [31:0] w_in2 = (r_opcode==`OPCODE_OP_IMM__) ? r_imm : r_rrs2;\n                                                   ^\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:120: Define or directive not defined: \'`OPCODE_LUI_____\'\n               `OPCODE_LUI_____ : r_rslt <= r_imm;\n               ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:120: syntax error, unexpected \':\', expecting endcase\n               `OPCODE_LUI_____ : r_rslt <= r_imm;\n                                ^\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:121: Define or directive not defined: \'`OPCODE_AUIPC___\'\n               `OPCODE_AUIPC___ : r_rslt <= r_pc + r_imm;\n               ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:122: Define or directive not defined: \'`OPCODE_JAL_____\'\n               `OPCODE_JAL_____ : r_rslt <= r_pc + 4;\n               ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:123: Define or directive not defined: \'`OPCODE_JALR____\'\n               `OPCODE_JALR____ : r_rslt <= r_pc + 4;\n               ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:124: Define or directive not defined: \'`OPCODE_OP______\'\n               `OPCODE_OP______ : r_rslt <= w_alu_i_rslt;\n               ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:125: Define or directive not defined: \'`OPCODE_OP_IMM__\'\n               `OPCODE_OP_IMM__ : r_rslt <= w_alu_i_rslt;\n               ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:126: Define or directive not defined: \'`OPCODE_BRANCH__\'\n               `OPCODE_BRANCH__ : r_rslt <= 0;\n               ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:127: Define or directive not defined: \'`OPCODE_LOAD____\'\n               `OPCODE_LOAD____ : r_rslt <= 0;\n               ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:128: Define or directive not defined: \'`OPCODE_STORE___\'\n               `OPCODE_STORE___ : r_rslt <= 0;\n               ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:129: Define or directive not defined: \'`OPCODE_MISC_MEM\'\n               `OPCODE_MISC_MEM : r_rslt <= 0;\n               ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:137: syntax error, unexpected endcase\n           endcase\n           ^~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:138: Define or directive not defined: \'`OPCODE_JALR____\'\n            r_jmp_pc <= (r_opcode==`OPCODE_JALR____) ? r_rrs1+r_imm : r_pc+r_imm;\n                                   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:139: Define or directive not defined: \'`OPCODE_JAL_____\'\n            r_tkn <= (r_opcode==`OPCODE_JAL_____ || r_opcode==`OPCODE_JALR____) ? 1 :\n                                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:139: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n            r_tkn <= (r_opcode==`OPCODE_JAL_____ || r_opcode==`OPCODE_JALR____) ? 1 :\n                                                 ^~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:139: Define or directive not defined: \'`OPCODE_JALR____\'\n            r_tkn <= (r_opcode==`OPCODE_JAL_____ || r_opcode==`OPCODE_JALR____) ? 1 :\n                                                              ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/413020148/verilog/rtl/cores/RVsoc/src/microc.v:140: Define or directive not defined: \'`OPCODE_BRANCH__\'\n                    (r_opcode==`OPCODE_BRANCH__) ? w_alu_b_rslt : 0;\n                               ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 40 error(s)\n'
module m_lm_mc(CLK, w_addr1, r_odata1, w_we, w_addr2, r_odata2, w_idata);
    input  wire                         CLK;
    input  wire                   [3:0] w_we;
    input  wire [(`D_UC_LM_BITS-2)-1:0] w_addr1, w_addr2;
    input  wire    [`D_UC_LM_WIDTH-1:0] w_idata;
    output  reg    [`D_UC_LM_WIDTH-1:0] r_odata1, r_odata2;

    (* ram_style = "block" *) reg [`D_UC_LM_WIDTH-1:0] mem[0:(`D_UC_LM_SIZE/4)-1];
    initial begin
        $readmemh(`D_UC_LM_IFILE, mem);
        $write("Load a micro contoroller's program: %s\n", `D_UC_LM_IFILE);
    end

    always@(posedge CLK) begin
        r_odata1 <= mem[w_addr1];
    end
    always @(posedge CLK) begin
        if (w_we[0]) mem[w_addr2][ 7: 0] <= w_idata[ 7: 0];
        if (w_we[1]) mem[w_addr2][15: 8] <= w_idata[15: 8];
        if (w_we[2]) mem[w_addr2][23:16] <= w_idata[23:16];
        if (w_we[3]) mem[w_addr2][31:24] <= w_idata[31:24];
        r_odata2 <= mem[w_addr2];
    end
endmodule
module m_lm_mc(CLK, w_addr1, r_odata1, w_we, w_addr2, r_odata2, w_idata);

    input  wire                         CLK;
    input  wire                   [3:0] w_we;
    input  wire [(`D_UC_LM_BITS-2)-1:0] w_addr1, w_addr2;
    input  wire    [`D_UC_LM_WIDTH-1:0] w_idata;
    output  reg    [`D_UC_LM_WIDTH-1:0] r_odata1, r_odata2;

    (* ram_style = "block" *) reg [`D_UC_LM_WIDTH-1:0] mem[0:(`D_UC_LM_SIZE/4)-1];
    initial begin
        $readmemh(`D_UC_LM_IFILE, mem);
        $write("Load a micro contoroller's program: %s\n", `D_UC_LM_IFILE);
    end

    always@(posedge CLK) begin
        r_odata1 <= mem[w_addr1];
    end
    always @(posedge CLK) begin
        if (w_we[0]) mem[w_addr2][ 7: 0] <= w_idata[ 7: 0];
        if (w_we[1]) mem[w_addr2][15: 8] <= w_idata[15: 8];
        if (w_we[2]) mem[w_addr2][23:16] <= w_idata[23:16];
        if (w_we[3]) mem[w_addr2][31:24] <= w_idata[31:24];
        r_odata2 <= mem[w_addr2];
    end
endmodule