data/full_repos/permissive/426864978/lab3/task2/tb_syn_task2.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task2/tb_syn_task2.sv:22: Unsupported: Ignoring delay on this delayed statement.\n        forever #5 CLOCK_50 = ~CLOCK_50;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task2/tb_syn_task2.sv:30: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task2/tb_syn_task2.sv:34: Unsupported: Ignoring delay on this delayed statement.\n        #30;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task2/tb_syn_task2.sv:38: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task2/tb_syn_task2.sv:42: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task2/tb_syn_task2.sv:46: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task2/tb_syn_task2.sv:57: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task2/tb_syn_task2.sv:61: syntax error, unexpected \'@\'\n                @(posedge CLOCK_50)          \n                ^\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_syn_task2();

    logic CLOCK_50, err;
    logic [3:0] KEY;
    logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
    logic [9:0] SW, LEDR;
    logic [7:0] mem[255:0];
    logic [31:0] tdo;

    task2 dut(
        .altera_reserved_tms(32'b0),
        .altera_reserved_tck(32'b0),
        .altera_reserved_tdi(32'b0),
        .altera_reserved_tdo(tdo),
        .*
    );

    initial begin
        CLOCK_50 = 1;
        forever #5 CLOCK_50 = ~CLOCK_50;
    end

    initial begin
        err = 1'b0;


        KEY[3] = 1'bx;
        #10;


        KEY[3] = 1'b0;
        #30;


        KEY[3] = 1'b1;
        #10;


        for (int i = 0; i < 256; i++) begin
            #10;
        end


        #10;


        for (int i = 0; i < 256; i++) begin
            if (tb_syn_task2.dut.\s|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i] !== i) begin
                $display("MEM ERR: Expected value is %d, actual value is %d", i, tb_syn_task2.dut.\s|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i]);
                err = 1'b1;
            end
        end

        SW = 10'h033C;
        #10;

        for (int i = 0; i < 256; i++)
            for (int j = 0; j < 7; j++)
                @(posedge CLOCK_50)
        #20;

        $readmemh("result.txt", mem);

        for (int i = 0; i < 256; i++) begin
            if (tb_syn_task2.dut.\s|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i] !== mem[i]) begin 
                $display("MEM ERROR %d: Expected mem is %d, actual mem is %d", i[7:0], mem[i], tb_syn_task2.dut.\s|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i]);
                err = 1'b1;
            end
        end

        if (~err)
            $display("SUCCESS: All tests passed.");
        $stop;
    end

endmodule
module tb_syn_task2();


    logic CLOCK_50, err;
    logic [3:0] KEY;
    logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
    logic [9:0] SW, LEDR;
    logic [7:0] mem[255:0];
    logic [31:0] tdo;

    task2 dut(
        .altera_reserved_tms(32'b0),
        .altera_reserved_tck(32'b0),
        .altera_reserved_tdi(32'b0),
        .altera_reserved_tdo(tdo),
        .*
    );

    initial begin
        CLOCK_50 = 1;
        forever #5 CLOCK_50 = ~CLOCK_50;
    end

    initial begin
        err = 1'b0;


        KEY[3] = 1'bx;
        #10;


        KEY[3] = 1'b0;
        #30;


        KEY[3] = 1'b1;
        #10;


        for (int i = 0; i < 256; i++) begin
            #10;
        end


        #10;


        for (int i = 0; i < 256; i++) begin
            if (tb_syn_task2.dut.\s|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i] !== i) begin
                $display("MEM ERR: Expected value is %d, actual value is %d", i, tb_syn_task2.dut.\s|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i]);
                err = 1'b1;
            end
        end

        SW = 10'h033C;
        #10;

        for (int i = 0; i < 256; i++)
            for (int j = 0; j < 7; j++)
                @(posedge CLOCK_50)
        #20;

        $readmemh("result.txt", mem);

        for (int i = 0; i < 256; i++) begin
            if (tb_syn_task2.dut.\s|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i] !== mem[i]) begin 
                $display("MEM ERROR %d: Expected mem is %d, actual mem is %d", i[7:0], mem[i], tb_syn_task2.dut.\s|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i]);
                err = 1'b1;
            end
        end

        if (~err)
            $display("SUCCESS: All tests passed.");
        $stop;
    end

endmodule