data/full_repos/permissive/458737381/src/verilog-parser/tests/casex_example.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/casex_example.v:26: Unsupported: Ignoring delay on this delayed statement.\nalways #2 a = $random;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/casex_example.v:27: Unsupported: Ignoring delay on this delayed statement.\nalways #2 b = $random;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/casex_example.v:28: Unsupported: Ignoring delay on this delayed statement.\nalways #2 c = $random;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/casex_example.v:32: Unsupported: Ignoring delay on this delayed statement.\n  #2 opcode = 4\'b101x;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/casex_example.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #2 opcode = 4\'b0101;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/casex_example.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #2 opcode = 4\'b0010;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/casex_example.v:35: Unsupported: Ignoring delay on this delayed statement.\n  #2 opcode = 4\'b0000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/casex_example.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #2 $finish;\n  ^\n%Warning-WIDTH: data/full_repos/permissive/458737381/src/verilog-parser/tests/casex_example.v:26: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                                : ... In instance casex_example\nalways #2 a = $random;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/458737381/src/verilog-parser/tests/casex_example.v:27: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                                : ... In instance casex_example\nalways #2 b = $random;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/458737381/src/verilog-parser/tests/casex_example.v:28: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                                                : ... In instance casex_example\nalways #2 c = $random;\n            ^\n%Error: Exiting due to 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module casex_example();
reg [3:0] opcode;
reg [1:0] a,b,c;
reg [1:0] out;

always @ (opcode or a or b or c)
casex(opcode)
  4'b1zzx : begin
              out = a; 
              $display("@%0dns 4'b1zzx is selected, opcode %b",$time,opcode);
            end
  4'b01?? : begin
              out = b; 
              $display("@%0dns 4'b01?? is selected, opcode %b",$time,opcode);
            end
  4'b001? : begin
              out = c;
              $display("@%0dns 4'b001? is selected, opcode %b",$time,opcode);
            end
  default : begin
              $display("@%0dns default is selected, opcode %b",$time,opcode);
            end
endcase 


always #2 a = $random;
always #2 b = $random;
always #2 c = $random;

initial begin
  opcode = 0;
  #2 opcode = 4'b101x;
  #2 opcode = 4'b0101;
  #2 opcode = 4'b0010;
  #2 opcode = 4'b0000;
  #2 $finish;
end

endmodule
module casex_example();

reg [3:0] opcode;
reg [1:0] a,b,c;
reg [1:0] out;

always @ (opcode or a or b or c)
casex(opcode)
  4'b1zzx : begin
              out = a; 
              $display("@%0dns 4'b1zzx is selected, opcode %b",$time,opcode);
            end
  4'b01?? : begin
              out = b; 
              $display("@%0dns 4'b01?? is selected, opcode %b",$time,opcode);
            end
  4'b001? : begin
              out = c;
              $display("@%0dns 4'b001? is selected, opcode %b",$time,opcode);
            end
  default : begin
              $display("@%0dns default is selected, opcode %b",$time,opcode);
            end
endcase 


always #2 a = $random;
always #2 b = $random;
always #2 c = $random;

initial begin
  opcode = 0;
  #2 opcode = 4'b101x;
  #2 opcode = 4'b0101;
  #2 opcode = 4'b0010;
  #2 opcode = 4'b0000;
  #2 $finish;
end

endmodule