data/full_repos/permissive/416058412/hw/rtl/nic_counters.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/416058412/hw/rtl/nic_counters.sv:76: Bit extraction of array[4:0] requires 3 bit index, not 8 bits.\n                                                                              : ... In instance nic_counters\n            counter_value_out <= counters[counter_id_in];\n                                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module nic_counters
    (
    input logic reset,


    input logic clk_0,
    input logic t_incoming_rpc,
    input logic t_outcoming_rpc,
    input logic t_pdrop_tx_flows,

    input logic clk_1,
    input logic t_outcoming_network_packets,
    input logic t_incoming_network_packets,


    input logic clk_io,
    input logic[7:0]   counter_id_in,
    output logic[63:0] counter_value_out

    );


    logic[63:0] counters [5];


    logic t_incoming_rpc_d;
    logic t_outcoming_rpc_d;
    logic t_pdrop_tx_flows_d;

    always @(posedge clk_0) begin
        if (reset) begin
            counters[0] <= {(64){1'b0}};
            counters[1] <= {(64){1'b0}};
            counters[4] <= {(64){1'b0}};

        end else begin
            t_incoming_rpc_d  <= t_incoming_rpc;
            t_outcoming_rpc_d <= t_outcoming_rpc;
            t_pdrop_tx_flows_d <= t_pdrop_tx_flows;

            if (t_incoming_rpc_d)  counters[0] <= counters[0] + 1;
            if (t_outcoming_rpc_d) counters[1] <= counters[1] + 1;
            if (t_pdrop_tx_flows_d) counters[4] <= counters[4] + 1;
        end
    end


    logic t_outcoming_network_packets_d;
    logic t_incoming_network_packets_d;

    always @(posedge clk_1) begin
        if (reset) begin
            counters[2] <= {(64){1'b0}};
            counters[3] <= {(64){1'b0}};

        end else begin
            t_outcoming_network_packets_d <= t_outcoming_network_packets;
            t_incoming_network_packets_d  <= t_incoming_network_packets;

            if (t_outcoming_network_packets_d) counters[2] <= counters[2] + 1;
            if (t_incoming_network_packets_d)  counters[3] <= counters[3] + 1;
        end
    end


    always @(posedge clk_io) begin
        if (reset) begin
            counter_value_out <= {(64){1'b0}};
        end else begin
            counter_value_out <= counters[counter_id_in];
        end
    end

endmodule
module nic_counters
    (
    input logic reset,


    input logic clk_0,
    input logic t_incoming_rpc,
    input logic t_outcoming_rpc,
    input logic t_pdrop_tx_flows,

    input logic clk_1,
    input logic t_outcoming_network_packets,
    input logic t_incoming_network_packets,


    input logic clk_io,
    input logic[7:0]   counter_id_in,
    output logic[63:0] counter_value_out

    );



    logic[63:0] counters [5];


    logic t_incoming_rpc_d;
    logic t_outcoming_rpc_d;
    logic t_pdrop_tx_flows_d;

    always @(posedge clk_0) begin
        if (reset) begin
            counters[0] <= {(64){1'b0}};
            counters[1] <= {(64){1'b0}};
            counters[4] <= {(64){1'b0}};

        end else begin
            t_incoming_rpc_d  <= t_incoming_rpc;
            t_outcoming_rpc_d <= t_outcoming_rpc;
            t_pdrop_tx_flows_d <= t_pdrop_tx_flows;

            if (t_incoming_rpc_d)  counters[0] <= counters[0] + 1;
            if (t_outcoming_rpc_d) counters[1] <= counters[1] + 1;
            if (t_pdrop_tx_flows_d) counters[4] <= counters[4] + 1;
        end
    end


    logic t_outcoming_network_packets_d;
    logic t_incoming_network_packets_d;

    always @(posedge clk_1) begin
        if (reset) begin
            counters[2] <= {(64){1'b0}};
            counters[3] <= {(64){1'b0}};

        end else begin
            t_outcoming_network_packets_d <= t_outcoming_network_packets;
            t_incoming_network_packets_d  <= t_incoming_network_packets;

            if (t_outcoming_network_packets_d) counters[2] <= counters[2] + 1;
            if (t_incoming_network_packets_d)  counters[3] <= counters[3] + 1;
        end
    end


    always @(posedge clk_io) begin
        if (reset) begin
            counter_value_out <= {(64){1'b0}};
        end else begin
            counter_value_out <= counters[counter_id_in];
        end
    end

endmodule