data/full_repos/permissive/465067219/RiscV/RiscV.srcs/sources_1/new/Branch.v
data/verilator_xmls/c3306c9d-fede-45ff-adce-cef644e9d9c8.xml
module Branch(
    input branch_flag,
    input zero_flag,
    output reg PCSrc
    );
    always @(*) begin
        if (branch_flag)
            PCSrc = zero_flag;
        else
            PCSrc = 0;
    end
endmodule
module Branch(
    input branch_flag,
    input zero_flag,
    output reg PCSrc
    );

    always @(*) begin
        if (branch_flag)
            PCSrc = zero_flag;
        else
            PCSrc = 0;
    end
endmodule