data/full_repos/permissive/473722449/DFF_clr.v
data/verilator_xmls/ca777a51-c66b-4091-b6bf-a41a316a3e21.xml
module DFF_clr(
    input d,
    input clk,
    input clear,
    output reg q
    );
    always@(posedge clk)
    begin
        if (clear == 1)
            q=1'b0;
        else
            q=d;   
    end
endmodule
module DFF_clr(
    input d,
    input clk,
    input clear,
    output reg q
    );

    always@(posedge clk)
    begin
        if (clear == 1)
            q=1'b0;
        else
            q=d;   
    end
endmodule