data/full_repos/permissive/490649362/single-cycle/src/IM.v
data/verilator_xmls/1371d4e8-66a8-4c3e-a37c-5b47010708c4.xml
module IM(addr, inst);

    parameter size = 64;

    input  [31:0] addr;
    output [31:0] inst;

    reg    [31:0] memory [0:size-1];



    initial begin
        $readmemb("InstructionMem_Demo.txt", memory);
    end

    assign inst = memory[addr>>2];

endmodule
module IM(addr, inst);


    parameter size = 64;

    input  [31:0] addr;
    output [31:0] inst;

    reg    [31:0] memory [0:size-1];



    initial begin
        $readmemb("InstructionMem_Demo.txt", memory);
    end

    assign inst = memory[addr>>2];

endmodule