data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:472: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s CONST \'4\'h6\' generates 4 bits.\n                                                                              : ... In instance fx68kAlu.aluCorf\n   htemp = { 1\'b0, binResult} + (lowC  ? 4\'h6 : 4\'h0);\n                                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:472: Operator COND expects 9 bits on the Conditional False, but Conditional False\'s CONST \'4\'h0\' generates 4 bits.\n                                                                              : ... In instance fx68kAlu.aluCorf\n   htemp = { 1\'b0, binResult} + (lowC  ? 4\'h6 : 4\'h0);\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:473: Operator COND expects 5 bits on the Conditional True, but Conditional True\'s CONST \'4\'h6\' generates 4 bits.\n                                                                              : ... In instance fx68kAlu.aluCorf\n   hNib  = htemp[8:4] + (highC ? 4\'h6 : 4\'h0);\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:473: Operator COND expects 5 bits on the Conditional False, but Conditional False\'s CONST \'4\'h0\' generates 4 bits.\n                                                                              : ... In instance fx68kAlu.aluCorf\n   hNib  = htemp[8:4] + (highC ? 4\'h6 : 4\'h0);\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:477: Operator COND expects 9 bits on the Conditional True, but Conditional True\'s CONST \'4\'h6\' generates 4 bits.\n                                                                              : ... In instance fx68kAlu.aluCorf\n   htemp = { 1\'b0, binResult} - (lowC  ? 4\'h6 : 4\'h0);\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:477: Operator COND expects 9 bits on the Conditional False, but Conditional False\'s CONST \'4\'h0\' generates 4 bits.\n                                                                              : ... In instance fx68kAlu.aluCorf\n   htemp = { 1\'b0, binResult} - (lowC  ? 4\'h6 : 4\'h0);\n                                       ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:478: Operator COND expects 5 bits on the Conditional True, but Conditional True\'s CONST \'4\'h6\' generates 4 bits.\n                                                                              : ... In instance fx68kAlu.aluCorf\n   hNib  = htemp[8:4] - (highC ? 4\'h6 : 4\'h0);\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:478: Operator COND expects 5 bits on the Conditional False, but Conditional False\'s CONST \'4\'h0\' generates 4 bits.\n                                                                              : ... In instance fx68kAlu.aluCorf\n   hNib  = htemp[8:4] - (highC ? 4\'h6 : 4\'h0);\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:282: Operator ADD expects 17 bits on the LHS, but LHS\'s REPLICATE generates 9 bits.\n                                                                              : ... In instance fx68kAlu\n    rtemp = bAdd ? { 1\'b0, inpb[7:0]} + { 1\'b0, inpa[7:0]} + cin:\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:282: Operator ADD expects 17 bits on the RHS, but RHS\'s REPLICATE generates 9 bits.\n                                                                              : ... In instance fx68kAlu\n    rtemp = bAdd ? { 1\'b0, inpb[7:0]} + { 1\'b0, inpa[7:0]} + cin:\n                                      ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:282: Operator ADD expects 17 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                              : ... In instance fx68kAlu\n    rtemp = bAdd ? { 1\'b0, inpb[7:0]} + { 1\'b0, inpa[7:0]} + cin:\n                                                           ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:283: Operator SUB expects 17 bits on the LHS, but LHS\'s REPLICATE generates 9 bits.\n                                                                              : ... In instance fx68kAlu\n        { 1\'b0, inpb[7:0] } - { 1\'b0, inpa[7:0]} - cin;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:283: Operator SUB expects 17 bits on the RHS, but RHS\'s REPLICATE generates 9 bits.\n                                                                              : ... In instance fx68kAlu\n        { 1\'b0, inpb[7:0] } - { 1\'b0, inpa[7:0]} - cin;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:283: Operator SUB expects 17 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                              : ... In instance fx68kAlu\n        { 1\'b0, inpb[7:0] } - { 1\'b0, inpa[7:0]} - cin;\n                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:288: Operator ADD expects 17 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                              : ... In instance fx68kAlu\n    rtemp = bAdd ? { 1\'b0, inpb } + { 1\'b0, inpa} + cin:\n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/452215364/rtl/fx86k/fx68kAlu.sv:289: Operator SUB expects 17 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                                              : ... In instance fx68kAlu\n        { 1\'b0, inpb } - { 1\'b0, inpa} - cin;\n                                       ^\n%Error: Exiting due to 16 warning(s)\n'
module ccrTable( 
	input [2:0] col, input [15:0] row, input finish,
	output logic [MASK_NBITS-1:0] ccrMask);
    
	localparam
		KNZ00 = 5'b01111,
		KKZKK = 5'b00100,
		KNZKK = 5'b01100,
		KNZ10 = 5'b01111,
		KNZ0C = 5'b01111,



		KNZVC	= 5'b01111,
		XNKVC	= 5'b11011,
		
		CUPDALL = 5'b11111,
		CUNUSED = 5'bxxxxx;
    

	logic [MASK_NBITS-1:0] ccrMask1;

	always_comb begin
		unique case( col)
		1:			ccrMask = ccrMask1;
		
		2,3:
			unique case( 1'b1)
			row[1]:		ccrMask = KNZ0C;
			
			row[3],
			row[9]:
						ccrMask = (col == 2) ? XNKVC : CUPDALL;
			
			row[2],
			row[5],
			row[10],
			row[12]:	ccrMask = CUPDALL;

			row[6],
			row[7],
			row[11]:	ccrMask = KNZVC;
			row[4],
			row[8],
			row[13],
			row[14]:	ccrMask = KNZ00;
			row[15]:	ccrMask = 5'b0;

			endcase			
			
		4:
			unique case( row)



			`ALU_ROW_02,
			`ALU_ROW_03,
			`ALU_ROW_04,
			`ALU_ROW_05:	ccrMask = CUPDALL;
			
			`ALU_ROW_07:	ccrMask = KNZ00;
			`ALU_ROW_09,
			`ALU_ROW_10:	ccrMask = KNZ00;
			`ALU_ROW_08,
			`ALU_ROW_11:	ccrMask = CUPDALL;
			default:	ccrMask = CUNUSED;
			endcase
		
		5:			ccrMask = row[1] ? KNZ10 : 5'b0;
		default:	ccrMask = CUNUSED;
		endcase
	end


	always_comb begin
		if( finish)
			ccrMask1 = row[7] ? KNZ00 : KNZKK;
		else
			ccrMask1 = row[13] | row[14] ? KKZKK : KNZ00;
	end
    
endmodule
module ccrTable( 
	input [2:0] col, input [15:0] row, input finish,
	output logic [MASK_NBITS-1:0] ccrMask);

    
	localparam
		KNZ00 = 5'b01111,
		KKZKK = 5'b00100,
		KNZKK = 5'b01100,
		KNZ10 = 5'b01111,
		KNZ0C = 5'b01111,



		KNZVC	= 5'b01111,
		XNKVC	= 5'b11011,
		
		CUPDALL = 5'b11111,
		CUNUSED = 5'bxxxxx;
    

	logic [MASK_NBITS-1:0] ccrMask1;

	always_comb begin
		unique case( col)
		1:			ccrMask = ccrMask1;
		
		2,3:
			unique case( 1'b1)
			row[1]:		ccrMask = KNZ0C;
			
			row[3],
			row[9]:
						ccrMask = (col == 2) ? XNKVC : CUPDALL;
			
			row[2],
			row[5],
			row[10],
			row[12]:	ccrMask = CUPDALL;

			row[6],
			row[7],
			row[11]:	ccrMask = KNZVC;
			row[4],
			row[8],
			row[13],
			row[14]:	ccrMask = KNZ00;
			row[15]:	ccrMask = 5'b0;

			endcase			
			
		4:
			unique case( row)



			`ALU_ROW_02,
			`ALU_ROW_03,
			`ALU_ROW_04,
			`ALU_ROW_05:	ccrMask = CUPDALL;
			
			`ALU_ROW_07:	ccrMask = KNZ00;
			`ALU_ROW_09,
			`ALU_ROW_10:	ccrMask = KNZ00;
			`ALU_ROW_08,
			`ALU_ROW_11:	ccrMask = CUPDALL;
			default:	ccrMask = CUNUSED;
			endcase
		
		5:			ccrMask = row[1] ? KNZ10 : 5'b0;
		default:	ccrMask = CUNUSED;
		endcase
	end


	always_comb begin
		if( finish)
			ccrMask1 = row[7] ? KNZ00 : KNZKK;
		else
			ccrMask1 = row[13] | row[14] ? KKZKK : KNZ00;
	end
    
endmodule