data/full_repos/permissive/445929378/mult_128_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/445929378/mult_128_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/445929378/mult_128_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n      #5;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/445929378/mult_128_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n      #12;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/445929378/mult_128_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n      #100;\n      ^\n%Error: data/full_repos/permissive/445929378/mult_128_tb.v:21: Cannot find file containing module: \'mult_128\'\n   mult_128 uut (\n   ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/mult_128\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/mult_128.v\n             data/full_repos/permissive/445929378,data/full_repos/permissive/445929378/mult_128.sv\n             mult_128\n             mult_128.v\n             mult_128.sv\n             obj_dir/mult_128\n             obj_dir/mult_128.v\n             obj_dir/mult_128.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module mult_128_tb;
   

   reg clk;
   reg rst;
   reg [63:0] input_a_tdata;
   reg [63:0] input_b_tdata;
   reg 	      input_a_tvalid;
   reg 	      input_b_tvalid;
   reg 	      output_tready;


   wire       input_a_tready;
   wire       input_b_tready;
   wire [127:0] output_tdata;
   wire 	output_tvalid;


   mult_128 uut (
		 .clk(clk), 
		 .rst(rst), 
		 .input_a_tdata(input_a_tdata), 
		 .input_b_tdata(input_b_tdata), 
		 .input_a_tvalid(input_a_tvalid), 
		 .input_b_tvalid(input_b_tvalid), 
		 .input_a_tready(input_a_tready), 
		 .input_b_tready(input_b_tready), 
		 .output_tdata(output_tdata), 
		 .output_tvalid(output_tvalid), 
		 .output_tready(output_tready)
		 );
   
   initial begin
      clk = 0;
      forever begin
	 #10 clk = ~clk;
      end
   end
   
   initial begin

      rst = 0;


      input_a_tdata = 64'd9223372036854775337;
      input_b_tdata = 64'd9223372036854775337;
      #5;
      input_a_tvalid = 1;
      input_b_tvalid = 1;
      #12;
      output_tready = 1;


      #100;


   end
   
endmodule
module mult_128_tb;

   

   reg clk;
   reg rst;
   reg [63:0] input_a_tdata;
   reg [63:0] input_b_tdata;
   reg 	      input_a_tvalid;
   reg 	      input_b_tvalid;
   reg 	      output_tready;


   wire       input_a_tready;
   wire       input_b_tready;
   wire [127:0] output_tdata;
   wire 	output_tvalid;


   mult_128 uut (
		 .clk(clk), 
		 .rst(rst), 
		 .input_a_tdata(input_a_tdata), 
		 .input_b_tdata(input_b_tdata), 
		 .input_a_tvalid(input_a_tvalid), 
		 .input_b_tvalid(input_b_tvalid), 
		 .input_a_tready(input_a_tready), 
		 .input_b_tready(input_b_tready), 
		 .output_tdata(output_tdata), 
		 .output_tvalid(output_tvalid), 
		 .output_tready(output_tready)
		 );
   
   initial begin
      clk = 0;
      forever begin
	 #10 clk = ~clk;
      end
   end
   
   initial begin

      rst = 0;


      input_a_tdata = 64'd9223372036854775337;
      input_b_tdata = 64'd9223372036854775337;
      #5;
      input_a_tvalid = 1;
      input_b_tvalid = 1;
      #12;
      output_tready = 1;


      #100;


   end
   
endmodule