data/full_repos/permissive/439087417/Add_Sub_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/439087417/Add_Sub_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/439087417/Add_Sub_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439087417/Add_Sub_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/439087417/Add_Sub_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/439087417/Add_Sub_tb.v:36: Cannot find file containing module: \'Add_Sub\'\n Add_Sub uut (\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/439087417,data/full_repos/permissive/439087417/Add_Sub\n             data/full_repos/permissive/439087417,data/full_repos/permissive/439087417/Add_Sub.v\n             data/full_repos/permissive/439087417,data/full_repos/permissive/439087417/Add_Sub.sv\n             Add_Sub\n             Add_Sub.v\n             Add_Sub.sv\n             obj_dir/Add_Sub\n             obj_dir/Add_Sub.v\n             obj_dir/Add_Sub.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Add_Sub_tb;


	reg [15:0] a;
	reg [15:0] b;
	reg add;


	wire [15:0] c;


	Add_Sub uut (
		.a(a), 
		.b(b), 
		.add(add), 
		.c(c)
	);

	initial begin

		a = 0;
		b = 0;
		add = 0;


		#100;
      a = 20;
		b = 5;
		#100;
		a = 15;
		b = 2;
		add = 1;
		#100;
		a = 20;
		b = 5;
		#100;


	end
      
endmodule
module Add_Sub_tb;



	reg [15:0] a;
	reg [15:0] b;
	reg add;


	wire [15:0] c;


	Add_Sub uut (
		.a(a), 
		.b(b), 
		.add(add), 
		.c(c)
	);

	initial begin

		a = 0;
		b = 0;
		add = 0;


		#100;
      a = 20;
		b = 5;
		#100;
		a = 15;
		b = 2;
		add = 1;
		#100;
		a = 20;
		b = 5;
		#100;


	end
      
endmodule