data/full_repos/permissive/479923049/cpu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/479923049/cpu.v:163: Operator CASE expects 11 bits on the Case expression, but Case expression\'s REPLICATE generates 10 bits.\n                                                              : ... In instance cpu.FSM\n   casex({state, opcode, op})\n   ^~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/479923049/cpu.v:163: Operator CASE expects 11 bits on the Case Item, but Case Item\'s REPLICATE generates 10 bits.\n                                                              : ... In instance cpu.FSM\n   casex({state, opcode, op})\n   ^~~~~\n%Error: data/full_repos/permissive/479923049/cpu.v:77: Cannot find file containing module: \'vDFFE\'\n    vDFFE #(16) instruction_register (clk, load_ir, read_data, ir_out);\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/479923049,data/full_repos/permissive/479923049/vDFFE\n             data/full_repos/permissive/479923049,data/full_repos/permissive/479923049/vDFFE.v\n             data/full_repos/permissive/479923049,data/full_repos/permissive/479923049/vDFFE.sv\n             vDFFE\n             vDFFE.v\n             vDFFE.sv\n             obj_dir/vDFFE\n             obj_dir/vDFFE.v\n             obj_dir/vDFFE.sv\n%Error: data/full_repos/permissive/479923049/cpu.v:91: Cannot find file containing module: \'datapath\'\n    datapath DP(\n    ^~~~~~~~\n%Error: data/full_repos/permissive/479923049/cpu.v:99: Cannot find file containing module: \'vDFFE\'\n    vDFFE #(9) program_counter (clk, load_pc, next_pc, PC);\n    ^~~~~\n%Error: data/full_repos/permissive/479923049/cpu.v:100: Cannot find file containing module: \'vDFFE\'\n    vDFFE #(9) data_address (clk, load_addr, datapath_out[8:0], data_addr_out);\n    ^~~~~\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module StateMachine(clk, reset, opcode, op, nsel, vsel, write, loada, loadb, shift, 
                    asel, bsel, loadc, loads, reset_pc, load_addr, load_pc, load_ir, addr_sel, mem_cmd);
    input clk;
    input reset;
    input [2:0] opcode;
    input [1:0] op;
    output reg [2:0] nsel;
    output reg [1:0] vsel, shift; 
    output reg write, loada, loadb, asel, bsel, loadc, loads; 


    output reg [1:0] mem_cmd;
    output reg reset_pc, load_addr, load_pc, load_ir, addr_sel; 

    reg [4:0] state;

    always @(posedge clk) begin 
        if (reset) begin
			state = `reset_state;
		end else begin 
			casex({state, opcode, op})
				{`reset_state, 3'bxxx, 2'bxx}:              state = `IF1_state;
                {`IF1_state, 3'bxxx, 2'bxx}:                state = `IF2_state;
                {`IF2_state, 3'bxxx, 2'bxx}:                state = `update_pc_state;
                {`update_pc_state, 3'bxxx, 2'bxx}:          state = `decode_state;

                {`decode_state, `alu_opcode, `alu_add_op}:  state = `get_A_state;
                {`decode_state, `alu_opcode, `alu_cmp_op}:  state = `get_A_state;
                {`decode_state, `alu_opcode, `alu_and_op}:  state = `get_A_state;
                {`decode_state, `alu_opcode, `alu_mvn_op}:  state = `get_B_state;
                {`decode_state, `ldr_opcode, 2'b00}:        state = `ldr_state_1;
                {`decode_state, `str_opcode, 2'b00}:        state = `str_state_1;
                

                {`ldr_state_1, 3'bxxx, 2'bxx}:              state = `ldr_state_2;
                {`ldr_state_2, 3'bxxx, 2'bxx}:              state = `ldr_state_3;                
                {`ldr_state_3, 3'bxxx, 2'bxx}:              state = `ldr_write_reg_state;
                {`ldr_write_reg_state, 3'bxxx, 2'bxx}:      state = `ldr_write_reg_state_2;
                {`ldr_write_reg_state_2, 3'bxxx, 2'bxx}:    state = `IF1_state;


                {`str_state_1, 3'bxxx, 2'bxx}:              state = `str_state_2;
                {`str_state_2, 3'bxxx, 2'bxx}:              state = `str_state_3;
                {`str_state_3, 3'bxxx, 2'bxx}:              state = `str_state_4;
                {`str_state_4, 3'bxxx, 2'bxx}:              state = `str_state_5;
                {`str_state_5, 3'bxxx, 2'bxx}:              state = `str_state_6;
                 {`str_state_6, 3'bxxx, 2'bxx}:              state = `IF1_state;


                {`decode_state, `halt_opcode, 3'b00}:       state = `halt_state;
                {`halt_state, 3'bxxx, 2'bxx}:               state = `halt_state;
                

                {`decode_state, `mov_opcode, `mov_imm_op}:  state = `write_imm_state;
                {`write_imm_state, 3'bxxx, 2'bxx}:          state = `IF1_state;


                {`decode_state, `mov_opcode, `mov_reg_op}:  state = `get_B_reg_state;
                {`get_B_reg_state, 3'bxxx, `alu_add_op}:    state = `mov_reg_state;
                {`mov_reg_state, 3'bxxx, 2'bxx}:            state = `write_reg_state;


                {`write_reg_state, 3'bxxx, 2'bxx}:          state = `IF1_state;


                {`get_A_state, 3'bxxx, 2'bxx}:              state = `get_B_state;
                {`get_B_state, 3'bxxx, `alu_add_op}:        state = `add_state;
                {`add_state, 3'bxxx, 2'bxx}:                state = `write_reg_state;


                {`get_B_state, 3'bxxx, `alu_cmp_op}:        state = `cmp_state;
                {`cmp_state, 3'bxxx, 2'bxx}:                state = `IF1_state;
                

                {`get_B_state, 3'bxxx, `alu_and_op}:        state = `and_state;
                {`and_state, 3'bxxx, 2'bxx}:                state = `write_reg_state;


                {`get_B_state, 3'bxxx, `alu_mvn_op}:        state = `mvn_state;
                {`mvn_state, 3'bxxx, 2'bxx}:                state = `write_reg_state;

                default:                                    state = 5'b11111;
            endcase
        end
    end  
    

    always @(*) begin
        case(state)
            `reset_state: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = { 
                        2'b00,
                        3'b000,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b1,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b0
                    };
            `IF1_state: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = { 
                        2'b00,
                        3'b000,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MREAD,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b1
                    };

            `IF2_state: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = { 
                        2'b00,
                        3'b000,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MREAD,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b1,
                        1'b1
                    };

            `update_pc_state: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = { 
                        2'b00,
                        3'b000,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b0
                    };

            `decode_state: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = { 
                        2'b00,
                        3'b000,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `halt_state: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = { 
                        2'b00,
                        3'b000,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `get_A_state: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = { 
                        2'b00,
                        3'b100,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `get_B_state:  {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = { 
                        2'b00,
                        3'b001,
                        1'b0,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
                    
            `get_B_reg_state: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = { 
                        2'b00,
                        3'b001,
                        1'b0,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `mov_reg_state:  {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = { 
                        2'b00,
                        3'b000,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b1,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `add_state:  {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = { 
                        2'b00,
                        3'b000,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b1,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `cmp_state:  {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = { 
                        2'b00,
                        3'b000,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b1,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };   
            `and_state:  {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = { 
                        2'b00,
                        3'b000,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b1,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };      
            `mvn_state:  {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = { 
                        2'b00,
                        3'b000,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b1,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };  
            `write_reg_state: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = { 
                        2'b11,
                        3'b010,
                        1'b1,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `write_imm_state: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = { 
                        2'b01,
                        3'b100,
                        1'b1,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `ldr_state_1: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = {
                        2'b01,
                        3'b100,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `ldr_state_2: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = {
                        2'b01,
                        3'b010,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b1,
                        1'b1,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `ldr_state_3: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = {
                        2'b00,
                        3'b100,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `ldr_write_reg_state: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = {
                        2'b00,
                        3'b010,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `ldr_write_reg_state_2: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = {
                        2'b00,
                        3'b010,
                        1'b1,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MREAD,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `str_state_1: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = {
                        2'b01,
                        3'b100,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `str_state_2: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = {
                        2'b01,
                        3'b100,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b1,
                        1'b1,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `str_state_3: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = {
                        2'b01,
                        3'b100,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `str_state_4: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = {
                        2'b01,
                        3'b010,
                        1'b0,
                        1'b0,
                        1'b1,
                        1'b1,
                        1'b0,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MWRITE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `str_state_5: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = {
                        2'b01,
                        3'b010,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b1,
                        1'b0,
                        2'b00,
                        `MWRITE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `str_state_6: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = {
                        2'b01,
                        3'b010,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b1,
                        1'b0,
                        2'b00,
                        `MWRITE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            default: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = {21{1'bx}};
        endcase
    
    
    end
endmodule
module StateMachine(clk, reset, opcode, op, nsel, vsel, write, loada, loadb, shift, 
                    asel, bsel, loadc, loads, reset_pc, load_addr, load_pc, load_ir, addr_sel, mem_cmd);

    input clk;
    input reset;
    input [2:0] opcode;
    input [1:0] op;
    output reg [2:0] nsel;
    output reg [1:0] vsel, shift; 
    output reg write, loada, loadb, asel, bsel, loadc, loads; 


    output reg [1:0] mem_cmd;
    output reg reset_pc, load_addr, load_pc, load_ir, addr_sel; 

    reg [4:0] state;

    always @(posedge clk) begin 
        if (reset) begin
			state = `reset_state;
		end else begin 
			casex({state, opcode, op})
				{`reset_state, 3'bxxx, 2'bxx}:              state = `IF1_state;
                {`IF1_state, 3'bxxx, 2'bxx}:                state = `IF2_state;
                {`IF2_state, 3'bxxx, 2'bxx}:                state = `update_pc_state;
                {`update_pc_state, 3'bxxx, 2'bxx}:          state = `decode_state;

                {`decode_state, `alu_opcode, `alu_add_op}:  state = `get_A_state;
                {`decode_state, `alu_opcode, `alu_cmp_op}:  state = `get_A_state;
                {`decode_state, `alu_opcode, `alu_and_op}:  state = `get_A_state;
                {`decode_state, `alu_opcode, `alu_mvn_op}:  state = `get_B_state;
                {`decode_state, `ldr_opcode, 2'b00}:        state = `ldr_state_1;
                {`decode_state, `str_opcode, 2'b00}:        state = `str_state_1;
                

                {`ldr_state_1, 3'bxxx, 2'bxx}:              state = `ldr_state_2;
                {`ldr_state_2, 3'bxxx, 2'bxx}:              state = `ldr_state_3;                
                {`ldr_state_3, 3'bxxx, 2'bxx}:              state = `ldr_write_reg_state;
                {`ldr_write_reg_state, 3'bxxx, 2'bxx}:      state = `ldr_write_reg_state_2;
                {`ldr_write_reg_state_2, 3'bxxx, 2'bxx}:    state = `IF1_state;


                {`str_state_1, 3'bxxx, 2'bxx}:              state = `str_state_2;
                {`str_state_2, 3'bxxx, 2'bxx}:              state = `str_state_3;
                {`str_state_3, 3'bxxx, 2'bxx}:              state = `str_state_4;
                {`str_state_4, 3'bxxx, 2'bxx}:              state = `str_state_5;
                {`str_state_5, 3'bxxx, 2'bxx}:              state = `str_state_6;
                 {`str_state_6, 3'bxxx, 2'bxx}:              state = `IF1_state;


                {`decode_state, `halt_opcode, 3'b00}:       state = `halt_state;
                {`halt_state, 3'bxxx, 2'bxx}:               state = `halt_state;
                

                {`decode_state, `mov_opcode, `mov_imm_op}:  state = `write_imm_state;
                {`write_imm_state, 3'bxxx, 2'bxx}:          state = `IF1_state;


                {`decode_state, `mov_opcode, `mov_reg_op}:  state = `get_B_reg_state;
                {`get_B_reg_state, 3'bxxx, `alu_add_op}:    state = `mov_reg_state;
                {`mov_reg_state, 3'bxxx, 2'bxx}:            state = `write_reg_state;


                {`write_reg_state, 3'bxxx, 2'bxx}:          state = `IF1_state;


                {`get_A_state, 3'bxxx, 2'bxx}:              state = `get_B_state;
                {`get_B_state, 3'bxxx, `alu_add_op}:        state = `add_state;
                {`add_state, 3'bxxx, 2'bxx}:                state = `write_reg_state;


                {`get_B_state, 3'bxxx, `alu_cmp_op}:        state = `cmp_state;
                {`cmp_state, 3'bxxx, 2'bxx}:                state = `IF1_state;
                

                {`get_B_state, 3'bxxx, `alu_and_op}:        state = `and_state;
                {`and_state, 3'bxxx, 2'bxx}:                state = `write_reg_state;


                {`get_B_state, 3'bxxx, `alu_mvn_op}:        state = `mvn_state;
                {`mvn_state, 3'bxxx, 2'bxx}:                state = `write_reg_state;

                default:                                    state = 5'b11111;
            endcase
        end
    end  
    

    always @(*) begin
        case(state)
            `reset_state: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = { 
                        2'b00,
                        3'b000,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b1,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b0
                    };
            `IF1_state: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = { 
                        2'b00,
                        3'b000,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MREAD,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b1
                    };

            `IF2_state: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = { 
                        2'b00,
                        3'b000,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MREAD,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b1,
                        1'b1
                    };

            `update_pc_state: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = { 
                        2'b00,
                        3'b000,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b0
                    };

            `decode_state: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = { 
                        2'b00,
                        3'b000,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `halt_state: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = { 
                        2'b00,
                        3'b000,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `get_A_state: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = { 
                        2'b00,
                        3'b100,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `get_B_state:  {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = { 
                        2'b00,
                        3'b001,
                        1'b0,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
                    
            `get_B_reg_state: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = { 
                        2'b00,
                        3'b001,
                        1'b0,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `mov_reg_state:  {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = { 
                        2'b00,
                        3'b000,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b1,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `add_state:  {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = { 
                        2'b00,
                        3'b000,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b1,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `cmp_state:  {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = { 
                        2'b00,
                        3'b000,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b1,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };   
            `and_state:  {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = { 
                        2'b00,
                        3'b000,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b1,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };      
            `mvn_state:  {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = { 
                        2'b00,
                        3'b000,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b1,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };  
            `write_reg_state: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = { 
                        2'b11,
                        3'b010,
                        1'b1,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `write_imm_state: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = { 
                        2'b01,
                        3'b100,
                        1'b1,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `ldr_state_1: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = {
                        2'b01,
                        3'b100,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `ldr_state_2: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = {
                        2'b01,
                        3'b010,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b1,
                        1'b1,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `ldr_state_3: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = {
                        2'b00,
                        3'b100,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `ldr_write_reg_state: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = {
                        2'b00,
                        3'b010,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `ldr_write_reg_state_2: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = {
                        2'b00,
                        3'b010,
                        1'b1,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MREAD,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `str_state_1: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = {
                        2'b01,
                        3'b100,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `str_state_2: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = {
                        2'b01,
                        3'b100,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b1,
                        1'b1,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `str_state_3: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = {
                        2'b01,
                        3'b100,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MNONE,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `str_state_4: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = {
                        2'b01,
                        3'b010,
                        1'b0,
                        1'b0,
                        1'b1,
                        1'b1,
                        1'b0,
                        1'b0,
                        1'b0,
                        2'b00,
                        `MWRITE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `str_state_5: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = {
                        2'b01,
                        3'b010,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b1,
                        1'b0,
                        2'b00,
                        `MWRITE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            `str_state_6: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = {
                        2'b01,
                        3'b010,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b1,
                        1'b0,
                        1'b1,
                        1'b0,
                        2'b00,
                        `MWRITE,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0,
                        1'b0
                    };
            default: {vsel, nsel, write, loada, loadb, asel, bsel, loadc, loads, shift, mem_cmd, reset_pc, load_addr, load_pc, load_ir, addr_sel} = {21{1'bx}};
        endcase
    
    
    end
endmodule