data/full_repos/permissive/433621701/generic_RB_array/generic_RB_array.v
data/verilator_xmls/f286a25c-41cd-4fb2-9dca-4e8b4365cf08.xml
module mux(input a, b, select, output reg out);
    always @(a or b or select)
    begin
        out = (a&~select)|(b&select);
    end
endmodule
module mux(input a, b, select, output reg out);

    always @(a or b or select)
    begin
        out = (a&~select)|(b&select);
    end
endmodule