data/full_repos/permissive/489075769/write_data.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/489075769/write_data.v:52: Multiple top level modules\n                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                       : ... Top module \'write_data_master\'\nmodule write_data_master (ACLK, ARESETn,WVALID, WREADY, i_WDATA, o_WDATA, WSTRB);\n       ^~~~~~~~~~~~~~~~~\n                                                                       : ... Top module \'write_data_slave\'\nmodule write_data_slave (ACLK, ARESETn,WVALID, WREADY, i_WDATA, o_WDATA, WSTRB);\n       ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489075769/write_data.v:1: Input/output/inout declaration not found for port: \'WVALID\'\nmodule write_data_master (ACLK, ARESETn,WVALID, WREADY, i_WDATA, o_WDATA, WSTRB);\n                                        ^~~~~~\n%Error: data/full_repos/permissive/489075769/write_data.v:1: Input/output/inout declaration not found for port: \'WSTRB\'\nmodule write_data_master (ACLK, ARESETn,WVALID, WREADY, i_WDATA, o_WDATA, WSTRB);\n                                                                          ^~~~~\n%Error: data/full_repos/permissive/489075769/write_data.v:52: Input/output/inout declaration not found for port: \'WREADY\'\nmodule write_data_slave (ACLK, ARESETn,WVALID, WREADY, i_WDATA, o_WDATA, WSTRB);\n                                               ^~~~~~\n%Error: data/full_repos/permissive/489075769/write_data.v:56: Input/output/inout does not appear in port list: \'o_WREADY\'\noutput o_WREADY;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/489075769/write_data.v:57: Input/output/inout does not appear in port list: \'i_WREADY\'\ninput i_WREADY;\n      ^~~~~~~~\n%Error: data/full_repos/permissive/489075769/write_data.v:83: Can\'t find definition of variable: \'i_WVALID\'\n                                                            : ... Suggested alternative: \'WVALID\'\nalways @(i_WVALID) begin        \n         ^~~~~~~~\n%Error: data/full_repos/permissive/489075769/write_data.v:85: Can\'t find definition of variable: \'o_WVALID\'\n                                                            : ... Suggested alternative: \'i_WVALID\'\n  o_WVALID<=1;\n  ^~~~~~~~\n%Error: data/full_repos/permissive/489075769/write_data.v:89: Can\'t find definition of variable: \'WREADY\'\n                                                            : ... Suggested alternative: \'i_WREADY\'\nif (o_WVALID && WREADY) \n                ^~~~~~\n%Error: data/full_repos/permissive/489075769/write_data.v:4: Input/output/inout does not appear in port list: \'i_WVALID\'\ninput i_WVALID;\n      ^~~~~~~~\n%Error: data/full_repos/permissive/489075769/write_data.v:5: Input/output/inout does not appear in port list: \'o_WVALID\'\noutput o_WVALID;\n       ^~~~~~~~\n%Error: data/full_repos/permissive/489075769/write_data.v:9: Input/output/inout does not appear in port list: \'i_WSTRB\'\ninput [3:0] i_WSTRB;  \n            ^~~~~~~\n%Error: data/full_repos/permissive/489075769/write_data.v:10: Input/output/inout does not appear in port list: \'o_WSTRB\'\ninput [3:0] o_WSTRB;         \n            ^~~~~~~\n%Error: data/full_repos/permissive/489075769/write_data.v:25: Can\'t find definition of variable: \'WSTRB\'\n                                                            : ... Suggested alternative: \'i_WSTRB\'\ncasex (WSTRB)\n       ^~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/489075769/write_data.v:22: Assigning to input/const variable: \'o_WSTRB\'\no_WSTRB=i_WSTRB;\n^~~~~~~\n%Error: Exiting due to 14 error(s), 1 warning(s)\n'
module write_data_master (ACLK, ARESETn,WVALID, WREADY, i_WDATA, o_WDATA, WSTRB);
input ACLK;
input ARESETn;
input i_WVALID;
output o_WVALID;
input WREADY;
input [31:0] i_WDATA;
output reg [31:0] o_WDATA;
input [3:0] i_WSTRB;  
input [3:0] o_WSTRB;         

reg [31:0] temp_WDATA;
	
	
always @(posedge ARESETn) begin
o_WDATA <= 0;
o_WVALID <=0;
end

always @(i_WSTRB) begin

o_WSTRB=i_WSTRB;

temp_WDATA=32'h0;
casex (WSTRB)
4'b1???: temp_WDATA[31:24]=8'b11111111;
4'b?1??: temp_WDATA[23:16]=8'b11111111;
4'b??1?: temp_WDATA[15:8]=8'b11111111;
4'b???1: temp_WDATA[7:0]=8'b11111111;
default:
temp_WDATA=0;
endcase
temp_WDATA=i_WDATA&temp_WDATA;
end

always @(i_WVALID) begin
		if(i_WVALID)
		o_WVALID<=1;
		end
	
always @(posedge ACLK) begin
if (o_WVALID && WREADY) 
o_WDATA <= temp_WDATA;
		
else 
o_WDATA <= 0;
end
	
endmodule
module write_data_master (ACLK, ARESETn,WVALID, WREADY, i_WDATA, o_WDATA, WSTRB);

input ACLK;
input ARESETn;
input i_WVALID;
output o_WVALID;
input WREADY;
input [31:0] i_WDATA;
output reg [31:0] o_WDATA;
input [3:0] i_WSTRB;  
input [3:0] o_WSTRB;         

reg [31:0] temp_WDATA;
	
	
always @(posedge ARESETn) begin
o_WDATA <= 0;
o_WVALID <=0;
end

always @(i_WSTRB) begin

o_WSTRB=i_WSTRB;

temp_WDATA=32'h0;
casex (WSTRB)
4'b1???: temp_WDATA[31:24]=8'b11111111;
4'b?1??: temp_WDATA[23:16]=8'b11111111;
4'b??1?: temp_WDATA[15:8]=8'b11111111;
4'b???1: temp_WDATA[7:0]=8'b11111111;
default:
temp_WDATA=0;
endcase
temp_WDATA=i_WDATA&temp_WDATA;
end

always @(i_WVALID) begin
		if(i_WVALID)
		o_WVALID<=1;
		end
	
always @(posedge ACLK) begin
if (o_WVALID && WREADY) 
o_WDATA <= temp_WDATA;
		
else 
o_WDATA <= 0;
end
	
endmodule