data/full_repos/permissive/493019833/test/testcase/firrtl/SmallOdds5/reference/SmallOdds5.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/SmallOdds5/reference/SmallOdds5.v:176: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 4 bits.\n                                                                                                               : ... In instance SmallOdds5.smalls.u_pad_1\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/SmallOdds5/reference/SmallOdds5.v:176: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                               : ... In instance SmallOdds5.odds.u_pad_35\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n%Error: Exiting due to 2 warning(s)\n'
module SmallOdds5(
    input clock,
    input reset,
    output io_in_ready,
    input io_in_valid,
    input [31:0] io_in_bits,
    input io_out_ready,
    output io_out_valid,
    output [31:0] io_out_bits
);
    wire _smalls__clock;
    wire _smalls__reset;
    wire _smalls__io_in_ready;
    wire _smalls__io_in_valid;
    wire [31:0] _smalls__io_in_bits;
    wire _smalls__io_out_ready;
    wire _smalls__io_out_valid;
    wire [31:0] _smalls__io_out_bits;
    SmallOdds5Filter smalls (
        .clock(_smalls__clock),
        .reset(_smalls__reset),
        .io_in_ready(_smalls__io_in_ready),
        .io_in_valid(_smalls__io_in_valid),
        .io_in_bits(_smalls__io_in_bits),
        .io_out_ready(_smalls__io_out_ready),
        .io_out_valid(_smalls__io_out_valid),
        .io_out_bits(_smalls__io_out_bits)
    );
    wire _q__clock;
    wire _q__reset;
    wire _q__io_enq_ready;
    wire _q__io_enq_valid;
    wire [31:0] _q__io_enq_bits;
    wire _q__io_deq_ready;
    wire _q__io_deq_valid;
    wire [31:0] _q__io_deq_bits;
    wire [1:0] _q__io_count;
    Queue q (
        .clock(_q__clock),
        .reset(_q__reset),
        .io_enq_ready(_q__io_enq_ready),
        .io_enq_valid(_q__io_enq_valid),
        .io_enq_bits(_q__io_enq_bits),
        .io_deq_ready(_q__io_deq_ready),
        .io_deq_valid(_q__io_deq_valid),
        .io_deq_bits(_q__io_deq_bits),
        .io_count(_q__io_count)
    );
    wire _odds__clock;
    wire _odds__reset;
    wire _odds__io_in_ready;
    wire _odds__io_in_valid;
    wire [31:0] _odds__io_in_bits;
    wire _odds__io_out_ready;
    wire _odds__io_out_valid;
    wire [31:0] _odds__io_out_bits;
    SmallOdds5Filter_1 odds (
        .clock(_odds__clock),
        .reset(_odds__reset),
        .io_in_ready(_odds__io_in_ready),
        .io_in_valid(_odds__io_in_valid),
        .io_in_bits(_odds__io_in_bits),
        .io_out_ready(_odds__io_out_ready),
        .io_out_valid(_odds__io_out_valid),
        .io_out_bits(_odds__io_out_bits)
    );
    assign io_in_ready = _smalls__io_in_ready;
    assign io_out_bits = _odds__io_out_bits;
    assign io_out_valid = _odds__io_out_valid;
    assign _odds__clock = clock;
    assign _odds__io_in_bits = _q__io_deq_bits;
    assign _odds__io_in_valid = _q__io_deq_valid;
    assign _odds__io_out_ready = io_out_ready;
    assign _odds__reset = reset;
    assign _q__clock = clock;
    assign _q__io_deq_ready = _odds__io_in_ready;
    assign _q__io_enq_bits = _smalls__io_out_bits;
    assign _q__io_enq_valid = _smalls__io_out_valid;
    assign _q__reset = reset;
    assign _smalls__clock = clock;
    assign _smalls__io_in_bits = io_in_bits;
    assign _smalls__io_in_valid = io_in_valid;
    assign _smalls__io_out_ready = _q__io_enq_ready;
    assign _smalls__reset = reset;
endmodule
module SmallOdds5(
    input clock,
    input reset,
    output io_in_ready,
    input io_in_valid,
    input [31:0] io_in_bits,
    input io_out_ready,
    output io_out_valid,
    output [31:0] io_out_bits
);

    wire _smalls__clock;
    wire _smalls__reset;
    wire _smalls__io_in_ready;
    wire _smalls__io_in_valid;
    wire [31:0] _smalls__io_in_bits;
    wire _smalls__io_out_ready;
    wire _smalls__io_out_valid;
    wire [31:0] _smalls__io_out_bits;
    SmallOdds5Filter smalls (
        .clock(_smalls__clock),
        .reset(_smalls__reset),
        .io_in_ready(_smalls__io_in_ready),
        .io_in_valid(_smalls__io_in_valid),
        .io_in_bits(_smalls__io_in_bits),
        .io_out_ready(_smalls__io_out_ready),
        .io_out_valid(_smalls__io_out_valid),
        .io_out_bits(_smalls__io_out_bits)
    );
    wire _q__clock;
    wire _q__reset;
    wire _q__io_enq_ready;
    wire _q__io_enq_valid;
    wire [31:0] _q__io_enq_bits;
    wire _q__io_deq_ready;
    wire _q__io_deq_valid;
    wire [31:0] _q__io_deq_bits;
    wire [1:0] _q__io_count;
    Queue q (
        .clock(_q__clock),
        .reset(_q__reset),
        .io_enq_ready(_q__io_enq_ready),
        .io_enq_valid(_q__io_enq_valid),
        .io_enq_bits(_q__io_enq_bits),
        .io_deq_ready(_q__io_deq_ready),
        .io_deq_valid(_q__io_deq_valid),
        .io_deq_bits(_q__io_deq_bits),
        .io_count(_q__io_count)
    );
    wire _odds__clock;
    wire _odds__reset;
    wire _odds__io_in_ready;
    wire _odds__io_in_valid;
    wire [31:0] _odds__io_in_bits;
    wire _odds__io_out_ready;
    wire _odds__io_out_valid;
    wire [31:0] _odds__io_out_bits;
    SmallOdds5Filter_1 odds (
        .clock(_odds__clock),
        .reset(_odds__reset),
        .io_in_ready(_odds__io_in_ready),
        .io_in_valid(_odds__io_in_valid),
        .io_in_bits(_odds__io_in_bits),
        .io_out_ready(_odds__io_out_ready),
        .io_out_valid(_odds__io_out_valid),
        .io_out_bits(_odds__io_out_bits)
    );
    assign io_in_ready = _smalls__io_in_ready;
    assign io_out_bits = _odds__io_out_bits;
    assign io_out_valid = _odds__io_out_valid;
    assign _odds__clock = clock;
    assign _odds__io_in_bits = _q__io_deq_bits;
    assign _odds__io_in_valid = _q__io_deq_valid;
    assign _odds__io_out_ready = io_out_ready;
    assign _odds__reset = reset;
    assign _q__clock = clock;
    assign _q__io_deq_ready = _odds__io_in_ready;
    assign _q__io_enq_bits = _smalls__io_out_bits;
    assign _q__io_enq_valid = _smalls__io_out_valid;
    assign _q__reset = reset;
    assign _smalls__clock = clock;
    assign _smalls__io_in_bits = io_in_bits;
    assign _smalls__io_in_valid = io_in_valid;
    assign _smalls__io_out_ready = _q__io_enq_ready;
    assign _smalls__reset = reset;
endmodule