data/full_repos/permissive/509335294/alusrcmux.v
data/verilator_xmls/f5a51b24-098d-4eeb-a0ce-d64195a52f2e.xml
module alusrcmux(	input[15:0] rd2,sign_ext_line,
								input sel,
								output reg[15:0] alusrcmux_out_ALU_in2
								);

always@(*)begin
	case(sel)
	1'b0 : alusrcmux_out_ALU_in2 <= rd2;
	1'b1 : alusrcmux_out_ALU_in2 <= sign_ext_line;
	endcase
end

endmodule
module alusrcmux(	input[15:0] rd2,sign_ext_line,
								input sel,
								output reg[15:0] alusrcmux_out_ALU_in2
								);


always@(*)begin
	case(sel)
	1'b0 : alusrcmux_out_ALU_in2 <= rd2;
	1'b1 : alusrcmux_out_ALU_in2 <= sign_ext_line;
	endcase
end

endmodule