data/full_repos/permissive/475231219/BabyRuner/andgate.v
data/verilator_xmls/855f0a8d-95e8-4853-9fdb-5683b3e64d43.xml
module top_module( 
    input a, 
    input b, 
    output out );
	assign out = a & b;


endmodule
module top_module( 
    input a, 
    input b, 
    output out );

	assign out = a & b;


endmodule