data/full_repos/permissive/418749135/jk_ff_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/418749135/jk_ff_tb.v:6: Unsupported: Ignoring delay on this delayed statement.\n   always #5 clk = ~clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/418749135/jk_ff_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n      #5 j <= 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/418749135/jk_ff_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n      #20 j <= 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/418749135/jk_ff_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n      #20 j <= 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/418749135/jk_ff_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n      #20 $finish;\n      ^\n%Error: data/full_repos/permissive/418749135/jk_ff_tb.v:27: Unsupported or unknown PLI call: $monitor\n      $monitor ("j=%0d k=%0d q=%0d", j, k, q);\n      ^~~~~~~~\n%Error: data/full_repos/permissive/418749135/jk_ff_tb.v:31: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("dump.vcd"); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/418749135/jk_ff_tb.v:32: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_jk;
   reg j;
   reg k;
   reg clk;

   always #5 clk = ~clk;

   jk_ff    jk0 ( .j(j),
                  .k(k),
                  .clk(clk),
                  .q(q));

   initial begin
      j <= 0;
      k <= 0;

      #5 j <= 0;
         k <= 1;
      #20 j <= 1;
          k <= 0;
      #20 j <= 1;
          k <= 1;
      #20 $finish;
   end

   initial begin
      $monitor ("j=%0d k=%0d q=%0d", j, k, q);
   end

initial begin
	$dumpfile("dump.vcd"); 
	$dumpvars;
	
	end
endmodule
module tb_jk;

   reg j;
   reg k;
   reg clk;

   always #5 clk = ~clk;

   jk_ff    jk0 ( .j(j),
                  .k(k),
                  .clk(clk),
                  .q(q));

   initial begin
      j <= 0;
      k <= 0;

      #5 j <= 0;
         k <= 1;
      #20 j <= 1;
          k <= 0;
      #20 j <= 1;
          k <= 1;
      #20 $finish;
   end

   initial begin
      $monitor ("j=%0d k=%0d q=%0d", j, k, q);
   end

initial begin
	$dumpfile("dump.vcd"); 
	$dumpvars;
	
	end
endmodule