data/full_repos/permissive/425166201/04_pong/de0.v
1: b"%Error: data/full_repos/permissive/425166201/04_pong/de0.v:83: Cannot find file containing module: 'de0pll'\nde0pll unit_pll\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/425166201/04_pong,data/full_repos/permissive/425166201/de0pll\n             data/full_repos/permissive/425166201/04_pong,data/full_repos/permissive/425166201/de0pll.v\n             data/full_repos/permissive/425166201/04_pong,data/full_repos/permissive/425166201/de0pll.sv\n             de0pll\n             de0pll.v\n             de0pll.sv\n             obj_dir/de0pll\n             obj_dir/de0pll.v\n             obj_dir/de0pll.sv\n%Error: data/full_repos/permissive/425166201/04_pong/de0.v:91: Cannot find file containing module: 'adapter'\nadapter DSUBAdapter\n^~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module de0(


    input              RESET_N,


    input              CLOCK_50,
    input              CLOCK2_50,
    input              CLOCK3_50,
    inout              CLOCK4_50,


    output             DRAM_CKE,
    output             DRAM_CLK,
    output      [1:0]  DRAM_BA,
    output      [12:0] DRAM_ADDR,
    inout       [15:0] DRAM_DQ,
    output             DRAM_CAS_N,
    output             DRAM_RAS_N,
    output             DRAM_WE_N,
    output             DRAM_CS_N,
    output             DRAM_LDQM,
    output             DRAM_UDQM,


    inout       [35:0] GPIO_0,
    inout       [35:0] GPIO_1,


    output      [6:0]  HEX0,
    output      [6:0]  HEX1,
    output      [6:0]  HEX2,
    output      [6:0]  HEX3,
    output      [6:0]  HEX4,
    output      [6:0]  HEX5,


    input       [3:0]  KEY,


    output      [9:0]  LEDR,


    inout              PS2_CLK,
    inout              PS2_DAT,
    inout              PS2_CLK2,
    inout              PS2_DAT2,


    output             SD_CLK,
    inout              SD_CMD,
    inout       [3:0]  SD_DATA,


    input       [9:0]  SW,


    output      [3:0]  VGA_R,
    output      [3:0]  VGA_G,
    output      [3:0]  VGA_B,
    output             VGA_HS,
    output             VGA_VS
);


assign DRAM_DQ = 16'hzzzz;
assign GPIO_0  = 36'hzzzzzzzz;
assign GPIO_1  = 36'hzzzzzzzz;


assign HEX0 = 7'b1111111;
assign HEX1 = 7'b1111111;
assign HEX2 = 7'b1111111;
assign HEX3 = 7'b1111111;
assign HEX4 = 7'b1111111;
assign HEX5 = 7'b1111111;


wire locked;
wire clock_25;
wire clock_106;

de0pll unit_pll
(
    .clkin     (CLOCK_50),
    .m25       (clock_25),
    .m106      (clock_106),
    .locked    (locked)
);

adapter DSUBAdapter
(
    .CLOCK  (clock_25),
    .VGA_R  (VGA_R),
    .VGA_G  (VGA_G),
    .VGA_B  (VGA_B),
    .VGA_HS (VGA_HS),
    .VGA_VS (VGA_VS),
    .KEY    (KEY)
);

endmodule
module de0(


    input              RESET_N,


    input              CLOCK_50,
    input              CLOCK2_50,
    input              CLOCK3_50,
    inout              CLOCK4_50,


    output             DRAM_CKE,
    output             DRAM_CLK,
    output      [1:0]  DRAM_BA,
    output      [12:0] DRAM_ADDR,
    inout       [15:0] DRAM_DQ,
    output             DRAM_CAS_N,
    output             DRAM_RAS_N,
    output             DRAM_WE_N,
    output             DRAM_CS_N,
    output             DRAM_LDQM,
    output             DRAM_UDQM,


    inout       [35:0] GPIO_0,
    inout       [35:0] GPIO_1,


    output      [6:0]  HEX0,
    output      [6:0]  HEX1,
    output      [6:0]  HEX2,
    output      [6:0]  HEX3,
    output      [6:0]  HEX4,
    output      [6:0]  HEX5,


    input       [3:0]  KEY,


    output      [9:0]  LEDR,


    inout              PS2_CLK,
    inout              PS2_DAT,
    inout              PS2_CLK2,
    inout              PS2_DAT2,


    output             SD_CLK,
    inout              SD_CMD,
    inout       [3:0]  SD_DATA,


    input       [9:0]  SW,


    output      [3:0]  VGA_R,
    output      [3:0]  VGA_G,
    output      [3:0]  VGA_B,
    output             VGA_HS,
    output             VGA_VS
);



assign DRAM_DQ = 16'hzzzz;
assign GPIO_0  = 36'hzzzzzzzz;
assign GPIO_1  = 36'hzzzzzzzz;


assign HEX0 = 7'b1111111;
assign HEX1 = 7'b1111111;
assign HEX2 = 7'b1111111;
assign HEX3 = 7'b1111111;
assign HEX4 = 7'b1111111;
assign HEX5 = 7'b1111111;


wire locked;
wire clock_25;
wire clock_106;

de0pll unit_pll
(
    .clkin     (CLOCK_50),
    .m25       (clock_25),
    .m106      (clock_106),
    .locked    (locked)
);

adapter DSUBAdapter
(
    .CLOCK  (clock_25),
    .VGA_R  (VGA_R),
    .VGA_G  (VGA_G),
    .VGA_B  (VGA_B),
    .VGA_HS (VGA_HS),
    .VGA_VS (VGA_VS),
    .KEY    (KEY)
);

endmodule