data/full_repos/permissive/417288846/List_1/Task_1/JK_latch.v
data/verilator_xmls/b67a8e9c-17d2-48b4-a686-700d01dd3610.xml
module d_latch(input d, clk, output q, nq);
    wire na1, na2, na3, na4;

    nand (na1, na4, na2);
    nand (na2, na1, clk);
    nand (na3, na2, clk, na4);
    nand (na4, na3, d);
    nand (q, na2, nq);
    nand (nq, na3, q);
endmodule
module d_latch(input d, clk, output q, nq);

    wire na1, na2, na3, na4;

    nand (na1, na4, na2);
    nand (na2, na1, clk);
    nand (na3, na2, clk, na4);
    nand (na4, na3, d);
    nand (q, na2, nq);
    nand (nq, na3, q);
endmodule