data/full_repos/permissive/451577625/system/reducer_64.v
1: b'%Error: data/full_repos/permissive/451577625/system/reducer_64.v:14: Cannot find file containing module: \'reducer_4_to_2\'\n    reducer_4_to_2 reducer(.in_w (in_w[i]),\n    ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/reducer_4_to_2\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/reducer_4_to_2.v\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/reducer_4_to_2.sv\n             reducer_4_to_2\n             reducer_4_to_2.v\n             reducer_4_to_2.sv\n             obj_dir/reducer_4_to_2\n             obj_dir/reducer_4_to_2.v\n             obj_dir/reducer_4_to_2.sv\n%Warning-WIDTH: data/full_repos/permissive/451577625/system/reducer_64.v:49: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h3b9aca00\' generates 32 bits.\n                                                                           : ... In instance reducer_64_tb\n  w = 32\'h3B9ACA00; x = 32\'h3B9ACA00; y = 32\'h4C4B40; z = 32\'h4C4B40; cin = 1\'b0;   \n    ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/451577625/system/reducer_64.v:49: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h3b9aca00\' generates 32 bits.\n                                                                           : ... In instance reducer_64_tb\n  w = 32\'h3B9ACA00; x = 32\'h3B9ACA00; y = 32\'h4C4B40; z = 32\'h4C4B40; cin = 1\'b0;   \n                      ^\n%Warning-WIDTH: data/full_repos/permissive/451577625/system/reducer_64.v:49: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h4c4b40\' generates 32 bits.\n                                                                           : ... In instance reducer_64_tb\n  w = 32\'h3B9ACA00; x = 32\'h3B9ACA00; y = 32\'h4C4B40; z = 32\'h4C4B40; cin = 1\'b0;   \n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/451577625/system/reducer_64.v:49: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h4c4b40\' generates 32 bits.\n                                                                           : ... In instance reducer_64_tb\n  w = 32\'h3B9ACA00; x = 32\'h3B9ACA00; y = 32\'h4C4B40; z = 32\'h4C4B40; cin = 1\'b0;   \n                                                        ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n'
module reducer_64_tb;

	reg [63:0] w, x, y, z;
	reg cin;
	
	wire [63:0] sum, carry;
	wire cout;
	
	parameter delay = 10;
	
	reducer_64 DUT (.in_w(w),
		.in_x (x),
		.in_y (y),
		.in_z (z),
		.in_cin (cin),
		.out_sum (sum),
		.out_carry (carry),
		.out_cout (cout));
	
	initial begin
		w = 32'h3B9ACA00; x = 32'h3B9ACA00; y = 32'h4C4B40; z = 32'h4C4B40; cin = 1'b0;
	end

endmodule
module reducer_64_tb;


	reg [63:0] w, x, y, z;
	reg cin;
	
	wire [63:0] sum, carry;
	wire cout;
	
	parameter delay = 10;
	
	reducer_64 DUT (.in_w(w),
		.in_x (x),
		.in_y (y),
		.in_z (z),
		.in_cin (cin),
		.out_sum (sum),
		.out_carry (carry),
		.out_cout (cout));
	
	initial begin
		w = 32'h3B9ACA00; x = 32'h3B9ACA00; y = 32'h4C4B40; z = 32'h4C4B40; cin = 1'b0;
	end

endmodule