data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/rtlacksyn.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/rtlacksyn.v:44: Cannot find file containing module: 'fflopx'\nfflopx #(4) iupack_shift (clk,rst,{upack_shift[2:0],eupack},upack_shift[3:0]);\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/fflopx\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/fflopx.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp,data/full_repos/permissive/530013823/fflopx.sv\n             fflopx\n             fflopx.v\n             fflopx.sv\n             obj_dir/fflopx\n             obj_dir/fflopx.v\n             obj_dir/fflopx.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/rtlacksyn.v:49: Cannot find file containing module: 'fflopx'\nfflopx #(1) iuprdy (clk,rst,uprdy0,uprdy);\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/rtlacksyn.v:52: Cannot find file containing module: 'fflopx'\nfflopx #(WID) ppeupdo (clk,rst,eupdo,eupdo1);\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/rtlacksyn.v:53: Cannot find file containing module: 'fflopx'\nfflopx #(WID) ppeupdo1 (clk,rst,eupdo1,updo);\n^~~~~~\n%Error: Exiting due to 4 error(s)\n"
module rtlacksyn
    (clk,
     rst,
     eupack,
     eupdo,
     uprdy,
     updo
     );



parameter   WID = 32;










input               clk,
                    rst;
input               eupack;
input [WID-1:0]     eupdo;
output              uprdy;
output [WID-1:0]    updo;

wire [3:0]           upack_shift;   
fflopx #(4) iupack_shift (clk,rst,{upack_shift[2:0],eupack},upack_shift[3:0]);

wire                 uprdy0; 
assign               uprdy0 = (upack_shift[3:2] == 2'b01);

fflopx #(1) iuprdy (clk,rst,uprdy0,uprdy);

wire [WID-1:0] eupdo1;
fflopx #(WID) ppeupdo (clk,rst,eupdo,eupdo1);
fflopx #(WID) ppeupdo1 (clk,rst,eupdo1,updo);

endmodule
module rtlacksyn
    (clk,
     rst,
     eupack,
     eupdo,
     uprdy,
     updo
     );




parameter   WID = 32;










input               clk,
                    rst;
input               eupack;
input [WID-1:0]     eupdo;
output              uprdy;
output [WID-1:0]    updo;

wire [3:0]           upack_shift;   
fflopx #(4) iupack_shift (clk,rst,{upack_shift[2:0],eupack},upack_shift[3:0]);

wire                 uprdy0; 
assign               uprdy0 = (upack_shift[3:2] == 2'b01);

fflopx #(1) iuprdy (clk,rst,uprdy0,uprdy);

wire [WID-1:0] eupdo1;
fflopx #(WID) ppeupdo (clk,rst,eupdo,eupdo1);
fflopx #(WID) ppeupdo1 (clk,rst,eupdo1,updo);

endmodule