data/full_repos/permissive/496266817/tb/tb_block_mix_new.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/496266817/tb/tb_block_mix_new.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #(HALF_PERIOD_CLOCK) clk <= ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/496266817/tb/tb_block_mix_new.v:74: Unsupported: Ignoring delay on this delayed statement.\n   #(HALF_PERIOD_CLOCK*2*num_delay)  reset_n <= 1\'b1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/496266817/tb/tb_block_mix_new.v:75: Unsupported: Ignoring delay on this delayed statement.\n   #(HALF_PERIOD_CLOCK*2)    init <= 1\'b1;\n   ^\n%Error: data/full_repos/permissive/496266817/tb/tb_block_mix_new.v:22: Cannot find file containing module: \'blockmix_dpct\'\n blockmix_dpct bm1 (\n ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/496266817/tb,data/full_repos/permissive/496266817/blockmix_dpct\n             data/full_repos/permissive/496266817/tb,data/full_repos/permissive/496266817/blockmix_dpct.v\n             data/full_repos/permissive/496266817/tb,data/full_repos/permissive/496266817/blockmix_dpct.sv\n             blockmix_dpct\n             blockmix_dpct.v\n             blockmix_dpct.sv\n             obj_dir/blockmix_dpct\n             obj_dir/blockmix_dpct.v\n             obj_dir/blockmix_dpct.sv\n%Error: data/full_repos/permissive/496266817/tb/tb_block_mix_new.v:31: Cannot find file containing module: \'blockmix_dpct_new\'\n    blockmix_dpct_new bm2 (\n    ^~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/496266817/tb/tb_block_mix_new.v:52: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s TIME generates 64 bits.\n                                                                             : ... In instance tb_block_mix_new\n   i = $time;\n     ^\n%Warning-WIDTH: data/full_repos/permissive/496266817/tb/tb_block_mix_new.v:57: Operator SUB expects 64 bits on the RHS, but RHS\'s VARREF \'start_time\' generates 32 bits.\n                                                                             : ... In instance tb_block_mix_new\n   $display("Output new block mix: %x cycle: %f", new_out, ($time-start_time)/(HALF_PERIOD_CLOCK*2));\n                                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/496266817/tb/tb_block_mix_new.v:76: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s TIME generates 64 bits.\n                                                                             : ... In instance tb_block_mix_new\n   start_time = $time;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/496266817/tb/tb_block_mix_new.v:83: Operator TASKREF \'reset_task\' expects 8 bits on the Function Argument, but Function Argument\'s CONST \'3\'h5\' generates 3 bits.\n                                                                             : ... In instance tb_block_mix_new\n  reset_task(3\'d5);\n  ^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_block_mix_new();
		reg				clk			;
		reg				init		;
		reg				reset_n		;
		reg		[1023:0]in			;




		wire			valid		;
		wire			new_valid	;
        

		
		parameter HALF_PERIOD_CLOCK = 10;
		

	wire [1023: 0] out;
	wire [1023: 0] new_out;
	
	blockmix_dpct bm1	(
		.clk	(clk)		,
		.init	(init)		,
		.reset_n(reset_n)	,
		.in		(in)		,
		.out	(out)		,
		.valid	(valid)
	);
    
    blockmix_dpct_new bm2	(
		.clk	(clk)		,
		.init	(init)		,
		.reset_n(reset_n)	,
		.in		(in)		,
		.out	(new_out)	,
		.valid	(new_valid)
	);
	
	

	integer i;
	integer start_time;
	integer check = 1;
	always @(*) 
	begin: clock_generator
		#(HALF_PERIOD_CLOCK) clk <= ~clk;
	end
	always @(clk, valid, new_valid) 
	begin
		if(valid == 1'd1 && check == 1) begin
			i = $time;
			check = 0;
		end
		if(valid == 1'd1 && new_valid == 1'd1) begin
			$display("Output old block mix: %x cycle: %f", out, (i-start_time)/(HALF_PERIOD_CLOCK*2));
			$display("Output new block mix: %x cycle: %f", new_out, ($time-start_time)/(HALF_PERIOD_CLOCK*2));
			$display("Test completed, time: %t!", $time);
			$stop;
		end
	end
	task init_task();
		begin
			clk  	= 1'b0;
			init 	= 1'b0;
			reset_n = 1'b0;

			in		= 1024'h264b5f120a5cd734959837046aac499cba1701807e78a726a1ebcacc144a50c86788331394f1a4ebad038f73e3fe594fcfa6a26fb841b099dd2aafaf38859bc3820ac6670d9a31f29eaa2a983c594cdfdddee8091612d0815203b64de5e40141fcc6127093a003dfb3b58c5280617a72f6653bc9a91110dbc99abeb4d0d4a3d0;			
		end
	endtask
	
	task reset_task (input reg[7:0] num_delay);
		begin
			#(HALF_PERIOD_CLOCK*2*num_delay) 	reset_n <= 1'b1;
			#(HALF_PERIOD_CLOCK*2)				init <= 1'b1;
			start_time = $time;
		end
	endtask
	
	initial begin: main_test
		$display("Test starts!");
		init_task();
		reset_task(3'd5);
	end
		
endmodule
module tb_block_mix_new();

		reg				clk			;
		reg				init		;
		reg				reset_n		;
		reg		[1023:0]in			;




		wire			valid		;
		wire			new_valid	;
        

		
		parameter HALF_PERIOD_CLOCK = 10;
		

	wire [1023: 0] out;
	wire [1023: 0] new_out;
	
	blockmix_dpct bm1	(
		.clk	(clk)		,
		.init	(init)		,
		.reset_n(reset_n)	,
		.in		(in)		,
		.out	(out)		,
		.valid	(valid)
	);
    
    blockmix_dpct_new bm2	(
		.clk	(clk)		,
		.init	(init)		,
		.reset_n(reset_n)	,
		.in		(in)		,
		.out	(new_out)	,
		.valid	(new_valid)
	);
	
	

	integer i;
	integer start_time;
	integer check = 1;
	always @(*) 
	begin: clock_generator
		#(HALF_PERIOD_CLOCK) clk <= ~clk;
	end
	always @(clk, valid, new_valid) 
	begin
		if(valid == 1'd1 && check == 1) begin
			i = $time;
			check = 0;
		end
		if(valid == 1'd1 && new_valid == 1'd1) begin
			$display("Output old block mix: %x cycle: %f", out, (i-start_time)/(HALF_PERIOD_CLOCK*2));
			$display("Output new block mix: %x cycle: %f", new_out, ($time-start_time)/(HALF_PERIOD_CLOCK*2));
			$display("Test completed, time: %t!", $time);
			$stop;
		end
	end
	task init_task();
		begin
			clk  	= 1'b0;
			init 	= 1'b0;
			reset_n = 1'b0;

			in		= 1024'h264b5f120a5cd734959837046aac499cba1701807e78a726a1ebcacc144a50c86788331394f1a4ebad038f73e3fe594fcfa6a26fb841b099dd2aafaf38859bc3820ac6670d9a31f29eaa2a983c594cdfdddee8091612d0815203b64de5e40141fcc6127093a003dfb3b58c5280617a72f6653bc9a91110dbc99abeb4d0d4a3d0;			
		end
	endtask
	
	task reset_task (input reg[7:0] num_delay);
		begin
			#(HALF_PERIOD_CLOCK*2*num_delay) 	reset_n <= 1'b1;
			#(HALF_PERIOD_CLOCK*2)				init <= 1'b1;
			start_time = $time;
		end
	endtask
	
	initial begin: main_test
		$display("Test starts!");
		init_task();
		reset_task(3'd5);
	end
		
endmodule