data/full_repos/permissive/468929885/verilog/rtl/el_sync.v
data/verilator_xmls/96e0e8a2-aab8-4cea-bee4-3c3590a8ec49.xml
module el_sync
(

	input							rst,
	input							clk,

	input [1:0]						in_async,
	input							in_ack,

	output							out_sync

);

reg [1:0] sync;

reg [1:0] ack_dly;

always@(posedge clk)
begin
	if(rst)
	begin
		ack_dly <= 0;
	end
	ack_dly[0] <= in_ack;
	ack_dly[1] <= ack_dly[0];
end


always@(posedge clk)
begin
	if(rst)
	begin
		sync <= 0;
	end
	else if(ack_dly[1] ^^ ack_dly[0])
	begin
		sync <= {sync[0],in_async[1]};
	end
end

assign out_sync = ^sync;

endmodule
module el_sync
(

	input							rst,
	input							clk,

	input [1:0]						in_async,
	input							in_ack,

	output							out_sync

);


reg [1:0] sync;

reg [1:0] ack_dly;

always@(posedge clk)
begin
	if(rst)
	begin
		ack_dly <= 0;
	end
	ack_dly[0] <= in_ack;
	ack_dly[1] <= ack_dly[0];
end


always@(posedge clk)
begin
	if(rst)
	begin
		sync <= 0;
	end
	else if(ack_dly[1] ^^ ack_dly[0])
	begin
		sync <= {sync[0],in_async[1]};
	end
end

assign out_sync = ^sync;

endmodule