data/full_repos/permissive/517390617/modules/jt51/ver/jt51_pg_meas/jt51_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/517390617/modules/jt51/ver/jt51_pg_meas/jt51_test.v:37: Unsupported: Ignoring delay on this delayed statement.\n forever #140 clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/517390617/modules/jt51/ver/jt51_pg_meas/jt51_test.v:42: Unsupported: Ignoring delay on this delayed statement.\n #20 rst = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/517390617/modules/jt51/ver/jt51_pg_meas/jt51_test.v:43: Unsupported: Ignoring delay on this delayed statement.\n #300 rst = 0;\n ^\n%Error: data/full_repos/permissive/517390617/modules/jt51/ver/jt51_pg_meas/jt51_test.v:116: Cannot find file containing module: \'jt51_pg\'\njt51_pg u_uut(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/517390617/modules/jt51/ver/jt51_pg_meas,data/full_repos/permissive/517390617/jt51_pg\n             data/full_repos/permissive/517390617/modules/jt51/ver/jt51_pg_meas,data/full_repos/permissive/517390617/jt51_pg.v\n             data/full_repos/permissive/517390617/modules/jt51/ver/jt51_pg_meas,data/full_repos/permissive/517390617/jt51_pg.sv\n             jt51_pg\n             jt51_pg.v\n             jt51_pg.sv\n             obj_dir/jt51_pg\n             obj_dir/jt51_pg.v\n             obj_dir/jt51_pg.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module jt51_test;

reg clk;
reg	rst;

reg	[6:0]	kc;
reg	[5:0]	kf;

reg	[3:0]	mul;

reg	[2:0]	dt1;
reg	[1:0]	dt2;

reg	signed	[7:0]	pm;
reg	[2:0]	pms;


wire	[ 4:0]	keycode_III;

`ifndef LFO_PM
	`define LFO_PM 0
`endif
`ifndef LFP_PMS
	`define LFP_PMS 0
`endif

initial begin
	clk = 0;
	forever #140 clk = ~clk;
end

initial begin
	rst = 0;
	#20 rst = 1;
	#300 rst = 0;
    $display("DUMP START");
end

`ifdef LFO_TEST
reg fin;

always @(posedge clk  ) begin
	if( rst ) begin
		kc <= { 3'd3, 4'd4 };
		kf <= 6'd0;
		dt2<= 2'd0;
		dt1<= 3'd0;
		mul<= 4'd1;
		pm <= 0;
		pms<= 3'd1;
        fin<=1'b0;
	end
	else begin
		{ fin,pms, pm } <= {fin,pms,pm} + 1'd1;
		if( fin ) begin
        	#(280*7) $display("DUMP END");
            $finish;
        end
	end
end
`endif

`ifdef LFO_FULL_TEST
reg fin;

always @(posedge clk or posedge rst ) begin
	if( rst ) begin
		kc <= 7'd0;
		kf <= 6'd0;
		dt2<= 2'd0;
		dt1<= 3'd0;
		mul<= 4'd1;
		pm <= 0;
		pms<= 3'd1;
        fin<=1'b0;
	end
	else begin
		{ fin,pms, kc, kf, pm } <= {fin,pms, kc, kf, pm} + 1'd1;
		if( fin ) begin
        	#(280*7) $display("DUMP END");
            $finish;
        end
	end
end
`endif

`ifdef KC_TEST
always @(posedge clk or posedge rst ) begin
	if( rst ) begin
		kc <= 7'd0;
		kf <= 6'd0;
		dt2<= 2'd0;
		dt1<= 3'd0;
		mul<= 4'd1;
		pm <= `LFO_PM;
		pms<= `LFO_PMS;
	end
	else begin
		{ dt2, dt1, kc, kf } <= { dt2, dt1, kc, kf } + 1'd1;
		if( &{ dt2, dt1, kc, kf }==1'b1 ) begin
        	#(280*7) $display("DUMP END");
            $finish;
        end
	end
end
`endif

jt51_pg u_uut(
	.clk(clk),
	.cen(1'b1),

	.kc_I(kc),
	.kf_I(kf),

	.mul_VI(mul),

	.dt1_II(dt1),
	.dt2_I(dt2),

	.pm(pm),
	.pms_I(pms),

	.pg_rst_III(1'b0),

	.pg_phase_X( )
);

initial begin
`ifdef DUMPSIGNALS
	`ifdef NCVERILOG
		$shm_open("jt51_test.shm");
		$shm_probe(jt51_test,"AS");
	`else
		$dumpfile("jt51_test.lxt");
		$dumpvars();
		$dumpon;
	`endif
	#(280*10000) $finish;
`endif
end

endmodule
module jt51_test;


reg clk;
reg	rst;

reg	[6:0]	kc;
reg	[5:0]	kf;

reg	[3:0]	mul;

reg	[2:0]	dt1;
reg	[1:0]	dt2;

reg	signed	[7:0]	pm;
reg	[2:0]	pms;


wire	[ 4:0]	keycode_III;

`ifndef LFO_PM
	`define LFO_PM 0
`endif
`ifndef LFP_PMS
	`define LFP_PMS 0
`endif

initial begin
	clk = 0;
	forever #140 clk = ~clk;
end

initial begin
	rst = 0;
	#20 rst = 1;
	#300 rst = 0;
    $display("DUMP START");
end

`ifdef LFO_TEST
reg fin;

always @(posedge clk  ) begin
	if( rst ) begin
		kc <= { 3'd3, 4'd4 };
		kf <= 6'd0;
		dt2<= 2'd0;
		dt1<= 3'd0;
		mul<= 4'd1;
		pm <= 0;
		pms<= 3'd1;
        fin<=1'b0;
	end
	else begin
		{ fin,pms, pm } <= {fin,pms,pm} + 1'd1;
		if( fin ) begin
        	#(280*7) $display("DUMP END");
            $finish;
        end
	end
end
`endif

`ifdef LFO_FULL_TEST
reg fin;

always @(posedge clk or posedge rst ) begin
	if( rst ) begin
		kc <= 7'd0;
		kf <= 6'd0;
		dt2<= 2'd0;
		dt1<= 3'd0;
		mul<= 4'd1;
		pm <= 0;
		pms<= 3'd1;
        fin<=1'b0;
	end
	else begin
		{ fin,pms, kc, kf, pm } <= {fin,pms, kc, kf, pm} + 1'd1;
		if( fin ) begin
        	#(280*7) $display("DUMP END");
            $finish;
        end
	end
end
`endif

`ifdef KC_TEST
always @(posedge clk or posedge rst ) begin
	if( rst ) begin
		kc <= 7'd0;
		kf <= 6'd0;
		dt2<= 2'd0;
		dt1<= 3'd0;
		mul<= 4'd1;
		pm <= `LFO_PM;
		pms<= `LFO_PMS;
	end
	else begin
		{ dt2, dt1, kc, kf } <= { dt2, dt1, kc, kf } + 1'd1;
		if( &{ dt2, dt1, kc, kf }==1'b1 ) begin
        	#(280*7) $display("DUMP END");
            $finish;
        end
	end
end
`endif

jt51_pg u_uut(
	.clk(clk),
	.cen(1'b1),

	.kc_I(kc),
	.kf_I(kf),

	.mul_VI(mul),

	.dt1_II(dt1),
	.dt2_I(dt2),

	.pm(pm),
	.pms_I(pms),

	.pg_rst_III(1'b0),

	.pg_phase_X( )
);

initial begin
`ifdef DUMPSIGNALS
	`ifdef NCVERILOG
		$shm_open("jt51_test.shm");
		$shm_probe(jt51_test,"AS");
	`else
		$dumpfile("jt51_test.lxt");
		$dumpvars();
		$dumpon;
	`endif
	#(280*10000) $finish;
`endif
end

endmodule