data/full_repos/permissive/528912093/Proiect/fullAdder.v
1: b"%Error: data/full_repos/permissive/528912093/Proiect/fullAdder.v:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final\n wire w5,w6,w7,w8,;\n                  ^\n%Error: data/full_repos/permissive/528912093/Proiect/fullAdder.v:18: syntax error, unexpected always\nalways\n^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module fullAdder( C,B,A,Sum,Carry);
 input C,B,A;
 output Sum,Carry;
 wire w5,w6,w7,w8,;
 xor #(18) xor2_1(w5,A,B);
 or #(3) or2_2(w6,A,B);
 or #(3) or2_3(Carry,w7,w8);
 xor #(18) xor2_4(Sum,w5,C);
 and #(3) and2_5(w7,B,A);
 and #(3) and2_6(w8,C,w6);
endmodule
module fullAdder( C,B,A,Sum,Carry);

 input C,B,A;
 output Sum,Carry;
 wire w5,w6,w7,w8,;
 xor #(18) xor2_1(w5,A,B);
 or #(3) or2_2(w6,A,B);
 or #(3) or2_3(Carry,w7,w8);
 xor #(18) xor2_4(Sum,w5,C);
 and #(3) and2_5(w7,B,A);
 and #(3) and2_6(w8,C,w6);
endmodule