data/full_repos/permissive/418753087/smart_run/logical/apb/apb.v
1: b"%Error: data/full_repos/permissive/418753087/smart_run/logical/apb/apb.v:172: Cannot find file containing module: 'apb_bridge'\napb_bridge  x_apb_bridge (\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418753087/smart_run/logical/apb,data/full_repos/permissive/418753087/apb_bridge\n             data/full_repos/permissive/418753087/smart_run/logical/apb,data/full_repos/permissive/418753087/apb_bridge.v\n             data/full_repos/permissive/418753087/smart_run/logical/apb,data/full_repos/permissive/418753087/apb_bridge.sv\n             apb_bridge\n             apb_bridge.v\n             apb_bridge.sv\n             obj_dir/apb_bridge\n             obj_dir/apb_bridge.v\n             obj_dir/apb_bridge.sv\n%Error: data/full_repos/permissive/418753087/smart_run/logical/apb/apb.v:237: Cannot find file containing module: 'pmu'\npmu  x_pmu (\n^~~\n%Error: data/full_repos/permissive/418753087/smart_run/logical/apb/apb.v:282: Cannot find file containing module: 'uart'\nuart  x_uart (\n^~~~\n%Error: data/full_repos/permissive/418753087/smart_run/logical/apb/apb.v:311: Cannot find file containing module: 'timer'\ntimer  x_timer (\n^~~~~\n%Error: data/full_repos/permissive/418753087/smart_run/logical/apb/apb.v:336: Cannot find file containing module: 'timer'\ntimer  x_stimer (\n^~~~~\n%Error: data/full_repos/permissive/418753087/smart_run/logical/apb/apb.v:361: Cannot find file containing module: 'timer'\ntimer  x_nmi_wake (\n^~~~~\n%Error: data/full_repos/permissive/418753087/smart_run/logical/apb/apb.v:397: Cannot find file containing module: 'clk_aligner'\nclk_aligner  x_clk_aligner (\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/418753087/smart_run/logical/apb/apb.v:443: Cannot find file containing module: 'clk_divider'\nclk_divider  x_clk_divider (\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/418753087/smart_run/logical/apb/apb.v:471: Cannot find file containing module: 'gpio'\ngpio  x_gpio (\n^~~~\n%Error: data/full_repos/permissive/418753087/smart_run/logical/apb/apb.v:499: Cannot find file containing module: 'smpu_top'\nsmpu_top  x_smpu_top (\n^~~~~~~~\n%Error: data/full_repos/permissive/418753087/smart_run/logical/apb/apb.v:527: Cannot find file containing module: 'wic_top'\nwic_top  x_wic_top (\n^~~~~~~\n%Error: Exiting due to 11 error(s)\n"
module apb(
  b_pad_gpio_porta,
  biu_pad_lpmd_b,
  clk_en,
  corec_pmu_sleep_out,
  cpu_clk,
  fifo_pad_haddr,
  fifo_pad_hprot,
  haddr_s2,
  hrdata_s2,
  hready_s2,
  hresp_s2,
  hsel_s2,
  hwdata_s2,
  hwrite_s2,
  i_pad_cpu_jtg_rst_b,
  i_pad_jtg_tclk,
  nmi_req,
  pad_clk,
  pad_cpu_rst_b,
  pad_had_jtg_tap_en,
  pad_had_jtg_tms_i,
  pad_had_jtg_trst_b,
  pad_had_jtg_trst_b_pre,
  pad_vic_int_vld,
  per_clk,
  pg_reset_b,
  pmu_corec_isolation,
  pmu_corec_sleep_in,
  smpu_deny,
  sys_rst,
  uart0_sin,
  uart0_sout,
  wakeup_req
);


input   [1 :0]  biu_pad_lpmd_b;        
input           corec_pmu_sleep_out;   
input   [31:0]  fifo_pad_haddr;        
input   [3 :0]  fifo_pad_hprot;        
input   [31:0]  haddr_s2;              
input           hsel_s2;               
input   [31:0]  hwdata_s2;             
input           hwrite_s2;             
input           i_pad_cpu_jtg_rst_b;   
input           i_pad_jtg_tclk;        
input           pad_clk;               
input           pad_cpu_rst_b;         
input           pad_had_jtg_tap_en;    
input           pad_had_jtg_tms_i;     
input           pad_had_jtg_trst_b_pre; 
input           sys_rst;               
input           uart0_sin;             
output          clk_en;                
output          cpu_clk;               
output  [31:0]  hrdata_s2;             
output          hready_s2;             
output  [1 :0]  hresp_s2;              
output          nmi_req;               
output          pad_had_jtg_trst_b;    
output  [31:0]  pad_vic_int_vld;       
output          per_clk;               
output          pg_reset_b;            
output          pmu_corec_isolation;   
output          pmu_corec_sleep_in;    
output          smpu_deny;             
output          uart0_sout;            
output          wakeup_req;            
inout   [7 :0]  b_pad_gpio_porta;      




wire            apb_clkgen_psel;       
wire            apb_gpio_psel;         
wire            apb_nmi_wake_psel;     
wire            apb_pmu_psel;          
wire            apb_smpu_psel;         
wire            apb_stim_psel;         
wire            apb_tim_psel;          
wire            apb_uart_psel;         
wire    [31:0]  apb_xx_paddr;          
wire            apb_xx_penable;        
wire    [31:0]  apb_xx_pwdata;         
wire            apb_xx_pwrite;         
wire    [7 :0]  b_pad_gpio_porta;      
wire    [1 :0]  biu_pad_lpmd_b;        
wire            clk_div_1;             
wire            clk_div_2;             
wire            clk_div_3;             
wire            clk_div_4;             
wire            clk_div_5;             
wire            clk_div_6;             
wire            clk_div_7;             
wire            clk_div_8;             
wire            clk_en;                
wire            clk_en_1;              
wire            clk_en_2;              
wire            clk_en_3;              
wire            clk_en_4;              
wire            clk_en_5;              
wire            clk_en_6;              
wire            clk_en_7;              
wire            clk_en_8;              
wire    [31:0]  clkgen_apb_prdata;     
wire            corec_pmu_sleep_out;   
wire            cpu_clk;               
wire    [31:0]  fifo_pad_haddr;        
wire    [3 :0]  fifo_pad_hprot;        
wire            gate_en0;              
wire            gate_en1;              
wire    [31:0]  gpio_apb_prdata;       
wire    [7 :0]  gpio_vic_int;          
wire    [31:0]  haddr_s2;              
wire    [31:0]  hrdata_s2;             
wire            hready_s2;             
wire    [1 :0]  hresp_s2;              
wire            hsel_s2;               
wire    [31:0]  hwdata_s2;             
wire            hwrite_s2;             
wire            i_pad_cpu_jtg_rst_b;   
wire            i_pad_jtg_tclk;        
wire            intraw_vld;            
wire            nmi_req;               
wire    [31:0]  nmi_wake_apb_prdata;   
wire    [3 :0]  nmi_wake_int;          
wire            pad_clk;               
wire            pad_cpu_rst_b;         
wire            pad_had_jtg_tap_en;    
wire            pad_had_jtg_tms_i;     
wire            pad_had_jtg_trst_b;    
wire            pad_had_jtg_trst_b_pre; 
wire    [31:0]  pad_vic_int_vld;       
wire            per_clk;               
wire            pg_reset_b;            
wire    [31:0]  pmu_apb_prdata;        
wire            pmu_clk;               
wire            pmu_corec_isolation;   
wire            pmu_corec_sleep_in;    
wire    [31:0]  smpu_apb_prdata;       
wire            smpu_deny;             
wire    [31:0]  stim_apb_prdata;       
wire    [3 :0]  stim_vic_int;          
wire            sys_rst;               
wire    [31:0]  tim_apb_prdata;        
wire    [3 :0]  tim_vic_int;           
wire            uart0_sin;             
wire            uart0_sout;            
wire            uart0_vic_int;         
wire    [31:0]  uart_apb_prdata;       
wire            wakeup_req;            
wire            wic_clk;               




apb_bridge  x_apb_bridge (
  .apb_harb_hrdata     (hrdata_s2          ),
  .apb_harb_hready     (hready_s2          ),
  .apb_harb_hresp      (hresp_s2           ),
  .apb_xx_paddr        (apb_xx_paddr       ),
  .apb_xx_penable      (apb_xx_penable     ),
  .apb_xx_pwdata       (apb_xx_pwdata      ),
  .apb_xx_pwrite       (apb_xx_pwrite      ),
  .harb_apb_hsel       (hsel_s2            ),
  .harb_xx_haddr       (haddr_s2           ),
  .harb_xx_hwdata      (hwdata_s2          ),
  .harb_xx_hwrite      (hwrite_s2          ),
  .hclk                (per_clk            ),
  .hrst_b              (pg_reset_b         ),
  .prdata_s1           (uart_apb_prdata    ),
  .prdata_s2           (tim_apb_prdata     ),
  .prdata_s3           (pmu_apb_prdata     ),
  .prdata_s4           (gpio_apb_prdata    ),
  .prdata_s5           (stim_apb_prdata    ),
  .prdata_s6           (clkgen_apb_prdata  ),
  .prdata_s7           (smpu_apb_prdata    ),
  .prdata_s8           (nmi_wake_apb_prdata),
  .psel_s1             (apb_uart_psel      ),
  .psel_s2             (apb_tim_psel       ),
  .psel_s3             (apb_pmu_psel       ),
  .psel_s4             (apb_gpio_psel      ),
  .psel_s5             (apb_stim_psel      ),
  .psel_s6             (apb_clkgen_psel    ),
  .psel_s7             (apb_smpu_psel      ),
  .psel_s8             (apb_nmi_wake_psel  )
);


































pmu  x_pmu (
  .apb_pmu_paddr          (apb_xx_paddr[11:0]    ),
  .apb_pmu_penable        (apb_xx_penable        ),
  .apb_pmu_psel           (apb_pmu_psel          ),
  .apb_pmu_pwdata         (apb_xx_pwdata         ),
  .apb_pmu_pwrite         (apb_xx_pwrite         ),
  .biu_pad_lpmd_b         (biu_pad_lpmd_b        ),
  .corec_pmu_sleep_out    (corec_pmu_sleep_out   ),
  .cpu_clk                (cpu_clk               ),
  .gate_en0               (gate_en0              ),
  .gate_en1               (gate_en1              ),
  .had_pad_wakeup_req_b   (1'b1                  ),
  .i_pad_cpu_jtg_rst_b    (i_pad_cpu_jtg_rst_b   ),
  .i_pad_jtg_tclk         (i_pad_jtg_tclk        ),
  .intraw_vld             (intraw_vld            ),
  .pad_cpu_rst_b          (pad_cpu_rst_b         ),
  .pad_had_jtg_tap_en     (pad_had_jtg_tap_en    ),
  .pad_had_jtg_tms_i      (pad_had_jtg_tms_i     ),
  .pad_had_jtg_trst_b     (pad_had_jtg_trst_b    ),
  .pad_had_jtg_trst_b_pre (pad_had_jtg_trst_b_pre),
  .pg_reset_b             (pg_reset_b            ),
  .pmu_apb_prdata         (pmu_apb_prdata        ),
  .pmu_clk                (pmu_clk               ),
  .pmu_corec_isolation    (pmu_corec_isolation   ),
  .pmu_corec_sleep_in     (pmu_corec_sleep_in    ),
  .sys_rst                (sys_rst               )
);


















uart  x_uart (
  .apb_uart_paddr   (apb_xx_paddr    ),
  .apb_uart_penable (apb_xx_penable  ),
  .apb_uart_psel    (apb_uart_psel   ),
  .apb_uart_pwdata  (apb_xx_pwdata   ),
  .apb_uart_pwrite  (apb_xx_pwrite   ),
  .rst_b            (pad_cpu_rst_b   ),
  .s_in             (uart0_sin       ),
  .s_out            (uart0_sout      ),
  .sys_clk          (pmu_clk         ),
  .uart_apb_prdata  (uart_apb_prdata ),
  .uart_vic_int     (uart0_vic_int   )
);
















timer  x_timer (
  .paddr              (apb_xx_paddr[15:0]),
  .pclk               (pmu_clk           ),
  .penable            (apb_xx_penable    ),
  .prdata             (tim_apb_prdata    ),
  .presetn            (pad_cpu_rst_b     ),
  .psel               (apb_tim_psel      ),
  .pwdata             (apb_xx_pwdata     ),
  .pwrite             (apb_xx_pwrite     ),
  .timer_int          (tim_vic_int       )
);














timer  x_stimer (
  .paddr              (apb_xx_paddr[15:0]),
  .pclk               (pmu_clk           ),
  .penable            (apb_xx_penable    ),
  .prdata             (stim_apb_prdata   ),
  .presetn            (pad_cpu_rst_b     ),
  .psel               (apb_stim_psel     ),
  .pwdata             (apb_xx_pwdata     ),
  .pwrite             (apb_xx_pwrite     ),
  .timer_int          (stim_vic_int      )
);














timer  x_nmi_wake (
  .paddr               (apb_xx_paddr[15:0] ),
  .pclk                (pmu_clk            ),
  .penable             (apb_xx_penable     ),
  .prdata              (nmi_wake_apb_prdata),
  .presetn             (pad_cpu_rst_b      ),
  .psel                (apb_nmi_wake_psel  ),
  .pwdata              (apb_xx_pwdata      ),
  .pwrite              (apb_xx_pwrite      ),
  .timer_int           (nmi_wake_int       )
);












assign nmi_req = nmi_wake_int[0];
assign wakeup_req = nmi_wake_int[1];











clk_aligner  x_clk_aligner (
  .clk_div_1          (clk_div_1         ),
  .clk_div_2          (clk_div_2         ),
  .clk_div_3          (clk_div_3         ),
  .clk_div_4          (clk_div_4         ),
  .clk_div_5          (clk_div_5         ),
  .clk_div_6          (clk_div_6         ),
  .clk_div_7          (clk_div_7         ),
  .clk_div_8          (clk_div_8         ),
  .clk_en             (clk_en            ),
  .clk_en_1           (clk_en_1          ),
  .clk_en_2           (clk_en_2          ),
  .clk_en_3           (clk_en_3          ),
  .clk_en_4           (clk_en_4          ),
  .clk_en_5           (clk_en_5          ),
  .clk_en_6           (clk_en_6          ),
  .clk_en_7           (clk_en_7          ),
  .clk_en_8           (clk_en_8          ),
  .clkrst_b           (pad_cpu_rst_b     ),
  .cpu_clk            (cpu_clk           ),
  .forever_cpuclk     (pad_clk           ),
  .gate_en0           (gate_en0          ),
  .gate_en1           (gate_en1          ),
  .paddr              (apb_xx_paddr[11:0]),
  .penable            (apb_xx_penable    ),
  .per_clk            (per_clk           ),
  .pmu_clk            (pmu_clk           ),
  .prdata             (clkgen_apb_prdata ),
  .psel               (apb_clkgen_psel   ),
  .pwdata             (apb_xx_pwdata[2:0]),
  .pwrite             (apb_xx_pwrite     ),
  .wic_clk            (wic_clk           )
);













clk_divider  x_clk_divider (
  .clk_div_1     (clk_div_1    ),
  .clk_div_2     (clk_div_2    ),
  .clk_div_3     (clk_div_3    ),
  .clk_div_4     (clk_div_4    ),
  .clk_div_5     (clk_div_5    ),
  .clk_div_6     (clk_div_6    ),
  .clk_div_7     (clk_div_7    ),
  .clk_div_8     (clk_div_8    ),
  .clk_en_1      (clk_en_1     ),
  .clk_en_2      (clk_en_2     ),
  .clk_en_3      (clk_en_3     ),
  .clk_en_4      (clk_en_4     ),
  .clk_en_5      (clk_en_5     ),
  .clk_en_6      (clk_en_6     ),
  .clk_en_7      (clk_en_7     ),
  .clk_en_8      (clk_en_8     ),
  .osc_clk       (pad_clk      ),
  .pad_cpu_rst_b (pad_cpu_rst_b)
);








gpio  x_gpio (
  .b_pad_gpio_porta  (b_pad_gpio_porta ),
  .gpio_intr         (gpio_vic_int     ),
  .paddr             (apb_xx_paddr[6:2]),
  .pclk              (pmu_clk          ),
  .pclk_intr         (pmu_clk          ),
  .penable           (apb_xx_penable   ),
  .prdata            (gpio_apb_prdata  ),
  .presetn           (pad_cpu_rst_b    ),
  .psel              (apb_gpio_psel    ),
  .pwdata            (apb_xx_pwdata    ),
  .pwrite            (apb_xx_pwrite    )
);















smpu_top  x_smpu_top (
  .biu_pad_haddr     (fifo_pad_haddr   ),
  .biu_pad_hprot     (fifo_pad_hprot   ),
  .paddr             (apb_xx_paddr[3:2]),
  .pclk              (per_clk          ),
  .penable           (apb_xx_penable   ),
  .prdata            (smpu_apb_prdata  ),
  .presetn           (pg_reset_b       ),
  .psel              (apb_smpu_psel    ),
  .pwdata            (apb_xx_pwdata    ),
  .pwrite            (apb_xx_pwrite    ),
  .smpu_deny         (smpu_deny        )
);















wic_top  x_wic_top (
  .ctl_xx_awake_enable (32'hffffffff       ),
  .gpio_vic_int        (gpio_vic_int       ),
  .intraw_vld          (intraw_vld         ),
  .pad_cpu_rst_b       (pad_cpu_rst_b      ),
  .pad_vic_int_vld     (pad_vic_int_vld    ),
  .pulse_int           (1'b0               ),
  .stim_vic_int        (stim_vic_int       ),
  .tim_vic_int         (tim_vic_int        ),
  .uart0_vic_int       (uart0_vic_int      ),
  .wic_clk             (wic_clk            )
);






















endmodule
module apb(
  b_pad_gpio_porta,
  biu_pad_lpmd_b,
  clk_en,
  corec_pmu_sleep_out,
  cpu_clk,
  fifo_pad_haddr,
  fifo_pad_hprot,
  haddr_s2,
  hrdata_s2,
  hready_s2,
  hresp_s2,
  hsel_s2,
  hwdata_s2,
  hwrite_s2,
  i_pad_cpu_jtg_rst_b,
  i_pad_jtg_tclk,
  nmi_req,
  pad_clk,
  pad_cpu_rst_b,
  pad_had_jtg_tap_en,
  pad_had_jtg_tms_i,
  pad_had_jtg_trst_b,
  pad_had_jtg_trst_b_pre,
  pad_vic_int_vld,
  per_clk,
  pg_reset_b,
  pmu_corec_isolation,
  pmu_corec_sleep_in,
  smpu_deny,
  sys_rst,
  uart0_sin,
  uart0_sout,
  wakeup_req
);



input   [1 :0]  biu_pad_lpmd_b;        
input           corec_pmu_sleep_out;   
input   [31:0]  fifo_pad_haddr;        
input   [3 :0]  fifo_pad_hprot;        
input   [31:0]  haddr_s2;              
input           hsel_s2;               
input   [31:0]  hwdata_s2;             
input           hwrite_s2;             
input           i_pad_cpu_jtg_rst_b;   
input           i_pad_jtg_tclk;        
input           pad_clk;               
input           pad_cpu_rst_b;         
input           pad_had_jtg_tap_en;    
input           pad_had_jtg_tms_i;     
input           pad_had_jtg_trst_b_pre; 
input           sys_rst;               
input           uart0_sin;             
output          clk_en;                
output          cpu_clk;               
output  [31:0]  hrdata_s2;             
output          hready_s2;             
output  [1 :0]  hresp_s2;              
output          nmi_req;               
output          pad_had_jtg_trst_b;    
output  [31:0]  pad_vic_int_vld;       
output          per_clk;               
output          pg_reset_b;            
output          pmu_corec_isolation;   
output          pmu_corec_sleep_in;    
output          smpu_deny;             
output          uart0_sout;            
output          wakeup_req;            
inout   [7 :0]  b_pad_gpio_porta;      




wire            apb_clkgen_psel;       
wire            apb_gpio_psel;         
wire            apb_nmi_wake_psel;     
wire            apb_pmu_psel;          
wire            apb_smpu_psel;         
wire            apb_stim_psel;         
wire            apb_tim_psel;          
wire            apb_uart_psel;         
wire    [31:0]  apb_xx_paddr;          
wire            apb_xx_penable;        
wire    [31:0]  apb_xx_pwdata;         
wire            apb_xx_pwrite;         
wire    [7 :0]  b_pad_gpio_porta;      
wire    [1 :0]  biu_pad_lpmd_b;        
wire            clk_div_1;             
wire            clk_div_2;             
wire            clk_div_3;             
wire            clk_div_4;             
wire            clk_div_5;             
wire            clk_div_6;             
wire            clk_div_7;             
wire            clk_div_8;             
wire            clk_en;                
wire            clk_en_1;              
wire            clk_en_2;              
wire            clk_en_3;              
wire            clk_en_4;              
wire            clk_en_5;              
wire            clk_en_6;              
wire            clk_en_7;              
wire            clk_en_8;              
wire    [31:0]  clkgen_apb_prdata;     
wire            corec_pmu_sleep_out;   
wire            cpu_clk;               
wire    [31:0]  fifo_pad_haddr;        
wire    [3 :0]  fifo_pad_hprot;        
wire            gate_en0;              
wire            gate_en1;              
wire    [31:0]  gpio_apb_prdata;       
wire    [7 :0]  gpio_vic_int;          
wire    [31:0]  haddr_s2;              
wire    [31:0]  hrdata_s2;             
wire            hready_s2;             
wire    [1 :0]  hresp_s2;              
wire            hsel_s2;               
wire    [31:0]  hwdata_s2;             
wire            hwrite_s2;             
wire            i_pad_cpu_jtg_rst_b;   
wire            i_pad_jtg_tclk;        
wire            intraw_vld;            
wire            nmi_req;               
wire    [31:0]  nmi_wake_apb_prdata;   
wire    [3 :0]  nmi_wake_int;          
wire            pad_clk;               
wire            pad_cpu_rst_b;         
wire            pad_had_jtg_tap_en;    
wire            pad_had_jtg_tms_i;     
wire            pad_had_jtg_trst_b;    
wire            pad_had_jtg_trst_b_pre; 
wire    [31:0]  pad_vic_int_vld;       
wire            per_clk;               
wire            pg_reset_b;            
wire    [31:0]  pmu_apb_prdata;        
wire            pmu_clk;               
wire            pmu_corec_isolation;   
wire            pmu_corec_sleep_in;    
wire    [31:0]  smpu_apb_prdata;       
wire            smpu_deny;             
wire    [31:0]  stim_apb_prdata;       
wire    [3 :0]  stim_vic_int;          
wire            sys_rst;               
wire    [31:0]  tim_apb_prdata;        
wire    [3 :0]  tim_vic_int;           
wire            uart0_sin;             
wire            uart0_sout;            
wire            uart0_vic_int;         
wire    [31:0]  uart_apb_prdata;       
wire            wakeup_req;            
wire            wic_clk;               




apb_bridge  x_apb_bridge (
  .apb_harb_hrdata     (hrdata_s2          ),
  .apb_harb_hready     (hready_s2          ),
  .apb_harb_hresp      (hresp_s2           ),
  .apb_xx_paddr        (apb_xx_paddr       ),
  .apb_xx_penable      (apb_xx_penable     ),
  .apb_xx_pwdata       (apb_xx_pwdata      ),
  .apb_xx_pwrite       (apb_xx_pwrite      ),
  .harb_apb_hsel       (hsel_s2            ),
  .harb_xx_haddr       (haddr_s2           ),
  .harb_xx_hwdata      (hwdata_s2          ),
  .harb_xx_hwrite      (hwrite_s2          ),
  .hclk                (per_clk            ),
  .hrst_b              (pg_reset_b         ),
  .prdata_s1           (uart_apb_prdata    ),
  .prdata_s2           (tim_apb_prdata     ),
  .prdata_s3           (pmu_apb_prdata     ),
  .prdata_s4           (gpio_apb_prdata    ),
  .prdata_s5           (stim_apb_prdata    ),
  .prdata_s6           (clkgen_apb_prdata  ),
  .prdata_s7           (smpu_apb_prdata    ),
  .prdata_s8           (nmi_wake_apb_prdata),
  .psel_s1             (apb_uart_psel      ),
  .psel_s2             (apb_tim_psel       ),
  .psel_s3             (apb_pmu_psel       ),
  .psel_s4             (apb_gpio_psel      ),
  .psel_s5             (apb_stim_psel      ),
  .psel_s6             (apb_clkgen_psel    ),
  .psel_s7             (apb_smpu_psel      ),
  .psel_s8             (apb_nmi_wake_psel  )
);


































pmu  x_pmu (
  .apb_pmu_paddr          (apb_xx_paddr[11:0]    ),
  .apb_pmu_penable        (apb_xx_penable        ),
  .apb_pmu_psel           (apb_pmu_psel          ),
  .apb_pmu_pwdata         (apb_xx_pwdata         ),
  .apb_pmu_pwrite         (apb_xx_pwrite         ),
  .biu_pad_lpmd_b         (biu_pad_lpmd_b        ),
  .corec_pmu_sleep_out    (corec_pmu_sleep_out   ),
  .cpu_clk                (cpu_clk               ),
  .gate_en0               (gate_en0              ),
  .gate_en1               (gate_en1              ),
  .had_pad_wakeup_req_b   (1'b1                  ),
  .i_pad_cpu_jtg_rst_b    (i_pad_cpu_jtg_rst_b   ),
  .i_pad_jtg_tclk         (i_pad_jtg_tclk        ),
  .intraw_vld             (intraw_vld            ),
  .pad_cpu_rst_b          (pad_cpu_rst_b         ),
  .pad_had_jtg_tap_en     (pad_had_jtg_tap_en    ),
  .pad_had_jtg_tms_i      (pad_had_jtg_tms_i     ),
  .pad_had_jtg_trst_b     (pad_had_jtg_trst_b    ),
  .pad_had_jtg_trst_b_pre (pad_had_jtg_trst_b_pre),
  .pg_reset_b             (pg_reset_b            ),
  .pmu_apb_prdata         (pmu_apb_prdata        ),
  .pmu_clk                (pmu_clk               ),
  .pmu_corec_isolation    (pmu_corec_isolation   ),
  .pmu_corec_sleep_in     (pmu_corec_sleep_in    ),
  .sys_rst                (sys_rst               )
);


















uart  x_uart (
  .apb_uart_paddr   (apb_xx_paddr    ),
  .apb_uart_penable (apb_xx_penable  ),
  .apb_uart_psel    (apb_uart_psel   ),
  .apb_uart_pwdata  (apb_xx_pwdata   ),
  .apb_uart_pwrite  (apb_xx_pwrite   ),
  .rst_b            (pad_cpu_rst_b   ),
  .s_in             (uart0_sin       ),
  .s_out            (uart0_sout      ),
  .sys_clk          (pmu_clk         ),
  .uart_apb_prdata  (uart_apb_prdata ),
  .uart_vic_int     (uart0_vic_int   )
);
















timer  x_timer (
  .paddr              (apb_xx_paddr[15:0]),
  .pclk               (pmu_clk           ),
  .penable            (apb_xx_penable    ),
  .prdata             (tim_apb_prdata    ),
  .presetn            (pad_cpu_rst_b     ),
  .psel               (apb_tim_psel      ),
  .pwdata             (apb_xx_pwdata     ),
  .pwrite             (apb_xx_pwrite     ),
  .timer_int          (tim_vic_int       )
);














timer  x_stimer (
  .paddr              (apb_xx_paddr[15:0]),
  .pclk               (pmu_clk           ),
  .penable            (apb_xx_penable    ),
  .prdata             (stim_apb_prdata   ),
  .presetn            (pad_cpu_rst_b     ),
  .psel               (apb_stim_psel     ),
  .pwdata             (apb_xx_pwdata     ),
  .pwrite             (apb_xx_pwrite     ),
  .timer_int          (stim_vic_int      )
);














timer  x_nmi_wake (
  .paddr               (apb_xx_paddr[15:0] ),
  .pclk                (pmu_clk            ),
  .penable             (apb_xx_penable     ),
  .prdata              (nmi_wake_apb_prdata),
  .presetn             (pad_cpu_rst_b      ),
  .psel                (apb_nmi_wake_psel  ),
  .pwdata              (apb_xx_pwdata      ),
  .pwrite              (apb_xx_pwrite      ),
  .timer_int           (nmi_wake_int       )
);












assign nmi_req = nmi_wake_int[0];
assign wakeup_req = nmi_wake_int[1];











clk_aligner  x_clk_aligner (
  .clk_div_1          (clk_div_1         ),
  .clk_div_2          (clk_div_2         ),
  .clk_div_3          (clk_div_3         ),
  .clk_div_4          (clk_div_4         ),
  .clk_div_5          (clk_div_5         ),
  .clk_div_6          (clk_div_6         ),
  .clk_div_7          (clk_div_7         ),
  .clk_div_8          (clk_div_8         ),
  .clk_en             (clk_en            ),
  .clk_en_1           (clk_en_1          ),
  .clk_en_2           (clk_en_2          ),
  .clk_en_3           (clk_en_3          ),
  .clk_en_4           (clk_en_4          ),
  .clk_en_5           (clk_en_5          ),
  .clk_en_6           (clk_en_6          ),
  .clk_en_7           (clk_en_7          ),
  .clk_en_8           (clk_en_8          ),
  .clkrst_b           (pad_cpu_rst_b     ),
  .cpu_clk            (cpu_clk           ),
  .forever_cpuclk     (pad_clk           ),
  .gate_en0           (gate_en0          ),
  .gate_en1           (gate_en1          ),
  .paddr              (apb_xx_paddr[11:0]),
  .penable            (apb_xx_penable    ),
  .per_clk            (per_clk           ),
  .pmu_clk            (pmu_clk           ),
  .prdata             (clkgen_apb_prdata ),
  .psel               (apb_clkgen_psel   ),
  .pwdata             (apb_xx_pwdata[2:0]),
  .pwrite             (apb_xx_pwrite     ),
  .wic_clk            (wic_clk           )
);













clk_divider  x_clk_divider (
  .clk_div_1     (clk_div_1    ),
  .clk_div_2     (clk_div_2    ),
  .clk_div_3     (clk_div_3    ),
  .clk_div_4     (clk_div_4    ),
  .clk_div_5     (clk_div_5    ),
  .clk_div_6     (clk_div_6    ),
  .clk_div_7     (clk_div_7    ),
  .clk_div_8     (clk_div_8    ),
  .clk_en_1      (clk_en_1     ),
  .clk_en_2      (clk_en_2     ),
  .clk_en_3      (clk_en_3     ),
  .clk_en_4      (clk_en_4     ),
  .clk_en_5      (clk_en_5     ),
  .clk_en_6      (clk_en_6     ),
  .clk_en_7      (clk_en_7     ),
  .clk_en_8      (clk_en_8     ),
  .osc_clk       (pad_clk      ),
  .pad_cpu_rst_b (pad_cpu_rst_b)
);








gpio  x_gpio (
  .b_pad_gpio_porta  (b_pad_gpio_porta ),
  .gpio_intr         (gpio_vic_int     ),
  .paddr             (apb_xx_paddr[6:2]),
  .pclk              (pmu_clk          ),
  .pclk_intr         (pmu_clk          ),
  .penable           (apb_xx_penable   ),
  .prdata            (gpio_apb_prdata  ),
  .presetn           (pad_cpu_rst_b    ),
  .psel              (apb_gpio_psel    ),
  .pwdata            (apb_xx_pwdata    ),
  .pwrite            (apb_xx_pwrite    )
);















smpu_top  x_smpu_top (
  .biu_pad_haddr     (fifo_pad_haddr   ),
  .biu_pad_hprot     (fifo_pad_hprot   ),
  .paddr             (apb_xx_paddr[3:2]),
  .pclk              (per_clk          ),
  .penable           (apb_xx_penable   ),
  .prdata            (smpu_apb_prdata  ),
  .presetn           (pg_reset_b       ),
  .psel              (apb_smpu_psel    ),
  .pwdata            (apb_xx_pwdata    ),
  .pwrite            (apb_xx_pwrite    ),
  .smpu_deny         (smpu_deny        )
);















wic_top  x_wic_top (
  .ctl_xx_awake_enable (32'hffffffff       ),
  .gpio_vic_int        (gpio_vic_int       ),
  .intraw_vld          (intraw_vld         ),
  .pad_cpu_rst_b       (pad_cpu_rst_b      ),
  .pad_vic_int_vld     (pad_vic_int_vld    ),
  .pulse_int           (1'b0               ),
  .stim_vic_int        (stim_vic_int       ),
  .tim_vic_int         (tim_vic_int        ),
  .uart0_vic_int       (uart0_vic_int      ),
  .wic_clk             (wic_clk            )
);






















endmodule