data/full_repos/permissive/467394306/rtl/pe_lin.sv
1: b"%Error: data/full_repos/permissive/467394306/rtl/pe_lin.sv:18: Duplicate declaration of signal: 'o1'\n                                                             : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n wire[11:0] o1, o2, o3, o4;\n            ^~\n        data/full_repos/permissive/467394306/rtl/pe_lin.sv:10: ... Location of original declaration\n output[11:0] o1,\n              ^~\n%Error: data/full_repos/permissive/467394306/rtl/pe_lin.sv:18: Duplicate declaration of signal: 'o2'\n wire[11:0] o1, o2, o3, o4;\n                ^~\n        data/full_repos/permissive/467394306/rtl/pe_lin.sv:11: ... Location of original declaration\n output[11:0] o2,\n              ^~\n%Error: data/full_repos/permissive/467394306/rtl/pe_lin.sv:18: Duplicate declaration of signal: 'o3'\n wire[11:0] o1, o2, o3, o4;\n                    ^~\n        data/full_repos/permissive/467394306/rtl/pe_lin.sv:12: ... Location of original declaration\n output[11:0] o3,\n              ^~\n%Error: data/full_repos/permissive/467394306/rtl/pe_lin.sv:18: Duplicate declaration of signal: 'o4'\n wire[11:0] o1, o2, o3, o4;\n                        ^~\n        data/full_repos/permissive/467394306/rtl/pe_lin.sv:13: ... Location of original declaration\n output[11:0] o4\n              ^~\n%Error: Exiting due to 4 error(s)\n"
module PE_Lin(
	input clk,
	input rstn,
	input fire,
	input[7:0] in_w1,
	input[7:0] in_w2,
	input[7:0] in_w3,
	input[7:0] in_w4,
	input[7:0] in_a,
	output[11:0] o1,
	output[11:0] o2,
	output[11:0] o3,
	output[11:0] o4
	);

	wire fo1, fo2, fo3, fo4;
	wire[7:0] ao1, ao2, ao3, ao4;
	wire[11:0] o1, o2, o3, o4;
	
	PE PE1 (clk, rstn, fire, in_w1, in_a, fo1, ao1, o1);
	PE PE2 (clk, rstn, fo1, in_w2, ao1, fo2, ao2, o2);
	PE PE3 (clk, rstn, fo2, in_w3, ao2, fo3, ao3, o3);
	PE PE4 (clk, rstn, fo3, in_w4, ao3, fo4, ao4, o4);

endmodule
module PE_Lin(
	input clk,
	input rstn,
	input fire,
	input[7:0] in_w1,
	input[7:0] in_w2,
	input[7:0] in_w3,
	input[7:0] in_w4,
	input[7:0] in_a,
	output[11:0] o1,
	output[11:0] o2,
	output[11:0] o3,
	output[11:0] o4
	);


	wire fo1, fo2, fo3, fo4;
	wire[7:0] ao1, ao2, ao3, ao4;
	wire[11:0] o1, o2, o3, o4;
	
	PE PE1 (clk, rstn, fire, in_w1, in_a, fo1, ao1, o1);
	PE PE2 (clk, rstn, fo1, in_w2, ao1, fo2, ao2, o2);
	PE PE3 (clk, rstn, fo2, in_w3, ao2, fo3, ao3, o3);
	PE PE4 (clk, rstn, fo3, in_w4, ao3, fo4, ao4, o4);

endmodule