data/full_repos/permissive/511902453/alu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/511902453/alu.v:117: Operator ADD expects 33 bits on the RHS, but RHS\'s VARREF \'cin\' generates 1 bits.\n                                                              : ... In instance alu.adder\n    assign {add_carry,add_result}=a+b+cin;\n                                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/511902453/alu.v:94: Operator SUB expects 6 bits on the RHS, but RHS\'s VARREF \'shiftctr\' generates 2 bits.\n                                                             : ... In instance alu.shifter\n  assign shift_n = 6\'d32 - shiftctr;\n                         ^\n%Error: Exiting due to 2 warning(s)\n'
module adder(input [31:0] a,
             input [31:0] b,
			 input cin,
			 input [3:0] alu_ctl,
			 output add_carry,
			 output add_overflow,
			 output add_zero,
			 output [31:0] add_result);


    assign {add_carry,add_result}=a+b+cin;
   assign add_zero = ~(|add_result);
   assign add_overflow=((alu_ctl==4'b0001) & ~a[31] & ~b[31] & add_result[31]) 
                      | ((alu_ctl==4'b0001) & a[31] & b[31] & ~add_result[31])
                      | ((alu_ctl==4'b0011) & a[31] & ~b[31] & ~add_result[31]) 
					  | ((alu_ctl==4'b0011) & ~a[31] & b[31] & add_result[31]);
endmodule
module adder(input [31:0] a,
             input [31:0] b,
			 input cin,
			 input [3:0] alu_ctl,
			 output add_carry,
			 output add_overflow,
			 output add_zero,
			 output [31:0] add_result);



    assign {add_carry,add_result}=a+b+cin;
   assign add_zero = ~(|add_result);
   assign add_overflow=((alu_ctl==4'b0001) & ~a[31] & ~b[31] & add_result[31]) 
                      | ((alu_ctl==4'b0001) & a[31] & b[31] & ~add_result[31])
                      | ((alu_ctl==4'b0011) & a[31] & ~b[31] & ~add_result[31]) 
					  | ((alu_ctl==4'b0011) & ~a[31] & b[31] & add_result[31]);
endmodule