data/full_repos/permissive/476411617/Parallel_Serial_Converter.v
1: b'%Warning-WIDTH: data/full_repos/permissive/476411617/Parallel_Serial_Converter.v:133: Operator COND expects 8 bits on the Conditional False, but Conditional False\'s CONST \'4\'bzzzz\' generates 4 bits.\n                                                                                    : ... In instance Parallel_Serial_Converter\n    assign serial_data_out[gi*(Slice_Size*2)+(Slice_Size*2-1) -:(Slice_Size*2)] = counting && mode==0? parallel_regs[gi*LENGTH-1 + (Slice_Size*2)*(counter/2+counter%2) -:(Slice_Size*2)] : 4\'hz; \n                                                                                                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Parallel_Serial_Converter
 # (parameter SIZE = 1,  parameter MAX_WORD_LENGTH = 32, parameter LENGTH = 32, parameter Slice_Size = 4, parameter PE = 2)
(
	clk,  
	reset, 
    mode,
    start,
    finish,
    serial_data_in,
    parallel_data_in,
    serial_data_out,
    parallel_data_out
);

input clk, reset, start;
input[1:0] mode;
input [(Slice_Size*PE*2)*SIZE-1:0] serial_data_in;
input [PE*MAX_WORD_LENGTH*SIZE-1:0] parallel_data_in;
output reg finish;
output[(Slice_Size*PE*2)*SIZE-1:0] serial_data_out;
output[PE*MAX_WORD_LENGTH*SIZE-1:0] parallel_data_out;


integer i;


reg [PE*SIZE*MAX_WORD_LENGTH-1:0] parallel_regs;

reg [7:0] counter;
reg state;
reg counting;









always@(posedge clk) begin
    if(reset==0) begin
        counter <= LENGTH/Slice_Size;
        finish <= 0;
        counting    <= 0;
    end
    else begin
        if(start) begin
            counter     <= 0;
            finish      <= 0;
            counting    <= 0;
        end
        else if(counter<LENGTH/Slice_Size+1) begin
            counter <= counter + 1;
            counting <= 1;
            if(counter == LENGTH/Slice_Size) begin
                finish <= 1;
                counting <= 0;
            end
        end
        else finish <= 0;
    end
end



always@(posedge clk)
begin
    if(reset==0) begin
        parallel_regs <= 0;
        i <= 0;
        state <= 0;
    end
    else
    begin
        if(mode==0)
        begin
            parallel_regs <= parallel_regs;
        end
        if(mode==1) begin
            if(counting) begin
                case(state)
				0: begin
				state <= 1;
				end
				1: begin
				for(i=0; i<SIZE*PE; i=i+1) begin
                    parallel_regs[i*LENGTH-1 + Slice_Size*counter -:(Slice_Size*2)] <= serial_data_in[i*(Slice_Size*2)+(Slice_Size*2-1) -:(Slice_Size*2)];
                end
                state <= 0;
				end
                endcase
            end
        end
        else if(mode==2)
        begin
            parallel_regs <= parallel_data_in;
        end
        
    end
end

assign parallel_data_out = parallel_regs;

genvar gi;
generate
for (gi=0; gi<SIZE*PE; gi=gi+1) begin : s
    assign serial_data_out[gi*(Slice_Size*2)+(Slice_Size*2-1) -:(Slice_Size*2)] = counting && mode==0? parallel_regs[gi*LENGTH-1 + (Slice_Size*2)*(counter/2+counter%2) -:(Slice_Size*2)] : 4'hz; 

end
endgenerate


endmodule
module Parallel_Serial_Converter
 # (parameter SIZE = 1,  parameter MAX_WORD_LENGTH = 32, parameter LENGTH = 32, parameter Slice_Size = 4, parameter PE = 2)
(
	clk,  
	reset, 
    mode,
    start,
    finish,
    serial_data_in,
    parallel_data_in,
    serial_data_out,
    parallel_data_out
);


input clk, reset, start;
input[1:0] mode;
input [(Slice_Size*PE*2)*SIZE-1:0] serial_data_in;
input [PE*MAX_WORD_LENGTH*SIZE-1:0] parallel_data_in;
output reg finish;
output[(Slice_Size*PE*2)*SIZE-1:0] serial_data_out;
output[PE*MAX_WORD_LENGTH*SIZE-1:0] parallel_data_out;


integer i;


reg [PE*SIZE*MAX_WORD_LENGTH-1:0] parallel_regs;

reg [7:0] counter;
reg state;
reg counting;









always@(posedge clk) begin
    if(reset==0) begin
        counter <= LENGTH/Slice_Size;
        finish <= 0;
        counting    <= 0;
    end
    else begin
        if(start) begin
            counter     <= 0;
            finish      <= 0;
            counting    <= 0;
        end
        else if(counter<LENGTH/Slice_Size+1) begin
            counter <= counter + 1;
            counting <= 1;
            if(counter == LENGTH/Slice_Size) begin
                finish <= 1;
                counting <= 0;
            end
        end
        else finish <= 0;
    end
end



always@(posedge clk)
begin
    if(reset==0) begin
        parallel_regs <= 0;
        i <= 0;
        state <= 0;
    end
    else
    begin
        if(mode==0)
        begin
            parallel_regs <= parallel_regs;
        end
        if(mode==1) begin
            if(counting) begin
                case(state)
				0: begin
				state <= 1;
				end
				1: begin
				for(i=0; i<SIZE*PE; i=i+1) begin
                    parallel_regs[i*LENGTH-1 + Slice_Size*counter -:(Slice_Size*2)] <= serial_data_in[i*(Slice_Size*2)+(Slice_Size*2-1) -:(Slice_Size*2)];
                end
                state <= 0;
				end
                endcase
            end
        end
        else if(mode==2)
        begin
            parallel_regs <= parallel_data_in;
        end
        
    end
end

assign parallel_data_out = parallel_regs;

genvar gi;
generate
for (gi=0; gi<SIZE*PE; gi=gi+1) begin : s
    assign serial_data_out[gi*(Slice_Size*2)+(Slice_Size*2-1) -:(Slice_Size*2)] = counting && mode==0? parallel_regs[gi*LENGTH-1 + (Slice_Size*2)*(counter/2+counter%2) -:(Slice_Size*2)] : 4'hz; 

end
endgenerate


endmodule