data/full_repos/permissive/477054115/iitb-risc/registerBank.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/477054115/iitb-risc/registerBank.v:19: Multiple top level modules\n                                                                                   : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                   : ... Top module \'register_n\'\nmodule register_n\n       ^~~~~~~~~~\n                                                                                   : ... Top module \'register_bank\'\nmodule register_bank\n       ^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/477054115/iitb-risc/registerBank.v:39: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS\'s CONST \'127\'h0\' generates 127 bits.\n                                                                                : ... In instance register_bank\n     readData_R7_to_R0 = 127\'b0;\n                       ^\n%Error: Exiting due to 2 warning(s)\n'
module register_bank
(
	input  [15:0] writeData, pcWriteData,
	input  [2:0]  readAddress1, readAddress2, writeAddress,
	input	writeEnable, clk, reset, pcWriteEnable,
	output reg [15:0] readData1, readData2,
	output reg [127:0] readData_R7_to_R0
);
		
	reg [15:0] registerFile [0:7];
	integer i = 0;
	
	initial 
    begin 
	    for (i=0; i<8; i=i+1) begin
	        registerFile[i] = 16'b0;
        end
       
	    readData1 = 16'b0;
	    readData2 = 16'b0;
	    readData_R7_to_R0 = 127'b0;
    end
    
	always @(*) begin 
        readData1 = registerFile[readAddress1];
        readData2 = registerFile[readAddress2];
        readData_R7_to_R0 = {registerFile[7], registerFile[6], registerFile[5], registerFile[4], 
                registerFile[3], registerFile[2], registerFile[1], registerFile[0]};
	end

	always @(posedge clk) begin 
	    if (reset) begin 
            for (i=0; i<7 ; i=i+1) begin
                registerFile[i] = 0;
            end
            registerFile[7] = 0;
        end
        
        else begin
            if (writeEnable) begin 
                if (writeAddress < 7)
                registerFile[writeAddress] <= writeData;		   
            end
            if (pcWriteEnable) 
                registerFile[7] <= pcWriteData;
        end
	end

endmodule
module register_bank
(
	input  [15:0] writeData, pcWriteData,
	input  [2:0]  readAddress1, readAddress2, writeAddress,
	input	writeEnable, clk, reset, pcWriteEnable,
	output reg [15:0] readData1, readData2,
	output reg [127:0] readData_R7_to_R0
);

		
	reg [15:0] registerFile [0:7];
	integer i = 0;
	
	initial 
    begin 
	    for (i=0; i<8; i=i+1) begin
	        registerFile[i] = 16'b0;
        end
       
	    readData1 = 16'b0;
	    readData2 = 16'b0;
	    readData_R7_to_R0 = 127'b0;
    end
    
	always @(*) begin 
        readData1 = registerFile[readAddress1];
        readData2 = registerFile[readAddress2];
        readData_R7_to_R0 = {registerFile[7], registerFile[6], registerFile[5], registerFile[4], 
                registerFile[3], registerFile[2], registerFile[1], registerFile[0]};
	end

	always @(posedge clk) begin 
	    if (reset) begin 
            for (i=0; i<7 ; i=i+1) begin
                registerFile[i] = 0;
            end
            registerFile[7] = 0;
        end
        
        else begin
            if (writeEnable) begin 
                if (writeAddress < 7)
                registerFile[writeAddress] <= writeData;		   
            end
            if (pcWriteEnable) 
                registerFile[7] <= pcWriteData;
        end
	end

endmodule