data/full_repos/permissive/461141714/src/Single Cycle CPU/DataPath.v
1: b'%Error: Cannot find file containing module: Cycle\n        ... Looked in:\n             data/full_repos/permissive/461141714/src/Single/Cycle\n             data/full_repos/permissive/461141714/src/Single/Cycle.v\n             data/full_repos/permissive/461141714/src/Single/Cycle.sv\n             Cycle\n             Cycle.v\n             Cycle.sv\n             obj_dir/Cycle\n             obj_dir/Cycle.v\n             obj_dir/Cycle.sv\n%Error: Cannot find file containing module: CPU,data/full_repos/permissive/461141714\n%Error: Cannot find file containing module: data/full_repos/permissive/461141714/src/Single\n%Error: Cannot find file containing module: CPU/DataPath.v\n%Error: Exiting due to 4 error(s)\n'
module DataPath(
    input clk,
    input reset_n,
    

    input [`WORD_SIZE-1: 0] instruction,
    input isR,
    input [5:0] aluFunc,
    input isADI,
    input isLHI,
    input isJMP,
    input isOUT,
    input regWrite,
    

    output reg [`WORD_SIZE-1:0] addr,
    output reg [`WORD_SIZE-1:0] outSignal
    );
    

    reg [`WORD_SIZE-1:0] PC;
    

    wire [3:0] opcode = instruction[15:12];
    wire [1:0] rs = instruction[11:10];
    wire [1:0] rt = instruction[9:8];
    wire [1:0] rd = instruction[7:6];
    wire [5:0] r_function = instruction[5:0];
    wire [7:0] i_immediate = instruction[7:0];
    wire [11:0] j_immediate = instruction[11:0];
    wire [15:0] lshift = {instruction[7:0], 8'b0};
    wire [15:0] sign_extend = {{8{instruction[7]}}, instruction[7:0]};
    

    reg [1:0] addr1;
    reg [1:0] addr2;
    reg [1:0] addr3;
    wire [`WORD_SIZE-1:0] data1;
    wire [`WORD_SIZE-1:0] data2;
    reg [`WORD_SIZE-1:0] data3;
    

    reg [`WORD_SIZE-1:0] aluA;
    reg [`WORD_SIZE-1:0] aluB;
    wire [`WORD_SIZE-1:0] aluResult;
    

    always @(*) begin
        addr1 = rs;
        addr2 = rt;
        addr3 = isR ? rd : rt;
        data3 = isLHI ? lshift : aluResult;
        aluA = data1;
        aluB = isADI ? sign_extend : data2;
    end
    

    RF registerFile(
        regWrite,clk,reset_n,
        addr1,addr2,addr3,
        data1,data2,data3
    );
    
    ALU alu(aluA, aluB, aluFunc, aluResult);
    

    initial begin
        PC = `WORD_SIZE'b0;
        addr = PC;
    end
    always @(posedge clk) begin
        if(reset_n != 0) begin
            PC = isJMP ? j_immediate : PC+1;
            addr = PC;
            outSignal = isOUT ? data1 : `WORD_SIZE'b0;
        end
    end
    always @(reset_n) begin
        if(reset_n == 1'b0) begin
            PC = `WORD_SIZE'b0;
            addr = PC;
        end
    end
    
endmodule
module DataPath(
    input clk,
    input reset_n,
    

    input [`WORD_SIZE-1: 0] instruction,
    input isR,
    input [5:0] aluFunc,
    input isADI,
    input isLHI,
    input isJMP,
    input isOUT,
    input regWrite,
    

    output reg [`WORD_SIZE-1:0] addr,
    output reg [`WORD_SIZE-1:0] outSignal
    );

    

    reg [`WORD_SIZE-1:0] PC;
    

    wire [3:0] opcode = instruction[15:12];
    wire [1:0] rs = instruction[11:10];
    wire [1:0] rt = instruction[9:8];
    wire [1:0] rd = instruction[7:6];
    wire [5:0] r_function = instruction[5:0];
    wire [7:0] i_immediate = instruction[7:0];
    wire [11:0] j_immediate = instruction[11:0];
    wire [15:0] lshift = {instruction[7:0], 8'b0};
    wire [15:0] sign_extend = {{8{instruction[7]}}, instruction[7:0]};
    

    reg [1:0] addr1;
    reg [1:0] addr2;
    reg [1:0] addr3;
    wire [`WORD_SIZE-1:0] data1;
    wire [`WORD_SIZE-1:0] data2;
    reg [`WORD_SIZE-1:0] data3;
    

    reg [`WORD_SIZE-1:0] aluA;
    reg [`WORD_SIZE-1:0] aluB;
    wire [`WORD_SIZE-1:0] aluResult;
    

    always @(*) begin
        addr1 = rs;
        addr2 = rt;
        addr3 = isR ? rd : rt;
        data3 = isLHI ? lshift : aluResult;
        aluA = data1;
        aluB = isADI ? sign_extend : data2;
    end
    

    RF registerFile(
        regWrite,clk,reset_n,
        addr1,addr2,addr3,
        data1,data2,data3
    );
    
    ALU alu(aluA, aluB, aluFunc, aluResult);
    

    initial begin
        PC = `WORD_SIZE'b0;
        addr = PC;
    end
    always @(posedge clk) begin
        if(reset_n != 0) begin
            PC = isJMP ? j_immediate : PC+1;
            addr = PC;
            outSignal = isOUT ? data1 : `WORD_SIZE'b0;
        end
    end
    always @(reset_n) begin
        if(reset_n == 1'b0) begin
            PC = `WORD_SIZE'b0;
            addr = PC;
        end
    end
    
endmodule