data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/tb_cswap.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/tb_cswap.v:11: Unsupported: Ignoring delay on this delayed statement.\n#50 clk=1;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/tb_cswap.v:12: Unsupported: Ignoring delay on this delayed statement.\n#50;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/tb_cswap.v:50: Unsupported: Ignoring delay on this delayed statement.\n#150 rst = 1\'b1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/tb_cswap.v:51: Unsupported: Ignoring delay on this delayed statement.\n#100 rst = 1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/tb_cswap.v:52: Unsupported: Ignoring delay on this delayed statement.\n#0.1 en = 1\'b1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/tb_cswap.v:53: Unsupported: Ignoring delay on this delayed statement.\n#100;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/tb_cswap.v:55: Unsupported: Ignoring delay on this delayed statement.\n#5000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/tb_cswap.v:59: Unsupported: Ignoring delay on this delayed statement.\n#100 en = 1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/tb_cswap.v:60: Unsupported: Ignoring delay on this delayed statement.\n#70000;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/tb_cswap.v:63: Unsupported: Ignoring delay on this delayed statement.\n#100 en = 1\'b0;\n^\n%Warning-STMTDLY: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/tb_cswap.v:64: Unsupported: Ignoring delay on this delayed statement.\n#70000\n^\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/tb_cswap.v:82: Unsupported or unknown PLI call: $shm_open\n$shm_open ("my_waves");\n^~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/tb_cswap.v:83: Unsupported or unknown PLI call: $shm_probe\n$shm_probe (tb_cswap,"AC");\n^~~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/tb_cswap.v:84: Unsupported or unknown PLI call: $recordfile\n$recordfile("testsample.trn");\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/tb_cswap.v:85: Unsupported or unknown PLI call: $recordvars\n$recordvars();\n^~~~~~~~~~~\n%Error: Exiting due to 4 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_cswap;

parameter WID = 256;

reg clk;
reg rst;

always begin
clk = 0;
#50 clk=1;
#50;
end

reg [WID-1:0] swap;
reg [WID-1:0] a;
reg [WID-1:0] b;
reg           en;

wire [WID-1:0] aswap;
wire [WID-1:0] bswap;
wire           vld;




cswap icswap
    (
     .clk(clk),
     .rst(rst),

     .swap(swap),
     .a(a),
     .b(b),
     .en(en),

     .aswap(aswap),
     .bswap(bswap),
     .vld(vld)
     );



initial begin
rst = 1'b0;
a = 256'd11;
b = 256'd11579;
swap = 256'd500;
en = 1'b0;
#150 rst = 1'b1;
#100 rst = 1'b0;
#0.1 en = 1'b1;
#100;
en = 1'b0;
#5000;
a = 256'd11;
b = 256'd12;
en = 1'b1;
#100 en = 1'b0;
#70000;
a = 256'd115792089210356248762697446949407573530086143415290314195533631308867097853950;
en = 1'b1;
#100 en = 1'b0;
#70000
$finish;
end

initial begin
$display ("==========OUTPUT==========");
end

always@(posedge clk) begin
if(vld)
    begin
    $display ("Output : %d ", aswap);
    $display ("Output : %d ", bswap);
    end
end


initial begin
$shm_open ("my_waves");
$shm_probe (tb_cswap,"AC");
$recordfile("testsample.trn");
$recordvars();
end

endmodule
module tb_cswap;


parameter WID = 256;

reg clk;
reg rst;

always begin
clk = 0;
#50 clk=1;
#50;
end

reg [WID-1:0] swap;
reg [WID-1:0] a;
reg [WID-1:0] b;
reg           en;

wire [WID-1:0] aswap;
wire [WID-1:0] bswap;
wire           vld;




cswap icswap
    (
     .clk(clk),
     .rst(rst),

     .swap(swap),
     .a(a),
     .b(b),
     .en(en),

     .aswap(aswap),
     .bswap(bswap),
     .vld(vld)
     );



initial begin
rst = 1'b0;
a = 256'd11;
b = 256'd11579;
swap = 256'd500;
en = 1'b0;
#150 rst = 1'b1;
#100 rst = 1'b0;
#0.1 en = 1'b1;
#100;
en = 1'b0;
#5000;
a = 256'd11;
b = 256'd12;
en = 1'b1;
#100 en = 1'b0;
#70000;
a = 256'd115792089210356248762697446949407573530086143415290314195533631308867097853950;
en = 1'b1;
#100 en = 1'b0;
#70000
$finish;
end

initial begin
$display ("==========OUTPUT==========");
end

always@(posedge clk) begin
if(vld)
    begin
    $display ("Output : %d ", aswap);
    $display ("Output : %d ", bswap);
    end
end


initial begin
$shm_open ("my_waves");
$shm_probe (tb_cswap,"AC");
$recordfile("testsample.trn");
$recordvars();
end

endmodule