data/full_repos/permissive/494664634/AxiLiteSlaveTest/src/hdl/AxiLiteSlaveTest.v
data/verilator_xmls/cefd15d1-fbbe-404f-8143-350dad2f80c6.xml
module AxiLiteSlaveTest(

  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clock CLK", X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF S_AXI_LITE"
     *)
  input         clock,

  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 reset RST", X_INTERFACE_PARAMETER = "POLARITY ACTIVE_HIGH" *)
  input         reset,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR" *)
  input  [31:0] s_axi_araddr,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID" *)
  input         s_axi_arvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY" *)
  output        s_axi_arready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA" *)
  output [31:0] s_axi_rdata,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP" *)
  output [1:0]  s_axi_rresp,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID" *)
  output        s_axi_rvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY" *)
  input         s_axi_rready,

  (*
    X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR", X_INTERFACE_PARAMETER = "CLK_DOMAIN clock, ID_WIDTH 0, PROTOCOL AXI4LITE, DATA_WIDTH 32"
     *)
  input  [31:0] s_axi_awaddr,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID" *)
  input         s_axi_awvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY" *)
  output        s_axi_awready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA" *)
  input  [31:0] s_axi_wdata,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID" *)
  input         s_axi_wvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY" *)
  output        s_axi_wready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP" *)
  output [1:0]  s_axi_bresp,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID" *)
  output        s_axi_bvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY" *)
  input         s_axi_bready,
  output [7:0]  led,
  input  [7:0]  sw
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif
  wire  axi_ctrl_clock;
  wire  axi_ctrl_reset;
  wire [31:0] axi_ctrl_s_axi_araddr;
  wire  axi_ctrl_s_axi_arvalid;
  wire  axi_ctrl_s_axi_arready;
  wire [31:0] axi_ctrl_s_axi_rdata;
  wire  axi_ctrl_s_axi_rvalid;
  wire  axi_ctrl_s_axi_rready;
  wire [31:0] axi_ctrl_s_axi_awaddr;
  wire  axi_ctrl_s_axi_awvalid;
  wire  axi_ctrl_s_axi_awready;
  wire [31:0] axi_ctrl_s_axi_wdata;
  wire  axi_ctrl_s_axi_wvalid;
  wire  axi_ctrl_s_axi_wready;
  wire  axi_ctrl_s_axi_bvalid;
  wire  axi_ctrl_s_axi_bready;
  wire  axi_ctrl_wr_en;
  wire  axi_ctrl_rd_en;
  wire [11:0] axi_ctrl_wr_addr;
  wire [11:0] axi_ctrl_rd_addr;
  wire [31:0] axi_ctrl_wr_data;
  wire [31:0] axi_ctrl_rd_data;
  reg [7:0] led_r;
  wire [31:0] _GEN_0 = axi_ctrl_wr_addr == 12'h0 ? axi_ctrl_wr_data : {{24'd0}, led_r};
  wire [31:0] _GEN_1 = axi_ctrl_wr_en ? _GEN_0 : {{24'd0}, led_r};
  wire [15:0] _GEN_2 = axi_ctrl_rd_addr == 12'h0 ? {{8'd0}, led_r} : 16'hdead;
  wire [15:0] _GEN_3 = axi_ctrl_rd_addr == 12'h4 ? {{8'd0}, sw} : _GEN_2;
  wire [15:0] _GEN_4 = axi_ctrl_rd_en ? _GEN_3 : 16'hdead;
  wire [31:0] _GEN_5 = reset ? 32'h0 : _GEN_1;
  AxiLiteControl axi_ctrl (
    .clock(axi_ctrl_clock),
    .reset(axi_ctrl_reset),
    .s_axi_araddr(axi_ctrl_s_axi_araddr),
    .s_axi_arvalid(axi_ctrl_s_axi_arvalid),
    .s_axi_arready(axi_ctrl_s_axi_arready),
    .s_axi_rdata(axi_ctrl_s_axi_rdata),
    .s_axi_rvalid(axi_ctrl_s_axi_rvalid),
    .s_axi_rready(axi_ctrl_s_axi_rready),
    .s_axi_awaddr(axi_ctrl_s_axi_awaddr),
    .s_axi_awvalid(axi_ctrl_s_axi_awvalid),
    .s_axi_awready(axi_ctrl_s_axi_awready),
    .s_axi_wdata(axi_ctrl_s_axi_wdata),
    .s_axi_wvalid(axi_ctrl_s_axi_wvalid),
    .s_axi_wready(axi_ctrl_s_axi_wready),
    .s_axi_bvalid(axi_ctrl_s_axi_bvalid),
    .s_axi_bready(axi_ctrl_s_axi_bready),
    .wr_en(axi_ctrl_wr_en),
    .rd_en(axi_ctrl_rd_en),
    .wr_addr(axi_ctrl_wr_addr),
    .rd_addr(axi_ctrl_rd_addr),
    .wr_data(axi_ctrl_wr_data),
    .rd_data(axi_ctrl_rd_data)
  );
  assign s_axi_arready = axi_ctrl_s_axi_arready;
  assign s_axi_rdata = axi_ctrl_s_axi_rdata;
  assign s_axi_rresp = 2'h0;
  assign s_axi_rvalid = axi_ctrl_s_axi_rvalid;
  assign s_axi_awready = axi_ctrl_s_axi_awready;
  assign s_axi_wready = axi_ctrl_s_axi_wready;
  assign s_axi_bresp = 2'h0;
  assign s_axi_bvalid = axi_ctrl_s_axi_bvalid;
  assign led = led_r;
  assign axi_ctrl_clock = clock;
  assign axi_ctrl_reset = reset;
  assign axi_ctrl_s_axi_araddr = s_axi_araddr;
  assign axi_ctrl_s_axi_arvalid = s_axi_arvalid;
  assign axi_ctrl_s_axi_rready = s_axi_rready;
  assign axi_ctrl_s_axi_awaddr = s_axi_awaddr;
  assign axi_ctrl_s_axi_awvalid = s_axi_awvalid;
  assign axi_ctrl_s_axi_wdata = s_axi_wdata;
  assign axi_ctrl_s_axi_wvalid = s_axi_wvalid;
  assign axi_ctrl_s_axi_bready = s_axi_bready;
  assign axi_ctrl_rd_data = {{16'd0}, _GEN_4};
  always @(posedge clock) begin
    led_r <= _GEN_5[7:0];
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  led_r = _RAND_0[7:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module AxiLiteSlaveTest(

  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clock CLK", X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF S_AXI_LITE"
     *)
  input         clock,

  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 reset RST", X_INTERFACE_PARAMETER = "POLARITY ACTIVE_HIGH" *)
  input         reset,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR" *)
  input  [31:0] s_axi_araddr,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID" *)
  input         s_axi_arvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY" *)
  output        s_axi_arready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA" *)
  output [31:0] s_axi_rdata,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP" *)
  output [1:0]  s_axi_rresp,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID" *)
  output        s_axi_rvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY" *)
  input         s_axi_rready,

  (*
    X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR", X_INTERFACE_PARAMETER = "CLK_DOMAIN clock, ID_WIDTH 0, PROTOCOL AXI4LITE, DATA_WIDTH 32"
     *)
  input  [31:0] s_axi_awaddr,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID" *)
  input         s_axi_awvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY" *)
  output        s_axi_awready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA" *)
  input  [31:0] s_axi_wdata,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID" *)
  input         s_axi_wvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY" *)
  output        s_axi_wready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP" *)
  output [1:0]  s_axi_bresp,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID" *)
  output        s_axi_bvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY" *)
  input         s_axi_bready,
  output [7:0]  led,
  input  [7:0]  sw
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif
  wire  axi_ctrl_clock;
  wire  axi_ctrl_reset;
  wire [31:0] axi_ctrl_s_axi_araddr;
  wire  axi_ctrl_s_axi_arvalid;
  wire  axi_ctrl_s_axi_arready;
  wire [31:0] axi_ctrl_s_axi_rdata;
  wire  axi_ctrl_s_axi_rvalid;
  wire  axi_ctrl_s_axi_rready;
  wire [31:0] axi_ctrl_s_axi_awaddr;
  wire  axi_ctrl_s_axi_awvalid;
  wire  axi_ctrl_s_axi_awready;
  wire [31:0] axi_ctrl_s_axi_wdata;
  wire  axi_ctrl_s_axi_wvalid;
  wire  axi_ctrl_s_axi_wready;
  wire  axi_ctrl_s_axi_bvalid;
  wire  axi_ctrl_s_axi_bready;
  wire  axi_ctrl_wr_en;
  wire  axi_ctrl_rd_en;
  wire [11:0] axi_ctrl_wr_addr;
  wire [11:0] axi_ctrl_rd_addr;
  wire [31:0] axi_ctrl_wr_data;
  wire [31:0] axi_ctrl_rd_data;
  reg [7:0] led_r;
  wire [31:0] _GEN_0 = axi_ctrl_wr_addr == 12'h0 ? axi_ctrl_wr_data : {{24'd0}, led_r};
  wire [31:0] _GEN_1 = axi_ctrl_wr_en ? _GEN_0 : {{24'd0}, led_r};
  wire [15:0] _GEN_2 = axi_ctrl_rd_addr == 12'h0 ? {{8'd0}, led_r} : 16'hdead;
  wire [15:0] _GEN_3 = axi_ctrl_rd_addr == 12'h4 ? {{8'd0}, sw} : _GEN_2;
  wire [15:0] _GEN_4 = axi_ctrl_rd_en ? _GEN_3 : 16'hdead;
  wire [31:0] _GEN_5 = reset ? 32'h0 : _GEN_1;
  AxiLiteControl axi_ctrl (
    .clock(axi_ctrl_clock),
    .reset(axi_ctrl_reset),
    .s_axi_araddr(axi_ctrl_s_axi_araddr),
    .s_axi_arvalid(axi_ctrl_s_axi_arvalid),
    .s_axi_arready(axi_ctrl_s_axi_arready),
    .s_axi_rdata(axi_ctrl_s_axi_rdata),
    .s_axi_rvalid(axi_ctrl_s_axi_rvalid),
    .s_axi_rready(axi_ctrl_s_axi_rready),
    .s_axi_awaddr(axi_ctrl_s_axi_awaddr),
    .s_axi_awvalid(axi_ctrl_s_axi_awvalid),
    .s_axi_awready(axi_ctrl_s_axi_awready),
    .s_axi_wdata(axi_ctrl_s_axi_wdata),
    .s_axi_wvalid(axi_ctrl_s_axi_wvalid),
    .s_axi_wready(axi_ctrl_s_axi_wready),
    .s_axi_bvalid(axi_ctrl_s_axi_bvalid),
    .s_axi_bready(axi_ctrl_s_axi_bready),
    .wr_en(axi_ctrl_wr_en),
    .rd_en(axi_ctrl_rd_en),
    .wr_addr(axi_ctrl_wr_addr),
    .rd_addr(axi_ctrl_rd_addr),
    .wr_data(axi_ctrl_wr_data),
    .rd_data(axi_ctrl_rd_data)
  );
  assign s_axi_arready = axi_ctrl_s_axi_arready;
  assign s_axi_rdata = axi_ctrl_s_axi_rdata;
  assign s_axi_rresp = 2'h0;
  assign s_axi_rvalid = axi_ctrl_s_axi_rvalid;
  assign s_axi_awready = axi_ctrl_s_axi_awready;
  assign s_axi_wready = axi_ctrl_s_axi_wready;
  assign s_axi_bresp = 2'h0;
  assign s_axi_bvalid = axi_ctrl_s_axi_bvalid;
  assign led = led_r;
  assign axi_ctrl_clock = clock;
  assign axi_ctrl_reset = reset;
  assign axi_ctrl_s_axi_araddr = s_axi_araddr;
  assign axi_ctrl_s_axi_arvalid = s_axi_arvalid;
  assign axi_ctrl_s_axi_rready = s_axi_rready;
  assign axi_ctrl_s_axi_awaddr = s_axi_awaddr;
  assign axi_ctrl_s_axi_awvalid = s_axi_awvalid;
  assign axi_ctrl_s_axi_wdata = s_axi_wdata;
  assign axi_ctrl_s_axi_wvalid = s_axi_wvalid;
  assign axi_ctrl_s_axi_bready = s_axi_bready;
  assign axi_ctrl_rd_data = {{16'd0}, _GEN_4};
  always @(posedge clock) begin
    led_r <= _GEN_5[7:0];
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  led_r = _RAND_0[7:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule