data/full_repos/permissive/43856783/Ultrasonico/control_fisico.v
1: b'%Warning-WIDTH: data/full_repos/permissive/43856783/Ultrasonico/control_fisico.v:24: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'waiting\' generates 32 or 4 bits.\n                                                                                   : ... In instance control_fisico\n      state <= waiting ;\n            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/43856783/Ultrasonico/control_fisico.v:19: Operator CASE expects 32 or 4 bits on the Case expression, but Case expression\'s VARREF \'state\' generates 2 bits.\n                                                                                   : ... In instance control_fisico\n   case ( state )\n   ^~~~\n%Warning-WIDTH: data/full_repos/permissive/43856783/Ultrasonico/control_fisico.v:35: Operator CASE expects 32 or 4 bits on the Case expression, but Case expression\'s VARREF \'state\' generates 2 bits.\n                                                                                   : ... In instance control_fisico\n  case ( state )\n  ^~~~\n%Error: Exiting due to 3 warning(s)\n'
module control_fisico (
	input clk ,
	input enable ,
	input [31:0] clkValue ,
	
	output reg start
	);
	
	reg [1:0] state ;
	
	localparam reset 	= 00 ;
	localparam on 		= 01 ;
	localparam waiting 	= 10 ;
	
	always @ ( negedge clk )
		if ( !enable )
			state <= reset ;
		else
			case ( state )
				reset:
					state <= on ;
				on:
					if ( 1_200 < clkValue )
						state <= waiting ;
					else
						state <= state ;
				waiting:
					if ( 1_000_000 > clkValue )
						state <= state ;
					else
						state <= state ;
		endcase
		
	always @ ( posedge clk )
		case ( state )
			reset: 
				start <= 0 ;
			on:
				start <= 1 ;
			waiting:
				start <= 0 ;
			default:
				start <= 0 ;
		endcase
		
endmodule
module control_fisico (
	input clk ,
	input enable ,
	input [31:0] clkValue ,
	
	output reg start
	);

	
	reg [1:0] state ;
	
	localparam reset 	= 00 ;
	localparam on 		= 01 ;
	localparam waiting 	= 10 ;
	
	always @ ( negedge clk )
		if ( !enable )
			state <= reset ;
		else
			case ( state )
				reset:
					state <= on ;
				on:
					if ( 1_200 < clkValue )
						state <= waiting ;
					else
						state <= state ;
				waiting:
					if ( 1_000_000 > clkValue )
						state <= state ;
					else
						state <= state ;
		endcase
		
	always @ ( posedge clk )
		case ( state )
			reset: 
				start <= 0 ;
			on:
				start <= 1 ;
			waiting:
				start <= 0 ;
			default:
				start <= 0 ;
		endcase
		
endmodule