data/full_repos/permissive/488482526/LR4_Top_V10.v
1: b"%Error: data/full_repos/permissive/488482526/LR4_Top_V10.v:16: Cannot find file containing module: 'M_CLOCK_DIVIDER'\nM_CLOCK_DIVIDER M_CLOCK_DIVIDER_wrapper(\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/488482526,data/full_repos/permissive/488482526/M_CLOCK_DIVIDER\n             data/full_repos/permissive/488482526,data/full_repos/permissive/488482526/M_CLOCK_DIVIDER.v\n             data/full_repos/permissive/488482526,data/full_repos/permissive/488482526/M_CLOCK_DIVIDER.sv\n             M_CLOCK_DIVIDER\n             M_CLOCK_DIVIDER.v\n             M_CLOCK_DIVIDER.sv\n             obj_dir/M_CLOCK_DIVIDER\n             obj_dir/M_CLOCK_DIVIDER.v\n             obj_dir/M_CLOCK_DIVIDER.sv\n%Error: data/full_repos/permissive/488482526/LR4_Top_V10.v:23: Cannot find file containing module: 'M_BTN_FILTER_V10'\nM_BTN_FILTER_V10 M_BTN_FILTER_V10_wrapper(\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/488482526/LR4_Top_V10.v:31: Cannot find file containing module: 'LR2_SEQ_GEN_FSM'\nLR2_SEQ_GEN_FSM LR2_SEQ_GEN_FSM_wrapper(\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/488482526/LR4_Top_V10.v:39: Cannot find file containing module: 'LR4_MATRIX_DISP_V10'\nLR4_MATRIX_DISP_V10 LR4_MATRIX_DISP_V10_wrapper(\n^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module LR4_Top_V10
(
input wire clk,
input wire rst,
input wire btn,
input wire switch,
output [7:0]row,
output [7:0]column
);

wire divided_clk;
wire filtred_btn;
wire [3:0]SEQ;

M_CLOCK_DIVIDER M_CLOCK_DIVIDER_wrapper(

.clk(clk),
.rst(rst),
.divided_clk(divided_clk)
);

M_BTN_FILTER_V10 M_BTN_FILTER_V10_wrapper(

.clk(clk),
.rst(rst),
.btn(btn),
.btn_down(filtred_btn)
);

LR2_SEQ_GEN_FSM LR2_SEQ_GEN_FSM_wrapper(
.clk(clk),
.rst(rst),
.CE(filtred_btn),
.UP(switch),
.SEQ(SEQ)
);

LR4_MATRIX_DISP_V10 LR4_MATRIX_DISP_V10_wrapper(
.clk(clk),
.rst(rst),
.CE(divided_clk),
.SEQ(SEQ),
.column(column),
.row(row)
);

endmodule
module LR4_Top_V10
(
input wire clk,
input wire rst,
input wire btn,
input wire switch,
output [7:0]row,
output [7:0]column
);


wire divided_clk;
wire filtred_btn;
wire [3:0]SEQ;

M_CLOCK_DIVIDER M_CLOCK_DIVIDER_wrapper(

.clk(clk),
.rst(rst),
.divided_clk(divided_clk)
);

M_BTN_FILTER_V10 M_BTN_FILTER_V10_wrapper(

.clk(clk),
.rst(rst),
.btn(btn),
.btn_down(filtred_btn)
);

LR2_SEQ_GEN_FSM LR2_SEQ_GEN_FSM_wrapper(
.clk(clk),
.rst(rst),
.CE(filtred_btn),
.UP(switch),
.SEQ(SEQ)
);

LR4_MATRIX_DISP_V10 LR4_MATRIX_DISP_V10_wrapper(
.clk(clk),
.rst(rst),
.CE(divided_clk),
.SEQ(SEQ),
.column(column),
.row(row)
);

endmodule