data/full_repos/permissive/451577625/system/cla_16.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/451577625/system/cla_16.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_x = 16\'h0001; in_y = 16\'h000F; in_carry = 0;  \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/cla_16.v:56: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_x = 16\'h0000; in_y = 16\'h0000; in_carry = 0;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/cla_16.v:57: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_x = 16\'h0001; in_y = 16\'h000F; in_carry = 1;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/cla_16.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_x = 16\'h0000; in_y = 16\'h0000; in_carry = 0;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/cla_16.v:59: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_x = 16\'hFFFF; in_y = 16\'h0002; in_carry = 0;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/cla_16.v:60: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_x = 16\'h0000; in_y = 16\'h0000; in_carry = 0;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/cla_16.v:61: Unsupported: Ignoring delay on this delayed statement.\n  #(delay) in_x = 16\'hFFFF; in_y = 16\'h0002; in_carry = 1;  \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/cla_16.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/451577625/system/cla_16.v:14: Cannot find file containing module: \'cla_4\'\n   cla_4 cla(.in_x (in_x[i+3:i]),\n   ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/cla_4\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/cla_4.v\n             data/full_repos/permissive/451577625/system,data/full_repos/permissive/451577625/cla_4.sv\n             cla_4\n             cla_4.v\n             cla_4.sv\n             obj_dir/cla_4\n             obj_dir/cla_4.v\n             obj_dir/cla_4.sv\n%Error: data/full_repos/permissive/451577625/system/cla_16.v:23: Cannot find file containing module: \'cla_logic\'\n cla_logic cla(.in_carry (w_carry[0]),\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module cla_16_tb;

	reg [15:0] in_x, in_y;
	reg in_carry;
	
	wire [15:0] out_sum;
	wire out_generate, out_propogate, out_carry;
	
	parameter delay = 10;
	
	cla_16 DUT(.in_x (in_x),
		.in_y (in_y),
		.in_carry (in_carry),
		.out_sum (out_sum),
		.out_carry (out_carry),
		.out_generate (out_generate),
		.out_propogate (out_propogate));
		
	initial begin
		in_x = 16'h0000; in_y = 16'h0000; in_carry = 0;
		
		#(delay) in_x = 16'h0001; in_y = 16'h000F; in_carry = 0;
		#(delay) in_x = 16'h0000; in_y = 16'h0000; in_carry = 0;
		#(delay) in_x = 16'h0001; in_y = 16'h000F; in_carry = 1;
		#(delay) in_x = 16'h0000; in_y = 16'h0000; in_carry = 0;
		#(delay) in_x = 16'hFFFF; in_y = 16'h0002; in_carry = 0;
		#(delay) in_x = 16'h0000; in_y = 16'h0000; in_carry = 0;
		#(delay) in_x = 16'hFFFF; in_y = 16'h0002; in_carry = 1;
		#100;
	end

endmodule
module cla_16_tb;


	reg [15:0] in_x, in_y;
	reg in_carry;
	
	wire [15:0] out_sum;
	wire out_generate, out_propogate, out_carry;
	
	parameter delay = 10;
	
	cla_16 DUT(.in_x (in_x),
		.in_y (in_y),
		.in_carry (in_carry),
		.out_sum (out_sum),
		.out_carry (out_carry),
		.out_generate (out_generate),
		.out_propogate (out_propogate));
		
	initial begin
		in_x = 16'h0000; in_y = 16'h0000; in_carry = 0;
		
		#(delay) in_x = 16'h0001; in_y = 16'h000F; in_carry = 0;
		#(delay) in_x = 16'h0000; in_y = 16'h0000; in_carry = 0;
		#(delay) in_x = 16'h0001; in_y = 16'h000F; in_carry = 1;
		#(delay) in_x = 16'h0000; in_y = 16'h0000; in_carry = 0;
		#(delay) in_x = 16'hFFFF; in_y = 16'h0002; in_carry = 0;
		#(delay) in_x = 16'h0000; in_y = 16'h0000; in_carry = 0;
		#(delay) in_x = 16'hFFFF; in_y = 16'h0002; in_carry = 1;
		#100;
	end

endmodule