data/full_repos/permissive/476296842/rtl/core/id_ex.v
1: b'%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:8: Cannot find include file: rtl/core/define.v\n`include "rtl/core/define.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/476296842/rtl/core,data/full_repos/permissive/476296842/rtl/core/define.v\n             data/full_repos/permissive/476296842/rtl/core,data/full_repos/permissive/476296842/rtl/core/define.v.v\n             data/full_repos/permissive/476296842/rtl/core,data/full_repos/permissive/476296842/rtl/core/define.v.sv\n             rtl/core/define.v\n             rtl/core/define.v.v\n             rtl/core/define.v.sv\n             obj_dir/rtl/core/define.v\n             obj_dir/rtl/core/define.v.v\n             obj_dir/rtl/core/define.v.sv\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:14: Define or directive not defined: \'`holdpip_bus\'\n    input wire [`holdpip_bus]           hold_flag_i,\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:14: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire [`holdpip_bus]           hold_flag_i,\n                            ^\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:16: Define or directive not defined: \'`reg_addr_bus\'\n    input wire [`reg_addr_bus]          r_reg_addr_1_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:17: Define or directive not defined: \'`reg_addr_bus\'\n    input wire [`reg_addr_bus]          r_reg_addr_2_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:18: Define or directive not defined: \'`csr_addr_bus\'\n    input wire [`csr_addr_bus]          r_csr_addr_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:20: Define or directive not defined: \'`reg_data_bus\'\n    input wire [`reg_data_bus]          r_reg_data_1_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:21: Define or directive not defined: \'`reg_data_bus\'\n    input wire [`reg_data_bus]          r_reg_data_2_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:22: Define or directive not defined: \'`imm_data_bus\'\n    input wire [`imm_data_bus]          imm_data_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:23: Define or directive not defined: \'`csr_data_bus\'\n    input wire [`csr_data_bus]          r_csr_data_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:24: Define or directive not defined: \'`inst_addr_bus\'\n    input wire [`inst_addr_bus]         r_pc_data_i,\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:27: Define or directive not defined: \'`alu_inst_bus\'\n    input wire [`alu_inst_bus]          alu_inst_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:30: Define or directive not defined: \'`inst_bus\'\n    input wire [`inst_bus]              r_inst_i,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:33: Define or directive not defined: \'`reg_addr_bus\'\n    input wire [`reg_addr_bus]          w_reg_addr_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:34: Define or directive not defined: \'`csr_addr_bus\'\n    input wire [`csr_addr_bus]          w_csr_addr_i,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:37: Define or directive not defined: \'`data_type_bus\'\n    input wire [`data_type_bus]         data_type_i,\n                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:39: Define or directive not defined: \'`reg_addr_bus\'\n    output wire [`reg_addr_bus]         r_reg_addr_1_o,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:40: Define or directive not defined: \'`reg_addr_bus\'\n    output wire [`reg_addr_bus]         r_reg_addr_2_o,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:41: Define or directive not defined: \'`csr_addr_bus\'\n    output wire [`csr_addr_bus]         r_csr_addr_o,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:43: Define or directive not defined: \'`reg_data_bus\'\n    output wire [`reg_data_bus]         r_reg_data_1_o,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:44: Define or directive not defined: \'`reg_data_bus\'\n    output wire [`reg_data_bus]         r_reg_data_2_o,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:45: Define or directive not defined: \'`imm_data_bus\'\n    output wire [`imm_data_bus]         imm_data_o,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:46: Define or directive not defined: \'`csr_data_bus\'\n    output wire [`csr_data_bus]         r_csr_data_o,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:47: Define or directive not defined: \'`inst_addr_bus\'\n    output wire [`inst_addr_bus]        r_pc_data_o,\n                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:50: Define or directive not defined: \'`alu_inst_bus\'\n    output wire [`alu_inst_bus]         alu_inst_o,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:53: Define or directive not defined: \'`inst_bus\'\n    output wire [`inst_bus]             r_inst_o,\n                 ^~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:56: Define or directive not defined: \'`reg_addr_bus\'\n    output wire [`reg_addr_bus]         w_reg_addr_o,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:57: Define or directive not defined: \'`csr_addr_bus\'\n    output wire [`csr_addr_bus]         w_csr_addr_o,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:60: Define or directive not defined: \'`data_type_bus\'\n    output wire [`data_type_bus]        data_type_o\n                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:63: Define or directive not defined: \'`hold_flush\'\n    wire hold_flush = (hold_flag_i == `hold_flush);\n                                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:63: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    wire hold_flush = (hold_flag_i == `hold_flush);\n                                                 ^\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:64: Define or directive not defined: \'`hold_wait\'\n    wire hold_wait = (hold_flag_i == `hold_wait);\n                                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:64: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    wire hold_wait = (hold_flag_i == `hold_wait);\n                                               ^\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:67: Define or directive not defined: \'`reg_data_bus_width\'\n        .dw (`reg_data_bus_width)\n             ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:73: Define or directive not defined: \'`data_zero\'\n        .default_data_i (`data_zero     ),\n                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:79: Define or directive not defined: \'`reg_addr_bus_width\'\n        .dw (`reg_addr_bus_width)\n             ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:85: Define or directive not defined: \'`reg_zero\'\n        .default_data_i (`reg_zero      ),\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:91: Define or directive not defined: \'`reg_data_bus_width\'\n        .dw (`reg_data_bus_width)\n             ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:97: Define or directive not defined: \'`data_zero\'\n        .default_data_i (`data_zero     ),\n                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:103: Define or directive not defined: \'`reg_addr_bus_width\'\n        .dw (`reg_addr_bus_width)\n             ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:109: Define or directive not defined: \'`reg_zero\'\n        .default_data_i (`reg_zero      ),\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:115: Define or directive not defined: \'`csr_addr_bus_width\'\n        .dw (`csr_addr_bus_width)\n             ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:121: Define or directive not defined: \'`csr_zero\'\n        .default_data_i (`csr_zero      ),\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:127: Define or directive not defined: \'`csr_data_bus_width\'\n        .dw (`csr_data_bus_width)\n             ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:133: Define or directive not defined: \'`csr_zero\'\n        .default_data_i (`csr_zero      ),\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:139: Define or directive not defined: \'`data_bus_width\'\n        .dw (`data_bus_width)\n             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:145: Define or directive not defined: \'`data_zero\'\n        .default_data_i (`data_zero     ),\n                         ^~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:151: Define or directive not defined: \'`inst_addr_bus_width\'\n        .dw (`inst_addr_bus_width)\n             ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:157: Define or directive not defined: \'`inst_addr_zero\'\n        .default_data_i (`inst_addr_zero),\n                         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476296842/rtl/core/id_ex.v:163: Define or directive not defined: \'`alu_inst_bus_width\'\n        .dw (`alu_inst_bus_width)\n             ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module id_ex (
    input wire                          clk,
    input wire                          rst_n,
    input wire [`holdpip_bus]           hold_flag_i,

    input wire [`reg_addr_bus]          r_reg_addr_1_i,
    input wire [`reg_addr_bus]          r_reg_addr_2_i,
    input wire [`csr_addr_bus]          r_csr_addr_i,

    input wire [`reg_data_bus]          r_reg_data_1_i,
    input wire [`reg_data_bus]          r_reg_data_2_i,
    input wire [`imm_data_bus]          imm_data_i,
    input wire [`csr_data_bus]          r_csr_data_i,
    input wire [`inst_addr_bus]         r_pc_data_i,
    

    input wire [`alu_inst_bus]          alu_inst_i,
    

    input wire [`inst_bus]              r_inst_i,


    input wire [`reg_addr_bus]          w_reg_addr_i,
    input wire [`csr_addr_bus]          w_csr_addr_i,


    input wire [`data_type_bus]         data_type_i,

    output wire [`reg_addr_bus]         r_reg_addr_1_o,
    output wire [`reg_addr_bus]         r_reg_addr_2_o,
    output wire [`csr_addr_bus]         r_csr_addr_o,

    output wire [`reg_data_bus]         r_reg_data_1_o,
    output wire [`reg_data_bus]         r_reg_data_2_o,
    output wire [`imm_data_bus]         imm_data_o,
    output wire [`csr_data_bus]         r_csr_data_o,
    output wire [`inst_addr_bus]        r_pc_data_o,
    

    output wire [`alu_inst_bus]         alu_inst_o,
    

    output wire [`inst_bus]             r_inst_o,


    output wire [`reg_addr_bus]         w_reg_addr_o,
    output wire [`csr_addr_bus]         w_csr_addr_o,


    output wire [`data_type_bus]        data_type_o
);

    wire hold_flush = (hold_flag_i == `hold_flush);
    wire hold_wait = (hold_flag_i == `hold_wait);

    pipe_reg_s #(
        .dw (`reg_data_bus_width)
    ) pipe_r_reg_data_1 (
    	.clk            (clk            ),
        .rst_n          (rst_n          ),
        .set_default    (hold_flush     ),
        .hold_en        (hold_wait      ),
        .default_data_i (`data_zero     ),
        .data_i         (r_reg_data_1_i ),
        .data_o         (r_reg_data_1_o )
    );

    pipe_reg_s #(
        .dw (`reg_addr_bus_width)
    ) pipe_r_reg_addr_1 (
    	.clk            (clk            ),
        .rst_n          (rst_n          ),
        .set_default    (hold_flush     ),
        .hold_en        (hold_wait      ),
        .default_data_i (`reg_zero      ),
        .data_i         (r_reg_addr_1_i ),
        .data_o         (r_reg_addr_1_o )
    );

    pipe_reg_s #(
        .dw (`reg_data_bus_width)
    ) pipe_r_reg_data_2 (
    	.clk            (clk            ),
        .rst_n          (rst_n          ),
        .set_default    (hold_flush     ),
        .hold_en        (hold_wait      ),
        .default_data_i (`data_zero     ),
        .data_i         (r_reg_data_2_i ),
        .data_o         (r_reg_data_2_o )
    );

    pipe_reg_s #(
        .dw (`reg_addr_bus_width)
    ) pipe_r_reg_addr_2 (
    	.clk            (clk            ),
        .rst_n          (rst_n          ),
        .set_default    (hold_flush     ),
        .hold_en        (hold_wait      ),
        .default_data_i (`reg_zero      ),
        .data_i         (r_reg_addr_2_i ),
        .data_o         (r_reg_addr_2_o )
    );

    pipe_reg_s #(
        .dw (`csr_addr_bus_width)
    ) pipe_r_csr_addr (
    	.clk            (clk            ),
        .rst_n          (rst_n          ),
        .set_default    (hold_flush     ),
        .hold_en        (hold_wait      ),
        .default_data_i (`csr_zero      ),
        .data_i         (r_csr_addr_i   ),
        .data_o         (r_csr_addr_o   )
    );

    pipe_reg_s #(
        .dw (`csr_data_bus_width)
    ) pipe_r_csr_data (
    	.clk            (clk            ),
        .rst_n          (rst_n          ),
        .set_default    (hold_flush     ),
        .hold_en        (hold_wait      ),
        .default_data_i (`csr_zero      ),
        .data_i         (r_csr_data_i   ),
        .data_o         (r_csr_data_o   )
    );

    pipe_reg_s #(
        .dw (`data_bus_width)
    ) pipe_imm_data (
    	.clk            (clk            ),
        .rst_n          (rst_n          ),
        .set_default    (hold_flush     ),
        .hold_en        (hold_wait      ),
        .default_data_i (`data_zero     ),
        .data_i         (imm_data_i     ),
        .data_o         (imm_data_o     )
    );

    pipe_reg_s #(
        .dw (`inst_addr_bus_width)
    ) pipe_pc_data (
    	.clk            (clk            ),
        .rst_n          (rst_n          ),
        .set_default    (hold_flush     ),
        .hold_en        (hold_wait      ),
        .default_data_i (`inst_addr_zero),
        .data_i         (r_pc_data_i    ),
        .data_o         (r_pc_data_o    )
    );

    pipe_reg_s #(
        .dw (`alu_inst_bus_width)
    ) pipe_alu_inst (
    	.clk            (clk            ),
        .rst_n          (rst_n          ),
        .set_default    (hold_flush     ),
        .hold_en        (hold_wait      ),
        .default_data_i (`alu_no        ),
        .data_i         (alu_inst_i     ),
        .data_o         (alu_inst_o     )
    );

    pipe_reg_s #(
        .dw (`inst_bus_width)
    ) pipe_r_inst (
    	.clk            (clk            ),
        .rst_n          (rst_n          ),
        .set_default    (hold_flush     ),
        .hold_en        (hold_wait      ),
        .default_data_i (`inst_nop      ),
        .data_i         (r_inst_i       ),
        .data_o         (r_inst_o       )
    );

    pipe_reg_s #(
        .dw (`reg_addr_bus_width)
    ) pipe_w_reg_addr (
    	.clk            (clk            ),
        .rst_n          (rst_n          ),
        .set_default    (hold_flush     ),
        .hold_en        (hold_wait      ),
        .default_data_i (`reg_zero      ),
        .data_i         (w_reg_addr_i   ),
        .data_o         (w_reg_addr_o   )
    );

    pipe_reg_s #(
        .dw (`csr_addr_bus_width)
    ) pipe_w_csr_addr (
    	.clk            (clk            ),
        .rst_n          (rst_n          ),
        .set_default    (hold_flush     ),
        .hold_en        (hold_wait      ),
        .default_data_i (`csr_zero      ),
        .data_i         (w_csr_addr_i   ),
        .data_o         (w_csr_addr_o   )
    );

    pipe_reg_s #(
        .dw (`data_type_bus_width)
    ) pipe_data_type (
    	.clk            (clk            ),
        .rst_n          (rst_n          ),
        .set_default    (hold_flush     ),
        .hold_en        (hold_wait      ),
        .default_data_i (`datatype_no   ),
        .data_i         (data_type_i    ),
        .data_o         (data_type_o    )
    );

    
    
endmodule
module id_ex (
    input wire                          clk,
    input wire                          rst_n,
    input wire [`holdpip_bus]           hold_flag_i,

    input wire [`reg_addr_bus]          r_reg_addr_1_i,
    input wire [`reg_addr_bus]          r_reg_addr_2_i,
    input wire [`csr_addr_bus]          r_csr_addr_i,

    input wire [`reg_data_bus]          r_reg_data_1_i,
    input wire [`reg_data_bus]          r_reg_data_2_i,
    input wire [`imm_data_bus]          imm_data_i,
    input wire [`csr_data_bus]          r_csr_data_i,
    input wire [`inst_addr_bus]         r_pc_data_i,
    

    input wire [`alu_inst_bus]          alu_inst_i,
    

    input wire [`inst_bus]              r_inst_i,


    input wire [`reg_addr_bus]          w_reg_addr_i,
    input wire [`csr_addr_bus]          w_csr_addr_i,


    input wire [`data_type_bus]         data_type_i,

    output wire [`reg_addr_bus]         r_reg_addr_1_o,
    output wire [`reg_addr_bus]         r_reg_addr_2_o,
    output wire [`csr_addr_bus]         r_csr_addr_o,

    output wire [`reg_data_bus]         r_reg_data_1_o,
    output wire [`reg_data_bus]         r_reg_data_2_o,
    output wire [`imm_data_bus]         imm_data_o,
    output wire [`csr_data_bus]         r_csr_data_o,
    output wire [`inst_addr_bus]        r_pc_data_o,
    

    output wire [`alu_inst_bus]         alu_inst_o,
    

    output wire [`inst_bus]             r_inst_o,


    output wire [`reg_addr_bus]         w_reg_addr_o,
    output wire [`csr_addr_bus]         w_csr_addr_o,


    output wire [`data_type_bus]        data_type_o
);


    wire hold_flush = (hold_flag_i == `hold_flush);
    wire hold_wait = (hold_flag_i == `hold_wait);

    pipe_reg_s #(
        .dw (`reg_data_bus_width)
    ) pipe_r_reg_data_1 (
    	.clk            (clk            ),
        .rst_n          (rst_n          ),
        .set_default    (hold_flush     ),
        .hold_en        (hold_wait      ),
        .default_data_i (`data_zero     ),
        .data_i         (r_reg_data_1_i ),
        .data_o         (r_reg_data_1_o )
    );

    pipe_reg_s #(
        .dw (`reg_addr_bus_width)
    ) pipe_r_reg_addr_1 (
    	.clk            (clk            ),
        .rst_n          (rst_n          ),
        .set_default    (hold_flush     ),
        .hold_en        (hold_wait      ),
        .default_data_i (`reg_zero      ),
        .data_i         (r_reg_addr_1_i ),
        .data_o         (r_reg_addr_1_o )
    );

    pipe_reg_s #(
        .dw (`reg_data_bus_width)
    ) pipe_r_reg_data_2 (
    	.clk            (clk            ),
        .rst_n          (rst_n          ),
        .set_default    (hold_flush     ),
        .hold_en        (hold_wait      ),
        .default_data_i (`data_zero     ),
        .data_i         (r_reg_data_2_i ),
        .data_o         (r_reg_data_2_o )
    );

    pipe_reg_s #(
        .dw (`reg_addr_bus_width)
    ) pipe_r_reg_addr_2 (
    	.clk            (clk            ),
        .rst_n          (rst_n          ),
        .set_default    (hold_flush     ),
        .hold_en        (hold_wait      ),
        .default_data_i (`reg_zero      ),
        .data_i         (r_reg_addr_2_i ),
        .data_o         (r_reg_addr_2_o )
    );

    pipe_reg_s #(
        .dw (`csr_addr_bus_width)
    ) pipe_r_csr_addr (
    	.clk            (clk            ),
        .rst_n          (rst_n          ),
        .set_default    (hold_flush     ),
        .hold_en        (hold_wait      ),
        .default_data_i (`csr_zero      ),
        .data_i         (r_csr_addr_i   ),
        .data_o         (r_csr_addr_o   )
    );

    pipe_reg_s #(
        .dw (`csr_data_bus_width)
    ) pipe_r_csr_data (
    	.clk            (clk            ),
        .rst_n          (rst_n          ),
        .set_default    (hold_flush     ),
        .hold_en        (hold_wait      ),
        .default_data_i (`csr_zero      ),
        .data_i         (r_csr_data_i   ),
        .data_o         (r_csr_data_o   )
    );

    pipe_reg_s #(
        .dw (`data_bus_width)
    ) pipe_imm_data (
    	.clk            (clk            ),
        .rst_n          (rst_n          ),
        .set_default    (hold_flush     ),
        .hold_en        (hold_wait      ),
        .default_data_i (`data_zero     ),
        .data_i         (imm_data_i     ),
        .data_o         (imm_data_o     )
    );

    pipe_reg_s #(
        .dw (`inst_addr_bus_width)
    ) pipe_pc_data (
    	.clk            (clk            ),
        .rst_n          (rst_n          ),
        .set_default    (hold_flush     ),
        .hold_en        (hold_wait      ),
        .default_data_i (`inst_addr_zero),
        .data_i         (r_pc_data_i    ),
        .data_o         (r_pc_data_o    )
    );

    pipe_reg_s #(
        .dw (`alu_inst_bus_width)
    ) pipe_alu_inst (
    	.clk            (clk            ),
        .rst_n          (rst_n          ),
        .set_default    (hold_flush     ),
        .hold_en        (hold_wait      ),
        .default_data_i (`alu_no        ),
        .data_i         (alu_inst_i     ),
        .data_o         (alu_inst_o     )
    );

    pipe_reg_s #(
        .dw (`inst_bus_width)
    ) pipe_r_inst (
    	.clk            (clk            ),
        .rst_n          (rst_n          ),
        .set_default    (hold_flush     ),
        .hold_en        (hold_wait      ),
        .default_data_i (`inst_nop      ),
        .data_i         (r_inst_i       ),
        .data_o         (r_inst_o       )
    );

    pipe_reg_s #(
        .dw (`reg_addr_bus_width)
    ) pipe_w_reg_addr (
    	.clk            (clk            ),
        .rst_n          (rst_n          ),
        .set_default    (hold_flush     ),
        .hold_en        (hold_wait      ),
        .default_data_i (`reg_zero      ),
        .data_i         (w_reg_addr_i   ),
        .data_o         (w_reg_addr_o   )
    );

    pipe_reg_s #(
        .dw (`csr_addr_bus_width)
    ) pipe_w_csr_addr (
    	.clk            (clk            ),
        .rst_n          (rst_n          ),
        .set_default    (hold_flush     ),
        .hold_en        (hold_wait      ),
        .default_data_i (`csr_zero      ),
        .data_i         (w_csr_addr_i   ),
        .data_o         (w_csr_addr_o   )
    );

    pipe_reg_s #(
        .dw (`data_type_bus_width)
    ) pipe_data_type (
    	.clk            (clk            ),
        .rst_n          (rst_n          ),
        .set_default    (hold_flush     ),
        .hold_en        (hold_wait      ),
        .default_data_i (`datatype_no   ),
        .data_i         (data_type_i    ),
        .data_o         (data_type_o    )
    );

    
    
endmodule