data/full_repos/permissive/419538859/lab4/lab4_2/lab4_2.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/419538859/lab4/lab4_2/lab4_2.v:12: Signal definition not found, creating implicitly: \'clk_idx\'\nfreq_div#(22) M1 (clk,reset,clk_idx);\n                            ^~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/419538859/lab4/lab4_2/lab4_2.v:13: Signal definition not found, creating implicitly: \'clk_row\'\nfreq_div#(12) M2 (clk,reset,clk_row);\n                            ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab4/lab4_2/lab4_2.v:163: Operator ADD expects 7 bits on the RHS, but RHS\'s VARREF \'cnt\' generates 3 bits.\n                                                                             : ... In instance lab4_2.M4\n  idx_cnt =idx+cnt;    \n              ^\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab4/lab4_2/lab4_2.v:14: Output port connection \'idx\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'idx\' generates 8 bits.\n                                                                            : ... In instance lab4_2\nidx_gen M3 (clk_idx,reset,idx); \n                          ^~~\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab4/lab4_2/lab4_2.v:15: Input port connection \'idx\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'idx\' generates 8 bits.\n                                                                            : ... In instance lab4_2\nrow_gen M4 (clk_row,reset, idx, row, idx_cnt);\n                           ^~~\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab4/lab4_2/lab4_2.v:15: Output port connection \'idx_cnt\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'idx_cnt\' generates 8 bits.\n                                                                            : ... In instance lab4_2\nrow_gen M4 (clk_row,reset, idx, row, idx_cnt);\n                                     ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab4/lab4_2/lab4_2.v:16: Input port connection \'addr\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'idx_cnt\' generates 8 bits.\n                                                                            : ... In instance lab4_2\nrom_char M5 (idx_cnt, column_out);\n             ^~~~~~~\n%Error: Exiting due to 7 warning(s)\n'
module 		freq_div(clk_in,reset,clk_out);

parameter	exp = 20;   
input		clk_in, reset;
output		clk_out;
reg			[exp-1:0] divider;
integer 	i;

assign 	clk_out= divider[exp-1];

always@ (posedge clk_in or posedge reset)
begin
	if(reset)
		for(i=0; i < exp; i=i+1)
		divider[i] = 1'b0;
	else
		divider = divider+ 1'b1;
end
endmodule
module 		freq_div(clk_in,reset,clk_out);


parameter	exp = 20;   
input		clk_in, reset;
output		clk_out;
reg			[exp-1:0] divider;
integer 	i;

assign 	clk_out= divider[exp-1];

always@ (posedge clk_in or posedge reset)
begin
	if(reset)
		for(i=0; i < exp; i=i+1)
		divider[i] = 1'b0;
	else
		divider = divider+ 1'b1;
end
endmodule