data/full_repos/permissive/429196919/FPGA/ws2811Decoder/ws2811Decoder.v
1: b'%Error: data/full_repos/permissive/429196919/FPGA/ws2811Decoder/ws2811Decoder.v:31: Cannot find include file: ../genericIOSateliteEnv.v\n `include "../genericIOSateliteEnv.v" \n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/429196919/FPGA/ws2811Decoder,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v\n             data/full_repos/permissive/429196919/FPGA/ws2811Decoder,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v.v\n             data/full_repos/permissive/429196919/FPGA/ws2811Decoder,data/full_repos/permissive/429196919/../genericIOSateliteEnv.v.sv\n             ../genericIOSateliteEnv.v\n             ../genericIOSateliteEnv.v.v\n             ../genericIOSateliteEnv.v.sv\n             obj_dir/../genericIOSateliteEnv.v\n             obj_dir/../genericIOSateliteEnv.v.v\n             obj_dir/../genericIOSateliteEnv.v.sv\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Decoder/ws2811Decoder.v:77: Define or directive not defined: \'`RESET_CYC\'\n  else if(cnt2 > `RESET_CYC) begin            \n                 ^~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Decoder/ws2811Decoder.v:77: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  else if(cnt2 > `RESET_CYC) begin            \n                           ^\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Decoder/ws2811Decoder.v:81: syntax error, unexpected else\n  else if(active)\n  ^~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Decoder/ws2811Decoder.v:85: Define or directive not defined: \'`T1HTRES_CYC\'\n   if(cnt1 > `T1HTRES_CYC)              \n             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Decoder/ws2811Decoder.v:85: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n   if(cnt1 > `T1HTRES_CYC)              \n                         ^\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Decoder/ws2811Decoder.v:90: Define or directive not defined: \'`K800_HALF_CYC\'\n  if(cnt1 >= `K800_HALF_CYC)              \n             ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Decoder/ws2811Decoder.v:90: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  if(cnt1 >= `K800_HALF_CYC)              \n                           ^\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Decoder/ws2811Decoder.v:92: Define or directive not defined: \'`K800_CYC\'\n  if(cnt1 > `K800_CYC || cnt1 < `K800_HALF_CYC) begin        \n            ^~~~~~~~~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Decoder/ws2811Decoder.v:92: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\n  if(cnt1 > `K800_CYC || cnt1 < `K800_HALF_CYC) begin        \n                      ^~\n%Error: data/full_repos/permissive/429196919/FPGA/ws2811Decoder/ws2811Decoder.v:92: Define or directive not defined: \'`K800_HALF_CYC\'\n  if(cnt1 > `K800_CYC || cnt1 < `K800_HALF_CYC) begin        \n                                ^~~~~~~~~~~~~~\n%Error: Cannot continue\n'
module ws2811Decoder (input masterClk,
					  input dataIn,
					  output reg dataOut,
					  output reg dataClk,
					  output reg active);

	reg[15:0] cnt1 = 0;
	reg[15:0] cnt2 = 0;

	reg dataInMeta = 1'b0;
	reg dataInReclocked = 1'b0;
	



	reg prevDataInReclocked = 1'b0;

	always @ (posedge masterClk) begin
		prevDataInReclocked <= dataInReclocked;
	end
	
	`define DECODE_DATAIN_RECLOCKED_POSEDGE (dataInReclocked && !prevDataInReclocked)
	`define DECODE_DATAIN_RECLOCKED_NEGEDGE (!dataInReclocked && prevDataInReclocked)





	always @ (posedge masterClk) begin
		dataInMeta <= dataIn;
		dataInReclocked <= dataInMeta;
		prevDataInReclocked <= dataInReclocked;

		if(`DECODE_DATAIN_RECLOCKED_POSEDGE) begin
			active <= 1;
			cnt1 <= 0;
		end
		else if (active)
			cnt1 <= cnt1 + 1'b1;

		if(dataInReclocked)
			cnt2 <= 0;
		else if(cnt2 > `RESET_CYC) begin
			active <= 0;
			cnt2 <= 0;
		end
		else if(active)
			cnt2 <= cnt2 + 1'b1;

		if(`DECODE_DATAIN_RECLOCKED_NEGEDGE) begin
			if(cnt1 > `T1HTRES_CYC)
				dataOut <= 1;
			else
				dataOut <= 0;
		end
		if(cnt1 >= `K800_HALF_CYC)
			dataClk <= 0;
		if(cnt1 > `K800_CYC || cnt1 < `K800_HALF_CYC) begin
			dataClk <= 1;
		end
	end

endmodule
module ws2811Decoder (input masterClk,
					  input dataIn,
					  output reg dataOut,
					  output reg dataClk,
					  output reg active);


	reg[15:0] cnt1 = 0;
	reg[15:0] cnt2 = 0;

	reg dataInMeta = 1'b0;
	reg dataInReclocked = 1'b0;
	



	reg prevDataInReclocked = 1'b0;

	always @ (posedge masterClk) begin
		prevDataInReclocked <= dataInReclocked;
	end
	
	`define DECODE_DATAIN_RECLOCKED_POSEDGE (dataInReclocked && !prevDataInReclocked)
	`define DECODE_DATAIN_RECLOCKED_NEGEDGE (!dataInReclocked && prevDataInReclocked)





	always @ (posedge masterClk) begin
		dataInMeta <= dataIn;
		dataInReclocked <= dataInMeta;
		prevDataInReclocked <= dataInReclocked;

		if(`DECODE_DATAIN_RECLOCKED_POSEDGE) begin
			active <= 1;
			cnt1 <= 0;
		end
		else if (active)
			cnt1 <= cnt1 + 1'b1;

		if(dataInReclocked)
			cnt2 <= 0;
		else if(cnt2 > `RESET_CYC) begin
			active <= 0;
			cnt2 <= 0;
		end
		else if(active)
			cnt2 <= cnt2 + 1'b1;

		if(`DECODE_DATAIN_RECLOCKED_NEGEDGE) begin
			if(cnt1 > `T1HTRES_CYC)
				dataOut <= 1;
			else
				dataOut <= 0;
		end
		if(cnt1 >= `K800_HALF_CYC)
			dataClk <= 0;
		if(cnt1 > `K800_CYC || cnt1 < `K800_HALF_CYC) begin
			dataClk <= 1;
		end
	end

endmodule