data/full_repos/permissive/515135468/verilog/rtl/spm.v
data/verilator_xmls/1aeea747-0eaa-47dd-b534-510811c95339.xml
module spm #(parameter size = 32)(
    input wire              clk, 
    input wire              rst,
    input wire              y,
    input wire [size-1:0]   x,
    output wire             p
);
    wire[size-1:1] pp;
    wire[size-1:0] xy;

    genvar i;

    CSADD csa0 (.clk(clk), .rst(rst), .x(x[0]&y), .y(pp[1]), .sum(p));
    
    generate 
        for(i=1; i<size-1; i=i+1) begin
            CSADD csa (.clk(clk), .rst(rst), .x(x[i]&y), .y(pp[i+1]), .sum(pp[i]));
        end 
    endgenerate
    
    TCMP tcmp (.clk(clk), .rst(rst), .a(x[size-1]&y), .s(pp[size-1]));

endmodule
module spm #(parameter size = 32)(
    input wire              clk, 
    input wire              rst,
    input wire              y,
    input wire [size-1:0]   x,
    output wire             p
);

    wire[size-1:1] pp;
    wire[size-1:0] xy;

    genvar i;

    CSADD csa0 (.clk(clk), .rst(rst), .x(x[0]&y), .y(pp[1]), .sum(p));
    
    generate 
        for(i=1; i<size-1; i=i+1) begin
            CSADD csa (.clk(clk), .rst(rst), .x(x[i]&y), .y(pp[i+1]), .sum(pp[i]));
        end 
    endgenerate
    
    TCMP tcmp (.clk(clk), .rst(rst), .a(x[size-1]&y), .s(pp[size-1]));

endmodule