data/full_repos/permissive/426864978/lab0/src/tb_adder.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/426864978/lab0/src/tb_adder.sv:9: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab0/src/tb_adder.sv:11: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab0/src/tb_adder.sv:13: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab0/src/tb_adder.sv:15: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/426864978/lab0/src/tb_adder.sv:10: Can\'t find definition of variable: \'BOGUS\'\n        BOGUS = 0\'b00010001;\n        ^~~~~\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_adder();
    reg [7:0] TB_SW;
    wire [3:0] TB_LEDR;
    adder adder(.SW(TB_SW), .LEDR(TB_LEDR));
    initial begin
        TB_SW = 0'b00000000;
        #10;
        BOGUS = 0'b00010001;
        #10;
        TB_SW = 0'b00100010;
        #10;
        TB_SW = 0'b01100011;
        #10;
    end
endmodule
module tb_adder();

    reg [7:0] TB_SW;
    wire [3:0] TB_LEDR;
    adder adder(.SW(TB_SW), .LEDR(TB_LEDR));
    initial begin
        TB_SW = 0'b00000000;
        #10;
        BOGUS = 0'b00010001;
        #10;
        TB_SW = 0'b00100010;
        #10;
        TB_SW = 0'b01100011;
        #10;
    end
endmodule