data/full_repos/permissive/503973366/SIM/acc_counter_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/acc_counter_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n            #(10/2) clk = ~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/503973366/SIM/acc_counter_tb.v:53: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/acc_counter_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #(3)\n        ^\n%Error: data/full_repos/permissive/503973366/SIM/acc_counter_tb.v:57: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/acc_counter_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n        #(3)\n        ^\n%Error: data/full_repos/permissive/503973366/SIM/acc_counter_tb.v:65: syntax error, unexpected \'@\'\n                @(posedge clk);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/acc_counter_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n                #(3)\n                ^\n%Error: data/full_repos/permissive/503973366/SIM/acc_counter_tb.v:71: syntax error, unexpected \'@\'\n                @(posedge clk);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/acc_counter_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n                #(3)\n                ^\n%Error: data/full_repos/permissive/503973366/SIM/acc_counter_tb.v:80: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/503973366/SIM/acc_counter_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n            #(3)\n            ^\n%Error: Exiting due to 5 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ACC_COUNTER_TB #(

    parameter PE_SIZE = 14,
    parameter WEIGHT_ROW_NUM = 70,
    parameter WEIGHT_COL_NUM = 294
    )
    (


    );    
    
    reg     clk;
    reg     rst_n;
    reg     psum_en_i;
    wire    ofmap_valid_o;
    wire    fifo_rst_n_o;
    


    ACC_COUNTER #(
        .PE_SIZE        ( PE_SIZE ),
        .WEIGHT_ROW_NUM ( WEIGHT_ROW_NUM ),
        .WEIGHT_COL_NUM ( WEIGHT_COL_NUM )
    )u_ACC_COUNTER(
        .clk            ( clk            ),
        .rst_n          ( rst_n          ),
        .psum_en_i      ( psum_en_i      ),
        .ofmap_valid_o  ( ofmap_valid_o  ),
        .fifo_rst_n_o   ( fifo_rst_n_o   )
    );
    

    initial begin
        clk = 1'b0;
        forever begin
            #(`CLOCK_PERIOD/2) clk = ~clk;
        end
    end

    integer i;
    integer j;

    initial begin

        rst_n = 1'b1;
        psum_en_i = 1'b0;
        

        @(posedge clk);
        #(`DELTA)
        rst_n = 1'b0;
        
        @(posedge clk);
        #(`DELTA)
        rst_n = 1'b1;
        

        for (i=0; i < (WEIGHT_COL_NUM/PE_SIZE) + 3; i=i+1) begin

            repeat(14) begin
                @(posedge clk);
                #(`DELTA)
                psum_en_i = 1'b0;
            end

            for (j=0; j < WEIGHT_ROW_NUM; j=j+1) begin
                @(posedge clk);
                #(`DELTA)
                psum_en_i = 1'b1;
            end
        end
        
        

        repeat (10) begin
            @(posedge clk);
            #(`DELTA)
            psum_en_i = 1'b0;        
        end
        
    end

endmodule
module ACC_COUNTER_TB #(

    parameter PE_SIZE = 14,
    parameter WEIGHT_ROW_NUM = 70,
    parameter WEIGHT_COL_NUM = 294
    )
    (


    );
    
    
    reg     clk;
    reg     rst_n;
    reg     psum_en_i;
    wire    ofmap_valid_o;
    wire    fifo_rst_n_o;
    


    ACC_COUNTER #(
        .PE_SIZE        ( PE_SIZE ),
        .WEIGHT_ROW_NUM ( WEIGHT_ROW_NUM ),
        .WEIGHT_COL_NUM ( WEIGHT_COL_NUM )
    )u_ACC_COUNTER(
        .clk            ( clk            ),
        .rst_n          ( rst_n          ),
        .psum_en_i      ( psum_en_i      ),
        .ofmap_valid_o  ( ofmap_valid_o  ),
        .fifo_rst_n_o   ( fifo_rst_n_o   )
    );
    

    initial begin
        clk = 1'b0;
        forever begin
            #(`CLOCK_PERIOD/2) clk = ~clk;
        end
    end

    integer i;
    integer j;

    initial begin

        rst_n = 1'b1;
        psum_en_i = 1'b0;
        

        @(posedge clk);
        #(`DELTA)
        rst_n = 1'b0;
        
        @(posedge clk);
        #(`DELTA)
        rst_n = 1'b1;
        

        for (i=0; i < (WEIGHT_COL_NUM/PE_SIZE) + 3; i=i+1) begin

            repeat(14) begin
                @(posedge clk);
                #(`DELTA)
                psum_en_i = 1'b0;
            end

            for (j=0; j < WEIGHT_ROW_NUM; j=j+1) begin
                @(posedge clk);
                #(`DELTA)
                psum_en_i = 1'b1;
            end
        end
        
        

        repeat (10) begin
            @(posedge clk);
            #(`DELTA)
            psum_en_i = 1'b0;        
        end
        
    end

endmodule