data/full_repos/permissive/460468583/data/yosys/xilinx/ff_map.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/460468583/data/yosys/xilinx/ff_map.v:29: Multiple top level modules\n                                                                                     : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                     : ... Top module \'$_DFFE_NP0P_\'\nmodule  \\$_DFFE_NP0P_ (input D, C, E, R, output Q);\n        ^~~~~~~~~~~~~\n                                                                                     : ... Top module \'$_DFFE_PP0P_\'\nmodule  \\$_DFFE_PP0P_ (input D, C, E, R, output Q);\n        ^~~~~~~~~~~~~\n                                                                                     : ... Top module \'$_DFFE_NP1P_\'\nmodule  \\$_DFFE_NP1P_ (input D, C, E, R, output Q);\n        ^~~~~~~~~~~~~\n                                                                                     : ... Top module \'$_DFFE_PP1P_\'\nmodule  \\$_DFFE_PP1P_ (input D, C, E, R, output Q);\n        ^~~~~~~~~~~~~\n                                                                                     : ... Top module \'$_DFFSRE_NPPP_\'\nmodule  \\$_DFFSRE_NPPP_ (input D, C, E, S, R, output Q);\n        ^~~~~~~~~~~~~~~\n                                                                                     : ... Top module \'$_DFFSRE_PPPP_\'\nmodule  \\$_DFFSRE_PPPP_ (input D, C, E, S, R, output Q);\n        ^~~~~~~~~~~~~~~\n                                                                                     : ... Top module \'$_SDFFE_NP0P_\'\nmodule  \\$_SDFFE_NP0P_ (input D, C, E, R, output Q);\n        ^~~~~~~~~~~~~~\n                                                                                     : ... Top module \'$_SDFFE_PP0P_\'\nmodule  \\$_SDFFE_PP0P_ (input D, C, E, R, output Q);\n        ^~~~~~~~~~~~~~\n                                                                                     : ... Top module \'$_SDFFE_NP1P_\'\nmodule  \\$_SDFFE_NP1P_ (input D, C, E, R, output Q);\n        ^~~~~~~~~~~~~~\n                                                                                     : ... Top module \'$_SDFFE_PP1P_\'\nmodule  \\$_SDFFE_PP1P_ (input D, C, E, R, output Q);\n        ^~~~~~~~~~~~~~\n                                                                                     : ... Top module \'$_DLATCH_NP0_\'\nmodule  \\$_DLATCH_NP0_ (input E, R, D, output Q);\n        ^~~~~~~~~~~~~~\n                                                                                     : ... Top module \'$_DLATCH_PP0_\'\nmodule  \\$_DLATCH_PP0_ (input E, R, D, output Q);\n        ^~~~~~~~~~~~~~\n                                                                                     : ... Top module \'$_DLATCH_NP1_\'\nmodule  \\$_DLATCH_NP1_ (input E, R, D, output Q);\n        ^~~~~~~~~~~~~~\n                                                                                     : ... Top module \'$_DLATCH_PP1_\'\nmodule  \\$_DLATCH_PP1_ (input E, R, D, output Q);\n        ^~~~~~~~~~~~~~\n                                                                                     : ... Top module \'$_DLATCH_NPP_\'\nmodule  \\$_DLATCH_NPP_ (input E, S, R, D, output Q);\n        ^~~~~~~~~~~~~~\n                                                                                     : ... Top module \'$_DLATCH_PPP_\'\nmodule  \\$_DLATCH_PPP_ (input E, S, R, D, output Q);\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/xilinx/ff_map.v:115: Cannot find file containing module: \'LDCPE\'\n  LDCPE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1\'b1), .CLR(R), .PRE(S));\n  ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/460468583/data/yosys/xilinx,data/full_repos/permissive/460468583/LDCPE\n             data/full_repos/permissive/460468583/data/yosys/xilinx,data/full_repos/permissive/460468583/LDCPE.v\n             data/full_repos/permissive/460468583/data/yosys/xilinx,data/full_repos/permissive/460468583/LDCPE.sv\n             LDCPE\n             LDCPE.v\n             LDCPE.sv\n             obj_dir/LDCPE\n             obj_dir/LDCPE.v\n             obj_dir/LDCPE.sv\n%Error: data/full_repos/permissive/460468583/data/yosys/xilinx/ff_map.v:110: Cannot find file containing module: \'LDCPE\'\n  LDCPE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1\'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1\'b1), .CLR(R), .PRE(S));\n  ^~~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/xilinx/ff_map.v:102: Cannot find file containing module: \'LDPE\'\n  LDPE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1\'b1), .PRE(R));\n  ^~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/xilinx/ff_map.v:97: Cannot find file containing module: \'LDPE\'\n  LDPE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1\'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1\'b1), .PRE(R));\n  ^~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/xilinx/ff_map.v:92: Cannot find file containing module: \'LDCE\'\n  LDCE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1\'b1), .CLR(R));\n  ^~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/xilinx/ff_map.v:87: Cannot find file containing module: \'LDCE\'\n  LDCE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_G_INVERTED(1\'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .G(E), .GE(1\'b1), .CLR(R));\n  ^~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/xilinx/ff_map.v:79: Cannot find file containing module: \'FDSE\'\n  FDSE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S(R));\n  ^~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/xilinx/ff_map.v:74: Cannot find file containing module: \'FDSE_1\'\n  FDSE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .S(R));\n  ^~~~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/xilinx/ff_map.v:68: Cannot find file containing module: \'FDRE\'\n  FDRE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(R));\n  ^~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/xilinx/ff_map.v:63: Cannot find file containing module: \'FDRE_1\'\n  FDRE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(R));\n  ^~~~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/xilinx/ff_map.v:55: Cannot find file containing module: \'FDCPE\'\n  FDCPE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R), .PRE(S));\n  ^~~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/xilinx/ff_map.v:50: Cannot find file containing module: \'FDCPE\'\n  FDCPE #(.INIT(_TECHMAP_WIREINIT_Q_), .IS_C_INVERTED(1\'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R), .PRE(S));\n  ^~~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/xilinx/ff_map.v:42: Cannot find file containing module: \'FDPE\'\n  FDPE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE(R));\n  ^~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/xilinx/ff_map.v:37: Cannot find file containing module: \'FDPE_1\'\n  FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE(R));\n  ^~~~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/xilinx/ff_map.v:31: Cannot find file containing module: \'FDCE\'\n  FDCE   #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R));\n  ^~~~\n%Error: data/full_repos/permissive/460468583/data/yosys/xilinx/ff_map.v:26: Cannot find file containing module: \'FDCE_1\'\n  FDCE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .CLR(R));\n  ^~~~~~\n%Error: Exiting due to 16 error(s), 1 warning(s)\n'
module  \$_DFFE_NP1P_ (input D, C, E, R, output Q);
  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE(R));
  wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module  \$_DFFE_NP1P_ (input D, C, E, R, output Q);

  parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
  FDPE_1 #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .PRE(R));
  wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule