data/full_repos/permissive/503509790/verilog/rtl/VerySimpleCPU_core.v
1: b"%Error: data/full_repos/permissive/503509790/verilog/rtl/VerySimpleCPU_core.v:24: Cannot find file containing module: 'VerySimpleCPU'\n VerySimpleCPU inst_VerySimpleCPU(\n ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/503509790/verilog/rtl,data/full_repos/permissive/503509790/VerySimpleCPU\n             data/full_repos/permissive/503509790/verilog/rtl,data/full_repos/permissive/503509790/VerySimpleCPU.v\n             data/full_repos/permissive/503509790/verilog/rtl,data/full_repos/permissive/503509790/VerySimpleCPU.sv\n             VerySimpleCPU\n             VerySimpleCPU.v\n             VerySimpleCPU.sv\n             obj_dir/VerySimpleCPU\n             obj_dir/VerySimpleCPU.v\n             obj_dir/VerySimpleCPU.sv\n%Error: Exiting due to 1 error(s)\n"
module VerySimpleCPU_core(
	`ifdef USE_POWER_PINS
		inout vccd1,
		inout vssd1,
	`endif


	input  clk,
	input  rst,

	output mem_ctrl_we,
	output [13:0] mem_ctrl_addr,
	output [31:0] mem_ctrl_in,
	input  [31:0] mem_ctrl_out,
	input  mem_ctrl_vld,
	output mem_ctrl_req,


	output done
	);

	VerySimpleCPU inst_VerySimpleCPU(


		.clk(clk),
		.rst(rst),

		.debug_en(1'b1),
		.debug_pc_out(),

		.data_fromRAM(mem_ctrl_out),
		.wrEn(mem_ctrl_we),
		.addr_toRAM(mem_ctrl_addr),
		.data_toRAM(mem_ctrl_in),
		.mem_vld(mem_ctrl_vld),
		.mem_req(mem_ctrl_req),

		.done(done)

	);

endmodule
module VerySimpleCPU_core(
	`ifdef USE_POWER_PINS
		inout vccd1,
		inout vssd1,
	`endif


	input  clk,
	input  rst,

	output mem_ctrl_we,
	output [13:0] mem_ctrl_addr,
	output [31:0] mem_ctrl_in,
	input  [31:0] mem_ctrl_out,
	input  mem_ctrl_vld,
	output mem_ctrl_req,


	output done
	);


	VerySimpleCPU inst_VerySimpleCPU(


		.clk(clk),
		.rst(rst),

		.debug_en(1'b1),
		.debug_pc_out(),

		.data_fromRAM(mem_ctrl_out),
		.wrEn(mem_ctrl_we),
		.addr_toRAM(mem_ctrl_addr),
		.data_toRAM(mem_ctrl_in),
		.mem_vld(mem_ctrl_vld),
		.mem_req(mem_ctrl_req),

		.done(done)

	);

endmodule