data/full_repos/permissive/468929885/verilog/rtl/el_pipeline_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_pipeline_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #100;    \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_pipeline_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n    #1000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_pipeline_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #1000;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_pipeline_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n    #1000;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_pipeline_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n    #2000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_pipeline_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n    #1000;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_pipeline_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n    #1000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_pipeline_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n    #2000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/468929885/verilog/rtl/el_pipeline_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n    #1000;\n    ^\n%Error: data/full_repos/permissive/468929885/verilog/rtl/el_pipeline_tb.v:38: Cannot find file containing module: \'el_pipeline\'\nel_pipeline#\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/468929885/verilog/rtl,data/full_repos/permissive/468929885/el_pipeline\n             data/full_repos/permissive/468929885/verilog/rtl,data/full_repos/permissive/468929885/el_pipeline.v\n             data/full_repos/permissive/468929885/verilog/rtl,data/full_repos/permissive/468929885/el_pipeline.sv\n             el_pipeline\n             el_pipeline.v\n             el_pipeline.sv\n             obj_dir/el_pipeline\n             obj_dir/el_pipeline.v\n             obj_dir/el_pipeline.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module el_pipeline_tb();

parameter LINK_WIDTH  = 2;
parameter RAIL_NUM    = 2;
parameter PIPE_DEPTH  = 10;

wire [LINK_WIDTH*RAIL_NUM-1 : 0] in_p_tb;
reg ack_i_tb = 0;

reg rst_tb = 0;
 
wire [LINK_WIDTH*RAIL_NUM-1 : 0] out_p_tb;
wire ack_o_tb;

genvar pk_idx;
genvar unpk_idx;

`define PACK_ARRAY(PK_WIDTH,PK_LEN,PK_SRC,PK_DEST) generate for (pk_idx=0; pk_idx<(PK_LEN); pk_idx=pk_idx+1) begin assign PK_DEST[((PK_WIDTH)*pk_idx+((PK_WIDTH)-1)):((PK_WIDTH)*pk_idx)] = PK_SRC[pk_idx][((PK_WIDTH)-1):0]; end endgenerate

`define UNPACK_ARRAY(PK_WIDTH,PK_LEN,PK_DEST,PK_SRC) generate for (unpk_idx=0; unpk_idx<(PK_LEN); unpk_idx=unpk_idx+1) begin assign PK_DEST[unpk_idx][((PK_WIDTH)-1):0] = PK_SRC[((PK_WIDTH)*unpk_idx+(PK_WIDTH-1)):((PK_WIDTH)*unpk_idx)]; end endgenerate


reg [RAIL_NUM-1 : 0] in_up_tb [LINK_WIDTH-1 : 0];


`PACK_ARRAY(RAIL_NUM,LINK_WIDTH,in_up_tb,in_p_tb)


wire [RAIL_NUM-1 : 0] out_up_tb [LINK_WIDTH-1 : 0];
`UNPACK_ARRAY(RAIL_NUM,LINK_WIDTH,out_up_tb,out_p_tb)




el_pipeline#
(
	.LINK_WIDTH(LINK_WIDTH),
	.RAIL_NUM(RAIL_NUM),
	.PIPE_DEPTH(PIPE_DEPTH)
)
DUT
(
    .rst(rst_tb),
    
    .ack_o(ack_o_tb),
    .in(in_p_tb),
    
    .ack_i(ack_i_tb),
    .out(out_p_tb)
);

integer in_idx;

initial
begin
    for (in_idx = 0; in_idx < RAIL_NUM ; in_idx = in_idx + 1)
    begin
        in_up_tb[in_idx] <= 0;
    end

    rst_tb = 1;
    #100;    
    rst_tb = 0;
    
    #1000;

    in_up_tb[0][0] = !in_up_tb[0][0];
    #1000;  

    in_up_tb[1][1] = !in_up_tb[1][1];   
    #1000;  
    
    #2000;

    in_up_tb[1][0] = !in_up_tb[1][0];
    #1000;  

    in_up_tb[0][1] = !in_up_tb[0][1];   
    #1000;
    
    #2000;
    ack_i_tb = !ack_i_tb;
    
    #1000;
    $finish;  
    
    
    
end

endmodule
module el_pipeline_tb();


parameter LINK_WIDTH  = 2;
parameter RAIL_NUM    = 2;
parameter PIPE_DEPTH  = 10;

wire [LINK_WIDTH*RAIL_NUM-1 : 0] in_p_tb;
reg ack_i_tb = 0;

reg rst_tb = 0;
 
wire [LINK_WIDTH*RAIL_NUM-1 : 0] out_p_tb;
wire ack_o_tb;

genvar pk_idx;
genvar unpk_idx;

`define PACK_ARRAY(PK_WIDTH,PK_LEN,PK_SRC,PK_DEST) generate for (pk_idx=0; pk_idx<(PK_LEN); pk_idx=pk_idx+1) begin assign PK_DEST[((PK_WIDTH)*pk_idx+((PK_WIDTH)-1)):((PK_WIDTH)*pk_idx)] = PK_SRC[pk_idx][((PK_WIDTH)-1):0]; end endgenerate

`define UNPACK_ARRAY(PK_WIDTH,PK_LEN,PK_DEST,PK_SRC) generate for (unpk_idx=0; unpk_idx<(PK_LEN); unpk_idx=unpk_idx+1) begin assign PK_DEST[unpk_idx][((PK_WIDTH)-1):0] = PK_SRC[((PK_WIDTH)*unpk_idx+(PK_WIDTH-1)):((PK_WIDTH)*unpk_idx)]; end endgenerate


reg [RAIL_NUM-1 : 0] in_up_tb [LINK_WIDTH-1 : 0];


`PACK_ARRAY(RAIL_NUM,LINK_WIDTH,in_up_tb,in_p_tb)


wire [RAIL_NUM-1 : 0] out_up_tb [LINK_WIDTH-1 : 0];
`UNPACK_ARRAY(RAIL_NUM,LINK_WIDTH,out_up_tb,out_p_tb)




el_pipeline#
(
	.LINK_WIDTH(LINK_WIDTH),
	.RAIL_NUM(RAIL_NUM),
	.PIPE_DEPTH(PIPE_DEPTH)
)
DUT
(
    .rst(rst_tb),
    
    .ack_o(ack_o_tb),
    .in(in_p_tb),
    
    .ack_i(ack_i_tb),
    .out(out_p_tb)
);

integer in_idx;

initial
begin
    for (in_idx = 0; in_idx < RAIL_NUM ; in_idx = in_idx + 1)
    begin
        in_up_tb[in_idx] <= 0;
    end

    rst_tb = 1;
    #100;    
    rst_tb = 0;
    
    #1000;

    in_up_tb[0][0] = !in_up_tb[0][0];
    #1000;  

    in_up_tb[1][1] = !in_up_tb[1][1];   
    #1000;  
    
    #2000;

    in_up_tb[1][0] = !in_up_tb[1][0];
    #1000;  

    in_up_tb[0][1] = !in_up_tb[0][1];   
    #1000;
    
    #2000;
    ack_i_tb = !ack_i_tb;
    
    #1000;
    $finish;  
    
    
    
end

endmodule