data/full_repos/permissive/517906403/RTDC_test.v
1: b'%Error: data/full_repos/permissive/517906403/RTDC_test.v:1: Cannot find include file: RTDC.v\n`include "RTDC.v" \n         ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/517906403,data/full_repos/permissive/517906403/RTDC.v\n             data/full_repos/permissive/517906403,data/full_repos/permissive/517906403/RTDC.v.v\n             data/full_repos/permissive/517906403,data/full_repos/permissive/517906403/RTDC.v.sv\n             RTDC.v\n             RTDC.v.v\n             RTDC.v.sv\n             obj_dir/RTDC.v\n             obj_dir/RTDC.v.v\n             obj_dir/RTDC.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/517906403/RTDC_test.v:28: Unsupported: Ignoring delay on this delayed statement.\nalways #10 clk=~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/517906403/RTDC_test.v:32: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("RTDC_test.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/517906403/RTDC_test.v:33: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,RTDC_test);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/517906403/RTDC_test.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #10;rst=0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/517906403/RTDC_test.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #3000;\n    ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n'
module RTDC_test;


reg clk;
reg rst;


wire [6:0] HRM;
wire [6:0] HRL;
wire [6:0] MIN_M;
wire [6:0] MIN_L;
wire [6:0] SEC_M;
wire [6:0] SEC_L;


RTDC uut(
    .clk(clk),
    .rst(rst),
    .HRM(HRM),
    .HRL(HRL),
    .MIN_M(MIN_M),
    .MIN_L(MIN_L),
    .SEC_M(SEC_M),
    .SEC_L(SEC_L)
);

always #10 clk=~clk;

initial begin

    $dumpfile("RTDC_test.vcd");
    $dumpvars(0,RTDC_test);


    clk=0;rst=1;


    #10;rst=0;
    #3000;
    $finish();



end

endmodule
module RTDC_test;



reg clk;
reg rst;


wire [6:0] HRM;
wire [6:0] HRL;
wire [6:0] MIN_M;
wire [6:0] MIN_L;
wire [6:0] SEC_M;
wire [6:0] SEC_L;


RTDC uut(
    .clk(clk),
    .rst(rst),
    .HRM(HRM),
    .HRL(HRL),
    .MIN_M(MIN_M),
    .MIN_L(MIN_L),
    .SEC_M(SEC_M),
    .SEC_L(SEC_L)
);

always #10 clk=~clk;

initial begin

    $dumpfile("RTDC_test.vcd");
    $dumpvars(0,RTDC_test);


    clk=0;rst=1;


    #10;rst=0;
    #3000;
    $finish();



end

endmodule