data/full_repos/permissive/423547971/FPGA Projects/NEW 7 Segment Clock with NEW Binary Clock Core/top.v
1: b'%Error: Cannot find file containing module: Projects/NEW\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/NEW\n             data/full_repos/permissive/423547971/FPGA/Projects/NEW.v\n             data/full_repos/permissive/423547971/FPGA/Projects/NEW.sv\n             Projects/NEW\n             Projects/NEW.v\n             Projects/NEW.sv\n             obj_dir/Projects/NEW\n             obj_dir/Projects/NEW.v\n             obj_dir/Projects/NEW.sv\n%Error: Cannot find file containing module: 7\n%Error: Cannot find file containing module: Segment\n%Error: Cannot find file containing module: Clock\n%Error: Cannot find file containing module: with\n%Error: Cannot find file containing module: NEW\n%Error: Cannot find file containing module: Binary\n%Error: Cannot find file containing module: Core,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: Core/top.v\n%Error: Exiting due to 10 error(s)\n'
module top(
    input clk_100MHz,
    input reset,
    input tick_hr,
    input tick_min,
    output blink,
    output [0:6] seg,
    output [3:0] an
    );
    

    wire [3:0] min_1s, min_10s, hr_1s, hr_10s;
    
    binary_clock bc(
        .clk_100MHz(clk_100MHz),
        .reset(reset),
        .tick_hr(tick_hr),
        .tick_min(tick_min),
        .tick_1Hz(blink),
        .sec_10s(),
        .sec_1s(),
        .min_10s(min_10s),
        .min_1s(min_1s),
        .hr_10s(hr_10s),
        .hr_1s(hr_1s)
        );
    
    seg_control seg7(
        .clk_100MHz(clk_100MHz),
        .reset(reset),
        .min_1s(min_1s),
        .min_10s(min_10s),
        .hr_1s(hr_1s),
        .hr_10s(hr_10s),
        .seg(seg),
        .an(an)
        );
    
endmodule
module top(
    input clk_100MHz,
    input reset,
    input tick_hr,
    input tick_min,
    output blink,
    output [0:6] seg,
    output [3:0] an
    );

    

    wire [3:0] min_1s, min_10s, hr_1s, hr_10s;
    
    binary_clock bc(
        .clk_100MHz(clk_100MHz),
        .reset(reset),
        .tick_hr(tick_hr),
        .tick_min(tick_min),
        .tick_1Hz(blink),
        .sec_10s(),
        .sec_1s(),
        .min_10s(min_10s),
        .min_1s(min_1s),
        .hr_10s(hr_10s),
        .hr_1s(hr_1s)
        );
    
    seg_control seg7(
        .clk_100MHz(clk_100MHz),
        .reset(reset),
        .min_1s(min_1s),
        .min_10s(min_10s),
        .hr_1s(hr_1s),
        .hr_10s(hr_10s),
        .seg(seg),
        .an(an)
        );
    
endmodule