data/full_repos/permissive/528677531/LAB-7/Q1/QB/q.v
data/verilator_xmls/ed076549-b4a8-46c3-8c2a-ee5cf820328a.xml
module fourtoone(d,s,f);
input [1:0]d;
input [1:0]s;
output f;
reg f;
always @(s)
begin
	case(s)
	0:f=(~d[0]|d[1]);
	1:f=d[0];
	2:f=0;
	3:f=0;
	endcase
end
endmodule
module fourtoone(d,s,f);

input [1:0]d;
input [1:0]s;
output f;
reg f;
always @(s)
begin
	case(s)
	0:f=(~d[0]|d[1]);
	1:f=d[0];
	2:f=0;
	3:f=0;
	endcase
end
endmodule