data/full_repos/permissive/482848318/ALU.v
data/verilator_xmls/df398a7b-7690-4007-b0af-6a164737dd40.xml
module ALU (
	input [3:0] Ain, Bin,
	input [2:0] ALUop,
	output reg [3:0] ALUout
);

	always@(ALUop, Ain, Bin)
		case(ALUop)
			3'b000: ALUout = Ain;
			3'b001: ALUout = Ain | Bin;
			3'b010: ALUout = Ain ^ Bin;
			3'b011: ALUout = Ain & Bin;
			3'b100: ALUout = Ain - Bin;
			3'b101: ALUout = Ain + Bin;
			default: ALUout = Bin;
		endcase

endmodule
module ALU (
	input [3:0] Ain, Bin,
	input [2:0] ALUop,
	output reg [3:0] ALUout
);


	always@(ALUop, Ain, Bin)
		case(ALUop)
			3'b000: ALUout = Ain;
			3'b001: ALUout = Ain | Bin;
			3'b010: ALUout = Ain ^ Bin;
			3'b011: ALUout = Ain & Bin;
			3'b100: ALUout = Ain - Bin;
			3'b101: ALUout = Ain + Bin;
			default: ALUout = Bin;
		endcase

endmodule