data/full_repos/permissive/433225833/Common/buffer_memory_auto_addr.v
1: b"%Error: data/full_repos/permissive/433225833/Common/buffer_memory_auto_addr.v:13: Cannot find file containing module: 'buffer_memory'\n  buffer_memory mem (.addr_wr(count_in), .addr_rd(count_out), .data_in(data_in), \n  ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/433225833/Common,data/full_repos/permissive/433225833/buffer_memory\n             data/full_repos/permissive/433225833/Common,data/full_repos/permissive/433225833/buffer_memory.v\n             data/full_repos/permissive/433225833/Common,data/full_repos/permissive/433225833/buffer_memory.sv\n             buffer_memory\n             buffer_memory.v\n             buffer_memory.sv\n             obj_dir/buffer_memory\n             obj_dir/buffer_memory.v\n             obj_dir/buffer_memory.sv\n%Error: Exiting due to 1 error(s)\n"
module buffer_memory_auto_addr (data_in, rd_en, wr_en, clk, reset, data_out, data_av);
  input [31:0] data_in;
  input rd_en, wr_en, clk, reset;
  output [31:0] data_out;
  output data_av;
  
  wire [31:0] data_in;
  wire rd_en, wr_en, clk, reset;
  wire [31:0] data_out;
  reg data_av;
  
  reg [13:0] count_in, count_out;
  buffer_memory mem (.addr_wr(count_in), .addr_rd(count_out), .data_in(data_in), 
                     .rd_en(rd_en), .wr_en(wr_en), .clk(clk), .reset(reset), .data_out(data_out));
  
  wire data_remain;
  assign data_remain = count_in > count_out;

  always @(posedge clk) begin
    if (reset) begin
      count_in <= 0;
      count_out <= 0;
    end
    else begin
      if (rd_en && data_remain) begin
        count_out <= count_out + 1;
        data_av <= 1;
      end else data_av <= 0;
      if (wr_en)
        count_in <= count_in + 1;
    end
  end
  
endmodule
module buffer_memory_auto_addr (data_in, rd_en, wr_en, clk, reset, data_out, data_av);

  input [31:0] data_in;
  input rd_en, wr_en, clk, reset;
  output [31:0] data_out;
  output data_av;
  
  wire [31:0] data_in;
  wire rd_en, wr_en, clk, reset;
  wire [31:0] data_out;
  reg data_av;
  
  reg [13:0] count_in, count_out;
  buffer_memory mem (.addr_wr(count_in), .addr_rd(count_out), .data_in(data_in), 
                     .rd_en(rd_en), .wr_en(wr_en), .clk(clk), .reset(reset), .data_out(data_out));
  
  wire data_remain;
  assign data_remain = count_in > count_out;

  always @(posedge clk) begin
    if (reset) begin
      count_in <= 0;
      count_out <= 0;
    end
    else begin
      if (rd_en && data_remain) begin
        count_out <= count_out + 1;
        data_av <= 1;
      end else data_av <= 0;
      if (wr_en)
        count_in <= count_in + 1;
    end
  end
  
endmodule