data/full_repos/permissive/515133384/Verilog Code for Design part.v
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/515133384/Verilog\n        ... Looked in:\n             data/full_repos/permissive/515133384,data/full_repos/permissive/515133384/data/full_repos/permissive/515133384/Verilog\n             data/full_repos/permissive/515133384,data/full_repos/permissive/515133384/data/full_repos/permissive/515133384/Verilog.v\n             data/full_repos/permissive/515133384,data/full_repos/permissive/515133384/data/full_repos/permissive/515133384/Verilog.sv\n             data/full_repos/permissive/515133384/Verilog\n             data/full_repos/permissive/515133384/Verilog.v\n             data/full_repos/permissive/515133384/Verilog.sv\n             obj_dir/data/full_repos/permissive/515133384/Verilog\n             obj_dir/data/full_repos/permissive/515133384/Verilog.v\n             obj_dir/data/full_repos/permissive/515133384/Verilog.sv\n%Error: Cannot find file containing module: Code\n%Error: Cannot find file containing module: for\n%Error: Cannot find file containing module: Design\n%Error: Cannot find file containing module: part.v\n%Error: Exiting due to 5 error(s)\n'
module B2C1(x,y8);
  input [7:0]x;
  wire [7:0]yx;
  output [8:0]y8;
  assign yx= ~x+1;
  assign y8={yx[7],yx[7:0]};
endmodule
module B2C1(x,y8);

  input [7:0]x;
  wire [7:0]yx;
  output [8:0]y8;
  assign yx= ~x+1;
  assign y8={yx[7],yx[7:0]};
endmodule