data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_top_intel/montpro.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_top_intel/montpro.v:156: Signal definition not found, creating implicitly: \'adamrscarry\'\n                                                                                                                            : ... Suggested alternative: \'adarscarry\'\n        rsrg <= {adamrscarry,adamrs};\n                 ^~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_top_intel/montpro.v:156: Signal definition not found, creating implicitly: \'adamrs\'\n                                                                                                                            : ... Suggested alternative: \'adars\'\n        rsrg <= {adamrscarry,adamrs};\n                             ^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_top_intel/montpro.v:85: Cannot find file containing module: \'mux_xx1\'\nmux_xx1 #(WID) imxa (ZERO,b,asrg[0],mxao);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_top_intel,data/full_repos/permissive/530013823/mux_xx1\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_top_intel,data/full_repos/permissive/530013823/mux_xx1.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_top_intel,data/full_repos/permissive/530013823/mux_xx1.sv\n             mux_xx1\n             mux_xx1.v\n             mux_xx1.sv\n             obj_dir/mux_xx1\n             obj_dir/mux_xx1.v\n             obj_dir/mux_xx1.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_top_intel/montpro.v:94: Cannot find file containing module: \'aladder\'\naladder ialadder(\n^~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_top_intel/montpro.v:106: Cannot find file containing module: \'mux_xx1\'\nmux_xx1 #(WID) imxm (ZERO,m,adars[0],mxmo);\n^~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_top_intel/montpro.v:112: Cannot find file containing module: \'aladder\'\naladder ialadder2(\n^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_top_intel/montpro.v:156: Operator ASSIGNDLY expects 257 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n                                                                                                                         : ... In instance montpro\n        rsrg <= {adamrscarry,adamrs};\n             ^~\n%Error: Exiting due to 4 error(s), 3 warning(s)\n'
module montpro
    (
     clk,
     rst,
     
     a,
     b,
     m,
     

     ldnew,

     
     r
     );




parameter WID = 256;
parameter ZERO = 0;




input     clk;
input     rst;

input [WID-1:0] a;
input [WID-1:0] b;
input [WID-1:0] m;


input           ldnew;


output [WID:0] r;









reg [WID-1:0]    asrg;

always@(posedge clk)
    begin
    if(rst)
        begin
        asrg <= ZERO;
        end
    else if(ldnew)
        begin
        asrg <= a;
        end




    else
        begin
        asrg <= {1'b0,asrg[WID-1:1]};
        end
    end


wire [WID-1:0] mxao;

mux_xx1 #(WID) imxa (ZERO,b,asrg[0],mxao);


wire [WID-1:0] adari;
wire           adaricarry;
wire [WID-1:0]   adars;
wire             adarscarry;


aladder ialadder(
    .cin(adaricarry),
    .clock(clk),
    .dataa(adari),
    .datab(mxao),
    .cout(adarscarry),
    .result(adars)
                 );


wire [WID-1:0] mxmo;

mux_xx1 #(WID) imxm (ZERO,m,adars[0],mxmo);


wire [WID-1:0]   admrs;
wire             admrscarry;

aladder ialadder2(
    .cin(adarscarry),
    .clock(clk),
    .dataa(adars),
    .datab(mxmo),
    .cout(adamrscarry),
    .result(adamrs)
                 );

reg [1:0]        cnt;

always@(posedge clk)
    begin
    if(rst)
        begin
        cnt <= 2'b00;
        end
    else
        begin
        cnt <= ldnew? 2'b00 : cnt + 2'b01;
        end
    end

wire shiften = cnt == 2'b11;


reg [WID:0]    rsrg;

always@(posedge clk)
    begin
    if(rst)
        begin
        rsrg <= ZERO;
        end
    else if(ldnew)
        begin
        rsrg <= ZERO;
        end




    else if(shiften)
        begin
        rsrg <= {adamrscarry,adamrs};
        end
    end

assign r = rsrg;
assign {adaricarry,adari} = rsrg[WID:0];
  
endmodule
module montpro
    (
     clk,
     rst,
     
     a,
     b,
     m,
     

     ldnew,

     
     r
     );





parameter WID = 256;
parameter ZERO = 0;




input     clk;
input     rst;

input [WID-1:0] a;
input [WID-1:0] b;
input [WID-1:0] m;


input           ldnew;


output [WID:0] r;









reg [WID-1:0]    asrg;

always@(posedge clk)
    begin
    if(rst)
        begin
        asrg <= ZERO;
        end
    else if(ldnew)
        begin
        asrg <= a;
        end




    else
        begin
        asrg <= {1'b0,asrg[WID-1:1]};
        end
    end


wire [WID-1:0] mxao;

mux_xx1 #(WID) imxa (ZERO,b,asrg[0],mxao);


wire [WID-1:0] adari;
wire           adaricarry;
wire [WID-1:0]   adars;
wire             adarscarry;


aladder ialadder(
    .cin(adaricarry),
    .clock(clk),
    .dataa(adari),
    .datab(mxao),
    .cout(adarscarry),
    .result(adars)
                 );


wire [WID-1:0] mxmo;

mux_xx1 #(WID) imxm (ZERO,m,adars[0],mxmo);


wire [WID-1:0]   admrs;
wire             admrscarry;

aladder ialadder2(
    .cin(adarscarry),
    .clock(clk),
    .dataa(adars),
    .datab(mxmo),
    .cout(adamrscarry),
    .result(adamrs)
                 );

reg [1:0]        cnt;

always@(posedge clk)
    begin
    if(rst)
        begin
        cnt <= 2'b00;
        end
    else
        begin
        cnt <= ldnew? 2'b00 : cnt + 2'b01;
        end
    end

wire shiften = cnt == 2'b11;


reg [WID:0]    rsrg;

always@(posedge clk)
    begin
    if(rst)
        begin
        rsrg <= ZERO;
        end
    else if(ldnew)
        begin
        rsrg <= ZERO;
        end




    else if(shiften)
        begin
        rsrg <= {adamrscarry,adamrs};
        end
    end

assign r = rsrg;
assign {adaricarry,adari} = rsrg[WID:0];
  
endmodule