data/full_repos/permissive/435890256/my_riscv/ram.sv
1: b'%Error: data/full_repos/permissive/435890256/my_riscv/ram.sv:3: Cannot find include file: dualport_bus.sv\n`include "dualport_bus.sv" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/435890256/my_riscv,data/full_repos/permissive/435890256/dualport_bus.sv\n             data/full_repos/permissive/435890256/my_riscv,data/full_repos/permissive/435890256/dualport_bus.sv.v\n             data/full_repos/permissive/435890256/my_riscv,data/full_repos/permissive/435890256/dualport_bus.sv.sv\n             dualport_bus.sv\n             dualport_bus.sv.v\n             dualport_bus.sv.sv\n             obj_dir/dualport_bus.sv\n             obj_dir/dualport_bus.sv.v\n             obj_dir/dualport_bus.sv.sv\n%Error: Exiting due to 1 error(s)\n'
module ram(
  input logic clk,
  input logic rst_n,
  input logic i_we,
  input logic [9:0] i_waddr, i_raddr,
  input logic [7:0] i_wdata,
  output logic [7:0] o_rdata
);

logic [7:0] data_ram_cell [0:1023];
    
always_ff @ (posedge clk or negedge rst_n) begin
  if (~rst_n) begin
    o_rdata <= 0;
  end else begin
    o_rdata <= data_ram_cell[i_raddr];
  end
end

always_ff @ (posedge clk or negedge rst_n) begin
  if (~rst_n) begin
    data_ram_cell <= '{default:'0};
  end else if (i_we) begin
    data_ram_cell[i_waddr] <= i_wdata;
  end
end

endmodule
module ram(
  input logic clk,
  input logic rst_n,
  input logic i_we,
  input logic [9:0] i_waddr, i_raddr,
  input logic [7:0] i_wdata,
  output logic [7:0] o_rdata
);


logic [7:0] data_ram_cell [0:1023];
    
always_ff @ (posedge clk or negedge rst_n) begin
  if (~rst_n) begin
    o_rdata <= 0;
  end else begin
    o_rdata <= data_ram_cell[i_raddr];
  end
end

always_ff @ (posedge clk or negedge rst_n) begin
  if (~rst_n) begin
    data_ram_cell <= '{default:'0};
  end else if (i_we) begin
    data_ram_cell[i_waddr] <= i_wdata;
  end
end

endmodule