data/full_repos/permissive/531341619/rtl/exponent_buffer.v
1: b"%Error: data/full_repos/permissive/531341619/rtl/exponent_buffer.v:51: Cannot find file containing module: 'true_dual_port_ram'\n  true_dual_port_ram\n  ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/531341619/rtl,data/full_repos/permissive/531341619/true_dual_port_ram\n             data/full_repos/permissive/531341619/rtl,data/full_repos/permissive/531341619/true_dual_port_ram.v\n             data/full_repos/permissive/531341619/rtl,data/full_repos/permissive/531341619/true_dual_port_ram.sv\n             true_dual_port_ram\n             true_dual_port_ram.v\n             true_dual_port_ram.sv\n             obj_dir/true_dual_port_ram\n             obj_dir/true_dual_port_ram.v\n             obj_dir/true_dual_port_ram.sv\n%Error: Exiting due to 1 error(s)\n"
module exponent_buffer
#(
  parameter DATA_WIDTH = 8,
  parameter BUFFER_ADDR_WIDTH = 15
) (
  input  wire clk, rst_n,

  input  wire activation_rd_en_i, buffer_wr_en_i,
  input  wire [BUFFER_ADDR_WIDTH-1:0] buffer_rd_addr_i, buffer_wr_addr,
  input  wire [DATA_WIDTH-1:0] buffer_data_i,
  output reg [DATA_WIDTH-1:0] buffer_activation_data_o
);

  wire [DATA_WIDTH-1:0] buffer_activation_data;
  reg                            activation_rd_en_0;
  reg                            activation_rd_en_1;
  reg [BUFFER_ADDR_WIDTH-1:0]    buffer_rd_addr_0;
  reg [BUFFER_ADDR_WIDTH-1:0]    buffer_rd_addr_1;


  always @(posedge clk)
  begin
    activation_rd_en_0 <= activation_rd_en_i;
    activation_rd_en_1 <= activation_rd_en_0;
    buffer_rd_addr_0 <= buffer_rd_addr_i;
    buffer_rd_addr_1 <= buffer_rd_addr_0;
    buffer_activation_data_o <= buffer_activation_data + 2;
  end

  true_dual_port_ram
  #(
    .ADDR_WIDTH(BUFFER_ADDR_WIDTH),
    .DATA_WIDTH(DATA_WIDTH)
  ) dual_port_ram(
    .clk(clk), 
    .activation_rd_en_i(activation_rd_en_1),
    .wr_en(buffer_wr_en_i),
    
    .wr_addr(buffer_wr_addr),
    .data_i(buffer_data_i),
    .rd_addr(buffer_rd_addr_1),
    .buffer_activation_data_o(buffer_activation_data)
  );
  endmodule
module exponent_buffer
#(
  parameter DATA_WIDTH = 8,
  parameter BUFFER_ADDR_WIDTH = 15
) (
  input  wire clk, rst_n,

  input  wire activation_rd_en_i, buffer_wr_en_i,
  input  wire [BUFFER_ADDR_WIDTH-1:0] buffer_rd_addr_i, buffer_wr_addr,
  input  wire [DATA_WIDTH-1:0] buffer_data_i,
  output reg [DATA_WIDTH-1:0] buffer_activation_data_o
);


  wire [DATA_WIDTH-1:0] buffer_activation_data;
  reg                            activation_rd_en_0;
  reg                            activation_rd_en_1;
  reg [BUFFER_ADDR_WIDTH-1:0]    buffer_rd_addr_0;
  reg [BUFFER_ADDR_WIDTH-1:0]    buffer_rd_addr_1;


  always @(posedge clk)
  begin
    activation_rd_en_0 <= activation_rd_en_i;
    activation_rd_en_1 <= activation_rd_en_0;
    buffer_rd_addr_0 <= buffer_rd_addr_i;
    buffer_rd_addr_1 <= buffer_rd_addr_0;
    buffer_activation_data_o <= buffer_activation_data + 2;
  end

  true_dual_port_ram
  #(
    .ADDR_WIDTH(BUFFER_ADDR_WIDTH),
    .DATA_WIDTH(DATA_WIDTH)
  ) dual_port_ram(
    .clk(clk), 
    .activation_rd_en_i(activation_rd_en_1),
    .wr_en(buffer_wr_en_i),
    
    .wr_addr(buffer_wr_addr),
    .data_i(buffer_data_i),
    .rd_addr(buffer_rd_addr_1),
    .buffer_activation_data_o(buffer_activation_data)
  );
  endmodule