data/full_repos/permissive/524532083/verilog/rtl/HBrigeDriver.v
data/verilator_xmls/3e54fc4e-3662-4451-9224-6a25d9f39d63.xml
module HBrigeDriver(
  output wire p_out,
  output wire n_out,
  input wire en_n,
  input wire in
);

 assign n_out = en_n ? 1'b0 : in ? 1'b0 : 1'b1; 
 assign p_out = en_n ? 1'b1 : in ? 1'b0 : 1'b1; 

endmodule
module HBrigeDriver(
  output wire p_out,
  output wire n_out,
  input wire en_n,
  input wire in
);


 assign n_out = en_n ? 1'b0 : in ? 1'b0 : 1'b1; 
 assign p_out = en_n ? 1'b1 : in ? 1'b0 : 1'b1; 

endmodule