data/full_repos/permissive/505451992/Con_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/505451992/Con_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n           #500;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/505451992/Con_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n           #500;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/Con_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n           #500;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/Con_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n           #500;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/Con_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n           #500;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/Con_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n           #500;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/Con_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n           #500;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/Con_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n           #500;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/Con_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n           #500;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/Con_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n           #500;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/505451992/Con_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n           forever #5 CLK=~CLK;\n                   ^\n%Error: data/full_repos/permissive/505451992/Con_tb.v:14: Cannot find file containing module: \'Converters\'\n        Converters utt(.PPR(PPR),.P(P),.Position(Position));\n        ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/505451992,data/full_repos/permissive/505451992/Converters\n             data/full_repos/permissive/505451992,data/full_repos/permissive/505451992/Converters.v\n             data/full_repos/permissive/505451992,data/full_repos/permissive/505451992/Converters.sv\n             Converters\n             Converters.v\n             Converters.sv\n             obj_dir/Converters\n             obj_dir/Converters.v\n             obj_dir/Converters.sv\n%Error: Exiting due to 1 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Con_tb(

    );
     
       reg CLK;

       reg[9:0] PPR;
       reg signed [9:0] P;
       wire [9:0] Position;
       
        Converters utt(.PPR(PPR),.P(P),.Position(Position));
        
        
           initial begin
           PPR = 599;
           P = 200;
           #500;
           PPR = 599;
           P = 144;
           #500;
           PPR = 599;
           P = -127;
           #500;
           PPR = 599;
           P = 0;
           #500;
           PPR = 599;
           P = -188;
           #500;
		   
		   
		   PPR = 399;
           P = 200;
           #500;
         
           P = 144;
           #500;
         
           P = -127;
           #500;
     
           P = 0;
           #500;
       
           P = -188;
           #500;
           
           end
               initial begin
           CLK=0;
           forever #5 CLK=~CLK;
           end
        
    
    
    
    
endmodule
module Con_tb(

    );

     
       reg CLK;

       reg[9:0] PPR;
       reg signed [9:0] P;
       wire [9:0] Position;
       
        Converters utt(.PPR(PPR),.P(P),.Position(Position));
        
        
           initial begin
           PPR = 599;
           P = 200;
           #500;
           PPR = 599;
           P = 144;
           #500;
           PPR = 599;
           P = -127;
           #500;
           PPR = 599;
           P = 0;
           #500;
           PPR = 599;
           P = -188;
           #500;
		   
		   
		   PPR = 399;
           P = 200;
           #500;
         
           P = 144;
           #500;
         
           P = -127;
           #500;
     
           P = 0;
           #500;
       
           P = -188;
           #500;
           
           end
               initial begin
           CLK=0;
           forever #5 CLK=~CLK;
           end
        
    
    
    
    
endmodule