data/full_repos/permissive/520452389/source_codes/mem_ld_sv.v
data/verilator_xmls/51d08d3b-81b9-4396-857b-4868e5380a9d.xml
module mem(input clk,input reset,input Branch_s3,input MemWrite_s3,input MemtoReg_s3,input MemRead_s3,input [4:0]write_reg_s3,
        input RegWrite_s3,input [31:0]ALU_result_s3,input [31:0]read_data2_s3,output MemtoReg_s4,output [31:0]read_data3_s4,
        output [31:0]ALU_result_s4,output RegWrite_s4,output [4:0]write_reg_s4,input zero_s3,output pcSrc);
        wire [31:0]read_data3;
        data_memory dm(reset,MemWrite_s3,MemRead_s3,ALU_result_s3,read_data2_s3,read_data3);
        
        and pc(pcSrc, zero_s3, Branch_s3);
        
        dff4 d4(clk,MemtoReg_s3,MemtoReg_s4,read_data3,read_data3_s4,ALU_result_s3,ALU_result_s4,RegWrite_s3,RegWrite_s4,write_reg_s3,write_reg_s4);

endmodule
module mem(input clk,input reset,input Branch_s3,input MemWrite_s3,input MemtoReg_s3,input MemRead_s3,input [4:0]write_reg_s3,
        input RegWrite_s3,input [31:0]ALU_result_s3,input [31:0]read_data2_s3,output MemtoReg_s4,output [31:0]read_data3_s4,
        output [31:0]ALU_result_s4,output RegWrite_s4,output [4:0]write_reg_s4,input zero_s3,output pcSrc);

        wire [31:0]read_data3;
        data_memory dm(reset,MemWrite_s3,MemRead_s3,ALU_result_s3,read_data2_s3,read_data3);
        
        and pc(pcSrc, zero_s3, Branch_s3);
        
        dff4 d4(clk,MemtoReg_s3,MemtoReg_s4,read_data3,read_data3_s4,ALU_result_s3,ALU_result_s4,RegWrite_s3,RegWrite_s4,write_reg_s3,write_reg_s4);

endmodule