data/full_repos/permissive/431687600/Proc_SRC/program_counter.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/431687600/Proc_SRC/program_counter.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #2 PCprev <= o_PCcurr;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/431687600/Proc_SRC/program_counter.v:38: Unsupported: Ignoring delay on this delayed statement.\n   #2 PCprev <= o_PCcurr;\n   ^\n%Warning-WIDTH: data/full_repos/permissive/431687600/Proc_SRC/program_counter.v:40: Operator ADD expects 13 bits on the RHS, but RHS\'s VARREF \'i_Branch\' generates 9 bits.\n                                                                                  : ... In instance PC\n  else o_PCcurr <= i_PC + i_Branch;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/431687600/Proc_SRC/program_counter.v:36: Operator EQ expects 13 bits on the LHS, but LHS\'s VARREF \'i_PCop\' generates 1 bits.\n                                                                                  : ... In instance PC\n  else if((i_PCop == 13\'b0000_000_000_000) && (reset == 1\'b0))begin\n                  ^~\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module PC(
	input clk,reset,i_PCop,
	input [12:0]i_PC,
	input [8:0] i_Branch,
	output reg [12:0] o_PCcurr );

	reg [12:0]PCprev;

	always@(posedge clk) begin
		if(reset == 1'b1)begin
			 o_PCcurr <= 13'b0000_000_000_000;
			 #2 PCprev <= o_PCcurr;
		end
		else if((i_PCop == 13'b0000_000_000_000) && (reset == 1'b0))begin
			o_PCcurr <= PCprev + 13'b0000_000_000_001;
			#2 PCprev <= o_PCcurr;
		end
		else o_PCcurr <= i_PC + i_Branch;
		
	end			
endmodule
module PC(
	input clk,reset,i_PCop,
	input [12:0]i_PC,
	input [8:0] i_Branch,
	output reg [12:0] o_PCcurr );


	reg [12:0]PCprev;

	always@(posedge clk) begin
		if(reset == 1'b1)begin
			 o_PCcurr <= 13'b0000_000_000_000;
			 #2 PCprev <= o_PCcurr;
		end
		else if((i_PCop == 13'b0000_000_000_000) && (reset == 1'b0))begin
			o_PCcurr <= PCprev + 13'b0000_000_000_001;
			#2 PCprev <= o_PCcurr;
		end
		else o_PCcurr <= i_PC + i_Branch;
		
	end			
endmodule