data/full_repos/permissive/427885334/rtl/apu/spdif_tx.v
1: b'%Warning-WIDTH: data/full_repos/permissive/427885334/rtl/apu/spdif_tx.v:155: Bit extraction of var[7:0] requires 3 bit index, not 5 bits.\n                                                                           : ... In instance spdif_tx\n              SPDIF_o <= preamble_w[bit_o_sel];\n                                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/427885334/rtl/apu/spdif_tx.v:157: Bit extraction of var[7:0] requires 3 bit index, not 5 bits.\n                                                                           : ... In instance spdif_tx\n              SPDIF_o <= preamble_m[bit_o_sel];\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/427885334/rtl/apu/spdif_tx.v:159: Bit extraction of var[7:0] requires 3 bit index, not 5 bits.\n                                                                           : ... In instance spdif_tx\n              SPDIF_o <= preamble_b[bit_o_sel];\n                                   ^\n%Error: Exiting due to 3 warning(s)\n'
module spdif_tx (
  MCLK_i,
  nRST_i,


  PDATA_LEFT_i,
  PDATA_RIGHT_i,
  PDATA_VALID_i,


  SPDIF_en,
  SPDIF_o
);

input MCLK_i;
input nRST_i;

input [23:0] PDATA_LEFT_i;
input [23:0] PDATA_RIGHT_i;
input PDATA_VALID_i;

input SPDIF_en;
output reg SPDIF_o;




localparam preamble_b = 8'b00010111;
localparam preamble_m = 8'b01000111;
localparam preamble_w = 8'b00100111;

localparam STATE_INIT       = 3'b000;
localparam STATE_PREAMBLE   = 3'b001;
localparam STATE_AUDIO      = 3'b010;
localparam STATE_VALID_BIT  = 3'b011;
localparam STATE_USER_BIT   = 3'b100;
localparam STATE_CHANNEL_ST = 3'b101;
localparam STATE_PARITY     = 3'b110;


wire mclk_en_w;
wire nRST_SPDIF_enc;


reg signed [23:0] audio_lr_i [0:1];
reg trigger_tx;
reg [1:0] mclk_en_cnt;

reg [2:0] spdif_tx_state;

reg signed [23:0] audio_lr_buf [0:1];
reg [7:0] frame_cnt;
reg subframe_sel;
reg [4:0] bit_o_sel;

reg bmc_phase;




always @(posedge MCLK_i or negedge nRST_i)
  if (!nRST_i) begin
    audio_lr_i[0] <= {24{1'b0}};
    audio_lr_i[1] <= {24{1'b0}};
    trigger_tx <= 1'b0;
    mclk_en_cnt <= 2'b00;
  end else begin
    if (PDATA_VALID_i) begin
      audio_lr_i[0] <= PDATA_LEFT_i;
      audio_lr_i[1] <= PDATA_RIGHT_i;
      trigger_tx <= SPDIF_en;
    end
    if (trigger_tx)
      mclk_en_cnt <= mclk_en_cnt + 2'b01;
    else
      mclk_en_cnt <= 2'b00;
  end

assign mclk_en_w = &mclk_en_cnt;
assign nRST_SPDIF_enc = nRST_i & trigger_tx;









always @(posedge MCLK_i or negedge nRST_SPDIF_enc)
  if (!nRST_SPDIF_enc) begin
    spdif_tx_state <= STATE_INIT;
    audio_lr_buf[0] <= {24{1'b0}};
    audio_lr_buf[1] <= {24{1'b0}};
    frame_cnt <= 8'd0;
    subframe_sel <= 1'b0;
    bit_o_sel <= 5'd0;
    bmc_phase <= 1'b0;
    SPDIF_o <= 1'b0;
  end else begin
    if (mclk_en_w) begin
      case (spdif_tx_state)
        STATE_INIT: begin
            spdif_tx_state <= STATE_PREAMBLE;
            audio_lr_buf[0] <= audio_lr_i[0];
            audio_lr_buf[1] <= audio_lr_i[1];
            frame_cnt <= 8'd0;
            subframe_sel <= 1'b0;
            bit_o_sel <= 5'd0;
            bmc_phase <= 1'b0;
            SPDIF_o <= 1'b0;
          end
        STATE_PREAMBLE: begin
            if (subframe_sel) begin
              SPDIF_o <= preamble_w[bit_o_sel];
            end else if (|frame_cnt) begin
              SPDIF_o <= preamble_m[bit_o_sel];
            end else begin
              SPDIF_o <= preamble_b[bit_o_sel];
            end
            if (bit_o_sel == 5'd7) begin
              spdif_tx_state <= STATE_AUDIO;
              
              bit_o_sel <= 5'd0;

            end else begin
              bit_o_sel <= bit_o_sel + 1'b1;
            end
          end
        STATE_AUDIO: begin
            if (!bmc_phase) begin
              SPDIF_o <= ~SPDIF_o;
            end else begin
              SPDIF_o <= SPDIF_o ^ audio_lr_buf[subframe_sel][bit_o_sel];
              if (bit_o_sel == 5'd23) begin
                spdif_tx_state <= STATE_VALID_BIT;
                bit_o_sel <= 5'd0;
              end else begin
                bit_o_sel <= bit_o_sel + 1'b1;
              end
            end
            bmc_phase <= ~bmc_phase;
          end
        STATE_VALID_BIT: begin
            if (!bmc_phase) begin
              SPDIF_o <= ~SPDIF_o;
            end else begin
              SPDIF_o <= SPDIF_o;
              spdif_tx_state <= STATE_USER_BIT;
            end
            bmc_phase <= ~bmc_phase;
          end
        STATE_USER_BIT: begin
            if (!bmc_phase) begin
              SPDIF_o <= ~SPDIF_o;
            end else begin
              SPDIF_o <= SPDIF_o;
              spdif_tx_state <= STATE_CHANNEL_ST;
            end
            bmc_phase <= ~bmc_phase;
          end
        STATE_CHANNEL_ST: begin
            if (!bmc_phase) begin
              SPDIF_o <= ~SPDIF_o;
            end else begin
              SPDIF_o <= SPDIF_o;
              spdif_tx_state <= STATE_PARITY;
            end
            bmc_phase <= ~bmc_phase;
          end
        STATE_PARITY: begin
            if (!bmc_phase) begin
              SPDIF_o <= ~SPDIF_o;
            end else begin
              SPDIF_o <= 1'b0;
              if (subframe_sel) begin
                if (frame_cnt == 8'd191)
                  frame_cnt <= 8'd0;
                else
                  frame_cnt <= frame_cnt + 1'b1;
              end
              subframe_sel <= ~subframe_sel;
              spdif_tx_state <= STATE_PREAMBLE;
              audio_lr_buf[0] <= audio_lr_i[0];
              audio_lr_buf[1] <= audio_lr_i[1];
            end
            bmc_phase <= ~bmc_phase;
          end
        default: begin
            spdif_tx_state <= STATE_INIT;
          end
      endcase
    end
  end

endmodule
module spdif_tx (
  MCLK_i,
  nRST_i,


  PDATA_LEFT_i,
  PDATA_RIGHT_i,
  PDATA_VALID_i,


  SPDIF_en,
  SPDIF_o
);


input MCLK_i;
input nRST_i;

input [23:0] PDATA_LEFT_i;
input [23:0] PDATA_RIGHT_i;
input PDATA_VALID_i;

input SPDIF_en;
output reg SPDIF_o;




localparam preamble_b = 8'b00010111;
localparam preamble_m = 8'b01000111;
localparam preamble_w = 8'b00100111;

localparam STATE_INIT       = 3'b000;
localparam STATE_PREAMBLE   = 3'b001;
localparam STATE_AUDIO      = 3'b010;
localparam STATE_VALID_BIT  = 3'b011;
localparam STATE_USER_BIT   = 3'b100;
localparam STATE_CHANNEL_ST = 3'b101;
localparam STATE_PARITY     = 3'b110;


wire mclk_en_w;
wire nRST_SPDIF_enc;


reg signed [23:0] audio_lr_i [0:1];
reg trigger_tx;
reg [1:0] mclk_en_cnt;

reg [2:0] spdif_tx_state;

reg signed [23:0] audio_lr_buf [0:1];
reg [7:0] frame_cnt;
reg subframe_sel;
reg [4:0] bit_o_sel;

reg bmc_phase;




always @(posedge MCLK_i or negedge nRST_i)
  if (!nRST_i) begin
    audio_lr_i[0] <= {24{1'b0}};
    audio_lr_i[1] <= {24{1'b0}};
    trigger_tx <= 1'b0;
    mclk_en_cnt <= 2'b00;
  end else begin
    if (PDATA_VALID_i) begin
      audio_lr_i[0] <= PDATA_LEFT_i;
      audio_lr_i[1] <= PDATA_RIGHT_i;
      trigger_tx <= SPDIF_en;
    end
    if (trigger_tx)
      mclk_en_cnt <= mclk_en_cnt + 2'b01;
    else
      mclk_en_cnt <= 2'b00;
  end

assign mclk_en_w = &mclk_en_cnt;
assign nRST_SPDIF_enc = nRST_i & trigger_tx;









always @(posedge MCLK_i or negedge nRST_SPDIF_enc)
  if (!nRST_SPDIF_enc) begin
    spdif_tx_state <= STATE_INIT;
    audio_lr_buf[0] <= {24{1'b0}};
    audio_lr_buf[1] <= {24{1'b0}};
    frame_cnt <= 8'd0;
    subframe_sel <= 1'b0;
    bit_o_sel <= 5'd0;
    bmc_phase <= 1'b0;
    SPDIF_o <= 1'b0;
  end else begin
    if (mclk_en_w) begin
      case (spdif_tx_state)
        STATE_INIT: begin
            spdif_tx_state <= STATE_PREAMBLE;
            audio_lr_buf[0] <= audio_lr_i[0];
            audio_lr_buf[1] <= audio_lr_i[1];
            frame_cnt <= 8'd0;
            subframe_sel <= 1'b0;
            bit_o_sel <= 5'd0;
            bmc_phase <= 1'b0;
            SPDIF_o <= 1'b0;
          end
        STATE_PREAMBLE: begin
            if (subframe_sel) begin
              SPDIF_o <= preamble_w[bit_o_sel];
            end else if (|frame_cnt) begin
              SPDIF_o <= preamble_m[bit_o_sel];
            end else begin
              SPDIF_o <= preamble_b[bit_o_sel];
            end
            if (bit_o_sel == 5'd7) begin
              spdif_tx_state <= STATE_AUDIO;
              
              bit_o_sel <= 5'd0;

            end else begin
              bit_o_sel <= bit_o_sel + 1'b1;
            end
          end
        STATE_AUDIO: begin
            if (!bmc_phase) begin
              SPDIF_o <= ~SPDIF_o;
            end else begin
              SPDIF_o <= SPDIF_o ^ audio_lr_buf[subframe_sel][bit_o_sel];
              if (bit_o_sel == 5'd23) begin
                spdif_tx_state <= STATE_VALID_BIT;
                bit_o_sel <= 5'd0;
              end else begin
                bit_o_sel <= bit_o_sel + 1'b1;
              end
            end
            bmc_phase <= ~bmc_phase;
          end
        STATE_VALID_BIT: begin
            if (!bmc_phase) begin
              SPDIF_o <= ~SPDIF_o;
            end else begin
              SPDIF_o <= SPDIF_o;
              spdif_tx_state <= STATE_USER_BIT;
            end
            bmc_phase <= ~bmc_phase;
          end
        STATE_USER_BIT: begin
            if (!bmc_phase) begin
              SPDIF_o <= ~SPDIF_o;
            end else begin
              SPDIF_o <= SPDIF_o;
              spdif_tx_state <= STATE_CHANNEL_ST;
            end
            bmc_phase <= ~bmc_phase;
          end
        STATE_CHANNEL_ST: begin
            if (!bmc_phase) begin
              SPDIF_o <= ~SPDIF_o;
            end else begin
              SPDIF_o <= SPDIF_o;
              spdif_tx_state <= STATE_PARITY;
            end
            bmc_phase <= ~bmc_phase;
          end
        STATE_PARITY: begin
            if (!bmc_phase) begin
              SPDIF_o <= ~SPDIF_o;
            end else begin
              SPDIF_o <= 1'b0;
              if (subframe_sel) begin
                if (frame_cnt == 8'd191)
                  frame_cnt <= 8'd0;
                else
                  frame_cnt <= frame_cnt + 1'b1;
              end
              subframe_sel <= ~subframe_sel;
              spdif_tx_state <= STATE_PREAMBLE;
              audio_lr_buf[0] <= audio_lr_i[0];
              audio_lr_buf[1] <= audio_lr_i[1];
            end
            bmc_phase <= ~bmc_phase;
          end
        default: begin
            spdif_tx_state <= STATE_INIT;
          end
      endcase
    end
  end

endmodule