data/full_repos/permissive/435885222/sources/regfile.v
data/verilator_xmls/843712b4-7ffd-4fb6-8ba6-f4caed603edc.xml
module regfile(
    input clk,
    input rst,
    input we,
    input [4:0] waddr,
    input [31:0] wdata,
    input re1,
    input [4:0] raddr1,
    input re2,
    input [4:0] raddr2,
    output reg[31:0] rdata1,
    output reg[31:0] rdata2
    );
    reg[31:0] regs[0:31];
    always @(posedge clk)begin
        if((rst==1'b0)&&(we==1'b1)&&(waddr!=5'h0)) regs[waddr]<=wdata;
    end
    always @(*)begin
        if((rst==1'b1)||(raddr1==5'h0)) rdata1<=32'h00000000;
        else if((raddr1==waddr)&&(we==1'b1)&&(re1==1'b1)) rdata1<=wdata;
        else if(re1==1'b1) rdata1<=regs[raddr1];
        else rdata1<=32'h00000000;
    end
    always @(*)begin
        if((rst==1'b1)||(raddr2==5'h0)) rdata2<=32'h00000000;
        else if((raddr2==waddr)&&(we==1'b1)&&(re2==1'b1)) rdata2<=wdata;
        else if(re2==1'b1) rdata2<=regs[raddr2];
        else rdata2<=32'h00000000;
    end
endmodule
module regfile(
    input clk,
    input rst,
    input we,
    input [4:0] waddr,
    input [31:0] wdata,
    input re1,
    input [4:0] raddr1,
    input re2,
    input [4:0] raddr2,
    output reg[31:0] rdata1,
    output reg[31:0] rdata2
    );

    reg[31:0] regs[0:31];
    always @(posedge clk)begin
        if((rst==1'b0)&&(we==1'b1)&&(waddr!=5'h0)) regs[waddr]<=wdata;
    end
    always @(*)begin
        if((rst==1'b1)||(raddr1==5'h0)) rdata1<=32'h00000000;
        else if((raddr1==waddr)&&(we==1'b1)&&(re1==1'b1)) rdata1<=wdata;
        else if(re1==1'b1) rdata1<=regs[raddr1];
        else rdata1<=32'h00000000;
    end
    always @(*)begin
        if((rst==1'b1)||(raddr2==5'h0)) rdata2<=32'h00000000;
        else if((raddr2==waddr)&&(we==1'b1)&&(re2==1'b1)) rdata2<=wdata;
        else if(re2==1'b1) rdata2<=regs[raddr2];
        else rdata2<=32'h00000000;
    end
endmodule