data/full_repos/permissive/517680549/traffic_light_controller_test.v
1: b'%Error: data/full_repos/permissive/517680549/traffic_light_controller_test.v:1: Cannot find include file: traffic_light_controller.v\n`include "traffic_light_controller.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/517680549,data/full_repos/permissive/517680549/traffic_light_controller.v\n             data/full_repos/permissive/517680549,data/full_repos/permissive/517680549/traffic_light_controller.v.v\n             data/full_repos/permissive/517680549,data/full_repos/permissive/517680549/traffic_light_controller.v.sv\n             traffic_light_controller.v\n             traffic_light_controller.v.v\n             traffic_light_controller.v.sv\n             obj_dir/traffic_light_controller.v\n             obj_dir/traffic_light_controller.v.v\n             obj_dir/traffic_light_controller.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/517680549/traffic_light_controller_test.v:18: Unsupported: Ignoring delay on this delayed statement.\nalways #3 clk=~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/517680549/traffic_light_controller_test.v:21: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("traffic_light_controller_test.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/517680549/traffic_light_controller_test.v:22: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,traffic_light_controller_test);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/517680549/traffic_light_controller_test.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #10 rst=1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/517680549/traffic_light_controller_test.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #200;\n    ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n'
module traffic_light_controller_test;

reg clk;
reg rst;


wire [1:0] NS_light;
wire [1:0] EW_light;

traffic_light_controller uut(
    .clk(clk),
    .rst(rst),
    .NS_light(NS_light),
    .EW_light(EW_light)
);

always #3 clk=~clk;
initial begin

    $dumpfile("traffic_light_controller_test.vcd");
    $dumpvars(0,traffic_light_controller_test);



    clk=0;rst=0;



    #10 rst=1;
    #200;

    $finish();
    


end

endmodule
module traffic_light_controller_test;


reg clk;
reg rst;


wire [1:0] NS_light;
wire [1:0] EW_light;

traffic_light_controller uut(
    .clk(clk),
    .rst(rst),
    .NS_light(NS_light),
    .EW_light(EW_light)
);

always #3 clk=~clk;
initial begin

    $dumpfile("traffic_light_controller_test.vcd");
    $dumpvars(0,traffic_light_controller_test);



    clk=0;rst=0;



    #10 rst=1;
    #200;

    $finish();
    


end

endmodule