data/full_repos/permissive/42581625/PersonalComputer/MemoryManagerUnit.v
1: b'%Error: data/full_repos/permissive/42581625/PersonalComputer/MemoryManagerUnit.v:65: Cannot find file containing module: \'Memory\'\nMemory Mem (\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/42581625/PersonalComputer,data/full_repos/permissive/42581625/Memory\n             data/full_repos/permissive/42581625/PersonalComputer,data/full_repos/permissive/42581625/Memory.v\n             data/full_repos/permissive/42581625/PersonalComputer,data/full_repos/permissive/42581625/Memory.sv\n             Memory\n             Memory.v\n             Memory.sv\n             obj_dir/Memory\n             obj_dir/Memory.v\n             obj_dir/Memory.sv\n%Error: data/full_repos/permissive/42581625/PersonalComputer/MemoryManagerUnit.v:80: Cannot find file containing module: \'vga_dis\'\nvga_dis vga (\n^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/42581625/PersonalComputer/MemoryManagerUnit.v:100: Operator COND expects 32 or 15 bits on the Conditional True, but Conditional True\'s CONST \'10\'h0\' generates 10 bits.\n                                                                                            : ... In instance MemoryManagerUnit\n                            (ypos[9:4]==height-1)? 10\'d0 : (lineBase + xpos[9:4] +1)\n                                                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/42581625/PersonalComputer/MemoryManagerUnit.v:100: Operator ADD expects 32 or 15 bits on the RHS, but RHS\'s SEL generates 6 bits.\n                                                                                            : ... In instance MemoryManagerUnit\n                            (ypos[9:4]==height-1)? 10\'d0 : (lineBase + xpos[9:4] +1)\n                                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/42581625/PersonalComputer/MemoryManagerUnit.v:102: Operator ADD expects 32 or 15 bits on the RHS, but RHS\'s SEL generates 6 bits.\n                                                                                            : ... In instance MemoryManagerUnit\n                    ) : (lineBase + xpos[9:4] + 1);\n                                  ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module MemoryManagerUnit(
input clk,
input clk_50M,
input[14:0] MemAddr,
input MemWrite,
input MemRead,
input SaveHalf,
input LoadHalf,
input[31:0] MemWriteData,
input ChipSelect,
output[31:0] MemReadData,
output reg MemOK,

output hsync,
output vsync,
output vga_r,
output vga_g,
output vga_b
    );

parameter width = 40;
parameter height = 25;
parameter screenBase = 14'h3000;
initial begin
    MemOK <= 0;
end
always @(posedge clk) begin
    MemOK <= (MemRead | MemWrite) & ChipSelect;
end
wire[14:0] ZBadr;
wire[15:0] outB;
Memory Mem (
    .clk(clk_50M), 
    .adrA(MemAddr), 
    .adrB(ZBadr), 
    .we(MemWrite&ChipSelect), 
    .data(MemWriteData), 
    .sh(SaveHalf), 
    .lh(LoadHalf),
    .outA(MemReadData), 
    .outB(outB)
    );

reg[15:0] ZBcode;
wire [9:0] xpos,ypos;
wire valid;
vga_dis vga (
    .clk(clk_50M),
    .rst_n(1'b1), 
    .ZBcode(ZBcode), 
     .valid(valid),
    .xpos(xpos[9:0]), 
    .ypos(ypos[9:0]), 
    .hsync(hsync), 
    .vsync(vsync), 
    .vga_r(vga_r), 
    .vga_g(vga_g), 
    .vga_b(vga_b)
    );
     
wire[14:0] offset;
assign ZBadr = screenBase+offset;
wire[14:0] lineBase;
assign lineBase = ypos[9:4]*width;
assign offset =(xpos[9:4]== width-1)?(
                        (ypos[3:0]==4'hf)?(
                            (ypos[9:4]==height-1)? 10'd0 : (lineBase + xpos[9:4] +1)
                        ) : lineBase
                    ) : (lineBase + xpos[9:4] + 1);

always @(posedge clk_50M) begin
    if(xpos[3:0] == 4'he && valid) begin
        ZBcode <= outB;
    end
end
endmodule
module MemoryManagerUnit(
input clk,
input clk_50M,
input[14:0] MemAddr,
input MemWrite,
input MemRead,
input SaveHalf,
input LoadHalf,
input[31:0] MemWriteData,
input ChipSelect,
output[31:0] MemReadData,
output reg MemOK,

output hsync,
output vsync,
output vga_r,
output vga_g,
output vga_b
    );


parameter width = 40;
parameter height = 25;
parameter screenBase = 14'h3000;
initial begin
    MemOK <= 0;
end
always @(posedge clk) begin
    MemOK <= (MemRead | MemWrite) & ChipSelect;
end
wire[14:0] ZBadr;
wire[15:0] outB;
Memory Mem (
    .clk(clk_50M), 
    .adrA(MemAddr), 
    .adrB(ZBadr), 
    .we(MemWrite&ChipSelect), 
    .data(MemWriteData), 
    .sh(SaveHalf), 
    .lh(LoadHalf),
    .outA(MemReadData), 
    .outB(outB)
    );

reg[15:0] ZBcode;
wire [9:0] xpos,ypos;
wire valid;
vga_dis vga (
    .clk(clk_50M),
    .rst_n(1'b1), 
    .ZBcode(ZBcode), 
     .valid(valid),
    .xpos(xpos[9:0]), 
    .ypos(ypos[9:0]), 
    .hsync(hsync), 
    .vsync(vsync), 
    .vga_r(vga_r), 
    .vga_g(vga_g), 
    .vga_b(vga_b)
    );
     
wire[14:0] offset;
assign ZBadr = screenBase+offset;
wire[14:0] lineBase;
assign lineBase = ypos[9:4]*width;
assign offset =(xpos[9:4]== width-1)?(
                        (ypos[3:0]==4'hf)?(
                            (ypos[9:4]==height-1)? 10'd0 : (lineBase + xpos[9:4] +1)
                        ) : lineBase
                    ) : (lineBase + xpos[9:4] + 1);

always @(posedge clk_50M) begin
    if(xpos[3:0] == 4'he && valid) begin
        ZBcode <= outB;
    end
end
endmodule