data/full_repos/permissive/456771003/testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/456771003/testbench.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #10 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/456771003/testbench.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/456771003/testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #5;\n        ^\n%Error: data/full_repos/permissive/456771003/testbench.v:35: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/456771003/testbench.v:37: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;

    wire write;
    wire read;
    wire [1:0] size;
    reg clk;
    reg rst;

    wire [19:0] addr;
    wire [31:0] data;
    wire oe_l;
    wire we_l;
    wire ce1_l, ce2_l;
    wire ub1_l, lb1_l, ub2_l, lb2_l;

    always begin
        #10 clk = ~clk;
    end

    initial begin
        clk <= 1'b0;
        rst <= 1'b0;
        #5;
        rst <= 1'b1;
        #5;
        rst <= 1'b0;
        
        repeat (90) begin
            @(posedge clk);
            $display("fetch        %h: %h", addr, data);
            @(posedge clk);
            if (!oe_l) begin
                $display("update read  %h: %h", addr, data);
            end
            if (!we_l) begin
                $display("update write %h: %h", addr, data);
            end
        end

        $finish;
    end

    always @(*) begin
        if ((rvc.state_q == `S_FETCH) && (rvc.decode_inst.inst == `INST_EBREAK)) begin
            $display("EBREAK %t", $time);
            $finish;
        end
    end

    assign addr[19:18] = 2'b0;



    sram mem(.addr(addr[17:0]), .data(data),  .oe_l(oe_l), .we_l(we_l));

    assign oe_l = ~read;
    assign we_l = ~write;
    assign ce1_l = 1'b0;
    assign ce2_l = 1'b0;
    assign ub1_l = 1'b0;
    assign lb1_l = 1'b0;
    assign ub2_l = 1'b0;
    assign lb2_l = 1'b0;

    rv_core rvc(
        .data(data),
        .addr(addr),
        .write(write),
        .read(read),
        .size(size),
        .clk(clk),
        .rst(rst)
    );

endmodule
module testbench;


    wire write;
    wire read;
    wire [1:0] size;
    reg clk;
    reg rst;

    wire [19:0] addr;
    wire [31:0] data;
    wire oe_l;
    wire we_l;
    wire ce1_l, ce2_l;
    wire ub1_l, lb1_l, ub2_l, lb2_l;

    always begin
        #10 clk = ~clk;
    end

    initial begin
        clk <= 1'b0;
        rst <= 1'b0;
        #5;
        rst <= 1'b1;
        #5;
        rst <= 1'b0;
        
        repeat (90) begin
            @(posedge clk);
            $display("fetch        %h: %h", addr, data);
            @(posedge clk);
            if (!oe_l) begin
                $display("update read  %h: %h", addr, data);
            end
            if (!we_l) begin
                $display("update write %h: %h", addr, data);
            end
        end

        $finish;
    end

    always @(*) begin
        if ((rvc.state_q == `S_FETCH) && (rvc.decode_inst.inst == `INST_EBREAK)) begin
            $display("EBREAK %t", $time);
            $finish;
        end
    end

    assign addr[19:18] = 2'b0;



    sram mem(.addr(addr[17:0]), .data(data),  .oe_l(oe_l), .we_l(we_l));

    assign oe_l = ~read;
    assign we_l = ~write;
    assign ce1_l = 1'b0;
    assign ce2_l = 1'b0;
    assign ub1_l = 1'b0;
    assign lb1_l = 1'b0;
    assign ub2_l = 1'b0;
    assign lb2_l = 1'b0;

    rv_core rvc(
        .data(data),
        .addr(addr),
        .write(write),
        .read(read),
        .size(size),
        .clk(clk),
        .rst(rst)
    );

endmodule