data/full_repos/permissive/493019833/test/testcase/firrtl/FixedPointReduce/reference/FixedPointReduce.v
data/verilator_xmls/5b3c1369-af84-4a0e-b757-3a2579675f09.xml
module ADD_SIGNED(y, a, b);
    parameter width = 4;
    output [width:0] y;
    input [width-1:0] a;
    input [width-1:0] b;
    assign y = $signed(a) + $signed(b);
endmodule
module ADD_SIGNED(y, a, b);

    parameter width = 4;
    output [width:0] y;
    input [width-1:0] a;
    input [width-1:0] b;
    assign y = $signed(a) + $signed(b);
endmodule