data/full_repos/permissive/515100461/pipeline/fetch.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/515100461/pipeline/fetch.v:18: Little bit endian vector: MSB < LSB of bit range: 0:7\n  reg [0:7] inst_mem[0:512];\n      ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/515100461/pipeline/fetch.v:19: Little bit endian vector: MSB < LSB of bit range: 0:79\n  reg [0:79] inst;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/515100461/pipeline/fetch.v:152: Bit extraction of array[512:0] requires 10 bit index, not 64 bits.\n                                                                         : ... In instance fetch\n    inst = {inst_mem[PC], inst_mem[PC+1], inst_mem[PC+2], inst_mem[PC+3], inst_mem[PC+4], \n                    ^\n%Warning-WIDTH: data/full_repos/permissive/515100461/pipeline/fetch.v:152: Bit extraction of array[512:0] requires 10 bit index, not 64 bits.\n                                                                         : ... In instance fetch\n    inst = {inst_mem[PC], inst_mem[PC+1], inst_mem[PC+2], inst_mem[PC+3], inst_mem[PC+4], \n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/515100461/pipeline/fetch.v:152: Bit extraction of array[512:0] requires 10 bit index, not 64 bits.\n                                                                         : ... In instance fetch\n    inst = {inst_mem[PC], inst_mem[PC+1], inst_mem[PC+2], inst_mem[PC+3], inst_mem[PC+4], \n                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/515100461/pipeline/fetch.v:152: Bit extraction of array[512:0] requires 10 bit index, not 64 bits.\n                                                                         : ... In instance fetch\n    inst = {inst_mem[PC], inst_mem[PC+1], inst_mem[PC+2], inst_mem[PC+3], inst_mem[PC+4], \n                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/515100461/pipeline/fetch.v:152: Bit extraction of array[512:0] requires 10 bit index, not 64 bits.\n                                                                         : ... In instance fetch\n    inst = {inst_mem[PC], inst_mem[PC+1], inst_mem[PC+2], inst_mem[PC+3], inst_mem[PC+4], \n                                                                                  ^\n%Warning-WIDTH: data/full_repos/permissive/515100461/pipeline/fetch.v:153: Bit extraction of array[512:0] requires 10 bit index, not 64 bits.\n                                                                         : ... In instance fetch\n            inst_mem[PC+5], inst_mem[PC+6], inst_mem[PC+7], inst_mem[PC+8], inst_mem[PC+9]};\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/515100461/pipeline/fetch.v:153: Bit extraction of array[512:0] requires 10 bit index, not 64 bits.\n                                                                         : ... In instance fetch\n            inst_mem[PC+5], inst_mem[PC+6], inst_mem[PC+7], inst_mem[PC+8], inst_mem[PC+9]};\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/515100461/pipeline/fetch.v:153: Bit extraction of array[512:0] requires 10 bit index, not 64 bits.\n                                                                         : ... In instance fetch\n            inst_mem[PC+5], inst_mem[PC+6], inst_mem[PC+7], inst_mem[PC+8], inst_mem[PC+9]};\n                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/515100461/pipeline/fetch.v:153: Bit extraction of array[512:0] requires 10 bit index, not 64 bits.\n                                                                         : ... In instance fetch\n            inst_mem[PC+5], inst_mem[PC+6], inst_mem[PC+7], inst_mem[PC+8], inst_mem[PC+9]};\n                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/515100461/pipeline/fetch.v:153: Bit extraction of array[512:0] requires 10 bit index, not 64 bits.\n                                                                         : ... In instance fetch\n            inst_mem[PC+5], inst_mem[PC+6], inst_mem[PC+7], inst_mem[PC+8], inst_mem[PC+9]};\n                                                                                    ^\n%Warning-WIDTH: data/full_repos/permissive/515100461/pipeline/fetch.v:337: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h1\' generates 2 bits.\n                                                                         : ... In instance fetch\n    f_stat = 2\'b01;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/515100461/pipeline/fetch.v:339: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                         : ... In instance fetch\n    f_stat = 2\'b10;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/515100461/pipeline/fetch.v:341: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h3\' generates 2 bits.\n                                                                         : ... In instance fetch\n    f_stat = 2\'b11;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/515100461/pipeline/fetch.v:342: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                         : ... In instance fetch\n    else f_stat = 2\'b00;\n                ^\n%Error: Exiting due to 16 warning(s)\n'
module fetch(clk,PC,m_icode,m_ifun,m_cnd,m_valA,w_icode,w_valM,
             f_stat,f_icode,f_ifun,f_rA,f_rB,f_valC,f_valP,f_dstM,
             pc_pred,D_stat,d_icode,d_ifun,d_rA,d_rB,d_valC,d_valP,d_dstM,d_srcA,d_srcB,d_bubble,
             e_icode,e_dstM);
  input clk,m_cnd;
  input [63:0] PC;
  input [3:0] e_icode,e_dstM,d_srcA,d_srcB;
  input [3:0] m_icode,w_icode,m_ifun;
  input [63:0] m_valA,w_valM;
  input d_bubble;
  output reg[2:0] f_stat,D_stat;
  output reg [3:0] f_icode, f_ifun;
  output reg [3:0] f_rA, f_rB,f_dstM;
  output reg [63:0] f_valC, f_valP;
  output reg [3:0] d_icode, d_ifun;
  output reg [3:0] d_rA, d_rB,d_dstM;
  output reg [63:0] d_valC, d_valP;
  reg [0:7] inst_mem[0:512];
  reg [0:79] inst;
  reg hlt,inst_invalid,mem_error;
  output reg [63:0] pc_pred;

initial begin

  






    inst_mem[1]=8'b00100000;
    inst_mem[2]=8'b00100100;
    inst_mem[3]=8'b01100000;
    inst_mem[4]=8'b00100100;
    inst_mem[5]=8'b00110000;
    inst_mem[6]=8'b00010011;
    inst_mem[7]=8'b00000000;
    inst_mem[8]=8'b00000000;
    inst_mem[9]=8'b00000000;
    inst_mem[10]=8'b00000000;
    inst_mem[11]=8'b00000000;
    inst_mem[12]=8'b00000000;
    inst_mem[13]=8'b00000000;
    inst_mem[14]=8'b00000101;
    inst_mem[15]=8'b00100000;
    inst_mem[16]=8'b00100100;
    inst_mem[17]=8'b01100000;
    inst_mem[18]=8'b00100100;











  





























































    inst_mem[39]=8'b00110000;
    inst_mem[40]=8'b00010011;
    inst_mem[41]=8'b00000000;
    inst_mem[42]=8'b00000000;
    inst_mem[43]=8'b00000000;
    inst_mem[44]=8'b00000000;
    inst_mem[45]=8'b00000000;
    inst_mem[46]=8'b00000000;
    inst_mem[47]=8'b00000000;
    inst_mem[48]=8'b00000101;
    inst_mem[49]=8'b01010000;
    inst_mem[50]=8'b00110000;
    inst_mem[51]=8'b00000000;
    inst_mem[52]=8'b00000000;
    inst_mem[53]=8'b00000000;
    inst_mem[54]=8'b00000000;
    inst_mem[55]=8'b00000000;
    inst_mem[56]=8'b00000000;
    inst_mem[57]=8'b00000000;
    inst_mem[58]=8'b00000000;
    inst_mem[59]=8'b01100000;
    inst_mem[60]=8'b00110001;



  end

always @(posedge clk)
begin
    inst = {inst_mem[PC], inst_mem[PC+1], inst_mem[PC+2], inst_mem[PC+3], inst_mem[PC+4], 
            inst_mem[PC+5], inst_mem[PC+6], inst_mem[PC+7], inst_mem[PC+8], inst_mem[PC+9]};

    f_icode = inst[0:3];
    f_ifun = inst[4:7];
    mem_error=0;
    if(PC>512)
    mem_error = 1;

    inst_invalid= 0;

    case(f_icode)

        4'b0000 :
        begin 
            f_valP = PC + 64'd1;
            hlt = 1;       
        end

        4'b0001 : f_valP = PC + 64'd1;

        4'b0010 :
        begin
            f_rA = inst[8:11];
            f_rB = inst[12:15];
            f_valP = PC + 64'd2;
        end

        4'b0011 :
        begin
            f_rA = inst[8:11];
            f_rB = inst[12:15];
            f_valC = inst[16:79];
            f_valP = PC + 64'd10;
        end
  
        4'b0100 :
        begin
            f_rA = inst[8:11];
            f_rB = inst[12:15];
            f_valC = inst[16:79];
            f_valP = PC + 64'd10;
        end

        4'b0101 :
        begin
            f_rA = inst[8:11];
            f_rB = inst[12:15];
            f_valC = inst[16:79];
            f_valP = PC + 64'd10;
        end

        4'b0110 :
        begin
            f_rA = inst[8:11];
            f_rB = inst[12:15];
            f_valP = PC + 64'd2;
        end

        4'b0111 :
        begin 
            f_valC = inst[8:71];
            f_valP = PC + 64'd9;
        end

        4'b1000 :
        begin
            f_valC = inst[8:71];
            f_valP = PC + 64'd9; 
        end

        4'b1001 :
        begin
            f_valP = PC + 64'd1;
        end

        4'b1010:
        begin
            f_rA = inst[8:11];
            f_rB = inst[12:15];
            f_valP = PC + 64'd2; 
            end

        4'b1011:
        begin
            f_rA = inst[8:11];
            f_rB = inst[12:15];
            f_valP = PC + 64'd2; 
        end

        default : inst_invalid=1;
  endcase
end 


always@(*)
    begin
        if(e_icode == 5 || e_icode ==12)
        begin

        if(e_dstM == d_srcA || e_dstM == d_srcB)
        begin

        pc_pred = PC;
        end 
        end
        if(e_icode == 9 || d_icode == 9 || m_icode ==9)
        begin
            pc_pred = PC;
        end
        else
        begin
        case(f_icode)

        4'b0000 :
        begin   
            pc_pred = f_valP;   
        end

        4'b0001 : pc_pred = f_valP;

        4'b0010 :
        begin
            pc_pred = f_valP;
        end

        4'b0011 :
        begin
            pc_pred = f_valP;
        end
  
        4'b0100 :
        begin
            pc_pred = f_valP;
        end

        4'b0101 :
        begin
            pc_pred = f_valP;
        end

        4'b0110 :
        begin
            pc_pred = f_valP;
        end

        4'b0111 :
        begin 
            pc_pred = f_valC;
        end

        4'b1000 :
        begin
            pc_pred = f_valC; 
        end






        4'b1010:
        begin
            pc_pred = f_valP;
            end

        4'b1011:
        begin
            pc_pred = f_valP; 
        end
  endcase
  if(m_icode == 7)
  begin
      if(m_ifun > 0 && m_cnd !=1)
      pc_pred = m_valA;
  end
  else if(w_icode == 9)
      pc_pred = w_valM;
         end
end


always@(*)
begin
    if(hlt == 1)
    f_stat = 2'b01;
    else if(mem_error==1)
    f_stat = 2'b10;
    else if(inst_invalid==1)
    f_stat = 2'b11;
    else f_stat = 2'b00;
end

always@(*)
begin
   if(f_icode == 5 || f_icode == 11)
   f_dstM = f_rA;
end

always@(negedge clk)
    begin
        if(d_bubble == 1)
        begin
            d_icode <= 1;
        end
        else
        begin
            d_icode <= f_icode;
        end
        d_ifun  <= f_ifun;
        d_rA    <= f_rA;
        d_rB    <= f_rB;
        d_valC  <= f_valC;
        d_valP  <= f_valP;
        D_stat  <= f_stat;
    end
endmodule
module fetch(clk,PC,m_icode,m_ifun,m_cnd,m_valA,w_icode,w_valM,
             f_stat,f_icode,f_ifun,f_rA,f_rB,f_valC,f_valP,f_dstM,
             pc_pred,D_stat,d_icode,d_ifun,d_rA,d_rB,d_valC,d_valP,d_dstM,d_srcA,d_srcB,d_bubble,
             e_icode,e_dstM);

  input clk,m_cnd;
  input [63:0] PC;
  input [3:0] e_icode,e_dstM,d_srcA,d_srcB;
  input [3:0] m_icode,w_icode,m_ifun;
  input [63:0] m_valA,w_valM;
  input d_bubble;
  output reg[2:0] f_stat,D_stat;
  output reg [3:0] f_icode, f_ifun;
  output reg [3:0] f_rA, f_rB,f_dstM;
  output reg [63:0] f_valC, f_valP;
  output reg [3:0] d_icode, d_ifun;
  output reg [3:0] d_rA, d_rB,d_dstM;
  output reg [63:0] d_valC, d_valP;
  reg [0:7] inst_mem[0:512];
  reg [0:79] inst;
  reg hlt,inst_invalid,mem_error;
  output reg [63:0] pc_pred;

initial begin

  






    inst_mem[1]=8'b00100000;
    inst_mem[2]=8'b00100100;
    inst_mem[3]=8'b01100000;
    inst_mem[4]=8'b00100100;
    inst_mem[5]=8'b00110000;
    inst_mem[6]=8'b00010011;
    inst_mem[7]=8'b00000000;
    inst_mem[8]=8'b00000000;
    inst_mem[9]=8'b00000000;
    inst_mem[10]=8'b00000000;
    inst_mem[11]=8'b00000000;
    inst_mem[12]=8'b00000000;
    inst_mem[13]=8'b00000000;
    inst_mem[14]=8'b00000101;
    inst_mem[15]=8'b00100000;
    inst_mem[16]=8'b00100100;
    inst_mem[17]=8'b01100000;
    inst_mem[18]=8'b00100100;











  





























































    inst_mem[39]=8'b00110000;
    inst_mem[40]=8'b00010011;
    inst_mem[41]=8'b00000000;
    inst_mem[42]=8'b00000000;
    inst_mem[43]=8'b00000000;
    inst_mem[44]=8'b00000000;
    inst_mem[45]=8'b00000000;
    inst_mem[46]=8'b00000000;
    inst_mem[47]=8'b00000000;
    inst_mem[48]=8'b00000101;
    inst_mem[49]=8'b01010000;
    inst_mem[50]=8'b00110000;
    inst_mem[51]=8'b00000000;
    inst_mem[52]=8'b00000000;
    inst_mem[53]=8'b00000000;
    inst_mem[54]=8'b00000000;
    inst_mem[55]=8'b00000000;
    inst_mem[56]=8'b00000000;
    inst_mem[57]=8'b00000000;
    inst_mem[58]=8'b00000000;
    inst_mem[59]=8'b01100000;
    inst_mem[60]=8'b00110001;



  end

always @(posedge clk)
begin
    inst = {inst_mem[PC], inst_mem[PC+1], inst_mem[PC+2], inst_mem[PC+3], inst_mem[PC+4], 
            inst_mem[PC+5], inst_mem[PC+6], inst_mem[PC+7], inst_mem[PC+8], inst_mem[PC+9]};

    f_icode = inst[0:3];
    f_ifun = inst[4:7];
    mem_error=0;
    if(PC>512)
    mem_error = 1;

    inst_invalid= 0;

    case(f_icode)

        4'b0000 :
        begin 
            f_valP = PC + 64'd1;
            hlt = 1;       
        end

        4'b0001 : f_valP = PC + 64'd1;

        4'b0010 :
        begin
            f_rA = inst[8:11];
            f_rB = inst[12:15];
            f_valP = PC + 64'd2;
        end

        4'b0011 :
        begin
            f_rA = inst[8:11];
            f_rB = inst[12:15];
            f_valC = inst[16:79];
            f_valP = PC + 64'd10;
        end
  
        4'b0100 :
        begin
            f_rA = inst[8:11];
            f_rB = inst[12:15];
            f_valC = inst[16:79];
            f_valP = PC + 64'd10;
        end

        4'b0101 :
        begin
            f_rA = inst[8:11];
            f_rB = inst[12:15];
            f_valC = inst[16:79];
            f_valP = PC + 64'd10;
        end

        4'b0110 :
        begin
            f_rA = inst[8:11];
            f_rB = inst[12:15];
            f_valP = PC + 64'd2;
        end

        4'b0111 :
        begin 
            f_valC = inst[8:71];
            f_valP = PC + 64'd9;
        end

        4'b1000 :
        begin
            f_valC = inst[8:71];
            f_valP = PC + 64'd9; 
        end

        4'b1001 :
        begin
            f_valP = PC + 64'd1;
        end

        4'b1010:
        begin
            f_rA = inst[8:11];
            f_rB = inst[12:15];
            f_valP = PC + 64'd2; 
            end

        4'b1011:
        begin
            f_rA = inst[8:11];
            f_rB = inst[12:15];
            f_valP = PC + 64'd2; 
        end

        default : inst_invalid=1;
  endcase
end 


always@(*)
    begin
        if(e_icode == 5 || e_icode ==12)
        begin

        if(e_dstM == d_srcA || e_dstM == d_srcB)
        begin

        pc_pred = PC;
        end 
        end
        if(e_icode == 9 || d_icode == 9 || m_icode ==9)
        begin
            pc_pred = PC;
        end
        else
        begin
        case(f_icode)

        4'b0000 :
        begin   
            pc_pred = f_valP;   
        end

        4'b0001 : pc_pred = f_valP;

        4'b0010 :
        begin
            pc_pred = f_valP;
        end

        4'b0011 :
        begin
            pc_pred = f_valP;
        end
  
        4'b0100 :
        begin
            pc_pred = f_valP;
        end

        4'b0101 :
        begin
            pc_pred = f_valP;
        end

        4'b0110 :
        begin
            pc_pred = f_valP;
        end

        4'b0111 :
        begin 
            pc_pred = f_valC;
        end

        4'b1000 :
        begin
            pc_pred = f_valC; 
        end






        4'b1010:
        begin
            pc_pred = f_valP;
            end

        4'b1011:
        begin
            pc_pred = f_valP; 
        end
  endcase
  if(m_icode == 7)
  begin
      if(m_ifun > 0 && m_cnd !=1)
      pc_pred = m_valA;
  end
  else if(w_icode == 9)
      pc_pred = w_valM;
         end
end


always@(*)
begin
    if(hlt == 1)
    f_stat = 2'b01;
    else if(mem_error==1)
    f_stat = 2'b10;
    else if(inst_invalid==1)
    f_stat = 2'b11;
    else f_stat = 2'b00;
end

always@(*)
begin
   if(f_icode == 5 || f_icode == 11)
   f_dstM = f_rA;
end

always@(negedge clk)
    begin
        if(d_bubble == 1)
        begin
            d_icode <= 1;
        end
        else
        begin
            d_icode <= f_icode;
        end
        d_ifun  <= f_ifun;
        d_rA    <= f_rA;
        d_rB    <= f_rB;
        d_valC  <= f_valC;
        d_valP  <= f_valP;
        D_stat  <= f_stat;
    end
endmodule