data/full_repos/permissive/527176783/Pipeline/decoder.v
1: b'%Error: data/full_repos/permissive/527176783/Pipeline/decoder.v:2: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/527176783/Pipeline,data/full_repos/permissive/527176783/define.v\n             data/full_repos/permissive/527176783/Pipeline,data/full_repos/permissive/527176783/define.v.v\n             data/full_repos/permissive/527176783/Pipeline,data/full_repos/permissive/527176783/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: Exiting due to 1 error(s)\n'
module decoder(
    input [31:0] ins,
    output [5:0] op,
    output [5:0] func,
    output [4:0] sa,
    output [4:0] rs,
    output [4:0] rt,
    output [4:0] rd,
    output [15:0] immd16,
    output [25:0] immd26
    );
    assign op = ins[31:26];
    assign func = ins[5:0];
    assign sa = ins[10:6];
    assign rs = ins[25:21];
    assign rt = ins[20:16];
    assign rd = ins[15:11];
    assign immd16 = ins[15:0];
    assign immd26 = ins[25:0];
endmodule
module decoder(
    input [31:0] ins,
    output [5:0] op,
    output [5:0] func,
    output [4:0] sa,
    output [4:0] rs,
    output [4:0] rt,
    output [4:0] rd,
    output [15:0] immd16,
    output [25:0] immd26
    );

    assign op = ins[31:26];
    assign func = ins[5:0];
    assign sa = ins[10:6];
    assign rs = ins[25:21];
    assign rt = ins[20:16];
    assign rd = ins[15:11];
    assign immd16 = ins[15:0];
    assign immd26 = ins[25:0];
endmodule