data/full_repos/permissive/439514885/verilog/bits_core.v
1: b"%Error: data/full_repos/permissive/439514885/verilog/bits_core.v:72: Cannot find file containing module: 'bits_fsm'\nbits_fsm bits_fsm(\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/439514885/verilog,data/full_repos/permissive/439514885/bits_fsm\n             data/full_repos/permissive/439514885/verilog,data/full_repos/permissive/439514885/bits_fsm.v\n             data/full_repos/permissive/439514885/verilog,data/full_repos/permissive/439514885/bits_fsm.sv\n             bits_fsm\n             bits_fsm.v\n             bits_fsm.sv\n             obj_dir/bits_fsm\n             obj_dir/bits_fsm.v\n             obj_dir/bits_fsm.sv\n%Error: data/full_repos/permissive/439514885/verilog/bits_core.v:113: Cannot find file containing module: 'bits_instruction_cache'\nbits_instruction_cache bits_instruction_cache(\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/439514885/verilog/bits_core.v:133: Cannot find file containing module: 'number_top'\nnumber_top number_decoder(\n^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module bits_core(


    smem_ceb,
    smem_web,
    smem_addr,
    smem_wdata,
    mem_req_b,


    done,
    version_sum,
    bits_value,
    bit_counter,



    clk,
    resetB,


    smem_rdata,


    instruction_word,
    instruction_byte_valid,
    done_reading_memory,
    mem_ack_b,


    start,
    expectedBytes
);

output       smem_ceb;
output       smem_web;
output[13:0] smem_addr;
output[95:0] smem_wdata;

output       mem_req_b;
output       done;
output[15:0] version_sum;
output[63:0] bits_value;
output[15:0] bit_counter;


input        clk;
input        resetB;

input[95:0]  smem_rdata;

input[127:0] instruction_word;
input[15:0]  instruction_byte_valid;
input        done_reading_memory;
input        mem_ack_b;

input        start;
input[15:0]  expectedBytes;

wire[63:0]   number;
wire[6:0]    bitsToShift;
wire[79:0]   encoded_number;
wire         decode_number;
wire[15:0]   validNibbles;
wire [4:0]   instruction_process;

wire mem_req_b;
wire mem_ack_b;
wire[255:0] instruction_cache_word;
wire space_available;

bits_fsm bits_fsm(


   .smem_ceb (smem_ceb),
   .smem_web (smem_web),
   .smem_addr (smem_addr),
   .smem_wdata (smem_wdata),

   .mem_req_b (mem_req_b),


   .done    (done),
   .bits_value (bits_value),
   .version_sum (version_sum),


   .encoded_number (encoded_number),
   .decodeNumber (decode_number),
   .instruction_process (instruction_process),



   .clk (clk),
   .resetB (resetB),


   .instruction_word(instruction_word),
   .instruction_byte_valid(instruction_byte_valid),
   .done_reading_memory(done_reading_memory),
   .start(start),
   .instruction_cache_word(instruction_cache_word),
   .space_available(space_available),
   .mem_ack_b (mem_ack_b),

    .smem_rdata (smem_rdata),


   .decodedNumber(number),
   .validNibbles(validNibbles)
);

bits_instruction_cache bits_instruction_cache(

   .instruction_cache (instruction_cache_word),
   .space_available (space_available),
   .bit_counter (bit_counter),


   .clk (clk),
   .resetB(resetB),


   .mem_req_b (mem_req_b),
   .mem_ack_b (mem_ack_b),
   .instruction_word (instruction_word),
   .valid_bytes (instruction_byte_valid),


   .instruction_process (instruction_process)
);

number_top number_decoder(

     .number          (number),
     .validNibbles    (validNibbles),


     .clk             (clk),
     .resetB          (resetB),
     .enable          (decode_number),
     .numberFromBits  (encoded_number)
);


endmodule
module bits_core(


    smem_ceb,
    smem_web,
    smem_addr,
    smem_wdata,
    mem_req_b,


    done,
    version_sum,
    bits_value,
    bit_counter,



    clk,
    resetB,


    smem_rdata,


    instruction_word,
    instruction_byte_valid,
    done_reading_memory,
    mem_ack_b,


    start,
    expectedBytes
);


output       smem_ceb;
output       smem_web;
output[13:0] smem_addr;
output[95:0] smem_wdata;

output       mem_req_b;
output       done;
output[15:0] version_sum;
output[63:0] bits_value;
output[15:0] bit_counter;


input        clk;
input        resetB;

input[95:0]  smem_rdata;

input[127:0] instruction_word;
input[15:0]  instruction_byte_valid;
input        done_reading_memory;
input        mem_ack_b;

input        start;
input[15:0]  expectedBytes;

wire[63:0]   number;
wire[6:0]    bitsToShift;
wire[79:0]   encoded_number;
wire         decode_number;
wire[15:0]   validNibbles;
wire [4:0]   instruction_process;

wire mem_req_b;
wire mem_ack_b;
wire[255:0] instruction_cache_word;
wire space_available;

bits_fsm bits_fsm(


   .smem_ceb (smem_ceb),
   .smem_web (smem_web),
   .smem_addr (smem_addr),
   .smem_wdata (smem_wdata),

   .mem_req_b (mem_req_b),


   .done    (done),
   .bits_value (bits_value),
   .version_sum (version_sum),


   .encoded_number (encoded_number),
   .decodeNumber (decode_number),
   .instruction_process (instruction_process),



   .clk (clk),
   .resetB (resetB),


   .instruction_word(instruction_word),
   .instruction_byte_valid(instruction_byte_valid),
   .done_reading_memory(done_reading_memory),
   .start(start),
   .instruction_cache_word(instruction_cache_word),
   .space_available(space_available),
   .mem_ack_b (mem_ack_b),

    .smem_rdata (smem_rdata),


   .decodedNumber(number),
   .validNibbles(validNibbles)
);

bits_instruction_cache bits_instruction_cache(

   .instruction_cache (instruction_cache_word),
   .space_available (space_available),
   .bit_counter (bit_counter),


   .clk (clk),
   .resetB(resetB),


   .mem_req_b (mem_req_b),
   .mem_ack_b (mem_ack_b),
   .instruction_word (instruction_word),
   .valid_bytes (instruction_byte_valid),


   .instruction_process (instruction_process)
);

number_top number_decoder(

     .number          (number),
     .validNibbles    (validNibbles),


     .clk             (clk),
     .resetB          (resetB),
     .enable          (decode_number),
     .numberFromBits  (encoded_number)
);


endmodule