data/full_repos/permissive/516533387/morsedecoder.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/516533387/morsedecoder.v:391: Multiple top level modules\n                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                          : ... Top module \'morse_decoder\'\nmodule morse_decoder(\n       ^~~~~~~~~~~~~\n                                                                          : ... Top module \'unit_conter\'\nmodule unit_conter(clk, unit_freq , out_clk);\n       ^~~~~~~~~~~\n                                                                          : ... Top module \'lcdlab3\'\nmodule lcdlab3(\n       ^~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/516533387/morsedecoder.v:37: Signal definition not found, creating implicitly: \'GIPO_0\'\n                                                                         : ... Suggested alternative: \'GPIO_0\'\nassign GIPO_0 = 36\'hzzzzzzzzz;\n       ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/516533387/morsedecoder.v:38: Signal definition not found, creating implicitly: \'GIPO_1\'\n                                                                         : ... Suggested alternative: \'GIPO_0\'\nassign GIPO_1 = 36\'hzzzzzzzzz;\n       ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/516533387/morsedecoder.v:41: Signal definition not found, creating implicitly: \'RST\'\nassign RST = KEY[0];\n       ^~~\n%Warning-IMPLICIT: data/full_repos/permissive/516533387/morsedecoder.v:54: Signal definition not found, creating implicitly: \'newsletter\'\n                                                                         : ... Suggested alternative: \'new_letter\'\nfsm F (clk2, beep, letter , LEDR[17:12] , newsletter);\n                                          ^~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/516533387/morsedecoder.v:71: Signal definition not found, creating implicitly: \'now_letter\'\n                                                                         : ... Suggested alternative: \'new_letter\'\nmux8bit9tol MUX1 (letter , now_letter);\n                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/516533387/morsedecoder.v:105: Pin not found: \'hex2\'\n                                                               : ... Suggested alternative: \'hex1\'\n    .hex2(rhex2),\n     ^~~~\n%Error: data/full_repos/permissive/516533387/morsedecoder.v:106: Pin not found: \'hex3\'\n                                                               : ... Suggested alternative: \'hex1\'\n    .hex3(rhex3),\n     ^~~~\n%Error: data/full_repos/permissive/516533387/morsedecoder.v:107: Pin not found: \'hex4\'\n                                                               : ... Suggested alternative: \'hex1\'\n    .hex4(rhex4),\n     ^~~~\n%Error: data/full_repos/permissive/516533387/morsedecoder.v:108: Pin not found: \'hex5\'\n                                                               : ... Suggested alternative: \'hex1\'\n    .hex5(rhex5),\n     ^~~~\n%Error: data/full_repos/permissive/516533387/morsedecoder.v:109: Pin not found: \'hex6\'\n                                                               : ... Suggested alternative: \'hex1\'\n    .hex6(rhex6),\n     ^~~~\n%Error: data/full_repos/permissive/516533387/morsedecoder.v:110: Pin not found: \'hex7\'\n                                                               : ... Suggested alternative: \'hex1\'\n    .hex7(rhex7),\n     ^~~~\n%Error: data/full_repos/permissive/516533387/morsedecoder.v:111: Pin not found: \'hex8\'\n                                                               : ... Suggested alternative: \'hex1\'\n    .hex8(rhex8),\n     ^~~~\n%Error: Exiting due to 7 error(s), 6 warning(s)\n'
module    Reset_Delay(iCLK,oRESET);
input        iCLK;
output reg    oRESET;
reg    [19:0]    Cont;

always@(posedge iCLK)
begin
    if(Cont!=20'hFFFFF)
    begin
        Cont    <=    Cont+1'b1;
        oRESET    <=    1'b0;
    end
    else
    oRESET    <=    1'b1;
end

endmodule
module    Reset_Delay(iCLK,oRESET);

input        iCLK;
output reg    oRESET;
reg    [19:0]    Cont;

always@(posedge iCLK)
begin
    if(Cont!=20'hFFFFF)
    begin
        Cont    <=    Cont+1'b1;
        oRESET    <=    1'b0;
    end
    else
    oRESET    <=    1'b1;
end

endmodule