data/full_repos/permissive/445216371/coprocessor0.v
1: b'%Error: data/full_repos/permissive/445216371/coprocessor0.v:11: Cannot find include file: parameters.vh\n    `include "parameters.vh" \n             ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/445216371,data/full_repos/permissive/445216371/parameters.vh\n             data/full_repos/permissive/445216371,data/full_repos/permissive/445216371/parameters.vh.v\n             data/full_repos/permissive/445216371,data/full_repos/permissive/445216371/parameters.vh.sv\n             parameters.vh\n             parameters.vh.v\n             parameters.vh.sv\n             obj_dir/parameters.vh\n             obj_dir/parameters.vh.v\n             obj_dir/parameters.vh.sv\n%Error: Exiting due to 1 error(s)\n'
module Divide(  
    input clk,  
    input rst,  
    input start,  
    input [31:0] A,  
    input [31:0] B,  
    output [31:0] D,  
    output [31:0] R,  
    output ok ,
    output err 
);  
    reg active;
    reg [4:0] cycle;
    reg [31:0] result;
    reg [31:0] denom;
    reg [31:0] work;

    wire [32:0] sub = { work[30:0], result[31] } - denom;  
    assign err = !B;  

    assign D = result;  
    assign R = work;  
    assign ok = ~active;


    always @(posedge clk,negedge rst) begin  
        if (!rst) begin  
            active <= 0;  
            cycle <= 0;  
            result <= 0;  
            denom <= 0;  
            work <= 0;  
        end  

        else begin
            if (active) begin  

                if (sub[32] == 0) begin  
                    work <= sub[31:0];  
                    result <= {result[30:0], 1'b1};  
                end  
                else begin  
                    work <= {work[30:0], result[31]};  
                    result <= {result[30:0], 1'b0};  
                end  
                if (cycle == 0) begin  
                    active <= 0;  
                end  
                cycle <= cycle - 5'd1;  

            end  
            else begin  

                if(start) begin
                    active <= 1; 
                end
                else begin
                    active <= 0;
                end
                cycle <= 5'd31;  
                result <= A;  
                denom <= B;  
                work <= 32'b0;  

            end  
        end
    end  

endmodule
module Divide(  
    input clk,  
    input rst,  
    input start,  
    input [31:0] A,  
    input [31:0] B,  
    output [31:0] D,  
    output [31:0] R,  
    output ok ,
    output err 
);
  
    reg active;
    reg [4:0] cycle;
    reg [31:0] result;
    reg [31:0] denom;
    reg [31:0] work;

    wire [32:0] sub = { work[30:0], result[31] } - denom;  
    assign err = !B;  

    assign D = result;  
    assign R = work;  
    assign ok = ~active;


    always @(posedge clk,negedge rst) begin  
        if (!rst) begin  
            active <= 0;  
            cycle <= 0;  
            result <= 0;  
            denom <= 0;  
            work <= 0;  
        end  

        else begin
            if (active) begin  

                if (sub[32] == 0) begin  
                    work <= sub[31:0];  
                    result <= {result[30:0], 1'b1};  
                end  
                else begin  
                    work <= {work[30:0], result[31]};  
                    result <= {result[30:0], 1'b0};  
                end  
                if (cycle == 0) begin  
                    active <= 0;  
                end  
                cycle <= cycle - 5'd1;  

            end  
            else begin  

                if(start) begin
                    active <= 1; 
                end
                else begin
                    active <= 0;
                end
                cycle <= 5'd31;  
                result <= A;  
                denom <= B;  
                work <= 32'b0;  

            end  
        end
    end  

endmodule