data/full_repos/permissive/52666593/vga/tb_v_syncer.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/52666593/vga/tb_v_syncer.v:11: Unsupported: Ignoring delay on this delayed statement.\n#5\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/52666593/vga/tb_v_syncer.v:14: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk <= ~clk;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/52666593/vga/tb_v_syncer.v:15: Unsupported: Ignoring delay on this delayed statement.\nalways #5 $display("h-sync:%b,v-sync:%b",h_sync,v_sync);\n       ^\n%Error: data/full_repos/permissive/52666593/vga/tb_v_syncer.v:6: Cannot find file containing module: \'h_syncer\'\nh_syncer hs(clk,reset,h_sync,line_complete);\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52666593/vga,data/full_repos/permissive/52666593/h_syncer\n             data/full_repos/permissive/52666593/vga,data/full_repos/permissive/52666593/h_syncer.v\n             data/full_repos/permissive/52666593/vga,data/full_repos/permissive/52666593/h_syncer.sv\n             h_syncer\n             h_syncer.v\n             h_syncer.sv\n             obj_dir/h_syncer\n             obj_dir/h_syncer.v\n             obj_dir/h_syncer.sv\n%Error: data/full_repos/permissive/52666593/vga/tb_v_syncer.v:7: Cannot find file containing module: \'v_syncer\'\nv_syncer vs(clk,reset,v_sync,line_complete);\n^~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_v_syncer;
reg clk;
reg reset;
wire h_sync,v_sync,line_complete;

h_syncer hs(clk,reset,h_sync,line_complete);
v_syncer vs(clk,reset,v_sync,line_complete);
initial begin
clk<=1'b0;
reset<=1'b1;
#5
reset<=1'b0;
end
always #5 clk <= ~clk;
always #5 $display("h-sync:%b,v-sync:%b",h_sync,v_sync);
endmodule
module tb_v_syncer;

reg clk;
reg reset;
wire h_sync,v_sync,line_complete;

h_syncer hs(clk,reset,h_sync,line_complete);
v_syncer vs(clk,reset,v_sync,line_complete);
initial begin
clk<=1'b0;
reset<=1'b1;
#5
reset<=1'b0;
end
always #5 clk <= ~clk;
always #5 $display("h-sync:%b,v-sync:%b",h_sync,v_sync);
endmodule