data/full_repos/permissive/472385934/datapath.v
1: b"%Error: data/full_repos/permissive/472385934/datapath.v:58: Cannot find file containing module: 'inst_memory'\ninst_memory fetch_mem(clk,pcF,instrF,ext_instr,ext_instr_addr,ext_instr_en,start); \n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/472385934,data/full_repos/permissive/472385934/inst_memory\n             data/full_repos/permissive/472385934,data/full_repos/permissive/472385934/inst_memory.v\n             data/full_repos/permissive/472385934,data/full_repos/permissive/472385934/inst_memory.sv\n             inst_memory\n             inst_memory.v\n             inst_memory.sv\n             obj_dir/inst_memory\n             obj_dir/inst_memory.v\n             obj_dir/inst_memory.sv\n%Error: data/full_repos/permissive/472385934/datapath.v:86: Cannot find file containing module: 'reg_file'\nreg_file reg_file(resultW,writeregW,clk,regwriteW,rst_n,a1,a2,rd1,rd2);\n^~~~~~~~\n%Error: data/full_repos/permissive/472385934/datapath.v:116: Cannot find file containing module: 'alu'\nalu alu(srcaE,srcbE,alucontrolE,aluoutE); \n^~~\n%Error: data/full_repos/permissive/472385934/datapath.v:117: Cannot find file containing module: 'multipler'\nmultipler multipler(srcaE,srcbE,clk,alucontrolE[3],multoutE); \n^~~~~~~~~\n%Error: data/full_repos/permissive/472385934/datapath.v:135: Cannot find file containing module: 'data_memory'\ndata_memory data_memory(realoutM,writedataM,clk,memwriteM,readdataM,ext_data,ext_data_addr,ext_data_en);\n^~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module Execute(
input clk,rst_n,
input flushE,
input [31:0] signimmD,rd1D,rd2D,
input [4:0] rtD,rdD,rsD,
input regwriteD,memtoregD,memwriteD,alusrcD,regdstD,mult_selD,
input [3:0]alucontrolD,
output reg [31:0] signimmE,rd1E,rd2E,
output reg [4:0] rtE,rdE,rsE,
output reg [3:0] alucontrolE,
output reg regwriteE,memtoregE,memwriteE,alusrcE,regdstE,mult_selE);

always@(posedge clk,negedge rst_n,posedge flushE)
begin
    if((!rst_n) || flushE) begin
        signimmE <= 0;
        rd1E <= 0;
        rd2E <= 0;
        {regwriteE,memtoregE,memwriteE,alucontrolE,alusrcE,regdstE,mult_selE} <= 0;
        rtE <= 0;
        rdE <= 0;
        rsE <= 0;
    end
    else begin
        signimmE <= signimmD;
        rd1E <= rd1D;
        rd2E <= rd2D;
        {regwriteE,memtoregE,memwriteE,alucontrolE,regdstE,mult_selE} <= 
        {regwriteD,memtoregD,memwriteD,alucontrolD,regdstD,mult_selD};
        alusrcE <= alusrcD;
        rtE <= rtD;
        rdE <= rdD;
        rsE <= rsD;
    end
end
endmodule
module Execute(
input clk,rst_n,
input flushE,
input [31:0] signimmD,rd1D,rd2D,
input [4:0] rtD,rdD,rsD,
input regwriteD,memtoregD,memwriteD,alusrcD,regdstD,mult_selD,
input [3:0]alucontrolD,
output reg [31:0] signimmE,rd1E,rd2E,
output reg [4:0] rtE,rdE,rsE,
output reg [3:0] alucontrolE,
output reg regwriteE,memtoregE,memwriteE,alusrcE,regdstE,mult_selE);


always@(posedge clk,negedge rst_n,posedge flushE)
begin
    if((!rst_n) || flushE) begin
        signimmE <= 0;
        rd1E <= 0;
        rd2E <= 0;
        {regwriteE,memtoregE,memwriteE,alucontrolE,alusrcE,regdstE,mult_selE} <= 0;
        rtE <= 0;
        rdE <= 0;
        rsE <= 0;
    end
    else begin
        signimmE <= signimmD;
        rd1E <= rd1D;
        rd2E <= rd2D;
        {regwriteE,memtoregE,memwriteE,alucontrolE,regdstE,mult_selE} <= 
        {regwriteD,memtoregD,memwriteD,alucontrolD,regdstD,mult_selD};
        alusrcE <= alusrcD;
        rtE <= rtD;
        rdE <= rdD;
        rsE <= rsD;
    end
end
endmodule