data/full_repos/permissive/405799749/arithmetic_netlists/muliplier/16-bit signed multiplier using wallace tree/multi_16bit.v
1: b'%Error: Cannot find file containing module: signed\n        ... Looked in:\n             data/full_repos/permissive/405799749/arithmetic_netlists/muliplier/16-bit/signed\n             data/full_repos/permissive/405799749/arithmetic_netlists/muliplier/16-bit/signed.v\n             data/full_repos/permissive/405799749/arithmetic_netlists/muliplier/16-bit/signed.sv\n             signed\n             signed.v\n             signed.sv\n             obj_dir/signed\n             obj_dir/signed.v\n             obj_dir/signed.sv\n%Error: Cannot find file containing module: multiplier\n%Error: Cannot find file containing module: using\n%Error: Cannot find file containing module: wallace\n%Error: Cannot find file containing module: tree,data/full_repos/permissive/405799749\n%Error: Cannot find file containing module: data/full_repos/permissive/405799749/arithmetic_netlists/muliplier/16-bit\n%Error: Cannot find file containing module: tree/multi_16bit.v\n%Error: Exiting due to 7 error(s)\n'
module tb_multi_16bit();
	reg [15:0] a,b;
	reg clk,rst,load;
	wire [31:0] prod;
	multi_16bit uut(.prod(prod),.a(a),.b(b),.clk(clk),.rst(rst),.load(load));
	
	initial
	begin
	#00 clk = 1'b0;
	forever #50 clk = ~clk;
	end
	
	initial
	begin
	#00 rst = 1'b1;
	#60 rst = 1'b0;
	end
	
	initial
	begin
	#110 load = 1'b1; a = 16'd640; b = 16'd288;
	# 60 load = 1'b0; 
	
	#570 load = 1'b1; a = 16'b1111111110000000; b = 16'b0000000111000000;
	# 20 load = 1'b0;
	#580 load = 1'b1; a = 16'b0111111111111111; b = 16'b1000000000000000;
	# 20 load = 1'b0;
	#580 load = 1'b1; a = 16'b0000111011110101; b = 16'b0000101101111001;
	# 20 load = 1'b0;
	#580 load = 1'b1; a = 16'b1010101010101010; b = 16'b1101010101010101;
	# 20 load = 1'b0;
	#580 load = 1'b1; a = 16'd55; b = 16'd46;
	# 20 load = 1'b0;
	#580 load = 1'b1; a = 16'd7; b = 16'd211;
	# 20 load = 1'b0;
	#580 $stop;
	

	end
	
	initial
	begin
	$dumpfile("multi_16bit.vcd");
	$dumpvars;
	end
	
endmodule
module tb_multi_16bit();

	reg [15:0] a,b;
	reg clk,rst,load;
	wire [31:0] prod;
	multi_16bit uut(.prod(prod),.a(a),.b(b),.clk(clk),.rst(rst),.load(load));
	
	initial
	begin
	#00 clk = 1'b0;
	forever #50 clk = ~clk;
	end
	
	initial
	begin
	#00 rst = 1'b1;
	#60 rst = 1'b0;
	end
	
	initial
	begin
	#110 load = 1'b1; a = 16'd640; b = 16'd288;
	# 60 load = 1'b0; 
	
	#570 load = 1'b1; a = 16'b1111111110000000; b = 16'b0000000111000000;
	# 20 load = 1'b0;
	#580 load = 1'b1; a = 16'b0111111111111111; b = 16'b1000000000000000;
	# 20 load = 1'b0;
	#580 load = 1'b1; a = 16'b0000111011110101; b = 16'b0000101101111001;
	# 20 load = 1'b0;
	#580 load = 1'b1; a = 16'b1010101010101010; b = 16'b1101010101010101;
	# 20 load = 1'b0;
	#580 load = 1'b1; a = 16'd55; b = 16'd46;
	# 20 load = 1'b0;
	#580 load = 1'b1; a = 16'd7; b = 16'd211;
	# 20 load = 1'b0;
	#580 $stop;
	

	end
	
	initial
	begin
	$dumpfile("multi_16bit.vcd");
	$dumpvars;
	end
	
endmodule