data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/flit_counter_wrap.v
1: b'%Error: data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/flit_counter_wrap.v:9: Cannot find include file: noc_parameter.vh\n    `include "noc_parameter.vh" \n             ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh\n             data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.v\n             data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.sv\n             noc_parameter.vh\n             noc_parameter.vh.v\n             noc_parameter.vh.sv\n             obj_dir/noc_parameter.vh\n             obj_dir/noc_parameter.vh.v\n             obj_dir/noc_parameter.vh.sv\n%Error: data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/flit_counter_wrap.v:10: syntax error, unexpected \',\', expecting \'[\'\n    ,parameter                      OUTPORT_QUANT       = 1\n    ^\n%Error: data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/flit_counter_wrap.v:11: syntax error, unexpected \')\', expecting \';\'\n)\n^\n%Error: data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/flit_counter_wrap.v:14: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire                                    reset_q_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/flit_counter_wrap.v:15: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire    [OUTPORT_QUANT-1:0]             cnt_en_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/flit_counter_wrap.v:16: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  wire    [CNT_SIZE-1:0]                  cnt_data_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/flit_counter_wrap.v:17: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire    [clogb2(OUTPORT_QUANT)-1:0]     cnt_port_sel_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/flit_counter_wrap.v:18: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input   wire                                    cnt_rst_i\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_router/source/rtl/verilog/flit_counter_wrap.v:35: syntax error, unexpected genvar\n    genvar gen_i;\n    ^~~~~~\n%Error: Exiting due to 9 error(s)\n'
function integer clogb2 (input [31:0] value_in);
        reg [31:0] value;
        begin
            value = value_in - 1;
            for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
                value = value >> 1;
        end
    endfunction
function integer clogb2 (input [31:0] value_in);

        reg [31:0] value;
        begin
            value = value_in - 1;
            for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
                value = value >> 1;
        end
    endfunction