data/full_repos/permissive/488490114/FSM.v
1: b'%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:30: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                             : ... In instance FSM\n state = 4\'d0; \n       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:42: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                             : ... In instance FSM\n  state <= 4\'d0;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:54: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                             : ... In instance FSM\n     state <= 4\'d1;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:58: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                             : ... In instance FSM\n     state <= 4\'d1;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:62: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                             : ... In instance FSM\n     state <= 4\'d1;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:66: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                             : ... In instance FSM\n     state <= 4\'d1;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:70: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                             : ... In instance FSM\n     state <= 4\'d1;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:74: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                             : ... In instance FSM\n     state <= 4\'d1;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:82: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h2\' generates 4 bits.\n                                                             : ... In instance FSM\n     state <= 4\'d2;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:86: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h2\' generates 4 bits.\n                                                             : ... In instance FSM\n     state <= 4\'d2;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:90: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h2\' generates 4 bits.\n                                                             : ... In instance FSM\n     state <= 4\'d2;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:94: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h2\' generates 4 bits.\n                                                             : ... In instance FSM\n     state <= 4\'d2;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:98: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h2\' generates 4 bits.\n                                                             : ... In instance FSM\n     state <= 4\'d2;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:102: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h2\' generates 4 bits.\n                                                              : ... In instance FSM\n     state <= 4\'d2;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:110: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h3\' generates 4 bits.\n                                                              : ... In instance FSM\n     state <= 4\'d3;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:114: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h3\' generates 4 bits.\n                                                              : ... In instance FSM\n     state <= 4\'d3;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:118: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h3\' generates 4 bits.\n                                                              : ... In instance FSM\n     state <= 4\'d3;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:122: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h3\' generates 4 bits.\n                                                              : ... In instance FSM\n     state <= 4\'d3;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:126: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h3\' generates 4 bits.\n                                                              : ... In instance FSM\n     state <= 4\'d3;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:130: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h3\' generates 4 bits.\n                                                              : ... In instance FSM\n     state <= 4\'d3;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:137: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h4\' generates 4 bits.\n                                                              : ... In instance FSM\n     state <= 4\'d4;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:141: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h4\' generates 4 bits.\n                                                              : ... In instance FSM\n     state <= 4\'d4;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:145: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h4\' generates 4 bits.\n                                                              : ... In instance FSM\n     state <= 4\'d4;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:149: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h4\' generates 4 bits.\n                                                              : ... In instance FSM\n     state <= 4\'d4;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:153: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h4\' generates 4 bits.\n                                                              : ... In instance FSM\n     state <= 4\'d4;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:157: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h4\' generates 4 bits.\n                                                              : ... In instance FSM\n     state <= 4\'d4;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:164: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h5\' generates 4 bits.\n                                                              : ... In instance FSM\n     state <= 4\'d5;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:168: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h5\' generates 4 bits.\n                                                              : ... In instance FSM\n     state <= 4\'d5;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:172: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h5\' generates 4 bits.\n                                                              : ... In instance FSM\n     state <= 4\'d5;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:176: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h5\' generates 4 bits.\n                                                              : ... In instance FSM\n     state <= 4\'d5;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:180: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h5\' generates 4 bits.\n                                                              : ... In instance FSM\n     state <= 4\'d5;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:184: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h5\' generates 4 bits.\n                                                              : ... In instance FSM\n     state <= 4\'d5;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:191: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h6\' generates 4 bits.\n                                                              : ... In instance FSM\n     state <= 4\'d6;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:195: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h6\' generates 4 bits.\n                                                              : ... In instance FSM\n     state <= 4\'d6;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:199: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h6\' generates 4 bits.\n                                                              : ... In instance FSM\n     state <= 4\'d6;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:203: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h6\' generates 4 bits.\n                                                              : ... In instance FSM\n     state <= 4\'d6;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:207: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h6\' generates 4 bits.\n                                                              : ... In instance FSM\n     state <= 4\'d6;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:211: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h6\' generates 4 bits.\n                                                              : ... In instance FSM\n     state <= 4\'d6;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:224: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                              : ... In instance FSM\n     state <= 4\'d0;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:240: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                              : ... In instance FSM\n     state <= 4\'d0;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:245: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                              : ... In instance FSM\n     state <= 4\'d0;\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/488490114/FSM.v:49: Operator CASE expects 4 bits on the Case expression, but Case expression\'s VARREF \'state\' generates 3 bits.\n                                                             : ... In instance FSM\n  case(state)\n  ^~~~\n%Error: Exiting due to 42 warning(s)\n'
module FSM(
input CLK,
input RST,
input BTNA,
input BTNB,
input BTNC,
input BTND,
input BTNE,
input BTNF,
output reg [23:0]SEG,
output reg SUCESS_FLAG,
output reg WRONG_FLAG
);

reg [2:0]state;
reg [3:0]data [0:5];
reg [3:0]sucess_comb [0:5];

integer i;

initial begin
	state = `S0;	
	sucess_comb[0] = 4'd1;
	sucess_comb[1] = 4'd2;
	sucess_comb[2] = 4'd3;
	sucess_comb[3] = 4'd4;
	sucess_comb[4] = 4'd5;
	sucess_comb[5] = 4'd6;
end

always@(posedge CLK)
begin
	if(RST) begin
		state <= `S0;
		for(i=0; i < 6; i = i + 1)
			data[i] <= 0;
		SUCESS_FLAG <= 0;
		WRONG_FLAG <= 0;
	end
	else begin 
		case(state)
		`S0:
			begin 
				if(BTNA) begin
					data[0] <= 4'd1;
					state <= `S1;
				end
				else if (BTNB) begin
					data[0] <= 4'd2;
					state <= `S1;
				end
				else if (BTNC) begin
					data[0] <= 4'd3;
					state <= `S1;
				end
				else if (BTND) begin
					data[0] <= 4'd4;
					state <= `S1;
				end
				else if (BTNE) begin
					data[0] <= 4'd5;
					state <= `S1;
				end
				else if (BTNF) begin
					data[0] <= 4'd6;
					state <= `S1;
				end
			end
			
		`S1:
			begin 
				if(BTNA) begin
					data[1] <= 4'd1;
					state <= `S2;
				end
				else if (BTNB) begin
					data[1] <= 4'd2;
					state <= `S2;
				end
				else if (BTNC) begin
					data[1] <= 4'd3;
					state <= `S2;
				end
				else if (BTND) begin
					data[1] <= 4'd4;
					state <= `S2;
				end
				else if (BTNE) begin
					data[1] <= 4'd5;
					state <= `S2;
				end
				else if (BTNF) begin
					data[1] <= 4'd6;
					state <= `S2;
				end
			end
			
		`S2:
			begin
				if(BTNA) begin
					data[2] <= 4'd1;
					state <= `S3;
				end
				else if (BTNB) begin
					data[2] <= 4'd2;
					state <= `S3;
				end
				else if (BTNC) begin
					data[2] <= 4'd3;
					state <= `S3;
				end
				else if (BTND) begin
					data[2] <= 4'd4;
					state <= `S3;
				end
				else if (BTNE) begin
					data[2] <= 4'd5;
					state <= `S3;
				end
				else if (BTNF) begin
					data[2] <= 4'd6;
					state <= `S3;
				end
			end
		`S3:
			begin
				if(BTNA) begin
					data[3] <= 4'd1;
					state <= `S4;
				end
				else if (BTNB) begin
					data[3] <= 4'd2;
					state <= `S4;
				end
				else if (BTNC) begin
					data[3] <= 4'd3;
					state <= `S4;
				end
				else if (BTND) begin
					data[3] <= 4'd4;
					state <= `S4;
				end
				else if (BTNE) begin
					data[3] <= 4'd5;
					state <= `S4;
				end
				else if (BTNF) begin
					data[3] <= 4'd6;
					state <= `S4;
				end
			end
		`S4:
			begin
				if(BTNA) begin
					data[4] <= 4'd1;
					state <= `S5;
				end
				else if (BTNB) begin
					data[4] <= 4'd2;
					state <= `S5;
				end
				else if (BTNC) begin
					data[4] <= 4'd3;
					state <= `S5;
				end
				else if (BTND) begin
					data[4] <= 4'd4;
					state <= `S5;
				end
				else if (BTNE) begin
					data[4] <= 4'd5;
					state <= `S5;
				end
				else if (BTNF) begin
					data[4] <= 4'd6;
					state <= `S5;
				end
			end
		`S5:
			begin 
				if(BTNA) begin
					data[5] <= 4'd1;
					state <= `S6;
				end
				else if (BTNB) begin
					data[5] <= 4'd2;
					state <= `S6;
				end
				else if (BTNC) begin
					data[5] <= 4'd3;
					state <= `S6;
				end
				else if (BTND) begin
					data[5] <= 4'd4;
					state <= `S6;
				end
				else if (BTNE) begin
					data[5] <= 4'd5;
					state <= `S6;
				end
				else if (BTNF) begin
					data[5] <= 4'd6;
					state <= `S6;
				end
			end
		`S6:
			begin
				if((data[0] == sucess_comb[0])&
				(data[1] == sucess_comb[1])&
				(data[2] == sucess_comb[2])&
				(data[3] == sucess_comb[3])&
				(data[4] == sucess_comb[4])&
				(data[5] == sucess_comb[5])) begin
					SUCESS_FLAG <= 1;
					WRONG_FLAG <= 0;
					state <= `S0;
				end
				else if((data[0] != sucess_comb[0])|
				(data[1] != sucess_comb[1])|
				(data[2] != sucess_comb[2])|
				(data[3] != sucess_comb[3])|
				(data[4] != sucess_comb[4])|
				(data[5] != sucess_comb[5])) begin
					WRONG_FLAG <= 1;
					SUCESS_FLAG <= 0;
					SEG[3:0] <= data[0];
					SEG[7:4] <= data[1];
					SEG[11:8] <= data[2];
					SEG[15:12] <= data[3];
					SEG[19:16] <= data[4];
					SEG[23:20] <= data[5];
					state <= `S0;
				end	
				else begin
					SUCESS_FLAG <= 0;
					WRONG_FLAG <= 0;
					state <= `S0;
				end
			end
		endcase
	end
end
endmodule
module FSM(
input CLK,
input RST,
input BTNA,
input BTNB,
input BTNC,
input BTND,
input BTNE,
input BTNF,
output reg [23:0]SEG,
output reg SUCESS_FLAG,
output reg WRONG_FLAG
);


reg [2:0]state;
reg [3:0]data [0:5];
reg [3:0]sucess_comb [0:5];

integer i;

initial begin
	state = `S0;	
	sucess_comb[0] = 4'd1;
	sucess_comb[1] = 4'd2;
	sucess_comb[2] = 4'd3;
	sucess_comb[3] = 4'd4;
	sucess_comb[4] = 4'd5;
	sucess_comb[5] = 4'd6;
end

always@(posedge CLK)
begin
	if(RST) begin
		state <= `S0;
		for(i=0; i < 6; i = i + 1)
			data[i] <= 0;
		SUCESS_FLAG <= 0;
		WRONG_FLAG <= 0;
	end
	else begin 
		case(state)
		`S0:
			begin 
				if(BTNA) begin
					data[0] <= 4'd1;
					state <= `S1;
				end
				else if (BTNB) begin
					data[0] <= 4'd2;
					state <= `S1;
				end
				else if (BTNC) begin
					data[0] <= 4'd3;
					state <= `S1;
				end
				else if (BTND) begin
					data[0] <= 4'd4;
					state <= `S1;
				end
				else if (BTNE) begin
					data[0] <= 4'd5;
					state <= `S1;
				end
				else if (BTNF) begin
					data[0] <= 4'd6;
					state <= `S1;
				end
			end
			
		`S1:
			begin 
				if(BTNA) begin
					data[1] <= 4'd1;
					state <= `S2;
				end
				else if (BTNB) begin
					data[1] <= 4'd2;
					state <= `S2;
				end
				else if (BTNC) begin
					data[1] <= 4'd3;
					state <= `S2;
				end
				else if (BTND) begin
					data[1] <= 4'd4;
					state <= `S2;
				end
				else if (BTNE) begin
					data[1] <= 4'd5;
					state <= `S2;
				end
				else if (BTNF) begin
					data[1] <= 4'd6;
					state <= `S2;
				end
			end
			
		`S2:
			begin
				if(BTNA) begin
					data[2] <= 4'd1;
					state <= `S3;
				end
				else if (BTNB) begin
					data[2] <= 4'd2;
					state <= `S3;
				end
				else if (BTNC) begin
					data[2] <= 4'd3;
					state <= `S3;
				end
				else if (BTND) begin
					data[2] <= 4'd4;
					state <= `S3;
				end
				else if (BTNE) begin
					data[2] <= 4'd5;
					state <= `S3;
				end
				else if (BTNF) begin
					data[2] <= 4'd6;
					state <= `S3;
				end
			end
		`S3:
			begin
				if(BTNA) begin
					data[3] <= 4'd1;
					state <= `S4;
				end
				else if (BTNB) begin
					data[3] <= 4'd2;
					state <= `S4;
				end
				else if (BTNC) begin
					data[3] <= 4'd3;
					state <= `S4;
				end
				else if (BTND) begin
					data[3] <= 4'd4;
					state <= `S4;
				end
				else if (BTNE) begin
					data[3] <= 4'd5;
					state <= `S4;
				end
				else if (BTNF) begin
					data[3] <= 4'd6;
					state <= `S4;
				end
			end
		`S4:
			begin
				if(BTNA) begin
					data[4] <= 4'd1;
					state <= `S5;
				end
				else if (BTNB) begin
					data[4] <= 4'd2;
					state <= `S5;
				end
				else if (BTNC) begin
					data[4] <= 4'd3;
					state <= `S5;
				end
				else if (BTND) begin
					data[4] <= 4'd4;
					state <= `S5;
				end
				else if (BTNE) begin
					data[4] <= 4'd5;
					state <= `S5;
				end
				else if (BTNF) begin
					data[4] <= 4'd6;
					state <= `S5;
				end
			end
		`S5:
			begin 
				if(BTNA) begin
					data[5] <= 4'd1;
					state <= `S6;
				end
				else if (BTNB) begin
					data[5] <= 4'd2;
					state <= `S6;
				end
				else if (BTNC) begin
					data[5] <= 4'd3;
					state <= `S6;
				end
				else if (BTND) begin
					data[5] <= 4'd4;
					state <= `S6;
				end
				else if (BTNE) begin
					data[5] <= 4'd5;
					state <= `S6;
				end
				else if (BTNF) begin
					data[5] <= 4'd6;
					state <= `S6;
				end
			end
		`S6:
			begin
				if((data[0] == sucess_comb[0])&
				(data[1] == sucess_comb[1])&
				(data[2] == sucess_comb[2])&
				(data[3] == sucess_comb[3])&
				(data[4] == sucess_comb[4])&
				(data[5] == sucess_comb[5])) begin
					SUCESS_FLAG <= 1;
					WRONG_FLAG <= 0;
					state <= `S0;
				end
				else if((data[0] != sucess_comb[0])|
				(data[1] != sucess_comb[1])|
				(data[2] != sucess_comb[2])|
				(data[3] != sucess_comb[3])|
				(data[4] != sucess_comb[4])|
				(data[5] != sucess_comb[5])) begin
					WRONG_FLAG <= 1;
					SUCESS_FLAG <= 0;
					SEG[3:0] <= data[0];
					SEG[7:4] <= data[1];
					SEG[11:8] <= data[2];
					SEG[15:12] <= data[3];
					SEG[19:16] <= data[4];
					SEG[23:20] <= data[5];
					state <= `S0;
				end	
				else begin
					SUCESS_FLAG <= 0;
					WRONG_FLAG <= 0;
					state <= `S0;
				end
			end
		endcase
	end
end
endmodule