data/full_repos/permissive/46132596/processor/SingleCycleDatapath/PcRegister.v
data/verilator_xmls/df9e012c-9a66-4576-9710-679ebd377201.xml
module PcRegister(input clock,
		input clear,
		input[31:0] in,
		output reg[31:0] out);


	always @(posedge clear, negedge clock)
		if (clear)
			out = 32'h00400000;
		else
			out = in;
endmodule
module PcRegister(input clock,
		input clear,
		input[31:0] in,
		output reg[31:0] out);



	always @(posedge clear, negedge clock)
		if (clear)
			out = 32'h00400000;
		else
			out = in;
endmodule