data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:33: Little bit endian vector: MSB < LSB of bit range: 0:12\ninput [0:12] chanx_left_in;\n      ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:35: Little bit endian vector: MSB < LSB of bit range: 0:12\ninput [0:12] chanx_right_in;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:37: Little bit endian vector: MSB < LSB of bit range: 0:65\ninput [0:65] bl;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:39: Little bit endian vector: MSB < LSB of bit range: 0:65\ninput [0:65] wl;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:41: Little bit endian vector: MSB < LSB of bit range: 0:12\noutput [0:12] chanx_left_out;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:43: Little bit endian vector: MSB < LSB of bit range: 0:12\noutput [0:12] chanx_right_out;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:75: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_0_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:76: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_0_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:77: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_10_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:78: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_10_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:79: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_1_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:80: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_1_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:81: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_2_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:82: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_2_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:83: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_3_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:84: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_3_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:85: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_4_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:86: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_4_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:87: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_5_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:88: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_5_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:89: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_6_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:90: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_6_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:91: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_7_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:92: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_7_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:93: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_8_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:94: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_8_sram_inv;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:95: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_9_sram;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:96: Little bit endian vector: MSB < LSB of bit range: 0:5\nwire [0:5] mux_2level_tapbuf_size6_9_sram_inv;\n     ^\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:207: Cannot find file containing module: \'mux_2level_tapbuf_size6\'\n mux_2level_tapbuf_size6 mux_bottom_ipin_0 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/mux_2level_tapbuf_size6\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/mux_2level_tapbuf_size6.v\n             data/full_repos/permissive/485085993/verilog/rtl,data/full_repos/permissive/485085993/mux_2level_tapbuf_size6.sv\n             mux_2level_tapbuf_size6\n             mux_2level_tapbuf_size6.v\n             mux_2level_tapbuf_size6.sv\n             obj_dir/mux_2level_tapbuf_size6\n             obj_dir/mux_2level_tapbuf_size6.v\n             obj_dir/mux_2level_tapbuf_size6.sv\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:213: Cannot find file containing module: \'mux_2level_tapbuf_size6\'\n mux_2level_tapbuf_size6 mux_bottom_ipin_1 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:219: Cannot find file containing module: \'mux_2level_tapbuf_size6\'\n mux_2level_tapbuf_size6 mux_bottom_ipin_2 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:225: Cannot find file containing module: \'mux_2level_tapbuf_size6\'\n mux_2level_tapbuf_size6 mux_top_ipin_0 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:231: Cannot find file containing module: \'mux_2level_tapbuf_size6\'\n mux_2level_tapbuf_size6 mux_top_ipin_1 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:237: Cannot find file containing module: \'mux_2level_tapbuf_size6\'\n mux_2level_tapbuf_size6 mux_top_ipin_2 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:243: Cannot find file containing module: \'mux_2level_tapbuf_size6\'\n mux_2level_tapbuf_size6 mux_top_ipin_3 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:249: Cannot find file containing module: \'mux_2level_tapbuf_size6\'\n mux_2level_tapbuf_size6 mux_top_ipin_4 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:255: Cannot find file containing module: \'mux_2level_tapbuf_size6\'\n mux_2level_tapbuf_size6 mux_top_ipin_5 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:261: Cannot find file containing module: \'mux_2level_tapbuf_size6\'\n mux_2level_tapbuf_size6 mux_top_ipin_6 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:267: Cannot find file containing module: \'mux_2level_tapbuf_size6\'\n mux_2level_tapbuf_size6 mux_top_ipin_7 (\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:273: Cannot find file containing module: \'mux_2level_tapbuf_size6_mem\'\n mux_2level_tapbuf_size6_mem mem_bottom_ipin_0 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:279: Cannot find file containing module: \'mux_2level_tapbuf_size6_mem\'\n mux_2level_tapbuf_size6_mem mem_bottom_ipin_1 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:285: Cannot find file containing module: \'mux_2level_tapbuf_size6_mem\'\n mux_2level_tapbuf_size6_mem mem_bottom_ipin_2 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:291: Cannot find file containing module: \'mux_2level_tapbuf_size6_mem\'\n mux_2level_tapbuf_size6_mem mem_top_ipin_0 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:297: Cannot find file containing module: \'mux_2level_tapbuf_size6_mem\'\n mux_2level_tapbuf_size6_mem mem_top_ipin_1 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:303: Cannot find file containing module: \'mux_2level_tapbuf_size6_mem\'\n mux_2level_tapbuf_size6_mem mem_top_ipin_2 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:309: Cannot find file containing module: \'mux_2level_tapbuf_size6_mem\'\n mux_2level_tapbuf_size6_mem mem_top_ipin_3 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:315: Cannot find file containing module: \'mux_2level_tapbuf_size6_mem\'\n mux_2level_tapbuf_size6_mem mem_top_ipin_4 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:321: Cannot find file containing module: \'mux_2level_tapbuf_size6_mem\'\n mux_2level_tapbuf_size6_mem mem_top_ipin_5 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:327: Cannot find file containing module: \'mux_2level_tapbuf_size6_mem\'\n mux_2level_tapbuf_size6_mem mem_top_ipin_6 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485085993/verilog/rtl/cbx_1__0_.v:333: Cannot find file containing module: \'mux_2level_tapbuf_size6_mem\'\n mux_2level_tapbuf_size6_mem mem_top_ipin_7 (\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 22 error(s), 28 warning(s)\n'
module cbx_1__0_(chanx_left_in,
                 chanx_right_in,
                 bl,
                 wl,
                 chanx_left_out,
                 chanx_right_out,
                 top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_,
                 top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_,
                 top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_,
                 bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_,
                 bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_,
                 bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_,
                 bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_,
                 bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_,
                 bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_,
                 bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_,
                 bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_);

input [0:12] chanx_left_in;

input [0:12] chanx_right_in;

input [0:65] bl;

input [0:65] wl;

output [0:12] chanx_left_out;

output [0:12] chanx_right_out;

output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_;

output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_;

output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_;

output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_;

output [0:0] bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_;

output [0:0] bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_;

output [0:0] bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_;

output [0:0] bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_;

output [0:0] bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_;

output [0:0] bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_;

output [0:0] bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_;









wire [0:5] mux_2level_tapbuf_size6_0_sram;
wire [0:5] mux_2level_tapbuf_size6_0_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_10_sram;
wire [0:5] mux_2level_tapbuf_size6_10_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_1_sram;
wire [0:5] mux_2level_tapbuf_size6_1_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_2_sram;
wire [0:5] mux_2level_tapbuf_size6_2_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_3_sram;
wire [0:5] mux_2level_tapbuf_size6_3_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_4_sram;
wire [0:5] mux_2level_tapbuf_size6_4_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_5_sram;
wire [0:5] mux_2level_tapbuf_size6_5_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_6_sram;
wire [0:5] mux_2level_tapbuf_size6_6_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_7_sram;
wire [0:5] mux_2level_tapbuf_size6_7_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_8_sram;
wire [0:5] mux_2level_tapbuf_size6_8_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_9_sram;
wire [0:5] mux_2level_tapbuf_size6_9_sram_inv;





	assign chanx_right_out[0] = chanx_left_in[0];



	assign chanx_right_out[1] = chanx_left_in[1];



	assign chanx_right_out[2] = chanx_left_in[2];



	assign chanx_right_out[3] = chanx_left_in[3];



	assign chanx_right_out[4] = chanx_left_in[4];



	assign chanx_right_out[5] = chanx_left_in[5];



	assign chanx_right_out[6] = chanx_left_in[6];



	assign chanx_right_out[7] = chanx_left_in[7];



	assign chanx_right_out[8] = chanx_left_in[8];



	assign chanx_right_out[9] = chanx_left_in[9];



	assign chanx_right_out[10] = chanx_left_in[10];



	assign chanx_right_out[11] = chanx_left_in[11];



	assign chanx_right_out[12] = chanx_left_in[12];



	assign chanx_left_out[0] = chanx_right_in[0];



	assign chanx_left_out[1] = chanx_right_in[1];



	assign chanx_left_out[2] = chanx_right_in[2];



	assign chanx_left_out[3] = chanx_right_in[3];



	assign chanx_left_out[4] = chanx_right_in[4];



	assign chanx_left_out[5] = chanx_right_in[5];



	assign chanx_left_out[6] = chanx_right_in[6];



	assign chanx_left_out[7] = chanx_right_in[7];



	assign chanx_left_out[8] = chanx_right_in[8];



	assign chanx_left_out[9] = chanx_right_in[9];



	assign chanx_left_out[10] = chanx_right_in[10];



	assign chanx_left_out[11] = chanx_right_in[11];



	assign chanx_left_out[12] = chanx_right_in[12];




	mux_2level_tapbuf_size6 mux_bottom_ipin_0 (
		.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12]}),
		.sram(mux_2level_tapbuf_size6_0_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_0_sram_inv[0:5]),
		.out(top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_));

	mux_2level_tapbuf_size6 mux_bottom_ipin_1 (
		.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[7], chanx_right_in[7]}),
		.sram(mux_2level_tapbuf_size6_1_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_1_sram_inv[0:5]),
		.out(top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_));

	mux_2level_tapbuf_size6 mux_bottom_ipin_2 (
		.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8]}),
		.sram(mux_2level_tapbuf_size6_2_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_2_sram_inv[0:5]),
		.out(top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_));

	mux_2level_tapbuf_size6 mux_top_ipin_0 (
		.in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9]}),
		.sram(mux_2level_tapbuf_size6_3_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_3_sram_inv[0:5]),
		.out(bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_));

	mux_2level_tapbuf_size6 mux_top_ipin_1 (
		.in({chanx_left_in[3], chanx_right_in[3], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10]}),
		.sram(mux_2level_tapbuf_size6_4_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_4_sram_inv[0:5]),
		.out(bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_));

	mux_2level_tapbuf_size6 mux_top_ipin_2 (
		.in({chanx_left_in[4], chanx_right_in[4], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11]}),
		.sram(mux_2level_tapbuf_size6_5_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_5_sram_inv[0:5]),
		.out(bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_));

	mux_2level_tapbuf_size6 mux_top_ipin_3 (
		.in({chanx_left_in[5], chanx_right_in[5], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12]}),
		.sram(mux_2level_tapbuf_size6_6_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_6_sram_inv[0:5]),
		.out(bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_));

	mux_2level_tapbuf_size6 mux_top_ipin_4 (
		.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[6], chanx_right_in[6], chanx_left_in[7], chanx_right_in[7]}),
		.sram(mux_2level_tapbuf_size6_7_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_7_sram_inv[0:5]),
		.out(bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_));

	mux_2level_tapbuf_size6 mux_top_ipin_5 (
		.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[7], chanx_right_in[7], chanx_left_in[8], chanx_right_in[8]}),
		.sram(mux_2level_tapbuf_size6_8_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_8_sram_inv[0:5]),
		.out(bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_));

	mux_2level_tapbuf_size6 mux_top_ipin_6 (
		.in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[9], chanx_right_in[9]}),
		.sram(mux_2level_tapbuf_size6_9_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_9_sram_inv[0:5]),
		.out(bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_));

	mux_2level_tapbuf_size6 mux_top_ipin_7 (
		.in({chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[10], chanx_right_in[10]}),
		.sram(mux_2level_tapbuf_size6_10_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_10_sram_inv[0:5]),
		.out(bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_));

	mux_2level_tapbuf_size6_mem mem_bottom_ipin_0 (
		.bl(bl[0:5]),
		.wl(wl[0:5]),
		.mem_out(mux_2level_tapbuf_size6_0_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_0_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_bottom_ipin_1 (
		.bl(bl[6:11]),
		.wl(wl[6:11]),
		.mem_out(mux_2level_tapbuf_size6_1_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_1_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_bottom_ipin_2 (
		.bl(bl[12:17]),
		.wl(wl[12:17]),
		.mem_out(mux_2level_tapbuf_size6_2_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_2_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_top_ipin_0 (
		.bl(bl[18:23]),
		.wl(wl[18:23]),
		.mem_out(mux_2level_tapbuf_size6_3_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_3_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_top_ipin_1 (
		.bl(bl[24:29]),
		.wl(wl[24:29]),
		.mem_out(mux_2level_tapbuf_size6_4_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_4_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_top_ipin_2 (
		.bl(bl[30:35]),
		.wl(wl[30:35]),
		.mem_out(mux_2level_tapbuf_size6_5_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_5_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_top_ipin_3 (
		.bl(bl[36:41]),
		.wl(wl[36:41]),
		.mem_out(mux_2level_tapbuf_size6_6_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_6_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_top_ipin_4 (
		.bl(bl[42:47]),
		.wl(wl[42:47]),
		.mem_out(mux_2level_tapbuf_size6_7_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_7_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_top_ipin_5 (
		.bl(bl[48:53]),
		.wl(wl[48:53]),
		.mem_out(mux_2level_tapbuf_size6_8_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_8_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_top_ipin_6 (
		.bl(bl[54:59]),
		.wl(wl[54:59]),
		.mem_out(mux_2level_tapbuf_size6_9_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_9_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_top_ipin_7 (
		.bl(bl[60:65]),
		.wl(wl[60:65]),
		.mem_out(mux_2level_tapbuf_size6_10_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_10_sram_inv[0:5]));

endmodule
module cbx_1__0_(chanx_left_in,
                 chanx_right_in,
                 bl,
                 wl,
                 chanx_left_out,
                 chanx_right_out,
                 top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_,
                 top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_,
                 top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_,
                 bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_,
                 bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_,
                 bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_,
                 bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_,
                 bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_,
                 bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_,
                 bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_,
                 bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_);


input [0:12] chanx_left_in;

input [0:12] chanx_right_in;

input [0:65] bl;

input [0:65] wl;

output [0:12] chanx_left_out;

output [0:12] chanx_right_out;

output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_;

output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_;

output [0:0] top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_;

output [0:0] bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_;

output [0:0] bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_;

output [0:0] bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_;

output [0:0] bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_;

output [0:0] bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_;

output [0:0] bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_;

output [0:0] bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_;

output [0:0] bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_;









wire [0:5] mux_2level_tapbuf_size6_0_sram;
wire [0:5] mux_2level_tapbuf_size6_0_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_10_sram;
wire [0:5] mux_2level_tapbuf_size6_10_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_1_sram;
wire [0:5] mux_2level_tapbuf_size6_1_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_2_sram;
wire [0:5] mux_2level_tapbuf_size6_2_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_3_sram;
wire [0:5] mux_2level_tapbuf_size6_3_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_4_sram;
wire [0:5] mux_2level_tapbuf_size6_4_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_5_sram;
wire [0:5] mux_2level_tapbuf_size6_5_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_6_sram;
wire [0:5] mux_2level_tapbuf_size6_6_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_7_sram;
wire [0:5] mux_2level_tapbuf_size6_7_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_8_sram;
wire [0:5] mux_2level_tapbuf_size6_8_sram_inv;
wire [0:5] mux_2level_tapbuf_size6_9_sram;
wire [0:5] mux_2level_tapbuf_size6_9_sram_inv;





	assign chanx_right_out[0] = chanx_left_in[0];



	assign chanx_right_out[1] = chanx_left_in[1];



	assign chanx_right_out[2] = chanx_left_in[2];



	assign chanx_right_out[3] = chanx_left_in[3];



	assign chanx_right_out[4] = chanx_left_in[4];



	assign chanx_right_out[5] = chanx_left_in[5];



	assign chanx_right_out[6] = chanx_left_in[6];



	assign chanx_right_out[7] = chanx_left_in[7];



	assign chanx_right_out[8] = chanx_left_in[8];



	assign chanx_right_out[9] = chanx_left_in[9];



	assign chanx_right_out[10] = chanx_left_in[10];



	assign chanx_right_out[11] = chanx_left_in[11];



	assign chanx_right_out[12] = chanx_left_in[12];



	assign chanx_left_out[0] = chanx_right_in[0];



	assign chanx_left_out[1] = chanx_right_in[1];



	assign chanx_left_out[2] = chanx_right_in[2];



	assign chanx_left_out[3] = chanx_right_in[3];



	assign chanx_left_out[4] = chanx_right_in[4];



	assign chanx_left_out[5] = chanx_right_in[5];



	assign chanx_left_out[6] = chanx_right_in[6];



	assign chanx_left_out[7] = chanx_right_in[7];



	assign chanx_left_out[8] = chanx_right_in[8];



	assign chanx_left_out[9] = chanx_right_in[9];



	assign chanx_left_out[10] = chanx_right_in[10];



	assign chanx_left_out[11] = chanx_right_in[11];



	assign chanx_left_out[12] = chanx_right_in[12];




	mux_2level_tapbuf_size6 mux_bottom_ipin_0 (
		.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12]}),
		.sram(mux_2level_tapbuf_size6_0_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_0_sram_inv[0:5]),
		.out(top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_));

	mux_2level_tapbuf_size6 mux_bottom_ipin_1 (
		.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[1], chanx_right_in[1], chanx_left_in[7], chanx_right_in[7]}),
		.sram(mux_2level_tapbuf_size6_1_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_1_sram_inv[0:5]),
		.out(top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_));

	mux_2level_tapbuf_size6 mux_bottom_ipin_2 (
		.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8]}),
		.sram(mux_2level_tapbuf_size6_2_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_2_sram_inv[0:5]),
		.out(top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_));

	mux_2level_tapbuf_size6 mux_top_ipin_0 (
		.in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9]}),
		.sram(mux_2level_tapbuf_size6_3_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_3_sram_inv[0:5]),
		.out(bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_));

	mux_2level_tapbuf_size6 mux_top_ipin_1 (
		.in({chanx_left_in[3], chanx_right_in[3], chanx_left_in[4], chanx_right_in[4], chanx_left_in[10], chanx_right_in[10]}),
		.sram(mux_2level_tapbuf_size6_4_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_4_sram_inv[0:5]),
		.out(bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_));

	mux_2level_tapbuf_size6 mux_top_ipin_2 (
		.in({chanx_left_in[4], chanx_right_in[4], chanx_left_in[5], chanx_right_in[5], chanx_left_in[11], chanx_right_in[11]}),
		.sram(mux_2level_tapbuf_size6_5_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_5_sram_inv[0:5]),
		.out(bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_));

	mux_2level_tapbuf_size6 mux_top_ipin_3 (
		.in({chanx_left_in[5], chanx_right_in[5], chanx_left_in[6], chanx_right_in[6], chanx_left_in[12], chanx_right_in[12]}),
		.sram(mux_2level_tapbuf_size6_6_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_6_sram_inv[0:5]),
		.out(bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_));

	mux_2level_tapbuf_size6 mux_top_ipin_4 (
		.in({chanx_left_in[0], chanx_right_in[0], chanx_left_in[6], chanx_right_in[6], chanx_left_in[7], chanx_right_in[7]}),
		.sram(mux_2level_tapbuf_size6_7_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_7_sram_inv[0:5]),
		.out(bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_));

	mux_2level_tapbuf_size6 mux_top_ipin_5 (
		.in({chanx_left_in[1], chanx_right_in[1], chanx_left_in[7], chanx_right_in[7], chanx_left_in[8], chanx_right_in[8]}),
		.sram(mux_2level_tapbuf_size6_8_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_8_sram_inv[0:5]),
		.out(bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_));

	mux_2level_tapbuf_size6 mux_top_ipin_6 (
		.in({chanx_left_in[2], chanx_right_in[2], chanx_left_in[8], chanx_right_in[8], chanx_left_in[9], chanx_right_in[9]}),
		.sram(mux_2level_tapbuf_size6_9_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_9_sram_inv[0:5]),
		.out(bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_));

	mux_2level_tapbuf_size6 mux_top_ipin_7 (
		.in({chanx_left_in[3], chanx_right_in[3], chanx_left_in[9], chanx_right_in[9], chanx_left_in[10], chanx_right_in[10]}),
		.sram(mux_2level_tapbuf_size6_10_sram[0:5]),
		.sram_inv(mux_2level_tapbuf_size6_10_sram_inv[0:5]),
		.out(bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_));

	mux_2level_tapbuf_size6_mem mem_bottom_ipin_0 (
		.bl(bl[0:5]),
		.wl(wl[0:5]),
		.mem_out(mux_2level_tapbuf_size6_0_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_0_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_bottom_ipin_1 (
		.bl(bl[6:11]),
		.wl(wl[6:11]),
		.mem_out(mux_2level_tapbuf_size6_1_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_1_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_bottom_ipin_2 (
		.bl(bl[12:17]),
		.wl(wl[12:17]),
		.mem_out(mux_2level_tapbuf_size6_2_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_2_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_top_ipin_0 (
		.bl(bl[18:23]),
		.wl(wl[18:23]),
		.mem_out(mux_2level_tapbuf_size6_3_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_3_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_top_ipin_1 (
		.bl(bl[24:29]),
		.wl(wl[24:29]),
		.mem_out(mux_2level_tapbuf_size6_4_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_4_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_top_ipin_2 (
		.bl(bl[30:35]),
		.wl(wl[30:35]),
		.mem_out(mux_2level_tapbuf_size6_5_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_5_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_top_ipin_3 (
		.bl(bl[36:41]),
		.wl(wl[36:41]),
		.mem_out(mux_2level_tapbuf_size6_6_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_6_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_top_ipin_4 (
		.bl(bl[42:47]),
		.wl(wl[42:47]),
		.mem_out(mux_2level_tapbuf_size6_7_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_7_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_top_ipin_5 (
		.bl(bl[48:53]),
		.wl(wl[48:53]),
		.mem_out(mux_2level_tapbuf_size6_8_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_8_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_top_ipin_6 (
		.bl(bl[54:59]),
		.wl(wl[54:59]),
		.mem_out(mux_2level_tapbuf_size6_9_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_9_sram_inv[0:5]));

	mux_2level_tapbuf_size6_mem mem_top_ipin_7 (
		.bl(bl[60:65]),
		.wl(wl[60:65]),
		.mem_out(mux_2level_tapbuf_size6_10_sram[0:5]),
		.mem_outb(mux_2level_tapbuf_size6_10_sram_inv[0:5]));

endmodule