data/full_repos/permissive/43858668/final_verilog/src/clib/c_prefix_net.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_prefix_net.v:35: Cannot find include file: c_functions.v\n`include "c_functions.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v.sv\n             c_functions.v\n             c_functions.v.v\n             c_functions.v.sv\n             obj_dir/c_functions.v\n             obj_dir/c_functions.v.v\n             obj_dir/c_functions.v.sv\n%Error: Exiting due to 1 error(s)\n'
module c_prefix_net
  (g_in, p_in, g_out, p_out);
   
`include "c_functions.v"
   

   parameter width = 16;
   

   parameter enable_wraparound = 0;
   

   localparam depth = clogb(width);
   

   localparam ext_width = (1 << depth);
   

   input [0:width-1] g_in;
   

   input [0:width-1] p_in;
   

   output [0:width-1] g_out;
   wire [0:width-1]   g_out;
   

   output [0:width-1] p_out;
   wire [0:width-1]   p_out;
   
   genvar 	      level;
   
   wire [0:(depth+1)*ext_width-1] g_int;
   wire [0:(depth+1)*ext_width-1] p_int;
   
   assign g_int[ext_width-width:ext_width-1] = g_in;
   assign p_int[ext_width-width:ext_width-1] = p_in;
   
   generate
      
      if(ext_width > width)
	begin
	   assign g_int[0:ext_width-width-1] = {(ext_width-width){1'b0}};
	   assign p_int[0:ext_width-width-1] = {(ext_width-width){1'b1}};
	end
      
      for(level = 0; level < depth; level = level + 1)
	begin:levels
	   
	   wire [0:ext_width-1] g_in;
	   assign g_in = g_int[level*ext_width:(level+1)*ext_width-1];
	   
	   wire [0:ext_width-1] p_in;
	   assign p_in = p_int[level*ext_width:(level+1)*ext_width-1];
	   
	   wire [0:ext_width-1] g_shifted;
	   assign g_shifted[(1<<level):ext_width-1]
	     = g_in[0:ext_width-(1<<level)-1];
	   if(enable_wraparound)
	     assign g_shifted[0:(1<<level)-1]
	       = g_in[ext_width-(1<<level):ext_width-1];
	   else
	     assign g_shifted[0:(1<<level)-1] = {(1<<level){1'b0}};
	   
	   wire [0:ext_width-1] p_shifted;
	   assign p_shifted[(1<<level):ext_width-1]
	     = p_in[0:ext_width-(1<<level)-1];
	   if(enable_wraparound)
	     assign p_shifted[0:(1<<level)-1]
	       = p_in[ext_width-(1<<level):ext_width-1];
	   else
	     assign p_shifted[0:(1<<level)-1] = {(1<<level){1'b0}};
	   
	   wire [0:ext_width-1] g_out;
	   assign g_out = g_in | p_in & g_shifted;
	   
	   wire [0:ext_width-1] p_out;
	   assign p_out = p_in & p_shifted;
	   
	   assign g_int[(level+1)*ext_width:(level+2)*ext_width-1] = g_out;
	   assign p_int[(level+1)*ext_width:(level+2)*ext_width-1] = p_out;
	   
	end
      
   endgenerate
   
   assign g_out = g_int[(depth+1)*ext_width-width:(depth+1)*ext_width-1];
   assign p_out = p_int[(depth+1)*ext_width-width:(depth+1)*ext_width-1];
   
endmodule
module c_prefix_net
  (g_in, p_in, g_out, p_out);

   
`include "c_functions.v"
   

   parameter width = 16;
   

   parameter enable_wraparound = 0;
   

   localparam depth = clogb(width);
   

   localparam ext_width = (1 << depth);
   

   input [0:width-1] g_in;
   

   input [0:width-1] p_in;
   

   output [0:width-1] g_out;
   wire [0:width-1]   g_out;
   

   output [0:width-1] p_out;
   wire [0:width-1]   p_out;
   
   genvar 	      level;
   
   wire [0:(depth+1)*ext_width-1] g_int;
   wire [0:(depth+1)*ext_width-1] p_int;
   
   assign g_int[ext_width-width:ext_width-1] = g_in;
   assign p_int[ext_width-width:ext_width-1] = p_in;
   
   generate
      
      if(ext_width > width)
	begin
	   assign g_int[0:ext_width-width-1] = {(ext_width-width){1'b0}};
	   assign p_int[0:ext_width-width-1] = {(ext_width-width){1'b1}};
	end
      
      for(level = 0; level < depth; level = level + 1)
	begin:levels
	   
	   wire [0:ext_width-1] g_in;
	   assign g_in = g_int[level*ext_width:(level+1)*ext_width-1];
	   
	   wire [0:ext_width-1] p_in;
	   assign p_in = p_int[level*ext_width:(level+1)*ext_width-1];
	   
	   wire [0:ext_width-1] g_shifted;
	   assign g_shifted[(1<<level):ext_width-1]
	     = g_in[0:ext_width-(1<<level)-1];
	   if(enable_wraparound)
	     assign g_shifted[0:(1<<level)-1]
	       = g_in[ext_width-(1<<level):ext_width-1];
	   else
	     assign g_shifted[0:(1<<level)-1] = {(1<<level){1'b0}};
	   
	   wire [0:ext_width-1] p_shifted;
	   assign p_shifted[(1<<level):ext_width-1]
	     = p_in[0:ext_width-(1<<level)-1];
	   if(enable_wraparound)
	     assign p_shifted[0:(1<<level)-1]
	       = p_in[ext_width-(1<<level):ext_width-1];
	   else
	     assign p_shifted[0:(1<<level)-1] = {(1<<level){1'b0}};
	   
	   wire [0:ext_width-1] g_out;
	   assign g_out = g_in | p_in & g_shifted;
	   
	   wire [0:ext_width-1] p_out;
	   assign p_out = p_in & p_shifted;
	   
	   assign g_int[(level+1)*ext_width:(level+2)*ext_width-1] = g_out;
	   assign p_int[(level+1)*ext_width:(level+2)*ext_width-1] = p_out;
	   
	end
      
   endgenerate
   
   assign g_out = g_int[(depth+1)*ext_width-width:(depth+1)*ext_width-1];
   assign p_out = p_int[(depth+1)*ext_width-width:(depth+1)*ext_width-1];
   
endmodule