data/full_repos/permissive/447976230/fpga/usrp2/fifo/fifo_pacer.v
1: b"%Error: data/full_repos/permissive/447976230/fpga/usrp2/fifo/fifo_pacer.v:31: Cannot find file containing module: 'cic_strober'\n   cic_strober strober (.clock(clk), .reset(reset), .enable(enable),\n   ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp2/fifo,data/full_repos/permissive/447976230/cic_strober\n             data/full_repos/permissive/447976230/fpga/usrp2/fifo,data/full_repos/permissive/447976230/cic_strober.v\n             data/full_repos/permissive/447976230/fpga/usrp2/fifo,data/full_repos/permissive/447976230/cic_strober.sv\n             cic_strober\n             cic_strober.v\n             cic_strober.sv\n             obj_dir/cic_strober\n             obj_dir/cic_strober.v\n             obj_dir/cic_strober.sv\n%Error: Exiting due to 1 error(s)\n"
module fifo_pacer
  (input clk,
   input reset,
   input [7:0] rate,
   input enable,
   input src1_rdy_i, output dst1_rdy_o,
   output src2_rdy_o, input dst2_rdy_i,
   output underrun, overrun);

   wire   strobe;
   
   cic_strober strober (.clock(clk), .reset(reset), .enable(enable),
			.rate(rate), .strobe_fast(1), .strobe_slow(strobe));

   wire   all_ready = src1_rdy_i & dst2_rdy_i;
   assign dst1_rdy_o = all_ready & strobe;
   assign src2_rdy_o = dst1_rdy_o;

   assign underrun = strobe & ~src1_rdy_i;
   assign overrun = strobe & ~dst2_rdy_i;
   
endmodule
module fifo_pacer
  (input clk,
   input reset,
   input [7:0] rate,
   input enable,
   input src1_rdy_i, output dst1_rdy_o,
   output src2_rdy_o, input dst2_rdy_i,
   output underrun, overrun);


   wire   strobe;
   
   cic_strober strober (.clock(clk), .reset(reset), .enable(enable),
			.rate(rate), .strobe_fast(1), .strobe_slow(strobe));

   wire   all_ready = src1_rdy_i & dst2_rdy_i;
   assign dst1_rdy_o = all_ready & strobe;
   assign src2_rdy_o = dst1_rdy_o;

   assign underrun = strobe & ~src1_rdy_i;
   assign overrun = strobe & ~dst2_rdy_i;
   
endmodule