data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/variable_latency_interconnect/addr_decoder.sv
data/verilator_xmls/3163ae7e-0aca-43f0-827a-207a5be8b9c2.xml
module addr_decoder #(
  parameter int unsigned NumOut    = 32,
  parameter int unsigned DataWidth = 32,
  parameter bit AxiVldRdy          = 1'b1,

  localparam int unsigned NumOutLog = NumOut == 1 ? 1 : $clog2(NumOut)
) (

  input  logic                             valid_i,
  input  logic [NumOutLog-1:0]             addr_i,
  input  logic [DataWidth-1:0]             data_i,
  output logic                             ready_o,

  output logic [NumOut-1:0]                valid_o,
  input  logic [NumOut-1:0]                ready_i,
  output logic [NumOut-1:0][DataWidth-1:0] data_o
);



  if (NumOut == 1) begin: gen_one_output
    assign valid_o[0] = valid_i   ;
    assign ready_o    = ready_i[0];
    assign data_o[0]  = data_i    ;
  end



  else begin: gen_several_outputs

    always_comb begin : p_addr_decoder
      valid_o         = '0     ;
      valid_o[addr_i] = valid_i;
    end


    assign data_o = {NumOut{data_i}};

    if (AxiVldRdy)

      assign ready_o = ready_i[addr_i];
    else

      assign ready_o = |ready_i;
  end



  if (NumOut <= 0)
    $fatal(1, "[addr_decoder] NumOut must be greater than 0.");

endmodule
module addr_decoder #(
  parameter int unsigned NumOut    = 32,
  parameter int unsigned DataWidth = 32,
  parameter bit AxiVldRdy          = 1'b1,

  localparam int unsigned NumOutLog = NumOut == 1 ? 1 : $clog2(NumOut)
) (

  input  logic                             valid_i,
  input  logic [NumOutLog-1:0]             addr_i,
  input  logic [DataWidth-1:0]             data_i,
  output logic                             ready_o,

  output logic [NumOut-1:0]                valid_o,
  input  logic [NumOut-1:0]                ready_i,
  output logic [NumOut-1:0][DataWidth-1:0] data_o
);




  if (NumOut == 1) begin: gen_one_output
    assign valid_o[0] = valid_i   ;
    assign ready_o    = ready_i[0];
    assign data_o[0]  = data_i    ;
  end



  else begin: gen_several_outputs

    always_comb begin : p_addr_decoder
      valid_o         = '0     ;
      valid_o[addr_i] = valid_i;
    end


    assign data_o = {NumOut{data_i}};

    if (AxiVldRdy)

      assign ready_o = ready_i[addr_i];
    else

      assign ready_o = |ready_i;
  end



  if (NumOut <= 0)
    $fatal(1, "[addr_decoder] NumOut must be greater than 0.");

endmodule