data/full_repos/permissive/472688398/verilog/rtl/user_proj_example.v
1: b'%Error: data/full_repos/permissive/472688398/verilog/rtl/user_proj_example.v:17: Cannot find include file: i2c_ctrl2202.v\n`include "i2c_ctrl2202.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/472688398/verilog/rtl,data/full_repos/permissive/472688398/i2c_ctrl2202.v\n             data/full_repos/permissive/472688398/verilog/rtl,data/full_repos/permissive/472688398/i2c_ctrl2202.v.v\n             data/full_repos/permissive/472688398/verilog/rtl,data/full_repos/permissive/472688398/i2c_ctrl2202.v.sv\n             i2c_ctrl2202.v\n             i2c_ctrl2202.v.v\n             i2c_ctrl2202.v.sv\n             obj_dir/i2c_ctrl2202.v\n             obj_dir/i2c_ctrl2202.v.v\n             obj_dir/i2c_ctrl2202.v.sv\n%Error: data/full_repos/permissive/472688398/verilog/rtl/user_proj_example.v:65: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472688398/verilog/rtl/user_proj_example.v:66: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472688398/verilog/rtl/user_proj_example.v:67: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472688398/verilog/rtl/user_proj_example.v:75: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    wire [`MPRJ_IO_PADS-1:0] io_in;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472688398/verilog/rtl/user_proj_example.v:76: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    wire [`MPRJ_IO_PADS-1:0] io_out;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472688398/verilog/rtl/user_proj_example.v:77: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    wire [`MPRJ_IO_PADS-1:0] io_oeb;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472688398/verilog/rtl/user_proj_example.v:95: Define or directive not defined: \'`MPRJ_IO_PADS\'\n    assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};\n                      ^~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n'
module user_proj_example #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,


    output [2:0] irq
);
    wire clk;
    wire rst;

    wire [`MPRJ_IO_PADS-1:0] io_in;
    wire [`MPRJ_IO_PADS-1:0] io_out;
    wire [`MPRJ_IO_PADS-1:0] io_oeb;

    wire [31:0] rdata; 
    wire [31:0] wdata;
    wire [BITS-1:0] count;

    wire valid;
    wire [3:0] wstrb;
    wire [31:0] la_write;


    assign valid = wbs_cyc_i && wbs_stb_i; 
    assign wstrb = wbs_sel_i & {4{wbs_we_i}};
    assign wbs_dat_o = rdata;
    assign wdata = wbs_dat_i;


    assign io_out = count;
    assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};


    assign irq = 3'b000;


    assign la_data_out = {{(127-BITS){1'b0}}, count};

    assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};

    assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
    assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;


		i2c_ctrl2202 CONTROLLER(
			.i_start(wstrb),
			.i_cclk(clk),
			.i_read(~la_write),
			.i_stop(rst),
			.i_sda(la_data_in),
			.i_address(wbs_dat_i[0:6]),
			.i_txdata(wbs_dat_i),
			.i_rxdata(rdata),
			.o_scl(la_data_out[8]),
			.o_busy(wbs_ack_o),
			.o_sda(la_data_out[0:7])
		);



endmodule
module user_proj_example #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,


    output [2:0] irq
);

    wire clk;
    wire rst;

    wire [`MPRJ_IO_PADS-1:0] io_in;
    wire [`MPRJ_IO_PADS-1:0] io_out;
    wire [`MPRJ_IO_PADS-1:0] io_oeb;

    wire [31:0] rdata; 
    wire [31:0] wdata;
    wire [BITS-1:0] count;

    wire valid;
    wire [3:0] wstrb;
    wire [31:0] la_write;


    assign valid = wbs_cyc_i && wbs_stb_i; 
    assign wstrb = wbs_sel_i & {4{wbs_we_i}};
    assign wbs_dat_o = rdata;
    assign wdata = wbs_dat_i;


    assign io_out = count;
    assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};


    assign irq = 3'b000;


    assign la_data_out = {{(127-BITS){1'b0}}, count};

    assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};

    assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
    assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;


		i2c_ctrl2202 CONTROLLER(
			.i_start(wstrb),
			.i_cclk(clk),
			.i_read(~la_write),
			.i_stop(rst),
			.i_sda(la_data_in),
			.i_address(wbs_dat_i[0:6]),
			.i_txdata(wbs_dat_i),
			.i_rxdata(rdata),
			.o_scl(la_data_out[8]),
			.o_busy(wbs_ack_o),
			.o_sda(la_data_out[0:7])
		);



endmodule