data/full_repos/permissive/447555422/src/clock_divider.v
data/verilator_xmls/74135644-435c-469f-83c7-cc3c9db83c77.xml
module clock_divider
    #(
        parameter INPUT_FREQUENCY = 100000000,
        parameter OUTPUT_FREQUENCY = 1
      )
    (
    input i_clk,
    output o_clk
    );
        
    localparam CLOCK_CYCLES = INPUT_FREQUENCY / (2*OUTPUT_FREQUENCY) - 1;
    integer counter_value = 0;
    
    reg r_divided_clk = 0;
    
    always @(posedge i_clk) begin
        if(counter_value <  CLOCK_CYCLES)
            counter_value <= counter_value + 1;
        else begin
            counter_value <= 0;
            r_divided_clk <= ~r_divided_clk;
        end
    end   
    
    assign o_clk = r_divided_clk;
 
endmodule
module clock_divider
    #(
        parameter INPUT_FREQUENCY = 100000000,
        parameter OUTPUT_FREQUENCY = 1
      )
    (
    input i_clk,
    output o_clk
    );

        
    localparam CLOCK_CYCLES = INPUT_FREQUENCY / (2*OUTPUT_FREQUENCY) - 1;
    integer counter_value = 0;
    
    reg r_divided_clk = 0;
    
    always @(posedge i_clk) begin
        if(counter_value <  CLOCK_CYCLES)
            counter_value <= counter_value + 1;
        else begin
            counter_value <= 0;
            r_divided_clk <= ~r_divided_clk;
        end
    end   
    
    assign o_clk = r_divided_clk;
 
endmodule