data/full_repos/permissive/423412549/src/rtl/rand.v
1: b'%Error: data/full_repos/permissive/423412549/src/rtl/rand.v:9: Cannot find include file: ../header/define.v\n`include "../header/define.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423412549/src/rtl,data/full_repos/permissive/423412549/../header/define.v\n             data/full_repos/permissive/423412549/src/rtl,data/full_repos/permissive/423412549/../header/define.v.v\n             data/full_repos/permissive/423412549/src/rtl,data/full_repos/permissive/423412549/../header/define.v.sv\n             ../header/define.v\n             ../header/define.v.v\n             ../header/define.v.sv\n             obj_dir/../header/define.v\n             obj_dir/../header/define.v.v\n             obj_dir/../header/define.v.sv\n%Error: data/full_repos/permissive/423412549/src/rtl/rand.v:10: syntax error, unexpected rand, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule rand (\n       ^~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/rand.v:12: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire rst,\n    ^~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/rand.v:14: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg  [`RAND_WIDTH-1:0] data_o\n    ^~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/rand.v:14: Define or directive not defined: \'`RAND_WIDTH\'\n    output reg  [`RAND_WIDTH-1:0] data_o\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/rand.v:15: syntax error, unexpected \')\', expecting \',\' or \';\'\n);\n^\n%Error: data/full_repos/permissive/423412549/src/rtl/rand.v:17: Define or directive not defined: \'`RAND_WIDTH\'\n    wire [`RAND_WIDTH-1:0] seed;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/rand.v:18: syntax error, unexpected assign\n    assign seed = `RAND_SEED;\n    ^~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/rand.v:18: Define or directive not defined: \'`RAND_SEED\'\n    assign seed = `RAND_SEED;\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/rand.v:22: Define or directive not defined: \'`RAND_WIDTH\'\n        for(i=0; i<`RAND_WIDTH; i=i+1) begin:RAND_LOOP\n                   ^~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/rand.v:29: Define or directive not defined: \'`RAND_WIDTH\'\n                            data_o[i] <= data_o[`RAND_WIDTH-1];\n                                                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/423412549/src/rtl/rand.v:32: Define or directive not defined: \'`RAND_WIDTH\'\n                            data_o[i] <= data_o[i] ^ data_o[`RAND_WIDTH-1];\n                                                            ^~~~~~~~~~~\n%Error: Exiting due to 12 error(s)\n'
module rand (
    input  wire clk_vga,
    input  wire rst,
    
    output reg  [`RAND_WIDTH-1:0] data_o
);

    wire [`RAND_WIDTH-1:0] seed;
    assign seed = `RAND_SEED;
    
    genvar i;
    generate
        for(i=0; i<`RAND_WIDTH; i=i+1) begin:RAND_LOOP
            always @(posedge clk_vga or posedge rst) begin
                if(rst) begin
                    data_o[i] <= seed[i];
                end else begin
                    case(i)
                        0:begin
                            data_o[i] <= data_o[`RAND_WIDTH-1];
                        end
                        1, 2, 3, 5:begin
                            data_o[i] <= data_o[i] ^ data_o[`RAND_WIDTH-1];
                        end
                        default: begin
                            data_o[i] <= data_o[i-1];
                        end
                    endcase
                end
            end
        end
    endgenerate

endmodule
module rand (
    input  wire clk_vga,
    input  wire rst,
    
    output reg  [`RAND_WIDTH-1:0] data_o
);


    wire [`RAND_WIDTH-1:0] seed;
    assign seed = `RAND_SEED;
    
    genvar i;
    generate
        for(i=0; i<`RAND_WIDTH; i=i+1) begin:RAND_LOOP
            always @(posedge clk_vga or posedge rst) begin
                if(rst) begin
                    data_o[i] <= seed[i];
                end else begin
                    case(i)
                        0:begin
                            data_o[i] <= data_o[`RAND_WIDTH-1];
                        end
                        1, 2, 3, 5:begin
                            data_o[i] <= data_o[i] ^ data_o[`RAND_WIDTH-1];
                        end
                        default: begin
                            data_o[i] <= data_o[i-1];
                        end
                    endcase
                end
            end
        end
    endgenerate

endmodule