data/full_repos/permissive/526589127/verilog/rtl/b_box/FFPMAC.v
1: b'%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/FFPMAC.v:8: Cannot find include file: ./const/parameters.v\n `include "./const/parameters.v" \n          ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters.v\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters.v.v\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/./const/parameters.v.sv\n             ./const/parameters.v\n             ./const/parameters.v.v\n             ./const/parameters.v.sv\n             obj_dir/./const/parameters.v\n             obj_dir/./const/parameters.v.v\n             obj_dir/./const/parameters.v.sv\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/FFPMAC.v:218: Cannot find include file: ./const/parameters.v\n `include "./const/parameters.v" \n          ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/FFPMAC.v:265: Cannot find include file: ./const/parameters.v\n `include "./const/parameters.v" \n          ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/FFPMAC.v:302: Cannot find include file: ./const/parameters.v\n `include "./const/parameters.v" \n          ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/FFPMAC.v:330: Cannot find include file: ./const/parameters.v\n  `include "./const/parameters.v" \n           ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/FFPMAC.v:364: Cannot find include file: ./const/parameters.v\n  `include "./const/parameters.v" \n           ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/FFPMAC.v:512: Cannot find include file: ./const/parameters.v\n  `include "./const/parameters.v" \n           ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/FFPMAC.v:912: Cannot find include file: ./const/parameters.v\n  `include "./const/parameters.v" \n           ^~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n'
module significandMultiplier1 #(parameter WIDTH = 8)(
input [WIDTH-1:0] mx,
input [WIDTH-1:0] my,
output [(WIDTH*2)+1:0] sum,
output [(WIDTH*2)+1:0] carry);

parameter group_cnt=(WIDTH>>1)+1;

wire [group_cnt - 1:0] s;
wire [group_cnt - 1:0] d;
wire [group_cnt - 1:0] n;

wire [WIDTH:0] epp2d[0:group_cnt - 1];
wire [9:0] fpp0;
wire [9:0] fpp1;
wire [9:0] fpp2;
wire [9:0] fpp3;
wire [9:0] fpp4;





                        booth_encoder b_e0(.x({mx[1], mx[0], 1'b0}), .single(s[0]), .double(d[0]), .neg(n[0]));
                        booth_encoder b_e1(.x({mx[3], mx[2], mx[1]}), .single(s[1]), .double(d[1]), .neg(n[1]));
                        booth_encoder b_e2(.x({mx[5], mx[4], mx[3]}), .single(s[2]), .double(d[2]), .neg(n[2]));
                        booth_encoder b_e3(.x({mx[7], mx[6], mx[5]}), .single(s[3]), .double(d[3]), .neg(n[3]));
                        booth_encoder b_e4(.x({1'b0, 1'b0, mx[WIDTH - 1]}), .single(s[4]), .double(d[4]), .neg(n[4]));



genvar i, j;

generate
    for (j = 0; j < group_cnt; j = j + 1) begin: b_selector
                        booth_selector bs(.double(d[j]), .shifted(1'b0), .single(s[j]), .y(my[0]), .neg(n[j]), .p(epp2d[j][0]));
                        booth_selector bs0(.double(d[j]), .shifted(my[0]), .single(s[j]), .y(my[1]), .neg(n[j]), .p(epp2d[j][1]));
                        booth_selector bs1(.double(d[j]), .shifted(my[1]), .single(s[j]), .y(my[2]), .neg(n[j]), .p(epp2d[j][2]));
                        booth_selector bs2(.double(d[j]), .shifted(my[2]), .single(s[j]), .y(my[3]), .neg(n[j]), .p(epp2d[j][3]));
                        booth_selector bs3(.double(d[j]), .shifted(my[3]), .single(s[j]), .y(my[4]), .neg(n[j]), .p(epp2d[j][4]));
                        booth_selector bs4(.double(d[j]), .shifted(my[4]), .single(s[j]), .y(my[5]), .neg(n[j]), .p(epp2d[j][5]));
                        booth_selector bs5(.double(d[j]), .shifted(my[5]), .single(s[j]), .y(my[6]), .neg(n[j]), .p(epp2d[j][6]));
                        booth_selector bs6(.double(d[j]), .shifted(my[6]), .single(s[j]), .y(my[7]), .neg(n[j]), .p(epp2d[j][7]));
                        booth_selector bs7(.double(d[j]), .shifted(my[7]), .single(s[j]), .y(1'b0), .neg(n[j]), .p(epp2d[j][8]));

end
endgenerate

assign fpp0 = {~n[0] , epp2d[0]};
assign fpp1 = {~n[1] , epp2d[1]};
assign fpp2 = {~n[2] , epp2d[2]};
assign fpp3 = {~n[3] , epp2d[3]};
assign fpp4 = {~n[4] , epp2d[4]};


wire [17:0]cv= {9'b010101011,n[4],1'b0,n[3],1'b0,n[2],1'b0,n[1],1'b0,n[0]};



wire has00;
wire hac00;
wire has01;
wire hac01;

wire ahas00;
wire ahac00;
wire ahas01;
wire ahac01;

wire has10;
wire hac10;
wire has11;
wire hac11;

wire ahas10;
wire ahac10;
wire ahas11;
wire ahac11;

wire [7:0] fas0;
wire [7:0] fac0;

wire [5:0] fas1;
wire [5:0] fac1;

wire [17:0] st00;
wire [11:0] st01;
wire [13:0] st02;
wire [9:0] st03;


HALF_ADDER ha0s0210(.a(cv[0]), .b(fpp0[0]) , .sum(has00), .cout(hac00));
HALF_ADDER ha0s0311(.a(cv[1]), .b(fpp0[1]) , .sum(has01), .cout(hac01));

HALF_ADDER aha0s0210(.a(cv[10]), .b(fpp1[8]) , .sum(ahas00), .cout(ahac00));
HALF_ADDER aha0s0311(.a(cv[11]), .b(fpp1[9]) , .sum(ahas01), .cout(ahac01));

generate
        for (i = 0; i < 8; i = i + 1) begin:    for_s0
                FULL_ADDER fa000(.a(cv[i + 2]), .b(fpp0[i + 2]), .cin(fpp1[i]), .sum(fas0[i]), .cout(fac0[i]));
        end
endgenerate

HALF_ADDER ha0s0220(.a(fpp2[2]), .b(fpp3[0]) , .sum(has10), .cout(hac10));
HALF_ADDER ha0s0321(.a(fpp2[3]), .b(fpp3[1]) , .sum(has11), .cout(hac11));

HALF_ADDER aha0s0220(.a(fpp3[8]), .b(fpp4[6]) , .sum(ahas10), .cout(ahac10));
HALF_ADDER aha0s0321(.a(fpp3[9]), .b(fpp4[7]) , .sum(ahas11), .cout(ahac11));

generate
        for (i = 0; i < 6; i = i + 1) begin:    for_s1
                FULL_ADDER fa001(.a(fpp2[i + 4]), .b(fpp3[i + 2]), .cin(fpp4[i]), .sum(fas1[i]), .cout(fac1[i]));
        end
endgenerate

assign st00 = {cv[17:12], ahas01,ahas00,fas0, has01, has00};
assign st01 = {ahac01, ahac00,fac0, hac01, hac00};
assign st02 = {fpp4[9:8],ahas11, ahas10, fas1, has11, has10, fpp2[1:0]};
assign st03 = {ahac11, ahac10, fac1, hac11, hac10};

/
module booth_encoder (x, single, double, neg);

input [2:0]x;

output single;

output  double;

output neg;

wire w0;

wire w1;

assign single = x[0] ^ x[1];

assign neg = x[2];

assign  w0 = ~(x[1] ^ x[2]);

assign  w1 = (x[0] ^ x[1]);

assign double =~(w0|w1);

endmodule
module significandMultiplier1 #(parameter WIDTH = 8)(
input [WIDTH-1:0] mx,
input [WIDTH-1:0] my,
output [(WIDTH*2)+1:0] sum,
output [(WIDTH*2)+1:0] carry);


parameter group_cnt=(WIDTH>>1)+1;

wire [group_cnt - 1:0] s;
wire [group_cnt - 1:0] d;
wire [group_cnt - 1:0] n;

wire [WIDTH:0] epp2d[0:group_cnt - 1];
wire [9:0] fpp0;
wire [9:0] fpp1;
wire [9:0] fpp2;
wire [9:0] fpp3;
wire [9:0] fpp4;





                        booth_encoder b_e0(.x({mx[1], mx[0], 1'b0}), .single(s[0]), .double(d[0]), .neg(n[0]));
                        booth_encoder b_e1(.x({mx[3], mx[2], mx[1]}), .single(s[1]), .double(d[1]), .neg(n[1]));
                        booth_encoder b_e2(.x({mx[5], mx[4], mx[3]}), .single(s[2]), .double(d[2]), .neg(n[2]));
                        booth_encoder b_e3(.x({mx[7], mx[6], mx[5]}), .single(s[3]), .double(d[3]), .neg(n[3]));
                        booth_encoder b_e4(.x({1'b0, 1'b0, mx[WIDTH - 1]}), .single(s[4]), .double(d[4]), .neg(n[4]));



genvar i, j;

generate
    for (j = 0; j < group_cnt; j = j + 1) begin: b_selector
                        booth_selector bs(.double(d[j]), .shifted(1'b0), .single(s[j]), .y(my[0]), .neg(n[j]), .p(epp2d[j][0]));
                        booth_selector bs0(.double(d[j]), .shifted(my[0]), .single(s[j]), .y(my[1]), .neg(n[j]), .p(epp2d[j][1]));
                        booth_selector bs1(.double(d[j]), .shifted(my[1]), .single(s[j]), .y(my[2]), .neg(n[j]), .p(epp2d[j][2]));
                        booth_selector bs2(.double(d[j]), .shifted(my[2]), .single(s[j]), .y(my[3]), .neg(n[j]), .p(epp2d[j][3]));
                        booth_selector bs3(.double(d[j]), .shifted(my[3]), .single(s[j]), .y(my[4]), .neg(n[j]), .p(epp2d[j][4]));
                        booth_selector bs4(.double(d[j]), .shifted(my[4]), .single(s[j]), .y(my[5]), .neg(n[j]), .p(epp2d[j][5]));
                        booth_selector bs5(.double(d[j]), .shifted(my[5]), .single(s[j]), .y(my[6]), .neg(n[j]), .p(epp2d[j][6]));
                        booth_selector bs6(.double(d[j]), .shifted(my[6]), .single(s[j]), .y(my[7]), .neg(n[j]), .p(epp2d[j][7]));
                        booth_selector bs7(.double(d[j]), .shifted(my[7]), .single(s[j]), .y(1'b0), .neg(n[j]), .p(epp2d[j][8]));

end
endgenerate

assign fpp0 = {~n[0] , epp2d[0]};
assign fpp1 = {~n[1] , epp2d[1]};
assign fpp2 = {~n[2] , epp2d[2]};
assign fpp3 = {~n[3] , epp2d[3]};
assign fpp4 = {~n[4] , epp2d[4]};


wire [17:0]cv= {9'b010101011,n[4],1'b0,n[3],1'b0,n[2],1'b0,n[1],1'b0,n[0]};



wire has00;
wire hac00;
wire has01;
wire hac01;

wire ahas00;
wire ahac00;
wire ahas01;
wire ahac01;

wire has10;
wire hac10;
wire has11;
wire hac11;

wire ahas10;
wire ahac10;
wire ahas11;
wire ahac11;

wire [7:0] fas0;
wire [7:0] fac0;

wire [5:0] fas1;
wire [5:0] fac1;

wire [17:0] st00;
wire [11:0] st01;
wire [13:0] st02;
wire [9:0] st03;


HALF_ADDER ha0s0210(.a(cv[0]), .b(fpp0[0]) , .sum(has00), .cout(hac00));
HALF_ADDER ha0s0311(.a(cv[1]), .b(fpp0[1]) , .sum(has01), .cout(hac01));

HALF_ADDER aha0s0210(.a(cv[10]), .b(fpp1[8]) , .sum(ahas00), .cout(ahac00));
HALF_ADDER aha0s0311(.a(cv[11]), .b(fpp1[9]) , .sum(ahas01), .cout(ahac01));

generate
        for (i = 0; i < 8; i = i + 1) begin:    for_s0
                FULL_ADDER fa000(.a(cv[i + 2]), .b(fpp0[i + 2]), .cin(fpp1[i]), .sum(fas0[i]), .cout(fac0[i]));
        end
endgenerate

HALF_ADDER ha0s0220(.a(fpp2[2]), .b(fpp3[0]) , .sum(has10), .cout(hac10));
HALF_ADDER ha0s0321(.a(fpp2[3]), .b(fpp3[1]) , .sum(has11), .cout(hac11));

HALF_ADDER aha0s0220(.a(fpp3[8]), .b(fpp4[6]) , .sum(ahas10), .cout(ahac10));
HALF_ADDER aha0s0321(.a(fpp3[9]), .b(fpp4[7]) , .sum(ahas11), .cout(ahac11));

generate
        for (i = 0; i < 6; i = i + 1) begin:    for_s1
                FULL_ADDER fa001(.a(fpp2[i + 4]), .b(fpp3[i + 2]), .cin(fpp4[i]), .sum(fas1[i]), .cout(fac1[i]));
        end
endgenerate

assign st00 = {cv[17:12], ahas01,ahas00,fas0, has01, has00};
assign st01 = {ahac01, ahac00,fac0, hac01, hac00};
assign st02 = {fpp4[9:8],ahas11, ahas10, fas1, has11, has10, fpp2[1:0]};
assign st03 = {ahac11, ahac10, fac1, hac11, hac10};

/
module booth_encoder (x, single, double, neg);

input [2:0]x;

output single;

output  double;

output neg;

wire w0;

wire w1;

assign single = x[0] ^ x[1];

assign neg = x[2];

assign  w0 = ~(x[1] ^ x[2]);

assign  w1 = (x[0] ^ x[1]);

assign double =~(w0|w1);

endmodule