data/full_repos/permissive/431682734/LabL/cpu.v
1: b'%Error: data/full_repos/permissive/431682734/LabL/cpu.v:25: syntax error, unexpected final, expecting IDENTIFIER\n    yMux #(SIZE) final(z, zLo, zHi, c[1]);\n                 ^~~~~\n%Error: Exiting due to 1 error(s)\n'
module yAdder(z, cout, a, b, cin);

    output [31:0] z;
    output cout;


    input [31:0] a, b;
    input cin;


    wire[31:0] in, out;


    yAdder1 mine[31:0](z, out, a, b, in);
    
    assign in[0] = cin;
    assign in[31:1] = out[30:0];
endmodule
module yAdder(z, cout, a, b, cin);


    output [31:0] z;
    output cout;


    input [31:0] a, b;
    input cin;


    wire[31:0] in, out;


    yAdder1 mine[31:0](z, out, a, b, in);
    
    assign in[0] = cin;
    assign in[31:1] = out[30:0];
endmodule