data/full_repos/permissive/427221126/src/FixedPointArith.v
1: b'%Warning-WIDTH: data/full_repos/permissive/427221126/src/FixedPointArith.v:63: Operator ADD expects 15 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                             : ... In instance FRound\n      din_pre_add <= DIN[EXTRA_FRAC+OUTWIDTH-2:EXTRA_FRAC] + DIN[EXTRA_FRAC-1];\n                                                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/FixedPointArith.v:92: Operator EQ expects 20 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n                                                                             : ... In instance FRound\n              if (din_trunc == $signed({signbit, {(OUTWIDTH-1){1\'b1}}})) begin  \n                            ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/FixedPointArith.v:85: Operator GTS expects 20 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n                                                                             : ... In instance FRound\n          if (din_trunc > $signed({signbit, {(OUTWIDTH-1){1\'b1}}})) begin  \n                        ^\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/FixedPointArith.v:119: Operator LTS expects 20 bits on the RHS, but RHS\'s SIGNED generates 16 bits.\n                                                                              : ... In instance FRound\n          if (din_trunc < $signed({1\'b1, {(OUTWIDTH-1){1\'b0}}})) begin  \n                        ^\n%Error: Exiting due to 4 warning(s)\n'
module FRound
  #(
    parameter INWIDTH = 33,
              IN_FRAC = 26,
              OUTWIDTH = 16,
              OUT_FRAC = 13
  )
  (
    input                        CLK  ,
    input                        RESET,
    input                        EN   ,
    input  signed [INWIDTH-1:0]  DIN  ,
    output signed [OUTWIDTH-1:0] DOUT ,
    output                       SATUR,
    output                       OVFL ,
    output                       UDFL
  );
  localparam EXTRA_FRAC = IN_FRAC - OUT_FRAC;
  
  reg  signed [INWIDTH-1:0]            din_d;
  reg         [OUTWIDTH-2:0]           din_pre_add;
  reg  signed [OUTWIDTH-1:0]           dout_reg;
  wire signed [INWIDTH-EXTRA_FRAC-1:0] din_trunc   = $signed(din_d[INWIDTH-1:EXTRA_FRAC]);
  wire        [EXTRA_FRAC-1:0]         din_extra   = din_d[EXTRA_FRAC-1:0];
  
  reg  satu_reg, ovfl_reg, udfl_reg;

  wire carryin     = din_d[EXTRA_FRAC-1];
  wire signbit     = din_d[INWIDTH-1];
  wire extra_has_1 = (|din_extra);

  always @(posedge CLK) begin
    if (RESET) begin
      din_d <= 0;
      din_pre_add <= 0;
    end
    else if (EN) begin
      din_d <= DIN;
      din_pre_add <= DIN[EXTRA_FRAC+OUTWIDTH-2:EXTRA_FRAC] + DIN[EXTRA_FRAC-1];
    end
  end

  always @(posedge CLK) begin
    if (RESET) begin
      dout_reg <= 0;
      satu_reg <= 0;
      ovfl_reg <= 0;
      udfl_reg <= 0;
    end
    else if (EN) begin
      if (signbit == 0) begin
        if ((din_trunc == 0)
          && (extra_has_1)) begin
          udfl_reg <= 1'b1;
          ovfl_reg <= 1'b0;
          satu_reg <= 1'b0;
          dout_reg <= 0;
        end 
        else begin
          udfl_reg <= 1'b0;
          if (din_trunc > $signed({signbit, {(OUTWIDTH-1){1'b1}}})) begin
            satu_reg <= 1'b1;
            ovfl_reg <= 1'b1;
            dout_reg <= $signed({signbit, {(OUTWIDTH-1){1'b1}}});
          end 
          else begin
            if (carryin) begin
              if (din_trunc == $signed({signbit, {(OUTWIDTH-1){1'b1}}})) begin
                satu_reg <= 1'b1;
                ovfl_reg <= 1'b1;
                dout_reg <= $signed({signbit, {(OUTWIDTH-1){1'b1}}});
              end else begin
                satu_reg <= 1'b0;
                ovfl_reg <= 1'b0;
                dout_reg <= $signed({signbit, din_pre_add});
              end
            end 
            else begin
              ovfl_reg <= 1'b0;
              satu_reg <= 1'b0;
              dout_reg <= $signed({signbit, din_pre_add});
            end
          end
        end
      end 
      else begin
        ovfl_reg <= 1'b0;
        if ( (din_trunc == $signed({(INWIDTH-EXTRA_FRAC){1'b1}})) && ( extra_has_1 ) ) begin
          udfl_reg <= 1'b1;
          satu_reg <= 1'b0;
          dout_reg <= 0;
        end 
        else begin
          udfl_reg <= 1'b0;
          if (din_trunc < $signed({1'b1, {(OUTWIDTH-1){1'b0}}})) begin
            satu_reg <= 1'b1;
            dout_reg <= $signed({1'b1, {(OUTWIDTH-1){1'b0}}});
          end 
          else begin
            satu_reg <= 1'b0;
            dout_reg <= $signed({signbit, din_pre_add});
          end 
        end
      end
    end
  end

  assign DOUT = dout_reg;
  assign OVFL = ovfl_reg;
  assign UDFL = udfl_reg;
  assign SATUR = satu_reg;
endmodule
module FRound
  #(
    parameter INWIDTH = 33,
              IN_FRAC = 26,
              OUTWIDTH = 16,
              OUT_FRAC = 13
  )
  (
    input                        CLK  ,
    input                        RESET,
    input                        EN   ,
    input  signed [INWIDTH-1:0]  DIN  ,
    output signed [OUTWIDTH-1:0] DOUT ,
    output                       SATUR,
    output                       OVFL ,
    output                       UDFL
  );

  localparam EXTRA_FRAC = IN_FRAC - OUT_FRAC;
  
  reg  signed [INWIDTH-1:0]            din_d;
  reg         [OUTWIDTH-2:0]           din_pre_add;
  reg  signed [OUTWIDTH-1:0]           dout_reg;
  wire signed [INWIDTH-EXTRA_FRAC-1:0] din_trunc   = $signed(din_d[INWIDTH-1:EXTRA_FRAC]);
  wire        [EXTRA_FRAC-1:0]         din_extra   = din_d[EXTRA_FRAC-1:0];
  
  reg  satu_reg, ovfl_reg, udfl_reg;

  wire carryin     = din_d[EXTRA_FRAC-1];
  wire signbit     = din_d[INWIDTH-1];
  wire extra_has_1 = (|din_extra);

  always @(posedge CLK) begin
    if (RESET) begin
      din_d <= 0;
      din_pre_add <= 0;
    end
    else if (EN) begin
      din_d <= DIN;
      din_pre_add <= DIN[EXTRA_FRAC+OUTWIDTH-2:EXTRA_FRAC] + DIN[EXTRA_FRAC-1];
    end
  end

  always @(posedge CLK) begin
    if (RESET) begin
      dout_reg <= 0;
      satu_reg <= 0;
      ovfl_reg <= 0;
      udfl_reg <= 0;
    end
    else if (EN) begin
      if (signbit == 0) begin
        if ((din_trunc == 0)
          && (extra_has_1)) begin
          udfl_reg <= 1'b1;
          ovfl_reg <= 1'b0;
          satu_reg <= 1'b0;
          dout_reg <= 0;
        end 
        else begin
          udfl_reg <= 1'b0;
          if (din_trunc > $signed({signbit, {(OUTWIDTH-1){1'b1}}})) begin
            satu_reg <= 1'b1;
            ovfl_reg <= 1'b1;
            dout_reg <= $signed({signbit, {(OUTWIDTH-1){1'b1}}});
          end 
          else begin
            if (carryin) begin
              if (din_trunc == $signed({signbit, {(OUTWIDTH-1){1'b1}}})) begin
                satu_reg <= 1'b1;
                ovfl_reg <= 1'b1;
                dout_reg <= $signed({signbit, {(OUTWIDTH-1){1'b1}}});
              end else begin
                satu_reg <= 1'b0;
                ovfl_reg <= 1'b0;
                dout_reg <= $signed({signbit, din_pre_add});
              end
            end 
            else begin
              ovfl_reg <= 1'b0;
              satu_reg <= 1'b0;
              dout_reg <= $signed({signbit, din_pre_add});
            end
          end
        end
      end 
      else begin
        ovfl_reg <= 1'b0;
        if ( (din_trunc == $signed({(INWIDTH-EXTRA_FRAC){1'b1}})) && ( extra_has_1 ) ) begin
          udfl_reg <= 1'b1;
          satu_reg <= 1'b0;
          dout_reg <= 0;
        end 
        else begin
          udfl_reg <= 1'b0;
          if (din_trunc < $signed({1'b1, {(OUTWIDTH-1){1'b0}}})) begin
            satu_reg <= 1'b1;
            dout_reg <= $signed({1'b1, {(OUTWIDTH-1){1'b0}}});
          end 
          else begin
            satu_reg <= 1'b0;
            dout_reg <= $signed({signbit, din_pre_add});
          end 
        end
      end
    end
  end

  assign DOUT = dout_reg;
  assign OVFL = ovfl_reg;
  assign UDFL = udfl_reg;
  assign SATUR = satu_reg;
endmodule