data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/src/deprecated/pulp_clock_gating_async.sv
1: b"%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/src/deprecated/pulp_clock_gating_async.sv:37: Cannot find file containing module: 'pulp_clock_gating'\n  pulp_clock_gating i_clk_gate (\n  ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/src/deprecated,data/full_repos/permissive/489147019/pulp_clock_gating\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/src/deprecated,data/full_repos/permissive/489147019/pulp_clock_gating.v\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/tech_cells_generic/src/deprecated,data/full_repos/permissive/489147019/pulp_clock_gating.sv\n             pulp_clock_gating\n             pulp_clock_gating.v\n             pulp_clock_gating.sv\n             obj_dir/pulp_clock_gating\n             obj_dir/pulp_clock_gating.v\n             obj_dir/pulp_clock_gating.sv\n%Error: Exiting due to 1 error(s)\n"
module pulp_clock_gating_async #(
  parameter int unsigned STAGES = 2
) (
  input  logic clk_i,
  input  logic rstn_i,
  input  logic en_async_i,
  output logic en_ack_o,
  input  logic test_en_i,
  output logic clk_o
);

  logic [STAGES-1:0] r_reg;

  assign en_ack_o =  r_reg[STAGES-1];


  always_ff @ (posedge clk_i or negedge rstn_i) begin
    if (!rstn_i) begin
      r_reg <= '0;
    end else begin
      r_reg <= {r_reg[STAGES-2:0], en_async_i};
    end
  end

  pulp_clock_gating i_clk_gate (
    .clk_i,
    .en_i ( r_reg[STAGES-1] ),
    .test_en_i,
    .clk_o
  );

endmodule
module pulp_clock_gating_async #(
  parameter int unsigned STAGES = 2
) (
  input  logic clk_i,
  input  logic rstn_i,
  input  logic en_async_i,
  output logic en_ack_o,
  input  logic test_en_i,
  output logic clk_o
);


  logic [STAGES-1:0] r_reg;

  assign en_ack_o =  r_reg[STAGES-1];


  always_ff @ (posedge clk_i or negedge rstn_i) begin
    if (!rstn_i) begin
      r_reg <= '0;
    end else begin
      r_reg <= {r_reg[STAGES-2:0], en_async_i};
    end
  end

  pulp_clock_gating i_clk_gate (
    .clk_i,
    .en_i ( r_reg[STAGES-1] ),
    .test_en_i,
    .clk_o
  );

endmodule