data/full_repos/permissive/476411617/Top_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/476411617/Top_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n  forever #5 clk = !clk;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/476411617/Top_tb.v:132: Too many digits for 32 bit number: \'h00000001_00000001_00000000_00000000_00000000\nram[1]  = \'h00000001_00000001_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:133: Too many digits for 32 bit number: \'h00000002_00000002_00000000_00000000_00000000\nram[2]  = \'h00000002_00000002_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:134: Too many digits for 32 bit number: \'h00000003_00000003_00000000_00000000_00000000\nram[3]  = \'h00000003_00000003_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:135: Too many digits for 32 bit number: \'h00000004_00000004_00000000_00000000_00000000\nram[4]  = \'h00000004_00000004_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:136: Too many digits for 32 bit number: \'h00000005_00000005_00000000_00000000_00000000\nram[5]  = \'h00000005_00000005_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:137: Too many digits for 32 bit number: \'h00000006_00000006_00000000_00000000_00000000\nram[6]  = \'h00000006_00000006_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:138: Too many digits for 32 bit number: \'h00000007_00000007_00000000_00000000_00000000\nram[7]  = \'h00000007_00000007_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:139: Too many digits for 32 bit number: \'h00000008_00000008_00000000_00000000_00000000\nram[8]  = \'h00000008_00000008_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:140: Too many digits for 32 bit number: \'h00000009_00000009_00000000_00000000_00000000\nram[9]  = \'h00000009_00000009_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:141: Too many digits for 32 bit number: \'h0000000a_0000000a_00000000_00000000_00000000\nram[10] = \'h0000000a_0000000a_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:142: Too many digits for 32 bit number: \'h0000000b_0000000b_00000000_00000000_00000000\nram[11] = \'h0000000b_0000000b_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:143: Too many digits for 32 bit number: \'h0000000c_0000000c_00000000_00000000_00000000\nram[12] = \'h0000000c_0000000c_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:144: Too many digits for 32 bit number: \'h0000000d_0000000d_00000000_00000000_00000000\nram[13] = \'h0000000d_0000000d_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:145: Too many digits for 32 bit number: \'h0000000e_0000000e_00000000_00000000_00000000\nram[14] = \'h0000000e_0000000e_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:146: Too many digits for 32 bit number: \'h0000000f_0000000f_00000000_00000000_00000000\nram[15] = \'h0000000f_0000000f_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/476411617/Top_tb.v:151: Unsupported: Ignoring delay on this delayed statement.\n#1610\n^\n%Error: data/full_repos/permissive/476411617/Top_tb.v:153: Too many digits for 32 bit number: \'h00000001_00000001_00000000_00000000_00000000\nram[1]  = \'h00000001_00000001_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:154: Too many digits for 32 bit number: \'h00000002_00000002_00000000_00000000_00000000\nram[2]  = \'h00000002_00000002_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:155: Too many digits for 32 bit number: \'h00000003_00000003_00000000_00000000_00000000\nram[3]  = \'h00000003_00000003_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:156: Too many digits for 32 bit number: \'h00000004_00000004_00000000_00000000_00000000\nram[4]  = \'h00000004_00000004_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:157: Too many digits for 32 bit number: \'h00000005_00000005_00000000_00000000_00000000\nram[5]  = \'h00000005_00000005_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:158: Too many digits for 32 bit number: \'h00000006_00000006_00000000_00000000_00000000\nram[6]  = \'h00000006_00000006_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:159: Too many digits for 32 bit number: \'h00000007_00000007_00000000_00000000_00000000\nram[7]  = \'h00000007_00000007_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:160: Too many digits for 32 bit number: \'h00000008_00000008_00000000_00000000_00000000\nram[8]  = \'h00000008_00000008_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:161: Too many digits for 32 bit number: \'h00000009_00000009_00000000_00000000_00000000\nram[9]  = \'h00000009_00000009_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:162: Too many digits for 32 bit number: \'h0000000a_0000000a_00000000_00000000_00000000\nram[10] = \'h0000000a_0000000a_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:163: Too many digits for 32 bit number: \'h0000000b_0000000b_00000000_00000000_00000000\nram[11] = \'h0000000b_0000000b_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:164: Too many digits for 32 bit number: \'h0000000c_0000000c_00000000_00000000_00000000\nram[12] = \'h0000000c_0000000c_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:165: Too many digits for 32 bit number: \'h0000000d_0000000d_00000000_00000000_00000000\nram[13] = \'h0000000d_0000000d_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:166: Too many digits for 32 bit number: \'h0000000e_0000000e_00000000_00000000_00000000\nram[14] = \'h0000000e_0000000e_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:167: Too many digits for 32 bit number: \'h0000000f_0000000f_00000000_00000000_00000000\nram[15] = \'h0000000f_0000000f_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/476411617/Top_tb.v:172: Unsupported: Ignoring delay on this delayed statement.\n#1610\n^\n%Error: data/full_repos/permissive/476411617/Top_tb.v:174: Too many digits for 32 bit number: \'h00000001_00000001_00000000_00000000_00000000\nram[1]  = \'h00000001_00000001_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:175: Too many digits for 32 bit number: \'h00000002_00000002_00000000_00000000_00000000\nram[2]  = \'h00000002_00000002_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:176: Too many digits for 32 bit number: \'h00000003_00000003_00000000_00000000_00000000\nram[3]  = \'h00000003_00000003_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:177: Too many digits for 32 bit number: \'h00000004_00000004_00000000_00000000_00000000\nram[4]  = \'h00000004_00000004_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:178: Too many digits for 32 bit number: \'h00000005_00000005_00000000_00000000_00000000\nram[5]  = \'h00000005_00000005_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:179: Too many digits for 32 bit number: \'h00000006_00000006_00000000_00000000_00000000\nram[6]  = \'h00000006_00000006_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:180: Too many digits for 32 bit number: \'h00000007_00000007_00000000_00000000_00000000\nram[7]  = \'h00000007_00000007_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:181: Too many digits for 32 bit number: \'h00000008_00000008_00000000_00000000_00000000\nram[8]  = \'h00000008_00000008_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:182: Too many digits for 32 bit number: \'h00000009_00000009_00000000_00000000_00000000\nram[9]  = \'h00000009_00000009_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:183: Too many digits for 32 bit number: \'h0000000a_0000000a_00000000_00000000_00000000\nram[10] = \'h0000000a_0000000a_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:184: Too many digits for 32 bit number: \'h0000000b_0000000b_00000000_00000000_00000000\nram[11] = \'h0000000b_0000000b_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:185: Too many digits for 32 bit number: \'h0000000c_0000000c_00000000_00000000_00000000\nram[12] = \'h0000000c_0000000c_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:186: Too many digits for 32 bit number: \'h0000000d_0000000d_00000000_00000000_00000000\nram[13] = \'h0000000d_0000000d_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:187: Too many digits for 32 bit number: \'h0000000e_0000000e_00000000_00000000_00000000\nram[14] = \'h0000000e_0000000e_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:188: Too many digits for 32 bit number: \'h0000000f_0000000f_00000000_00000000_00000000\nram[15] = \'h0000000f_0000000f_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/476411617/Top_tb.v:193: Unsupported: Ignoring delay on this delayed statement.\n#1610\n^\n%Error: data/full_repos/permissive/476411617/Top_tb.v:195: Too many digits for 32 bit number: \'h00000001_00000001_00000000_00000000_00000000\nram[1]  = \'h00000001_00000001_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:196: Too many digits for 32 bit number: \'h00000002_00000002_00000000_00000000_00000000\nram[2]  = \'h00000002_00000002_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:197: Too many digits for 32 bit number: \'h00000003_00000003_00000000_00000000_00000000\nram[3]  = \'h00000003_00000003_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:198: Too many digits for 32 bit number: \'h00000004_00000004_00000000_00000000_00000000\nram[4]  = \'h00000004_00000004_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/Top_tb.v:199: Too many digits for 32 bit number: \'h00000005_00000005_00000000_00000000_00000000\nram[5]  = \'h00000005_00000005_00000000_00000000_00000000;\n          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n        ... See the manual and https://verilator.org for more assistance.\n'
module Top_tb;

parameter SIZE = 2;
parameter MAX_WORD_LENGTH = 32;


reg clk, reset, start;
reg[31:0] instruction;
reg[5:0] LENGTH;



reg external;
reg[7:0] BRAM_i;
reg[7:0] BRAM_j;
reg WEA, WEB;
reg[9:0] ADDRA = -1;
reg[9:0] ADDRB = 5;
reg[15:0] DINA, DINB;
wire[15:0] DOUTA, DOUTB;
reg[159:0] ram[15:0];
reg[9:0] ram_ptr = 0;
integer i=0, j=0, k=0;
wire[0:SIZE*8-1] WOUT;
wire[0:SIZE*8-1] EOUT;
wire[0:4*SIZE*MAX_WORD_LENGTH-1] EAST_O;
wire[0:4*SIZE*MAX_WORD_LENGTH-1] WEST_O;
Top #(SIZE, MAX_WORD_LENGTH) TopTB(clk, reset, start, LENGTH, instruction, external, BRAM_i, BRAM_j, WEA, WEB, ADDRA, ADDRB, DINA, DINB, DOUTA, DOUTB, EAST_O, WEST_O);

initial begin
  clk = 1;
  forever #5 clk = !clk;
end

always @ (posedge clk) begin



           


    if(BRAM_i == 0 && BRAM_j == 0) begin
        if(!reset) begin
            WEA = 1;
            for(k=15; k>=0; k=k-1) begin  
                DINA[k] = ram[k][ram_ptr];
            end
            LENGTH = 32;
            ADDRA = ADDRA + 1;
            ram_ptr = ram_ptr + 1;
        end 
        else DINA = 0;
    end 
    if(BRAM_i == 0 && BRAM_j == 1) begin
        if(!reset) begin
            WEA = 1;
            for(k=15; k>=0; k=k-1) begin  
                DINA[k] = ram[k][ram_ptr];
            end
            LENGTH = 32;
            ADDRA = ADDRA + 1;
            ram_ptr = ram_ptr + 1;
        end 
        else DINA = 0;
    end 
    if(BRAM_i == 1 && BRAM_j == 0) begin
        if(!reset) begin
            WEA = 1;
            for(k=15; k>=0; k=k-1) begin  
                DINA[k] = ram[k][ram_ptr];
            end
            LENGTH = 32;
            ADDRA = ADDRA + 1;
            ram_ptr = ram_ptr + 1;
        end 
        else DINA = 0;
    end 
    if(BRAM_i == 1 && BRAM_j == 1) begin
        if(!reset) begin
            WEA = 1;
            for(k=15; k>=0; k=k-1) begin  
                DINA[k] = ram[k][ram_ptr];
            end
            LENGTH = 32;
            ADDRA = ADDRA + 1;
            ram_ptr = ram_ptr + 1;
        end 
        else DINA = 0;
    end 
end
initial
 
begin







reset = 0; 
start = 0;
external = 1;
ram[0]  = 'h00000000_00000000_00000000_00000000_00000000;
ram[1]  = 'h00000001_00000001_00000000_00000000_00000000;
ram[2]  = 'h00000002_00000002_00000000_00000000_00000000;
ram[3]  = 'h00000003_00000003_00000000_00000000_00000000;
ram[4]  = 'h00000004_00000004_00000000_00000000_00000000;
ram[5]  = 'h00000005_00000005_00000000_00000000_00000000;
ram[6] 	= 'h00000006_00000006_00000000_00000000_00000000;
ram[7] 	= 'h00000007_00000007_00000000_00000000_00000000;
ram[8] 	= 'h00000008_00000008_00000000_00000000_00000000;
ram[9] 	= 'h00000009_00000009_00000000_00000000_00000000;
ram[10]	= 'h0000000a_0000000a_00000000_00000000_00000000;
ram[11]	= 'h0000000b_0000000b_00000000_00000000_00000000;
ram[12]	= 'h0000000c_0000000c_00000000_00000000_00000000;
ram[13]	= 'h0000000d_0000000d_00000000_00000000_00000000;
ram[14]	= 'h0000000e_0000000e_00000000_00000000_00000000;
ram[15]	= 'h0000000f_0000000f_00000000_00000000_00000000;
BRAM_i = 0;
BRAM_j = 0;
ADDRA = -1;
ram_ptr = 0;
#1610
ram[0]  = 'h00000000_00000000_00000000_00000000_00000000;
ram[1]  = 'h00000001_00000001_00000000_00000000_00000000;
ram[2]  = 'h00000002_00000002_00000000_00000000_00000000;
ram[3]  = 'h00000003_00000003_00000000_00000000_00000000;
ram[4]  = 'h00000004_00000004_00000000_00000000_00000000;
ram[5]  = 'h00000005_00000005_00000000_00000000_00000000;
ram[6] 	= 'h00000006_00000006_00000000_00000000_00000000;
ram[7] 	= 'h00000007_00000007_00000000_00000000_00000000;
ram[8] 	= 'h00000008_00000008_00000000_00000000_00000000;
ram[9] 	= 'h00000009_00000009_00000000_00000000_00000000;
ram[10]	= 'h0000000a_0000000a_00000000_00000000_00000000;
ram[11]	= 'h0000000b_0000000b_00000000_00000000_00000000;
ram[12]	= 'h0000000c_0000000c_00000000_00000000_00000000;
ram[13]	= 'h0000000d_0000000d_00000000_00000000_00000000;
ram[14]	= 'h0000000e_0000000e_00000000_00000000_00000000;
ram[15]	= 'h0000000f_0000000f_00000000_00000000_00000000;
BRAM_i = 0;
BRAM_j = 1;
ADDRA = -1;
ram_ptr = 0;
#1610
ram[0]  = 'h00000000_00000000_00000000_00000000_00000000;
ram[1]  = 'h00000001_00000001_00000000_00000000_00000000;
ram[2]  = 'h00000002_00000002_00000000_00000000_00000000;
ram[3]  = 'h00000003_00000003_00000000_00000000_00000000;
ram[4]  = 'h00000004_00000004_00000000_00000000_00000000;
ram[5]  = 'h00000005_00000005_00000000_00000000_00000000;
ram[6] 	= 'h00000006_00000006_00000000_00000000_00000000;
ram[7] 	= 'h00000007_00000007_00000000_00000000_00000000;
ram[8] 	= 'h00000008_00000008_00000000_00000000_00000000;
ram[9] 	= 'h00000009_00000009_00000000_00000000_00000000;
ram[10]	= 'h0000000a_0000000a_00000000_00000000_00000000;
ram[11]	= 'h0000000b_0000000b_00000000_00000000_00000000;
ram[12]	= 'h0000000c_0000000c_00000000_00000000_00000000;
ram[13]	= 'h0000000d_0000000d_00000000_00000000_00000000;
ram[14]	= 'h0000000e_0000000e_00000000_00000000_00000000;
ram[15]	= 'h0000000f_0000000f_00000000_00000000_00000000;
BRAM_i = 1;
BRAM_j = 0;
ADDRA = -1;
ram_ptr = 0;
#1610
ram[0]  = 'h00000000_00000000_00000000_00000000_00000000;
ram[1]  = 'h00000001_00000001_00000000_00000000_00000000;
ram[2]  = 'h00000002_00000002_00000000_00000000_00000000;
ram[3]  = 'h00000003_00000003_00000000_00000000_00000000;
ram[4]  = 'h00000004_00000004_00000000_00000000_00000000;
ram[5]  = 'h00000005_00000005_00000000_00000000_00000000;
ram[6] 	= 'h00000006_00000006_00000000_00000000_00000000;
ram[7] 	= 'h00000007_00000007_00000000_00000000_00000000;
ram[8] 	= 'h00000008_00000008_00000000_00000000_00000000;
ram[9] 	= 'h00000009_00000009_00000000_00000000_00000000;
ram[10]	= 'h0000000a_0000000a_00000000_00000000_00000000;
ram[11]	= 'h0000000b_0000000b_00000000_00000000_00000000;
ram[12]	= 'h0000000c_0000000c_00000000_00000000_00000000;
ram[13]	= 'h0000000d_0000000d_00000000_00000000_00000000;
ram[14]	= 'h0000000e_0000000e_00000000_00000000_00000000;
ram[15]	= 'h0000000f_0000000f_00000000_00000000_00000000;
BRAM_i = 1;
BRAM_j = 1;
ADDRA = -1;
ram_ptr = 0;
#1610
reset = 1;
#2000
external = 0;

instruction = (2<<26) + (1<<21) + (3<<16) + (4<<11);
start = 1;
#10 
start = 0;



































end

endmodule
module Top_tb;


parameter SIZE = 2;
parameter MAX_WORD_LENGTH = 32;


reg clk, reset, start;
reg[31:0] instruction;
reg[5:0] LENGTH;



reg external;
reg[7:0] BRAM_i;
reg[7:0] BRAM_j;
reg WEA, WEB;
reg[9:0] ADDRA = -1;
reg[9:0] ADDRB = 5;
reg[15:0] DINA, DINB;
wire[15:0] DOUTA, DOUTB;
reg[159:0] ram[15:0];
reg[9:0] ram_ptr = 0;
integer i=0, j=0, k=0;
wire[0:SIZE*8-1] WOUT;
wire[0:SIZE*8-1] EOUT;
wire[0:4*SIZE*MAX_WORD_LENGTH-1] EAST_O;
wire[0:4*SIZE*MAX_WORD_LENGTH-1] WEST_O;
Top #(SIZE, MAX_WORD_LENGTH) TopTB(clk, reset, start, LENGTH, instruction, external, BRAM_i, BRAM_j, WEA, WEB, ADDRA, ADDRB, DINA, DINB, DOUTA, DOUTB, EAST_O, WEST_O);

initial begin
  clk = 1;
  forever #5 clk = !clk;
end

always @ (posedge clk) begin



           


    if(BRAM_i == 0 && BRAM_j == 0) begin
        if(!reset) begin
            WEA = 1;
            for(k=15; k>=0; k=k-1) begin  
                DINA[k] = ram[k][ram_ptr];
            end
            LENGTH = 32;
            ADDRA = ADDRA + 1;
            ram_ptr = ram_ptr + 1;
        end 
        else DINA = 0;
    end 
    if(BRAM_i == 0 && BRAM_j == 1) begin
        if(!reset) begin
            WEA = 1;
            for(k=15; k>=0; k=k-1) begin  
                DINA[k] = ram[k][ram_ptr];
            end
            LENGTH = 32;
            ADDRA = ADDRA + 1;
            ram_ptr = ram_ptr + 1;
        end 
        else DINA = 0;
    end 
    if(BRAM_i == 1 && BRAM_j == 0) begin
        if(!reset) begin
            WEA = 1;
            for(k=15; k>=0; k=k-1) begin  
                DINA[k] = ram[k][ram_ptr];
            end
            LENGTH = 32;
            ADDRA = ADDRA + 1;
            ram_ptr = ram_ptr + 1;
        end 
        else DINA = 0;
    end 
    if(BRAM_i == 1 && BRAM_j == 1) begin
        if(!reset) begin
            WEA = 1;
            for(k=15; k>=0; k=k-1) begin  
                DINA[k] = ram[k][ram_ptr];
            end
            LENGTH = 32;
            ADDRA = ADDRA + 1;
            ram_ptr = ram_ptr + 1;
        end 
        else DINA = 0;
    end 
end
initial
 
begin







reset = 0; 
start = 0;
external = 1;
ram[0]  = 'h00000000_00000000_00000000_00000000_00000000;
ram[1]  = 'h00000001_00000001_00000000_00000000_00000000;
ram[2]  = 'h00000002_00000002_00000000_00000000_00000000;
ram[3]  = 'h00000003_00000003_00000000_00000000_00000000;
ram[4]  = 'h00000004_00000004_00000000_00000000_00000000;
ram[5]  = 'h00000005_00000005_00000000_00000000_00000000;
ram[6] 	= 'h00000006_00000006_00000000_00000000_00000000;
ram[7] 	= 'h00000007_00000007_00000000_00000000_00000000;
ram[8] 	= 'h00000008_00000008_00000000_00000000_00000000;
ram[9] 	= 'h00000009_00000009_00000000_00000000_00000000;
ram[10]	= 'h0000000a_0000000a_00000000_00000000_00000000;
ram[11]	= 'h0000000b_0000000b_00000000_00000000_00000000;
ram[12]	= 'h0000000c_0000000c_00000000_00000000_00000000;
ram[13]	= 'h0000000d_0000000d_00000000_00000000_00000000;
ram[14]	= 'h0000000e_0000000e_00000000_00000000_00000000;
ram[15]	= 'h0000000f_0000000f_00000000_00000000_00000000;
BRAM_i = 0;
BRAM_j = 0;
ADDRA = -1;
ram_ptr = 0;
#1610
ram[0]  = 'h00000000_00000000_00000000_00000000_00000000;
ram[1]  = 'h00000001_00000001_00000000_00000000_00000000;
ram[2]  = 'h00000002_00000002_00000000_00000000_00000000;
ram[3]  = 'h00000003_00000003_00000000_00000000_00000000;
ram[4]  = 'h00000004_00000004_00000000_00000000_00000000;
ram[5]  = 'h00000005_00000005_00000000_00000000_00000000;
ram[6] 	= 'h00000006_00000006_00000000_00000000_00000000;
ram[7] 	= 'h00000007_00000007_00000000_00000000_00000000;
ram[8] 	= 'h00000008_00000008_00000000_00000000_00000000;
ram[9] 	= 'h00000009_00000009_00000000_00000000_00000000;
ram[10]	= 'h0000000a_0000000a_00000000_00000000_00000000;
ram[11]	= 'h0000000b_0000000b_00000000_00000000_00000000;
ram[12]	= 'h0000000c_0000000c_00000000_00000000_00000000;
ram[13]	= 'h0000000d_0000000d_00000000_00000000_00000000;
ram[14]	= 'h0000000e_0000000e_00000000_00000000_00000000;
ram[15]	= 'h0000000f_0000000f_00000000_00000000_00000000;
BRAM_i = 0;
BRAM_j = 1;
ADDRA = -1;
ram_ptr = 0;
#1610
ram[0]  = 'h00000000_00000000_00000000_00000000_00000000;
ram[1]  = 'h00000001_00000001_00000000_00000000_00000000;
ram[2]  = 'h00000002_00000002_00000000_00000000_00000000;
ram[3]  = 'h00000003_00000003_00000000_00000000_00000000;
ram[4]  = 'h00000004_00000004_00000000_00000000_00000000;
ram[5]  = 'h00000005_00000005_00000000_00000000_00000000;
ram[6] 	= 'h00000006_00000006_00000000_00000000_00000000;
ram[7] 	= 'h00000007_00000007_00000000_00000000_00000000;
ram[8] 	= 'h00000008_00000008_00000000_00000000_00000000;
ram[9] 	= 'h00000009_00000009_00000000_00000000_00000000;
ram[10]	= 'h0000000a_0000000a_00000000_00000000_00000000;
ram[11]	= 'h0000000b_0000000b_00000000_00000000_00000000;
ram[12]	= 'h0000000c_0000000c_00000000_00000000_00000000;
ram[13]	= 'h0000000d_0000000d_00000000_00000000_00000000;
ram[14]	= 'h0000000e_0000000e_00000000_00000000_00000000;
ram[15]	= 'h0000000f_0000000f_00000000_00000000_00000000;
BRAM_i = 1;
BRAM_j = 0;
ADDRA = -1;
ram_ptr = 0;
#1610
ram[0]  = 'h00000000_00000000_00000000_00000000_00000000;
ram[1]  = 'h00000001_00000001_00000000_00000000_00000000;
ram[2]  = 'h00000002_00000002_00000000_00000000_00000000;
ram[3]  = 'h00000003_00000003_00000000_00000000_00000000;
ram[4]  = 'h00000004_00000004_00000000_00000000_00000000;
ram[5]  = 'h00000005_00000005_00000000_00000000_00000000;
ram[6] 	= 'h00000006_00000006_00000000_00000000_00000000;
ram[7] 	= 'h00000007_00000007_00000000_00000000_00000000;
ram[8] 	= 'h00000008_00000008_00000000_00000000_00000000;
ram[9] 	= 'h00000009_00000009_00000000_00000000_00000000;
ram[10]	= 'h0000000a_0000000a_00000000_00000000_00000000;
ram[11]	= 'h0000000b_0000000b_00000000_00000000_00000000;
ram[12]	= 'h0000000c_0000000c_00000000_00000000_00000000;
ram[13]	= 'h0000000d_0000000d_00000000_00000000_00000000;
ram[14]	= 'h0000000e_0000000e_00000000_00000000_00000000;
ram[15]	= 'h0000000f_0000000f_00000000_00000000_00000000;
BRAM_i = 1;
BRAM_j = 1;
ADDRA = -1;
ram_ptr = 0;
#1610
reset = 1;
#2000
external = 0;

instruction = (2<<26) + (1<<21) + (3<<16) + (4<<11);
start = 1;
#10 
start = 0;



































end

endmodule