data/full_repos/permissive/440502068/verilog/rtl/cores/ibex_controller.v
1: b'%Warning-WIDTH: data/full_repos/permissive/440502068/verilog/rtl/cores/ibex_controller.v:279: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'sh0\' generates 1 bits.\n                                                                                            : ... In instance ibex_controller\n  csr_mtval_o = 1\'sb0;\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
function automatic [5:0] sv2v_cast_6;
		input reg [5:0] inp;
		sv2v_cast_6 = inp;
	endfunction
function automatic [5:0] sv2v_cast_6;

		input reg [5:0] inp;
		sv2v_cast_6 = inp;
	endfunction