data/full_repos/permissive/509468557/tools/dsptools/src/main/resources/BBFLn.v
data/verilator_xmls/ed137662-baa6-4a52-ac07-f4bceed40a7a.xml
module BBFLn(
    input  [63:0] in,
    output reg [63:0] out
);
  always @* begin
  out = $realtobits($ln($bitstoreal(in)));
  end
endmodule
module BBFLn(
    input  [63:0] in,
    output reg [63:0] out
);

  always @* begin
  out = $realtobits($ln($bitstoreal(in)));
  end
endmodule