data/full_repos/permissive/481307378/source_files/TrafficLight/ampel_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/TrafficLight/ampel_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n    always #250 CLK = !CLK;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/481307378/source_files/TrafficLight/ampel_tb.v:28: syntax error, unexpected \'@\'\n        @(negedge CLK);  \n        ^\n%Error: data/full_repos/permissive/481307378/source_files/TrafficLight/ampel_tb.v:32: syntax error, unexpected \'@\'\n            @(negedge CLK);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/TrafficLight/ampel_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #35000 $finish;\n        ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ampel_tb();

    reg RESN, CLK, BTN;
    wire [2 : 0] RGB;
    

    ampel dut(.RESN(RESN), .CLK(CLK), .BTN(BTN), .RGB(RGB));
    

    defparam dut.CLOCK_SIGNALS = 32'd10;
    

    initial 
    begin
        RESN = 1'b0;
        BTN = 1'b0;
        CLK = 1'b0;
    end
    

    always #250 CLK = !CLK;
    

    initial
    begin  
        @(negedge CLK);
        RESN = 1'b1;
        BTN = 1'b1;
        repeat(3) begin
            @(negedge CLK);
        end   
        BTN = 1'b0;
        
        
        
        #35000 $finish;
    end
      

endmodule
module ampel_tb();


    reg RESN, CLK, BTN;
    wire [2 : 0] RGB;
    

    ampel dut(.RESN(RESN), .CLK(CLK), .BTN(BTN), .RGB(RGB));
    

    defparam dut.CLOCK_SIGNALS = 32'd10;
    

    initial 
    begin
        RESN = 1'b0;
        BTN = 1'b0;
        CLK = 1'b0;
    end
    

    always #250 CLK = !CLK;
    

    initial
    begin  
        @(negedge CLK);
        RESN = 1'b1;
        BTN = 1'b1;
        repeat(3) begin
            @(negedge CLK);
        end   
        BTN = 1'b0;
        
        
        
        #35000 $finish;
    end
      

endmodule