data/full_repos/permissive/418897317/verilog/dv/ethernet_100m/ethernet_100m_tb.v
1: b'%Error: data/full_repos/permissive/418897317/verilog/dv/ethernet_100m/ethernet_100m_tb.v:20: Cannot find include file: udp_host.v\n`include "udp_host.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418897317/verilog/dv/ethernet_100m,data/full_repos/permissive/418897317/udp_host.v\n             data/full_repos/permissive/418897317/verilog/dv/ethernet_100m,data/full_repos/permissive/418897317/udp_host.v.v\n             data/full_repos/permissive/418897317/verilog/dv/ethernet_100m,data/full_repos/permissive/418897317/udp_host.v.sv\n             udp_host.v\n             udp_host.v.v\n             udp_host.v.sv\n             obj_dir/udp_host.v\n             obj_dir/udp_host.v.v\n             obj_dir/udp_host.v.sv\n%Error: data/full_repos/permissive/418897317/verilog/dv/ethernet_100m/ethernet_100m_tb.v:21: Cannot find include file: uprj_netlists.v\n`include "uprj_netlists.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418897317/verilog/dv/ethernet_100m/ethernet_100m_tb.v:22: Cannot find include file: caravel_netlists.v\n`include "caravel_netlists.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418897317/verilog/dv/ethernet_100m/ethernet_100m_tb.v:23: Cannot find include file: spiflash.v\n`include "spiflash.v" \n         ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/418897317/verilog/dv/ethernet_100m/ethernet_100m_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n always #20 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/418897317/verilog/dv/ethernet_100m/ethernet_100m_tb.v:76: Unsupported: wait statements\n    #172001 wait(CSB);\n            ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/418897317/verilog/dv/ethernet_100m/ethernet_100m_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n    #172001 wait(CSB);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/418897317/verilog/dv/ethernet_100m/ethernet_100m_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n    #1000 rst = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/418897317/verilog/dv/ethernet_100m/ethernet_100m_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n    #100  rst = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/418897317/verilog/dv/ethernet_100m/ethernet_100m_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n    #100000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/418897317/verilog/dv/ethernet_100m/ethernet_100m_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n  #2000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/418897317/verilog/dv/ethernet_100m/ethernet_100m_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n  #170000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/418897317/verilog/dv/ethernet_100m/ethernet_100m_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/418897317/verilog/dv/ethernet_100m/ethernet_100m_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/418897317/verilog/dv/ethernet_100m/ethernet_100m_tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/418897317/verilog/dv/ethernet_100m/ethernet_100m_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/418897317/verilog/dv/ethernet_100m/ethernet_100m_tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);\n  ^\n%Error: Exiting due to 5 error(s), 12 warning(s)\n'
module ethernet_100m_tb;
	reg clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

	wire gpio;
	wire [37:0] mprj_io;
	
	reg  rst;
	wire [3:0] phy_txd;
    wire phy_tx_en;
    wire phy_tx_clk;
    wire phy_rx_clk;
    wire [3:0] phy_rxd;
    wire phy_rx_dv;
    wire phy_rx_er;

    integer clock_counter = 0;
    integer f = 0;

    assign mprj_io[8]	= rst;
	assign phy_txd		= mprj_io[21:18];
    assign phy_tx_en	= mprj_io[17];
    assign phy_tx_clk	= mprj_io[16];
    assign phy_rx_clk	= mprj_io[9];
    assign phy_rxd 		= mprj_io[15:12];
    assign phy_rx_dv	= mprj_io[10];
    assign phy_rx_er	= mprj_io[11];

	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;





	always #20 clock <= (clock === 1'b0);

	always @(posedge clock) begin
		clock_counter = clock_counter + 1;
		if (clock_counter == 25) $fwrite(f, "%d nanoseconds elapsed.\n", clock_counter*40);
	end

	initial begin
	   clock = 0;
	   rst = 0;

	   f = $fopen("output.txt","w");
	   $fwrite(f, "Test Ethernet 100Mbps Started");

	   #172001 wait(CSB);
	   
	   #1000 rst = 1;
	   #100  rst = 0;

	   #100000;
	   `ifdef GL
	      $display ("Monitor: Timeout, Test Ethernet 100Mbps (GL) Failed");
	   `else
	      $display ("Monitor: Timeout, Test Ethernet 100Mbps (RTL) Failed");
	   `endif
	   $finish;
	end

	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#170000;
		CSB = 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end

	always @(mprj_io) begin
		#1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
	end

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3 = power1;
	wire VDD1V8 = power2;
	wire USER_VDD3V3 = power3;
	wire USER_VDD1V8 = power4;
	wire VSS = 1'b0;

	udp_host host(
	    .clk(clock),
	    .rst(rst),
	    .phy_txd(phy_txd),
	    .phy_tx_en(phy_tx_en),
	    .phy_tx_clk(phy_tx_clk),
	    .phy_rx_clk(phy_rx_clk),
	    .phy_rxd(phy_rxd),
	    .phy_rx_dv(phy_rx_dv),
	    .phy_rx_er(phy_rx_er)
    );

	caravel uut (
		.vddio	  (VDD3V3),
		.vssio	  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (USER_VDD3V3),
		.vdda2    (USER_VDD3V3),
		.vssa1	  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (USER_VDD1V8),
		.vccd2	  (USER_VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock	  (clock),
		.gpio     (gpio),
        .mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("ethernet_100m.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule
module ethernet_100m_tb;

	reg clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

	wire gpio;
	wire [37:0] mprj_io;
	
	reg  rst;
	wire [3:0] phy_txd;
    wire phy_tx_en;
    wire phy_tx_clk;
    wire phy_rx_clk;
    wire [3:0] phy_rxd;
    wire phy_rx_dv;
    wire phy_rx_er;

    integer clock_counter = 0;
    integer f = 0;

    assign mprj_io[8]	= rst;
	assign phy_txd		= mprj_io[21:18];
    assign phy_tx_en	= mprj_io[17];
    assign phy_tx_clk	= mprj_io[16];
    assign phy_rx_clk	= mprj_io[9];
    assign phy_rxd 		= mprj_io[15:12];
    assign phy_rx_dv	= mprj_io[10];
    assign phy_rx_er	= mprj_io[11];

	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;





	always #20 clock <= (clock === 1'b0);

	always @(posedge clock) begin
		clock_counter = clock_counter + 1;
		if (clock_counter == 25) $fwrite(f, "%d nanoseconds elapsed.\n", clock_counter*40);
	end

	initial begin
	   clock = 0;
	   rst = 0;

	   f = $fopen("output.txt","w");
	   $fwrite(f, "Test Ethernet 100Mbps Started");

	   #172001 wait(CSB);
	   
	   #1000 rst = 1;
	   #100  rst = 0;

	   #100000;
	   `ifdef GL
	      $display ("Monitor: Timeout, Test Ethernet 100Mbps (GL) Failed");
	   `else
	      $display ("Monitor: Timeout, Test Ethernet 100Mbps (RTL) Failed");
	   `endif
	   $finish;
	end

	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#170000;
		CSB = 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end

	always @(mprj_io) begin
		#1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
	end

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3 = power1;
	wire VDD1V8 = power2;
	wire USER_VDD3V3 = power3;
	wire USER_VDD1V8 = power4;
	wire VSS = 1'b0;

	udp_host host(
	    .clk(clock),
	    .rst(rst),
	    .phy_txd(phy_txd),
	    .phy_tx_en(phy_tx_en),
	    .phy_tx_clk(phy_tx_clk),
	    .phy_rx_clk(phy_rx_clk),
	    .phy_rxd(phy_rxd),
	    .phy_rx_dv(phy_rx_dv),
	    .phy_rx_er(phy_rx_er)
    );

	caravel uut (
		.vddio	  (VDD3V3),
		.vssio	  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (USER_VDD3V3),
		.vdda2    (USER_VDD3V3),
		.vssa1	  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (USER_VDD1V8),
		.vccd2	  (USER_VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock	  (clock),
		.gpio     (gpio),
        .mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("ethernet_100m.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule