data/full_repos/permissive/43856783/j1_soc/hdl/Position/position_j1_tst.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Position/position_j1_tst.v:129: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Position/position_j1_tst.v:135: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Position/position_j1_tst.v:139: Unsupported: Ignoring delay on this delayed statement.\n  #50;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Position/position_j1_tst.v:140: Unsupported: Ignoring delay on this delayed statement.\n  while(d_out!=0)#10;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/Position/position_j1_tst.v:146: Unsupported: Ignoring delay on this delayed statement.\n always #5 clk = !clk;\n        ^\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/Position/position_j1_tst.v:55: Cannot find file containing module: \'position_peripheral\'\n position_peripheral uut (\n ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43856783/j1_soc/hdl/Position,data/full_repos/permissive/43856783/position_peripheral\n             data/full_repos/permissive/43856783/j1_soc/hdl/Position,data/full_repos/permissive/43856783/position_peripheral.v\n             data/full_repos/permissive/43856783/j1_soc/hdl/Position,data/full_repos/permissive/43856783/position_peripheral.sv\n             position_peripheral\n             position_peripheral.v\n             position_peripheral.sv\n             obj_dir/position_peripheral\n             obj_dir/position_peripheral.v\n             obj_dir/position_peripheral.sv\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/Position/position_j1_tst.v:83: Cannot find file containing module: \'clk_counter\'\n clk_counter count(\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/Position/position_j1_tst.v:90: Cannot find file containing module: \'clk_counter\'\n clk_counter count2(\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/Position/position_j1_tst.v:97: Cannot find file containing module: \'clk_generator\'\n clk_generator genCLK(\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/Position/position_j1_tst.v:105: Cannot find file containing module: \'clk_interruptor\'\n clk_interruptor intGen(\n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module position_j1_tst;


	reg clk;
	reg rst;
	reg SDA_in;
	wire int_o;
	wire clk_frame;
	wire [31:0] counter_count;
	reg cs;
	reg rd;
	reg wr;
	reg [4:0] addr;
	reg [15:0] d_in;


	wire [15:0] d_out;
	wire SDA_oen;
	wire SDA_out;
	wire [31:0] int_limit;
	wire int_en;
	wire counter_en;
	wire counter_rst;
	wire [31:0] clk_freq;
	wire SCL;
	
	wire SDA;
	assign SDA = SDA_oen? SDA_out : SDA_in;


	position_peripheral uut (
		.clk(clk), 
		.rst(rst), 
		.SDA_in(SDA_in), 
		.int_o(int_o), 
		.clk_frame(clk_frame), 
		.counter_count(counter_count), 
		.cs(cs), 
		.rd(rd), 
		.wr(wr), 
		.addr(addr), 
		.d_in(d_in), 
		.d_out(d_out), 
		.SDA_oen(SDA_oen), 
		.SDA_out(SDA_out), 
		.SCL(SCL),
		.int_limit(int_limit), 
		.int_en(int_en), 
		.counter_en(counter_en), 
		.counter_rst(counter_rst), 
		.clk_freq(clk_freq)
	);
	
	wire [31:0] mcount;
	reg mcoun_en;
	reg mcoun_rst;
	reg clk_enable;
	
	clk_counter count(
		.clk(clk),
		.en(mcoun_en),
		.rst(mcoun_rst),
		.count(mcount)
	);
	
	clk_counter count2(
		.clk(clk),
		.en(counter_en),
		.rst(counter_rst),
		.count(counter_count)
	);
	
	clk_generator genCLK(
		.clk(clk),
		.en(clk_enable),
		.limit(clk_freq),
		.count(mcount),
		.clk_0(clk_frame)
	);
	
	clk_interruptor intGen(
		.clk(clk),
		.en(int_en),
		.limit(int_limit),
		.count(mcount),
		.int_0(int_o)
	);
	
	initial begin

		clk = 0;
		rst = 1;
		SDA_in = 0;
		cs = 0;
		rd = 0;
		wr = 0;
		addr = 0;
		d_in = 0;
		
		mcoun_en  = 0;
		mcoun_rst = 1;
		clk_enable = 0;


		#100;
		rst = 0;
		mcoun_rst = 0;
		mcoun_en = 1;
		clk_enable = 1;

		#10;
		rd = 1;
		addr = 1;
		cs = 1;
		#50;
		while(d_out!=0)#10;
		rd = 0;
		addr = 0;
		cs = 0;
	end
	
	always #5 clk = !clk;
	
endmodule
module position_j1_tst;



	reg clk;
	reg rst;
	reg SDA_in;
	wire int_o;
	wire clk_frame;
	wire [31:0] counter_count;
	reg cs;
	reg rd;
	reg wr;
	reg [4:0] addr;
	reg [15:0] d_in;


	wire [15:0] d_out;
	wire SDA_oen;
	wire SDA_out;
	wire [31:0] int_limit;
	wire int_en;
	wire counter_en;
	wire counter_rst;
	wire [31:0] clk_freq;
	wire SCL;
	
	wire SDA;
	assign SDA = SDA_oen? SDA_out : SDA_in;


	position_peripheral uut (
		.clk(clk), 
		.rst(rst), 
		.SDA_in(SDA_in), 
		.int_o(int_o), 
		.clk_frame(clk_frame), 
		.counter_count(counter_count), 
		.cs(cs), 
		.rd(rd), 
		.wr(wr), 
		.addr(addr), 
		.d_in(d_in), 
		.d_out(d_out), 
		.SDA_oen(SDA_oen), 
		.SDA_out(SDA_out), 
		.SCL(SCL),
		.int_limit(int_limit), 
		.int_en(int_en), 
		.counter_en(counter_en), 
		.counter_rst(counter_rst), 
		.clk_freq(clk_freq)
	);
	
	wire [31:0] mcount;
	reg mcoun_en;
	reg mcoun_rst;
	reg clk_enable;
	
	clk_counter count(
		.clk(clk),
		.en(mcoun_en),
		.rst(mcoun_rst),
		.count(mcount)
	);
	
	clk_counter count2(
		.clk(clk),
		.en(counter_en),
		.rst(counter_rst),
		.count(counter_count)
	);
	
	clk_generator genCLK(
		.clk(clk),
		.en(clk_enable),
		.limit(clk_freq),
		.count(mcount),
		.clk_0(clk_frame)
	);
	
	clk_interruptor intGen(
		.clk(clk),
		.en(int_en),
		.limit(int_limit),
		.count(mcount),
		.int_0(int_o)
	);
	
	initial begin

		clk = 0;
		rst = 1;
		SDA_in = 0;
		cs = 0;
		rd = 0;
		wr = 0;
		addr = 0;
		d_in = 0;
		
		mcoun_en  = 0;
		mcoun_rst = 1;
		clk_enable = 0;


		#100;
		rst = 0;
		mcoun_rst = 0;
		mcoun_en = 1;
		clk_enable = 1;

		#10;
		rd = 1;
		addr = 1;
		cs = 1;
		#50;
		while(d_out!=0)#10;
		rd = 0;
		addr = 0;
		cs = 0;
	end
	
	always #5 clk = !clk;
	
endmodule