data/full_repos/permissive/42434302/ivltests/pr2486350.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr2486350.v:9: Unsupported: Ignoring delay on this delayed statement.\n      #10 ;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/42434302/ivltests/pr2486350.v:10: Unsupported or unknown PLI call: $simtime\n      $display("simtime=%d (%h)", $simtime, $simtime);\n                                  ^~~~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/pr2486350.v:10: Unsupported or unknown PLI call: $simtime\n      $display("simtime=%d (%h)", $simtime, $simtime);\n                                            ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr2486350.v:15: Unsupported: Ignoring delay on this delayed statement.\n      #100 $finish;\n      ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;

   reg a;

   initial begin
      a = 1'b0;
      #10 ;
      $display("simtime=%d (%h)", $simtime, $simtime);
      a = 1'b1;
   end

   initial begin
      #100 $finish;
   end

endmodule
module main;


   reg a;

   initial begin
      a = 1'b0;
      #10 ;
      $display("simtime=%d (%h)", $simtime, $simtime);
      a = 1'b1;
   end

   initial begin
      #100 $finish;
   end

endmodule