data/full_repos/permissive/460468583/data/yosys/gowin/cells_sim.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/460468583/data/yosys/gowin/cells_sim.v:11: Multiple top level modules\n                                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                       : ... Top module \'LUT1\'\nmodule LUT1(output F, input I0);\n       ^~~~\n                                                                                       : ... Top module \'LUT2\'\nmodule LUT2(output F, input I0, I1);\n       ^~~~\n                                                                                       : ... Top module \'LUT3\'\nmodule LUT3(output F, input I0, I1, I2);\n       ^~~~\n                                                                                       : ... Top module \'LUT4\'\nmodule LUT4(output F, input I0, I1, I2, I3);\n       ^~~~\n                                                                                       : ... Top module \'__APICULA_LUT5\'\nmodule __APICULA_LUT5(output F, input I0, I1, I2, I3, M0);\n       ^~~~~~~~~~~~~~\n                                                                                       : ... Top module \'__APICULA_LUT6\'\nmodule __APICULA_LUT6(output F, input I0, I1, I2, I3, M0, M1);\n       ^~~~~~~~~~~~~~\n                                                                                       : ... Top module \'__APICULA_LUT7\'\nmodule __APICULA_LUT7(output F, input I0, I1, I2, I3, M0, M1, M2);\n       ^~~~~~~~~~~~~~\n                                                                                       : ... Top module \'__APICULA_LUT8\'\nmodule __APICULA_LUT8(output F, input I0, I1, I2, I3, M0, M1, M2, M3);\n       ^~~~~~~~~~~~~~\n                                                                                       : ... Top module \'MUX2_LUT5\'\nmodule MUX2_LUT5 (O, I0, I1, S0);\n       ^~~~~~~~~\n                                                                                       : ... Top module \'MUX2_LUT6\'\nmodule MUX2_LUT6 (O, I0, I1, S0);\n       ^~~~~~~~~\n                                                                                       : ... Top module \'MUX2_LUT7\'\nmodule MUX2_LUT7 (O, I0, I1, S0);\n       ^~~~~~~~~\n                                                                                       : ... Top module \'MUX2_LUT8\'\nmodule MUX2_LUT8 (O, I0, I1, S0);\n       ^~~~~~~~~\n                                                                                       : ... Top module \'DFF\'\nmodule DFF (output reg Q, input CLK, D);\n       ^~~\n                                                                                       : ... Top module \'DFFE\'\nmodule DFFE (output reg Q, input D, CLK, CE);\n       ^~~~\n                                                                                       : ... Top module \'DFFS\'\nmodule DFFS (output reg Q, input D, CLK, SET);\n       ^~~~\n                                                                                       : ... Top module \'DFFSE\'\nmodule DFFSE (output reg Q, input D, CLK, CE, SET);\n       ^~~~~\n                                                                                       : ... Top module \'DFFR\'\nmodule DFFR (output reg Q, input D, CLK, RESET);\n       ^~~~\n                                                                                       : ... Top module \'DFFRE\'\nmodule DFFRE (output reg Q, input D, CLK, CE, RESET);\n       ^~~~~\n                                                                                       : ... Top module \'DFFP\'\nmodule DFFP (output reg Q, input D, CLK, PRESET);\n       ^~~~\n                                                                                       : ... Top module \'DFFPE\'\nmodule DFFPE (output reg Q, input D, CLK, CE, PRESET);\n       ^~~~~\n                                                                                       : ... Top module \'DFFC\'\nmodule DFFC (output reg Q, input D, CLK, CLEAR);\n       ^~~~\n                                                                                       : ... Top module \'DFFCE\'\nmodule DFFCE (output reg Q, input D, CLK, CE, CLEAR);\n       ^~~~~\n                                                                                       : ... Top module \'DFFN\'\nmodule DFFN (output reg Q, input CLK, D);\n       ^~~~\n                                                                                       : ... Top module \'DFFNE\'\nmodule DFFNE (output reg Q, input D, CLK, CE);\n       ^~~~~\n                                                                                       : ... Top module \'DFFNS\'\nmodule DFFNS (output reg Q, input D, CLK, SET);\n       ^~~~~\n                                                                                       : ... Top module \'DFFNSE\'\nmodule DFFNSE (output reg Q, input D, CLK, CE, SET);\n       ^~~~~~\n                                                                                       : ... Top module \'DFFNR\'\nmodule DFFNR (output reg Q, input D, CLK, RESET);\n       ^~~~~\n                                                                                       : ... Top module \'DFFNRE\'\nmodule DFFNRE (output reg Q, input D, CLK, CE, RESET);\n       ^~~~~~\n                                                                                       : ... Top module \'DFFNP\'\nmodule DFFNP (output reg Q, input D, CLK, PRESET);\n       ^~~~~\n                                                                                       : ... Top module \'DFFNPE\'\nmodule DFFNPE (output reg Q, input D, CLK, CE, PRESET);\n       ^~~~~~\n                                                                                       : ... Top module \'DFFNC\'\nmodule DFFNC (output reg Q, input D, CLK, CLEAR);\n       ^~~~~\n                                                                                       : ... Top module \'DFFNCE\'\nmodule DFFNCE (output reg Q, input D, CLK, CE, CLEAR);\n       ^~~~~~\n                                                                                       : ... Top module \'VCC\'\nmodule VCC(output V);\n       ^~~\n                                                                                       : ... Top module \'GND\'\nmodule GND(output G);\n       ^~~\n                                                                                       : ... Top module \'IBUF\'\nmodule IBUF(output O, input I);\n       ^~~~\n                                                                                       : ... Top module \'OBUF\'\nmodule OBUF(output O, input I);\n       ^~~~\n                                                                                       : ... Top module \'TBUF\'\nmodule TBUF (O, I, OEN);\n       ^~~~\n                                                                                       : ... Top module \'IOBUF\'\nmodule IOBUF (O, IO, I, OEN);\n       ^~~~~\n                                                                                       : ... Top module \'GSR\'\nmodule GSR (input GSRI);\n       ^~~\n                                                                                       : ... Top module \'ALU\'\nmodule ALU (SUM, COUT, I0, I1, I3, CIN);\n       ^~~\n                                                                                       : ... Top module \'RAM16S4\'\nmodule RAM16S4 (DO, DI, AD, WRE, CLK);\n       ^~~~~~~\n                                                                                       : ... Top module \'SDP\'\nmodule SDP (DO, DI, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCE, RESETA, RESETB);\n       ^~~\n                                                                                       : ... Top module \'rPLL\'\nmodule rPLL (CLKOUT, CLKOUTP, CLKOUTD, CLKOUTD3, LOCK, CLKIN, CLKFB, FBDSEL, IDSEL, ODSEL, DUTYDA, PSDA, FDLY, RESET, RESET_P);\n       ^~~~\n%Error-ASSIGNIN: data/full_repos/permissive/460468583/data/yosys/gowin/cells_sim.v:584: Assigning to input/const variable: \'I\'\n  assign I = IO;\n         ^\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module DFFCE (output reg Q, input D, CLK, CE, CLEAR);
  parameter [0:0] INIT = 1'b0;
  initial Q = INIT;

	specify
		if (CE) (posedge CLK => (Q : D)) = (480, 660);
		(posedge CLEAR => (Q : 1'b0)) = (1800, 2679);
		$setup(D, posedge CLK &&& CE, 576);
		$setup(CE, posedge CLK, 63);
	endspecify

  always @(posedge CLK or posedge CLEAR) begin
    if(CLEAR)
      Q <= 1'b0;
    else if (CE)
      Q <= D;
  end
endmodule
module DFFCE (output reg Q, input D, CLK, CE, CLEAR);

  parameter [0:0] INIT = 1'b0;
  initial Q = INIT;

	specify
		if (CE) (posedge CLK => (Q : D)) = (480, 660);
		(posedge CLEAR => (Q : 1'b0)) = (1800, 2679);
		$setup(D, posedge CLK &&& CE, 576);
		$setup(CE, posedge CLK, 63);
	endspecify

  always @(posedge CLK or posedge CLEAR) begin
    if(CLEAR)
      Q <= 1'b0;
    else if (CE)
      Q <= D;
  end
endmodule