data/full_repos/permissive/431863558/combinational-circuits/basic-arithmetic/full_adder.v
data/verilator_xmls/f87c4f0b-ea5e-4a96-93b5-639e2667fc17.xml
module full_adder ( output S, C,
					input x, y, c);

	assign {C, S} = x + y + c;

endmodule
module full_adder ( output S, C,
					input x, y, c);


	assign {C, S} = x + y + c;

endmodule