data/full_repos/permissive/425529933/Proyecto1Digitales2/clk-generator/probador_clk.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/425529933/Proyecto1Digitales2/clk-generator/probador_clk.v:12: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk_32f = ~clk_32f;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/clk-generator/probador_clk.v:15: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile ("prueba_clk.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/clk-generator/probador_clk.v:16: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/clk-generator/probador_clk.v:19: syntax error, unexpected \'@\'\n  @(posedge clk_32f);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/425529933/Proyecto1Digitales2/clk-generator/probador_clk.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #128 $finish;\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/clk-generator/probador_clk.v:28: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n reg [2:0] checker; \n           ^~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/clk-generator/probador_clk.v:28: syntax error, unexpected \';\', expecting IDENTIFIER or \'=\' or do or final\n reg [2:0] checker; \n                  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/clk-generator/probador_clk.v:30: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  if (clk_4f_c == clk_4f_e) checker[2] = 1;\n                            ^~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/clk-generator/probador_clk.v:30: syntax error, unexpected \'[\'\n  if (clk_4f_c == clk_4f_e) checker[2] = 1;\n                                   ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/clk-generator/probador_clk.v:31: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  else checker[2] = 0;\n       ^~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/clk-generator/probador_clk.v:33: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  if (clk_2f_c == clk_2f_e) checker[1] = 1;\n                            ^~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/clk-generator/probador_clk.v:33: syntax error, unexpected \'[\'\n  if (clk_2f_c == clk_2f_e) checker[1] = 1;\n                                   ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/clk-generator/probador_clk.v:34: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  else checker[1] = 0;\n       ^~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/clk-generator/probador_clk.v:36: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  if (clk_f_c == clk_f_e) checker[0] = 1;\n                          ^~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/clk-generator/probador_clk.v:36: syntax error, unexpected \'[\'\n  if (clk_f_c == clk_f_e) checker[0] = 1;\n                                 ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/clk-generator/probador_clk.v:37: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  else checker[0] = 0;\n       ^~~~~~~\n%Error: Exiting due to 14 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module probador_clk (
	output reg clk_32f,
	output reg reset,
	input clk_4f_c,
	input clk_2f_c,
	input clk_f_c,
	input clk_4f_e,
	input clk_2f_e,
	input clk_f_e
);
	initial clk_32f = 0;
	always #1 clk_32f = ~clk_32f;

	initial begin
		$dumpfile ("prueba_clk.vcd");
		$dumpvars;
		
		reset <= 0;
		@(posedge clk_32f);
		reset <= 1;
		#128 $finish;
	end





	reg [2:0] checker; 
	always @(*) begin
		if (clk_4f_c == clk_4f_e) checker[2] = 1;
		else checker[2] = 0;

		if (clk_2f_c == clk_2f_e) checker[1] = 1;
		else checker[1] = 0;

		if (clk_f_c == clk_f_e) checker[0] = 1;
		else checker[0] = 0;
	end
endmodule
module probador_clk (
	output reg clk_32f,
	output reg reset,
	input clk_4f_c,
	input clk_2f_c,
	input clk_f_c,
	input clk_4f_e,
	input clk_2f_e,
	input clk_f_e
);

	initial clk_32f = 0;
	always #1 clk_32f = ~clk_32f;

	initial begin
		$dumpfile ("prueba_clk.vcd");
		$dumpvars;
		
		reset <= 0;
		@(posedge clk_32f);
		reset <= 1;
		#128 $finish;
	end





	reg [2:0] checker; 
	always @(*) begin
		if (clk_4f_c == clk_4f_e) checker[2] = 1;
		else checker[2] = 0;

		if (clk_2f_c == clk_2f_e) checker[1] = 1;
		else checker[1] = 0;

		if (clk_f_c == clk_f_e) checker[0] = 1;
		else checker[0] = 0;
	end
endmodule