data/full_repos/permissive/476477303/verilog/rtl/ExperiarCore/CSR/CSR_DataRegister.v
data/verilator_xmls/50af18c4-7ee8-49d1-9670-c7eae9646f2f.xml
module CSR_DataRegister #(
		parameter ADDRESS = 12'h000
	)(
		input wire clk,
		input wire rst,


		input wire csrWriteEnable,
		input wire csrReadEnable,
		input wire[11:0] csrAddress,
		input wire[31:0] csrWriteData,
		output wire[31:0] csrReadData,
		output wire csrRequestOutput,


		input wire[31:0] readData,
		output wire readDataEnable,
		output wire[31:0] writeData,
		output wire writeDataEnable
	);
	
	wire csrEnabled = csrAddress == ADDRESS;

	assign csrReadData = csrEnabled && csrReadEnable ? readData : 32'b0;
	assign readDataEnable = csrEnabled && csrReadEnable;
	assign writeData = csrWriteData;
	assign writeDataEnable = csrEnabled && csrWriteEnable;

	assign csrRequestOutput = csrEnabled && csrReadEnable;
	
endmodule
module CSR_DataRegister #(
		parameter ADDRESS = 12'h000
	)(
		input wire clk,
		input wire rst,


		input wire csrWriteEnable,
		input wire csrReadEnable,
		input wire[11:0] csrAddress,
		input wire[31:0] csrWriteData,
		output wire[31:0] csrReadData,
		output wire csrRequestOutput,


		input wire[31:0] readData,
		output wire readDataEnable,
		output wire[31:0] writeData,
		output wire writeDataEnable
	);

	
	wire csrEnabled = csrAddress == ADDRESS;

	assign csrReadData = csrEnabled && csrReadEnable ? readData : 32'b0;
	assign readDataEnable = csrEnabled && csrReadEnable;
	assign writeData = csrWriteData;
	assign writeDataEnable = csrEnabled && csrWriteEnable;

	assign csrRequestOutput = csrEnabled && csrReadEnable;
	
endmodule