data/full_repos/permissive/449370139/verilog_code/L3G4200D_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/449370139/verilog_code/L3G4200D_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #50\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/449370139/verilog_code/L3G4200D_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #50\n    ^\n%Error: data/full_repos/permissive/449370139/verilog_code/L3G4200D_tb.v:33: Cannot find file containing module: \'top\'\ntop t(\n^~~\n        ... Looked in:\n             data/full_repos/permissive/449370139/verilog_code,data/full_repos/permissive/449370139/top\n             data/full_repos/permissive/449370139/verilog_code,data/full_repos/permissive/449370139/top.v\n             data/full_repos/permissive/449370139/verilog_code,data/full_repos/permissive/449370139/top.sv\n             top\n             top.v\n             top.sv\n             obj_dir/top\n             obj_dir/top.v\n             obj_dir/top.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module L3G4200D_tb();
reg clk;
reg rst;
reg ACL_MISO;
wire [5:0]led;
wire ACL_CSN;
wire ACL_MOSI;
wire ACL_SCLK;


top t(

    .clk(clk),
    .rst(rst),
    .led(led),

    .ACL_CSN(ACL_CSN),
    .ACL_MOSI(ACL_MOSI),
    .ACL_MISO(ACL_MISO),
    .ACL_SCLK(ACL_SCLK)
);

initial
begin
    rst=1'b1;
    #50
    rst=1'b0;
    #50
    ACL_MISO=1'b1;
end
endmodule
module L3G4200D_tb();

reg clk;
reg rst;
reg ACL_MISO;
wire [5:0]led;
wire ACL_CSN;
wire ACL_MOSI;
wire ACL_SCLK;


top t(

    .clk(clk),
    .rst(rst),
    .led(led),

    .ACL_CSN(ACL_CSN),
    .ACL_MOSI(ACL_MOSI),
    .ACL_MISO(ACL_MISO),
    .ACL_SCLK(ACL_SCLK)
);

initial
begin
    rst=1'b1;
    #50
    rst=1'b0;
    #50
    ACL_MISO=1'b1;
end
endmodule