data/full_repos/permissive/469195529/sources/hdl/DFlipFlop.v
data/verilator_xmls/a176137b-3919-41e6-9107-67eeac6e8403.xml
module DFlipFlop(
    input D, clk, reset,
    output reg Q
    );
    
    always@(posedge clk) begin
        if(reset) Q <= 0;
        else Q <= D;
    end
endmodule
module DFlipFlop(
    input D, clk, reset,
    output reg Q
    );

    
    always@(posedge clk) begin
        if(reset) Q <= 0;
        else Q <= D;
    end
endmodule