data/full_repos/permissive/500128826/HDLBits/More Verilog Features/Bcdadd100/top_module_tb.v
1: b'%Error: Cannot find file containing module: Verilog\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/More/Verilog\n             data/full_repos/permissive/500128826/HDLBits/More/Verilog.v\n             data/full_repos/permissive/500128826/HDLBits/More/Verilog.sv\n             Verilog\n             Verilog.v\n             Verilog.sv\n             obj_dir/Verilog\n             obj_dir/Verilog.v\n             obj_dir/Verilog.sv\n%Error: Cannot find file containing module: Features/Bcdadd100,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/More\n%Error: Cannot find file containing module: Features/Bcdadd100/top_module_tb.v\n%Error: Exiting due to 4 error(s)\n'
module top_module_tb ();

  wire [399:0] sum;

  reg [399:0] stim_a = 400'h1234567890123456789012345678901234567890;
  reg [399:0] stim_b = 400'h1234567890123456789012345678901234567890;

  localparam ITERATIONS = 8;

  always begin
    #1 stim_a = stim_a + 1;
    stim_b = stim_b + 1;
  end

  top_module uut (
      .a(stim_a),
      .b(stim_b),
      .cin(1'b0),
      .sum(sum),
      .cout()
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule
module top_module_tb ();


  wire [399:0] sum;

  reg [399:0] stim_a = 400'h1234567890123456789012345678901234567890;
  reg [399:0] stim_b = 400'h1234567890123456789012345678901234567890;

  localparam ITERATIONS = 8;

  always begin
    #1 stim_a = stim_a + 1;
    stim_b = stim_b + 1;
  end

  top_module uut (
      .a(stim_a),
      .b(stim_b),
      .cin(1'b0),
      .sum(sum),
      .cout()
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule