data/full_repos/permissive/487568919/basic_verilog/reverse_vector_tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/reverse_vector_tb.sv:16: Unsupported: Ignoring delay on this delayed statement.\n  #0 clk200 = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/reverse_vector_tb.sv:18: Unsupported: Ignoring delay on this delayed statement.\n    #2.5 clk200 = ~clk200;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/reverse_vector_tb.sv:23: Unsupported: Ignoring delay on this delayed statement.\n  #10.2 rst = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/reverse_vector_tb.sv:24: Unsupported: Ignoring delay on this delayed statement.\n  #5 rst = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/reverse_vector_tb.sv:27: Unsupported: Ignoring delay on this delayed statement.\n    #9985 rst = ~rst;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/reverse_vector_tb.sv:28: Unsupported: Ignoring delay on this delayed statement.\n    #5 rst = ~rst;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/reverse_vector_tb.sv:37: Unsupported: Ignoring delay on this delayed statement.\n  #10.2 rst_once = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/reverse_vector_tb.sv:38: Unsupported: Ignoring delay on this delayed statement.\n  #5 rst_once = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/reverse_vector_tb.sv:41: Unsupported: Ignoring delay on this delayed statement.\n  #510.2 rst_once = 1;     \n  ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/reverse_vector_tb.sv:42: Unsupported: Ignoring delay on this delayed statement.\n  #5 rst_once = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/reverse_vector_tb.sv:78: Unsupported: Ignoring delay on this delayed statement.\n  #0 start = 1\'b0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/reverse_vector_tb.sv:79: Unsupported: Ignoring delay on this delayed statement.\n  #100.2 start = 1\'b1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/487568919/basic_verilog/reverse_vector_tb.sv:80: Unsupported: Ignoring delay on this delayed statement.\n  #5 start = 1\'b0;\n  ^\n%Error: data/full_repos/permissive/487568919/basic_verilog/reverse_vector_tb.sv:49: Cannot find file containing module: \'ClkDivider\'\nClkDivider #(\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/487568919/basic_verilog,data/full_repos/permissive/487568919/ClkDivider\n             data/full_repos/permissive/487568919/basic_verilog,data/full_repos/permissive/487568919/ClkDivider.v\n             data/full_repos/permissive/487568919/basic_verilog,data/full_repos/permissive/487568919/ClkDivider.sv\n             ClkDivider\n             ClkDivider.v\n             ClkDivider.sv\n             obj_dir/ClkDivider\n             obj_dir/ClkDivider.v\n             obj_dir/ClkDivider.sv\n%Error: data/full_repos/permissive/487568919/basic_verilog/reverse_vector_tb.sv:58: Cannot find file containing module: \'EdgeDetect\'\nEdgeDetect ED1[31:0] (\n^~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/reverse_vector_tb.sv:68: Cannot find file containing module: \'c_rand\'\nc_rand RNG1 (\n^~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/reverse_vector_tb.sv:87: Cannot find file containing module: \'reverse_vector\'\nreverse_vector #(\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/487568919/basic_verilog/reverse_vector_tb.sv:96: Cannot find file containing module: \'reverse_vector\'\nreverse_vector #(\n^~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module reverse_vector_tb();

logic clk200;
initial begin
  #0 clk200 = 1;
  forever
    #2.5 clk200 = ~clk200;
end

logic rst;
initial begin
  #10.2 rst = 1;
  #5 rst = 0;

  forever begin
    #9985 rst = ~rst;
    #5 rst = ~rst;
  end
end

logic nrst;
assign nrst = ~rst;

logic rst_once;
initial begin
  #10.2 rst_once = 1;
  #5 rst_once = 0;
end
initial begin
  #510.2 rst_once = 1;
  #5 rst_once = 0;
end

logic nrst_once;
assign nrst_once = ~rst_once;

logic [31:0] DerivedClocks;
ClkDivider #(
  .WIDTH( 32 )
) CD1 (
  .clk( clk200 ),
  .nrst( nrst_once ),
  .out( DerivedClocks[31:0] )
);

logic [31:0] E_DerivedClocks;
EdgeDetect ED1[31:0] (
  .clk( {32{clk200}} ),
  .nrst( {32{nrst_once}} ),
  .in( DerivedClocks[31:0] ),
  .rising( E_DerivedClocks[31:0] ),
  .falling(  ),
  .both(  )
);

logic [15:0] RandomNumber1;
c_rand RNG1 (
  .clk( clk200 ),
  .rst( rst_once ),
  .reseed( 1'b0 ),
  .seed_val( DerivedClocks[31:0] ),
  .out( RandomNumber1[15:0] )
);

logic start;
initial begin
  #0 start = 1'b0;
  #100.2 start = 1'b1;
  #5 start = 1'b0;
end




logic [14:0] reversed1;
reverse_vector #(
  .WIDTH( 15 )
) RV1 (
  .in( RandomNumber1[14:0] ),
  .out( reversed1[14:0] )
);


logic [13:0] reversed2;
reverse_vector #(
  .WIDTH( 14 )
) RV2 (
  .in( reversed1[13:0] ),
  .out( reversed2[13:0] )
);

endmodule
module reverse_vector_tb();


logic clk200;
initial begin
  #0 clk200 = 1;
  forever
    #2.5 clk200 = ~clk200;
end

logic rst;
initial begin
  #10.2 rst = 1;
  #5 rst = 0;

  forever begin
    #9985 rst = ~rst;
    #5 rst = ~rst;
  end
end

logic nrst;
assign nrst = ~rst;

logic rst_once;
initial begin
  #10.2 rst_once = 1;
  #5 rst_once = 0;
end
initial begin
  #510.2 rst_once = 1;
  #5 rst_once = 0;
end

logic nrst_once;
assign nrst_once = ~rst_once;

logic [31:0] DerivedClocks;
ClkDivider #(
  .WIDTH( 32 )
) CD1 (
  .clk( clk200 ),
  .nrst( nrst_once ),
  .out( DerivedClocks[31:0] )
);

logic [31:0] E_DerivedClocks;
EdgeDetect ED1[31:0] (
  .clk( {32{clk200}} ),
  .nrst( {32{nrst_once}} ),
  .in( DerivedClocks[31:0] ),
  .rising( E_DerivedClocks[31:0] ),
  .falling(  ),
  .both(  )
);

logic [15:0] RandomNumber1;
c_rand RNG1 (
  .clk( clk200 ),
  .rst( rst_once ),
  .reseed( 1'b0 ),
  .seed_val( DerivedClocks[31:0] ),
  .out( RandomNumber1[15:0] )
);

logic start;
initial begin
  #0 start = 1'b0;
  #100.2 start = 1'b1;
  #5 start = 1'b0;
end




logic [14:0] reversed1;
reverse_vector #(
  .WIDTH( 15 )
) RV1 (
  .in( RandomNumber1[14:0] ),
  .out( reversed1[14:0] )
);


logic [13:0] reversed2;
reverse_vector #(
  .WIDTH( 14 )
) RV2 (
  .in( reversed1[13:0] ),
  .out( reversed2[13:0] )
);

endmodule