data/full_repos/permissive/423270459/verilog/rtl/nco.v
data/verilator_xmls/2fe4aac3-f7a1-4d1a-a629-08455e8230dc.xml
module nco (

    input              clk,
    input              reset_n,
    input       [31:0] t_angle_dat,
    input              t_angle_req,
    output             t_angle_ack,
    output      [31:0] i_nco_dat,
    output             i_nco_req,
    input              i_nco_ack
);

wire      [31:0] dat0, dat0_nxt;
wire      [67:0] dat1, dat1_nxt;
wire      [67:0] dat2, dat2_nxt;
wire      [67:0] dat3, dat3_nxt;
wire      [67:0] dat4, dat4_nxt;
wire      [67:0] dat5, dat5_nxt;
wire      [67:0] dat6, dat6_nxt;
wire      [67:0] dat7, dat7_nxt;
wire      [67:0] dat8, dat8_nxt;
wire      [31:0] dat9;


assign dat0_nxt = t_angle_dat;






reg [31:0] ncolut;

always @*
casez (node1_addr)
0 : ncolut = {16'd3215, 16'd65453};
1 : ncolut = {16'd9615, 16'd64823};
2 : ncolut = {16'd15923, 16'd63568};
3 : ncolut = {16'd22077, 16'd61702};
4 : ncolut = {16'd28018, 16'd59241};
5 : ncolut = {16'd33690, 16'd56209};
6 : ncolut = {16'd39037, 16'd52636};
7 : ncolut = {16'd44009, 16'd48556};
endcase

wire [31:0] node1_angle;
wire [2:0] node1_phase;
wire [2:0] node1_addr;
wire [17:0] node1_reSwap;
wire [17:0] node1_imSwap;


assign node1_angle = dat0;
assign node1_phase = node1_angle[31:29];
assign node1_addr = node1_phase[0]?~node1_angle[28:26]:node1_angle[28:26];

assign node1_reSwap[17:16]=2'b0;
assign node1_imSwap[17:16]=2'b0;
assign node1_reSwap[15:0] = node1_phase[0]^node1_phase[1] ? ncolut[31:16]:ncolut[15:0];
assign node1_imSwap[15:0] = node1_phase[0]^node1_phase[1] ? ncolut[15:0]:ncolut[31:16];

assign dat1_nxt[17:0] = node1_phase[2]^node1_phase[1]?~node1_reSwap:node1_reSwap;
assign dat1_nxt[35:18] = node1_phase[2]?~node1_imSwap:node1_imSwap;
assign dat1_nxt[61:36] = node1_angle[25:0];






wire [25:0] beta0;
wire [25:0] beta_calc0;
wire [17:0] re0,im0,re_shift0,im_shift0;


assign  beta0 = dat1[25:0];

assign re0=dat1[17:0];
assign im0=dat1[35:18];




assign re_shift0=$signed(re0) >> 5;
assign im_shift0=$signed(im0) >> 5;

assign beta_calc0 = beta0[25]?beta0+20:beta0-20;
assign dat2_nxt[17:0] = beta0[25]?re0-im_shift0 : re0+im_shift0;
assign dat2_nxt[35:18] = beta0[25]?im0+re_shift0 : im0-re_shift0;
assign dat2_nxt[61:36] = beta_calc0;







wire [25:0] beta1;
wire [25:0] beta_calc1;
wire [17:0] re1,im1,re_shift1,im_shift1;


assign  beta1 = dat2[25:0];

assign re1=dat2[17:0];
assign im1=dat2[35:18];




assign re_shift1=$signed(re1) >> 6;
assign im_shift1=$signed(im1) >> 6;

assign beta_calc1 = beta1[25]?beta1+10:beta1-10;
assign dat3_nxt[17:0] = beta1[25]?re1-im_shift1 : re1+im_shift1;
assign dat3_nxt[35:18] = beta1[25]?im1+re_shift1 : im1-re_shift1;
assign dat3_nxt[61:36] = beta_calc1;







wire [25:0] beta2;
wire [25:0] beta_calc2;
wire [17:0] re2,im2,re_shift2,im_shift2;


assign  beta2 = dat3[25:0];

assign re2=dat3[17:0];
assign im2=dat3[35:18];




assign re_shift2=$signed(re2) >> 7;
assign im_shift2=$signed(im2) >> 7;

assign beta_calc2 = beta2[25]?beta2+5:beta2-5;
assign dat4_nxt[17:0] = beta2[25]?re2-im_shift2 : re2+im_shift2;
assign dat4_nxt[35:18] = beta2[25]?im2+re_shift2 : im2-re_shift2;
assign dat4_nxt[61:36] = beta_calc2;







wire [25:0] beta3;
wire [25:0] beta_calc3;
wire [17:0] re3,im3,re_shift3,im_shift3;


assign  beta3 = dat4[25:0];

assign re3=dat4[17:0];
assign im3=dat4[35:18];




assign re_shift3=$signed(re3) >> 8;
assign im_shift3=$signed(im3) >> 8;

assign beta_calc3 = beta3[25]?beta3+3:beta3-3;
assign dat5_nxt[17:0] = beta3[25]?re3-im_shift3 : re3+im_shift3;
assign dat5_nxt[35:18] = beta3[25]?im3+re_shift3 : im3-re_shift3;
assign dat5_nxt[61:36] = beta_calc3;







wire [25:0] beta4;
wire [25:0] beta_calc4;
wire [17:0] re4,im4,re_shift4,im_shift4;


assign  beta4 = dat5[25:0];

assign re4=dat5[17:0];
assign im4=dat5[35:18];




assign re_shift4=$signed(re4) >> 9;
assign im_shift4=$signed(im4) >> 9;

assign beta_calc4 = beta4[25]?beta4+1:beta4-1;
assign dat6_nxt[17:0] = beta4[25]?re4-im_shift4 : re4+im_shift4;
assign dat6_nxt[35:18] = beta4[25]?im4+re_shift4 : im4-re_shift4;
assign dat6_nxt[61:36] = beta_calc4;







wire [25:0] beta5;
wire [25:0] beta_calc5;
wire [17:0] re5,im5,re_shift5,im_shift5;


assign  beta5 = dat6[25:0];

assign re5=dat6[17:0];
assign im5=dat6[35:18];




assign re_shift5=$signed(re5) >> 10;
assign im_shift5=$signed(im5) >> 10;

assign beta_calc5 = beta5[25]?beta5+1:beta5-1;
assign dat7_nxt[17:0] = beta5[25]?re5-im_shift5 : re5+im_shift5;
assign dat7_nxt[35:18] = beta5[25]?im5+re_shift5 : im5-re_shift5;
assign dat7_nxt[61:36] = beta_calc5;







wire [25:0] beta6;
wire [25:0] beta_calc6;
wire [17:0] re6,im6,re_shift6,im_shift6;


assign  beta6 = dat7[25:0];

assign re6=dat7[17:0];
assign im6=dat7[35:18];




assign re_shift6=$signed(re6) >> 11;
assign im_shift6=$signed(im6) >> 11;

assign beta_calc6 = beta6[25]?beta6+0:beta6-0;
assign dat8_nxt[17:0] = beta6[25]?re6-im_shift6 : re6+im_shift6;
assign dat8_nxt[35:18] = beta6[25]?im6+re_shift6 : im6-re_shift6;
assign dat8_nxt[61:36] = beta_calc6;




wire [17:0] recalc9,imcalc9;
wire [15:0] redata9,imdata9;

assign recalc9=dat8[17:0];
assign imcalc9=dat8[35:18];

assign dat9[15:0]=^recalc9[17:16]?{recalc9[17],{15{~recalc9[17]}}}:{recalc9[17],recalc9[15:1]};

assign dat9[31:16]=^imcalc9[17:16]?{imcalc9[17],{15{~imcalc9[17]}}}:{imcalc9[17],imcalc9[15:1]};

assign redata9 = dat9[15:0];
assign imdata9 = dat9[31:16];



assign i_nco_dat = dat9;




wire en0;
reg [31:0] dat0_r;
always @(posedge clk) if (en0) dat0_r <= dat0_nxt;
assign dat0 = dat0_r;



wire en1;
reg [67:0] dat1_r;
always @(posedge clk) if (en1) dat1_r <= dat1_nxt;
assign dat1 = dat1_r;



wire en2;
reg [67:0] dat2_r;
always @(posedge clk) if (en2) dat2_r <= dat2_nxt;
assign dat2 = dat2_r;



wire en3;
reg [67:0] dat3_r;
always @(posedge clk) if (en3) dat3_r <= dat3_nxt;
assign dat3 = dat3_r;



wire en4;
reg [67:0] dat4_r;
always @(posedge clk) if (en4) dat4_r <= dat4_nxt;
assign dat4 = dat4_r;



wire en5;
reg [67:0] dat5_r;
always @(posedge clk) if (en5) dat5_r <= dat5_nxt;
assign dat5 = dat5_r;



wire en6;
reg [67:0] dat6_r;
always @(posedge clk) if (en6) dat6_r <= dat6_nxt;
assign dat6 = dat6_r;



wire en7;
reg [67:0] dat7_r;
always @(posedge clk) if (en7) dat7_r <= dat7_nxt;
assign dat7 = dat7_r;



wire en8;
reg [67:0] dat8_r;
always @(posedge clk) if (en8) dat8_r <= dat8_nxt;
assign dat8 = dat8_r;




nco_ctrl uctrl (
    .clk(clk),
    .reset_n(reset_n),
    .t_angle_req(t_angle_req),
    .t_angle_ack(t_angle_ack),
    .i_nco_req(i_nco_req),
    .i_nco_ack(i_nco_ack),
    .en0(en0),
    .en1(en1),
    .en2(en2),
    .en3(en3),
    .en4(en4),
    .en5(en5),
    .en6(en6),
    .en7(en7),
    .en8(en8)
);
endmodule
module nco (

    input              clk,
    input              reset_n,
    input       [31:0] t_angle_dat,
    input              t_angle_req,
    output             t_angle_ack,
    output      [31:0] i_nco_dat,
    output             i_nco_req,
    input              i_nco_ack
);


wire      [31:0] dat0, dat0_nxt;
wire      [67:0] dat1, dat1_nxt;
wire      [67:0] dat2, dat2_nxt;
wire      [67:0] dat3, dat3_nxt;
wire      [67:0] dat4, dat4_nxt;
wire      [67:0] dat5, dat5_nxt;
wire      [67:0] dat6, dat6_nxt;
wire      [67:0] dat7, dat7_nxt;
wire      [67:0] dat8, dat8_nxt;
wire      [31:0] dat9;


assign dat0_nxt = t_angle_dat;






reg [31:0] ncolut;

always @*
casez (node1_addr)
0 : ncolut = {16'd3215, 16'd65453};
1 : ncolut = {16'd9615, 16'd64823};
2 : ncolut = {16'd15923, 16'd63568};
3 : ncolut = {16'd22077, 16'd61702};
4 : ncolut = {16'd28018, 16'd59241};
5 : ncolut = {16'd33690, 16'd56209};
6 : ncolut = {16'd39037, 16'd52636};
7 : ncolut = {16'd44009, 16'd48556};
endcase

wire [31:0] node1_angle;
wire [2:0] node1_phase;
wire [2:0] node1_addr;
wire [17:0] node1_reSwap;
wire [17:0] node1_imSwap;


assign node1_angle = dat0;
assign node1_phase = node1_angle[31:29];
assign node1_addr = node1_phase[0]?~node1_angle[28:26]:node1_angle[28:26];

assign node1_reSwap[17:16]=2'b0;
assign node1_imSwap[17:16]=2'b0;
assign node1_reSwap[15:0] = node1_phase[0]^node1_phase[1] ? ncolut[31:16]:ncolut[15:0];
assign node1_imSwap[15:0] = node1_phase[0]^node1_phase[1] ? ncolut[15:0]:ncolut[31:16];

assign dat1_nxt[17:0] = node1_phase[2]^node1_phase[1]?~node1_reSwap:node1_reSwap;
assign dat1_nxt[35:18] = node1_phase[2]?~node1_imSwap:node1_imSwap;
assign dat1_nxt[61:36] = node1_angle[25:0];






wire [25:0] beta0;
wire [25:0] beta_calc0;
wire [17:0] re0,im0,re_shift0,im_shift0;


assign  beta0 = dat1[25:0];

assign re0=dat1[17:0];
assign im0=dat1[35:18];




assign re_shift0=$signed(re0) >> 5;
assign im_shift0=$signed(im0) >> 5;

assign beta_calc0 = beta0[25]?beta0+20:beta0-20;
assign dat2_nxt[17:0] = beta0[25]?re0-im_shift0 : re0+im_shift0;
assign dat2_nxt[35:18] = beta0[25]?im0+re_shift0 : im0-re_shift0;
assign dat2_nxt[61:36] = beta_calc0;







wire [25:0] beta1;
wire [25:0] beta_calc1;
wire [17:0] re1,im1,re_shift1,im_shift1;


assign  beta1 = dat2[25:0];

assign re1=dat2[17:0];
assign im1=dat2[35:18];




assign re_shift1=$signed(re1) >> 6;
assign im_shift1=$signed(im1) >> 6;

assign beta_calc1 = beta1[25]?beta1+10:beta1-10;
assign dat3_nxt[17:0] = beta1[25]?re1-im_shift1 : re1+im_shift1;
assign dat3_nxt[35:18] = beta1[25]?im1+re_shift1 : im1-re_shift1;
assign dat3_nxt[61:36] = beta_calc1;







wire [25:0] beta2;
wire [25:0] beta_calc2;
wire [17:0] re2,im2,re_shift2,im_shift2;


assign  beta2 = dat3[25:0];

assign re2=dat3[17:0];
assign im2=dat3[35:18];




assign re_shift2=$signed(re2) >> 7;
assign im_shift2=$signed(im2) >> 7;

assign beta_calc2 = beta2[25]?beta2+5:beta2-5;
assign dat4_nxt[17:0] = beta2[25]?re2-im_shift2 : re2+im_shift2;
assign dat4_nxt[35:18] = beta2[25]?im2+re_shift2 : im2-re_shift2;
assign dat4_nxt[61:36] = beta_calc2;







wire [25:0] beta3;
wire [25:0] beta_calc3;
wire [17:0] re3,im3,re_shift3,im_shift3;


assign  beta3 = dat4[25:0];

assign re3=dat4[17:0];
assign im3=dat4[35:18];




assign re_shift3=$signed(re3) >> 8;
assign im_shift3=$signed(im3) >> 8;

assign beta_calc3 = beta3[25]?beta3+3:beta3-3;
assign dat5_nxt[17:0] = beta3[25]?re3-im_shift3 : re3+im_shift3;
assign dat5_nxt[35:18] = beta3[25]?im3+re_shift3 : im3-re_shift3;
assign dat5_nxt[61:36] = beta_calc3;







wire [25:0] beta4;
wire [25:0] beta_calc4;
wire [17:0] re4,im4,re_shift4,im_shift4;


assign  beta4 = dat5[25:0];

assign re4=dat5[17:0];
assign im4=dat5[35:18];




assign re_shift4=$signed(re4) >> 9;
assign im_shift4=$signed(im4) >> 9;

assign beta_calc4 = beta4[25]?beta4+1:beta4-1;
assign dat6_nxt[17:0] = beta4[25]?re4-im_shift4 : re4+im_shift4;
assign dat6_nxt[35:18] = beta4[25]?im4+re_shift4 : im4-re_shift4;
assign dat6_nxt[61:36] = beta_calc4;







wire [25:0] beta5;
wire [25:0] beta_calc5;
wire [17:0] re5,im5,re_shift5,im_shift5;


assign  beta5 = dat6[25:0];

assign re5=dat6[17:0];
assign im5=dat6[35:18];




assign re_shift5=$signed(re5) >> 10;
assign im_shift5=$signed(im5) >> 10;

assign beta_calc5 = beta5[25]?beta5+1:beta5-1;
assign dat7_nxt[17:0] = beta5[25]?re5-im_shift5 : re5+im_shift5;
assign dat7_nxt[35:18] = beta5[25]?im5+re_shift5 : im5-re_shift5;
assign dat7_nxt[61:36] = beta_calc5;







wire [25:0] beta6;
wire [25:0] beta_calc6;
wire [17:0] re6,im6,re_shift6,im_shift6;


assign  beta6 = dat7[25:0];

assign re6=dat7[17:0];
assign im6=dat7[35:18];




assign re_shift6=$signed(re6) >> 11;
assign im_shift6=$signed(im6) >> 11;

assign beta_calc6 = beta6[25]?beta6+0:beta6-0;
assign dat8_nxt[17:0] = beta6[25]?re6-im_shift6 : re6+im_shift6;
assign dat8_nxt[35:18] = beta6[25]?im6+re_shift6 : im6-re_shift6;
assign dat8_nxt[61:36] = beta_calc6;




wire [17:0] recalc9,imcalc9;
wire [15:0] redata9,imdata9;

assign recalc9=dat8[17:0];
assign imcalc9=dat8[35:18];

assign dat9[15:0]=^recalc9[17:16]?{recalc9[17],{15{~recalc9[17]}}}:{recalc9[17],recalc9[15:1]};

assign dat9[31:16]=^imcalc9[17:16]?{imcalc9[17],{15{~imcalc9[17]}}}:{imcalc9[17],imcalc9[15:1]};

assign redata9 = dat9[15:0];
assign imdata9 = dat9[31:16];



assign i_nco_dat = dat9;




wire en0;
reg [31:0] dat0_r;
always @(posedge clk) if (en0) dat0_r <= dat0_nxt;
assign dat0 = dat0_r;



wire en1;
reg [67:0] dat1_r;
always @(posedge clk) if (en1) dat1_r <= dat1_nxt;
assign dat1 = dat1_r;



wire en2;
reg [67:0] dat2_r;
always @(posedge clk) if (en2) dat2_r <= dat2_nxt;
assign dat2 = dat2_r;



wire en3;
reg [67:0] dat3_r;
always @(posedge clk) if (en3) dat3_r <= dat3_nxt;
assign dat3 = dat3_r;



wire en4;
reg [67:0] dat4_r;
always @(posedge clk) if (en4) dat4_r <= dat4_nxt;
assign dat4 = dat4_r;



wire en5;
reg [67:0] dat5_r;
always @(posedge clk) if (en5) dat5_r <= dat5_nxt;
assign dat5 = dat5_r;



wire en6;
reg [67:0] dat6_r;
always @(posedge clk) if (en6) dat6_r <= dat6_nxt;
assign dat6 = dat6_r;



wire en7;
reg [67:0] dat7_r;
always @(posedge clk) if (en7) dat7_r <= dat7_nxt;
assign dat7 = dat7_r;



wire en8;
reg [67:0] dat8_r;
always @(posedge clk) if (en8) dat8_r <= dat8_nxt;
assign dat8 = dat8_r;




nco_ctrl uctrl (
    .clk(clk),
    .reset_n(reset_n),
    .t_angle_req(t_angle_req),
    .t_angle_ack(t_angle_ack),
    .i_nco_req(i_nco_req),
    .i_nco_ack(i_nco_ack),
    .en0(en0),
    .en1(en1),
    .en2(en2),
    .en3(en3),
    .en4(en4),
    .en5(en5),
    .en6(en6),
    .en7(en7),
    .en8(en8)
);
endmodule