data/full_repos/permissive/449521261/parallel_to_UART.v
1: b'%Warning-WIDTH: data/full_repos/permissive/449521261/parallel_to_UART.v:216: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'clock_divider\' generates 11 bits.\n                                                                           : ... In instance parallel_to_UART.serial_clock\n            end else if(clock_divider == max_counter) begin\n                                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/449521261/parallel_to_UART.v:214: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'clock_divider\' generates 11 bits.\n                                                                           : ... In instance parallel_to_UART.serial_clock\n            if(clock_divider == max_counter/2) begin\n                             ^~\n%Error: Exiting due to 2 warning(s)\n'
module parallel_to_UART(
    input reset,
    input clock,
    input [7:0] data,
    input data_ready,
    output serial_out,
    output ready
    );



    parameter input_clock_frequency = 100000;


    parameter baud_rate = 115200;




    localparam clock_divider_max_counter = input_clock_frequency * 1000 / baud_rate;


    wire internal_clock;


    clock_divider # (
        .max_counter (clock_divider_max_counter)
    ) serial_clock (
        .reset(reset),
        .input_clock(clock),
        .output_clock(internal_clock)
    );


    wire done_sending;


    wire [3:0] bit_to_send;


    wire [7:0] latched_data;


    wire counter_enable;

    assign ready = !counter_enable;



    SR_latch latch_data (
        .set(data_ready),
        .reset(done_sending | reset),
        .Q(counter_enable)
    );


    data_latch data_latch_circuit(
        .clock(data_ready),
        .reset(reset),
        .enable(!counter_enable),
        .data_input(data),
        .data_output(latched_data)
    );



    assign done_sending = (bit_to_send == 'd11);


    binary_counter_4_bit bit_to_send_counter(
        .reset(reset | done_sending),
        .clock(internal_clock),
        .enable(counter_enable),
        .count(bit_to_send)
    );


    mux_4_bit data_out_mux(
        .data_input_0(1'b1),
        .data_input_1(1'b0),
        .data_input_2(data[0]),
        .data_input_3(data[1]),
        .data_input_4(data[2]),
        .data_input_5(data[3]),
        .data_input_6(data[4]),
        .data_input_7(data[5]),
        .data_input_8(data[6]),
        .data_input_9(data[7]),
        .data_input_10(1'b1),
        .data_input_11(1'b1),
        .select(bit_to_send),
        .mux_output(serial_out)
    );
endmodule
module parallel_to_UART(
    input reset,
    input clock,
    input [7:0] data,
    input data_ready,
    output serial_out,
    output ready
    );




    parameter input_clock_frequency = 100000;


    parameter baud_rate = 115200;




    localparam clock_divider_max_counter = input_clock_frequency * 1000 / baud_rate;


    wire internal_clock;


    clock_divider # (
        .max_counter (clock_divider_max_counter)
    ) serial_clock (
        .reset(reset),
        .input_clock(clock),
        .output_clock(internal_clock)
    );


    wire done_sending;


    wire [3:0] bit_to_send;


    wire [7:0] latched_data;


    wire counter_enable;

    assign ready = !counter_enable;



    SR_latch latch_data (
        .set(data_ready),
        .reset(done_sending | reset),
        .Q(counter_enable)
    );


    data_latch data_latch_circuit(
        .clock(data_ready),
        .reset(reset),
        .enable(!counter_enable),
        .data_input(data),
        .data_output(latched_data)
    );



    assign done_sending = (bit_to_send == 'd11);


    binary_counter_4_bit bit_to_send_counter(
        .reset(reset | done_sending),
        .clock(internal_clock),
        .enable(counter_enable),
        .count(bit_to_send)
    );


    mux_4_bit data_out_mux(
        .data_input_0(1'b1),
        .data_input_1(1'b0),
        .data_input_2(data[0]),
        .data_input_3(data[1]),
        .data_input_4(data[2]),
        .data_input_5(data[3]),
        .data_input_6(data[4]),
        .data_input_7(data[5]),
        .data_input_8(data[6]),
        .data_input_9(data[7]),
        .data_input_10(1'b1),
        .data_input_11(1'b1),
        .select(bit_to_send),
        .mux_output(serial_out)
    );
endmodule