data/full_repos/permissive/459421171/Pipelined/memory_testbench.v
1: b'%Error: data/full_repos/permissive/459421171/Pipelined/memory_testbench.v:14: Unsupported or unknown PLI call: $monitor\n            $monitor ($time ,"clk=%d, icode=%d,valA=%d,valE=%d,valP=%d,valM=%d,data_memory_error=%d",clk,icode,valA,valE,valP,valM,data_memory_error);\n            ^~~~~~~~\n%Error: data/full_repos/permissive/459421171/Pipelined/memory_testbench.v:15: Unsupported or unknown PLI call: $dumpfile\n            $dumpfile ("memory_test.vcd");\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/459421171/Pipelined/memory_testbench.v:16: Unsupported or unknown PLI call: $dumpvars\n            $dumpvars (0,memory_test);  \n            ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/memory_testbench.v:18: Unsupported: Ignoring delay on this delayed statement.\n            #5clk=1;icode=4\'b0100;valA=64\'d30;valE=-64\'d50;valP=64\'d70; \n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/459421171/Pipelined/memory_testbench.v:19: Unsupported: Ignoring delay on this delayed statement.\n            #5clk=1;icode=4\'b1001;valA=64\'d50;\n            ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module memory_test;
    memory DUT(.clk(clk),.icode(icode),.valA(valA),.valE(valE),.valP(valP),
               .valM(valM),.data_memory_error(data_memory_error));
    reg  clk;
    reg [3:0] icode;
    reg signed [63:0] valA;
    reg signed [63:0] valE;
    reg signed [63:0] valP;

    wire [63:0] valM;
    wire data_memory_error;
    initial
        begin
            $monitor ($time ,"clk=%d, icode=%d,valA=%d,valE=%d,valP=%d,valM=%d,data_memory_error=%d",clk,icode,valA,valE,valP,valM,data_memory_error);
            $dumpfile ("memory_test.vcd");
            $dumpvars (0,memory_test);  
            clk=1;icode=4'b0100;valA=64'd20;valE=64'd50;valP=64'd70; 
            #5clk=1;icode=4'b0100;valA=64'd30;valE=-64'd50;valP=64'd70; 
            #5clk=1;icode=4'b1001;valA=64'd50;
        end
endmodule
module memory_test;

    memory DUT(.clk(clk),.icode(icode),.valA(valA),.valE(valE),.valP(valP),
               .valM(valM),.data_memory_error(data_memory_error));
    reg  clk;
    reg [3:0] icode;
    reg signed [63:0] valA;
    reg signed [63:0] valE;
    reg signed [63:0] valP;

    wire [63:0] valM;
    wire data_memory_error;
    initial
        begin
            $monitor ($time ,"clk=%d, icode=%d,valA=%d,valE=%d,valP=%d,valM=%d,data_memory_error=%d",clk,icode,valA,valE,valP,valM,data_memory_error);
            $dumpfile ("memory_test.vcd");
            $dumpvars (0,memory_test);  
            clk=1;icode=4'b0100;valA=64'd20;valE=64'd50;valP=64'd70; 
            #5clk=1;icode=4'b0100;valA=64'd30;valE=-64'd50;valP=64'd70; 
            #5clk=1;icode=4'b1001;valA=64'd50;
        end
endmodule