data/full_repos/permissive/500128826/HDLBits/Modules/Module_shift8/top_module_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/500128826/HDLBits/Modules/Module_shift8/top_module_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/500128826/HDLBits/Modules/Module_shift8/top_module_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #5 d = d + 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/500128826/HDLBits/Modules/Module_shift8/top_module_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #15;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/500128826/HDLBits/Modules/Module_shift8/top_module_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n    #2560 sel = sel + 1;\n    ^\n%Error: data/full_repos/permissive/500128826/HDLBits/Modules/Module_shift8/top_module_tb.v:45: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("top_module_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/500128826/HDLBits/Modules/Module_shift8/top_module_tb.v:46: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, top_module_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/500128826/HDLBits/Modules/Module_shift8/top_module_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #(ITERATIONS) $display("Done simulating.");\n    ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_module_tb ();

  reg clk = 0;

  reg [7:0] d = 8'd0;
  reg [1:0] sel = 2'd0;
  wire [7:0] q;

  reg [2:0] stim_a = 2'd0;
  reg [2:0] stim_b = 2'd0;

  localparam ITERATIONS = 10240;

  always begin
    clk = clk + 1;
    #10;
  end

  always begin
    #5 d = d + 1;
    #15;
  end

  always begin
    #2560 sel = sel + 1;
  end

  top_module uut (
      .clk(clk),
      .d  (d),
      .sel(sel),
      .q  (q)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule
module top_module_tb ();


  reg clk = 0;

  reg [7:0] d = 8'd0;
  reg [1:0] sel = 2'd0;
  wire [7:0] q;

  reg [2:0] stim_a = 2'd0;
  reg [2:0] stim_b = 2'd0;

  localparam ITERATIONS = 10240;

  always begin
    clk = clk + 1;
    #10;
  end

  always begin
    #5 d = d + 1;
    #15;
  end

  always begin
    #2560 sel = sel + 1;
  end

  top_module uut (
      .clk(clk),
      .d  (d),
      .sel(sel),
      .q  (q)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule