data/full_repos/permissive/413345709/Project/vertical_counter.v
data/verilator_xmls/75c9d6c6-6b78-4c63-9172-e3849b5c6a0e.xml
module VerticalCnt(vga_clk, reset, VcntEnable, VcntValue);
input vga_clk, reset, VcntEnable;
output reg [8:0] VcntValue=0;

always @(posedge vga_clk or posedge reset) 
begin
	if (reset) 
	begin
	VcntValue <= 0;
	end
	else
		begin
		 if(VcntEnable == 1'b1)
			  begin
				if(VcntValue < 449)
					begin
					 VcntValue <= VcntValue + 1;
					end
				else
					begin
					 VcntValue <= 0;
					end
				end
		end
end
endmodule
module VerticalCnt(vga_clk, reset, VcntEnable, VcntValue);

input vga_clk, reset, VcntEnable;
output reg [8:0] VcntValue=0;

always @(posedge vga_clk or posedge reset) 
begin
	if (reset) 
	begin
	VcntValue <= 0;
	end
	else
		begin
		 if(VcntEnable == 1'b1)
			  begin
				if(VcntValue < 449)
					begin
					 VcntValue <= VcntValue + 1;
					end
				else
					begin
					 VcntValue <= 0;
					end
				end
		end
end
endmodule