data/full_repos/permissive/528912093/Proiect/Vsm-AccumulatorB.v
1: b'%Error: data/full_repos/permissive/528912093/Proiect/Vsm-AccumulatorB.v:19: syntax error, unexpected always\nalways\n^~~~~~\n%Error: Exiting due to 1 error(s)\n'
module VsmAccumulatorB( kbd1[1],kbd1[2],kbd1[3],kbd1[4],ClearB,LatchB,MainClk,AluB3,
 AluB0,AluB2,AluB1);
 input kbd1[1],kbd1[2],kbd1[3],kbd1[4],ClearB,LatchB,MainClk;
 output AluB3,AluB0,AluB2,AluB1;
 wire w7,w10,w12,w14,w16,w18;
 not #(3) inv_1(w7,ClearB);
 and #(5) and2_2(w10,MainClk,LatchB);
 dreg #(4) dreg_3(AluB0,w12,kbd1[1],w7,w10);
 dreg #(4) dreg_4(AluB1,w14,kbd1[2],w7,w10);
 dreg #(4) dreg_5(AluB2,w16,kbd1[3],w7,w10);
 dreg #(4) dreg_6(AluB3,w18,kbd1[4],w7,w10);
endmodule
module VsmAccumulatorB( kbd1[1],kbd1[2],kbd1[3],kbd1[4],ClearB,LatchB,MainClk,AluB3,
 AluB0,AluB2,AluB1);

 input kbd1[1],kbd1[2],kbd1[3],kbd1[4],ClearB,LatchB,MainClk;
 output AluB3,AluB0,AluB2,AluB1;
 wire w7,w10,w12,w14,w16,w18;
 not #(3) inv_1(w7,ClearB);
 and #(5) and2_2(w10,MainClk,LatchB);
 dreg #(4) dreg_3(AluB0,w12,kbd1[1],w7,w10);
 dreg #(4) dreg_4(AluB1,w14,kbd1[2],w7,w10);
 dreg #(4) dreg_5(AluB2,w16,kbd1[3],w7,w10);
 dreg #(4) dreg_6(AluB3,w18,kbd1[4],w7,w10);
endmodule