data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/pmu/rtl/pa_hpcp_event.v
1: b"%Error: data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/pmu/rtl/pa_hpcp_event.v:58: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_gated_clk (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/pmu/rtl,data/full_repos/permissive/418753455/gated_clk_cell\n             data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/pmu/rtl,data/full_repos/permissive/418753455/gated_clk_cell.v\n             data/full_repos/permissive/418753455/E906_RTL_FACTORY/gen_rtl/pmu/rtl,data/full_repos/permissive/418753455/gated_clk_cell.sv\n             gated_clk_cell\n             gated_clk_cell.v\n             gated_clk_cell.sv\n             obj_dir/gated_clk_cell\n             obj_dir/gated_clk_cell.v\n             obj_dir/gated_clk_cell.sv\n%Error: Exiting due to 1 error(s)\n"
module pa_hpcp_event(
  clk_en,
  cnt_output,
  cnt_wen,
  cp0_hpcp_icg_en,
  cpurst_b,
  forever_cpuclk,
  hpcp_wdata,
  pad_yy_icg_scan_en
);


input           clk_en;            
input           cnt_wen;           
input           cp0_hpcp_icg_en;   
input           cpurst_b;          
input           forever_cpuclk;    
input   [31:0]  hpcp_wdata;        
input           pad_yy_icg_scan_en; 
output  [31:0]  cnt_output;        


reg     [4 :0]  counter;           


wire            clk_en;            
wire            cnt_clk;           
wire    [31:0]  cnt_output;        
wire            cnt_wen;           
wire            cp0_hpcp_icg_en;   
wire            cpurst_b;          
wire            forever_cpuclk;    
wire    [31:0]  hpcp_wdata;        
wire            pad_yy_icg_scan_en; 







gated_clk_cell  x_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (cnt_clk           ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (clk_en            ),
  .module_en          (cp0_hpcp_icg_en   ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);











always @(posedge cnt_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    counter[4:0] <= 5'b0;
  else if(cnt_wen)
    counter[4:0] <= hpcp_wdata[4:0];
  else
    counter[4:0] <= counter[4:0];
end


assign cnt_output[31:0] = {27'b0, counter[4:0]};


endmodule
module pa_hpcp_event(
  clk_en,
  cnt_output,
  cnt_wen,
  cp0_hpcp_icg_en,
  cpurst_b,
  forever_cpuclk,
  hpcp_wdata,
  pad_yy_icg_scan_en
);



input           clk_en;            
input           cnt_wen;           
input           cp0_hpcp_icg_en;   
input           cpurst_b;          
input           forever_cpuclk;    
input   [31:0]  hpcp_wdata;        
input           pad_yy_icg_scan_en; 
output  [31:0]  cnt_output;        


reg     [4 :0]  counter;           


wire            clk_en;            
wire            cnt_clk;           
wire    [31:0]  cnt_output;        
wire            cnt_wen;           
wire            cp0_hpcp_icg_en;   
wire            cpurst_b;          
wire            forever_cpuclk;    
wire    [31:0]  hpcp_wdata;        
wire            pad_yy_icg_scan_en; 







gated_clk_cell  x_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (cnt_clk           ),
  .external_en        (1'b0              ),
  .global_en          (1'b1              ),
  .local_en           (clk_en            ),
  .module_en          (cp0_hpcp_icg_en   ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);











always @(posedge cnt_clk or negedge cpurst_b)
begin
  if(!cpurst_b)
    counter[4:0] <= 5'b0;
  else if(cnt_wen)
    counter[4:0] <= hpcp_wdata[4:0];
  else
    counter[4:0] <= counter[4:0];
end


assign cnt_output[31:0] = {27'b0, counter[4:0]};


endmodule