data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro/ffclkconvx.v
1: b'%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro/ffclkconvx.v:34: Operator ADD expects 4 bits on the RHS, but RHS\'s VARREF \'OFFSET\' generates 2 bits.\n                                                                                                               : ... In instance ffclkconvx\nparameter RDCNT_SLP = RDCNT_RST + OFFSET;\n                                ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro/ffclkconvx.v:77: Operator SUB expects 4 bits on the RHS, but RHS\'s VARREF \'OFFSET\' generates 2 bits.\n                                                                                                               : ... In instance ffclkconvx\nassign             window = rdcnt - OFFSET ;\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro/ffclkconvx.v:80: Operator ADD expects 4 bits on the LHS, but LHS\'s VARREF \'winsize\' generates 2 bits.\n                                                                                                               : ... In instance ffclkconvx\nassign size = window[ADDRBIT-1] ? (winsize + window[ADDRBIT-2:0]) :\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro/ffclkconvx.v:81: Operator SUB expects 4 bits on the RHS, but RHS\'s VARREF \'winsize\' generates 2 bits.\n                                                                                                               : ... In instance ffclkconvx\n                                  (window - winsize);\n                                          ^\n%Error: Exiting due to 4 warning(s)\n'
module ffclkconvx
    (
     wrclk,
     rdclk,
     rst_,

     winsize,
     forceslip,
     

     wraddr,
     rdaddr
     );

parameter ADDRBIT = 4;
parameter WIN_WIDTH = 2;

parameter OFFSET = 2'd2;
parameter RDCNT_RST = {1'b1,{ADDRBIT-1{1'b0}}};
parameter RDCNT_SLP = RDCNT_RST + OFFSET;
input   wrclk;
input   rdclk;

input   rst_;

input [WIN_WIDTH -1 :0] winsize;

input   forceslip;

output [ADDRBIT-1:0] wraddr;
output [ADDRBIT-1:0] rdaddr;

reg     [ADDRBIT-1:0]   wrcnt;

wire    [ADDRBIT-1:0] wraddr;
assign  wraddr = wrcnt;

reg     [ADDRBIT-1:0]   rdcnt;

wire    [ADDRBIT-1:0] rdaddr;
assign  rdaddr = rdcnt;

always @(posedge wrclk or negedge rst_)
    begin
    if(!rst_) wrcnt <= {ADDRBIT{1'b0}};
    else if (forceslip) wrcnt <= {ADDRBIT{1'b0}};
    else wrcnt  <= wrcnt  + 1'b1;
    end

wire     sync;
assign   sync = ~wrcnt[ADDRBIT-1];

reg [1:0] shiftsync;
always @(posedge rdclk or negedge rst_)
    begin
    if (!rst_) shiftsync <= 2'b00;
    else shiftsync <= {shiftsync[0],sync};
    end
wire    syncedg;
assign  syncedg = {shiftsync,sync} == 3'b011;

wire [ADDRBIT-1:0] window;
assign             window = rdcnt - OFFSET ;

wire [ADDRBIT-1:0] size; 
assign size = window[ADDRBIT-1] ? (winsize + window[ADDRBIT-2:0]) :
                                  (window - winsize);

wire   slipped;
assign slipped = syncedg & size[ADDRBIT-1];

always @(posedge rdclk or negedge rst_)
    begin
    if(!rst_) rdcnt <= RDCNT_RST;
    else if (forceslip) rdcnt <= RDCNT_RST;
    else if (slipped) rdcnt <= RDCNT_SLP;
    else rdcnt <= rdcnt + 1'b1;
    end

endmodule
module ffclkconvx
    (
     wrclk,
     rdclk,
     rst_,

     winsize,
     forceslip,
     

     wraddr,
     rdaddr
     );


parameter ADDRBIT = 4;
parameter WIN_WIDTH = 2;

parameter OFFSET = 2'd2;
parameter RDCNT_RST = {1'b1,{ADDRBIT-1{1'b0}}};
parameter RDCNT_SLP = RDCNT_RST + OFFSET;
input   wrclk;
input   rdclk;

input   rst_;

input [WIN_WIDTH -1 :0] winsize;

input   forceslip;

output [ADDRBIT-1:0] wraddr;
output [ADDRBIT-1:0] rdaddr;

reg     [ADDRBIT-1:0]   wrcnt;

wire    [ADDRBIT-1:0] wraddr;
assign  wraddr = wrcnt;

reg     [ADDRBIT-1:0]   rdcnt;

wire    [ADDRBIT-1:0] rdaddr;
assign  rdaddr = rdcnt;

always @(posedge wrclk or negedge rst_)
    begin
    if(!rst_) wrcnt <= {ADDRBIT{1'b0}};
    else if (forceslip) wrcnt <= {ADDRBIT{1'b0}};
    else wrcnt  <= wrcnt  + 1'b1;
    end

wire     sync;
assign   sync = ~wrcnt[ADDRBIT-1];

reg [1:0] shiftsync;
always @(posedge rdclk or negedge rst_)
    begin
    if (!rst_) shiftsync <= 2'b00;
    else shiftsync <= {shiftsync[0],sync};
    end
wire    syncedg;
assign  syncedg = {shiftsync,sync} == 3'b011;

wire [ADDRBIT-1:0] window;
assign             window = rdcnt - OFFSET ;

wire [ADDRBIT-1:0] size; 
assign size = window[ADDRBIT-1] ? (winsize + window[ADDRBIT-2:0]) :
                                  (window - winsize);

wire   slipped;
assign slipped = syncedg & size[ADDRBIT-1];

always @(posedge rdclk or negedge rst_)
    begin
    if(!rst_) rdcnt <= RDCNT_RST;
    else if (forceslip) rdcnt <= RDCNT_RST;
    else if (slipped) rdcnt <= RDCNT_SLP;
    else rdcnt <= rdcnt + 1'b1;
    end

endmodule