data/full_repos/permissive/412284801/counter_up_down/counter_up_down_tb.v
1: b'%Error: data/full_repos/permissive/412284801/counter_up_down/counter_up_down_tb.v:1: Cannot find include file: counter_up_down.v\n`include "counter_up_down.v"\n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/412284801/counter_up_down,data/full_repos/permissive/412284801/counter_up_down.v\n             data/full_repos/permissive/412284801/counter_up_down,data/full_repos/permissive/412284801/counter_up_down.v.v\n             data/full_repos/permissive/412284801/counter_up_down,data/full_repos/permissive/412284801/counter_up_down.v.sv\n             counter_up_down.v\n             counter_up_down.v.v\n             counter_up_down.v.sv\n             obj_dir/counter_up_down.v\n             obj_dir/counter_up_down.v.v\n             obj_dir/counter_up_down.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/412284801/counter_up_down/counter_up_down_tb.v:8: Unsupported: Ignoring delay on this delayed statement.\n  always #5 clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/412284801/counter_up_down/counter_up_down_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n    #10 up_down = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/412284801/counter_up_down/counter_up_down_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #10 reset = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/412284801/counter_up_down/counter_up_down_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n    #150 up_down = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/412284801/counter_up_down/counter_up_down_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n    #150 reset = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/412284801/counter_up_down/counter_up_down_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n    #20 up_down = 1\'b0;\n    ^\n%Error: data/full_repos/permissive/412284801/counter_up_down/counter_up_down_tb.v:19: Unsupported or unknown PLI call: $monitor\n    $monitor("Reset = %b, Up_down = %b, Count = %d", reset, up_down, count);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/412284801/counter_up_down/counter_up_down_tb.v:20: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("test.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/412284801/counter_up_down/counter_up_down_tb.v:21: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,counter_up_down_tb);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/412284801/counter_up_down/counter_up_down_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #350 $finish;\n    ^\n%Error: Exiting due to 4 error(s), 7 warning(s)\n'
module counter_up_down_tb #(parameter WIDTH = 2)();
  reg clk = 0, reset, up_down;
  wire [WIDTH-1:0] count;
  
  counter_up_down #(WIDTH) uut (clk, reset, up_down, count);
  
  always #5 clk = ~clk;
  initial begin
    reset = 1'b1;
    up_down = 1'b1;
    #10 up_down = 1'b0;
    #10 reset = 1'b0;
    #150 up_down = 1'b1;
    #150 reset = 1'b1;
    #20 up_down = 1'b0;
  end
  initial begin
    $monitor("Reset = %b, Up_down = %b, Count = %d", reset, up_down, count);
    $dumpfile("test.vcd");
    $dumpvars(0,counter_up_down_tb);
    #350 $finish;
  end
endmodule
module counter_up_down_tb #(parameter WIDTH = 2)();

  reg clk = 0, reset, up_down;
  wire [WIDTH-1:0] count;
  
  counter_up_down #(WIDTH) uut (clk, reset, up_down, count);
  
  always #5 clk = ~clk;
  initial begin
    reset = 1'b1;
    up_down = 1'b1;
    #10 up_down = 1'b0;
    #10 reset = 1'b0;
    #150 up_down = 1'b1;
    #150 reset = 1'b1;
    #20 up_down = 1'b0;
  end
  initial begin
    $monitor("Reset = %b, Up_down = %b, Count = %d", reset, up_down, count);
    $dumpfile("test.vcd");
    $dumpvars(0,counter_up_down_tb);
    #350 $finish;
  end
endmodule