data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_ex_block.sv
1: b"%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_ex_block.sv:12: syntax error, unexpected ::, expecting ')' or ','\n  parameter ibex_pkg::rv32m_e RV32M           = ibex_pkg::RV32MFast,\n                    ^~\n                                                                                                : ... Perhaps 'ibex_pkg' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_ex_block.sv:15: syntax error, unexpected ')', expecting ';'\n) (\n^\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_ex_block.sv:17: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic                  rst_ni,\n  ^~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_ex_block.sv:20: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  ibex_pkg::alu_op_e     alu_operator_i,\n  ^~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_ex_block.sv:22: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic [31:0]           alu_operand_b_i,\n  ^~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_ex_block.sv:23: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic                  alu_instr_first_cycle_i,\n  ^~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_ex_block.sv:27: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic [31:0]           bt_a_operand_i,\n  ^~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_ex_block.sv:28: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic [31:0]           bt_b_operand_i,\n  ^~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_ex_block.sv:31: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  ibex_pkg::md_op_e      multdiv_operator_i,\n  ^~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_ex_block.sv:33: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic                  div_en_i,               \n  ^~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_ex_block.sv:34: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic                  mult_sel_i,             \n  ^~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_ex_block.sv:35: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic                  div_sel_i,              \n  ^~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_ex_block.sv:36: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic  [1:0]           multdiv_signed_mode_i,\n  ^~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_ex_block.sv:37: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic [31:0]           multdiv_operand_a_i,\n  ^~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_ex_block.sv:38: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic [31:0]           multdiv_operand_b_i,\n  ^~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_ex_block.sv:39: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic                  multdiv_ready_id_i,\n  ^~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_ex_block.sv:40: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic                  data_ind_timing_i,\n  ^~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_ex_block.sv:43: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output logic [1:0]            imd_val_we_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_ex_block.sv:44: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output logic [33:0]           imd_val_d_o[2],\n  ^~~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_ex_block.sv:45: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n  input  logic [33:0]           imd_val_q_i[2],\n  ^~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_ex_block.sv:48: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output logic [31:0]           alu_adder_result_ex_o,  \n  ^~~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_ex_block.sv:49: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output logic [31:0]           result_ex_o,\n  ^~~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_ex_block.sv:50: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output logic [31:0]           branch_target_o,        \n  ^~~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_ex_block.sv:51: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output logic                  branch_decision_o,      \n  ^~~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_ex_block.sv:53: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output logic                  ex_valid_o              \n  ^~~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_ex_block.sv:76: syntax error, unexpected if\n  if (RV32M != RV32MNone) begin : gen_multdiv_m\n  ^~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_ex_block.sv:98: syntax error, unexpected assign\n    assign bt_alu_result   = bt_a_operand_i + bt_b_operand_i;\n    ^~~~~~\n%Error: data/full_repos/permissive/419809304/verilog/rtl/ibex/sv-source-orig/ibex_ex_block.sv:106: syntax error, unexpected assign\n    assign unused_bt_a_operand = bt_a_operand_i;\n    ^~~~~~\n%Error: Exiting due to 28 error(s)\n"
module ibex_ex_block #(
  parameter ibex_pkg::rv32m_e RV32M           = ibex_pkg::RV32MFast,
  parameter ibex_pkg::rv32b_e RV32B           = ibex_pkg::RV32BNone,
  parameter bit               BranchTargetALU = 0
) (
  input  logic                  clk_i,
  input  logic                  rst_ni,


  input  ibex_pkg::alu_op_e     alu_operator_i,
  input  logic [31:0]           alu_operand_a_i,
  input  logic [31:0]           alu_operand_b_i,
  input  logic                  alu_instr_first_cycle_i,



  input  logic [31:0]           bt_a_operand_i,
  input  logic [31:0]           bt_b_operand_i,


  input  ibex_pkg::md_op_e      multdiv_operator_i,
  input  logic                  mult_en_i,
  input  logic                  div_en_i,
  input  logic                  mult_sel_i,
  input  logic                  div_sel_i,
  input  logic  [1:0]           multdiv_signed_mode_i,
  input  logic [31:0]           multdiv_operand_a_i,
  input  logic [31:0]           multdiv_operand_b_i,
  input  logic                  multdiv_ready_id_i,
  input  logic                  data_ind_timing_i,


  output logic [1:0]            imd_val_we_o,
  output logic [33:0]           imd_val_d_o[2],
  input  logic [33:0]           imd_val_q_i[2],


  output logic [31:0]           alu_adder_result_ex_o,
  output logic [31:0]           result_ex_o,
  output logic [31:0]           branch_target_o,
  output logic                  branch_decision_o,

  output logic                  ex_valid_o
);

  import ibex_pkg::*;

  logic [31:0] alu_result, multdiv_result;

  logic [32:0] multdiv_alu_operand_b, multdiv_alu_operand_a;
  logic [33:0] alu_adder_result_ext;
  logic        alu_cmp_result, alu_is_equal_result;
  logic        multdiv_valid;
  logic        multdiv_sel;
  logic [31:0] alu_imd_val_q[2];
  logic [31:0] alu_imd_val_d[2];
  logic [ 1:0] alu_imd_val_we;
  logic [33:0] multdiv_imd_val_d[2];
  logic [ 1:0] multdiv_imd_val_we;


  if (RV32M != RV32MNone) begin : gen_multdiv_m
    assign multdiv_sel = mult_sel_i | div_sel_i;
  end else begin : gen_multdiv_no_m
    assign multdiv_sel = 1'b0;
  end


  assign imd_val_d_o[0] = multdiv_sel ? multdiv_imd_val_d[0] : {2'b0, alu_imd_val_d[0]};
  assign imd_val_d_o[1] = multdiv_sel ? multdiv_imd_val_d[1] : {2'b0, alu_imd_val_d[1]};
  assign imd_val_we_o   = multdiv_sel ? multdiv_imd_val_we : alu_imd_val_we;

  assign alu_imd_val_q = '{imd_val_q_i[0][31:0], imd_val_q_i[1][31:0]};

  assign result_ex_o  = multdiv_sel ? multdiv_result : alu_result;


  assign branch_decision_o  = alu_cmp_result;

  if (BranchTargetALU) begin : g_branch_target_alu
    logic [32:0] bt_alu_result;
    logic        unused_bt_carry;

    assign bt_alu_result   = bt_a_operand_i + bt_b_operand_i;

    assign unused_bt_carry = bt_alu_result[32];
    assign branch_target_o = bt_alu_result[31:0];
  end else begin : g_no_branch_target_alu

    logic [31:0] unused_bt_a_operand, unused_bt_b_operand;

    assign unused_bt_a_operand = bt_a_operand_i;
    assign unused_bt_b_operand = bt_b_operand_i;

    assign branch_target_o = alu_adder_result_ex_o;
  end





  ibex_alu #(
    .RV32B(RV32B)
  ) alu_i (
    .operator_i         (alu_operator_i),
    .operand_a_i        (alu_operand_a_i),
    .operand_b_i        (alu_operand_b_i),
    .instr_first_cycle_i(alu_instr_first_cycle_i),
    .imd_val_q_i        (alu_imd_val_q),
    .imd_val_we_o       (alu_imd_val_we),
    .imd_val_d_o        (alu_imd_val_d),
    .multdiv_operand_a_i(multdiv_alu_operand_a),
    .multdiv_operand_b_i(multdiv_alu_operand_b),
    .multdiv_sel_i      (multdiv_sel),
    .adder_result_o     (alu_adder_result_ex_o),
    .adder_result_ext_o (alu_adder_result_ext),
    .result_o           (alu_result),
    .comparison_result_o(alu_cmp_result),
    .is_equal_result_o  (alu_is_equal_result)
  );





  if (RV32M == RV32MSlow) begin : gen_multdiv_slow
    ibex_multdiv_slow multdiv_i (
      .clk_i             (clk_i),
      .rst_ni            (rst_ni),
      .mult_en_i         (mult_en_i),
      .div_en_i          (div_en_i),
      .mult_sel_i        (mult_sel_i),
      .div_sel_i         (div_sel_i),
      .operator_i        (multdiv_operator_i),
      .signed_mode_i     (multdiv_signed_mode_i),
      .op_a_i            (multdiv_operand_a_i),
      .op_b_i            (multdiv_operand_b_i),
      .alu_adder_ext_i   (alu_adder_result_ext),
      .alu_adder_i       (alu_adder_result_ex_o),
      .equal_to_zero_i   (alu_is_equal_result),
      .data_ind_timing_i (data_ind_timing_i),
      .valid_o           (multdiv_valid),
      .alu_operand_a_o   (multdiv_alu_operand_a),
      .alu_operand_b_o   (multdiv_alu_operand_b),
      .imd_val_q_i       (imd_val_q_i),
      .imd_val_d_o       (multdiv_imd_val_d),
      .imd_val_we_o      (multdiv_imd_val_we),
      .multdiv_ready_id_i(multdiv_ready_id_i),
      .multdiv_result_o  (multdiv_result)
    );
  end else if (RV32M == RV32MFast || RV32M == RV32MSingleCycle) begin : gen_multdiv_fast
    ibex_multdiv_fast #(
      .RV32M(RV32M)
    ) multdiv_i (
      .clk_i             (clk_i),
      .rst_ni            (rst_ni),
      .mult_en_i         (mult_en_i),
      .div_en_i          (div_en_i),
      .mult_sel_i        (mult_sel_i),
      .div_sel_i         (div_sel_i),
      .operator_i        (multdiv_operator_i),
      .signed_mode_i     (multdiv_signed_mode_i),
      .op_a_i            (multdiv_operand_a_i),
      .op_b_i            (multdiv_operand_b_i),
      .alu_operand_a_o   (multdiv_alu_operand_a),
      .alu_operand_b_o   (multdiv_alu_operand_b),
      .alu_adder_ext_i   (alu_adder_result_ext),
      .alu_adder_i       (alu_adder_result_ex_o),
      .equal_to_zero_i   (alu_is_equal_result),
      .data_ind_timing_i (data_ind_timing_i),
      .imd_val_q_i       (imd_val_q_i),
      .imd_val_d_o       (multdiv_imd_val_d),
      .imd_val_we_o      (multdiv_imd_val_we),
      .multdiv_ready_id_i(multdiv_ready_id_i),
      .valid_o           (multdiv_valid),
      .multdiv_result_o  (multdiv_result)
    );
  end




  assign ex_valid_o = multdiv_sel ? multdiv_valid : ~(|alu_imd_val_we);

endmodule
module ibex_ex_block #(
  parameter ibex_pkg::rv32m_e RV32M           = ibex_pkg::RV32MFast,
  parameter ibex_pkg::rv32b_e RV32B           = ibex_pkg::RV32BNone,
  parameter bit               BranchTargetALU = 0
) (
  input  logic                  clk_i,
  input  logic                  rst_ni,


  input  ibex_pkg::alu_op_e     alu_operator_i,
  input  logic [31:0]           alu_operand_a_i,
  input  logic [31:0]           alu_operand_b_i,
  input  logic                  alu_instr_first_cycle_i,



  input  logic [31:0]           bt_a_operand_i,
  input  logic [31:0]           bt_b_operand_i,


  input  ibex_pkg::md_op_e      multdiv_operator_i,
  input  logic                  mult_en_i,
  input  logic                  div_en_i,
  input  logic                  mult_sel_i,
  input  logic                  div_sel_i,
  input  logic  [1:0]           multdiv_signed_mode_i,
  input  logic [31:0]           multdiv_operand_a_i,
  input  logic [31:0]           multdiv_operand_b_i,
  input  logic                  multdiv_ready_id_i,
  input  logic                  data_ind_timing_i,


  output logic [1:0]            imd_val_we_o,
  output logic [33:0]           imd_val_d_o[2],
  input  logic [33:0]           imd_val_q_i[2],


  output logic [31:0]           alu_adder_result_ex_o,
  output logic [31:0]           result_ex_o,
  output logic [31:0]           branch_target_o,
  output logic                  branch_decision_o,

  output logic                  ex_valid_o
);


  import ibex_pkg::*;

  logic [31:0] alu_result, multdiv_result;

  logic [32:0] multdiv_alu_operand_b, multdiv_alu_operand_a;
  logic [33:0] alu_adder_result_ext;
  logic        alu_cmp_result, alu_is_equal_result;
  logic        multdiv_valid;
  logic        multdiv_sel;
  logic [31:0] alu_imd_val_q[2];
  logic [31:0] alu_imd_val_d[2];
  logic [ 1:0] alu_imd_val_we;
  logic [33:0] multdiv_imd_val_d[2];
  logic [ 1:0] multdiv_imd_val_we;


  if (RV32M != RV32MNone) begin : gen_multdiv_m
    assign multdiv_sel = mult_sel_i | div_sel_i;
  end else begin : gen_multdiv_no_m
    assign multdiv_sel = 1'b0;
  end


  assign imd_val_d_o[0] = multdiv_sel ? multdiv_imd_val_d[0] : {2'b0, alu_imd_val_d[0]};
  assign imd_val_d_o[1] = multdiv_sel ? multdiv_imd_val_d[1] : {2'b0, alu_imd_val_d[1]};
  assign imd_val_we_o   = multdiv_sel ? multdiv_imd_val_we : alu_imd_val_we;

  assign alu_imd_val_q = '{imd_val_q_i[0][31:0], imd_val_q_i[1][31:0]};

  assign result_ex_o  = multdiv_sel ? multdiv_result : alu_result;


  assign branch_decision_o  = alu_cmp_result;

  if (BranchTargetALU) begin : g_branch_target_alu
    logic [32:0] bt_alu_result;
    logic        unused_bt_carry;

    assign bt_alu_result   = bt_a_operand_i + bt_b_operand_i;

    assign unused_bt_carry = bt_alu_result[32];
    assign branch_target_o = bt_alu_result[31:0];
  end else begin : g_no_branch_target_alu

    logic [31:0] unused_bt_a_operand, unused_bt_b_operand;

    assign unused_bt_a_operand = bt_a_operand_i;
    assign unused_bt_b_operand = bt_b_operand_i;

    assign branch_target_o = alu_adder_result_ex_o;
  end





  ibex_alu #(
    .RV32B(RV32B)
  ) alu_i (
    .operator_i         (alu_operator_i),
    .operand_a_i        (alu_operand_a_i),
    .operand_b_i        (alu_operand_b_i),
    .instr_first_cycle_i(alu_instr_first_cycle_i),
    .imd_val_q_i        (alu_imd_val_q),
    .imd_val_we_o       (alu_imd_val_we),
    .imd_val_d_o        (alu_imd_val_d),
    .multdiv_operand_a_i(multdiv_alu_operand_a),
    .multdiv_operand_b_i(multdiv_alu_operand_b),
    .multdiv_sel_i      (multdiv_sel),
    .adder_result_o     (alu_adder_result_ex_o),
    .adder_result_ext_o (alu_adder_result_ext),
    .result_o           (alu_result),
    .comparison_result_o(alu_cmp_result),
    .is_equal_result_o  (alu_is_equal_result)
  );





  if (RV32M == RV32MSlow) begin : gen_multdiv_slow
    ibex_multdiv_slow multdiv_i (
      .clk_i             (clk_i),
      .rst_ni            (rst_ni),
      .mult_en_i         (mult_en_i),
      .div_en_i          (div_en_i),
      .mult_sel_i        (mult_sel_i),
      .div_sel_i         (div_sel_i),
      .operator_i        (multdiv_operator_i),
      .signed_mode_i     (multdiv_signed_mode_i),
      .op_a_i            (multdiv_operand_a_i),
      .op_b_i            (multdiv_operand_b_i),
      .alu_adder_ext_i   (alu_adder_result_ext),
      .alu_adder_i       (alu_adder_result_ex_o),
      .equal_to_zero_i   (alu_is_equal_result),
      .data_ind_timing_i (data_ind_timing_i),
      .valid_o           (multdiv_valid),
      .alu_operand_a_o   (multdiv_alu_operand_a),
      .alu_operand_b_o   (multdiv_alu_operand_b),
      .imd_val_q_i       (imd_val_q_i),
      .imd_val_d_o       (multdiv_imd_val_d),
      .imd_val_we_o      (multdiv_imd_val_we),
      .multdiv_ready_id_i(multdiv_ready_id_i),
      .multdiv_result_o  (multdiv_result)
    );
  end else if (RV32M == RV32MFast || RV32M == RV32MSingleCycle) begin : gen_multdiv_fast
    ibex_multdiv_fast #(
      .RV32M(RV32M)
    ) multdiv_i (
      .clk_i             (clk_i),
      .rst_ni            (rst_ni),
      .mult_en_i         (mult_en_i),
      .div_en_i          (div_en_i),
      .mult_sel_i        (mult_sel_i),
      .div_sel_i         (div_sel_i),
      .operator_i        (multdiv_operator_i),
      .signed_mode_i     (multdiv_signed_mode_i),
      .op_a_i            (multdiv_operand_a_i),
      .op_b_i            (multdiv_operand_b_i),
      .alu_operand_a_o   (multdiv_alu_operand_a),
      .alu_operand_b_o   (multdiv_alu_operand_b),
      .alu_adder_ext_i   (alu_adder_result_ext),
      .alu_adder_i       (alu_adder_result_ex_o),
      .equal_to_zero_i   (alu_is_equal_result),
      .data_ind_timing_i (data_ind_timing_i),
      .imd_val_q_i       (imd_val_q_i),
      .imd_val_d_o       (multdiv_imd_val_d),
      .imd_val_we_o      (multdiv_imd_val_we),
      .multdiv_ready_id_i(multdiv_ready_id_i),
      .valid_o           (multdiv_valid),
      .multdiv_result_o  (multdiv_result)
    );
  end




  assign ex_valid_o = multdiv_sel ? multdiv_valid : ~(|alu_imd_val_we);

endmodule