data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_lib.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ctu_lib.v:27: Cannot find include file: sys.h\n`include "sys.h"  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: Exiting due to 1 error(s)\n'
module ctu_synch_ref_jl(

syncdata, 

pll_raw_clk_out, presyncdata
);

parameter SIZE = 1;

input  pll_raw_clk_out;
input  [SIZE-1:0]  presyncdata; 
output [SIZE-1:0]  syncdata;

wire [SIZE-1:0]  presyncdata_in; 

bw_u1_scanl_2x u_ctu_synch_ref_jl_0 [SIZE-1:0]
   (.sd (presyncdata[SIZE-1:0]),
    .ck (pll_raw_clk_out),
    .so (syncdata[SIZE-1:0])
    );


endmodule
module ctu_synch_ref_jl(

syncdata, 

pll_raw_clk_out, presyncdata
);


parameter SIZE = 1;

input  pll_raw_clk_out;
input  [SIZE-1:0]  presyncdata; 
output [SIZE-1:0]  syncdata;

wire [SIZE-1:0]  presyncdata_in; 

bw_u1_scanl_2x u_ctu_synch_ref_jl_0 [SIZE-1:0]
   (.sd (presyncdata[SIZE-1:0]),
    .ck (pll_raw_clk_out),
    .so (syncdata[SIZE-1:0])
    );


endmodule