data/full_repos/permissive/452461941/AES_Decryption/testbench_Decryption.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/452461941/AES_Decryption/testbench_Decryption.v:13: Unsupported: Ignoring delay on this delayed statement.\n  clock = 0; forever #50 clock = ~clock;\n                     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/452461941/AES_Decryption/testbench_Decryption.v:18: syntax error, unexpected \'@\'\n @(negedge clock) reset = 1;\n ^\n%Error: data/full_repos/permissive/452461941/AES_Decryption/testbench_Decryption.v:20: syntax error, unexpected \'@\'\n @(negedge clock) decrypt = 0;\n ^\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench_Decryption();
	reg [127:0] encrypted_text, key;
	reg decrypt, clock, reset;
	wire  [127:0] Data_OUT;
	wire done;

	ASMD_Decryption A(done, Data_OUT, encrypted_text, key, decrypt, clock, reset);

	
	initial begin
		clock = 0; forever #50 clock = ~clock;
	end
	
	initial begin

	@(negedge clock) reset = 1;
	@(negedge clock) reset = 0; decrypt = 1; key = 128'h49206c6f76652063686f636f6c617465; encrypted_text=128'hd4d9e235c89a2989fd6bdddc7f19aa94;
	@(negedge clock) decrypt = 0;
	@(negedge clock) ;
	
	
	end

endmodule
module testbench_Decryption();

	reg [127:0] encrypted_text, key;
	reg decrypt, clock, reset;
	wire  [127:0] Data_OUT;
	wire done;

	ASMD_Decryption A(done, Data_OUT, encrypted_text, key, decrypt, clock, reset);

	
	initial begin
		clock = 0; forever #50 clock = ~clock;
	end
	
	initial begin

	@(negedge clock) reset = 1;
	@(negedge clock) reset = 0; decrypt = 1; key = 128'h49206c6f76652063686f636f6c617465; encrypted_text=128'hd4d9e235c89a2989fd6bdddc7f19aa94;
	@(negedge clock) decrypt = 0;
	@(negedge clock) ;
	
	
	end

endmodule