data/full_repos/permissive/406635962/src/rtl/dtcm_ctrl.v
1: b'%Error: data/full_repos/permissive/406635962/src/rtl/dtcm_ctrl.v:6: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/406635962/src/rtl/dtcm_ctrl.v:14: Define or directive not defined: \'`DTCM_ADDR_WIDTH\'\n    input [`DTCM_ADDR_WIDTH-1:0] lsu2dtcm_cmd_addr,\n           ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/dtcm_ctrl.v:15: Define or directive not defined: \'`DTCM_RAM_MW\'\n    input [`DTCM_RAM_MW-1:0] lsu2dtcm_cmd_wmask,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/dtcm_ctrl.v:16: Define or directive not defined: \'`DTCM_RAM_DW\'\n    input [`DTCM_RAM_DW-1:0] lsu2dtcm_cmd_wdata,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/dtcm_ctrl.v:21: Define or directive not defined: \'`DTCM_RAM_DW\'\n    output [`DTCM_RAM_DW-1:0] lsu2dtcm_rsp_rdata,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/dtcm_ctrl.v:25: Define or directive not defined: \'`DTCM_RAM_AW\'\n    output [`DTCM_RAM_AW-1:0] dtcm_ram_addr,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/dtcm_ctrl.v:26: Define or directive not defined: \'`DTCM_RAM_MW\'\n    output [`DTCM_RAM_MW-1:0] dtcm_ram_wem,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/dtcm_ctrl.v:27: Define or directive not defined: \'`DTCM_RAM_DW\'\n    output [`DTCM_RAM_DW-1:0] dtcm_ram_din,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/dtcm_ctrl.v:28: Define or directive not defined: \'`DTCM_RAM_DW\'\n    input [`DTCM_RAM_DW-1:0] dtcm_ram_dout,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/dtcm_ctrl.v:39: Define or directive not defined: \'`DTCM_ADDR_WIDTH\'\n    assign dtcm_ram_addr = lsu2dtcm_cmd_addr[`DTCM_ADDR_WIDTH-1:2];\n                                             ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 10 error(s)\n'
module dtcm_ctrl (


    input lsu2dtcm_cmd_valid,
    output lsu2dtcm_cmd_ready,
    input lsu2dtcm_cmd_read,
    input [`DTCM_ADDR_WIDTH-1:0] lsu2dtcm_cmd_addr,
    input [`DTCM_RAM_MW-1:0] lsu2dtcm_cmd_wmask,
    input [`DTCM_RAM_DW-1:0] lsu2dtcm_cmd_wdata,
    

    output lsu2dtcm_rsp_valid,
    input lsu2dtcm_rsp_ready,
    output [`DTCM_RAM_DW-1:0] lsu2dtcm_rsp_rdata,


    output dtcm_ram_we,
    output [`DTCM_RAM_AW-1:0] dtcm_ram_addr,
    output [`DTCM_RAM_MW-1:0] dtcm_ram_wem,
    output [`DTCM_RAM_DW-1:0] dtcm_ram_din,
    input [`DTCM_RAM_DW-1:0] dtcm_ram_dout,

    input clk,
    input rst_n
);
    wire lsu2dtcm_rsp_valid_r;

    assign lsu2dtcm_cmd_ready = 1;
    assign lsu2dtcm_rsp_valid = lsu2dtcm_rsp_valid_r;
    assign lsu2dtcm_rsp_rdata = dtcm_ram_dout;
    assign dtcm_ram_we = ~lsu2dtcm_cmd_read & lsu2dtcm_cmd_valid;
    assign dtcm_ram_addr = lsu2dtcm_cmd_addr[`DTCM_ADDR_WIDTH-1:2];
    assign dtcm_ram_wem = lsu2dtcm_cmd_wmask;
    assign dtcm_ram_din = lsu2dtcm_cmd_wdata;


    wire lsu2dtcm_rsp_valid_set = lsu2dtcm_cmd_valid;
    wire lsu2dtcm_rsp_valid_clr = lsu2dtcm_rsp_valid_r;
    wire lsu2dtcm_rsp_valid_nxt = lsu2dtcm_rsp_valid_set | (~lsu2dtcm_rsp_valid_clr);
    wire lsu2dtcm_rsp_valid_ena = lsu2dtcm_rsp_valid_set | lsu2dtcm_rsp_valid_clr;
    gnrl_dfflr #(1) lsu2dtcm_rsp_valid_dfflr(lsu2dtcm_rsp_valid_ena, lsu2dtcm_rsp_valid_nxt, lsu2dtcm_rsp_valid_r, clk, rst_n);
endmodule
module dtcm_ctrl (


    input lsu2dtcm_cmd_valid,
    output lsu2dtcm_cmd_ready,
    input lsu2dtcm_cmd_read,
    input [`DTCM_ADDR_WIDTH-1:0] lsu2dtcm_cmd_addr,
    input [`DTCM_RAM_MW-1:0] lsu2dtcm_cmd_wmask,
    input [`DTCM_RAM_DW-1:0] lsu2dtcm_cmd_wdata,
    

    output lsu2dtcm_rsp_valid,
    input lsu2dtcm_rsp_ready,
    output [`DTCM_RAM_DW-1:0] lsu2dtcm_rsp_rdata,


    output dtcm_ram_we,
    output [`DTCM_RAM_AW-1:0] dtcm_ram_addr,
    output [`DTCM_RAM_MW-1:0] dtcm_ram_wem,
    output [`DTCM_RAM_DW-1:0] dtcm_ram_din,
    input [`DTCM_RAM_DW-1:0] dtcm_ram_dout,

    input clk,
    input rst_n
);

    wire lsu2dtcm_rsp_valid_r;

    assign lsu2dtcm_cmd_ready = 1;
    assign lsu2dtcm_rsp_valid = lsu2dtcm_rsp_valid_r;
    assign lsu2dtcm_rsp_rdata = dtcm_ram_dout;
    assign dtcm_ram_we = ~lsu2dtcm_cmd_read & lsu2dtcm_cmd_valid;
    assign dtcm_ram_addr = lsu2dtcm_cmd_addr[`DTCM_ADDR_WIDTH-1:2];
    assign dtcm_ram_wem = lsu2dtcm_cmd_wmask;
    assign dtcm_ram_din = lsu2dtcm_cmd_wdata;


    wire lsu2dtcm_rsp_valid_set = lsu2dtcm_cmd_valid;
    wire lsu2dtcm_rsp_valid_clr = lsu2dtcm_rsp_valid_r;
    wire lsu2dtcm_rsp_valid_nxt = lsu2dtcm_rsp_valid_set | (~lsu2dtcm_rsp_valid_clr);
    wire lsu2dtcm_rsp_valid_ena = lsu2dtcm_rsp_valid_set | lsu2dtcm_rsp_valid_clr;
    gnrl_dfflr #(1) lsu2dtcm_rsp_valid_dfflr(lsu2dtcm_rsp_valid_ena, lsu2dtcm_rsp_valid_nxt, lsu2dtcm_rsp_valid_r, clk, rst_n);
endmodule