data/full_repos/permissive/420726213/verilog/dv/tb/prng_wrap_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/420726213/verilog/dv/tb/prng_wrap_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/420726213/verilog/dv/tb/prng_wrap_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n   #10 rst_n <= 1;\n   ^\n%Error: data/full_repos/permissive/420726213/verilog/dv/tb/prng_wrap_tb.v:33: Unsupported or unknown PLI call: $monitor\n   $monitor("%4d %128b", $time, random);\n   ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/420726213/verilog/dv/tb/prng_wrap_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n   #200 $stop;\n   ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module prng_wrap_tb();

parameter INDEX = 0;
parameter OUTPUT_BITS = 128;

reg clk;
reg rst_n;
wire [OUTPUT_BITS-1:0] random;

prng_wrap #(
   .INDEX(INDEX),
   .OUTPUT_BITS(OUTPUT_BITS)
) prng_wrap_dut (
   .clk(clk),
   .rst_n(rst_n),
   .entropy(1'b0),
   .random(random)
);

always #5 clk = ~clk;

initial begin
   clk <= 0;
   rst_n <= 0;
   #10 rst_n <= 1;
   $display("%8x", prng_wrap_dut.prng_inst.POLYNOMIAL);
   $display("%8x", prng_wrap_dut.prng_inst.scrambled_init);
   $monitor("%4d %128b", $time, random);
   #200 $stop;
end

endmodule
module prng_wrap_tb();


parameter INDEX = 0;
parameter OUTPUT_BITS = 128;

reg clk;
reg rst_n;
wire [OUTPUT_BITS-1:0] random;

prng_wrap #(
   .INDEX(INDEX),
   .OUTPUT_BITS(OUTPUT_BITS)
) prng_wrap_dut (
   .clk(clk),
   .rst_n(rst_n),
   .entropy(1'b0),
   .random(random)
);

always #5 clk = ~clk;

initial begin
   clk <= 0;
   rst_n <= 0;
   #10 rst_n <= 1;
   $display("%8x", prng_wrap_dut.prng_inst.POLYNOMIAL);
   $display("%8x", prng_wrap_dut.prng_inst.scrambled_init);
   $monitor("%4d %128b", $time, random);
   #200 $stop;
end

endmodule