data/full_repos/permissive/451853158/MIPS_Pipeline_Processor/signExt.v
data/verilator_xmls/b1b09614-7ca2-42e3-a7c0-49f255274ca1.xml
module signExt (
  input [15:0] a,
  output wire [31:0] y
);

assign y = {{16{a[15]}},a};

endmodule
module signExt (
  input [15:0] a,
  output wire [31:0] y
);


assign y = {{16{a[15]}},a};

endmodule