data/full_repos/permissive/414867793/Logic_Circuits/Full_Substrator/F_SUBS.v
data/verilator_xmls/bb333866-7232-4ff9-b4c4-383306234402.xml
module F_SUBS(A,B,C,D,E);

input A,B,C;
output D,E;
 assign D=A^B^C;
 assign E=((~(A))&C|(~(A))&B|B&C);

endmodule
module F_SUBS(A,B,C,D,E);


input A,B,C;
output D,E;
 assign D=A^B^C;
 assign E=((~(A))&C|(~(A))&B|B&C);

endmodule