data/full_repos/permissive/432384243/verilog/dv/user_uart_master/user_uart_master_tb.v
1: b'%Error: data/full_repos/permissive/432384243/verilog/dv/user_uart_master/user_uart_master_tb.v:69: Cannot find include file: uprj_netlists.v\n`include "uprj_netlists.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/432384243/verilog/dv/user_uart_master,data/full_repos/permissive/432384243/uprj_netlists.v\n             data/full_repos/permissive/432384243/verilog/dv/user_uart_master,data/full_repos/permissive/432384243/uprj_netlists.v.v\n             data/full_repos/permissive/432384243/verilog/dv/user_uart_master,data/full_repos/permissive/432384243/uprj_netlists.v.sv\n             uprj_netlists.v\n             uprj_netlists.v.v\n             uprj_netlists.v.sv\n             obj_dir/uprj_netlists.v\n             obj_dir/uprj_netlists.v.v\n             obj_dir/uprj_netlists.v.sv\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_uart_master/user_uart_master_tb.v:70: Cannot find include file: uart_agent.v\n`include "uart_agent.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_uart_master/user_uart_master_tb.v:294: Cannot find include file: uart_master_tasks.sv\n`include "uart_master_tasks.sv" \n         ^~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/432384243/verilog/dv/user_uart_master/user_uart_master_tb.v:130: Unsupported: Ignoring delay on this delayed statement.\n always #12.5 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/432384243/verilog/dv/user_uart_master/user_uart_master_tb.v:172: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Error: data/full_repos/permissive/432384243/verilog/dv/user_uart_master/user_uart_master_tb.v:195: syntax error, unexpected \'@\'\n   repeat (2) @(posedge clock);\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/432384243/verilog/dv/user_uart_master/user_uart_master_tb.v:196: Unsupported: Ignoring delay on this delayed statement.\n   #1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/432384243/verilog/dv/user_uart_master/user_uart_master_tb.v:227: Unsupported: Ignoring delay on this delayed statement.\n   #100\n   ^\n%Error: Exiting due to 4 error(s), 4 warning(s)\n'
module user_uart_master_tb;

reg            clock         ;
reg            wb_rst_i      ;
reg            power1, power2;
reg            power3, power4;

reg            wbd_ext_cyc_i;
reg            wbd_ext_stb_i;
reg [31:0]     wbd_ext_adr_i;
reg            wbd_ext_we_i;
reg [31:0]     wbd_ext_dat_i;
reg [3:0]      wbd_ext_sel_i;

wire [31:0]    wbd_ext_dat_o;
wire           wbd_ext_ack_o;
wire           wbd_ext_err_o;


wire [37:0]    io_oeb        ;
wire [37:0]    io_out        ;
wire [37:0]    io_in         ;

wire [37:0]    mprj_io       ;
wire [7:0]     mprj_io_0     ;
reg            test_fail     ;
reg [31:0]     read_data     ;



reg [1:0]      uart_data_bit        ;
reg	       uart_stop_bits       ;
reg	       uart_stick_parity    ;
reg	       uart_parity_en       ;
reg	       uart_even_odd_parity ;

reg [7:0]      uart_data            ;
reg [15:0]     uart_divisor         ;
reg [15:0]     uart_timeout         ;

reg [15:0]     uart_rx_nu           ;
reg [15:0]     uart_tx_nu           ;
reg [7:0]      uart_write_data [0:39];
reg 	       uart_fifo_enable     ;

reg  [127:0]   la_data_in;
reg       flag;


integer i,j;





	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
		la_data_in = 1;
	end

	`ifdef WFDUMP
	   initial begin
	   	$dumpfile("risc_boot.vcd");
	   	$dumpvars(0, user_uart_master_tb);
	   end
       `endif

	initial begin
		clock = 0;
                wbd_ext_cyc_i ='h0;
                wbd_ext_stb_i ='h0;
                wbd_ext_adr_i ='h0;
                wbd_ext_we_i  ='h0;
                wbd_ext_dat_i ='h0;
                wbd_ext_sel_i ='h0;
	end
initial
begin
   wb_rst_i <= 1'b1;
   uart_data_bit           = 2'b11;
   uart_stop_bits          = 1;
   uart_stick_parity       = 0;
   uart_parity_en          = 0;
   uart_even_odd_parity    = 1;
   uart_divisor            = 15;
   uart_timeout            = 600;
   uart_fifo_enable        = 0;


   la_data_in[1] = 1;
   la_data_in[2] = 1;
   la_data_in[3] = 1;
   la_data_in[15:4] = ((uart_divisor+1)/16)-1;
   la_data_in[17:16] = 2'b00;

   #100;
   wb_rst_i <= 1'b0;

   $display("Monitor: Standalone User Uart master Test Started");

   tb_master_uart.debug_mode = 0;
   tb_master_uart.uart_init;
   tb_master_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, 
	                          uart_stick_parity, uart_timeout, uart_divisor);


   flag = 0;
   while(flag == 0)
   begin
        tb_master_uart.read_char(read_data,flag);
        $write ("%c",read_data);
   end




   uartm_reg_write('h3080_0000,'h1);

   repeat (2) @(posedge clock);
   #1;

   $display("Monitor: Writing  expected value");
   
   test_fail = 0;
   uartm_reg_read_check(32'h30000000,32'h44332211);
   uartm_reg_read_check(32'h30000004,32'hDDCCBBAA);

   uartm_reg_write(32'h30020000,32'h11223344);
   uartm_reg_write(32'h30020004,32'h22334455);

   uartm_reg_read_check(32'h30000000,32'h11223344);
   uartm_reg_read_check(32'h30000004,32'h22334455);
   
   
   
   $display("###################################################");
   if(test_fail == 0) begin
      `ifdef GL
          $display("Monitor: Standalone User UART Master (GL) Passed");
      `else
          $display("Monitor: Standalone User Uart Master (RTL) Passed");
      `endif
   end else begin
       `ifdef GL
           $display("Monitor: Standalone User Uart Master (GL) Failed");
       `else
           $display("Monitor: Standalone User Uart Master (RTL) Failed");
       `endif
    end
   $display("###################################################");
   #100
   $finish;
end


wire USER_VDD1V8 = 1'b1;
wire VSS = 1'b0;


user_project_wrapper u_top(
`ifdef USE_POWER_PINS
    .vccd1(USER_VDD1V8),
    .vssd1(VSS),
`endif
    .wb_clk_i        (clock),
    .user_clock2     (1'b1),
    .wb_rst_i        (wb_rst_i),

    .wbs_cyc_i   (wbd_ext_cyc_i),
    .wbs_stb_i   (wbd_ext_stb_i),
    .wbs_adr_i   (wbd_ext_adr_i),
    .wbs_we_i    (wbd_ext_we_i),
    .wbs_dat_i   (wbd_ext_dat_i),
    .wbs_sel_i   (wbd_ext_sel_i),

    .wbs_dat_o   (wbd_ext_dat_o),
    .wbs_ack_o   (wbd_ext_ack_o),

 

    .la_data_in      (la_data_in) ,
    .la_data_out     (),
    .la_oenb         ('0),
 


    .io_in          (io_in)  ,
    .io_out         (io_out) ,
    .io_oeb         (io_oeb) ,

    .user_irq       () 

);

`ifndef GL

    initial begin
    end
`endif    





wire uart_txd,uart_rxd;

assign uart_txd   = io_out[1];
assign io_in[0]  = uart_rxd ;
 
uart_agent tb_master_uart(
	.mclk                (clock              ),
	.txd                 (uart_rxd           ),
	.rxd                 (uart_txd           )
	);



`include "uart_master_tasks.sv"
endmodule
module user_uart_master_tb;


reg            clock         ;
reg            wb_rst_i      ;
reg            power1, power2;
reg            power3, power4;

reg            wbd_ext_cyc_i;
reg            wbd_ext_stb_i;
reg [31:0]     wbd_ext_adr_i;
reg            wbd_ext_we_i;
reg [31:0]     wbd_ext_dat_i;
reg [3:0]      wbd_ext_sel_i;

wire [31:0]    wbd_ext_dat_o;
wire           wbd_ext_ack_o;
wire           wbd_ext_err_o;


wire [37:0]    io_oeb        ;
wire [37:0]    io_out        ;
wire [37:0]    io_in         ;

wire [37:0]    mprj_io       ;
wire [7:0]     mprj_io_0     ;
reg            test_fail     ;
reg [31:0]     read_data     ;



reg [1:0]      uart_data_bit        ;
reg	       uart_stop_bits       ;
reg	       uart_stick_parity    ;
reg	       uart_parity_en       ;
reg	       uart_even_odd_parity ;

reg [7:0]      uart_data            ;
reg [15:0]     uart_divisor         ;
reg [15:0]     uart_timeout         ;

reg [15:0]     uart_rx_nu           ;
reg [15:0]     uart_tx_nu           ;
reg [7:0]      uart_write_data [0:39];
reg 	       uart_fifo_enable     ;

reg  [127:0]   la_data_in;
reg       flag;


integer i,j;





	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
		la_data_in = 1;
	end

	`ifdef WFDUMP
	   initial begin
	   	$dumpfile("risc_boot.vcd");
	   	$dumpvars(0, user_uart_master_tb);
	   end
       `endif

	initial begin
		clock = 0;
                wbd_ext_cyc_i ='h0;
                wbd_ext_stb_i ='h0;
                wbd_ext_adr_i ='h0;
                wbd_ext_we_i  ='h0;
                wbd_ext_dat_i ='h0;
                wbd_ext_sel_i ='h0;
	end
initial
begin
   wb_rst_i <= 1'b1;
   uart_data_bit           = 2'b11;
   uart_stop_bits          = 1;
   uart_stick_parity       = 0;
   uart_parity_en          = 0;
   uart_even_odd_parity    = 1;
   uart_divisor            = 15;
   uart_timeout            = 600;
   uart_fifo_enable        = 0;


   la_data_in[1] = 1;
   la_data_in[2] = 1;
   la_data_in[3] = 1;
   la_data_in[15:4] = ((uart_divisor+1)/16)-1;
   la_data_in[17:16] = 2'b00;

   #100;
   wb_rst_i <= 1'b0;

   $display("Monitor: Standalone User Uart master Test Started");

   tb_master_uart.debug_mode = 0;
   tb_master_uart.uart_init;
   tb_master_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, 
	                          uart_stick_parity, uart_timeout, uart_divisor);


   flag = 0;
   while(flag == 0)
   begin
        tb_master_uart.read_char(read_data,flag);
        $write ("%c",read_data);
   end




   uartm_reg_write('h3080_0000,'h1);

   repeat (2) @(posedge clock);
   #1;

   $display("Monitor: Writing  expected value");
   
   test_fail = 0;
   uartm_reg_read_check(32'h30000000,32'h44332211);
   uartm_reg_read_check(32'h30000004,32'hDDCCBBAA);

   uartm_reg_write(32'h30020000,32'h11223344);
   uartm_reg_write(32'h30020004,32'h22334455);

   uartm_reg_read_check(32'h30000000,32'h11223344);
   uartm_reg_read_check(32'h30000004,32'h22334455);
   
   
   
   $display("###################################################");
   if(test_fail == 0) begin
      `ifdef GL
          $display("Monitor: Standalone User UART Master (GL) Passed");
      `else
          $display("Monitor: Standalone User Uart Master (RTL) Passed");
      `endif
   end else begin
       `ifdef GL
           $display("Monitor: Standalone User Uart Master (GL) Failed");
       `else
           $display("Monitor: Standalone User Uart Master (RTL) Failed");
       `endif
    end
   $display("###################################################");
   #100
   $finish;
end


wire USER_VDD1V8 = 1'b1;
wire VSS = 1'b0;


user_project_wrapper u_top(
`ifdef USE_POWER_PINS
    .vccd1(USER_VDD1V8),
    .vssd1(VSS),
`endif
    .wb_clk_i        (clock),
    .user_clock2     (1'b1),
    .wb_rst_i        (wb_rst_i),

    .wbs_cyc_i   (wbd_ext_cyc_i),
    .wbs_stb_i   (wbd_ext_stb_i),
    .wbs_adr_i   (wbd_ext_adr_i),
    .wbs_we_i    (wbd_ext_we_i),
    .wbs_dat_i   (wbd_ext_dat_i),
    .wbs_sel_i   (wbd_ext_sel_i),

    .wbs_dat_o   (wbd_ext_dat_o),
    .wbs_ack_o   (wbd_ext_ack_o),

 

    .la_data_in      (la_data_in) ,
    .la_data_out     (),
    .la_oenb         ('0),
 


    .io_in          (io_in)  ,
    .io_out         (io_out) ,
    .io_oeb         (io_oeb) ,

    .user_irq       () 

);

`ifndef GL

    initial begin
    end
`endif    





wire uart_txd,uart_rxd;

assign uart_txd   = io_out[1];
assign io_in[0]  = uart_rxd ;
 
uart_agent tb_master_uart(
	.mclk                (clock              ),
	.txd                 (uart_rxd           ),
	.rxd                 (uart_txd           )
	);



`include "uart_master_tasks.sv"
endmodule