data/full_repos/permissive/437141606/MIPS.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/437141606/MIPS.v:259: Signal definition not found, creating implicitly: \'zero\'\n controller controller(instrD[31:26], instrD[5:0], zero,\n                                                   ^~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/437141606/MIPS.v:313: Unsized numbers/parameters not allowed in concatenations.\n                                                                     : ... In instance mips.decode.rf\n    rf[{0,wa3[3:0]}] <= wd3;\n        ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/437141606/MIPS.v:313: Unsized numbers/parameters not allowed in replications.\n                                                                     : ... In instance mips.decode.rf\n    rf[{0,wa3[3:0]}] <= wd3;\n         ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/437141606/MIPS.v:315: Unsized numbers/parameters not allowed in concatenations.\n                                                                     : ... In instance mips.decode.rf\n    rf[{1,wa3[3:0]}] <= wd3;\n        ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/437141606/MIPS.v:315: Unsized numbers/parameters not allowed in replications.\n                                                                     : ... In instance mips.decode.rf\n    rf[{1,wa3[3:0]}] <= wd3;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/437141606/MIPS.v:179: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                               : ... In instance mips.excute.alu\n assign sum = a + b2 + alucont[2];\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/437141606/MIPS.v:180: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n                                                               : ... In instance mips.excute.alu\n assign slt = sum[31];\n            ^\n%Warning-WIDTH: data/full_repos/permissive/437141606/MIPS.v:134: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'hff\' generates 8 bits.\n                                                               : ... In instance mips.memory.dmem\n   ram[n] = 8\'hFF;\n          ^\n%Warning-WIDTH: data/full_repos/permissive/437141606/MIPS.v:136: Bit extraction of array[63:0] requires 6 bit index, not 30 bits.\n                                                               : ... In instance mips.memory.dmem\n assign dOut = ram[addr[31:2]];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/437141606/MIPS.v:140: Bit extraction of array[63:0] requires 6 bit index, not 30 bits.\n                                                               : ... In instance mips.memory.dmem\n   ram[addr[31:2]] = dIn; \n      ^\n%Error: Exiting due to 10 warning(s)\n'
module decode (input	clk,
			   input[31:0]	pcplus4F, pcplus4D, instrD, resultW,
			   input[4:0]   resultAddW,
			   input		regwriteW,
			   output		memtoregD, memwriteD, alusrcD, regdstD, regwriteD,
							wlhD, memloD, memhiD, jalD,
			   output[2:0]  alucontrolD,
			   output[31:0] rd1D, rd2D, signimmD, pcnextD,
			   input[4:0] 	dispSel,
			   output[31:0] dispDat);
			   
	wire[31:0] signimmDsh, pcnextbrD, pcjumpD, pcbranchD;
	wire	pcsrcD, jumpD, jraD;
	
	
	controller controller(instrD[31:26], instrD[5:0], zero,
						  memtoregD, memwriteD, pcsrcD,
						  alusrcD, regdstD, regwriteD, jumpD,
						  alucontrolD,wlhD, memloD, memhiD, jraD, jalD);
	equal	equal (rd1D, rd2D, zero);
	regfile	rf	  (clk, regwriteW, instrD[25:21], instrD[20:16], resultAddW, resultW, rd1D, rd2D, dispSel, dispDat);
	signext	se	  (instrD[15:0], signimmD);
	sl2     immsh (signimmD, signimmDsh);
	adder   pcadd2(pcplus4D, signimmDsh, pcbranchD);

	mux2 #(32)  pcbrmux(pcplus4F, pcbranchD, pcsrcD, pcnextbrD);
	mux2 #(32)  pcjmux(pcnextbrD, {pcplus4D[31:28], instrD[25:0], 2'b00}, jumpD, pcjumpD);
	mux2 #(32)	pcmux(pcjumpD, rd1D, jraD, pcnextD);
	
endmodule
module decode (input	clk,
			   input[31:0]	pcplus4F, pcplus4D, instrD, resultW,
			   input[4:0]   resultAddW,
			   input		regwriteW,
			   output		memtoregD, memwriteD, alusrcD, regdstD, regwriteD,
							wlhD, memloD, memhiD, jalD,
			   output[2:0]  alucontrolD,
			   output[31:0] rd1D, rd2D, signimmD, pcnextD,
			   input[4:0] 	dispSel,
			   output[31:0] dispDat);

			   
	wire[31:0] signimmDsh, pcnextbrD, pcjumpD, pcbranchD;
	wire	pcsrcD, jumpD, jraD;
	
	
	controller controller(instrD[31:26], instrD[5:0], zero,
						  memtoregD, memwriteD, pcsrcD,
						  alusrcD, regdstD, regwriteD, jumpD,
						  alucontrolD,wlhD, memloD, memhiD, jraD, jalD);
	equal	equal (rd1D, rd2D, zero);
	regfile	rf	  (clk, regwriteW, instrD[25:21], instrD[20:16], resultAddW, resultW, rd1D, rd2D, dispSel, dispDat);
	signext	se	  (instrD[15:0], signimmD);
	sl2     immsh (signimmD, signimmDsh);
	adder   pcadd2(pcplus4D, signimmDsh, pcbranchD);

	mux2 #(32)  pcbrmux(pcplus4F, pcbranchD, pcsrcD, pcnextbrD);
	mux2 #(32)  pcjmux(pcnextbrD, {pcplus4D[31:28], instrD[25:0], 2'b00}, jumpD, pcjumpD);
	mux2 #(32)	pcmux(pcjumpD, rd1D, jraD, pcnextD);
	
endmodule