data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/rtl/alu/compare/equality_Nb.v
data/verilator_xmls/66602210-1fac-4744-9d0e-5e72a6c64976.xml
module equality_Nb #(parameter N = 32) (
	input  [N-1:0] a,
	input  [N-1:0] b,
	output         r
);

wire [N-1:0] w;

assign w = a ^ b;
assign r = ~( |w );

endmodule
module equality_Nb #(parameter N = 32) (
	input  [N-1:0] a,
	input  [N-1:0] b,
	output         r
);


wire [N-1:0] w;

assign w = a ^ b;
assign r = ~( |w );

endmodule