data/full_repos/permissive/518304282/iiitb_rtc.v
data/verilator_xmls/9fd4bca6-5cb2-42cd-ab00-83fca15efb93.xml
module counter #(parameter max_value=15) (
input clk,rst,clr,en,
output reg [3:0] count);
initial
count=4'b0;
always @(posedge clk)
begin
if(rst==0) count <=4'd0;
else if(clr==1) count<=4'd0;
else
begin
if(en==1)
if(count==max_value) count<=4'd0;
else count<=count+1;
else count<=count;
end
end
endmodule
module counter #(parameter max_value=15) (
input clk,rst,clr,en,
output reg [3:0] count);

initial
count=4'b0;
always @(posedge clk)
begin
if(rst==0) count <=4'd0;
else if(clr==1) count<=4'd0;
else
begin
if(en==1)
if(count==max_value) count<=4'd0;
else count<=count+1;
else count<=count;
end
end
endmodule