data/full_repos/permissive/496903659/086 dff16e.v
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/496903659/086\n        ... Looked in:\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/086\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/086.v\n             data/full_repos/permissive/496903659,data/full_repos/permissive/496903659/data/full_repos/permissive/496903659/086.sv\n             data/full_repos/permissive/496903659/086\n             data/full_repos/permissive/496903659/086.v\n             data/full_repos/permissive/496903659/086.sv\n             obj_dir/data/full_repos/permissive/496903659/086\n             obj_dir/data/full_repos/permissive/496903659/086.v\n             obj_dir/data/full_repos/permissive/496903659/086.sv\n%Error: Cannot find file containing module: dff16e.v\n%Error: Exiting due to 2 error(s)\n'
module top_module (
    input clk,
    input resetn,
    input [1:0] byteena,
    input [15:0] d,
    output [15:0] q
);
    always @(posedge clk) begin
        if(!resetn)
            q[15:0] <= 0;
        else begin
            if(!byteena[1])
                q[15:8] <= q[15:8];
            else
                q[15:8] <= d[15:8];

            if(!byteena[0])
                q[7:0] <= q[7:0];
            else
                q[7:0] <= d[7:0];
        end
    end

endmodule
module top_module (
    input clk,
    input resetn,
    input [1:0] byteena,
    input [15:0] d,
    output [15:0] q
);

    always @(posedge clk) begin
        if(!resetn)
            q[15:0] <= 0;
        else begin
            if(!byteena[1])
                q[15:8] <= q[15:8];
            else
                q[15:8] <= d[15:8];

            if(!byteena[0])
                q[7:0] <= q[7:0];
            else
                q[7:0] <= d[7:0];
        end
    end

endmodule