data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy/Modules and vectors.v
1: b'%Error: Cannot find file containing module: and\n        ... Looked in:\n             data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy,data/full_repos/permissive/463549945/and\n             data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy,data/full_repos/permissive/463549945/and.v\n             data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy,data/full_repos/permissive/463549945/and.sv\n             and\n             and.v\n             and.sv\n             obj_dir/and\n             obj_dir/and.v\n             obj_dir/and.sv\n%Error: Cannot find file containing module: vectors.v\n%Error: Exiting due to 2 error(s)\n'
module top_module ( 
    input clk, 
    input [7:0] d, 
    input [1:0] sel, 
    output [7:0] q 
);
    
endmodule
module top_module ( 
    input clk, 
    input [7:0] d, 
    input [1:0] sel, 
    output [7:0] q 
);

    
endmodule