data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/MICROBENCHMARKS/bm_lpm_concat.v
1: b"%Error: data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/MICROBENCHMARKS/bm_lpm_concat.v:16: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/MICROBENCHMARKS/bm_lpm_concat.v:44: syntax error, unexpected assign\nassign out1 = {1'b0, a};\n^~~~~~\n%Error: Exiting due to 2 error(s)\n"
module 	bm_lpm_concat(clock, 
		reset_n, 
		a, 
		b, 
		out1,
		out2,
		out3,
		out4,
		out5,
		out6,
		out7,
		out8,
);


input	clock;
input 	reset_n;

input [`BITS-9:0] a;
input [`BITS-9:0] b;

output [`BITS-8:0] out1;
output [`BITS-7:0] out2;
output [`BITS-6:0] out3;
output [`BITS-5:0] out4;
output [`BITS-4:0] out5;
output [`BITS-3:0] out6;
output [`BITS-2:0] out7;
output [`BITS-1:0] out8;

wire [`BITS-8:0]    out1;
wire [`BITS-7:0]    out2;
wire [`BITS-6:0]    out3;
wire [`BITS-5:0]    out4;
wire [`BITS-4:0]    out5;
wire [`BITS-3:0]    out6;
wire [`BITS-2:0]    out7;
wire [`BITS-1:0]    out8;


assign out1 = {1'b0, a};
assign out2 = {1'b1, 1'b0, b}; 
assign out3 = {1'b1, 1'b1, out1};
assign out4 = {1'b0, out3};
assign out5 = {1'b1, out4};
assign out6 = {1'b0, out5};
assign out7 = {1'b1, out6};
assign out8 = {1'b0, out7};

endmodule
module 	bm_lpm_concat(clock, 
		reset_n, 
		a, 
		b, 
		out1,
		out2,
		out3,
		out4,
		out5,
		out6,
		out7,
		out8,
);



input	clock;
input 	reset_n;

input [`BITS-9:0] a;
input [`BITS-9:0] b;

output [`BITS-8:0] out1;
output [`BITS-7:0] out2;
output [`BITS-6:0] out3;
output [`BITS-5:0] out4;
output [`BITS-4:0] out5;
output [`BITS-3:0] out6;
output [`BITS-2:0] out7;
output [`BITS-1:0] out8;

wire [`BITS-8:0]    out1;
wire [`BITS-7:0]    out2;
wire [`BITS-6:0]    out3;
wire [`BITS-5:0]    out4;
wire [`BITS-4:0]    out5;
wire [`BITS-3:0]    out6;
wire [`BITS-2:0]    out7;
wire [`BITS-1:0]    out8;


assign out1 = {1'b0, a};
assign out2 = {1'b1, 1'b0, b}; 
assign out3 = {1'b1, 1'b1, out1};
assign out4 = {1'b0, out3};
assign out5 = {1'b1, out4};
assign out6 = {1'b0, out5};
assign out7 = {1'b1, out6};
assign out8 = {1'b0, out7};

endmodule