data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Counters/ece241_2014_q7a/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Counters/ece241_2014_q7a,data/full_repos/permissive/500128826\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/ece241_2014_q7a,data/full_repos/permissive/500128826\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/ece241_2014_q7a,data/full_repos/permissive/500128826.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Counters/ece241_2014_q7a,data/full_repos/permissive/500128826.sv\n             Logic/Counters/ece241_2014_q7a,data/full_repos/permissive/500128826\n             Logic/Counters/ece241_2014_q7a,data/full_repos/permissive/500128826.v\n             Logic/Counters/ece241_2014_q7a,data/full_repos/permissive/500128826.sv\n             obj_dir/Logic/Counters/ece241_2014_q7a,data/full_repos/permissive/500128826\n             obj_dir/Logic/Counters/ece241_2014_q7a,data/full_repos/permissive/500128826.v\n             obj_dir/Logic/Counters/ece241_2014_q7a,data/full_repos/permissive/500128826.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Logic/Counters/ece241_2014_q7a/top_module.v\n%Error: Exiting due to 3 error(s)\n'
module top_module (
    input wire clk,
    input wire reset,
    input wire enable,
    output wire [3:0] Q,
    output wire c_enable,
    output wire c_load,
    output wire [3:0] c_d
);

  wire counter_load;
  wire counter_enable;
  reg [3:0] counter_d = 4'd1;

  count4 the_counter (
      .clk(clk),
      .enable(counter_enable),
      .load(counter_load),
      .d(counter_d),
      .Q(Q)
  );

  assign counter_enable = enable;
  assign counter_load = (Q == 4'd12 & counter_enable) | reset;

  assign c_enable = counter_enable;
  assign c_load = counter_load;
  assign c_d = counter_d;

endmodule
module top_module (
    input wire clk,
    input wire reset,
    input wire enable,
    output wire [3:0] Q,
    output wire c_enable,
    output wire c_load,
    output wire [3:0] c_d
);


  wire counter_load;
  wire counter_enable;
  reg [3:0] counter_d = 4'd1;

  count4 the_counter (
      .clk(clk),
      .enable(counter_enable),
      .load(counter_load),
      .d(counter_d),
      .Q(Q)
  );

  assign counter_enable = enable;
  assign counter_load = (Q == 4'd12 & counter_enable) | reset;

  assign c_enable = counter_enable;
  assign c_load = counter_load;
  assign c_d = counter_d;

endmodule