data/full_repos/permissive/504762811/alu.v
1: b'%Error: data/full_repos/permissive/504762811/alu.v:1: Cannot find include file: minicpu.h\n`include "minicpu.h" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/504762811,data/full_repos/permissive/504762811/minicpu.h\n             data/full_repos/permissive/504762811,data/full_repos/permissive/504762811/minicpu.h.v\n             data/full_repos/permissive/504762811,data/full_repos/permissive/504762811/minicpu.h.sv\n             minicpu.h\n             minicpu.h.v\n             minicpu.h.sv\n             obj_dir/minicpu.h\n             obj_dir/minicpu.h.v\n             obj_dir/minicpu.h.sv\n%Error: data/full_repos/permissive/504762811/alu.v:8: Define or directive not defined: \'`DataBus\'\n    input wire [`DataBus] A,\n                ^~~~~~~~\n%Error: data/full_repos/permissive/504762811/alu.v:8: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input wire [`DataBus] A,\n                        ^\n%Error: data/full_repos/permissive/504762811/alu.v:9: Define or directive not defined: \'`DataBus\'\n    input wire [`DataBus] B,   \n                ^~~~~~~~\n%Error: data/full_repos/permissive/504762811/alu.v:10: Define or directive not defined: \'`DataBus\'\n    output reg [`DataBus] E,  \n                ^~~~~~~~\n%Error: data/full_repos/permissive/504762811/alu.v:12: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg [1:0] cc   \n    ^~~~~~\n%Error: data/full_repos/permissive/504762811/alu.v:13: syntax error, unexpected \')\', expecting \',\' or \';\'\n);        \n^\n%Error: Exiting due to 7 error(s)\n'
module ALU (
    input wire [`DataBus] A,
    input wire [`DataBus] B,
    output reg [`DataBus] E,  
	input wire [3:0] op,
    output reg [1:0] cc
);
	always @(*) begin
		E = 8'hxx;
		cc = 2'bxx;
		case (op)
			4'h0 : E = A + B;
			4'h1 : begin
				E = A - B;
				cc = {!E, $signed(E)>0};
			end
			4'h3 : E = B + 1;
			4'h4 : E = B - 1;
			endcase
		end
endmodule
module ALU (
    input wire [`DataBus] A,
    input wire [`DataBus] B,
    output reg [`DataBus] E,  
	input wire [3:0] op,
    output reg [1:0] cc
);

	always @(*) begin
		E = 8'hxx;
		cc = 2'bxx;
		case (op)
			4'h0 : E = A + B;
			4'h1 : begin
				E = A - B;
				cc = {!E, $signed(E)>0};
			end
			4'h3 : E = B + 1;
			4'h4 : E = B - 1;
			endcase
		end
endmodule