data/full_repos/permissive/519811862/password_based_lock_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/519811862/password_based_lock_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n forever #10 clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/519811862/password_based_lock_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n #40 in=\'h14343542;  \n ^\n%Warning-STMTDLY: data/full_repos/permissive/519811862/password_based_lock_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n #40 in=\'h1242adcb;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/519811862/password_based_lock_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n #40 in=\'h1234abcd;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/519811862/password_based_lock_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n #40 in=\'h14343542;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/519811862/password_based_lock_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n #40 in=\'h12345678; reset=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/519811862/password_based_lock_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n #40 in=\'h12342378; reset=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/519811862/password_based_lock_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n #40 in=\'h1234abcd;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/519811862/password_based_lock_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #40 in=\'h12345678;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/519811862/password_based_lock_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #40 in=\'h12acfe38; reset=1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/519811862/password_based_lock_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n #40 in=\'h12345678; reset=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/519811862/password_based_lock_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #40 in=\'h1242adcb;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/519811862/password_based_lock_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n #40 in=\'h1234abcd; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/519811862/password_based_lock_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #10 $stop;\n ^\n%Error: data/full_repos/permissive/519811862/password_based_lock_tb.v:31: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("dump.vcd"); $dumpvars;\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/519811862/password_based_lock_tb.v:31: Unsupported or unknown PLI call: $dumpvars\n    $dumpfile("dump.vcd"); $dumpvars;\n                           ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/519811862/password_based_lock_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #400 $finish;\n    ^\n%Error: Exiting due to 2 error(s), 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
wire access,alarm;
reg [31:0]in;
reg clk,reset;
reg[2:0] current_state, next_state;
  password p0(access,alarm,in,reset,clk);
 

initial begin
 clk = 0;
 forever #10 clk = ~clk;
 end

initial begin
	 in='h12345678;reset=0;
	#40 in='h14343542;  
	#40 in='h1242adcb;
	#40 in='h1234abcd;
	#40 in='h14343542;
	#40 in='h12345678;	reset=1;
	#40 in='h12342378;	reset=0;
	#40 in='h1234abcd;
	#40 in='h12345678;
	#40 in='h12acfe38;	reset=1;
	#40 in='h12345678;	reset=0;
	#40 in='h1242adcb;
	#40 in='h1234abcd;	
	#10 $stop;
end
initial begin
    $dumpfile("dump.vcd"); $dumpvars;
    #400 $finish;
 end

endmodule
module testbench;

wire access,alarm;
reg [31:0]in;
reg clk,reset;
reg[2:0] current_state, next_state;
  password p0(access,alarm,in,reset,clk);
 

initial begin
 clk = 0;
 forever #10 clk = ~clk;
 end

initial begin
	 in='h12345678;reset=0;
	#40 in='h14343542;  
	#40 in='h1242adcb;
	#40 in='h1234abcd;
	#40 in='h14343542;
	#40 in='h12345678;	reset=1;
	#40 in='h12342378;	reset=0;
	#40 in='h1234abcd;
	#40 in='h12345678;
	#40 in='h12acfe38;	reset=1;
	#40 in='h12345678;	reset=0;
	#40 in='h1242adcb;
	#40 in='h1234abcd;	
	#10 $stop;
end
initial begin
    $dumpfile("dump.vcd"); $dumpvars;
    #400 $finish;
 end

endmodule