data/full_repos/permissive/437654144/width_convert/up_width_conv.v
1: b'%Warning-WIDTH: data/full_repos/permissive/437654144/width_convert/up_width_conv.v:96: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                     : ... In instance up_width_conv\n            temp_din   <= {DOUT_WIDTH{1\'b0}};\n                       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/437654144/width_convert/up_width_conv.v:97: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 4 bits.\n                                                                                     : ... In instance up_width_conv\n            temp_strb  <= {DOUT_WIDTH/8{1\'b0}};\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/437654144/width_convert/up_width_conv.v:129: Operator EQ expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'data_cnt\' generates 2 bits.\n                                                                                      : ... In instance up_width_conv\n                        if ((data_cnt == WIDTH_RATIO - 1) || din_last || (temp_valid & temp_last)) begin\n                                      ^~\n%Error: Exiting due to 3 warning(s)\n'
module up_width_conv #
(
    parameter DIN_WIDTH  = 8,
    parameter DOUT_WIDTH = 32
)
(
    input   wire                            clk,
    input   wire                            cen,
    input   wire                            rstn,
    
    input   wire    [DIN_WIDTH - 1:0]       din,
    input   wire    [DIN_WIDTH/8 - 1:0]     din_strb,
    input   wire                            din_last,
    input   wire                            din_valid,
    output  reg                             din_ready,
    
    output  reg     [DOUT_WIDTH - 1:0]      dout,
    output  reg     [DOUT_WIDTH/8 - 1:0]    dout_strb,
    output  reg                             dout_last,
    output  reg                             dout_valid,
    input   wire                            dout_ready
);



    generate
        if ((DIN_WIDTH  < 1)                ||
            (DOUT_WIDTH < 1)                ||
            ((DOUT_WIDTH % 8) != 0)         ||
            ((DIN_WIDTH  % 8) != 0)         ||
            (DOUT_WIDTH <= DIN_WIDTH)       ||
            ((DOUT_WIDTH % DIN_WIDTH) != 0)) begin

            INVALID_PARAMETER invalid_parameters_msg();
        end
    endgenerate



    function integer clog2;
        input integer value;
        integer i;
        begin
            clog2 = 0;
            for (i = 0; 2**i < value; i = i + 1) begin
                clog2 = i + 1;
            end
        end
    endfunction


    
    localparam  WIDTH_RATIO = DOUT_WIDTH / DIN_WIDTH;
    localparam  DATA_CNT_WIDTH = clog2(WIDTH_RATIO);
    
    
    reg     [DIN_WIDTH - 1:0]       temp_din;
    reg     [DIN_WIDTH/8 - 1:0]     temp_strb;
    reg                             temp_last;
    reg                             temp_valid;
    reg     [DATA_CNT_WIDTH - 1:0]  data_cnt;
    
    wire [3:0] state = { din_valid,  din_ready,  dout_valid,  dout_ready};
    
    
    always @(posedge clk or negedge rstn) begin
        if (~rstn) begin
            dout       <= {DOUT_WIDTH{1'b0}};
            dout_strb  <= {DOUT_WIDTH/8{1'b0}};
            dout_last  <= 1'b0;
            dout_valid <= 1'b0;
            
            temp_din   <= {DOUT_WIDTH{1'b0}};
            temp_strb  <= {DOUT_WIDTH/8{1'b0}};
            temp_last  <= 1'b0;
            temp_valid <= 1'b0;
            
            data_cnt   <= {DATA_CNT_WIDTH{1'b0}};
            din_ready  <= 1'b1;
        end else begin
            if (cen) begin
                case (4'b1111)
                    

                    {~din_valid, ~din_ready, ~dout_valid, ~dout_ready},
                    {~din_valid, ~din_ready, ~dout_valid,  dout_ready},
                    { din_valid, ~din_ready, ~dout_valid, ~dout_ready},
                    { din_valid, ~din_ready, ~dout_valid,  dout_ready}: begin
                        din_ready <= 1'b1;
                    end
                    

                    { din_valid,  din_ready, ~dout_valid, ~dout_ready},
                    { din_valid,  din_ready, ~dout_valid,  dout_ready}: begin
                        if (temp_valid) begin
                            temp_valid <= 1'b0;
                            dout[0 +: DIN_WIDTH]        <= temp_din;
                            dout_strb[0 +: DIN_WIDTH/8] <= temp_strb;
                            dout_last                   <= temp_last;
                        end
                        
                        dout[DIN_WIDTH * data_cnt +: DIN_WIDTH] <= din;
                        dout_strb[DIN_WIDTH/8 * data_cnt +: DIN_WIDTH/8] <= din_strb;
                        dout_last  <= din_last;
                        
                        if ((data_cnt == WIDTH_RATIO - 1) || din_last || (temp_valid & temp_last)) begin
                            data_cnt   <= {DATA_CNT_WIDTH{1'b0}};
                            dout_valid <= 1'b1;
                        end else begin
                            data_cnt <= data_cnt + 1'b1;
                        end
                    end
                    

                    {~din_valid, ~din_ready,  dout_valid,  dout_ready},
                    { din_valid, ~din_ready,  dout_valid,  dout_ready},
                    

                    {~din_valid,  din_ready,  dout_valid,  dout_ready}: begin
                        din_ready  <= 1'b1;
                        dout       <= {DOUT_WIDTH{1'b0}};
                        dout_strb  <= {DOUT_WIDTH/8{1'b0}};
                        dout_last  <= 1'b0;
                        dout_valid <= 1'b0;
                    end
                    

                    { din_valid,  din_ready,  dout_valid, ~dout_ready}: begin
                        temp_din   <= din;
                        temp_strb  <= din_strb;
                        temp_last  <= din_last;
                        temp_valid <= 1'b1;
                        data_cnt   <= 'd1;
                        din_ready  <= 1'b0;
                    end
                    

                    { din_valid,  din_ready,  dout_valid,  dout_ready}: begin
                        dout       <= {DOUT_WIDTH{1'b0}};
                        dout_strb  <= {DOUT_WIDTH/8{1'b0}};
                        dout_last  <= 1'b0;
                        
                        dout[DIN_WIDTH * data_cnt +: DIN_WIDTH] <= din;
                        dout_strb[DIN_WIDTH/8 * data_cnt +: DIN_WIDTH/8] <= din_strb;
                        dout_last <= din_last;
                        
                        if (~din_last) begin
                            data_cnt   <= 'd1;
                            dout_valid <= 1'b0;
                        end
                    end
                    

                    {~din_valid, ~din_ready,  dout_valid, ~dout_ready},
                    { din_valid, ~din_ready,  dout_valid, ~dout_ready},
                    

                    {~din_valid,  din_ready,  dout_valid, ~dout_ready},
                    

                    {~din_valid,  din_ready, ~dout_valid, ~dout_ready},
                    {~din_valid,  din_ready, ~dout_valid,  dout_ready}: begin

                    end
                    
                endcase
            end
        end
    end
    

    
endmodule
module up_width_conv #
(
    parameter DIN_WIDTH  = 8,
    parameter DOUT_WIDTH = 32
)
(
    input   wire                            clk,
    input   wire                            cen,
    input   wire                            rstn,
    
    input   wire    [DIN_WIDTH - 1:0]       din,
    input   wire    [DIN_WIDTH/8 - 1:0]     din_strb,
    input   wire                            din_last,
    input   wire                            din_valid,
    output  reg                             din_ready,
    
    output  reg     [DOUT_WIDTH - 1:0]      dout,
    output  reg     [DOUT_WIDTH/8 - 1:0]    dout_strb,
    output  reg                             dout_last,
    output  reg                             dout_valid,
    input   wire                            dout_ready
);




    generate
        if ((DIN_WIDTH  < 1)                ||
            (DOUT_WIDTH < 1)                ||
            ((DOUT_WIDTH % 8) != 0)         ||
            ((DIN_WIDTH  % 8) != 0)         ||
            (DOUT_WIDTH <= DIN_WIDTH)       ||
            ((DOUT_WIDTH % DIN_WIDTH) != 0)) begin

            INVALID_PARAMETER invalid_parameters_msg();
        end
    endgenerate



    function integer clog2;
        input integer value;
        integer i;
        begin
            clog2 = 0;
            for (i = 0; 2**i < value; i = i + 1) begin
                clog2 = i + 1;
            end
        end
    endfunction


    
    localparam  WIDTH_RATIO = DOUT_WIDTH / DIN_WIDTH;
    localparam  DATA_CNT_WIDTH = clog2(WIDTH_RATIO);
    
    
    reg     [DIN_WIDTH - 1:0]       temp_din;
    reg     [DIN_WIDTH/8 - 1:0]     temp_strb;
    reg                             temp_last;
    reg                             temp_valid;
    reg     [DATA_CNT_WIDTH - 1:0]  data_cnt;
    
    wire [3:0] state = { din_valid,  din_ready,  dout_valid,  dout_ready};
    
    
    always @(posedge clk or negedge rstn) begin
        if (~rstn) begin
            dout       <= {DOUT_WIDTH{1'b0}};
            dout_strb  <= {DOUT_WIDTH/8{1'b0}};
            dout_last  <= 1'b0;
            dout_valid <= 1'b0;
            
            temp_din   <= {DOUT_WIDTH{1'b0}};
            temp_strb  <= {DOUT_WIDTH/8{1'b0}};
            temp_last  <= 1'b0;
            temp_valid <= 1'b0;
            
            data_cnt   <= {DATA_CNT_WIDTH{1'b0}};
            din_ready  <= 1'b1;
        end else begin
            if (cen) begin
                case (4'b1111)
                    

                    {~din_valid, ~din_ready, ~dout_valid, ~dout_ready},
                    {~din_valid, ~din_ready, ~dout_valid,  dout_ready},
                    { din_valid, ~din_ready, ~dout_valid, ~dout_ready},
                    { din_valid, ~din_ready, ~dout_valid,  dout_ready}: begin
                        din_ready <= 1'b1;
                    end
                    

                    { din_valid,  din_ready, ~dout_valid, ~dout_ready},
                    { din_valid,  din_ready, ~dout_valid,  dout_ready}: begin
                        if (temp_valid) begin
                            temp_valid <= 1'b0;
                            dout[0 +: DIN_WIDTH]        <= temp_din;
                            dout_strb[0 +: DIN_WIDTH/8] <= temp_strb;
                            dout_last                   <= temp_last;
                        end
                        
                        dout[DIN_WIDTH * data_cnt +: DIN_WIDTH] <= din;
                        dout_strb[DIN_WIDTH/8 * data_cnt +: DIN_WIDTH/8] <= din_strb;
                        dout_last  <= din_last;
                        
                        if ((data_cnt == WIDTH_RATIO - 1) || din_last || (temp_valid & temp_last)) begin
                            data_cnt   <= {DATA_CNT_WIDTH{1'b0}};
                            dout_valid <= 1'b1;
                        end else begin
                            data_cnt <= data_cnt + 1'b1;
                        end
                    end
                    

                    {~din_valid, ~din_ready,  dout_valid,  dout_ready},
                    { din_valid, ~din_ready,  dout_valid,  dout_ready},
                    

                    {~din_valid,  din_ready,  dout_valid,  dout_ready}: begin
                        din_ready  <= 1'b1;
                        dout       <= {DOUT_WIDTH{1'b0}};
                        dout_strb  <= {DOUT_WIDTH/8{1'b0}};
                        dout_last  <= 1'b0;
                        dout_valid <= 1'b0;
                    end
                    

                    { din_valid,  din_ready,  dout_valid, ~dout_ready}: begin
                        temp_din   <= din;
                        temp_strb  <= din_strb;
                        temp_last  <= din_last;
                        temp_valid <= 1'b1;
                        data_cnt   <= 'd1;
                        din_ready  <= 1'b0;
                    end
                    

                    { din_valid,  din_ready,  dout_valid,  dout_ready}: begin
                        dout       <= {DOUT_WIDTH{1'b0}};
                        dout_strb  <= {DOUT_WIDTH/8{1'b0}};
                        dout_last  <= 1'b0;
                        
                        dout[DIN_WIDTH * data_cnt +: DIN_WIDTH] <= din;
                        dout_strb[DIN_WIDTH/8 * data_cnt +: DIN_WIDTH/8] <= din_strb;
                        dout_last <= din_last;
                        
                        if (~din_last) begin
                            data_cnt   <= 'd1;
                            dout_valid <= 1'b0;
                        end
                    end
                    

                    {~din_valid, ~din_ready,  dout_valid, ~dout_ready},
                    { din_valid, ~din_ready,  dout_valid, ~dout_ready},
                    

                    {~din_valid,  din_ready,  dout_valid, ~dout_ready},
                    

                    {~din_valid,  din_ready, ~dout_valid, ~dout_ready},
                    {~din_valid,  din_ready, ~dout_valid,  dout_ready}: begin

                    end
                    
                endcase
            end
        end
    end
    

    
endmodule