data/full_repos/permissive/493019833/test/testcase/firrtl/Complex2R1WSMem/reference/Complex2R1WSMem.v
data/verilator_xmls/28864c4a-cb47-4a3c-afc3-7052dc080c91.xml
module BITS(y, in);
    parameter width = 4;
    parameter high = 2;
    parameter low = 0;
    output [high-low:0] y;
    input [width-1:0] in;
    assign y = in[high:low];
endmodule
module BITS(y, in);

    parameter width = 4;
    parameter high = 2;
    parameter low = 0;
    output [high-low:0] y;
    input [width-1:0] in;
    assign y = in[high:low];
endmodule