data/full_repos/permissive/491135068/zeroreg.v
data/verilator_xmls/56a75ca3-d4d5-43a4-b43e-21c272543c6e.xml
module zeroreg(Dselect, D, Q);
    input [31:0] D;
    input Dselect;
    output [31:0] Q;
    
    assign Q = 32'b0;
endmodule
module zeroreg(Dselect, D, Q);

    input [31:0] D;
    input Dselect;
    output [31:0] Q;
    
    assign Q = 32'b0;
endmodule