data/full_repos/permissive/515477729/source/booth_datapath.v
1: b"%Error: data/full_repos/permissive/515477729/source/booth_datapath.v:9: Cannot find file containing module: 'alu'\n    alu a0 (Z, A, M, addsub);\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/515477729/source,data/full_repos/permissive/515477729/alu\n             data/full_repos/permissive/515477729/source,data/full_repos/permissive/515477729/alu.v\n             data/full_repos/permissive/515477729/source,data/full_repos/permissive/515477729/alu.sv\n             alu\n             alu.v\n             alu.sv\n             obj_dir/alu\n             obj_dir/alu.v\n             obj_dir/alu.sv\n%Error: data/full_repos/permissive/515477729/source/booth_datapath.v:12: Cannot find file containing module: 'dff'\n    dff d0 (qm1, Q[0], clk, clrff);\n    ^~~\n%Error: data/full_repos/permissive/515477729/source/booth_datapath.v:15: Cannot find file containing module: 'shiftreg'\n    shiftreg Areg (A, Z, A[15], clk, ldA, clrA, sftA);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/515477729/source/booth_datapath.v:16: Cannot find file containing module: 'shiftreg'\n    shiftreg Qreg (Q, data_in, A[0], clk, ldQ, clrQ, sftQ);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/515477729/source/booth_datapath.v:19: Cannot find file containing module: 'pipo'\n    pipo mreg (M, data_in, clk, ldM);\n    ^~~~\n%Error: data/full_repos/permissive/515477729/source/booth_datapath.v:22: Cannot find file containing module: 'counter'\n    counter c0 (count, dec, clk, ldCnt);\n    ^~~~~~~\n%Error: Exiting due to 6 error(s)\n"
module booth_datapath ( input clk, ldA, ldM, ldQ, clrA, clrQ, clrff, sftA, sftQ, addsub, dec, ldCnt, input [15:0] data_in, output q0, qm1, eqz);

    wire [15:0] A, M, Q, Z;
    wire [4:0] count;

    assign eqz = ~|count;
    assign q0 = Q[0];

    alu a0 (Z, A, M, addsub);


    dff d0 (qm1, Q[0], clk, clrff);


    shiftreg Areg (A, Z, A[15], clk, ldA, clrA, sftA);
    shiftreg Qreg (Q, data_in, A[0], clk, ldQ, clrQ, sftQ);


    pipo mreg (M, data_in, clk, ldM);


    counter c0 (count, dec, clk, ldCnt);

endmodule
module booth_datapath ( input clk, ldA, ldM, ldQ, clrA, clrQ, clrff, sftA, sftQ, addsub, dec, ldCnt, input [15:0] data_in, output q0, qm1, eqz);


    wire [15:0] A, M, Q, Z;
    wire [4:0] count;

    assign eqz = ~|count;
    assign q0 = Q[0];

    alu a0 (Z, A, M, addsub);


    dff d0 (qm1, Q[0], clk, clrff);


    shiftreg Areg (A, Z, A[15], clk, ldA, clrA, sftA);
    shiftreg Qreg (Q, data_in, A[0], clk, ldQ, clrQ, sftQ);


    pipo mreg (M, data_in, clk, ldM);


    counter c0 (count, dec, clk, ldCnt);

endmodule