data/full_repos/permissive/447976230/fpga/usrp2/udp/prot_eng_tx.v
1: b"%Error: data/full_repos/permissive/447976230/fpga/usrp2/udp/prot_eng_tx.v:31: Cannot find file containing module: 'fifo_short'\n   fifo_short #(.WIDTH(36)) head_fifo\n   ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp2/udp,data/full_repos/permissive/447976230/fifo_short\n             data/full_repos/permissive/447976230/fpga/usrp2/udp,data/full_repos/permissive/447976230/fifo_short.v\n             data/full_repos/permissive/447976230/fpga/usrp2/udp,data/full_repos/permissive/447976230/fifo_short.sv\n             fifo_short\n             fifo_short.v\n             fifo_short.sv\n             obj_dir/fifo_short\n             obj_dir/fifo_short.v\n             obj_dir/fifo_short.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/udp/prot_eng_tx.v:95: Cannot find file containing module: 'add_onescomp'\n   add_onescomp #(.WIDTH(16)) add_onescomp \n   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/udp/prot_eng_tx.v:121: Cannot find file containing module: 'fifo_short'\n   fifo_short #(.WIDTH(36)) tail_fifo\n   ^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module prot_eng_tx
  #(parameter BASE=0)
   (input clk, input reset, input clear,
    input set_stb, input [7:0] set_addr, input [31:0] set_data,
    input [35:0] datain, input src_rdy_i, output dst_rdy_o,
    output [35:0] dataout, output src_rdy_o, input dst_rdy_i);

   wire 	  src_rdy_int1, dst_rdy_int1;
   wire 	  src_rdy_int2, dst_rdy_int2;
   wire [35:0] 	  data_int1, data_int2;


   fifo_short #(.WIDTH(36)) head_fifo
     (.clk(clk),.reset(reset),.clear(clear),
      .datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
      .dataout(data_int1), .src_rdy_o(src_rdy_int1), .dst_rdy_i(dst_rdy_int1),
      .space(),.occupied() );
   

   reg [31:0] 	  header_ram[0:63];
   reg [3:0] 	  state;
   reg [1:0] 	  port_sel;
   
   always @(posedge clk)
     if(set_stb & ((set_addr & 8'hC0) == BASE))
       header_ram[set_addr[5:0]] <= set_data;

   wire [31:0] 	  header_word = header_ram[{port_sel[1:0],state[3:0]}];

   reg [15:0] 	  pre_checksums [0:3];
   always @(posedge clk)
     if(set_stb & ((set_addr & 8'hCF)== (BASE+7)))
       pre_checksums[set_addr[5:4]] <= set_data[15:0];

   wire [15:0] 	  pre_checksum = pre_checksums[port_sel[1:0]];


   reg [15:0] length;
   wire [15:0] ip_length = length + 28;
   wire [15:0] udp_length = length + 8;
   reg 	       sof_o;
   reg [31:0]  prot_data;
   
   always @(posedge clk)
     if(reset)
       begin
	  state   <= 0;
	  sof_o   <= 0;
       end
     else
       if(src_rdy_int1 & dst_rdy_int2)
	 case(state)
	   0 :
	     begin
		port_sel <= data_int1[18:17];
		length 	<= data_int1[15:0];
		sof_o <= 1;
		if(data_int1[16])
		  state <= 1;
		else
		  state <= 12;
	     end
	   12 :
	     begin
		sof_o <= 0;
		if(data_int1[33])
		  state <= 0;
	     end
	   default :
	     begin
		sof_o 	<= 0;
		state <= state + 1;
	     end
	 endcase

   wire [15:0] ip_checksum;
   add_onescomp #(.WIDTH(16)) add_onescomp 
     (.A(pre_checksum),.B(ip_length),.SUM(ip_checksum));
   reg [15:0]  ip_checksum_reg;
   always @(posedge clk) ip_checksum_reg <= ip_checksum;
   
   always @*
     case(state)
       1 : prot_data <= header_word;
       2 : prot_data <= header_word;
       3 : prot_data <= header_word;
       4 : prot_data <= header_word;
       5 : prot_data <= { header_word[31:16], ip_length };
       6 : prot_data <= header_word;
       7 : prot_data <= { header_word[31:16], (16'hFFFF ^ ip_checksum_reg) };
       8 : prot_data <= header_word;
       9 : prot_data <= header_word;
       10: prot_data <= header_word;
       11: prot_data <= { udp_length, header_word[15:0]};
       default : prot_data <= data_int1[31:0];
     endcase

   assign data_int2 = { data_int1[35:33] & {3{state[3]}},  sof_o, prot_data };
   assign dst_rdy_int1 = dst_rdy_int2 & ((state == 0) | (state == 12));
   assign src_rdy_int2 = src_rdy_int1 & (state != 0);
   

   fifo_short #(.WIDTH(36)) tail_fifo
     (.clk(clk),.reset(reset),.clear(clear),
      .datain(data_int2), .src_rdy_i(src_rdy_int2), .dst_rdy_o(dst_rdy_int2),
      .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i),
      .space(),.occupied() );
   
endmodule
module prot_eng_tx
  #(parameter BASE=0)
   (input clk, input reset, input clear,
    input set_stb, input [7:0] set_addr, input [31:0] set_data,
    input [35:0] datain, input src_rdy_i, output dst_rdy_o,
    output [35:0] dataout, output src_rdy_o, input dst_rdy_i);


   wire 	  src_rdy_int1, dst_rdy_int1;
   wire 	  src_rdy_int2, dst_rdy_int2;
   wire [35:0] 	  data_int1, data_int2;


   fifo_short #(.WIDTH(36)) head_fifo
     (.clk(clk),.reset(reset),.clear(clear),
      .datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
      .dataout(data_int1), .src_rdy_o(src_rdy_int1), .dst_rdy_i(dst_rdy_int1),
      .space(),.occupied() );
   

   reg [31:0] 	  header_ram[0:63];
   reg [3:0] 	  state;
   reg [1:0] 	  port_sel;
   
   always @(posedge clk)
     if(set_stb & ((set_addr & 8'hC0) == BASE))
       header_ram[set_addr[5:0]] <= set_data;

   wire [31:0] 	  header_word = header_ram[{port_sel[1:0],state[3:0]}];

   reg [15:0] 	  pre_checksums [0:3];
   always @(posedge clk)
     if(set_stb & ((set_addr & 8'hCF)== (BASE+7)))
       pre_checksums[set_addr[5:4]] <= set_data[15:0];

   wire [15:0] 	  pre_checksum = pre_checksums[port_sel[1:0]];


   reg [15:0] length;
   wire [15:0] ip_length = length + 28;
   wire [15:0] udp_length = length + 8;
   reg 	       sof_o;
   reg [31:0]  prot_data;
   
   always @(posedge clk)
     if(reset)
       begin
	  state   <= 0;
	  sof_o   <= 0;
       end
     else
       if(src_rdy_int1 & dst_rdy_int2)
	 case(state)
	   0 :
	     begin
		port_sel <= data_int1[18:17];
		length 	<= data_int1[15:0];
		sof_o <= 1;
		if(data_int1[16])
		  state <= 1;
		else
		  state <= 12;
	     end
	   12 :
	     begin
		sof_o <= 0;
		if(data_int1[33])
		  state <= 0;
	     end
	   default :
	     begin
		sof_o 	<= 0;
		state <= state + 1;
	     end
	 endcase

   wire [15:0] ip_checksum;
   add_onescomp #(.WIDTH(16)) add_onescomp 
     (.A(pre_checksum),.B(ip_length),.SUM(ip_checksum));
   reg [15:0]  ip_checksum_reg;
   always @(posedge clk) ip_checksum_reg <= ip_checksum;
   
   always @*
     case(state)
       1 : prot_data <= header_word;
       2 : prot_data <= header_word;
       3 : prot_data <= header_word;
       4 : prot_data <= header_word;
       5 : prot_data <= { header_word[31:16], ip_length };
       6 : prot_data <= header_word;
       7 : prot_data <= { header_word[31:16], (16'hFFFF ^ ip_checksum_reg) };
       8 : prot_data <= header_word;
       9 : prot_data <= header_word;
       10: prot_data <= header_word;
       11: prot_data <= { udp_length, header_word[15:0]};
       default : prot_data <= data_int1[31:0];
     endcase

   assign data_int2 = { data_int1[35:33] & {3{state[3]}},  sof_o, prot_data };
   assign dst_rdy_int1 = dst_rdy_int2 & ((state == 0) | (state == 12));
   assign src_rdy_int2 = src_rdy_int1 & (state != 0);
   

   fifo_short #(.WIDTH(36)) tail_fifo
     (.clk(clk),.reset(reset),.clear(clear),
      .datain(data_int2), .src_rdy_i(src_rdy_int2), .dst_rdy_o(dst_rdy_int2),
      .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i),
      .space(),.occupied() );
   
endmodule