data/full_repos/permissive/468612001/Week06/fsm/tb_fsm.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/468612001/Week06/fsm/tb_fsm.v:8: Unsupported: Ignoring delay on this delayed statement.\n  #15 rst = 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week06/fsm/tb_fsm.v:9: Unsupported: Ignoring delay on this delayed statement.\n  #25 rst = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week06/fsm/tb_fsm.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #10 clk = ~clk;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week06/fsm/tb_fsm.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #100 bypss = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week06/fsm/tb_fsm.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #100 bypss = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/468612001/Week06/fsm/tb_fsm.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #100 $stop;\n  ^\n%Error: data/full_repos/permissive/468612001/Week06/fsm/tb_fsm.v:5: Cannot find file containing module: \'fsm\'\n fsm u0(clk, rst, bypss, out);\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/468612001/Week06/fsm,data/full_repos/permissive/468612001/fsm\n             data/full_repos/permissive/468612001/Week06/fsm,data/full_repos/permissive/468612001/fsm.v\n             data/full_repos/permissive/468612001/Week06/fsm,data/full_repos/permissive/468612001/fsm.sv\n             fsm\n             fsm.v\n             fsm.sv\n             obj_dir/fsm\n             obj_dir/fsm.v\n             obj_dir/fsm.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_fsm();
	reg clk, rst, bypss;
	wire [1:0] out;
	
	fsm u0(clk, rst, bypss, out);
	initial begin
		rst = 1;
		#15 rst = 0;
		#25 rst = 1;
	end
	
	initial begin
		clk = 0;
		forever
		#10 clk = ~clk;
	end
	
	initial begin
		bypss = 0;
		#100 bypss = 1;
		#100 bypss = 0;
		#100 $stop;
	end
endmodule
module tb_fsm();

	reg clk, rst, bypss;
	wire [1:0] out;
	
	fsm u0(clk, rst, bypss, out);
	initial begin
		rst = 1;
		#15 rst = 0;
		#25 rst = 1;
	end
	
	initial begin
		clk = 0;
		forever
		#10 clk = ~clk;
	end
	
	initial begin
		bypss = 0;
		#100 bypss = 1;
		#100 bypss = 0;
		#100 $stop;
	end
endmodule