data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/peripheral_interco/FanInPrimitive_PE_Resp.sv
1: b'%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/peripheral_interco/FanInPrimitive_PE_Resp.sv:48: Cannot find include file: parameters.v\n`include "parameters.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/peripheral_interco,data/full_repos/permissive/489147019/parameters.v\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/peripheral_interco,data/full_repos/permissive/489147019/parameters.v.v\n             data/full_repos/permissive/489147019/Testcases/mempool/rtl/cluster_interconnect/rtl/peripheral_interco,data/full_repos/permissive/489147019/parameters.v.sv\n             parameters.v\n             parameters.v.v\n             parameters.v.sv\n             obj_dir/parameters.v\n             obj_dir/parameters.v.v\n             obj_dir/parameters.v.sv\n%Error: Exiting due to 1 error(s)\n'
module FanInPrimitive_PE_Resp
#(
    parameter DATA_WIDTH = 32
)
(

    input  logic [DATA_WIDTH-1:0]        data_r_rdata0_i,
    input  logic [DATA_WIDTH-1:0]        data_r_rdata1_i,
    input  logic                         data_r_valid0_i,
    input  logic                         data_r_valid1_i,
    input  logic                         data_r_opc0_i,
    input  logic                         data_r_opc1_i,


    output logic [DATA_WIDTH-1:0]        data_r_rdata_o,
    output logic                         data_r_valid_o,
    output logic                         data_r_opc_o
);


    logic                  SEL;


    assign data_r_valid_o = data_r_valid1_i | data_r_valid0_i;


    assign SEL = data_r_valid1_i;



    always_comb
    begin : FanOut_MUX2
        case(SEL) 
          1'b0: begin data_r_rdata_o  = data_r_rdata0_i; data_r_opc_o = data_r_opc0_i; end
          1'b1: begin data_r_rdata_o  = data_r_rdata1_i; data_r_opc_o = data_r_opc1_i; end
        endcase
    end
endmodule
module FanInPrimitive_PE_Resp
#(
    parameter DATA_WIDTH = 32
)
(

    input  logic [DATA_WIDTH-1:0]        data_r_rdata0_i,
    input  logic [DATA_WIDTH-1:0]        data_r_rdata1_i,
    input  logic                         data_r_valid0_i,
    input  logic                         data_r_valid1_i,
    input  logic                         data_r_opc0_i,
    input  logic                         data_r_opc1_i,


    output logic [DATA_WIDTH-1:0]        data_r_rdata_o,
    output logic                         data_r_valid_o,
    output logic                         data_r_opc_o
);



    logic                  SEL;


    assign data_r_valid_o = data_r_valid1_i | data_r_valid0_i;


    assign SEL = data_r_valid1_i;



    always_comb
    begin : FanOut_MUX2
        case(SEL) 
          1'b0: begin data_r_rdata_o  = data_r_rdata0_i; data_r_opc_o = data_r_opc0_i; end
          1'b1: begin data_r_rdata_o  = data_r_rdata1_i; data_r_opc_o = data_r_opc1_i; end
        endcase
    end
endmodule