data/full_repos/permissive/52836497/sha1.v
1: b"%Error: data/full_repos/permissive/52836497/sha1.v:13: syntax error, unexpected context, expecting IDENTIFIER or '=' or do or final\nreg [159:0] context;\n            ^~~~~~~\n%Error: data/full_repos/permissive/52836497/sha1.v:25: syntax error, unexpected context, expecting TYPE-IDENTIFIER\nwire [31:0] a = context[159:128];\n                ^~~~~~~\n%Error: data/full_repos/permissive/52836497/sha1.v:26: syntax error, unexpected context, expecting TYPE-IDENTIFIER\nwire [31:0] b = context[127:96];\n                ^~~~~~~\n%Error: data/full_repos/permissive/52836497/sha1.v:27: syntax error, unexpected context, expecting TYPE-IDENTIFIER\nwire [31:0] c = context[95:64];\n                ^~~~~~~\n%Error: data/full_repos/permissive/52836497/sha1.v:28: syntax error, unexpected context, expecting TYPE-IDENTIFIER\nwire [31:0] d = context[63:32];\n                ^~~~~~~\n%Error: data/full_repos/permissive/52836497/sha1.v:29: syntax error, unexpected context, expecting TYPE-IDENTIFIER\nwire [31:0] e = context[31:0];\n                ^~~~~~~\n%Error: data/full_repos/permissive/52836497/sha1.v:48: syntax error, unexpected context, expecting TYPE-IDENTIFIER\n    .context_in(context),\n                ^~~~~~~\n%Error: data/full_repos/permissive/52836497/sha1.v:60: syntax error, unexpected context\n        context <= context_in;\n        ^~~~~~~\n%Error: data/full_repos/permissive/52836497/sha1.v:64: syntax error, unexpected context\n        context <= context_next;\n        ^~~~~~~\n%Error: Exiting due to 9 error(s)\n"
module w_machine (
    input wire clk,
    input wire load,
    input wire [511:0] block,
    output wire [31:0] w);

reg [511:0] state;
assign w = state[511:480];
wire [31:0] w_im3 = state[95:64];
wire [31:0] w_im8 = state[255:224];
wire [31:0] w_im14 = state[447:416];
wire [31:0] w_im16 = state[511:480];
wire [31:0] w_temp = w_im3 ^ w_im8 ^ w_im14 ^ w_im16;
wire [31:0] w_next = {w_temp[30:0], w_temp[31]};

always @(posedge clk)
begin
    if (load)
        state <= block;
    else begin
        state <= {state[479:0], w_next};
    end
end

endmodule
module w_machine (
    input wire clk,
    input wire load,
    input wire [511:0] block,
    output wire [31:0] w);


reg [511:0] state;
assign w = state[511:480];
wire [31:0] w_im3 = state[95:64];
wire [31:0] w_im8 = state[255:224];
wire [31:0] w_im14 = state[447:416];
wire [31:0] w_im16 = state[511:480];
wire [31:0] w_temp = w_im3 ^ w_im8 ^ w_im14 ^ w_im16;
wire [31:0] w_next = {w_temp[30:0], w_temp[31]};

always @(posedge clk)
begin
    if (load)
        state <= block;
    else begin
        state <= {state[479:0], w_next};
    end
end

endmodule