data/full_repos/permissive/472385934/datapath.v
1: b"%Error: data/full_repos/permissive/472385934/datapath.v:58: Cannot find file containing module: 'inst_memory'\ninst_memory fetch_mem(clk,pcF,instrF,ext_instr,ext_instr_addr,ext_instr_en,start); \n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/472385934,data/full_repos/permissive/472385934/inst_memory\n             data/full_repos/permissive/472385934,data/full_repos/permissive/472385934/inst_memory.v\n             data/full_repos/permissive/472385934,data/full_repos/permissive/472385934/inst_memory.sv\n             inst_memory\n             inst_memory.v\n             inst_memory.sv\n             obj_dir/inst_memory\n             obj_dir/inst_memory.v\n             obj_dir/inst_memory.sv\n%Error: data/full_repos/permissive/472385934/datapath.v:86: Cannot find file containing module: 'reg_file'\nreg_file reg_file(resultW,writeregW,clk,regwriteW,rst_n,a1,a2,rd1,rd2);\n^~~~~~~~\n%Error: data/full_repos/permissive/472385934/datapath.v:116: Cannot find file containing module: 'alu'\nalu alu(srcaE,srcbE,alucontrolE,aluoutE); \n^~~\n%Error: data/full_repos/permissive/472385934/datapath.v:117: Cannot find file containing module: 'multipler'\nmultipler multipler(srcaE,srcbE,clk,alucontrolE[3],multoutE); \n^~~~~~~~~\n%Error: data/full_repos/permissive/472385934/datapath.v:135: Cannot find file containing module: 'data_memory'\ndata_memory data_memory(realoutM,writedataM,clk,memwriteM,readdataM,ext_data,ext_data_addr,ext_data_en);\n^~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module datapath(
input clk,
input rst_n,
input regwrite,
input memtoreg,
input memwrite,
input [1:0] branch,
input [3:0] alucontrol,
input alusrc,
input regdst,
input jump,
input mult_sel,

input [1:0]forwardAE,forwardBE,
input forwardAD,forwardBD,
input flushD,
input stallF,stallD,flushE,

output [4:0] rsE,rtE,
output [4:0] rtD,
output [4:0] rsD,
output [4:0] writeregM,writeregW,
output regwriteM,regwriteW,
output memtoregE,
output [4:0] writeregE,
output pcsrcD,
output memtoregM,regwriteE,

output [5:0]op,
output [5:0] funct,
output [31:0] resultW,

input [31:0] ext_data,ext_data_addr,
input ext_data_en,
input [31:0] ext_instr,ext_instr_addr,
input ext_instr_en,
input start);


wire [31:0]realoutM,writedataM;

wire [31:0] pcF;
wire [31:0] instrD;
wire [31:0] pcplus4D;
wire [31:0] pc_n;
wire [31:0] pcbranchD;
wire [31:0] instrF,pcplus4F;
wire [31:0] jumpadd;
assign pcplus4F = pcF+4;

wire [31:0] pc_n_temp;

mux2 #(32) PCBranchMux(pcplus4F,pcbranchD,pcsrcD,pc_n_temp);
mux2 #(32) PCJumpMux(pc_n_temp,jumpadd,jump,pc_n);


Fetch Fetchff(clk,rst_n,stallF,pc_n,pcF);
inst_memory fetch_mem(clk,pcF,instrF,ext_instr,ext_instr_addr,ext_instr_en,start);


Decode Decodeff(clk,rst_n,stallD,flushD,instrF,pcplus4F,instrD,pcplus4D);

assign op = instrD[31:26];
assign funct = instrD[5:0];
wire regwriteD,memtoregD,memwriteD;
wire [1:0] branchD;
wire [4:0] a1,a2;
wire [3:0] alucontrolD;
wire alusrcD,regdstD,jumpD,mult_selD;
assign {regwriteD,memtoregD,memwriteD,branchD,alucontrolD,alusrcD,regdstD,jumpD,mult_selD}=
        {regwrite,memtoreg,memwrite,branch,alucontrol,alusrc,regdst,jump,mult_sel};
assign a1 = instrD[25:21];
assign a2 = instrD[20:16];
wire [31:0] rd1D,rd2D,signimmD;
wire [4:0] rdD;
wire [31:0] signimmE,rd1E,rd2E;
wire [4:0] rdE;
wire memwriteE,alusrcE,regdstE,mult_selE;
wire [3:0] alucontrolE;
assign rtD = instrD[20:16];
assign rdD = instrD[15:11];
assign rsD = instrD[25:21];

wire [31:0]rd1,rd2;

reg_file reg_file(resultW,writeregW,clk,regwriteW,rst_n,a1,a2,rd1,rd2);

mux2 #(32) CtrHazardMux1(rd1,realoutM,forwardAD,rd1D);
mux2 #(32) CtrHazardMux2(rd2,realoutM,forwardBD,rd2D);

wire pcsrcD_temp;
mux2 #(1) BranchMux1((rd1D == rd2D),(rd1D != rd2D),branchD[0],pcsrcD_temp);
mux2 #(1) BranchMux2(1'b0,pcsrcD_temp,branchD[1],pcsrcD);

assign jumpadd = {pcF[31:28],instrD[25:0],2'b0};
assign signimmD = {{16{instrD[15]}},instrD[15:0]}<<2;
assign pcbranchD = pcplus4D+signimmD;


wire [31:0] srcaE,srcbE;
wire [31:0] aluoutE, multoutE;
wire [31:0] writedataE;
wire [31:0] rd1E_temp,rd2E_temp;

Execute Executeff(clk,rst_n,flushE,signimmD,rd1D,rd2D,rtD,rdD,rsD,regwriteD,memtoregD,memwriteD,alusrcD,regdstD,mult_selD,
                    alucontrolD,signimmE,rd1E_temp,rd2E_temp,rtE,rdE,rsE,alucontrolE,
                    regwriteE,memtoregE,memwriteE,alusrcE,regdstE,mult_selE);

mux3 #(32) RAWHazardMux1(rd1E_temp,resultW,realoutM,forwardAE,rd1E);
mux3 #(32) RAWHazardMux2(rd2E_temp,resultW,realoutM,forwardBE,rd2E);

assign srcaE = rd1E;
mux2 #(32) SrcBMux(rd2E,signimmE,alusrcE,srcbE);


alu alu(srcaE,srcbE,alucontrolE,aluoutE); 
multipler multipler(srcaE,srcbE,clk,alucontrolE[3],multoutE);

wire [31:0] realoutE;
wire memwriteM;

mux2 #(32) ALU_MULT_Mux(aluoutE,multoutE,mult_sel,realoutE);

assign writedataE = rd2E;
mux2 #(5) regMux(rtE,rdE,regdstE,writeregE);




Memory Memoryff(clk,rst_n,regwriteE,memtoregE,memwriteE,realoutE,writedataE,writeregE,
                regwriteM,memtoregM,memwriteM,realoutM,writedataM,writeregM);

wire [31:0]readdataM;

data_memory data_memory(realoutM,writedataM,clk,memwriteM,readdataM,ext_data,ext_data_addr,ext_data_en);

wire memtoregW;
wire [31:0]readdataW,realoutW;

WriteBack WriteBackff(clk,rst_n,regwriteM,memtoregM,realoutM,writeregM,readdataM,
                        regwriteW,memtoregW,realoutW,writeregW,readdataW);
mux2 #(32) ResultMux(realoutW,readdataW,memtoregW,resultW);

endmodule
module datapath(
input clk,
input rst_n,
input regwrite,
input memtoreg,
input memwrite,
input [1:0] branch,
input [3:0] alucontrol,
input alusrc,
input regdst,
input jump,
input mult_sel,

input [1:0]forwardAE,forwardBE,
input forwardAD,forwardBD,
input flushD,
input stallF,stallD,flushE,

output [4:0] rsE,rtE,
output [4:0] rtD,
output [4:0] rsD,
output [4:0] writeregM,writeregW,
output regwriteM,regwriteW,
output memtoregE,
output [4:0] writeregE,
output pcsrcD,
output memtoregM,regwriteE,

output [5:0]op,
output [5:0] funct,
output [31:0] resultW,

input [31:0] ext_data,ext_data_addr,
input ext_data_en,
input [31:0] ext_instr,ext_instr_addr,
input ext_instr_en,
input start);



wire [31:0]realoutM,writedataM;

wire [31:0] pcF;
wire [31:0] instrD;
wire [31:0] pcplus4D;
wire [31:0] pc_n;
wire [31:0] pcbranchD;
wire [31:0] instrF,pcplus4F;
wire [31:0] jumpadd;
assign pcplus4F = pcF+4;

wire [31:0] pc_n_temp;

mux2 #(32) PCBranchMux(pcplus4F,pcbranchD,pcsrcD,pc_n_temp);
mux2 #(32) PCJumpMux(pc_n_temp,jumpadd,jump,pc_n);


Fetch Fetchff(clk,rst_n,stallF,pc_n,pcF);
inst_memory fetch_mem(clk,pcF,instrF,ext_instr,ext_instr_addr,ext_instr_en,start);


Decode Decodeff(clk,rst_n,stallD,flushD,instrF,pcplus4F,instrD,pcplus4D);

assign op = instrD[31:26];
assign funct = instrD[5:0];
wire regwriteD,memtoregD,memwriteD;
wire [1:0] branchD;
wire [4:0] a1,a2;
wire [3:0] alucontrolD;
wire alusrcD,regdstD,jumpD,mult_selD;
assign {regwriteD,memtoregD,memwriteD,branchD,alucontrolD,alusrcD,regdstD,jumpD,mult_selD}=
        {regwrite,memtoreg,memwrite,branch,alucontrol,alusrc,regdst,jump,mult_sel};
assign a1 = instrD[25:21];
assign a2 = instrD[20:16];
wire [31:0] rd1D,rd2D,signimmD;
wire [4:0] rdD;
wire [31:0] signimmE,rd1E,rd2E;
wire [4:0] rdE;
wire memwriteE,alusrcE,regdstE,mult_selE;
wire [3:0] alucontrolE;
assign rtD = instrD[20:16];
assign rdD = instrD[15:11];
assign rsD = instrD[25:21];

wire [31:0]rd1,rd2;

reg_file reg_file(resultW,writeregW,clk,regwriteW,rst_n,a1,a2,rd1,rd2);

mux2 #(32) CtrHazardMux1(rd1,realoutM,forwardAD,rd1D);
mux2 #(32) CtrHazardMux2(rd2,realoutM,forwardBD,rd2D);

wire pcsrcD_temp;
mux2 #(1) BranchMux1((rd1D == rd2D),(rd1D != rd2D),branchD[0],pcsrcD_temp);
mux2 #(1) BranchMux2(1'b0,pcsrcD_temp,branchD[1],pcsrcD);

assign jumpadd = {pcF[31:28],instrD[25:0],2'b0};
assign signimmD = {{16{instrD[15]}},instrD[15:0]}<<2;
assign pcbranchD = pcplus4D+signimmD;


wire [31:0] srcaE,srcbE;
wire [31:0] aluoutE, multoutE;
wire [31:0] writedataE;
wire [31:0] rd1E_temp,rd2E_temp;

Execute Executeff(clk,rst_n,flushE,signimmD,rd1D,rd2D,rtD,rdD,rsD,regwriteD,memtoregD,memwriteD,alusrcD,regdstD,mult_selD,
                    alucontrolD,signimmE,rd1E_temp,rd2E_temp,rtE,rdE,rsE,alucontrolE,
                    regwriteE,memtoregE,memwriteE,alusrcE,regdstE,mult_selE);

mux3 #(32) RAWHazardMux1(rd1E_temp,resultW,realoutM,forwardAE,rd1E);
mux3 #(32) RAWHazardMux2(rd2E_temp,resultW,realoutM,forwardBE,rd2E);

assign srcaE = rd1E;
mux2 #(32) SrcBMux(rd2E,signimmE,alusrcE,srcbE);


alu alu(srcaE,srcbE,alucontrolE,aluoutE); 
multipler multipler(srcaE,srcbE,clk,alucontrolE[3],multoutE);

wire [31:0] realoutE;
wire memwriteM;

mux2 #(32) ALU_MULT_Mux(aluoutE,multoutE,mult_sel,realoutE);

assign writedataE = rd2E;
mux2 #(5) regMux(rtE,rdE,regdstE,writeregE);




Memory Memoryff(clk,rst_n,regwriteE,memtoregE,memwriteE,realoutE,writedataE,writeregE,
                regwriteM,memtoregM,memwriteM,realoutM,writedataM,writeregM);

wire [31:0]readdataM;

data_memory data_memory(realoutM,writedataM,clk,memwriteM,readdataM,ext_data,ext_data_addr,ext_data_en);

wire memtoregW;
wire [31:0]readdataW,realoutW;

WriteBack WriteBackff(clk,rst_n,regwriteM,memtoregM,realoutM,writeregM,readdataM,
                        regwriteW,memtoregW,realoutW,writeregW,readdataW);
mux2 #(32) ResultMux(realoutW,readdataW,memtoregW,resultW);

endmodule