data/full_repos/permissive/458313092/Debouncer/Debouncer_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/458313092/Debouncer/Debouncer_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n   #period CLK = ~CLK;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458313092/Debouncer/Debouncer_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n   #5 CLR = 1\'b0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/Debouncer/Debouncer_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #(29*period);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/Debouncer/Debouncer_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #4.5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/Debouncer/Debouncer_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n #(2*period);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/Debouncer/Debouncer_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #(62*period); \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/Debouncer/Debouncer_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #1 PUSH = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/Debouncer/Debouncer_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n    #17 PUSH = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/Debouncer/Debouncer_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #1 PUSH = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/Debouncer/Debouncer_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #1 PUSH = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/Debouncer/Debouncer_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #1 PUSH = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/Debouncer/Debouncer_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n #(100*period);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/Debouncer/Debouncer_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n #(40*period)  PUSH = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/458313092/Debouncer/Debouncer_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #(200*period);\n    ^\n%Error: data/full_repos/permissive/458313092/Debouncer/Debouncer_tb.v:7: Cannot find file containing module: \'Debouncer\'\nDebouncer UUT (.CLK(CLK),.CEI(CEI),.PUSH(PUSH),.CLR(CLR),.PE(PE));\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458313092/Debouncer,data/full_repos/permissive/458313092/Debouncer\n             data/full_repos/permissive/458313092/Debouncer,data/full_repos/permissive/458313092/Debouncer.v\n             data/full_repos/permissive/458313092/Debouncer,data/full_repos/permissive/458313092/Debouncer.sv\n             Debouncer\n             Debouncer.v\n             Debouncer.sv\n             obj_dir/Debouncer\n             obj_dir/Debouncer.v\n             obj_dir/Debouncer.sv\n%Error: Exiting due to 1 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Debouncer_tb;

reg CLK,CEI,PUSH,CLR;
wire PE;
localparam period = 4;
Debouncer UUT (.CLK(CLK),.CEI(CEI),.PUSH(PUSH),.CLR(CLR),.PE(PE));


initial begin
    CLK = 1'b1;
    CEI = 1'b0;
    PUSH = 1'b0;
    CLR = 1'b1;

end


always begin
   #period CLK = ~CLK;
end

always begin
   #5 CLR = 1'b0;
end

always  begin
 #(29*period);
 #4.5;
 CEI = 1'b1;
 #(2*period);
 CEI = 1'b0;   
end


always begin
    #(62*period);
    #1 PUSH = 1'b1;
    #17 PUSH = 1'b0;
    #1 PUSH = 1'b1;
    #1 PUSH = 1'b0;
    #1 PUSH = 1'b1;
	#(100*period);
	PUSH = 1'b0;
	#(40*period)  PUSH = 1'b1;
	

    #(200*period);
    $finish;

end

endmodule
module Debouncer_tb;


reg CLK,CEI,PUSH,CLR;
wire PE;
localparam period = 4;
Debouncer UUT (.CLK(CLK),.CEI(CEI),.PUSH(PUSH),.CLR(CLR),.PE(PE));


initial begin
    CLK = 1'b1;
    CEI = 1'b0;
    PUSH = 1'b0;
    CLR = 1'b1;

end


always begin
   #period CLK = ~CLK;
end

always begin
   #5 CLR = 1'b0;
end

always  begin
 #(29*period);
 #4.5;
 CEI = 1'b1;
 #(2*period);
 CEI = 1'b0;   
end


always begin
    #(62*period);
    #1 PUSH = 1'b1;
    #17 PUSH = 1'b0;
    #1 PUSH = 1'b1;
    #1 PUSH = 1'b0;
    #1 PUSH = 1'b1;
	#(100*period);
	PUSH = 1'b0;
	#(40*period)  PUSH = 1'b1;
	

    #(200*period);
    $finish;

end

endmodule