data/full_repos/permissive/501457949/verilog/rtl/user_project_wrapper.v
1: b"%Error: data/full_repos/permissive/501457949/verilog/rtl/user_project_wrapper.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501457949/verilog/rtl/user_project_wrapper.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501457949/verilog/rtl/user_project_wrapper.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501457949/verilog/rtl/user_project_wrapper.v:72: Define or directive not defined: '`MPRJ_IO_PADS'\n    inout [`MPRJ_IO_PADS-10:0] analog_io,\n           ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module user_project_wrapper #(
    parameter BITS = 32
) (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,





    inout [`MPRJ_IO_PADS-10:0] analog_io,


    input   user_clock2,


    output [2:0] user_irq
);





pulpino_top mprj (

  .clk(wb_clk_i),
  .rst_n(wb_rst_i),

  .clk_sel_i(io_in[0]),
  .clk_standalone_i(io_in[1]),
  .testmode_i(io_in[2]),
  .fetch_enable_i(io_in[3]),
  .scan_enable_i(io_in[4]),


  .spi_clk_i(io_in[5]),
  .spi_cs_i(io_in[6]),
  .spi_mode_o(io_out[1:0]),
  .spi_sdo0_o(io_out[2]),
  .spi_sdo1_o(io_out[3]),
  .spi_sdo2_o(io_out[4]),
  .spi_sdo3_o(io_out[5]),
  .spi_sdi0_i(io_in[7]),
  .spi_sdi1_i(io_in[8]),
  .spi_sdi2_i(io_in[9]),
  .spi_sdi3_i(io_in[10]),


  .spi_master_clk_o(io_out[6]),
  .spi_master_csn0_o(io_out[7]),
  .spi_master_csn1_o(io_out[8]),
  .spi_master_csn2_o(io_out[9]),
  .spi_master_csn3_o(io_out[10]),
  .spi_master_mode_o(io_out[12:11]),
  .spi_master_sdo0_o(io_out[13]),
  .spi_master_sdo1_o(io_out[14]),
  .spi_master_sdo2_o(io_out[15]),
  .spi_master_sdo3_o(io_out[16]),
  .spi_master_sdi0_i(io_in[11]),
  .spi_master_sdi1_i(io_in[12]),
  .spi_master_sdi2_i(io_in[13]),
  .spi_master_sdi3_i(io_in[14]),

  .scl_pad_i(io_in[15]),
  .scl_pad_o(io_out[17]),
  .scl_padoen_o(io_out[18]),
  .sda_pad_i(io_in[16]),
  .sda_pad_o(io_out[19]),
  .sda_padoen_o(io_out[20]),

  .uart_tx(io_out[21]),
  .uart_rx(io_in[17]),
  .uart_rts(io_out[22]),
  .uart_dtr(io_out[23]),
  .uart_cts(io_in[18]),
  .uart_dsr(io_in[19]),

  .gpio_in(io_in[27:20]),
  .gpio_out(io_out[31:24]),




  .tck_i(user_clock2),
  .trstn_i(io_in[28]),
  .tms_i(io_in[29]),
  .tdi_i(io_in[30]),
  .tdo_o(io_out[32]),






  .io_oeb(io_oeb[32:0])
);

endmodule
module user_project_wrapper #(
    parameter BITS = 32
) (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,





    inout [`MPRJ_IO_PADS-10:0] analog_io,


    input   user_clock2,


    output [2:0] user_irq
);






pulpino_top mprj (

  .clk(wb_clk_i),
  .rst_n(wb_rst_i),

  .clk_sel_i(io_in[0]),
  .clk_standalone_i(io_in[1]),
  .testmode_i(io_in[2]),
  .fetch_enable_i(io_in[3]),
  .scan_enable_i(io_in[4]),


  .spi_clk_i(io_in[5]),
  .spi_cs_i(io_in[6]),
  .spi_mode_o(io_out[1:0]),
  .spi_sdo0_o(io_out[2]),
  .spi_sdo1_o(io_out[3]),
  .spi_sdo2_o(io_out[4]),
  .spi_sdo3_o(io_out[5]),
  .spi_sdi0_i(io_in[7]),
  .spi_sdi1_i(io_in[8]),
  .spi_sdi2_i(io_in[9]),
  .spi_sdi3_i(io_in[10]),


  .spi_master_clk_o(io_out[6]),
  .spi_master_csn0_o(io_out[7]),
  .spi_master_csn1_o(io_out[8]),
  .spi_master_csn2_o(io_out[9]),
  .spi_master_csn3_o(io_out[10]),
  .spi_master_mode_o(io_out[12:11]),
  .spi_master_sdo0_o(io_out[13]),
  .spi_master_sdo1_o(io_out[14]),
  .spi_master_sdo2_o(io_out[15]),
  .spi_master_sdo3_o(io_out[16]),
  .spi_master_sdi0_i(io_in[11]),
  .spi_master_sdi1_i(io_in[12]),
  .spi_master_sdi2_i(io_in[13]),
  .spi_master_sdi3_i(io_in[14]),

  .scl_pad_i(io_in[15]),
  .scl_pad_o(io_out[17]),
  .scl_padoen_o(io_out[18]),
  .sda_pad_i(io_in[16]),
  .sda_pad_o(io_out[19]),
  .sda_padoen_o(io_out[20]),

  .uart_tx(io_out[21]),
  .uart_rx(io_in[17]),
  .uart_rts(io_out[22]),
  .uart_dtr(io_out[23]),
  .uart_cts(io_in[18]),
  .uart_dsr(io_in[19]),

  .gpio_in(io_in[27:20]),
  .gpio_out(io_out[31:24]),




  .tck_i(user_clock2),
  .trstn_i(io_in[28]),
  .tms_i(io_in[29]),
  .tdi_i(io_in[30]),
  .tdo_o(io_out[32]),






  .io_oeb(io_oeb[32:0])
);

endmodule