data/full_repos/permissive/446997925/hw3/and.v
data/verilator_xmls/e2b82ace-9d56-43df-a68f-94f4fe8a4f8c.xml
module and_4(out, a, b);
input [3:0] a, b;
output [3:0] out;

and_2 f(out[1:0], a[1:0], b[1:0]),
          s(out[3:2], a[3:2], b[3:2]);
endmodule
module and_4(out, a, b);

input [3:0] a, b;
output [3:0] out;

and_2 f(out[1:0], a[1:0], b[1:0]),
          s(out[3:2], a[3:2], b[3:2]);
endmodule