data/full_repos/permissive/418331750/priRV32_SoC.v
1: b'%Error: data/full_repos/permissive/418331750/priRV32_SoC.v:1: Cannot find include file: ./core/priRV32_top.v\n`include "./core/priRV32_top.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418331750,data/full_repos/permissive/418331750/./core/priRV32_top.v\n             data/full_repos/permissive/418331750,data/full_repos/permissive/418331750/./core/priRV32_top.v.v\n             data/full_repos/permissive/418331750,data/full_repos/permissive/418331750/./core/priRV32_top.v.sv\n             ./core/priRV32_top.v\n             ./core/priRV32_top.v.v\n             ./core/priRV32_top.v.sv\n             obj_dir/./core/priRV32_top.v\n             obj_dir/./core/priRV32_top.v.v\n             obj_dir/./core/priRV32_top.v.sv\n%Error: data/full_repos/permissive/418331750/priRV32_SoC.v:2: Cannot find include file: ./periph/uart/uart_top.v\n`include "./periph/uart/uart_top.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418331750/priRV32_SoC.v:3: Cannot find include file: ./fpga/itcm_ram.v\n`include "./fpga/itcm_ram.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418331750/priRV32_SoC.v:4: Cannot find include file: ./periph/flash/spi_flash\n`include "./periph/flash/spi_flash" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module PowerOn_RST#(
	parameter CNT = 20'd500_000
)(
    input clk_in,
    input rst_in,
    output rst_n
);
    wire buf_rst_n;
    reg [26:0] cnt = 27'd0;
    assign buf_rst_n = (cnt == CNT - 1'b1) ? 1'b1 : 1'b0;
    assign rst_n = buf_rst_n || rst_in;
    always @ (posedge clk_in)begin
        if (cnt < CNT - 1'b1)
            cnt <= cnt + 1'b1;
        else
            cnt <= cnt;
    end
endmodule
module PowerOn_RST#(
	parameter CNT = 20'd500_000
)(
    input clk_in,
    input rst_in,
    output rst_n
);

    wire buf_rst_n;
    reg [26:0] cnt = 27'd0;
    assign buf_rst_n = (cnt == CNT - 1'b1) ? 1'b1 : 1'b0;
    assign rst_n = buf_rst_n || rst_in;
    always @ (posedge clk_in)begin
        if (cnt < CNT - 1'b1)
            cnt <= cnt + 1'b1;
        else
            cnt <= cnt;
    end
endmodule