data/full_repos/permissive/492363527/ShiftRegister_version2.v
data/verilator_xmls/9f064605-59a2-4377-abac-5d8763d9144e.xml
module ShiftRegister(clk,x);
	input clk;
	output reg [3:0]x;
	
	initial
  begin
		x = 4'b0001;
  end
	
	always@(posedge clk) 
  begin
    x[3:0] <= {x[2:0],x[3]};
		
	
	end
	
endmodule
module ShiftRegister(clk,x);

	input clk;
	output reg [3:0]x;
	
	initial
  begin
		x = 4'b0001;
  end
	
	always@(posedge clk) 
  begin
    x[3:0] <= {x[2:0],x[3]};
		
	
	end
	
endmodule