data/full_repos/permissive/494696040/Control.v
data/verilator_xmls/1c663f8c-1aaf-42e1-a69c-61e03c812813.xml
module Control(
    input wire [5:0] opcode,
    output reg RegDst,
    output reg Jump,
    output reg Branch,
    output reg MemRead,
    output reg MemtoReg,
    output reg [1:0] ALUOp,
    output reg MemWrite,
    output reg ALUSrc,
    output reg RegWrite
    );
    
    initial begin
        RegDst <= 1'b0;
        Jump <= 1'b0;
        ALUSrc <= 1'b0;
        MemtoReg <= 1'b0;
        RegWrite  <= 1'b0;
        MemRead <= 1'b0;
        MemWrite <= 1'b0;
        Branch <= 1'b0;
        ALUOp <= 2'b00;
    end
    
    

        always @(opcode) begin
        case(opcode)
            0: begin
                RegDst <= 1'b1;
                Jump <= 1'b0;
                ALUSrc <= 1'b0;
                MemtoReg <= 1'b0;
                RegWrite  <= 1'b1;
                MemRead <= 1'b0;
                MemWrite <= 1'b0;
                Branch <= 1'b0;
                ALUOp <= 2'b10;
            end
            2: begin
                RegDst <= 1'b0;
                Jump <= 1'b1;
                ALUSrc <= 1'b0;
                MemtoReg <= 1'b0;
                RegWrite  <= 1'b0;
                MemRead <= 1'b0;
                MemWrite <= 1'b0;
                Branch <= 1'b0;
                ALUOp <= 2'b00;
            end
            35: begin
                RegDst <= 1'b0;
                Jump <= 1'b0;
                ALUSrc <= 1'b1;
                MemtoReg <= 1'b1;
                RegWrite  <= 1'b1;
                MemRead <= 1'b1;
                MemWrite <= 1'b0;
                Branch <= 1'b0;
                ALUOp <= 2'b00;
            end
            43: begin
                ALUSrc <= 1'b1;
                Jump <= 1'b0;
                RegWrite  <= 1'b0;
                MemRead <= 1'b0;
                MemWrite <= 1'b1;
                Branch <= 1'b0;
                ALUOp <= 2'b00;
            end
            4: begin
                ALUSrc <= 1'b0;
                Jump <= 1'b0;
                RegWrite  <= 1'b0;
                MemRead <= 1'b0;
                MemWrite <= 1'b0;
                Branch <= 1'b1;
                ALUOp <= 2'b01;
            end
        endcase
    end
    
    
endmodule
module Control(
    input wire [5:0] opcode,
    output reg RegDst,
    output reg Jump,
    output reg Branch,
    output reg MemRead,
    output reg MemtoReg,
    output reg [1:0] ALUOp,
    output reg MemWrite,
    output reg ALUSrc,
    output reg RegWrite
    );

    
    initial begin
        RegDst <= 1'b0;
        Jump <= 1'b0;
        ALUSrc <= 1'b0;
        MemtoReg <= 1'b0;
        RegWrite  <= 1'b0;
        MemRead <= 1'b0;
        MemWrite <= 1'b0;
        Branch <= 1'b0;
        ALUOp <= 2'b00;
    end
    
    

        always @(opcode) begin
        case(opcode)
            0: begin
                RegDst <= 1'b1;
                Jump <= 1'b0;
                ALUSrc <= 1'b0;
                MemtoReg <= 1'b0;
                RegWrite  <= 1'b1;
                MemRead <= 1'b0;
                MemWrite <= 1'b0;
                Branch <= 1'b0;
                ALUOp <= 2'b10;
            end
            2: begin
                RegDst <= 1'b0;
                Jump <= 1'b1;
                ALUSrc <= 1'b0;
                MemtoReg <= 1'b0;
                RegWrite  <= 1'b0;
                MemRead <= 1'b0;
                MemWrite <= 1'b0;
                Branch <= 1'b0;
                ALUOp <= 2'b00;
            end
            35: begin
                RegDst <= 1'b0;
                Jump <= 1'b0;
                ALUSrc <= 1'b1;
                MemtoReg <= 1'b1;
                RegWrite  <= 1'b1;
                MemRead <= 1'b1;
                MemWrite <= 1'b0;
                Branch <= 1'b0;
                ALUOp <= 2'b00;
            end
            43: begin
                ALUSrc <= 1'b1;
                Jump <= 1'b0;
                RegWrite  <= 1'b0;
                MemRead <= 1'b0;
                MemWrite <= 1'b1;
                Branch <= 1'b0;
                ALUOp <= 2'b00;
            end
            4: begin
                ALUSrc <= 1'b0;
                Jump <= 1'b0;
                RegWrite  <= 1'b0;
                MemRead <= 1'b0;
                MemWrite <= 1'b0;
                Branch <= 1'b1;
                ALUOp <= 2'b01;
            end
        endcase
    end
    
    
endmodule