data/full_repos/permissive/466186773/verilog/rtl/counter_multiply_reg.v
1: b"%Error: data/full_repos/permissive/466186773/verilog/rtl/counter_multiply_reg.v:53: Duplicate declaration of signal: 'ready'\n                                                                                  : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n    reg ready;\n        ^~~~~\n        data/full_repos/permissive/466186773/verilog/rtl/counter_multiply_reg.v:49: ... Location of original declaration\n    output ready,\n           ^~~~~\n%Error: data/full_repos/permissive/466186773/verilog/rtl/counter_multiply_reg.v:54: Duplicate declaration of signal: 'count'\n    reg [BITS-1:0] count;\n                   ^~~~~\n        data/full_repos/permissive/466186773/verilog/rtl/counter_multiply_reg.v:51: ... Location of original declaration\n    output [BITS-1:0] count\n                      ^~~~~\n%Error: data/full_repos/permissive/466186773/verilog/rtl/counter_multiply_reg.v:55: Duplicate declaration of signal: 'rdata'\n    reg [BITS-1:0] rdata;\n                   ^~~~~\n        data/full_repos/permissive/466186773/verilog/rtl/counter_multiply_reg.v:50: ... Location of original declaration\n    output [BITS-1:0] rdata,\n                      ^~~~~\n%Error: Exiting due to 3 error(s)\n"
module counter_multiply_reg #(
    parameter BITS = 32
)(
    input clk,
    input reset,
    input valid,
    input [3:0] wstrb,
    input [BITS-1:0] wdata,
    input [BITS-1:0] la_write,
    input [BITS-1:0] la_input,
    output ready,
    output [BITS-1:0] rdata,
    output [BITS-1:0] count
);
    reg ready;
    reg [BITS-1:0] count;
    reg [BITS-1:0] rdata;
    
    reg [4:0]  la_write_1d;
    reg [4:0]  la_write_2d;
    reg [4:0]  la_write_3d;
    reg [4:0]  la_write_4d;
    
    reg [4:0]  la_input_1d;
    reg [4:0]  la_input_2d;
    reg [4:0]  la_input_3d;
    reg [4:0]  la_input_4d;
    
    wire [7:0] multi_out;
    
    reg [7:0] multi_out_1d;
    reg [7:0] multi_out_2d;
    reg [7:0] multi_out_3d;
    reg [7:0] multi_out_4d;
    
    
    always @(posedge clk) begin
        if (reset) begin
            la_write_1d <= 0;
            la_write_2d <= 0;
            la_write_3d <= 0;
            la_write_4d <= 0;
            
            la_input_1d <= 0;
            la_input_2d <= 0;
            la_input_3d <= 0;
            la_input_4d <= 0;
            
            multi_out_1d <= 0;
            multi_out_2d <= 0;
            multi_out_3d <= 0;
            multi_out_4d <= 0;
        end 
        else begin
        	la_write_1d <= la_write[4:0];
        	la_write_2d <= la_write_1d;
        	la_write_3d <= la_write_2d;
        	la_write_4d <= la_write_3d;
        	
        	la_input_1d <= la_input[4:0];
        	la_input_2d <= la_input_1d;
        	la_input_3d <= la_input_2d;
        	la_input_4d <= la_input_3d;
        	
        	multi_out_1d <= multi_out;
        	multi_out_2d <= multi_out_1d;
        	multi_out_3d <= multi_out_2d;
        	multi_out_4d <= multi_out_3d;
        end
    end
    
    assign multi_out = la_write_4d * la_input_4d;

    always @(posedge clk) begin
        if (reset) begin
            count <= 0;
            ready <= 0;
        end else begin
            ready <= 1'b0;
            if (~|la_write) begin
                count <= count + 1;
            end
            if (valid && !ready) begin
                ready <= 1'b1;
                rdata <= count;
                if (wstrb[0]) count[7:0]   <= wdata[7:0];
                if (wstrb[1]) count[15:8]  <= wdata[15:8];
                if (wstrb[2]) count[23:16] <= wdata[23:16];
                if (wstrb[3]) count[31:24] <= wdata[31:24];
            end else if (|la_write) begin
                count[7:0] <= multi_out_4d;
            end
        end
    end

endmodule
module counter_multiply_reg #(
    parameter BITS = 32
)(
    input clk,
    input reset,
    input valid,
    input [3:0] wstrb,
    input [BITS-1:0] wdata,
    input [BITS-1:0] la_write,
    input [BITS-1:0] la_input,
    output ready,
    output [BITS-1:0] rdata,
    output [BITS-1:0] count
);

    reg ready;
    reg [BITS-1:0] count;
    reg [BITS-1:0] rdata;
    
    reg [4:0]  la_write_1d;
    reg [4:0]  la_write_2d;
    reg [4:0]  la_write_3d;
    reg [4:0]  la_write_4d;
    
    reg [4:0]  la_input_1d;
    reg [4:0]  la_input_2d;
    reg [4:0]  la_input_3d;
    reg [4:0]  la_input_4d;
    
    wire [7:0] multi_out;
    
    reg [7:0] multi_out_1d;
    reg [7:0] multi_out_2d;
    reg [7:0] multi_out_3d;
    reg [7:0] multi_out_4d;
    
    
    always @(posedge clk) begin
        if (reset) begin
            la_write_1d <= 0;
            la_write_2d <= 0;
            la_write_3d <= 0;
            la_write_4d <= 0;
            
            la_input_1d <= 0;
            la_input_2d <= 0;
            la_input_3d <= 0;
            la_input_4d <= 0;
            
            multi_out_1d <= 0;
            multi_out_2d <= 0;
            multi_out_3d <= 0;
            multi_out_4d <= 0;
        end 
        else begin
        	la_write_1d <= la_write[4:0];
        	la_write_2d <= la_write_1d;
        	la_write_3d <= la_write_2d;
        	la_write_4d <= la_write_3d;
        	
        	la_input_1d <= la_input[4:0];
        	la_input_2d <= la_input_1d;
        	la_input_3d <= la_input_2d;
        	la_input_4d <= la_input_3d;
        	
        	multi_out_1d <= multi_out;
        	multi_out_2d <= multi_out_1d;
        	multi_out_3d <= multi_out_2d;
        	multi_out_4d <= multi_out_3d;
        end
    end
    
    assign multi_out = la_write_4d * la_input_4d;

    always @(posedge clk) begin
        if (reset) begin
            count <= 0;
            ready <= 0;
        end else begin
            ready <= 1'b0;
            if (~|la_write) begin
                count <= count + 1;
            end
            if (valid && !ready) begin
                ready <= 1'b1;
                rdata <= count;
                if (wstrb[0]) count[7:0]   <= wdata[7:0];
                if (wstrb[1]) count[15:8]  <= wdata[15:8];
                if (wstrb[2]) count[23:16] <= wdata[23:16];
                if (wstrb[3]) count[31:24] <= wdata[31:24];
            end else if (|la_write) begin
                count[7:0] <= multi_out_4d;
            end
        end
    end

endmodule