data/full_repos/permissive/501451666/verilog/rtl/user_analog_project_wrapper.v
1: b"%Error: data/full_repos/permissive/501451666/verilog/rtl/user_analog_project_wrapper.v:64: Define or directive not defined: '`ANALOG_PADS'\n    inout [`ANALOG_PADS-1:0] io_analog,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/501451666/verilog/rtl/user_analog_project_wrapper.v:67: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/501451666/verilog/rtl/user_analog_project_wrapper.v:120: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501451666/verilog/rtl/user_analog_project_wrapper.v:120: Define or directive not defined: '`ANALOG_PADS'\n    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,\n                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/501451666/verilog/rtl/user_analog_project_wrapper.v:121: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501451666/verilog/rtl/user_analog_project_wrapper.v:121: Define or directive not defined: '`ANALOG_PADS'\n    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,\n                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/501451666/verilog/rtl/user_analog_project_wrapper.v:122: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501451666/verilog/rtl/user_analog_project_wrapper.v:122: Define or directive not defined: '`ANALOG_PADS'\n    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,\n                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/501451666/verilog/rtl/user_analog_project_wrapper.v:123: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501451666/verilog/rtl/user_analog_project_wrapper.v:123: Define or directive not defined: '`ANALOG_PADS'\n    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,\n                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/501451666/verilog/rtl/user_analog_project_wrapper.v:140: Define or directive not defined: '`MPRJ_IO_PADS'\n    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501451666/verilog/rtl/user_analog_project_wrapper.v:140: Define or directive not defined: '`ANALOG_PADS'\n    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,\n                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/501451666/verilog/rtl/user_analog_project_wrapper.v:141: Define or directive not defined: '`MPRJ_IO_PADS'\n    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,\n           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/501451666/verilog/rtl/user_analog_project_wrapper.v:141: Define or directive not defined: '`ANALOG_PADS'\n    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,\n                         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/501451666/verilog/rtl/user_analog_project_wrapper.v:149: Define or directive not defined: '`ANALOG_PADS'\n    inout [`ANALOG_PADS-1:0] io_analog,\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/501451666/verilog/rtl/user_analog_project_wrapper.v:200: syntax error, unexpected endmodule, expecting ',' or ';'\nendmodule  \n^~~~~~~~~\n%Error: Cannot continue\n"
module user_analog_project_wrapper (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,



    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,


    
    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,


    inout [`ANALOG_PADS-1:0] io_analog,


    inout [2:0] io_clamp_high,
    inout [2:0] io_clamp_low,


    input   user_clock2,


    output [2:0] user_irq
);





reram U_reram16x16(
	`ifdef USE_POWER_PINS

    inout VDD_HIGH,
    inout VDD_LOW,
    inout VSS,
    inout V1_WL,
    inout V2_WL,
    inout V3_WL,
    inout V4_WL,
    inout V1_BL,
    inout V2_BL,
    inout V3_BL,
    inout V4_BL,
    inout V1_SL,
    inout V2_SL,
    inout V3_SL,
    inout V4_SL,

    `endif
    
    .la_data_in(la_data_in),
    .io_analog(io_analog)

)


endmodule
module user_analog_project_wrapper (
`ifdef USE_POWER_PINS
    inout vdda1,
    inout vdda2,
    inout vssa1,
    inout vssa2,
    inout vccd1,
    inout vccd2,
    inout vssd1,
    inout vssd2,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,



    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,


    
    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,


    inout [`ANALOG_PADS-1:0] io_analog,


    inout [2:0] io_clamp_high,
    inout [2:0] io_clamp_low,


    input   user_clock2,


    output [2:0] user_irq
);






reram U_reram16x16(
	`ifdef USE_POWER_PINS

    inout VDD_HIGH,
    inout VDD_LOW,
    inout VSS,
    inout V1_WL,
    inout V2_WL,
    inout V3_WL,
    inout V4_WL,
    inout V1_BL,
    inout V2_BL,
    inout V3_BL,
    inout V4_BL,
    inout V1_SL,
    inout V2_SL,
    inout V3_SL,
    inout V4_SL,

    `endif
    
    .la_data_in(la_data_in),
    .io_analog(io_analog)

)


endmodule