data/full_repos/permissive/434840709/lab2/mux4to1_based_o_2to1/mux4to1.v
1: b"%Error: data/full_repos/permissive/434840709/lab2/mux4to1_based_o_2to1/mux4to1.v:15: Cannot find file containing module: 'mux1'\n    mux1 mux2_inst(.d(d),.a(a[1]),.y(y));\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/434840709/lab2/mux4to1_based_o_2to1,data/full_repos/permissive/434840709/mux1\n             data/full_repos/permissive/434840709/lab2/mux4to1_based_o_2to1,data/full_repos/permissive/434840709/mux1.v\n             data/full_repos/permissive/434840709/lab2/mux4to1_based_o_2to1,data/full_repos/permissive/434840709/mux1.sv\n             mux1\n             mux1.v\n             mux1.sv\n             obj_dir/mux1\n             obj_dir/mux1.v\n             obj_dir/mux1.sv\n%Error: Exiting due to 1 error(s)\n"
module mux4_1(
        input  wire [1:0] d1,d2,
        input  wire [1:0] a,
        output wire       y
    );
    
    reg[1:0] d;
    always @(*) begin
        if (a[0]) begin
          assign d = d1;
        end else begin
          assign d = d2;
        end 
    end 
    mux1 mux2_inst(.d(d),.a(a[1]),.y(y));
endmodule
module mux4_1(
        input  wire [1:0] d1,d2,
        input  wire [1:0] a,
        output wire       y
    );

    
    reg[1:0] d;
    always @(*) begin
        if (a[0]) begin
          assign d = d1;
        end else begin
          assign d = d2;
        end 
    end 
    mux1 mux2_inst(.d(d),.a(a[1]),.y(y));
endmodule