data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/asyn_rst.v
data/verilator_xmls/ddb84d87-f3e6-408a-8101-293848ddd179.xml
module asyn_rst
    (
     clk,
     irst,
     orst
     
     );



parameter           ENBBUFG = 1'b0;



input   clk;
input   irst;
output  orst;



wire    orst;




  
(* ASYNC_REG = "TRUE" *) reg     irstp1 = 1'b1;
(* ASYNC_REG = "TRUE" *) reg     irstp2 = 1'b1;

always @(posedge clk or posedge irst)
    begin
    if(irst)
        begin
        irstp1 <= 1'b1;
        irstp2 <= 1'b1;
        end
    else
        begin
        irstp1 <= 1'b0;
        irstp2 <= irstp1;
        end
    end

generate
if(ENBBUFG==1'b1)
    begin : enbbufg
    BUFG BUFG (.I(irstp2), .O(orst));
    end
else
    begin : disbufg
    assign  orst = irstp2;
    end
endgenerate

endmodule
module asyn_rst
    (
     clk,
     irst,
     orst
     
     );




parameter           ENBBUFG = 1'b0;



input   clk;
input   irst;
output  orst;



wire    orst;




  
(* ASYNC_REG = "TRUE" *) reg     irstp1 = 1'b1;
(* ASYNC_REG = "TRUE" *) reg     irstp2 = 1'b1;

always @(posedge clk or posedge irst)
    begin
    if(irst)
        begin
        irstp1 <= 1'b1;
        irstp2 <= 1'b1;
        end
    else
        begin
        irstp1 <= 1'b0;
        irstp2 <= irstp1;
        end
    end

generate
if(ENBBUFG==1'b1)
    begin : enbbufg
    BUFG BUFG (.I(irstp2), .O(orst));
    end
else
    begin : disbufg
    assign  orst = irstp2;
    end
endgenerate

endmodule