data/full_repos/permissive/476810618/AD1_AD2/exact_sub_tb.v
1: b'%Error: data/full_repos/permissive/476810618/AD1_AD2/exact_sub_tb.v:1: Cannot find include file: exact_sub.v\n`include "exact_sub.v" \n         ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/476810618/AD1_AD2,data/full_repos/permissive/476810618/exact_sub.v\n             data/full_repos/permissive/476810618/AD1_AD2,data/full_repos/permissive/476810618/exact_sub.v.v\n             data/full_repos/permissive/476810618/AD1_AD2,data/full_repos/permissive/476810618/exact_sub.v.sv\n             exact_sub.v\n             exact_sub.v.v\n             exact_sub.v.sv\n             obj_dir/exact_sub.v\n             obj_dir/exact_sub.v.v\n             obj_dir/exact_sub.v.sv\n%Error: data/full_repos/permissive/476810618/AD1_AD2/exact_sub_tb.v:11: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("sub_exact.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/476810618/AD1_AD2/exact_sub_tb.v:12: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, sub_exact);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/476810618/AD1_AD2/exact_sub_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/476810618/AD1_AD2/exact_sub_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/476810618/AD1_AD2/exact_sub_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/476810618/AD1_AD2/exact_sub_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/476810618/AD1_AD2/exact_sub_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/476810618/AD1_AD2/exact_sub_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/476810618/AD1_AD2/exact_sub_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/476810618/AD1_AD2/exact_sub_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/476810618/AD1_AD2/exact_sub_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/476810618/AD1_AD2/exact_sub_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/476810618/AD1_AD2/exact_sub_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Error: Exiting due to 3 error(s), 11 warning(s)\n'
module sub_exact ;
    reg [15:0]x;
    reg [7:0]y;
    reg bin;
    wire [7:0]q;
    wire [7:0]r;
    array error (.x(x), .y(y), .bin(bin), .q(q), .r(r));
    initial begin
        $dumpfile("sub_exact.vcd");
        $dumpvars(0, sub_exact);
        bin = 0;
        x = 8; y = 4;
        #20;
        x = 7; y = 3;
        #20;
        x = 5; y = 5;
        #20;
        x = 16; y = 4;
        #20
        x = 20; y = 5;
        #20;
        x = 15; y = 3;
        #20;
        x = 12; y = 5;
        #20;
        x = 40; y = 13;
        #20;
        x = 17; y = 5;
        #20;
        x = 199; y = 7;
        #20;
        x = 127; y = 5;
        #20;
    end
endmodule
module sub_exact ;

    reg [15:0]x;
    reg [7:0]y;
    reg bin;
    wire [7:0]q;
    wire [7:0]r;
    array error (.x(x), .y(y), .bin(bin), .q(q), .r(r));
    initial begin
        $dumpfile("sub_exact.vcd");
        $dumpvars(0, sub_exact);
        bin = 0;
        x = 8; y = 4;
        #20;
        x = 7; y = 3;
        #20;
        x = 5; y = 5;
        #20;
        x = 16; y = 4;
        #20
        x = 20; y = 5;
        #20;
        x = 15; y = 3;
        #20;
        x = 12; y = 5;
        #20;
        x = 40; y = 13;
        #20;
        x = 17; y = 5;
        #20;
        x = 199; y = 7;
        #20;
        x = 127; y = 5;
        #20;
    end
endmodule