data/full_repos/permissive/432564927/Lab3 (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new/CPU.v
1: b'%Error: Cannot find file containing module: (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927\n        ... Looked in:\n             data/full_repos/permissive/432564927/Lab3/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927\n             data/full_repos/permissive/432564927/Lab3/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             data/full_repos/permissive/432564927/Lab3/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927\n             (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             obj_dir/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927\n             obj_dir/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             obj_dir/(Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/432564927/Lab3\n%Error: Cannot find file containing module: (Verilog)/Lab3_Unal/Lab3_Unal.srcs/sources_1/new/CPU.v\n%Error: Exiting due to 3 error(s)\n'
module InstructMem(if_idin,if_idout);
    input [31:0] if_idin;
    output reg [31:0] if_idout;
    initial begin
        if_idout[100] = 32'h8c220000;
        if_idout[104] = 32'h8c230004;
        if_idout[108] = 32'h8c240008;
        if_idout[112] = 32'h8c25000c;
        if_idout[116] = 32'h004a3020;
    end
    always @ (if_idin) begin
        if_idout <= if_idout[if_idin];
    end

endmodule
module InstructMem(if_idin,if_idout);

    input [31:0] if_idin;
    output reg [31:0] if_idout;
    initial begin
        if_idout[100] = 32'h8c220000;
        if_idout[104] = 32'h8c230004;
        if_idout[108] = 32'h8c240008;
        if_idout[112] = 32'h8c25000c;
        if_idout[116] = 32'h004a3020;
    end
    always @ (if_idin) begin
        if_idout <= if_idout[if_idin];
    end

endmodule