data/full_repos/permissive/479923049/datapath.v
1: b"%Error: data/full_repos/permissive/479923049/datapath.v:33: Cannot find file containing module: 'regfile'\n    regfile REGFILE(data_in,writenum,write,readnum,clk,data_out);  \n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/479923049,data/full_repos/permissive/479923049/regfile\n             data/full_repos/permissive/479923049,data/full_repos/permissive/479923049/regfile.v\n             data/full_repos/permissive/479923049,data/full_repos/permissive/479923049/regfile.sv\n             regfile\n             regfile.v\n             regfile.sv\n             obj_dir/regfile\n             obj_dir/regfile.v\n             obj_dir/regfile.sv\n%Error: data/full_repos/permissive/479923049/datapath.v:35: Cannot find file containing module: 'vDFFE'\n    vDFFE register_a(clk, loada, data_out, register_a_out);  \n    ^~~~~\n%Error: data/full_repos/permissive/479923049/datapath.v:36: Cannot find file containing module: 'vDFFE'\n    vDFFE register_b(clk, loadb, data_out, register_b_out);  \n    ^~~~~\n%Error: data/full_repos/permissive/479923049/datapath.v:40: Cannot find file containing module: 'shifter'\n    shifter shift_b(register_b_out,shift,sout);  \n    ^~~~~~~\n%Error: data/full_repos/permissive/479923049/datapath.v:44: Cannot find file containing module: 'ALU'\n    ALU alu(Ain, Bin, ALUop, ALUout, status_register_input);  \n    ^~~\n%Error: data/full_repos/permissive/479923049/datapath.v:46: Cannot find file containing module: 'vDFFE'\n    vDFFE #(3) status_reg (clk, loads, status_register_input, status_out);  \n    ^~~~~\n%Error: data/full_repos/permissive/479923049/datapath.v:47: Cannot find file containing module: 'vDFFE'\n    vDFFE register_c(clk, loadc, ALUout, register_c_out);  \n    ^~~~~\n%Error: Exiting due to 7 error(s)\n"
module datapath(clk, readnum, vsel, loada, loadb, shift, asel, bsel, ALUop, loadc, loads, writenum, write, mdata, sximm8, sximm5, PC_dp, status_out, datapath_out);
    input clk, loada, loadb, asel, bsel, loadc, loads, write;
    input [2:0] readnum; 
    input [1:0] shift;
    input [1:0] ALUop;
    input [1:0] vsel;
    input [2:0] writenum;
    input [15:0] sximm8, sximm5;
    input [7:0] PC_dp;
    output [2:0] status_out;
    output [15:0] datapath_out;

    input [15:0]mdata;


    wire [15:0] data_out, register_a_out, register_b_out, Ain, Bin, ALUout, sout, register_c_out; 
    wire [2:0] status_register_input;
    reg [15:0] data_in;



    

    always @(*) begin
        case (vsel)
            2'b00: data_in = mdata;
            2'b01: data_in = sximm8;
            2'b10: data_in = {8'd0, PC_dp};
            2'b11: data_in = datapath_out;
        endcase
    end
   
    regfile REGFILE(data_in,writenum,write,readnum,clk,data_out);

    vDFFE register_a(clk, loada, data_out, register_a_out);
    vDFFE register_b(clk, loadb, data_out, register_b_out);

    assign Ain = asel ? 16'd0 : register_a_out;

    shifter shift_b(register_b_out,shift,sout);

    assign Bin = bsel ? sximm5 : sout;
    
    ALU alu(Ain, Bin, ALUop, ALUout, status_register_input);

    vDFFE #(3) status_reg (clk, loads, status_register_input, status_out);
    vDFFE register_c(clk, loadc, ALUout, register_c_out);

    assign datapath_out = register_c_out;
    
endmodule
module datapath(clk, readnum, vsel, loada, loadb, shift, asel, bsel, ALUop, loadc, loads, writenum, write, mdata, sximm8, sximm5, PC_dp, status_out, datapath_out);

    input clk, loada, loadb, asel, bsel, loadc, loads, write;
    input [2:0] readnum; 
    input [1:0] shift;
    input [1:0] ALUop;
    input [1:0] vsel;
    input [2:0] writenum;
    input [15:0] sximm8, sximm5;
    input [7:0] PC_dp;
    output [2:0] status_out;
    output [15:0] datapath_out;

    input [15:0]mdata;


    wire [15:0] data_out, register_a_out, register_b_out, Ain, Bin, ALUout, sout, register_c_out; 
    wire [2:0] status_register_input;
    reg [15:0] data_in;



    

    always @(*) begin
        case (vsel)
            2'b00: data_in = mdata;
            2'b01: data_in = sximm8;
            2'b10: data_in = {8'd0, PC_dp};
            2'b11: data_in = datapath_out;
        endcase
    end
   
    regfile REGFILE(data_in,writenum,write,readnum,clk,data_out);

    vDFFE register_a(clk, loada, data_out, register_a_out);
    vDFFE register_b(clk, loadb, data_out, register_b_out);

    assign Ain = asel ? 16'd0 : register_a_out;

    shifter shift_b(register_b_out,shift,sout);

    assign Bin = bsel ? sximm5 : sout;
    
    ALU alu(Ain, Bin, ALUop, ALUout, status_register_input);

    vDFFE #(3) status_reg (clk, loads, status_register_input, status_out);
    vDFFE register_c(clk, loadc, ALUout, register_c_out);

    assign datapath_out = register_c_out;
    
endmodule