data/full_repos/permissive/435516446/MIPS/ALUControlUnit.v
1: b'%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/ALUControlUnit.v:31: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                             : ... In instance ALUControlUnit\n    ALUCnt = 4\'b0000;\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/ALUControlUnit.v:34: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                             : ... In instance ALUControlUnit\n    ALUCnt = 4\'b0001;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/ALUControlUnit.v:37: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h5\' generates 4 bits.\n                                                                             : ... In instance ALUControlUnit\n    ALUCnt = 4\'b0101;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/ALUControlUnit.v:40: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h6\' generates 4 bits.\n                                                                             : ... In instance ALUControlUnit\n    ALUCnt = 4\'b0110;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/ALUControlUnit.v:43: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h7\' generates 4 bits.\n                                                                             : ... In instance ALUControlUnit\n    ALUCnt = 4\'b0111;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/ALUControlUnit.v:46: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h3\' generates 4 bits.\n                                                                             : ... In instance ALUControlUnit\n    ALUCnt = 4\'b0011;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/ALUControlUnit.v:49: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h4\' generates 4 bits.\n                                                                             : ... In instance ALUControlUnit\n    ALUCnt = 4\'b0100;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/ALUControlUnit.v:52: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h2\' generates 4 bits.\n                                                                             : ... In instance ALUControlUnit\n    ALUCnt = 4\'b0010;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/ALUControlUnit.v:60: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                             : ... In instance ALUControlUnit\n  ALUCnt = 4\'b0001;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/ALUControlUnit.v:62: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h7\' generates 4 bits.\n                                                                             : ... In instance ALUControlUnit\n  ALUCnt = 4\'b0111;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/ALUControlUnit.v:64: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                             : ... In instance ALUControlUnit\n  ALUCnt = 4\'b0000;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/ALUControlUnit.v:63: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'3\'h3\' generates 3 bits.\n                                                                             : ... In instance ALUControlUnit\n else if (ALUOp == 3\'b011)  \n                ^~\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/ALUControlUnit.v:61: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'3\'h2\' generates 3 bits.\n                                                                             : ... In instance ALUControlUnit\n else if (ALUOp == 3\'b010)  \n                ^~\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/ALUControlUnit.v:59: Operator EQ expects 6 bits on the RHS, but RHS\'s CONST \'3\'h1\' generates 3 bits.\n                                                                             : ... In instance ALUControlUnit\n else if (ALUOp == 3\'b001)  \n                ^~\n%Error: Exiting due to 14 warning(s)\n'
module ALUControlUnit(
    input [5:0] ALUOp,
    input [5:0] funct,
    output reg [4:0] ALUCnt
    );
	
always@(ALUOp or funct) begin
	if (ALUOp == 0) begin
		case(funct)
			6'b000000: begin
				ALUCnt = 4'b0000;
			end
			6'b000001: begin
				ALUCnt = 4'b0001;
			end
			6'b000010: begin
				ALUCnt = 4'b0101;
			end
			6'b000011: begin
				ALUCnt = 4'b0110;
			end
			6'b000100: begin
				ALUCnt = 4'b0111;
			end
			6'b000101: begin
				ALUCnt = 4'b0011;
			end
			6'b000110: begin
				ALUCnt = 4'b0100;
			end
			6'b000111: begin
				ALUCnt = 4'b0010;
			end
			6'b001000: begin
				ALUCnt = 17;
			end
		endcase
	end
	else if (ALUOp == 3'b001)
		ALUCnt = 4'b0001;
	else if (ALUOp == 3'b010)
		ALUCnt = 4'b0111;
	else if (ALUOp == 3'b011)
		ALUCnt = 4'b0000;
	

	else if(ALUOp == 4) begin
		ALUCnt = 8;
	end
	else if(ALUOp == 5) begin
		ALUCnt = 9;
	end
	else if(ALUOp == 6) begin
		ALUCnt = 10;
	end
	else if(ALUOp == 7) begin
		ALUCnt = 11;
	end
	else if(ALUOp == 8) begin
		ALUCnt = 12;
	end
	else if(ALUOp == 9) begin
		ALUCnt = 13;
	end
	

	else if(ALUOp == 10) begin
		ALUCnt = 14;
	end

	else if(ALUOp == 11) begin
		ALUCnt = 15;
	end

	else if(ALUOp == 12) begin
		ALUCnt = 16;
	end


end

endmodule
module ALUControlUnit(
    input [5:0] ALUOp,
    input [5:0] funct,
    output reg [4:0] ALUCnt
    );

	
always@(ALUOp or funct) begin
	if (ALUOp == 0) begin
		case(funct)
			6'b000000: begin
				ALUCnt = 4'b0000;
			end
			6'b000001: begin
				ALUCnt = 4'b0001;
			end
			6'b000010: begin
				ALUCnt = 4'b0101;
			end
			6'b000011: begin
				ALUCnt = 4'b0110;
			end
			6'b000100: begin
				ALUCnt = 4'b0111;
			end
			6'b000101: begin
				ALUCnt = 4'b0011;
			end
			6'b000110: begin
				ALUCnt = 4'b0100;
			end
			6'b000111: begin
				ALUCnt = 4'b0010;
			end
			6'b001000: begin
				ALUCnt = 17;
			end
		endcase
	end
	else if (ALUOp == 3'b001)
		ALUCnt = 4'b0001;
	else if (ALUOp == 3'b010)
		ALUCnt = 4'b0111;
	else if (ALUOp == 3'b011)
		ALUCnt = 4'b0000;
	

	else if(ALUOp == 4) begin
		ALUCnt = 8;
	end
	else if(ALUOp == 5) begin
		ALUCnt = 9;
	end
	else if(ALUOp == 6) begin
		ALUCnt = 10;
	end
	else if(ALUOp == 7) begin
		ALUCnt = 11;
	end
	else if(ALUOp == 8) begin
		ALUCnt = 12;
	end
	else if(ALUOp == 9) begin
		ALUCnt = 13;
	end
	

	else if(ALUOp == 10) begin
		ALUCnt = 14;
	end

	else if(ALUOp == 11) begin
		ALUCnt = 15;
	end

	else if(ALUOp == 12) begin
		ALUCnt = 16;
	end


end

endmodule