data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_hdl_models_mux_2to1_gates.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_hdl_models_mux_2to1_gates.v:13: Signal definition not found, creating implicitly: \'inv_sel\'\n                                                                                                                     : ... Suggested alternative: \'a_sel\'\nnot U_inv (inv_sel,sel);\n           ^~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_hdl_models_mux_2to1_gates.v:14: Signal definition not found, creating implicitly: \'asel\'\n                                                                                                                     : ... Suggested alternative: \'sel\'\nand U_anda (asel,a,inv_sel),\n            ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_hdl_models_mux_2to1_gates.v:15: Signal definition not found, creating implicitly: \'bsel\'\n                                                                                                                     : ... Suggested alternative: \'sel\'\n    U_andb (bsel,b,sel);\n            ^~~~\n%Error: Exiting due to 3 warning(s)\n'
module mux_2to1_gates(a,b,sel,y);
input a,b,sel;
output y;

wire sel,a_sel,b_sel;

not U_inv (inv_sel,sel);
and U_anda (asel,a,inv_sel),
    U_andb (bsel,b,sel);
or U_or (y,asel,bsel);

endmodule
module mux_2to1_gates(a,b,sel,y);

input a,b,sel;
output y;

wire sel,a_sel,b_sel;

not U_inv (inv_sel,sel);
and U_anda (asel,a,inv_sel),
    U_andb (bsel,b,sel);
or U_or (y,asel,bsel);

endmodule