data/full_repos/permissive/454159683/cont9/cont9.v
data/verilator_xmls/f9c431bf-6377-494b-a8c4-8772711a32f1.xml
module cont9(input clk, rst, ctrl, output reg[3:0] count);
	always @(posedge clk)
	begin
		if (rst)
			count = 0;
		else if (ctrl)
			if (count == 0)
				count = 9;
			else
				count = count - 1;
		else if (count == 9)
			count = 0;
		else
			count = count + 1;
	end
endmodule
module cont9(input clk, rst, ctrl, output reg[3:0] count);

	always @(posedge clk)
	begin
		if (rst)
			count = 0;
		else if (ctrl)
			if (count == 0)
				count = 9;
			else
				count = count - 1;
		else if (count == 9)
			count = 0;
		else
			count = count + 1;
	end
endmodule