data/full_repos/permissive/447976230/fpga/usrp3/top/x400/rfdc_timing_control.v
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/rfdc_timing_control.v:67: Cannot find include file: regmap/radio_ctrlport_regmap_utils.vh\n  `include "regmap/radio_ctrlport_regmap_utils.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400,data/full_repos/permissive/447976230/regmap/radio_ctrlport_regmap_utils.vh\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400,data/full_repos/permissive/447976230/regmap/radio_ctrlport_regmap_utils.vh.v\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400,data/full_repos/permissive/447976230/regmap/radio_ctrlport_regmap_utils.vh.sv\n             regmap/radio_ctrlport_regmap_utils.vh\n             regmap/radio_ctrlport_regmap_utils.vh.v\n             regmap/radio_ctrlport_regmap_utils.vh.sv\n             obj_dir/regmap/radio_ctrlport_regmap_utils.vh\n             obj_dir/regmap/radio_ctrlport_regmap_utils.vh.v\n             obj_dir/regmap/radio_ctrlport_regmap_utils.vh.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/rfdc_timing_control.v:68: Cannot find include file: regmap/rfdc_timing_regmap_utils.vh\n  `include "regmap/rfdc_timing_regmap_utils.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module rfdc_timing_control #(
  parameter NUM_DBOARDS = 2
) (

  input wire clk,
  input wire rst,


  input wire [63:0] time_now,
  input wire        time_now_stb,
  input wire [ 3:0] time_ignore_bits,


  input  wire [  1*NUM_DBOARDS-1:0] s_ctrlport_req_wr,
  input  wire [  1*NUM_DBOARDS-1:0] s_ctrlport_req_rd,
  input  wire [ 20*NUM_DBOARDS-1:0] s_ctrlport_req_addr,
  input  wire [ 32*NUM_DBOARDS-1:0] s_ctrlport_req_data,
  input  wire [  4*NUM_DBOARDS-1:0] s_ctrlport_req_byte_en,
  input  wire [  1*NUM_DBOARDS-1:0] s_ctrlport_req_has_time,
  input  wire [ 64*NUM_DBOARDS-1:0] s_ctrlport_req_time,
  output wire [  1*NUM_DBOARDS-1:0] s_ctrlport_resp_ack,
  output wire [  2*NUM_DBOARDS-1:0] s_ctrlport_resp_status,
  output wire [ 32*NUM_DBOARDS-1:0] s_ctrlport_resp_data,


  output wire [  1*NUM_DBOARDS-1:0] m_ctrlport_req_wr,
  output wire [  1*NUM_DBOARDS-1:0] m_ctrlport_req_rd,
  output wire [ 20*NUM_DBOARDS-1:0] m_ctrlport_req_addr,
  output wire [ 32*NUM_DBOARDS-1:0] m_ctrlport_req_data,
  output wire [  4*NUM_DBOARDS-1:0] m_ctrlport_req_byte_en,
  output wire [  1*NUM_DBOARDS-1:0] m_ctrlport_req_has_time,
  output wire [ 64*NUM_DBOARDS-1:0] m_ctrlport_req_time,
  input  wire [  1*NUM_DBOARDS-1:0] m_ctrlport_resp_ack,
  input  wire [  2*NUM_DBOARDS-1:0] m_ctrlport_resp_status,
  input  wire [ 32*NUM_DBOARDS-1:0] m_ctrlport_resp_data,


  output reg  start_nco_reset,
  input  wire nco_reset_done,
  output reg  adc_reset_pulse,
  output reg  dac_reset_pulse
);

  `include "regmap/radio_ctrlport_regmap_utils.vh"
  `include "regmap/rfdc_timing_regmap_utils.vh"


  reg [NUM_DBOARDS-1:0] reg_nco_reset_start = 0;
  reg [NUM_DBOARDS-1:0] reg_adc_reset_pulse = 0;
  reg [NUM_DBOARDS-1:0] reg_dac_reset_pulse = 0;

  genvar db;
  generate
    for (db = 0; db < NUM_DBOARDS; db = db+1) begin : gen_db_ctrlport





      wire [  1-1:0] rf_ctrlport_req_wr;
      wire [  1-1:0] rf_ctrlport_req_rd;
      wire [ 20-1:0] rf_ctrlport_req_addr;
      wire [ 32-1:0] rf_ctrlport_req_data;
      wire [  4-1:0] rf_ctrlport_req_byte_en;
      wire [  1-1:0] rf_ctrlport_req_has_time;
      wire [ 64-1:0] rf_ctrlport_req_time;
      wire [  1-1:0] rf_ctrlport_resp_ack;
      wire [  2-1:0] rf_ctrlport_resp_status;
      wire [ 32-1:0] rf_ctrlport_resp_data;

      localparam [31:0] RFDC_TIMING_WINDOW_SIZE_W = $clog2(RFDC_TIMING_WINDOW_SIZE);
      localparam [31:0] DB_WINDOW_SIZE_W          = $clog2(DB_WINDOW_SIZE);

      ctrlport_decoder_param #(
        .NUM_SLAVES  (2),
        .PORT_BASE   ({ RFDC_TIMING_WINDOW[19:0],  DB_WINDOW[19:0]  }),
        .PORT_ADDR_W ({ RFDC_TIMING_WINDOW_SIZE_W, DB_WINDOW_SIZE_W })
      ) ctrlport_decoder_param_i (
        .ctrlport_clk            (clk),
        .ctrlport_rst            (rst),
        .s_ctrlport_req_wr       (s_ctrlport_req_wr       [ 1*db+: 1]),
        .s_ctrlport_req_rd       (s_ctrlport_req_rd       [ 1*db+: 1]),
        .s_ctrlport_req_addr     (s_ctrlport_req_addr     [20*db+:20]),
        .s_ctrlport_req_data     (s_ctrlport_req_data     [32*db+:32]),
        .s_ctrlport_req_byte_en  (s_ctrlport_req_byte_en  [ 4*db+: 4]),
        .s_ctrlport_req_has_time (s_ctrlport_req_has_time [ 1*db+: 1]),
        .s_ctrlport_req_time     (s_ctrlport_req_time     [64*db+:64]),
        .s_ctrlport_resp_ack     (s_ctrlport_resp_ack     [ 1*db+: 1]),
        .s_ctrlport_resp_status  (s_ctrlport_resp_status  [ 2*db+: 2]),
        .s_ctrlport_resp_data    (s_ctrlport_resp_data    [32*db+:32]),
        .m_ctrlport_req_wr       ({ rf_ctrlport_req_wr,       m_ctrlport_req_wr       [ 1*db+: 1] }),
        .m_ctrlport_req_rd       ({ rf_ctrlport_req_rd,       m_ctrlport_req_rd       [ 1*db+: 1] }),
        .m_ctrlport_req_addr     ({ rf_ctrlport_req_addr,     m_ctrlport_req_addr     [20*db+:20] }),
        .m_ctrlport_req_data     ({ rf_ctrlport_req_data,     m_ctrlport_req_data     [32*db+:32] }),
        .m_ctrlport_req_byte_en  ({ rf_ctrlport_req_byte_en,  m_ctrlport_req_byte_en  [ 4*db+: 4] }),
        .m_ctrlport_req_has_time ({ rf_ctrlport_req_has_time, m_ctrlport_req_has_time [ 1*db+: 1] }),
        .m_ctrlport_req_time     ({ rf_ctrlport_req_time,     m_ctrlport_req_time     [64*db+:64] }),
        .m_ctrlport_resp_ack     ({ rf_ctrlport_resp_ack,     m_ctrlport_resp_ack     [ 1*db+: 1] }),
        .m_ctrlport_resp_status  ({ rf_ctrlport_resp_status,  m_ctrlport_resp_status  [ 2*db+: 2] }),
        .m_ctrlport_resp_data    ({ rf_ctrlport_resp_data,    m_ctrlport_resp_data    [32*db+:32] })
      );






      wire [  1-1:0] nco_ctrlport_req_wr;
      wire [  1-1:0] nco_ctrlport_req_rd;
      wire [ 20-1:0] nco_ctrlport_req_addr;
      wire [ 32-1:0] nco_ctrlport_req_data;
      reg  [  1-1:0] nco_ctrlport_resp_ack;
      reg  [ 32-1:0] nco_ctrlport_resp_data;

      ctrlport_timer #(
        .EXEC_LATE_CMDS (1)
      ) ctrlport_timer_nco (
        .clk                     (clk),
        .rst                     (rst),
        .time_now                (time_now),
        .time_now_stb            (time_now_stb),
        .time_ignore_bits        (time_ignore_bits),
        .s_ctrlport_req_wr       (rf_ctrlport_req_wr),
        .s_ctrlport_req_rd       (rf_ctrlport_req_rd),
        .s_ctrlport_req_addr     (rf_ctrlport_req_addr),
        .s_ctrlport_req_data     (rf_ctrlport_req_data),
        .s_ctrlport_req_byte_en  (rf_ctrlport_req_byte_en),
        .s_ctrlport_req_has_time (rf_ctrlport_req_has_time),
        .s_ctrlport_req_time     (rf_ctrlport_req_time),
        .s_ctrlport_resp_ack     (rf_ctrlport_resp_ack),
        .s_ctrlport_resp_status  (rf_ctrlport_resp_status),
        .s_ctrlport_resp_data    (rf_ctrlport_resp_data),
        .m_ctrlport_req_wr       (nco_ctrlport_req_wr),
        .m_ctrlport_req_rd       (nco_ctrlport_req_rd),
        .m_ctrlport_req_addr     (nco_ctrlport_req_addr),
        .m_ctrlport_req_data     (nco_ctrlport_req_data),
        .m_ctrlport_req_byte_en  (),
        .m_ctrlport_resp_ack     (nco_ctrlport_resp_ack),
        .m_ctrlport_resp_status  (2'b0),
        .m_ctrlport_resp_data    (nco_ctrlport_resp_data)
      );

      always @(posedge clk) begin
        if (rst) begin
          nco_ctrlport_resp_ack   <= 0;
          reg_nco_reset_start[db] <= 0;
          nco_ctrlport_resp_data  <= 'bX;
        end else begin

          reg_nco_reset_start[db] <= 0;
          reg_adc_reset_pulse[db] <= 0;
          reg_dac_reset_pulse[db] <= 0;
          nco_ctrlport_resp_ack   <= 0;
          nco_ctrlport_resp_data  <= 0;


          if (nco_ctrlport_req_rd) begin
            case (nco_ctrlport_req_addr)
              NCO_RESET_REG: begin
                nco_ctrlport_resp_ack <= 1;
                nco_ctrlport_resp_data[NCO_RESET_DONE] <= nco_reset_done;
              end
              GEARBOX_RESET_REG: begin
                nco_ctrlport_resp_ack <= 1;
              end
            endcase
          end


          if (nco_ctrlport_req_wr) begin
            case (nco_ctrlport_req_addr)
              NCO_RESET_REG: begin
                nco_ctrlport_resp_ack   <= 1;
                reg_nco_reset_start[db] <= nco_ctrlport_req_data[NCO_RESET_START];
              end
              GEARBOX_RESET_REG: begin
                nco_ctrlport_resp_ack   <= 1;
                reg_adc_reset_pulse[db] <= nco_ctrlport_req_data[ADC_RESET];
                reg_dac_reset_pulse[db] <= nco_ctrlport_req_data[DAC_RESET];
              end
            endcase
          end
        end
      end

    end
  endgenerate












  always @(posedge clk) begin
    if (rst) begin
      start_nco_reset <= 0;
      adc_reset_pulse <= 0;
      dac_reset_pulse <= 0;
    end else begin
      start_nco_reset <= |reg_nco_reset_start;
      adc_reset_pulse <= |reg_adc_reset_pulse;
      dac_reset_pulse <= |reg_dac_reset_pulse;
    end
  end

endmodule
module rfdc_timing_control #(
  parameter NUM_DBOARDS = 2
) (

  input wire clk,
  input wire rst,


  input wire [63:0] time_now,
  input wire        time_now_stb,
  input wire [ 3:0] time_ignore_bits,


  input  wire [  1*NUM_DBOARDS-1:0] s_ctrlport_req_wr,
  input  wire [  1*NUM_DBOARDS-1:0] s_ctrlport_req_rd,
  input  wire [ 20*NUM_DBOARDS-1:0] s_ctrlport_req_addr,
  input  wire [ 32*NUM_DBOARDS-1:0] s_ctrlport_req_data,
  input  wire [  4*NUM_DBOARDS-1:0] s_ctrlport_req_byte_en,
  input  wire [  1*NUM_DBOARDS-1:0] s_ctrlport_req_has_time,
  input  wire [ 64*NUM_DBOARDS-1:0] s_ctrlport_req_time,
  output wire [  1*NUM_DBOARDS-1:0] s_ctrlport_resp_ack,
  output wire [  2*NUM_DBOARDS-1:0] s_ctrlport_resp_status,
  output wire [ 32*NUM_DBOARDS-1:0] s_ctrlport_resp_data,


  output wire [  1*NUM_DBOARDS-1:0] m_ctrlport_req_wr,
  output wire [  1*NUM_DBOARDS-1:0] m_ctrlport_req_rd,
  output wire [ 20*NUM_DBOARDS-1:0] m_ctrlport_req_addr,
  output wire [ 32*NUM_DBOARDS-1:0] m_ctrlport_req_data,
  output wire [  4*NUM_DBOARDS-1:0] m_ctrlport_req_byte_en,
  output wire [  1*NUM_DBOARDS-1:0] m_ctrlport_req_has_time,
  output wire [ 64*NUM_DBOARDS-1:0] m_ctrlport_req_time,
  input  wire [  1*NUM_DBOARDS-1:0] m_ctrlport_resp_ack,
  input  wire [  2*NUM_DBOARDS-1:0] m_ctrlport_resp_status,
  input  wire [ 32*NUM_DBOARDS-1:0] m_ctrlport_resp_data,


  output reg  start_nco_reset,
  input  wire nco_reset_done,
  output reg  adc_reset_pulse,
  output reg  dac_reset_pulse
);


  `include "regmap/radio_ctrlport_regmap_utils.vh"
  `include "regmap/rfdc_timing_regmap_utils.vh"


  reg [NUM_DBOARDS-1:0] reg_nco_reset_start = 0;
  reg [NUM_DBOARDS-1:0] reg_adc_reset_pulse = 0;
  reg [NUM_DBOARDS-1:0] reg_dac_reset_pulse = 0;

  genvar db;
  generate
    for (db = 0; db < NUM_DBOARDS; db = db+1) begin : gen_db_ctrlport





      wire [  1-1:0] rf_ctrlport_req_wr;
      wire [  1-1:0] rf_ctrlport_req_rd;
      wire [ 20-1:0] rf_ctrlport_req_addr;
      wire [ 32-1:0] rf_ctrlport_req_data;
      wire [  4-1:0] rf_ctrlport_req_byte_en;
      wire [  1-1:0] rf_ctrlport_req_has_time;
      wire [ 64-1:0] rf_ctrlport_req_time;
      wire [  1-1:0] rf_ctrlport_resp_ack;
      wire [  2-1:0] rf_ctrlport_resp_status;
      wire [ 32-1:0] rf_ctrlport_resp_data;

      localparam [31:0] RFDC_TIMING_WINDOW_SIZE_W = $clog2(RFDC_TIMING_WINDOW_SIZE);
      localparam [31:0] DB_WINDOW_SIZE_W          = $clog2(DB_WINDOW_SIZE);

      ctrlport_decoder_param #(
        .NUM_SLAVES  (2),
        .PORT_BASE   ({ RFDC_TIMING_WINDOW[19:0],  DB_WINDOW[19:0]  }),
        .PORT_ADDR_W ({ RFDC_TIMING_WINDOW_SIZE_W, DB_WINDOW_SIZE_W })
      ) ctrlport_decoder_param_i (
        .ctrlport_clk            (clk),
        .ctrlport_rst            (rst),
        .s_ctrlport_req_wr       (s_ctrlport_req_wr       [ 1*db+: 1]),
        .s_ctrlport_req_rd       (s_ctrlport_req_rd       [ 1*db+: 1]),
        .s_ctrlport_req_addr     (s_ctrlport_req_addr     [20*db+:20]),
        .s_ctrlport_req_data     (s_ctrlport_req_data     [32*db+:32]),
        .s_ctrlport_req_byte_en  (s_ctrlport_req_byte_en  [ 4*db+: 4]),
        .s_ctrlport_req_has_time (s_ctrlport_req_has_time [ 1*db+: 1]),
        .s_ctrlport_req_time     (s_ctrlport_req_time     [64*db+:64]),
        .s_ctrlport_resp_ack     (s_ctrlport_resp_ack     [ 1*db+: 1]),
        .s_ctrlport_resp_status  (s_ctrlport_resp_status  [ 2*db+: 2]),
        .s_ctrlport_resp_data    (s_ctrlport_resp_data    [32*db+:32]),
        .m_ctrlport_req_wr       ({ rf_ctrlport_req_wr,       m_ctrlport_req_wr       [ 1*db+: 1] }),
        .m_ctrlport_req_rd       ({ rf_ctrlport_req_rd,       m_ctrlport_req_rd       [ 1*db+: 1] }),
        .m_ctrlport_req_addr     ({ rf_ctrlport_req_addr,     m_ctrlport_req_addr     [20*db+:20] }),
        .m_ctrlport_req_data     ({ rf_ctrlport_req_data,     m_ctrlport_req_data     [32*db+:32] }),
        .m_ctrlport_req_byte_en  ({ rf_ctrlport_req_byte_en,  m_ctrlport_req_byte_en  [ 4*db+: 4] }),
        .m_ctrlport_req_has_time ({ rf_ctrlport_req_has_time, m_ctrlport_req_has_time [ 1*db+: 1] }),
        .m_ctrlport_req_time     ({ rf_ctrlport_req_time,     m_ctrlport_req_time     [64*db+:64] }),
        .m_ctrlport_resp_ack     ({ rf_ctrlport_resp_ack,     m_ctrlport_resp_ack     [ 1*db+: 1] }),
        .m_ctrlport_resp_status  ({ rf_ctrlport_resp_status,  m_ctrlport_resp_status  [ 2*db+: 2] }),
        .m_ctrlport_resp_data    ({ rf_ctrlport_resp_data,    m_ctrlport_resp_data    [32*db+:32] })
      );






      wire [  1-1:0] nco_ctrlport_req_wr;
      wire [  1-1:0] nco_ctrlport_req_rd;
      wire [ 20-1:0] nco_ctrlport_req_addr;
      wire [ 32-1:0] nco_ctrlport_req_data;
      reg  [  1-1:0] nco_ctrlport_resp_ack;
      reg  [ 32-1:0] nco_ctrlport_resp_data;

      ctrlport_timer #(
        .EXEC_LATE_CMDS (1)
      ) ctrlport_timer_nco (
        .clk                     (clk),
        .rst                     (rst),
        .time_now                (time_now),
        .time_now_stb            (time_now_stb),
        .time_ignore_bits        (time_ignore_bits),
        .s_ctrlport_req_wr       (rf_ctrlport_req_wr),
        .s_ctrlport_req_rd       (rf_ctrlport_req_rd),
        .s_ctrlport_req_addr     (rf_ctrlport_req_addr),
        .s_ctrlport_req_data     (rf_ctrlport_req_data),
        .s_ctrlport_req_byte_en  (rf_ctrlport_req_byte_en),
        .s_ctrlport_req_has_time (rf_ctrlport_req_has_time),
        .s_ctrlport_req_time     (rf_ctrlport_req_time),
        .s_ctrlport_resp_ack     (rf_ctrlport_resp_ack),
        .s_ctrlport_resp_status  (rf_ctrlport_resp_status),
        .s_ctrlport_resp_data    (rf_ctrlport_resp_data),
        .m_ctrlport_req_wr       (nco_ctrlport_req_wr),
        .m_ctrlport_req_rd       (nco_ctrlport_req_rd),
        .m_ctrlport_req_addr     (nco_ctrlport_req_addr),
        .m_ctrlport_req_data     (nco_ctrlport_req_data),
        .m_ctrlport_req_byte_en  (),
        .m_ctrlport_resp_ack     (nco_ctrlport_resp_ack),
        .m_ctrlport_resp_status  (2'b0),
        .m_ctrlport_resp_data    (nco_ctrlport_resp_data)
      );

      always @(posedge clk) begin
        if (rst) begin
          nco_ctrlport_resp_ack   <= 0;
          reg_nco_reset_start[db] <= 0;
          nco_ctrlport_resp_data  <= 'bX;
        end else begin

          reg_nco_reset_start[db] <= 0;
          reg_adc_reset_pulse[db] <= 0;
          reg_dac_reset_pulse[db] <= 0;
          nco_ctrlport_resp_ack   <= 0;
          nco_ctrlport_resp_data  <= 0;


          if (nco_ctrlport_req_rd) begin
            case (nco_ctrlport_req_addr)
              NCO_RESET_REG: begin
                nco_ctrlport_resp_ack <= 1;
                nco_ctrlport_resp_data[NCO_RESET_DONE] <= nco_reset_done;
              end
              GEARBOX_RESET_REG: begin
                nco_ctrlport_resp_ack <= 1;
              end
            endcase
          end


          if (nco_ctrlport_req_wr) begin
            case (nco_ctrlport_req_addr)
              NCO_RESET_REG: begin
                nco_ctrlport_resp_ack   <= 1;
                reg_nco_reset_start[db] <= nco_ctrlport_req_data[NCO_RESET_START];
              end
              GEARBOX_RESET_REG: begin
                nco_ctrlport_resp_ack   <= 1;
                reg_adc_reset_pulse[db] <= nco_ctrlport_req_data[ADC_RESET];
                reg_dac_reset_pulse[db] <= nco_ctrlport_req_data[DAC_RESET];
              end
            endcase
          end
        end
      end

    end
  endgenerate












  always @(posedge clk) begin
    if (rst) begin
      start_nco_reset <= 0;
      adc_reset_pulse <= 0;
      dac_reset_pulse <= 0;
    end else begin
      start_nco_reset <= |reg_nco_reset_start;
      adc_reset_pulse <= |reg_adc_reset_pulse;
      dac_reset_pulse <= |reg_dac_reset_pulse;
    end
  end

endmodule