data/full_repos/permissive/458208177/hdl/32_bit_add_cla_tree.v
data/verilator_xmls/58351226-0f93-46d8-8a2a-3b95175c06b8.xml
module gpc(G_hl, P_hl, C_h, C_l, G_h, P_h, G_l, P_l, C_in);
    output G_hl, P_hl, C_h, C_l;
    input G_h, P_h, G_l, P_l, C_in;

    wire w1;

    gp M1(G_hl, P_hl, G_h, P_h, G_l, P_l);





    and(w1, P_l, C_in);
    or(C_h, G_l, w1);

    assign C_l = C_in;

endmodule
module gpc(G_hl, P_hl, C_h, C_l, G_h, P_h, G_l, P_l, C_in);

    output G_hl, P_hl, C_h, C_l;
    input G_h, P_h, G_l, P_l, C_in;

    wire w1;

    gp M1(G_hl, P_hl, G_h, P_h, G_l, P_l);





    and(w1, P_l, C_in);
    or(C_h, G_l, w1);

    assign C_l = C_in;

endmodule