data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex1.v
1: b'%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex1.v:5: Cannot find include file: fixedpt.vh\n`include "fixedpt.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/472196771/verilog/rtl/src,data/full_repos/permissive/472196771/fixedpt.vh\n             data/full_repos/permissive/472196771/verilog/rtl/src,data/full_repos/permissive/472196771/fixedpt.vh.v\n             data/full_repos/permissive/472196771/verilog/rtl/src,data/full_repos/permissive/472196771/fixedpt.vh.sv\n             fixedpt.vh\n             fixedpt.vh.v\n             fixedpt.vh.sv\n             obj_dir/fixedpt.vh\n             obj_dir/fixedpt.vh.v\n             obj_dir/fixedpt.vh.sv\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex1.v:13: Define or directive not defined: \'`FIXPT\'\n  input `FIXPT            i_area,\n        ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex1.v:14: Define or directive not defined: \'`FIXPT\'\n  input `FIXPT            i_e1,\n        ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex1.v:15: Define or directive not defined: \'`FIXPT\'\n  input `FIXPT            i_e2,\n        ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex1.v:16: Define or directive not defined: \'`FIXPT\'\n  input `FIXPT            i_e3,\n        ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex1.v:40: Define or directive not defined: \'`FIXPT\'\n  output reg `FIXPT       o_w1,\n             ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex1.v:41: Define or directive not defined: \'`FIXPT\'\n  output reg `FIXPT       o_w2,\n             ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex1.v:42: Define or directive not defined: \'`FIXPT\'\n  output reg `FIXPT       o_w3,\n             ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex1.v:63: Define or directive not defined: \'`FIXPT_SIZE\'\n  parameter DIV_WIDTH = `FIXPT_SIZE * 2;\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex1.v:63: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n  parameter DIV_WIDTH = `FIXPT_SIZE * 2;\n                                    ^\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex1.v:64: Define or directive not defined: \'`FIXPT_SIZE\'\n  parameter PIPELINE_WIDTH = `FIXPT_SIZE;\n                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex1.v:64: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  parameter PIPELINE_WIDTH = `FIXPT_SIZE;\n                                        ^\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex1.v:65: Define or directive not defined: \'`FIXPT_SIZE\'\n  parameter DIV_PADDING = DIV_WIDTH - (`FIXPT_SIZE - `FIXPT_FRACTION_BITS);\n                                       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex1.v:65: Define or directive not defined: \'`FIXPT_FRACTION_BITS\'\n  parameter DIV_PADDING = DIV_WIDTH - (`FIXPT_SIZE - `FIXPT_FRACTION_BITS);\n                                                     ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex1.v:65: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  parameter DIV_PADDING = DIV_WIDTH - (`FIXPT_SIZE - `FIXPT_FRACTION_BITS);\n                                                                         ^\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex1.v:198: Define or directive not defined: \'`FIXPT\'\n  wire `FIXPT w_w1;\n       ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex1.v:199: Define or directive not defined: \'`FIXPT\'\n  wire `FIXPT w_w2;\n       ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex1.v:200: Define or directive not defined: \'`FIXPT\'\n  wire `FIXPT w_w3;\n       ^~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex1.v:266: Define or directive not defined: \'`FIXPT_FRACTION_BITS\'\n    .z      ({ {DIV_PADDING{1\'b0}}, i_e1, `FIXPT_FRACTION_BITS\'b0}),\n                                          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex1.v:274: Define or directive not defined: \'`FIXPT_FRACTION_BITS\'\n    .z      ({ {DIV_PADDING{1\'b0}}, i_e2, `FIXPT_FRACTION_BITS\'b0}),\n                                          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472196771/verilog/rtl/src/raster_pipeline_ex1.v:282: Define or directive not defined: \'`FIXPT_FRACTION_BITS\'\n    .z      ({ {DIV_PADDING{1\'b0}}, i_e3, `FIXPT_FRACTION_BITS\'b0}),\n                                          ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 21 error(s)\n'
module RasterPipelineEX1(
  input                   i_clk,
  input                   i_write_enable,
  input signed [15:0]     i_x_pos,
  input signed [15:0]     i_y_pos,
  input `FIXPT            i_area,
  input `FIXPT            i_e1,
  input `FIXPT            i_e2,
  input `FIXPT            i_e3,








  input [7:0]             i_v1_r,
  input [7:0]             i_v1_g,
  input [7:0]             i_v1_b,

  input [7:0]             i_v2_r,
  input [7:0]             i_v2_g,
  input [7:0]             i_v2_b,

  input [7:0]             i_v3_r,
  input [7:0]             i_v3_g,
  input [7:0]             i_v3_b,

  output reg              o_write_pixel,
  output reg signed[15:0] o_x,
  output reg signed[15:0] o_y,
  output reg `FIXPT       o_w1,
  output reg `FIXPT       o_w2,
  output reg `FIXPT       o_w3,

  output reg [7:0]        o_v1_r,
  output reg [7:0]        o_v1_g,
  output reg [7:0]        o_v1_b,

  output reg [7:0]        o_v2_r,
  output reg [7:0]        o_v2_g,
  output reg [7:0]        o_v2_b,

  output reg [7:0]        o_v3_r,
  output reg [7:0]        o_v3_g,
  output reg [7:0]        o_v3_b







);
  parameter DIV_WIDTH = `FIXPT_SIZE * 2;
  parameter PIPELINE_WIDTH = `FIXPT_SIZE;
  parameter DIV_PADDING = DIV_WIDTH - (`FIXPT_SIZE - `FIXPT_FRACTION_BITS);

  reg signed [15:0] x_pos_pipe[0:PIPELINE_WIDTH];
  reg signed [15:0] y_pos_pipe[0:PIPELINE_WIDTH];









  reg [7:0] v1_r_pipe[0:PIPELINE_WIDTH];
  reg [7:0] v1_g_pipe[0:PIPELINE_WIDTH];
  reg [7:0] v1_b_pipe[0:PIPELINE_WIDTH];

  reg [7:0] v2_r_pipe[0:PIPELINE_WIDTH];
  reg [7:0] v2_g_pipe[0:PIPELINE_WIDTH];
  reg [7:0] v2_b_pipe[0:PIPELINE_WIDTH];

  reg [7:0] v3_r_pipe[0:PIPELINE_WIDTH];
  reg [7:0] v3_g_pipe[0:PIPELINE_WIDTH];
  reg [7:0] v3_b_pipe[0:PIPELINE_WIDTH];

  reg [31:0] counter = 0;

  integer i;

  initial begin
    for (i = 0; i <= PIPELINE_WIDTH; i = i+1)
    begin
      x_pos_pipe[i] <= 0;
      y_pos_pipe[i] <= 0;
      v1_r_pipe[i]  <= 0;
      v1_g_pipe[i]  <= 0;
      v1_b_pipe[i]  <= 0;

      v2_r_pipe[i]  <= 0;
      v2_g_pipe[i]  <= 0;
      v2_b_pipe[i]  <= 0;

      v3_r_pipe[i]  <= 0;
      v3_g_pipe[i]  <= 0;
      v3_b_pipe[i]  <= 0;







    end
  end


  always @(posedge i_clk)
  begin
    counter <= counter + 1;
    if (i_write_enable)
    begin
      x_pos_pipe[0] <= i_x_pos;
      y_pos_pipe[0] <= i_y_pos;
      
      v1_r_pipe[0]  <= i_v1_r;
      v1_g_pipe[0]  <= i_v1_g;
      v1_b_pipe[0]  <= i_v1_b;
      
      v2_r_pipe[0]  <= i_v2_r;
      v2_g_pipe[0]  <= i_v2_g;
      v2_b_pipe[0]  <= i_v2_b;

      v3_r_pipe[0]  <= i_v3_r;
      v3_g_pipe[0]  <= i_v3_g;
      v3_b_pipe[0]  <= i_v3_b;








    end
    else
    begin
      x_pos_pipe[0] <= 32'bx;
      y_pos_pipe[0] <= 32'bx;
      v1_r_pipe[0]  <= 32'bx;
      v1_g_pipe[0]  <= 32'bx;
      v1_b_pipe[0]  <= 32'bx;
      v2_r_pipe[0]  <= 32'bx;
      v2_g_pipe[0]  <= 32'bx;
      v2_b_pipe[0]  <= 32'bx;
      v3_r_pipe[0]  <= 32'bx;
      v3_g_pipe[0]  <= 32'bx;
      v3_b_pipe[0]  <= 32'bx;







    end


    for (i = 1; i <= PIPELINE_WIDTH; i = i+1)
    begin
      x_pos_pipe[i] <= x_pos_pipe[i - 1];
      y_pos_pipe[i] <= y_pos_pipe[i - 1];

      v1_r_pipe[i]  <= v1_r_pipe[i - 1];
      v1_g_pipe[i]  <= v1_g_pipe[i - 1];
      v1_b_pipe[i]  <= v1_b_pipe[i - 1];

      v2_r_pipe[i]  <= v2_r_pipe[i - 1];
      v2_g_pipe[i]  <= v2_g_pipe[i - 1];
      v2_b_pipe[i]  <= v2_b_pipe[i - 1];

      v3_r_pipe[i]  <= v3_r_pipe[i - 1];
      v3_g_pipe[i]  <= v3_g_pipe[i - 1];
      v3_b_pipe[i]  <= v3_b_pipe[i - 1];







    end
  end

  wire `FIXPT w_w1;
  wire `FIXPT w_w2;
  wire `FIXPT w_w3;

  wire valid;

  always @(posedge i_clk)
  begin
    if (valid)
    begin
      o_write_pixel <= 1;
      o_x           <= x_pos_pipe[PIPELINE_WIDTH];
      o_y           <= y_pos_pipe[PIPELINE_WIDTH];
      
      o_w1          <= w_w1;
      o_w2          <= w_w2;
      o_w3          <= w_w3;

      o_v1_r        <= v1_r_pipe[PIPELINE_WIDTH];
      o_v1_g        <= v1_g_pipe[PIPELINE_WIDTH];
      o_v1_b        <= v1_b_pipe[PIPELINE_WIDTH];

      o_v2_r        <= v2_r_pipe[PIPELINE_WIDTH];
      o_v2_g        <= v2_g_pipe[PIPELINE_WIDTH];
      o_v2_b        <= v2_b_pipe[PIPELINE_WIDTH];
      
      o_v3_r        <= v3_r_pipe[PIPELINE_WIDTH];
      o_v3_g        <= v3_g_pipe[PIPELINE_WIDTH];
      o_v3_b        <= v3_b_pipe[PIPELINE_WIDTH];










    end
    else begin
      o_write_pixel <= 0;
    end
  end
  
  pipeline_ctrl #(PIPELINE_WIDTH) pc(
    .i_clk      (i_clk),
    .i_enable   (i_write_enable),
    .o_ack      (valid)
  );

  div_uu #(DIV_WIDTH) w1_div(
    .clk    (i_clk),
    .ena    (1'b1),
    .z      ({ {DIV_PADDING{1'b0}}, i_e1, `FIXPT_FRACTION_BITS'b0}),
    .d      (i_area),
    .q      (w_w1)
  );

  div_uu #(DIV_WIDTH) w2_div(
    .clk    (i_clk),
    .ena    (1'b1),
    .z      ({ {DIV_PADDING{1'b0}}, i_e2, `FIXPT_FRACTION_BITS'b0}),
    .d      (i_area),
    .q      (w_w2)
  );

  div_uu #(DIV_WIDTH) w3_div(
    .clk    (i_clk),
    .ena    (1'b1),
    .z      ({ {DIV_PADDING{1'b0}}, i_e3, `FIXPT_FRACTION_BITS'b0}),
    .d      (i_area),
    .q      (w_w3)
  );

endmodule
module RasterPipelineEX1(
  input                   i_clk,
  input                   i_write_enable,
  input signed [15:0]     i_x_pos,
  input signed [15:0]     i_y_pos,
  input `FIXPT            i_area,
  input `FIXPT            i_e1,
  input `FIXPT            i_e2,
  input `FIXPT            i_e3,








  input [7:0]             i_v1_r,
  input [7:0]             i_v1_g,
  input [7:0]             i_v1_b,

  input [7:0]             i_v2_r,
  input [7:0]             i_v2_g,
  input [7:0]             i_v2_b,

  input [7:0]             i_v3_r,
  input [7:0]             i_v3_g,
  input [7:0]             i_v3_b,

  output reg              o_write_pixel,
  output reg signed[15:0] o_x,
  output reg signed[15:0] o_y,
  output reg `FIXPT       o_w1,
  output reg `FIXPT       o_w2,
  output reg `FIXPT       o_w3,

  output reg [7:0]        o_v1_r,
  output reg [7:0]        o_v1_g,
  output reg [7:0]        o_v1_b,

  output reg [7:0]        o_v2_r,
  output reg [7:0]        o_v2_g,
  output reg [7:0]        o_v2_b,

  output reg [7:0]        o_v3_r,
  output reg [7:0]        o_v3_g,
  output reg [7:0]        o_v3_b







);

  parameter DIV_WIDTH = `FIXPT_SIZE * 2;
  parameter PIPELINE_WIDTH = `FIXPT_SIZE;
  parameter DIV_PADDING = DIV_WIDTH - (`FIXPT_SIZE - `FIXPT_FRACTION_BITS);

  reg signed [15:0] x_pos_pipe[0:PIPELINE_WIDTH];
  reg signed [15:0] y_pos_pipe[0:PIPELINE_WIDTH];









  reg [7:0] v1_r_pipe[0:PIPELINE_WIDTH];
  reg [7:0] v1_g_pipe[0:PIPELINE_WIDTH];
  reg [7:0] v1_b_pipe[0:PIPELINE_WIDTH];

  reg [7:0] v2_r_pipe[0:PIPELINE_WIDTH];
  reg [7:0] v2_g_pipe[0:PIPELINE_WIDTH];
  reg [7:0] v2_b_pipe[0:PIPELINE_WIDTH];

  reg [7:0] v3_r_pipe[0:PIPELINE_WIDTH];
  reg [7:0] v3_g_pipe[0:PIPELINE_WIDTH];
  reg [7:0] v3_b_pipe[0:PIPELINE_WIDTH];

  reg [31:0] counter = 0;

  integer i;

  initial begin
    for (i = 0; i <= PIPELINE_WIDTH; i = i+1)
    begin
      x_pos_pipe[i] <= 0;
      y_pos_pipe[i] <= 0;
      v1_r_pipe[i]  <= 0;
      v1_g_pipe[i]  <= 0;
      v1_b_pipe[i]  <= 0;

      v2_r_pipe[i]  <= 0;
      v2_g_pipe[i]  <= 0;
      v2_b_pipe[i]  <= 0;

      v3_r_pipe[i]  <= 0;
      v3_g_pipe[i]  <= 0;
      v3_b_pipe[i]  <= 0;







    end
  end


  always @(posedge i_clk)
  begin
    counter <= counter + 1;
    if (i_write_enable)
    begin
      x_pos_pipe[0] <= i_x_pos;
      y_pos_pipe[0] <= i_y_pos;
      
      v1_r_pipe[0]  <= i_v1_r;
      v1_g_pipe[0]  <= i_v1_g;
      v1_b_pipe[0]  <= i_v1_b;
      
      v2_r_pipe[0]  <= i_v2_r;
      v2_g_pipe[0]  <= i_v2_g;
      v2_b_pipe[0]  <= i_v2_b;

      v3_r_pipe[0]  <= i_v3_r;
      v3_g_pipe[0]  <= i_v3_g;
      v3_b_pipe[0]  <= i_v3_b;








    end
    else
    begin
      x_pos_pipe[0] <= 32'bx;
      y_pos_pipe[0] <= 32'bx;
      v1_r_pipe[0]  <= 32'bx;
      v1_g_pipe[0]  <= 32'bx;
      v1_b_pipe[0]  <= 32'bx;
      v2_r_pipe[0]  <= 32'bx;
      v2_g_pipe[0]  <= 32'bx;
      v2_b_pipe[0]  <= 32'bx;
      v3_r_pipe[0]  <= 32'bx;
      v3_g_pipe[0]  <= 32'bx;
      v3_b_pipe[0]  <= 32'bx;







    end


    for (i = 1; i <= PIPELINE_WIDTH; i = i+1)
    begin
      x_pos_pipe[i] <= x_pos_pipe[i - 1];
      y_pos_pipe[i] <= y_pos_pipe[i - 1];

      v1_r_pipe[i]  <= v1_r_pipe[i - 1];
      v1_g_pipe[i]  <= v1_g_pipe[i - 1];
      v1_b_pipe[i]  <= v1_b_pipe[i - 1];

      v2_r_pipe[i]  <= v2_r_pipe[i - 1];
      v2_g_pipe[i]  <= v2_g_pipe[i - 1];
      v2_b_pipe[i]  <= v2_b_pipe[i - 1];

      v3_r_pipe[i]  <= v3_r_pipe[i - 1];
      v3_g_pipe[i]  <= v3_g_pipe[i - 1];
      v3_b_pipe[i]  <= v3_b_pipe[i - 1];







    end
  end

  wire `FIXPT w_w1;
  wire `FIXPT w_w2;
  wire `FIXPT w_w3;

  wire valid;

  always @(posedge i_clk)
  begin
    if (valid)
    begin
      o_write_pixel <= 1;
      o_x           <= x_pos_pipe[PIPELINE_WIDTH];
      o_y           <= y_pos_pipe[PIPELINE_WIDTH];
      
      o_w1          <= w_w1;
      o_w2          <= w_w2;
      o_w3          <= w_w3;

      o_v1_r        <= v1_r_pipe[PIPELINE_WIDTH];
      o_v1_g        <= v1_g_pipe[PIPELINE_WIDTH];
      o_v1_b        <= v1_b_pipe[PIPELINE_WIDTH];

      o_v2_r        <= v2_r_pipe[PIPELINE_WIDTH];
      o_v2_g        <= v2_g_pipe[PIPELINE_WIDTH];
      o_v2_b        <= v2_b_pipe[PIPELINE_WIDTH];
      
      o_v3_r        <= v3_r_pipe[PIPELINE_WIDTH];
      o_v3_g        <= v3_g_pipe[PIPELINE_WIDTH];
      o_v3_b        <= v3_b_pipe[PIPELINE_WIDTH];










    end
    else begin
      o_write_pixel <= 0;
    end
  end
  
  pipeline_ctrl #(PIPELINE_WIDTH) pc(
    .i_clk      (i_clk),
    .i_enable   (i_write_enable),
    .o_ack      (valid)
  );

  div_uu #(DIV_WIDTH) w1_div(
    .clk    (i_clk),
    .ena    (1'b1),
    .z      ({ {DIV_PADDING{1'b0}}, i_e1, `FIXPT_FRACTION_BITS'b0}),
    .d      (i_area),
    .q      (w_w1)
  );

  div_uu #(DIV_WIDTH) w2_div(
    .clk    (i_clk),
    .ena    (1'b1),
    .z      ({ {DIV_PADDING{1'b0}}, i_e2, `FIXPT_FRACTION_BITS'b0}),
    .d      (i_area),
    .q      (w_w2)
  );

  div_uu #(DIV_WIDTH) w3_div(
    .clk    (i_clk),
    .ena    (1'b1),
    .z      ({ {DIV_PADDING{1'b0}}, i_e3, `FIXPT_FRACTION_BITS'b0}),
    .d      (i_area),
    .q      (w_w3)
  );

endmodule