data/full_repos/permissive/501791642/src/uart/uart_rx.v
1: b"%Error: data/full_repos/permissive/501791642/src/uart/uart_rx.v:37: Cannot find file containing module: 'shift_reg'\nshift_reg #(\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/501791642/src/uart,data/full_repos/permissive/501791642/shift_reg\n             data/full_repos/permissive/501791642/src/uart,data/full_repos/permissive/501791642/shift_reg.v\n             data/full_repos/permissive/501791642/src/uart,data/full_repos/permissive/501791642/shift_reg.sv\n             shift_reg\n             shift_reg.v\n             shift_reg.sv\n             obj_dir/shift_reg\n             obj_dir/shift_reg.v\n             obj_dir/shift_reg.sv\n%Error: data/full_repos/permissive/501791642/src/uart/uart_rx.v:51: Cannot find file containing module: 'up_cnt_mod'\nup_cnt_mod #(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/501791642/src/uart/uart_rx.v:64: Cannot find file containing module: 'up_cnt_mod'\nup_cnt_mod #(\n^~~~~~~~~~\n%Error: data/full_repos/permissive/501791642/src/uart/uart_rx.v:78: Cannot find file containing module: 'uart_fsm'\nuart_fsm fsm (\n^~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module uart_rx #(
    parameter CLKS_PER_BIT = 3200,
    parameter CLKS_PER_BIT_W = 12
)
(
    input           CLK,
    input           CE,
    input           RST,
    input           DI,
    output          DV,
    output [7:0]    PO  
);

parameter HALF_BAUD = CLKS_PER_BIT/2;
parameter IDLE = 3'b000;
parameter START = 3'b001;
parameter START_CHECK = 3'b010;
parameter READ = 3'b011;
parameter STOP = 3'b100;

wire [2:0] status;
wire [CLKS_PER_BIT_W-1:0] baud_cnt;
wire [3:0] bit_cnt;
wire HB, BD, LB;
wire baud_reset;
reg data;

assign DV = (status == STOP) & BD & data;
assign HB = (baud_cnt == HALF_BAUD-1);
assign baud_reset = ((status == START) & HB) | (status == IDLE);


always @(posedge CLK)
    data <= DI;

shift_reg #(
    .W(8)
)
out_reg
(
    .CLK(CLK),
    .CE( (status == READ) & BD ),
    .CLR(RST),
    .DIR(1'b1),
    .D(data),
    .Q(PO)
);


up_cnt_mod #(
    .MODULO(CLKS_PER_BIT),
    .W(CLKS_PER_BIT_W)
)
baud_counter
(
    .CLK(CLK),
    .CE(~baud_reset),
    .CLR(baud_reset),
    .Q(baud_cnt),
    .CO(BD)
);

up_cnt_mod #(
    .MODULO(8),
    .W(3)
)
bit_counter
(
    .CLK(CLK),
    .CE((status == READ) & BD),
    .CLR(status == IDLE),
    .Q(bit_cnt),
    .CO(LB)
);


uart_fsm fsm (
	.CLK(CLK),
	.CE(CE),
	.CLR(RST),
	.DI(data),
	.HB(HB),
	.BD(BD),
	.LB(LB),
	.STATUS(status)
);

endmodule
module uart_rx #(
    parameter CLKS_PER_BIT = 3200,
    parameter CLKS_PER_BIT_W = 12
)
(
    input           CLK,
    input           CE,
    input           RST,
    input           DI,
    output          DV,
    output [7:0]    PO  
);


parameter HALF_BAUD = CLKS_PER_BIT/2;
parameter IDLE = 3'b000;
parameter START = 3'b001;
parameter START_CHECK = 3'b010;
parameter READ = 3'b011;
parameter STOP = 3'b100;

wire [2:0] status;
wire [CLKS_PER_BIT_W-1:0] baud_cnt;
wire [3:0] bit_cnt;
wire HB, BD, LB;
wire baud_reset;
reg data;

assign DV = (status == STOP) & BD & data;
assign HB = (baud_cnt == HALF_BAUD-1);
assign baud_reset = ((status == START) & HB) | (status == IDLE);


always @(posedge CLK)
    data <= DI;

shift_reg #(
    .W(8)
)
out_reg
(
    .CLK(CLK),
    .CE( (status == READ) & BD ),
    .CLR(RST),
    .DIR(1'b1),
    .D(data),
    .Q(PO)
);


up_cnt_mod #(
    .MODULO(CLKS_PER_BIT),
    .W(CLKS_PER_BIT_W)
)
baud_counter
(
    .CLK(CLK),
    .CE(~baud_reset),
    .CLR(baud_reset),
    .Q(baud_cnt),
    .CO(BD)
);

up_cnt_mod #(
    .MODULO(8),
    .W(3)
)
bit_counter
(
    .CLK(CLK),
    .CE((status == READ) & BD),
    .CLR(status == IDLE),
    .Q(bit_cnt),
    .CO(LB)
);


uart_fsm fsm (
	.CLK(CLK),
	.CE(CE),
	.CLR(RST),
	.DI(data),
	.HB(HB),
	.BD(BD),
	.LB(LB),
	.STATUS(status)
);

endmodule