data/full_repos/permissive/466926510/Project_files/Top_design.v
1: b"%Error: data/full_repos/permissive/466926510/Project_files/Top_design.v:38: Cannot find file containing module: 'Reg_A'\nReg_A R1 (d_in , load_A  , i_clk ,out_A);\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/466926510/Project_files,data/full_repos/permissive/466926510/Reg_A\n             data/full_repos/permissive/466926510/Project_files,data/full_repos/permissive/466926510/Reg_A.v\n             data/full_repos/permissive/466926510/Project_files,data/full_repos/permissive/466926510/Reg_A.sv\n             Reg_A\n             Reg_A.v\n             Reg_A.sv\n             obj_dir/Reg_A\n             obj_dir/Reg_A.v\n             obj_dir/Reg_A.sv\n%Error: data/full_repos/permissive/466926510/Project_files/Top_design.v:39: Cannot find file containing module: 'Reg_B'\nReg_B  R2(d_in , load_B  , i_clk ,out_B);\n^~~~~\n%Error: data/full_repos/permissive/466926510/Project_files/Top_design.v:40: Cannot find file containing module: 'CMP'\n CMP   C1(out_A, out_B , EQ , LT , GT );\n ^~~\n%Error: data/full_repos/permissive/466926510/Project_files/Top_design.v:41: Cannot find file containing module: 'SUB_AB'\n SUB_AB  S1(M_outA, M_outB , Sub_out );\n ^~~~~~\n%Error: data/full_repos/permissive/466926510/Project_files/Top_design.v:42: Cannot find file containing module: 'mux_A'\n mux_A     M1(out_A , out_B , M_outA, s_in1 );\n ^~~~~\n%Error: data/full_repos/permissive/466926510/Project_files/Top_design.v:43: Cannot find file containing module: 'mux_B'\n mux_B   M2(out_A , out_B , M_outB  , s_in2);\n ^~~~~\n%Error: data/full_repos/permissive/466926510/Project_files/Top_design.v:44: Cannot find file containing module: 'Mux_D'\n Mux_D   M3(Sub_out , data_input , d_in  , s_in3  );\n ^~~~~\n%Error: Exiting due to 7 error(s)\n"
module Top_design(
data_input , i_clk  , EQ, LT, GT,s_in1 , s_in2 , s_in3,load_A, load_B, out_A, out_B, Sub_out
    );
input [`DATA_WID-1:0] data_input ;
input i_clk ;
input load_A, load_B ;
input s_in1 , s_in2 , s_in3 ;
output EQ, LT , GT ;
wire [`DATA_WID-1:0] M_outA , M_outB ;
output  [`DATA_WID-1:0] out_A ; 
 output  [`DATA_WID-1:0]  out_B ;
output [`DATA_WID-1:0] Sub_out ;
wire [`DATA_WID-1:0] d_in ;

Reg_A R1 (d_in , load_A  , i_clk ,out_A);
Reg_B  R2(d_in , load_B  , i_clk ,out_B);
 CMP   C1(out_A, out_B , EQ , LT , GT );
 SUB_AB  S1(M_outA, M_outB , Sub_out );
 mux_A     M1(out_A , out_B , M_outA, s_in1 );
 mux_B   M2(out_A , out_B , M_outB  , s_in2);
 Mux_D   M3(Sub_out , data_input , d_in  , s_in3  );
 
 
endmodule
module Top_design(
data_input , i_clk  , EQ, LT, GT,s_in1 , s_in2 , s_in3,load_A, load_B, out_A, out_B, Sub_out
    );

input [`DATA_WID-1:0] data_input ;
input i_clk ;
input load_A, load_B ;
input s_in1 , s_in2 , s_in3 ;
output EQ, LT , GT ;
wire [`DATA_WID-1:0] M_outA , M_outB ;
output  [`DATA_WID-1:0] out_A ; 
 output  [`DATA_WID-1:0]  out_B ;
output [`DATA_WID-1:0] Sub_out ;
wire [`DATA_WID-1:0] d_in ;

Reg_A R1 (d_in , load_A  , i_clk ,out_A);
Reg_B  R2(d_in , load_B  , i_clk ,out_B);
 CMP   C1(out_A, out_B , EQ , LT , GT );
 SUB_AB  S1(M_outA, M_outB , Sub_out );
 mux_A     M1(out_A , out_B , M_outA, s_in1 );
 mux_B   M2(out_A , out_B , M_outB  , s_in2);
 Mux_D   M3(Sub_out , data_input , d_in  , s_in3  );
 
 
endmodule