data/full_repos/permissive/479923049/regfile_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/479923049/regfile_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n        clk = 0; #5;\n                 ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/479923049/regfile_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n            clk = 1; #5;\n                     ^\n%Warning-STMTDLY: data/full_repos/permissive/479923049/regfile_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n            clk = 0; #5;\n                     ^\n%Error: data/full_repos/permissive/479923049/regfile_tb.v:18: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n    task checker;\n         ^~~~~~~\n%Error: data/full_repos/permissive/479923049/regfile_tb.v:18: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    task checker;\n                ^\n%Error: data/full_repos/permissive/479923049/regfile_tb.v:21: syntax error, unexpected begin\n        begin \n        ^~~~~\n%Error: data/full_repos/permissive/479923049/regfile_tb.v:37: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n        checker(16\'d65); #5; \n        ^~~~~~~\n%Error: data/full_repos/permissive/479923049/regfile_tb.v:39: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n        checker(16\'d100); #5;\n        ^~~~~~~\n%Error: data/full_repos/permissive/479923049/regfile_tb.v:41: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n        checker(16\'d45); #5;\n        ^~~~~~~\n%Error: data/full_repos/permissive/479923049/regfile_tb.v:43: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n        checker(16\'d12); #5\n        ^~~~~~~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module regfile_tb();
    reg [15:0] data_in;
    reg [2:0] writenum, readnum;
    reg write, clk, err;

    wire [15:0] data_out;

    regfile DUT (data_in,writenum,write,readnum,clk,data_out);

    initial begin
        clk = 0; #5;
        forever begin
            clk = 1; #5;
            clk = 0; #5;
        end
    end

    task checker;
        input [15:0] expected_data_out;

        begin 
            if( data_out !== expected_data_out ) begin
            $display("ERROR ** data_out is %b, expected %b", data_out, expected_data_out );
            err = 1'b1;
            end
        end
    endtask
  

    initial begin
        data_in = 16'd65; writenum = 3'b000; readnum =3'b000; write = 1'b1; err = 1'b0; #10; 
        data_in = 16'd100; writenum = 3'b001; readnum = 3'b000; write = 1'b1; err = 1'b0; #10;
        data_in = 16'd45; writenum = 3'b100; readnum = 3'b000; write = 1'b1; err = 1'b0; #10;
        data_in = 16'd12; writenum = 3'b101; readnum = 3'b000; write = 1'b1; err = 1'b0; #10;
        write = 1'b0; #5;
        readnum = 3'b000;
        checker(16'd65); #5; 
        readnum = 3'b001; #5;
        checker(16'd100); #5;
        readnum = 3'b100; #5;
        checker(16'd45); #5;
        readnum = 3'b101; #5;
        checker(16'd12); #5
        
        if( ~err ) $display("PASSED");
        else $display("FAILED");


        
    end
endmodule
module regfile_tb();

    reg [15:0] data_in;
    reg [2:0] writenum, readnum;
    reg write, clk, err;

    wire [15:0] data_out;

    regfile DUT (data_in,writenum,write,readnum,clk,data_out);

    initial begin
        clk = 0; #5;
        forever begin
            clk = 1; #5;
            clk = 0; #5;
        end
    end

    task checker;
        input [15:0] expected_data_out;

        begin 
            if( data_out !== expected_data_out ) begin
            $display("ERROR ** data_out is %b, expected %b", data_out, expected_data_out );
            err = 1'b1;
            end
        end
    endtask
  

    initial begin
        data_in = 16'd65; writenum = 3'b000; readnum =3'b000; write = 1'b1; err = 1'b0; #10; 
        data_in = 16'd100; writenum = 3'b001; readnum = 3'b000; write = 1'b1; err = 1'b0; #10;
        data_in = 16'd45; writenum = 3'b100; readnum = 3'b000; write = 1'b1; err = 1'b0; #10;
        data_in = 16'd12; writenum = 3'b101; readnum = 3'b000; write = 1'b1; err = 1'b0; #10;
        write = 1'b0; #5;
        readnum = 3'b000;
        checker(16'd65); #5; 
        readnum = 3'b001; #5;
        checker(16'd100); #5;
        readnum = 3'b100; #5;
        checker(16'd45); #5;
        readnum = 3'b101; #5;
        checker(16'd12); #5
        
        if( ~err ) $display("PASSED");
        else $display("FAILED");


        
    end
endmodule