data/full_repos/permissive/441359809/src/yosys/manual/PRESENTATION_ExAdv/macc_xilinx_xmap.v
data/verilator_xmls/d1a33396-0066-4947-9077-7215572191f9.xml
module DSP48_MACC (a, b, c, y);

input [17:0] a;
input [24:0] b;
input [47:0] c;
output [47:0] y;

assign y = a*b + c;

endmodule
module DSP48_MACC (a, b, c, y);


input [17:0] a;
input [24:0] b;
input [47:0] c;
output [47:0] y;

assign y = a*b + c;

endmodule