data/full_repos/permissive/405799749/amg_new2/adder/FSA_16_64_Carry_select_adder.v
data/verilator_xmls/a1e22f4f-1bee-4d86-a007-eae88622d5c2.xml
module UBCSlB_63_56(Co, S, X, Y, Ci);
  output Co;
  output [63:56] S;
  input Ci;
  input [63:56] X;
  input [63:56] Y;
  wire Ci_0;
  wire Ci_1;
  wire Co_0;
  wire Co_1;
  wire [63:56] S_0;
  wire [63:56] S_1;
  assign S[56] = ( S_0[56] & ( ~ Ci ) ) | ( S_1[56] & Ci );
  assign S[57] = ( S_0[57] & ( ~ Ci ) ) | ( S_1[57] & Ci );
  assign S[58] = ( S_0[58] & ( ~ Ci ) ) | ( S_1[58] & Ci );
  assign S[59] = ( S_0[59] & ( ~ Ci ) ) | ( S_1[59] & Ci );
  assign S[60] = ( S_0[60] & ( ~ Ci ) ) | ( S_1[60] & Ci );
  assign S[61] = ( S_0[61] & ( ~ Ci ) ) | ( S_1[61] & Ci );
  assign S[62] = ( S_0[62] & ( ~ Ci ) ) | ( S_1[62] & Ci );
  assign S[63] = ( S_0[63] & ( ~ Ci ) ) | ( S_1[63] & Ci );
  assign Co = ( Co_0 & ( ~ Ci ) ) | ( Co_1 & Ci );
  UBOne_56 U0 (Ci_1);
  UBZero_56_56 U1 (Ci_0);
  UBRCB_63_56 U2 (Co_0, S_0, X, Y, Ci_0);
  UBRCB_63_56 U3 (Co_1, S_1, X, Y, Ci_1);
endmodule
module UBCSlB_63_56(Co, S, X, Y, Ci);

  output Co;
  output [63:56] S;
  input Ci;
  input [63:56] X;
  input [63:56] Y;
  wire Ci_0;
  wire Ci_1;
  wire Co_0;
  wire Co_1;
  wire [63:56] S_0;
  wire [63:56] S_1;
  assign S[56] = ( S_0[56] & ( ~ Ci ) ) | ( S_1[56] & Ci );
  assign S[57] = ( S_0[57] & ( ~ Ci ) ) | ( S_1[57] & Ci );
  assign S[58] = ( S_0[58] & ( ~ Ci ) ) | ( S_1[58] & Ci );
  assign S[59] = ( S_0[59] & ( ~ Ci ) ) | ( S_1[59] & Ci );
  assign S[60] = ( S_0[60] & ( ~ Ci ) ) | ( S_1[60] & Ci );
  assign S[61] = ( S_0[61] & ( ~ Ci ) ) | ( S_1[61] & Ci );
  assign S[62] = ( S_0[62] & ( ~ Ci ) ) | ( S_1[62] & Ci );
  assign S[63] = ( S_0[63] & ( ~ Ci ) ) | ( S_1[63] & Ci );
  assign Co = ( Co_0 & ( ~ Ci ) ) | ( Co_1 & Ci );
  UBOne_56 U0 (Ci_1);
  UBZero_56_56 U1 (Ci_0);
  UBRCB_63_56 U2 (Co_0, S_0, X, Y, Ci_0);
  UBRCB_63_56 U3 (Co_1, S_1, X, Y, Ci_1);
endmodule