data/full_repos/permissive/492462267/ctrl.v
data/verilator_xmls/60d0e9e8-8f08-43ff-bccb-4494ec1241c9.xml
module ctrl (
    input  wire     rst,
    input  wire     stall_from_id,
    input  wire     stall_from_ex,
    output reg[5:0] stall
);

always@(*) begin
    if(rst) begin
        stall = 6'b000000;
    end else if(stall_from_ex)begin
        stall = 6'b001111;
    end else if(stall_from_id) begin
        stall = 6'b000111;
    end else begin
        stall = 6'b000000;
    end
end

endmodule
module ctrl (
    input  wire     rst,
    input  wire     stall_from_id,
    input  wire     stall_from_ex,
    output reg[5:0] stall
);


always@(*) begin
    if(rst) begin
        stall = 6'b000000;
    end else if(stall_from_ex)begin
        stall = 6'b001111;
    end else if(stall_from_id) begin
        stall = 6'b000111;
    end else begin
        stall = 6'b000000;
    end
end

endmodule