data/full_repos/permissive/43638243/spi_slave_simpler.v
1: b'%Warning-WIDTH: data/full_repos/permissive/43638243/spi_slave_simpler.v:38: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                          : ... In instance spi_slave_simpler\n     if (shift_count == 1\'b0) begin\n                     ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module spi_slave_simpler(clk, cs, mosi, miso, sck, done, din, dout);
	parameter bc=8;
	
	input clk;
	input cs;
	input mosi;
	output reg miso;
	input sck;
	output reg done;
	input [bc-1:0] din;
	output reg [bc-1:0] dout;
	
	reg [bc-1:0] shift_reg;
	reg prev_cs, prev_sck;
	reg [3:0]shift_count;
	


	always @(*) begin
		if (~cs) begin

			miso = shift_reg[bc-1];
		end
	end

	always @(posedge clk) begin
		if (~cs) begin
			if (prev_cs) begin

				done <= 0;
				shift_reg[bc-1:0] <= din[bc-1:0];
				shift_count <= bc;
			end
			if (~done && sck && ~prev_sck) begin

					shift_reg[bc-1:0] <= {shift_reg[bc-2:0], mosi};
					shift_count <= shift_count - 1'b1;
					if (shift_count == 1'b0) begin
						dout <= shift_reg;
						done <= 1;
					end
			end
		end else begin
			done <= 1;
		end
		prev_cs <= cs;
		prev_sck <= sck;
	end
endmodule
module spi_slave_simpler(clk, cs, mosi, miso, sck, done, din, dout);

	parameter bc=8;
	
	input clk;
	input cs;
	input mosi;
	output reg miso;
	input sck;
	output reg done;
	input [bc-1:0] din;
	output reg [bc-1:0] dout;
	
	reg [bc-1:0] shift_reg;
	reg prev_cs, prev_sck;
	reg [3:0]shift_count;
	


	always @(*) begin
		if (~cs) begin

			miso = shift_reg[bc-1];
		end
	end

	always @(posedge clk) begin
		if (~cs) begin
			if (prev_cs) begin

				done <= 0;
				shift_reg[bc-1:0] <= din[bc-1:0];
				shift_count <= bc;
			end
			if (~done && sck && ~prev_sck) begin

					shift_reg[bc-1:0] <= {shift_reg[bc-2:0], mosi};
					shift_count <= shift_count - 1'b1;
					if (shift_count == 1'b0) begin
						dout <= shift_reg;
						done <= 1;
					end
			end
		end else begin
			done <= 1;
		end
		prev_cs <= cs;
		prev_sck <= sck;
	end
endmodule