data/full_repos/permissive/500396778/3-Bit-Synchronous-Up-Down-Counter/Up.v
data/verilator_xmls/459ae218-bb26-4ae7-a4df-789f645db6b0.xml
module invert (input wire i, output wire o);
   assign o = !i;
endmodule
module invert (input wire i, output wire o);

   assign o = !i;
endmodule