data/full_repos/permissive/520428138/verilog/rtl/user_module_340218629792465491.v
1: b"%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_340218629792465491.v:28: Cannot find file containing module: 'and_cell'\n  and_cell gate1 (\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/520428138/verilog/rtl,data/full_repos/permissive/520428138/and_cell\n             data/full_repos/permissive/520428138/verilog/rtl,data/full_repos/permissive/520428138/and_cell.v\n             data/full_repos/permissive/520428138/verilog/rtl,data/full_repos/permissive/520428138/and_cell.sv\n             and_cell\n             and_cell.v\n             and_cell.sv\n             obj_dir/and_cell\n             obj_dir/and_cell.v\n             obj_dir/and_cell.sv\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_340218629792465491.v:31: Cannot find file containing module: 'or_cell'\n  or_cell gate2 (\n  ^~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_340218629792465491.v:34: Cannot find file containing module: 'xor_cell'\n  xor_cell gate3 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_340218629792465491.v:37: Cannot find file containing module: 'nand_cell'\n  nand_cell gate4 (\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_340218629792465491.v:40: Cannot find file containing module: 'not_cell'\n  not_cell gate5 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_340218629792465491.v:43: Cannot find file containing module: 'buffer_cell'\n  buffer_cell gate6 (\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_340218629792465491.v:46: Cannot find file containing module: 'mux_cell'\n  mux_cell mux1 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_340218629792465491.v:49: Cannot find file containing module: 'dff_cell'\n  dff_cell flipflop1 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_340218629792465491.v:52: Cannot find file containing module: 'dff_cell'\n  dff_cell flipflop2 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_340218629792465491.v:57: Cannot find file containing module: 'dff_cell'\n  dff_cell flipflop3 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_340218629792465491.v:62: Cannot find file containing module: 'dff_cell'\n  dff_cell flipflop4 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_340218629792465491.v:67: Cannot find file containing module: 'dff_cell'\n  dff_cell flipflop5 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_340218629792465491.v:72: Cannot find file containing module: 'dff_cell'\n  dff_cell flipflop6 (\n  ^~~~~~~~\n%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_340218629792465491.v:77: Cannot find file containing module: 'dff_cell'\n  dff_cell flipflop7 (\n  ^~~~~~~~\n%Error: Exiting due to 14 error(s)\n"
module user_module_340218629792465491(
  input [7:0] io_in,
  output [7:0] io_out
);
  wire net1 = io_in[0];
  wire net2;
  wire net3;
  wire net4;
  wire net5;
  wire net6;
  wire net7;
  wire net8 = 1'b0;
  wire net9 = 1'b1;
  wire net10 = 1'b1;
  wire net11;

  assign io_out[0] = net2;
  assign io_out[1] = net3;
  assign io_out[2] = net4;
  assign io_out[3] = net5;
  assign io_out[4] = net6;
  assign io_out[5] = net7;

  and_cell gate1 (

  );
  or_cell gate2 (

  );
  xor_cell gate3 (

  );
  nand_cell gate4 (

  );
  not_cell gate5 (

  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (

  );
  dff_cell flipflop1 (

  );
  dff_cell flipflop2 (
    .d (net11),
    .clk (net1),
    .q (net2)
  );
  dff_cell flipflop3 (
    .d (net2),
    .clk (net1),
    .q (net3)
  );
  dff_cell flipflop4 (
    .d (net3),
    .clk (net1),
    .q (net4)
  );
  dff_cell flipflop5 (
    .d (net4),
    .clk (net1),
    .q (net5)
  );
  dff_cell flipflop6 (
    .d (net5),
    .clk (net1),
    .q (net6)
  );
  dff_cell flipflop7 (
    .d (net6),
    .clk (net1),
    .q (net7),
    .notq (net11)
  );
endmodule
module user_module_340218629792465491(
  input [7:0] io_in,
  output [7:0] io_out
);

  wire net1 = io_in[0];
  wire net2;
  wire net3;
  wire net4;
  wire net5;
  wire net6;
  wire net7;
  wire net8 = 1'b0;
  wire net9 = 1'b1;
  wire net10 = 1'b1;
  wire net11;

  assign io_out[0] = net2;
  assign io_out[1] = net3;
  assign io_out[2] = net4;
  assign io_out[3] = net5;
  assign io_out[4] = net6;
  assign io_out[5] = net7;

  and_cell gate1 (

  );
  or_cell gate2 (

  );
  xor_cell gate3 (

  );
  nand_cell gate4 (

  );
  not_cell gate5 (

  );
  buffer_cell gate6 (

  );
  mux_cell mux1 (

  );
  dff_cell flipflop1 (

  );
  dff_cell flipflop2 (
    .d (net11),
    .clk (net1),
    .q (net2)
  );
  dff_cell flipflop3 (
    .d (net2),
    .clk (net1),
    .q (net3)
  );
  dff_cell flipflop4 (
    .d (net3),
    .clk (net1),
    .q (net4)
  );
  dff_cell flipflop5 (
    .d (net4),
    .clk (net1),
    .q (net5)
  );
  dff_cell flipflop6 (
    .d (net5),
    .clk (net1),
    .q (net6)
  );
  dff_cell flipflop7 (
    .d (net6),
    .clk (net1),
    .q (net7),
    .notq (net11)
  );
endmodule