data/full_repos/permissive/464047355/board/terasic_de0cv/rtl/serializer.sv
1: b"%Error: data/full_repos/permissive/464047355/board/terasic_de0cv/rtl/serializer.sv:42: Cannot find file containing module: 'stx'\n    stx stx0(\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/464047355/board/terasic_de0cv/rtl,data/full_repos/permissive/464047355/stx\n             data/full_repos/permissive/464047355/board/terasic_de0cv/rtl,data/full_repos/permissive/464047355/stx.v\n             data/full_repos/permissive/464047355/board/terasic_de0cv/rtl,data/full_repos/permissive/464047355/stx.sv\n             stx\n             stx.v\n             stx.sv\n             obj_dir/stx\n             obj_dir/stx.v\n             obj_dir/stx.sv\n%Error: Exiting due to 1 error(s)\n"
module serializer
(
    input logic clk_pixel,
    input logic clk_pixel_x5,
    input logic reset,
    input logic [9:0] tmds_internal [2:0],
    output logic [2:0] tmds,
    output logic tmds_clock
);

    logic [9:0] tmds_reversed [2:0];
    logic buf_loaden;
    logic buf_lvdsclk;



    genvar i, j;
    generate
        for (i = 0; i < 3; i++)
        begin: tmds_rev
            for (j = 0; j < 10; j++)
            begin: tmds_rev_channel
                assign tmds_reversed[i][j] = tmds_internal[i][9-j];
            end
        end
    endgenerate





    stx stx0(
        .pll_areset     (reset),
	    .tx_in          ({10'b1111100000, tmds_reversed[2], tmds_reversed[1], tmds_reversed[0]}),
	    .tx_inclock     (clk_pixel),
	    .tx_out         ({tmds_clock, tmds[2], tmds[1], tmds[0]})
    );

endmodule
module serializer
(
    input logic clk_pixel,
    input logic clk_pixel_x5,
    input logic reset,
    input logic [9:0] tmds_internal [2:0],
    output logic [2:0] tmds,
    output logic tmds_clock
);


    logic [9:0] tmds_reversed [2:0];
    logic buf_loaden;
    logic buf_lvdsclk;



    genvar i, j;
    generate
        for (i = 0; i < 3; i++)
        begin: tmds_rev
            for (j = 0; j < 10; j++)
            begin: tmds_rev_channel
                assign tmds_reversed[i][j] = tmds_internal[i][9-j];
            end
        end
    endgenerate





    stx stx0(
        .pll_areset     (reset),
	    .tx_in          ({10'b1111100000, tmds_reversed[2], tmds_reversed[1], tmds_reversed[0]}),
	    .tx_inclock     (clk_pixel),
	    .tx_out         ({tmds_clock, tmds[2], tmds[1], tmds[0]})
    );

endmodule