data/full_repos/permissive/456468799/Verilog/VideoBuffer.v
data/verilator_xmls/e1e1f743-b8b1-4db4-a17a-3518eaaa07ed.xml
module VideoBuffer(input DISPEN,
                   input S3,
                   input CAS_n_in,
                   input[7 : 0] D,
                   output reg[7 : 0] VIDEO_BUF,
                   output reg DISPEN_BUF);
  wire clk = S3 | CAS_n_in;
  always
    @(posedge clk)
      begin
        DISPEN_BUF <= DISPEN;
        VIDEO_BUF <= D;
      end
endmodule
module VideoBuffer(input DISPEN,
                   input S3,
                   input CAS_n_in,
                   input[7 : 0] D,
                   output reg[7 : 0] VIDEO_BUF,
                   output reg DISPEN_BUF);

  wire clk = S3 | CAS_n_in;
  always
    @(posedge clk)
      begin
        DISPEN_BUF <= DISPEN;
        VIDEO_BUF <= D;
      end
endmodule