data/full_repos/permissive/426864978/lab2/task4/tb_rtl_task4.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task4/tb_rtl_task4.sv:18: Unsupported: Ignoring delay on this delayed statement.\n        forever #5 CLOCK_50 = ~CLOCK_50;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task4/tb_rtl_task4.sv:58: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task4/tb_rtl_task4.sv:67: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task4/tb_rtl_task4.sv:76: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task4/tb_rtl_task4.sv:92: Unsupported: Ignoring delay on this delayed statement.\n                #10;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task4/tb_rtl_task4.sv:98: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab2/task4/tb_rtl_task4.sv:106: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/426864978/lab2/task4/tb_rtl_task4.sv:114: Unsupported: wait statements\n        wait (tb_rtl_task4.dut.done_draw === 1\'b1);\n        ^~~~\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_rtl_task4();


    logic CLOCK_50, VGA_HS, VGA_VS, VGA_CLK, VGA_PLOT, err;
    logic [3:0] KEY;
    logic [9:0] SW, LEDR;
    logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, VGA_Y;
    logic [7:0] VGA_R, VGA_G, VGA_B, VGA_X;
    logic [2:0] VGA_COLOUR;
    integer i, j;

    task4 dut(.*);

    initial begin
        CLOCK_50 = 0;
        forever #5 CLOCK_50 = ~CLOCK_50;
    end

    task validator;
        input [7:0] exp_x;
        input [6:0] exp_y;
        input [2:0] exp_colour;
        input exp_done_fill, exp_plot;
        begin
            if (tb_rtl_task4.dut.VGA_X !== exp_x) begin
                $display("ERROR A: Expected VGA_X is %d, actual VGA_X is %d at x =%d, y =%d", exp_x, tb_rtl_task4.dut.VGA_X, i, j);
                err = 1'b1;
            end
            if (tb_rtl_task4.dut.VGA_Y !== exp_y) begin
                $display("ERROR B: Expected VGA_Y is %d, actual VGA_Y is %d at x =%d, y =%d", exp_y, tb_rtl_task4.dut.VGA_Y, i, j);
                err = 1'b1;
            end
            if (tb_rtl_task4.dut.VGA_COLOUR !== exp_colour) begin
                $display("ERROR C: Expected VGA_COLOUR is %d, actual VGA_COLOUR is %d at x =%d, y =%d", exp_colour, tb_rtl_task4.dut.VGA_COLOUR, i, j);
                err = 1'b1;
            end
            if (tb_rtl_task4.dut.done_fill !== exp_done_fill) begin
                $display("ERROR D: Expected done_fill is %b, actual done_fill is %b at x =%d, y =%d", exp_done_fill, tb_rtl_task4.dut.done_fill, i, j);
                err = 1'b1;
            end
            if (tb_rtl_task4.dut.VGA_PLOT !== exp_plot) begin
                $display("ERROR E: Expected VGA_PLOT is %b, actual VGA_PLOT is %b at x =%d, y =%d", exp_plot, tb_rtl_task4.dut.VGA_PLOT, i, j);
                err = 1'b1;
            end
        end
    endtask

    `define BLACK    3'b000
    `define GREEN    3'b010

    initial begin
        err = 1'b0;


        KEY[3] = 1'bx;
        #10;
        validator(8'b0, 7'b0, 3'b0, 1'b0, 1'b0);
        if (tb_rtl_task4.dut.start_fill !== 1'b1) begin
            $display("ERROR 1: Expected start_fill is %b, actual start_fill is %b", 1'b1, tb_rtl_task4.dut.start_fill);
            err = 1'b1;
        end


        KEY[3] = 1'b0;
        #10;
        validator(8'b0, 7'b0, 3'b0, 1'b0, 1'b0);
        if (tb_rtl_task4.dut.start_fill !== 1'b1) begin
            $display("ERROR 2: Expected start_fill is %b, actual start_fill is %b", 1'b1, tb_rtl_task4.dut.start_fill);
            err = 1'b1;
        end


        KEY[3] = 1'b1;
        #10;
        validator(8'b0, 7'b0, 3'b0, 1'b0, 1'b1);
        if (tb_rtl_task4.dut.start_fill !== 1'b1) begin
            $display("ERROR 3: Expected start_fill is %b, actual start_fill is %b", 1'b1, tb_rtl_task4.dut.start_fill);
            err = 1'b1;
        end


        if (tb_rtl_task4.dut.start_draw !== 1'b0) begin
            $display("ERROR 4: Expected start_draw is %b, actual start_draw is %b", 1'b0, tb_rtl_task4.dut.start_draw);
            err = 1'b1;
        end

        for (i = 0; i < 160; i = i + 1) begin
            for (j = 0; j < 120; j = j + 1) begin
                validator(i, j, `BLACK, 1'b0, 1'b1);
                #10;
            end
        end



        #10;
        validator(8'd0, 7'd0, `GREEN, 1'b1, 1'b0);
        if (tb_rtl_task4.dut.start_draw !== 1'b1) begin
            $display("ERROR 5: Expected start_draw is %b, actual start_draw is %b", 1'b1, tb_rtl_task4.dut.start_draw);
            err = 1'b1;
        end


        #10;
        validator(8'd0, 7'd0, `GREEN, 1'b1, 1'b0);
        if (tb_rtl_task4.dut.done_draw !== 1'b0) begin
            $display("ERROR 6: Expected done_draw is %b, actual done_draw is %b", 1'b0, tb_rtl_task4.dut.done_draw);
            err = 1'b1;
        end


        wait (tb_rtl_task4.dut.done_draw === 1'b1);
        validator(8'd0, 7'd0, `GREEN, 1'b1, 1'b0);

        if (~err) begin
            $display("SUCCESS: All tests passed.");
        end
        $stop;
    end

endmodule
module tb_rtl_task4();



    logic CLOCK_50, VGA_HS, VGA_VS, VGA_CLK, VGA_PLOT, err;
    logic [3:0] KEY;
    logic [9:0] SW, LEDR;
    logic [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, VGA_Y;
    logic [7:0] VGA_R, VGA_G, VGA_B, VGA_X;
    logic [2:0] VGA_COLOUR;
    integer i, j;

    task4 dut(.*);

    initial begin
        CLOCK_50 = 0;
        forever #5 CLOCK_50 = ~CLOCK_50;
    end

    task validator;
        input [7:0] exp_x;
        input [6:0] exp_y;
        input [2:0] exp_colour;
        input exp_done_fill, exp_plot;
        begin
            if (tb_rtl_task4.dut.VGA_X !== exp_x) begin
                $display("ERROR A: Expected VGA_X is %d, actual VGA_X is %d at x =%d, y =%d", exp_x, tb_rtl_task4.dut.VGA_X, i, j);
                err = 1'b1;
            end
            if (tb_rtl_task4.dut.VGA_Y !== exp_y) begin
                $display("ERROR B: Expected VGA_Y is %d, actual VGA_Y is %d at x =%d, y =%d", exp_y, tb_rtl_task4.dut.VGA_Y, i, j);
                err = 1'b1;
            end
            if (tb_rtl_task4.dut.VGA_COLOUR !== exp_colour) begin
                $display("ERROR C: Expected VGA_COLOUR is %d, actual VGA_COLOUR is %d at x =%d, y =%d", exp_colour, tb_rtl_task4.dut.VGA_COLOUR, i, j);
                err = 1'b1;
            end
            if (tb_rtl_task4.dut.done_fill !== exp_done_fill) begin
                $display("ERROR D: Expected done_fill is %b, actual done_fill is %b at x =%d, y =%d", exp_done_fill, tb_rtl_task4.dut.done_fill, i, j);
                err = 1'b1;
            end
            if (tb_rtl_task4.dut.VGA_PLOT !== exp_plot) begin
                $display("ERROR E: Expected VGA_PLOT is %b, actual VGA_PLOT is %b at x =%d, y =%d", exp_plot, tb_rtl_task4.dut.VGA_PLOT, i, j);
                err = 1'b1;
            end
        end
    endtask

    `define BLACK    3'b000
    `define GREEN    3'b010

    initial begin
        err = 1'b0;


        KEY[3] = 1'bx;
        #10;
        validator(8'b0, 7'b0, 3'b0, 1'b0, 1'b0);
        if (tb_rtl_task4.dut.start_fill !== 1'b1) begin
            $display("ERROR 1: Expected start_fill is %b, actual start_fill is %b", 1'b1, tb_rtl_task4.dut.start_fill);
            err = 1'b1;
        end


        KEY[3] = 1'b0;
        #10;
        validator(8'b0, 7'b0, 3'b0, 1'b0, 1'b0);
        if (tb_rtl_task4.dut.start_fill !== 1'b1) begin
            $display("ERROR 2: Expected start_fill is %b, actual start_fill is %b", 1'b1, tb_rtl_task4.dut.start_fill);
            err = 1'b1;
        end


        KEY[3] = 1'b1;
        #10;
        validator(8'b0, 7'b0, 3'b0, 1'b0, 1'b1);
        if (tb_rtl_task4.dut.start_fill !== 1'b1) begin
            $display("ERROR 3: Expected start_fill is %b, actual start_fill is %b", 1'b1, tb_rtl_task4.dut.start_fill);
            err = 1'b1;
        end


        if (tb_rtl_task4.dut.start_draw !== 1'b0) begin
            $display("ERROR 4: Expected start_draw is %b, actual start_draw is %b", 1'b0, tb_rtl_task4.dut.start_draw);
            err = 1'b1;
        end

        for (i = 0; i < 160; i = i + 1) begin
            for (j = 0; j < 120; j = j + 1) begin
                validator(i, j, `BLACK, 1'b0, 1'b1);
                #10;
            end
        end



        #10;
        validator(8'd0, 7'd0, `GREEN, 1'b1, 1'b0);
        if (tb_rtl_task4.dut.start_draw !== 1'b1) begin
            $display("ERROR 5: Expected start_draw is %b, actual start_draw is %b", 1'b1, tb_rtl_task4.dut.start_draw);
            err = 1'b1;
        end


        #10;
        validator(8'd0, 7'd0, `GREEN, 1'b1, 1'b0);
        if (tb_rtl_task4.dut.done_draw !== 1'b0) begin
            $display("ERROR 6: Expected done_draw is %b, actual done_draw is %b", 1'b0, tb_rtl_task4.dut.done_draw);
            err = 1'b1;
        end


        wait (tb_rtl_task4.dut.done_draw === 1'b1);
        validator(8'd0, 7'd0, `GREEN, 1'b1, 1'b0);

        if (~err) begin
            $display("SUCCESS: All tests passed.");
        end
        $stop;
    end

endmodule