data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/ALU.v
1: b'%Warning-WIDTH: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/ALU.v:30: Operator SUB expects 8 bits on the LHS, but LHS\'s VARREF \'opb\' generates 4 bits.\n                                                                                    : ... In instance ALU\n                    ropc <= opb-opa;\n                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/ALU.v:30: Operator SUB expects 8 bits on the RHS, but RHS\'s VARREF \'opa\' generates 4 bits.\n                                                                                    : ... In instance ALU\n                    ropc <= opb-opa;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/ALU.v:35: Operator SUB expects 8 bits on the LHS, but LHS\'s VARREF \'opa\' generates 4 bits.\n                                                                                    : ... In instance ALU\n                    ropc <= opa-opb;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/ALU.v:35: Operator SUB expects 8 bits on the RHS, but RHS\'s VARREF \'opb\' generates 4 bits.\n                                                                                    : ... In instance ALU\n                    ropc <= opa-opb;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/ALU.v:48: Operator SUB expects 8 bits on the LHS, but LHS\'s VARREF \'opb\' generates 4 bits.\n                                                                                    : ... In instance ALU\n                    ropc <= opb-opa;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/ALU.v:48: Operator SUB expects 8 bits on the RHS, but RHS\'s VARREF \'opa\' generates 4 bits.\n                                                                                    : ... In instance ALU\n                    ropc <= opb-opa;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/ALU.v:53: Operator SUB expects 8 bits on the LHS, but LHS\'s VARREF \'opa\' generates 4 bits.\n                                                                                    : ... In instance ALU\n                    ropc <= opa-opb;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/ALU.v:53: Operator SUB expects 8 bits on the RHS, but RHS\'s VARREF \'opb\' generates 4 bits.\n                                                                                    : ... In instance ALU\n                    ropc <= opa-opb;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/ALU.v:64: Operator ADD expects 8 bits on the LHS, but LHS\'s VARREF \'opa\' generates 4 bits.\n                                                                                    : ... In instance ALU\n                ropc <=opa+opb;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/ALU.v:64: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'opb\' generates 4 bits.\n                                                                                    : ... In instance ALU\n                ropc <=opa+opb;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/ALU.v:69: Operator ADD expects 8 bits on the LHS, but LHS\'s VARREF \'opa\' generates 4 bits.\n                                                                                    : ... In instance ALU\n                ropc <=opa+opb;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/ALU.v:69: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'opb\' generates 4 bits.\n                                                                                    : ... In instance ALU\n                ropc <=opa+opb;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/ALU.v:80: Operator SUB expects 8 bits on the LHS, but LHS\'s VARREF \'opb\' generates 4 bits.\n                                                                                    : ... In instance ALU\n                    ropc <= opb-opa;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/ALU.v:80: Operator SUB expects 8 bits on the RHS, but RHS\'s VARREF \'opa\' generates 4 bits.\n                                                                                    : ... In instance ALU\n                    ropc <= opb-opa;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/ALU.v:85: Operator SUB expects 8 bits on the LHS, but LHS\'s VARREF \'opa\' generates 4 bits.\n                                                                                    : ... In instance ALU\n                    ropc <= opa-opb;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/ALU.v:85: Operator SUB expects 8 bits on the RHS, but RHS\'s VARREF \'opb\' generates 4 bits.\n                                                                                    : ... In instance ALU\n                    ropc <= opa-opb;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/ALU.v:98: Operator SUB expects 8 bits on the LHS, but LHS\'s VARREF \'opb\' generates 4 bits.\n                                                                                    : ... In instance ALU\n                    ropc <= opb-opa;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/ALU.v:98: Operator SUB expects 8 bits on the RHS, but RHS\'s VARREF \'opa\' generates 4 bits.\n                                                                                    : ... In instance ALU\n                    ropc <= opb-opa;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/ALU.v:103: Operator SUB expects 8 bits on the LHS, but LHS\'s VARREF \'opa\' generates 4 bits.\n                                                                                     : ... In instance ALU\n                    ropc <= opa-opb;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/ALU.v:103: Operator SUB expects 8 bits on the RHS, but RHS\'s VARREF \'opb\' generates 4 bits.\n                                                                                     : ... In instance ALU\n                    ropc <= opa-opb;\n                               ^\n%Warning-WIDTH: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/ALU.v:114: Operator ADD expects 8 bits on the LHS, but LHS\'s VARREF \'opa\' generates 4 bits.\n                                                                                     : ... In instance ALU\n                ropc <=opa+opb;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/ALU.v:114: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'opb\' generates 4 bits.\n                                                                                     : ... In instance ALU\n                ropc <=opa+opb;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/ALU.v:119: Operator ADD expects 8 bits on the LHS, but LHS\'s VARREF \'opa\' generates 4 bits.\n                                                                                     : ... In instance ALU\n                ropc <=opa+opb;\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/502135797/Lab7_April_6_2022/Code/ALU.v:119: Operator ADD expects 8 bits on the RHS, but RHS\'s VARREF \'opb\' generates 4 bits.\n                                                                                     : ... In instance ALU\n                ropc <=opa+opb;\n                          ^\n%Error: Exiting due to 24 warning(s)\n'
module ALU(
    input [3:0] opa,
    input [3:0] opb,
    input signa,
    input signb,
    input [1:0] asm,
    output [7:0] opc,
    output signc1
    );
    reg [7:0] ropc=0;
    reg signc=0;
    always@(*)
    begin
    case(asm)
            2'b00: 
            begin
            ropc <= 0;
            signc <=0;
            end
            
            2'b01:
            begin
                if(signa==0 && signb==1)
                begin
                    if(opa<opb)
                    begin
                    ropc <= opb-opa;
                    signc <=1;
                    end
                   else if(opa>opb)
                    begin
                    ropc <= opa-opb;
                    signc <=0;
                    end
                    else
                    begin
                    ropc <=0;
                    signc <=0;
                    end
                end
               else if(signa==1 && signb==0)
                begin
                    if(opa<opb)
                    begin
                    ropc <= opb-opa;
                    signc <=0;
                    end
                   else if(opa>opb)
                    begin
                    ropc <= opa-opb;
                    signc <=1;
                    end
                    else
                    begin
                    ropc <=0;
                    signc <=0;
                    end
                end
                else if(signa==1 && signb==1)
                begin
                ropc <=opa+opb;
                signc <=1;                
                end
                else 
                begin
                ropc <=opa+opb;
                signc <=0;                
                end
            end 
            
            2'b10:
            begin
                if(signa==0 && signb==0)
                begin
                    if(opa<opb)
                    begin
                    ropc <= opb-opa;
                    signc <=1;
                    end
                   else if(opa>opb)
                    begin
                    ropc <= opa-opb;
                    signc <=0;
                    end
                    else
                    begin
                    ropc <=0;
                    signc <=0;
                    end
                end
               else if(signa==1 && signb==1)
                begin
                    if(opa<opb)
                    begin
                    ropc <= opb-opa;
                    signc <=0;
                    end
                   else if(opa>opb)
                    begin
                    ropc <= opa-opb;
                    signc <=1;
                    end
                    else
                    begin
                    ropc <=0;
                    signc <=0;
                    end
                end
                else if(signa==1 && signb==0)
                begin
                ropc <=opa+opb;
                signc <=1;                
                end
                else 
                begin
                ropc <=opa+opb;
                signc <=0;                
                end
            end 
            
            2'b11:
            begin
             ropc = opa * opb;
                if(signa==1 || signb==1)
                    signc <= 1;
                else if(signa==0 && signb==0)
                    signc <= 0;
                else
                    signc <= 0;
            
            end 
           
        endcase
   end 
   assign opc = ropc;
   assign signc1 = signc;
endmodule
module ALU(
    input [3:0] opa,
    input [3:0] opb,
    input signa,
    input signb,
    input [1:0] asm,
    output [7:0] opc,
    output signc1
    );

    reg [7:0] ropc=0;
    reg signc=0;
    always@(*)
    begin
    case(asm)
            2'b00: 
            begin
            ropc <= 0;
            signc <=0;
            end
            
            2'b01:
            begin
                if(signa==0 && signb==1)
                begin
                    if(opa<opb)
                    begin
                    ropc <= opb-opa;
                    signc <=1;
                    end
                   else if(opa>opb)
                    begin
                    ropc <= opa-opb;
                    signc <=0;
                    end
                    else
                    begin
                    ropc <=0;
                    signc <=0;
                    end
                end
               else if(signa==1 && signb==0)
                begin
                    if(opa<opb)
                    begin
                    ropc <= opb-opa;
                    signc <=0;
                    end
                   else if(opa>opb)
                    begin
                    ropc <= opa-opb;
                    signc <=1;
                    end
                    else
                    begin
                    ropc <=0;
                    signc <=0;
                    end
                end
                else if(signa==1 && signb==1)
                begin
                ropc <=opa+opb;
                signc <=1;                
                end
                else 
                begin
                ropc <=opa+opb;
                signc <=0;                
                end
            end 
            
            2'b10:
            begin
                if(signa==0 && signb==0)
                begin
                    if(opa<opb)
                    begin
                    ropc <= opb-opa;
                    signc <=1;
                    end
                   else if(opa>opb)
                    begin
                    ropc <= opa-opb;
                    signc <=0;
                    end
                    else
                    begin
                    ropc <=0;
                    signc <=0;
                    end
                end
               else if(signa==1 && signb==1)
                begin
                    if(opa<opb)
                    begin
                    ropc <= opb-opa;
                    signc <=0;
                    end
                   else if(opa>opb)
                    begin
                    ropc <= opa-opb;
                    signc <=1;
                    end
                    else
                    begin
                    ropc <=0;
                    signc <=0;
                    end
                end
                else if(signa==1 && signb==0)
                begin
                ropc <=opa+opb;
                signc <=1;                
                end
                else 
                begin
                ropc <=opa+opb;
                signc <=0;                
                end
            end 
            
            2'b11:
            begin
             ropc = opa * opb;
                if(signa==1 || signb==1)
                    signc <= 1;
                else if(signa==0 && signb==0)
                    signc <= 0;
                else
                    signc <= 0;
            
            end 
           
        endcase
   end 
   assign opc = ropc;
   assign signc1 = signc;
endmodule