data/full_repos/permissive/435890256/test_operator/tb_test.sv
1: b'%Error: data/full_repos/permissive/435890256/test_operator/tb_test.sv:2: Cannot find include file: test.sv\n`include "test.sv" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/435890256/test_operator,data/full_repos/permissive/435890256/test.sv\n             data/full_repos/permissive/435890256/test_operator,data/full_repos/permissive/435890256/test.sv.v\n             data/full_repos/permissive/435890256/test_operator,data/full_repos/permissive/435890256/test.sv.sv\n             test.sv\n             test.sv.v\n             test.sv.sv\n             obj_dir/test.sv\n             obj_dir/test.sv.v\n             obj_dir/test.sv.sv\n%Error: data/full_repos/permissive/435890256/test_operator/tb_test.sv:5: Unsupported or unknown PLI call: $timeformat\n initial $timeformat(-9,1," ns",9);\n         ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/435890256/test_operator/tb_test.sv:40: Unsupported: Ignoring delay on this delayed statement.\n  #20;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/435890256/test_operator/tb_test.sv:41: Unsupported: Ignoring delay on this delayed statement.\n  forever #20 clk = ! clk;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/435890256/test_operator/tb_test.sv:58: Unsupported: Ignoring delay on this delayed statement.\n      #5;\n      ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n'
module tb_test;

  logic clk;
  logic [31:0] a;
  logic [31:0] b;
  logic [4:0] shamt;

  int counter_finish;

  test DUT(.a(a),.shamt(shamt),.b(b));

  logic        [9:0] c;
  logic signed [9:0] d;
  logic signed [9:0] a_signed;
  logic        [9:0] a_unsigned;

  initial begin
    c = 10'b11_0101_0101;
    d = c;
    a_unsigned   = d >>> 2;



  end

  initial begin
    clk = 1'b0;
    a = 32'b0;
    shamt = 4'b0;
  end

  initial begin
		#20;
		forever #20 clk = ! clk;
	end
  

  always@(posedge clk) begin
		counter_finish = counter_finish + 1;
		
		if(counter_finish == 30) $finish;
	end

  always @(posedge clk) begin
    a = 32'b01000000_00000000_00000000_00000000;
    shamt = counter_finish;
  end
  
  always @(posedge clk) begin
    if (shamt > 1) begin
      #5;
      $display("%d >>> %d = %d\n",a,shamt,b);

    end
  end
endmodule
module tb_test;


  logic clk;
  logic [31:0] a;
  logic [31:0] b;
  logic [4:0] shamt;

  int counter_finish;

  test DUT(.a(a),.shamt(shamt),.b(b));

  logic        [9:0] c;
  logic signed [9:0] d;
  logic signed [9:0] a_signed;
  logic        [9:0] a_unsigned;

  initial begin
    c = 10'b11_0101_0101;
    d = c;
    a_unsigned   = d >>> 2;



  end

  initial begin
    clk = 1'b0;
    a = 32'b0;
    shamt = 4'b0;
  end

  initial begin
		#20;
		forever #20 clk = ! clk;
	end
  

  always@(posedge clk) begin
		counter_finish = counter_finish + 1;
		
		if(counter_finish == 30) $finish;
	end

  always @(posedge clk) begin
    a = 32'b01000000_00000000_00000000_00000000;
    shamt = counter_finish;
  end
  
  always @(posedge clk) begin
    if (shamt > 1) begin
      #5;
      $display("%d >>> %d = %d\n",a,shamt,b);

    end
  end
endmodule