data/full_repos/permissive/43856783/crc_7/peripheral_crc_7.v
1: b'%Warning-WIDTH: data/full_repos/permissive/43856783/crc_7/peripheral_crc_7.v:51: Operator COND expects 17 bits on the Conditional True, but Conditional True\'s VARREF \'d_in\' generates 16 bits.\n                                                                               : ... In instance peripheral_crc_7\n  data_in = (s[0]) ? d_in : data_in;  \n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/43856783/crc_7/peripheral_crc_7.v:70: Cannot find file containing module: \'crc_7\'\n crc_7 c_7 ( .clk(clk), .rst(rst), .data_in(data_in), .start(start), .data_out(data_out), .done(done) );  \n ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/43856783/crc_7,data/full_repos/permissive/43856783/crc_7\n             data/full_repos/permissive/43856783/crc_7,data/full_repos/permissive/43856783/crc_7.v\n             data/full_repos/permissive/43856783/crc_7,data/full_repos/permissive/43856783/crc_7.sv\n             crc_7\n             crc_7.v\n             crc_7.sv\n             obj_dir/crc_7\n             obj_dir/crc_7.v\n             obj_dir/crc_7.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module peripheral_crc_7(clk , rst , d_in , cs , addr , rd , wr, d_out );
  	

	  input clk;
	  input rst;
	  input [15:0]d_in;
	  input cs;
	  input [3:0]addr;
	  input rd;
	  input wr;
	  output reg [15:0]d_out;





	reg [3:0] s;
	
	reg [16:0] data_in=0;
	reg start=0;

	wire [6:0] data_out;
	wire done;







	always @(*) begin
		case (addr)


			4'h0:begin s = (cs && wr) ? 4'b0001 : 4'b0000 ;end
			4'h2:begin s = (cs && wr) ? 4'b0010 : 4'b0000 ;end


			4'h4:begin s = (cs && rd) ? 4'b0100 : 4'b0000 ;end
			4'h6:begin s = (cs && rd) ? 4'b1000 : 4'b0000 ;end

			default:begin s = 4'b0000 ; end
		endcase
	end




	always @(negedge clk) begin

		data_in = (s[0]) ? d_in : data_in;
		start = s[1];
	

	end




	always @(negedge clk) begin
		case (s[3:2])
			2'b01: d_out[0] = done ;
			2'b10: d_out[6:0]  = data_out ;
			default: d_out   = 0 ;
		endcase
	end



	crc_7 c_7 ( .clk(clk), .rst(rst), .data_in(data_in), .start(start), .data_out(data_out), .done(done) );


endmodule
module peripheral_crc_7(clk , rst , d_in , cs , addr , rd , wr, d_out );

  	

	  input clk;
	  input rst;
	  input [15:0]d_in;
	  input cs;
	  input [3:0]addr;
	  input rd;
	  input wr;
	  output reg [15:0]d_out;





	reg [3:0] s;
	
	reg [16:0] data_in=0;
	reg start=0;

	wire [6:0] data_out;
	wire done;







	always @(*) begin
		case (addr)


			4'h0:begin s = (cs && wr) ? 4'b0001 : 4'b0000 ;end
			4'h2:begin s = (cs && wr) ? 4'b0010 : 4'b0000 ;end


			4'h4:begin s = (cs && rd) ? 4'b0100 : 4'b0000 ;end
			4'h6:begin s = (cs && rd) ? 4'b1000 : 4'b0000 ;end

			default:begin s = 4'b0000 ; end
		endcase
	end




	always @(negedge clk) begin

		data_in = (s[0]) ? d_in : data_in;
		start = s[1];
	

	end




	always @(negedge clk) begin
		case (s[3:2])
			2'b01: d_out[0] = done ;
			2'b10: d_out[6:0]  = data_out ;
			default: d_out   = 0 ;
		endcase
	end



	crc_7 c_7 ( .clk(clk), .rst(rst), .data_in(data_in), .start(start), .data_out(data_out), .done(done) );


endmodule