data/full_repos/permissive/454159683/mux4to1c/mux4to1c.v
data/verilator_xmls/0532e83c-5d5d-4858-88e6-524cc6d8545f.xml
module mux4to1c(input a, b, c, d, input [1:0] sel, output reg out);
	always @(sel)
	begin
		if (sel == 0)
			out = a;
		else if (sel == 1)
			out = b;
		else if (sel == 2)
			out = c;
		else
			out = d;
	end










endmodule
module mux4to1c(input a, b, c, d, input [1:0] sel, output reg out);

	always @(sel)
	begin
		if (sel == 0)
			out = a;
		else if (sel == 1)
			out = b;
		else if (sel == 2)
			out = c;
		else
			out = d;
	end










endmodule