data/full_repos/permissive/514992586/1_Verilog_language/More_Verilog_Features/38_Reduction.v
data/verilator_xmls/db556fc6-5a51-471a-a76c-3c437216534b.xml
module top_module (
    input [7:0] in,
    output parity); 

    assign parity = ^ in;
endmodule
module top_module (
    input [7:0] in,
    output parity);
 

    assign parity = ^ in;
endmodule