data/full_repos/permissive/427221126/src/BasicArith.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/427221126/src/BasicArith.v:89: Multiple top level modules\n                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                           : ... Top module \'MAC\'\nmodule MAC\n       ^~~\n                                                                           : ... Top module \'ComplexMult\'\nmodule ComplexMult \n       ^~~~~~~~~~~\n                                                                           : ... Top module \'FMA\'\nmodule FMA\n       ^~~\n                                                                           : ... Top module \'Acc\'\nmodule Acc\n       ^~~\n                                                                           : ... Top module \'FMApFRound\'\nmodule FMApFRound\n       ^~~~~~~~~~\n                                                                           : ... Top module \'Max4\'\nmodule Max4\n       ^~~~\n                                                                           : ... Top module \'Add3\'\nmodule Add3(clk, reset, en, a, d, c, y);\n       ^~~~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:357: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 24 bits.\n                                                                         : ... In instance FMApFRound.U_fmap\n      cin <= $signed({C, {EXT_WIDTH{1\'b0}}});  \n          ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:362: Operator ADD expects 33 bits on the LHS, but LHS\'s VARREF \'ain\' generates 16 bits.\n                                                                         : ... In instance FMApFRound.U_fmap\n  assign a_mul_b = (ain + din) * bin;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:362: Operator ADD expects 33 bits on the RHS, but RHS\'s VARREF \'din\' generates 16 bits.\n                                                                         : ... In instance FMApFRound.U_fmap\n  assign a_mul_b = (ain + din) * bin;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:357: Operator ASSIGNDLY expects 96 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 48 bits.\n                                                                         : ... In instance Add3.U_fmap\n      cin <= $signed({C, {EXT_WIDTH{1\'b0}}});  \n          ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:362: Operator ADD expects 97 bits on the LHS, but LHS\'s VARREF \'ain\' generates 48 bits.\n                                                                         : ... In instance Add3.U_fmap\n  assign a_mul_b = (ain + din) * bin;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:362: Operator ADD expects 97 bits on the RHS, but RHS\'s VARREF \'din\' generates 48 bits.\n                                                                         : ... In instance Add3.U_fmap\n  assign a_mul_b = (ain + din) * bin;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:555: Output port connection \'Y\' expects 97 bits on the pin connection, but pin connection\'s VARREF \'y\' generates 50 bits.\n                                                                         : ... In instance Add3\n  .Y(y)\n   ^\n%Error: data/full_repos/permissive/427221126/src/BasicArith.v:408: Cannot find file containing module: \'FRound\'\n  FRound #(\n  ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/FRound\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/FRound.v\n             data/full_repos/permissive/427221126/src,data/full_repos/permissive/427221126/FRound.sv\n             FRound\n             FRound.v\n             FRound.sv\n             obj_dir/FRound\n             obj_dir/FRound.v\n             obj_dir/FRound.sv\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:291: Operator ASSIGNDLY expects 47 bits on the Assign RHS, but Assign RHS\'s VARREF \'din_reg\' generates 16 bits.\n                                                                         : ... In instance Acc\n        sum <= din_reg;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:293: Operator ADD expects 47 bits on the RHS, but RHS\'s VARREF \'din_reg\' generates 16 bits.\n                                                                         : ... In instance Acc\n        sum <= sum + din_reg;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:225: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 29 bits.\n                                                                         : ... In instance FMA\n      cin <= $signed({C, {EXT_WIDTH{1\'b0}}});  \n          ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:76: Operator ASSIGNDLY expects 42 bits on the Assign RHS, but Assign RHS\'s VARREF \'mult\' generates 32 bits.\n                                                                        : ... In instance MAC\n        sum <= mult;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/427221126/src/BasicArith.v:78: Operator ADD expects 42 bits on the RHS, but RHS\'s VARREF \'mult\' generates 32 bits.\n                                                                        : ... In instance MAC\n        sum <= sum + mult;\n                   ^\n%Error: Exiting due to 1 error(s), 13 warning(s)\n'
module MAC
  #(
    parameter INWIDTH_A = 16,
              INWIDTH_B = 16,
              ACC_WIDTH = 42
  )
  (
    input                         CLK,
    input                         RESET,
    input                         EN,
    input                         CLEAR,
    input  signed [INWIDTH_A-1:0] A,
    input  signed [INWIDTH_B-1:0] B,
    output signed [ACC_WIDTH-1:0] ACC
  );

  reg signed [INWIDTH_A-1:0] ain;
  reg signed [INWIDTH_B-1:0] bin;
  reg signed [ACC_WIDTH-1:0] sum;
  reg signed [INWIDTH_A+INWIDTH_B-1:0] mult;
  
  reg clr_d;
  reg clr_n_dd;

  always @(posedge CLK) begin
    if (RESET) begin
      ain <= 0;
      bin <= 0;
      clr_d <= 0;
    end
    else if (EN) begin
      ain <= A;
      bin <= B;
      clr_d <= CLEAR;
    end
  end

  always @(posedge CLK) begin
    if (RESET) begin
      mult <= 0;
      clr_n_dd <= 0;
    end
    else if (EN) begin
      mult <= ain * bin;
      clr_n_dd <= ~clr_d;
    end
  end

  always @(posedge CLK) begin
    if (RESET)
      sum <= 0;
    else if (EN) 
      if (!clr_n_dd)
        sum <= mult;
      else
        sum <= sum + mult;
  end

  assign ACC = sum;
endmodule
module MAC
  #(
    parameter INWIDTH_A = 16,
              INWIDTH_B = 16,
              ACC_WIDTH = 42
  )
  (
    input                         CLK,
    input                         RESET,
    input                         EN,
    input                         CLEAR,
    input  signed [INWIDTH_A-1:0] A,
    input  signed [INWIDTH_B-1:0] B,
    output signed [ACC_WIDTH-1:0] ACC
  );


  reg signed [INWIDTH_A-1:0] ain;
  reg signed [INWIDTH_B-1:0] bin;
  reg signed [ACC_WIDTH-1:0] sum;
  reg signed [INWIDTH_A+INWIDTH_B-1:0] mult;
  
  reg clr_d;
  reg clr_n_dd;

  always @(posedge CLK) begin
    if (RESET) begin
      ain <= 0;
      bin <= 0;
      clr_d <= 0;
    end
    else if (EN) begin
      ain <= A;
      bin <= B;
      clr_d <= CLEAR;
    end
  end

  always @(posedge CLK) begin
    if (RESET) begin
      mult <= 0;
      clr_n_dd <= 0;
    end
    else if (EN) begin
      mult <= ain * bin;
      clr_n_dd <= ~clr_d;
    end
  end

  always @(posedge CLK) begin
    if (RESET)
      sum <= 0;
    else if (EN) 
      if (!clr_n_dd)
        sum <= mult;
      else
        sum <= sum + mult;
  end

  assign ACC = sum;
endmodule