data/full_repos/permissive/43858668/final_verilog/src/clib/c_rotate.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_rotate.v:35: Cannot find include file: c_functions.v\n`include "c_functions.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_functions.v.sv\n             c_functions.v\n             c_functions.v.v\n             c_functions.v.sv\n             obj_dir/c_functions.v\n             obj_dir/c_functions.v.v\n             obj_dir/c_functions.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_rotate.v:36: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_rotate.v:42: Define or directive not defined: \'`ROTATE_DIR_LEFT\'\n   parameter rotate_dir = `ROTATE_DIR_LEFT;\n                          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_rotate.v:42: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter rotate_dir = `ROTATE_DIR_LEFT;\n                                          ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_rotate.v:63: Define or directive not defined: \'`ROTATE_DIR_LEFT\'\n `ROTATE_DIR_LEFT:\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_rotate.v:63: syntax error, unexpected \':\', expecting endcase\n `ROTATE_DIR_LEFT:\n                 ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_rotate.v:68: syntax error, unexpected end\n   end\n   ^~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_rotate.v:69: Define or directive not defined: \'`ROTATE_DIR_RIGHT\'\n `ROTATE_DIR_RIGHT:\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_rotate.v:74: syntax error, unexpected end\n   end\n   ^~~\n%Error: Cannot continue\n'
module c_rotate
  (amount, data_in, data_out);
   
`include "c_functions.v"
`include "c_constants.v"
   

   parameter width = 8;
   

   parameter rotate_dir = `ROTATE_DIR_LEFT;
   

   localparam amount_width = clogb(width);
   

   input [0:width-1] data_in;
   

   input [0:amount_width-1] amount;
   

   output [0:width-1] data_out;
   wire [0:width-1] data_out;
   
   wire [0:(2*width-1)-1] data_dup;
   wire [0:(2*width-1)-1] data_rot;
   
   generate
      
      case (rotate_dir)
	`ROTATE_DIR_LEFT:
	  begin
	     assign data_dup = {data_in, data_in[0:(width-1)-1]};
	     assign data_rot = data_dup << amount;
	     assign data_out = data_rot[0:width-1];
	  end
	`ROTATE_DIR_RIGHT:
	  begin
	     assign data_dup = {data_in[1:width-1], data_in};
	     assign data_rot = data_dup >> amount;
	     assign data_out = data_rot[width-1:(2*width-1)-1];
	  end
      endcase
      
   endgenerate
   
endmodule
module c_rotate
  (amount, data_in, data_out);

   
`include "c_functions.v"
`include "c_constants.v"
   

   parameter width = 8;
   

   parameter rotate_dir = `ROTATE_DIR_LEFT;
   

   localparam amount_width = clogb(width);
   

   input [0:width-1] data_in;
   

   input [0:amount_width-1] amount;
   

   output [0:width-1] data_out;
   wire [0:width-1] data_out;
   
   wire [0:(2*width-1)-1] data_dup;
   wire [0:(2*width-1)-1] data_rot;
   
   generate
      
      case (rotate_dir)
	`ROTATE_DIR_LEFT:
	  begin
	     assign data_dup = {data_in, data_in[0:(width-1)-1]};
	     assign data_rot = data_dup << amount;
	     assign data_out = data_rot[0:width-1];
	  end
	`ROTATE_DIR_RIGHT:
	  begin
	     assign data_dup = {data_in[1:width-1], data_in};
	     assign data_rot = data_dup >> amount;
	     assign data_out = data_rot[width-1:(2*width-1)-1];
	  end
      endcase
      
   endgenerate
   
endmodule