data/full_repos/permissive/501791642/sim/nco_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/nco_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\nalways #1 CLK = ~CLK; \n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/nco_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #10000000 NOTE_VEL = 64;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501791642/sim/nco_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #10000000 NOTE_VEL = 20;\n    ^\n%Error: data/full_repos/permissive/501791642/sim/nco_tb.v:22: Cannot find file containing module: \'nco\'\nnco osc (\n^~~\n        ... Looked in:\n             data/full_repos/permissive/501791642/sim,data/full_repos/permissive/501791642/nco\n             data/full_repos/permissive/501791642/sim,data/full_repos/permissive/501791642/nco.v\n             data/full_repos/permissive/501791642/sim,data/full_repos/permissive/501791642/nco.sv\n             nco\n             nco.v\n             nco.sv\n             obj_dir/nco\n             obj_dir/nco.v\n             obj_dir/nco.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module nco_tb;

reg CLK;
reg CE;
reg [6:0] NOTE_NUM;
reg [6:0] NOTE_VEL;
reg [6:0] PROGRAM;
wire [7:0] SAMPLE_OUT;


initial begin
    CLK = 0;
    CE = 1;
    NOTE_NUM = 0;
    NOTE_VEL = 127;
    PROGRAM = 1;
end

always #1 CLK = ~CLK; 

nco osc (
    .CLK(CLK),
    .CE(CE),
    .NOTE_NUM(NOTE_NUM),
    .NOTE_VEL(NOTE_VEL),
    .PROGRAM(PROGRAM),
    .SAMPLE_OUT(SAMPLE_OUT)
);

initial begin
    #10000000 NOTE_VEL = 64;
    #10000000 NOTE_VEL = 20;
    
    
end


endmodule
module nco_tb;


reg CLK;
reg CE;
reg [6:0] NOTE_NUM;
reg [6:0] NOTE_VEL;
reg [6:0] PROGRAM;
wire [7:0] SAMPLE_OUT;


initial begin
    CLK = 0;
    CE = 1;
    NOTE_NUM = 0;
    NOTE_VEL = 127;
    PROGRAM = 1;
end

always #1 CLK = ~CLK; 

nco osc (
    .CLK(CLK),
    .CE(CE),
    .NOTE_NUM(NOTE_NUM),
    .NOTE_VEL(NOTE_VEL),
    .PROGRAM(PROGRAM),
    .SAMPLE_OUT(SAMPLE_OUT)
);

initial begin
    #10000000 NOTE_VEL = 64;
    #10000000 NOTE_VEL = 20;
    
    
end


endmodule