data/full_repos/permissive/531341619/rtl/bfp_converter_compare_exponent.v
data/verilator_xmls/c45050c4-a63e-4c64-ace0-beb5ed806574.xml
module bfp_converter_compare_exponent
#(
  EXPONENT_WIDTH = 8
) (
  input  wire clk,
  input  wire signed [EXPONENT_WIDTH-1:0] exponent_a, exponent_b, 
  output reg signed [EXPONENT_WIDTH-1:0] exponent_big,
  output reg  [EXPONENT_WIDTH-1:0] exponent_diff_a, exponent_diff_b
);
  wire [EXPONENT_WIDTH-1:0] exponent_diff;
  
  always @(posedge clk)
  begin
    if(exponent_diff[EXPONENT_WIDTH-1])
    begin
      exponent_diff_a <= -exponent_diff;
      exponent_diff_b <= 'd0;
      exponent_big <= exponent_b;
    end
    else
    begin
      exponent_diff_a <= 'd0;
      exponent_diff_b <= exponent_diff;
      exponent_big <= exponent_a;
    end
  end
  assign exponent_diff = exponent_a - exponent_b;
endmodule
module bfp_converter_compare_exponent
#(
  EXPONENT_WIDTH = 8
) (
  input  wire clk,
  input  wire signed [EXPONENT_WIDTH-1:0] exponent_a, exponent_b, 
  output reg signed [EXPONENT_WIDTH-1:0] exponent_big,
  output reg  [EXPONENT_WIDTH-1:0] exponent_diff_a, exponent_diff_b
);

  wire [EXPONENT_WIDTH-1:0] exponent_diff;
  
  always @(posedge clk)
  begin
    if(exponent_diff[EXPONENT_WIDTH-1])
    begin
      exponent_diff_a <= -exponent_diff;
      exponent_diff_b <= 'd0;
      exponent_big <= exponent_b;
    end
    else
    begin
      exponent_diff_a <= 'd0;
      exponent_diff_b <= exponent_diff;
      exponent_big <= exponent_a;
    end
  end
  assign exponent_diff = exponent_a - exponent_b;
endmodule