data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_dpopt/bdw_work/modules/dut/DPO_AUTO_EXPR/v_rtl/dut_Mul2u29Add2u8u8_4.v
data/verilator_xmls/956086a3-2eea-4245-aebf-a70064070c43.xml
module dut_Mul2u29Add2u8u8_4 (
	in3,
	in2,
	in1,
	out1
	);
input [7:0] in3,
	in2;
input [28:0] in1;
output [31:0] out1;
wire [31:0] asc001;
wire [8:0] asc002;

assign asc002 = 
	+(in3)
	+(in2);

assign asc001 = 
	+(in1 * asc002);

assign out1 = asc001;
endmodule
module dut_Mul2u29Add2u8u8_4 (
	in3,
	in2,
	in1,
	out1
	);

input [7:0] in3,
	in2;
input [28:0] in1;
output [31:0] out1;
wire [31:0] asc001;
wire [8:0] asc002;

assign asc002 = 
	+(in3)
	+(in2);

assign asc001 = 
	+(in1 * asc002);

assign out1 = asc001;
endmodule