data/full_repos/permissive/424376038/src/NES_Nexys4.v
1: b'%Error: data/full_repos/permissive/424376038/src/NES_Nexys4.v:160: Duplicate declaration of signal: \'cycle\'\n                                                                 : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n  wire [8:0] cycle;\n             ^~~~~\n        data/full_repos/permissive/424376038/src/NES_Nexys4.v:138: ... Location of original declaration\n       output [8:0] cycle,\n                    ^~~~~\n%Error: data/full_repos/permissive/424376038/src/NES_Nexys4.v:161: Duplicate declaration of signal: \'scanline\'\n  wire [8:0] scanline;\n             ^~~~~~~~\n        data/full_repos/permissive/424376038/src/NES_Nexys4.v:139: ... Location of original declaration\n       output [8:0] scanline,\n                    ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/424376038/src/NES_Nexys4.v:224: Signal definition not found, creating implicitly: \'loader_write\'\n                                                                            : ... Suggested alternative: \'loader_done\'\n                          memory_write && run_mem || loader_write,\n                                                     ^~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module NES_SSDS3(input CLKNES,
                 input CPU_RESET,
					  input  [127:0] ines_in,
					  input [7:0] joypad1,
					  input [7:0] joypad2,

                 output vga_v, output vga_h, output [3:0] vga_r, output [3:0] vga_g, output [3:0] vga_b,
					  output vga_clk,

                 output MemOE,
                 output MemWR,
                 output RamCS,
                 output [23:0] MemAdr,
                 input [7:0] MemDB_in,
					  output [7:0] MemDB_out,

					  output pixel_clock,
					  output [8:0] cycle,
					  output [8:0] scanline,
					  output [14:0] pixel_out,
					  output [5:0] color_out,
  

					  output [15:0] audio_out,
					  output audio_clock,
                 output AUD_MCLK,
                 output AUD_LRCK,
                 output AUD_SCK,
                 output AUD_SDIN
                 );

  wire clock_locked;
  wire clk;
  assign clk = CLKNES;


  reg [14:0] pallut[0:63];
  initial $readmemh("nes_palette.txt", pallut);

  wire [8:0] cycle;
  wire [8:0] scanline;
  wire [15:0] sample;
  wire [5:0] color;
  wire joypad_strobe;
  wire [1:0] joypad_clock;
  wire [21:0] memory_addr;
  wire memory_read_cpu, memory_read_ppu;
  wire memory_write;
  wire [7:0] memory_din_cpu, memory_din_ppu;
  wire [7:0] memory_dout;
  reg [7:0] joypad_bits, joypad_bits2;
  reg [1:0] last_joypad_clock;
  wire [31:0] dbgadr;
  wire [1:0] dbgctr;

  reg [1:0] nes_ce;

  always @(posedge clk) begin
    if (joypad_strobe) begin
      joypad_bits <= joypad1;
      joypad_bits2 <= joypad2;
    end
    if (!joypad_clock[0] && last_joypad_clock[0])
      joypad_bits <= {1'b0, joypad_bits[7:1]};
    if (!joypad_clock[1] && last_joypad_clock[1])
      joypad_bits2 <= {1'b0, joypad_bits2[7:1]};
    last_joypad_clock <= joypad_clock;
  end
  
  wire [21:0] loader_addr;
  wire [7:0] loader_write_data;
  wire [31:0] mapper_flags;
  wire loader_done, loader_fail;
  GameLoader loader(clk, ines_in, mapper_flags, loader_done);

  wire reset_nes = CPU_RESET;
  wire run_mem = (nes_ce == 0) && !reset_nes;
  wire run_nes = (nes_ce == 3) && !reset_nes;
  
  assign pixel_clock = (nes_ce == 3);


  always @(posedge clk)
    nes_ce <= nes_ce + 1;
    
  NES nes(clk, reset_nes, run_nes,
          mapper_flags,
          sample, color,
          joypad_strobe, joypad_clock, {joypad_bits2[0], joypad_bits[0]},
          5'b11111,
          memory_addr,
          memory_read_cpu, memory_din_cpu,
          memory_read_ppu, memory_din_ppu,
          memory_write, memory_dout,
          cycle, scanline,
          dbgadr,
          dbgctr);


  wire ram_busy;
  MemoryController memory(clk,
                          memory_read_cpu && run_mem, 
                          memory_read_ppu && run_mem,
                          memory_write && run_mem || loader_write,
                          loader_write ? {2'b00, loader_addr} : {2'b00, memory_addr},
                          loader_write ? loader_write_data : memory_dout,
                          memory_din_cpu,
                          memory_din_ppu,
                          ram_busy,
                          MemOE, MemWR, RamCS, MemAdr, MemDB_in, MemDB_out);

  wire [14:0] doubler_pixel;
  wire doubler_sync;
  wire [9:0] vga_hcounter, doubler_x;
  wire [9:0] vga_vcounter;
  assign vga_clk = clk;
  
  VgaDriver vga(clk, vga_h, vga_v, vga_r, vga_g, vga_b, vga_hcounter, vga_vcounter, doubler_x, doubler_pixel, doubler_sync, 1);
  
  wire [14:0] pixel_in = pallut[color];
  assign color_out = color;
  assign pixel_out = pixel_in;
  assign audio_out = sample;
  
  Hq2x hq2x(clk, pixel_in, 1, 
            scanline[8],
            (cycle[8:3] == 42),
            doubler_x,
            doubler_sync,
            doubler_pixel);

  wire [15:0] sound_signal = {sample[15] ^ 1'b1, sample[14:0]};
  wire [15:0] sound_signal_fir;
  wire sample_now_fir;







  reg [7:0] sound_ctr;
  always @(posedge clk)
    sound_ctr <= sound_ctr + 1;
  wire sound_load =(sound_ctr == 0);
  assign audio_clock = sound_load;
  SoundDriver sound_driver(clk, 
sound_signal, 
      sound_load,
      sound_load,
      AUD_MCLK, AUD_LRCK, AUD_SCK, AUD_SDIN);

endmodule
module NES_SSDS3(input CLKNES,
                 input CPU_RESET,
					  input  [127:0] ines_in,
					  input [7:0] joypad1,
					  input [7:0] joypad2,

                 output vga_v, output vga_h, output [3:0] vga_r, output [3:0] vga_g, output [3:0] vga_b,
					  output vga_clk,

                 output MemOE,
                 output MemWR,
                 output RamCS,
                 output [23:0] MemAdr,
                 input [7:0] MemDB_in,
					  output [7:0] MemDB_out,

					  output pixel_clock,
					  output [8:0] cycle,
					  output [8:0] scanline,
					  output [14:0] pixel_out,
					  output [5:0] color_out,
  

					  output [15:0] audio_out,
					  output audio_clock,
                 output AUD_MCLK,
                 output AUD_LRCK,
                 output AUD_SCK,
                 output AUD_SDIN
                 );


  wire clock_locked;
  wire clk;
  assign clk = CLKNES;


  reg [14:0] pallut[0:63];
  initial $readmemh("nes_palette.txt", pallut);

  wire [8:0] cycle;
  wire [8:0] scanline;
  wire [15:0] sample;
  wire [5:0] color;
  wire joypad_strobe;
  wire [1:0] joypad_clock;
  wire [21:0] memory_addr;
  wire memory_read_cpu, memory_read_ppu;
  wire memory_write;
  wire [7:0] memory_din_cpu, memory_din_ppu;
  wire [7:0] memory_dout;
  reg [7:0] joypad_bits, joypad_bits2;
  reg [1:0] last_joypad_clock;
  wire [31:0] dbgadr;
  wire [1:0] dbgctr;

  reg [1:0] nes_ce;

  always @(posedge clk) begin
    if (joypad_strobe) begin
      joypad_bits <= joypad1;
      joypad_bits2 <= joypad2;
    end
    if (!joypad_clock[0] && last_joypad_clock[0])
      joypad_bits <= {1'b0, joypad_bits[7:1]};
    if (!joypad_clock[1] && last_joypad_clock[1])
      joypad_bits2 <= {1'b0, joypad_bits2[7:1]};
    last_joypad_clock <= joypad_clock;
  end
  
  wire [21:0] loader_addr;
  wire [7:0] loader_write_data;
  wire [31:0] mapper_flags;
  wire loader_done, loader_fail;
  GameLoader loader(clk, ines_in, mapper_flags, loader_done);

  wire reset_nes = CPU_RESET;
  wire run_mem = (nes_ce == 0) && !reset_nes;
  wire run_nes = (nes_ce == 3) && !reset_nes;
  
  assign pixel_clock = (nes_ce == 3);


  always @(posedge clk)
    nes_ce <= nes_ce + 1;
    
  NES nes(clk, reset_nes, run_nes,
          mapper_flags,
          sample, color,
          joypad_strobe, joypad_clock, {joypad_bits2[0], joypad_bits[0]},
          5'b11111,
          memory_addr,
          memory_read_cpu, memory_din_cpu,
          memory_read_ppu, memory_din_ppu,
          memory_write, memory_dout,
          cycle, scanline,
          dbgadr,
          dbgctr);


  wire ram_busy;
  MemoryController memory(clk,
                          memory_read_cpu && run_mem, 
                          memory_read_ppu && run_mem,
                          memory_write && run_mem || loader_write,
                          loader_write ? {2'b00, loader_addr} : {2'b00, memory_addr},
                          loader_write ? loader_write_data : memory_dout,
                          memory_din_cpu,
                          memory_din_ppu,
                          ram_busy,
                          MemOE, MemWR, RamCS, MemAdr, MemDB_in, MemDB_out);

  wire [14:0] doubler_pixel;
  wire doubler_sync;
  wire [9:0] vga_hcounter, doubler_x;
  wire [9:0] vga_vcounter;
  assign vga_clk = clk;
  
  VgaDriver vga(clk, vga_h, vga_v, vga_r, vga_g, vga_b, vga_hcounter, vga_vcounter, doubler_x, doubler_pixel, doubler_sync, 1);
  
  wire [14:0] pixel_in = pallut[color];
  assign color_out = color;
  assign pixel_out = pixel_in;
  assign audio_out = sample;
  
  Hq2x hq2x(clk, pixel_in, 1, 
            scanline[8],
            (cycle[8:3] == 42),
            doubler_x,
            doubler_sync,
            doubler_pixel);

  wire [15:0] sound_signal = {sample[15] ^ 1'b1, sample[14:0]};
  wire [15:0] sound_signal_fir;
  wire sample_now_fir;







  reg [7:0] sound_ctr;
  always @(posedge clk)
    sound_ctr <= sound_ctr + 1;
  wire sound_load =(sound_ctr == 0);
  assign audio_clock = sound_load;
  SoundDriver sound_driver(clk, 
sound_signal, 
      sound_load,
      sound_load,
      AUD_MCLK, AUD_LRCK, AUD_SCK, AUD_SDIN);

endmodule