data/full_repos/permissive/497604366/cpu/cpu.srcs/sources_1/new/alu_mux.v
data/verilator_xmls/99a4b462-9539-4b0f-9b60-a80e96f23e66.xml
module alu_mux(
    input [31:0] eqb,
    input [31:0] eimm32,
    input ealuimm,
    output reg [31:0] b
    );
    
    always @(*) begin
        if (ealuimm == 0) begin
            b <= eqb;
        end
        if (ealuimm == 1) begin
            b <= eimm32;
        end
    end
endmodule
module alu_mux(
    input [31:0] eqb,
    input [31:0] eimm32,
    input ealuimm,
    output reg [31:0] b
    );

    
    always @(*) begin
        if (ealuimm == 0) begin
            b <= eqb;
        end
        if (ealuimm == 1) begin
            b <= eimm32;
        end
    end
endmodule