data/full_repos/permissive/451577625/system/register_32.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/451577625/system/register_32.v:45: Unsupported: Ignoring delay on this delayed statement.\n   forever #10 clockin = ~clockin;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/register_32.v:77: Unsupported: Ignoring delay on this delayed statement.\n    #10;  \n    ^\n%Warning-INFINITELOOP: data/full_repos/permissive/451577625/system/register_32.v:45: Infinite loop (condition always true)\n                                                                                   : ... In instance register_32_tb\n   forever #10 clockin = ~clockin;\n   ^~~~~~~\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module register_32(input [31:0] D, output [31:0] Q, input clr, input clk, input write);

	reg [31:0] value_32;
	initial begin
		value_32 [31:0] = 32'b0;
	end
	



	
	always @ (posedge clk, negedge clr)
	if(clr == 0) begin
		value_32 [31:0] <= 32'b0;
	end else if(write == 1) begin
		value_32 [31:0] <= D [31:0];
	end
	
	assign Q [31:0] = value_32 [31:0];
	
endmodule
module register_32(input [31:0] D, output [31:0] Q, input clr, input clk, input write);


	reg [31:0] value_32;
	initial begin
		value_32 [31:0] = 32'b0;
	end
	



	
	always @ (posedge clk, negedge clr)
	if(clr == 0) begin
		value_32 [31:0] <= 32'b0;
	end else if(write == 1) begin
		value_32 [31:0] <= D [31:0];
	end
	
	assign Q [31:0] = value_32 [31:0];
	
endmodule