data/full_repos/permissive/437157208/src/FF_W_en.v
data/verilator_xmls/51ff00ef-6633-404e-ae49-34e2ca18f877.xml
module FF_W_en

 #(
	parameter WIDTH = 32
)
(

	input			[WIDTH-1:0] D, 
	input 		clk,
	input			reset,
	output		[WIDTH-1:0] Q
);

	reg [WIDTH-1:0] data;
	always @(posedge clk or negedge reset) 
	begin
      if (!reset)
         data <= 0;
      else
         data <= D;
   end 
	assign Q = data;	
endmodule
module FF_W_en

 #(
	parameter WIDTH = 32
)
(

	input			[WIDTH-1:0] D, 
	input 		clk,
	input			reset,
	output		[WIDTH-1:0] Q
);


	reg [WIDTH-1:0] data;
	always @(posedge clk or negedge reset) 
	begin
      if (!reset)
         data <= 0;
      else
         data <= D;
   end 
	assign Q = data;	
endmodule