data/full_repos/permissive/486035660/verilog/rtl/Microwatt_FP_DFFRFile.v
data/verilator_xmls/6e6017c2-4e5c-4ed2-914c-21a0718a8b78.xml
module Microwatt_FP_DFFRFile (
`ifdef USE_POWER_PINS
    inout VPWR,
    inout VGND,
`endif
    input [5:0]   R1, R2, R3, RW,
    input [63:0]  DW,
    output reg [63:0] D1, D2, D3,
    input CLK,
    input WE
);

    reg [63:0] registers[0:63];

    always @(posedge CLK) begin
        if (WE)
            registers[RW] <= DW;
        D1 <= registers[R1];
        D2 <= registers[R2];
        D3 <= registers[R3];
    end

endmodule
module Microwatt_FP_DFFRFile (
`ifdef USE_POWER_PINS
    inout VPWR,
    inout VGND,
`endif
    input [5:0]   R1, R2, R3, RW,
    input [63:0]  DW,
    output reg [63:0] D1, D2, D3,
    input CLK,
    input WE
);


    reg [63:0] registers[0:63];

    always @(posedge CLK) begin
        if (WE)
            registers[RW] <= DW;
        D1 <= registers[R1];
        D2 <= registers[R2];
        D3 <= registers[R3];
    end

endmodule