data/full_repos/permissive/493019833/test/testcase/firrtl/ClockDividerTest/sbt/ClockDividerTest.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/ClockDividerTest/sbt/ClockDividerTest.v:16: Operator DIV expects 8 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                                                    : ... In instance ClockDividerTest\n  wire [7:0] _T_19 = reg1 / 2\'h2;  \n                          ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module ClockDividerTest(
  input   clock,
  input   reset
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif
  reg  cDiv;
  reg [7:0] reg1;
  wire [7:0] _T_10 = reg1 + 8'h1;
  reg [7:0] reg2;
  wire [7:0] _T_15 = reg2 + 8'h1;
  wire  _T_17 = reg1 < 8'ha;
  wire [7:0] _T_19 = reg1 / 2'h2;
  wire  _T_26 = reg1 == 8'ha;
  always @(posedge clock) begin
    cDiv <= reset | ~cDiv;
    if (reset) begin
      reg1 <= 8'h0;
    end else begin
      reg1 <= _T_10;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_17 & ~(reg2 == _T_19 | reset)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at MultiClockSpec.scala:22 assert(reg2 === reg1 / 2.U) // 1:2 clock relationship\n");
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_17 & ~(reg2 == _T_19 | reset)) begin
          $fatal;
        end
    `ifdef STOP_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_26 & ~reset) begin
          $finish;
        end
    `ifdef STOP_COND
      end
    `endif
    `endif
  end
  always @(posedge cDiv) begin
    if (reset) begin
      reg2 <= 8'h0;
    end else begin
      reg2 <= _T_15;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  cDiv = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  reg1 = _RAND_1[7:0];
  _RAND_2 = {1{`RANDOM}};
  reg2 = _RAND_2[7:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module ClockDividerTest(
  input   clock,
  input   reset
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif
  reg  cDiv;
  reg [7:0] reg1;
  wire [7:0] _T_10 = reg1 + 8'h1;
  reg [7:0] reg2;
  wire [7:0] _T_15 = reg2 + 8'h1;
  wire  _T_17 = reg1 < 8'ha;
  wire [7:0] _T_19 = reg1 / 2'h2;
  wire  _T_26 = reg1 == 8'ha;
  always @(posedge clock) begin
    cDiv <= reset | ~cDiv;
    if (reset) begin
      reg1 <= 8'h0;
    end else begin
      reg1 <= _T_10;
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_17 & ~(reg2 == _T_19 | reset)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at MultiClockSpec.scala:22 assert(reg2 === reg1 / 2.U) // 1:2 clock relationship\n");
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_17 & ~(reg2 == _T_19 | reset)) begin
          $fatal;
        end
    `ifdef STOP_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_26 & ~reset) begin
          $finish;
        end
    `ifdef STOP_COND
      end
    `endif
    `endif
  end
  always @(posedge cDiv) begin
    if (reset) begin
      reg2 <= 8'h0;
    end else begin
      reg2 <= _T_15;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  cDiv = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  reg1 = _RAND_1[7:0];
  _RAND_2 = {1{`RANDOM}};
  reg2 = _RAND_2[7:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule