data/full_repos/permissive/480154458/Gateware/riscv/icarus/tb_system.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/480154458/Gateware/riscv/icarus/tb_system.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #(2*10.4167) clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/480154458/Gateware/riscv/icarus/tb_system.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #(10.4167) hclk = ~hclk;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/480154458/Gateware/riscv/icarus/tb_system.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #1000\n        ^\n%Error: data/full_repos/permissive/480154458/Gateware/riscv/icarus/tb_system.v:55: Cannot find file containing module: \'system\'\n system u_riscv(\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/480154458/Gateware/riscv/icarus,data/full_repos/permissive/480154458/system\n             data/full_repos/permissive/480154458/Gateware/riscv/icarus,data/full_repos/permissive/480154458/system.v\n             data/full_repos/permissive/480154458/Gateware/riscv/icarus,data/full_repos/permissive/480154458/system.sv\n             system\n             system.v\n             system.sv\n             obj_dir/system\n             obj_dir/system.v\n             obj_dir/system.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_system;
    reg clk, hclk;
    reg reset, hreset;
	reg rx;
	wire tx;
	reg [11:0] a0, a1, a2, a3;
	wire [31:0] gp_out0, gp_out1, gp_out2, gp_out3;
	

    always
        #(2*10.4167) clk = ~clk;
    

    always
        #(10.4167) hclk = ~hclk;
    

    initial
    begin
`ifdef icarus
  		$dumpfile("tb_system.vcd");
		$dumpvars;
`endif
		

        clk = 1'b0;
        reset = 1'b1;
        hclk = 1'b0;
        hreset = 1'b1;
		rx = 1'b1;
		a0 = 12'h000;
		a1 = 12'h000;
		a2 = 12'h000;
		a3 = 12'h000;
		

        #1000
        reset = 1'b0;
        hreset = 1'b0;
        
`ifdef icarus


		#700000 $finish;
`endif
    end
	

	system u_riscv(
		.clk24(clk),
		.reset(reset),
		.RX(rx),
		.TX(tx),
		.gp_in0({20'h00000,a0}),
		.gp_in1({20'h00000,a1}),
		.gp_in2({20'h00000,a2}),
		.gp_in3({20'h00000,a3}),
		.gp_out0(gp_out0),
		.gp_out1(gp_out1),
		.gp_out2(gp_out2),
		.gp_out3(gp_out3),
		.ext_clk(hclk),
		.ext_reset(hreset),
		.mbx_ord(1'b0)
	);
endmodule
module tb_system;

    reg clk, hclk;
    reg reset, hreset;
	reg rx;
	wire tx;
	reg [11:0] a0, a1, a2, a3;
	wire [31:0] gp_out0, gp_out1, gp_out2, gp_out3;
	

    always
        #(2*10.4167) clk = ~clk;
    

    always
        #(10.4167) hclk = ~hclk;
    

    initial
    begin
`ifdef icarus
  		$dumpfile("tb_system.vcd");
		$dumpvars;
`endif
		

        clk = 1'b0;
        reset = 1'b1;
        hclk = 1'b0;
        hreset = 1'b1;
		rx = 1'b1;
		a0 = 12'h000;
		a1 = 12'h000;
		a2 = 12'h000;
		a3 = 12'h000;
		

        #1000
        reset = 1'b0;
        hreset = 1'b0;
        
`ifdef icarus


		#700000 $finish;
`endif
    end
	

	system u_riscv(
		.clk24(clk),
		.reset(reset),
		.RX(rx),
		.TX(tx),
		.gp_in0({20'h00000,a0}),
		.gp_in1({20'h00000,a1}),
		.gp_in2({20'h00000,a2}),
		.gp_in3({20'h00000,a3}),
		.gp_out0(gp_out0),
		.gp_out1(gp_out1),
		.gp_out2(gp_out2),
		.gp_out3(gp_out3),
		.ext_clk(hclk),
		.ext_reset(hreset),
		.mbx_ord(1'b0)
	);
endmodule