data/full_repos/permissive/43856783/crc_16/peripheral_crc_16.v
1: b'%Warning-WIDTH: data/full_repos/permissive/43856783/crc_16/peripheral_crc_16.v:62: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s VARREF \'data_out\' generates 16 bits.\n                                                                                 : ... In instance peripheral_crc_16\n   2\'b10: d_out[6:0]  = data_out ;\n                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/43856783/crc_16/peripheral_crc_16.v:68: Cannot find file containing module: \'crc_16\'\n crc_16 c_16 ( .clk(clk), .rst(rst), .data_in(data_in), .start(start), .data_out(data_out), .done(done) );  \n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43856783/crc_16,data/full_repos/permissive/43856783/crc_16\n             data/full_repos/permissive/43856783/crc_16,data/full_repos/permissive/43856783/crc_16.v\n             data/full_repos/permissive/43856783/crc_16,data/full_repos/permissive/43856783/crc_16.sv\n             crc_16\n             crc_16.v\n             crc_16.sv\n             obj_dir/crc_16\n             obj_dir/crc_16.v\n             obj_dir/crc_16.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module peripheral_crc_16 (clk , rst , d_in , cs , addr , rd , wr, d_out );
  	

	  input clk;
	  input rst;
	  input [15:0]d_in;
	  input cs;
	  input [3:0]addr;
	  input rd;
	  input wr;
	  output reg [15:0]d_out;




	reg [4:0] s;
	
	reg [31:0] data_in=0;
	reg start=0;

	wire [15:0] data_out;
	wire done;





	always @(*) begin
		case (addr)


			4'h0:begin s = (cs && wr) ? 5'b00001 : 5'b00000 ;end
			4'h2:begin s = (cs && wr) ? 5'b00010 : 5'b00000 ;end
			4'h4:begin s = (cs && wr) ? 5'b00100 : 5'b00000 ;end
			

			4'h6:begin s = (cs && rd) ? 5'b01000 : 5'b00000 ;end
			4'h8:begin s = (cs && rd) ? 5'b10000 : 5'b00000 ;end

			default:begin s = 5'b00000 ; end
		endcase
	end




	always @(negedge clk) begin

		data_in[31:16] = (s[0]) ? d_in : data_in[31:16];
		data_in[15:0] = (s[1]) ? d_in : data_in[15:0];
		start = s[2];
	

	end




	always @(negedge clk) begin
		case (s[4:3])
			2'b01: d_out[0] = done ;
			2'b10: d_out[6:0]  = data_out ;
			default: d_out   = 0 ;
		endcase
	end


	crc_16 c_16 ( .clk(clk), .rst(rst), .data_in(data_in), .start(start), .data_out(data_out), .done(done) );



endmodule
module peripheral_crc_16 (clk , rst , d_in , cs , addr , rd , wr, d_out );

  	

	  input clk;
	  input rst;
	  input [15:0]d_in;
	  input cs;
	  input [3:0]addr;
	  input rd;
	  input wr;
	  output reg [15:0]d_out;




	reg [4:0] s;
	
	reg [31:0] data_in=0;
	reg start=0;

	wire [15:0] data_out;
	wire done;





	always @(*) begin
		case (addr)


			4'h0:begin s = (cs && wr) ? 5'b00001 : 5'b00000 ;end
			4'h2:begin s = (cs && wr) ? 5'b00010 : 5'b00000 ;end
			4'h4:begin s = (cs && wr) ? 5'b00100 : 5'b00000 ;end
			

			4'h6:begin s = (cs && rd) ? 5'b01000 : 5'b00000 ;end
			4'h8:begin s = (cs && rd) ? 5'b10000 : 5'b00000 ;end

			default:begin s = 5'b00000 ; end
		endcase
	end




	always @(negedge clk) begin

		data_in[31:16] = (s[0]) ? d_in : data_in[31:16];
		data_in[15:0] = (s[1]) ? d_in : data_in[15:0];
		start = s[2];
	

	end




	always @(negedge clk) begin
		case (s[4:3])
			2'b01: d_out[0] = done ;
			2'b10: d_out[6:0]  = data_out ;
			default: d_out   = 0 ;
		endcase
	end


	crc_16 c_16 ( .clk(clk), .rst(rst), .data_in(data_in), .start(start), .data_out(data_out), .done(done) );



endmodule