data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:119: Signal definition not found, creating implicitly: \'dram_io_pad_enable_p_d1\'\n                                                                                                        : ... Suggested alternative: \'dram_io_pad_enable_d1\'\nwire dq_pad_pos_neg_rd_en = dram_io_pad_enable_p_d1 | dram_io_pad_enable_pn_d1;\n                            ^~~~~~~~~~~~~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:119: Signal definition not found, creating implicitly: \'dram_io_pad_enable_pn_d1\'\n                                                                                                        : ... Suggested alternative: \'dram_io_pad_enable_p_d1\'\nwire dq_pad_pos_neg_rd_en = dram_io_pad_enable_p_d1 | dram_io_pad_enable_pn_d1;\n                                                      ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:120: Signal definition not found, creating implicitly: \'dram_io_pad_enable_n_d1\'\n                                                                                                        : ... Suggested alternative: \'dram_io_pad_enable_p_d1\'\nwire dq_pad_neg_pos_rd_en = dram_io_pad_enable_n_d1 | dram_io_pad_enable_np_d1;\n                            ^~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:120: Signal definition not found, creating implicitly: \'dram_io_pad_enable_np_d1\'\n                                                                                                        : ... Suggested alternative: \'dram_io_pad_enable_n_d1\'\nwire dq_pad_neg_pos_rd_en = dram_io_pad_enable_n_d1 | dram_io_pad_enable_np_d1;\n                                                      ^~~~~~~~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:137: Signal definition not found, creating implicitly: \'data_neg_d1\'\n                                                                                                        : ... Suggested alternative: \'data_neg\'\nwire data_out = dqs_read ? data_neg_d1 : data_pos_d1;\n                           ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:137: Signal definition not found, creating implicitly: \'data_pos_d1\'\n                                                                                                        : ... Suggested alternative: \'data_pos\'\nwire data_out = dqs_read ? data_neg_d1 : data_pos_d1;\n                                         ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:151: Signal definition not found, creating implicitly: \'enable_data\'\nwire output_enable = (enable_data & enable_q);\n                      ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:151: Signal definition not found, creating implicitly: \'enable_q\'\n                                                                                                        : ... Suggested alternative: \'enable_data\'\nwire output_enable = (enable_data & enable_q);\n                                    ^~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:231: Signal definition not found, creating implicitly: \'dram_pad_data2\'\nassign pad_pos_data = pad_pos_cnt[1:0] == 3 ? dram_pad_data2 : \n                                              ^~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:232: Signal definition not found, creating implicitly: \'dram_pad_data1\'\n                                                                                                        : ... Suggested alternative: \'dram_pad_data2\'\n     pad_pos_cnt[1:0] == 2 ? dram_pad_data1 :\n                             ^~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:233: Signal definition not found, creating implicitly: \'dram_pad_data0\'\n                                                                                                        : ... Suggested alternative: \'dram_pad_data1\'\n     pad_pos_cnt[1:0] == 1 ?  dram_pad_data0 : dram_pad_data3;\n                              ^~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:233: Signal definition not found, creating implicitly: \'dram_pad_data3\'\n                                                                                                        : ... Suggested alternative: \'dram_pad_data0\'\n     pad_pos_cnt[1:0] == 1 ?  dram_pad_data0 : dram_pad_data3;\n                                               ^~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:234: Signal definition not found, creating implicitly: \'dram_neg_pad_data2\'\n                                                                                                        : ... Suggested alternative: \'dram_pad_data2\'\nassign pad_neg_data = pad_neg_cnt[1:0] == 3 ?  dram_neg_pad_data2 : \n                                               ^~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:235: Signal definition not found, creating implicitly: \'dram_neg_pad_data1\'\n                                                                                                        : ... Suggested alternative: \'dram_neg_pad_data2\'\n                                 pad_neg_cnt[1:0] == 2 ? dram_neg_pad_data1 :\n                                                         ^~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:236: Signal definition not found, creating implicitly: \'dram_neg_pad_data0\'\n                                                                                                        : ... Suggested alternative: \'dram_neg_pad_data1\'\n                                 pad_neg_cnt[1:0] == 1 ?  dram_neg_pad_data0 : dram_neg_pad_data3;\n                                                          ^~~~~~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:236: Signal definition not found, creating implicitly: \'dram_neg_pad_data3\'\n                                                                                                        : ... Suggested alternative: \'dram_neg_pad_data0\'\n                                 pad_neg_cnt[1:0] == 1 ?  dram_neg_pad_data0 : dram_neg_pad_data3;\n                                                                               ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:88: Cannot find file containing module: \'dff_s\'\ndff_s #(1) flop_io_pad_clk_bit1(\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/dff_s\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/dff_s.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/dff_s.sv\n             dff_s\n             dff_s.v\n             dff_s.sv\n             obj_dir/dff_s\n             obj_dir/dff_s.v\n             obj_dir/dff_s.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:94: Cannot find file containing module: \'dff_s\'\ndff_s #(1) flop_io_pad_enable_p(\n^~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:100: Cannot find file containing module: \'dff_s\'\ndff_s #(1) flop_io_pad_enable_pn(\n^~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:106: Cannot find file containing module: \'dff_s\'\ndff_s #(1) flop_io_pad_enable_n(\n^~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:112: Cannot find file containing module: \'dff_s\'\ndff_s #(1) flop_io_pad_enable_np(\n^~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:127: Cannot find file containing module: \'dff_s\'\ndff_s #(1) flop_data_pos(\n^~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:132: Cannot find file containing module: \'dff_s\'\ndff_s #(1) flop_data_neg(\n^~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:141: Cannot find file containing module: \'dff_s\'\ndff_s #(1)        flop_drive_dqs(\n^~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:146: Cannot find file containing module: \'dff_s\'\ndff_s #(1)        flop_drive_data(\n^~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:163: Cannot find file containing module: \'dffrl_async\'\ndffrl_async #(1) ff_ptr_pos0(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:169: Cannot find file containing module: \'dffrl_async\'\ndffrl_async #(1) ff_ptr_pos1(\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:181: Cannot find file containing module: \'dffe_s\'\ndffe_s #(1)        ff_data_pos0_in0(\n^~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:187: Cannot find file containing module: \'dffe_s\'\ndffe_s #(1)        ff_data_pos1_in0(\n^~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:193: Cannot find file containing module: \'dffe_s\'\ndffe_s #(1)        ff_data_pos2_in0(\n^~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:199: Cannot find file containing module: \'dffe_s\'\ndffe_s #(1)        ff_data_pos3_in0(\n^~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:207: Cannot find file containing module: \'dffe_s\'\ndffe_s #(1)        ff_data_neg0_in0(\n^~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:213: Cannot find file containing module: \'dffe_s\'\ndffe_s #(1)        ff_data_neg1_in0(\n^~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:219: Cannot find file containing module: \'dffe_s\'\ndffe_s #(1)        ff_data_neg2_in0(\n^~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:225: Cannot find file containing module: \'dffe_s\'\ndffe_s #(1)        ff_data_neg3_in0(\n^~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:240: Cannot find file containing module: \'dff_s\'\ndff_s #(1)      ff_data_pos_dqs(\n^~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:245: Cannot find file containing module: \'dff_s\'\ndff_s #(1)      ff_data_neg_dqs(\n^~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:260: Cannot find file containing module: \'bw_u1_scanlg_2x\'\nbw_u1_scanlg_2x lockup_latch_clk_dqs(\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:266: Cannot find file containing module: \'bw_u1_scanlg_2x\'\nbw_u1_scanlg_2x lockup_latch_dqs_inv_dqs(\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_dq_edgelogic.v:274: Cannot find file containing module: \'dff_ns\'\ndff_ns #(1)      ff_dummy_scan(\n^~~~~~\n%Error: Exiting due to 24 error(s), 16 warning(s)\n'
module dram_dq_edgelogic(

   io_dram_data_in_hi, io_dram_data_in, dq_pad_clk_so, 
   to_pad, oe, afi, 

   clk, rst_l, arst_l, dq_pad_clk_se, dq_pad_clk_si, dqs_read, data_pos, 
   data_neg, pad_pos_cnt, pad_neg_cnt, dram_io_drive_enable, 
   dram_io_pad_enable, dram_io_ptr_clk_inv, 
   burst_length_four, to_core, testmode_l, test_mode, tp_out_type, afo
   );




input			clk;
input			rst_l;
input			arst_l;
input			dq_pad_clk_se;
input			dq_pad_clk_si;
input			dqs_read;
input			data_pos;
input			data_neg;
input [1:0]		pad_pos_cnt;
input [1:0]		pad_neg_cnt;
input			dram_io_drive_enable;
input			dram_io_pad_enable;
input 			dram_io_ptr_clk_inv;
input			burst_length_four;
input			to_core;
input			testmode_l;
input			test_mode;
input			tp_out_type;
input			afo;




output			io_dram_data_in_hi;
output			io_dram_data_in;
output			dq_pad_clk_so;
output			to_pad;
output			oe;
output			afi;


wire [0:0]		pad_ptr0_pos;
wire [0:0]		pad_ptr1_pos;
wire [0:0]		pad_ptr2_pos;
wire [0:0]		pad_ptr3_pos;
wire			pad_pos_data;
wire			pad_neg_data;
wire			pad_data_clk_flip_out;
wire			pad_data_cap_clk;
wire			dq_pad_enable;
wire [1:0]		pad_ptr_pos0_in;
wire [1:0]		pad_ptr_pos0;
wire 			dram_io_ptr_clk_d1;






wire tclk = testmode_l ? ~clk : clk;



dff_s #(1)	flop_io_pad_clk_bit1(
		.din(dram_io_ptr_clk_inv),
		.q(dram_io_ptr_clk_d1),
		.clk(clk), 
		.si(dq_pad_clk_si), .so(dq_pad_clk_si0), .se(dq_pad_clk_se));

dff_s #(1)	flop_io_pad_enable_p(
		.din(dram_io_pad_enable),
		.q(dram_io_pad_enable_p_d1),
		.clk(clk), 
		.si(dq_pad_clk_si13), .so(dq_pad_clk_si1), .se(dq_pad_clk_se));

dff_s #(1)	flop_io_pad_enable_pn(
		.din(dram_io_pad_enable_p_d1),
		.q(dram_io_pad_enable_pn_d1),
		.clk(tclk), 
		.si(dq_pad_clk_si0), .so(dq_pad_clk_si13), .se(dq_pad_clk_se));

dff_s #(1)	flop_io_pad_enable_n(
		.din(dram_io_pad_enable),
		.q(dram_io_pad_enable_n_d1),
		.clk(tclk), 
		.si(dq_pad_clk_si14), .so(dq_pad_clk_si2), .se(dq_pad_clk_se));

dff_s #(1)	flop_io_pad_enable_np(
		.din(dram_io_pad_enable_n_d1),
		.q(dram_io_pad_enable_np_d1),
		.clk(clk), 
		.si(dq_pad_clk_si1), .so(dq_pad_clk_si14), .se(dq_pad_clk_se));


wire dq_pad_pos_neg_rd_en = dram_io_pad_enable_p_d1 | dram_io_pad_enable_pn_d1;
wire dq_pad_neg_pos_rd_en = dram_io_pad_enable_n_d1 | dram_io_pad_enable_np_d1;

wire dram_io_pad_enable_d1 = dram_io_ptr_clk_d1 ? dq_pad_neg_pos_rd_en : dq_pad_pos_neg_rd_en;
assign dq_pad_enable = dram_io_pad_enable_d1 | (pad_ptr_pos0[0] == 1'b1);



dff_s #(1)	flop_data_pos(
		.din(data_pos),
		.q(data_pos_d1),
		.clk(tclk), .si(dq_pad_clk_si2), .so(dq_pad_clk_si3), .se(dq_pad_clk_se));

dff_s #(1)	flop_data_neg(
		.din(data_neg),
		.q(data_neg_d1),
		.clk(clk), .si(dq_pad_clk_si4), .so(dq_pad_clk_si5), .se(dq_pad_clk_se)); 

wire data_out = dqs_read ? data_neg_d1 : data_pos_d1;



dff_s #(1)        flop_drive_dqs(
                .din(dram_io_drive_enable),
                .q(enable_q),
                .clk(clk), .si(dq_pad_clk_si5), .so(dq_pad_clk_so_clk), .se(dq_pad_clk_se)); 

dff_s #(1)        flop_drive_data(
                .din(enable_q),
                .q(enable_data),
                .clk(tclk), .si(dq_pad_clk_si3), .so(dq_pad_clk_si4), .se(dq_pad_clk_se));

wire output_enable = (enable_data & enable_q);




assign pad_ptr_pos0_in[1:0] = burst_length_four ? (
				dq_pad_enable ? pad_ptr_pos0 + 1'b1 : pad_ptr_pos0[1:0]) :
                             	(dram_io_pad_enable_d1 | ~(pad_ptr_pos0[1:0] == 2'b00)) ?
				pad_ptr_pos0 + 1'b1 : pad_ptr_pos0;



dffrl_async #(1) ff_ptr_pos0(
                .din(pad_ptr_pos0_in[0]),
                .q(pad_ptr_pos0[0]),
                .rst_l(arst_l & (rst_l | ~testmode_l)),
                .clk(~dqs_read), .se(dq_pad_clk_se), .si(dq_pad_clk_si15), .so(dq_pad_clkn_si0));

dffrl_async #(1) ff_ptr_pos1(
                .din(pad_ptr_pos0_in[1]),
                .q(pad_ptr_pos0[1]),
                .rst_l(arst_l & (rst_l | ~testmode_l)),
                .clk(~dqs_read), .se(dq_pad_clk_se), .si(dq_pad_clkn_si0), .so(dq_pad_clkn_si1));

assign pad_ptr0_pos[0] = pad_ptr_pos0 == 0;
assign pad_ptr1_pos[0] = pad_ptr_pos0 == 1;
assign pad_ptr2_pos[0] = pad_ptr_pos0 == 2;
assign pad_ptr3_pos[0] = pad_ptr_pos0 == 3;


dffe_s #(1)        ff_data_pos0_in0(
                .din(to_core),
                .q(dram_pad_data0),
		.en(pad_ptr0_pos[0]),
                .clk(dqs_read), .se(dq_pad_clk_se), .si(dq_pad_clk_si6), .so(dq_pad_clk_si7));
                
dffe_s #(1)        ff_data_pos1_in0(
                .din(to_core),
                .q(dram_pad_data1),
		.en(pad_ptr1_pos[0]),
                .clk(dqs_read), .se(dq_pad_clk_se), .si(dq_pad_clk_si7), .so(dq_pad_clk_si8));
                
dffe_s #(1)        ff_data_pos2_in0(
                .din(to_core),
                .q(dram_pad_data2),
                .en(pad_ptr2_pos[0]),
                .clk(dqs_read), .se(dq_pad_clk_se), .si(dq_pad_clk_si8), .so(dq_pad_clk_si9));
                
dffe_s #(1)        ff_data_pos3_in0(
                .din(to_core),
                .q(dram_pad_data3),
                .en(pad_ptr3_pos[0]),
                .clk(dqs_read), .se(dq_pad_clk_se), .si(dq_pad_clk_si9), .so(dq_pad_clk_si10));



dffe_s #(1)        ff_data_neg0_in0(
                .din(to_core),
                .q(dram_neg_pad_data0),
		.en(pad_ptr0_pos[0]),
                .clk(~dqs_read), .se(dq_pad_clk_se), .si(dq_pad_clkn_si1), .so(dq_pad_clkn_si2));

dffe_s #(1)        ff_data_neg1_in0(
                .din(to_core),
                .q(dram_neg_pad_data1),
		.en(pad_ptr1_pos[0]),
                .clk(~dqs_read), .se(dq_pad_clk_se), .si(dq_pad_clkn_si2), .so(dq_pad_clkn_si3));

dffe_s #(1)        ff_data_neg2_in0(
                .din(to_core),
                .q(dram_neg_pad_data2),
		.en(pad_ptr2_pos[0]),
                .clk(~dqs_read), .se(dq_pad_clk_se), .si(dq_pad_clkn_si3), .so(dq_pad_clkn_si4));

dffe_s #(1)        ff_data_neg3_in0(
                .din(to_core),
                .q(dram_neg_pad_data3),
		.en(pad_ptr3_pos[0]),
                .clk(~dqs_read), .se(dq_pad_clk_se), .si(dq_pad_clkn_si4), .so(dq_pad_clkn_so));

assign pad_pos_data = pad_pos_cnt[1:0] == 3 ? dram_pad_data2 : 
				 pad_pos_cnt[1:0] == 2 ? dram_pad_data1 :
				 pad_pos_cnt[1:0] == 1 ?  dram_pad_data0 : dram_pad_data3;
assign pad_neg_data = pad_neg_cnt[1:0] == 3 ?  dram_neg_pad_data2 : 
                                 pad_neg_cnt[1:0] == 2 ? dram_neg_pad_data1 :
                                 pad_neg_cnt[1:0] == 1 ?  dram_neg_pad_data0 : dram_neg_pad_data3;



dff_s #(1)      ff_data_pos_dqs(
                .din(pad_pos_data),
                .q(io_dram_data_in_hi),
                .clk(clk), .se(dq_pad_clk_se), .si(dq_pad_clk_so_clk), .so(dq_pad_clk_si11));

dff_s #(1)      ff_data_neg_dqs(
                .din(pad_neg_data),
                .q(io_dram_data_in),
                .clk(tclk), 
		.se(dq_pad_clk_se), .si(dq_pad_clk_si11), .so(dq_pad_clk_si12));



assign oe = test_mode ? tp_out_type : output_enable;
assign to_pad = test_mode ? afo : data_out;
assign afi = test_mode & to_core;




bw_u1_scanlg_2x lockup_latch_clk_dqs(
		.so(dq_pad_clk_si6), 
		.sd(dq_pad_clk_si12), 
		.ck(tclk), 
		.se(dq_pad_clk_se));

bw_u1_scanlg_2x lockup_latch_dqs_inv_dqs(
		.so(dq_pad_clk_si15), 
		.sd(dq_pad_clk_si10), 
		.ck(dqs_read), 
		.se(dq_pad_clk_se));



dff_ns #(1)      ff_dummy_scan(
                .din(dq_pad_clkn_so),
                .q(dq_pad_clk_so),
                .clk(clk)); 

endmodule
module dram_dq_edgelogic(

   io_dram_data_in_hi, io_dram_data_in, dq_pad_clk_so, 
   to_pad, oe, afi, 

   clk, rst_l, arst_l, dq_pad_clk_se, dq_pad_clk_si, dqs_read, data_pos, 
   data_neg, pad_pos_cnt, pad_neg_cnt, dram_io_drive_enable, 
   dram_io_pad_enable, dram_io_ptr_clk_inv, 
   burst_length_four, to_core, testmode_l, test_mode, tp_out_type, afo
   );





input			clk;
input			rst_l;
input			arst_l;
input			dq_pad_clk_se;
input			dq_pad_clk_si;
input			dqs_read;
input			data_pos;
input			data_neg;
input [1:0]		pad_pos_cnt;
input [1:0]		pad_neg_cnt;
input			dram_io_drive_enable;
input			dram_io_pad_enable;
input 			dram_io_ptr_clk_inv;
input			burst_length_four;
input			to_core;
input			testmode_l;
input			test_mode;
input			tp_out_type;
input			afo;




output			io_dram_data_in_hi;
output			io_dram_data_in;
output			dq_pad_clk_so;
output			to_pad;
output			oe;
output			afi;


wire [0:0]		pad_ptr0_pos;
wire [0:0]		pad_ptr1_pos;
wire [0:0]		pad_ptr2_pos;
wire [0:0]		pad_ptr3_pos;
wire			pad_pos_data;
wire			pad_neg_data;
wire			pad_data_clk_flip_out;
wire			pad_data_cap_clk;
wire			dq_pad_enable;
wire [1:0]		pad_ptr_pos0_in;
wire [1:0]		pad_ptr_pos0;
wire 			dram_io_ptr_clk_d1;






wire tclk = testmode_l ? ~clk : clk;



dff_s #(1)	flop_io_pad_clk_bit1(
		.din(dram_io_ptr_clk_inv),
		.q(dram_io_ptr_clk_d1),
		.clk(clk), 
		.si(dq_pad_clk_si), .so(dq_pad_clk_si0), .se(dq_pad_clk_se));

dff_s #(1)	flop_io_pad_enable_p(
		.din(dram_io_pad_enable),
		.q(dram_io_pad_enable_p_d1),
		.clk(clk), 
		.si(dq_pad_clk_si13), .so(dq_pad_clk_si1), .se(dq_pad_clk_se));

dff_s #(1)	flop_io_pad_enable_pn(
		.din(dram_io_pad_enable_p_d1),
		.q(dram_io_pad_enable_pn_d1),
		.clk(tclk), 
		.si(dq_pad_clk_si0), .so(dq_pad_clk_si13), .se(dq_pad_clk_se));

dff_s #(1)	flop_io_pad_enable_n(
		.din(dram_io_pad_enable),
		.q(dram_io_pad_enable_n_d1),
		.clk(tclk), 
		.si(dq_pad_clk_si14), .so(dq_pad_clk_si2), .se(dq_pad_clk_se));

dff_s #(1)	flop_io_pad_enable_np(
		.din(dram_io_pad_enable_n_d1),
		.q(dram_io_pad_enable_np_d1),
		.clk(clk), 
		.si(dq_pad_clk_si1), .so(dq_pad_clk_si14), .se(dq_pad_clk_se));


wire dq_pad_pos_neg_rd_en = dram_io_pad_enable_p_d1 | dram_io_pad_enable_pn_d1;
wire dq_pad_neg_pos_rd_en = dram_io_pad_enable_n_d1 | dram_io_pad_enable_np_d1;

wire dram_io_pad_enable_d1 = dram_io_ptr_clk_d1 ? dq_pad_neg_pos_rd_en : dq_pad_pos_neg_rd_en;
assign dq_pad_enable = dram_io_pad_enable_d1 | (pad_ptr_pos0[0] == 1'b1);



dff_s #(1)	flop_data_pos(
		.din(data_pos),
		.q(data_pos_d1),
		.clk(tclk), .si(dq_pad_clk_si2), .so(dq_pad_clk_si3), .se(dq_pad_clk_se));

dff_s #(1)	flop_data_neg(
		.din(data_neg),
		.q(data_neg_d1),
		.clk(clk), .si(dq_pad_clk_si4), .so(dq_pad_clk_si5), .se(dq_pad_clk_se)); 

wire data_out = dqs_read ? data_neg_d1 : data_pos_d1;



dff_s #(1)        flop_drive_dqs(
                .din(dram_io_drive_enable),
                .q(enable_q),
                .clk(clk), .si(dq_pad_clk_si5), .so(dq_pad_clk_so_clk), .se(dq_pad_clk_se)); 

dff_s #(1)        flop_drive_data(
                .din(enable_q),
                .q(enable_data),
                .clk(tclk), .si(dq_pad_clk_si3), .so(dq_pad_clk_si4), .se(dq_pad_clk_se));

wire output_enable = (enable_data & enable_q);




assign pad_ptr_pos0_in[1:0] = burst_length_four ? (
				dq_pad_enable ? pad_ptr_pos0 + 1'b1 : pad_ptr_pos0[1:0]) :
                             	(dram_io_pad_enable_d1 | ~(pad_ptr_pos0[1:0] == 2'b00)) ?
				pad_ptr_pos0 + 1'b1 : pad_ptr_pos0;



dffrl_async #(1) ff_ptr_pos0(
                .din(pad_ptr_pos0_in[0]),
                .q(pad_ptr_pos0[0]),
                .rst_l(arst_l & (rst_l | ~testmode_l)),
                .clk(~dqs_read), .se(dq_pad_clk_se), .si(dq_pad_clk_si15), .so(dq_pad_clkn_si0));

dffrl_async #(1) ff_ptr_pos1(
                .din(pad_ptr_pos0_in[1]),
                .q(pad_ptr_pos0[1]),
                .rst_l(arst_l & (rst_l | ~testmode_l)),
                .clk(~dqs_read), .se(dq_pad_clk_se), .si(dq_pad_clkn_si0), .so(dq_pad_clkn_si1));

assign pad_ptr0_pos[0] = pad_ptr_pos0 == 0;
assign pad_ptr1_pos[0] = pad_ptr_pos0 == 1;
assign pad_ptr2_pos[0] = pad_ptr_pos0 == 2;
assign pad_ptr3_pos[0] = pad_ptr_pos0 == 3;


dffe_s #(1)        ff_data_pos0_in0(
                .din(to_core),
                .q(dram_pad_data0),
		.en(pad_ptr0_pos[0]),
                .clk(dqs_read), .se(dq_pad_clk_se), .si(dq_pad_clk_si6), .so(dq_pad_clk_si7));
                
dffe_s #(1)        ff_data_pos1_in0(
                .din(to_core),
                .q(dram_pad_data1),
		.en(pad_ptr1_pos[0]),
                .clk(dqs_read), .se(dq_pad_clk_se), .si(dq_pad_clk_si7), .so(dq_pad_clk_si8));
                
dffe_s #(1)        ff_data_pos2_in0(
                .din(to_core),
                .q(dram_pad_data2),
                .en(pad_ptr2_pos[0]),
                .clk(dqs_read), .se(dq_pad_clk_se), .si(dq_pad_clk_si8), .so(dq_pad_clk_si9));
                
dffe_s #(1)        ff_data_pos3_in0(
                .din(to_core),
                .q(dram_pad_data3),
                .en(pad_ptr3_pos[0]),
                .clk(dqs_read), .se(dq_pad_clk_se), .si(dq_pad_clk_si9), .so(dq_pad_clk_si10));



dffe_s #(1)        ff_data_neg0_in0(
                .din(to_core),
                .q(dram_neg_pad_data0),
		.en(pad_ptr0_pos[0]),
                .clk(~dqs_read), .se(dq_pad_clk_se), .si(dq_pad_clkn_si1), .so(dq_pad_clkn_si2));

dffe_s #(1)        ff_data_neg1_in0(
                .din(to_core),
                .q(dram_neg_pad_data1),
		.en(pad_ptr1_pos[0]),
                .clk(~dqs_read), .se(dq_pad_clk_se), .si(dq_pad_clkn_si2), .so(dq_pad_clkn_si3));

dffe_s #(1)        ff_data_neg2_in0(
                .din(to_core),
                .q(dram_neg_pad_data2),
		.en(pad_ptr2_pos[0]),
                .clk(~dqs_read), .se(dq_pad_clk_se), .si(dq_pad_clkn_si3), .so(dq_pad_clkn_si4));

dffe_s #(1)        ff_data_neg3_in0(
                .din(to_core),
                .q(dram_neg_pad_data3),
		.en(pad_ptr3_pos[0]),
                .clk(~dqs_read), .se(dq_pad_clk_se), .si(dq_pad_clkn_si4), .so(dq_pad_clkn_so));

assign pad_pos_data = pad_pos_cnt[1:0] == 3 ? dram_pad_data2 : 
				 pad_pos_cnt[1:0] == 2 ? dram_pad_data1 :
				 pad_pos_cnt[1:0] == 1 ?  dram_pad_data0 : dram_pad_data3;
assign pad_neg_data = pad_neg_cnt[1:0] == 3 ?  dram_neg_pad_data2 : 
                                 pad_neg_cnt[1:0] == 2 ? dram_neg_pad_data1 :
                                 pad_neg_cnt[1:0] == 1 ?  dram_neg_pad_data0 : dram_neg_pad_data3;



dff_s #(1)      ff_data_pos_dqs(
                .din(pad_pos_data),
                .q(io_dram_data_in_hi),
                .clk(clk), .se(dq_pad_clk_se), .si(dq_pad_clk_so_clk), .so(dq_pad_clk_si11));

dff_s #(1)      ff_data_neg_dqs(
                .din(pad_neg_data),
                .q(io_dram_data_in),
                .clk(tclk), 
		.se(dq_pad_clk_se), .si(dq_pad_clk_si11), .so(dq_pad_clk_si12));



assign oe = test_mode ? tp_out_type : output_enable;
assign to_pad = test_mode ? afo : data_out;
assign afi = test_mode & to_core;




bw_u1_scanlg_2x lockup_latch_clk_dqs(
		.so(dq_pad_clk_si6), 
		.sd(dq_pad_clk_si12), 
		.ck(tclk), 
		.se(dq_pad_clk_se));

bw_u1_scanlg_2x lockup_latch_dqs_inv_dqs(
		.so(dq_pad_clk_si15), 
		.sd(dq_pad_clk_si10), 
		.ck(dqs_read), 
		.se(dq_pad_clk_se));



dff_ns #(1)      ff_dummy_scan(
                .din(dq_pad_clkn_so),
                .q(dq_pad_clk_so),
                .clk(clk)); 

endmodule