data/full_repos/permissive/502135797/Lab1_Feb_11_2022/Code/GenvarDECO_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab1_Feb_11_2022/Code/GenvarDECO_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab1_Feb_11_2022/Code/GenvarDECO_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab1_Feb_11_2022/Code/GenvarDECO_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab1_Feb_11_2022/Code/GenvarDECO_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #100\n        ^\n%Error: data/full_repos/permissive/502135797/Lab1_Feb_11_2022/Code/GenvarDECO_tb.v:35: Cannot find file containing module: \'GenvarDECO\'\n  GenvarDECO\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502135797/Lab1_Feb_11_2022/Code,data/full_repos/permissive/502135797/GenvarDECO\n             data/full_repos/permissive/502135797/Lab1_Feb_11_2022/Code,data/full_repos/permissive/502135797/GenvarDECO.v\n             data/full_repos/permissive/502135797/Lab1_Feb_11_2022/Code,data/full_repos/permissive/502135797/GenvarDECO.sv\n             GenvarDECO\n             GenvarDECO.v\n             GenvarDECO.sv\n             obj_dir/GenvarDECO\n             obj_dir/GenvarDECO.v\n             obj_dir/GenvarDECO.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module GenvarDECO_tb
   #(parameter s=8)
    (

    );
    
    reg [2:0] i_tb;
    reg e_tb;
    
    wire[7:0] p_tb;
    
    
  GenvarDECO
  #(
        .n(s) 
   )
   GenvarDECO_TB
(
    .i(i_tb),
    .e(e_tb),
    .p(p_tb)
     
);   
    initial
        begin:TSTB
        e_tb=1;
        i_tb=1;
        #10
        i_tb=2; 
        #10
        i_tb=5;
        #10
        i_tb=6;       
        #100
        $finish;
        end
    
      
endmodule
module GenvarDECO_tb
   #(parameter s=8)
    (

    );

    
    reg [2:0] i_tb;
    reg e_tb;
    
    wire[7:0] p_tb;
    
    
  GenvarDECO
  #(
        .n(s) 
   )
   GenvarDECO_TB
(
    .i(i_tb),
    .e(e_tb),
    .p(p_tb)
     
);   
    initial
        begin:TSTB
        e_tb=1;
        i_tb=1;
        #10
        i_tb=2; 
        #10
        i_tb=5;
        #10
        i_tb=6;       
        #100
        $finish;
        end
    
      
endmodule