data/full_repos/permissive/488739248/rtl/ym3526/jtopl_acc.v
1: b"%Error: data/full_repos/permissive/488739248/rtl/ym3526/jtopl_acc.v:39: Cannot find file containing module: 'jtopl_single_acc'\njtopl_single_acc  u_acc(\n^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/488739248/rtl/ym3526,data/full_repos/permissive/488739248/jtopl_single_acc\n             data/full_repos/permissive/488739248/rtl/ym3526,data/full_repos/permissive/488739248/jtopl_single_acc.v\n             data/full_repos/permissive/488739248/rtl/ym3526,data/full_repos/permissive/488739248/jtopl_single_acc.sv\n             jtopl_single_acc\n             jtopl_single_acc.v\n             jtopl_single_acc.sv\n             obj_dir/jtopl_single_acc\n             obj_dir/jtopl_single_acc.v\n             obj_dir/jtopl_single_acc.sv\n%Error: Exiting due to 1 error(s)\n"
module jtopl_acc(
    input wire               rst,
    input wire               clk,
    input wire               cenop,
    input wire signed [12:0] op_result,
    input wire               zero,
    input wire               op,
    input wire               con,
    output wire signed [15:0] snd
);

wire sum_en;

assign sum_en = op | con;


jtopl_single_acc  u_acc(
    .clk        ( clk       ),
    .cenop      ( cenop     ),
    .op_result  ( op_result ),
    .sum_en     ( sum_en    ),
    .zero       ( zero      ),
    .snd        ( snd       )
);

endmodule
module jtopl_acc(
    input wire               rst,
    input wire               clk,
    input wire               cenop,
    input wire signed [12:0] op_result,
    input wire               zero,
    input wire               op,
    input wire               con,
    output wire signed [15:0] snd
);


wire sum_en;

assign sum_en = op | con;


jtopl_single_acc  u_acc(
    .clk        ( clk       ),
    .cenop      ( cenop     ),
    .op_result  ( op_result ),
    .sum_en     ( sum_en    ),
    .zero       ( zero      ),
    .snd        ( snd       )
);

endmodule