data/full_repos/permissive/525825809/oc-accel/hardware/hdl/core/oc_function.v
1: b'%Error: data/full_repos/permissive/525825809/oc-accel/hardware/hdl/core/oc_function.v:18: Cannot find include file: snap_global_vars.v\n`include "snap_global_vars.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/525825809/oc-accel/hardware/hdl/core,data/full_repos/permissive/525825809/snap_global_vars.v\n             data/full_repos/permissive/525825809/oc-accel/hardware/hdl/core,data/full_repos/permissive/525825809/snap_global_vars.v.v\n             data/full_repos/permissive/525825809/oc-accel/hardware/hdl/core,data/full_repos/permissive/525825809/snap_global_vars.v.sv\n             snap_global_vars.v\n             snap_global_vars.v.v\n             snap_global_vars.v.sv\n             obj_dir/snap_global_vars.v\n             obj_dir/snap_global_vars.v.v\n             obj_dir/snap_global_vars.v.sv\n%Error: Exiting due to 1 error(s)\n'
module oc_function (




    input          clock_tlx
  , input          clock_afu                               
  , input          reset                        


  , input    [7:0] cfg_bus


  , input    [4:0] ro_device
  , input    [2:0] ro_function
    




  , input          tlx_afu_ready


  , output [  6:0] afu_tlx_cmd_initial_credit
  , output         afu_tlx_cmd_credit
  , input          tlx_afu_cmd_valid
  , input  [  7:0] tlx_afu_cmd_opcode
  , input  [  1:0] tlx_afu_cmd_dl
  , input          tlx_afu_cmd_end
  , input  [ 63:0] tlx_afu_cmd_pa
  , input  [  3:0] tlx_afu_cmd_flag
  , input          tlx_afu_cmd_os
  , input  [ 15:0] tlx_afu_cmd_capptag
  , input  [  2:0] tlx_afu_cmd_pl
  , input  [ 63:0] tlx_afu_cmd_be


  , output [  6:0] afu_tlx_resp_initial_credit
  , output         afu_tlx_resp_credit
  , input          tlx_afu_resp_valid
  , input  [  7:0] tlx_afu_resp_opcode
  , input  [ 15:0] tlx_afu_resp_afutag
  , input  [  3:0] tlx_afu_resp_code
  , input  [  5:0] tlx_afu_resp_pg_size
  , input  [  1:0] tlx_afu_resp_dl
  , input  [  1:0] tlx_afu_resp_dp
  , input  [ 23:0] tlx_afu_resp_host_tag
  , input  [  3:0] tlx_afu_resp_cache_state
  , input  [ 17:0] tlx_afu_resp_addr_tag


  , output         afu_tlx_cmd_rd_req
  , output [  2:0] afu_tlx_cmd_rd_cnt
  , input          tlx_afu_cmd_data_valid
  , input          tlx_afu_cmd_data_bdi
  , input  [511:0] tlx_afu_cmd_data_bus


  , output         afu_tlx_resp_rd_req
  , output [  2:0] afu_tlx_resp_rd_cnt
  , input          tlx_afu_resp_data_valid
  , input          tlx_afu_resp_data_bdi
  , input  [511:0] tlx_afu_resp_data_bus









  , input  [  3:0] tlx_afu_cmd_initial_credit
  , input  [  3:0] tlx_afu_resp_initial_credit
  , input  [  5:0] tlx_afu_cmd_data_initial_credit
  , input  [  5:0] tlx_afu_resp_data_initial_credit



  , input          tlx_afu_cmd_credit                
  , output         afu_tlx_cmd_valid                 
  , output [  7:0] afu_tlx_cmd_opcode                
  , output [ 11:0] afu_tlx_cmd_actag                 
  , output [  3:0] afu_tlx_cmd_stream_id             
  , output [ 67:0] afu_tlx_cmd_ea_or_obj             
  , output [ 15:0] afu_tlx_cmd_afutag               
  , output [  1:0] afu_tlx_cmd_dl                    
  , output [  2:0] afu_tlx_cmd_pl                    
  , output         afu_tlx_cmd_os                    
  , output [ 63:0] afu_tlx_cmd_be                    
  , output [  3:0] afu_tlx_cmd_flag                  
  , output         afu_tlx_cmd_endian                
  , output [ 15:0] afu_tlx_cmd_bdf
  , output [ 19:0] afu_tlx_cmd_pasid                 
  , output [  5:0] afu_tlx_cmd_pg_size               


  , input          tlx_afu_cmd_data_credit           
  , output         afu_tlx_cdata_valid               
  , output [511:0] afu_tlx_cdata_bus                 
  , output         afu_tlx_cdata_bdi


  , input          tlx_afu_resp_credit               
  , output         afu_tlx_resp_valid                
  , output [  7:0] afu_tlx_resp_opcode               
  , output [  1:0] afu_tlx_resp_dl   
  , output [ 15:0] afu_tlx_resp_capptag          
  , output [  1:0] afu_tlx_resp_dp                   
  , output [  3:0] afu_tlx_resp_code                 


  , input          tlx_afu_resp_data_credit          
  , output         afu_tlx_rdata_valid               
  , output [511:0] afu_tlx_rdata_bus                 
  , output         afu_tlx_rdata_bdi





  , input    [2:0] cfg_function
  , input    [1:0] cfg_portnum                  
  , input   [11:0] cfg_addr                     
  , input   [31:0] cfg_wdata                    
  , output  [31:0] cfg_f1_rdata               
  , output         cfg_f1_rdata_vld            
  , input          cfg_wr_1B                    
  , input          cfg_wr_2B                    
  , input          cfg_wr_4B                    
  , input          cfg_rd                       
  , output         cfg_f1_bad_op_or_align       
  , output         cfg_f1_addr_not_implemented  






  , output         cfg_f1_octrl00_fence_afu


  , input    [3:0] cfg_f0_otl0_long_backoff_timer
  , input    [3:0] cfg_f0_otl0_short_backoff_timer


  , input          vpd_err_unimplemented_addr
  , input          cfg0_cff_fifo_overflow
  , input          cfg1_cff_fifo_overflow
  , input          cfg0_rff_fifo_overflow
  , input          cfg1_rff_fifo_overflow
  , input  [127:0] cfg_errvec
  , input          cfg_errvec_valid


  , output         cfg_f1_octrl00_resync_credits
  
  

    ,input [31:0] f1_csh_expansion_rom_bar       
    ,input [15:0] f1_csh_subsystem_id            
    ,input [15:0] f1_csh_subsystem_vendor_id     
    ,input [63:0] f1_csh_mmio_bar0_size          
    ,input [63:0] f1_csh_mmio_bar1_size          
    ,input [63:0] f1_csh_mmio_bar2_size          
    ,input        f1_csh_mmio_bar0_prefetchable  
    ,input        f1_csh_mmio_bar1_prefetchable  
    ,input        f1_csh_mmio_bar2_prefetchable  
    ,input  [4:0] f1_pasid_max_pasid_width       
    ,input  [7:0] f1_ofunc_reset_duration        
    ,input        f1_ofunc_afu_present           
    ,input  [4:0] f1_ofunc_max_afu_index         
    ,input  [7:0] f1_octrl00_reset_duration      
    ,input  [5:0] f1_octrl00_afu_control_index   
    ,input  [4:0] f1_octrl00_pasid_len_supported 
    ,input        f1_octrl00_metadata_supported  
    ,input [11:0] f1_octrl00_actag_len_supported 

  `ifdef ENABLE_DDR 
  `ifdef AD9V3
  


    , input                  c0_sys_clk_p
    , input                  c0_sys_clk_n
    , output  [16 : 0]       c0_ddr4_adr
    , output  [1 : 0]        c0_ddr4_ba
    , output  [0 : 0]        c0_ddr4_cke
    , output  [0 : 0]        c0_ddr4_cs_n
    , inout   [8 : 0]        c0_ddr4_dm_dbi_n
    , inout   [71 : 0]       c0_ddr4_dq
    , inout   [8 : 0]        c0_ddr4_dqs_c
    , inout   [8 : 0]        c0_ddr4_dqs_t
    , output  [0 : 0]        c0_ddr4_odt
    , output  [1 : 0]        c0_ddr4_bg
    , output                 c0_ddr4_reset_n
    , output                 c0_ddr4_act_n
    , output  [0 : 0]        c0_ddr4_ck_c
    , output  [0 : 0]        c0_ddr4_ck_t
   `endif
   `ifdef BW250SOC


    , input                  c0_sys_clk_p
    , input                  c0_sys_clk_n
    , output  [16 : 0]       c0_ddr4_adr
    , output  [1 : 0]        c0_ddr4_ba
    , output  [0 : 0]        c0_ddr4_cke
    , output  [0 : 0]        c0_ddr4_cs_n
    , inout   [8 : 0]        c0_ddr4_dm_dbi_n
    , inout   [71 : 0]       c0_ddr4_dq
    , inout   [8 : 0]        c0_ddr4_dqs_c
    , inout   [8 : 0]        c0_ddr4_dqs_t
    , output  [0 : 0]        c0_ddr4_odt
    , output  [0 : 0]        c0_ddr4_bg
    , output                 c0_ddr4_reset_n
    , output                 c0_ddr4_act_n
    , output  [0 : 0]        c0_ddr4_ck_c
    , output  [0 : 0]        c0_ddr4_ck_t
   `endif
   `endif

`ifdef ENABLE_ETHERNET
`ifndef ENABLE_ETH_LOOP_BACK
    , input                  gt_ref_clk_n
    , input                  gt_ref_clk_p
    , input                  gt_rx_gt_port_0_n
    , input                  gt_rx_gt_port_0_p
    , input                  gt_rx_gt_port_1_n
    , input                  gt_rx_gt_port_1_p
    , input                  gt_rx_gt_port_2_n
    , input                  gt_rx_gt_port_2_p
    , input                  gt_rx_gt_port_3_n
    , input                  gt_rx_gt_port_3_p
    , output                 gt_tx_gt_port_0_n
    , output                 gt_tx_gt_port_0_p
    , output                 gt_tx_gt_port_1_n
    , output                 gt_tx_gt_port_1_p
    , output                 gt_tx_gt_port_2_n
    , output                 gt_tx_gt_port_2_p
    , output                 gt_tx_gt_port_3_n
    , output                 gt_tx_gt_port_3_p
`endif
`endif

`ifdef ENABLE_9H3_LED
     , output                 user_led_a0
     , output                 user_led_a1
     , output                 user_led_g0
     , output                 user_led_g1
`endif
`ifdef ENABLE_9H3_EEPROM
     , inout                  eeprom_scl
     , inout                  eeprom_sda
     , output                 eeprom_wp
`endif
`ifdef ENABLE_9H3_AVR
    , input                  avr_rx
    , output                 avr_tx
    , input                  avr_ck
`endif
);






  wire  [5:0] cfg_desc_afu_index
; wire [30:0] cfg_desc_offset
; wire        cfg_desc_cmd_valid
; wire [31:0] desc_cfg_data
; wire        desc_cfg_data_valid
; wire        desc_cfg_echo_cmd_valid
; wire [31:0] desc0_cfg_data
; wire        desc0_cfg_data_valid
; wire        desc0_cfg_echo_cmd_valid
 

; wire        reset_afu00
; wire        resync_credits_afu00
; 


wire [31:0] f1_ro_csh_expansion_rom_bar       ;
wire [15:0] f1_ro_csh_subsystem_id            ;
wire [15:0] f1_ro_csh_subsystem_vendor_id     ;
wire [63:0] f1_ro_csh_mmio_bar0_size          ;
wire [63:0] f1_ro_csh_mmio_bar1_size          ;
wire [63:0] f1_ro_csh_mmio_bar2_size          ;
wire        f1_ro_csh_mmio_bar0_prefetchable  ;
wire        f1_ro_csh_mmio_bar1_prefetchable  ;
wire        f1_ro_csh_mmio_bar2_prefetchable  ;
wire  [4:0] f1_ro_pasid_max_pasid_width       ;
wire  [7:0] f1_ro_ofunc_reset_duration        ;
wire        f1_ro_ofunc_afu_present           ;
wire  [4:0] f1_ro_ofunc_max_afu_index         ;
wire  [7:0] f1_ro_octrl00_reset_duration      ;
wire  [5:0] f1_ro_octrl00_afu_control_index   ;
wire  [4:0] f1_ro_octrl00_pasid_len_supported ;
wire        f1_ro_octrl00_metadata_supported  ;
wire [11:0] f1_ro_octrl00_actag_len_supported ;


assign f1_ro_csh_expansion_rom_bar       = f1_csh_expansion_rom_bar      ;
assign f1_ro_csh_subsystem_id            = f1_csh_subsystem_id           ;
assign f1_ro_csh_subsystem_vendor_id     = f1_csh_subsystem_vendor_id    ;
assign f1_ro_csh_mmio_bar0_size          = f1_csh_mmio_bar0_size         ;
assign f1_ro_csh_mmio_bar1_size          = f1_csh_mmio_bar1_size         ;
assign f1_ro_csh_mmio_bar2_size          = f1_csh_mmio_bar2_size         ;
assign f1_ro_csh_mmio_bar0_prefetchable  = f1_csh_mmio_bar0_prefetchable ;
assign f1_ro_csh_mmio_bar1_prefetchable  = f1_csh_mmio_bar1_prefetchable ;
assign f1_ro_csh_mmio_bar2_prefetchable  = f1_csh_mmio_bar2_prefetchable ;
assign f1_ro_pasid_max_pasid_width       = f1_pasid_max_pasid_width      ;
assign f1_ro_ofunc_reset_duration        = f1_ofunc_reset_duration       ;
assign f1_ro_ofunc_afu_present           = f1_ofunc_afu_present          ;
assign f1_ro_ofunc_max_afu_index         = f1_ofunc_max_afu_index        ;
assign f1_ro_octrl00_reset_duration      = f1_octrl00_reset_duration     ;
assign f1_ro_octrl00_afu_control_index   = f1_octrl00_afu_control_index  ;
assign f1_ro_octrl00_pasid_len_supported = f1_octrl00_pasid_len_supported;
assign f1_ro_octrl00_metadata_supported  = f1_octrl00_metadata_supported ;
assign f1_ro_octrl00_actag_len_supported = f1_octrl00_actag_len_supported;







  wire         afu_f1_cfg_terminate_in_progress


; wire         cfg_f1_csh_memory_space
; wire  [63:0] cfg_f1_csh_mmio_bar0
; wire  [63:0] cfg_f1_csh_mmio_bar1
; wire  [63:0] cfg_f1_csh_mmio_bar2
; wire  [31:0] cfg_f1_csh_expansion_ROM_bar
; wire         cfg_f1_csh_expansion_ROM_enable
; wire         cfg_f1_ofunc_function_reset      
; wire  [11:0] cfg_f1_ofunc_func_actag_base
; wire  [11:0] cfg_f1_ofunc_func_actag_len_enab
; wire   [5:0] cfg_f1_octrl00_afu_control_index 
; wire   [3:0] cfg_f1_octrl00_afu_unique              

; wire         cfg_f1_octrl00_enable_afu           
; wire         cfg_f1_octrl00_reset_afu            
; wire         cfg_f1_octrl00_terminate_valid      
; wire  [19:0] cfg_f1_octrl00_terminate_pasid      
; wire   [4:0] cfg_f1_octrl00_pasid_length_enabled
; wire         cfg_f1_octrl00_metadata_enabled
; wire   [2:0] cfg_f1_octrl00_host_tag_run_length
; wire  [19:0] cfg_f1_octrl00_pasid_base
; wire  [11:0] cfg_f1_octrl00_afu_actag_len_enab
; wire  [11:0] cfg_f1_octrl00_afu_actag_base
;

wire   cfg_f1_reset;
assign cfg_f1_reset = (reset == 1'b1 || cfg_f1_ofunc_function_reset == 1'b1) ? 1'b1 : 1'b0;

cfg_func1 cfg_f1
    (

      .clock                               ( clock_tlx ),
      .reset                               ( cfg_f1_reset ),
      .device_reset                        ( reset ),
                                                                                        


      .cfg_ro_csh_device_id                ( 16'h062B ),
      .cfg_ro_csh_vendor_id                ( 16'h1014 ),
      .cfg_ro_csh_class_code               ( 24'h120000 ),
      .cfg_ro_csh_revision_id              (  8'h00 ),
      .cfg_ro_csh_multi_function           (  1'b1 ),
      .cfg_ro_csh_mmio_bar0_size           ( f1_ro_csh_mmio_bar0_size         ),
      .cfg_ro_csh_mmio_bar1_size           ( f1_ro_csh_mmio_bar1_size         ),
      .cfg_ro_csh_mmio_bar2_size           ( f1_ro_csh_mmio_bar2_size         ),
      .cfg_ro_csh_mmio_bar0_prefetchable   ( f1_ro_csh_mmio_bar0_prefetchable ),
      .cfg_ro_csh_mmio_bar1_prefetchable   ( f1_ro_csh_mmio_bar1_prefetchable ),
      .cfg_ro_csh_mmio_bar2_prefetchable   ( f1_ro_csh_mmio_bar2_prefetchable ),
      .cfg_ro_csh_subsystem_id             ( f1_ro_csh_subsystem_id           ),
      .cfg_ro_csh_subsystem_vendor_id      ( f1_ro_csh_subsystem_vendor_id    ),
      .cfg_ro_csh_expansion_rom_bar        ( f1_ro_csh_expansion_rom_bar      ),
                                                                                        

      .cfg_ro_pasid_max_pasid_width        ( f1_ro_pasid_max_pasid_width ),
                                                                                        

      .cfg_ro_ofunc_reset_duration         ( f1_ro_ofunc_reset_duration ),
      .cfg_ro_ofunc_afu_present            ( f1_ro_ofunc_afu_present    ),
      .cfg_ro_ofunc_max_afu_index          ( f1_ro_ofunc_max_afu_index  ),
                                                                                        

      .cfg_ro_octrl00_reset_duration       ( f1_ro_octrl00_reset_duration      ),
      .cfg_ro_octrl00_afu_control_index    ( f1_ro_octrl00_afu_control_index   ),
      .cfg_ro_octrl00_pasid_len_supported  ( f1_ro_octrl00_pasid_len_supported ),
      .cfg_ro_octrl00_metadata_supported   ( f1_ro_octrl00_metadata_supported  ),
      .cfg_ro_octrl00_actag_len_supported  ( f1_ro_octrl00_actag_len_supported ),
                                                                                        

      .cfg_ro_function                     ( ro_function ),
                                                                                        

      .cfg_function                        ( cfg_function[2:0] ),
      .cfg_portnum                         ( cfg_portnum[1:0] ),
      .cfg_addr                            ( cfg_addr[11:0] ),
      .cfg_wdata                           ( cfg_wdata[31:0] ),
      .cfg_rdata                           ( cfg_f1_rdata[31:0] ),
      .cfg_rdata_vld                       ( cfg_f1_rdata_vld ),
      .cfg_wr_1B                           ( cfg_wr_1B ),
      .cfg_wr_2B                           ( cfg_wr_2B ),
      .cfg_wr_4B                           ( cfg_wr_4B ),
      .cfg_rd                              ( cfg_rd ),
      .cfg_bad_op_or_align                 ( cfg_f1_bad_op_or_align ),
      .cfg_addr_not_implemented            ( cfg_f1_addr_not_implemented ),
                                                                                        

      .cfg_octrl00_terminate_in_progress   ( afu_f1_cfg_terminate_in_progress ),
                                                                                        


      .cfg_csh_memory_space                ( cfg_f1_csh_memory_space ),
      .cfg_csh_mmio_bar0                   ( cfg_f1_csh_mmio_bar0[63:0] ),
      .cfg_csh_mmio_bar1                   ( cfg_f1_csh_mmio_bar1[63:0] ),
      .cfg_csh_mmio_bar2                   ( cfg_f1_csh_mmio_bar2[63:0] ),
      .cfg_csh_expansion_ROM_bar           ( cfg_f1_csh_expansion_ROM_bar[31:0] ),
      .cfg_csh_expansion_ROM_enable        ( cfg_f1_csh_expansion_ROM_enable ),
                                                                                        

      .cfg_ofunc_function_reset            ( cfg_f1_ofunc_function_reset ),
      .cfg_ofunc_func_actag_base           ( cfg_f1_ofunc_func_actag_base[11:0] ),
      .cfg_ofunc_func_actag_len_enab       ( cfg_f1_ofunc_func_actag_len_enab[11:0] ),
                                                                                        

      .cfg_octrl00_afu_control_index       ( cfg_f1_octrl00_afu_control_index[5:0] ),
      .cfg_octrl00_afu_unique              ( cfg_f1_octrl00_afu_unique[3:0] ),
      .cfg_octrl00_fence_afu               ( cfg_f1_octrl00_fence_afu ),
      .cfg_octrl00_enable_afu              ( cfg_f1_octrl00_enable_afu ),
      .cfg_octrl00_reset_afu               ( cfg_f1_octrl00_reset_afu ),
      .cfg_octrl00_terminate_valid         ( cfg_f1_octrl00_terminate_valid ),
      .cfg_octrl00_terminate_pasid         ( cfg_f1_octrl00_terminate_pasid[19:0] ),
      .cfg_octrl00_pasid_length_enabled    ( cfg_f1_octrl00_pasid_length_enabled[4:0] ),
      .cfg_octrl00_metadata_enabled        ( cfg_f1_octrl00_metadata_enabled ),
      .cfg_octrl00_host_tag_run_length     ( cfg_f1_octrl00_host_tag_run_length[2:0] ),
      .cfg_octrl00_pasid_base              ( cfg_f1_octrl00_pasid_base[19:0] ),
      .cfg_octrl00_afu_actag_base          ( cfg_f1_octrl00_afu_actag_base[11:0] ),
      .cfg_octrl00_afu_actag_len_enab      ( cfg_f1_octrl00_afu_actag_len_enab[11:0] ),


      .cfg_desc_afu_index                  ( cfg_desc_afu_index[5:0] ),
      .cfg_desc_offset                     ( cfg_desc_offset[30:0] ),
      .cfg_desc_cmd_valid                  ( cfg_desc_cmd_valid ),
      .desc_cfg_data                       ( desc_cfg_data[31:0] ),
      .desc_cfg_data_valid                 ( desc_cfg_data_valid ),
      .desc_cfg_echo_cmd_valid             ( desc_cfg_echo_cmd_valid )

    );





assign desc_cfg_echo_cmd_valid  = desc0_cfg_echo_cmd_valid ;
assign desc_cfg_data_valid      = desc0_cfg_data_valid     ;
assign desc_cfg_data            = desc0_cfg_data           ;


assign cfg_f1_octrl00_resync_credits = cfg_f1_octrl00_afu_unique[0];
assign resync_credits_afu00          = cfg_f1_octrl00_afu_unique[0];





assign reset_afu00 = ( reset == 1'b1        || 
                       cfg_f1_reset == 1'b1 ||
                      (cfg_f1_octrl00_reset_afu == 1'b1 && cfg_f1_octrl00_afu_control_index == 6'b000000) ) ? 1'b1 : 1'b0; 

wire afu_tlx_fatal_error;

framework_afu  fw_afu 
    (

      .clock_tlx                           ( clock_tlx),
      .clock_afu                           ( clock_afu ),
      .reset                               ( reset_afu00 ),
                                                                                         
  `ifdef ENABLE_DDR 
  `ifdef AD9V3
  

      .c0_sys_clk_p     ( c0_sys_clk_p     ) ,
      .c0_sys_clk_n     ( c0_sys_clk_n     ) ,
      .c0_ddr4_adr      ( c0_ddr4_adr      ) ,
      .c0_ddr4_ba       ( c0_ddr4_ba       ) ,
      .c0_ddr4_cke      ( c0_ddr4_cke      ) ,
      .c0_ddr4_cs_n     ( c0_ddr4_cs_n     ) ,
      .c0_ddr4_dm_dbi_n ( c0_ddr4_dm_dbi_n ) ,
      .c0_ddr4_dq       ( c0_ddr4_dq       ) ,
      .c0_ddr4_dqs_c    ( c0_ddr4_dqs_c    ) ,
      .c0_ddr4_dqs_t    ( c0_ddr4_dqs_t    ) ,
      .c0_ddr4_odt      ( c0_ddr4_odt      ) ,
      .c0_ddr4_bg       ( c0_ddr4_bg       ) ,
      .c0_ddr4_reset_n  ( c0_ddr4_reset_n  ) ,
      .c0_ddr4_act_n    ( c0_ddr4_act_n    ) ,
      .c0_ddr4_ck_c     ( c0_ddr4_ck_c     ) ,
      .c0_ddr4_ck_t     ( c0_ddr4_ck_t     ) ,
   `endif
   `ifdef BW250SOC
  

      .c0_sys_clk_p     ( c0_sys_clk_p     ) ,
      .c0_sys_clk_n     ( c0_sys_clk_n     ) ,
      .c0_ddr4_adr      ( c0_ddr4_adr      ) ,
      .c0_ddr4_ba       ( c0_ddr4_ba       ) ,
      .c0_ddr4_cke      ( c0_ddr4_cke      ) ,
      .c0_ddr4_cs_n     ( c0_ddr4_cs_n     ) ,
      .c0_ddr4_dm_dbi_n ( c0_ddr4_dm_dbi_n ) ,
      .c0_ddr4_dq       ( c0_ddr4_dq       ) ,
      .c0_ddr4_dqs_c    ( c0_ddr4_dqs_c    ) ,
      .c0_ddr4_dqs_t    ( c0_ddr4_dqs_t    ) ,
      .c0_ddr4_odt      ( c0_ddr4_odt      ) ,
      .c0_ddr4_bg       ( c0_ddr4_bg       ) ,
      .c0_ddr4_reset_n  ( c0_ddr4_reset_n  ) ,
      .c0_ddr4_act_n    ( c0_ddr4_act_n    ) ,
      .c0_ddr4_ck_c     ( c0_ddr4_ck_c     ) ,
      .c0_ddr4_ck_t     ( c0_ddr4_ck_t     ) ,
   `endif

   `endif
  `ifdef ENABLE_ETHERNET
  `ifndef ENABLE_ETH_LOOP_BACK
      .gt_ref_clk_n      ( gt_ref_clk_n       ),
      .gt_ref_clk_p      ( gt_ref_clk_p       ),
      .gt_rx_gt_port_0_n ( gt_rx_gt_port_0_n  ),
      .gt_rx_gt_port_0_p ( gt_rx_gt_port_0_p  ),
      .gt_rx_gt_port_1_n ( gt_rx_gt_port_1_n  ),
      .gt_rx_gt_port_1_p ( gt_rx_gt_port_1_p  ),
      .gt_rx_gt_port_2_n ( gt_rx_gt_port_2_n  ),
      .gt_rx_gt_port_2_p ( gt_rx_gt_port_2_p  ),
      .gt_rx_gt_port_3_n ( gt_rx_gt_port_3_n  ),
      .gt_rx_gt_port_3_p ( gt_rx_gt_port_3_p  ),
      .gt_tx_gt_port_0_n ( gt_tx_gt_port_0_n  ),
      .gt_tx_gt_port_0_p ( gt_tx_gt_port_0_p  ),
      .gt_tx_gt_port_1_n ( gt_tx_gt_port_1_n  ),
      .gt_tx_gt_port_1_p ( gt_tx_gt_port_1_p  ),
      .gt_tx_gt_port_2_n ( gt_tx_gt_port_2_n  ),
      .gt_tx_gt_port_2_p ( gt_tx_gt_port_2_p  ),
      .gt_tx_gt_port_3_n ( gt_tx_gt_port_3_n  ),
      .gt_tx_gt_port_3_p ( gt_tx_gt_port_3_p  ),
   `endif
   `endif

   `ifdef ENABLE_9H3_LED
      .user_led_a0     ( user_led_a0        ),
      .user_led_a1     ( user_led_a1        ),
      .user_led_g0     ( user_led_g0        ),
      .user_led_g1     ( user_led_g1        ),
   `endif
   `ifdef ENABLE_9H3_EEPROM
      .eeprom_scl      (eeprom_scl          ),
      .eeprom_sda      (eeprom_sda          ),
      .eeprom_wp       (eeprom_wp           ),
   `endif
   `ifdef ENABLE_9H3_AVR
      .avr_rx          (avr_rx              ),
      .avr_tx          (avr_tx              ),
      .avr_ck          (avr_ck              ),
    `endif


      .afu_index                           ( 6'b000000 ),
                                                                                         

      .tlx_afu_ready                       ( tlx_afu_ready ),
      .tlx_afu_cmd_valid                   ( tlx_afu_cmd_valid ),
      .tlx_afu_cmd_opcode                  ( tlx_afu_cmd_opcode[7:0] ),
      .tlx_afu_cmd_capptag                 ( tlx_afu_cmd_capptag[15:0] ),
      .tlx_afu_cmd_dl                      ( tlx_afu_cmd_dl[1:0] ),
      .tlx_afu_cmd_pl                      ( tlx_afu_cmd_pl[2:0] ),
      .tlx_afu_cmd_be                      ( tlx_afu_cmd_be[63:0] ),
      .tlx_afu_cmd_end                     ( tlx_afu_cmd_end ),
      .tlx_afu_cmd_pa                      ( tlx_afu_cmd_pa[63:0] ),
      .tlx_afu_cmd_flag                    ( tlx_afu_cmd_flag[3:0] ),
      .tlx_afu_cmd_os                      ( tlx_afu_cmd_os ),
                                                                                         
      .afu_tlx_cmd_rd_req                  ( afu_tlx_cmd_rd_req ),
      .afu_tlx_cmd_rd_cnt                  ( afu_tlx_cmd_rd_cnt[2:0] ),
                                                                                         
      .tlx_afu_cmd_data_valid              ( tlx_afu_cmd_data_valid ),
      .tlx_afu_cmd_data_bdi                ( tlx_afu_cmd_data_bdi ),
      .tlx_afu_cmd_data_bus                ( tlx_afu_cmd_data_bus[511:0] ),
                                                                                         
      .afu_tlx_cmd_credit                  ( afu_tlx_cmd_credit ),
      .afu_tlx_cmd_initial_credit          ( afu_tlx_cmd_initial_credit[6:0] ),
                                                                                         

      .afu_tlx_resp_valid                  ( afu_tlx_resp_valid ),
      .afu_tlx_resp_opcode                 ( afu_tlx_resp_opcode[7:0] ),
      .afu_tlx_resp_dl                     ( afu_tlx_resp_dl[1:0] ),
      .afu_tlx_resp_capptag                ( afu_tlx_resp_capptag[15:0] ),
      .afu_tlx_resp_dp                     ( afu_tlx_resp_dp[1:0] ),
      .afu_tlx_resp_code                   ( afu_tlx_resp_code[3:0] ),
                                                                                         
      .afu_tlx_rdata_valid                 ( afu_tlx_rdata_valid ),
      .afu_tlx_rdata_bdi                   ( afu_tlx_rdata_bdi ),
      .afu_tlx_rdata_bus                   ( afu_tlx_rdata_bus[511:0] ),
                                                                                         
      .tlx_afu_resp_credit                 ( tlx_afu_resp_credit ),
      .tlx_afu_resp_data_credit            ( tlx_afu_resp_data_credit ),
                                                                                         

      .afu_tlx_cmd_valid                   ( afu_tlx_cmd_valid ),
      .afu_tlx_cmd_opcode                  ( afu_tlx_cmd_opcode[7:0] ),
      .afu_tlx_cmd_actag                   ( afu_tlx_cmd_actag[11:0] ),
      .afu_tlx_cmd_stream_id               ( afu_tlx_cmd_stream_id[3:0] ),
      .afu_tlx_cmd_ea_or_obj               ( afu_tlx_cmd_ea_or_obj[67:0] ),
      .afu_tlx_cmd_afutag                  ( afu_tlx_cmd_afutag[15:0] ),
      .afu_tlx_cmd_dl                      ( afu_tlx_cmd_dl[1:0] ),
      .afu_tlx_cmd_pl                      ( afu_tlx_cmd_pl[2:0] ),
      .afu_tlx_cmd_os                      ( afu_tlx_cmd_os ),
      .afu_tlx_cmd_be                      ( afu_tlx_cmd_be[63:0] ),
      .afu_tlx_cmd_flag                    ( afu_tlx_cmd_flag[3:0] ),
      .afu_tlx_cmd_endian                  ( afu_tlx_cmd_endian ),
      .afu_tlx_cmd_bdf                     ( afu_tlx_cmd_bdf[15:0] ),
      .afu_tlx_cmd_pasid                   ( afu_tlx_cmd_pasid[19:0] ),
      .afu_tlx_cmd_pg_size                 ( afu_tlx_cmd_pg_size[5:0] ),
                                                                                         
      .afu_tlx_cdata_valid                 ( afu_tlx_cdata_valid ),
      .afu_tlx_cdata_bdi                   ( afu_tlx_cdata_bdi ),
      .afu_tlx_cdata_bus                   ( afu_tlx_cdata_bus[511:0] ),
                                                                                         
      .tlx_afu_cmd_credit                  ( tlx_afu_cmd_credit ),
      .tlx_afu_cmd_data_credit             ( tlx_afu_cmd_data_credit ),
                                                                                         

      .tlx_afu_cmd_initial_credit_x        ( 1'b0 ),

      .tlx_afu_cmd_initial_credit          ( tlx_afu_cmd_initial_credit ),
      .tlx_afu_resp_initial_credit         ( tlx_afu_resp_initial_credit ),

      .tlx_afu_cmd_data_initial_credit_x   ( 1'b0 ),

      .tlx_afu_cmd_data_initial_credit     ( tlx_afu_cmd_data_initial_credit ),
      .tlx_afu_resp_data_initial_credit    ( tlx_afu_resp_data_initial_credit ),
                                                                                         

      .tlx_afu_resp_valid                  ( tlx_afu_resp_valid ),
      .tlx_afu_resp_opcode                 ( tlx_afu_resp_opcode[7:0] ),
      .tlx_afu_resp_afutag                 ( tlx_afu_resp_afutag[15:0] ),
      .tlx_afu_resp_code                   ( tlx_afu_resp_code[3:0] ),
      .tlx_afu_resp_dl                     ( tlx_afu_resp_dl[1:0] ),
      .tlx_afu_resp_dp                     ( tlx_afu_resp_dp[1:0] ),
      .tlx_afu_resp_pg_size                ( tlx_afu_resp_pg_size[5:0] ),
      .tlx_afu_resp_addr_tag               ( tlx_afu_resp_addr_tag[17:0] ),


                                                                                         
      .afu_tlx_resp_rd_req                 ( afu_tlx_resp_rd_req ),
      .afu_tlx_resp_rd_cnt                 ( afu_tlx_resp_rd_cnt[2:0] ),
                                                                                         
      .tlx_afu_resp_data_valid             ( tlx_afu_resp_data_valid ),
      .tlx_afu_resp_data_bdi               ( tlx_afu_resp_data_bdi ),
      .tlx_afu_resp_data_bus               ( tlx_afu_resp_data_bus[511:0] ),
                                                                                         
      .afu_tlx_resp_credit                 ( afu_tlx_resp_credit ),
      .afu_tlx_resp_initial_credit         ( afu_tlx_resp_initial_credit[6:0] ),

      .afu_tlx_fatal_error                 ( afu_tlx_fatal_error ),


      .cfg_afu_bdf_bus                     ( cfg_bus[7:0] ),
      .cfg_afu_bdf_device                  ( ro_device[4:0] ),
      .cfg_afu_bdf_function                ( ro_function[2:0] ),



      .cfg_csh_memory_space                ( cfg_f1_csh_memory_space ),
      .cfg_csh_mmio_bar0                   ( cfg_f1_csh_mmio_bar0[63:0] ),


      .cfg_octrl00_afu_actag_len_enab      ( cfg_f1_octrl00_afu_actag_len_enab[11:0] ),
      .cfg_octrl00_afu_actag_base          ( cfg_f1_octrl00_afu_actag_base[11:0] ),


      .cfg_octrl00_terminate_in_progress   ( afu_f1_cfg_terminate_in_progress ),
      .cfg_octrl00_terminate_valid         ( cfg_f1_octrl00_terminate_valid ),
      .cfg_octrl00_terminate_pasid         ( cfg_f1_octrl00_terminate_pasid[19:0] ),


      .cfg_octrl00_pasid_length_enabled    ( cfg_f1_octrl00_pasid_length_enabled[4:0] ),
      .cfg_octrl00_pasid_base              ( cfg_f1_octrl00_pasid_base[19:0] ),


      .cfg_f0_otl0_long_backoff_timer      ( cfg_f0_otl0_long_backoff_timer[3:0] ),
      .cfg_f0_otl0_short_backoff_timer     ( cfg_f0_otl0_short_backoff_timer[3:0] ),
      .cfg_octrl00_enable_afu              ( cfg_f1_octrl00_enable_afu ),


      .cfg_desc_afu_index                  ( cfg_desc_afu_index[5:0] ),
      .cfg_desc_offset                     ( cfg_desc_offset[30:0] ),
      .cfg_desc_cmd_valid                  ( cfg_desc_cmd_valid ),
      .desc_cfg_data                       ( desc0_cfg_data[31:0] ),
      .desc_cfg_data_valid                 ( desc0_cfg_data_valid ),
      .desc_cfg_echo_cmd_valid             ( desc0_cfg_echo_cmd_valid ),


      .vpd_err_unimplemented_addr          ( vpd_err_unimplemented_addr ),
      .cfg0_cff_fifo_overflow              ( cfg0_cff_fifo_overflow ),

      .cfg0_rff_fifo_overflow              ( cfg0_rff_fifo_overflow ),

      .cfg_errvec                          ( cfg_errvec ),
      .cfg_errvec_valid                    ( cfg_errvec_valid )

    );





endmodule
module oc_function (




    input          clock_tlx
  , input          clock_afu                               
  , input          reset                        


  , input    [7:0] cfg_bus


  , input    [4:0] ro_device
  , input    [2:0] ro_function
    




  , input          tlx_afu_ready


  , output [  6:0] afu_tlx_cmd_initial_credit
  , output         afu_tlx_cmd_credit
  , input          tlx_afu_cmd_valid
  , input  [  7:0] tlx_afu_cmd_opcode
  , input  [  1:0] tlx_afu_cmd_dl
  , input          tlx_afu_cmd_end
  , input  [ 63:0] tlx_afu_cmd_pa
  , input  [  3:0] tlx_afu_cmd_flag
  , input          tlx_afu_cmd_os
  , input  [ 15:0] tlx_afu_cmd_capptag
  , input  [  2:0] tlx_afu_cmd_pl
  , input  [ 63:0] tlx_afu_cmd_be


  , output [  6:0] afu_tlx_resp_initial_credit
  , output         afu_tlx_resp_credit
  , input          tlx_afu_resp_valid
  , input  [  7:0] tlx_afu_resp_opcode
  , input  [ 15:0] tlx_afu_resp_afutag
  , input  [  3:0] tlx_afu_resp_code
  , input  [  5:0] tlx_afu_resp_pg_size
  , input  [  1:0] tlx_afu_resp_dl
  , input  [  1:0] tlx_afu_resp_dp
  , input  [ 23:0] tlx_afu_resp_host_tag
  , input  [  3:0] tlx_afu_resp_cache_state
  , input  [ 17:0] tlx_afu_resp_addr_tag


  , output         afu_tlx_cmd_rd_req
  , output [  2:0] afu_tlx_cmd_rd_cnt
  , input          tlx_afu_cmd_data_valid
  , input          tlx_afu_cmd_data_bdi
  , input  [511:0] tlx_afu_cmd_data_bus


  , output         afu_tlx_resp_rd_req
  , output [  2:0] afu_tlx_resp_rd_cnt
  , input          tlx_afu_resp_data_valid
  , input          tlx_afu_resp_data_bdi
  , input  [511:0] tlx_afu_resp_data_bus









  , input  [  3:0] tlx_afu_cmd_initial_credit
  , input  [  3:0] tlx_afu_resp_initial_credit
  , input  [  5:0] tlx_afu_cmd_data_initial_credit
  , input  [  5:0] tlx_afu_resp_data_initial_credit



  , input          tlx_afu_cmd_credit                
  , output         afu_tlx_cmd_valid                 
  , output [  7:0] afu_tlx_cmd_opcode                
  , output [ 11:0] afu_tlx_cmd_actag                 
  , output [  3:0] afu_tlx_cmd_stream_id             
  , output [ 67:0] afu_tlx_cmd_ea_or_obj             
  , output [ 15:0] afu_tlx_cmd_afutag               
  , output [  1:0] afu_tlx_cmd_dl                    
  , output [  2:0] afu_tlx_cmd_pl                    
  , output         afu_tlx_cmd_os                    
  , output [ 63:0] afu_tlx_cmd_be                    
  , output [  3:0] afu_tlx_cmd_flag                  
  , output         afu_tlx_cmd_endian                
  , output [ 15:0] afu_tlx_cmd_bdf
  , output [ 19:0] afu_tlx_cmd_pasid                 
  , output [  5:0] afu_tlx_cmd_pg_size               


  , input          tlx_afu_cmd_data_credit           
  , output         afu_tlx_cdata_valid               
  , output [511:0] afu_tlx_cdata_bus                 
  , output         afu_tlx_cdata_bdi


  , input          tlx_afu_resp_credit               
  , output         afu_tlx_resp_valid                
  , output [  7:0] afu_tlx_resp_opcode               
  , output [  1:0] afu_tlx_resp_dl   
  , output [ 15:0] afu_tlx_resp_capptag          
  , output [  1:0] afu_tlx_resp_dp                   
  , output [  3:0] afu_tlx_resp_code                 


  , input          tlx_afu_resp_data_credit          
  , output         afu_tlx_rdata_valid               
  , output [511:0] afu_tlx_rdata_bus                 
  , output         afu_tlx_rdata_bdi





  , input    [2:0] cfg_function
  , input    [1:0] cfg_portnum                  
  , input   [11:0] cfg_addr                     
  , input   [31:0] cfg_wdata                    
  , output  [31:0] cfg_f1_rdata               
  , output         cfg_f1_rdata_vld            
  , input          cfg_wr_1B                    
  , input          cfg_wr_2B                    
  , input          cfg_wr_4B                    
  , input          cfg_rd                       
  , output         cfg_f1_bad_op_or_align       
  , output         cfg_f1_addr_not_implemented  






  , output         cfg_f1_octrl00_fence_afu


  , input    [3:0] cfg_f0_otl0_long_backoff_timer
  , input    [3:0] cfg_f0_otl0_short_backoff_timer


  , input          vpd_err_unimplemented_addr
  , input          cfg0_cff_fifo_overflow
  , input          cfg1_cff_fifo_overflow
  , input          cfg0_rff_fifo_overflow
  , input          cfg1_rff_fifo_overflow
  , input  [127:0] cfg_errvec
  , input          cfg_errvec_valid


  , output         cfg_f1_octrl00_resync_credits
  
  

    ,input [31:0] f1_csh_expansion_rom_bar       
    ,input [15:0] f1_csh_subsystem_id            
    ,input [15:0] f1_csh_subsystem_vendor_id     
    ,input [63:0] f1_csh_mmio_bar0_size          
    ,input [63:0] f1_csh_mmio_bar1_size          
    ,input [63:0] f1_csh_mmio_bar2_size          
    ,input        f1_csh_mmio_bar0_prefetchable  
    ,input        f1_csh_mmio_bar1_prefetchable  
    ,input        f1_csh_mmio_bar2_prefetchable  
    ,input  [4:0] f1_pasid_max_pasid_width       
    ,input  [7:0] f1_ofunc_reset_duration        
    ,input        f1_ofunc_afu_present           
    ,input  [4:0] f1_ofunc_max_afu_index         
    ,input  [7:0] f1_octrl00_reset_duration      
    ,input  [5:0] f1_octrl00_afu_control_index   
    ,input  [4:0] f1_octrl00_pasid_len_supported 
    ,input        f1_octrl00_metadata_supported  
    ,input [11:0] f1_octrl00_actag_len_supported 

  `ifdef ENABLE_DDR 
  `ifdef AD9V3
  


    , input                  c0_sys_clk_p
    , input                  c0_sys_clk_n
    , output  [16 : 0]       c0_ddr4_adr
    , output  [1 : 0]        c0_ddr4_ba
    , output  [0 : 0]        c0_ddr4_cke
    , output  [0 : 0]        c0_ddr4_cs_n
    , inout   [8 : 0]        c0_ddr4_dm_dbi_n
    , inout   [71 : 0]       c0_ddr4_dq
    , inout   [8 : 0]        c0_ddr4_dqs_c
    , inout   [8 : 0]        c0_ddr4_dqs_t
    , output  [0 : 0]        c0_ddr4_odt
    , output  [1 : 0]        c0_ddr4_bg
    , output                 c0_ddr4_reset_n
    , output                 c0_ddr4_act_n
    , output  [0 : 0]        c0_ddr4_ck_c
    , output  [0 : 0]        c0_ddr4_ck_t
   `endif
   `ifdef BW250SOC


    , input                  c0_sys_clk_p
    , input                  c0_sys_clk_n
    , output  [16 : 0]       c0_ddr4_adr
    , output  [1 : 0]        c0_ddr4_ba
    , output  [0 : 0]        c0_ddr4_cke
    , output  [0 : 0]        c0_ddr4_cs_n
    , inout   [8 : 0]        c0_ddr4_dm_dbi_n
    , inout   [71 : 0]       c0_ddr4_dq
    , inout   [8 : 0]        c0_ddr4_dqs_c
    , inout   [8 : 0]        c0_ddr4_dqs_t
    , output  [0 : 0]        c0_ddr4_odt
    , output  [0 : 0]        c0_ddr4_bg
    , output                 c0_ddr4_reset_n
    , output                 c0_ddr4_act_n
    , output  [0 : 0]        c0_ddr4_ck_c
    , output  [0 : 0]        c0_ddr4_ck_t
   `endif
   `endif

`ifdef ENABLE_ETHERNET
`ifndef ENABLE_ETH_LOOP_BACK
    , input                  gt_ref_clk_n
    , input                  gt_ref_clk_p
    , input                  gt_rx_gt_port_0_n
    , input                  gt_rx_gt_port_0_p
    , input                  gt_rx_gt_port_1_n
    , input                  gt_rx_gt_port_1_p
    , input                  gt_rx_gt_port_2_n
    , input                  gt_rx_gt_port_2_p
    , input                  gt_rx_gt_port_3_n
    , input                  gt_rx_gt_port_3_p
    , output                 gt_tx_gt_port_0_n
    , output                 gt_tx_gt_port_0_p
    , output                 gt_tx_gt_port_1_n
    , output                 gt_tx_gt_port_1_p
    , output                 gt_tx_gt_port_2_n
    , output                 gt_tx_gt_port_2_p
    , output                 gt_tx_gt_port_3_n
    , output                 gt_tx_gt_port_3_p
`endif
`endif

`ifdef ENABLE_9H3_LED
     , output                 user_led_a0
     , output                 user_led_a1
     , output                 user_led_g0
     , output                 user_led_g1
`endif
`ifdef ENABLE_9H3_EEPROM
     , inout                  eeprom_scl
     , inout                  eeprom_sda
     , output                 eeprom_wp
`endif
`ifdef ENABLE_9H3_AVR
    , input                  avr_rx
    , output                 avr_tx
    , input                  avr_ck
`endif
);







  wire  [5:0] cfg_desc_afu_index
; wire [30:0] cfg_desc_offset
; wire        cfg_desc_cmd_valid
; wire [31:0] desc_cfg_data
; wire        desc_cfg_data_valid
; wire        desc_cfg_echo_cmd_valid
; wire [31:0] desc0_cfg_data
; wire        desc0_cfg_data_valid
; wire        desc0_cfg_echo_cmd_valid
 

; wire        reset_afu00
; wire        resync_credits_afu00
; 


wire [31:0] f1_ro_csh_expansion_rom_bar       ;
wire [15:0] f1_ro_csh_subsystem_id            ;
wire [15:0] f1_ro_csh_subsystem_vendor_id     ;
wire [63:0] f1_ro_csh_mmio_bar0_size          ;
wire [63:0] f1_ro_csh_mmio_bar1_size          ;
wire [63:0] f1_ro_csh_mmio_bar2_size          ;
wire        f1_ro_csh_mmio_bar0_prefetchable  ;
wire        f1_ro_csh_mmio_bar1_prefetchable  ;
wire        f1_ro_csh_mmio_bar2_prefetchable  ;
wire  [4:0] f1_ro_pasid_max_pasid_width       ;
wire  [7:0] f1_ro_ofunc_reset_duration        ;
wire        f1_ro_ofunc_afu_present           ;
wire  [4:0] f1_ro_ofunc_max_afu_index         ;
wire  [7:0] f1_ro_octrl00_reset_duration      ;
wire  [5:0] f1_ro_octrl00_afu_control_index   ;
wire  [4:0] f1_ro_octrl00_pasid_len_supported ;
wire        f1_ro_octrl00_metadata_supported  ;
wire [11:0] f1_ro_octrl00_actag_len_supported ;


assign f1_ro_csh_expansion_rom_bar       = f1_csh_expansion_rom_bar      ;
assign f1_ro_csh_subsystem_id            = f1_csh_subsystem_id           ;
assign f1_ro_csh_subsystem_vendor_id     = f1_csh_subsystem_vendor_id    ;
assign f1_ro_csh_mmio_bar0_size          = f1_csh_mmio_bar0_size         ;
assign f1_ro_csh_mmio_bar1_size          = f1_csh_mmio_bar1_size         ;
assign f1_ro_csh_mmio_bar2_size          = f1_csh_mmio_bar2_size         ;
assign f1_ro_csh_mmio_bar0_prefetchable  = f1_csh_mmio_bar0_prefetchable ;
assign f1_ro_csh_mmio_bar1_prefetchable  = f1_csh_mmio_bar1_prefetchable ;
assign f1_ro_csh_mmio_bar2_prefetchable  = f1_csh_mmio_bar2_prefetchable ;
assign f1_ro_pasid_max_pasid_width       = f1_pasid_max_pasid_width      ;
assign f1_ro_ofunc_reset_duration        = f1_ofunc_reset_duration       ;
assign f1_ro_ofunc_afu_present           = f1_ofunc_afu_present          ;
assign f1_ro_ofunc_max_afu_index         = f1_ofunc_max_afu_index        ;
assign f1_ro_octrl00_reset_duration      = f1_octrl00_reset_duration     ;
assign f1_ro_octrl00_afu_control_index   = f1_octrl00_afu_control_index  ;
assign f1_ro_octrl00_pasid_len_supported = f1_octrl00_pasid_len_supported;
assign f1_ro_octrl00_metadata_supported  = f1_octrl00_metadata_supported ;
assign f1_ro_octrl00_actag_len_supported = f1_octrl00_actag_len_supported;







  wire         afu_f1_cfg_terminate_in_progress


; wire         cfg_f1_csh_memory_space
; wire  [63:0] cfg_f1_csh_mmio_bar0
; wire  [63:0] cfg_f1_csh_mmio_bar1
; wire  [63:0] cfg_f1_csh_mmio_bar2
; wire  [31:0] cfg_f1_csh_expansion_ROM_bar
; wire         cfg_f1_csh_expansion_ROM_enable
; wire         cfg_f1_ofunc_function_reset      
; wire  [11:0] cfg_f1_ofunc_func_actag_base
; wire  [11:0] cfg_f1_ofunc_func_actag_len_enab
; wire   [5:0] cfg_f1_octrl00_afu_control_index 
; wire   [3:0] cfg_f1_octrl00_afu_unique              

; wire         cfg_f1_octrl00_enable_afu           
; wire         cfg_f1_octrl00_reset_afu            
; wire         cfg_f1_octrl00_terminate_valid      
; wire  [19:0] cfg_f1_octrl00_terminate_pasid      
; wire   [4:0] cfg_f1_octrl00_pasid_length_enabled
; wire         cfg_f1_octrl00_metadata_enabled
; wire   [2:0] cfg_f1_octrl00_host_tag_run_length
; wire  [19:0] cfg_f1_octrl00_pasid_base
; wire  [11:0] cfg_f1_octrl00_afu_actag_len_enab
; wire  [11:0] cfg_f1_octrl00_afu_actag_base
;

wire   cfg_f1_reset;
assign cfg_f1_reset = (reset == 1'b1 || cfg_f1_ofunc_function_reset == 1'b1) ? 1'b1 : 1'b0;

cfg_func1 cfg_f1
    (

      .clock                               ( clock_tlx ),
      .reset                               ( cfg_f1_reset ),
      .device_reset                        ( reset ),
                                                                                        


      .cfg_ro_csh_device_id                ( 16'h062B ),
      .cfg_ro_csh_vendor_id                ( 16'h1014 ),
      .cfg_ro_csh_class_code               ( 24'h120000 ),
      .cfg_ro_csh_revision_id              (  8'h00 ),
      .cfg_ro_csh_multi_function           (  1'b1 ),
      .cfg_ro_csh_mmio_bar0_size           ( f1_ro_csh_mmio_bar0_size         ),
      .cfg_ro_csh_mmio_bar1_size           ( f1_ro_csh_mmio_bar1_size         ),
      .cfg_ro_csh_mmio_bar2_size           ( f1_ro_csh_mmio_bar2_size         ),
      .cfg_ro_csh_mmio_bar0_prefetchable   ( f1_ro_csh_mmio_bar0_prefetchable ),
      .cfg_ro_csh_mmio_bar1_prefetchable   ( f1_ro_csh_mmio_bar1_prefetchable ),
      .cfg_ro_csh_mmio_bar2_prefetchable   ( f1_ro_csh_mmio_bar2_prefetchable ),
      .cfg_ro_csh_subsystem_id             ( f1_ro_csh_subsystem_id           ),
      .cfg_ro_csh_subsystem_vendor_id      ( f1_ro_csh_subsystem_vendor_id    ),
      .cfg_ro_csh_expansion_rom_bar        ( f1_ro_csh_expansion_rom_bar      ),
                                                                                        

      .cfg_ro_pasid_max_pasid_width        ( f1_ro_pasid_max_pasid_width ),
                                                                                        

      .cfg_ro_ofunc_reset_duration         ( f1_ro_ofunc_reset_duration ),
      .cfg_ro_ofunc_afu_present            ( f1_ro_ofunc_afu_present    ),
      .cfg_ro_ofunc_max_afu_index          ( f1_ro_ofunc_max_afu_index  ),
                                                                                        

      .cfg_ro_octrl00_reset_duration       ( f1_ro_octrl00_reset_duration      ),
      .cfg_ro_octrl00_afu_control_index    ( f1_ro_octrl00_afu_control_index   ),
      .cfg_ro_octrl00_pasid_len_supported  ( f1_ro_octrl00_pasid_len_supported ),
      .cfg_ro_octrl00_metadata_supported   ( f1_ro_octrl00_metadata_supported  ),
      .cfg_ro_octrl00_actag_len_supported  ( f1_ro_octrl00_actag_len_supported ),
                                                                                        

      .cfg_ro_function                     ( ro_function ),
                                                                                        

      .cfg_function                        ( cfg_function[2:0] ),
      .cfg_portnum                         ( cfg_portnum[1:0] ),
      .cfg_addr                            ( cfg_addr[11:0] ),
      .cfg_wdata                           ( cfg_wdata[31:0] ),
      .cfg_rdata                           ( cfg_f1_rdata[31:0] ),
      .cfg_rdata_vld                       ( cfg_f1_rdata_vld ),
      .cfg_wr_1B                           ( cfg_wr_1B ),
      .cfg_wr_2B                           ( cfg_wr_2B ),
      .cfg_wr_4B                           ( cfg_wr_4B ),
      .cfg_rd                              ( cfg_rd ),
      .cfg_bad_op_or_align                 ( cfg_f1_bad_op_or_align ),
      .cfg_addr_not_implemented            ( cfg_f1_addr_not_implemented ),
                                                                                        

      .cfg_octrl00_terminate_in_progress   ( afu_f1_cfg_terminate_in_progress ),
                                                                                        


      .cfg_csh_memory_space                ( cfg_f1_csh_memory_space ),
      .cfg_csh_mmio_bar0                   ( cfg_f1_csh_mmio_bar0[63:0] ),
      .cfg_csh_mmio_bar1                   ( cfg_f1_csh_mmio_bar1[63:0] ),
      .cfg_csh_mmio_bar2                   ( cfg_f1_csh_mmio_bar2[63:0] ),
      .cfg_csh_expansion_ROM_bar           ( cfg_f1_csh_expansion_ROM_bar[31:0] ),
      .cfg_csh_expansion_ROM_enable        ( cfg_f1_csh_expansion_ROM_enable ),
                                                                                        

      .cfg_ofunc_function_reset            ( cfg_f1_ofunc_function_reset ),
      .cfg_ofunc_func_actag_base           ( cfg_f1_ofunc_func_actag_base[11:0] ),
      .cfg_ofunc_func_actag_len_enab       ( cfg_f1_ofunc_func_actag_len_enab[11:0] ),
                                                                                        

      .cfg_octrl00_afu_control_index       ( cfg_f1_octrl00_afu_control_index[5:0] ),
      .cfg_octrl00_afu_unique              ( cfg_f1_octrl00_afu_unique[3:0] ),
      .cfg_octrl00_fence_afu               ( cfg_f1_octrl00_fence_afu ),
      .cfg_octrl00_enable_afu              ( cfg_f1_octrl00_enable_afu ),
      .cfg_octrl00_reset_afu               ( cfg_f1_octrl00_reset_afu ),
      .cfg_octrl00_terminate_valid         ( cfg_f1_octrl00_terminate_valid ),
      .cfg_octrl00_terminate_pasid         ( cfg_f1_octrl00_terminate_pasid[19:0] ),
      .cfg_octrl00_pasid_length_enabled    ( cfg_f1_octrl00_pasid_length_enabled[4:0] ),
      .cfg_octrl00_metadata_enabled        ( cfg_f1_octrl00_metadata_enabled ),
      .cfg_octrl00_host_tag_run_length     ( cfg_f1_octrl00_host_tag_run_length[2:0] ),
      .cfg_octrl00_pasid_base              ( cfg_f1_octrl00_pasid_base[19:0] ),
      .cfg_octrl00_afu_actag_base          ( cfg_f1_octrl00_afu_actag_base[11:0] ),
      .cfg_octrl00_afu_actag_len_enab      ( cfg_f1_octrl00_afu_actag_len_enab[11:0] ),


      .cfg_desc_afu_index                  ( cfg_desc_afu_index[5:0] ),
      .cfg_desc_offset                     ( cfg_desc_offset[30:0] ),
      .cfg_desc_cmd_valid                  ( cfg_desc_cmd_valid ),
      .desc_cfg_data                       ( desc_cfg_data[31:0] ),
      .desc_cfg_data_valid                 ( desc_cfg_data_valid ),
      .desc_cfg_echo_cmd_valid             ( desc_cfg_echo_cmd_valid )

    );





assign desc_cfg_echo_cmd_valid  = desc0_cfg_echo_cmd_valid ;
assign desc_cfg_data_valid      = desc0_cfg_data_valid     ;
assign desc_cfg_data            = desc0_cfg_data           ;


assign cfg_f1_octrl00_resync_credits = cfg_f1_octrl00_afu_unique[0];
assign resync_credits_afu00          = cfg_f1_octrl00_afu_unique[0];





assign reset_afu00 = ( reset == 1'b1        || 
                       cfg_f1_reset == 1'b1 ||
                      (cfg_f1_octrl00_reset_afu == 1'b1 && cfg_f1_octrl00_afu_control_index == 6'b000000) ) ? 1'b1 : 1'b0; 

wire afu_tlx_fatal_error;

framework_afu  fw_afu 
    (

      .clock_tlx                           ( clock_tlx),
      .clock_afu                           ( clock_afu ),
      .reset                               ( reset_afu00 ),
                                                                                         
  `ifdef ENABLE_DDR 
  `ifdef AD9V3
  

      .c0_sys_clk_p     ( c0_sys_clk_p     ) ,
      .c0_sys_clk_n     ( c0_sys_clk_n     ) ,
      .c0_ddr4_adr      ( c0_ddr4_adr      ) ,
      .c0_ddr4_ba       ( c0_ddr4_ba       ) ,
      .c0_ddr4_cke      ( c0_ddr4_cke      ) ,
      .c0_ddr4_cs_n     ( c0_ddr4_cs_n     ) ,
      .c0_ddr4_dm_dbi_n ( c0_ddr4_dm_dbi_n ) ,
      .c0_ddr4_dq       ( c0_ddr4_dq       ) ,
      .c0_ddr4_dqs_c    ( c0_ddr4_dqs_c    ) ,
      .c0_ddr4_dqs_t    ( c0_ddr4_dqs_t    ) ,
      .c0_ddr4_odt      ( c0_ddr4_odt      ) ,
      .c0_ddr4_bg       ( c0_ddr4_bg       ) ,
      .c0_ddr4_reset_n  ( c0_ddr4_reset_n  ) ,
      .c0_ddr4_act_n    ( c0_ddr4_act_n    ) ,
      .c0_ddr4_ck_c     ( c0_ddr4_ck_c     ) ,
      .c0_ddr4_ck_t     ( c0_ddr4_ck_t     ) ,
   `endif
   `ifdef BW250SOC
  

      .c0_sys_clk_p     ( c0_sys_clk_p     ) ,
      .c0_sys_clk_n     ( c0_sys_clk_n     ) ,
      .c0_ddr4_adr      ( c0_ddr4_adr      ) ,
      .c0_ddr4_ba       ( c0_ddr4_ba       ) ,
      .c0_ddr4_cke      ( c0_ddr4_cke      ) ,
      .c0_ddr4_cs_n     ( c0_ddr4_cs_n     ) ,
      .c0_ddr4_dm_dbi_n ( c0_ddr4_dm_dbi_n ) ,
      .c0_ddr4_dq       ( c0_ddr4_dq       ) ,
      .c0_ddr4_dqs_c    ( c0_ddr4_dqs_c    ) ,
      .c0_ddr4_dqs_t    ( c0_ddr4_dqs_t    ) ,
      .c0_ddr4_odt      ( c0_ddr4_odt      ) ,
      .c0_ddr4_bg       ( c0_ddr4_bg       ) ,
      .c0_ddr4_reset_n  ( c0_ddr4_reset_n  ) ,
      .c0_ddr4_act_n    ( c0_ddr4_act_n    ) ,
      .c0_ddr4_ck_c     ( c0_ddr4_ck_c     ) ,
      .c0_ddr4_ck_t     ( c0_ddr4_ck_t     ) ,
   `endif

   `endif
  `ifdef ENABLE_ETHERNET
  `ifndef ENABLE_ETH_LOOP_BACK
      .gt_ref_clk_n      ( gt_ref_clk_n       ),
      .gt_ref_clk_p      ( gt_ref_clk_p       ),
      .gt_rx_gt_port_0_n ( gt_rx_gt_port_0_n  ),
      .gt_rx_gt_port_0_p ( gt_rx_gt_port_0_p  ),
      .gt_rx_gt_port_1_n ( gt_rx_gt_port_1_n  ),
      .gt_rx_gt_port_1_p ( gt_rx_gt_port_1_p  ),
      .gt_rx_gt_port_2_n ( gt_rx_gt_port_2_n  ),
      .gt_rx_gt_port_2_p ( gt_rx_gt_port_2_p  ),
      .gt_rx_gt_port_3_n ( gt_rx_gt_port_3_n  ),
      .gt_rx_gt_port_3_p ( gt_rx_gt_port_3_p  ),
      .gt_tx_gt_port_0_n ( gt_tx_gt_port_0_n  ),
      .gt_tx_gt_port_0_p ( gt_tx_gt_port_0_p  ),
      .gt_tx_gt_port_1_n ( gt_tx_gt_port_1_n  ),
      .gt_tx_gt_port_1_p ( gt_tx_gt_port_1_p  ),
      .gt_tx_gt_port_2_n ( gt_tx_gt_port_2_n  ),
      .gt_tx_gt_port_2_p ( gt_tx_gt_port_2_p  ),
      .gt_tx_gt_port_3_n ( gt_tx_gt_port_3_n  ),
      .gt_tx_gt_port_3_p ( gt_tx_gt_port_3_p  ),
   `endif
   `endif

   `ifdef ENABLE_9H3_LED
      .user_led_a0     ( user_led_a0        ),
      .user_led_a1     ( user_led_a1        ),
      .user_led_g0     ( user_led_g0        ),
      .user_led_g1     ( user_led_g1        ),
   `endif
   `ifdef ENABLE_9H3_EEPROM
      .eeprom_scl      (eeprom_scl          ),
      .eeprom_sda      (eeprom_sda          ),
      .eeprom_wp       (eeprom_wp           ),
   `endif
   `ifdef ENABLE_9H3_AVR
      .avr_rx          (avr_rx              ),
      .avr_tx          (avr_tx              ),
      .avr_ck          (avr_ck              ),
    `endif


      .afu_index                           ( 6'b000000 ),
                                                                                         

      .tlx_afu_ready                       ( tlx_afu_ready ),
      .tlx_afu_cmd_valid                   ( tlx_afu_cmd_valid ),
      .tlx_afu_cmd_opcode                  ( tlx_afu_cmd_opcode[7:0] ),
      .tlx_afu_cmd_capptag                 ( tlx_afu_cmd_capptag[15:0] ),
      .tlx_afu_cmd_dl                      ( tlx_afu_cmd_dl[1:0] ),
      .tlx_afu_cmd_pl                      ( tlx_afu_cmd_pl[2:0] ),
      .tlx_afu_cmd_be                      ( tlx_afu_cmd_be[63:0] ),
      .tlx_afu_cmd_end                     ( tlx_afu_cmd_end ),
      .tlx_afu_cmd_pa                      ( tlx_afu_cmd_pa[63:0] ),
      .tlx_afu_cmd_flag                    ( tlx_afu_cmd_flag[3:0] ),
      .tlx_afu_cmd_os                      ( tlx_afu_cmd_os ),
                                                                                         
      .afu_tlx_cmd_rd_req                  ( afu_tlx_cmd_rd_req ),
      .afu_tlx_cmd_rd_cnt                  ( afu_tlx_cmd_rd_cnt[2:0] ),
                                                                                         
      .tlx_afu_cmd_data_valid              ( tlx_afu_cmd_data_valid ),
      .tlx_afu_cmd_data_bdi                ( tlx_afu_cmd_data_bdi ),
      .tlx_afu_cmd_data_bus                ( tlx_afu_cmd_data_bus[511:0] ),
                                                                                         
      .afu_tlx_cmd_credit                  ( afu_tlx_cmd_credit ),
      .afu_tlx_cmd_initial_credit          ( afu_tlx_cmd_initial_credit[6:0] ),
                                                                                         

      .afu_tlx_resp_valid                  ( afu_tlx_resp_valid ),
      .afu_tlx_resp_opcode                 ( afu_tlx_resp_opcode[7:0] ),
      .afu_tlx_resp_dl                     ( afu_tlx_resp_dl[1:0] ),
      .afu_tlx_resp_capptag                ( afu_tlx_resp_capptag[15:0] ),
      .afu_tlx_resp_dp                     ( afu_tlx_resp_dp[1:0] ),
      .afu_tlx_resp_code                   ( afu_tlx_resp_code[3:0] ),
                                                                                         
      .afu_tlx_rdata_valid                 ( afu_tlx_rdata_valid ),
      .afu_tlx_rdata_bdi                   ( afu_tlx_rdata_bdi ),
      .afu_tlx_rdata_bus                   ( afu_tlx_rdata_bus[511:0] ),
                                                                                         
      .tlx_afu_resp_credit                 ( tlx_afu_resp_credit ),
      .tlx_afu_resp_data_credit            ( tlx_afu_resp_data_credit ),
                                                                                         

      .afu_tlx_cmd_valid                   ( afu_tlx_cmd_valid ),
      .afu_tlx_cmd_opcode                  ( afu_tlx_cmd_opcode[7:0] ),
      .afu_tlx_cmd_actag                   ( afu_tlx_cmd_actag[11:0] ),
      .afu_tlx_cmd_stream_id               ( afu_tlx_cmd_stream_id[3:0] ),
      .afu_tlx_cmd_ea_or_obj               ( afu_tlx_cmd_ea_or_obj[67:0] ),
      .afu_tlx_cmd_afutag                  ( afu_tlx_cmd_afutag[15:0] ),
      .afu_tlx_cmd_dl                      ( afu_tlx_cmd_dl[1:0] ),
      .afu_tlx_cmd_pl                      ( afu_tlx_cmd_pl[2:0] ),
      .afu_tlx_cmd_os                      ( afu_tlx_cmd_os ),
      .afu_tlx_cmd_be                      ( afu_tlx_cmd_be[63:0] ),
      .afu_tlx_cmd_flag                    ( afu_tlx_cmd_flag[3:0] ),
      .afu_tlx_cmd_endian                  ( afu_tlx_cmd_endian ),
      .afu_tlx_cmd_bdf                     ( afu_tlx_cmd_bdf[15:0] ),
      .afu_tlx_cmd_pasid                   ( afu_tlx_cmd_pasid[19:0] ),
      .afu_tlx_cmd_pg_size                 ( afu_tlx_cmd_pg_size[5:0] ),
                                                                                         
      .afu_tlx_cdata_valid                 ( afu_tlx_cdata_valid ),
      .afu_tlx_cdata_bdi                   ( afu_tlx_cdata_bdi ),
      .afu_tlx_cdata_bus                   ( afu_tlx_cdata_bus[511:0] ),
                                                                                         
      .tlx_afu_cmd_credit                  ( tlx_afu_cmd_credit ),
      .tlx_afu_cmd_data_credit             ( tlx_afu_cmd_data_credit ),
                                                                                         

      .tlx_afu_cmd_initial_credit_x        ( 1'b0 ),

      .tlx_afu_cmd_initial_credit          ( tlx_afu_cmd_initial_credit ),
      .tlx_afu_resp_initial_credit         ( tlx_afu_resp_initial_credit ),

      .tlx_afu_cmd_data_initial_credit_x   ( 1'b0 ),

      .tlx_afu_cmd_data_initial_credit     ( tlx_afu_cmd_data_initial_credit ),
      .tlx_afu_resp_data_initial_credit    ( tlx_afu_resp_data_initial_credit ),
                                                                                         

      .tlx_afu_resp_valid                  ( tlx_afu_resp_valid ),
      .tlx_afu_resp_opcode                 ( tlx_afu_resp_opcode[7:0] ),
      .tlx_afu_resp_afutag                 ( tlx_afu_resp_afutag[15:0] ),
      .tlx_afu_resp_code                   ( tlx_afu_resp_code[3:0] ),
      .tlx_afu_resp_dl                     ( tlx_afu_resp_dl[1:0] ),
      .tlx_afu_resp_dp                     ( tlx_afu_resp_dp[1:0] ),
      .tlx_afu_resp_pg_size                ( tlx_afu_resp_pg_size[5:0] ),
      .tlx_afu_resp_addr_tag               ( tlx_afu_resp_addr_tag[17:0] ),


                                                                                         
      .afu_tlx_resp_rd_req                 ( afu_tlx_resp_rd_req ),
      .afu_tlx_resp_rd_cnt                 ( afu_tlx_resp_rd_cnt[2:0] ),
                                                                                         
      .tlx_afu_resp_data_valid             ( tlx_afu_resp_data_valid ),
      .tlx_afu_resp_data_bdi               ( tlx_afu_resp_data_bdi ),
      .tlx_afu_resp_data_bus               ( tlx_afu_resp_data_bus[511:0] ),
                                                                                         
      .afu_tlx_resp_credit                 ( afu_tlx_resp_credit ),
      .afu_tlx_resp_initial_credit         ( afu_tlx_resp_initial_credit[6:0] ),

      .afu_tlx_fatal_error                 ( afu_tlx_fatal_error ),


      .cfg_afu_bdf_bus                     ( cfg_bus[7:0] ),
      .cfg_afu_bdf_device                  ( ro_device[4:0] ),
      .cfg_afu_bdf_function                ( ro_function[2:0] ),



      .cfg_csh_memory_space                ( cfg_f1_csh_memory_space ),
      .cfg_csh_mmio_bar0                   ( cfg_f1_csh_mmio_bar0[63:0] ),


      .cfg_octrl00_afu_actag_len_enab      ( cfg_f1_octrl00_afu_actag_len_enab[11:0] ),
      .cfg_octrl00_afu_actag_base          ( cfg_f1_octrl00_afu_actag_base[11:0] ),


      .cfg_octrl00_terminate_in_progress   ( afu_f1_cfg_terminate_in_progress ),
      .cfg_octrl00_terminate_valid         ( cfg_f1_octrl00_terminate_valid ),
      .cfg_octrl00_terminate_pasid         ( cfg_f1_octrl00_terminate_pasid[19:0] ),


      .cfg_octrl00_pasid_length_enabled    ( cfg_f1_octrl00_pasid_length_enabled[4:0] ),
      .cfg_octrl00_pasid_base              ( cfg_f1_octrl00_pasid_base[19:0] ),


      .cfg_f0_otl0_long_backoff_timer      ( cfg_f0_otl0_long_backoff_timer[3:0] ),
      .cfg_f0_otl0_short_backoff_timer     ( cfg_f0_otl0_short_backoff_timer[3:0] ),
      .cfg_octrl00_enable_afu              ( cfg_f1_octrl00_enable_afu ),


      .cfg_desc_afu_index                  ( cfg_desc_afu_index[5:0] ),
      .cfg_desc_offset                     ( cfg_desc_offset[30:0] ),
      .cfg_desc_cmd_valid                  ( cfg_desc_cmd_valid ),
      .desc_cfg_data                       ( desc0_cfg_data[31:0] ),
      .desc_cfg_data_valid                 ( desc0_cfg_data_valid ),
      .desc_cfg_echo_cmd_valid             ( desc0_cfg_echo_cmd_valid ),


      .vpd_err_unimplemented_addr          ( vpd_err_unimplemented_addr ),
      .cfg0_cff_fifo_overflow              ( cfg0_cff_fifo_overflow ),

      .cfg0_rff_fifo_overflow              ( cfg0_rff_fifo_overflow ),

      .cfg_errvec                          ( cfg_errvec ),
      .cfg_errvec_valid                    ( cfg_errvec_valid )

    );





endmodule