data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/barrier_v1_0_0/hdl/barrier.v
1: b'%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/barrier_v1_0_0/hdl/barrier.v:86: Unsupported: wait statements\n      wait ({barrier_req, barrier_req_trans} != \'h0);\n      ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/barrier_v1_0_0/hdl/barrier.v:90: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/barrier_v1_0_0/hdl/barrier.v:95: Unsupported: wait statements\n      wait (({barrier_req, barrier_req_trans} === {(NUM_PORTS+2){1\'b1}}) ||\n      ^~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/barrier_v1_0_0/hdl/barrier.v:107: Unsupported: wait statements\n         wait ({barrier_req, barrier_req_trans} === \'h0);\n         ^~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/barrier_v1_0_0/hdl/barrier.v:117: Unsupported: wait statements\n      wait ({barrier_req, barrier_req_trans} != \'h0 && {activity, activity_trans} != \'h0);\n      ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/barrier_v1_0_0/hdl/barrier.v:120: Unsupported: Ignoring delay on this delayed statement.\n      #1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/barrier_v1_0_0/hdl/barrier.v:130: Unsupported: Ignoring delay on this delayed statement.\n            #1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/barrier_v1_0_0/hdl/barrier.v:131: Unsupported: Ignoring delay on this delayed statement.\n            #(req_time + INACTIVITY_TIMEOUT - $time);\n            ^\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/barrier_v1_0_0/hdl/barrier.v:137: Unsupported: wait statements\n         wait ({barrier_req, barrier_req_trans} != \'h0);\n         ^~~~\n%Error: Exiting due to 5 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module barrier #(
   parameter NUM_PORTS = 4
)
(
   input [NUM_PORTS:0] activity_stim, 
   input [NUM_PORTS:0] activity_rec,
   input activity_trans_sim,
   input activity_trans_log,
   input [NUM_PORTS:0] barrier_req, 
   input barrier_req_trans,
   output reg barrier_proceed
);




parameter INACTIVITY_TIMEOUT = 4000000;
time req_time;
reg timeout;
wire [NUM_PORTS:0] activity;
wire activity_trans;

assign activity = {activity_stim[4] || activity_rec[4],activity_stim[3] || activity_rec[3],activity_stim[2] || activity_rec[2],activity_stim[1] || activity_rec[1],activity_stim[0] || activity_rec[0]};

assign activity_trans = {activity_trans_sim || activity_trans_log};

initial
begin
   barrier_proceed = 0;
   timeout = 0;

   forever begin
      wait ({barrier_req, barrier_req_trans} != 'h0);

      req_time = $time;
      timeout = 0;
      #1;




      wait (({barrier_req, barrier_req_trans} === {(NUM_PORTS+2){1'b1}}) ||
            ({barrier_req, barrier_req_trans} === 'h0) || timeout);

      if (timeout == 1) begin
         $display($time," %m Error: timeout exceeded waiting for barrier");
         $finish;
      end
      else if ({barrier_req, barrier_req_trans} === {(NUM_PORTS+2){1'b1}}) begin


         barrier_proceed = 1;

         wait ({barrier_req, barrier_req_trans} === 'h0);

         barrier_proceed = 0;
      end      
   end  
end

initial
begin
   forever begin
      wait ({barrier_req, barrier_req_trans} != 'h0 && {activity, activity_trans} != 'h0);

      req_time = $time;
      #1;
   end
end

initial
begin
   forever begin
      
      if ({barrier_req, barrier_req_trans} != 'h0) begin
         while ({barrier_req, barrier_req_trans} != 'h0) begin
            #1;
            #(req_time + INACTIVITY_TIMEOUT - $time);
            if ({barrier_req, barrier_req_trans} != 'h0 && req_time + INACTIVITY_TIMEOUT <= $time)
               timeout = 1;
         end
      end
      else begin
         wait ({barrier_req, barrier_req_trans} != 'h0);
      end
   end
end

endmodule
module barrier #(
   parameter NUM_PORTS = 4
)
(
   input [NUM_PORTS:0] activity_stim, 
   input [NUM_PORTS:0] activity_rec,
   input activity_trans_sim,
   input activity_trans_log,
   input [NUM_PORTS:0] barrier_req, 
   input barrier_req_trans,
   output reg barrier_proceed
);





parameter INACTIVITY_TIMEOUT = 4000000;
time req_time;
reg timeout;
wire [NUM_PORTS:0] activity;
wire activity_trans;

assign activity = {activity_stim[4] || activity_rec[4],activity_stim[3] || activity_rec[3],activity_stim[2] || activity_rec[2],activity_stim[1] || activity_rec[1],activity_stim[0] || activity_rec[0]};

assign activity_trans = {activity_trans_sim || activity_trans_log};

initial
begin
   barrier_proceed = 0;
   timeout = 0;

   forever begin
      wait ({barrier_req, barrier_req_trans} != 'h0);

      req_time = $time;
      timeout = 0;
      #1;




      wait (({barrier_req, barrier_req_trans} === {(NUM_PORTS+2){1'b1}}) ||
            ({barrier_req, barrier_req_trans} === 'h0) || timeout);

      if (timeout == 1) begin
         $display($time," %m Error: timeout exceeded waiting for barrier");
         $finish;
      end
      else if ({barrier_req, barrier_req_trans} === {(NUM_PORTS+2){1'b1}}) begin


         barrier_proceed = 1;

         wait ({barrier_req, barrier_req_trans} === 'h0);

         barrier_proceed = 0;
      end      
   end  
end

initial
begin
   forever begin
      wait ({barrier_req, barrier_req_trans} != 'h0 && {activity, activity_trans} != 'h0);

      req_time = $time;
      #1;
   end
end

initial
begin
   forever begin
      
      if ({barrier_req, barrier_req_trans} != 'h0) begin
         while ({barrier_req, barrier_req_trans} != 'h0) begin
            #1;
            #(req_time + INACTIVITY_TIMEOUT - $time);
            if ({barrier_req, barrier_req_trans} != 'h0 && req_time + INACTIVITY_TIMEOUT <= $time)
               timeout = 1;
         end
      end
      else begin
         wait ({barrier_req, barrier_req_trans} != 'h0);
      end
   end
end

endmodule