data/full_repos/permissive/521337848/Hardware/procesor/aluX.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/521337848/Hardware/procesor/aluX.v:111: Cell has missing pin: \'sreg3\'\ncollectsubreg csr(.bank(bank[1]),\n              ^~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/521337848/Hardware/procesor/aluX.v:111: Cell has missing pin: \'sreg4\'\ncollectsubreg csr(.bank(bank[1]),\n              ^~~\n%Error: Exiting due to 2 warning(s)\n'
module saver(
	
	input s,
	input[15:0] result,
	
	input[1:0] reg1,
	
	input[15:0] ireg1,
	input[15:0] ireg2,
	input[15:0] ireg3,
	input[15:0] ireg4,
	
	output reg[15:0] oreg1,
	output reg[15:0] oreg2,
	output reg[15:0] oreg3,
	output reg[15:0] oreg4
);


always@(*)begin
	if(s && reg1 == 0) oreg1 = result;
	else oreg1 = ireg1;
end


always@(*)begin
	if(s && reg1 == 1) oreg2 <= result;
	else oreg2 <= ireg2;
end



always@(*)begin
	if(s && reg1 == 2) oreg3 <= result;
	else oreg3 <= ireg3;
end



always@(*)begin
	
	if(s && reg1 == 3) oreg4 <= result;
	else oreg4 <= ireg4;
	
end


endmodule
module saver(
	
	input s,
	input[15:0] result,
	
	input[1:0] reg1,
	
	input[15:0] ireg1,
	input[15:0] ireg2,
	input[15:0] ireg3,
	input[15:0] ireg4,
	
	output reg[15:0] oreg1,
	output reg[15:0] oreg2,
	output reg[15:0] oreg3,
	output reg[15:0] oreg4
);



always@(*)begin
	if(s && reg1 == 0) oreg1 = result;
	else oreg1 = ireg1;
end


always@(*)begin
	if(s && reg1 == 1) oreg2 <= result;
	else oreg2 <= ireg2;
end



always@(*)begin
	if(s && reg1 == 2) oreg3 <= result;
	else oreg3 <= ireg3;
end



always@(*)begin
	
	if(s && reg1 == 3) oreg4 <= result;
	else oreg4 <= ireg4;
	
end


endmodule