data/full_repos/permissive/471533249/register_tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/471533249/register_tb.sv:29: Unsupported: Ignoring delay on this delayed statement.\n       clk = 0; #20; clk = 1; #20;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/471533249/register_tb.sv:29: Unsupported: Ignoring delay on this delayed statement.\n       clk = 0; #20; clk = 1; #20;\n                              ^\n%Warning-STMTDLY: data/full_repos/permissive/471533249/register_tb.sv:43: Unsupported: Ignoring delay on this delayed statement.\n       #18; {reset,load_en,D,Q_expected} = testvectors[vectornum];\n       ^\n%Error: data/full_repos/permissive/471533249/register_tb.sv:24: Cannot find file containing module: \'register\'\n   register dut(clk, reset, load_en, D, Q);\n   ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/471533249,data/full_repos/permissive/471533249/register\n             data/full_repos/permissive/471533249,data/full_repos/permissive/471533249/register.v\n             data/full_repos/permissive/471533249,data/full_repos/permissive/471533249/register.sv\n             register\n             register.v\n             register.sv\n             obj_dir/register\n             obj_dir/register.v\n             obj_dir/register.sv\n%Warning-WIDTH: data/full_repos/permissive/471533249/register_tb.sv:43: Bit extraction of array[100:0] requires 7 bit index, not 16 bits.\n                                                                      : ... In instance register_tb\n       #18; {reset,load_en,D,Q_expected} = testvectors[vectornum];\n                                                      ^\n%Warning-WIDTH: data/full_repos/permissive/471533249/register_tb.sv:43: Operator ASSIGN expects 34 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 35 bits.\n                                                                      : ... In instance register_tb\n       #18; {reset,load_en,D,Q_expected} = testvectors[vectornum];\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/471533249/register_tb.sv:56: Bit extraction of array[100:0] requires 7 bit index, not 16 bits.\n                                                                      : ... In instance register_tb\n       if (testvectors[vectornum] === \'bx) begin\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/471533249/register_tb.sv:56: Unsized constant being X/Z extended to 35 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                      : ... In instance register_tb\n       if (testvectors[vectornum] === \'bx) begin\n                                      ^~~\n%Error: Exiting due to 1 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module register_tb();


	logic clk, reset, load_en;
	logic [15:0] D;
	

	logic [15:0] Q, Q_expected;
	

	logic [15:0] vectornum, errors;
   logic [34:0] testvectors[100:0];
   

   register dut(clk, reset, load_en, D, Q);
	

   always
     begin
       clk = 0; #20; clk = 1; #20;
     end
	  

  initial
   begin
      $readmemb("register.tv", testvectors);
      vectornum = 0; errors = 0;
   end
	

   always @(negedge clk)
     begin

       #18; {reset,load_en,D,Q_expected} = testvectors[vectornum];
     end


   always @(posedge clk)
    begin
       if (Q !== Q_expected) begin
         $display("Error: inputs = %b, %b, $d, ", reset, load_en, D);
         $display(" outputs = %d (%d expected)",
                Q, Q_expected);
         errors = errors + 1;
       end
       vectornum = vectornum + 1;
       if (testvectors[vectornum] === 'bx) begin
          $display("%d tests completed with %d errors", vectornum, errors);
          $finish;
       end
    end
endmodule
module register_tb();



	logic clk, reset, load_en;
	logic [15:0] D;
	

	logic [15:0] Q, Q_expected;
	

	logic [15:0] vectornum, errors;
   logic [34:0] testvectors[100:0];
   

   register dut(clk, reset, load_en, D, Q);
	

   always
     begin
       clk = 0; #20; clk = 1; #20;
     end
	  

  initial
   begin
      $readmemb("register.tv", testvectors);
      vectornum = 0; errors = 0;
   end
	

   always @(negedge clk)
     begin

       #18; {reset,load_en,D,Q_expected} = testvectors[vectornum];
     end


   always @(posedge clk)
    begin
       if (Q !== Q_expected) begin
         $display("Error: inputs = %b, %b, $d, ", reset, load_en, D);
         $display(" outputs = %d (%d expected)",
                Q, Q_expected);
         errors = errors + 1;
       end
       vectornum = vectornum + 1;
       if (testvectors[vectornum] === 'bx) begin
          $display("%d tests completed with %d errors", vectornum, errors);
          $finish;
       end
    end
endmodule