data/full_repos/permissive/481490387/lab03/simulation/src/better_booth_scala/better_booth_scala.v
data/verilator_xmls/f350f7ea-6ed0-4f0e-bf5a-cc24c93da96f.xml
module BetterBooth(
  input         clock,
  input         reset,
  input  [15:0] io_x,
  input  [15:0] io_y,
  output        io_busy,
  input         io_start,
  output [31:0] io_z
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
`endif
  reg [18:0] yReg;
  reg [31:0] sumReg;
  reg [3:0] cnt;
  reg [1:0] state;
  wire [1:0] _T = io_start ? 2'h1 : 2'h0;
  wire  _nextState_T = 2'h0 == state;
  wire  _nextState_T_2 = 2'h1 == state;
  wire  _nextState_T_4 = 2'h2 == state;
  reg [31:0] xReg;
  reg [31:0] lastResultReg;
  wire [15:0] _xReg_T = io_x;
  wire [16:0] _yReg_T = {io_y, 1'h0};
  wire [49:0] _yReg_T_4 = $signed(io_y) < 16'sh0 ? 50'h60000 : 50'h0;
  wire [49:0] _GEN_16 = {{33'd0}, _yReg_T};
  wire [49:0] _yReg_T_6 = _GEN_16 + _yReg_T_4;
  wire [31:0] _T_10 = 32'sh0 - $signed(xReg);
  wire [31:0] _T_11 = 32'sh0 - $signed(xReg);
  wire  _T_13 = ~reset;
  wire [32:0] _T_15 = {$signed(xReg), 1'h0};
  wire [32:0] _T_19 = 33'sh0 - $signed(_T_15);
  wire [31:0] _T_27 = 3'h1 == yReg[2:0] ? $signed(xReg) : $signed(32'sh0);
  wire [31:0] _T_29 = 3'h2 == yReg[2:0] ? $signed(xReg) : $signed(_T_27);
  wire [32:0] _T_31 = 3'h3 == yReg[2:0] ? $signed(_T_15) : $signed({{1{_T_29[31]}},_T_29});
  wire [32:0] _T_33 = 3'h4 == yReg[2:0] ? $signed(_T_19) : $signed(_T_31);
  wire [32:0] _T_35 = 3'h5 == yReg[2:0] ? $signed({{1{_T_10[31]}},_T_10}) : $signed(_T_33);
  wire [32:0] _add_T_1 = 3'h6 == yReg[2:0] ? $signed({{1{_T_10[31]}},_T_10}) : $signed(_T_35);
  wire [4:0] _add_T_2 = {cnt, 1'h0};
  wire [31:0] _add_WIRE = _add_T_1[31:0];
  wire [62:0] _GEN_7 = {{31{_add_WIRE[31]}},_add_WIRE};
  wire [62:0] add = $signed(_GEN_7) << _add_T_2;
  wire [62:0] _GEN_18 = {{31{sumReg[31]}},sumReg};
  wire [62:0] _sumReg_T_2 = $signed(_GEN_18) + $signed(add);
  wire [18:0] _yReg_T_7 = {{2'd0}, yReg[18:2]};
  wire [3:0] _cnt_T_1 = cnt + 4'h1;
  wire [31:0] _GEN_1 = _nextState_T_4 ? sumReg : 32'h0;
  wire [62:0] _GEN_4 = _nextState_T_2 ? $signed(_sumReg_T_2) : $signed({{31{sumReg[31]}},sumReg});
  wire [18:0] _GEN_5 = _nextState_T_2 ? _yReg_T_7 : yReg;
  wire [31:0] _GEN_8 = _nextState_T_2 ? 32'h0 : _GEN_1;
  wire [49:0] _GEN_12 = _nextState_T ? _yReg_T_6 : {{31'd0}, _GEN_5};
  wire [62:0] _GEN_13 = _nextState_T ? $signed(63'sh0) : $signed(_GEN_4);
  wire [49:0] _GEN_20 = reset ? 50'h0 : _GEN_12;
  wire [62:0] _GEN_21 = reset ? $signed(63'sh0) : $signed(_GEN_13);
  wire  _GEN_23 = ~_nextState_T;
  wire  _GEN_24 = ~_nextState_T & _nextState_T_2;
  assign io_busy = _nextState_T ? 1'h0 : _nextState_T_2;
  assign io_z = _nextState_T ? lastResultReg : _GEN_8;
  always @(posedge clock) begin
    yReg <= _GEN_20[18:0];
    sumReg <= _GEN_21[31:0];
    if (reset) begin
      cnt <= 4'h0;
    end else if (_nextState_T) begin
      cnt <= 4'h0;
    end else if (_nextState_T_2) begin
      cnt <= _cnt_T_1;
    end else if (_nextState_T_4) begin
      cnt <= 4'h0;
    end
    if (reset) begin
      state <= 2'h0;
    end else if (2'h2 == state) begin
      state <= 2'h0;
    end else if (2'h1 == state) begin
      if (cnt == 4'h8) begin
        state <= 2'h2;
      end else begin
        state <= 2'h1;
      end
    end else if (2'h0 == state) begin
      state <= _T;
    end else begin
      state <= 2'h0;
    end
    if (reset) begin
      xReg <= 32'sh0;
    end else if (_nextState_T) begin
      xReg <= {{16{_xReg_T[15]}},_xReg_T};
    end
    if (reset) begin
      lastResultReg <= 32'h0;
    end else if (!(_nextState_T)) begin
      if (_nextState_T_2) begin
        lastResultReg <= 32'h0;
      end else if (_nextState_T_4) begin
        lastResultReg <= sumReg;
      end
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~_nextState_T & _nextState_T_2 & ~reset) begin
          $fwrite(32'h80000002,"[%d state=%b], yReg=%b, yRegLast=%b, x=%b, -x=%b\n",cnt,state,yReg,yReg[2:0],xReg,_T_11
            );
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_24 & _T_13) begin
          $fwrite(32'h80000002,"yRegExtra = %b, addValue = %b, sum = %b\n",yReg,add,sumReg);
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_23 & ~_nextState_T_2 & _nextState_T_4 & _T_13) begin
          $fwrite(32'h80000002,"result = %b\n",sumReg);
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  yReg = _RAND_0[18:0];
  _RAND_1 = {1{`RANDOM}};
  sumReg = _RAND_1[31:0];
  _RAND_2 = {1{`RANDOM}};
  cnt = _RAND_2[3:0];
  _RAND_3 = {1{`RANDOM}};
  state = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  xReg = _RAND_4[31:0];
  _RAND_5 = {1{`RANDOM}};
  lastResultReg = _RAND_5[31:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module BetterBooth(
  input         clock,
  input         reset,
  input  [15:0] io_x,
  input  [15:0] io_y,
  output        io_busy,
  input         io_start,
  output [31:0] io_z
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
`endif
  reg [18:0] yReg;
  reg [31:0] sumReg;
  reg [3:0] cnt;
  reg [1:0] state;
  wire [1:0] _T = io_start ? 2'h1 : 2'h0;
  wire  _nextState_T = 2'h0 == state;
  wire  _nextState_T_2 = 2'h1 == state;
  wire  _nextState_T_4 = 2'h2 == state;
  reg [31:0] xReg;
  reg [31:0] lastResultReg;
  wire [15:0] _xReg_T = io_x;
  wire [16:0] _yReg_T = {io_y, 1'h0};
  wire [49:0] _yReg_T_4 = $signed(io_y) < 16'sh0 ? 50'h60000 : 50'h0;
  wire [49:0] _GEN_16 = {{33'd0}, _yReg_T};
  wire [49:0] _yReg_T_6 = _GEN_16 + _yReg_T_4;
  wire [31:0] _T_10 = 32'sh0 - $signed(xReg);
  wire [31:0] _T_11 = 32'sh0 - $signed(xReg);
  wire  _T_13 = ~reset;
  wire [32:0] _T_15 = {$signed(xReg), 1'h0};
  wire [32:0] _T_19 = 33'sh0 - $signed(_T_15);
  wire [31:0] _T_27 = 3'h1 == yReg[2:0] ? $signed(xReg) : $signed(32'sh0);
  wire [31:0] _T_29 = 3'h2 == yReg[2:0] ? $signed(xReg) : $signed(_T_27);
  wire [32:0] _T_31 = 3'h3 == yReg[2:0] ? $signed(_T_15) : $signed({{1{_T_29[31]}},_T_29});
  wire [32:0] _T_33 = 3'h4 == yReg[2:0] ? $signed(_T_19) : $signed(_T_31);
  wire [32:0] _T_35 = 3'h5 == yReg[2:0] ? $signed({{1{_T_10[31]}},_T_10}) : $signed(_T_33);
  wire [32:0] _add_T_1 = 3'h6 == yReg[2:0] ? $signed({{1{_T_10[31]}},_T_10}) : $signed(_T_35);
  wire [4:0] _add_T_2 = {cnt, 1'h0};
  wire [31:0] _add_WIRE = _add_T_1[31:0];
  wire [62:0] _GEN_7 = {{31{_add_WIRE[31]}},_add_WIRE};
  wire [62:0] add = $signed(_GEN_7) << _add_T_2;
  wire [62:0] _GEN_18 = {{31{sumReg[31]}},sumReg};
  wire [62:0] _sumReg_T_2 = $signed(_GEN_18) + $signed(add);
  wire [18:0] _yReg_T_7 = {{2'd0}, yReg[18:2]};
  wire [3:0] _cnt_T_1 = cnt + 4'h1;
  wire [31:0] _GEN_1 = _nextState_T_4 ? sumReg : 32'h0;
  wire [62:0] _GEN_4 = _nextState_T_2 ? $signed(_sumReg_T_2) : $signed({{31{sumReg[31]}},sumReg});
  wire [18:0] _GEN_5 = _nextState_T_2 ? _yReg_T_7 : yReg;
  wire [31:0] _GEN_8 = _nextState_T_2 ? 32'h0 : _GEN_1;
  wire [49:0] _GEN_12 = _nextState_T ? _yReg_T_6 : {{31'd0}, _GEN_5};
  wire [62:0] _GEN_13 = _nextState_T ? $signed(63'sh0) : $signed(_GEN_4);
  wire [49:0] _GEN_20 = reset ? 50'h0 : _GEN_12;
  wire [62:0] _GEN_21 = reset ? $signed(63'sh0) : $signed(_GEN_13);
  wire  _GEN_23 = ~_nextState_T;
  wire  _GEN_24 = ~_nextState_T & _nextState_T_2;
  assign io_busy = _nextState_T ? 1'h0 : _nextState_T_2;
  assign io_z = _nextState_T ? lastResultReg : _GEN_8;
  always @(posedge clock) begin
    yReg <= _GEN_20[18:0];
    sumReg <= _GEN_21[31:0];
    if (reset) begin
      cnt <= 4'h0;
    end else if (_nextState_T) begin
      cnt <= 4'h0;
    end else if (_nextState_T_2) begin
      cnt <= _cnt_T_1;
    end else if (_nextState_T_4) begin
      cnt <= 4'h0;
    end
    if (reset) begin
      state <= 2'h0;
    end else if (2'h2 == state) begin
      state <= 2'h0;
    end else if (2'h1 == state) begin
      if (cnt == 4'h8) begin
        state <= 2'h2;
      end else begin
        state <= 2'h1;
      end
    end else if (2'h0 == state) begin
      state <= _T;
    end else begin
      state <= 2'h0;
    end
    if (reset) begin
      xReg <= 32'sh0;
    end else if (_nextState_T) begin
      xReg <= {{16{_xReg_T[15]}},_xReg_T};
    end
    if (reset) begin
      lastResultReg <= 32'h0;
    end else if (!(_nextState_T)) begin
      if (_nextState_T_2) begin
        lastResultReg <= 32'h0;
      end else if (_nextState_T_4) begin
        lastResultReg <= sumReg;
      end
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~_nextState_T & _nextState_T_2 & ~reset) begin
          $fwrite(32'h80000002,"[%d state=%b], yReg=%b, yRegLast=%b, x=%b, -x=%b\n",cnt,state,yReg,yReg[2:0],xReg,_T_11
            );
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_24 & _T_13) begin
          $fwrite(32'h80000002,"yRegExtra = %b, addValue = %b, sum = %b\n",yReg,add,sumReg);
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_23 & ~_nextState_T_2 & _nextState_T_4 & _T_13) begin
          $fwrite(32'h80000002,"result = %b\n",sumReg);
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  yReg = _RAND_0[18:0];
  _RAND_1 = {1{`RANDOM}};
  sumReg = _RAND_1[31:0];
  _RAND_2 = {1{`RANDOM}};
  cnt = _RAND_2[3:0];
  _RAND_3 = {1{`RANDOM}};
  state = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  xReg = _RAND_4[31:0];
  _RAND_5 = {1{`RANDOM}};
  lastResultReg = _RAND_5[31:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule