data/full_repos/permissive/425928416/verilog/rtl/jacaranda-8/alu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/425928416/verilog/rtl/jacaranda-8/alu.v:32: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s EQ generates 1 bits.\n                                                                                     : ... In instance alu\n            4\'b0111: execute = (rd == rs);\n                             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
function [7:0] execute(input [7:0] rd, input [7:0] rs, input [3:0] alu_ctrl);
        begin
            case(alu_ctrl)
            4'b0000: execute = rd + rs;
            4'b0001: execute = rd & rs;
            4'b0010: execute = rd | rs;
            4'b0011: execute = ~rs;
            4'b0100: execute = rd << rs;
            4'b0101: execute = rd >> rs;
            4'b0110: execute = $signed(rd) >>> $signed(rs);
            4'b0111: execute = (rd == rs);
            4'b1000: execute = rd - rs;
            default: execute = 8'b0000_0000;
            endcase
        end
    endfunction
function [7:0] execute(input [7:0] rd, input [7:0] rs, input [3:0] alu_ctrl);

        begin
            case(alu_ctrl)
            4'b0000: execute = rd + rs;
            4'b0001: execute = rd & rs;
            4'b0010: execute = rd | rs;
            4'b0011: execute = ~rs;
            4'b0100: execute = rd << rs;
            4'b0101: execute = rd >> rs;
            4'b0110: execute = $signed(rd) >>> $signed(rs);
            4'b0111: execute = (rd == rs);
            4'b1000: execute = rd - rs;
            default: execute = 8'b0000_0000;
            endcase
        end
    endfunction