data/full_repos/permissive/515599642/Simple CPU module using Verilog/Shift_Register.v
1: b'%Error: Cannot find file containing module: CPU\n        ... Looked in:\n             data/full_repos/permissive/515599642/Simple/CPU\n             data/full_repos/permissive/515599642/Simple/CPU.v\n             data/full_repos/permissive/515599642/Simple/CPU.sv\n             CPU\n             CPU.v\n             CPU.sv\n             obj_dir/CPU\n             obj_dir/CPU.v\n             obj_dir/CPU.sv\n%Error: Cannot find file containing module: module\n%Error: Cannot find file containing module: using\n%Error: Cannot find file containing module: Verilog,data/full_repos/permissive/515599642\n%Error: Cannot find file containing module: data/full_repos/permissive/515599642/Simple\n%Error: Cannot find file containing module: Verilog/Shift_Register.v\n%Error: Exiting due to 6 error(s)\n'
module Shift_Reg(X, SHIFT, S );

input [3:0] X;
input [1:0] SHIFT;
output  reg [3:0] S;

always@(*) begin
case(SHIFT)
       2'b00:
	 S = X;  
       2'b01:
	 S = X << 1;
       2'b10:
	 S = X << 2; 
       2'b11:
	 S = X << 3;
 endcase
 end
endmodule
module Shift_Reg(X, SHIFT, S );


input [3:0] X;
input [1:0] SHIFT;
output  reg [3:0] S;

always@(*) begin
case(SHIFT)
       2'b00:
	 S = X;  
       2'b01:
	 S = X << 1;
       2'b10:
	 S = X << 2; 
       2'b11:
	 S = X << 3;
 endcase
 end
endmodule