data/full_repos/permissive/514313792/prj_qsys/avalon_isp_lite/isp_lite/isp_gamma.v
data/verilator_xmls/bdc7b6f6-9011-4eac-a422-44a4f50a3d78.xml
module isp_gamma
#(
	parameter BITS = 8,
	parameter WIDTH = 1280,
	parameter HEIGHT = 960
)
(
	input pclk,
	input rst_n,

	input in_href,
	input in_vsync,
	input [BITS-1:0] in_y,
	input [BITS-1:0] in_u,
	input [BITS-1:0] in_v,

	output out_href,
	output out_vsync,
	output [BITS-1:0] out_y,
	output [BITS-1:0] out_u,
	output [BITS-1:0] out_v
);

	wire [BITS-1:0] gamma_y;
	isp_gamma_lut_y #(BITS) lut_y(in_y, gamma_y);

	reg [BITS-1:0] data_y;
	reg [BITS-1:0] data_u;
	reg [BITS-1:0] data_v;
	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n) begin
			data_y <= 0;
			data_u <= 0;
			data_v <= 0;
		end
		else begin
			data_y <= gamma_y;
			data_u <= in_u;
			data_v <= in_v;
		end
	end


	reg href_dly;
	reg vsync_dly;
	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n) begin
			href_dly <= 0;
			vsync_dly <= 0;
		end
		else begin
			href_dly <= in_href;
			vsync_dly <= in_vsync;
		end
	end

	assign out_href = href_dly;
	assign out_vsync = vsync_dly;
	assign out_y = out_href ? data_y : {BITS{1'b0}};
	assign out_u = out_href ? data_u : {BITS{1'b0}};
	assign out_v = out_href ? data_v : {BITS{1'b0}};
endmodule
module isp_gamma
#(
	parameter BITS = 8,
	parameter WIDTH = 1280,
	parameter HEIGHT = 960
)
(
	input pclk,
	input rst_n,

	input in_href,
	input in_vsync,
	input [BITS-1:0] in_y,
	input [BITS-1:0] in_u,
	input [BITS-1:0] in_v,

	output out_href,
	output out_vsync,
	output [BITS-1:0] out_y,
	output [BITS-1:0] out_u,
	output [BITS-1:0] out_v
);


	wire [BITS-1:0] gamma_y;
	isp_gamma_lut_y #(BITS) lut_y(in_y, gamma_y);

	reg [BITS-1:0] data_y;
	reg [BITS-1:0] data_u;
	reg [BITS-1:0] data_v;
	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n) begin
			data_y <= 0;
			data_u <= 0;
			data_v <= 0;
		end
		else begin
			data_y <= gamma_y;
			data_u <= in_u;
			data_v <= in_v;
		end
	end


	reg href_dly;
	reg vsync_dly;
	always @ (posedge pclk or negedge rst_n) begin
		if (!rst_n) begin
			href_dly <= 0;
			vsync_dly <= 0;
		end
		else begin
			href_dly <= in_href;
			vsync_dly <= in_vsync;
		end
	end

	assign out_href = href_dly;
	assign out_vsync = vsync_dly;
	assign out_y = out_href ? data_y : {BITS{1'b0}};
	assign out_u = out_href ? data_u : {BITS{1'b0}};
	assign out_v = out_href ? data_v : {BITS{1'b0}};
endmodule