data/full_repos/permissive/468929885/verilog/rtl _bak/c_elem.v
1: b'%Error: Cannot find file containing module: _bak,data/full_repos/permissive/468929885\n        ... Looked in:\n             data/full_repos/permissive/468929885/verilog/rtl/_bak,data/full_repos/permissive/468929885\n             data/full_repos/permissive/468929885/verilog/rtl/_bak,data/full_repos/permissive/468929885.v\n             data/full_repos/permissive/468929885/verilog/rtl/_bak,data/full_repos/permissive/468929885.sv\n             _bak,data/full_repos/permissive/468929885\n             _bak,data/full_repos/permissive/468929885.v\n             _bak,data/full_repos/permissive/468929885.sv\n             obj_dir/_bak,data/full_repos/permissive/468929885\n             obj_dir/_bak,data/full_repos/permissive/468929885.v\n             obj_dir/_bak,data/full_repos/permissive/468929885.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/468929885/verilog/rtl\n%Error: Cannot find file containing module: _bak/c_elem.v\n%Error: Exiting due to 3 error(s)\n'
module c_elem#(
	parameter						IN_NUM = 2
)
(

	input							rst,

	input	[IN_NUM-1 : 0]					in,

	output							out

);


reg phase = 0;
wire click;

wire [IN_NUM-1 : 0] in_rst;
assign in_rst = in & {IN_NUM{!rst}};

assign click = ((&in_rst) & !phase) | (&(~in_rst) & phase);
assign out = phase;

always@(posedge click)
begin
	phase <= !phase;
end

endmodule
module c_elem#(
	parameter						IN_NUM = 2
)
(

	input							rst,

	input	[IN_NUM-1 : 0]					in,

	output							out

);



reg phase = 0;
wire click;

wire [IN_NUM-1 : 0] in_rst;
assign in_rst = in & {IN_NUM{!rst}};

assign click = ((&in_rst) & !phase) | (&(~in_rst) & phase);
assign out = phase;

always@(posedge click)
begin
	phase <= !phase;
end

endmodule