data/full_repos/permissive/451970862/rtl/common/rst_n_sync.v
data/verilator_xmls/76b35882-b792-4ee6-b143-49451faf24d8.xml
module rst_n_sync(
  input   clk,
  input   rst_n_async,
  output  rst_n_sync
);

reg   r1;
reg   r2;

always @ (posedge clk or negedge rst_n_async) begin
  if(!rst_n_async) begin
    r1  <=  1'b0;
    r2  <=  1'b0;
  end
  else begin
    r1  <=  1'b1;
    r2  <=  r1;
  end
end

assign  rst_n_sync  = r2;

endmodule
module rst_n_sync(
  input   clk,
  input   rst_n_async,
  output  rst_n_sync
);


reg   r1;
reg   r2;

always @ (posedge clk or negedge rst_n_async) begin
  if(!rst_n_async) begin
    r1  <=  1'b0;
    r2  <=  1'b0;
  end
  else begin
    r1  <=  1'b1;
    r2  <=  r1;
  end
end

assign  rst_n_sync  = r2;

endmodule