data/full_repos/permissive/507203156/01-Fuxi_sift_hw_sim/ip_core/fifo_v2/sim/sim_src/m7s_sync_single.v
data/verilator_xmls/77d91c63-0849-47fa-b7db-43289c18c18b.xml
module m7s_sync_single (
     dst_rst_n
    ,dst_clk
    ,src_dat
    ,dst_dat
    );




parameter SYNC_BW =1;
parameter DEFAULT_VALUE='b0;




input                  dst_rst_n;
input                  dst_clk;
input   [SYNC_BW-1:0]  src_dat;
output  [SYNC_BW-1:0]  dst_dat;

reg     [SYNC_BW-1:0] synchronizer_tmp_stage1;
reg     [SYNC_BW-1:0] dst_dat;

always @ (posedge dst_clk or negedge dst_rst_n) begin
   if(~dst_rst_n) begin
       synchronizer_tmp_stage1 <= `DLY DEFAULT_VALUE;
       dst_dat    <= `DLY DEFAULT_VALUE;
   end else begin
       synchronizer_tmp_stage1 <= `DLY src_dat;
       dst_dat    <= `DLY synchronizer_tmp_stage1;
   end
end
endmodule
module m7s_sync_single (
     dst_rst_n
    ,dst_clk
    ,src_dat
    ,dst_dat
    );





parameter SYNC_BW =1;
parameter DEFAULT_VALUE='b0;




input                  dst_rst_n;
input                  dst_clk;
input   [SYNC_BW-1:0]  src_dat;
output  [SYNC_BW-1:0]  dst_dat;

reg     [SYNC_BW-1:0] synchronizer_tmp_stage1;
reg     [SYNC_BW-1:0] dst_dat;

always @ (posedge dst_clk or negedge dst_rst_n) begin
   if(~dst_rst_n) begin
       synchronizer_tmp_stage1 <= `DLY DEFAULT_VALUE;
       dst_dat    <= `DLY DEFAULT_VALUE;
   end else begin
       synchronizer_tmp_stage1 <= `DLY src_dat;
       dst_dat    <= `DLY synchronizer_tmp_stage1;
   end
end
endmodule