data/full_repos/permissive/469273213/alu/rtl/alu_tb.v
1: b'%Error: data/full_repos/permissive/469273213/alu/rtl/alu_tb.v:15: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("alu.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/469273213/alu/rtl/alu_tb.v:16: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, alu_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/469273213/alu/rtl/alu_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #2 rst_n = 1\'b0; #10 rst_n = 1\'b1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/469273213/alu/rtl/alu_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #2 rst_n = 1\'b0; #10 rst_n = 1\'b1;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/469273213/alu/rtl/alu_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n            #10 opcode = i;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/469273213/alu/rtl/alu_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #10 $finish();\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/469273213/alu/rtl/alu_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n        forever #5 clk = ~clk;\n                ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu_tb;

    parameter WIDTH = 16;
    integer i;
    reg     [WIDTH-1:0] in0, in1;
    reg     [2:0] opcode;
    reg     clk, rst_n;
    wire    [WIDTH-1:0] out;
    wire    overflow;

    initial begin
        $dumpfile("alu.vcd");
        $dumpvars(0, alu_tb);
        clk = 1'b0; rst_n = 1'b1; opcode = 3'b0;
        in0 = 'd0; in1 = 'd0;
        #2 rst_n = 1'b0; #10 rst_n = 1'b1;
        in0 = 'd20; in1 = 'd4;
        for (i = 0; i<=7; i = i+1) begin
            #10 opcode = i;
        end
        #10 $finish();
    end

    initial begin
        forever #5 clk = ~clk;
    end

    alu #(.WIDTH(WIDTH)) alu_ut (.clk(clk), .rst_n(rst_n), .in0(in0), .in1(in1), .opcode(opcode), .out(out), .overflow(overflow));

endmodule
module alu_tb;


    parameter WIDTH = 16;
    integer i;
    reg     [WIDTH-1:0] in0, in1;
    reg     [2:0] opcode;
    reg     clk, rst_n;
    wire    [WIDTH-1:0] out;
    wire    overflow;

    initial begin
        $dumpfile("alu.vcd");
        $dumpvars(0, alu_tb);
        clk = 1'b0; rst_n = 1'b1; opcode = 3'b0;
        in0 = 'd0; in1 = 'd0;
        #2 rst_n = 1'b0; #10 rst_n = 1'b1;
        in0 = 'd20; in1 = 'd4;
        for (i = 0; i<=7; i = i+1) begin
            #10 opcode = i;
        end
        #10 $finish();
    end

    initial begin
        forever #5 clk = ~clk;
    end

    alu #(.WIDTH(WIDTH)) alu_ut (.clk(clk), .rst_n(rst_n), .in0(in0), .in1(in1), .opcode(opcode), .out(out), .overflow(overflow));

endmodule