data/full_repos/permissive/456528918/RTL/SoC.v
1: b"%Error: data/full_repos/permissive/456528918/RTL/SoC.v:24: Cannot find file containing module: 'YD_core'\nYD_core u_YD_core\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/456528918/RTL,data/full_repos/permissive/456528918/YD_core\n             data/full_repos/permissive/456528918/RTL,data/full_repos/permissive/456528918/YD_core.v\n             data/full_repos/permissive/456528918/RTL,data/full_repos/permissive/456528918/YD_core.sv\n             YD_core\n             YD_core.v\n             YD_core.sv\n             obj_dir/YD_core\n             obj_dir/YD_core.v\n             obj_dir/YD_core.sv\n%Error: data/full_repos/permissive/456528918/RTL/SoC.v:37: Cannot find file containing module: 'dbus'\ndbus #(\n^~~~\n%Error: data/full_repos/permissive/456528918/RTL/SoC.v:56: Cannot find file containing module: 'ibus'\nibus #(\n^~~~\n%Error: Exiting due to 3 error(s)\n"
module SoC (
	input wire clk,
	input wire rst,

	input wire [15:0]gpio_in,
	output wire [15:0]gpio_out,

	output wire T0_PWM_P,
	output wire T0_PWM_N,
	output wire T1_PWM_P,
	output wire T1_PWM_N,

	input wire [3:0]intp_ext,
	input wire intp_s

);
parameter RAM_AW=7;
parameter ROM_AW=7;


wire [15:0]i_addr,i_dout,d_din,d_addr,d_dout;
wire d_we;
wire int_rdy,int_vld;
YD_core u_YD_core
(
	.clk    (clk),
	.rst    (rst),
	.i_addr (i_addr),
	.i_dout (i_dout),
	.d_din  (d_din),
	.d_addr (d_addr),
	.d_we   (d_we),
	.d_dout (d_dout),
	.int_vld(int_vld|intp_s),
	.int_rdy(int_rdy)
);
dbus #(
	.RAM_AW(RAM_AW)
) u_dbus (
	.clk      (clk),
	.rst      (rst),
	.din      (d_din),
	.addr     (d_addr),
	.we       (d_we),
	.dout     (d_dout),
	.gpio_in  (gpio_in),
	.gpio_out (gpio_out),
	.T0_PWM_P(T0_PWM_P),
	.T0_PWM_N(T0_PWM_N),
	.T1_PWM_P(T1_PWM_P),
	.T1_PWM_N(T1_PWM_N),
	.intp_ext(intp_ext),
	.int_rdy (int_rdy),
	.int_vld (int_vld)
);
ibus #(
	.ROM_AW(ROM_AW)
) u_ibus (
	.clk(clk), 
	.addr(i_addr), 
	.dout(i_dout)
);

endmodule
module SoC (
	input wire clk,
	input wire rst,

	input wire [15:0]gpio_in,
	output wire [15:0]gpio_out,

	output wire T0_PWM_P,
	output wire T0_PWM_N,
	output wire T1_PWM_P,
	output wire T1_PWM_N,

	input wire [3:0]intp_ext,
	input wire intp_s

);

parameter RAM_AW=7;
parameter ROM_AW=7;


wire [15:0]i_addr,i_dout,d_din,d_addr,d_dout;
wire d_we;
wire int_rdy,int_vld;
YD_core u_YD_core
(
	.clk    (clk),
	.rst    (rst),
	.i_addr (i_addr),
	.i_dout (i_dout),
	.d_din  (d_din),
	.d_addr (d_addr),
	.d_we   (d_we),
	.d_dout (d_dout),
	.int_vld(int_vld|intp_s),
	.int_rdy(int_rdy)
);
dbus #(
	.RAM_AW(RAM_AW)
) u_dbus (
	.clk      (clk),
	.rst      (rst),
	.din      (d_din),
	.addr     (d_addr),
	.we       (d_we),
	.dout     (d_dout),
	.gpio_in  (gpio_in),
	.gpio_out (gpio_out),
	.T0_PWM_P(T0_PWM_P),
	.T0_PWM_N(T0_PWM_N),
	.T1_PWM_P(T1_PWM_P),
	.T1_PWM_N(T1_PWM_N),
	.intp_ext(intp_ext),
	.int_rdy (int_rdy),
	.int_vld (int_vld)
);
ibus #(
	.ROM_AW(ROM_AW)
) u_ibus (
	.clk(clk), 
	.addr(i_addr), 
	.dout(i_dout)
);

endmodule