data/full_repos/permissive/450959760/32 bit alu/src/test_bench_slt.v
1: b'%Error: Cannot find file containing module: bit\n        ... Looked in:\n             data/full_repos/permissive/450959760/32/bit\n             data/full_repos/permissive/450959760/32/bit.v\n             data/full_repos/permissive/450959760/32/bit.sv\n             bit\n             bit.v\n             bit.sv\n             obj_dir/bit\n             obj_dir/bit.v\n             obj_dir/bit.sv\n%Error: Cannot find file containing module: alu/src,data/full_repos/permissive/450959760\n%Error: Cannot find file containing module: data/full_repos/permissive/450959760/32\n%Error: Cannot find file containing module: alu/src/test_bench_slt.v\n%Error: Exiting due to 4 error(s)\n'
module test_bench_slt();
reg [31:0]a,b; 
reg S0,S1,S2,Ci;
wire [31:0]F;
wire Co;
alu_32_bit ahmet (a, b,S0,S1,S2,Ci,F,Co);

initial begin
a = 32'b01000001000000010000000100000001; b = 32'b00100001011000010110000101100001; Ci=1'b1;  S0 = 1'b0; S1 = 1'b0; S2 = 1'b1;
#`DELAY;

a = 32'b00000001000000010000000100001111; b = 32'b11100001001000010110000001100001; Ci=1'b1;  S0 = 1'b0; S1 = 1'b0; S2 = 1'b1;
#`DELAY;

a = 32'b00100101000000010000000100000111; b = 32'b01100001011000010110000101100111; Ci=1'b1;  S0 = 1'b0; S1 = 1'b0; S2 = 1'b1;
#`DELAY;

a = 32'b10100101000100010000000100000111; b = 32'b01100001011001010110000101100111; Ci=1'b1;  S0 = 1'b0; S1 = 1'b0; S2 = 1'b1;
#`DELAY;

end

 
 
initial
begin
$monitor("time = %2d,a =%32b,b=%32b, B<A=%1b",$time,a,b,Co);
end
 
endmodule
module test_bench_slt();

reg [31:0]a,b; 
reg S0,S1,S2,Ci;
wire [31:0]F;
wire Co;
alu_32_bit ahmet (a, b,S0,S1,S2,Ci,F,Co);

initial begin
a = 32'b01000001000000010000000100000001; b = 32'b00100001011000010110000101100001; Ci=1'b1;  S0 = 1'b0; S1 = 1'b0; S2 = 1'b1;
#`DELAY;

a = 32'b00000001000000010000000100001111; b = 32'b11100001001000010110000001100001; Ci=1'b1;  S0 = 1'b0; S1 = 1'b0; S2 = 1'b1;
#`DELAY;

a = 32'b00100101000000010000000100000111; b = 32'b01100001011000010110000101100111; Ci=1'b1;  S0 = 1'b0; S1 = 1'b0; S2 = 1'b1;
#`DELAY;

a = 32'b10100101000100010000000100000111; b = 32'b01100001011001010110000101100111; Ci=1'b1;  S0 = 1'b0; S1 = 1'b0; S2 = 1'b1;
#`DELAY;

end

 
 
initial
begin
$monitor("time = %2d,a =%32b,b=%32b, B<A=%1b",$time,a,b,Co);
end
 
endmodule