data/full_repos/permissive/51449864/verilog/vga_noise.v
1: b"%Error: data/full_repos/permissive/51449864/verilog/vga_noise.v:48: Cannot find file containing module: 'noise_generator'\n noise_generator gen (\n ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/51449864/verilog,data/full_repos/permissive/51449864/noise_generator\n             data/full_repos/permissive/51449864/verilog,data/full_repos/permissive/51449864/noise_generator.v\n             data/full_repos/permissive/51449864/verilog,data/full_repos/permissive/51449864/noise_generator.sv\n             noise_generator\n             noise_generator.v\n             noise_generator.sv\n             obj_dir/noise_generator\n             obj_dir/noise_generator.v\n             obj_dir/noise_generator.sv\n%Error: Exiting due to 1 error(s)\n"
module vga_noise(clk, color, pause, vsync, hsync, style, test, audio_l, audio_r);

	input clk;
	output [7:0] color;
	input pause;
	input vsync, hsync;
	input style;
	input test;
	output audio_l, audio_r;
	
	reg [1:0] audio_data;

	reg [7:0] latch;
	reg [7:0] sr;
	
	reg [12:0] divider;
	
	wire noise_bit;
		
	noise_generator gen (
		.clk(clk),
		.reset(pause&vsync),
		.random_bit(noise_bit)
		);	


	always @(negedge clk)
	begin
	
		if(hsync)
			divider <= 0;
		else
			divider <= divider + 1;

	end


	always @(posedge divider[2])
	begin
		latch <= sr;
	end


	always @(posedge divider[12])
	begin
		if(!test && !pause)
		begin
			audio_data <= sr[1:0];
		end
	end

	always @(posedge clk)
	begin	
	
		if(style)
		begin
		
			if(test)
			begin

				sr <= {divider[9],divider[9],divider[9],divider[8],divider[8],divider[8],divider[7],divider[7]};
			end
			else
			begin

				sr[7:1] <= sr[6:0];
				sr[0] <= noise_bit;
			end
		end
		else
		begin
			if(test)
			begin

				sr <= {divider[5],divider[5],divider[5],divider[5],divider[5],divider[5],divider[5],divider[5]};
			end
			else
			begin
			

				sr <= {noise_bit,noise_bit,noise_bit,noise_bit,noise_bit,noise_bit,noise_bit,noise_bit};
			end
		end
		
	end

	assign color = latch;
	

	assign audio_l = audio_data[0];
	assign audio_r = audio_data[1];

endmodule
module vga_noise(clk, color, pause, vsync, hsync, style, test, audio_l, audio_r);


	input clk;
	output [7:0] color;
	input pause;
	input vsync, hsync;
	input style;
	input test;
	output audio_l, audio_r;
	
	reg [1:0] audio_data;

	reg [7:0] latch;
	reg [7:0] sr;
	
	reg [12:0] divider;
	
	wire noise_bit;
		
	noise_generator gen (
		.clk(clk),
		.reset(pause&vsync),
		.random_bit(noise_bit)
		);	


	always @(negedge clk)
	begin
	
		if(hsync)
			divider <= 0;
		else
			divider <= divider + 1;

	end


	always @(posedge divider[2])
	begin
		latch <= sr;
	end


	always @(posedge divider[12])
	begin
		if(!test && !pause)
		begin
			audio_data <= sr[1:0];
		end
	end

	always @(posedge clk)
	begin	
	
		if(style)
		begin
		
			if(test)
			begin

				sr <= {divider[9],divider[9],divider[9],divider[8],divider[8],divider[8],divider[7],divider[7]};
			end
			else
			begin

				sr[7:1] <= sr[6:0];
				sr[0] <= noise_bit;
			end
		end
		else
		begin
			if(test)
			begin

				sr <= {divider[5],divider[5],divider[5],divider[5],divider[5],divider[5],divider[5],divider[5]};
			end
			else
			begin
			

				sr <= {noise_bit,noise_bit,noise_bit,noise_bit,noise_bit,noise_bit,noise_bit,noise_bit};
			end
		end
		
	end

	assign color = latch;
	

	assign audio_l = audio_data[0];
	assign audio_r = audio_data[1];

endmodule