data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv
1: b'%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:7: Cannot find include file: noc_parameter.vh\n    `include "noc_parameter.vh" \n             ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog,data/full_repos/permissive/463204869/noc_parameter.vh\n             data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog,data/full_repos/permissive/463204869/noc_parameter.vh.v\n             data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog,data/full_repos/permissive/463204869/noc_parameter.vh.sv\n             noc_parameter.vh\n             noc_parameter.vh.v\n             noc_parameter.vh.sv\n             obj_dir/noc_parameter.vh\n             obj_dir/noc_parameter.vh.v\n             obj_dir/noc_parameter.vh.sv\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:8: syntax error, unexpected \',\', expecting \'[\'\n    ,parameter PORT_QUANT_R0 = 5,\n    ^\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:9: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter PORT_QUANT_R1  = 5,\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:10: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter PORT_QUANT_R2  = 5,\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:11: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter PORT_QUANT_R3  = 5,\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:12: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter SYNC_ROUTER    = 0\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:13: syntax error, unexpected \')\', expecting \';\'\n)\n^\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                                   reset_q_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:17: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire             [NOC_CHIPID_SIZE-1:0] home_chipid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:19: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile0_noc_fifo_in_data_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:20: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile0_noc_fifo_in_raddr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:21: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile0_noc_fifo_in_waddr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:22: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile0_noc_fifo_out_data_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:23: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile0_noc_fifo_out_raddr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:24: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile0_noc_fifo_out_waddr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:25: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile1_noc_fifo_in_data_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:26: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile1_noc_fifo_in_raddr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:27: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile1_noc_fifo_in_waddr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:28: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile1_noc_fifo_out_data_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:29: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile1_noc_fifo_out_raddr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:30: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile1_noc_fifo_out_waddr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:31: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile2_noc_fifo_in_data_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:32: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile2_noc_fifo_in_raddr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:33: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile2_noc_fifo_in_waddr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:34: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile2_noc_fifo_out_data_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:35: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile2_noc_fifo_out_raddr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:36: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile2_noc_fifo_out_waddr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:37: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile3_noc_fifo_in_data_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:38: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile3_noc_fifo_in_raddr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:39: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile3_noc_fifo_in_waddr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:40: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile3_noc_fifo_out_data_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:41: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile3_noc_fifo_out_raddr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:42: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile3_noc_fifo_out_waddr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:43: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile4_noc_fifo_in_data_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:44: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile4_noc_fifo_in_raddr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:45: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile4_noc_fifo_in_waddr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:46: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile4_noc_fifo_out_data_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:47: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile4_noc_fifo_out_raddr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:48: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile4_noc_fifo_out_waddr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:49: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile5_noc_fifo_in_data_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:50: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile5_noc_fifo_in_raddr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:51: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile5_noc_fifo_in_waddr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:52: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile5_noc_fifo_out_data_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:53: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile5_noc_fifo_out_raddr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:54: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile5_noc_fifo_out_waddr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:55: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile6_noc_fifo_in_data_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:56: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile6_noc_fifo_in_raddr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:57: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile6_noc_fifo_in_waddr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:58: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile6_noc_fifo_out_data_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/noc_network/source/rtl/systemverilog/onchip_network.sv:59: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile6_noc_fifo_out_raddr_o,\n    ^~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module onchip_network #(
    `include "noc_parameter.vh"
    ,parameter PORT_QUANT_R0 = 5,
    parameter PORT_QUANT_R1  = 5,
    parameter PORT_QUANT_R2  = 5,
    parameter PORT_QUANT_R3  = 5,
    parameter SYNC_ROUTER    = 0
)
(
    input  wire                                   clk_i,
    input  wire                                   reset_q_i,
    input  wire             [NOC_CHIPID_SIZE-1:0] home_chipid_i,

    output wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile0_noc_fifo_in_data_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile0_noc_fifo_in_raddr_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile0_noc_fifo_in_waddr_o,
    input  wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile0_noc_fifo_out_data_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile0_noc_fifo_out_raddr_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile0_noc_fifo_out_waddr_i,
    output wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile1_noc_fifo_in_data_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile1_noc_fifo_in_raddr_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile1_noc_fifo_in_waddr_o,
    input  wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile1_noc_fifo_out_data_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile1_noc_fifo_out_raddr_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile1_noc_fifo_out_waddr_i,
    output wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile2_noc_fifo_in_data_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile2_noc_fifo_in_raddr_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile2_noc_fifo_in_waddr_o,
    input  wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile2_noc_fifo_out_data_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile2_noc_fifo_out_raddr_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile2_noc_fifo_out_waddr_i,
    output wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile3_noc_fifo_in_data_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile3_noc_fifo_in_raddr_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile3_noc_fifo_in_waddr_o,
    input  wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile3_noc_fifo_out_data_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile3_noc_fifo_out_raddr_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile3_noc_fifo_out_waddr_i,
    output wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile4_noc_fifo_in_data_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile4_noc_fifo_in_raddr_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile4_noc_fifo_in_waddr_o,
    input  wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile4_noc_fifo_out_data_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile4_noc_fifo_out_raddr_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile4_noc_fifo_out_waddr_i,
    output wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile5_noc_fifo_in_data_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile5_noc_fifo_in_raddr_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile5_noc_fifo_in_waddr_o,
    input  wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile5_noc_fifo_out_data_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile5_noc_fifo_out_raddr_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile5_noc_fifo_out_waddr_i,
    output wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile6_noc_fifo_in_data_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile6_noc_fifo_in_raddr_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile6_noc_fifo_in_waddr_o,
    input  wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile6_noc_fifo_out_data_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile6_noc_fifo_out_raddr_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile6_noc_fifo_out_waddr_i,
    output wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile7_noc_fifo_in_data_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile7_noc_fifo_in_raddr_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile7_noc_fifo_in_waddr_o,
    input  wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile7_noc_fifo_out_data_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile7_noc_fifo_out_raddr_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile7_noc_fifo_out_waddr_i,
    output wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile8_noc_fifo_in_data_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile8_noc_fifo_in_raddr_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile8_noc_fifo_in_waddr_o,
    input  wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile8_noc_fifo_out_data_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile8_noc_fifo_out_raddr_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile8_noc_fifo_out_waddr_i,
    output wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile9_noc_fifo_in_data_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile9_noc_fifo_in_raddr_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile9_noc_fifo_in_waddr_o,
    input  wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile9_noc_fifo_out_data_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile9_noc_fifo_out_raddr_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile9_noc_fifo_out_waddr_i,
    output wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile10_noc_fifo_in_data_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile10_noc_fifo_in_raddr_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile10_noc_fifo_in_waddr_o,
    input  wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile10_noc_fifo_out_data_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile10_noc_fifo_out_raddr_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile10_noc_fifo_out_waddr_i,
    output wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile11_noc_fifo_in_data_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile11_noc_fifo_in_raddr_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile11_noc_fifo_in_waddr_o,
    input  wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile11_noc_fifo_out_data_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile11_noc_fifo_out_raddr_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile11_noc_fifo_out_waddr_i
);





    wire testmode_s = 1'b0;


    noc_link_if rx_if_R0[0:PORT_QUANT_R0-1]();
    noc_link_if rx_if_R1[0:PORT_QUANT_R1-1]();
    noc_link_if rx_if_R2[0:PORT_QUANT_R2-1]();
    noc_link_if rx_if_R3[0:PORT_QUANT_R3-1]();

    noc_link_if tx_if_R0[0:PORT_QUANT_R0-1]();
    noc_link_if tx_if_R1[0:PORT_QUANT_R1-1]();
    noc_link_if tx_if_R2[0:PORT_QUANT_R2-1]();
    noc_link_if tx_if_R3[0:PORT_QUANT_R3-1]();

















    assign rx_if_R0[0].fifo_write_addr = tile0_noc_fifo_out_waddr_i;
    assign rx_if_R0[0].fifo_read_data = tile0_noc_fifo_out_data_i;
    assign tile0_noc_fifo_out_raddr_o = rx_if_R0[0].fifo_read_addr;

    assign rx_if_R0[1].fifo_write_addr = tile1_noc_fifo_out_waddr_i;
    assign rx_if_R0[1].fifo_read_data = tile1_noc_fifo_out_data_i;
    assign tile1_noc_fifo_out_raddr_o = rx_if_R0[1].fifo_read_addr;

    assign rx_if_R0[2].fifo_write_addr = tile2_noc_fifo_out_waddr_i;
    assign rx_if_R0[2].fifo_read_data = tile2_noc_fifo_out_data_i;
    assign tile2_noc_fifo_out_raddr_o = rx_if_R0[2].fifo_read_addr;

    assign rx_if_R0[3].fifo_write_addr = tx_if_R1[4].fifo_write_addr;
    assign rx_if_R0[3].fifo_read_data = tx_if_R1[4].fifo_read_data;
    assign tx_if_R1[4].fifo_read_addr = rx_if_R0[3].fifo_read_addr;

    assign rx_if_R0[4].fifo_write_addr = tx_if_R2[3].fifo_write_addr;
    assign rx_if_R0[4].fifo_read_data = tx_if_R2[3].fifo_read_data;
    assign tx_if_R2[3].fifo_read_addr = rx_if_R0[4].fifo_read_addr;


    assign tile0_noc_fifo_in_waddr_o = tx_if_R0[0].fifo_write_addr;
    assign tile0_noc_fifo_in_data_o = tx_if_R0[0].fifo_read_data;
    assign tx_if_R0[0].fifo_read_addr = tile0_noc_fifo_in_raddr_i;

    assign tile1_noc_fifo_in_waddr_o = tx_if_R0[1].fifo_write_addr;
    assign tile1_noc_fifo_in_data_o = tx_if_R0[1].fifo_read_data;
    assign tx_if_R0[1].fifo_read_addr = tile1_noc_fifo_in_raddr_i;

    assign tile2_noc_fifo_in_waddr_o = tx_if_R0[2].fifo_write_addr;
    assign tile2_noc_fifo_in_data_o = tx_if_R0[2].fifo_read_data;
    assign tx_if_R0[2].fifo_read_addr = tile2_noc_fifo_in_raddr_i;

    assign rx_if_R1[4].fifo_write_addr = tx_if_R0[3].fifo_write_addr;
    assign rx_if_R1[4].fifo_read_data = tx_if_R0[3].fifo_read_data;
    assign tx_if_R0[3].fifo_read_addr = rx_if_R1[4].fifo_read_addr;

    assign rx_if_R2[3].fifo_write_addr = tx_if_R0[4].fifo_write_addr;
    assign rx_if_R2[3].fifo_read_data = tx_if_R0[4].fifo_read_data;
    assign tx_if_R0[4].fifo_read_addr = rx_if_R2[3].fifo_read_addr;

    router_wrap #(
        .PORT_QUANT         (PORT_QUANT_R0),
        .MODULES_PER_ROUTER (3),

        .LUT_RESET_VALUE    ({8'b00001000,
                              8'b00110000}),
        .DIRECTION_ADD_X    (0),
        .DIRECTION_ADD_Y    (1),
        .SYNC_ROUTER        (SYNC_ROUTER),
        .INSTANCE_NAME      ("R0")
    ) router_wrap_r0 (
        .clk_i              (clk_i),
        .reset_q_i          (reset_q_i),
        .testmode_i         (testmode_s),
        .home_chipid_i      (home_chipid_i),

        .rx_if              (rx_if_R0),
        .tx_if              (tx_if_R0)
    );



    assign rx_if_R1[0].fifo_write_addr = tile3_noc_fifo_out_waddr_i;
    assign rx_if_R1[0].fifo_read_data = tile3_noc_fifo_out_data_i;
    assign tile3_noc_fifo_out_raddr_o = rx_if_R1[0].fifo_read_addr;

    assign rx_if_R1[1].fifo_write_addr = tile4_noc_fifo_out_waddr_i;
    assign rx_if_R1[1].fifo_read_data = tile4_noc_fifo_out_data_i;
    assign tile4_noc_fifo_out_raddr_o = rx_if_R1[1].fifo_read_addr;

    assign rx_if_R1[2].fifo_write_addr = tile5_noc_fifo_out_waddr_i;
    assign rx_if_R1[2].fifo_read_data = tile5_noc_fifo_out_data_i;
    assign tile5_noc_fifo_out_raddr_o = rx_if_R1[2].fifo_read_addr;

    assign rx_if_R1[3].fifo_write_addr = tx_if_R3[3].fifo_write_addr;
    assign rx_if_R1[3].fifo_read_data = tx_if_R3[3].fifo_read_data;
    assign tx_if_R3[3].fifo_read_addr = rx_if_R1[3].fifo_read_addr;

    assign rx_if_R1[4].fifo_write_addr = tx_if_R0[3].fifo_write_addr;
    assign rx_if_R1[4].fifo_read_data = tx_if_R0[3].fifo_read_data;
    assign tx_if_R0[3].fifo_read_addr = rx_if_R1[4].fifo_read_addr;


    assign tile3_noc_fifo_in_waddr_o = tx_if_R1[0].fifo_write_addr;
    assign tile3_noc_fifo_in_data_o = tx_if_R1[0].fifo_read_data;
    assign tx_if_R1[0].fifo_read_addr = tile3_noc_fifo_in_raddr_i;

    assign tile4_noc_fifo_in_waddr_o = tx_if_R1[1].fifo_write_addr;
    assign tile4_noc_fifo_in_data_o = tx_if_R1[1].fifo_read_data;
    assign tx_if_R1[1].fifo_read_addr = tile4_noc_fifo_in_raddr_i;

    assign tile5_noc_fifo_in_waddr_o = tx_if_R1[2].fifo_write_addr;
    assign tile5_noc_fifo_in_data_o = tx_if_R1[2].fifo_read_data;
    assign tx_if_R1[2].fifo_read_addr = tile5_noc_fifo_in_raddr_i;

    assign rx_if_R3[3].fifo_write_addr = tx_if_R1[3].fifo_write_addr;
    assign rx_if_R3[3].fifo_read_data = tx_if_R1[3].fifo_read_data;
    assign tx_if_R1[3].fifo_read_addr = rx_if_R3[3].fifo_read_addr;

    assign rx_if_R0[3].fifo_write_addr = tx_if_R1[4].fifo_write_addr;
    assign rx_if_R0[3].fifo_read_data = tx_if_R1[4].fifo_read_data;
    assign tx_if_R1[4].fifo_read_addr = rx_if_R0[3].fifo_read_addr;

    router_wrap #(
        .PORT_QUANT         (PORT_QUANT_R1),
        .MODULES_PER_ROUTER (3),

        .LUT_RESET_VALUE    ({8'b00000110,
                              8'b00001000}),
        .DIRECTION_ADD_X    (1),
        .DIRECTION_ADD_Y    (1),
        .SYNC_ROUTER        (SYNC_ROUTER),
        .INSTANCE_NAME      ("R1")
    ) router_wrap_r1 (
        .clk_i              (clk_i),
        .reset_q_i          (reset_q_i),
        .testmode_i         (testmode_s),
        .home_chipid_i      (home_chipid_i),

        .rx_if              (rx_if_R1),
        .tx_if              (tx_if_R1)
    );




    assign rx_if_R2[0].fifo_write_addr = tile6_noc_fifo_out_waddr_i;
    assign rx_if_R2[0].fifo_read_data = tile6_noc_fifo_out_data_i;
    assign tile6_noc_fifo_out_raddr_o = rx_if_R2[0].fifo_read_addr;

    assign rx_if_R2[1].fifo_write_addr = tile7_noc_fifo_out_waddr_i;
    assign rx_if_R2[1].fifo_read_data = tile7_noc_fifo_out_data_i;
    assign tile7_noc_fifo_out_raddr_o = rx_if_R2[1].fifo_read_addr;

    assign rx_if_R2[2].fifo_write_addr = tile8_noc_fifo_out_waddr_i;
    assign rx_if_R2[2].fifo_read_data = tile8_noc_fifo_out_data_i;
    assign tile8_noc_fifo_out_raddr_o = rx_if_R2[2].fifo_read_addr;

    assign rx_if_R2[3].fifo_write_addr = tx_if_R0[4].fifo_write_addr;
    assign rx_if_R2[3].fifo_read_data = tx_if_R0[4].fifo_read_data;
    assign tx_if_R0[4].fifo_read_addr = rx_if_R2[3].fifo_read_addr;

    assign rx_if_R2[4].fifo_write_addr = tx_if_R3[4].fifo_write_addr;
    assign rx_if_R2[4].fifo_read_data = tx_if_R3[4].fifo_read_data;
    assign tx_if_R3[4].fifo_read_addr = rx_if_R2[4].fifo_read_addr;


    assign tile6_noc_fifo_in_waddr_o = tx_if_R2[0].fifo_write_addr;
    assign tile6_noc_fifo_in_data_o = tx_if_R2[0].fifo_read_data;
    assign tx_if_R2[0].fifo_read_addr = tile6_noc_fifo_in_raddr_i;

    assign tile7_noc_fifo_in_waddr_o = tx_if_R2[1].fifo_write_addr;
    assign tile7_noc_fifo_in_data_o = tx_if_R2[1].fifo_read_data;
    assign tx_if_R2[1].fifo_read_addr = tile7_noc_fifo_in_raddr_i;

    assign tile8_noc_fifo_in_waddr_o = tx_if_R2[2].fifo_write_addr;
    assign tile8_noc_fifo_in_data_o = tx_if_R2[2].fifo_read_data;
    assign tx_if_R2[2].fifo_read_addr = tile8_noc_fifo_in_raddr_i;

    assign rx_if_R0[4].fifo_write_addr = tx_if_R2[3].fifo_write_addr;
    assign rx_if_R0[4].fifo_read_data = tx_if_R2[3].fifo_read_data;
    assign tx_if_R2[3].fifo_read_addr = rx_if_R0[4].fifo_read_addr;

    assign rx_if_R3[4].fifo_write_addr = tx_if_R2[4].fifo_write_addr;
    assign rx_if_R3[4].fifo_read_data = tx_if_R2[4].fifo_read_data;
    assign tx_if_R2[4].fifo_read_addr = rx_if_R3[4].fifo_read_addr;

    router_wrap #(
        .PORT_QUANT         (PORT_QUANT_R2),
        .MODULES_PER_ROUTER (3),

        .LUT_RESET_VALUE    ({8'b01100000,
                              8'b10000000}),
        .DIRECTION_ADD_X    (0),
        .DIRECTION_ADD_Y    (0),
        .SYNC_ROUTER        (SYNC_ROUTER),
        .INSTANCE_NAME      ("R2")
    ) router_wrap_r2 (
        .clk_i              (clk_i),
        .reset_q_i          (reset_q_i),
        .testmode_i         (testmode_s),
        .home_chipid_i      (home_chipid_i),

        .rx_if              (rx_if_R2),
        .tx_if              (tx_if_R2)
    );



    assign rx_if_R3[0].fifo_write_addr = tile9_noc_fifo_out_waddr_i;
    assign rx_if_R3[0].fifo_read_data = tile9_noc_fifo_out_data_i;
    assign tile9_noc_fifo_out_raddr_o = rx_if_R3[0].fifo_read_addr;

    assign rx_if_R3[1].fifo_write_addr = tile10_noc_fifo_out_waddr_i;
    assign rx_if_R3[1].fifo_read_data = tile10_noc_fifo_out_data_i;
    assign tile10_noc_fifo_out_raddr_o = rx_if_R3[1].fifo_read_addr;

    assign rx_if_R3[2].fifo_write_addr = tile11_noc_fifo_out_waddr_i;
    assign rx_if_R3[2].fifo_read_data = tile11_noc_fifo_out_data_i;
    assign tile11_noc_fifo_out_raddr_o = rx_if_R3[2].fifo_read_addr;

    assign rx_if_R3[3].fifo_write_addr = tx_if_R1[3].fifo_write_addr;
    assign rx_if_R3[3].fifo_read_data = tx_if_R1[3].fifo_read_data;
    assign tx_if_R1[3].fifo_read_addr = rx_if_R3[3].fifo_read_addr;

    assign rx_if_R3[4].fifo_write_addr = tx_if_R2[4].fifo_write_addr;
    assign rx_if_R3[4].fifo_read_data = tx_if_R2[4].fifo_read_data;
    assign tx_if_R2[4].fifo_read_addr = rx_if_R3[4].fifo_read_addr;


    assign tile9_noc_fifo_in_waddr_o = tx_if_R3[0].fifo_write_addr;
    assign tile9_noc_fifo_in_data_o = tx_if_R3[0].fifo_read_data;
    assign tx_if_R3[0].fifo_read_addr = tile9_noc_fifo_in_raddr_i;

    assign tile10_noc_fifo_in_waddr_o = tx_if_R3[1].fifo_write_addr;
    assign tile10_noc_fifo_in_data_o = tx_if_R3[1].fifo_read_data;
    assign tx_if_R3[1].fifo_read_addr = tile10_noc_fifo_in_raddr_i;

    assign tile11_noc_fifo_in_waddr_o = tx_if_R3[2].fifo_write_addr;
    assign tile11_noc_fifo_in_data_o = tx_if_R3[2].fifo_read_data;
    assign tx_if_R3[2].fifo_read_addr = tile11_noc_fifo_in_raddr_i;

    assign rx_if_R1[3].fifo_write_addr = tx_if_R3[3].fifo_write_addr;
    assign rx_if_R1[3].fifo_read_data = tx_if_R3[3].fifo_read_data;
    assign tx_if_R3[3].fifo_read_addr = rx_if_R1[3].fifo_read_addr;

    assign rx_if_R2[4].fifo_write_addr = tx_if_R3[4].fifo_write_addr;
    assign rx_if_R2[4].fifo_read_data = tx_if_R3[4].fifo_read_data;
    assign tx_if_R3[4].fifo_read_addr = rx_if_R2[4].fifo_read_addr;

    router_wrap #(
        .PORT_QUANT         (PORT_QUANT_R3),
        .MODULES_PER_ROUTER (3),

        .LUT_RESET_VALUE    ({8'b00000011,
                              8'b10000000}),
        .DIRECTION_ADD_X    (1),
        .DIRECTION_ADD_Y    (0),
        .SYNC_ROUTER        (SYNC_ROUTER),
        .INSTANCE_NAME      ("R3")
    ) router_wrap_r3 (
        .clk_i              (clk_i),
        .reset_q_i          (reset_q_i),
        .testmode_i         (testmode_s),
        .home_chipid_i      (home_chipid_i),

        .rx_if              (rx_if_R3),
        .tx_if              (tx_if_R3)
    );

endmodule
module onchip_network #(
    `include "noc_parameter.vh"
    ,parameter PORT_QUANT_R0 = 5,
    parameter PORT_QUANT_R1  = 5,
    parameter PORT_QUANT_R2  = 5,
    parameter PORT_QUANT_R3  = 5,
    parameter SYNC_ROUTER    = 0
)
(
    input  wire                                   clk_i,
    input  wire                                   reset_q_i,
    input  wire             [NOC_CHIPID_SIZE-1:0] home_chipid_i,

    output wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile0_noc_fifo_in_data_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile0_noc_fifo_in_raddr_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile0_noc_fifo_in_waddr_o,
    input  wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile0_noc_fifo_out_data_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile0_noc_fifo_out_raddr_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile0_noc_fifo_out_waddr_i,
    output wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile1_noc_fifo_in_data_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile1_noc_fifo_in_raddr_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile1_noc_fifo_in_waddr_o,
    input  wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile1_noc_fifo_out_data_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile1_noc_fifo_out_raddr_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile1_noc_fifo_out_waddr_i,
    output wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile2_noc_fifo_in_data_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile2_noc_fifo_in_raddr_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile2_noc_fifo_in_waddr_o,
    input  wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile2_noc_fifo_out_data_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile2_noc_fifo_out_raddr_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile2_noc_fifo_out_waddr_i,
    output wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile3_noc_fifo_in_data_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile3_noc_fifo_in_raddr_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile3_noc_fifo_in_waddr_o,
    input  wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile3_noc_fifo_out_data_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile3_noc_fifo_out_raddr_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile3_noc_fifo_out_waddr_i,
    output wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile4_noc_fifo_in_data_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile4_noc_fifo_in_raddr_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile4_noc_fifo_in_waddr_o,
    input  wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile4_noc_fifo_out_data_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile4_noc_fifo_out_raddr_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile4_noc_fifo_out_waddr_i,
    output wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile5_noc_fifo_in_data_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile5_noc_fifo_in_raddr_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile5_noc_fifo_in_waddr_o,
    input  wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile5_noc_fifo_out_data_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile5_noc_fifo_out_raddr_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile5_noc_fifo_out_waddr_i,
    output wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile6_noc_fifo_in_data_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile6_noc_fifo_in_raddr_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile6_noc_fifo_in_waddr_o,
    input  wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile6_noc_fifo_out_data_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile6_noc_fifo_out_raddr_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile6_noc_fifo_out_waddr_i,
    output wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile7_noc_fifo_in_data_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile7_noc_fifo_in_raddr_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile7_noc_fifo_in_waddr_o,
    input  wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile7_noc_fifo_out_data_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile7_noc_fifo_out_raddr_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile7_noc_fifo_out_waddr_i,
    output wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile8_noc_fifo_in_data_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile8_noc_fifo_in_raddr_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile8_noc_fifo_in_waddr_o,
    input  wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile8_noc_fifo_out_data_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile8_noc_fifo_out_raddr_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile8_noc_fifo_out_waddr_i,
    output wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile9_noc_fifo_in_data_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile9_noc_fifo_in_raddr_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile9_noc_fifo_in_waddr_o,
    input  wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile9_noc_fifo_out_data_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile9_noc_fifo_out_raddr_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile9_noc_fifo_out_waddr_i,
    output wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile10_noc_fifo_in_data_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile10_noc_fifo_in_raddr_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile10_noc_fifo_in_waddr_o,
    input  wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile10_noc_fifo_out_data_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile10_noc_fifo_out_raddr_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile10_noc_fifo_out_waddr_i,
    output wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile11_noc_fifo_in_data_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile11_noc_fifo_in_raddr_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile11_noc_fifo_in_waddr_o,
    input  wire  [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] tile11_noc_fifo_out_data_i,
    output wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile11_noc_fifo_out_raddr_o,
    input  wire         [NOC_ASYNC_FIFO_AWIDTH:0] tile11_noc_fifo_out_waddr_i
);






    wire testmode_s = 1'b0;


    noc_link_if rx_if_R0[0:PORT_QUANT_R0-1]();
    noc_link_if rx_if_R1[0:PORT_QUANT_R1-1]();
    noc_link_if rx_if_R2[0:PORT_QUANT_R2-1]();
    noc_link_if rx_if_R3[0:PORT_QUANT_R3-1]();

    noc_link_if tx_if_R0[0:PORT_QUANT_R0-1]();
    noc_link_if tx_if_R1[0:PORT_QUANT_R1-1]();
    noc_link_if tx_if_R2[0:PORT_QUANT_R2-1]();
    noc_link_if tx_if_R3[0:PORT_QUANT_R3-1]();

















    assign rx_if_R0[0].fifo_write_addr = tile0_noc_fifo_out_waddr_i;
    assign rx_if_R0[0].fifo_read_data = tile0_noc_fifo_out_data_i;
    assign tile0_noc_fifo_out_raddr_o = rx_if_R0[0].fifo_read_addr;

    assign rx_if_R0[1].fifo_write_addr = tile1_noc_fifo_out_waddr_i;
    assign rx_if_R0[1].fifo_read_data = tile1_noc_fifo_out_data_i;
    assign tile1_noc_fifo_out_raddr_o = rx_if_R0[1].fifo_read_addr;

    assign rx_if_R0[2].fifo_write_addr = tile2_noc_fifo_out_waddr_i;
    assign rx_if_R0[2].fifo_read_data = tile2_noc_fifo_out_data_i;
    assign tile2_noc_fifo_out_raddr_o = rx_if_R0[2].fifo_read_addr;

    assign rx_if_R0[3].fifo_write_addr = tx_if_R1[4].fifo_write_addr;
    assign rx_if_R0[3].fifo_read_data = tx_if_R1[4].fifo_read_data;
    assign tx_if_R1[4].fifo_read_addr = rx_if_R0[3].fifo_read_addr;

    assign rx_if_R0[4].fifo_write_addr = tx_if_R2[3].fifo_write_addr;
    assign rx_if_R0[4].fifo_read_data = tx_if_R2[3].fifo_read_data;
    assign tx_if_R2[3].fifo_read_addr = rx_if_R0[4].fifo_read_addr;


    assign tile0_noc_fifo_in_waddr_o = tx_if_R0[0].fifo_write_addr;
    assign tile0_noc_fifo_in_data_o = tx_if_R0[0].fifo_read_data;
    assign tx_if_R0[0].fifo_read_addr = tile0_noc_fifo_in_raddr_i;

    assign tile1_noc_fifo_in_waddr_o = tx_if_R0[1].fifo_write_addr;
    assign tile1_noc_fifo_in_data_o = tx_if_R0[1].fifo_read_data;
    assign tx_if_R0[1].fifo_read_addr = tile1_noc_fifo_in_raddr_i;

    assign tile2_noc_fifo_in_waddr_o = tx_if_R0[2].fifo_write_addr;
    assign tile2_noc_fifo_in_data_o = tx_if_R0[2].fifo_read_data;
    assign tx_if_R0[2].fifo_read_addr = tile2_noc_fifo_in_raddr_i;

    assign rx_if_R1[4].fifo_write_addr = tx_if_R0[3].fifo_write_addr;
    assign rx_if_R1[4].fifo_read_data = tx_if_R0[3].fifo_read_data;
    assign tx_if_R0[3].fifo_read_addr = rx_if_R1[4].fifo_read_addr;

    assign rx_if_R2[3].fifo_write_addr = tx_if_R0[4].fifo_write_addr;
    assign rx_if_R2[3].fifo_read_data = tx_if_R0[4].fifo_read_data;
    assign tx_if_R0[4].fifo_read_addr = rx_if_R2[3].fifo_read_addr;

    router_wrap #(
        .PORT_QUANT         (PORT_QUANT_R0),
        .MODULES_PER_ROUTER (3),

        .LUT_RESET_VALUE    ({8'b00001000,
                              8'b00110000}),
        .DIRECTION_ADD_X    (0),
        .DIRECTION_ADD_Y    (1),
        .SYNC_ROUTER        (SYNC_ROUTER),
        .INSTANCE_NAME      ("R0")
    ) router_wrap_r0 (
        .clk_i              (clk_i),
        .reset_q_i          (reset_q_i),
        .testmode_i         (testmode_s),
        .home_chipid_i      (home_chipid_i),

        .rx_if              (rx_if_R0),
        .tx_if              (tx_if_R0)
    );



    assign rx_if_R1[0].fifo_write_addr = tile3_noc_fifo_out_waddr_i;
    assign rx_if_R1[0].fifo_read_data = tile3_noc_fifo_out_data_i;
    assign tile3_noc_fifo_out_raddr_o = rx_if_R1[0].fifo_read_addr;

    assign rx_if_R1[1].fifo_write_addr = tile4_noc_fifo_out_waddr_i;
    assign rx_if_R1[1].fifo_read_data = tile4_noc_fifo_out_data_i;
    assign tile4_noc_fifo_out_raddr_o = rx_if_R1[1].fifo_read_addr;

    assign rx_if_R1[2].fifo_write_addr = tile5_noc_fifo_out_waddr_i;
    assign rx_if_R1[2].fifo_read_data = tile5_noc_fifo_out_data_i;
    assign tile5_noc_fifo_out_raddr_o = rx_if_R1[2].fifo_read_addr;

    assign rx_if_R1[3].fifo_write_addr = tx_if_R3[3].fifo_write_addr;
    assign rx_if_R1[3].fifo_read_data = tx_if_R3[3].fifo_read_data;
    assign tx_if_R3[3].fifo_read_addr = rx_if_R1[3].fifo_read_addr;

    assign rx_if_R1[4].fifo_write_addr = tx_if_R0[3].fifo_write_addr;
    assign rx_if_R1[4].fifo_read_data = tx_if_R0[3].fifo_read_data;
    assign tx_if_R0[3].fifo_read_addr = rx_if_R1[4].fifo_read_addr;


    assign tile3_noc_fifo_in_waddr_o = tx_if_R1[0].fifo_write_addr;
    assign tile3_noc_fifo_in_data_o = tx_if_R1[0].fifo_read_data;
    assign tx_if_R1[0].fifo_read_addr = tile3_noc_fifo_in_raddr_i;

    assign tile4_noc_fifo_in_waddr_o = tx_if_R1[1].fifo_write_addr;
    assign tile4_noc_fifo_in_data_o = tx_if_R1[1].fifo_read_data;
    assign tx_if_R1[1].fifo_read_addr = tile4_noc_fifo_in_raddr_i;

    assign tile5_noc_fifo_in_waddr_o = tx_if_R1[2].fifo_write_addr;
    assign tile5_noc_fifo_in_data_o = tx_if_R1[2].fifo_read_data;
    assign tx_if_R1[2].fifo_read_addr = tile5_noc_fifo_in_raddr_i;

    assign rx_if_R3[3].fifo_write_addr = tx_if_R1[3].fifo_write_addr;
    assign rx_if_R3[3].fifo_read_data = tx_if_R1[3].fifo_read_data;
    assign tx_if_R1[3].fifo_read_addr = rx_if_R3[3].fifo_read_addr;

    assign rx_if_R0[3].fifo_write_addr = tx_if_R1[4].fifo_write_addr;
    assign rx_if_R0[3].fifo_read_data = tx_if_R1[4].fifo_read_data;
    assign tx_if_R1[4].fifo_read_addr = rx_if_R0[3].fifo_read_addr;

    router_wrap #(
        .PORT_QUANT         (PORT_QUANT_R1),
        .MODULES_PER_ROUTER (3),

        .LUT_RESET_VALUE    ({8'b00000110,
                              8'b00001000}),
        .DIRECTION_ADD_X    (1),
        .DIRECTION_ADD_Y    (1),
        .SYNC_ROUTER        (SYNC_ROUTER),
        .INSTANCE_NAME      ("R1")
    ) router_wrap_r1 (
        .clk_i              (clk_i),
        .reset_q_i          (reset_q_i),
        .testmode_i         (testmode_s),
        .home_chipid_i      (home_chipid_i),

        .rx_if              (rx_if_R1),
        .tx_if              (tx_if_R1)
    );




    assign rx_if_R2[0].fifo_write_addr = tile6_noc_fifo_out_waddr_i;
    assign rx_if_R2[0].fifo_read_data = tile6_noc_fifo_out_data_i;
    assign tile6_noc_fifo_out_raddr_o = rx_if_R2[0].fifo_read_addr;

    assign rx_if_R2[1].fifo_write_addr = tile7_noc_fifo_out_waddr_i;
    assign rx_if_R2[1].fifo_read_data = tile7_noc_fifo_out_data_i;
    assign tile7_noc_fifo_out_raddr_o = rx_if_R2[1].fifo_read_addr;

    assign rx_if_R2[2].fifo_write_addr = tile8_noc_fifo_out_waddr_i;
    assign rx_if_R2[2].fifo_read_data = tile8_noc_fifo_out_data_i;
    assign tile8_noc_fifo_out_raddr_o = rx_if_R2[2].fifo_read_addr;

    assign rx_if_R2[3].fifo_write_addr = tx_if_R0[4].fifo_write_addr;
    assign rx_if_R2[3].fifo_read_data = tx_if_R0[4].fifo_read_data;
    assign tx_if_R0[4].fifo_read_addr = rx_if_R2[3].fifo_read_addr;

    assign rx_if_R2[4].fifo_write_addr = tx_if_R3[4].fifo_write_addr;
    assign rx_if_R2[4].fifo_read_data = tx_if_R3[4].fifo_read_data;
    assign tx_if_R3[4].fifo_read_addr = rx_if_R2[4].fifo_read_addr;


    assign tile6_noc_fifo_in_waddr_o = tx_if_R2[0].fifo_write_addr;
    assign tile6_noc_fifo_in_data_o = tx_if_R2[0].fifo_read_data;
    assign tx_if_R2[0].fifo_read_addr = tile6_noc_fifo_in_raddr_i;

    assign tile7_noc_fifo_in_waddr_o = tx_if_R2[1].fifo_write_addr;
    assign tile7_noc_fifo_in_data_o = tx_if_R2[1].fifo_read_data;
    assign tx_if_R2[1].fifo_read_addr = tile7_noc_fifo_in_raddr_i;

    assign tile8_noc_fifo_in_waddr_o = tx_if_R2[2].fifo_write_addr;
    assign tile8_noc_fifo_in_data_o = tx_if_R2[2].fifo_read_data;
    assign tx_if_R2[2].fifo_read_addr = tile8_noc_fifo_in_raddr_i;

    assign rx_if_R0[4].fifo_write_addr = tx_if_R2[3].fifo_write_addr;
    assign rx_if_R0[4].fifo_read_data = tx_if_R2[3].fifo_read_data;
    assign tx_if_R2[3].fifo_read_addr = rx_if_R0[4].fifo_read_addr;

    assign rx_if_R3[4].fifo_write_addr = tx_if_R2[4].fifo_write_addr;
    assign rx_if_R3[4].fifo_read_data = tx_if_R2[4].fifo_read_data;
    assign tx_if_R2[4].fifo_read_addr = rx_if_R3[4].fifo_read_addr;

    router_wrap #(
        .PORT_QUANT         (PORT_QUANT_R2),
        .MODULES_PER_ROUTER (3),

        .LUT_RESET_VALUE    ({8'b01100000,
                              8'b10000000}),
        .DIRECTION_ADD_X    (0),
        .DIRECTION_ADD_Y    (0),
        .SYNC_ROUTER        (SYNC_ROUTER),
        .INSTANCE_NAME      ("R2")
    ) router_wrap_r2 (
        .clk_i              (clk_i),
        .reset_q_i          (reset_q_i),
        .testmode_i         (testmode_s),
        .home_chipid_i      (home_chipid_i),

        .rx_if              (rx_if_R2),
        .tx_if              (tx_if_R2)
    );



    assign rx_if_R3[0].fifo_write_addr = tile9_noc_fifo_out_waddr_i;
    assign rx_if_R3[0].fifo_read_data = tile9_noc_fifo_out_data_i;
    assign tile9_noc_fifo_out_raddr_o = rx_if_R3[0].fifo_read_addr;

    assign rx_if_R3[1].fifo_write_addr = tile10_noc_fifo_out_waddr_i;
    assign rx_if_R3[1].fifo_read_data = tile10_noc_fifo_out_data_i;
    assign tile10_noc_fifo_out_raddr_o = rx_if_R3[1].fifo_read_addr;

    assign rx_if_R3[2].fifo_write_addr = tile11_noc_fifo_out_waddr_i;
    assign rx_if_R3[2].fifo_read_data = tile11_noc_fifo_out_data_i;
    assign tile11_noc_fifo_out_raddr_o = rx_if_R3[2].fifo_read_addr;

    assign rx_if_R3[3].fifo_write_addr = tx_if_R1[3].fifo_write_addr;
    assign rx_if_R3[3].fifo_read_data = tx_if_R1[3].fifo_read_data;
    assign tx_if_R1[3].fifo_read_addr = rx_if_R3[3].fifo_read_addr;

    assign rx_if_R3[4].fifo_write_addr = tx_if_R2[4].fifo_write_addr;
    assign rx_if_R3[4].fifo_read_data = tx_if_R2[4].fifo_read_data;
    assign tx_if_R2[4].fifo_read_addr = rx_if_R3[4].fifo_read_addr;


    assign tile9_noc_fifo_in_waddr_o = tx_if_R3[0].fifo_write_addr;
    assign tile9_noc_fifo_in_data_o = tx_if_R3[0].fifo_read_data;
    assign tx_if_R3[0].fifo_read_addr = tile9_noc_fifo_in_raddr_i;

    assign tile10_noc_fifo_in_waddr_o = tx_if_R3[1].fifo_write_addr;
    assign tile10_noc_fifo_in_data_o = tx_if_R3[1].fifo_read_data;
    assign tx_if_R3[1].fifo_read_addr = tile10_noc_fifo_in_raddr_i;

    assign tile11_noc_fifo_in_waddr_o = tx_if_R3[2].fifo_write_addr;
    assign tile11_noc_fifo_in_data_o = tx_if_R3[2].fifo_read_data;
    assign tx_if_R3[2].fifo_read_addr = tile11_noc_fifo_in_raddr_i;

    assign rx_if_R1[3].fifo_write_addr = tx_if_R3[3].fifo_write_addr;
    assign rx_if_R1[3].fifo_read_data = tx_if_R3[3].fifo_read_data;
    assign tx_if_R3[3].fifo_read_addr = rx_if_R1[3].fifo_read_addr;

    assign rx_if_R2[4].fifo_write_addr = tx_if_R3[4].fifo_write_addr;
    assign rx_if_R2[4].fifo_read_data = tx_if_R3[4].fifo_read_data;
    assign tx_if_R3[4].fifo_read_addr = rx_if_R2[4].fifo_read_addr;

    router_wrap #(
        .PORT_QUANT         (PORT_QUANT_R3),
        .MODULES_PER_ROUTER (3),

        .LUT_RESET_VALUE    ({8'b00000011,
                              8'b10000000}),
        .DIRECTION_ADD_X    (1),
        .DIRECTION_ADD_Y    (0),
        .SYNC_ROUTER        (SYNC_ROUTER),
        .INSTANCE_NAME      ("R3")
    ) router_wrap_r3 (
        .clk_i              (clk_i),
        .reset_q_i          (reset_q_i),
        .testmode_i         (testmode_s),
        .home_chipid_i      (home_chipid_i),

        .rx_if              (rx_if_R3),
        .tx_if              (tx_if_R3)
    );

endmodule