data/full_repos/permissive/518325211/pll/DSM_lib/OpenLane/src/Special_Adder.v
data/verilator_xmls/01b47029-8135-4784-9074-35014fc15973.xml
module spec_adder(Data1, Data2, Data3, Out_Data);

	input [4:0] Data1, Data2, Data3;
	output [4:0] Out_Data;

	wire [5:0] Temp;

	assign Temp = Data1 + Data2 - Data3;

	assign Out_Data = Temp[4:0];

endmodule
module spec_adder(Data1, Data2, Data3, Out_Data);


	input [4:0] Data1, Data2, Data3;
	output [4:0] Out_Data;

	wire [5:0] Temp;

	assign Temp = Data1 + Data2 - Data3;

	assign Out_Data = Temp[4:0];

endmodule