data/full_repos/permissive/42434302/ivltests/pr2728032.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr2728032.v:19: Unsupported: Ignoring delay on this delayed statement.\n    #1000 in = 1\'b0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr2728032.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #1000 in = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr2728032.v:21: Unsupported: Ignoring delay on this delayed statement.\n    #1000 in = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr2728032.v:22: Unsupported: Ignoring delay on this delayed statement.\n    #1000 in = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr2728032.v:23: Unsupported: Ignoring delay on this delayed statement.\n    #1000 in = 1\'bx;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr2728032.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #1000 in = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr2728032.v:25: Unsupported: Ignoring delay on this delayed statement.\n    #1000 in = 1\'bx;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr2728032.v:26: Unsupported: Ignoring delay on this delayed statement.\n    #1000 in = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr2728032.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #1000 in = 1\'b0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr2728032.v:28: Unsupported: Ignoring delay on this delayed statement.\n    #1000 if (pass) $display("PASSED");\n    ^\n%Error: Exiting due to 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top;
  reg pass;
  time change;
  reg in;
  wire c1, c2a, c2b, c3;
  wire v1, v2, v3;

  const_1 d_c1(c1, in);
  const_2a d_c2a(c2a, in);
  const_2b d_c2b(c2b, in);
  const_3 d_c3(c3, in);

  var_1 d_v1(v1, in);

  var_3 d_v3(v2, in);

  initial begin
    pass = 1'b1;
    #1000 in = 1'b0;
    #1000 in = 1'b1;
    #1000 in = 1'b0;
    #1000 in = 1'b1;
    #1000 in = 1'bx;
    #1000 in = 1'b0;
    #1000 in = 1'bx;
    #1000 in = 1'b1;
    #1000 in = 1'b0;
    #1000 if (pass) $display("PASSED");
  end

  always @(in) change = $time;
endmodule
module top;

  reg pass;
  time change;
  reg in;
  wire c1, c2a, c2b, c3;
  wire v1, v2, v3;

  const_1 d_c1(c1, in);
  const_2a d_c2a(c2a, in);
  const_2b d_c2b(c2b, in);
  const_3 d_c3(c3, in);

  var_1 d_v1(v1, in);

  var_3 d_v3(v2, in);

  initial begin
    pass = 1'b1;
    #1000 in = 1'b0;
    #1000 in = 1'b1;
    #1000 in = 1'b0;
    #1000 in = 1'b1;
    #1000 in = 1'bx;
    #1000 in = 1'b0;
    #1000 in = 1'bx;
    #1000 in = 1'b1;
    #1000 in = 1'b0;
    #1000 if (pass) $display("PASSED");
  end

  always @(in) change = $time;
endmodule