data/full_repos/permissive/522019127/testbench.v
1: b'%Error: data/full_repos/permissive/522019127/testbench.v:43: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("test.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/522019127/testbench.v:44: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,test);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/522019127/testbench.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #50 clk= ~clk;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/522019127/testbench.v:58: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522019127/testbench.v:65: Unsupported: Ignoring delay on this delayed statement.\n  #200\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522019127/testbench.v:67: Unsupported: Ignoring delay on this delayed statement.\n  #(100*n_bits)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522019127/testbench.v:71: Unsupported: Ignoring delay on this delayed statement.\n  #200\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/522019127/testbench.v:73: Unsupported: Ignoring delay on this delayed statement.\n  #(100*n_bits)\n  ^\n%Error: Exiting due to 2 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;
   parameter n_bits = 5;
	

	reg [n_bits-1:0] a_in;
	reg [n_bits-1:0] b_in;
	reg clk;
	reg start;
	reg reset;


	wire [(n_bits*2)-1:0] out;
	wire finish;
	wire [(((n_bits*2)/3)+1)*4-1:0] bcd;


	multiplier uut (
		.out(out), 
		.a_in(a_in), 
		.b_in(b_in), 
		.clk(clk), 
		.start(start), 
		.reset(reset), 
		.finish(finish),
		.bcd(bcd)
	);
   defparam uut.N = n_bits;

   
	initial begin
	$dumpfile("test.vcd");
	$dumpvars(0,test);
	forever 
		#50 clk= ~clk;
	end
	
	initial begin

		a_in = 0;
		b_in = 0;
		clk = 0;
		start = 0;
		reset = 1;


		#100;
        

		reset = 0;
      a_in = 'd26;
		b_in = 'd30;
		start = 0;
		#200
		start = 1;
		#(100*n_bits)
		a_in = 'd13;
		b_in = 'd13;
		start = 0;
		#200
		start = 1;
		#(100*n_bits)
		$finish;
	end
      
endmodule
module test;

   parameter n_bits = 5;
	

	reg [n_bits-1:0] a_in;
	reg [n_bits-1:0] b_in;
	reg clk;
	reg start;
	reg reset;


	wire [(n_bits*2)-1:0] out;
	wire finish;
	wire [(((n_bits*2)/3)+1)*4-1:0] bcd;


	multiplier uut (
		.out(out), 
		.a_in(a_in), 
		.b_in(b_in), 
		.clk(clk), 
		.start(start), 
		.reset(reset), 
		.finish(finish),
		.bcd(bcd)
	);
   defparam uut.N = n_bits;

   
	initial begin
	$dumpfile("test.vcd");
	$dumpvars(0,test);
	forever 
		#50 clk= ~clk;
	end
	
	initial begin

		a_in = 0;
		b_in = 0;
		clk = 0;
		start = 0;
		reset = 1;


		#100;
        

		reset = 0;
      a_in = 'd26;
		b_in = 'd30;
		start = 0;
		#200
		start = 1;
		#(100*n_bits)
		a_in = 'd13;
		b_in = 'd13;
		start = 0;
		#200
		start = 1;
		#(100*n_bits)
		$finish;
	end
      
endmodule