data/full_repos/permissive/482974936/MultiCycle.srcs/sources_1/new/OR.v
data/verilator_xmls/93b9f588-c422-4c10-bf7c-d8164bb84e4c.xml
module OR(
    input PCWE,
    input ANDOut,
    output OROut
    );
    assign OROut = PCWE | ANDOut;
endmodule
module OR(
    input PCWE,
    input ANDOut,
    output OROut
    );

    assign OROut = PCWE | ANDOut;
endmodule