data/full_repos/permissive/492581806/cpu_tb.v
1: b'%Error: data/full_repos/permissive/492581806/cpu_tb.v:1: Cannot find include file: alumod.v\n`include "alumod.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/492581806,data/full_repos/permissive/492581806/alumod.v\n             data/full_repos/permissive/492581806,data/full_repos/permissive/492581806/alumod.v.v\n             data/full_repos/permissive/492581806,data/full_repos/permissive/492581806/alumod.v.sv\n             alumod.v\n             alumod.v.v\n             alumod.v.sv\n             obj_dir/alumod.v\n             obj_dir/alumod.v.v\n             obj_dir/alumod.v.sv\n%Error: data/full_repos/permissive/492581806/cpu_tb.v:2: Cannot find include file: regmod.v\n`include "regmod.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/492581806/cpu_tb.v:3: Cannot find include file: cpu.v\n`include "cpu.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/492581806/cpu_tb.v:4: Cannot find include file: dmem.v\n`include "dmem.v" \n         ^~~~~~~~\n%Error: data/full_repos/permissive/492581806/cpu_tb.v:5: Cannot find include file: dcache.v\n`include "dcache.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/492581806/cpu_tb.v:6: Cannot find include file: ins_Cache.v\n`include "ins_Cache.v" \n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492581806/cpu_tb.v:7: Cannot find include file: imem_for_icache.v\n`include "imem_for_icache.v" \n         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492581806/cpu_tb.v:79: Unsupported or unknown PLI call: $dumpfile\n       $dumpfile("cpu_wavedata.vcd");\n       ^~~~~~~~~\n%Error: data/full_repos/permissive/492581806/cpu_tb.v:80: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0, cpu_tb);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/492581806/cpu_tb.v:81: Unsupported or unknown PLI call: $dumpvars\n for(i=0;i<8;i=i+1)$dumpvars(0, mycpu.myreg.store[i]);\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/492581806/cpu_tb.v:82: Unsupported or unknown PLI call: $dumpvars\n        for(i=0;i<8;i=i+1)$dumpvars(0, my_dcache.Cache_MEM[i]);\n                          ^~~~~~~~~\n%Error: data/full_repos/permissive/492581806/cpu_tb.v:83: Unsupported or unknown PLI call: $dumpvars\n         for(i=0;i<8;i=i+1)$dumpvars(0, myicache.iCache[i]);\n                           ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/492581806/cpu_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n        #5 RESET=1\'b0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/492581806/cpu_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n        #3000\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/492581806/cpu_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n        #4 CLK = ~CLK;\n        ^\n%Error: Exiting due to 12 error(s), 3 warning(s)\n'
module cpu_tb;

    reg CLK, RESET;
    wire [31:0] PC;
    wire [31:0] INSTRUCTION;
    wire C_READ,C_WRITE,busywait,insbusywait;
    wire [7:0] C_Address,C_READDATA,C_WRITEDATA;
    wire mem_write,mem_read,mem_busywait;
    wire [5:0] mem_address,imem_address;
    wire [31:0] mem_writedata,mem_readdata;
    wire imem_busywait,imem_read;
    wire [127:0] mem_instruction;

    





    






        




        



    



   cpu mycpu(PC,INSTRUCTION, CLK,RESET,busywait,C_READ,C_WRITE,C_WRITEDATA,C_READDATA,C_Address,insbusywait);
 
   dcache my_dcache(CLK,RESET,C_WRITE,C_READ,C_Address,C_WRITEDATA,C_READDATA,busywait,mem_write,mem_read,mem_address,mem_writedata,mem_readdata,mem_busywait);
                      
   data_memory my_data_memory(CLK,RESET,mem_read,mem_write,mem_address,mem_writedata,mem_readdata,mem_busywait);

 ins_cache myicache  (CLK,PC,RESET,INSTRUCTION,insbusywait,mem_instruction,imem_read,imem_address,imem_busywait);

instruction_memory myinsmem(CLK,imem_read,imem_address,mem_instruction,imem_busywait);
   
                    
   
    

   integer i;
    initial
    begin
    

       $dumpfile("cpu_wavedata.vcd");
	$dumpvars(0, cpu_tb);
	for(i=0;i<8;i=i+1)$dumpvars(0, mycpu.myreg.store[i]);
        for(i=0;i<8;i=i+1)$dumpvars(0, my_dcache.Cache_MEM[i]);
         for(i=0;i<8;i=i+1)$dumpvars(0, myicache.iCache[i]);
        CLK = 1'b0;
        RESET = 1'b1;
        

        #5 RESET=1'b0;
       

        #3000
        $finish;
        
    end
    

    always
        #4 CLK = ~CLK;
        

endmodule
module cpu_tb;


    reg CLK, RESET;
    wire [31:0] PC;
    wire [31:0] INSTRUCTION;
    wire C_READ,C_WRITE,busywait,insbusywait;
    wire [7:0] C_Address,C_READDATA,C_WRITEDATA;
    wire mem_write,mem_read,mem_busywait;
    wire [5:0] mem_address,imem_address;
    wire [31:0] mem_writedata,mem_readdata;
    wire imem_busywait,imem_read;
    wire [127:0] mem_instruction;

    





    






        




        



    



   cpu mycpu(PC,INSTRUCTION, CLK,RESET,busywait,C_READ,C_WRITE,C_WRITEDATA,C_READDATA,C_Address,insbusywait);
 
   dcache my_dcache(CLK,RESET,C_WRITE,C_READ,C_Address,C_WRITEDATA,C_READDATA,busywait,mem_write,mem_read,mem_address,mem_writedata,mem_readdata,mem_busywait);
                      
   data_memory my_data_memory(CLK,RESET,mem_read,mem_write,mem_address,mem_writedata,mem_readdata,mem_busywait);

 ins_cache myicache  (CLK,PC,RESET,INSTRUCTION,insbusywait,mem_instruction,imem_read,imem_address,imem_busywait);

instruction_memory myinsmem(CLK,imem_read,imem_address,mem_instruction,imem_busywait);
   
                    
   
    

   integer i;
    initial
    begin
    

       $dumpfile("cpu_wavedata.vcd");
	$dumpvars(0, cpu_tb);
	for(i=0;i<8;i=i+1)$dumpvars(0, mycpu.myreg.store[i]);
        for(i=0;i<8;i=i+1)$dumpvars(0, my_dcache.Cache_MEM[i]);
         for(i=0;i<8;i=i+1)$dumpvars(0, myicache.iCache[i]);
        CLK = 1'b0;
        RESET = 1'b1;
        

        #5 RESET=1'b0;
       

        #3000
        $finish;
        
    end
    

    always
        #4 CLK = ~CLK;
        

endmodule