data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:58: Signal definition not found, creating implicitly: \'QEND\'\n                                                                                                                                           : ... Suggested alternative: \'END\'\n assign { QEND, QHULL_RECURSE, QCROSS, QHULL_START, QFIND_MIN, QFIND_MAX, QINITIAL } = state;\n          ^~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:58: Signal definition not found, creating implicitly: \'QHULL_RECURSE\'\n                                                                                                                                           : ... Suggested alternative: \'HULL_RECURSE\'\n assign { QEND, QHULL_RECURSE, QCROSS, QHULL_START, QFIND_MIN, QFIND_MAX, QINITIAL } = state;\n                ^~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:58: Signal definition not found, creating implicitly: \'QCROSS\'\n                                                                                                                                           : ... Suggested alternative: \'CROSS\'\n assign { QEND, QHULL_RECURSE, QCROSS, QHULL_START, QFIND_MIN, QFIND_MAX, QINITIAL } = state;\n                               ^~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:58: Signal definition not found, creating implicitly: \'QHULL_START\'\n                                                                                                                                           : ... Suggested alternative: \'HULL_START\'\n assign { QEND, QHULL_RECURSE, QCROSS, QHULL_START, QFIND_MIN, QFIND_MAX, QINITIAL } = state;\n                                       ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:58: Signal definition not found, creating implicitly: \'QFIND_MIN\'\n                                                                                                                                           : ... Suggested alternative: \'FIND_XMIN\'\n assign { QEND, QHULL_RECURSE, QCROSS, QHULL_START, QFIND_MIN, QFIND_MAX, QINITIAL } = state;\n                                                    ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:58: Signal definition not found, creating implicitly: \'QFIND_MAX\'\n                                                                                                                                           : ... Suggested alternative: \'FIND_XMAX\'\n assign { QEND, QHULL_RECURSE, QCROSS, QHULL_START, QFIND_MIN, QFIND_MAX, QINITIAL } = state;\n                                                               ^~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:58: Signal definition not found, creating implicitly: \'QINITIAL\'\n                                                                                                                                           : ... Suggested alternative: \'INITIAL\'\n assign { QEND, QHULL_RECURSE, QCROSS, QHULL_START, QFIND_MIN, QFIND_MAX, QINITIAL } = state;\n                                                                          ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:53: Operator ASSIGNW expects 4096 bits on the Assign RHS, but Assign RHS\'s VARREF \'convexPoints\' generates 4097 bits.\n                                                                                                                                        : ... In instance m_port_ultra_quickhull\n assign convexPointsOutput = convexPoints;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:76: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'ptIndex\' generates 16 bits.\n                                                                                                                                        : ... In instance m_port_ultra_quickhull\n   for (i = ptIndex; i < ptIndex + PTSIZE; i = i + 1) begin\n          ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:76: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'ptIndex\' generates 16 bits.\n                                                                                                                                        : ... In instance m_port_ultra_quickhull\n   for (i = ptIndex; i < ptIndex + PTSIZE; i = i + 1) begin\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:86: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'ptIndex\' generates 16 bits.\n                                                                                                                                        : ... In instance m_port_ultra_quickhull\n   for (i = ptIndex; i < ptIndex + (PTSIZE / 2); i = i + 1) begin\n          ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:86: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'ptIndex\' generates 16 bits.\n                                                                                                                                        : ... In instance m_port_ultra_quickhull\n   for (i = ptIndex; i < ptIndex + (PTSIZE / 2); i = i + 1) begin\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:96: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'ptIndex\' generates 16 bits.\n                                                                                                                                        : ... In instance m_port_ultra_quickhull\n   for (i = ptIndex + (PTSIZE / 2); i < ptIndex + PTSIZE; i = i + 1) begin\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:96: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'ptIndex\' generates 16 bits.\n                                                                                                                                        : ... In instance m_port_ultra_quickhull\n   for (i = ptIndex + (PTSIZE / 2); i < ptIndex + PTSIZE; i = i + 1) begin\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:106: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'lnIndex\' generates 16 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n   for (i = lnIndex; i < lnIndex + LNSIZE; i = i + 1) begin\n          ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:106: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'lnIndex\' generates 16 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n   for (i = lnIndex; i < lnIndex + LNSIZE; i = i + 1) begin\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:116: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'lnIndex\' generates 16 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n   for (i = lnIndex; i < lnIndex + (LNSIZE/2); i = i + 1) begin\n          ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:116: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'lnIndex\' generates 16 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n   for (i = lnIndex; i < lnIndex + (LNSIZE/2); i = i + 1) begin\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:126: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'lnIndex\' generates 16 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n   for (i = lnIndex; i < lnIndex + (PTSIZE/2); i = i + 1) begin\n          ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:126: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'lnIndex\' generates 16 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n   for (i = lnIndex; i < lnIndex + (PTSIZE/2); i = i + 1) begin\n                                 ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:136: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'lnIndex\' generates 16 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n   for (i = lnIndex + (PTSIZE / 2); i < lnIndex + PTSIZE; i = i + 1) begin\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:136: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'lnIndex\' generates 16 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n   for (i = lnIndex + (PTSIZE / 2); i < lnIndex + PTSIZE; i = i + 1) begin\n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:146: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'lnIndex\' generates 16 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n   for (i = lnIndex + (LNSIZE/2); i < lnIndex + LNSIZE; i = i + 1) begin\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:146: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'lnIndex\' generates 16 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n   for (i = lnIndex + (LNSIZE/2); i < lnIndex + LNSIZE; i = i + 1) begin\n                                              ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:156: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'lnIndex\' generates 16 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n   for (i = lnIndex + PTSIZE; i < lnIndex + LNSIZE - (PTSIZE/2); i = i + 1) begin\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:156: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'lnIndex\' generates 16 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n   for (i = lnIndex + PTSIZE; i < lnIndex + LNSIZE - (PTSIZE/2); i = i + 1) begin\n                                          ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:166: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'lnIndex\' generates 16 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n   for (i = lnIndex + LNSIZE - (PTSIZE / 2); i < lnIndex + LNSIZE; i = i + 1) begin\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:166: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'lnIndex\' generates 16 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n   for (i = lnIndex + LNSIZE - (PTSIZE / 2); i < lnIndex + LNSIZE; i = i + 1) begin\n                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:201: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'currLine_AX\' generates 8 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n  crossValue = (((currLine_AX - currPoint_X) * (currLine_BY - currPoint_Y)) - ((currLine_AY - currPoint_Y) * (currLine_BX - currPoint_X)));\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:201: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'currPoint_X\' generates 8 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n  crossValue = (((currLine_AX - currPoint_X) * (currLine_BY - currPoint_Y)) - ((currLine_AY - currPoint_Y) * (currLine_BX - currPoint_X)));\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:201: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'currLine_BY\' generates 8 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n  crossValue = (((currLine_AX - currPoint_X) * (currLine_BY - currPoint_Y)) - ((currLine_AY - currPoint_Y) * (currLine_BX - currPoint_X)));\n                                                            ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:201: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'currPoint_Y\' generates 8 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n  crossValue = (((currLine_AX - currPoint_X) * (currLine_BY - currPoint_Y)) - ((currLine_AY - currPoint_Y) * (currLine_BX - currPoint_X)));\n                                                            ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:201: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'currLine_AY\' generates 8 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n  crossValue = (((currLine_AX - currPoint_X) * (currLine_BY - currPoint_Y)) - ((currLine_AY - currPoint_Y) * (currLine_BX - currPoint_X)));\n                                                                                            ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:201: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'currPoint_Y\' generates 8 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n  crossValue = (((currLine_AX - currPoint_X) * (currLine_BY - currPoint_Y)) - ((currLine_AY - currPoint_Y) * (currLine_BX - currPoint_X)));\n                                                                                            ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:201: Operator SUB expects 32 bits on the LHS, but LHS\'s VARREF \'currLine_BX\' generates 8 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n  crossValue = (((currLine_AX - currPoint_X) * (currLine_BY - currPoint_Y)) - ((currLine_AY - currPoint_Y) * (currLine_BX - currPoint_X)));\n                                                                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:201: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'currPoint_X\' generates 8 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n  crossValue = (((currLine_AX - currPoint_X) * (currLine_BY - currPoint_Y)) - ((currLine_AY - currPoint_Y) * (currLine_BX - currPoint_X)));\n                                                                                                                          ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:287: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'lnIndex\' generates 16 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n    for (i = lnIndex; i < lnIndex + LNSIZE; i = i + 1) begin\n           ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:287: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'lnIndex\' generates 16 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n    for (i = lnIndex; i < lnIndex + LNSIZE; i = i + 1) begin\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:294: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'lnIndex\' generates 16 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n    for (i = lnIndex + LNSIZE; i < lnIndex + (LNSIZE * 2); i = i + 1) begin\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:294: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'lnIndex\' generates 16 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n    for (i = lnIndex + LNSIZE; i < lnIndex + (LNSIZE * 2); i = i + 1) begin\n                                           ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:343: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'cxIndex\' generates 16 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n     for (i = cxIndex; i < cxIndex + PTSIZE; i = i + 1) begin\n            ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:343: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'cxIndex\' generates 16 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n     for (i = cxIndex; i < cxIndex + PTSIZE; i = i + 1) begin\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:349: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'cxIndex\' generates 16 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n     for (i = cxIndex + PTSIZE; i < cxIndex + (PTSIZE * 2); i = i + 1) begin\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:349: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'cxIndex\' generates 16 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n     for (i = cxIndex + PTSIZE; i < cxIndex + (PTSIZE * 2); i = i + 1) begin\n                                            ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:368: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'cxIndex\' generates 16 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n     for (i = cxIndex; i < cxIndex + PTSIZE; i = i + 1) begin\n            ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:368: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'cxIndex\' generates 16 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n     for (i = cxIndex; i < cxIndex + PTSIZE; i = i + 1) begin\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:390: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'lnIndex\' generates 16 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n     for (i = lnIndex; i < lnIndex + LNSIZE; i = i + 1) begin\n            ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:390: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'lnIndex\' generates 16 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n     for (i = lnIndex; i < lnIndex + LNSIZE; i = i + 1) begin\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:396: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'lnIndex\' generates 16 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n     for (i = lnIndex + LNSIZE; i < lnIndex + (LNSIZE * 2); i = i + 1) begin\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/45440421/Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_quickhull.v:396: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'lnIndex\' generates 16 bits.\n                                                                                                                                         : ... In instance m_port_ultra_quickhull\n     for (i = lnIndex + LNSIZE; i < lnIndex + (LNSIZE * 2); i = i + 1) begin\n                                            ^\n%Error: Exiting due to 50 warning(s)\n'
module m_port_ultra_quickhull
(
	input clk,
	input reset_n,
	input processorEnable,
	input [4095:0] points,
	input [8:0] SS,
	output [4095:0] convexPointsOutput,
	output [7:0] convexSetSizeOutput
);


	localparam PTSIZE = 16;
	localparam LNSIZE = 32;

	reg [LNSIZE * 256 - 1 : 0] lineFIFO;
	reg [15:0] lnIndex;
	reg [15:0] cxIndex;
	reg [15:0] ptIndex;
	reg [8:0] ptCount;
	reg [4096:0] convexPoints;
	reg [7:0] convexSetSize;

	reg [PTSIZE - 1 : 0] xMinPoint;
	reg [PTSIZE - 1 : 0] xMaxPoint;
	reg [LNSIZE:0] line;
	reg [8:0] positiveCrossCount;
	
	reg [PTSIZE - 1 : 0] furthest;
	reg [PTSIZE - 1 : 0] currPoint;
	reg [(PTSIZE / 2) - 1 : 0] currPoint_X;
	reg [(PTSIZE / 2) - 1 : 0] currPoint_Y;
	reg [LNSIZE - 1 : 0] currLine;
	reg [PTSIZE - 1 : 0] currLine_A;
	reg [(PTSIZE / 2) - 1 : 0] currLine_AX;
	reg [(PTSIZE / 2) - 1 : 0] currLine_AY;
	reg [PTSIZE - 1 : 0] currLine_B;
	reg [(PTSIZE / 2) - 1 : 0] currLine_BX;
	reg [(PTSIZE / 2) - 1 : 0] currLine_BY;
	reg signed [31:0] crossValue;
	reg signed [31:0] furthestCrossValue;
	reg [LNSIZE - 1: 0] nextLineAddr;
	reg [LNSIZE - 1: 0] nextLineAddr2;
	reg [PTSIZE - 1: 0] nextCXAddr;
	reg [PTSIZE - 1: 0] nextCXAddr2;

	reg furthestFlag;
	

	assign convexSetSizeOutput = convexSetSize;
	assign convexPointsOutput = convexPoints;


	reg[6:0] state;

	assign { QEND, QHULL_RECURSE, QCROSS, QHULL_START, QFIND_MIN, QFIND_MAX, QINITIAL } = state;
	
	localparam 
		INITIAL			=	7'b0000001,
		FIND_XMAX		=	7'b0000010,
		FIND_XMIN		=	7'b0000100,
		HULL_START		=	7'b0001000,
		CROSS 			= 	7'b0010000, 
		HULL_RECURSE	=	7'b0100000,
		END 			=	7'b1000000;


	integer i;
	integer j;

	generate
		always @(clk) begin
			j = 0;
			for (i = ptIndex; i < ptIndex + PTSIZE; i = i + 1) begin
				currPoint[j] = points[i];
				j = j + 1;
			end
		end
	endgenerate
	
	generate
		always @(clk) begin
			j = 0;
			for (i = ptIndex; i < ptIndex + (PTSIZE / 2); i = i + 1) begin
				currPoint_X[j] = points[i];
				j = j + 1;
			end
		end
	endgenerate
			
	generate
		always @(clk) begin
			j = 0;
			for (i = ptIndex + (PTSIZE / 2); i < ptIndex + PTSIZE; i = i + 1) begin
				currPoint_Y[j] = points[i];
				j = j + 1;
			end
		end
	endgenerate
			
	generate
		always @(clk) begin
			j = 0;
			for (i = lnIndex; i < lnIndex + LNSIZE; i = i + 1) begin
				currLine[j] = lineFIFO[i];
				j = j + 1;
			end
		end
	endgenerate
	
	generate
		always @(clk) begin
			j = 0;
			for (i = lnIndex; i < lnIndex + (LNSIZE/2); i = i + 1) begin
				currLine_A[j] = lineFIFO[i];
				j = j + 1;
			end
		end
	endgenerate
		
	generate
		always @(clk) begin
			j = 0;
			for (i = lnIndex; i < lnIndex + (PTSIZE/2); i = i + 1) begin
				currLine_AX[j] = lineFIFO[i];
				j = j + 1;
			end
		end
	endgenerate
		
	generate
		always @(clk) begin
			j = 0;
			for (i = lnIndex + (PTSIZE / 2); i < lnIndex + PTSIZE; i = i + 1) begin
				currLine_AY[j] = lineFIFO[i];
				j = j + 1;
			end
		end
	endgenerate
			
	generate
		always @(clk) begin
			j = 0;
			for (i = lnIndex + (LNSIZE/2); i < lnIndex + LNSIZE; i = i + 1) begin
				currLine_B [j] = lineFIFO[i];
				j = j + 1;
			end
		end
	endgenerate
		
	generate
		always @(clk) begin
			j = 0;
			for (i = lnIndex + PTSIZE; i < lnIndex + LNSIZE - (PTSIZE/2); i = i + 1) begin
				currLine_BX[j] = lineFIFO[i];
				j = j + 1;
			end
		end
	endgenerate
	
	generate
		always @(clk) begin
			j = 0;
			for (i = lnIndex + LNSIZE - (PTSIZE / 2); i < lnIndex + LNSIZE; i = i + 1) begin
				currLine_BY[j] = lineFIFO[i];
				j = j + 1;
			end
		end
	endgenerate
	

	always @(posedge clk, negedge reset_n) begin
		
		ptIndex = PTSIZE * ptCount;

		crossValue = (((currLine_AX - currPoint_X) * (currLine_BY - currPoint_Y)) - ((currLine_AY - currPoint_Y) * (currLine_BX - currPoint_X)));
	
		if (!reset_n) begin

			state <= INITIAL;
		end
		case (state)
			INITIAL: begin

				lineFIFO <= 0;
				lnIndex <= 32;
				cxIndex <= 0;
				line <= 0;
				ptIndex <= 0;
				ptCount <= 0;
				positiveCrossCount <= 0;
				xMinPoint <= 0;
				xMaxPoint <= 0;
				crossValue <= 0;
				furthest <= 0;
				furthestCrossValue <= 0;
				furthestFlag <= 0;
				convexSetSize <= 0;
				convexPoints <= 0;
				

				if (processorEnable) begin
					state <= FIND_XMAX;
				end

			end

			FIND_XMAX: begin

				if (ptCount == 0) begin
					xMaxPoint <= currPoint;
				end
				else begin
					if (xMaxPoint < currPoint) begin
						xMaxPoint <= currPoint;
					end
					else begin

					end
				end


				if (ptCount != (SS - 1)) begin
					ptCount <= ptCount + 1;
					state <= FIND_XMAX;			
				end
				else begin
					ptCount <= 0;
					state <= FIND_XMIN;
				end
			end

			FIND_XMIN: begin

				if (ptCount == 0) begin
					xMinPoint <= currPoint;
				end
				else begin
					if (xMinPoint > currPoint) begin
						xMinPoint <= currPoint;
					end
					else begin

					end
				end


				if (ptCount != (SS - 1)) begin
					ptCount <= ptCount + 1;
					state <= FIND_XMIN;					
				end
				else begin
					ptCount <= 0;
					state <= HULL_START;
				end
			end

			HULL_START: begin

				nextLineAddr = {xMinPoint, xMaxPoint};
				j = 0;
				for (i = lnIndex; i < lnIndex + LNSIZE; i = i + 1) begin
					lineFIFO[i] = nextLineAddr[j];
					j = j + 1;
				end
				
				nextLineAddr2 = {xMaxPoint, xMinPoint};
				j = 0;
				for (i = lnIndex + LNSIZE; i < lnIndex + (LNSIZE * 2); i = i + 1) begin
					lineFIFO[i] = nextLineAddr2[j];
					j = j + 1;
				end				
				lnIndex <= lnIndex + LNSIZE;
				

				ptCount <= 0;
				state <= CROSS;
			end

			CROSS: begin


				if (crossValue > 0 && ptCount != (SS)) begin
					positiveCrossCount <= positiveCrossCount + 1;
					if (furthestFlag == 0) begin
						furthestCrossValue <= crossValue;
						furthest <= currPoint;
						furthestFlag <= 1;
					end
					else begin
						if (furthestCrossValue < crossValue) begin
							furthestCrossValue <= crossValue;
							furthest <= currPoint;
						end
					end
				end


				if (ptCount != (SS)) begin
					ptCount <= ptCount + 1;
					state <= CROSS;
				end
				else begin
					ptCount <= 0;
					furthestFlag <= 0;
					state <= HULL_RECURSE;
				end

			end
			
			HULL_RECURSE: begin 



				if (positiveCrossCount == 1 && lnIndex != 0) begin
					nextCXAddr = currLine_A;
					j = 0;
					for (i = cxIndex; i < cxIndex + PTSIZE; i = i + 1) begin
						convexPoints[i] = nextCXAddr[j];
						j = j + 1;
					end
					nextCXAddr2 = furthest;
					j = 0;
					for (i = cxIndex + PTSIZE; i < cxIndex + (PTSIZE * 2); i = i + 1) begin
						convexPoints[i] = nextCXAddr2[j];
						j = j + 1;
					end
					cxIndex <= cxIndex + (2 * PTSIZE);
					convexSetSize <= convexSetSize + 2;
					

					lnIndex <= lnIndex - LNSIZE;
				end
				else if (positiveCrossCount == 0 && lnIndex != 0) begin
					nextCXAddr = currLine_A;
					j = 0;
					for (i = cxIndex; i < cxIndex + PTSIZE; i = i + 1) begin
						convexPoints[i] = nextCXAddr[j];
						j = j + 1;
					end
					cxIndex <= cxIndex + PTSIZE;
					convexSetSize <= convexSetSize + 1;


					lnIndex <= lnIndex - LNSIZE;
				end
				else begin
					nextLineAddr 	= {furthest, currLine_A};
					nextLineAddr2	= {currLine_B, furthest};


					j = 0;
					for (i = lnIndex; i < lnIndex + LNSIZE; i = i + 1) begin
						lineFIFO[i] = nextLineAddr[j];
						j = j + 1;
					end
					
					j = 0;
					for (i = lnIndex + LNSIZE; i < lnIndex + (LNSIZE * 2); i = i + 1) begin
						lineFIFO[i] = nextLineAddr2[j];
						j = j + 1;
					end						
					lnIndex <= lnIndex + LNSIZE;
				end

				if ((lnIndex) != 0) begin
					positiveCrossCount <= 0;
					furthest <= 0;
					furthestCrossValue <= 0;
					ptCount <= 0;
					state <= CROSS;
				end
				else begin
					state <= END;
				end
			end

			END: begin

			end

		endcase
	end

endmodule
module m_port_ultra_quickhull
(
	input clk,
	input reset_n,
	input processorEnable,
	input [4095:0] points,
	input [8:0] SS,
	output [4095:0] convexPointsOutput,
	output [7:0] convexSetSizeOutput
);



	localparam PTSIZE = 16;
	localparam LNSIZE = 32;

	reg [LNSIZE * 256 - 1 : 0] lineFIFO;
	reg [15:0] lnIndex;
	reg [15:0] cxIndex;
	reg [15:0] ptIndex;
	reg [8:0] ptCount;
	reg [4096:0] convexPoints;
	reg [7:0] convexSetSize;

	reg [PTSIZE - 1 : 0] xMinPoint;
	reg [PTSIZE - 1 : 0] xMaxPoint;
	reg [LNSIZE:0] line;
	reg [8:0] positiveCrossCount;
	
	reg [PTSIZE - 1 : 0] furthest;
	reg [PTSIZE - 1 : 0] currPoint;
	reg [(PTSIZE / 2) - 1 : 0] currPoint_X;
	reg [(PTSIZE / 2) - 1 : 0] currPoint_Y;
	reg [LNSIZE - 1 : 0] currLine;
	reg [PTSIZE - 1 : 0] currLine_A;
	reg [(PTSIZE / 2) - 1 : 0] currLine_AX;
	reg [(PTSIZE / 2) - 1 : 0] currLine_AY;
	reg [PTSIZE - 1 : 0] currLine_B;
	reg [(PTSIZE / 2) - 1 : 0] currLine_BX;
	reg [(PTSIZE / 2) - 1 : 0] currLine_BY;
	reg signed [31:0] crossValue;
	reg signed [31:0] furthestCrossValue;
	reg [LNSIZE - 1: 0] nextLineAddr;
	reg [LNSIZE - 1: 0] nextLineAddr2;
	reg [PTSIZE - 1: 0] nextCXAddr;
	reg [PTSIZE - 1: 0] nextCXAddr2;

	reg furthestFlag;
	

	assign convexSetSizeOutput = convexSetSize;
	assign convexPointsOutput = convexPoints;


	reg[6:0] state;

	assign { QEND, QHULL_RECURSE, QCROSS, QHULL_START, QFIND_MIN, QFIND_MAX, QINITIAL } = state;
	
	localparam 
		INITIAL			=	7'b0000001,
		FIND_XMAX		=	7'b0000010,
		FIND_XMIN		=	7'b0000100,
		HULL_START		=	7'b0001000,
		CROSS 			= 	7'b0010000, 
		HULL_RECURSE	=	7'b0100000,
		END 			=	7'b1000000;


	integer i;
	integer j;

	generate
		always @(clk) begin
			j = 0;
			for (i = ptIndex; i < ptIndex + PTSIZE; i = i + 1) begin
				currPoint[j] = points[i];
				j = j + 1;
			end
		end
	endgenerate
	
	generate
		always @(clk) begin
			j = 0;
			for (i = ptIndex; i < ptIndex + (PTSIZE / 2); i = i + 1) begin
				currPoint_X[j] = points[i];
				j = j + 1;
			end
		end
	endgenerate
			
	generate
		always @(clk) begin
			j = 0;
			for (i = ptIndex + (PTSIZE / 2); i < ptIndex + PTSIZE; i = i + 1) begin
				currPoint_Y[j] = points[i];
				j = j + 1;
			end
		end
	endgenerate
			
	generate
		always @(clk) begin
			j = 0;
			for (i = lnIndex; i < lnIndex + LNSIZE; i = i + 1) begin
				currLine[j] = lineFIFO[i];
				j = j + 1;
			end
		end
	endgenerate
	
	generate
		always @(clk) begin
			j = 0;
			for (i = lnIndex; i < lnIndex + (LNSIZE/2); i = i + 1) begin
				currLine_A[j] = lineFIFO[i];
				j = j + 1;
			end
		end
	endgenerate
		
	generate
		always @(clk) begin
			j = 0;
			for (i = lnIndex; i < lnIndex + (PTSIZE/2); i = i + 1) begin
				currLine_AX[j] = lineFIFO[i];
				j = j + 1;
			end
		end
	endgenerate
		
	generate
		always @(clk) begin
			j = 0;
			for (i = lnIndex + (PTSIZE / 2); i < lnIndex + PTSIZE; i = i + 1) begin
				currLine_AY[j] = lineFIFO[i];
				j = j + 1;
			end
		end
	endgenerate
			
	generate
		always @(clk) begin
			j = 0;
			for (i = lnIndex + (LNSIZE/2); i < lnIndex + LNSIZE; i = i + 1) begin
				currLine_B [j] = lineFIFO[i];
				j = j + 1;
			end
		end
	endgenerate
		
	generate
		always @(clk) begin
			j = 0;
			for (i = lnIndex + PTSIZE; i < lnIndex + LNSIZE - (PTSIZE/2); i = i + 1) begin
				currLine_BX[j] = lineFIFO[i];
				j = j + 1;
			end
		end
	endgenerate
	
	generate
		always @(clk) begin
			j = 0;
			for (i = lnIndex + LNSIZE - (PTSIZE / 2); i < lnIndex + LNSIZE; i = i + 1) begin
				currLine_BY[j] = lineFIFO[i];
				j = j + 1;
			end
		end
	endgenerate
	

	always @(posedge clk, negedge reset_n) begin
		
		ptIndex = PTSIZE * ptCount;

		crossValue = (((currLine_AX - currPoint_X) * (currLine_BY - currPoint_Y)) - ((currLine_AY - currPoint_Y) * (currLine_BX - currPoint_X)));
	
		if (!reset_n) begin

			state <= INITIAL;
		end
		case (state)
			INITIAL: begin

				lineFIFO <= 0;
				lnIndex <= 32;
				cxIndex <= 0;
				line <= 0;
				ptIndex <= 0;
				ptCount <= 0;
				positiveCrossCount <= 0;
				xMinPoint <= 0;
				xMaxPoint <= 0;
				crossValue <= 0;
				furthest <= 0;
				furthestCrossValue <= 0;
				furthestFlag <= 0;
				convexSetSize <= 0;
				convexPoints <= 0;
				

				if (processorEnable) begin
					state <= FIND_XMAX;
				end

			end

			FIND_XMAX: begin

				if (ptCount == 0) begin
					xMaxPoint <= currPoint;
				end
				else begin
					if (xMaxPoint < currPoint) begin
						xMaxPoint <= currPoint;
					end
					else begin

					end
				end


				if (ptCount != (SS - 1)) begin
					ptCount <= ptCount + 1;
					state <= FIND_XMAX;			
				end
				else begin
					ptCount <= 0;
					state <= FIND_XMIN;
				end
			end

			FIND_XMIN: begin

				if (ptCount == 0) begin
					xMinPoint <= currPoint;
				end
				else begin
					if (xMinPoint > currPoint) begin
						xMinPoint <= currPoint;
					end
					else begin

					end
				end


				if (ptCount != (SS - 1)) begin
					ptCount <= ptCount + 1;
					state <= FIND_XMIN;					
				end
				else begin
					ptCount <= 0;
					state <= HULL_START;
				end
			end

			HULL_START: begin

				nextLineAddr = {xMinPoint, xMaxPoint};
				j = 0;
				for (i = lnIndex; i < lnIndex + LNSIZE; i = i + 1) begin
					lineFIFO[i] = nextLineAddr[j];
					j = j + 1;
				end
				
				nextLineAddr2 = {xMaxPoint, xMinPoint};
				j = 0;
				for (i = lnIndex + LNSIZE; i < lnIndex + (LNSIZE * 2); i = i + 1) begin
					lineFIFO[i] = nextLineAddr2[j];
					j = j + 1;
				end				
				lnIndex <= lnIndex + LNSIZE;
				

				ptCount <= 0;
				state <= CROSS;
			end

			CROSS: begin


				if (crossValue > 0 && ptCount != (SS)) begin
					positiveCrossCount <= positiveCrossCount + 1;
					if (furthestFlag == 0) begin
						furthestCrossValue <= crossValue;
						furthest <= currPoint;
						furthestFlag <= 1;
					end
					else begin
						if (furthestCrossValue < crossValue) begin
							furthestCrossValue <= crossValue;
							furthest <= currPoint;
						end
					end
				end


				if (ptCount != (SS)) begin
					ptCount <= ptCount + 1;
					state <= CROSS;
				end
				else begin
					ptCount <= 0;
					furthestFlag <= 0;
					state <= HULL_RECURSE;
				end

			end
			
			HULL_RECURSE: begin 



				if (positiveCrossCount == 1 && lnIndex != 0) begin
					nextCXAddr = currLine_A;
					j = 0;
					for (i = cxIndex; i < cxIndex + PTSIZE; i = i + 1) begin
						convexPoints[i] = nextCXAddr[j];
						j = j + 1;
					end
					nextCXAddr2 = furthest;
					j = 0;
					for (i = cxIndex + PTSIZE; i < cxIndex + (PTSIZE * 2); i = i + 1) begin
						convexPoints[i] = nextCXAddr2[j];
						j = j + 1;
					end
					cxIndex <= cxIndex + (2 * PTSIZE);
					convexSetSize <= convexSetSize + 2;
					

					lnIndex <= lnIndex - LNSIZE;
				end
				else if (positiveCrossCount == 0 && lnIndex != 0) begin
					nextCXAddr = currLine_A;
					j = 0;
					for (i = cxIndex; i < cxIndex + PTSIZE; i = i + 1) begin
						convexPoints[i] = nextCXAddr[j];
						j = j + 1;
					end
					cxIndex <= cxIndex + PTSIZE;
					convexSetSize <= convexSetSize + 1;


					lnIndex <= lnIndex - LNSIZE;
				end
				else begin
					nextLineAddr 	= {furthest, currLine_A};
					nextLineAddr2	= {currLine_B, furthest};


					j = 0;
					for (i = lnIndex; i < lnIndex + LNSIZE; i = i + 1) begin
						lineFIFO[i] = nextLineAddr[j];
						j = j + 1;
					end
					
					j = 0;
					for (i = lnIndex + LNSIZE; i < lnIndex + (LNSIZE * 2); i = i + 1) begin
						lineFIFO[i] = nextLineAddr2[j];
						j = j + 1;
					end						
					lnIndex <= lnIndex + LNSIZE;
				end

				if ((lnIndex) != 0) begin
					positiveCrossCount <= 0;
					furthest <= 0;
					furthestCrossValue <= 0;
					ptCount <= 0;
					state <= CROSS;
				end
				else begin
					state <= END;
				end
			end

			END: begin

			end

		endcase
	end

endmodule