data/full_repos/permissive/420117502/Basic/1_Half_Adder/tb.v
1: b'%Error: data/full_repos/permissive/420117502/Basic/1_Half_Adder/tb.v:14: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("./dumpfile.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/420117502/Basic/1_Half_Adder/tb.v:15: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/1_Half_Adder/tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n        # 20 $finish;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/420117502/Basic/1_Half_Adder/tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n    always # 1 clk <= ~clk;\n           ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb ();

    reg clk;
    reg [1:0]in;
    wire [1:0] res;
    Half_Adder ha(
        .a(in[1]),
        .b(in[0]),
        .sum(res[0]),
        .carry(res[1])
    );
    
    initial begin
        $dumpfile("./dumpfile.vcd");
        $dumpvars;
        clk<=1'b0;
        in<=2'b00;
        # 20 $finish;
    end
    always # 1 clk <= ~clk;
    always @(edge clk) begin
        in<=in+1'b1;
    end
endmodule
module tb ();


    reg clk;
    reg [1:0]in;
    wire [1:0] res;
    Half_Adder ha(
        .a(in[1]),
        .b(in[0]),
        .sum(res[0]),
        .carry(res[1])
    );
    
    initial begin
        $dumpfile("./dumpfile.vcd");
        $dumpvars;
        clk<=1'b0;
        in<=2'b00;
        # 20 $finish;
    end
    always # 1 clk <= ~clk;
    always @(edge clk) begin
        in<=in+1'b1;
    end
endmodule