data/full_repos/permissive/482974019/CORDIC.srcs/sources_1/new/SetDI.v
data/verilator_xmls/17a3ef2c-1809-4840-af1c-e8b1df74f7f4.xml
module SetDI #(parameter WLI = 8, WLF = 8)
    (input [(WLI+WLF)-1:0] in1, in2,
    output reg signed [1:0] di);
    
    always @(*) begin
        di = (in1 > in2) ? 1 : (in1 < in2) ? -1 : 0;
    end
endmodule
module SetDI #(parameter WLI = 8, WLF = 8)
    (input [(WLI+WLF)-1:0] in1, in2,
    output reg signed [1:0] di);

    
    always @(*) begin
        di = (in1 > in2) ? 1 : (in1 < in2) ? -1 : 0;
    end
endmodule