data/full_repos/permissive/46343463/src/ALU.v
1: b'%Error: data/full_repos/permissive/46343463/src/ALU.v:1: Cannot find include file: LookupTable.v\n`include "LookupTable.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/46343463/src,data/full_repos/permissive/46343463/LookupTable.v\n             data/full_repos/permissive/46343463/src,data/full_repos/permissive/46343463/LookupTable.v.v\n             data/full_repos/permissive/46343463/src,data/full_repos/permissive/46343463/LookupTable.v.sv\n             LookupTable.v\n             LookupTable.v.v\n             LookupTable.v.sv\n             obj_dir/LookupTable.v\n             obj_dir/LookupTable.v.v\n             obj_dir/LookupTable.v.sv\n%Error: data/full_repos/permissive/46343463/src/ALU.v:19: Define or directive not defined: \'`ADD_alu\'\n   `ADD_alu : data_o = data_1 + data_2;\n   ^~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/ALU.v:19: syntax error, unexpected \':\', expecting endcase\n   `ADD_alu : data_o = data_1 + data_2;\n            ^\n%Error: data/full_repos/permissive/46343463/src/ALU.v:20: Define or directive not defined: \'`SUB_alu\'\n   `SUB_alu : data_o = data_1 - data_2;\n   ^~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/ALU.v:21: Define or directive not defined: \'`MUL_alu\'\n   `MUL_alu : data_o = data_1 * data_2;\n   ^~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/ALU.v:22: Define or directive not defined: \'`AND_alu\'\n   `AND_alu : data_o = data_1 & data_2;\n   ^~~~~~~~\n%Error: data/full_repos/permissive/46343463/src/ALU.v:23: Define or directive not defined: \'`OR_alu\'\n   `OR_alu  : data_o = data_1 | data_2;\n   ^~~~~~~\n%Error: Cannot continue\n'
module ALU 
#(
	parameter data_width = 32
)
(
	input		[2:0]				ALUop_i,
	input		[data_width-1:0]	data_1, data_2,
	output reg 	[data_width-1:0]	data_o,
	output 							is_zero
);

	assign is_zero = (data_o == {data_width{1'b0}});

	always @ (*)
	begin
		case (ALUop_i)
			`ADD_alu	:	data_o = data_1 + data_2;
			`SUB_alu	:	data_o = data_1 - data_2;
			`MUL_alu	:	data_o = data_1 * data_2;
			`AND_alu	:	data_o = data_1 & data_2;
			`OR_alu		:	data_o = data_1 | data_2;
		endcase
	end

endmodule
module ALU 
#(
	parameter data_width = 32
)
(
	input		[2:0]				ALUop_i,
	input		[data_width-1:0]	data_1, data_2,
	output reg 	[data_width-1:0]	data_o,
	output 							is_zero
);


	assign is_zero = (data_o == {data_width{1'b0}});

	always @ (*)
	begin
		case (ALUop_i)
			`ADD_alu	:	data_o = data_1 + data_2;
			`SUB_alu	:	data_o = data_1 - data_2;
			`MUL_alu	:	data_o = data_1 * data_2;
			`AND_alu	:	data_o = data_1 & data_2;
			`OR_alu		:	data_o = data_1 | data_2;
		endcase
	end

endmodule