data/full_repos/permissive/515890445/ARM_MultiCycle/MultiCycle/Modules/Mux2x1.v
data/verilator_xmls/1a4be2c5-85ec-4ad4-8ad3-bd4c405de47c.xml
module Mux2x1
#(
	parameter W = 4
)
(
	input 	wire [W-1:0] 	In1,
	input 	wire [W-1:0] 	In2,
	input 	wire  			Sel,
	output 	wire [W-1:0]	Out
);

	assign Out = (Sel) ? In2 : In1;

endmodule
module Mux2x1
#(
	parameter W = 4
)
(
	input 	wire [W-1:0] 	In1,
	input 	wire [W-1:0] 	In2,
	input 	wire  			Sel,
	output 	wire [W-1:0]	Out
);


	assign Out = (Sel) ? In2 : In1;

endmodule