data/full_repos/permissive/51595169/VerilogSource/Decoder4x16/DecoderTestBench.v
1: b'%Error: data/full_repos/permissive/51595169/VerilogSource/Decoder4x16/DecoderTestBench.v:11: Unsupported: fork statements\ninitial fork\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Decoder4x16/DecoderTestBench.v:13: Unsupported: Ignoring delay on this delayed statement.\n  #1 in_test = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Decoder4x16/DecoderTestBench.v:14: Unsupported: Ignoring delay on this delayed statement.\n  #2 in_test = 2;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Decoder4x16/DecoderTestBench.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #3 in_test = 3;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Decoder4x16/DecoderTestBench.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #4 in_test = 4;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Decoder4x16/DecoderTestBench.v:17: Unsupported: Ignoring delay on this delayed statement.\n  #5 in_test = 5;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Decoder4x16/DecoderTestBench.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #6 in_test = 6;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Decoder4x16/DecoderTestBench.v:19: Unsupported: Ignoring delay on this delayed statement.\n  #7 in_test = 7;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Decoder4x16/DecoderTestBench.v:20: Unsupported: Ignoring delay on this delayed statement.\n  #8 in_test = 8;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Decoder4x16/DecoderTestBench.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #9 in_test = 9;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Decoder4x16/DecoderTestBench.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #10 in_test = 10;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Decoder4x16/DecoderTestBench.v:23: Unsupported: Ignoring delay on this delayed statement.\n  #11 in_test = 11;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Decoder4x16/DecoderTestBench.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #12 in_test = 12;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Decoder4x16/DecoderTestBench.v:25: Unsupported: Ignoring delay on this delayed statement.\n  #13 in_test = 13;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Decoder4x16/DecoderTestBench.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #14 in_test = 14;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Decoder4x16/DecoderTestBench.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #15 in_test = 15;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/51595169/VerilogSource/Decoder4x16/DecoderTestBench.v:31: Unsupported: Ignoring delay on this delayed statement.\ninitial #sim_time $finish;            \n        ^\n%Error: data/full_repos/permissive/51595169/VerilogSource/Decoder4x16/DecoderTestBench.v:36: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("DecoderTestBench.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/Decoder4x16/DecoderTestBench.v:37: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,DecoderTestBench);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/Decoder4x16/DecoderTestBench.v:39: Unsupported or unknown PLI call: $monitor\n $monitor("Time = %3d,IN = %3d,OUT=%4b",$time,in_test,out_test);\n ^~~~~~~~\n%Error: Exiting due to 4 error(s), 16 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module DecoderTestBench;

parameter sim_time = 750*2;

reg [3:0] in_test;
wire[15:0] out_test;

Decoder4x16 dec(.IN(in_test),.OUT(out_test));


initial fork
	 in_test = 0;
	 #1 in_test = 1;
	 #2 in_test = 2;
	 #3 in_test = 3;
	 #4 in_test = 4;
	 #5 in_test = 5;
	 #6 in_test = 6;
	 #7 in_test = 7;
	 #8 in_test = 8;
	 #9 in_test = 9;
	 #10 in_test = 10;
	 #11 in_test = 11;
	 #12 in_test = 12;
	 #13 in_test = 13;
	 #14 in_test = 14;
	 #15 in_test = 15;
join


initial #sim_time $finish;



initial begin
	$dumpfile("DecoderTestBench.vcd");
	$dumpvars(0,DecoderTestBench);
	$display(" Test Results" );
	$monitor("Time = %3d,IN = %3d,OUT=%4b",$time,in_test,out_test);
end

endmodule
module DecoderTestBench;


parameter sim_time = 750*2;

reg [3:0] in_test;
wire[15:0] out_test;

Decoder4x16 dec(.IN(in_test),.OUT(out_test));


initial fork
	 in_test = 0;
	 #1 in_test = 1;
	 #2 in_test = 2;
	 #3 in_test = 3;
	 #4 in_test = 4;
	 #5 in_test = 5;
	 #6 in_test = 6;
	 #7 in_test = 7;
	 #8 in_test = 8;
	 #9 in_test = 9;
	 #10 in_test = 10;
	 #11 in_test = 11;
	 #12 in_test = 12;
	 #13 in_test = 13;
	 #14 in_test = 14;
	 #15 in_test = 15;
join


initial #sim_time $finish;



initial begin
	$dumpfile("DecoderTestBench.vcd");
	$dumpvars(0,DecoderTestBench);
	$display(" Test Results" );
	$monitor("Time = %3d,IN = %3d,OUT=%4b",$time,in_test,out_test);
end

endmodule