data/full_repos/permissive/493019833/test/testcase/firrtl/MultiClockSubModuleTest/reference/MultiClockSubModuleTest.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/MultiClockSubModuleTest/reference/MultiClockSubModuleTest.v:178: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                                                         : ... In instance MultiClockSubModuleTest.u_pad_3\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/MultiClockSubModuleTest/reference/MultiClockSubModuleTest.v:178: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 2 bits.\n                                                                                                                                         : ... In instance MultiClockSubModuleTest.u_pad_11\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n%Error: Exiting due to 2 warning(s)\n'
module MultiClockSubModuleTestSubModule(
    input clock,
    input reset,
    output [3:0] io_out
);
    wire [3:0] _value__q;
    wire [3:0] _value__d;
    DFF_POSCLK #(.width(4)) value (
        .q(_value__q),
        .d(_value__d),
        .clk(clock)
    );
    wire [3:0] _WTEMP_5;
    MUX_UNSIGNED #(.width(4)) u_mux_13 (
        .y(_value__d),
        .sel(reset),
        .a(4'h0),
        .b(_WTEMP_5)
    );
    wire _T_7;
    EQ_UNSIGNED #(.width(4)) u_eq_14 (
        .y(_T_7),
        .a(_value__q),
        .b(4'h9)
    );
    wire [4:0] _T_9;
    wire [3:0] _WTEMP_6;
    PAD_UNSIGNED #(.width(1), .n(4)) u_pad_15 (
        .y(_WTEMP_6),
        .in(1'h1)
    );
    ADD_UNSIGNED #(.width(4)) u_add_16 (
        .y(_T_9),
        .a(_value__q),
        .b(_WTEMP_6)
    );
    wire [3:0] _T_10;
    TAIL #(.width(5), .n(1)) tail_17 (
        .y(_T_10),
        .in(_T_9)
    );
    wire [3:0] _node_1;
    wire [3:0] _WTEMP_7;
    PAD_UNSIGNED #(.width(1), .n(4)) u_pad_18 (
        .y(_WTEMP_7),
        .in(1'h0)
    );
    MUX_UNSIGNED #(.width(4)) u_mux_19 (
        .y(_node_1),
        .sel(_T_7),
        .a(_WTEMP_7),
        .b(_T_10)
    );
    wire _T_12;
    BITWISEAND #(.width(1)) bitwiseand_20 (
        .y(_T_12),
        .a(1'h1),
        .b(_T_7)
    );
    assign io_out = _value__q;
    MUX_UNSIGNED #(.width(4)) u_mux_21 (
        .y(_WTEMP_5),
        .sel(1'h1),
        .a(_node_1),
        .b(_value__q)
    );
endmodule
module MultiClockSubModuleTestSubModule(
    input clock,
    input reset,
    output [3:0] io_out
);

    wire [3:0] _value__q;
    wire [3:0] _value__d;
    DFF_POSCLK #(.width(4)) value (
        .q(_value__q),
        .d(_value__d),
        .clk(clock)
    );
    wire [3:0] _WTEMP_5;
    MUX_UNSIGNED #(.width(4)) u_mux_13 (
        .y(_value__d),
        .sel(reset),
        .a(4'h0),
        .b(_WTEMP_5)
    );
    wire _T_7;
    EQ_UNSIGNED #(.width(4)) u_eq_14 (
        .y(_T_7),
        .a(_value__q),
        .b(4'h9)
    );
    wire [4:0] _T_9;
    wire [3:0] _WTEMP_6;
    PAD_UNSIGNED #(.width(1), .n(4)) u_pad_15 (
        .y(_WTEMP_6),
        .in(1'h1)
    );
    ADD_UNSIGNED #(.width(4)) u_add_16 (
        .y(_T_9),
        .a(_value__q),
        .b(_WTEMP_6)
    );
    wire [3:0] _T_10;
    TAIL #(.width(5), .n(1)) tail_17 (
        .y(_T_10),
        .in(_T_9)
    );
    wire [3:0] _node_1;
    wire [3:0] _WTEMP_7;
    PAD_UNSIGNED #(.width(1), .n(4)) u_pad_18 (
        .y(_WTEMP_7),
        .in(1'h0)
    );
    MUX_UNSIGNED #(.width(4)) u_mux_19 (
        .y(_node_1),
        .sel(_T_7),
        .a(_WTEMP_7),
        .b(_T_10)
    );
    wire _T_12;
    BITWISEAND #(.width(1)) bitwiseand_20 (
        .y(_T_12),
        .a(1'h1),
        .b(_T_7)
    );
    assign io_out = _value__q;
    MUX_UNSIGNED #(.width(4)) u_mux_21 (
        .y(_WTEMP_5),
        .sel(1'h1),
        .a(_node_1),
        .b(_value__q)
    );
endmodule