data/full_repos/permissive/506820191/design_entry/voting_rule_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/506820191/design_entry/voting_rule_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n  forever #5 tb_o = ~tb_o;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/506820191/design_entry/voting_rule_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n  forever #10 tb_n = ~tb_n;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/506820191/design_entry/voting_rule_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n  forever #20 tb_w = ~tb_w;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/506820191/design_entry/voting_rule_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n  #40 $stop;\n  ^\n%Error: data/full_repos/permissive/506820191/design_entry/voting_rule_tb.v:47: Unsupported or unknown PLI call: $monitor\n  $monitor($time, "A=%b, B=%b, C=%b: a=%b, b=%b, c=%b, d=%b", \n  ^~~~~~~~\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module voting_rule_tb;

reg tb_w, tb_n, tb_o;
wire tb_a, tb_b, tb_c, tb_d;

	voting_rule DUT (tb_w, tb_n, tb_o, tb_a, tb_b, tb_c, tb_d);

	initial
	begin
		tb_o = 0;
		forever #5 tb_o = ~tb_o;
	end
	initial
	begin
		tb_n = 0;
		forever #10 tb_n = ~tb_n;
	end
	initial 
	begin
		tb_w = 0;
		forever #20 tb_w = ~tb_w;
	end

	initial
		#40 $stop;
	initial
		$monitor($time, "A=%b, B=%b, C=%b: a=%b, b=%b, c=%b, d=%b", 
		tb_w, tb_n, tb_o, tb_a, tb_b, tb_c, tb_d);	
endmodule
module voting_rule_tb;


reg tb_w, tb_n, tb_o;
wire tb_a, tb_b, tb_c, tb_d;

	voting_rule DUT (tb_w, tb_n, tb_o, tb_a, tb_b, tb_c, tb_d);

	initial
	begin
		tb_o = 0;
		forever #5 tb_o = ~tb_o;
	end
	initial
	begin
		tb_n = 0;
		forever #10 tb_n = ~tb_n;
	end
	initial 
	begin
		tb_w = 0;
		forever #20 tb_w = ~tb_w;
	end

	initial
		#40 $stop;
	initial
		$monitor($time, "A=%b, B=%b, C=%b: a=%b, b=%b, c=%b, d=%b", 
		tb_w, tb_n, tb_o, tb_a, tb_b, tb_c, tb_d);	
endmodule