data/full_repos/permissive/490492655/regn.v
data/verilator_xmls/5f55b3e9-a63d-43d2-8cde-c927db27eb20.xml
module regn #(parameter n = 8) (
	input clk, rst, pst, en,
	input [n-1:0] d,
	output reg [n-1:0] q
);

	always @ (negedge rst, posedge pst, negedge clk)
	begin
		if (rst == 0) q <= 0;
		else if (pst == 1) q <= { n{1'b1} };
		else if (en == 1) q <= d;
		else q <= q;
	end

endmodule
module regn #(parameter n = 8) (
	input clk, rst, pst, en,
	input [n-1:0] d,
	output reg [n-1:0] q
);


	always @ (negedge rst, posedge pst, negedge clk)
	begin
		if (rst == 0) q <= 0;
		else if (pst == 1) q <= { n{1'b1} };
		else if (en == 1) q <= d;
		else q <= q;
	end

endmodule