data/full_repos/permissive/505898990/verilog/rtl/distance_display.v
1: b'%Warning-WIDTH: data/full_repos/permissive/505898990/verilog/rtl/distance_display.v:192: Operator ASSIGNDLY expects 12 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 11 bits.\n                                                                                       : ... In instance distance_display.b_t_btc\n        r_bcd <= {DECIMAL_DIGITS*4-1{1\'b0}};\n              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/505898990/verilog/rtl/distance_display.v:193: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                       : ... In instance distance_display.b_t_btc\n        r_Binary <= {INPUT_WIDTH-1{1\'b0}};\n                 ^~\n%Warning-WIDTH: data/full_repos/permissive/505898990/verilog/rtl/distance_display.v:194: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n                                                                                       : ... In instance distance_display.b_t_btc\n        r_Digit_Index <= {DECIMAL_DIGITS-1{1\'b0}};\n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/505898990/verilog/rtl/distance_display.v:124: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'s_COUNT_ECHO\' generates 2 bits.\n                                                                                       : ... In instance distance_display.d_m\n            if(!s_COUNT_ECHO || r_measurment_counter_10_uS > MAX_DISTANCE_CYCLES - 1) begin\n               ^\n%Warning-WIDTH: data/full_repos/permissive/505898990/verilog/rtl/distance_display.v:134: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s DIVS generates 32 bits.\n                                                                                       : ... In instance distance_display.d_m\n            o_distance <= ((r_measurment_counter_10_uS / 10)) / 58;\n                       ^~\n%Error: Exiting due to 5 warning(s)\n'
module binary_to_bcd
  #(parameter INPUT_WIDTH = 9,
    parameter DECIMAL_DIGITS = 3)
  (
   input wire                           i_clk,
   input wire                           i_reset,
   input wire [INPUT_WIDTH-1:0]         i_binary,
   input wire                           i_start,

   output wire [DECIMAL_DIGITS*4-1:0]   o_bcd,
   output wire                          o_finished
   );
   

  localparam s_IDLE              = 3'b000;
  localparam s_SHIFT             = 3'b001;
  localparam s_CHECK_SHIFT_INDEX = 3'b010;
  localparam s_ADD               = 3'b011;
  localparam s_CHECK_DIGIT_INDEX = 3'b100;
  localparam s_BCD_DONE          = 3'b101;


  reg [2:0] r_current_state;
   

  reg [DECIMAL_DIGITS*4-1:0] r_bcd;
    

  reg [INPUT_WIDTH-1:0]      r_Binary;
      

  reg [DECIMAL_DIGITS-1:0]   r_Digit_Index;
    


  reg [7:0]                  r_Loop_Count;
 
  wire [3:0]                 w_BCD_Digit;
  reg                        r_DV;                       
    
  always @(posedge i_clk)
    begin

      if (i_reset) begin
        r_current_state <= s_IDLE;
        r_bcd <= {DECIMAL_DIGITS*4-1{1'b0}};
        r_Binary <= {INPUT_WIDTH-1{1'b0}};
        r_Digit_Index <= {DECIMAL_DIGITS-1{1'b0}};
        r_Loop_Count <= {8{1'b0}};
        r_DV <= 0;


      end else begin
 
      case (r_current_state) 
  

        s_IDLE :
          begin
            r_DV <= 1'b0;
            
             
            if (i_start == 1'b1)
              begin
                r_Binary  <= i_binary;
                r_current_state <= s_SHIFT;
                r_bcd     <= 0;
              end
            else
              r_current_state <= s_IDLE;
          end
                 
  


        s_SHIFT :
          begin
            r_bcd     <= r_bcd << 1;
            r_bcd[0]  <= r_Binary[INPUT_WIDTH-1];
            r_Binary  <= r_Binary << 1;
            r_current_state <= s_CHECK_SHIFT_INDEX;
          end          
         
  

        s_CHECK_SHIFT_INDEX :
          begin
            if (r_Loop_Count == INPUT_WIDTH-1)
              begin
                r_Loop_Count <= 0;
                r_current_state    <= s_BCD_DONE;
              end
            else
              begin
                r_Loop_Count <= r_Loop_Count + 1;
                r_current_state    <= s_ADD;
              end
          end
                 
  



        s_ADD :
          begin
            if (w_BCD_Digit > 4)
              begin                                     
                r_bcd[(r_Digit_Index*4)+:4] <= w_BCD_Digit + 3;  
              end
             
            r_current_state <= s_CHECK_DIGIT_INDEX; 
          end       
         
         

        s_CHECK_DIGIT_INDEX :
          begin
            if (r_Digit_Index == DECIMAL_DIGITS-1)
              begin
                r_Digit_Index <= 0;
                r_current_state     <= s_SHIFT;
              end
            else
              begin
                r_Digit_Index <= r_Digit_Index + 1;
                r_current_state     <= s_ADD;
              end
          end
         
        s_BCD_DONE :
          begin
            r_DV      <= 1'b1;
            r_current_state <= s_IDLE;
          end
         
         
        default :
          r_current_state <= s_IDLE;
            
      endcase
    end
  end
   
  assign w_BCD_Digit = r_bcd[r_Digit_Index*4 +: 4];
       
  assign o_bcd = r_bcd;
  assign o_finished  = r_DV;
      
endmodule
module binary_to_bcd
  #(parameter INPUT_WIDTH = 9,
    parameter DECIMAL_DIGITS = 3)
  (
   input wire                           i_clk,
   input wire                           i_reset,
   input wire [INPUT_WIDTH-1:0]         i_binary,
   input wire                           i_start,

   output wire [DECIMAL_DIGITS*4-1:0]   o_bcd,
   output wire                          o_finished
   );

   

  localparam s_IDLE              = 3'b000;
  localparam s_SHIFT             = 3'b001;
  localparam s_CHECK_SHIFT_INDEX = 3'b010;
  localparam s_ADD               = 3'b011;
  localparam s_CHECK_DIGIT_INDEX = 3'b100;
  localparam s_BCD_DONE          = 3'b101;


  reg [2:0] r_current_state;
   

  reg [DECIMAL_DIGITS*4-1:0] r_bcd;
    

  reg [INPUT_WIDTH-1:0]      r_Binary;
      

  reg [DECIMAL_DIGITS-1:0]   r_Digit_Index;
    


  reg [7:0]                  r_Loop_Count;
 
  wire [3:0]                 w_BCD_Digit;
  reg                        r_DV;                       
    
  always @(posedge i_clk)
    begin

      if (i_reset) begin
        r_current_state <= s_IDLE;
        r_bcd <= {DECIMAL_DIGITS*4-1{1'b0}};
        r_Binary <= {INPUT_WIDTH-1{1'b0}};
        r_Digit_Index <= {DECIMAL_DIGITS-1{1'b0}};
        r_Loop_Count <= {8{1'b0}};
        r_DV <= 0;


      end else begin
 
      case (r_current_state) 
  

        s_IDLE :
          begin
            r_DV <= 1'b0;
            
             
            if (i_start == 1'b1)
              begin
                r_Binary  <= i_binary;
                r_current_state <= s_SHIFT;
                r_bcd     <= 0;
              end
            else
              r_current_state <= s_IDLE;
          end
                 
  


        s_SHIFT :
          begin
            r_bcd     <= r_bcd << 1;
            r_bcd[0]  <= r_Binary[INPUT_WIDTH-1];
            r_Binary  <= r_Binary << 1;
            r_current_state <= s_CHECK_SHIFT_INDEX;
          end          
         
  

        s_CHECK_SHIFT_INDEX :
          begin
            if (r_Loop_Count == INPUT_WIDTH-1)
              begin
                r_Loop_Count <= 0;
                r_current_state    <= s_BCD_DONE;
              end
            else
              begin
                r_Loop_Count <= r_Loop_Count + 1;
                r_current_state    <= s_ADD;
              end
          end
                 
  



        s_ADD :
          begin
            if (w_BCD_Digit > 4)
              begin                                     
                r_bcd[(r_Digit_Index*4)+:4] <= w_BCD_Digit + 3;  
              end
             
            r_current_state <= s_CHECK_DIGIT_INDEX; 
          end       
         
         

        s_CHECK_DIGIT_INDEX :
          begin
            if (r_Digit_Index == DECIMAL_DIGITS-1)
              begin
                r_Digit_Index <= 0;
                r_current_state     <= s_SHIFT;
              end
            else
              begin
                r_Digit_Index <= r_Digit_Index + 1;
                r_current_state     <= s_ADD;
              end
          end
         
        s_BCD_DONE :
          begin
            r_DV      <= 1'b1;
            r_current_state <= s_IDLE;
          end
         
         
        default :
          r_current_state <= s_IDLE;
            
      endcase
    end
  end
   
  assign w_BCD_Digit = r_bcd[r_Digit_Index*4 +: 4];
       
  assign o_bcd = r_bcd;
  assign o_finished  = r_DV;
      
endmodule