data/full_repos/permissive/476412093/Tile.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/476412093/Tile.v:248: Signal definition not found, creating implicitly: \'east\'\n  assign Eout_Wout_0[8*gi+:8] = (east)?EtoW_WtoE[gi][TILE_DIM-1][0]:(west)?EtoW_WtoE[gi][0][0]:8\'bz;\n                                 ^~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/476412093/Tile.v:248: Signal definition not found, creating implicitly: \'west\'\n  assign Eout_Wout_0[8*gi+:8] = (east)?EtoW_WtoE[gi][TILE_DIM-1][0]:(west)?EtoW_WtoE[gi][0][0]:8\'bz;\n                                                                     ^~~~\n%Warning-IMPLICIT: data/full_repos/permissive/476412093/Tile.v:249: Signal definition not found, creating implicitly: \'north\'\n  assign Nout_Sout_0[8*gj+:8] = (north)?NtoS_StoN[0][gj][0]:(south)?NtoS_StoN[TILE_DIM-1][gj][0]:8\'bz;\n                                 ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/476412093/Tile.v:249: Signal definition not found, creating implicitly: \'south\'\n  assign Nout_Sout_0[8*gj+:8] = (north)?NtoS_StoN[0][gj][0]:(south)?NtoS_StoN[TILE_DIM-1][gj][0]:8\'bz;\n                                                             ^~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/476412093/Tile.v:46: Little bit endian vector: MSB < LSB of bit range: 0:7\n  input[0:TILE_DIM*8-1] Ein_Win_0,\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/476412093/Tile.v:47: Little bit endian vector: MSB < LSB of bit range: 0:7\n  input[0:TILE_DIM*8-1] Nin_Sin_0,\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/476412093/Tile.v:48: Little bit endian vector: MSB < LSB of bit range: 0:7\n  input[0:TILE_DIM*8-1] Ein_Win_1,\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/476412093/Tile.v:49: Little bit endian vector: MSB < LSB of bit range: 0:7\n  input[0:TILE_DIM*8-1] Nin_Sin_1,\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/476412093/Tile.v:50: Little bit endian vector: MSB < LSB of bit range: 0:7\n  input[0:TILE_DIM*8-1] Ein_Win_2,\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/476412093/Tile.v:51: Little bit endian vector: MSB < LSB of bit range: 0:7\n  input[0:TILE_DIM*8-1] Nin_Sin_2,\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/476412093/Tile.v:52: Little bit endian vector: MSB < LSB of bit range: 0:7\n  input[0:TILE_DIM*8-1] Ein_Win_3,\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/476412093/Tile.v:53: Little bit endian vector: MSB < LSB of bit range: 0:7\n  input[0:TILE_DIM*8-1] Nin_Sin_3,\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/476412093/Tile.v:58: Little bit endian vector: MSB < LSB of bit range: 0:7\n  output[0:TILE_DIM*8-1] Eout_Wout_0,\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/476412093/Tile.v:59: Little bit endian vector: MSB < LSB of bit range: 0:7\n  output[0:TILE_DIM*8-1] Nout_Sout_0, \n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/476412093/Tile.v:60: Little bit endian vector: MSB < LSB of bit range: 0:7\n  output[0:TILE_DIM*8-1] Eout_Wout_1,\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/476412093/Tile.v:61: Little bit endian vector: MSB < LSB of bit range: 0:7\n  output[0:TILE_DIM*8-1] Nout_Sout_1,  \n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/476412093/Tile.v:62: Little bit endian vector: MSB < LSB of bit range: 0:7\n  output[0:TILE_DIM*8-1] Eout_Wout_2,\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/476412093/Tile.v:63: Little bit endian vector: MSB < LSB of bit range: 0:7\n  output[0:TILE_DIM*8-1] Nout_Sout_2, \n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/476412093/Tile.v:64: Little bit endian vector: MSB < LSB of bit range: 0:7\n  output[0:TILE_DIM*8-1] Eout_Wout_3,\n        ^\n%Warning-LITENDIAN: data/full_repos/permissive/476412093/Tile.v:65: Little bit endian vector: MSB < LSB of bit range: 0:7\n  output[0:TILE_DIM*8-1] Nout_Sout_3\n        ^\n%Warning-WIDTH: data/full_repos/permissive/476412093/Tile.v:93: Bit extraction of array[0:0] requires 1 bit index, not 8 bits.\n                                                              : ... In instance Tile\nassign DOA = wDOA[BRAM_i][BRAM_j];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/476412093/Tile.v:93: Bit extraction of array[0:0] requires 1 bit index, not 8 bits.\n                                                              : ... In instance Tile\nassign DOA = wDOA[BRAM_i][BRAM_j];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/476412093/Tile.v:94: Bit extraction of array[0:0] requires 1 bit index, not 8 bits.\n                                                              : ... In instance Tile\nassign DOB = wDOB[BRAM_i][BRAM_j];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/476412093/Tile.v:94: Bit extraction of array[0:0] requires 1 bit index, not 8 bits.\n                                                              : ... In instance Tile\nassign DOB = wDOB[BRAM_i][BRAM_j];\n                         ^\n%Error: data/full_repos/permissive/476412093/Tile.v:96: Cannot find file containing module: \'Controller\'\nController #(32) FSM\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/476412093,data/full_repos/permissive/476412093/Controller\n             data/full_repos/permissive/476412093,data/full_repos/permissive/476412093/Controller.v\n             data/full_repos/permissive/476412093,data/full_repos/permissive/476412093/Controller.sv\n             Controller\n             Controller.v\n             Controller.sv\n             obj_dir/Controller\n             obj_dir/Controller.v\n             obj_dir/Controller.sv\n%Error: data/full_repos/permissive/476412093/Tile.v:132: Cannot find file containing module: \'PE16_Block\'\n  PE16_Block #(TILE_DIM, 32) block \n  ^~~~~~~~~~\n%Error: Exiting due to 2 error(s), 24 warning(s)\n'
module Tile #(parameter TILE_DIM = 1)(
		input clk,
		input reset,
		input start,
		input[31:0] instruction,
		input external,
		input[7:0] BRAM_i,
		input[7:0] BRAM_j,
		input WEA,
		input WEB,
		input[9:0] ADDRA,
		input[9:0] ADDRB,
		input[15:0] DIA,
		input[15:0] DIB,
		output[15:0] DOA,
		output[15:0] DOB,




		input[0:TILE_DIM*8-1] Ein_Win_0,
		input[0:TILE_DIM*8-1] Nin_Sin_0,
		input[0:TILE_DIM*8-1] Ein_Win_1,
		input[0:TILE_DIM*8-1] Nin_Sin_1,
		input[0:TILE_DIM*8-1] Ein_Win_2,
		input[0:TILE_DIM*8-1] Nin_Sin_2,
		input[0:TILE_DIM*8-1] Ein_Win_3,
		input[0:TILE_DIM*8-1] Nin_Sin_3,




		output[0:TILE_DIM*8-1] Eout_Wout_0,
		output[0:TILE_DIM*8-1] Nout_Sout_0, 
		output[0:TILE_DIM*8-1] Eout_Wout_1,
		output[0:TILE_DIM*8-1] Nout_Sout_1,		
		output[0:TILE_DIM*8-1] Eout_Wout_2,
		output[0:TILE_DIM*8-1] Nout_Sout_2,	
		output[0:TILE_DIM*8-1] Eout_Wout_3,
		output[0:TILE_DIM*8-1] Nout_Sout_3

    );

wire[3:0] alu_op;

wire[9:0] addra;
wire[9:0] addrb;
wire[1:0] east_mode;
wire[1:0] west_mode;
wire[1:0] south_mode;
wire[1:0] north_mode;
wire[4:0] num_shift;

wire[7:0] count;
wire[2:0] state;






wire[7:0] EtoW_WtoE[TILE_DIM-1:0][TILE_DIM-1:0][3:0];
wire[7:0] NtoS_StoN[TILE_DIM-1:0][TILE_DIM-1:0][3:0];

wire[15:0] wDOA[TILE_DIM-1:0][TILE_DIM-1:0];
wire[15:0] wDOB[TILE_DIM-1:0][TILE_DIM-1:0];

assign DOA = wDOA[BRAM_i][BRAM_j];
assign DOB = wDOB[BRAM_i][BRAM_j];

Controller #(32) FSM
		(
			clk, 
			reset,
			start,
			instruction,

			alu_op,

			wea,
			web,
			addra, 
			addrb,

			east,	
			west,	
			south,	
			north,
			east_mode,
			west_mode,
			south_mode,
			north_mode,
			num_shift,

			count,
			state
		);


generate

genvar gi;
genvar gj;

for (gi=0; gi<TILE_DIM; gi=gi+1) begin : ROW
	for (gj=0; gj<TILE_DIM; gj=gj+1) begin : COL
		PE16_Block #(TILE_DIM, 32) block 
		(
			clk,
			reset,


			alu_op,

			(gi==BRAM_i && gj==BRAM_j? (external? WEA : wea) : wea),
			(gi==BRAM_i && gj==BRAM_j? (external? WEB : web) : web),
			(gi==BRAM_i && gj==BRAM_j? (external? ADDRA : addra) : addra),
			(gi==BRAM_i && gj==BRAM_j? (external? ADDRB : addrb) : addrb),
            gi==BRAM_i && gj==BRAM_j? DIA : 16'hzzzz,
            gi==BRAM_i && gj==BRAM_j? DIB : 16'hzzzz,
		    wDOA[gi][gj],
            wDOB[gi][gj],
            external,

			count,


			state,

			east,	
			west,	
			south,		
			north,		





			(num_shift == 1)? (west)?EtoW_WtoE[gi][gj][1]:
							  (east)?(gj==0)?Ein_Win_0[8*gi+:8]:EtoW_WtoE[gi][gj-1][3]:8'bz
			:(num_shift == 2)?(west)?EtoW_WtoE[gi][gj][2]:
							  (east)?(gj==0)?Ein_Win_0[8*gi+:8]:EtoW_WtoE[gi][gj-1][2]:8'bz
			:(num_shift >= 4)?(west)?(gj==TILE_DIM-num_shift/4)?Ein_Win_0[8*gi+:8]:EtoW_WtoE[gi][gj+num_shift/4][0]:
							  (east)?(gj==num_shift/4-1)?Ein_Win_0[8*gi+:8]:EtoW_WtoE[gi][gj-num_shift/4][0]:8'bz:8'bz,


			(num_shift == 1)? (north)?NtoS_StoN[gi][gj][1]:
							  (south)?(gi==0)?Nin_Sin_0[8*gj+:8]:NtoS_StoN[gi-1][gj][3]:8'bz
			:(num_shift == 2)?(north)?NtoS_StoN[gi][gj][2]:
							  (south)?(gi==0)?Nin_Sin_0[8*gj+:8]:NtoS_StoN[gi-1][gj][2]:8'bz
			:(num_shift >= 4)?(north)?(gi==TILE_DIM-num_shift/4)?Nin_Sin_0[8*gj+:8]:NtoS_StoN[gi+num_shift/4][gj][0]:
							  (south)?(gj==num_shift/4-1)?Nin_Sin_0[8*gj+:8]:NtoS_StoN[gi-num_shift/4][gj][0]:8'bz:8'bz,
									 
			
			(num_shift == 1)? (west)?EtoW_WtoE[gi][gj][2]:
							  (east)?(gj==0)?Ein_Win_1[8*gi+:8]:EtoW_WtoE[gi][gj][0]:8'bz
			:(num_shift == 2)?(west)?EtoW_WtoE[gi][gj][3]:
							  (east)?(gj==0)?Ein_Win_1[8*gi+:8]:EtoW_WtoE[gi][gj-1][3]:8'bz
			:(num_shift >= 4)?(west)?(gj==TILE_DIM-num_shift/4)?Ein_Win_1[8*gi+:8]:EtoW_WtoE[gi][gj+num_shift/4][0]:
							  (east)?(gj==num_shift/4-1)?Ein_Win_1[8*gi+:8]:EtoW_WtoE[gi][gj-num_shift/4][1]:8'bz:8'bz,


			(num_shift == 1)? (north)?NtoS_StoN[gi][gj][2]:
							  (south)?NtoS_StoN[gi][gj][0]:8'bz
			:(num_shift == 2)?(north)?NtoS_StoN[gi][gj][3]:
							  (south)?(gi==0)?Nin_Sin_1[8*gj+:8]:NtoS_StoN[gi-1][gj][3]:8'bz
			:(num_shift >= 4)?(north)?(gi==TILE_DIM-num_shift/4)?Nin_Sin_1[8*gj+:8]:NtoS_StoN[gi+num_shift/4][gj][1]:
							  (south)?(gi==num_shift/4-1)?Nin_Sin_1[8*gj+:8]:NtoS_StoN[gi-num_shift/4][gj][1]:8'bz:8'bz,
									 
			
			(num_shift == 1)? (west)?EtoW_WtoE[gi][gj][3]:
							  (east)?EtoW_WtoE[gi][gj][1]:8'bz
			:(num_shift == 2)?(west)?(gj==TILE_DIM-1)?Ein_Win_2[8*gi+:8]:EtoW_WtoE[gi][gj+1][0]:
							  (east)?EtoW_WtoE[gi][gj][0]:8'bz
			:(num_shift >= 4)?(west)?(gj==TILE_DIM-num_shift/4)?Ein_Win_2[8*gi+:8]:EtoW_WtoE[gi][gj+num_shift/4][2]:
							  (east)?(gj==num_shift/4-1)?Ein_Win_2[8*gi+:8]:EtoW_WtoE[gi][gj-num_shift/4][2]:8'bz:8'bz,


			(num_shift == 1)? (north)?NtoS_StoN[gi][gj][3]:
							  (south)?NtoS_StoN[gi][gj][1]:8'bz
			:(num_shift == 2)?(north)?(gi==TILE_DIM-1)?Nin_Sin_2[8*gj+:8]:NtoS_StoN[gi+1][gj][0]:							  
							  (south)?NtoS_StoN[gi][gj][0]:8'bz
			:(num_shift >= 4)?(north)?(gj==TILE_DIM-num_shift/4)?Nin_Sin_2[8*gj+:8]:NtoS_StoN[gi+num_shift/4][gj][2]:
							  (south)?(gj==num_shift/4-1)?Nin_Sin_2[8*gj+:8]:NtoS_StoN[gi-num_shift/4][gj][0]:8'bz:8'bz,
									 
			
			(num_shift == 1)? (west)?(gj==TILE_DIM-1)?Ein_Win_3[8*gi+:8]:EtoW_WtoE[gi][gj+1][0]:
							  (east)?EtoW_WtoE[gi][gj][2]:8'bz
			:(num_shift == 2)?(west)?EtoW_WtoE[gi][gj][1]:
							  (east)?(gj==TILE_DIM-1)?Ein_Win_3[8*gi+:8]:EtoW_WtoE[gi][gj+1][1]:8'bz
			:(num_shift >= 4)?(west)?(gj==TILE_DIM-num_shift/4)?Ein_Win_3[8*gi+:8]:EtoW_WtoE[gi][gj+num_shift/4][3]:
							  (east)?(gj==num_shift/4-1)?Ein_Win_3[8*gi+:8]:EtoW_WtoE[gi][gj-num_shift/4][0]:8'bz:8'bz,


			(num_shift == 1)? (north)?(gj==TILE_DIM-1)?Nin_Sin_3[8*gj+:8]:NtoS_StoN[gi+1][gj][0]:
							  (south)?NtoS_StoN[gi][gj][2]:8'bz
			:(num_shift == 2)?(north)?(gj==TILE_DIM-1)?Nin_Sin_3[8*gj+:8]:NtoS_StoN[gi+1][gj][1]:
							  (south)?NtoS_StoN[gi][gj][1]:8'bz
			:(num_shift >= 4)?(north)?(gj==TILE_DIM-num_shift/4)?Nin_Sin_3[8*gj+:8]:NtoS_StoN[gi+num_shift/4][gj][3]:
							  (south)?(gj==num_shift/4-1)?Nin_Sin_3[8*gj+:8]:NtoS_StoN[gi-num_shift/4][gj][3]:8'bz:8'bz,
			
			
			EtoW_WtoE[gi][gj][0],
			NtoS_StoN[gi][gj][0],
			
			EtoW_WtoE[gi][gj][1],
			NtoS_StoN[gi][gj][1],
			
			EtoW_WtoE[gi][gj][2],
			NtoS_StoN[gi][gj][2],
			
			EtoW_WtoE[gi][gj][3],
			NtoS_StoN[gi][gj][3],
		
			num_shift
		
		);




		
		assign Eout_Wout_0[8*gi+:8] = (east)?EtoW_WtoE[gi][TILE_DIM-1][0]:(west)?EtoW_WtoE[gi][0][0]:8'bz;
		assign Nout_Sout_0[8*gj+:8] = (north)?NtoS_StoN[0][gj][0]:(south)?NtoS_StoN[TILE_DIM-1][gj][0]:8'bz;
		assign Eout_Wout_1[8*gi+:8] = (east)?EtoW_WtoE[gi][TILE_DIM-1][1]:(west)?EtoW_WtoE[gi][0][1]:8'bz;
		assign Nout_Sout_1[8*gj+:8] = (north)?NtoS_StoN[0][gj][1]:(south)?NtoS_StoN[TILE_DIM-1][gj][1]:8'bz;
		assign Eout_Wout_2[8*gi+:8] = (east)?EtoW_WtoE[gi][TILE_DIM-1][2]:(west)?EtoW_WtoE[gi][0][2]:8'bz;
		assign Nout_Sout_2[8*gj+:8] = (north)?NtoS_StoN[0][gj][2]:(south)?NtoS_StoN[TILE_DIM-1][gj][2]:8'bz;
		assign Eout_Wout_3[8*gi+:8] = (east)?EtoW_WtoE[gi][TILE_DIM-1][3]:(west)?EtoW_WtoE[gi][0][3]:8'bz;
		assign Nout_Sout_3[8*gj+:8] = (north)?NtoS_StoN[0][gj][3]:(south)?NtoS_StoN[TILE_DIM-1][gj][3]:8'bz;
		








		
		
		

	end
  end
  
endgenerate
endmodule
module Tile #(parameter TILE_DIM = 1)(
		input clk,
		input reset,
		input start,
		input[31:0] instruction,
		input external,
		input[7:0] BRAM_i,
		input[7:0] BRAM_j,
		input WEA,
		input WEB,
		input[9:0] ADDRA,
		input[9:0] ADDRB,
		input[15:0] DIA,
		input[15:0] DIB,
		output[15:0] DOA,
		output[15:0] DOB,




		input[0:TILE_DIM*8-1] Ein_Win_0,
		input[0:TILE_DIM*8-1] Nin_Sin_0,
		input[0:TILE_DIM*8-1] Ein_Win_1,
		input[0:TILE_DIM*8-1] Nin_Sin_1,
		input[0:TILE_DIM*8-1] Ein_Win_2,
		input[0:TILE_DIM*8-1] Nin_Sin_2,
		input[0:TILE_DIM*8-1] Ein_Win_3,
		input[0:TILE_DIM*8-1] Nin_Sin_3,




		output[0:TILE_DIM*8-1] Eout_Wout_0,
		output[0:TILE_DIM*8-1] Nout_Sout_0, 
		output[0:TILE_DIM*8-1] Eout_Wout_1,
		output[0:TILE_DIM*8-1] Nout_Sout_1,		
		output[0:TILE_DIM*8-1] Eout_Wout_2,
		output[0:TILE_DIM*8-1] Nout_Sout_2,	
		output[0:TILE_DIM*8-1] Eout_Wout_3,
		output[0:TILE_DIM*8-1] Nout_Sout_3

    );


wire[3:0] alu_op;

wire[9:0] addra;
wire[9:0] addrb;
wire[1:0] east_mode;
wire[1:0] west_mode;
wire[1:0] south_mode;
wire[1:0] north_mode;
wire[4:0] num_shift;

wire[7:0] count;
wire[2:0] state;






wire[7:0] EtoW_WtoE[TILE_DIM-1:0][TILE_DIM-1:0][3:0];
wire[7:0] NtoS_StoN[TILE_DIM-1:0][TILE_DIM-1:0][3:0];

wire[15:0] wDOA[TILE_DIM-1:0][TILE_DIM-1:0];
wire[15:0] wDOB[TILE_DIM-1:0][TILE_DIM-1:0];

assign DOA = wDOA[BRAM_i][BRAM_j];
assign DOB = wDOB[BRAM_i][BRAM_j];

Controller #(32) FSM
		(
			clk, 
			reset,
			start,
			instruction,

			alu_op,

			wea,
			web,
			addra, 
			addrb,

			east,	
			west,	
			south,	
			north,
			east_mode,
			west_mode,
			south_mode,
			north_mode,
			num_shift,

			count,
			state
		);


generate

genvar gi;
genvar gj;

for (gi=0; gi<TILE_DIM; gi=gi+1) begin : ROW
	for (gj=0; gj<TILE_DIM; gj=gj+1) begin : COL
		PE16_Block #(TILE_DIM, 32) block 
		(
			clk,
			reset,


			alu_op,

			(gi==BRAM_i && gj==BRAM_j? (external? WEA : wea) : wea),
			(gi==BRAM_i && gj==BRAM_j? (external? WEB : web) : web),
			(gi==BRAM_i && gj==BRAM_j? (external? ADDRA : addra) : addra),
			(gi==BRAM_i && gj==BRAM_j? (external? ADDRB : addrb) : addrb),
            gi==BRAM_i && gj==BRAM_j? DIA : 16'hzzzz,
            gi==BRAM_i && gj==BRAM_j? DIB : 16'hzzzz,
		    wDOA[gi][gj],
            wDOB[gi][gj],
            external,

			count,


			state,

			east,	
			west,	
			south,		
			north,		





			(num_shift == 1)? (west)?EtoW_WtoE[gi][gj][1]:
							  (east)?(gj==0)?Ein_Win_0[8*gi+:8]:EtoW_WtoE[gi][gj-1][3]:8'bz
			:(num_shift == 2)?(west)?EtoW_WtoE[gi][gj][2]:
							  (east)?(gj==0)?Ein_Win_0[8*gi+:8]:EtoW_WtoE[gi][gj-1][2]:8'bz
			:(num_shift >= 4)?(west)?(gj==TILE_DIM-num_shift/4)?Ein_Win_0[8*gi+:8]:EtoW_WtoE[gi][gj+num_shift/4][0]:
							  (east)?(gj==num_shift/4-1)?Ein_Win_0[8*gi+:8]:EtoW_WtoE[gi][gj-num_shift/4][0]:8'bz:8'bz,


			(num_shift == 1)? (north)?NtoS_StoN[gi][gj][1]:
							  (south)?(gi==0)?Nin_Sin_0[8*gj+:8]:NtoS_StoN[gi-1][gj][3]:8'bz
			:(num_shift == 2)?(north)?NtoS_StoN[gi][gj][2]:
							  (south)?(gi==0)?Nin_Sin_0[8*gj+:8]:NtoS_StoN[gi-1][gj][2]:8'bz
			:(num_shift >= 4)?(north)?(gi==TILE_DIM-num_shift/4)?Nin_Sin_0[8*gj+:8]:NtoS_StoN[gi+num_shift/4][gj][0]:
							  (south)?(gj==num_shift/4-1)?Nin_Sin_0[8*gj+:8]:NtoS_StoN[gi-num_shift/4][gj][0]:8'bz:8'bz,
									 
			
			(num_shift == 1)? (west)?EtoW_WtoE[gi][gj][2]:
							  (east)?(gj==0)?Ein_Win_1[8*gi+:8]:EtoW_WtoE[gi][gj][0]:8'bz
			:(num_shift == 2)?(west)?EtoW_WtoE[gi][gj][3]:
							  (east)?(gj==0)?Ein_Win_1[8*gi+:8]:EtoW_WtoE[gi][gj-1][3]:8'bz
			:(num_shift >= 4)?(west)?(gj==TILE_DIM-num_shift/4)?Ein_Win_1[8*gi+:8]:EtoW_WtoE[gi][gj+num_shift/4][0]:
							  (east)?(gj==num_shift/4-1)?Ein_Win_1[8*gi+:8]:EtoW_WtoE[gi][gj-num_shift/4][1]:8'bz:8'bz,


			(num_shift == 1)? (north)?NtoS_StoN[gi][gj][2]:
							  (south)?NtoS_StoN[gi][gj][0]:8'bz
			:(num_shift == 2)?(north)?NtoS_StoN[gi][gj][3]:
							  (south)?(gi==0)?Nin_Sin_1[8*gj+:8]:NtoS_StoN[gi-1][gj][3]:8'bz
			:(num_shift >= 4)?(north)?(gi==TILE_DIM-num_shift/4)?Nin_Sin_1[8*gj+:8]:NtoS_StoN[gi+num_shift/4][gj][1]:
							  (south)?(gi==num_shift/4-1)?Nin_Sin_1[8*gj+:8]:NtoS_StoN[gi-num_shift/4][gj][1]:8'bz:8'bz,
									 
			
			(num_shift == 1)? (west)?EtoW_WtoE[gi][gj][3]:
							  (east)?EtoW_WtoE[gi][gj][1]:8'bz
			:(num_shift == 2)?(west)?(gj==TILE_DIM-1)?Ein_Win_2[8*gi+:8]:EtoW_WtoE[gi][gj+1][0]:
							  (east)?EtoW_WtoE[gi][gj][0]:8'bz
			:(num_shift >= 4)?(west)?(gj==TILE_DIM-num_shift/4)?Ein_Win_2[8*gi+:8]:EtoW_WtoE[gi][gj+num_shift/4][2]:
							  (east)?(gj==num_shift/4-1)?Ein_Win_2[8*gi+:8]:EtoW_WtoE[gi][gj-num_shift/4][2]:8'bz:8'bz,


			(num_shift == 1)? (north)?NtoS_StoN[gi][gj][3]:
							  (south)?NtoS_StoN[gi][gj][1]:8'bz
			:(num_shift == 2)?(north)?(gi==TILE_DIM-1)?Nin_Sin_2[8*gj+:8]:NtoS_StoN[gi+1][gj][0]:							  
							  (south)?NtoS_StoN[gi][gj][0]:8'bz
			:(num_shift >= 4)?(north)?(gj==TILE_DIM-num_shift/4)?Nin_Sin_2[8*gj+:8]:NtoS_StoN[gi+num_shift/4][gj][2]:
							  (south)?(gj==num_shift/4-1)?Nin_Sin_2[8*gj+:8]:NtoS_StoN[gi-num_shift/4][gj][0]:8'bz:8'bz,
									 
			
			(num_shift == 1)? (west)?(gj==TILE_DIM-1)?Ein_Win_3[8*gi+:8]:EtoW_WtoE[gi][gj+1][0]:
							  (east)?EtoW_WtoE[gi][gj][2]:8'bz
			:(num_shift == 2)?(west)?EtoW_WtoE[gi][gj][1]:
							  (east)?(gj==TILE_DIM-1)?Ein_Win_3[8*gi+:8]:EtoW_WtoE[gi][gj+1][1]:8'bz
			:(num_shift >= 4)?(west)?(gj==TILE_DIM-num_shift/4)?Ein_Win_3[8*gi+:8]:EtoW_WtoE[gi][gj+num_shift/4][3]:
							  (east)?(gj==num_shift/4-1)?Ein_Win_3[8*gi+:8]:EtoW_WtoE[gi][gj-num_shift/4][0]:8'bz:8'bz,


			(num_shift == 1)? (north)?(gj==TILE_DIM-1)?Nin_Sin_3[8*gj+:8]:NtoS_StoN[gi+1][gj][0]:
							  (south)?NtoS_StoN[gi][gj][2]:8'bz
			:(num_shift == 2)?(north)?(gj==TILE_DIM-1)?Nin_Sin_3[8*gj+:8]:NtoS_StoN[gi+1][gj][1]:
							  (south)?NtoS_StoN[gi][gj][1]:8'bz
			:(num_shift >= 4)?(north)?(gj==TILE_DIM-num_shift/4)?Nin_Sin_3[8*gj+:8]:NtoS_StoN[gi+num_shift/4][gj][3]:
							  (south)?(gj==num_shift/4-1)?Nin_Sin_3[8*gj+:8]:NtoS_StoN[gi-num_shift/4][gj][3]:8'bz:8'bz,
			
			
			EtoW_WtoE[gi][gj][0],
			NtoS_StoN[gi][gj][0],
			
			EtoW_WtoE[gi][gj][1],
			NtoS_StoN[gi][gj][1],
			
			EtoW_WtoE[gi][gj][2],
			NtoS_StoN[gi][gj][2],
			
			EtoW_WtoE[gi][gj][3],
			NtoS_StoN[gi][gj][3],
		
			num_shift
		
		);




		
		assign Eout_Wout_0[8*gi+:8] = (east)?EtoW_WtoE[gi][TILE_DIM-1][0]:(west)?EtoW_WtoE[gi][0][0]:8'bz;
		assign Nout_Sout_0[8*gj+:8] = (north)?NtoS_StoN[0][gj][0]:(south)?NtoS_StoN[TILE_DIM-1][gj][0]:8'bz;
		assign Eout_Wout_1[8*gi+:8] = (east)?EtoW_WtoE[gi][TILE_DIM-1][1]:(west)?EtoW_WtoE[gi][0][1]:8'bz;
		assign Nout_Sout_1[8*gj+:8] = (north)?NtoS_StoN[0][gj][1]:(south)?NtoS_StoN[TILE_DIM-1][gj][1]:8'bz;
		assign Eout_Wout_2[8*gi+:8] = (east)?EtoW_WtoE[gi][TILE_DIM-1][2]:(west)?EtoW_WtoE[gi][0][2]:8'bz;
		assign Nout_Sout_2[8*gj+:8] = (north)?NtoS_StoN[0][gj][2]:(south)?NtoS_StoN[TILE_DIM-1][gj][2]:8'bz;
		assign Eout_Wout_3[8*gi+:8] = (east)?EtoW_WtoE[gi][TILE_DIM-1][3]:(west)?EtoW_WtoE[gi][0][3]:8'bz;
		assign Nout_Sout_3[8*gj+:8] = (north)?NtoS_StoN[0][gj][3]:(south)?NtoS_StoN[TILE_DIM-1][gj][3]:8'bz;
		








		
		
		

	end
  end
  
endgenerate
endmodule