data/full_repos/permissive/494148647/src/memory/sdram/bench/sdram_tb.v
1: b'%Error: data/full_repos/permissive/494148647/src/memory/sdram/bench/sdram_tb.v:8: Cannot find include file: sdram.vh\n`include "sdram.vh" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/494148647/src/memory/sdram/bench,data/full_repos/permissive/494148647/sdram.vh\n             data/full_repos/permissive/494148647/src/memory/sdram/bench,data/full_repos/permissive/494148647/sdram.vh.v\n             data/full_repos/permissive/494148647/src/memory/sdram/bench,data/full_repos/permissive/494148647/sdram.vh.sv\n             sdram.vh\n             sdram.vh.v\n             sdram.vh.sv\n             obj_dir/sdram.vh\n             obj_dir/sdram.vh.v\n             obj_dir/sdram.vh.sv\n%Error: data/full_repos/permissive/494148647/src/memory/sdram/bench/sdram_tb.v:16: Define or directive not defined: \'`SDRAM_WIRE_DECLS\'\n    `SDRAM_WIRE_DECLS;\n    ^~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/494148647/src/memory/sdram/bench/sdram_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n        repeat(32) #5 clk = ~clk;\n                   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/494148647/src/memory/sdram/bench/sdram_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n        forever #5 clk = ~clk;\n                ^\n%Error: data/full_repos/permissive/494148647/src/memory/sdram/bench/sdram_tb.v:84: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("sdram_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/494148647/src/memory/sdram/bench/sdram_tb.v:85: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, sdram_tb);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/494148647/src/memory/sdram/bench/sdram_tb.v:88: syntax error, unexpected \'@\'\n        repeat(2) @(negedge leds[7]);\n                  ^\n%Error: Exiting due to 5 error(s), 2 warning(s)\n'
module sdram_tb();

    reg clk, rst;

    `SDRAM_WIRE_DECLS;

    wire [22:0] addr;
    wire rw;
    wire [31:0] data_in, data_out;
    wire busy;
    wire in_valid, out_valid;

    wire [7:0] leds;

    sdram DUT (
        .clk(clk),
        .rst(rst),
        .sdram_clk(sdram_clk),
        .sdram_cle(sdram_cle),
        .sdram_cs(sdram_cs),
        .sdram_cas(sdram_cas),
        .sdram_ras(sdram_ras),
        .sdram_we(sdram_we),
        .sdram_dqm(sdram_dqm),
        .sdram_ba(sdram_ba),
        .sdram_a(sdram_a),
        .sdram_dq(sdram_dq),
        .addr(addr),
        .rw(rw),
        .data_in(data_in),
        .data_out(data_out),
        .busy(busy),
        .in_valid(in_valid),
        .out_valid(out_valid)
    );

    mt48lc32m8a2 ram_model (
        .Dq(sdram_dq),
        .Addr(sdram_a),
        .Ba(sdram_ba),
        .Clk(sdram_clk),
        .Cke(sdram_cle),
        .Cs_n(sdram_cs),
        .Ras_n(sdram_ras),
        .Cas_n(sdram_cas),
        .We_n(sdram_we),
        .Dqm(sdram_dqm)
    );

    ram_test ram_test (
        .clk(clk),
        .rst(rst),
        .addr(addr),
        .rw(rw),
        .data_in(data_in),
        .data_out(data_out),
        .busy(busy),
        .in_valid(in_valid),
        .out_valid(out_valid),
        .leds(leds)
    );


    initial begin
        clk = 1'b0;
        rst = 1'b1;
        repeat(32) #5 clk = ~clk;
        rst = 1'b0;
        forever #5 clk = ~clk;
    end

    initial begin
        $dumpfile("sdram_tb.vcd");
        $dumpvars(0, sdram_tb);


        repeat(2) @(negedge leds[7]);
        $display("read errors: %h", leds[6:0]);
        $finish();
    end

endmodule
module sdram_tb();


    reg clk, rst;

    `SDRAM_WIRE_DECLS;

    wire [22:0] addr;
    wire rw;
    wire [31:0] data_in, data_out;
    wire busy;
    wire in_valid, out_valid;

    wire [7:0] leds;

    sdram DUT (
        .clk(clk),
        .rst(rst),
        .sdram_clk(sdram_clk),
        .sdram_cle(sdram_cle),
        .sdram_cs(sdram_cs),
        .sdram_cas(sdram_cas),
        .sdram_ras(sdram_ras),
        .sdram_we(sdram_we),
        .sdram_dqm(sdram_dqm),
        .sdram_ba(sdram_ba),
        .sdram_a(sdram_a),
        .sdram_dq(sdram_dq),
        .addr(addr),
        .rw(rw),
        .data_in(data_in),
        .data_out(data_out),
        .busy(busy),
        .in_valid(in_valid),
        .out_valid(out_valid)
    );

    mt48lc32m8a2 ram_model (
        .Dq(sdram_dq),
        .Addr(sdram_a),
        .Ba(sdram_ba),
        .Clk(sdram_clk),
        .Cke(sdram_cle),
        .Cs_n(sdram_cs),
        .Ras_n(sdram_ras),
        .Cas_n(sdram_cas),
        .We_n(sdram_we),
        .Dqm(sdram_dqm)
    );

    ram_test ram_test (
        .clk(clk),
        .rst(rst),
        .addr(addr),
        .rw(rw),
        .data_in(data_in),
        .data_out(data_out),
        .busy(busy),
        .in_valid(in_valid),
        .out_valid(out_valid),
        .leds(leds)
    );


    initial begin
        clk = 1'b0;
        rst = 1'b1;
        repeat(32) #5 clk = ~clk;
        rst = 1'b0;
        forever #5 clk = ~clk;
    end

    initial begin
        $dumpfile("sdram_tb.vcd");
        $dumpvars(0, sdram_tb);


        repeat(2) @(negedge leds[7]);
        $display("read errors: %h", leds[6:0]);
        $finish();
    end

endmodule