data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Finite State Machines/Fsm3onehot/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines/Fsm3onehot,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/Fsm3onehot/top_module.v\n%Error: Exiting due to 5 error(s)\n'
module top_module (
    input wire in,
    input wire [3:0] state,
    output wire [3:0] next_state,
    output wire out
);

  parameter A = 2'h0, B = 2'h1, C = 2'h2, D = 2'h3;


  assign next_state[A] = state[A] & ~in | state[C] & ~in;
  assign next_state[B] = state[A] & in | state[B] & in | state[D] & in;
  assign next_state[C] = state[B] & ~in | state[D] & ~in;
  assign next_state[D] = state[C] & in;


  assign out = state[D];
endmodule
module top_module (
    input wire in,
    input wire [3:0] state,
    output wire [3:0] next_state,
    output wire out
);


  parameter A = 2'h0, B = 2'h1, C = 2'h2, D = 2'h3;


  assign next_state[A] = state[A] & ~in | state[C] & ~in;
  assign next_state[B] = state[A] & in | state[B] & in | state[D] & in;
  assign next_state[C] = state[B] & ~in | state[D] & ~in;
  assign next_state[D] = state[C] & in;


  assign out = state[D];
endmodule