data/full_repos/permissive/527597746/CPU/CPU.srcs/sources_1/new/pc.v
data/verilator_xmls/0432921c-2813-450c-b4a7-7d7296ab271d.xml
module pc(
    input clk,
    input reset,
    input [31:0] next_addr,
    input pcwre,
    output reg [31:0] pc
    );
    always @(negedge reset, posedge clk)
    begin
        if(reset == 0) pc <= 0;
        else if(pcwre) pc <= next_addr;
    end
endmodule
module pc(
    input clk,
    input reset,
    input [31:0] next_addr,
    input pcwre,
    output reg [31:0] pc
    );

    always @(negedge reset, posedge clk)
    begin
        if(reset == 0) pc <= 0;
        else if(pcwre) pc <= next_addr;
    end
endmodule