data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/LEDInterface.v
1: b"%Error: data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/LEDInterface.v:38: Cannot find file containing module: 'SyzFETRegister3Out'\n  SyzFETRegister3Out ledReg(\n  ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new,data/full_repos/permissive/42815087/SyzFETRegister3Out\n             data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new,data/full_repos/permissive/42815087/SyzFETRegister3Out.v\n             data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new,data/full_repos/permissive/42815087/SyzFETRegister3Out.sv\n             SyzFETRegister3Out\n             SyzFETRegister3Out.v\n             SyzFETRegister3Out.sv\n             obj_dir/SyzFETRegister3Out\n             obj_dir/SyzFETRegister3Out.v\n             obj_dir/SyzFETRegister3Out.sv\n%Error: Exiting due to 1 error(s)\n"
module LEDInterface(
    input cpuClock,
    input periphSelect,
    input [15:0] dIn,
    input [3:0] regSelect,
    input readEn,
    input writeEn,
    input reset,
    input exec,
    output [15:0] dOut,
    output [15:0] ledsOut,
    output [15:0] debugOut
  );
  

  SyzFETRegister3Out ledReg(
    .dIn(dIn[15:0]),
    .clockSig(cpuClock),
    .read(readEn & periphSelect),
    .write(writeEn & periphSelect),
    .reset(reset),
    .dOut(dOut[15:0]),
    .dOut2(ledsOut[15:0]),
    .debugOut(debugOut[15:0])
  );
  
endmodule
module LEDInterface(
    input cpuClock,
    input periphSelect,
    input [15:0] dIn,
    input [3:0] regSelect,
    input readEn,
    input writeEn,
    input reset,
    input exec,
    output [15:0] dOut,
    output [15:0] ledsOut,
    output [15:0] debugOut
  );

  

  SyzFETRegister3Out ledReg(
    .dIn(dIn[15:0]),
    .clockSig(cpuClock),
    .read(readEn & periphSelect),
    .write(writeEn & periphSelect),
    .reset(reset),
    .dOut(dOut[15:0]),
    .dOut2(ledsOut[15:0]),
    .debugOut(debugOut[15:0])
  );
  
endmodule