data/full_repos/permissive/450962776/processor/src/control.v
1: b"%Error: data/full_repos/permissive/450962776/processor/src/control.v:4: Input/output/inout does not appear in port list: 'sum'\noutput sum, carry_out;\n       ^~~\n%Error: data/full_repos/permissive/450962776/processor/src/control.v:4: Input/output/inout does not appear in port list: 'carry_out'\noutput sum, carry_out;\n            ^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module control(Instruction,RegDst,Branch,MemRead,MemtoReg,ALUOp,MemWrite,ALUSrc,RegWrite);
input [3:0]Instruction;
output RegDst,Branch,MemRead,MemtoReg,ALUOp,MemWrite,ALUSrc,RegWrite;
output sum, carry_out;
endmodule
module control(Instruction,RegDst,Branch,MemRead,MemtoReg,ALUOp,MemWrite,ALUSrc,RegWrite);

input [3:0]Instruction;
output RegDst,Branch,MemRead,MemtoReg,ALUOp,MemWrite,ALUSrc,RegWrite;
output sum, carry_out;
endmodule