data/full_repos/permissive/419273451/lab1/codes/Pipeline_Registers.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/419273451/lab1/codes/Pipeline_Registers.v:38: Multiple top level modules\n                                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                          : ... Top module \'IF_ID_Registers\'\nmodule IF_ID_Registers\n       ^~~~~~~~~~~~~~~\n                                                                                          : ... Top module \'ID_EX_Registers\'\nmodule ID_EX_Registers\n       ^~~~~~~~~~~~~~~\n                                                                                          : ... Top module \'EX_MEM_Registers\'\nmodule EX_MEM_Registers\n       ^~~~~~~~~~~~~~~~\n                                                                                          : ... Top module \'MEM_WB_Registers\'\nmodule MEM_WB_Registers\n       ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module IF_ID_Registers
(
    clk_i,
    rst_i,
    Stall_i,
    Flush_i,
    pc_o_i,
    instruction_i,
    pc_o_o,
    instruction_o
);

input                   clk_i;
input                   rst_i;
input                   Stall_i;
input                   Flush_i;
input       [31:0]      pc_o_i;
input       [31:0]      instruction_i;
output reg  [31:0]      pc_o_o;
output reg  [31:0]      instruction_o;

always @ (posedge clk_i or posedge rst_i) begin
    if (rst_i) begin
        pc_o_o <= 32'b0;
        instruction_o <= 32'b0;
    end
    else if (Flush_i) begin
        instruction_o <= 32'b0;
    end
    else if (~Stall_i) begin
        pc_o_o <= pc_o_i;
        instruction_o <= instruction_i;
    end
end

endmodule
module IF_ID_Registers
(
    clk_i,
    rst_i,
    Stall_i,
    Flush_i,
    pc_o_i,
    instruction_i,
    pc_o_o,
    instruction_o
);


input                   clk_i;
input                   rst_i;
input                   Stall_i;
input                   Flush_i;
input       [31:0]      pc_o_i;
input       [31:0]      instruction_i;
output reg  [31:0]      pc_o_o;
output reg  [31:0]      instruction_o;

always @ (posedge clk_i or posedge rst_i) begin
    if (rst_i) begin
        pc_o_o <= 32'b0;
        instruction_o <= 32'b0;
    end
    else if (Flush_i) begin
        instruction_o <= 32'b0;
    end
    else if (~Stall_i) begin
        pc_o_o <= pc_o_i;
        instruction_o <= instruction_i;
    end
end

endmodule