data/full_repos/permissive/423547971/College Coursework/Advanced Computer Architecture Final Project/verilog CPU/bit_selector.v
1: b'%Error: Cannot find file containing module: Coursework/Advanced\n        ... Looked in:\n             data/full_repos/permissive/423547971/College/Coursework/Advanced\n             data/full_repos/permissive/423547971/College/Coursework/Advanced.v\n             data/full_repos/permissive/423547971/College/Coursework/Advanced.sv\n             Coursework/Advanced\n             Coursework/Advanced.v\n             Coursework/Advanced.sv\n             obj_dir/Coursework/Advanced\n             obj_dir/Coursework/Advanced.v\n             obj_dir/Coursework/Advanced.sv\n%Error: Cannot find file containing module: Computer\n%Error: Cannot find file containing module: Architecture\n%Error: Cannot find file containing module: Final\n%Error: Cannot find file containing module: Project/verilog\n%Error: Cannot find file containing module: CPU,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/College\n%Error: Cannot find file containing module: CPU/bit_selector.v\n%Error: Exiting due to 8 error(s)\n'
module bit_selector( y, shift_value );

  input      [15:0]	y;
  output reg [3:0]	shift_value;

always @*
  begin  
    output <= y[3:0];
  end

endmodule
module bit_selector( y, shift_value );


  input      [15:0]	y;
  output reg [3:0]	shift_value;

always @*
  begin  
    output <= y[3:0];
  end

endmodule