data/full_repos/permissive/410272426/hardware_code_radix-2/tf_address_generator.v
1: b'%Error: data/full_repos/permissive/410272426/hardware_code_radix-2/tf_address_generator.v:14: Cannot find file containing module: \'DFF\'\n    DFF #(.data_width(10)) dff_tf(.clk(clk),.rst(rst),.d(tf_address_tmp),.q(tf_address));\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/410272426/hardware_code_radix-2,data/full_repos/permissive/410272426/DFF\n             data/full_repos/permissive/410272426/hardware_code_radix-2,data/full_repos/permissive/410272426/DFF.v\n             data/full_repos/permissive/410272426/hardware_code_radix-2,data/full_repos/permissive/410272426/DFF.sv\n             DFF\n             DFF.v\n             DFF.sv\n             obj_dir/DFF\n             obj_dir/DFF.v\n             obj_dir/DFF.sv\n%Warning-WIDTH: data/full_repos/permissive/410272426/hardware_code_radix-2/tf_address_generator.v:19: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'k\' generates 9 bits.\n                                                                                                    : ... In instance tf_address_generator\n      9:begin tf_address_reg_0 = k; tf_address_reg_1 = k; end\n                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/410272426/hardware_code_radix-2/tf_address_generator.v:19: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'k\' generates 9 bits.\n                                                                                                    : ... In instance tf_address_generator\n      9:begin tf_address_reg_0 = k; tf_address_reg_1 = k; end\n                                                     ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module tf_address_generator(
    input clk,rst,
    input [2:0] conf,
    input [8:0] k,
    input [3:0] p,
    output wire [9:0] tf_address
    );
    
    reg [9:0] tf_address_reg_0,tf_address_reg_1;
    wire [9:0] tf_address_tmp;

    assign tf_address_tmp = ((conf == 3'b001) || (conf == 3'b100)) ? tf_address_reg_0 : tf_address_reg_1;
    
    DFF #(.data_width(10)) dff_tf(.clk(clk),.rst(rst),.d(tf_address_tmp),.q(tf_address));
    
    always@(*)
    begin
      case(p)
      9:begin tf_address_reg_0 = k; tf_address_reg_1 = k; end
      8:begin tf_address_reg_0 = k + 1; tf_address_reg_1 = 2 - k; end
      7:begin tf_address_reg_0 = k + 3; tf_address_reg_1 = 6 - k ; end
      6:begin tf_address_reg_0 = k + 7; tf_address_reg_1 = 14 - k; end
      5:begin tf_address_reg_0 = k + 15; tf_address_reg_1 = 30 - k; end
      4:begin tf_address_reg_0 = k + 31; tf_address_reg_1 = 62 - k; end
      3:begin tf_address_reg_0 = k + 63; tf_address_reg_1 = 126 - k; end
      2:begin tf_address_reg_0 = k + 127; tf_address_reg_1 = 254 - k; end
      1:begin tf_address_reg_0 = k + 255; tf_address_reg_1 = 510 - k; end
      0:begin tf_address_reg_0 = k + 511; tf_address_reg_1 = 1022 - k; end
      default:begin tf_address_reg_0 = 0; tf_address_reg_1 = 0; end
      endcase
    end
endmodule
module tf_address_generator(
    input clk,rst,
    input [2:0] conf,
    input [8:0] k,
    input [3:0] p,
    output wire [9:0] tf_address
    );

    
    reg [9:0] tf_address_reg_0,tf_address_reg_1;
    wire [9:0] tf_address_tmp;

    assign tf_address_tmp = ((conf == 3'b001) || (conf == 3'b100)) ? tf_address_reg_0 : tf_address_reg_1;
    
    DFF #(.data_width(10)) dff_tf(.clk(clk),.rst(rst),.d(tf_address_tmp),.q(tf_address));
    
    always@(*)
    begin
      case(p)
      9:begin tf_address_reg_0 = k; tf_address_reg_1 = k; end
      8:begin tf_address_reg_0 = k + 1; tf_address_reg_1 = 2 - k; end
      7:begin tf_address_reg_0 = k + 3; tf_address_reg_1 = 6 - k ; end
      6:begin tf_address_reg_0 = k + 7; tf_address_reg_1 = 14 - k; end
      5:begin tf_address_reg_0 = k + 15; tf_address_reg_1 = 30 - k; end
      4:begin tf_address_reg_0 = k + 31; tf_address_reg_1 = 62 - k; end
      3:begin tf_address_reg_0 = k + 63; tf_address_reg_1 = 126 - k; end
      2:begin tf_address_reg_0 = k + 127; tf_address_reg_1 = 254 - k; end
      1:begin tf_address_reg_0 = k + 255; tf_address_reg_1 = 510 - k; end
      0:begin tf_address_reg_0 = k + 511; tf_address_reg_1 = 1022 - k; end
      default:begin tf_address_reg_0 = 0; tf_address_reg_1 = 0; end
      endcase
    end
endmodule