data/full_repos/permissive/450922687/Task 2/Forwarding_Unit.v
1: b'%Error: Cannot find file containing module: 2,data/full_repos/permissive/450922687\n        ... Looked in:\n             data/full_repos/permissive/450922687/Task/2,data/full_repos/permissive/450922687\n             data/full_repos/permissive/450922687/Task/2,data/full_repos/permissive/450922687.v\n             data/full_repos/permissive/450922687/Task/2,data/full_repos/permissive/450922687.sv\n             2,data/full_repos/permissive/450922687\n             2,data/full_repos/permissive/450922687.v\n             2,data/full_repos/permissive/450922687.sv\n             obj_dir/2,data/full_repos/permissive/450922687\n             obj_dir/2,data/full_repos/permissive/450922687.v\n             obj_dir/2,data/full_repos/permissive/450922687.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/450922687/Task\n%Error: Cannot find file containing module: 2/Forwarding_Unit.v\n%Error: Exiting due to 3 error(s)\n'
module forwarding_Unit(
    input [4:0] ID_EX_rs1, ID_EX_rs2,
	input [4:0] EX_MEM_rd,
	input EX_MEM_RegWrite,
	input [4:0] MEM_WB_rd,
	input MEM_WB_RegWrite,
  output reg [1:0] forward_A, forward_B

);
  always @(*)
      begin




        if (EX_MEM_rd != 0 && EX_MEM_RegWrite == 1 && EX_MEM_rd == ID_EX_rs1)
            forward_A = 2'b10;
        
		else if (MEM_WB_RegWrite == 1 && MEM_WB_rd != 0 && MEM_WB_rd == ID_EX_rs1 && !(EX_MEM_RegWrite == 1 && EX_MEM_rd == ID_EX_rs1 && EX_MEM_rd != 0))
			forward_A = 2'b01;
        
		else
			forward_A = 2'b00;
		

        if (EX_MEM_rd != 0 && EX_MEM_RegWrite == 1 && EX_MEM_rd == ID_EX_rs2)
            forward_B = 2'b10;
        
        else if (MEM_WB_RegWrite == 1 && MEM_WB_rd != 0 && MEM_WB_rd == ID_EX_rs2 && !(EX_MEM_RegWrite == 1 && EX_MEM_rd == ID_EX_rs2 && EX_MEM_rd != 0))
        	forward_B = 2'b01;
        
        else 
            forward_B = 2'b00;
        
      end
endmodule
module forwarding_Unit(
    input [4:0] ID_EX_rs1, ID_EX_rs2,
	input [4:0] EX_MEM_rd,
	input EX_MEM_RegWrite,
	input [4:0] MEM_WB_rd,
	input MEM_WB_RegWrite,
  output reg [1:0] forward_A, forward_B

);

  always @(*)
      begin




        if (EX_MEM_rd != 0 && EX_MEM_RegWrite == 1 && EX_MEM_rd == ID_EX_rs1)
            forward_A = 2'b10;
        
		else if (MEM_WB_RegWrite == 1 && MEM_WB_rd != 0 && MEM_WB_rd == ID_EX_rs1 && !(EX_MEM_RegWrite == 1 && EX_MEM_rd == ID_EX_rs1 && EX_MEM_rd != 0))
			forward_A = 2'b01;
        
		else
			forward_A = 2'b00;
		

        if (EX_MEM_rd != 0 && EX_MEM_RegWrite == 1 && EX_MEM_rd == ID_EX_rs2)
            forward_B = 2'b10;
        
        else if (MEM_WB_RegWrite == 1 && MEM_WB_rd != 0 && MEM_WB_rd == ID_EX_rs2 && !(EX_MEM_RegWrite == 1 && EX_MEM_rd == ID_EX_rs2 && EX_MEM_rd != 0))
        	forward_B = 2'b01;
        
        else 
            forward_B = 2'b00;
        
      end
endmodule