data/full_repos/permissive/515624136/rtl/INS_MEM.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/515624136/rtl/INS_MEM.sv:122: Bit extraction of array[255:0] requires 8 bit index, not 10 bits.\n                                                                       : ... In instance INS_MEM\n  Ram_Array[Shift_Addr]<=INS_MEM_Data_In;\n           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/515624136/rtl/INS_MEM.sv:126: Bit extraction of array[255:0] requires 8 bit index, not 10 bits.\n                                                                       : ... In instance INS_MEM\n  INS_MEM_Data_Out<=Ram_Array[Shift_Addr];\n                             ^\n%Error: Exiting due to 2 warning(s)\n'
module INS_MEM #(parameter ADDR_WIDTH = 10, BINPATH="")
(

INS_MEM_Clk,
INS_MEM_Re,
INS_MEM_We,
INS_MEM_Address, 
INS_MEM_Data_In,


INS_MEM_Data_Out,
INS_MEM_Read_Valid,
INS_MEM_Write_Ready

);





input INS_MEM_Clk;
input INS_MEM_Re;
input INS_MEM_We;
input [ADDR_WIDTH-1:0] INS_MEM_Address;
input [31:0] INS_MEM_Data_In;
output reg [31:0] INS_MEM_Data_Out;
output INS_MEM_Read_Valid;
output INS_MEM_Write_Ready;





reg [31:0] Ram_Array[0:(2**(ADDR_WIDTH-2))-1];
wire [ADDR_WIDTH-1:0] Shift_Addr;
reg [31:0] reg32_data;
reg read_valid = 1'b0;
reg write_ready = 1'b0;






integer File_ID;


function void load_ram(integer file);
	
	integer Status;
	
	Status  = $fread(reg32_data,file);
	for(integer i=0; Status ==4; i=i+1)
	begin	

		Ram_Array[i]=((reg32_data&32'h000000ff) << 24) + ((reg32_data&32'h0000ff00) << 8) + ((reg32_data&32'h00ff0000) >> 8) + ((reg32_data&32'hff000000) >> 24);
		Status  = $fread(reg32_data,File_ID);
	end

	$fclose(file);

endfunction


initial
begin
	$display("Loading Instruction Memory...");
	File_ID = $fopen(BINPATH, "rb");
	load_ram(File_ID);
	$display("Ram successfully loaded.");
end



always@(INS_MEM_Re,INS_MEM_We)
begin
	
	if(INS_MEM_Re)
		read_valid=1'b1;
	else
		read_valid=1'b0;
		
	
	if(INS_MEM_We)
		write_ready=1'b1;
	else
		write_ready=1'b0;

end






always@(posedge INS_MEM_Clk)
begin
	
	if(INS_MEM_We&write_ready) begin
		Ram_Array[Shift_Addr]<=INS_MEM_Data_In;
	end
	
	if(INS_MEM_Re&read_valid) begin
		INS_MEM_Data_Out<=Ram_Array[Shift_Addr];
	end
	
	else begin
		INS_MEM_Data_Out<=32'b0;
	end
	
end


assign Shift_Addr=INS_MEM_Address>>2;
assign INS_MEM_Read_Valid=read_valid;
assign INS_MEM_Write_Ready=write_ready;




endmodule
module INS_MEM #(parameter ADDR_WIDTH = 10, BINPATH="")
(

INS_MEM_Clk,
INS_MEM_Re,
INS_MEM_We,
INS_MEM_Address, 
INS_MEM_Data_In,


INS_MEM_Data_Out,
INS_MEM_Read_Valid,
INS_MEM_Write_Ready

);






input INS_MEM_Clk;
input INS_MEM_Re;
input INS_MEM_We;
input [ADDR_WIDTH-1:0] INS_MEM_Address;
input [31:0] INS_MEM_Data_In;
output reg [31:0] INS_MEM_Data_Out;
output INS_MEM_Read_Valid;
output INS_MEM_Write_Ready;





reg [31:0] Ram_Array[0:(2**(ADDR_WIDTH-2))-1];
wire [ADDR_WIDTH-1:0] Shift_Addr;
reg [31:0] reg32_data;
reg read_valid = 1'b0;
reg write_ready = 1'b0;






integer File_ID;


function void load_ram(integer file);
	
	integer Status;
	
	Status  = $fread(reg32_data,file);
	for(integer i=0; Status ==4; i=i+1)
	begin	

		Ram_Array[i]=((reg32_data&32'h000000ff) << 24) + ((reg32_data&32'h0000ff00) << 8) + ((reg32_data&32'h00ff0000) >> 8) + ((reg32_data&32'hff000000) >> 24);
		Status  = $fread(reg32_data,File_ID);
	end

	$fclose(file);

endfunction


initial
begin
	$display("Loading Instruction Memory...");
	File_ID = $fopen(BINPATH, "rb");
	load_ram(File_ID);
	$display("Ram successfully loaded.");
end



always@(INS_MEM_Re,INS_MEM_We)
begin
	
	if(INS_MEM_Re)
		read_valid=1'b1;
	else
		read_valid=1'b0;
		
	
	if(INS_MEM_We)
		write_ready=1'b1;
	else
		write_ready=1'b0;

end






always@(posedge INS_MEM_Clk)
begin
	
	if(INS_MEM_We&write_ready) begin
		Ram_Array[Shift_Addr]<=INS_MEM_Data_In;
	end
	
	if(INS_MEM_Re&read_valid) begin
		INS_MEM_Data_Out<=Ram_Array[Shift_Addr];
	end
	
	else begin
		INS_MEM_Data_Out<=32'b0;
	end
	
end


assign Shift_Addr=INS_MEM_Address>>2;
assign INS_MEM_Read_Valid=read_valid;
assign INS_MEM_Write_Ready=write_ready;




endmodule