data/full_repos/permissive/456099881/top.v
1: b'%Error: data/full_repos/permissive/456099881/top.v:8: Cannot find file containing module: \'OSCH\'\n    OSCH #(.NOM_FREQ("133.00")) rc_oscillator(.STDBY(1\'b0), .OSC(fpga_clock));\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/456099881,data/full_repos/permissive/456099881/OSCH\n             data/full_repos/permissive/456099881,data/full_repos/permissive/456099881/OSCH.v\n             data/full_repos/permissive/456099881,data/full_repos/permissive/456099881/OSCH.sv\n             OSCH\n             OSCH.v\n             OSCH.sv\n             obj_dir/OSCH\n             obj_dir/OSCH.v\n             obj_dir/OSCH.sv\n%Error: Exiting due to 1 error(s)\n'
module slow_counter(clock,enable,output_byte);

input wire clock;
input wire enable;
output reg [7:0] output_byte;

  reg [31:0] counter;
  reg [3:0] BCD;
  reg[7:0] SevenSeg;
initial
begin
	output_byte = 8'b00000000;
	counter = 32'b0;
	end
    
  
  always @(posedge clock) 
   begin
	   if(enable == 1'b1)
		   begin
			   counter<=counter+1'b1;
			   output_byte <=~counter[31:24];
			end  	   
	end
endmodule
module slow_counter(clock,enable,output_byte);


input wire clock;
input wire enable;
output reg [7:0] output_byte;

  reg [31:0] counter;
  reg [3:0] BCD;
  reg[7:0] SevenSeg;
initial
begin
	output_byte = 8'b00000000;
	counter = 32'b0;
	end
    
  
  always @(posedge clock) 
   begin
	   if(enable == 1'b1)
		   begin
			   counter<=counter+1'b1;
			   output_byte <=~counter[31:24];
			end  	   
	end
endmodule