data/full_repos/permissive/493019833/test/testcase/firrtl/SimpleIOModule/reference/SimpleIOModule.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/SimpleIOModule/reference/SimpleIOModule.v:575: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 8 bits.\n                                                                                                                       : ... In instance SimpleIOModule.u_pad_8\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/SimpleIOModule/reference/SimpleIOModule.v:568: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 12 bits.\n                                                                                                                       : ... In instance SimpleIOModule.s_pad_5\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/SimpleIOModule/reference/SimpleIOModule.v:568: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 8 bits.\n                                                                                                                       : ... In instance SimpleIOModule.s_pad_7\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/SimpleIOModule/reference/SimpleIOModule.v:561: Operator COND expects 12 bits on the Conditional False, but Conditional False\'s SEL generates 1 bits.\n                                                                                                                       : ... In instance SimpleIOModule.s_shr_3\n    assign y = n < width ? in[width-1:n] : in[width-1:width-1];\n                         ^\n%Error: Exiting due to 4 warning(s)\n'
module BITS(y, in);
    parameter width = 4;
    parameter high = 2;
    parameter low = 0;
    output [high-low:0] y;
    input [width-1:0] in;
    assign y = in[high:low];
endmodule
module BITS(y, in);

    parameter width = 4;
    parameter high = 2;
    parameter low = 0;
    output [high-low:0] y;
    input [width-1:0] in;
    assign y = in[high:low];
endmodule