data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_dpopt/bdw_work/modules/dut/BASIC/v_rtl/dut_Mul_20Ux10U_29U_4.v
data/verilator_xmls/df212174-c20f-4fae-af41-20567ad9df16.xml
module dut_Mul_20Ux10U_29U_4 (
	in2,
	in1,
	out1
	);
input [19:0] in2;
input [9:0] in1;
output [28:0] out1;
wire [28:0] asc001;

assign asc001 = 
	+(in2 * in1);

assign out1 = asc001;
endmodule
module dut_Mul_20Ux10U_29U_4 (
	in2,
	in1,
	out1
	);

input [19:0] in2;
input [9:0] in1;
output [28:0] out1;
wire [28:0] asc001;

assign asc001 = 
	+(in2 * in1);

assign out1 = asc001;
endmodule