data/full_repos/permissive/489075769/write_response_ms.v
1: b'%Warning-WIDTH: data/full_repos/permissive/489075769/write_response_ms.v:56: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                           : ... In instance write_response_ms.resp_s\no_BRESP <= 1\'b0;\n        ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module write_response_slave(ACLK, ARESETn,i_BVALID, o_BVALID, BREADY, i_BRESP, o_BRESP);
input ACLK, ARESETn;
input i_BVALID, BREADY;
input [1:0] i_BRESP;
	
output reg o_BVALID;
output reg [1:0] o_BRESP;
	        	
	

always @(posedge ACLK) begin
o_BVALID <= i_BVALID;
if(ARESETn)
begin
o_BVALID <= 1'b0;
o_BRESP <= 1'b0;
end
else if(BREADY && o_BVALID)
o_BRESP <= i_BRESP;
else 
o_BRESP <= 2'b0;

end

endmodule
module write_response_slave(ACLK, ARESETn,i_BVALID, o_BVALID, BREADY, i_BRESP, o_BRESP);

input ACLK, ARESETn;
input i_BVALID, BREADY;
input [1:0] i_BRESP;
	
output reg o_BVALID;
output reg [1:0] o_BRESP;
	        	
	

always @(posedge ACLK) begin
o_BVALID <= i_BVALID;
if(ARESETn)
begin
o_BVALID <= 1'b0;
o_BRESP <= 1'b0;
end
else if(BREADY && o_BVALID)
o_BRESP <= i_BRESP;
else 
o_BRESP <= 2'b0;

end

endmodule