data/full_repos/permissive/42434302/ivltests/pr2470181b.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr2470181b.v:7: Unsupported: Ignoring delay on this delayed statement.\n    #2;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/42434302/ivltests/pr2470181b.v:12: syntax error, unexpected \';\', expecting IDENTIFIER\n    input bit;\n             ^\n%Error: data/full_repos/permissive/42434302/ivltests/pr2470181b.v:15: syntax error, unexpected \';\', expecting "\'{"\n      a = bit;\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr2470181b.v:16: Unsupported: Ignoring delay on this delayed statement.\n      #1 if (a !== b) begin\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr2470181b.v:20: Unsupported: Ignoring delay on this delayed statement.\n      #2 if (b !== 1\'b0) begin\n      ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module main;
  reg pass;
  reg a, b;

  always @* begin
    b = a;
    #2;
    b = 1'b0;
  end

  task check_bit;
    input bit;

    begin
      a = bit;
      #1 if (a !== b) begin
        $display("FAILED, expected %b, got %b", a, b);
        pass = 1'b0;
      end
      #2 if (b !== 1'b0) begin
        $display("FAILED return to zero, got %b", b);
        pass = 1'b0;
      end
    end
  endtask

  initial begin
    pass = 1'b1;

    check_bit(1'b1);
    check_bit(1'b0);
    check_bit(1'bx);
    check_bit(1'bz);

    if (pass) $display("PASSED");
  end

endmodule
module main;

  reg pass;
  reg a, b;

  always @* begin
    b = a;
    #2;
    b = 1'b0;
  end

  task check_bit;
    input bit;

    begin
      a = bit;
      #1 if (a !== b) begin
        $display("FAILED, expected %b, got %b", a, b);
        pass = 1'b0;
      end
      #2 if (b !== 1'b0) begin
        $display("FAILED return to zero, got %b", b);
        pass = 1'b0;
      end
    end
  endtask

  initial begin
    pass = 1'b1;

    check_bit(1'b1);
    check_bit(1'b0);
    check_bit(1'bx);
    check_bit(1'bz);

    if (pass) $display("PASSED");
  end

endmodule