data/full_repos/permissive/415491487/design_src/decode.v
data/verilator_xmls/d6b67c5d-2a29-4132-a363-8e0d776cdc6c.xml
module decodeunit(
    input clk,
    input rst,
    input [23:0] instr,
    
    output reg valid,
    output reg conditional,
    
    output reg lit_mv,
    output reg [6:0] src,
    output reg [6:0] dest,
    
    output reg hl,
    output reg [11:0] lit
);

    parameter ireg = 1'b0;
    parameter iimm = 1'b1;

    parameter invalid_instr = 1'b0;
    parameter valid_instr = 1'b1;

    parameter literal = 1'b1;
    parameter move = 1'b0;
    
    wire intop;
    assign intop = instr[23];
    
    always @(negedge clk) begin
        conditional <= instr[22];
        dest <= instr[18:12];
        case (intop)
            ireg: begin
                src <= instr[11:5];
                lit_mv <= move;
                valid <= valid_instr;
            end
            iimm: begin
                hl <= instr[21];
                lit <= instr[11:0];
                lit_mv <= literal;
                valid <= valid_instr;
            end
            default: begin
                valid <= invalid_instr;
            end
        endcase
    end
    
    always @(posedge rst) begin
        valid <= invalid_instr;
    end
    
endmodule
module decodeunit(
    input clk,
    input rst,
    input [23:0] instr,
    
    output reg valid,
    output reg conditional,
    
    output reg lit_mv,
    output reg [6:0] src,
    output reg [6:0] dest,
    
    output reg hl,
    output reg [11:0] lit
);


    parameter ireg = 1'b0;
    parameter iimm = 1'b1;

    parameter invalid_instr = 1'b0;
    parameter valid_instr = 1'b1;

    parameter literal = 1'b1;
    parameter move = 1'b0;
    
    wire intop;
    assign intop = instr[23];
    
    always @(negedge clk) begin
        conditional <= instr[22];
        dest <= instr[18:12];
        case (intop)
            ireg: begin
                src <= instr[11:5];
                lit_mv <= move;
                valid <= valid_instr;
            end
            iimm: begin
                hl <= instr[21];
                lit <= instr[11:0];
                lit_mv <= literal;
                valid <= valid_instr;
            end
            default: begin
                valid <= invalid_instr;
            end
        endcase
    end
    
    always @(posedge rst) begin
        valid <= invalid_instr;
    end
    
endmodule