data/full_repos/permissive/528831163/tb/boron_enc_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/528831163/tb/boron_enc_tb.v:5: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/528831163/tb/boron_enc_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Error: data/full_repos/permissive/528831163/tb/boron_enc_tb.v:13: Cannot find file containing module: \'boron_enc\'\n    boron_enc be(.clk(clk), .rst(rst), .start(start), .plain_text(plain_text), \n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/528831163/tb,data/full_repos/permissive/528831163/boron_enc\n             data/full_repos/permissive/528831163/tb,data/full_repos/permissive/528831163/boron_enc.v\n             data/full_repos/permissive/528831163/tb,data/full_repos/permissive/528831163/boron_enc.sv\n             boron_enc\n             boron_enc.v\n             boron_enc.sv\n             obj_dir/boron_enc\n             obj_dir/boron_enc.v\n             obj_dir/boron_enc.sv\n%Error: data/full_repos/permissive/528831163/tb/boron_enc_tb.v:16: Cannot find file containing module: \'dec_add_round_key\'\n    dec_add_round_key dark(.i_ark_cipher(cipher_text), .i_ark_key(be.reg_key), .o_ark_msg(desired_text));\n    ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module boron_enc_tb ();
     reg clk, rst, start;

    always begin
        #5 clk = ~clk;
    end
    reg [63:0] plain_text;
    reg [79:0] master_key;
    wire [63:0] cipher_text;
    wire  [63:0] desired_text;
    wire done;
    
    boron_enc be(.clk(clk), .rst(rst), .start(start), .plain_text(plain_text), 
    .master_key(master_key), .done(done), .cipher_text(cipher_text));

    dec_add_round_key dark(.i_ark_cipher(cipher_text), .i_ark_key(be.reg_key), .o_ark_msg(desired_text));
    initial begin
        clk = 0;
        plain_text = 64'd0;
        master_key = 80'h00000000000000000000;

        rst = 0;
        #20;
        rst = 1;
        start = 1'b1;

        
        
    end

endmodule
module boron_enc_tb ();

     reg clk, rst, start;

    always begin
        #5 clk = ~clk;
    end
    reg [63:0] plain_text;
    reg [79:0] master_key;
    wire [63:0] cipher_text;
    wire  [63:0] desired_text;
    wire done;
    
    boron_enc be(.clk(clk), .rst(rst), .start(start), .plain_text(plain_text), 
    .master_key(master_key), .done(done), .cipher_text(cipher_text));

    dec_add_round_key dark(.i_ark_cipher(cipher_text), .i_ark_key(be.reg_key), .o_ark_msg(desired_text));
    initial begin
        clk = 0;
        plain_text = 64'd0;
        master_key = 80'h00000000000000000000;

        rst = 0;
        #20;
        rst = 1;
        start = 1'b1;

        
        
    end

endmodule