data/full_repos/permissive/51494710/Hardware/Perceptron_xor/unchatter.sv
data/verilator_xmls/11988534-6c8d-46b2-9666-f297bb9aa10a.xml
module unchatter(
  input	iCLK,
  input	iDATA,
  output	oDATA
);

  reg	[15:0]	cnt;
  reg				dff;

  always @(posedge iCLK) begin
    cnt <= cnt + 1;
  end
	
  always @(posedge cnt[15]) begin
    dff <= iDATA;
  end
	
  assign oDATA = dff;
	
endmodule
module unchatter(
  input	iCLK,
  input	iDATA,
  output	oDATA
);


  reg	[15:0]	cnt;
  reg				dff;

  always @(posedge iCLK) begin
    cnt <= cnt + 1;
  end
	
  always @(posedge cnt[15]) begin
    dff <= iDATA;
  end
	
  assign oDATA = dff;
	
endmodule