data/full_repos/permissive/439731184/adder_implicit.v
1: b'%Error: data/full_repos/permissive/439731184/adder_implicit.v:1: Cannot find include file: addbit.v\n`include "addbit.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/439731184,data/full_repos/permissive/439731184/addbit.v\n             data/full_repos/permissive/439731184,data/full_repos/permissive/439731184/addbit.v.v\n             data/full_repos/permissive/439731184,data/full_repos/permissive/439731184/addbit.v.sv\n             addbit.v\n             addbit.v.v\n             addbit.v.sv\n             obj_dir/addbit.v\n             obj_dir/addbit.v.v\n             obj_dir/addbit.v.sv\n%Error: Exiting due to 1 error(s)\n'
module adder_implicit( result, carry, r1, r2, ci );


input [3:0] r1;
input [3:0] r2;
input ci;


output [3:0] result;
output carry;


wire [3:0] r1;
wire [3:0] r2;
wire ci;
wire [3:0] result;
wire carry;


wire [1:0] c; 

addbit u0 ( r1[0], r2[0], ci, result[0], c[0] );
addbit u1 ( r1[1], r2[1], c[0], result[1], c[1] );
addbit u2 ( r1[2], r2[2], c[1], result[2], carry );

endmodule
module adder_implicit( result, carry, r1, r2, ci );



input [3:0] r1;
input [3:0] r2;
input ci;


output [3:0] result;
output carry;


wire [3:0] r1;
wire [3:0] r2;
wire ci;
wire [3:0] result;
wire carry;


wire [1:0] c; 

addbit u0 ( r1[0], r2[0], ci, result[0], c[0] );
addbit u1 ( r1[1], r2[1], c[0], result[1], c[1] );
addbit u2 ( r1[2], r2[2], c[1], result[2], carry );

endmodule