data/full_repos/permissive/449071180/tb_row_converter.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_row_converter.v:32: Unsupported: Ignoring delay on this delayed statement.\n   #5;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_row_converter.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #5;\n  ^\n%Error: data/full_repos/permissive/449071180/tb_row_converter.v:13: Cannot find file containing module: \'row_converter\'\nrow_converter port_map(\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/row_converter\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/row_converter.v\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/row_converter.sv\n             row_converter\n             row_converter.v\n             row_converter.sv\n             obj_dir/row_converter\n             obj_dir/row_converter.v\n             obj_dir/row_converter.sv\n%Warning-WIDTH: data/full_repos/permissive/449071180/tb_row_converter.v:29: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'count1\' generates 32 bits.\n                                                                          : ... In instance tb_row_converter\n  coordinate_y_test = count1;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/449071180/tb_row_converter.v:31: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'count2\' generates 32 bits.\n                                                                          : ... In instance tb_row_converter\n   coordinate_x_test = count2;\n                     ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_row_converter();

reg [2:0] coordinate_y_test;

reg [2:0] coordinate_x_test;

wire [7:0] row1_test,row2_test,row3_test,row4_test,row5_test,row6_test,row7_test,row8_test;

integer count1;
integer count2;


row_converter port_map(
.coordinate_y(coordinate_y_test),
.coordinate_x(coordinate_x_test),
.row1(row1_test),
.row2(row2_test),
.row3(row3_test),
.row4(row4_test),
.row5(row5_test),
.row6(row6_test),
.row7(row7_test),
.row8(row8_test)

);

always begin
for (count1 = 0; count1 < 8; count1 = count1 + 1) begin
		coordinate_y_test = count1;
		for (count2 = 0; count2 < 8; count2 = count2 + 1) begin
			coordinate_x_test = count2;
			#5;
		end
		#5;
end

end



endmodule
module tb_row_converter();


reg [2:0] coordinate_y_test;

reg [2:0] coordinate_x_test;

wire [7:0] row1_test,row2_test,row3_test,row4_test,row5_test,row6_test,row7_test,row8_test;

integer count1;
integer count2;


row_converter port_map(
.coordinate_y(coordinate_y_test),
.coordinate_x(coordinate_x_test),
.row1(row1_test),
.row2(row2_test),
.row3(row3_test),
.row4(row4_test),
.row5(row5_test),
.row6(row6_test),
.row7(row7_test),
.row8(row8_test)

);

always begin
for (count1 = 0; count1 < 8; count1 = count1 + 1) begin
		coordinate_y_test = count1;
		for (count2 = 0; count2 < 8; count2 = count2 + 1) begin
			coordinate_x_test = count2;
			#5;
		end
		#5;
end

end



endmodule