data/full_repos/permissive/481623724/hw/cores/common/bsv.vivado/FIFO18E2_WRAPPER.v
1: b"%Error: data/full_repos/permissive/481623724/hw/cores/common/bsv.vivado/FIFO18E2_WRAPPER.v:65: Cannot find file containing module: 'FIFO18E2'\n  FIFO18E2\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/481623724/hw/cores/common/bsv.vivado,data/full_repos/permissive/481623724/FIFO18E2\n             data/full_repos/permissive/481623724/hw/cores/common/bsv.vivado,data/full_repos/permissive/481623724/FIFO18E2.v\n             data/full_repos/permissive/481623724/hw/cores/common/bsv.vivado,data/full_repos/permissive/481623724/FIFO18E2.sv\n             FIFO18E2\n             FIFO18E2.v\n             FIFO18E2.sv\n             obj_dir/FIFO18E2\n             obj_dir/FIFO18E2.v\n             obj_dir/FIFO18E2.sv\n%Error: Exiting due to 1 error(s)\n"
module FIFO18E2_WRAPPER
#(
  parameter CASCADE_ORDER = "NONE",
  parameter CLOCK_DOMAINS = "COMMON",
  parameter FIRST_WORD_FALL_THROUGH = "TRUE",
  parameter REGISTER_MODE = "REGISTERED",
  parameter integer W = 32
 )
 (
  output [W-1:0] CASDOUT,
  output         CASNXTEMPTY,
  output         CASPRVRDEN,
  output [W-1:0] DOUT,
  output         EMPTY_N,
  output         FULL_N,
  output         RDRSTBUSY,
  output         WRRSTBUSY,

  input [W-1:0]  CASDIN,
  input          CASNXTRDEN,
  input          CASPRVEMPTY,
  input          CLR,
  input [W-1:0]  DIN,
  input          RDCLK,
  input          RDEN,
  input          RST_N,
  input          WRCLK,
  input          WREN

  );

  wire          EMPTY;
  wire          FULL;



  wire          resetn = ~(~RST_N || CLR);

  wire [31:0]   CASDOUT32;
  wire [3:0]    CASDOUTP;

  wire [31:0]   DOUT32;
  wire [3:0]    DOUTP;

  wire [31:0]   CASDIN32;
  wire [3:0]    CASDINP;

  wire [31:0]   DIN32;
  wire [3:0]    DINP;

  localparam WIDTH = (W <= 4) ? 4 : ((W <= 9) ? 9 : ((W <= 18) ? 18 : 36));




  FIFO18E2
  #(
    .CASCADE_ORDER           (CASCADE_ORDER),
    .CLOCK_DOMAINS           (CLOCK_DOMAINS),
    .FIRST_WORD_FALL_THROUGH (FIRST_WORD_FALL_THROUGH),
    .INIT                    (36'h000000000),
    .PROG_EMPTY_THRESH       (256),
    .PROG_FULL_THRESH        (256),

    .IS_RDCLK_INVERTED       (1'b0),
    .IS_RDEN_INVERTED        (1'b0),
    .IS_RSTREG_INVERTED      (1'b0),
    .IS_RST_INVERTED         (1'b1),
    .IS_WRCLK_INVERTED       (1'b0),
    .IS_WREN_INVERTED        (1'b0),
    .RDCOUNT_TYPE            ("EXTENDED_DATACOUNT"),
    .READ_WIDTH              (WIDTH),
    .REGISTER_MODE           (REGISTER_MODE),
    .RSTREG_PRIORITY         ("RSTREG"),
    .SLEEP_ASYNC             ("FALSE"),
    .SRVAL                   (36'h000000000),
    .WRCOUNT_TYPE            ("EXTENDED_DATACOUNT"),
    .WRITE_WIDTH             (WIDTH)
  ) FIFO18E2_i
   (

    .CASDOUT        (CASDOUT32),
    .CASDOUTP       (CASDOUTP),
    .CASNXTEMPTY    (CASNXTEMPTY),
    .CASPRVRDEN     (CASPRVRDEN),

    .DOUT           (DOUT32),
    .DOUTP          (DOUTP),

    .EMPTY          (EMPTY),
    .FULL           (FULL),
    .PROGEMPTY      (),
    .PROGFULL       (),
    .RDCOUNT        (),
    .RDERR          (),
    .RDRSTBUSY      (RDRSTBUSY),
    .WRCOUNT        (),
    .WRERR          (),
    .WRRSTBUSY      (WRRSTBUSY),

    .CASDIN         (CASDIN32),
    .CASDINP        (CASDINP),
    .CASDOMUX       (1'b0),
    .CASDOMUXEN     (1'b0),
    .CASNXTRDEN     (CASNXTRDEN),
    .CASOREGIMUX    (1'b0),
    .CASOREGIMUXEN  (1'b0),
    .CASPRVEMPTY    (CASPRVEMPTY),

    .RDCLK          (RDCLK),
    .RDEN           (RDEN),
    .REGCE          (1'b1),
    .RSTREG         (1'b0),
    .SLEEP          (1'b0),

    .RST            (resetn),
    .WRCLK          (WRCLK),
    .WREN           (WREN),

    .DIN            (DIN32),
    .DINP           (DINP)
    );

  assign EMPTY_N = ~EMPTY;
  assign FULL_N  = ~FULL;

  generate
    if ((W <= 8) || ((W > 9) && (W <= 16)) || ((W > 18) && (W <= 32))) begin
      assign DOUT    = DOUT32[W-1:0];
      assign CASDOUT = CASDOUT32[W-1:0];
      assign {DINP, DIN32}       = {{(4+32-W){1'b0}}, DIN[W-1:0]};
      assign {CASDINP, CASDIN32} = {{(4+32-W){1'b0}}, CASDIN[W-1:0]};
    end
    else if (W == 9) begin
      assign DOUT    = {DOUTP[0],    DOUT32[7:0]};
      assign CASDOUT = {CASDOUTP[0], CASDOUT32[7:0]};
      assign {DINP, DIN32}       = {{3{1'b0}}, DIN[8], {24{1'b0}}, DIN[7:0]};
      assign {CASDINP, CASDIN32} = {{3{1'b0}}, CASDIN[8], {24{1'b0}}, CASDIN[7:0]};
    end
    else if ((W >= 17) && (W <= 18)) begin
      assign DOUT    = {DOUTP[W-17:0],    DOUT32[15:0]};
      assign CASDOUT = {CASDOUTP[W-17:0], CASDOUT32[15:0]};
      assign {DINP, DIN32}       = {{(20-W){1'b0}}, DIN[W-1:16], {16{1'b0}}, DIN[15:0]};
      assign {CASDINP, CASDIN32} = {{(20-W){1'b0}}, CASDIN[W-1:16], {16{1'b0}}, CASDIN[15:0]};
    end
    else if ((W >= 33) && (W <= 36)) begin
      assign DOUT    = {DOUTP[W-33:0],    DOUT32[31:0]};
      assign CASDOUT = {CASDOUTP[W-33:0], CASDOUT32[31:0]};
      if (W < 36) begin
        assign {DINP, DIN32}       = {{(36-W){1'b0}}, DIN[W-1:0]};
        assign {CASDINP, CASDIN32} = {{(36-W){1'b0}}, CASDIN[W-1:0]};
      end
      else begin


        assign {DINP, DIN32}       = DIN[W-1:0];
        assign {CASDINP, CASDIN32} = CASDIN[W-1:0];
      end
    end
  endgenerate

endmodule
module FIFO18E2_WRAPPER
#(
  parameter CASCADE_ORDER = "NONE",
  parameter CLOCK_DOMAINS = "COMMON",
  parameter FIRST_WORD_FALL_THROUGH = "TRUE",
  parameter REGISTER_MODE = "REGISTERED",
  parameter integer W = 32
 )
 (
  output [W-1:0] CASDOUT,
  output         CASNXTEMPTY,
  output         CASPRVRDEN,
  output [W-1:0] DOUT,
  output         EMPTY_N,
  output         FULL_N,
  output         RDRSTBUSY,
  output         WRRSTBUSY,

  input [W-1:0]  CASDIN,
  input          CASNXTRDEN,
  input          CASPRVEMPTY,
  input          CLR,
  input [W-1:0]  DIN,
  input          RDCLK,
  input          RDEN,
  input          RST_N,
  input          WRCLK,
  input          WREN

  );


  wire          EMPTY;
  wire          FULL;



  wire          resetn = ~(~RST_N || CLR);

  wire [31:0]   CASDOUT32;
  wire [3:0]    CASDOUTP;

  wire [31:0]   DOUT32;
  wire [3:0]    DOUTP;

  wire [31:0]   CASDIN32;
  wire [3:0]    CASDINP;

  wire [31:0]   DIN32;
  wire [3:0]    DINP;

  localparam WIDTH = (W <= 4) ? 4 : ((W <= 9) ? 9 : ((W <= 18) ? 18 : 36));




  FIFO18E2
  #(
    .CASCADE_ORDER           (CASCADE_ORDER),
    .CLOCK_DOMAINS           (CLOCK_DOMAINS),
    .FIRST_WORD_FALL_THROUGH (FIRST_WORD_FALL_THROUGH),
    .INIT                    (36'h000000000),
    .PROG_EMPTY_THRESH       (256),
    .PROG_FULL_THRESH        (256),

    .IS_RDCLK_INVERTED       (1'b0),
    .IS_RDEN_INVERTED        (1'b0),
    .IS_RSTREG_INVERTED      (1'b0),
    .IS_RST_INVERTED         (1'b1),
    .IS_WRCLK_INVERTED       (1'b0),
    .IS_WREN_INVERTED        (1'b0),
    .RDCOUNT_TYPE            ("EXTENDED_DATACOUNT"),
    .READ_WIDTH              (WIDTH),
    .REGISTER_MODE           (REGISTER_MODE),
    .RSTREG_PRIORITY         ("RSTREG"),
    .SLEEP_ASYNC             ("FALSE"),
    .SRVAL                   (36'h000000000),
    .WRCOUNT_TYPE            ("EXTENDED_DATACOUNT"),
    .WRITE_WIDTH             (WIDTH)
  ) FIFO18E2_i
   (

    .CASDOUT        (CASDOUT32),
    .CASDOUTP       (CASDOUTP),
    .CASNXTEMPTY    (CASNXTEMPTY),
    .CASPRVRDEN     (CASPRVRDEN),

    .DOUT           (DOUT32),
    .DOUTP          (DOUTP),

    .EMPTY          (EMPTY),
    .FULL           (FULL),
    .PROGEMPTY      (),
    .PROGFULL       (),
    .RDCOUNT        (),
    .RDERR          (),
    .RDRSTBUSY      (RDRSTBUSY),
    .WRCOUNT        (),
    .WRERR          (),
    .WRRSTBUSY      (WRRSTBUSY),

    .CASDIN         (CASDIN32),
    .CASDINP        (CASDINP),
    .CASDOMUX       (1'b0),
    .CASDOMUXEN     (1'b0),
    .CASNXTRDEN     (CASNXTRDEN),
    .CASOREGIMUX    (1'b0),
    .CASOREGIMUXEN  (1'b0),
    .CASPRVEMPTY    (CASPRVEMPTY),

    .RDCLK          (RDCLK),
    .RDEN           (RDEN),
    .REGCE          (1'b1),
    .RSTREG         (1'b0),
    .SLEEP          (1'b0),

    .RST            (resetn),
    .WRCLK          (WRCLK),
    .WREN           (WREN),

    .DIN            (DIN32),
    .DINP           (DINP)
    );

  assign EMPTY_N = ~EMPTY;
  assign FULL_N  = ~FULL;

  generate
    if ((W <= 8) || ((W > 9) && (W <= 16)) || ((W > 18) && (W <= 32))) begin
      assign DOUT    = DOUT32[W-1:0];
      assign CASDOUT = CASDOUT32[W-1:0];
      assign {DINP, DIN32}       = {{(4+32-W){1'b0}}, DIN[W-1:0]};
      assign {CASDINP, CASDIN32} = {{(4+32-W){1'b0}}, CASDIN[W-1:0]};
    end
    else if (W == 9) begin
      assign DOUT    = {DOUTP[0],    DOUT32[7:0]};
      assign CASDOUT = {CASDOUTP[0], CASDOUT32[7:0]};
      assign {DINP, DIN32}       = {{3{1'b0}}, DIN[8], {24{1'b0}}, DIN[7:0]};
      assign {CASDINP, CASDIN32} = {{3{1'b0}}, CASDIN[8], {24{1'b0}}, CASDIN[7:0]};
    end
    else if ((W >= 17) && (W <= 18)) begin
      assign DOUT    = {DOUTP[W-17:0],    DOUT32[15:0]};
      assign CASDOUT = {CASDOUTP[W-17:0], CASDOUT32[15:0]};
      assign {DINP, DIN32}       = {{(20-W){1'b0}}, DIN[W-1:16], {16{1'b0}}, DIN[15:0]};
      assign {CASDINP, CASDIN32} = {{(20-W){1'b0}}, CASDIN[W-1:16], {16{1'b0}}, CASDIN[15:0]};
    end
    else if ((W >= 33) && (W <= 36)) begin
      assign DOUT    = {DOUTP[W-33:0],    DOUT32[31:0]};
      assign CASDOUT = {CASDOUTP[W-33:0], CASDOUT32[31:0]};
      if (W < 36) begin
        assign {DINP, DIN32}       = {{(36-W){1'b0}}, DIN[W-1:0]};
        assign {CASDINP, CASDIN32} = {{(36-W){1'b0}}, CASDIN[W-1:0]};
      end
      else begin


        assign {DINP, DIN32}       = DIN[W-1:0];
        assign {CASDINP, CASDIN32} = CASDIN[W-1:0];
      end
    end
  endgenerate

endmodule