data/full_repos/permissive/456528918/RTL/YD_reg.v
data/verilator_xmls/adf8323a-b3f6-4f2c-939f-817b81c10834.xml
module YD_reg (
	input wire clk,
	input wire rst,
	input wire jpc,
	input wire dsv,

	input wire [15:0]din0,
	input wire [3:0]waddr0,
	input wire we0,

	input wire [15:0]din1,
	input wire [3:0]waddr1,
	input wire we1,

	input wire [3:0]raddr0,
	output reg [15:0]dout0,

	input wire [3:0]raddr1,
	output reg [15:0]dout1,

	output reg [15:0]PC,
	output reg [15:0]DKD
);

reg [15:0]RX[12:0];
reg [15:0]DK;

reg [3:0]raddr0_r;
reg [3:0]raddr1_r;
reg [3:0]waddr0_r;
reg [3:0]waddr1_r;
reg we0_r;
reg we1_r;
reg [15:0]din0_r;
reg [15:0]din1_r;
reg [15:0]dout0_r;
reg [15:0]dout1_r;

localparam ZEA=4'b0000;
localparam DKA=4'b0001;
localparam R0A=4'b0010;

localparam PCA=4'b1111;


always @(posedge clk) begin
if(rst) begin
	DK <= 16'h0;
	PC <= 16'h0;
	RX[0] <= 16'h0;
	RX[1] <= 16'h0;
	RX[2] <= 16'h0;
	RX[3] <= 16'h0;
	RX[4] <= 16'h0;
	RX[5] <= 16'h0;
	RX[6] <= 16'h0;
	RX[7] <= 16'h0;
	RX[8] <= 16'h0;
	RX[9] <= 16'h0;
	RX[10] <= 16'h0;
	RX[11] <= 16'h0;
	RX[12] <= 16'h0;
	end 
else begin
	if(~jpc && ~dsv)
		PC <= PC+16'h1;
	if(we0&&we1&&(waddr0==waddr1)) begin
		case(waddr0)
			ZEA:;
			DKA:DK <= din0;
			PCA:if(jpc) PC <= din0;
			default:RX[waddr0-R0A] <= din0;
			endcase 
		end
	else begin
		if(we0) begin
			case(waddr0)
				ZEA:;
				DKA:DK <= din0;
				PCA:if(jpc) PC <= din0;
				default:RX[waddr0-R0A] <= din0;
				endcase 
			end
		if(we1) begin
			case(waddr1)
				ZEA:;
				DKA:DK <= din1;
				PCA:if(jpc) PC <= din1;
				default:RX[waddr1-R0A] <= din1;
				endcase 
			end
		end
	end
end



always @(posedge clk) begin
if(rst) begin
	raddr0_r <= 4'h0;
	raddr1_r <= 4'h0;
	waddr0_r <= 4'h0;
	waddr1_r <= 4'h0;
	din0_r <= 16'h0;
	din1_r <= 16'h0;
	we0_r <= 1'b0;
	we1_r <= 1'b0;
	end 
else begin
	raddr0_r <= raddr0;
	raddr1_r <= raddr1;
	waddr0_r <= waddr0;
	waddr1_r <= waddr1;
	din0_r <= din0;
	din1_r <= din1;
	we0_r <= we0;
	we1_r <= we1;
	end
end


always @(*) begin
	case (raddr0_r)
		ZEA:dout0=16'h0;
		DKA:
			if ((raddr0_r==waddr0_r&&we0_r)||(raddr0_r==waddr1_r&&we1_r))
				if(raddr0_r==waddr0_r&&we0_r)
					dout0=din0_r;
				else if(raddr0_r==waddr1_r&&we1_r)
					dout0=din1_r;
				else
					dout0=DK;
			else
				dout0=DK;
		PCA:
			if (((raddr0_r==waddr0_r&&we0_r)||(raddr0_r==waddr1_r&&we1_r))&&jpc)
				if(raddr0_r==waddr0_r&&we0_r)
					dout0=din0_r;
				else if(raddr0_r==waddr1_r&&we1_r)
					dout0=din1_r;
				else
					dout0=PC;
			else
				dout0=PC;
		default:
			if ((raddr0_r==waddr0_r&&we0_r)||(raddr0_r==waddr1_r&&we1_r))
				if(raddr0_r==waddr0_r&&we0_r)
					dout0=din0_r;
				else if(raddr0_r==waddr1_r&&we1_r)
					dout0=din1_r;
				else
					dout0=RX[raddr0_r-R0A];
			else
				dout0=RX[raddr0_r-R0A];
		endcase

	case (raddr1_r)
		ZEA:dout1=16'h0;
		DKA:
			if ((raddr1_r==waddr0_r&&we0_r)||(raddr1_r==waddr1_r&&we1_r))
				if(raddr1_r==waddr0_r&&we0_r)
					dout1=din0_r;
				else if(raddr1_r==waddr1_r&&we1_r)
					dout1=din1_r;
				else
					dout1=DK;
			else
				dout1=DK;
		PCA:
			if (((raddr1_r==waddr0_r&&we0_r)||(raddr1_r==waddr1_r&&we1_r))&&jpc)
				if(raddr1_r==waddr0_r&&we0_r)
					dout1=din0_r;
				else if(raddr1_r==waddr1_r&&we1_r)
					dout1=din1_r;
				else
					dout1=PC;
			else
				dout1=PC;
		default:
			if ((raddr1_r==waddr0_r&&we0_r)||(raddr1_r==waddr1_r&&we1_r))
				if(raddr1_r==waddr0_r&&we0_r)
					dout1=din0_r;
				else if(raddr1_r==waddr1_r&&we1_r)
					dout1=din1_r;
				else
					dout1=RX[raddr1_r-R0A];
			else
				dout1=RX[raddr1_r-R0A];
		endcase
end


always @(*) begin
	DKD=DK;
	if(waddr0==DKA && we0 || waddr1==DKA && we1)
		if(waddr0==DKA && we0)
			DKD=din0;
		else if(waddr1==DKA && we1)
			DKD=din1;
	else
		DKD=DK;
end


wire [15:0]R0W=RX[0];
wire [15:0]R1W=RX[1];
wire [15:0]R2W=RX[2];
wire [15:0]R3W=RX[3];
wire [15:0]R4W=RX[4];
wire [15:0]R5W=RX[5];
wire [15:0]R6W=RX[6];
wire [15:0]R7W=RX[7];
wire [15:0]R8W=RX[8];
wire [15:0]R9W=RX[9];
wire [15:0]RAW=RX[10];
wire [15:0]RBW=RX[11];
wire [15:0]RCW=RX[12];

endmodule
module YD_reg (
	input wire clk,
	input wire rst,
	input wire jpc,
	input wire dsv,

	input wire [15:0]din0,
	input wire [3:0]waddr0,
	input wire we0,

	input wire [15:0]din1,
	input wire [3:0]waddr1,
	input wire we1,

	input wire [3:0]raddr0,
	output reg [15:0]dout0,

	input wire [3:0]raddr1,
	output reg [15:0]dout1,

	output reg [15:0]PC,
	output reg [15:0]DKD
);


reg [15:0]RX[12:0];
reg [15:0]DK;

reg [3:0]raddr0_r;
reg [3:0]raddr1_r;
reg [3:0]waddr0_r;
reg [3:0]waddr1_r;
reg we0_r;
reg we1_r;
reg [15:0]din0_r;
reg [15:0]din1_r;
reg [15:0]dout0_r;
reg [15:0]dout1_r;

localparam ZEA=4'b0000;
localparam DKA=4'b0001;
localparam R0A=4'b0010;

localparam PCA=4'b1111;


always @(posedge clk) begin
if(rst) begin
	DK <= 16'h0;
	PC <= 16'h0;
	RX[0] <= 16'h0;
	RX[1] <= 16'h0;
	RX[2] <= 16'h0;
	RX[3] <= 16'h0;
	RX[4] <= 16'h0;
	RX[5] <= 16'h0;
	RX[6] <= 16'h0;
	RX[7] <= 16'h0;
	RX[8] <= 16'h0;
	RX[9] <= 16'h0;
	RX[10] <= 16'h0;
	RX[11] <= 16'h0;
	RX[12] <= 16'h0;
	end 
else begin
	if(~jpc && ~dsv)
		PC <= PC+16'h1;
	if(we0&&we1&&(waddr0==waddr1)) begin
		case(waddr0)
			ZEA:;
			DKA:DK <= din0;
			PCA:if(jpc) PC <= din0;
			default:RX[waddr0-R0A] <= din0;
			endcase 
		end
	else begin
		if(we0) begin
			case(waddr0)
				ZEA:;
				DKA:DK <= din0;
				PCA:if(jpc) PC <= din0;
				default:RX[waddr0-R0A] <= din0;
				endcase 
			end
		if(we1) begin
			case(waddr1)
				ZEA:;
				DKA:DK <= din1;
				PCA:if(jpc) PC <= din1;
				default:RX[waddr1-R0A] <= din1;
				endcase 
			end
		end
	end
end



always @(posedge clk) begin
if(rst) begin
	raddr0_r <= 4'h0;
	raddr1_r <= 4'h0;
	waddr0_r <= 4'h0;
	waddr1_r <= 4'h0;
	din0_r <= 16'h0;
	din1_r <= 16'h0;
	we0_r <= 1'b0;
	we1_r <= 1'b0;
	end 
else begin
	raddr0_r <= raddr0;
	raddr1_r <= raddr1;
	waddr0_r <= waddr0;
	waddr1_r <= waddr1;
	din0_r <= din0;
	din1_r <= din1;
	we0_r <= we0;
	we1_r <= we1;
	end
end


always @(*) begin
	case (raddr0_r)
		ZEA:dout0=16'h0;
		DKA:
			if ((raddr0_r==waddr0_r&&we0_r)||(raddr0_r==waddr1_r&&we1_r))
				if(raddr0_r==waddr0_r&&we0_r)
					dout0=din0_r;
				else if(raddr0_r==waddr1_r&&we1_r)
					dout0=din1_r;
				else
					dout0=DK;
			else
				dout0=DK;
		PCA:
			if (((raddr0_r==waddr0_r&&we0_r)||(raddr0_r==waddr1_r&&we1_r))&&jpc)
				if(raddr0_r==waddr0_r&&we0_r)
					dout0=din0_r;
				else if(raddr0_r==waddr1_r&&we1_r)
					dout0=din1_r;
				else
					dout0=PC;
			else
				dout0=PC;
		default:
			if ((raddr0_r==waddr0_r&&we0_r)||(raddr0_r==waddr1_r&&we1_r))
				if(raddr0_r==waddr0_r&&we0_r)
					dout0=din0_r;
				else if(raddr0_r==waddr1_r&&we1_r)
					dout0=din1_r;
				else
					dout0=RX[raddr0_r-R0A];
			else
				dout0=RX[raddr0_r-R0A];
		endcase

	case (raddr1_r)
		ZEA:dout1=16'h0;
		DKA:
			if ((raddr1_r==waddr0_r&&we0_r)||(raddr1_r==waddr1_r&&we1_r))
				if(raddr1_r==waddr0_r&&we0_r)
					dout1=din0_r;
				else if(raddr1_r==waddr1_r&&we1_r)
					dout1=din1_r;
				else
					dout1=DK;
			else
				dout1=DK;
		PCA:
			if (((raddr1_r==waddr0_r&&we0_r)||(raddr1_r==waddr1_r&&we1_r))&&jpc)
				if(raddr1_r==waddr0_r&&we0_r)
					dout1=din0_r;
				else if(raddr1_r==waddr1_r&&we1_r)
					dout1=din1_r;
				else
					dout1=PC;
			else
				dout1=PC;
		default:
			if ((raddr1_r==waddr0_r&&we0_r)||(raddr1_r==waddr1_r&&we1_r))
				if(raddr1_r==waddr0_r&&we0_r)
					dout1=din0_r;
				else if(raddr1_r==waddr1_r&&we1_r)
					dout1=din1_r;
				else
					dout1=RX[raddr1_r-R0A];
			else
				dout1=RX[raddr1_r-R0A];
		endcase
end


always @(*) begin
	DKD=DK;
	if(waddr0==DKA && we0 || waddr1==DKA && we1)
		if(waddr0==DKA && we0)
			DKD=din0;
		else if(waddr1==DKA && we1)
			DKD=din1;
	else
		DKD=DK;
end


wire [15:0]R0W=RX[0];
wire [15:0]R1W=RX[1];
wire [15:0]R2W=RX[2];
wire [15:0]R3W=RX[3];
wire [15:0]R4W=RX[4];
wire [15:0]R5W=RX[5];
wire [15:0]R6W=RX[6];
wire [15:0]R7W=RX[7];
wire [15:0]R8W=RX[8];
wire [15:0]R9W=RX[9];
wire [15:0]RAW=RX[10];
wire [15:0]RBW=RX[11];
wire [15:0]RCW=RX[12];

endmodule