data/full_repos/permissive/476477303/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/476477303/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n always #12.5 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v:75: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("peripheralsSPI.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v:80: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(1, peripheralsSPI_tb);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v:81: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(2, peripheralsSPI_tb.uut.mprj);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v:86: syntax error, unexpected \'@\'\n   repeat (1000) @(posedge clock);\n                 ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v:102: syntax error, unexpected \'@\'\n  @(posedge chipSelect);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v:110: Unsupported: wait statements\n  wait(shiftValue == 8\'h1F);\n  ^~~~\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v:113: syntax error, unexpected \'@\'\n  @(posedge nextTestOutput);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v:122: Unsupported: wait statements\n  wait(shiftValue == 8\'hA3);\n  ^~~~\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v:125: syntax error, unexpected \'@\'\n  @(posedge chipSelect);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v:133: syntax error, unexpected \'@\'\n  @(posedge nextTestOutput);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v:136: Unsupported: wait statements\n  wait(shiftValue == 8\'h1F);\n  ^~~~\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v:139: syntax error, unexpected \'@\'\n  @(posedge nextTestOutput);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v:142: Unsupported: wait statements\n  wait(shiftValue == 8\'h83);\n  ^~~~\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v:145: syntax error, unexpected \'@\'\n  @(posedge nextTestOutput);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v:150: syntax error, unexpected \'@\'\n  @(posedge nextTestOutput);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v:155: Unsupported: wait statements\n  wait(chipSelect == 1\'b0);\n  ^~~~\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v:158: syntax error, unexpected \'@\'\n  @(negedge sck);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v:162: syntax error, unexpected \'@\'\n  @(posedge sck);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v:171: syntax error, unexpected \'@\'\n  @(negedge sck);\n  ^\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v:180: Unsupported: wait statements\n  wait(shiftValue == 8\'h9B);\n  ^~~~\n%Error: data/full_repos/permissive/476477303/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v:183: syntax error, unexpected \'@\'\n  @(posedge nextTestOutput);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/476477303/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v:216: Unsupported: Ignoring delay on this delayed statement.\n  #2000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/476477303/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v:218: Unsupported: Ignoring delay on this delayed statement.\n  #300000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/476477303/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v:227: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/476477303/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v:229: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/476477303/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v:231: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/476477303/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v:233: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/476477303/verilog/dv/peripheralsSPI/peripheralsSPI_tb.v:238: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("Success:0b%b Timing Valid:0b%b Next test:0b%b", succesOutput, timingValid, nextTestOutput);\n  ^\n%Error: Exiting due to 21 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module peripheralsSPI_tb;
	reg clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

	wire gpio;
	wire [37:0] mprj_io;

	wire sck = mprj_io[22];
	wire mosi = mprj_io[23];
	wire miso;
	assign mprj_io[24] = miso;
	wire chipSelect = mprj_io[25];

	reg[7:0] shiftValue;
	assign miso = shiftValue[7];

	wire succesOutput = mprj_io[12];
	wire nextTestOutput = mprj_io[13];
	reg timingValid = 1'b1;

	pullup(mprj_io[3]);
	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;




	always #12.5 clock <= (clock === 1'b0);


	assign mprj_io[2:0] = 3'b0;
	assign mprj_io[11:4] = 8'b0;
	assign mprj_io[21:17] = 5'b0;
	assign mprj_io[37:26] = 12'b0;

	reg clockMode;
	wire spiClock = clockMode ^ sck;

	always @(posedge spiClock) begin
		if (!chipSelect) shiftValue <= { shiftValue[6:0], mosi };
	end

	initial begin
		clock = 0;
		timingValid = 1'b1;
		shiftValue = 8'hC5;
		clockMode = 1'b0;
	end

	realtime timerStart;
	realtime timerLength;

	initial begin
		$dumpfile("peripheralsSPI.vcd");

`ifdef SIM
		$dumpvars(0, peripheralsSPI_tb);
`else
		$dumpvars(1, peripheralsSPI_tb);
		$dumpvars(2, peripheralsSPI_tb.uut.mprj);
`endif


		repeat (500) begin
			repeat (1000) @(posedge clock);

		end
		$display("%c[1;35m",27);
		`ifdef GL
			$display ("Monitor: Timeout, Peripherals SPI Test (GL) Failed");
		`else
			$display ("Monitor: Timeout, Peripherals SPI Test (RTL) Failed");
		`endif
		$display("%c[0m",27);
		$finish;
	end

	initial begin
		

		@(posedge chipSelect);
		@(posedge sck);
		@(negedge sck);


		@(posedge nextTestOutput);


		wait(shiftValue == 8'h1F);


		@(posedge nextTestOutput);


		@(posedge nextTestOutput);


		@(negedge chipSelect);


		wait(shiftValue == 8'hA3);


		@(posedge chipSelect);


		@(posedge nextTestOutput);

		clockMode = 1'b1;


		@(posedge nextTestOutput);


		wait(shiftValue == 8'h1F);


		@(posedge nextTestOutput);


		wait(shiftValue == 8'h83);


		@(posedge nextTestOutput);

		clockMode = 1'b0;


		@(posedge nextTestOutput);


		

		wait(chipSelect == 1'b0);


		@(negedge sck);
		timerStart = $realtime;


		@(posedge sck);
		timerLength = $realtime - timerStart;
		$display("SCK Low Time: ", timerLength);
		if (timerLength < 190 || timerLength > 210) begin
			timingValid = 1'b0;
			$display("Invalid time, should be between 0.190us and 0.210us");
		end


		@(negedge sck);
		timerLength = $realtime - timerStart;
		$display("SCK Period:   ", timerLength);
		if (timerLength < 390 || timerLength > 410) begin
			timingValid = 1'b0;
			$display("Invalid time, should be between 0.390us and 0.410us");
		end
		

		wait(shiftValue == 8'h9B);


		@(posedge nextTestOutput);
		
		if (!timingValid) begin
			$display("%c[1;31m",27);
			`ifdef GL
				$display ("Monitor: Peripherals SPI Timing (GL) Failed");
			`else
				$display ("Monitor: Peripherals SPI Timing (RTL) Failed");
			`endif
			$display("%c[0m",27);
		end else if (succesOutput) begin
			$display("%c[1;92m",27);
			`ifdef GL
				$display("Monitor: Peripherals SPI Test (GL) Passed");
			`else
				$display("Monitor: Peripherals SPI Test (RTL) Passed");
			`endif
			$display("%c[0m",27);
		end else begin
			$display("%c[1;31m",27);
			`ifdef GL
				$display ("Monitor: Peripherals SPI Test (GL) Failed");
			`else
				$display ("Monitor: Peripherals SPI Test (RTL) Failed");
			`endif
			$display("%c[0m",27);
		end
	    $finish;
	end

	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#300000;
		CSB = 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end

	always @(succesOutput, nextTestOutput, timingValid) begin
		#1 $display("Success:0b%b Timing Valid:0b%b Next test:0b%b", succesOutput, timingValid, nextTestOutput);
	end

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3;
	wire VDD1V8;
	wire VSS;
	
	assign VDD3V3 = power1;
	assign VDD1V8 = power2;
	assign VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda1_2  (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock    (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("peripheralsSPI.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule
module peripheralsSPI_tb;

	reg clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

	wire gpio;
	wire [37:0] mprj_io;

	wire sck = mprj_io[22];
	wire mosi = mprj_io[23];
	wire miso;
	assign mprj_io[24] = miso;
	wire chipSelect = mprj_io[25];

	reg[7:0] shiftValue;
	assign miso = shiftValue[7];

	wire succesOutput = mprj_io[12];
	wire nextTestOutput = mprj_io[13];
	reg timingValid = 1'b1;

	pullup(mprj_io[3]);
	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;




	always #12.5 clock <= (clock === 1'b0);


	assign mprj_io[2:0] = 3'b0;
	assign mprj_io[11:4] = 8'b0;
	assign mprj_io[21:17] = 5'b0;
	assign mprj_io[37:26] = 12'b0;

	reg clockMode;
	wire spiClock = clockMode ^ sck;

	always @(posedge spiClock) begin
		if (!chipSelect) shiftValue <= { shiftValue[6:0], mosi };
	end

	initial begin
		clock = 0;
		timingValid = 1'b1;
		shiftValue = 8'hC5;
		clockMode = 1'b0;
	end

	realtime timerStart;
	realtime timerLength;

	initial begin
		$dumpfile("peripheralsSPI.vcd");

`ifdef SIM
		$dumpvars(0, peripheralsSPI_tb);
`else
		$dumpvars(1, peripheralsSPI_tb);
		$dumpvars(2, peripheralsSPI_tb.uut.mprj);
`endif


		repeat (500) begin
			repeat (1000) @(posedge clock);

		end
		$display("%c[1;35m",27);
		`ifdef GL
			$display ("Monitor: Timeout, Peripherals SPI Test (GL) Failed");
		`else
			$display ("Monitor: Timeout, Peripherals SPI Test (RTL) Failed");
		`endif
		$display("%c[0m",27);
		$finish;
	end

	initial begin
		

		@(posedge chipSelect);
		@(posedge sck);
		@(negedge sck);


		@(posedge nextTestOutput);


		wait(shiftValue == 8'h1F);


		@(posedge nextTestOutput);


		@(posedge nextTestOutput);


		@(negedge chipSelect);


		wait(shiftValue == 8'hA3);


		@(posedge chipSelect);


		@(posedge nextTestOutput);

		clockMode = 1'b1;


		@(posedge nextTestOutput);


		wait(shiftValue == 8'h1F);


		@(posedge nextTestOutput);


		wait(shiftValue == 8'h83);


		@(posedge nextTestOutput);

		clockMode = 1'b0;


		@(posedge nextTestOutput);


		

		wait(chipSelect == 1'b0);


		@(negedge sck);
		timerStart = $realtime;


		@(posedge sck);
		timerLength = $realtime - timerStart;
		$display("SCK Low Time: ", timerLength);
		if (timerLength < 190 || timerLength > 210) begin
			timingValid = 1'b0;
			$display("Invalid time, should be between 0.190us and 0.210us");
		end


		@(negedge sck);
		timerLength = $realtime - timerStart;
		$display("SCK Period:   ", timerLength);
		if (timerLength < 390 || timerLength > 410) begin
			timingValid = 1'b0;
			$display("Invalid time, should be between 0.390us and 0.410us");
		end
		

		wait(shiftValue == 8'h9B);


		@(posedge nextTestOutput);
		
		if (!timingValid) begin
			$display("%c[1;31m",27);
			`ifdef GL
				$display ("Monitor: Peripherals SPI Timing (GL) Failed");
			`else
				$display ("Monitor: Peripherals SPI Timing (RTL) Failed");
			`endif
			$display("%c[0m",27);
		end else if (succesOutput) begin
			$display("%c[1;92m",27);
			`ifdef GL
				$display("Monitor: Peripherals SPI Test (GL) Passed");
			`else
				$display("Monitor: Peripherals SPI Test (RTL) Passed");
			`endif
			$display("%c[0m",27);
		end else begin
			$display("%c[1;31m",27);
			`ifdef GL
				$display ("Monitor: Peripherals SPI Test (GL) Failed");
			`else
				$display ("Monitor: Peripherals SPI Test (RTL) Failed");
			`endif
			$display("%c[0m",27);
		end
	    $finish;
	end

	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#300000;
		CSB = 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end

	always @(succesOutput, nextTestOutput, timingValid) begin
		#1 $display("Success:0b%b Timing Valid:0b%b Next test:0b%b", succesOutput, timingValid, nextTestOutput);
	end

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3;
	wire VDD1V8;
	wire VSS;
	
	assign VDD3V3 = power1;
	assign VDD1V8 = power2;
	assign VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda1_2  (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock    (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("peripheralsSPI.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule