data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/fifo_depth_monitor.v
1: b'%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/fifo_depth_monitor.v:33: Cannot find include file: nf_sume_blueswitch_register_define.v\n`include "nf_sume_blueswitch_register_define.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog,data/full_repos/permissive/498471995/nf_sume_blueswitch_register_define.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog,data/full_repos/permissive/498471995/nf_sume_blueswitch_register_define.v.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog,data/full_repos/permissive/498471995/nf_sume_blueswitch_register_define.v.sv\n             nf_sume_blueswitch_register_define.v\n             nf_sume_blueswitch_register_define.v.v\n             nf_sume_blueswitch_register_define.v.sv\n             obj_dir/nf_sume_blueswitch_register_define.v\n             obj_dir/nf_sume_blueswitch_register_define.v.v\n             obj_dir/nf_sume_blueswitch_register_define.v.sv\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/fifo_depth_monitor.v:34: Cannot find include file: nf_sume_blueswitch_parameter_define.v\n`include "nf_sume_blueswitch_parameter_define.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module fifo_depth_monitor
#(
   parameter   C_S_AXI_DATA_WIDTH      = 32
)
(
   input                                        axi_aclk,
   input                                        axi_resetn,

   input                                        fifo_wren,
   input                                        fifo_rden,

   input                                        clear,

   output   reg   [C_S_AXI_DATA_WIDTH-1:0]      fifo_depth,
   output   reg   [C_S_AXI_DATA_WIDTH-1:0]      fifo_depth_max
);

reg   r_fifo_wren, r_fifo_rden;
always @(posedge axi_aclk)
   if (~axi_resetn) begin
      r_fifo_wren    <= 0;
      r_fifo_rden    <= 0;
   end
   else begin
      r_fifo_wren    <= fifo_wren;
      r_fifo_rden    <= fifo_rden;
   end

reg   r_rden, r_wren;
always @(posedge axi_aclk)
   if (~axi_resetn) begin
      r_rden   <= 0;
      r_wren   <= 0;
   end
   else begin
      r_rden   <= (r_fifo_wren &  ~r_fifo_rden);
      r_wren   <= (r_fifo_rden &  ~r_fifo_wren);
   end
   
always @(posedge axi_aclk)
   if (~axi_resetn)
      fifo_depth  <= 0;
   else if (clear)
      fifo_depth  <= 0;
   else if (r_rden)
      fifo_depth  <= fifo_depth + 1;
   else if (r_wren)
      fifo_depth  <= fifo_depth - 1;

always @(posedge axi_aclk)
   if (~axi_resetn)
      fifo_depth_max <= 0;
   else if (clear)
      fifo_depth_max <= 0;
   else if (fifo_depth > fifo_depth_max)
      fifo_depth_max <= fifo_depth;

endmodule
module fifo_depth_monitor
#(
   parameter   C_S_AXI_DATA_WIDTH      = 32
)
(
   input                                        axi_aclk,
   input                                        axi_resetn,

   input                                        fifo_wren,
   input                                        fifo_rden,

   input                                        clear,

   output   reg   [C_S_AXI_DATA_WIDTH-1:0]      fifo_depth,
   output   reg   [C_S_AXI_DATA_WIDTH-1:0]      fifo_depth_max
);


reg   r_fifo_wren, r_fifo_rden;
always @(posedge axi_aclk)
   if (~axi_resetn) begin
      r_fifo_wren    <= 0;
      r_fifo_rden    <= 0;
   end
   else begin
      r_fifo_wren    <= fifo_wren;
      r_fifo_rden    <= fifo_rden;
   end

reg   r_rden, r_wren;
always @(posedge axi_aclk)
   if (~axi_resetn) begin
      r_rden   <= 0;
      r_wren   <= 0;
   end
   else begin
      r_rden   <= (r_fifo_wren &  ~r_fifo_rden);
      r_wren   <= (r_fifo_rden &  ~r_fifo_wren);
   end
   
always @(posedge axi_aclk)
   if (~axi_resetn)
      fifo_depth  <= 0;
   else if (clear)
      fifo_depth  <= 0;
   else if (r_rden)
      fifo_depth  <= fifo_depth + 1;
   else if (r_wren)
      fifo_depth  <= fifo_depth - 1;

always @(posedge axi_aclk)
   if (~axi_resetn)
      fifo_depth_max <= 0;
   else if (clear)
      fifo_depth_max <= 0;
   else if (fifo_depth > fifo_depth_max)
      fifo_depth_max <= fifo_depth;

endmodule