data/full_repos/permissive/424312442/final_project/sources_1/motor_project.v
1: b'%Error: data/full_repos/permissive/424312442/final_project/sources_1/motor_project.v:74: Cannot find file containing module: \'xadc_wiz_2\'\nxadc_wiz_2  XLXI_7 (\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/424312442/final_project/sources_1,data/full_repos/permissive/424312442/xadc_wiz_2\n             data/full_repos/permissive/424312442/final_project/sources_1,data/full_repos/permissive/424312442/xadc_wiz_2.v\n             data/full_repos/permissive/424312442/final_project/sources_1,data/full_repos/permissive/424312442/xadc_wiz_2.sv\n             xadc_wiz_2\n             xadc_wiz_2.v\n             xadc_wiz_2.sv\n             obj_dir/xadc_wiz_2\n             obj_dir/xadc_wiz_2.v\n             obj_dir/xadc_wiz_2.sv\n%Warning-WIDTH: data/full_repos/permissive/424312442/final_project/sources_1/motor_project.v:109: Input port connection \'jxADC\' expects 7 bits on the pin connection, but pin connection\'s VARREF \'JXADC\' generates 8 bits.\n                                                                                                : ... In instance main_driver\nadc_controller dut0(clk, JXADC, data);\n                         ^~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module adc_controller(CLK, jxADC, data_out);
input CLK;
input [6:0] jxADC;
output reg [15:0] data_out;

wire enable;
wire ready;
wire [15:0] data; 

xadc_wiz_2  XLXI_7 (
        .daddr_in(8'h1f),
        .dclk_in(CLK), 
        .den_in(enable), 
        .di_in(0), 
        .dwe_in(0),
        .vauxp15(jxADC[3]),
        .vauxn15(jxADC[7]), 
        .do_out(data),
        .eoc_out(enable),
        .drdy_out(ready));

always @(posedge CLK) begin
    data_out <= data; 
end
endmodule
module adc_controller(CLK, jxADC, data_out);

input CLK;
input [6:0] jxADC;
output reg [15:0] data_out;

wire enable;
wire ready;
wire [15:0] data; 

xadc_wiz_2  XLXI_7 (
        .daddr_in(8'h1f),
        .dclk_in(CLK), 
        .den_in(enable), 
        .di_in(0), 
        .dwe_in(0),
        .vauxp15(jxADC[3]),
        .vauxn15(jxADC[7]), 
        .do_out(data),
        .eoc_out(enable),
        .drdy_out(ready));

always @(posedge CLK) begin
    data_out <= data; 
end
endmodule