data/full_repos/permissive/43264243/counter.v
data/verilator_xmls/1d664c75-1016-43c1-a185-d1cf4f1b202d.xml
module counter (rstn, clk, up, down, count);

	parameter WIDTH = 8;
	
	input rstn;
	input clk;
	input up;
	input down;
	output [WIDTH-1:0] count;
	
	reg[WIDTH-1:0] count_int = 0;
	
	assign count = count_int;
	
	always @ (posedge clk or negedge rstn) begin
		if(rstn == 0) begin
			count_int <= 0;
		end else begin		
			if(up == 1) begin
				count_int  <= count_int + 1'b1;
			end else if(down == 1) begin
				count_int <= count_int - 1'b1;
			end
		end
	end
endmodule
module counter (rstn, clk, up, down, count);


	parameter WIDTH = 8;
	
	input rstn;
	input clk;
	input up;
	input down;
	output [WIDTH-1:0] count;
	
	reg[WIDTH-1:0] count_int = 0;
	
	assign count = count_int;
	
	always @ (posedge clk or negedge rstn) begin
		if(rstn == 0) begin
			count_int <= 0;
		end else begin		
			if(up == 1) begin
				count_int  <= count_int + 1'b1;
			end else if(down == 1) begin
				count_int <= count_int - 1'b1;
			end
		end
	end
endmodule