data/full_repos/permissive/490299936/verilog/speed_config.v
1: b'%Warning-WIDTH: data/full_repos/permissive/490299936/verilog/speed_config.v:40: Operator EQ expects 32 or 24 bits on the LHS, but LHS\'s VARREF \'cnt\' generates 13 bits.\n                                                                              : ... In instance speed_config\n else if((cnt == (10_000_000/10/1152)) || !bps_start) begin\n              ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/490299936/verilog/speed_config.v:52: Operator EQ expects 32 or 24 bits on the LHS, but LHS\'s VARREF \'cnt\' generates 13 bits.\n                                                                              : ... In instance speed_config\n else if(cnt == ((10_000_000/10/1152)/2)) begin\n             ^~\n%Error: Exiting due to 2 warning(s)\n'
module speed_config(
	input clk,
	input rst_n,
	input bps_start,
	output clk_bps
    );

`define CLK_PERIOD 10
`define BPS_SET	   1152
`define BPS_PARA (10_000_000/`CLK_PERIOD/`BPS_SET)
`define BPS_PARA_2 (`BPS_PARA/2)

reg [12:0] cnt;
reg clk_bps_r;

always @(posedge clk or negedge rst_n) begin
	if(!rst_n)begin
		cnt <= 13'd0;
	end
	else if((cnt == `BPS_PARA) || !bps_start) begin
		cnt <= 13'd0;
	end
	else begin
		cnt <= cnt + 1'b1;
	end
end

always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		clk_bps_r <= 1'b0;
	end
	else if(cnt == `BPS_PARA_2) begin
		clk_bps_r <= 1'b1;
	end
	else begin
		clk_bps_r <= 1'b0;
	end
end

assign clk_bps = clk_bps_r;

endmodule
module speed_config(
	input clk,
	input rst_n,
	input bps_start,
	output clk_bps
    );


`define CLK_PERIOD 10
`define BPS_SET	   1152
`define BPS_PARA (10_000_000/`CLK_PERIOD/`BPS_SET)
`define BPS_PARA_2 (`BPS_PARA/2)

reg [12:0] cnt;
reg clk_bps_r;

always @(posedge clk or negedge rst_n) begin
	if(!rst_n)begin
		cnt <= 13'd0;
	end
	else if((cnt == `BPS_PARA) || !bps_start) begin
		cnt <= 13'd0;
	end
	else begin
		cnt <= cnt + 1'b1;
	end
end

always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		clk_bps_r <= 1'b0;
	end
	else if(cnt == `BPS_PARA_2) begin
		clk_bps_r <= 1'b1;
	end
	else begin
		clk_bps_r <= 1'b0;
	end
end

assign clk_bps = clk_bps_r;

endmodule