data/full_repos/permissive/497232952/RTL/TOP_design.v
1: b'%Warning-WIDTH: data/full_repos/permissive/497232952/RTL/TOP_design.v:56: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                        : ... In instance TOP_design\n    nEXT_STATE = 1\'b0;\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module TOP_design(input clk , 
                  input rst_n , 
                  input d_in ,   
                  output out_mealy , 
                  output reg [`STATE_WIDTH-1:0] p_STATE  , 
                  output reg mealy_glitch_free
                   );
 reg [`STATE_WIDTH-1:0] nEXT_STATE ;
reg out ;


always @(posedge clk)
  begin
   if(~rst_n)
    begin
     p_STATE <= `S0; 
      end
   else
     begin
     p_STATE <= nEXT_STATE ; 
       end 
  end
            
     

  always @(*)
    begin
    nEXT_STATE = 1'b0;
     out = 1'b0;
     case(p_STATE)
    `S0: begin
            if(d_in == 1'b0)
        begin
             nEXT_STATE = `S0;
             out = 1'b0;
        end
              else
        begin
             nEXT_STATE = `S1;
             out = 1'b0;
          end
        end
    `S1 : begin
             if(d_in==1'b0)
             begin
               nEXT_STATE = `S2;
               out = 1'b0;
         end
               else
            begin 
              out = 1'b0;
               nEXT_STATE = `S1 ;
          end
        end  
    `S2 : begin
             if(d_in == 1'b0 )
            begin 
                 nEXT_STATE = `S0 ;
                  out = 1'b0;
                 end
               else
              begin 
                   nEXT_STATE = `S3;
                  out = 1'b0;
           end               
        end                 
     `S3 :  begin 
             if(d_in == 1'b0)  
             begin            
                nEXT_STATE = `S2;
                out = 1'b1;
               end 
            else
           begin
                out = 1'b0;
                nEXT_STATE = `S1 ;
            end
         end   
      default : begin
                 nEXT_STATE = `S0; 
                 end 
             endcase
           end              
                  


always @(posedge clk)
      begin                  
       if(~rst_n)
        begin
         mealy_glitch_free <= 1'b0;
          end
       else
   begin
       mealy_glitch_free <= out ;
       end                 
 end         
 
 assign out_mealy = out ; 
endmodule
module TOP_design(input clk , 
                  input rst_n , 
                  input d_in ,   
                  output out_mealy , 
                  output reg [`STATE_WIDTH-1:0] p_STATE  , 
                  output reg mealy_glitch_free
                   );

 reg [`STATE_WIDTH-1:0] nEXT_STATE ;
reg out ;


always @(posedge clk)
  begin
   if(~rst_n)
    begin
     p_STATE <= `S0; 
      end
   else
     begin
     p_STATE <= nEXT_STATE ; 
       end 
  end
            
     

  always @(*)
    begin
    nEXT_STATE = 1'b0;
     out = 1'b0;
     case(p_STATE)
    `S0: begin
            if(d_in == 1'b0)
        begin
             nEXT_STATE = `S0;
             out = 1'b0;
        end
              else
        begin
             nEXT_STATE = `S1;
             out = 1'b0;
          end
        end
    `S1 : begin
             if(d_in==1'b0)
             begin
               nEXT_STATE = `S2;
               out = 1'b0;
         end
               else
            begin 
              out = 1'b0;
               nEXT_STATE = `S1 ;
          end
        end  
    `S2 : begin
             if(d_in == 1'b0 )
            begin 
                 nEXT_STATE = `S0 ;
                  out = 1'b0;
                 end
               else
              begin 
                   nEXT_STATE = `S3;
                  out = 1'b0;
           end               
        end                 
     `S3 :  begin 
             if(d_in == 1'b0)  
             begin            
                nEXT_STATE = `S2;
                out = 1'b1;
               end 
            else
           begin
                out = 1'b0;
                nEXT_STATE = `S1 ;
            end
         end   
      default : begin
                 nEXT_STATE = `S0; 
                 end 
             endcase
           end              
                  


always @(posedge clk)
      begin                  
       if(~rst_n)
        begin
         mealy_glitch_free <= 1'b0;
          end
       else
   begin
       mealy_glitch_free <= out ;
       end                 
 end         
 
 assign out_mealy = out ; 
endmodule