data/full_repos/permissive/503509790/verilog/rtl/main_memory.v
1: b'%Warning-WIDTH: data/full_repos/permissive/503509790/verilog/rtl/main_memory.v:40: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s SEL generates 11 bits.\n                                                                                 : ... In instance main_memory\n    douta <= (dina[31]) ? dina[10:0] : (~dina[26:16] & gpio_out) | (dina[26:16] & dina[10:0]);\n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/503509790/verilog/rtl/main_memory.v:40: Operator NOT expects 32 bits on the LHS, but LHS\'s SEL generates 11 bits.\n                                                                                 : ... In instance main_memory\n    douta <= (dina[31]) ? dina[10:0] : (~dina[26:16] & gpio_out) | (dina[26:16] & dina[10:0]);\n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/503509790/verilog/rtl/main_memory.v:40: Operator AND expects 32 bits on the RHS, but RHS\'s VARREF \'gpio_out\' generates 11 bits.\n                                                                                 : ... In instance main_memory\n    douta <= (dina[31]) ? dina[10:0] : (~dina[26:16] & gpio_out) | (dina[26:16] & dina[10:0]);\n                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/503509790/verilog/rtl/main_memory.v:40: Operator AND expects 32 bits on the LHS, but LHS\'s SEL generates 11 bits.\n                                                                                 : ... In instance main_memory\n    douta <= (dina[31]) ? dina[10:0] : (~dina[26:16] & gpio_out) | (dina[26:16] & dina[10:0]);\n                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/503509790/verilog/rtl/main_memory.v:40: Operator AND expects 32 bits on the RHS, but RHS\'s SEL generates 11 bits.\n                                                                                 : ... In instance main_memory\n    douta <= (dina[31]) ? dina[10:0] : (~dina[26:16] & gpio_out) | (dina[26:16] & dina[10:0]);\n                                                                                ^\n%Warning-WIDTH: data/full_repos/permissive/503509790/verilog/rtl/main_memory.v:42: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'gpio_out\' generates 11 bits.\n                                                                                 : ... In instance main_memory\n   else douta <= gpio_out;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/503509790/verilog/rtl/main_memory.v:44: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'gpio_in_reg\' generates 11 bits.\n                                                                                 : ... In instance main_memory\n  else if (addra == ADDR_GPIO_IN) douta <= gpio_in_reg;\n                                        ^~\n%Error: Exiting due to 7 warning(s)\n'
module main_memory(
	`ifdef USE_POWER_PINS
		inout vccd1,
		inout vssd1,
	`endif
	input clk,
	input wea,
	input [5:0] addra,
	input [31:0] dina,
	input [10:0] gpio_in,
	output reg [31:0] douta,
	output reg [10:0] gpio_out
	);

	localparam ADDR_GPIO_OUT = 6'h3e;
	localparam ADDR_GPIO_IN  = 6'h3f;

	reg [31:0] mem [0:2**6-3];

	reg [10:0] gpio_in_reg;
	reg [10:0] gpio_in_reg_q0;
	reg [10:0] gpio_in_reg_q1;

	always @(posedge clk) begin
		if (addra < ADDR_GPIO_OUT) begin
			if (wea) begin
				mem[addra] <= dina;
				douta <= dina;
			end
			else douta <= mem[addra];
		end
		else if (addra == ADDR_GPIO_OUT) begin



			if (wea) begin
				gpio_out <= (~dina[31]) ? dina[10:0] : (~dina[26:16] & gpio_out) | (dina[26:16] & dina[10:0]);
				douta <= (dina[31]) ? dina[10:0] : (~dina[26:16] & gpio_out) | (dina[26:16] & dina[10:0]);
			end
			else douta <= gpio_out;
		end
		else if (addra == ADDR_GPIO_IN) douta <= gpio_in_reg;
	end

	always @(posedge clk) begin
	   gpio_in_reg <= gpio_in_reg_q1;
	   gpio_in_reg_q1 <= gpio_in_reg_q0;
	   gpio_in_reg_q0 <= gpio_in;
	end

endmodule
module main_memory(
	`ifdef USE_POWER_PINS
		inout vccd1,
		inout vssd1,
	`endif
	input clk,
	input wea,
	input [5:0] addra,
	input [31:0] dina,
	input [10:0] gpio_in,
	output reg [31:0] douta,
	output reg [10:0] gpio_out
	);


	localparam ADDR_GPIO_OUT = 6'h3e;
	localparam ADDR_GPIO_IN  = 6'h3f;

	reg [31:0] mem [0:2**6-3];

	reg [10:0] gpio_in_reg;
	reg [10:0] gpio_in_reg_q0;
	reg [10:0] gpio_in_reg_q1;

	always @(posedge clk) begin
		if (addra < ADDR_GPIO_OUT) begin
			if (wea) begin
				mem[addra] <= dina;
				douta <= dina;
			end
			else douta <= mem[addra];
		end
		else if (addra == ADDR_GPIO_OUT) begin



			if (wea) begin
				gpio_out <= (~dina[31]) ? dina[10:0] : (~dina[26:16] & gpio_out) | (dina[26:16] & dina[10:0]);
				douta <= (dina[31]) ? dina[10:0] : (~dina[26:16] & gpio_out) | (dina[26:16] & dina[10:0]);
			end
			else douta <= gpio_out;
		end
		else if (addra == ADDR_GPIO_IN) douta <= gpio_in_reg;
	end

	always @(posedge clk) begin
	   gpio_in_reg <= gpio_in_reg_q1;
	   gpio_in_reg_q1 <= gpio_in_reg_q0;
	   gpio_in_reg_q0 <= gpio_in;
	end

endmodule