data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_mem.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_mem.v:85: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n          .do ({temp0, que_mem_data[63:0]}),  \n           ^~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_mem.v:85: syntax error, unexpected '(', expecting ')'\n          .do ({temp0, que_mem_data[63:0]}),  \n               ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_mem.v:120: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n          .do ({temp1, que_mem_data[127:64]}),  \n           ^~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_mem.v:120: syntax error, unexpected '(', expecting ')'\n          .do ({temp1, que_mem_data[127:64]}),  \n               ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_mem.v:138: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n          .do ({temp2, que_mem_data[191:128]}),  \n           ^~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_mem.v:138: syntax error, unexpected '(', expecting ')'\n          .do ({temp2, que_mem_data[191:128]}),  \n               ^\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_mem.v:173: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n          .do ({temp3, que_mem_data[255:192]}),  \n           ^~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/dram_mem.v:173: syntax error, unexpected '(', expecting ')'\n          .do ({temp3, que_mem_data[255:192]}),  \n               ^\n%Error: Exiting due to 8 error(s)\n"
module dram_mem (

   que_mem_data, listen_out, 

   que_mem_addr, dram_cpu_wr_addr, dram_cpu_wr_data, dram_clk, clk, 
   dram_cpu_wr_en, margin, sehold, mem_bypass
   );


output [255:0]		que_mem_data;
output [64:0]		listen_out;


input [4:0]		que_mem_addr;
input [3:0]		dram_cpu_wr_addr;
input [63:0]		dram_cpu_wr_data;
input			dram_clk;
input			clk;
input [3:0]		dram_cpu_wr_en;
input [4:0]		margin;
input			sehold;
input			mem_bypass;




wire			temp0;
wire			temp1;
wire			temp2;
wire			temp3;
wire			si;

wire [64:0]		listen_out1;
wire [64:0]		listen_out2;
wire [64:0]		listen_out3;










bw_rf_16x65 dramdatawrqent0b01(

			       .so	(so),
			       .do	({temp0, que_mem_data[63:0]}),
			       .listen_out(listen_out[64:0]),

			       .rd_clk	(dram_clk),
			       .wr_clk	(clk),
			       .csn_rd	(que_mem_addr[4]),
			       .csn_wr	(dram_cpu_wr_en[0]),
			       .hold	(sehold),
			       .testmux_sel(mem_bypass),
			       .scan_en	(1'b0),
			       .margin	(margin[4:0]),
			       .rd_a	(que_mem_addr[3:0]),
			       .wr_a	(dram_cpu_wr_addr[3:0]),
			       .di	({1'b0, dram_cpu_wr_data[63:0]}),
			       .si	(si));


bw_rf_16x65 dramdatawrqent1b01(

			       .so	(so),
			       .do	({temp1, que_mem_data[127:64]}),
			       .listen_out(listen_out1[64:0]),

			       .rd_clk	(dram_clk),
			       .wr_clk	(clk),
			       .csn_rd	(que_mem_addr[4]),
			       .csn_wr	(dram_cpu_wr_en[1]),
			       .hold	(sehold),
			       .testmux_sel(mem_bypass),
			       .scan_en	(1'b0),
			       .margin	(margin[4:0]),
			       .rd_a	(que_mem_addr[3:0]),
			       .wr_a	(dram_cpu_wr_addr[3:0]),
			       .di	({1'b0, dram_cpu_wr_data[63:0]}),
			       .si	(si));
bw_rf_16x65 dramdatawrqent2b01(

			       .so	(so),
			       .do	({temp2, que_mem_data[191:128]}),
			       .listen_out(listen_out2[64:0]),

			       .rd_clk	(dram_clk),
			       .wr_clk	(clk),
			       .csn_rd	(que_mem_addr[4]),
			       .csn_wr	(dram_cpu_wr_en[2]),
			       .hold	(sehold),
			       .testmux_sel(mem_bypass),
			       .scan_en	(1'b0),
			       .margin	(margin[4:0]),
			       .rd_a	(que_mem_addr[3:0]),
			       .wr_a	(dram_cpu_wr_addr[3:0]),
			       .di	({1'b0, dram_cpu_wr_data[63:0]}),
			       .si	(si));


bw_rf_16x65 dramdatawrqent3b01(

			       .so	(so),
			       .do	({temp3, que_mem_data[255:192]}),
			       .listen_out(listen_out3[64:0]),

			       .rd_clk	(dram_clk),
			       .wr_clk	(clk),
			       .csn_rd	(que_mem_addr[4]),
			       .csn_wr	(dram_cpu_wr_en[3]),
			       .hold	(sehold),
			       .testmux_sel(mem_bypass),
			       .scan_en	(1'b0),
			       .margin	(margin[4:0]),
			       .rd_a	(que_mem_addr[3:0]),
			       .wr_a	(dram_cpu_wr_addr[3:0]),
			       .di	({1'b0, dram_cpu_wr_data[63:0]}),
			       .si	(si));
endmodule
module dram_mem (

   que_mem_data, listen_out, 

   que_mem_addr, dram_cpu_wr_addr, dram_cpu_wr_data, dram_clk, clk, 
   dram_cpu_wr_en, margin, sehold, mem_bypass
   );



output [255:0]		que_mem_data;
output [64:0]		listen_out;


input [4:0]		que_mem_addr;
input [3:0]		dram_cpu_wr_addr;
input [63:0]		dram_cpu_wr_data;
input			dram_clk;
input			clk;
input [3:0]		dram_cpu_wr_en;
input [4:0]		margin;
input			sehold;
input			mem_bypass;




wire			temp0;
wire			temp1;
wire			temp2;
wire			temp3;
wire			si;

wire [64:0]		listen_out1;
wire [64:0]		listen_out2;
wire [64:0]		listen_out3;










bw_rf_16x65 dramdatawrqent0b01(

			       .so	(so),
			       .do	({temp0, que_mem_data[63:0]}),
			       .listen_out(listen_out[64:0]),

			       .rd_clk	(dram_clk),
			       .wr_clk	(clk),
			       .csn_rd	(que_mem_addr[4]),
			       .csn_wr	(dram_cpu_wr_en[0]),
			       .hold	(sehold),
			       .testmux_sel(mem_bypass),
			       .scan_en	(1'b0),
			       .margin	(margin[4:0]),
			       .rd_a	(que_mem_addr[3:0]),
			       .wr_a	(dram_cpu_wr_addr[3:0]),
			       .di	({1'b0, dram_cpu_wr_data[63:0]}),
			       .si	(si));


bw_rf_16x65 dramdatawrqent1b01(

			       .so	(so),
			       .do	({temp1, que_mem_data[127:64]}),
			       .listen_out(listen_out1[64:0]),

			       .rd_clk	(dram_clk),
			       .wr_clk	(clk),
			       .csn_rd	(que_mem_addr[4]),
			       .csn_wr	(dram_cpu_wr_en[1]),
			       .hold	(sehold),
			       .testmux_sel(mem_bypass),
			       .scan_en	(1'b0),
			       .margin	(margin[4:0]),
			       .rd_a	(que_mem_addr[3:0]),
			       .wr_a	(dram_cpu_wr_addr[3:0]),
			       .di	({1'b0, dram_cpu_wr_data[63:0]}),
			       .si	(si));
bw_rf_16x65 dramdatawrqent2b01(

			       .so	(so),
			       .do	({temp2, que_mem_data[191:128]}),
			       .listen_out(listen_out2[64:0]),

			       .rd_clk	(dram_clk),
			       .wr_clk	(clk),
			       .csn_rd	(que_mem_addr[4]),
			       .csn_wr	(dram_cpu_wr_en[2]),
			       .hold	(sehold),
			       .testmux_sel(mem_bypass),
			       .scan_en	(1'b0),
			       .margin	(margin[4:0]),
			       .rd_a	(que_mem_addr[3:0]),
			       .wr_a	(dram_cpu_wr_addr[3:0]),
			       .di	({1'b0, dram_cpu_wr_data[63:0]}),
			       .si	(si));


bw_rf_16x65 dramdatawrqent3b01(

			       .so	(so),
			       .do	({temp3, que_mem_data[255:192]}),
			       .listen_out(listen_out3[64:0]),

			       .rd_clk	(dram_clk),
			       .wr_clk	(clk),
			       .csn_rd	(que_mem_addr[4]),
			       .csn_wr	(dram_cpu_wr_en[3]),
			       .hold	(sehold),
			       .testmux_sel(mem_bypass),
			       .scan_en	(1'b0),
			       .margin	(margin[4:0]),
			       .rd_a	(que_mem_addr[3:0]),
			       .wr_a	(dram_cpu_wr_addr[3:0]),
			       .di	({1'b0, dram_cpu_wr_data[63:0]}),
			       .si	(si));
endmodule