data/full_repos/permissive/427221126/workspace/conv_top.sv
1: b'%Error: data/full_repos/permissive/427221126/workspace/conv_top.sv:70: Cannot find file containing module: \'rom\'\nrom u_rom(\n^~~\n        ... Looked in:\n             data/full_repos/permissive/427221126/workspace,data/full_repos/permissive/427221126/rom\n             data/full_repos/permissive/427221126/workspace,data/full_repos/permissive/427221126/rom.v\n             data/full_repos/permissive/427221126/workspace,data/full_repos/permissive/427221126/rom.sv\n             rom\n             rom.v\n             rom.sv\n             obj_dir/rom\n             obj_dir/rom.v\n             obj_dir/rom.sv\n%Error: data/full_repos/permissive/427221126/workspace/conv_top.sv:196: Cannot find file containing module: \'PE\'\nPE u_PE_1_1( \n^~\n%Error: data/full_repos/permissive/427221126/workspace/conv_top.sv:209: Cannot find file containing module: \'PE\'\nPE u_PE_2_1( \n^~\n%Error: data/full_repos/permissive/427221126/workspace/conv_top.sv:222: Cannot find file containing module: \'PE\'\nPE u_PE_3_1( \n^~\n%Error: data/full_repos/permissive/427221126/workspace/conv_top.sv:235: Cannot find file containing module: \'PE\'\nPE u_PE_3_2( \n^~\n%Error: data/full_repos/permissive/427221126/workspace/conv_top.sv:248: Cannot find file containing module: \'PE\'\nPE u_PE_3_3( \n^~\n%Error: data/full_repos/permissive/427221126/workspace/conv_top.sv:261: Cannot find file containing module: \'PE\'\nPE u_PE_3_4( \n^~\n%Error: data/full_repos/permissive/427221126/workspace/conv_top.sv:274: Cannot find file containing module: \'PE\'\nPE u_PE_3_5( \n^~\n%Error: data/full_repos/permissive/427221126/workspace/conv_top.sv:288: Cannot find file containing module: \'PE\'\nPE u_PE_2_2( \n^~\n%Error: data/full_repos/permissive/427221126/workspace/conv_top.sv:301: Cannot find file containing module: \'PE\'\nPE u_PE_2_3( \n^~\n%Error: data/full_repos/permissive/427221126/workspace/conv_top.sv:314: Cannot find file containing module: \'PE\'\nPE u_PE_2_4( \n^~\n%Error: data/full_repos/permissive/427221126/workspace/conv_top.sv:327: Cannot find file containing module: \'PE\'\nPE u_PE_2_5( \n^~\n%Error: data/full_repos/permissive/427221126/workspace/conv_top.sv:340: Cannot find file containing module: \'PE\'\nPE u_PE_1_2( \n^~\n%Error: data/full_repos/permissive/427221126/workspace/conv_top.sv:353: Cannot find file containing module: \'PE\'\nPE u_PE_1_3( \n^~\n%Error: data/full_repos/permissive/427221126/workspace/conv_top.sv:366: Cannot find file containing module: \'PE\'\nPE u_PE_1_4( \n^~\n%Error: data/full_repos/permissive/427221126/workspace/conv_top.sv:379: Cannot find file containing module: \'PE\'\nPE u_PE_1_5( \n^~\n%Error: data/full_repos/permissive/427221126/workspace/conv_top.sv:414: Unsupported: Replication to form \'logic[15:0]$[0:4]\' data type\n                                                                      : ... In instance conv_top\n    if(rst||en) data_out_series <= {0,0,0,0,0};\n                                   ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/427221126/workspace/conv_top.sv:414: Unsized numbers/parameters not allowed in concatenations.\n                                                                                    : ... In instance conv_top\n    if(rst||en) data_out_series <= {0,0,0,0,0};\n                                    ^\n                      ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message.\n%Warning-WIDTHCONCAT: data/full_repos/permissive/427221126/workspace/conv_top.sv:414: Unsized numbers/parameters not allowed in concatenations.\n                                                                                    : ... In instance conv_top\n    if(rst||en) data_out_series <= {0,0,0,0,0};\n                                     ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/427221126/workspace/conv_top.sv:414: Unsized numbers/parameters not allowed in concatenations.\n                                                                                    : ... In instance conv_top\n    if(rst||en) data_out_series <= {0,0,0,0,0};\n                                       ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/427221126/workspace/conv_top.sv:414: Unsized numbers/parameters not allowed in concatenations.\n                                                                                    : ... In instance conv_top\n    if(rst||en) data_out_series <= {0,0,0,0,0};\n                                         ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/427221126/workspace/conv_top.sv:414: Unsized numbers/parameters not allowed in replications.\n                                                                                    : ... In instance conv_top\n    if(rst||en) data_out_series <= {0,0,0,0,0};\n                                           ^\n%Error: Exiting due to 17 error(s), 5 warning(s)\n'
module conv_top  (
    input clk,rst,en,
    input     [5:0] addr,
    input           read,
    output   [15:0] DATA_OUT,
    output          VALID

);
wire   [15:0] filter_1_1 [0:2] ;
wire   [15:0] filter_1_2 [0:2] ;
wire   [15:0] filter_1_3 [0:2] ;
wire   [15:0] filter_1_4 [0:2] ;
wire   [15:0] filter_1_5 [0:2] ;
wire   [15:0] filter_2_1 [0:2] ;
wire   [15:0] filter_2_2 [0:2] ;
wire   [15:0] filter_2_3 [0:2] ;
wire   [15:0] filter_2_4 [0:2] ;
wire   [15:0] filter_2_5 [0:2] ;
wire   [15:0] filter_3_1 [0:2] ;
wire   [15:0] filter_3_2 [0:2] ;
wire   [15:0] filter_3_3 [0:2] ;
wire   [15:0] filter_3_4 [0:2] ;
wire   [15:0] filter_3_5 [0:2] ;

wire   [15:0] data_1_1 [0:6] ;
wire   [15:0] data_1_2 [0:6] ;
wire   [15:0] data_1_3 [0:6] ;
wire   [15:0] data_1_4 [0:6] ;
wire   [15:0] data_1_5 [0:6] ;
wire   [15:0] data_2_1 [0:6] ;
wire   [15:0] data_2_2 [0:6] ;
wire   [15:0] data_2_3 [0:6] ;
wire   [15:0] data_2_4 [0:6] ;
wire   [15:0] data_2_5 [0:6] ;
wire   [15:0] data_3_1 [0:6] ;
wire   [15:0] data_3_2 [0:6] ;
wire   [15:0] data_3_3 [0:6] ;
wire   [15:0] data_3_4 [0:6] ;
wire   [15:0] data_3_5 [0:6] ;

wire   [15:0] psum_1_1 [0:4] ;
wire   [15:0] psum_1_2 [0:4] ;
wire   [15:0] psum_1_3 [0:4] ;
wire   [15:0] psum_1_4 [0:4] ;
wire   [15:0] psum_1_5 [0:4] ;
wire   [15:0] psum_2_1 [0:4] ;
wire   [15:0] psum_2_2 [0:4] ;
wire   [15:0] psum_2_3 [0:4] ;
wire   [15:0] psum_2_4 [0:4] ;
wire   [15:0] psum_2_5 [0:4] ;
wire   [15:0] psum_3_1 [0:4] ;
wire   [15:0] psum_3_2 [0:4] ;
wire   [15:0] psum_3_3 [0:4] ;
wire   [15:0] psum_3_4 [0:4] ;
wire   [15:0] psum_3_5 [0:4] ;

wire    done_1_1,done_1_2,done_1_3,done_1_4,done_1_5,
        done_2_1,done_2_2,done_2_3,done_2_4,done_2_5,
        done_3_1,done_3_2,done_3_3,done_3_4,done_3_5;

reg en1,en2,en3,en4,en5,en6,en7;

reg [15:0]filter_buff[0:2];
reg [15:0]data_buff[0:6];

wire    [15:0]data_in;
reg     [15:0]data_out;

rom u_rom(
    .clk(clk),
    .rst(rst),
    .addr(addr),
    .read(read),
    .dout(data_in)  
);

wire en_c;
reg en_d,en_dd;
reg [3:0]counter;

always @(posedge clk) begin
    en_d <= en;
    en_dd <= en_d;
end
assign en_c = en_dd||en1||en2||en3||en4||en5||en6||en7;

always @(posedge clk) begin
    if(rst||en_c) counter <= 0;
    else  counter <= counter + 1;
end












always @(posedge clk) begin
    if(rst||en) begin
    data_buff[0] <= 16'd0;
    data_buff[1] <= 16'd0;
    data_buff[2] <= 16'd0;
    data_buff[3] <= 16'd0;
    data_buff[4] <= 16'd0;
    data_buff[5] <= 16'd0;
    data_buff[6] <= 16'd0;
    filter_buff[0] <= 16'd0;
    filter_buff[1] <= 16'd0;
    filter_buff[2] <= 16'd0;        
    end

    else if(counter < 7) begin
        data_buff[0] <= data_buff[1];
        data_buff[1] <= data_buff[2];
        data_buff[2] <= data_buff[3];
        data_buff[3] <= data_buff[4];
        data_buff[4] <= data_buff[5];
        data_buff[5] <= data_buff[6];
        data_buff[6] <= data_in;
    end
    else if(counter < 10) begin
        filter_buff[0] <= filter_buff[1];
        filter_buff[1] <= filter_buff[2];
        filter_buff[2] <= data_in;       
    end
end


reg [3:0] state,state_next;
parameter   IDLE = 4'd0,
            READ1 = 4'd1,
            READ2 = 4'd2,
            READ3 = 4'd3,
            READ4 = 4'd4,
            READ5 = 4'd5,
            READ6 = 4'd6,
            READ7 = 4'd7,
            COMP  = 4'd8,
            OUPT  = 4'd9;

always @(posedge clk) begin
    if(rst)
    state <= IDLE;
    else
    state <= state_next;
end

always @(*) begin
    if(rst)
    state_next = IDLE;
    else begin
    case (state)
        IDLE: if(en) state_next = READ1; 
        READ1: if(counter == 10) state_next = READ2;
        READ2: if(counter == 10) state_next = READ3;
        READ3: if(counter == 10) state_next = READ4;
        READ4: if(counter == 7)  state_next = READ5;
        READ5: if(counter == 7)  state_next = READ6;
        READ6: if(counter == 7) state_next = READ7;
        READ7: if(counter == 7) state_next = COMP;
        COMP:if(done_1_5) state_next = OUPT;
        OUPT: state_next = IDLE;
        default: state_next = IDLE;
    endcase
    end
end

always @(posedge clk) begin
    if(rst||en) begin
        en1 <= 0;
        en2 <= 0;
        en3 <= 0;
        en4 <= 0;
        en5 <= 0;
        en6 <= 0;
        en7 <= 0;
    end
    else begin
     en1 <= (state == READ1 && state_next == READ2);
     en2 <= (state == READ2 && state_next == READ3);
     en3 <= (state == READ3 && state_next == READ4);
     en4 <= (state == READ4 && state_next == READ5);
     en5 <= (state == READ5 && state_next == READ6);
     en6 <= (state == READ6 && state_next == READ7);
     en7 <= (state == READ7 && state_next == COMP);
    end
end


PE u_PE_1_1( 
    .clk(clk),
    .rst(rst),
    .en(en3),
    .FILTER_IN(filter_buff), 
    .DATA_IN(data_buff),
    .PSUM_IN(psum_2_1),
    .FILTER_OUT(filter_1_1),
    .DATA_OUT(data_1_1),
    .PSUM_OUT(psum_1_1),
    .DONE(done_1_1)
);

PE u_PE_2_1( 
    .clk(clk),
    .rst(rst),
    .en(en2),
    .FILTER_IN(filter_buff),
    .DATA_IN(data_buff),
    .PSUM_IN(psum_3_1),
    .FILTER_OUT(filter_2_1),
    .DATA_OUT(data_2_1),
    .PSUM_OUT(psum_2_1),
    .DONE(done_2_1)
);

PE u_PE_3_1( 
    .clk(clk),
    .rst(rst),
    .en(en1),
    .FILTER_IN(filter_buff),
    .DATA_IN(data_buff),
    .PSUM_IN({16'd0,16'd0,16'd0,16'd0,16'd0}),
    .FILTER_OUT(filter_3_1),
    .DATA_OUT(data_3_1),
    .PSUM_OUT(psum_3_1),
    .DONE(done_3_1)
);

PE u_PE_3_2( 
    .clk(clk),
    .rst(rst),
    .en(en4),
    .FILTER_IN(filter_3_1),
    .DATA_IN(data_buff),
    .PSUM_IN({16'd0,16'd0,16'd0,16'd0,16'd0}),
    .FILTER_OUT(filter_3_2),
    .DATA_OUT(data_3_2),
    .PSUM_OUT(psum_3_2),
    .DONE(done_3_2)
);

PE u_PE_3_3( 
    .clk(clk),
    .rst(rst),
    .en(en5),
    .FILTER_IN(filter_3_2),
    .DATA_IN(data_buff),
    .PSUM_IN({16'd0,16'd0,16'd0,16'd0,16'd0}),
    .FILTER_OUT(filter_3_3),
    .DATA_OUT(data_3_3),
    .PSUM_OUT(psum_3_3),
    .DONE(done_3_3)
);

PE u_PE_3_4( 
    .clk(clk),
    .rst(rst),
    .en(en6),
    .FILTER_IN(filter_3_3),
    .DATA_IN(data_buff),
    .PSUM_IN({16'd0,16'd0,16'd0,16'd0,16'd0}),
    .FILTER_OUT(filter_3_4),
    .DATA_OUT(data_3_4),
    .PSUM_OUT(psum_3_4),
    .DONE(done_3_4)
);

PE u_PE_3_5( 
    .clk(clk),
    .rst(rst),
    .en(en7),
    .FILTER_IN(filter_3_4),
    .DATA_IN(data_buff),
    .PSUM_IN({16'd0,16'd0,16'd0,16'd0,16'd0}),
    .FILTER_OUT(filter_3_5),
    .DATA_OUT(data_3_5),
    .PSUM_OUT(psum_3_5),
    .DONE(done_3_5)
);


PE u_PE_2_2( 
    .clk(clk),
    .rst(rst),
    .en(en5),
    .FILTER_IN(filter_2_1),
    .DATA_IN(data_3_1),
    .PSUM_IN(psum_3_2),
    .FILTER_OUT(filter_2_2),
    .DATA_OUT(data_2_2),
    .PSUM_OUT(psum_2_2),
    .DONE(done_2_2)
);

PE u_PE_2_3( 
    .clk(clk),
    .rst(rst),
    .en(en6),
    .FILTER_IN(filter_2_2),
    .DATA_IN(data_3_2),
    .PSUM_IN(psum_3_3),
    .FILTER_OUT(filter_2_3),
    .DATA_OUT(data_2_3),
    .PSUM_OUT(psum_2_3),
    .DONE(done_2_3)
);

PE u_PE_2_4( 
    .clk(clk),
    .rst(rst),
    .en(en7),
    .FILTER_IN(filter_2_3),
    .DATA_IN(data_3_3),
    .PSUM_IN(psum_3_4),
    .FILTER_OUT(filter_2_4),
    .DATA_OUT(data_2_4),
    .PSUM_OUT(psum_2_4),
    .DONE(done_2_4)
);

PE u_PE_2_5( 
    .clk(clk),
    .rst(rst),
    .en(done_2_4 && done_3_5),
    .FILTER_IN(filter_2_4),
    .DATA_IN(data_3_4),
    .PSUM_IN(psum_3_5),
    .FILTER_OUT(filter_2_5),
    .DATA_OUT(data_2_5),
    .PSUM_OUT(psum_2_5),
    .DONE(done_2_5)
);

PE u_PE_1_2( 
    .clk(clk),
    .rst(rst),
    .en(en6),
    .FILTER_IN(filter_1_1),
    .DATA_IN(data_2_1),
    .PSUM_IN(psum_2_2),
    .FILTER_OUT(filter_1_2),
    .DATA_OUT(data_1_2),
    .PSUM_OUT(psum_1_2),
    .DONE(done_1_2)
);

PE u_PE_1_3( 
    .clk(clk),
    .rst(rst),
    .en(en7),
    .FILTER_IN(filter_1_2),
    .DATA_IN(data_2_2),
    .PSUM_IN(psum_2_3),
    .FILTER_OUT(filter_1_3),
    .DATA_OUT(data_1_3),
    .PSUM_OUT(psum_1_3),
    .DONE(done_1_3)
);

PE u_PE_1_4( 
    .clk(clk),
    .rst(rst),
    .en(done_1_3 && done_2_4),
    .FILTER_IN(filter_1_3),
    .DATA_IN(data_2_3),
    .PSUM_IN(psum_2_4),
    .FILTER_OUT(filter_1_4),
    .DATA_OUT(data_1_4),
    .PSUM_OUT(psum_1_4),
    .DONE(done_1_4)
);

PE u_PE_1_5( 
    .clk(clk),
    .rst(rst),
    .en(done_1_4 && done_2_5),
    .FILTER_IN(filter_1_4),
    .DATA_IN(data_2_4),
    .PSUM_IN(psum_2_5),
    .FILTER_OUT(filter_1_5),
    .DATA_OUT(data_1_5),
    .PSUM_OUT(psum_1_5),
    .DONE(done_1_5)
);





















reg [15:0] data_out_series [0:4];
always @(posedge clk) begin
    if(rst||en) data_out_series <= {0,0,0,0,0};
    else if(done_1_1)
    data_out_series <= psum_1_1;
    else if(done_1_2)
    data_out_series <= psum_1_2;
    else if(done_1_3)
    data_out_series <= psum_1_3;
    else if(done_1_4)
    data_out_series <= psum_1_4;
    else if(done_1_5)
    data_out_series <= psum_1_5;
end


reg [4:0]num1;
reg [2:0]num2;
wire valid;
always @(posedge clk) begin
    if(rst||en) begin    num1 <=0; num2<=0;    end
        else if(done_1_1||done_1_2||done_1_3||done_1_4||done_1_5) begin num1 <=0; num2 <= num2+1; end
    else    begin
        num1 <= num1 + 1;
    if(num2==1) begin
        case (num1)
            1: begin data_out <= psum_1_1[0]; end
            2: data_out <= psum_1_1[1]; 
            3: data_out <= psum_1_1[2]; 
            4: data_out <= psum_1_1[3]; 
            5: data_out <= psum_1_1[4]; 
            default: data_out <= 16'h0000;
        endcase
    end
    else if(num2==2) begin
        case (num1)
            1: begin data_out <= psum_1_2[0]; end
            2: data_out <= psum_1_2[1]; 
            3: data_out <= psum_1_2[2]; 
            4: data_out <= psum_1_2[3]; 
            5: data_out <= psum_1_2[4]; 
            default: data_out <= 16'h0000;
        endcase
    end
    else if(num2==3) begin
        case (num1)
            1: begin data_out <= psum_1_3[0];  end
            2: data_out <= psum_1_3[1]; 
            3: data_out <= psum_1_3[2]; 
            4: data_out <= psum_1_3[3]; 
            5: data_out <= psum_1_3[4]; 
            default: data_out <= 16'h0000;
        endcase
    end
    else if(num2==4) begin
        case (num1)
            1: begin data_out <= psum_1_4[0];  end
            2: data_out <= psum_1_4[1]; 
            3: data_out <= psum_1_4[2]; 
            4: data_out <= psum_1_4[3]; 
            5: data_out <= psum_1_4[4]; 

            default: data_out <= 16'h0000;
        endcase
    end
    if(num2==5) begin
        case (num1)
            1: begin data_out <= psum_1_5[0];  end
            2: data_out <= psum_1_5[1]; 
            3: data_out <= psum_1_5[2]; 
            4: data_out <= psum_1_5[3]; 
            5: data_out <= psum_1_5[4]; 
            default: data_out <= 16'h0000;
        endcase
    end
    end
end
assign valid = (num1==2||num1==3||num1==4||num1==5||num1==6);


assign DATA_OUT = data_out;
assign VALID = valid;
endmodule
module conv_top  (
    input clk,rst,en,
    input     [5:0] addr,
    input           read,
    output   [15:0] DATA_OUT,
    output          VALID

);

wire   [15:0] filter_1_1 [0:2] ;
wire   [15:0] filter_1_2 [0:2] ;
wire   [15:0] filter_1_3 [0:2] ;
wire   [15:0] filter_1_4 [0:2] ;
wire   [15:0] filter_1_5 [0:2] ;
wire   [15:0] filter_2_1 [0:2] ;
wire   [15:0] filter_2_2 [0:2] ;
wire   [15:0] filter_2_3 [0:2] ;
wire   [15:0] filter_2_4 [0:2] ;
wire   [15:0] filter_2_5 [0:2] ;
wire   [15:0] filter_3_1 [0:2] ;
wire   [15:0] filter_3_2 [0:2] ;
wire   [15:0] filter_3_3 [0:2] ;
wire   [15:0] filter_3_4 [0:2] ;
wire   [15:0] filter_3_5 [0:2] ;

wire   [15:0] data_1_1 [0:6] ;
wire   [15:0] data_1_2 [0:6] ;
wire   [15:0] data_1_3 [0:6] ;
wire   [15:0] data_1_4 [0:6] ;
wire   [15:0] data_1_5 [0:6] ;
wire   [15:0] data_2_1 [0:6] ;
wire   [15:0] data_2_2 [0:6] ;
wire   [15:0] data_2_3 [0:6] ;
wire   [15:0] data_2_4 [0:6] ;
wire   [15:0] data_2_5 [0:6] ;
wire   [15:0] data_3_1 [0:6] ;
wire   [15:0] data_3_2 [0:6] ;
wire   [15:0] data_3_3 [0:6] ;
wire   [15:0] data_3_4 [0:6] ;
wire   [15:0] data_3_5 [0:6] ;

wire   [15:0] psum_1_1 [0:4] ;
wire   [15:0] psum_1_2 [0:4] ;
wire   [15:0] psum_1_3 [0:4] ;
wire   [15:0] psum_1_4 [0:4] ;
wire   [15:0] psum_1_5 [0:4] ;
wire   [15:0] psum_2_1 [0:4] ;
wire   [15:0] psum_2_2 [0:4] ;
wire   [15:0] psum_2_3 [0:4] ;
wire   [15:0] psum_2_4 [0:4] ;
wire   [15:0] psum_2_5 [0:4] ;
wire   [15:0] psum_3_1 [0:4] ;
wire   [15:0] psum_3_2 [0:4] ;
wire   [15:0] psum_3_3 [0:4] ;
wire   [15:0] psum_3_4 [0:4] ;
wire   [15:0] psum_3_5 [0:4] ;

wire    done_1_1,done_1_2,done_1_3,done_1_4,done_1_5,
        done_2_1,done_2_2,done_2_3,done_2_4,done_2_5,
        done_3_1,done_3_2,done_3_3,done_3_4,done_3_5;

reg en1,en2,en3,en4,en5,en6,en7;

reg [15:0]filter_buff[0:2];
reg [15:0]data_buff[0:6];

wire    [15:0]data_in;
reg     [15:0]data_out;

rom u_rom(
    .clk(clk),
    .rst(rst),
    .addr(addr),
    .read(read),
    .dout(data_in)  
);

wire en_c;
reg en_d,en_dd;
reg [3:0]counter;

always @(posedge clk) begin
    en_d <= en;
    en_dd <= en_d;
end
assign en_c = en_dd||en1||en2||en3||en4||en5||en6||en7;

always @(posedge clk) begin
    if(rst||en_c) counter <= 0;
    else  counter <= counter + 1;
end












always @(posedge clk) begin
    if(rst||en) begin
    data_buff[0] <= 16'd0;
    data_buff[1] <= 16'd0;
    data_buff[2] <= 16'd0;
    data_buff[3] <= 16'd0;
    data_buff[4] <= 16'd0;
    data_buff[5] <= 16'd0;
    data_buff[6] <= 16'd0;
    filter_buff[0] <= 16'd0;
    filter_buff[1] <= 16'd0;
    filter_buff[2] <= 16'd0;        
    end

    else if(counter < 7) begin
        data_buff[0] <= data_buff[1];
        data_buff[1] <= data_buff[2];
        data_buff[2] <= data_buff[3];
        data_buff[3] <= data_buff[4];
        data_buff[4] <= data_buff[5];
        data_buff[5] <= data_buff[6];
        data_buff[6] <= data_in;
    end
    else if(counter < 10) begin
        filter_buff[0] <= filter_buff[1];
        filter_buff[1] <= filter_buff[2];
        filter_buff[2] <= data_in;       
    end
end


reg [3:0] state,state_next;
parameter   IDLE = 4'd0,
            READ1 = 4'd1,
            READ2 = 4'd2,
            READ3 = 4'd3,
            READ4 = 4'd4,
            READ5 = 4'd5,
            READ6 = 4'd6,
            READ7 = 4'd7,
            COMP  = 4'd8,
            OUPT  = 4'd9;

always @(posedge clk) begin
    if(rst)
    state <= IDLE;
    else
    state <= state_next;
end

always @(*) begin
    if(rst)
    state_next = IDLE;
    else begin
    case (state)
        IDLE: if(en) state_next = READ1; 
        READ1: if(counter == 10) state_next = READ2;
        READ2: if(counter == 10) state_next = READ3;
        READ3: if(counter == 10) state_next = READ4;
        READ4: if(counter == 7)  state_next = READ5;
        READ5: if(counter == 7)  state_next = READ6;
        READ6: if(counter == 7) state_next = READ7;
        READ7: if(counter == 7) state_next = COMP;
        COMP:if(done_1_5) state_next = OUPT;
        OUPT: state_next = IDLE;
        default: state_next = IDLE;
    endcase
    end
end

always @(posedge clk) begin
    if(rst||en) begin
        en1 <= 0;
        en2 <= 0;
        en3 <= 0;
        en4 <= 0;
        en5 <= 0;
        en6 <= 0;
        en7 <= 0;
    end
    else begin
     en1 <= (state == READ1 && state_next == READ2);
     en2 <= (state == READ2 && state_next == READ3);
     en3 <= (state == READ3 && state_next == READ4);
     en4 <= (state == READ4 && state_next == READ5);
     en5 <= (state == READ5 && state_next == READ6);
     en6 <= (state == READ6 && state_next == READ7);
     en7 <= (state == READ7 && state_next == COMP);
    end
end


PE u_PE_1_1( 
    .clk(clk),
    .rst(rst),
    .en(en3),
    .FILTER_IN(filter_buff), 
    .DATA_IN(data_buff),
    .PSUM_IN(psum_2_1),
    .FILTER_OUT(filter_1_1),
    .DATA_OUT(data_1_1),
    .PSUM_OUT(psum_1_1),
    .DONE(done_1_1)
);

PE u_PE_2_1( 
    .clk(clk),
    .rst(rst),
    .en(en2),
    .FILTER_IN(filter_buff),
    .DATA_IN(data_buff),
    .PSUM_IN(psum_3_1),
    .FILTER_OUT(filter_2_1),
    .DATA_OUT(data_2_1),
    .PSUM_OUT(psum_2_1),
    .DONE(done_2_1)
);

PE u_PE_3_1( 
    .clk(clk),
    .rst(rst),
    .en(en1),
    .FILTER_IN(filter_buff),
    .DATA_IN(data_buff),
    .PSUM_IN({16'd0,16'd0,16'd0,16'd0,16'd0}),
    .FILTER_OUT(filter_3_1),
    .DATA_OUT(data_3_1),
    .PSUM_OUT(psum_3_1),
    .DONE(done_3_1)
);

PE u_PE_3_2( 
    .clk(clk),
    .rst(rst),
    .en(en4),
    .FILTER_IN(filter_3_1),
    .DATA_IN(data_buff),
    .PSUM_IN({16'd0,16'd0,16'd0,16'd0,16'd0}),
    .FILTER_OUT(filter_3_2),
    .DATA_OUT(data_3_2),
    .PSUM_OUT(psum_3_2),
    .DONE(done_3_2)
);

PE u_PE_3_3( 
    .clk(clk),
    .rst(rst),
    .en(en5),
    .FILTER_IN(filter_3_2),
    .DATA_IN(data_buff),
    .PSUM_IN({16'd0,16'd0,16'd0,16'd0,16'd0}),
    .FILTER_OUT(filter_3_3),
    .DATA_OUT(data_3_3),
    .PSUM_OUT(psum_3_3),
    .DONE(done_3_3)
);

PE u_PE_3_4( 
    .clk(clk),
    .rst(rst),
    .en(en6),
    .FILTER_IN(filter_3_3),
    .DATA_IN(data_buff),
    .PSUM_IN({16'd0,16'd0,16'd0,16'd0,16'd0}),
    .FILTER_OUT(filter_3_4),
    .DATA_OUT(data_3_4),
    .PSUM_OUT(psum_3_4),
    .DONE(done_3_4)
);

PE u_PE_3_5( 
    .clk(clk),
    .rst(rst),
    .en(en7),
    .FILTER_IN(filter_3_4),
    .DATA_IN(data_buff),
    .PSUM_IN({16'd0,16'd0,16'd0,16'd0,16'd0}),
    .FILTER_OUT(filter_3_5),
    .DATA_OUT(data_3_5),
    .PSUM_OUT(psum_3_5),
    .DONE(done_3_5)
);


PE u_PE_2_2( 
    .clk(clk),
    .rst(rst),
    .en(en5),
    .FILTER_IN(filter_2_1),
    .DATA_IN(data_3_1),
    .PSUM_IN(psum_3_2),
    .FILTER_OUT(filter_2_2),
    .DATA_OUT(data_2_2),
    .PSUM_OUT(psum_2_2),
    .DONE(done_2_2)
);

PE u_PE_2_3( 
    .clk(clk),
    .rst(rst),
    .en(en6),
    .FILTER_IN(filter_2_2),
    .DATA_IN(data_3_2),
    .PSUM_IN(psum_3_3),
    .FILTER_OUT(filter_2_3),
    .DATA_OUT(data_2_3),
    .PSUM_OUT(psum_2_3),
    .DONE(done_2_3)
);

PE u_PE_2_4( 
    .clk(clk),
    .rst(rst),
    .en(en7),
    .FILTER_IN(filter_2_3),
    .DATA_IN(data_3_3),
    .PSUM_IN(psum_3_4),
    .FILTER_OUT(filter_2_4),
    .DATA_OUT(data_2_4),
    .PSUM_OUT(psum_2_4),
    .DONE(done_2_4)
);

PE u_PE_2_5( 
    .clk(clk),
    .rst(rst),
    .en(done_2_4 && done_3_5),
    .FILTER_IN(filter_2_4),
    .DATA_IN(data_3_4),
    .PSUM_IN(psum_3_5),
    .FILTER_OUT(filter_2_5),
    .DATA_OUT(data_2_5),
    .PSUM_OUT(psum_2_5),
    .DONE(done_2_5)
);

PE u_PE_1_2( 
    .clk(clk),
    .rst(rst),
    .en(en6),
    .FILTER_IN(filter_1_1),
    .DATA_IN(data_2_1),
    .PSUM_IN(psum_2_2),
    .FILTER_OUT(filter_1_2),
    .DATA_OUT(data_1_2),
    .PSUM_OUT(psum_1_2),
    .DONE(done_1_2)
);

PE u_PE_1_3( 
    .clk(clk),
    .rst(rst),
    .en(en7),
    .FILTER_IN(filter_1_2),
    .DATA_IN(data_2_2),
    .PSUM_IN(psum_2_3),
    .FILTER_OUT(filter_1_3),
    .DATA_OUT(data_1_3),
    .PSUM_OUT(psum_1_3),
    .DONE(done_1_3)
);

PE u_PE_1_4( 
    .clk(clk),
    .rst(rst),
    .en(done_1_3 && done_2_4),
    .FILTER_IN(filter_1_3),
    .DATA_IN(data_2_3),
    .PSUM_IN(psum_2_4),
    .FILTER_OUT(filter_1_4),
    .DATA_OUT(data_1_4),
    .PSUM_OUT(psum_1_4),
    .DONE(done_1_4)
);

PE u_PE_1_5( 
    .clk(clk),
    .rst(rst),
    .en(done_1_4 && done_2_5),
    .FILTER_IN(filter_1_4),
    .DATA_IN(data_2_4),
    .PSUM_IN(psum_2_5),
    .FILTER_OUT(filter_1_5),
    .DATA_OUT(data_1_5),
    .PSUM_OUT(psum_1_5),
    .DONE(done_1_5)
);





















reg [15:0] data_out_series [0:4];
always @(posedge clk) begin
    if(rst||en) data_out_series <= {0,0,0,0,0};
    else if(done_1_1)
    data_out_series <= psum_1_1;
    else if(done_1_2)
    data_out_series <= psum_1_2;
    else if(done_1_3)
    data_out_series <= psum_1_3;
    else if(done_1_4)
    data_out_series <= psum_1_4;
    else if(done_1_5)
    data_out_series <= psum_1_5;
end


reg [4:0]num1;
reg [2:0]num2;
wire valid;
always @(posedge clk) begin
    if(rst||en) begin    num1 <=0; num2<=0;    end
        else if(done_1_1||done_1_2||done_1_3||done_1_4||done_1_5) begin num1 <=0; num2 <= num2+1; end
    else    begin
        num1 <= num1 + 1;
    if(num2==1) begin
        case (num1)
            1: begin data_out <= psum_1_1[0]; end
            2: data_out <= psum_1_1[1]; 
            3: data_out <= psum_1_1[2]; 
            4: data_out <= psum_1_1[3]; 
            5: data_out <= psum_1_1[4]; 
            default: data_out <= 16'h0000;
        endcase
    end
    else if(num2==2) begin
        case (num1)
            1: begin data_out <= psum_1_2[0]; end
            2: data_out <= psum_1_2[1]; 
            3: data_out <= psum_1_2[2]; 
            4: data_out <= psum_1_2[3]; 
            5: data_out <= psum_1_2[4]; 
            default: data_out <= 16'h0000;
        endcase
    end
    else if(num2==3) begin
        case (num1)
            1: begin data_out <= psum_1_3[0];  end
            2: data_out <= psum_1_3[1]; 
            3: data_out <= psum_1_3[2]; 
            4: data_out <= psum_1_3[3]; 
            5: data_out <= psum_1_3[4]; 
            default: data_out <= 16'h0000;
        endcase
    end
    else if(num2==4) begin
        case (num1)
            1: begin data_out <= psum_1_4[0];  end
            2: data_out <= psum_1_4[1]; 
            3: data_out <= psum_1_4[2]; 
            4: data_out <= psum_1_4[3]; 
            5: data_out <= psum_1_4[4]; 

            default: data_out <= 16'h0000;
        endcase
    end
    if(num2==5) begin
        case (num1)
            1: begin data_out <= psum_1_5[0];  end
            2: data_out <= psum_1_5[1]; 
            3: data_out <= psum_1_5[2]; 
            4: data_out <= psum_1_5[3]; 
            5: data_out <= psum_1_5[4]; 
            default: data_out <= 16'h0000;
        endcase
    end
    end
end
assign valid = (num1==2||num1==3||num1==4||num1==5||num1==6);


assign DATA_OUT = data_out;
assign VALID = valid;
endmodule