data/full_repos/permissive/52703097/shifter.test.v
1: b'%Error: data/full_repos/permissive/52703097/shifter.test.v:1: Cannot find include file: shifter.v\n`include "shifter.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52703097,data/full_repos/permissive/52703097/shifter.v\n             data/full_repos/permissive/52703097,data/full_repos/permissive/52703097/shifter.v.v\n             data/full_repos/permissive/52703097,data/full_repos/permissive/52703097/shifter.v.sv\n             shifter.v\n             shifter.v.v\n             shifter.v.sv\n             obj_dir/shifter.v\n             obj_dir/shifter.v.v\n             obj_dir/shifter.v.sv\n%Error: data/full_repos/permissive/52703097/shifter.test.v:9: Define or directive not defined: \'`WIDTH\'\n    reg[`WIDTH-1:0] data;\n        ^~~~~~\n%Error: data/full_repos/permissive/52703097/shifter.test.v:10: Define or directive not defined: \'`SHIFT_WIDTH\'\n    reg[`SHIFT_WIDTH-1:0] shift;\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/52703097/shifter.test.v:11: Define or directive not defined: \'`OPS\'\n    reg[`OPS-1:0] op;\n        ^~~~\n%Error: data/full_repos/permissive/52703097/shifter.test.v:12: Define or directive not defined: \'`WIDTH\'\n    wire[`WIDTH-1:0] result;\n         ^~~~~~\n%Error: data/full_repos/permissive/52703097/shifter.test.v:13: Define or directive not defined: \'`WIDTH\'\n    reg[`WIDTH-1:0] corr_result;\n        ^~~~~~\n%Error: data/full_repos/permissive/52703097/shifter.test.v:14: Define or directive not defined: \'`WIDTH\'\n    reg[`WIDTH-1:0] test_vals[0:32-1];\n        ^~~~~~\n%Error: data/full_repos/permissive/52703097/shifter.test.v:15: Define or directive not defined: \'`SHIFT_WIDTH\'\n    reg[`SHIFT_WIDTH-1:0] test_shifts[0:32-1];\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/52703097/shifter.test.v:18: Define or directive not defined: \'`WIDTH\'\n    reg[`WIDTH-1:0] tests;\n        ^~~~~~\n%Error: data/full_repos/permissive/52703097/shifter.test.v:21: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("dump.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/52703097/shifter.test.v:22: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars;\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/52703097/shifter.test.v:40: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk_reg <= ~clk_reg;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/52703097/shifter.test.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #2 start <= 1\'b0;\n        ^\n%Error: data/full_repos/permissive/52703097/shifter.test.v:56: Define or directive not defined: \'`LEFT_SHIFTA\'\n            `LEFT_SHIFTA: corr_result <= $signed(test_vals[tests]) <<< test_shifts[tests];\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/52703097/shifter.test.v:56: syntax error, unexpected \':\', expecting endcase\n            `LEFT_SHIFTA: corr_result <= $signed(test_vals[tests]) <<< test_shifts[tests];\n                        ^\n%Error: data/full_repos/permissive/52703097/shifter.test.v:57: Define or directive not defined: \'`LEFT_SHIFTL\'\n            `LEFT_SHIFTL: corr_result <= test_vals[tests] << test_shifts[tests];\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/52703097/shifter.test.v:58: Define or directive not defined: \'`RIGHT_SHIFTA\'\n            `RIGHT_SHIFTA: corr_result <= $signed(test_vals[tests]) >>> test_shifts[tests];\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/52703097/shifter.test.v:59: Define or directive not defined: \'`RIGHT_SHIFTL\'\n            `RIGHT_SHIFTL: corr_result <= test_vals[tests] >> test_shifts[tests];\n            ^~~~~~~~~~~~~\n%Error: Exiting due to 16 error(s), 2 warning(s)\n'
module test;

    reg[`WIDTH-1:0] data;
    reg[`SHIFT_WIDTH-1:0] shift;
    reg[`OPS-1:0] op;
    wire[`WIDTH-1:0] result;
    reg[`WIDTH-1:0] corr_result;
    reg[`WIDTH-1:0] test_vals[0:`TESTS-1];
    reg[`SHIFT_WIDTH-1:0] test_shifts[0:`TESTS-1];
    reg start;
    
    reg[`WIDTH-1:0] tests;

    initial begin
        $dumpfile("dump.vcd");
        $dumpvars;
        data = $random;
        op = 2'b00;
        for (tests = 0; tests < `TESTS; ++tests) begin
            test_vals[tests] = $random;
            test_shifts[tests] = $random % 32;
        end

        data = 0;
        shift = test_shifts[0];
        tests = 0;
        start = 1'b0;
    end

    reg clk_reg = 1'b0;
    wire clk;
    assign clk = clk_reg;

    always #5 clk_reg <= ~clk_reg;

    shifter uut(data, shift, op, start, result);

    always @(negedge clk) begin
        #2 start <= 1'b0;
        if (corr_result != result)
            $display("Invalid result : expected - %d, got - %d", corr_result, result);
    end

    always @(posedge clk) begin
        tests <= tests + 1;
        data <= test_vals[tests];
        shift <= test_shifts[tests];
        start <= 1'b1;
        case (op)
            `LEFT_SHIFTA: corr_result <= $signed(test_vals[tests]) <<< test_shifts[tests];
            `LEFT_SHIFTL: corr_result <= test_vals[tests] << test_shifts[tests];
            `RIGHT_SHIFTA: corr_result <= $signed(test_vals[tests]) >>> test_shifts[tests];
            `RIGHT_SHIFTL: corr_result <= test_vals[tests] >> test_shifts[tests];
            default: $display("Invalid op");
        endcase
        if (tests >= `TESTS-1)
            #20 $finish;
    end
endmodule
module test;


    reg[`WIDTH-1:0] data;
    reg[`SHIFT_WIDTH-1:0] shift;
    reg[`OPS-1:0] op;
    wire[`WIDTH-1:0] result;
    reg[`WIDTH-1:0] corr_result;
    reg[`WIDTH-1:0] test_vals[0:`TESTS-1];
    reg[`SHIFT_WIDTH-1:0] test_shifts[0:`TESTS-1];
    reg start;
    
    reg[`WIDTH-1:0] tests;

    initial begin
        $dumpfile("dump.vcd");
        $dumpvars;
        data = $random;
        op = 2'b00;
        for (tests = 0; tests < `TESTS; ++tests) begin
            test_vals[tests] = $random;
            test_shifts[tests] = $random % 32;
        end

        data = 0;
        shift = test_shifts[0];
        tests = 0;
        start = 1'b0;
    end

    reg clk_reg = 1'b0;
    wire clk;
    assign clk = clk_reg;

    always #5 clk_reg <= ~clk_reg;

    shifter uut(data, shift, op, start, result);

    always @(negedge clk) begin
        #2 start <= 1'b0;
        if (corr_result != result)
            $display("Invalid result : expected - %d, got - %d", corr_result, result);
    end

    always @(posedge clk) begin
        tests <= tests + 1;
        data <= test_vals[tests];
        shift <= test_shifts[tests];
        start <= 1'b1;
        case (op)
            `LEFT_SHIFTA: corr_result <= $signed(test_vals[tests]) <<< test_shifts[tests];
            `LEFT_SHIFTL: corr_result <= test_vals[tests] << test_shifts[tests];
            `RIGHT_SHIFTA: corr_result <= $signed(test_vals[tests]) >>> test_shifts[tests];
            `RIGHT_SHIFTL: corr_result <= test_vals[tests] >> test_shifts[tests];
            default: $display("Invalid op");
        endcase
        if (tests >= `TESTS-1)
            #20 $finish;
    end
endmodule