data/full_repos/permissive/48602886/sim/model/sim_uart_receiver_model/sim_uart_receiver_model.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/48602886/sim/model/sim_uart_receiver_model/sim_uart_receiver_model.sv:22: Unsupported: Ignoring delay on this delayed statement.\n always#(base_latency/2)begin\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/48602886/sim/model/sim_uart_receiver_model/sim_uart_receiver_model.sv:39: Unsupported: Ignoring delay on this delayed statement.\n    #(base_latency);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/48602886/sim/model/sim_uart_receiver_model/sim_uart_receiver_model.sv:42: Unsupported: Ignoring delay on this delayed statement.\n    #(base_latency);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/48602886/sim/model/sim_uart_receiver_model/sim_uart_receiver_model.sv:45: Unsupported: Ignoring delay on this delayed statement.\n    #(base_latency);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/48602886/sim/model/sim_uart_receiver_model/sim_uart_receiver_model.sv:48: Unsupported: Ignoring delay on this delayed statement.\n    #(base_latency);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/48602886/sim/model/sim_uart_receiver_model/sim_uart_receiver_model.sv:51: Unsupported: Ignoring delay on this delayed statement.\n    #(base_latency);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/48602886/sim/model/sim_uart_receiver_model/sim_uart_receiver_model.sv:54: Unsupported: Ignoring delay on this delayed statement.\n    #(base_latency);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/48602886/sim/model/sim_uart_receiver_model/sim_uart_receiver_model.sv:57: Unsupported: Ignoring delay on this delayed statement.\n    #(base_latency);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/48602886/sim/model/sim_uart_receiver_model/sim_uart_receiver_model.sv:60: Unsupported: Ignoring delay on this delayed statement.\n    #(base_latency);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/48602886/sim/model/sim_uart_receiver_model/sim_uart_receiver_model.sv:63: Unsupported: Ignoring delay on this delayed statement.\n    #(base_latency);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/48602886/sim/model/sim_uart_receiver_model/sim_uart_receiver_model.sv:65: Unsupported: Ignoring delay on this delayed statement.\n    #(base_latency);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/48602886/sim/model/sim_uart_receiver_model/sim_uart_receiver_model.sv:82: Unsupported: Ignoring delay on this delayed statement.\n    #(base_latency);\n    ^\n%Warning-INFINITELOOP: data/full_repos/permissive/48602886/sim/model/sim_uart_receiver_model/sim_uart_receiver_model.sv:36: Infinite loop (condition always true)\n                                                                                                                          : ... In instance sim_uart_receiver_model\n  forever begin\n  ^~~~~~~\n%Error: Exiting due to 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sim_uart_receiver_model #(
		parameter P_BAUDRATE = 115200,
		parameter P_DISPLAY_ENA = 1,
		parameter P_DISPLAY_REALTIME = 1
	)(
		input wire iUART_RXD
	);

	integer base_latency = 8680;

	reg [7:0] b_rd_data;
	reg b_timing;

	initial begin
		b_rd_data = 8'h0;
		b_timing = 1'b0;
	end

	always#(base_latency/2)begin
		b_timing = !b_timing;
	end

	function [7:0] func_get_data_bit;
		input func_bit;
		input [7:0] func_data;
		begin
			func_get_data_bit = {func_bit, func_data[7:1]};
		end
	endfunction


	initial begin
		forever begin
			if(!iUART_RXD)begin

				#(base_latency);

				b_rd_data = func_get_data_bit(iUART_RXD, b_rd_data);
				#(base_latency);

				b_rd_data = func_get_data_bit(iUART_RXD, b_rd_data);
				#(base_latency);

				b_rd_data = func_get_data_bit(iUART_RXD, b_rd_data);
				#(base_latency);

				b_rd_data = func_get_data_bit(iUART_RXD, b_rd_data);
				#(base_latency);

				b_rd_data = func_get_data_bit(iUART_RXD, b_rd_data);
				#(base_latency);

				b_rd_data = func_get_data_bit(iUART_RXD, b_rd_data);
				#(base_latency);

				b_rd_data = func_get_data_bit(iUART_RXD, b_rd_data);
				#(base_latency);

				b_rd_data = func_get_data_bit(iUART_RXD, b_rd_data);
				#(base_latency);

				#(base_latency);

				if(P_DISPLAY_ENA)begin
					if(b_rd_data == 8'h0a)begin
						$display("");
					end
					else begin
						if(P_DISPLAY_REALTIME)begin
							$display("%s", b_rd_data);
						end
						else begin
							$write("%s", b_rd_data);
						end
					end
				end
			end
			else begin
				#(base_latency);
			end
		end
	end


endmodule
module sim_uart_receiver_model #(
		parameter P_BAUDRATE = 115200,
		parameter P_DISPLAY_ENA = 1,
		parameter P_DISPLAY_REALTIME = 1
	)(
		input wire iUART_RXD
	);


	integer base_latency = 8680;

	reg [7:0] b_rd_data;
	reg b_timing;

	initial begin
		b_rd_data = 8'h0;
		b_timing = 1'b0;
	end

	always#(base_latency/2)begin
		b_timing = !b_timing;
	end

	function [7:0] func_get_data_bit;
		input func_bit;
		input [7:0] func_data;
		begin
			func_get_data_bit = {func_bit, func_data[7:1]};
		end
	endfunction


	initial begin
		forever begin
			if(!iUART_RXD)begin

				#(base_latency);

				b_rd_data = func_get_data_bit(iUART_RXD, b_rd_data);
				#(base_latency);

				b_rd_data = func_get_data_bit(iUART_RXD, b_rd_data);
				#(base_latency);

				b_rd_data = func_get_data_bit(iUART_RXD, b_rd_data);
				#(base_latency);

				b_rd_data = func_get_data_bit(iUART_RXD, b_rd_data);
				#(base_latency);

				b_rd_data = func_get_data_bit(iUART_RXD, b_rd_data);
				#(base_latency);

				b_rd_data = func_get_data_bit(iUART_RXD, b_rd_data);
				#(base_latency);

				b_rd_data = func_get_data_bit(iUART_RXD, b_rd_data);
				#(base_latency);

				b_rd_data = func_get_data_bit(iUART_RXD, b_rd_data);
				#(base_latency);

				#(base_latency);

				if(P_DISPLAY_ENA)begin
					if(b_rd_data == 8'h0a)begin
						$display("");
					end
					else begin
						if(P_DISPLAY_REALTIME)begin
							$display("%s", b_rd_data);
						end
						else begin
							$write("%s", b_rd_data);
						end
					end
				end
			end
			else begin
				#(base_latency);
			end
		end
	end


endmodule