data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word/probador_bits8_32word.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word/probador_bits8_32word.v:12: Unsupported: Ignoring delay on this delayed statement.\n always #1 clk_4f = ~clk_4f;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word/probador_bits8_32word.v:15: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile ("prueba_bits8_32word.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word/probador_bits8_32word.v:16: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars;\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word/probador_bits8_32word.v:21: syntax error, unexpected \'@\'\n  @(posedge clk_4f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word/probador_bits8_32word.v:25: syntax error, unexpected \'@\'\n  @(posedge clk_4f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word/probador_bits8_32word.v:27: syntax error, unexpected \'@\'\n  @(posedge clk_4f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word/probador_bits8_32word.v:29: syntax error, unexpected \'@\'\n  @(posedge clk_4f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word/probador_bits8_32word.v:31: syntax error, unexpected \'@\'\n  @(posedge clk_4f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word/probador_bits8_32word.v:33: syntax error, unexpected \'@\'\n  @(posedge clk_4f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word/probador_bits8_32word.v:35: syntax error, unexpected \'@\'\n  @(posedge clk_4f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word/probador_bits8_32word.v:37: syntax error, unexpected \'@\'\n  @(posedge clk_4f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word/probador_bits8_32word.v:39: syntax error, unexpected \'@\'\n  @(posedge clk_4f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word/probador_bits8_32word.v:41: syntax error, unexpected \'@\'\n  @(posedge clk_4f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word/probador_bits8_32word.v:47: syntax error, unexpected \'@\'\n  @(posedge clk_4f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word/probador_bits8_32word.v:49: syntax error, unexpected \'@\'\n  @(posedge clk_4f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word/probador_bits8_32word.v:51: syntax error, unexpected \'@\'\n  @(posedge clk_4f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word/probador_bits8_32word.v:53: syntax error, unexpected \'@\'\n  @(posedge clk_4f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word/probador_bits8_32word.v:56: syntax error, unexpected \'@\'\n  @(posedge clk_4f);\n  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word/probador_bits8_32word.v:68: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n reg [1:0] checker; \n           ^~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word/probador_bits8_32word.v:68: syntax error, unexpected \';\', expecting IDENTIFIER or \'=\' or do or final\n reg [1:0] checker; \n                  ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word/probador_bits8_32word.v:70: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  if (Data_out_c == Data_out_e) checker[1] = 1;\n                                ^~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word/probador_bits8_32word.v:70: syntax error, unexpected \'[\'\n  if (Data_out_c == Data_out_e) checker[1] = 1;\n                                       ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word/probador_bits8_32word.v:71: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  else checker[1] = 0;\n       ^~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word/probador_bits8_32word.v:73: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  if (valid_out_c == valid_out_e) checker[0] = 1;\n                                  ^~~~~~~\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word/probador_bits8_32word.v:73: syntax error, unexpected \'[\'\n  if (valid_out_c == valid_out_e) checker[0] = 1;\n                                         ^\n%Error: data/full_repos/permissive/425529933/Proyecto1Digitales2/bits8-32word/probador_bits8_32word.v:74: Unsupported: SystemVerilog 2009 reserved word not implemented: \'checker\'\n  else checker[0] = 0;\n       ^~~~~~~\n%Error: Exiting due to 25 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module probador_bits8_32word (
	output reg clk_4f,
	output reg reset,
	output reg valid_in,
	output reg [7:0] Data_in,
	input valid_out_c,
	input [31:0] Data_out_c,
	input valid_out_e,
	input [31:0] Data_out_e
);
	initial clk_4f = 0;
	always #1 clk_4f = ~clk_4f;

	initial begin
		$dumpfile ("prueba_bits8_32word.vcd");
		$dumpvars;

		reset <= 0;
		valid_in <= 0;
		Data_in <= 8'b0;
		@(posedge clk_4f);
		reset <= 1;
		valid_in <= 1;
		Data_in <= 'hFF;
		@(posedge clk_4f);
		Data_in <= 'hAA;
		@(posedge clk_4f);
		Data_in <= 'hFF;
		@(posedge clk_4f);
		Data_in <= 'hBB;
		@(posedge clk_4f);
		Data_in <= 'hDD;
		@(posedge clk_4f);
		Data_in <= 'hCC;
		@(posedge clk_4f);
		Data_in <= 'hDD;
		@(posedge clk_4f);
		Data_in <= 'hEE;
		@(posedge clk_4f);
		valid_in <= 0;
		@(posedge clk_4f);
		@(posedge clk_4f);
		@(posedge clk_4f);
		@(posedge clk_4f);
		valid_in <= 1;
		Data_in <= 'h01;
		@(posedge clk_4f);
		Data_in <= 'h0F;
		@(posedge clk_4f);
		Data_in <= 'h0A;
		@(posedge clk_4f);
		Data_in <= 'h03;
		@(posedge clk_4f);
		Data_in <= 'h00;
		valid_in <= 0;
		@(posedge clk_4f);
		@(posedge clk_4f);
		@(posedge clk_4f);
		@(posedge clk_4f);
		@(posedge clk_4f);
		@(posedge clk_4f);
		$finish;
	end




	reg [1:0] checker; 
	always @(*) begin
		if (Data_out_c == Data_out_e) checker[1] = 1;
		else checker[1] = 0;

		if (valid_out_c == valid_out_e) checker[0] = 1;
		else checker[0] = 0;
	end
endmodule
module probador_bits8_32word (
	output reg clk_4f,
	output reg reset,
	output reg valid_in,
	output reg [7:0] Data_in,
	input valid_out_c,
	input [31:0] Data_out_c,
	input valid_out_e,
	input [31:0] Data_out_e
);

	initial clk_4f = 0;
	always #1 clk_4f = ~clk_4f;

	initial begin
		$dumpfile ("prueba_bits8_32word.vcd");
		$dumpvars;

		reset <= 0;
		valid_in <= 0;
		Data_in <= 8'b0;
		@(posedge clk_4f);
		reset <= 1;
		valid_in <= 1;
		Data_in <= 'hFF;
		@(posedge clk_4f);
		Data_in <= 'hAA;
		@(posedge clk_4f);
		Data_in <= 'hFF;
		@(posedge clk_4f);
		Data_in <= 'hBB;
		@(posedge clk_4f);
		Data_in <= 'hDD;
		@(posedge clk_4f);
		Data_in <= 'hCC;
		@(posedge clk_4f);
		Data_in <= 'hDD;
		@(posedge clk_4f);
		Data_in <= 'hEE;
		@(posedge clk_4f);
		valid_in <= 0;
		@(posedge clk_4f);
		@(posedge clk_4f);
		@(posedge clk_4f);
		@(posedge clk_4f);
		valid_in <= 1;
		Data_in <= 'h01;
		@(posedge clk_4f);
		Data_in <= 'h0F;
		@(posedge clk_4f);
		Data_in <= 'h0A;
		@(posedge clk_4f);
		Data_in <= 'h03;
		@(posedge clk_4f);
		Data_in <= 'h00;
		valid_in <= 0;
		@(posedge clk_4f);
		@(posedge clk_4f);
		@(posedge clk_4f);
		@(posedge clk_4f);
		@(posedge clk_4f);
		@(posedge clk_4f);
		$finish;
	end




	reg [1:0] checker; 
	always @(*) begin
		if (Data_out_c == Data_out_e) checker[1] = 1;
		else checker[1] = 0;

		if (valid_out_c == valid_out_e) checker[0] = 1;
		else checker[0] = 0;
	end
endmodule