data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/branch_unit.sv
1: b"%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/branch_unit.sv:19: syntax error, unexpected ::, expecting ')' or ','\n    input  ariane_pkg::fu_data_t      fu_data_i,\n                     ^~\n                                                                                                               : ... Perhaps 'ariane_pkg' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/branch_unit.sv:20: syntax error, unexpected ::, expecting ':'\n    input  logic [riscv::VLEN-1:0]    pc_i,                    \n                       ^~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/branch_unit.sv:22: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic                      fu_valid_i,              \n    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/branch_unit.sv:23: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic                      branch_valid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/branch_unit.sv:24: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic                      branch_comp_res_i,       \n    ^~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/branch_unit.sv:25: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic [riscv::VLEN-1:0]    branch_result_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/branch_unit.sv:25: syntax error, unexpected ::, expecting ':'\n    output logic [riscv::VLEN-1:0]    branch_result_o,\n                       ^~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/branch_unit.sv:31: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output ariane_pkg::exception_t    branch_exception_o       \n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/branch_unit.sv:33: syntax error, unexpected ::, expecting ':'\n    logic [riscv::VLEN-1:0] target_address;\n                ^~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/branch_unit.sv:34: syntax error, unexpected ::, expecting ':'\n    logic [riscv::VLEN-1:0] next_pc;\n                ^~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/src/branch_unit.sv:39: syntax error, unexpected ::, expecting ':'\n        automatic logic [riscv::VLEN-1:0] jump_base;\n                              ^~\n%Error: Exiting due to 11 error(s)\n"
module branch_unit (
    input  logic                      clk_i,
    input  logic                      rst_ni,
    input  logic                      debug_mode_i,
    input  ariane_pkg::fu_data_t      fu_data_i,
    input  logic [riscv::VLEN-1:0]    pc_i,
    input  logic                      is_compressed_instr_i,
    input  logic                      fu_valid_i,
    input  logic                      branch_valid_i,
    input  logic                      branch_comp_res_i,
    output logic [riscv::VLEN-1:0]    branch_result_o,

    input  ariane_pkg::branchpredict_sbe_t        branch_predict_i,
    output ariane_pkg::bp_resolve_t               resolved_branch_o,
    output logic                      resolve_branch_o,

    output ariane_pkg::exception_t    branch_exception_o
);
    logic [riscv::VLEN-1:0] target_address;
    logic [riscv::VLEN-1:0] next_pc;


    always_comb begin : mispredict_handler

        automatic logic [riscv::VLEN-1:0] jump_base;

        jump_base = (fu_data_i.operator == ariane_pkg::JALR) ? fu_data_i.operand_a[riscv::VLEN-1:0] : pc_i;

        target_address                   = {riscv::VLEN{1'b0}};
        resolve_branch_o                 = 1'b0;
        resolved_branch_o.target_address = {riscv::VLEN{1'b0}};
        resolved_branch_o.is_taken       = 1'b0;
        resolved_branch_o.valid          = branch_valid_i;
        resolved_branch_o.is_mispredict  = 1'b0;
        resolved_branch_o.cf_type        = branch_predict_i.cf;


        next_pc                          = pc_i + ((is_compressed_instr_i) ? {{riscv::VLEN-2{1'b0}}, 2'h2} : {{riscv::VLEN-3{1'b0}}, 3'h4});

        target_address                   = $unsigned($signed(jump_base) + $signed(fu_data_i.imm[riscv::VLEN-1:0]));

        if (fu_data_i.operator == ariane_pkg::JALR) target_address[0] = 1'b0;

        branch_result_o = next_pc;
        resolved_branch_o.pc = pc_i;



        if (branch_valid_i) begin

            resolved_branch_o.target_address = (branch_comp_res_i) ? target_address : next_pc;
            resolved_branch_o.is_taken = branch_comp_res_i;

            if (ariane_pkg::op_is_branch(fu_data_i.operator) && branch_comp_res_i != (branch_predict_i.cf == ariane_pkg::Branch)) begin


                resolved_branch_o.is_mispredict  = 1'b1;
                resolved_branch_o.cf_type = ariane_pkg::Branch;
            end
            if (fu_data_i.operator == ariane_pkg::JALR

                && (branch_predict_i.cf == ariane_pkg::NoCF || target_address != branch_predict_i.predict_address)) begin
                resolved_branch_o.is_mispredict  = 1'b1;

                if (branch_predict_i.cf != ariane_pkg::Return) resolved_branch_o.cf_type = ariane_pkg::JumpR;
            end

            resolve_branch_o = 1'b1;
        end
    end


    always_comb begin : exception_handling
        branch_exception_o.cause = riscv::INSTR_ADDR_MISALIGNED;
        branch_exception_o.valid = 1'b0;
        branch_exception_o.tval  = {{riscv::XLEN-riscv::VLEN{pc_i[riscv::VLEN-1]}}, pc_i};

        if (branch_valid_i && target_address[0] != 1'b0) branch_exception_o.valid = 1'b1;
    end
endmodule
module branch_unit (
    input  logic                      clk_i,
    input  logic                      rst_ni,
    input  logic                      debug_mode_i,
    input  ariane_pkg::fu_data_t      fu_data_i,
    input  logic [riscv::VLEN-1:0]    pc_i,
    input  logic                      is_compressed_instr_i,
    input  logic                      fu_valid_i,
    input  logic                      branch_valid_i,
    input  logic                      branch_comp_res_i,
    output logic [riscv::VLEN-1:0]    branch_result_o,

    input  ariane_pkg::branchpredict_sbe_t        branch_predict_i,
    output ariane_pkg::bp_resolve_t               resolved_branch_o,
    output logic                      resolve_branch_o,

    output ariane_pkg::exception_t    branch_exception_o
);

    logic [riscv::VLEN-1:0] target_address;
    logic [riscv::VLEN-1:0] next_pc;


    always_comb begin : mispredict_handler

        automatic logic [riscv::VLEN-1:0] jump_base;

        jump_base = (fu_data_i.operator == ariane_pkg::JALR) ? fu_data_i.operand_a[riscv::VLEN-1:0] : pc_i;

        target_address                   = {riscv::VLEN{1'b0}};
        resolve_branch_o                 = 1'b0;
        resolved_branch_o.target_address = {riscv::VLEN{1'b0}};
        resolved_branch_o.is_taken       = 1'b0;
        resolved_branch_o.valid          = branch_valid_i;
        resolved_branch_o.is_mispredict  = 1'b0;
        resolved_branch_o.cf_type        = branch_predict_i.cf;


        next_pc                          = pc_i + ((is_compressed_instr_i) ? {{riscv::VLEN-2{1'b0}}, 2'h2} : {{riscv::VLEN-3{1'b0}}, 3'h4});

        target_address                   = $unsigned($signed(jump_base) + $signed(fu_data_i.imm[riscv::VLEN-1:0]));

        if (fu_data_i.operator == ariane_pkg::JALR) target_address[0] = 1'b0;

        branch_result_o = next_pc;
        resolved_branch_o.pc = pc_i;



        if (branch_valid_i) begin

            resolved_branch_o.target_address = (branch_comp_res_i) ? target_address : next_pc;
            resolved_branch_o.is_taken = branch_comp_res_i;

            if (ariane_pkg::op_is_branch(fu_data_i.operator) && branch_comp_res_i != (branch_predict_i.cf == ariane_pkg::Branch)) begin


                resolved_branch_o.is_mispredict  = 1'b1;
                resolved_branch_o.cf_type = ariane_pkg::Branch;
            end
            if (fu_data_i.operator == ariane_pkg::JALR

                && (branch_predict_i.cf == ariane_pkg::NoCF || target_address != branch_predict_i.predict_address)) begin
                resolved_branch_o.is_mispredict  = 1'b1;

                if (branch_predict_i.cf != ariane_pkg::Return) resolved_branch_o.cf_type = ariane_pkg::JumpR;
            end

            resolve_branch_o = 1'b1;
        end
    end


    always_comb begin : exception_handling
        branch_exception_o.cause = riscv::INSTR_ADDR_MISALIGNED;
        branch_exception_o.valid = 1'b0;
        branch_exception_o.tval  = {{riscv::XLEN-riscv::VLEN{pc_i[riscv::VLEN-1]}}, pc_i};

        if (branch_valid_i && target_address[0] != 1'b0) branch_exception_o.valid = 1'b1;
    end
endmodule