data/full_repos/permissive/528677531/LAB-5/Q3/q.v
data/verilator_xmls/33d66697-dd49-4d46-93ed-7a6710a18fe3.xml
module q(g,b);
input [3:0]g;
output [3:0]b;
assign b[0] = g[0];
assign b[1] = g[1]^g[0];
assign b[2] = (~g[2]&g[0])|(g[1]&~g[2])|(~g[1]&~g[0]&g[2]);
assign b[3] = (g[3]&g[2])|(g[3]&~g[1]&~g[0]);
endmodule
module q(g,b);

input [3:0]g;
output [3:0]b;
assign b[0] = g[0];
assign b[1] = g[1]^g[0];
assign b[2] = (~g[2]&g[0])|(g[1]&~g[2])|(~g[1]&~g[0]&g[2]);
assign b[3] = (g[3]&g[2])|(g[3]&~g[1]&~g[0]);
endmodule