data/full_repos/permissive/446997925/hw3/datapath.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/446997925/hw3/datapath.v:36: Signal definition not found, creating implicitly: \'shift\'\n                                                                         : ... Suggested alternative: \'shift_l\'\n else if(shift)\n         ^~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/446997925/hw3/datapath.v:38: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                      : ... In instance mult_32\n  product_out <= {1\'b0,product_out[N-1:1]};  \n              ^~\n%Error: data/full_repos/permissive/446997925/hw3/datapath.v:59: Cannot find file containing module: \'add_32\'\nadd_32 add_count(count_wire,count,32\'b1);\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/446997925/hw3,data/full_repos/permissive/446997925/add_32\n             data/full_repos/permissive/446997925/hw3,data/full_repos/permissive/446997925/add_32.v\n             data/full_repos/permissive/446997925/hw3,data/full_repos/permissive/446997925/add_32.sv\n             add_32\n             add_32.v\n             add_32.sv\n             obj_dir/add_32\n             obj_dir/add_32.v\n             obj_dir/add_32.sv\n%Error: data/full_repos/permissive/446997925/hw3/datapath.v:66: Cannot find file containing module: \'control_unit\'\ncontrol_unit CU \n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/446997925/hw3/datapath.v:80: Cannot find file containing module: \'adder_32\'\nadder_32  adder_multiplier (add_result,multiplicant_state,product_wire[2*N-1:N]); \n^~~~~~~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module mult_32 (clk,reset,start,multiplier_input,multiplicand_input,product_out);

parameter N=32;


input clk;
input reset;
input start;
input [N-1:0] multiplier_input;
input [N-1:0] multiplicand_input;


output reg[2*N-1:0] product_out;
reg[N-1:0] count;



reg [N-1:0] multiplicant_state;
wire [2*N-1:0] product_wire;
wire shift_l,shift_r,load,write,increment;


always@(posedge clk)
begin
	if(reset)
	begin
		multiplicant_state <= 'b0;
       product_out <= 'b0;
		 end
	else if(load)
	begin
		multiplicant_state <= multiplicand_input;
      product_out <= {{N{1'b0}},multiplier_input};
		end
	else if(shift)
	begin
		product_out <= {1'b0,product_out[N-1:1]};
		end
    else if(write)
	 begin
        product_out <= {add_result[N-1:0],product_out[N-1:0]};
		  end

end


always@(posedge clk or posedge reset)
begin
	if(reset)
		count <= 32'b0;
	else if(increment)
		count <= count_wire;
end
		


wire[N-1:0] count_wire;
add_32 add_count(count_wire,count,32'b1);




	

control_unit CU 
(
	.clk(clk),
	.reset(reset),
	.start(start),
	.lsb(product_out[0]),
	.load(load),
	.shift(shift),
	.write(write),
   .counter32(count[5]),
	.increment(increment)
);

wire [N-1:0] add_result ;
adder_32  adder_multiplier (add_result,multiplicant_state,product_wire[2*N-1:N]);	





endmodule
module mult_32 (clk,reset,start,multiplier_input,multiplicand_input,product_out);


parameter N=32;


input clk;
input reset;
input start;
input [N-1:0] multiplier_input;
input [N-1:0] multiplicand_input;


output reg[2*N-1:0] product_out;
reg[N-1:0] count;



reg [N-1:0] multiplicant_state;
wire [2*N-1:0] product_wire;
wire shift_l,shift_r,load,write,increment;


always@(posedge clk)
begin
	if(reset)
	begin
		multiplicant_state <= 'b0;
       product_out <= 'b0;
		 end
	else if(load)
	begin
		multiplicant_state <= multiplicand_input;
      product_out <= {{N{1'b0}},multiplier_input};
		end
	else if(shift)
	begin
		product_out <= {1'b0,product_out[N-1:1]};
		end
    else if(write)
	 begin
        product_out <= {add_result[N-1:0],product_out[N-1:0]};
		  end

end


always@(posedge clk or posedge reset)
begin
	if(reset)
		count <= 32'b0;
	else if(increment)
		count <= count_wire;
end
		


wire[N-1:0] count_wire;
add_32 add_count(count_wire,count,32'b1);




	

control_unit CU 
(
	.clk(clk),
	.reset(reset),
	.start(start),
	.lsb(product_out[0]),
	.load(load),
	.shift(shift),
	.write(write),
   .counter32(count[5]),
	.increment(increment)
);

wire [N-1:0] add_result ;
adder_32  adder_multiplier (add_result,multiplicant_state,product_wire[2*N-1:N]);	





endmodule