data/full_repos/permissive/454159683/mux2to1e/mux2to1e.v
data/verilator_xmls/328c26a0-7c6f-4045-b827-56ba067a0b8d.xml
module mux2to1e(input a, b, sel, output out);
	wire [2:0] x;
	assign x[0] = !sel;
	assign x[1] = x[0] & a;
	assign x[2] = sel & b;
	
	assign out = x[1] | x[2];
endmodule
module mux2to1e(input a, b, sel, output out);

	wire [2:0] x;
	assign x[0] = !sel;
	assign x[1] = x[0] & a;
	assign x[2] = sel & b;
	
	assign out = x[1] | x[2];
endmodule