data/full_repos/permissive/449652714/src/sources_1/rtl/memory.v
1: b'%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/memory.v:7: Cannot find include file: define.vh\n`include "define.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/449652714/src/sources_1/rtl,data/full_repos/permissive/449652714/define.vh\n             data/full_repos/permissive/449652714/src/sources_1/rtl,data/full_repos/permissive/449652714/define.vh.v\n             data/full_repos/permissive/449652714/src/sources_1/rtl,data/full_repos/permissive/449652714/define.vh.sv\n             define.vh\n             define.vh.v\n             define.vh.sv\n             obj_dir/define.vh\n             obj_dir/define.vh.v\n             obj_dir/define.vh.sv\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/memory.v:447: Define or directive not defined: \'`CACHE_SIZE\'\n    m_dram_cache#(28,128,`CACHE_SIZE/16) cache(i_clk, 1\'b1, 1\'b0, c_clr, c_we,\n                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/449652714/src/sources_1/rtl/memory.v:447: syntax error, unexpected \'/\', expecting \')\'\n    m_dram_cache#(28,128,`CACHE_SIZE/16) cache(i_clk, 1\'b1, 1\'b0, c_clr, c_we,\n                                    ^\n%Error: Exiting due to 3 error(s)\n'
module m_col_bram#(parameter WIDTH=32, ENTRY=256)(CLK, w_we, w_addr, w_idata, w_odata);
    input  wire                     CLK;
    input  wire               [3:0] w_we;
    input  wire [$clog2(ENTRY)-1:0] w_addr;
    input  wire         [WIDTH-1:0] w_idata;
    output wire         [WIDTH-1:0] w_odata;



    (* ram_style = "block" *) reg [WIDTH-1:0] mem[0:ENTRY-1];
    reg [$clog2(ENTRY)-1:0] addr=0;
    always @(posedge CLK) begin
        if (w_we[0]) mem[w_addr][ 7: 0] <= w_idata[ 7: 0];
        if (w_we[1]) mem[w_addr][15: 8] <= w_idata[15: 8];
        if (w_we[2]) mem[w_addr][23:16] <= w_idata[23:16];
        if (w_we[3]) mem[w_addr][31:24] <= w_idata[31:24];
        addr <= w_addr;
    end
    assign w_odata = mem[addr];
endmodule
module m_col_bram#(parameter WIDTH=32, ENTRY=256)(CLK, w_we, w_addr, w_idata, w_odata);

    input  wire                     CLK;
    input  wire               [3:0] w_we;
    input  wire [$clog2(ENTRY)-1:0] w_addr;
    input  wire         [WIDTH-1:0] w_idata;
    output wire         [WIDTH-1:0] w_odata;



    (* ram_style = "block" *) reg [WIDTH-1:0] mem[0:ENTRY-1];
    reg [$clog2(ENTRY)-1:0] addr=0;
    always @(posedge CLK) begin
        if (w_we[0]) mem[w_addr][ 7: 0] <= w_idata[ 7: 0];
        if (w_we[1]) mem[w_addr][15: 8] <= w_idata[15: 8];
        if (w_we[2]) mem[w_addr][23:16] <= w_idata[23:16];
        if (w_we[3]) mem[w_addr][31:24] <= w_idata[31:24];
        addr <= w_addr;
    end
    assign w_odata = mem[addr];
endmodule