data/full_repos/permissive/515624136/rtl/LSU.v
data/verilator_xmls/006e9c49-aed3-4b4e-ae87-6b20c4d9f1e1.xml
module LSU #(parameter DATAWIDTH=32) (



LSU_MemData_InBUS,
LSU_Funct3_InBUS,
LSU_Store,
LSU_En,


LSU_Byteenable_OutBUS,
LSU_Data_OutBUS

);





input [DATAWIDTH-1:0] LSU_MemData_InBUS;
input [2:0] LSU_Funct3_InBUS;
input LSU_Store;
input LSU_En;

output [3:0]  LSU_Byteenable_OutBUS;
output [DATAWIDTH-1:0] LSU_Data_OutBUS;






localparam ONE_BYTE   = 4'b0001,
			  TWO_BYTES  = 4'b0011,
           FOUR_BYTES = 4'b1111;

localparam LSB = 3'b000,
			  LSH = 3'b001,
			  LSW = 3'b010,
			  LBU = 3'b100,
			  LHU = 3'b101;
			  





reg [DATAWIDTH-1:0] Temp_Data;
reg [3:0] Byteenable;





always@(*)
begin	
	casex(LSU_Funct3_InBUS)
		3'b?00: Byteenable = ONE_BYTE;
		3'b?01: Byteenable = TWO_BYTES;
		3'b010: Byteenable = FOUR_BYTES;
		default: Byteenable = FOUR_BYTES; 	
	endcase
end

always@(*)
begin

	case(LSU_Funct3_InBUS)
		
		LSB: Temp_Data = {{25{LSU_MemData_InBUS[7]}},
							   LSU_MemData_InBUS[6:0]};
		
		LSH: Temp_Data = {{17{LSU_MemData_InBUS[15]}},
							   LSU_MemData_InBUS[14:0]};
		
		LSW: Temp_Data = LSU_MemData_InBUS;
		
		LBU: Temp_Data= {{24{1'b0}},
							   LSU_MemData_InBUS[7:0]};
								
		LHU: Temp_Data = {{16{1'b0}},
							   LSU_MemData_InBUS[15:0]};
								
		default Temp_Data= LSU_MemData_InBUS;
	
	endcase 

end


assign LSU_Data_OutBUS = (LSU_En&(~LSU_Store)) == 1'b1 ? Temp_Data : LSU_MemData_InBUS;
assign LSU_Byteenable_OutBUS =  LSU_En == 1'b1 ? Byteenable : 4'b0000;

endmodule
module LSU #(parameter DATAWIDTH=32) (



LSU_MemData_InBUS,
LSU_Funct3_InBUS,
LSU_Store,
LSU_En,


LSU_Byteenable_OutBUS,
LSU_Data_OutBUS

);






input [DATAWIDTH-1:0] LSU_MemData_InBUS;
input [2:0] LSU_Funct3_InBUS;
input LSU_Store;
input LSU_En;

output [3:0]  LSU_Byteenable_OutBUS;
output [DATAWIDTH-1:0] LSU_Data_OutBUS;






localparam ONE_BYTE   = 4'b0001,
			  TWO_BYTES  = 4'b0011,
           FOUR_BYTES = 4'b1111;

localparam LSB = 3'b000,
			  LSH = 3'b001,
			  LSW = 3'b010,
			  LBU = 3'b100,
			  LHU = 3'b101;
			  





reg [DATAWIDTH-1:0] Temp_Data;
reg [3:0] Byteenable;





always@(*)
begin	
	casex(LSU_Funct3_InBUS)
		3'b?00: Byteenable = ONE_BYTE;
		3'b?01: Byteenable = TWO_BYTES;
		3'b010: Byteenable = FOUR_BYTES;
		default: Byteenable = FOUR_BYTES; 	
	endcase
end

always@(*)
begin

	case(LSU_Funct3_InBUS)
		
		LSB: Temp_Data = {{25{LSU_MemData_InBUS[7]}},
							   LSU_MemData_InBUS[6:0]};
		
		LSH: Temp_Data = {{17{LSU_MemData_InBUS[15]}},
							   LSU_MemData_InBUS[14:0]};
		
		LSW: Temp_Data = LSU_MemData_InBUS;
		
		LBU: Temp_Data= {{24{1'b0}},
							   LSU_MemData_InBUS[7:0]};
								
		LHU: Temp_Data = {{16{1'b0}},
							   LSU_MemData_InBUS[15:0]};
								
		default Temp_Data= LSU_MemData_InBUS;
	
	endcase 

end


assign LSU_Data_OutBUS = (LSU_En&(~LSU_Store)) == 1'b1 ? Temp_Data : LSU_MemData_InBUS;
assign LSU_Byteenable_OutBUS =  LSU_En == 1'b1 ? Byteenable : 4'b0000;

endmodule