data/full_repos/permissive/491294671/timer_input_control/mux/mux.v
data/verilator_xmls/6fa9186b-62b1-42ec-9e23-234570d03540.xml
module MUX_2to1 (output wire out, input wire sel, A, B);
  
  assign out = (sel == 1'b0) ? A :
    (sel == 1'b1) ? B:
    1'bX;
    
  
endmodule
module MUX_2to1 (output wire out, input wire sel, A, B);

  
  assign out = (sel == 1'b0) ? A :
    (sel == 1'b1) ? B:
    1'bX;
    
  
endmodule