data/full_repos/permissive/493019833/test/testcase/firrtl/DspComplexExamplesTester/reference/DspComplexExamplesTester.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/DspComplexExamplesTester/reference/DspComplexExamplesTester.v:452: Operator COND expects 5 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                                                           : ... In instance DspComplexExamplesTester.s_pad_39\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/DspComplexExamplesTester/reference/DspComplexExamplesTester.v:452: Operator COND expects 5 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 2 bits.\n                                                                                                                                           : ... In instance DspComplexExamplesTester.s_pad_44\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/DspComplexExamplesTester/reference/DspComplexExamplesTester.v:452: Operator COND expects 5 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 4 bits.\n                                                                                                                                           : ... In instance DspComplexExamplesTester.s_pad_49\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/DspComplexExamplesTester/reference/DspComplexExamplesTester.v:452: Operator COND expects 5 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 3 bits.\n                                                                                                                                           : ... In instance DspComplexExamplesTester.s_pad_71\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/DspComplexExamplesTester/reference/DspComplexExamplesTester.v:452: Operator COND expects 2 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                                                           : ... In instance DspComplexExamplesTester.dut.s_pad_1\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/DspComplexExamplesTester/reference/DspComplexExamplesTester.v:452: Operator COND expects 7 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 6 bits.\n                                                                                                                                           : ... In instance DspComplexExamplesTester.dut.s_pad_17\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n%Error: Exiting due to 6 warning(s)\n'
module TAIL(y, in);
    parameter width = 4;
    parameter n = 2;
    output [width-n-1:0] y;
    input [width-1:0] in;
    assign y = in[width-n-1:0];
endmodule
module TAIL(y, in);

    parameter width = 4;
    parameter n = 2;
    output [width-n-1:0] y;
    input [width-1:0] in;
    assign y = in[width-n-1:0];
endmodule