data/full_repos/permissive/496508301/Lesson10/cmd_pro.v
data/verilator_xmls/e02c87f9-5d0e-4920-8f82-68eb2c55ffba.xml
module cmd_pro(
                clk, 
                res, 
                din_pro, 
                en_din_pro, 
                dout_pro, 
                en_dout_pro,
                rdy
);
input           clk;
input           res;
input[7:0]      din_pro;
input           en_din_pro;
output[7:0]     dout_pro;
output          en_dout_pro;
output          rdy;

parameter       addx = 8'h0a;
parameter       subx = 8'h0b;
parameter       andx = 8'h0c;
parameter       orx  = 8'h0d;
reg[2:0]        state;
reg[7:0]        cmd, A, B;
reg[7:0]        dout_pro;
reg             en_dout_pro;
always @(posedge clk or negedge res) begin
    if(~res)begin
        state <= 0; cmd <= 0; A <= 0; B <= 0; dout_pro <= 0; 
        en_dout_pro <= 0;
    end
    else begin
        case(state)
        0:
        begin
            en_dout_pro <= 0;
            if(en_din_pro)begin
                cmd <= din_pro;
                state <= 1;
            end
        end
        1:
        begin
            if (en_din_pro)begin
                A <= din_pro;
                state <= 2;
            end
        end
        2:
        begin
            if (en_din_pro)begin
                B <= din_pro;
                state <= 3;
            end
        end
        3:
        begin
            case(cmd)
            addx: begin dout_pro <= A+B; end 
            subx: begin dout_pro <= A-B; end
            andx: begin dout_pro <= A&B; end
            orx:  begin dout_pro <= A|B; end
            endcase
            state <= 4;
        end
        4:
        begin
            if(~rdy)begin
                en_dout_pro <= 1;
                state <= 0;
            end
        end
        default:
        begin
            state <= 0;
            en_dout_pro <= 0;
        end
        endcase
    end
end
endmodule
module cmd_pro(
                clk, 
                res, 
                din_pro, 
                en_din_pro, 
                dout_pro, 
                en_dout_pro,
                rdy
);

input           clk;
input           res;
input[7:0]      din_pro;
input           en_din_pro;
output[7:0]     dout_pro;
output          en_dout_pro;
output          rdy;

parameter       addx = 8'h0a;
parameter       subx = 8'h0b;
parameter       andx = 8'h0c;
parameter       orx  = 8'h0d;
reg[2:0]        state;
reg[7:0]        cmd, A, B;
reg[7:0]        dout_pro;
reg             en_dout_pro;
always @(posedge clk or negedge res) begin
    if(~res)begin
        state <= 0; cmd <= 0; A <= 0; B <= 0; dout_pro <= 0; 
        en_dout_pro <= 0;
    end
    else begin
        case(state)
        0:
        begin
            en_dout_pro <= 0;
            if(en_din_pro)begin
                cmd <= din_pro;
                state <= 1;
            end
        end
        1:
        begin
            if (en_din_pro)begin
                A <= din_pro;
                state <= 2;
            end
        end
        2:
        begin
            if (en_din_pro)begin
                B <= din_pro;
                state <= 3;
            end
        end
        3:
        begin
            case(cmd)
            addx: begin dout_pro <= A+B; end 
            subx: begin dout_pro <= A-B; end
            andx: begin dout_pro <= A&B; end
            orx:  begin dout_pro <= A|B; end
            endcase
            state <= 4;
        end
        4:
        begin
            if(~rdy)begin
                en_dout_pro <= 1;
                state <= 0;
            end
        end
        default:
        begin
            state <= 0;
            en_dout_pro <= 0;
        end
        endcase
    end
end
endmodule