data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/idu/rtl/aq_idu_id_gpr_gated_reg.v
1: b"%Error: data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/idu/rtl/aq_idu_id_gpr_gated_reg.v:65: Cannot find file containing module: 'gated_clk_cell'\ngated_clk_cell  x_reg_gated_clk (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/idu/rtl,data/full_repos/permissive/418750043/gated_clk_cell\n             data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/idu/rtl,data/full_repos/permissive/418750043/gated_clk_cell.v\n             data/full_repos/permissive/418750043/C906_RTL_FACTORY/gen_rtl/idu/rtl,data/full_repos/permissive/418750043/gated_clk_cell.sv\n             gated_clk_cell\n             gated_clk_cell.v\n             gated_clk_cell.sv\n             obj_dir/gated_clk_cell\n             obj_dir/gated_clk_cell.v\n             obj_dir/gated_clk_cell.sv\n%Error: Exiting due to 1 error(s)\n"
module aq_idu_id_gpr_gated_reg(
  cp0_idu_icg_en,
  cp0_yy_clk_en,
  forever_cpuclk,
  pad_yy_icg_scan_en,
  read_data_y,
  rtu_idu_wb0_data,
  rtu_idu_wb1_data,
  wb0_vld_x,
  wb1_vld_x
);


input           cp0_idu_icg_en;    
input           cp0_yy_clk_en;     
input           forever_cpuclk;    
input           pad_yy_icg_scan_en; 
input   [63:0]  rtu_idu_wb0_data;  
input   [63:0]  rtu_idu_wb1_data;  
input           wb0_vld_x;         
input           wb1_vld_x;         
output  [63:0]  read_data_y;       


reg     [63:0]  reg_dout;          
reg     [63:0]  write_data;        


wire            cp0_idu_icg_en;    
wire            cp0_yy_clk_en;     
wire            forever_cpuclk;    
wire            pad_yy_icg_scan_en; 
wire    [63:0]  read_data_y;       
wire            reg_clk;           
wire            reg_clk_en;        
wire    [63:0]  rtu_idu_wb0_data;  
wire    [63:0]  rtu_idu_wb1_data;  
wire            wb0_vld_x;         
wire            wb1_vld_x;         
wire            write_en;          






assign reg_clk_en = write_en;

gated_clk_cell  x_reg_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (reg_clk           ),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (reg_clk_en        ),
  .module_en          (cp0_idu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);











assign write_en = wb0_vld_x || wb1_vld_x;

always @( rtu_idu_wb1_data[63:0]
       or rtu_idu_wb0_data[63:0]
       or wb1_vld_x
       or wb0_vld_x
       or reg_dout[63:0])
begin
  case ({wb1_vld_x,wb0_vld_x})
    2'b01  : write_data[63:0] = rtu_idu_wb0_data[63:0];
    2'b10  : write_data[63:0] = rtu_idu_wb1_data[63:0];
    default: write_data[63:0] = reg_dout[63:0];
  endcase

end




always @(posedge reg_clk)
begin
    reg_dout[63:0] <= write_data[63:0];
end

assign read_data_y[63:0] = write_data[63:0];


endmodule
module aq_idu_id_gpr_gated_reg(
  cp0_idu_icg_en,
  cp0_yy_clk_en,
  forever_cpuclk,
  pad_yy_icg_scan_en,
  read_data_y,
  rtu_idu_wb0_data,
  rtu_idu_wb1_data,
  wb0_vld_x,
  wb1_vld_x
);



input           cp0_idu_icg_en;    
input           cp0_yy_clk_en;     
input           forever_cpuclk;    
input           pad_yy_icg_scan_en; 
input   [63:0]  rtu_idu_wb0_data;  
input   [63:0]  rtu_idu_wb1_data;  
input           wb0_vld_x;         
input           wb1_vld_x;         
output  [63:0]  read_data_y;       


reg     [63:0]  reg_dout;          
reg     [63:0]  write_data;        


wire            cp0_idu_icg_en;    
wire            cp0_yy_clk_en;     
wire            forever_cpuclk;    
wire            pad_yy_icg_scan_en; 
wire    [63:0]  read_data_y;       
wire            reg_clk;           
wire            reg_clk_en;        
wire    [63:0]  rtu_idu_wb0_data;  
wire    [63:0]  rtu_idu_wb1_data;  
wire            wb0_vld_x;         
wire            wb1_vld_x;         
wire            write_en;          






assign reg_clk_en = write_en;

gated_clk_cell  x_reg_gated_clk (
  .clk_in             (forever_cpuclk    ),
  .clk_out            (reg_clk           ),
  .external_en        (1'b0              ),
  .global_en          (cp0_yy_clk_en     ),
  .local_en           (reg_clk_en        ),
  .module_en          (cp0_idu_icg_en    ),
  .pad_yy_icg_scan_en (pad_yy_icg_scan_en)
);











assign write_en = wb0_vld_x || wb1_vld_x;

always @( rtu_idu_wb1_data[63:0]
       or rtu_idu_wb0_data[63:0]
       or wb1_vld_x
       or wb0_vld_x
       or reg_dout[63:0])
begin
  case ({wb1_vld_x,wb0_vld_x})
    2'b01  : write_data[63:0] = rtu_idu_wb0_data[63:0];
    2'b10  : write_data[63:0] = rtu_idu_wb1_data[63:0];
    default: write_data[63:0] = reg_dout[63:0];
  endcase

end




always @(posedge reg_clk)
begin
    reg_dout[63:0] <= write_data[63:0];
end

assign read_data_y[63:0] = write_data[63:0];


endmodule