data/full_repos/permissive/463481430/RTL/core/rib.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/463481430/RTL/core/rib.v:155: Multiple top level modules\n                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                          : ... Top module \'SLAVE_SEL\'\nmodule SLAVE_SEL #(\n       ^~~~~~~~~\n                                                                          : ... Top module \'MASTER_SEL\'\nmodule MASTER_SEL #(\n       ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/463481430/RTL/core/rib.v:267: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'onehot2int\' generates 32 bits.\n                                                                       : ... In instance MASTER_SEL\n                sel_tag_id <= onehot2int(sel_tag);\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/463481430/RTL/core/rib.v:281: Bit extraction of var[2:0] requires 2 bit index, not 3 bits.\n                                                                       : ... In instance MASTER_SEL\n    assign o_ribs_rdy = i_ribm_rdy[sel_tag_id];\n                                  ^\n%Warning-WIDTH: data/full_repos/permissive/463481430/RTL/core/rib.v:130: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s FUNCREF \'onehot2int\' generates 32 bits.\n                                                                       : ... In instance SLAVE_SEL\n                sel_tag_id <= onehot2int(sel_tag);\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/463481430/RTL/core/rib.v:146: Bit extraction of array[2:0] requires 2 bit index, not 8 bits.\n                                                                       : ... In instance SLAVE_SEL\n    assign o_ribm_rdata = default_cs ? i_ribd_rdata : ribs_rdata[sel_tag_id];\n                                                                ^\n%Error: Exiting due to 5 warning(s)\n'
module SLAVE_SEL #(
    parameter slaves = 3
)(
    input wire i_clk,
    input wire i_rstn,

    input wire [8*slaves-1:0] i_slave_mask,


    input wire[31:0]            i_ribm_addr,
    input wire                  i_ribm_wrcs,
    input wire[3:0]             i_ribm_mask,
    input wire[31:0]            i_ribm_wdata,
    output wire[31:0]           o_ribm_rdata,
    input wire                  i_ribm_req,
    output wire                 o_ribm_gnt,
    output wire                 o_ribm_rsp,
    input wire                  i_ribm_rdy,



    output wire[32*slaves-1:0]  o_ribs_addr,
    output wire[slaves-1:0]     o_ribs_wrcs,
    output wire[4*slaves-1:0]   o_ribs_mask,
    output wire[32*slaves-1:0]  o_ribs_wdata,
    input wire[32*slaves-1:0]   i_ribs_rdata,
    output wire[slaves-1:0]     o_ribs_req, 
    input wire[slaves-1:0]      i_ribs_gnt, 
    input wire[slaves-1:0]      i_ribs_rsp, 
    output wire[slaves-1:0]     o_ribs_rdy,


    output wire[31:0]           o_ribd_addr,
    output wire                 o_ribd_wrcs,
    output wire[3:0]            o_ribd_mask,
    output wire[31:0]           o_ribd_wdata,
    input wire[31:0]            i_ribd_rdata,
    output wire                 o_ribd_req, 
    input wire                  i_ribd_gnt, 
    input wire                  i_ribd_rsp, 
    output wire                 o_ribd_rdy

);
    wire[31:0] ribs_rdata[slaves-1:0];
    generate
        genvar j;
        for(j=0;j<slaves;j=j+1)begin
            assign ribs_rdata[j] = i_ribs_rdata[32*j+31:32*j];
        end
    endgenerate



    function integer onehot2int;
        input[slaves-1:0] onehot;
        integer j;
        begin
            onehot2int = 0;
            for(j=0;j<slaves;j=j+1)begin
                if(onehot[j])begin
                    onehot2int = j;
                end
            end
        end
    endfunction



    wire[slaves-1:0] sel_tag;
    generate
        genvar i;
        for(i=0;i<slaves;i=i+1) begin:gen_sel_tag

            assign sel_tag[i] = (i_ribm_addr[31:24] == i_slave_mask[8*i+7:8*i]);

            assign o_ribs_addr[32*i+31:32*i] = {8'b0,i_ribm_addr[23:0]};
            assign o_ribs_wrcs[i] = i_ribm_wrcs;
            assign o_ribs_mask[4*i+3:4*i] = i_ribm_mask;
            assign o_ribs_wdata[32*i+31:32*i] = i_ribm_wdata;

            assign o_ribs_req[i] = i_ribm_req & sel_tag[i];
            
        end
    endgenerate

    assign o_ribm_gnt = (|i_ribs_gnt) | i_ribd_gnt;

    assign o_ribm_rsp = (|i_ribs_rsp) | i_ribd_rsp;


    assign o_ribd_addr = i_ribm_addr;
    assign o_ribd_wrcs = i_ribm_wrcs;
    assign o_ribd_mask = i_ribm_mask;
    assign o_ribd_wdata = i_ribm_wdata;

    assign o_ribd_req = i_ribm_req & (~(|sel_tag));
    
    




    reg default_cs;
    reg[7:0] sel_tag_id;
    wire handshake_rdy = i_ribm_req & o_ribm_gnt;

    wire access_rdy = o_ribm_rsp;
    reg handshake_rdy_last;

    wire trans_finish = handshake_rdy_last & access_rdy;
    always @(posedge i_clk or negedge i_rstn) begin
        if(~i_rstn)begin
            handshake_rdy_last <= 0;
            sel_tag_id <= 0;
            default_cs<=1;
        end
        else begin

            if(access_rdy | (~handshake_rdy_last))begin
                handshake_rdy_last <= handshake_rdy;
                sel_tag_id <= onehot2int(sel_tag);
                default_cs <= ~(|sel_tag);
            end
        end
    end


    generate
        for(i=0;i<slaves;i=i+1) begin:gen_ribs_rdata
            assign o_ribs_rdy[i] = default_cs ? 0 : (i_ribm_rdy & (sel_tag_id == i));
        end
    endgenerate

    assign o_ribd_rdy = i_ribm_rdy & default_cs;


    assign o_ribm_rdata = default_cs ? i_ribd_rdata : ribs_rdata[sel_tag_id];

endmodule
module SLAVE_SEL #(
    parameter slaves = 3
)(
    input wire i_clk,
    input wire i_rstn,

    input wire [8*slaves-1:0] i_slave_mask,


    input wire[31:0]            i_ribm_addr,
    input wire                  i_ribm_wrcs,
    input wire[3:0]             i_ribm_mask,
    input wire[31:0]            i_ribm_wdata,
    output wire[31:0]           o_ribm_rdata,
    input wire                  i_ribm_req,
    output wire                 o_ribm_gnt,
    output wire                 o_ribm_rsp,
    input wire                  i_ribm_rdy,



    output wire[32*slaves-1:0]  o_ribs_addr,
    output wire[slaves-1:0]     o_ribs_wrcs,
    output wire[4*slaves-1:0]   o_ribs_mask,
    output wire[32*slaves-1:0]  o_ribs_wdata,
    input wire[32*slaves-1:0]   i_ribs_rdata,
    output wire[slaves-1:0]     o_ribs_req, 
    input wire[slaves-1:0]      i_ribs_gnt, 
    input wire[slaves-1:0]      i_ribs_rsp, 
    output wire[slaves-1:0]     o_ribs_rdy,


    output wire[31:0]           o_ribd_addr,
    output wire                 o_ribd_wrcs,
    output wire[3:0]            o_ribd_mask,
    output wire[31:0]           o_ribd_wdata,
    input wire[31:0]            i_ribd_rdata,
    output wire                 o_ribd_req, 
    input wire                  i_ribd_gnt, 
    input wire                  i_ribd_rsp, 
    output wire                 o_ribd_rdy

);

    wire[31:0] ribs_rdata[slaves-1:0];
    generate
        genvar j;
        for(j=0;j<slaves;j=j+1)begin
            assign ribs_rdata[j] = i_ribs_rdata[32*j+31:32*j];
        end
    endgenerate



    function integer onehot2int;
        input[slaves-1:0] onehot;
        integer j;
        begin
            onehot2int = 0;
            for(j=0;j<slaves;j=j+1)begin
                if(onehot[j])begin
                    onehot2int = j;
                end
            end
        end
    endfunction



    wire[slaves-1:0] sel_tag;
    generate
        genvar i;
        for(i=0;i<slaves;i=i+1) begin:gen_sel_tag

            assign sel_tag[i] = (i_ribm_addr[31:24] == i_slave_mask[8*i+7:8*i]);

            assign o_ribs_addr[32*i+31:32*i] = {8'b0,i_ribm_addr[23:0]};
            assign o_ribs_wrcs[i] = i_ribm_wrcs;
            assign o_ribs_mask[4*i+3:4*i] = i_ribm_mask;
            assign o_ribs_wdata[32*i+31:32*i] = i_ribm_wdata;

            assign o_ribs_req[i] = i_ribm_req & sel_tag[i];
            
        end
    endgenerate

    assign o_ribm_gnt = (|i_ribs_gnt) | i_ribd_gnt;

    assign o_ribm_rsp = (|i_ribs_rsp) | i_ribd_rsp;


    assign o_ribd_addr = i_ribm_addr;
    assign o_ribd_wrcs = i_ribm_wrcs;
    assign o_ribd_mask = i_ribm_mask;
    assign o_ribd_wdata = i_ribm_wdata;

    assign o_ribd_req = i_ribm_req & (~(|sel_tag));
    
    




    reg default_cs;
    reg[7:0] sel_tag_id;
    wire handshake_rdy = i_ribm_req & o_ribm_gnt;

    wire access_rdy = o_ribm_rsp;
    reg handshake_rdy_last;

    wire trans_finish = handshake_rdy_last & access_rdy;
    always @(posedge i_clk or negedge i_rstn) begin
        if(~i_rstn)begin
            handshake_rdy_last <= 0;
            sel_tag_id <= 0;
            default_cs<=1;
        end
        else begin

            if(access_rdy | (~handshake_rdy_last))begin
                handshake_rdy_last <= handshake_rdy;
                sel_tag_id <= onehot2int(sel_tag);
                default_cs <= ~(|sel_tag);
            end
        end
    end


    generate
        for(i=0;i<slaves;i=i+1) begin:gen_ribs_rdata
            assign o_ribs_rdy[i] = default_cs ? 0 : (i_ribm_rdy & (sel_tag_id == i));
        end
    endgenerate

    assign o_ribd_rdy = i_ribm_rdy & default_cs;


    assign o_ribm_rdata = default_cs ? i_ribd_rdata : ribs_rdata[sel_tag_id];

endmodule