data/full_repos/permissive/528252229/id_ex.v
1: b'%Error: data/full_repos/permissive/528252229/id_ex.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/528252229,data/full_repos/permissive/528252229/defines.v\n             data/full_repos/permissive/528252229,data/full_repos/permissive/528252229/defines.v.v\n             data/full_repos/permissive/528252229,data/full_repos/permissive/528252229/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/528252229/id_ex.v:10: Define or directive not defined: \'`AluOpBus\'\n input wire[`AluOpBus]          id_aluop,  \n            ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:10: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`AluOpBus]          id_aluop,  \n                     ^\n%Error: data/full_repos/permissive/528252229/id_ex.v:11: Define or directive not defined: \'`AluSelBus\'\n input wire[`AluSelBus]         id_alusel,  \n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:12: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus]            id_reg1,  \n            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:13: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus]            id_reg2,\n            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:14: Define or directive not defined: \'`RegAddrBus\'\n input wire[`RegAddrBus]        id_wd,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:15: Define or directive not defined: \'`WriteBus\'\n input wire[`WriteBus]           id_wreg,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:16: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus]    id_return_addr, \n            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:17: Define or directive not defined: \'`RegBus\'\n input wire[`RegBus]    id_inst,\n            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:18: Define or directive not defined: \'`InstAddrBus\'\n input wire[`InstAddrBus]     id_pc,\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:19: Define or directive not defined: \'`StopBus\'\n input wire[`StopBus]            stall,\n            ^~~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:23: Define or directive not defined: \'`AluOpBus\'\n output reg[`AluOpBus]          ex_aluop,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:24: Define or directive not defined: \'`AluSelBus\'\n output reg[`AluSelBus]         ex_alusel,\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:25: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus]            ex_reg1,\n            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:26: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus]            ex_reg2,\n            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:27: Define or directive not defined: \'`RegAddrBus\'\n output reg[`RegAddrBus]        ex_wd,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:28: Define or directive not defined: \'`WriteBus\'\n output reg[`WriteBus]           ex_wreg,\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:29: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus]    ex_return_addr,\n            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:30: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus]    ex_inst,\n            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:31: Define or directive not defined: \'`RegBus\'\n output reg[`RegBus]          ex_pc\n            ^~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:37: Define or directive not defined: \'`RstDisable\'\n        if(rst == `RstDisable) begin\n                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:38: Define or directive not defined: \'`ALU_OP_NOP\'\n            ex_aluop <= `ALU_OP_NOP;\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:39: Define or directive not defined: \'`ALU_RES_NOP\'\n         ex_alusel <= `ALU_RES_NOP;\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:40: Define or directive not defined: \'`ZeroWord\'\n            ex_reg1 <= `ZeroWord;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:41: Define or directive not defined: \'`ZeroWord\'\n            ex_reg2 <= `ZeroWord;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:42: Define or directive not defined: \'`ZeroRegAddr\'\n            ex_wd <= `ZeroRegAddr;\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:43: Define or directive not defined: \'`WriteDisable\'\n            ex_wreg <= `WriteDisable;\n                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:44: Define or directive not defined: \'`ZeroWord\'\n            ex_return_addr <= `ZeroWord;\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:45: Define or directive not defined: \'`ZeroWord\'\n            ex_inst <= `ZeroWord;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:46: Define or directive not defined: \'`InitialPc\'\n            ex_pc <= `InitialPc;\n                     ^~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:48: Define or directive not defined: \'`Stop\'\n        else if(stall[2] == `Stop && stall[3] == `NoStop) begin\n                            ^~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:48: Define or directive not defined: \'`NoStop\'\n        else if(stall[2] == `Stop && stall[3] == `NoStop) begin\n                                                 ^~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:49: Define or directive not defined: \'`ALU_OP_NOP\'\n            ex_aluop <= `ALU_OP_NOP;\n                        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:50: Define or directive not defined: \'`ALU_RES_NOP\'\n         ex_alusel <= `ALU_RES_NOP;\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:51: Define or directive not defined: \'`ZeroWord\'\n            ex_reg1 <= `ZeroWord;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:52: Define or directive not defined: \'`ZeroWord\'\n            ex_reg2 <= `ZeroWord;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:53: Define or directive not defined: \'`ZeroRegAddr\'\n            ex_wd <= `ZeroRegAddr;\n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:54: Define or directive not defined: \'`WriteDisable\'\n            ex_wreg <= `WriteDisable;\n                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:55: Define or directive not defined: \'`ZeroWord\'\n            ex_return_addr <= `ZeroWord;\n                              ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:56: Define or directive not defined: \'`ZeroWord\'\n            ex_inst <= `ZeroWord;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/528252229/id_ex.v:59: Define or directive not defined: \'`NoStop\'\n        else if(stall[2] == `NoStop) begin\n                            ^~~~~~~\n%Error: Exiting due to 42 error(s)\n'
module id_ex(

	input wire						clk,
	input wire						rst,

	
	
	input wire[`AluOpBus]         	id_aluop,		
	input wire[`AluSelBus]        	id_alusel,		
	input wire[`RegBus]           	id_reg1,		
	input wire[`RegBus]           	id_reg2,
	input wire[`RegAddrBus]       	id_wd,
	input wire[`WriteBus]           id_wreg,
	input wire[`RegBus]				id_return_addr,	
	input wire[`RegBus]				id_inst,
	input wire[`InstAddrBus]	    id_pc,
	input wire[`StopBus]            stall,

	
	
	output reg[`AluOpBus]         	ex_aluop,
	output reg[`AluSelBus]        	ex_alusel,
	output reg[`RegBus]           	ex_reg1,
	output reg[`RegBus]           	ex_reg2,
	output reg[`RegAddrBus]       	ex_wd,
	output reg[`WriteBus]           ex_wreg,
	output reg[`RegBus]				ex_return_addr,
	output reg[`RegBus]				ex_inst,
	output reg[`RegBus]	       		ex_pc
);



    always @(posedge clk) begin
        if(rst == `RstDisable) begin
            ex_aluop <= `ALU_OP_NOP;
	        ex_alusel <= `ALU_RES_NOP;
            ex_reg1 <= `ZeroWord;
            ex_reg2 <= `ZeroWord;
            ex_wd <= `ZeroRegAddr;
            ex_wreg <= `WriteDisable;
            ex_return_addr <= `ZeroWord;
            ex_inst <= `ZeroWord;
            ex_pc <= `InitialPc;
        end 
        else if(stall[2] == `Stop && stall[3] == `NoStop) begin
            ex_aluop <= `ALU_OP_NOP;
	        ex_alusel <= `ALU_RES_NOP;
            ex_reg1 <= `ZeroWord;
            ex_reg2 <= `ZeroWord;
            ex_wd <= `ZeroRegAddr;
            ex_wreg <= `WriteDisable;
            ex_return_addr <= `ZeroWord;
            ex_inst <= `ZeroWord;
            ex_pc <= id_pc;
        end 
        else if(stall[2] == `NoStop) begin
            ex_aluop <= id_aluop; 
	        ex_alusel <= id_alusel;
            ex_reg1 <= id_reg1;
            ex_reg2 <= id_reg2;
            ex_wd <= id_wd;
            ex_wreg <= id_wreg;
            ex_return_addr <= id_return_addr;
            ex_inst <= id_inst;
            ex_pc <= id_pc;
        end
    end

endmodule
module id_ex(

	input wire						clk,
	input wire						rst,

	
	
	input wire[`AluOpBus]         	id_aluop,		
	input wire[`AluSelBus]        	id_alusel,		
	input wire[`RegBus]           	id_reg1,		
	input wire[`RegBus]           	id_reg2,
	input wire[`RegAddrBus]       	id_wd,
	input wire[`WriteBus]           id_wreg,
	input wire[`RegBus]				id_return_addr,	
	input wire[`RegBus]				id_inst,
	input wire[`InstAddrBus]	    id_pc,
	input wire[`StopBus]            stall,

	
	
	output reg[`AluOpBus]         	ex_aluop,
	output reg[`AluSelBus]        	ex_alusel,
	output reg[`RegBus]           	ex_reg1,
	output reg[`RegBus]           	ex_reg2,
	output reg[`RegAddrBus]       	ex_wd,
	output reg[`WriteBus]           ex_wreg,
	output reg[`RegBus]				ex_return_addr,
	output reg[`RegBus]				ex_inst,
	output reg[`RegBus]	       		ex_pc
);




    always @(posedge clk) begin
        if(rst == `RstDisable) begin
            ex_aluop <= `ALU_OP_NOP;
	        ex_alusel <= `ALU_RES_NOP;
            ex_reg1 <= `ZeroWord;
            ex_reg2 <= `ZeroWord;
            ex_wd <= `ZeroRegAddr;
            ex_wreg <= `WriteDisable;
            ex_return_addr <= `ZeroWord;
            ex_inst <= `ZeroWord;
            ex_pc <= `InitialPc;
        end 
        else if(stall[2] == `Stop && stall[3] == `NoStop) begin
            ex_aluop <= `ALU_OP_NOP;
	        ex_alusel <= `ALU_RES_NOP;
            ex_reg1 <= `ZeroWord;
            ex_reg2 <= `ZeroWord;
            ex_wd <= `ZeroRegAddr;
            ex_wreg <= `WriteDisable;
            ex_return_addr <= `ZeroWord;
            ex_inst <= `ZeroWord;
            ex_pc <= id_pc;
        end 
        else if(stall[2] == `NoStop) begin
            ex_aluop <= id_aluop; 
	        ex_alusel <= id_alusel;
            ex_reg1 <= id_reg1;
            ex_reg2 <= id_reg2;
            ex_wd <= id_wd;
            ex_wreg <= id_wreg;
            ex_return_addr <= id_return_addr;
            ex_inst <= id_inst;
            ex_pc <= id_pc;
        end
    end

endmodule