data/full_repos/permissive/52196097/DSP/Radar_DSP/FPGA/memory.v
data/verilator_xmls/9add9e9d-187d-401c-87cc-791525828010.xml
module memory
#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=11)
(
	input [(ADDR_WIDTH-1):0] addr_a, addr_b,
	input clk, 
	output reg [(DATA_WIDTH-1):0] q_a, q_b
);


	reg [DATA_WIDTH-1:0] rom[2**ADDR_WIDTH-1:0];







	initial
	begin
		$readmemb("Window_Constants.txt", rom);
	end

	always @ (posedge clk)
	begin
		q_a <= rom[addr_a];
		q_b <= rom[addr_b];
	end

endmodule
module memory
#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=11)
(
	input [(ADDR_WIDTH-1):0] addr_a, addr_b,
	input clk, 
	output reg [(DATA_WIDTH-1):0] q_a, q_b
);



	reg [DATA_WIDTH-1:0] rom[2**ADDR_WIDTH-1:0];







	initial
	begin
		$readmemb("Window_Constants.txt", rom);
	end

	always @ (posedge clk)
	begin
		q_a <= rom[addr_a];
		q_b <= rom[addr_b];
	end

endmodule