data/full_repos/permissive/487568919/basic_verilog/true_single_port_write_first_ram.sv
1: b'%Error: data/full_repos/permissive/487568919/basic_verilog/true_single_port_write_first_ram.sv:93: Cannot find include file: clogb2.svh\n  `include "clogb2.svh" \n           ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/487568919/basic_verilog,data/full_repos/permissive/487568919/clogb2.svh\n             data/full_repos/permissive/487568919/basic_verilog,data/full_repos/permissive/487568919/clogb2.svh.v\n             data/full_repos/permissive/487568919/basic_verilog,data/full_repos/permissive/487568919/clogb2.svh.sv\n             clogb2.svh\n             clogb2.svh.v\n             clogb2.svh.sv\n             obj_dir/clogb2.svh\n             obj_dir/clogb2.svh.v\n             obj_dir/clogb2.svh.sv\n%Error: Exiting due to 1 error(s)\n'
module true_single_port_write_first_ram #( parameter
  RAM_WIDTH = 16,
  RAM_DEPTH = 8,


  RAM_STYLE = "",
  INIT_FILE = ""
)(
  input clka,
  input [clogb2(RAM_DEPTH-1)-1:0] addra,
  input ena,
  input wea,
  input [RAM_WIDTH-1:0] dina,
  output [RAM_WIDTH-1:0] douta
);












  (* ramstyle = RAM_STYLE *) logic [RAM_WIDTH-1:0] data_mem [RAM_DEPTH-1:0];


  logic [RAM_WIDTH-1:0] ram_data_a = {RAM_WIDTH{1'b0}};


  generate
    if (INIT_FILE != "") begin: use_init_file
      initial
        $readmemh(INIT_FILE, data_mem, 0, RAM_DEPTH-1);
    end else begin: init_bram_to_zero
      integer i;
      initial begin
        for (i=0; i<RAM_DEPTH; i=i+1 ) begin
          data_mem[i] = {RAM_WIDTH{1'b0}};
        end
      end
    end
  endgenerate

  always @(posedge clka) begin
    if (ena) begin
      if (wea) begin
        data_mem[addra] <= dina;
        ram_data_a <= dina;
      end else begin
        ram_data_a <= data_mem[addra];
      end
    end
  end


  assign douta = ram_data_a;

  `include "clogb2.svh"

endmodule
module true_single_port_write_first_ram #( parameter
  RAM_WIDTH = 16,
  RAM_DEPTH = 8,


  RAM_STYLE = "",
  INIT_FILE = ""
)(
  input clka,
  input [clogb2(RAM_DEPTH-1)-1:0] addra,
  input ena,
  input wea,
  input [RAM_WIDTH-1:0] dina,
  output [RAM_WIDTH-1:0] douta
);













  (* ramstyle = RAM_STYLE *) logic [RAM_WIDTH-1:0] data_mem [RAM_DEPTH-1:0];


  logic [RAM_WIDTH-1:0] ram_data_a = {RAM_WIDTH{1'b0}};


  generate
    if (INIT_FILE != "") begin: use_init_file
      initial
        $readmemh(INIT_FILE, data_mem, 0, RAM_DEPTH-1);
    end else begin: init_bram_to_zero
      integer i;
      initial begin
        for (i=0; i<RAM_DEPTH; i=i+1 ) begin
          data_mem[i] = {RAM_WIDTH{1'b0}};
        end
      end
    end
  endgenerate

  always @(posedge clka) begin
    if (ena) begin
      if (wea) begin
        data_mem[addra] <= dina;
        ram_data_a <= dina;
      end else begin
        ram_data_a <= data_mem[addra];
      end
    end
  end


  assign douta = ram_data_a;

  `include "clogb2.svh"

endmodule