data/full_repos/permissive/455223995/src/slzw_axi4_master.v
1: b'%Warning-WIDTH: data/full_repos/permissive/455223995/src/slzw_axi4_master.v:145: Operator AND expects 32 or 6 bits on the RHS, but RHS\'s NEQ generates 1 bits.\n                                                                               : ... In instance slzw_axi4_master\nif ((USRPORTWIDTH & (USRPORTWIDTH-1) != 0) || (USRPORTWIDTH > MAXUSRPORTWIDTH) || (USRPORTWIDTH < MINUSRPORTWIDTH))\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/455223995/src/slzw_axi4_master.v:145: Logical Operator LOGOR expects 1 bit on the LHS, but LHS\'s AND generates 32 or 6 bits.\n                                                                               : ... In instance slzw_axi4_master\nif ((USRPORTWIDTH & (USRPORTWIDTH-1) != 0) || (USRPORTWIDTH > MAXUSRPORTWIDTH) || (USRPORTWIDTH < MINUSRPORTWIDTH))\n                                           ^~\n%Error: data/full_repos/permissive/455223995/src/slzw_axi4_master.v:252: Cannot find file containing module: \'slzw_fifo\'\n  slzw_fifo\n  ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/455223995/src,data/full_repos/permissive/455223995/slzw_fifo\n             data/full_repos/permissive/455223995/src,data/full_repos/permissive/455223995/slzw_fifo.v\n             data/full_repos/permissive/455223995/src,data/full_repos/permissive/455223995/slzw_fifo.sv\n             slzw_fifo\n             slzw_fifo.v\n             slzw_fifo.sv\n             obj_dir/slzw_fifo\n             obj_dir/slzw_fifo.v\n             obj_dir/slzw_fifo.sv\n%Warning-WIDTH: data/full_repos/permissive/455223995/src/slzw_axi4_master.v:293: Operator ADD expects 32 bits on the LHS, but LHS\'s SEL generates 30 bits.\n                                                                               : ... In instance slzw_axi4_master\n    rx_len_words                       <= rx_len[31:2] + {29\'h0, |rx_len[1:0]};  \n                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/455223995/src/slzw_axi4_master.v:293: Operator ADD expects 32 bits on the RHS, but RHS\'s REPLICATE generates 30 bits.\n                                                                               : ... In instance slzw_axi4_master\n    rx_len_words                       <= rx_len[31:2] + {29\'h0, |rx_len[1:0]};  \n                                                       ^\n%Warning-WIDTH: data/full_repos/permissive/455223995/src/slzw_axi4_master.v:329: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'rx_words_to_boundary\' generates 9 bits.\n                                                                               : ... In instance slzw_axi4_master\n      remaining_word_count             <= rx_len_words - rx_words_to_boundary;\n                                                       ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/455223995/src/slzw_axi4_master.v:349: Unsized numbers/parameters not allowed in concatenations.\n                                                                                     : ... In instance slzw_axi4_master\n          araddr                       <= araddr + {(arlen + 1), 2\'b00};\n                                                           ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/455223995/src/slzw_axi4_master.v:349: Unsized numbers/parameters not allowed in replications.\n                                                                                     : ... In instance slzw_axi4_master\n          araddr                       <= araddr + {(arlen + 1), 2\'b00};\n                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/455223995/src/slzw_axi4_master.v:358: Operator SUB expects 32 bits on the RHS, but RHS\'s VARREF \'next_burst_size\' generates 8 bits.\n                                                                               : ... In instance slzw_axi4_master\n          remaining_word_count         <= remaining_word_count - next_burst_size;\n                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/455223995/src/slzw_axi4_master.v:341: Operator LTE expects 32 or 9 bits on the LHS, but LHS\'s VARREF \'rx_fifo_count\' generates 8 bits.\n                                                                               : ... In instance slzw_axi4_master\n      if (remaining_word_count != 0 && rx_fifo_count <= (RXFIFODEPTH-DEFAULTBURSTSIZE))\n                                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/455223995/src/slzw_axi4_master.v:381: Operator ADD expects 32 or 6 bits on the LHS, but LHS\'s VARREF \'user_rd_byte_count\' generates 2 bits.\n                                                                               : ... In instance slzw_axi4_master\n      user_rd_byte_count               <= user_rd_byte_count + USRPORTWIDTH/8;\n                                                             ^\n%Warning-WIDTH: data/full_repos/permissive/455223995/src/slzw_axi4_master.v:381: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 or 6 bits.\n                                                                               : ... In instance slzw_axi4_master\n      user_rd_byte_count               <= user_rd_byte_count + USRPORTWIDTH/8;\n                                       ^~\n%Error: Exiting due to 1 error(s), 11 warning(s)\n'
module slzw_axi4_master
#(parameter
  RXFIFODEPTH                          = 256,
  USRPORTWIDTH                         = 32,
  DEFAULTBURSTSIZE                     = 128,
  DEFAULTARUSER                        = 1'b1,
  DEFAULTARCACHE                       = 4'b1110,
  DEFAULTPROT                          = 3'b000
)
(
  input                                aclk,
  input                                aresetn,


  input                                clear,
  input                                start,

  input      [31:0]                    rx_start_addr,
  input      [31:0]                    rx_len,
  input      [31:0]                    tx_start_addr,
  input      [31:0]                    tx_len,

  input                                user_read_byte,
  output     [USRPORTWIDTH-1:0]        user_read_data,
  output                               user_read_data_valid,

  input                                user_write_byte,
  input       [7:0]                    user_write_data,
  output                               user_write_ready,

  output                               busy,





  output     [31:0]                    awaddr,
  output      [7:0]                    awlen,
  output      [2:0]                    awprot,
  output reg                           awvalid,
  input                                awready,



  output     [31:0]                    wdata,
  output                               wlast,
  output reg                           wvalid,
  input                                wready,



  input                                bvalid,
  output                               bready,



  output reg [31:0]                    araddr,
  output reg  [7:0]                    arlen,
  output      [3:0]                    arcache,
  output                               aruser,
  output      [2:0]                    arprot,
  output reg                           arvalid,
  input                                arready,



  input      [31:0]                    rdata,
  input                                rvalid,
  output                               rready
);






localparam                             MAXUSRPORTWIDTH   = 32;
localparam                             MINUSRPORTWIDTH   =  8;
localparam                             MAXAXIBURSTSIZE   = 256;
localparam                             LOG2MAXAXIBURST   = $clog2(MAXAXIBURSTSIZE);
localparam                             LOG2BURSTSIZE     = $clog2(DEFAULTBURSTSIZE);








generate
if (DEFAULTBURSTSIZE > MAXAXIBURSTSIZE || DEFAULTBURSTSIZE < 1 ||
   ((DEFAULTBURSTSIZE & (DEFAULTBURSTSIZE-1)) != 0))
begin
  initial
  begin
    $display("**Runtime error for invalid DEFAULTBURSTSIZE parameter value %0d", DEFAULTBURSTSIZE);
    $finish(1);
  end
end
endgenerate


generate
if ((USRPORTWIDTH & (USRPORTWIDTH-1) != 0) || (USRPORTWIDTH > MAXUSRPORTWIDTH) || (USRPORTWIDTH < MINUSRPORTWIDTH))
begin
  initial
  begin
    $display("**Runtime error for invalid USRPORTWIDTH parameter value %0d", USRPORTWIDTH);
    $finish(1);
  end
end
endgenerate







reg                                    rbusy;
reg   [1:0]                            user_rd_byte_count;
reg  [31:0]                            remaining_word_count;
reg  [31:0]                            rx_outstanding_count;
reg  [LOG2MAXAXIBURST-1:0]             rx_fifo_count;
reg  [31:0]                            rx_len_int;
reg  [31:0]                            rx_len_words;
reg   [8:0]                            rx_words_to_boundary;





wire                                   clk;
wire                                   reset_n;

wire   [31:0]                          user_read_data_int;

wire                                   rx_empty;
wire                                   rx_full;

wire                                   rx_fifo_rd;
wire                                   rx_fifo_clr;
wire   [31:0]                          rx_fifo_data;

wire   [31:0]                          rx_start_addr_int;

wire                                   remain_count_gt_burst;
wire   [LOG2MAXAXIBURST-1:0]           next_burst_size;

wire   [1:0]                           user_rd_byte_count_cmp;





assign clk                             = aclk;
assign reset_n                         = aresetn;

assign busy                            = rbusy | ~rx_empty;


assign awprot                          = DEFAULTPROT;
assign arprot                          = DEFAULTPROT;
assign arcache                         = DEFAULTARCACHE;
assign aruser                          = DEFAULTARUSER;

assign bready                          = 1'b1;
assign rready                          = 1'b1;




assign user_rd_byte_count_cmp          = (USRPORTWIDTH == 32) ? 2'b00 :
                                         (USRPORTWIDTH == 16) ? 2'b10 :
                                                                2'b11 ;


assign rx_fifo_rd                      = ~rx_empty & user_read_byte & (user_rd_byte_count == user_rd_byte_count_cmp);


assign rx_fifo_clr                     = clear;


assign user_read_data_valid            = ~rx_empty;



assign user_read_data_int              = (user_rd_byte_count == 2'b11) ? {rx_fifo_data[23:0], rx_fifo_data[31:24]} :
                                         (user_rd_byte_count == 2'b10) ? {rx_fifo_data[15:0], rx_fifo_data[31:16]} :
                                         (user_rd_byte_count == 2'b01) ? {rx_fifo_data[7:0],  rx_fifo_data[31:8]}  :
                                                                         {rx_fifo_data[31:0]};


assign user_read_data                  = user_read_data_int[USRPORTWIDTH-1:0];


assign rx_start_addr_int               = {rx_start_addr[31:2], 2'b00};


assign remain_count_gt_burst           = (remaining_word_count > DEFAULTBURSTSIZE) ? 1'b1 : 1'b0;



assign next_burst_size                 = remain_count_gt_burst ? DEFAULTBURSTSIZE[LOG2MAXAXIBURST-1:0] :
                                                                 remaining_word_count[LOG2MAXAXIBURST-1:0];





  slzw_fifo
  #(
     .DEPTH                            (RXFIFODEPTH),
     .WIDTH                            (32),
     .NEARLYFULL                       (128)
  ) rx_fifo
  (
    .clk                               (aclk),
    .reset_n                           (aresetn),

    .clr                               (rx_fifo_clr),

    .write                             (rvalid),
    .wdata                             (rdata),

    .read                              (rx_fifo_rd),
    .rdata                             (rx_fifo_data),

    .empty                             (rx_empty),
    .full                              (rx_full),
    .nearly_full                       ()
  );





always @(posedge clk `RESET)
begin
  if (reset_n == 1'b0)
  begin
    user_rd_byte_count                 <= 2'b00;
    rbusy                              <= 1'b0;
    arvalid                            <= 1'b0;
    wvalid                             <= 1'b0;
    awvalid                            <= 1'b0;
  end
  else
  begin


    rx_len_words                       <= rx_len[31:2] + {29'h0, |rx_len[1:0]};





    rx_words_to_boundary               <= DEFAULTBURSTSIZE[LOG2BURSTSIZE:0] - {2'b00, rx_start_addr_int[LOG2BURSTSIZE+1:2]};


    arvalid                            <= (arvalid & ~arready);






    if (rx_fifo_rd)
    begin
      rx_fifo_count                    <= rx_fifo_count - 1;
    end


    if (start & ~rbusy)
    begin
      rbusy                            <= 1'b1;
      arvalid                          <= 1'b1;
      araddr                           <= rx_start_addr_int;


      arlen                            <= rx_words_to_boundary[LOG2MAXAXIBURST-1:0] - 1;


      rx_fifo_count                    <= rx_words_to_boundary[LOG2MAXAXIBURST-1:0];



      remaining_word_count             <= rx_len_words - rx_words_to_boundary;


      rx_outstanding_count             <= rx_len_words;
    end



    if (rbusy)
    begin


      if (remaining_word_count != 0 && rx_fifo_count <= (RXFIFODEPTH-DEFAULTBURSTSIZE))
      begin

        if (~arvalid | arready)
        begin
          arvalid                      <= 1'b1;


          araddr                       <= araddr + {(arlen + 1), 2'b00};


          arlen                        <= next_burst_size - 8'd1;


          rx_fifo_count             <= rx_fifo_count + next_burst_size - {{LOG2MAXAXIBURST-2{1'b0}}, rx_fifo_rd};


          remaining_word_count         <= remaining_word_count - next_burst_size;
        end
      end
    end


    if (rvalid)
    begin
      rx_outstanding_count             <= rx_outstanding_count - 32'd1;


      if (rx_outstanding_count == 32'd1)
      begin
        rbusy                          <= 1'b0;
      end
    end





    if (user_read_byte & user_read_data_valid)
    begin
      user_rd_byte_count               <= user_rd_byte_count + USRPORTWIDTH/8;
    end



    if (clear)
    begin
      user_rd_byte_count               <= 2'b00;
      rbusy                            <= 1'b0;
      arvalid                          <= 1'b0;
      wvalid                           <= 1'b0;
      awvalid                          <= 1'b0;
    end
  end
end




always @(posedge clk `RESET)
begin
  if (reset_n == 1'b0)
  begin
  end
  else
  begin
  end
end

endmodule
module slzw_axi4_master
#(parameter
  RXFIFODEPTH                          = 256,
  USRPORTWIDTH                         = 32,
  DEFAULTBURSTSIZE                     = 128,
  DEFAULTARUSER                        = 1'b1,
  DEFAULTARCACHE                       = 4'b1110,
  DEFAULTPROT                          = 3'b000
)
(
  input                                aclk,
  input                                aresetn,


  input                                clear,
  input                                start,

  input      [31:0]                    rx_start_addr,
  input      [31:0]                    rx_len,
  input      [31:0]                    tx_start_addr,
  input      [31:0]                    tx_len,

  input                                user_read_byte,
  output     [USRPORTWIDTH-1:0]        user_read_data,
  output                               user_read_data_valid,

  input                                user_write_byte,
  input       [7:0]                    user_write_data,
  output                               user_write_ready,

  output                               busy,





  output     [31:0]                    awaddr,
  output      [7:0]                    awlen,
  output      [2:0]                    awprot,
  output reg                           awvalid,
  input                                awready,



  output     [31:0]                    wdata,
  output                               wlast,
  output reg                           wvalid,
  input                                wready,



  input                                bvalid,
  output                               bready,



  output reg [31:0]                    araddr,
  output reg  [7:0]                    arlen,
  output      [3:0]                    arcache,
  output                               aruser,
  output      [2:0]                    arprot,
  output reg                           arvalid,
  input                                arready,



  input      [31:0]                    rdata,
  input                                rvalid,
  output                               rready
);







localparam                             MAXUSRPORTWIDTH   = 32;
localparam                             MINUSRPORTWIDTH   =  8;
localparam                             MAXAXIBURSTSIZE   = 256;
localparam                             LOG2MAXAXIBURST   = $clog2(MAXAXIBURSTSIZE);
localparam                             LOG2BURSTSIZE     = $clog2(DEFAULTBURSTSIZE);








generate
if (DEFAULTBURSTSIZE > MAXAXIBURSTSIZE || DEFAULTBURSTSIZE < 1 ||
   ((DEFAULTBURSTSIZE & (DEFAULTBURSTSIZE-1)) != 0))
begin
  initial
  begin
    $display("**Runtime error for invalid DEFAULTBURSTSIZE parameter value %0d", DEFAULTBURSTSIZE);
    $finish(1);
  end
end
endgenerate


generate
if ((USRPORTWIDTH & (USRPORTWIDTH-1) != 0) || (USRPORTWIDTH > MAXUSRPORTWIDTH) || (USRPORTWIDTH < MINUSRPORTWIDTH))
begin
  initial
  begin
    $display("**Runtime error for invalid USRPORTWIDTH parameter value %0d", USRPORTWIDTH);
    $finish(1);
  end
end
endgenerate







reg                                    rbusy;
reg   [1:0]                            user_rd_byte_count;
reg  [31:0]                            remaining_word_count;
reg  [31:0]                            rx_outstanding_count;
reg  [LOG2MAXAXIBURST-1:0]             rx_fifo_count;
reg  [31:0]                            rx_len_int;
reg  [31:0]                            rx_len_words;
reg   [8:0]                            rx_words_to_boundary;





wire                                   clk;
wire                                   reset_n;

wire   [31:0]                          user_read_data_int;

wire                                   rx_empty;
wire                                   rx_full;

wire                                   rx_fifo_rd;
wire                                   rx_fifo_clr;
wire   [31:0]                          rx_fifo_data;

wire   [31:0]                          rx_start_addr_int;

wire                                   remain_count_gt_burst;
wire   [LOG2MAXAXIBURST-1:0]           next_burst_size;

wire   [1:0]                           user_rd_byte_count_cmp;





assign clk                             = aclk;
assign reset_n                         = aresetn;

assign busy                            = rbusy | ~rx_empty;


assign awprot                          = DEFAULTPROT;
assign arprot                          = DEFAULTPROT;
assign arcache                         = DEFAULTARCACHE;
assign aruser                          = DEFAULTARUSER;

assign bready                          = 1'b1;
assign rready                          = 1'b1;




assign user_rd_byte_count_cmp          = (USRPORTWIDTH == 32) ? 2'b00 :
                                         (USRPORTWIDTH == 16) ? 2'b10 :
                                                                2'b11 ;


assign rx_fifo_rd                      = ~rx_empty & user_read_byte & (user_rd_byte_count == user_rd_byte_count_cmp);


assign rx_fifo_clr                     = clear;


assign user_read_data_valid            = ~rx_empty;



assign user_read_data_int              = (user_rd_byte_count == 2'b11) ? {rx_fifo_data[23:0], rx_fifo_data[31:24]} :
                                         (user_rd_byte_count == 2'b10) ? {rx_fifo_data[15:0], rx_fifo_data[31:16]} :
                                         (user_rd_byte_count == 2'b01) ? {rx_fifo_data[7:0],  rx_fifo_data[31:8]}  :
                                                                         {rx_fifo_data[31:0]};


assign user_read_data                  = user_read_data_int[USRPORTWIDTH-1:0];


assign rx_start_addr_int               = {rx_start_addr[31:2], 2'b00};


assign remain_count_gt_burst           = (remaining_word_count > DEFAULTBURSTSIZE) ? 1'b1 : 1'b0;



assign next_burst_size                 = remain_count_gt_burst ? DEFAULTBURSTSIZE[LOG2MAXAXIBURST-1:0] :
                                                                 remaining_word_count[LOG2MAXAXIBURST-1:0];





  slzw_fifo
  #(
     .DEPTH                            (RXFIFODEPTH),
     .WIDTH                            (32),
     .NEARLYFULL                       (128)
  ) rx_fifo
  (
    .clk                               (aclk),
    .reset_n                           (aresetn),

    .clr                               (rx_fifo_clr),

    .write                             (rvalid),
    .wdata                             (rdata),

    .read                              (rx_fifo_rd),
    .rdata                             (rx_fifo_data),

    .empty                             (rx_empty),
    .full                              (rx_full),
    .nearly_full                       ()
  );





always @(posedge clk `RESET)
begin
  if (reset_n == 1'b0)
  begin
    user_rd_byte_count                 <= 2'b00;
    rbusy                              <= 1'b0;
    arvalid                            <= 1'b0;
    wvalid                             <= 1'b0;
    awvalid                            <= 1'b0;
  end
  else
  begin


    rx_len_words                       <= rx_len[31:2] + {29'h0, |rx_len[1:0]};





    rx_words_to_boundary               <= DEFAULTBURSTSIZE[LOG2BURSTSIZE:0] - {2'b00, rx_start_addr_int[LOG2BURSTSIZE+1:2]};


    arvalid                            <= (arvalid & ~arready);






    if (rx_fifo_rd)
    begin
      rx_fifo_count                    <= rx_fifo_count - 1;
    end


    if (start & ~rbusy)
    begin
      rbusy                            <= 1'b1;
      arvalid                          <= 1'b1;
      araddr                           <= rx_start_addr_int;


      arlen                            <= rx_words_to_boundary[LOG2MAXAXIBURST-1:0] - 1;


      rx_fifo_count                    <= rx_words_to_boundary[LOG2MAXAXIBURST-1:0];



      remaining_word_count             <= rx_len_words - rx_words_to_boundary;


      rx_outstanding_count             <= rx_len_words;
    end



    if (rbusy)
    begin


      if (remaining_word_count != 0 && rx_fifo_count <= (RXFIFODEPTH-DEFAULTBURSTSIZE))
      begin

        if (~arvalid | arready)
        begin
          arvalid                      <= 1'b1;


          araddr                       <= araddr + {(arlen + 1), 2'b00};


          arlen                        <= next_burst_size - 8'd1;


          rx_fifo_count             <= rx_fifo_count + next_burst_size - {{LOG2MAXAXIBURST-2{1'b0}}, rx_fifo_rd};


          remaining_word_count         <= remaining_word_count - next_burst_size;
        end
      end
    end


    if (rvalid)
    begin
      rx_outstanding_count             <= rx_outstanding_count - 32'd1;


      if (rx_outstanding_count == 32'd1)
      begin
        rbusy                          <= 1'b0;
      end
    end





    if (user_read_byte & user_read_data_valid)
    begin
      user_rd_byte_count               <= user_rd_byte_count + USRPORTWIDTH/8;
    end



    if (clear)
    begin
      user_rd_byte_count               <= 2'b00;
      rbusy                            <= 1'b0;
      arvalid                          <= 1'b0;
      wvalid                           <= 1'b0;
      awvalid                          <= 1'b0;
    end
  end
end




always @(posedge clk `RESET)
begin
  if (reset_n == 1'b0)
  begin
  end
  else
  begin
  end
end

endmodule