data/full_repos/permissive/489075769/test bench/top_tb.v
1: b'%Error: Cannot find file containing module: bench,data/full_repos/permissive/489075769\n        ... Looked in:\n             data/full_repos/permissive/489075769/test/bench,data/full_repos/permissive/489075769\n             data/full_repos/permissive/489075769/test/bench,data/full_repos/permissive/489075769.v\n             data/full_repos/permissive/489075769/test/bench,data/full_repos/permissive/489075769.sv\n             bench,data/full_repos/permissive/489075769\n             bench,data/full_repos/permissive/489075769.v\n             bench,data/full_repos/permissive/489075769.sv\n             obj_dir/bench,data/full_repos/permissive/489075769\n             obj_dir/bench,data/full_repos/permissive/489075769.v\n             obj_dir/bench,data/full_repos/permissive/489075769.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/489075769/test\n%Error: Cannot find file containing module: bench/top_tb.v\n%Error: Exiting due to 3 error(s)\n'
module top_tb;
	reg ACLK;
	reg ARESETn;
	reg AWREADY, AWVALID;
	reg [31:0] i_AWADDR;
	wire [31:0] o_AWADDR;
	reg [2:0] AWPROT;
	reg WVALID, WREADY;
	reg [31:0] i_WDATA;
	reg [3:0] i_WSTRB;  
	wire [3:0] o_WSTRB;
	wire [31:0] o_WDATA;
	reg BVALID, BREADY;
	reg [1:0] i_BRESP;
	wire [1:0] o_BRESP;

	reg ARVALID;
	reg ARREADY;
	reg [2:0] ARPROT;
	reg [31:0] i_ARADDR;
	wire [31:0] o_ARADDR;
	reg RVALID, RREADY;
	reg [31:0] i_RDATA;
	reg [1:0] i_RRESP;
	wire [31:0] o_RDATA;
	wire [1:0] o_RRESP;

	top2 top_uut(ACLK,ARESETn,BREADY, BVALID, i_BRESP, o_BRESP
		     ,WVALID, WREADY, i_WDATA, o_WDATA, i_WSTRB, o_WSTRB
		     ,AWVALID, AWREADY, i_AWADDR, o_AWADDR, AWPROT, ARVALID, ARREADY, ARPROT,
 		     i_ARADDR, o_ARADDR, RVALID, RREADY, i_RDATA, i_RRESP,o_RDATA, o_RRESP);


	initial begin
		ACLK=1'b0;
		forever #5 ACLK=~ACLK;
	end



initial begin
		ARESETn=1'b0;
		ARREADY=1'b0; ARVALID=1'b0;
		RVALID=1'b0; RREADY=1'b0;
		RVALID=1'b0; RREADY=1'b0;
		i_ARADDR= 32'hFFFFFFFF;
		AWPROT= 3'b0;
		i_RDATA=32'hFFFFFFFF;

	end
initial	begin
i_ARADDR = 32'hffffffff;
#5 ARREADY=1'b0;  ARVALID=1'b1;
#5 ARREADY=1'b0;  ARVALID=1'b1;
#5 ARREADY=1'b1;  ARVALID=1'b1;
#5 ARREADY=1'b1;  ARVALID=1'b1;
#5 ARREADY=1'b1;  ARVALID=1'b1;
#200 $finish;
end
endmodule
module top_tb;

	reg ACLK;
	reg ARESETn;
	reg AWREADY, AWVALID;
	reg [31:0] i_AWADDR;
	wire [31:0] o_AWADDR;
	reg [2:0] AWPROT;
	reg WVALID, WREADY;
	reg [31:0] i_WDATA;
	reg [3:0] i_WSTRB;  
	wire [3:0] o_WSTRB;
	wire [31:0] o_WDATA;
	reg BVALID, BREADY;
	reg [1:0] i_BRESP;
	wire [1:0] o_BRESP;

	reg ARVALID;
	reg ARREADY;
	reg [2:0] ARPROT;
	reg [31:0] i_ARADDR;
	wire [31:0] o_ARADDR;
	reg RVALID, RREADY;
	reg [31:0] i_RDATA;
	reg [1:0] i_RRESP;
	wire [31:0] o_RDATA;
	wire [1:0] o_RRESP;

	top2 top_uut(ACLK,ARESETn,BREADY, BVALID, i_BRESP, o_BRESP
		     ,WVALID, WREADY, i_WDATA, o_WDATA, i_WSTRB, o_WSTRB
		     ,AWVALID, AWREADY, i_AWADDR, o_AWADDR, AWPROT, ARVALID, ARREADY, ARPROT,
 		     i_ARADDR, o_ARADDR, RVALID, RREADY, i_RDATA, i_RRESP,o_RDATA, o_RRESP);


	initial begin
		ACLK=1'b0;
		forever #5 ACLK=~ACLK;
	end



initial begin
		ARESETn=1'b0;
		ARREADY=1'b0; ARVALID=1'b0;
		RVALID=1'b0; RREADY=1'b0;
		RVALID=1'b0; RREADY=1'b0;
		i_ARADDR= 32'hFFFFFFFF;
		AWPROT= 3'b0;
		i_RDATA=32'hFFFFFFFF;

	end
initial	begin
i_ARADDR = 32'hffffffff;
#5 ARREADY=1'b0;  ARVALID=1'b1;
#5 ARREADY=1'b0;  ARVALID=1'b1;
#5 ARREADY=1'b1;  ARVALID=1'b1;
#5 ARREADY=1'b1;  ARVALID=1'b1;
#5 ARREADY=1'b1;  ARVALID=1'b1;
#200 $finish;
end
endmodule