data/full_repos/permissive/522095295/fetch.v
data/verilator_xmls/131b27cd-3276-41bd-9311-1833e7a476d8.xml
module fetch
(
   input wire clk,
   input wire reset,
   input wire [31:0] data_i,
   input wire pc_readin,
   input wire [31:0] pc_wd_i,
   output wire [31:0] pc_o
);
   reg [31:0] pc;

   always @ (negedge reset) begin

      pc <= data_i;
   end   

   always @ (posedge pc_readin) begin
      pc <= pc_wd_i;
   end

   assign pc_o = pc;

   initial begin
      pc = 0;
   end
endmodule
module fetch
(
   input wire clk,
   input wire reset,
   input wire [31:0] data_i,
   input wire pc_readin,
   input wire [31:0] pc_wd_i,
   output wire [31:0] pc_o
);

   reg [31:0] pc;

   always @ (negedge reset) begin

      pc <= data_i;
   end   

   always @ (posedge pc_readin) begin
      pc <= pc_wd_i;
   end

   assign pc_o = pc;

   initial begin
      pc = 0;
   end
endmodule