data/full_repos/permissive/461069000/spi/src/edge_detector.v
data/verilator_xmls/969b9698-8243-4f33-8d9d-89cc26bc9e65.xml
module edge_detector(
    input clk,
    input signal,
    output negative_edge,
    output positive_edge);
    

    reg signal_delay;


    always @(posedge clk ) 
    begin
        signal_delay <= signal;
    end

    assign negative_edge = ~signal & signal_delay;
    assign positive_edge = signal & ~signal_delay;


endmodule
module edge_detector(
    input clk,
    input signal,
    output negative_edge,
    output positive_edge);

    

    reg signal_delay;


    always @(posedge clk ) 
    begin
        signal_delay <= signal;
    end

    assign negative_edge = ~signal & signal_delay;
    assign positive_edge = signal & ~signal_delay;


endmodule