data/full_repos/permissive/502540587/TestBench/board_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/502540587/TestBench/board_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n            #5\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/502540587/TestBench/board_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n        #17\n        ^\n%Error: data/full_repos/permissive/502540587/TestBench/board_tb.v:20: Cannot find file containing module: \'GPUBoard\'\n    GPUBoard gpu_board(\n    ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502540587/TestBench,data/full_repos/permissive/502540587/GPUBoard\n             data/full_repos/permissive/502540587/TestBench,data/full_repos/permissive/502540587/GPUBoard.v\n             data/full_repos/permissive/502540587/TestBench,data/full_repos/permissive/502540587/GPUBoard.sv\n             GPUBoard\n             GPUBoard.v\n             GPUBoard.sv\n             obj_dir/GPUBoard\n             obj_dir/GPUBoard.v\n             obj_dir/GPUBoard.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module BoardTB;
    
    reg reset;
    reg clk;

    wire [3:0] oRed;
    wire [3:0] oGreen;
    wire [3:0] oBlue;
    wire oHs;
    wire oVs;

    wire cs_n;
    reg sdi;
    wire sdo;
    wire wp_n;
    wire hld_n;

    GPUBoard gpu_board(
        .clk(clk),
        .reset(reset),

        .cs_n(cs_n),
        .sdi(sdi),
        .sdo(sdo),
        .wp_n(wp_n),
        .hld_n(hld_n),
        
        .oRed(oRed),
        .oBlue(oBlue),
        .oGreen(oGreen),
        .oHs(oHs),
        .oVs(oVs)
    );

    initial begin
        clk = 0;

        forever begin
            #5
            clk = ~clk;
        end
    end





    initial begin
        reset = 1;
        sdi = 1'b0;

        #17
        reset = 0;
    end
endmodule
module BoardTB;

    
    reg reset;
    reg clk;

    wire [3:0] oRed;
    wire [3:0] oGreen;
    wire [3:0] oBlue;
    wire oHs;
    wire oVs;

    wire cs_n;
    reg sdi;
    wire sdo;
    wire wp_n;
    wire hld_n;

    GPUBoard gpu_board(
        .clk(clk),
        .reset(reset),

        .cs_n(cs_n),
        .sdi(sdi),
        .sdo(sdo),
        .wp_n(wp_n),
        .hld_n(hld_n),
        
        .oRed(oRed),
        .oBlue(oBlue),
        .oGreen(oGreen),
        .oHs(oHs),
        .oVs(oVs)
    );

    initial begin
        clk = 0;

        forever begin
            #5
            clk = ~clk;
        end
    end





    initial begin
        reset = 1;
        sdi = 1'b0;

        #17
        reset = 0;
    end
endmodule