data/full_repos/permissive/426864978/lab3/task3/tb_syn_arc4.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task3/tb_syn_arc4.sv:27: Unsupported: Ignoring delay on this delayed statement.\n        forever #5 clk = ~clk;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task3/tb_syn_arc4.sv:41: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_syn_arc4.sv:49: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_syn_arc4.sv:57: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_syn_arc4.sv:65: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_syn_arc4.sv:73: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task3/tb_syn_arc4.sv:81: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_syn_arc4.sv:94: syntax error, unexpected \'@\'\n                @(posedge clk);        \n                ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_syn_arc4.sv:105: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_syn_arc4.sv:108: syntax error, unexpected \'@\'\n            @(posedge clk);   \n            ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_syn_arc4.sv:111: syntax error, unexpected \'@\'\n            @(posedge clk);   \n            ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_syn_arc4.sv:124: syntax error, unexpected \'@\'\n            @(posedge clk);   \n            ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_syn_arc4.sv:128: Unsupported: wait statements\n        wait(tb_syn_arc4.dut.rdy == 1\'b1);\n        ^~~~\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_syn_arc4.sv:148: syntax error, unexpected \'@\'\n        @(negedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_syn_arc4.sv:156: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_syn_arc4.sv:164: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_syn_arc4.sv:172: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/426864978/lab3/task3/tb_syn_arc4.sv:180: Unsupported: Ignoring delay on this delayed statement.\n            #10;\n            ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_syn_arc4.sv:193: syntax error, unexpected \'@\'\n                @(posedge clk);          \n                ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_syn_arc4.sv:204: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_syn_arc4.sv:207: syntax error, unexpected \'@\'\n            @(posedge clk);   \n            ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_syn_arc4.sv:210: syntax error, unexpected \'@\'\n            @(posedge clk);   \n            ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_syn_arc4.sv:224: syntax error, unexpected \'@\'\n            @(posedge clk);   \n            ^\n%Error: data/full_repos/permissive/426864978/lab3/task3/tb_syn_arc4.sv:228: Unsupported: wait statements\n        wait(tb_syn_arc4.dut.rdy == 1\'b1);\n        ^~~~\n%Error: Exiting due to 20 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_syn_arc4();

    logic clk, rst_n, en, rdy, pt_wren, err;
    logic [23:0] key;
    logic [7:0] ct_addr, ct_rddata, pt_addr, pt_rddata, pt_wrdata;
    logic [31:0] tdo;


    logic [7:0] exp_ksa [255:0];
    logic [7:0] exp_pad [255:0];
    logic [7:0] exp_pt [255:0];
    logic [7:0] ciphertext [255:0];
    logic [7:0] pt [255:0];

    arc4 dut(
        .altera_reserved_tms(32'b0),
        .altera_reserved_tck(32'b0),
        .altera_reserved_tdi(32'b0),
        .altera_reserved_tdo(tdo),
        .*
    );

    initial begin
        clk = 1;
        forever #5 clk = ~clk;
    end

    initial begin
        err = 1'b0;


        $readmemh("ksa_res.txt", exp_ksa);
        $readmemh("pad_res.txt", exp_pad);
        $readmemh("prga_res.txt", exp_pt);
        $readmemh("test1.memh", ciphertext);


        rst_n = 1'bx; en = 1'bx;
        #10;
        if (tb_syn_arc4.dut.rdy !== 1'b0) begin
            $display("ERROR 1: Expected rdy is %d, actual rdy is %d", 1'b0, tb_syn_arc4.dut.rdy);
            err = 1'b1;
        end


        rst_n = 1'b0; en = 1'b0; key = 24'h1E4600;
        @(negedge clk);
        if (tb_syn_arc4.dut.rdy !== 1'b0) begin
            $display("ERROR 2: Expected rdy is %d, actual rdy is %d", 1'b0, tb_syn_arc4.dut.rdy);
            err = 1'b1;
        end


        rst_n = 1'b1;
        @(posedge clk);
        if (tb_syn_arc4.dut.rdy !== 1'b0) begin
            $display("ERROR 3: Expected rdy is %d, actual rdy is %d", 1'b0, tb_syn_arc4.dut.rdy);
            err = 1'b1;
        end


        en = 1'b1; ct_rddata = ciphertext[0];
        @(posedge clk);
        if (tb_syn_arc4.dut.rdy !== 1'b1) begin
            $display("ERROR 4: Expected rdy is %d, actual rdy is %d", 1'b1, tb_syn_arc4.dut.rdy);
            err = 1'b1;
        end


        en = 1'b0;
        @(posedge clk);
        if (tb_syn_arc4.dut.rdy !== 1'b0) begin
            $display("ERROR 5: Expected rdy is %d, actual rdy is %d", 1'b0, tb_syn_arc4.dut.rdy);
            err = 1'b1;
        end


        for (int i = 0; i < 256; i++) begin
            #10;
        end

        for (int i = 0; i < 256; i++) begin
            if (tb_syn_arc4.dut.\s|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i] !== i) begin
                $display("INIT MEM[%d] ERR: Expected value is %d, actual value is %d", i[7:0], i, tb_syn_arc4.dut.\s|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i]);
                err = 1'b1;
            end
        end


        for (int i = 0; i < 256; i++)
            for (int j = 0; j < 7; j++)
                @(posedge clk);

        for (int i = 0; i < 256; i++) begin
            if (tb_syn_arc4.dut.\s|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i] !== exp_ksa[i]) begin
                $display("KSA MEM[%d] ERR: Expected value is %d, actual value is %d", i[7:0], exp_ksa[i], tb_syn_arc4.dut.\s|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i]);
                err = 1'b1;
            end
        end


        ct_rddata = ciphertext[0];
        @(posedge clk);

        for (int i = 0; i < 8'h49; i++) begin
            @(posedge clk);
            @(posedge clk);
            ct_rddata = ciphertext[tb_syn_arc4.dut.ct_addr];
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
        end

        @(posedge clk);


        for (int k = 0; k < 8'h49; k++) begin
            @(posedge clk);
            pt[tb_syn_arc4.dut.pt_addr] = tb_syn_arc4.dut.pt_wrdata;
        end

        wait(tb_syn_arc4.dut.rdy == 1'b1);


        for (int i = 0; i < 8'h49; i++) begin
           if (exp_pt[i] !== pt[i]) begin 
                $display("PT[%d] ERROR: Expected pt is %h, actual pt is %h", i[7:0], exp_pt[i], pt[i]);
                err = 1'b1;
            end
        end




        $readmemh("ksa_res2.txt", exp_ksa);
        $readmemh("pad_res2.txt", exp_pad);
        $readmemh("prga_res2.txt", exp_pt);
        $readmemh("test2.memh", ciphertext);


        rst_n = 1'b0; en = 1'b0; key = 24'h000018;
        @(negedge clk);
        if (tb_syn_arc4.dut.rdy !== 1'b0) begin
            $display("ERROR 14: Expected rdy is %d, actual rdy is %d", 1'b0, tb_syn_arc4.dut.rdy);
            err = 1'b1;
        end


        rst_n = 1'b1;
        @(posedge clk);
        if (tb_syn_arc4.dut.rdy !== 1'b0) begin
            $display("ERROR 15: Expected rdy is %d, actual rdy is %d", 1'b0, tb_syn_arc4.dut.rdy);
            err = 1'b1;
        end


        en = 1'b1; ct_rddata = ciphertext[0];
        @(posedge clk);
        if (tb_syn_arc4.dut.rdy !== 1'b1) begin
            $display("ERROR 16: Expected rdy is %d, actual rdy is %d", 1'b1, tb_syn_arc4.dut.rdy);
            err = 1'b1;
        end


        en = 1'b0;
        @(posedge clk);
        if (tb_syn_arc4.dut.rdy !== 1'b0) begin
            $display("ERROR 17: Expected rdy is %d, actual rdy is %d", 1'b0, tb_syn_arc4.dut.rdy);
            err = 1'b1;
        end


        for (int i = 0; i < 256; i++) begin
            #10;
        end

        for (int i = 0; i < 256; i++) begin
            if (tb_syn_arc4.dut.\s|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i] !== i) begin
                $display("INIT 2 MEM[%d] ERR: Expected value is %d, actual value is %d", i[7:0], i, tb_syn_arc4.dut.\s|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i]);
                err = 1'b1;
            end
        end


        for (int i = 0; i < 256; i++)
            for (int j = 0; j < 7; j++)
                @(posedge clk);

        for (int i = 0; i < 256; i++) begin
            if (tb_syn_arc4.dut.\s|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i] !== exp_ksa[i]) begin
                $display("KSA 2 MEM[%d] ERR: Expected value is %d, actual value is %d", i[7:0], exp_ksa[i], tb_syn_arc4.dut.\s|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i]);
                err = 1'b1;
            end
        end


        ct_rddata = ciphertext[0];
        @(posedge clk);

        for (int i = 0; i < 8'd53; i++) begin
            @(posedge clk);
            @(posedge clk);
            ct_rddata = ciphertext[tb_syn_arc4.dut.ct_addr];
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
        end

        @(posedge clk);


        pt[0] = exp_pt[0];
        for (int k = 0; k < 8'd53; k++) begin
            @(posedge clk);
            pt[tb_syn_arc4.dut.pt_addr] = exp_pad[k] ^ ciphertext[k + 8'b1];
        end

        wait(tb_syn_arc4.dut.rdy == 1'b1);


        for (int i = 0; i < 8'd53; i++) begin
           if (exp_pt[i] !== pt[i]) begin 
                $display("PT 2[%d] ERROR: Expected pt is %h, actual pt is %h", i[7:0], exp_pt[i], pt[i]);
                err = 1'b1;
            end
        end

        if (~err)
            $display("SUCCESS: All tests passed.");
        $stop;
    end

endmodule
module tb_syn_arc4();


    logic clk, rst_n, en, rdy, pt_wren, err;
    logic [23:0] key;
    logic [7:0] ct_addr, ct_rddata, pt_addr, pt_rddata, pt_wrdata;
    logic [31:0] tdo;


    logic [7:0] exp_ksa [255:0];
    logic [7:0] exp_pad [255:0];
    logic [7:0] exp_pt [255:0];
    logic [7:0] ciphertext [255:0];
    logic [7:0] pt [255:0];

    arc4 dut(
        .altera_reserved_tms(32'b0),
        .altera_reserved_tck(32'b0),
        .altera_reserved_tdi(32'b0),
        .altera_reserved_tdo(tdo),
        .*
    );

    initial begin
        clk = 1;
        forever #5 clk = ~clk;
    end

    initial begin
        err = 1'b0;


        $readmemh("ksa_res.txt", exp_ksa);
        $readmemh("pad_res.txt", exp_pad);
        $readmemh("prga_res.txt", exp_pt);
        $readmemh("test1.memh", ciphertext);


        rst_n = 1'bx; en = 1'bx;
        #10;
        if (tb_syn_arc4.dut.rdy !== 1'b0) begin
            $display("ERROR 1: Expected rdy is %d, actual rdy is %d", 1'b0, tb_syn_arc4.dut.rdy);
            err = 1'b1;
        end


        rst_n = 1'b0; en = 1'b0; key = 24'h1E4600;
        @(negedge clk);
        if (tb_syn_arc4.dut.rdy !== 1'b0) begin
            $display("ERROR 2: Expected rdy is %d, actual rdy is %d", 1'b0, tb_syn_arc4.dut.rdy);
            err = 1'b1;
        end


        rst_n = 1'b1;
        @(posedge clk);
        if (tb_syn_arc4.dut.rdy !== 1'b0) begin
            $display("ERROR 3: Expected rdy is %d, actual rdy is %d", 1'b0, tb_syn_arc4.dut.rdy);
            err = 1'b1;
        end


        en = 1'b1; ct_rddata = ciphertext[0];
        @(posedge clk);
        if (tb_syn_arc4.dut.rdy !== 1'b1) begin
            $display("ERROR 4: Expected rdy is %d, actual rdy is %d", 1'b1, tb_syn_arc4.dut.rdy);
            err = 1'b1;
        end


        en = 1'b0;
        @(posedge clk);
        if (tb_syn_arc4.dut.rdy !== 1'b0) begin
            $display("ERROR 5: Expected rdy is %d, actual rdy is %d", 1'b0, tb_syn_arc4.dut.rdy);
            err = 1'b1;
        end


        for (int i = 0; i < 256; i++) begin
            #10;
        end

        for (int i = 0; i < 256; i++) begin
            if (tb_syn_arc4.dut.\s|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i] !== i) begin
                $display("INIT MEM[%d] ERR: Expected value is %d, actual value is %d", i[7:0], i, tb_syn_arc4.dut.\s|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i]);
                err = 1'b1;
            end
        end


        for (int i = 0; i < 256; i++)
            for (int j = 0; j < 7; j++)
                @(posedge clk);

        for (int i = 0; i < 256; i++) begin
            if (tb_syn_arc4.dut.\s|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i] !== exp_ksa[i]) begin
                $display("KSA MEM[%d] ERR: Expected value is %d, actual value is %d", i[7:0], exp_ksa[i], tb_syn_arc4.dut.\s|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i]);
                err = 1'b1;
            end
        end


        ct_rddata = ciphertext[0];
        @(posedge clk);

        for (int i = 0; i < 8'h49; i++) begin
            @(posedge clk);
            @(posedge clk);
            ct_rddata = ciphertext[tb_syn_arc4.dut.ct_addr];
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
        end

        @(posedge clk);


        for (int k = 0; k < 8'h49; k++) begin
            @(posedge clk);
            pt[tb_syn_arc4.dut.pt_addr] = tb_syn_arc4.dut.pt_wrdata;
        end

        wait(tb_syn_arc4.dut.rdy == 1'b1);


        for (int i = 0; i < 8'h49; i++) begin
           if (exp_pt[i] !== pt[i]) begin 
                $display("PT[%d] ERROR: Expected pt is %h, actual pt is %h", i[7:0], exp_pt[i], pt[i]);
                err = 1'b1;
            end
        end




        $readmemh("ksa_res2.txt", exp_ksa);
        $readmemh("pad_res2.txt", exp_pad);
        $readmemh("prga_res2.txt", exp_pt);
        $readmemh("test2.memh", ciphertext);


        rst_n = 1'b0; en = 1'b0; key = 24'h000018;
        @(negedge clk);
        if (tb_syn_arc4.dut.rdy !== 1'b0) begin
            $display("ERROR 14: Expected rdy is %d, actual rdy is %d", 1'b0, tb_syn_arc4.dut.rdy);
            err = 1'b1;
        end


        rst_n = 1'b1;
        @(posedge clk);
        if (tb_syn_arc4.dut.rdy !== 1'b0) begin
            $display("ERROR 15: Expected rdy is %d, actual rdy is %d", 1'b0, tb_syn_arc4.dut.rdy);
            err = 1'b1;
        end


        en = 1'b1; ct_rddata = ciphertext[0];
        @(posedge clk);
        if (tb_syn_arc4.dut.rdy !== 1'b1) begin
            $display("ERROR 16: Expected rdy is %d, actual rdy is %d", 1'b1, tb_syn_arc4.dut.rdy);
            err = 1'b1;
        end


        en = 1'b0;
        @(posedge clk);
        if (tb_syn_arc4.dut.rdy !== 1'b0) begin
            $display("ERROR 17: Expected rdy is %d, actual rdy is %d", 1'b0, tb_syn_arc4.dut.rdy);
            err = 1'b1;
        end


        for (int i = 0; i < 256; i++) begin
            #10;
        end

        for (int i = 0; i < 256; i++) begin
            if (tb_syn_arc4.dut.\s|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i] !== i) begin
                $display("INIT 2 MEM[%d] ERR: Expected value is %d, actual value is %d", i[7:0], i, tb_syn_arc4.dut.\s|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i]);
                err = 1'b1;
            end
        end


        for (int i = 0; i < 256; i++)
            for (int j = 0; j < 7; j++)
                @(posedge clk);

        for (int i = 0; i < 256; i++) begin
            if (tb_syn_arc4.dut.\s|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i] !== exp_ksa[i]) begin
                $display("KSA 2 MEM[%d] ERR: Expected value is %d, actual value is %d", i[7:0], exp_ksa[i], tb_syn_arc4.dut.\s|altsyncram_component|auto_generated|altsyncram1|ram_block3a0 .ram_core0.ram_core0.mem[i]);
                err = 1'b1;
            end
        end


        ct_rddata = ciphertext[0];
        @(posedge clk);

        for (int i = 0; i < 8'd53; i++) begin
            @(posedge clk);
            @(posedge clk);
            ct_rddata = ciphertext[tb_syn_arc4.dut.ct_addr];
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
            @(posedge clk);
        end

        @(posedge clk);


        pt[0] = exp_pt[0];
        for (int k = 0; k < 8'd53; k++) begin
            @(posedge clk);
            pt[tb_syn_arc4.dut.pt_addr] = exp_pad[k] ^ ciphertext[k + 8'b1];
        end

        wait(tb_syn_arc4.dut.rdy == 1'b1);


        for (int i = 0; i < 8'd53; i++) begin
           if (exp_pt[i] !== pt[i]) begin 
                $display("PT 2[%d] ERROR: Expected pt is %h, actual pt is %h", i[7:0], exp_pt[i], pt[i]);
                err = 1'b1;
            end
        end

        if (~err)
            $display("SUCCESS: All tests passed.");
        $stop;
    end

endmodule