data/full_repos/permissive/453763315/rom.v
1: b'%Warning-WIDTH: data/full_repos/permissive/453763315/rom.v:12: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 16 bits.\n                                                             : ... In instance rom\n      read <= rom[addr];\n           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module rom(en, addr, read);
  input en;
  input reg [15:0] addr;
  output reg [31:0] read;
  reg [31:0][15:0] rom;




  always @(*) begin
    if (en) begin
      read <= rom[addr];
    end
  end
endmodule
module rom(en, addr, read);

  input en;
  input reg [15:0] addr;
  output reg [31:0] read;
  reg [31:0][15:0] rom;




  always @(*) begin
    if (en) begin
      read <= rom[addr];
    end
  end
endmodule