data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy/Adder 2.v
1: b'%Error: Cannot find file containing module: data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy/Adder\n        ... Looked in:\n             data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy,data/full_repos/permissive/463549945/data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy/Adder\n             data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy,data/full_repos/permissive/463549945/data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy/Adder.v\n             data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy,data/full_repos/permissive/463549945/data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy/Adder.sv\n             data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy/Adder\n             data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy/Adder.v\n             data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy/Adder.sv\n             obj_dir/data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy/Adder\n             obj_dir/data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy/Adder.v\n             obj_dir/data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy/Adder.sv\n%Error: Cannot find file containing module: 2.v\n%Error: Exiting due to 2 error(s)\n'
module add1 ( input a, input b, input cin,   output sum, output cout );


    assign sum  = a ^ b ^ cin        ;
    assign cout = a&b | a&cin | b&cin;

endmodule
module add1 ( input a, input b, input cin,   output sum, output cout );



    assign sum  = a ^ b ^ cin        ;
    assign cout = a&b | a&cin | b&cin;

endmodule