data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_ctu_clk_sync_mux.v
1: b"%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_ctu_clk_sync_mux.v:238: Cannot find file containing module: 'bw_u1_soffi_4x'\nbw_u1_soffi_4x xf0 (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_soffi_4x\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_soffi_4x.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/bw_u1_soffi_4x.sv\n             bw_u1_soffi_4x\n             bw_u1_soffi_4x.v\n             bw_u1_soffi_4x.sv\n             obj_dir/bw_u1_soffi_4x\n             obj_dir/bw_u1_soffi_4x.v\n             obj_dir/bw_u1_soffi_4x.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_ctu_clk_sync_mux.v:246: Cannot find file containing module: 'bw_u1_soffi_4x'\nbw_u1_soffi_4x xf1 (\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_ctu_clk_sync_mux.v:254: Cannot find file containing module: 'bw_u1_muxi21_4x'\nbw_u1_muxi21_4x xmux (\n^~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module bw_ctu_clk_sync_mux_1path(pll_clk_out_l ,muxin0 ,mux_out_l ,in1 ,
     selg ,in0 ,pll_clk_out ,clk_out );
output		mux_out_l ;
output		clk_out ;
input		pll_clk_out_l ;
input		muxin0 ;
input		in1 ;
input		selg ;
input		in0 ;
input		pll_clk_out ;

 
wire		fout0_l ;
wire		fout1_l ;
wire		gclk_mux_l ;
wire		net22 ;
wire		net28 ;
wire		clk_out_l ;
wire		gclk_mux ;
wire		gclk ;


assign gclk_mux = ~(fout1_l & fout0_l);
assign gclk_mux_l = ~gclk_mux;
assign mux_out_l = ~gclk_mux;
assign clk_out = ~clk_out_l;
assign clk_out_l = ~gclk;

bw_u1_soffi_4x xf0 (
     .q_l             (fout0_l ),
     .so              (),
     .ck              (pll_clk_out ),
     .d               (in0 ),
     .se              (1'b0),
     .sd              () );

bw_u1_soffi_4x xf1 (
     .q_l             (fout1_l ),
     .so              (),
     .ck              (pll_clk_out_l ),
     .d               (in1 ),
     .se              (1'b0),
     .sd              () );

bw_u1_muxi21_4x xmux (
     .s               (selg ),
     .d1              (gclk_mux_l ),
     .d0              (muxin0 ),
     .z               (gclk ) );


 

endmodule
module bw_ctu_clk_sync_mux_1path(pll_clk_out_l ,muxin0 ,mux_out_l ,in1 ,
     selg ,in0 ,pll_clk_out ,clk_out );

output		mux_out_l ;
output		clk_out ;
input		pll_clk_out_l ;
input		muxin0 ;
input		in1 ;
input		selg ;
input		in0 ;
input		pll_clk_out ;

 
wire		fout0_l ;
wire		fout1_l ;
wire		gclk_mux_l ;
wire		net22 ;
wire		net28 ;
wire		clk_out_l ;
wire		gclk_mux ;
wire		gclk ;


assign gclk_mux = ~(fout1_l & fout0_l);
assign gclk_mux_l = ~gclk_mux;
assign mux_out_l = ~gclk_mux;
assign clk_out = ~clk_out_l;
assign clk_out_l = ~gclk;

bw_u1_soffi_4x xf0 (
     .q_l             (fout0_l ),
     .so              (),
     .ck              (pll_clk_out ),
     .d               (in0 ),
     .se              (1'b0),
     .sd              () );

bw_u1_soffi_4x xf1 (
     .q_l             (fout1_l ),
     .so              (),
     .ck              (pll_clk_out_l ),
     .d               (in1 ),
     .se              (1'b0),
     .sd              () );

bw_u1_muxi21_4x xmux (
     .s               (selg ),
     .d1              (gclk_mux_l ),
     .d0              (muxin0 ),
     .z               (gclk ) );


 

endmodule