data/full_repos/permissive/488093047/Verilog Codes/HalfAdder.v
1: b'%Error: Cannot find file containing module: Codes,data/full_repos/permissive/488093047\n        ... Looked in:\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.v\n             data/full_repos/permissive/488093047/Verilog/Codes,data/full_repos/permissive/488093047.sv\n             Codes,data/full_repos/permissive/488093047\n             Codes,data/full_repos/permissive/488093047.v\n             Codes,data/full_repos/permissive/488093047.sv\n             obj_dir/Codes,data/full_repos/permissive/488093047\n             obj_dir/Codes,data/full_repos/permissive/488093047.v\n             obj_dir/Codes,data/full_repos/permissive/488093047.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/488093047/Verilog\n%Error: Cannot find file containing module: Codes/HalfAdder.v\n%Error: Exiting due to 3 error(s)\n'
module HalfAdder(A,B,Sum,Cout);
input A,B;
output Sum,Cout;
xor DUT1(Sum,A,B);
and DUT2(Cout,A,B);


endmodule
module HalfAdder(A,B,Sum,Cout);

input A,B;
output Sum,Cout;
xor DUT1(Sum,A,B);
and DUT2(Cout,A,B);


endmodule