data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_io_config/bdw_work/wrappers/dut_vlwrapper.v
data/verilator_xmls/d03a9aac-e43a-4703-af9f-b4d09c59f09d.xml
module dut_vlwrapper(
      `ifdef ioConfig_TLM
      
      clk,
       rst
      `endif
      `ifdef ioConfig_PIN
      
      clk,
       rst
      `endif

    );

	`ifdef ioConfig_TLM
	
	input clk;
	input rst;
	
	`endif
	`ifdef ioConfig_PIN
	
	input clk;
	input rst;
	
	`endif



    dut_type_wrapper dut_sc(
        `ifdef ioConfig_TLM
        
        .clk(clk),
         .rst(rst)
        `endif
        `ifdef ioConfig_PIN
        
        .clk(clk),
         .rst(rst)
        `endif

    );




    `ifdef ioConfig_TLM
    
    
    `endif
    `ifdef ioConfig_PIN
    
    
    `endif


endmodule
module dut_vlwrapper(
      `ifdef ioConfig_TLM
      
      clk,
       rst
      `endif
      `ifdef ioConfig_PIN
      
      clk,
       rst
      `endif

    );


	`ifdef ioConfig_TLM
	
	input clk;
	input rst;
	
	`endif
	`ifdef ioConfig_PIN
	
	input clk;
	input rst;
	
	`endif



    dut_type_wrapper dut_sc(
        `ifdef ioConfig_TLM
        
        .clk(clk),
         .rst(rst)
        `endif
        `ifdef ioConfig_PIN
        
        .clk(clk),
         .rst(rst)
        `endif

    );




    `ifdef ioConfig_TLM
    
    
    `endif
    `ifdef ioConfig_PIN
    
    
    `endif


endmodule