data/full_repos/permissive/463395574/cpu.v
1: b'%Error: data/full_repos/permissive/463395574/cpu.v:3: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v.v\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/463395574/cpu.v:299: Define or directive not defined: \'`INSTR_SIZE\'\n    wire [`INSTR_SIZE-1:0] instr;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:300: Define or directive not defined: \'`ADDR_SIZE\'\n    wire [`ADDR_SIZE-1:0] pc, newPC, newSeqAddr, newJumpAddr;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:301: Define or directive not defined: \'`WORD_LEN\'\n    wire [`WORD_LEN-1:0] immOut, readData1, readData2, regWriteData;\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:302: Define or directive not defined: \'`REG_IDX_WIDTH\'\n    wire [`REG_IDX_WIDTH-1:0] readAddr1 = instr[19:15];\n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:303: Define or directive not defined: \'`REG_IDX_WIDTH\'\n    wire [`REG_IDX_WIDTH-1:0] readAddr2 = instr[24:20];\n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:304: Define or directive not defined: \'`REG_IDX_WIDTH\'\n    wire [`REG_IDX_WIDTH-1:0] writeAddr = instr[11:7];\n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:306: Define or directive not defined: \'`WORD_LEN\'\n    wire [`WORD_LEN-1:0] aluInputA, aluInputB, aluOut;\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:307: Define or directive not defined: \'`WORD_LEN\'\n    wire [`WORD_LEN-1:0] memReadData;\n          ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:317: Define or directive not defined: \'`WORD_LEN\'\n    addrAdder adder1(pc, {{{`WORD_LEN-3}{1\'b0}}, 3\'b100}, newSeqAddr);\n                            ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:318: Define or directive not defined: \'`ADDR_SIZE\'\n    wire [`ADDR_SIZE-1:0] addrAdderSrc1 = {{{`ADDR_SIZE-`WORD_LEN}{1\'b0}}, immOut};\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:318: Define or directive not defined: \'`ADDR_SIZE\'\n    wire [`ADDR_SIZE-1:0] addrAdderSrc1 = {{{`ADDR_SIZE-`WORD_LEN}{1\'b0}}, immOut};\n                                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:318: Define or directive not defined: \'`WORD_LEN\'\n    wire [`ADDR_SIZE-1:0] addrAdderSrc1 = {{{`ADDR_SIZE-`WORD_LEN}{1\'b0}}, immOut};\n                                                        ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:318: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n    wire [`ADDR_SIZE-1:0] addrAdderSrc1 = {{{`ADDR_SIZE-`WORD_LEN}{1\'b0}}, immOut};\n                                                                 ^\n%Error: data/full_repos/permissive/463395574/cpu.v:319: Define or directive not defined: \'`ADDR_SIZE\'\n    wire [`ADDR_SIZE-1:0] addrAdderSrc2 = jumpType == `JUMP_TYPE_JALR ? {{{`ADDR_SIZE-`WORD_LEN}{1\'b0}}, readData1} : pc;   \n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:319: Define or directive not defined: \'`JUMP_TYPE_JALR\'\n    wire [`ADDR_SIZE-1:0] addrAdderSrc2 = jumpType == `JUMP_TYPE_JALR ? {{{`ADDR_SIZE-`WORD_LEN}{1\'b0}}, readData1} : pc;   \n                                                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:319: syntax error, unexpected \'?\', expecting TYPE-IDENTIFIER\n    wire [`ADDR_SIZE-1:0] addrAdderSrc2 = jumpType == `JUMP_TYPE_JALR ? {{{`ADDR_SIZE-`WORD_LEN}{1\'b0}}, readData1} : pc;   \n                                                                      ^\n%Error: data/full_repos/permissive/463395574/cpu.v:319: Define or directive not defined: \'`ADDR_SIZE\'\n    wire [`ADDR_SIZE-1:0] addrAdderSrc2 = jumpType == `JUMP_TYPE_JALR ? {{{`ADDR_SIZE-`WORD_LEN}{1\'b0}}, readData1} : pc;   \n                                                                           ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:319: Define or directive not defined: \'`WORD_LEN\'\n    wire [`ADDR_SIZE-1:0] addrAdderSrc2 = jumpType == `JUMP_TYPE_JALR ? {{{`ADDR_SIZE-`WORD_LEN}{1\'b0}}, readData1} : pc;   \n                                                                                      ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:344: Define or directive not defined: \'`JUMP_TYPE_NONE\'\n        .isJumpOp(jumpType != `JUMP_TYPE_NONE),\n                              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:344: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        .isJumpOp(jumpType != `JUMP_TYPE_NONE),\n                                             ^\n%Error: data/full_repos/permissive/463395574/cpu.v:371: Define or directive not defined: \'`ADDR_SIZE\'\n    wire [`ADDR_SIZE-1:0] memAccessAddr = {{{`ADDR_SIZE-`WORD_LEN}{1\'b0}}, aluOut};\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:371: Define or directive not defined: \'`ADDR_SIZE\'\n    wire [`ADDR_SIZE-1:0] memAccessAddr = {{{`ADDR_SIZE-`WORD_LEN}{1\'b0}}, aluOut};\n                                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:371: Define or directive not defined: \'`WORD_LEN\'\n    wire [`ADDR_SIZE-1:0] memAccessAddr = {{{`ADDR_SIZE-`WORD_LEN}{1\'b0}}, aluOut};\n                                                        ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/cpu.v:371: syntax error, unexpected \'}\', expecting TYPE-IDENTIFIER\n    wire [`ADDR_SIZE-1:0] memAccessAddr = {{{`ADDR_SIZE-`WORD_LEN}{1\'b0}}, aluOut};\n                                                                 ^\n%Error: Exiting due to 25 error(s)\n'
module CPU (
    input clk, rst
);
    wire [`ADDR_SIZE-1:0] pc_IF;
    wire [`ADDR_SIZE-1:0] memAccessAddr;
    wire [`INSTR_SIZE-1:0] instr_IF;
    wire [`WORD_LEN-1:0] memWriteData, memReadData_MEM;
    wire [2:0] memAccessUnitSize;
    wire memRead_MEM, memWrite_MEM;

    IMem imem(pc_IF, instr_IF);

    DMem dmem(
        .clk(clk),
        .readEnable(memRead_MEM),
        .writeEnable(memWrite_MEM),
        .addr(memAccessAddr),
        .unitSize(memAccessUnitSize),
        .writeData(memWriteData),
        .readData(memReadData_MEM)
    );

    CPUCore cpuCore(
        .clk(clk),
        .rst(rst),
        .pc_IF(pc_IF),
        .instr_IF(instr_IF),
        .memRead_MEM(memRead_MEM),
        .memWrite_MEM(memWrite_MEM),
        .memAccessAddr(memAccessAddr),
        .memAccessUnitSize(memAccessUnitSize),
        .memWriteData(memWriteData),
        .memReadData_MEM(memReadData_MEM)
    );
endmodule
module CPU (
    input clk, rst
);

    wire [`ADDR_SIZE-1:0] pc_IF;
    wire [`ADDR_SIZE-1:0] memAccessAddr;
    wire [`INSTR_SIZE-1:0] instr_IF;
    wire [`WORD_LEN-1:0] memWriteData, memReadData_MEM;
    wire [2:0] memAccessUnitSize;
    wire memRead_MEM, memWrite_MEM;

    IMem imem(pc_IF, instr_IF);

    DMem dmem(
        .clk(clk),
        .readEnable(memRead_MEM),
        .writeEnable(memWrite_MEM),
        .addr(memAccessAddr),
        .unitSize(memAccessUnitSize),
        .writeData(memWriteData),
        .readData(memReadData_MEM)
    );

    CPUCore cpuCore(
        .clk(clk),
        .rst(rst),
        .pc_IF(pc_IF),
        .instr_IF(instr_IF),
        .memRead_MEM(memRead_MEM),
        .memWrite_MEM(memWrite_MEM),
        .memAccessAddr(memAccessAddr),
        .memAccessUnitSize(memAccessUnitSize),
        .memWriteData(memWriteData),
        .memReadData_MEM(memReadData_MEM)
    );
endmodule