data/full_repos/permissive/521925561/router_top_tb_cc.v
1: b'%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:16: Unsupported: event data types\nevent e1,e2;\n^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/521925561/router_top_tb_cc.v:29: Unsupported: Ignoring delay on this delayed statement.\n   forever #(T/2) clock = ~clock;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:37: syntax error, unexpected \'@\'\n   @(negedge clock)\n   ^\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:59: syntax error, unexpected \'@\'\n   @(negedge clock);\n   ^\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:60: Unsupported: wait statements\n    wait(~busy)\n    ^~~~\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:62: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:69: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:73: syntax error, unexpected \'@\'\n   @(negedge clock);\n   ^\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:74: Unsupported: wait statements\n    wait(~busy)\n    ^~~~\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:70: Unsupported: wait statements\n wait(~busy)\n ^~~~\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:79: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:80: Unsupported: wait statements\n wait(~busy)\n ^~~~\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:93: syntax error, unexpected \'@\'\n   @(negedge clock);\n   ^\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:94: Unsupported: wait statements\n    wait(~busy)\n    ^~~~\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:96: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:103: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:107: syntax error, unexpected \'@\'\n   @(negedge clock);\n   ^\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:108: Unsupported: wait statements\n    wait(~busy)\n    ^~~~\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:104: Unsupported: wait statements\n wait(~busy)\n ^~~~\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:113: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:114: Unsupported: wait statements\n wait(~busy)\n ^~~~\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:127: syntax error, unexpected \'@\'\n   @(negedge clock);\n   ^\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:128: Unsupported: wait statements\n    wait(~busy)\n    ^~~~\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:130: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:137: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:141: syntax error, unexpected \'@\'\n   @(negedge clock);\n   ^\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:142: Unsupported: wait statements\n    wait(~busy)\n    ^~~~\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:138: Unsupported: wait statements\n wait(~busy)\n ^~~~\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:147: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:148: Unsupported: wait statements\n wait(~busy)\n ^~~~\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:161: syntax error, unexpected ->\n  ->e2;\n  ^~\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:163: Unsupported: wait statements\n    wait(~busy)\n    ^~~~\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:165: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:172: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:176: syntax error, unexpected \'@\'\n   @(negedge clock);\n   ^\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:177: Unsupported: wait statements\n    wait(~busy)\n    ^~~~\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:173: Unsupported: wait statements\n wait(~busy)\n ^~~~\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:182: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:183: Unsupported: wait statements\n wait(~busy)\n ^~~~\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:196: syntax error, unexpected \'@\'\n   @(negedge clock);\n   ^\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:197: Unsupported: wait statements\n    wait(~busy)\n    ^~~~\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:199: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:206: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:210: syntax error, unexpected \'@\'\n   @(negedge clock);\n   ^\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:211: Unsupported: wait statements\n    wait(~busy)\n    ^~~~\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:207: Unsupported: wait statements\n wait(~busy)\n ^~~~\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:216: syntax error, unexpected ->\n ->e1;\n ^~\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:218: Unsupported: wait statements\n wait(~busy)\n ^~~~\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:231: syntax error, unexpected \'@\'\n   @(negedge clock);\n   ^\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:232: Unsupported: wait statements\n    wait(~busy)\n    ^~~~\n%Error: data/full_repos/permissive/521925561/router_top_tb_cc.v:234: syntax error, unexpected \'@\'\n @(negedge clock);\n ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n        ... See the manual and https://verilator.org for more assistance.\n'
module router_top_tb_cc();


 
reg clock,resetn;
reg pkt_valid;
reg [7:0]data_in;
reg read_enb_0,read_enb_1,read_enb_2;

wire [7:0]data_out_0,data_out_1,data_out_2;
wire vld_out_0,vld_out_1,vld_out_2,busy,error;

parameter T = 10;
integer k;
event e1,e2;



router_top ROUTER_DUT(clock,resetn,read_enb_0,read_enb_1,read_enb_2,pkt_valid,data_in,data_out_0,
                      data_out_1,data_out_2,vld_out_0,vld_out_1,vld_out_2,error,busy);
					  


initial 
  begin
   clock = 1'b0;  

   forever #(T/2) clock = ~clock;

 end



task rst;
  begin
   @(negedge clock)
    resetn = 1'b0;
   @(negedge clock)
    resetn = 1'b1;
  end
endtask



task initialise;
  begin
    {read_enb_0,read_enb_1,read_enb_2,pkt_valid,data_in} = 12'd0;
  end
 endtask
 


task pkt_gen_14(input [1:0]addr);
reg [7:0]payload_data,parity,header;
reg [5:0]payload_length;
reg [1:0]address;
  begin
   @(negedge clock);
    wait(~busy)
   parity = 8'd0;
	@(negedge clock);
    payload_length = 6'd14;
	address = addr;
	header = {payload_length,address};
	data_in = header;
	pkt_valid = 1'b1;
	parity = parity ^ header;
	@(negedge clock);
	wait(~busy)
	for(k=0;k<payload_length;k=k+1)
	 begin
	  @(negedge clock);
	   wait(~busy)
	  payload_data = {$random}%256;
	  data_in = payload_data;
	  parity = parity ^ payload_data;
	end
	@(negedge clock);
	wait(~busy)
	pkt_valid = 1'b0;
	data_in = parity;
  end
endtask



task pkt_gen_12(input [1:0]addr);
reg [7:0]payload_data,parity,header;
reg [5:0]payload_length;
reg [1:0]address;
  begin
   @(negedge clock);
    wait(~busy)
     parity = 8'd0;
	@(negedge clock);
    payload_length = 6'd12;
	address = addr;
	header = {payload_length,address};
	data_in = header;
	pkt_valid = 1'b1;
	parity = parity ^ header;
	@(negedge clock);
	wait(~busy)
	for(k=0;k<payload_length;k=k+1)
	 begin
	  @(negedge clock);
	   wait(~busy)
	  payload_data = {$random}%256;
	  data_in = payload_data;
	  parity = parity ^ payload_data;
	end
	@(negedge clock);
	wait(~busy)
	pkt_valid = 1'b0;
	data_in = parity;
  end
endtask



task pkt_gen_16(input [1:0]addr);
reg [7:0]payload_data,parity,header;
reg [5:0]payload_length;
reg [1:0]address;
  begin
   @(negedge clock);
    wait(~busy)
	parity = 8'd0;
	@(negedge clock);
    payload_length = 6'd16;
	address = addr;
	header = {payload_length,address};
	data_in = header;
	pkt_valid = 1'b1;
	parity = parity ^ header;
	@(negedge clock);
	wait(~busy)
	for(k=0;k<payload_length;k=k+1)
	 begin
	  @(negedge clock);
	   wait(~busy)
	  payload_data = {$random}%256;
	  data_in = payload_data;
	  parity = parity ^ payload_data;
	end
	@(negedge clock);
	wait(~busy)
	pkt_valid = 1'b0;
	data_in = parity;
  end
endtask



task random_pkt(input [1:0]addr);
reg [7:0]payload_data,parity,header;
reg [5:0]payload_length;
reg [1:0]address;
  begin
  ->e2;
   @(negedge clock);
    wait(~busy)
	parity = 8'd0;
	@(negedge clock);
    payload_length = {$random}%63 + 1;
	address = addr;
	header = {payload_length,address};
	data_in = header;
	pkt_valid = 1'b1;
	parity = parity ^ header;
	@(negedge clock);
	wait(~busy)
	for(k=0;k<payload_length;k=k+1)
	 begin
	  @(negedge clock);
	   wait(~busy)
	  payload_data = {$random}%256;
	  data_in = payload_data;
	  parity = parity ^ payload_data;
	end
	@(negedge clock);
	wait(~busy)
	pkt_valid = 1'b0;
	data_in = parity;
  end
endtask



task pkt_gen_17(input [1:0]addr);
reg [7:0]payload_data,parity,header;
reg [5:0]payload_length;
reg [1:0]address;
  begin
   @(negedge clock);
    wait(~busy)
	parity = 8'd0;
	@(negedge clock);
    payload_length = 6'd17;
	address = addr;
	header = {payload_length,address};
	data_in = header;
	pkt_valid = 1'b1;
	parity = parity ^ header;
	@(negedge clock);
	wait(~busy)
	for(k=0;k<payload_length;k=k+1)
	 begin
	  @(negedge clock);
	   wait(~busy)
	  payload_data = {$random}%256;
	  data_in = payload_data;
	  parity = parity ^ payload_data;
	end
	->e1;
	@(negedge clock);
	wait(~busy)
	pkt_valid = 1'b0;
	data_in = parity;
  end
endtask



task pkt_gen_error_10(input [1:0]addr);
reg [7:0]payload_data,parity,header;
reg [5:0]payload_length;
reg [1:0]address;
  begin
   @(negedge clock);
    wait(~busy)
   parity = 8'd0;
	@(negedge clock);
    payload_length = 6'd10;
	address = addr;
	header = {payload_length,address};
	data_in = header;
	pkt_valid = 1'b1;
	parity = parity ^ header;
	@(negedge clock);
	wait(~busy)
	for(k=0;k<payload_length;k=k+1)
	 begin
	  @(negedge clock);
	   wait(~busy)
	  payload_data = {$random}%256;
	  data_in = payload_data;
	  parity = parity ^ payload_data;
	end
	@(negedge clock);
	wait(~busy)
	pkt_valid = 1'b0;
	data_in = $random;
  end
endtask



initial
 begin
  forever
   begin
   @(e1);
   @(negedge clock);
   begin
    case(vld_out_0 || vld_out_1 || vld_out_2)
	  vld_out_0 :  read_enb_0 = 1'b1;
      vld_out_1 :  read_enb_1 = 1'b1;
      vld_out_2 :  read_enb_2 = 1'b1;
	endcase
   end
   @(negedge clock);
   wait(~(vld_out_0 || vld_out_1 || vld_out_2))
   @(negedge clock);
   {read_enb_0,read_enb_1,read_enb_2} = 3'b000;
   end
   end   



initial
 begin
  forever
  begin
   @(e2);
   @(negedge clock);
   wait(vld_out_0 || vld_out_1 || vld_out_2);
   @(negedge clock) 
   begin
    case(vld_out_0 || vld_out_1 || vld_out_2)
	  vld_out_0 :  read_enb_0 = 1'b1;
      vld_out_1 :  read_enb_1 = 1'b1;
      vld_out_2 :  read_enb_2 = 1'b1;
	endcase
   end
   wait (~(vld_out_0 || vld_out_1 || vld_out_2));
   @(negedge clock)
    {read_enb_0,read_enb_1,read_enb_2} = 3'b000;
   end
   end
   


initial
 begin
  initialise;
  


  rst;
  repeat(3)
  @(negedge clock);
   pkt_gen_12(2'b00);
  @(negedge clock);
   read_enb_0 = 1'b1;
   wait (~vld_out_0)
  @(negedge clock);
   read_enb_0 = 1'b0;
   #30;
   


    rst;
  repeat(3)
  @(negedge clock);
   pkt_gen_14(2'b00);
   @(negedge clock);
   read_enb_0 = 1'b1;
   wait (~vld_out_0)
  @(negedge clock);
   read_enb_0 = 1'b0;
   #30;
   


  rst;
 repeat(3)
@(negedge clock);
   pkt_gen_16(2'b00);
   @(negedge clock);
   read_enb_0 = 1'b1;
   wait (~vld_out_0)
  @(negedge clock);
   read_enb_0 = 1'b0;
   #30;
   


rst;
 repeat(3)
@(negedge clock);
   pkt_gen_17(2'b00);
   #200;
   


rst;
 repeat(3)
@(negedge clock);
   random_pkt(2'b00);
   #100;
   


rst;
  repeat(3)
  @(negedge clock);
   pkt_gen_error_10(2'b00);
  @(negedge clock);
   read_enb_0 = 1'b1;
   wait (~vld_out_0)
  @(negedge clock);
   read_enb_0 = 1'b0;
   #30;
 

 
 rst;
  repeat(3)
  @(negedge clock);
   pkt_gen_12(2'b00);
  @(negedge clock);
   read_enb_0 = 1'b1;
   @(negedge clock);
   pkt_gen_12(2'b00);
   wait (~vld_out_0)
  @(negedge clock);
   read_enb_0 = 1'b0;
   #30;



rst;
  repeat(3)
  @(negedge clock);
   pkt_gen_12(2'b00);
   #210;
 


  rst;
  repeat(3)
  @(negedge clock);
   pkt_gen_12(2'b01);
  @(negedge clock);
   read_enb_1 = 1'b1;
   wait (~vld_out_1)
  @(negedge clock);
   read_enb_1= 1'b0;
   #30;
   


    rst;
  repeat(3)
  @(negedge clock);
   pkt_gen_14(2'b01);
   @(negedge clock);
   read_enb_1 = 1'b1;
   wait (~vld_out_1)
  @(negedge clock);
   read_enb_1 = 1'b0;
   #30;
   


  rst;
 repeat(3)
@(negedge clock);
   pkt_gen_16(2'b01);
   @(negedge clock);
   read_enb_1 = 1'b1;
   wait (~vld_out_1)
  @(negedge clock);
   read_enb_1 = 1'b0;
   #30;
   


rst;                                   
 repeat(3)
@(negedge clock);
   pkt_gen_17(2'b01);
   #200;
   


rst;
 repeat(3)
@(negedge clock);
   random_pkt(2'b01);
   #100;
   


rst;
  repeat(3)
  @(negedge clock);
   pkt_gen_error_10(2'b01);
  @(negedge clock);
   read_enb_1 = 1'b1;
   wait (~vld_out_1)
  @(negedge clock);
   read_enb_1 = 1'b0;
   #30;
   

 
 rst;
  repeat(3)
  @(negedge clock);
   pkt_gen_12(2'b01);
  @(negedge clock);
   read_enb_1 = 1'b1;
   @(negedge clock);
   pkt_gen_12(2'b01);
   wait (~vld_out_1)
  @(negedge clock);
   read_enb_1 = 1'b0;
   #30;



rst;
  repeat(3)
  @(negedge clock);
   pkt_gen_12(2'b01);
   #210;



  rst;
  repeat(3)
  @(negedge clock);
   pkt_gen_12(2'b10);
  @(negedge clock);
   read_enb_2 = 1'b1;
   wait (~vld_out_2)
  @(negedge clock);
   read_enb_2 = 1'b0;
   #30;
   


    rst;
  repeat(3)
  @(negedge clock);
   pkt_gen_14(2'b10);
   @(negedge clock);
   read_enb_2 = 1'b1;
   wait (~vld_out_2)
  @(negedge clock);
   read_enb_2 = 1'b0;
   #30;
   


  rst;
 repeat(3)
@(negedge clock);
   pkt_gen_16(2'b10);
   @(negedge clock);
   read_enb_2 = 1'b1;
   wait (~vld_out_2)
  @(negedge clock);
   read_enb_2 = 1'b0;
   #30;
   


rst;
 repeat(3)
@(negedge clock);
   pkt_gen_17(2'b10);
   #200;
   


rst;
 repeat(3)
@(negedge clock);
   random_pkt(2'b10);
   #30;
   


rst;
  repeat(3)
  @(negedge clock);
   pkt_gen_error_10(2'b10);
  @(negedge clock);
   read_enb_2 = 1'b1;
   wait (~vld_out_2)
  @(negedge clock);
   read_enb_2 = 1'b0;
   #30;
   

 
 rst;
  repeat(3)
  @(negedge clock);
   pkt_gen_12(2'b10);
  @(negedge clock);
   read_enb_2 = 1'b1;
   @(negedge clock);
   pkt_gen_12(2'b10);
   wait (~vld_out_2)
  @(negedge clock);
   read_enb_2 = 1'b0;
   #30;



rst;
  repeat(3)
  @(negedge clock);
   pkt_gen_12(2'b10);
   




 @(negedge clock);
  ROUTER_DUT.FIFO_0.i = 32'h00000000;
 @(negedge clock);
  ROUTER_DUT.FIFO_0.i = 32'hFFFFFFFF;
 @(negedge clock);
  ROUTER_DUT.FIFO_0.i = 32'h00000000;
  


 @(negedge clock);
  ROUTER_DUT.FIFO_1.i = 32'h00000000;
 @(negedge clock);
  ROUTER_DUT.FIFO_1.i = 32'hFFFFFFFF;
 @(negedge clock);
  ROUTER_DUT.FIFO_1.i = 32'h00000000;
  

  
 @(negedge clock);
  ROUTER_DUT.FIFO_2.i = 32'h00000000;
 @(negedge clock);
  ROUTER_DUT.FIFO_2.i = 32'hFFFFFFFF;
 @(negedge clock);
  ROUTER_DUT.FIFO_2.i = 32'h00000000;

end

initial #10600 $finish; 

endmodule
module router_top_tb_cc();



 
reg clock,resetn;
reg pkt_valid;
reg [7:0]data_in;
reg read_enb_0,read_enb_1,read_enb_2;

wire [7:0]data_out_0,data_out_1,data_out_2;
wire vld_out_0,vld_out_1,vld_out_2,busy,error;

parameter T = 10;
integer k;
event e1,e2;



router_top ROUTER_DUT(clock,resetn,read_enb_0,read_enb_1,read_enb_2,pkt_valid,data_in,data_out_0,
                      data_out_1,data_out_2,vld_out_0,vld_out_1,vld_out_2,error,busy);
					  


initial 
  begin
   clock = 1'b0;  

   forever #(T/2) clock = ~clock;

 end



task rst;
  begin
   @(negedge clock)
    resetn = 1'b0;
   @(negedge clock)
    resetn = 1'b1;
  end
endtask



task initialise;
  begin
    {read_enb_0,read_enb_1,read_enb_2,pkt_valid,data_in} = 12'd0;
  end
 endtask
 


task pkt_gen_14(input [1:0]addr);
reg [7:0]payload_data,parity,header;
reg [5:0]payload_length;
reg [1:0]address;
  begin
   @(negedge clock);
    wait(~busy)
   parity = 8'd0;
	@(negedge clock);
    payload_length = 6'd14;
	address = addr;
	header = {payload_length,address};
	data_in = header;
	pkt_valid = 1'b1;
	parity = parity ^ header;
	@(negedge clock);
	wait(~busy)
	for(k=0;k<payload_length;k=k+1)
	 begin
	  @(negedge clock);
	   wait(~busy)
	  payload_data = {$random}%256;
	  data_in = payload_data;
	  parity = parity ^ payload_data;
	end
	@(negedge clock);
	wait(~busy)
	pkt_valid = 1'b0;
	data_in = parity;
  end
endtask



task pkt_gen_12(input [1:0]addr);
reg [7:0]payload_data,parity,header;
reg [5:0]payload_length;
reg [1:0]address;
  begin
   @(negedge clock);
    wait(~busy)
     parity = 8'd0;
	@(negedge clock);
    payload_length = 6'd12;
	address = addr;
	header = {payload_length,address};
	data_in = header;
	pkt_valid = 1'b1;
	parity = parity ^ header;
	@(negedge clock);
	wait(~busy)
	for(k=0;k<payload_length;k=k+1)
	 begin
	  @(negedge clock);
	   wait(~busy)
	  payload_data = {$random}%256;
	  data_in = payload_data;
	  parity = parity ^ payload_data;
	end
	@(negedge clock);
	wait(~busy)
	pkt_valid = 1'b0;
	data_in = parity;
  end
endtask



task pkt_gen_16(input [1:0]addr);
reg [7:0]payload_data,parity,header;
reg [5:0]payload_length;
reg [1:0]address;
  begin
   @(negedge clock);
    wait(~busy)
	parity = 8'd0;
	@(negedge clock);
    payload_length = 6'd16;
	address = addr;
	header = {payload_length,address};
	data_in = header;
	pkt_valid = 1'b1;
	parity = parity ^ header;
	@(negedge clock);
	wait(~busy)
	for(k=0;k<payload_length;k=k+1)
	 begin
	  @(negedge clock);
	   wait(~busy)
	  payload_data = {$random}%256;
	  data_in = payload_data;
	  parity = parity ^ payload_data;
	end
	@(negedge clock);
	wait(~busy)
	pkt_valid = 1'b0;
	data_in = parity;
  end
endtask



task random_pkt(input [1:0]addr);
reg [7:0]payload_data,parity,header;
reg [5:0]payload_length;
reg [1:0]address;
  begin
  ->e2;
   @(negedge clock);
    wait(~busy)
	parity = 8'd0;
	@(negedge clock);
    payload_length = {$random}%63 + 1;
	address = addr;
	header = {payload_length,address};
	data_in = header;
	pkt_valid = 1'b1;
	parity = parity ^ header;
	@(negedge clock);
	wait(~busy)
	for(k=0;k<payload_length;k=k+1)
	 begin
	  @(negedge clock);
	   wait(~busy)
	  payload_data = {$random}%256;
	  data_in = payload_data;
	  parity = parity ^ payload_data;
	end
	@(negedge clock);
	wait(~busy)
	pkt_valid = 1'b0;
	data_in = parity;
  end
endtask



task pkt_gen_17(input [1:0]addr);
reg [7:0]payload_data,parity,header;
reg [5:0]payload_length;
reg [1:0]address;
  begin
   @(negedge clock);
    wait(~busy)
	parity = 8'd0;
	@(negedge clock);
    payload_length = 6'd17;
	address = addr;
	header = {payload_length,address};
	data_in = header;
	pkt_valid = 1'b1;
	parity = parity ^ header;
	@(negedge clock);
	wait(~busy)
	for(k=0;k<payload_length;k=k+1)
	 begin
	  @(negedge clock);
	   wait(~busy)
	  payload_data = {$random}%256;
	  data_in = payload_data;
	  parity = parity ^ payload_data;
	end
	->e1;
	@(negedge clock);
	wait(~busy)
	pkt_valid = 1'b0;
	data_in = parity;
  end
endtask



task pkt_gen_error_10(input [1:0]addr);
reg [7:0]payload_data,parity,header;
reg [5:0]payload_length;
reg [1:0]address;
  begin
   @(negedge clock);
    wait(~busy)
   parity = 8'd0;
	@(negedge clock);
    payload_length = 6'd10;
	address = addr;
	header = {payload_length,address};
	data_in = header;
	pkt_valid = 1'b1;
	parity = parity ^ header;
	@(negedge clock);
	wait(~busy)
	for(k=0;k<payload_length;k=k+1)
	 begin
	  @(negedge clock);
	   wait(~busy)
	  payload_data = {$random}%256;
	  data_in = payload_data;
	  parity = parity ^ payload_data;
	end
	@(negedge clock);
	wait(~busy)
	pkt_valid = 1'b0;
	data_in = $random;
  end
endtask



initial
 begin
  forever
   begin
   @(e1);
   @(negedge clock);
   begin
    case(vld_out_0 || vld_out_1 || vld_out_2)
	  vld_out_0 :  read_enb_0 = 1'b1;
      vld_out_1 :  read_enb_1 = 1'b1;
      vld_out_2 :  read_enb_2 = 1'b1;
	endcase
   end
   @(negedge clock);
   wait(~(vld_out_0 || vld_out_1 || vld_out_2))
   @(negedge clock);
   {read_enb_0,read_enb_1,read_enb_2} = 3'b000;
   end
   end   



initial
 begin
  forever
  begin
   @(e2);
   @(negedge clock);
   wait(vld_out_0 || vld_out_1 || vld_out_2);
   @(negedge clock) 
   begin
    case(vld_out_0 || vld_out_1 || vld_out_2)
	  vld_out_0 :  read_enb_0 = 1'b1;
      vld_out_1 :  read_enb_1 = 1'b1;
      vld_out_2 :  read_enb_2 = 1'b1;
	endcase
   end
   wait (~(vld_out_0 || vld_out_1 || vld_out_2));
   @(negedge clock)
    {read_enb_0,read_enb_1,read_enb_2} = 3'b000;
   end
   end
   


initial
 begin
  initialise;
  


  rst;
  repeat(3)
  @(negedge clock);
   pkt_gen_12(2'b00);
  @(negedge clock);
   read_enb_0 = 1'b1;
   wait (~vld_out_0)
  @(negedge clock);
   read_enb_0 = 1'b0;
   #30;
   


    rst;
  repeat(3)
  @(negedge clock);
   pkt_gen_14(2'b00);
   @(negedge clock);
   read_enb_0 = 1'b1;
   wait (~vld_out_0)
  @(negedge clock);
   read_enb_0 = 1'b0;
   #30;
   


  rst;
 repeat(3)
@(negedge clock);
   pkt_gen_16(2'b00);
   @(negedge clock);
   read_enb_0 = 1'b1;
   wait (~vld_out_0)
  @(negedge clock);
   read_enb_0 = 1'b0;
   #30;
   


rst;
 repeat(3)
@(negedge clock);
   pkt_gen_17(2'b00);
   #200;
   


rst;
 repeat(3)
@(negedge clock);
   random_pkt(2'b00);
   #100;
   


rst;
  repeat(3)
  @(negedge clock);
   pkt_gen_error_10(2'b00);
  @(negedge clock);
   read_enb_0 = 1'b1;
   wait (~vld_out_0)
  @(negedge clock);
   read_enb_0 = 1'b0;
   #30;
 

 
 rst;
  repeat(3)
  @(negedge clock);
   pkt_gen_12(2'b00);
  @(negedge clock);
   read_enb_0 = 1'b1;
   @(negedge clock);
   pkt_gen_12(2'b00);
   wait (~vld_out_0)
  @(negedge clock);
   read_enb_0 = 1'b0;
   #30;



rst;
  repeat(3)
  @(negedge clock);
   pkt_gen_12(2'b00);
   #210;
 


  rst;
  repeat(3)
  @(negedge clock);
   pkt_gen_12(2'b01);
  @(negedge clock);
   read_enb_1 = 1'b1;
   wait (~vld_out_1)
  @(negedge clock);
   read_enb_1= 1'b0;
   #30;
   


    rst;
  repeat(3)
  @(negedge clock);
   pkt_gen_14(2'b01);
   @(negedge clock);
   read_enb_1 = 1'b1;
   wait (~vld_out_1)
  @(negedge clock);
   read_enb_1 = 1'b0;
   #30;
   


  rst;
 repeat(3)
@(negedge clock);
   pkt_gen_16(2'b01);
   @(negedge clock);
   read_enb_1 = 1'b1;
   wait (~vld_out_1)
  @(negedge clock);
   read_enb_1 = 1'b0;
   #30;
   


rst;                                   
 repeat(3)
@(negedge clock);
   pkt_gen_17(2'b01);
   #200;
   


rst;
 repeat(3)
@(negedge clock);
   random_pkt(2'b01);
   #100;
   


rst;
  repeat(3)
  @(negedge clock);
   pkt_gen_error_10(2'b01);
  @(negedge clock);
   read_enb_1 = 1'b1;
   wait (~vld_out_1)
  @(negedge clock);
   read_enb_1 = 1'b0;
   #30;
   

 
 rst;
  repeat(3)
  @(negedge clock);
   pkt_gen_12(2'b01);
  @(negedge clock);
   read_enb_1 = 1'b1;
   @(negedge clock);
   pkt_gen_12(2'b01);
   wait (~vld_out_1)
  @(negedge clock);
   read_enb_1 = 1'b0;
   #30;



rst;
  repeat(3)
  @(negedge clock);
   pkt_gen_12(2'b01);
   #210;



  rst;
  repeat(3)
  @(negedge clock);
   pkt_gen_12(2'b10);
  @(negedge clock);
   read_enb_2 = 1'b1;
   wait (~vld_out_2)
  @(negedge clock);
   read_enb_2 = 1'b0;
   #30;
   


    rst;
  repeat(3)
  @(negedge clock);
   pkt_gen_14(2'b10);
   @(negedge clock);
   read_enb_2 = 1'b1;
   wait (~vld_out_2)
  @(negedge clock);
   read_enb_2 = 1'b0;
   #30;
   


  rst;
 repeat(3)
@(negedge clock);
   pkt_gen_16(2'b10);
   @(negedge clock);
   read_enb_2 = 1'b1;
   wait (~vld_out_2)
  @(negedge clock);
   read_enb_2 = 1'b0;
   #30;
   


rst;
 repeat(3)
@(negedge clock);
   pkt_gen_17(2'b10);
   #200;
   


rst;
 repeat(3)
@(negedge clock);
   random_pkt(2'b10);
   #30;
   


rst;
  repeat(3)
  @(negedge clock);
   pkt_gen_error_10(2'b10);
  @(negedge clock);
   read_enb_2 = 1'b1;
   wait (~vld_out_2)
  @(negedge clock);
   read_enb_2 = 1'b0;
   #30;
   

 
 rst;
  repeat(3)
  @(negedge clock);
   pkt_gen_12(2'b10);
  @(negedge clock);
   read_enb_2 = 1'b1;
   @(negedge clock);
   pkt_gen_12(2'b10);
   wait (~vld_out_2)
  @(negedge clock);
   read_enb_2 = 1'b0;
   #30;



rst;
  repeat(3)
  @(negedge clock);
   pkt_gen_12(2'b10);
   




 @(negedge clock);
  ROUTER_DUT.FIFO_0.i = 32'h00000000;
 @(negedge clock);
  ROUTER_DUT.FIFO_0.i = 32'hFFFFFFFF;
 @(negedge clock);
  ROUTER_DUT.FIFO_0.i = 32'h00000000;
  


 @(negedge clock);
  ROUTER_DUT.FIFO_1.i = 32'h00000000;
 @(negedge clock);
  ROUTER_DUT.FIFO_1.i = 32'hFFFFFFFF;
 @(negedge clock);
  ROUTER_DUT.FIFO_1.i = 32'h00000000;
  

  
 @(negedge clock);
  ROUTER_DUT.FIFO_2.i = 32'h00000000;
 @(negedge clock);
  ROUTER_DUT.FIFO_2.i = 32'hFFFFFFFF;
 @(negedge clock);
  ROUTER_DUT.FIFO_2.i = 32'h00000000;

end

initial #10600 $finish; 

endmodule