data/full_repos/permissive/434840709/lab3/3.1/GPU.v
1: b"%Error-ASSIGNIN: data/full_repos/permissive/434840709/lab3/3.1/GPU.v:11: Assigning to input/const variable: 'dataBus'\n    assign dataBus = msgArray[31:16];\n           ^~~~~~~\n%Error: Exiting due to 1 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module GPU(
    input clk3hz,
    input clr,
    input [15:0] dataBus
    );

    reg [31:0] msgArray;
    parameter NUMBER = 32'h42024137;

    assign dataBus = msgArray[31:16];

    always @(posedge clk3hz or negedge clr) begin
        if (!clr)
            msgArray <= NUMBER;
        else begin
            msgArray[3:0] <= msgArray[31:28];
            msgArray[31:4] <= msgArray[27:0];
        end        
    end

endmodule
module GPU(
    input clk3hz,
    input clr,
    input [15:0] dataBus
    );


    reg [31:0] msgArray;
    parameter NUMBER = 32'h42024137;

    assign dataBus = msgArray[31:16];

    always @(posedge clk3hz or negedge clr) begin
        if (!clr)
            msgArray <= NUMBER;
        else begin
            msgArray[3:0] <= msgArray[31:28];
            msgArray[31:4] <= msgArray[27:0];
        end        
    end

endmodule