data/full_repos/permissive/499944578/rtl/test/fragment_interpolator/fragment_interpolator_Test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/fragment_interpolator/fragment_interpolator_Test.v:99: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD/2);\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/fragment_interpolator/fragment_interpolator_Test.v:101: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD/2);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/fragment_interpolator/fragment_interpolator_Test.v:103: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD/2);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/fragment_interpolator/fragment_interpolator_Test.v:111: Unsupported: Ignoring delay on this delayed statement.\n            #PERIOD;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/fragment_interpolator/fragment_interpolator_Test.v:118: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD/2);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/fragment_interpolator/fragment_interpolator_Test.v:120: Unsupported: Ignoring delay on this delayed statement.\n            #(PERIOD/2);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/fragment_interpolator/fragment_interpolator_Test.v:137: Unsupported: Ignoring delay on this delayed statement.\n            #TIMEOUT;\n            ^\n%Error: data/full_repos/permissive/499944578/rtl/test/fragment_interpolator/fragment_interpolator_Test.v:143: Unsupported or unknown PLI call: $dumpfile\n            $dumpfile("fragment_interpolator_Test.vcd");\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/499944578/rtl/test/fragment_interpolator/fragment_interpolator_Test.v:144: Unsupported or unknown PLI call: $dumpvars\n            $dumpvars(0,fragment_interpolator_Test);\n            ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/499944578/rtl/test/fragment_interpolator/fragment_interpolator_Test.v:145: Unsupported: Ignoring delay on this delayed statement.\n            #1;\n            ^\n%Error: Exiting due to 2 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fragment_interpolator_Test#(
    parameter PIN = {QuarterFP,QuarterFP},
    parameter NOPERSPECTIVE = 'b0,
    parameter FLAT = 'b0,
    parameter PROVOKEMODE = 'b0,
    parameter VERTEXSIZE = 4'd15
)();
    
    localparam DATA_WIDTH = 32;
    localparam ADDR_WIDTH = 4;
    localparam CYCLES_WAIT_FOR_RECIEVE = 4'b0001;
    localparam OneFP = 32'h3f800000;
    localparam ZeroFP = 32'h00000000;
    localparam HalfFP = 32'h3f000000;
    localparam QuarterFP = 32'h3e800000;
    localparam PERIOD = 20;
    localparam TIMEOUT = PERIOD*1000;
    reg clk;
    reg resetn, en;

    wire [2:0][ADDR_WIDTH-1:0] vert_attr_rd_addr;
    wire [2:0][0:0]            vert_attr_rd_en;
    wire [2:0][DATA_WIDTH-1:0] vert_attr_rd_data; 

    wire [DATA_WIDTH-1:0] frag_attr_wr_data;       
    wire [ADDR_WIDTH-1:0] frag_attr_wr_addr;
    wire                  frag_attr_wr_en;

    wire [65:0] PinRecFN;
    reg [63:0] Pin;
    reg start;
    wire done;
    reg noPerspective, flat, provokeMode;
    reg [ADDR_WIDTH-1:0] vertexSize;

v0ROM #(DATA_WIDTH, ADDR_WIDTH)v0ROM_inst(
    vert_attr_rd_addr[0], 
    clk,   
    vert_attr_rd_en[0],        
    vert_attr_rd_data[0]
);
v1ROM #(DATA_WIDTH, ADDR_WIDTH)v1ROM_inst(
    vert_attr_rd_addr[1], 
    clk,   
    vert_attr_rd_en[1],        
    vert_attr_rd_data[1]
);
v2ROM #(DATA_WIDTH, ADDR_WIDTH)v2ROM_inst(
    vert_attr_rd_addr[2], 
    clk,   
    vert_attr_rd_en[2],        
    vert_attr_rd_data[2]
);

fNToRecFN#(8,24) fNToRecFNx (Pin[63:32], PinRecFN[65:33]);
fNToRecFN#(8,24) fNToRecFNy (Pin[31:0], PinRecFN[32:0]);


wire [32:0] halfrecfp;
fNToRecFN#(8,24) fNToRecFNtest (HalfFP, halfrecfp);

fragment_interpolator #(
    DATA_WIDTH, ADDR_WIDTH, CYCLES_WAIT_FOR_RECIEVE
) DUT (
    clk,resetn,en,
    frag_attr_wr_data,       
    frag_attr_wr_addr, 
    frag_attr_wr_en,  

    vert_attr_rd_data,       
    vert_attr_rd_addr, 
    vert_attr_rd_en,    

    PinRecFN,

    start, done,   
    
    noPerspective,
    flat, provokeMode,
    vertexSize 
);

simple_ram_dual_clock#(
    DATA_WIDTH,
    ADDR_WIDTH
) frag_mem (
    .data(frag_attr_wr_data),
    .read_addr(),
    .write_addr(frag_attr_wr_addr),
    .we(frag_attr_wr_en),
    .read_clk(clk),
    .write_clk(clk),
    .re(),
    .q()
);
    initial
        begin
            resetn = 1'b1;
            #(PERIOD/2);
            resetn = 1'b0; 
            #(PERIOD/2);
            resetn = 1'b1;
            #(PERIOD/2);
            en = 1'b1;
            start = 1'b1;
            Pin = PIN;
            noPerspective = NOPERSPECTIVE;
            flat = FLAT;
            provokeMode = PROVOKEMODE;
            vertexSize = VERTEXSIZE;
            #PERIOD;
            start = 1'b0;

        end
    always 
        begin
            clk = 1'b1; 
            #(PERIOD/2);
            clk = 1'b0;
            #(PERIOD/2);
        end
    
    always @(frag_attr_wr_en, frag_attr_wr_data, frag_attr_wr_addr) begin
        if(frag_attr_wr_en) begin
            $display("[fragment_write] data:0x%0h, addr:0x%0h ", frag_attr_wr_data, frag_attr_wr_addr);
        end
    end







    initial 
        begin
            #TIMEOUT;
            $display("Simulation Timed Out :(");
            $finish;
        end
    initial
        begin
            $dumpfile("fragment_interpolator_Test.vcd");
            $dumpvars(0,fragment_interpolator_Test);
            #1;
        end
endmodule
module fragment_interpolator_Test#(
    parameter PIN = {QuarterFP,QuarterFP},
    parameter NOPERSPECTIVE = 'b0,
    parameter FLAT = 'b0,
    parameter PROVOKEMODE = 'b0,
    parameter VERTEXSIZE = 4'd15
)();

    
    localparam DATA_WIDTH = 32;
    localparam ADDR_WIDTH = 4;
    localparam CYCLES_WAIT_FOR_RECIEVE = 4'b0001;
    localparam OneFP = 32'h3f800000;
    localparam ZeroFP = 32'h00000000;
    localparam HalfFP = 32'h3f000000;
    localparam QuarterFP = 32'h3e800000;
    localparam PERIOD = 20;
    localparam TIMEOUT = PERIOD*1000;
    reg clk;
    reg resetn, en;

    wire [2:0][ADDR_WIDTH-1:0] vert_attr_rd_addr;
    wire [2:0][0:0]            vert_attr_rd_en;
    wire [2:0][DATA_WIDTH-1:0] vert_attr_rd_data; 

    wire [DATA_WIDTH-1:0] frag_attr_wr_data;       
    wire [ADDR_WIDTH-1:0] frag_attr_wr_addr;
    wire                  frag_attr_wr_en;

    wire [65:0] PinRecFN;
    reg [63:0] Pin;
    reg start;
    wire done;
    reg noPerspective, flat, provokeMode;
    reg [ADDR_WIDTH-1:0] vertexSize;

v0ROM #(DATA_WIDTH, ADDR_WIDTH)v0ROM_inst(
    vert_attr_rd_addr[0], 
    clk,   
    vert_attr_rd_en[0],        
    vert_attr_rd_data[0]
);
v1ROM #(DATA_WIDTH, ADDR_WIDTH)v1ROM_inst(
    vert_attr_rd_addr[1], 
    clk,   
    vert_attr_rd_en[1],        
    vert_attr_rd_data[1]
);
v2ROM #(DATA_WIDTH, ADDR_WIDTH)v2ROM_inst(
    vert_attr_rd_addr[2], 
    clk,   
    vert_attr_rd_en[2],        
    vert_attr_rd_data[2]
);

fNToRecFN#(8,24) fNToRecFNx (Pin[63:32], PinRecFN[65:33]);
fNToRecFN#(8,24) fNToRecFNy (Pin[31:0], PinRecFN[32:0]);


wire [32:0] halfrecfp;
fNToRecFN#(8,24) fNToRecFNtest (HalfFP, halfrecfp);

fragment_interpolator #(
    DATA_WIDTH, ADDR_WIDTH, CYCLES_WAIT_FOR_RECIEVE
) DUT (
    clk,resetn,en,
    frag_attr_wr_data,       
    frag_attr_wr_addr, 
    frag_attr_wr_en,  

    vert_attr_rd_data,       
    vert_attr_rd_addr, 
    vert_attr_rd_en,    

    PinRecFN,

    start, done,   
    
    noPerspective,
    flat, provokeMode,
    vertexSize 
);

simple_ram_dual_clock#(
    DATA_WIDTH,
    ADDR_WIDTH
) frag_mem (
    .data(frag_attr_wr_data),
    .read_addr(),
    .write_addr(frag_attr_wr_addr),
    .we(frag_attr_wr_en),
    .read_clk(clk),
    .write_clk(clk),
    .re(),
    .q()
);
    initial
        begin
            resetn = 1'b1;
            #(PERIOD/2);
            resetn = 1'b0; 
            #(PERIOD/2);
            resetn = 1'b1;
            #(PERIOD/2);
            en = 1'b1;
            start = 1'b1;
            Pin = PIN;
            noPerspective = NOPERSPECTIVE;
            flat = FLAT;
            provokeMode = PROVOKEMODE;
            vertexSize = VERTEXSIZE;
            #PERIOD;
            start = 1'b0;

        end
    always 
        begin
            clk = 1'b1; 
            #(PERIOD/2);
            clk = 1'b0;
            #(PERIOD/2);
        end
    
    always @(frag_attr_wr_en, frag_attr_wr_data, frag_attr_wr_addr) begin
        if(frag_attr_wr_en) begin
            $display("[fragment_write] data:0x%0h, addr:0x%0h ", frag_attr_wr_data, frag_attr_wr_addr);
        end
    end







    initial 
        begin
            #TIMEOUT;
            $display("Simulation Timed Out :(");
            $finish;
        end
    initial
        begin
            $dumpfile("fragment_interpolator_Test.vcd");
            $dumpvars(0,fragment_interpolator_Test);
            #1;
        end
endmodule