data/full_repos/permissive/48250786/test_mixcolumns.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/48250786/test_mixcolumns.v:47: Unsupported: Ignoring delay on this delayed statement.\n  #20 mixIn = 32\'he0b452ae;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_mixcolumns.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #20 mixIn = 32\'hb84111f1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_mixcolumns.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #20 mixIn = 32\'h1e2798e5;\n  ^\n%Error: data/full_repos/permissive/48250786/test_mixcolumns.v:35: Cannot find file containing module: \'mixColumns\'\n mixColumns uut (\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/48250786,data/full_repos/permissive/48250786/mixColumns\n             data/full_repos/permissive/48250786,data/full_repos/permissive/48250786/mixColumns.v\n             data/full_repos/permissive/48250786,data/full_repos/permissive/48250786/mixColumns.sv\n             mixColumns\n             mixColumns.v\n             mixColumns.sv\n             obj_dir/mixColumns\n             obj_dir/mixColumns.v\n             obj_dir/mixColumns.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_mixcolumns;


	reg [31:0] mixIn;
	reg inv;


	wire [31:0] mixOut;


	mixColumns uut (
		.mixOut(mixOut), 
		.mixIn(mixIn), 
		.inv(inv)
	);

	initial begin

		
		inv = 0;
		
		mixIn = 32'hd4bf5d30;
		#20 mixIn = 32'he0b452ae;
		#20 mixIn = 32'hb84111f1;
		#20 mixIn = 32'h1e2798e5;
      


	end
      
endmodule
module test_mixcolumns;



	reg [31:0] mixIn;
	reg inv;


	wire [31:0] mixOut;


	mixColumns uut (
		.mixOut(mixOut), 
		.mixIn(mixIn), 
		.inv(inv)
	);

	initial begin

		
		inv = 0;
		
		mixIn = 32'hd4bf5d30;
		#20 mixIn = 32'he0b452ae;
		#20 mixIn = 32'hb84111f1;
		#20 mixIn = 32'h1e2798e5;
      


	end
      
endmodule