data/full_repos/permissive/42581625/PersonalComputer/NumIn.v
data/verilator_xmls/5f302274-8917-462c-8f81-f95b9f2ff9b2.xml
module NumIn(
input clk,
input[7:0] addFlag,
output reg[31:0] number
    );
wire[7:0] btn_out;
	pbdebounce p0(clk,addFlag[0],btn_out[0]);
	pbdebounce p1(clk,addFlag[1],btn_out[1]);
	pbdebounce p2(clk,addFlag[2],btn_out[2]);
	pbdebounce p3(clk,addFlag[3],btn_out[3]);
	pbdebounce p4(clk,addFlag[4],btn_out[4]);
	pbdebounce p5(clk,addFlag[5],btn_out[5]);
	pbdebounce p6(clk,addFlag[6],btn_out[6]);
	pbdebounce p7(clk,addFlag[7],btn_out[7]);
	
	always @(posedge btn_out[0]) number[ 3: 0] <= number[ 3: 0] + 4'd1;
	always @(posedge btn_out[1]) number[ 7: 4] <= number[ 7: 4] + 4'd1;
	always @(posedge btn_out[2]) number[11: 8] <= number[11: 8] + 4'd1;
	always @(posedge btn_out[3]) number[15:12] <= number[15:12] + 4'd1;
	always @(posedge btn_out[4]) number[19:16] <= number[19:16] + 4'd1;
	always @(posedge btn_out[5]) number[23:20] <= number[23:20] + 4'd1;
	always @(posedge btn_out[6]) number[27:24] <= number[27:24] + 4'd1;
	always @(posedge btn_out[7]) number[31:28] <= number[31:28] + 4'd1;
endmodule
module NumIn(
input clk,
input[7:0] addFlag,
output reg[31:0] number
    );

wire[7:0] btn_out;
	pbdebounce p0(clk,addFlag[0],btn_out[0]);
	pbdebounce p1(clk,addFlag[1],btn_out[1]);
	pbdebounce p2(clk,addFlag[2],btn_out[2]);
	pbdebounce p3(clk,addFlag[3],btn_out[3]);
	pbdebounce p4(clk,addFlag[4],btn_out[4]);
	pbdebounce p5(clk,addFlag[5],btn_out[5]);
	pbdebounce p6(clk,addFlag[6],btn_out[6]);
	pbdebounce p7(clk,addFlag[7],btn_out[7]);
	
	always @(posedge btn_out[0]) number[ 3: 0] <= number[ 3: 0] + 4'd1;
	always @(posedge btn_out[1]) number[ 7: 4] <= number[ 7: 4] + 4'd1;
	always @(posedge btn_out[2]) number[11: 8] <= number[11: 8] + 4'd1;
	always @(posedge btn_out[3]) number[15:12] <= number[15:12] + 4'd1;
	always @(posedge btn_out[4]) number[19:16] <= number[19:16] + 4'd1;
	always @(posedge btn_out[5]) number[23:20] <= number[23:20] + 4'd1;
	always @(posedge btn_out[6]) number[27:24] <= number[27:24] + 4'd1;
	always @(posedge btn_out[7]) number[31:28] <= number[31:28] + 4'd1;
endmodule