data/full_repos/permissive/441359809/src/yosys/tests/simple/dff_different_styles.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/tests/simple/dff_different_styles.v:9: Multiple top level modules\n                                                                                                       : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                       : ... Top module \'dff\'\nmodule dff(clk, d, q);\n       ^~~\n                                                                                                       : ... Top module \'dffa\'\nmodule dffa(clk, arst, d, q);\n       ^~~~\n                                                                                                       : ... Top module \'dffa1\'\nmodule dffa1(clk, arst, d, q);\n       ^~~~~\n                                                                                                       : ... Top module \'dffa2\'\nmodule dffa2(clk, arst, d, q);\n       ^~~~~\n                                                                                                       : ... Top module \'dffa3\'\nmodule dffa3(clk, arst, d, q);\n       ^~~~~\n                                                                                                       : ... Top module \'dffa4\'\nmodule dffa4(clk, arst1, arst2, arst3, d, q);\n       ^~~~~\n                                                                                                       : ... Top module \'dffsr1\'\nmodule dffsr1(clk, arst, d, q);\n       ^~~~~~\n                                                                                                       : ... Top module \'dffsr2\'\nmodule dffsr2(clk, preset, clear, d, q);\n       ^~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module dffa1(clk, arst, d, q);
input clk, arst, d;
output reg q;
always @(posedge clk or negedge arst) begin
	if (~arst)
		q <= 0;
	else
		q <= d;
end
endmodule
module dffa1(clk, arst, d, q);

input clk, arst, d;
output reg q;
always @(posedge clk or negedge arst) begin
	if (~arst)
		q <= 0;
	else
		q <= d;
end
endmodule