data/full_repos/permissive/509809169/Verilog Language/More Verilog Features/Generate for loop_ 100bit adder.v
1: b'%Error: Cannot find file containing module: Language/More\n        ... Looked in:\n             data/full_repos/permissive/509809169/Verilog/Language/More\n             data/full_repos/permissive/509809169/Verilog/Language/More.v\n             data/full_repos/permissive/509809169/Verilog/Language/More.sv\n             Language/More\n             Language/More.v\n             Language/More.sv\n             obj_dir/Language/More\n             obj_dir/Language/More.v\n             obj_dir/Language/More.sv\n%Error: Cannot find file containing module: Verilog\n%Error: Cannot find file containing module: Features,data/full_repos/permissive/509809169\n%Error: Cannot find file containing module: data/full_repos/permissive/509809169/Verilog\n%Error: Cannot find file containing module: Features/Generate\n%Error: Cannot find file containing module: for\n%Error: Cannot find file containing module: loop_\n%Error: Cannot find file containing module: 100bit\n%Error: Cannot find file containing module: adder.v\n%Error: Exiting due to 9 error(s)\n'
module FA(
    input a,b,
    input cin,
    output cout,sum);
	
    assign sum  = a^b^cin;
    assign cout = (a&b)|(b&cin)|(cin&a);
endmodule
module FA(
    input a,b,
    input cin,
    output cout,sum);

	
    assign sum  = a^b^cin;
    assign cout = (a&b)|(b&cin)|(cin&a);
endmodule