data/full_repos/permissive/458737381/src/verilog-parser/tests/macros.v
data/verilator_xmls/e7b762cf-b067-49ec-b423-8daafa4fdb7b.xml
module bus_snooper(
    input [31:0]        safe_buslines,
    input [`BUS_RANGE]  bus_lines_1,
    input [`BUS_RANGE]  bus_lines_2
);

`undef BUS_WIDTH

`undef BUS_RANGE

endmodule
module bus_snooper(
    input [31:0]        safe_buslines,
    input [`BUS_RANGE]  bus_lines_1,
    input [`BUS_RANGE]  bus_lines_2
);


`undef BUS_WIDTH

`undef BUS_RANGE

endmodule