data/full_repos/permissive/488739248/rtl/ttl/ttl_74163a_sync.v
data/verilator_xmls/e2ad58fc-e805-4975-9662-f7e82c4d8450.xml
module ttl_74163a_sync #(parameter WIDTH = 4)
(
  input wire Clk,
  input wire Rst_n,
  input wire Clear_bar,
  input wire Load_bar,
  input wire ENT,
  input wire ENP,
  input wire [WIDTH-1:0] D,

  input wire Cen,
  output wire RCO,
  output wire [WIDTH-1:0] Q
);


wire RCO_current;
reg [WIDTH-1:0] Q_current;
wire [WIDTH-1:0] Q_next;
reg last_cen;
reg load_reg;

initial Q_current = {WIDTH{1'b0}};


assign Q_next = Q_current + 1;

always @(posedge Clk)
begin
  if (!Rst_n) begin
    Q_current <= {WIDTH{1'b0}};
    last_cen  <= 1;
    load_reg <= 1;
  end
  else begin
    last_cen <= Cen;
    load_reg <= Load_bar;
    if (!Clear_bar)  begin
      Q_current <= {WIDTH{1'b0}};
    end else
    begin
      if (!Load_bar && Cen && !last_cen) begin
        Q_current <= D;
      end
      else
      if (Load_bar && ENT && ENP && Cen && !last_cen) begin
        Q_current <= Q_next;
      end
    end
  end
end
  

assign RCO_current = ENT && (&Q_current);

assign RCO = RCO_current;
assign Q = Q_current;

endmodule
module ttl_74163a_sync #(parameter WIDTH = 4)
(
  input wire Clk,
  input wire Rst_n,
  input wire Clear_bar,
  input wire Load_bar,
  input wire ENT,
  input wire ENP,
  input wire [WIDTH-1:0] D,

  input wire Cen,
  output wire RCO,
  output wire [WIDTH-1:0] Q
);



wire RCO_current;
reg [WIDTH-1:0] Q_current;
wire [WIDTH-1:0] Q_next;
reg last_cen;
reg load_reg;

initial Q_current = {WIDTH{1'b0}};


assign Q_next = Q_current + 1;

always @(posedge Clk)
begin
  if (!Rst_n) begin
    Q_current <= {WIDTH{1'b0}};
    last_cen  <= 1;
    load_reg <= 1;
  end
  else begin
    last_cen <= Cen;
    load_reg <= Load_bar;
    if (!Clear_bar)  begin
      Q_current <= {WIDTH{1'b0}};
    end else
    begin
      if (!Load_bar && Cen && !last_cen) begin
        Q_current <= D;
      end
      else
      if (Load_bar && ENT && ENP && Cen && !last_cen) begin
        Q_current <= Q_next;
      end
    end
  end
end
  

assign RCO_current = ENT && (&Q_current);

assign RCO = RCO_current;
assign Q = Q_current;

endmodule