data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/auc_mmul.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/auc_mmul.v:307: Cannot find file containing module: 'auc_mmulinit'\nauc_mmulinit iauc_mmul_init\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult,data/full_repos/permissive/530013823/auc_mmulinit\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult,data/full_repos/permissive/530013823/auc_mmulinit.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult,data/full_repos/permissive/530013823/auc_mmulinit.sv\n             auc_mmulinit\n             auc_mmulinit.v\n             auc_mmulinit.sv\n             obj_dir/auc_mmulinit\n             obj_dir/auc_mmulinit.v\n             obj_dir/auc_mmulinit.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/auc_mmul.v:335: Cannot find file containing module: 'auc_mmulcomp'\nauc_mmulcomp iauc_mmul_comp\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/auc_mmul.v:368: Cannot find file containing module: 'auc_mmulfinal'\nauc_mmulfinal iauc_mmul_final\n^~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module auc_mmul
    (
     clk,
     rst,
     

     mmul_en,


     mmul_auvld,
     mmul_audat,
     mmul_aurswap,

     mmul_done,


     mmul_opcode,
     mmul_auen,
     mmul_carry,
     mmul_swapop,
     mmul_swapvl,
     

     mmul_ra,
     mmul_wa,
     mmul_we,
     mmul_wd
     );



parameter           WID   = 256;
parameter           CURWID = 255;
parameter           AWID  = 5;
parameter           OPWID = 4;


localparam          IDLE    = 2'b00;
localparam          INIT    = 2'b01;
localparam          COMP    = 2'b10;
localparam          FINAL   = 2'b11;




input     clk;
input     rst;
     

input     mmul_en;


input [WID-1:0] mmul_audat;
input           mmul_auvld;
input [WID-1:0] mmul_aurswap;


output          mmul_done;


output [OPWID-1:0] mmul_opcode;
output             mmul_auen;
output             mmul_carry;
output             mmul_swapop;
output             mmul_swapvl;


output [AWID-1:0]  mmul_ra;
output [AWID-1:0]  mmul_wa;
output             mmul_we;
output [WID-1:0]   mmul_wd;






reg     init_en;


wire [WID-1:0] init_audat;
wire           init_auvld;


wire          init_done;


wire [OPWID-1:0] init_opcode;
wire             init_auen;
wire             init_carry;


wire [AWID-1:0]  init_ra;
wire [AWID-1:0]  init_wa;
wire             init_we;
wire [WID-1:0]   init_wd;


reg     comp_en;


wire [WID-1:0] comp_audat;
wire           comp_auvld;
wire [WID-1:0] comp_aurswap;


wire          comp_done;


wire [OPWID-1:0] comp_opcode;
wire             comp_auen;
wire             comp_carry;
wire             comp_swapop;
wire             comp_swapvl;


wire [AWID-1:0]  comp_ra;
wire [AWID-1:0]  comp_wa;
wire             comp_we;
wire [WID-1:0]   comp_wd;


reg     final_en;


wire [WID-1:0] final_audat;
wire           final_auvld;
wire [WID-1:0] final_aurswap;


wire          final_done;


wire [OPWID-1:0] final_opcode;
wire             final_auen;
wire             final_carry;
wire             final_swapop;
wire             final_swapvl;


wire [AWID-1:0]  final_ra;
wire [AWID-1:0]  final_wa;
wire             final_we;
wire [WID-1:0]   final_wd;



reg [1:0]          main;

wire      mainisidle;

assign    mainisidle = main == IDLE;

wire      mainenidle;

assign    mainenidle = mainisidle & mmul_en;

reg       main_en;

wire      mainisinit;

assign    mainisinit = main == INIT;

wire      maindoneinit;

assign    maindoneinit = mainisinit & init_done;

wire      mainiscomp;

assign    mainiscomp = main == COMP;

wire      maindonecomp;

assign    maindonecomp = mainiscomp & comp_done;

wire      mainisfinal;

assign    mainisfinal = main == FINAL;

wire      maindonefinal;

assign    maindonefinal = mainisfinal & final_done;

always@(posedge clk)
    begin
    if(rst)
        begin
        main <= IDLE;
        end
    else
        begin
        if(mainenidle)
            begin
            main <= INIT;
            end
        else if(maindoneinit)
            begin
            main <= COMP;
            end
        else if(maindonecomp)
            begin
            main <= FINAL;
            end
        else if(maindonefinal)
            begin
            main <= IDLE;
            end
        else
            begin
            main <= main;
            end
        end
    end



always@(posedge clk)
    begin
    init_en <= mainenidle? 1'b1 : 1'b0;
    end

assign init_auvld = mmul_auvld;
assign init_audat = mmul_audat;



always@(posedge clk)
    begin
    comp_en <= maindoneinit? 1'b1 : 1'b0;
    end

assign comp_auvld = mmul_auvld;
assign comp_audat = mmul_audat;
assign comp_aurswap = mmul_aurswap;


always@(posedge clk)
    begin
    final_en <= maindonecomp? 1'b1 : 1'b0;
    end

assign final_auvld = mmul_auvld;
assign final_audat = mmul_audat;
assign final_aurswap = mmul_aurswap;



assign mmul_opcode = mainisinit? init_opcode:
       mainiscomp? comp_opcode:
       mainisfinal? final_opcode:
       4'b0;

assign mmul_auen = mainisinit? init_auen:
       mainiscomp? comp_auen:
       mainisfinal? final_auen:
       1'b0;

assign mmul_carry = mainisinit? init_carry:
       mainiscomp? comp_carry:
       mainisfinal? final_carry:
       1'b0;

assign mmul_swapop = mainiscomp? comp_swapop:
       mainisfinal? final_swapop:
       1'b0;

assign mmul_swapvl = mainiscomp? comp_swapvl:
       mainisfinal? final_swapvl:
       1'b0;

assign mmul_ra = mainisinit? init_ra:
       mainiscomp? comp_ra:
       mainisfinal? final_ra:
       5'b0;

assign mmul_wd = mainisinit? init_wd:
       mainiscomp? comp_wd:
       mainisfinal? final_wd:
       256'b0;

assign mmul_wa = mainisinit? init_wa:
       mainiscomp? comp_wa:
       mainisfinal? final_wa:
       5'b0;

assign mmul_we = mainisinit? init_we:
       mainiscomp? comp_we:
       mainisfinal? final_we:
       1'b0;



auc_mmulinit iauc_mmul_init
    (
     .clk(clk),
     .rst(rst),
     

     .init_en(init_en),


     .init_auvld(init_auvld),
     .init_audat(init_audat),
     

     .init_done(init_done),


     .init_opcode(init_opcode),
     .init_auen(init_auen),
     .init_carry(init_carry),
     

     .init_ra(init_ra),
     .init_wa(init_wa),
     .init_we(init_we),
     .init_wd(init_wd)
     );


auc_mmulcomp iauc_mmul_comp
    (
     .clk(clk),
     .rst(rst),
     

     .comp_en(comp_en),


     .comp_auvld(comp_auvld),
     .comp_audat(comp_audat),
     .comp_aurswap(comp_aurswap),
     

     .comp_done(comp_done),


     .comp_opcode(comp_opcode),
     .comp_auen(comp_auen),
     .comp_carry(comp_carry),
     .comp_swapvl(comp_swapvl),
     .comp_swapop(comp_swapop),
     

     .comp_ra(comp_ra),
     .comp_wa(comp_wa),
     .comp_we(comp_we),
     .comp_wd(comp_wd)
     );




auc_mmulfinal iauc_mmul_final
    (
     .clk(clk),
     .rst(rst),
     

     .final_en(final_en),


     .final_auvld(final_auvld),
     .final_audat(final_audat),
     .final_aurswap(final_aurswap),
     

     .final_done(final_done),


     .final_opcode(final_opcode),
     .final_auen(final_auen),
     .final_carry(final_carry),
     .final_swapvl(final_swapvl),
     .final_swapop(final_swapop),
     

     .final_ra(final_ra),
     .final_wa(final_wa),
     .final_we(final_we),
     .final_wd(final_wd)
     );
endmodule
module auc_mmul
    (
     clk,
     rst,
     

     mmul_en,


     mmul_auvld,
     mmul_audat,
     mmul_aurswap,

     mmul_done,


     mmul_opcode,
     mmul_auen,
     mmul_carry,
     mmul_swapop,
     mmul_swapvl,
     

     mmul_ra,
     mmul_wa,
     mmul_we,
     mmul_wd
     );




parameter           WID   = 256;
parameter           CURWID = 255;
parameter           AWID  = 5;
parameter           OPWID = 4;


localparam          IDLE    = 2'b00;
localparam          INIT    = 2'b01;
localparam          COMP    = 2'b10;
localparam          FINAL   = 2'b11;




input     clk;
input     rst;
     

input     mmul_en;


input [WID-1:0] mmul_audat;
input           mmul_auvld;
input [WID-1:0] mmul_aurswap;


output          mmul_done;


output [OPWID-1:0] mmul_opcode;
output             mmul_auen;
output             mmul_carry;
output             mmul_swapop;
output             mmul_swapvl;


output [AWID-1:0]  mmul_ra;
output [AWID-1:0]  mmul_wa;
output             mmul_we;
output [WID-1:0]   mmul_wd;






reg     init_en;


wire [WID-1:0] init_audat;
wire           init_auvld;


wire          init_done;


wire [OPWID-1:0] init_opcode;
wire             init_auen;
wire             init_carry;


wire [AWID-1:0]  init_ra;
wire [AWID-1:0]  init_wa;
wire             init_we;
wire [WID-1:0]   init_wd;


reg     comp_en;


wire [WID-1:0] comp_audat;
wire           comp_auvld;
wire [WID-1:0] comp_aurswap;


wire          comp_done;


wire [OPWID-1:0] comp_opcode;
wire             comp_auen;
wire             comp_carry;
wire             comp_swapop;
wire             comp_swapvl;


wire [AWID-1:0]  comp_ra;
wire [AWID-1:0]  comp_wa;
wire             comp_we;
wire [WID-1:0]   comp_wd;


reg     final_en;


wire [WID-1:0] final_audat;
wire           final_auvld;
wire [WID-1:0] final_aurswap;


wire          final_done;


wire [OPWID-1:0] final_opcode;
wire             final_auen;
wire             final_carry;
wire             final_swapop;
wire             final_swapvl;


wire [AWID-1:0]  final_ra;
wire [AWID-1:0]  final_wa;
wire             final_we;
wire [WID-1:0]   final_wd;



reg [1:0]          main;

wire      mainisidle;

assign    mainisidle = main == IDLE;

wire      mainenidle;

assign    mainenidle = mainisidle & mmul_en;

reg       main_en;

wire      mainisinit;

assign    mainisinit = main == INIT;

wire      maindoneinit;

assign    maindoneinit = mainisinit & init_done;

wire      mainiscomp;

assign    mainiscomp = main == COMP;

wire      maindonecomp;

assign    maindonecomp = mainiscomp & comp_done;

wire      mainisfinal;

assign    mainisfinal = main == FINAL;

wire      maindonefinal;

assign    maindonefinal = mainisfinal & final_done;

always@(posedge clk)
    begin
    if(rst)
        begin
        main <= IDLE;
        end
    else
        begin
        if(mainenidle)
            begin
            main <= INIT;
            end
        else if(maindoneinit)
            begin
            main <= COMP;
            end
        else if(maindonecomp)
            begin
            main <= FINAL;
            end
        else if(maindonefinal)
            begin
            main <= IDLE;
            end
        else
            begin
            main <= main;
            end
        end
    end



always@(posedge clk)
    begin
    init_en <= mainenidle? 1'b1 : 1'b0;
    end

assign init_auvld = mmul_auvld;
assign init_audat = mmul_audat;



always@(posedge clk)
    begin
    comp_en <= maindoneinit? 1'b1 : 1'b0;
    end

assign comp_auvld = mmul_auvld;
assign comp_audat = mmul_audat;
assign comp_aurswap = mmul_aurswap;


always@(posedge clk)
    begin
    final_en <= maindonecomp? 1'b1 : 1'b0;
    end

assign final_auvld = mmul_auvld;
assign final_audat = mmul_audat;
assign final_aurswap = mmul_aurswap;



assign mmul_opcode = mainisinit? init_opcode:
       mainiscomp? comp_opcode:
       mainisfinal? final_opcode:
       4'b0;

assign mmul_auen = mainisinit? init_auen:
       mainiscomp? comp_auen:
       mainisfinal? final_auen:
       1'b0;

assign mmul_carry = mainisinit? init_carry:
       mainiscomp? comp_carry:
       mainisfinal? final_carry:
       1'b0;

assign mmul_swapop = mainiscomp? comp_swapop:
       mainisfinal? final_swapop:
       1'b0;

assign mmul_swapvl = mainiscomp? comp_swapvl:
       mainisfinal? final_swapvl:
       1'b0;

assign mmul_ra = mainisinit? init_ra:
       mainiscomp? comp_ra:
       mainisfinal? final_ra:
       5'b0;

assign mmul_wd = mainisinit? init_wd:
       mainiscomp? comp_wd:
       mainisfinal? final_wd:
       256'b0;

assign mmul_wa = mainisinit? init_wa:
       mainiscomp? comp_wa:
       mainisfinal? final_wa:
       5'b0;

assign mmul_we = mainisinit? init_we:
       mainiscomp? comp_we:
       mainisfinal? final_we:
       1'b0;



auc_mmulinit iauc_mmul_init
    (
     .clk(clk),
     .rst(rst),
     

     .init_en(init_en),


     .init_auvld(init_auvld),
     .init_audat(init_audat),
     

     .init_done(init_done),


     .init_opcode(init_opcode),
     .init_auen(init_auen),
     .init_carry(init_carry),
     

     .init_ra(init_ra),
     .init_wa(init_wa),
     .init_we(init_we),
     .init_wd(init_wd)
     );


auc_mmulcomp iauc_mmul_comp
    (
     .clk(clk),
     .rst(rst),
     

     .comp_en(comp_en),


     .comp_auvld(comp_auvld),
     .comp_audat(comp_audat),
     .comp_aurswap(comp_aurswap),
     

     .comp_done(comp_done),


     .comp_opcode(comp_opcode),
     .comp_auen(comp_auen),
     .comp_carry(comp_carry),
     .comp_swapvl(comp_swapvl),
     .comp_swapop(comp_swapop),
     

     .comp_ra(comp_ra),
     .comp_wa(comp_wa),
     .comp_we(comp_we),
     .comp_wd(comp_wd)
     );




auc_mmulfinal iauc_mmul_final
    (
     .clk(clk),
     .rst(rst),
     

     .final_en(final_en),


     .final_auvld(final_auvld),
     .final_audat(final_audat),
     .final_aurswap(final_aurswap),
     

     .final_done(final_done),


     .final_opcode(final_opcode),
     .final_auen(final_auen),
     .final_carry(final_carry),
     .final_swapvl(final_swapvl),
     .final_swapop(final_swapop),
     

     .final_ra(final_ra),
     .final_wa(final_wa),
     .final_we(final_we),
     .final_wd(final_wd)
     );
endmodule