data/full_repos/permissive/441359809/src/yosys/tests/various/specify.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/tests/various/specify.v:16: Multiple top level modules\n                                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                            : ... Top module \'test\'\nmodule test (\n       ^~~~\n                                                                                            : ... Top module \'test2\'\nmodule test2 (\n       ^~~~~\n                                                                                            : ... Top module \'issue01144\'\nmodule issue01144(input clk, d, output q);\n       ^~~~~~~~~~\n                                                                                            : ... Top module \'test3\'\nmodule test3(input clk, input [1:0] d, output [1:0] q);\n       ^~~~~\n                                                                                            : ... Top module \'test4\'\nmodule test4(input clk, d, output q);\n       ^~~~~\n                                                                                            : ... Top module \'test5\'\nmodule test5(input clk, d, e, output q);\n       ^~~~~\n                                                                                            : ... Top module \'test6\'\nmodule test6(input clk, d, e, output q);\n       ^~~~~\n%Error: Exiting due to 1 warning(s)\n'
module test (
	input EN, CLK,
	input [3:0] D,
	output reg [3:0] Q
);
	always @(posedge CLK)
		if (EN) Q <= D;

	specify
		if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4);
		$setup(D, posedge CLK &&& EN, 5);
		$hold(posedge CLK, D &&& EN, 6);
	endspecify
endmodule
module test (
	input EN, CLK,
	input [3:0] D,
	output reg [3:0] Q
);

	always @(posedge CLK)
		if (EN) Q <= D;

	specify
		if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4);
		$setup(D, posedge CLK &&& EN, 5);
		$hold(posedge CLK, D &&& EN, 6);
	endspecify
endmodule