data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv
1: b'%Warning-LITENDIAN: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:17: Little bit endian vector: MSB < LSB of bit range: -2:0\n    output logic [N-1:0] value_o,\n                 ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:59: Little bit endian vector: MSB < LSB of bit range: -2:0\n        logic [N-1:0] q, d, taps;\n              ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:74: Extracting 4 bits from only 3 bit number\n                                                                                                                    : ... In instance snitch_icache_lfsr\n                d = {1\'b0, q[N-1:1]};\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:74: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n                                                                                                                            : ... In instance snitch_icache_lfsr\n                d = {1\'b0, q[N-1:1]};\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:84: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                            : ... In instance snitch_icache_lfsr\n                2:  taps = $unsigned( 1<< 1 | 1<< 0                 );\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:85: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                            : ... In instance snitch_icache_lfsr\n                3:  taps = $unsigned( 1<< 2 | 1<< 1                 );\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:86: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                            : ... In instance snitch_icache_lfsr\n                4:  taps = $unsigned( 1<< 3 | 1<< 2                 );\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:87: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                            : ... In instance snitch_icache_lfsr\n                5:  taps = $unsigned( 1<< 4 | 1<< 2                 );\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:88: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                            : ... In instance snitch_icache_lfsr\n                6:  taps = $unsigned( 1<< 5 | 1<< 4                 );\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:89: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                            : ... In instance snitch_icache_lfsr\n                7:  taps = $unsigned( 1<< 6 | 1<< 5                 );\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:90: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                            : ... In instance snitch_icache_lfsr\n                8:  taps = $unsigned( 1<< 7 | 1<< 5 | 1<< 4 | 1<< 3 );\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:91: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                            : ... In instance snitch_icache_lfsr\n                9:  taps = $unsigned( 1<< 8 | 1<< 4                 );\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:92: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                            : ... In instance snitch_icache_lfsr\n                10: taps = $unsigned( 1<< 9 | 1<< 6                 );\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:93: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                            : ... In instance snitch_icache_lfsr\n                11: taps = $unsigned( 1<<10 | 1<< 8                 );\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:94: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                            : ... In instance snitch_icache_lfsr\n                12: taps = $unsigned( 1<<11 | 1<<10 | 1<< 9 | 1<< 3 );\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:95: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                            : ... In instance snitch_icache_lfsr\n                13: taps = $unsigned( 1<<12 | 1<<11 | 1<<10 | 1<< 7 );\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:96: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                            : ... In instance snitch_icache_lfsr\n                14: taps = $unsigned( 1<<13 | 1<<12 | 1<<11 | 1<< 1 );\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:97: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                            : ... In instance snitch_icache_lfsr\n                15: taps = $unsigned( 1<<14 | 1<<13                 );\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:98: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                            : ... In instance snitch_icache_lfsr\n                16: taps = $unsigned( 1<<15 | 1<<14 | 1<<12 | 1<< 3 );\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:99: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                            : ... In instance snitch_icache_lfsr\n                17: taps = $unsigned( 1<<16 | 1<<13                 );\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:100: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                             : ... In instance snitch_icache_lfsr\n                18: taps = $unsigned( 1<<17 | 1<<10                 );\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:101: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                             : ... In instance snitch_icache_lfsr\n                19: taps = $unsigned( 1<<18 | 1<<17 | 1<<16 | 1<<13 );\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:102: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                             : ... In instance snitch_icache_lfsr\n                20: taps = $unsigned( 1<<19 | 1<<16                 );\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:103: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                             : ... In instance snitch_icache_lfsr\n                21: taps = $unsigned( 1<<20 | 1<<18                 );\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:104: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                             : ... In instance snitch_icache_lfsr\n                22: taps = $unsigned( 1<<21 | 1<<20                 );\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:105: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                             : ... In instance snitch_icache_lfsr\n                23: taps = $unsigned( 1<<22 | 1<<17                 );\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:106: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                             : ... In instance snitch_icache_lfsr\n                24: taps = $unsigned( 1<<23 | 1<<22 | 1<<21 | 1<<16 );\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:107: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                             : ... In instance snitch_icache_lfsr\n                25: taps = $unsigned( 1<<24 | 1<<21                 );\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:108: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                             : ... In instance snitch_icache_lfsr\n                26: taps = $unsigned( 1<<25 | 1<< 5 | 1<< 1 | 1<< 0 );\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:109: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                             : ... In instance snitch_icache_lfsr\n                27: taps = $unsigned( 1<<26 | 1<< 4 | 1<< 1 | 1<< 0 );\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:110: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                             : ... In instance snitch_icache_lfsr\n                28: taps = $unsigned( 1<<27 | 1<<24                 );\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:111: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                             : ... In instance snitch_icache_lfsr\n                29: taps = $unsigned( 1<<28 | 1<<26                 );\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:112: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                             : ... In instance snitch_icache_lfsr\n                30: taps = $unsigned( 1<<29 | 1<< 5 | 1<< 3 | 1<< 0 );\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:113: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                             : ... In instance snitch_icache_lfsr\n                31: taps = $unsigned( 1<<30 | 1<<27                 );\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv:114: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n                                                                                                                             : ... In instance snitch_icache_lfsr\n                32: taps = $unsigned( 1<<31 | 1<<21 | 1<< 1 | 1<< 0 );\n                         ^\n%Error: Exiting due to 1 error(s), 34 warning(s)\n'
module snitch_icache_lfsr #(
    parameter int N = -1
)(
    input  logic         clk_i,
    input  logic         rst_ni,
    output logic [N-1:0] value_o,
    input  logic         enable_i
);

    `ifndef SYNTHESIS
    initial assert(N > 0);
    `endif

    if (N > 32) begin : g_split

        localparam int N0 = N/2;
        localparam int N1 = N-N0;

        snitch_icache_lfsr #(N0) i_lo (
            .clk_i    ( clk_i           ),
            .rst_ni   ( rst_ni          ),
            .value_o  ( value_o[N0-1:0] ),
            .enable_i ( enable_i        )
        );

        snitch_icache_lfsr #(N1) i_hi (
            .clk_i    ( clk_i                            ),
            .rst_ni   ( rst_ni                           ),
            .value_o  ( value_o[N-1:N0]                  ),
            .enable_i ( enable_i && value_o[N0-1:0] == 0 )
        );

    end else if (N == 1) begin : g_toggle

        logic q;

        always_ff @(posedge clk_i, negedge rst_ni) begin
            if (!rst_ni)
                q <= 0;
            else if (enable_i)
                q <= ~q;
        end

        assign value_o = q;

    end else begin : g_impl

        logic [N-1:0] q, d, taps;

        assign value_o = q;

        always_ff @(posedge clk_i, negedge rst_ni) begin
            if (!rst_ni)
                q <= 0;
            else if (enable_i)
                q <= d;
        end

        always_comb begin
            if (q == '0) begin
                d = '1;
            end else begin
                d = {1'b0, q[N-1:1]};
                if (q[0]) d ^= taps;
                if (d == '1) d = '0;
            end
        end


        always_comb begin
            taps = 1 << (N-1);
            case (N)
                2:  taps = $unsigned( 1<< 1 | 1<< 0                 );
                3:  taps = $unsigned( 1<< 2 | 1<< 1                 );
                4:  taps = $unsigned( 1<< 3 | 1<< 2                 );
                5:  taps = $unsigned( 1<< 4 | 1<< 2                 );
                6:  taps = $unsigned( 1<< 5 | 1<< 4                 );
                7:  taps = $unsigned( 1<< 6 | 1<< 5                 );
                8:  taps = $unsigned( 1<< 7 | 1<< 5 | 1<< 4 | 1<< 3 );
                9:  taps = $unsigned( 1<< 8 | 1<< 4                 );
                10: taps = $unsigned( 1<< 9 | 1<< 6                 );
                11: taps = $unsigned( 1<<10 | 1<< 8                 );
                12: taps = $unsigned( 1<<11 | 1<<10 | 1<< 9 | 1<< 3 );
                13: taps = $unsigned( 1<<12 | 1<<11 | 1<<10 | 1<< 7 );
                14: taps = $unsigned( 1<<13 | 1<<12 | 1<<11 | 1<< 1 );
                15: taps = $unsigned( 1<<14 | 1<<13                 );
                16: taps = $unsigned( 1<<15 | 1<<14 | 1<<12 | 1<< 3 );
                17: taps = $unsigned( 1<<16 | 1<<13                 );
                18: taps = $unsigned( 1<<17 | 1<<10                 );
                19: taps = $unsigned( 1<<18 | 1<<17 | 1<<16 | 1<<13 );
                20: taps = $unsigned( 1<<19 | 1<<16                 );
                21: taps = $unsigned( 1<<20 | 1<<18                 );
                22: taps = $unsigned( 1<<21 | 1<<20                 );
                23: taps = $unsigned( 1<<22 | 1<<17                 );
                24: taps = $unsigned( 1<<23 | 1<<22 | 1<<21 | 1<<16 );
                25: taps = $unsigned( 1<<24 | 1<<21                 );
                26: taps = $unsigned( 1<<25 | 1<< 5 | 1<< 1 | 1<< 0 );
                27: taps = $unsigned( 1<<26 | 1<< 4 | 1<< 1 | 1<< 0 );
                28: taps = $unsigned( 1<<27 | 1<<24                 );
                29: taps = $unsigned( 1<<28 | 1<<26                 );
                30: taps = $unsigned( 1<<29 | 1<< 5 | 1<< 3 | 1<< 0 );
                31: taps = $unsigned( 1<<30 | 1<<27                 );
                32: taps = $unsigned( 1<<31 | 1<<21 | 1<< 1 | 1<< 0 );
            endcase;
        end

    end

endmodule
module snitch_icache_lfsr #(
    parameter int N = -1
)(
    input  logic         clk_i,
    input  logic         rst_ni,
    output logic [N-1:0] value_o,
    input  logic         enable_i
);


    `ifndef SYNTHESIS
    initial assert(N > 0);
    `endif

    if (N > 32) begin : g_split

        localparam int N0 = N/2;
        localparam int N1 = N-N0;

        snitch_icache_lfsr #(N0) i_lo (
            .clk_i    ( clk_i           ),
            .rst_ni   ( rst_ni          ),
            .value_o  ( value_o[N0-1:0] ),
            .enable_i ( enable_i        )
        );

        snitch_icache_lfsr #(N1) i_hi (
            .clk_i    ( clk_i                            ),
            .rst_ni   ( rst_ni                           ),
            .value_o  ( value_o[N-1:N0]                  ),
            .enable_i ( enable_i && value_o[N0-1:0] == 0 )
        );

    end else if (N == 1) begin : g_toggle

        logic q;

        always_ff @(posedge clk_i, negedge rst_ni) begin
            if (!rst_ni)
                q <= 0;
            else if (enable_i)
                q <= ~q;
        end

        assign value_o = q;

    end else begin : g_impl

        logic [N-1:0] q, d, taps;

        assign value_o = q;

        always_ff @(posedge clk_i, negedge rst_ni) begin
            if (!rst_ni)
                q <= 0;
            else if (enable_i)
                q <= d;
        end

        always_comb begin
            if (q == '0) begin
                d = '1;
            end else begin
                d = {1'b0, q[N-1:1]};
                if (q[0]) d ^= taps;
                if (d == '1) d = '0;
            end
        end


        always_comb begin
            taps = 1 << (N-1);
            case (N)
                2:  taps = $unsigned( 1<< 1 | 1<< 0                 );
                3:  taps = $unsigned( 1<< 2 | 1<< 1                 );
                4:  taps = $unsigned( 1<< 3 | 1<< 2                 );
                5:  taps = $unsigned( 1<< 4 | 1<< 2                 );
                6:  taps = $unsigned( 1<< 5 | 1<< 4                 );
                7:  taps = $unsigned( 1<< 6 | 1<< 5                 );
                8:  taps = $unsigned( 1<< 7 | 1<< 5 | 1<< 4 | 1<< 3 );
                9:  taps = $unsigned( 1<< 8 | 1<< 4                 );
                10: taps = $unsigned( 1<< 9 | 1<< 6                 );
                11: taps = $unsigned( 1<<10 | 1<< 8                 );
                12: taps = $unsigned( 1<<11 | 1<<10 | 1<< 9 | 1<< 3 );
                13: taps = $unsigned( 1<<12 | 1<<11 | 1<<10 | 1<< 7 );
                14: taps = $unsigned( 1<<13 | 1<<12 | 1<<11 | 1<< 1 );
                15: taps = $unsigned( 1<<14 | 1<<13                 );
                16: taps = $unsigned( 1<<15 | 1<<14 | 1<<12 | 1<< 3 );
                17: taps = $unsigned( 1<<16 | 1<<13                 );
                18: taps = $unsigned( 1<<17 | 1<<10                 );
                19: taps = $unsigned( 1<<18 | 1<<17 | 1<<16 | 1<<13 );
                20: taps = $unsigned( 1<<19 | 1<<16                 );
                21: taps = $unsigned( 1<<20 | 1<<18                 );
                22: taps = $unsigned( 1<<21 | 1<<20                 );
                23: taps = $unsigned( 1<<22 | 1<<17                 );
                24: taps = $unsigned( 1<<23 | 1<<22 | 1<<21 | 1<<16 );
                25: taps = $unsigned( 1<<24 | 1<<21                 );
                26: taps = $unsigned( 1<<25 | 1<< 5 | 1<< 1 | 1<< 0 );
                27: taps = $unsigned( 1<<26 | 1<< 4 | 1<< 1 | 1<< 0 );
                28: taps = $unsigned( 1<<27 | 1<<24                 );
                29: taps = $unsigned( 1<<28 | 1<<26                 );
                30: taps = $unsigned( 1<<29 | 1<< 5 | 1<< 3 | 1<< 0 );
                31: taps = $unsigned( 1<<30 | 1<<27                 );
                32: taps = $unsigned( 1<<31 | 1<<21 | 1<< 1 | 1<< 0 );
            endcase;
        end

    end

endmodule