data/full_repos/permissive/460328193/ipa_proj_pipe/alu_tb.v
1: b'%Error: data/full_repos/permissive/460328193/ipa_proj_pipe/alu_tb.v:1: Cannot find include file: alu.v\n`include"alu.v" \n        ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/460328193/ipa_proj_pipe,data/full_repos/permissive/460328193/alu.v\n             data/full_repos/permissive/460328193/ipa_proj_pipe,data/full_repos/permissive/460328193/alu.v.v\n             data/full_repos/permissive/460328193/ipa_proj_pipe,data/full_repos/permissive/460328193/alu.v.sv\n             alu.v\n             alu.v.v\n             alu.v.sv\n             obj_dir/alu.v\n             obj_dir/alu.v.v\n             obj_dir/alu.v.sv\n%Error: data/full_repos/permissive/460328193/ipa_proj_pipe/alu_tb.v:11: Unsupported or unknown PLI call: $monitor\n $monitor ($time,"ns:  control =  %b,\\n\\t\\t        a = %b,\\n\\t\\t        b = %b,\\n\\t\\t   result = %b, overflow=%b \\n",control,a, b, out,c); \n ^~~~~~~~\n%Error: data/full_repos/permissive/460328193/ipa_proj_pipe/alu_tb.v:12: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("alu.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/460328193/ipa_proj_pipe/alu_tb.v:13: Unsupported or unknown PLI call: $dumpvars\n     $dumpvars(0,control,a,b,c,out);\n     ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/460328193/ipa_proj_pipe/alu_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/460328193/ipa_proj_pipe/alu_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module testbench;
	reg [63:0] a,b;
	reg [1:0] control;
	wire [63:0] out;
	wire c;
	integer i,k,j;
	alu DUT(control,a,b,out,c);
	initial begin
	$monitor ($time,"ns:  control =  %b,\n\t\t        a = %b,\n\t\t        b = %b,\n\t\t   result = %b, overflow=%b \n",control,a, b, out,c); 
	$dumpfile("alu.vcd");
    	$dumpvars(0,control,a,b,c,out);
	b=2**6-1;
	a=2**6-1;
	control=0;
	#10;
	for(j=0;j<4;j++) begin
	control=j;
	b=2**6-1;
	a=2**6-1;
	for(i=0; i<=2**3-1; i++) begin
		a=2**6-1;
		for(k=0;k<=2**3-1;k++) begin
		a--;
		#10;
		end
		b--;
	end
	end
	end
endmodule
module testbench;

	reg [63:0] a,b;
	reg [1:0] control;
	wire [63:0] out;
	wire c;
	integer i,k,j;
	alu DUT(control,a,b,out,c);
	initial begin
	$monitor ($time,"ns:  control =  %b,\n\t\t        a = %b,\n\t\t        b = %b,\n\t\t   result = %b, overflow=%b \n",control,a, b, out,c); 
	$dumpfile("alu.vcd");
    	$dumpvars(0,control,a,b,c,out);
	b=2**6-1;
	a=2**6-1;
	control=0;
	#10;
	for(j=0;j<4;j++) begin
	control=j;
	b=2**6-1;
	a=2**6-1;
	for(i=0; i<=2**3-1; i++) begin
		a=2**6-1;
		for(k=0;k<=2**3-1;k++) begin
		a--;
		#10;
		end
		b--;
	end
	end
	end
endmodule