data/full_repos/permissive/48787480/hdl/src/test.v
1: b'%Error: data/full_repos/permissive/48787480/hdl/src/test.v:5: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("test.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/48787480/hdl/src/test.v:6: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, test);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/48787480/hdl/src/test.v:11: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk <= ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/48787480/hdl/src/test.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #1 rst_ = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48787480/hdl/src/test.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #6 rst_ = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/48787480/hdl/src/test.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #10000 $finish;\n        ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;
    initial begin
        $dumpfile("test.vcd");
        $dumpvars(0, test);
    end

    reg clk = 0;
    always begin
        #5 clk <= ~clk;
    end

    reg rst_;
    initial begin
        rst_ = 1;
        #1 rst_ = 0;
        #6 rst_ = 1;
        #10000 $finish;
    end

    top top(
        .clk(clk), .rst_(rst_)
    );

endmodule
module test;

    initial begin
        $dumpfile("test.vcd");
        $dumpvars(0, test);
    end

    reg clk = 0;
    always begin
        #5 clk <= ~clk;
    end

    reg rst_;
    initial begin
        rst_ = 1;
        #1 rst_ = 0;
        #6 rst_ = 1;
        #10000 $finish;
    end

    top top(
        .clk(clk), .rst_(rst_)
    );

endmodule