data/full_repos/permissive/449521261/parallel_to_UART.v
1: b'%Warning-WIDTH: data/full_repos/permissive/449521261/parallel_to_UART.v:216: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'clock_divider\' generates 11 bits.\n                                                                           : ... In instance parallel_to_UART.serial_clock\n            end else if(clock_divider == max_counter) begin\n                                      ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/449521261/parallel_to_UART.v:214: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'clock_divider\' generates 11 bits.\n                                                                           : ... In instance parallel_to_UART.serial_clock\n            if(clock_divider == max_counter/2) begin\n                             ^~\n%Error: Exiting due to 2 warning(s)\n'
module mux_4_bit(


    input data_input_0,
    input data_input_1,
    input data_input_2,
    input data_input_3,
    input data_input_4,
    input data_input_5,
    input data_input_6,
    input data_input_7,
    input data_input_8,
    input data_input_9,
    input data_input_10,
    input data_input_11,
    input [3:0] select,
    output reg mux_output
    );


    always @ (*) begin
        case(select)
            'd0 : mux_output <= data_input_0;
            'd1 : mux_output <= data_input_1;
            'd2 : mux_output <= data_input_2;
            'd3 : mux_output <= data_input_3;
            'd4 : mux_output <= data_input_4;
            'd5 : mux_output <= data_input_5;
            'd6 : mux_output <= data_input_6;
            'd7 : mux_output <= data_input_7;
            'd8 : mux_output <= data_input_8;
            'd9 : mux_output <= data_input_9;
            'd10 : mux_output <= data_input_10;
            'd11 : mux_output <= data_input_11;
            default: mux_output <= 'b0;
        endcase
    end
endmodule
module mux_4_bit(


    input data_input_0,
    input data_input_1,
    input data_input_2,
    input data_input_3,
    input data_input_4,
    input data_input_5,
    input data_input_6,
    input data_input_7,
    input data_input_8,
    input data_input_9,
    input data_input_10,
    input data_input_11,
    input [3:0] select,
    output reg mux_output
    );



    always @ (*) begin
        case(select)
            'd0 : mux_output <= data_input_0;
            'd1 : mux_output <= data_input_1;
            'd2 : mux_output <= data_input_2;
            'd3 : mux_output <= data_input_3;
            'd4 : mux_output <= data_input_4;
            'd5 : mux_output <= data_input_5;
            'd6 : mux_output <= data_input_6;
            'd7 : mux_output <= data_input_7;
            'd8 : mux_output <= data_input_8;
            'd9 : mux_output <= data_input_9;
            'd10 : mux_output <= data_input_10;
            'd11 : mux_output <= data_input_11;
            default: mux_output <= 'b0;
        endcase
    end
endmodule