data/full_repos/permissive/529642835/rtl/Pokey/latch_delay_line.v
1: b'%Error: data/full_repos/permissive/529642835/rtl/Pokey/latch_delay_line.v:51: [0:1] Range extract has backward bit ordering, perhaps you wanted [1:0]\n                                                                            : ... In instance latch_delay_line\n         shift_next <= {(data_in | data_in_reg), shift_reg[count - 1:1]};\n                                                          ^\n%Error: data/full_repos/permissive/529642835/rtl/Pokey/latch_delay_line.v:51: Extracting 2 bits from only 1 bit number\n                                                                            : ... In instance latch_delay_line\n         shift_next <= {(data_in | data_in_reg), shift_reg[count - 1:1]};\n                                                          ^\n%Warning-SELRANGE: data/full_repos/permissive/529642835/rtl/Pokey/latch_delay_line.v:51: Selection index out of range: 2:1 outside 0:0\n                                                                                       : ... In instance latch_delay_line\n         shift_next <= {(data_in | data_in_reg), shift_reg[count - 1:1]};\n                                                          ^\n                   ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/529642835/rtl/Pokey/latch_delay_line.v:51: Operator ASSIGNDLY expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 3 bits.\n                                                                                    : ... In instance latch_delay_line\n         shift_next <= {(data_in | data_in_reg), shift_reg[count - 1:1]};\n                    ^~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module latch_delay_line(clk, ce, sync_reset, data_in, enable, reset_n, data_out);
   parameter       count = 1;
   input           clk;
   input           ce;
   input           sync_reset;
   input           data_in;
   input           enable;
   input           reset_n;
   
   output          data_out;
   
   reg [count-1:0] shift_reg;
   reg [count-1:0] shift_next;
   
   reg             data_in_reg;
   reg             data_in_next;
   
   always @(posedge clk or negedge reset_n)
      if (reset_n == 1'b0)
      begin
         shift_reg <= {count{1'b0}};
         data_in_reg <= 1'b0;
      end
      else if (ce)
      begin
         shift_reg <= shift_next;
         data_in_reg <= data_in_next;
      end
   
   
   always @(shift_reg or enable or data_in or data_in_reg or sync_reset)
   begin
      shift_next <= shift_reg;
      
      data_in_next <= data_in | data_in_reg;
      
      if (enable == 1'b1)
      begin
         shift_next <= {(data_in | data_in_reg), shift_reg[count - 1:1]};
         data_in_next <= 1'b0;
      end
      
      if (sync_reset == 1'b1)
      begin
         shift_next <= {count{1'b0}};
         data_in_next <= 1'b0;
      end
   end
   
   assign data_out = shift_reg[0] & enable;
   
endmodule
module latch_delay_line(clk, ce, sync_reset, data_in, enable, reset_n, data_out);

   parameter       count = 1;
   input           clk;
   input           ce;
   input           sync_reset;
   input           data_in;
   input           enable;
   input           reset_n;
   
   output          data_out;
   
   reg [count-1:0] shift_reg;
   reg [count-1:0] shift_next;
   
   reg             data_in_reg;
   reg             data_in_next;
   
   always @(posedge clk or negedge reset_n)
      if (reset_n == 1'b0)
      begin
         shift_reg <= {count{1'b0}};
         data_in_reg <= 1'b0;
      end
      else if (ce)
      begin
         shift_reg <= shift_next;
         data_in_reg <= data_in_next;
      end
   
   
   always @(shift_reg or enable or data_in or data_in_reg or sync_reset)
   begin
      shift_next <= shift_reg;
      
      data_in_next <= data_in | data_in_reg;
      
      if (enable == 1'b1)
      begin
         shift_next <= {(data_in | data_in_reg), shift_reg[count - 1:1]};
         data_in_next <= 1'b0;
      end
      
      if (sync_reset == 1'b1)
      begin
         shift_next <= {count{1'b0}};
         data_in_next <= 1'b0;
      end
   end
   
   assign data_out = shift_reg[0] & enable;
   
endmodule