data/full_repos/permissive/496508301/Lesson10/UART_top.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson10/UART_top.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #17       res <= 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson10/UART_top.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #3000000  $stop;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson10/UART_top.v:67: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk <= ~clk;\n       ^\n%Error: data/full_repos/permissive/496508301/Lesson10/UART_top.v:82: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("UART_top_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/496508301/Lesson10/UART_top.v:83: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(clk, res, RX, TX);\n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module UART_top_tb;
reg         clk;
reg         res;
wire        RX;
wire        TX;

reg[45:0]   RX_send;
assign      RX = RX_send[0];
reg[12:0]   con;
UART_top UART_top(
            clk,
            res,
            RX,
            TX
);
initial begin
    clk <= 0; res <= 0; 
    RX_send <= {1'b1, 8'h0A, 1'b0, 1'b1, 8'hA0, 1'b0, 1'b1, 8'h0a, 1'b0, 16'hffff}; con <= 0;
    #17       res <= 1;
    #3000000  $stop;
end
always #5 clk <= ~clk;
always @(posedge clk) begin
    if (con == 5000-1)begin
        con <= 0;
    end
    else begin
        con <= con+1;
    end
    if (con == 0)begin
        RX_send[44:0] <= RX_send[45:1];
        RX_send[45] <= RX_send[0]; 
    end
end

initial begin
    $dumpfile("UART_top_tb.vcd");
    $dumpvars(clk, res, RX, TX);
end

endmodule
module UART_top_tb;

reg         clk;
reg         res;
wire        RX;
wire        TX;

reg[45:0]   RX_send;
assign      RX = RX_send[0];
reg[12:0]   con;
UART_top UART_top(
            clk,
            res,
            RX,
            TX
);
initial begin
    clk <= 0; res <= 0; 
    RX_send <= {1'b1, 8'h0A, 1'b0, 1'b1, 8'hA0, 1'b0, 1'b1, 8'h0a, 1'b0, 16'hffff}; con <= 0;
    #17       res <= 1;
    #3000000  $stop;
end
always #5 clk <= ~clk;
always @(posedge clk) begin
    if (con == 5000-1)begin
        con <= 0;
    end
    else begin
        con <= con+1;
    end
    if (con == 0)begin
        RX_send[44:0] <= RX_send[45:1];
        RX_send[45] <= RX_send[0]; 
    end
end

initial begin
    $dumpfile("UART_top_tb.vcd");
    $dumpvars(clk, res, RX, TX);
end

endmodule