data/full_repos/permissive/415491487/design_src/main_bus.v
1: b'%Error: data/full_repos/permissive/415491487/design_src/main_bus.v:54: Cannot find file containing module: \'u24add_bus\'\n    u24add_bus a0(.clk(clk), .op_sel(), .bus(move_bus));\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/415491487/design_src,data/full_repos/permissive/415491487/u24add_bus\n             data/full_repos/permissive/415491487/design_src,data/full_repos/permissive/415491487/u24add_bus.v\n             data/full_repos/permissive/415491487/design_src,data/full_repos/permissive/415491487/u24add_bus.sv\n             u24add_bus\n             u24add_bus.v\n             u24add_bus.sv\n             obj_dir/u24add_bus\n             obj_dir/u24add_bus.v\n             obj_dir/u24add_bus.sv\n%Error: data/full_repos/permissive/415491487/design_src/main_bus.v:55: Cannot find file containing module: \'u24sub_bus\'\n    u24sub_bus s0(.clk(clk), .op_sel(), .bus(move_bus));\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/415491487/design_src/main_bus.v:56: Cannot find file containing module: \'cmp_bus\'\n    cmp_bus c(.clk(clk), .op_sel(), .bus(move_bus), .cmp_true(execute_conditional));\n    ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/415491487/design_src/main_bus.v:63: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                             : ... In instance proc_bus\n            enablefile <= 32\'h0;\n                       ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/415491487/design_src/main_bus.v:71: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'h0\' generates 32 bits.\n                                                                             : ... In instance proc_bus\n                    enablefile <= 32\'h0;  \n                               ^~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module proc_bus(
    input clk,
    input rst,
    
    output reg [23:0] iaddr,
    input [23:0] idata,
    
    output [23:0] dwaddr,
    output [23:0] dwdata,
    
    output [23:0] draddr,
    input [23:0] drdata
);    
    parameter pc = 31;
    parameter num_registers = 32;
    
    parameter fetch = 2'b00;
    parameter decode = 2'b01;
    parameter execute = 2'b10;
    
    parameter ireg = 1'b0;
    parameter iimm = 1'b1;
    
    parameter opcode = 23;
    parameter conditional = 22;
    parameter high_low_select = 21;
    
    reg [1:0] statecounter;
    


    
    reg [63:0] enablefile;
    
    reg cond;
    reg imm_load;
    reg hl;
    
    wire [23:0] move_bus;
    wire execute_conditional;
    
    u24add_bus a0(.clk(clk), .op_sel(), .bus(move_bus));
    u24sub_bus s0(.clk(clk), .op_sel(), .bus(move_bus));
    cmp_bus c(.clk(clk), .op_sel(), .bus(move_bus), .cmp_true(execute_conditional));
    
    always @(posedge clk) begin
        if (rst) begin
            statecounter <= fetch;


            enablefile <= 32'h0;
            
            cond <= 1'b0;
            imm_load <= 1'b0;
            hl <= 1'b0;
        end else begin
            case (statecounter)
                fetch: begin
                    enablefile <= 32'h0;


                    statecounter <= decode;
                end
                decode: begin
                    $display("got instr 0x%0h back, addr = 0x%0h.", idata, iaddr);
                    cond <= idata[conditional];
                    if (idata[18:12] >= num_registers) begin
                        enablefile <= enablefile | (1 << idata[18:12]);
                    end
                    case (idata[opcode])
                        ireg: begin
                            if (idata[11:5] >= num_registers) begin
                                enablefile <= enablefile | (1 << idata[11:5]);
                            end
                        end
                        iimm: begin
                            imm_load <= 1'b1;
                            hl <= idata[high_low_select];

                        end
                    endcase
                    statecounter <= execute;
                end
                execute: begin



                    statecounter <= fetch;
                end
                default: begin
                    $display("ERROR: invalid state counter %d.", statecounter);
                end
            endcase
        end
    end
endmodule
module proc_bus(
    input clk,
    input rst,
    
    output reg [23:0] iaddr,
    input [23:0] idata,
    
    output [23:0] dwaddr,
    output [23:0] dwdata,
    
    output [23:0] draddr,
    input [23:0] drdata
);
    
    parameter pc = 31;
    parameter num_registers = 32;
    
    parameter fetch = 2'b00;
    parameter decode = 2'b01;
    parameter execute = 2'b10;
    
    parameter ireg = 1'b0;
    parameter iimm = 1'b1;
    
    parameter opcode = 23;
    parameter conditional = 22;
    parameter high_low_select = 21;
    
    reg [1:0] statecounter;
    


    
    reg [63:0] enablefile;
    
    reg cond;
    reg imm_load;
    reg hl;
    
    wire [23:0] move_bus;
    wire execute_conditional;
    
    u24add_bus a0(.clk(clk), .op_sel(), .bus(move_bus));
    u24sub_bus s0(.clk(clk), .op_sel(), .bus(move_bus));
    cmp_bus c(.clk(clk), .op_sel(), .bus(move_bus), .cmp_true(execute_conditional));
    
    always @(posedge clk) begin
        if (rst) begin
            statecounter <= fetch;


            enablefile <= 32'h0;
            
            cond <= 1'b0;
            imm_load <= 1'b0;
            hl <= 1'b0;
        end else begin
            case (statecounter)
                fetch: begin
                    enablefile <= 32'h0;


                    statecounter <= decode;
                end
                decode: begin
                    $display("got instr 0x%0h back, addr = 0x%0h.", idata, iaddr);
                    cond <= idata[conditional];
                    if (idata[18:12] >= num_registers) begin
                        enablefile <= enablefile | (1 << idata[18:12]);
                    end
                    case (idata[opcode])
                        ireg: begin
                            if (idata[11:5] >= num_registers) begin
                                enablefile <= enablefile | (1 << idata[11:5]);
                            end
                        end
                        iimm: begin
                            imm_load <= 1'b1;
                            hl <= idata[high_low_select];

                        end
                    endcase
                    statecounter <= execute;
                end
                execute: begin



                    statecounter <= fetch;
                end
                default: begin
                    $display("ERROR: invalid state counter %d.", statecounter);
                end
            endcase
        end
    end
endmodule