data/full_repos/permissive/529457593/Sprint10/Register.v
data/verilator_xmls/ffc212a8-a7d7-46a8-84ef-80ceea4b977b.xml
module register (input [7:0] d_in, input clk , enable, output reg [7:0] d_out);

	always @ (posedge clk) begin
		if(enable == 1)
			d_out = d_in;
	end

endmodule
module register (input [7:0] d_in, input clk , enable, output reg [7:0] d_out);


	always @ (posedge clk) begin
		if(enable == 1)
			d_out = d_in;
	end

endmodule