data/full_repos/permissive/50693363/riffa_builder/src/fpga/riffa_axis_m.v
1: b'%Warning-WIDTH: data/full_repos/permissive/50693363/riffa_builder/src/fpga/riffa_axis_m.v:165: Operator ASSIGNDLY expects 129 bits on the Assign RHS, but Assign RHS\'s SEL generates 97 bits.\n                                                                                             : ... In instance riffa_axis_m\n                            buffer <= buffer[C_PCI_DATA_WIDTH: \n                                   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/50693363/riffa_builder/src/fpga/riffa_axis_m.v:145: Operator EQ expects 32 or 8 bits on the LHS, but LHS\'s VARREF \'buffer_status\' generates 5 bits.\n                                                                                             : ... In instance riffa_axis_m\n                        if (buffer_status == C_WIDTH_RATIO) \n                                          ^~\n%Warning-WIDTH: data/full_repos/permissive/50693363/riffa_builder/src/fpga/riffa_axis_m.v:209: Operator EQ expects 32 or 8 bits on the LHS, but LHS\'s VARREF \'buffer_status\' generates 5 bits.\n                                                                                             : ... In instance riffa_axis_m\n            else if (buffer_status == C_WIDTH_RATIO)\n                                   ^~\n%Error: Exiting due to 3 warning(s)\n'
module riffa_axis_m #(
    parameter C_AXIS_DATA_WIDTH = 32,
    parameter C_PCI_DATA_WIDTH = 128,
    parameter C_COUNTER = 0,
    parameter C_COUNTER_WIDTH = 32,
    parameter C_COUNTER_DIV = 0)
(


    input  M_AXIS_RSTN,
    input  M_AXIS_CLK,
    output reg M_AXIS_TVALID,
    output reg M_AXIS_TLAST,
    input  M_AXIS_TREADY,
    output [C_AXIS_DATA_WIDTH-1 : 0] M_AXIS_TDATA,

    output CHNL_RX_CLK,
    input  CHNL_RX,
    output reg  CHNL_RX_ACK,
    input  CHNL_RX_LAST,
    input  [31:0] CHNL_RX_LEN,
    input  [30:0] CHNL_RX_OFF,
    input  [C_PCI_DATA_WIDTH-1:0] CHNL_RX_DATA,
    input  CHNL_RX_DATA_VALID,
    output reg  CHNL_RX_DATA_REN,

    output reg [C_COUNTER_WIDTH-1: 0] START_TICKS,
    output reg [C_COUNTER_WIDTH-1: 0] END_TICKS,
    output reg [C_COUNTER_WIDTH-1: 0] DATA_BYTES
);

    wire clk, rstn;
    assign clk = M_AXIS_CLK;
    assign rstn = M_AXIS_RSTN;
    assign CHNL_RX_CLK = clk;
    
    localparam C_WIDTH_RATIO = (C_PCI_DATA_WIDTH / C_AXIS_DATA_WIDTH);
    localparam C_PCI_BYTE_WIDTH = (C_PCI_DATA_WIDTH / 8);
    localparam C_AXIS_BYTE_WIDTH = (C_AXIS_DATA_WIDTH / 8);

    reg [C_PCI_DATA_WIDTH:0] buffer;

    reg [4:0] buffer_status;
    
    localparam ST_IDLE          = 4'b0000;
    localparam ST_RX            = 4'b0001;
    localparam ST_RX_END        = 4'b0010;

    reg [3:0] stat;
    reg [33:0] byte_cnt; 
    reg chnl_rx_valid_r;
    reg chnl_rx_last_r;
    
    always @ (posedge clk)
    begin
        if (!rstn)
        begin
            stat <= ST_IDLE;
            buffer_status <= 'b0;
            buffer <= 'b0;
            byte_cnt <= 'b0;
            chnl_rx_last_r <= 'b0;
            CHNL_RX_ACK <= 'b0;
            M_AXIS_TLAST <= 1'b0;
            M_AXIS_TVALID <= 1'b0;
        end else begin
            case (stat)
            ST_IDLE : begin
                    if (CHNL_RX)
                    begin
                        buffer_status <= 5'b0;

                        byte_cnt <= {CHNL_RX_LEN, 2'b00}; 
                        chnl_rx_last_r <= CHNL_RX_LAST;
                        CHNL_RX_ACK <= 1'b1;
                        M_AXIS_TLAST <= 1'b0;
                        M_AXIS_TVALID <= 1'b0;
                        stat <= ST_RX;
                    end
                end
            ST_RX : begin
                    CHNL_RX_ACK <= 1'b0;
                    
                    if (buffer_status == 'b0)
                    begin
                        if (CHNL_RX_DATA_VALID)
                        begin

                            buffer <= {1'b0, CHNL_RX_DATA};
                            buffer_status <= 5'b1;
                            M_AXIS_TVALID <= 1'b1;
                            M_AXIS_TLAST <= (chnl_rx_last_r && 
                                (byte_cnt <= C_AXIS_BYTE_WIDTH));
                            if (byte_cnt <= C_AXIS_BYTE_WIDTH)
                                stat <= ST_RX_END;
                        end
                    end else if (M_AXIS_TREADY)
                    begin
                        if (buffer_status == C_WIDTH_RATIO) 

                        begin
                            if (CHNL_RX_DATA_VALID)
                            begin

                                buffer <= {1'b0, CHNL_RX_DATA};
                                buffer_status <= 5'b1;
                                M_AXIS_TVALID <= 1'b1;
                                M_AXIS_TLAST <= (chnl_rx_last_r && 
                                    (byte_cnt <= C_AXIS_BYTE_WIDTH*2));
                                if (byte_cnt <= C_AXIS_BYTE_WIDTH*2)
                                    stat <= ST_RX_END;
                            end else begin

                                buffer_status <= 5'b0;
                                M_AXIS_TVALID <= 1'b0;
                            end
                        end else begin

                            buffer <= buffer[C_PCI_DATA_WIDTH: 
                                C_AXIS_DATA_WIDTH];
                            buffer_status <= buffer_status + 1;
                            M_AXIS_TVALID <= 1'b1;
                            M_AXIS_TLAST <= (chnl_rx_last_r && 
                                (byte_cnt <= C_AXIS_BYTE_WIDTH*2));
                            if (byte_cnt <= C_AXIS_BYTE_WIDTH*2)
                                stat <= ST_RX_END;
                        end
                        
                        byte_cnt <= byte_cnt - C_AXIS_BYTE_WIDTH;
                        
                        
                    end
                 end
             ST_RX_END : begin
             
                        CHNL_RX_ACK <= 1'b0;
                        
                        if (M_AXIS_TREADY)
                        begin
                            M_AXIS_TLAST <= 1'b0;
                            M_AXIS_TVALID <= 1'b0;
                        end
                        

                        if (!(CHNL_RX || M_AXIS_TVALID)) 
                            stat <= ST_IDLE;                        
                end
             default : begin
                    stat <= ST_IDLE;
                end
            endcase
        end
    end
    
    always @ (posedge clk) chnl_rx_valid_r <= CHNL_RX_DATA_VALID;
    
    always @ (*)
    begin
        if (stat == ST_RX)
        begin
            if (buffer_status == 0)
                CHNL_RX_DATA_REN <= 1'b1;
            else if (buffer_status == C_WIDTH_RATIO)
                CHNL_RX_DATA_REN <= M_AXIS_TREADY;
            else
                CHNL_RX_DATA_REN <= 1'b0;
        end else if (stat == ST_RX_END)
        begin

            CHNL_RX_DATA_REN <= chnl_rx_valid_r;  
        end else 
        begin
            CHNL_RX_DATA_REN <= 1'b0;
        end
    end
    
    assign M_AXIS_TDATA = buffer[C_AXIS_DATA_WIDTH - 1: 0];
    
    reg [C_COUNTER_DIV + C_COUNTER_WIDTH - 1: 0] timer;
    reg start_tick_rdy, end_tick_rdy;
    reg start_tick_trig, end_tick_trig;
    reg data_cnt_pulse;
    

    always @ (posedge clk)
    begin
        if (!rstn)
        begin
            START_TICKS <= 'b0;
            END_TICKS <= 'b0;
            DATA_BYTES <= 'b0;
            timer <= 'b0;
            start_tick_rdy <= 1'b0;
            start_tick_trig <= 1'b0;
            end_tick_rdy <= 1'b0;
            end_tick_trig <= 1'b0;
            data_cnt_pulse <= 1'b0;
        end else begin
        
            if (C_COUNTER)
            begin
                if (~timer != 0)
                    timer <= timer + 1'b1;
                
                start_tick_rdy <= (stat == ST_RX);
                start_tick_trig <= (stat == ST_RX) && !start_tick_rdy;
                if (start_tick_trig)
                    START_TICKS <= timer[C_COUNTER_DIV +: C_COUNTER_WIDTH];
                
                end_tick_rdy <= (stat == ST_RX_END);
                end_tick_trig <= (stat == ST_RX_END) && !end_tick_rdy;
                if (end_tick_trig)
                    END_TICKS <= timer[C_COUNTER_DIV +: C_COUNTER_WIDTH];
                    
                data_cnt_pulse <= (stat == ST_RX) && CHNL_RX_DATA_REN && CHNL_RX_DATA_VALID;
                
                if (data_cnt_pulse)
                    DATA_BYTES <= DATA_BYTES + C_PCI_BYTE_WIDTH;
            end else begin
                START_TICKS <= 'b0;
                END_TICKS <= 'b0;
                DATA_BYTES <= 'b0;
                timer <= 'b0;
            end
        end
    end
   
    

endmodule
module riffa_axis_m #(
    parameter C_AXIS_DATA_WIDTH = 32,
    parameter C_PCI_DATA_WIDTH = 128,
    parameter C_COUNTER = 0,
    parameter C_COUNTER_WIDTH = 32,
    parameter C_COUNTER_DIV = 0)
(


    input  M_AXIS_RSTN,
    input  M_AXIS_CLK,
    output reg M_AXIS_TVALID,
    output reg M_AXIS_TLAST,
    input  M_AXIS_TREADY,
    output [C_AXIS_DATA_WIDTH-1 : 0] M_AXIS_TDATA,

    output CHNL_RX_CLK,
    input  CHNL_RX,
    output reg  CHNL_RX_ACK,
    input  CHNL_RX_LAST,
    input  [31:0] CHNL_RX_LEN,
    input  [30:0] CHNL_RX_OFF,
    input  [C_PCI_DATA_WIDTH-1:0] CHNL_RX_DATA,
    input  CHNL_RX_DATA_VALID,
    output reg  CHNL_RX_DATA_REN,

    output reg [C_COUNTER_WIDTH-1: 0] START_TICKS,
    output reg [C_COUNTER_WIDTH-1: 0] END_TICKS,
    output reg [C_COUNTER_WIDTH-1: 0] DATA_BYTES
);


    wire clk, rstn;
    assign clk = M_AXIS_CLK;
    assign rstn = M_AXIS_RSTN;
    assign CHNL_RX_CLK = clk;
    
    localparam C_WIDTH_RATIO = (C_PCI_DATA_WIDTH / C_AXIS_DATA_WIDTH);
    localparam C_PCI_BYTE_WIDTH = (C_PCI_DATA_WIDTH / 8);
    localparam C_AXIS_BYTE_WIDTH = (C_AXIS_DATA_WIDTH / 8);

    reg [C_PCI_DATA_WIDTH:0] buffer;

    reg [4:0] buffer_status;
    
    localparam ST_IDLE          = 4'b0000;
    localparam ST_RX            = 4'b0001;
    localparam ST_RX_END        = 4'b0010;

    reg [3:0] stat;
    reg [33:0] byte_cnt; 
    reg chnl_rx_valid_r;
    reg chnl_rx_last_r;
    
    always @ (posedge clk)
    begin
        if (!rstn)
        begin
            stat <= ST_IDLE;
            buffer_status <= 'b0;
            buffer <= 'b0;
            byte_cnt <= 'b0;
            chnl_rx_last_r <= 'b0;
            CHNL_RX_ACK <= 'b0;
            M_AXIS_TLAST <= 1'b0;
            M_AXIS_TVALID <= 1'b0;
        end else begin
            case (stat)
            ST_IDLE : begin
                    if (CHNL_RX)
                    begin
                        buffer_status <= 5'b0;

                        byte_cnt <= {CHNL_RX_LEN, 2'b00}; 
                        chnl_rx_last_r <= CHNL_RX_LAST;
                        CHNL_RX_ACK <= 1'b1;
                        M_AXIS_TLAST <= 1'b0;
                        M_AXIS_TVALID <= 1'b0;
                        stat <= ST_RX;
                    end
                end
            ST_RX : begin
                    CHNL_RX_ACK <= 1'b0;
                    
                    if (buffer_status == 'b0)
                    begin
                        if (CHNL_RX_DATA_VALID)
                        begin

                            buffer <= {1'b0, CHNL_RX_DATA};
                            buffer_status <= 5'b1;
                            M_AXIS_TVALID <= 1'b1;
                            M_AXIS_TLAST <= (chnl_rx_last_r && 
                                (byte_cnt <= C_AXIS_BYTE_WIDTH));
                            if (byte_cnt <= C_AXIS_BYTE_WIDTH)
                                stat <= ST_RX_END;
                        end
                    end else if (M_AXIS_TREADY)
                    begin
                        if (buffer_status == C_WIDTH_RATIO) 

                        begin
                            if (CHNL_RX_DATA_VALID)
                            begin

                                buffer <= {1'b0, CHNL_RX_DATA};
                                buffer_status <= 5'b1;
                                M_AXIS_TVALID <= 1'b1;
                                M_AXIS_TLAST <= (chnl_rx_last_r && 
                                    (byte_cnt <= C_AXIS_BYTE_WIDTH*2));
                                if (byte_cnt <= C_AXIS_BYTE_WIDTH*2)
                                    stat <= ST_RX_END;
                            end else begin

                                buffer_status <= 5'b0;
                                M_AXIS_TVALID <= 1'b0;
                            end
                        end else begin

                            buffer <= buffer[C_PCI_DATA_WIDTH: 
                                C_AXIS_DATA_WIDTH];
                            buffer_status <= buffer_status + 1;
                            M_AXIS_TVALID <= 1'b1;
                            M_AXIS_TLAST <= (chnl_rx_last_r && 
                                (byte_cnt <= C_AXIS_BYTE_WIDTH*2));
                            if (byte_cnt <= C_AXIS_BYTE_WIDTH*2)
                                stat <= ST_RX_END;
                        end
                        
                        byte_cnt <= byte_cnt - C_AXIS_BYTE_WIDTH;
                        
                        
                    end
                 end
             ST_RX_END : begin
             
                        CHNL_RX_ACK <= 1'b0;
                        
                        if (M_AXIS_TREADY)
                        begin
                            M_AXIS_TLAST <= 1'b0;
                            M_AXIS_TVALID <= 1'b0;
                        end
                        

                        if (!(CHNL_RX || M_AXIS_TVALID)) 
                            stat <= ST_IDLE;                        
                end
             default : begin
                    stat <= ST_IDLE;
                end
            endcase
        end
    end
    
    always @ (posedge clk) chnl_rx_valid_r <= CHNL_RX_DATA_VALID;
    
    always @ (*)
    begin
        if (stat == ST_RX)
        begin
            if (buffer_status == 0)
                CHNL_RX_DATA_REN <= 1'b1;
            else if (buffer_status == C_WIDTH_RATIO)
                CHNL_RX_DATA_REN <= M_AXIS_TREADY;
            else
                CHNL_RX_DATA_REN <= 1'b0;
        end else if (stat == ST_RX_END)
        begin

            CHNL_RX_DATA_REN <= chnl_rx_valid_r;  
        end else 
        begin
            CHNL_RX_DATA_REN <= 1'b0;
        end
    end
    
    assign M_AXIS_TDATA = buffer[C_AXIS_DATA_WIDTH - 1: 0];
    
    reg [C_COUNTER_DIV + C_COUNTER_WIDTH - 1: 0] timer;
    reg start_tick_rdy, end_tick_rdy;
    reg start_tick_trig, end_tick_trig;
    reg data_cnt_pulse;
    

    always @ (posedge clk)
    begin
        if (!rstn)
        begin
            START_TICKS <= 'b0;
            END_TICKS <= 'b0;
            DATA_BYTES <= 'b0;
            timer <= 'b0;
            start_tick_rdy <= 1'b0;
            start_tick_trig <= 1'b0;
            end_tick_rdy <= 1'b0;
            end_tick_trig <= 1'b0;
            data_cnt_pulse <= 1'b0;
        end else begin
        
            if (C_COUNTER)
            begin
                if (~timer != 0)
                    timer <= timer + 1'b1;
                
                start_tick_rdy <= (stat == ST_RX);
                start_tick_trig <= (stat == ST_RX) && !start_tick_rdy;
                if (start_tick_trig)
                    START_TICKS <= timer[C_COUNTER_DIV +: C_COUNTER_WIDTH];
                
                end_tick_rdy <= (stat == ST_RX_END);
                end_tick_trig <= (stat == ST_RX_END) && !end_tick_rdy;
                if (end_tick_trig)
                    END_TICKS <= timer[C_COUNTER_DIV +: C_COUNTER_WIDTH];
                    
                data_cnt_pulse <= (stat == ST_RX) && CHNL_RX_DATA_REN && CHNL_RX_DATA_VALID;
                
                if (data_cnt_pulse)
                    DATA_BYTES <= DATA_BYTES + C_PCI_BYTE_WIDTH;
            end else begin
                START_TICKS <= 'b0;
                END_TICKS <= 'b0;
                DATA_BYTES <= 'b0;
                timer <= 'b0;
            end
        end
    end
   
    

endmodule