data/full_repos/permissive/498662723/Circuits/Sequential Logic/Finite State Machines/fsm3 (async reset).v
1: b'%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/498662723/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/498662723/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/498662723/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines,data/full_repos/permissive/498662723\n%Error: Cannot find file containing module: data/full_repos/permissive/498662723/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/fsm3\n%Error: Cannot find file containing module: (async\n%Error: Cannot find file containing module: reset).v\n%Error: Exiting due to 7 error(s)\n'
module top_module(
    input clk,
    input in,
    input areset,
    output out);


    parameter A=2'b00, B =2'b01, C = 2'b10, D = 2'b11;
    reg [1:0]state, next_state;
	
    always @ (*)
        begin     
            case (state)
                A: next_state = in ? B : A;
                B: next_state = in ? B : C;
                C: next_state = in ? D : A;
                D: next_state = in ? B : C;
            endcase
        end
    
    always @ (posedge clk, posedge areset)
        begin
            if (areset)
                state <= A;
            else
                state <= next_state;
        end


    assign out = (state == D) ? 1'b1:1'b0;

endmodule
module top_module(
    input clk,
    input in,
    input areset,
    output out);



    parameter A=2'b00, B =2'b01, C = 2'b10, D = 2'b11;
    reg [1:0]state, next_state;
	
    always @ (*)
        begin     
            case (state)
                A: next_state = in ? B : A;
                B: next_state = in ? B : C;
                C: next_state = in ? D : A;
                D: next_state = in ? B : C;
            endcase
        end
    
    always @ (posedge clk, posedge areset)
        begin
            if (areset)
                state <= A;
            else
                state <= next_state;
        end


    assign out = (state == D) ? 1'b1:1'b0;

endmodule