data/full_repos/permissive/46804359/processor_test_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/46804359/processor_test_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk=~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/46804359/processor_test_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #50\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/46804359/processor_test_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #50\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/46804359/processor_test_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #50\n    ^\n%Error: data/full_repos/permissive/46804359/processor_test_tb.v:11: Cannot find file containing module: \'processor_test\'\nprocessor_test DUT(clk, rst, en);\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/46804359,data/full_repos/permissive/46804359/processor_test\n             data/full_repos/permissive/46804359,data/full_repos/permissive/46804359/processor_test.v\n             data/full_repos/permissive/46804359,data/full_repos/permissive/46804359/processor_test.sv\n             processor_test\n             processor_test.v\n             processor_test.sv\n             obj_dir/processor_test\n             obj_dir/processor_test.v\n             obj_dir/processor_test.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module processor_test_tb;

reg clk;
reg rst;
reg en;
reg [31:0] in;

wire [31:0] out;

processor_test DUT(clk, rst, en);


initial begin
    clk=0;
    rst=0;
    en=0;
end


always #5 clk=~clk;


initial begin





	 #50
    en=1;
	
    #50
	rst=1;

    #50
    rst=0;


end

endmodule
module processor_test_tb;


reg clk;
reg rst;
reg en;
reg [31:0] in;

wire [31:0] out;

processor_test DUT(clk, rst, en);


initial begin
    clk=0;
    rst=0;
    en=0;
end


always #5 clk=~clk;


initial begin





	 #50
    en=1;
	
    #50
	rst=1;

    #50
    rst=0;


end

endmodule