data/full_repos/permissive/458113953/LAB 5&6_2019A8PS0621H/Car_FSM.v
1: b'%Error: Cannot find file containing module: 5&6_2019A8PS0621H,data/full_repos/permissive/458113953\n        ... Looked in:\n             data/full_repos/permissive/458113953/LAB/5&6_2019A8PS0621H,data/full_repos/permissive/458113953\n             data/full_repos/permissive/458113953/LAB/5&6_2019A8PS0621H,data/full_repos/permissive/458113953.v\n             data/full_repos/permissive/458113953/LAB/5&6_2019A8PS0621H,data/full_repos/permissive/458113953.sv\n             5&6_2019A8PS0621H,data/full_repos/permissive/458113953\n             5&6_2019A8PS0621H,data/full_repos/permissive/458113953.v\n             5&6_2019A8PS0621H,data/full_repos/permissive/458113953.sv\n             obj_dir/5&6_2019A8PS0621H,data/full_repos/permissive/458113953\n             obj_dir/5&6_2019A8PS0621H,data/full_repos/permissive/458113953.v\n             obj_dir/5&6_2019A8PS0621H,data/full_repos/permissive/458113953.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/458113953/LAB\n%Error: Cannot find file containing module: 5&6_2019A8PS0621H/Car_FSM.v\n%Error: Exiting due to 3 error(s)\n'
module Car_FSM(
    input left,right,
    input Clk,
    input Reset,
    output reg [5:0] out
    );

    reg[2:0] next_state,present_state;


   parameter S0=3'b000,
             S1=3'b001,
             S2=3'b010,
             S3=3'b011,
             S4=3'b100,
             S5=3'b101,
             S6=3'b110;

    reg [25:0] Clk_Div;
           always@(posedge Clk,posedge Reset)
           begin
           if(Reset==1)
           Clk_Div=0;
           else
           Clk_Div=Clk_Div+1;
           end
    always@(posedge Clk_Div[25], posedge Reset)
    begin
    if(Reset==1)
    present_state=3'b000;
    else
    present_state=next_state;
    end


    always@(present_state[2:0],left,right)
    begin
    case(present_state)
    S0:begin
       if(left==0 && right==0)
       next_state=S0;
       else if(left==1 && right!=1)
       next_state=S1;
       else if(right==1 && left!=1)
       next_state=S4;
       else
       next_state=S0;
       end
    S1:next_state=S2;
    S2:next_state=S3;
    S3:next_state=S0;
    S4:next_state=S5;
    S5:next_state=S6;
    S6:next_state=S0;
   default: next_state=S0;
    endcase
    end

    always@(present_state[2:0],left,right)
    begin
    case(present_state[2:0])
    S0:begin
       if(left==0 && right==0)
       out=6'b000000;
       else if(left==1 && right!=1)
       out=6'b001000;
       else if(right==1 && left!=1)
       out=6'b000100;
       else
       out=6'b000000;
       end
     S1:out=6'b011000;
     S2:out=6'b111000;
     S3:out=6'b000000;
     S4:out=6'b000110;
     S5:out=6'b000111;
     S6:out=6'b000000;
     default: out=6'b000000;
    endcase
    end
endmodule
module Car_FSM(
    input left,right,
    input Clk,
    input Reset,
    output reg [5:0] out
    );


    reg[2:0] next_state,present_state;


   parameter S0=3'b000,
             S1=3'b001,
             S2=3'b010,
             S3=3'b011,
             S4=3'b100,
             S5=3'b101,
             S6=3'b110;

    reg [25:0] Clk_Div;
           always@(posedge Clk,posedge Reset)
           begin
           if(Reset==1)
           Clk_Div=0;
           else
           Clk_Div=Clk_Div+1;
           end
    always@(posedge Clk_Div[25], posedge Reset)
    begin
    if(Reset==1)
    present_state=3'b000;
    else
    present_state=next_state;
    end


    always@(present_state[2:0],left,right)
    begin
    case(present_state)
    S0:begin
       if(left==0 && right==0)
       next_state=S0;
       else if(left==1 && right!=1)
       next_state=S1;
       else if(right==1 && left!=1)
       next_state=S4;
       else
       next_state=S0;
       end
    S1:next_state=S2;
    S2:next_state=S3;
    S3:next_state=S0;
    S4:next_state=S5;
    S5:next_state=S6;
    S6:next_state=S0;
   default: next_state=S0;
    endcase
    end

    always@(present_state[2:0],left,right)
    begin
    case(present_state[2:0])
    S0:begin
       if(left==0 && right==0)
       out=6'b000000;
       else if(left==1 && right!=1)
       out=6'b001000;
       else if(right==1 && left!=1)
       out=6'b000100;
       else
       out=6'b000000;
       end
     S1:out=6'b011000;
     S2:out=6'b111000;
     S3:out=6'b000000;
     S4:out=6'b000110;
     S5:out=6'b000111;
     S6:out=6'b000000;
     default: out=6'b000000;
    endcase
    end
endmodule