data/full_repos/permissive/522149450/01.hdmi/src/hdmi_top.v
1: b"%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi_top.v:27: Cannot find file containing module: 'Gowin_rPLL'\nGowin_rPLL u_pll (\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/522149450/01.hdmi/src,data/full_repos/permissive/522149450/Gowin_rPLL\n             data/full_repos/permissive/522149450/01.hdmi/src,data/full_repos/permissive/522149450/Gowin_rPLL.v\n             data/full_repos/permissive/522149450/01.hdmi/src,data/full_repos/permissive/522149450/Gowin_rPLL.sv\n             Gowin_rPLL\n             Gowin_rPLL.v\n             Gowin_rPLL.sv\n             obj_dir/Gowin_rPLL\n             obj_dir/Gowin_rPLL.v\n             obj_dir/Gowin_rPLL.sv\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi_top.v:33: Cannot find file containing module: 'Gowin_CLKDIV'\nGowin_CLKDIV u_div_5 (\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/522149450/01.hdmi/src/hdmi_top.v:42: Cannot find file containing module: 'svo_hdmi_top'\nsvo_hdmi_top u_hdmi (\n^~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module hdmi_top (
  input clk,
  input sys_resetn,


  output       tmds_clk_n,
  output       tmds_clk_p,
  output [2:0] tmds_d_n,
  output [2:0] tmds_d_p,


  input  ser_rx,
  output ser_tx
);

wire clk_p;
wire clk_p5;
wire pll_lock;

wire uart_valid;
wire uart_ready;
wire [31:0] uart_addr;
wire [31:0] uart_wdata;
wire [3:0] uart_wstrb;
wire [31:0] uart_rdata;

Gowin_rPLL u_pll (
  .clkin(clk),
  .clkout(clk_p5),
  .lock(pll_lock)
);

Gowin_CLKDIV u_div_5 (
    .clkout(clk_p),
    .hclkin(clk_p5),
    .resetn(pll_lock)
);

wire svo_term_valid;
assign svo_term_valid = 1'b0;

svo_hdmi_top u_hdmi (
	.clk(clk_p),
	.resetn(sys_resetn),


	.clk_pixel(clk_p),
	.clk_5x_pixel(clk_p5),
	.locked(pll_lock),

	.term_in_tvalid( svo_term_valid ),
	.term_out_tready(),
	.term_in_tdata(),


	.tmds_clk_n(tmds_clk_n),
	.tmds_clk_p(tmds_clk_p),
	.tmds_d_n(tmds_d_n),
	.tmds_d_p(tmds_d_p)
);

endmodule
module hdmi_top (
  input clk,
  input sys_resetn,


  output       tmds_clk_n,
  output       tmds_clk_p,
  output [2:0] tmds_d_n,
  output [2:0] tmds_d_p,


  input  ser_rx,
  output ser_tx
);


wire clk_p;
wire clk_p5;
wire pll_lock;

wire uart_valid;
wire uart_ready;
wire [31:0] uart_addr;
wire [31:0] uart_wdata;
wire [3:0] uart_wstrb;
wire [31:0] uart_rdata;

Gowin_rPLL u_pll (
  .clkin(clk),
  .clkout(clk_p5),
  .lock(pll_lock)
);

Gowin_CLKDIV u_div_5 (
    .clkout(clk_p),
    .hclkin(clk_p5),
    .resetn(pll_lock)
);

wire svo_term_valid;
assign svo_term_valid = 1'b0;

svo_hdmi_top u_hdmi (
	.clk(clk_p),
	.resetn(sys_resetn),


	.clk_pixel(clk_p),
	.clk_5x_pixel(clk_p5),
	.locked(pll_lock),

	.term_in_tvalid( svo_term_valid ),
	.term_out_tready(),
	.term_in_tdata(),


	.tmds_clk_n(tmds_clk_n),
	.tmds_clk_p(tmds_clk_p),
	.tmds_d_n(tmds_d_n),
	.tmds_d_p(tmds_d_p)
);

endmodule