data/full_repos/permissive/439731184/udp.v
1: b'%Error: data/full_repos/permissive/439731184/udp.v:31: Unsupported or unknown PLI call: $monitor\n    $monitor("%b\\t%b\\t%b", in0, in1, out);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/439731184/udp.v:35: Unsupported: Ignoring delay on this delayed statement.\n    #1 in0 = 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/439731184/udp.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #1 in0 = 0; in1 = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/udp.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #1 in0 = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/439731184/udp.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #1 $finish;\n    ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module udp_tb(); 

reg in0, in1, in2, in3, in4, in5, in6, in7, in8, in9, in10, in11;
wire out;

test T (out, in0, in1, in2, in3, in4, in5, in6, in7, in8, in9, in10, in11);

initial begin
    $display("in0\tin1\tout");
    $monitor("%b\t%b\t%b", in0, in1, out);
    in0 = 0;
    in1 = 0;
    in11 = 0;
    #1 in0 = 1;
    #1 in0 = 0; in1 = 1;
    #1 in0 = 1;
    #1 $finish;
end

endmodule
module udp_tb();
 

reg in0, in1, in2, in3, in4, in5, in6, in7, in8, in9, in10, in11;
wire out;

test T (out, in0, in1, in2, in3, in4, in5, in6, in7, in8, in9, in10, in11);

initial begin
    $display("in0\tin1\tout");
    $monitor("%b\t%b\t%b", in0, in1, out);
    in0 = 0;
    in1 = 0;
    in11 = 0;
    #1 in0 = 1;
    #1 in0 = 0; in1 = 1;
    #1 in0 = 1;
    #1 $finish;
end

endmodule