data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Latches and Flip-Flops/Edgedetect/top_module_tb.v
1: b'%Error: Cannot find file containing module: Logic/Latches\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Latches\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Latches.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Latches.sv\n             Logic/Latches\n             Logic/Latches.v\n             Logic/Latches.sv\n             obj_dir/Logic/Latches\n             obj_dir/Logic/Latches.v\n             obj_dir/Logic/Latches.sv\n%Error: Cannot find file containing module: and\n%Error: Cannot find file containing module: Flip-Flops/Edgedetect,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Flip-Flops/Edgedetect/top_module_tb.v\n%Error: Exiting due to 5 error(s)\n'
module top_module_tb ();
  wire [7:0] pedge;

  reg clk = 1'd1;
  reg [7:0] in = 1'd0;

  localparam ITERATIONS = 300;

  always begin
    #1 clk = clk + 1;
  end

  always begin
    #2 in = in + 1;
  end

  top_module uut (
      .clk(clk),
      .in(in),
      .pedge(pedge)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule
module top_module_tb ();

  wire [7:0] pedge;

  reg clk = 1'd1;
  reg [7:0] in = 1'd0;

  localparam ITERATIONS = 300;

  always begin
    #1 clk = clk + 1;
  end

  always begin
    #2 in = in + 1;
  end

  top_module uut (
      .clk(clk),
      .in(in),
      .pedge(pedge)
  );

  initial begin
    $dumpfile("top_module_tb.vcd");
    $dumpvars(0, top_module_tb);

    #(ITERATIONS) $display("Done simulating.");
    $finish;
  end

endmodule