data/full_repos/permissive/42149584/Lab4-Part2-RAMwithHyperTerminalDisplay/BaudRateGenerator.v
1: b'%Warning-WIDTH: data/full_repos/permissive/42149584/Lab4-Part2-RAMwithHyperTerminalDisplay/BaudRateGenerator.v:18: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                 : ... In instance BaudRateGenerator\n      if(Reset==1) begin baud_count <= 1\'b0;\n                                    ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/42149584/Lab4-Part2-RAMwithHyperTerminalDisplay/BaudRateGenerator.v:24: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                 : ... In instance BaudRateGenerator\n             baud_count <= 1\'b0;\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/42149584/Lab4-Part2-RAMwithHyperTerminalDisplay/BaudRateGenerator.v:22: Operator EQ expects 32 or 30 bits on the LHS, but LHS\'s VARREF \'baud_count\' generates 16 bits.\n                                                                                                                 : ... In instance BaudRateGenerator\n  else if (baud_count == ClockFrequency/(BaudRate*16)) \n                      ^~\n%Error: Exiting due to 3 warning(s)\n'
module BaudRateGenerator (uartClock, Reset, clock, BaudRate, ClockFrequency);
input Reset, clock;
input [19:0] BaudRate;
input [29:0] ClockFrequency;

output reg  uartClock; 
reg [15:0] 	baud_count;

 always @(posedge clock)
      if(Reset==1) begin baud_count <= 1'b0;
      	     	uartClock <= 1'b1;
					end

		else if (baud_count == ClockFrequency/(BaudRate*16)) 
		begin
           		baud_count <= 1'b0;
      	     	uartClock <= 1'b1;
		end
       else
		begin
           		baud_count <= baud_count + 1'b1;
           		uartClock <= 1'b0;
      	end
endmodule
module BaudRateGenerator (uartClock, Reset, clock, BaudRate, ClockFrequency);

input Reset, clock;
input [19:0] BaudRate;
input [29:0] ClockFrequency;

output reg  uartClock; 
reg [15:0] 	baud_count;

 always @(posedge clock)
      if(Reset==1) begin baud_count <= 1'b0;
      	     	uartClock <= 1'b1;
					end

		else if (baud_count == ClockFrequency/(BaudRate*16)) 
		begin
           		baud_count <= 1'b0;
      	     	uartClock <= 1'b1;
		end
       else
		begin
           		baud_count <= baud_count + 1'b1;
           		uartClock <= 1'b0;
      	end
endmodule