data/full_repos/permissive/529706848/verilog/tb_direction.v
1: b'%Error: data/full_repos/permissive/529706848/verilog/tb_direction.v:17: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/529706848/verilog/tb_direction.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/529706848/verilog/tb_direction.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/529706848/verilog/tb_direction.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/529706848/verilog/tb_direction.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/529706848/verilog/tb_direction.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/529706848/verilog/tb_direction.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/529706848/verilog/tb_direction.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/529706848/verilog/tb_direction.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/529706848/verilog/tb_direction.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/529706848/verilog/tb_direction.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: Exiting due to 1 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_direction();

reg [7:0] state;
reg [2:0] sym;
wire direction;

direction_PROJECT_ID direction_block(
    .state(state),
    .s2(sym[2]),
    .s1(sym[1]),
    .s0(sym[0]),
    .direction(direction)
);

integer i;
initial begin
    $dumpvars;
    for (i = 0; i < 8; i = i + 1) begin
        state = 1 << i;
        $display("==== state 0x%x %c ====", state, "A" + $clog2(state));
        sym = 3'b000;
        #10;
        $display("sym %b -> direction %b", sym, direction);
        #10;

        sym = 3'b001;
        #10;
        $display("sym %b -> direction %b", sym, direction);
        #10;

        sym = 3'b010;
        #10;
        $display("sym %b -> direction %b", sym, direction);
        #10;

        sym = 3'b100;
        #10;
        $display("sym %b -> direction %b", sym, direction);
        #10;

        sym = 3'b101;
        #10;
        $display("sym %b -> direction %b", sym, direction);
        #10;
    end
end

endmodule
module tb_direction();


reg [7:0] state;
reg [2:0] sym;
wire direction;

direction_PROJECT_ID direction_block(
    .state(state),
    .s2(sym[2]),
    .s1(sym[1]),
    .s0(sym[0]),
    .direction(direction)
);

integer i;
initial begin
    $dumpvars;
    for (i = 0; i < 8; i = i + 1) begin
        state = 1 << i;
        $display("==== state 0x%x %c ====", state, "A" + $clog2(state));
        sym = 3'b000;
        #10;
        $display("sym %b -> direction %b", sym, direction);
        #10;

        sym = 3'b001;
        #10;
        $display("sym %b -> direction %b", sym, direction);
        #10;

        sym = 3'b010;
        #10;
        $display("sym %b -> direction %b", sym, direction);
        #10;

        sym = 3'b100;
        #10;
        $display("sym %b -> direction %b", sym, direction);
        #10;

        sym = 3'b101;
        #10;
        $display("sym %b -> direction %b", sym, direction);
        #10;
    end
end

endmodule