data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_rxframing.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_rxframing.v:139: Cannot find file containing module: 'fflopxe'\nfflopxe #(DAT_DW*1) ff1erxdat  (rxclk, rst_, eval, edat, edat1);\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core,data/full_repos/permissive/530013823/fflopxe\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core,data/full_repos/permissive/530013823/fflopxe.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core,data/full_repos/permissive/530013823/fflopxe.sv\n             fflopxe\n             fflopxe.v\n             fflopxe.sv\n             obj_dir/fflopxe\n             obj_dir/fflopxe.v\n             obj_dir/fflopxe.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_rxframing.v:140: Cannot find file containing module: 'fflopxe'\nfflopxe #(1*1)      ff1sfd1    (rxclk, rst_, eval, esfd, esfd1);\n^~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_rxframing.v:218: Cannot find file containing module: 'ippcrc_crc32_8b'\nippcrc_crc32_8b icrc32_8b\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_rxframing.v:260: Cannot find file containing module: 'fflopx'\nfflopx #(DAT_DW*1) ffodat  (rxclk, rst_, edat1, odat);\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_rxframing.v:261: Cannot find file containing module: 'fflopx'\nfflopx #(1)        ffosop  (rxclk, rst_, esop, osop);\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_rxframing.v:262: Cannot find file containing module: 'fflopx'\nfflopx #(1)        ffoeop  (rxclk, rst_, eeof, oeop);\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_rxframing.v:263: Cannot find file containing module: 'fflopx'\nfflopx #(1)        ffoval  (rxclk, rst_, dval, oval);\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_rxframing.v:264: Cannot find file containing module: 'fflopx'\nfflopx #(1)        ffistt  (rxclk, rst_, gval, oistt);\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_rxframing.v:265: Cannot find file containing module: 'fflopx'\nfflopx #(DAT_EW*1) ffoerr  (rxclk, rst_, eerr, oerr);\n^~~~~~\n%Error: Exiting due to 9 error(s)\n"
module ipsmacge_rxframing
    (
     rst_,
     rxclk,

     igval,
     igdat,
     igdv,
     iger,

     odat, 
     osop,  
     oeop,  
     oval,  
     oerr,

     oistt,

     up_rxen,
     up_act,
     up_thipg,
     up_rxnumprm
     );



parameter DAT_DW = 8,
          DAT_EW = 4;

parameter PRM_CW = 5;

parameter DAT_PRM = 8'h55,
          DAT_SFD = 8'hD5;

parameter STT_DW = 2;
parameter STT_IDLE = 2'b00,
          STT_IPRM = 2'b01,
          STT_IPAY = 2'b10;

parameter FCS32_VAL = 32'hc704dd7b;

parameter MRESERVE = 2'b11,
          M1000    = 2'b10,
          M100     = 2'b01,
          M10      = 2'b00;












input               rst_;
input               rxclk;


input  [DAT_DW-1:0] igdat;
input               igdv;
input               iger;
input               igval;

output [DAT_DW-1:0] odat;
output              osop;
output              oeop;
output [DAT_EW-1:0] oerr;
output              oval;

output              oistt;

input               up_rxen;
input               up_act;
input [3:0]         up_thipg;
input [3:0]         up_rxnumprm;



wire [31:0]          crc_dat;
reg  [31:0]          fcs_dat;
reg [PRM_CW-1:0]     prmc;

wire                 rxdv;
wire                 rxer;
wire [DAT_DW-1:0]    edat;
wire [DAT_DW-1:0]    edat1;
reg [STT_DW-1:0]     statem;

wire                 eval;
wire                 esof;
wire                 esop;
wire                 eeof;
wire                 esfd;
wire                 esfd1;
wire                 dval;
wire                 pval;
wire                 gval;

wire                 sfde;
wire                 prme;
wire [DAT_EW-1:0]    eerr;
wire                 fcs_err;
reg                  rcv_err;
reg                  prm_err;
reg                  ipacketok;

wire [DAT_DW-1:0]    odat;
wire                 oval;
wire                 osop;
wire                 oeop;
wire                 oistt;
wire [DAT_EW-1:0]    oerr;
reg                  gap_err;





assign             edat = up_rxen ? igdat : 8'h00;
assign             rxdv = up_rxen ? igdv  : 1'b0;
assign             rxer = up_rxen ? iger  : 1'b0;
assign             eval = igval;

fflopxe #(DAT_DW*1) ff1erxdat  (rxclk, rst_, eval, edat, edat1);
fflopxe #(1*1)      ff1sfd1    (rxclk, rst_, eval, esfd, esfd1);


always @(posedge rxclk or negedge rst_)
    begin
    if (!rst_)                  statem <= STT_IDLE;
    else if (eval)
        begin
        case (statem)
            STT_IDLE:   statem <= rxdv  ? STT_IPRM : STT_IDLE;
            STT_IPRM:   statem <= ~rxdv ? STT_IDLE :
                                  esfd  ? STT_IPAY : STT_IPRM;
            STT_IPAY:   statem <= ~rxdv ? STT_IDLE : STT_IPAY;
            default:            statem <= STT_IDLE;
        endcase
        end
    else                        statem <= statem;
    end

assign         dval = (statem == STT_IPAY) & eval;
assign         pval = (statem == STT_IPRM) & eval;
assign         gval = (statem == STT_IDLE) & eval;

assign         esof = eval & (statem == STT_IDLE) & ( rxdv);
assign         eeof = eval & (statem == STT_IPAY) & (~rxdv) & ipacketok;

assign         esfd = (pval & ((edat1 == DAT_SFD) | (prmc >= {1'b0, up_rxnumprm})));
assign         esop = esfd1 & eval;

assign         sfde = esfd & (edat1 != DAT_SFD);
assign         prme = ((!esfd & pval) & (edat1 != DAT_PRM)) | sfde;

always @(posedge rxclk or negedge rst_)
    begin
    if (!rst_)      ipacketok <= 1'b0;
    else if (esfd)  ipacketok <= 1'b1;
    else if (eeof)  ipacketok <= 1'b0;
    else            ipacketok <= ipacketok;
    end




always @(posedge rxclk or negedge rst_)
    begin
    if (!rst_)          prm_err <= 1'b0;
    else if (eeof)      prm_err <= 1'b0;
    else if (prme)      prm_err <= 1'b1;
    else                prm_err <= prm_err;
    end


always @(posedge rxclk or negedge rst_)
    begin
    if (!rst_)          prmc <= {PRM_CW{1'b0}};
    else if (~up_act)   prmc <= {PRM_CW{1'b0}};
    else if (eval)
        begin
        if (esof)       prmc <= {PRM_CW{1'b0}};
        else if (eeof)  prmc <= {PRM_CW{1'b0}} + 1'b1; 
        else            prmc <= &prmc ? {PRM_CW{1'b1}} : prmc + 1'b1;
        end
    end



always @(posedge rxclk or negedge rst_)
    begin
    if (!rst_)      fcs_dat <= {32{1'b1}};
    else if (esof)  fcs_dat <= {32{1'b1}};
    else if (esfd)  fcs_dat <= crc_dat;
    else if (eeof)  fcs_dat <= {32{1'b1}};
    else if (dval)  fcs_dat <= crc_dat;
    else            fcs_dat <= fcs_dat;
    end

assign fcs_err = (|(fcs_dat ^ FCS32_VAL)) & eeof;

ippcrc_crc32_8b icrc32_8b
    (
     .ci    (fcs_dat),
     .di    (edat),

     .co    (crc_dat)
     );





always @(posedge rxclk or negedge rst_)
    begin
    if (!rst_)          rcv_err <= 1'b0;
    else if (~up_act)   rcv_err <= 1'b0;
    else if (esof)      rcv_err <= 1'b0;
    else if (dval)      rcv_err <= rxer     ? 1'b1 : 
                                   rcv_err  ? 1'b1 : 1'b0;
    end



always @(posedge rxclk or negedge rst_)
    begin
    if (!rst_)          gap_err <= 1'b0;
    else if (esof)      gap_err <= (~(prmc >= {1'b0, up_thipg}));
    end




assign             eerr = {gap_err, rcv_err, prm_err, fcs_err};

fflopx #(DAT_DW*1) ffodat  (rxclk, rst_, edat1, odat);
fflopx #(1)        ffosop  (rxclk, rst_, esop, osop);
fflopx #(1)        ffoeop  (rxclk, rst_, eeof, oeop);
fflopx #(1)        ffoval  (rxclk, rst_, dval, oval);
fflopx #(1)        ffistt  (rxclk, rst_, gval, oistt);
fflopx #(DAT_EW*1) ffoerr  (rxclk, rst_, eerr, oerr);

endmodule
module ipsmacge_rxframing
    (
     rst_,
     rxclk,

     igval,
     igdat,
     igdv,
     iger,

     odat, 
     osop,  
     oeop,  
     oval,  
     oerr,

     oistt,

     up_rxen,
     up_act,
     up_thipg,
     up_rxnumprm
     );




parameter DAT_DW = 8,
          DAT_EW = 4;

parameter PRM_CW = 5;

parameter DAT_PRM = 8'h55,
          DAT_SFD = 8'hD5;

parameter STT_DW = 2;
parameter STT_IDLE = 2'b00,
          STT_IPRM = 2'b01,
          STT_IPAY = 2'b10;

parameter FCS32_VAL = 32'hc704dd7b;

parameter MRESERVE = 2'b11,
          M1000    = 2'b10,
          M100     = 2'b01,
          M10      = 2'b00;












input               rst_;
input               rxclk;


input  [DAT_DW-1:0] igdat;
input               igdv;
input               iger;
input               igval;

output [DAT_DW-1:0] odat;
output              osop;
output              oeop;
output [DAT_EW-1:0] oerr;
output              oval;

output              oistt;

input               up_rxen;
input               up_act;
input [3:0]         up_thipg;
input [3:0]         up_rxnumprm;



wire [31:0]          crc_dat;
reg  [31:0]          fcs_dat;
reg [PRM_CW-1:0]     prmc;

wire                 rxdv;
wire                 rxer;
wire [DAT_DW-1:0]    edat;
wire [DAT_DW-1:0]    edat1;
reg [STT_DW-1:0]     statem;

wire                 eval;
wire                 esof;
wire                 esop;
wire                 eeof;
wire                 esfd;
wire                 esfd1;
wire                 dval;
wire                 pval;
wire                 gval;

wire                 sfde;
wire                 prme;
wire [DAT_EW-1:0]    eerr;
wire                 fcs_err;
reg                  rcv_err;
reg                  prm_err;
reg                  ipacketok;

wire [DAT_DW-1:0]    odat;
wire                 oval;
wire                 osop;
wire                 oeop;
wire                 oistt;
wire [DAT_EW-1:0]    oerr;
reg                  gap_err;





assign             edat = up_rxen ? igdat : 8'h00;
assign             rxdv = up_rxen ? igdv  : 1'b0;
assign             rxer = up_rxen ? iger  : 1'b0;
assign             eval = igval;

fflopxe #(DAT_DW*1) ff1erxdat  (rxclk, rst_, eval, edat, edat1);
fflopxe #(1*1)      ff1sfd1    (rxclk, rst_, eval, esfd, esfd1);


always @(posedge rxclk or negedge rst_)
    begin
    if (!rst_)                  statem <= STT_IDLE;
    else if (eval)
        begin
        case (statem)
            STT_IDLE:   statem <= rxdv  ? STT_IPRM : STT_IDLE;
            STT_IPRM:   statem <= ~rxdv ? STT_IDLE :
                                  esfd  ? STT_IPAY : STT_IPRM;
            STT_IPAY:   statem <= ~rxdv ? STT_IDLE : STT_IPAY;
            default:            statem <= STT_IDLE;
        endcase
        end
    else                        statem <= statem;
    end

assign         dval = (statem == STT_IPAY) & eval;
assign         pval = (statem == STT_IPRM) & eval;
assign         gval = (statem == STT_IDLE) & eval;

assign         esof = eval & (statem == STT_IDLE) & ( rxdv);
assign         eeof = eval & (statem == STT_IPAY) & (~rxdv) & ipacketok;

assign         esfd = (pval & ((edat1 == DAT_SFD) | (prmc >= {1'b0, up_rxnumprm})));
assign         esop = esfd1 & eval;

assign         sfde = esfd & (edat1 != DAT_SFD);
assign         prme = ((!esfd & pval) & (edat1 != DAT_PRM)) | sfde;

always @(posedge rxclk or negedge rst_)
    begin
    if (!rst_)      ipacketok <= 1'b0;
    else if (esfd)  ipacketok <= 1'b1;
    else if (eeof)  ipacketok <= 1'b0;
    else            ipacketok <= ipacketok;
    end




always @(posedge rxclk or negedge rst_)
    begin
    if (!rst_)          prm_err <= 1'b0;
    else if (eeof)      prm_err <= 1'b0;
    else if (prme)      prm_err <= 1'b1;
    else                prm_err <= prm_err;
    end


always @(posedge rxclk or negedge rst_)
    begin
    if (!rst_)          prmc <= {PRM_CW{1'b0}};
    else if (~up_act)   prmc <= {PRM_CW{1'b0}};
    else if (eval)
        begin
        if (esof)       prmc <= {PRM_CW{1'b0}};
        else if (eeof)  prmc <= {PRM_CW{1'b0}} + 1'b1; 
        else            prmc <= &prmc ? {PRM_CW{1'b1}} : prmc + 1'b1;
        end
    end



always @(posedge rxclk or negedge rst_)
    begin
    if (!rst_)      fcs_dat <= {32{1'b1}};
    else if (esof)  fcs_dat <= {32{1'b1}};
    else if (esfd)  fcs_dat <= crc_dat;
    else if (eeof)  fcs_dat <= {32{1'b1}};
    else if (dval)  fcs_dat <= crc_dat;
    else            fcs_dat <= fcs_dat;
    end

assign fcs_err = (|(fcs_dat ^ FCS32_VAL)) & eeof;

ippcrc_crc32_8b icrc32_8b
    (
     .ci    (fcs_dat),
     .di    (edat),

     .co    (crc_dat)
     );





always @(posedge rxclk or negedge rst_)
    begin
    if (!rst_)          rcv_err <= 1'b0;
    else if (~up_act)   rcv_err <= 1'b0;
    else if (esof)      rcv_err <= 1'b0;
    else if (dval)      rcv_err <= rxer     ? 1'b1 : 
                                   rcv_err  ? 1'b1 : 1'b0;
    end



always @(posedge rxclk or negedge rst_)
    begin
    if (!rst_)          gap_err <= 1'b0;
    else if (esof)      gap_err <= (~(prmc >= {1'b0, up_thipg}));
    end




assign             eerr = {gap_err, rcv_err, prm_err, fcs_err};

fflopx #(DAT_DW*1) ffodat  (rxclk, rst_, edat1, odat);
fflopx #(1)        ffosop  (rxclk, rst_, esop, osop);
fflopx #(1)        ffoeop  (rxclk, rst_, eeof, oeop);
fflopx #(1)        ffoval  (rxclk, rst_, dval, oval);
fflopx #(1)        ffistt  (rxclk, rst_, gval, oistt);
fflopx #(DAT_EW*1) ffoerr  (rxclk, rst_, eerr, oerr);

endmodule