data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v
1: b'%Warning-WIDTH: data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v:107: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                  : ... In instance part3.u2\n    X_out <= Location[7:0] + Counter[1:0];\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v:108: Operator ADD expects 7 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                  : ... In instance part3.u2\n    Y_out <= Location[14:8] + Counter[3:2];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v:113: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                  : ... In instance part3.u2\n    X_out <= Location[7:0] + Counter[1:0];\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v:114: Operator ADD expects 7 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                  : ... In instance part3.u2\n    Y_out <= Location[14:8] + Counter[3:2];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v:40: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'Divider\' generates 7 bits.\n                                                                                 : ... In instance part3.u0\n  else if(Divider == (Frame_num - 1))\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v:49: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'Divider\' generates 7 bits.\n                                                                                 : ... In instance part3.u0\n  else if(Divider == (Frame_num - 1))\n                  ^~\n%Error: Exiting due to 6 warning(s)\n'
module RateDivider(Clock, Resetn, Frame_num, Enable);
	
	input Clock, Resetn;
	input [31:0] Frame_num; 
	
	output reg Enable;
	
	reg [6:0] Divider;
	
	
	always @(posedge Clock)
		if(!Resetn)
			Divider = 0;
		else if(Divider == (Frame_num - 1))
			Divider = 0;
		else 
			Divider = Divider + 1;
		
		
	always @(posedge Clock)
		if(!Resetn)
			Enable = 0;
		else if(Divider == (Frame_num - 1))
			Enable = 1;
		else 
			Enable = 0;

endmodule
module RateDivider(Clock, Resetn, Frame_num, Enable);

	
	input Clock, Resetn;
	input [31:0] Frame_num; 
	
	output reg Enable;
	
	reg [6:0] Divider;
	
	
	always @(posedge Clock)
		if(!Resetn)
			Divider = 0;
		else if(Divider == (Frame_num - 1))
			Divider = 0;
		else 
			Divider = Divider + 1;
		
		
	always @(posedge Clock)
		if(!Resetn)
			Enable = 0;
		else if(Divider == (Frame_num - 1))
			Enable = 1;
		else 
			Enable = 0;

endmodule