data/full_repos/permissive/489980666/old_ip/axi4_dv/axi4/rtl/axi4_slave.sv
1: b'%Warning-MULTITOP: data/full_repos/permissive/489980666/old_ip/axi4_dv/axi4/rtl/axi4_slave.sv:1: Multiple top level modules\n                                                                                               : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                               : ... Top module \'axi4_slave\'\nmodule axi4_slave(dut_if dif);\n       ^~~~~~~~~~\n                                                                                               : ... Top module \'dut_if\'\nmodule axi4_slave(dut_if dif);\n                  ^~~~~~\n%Error: data/full_repos/permissive/489980666/old_ip/axi4_dv/axi4/rtl/axi4_slave.sv:1: Unsupported: Interfaced port on top level module\nmodule axi4_slave(dut_if dif);\n                         ^~~\n%Error: data/full_repos/permissive/489980666/old_ip/axi4_dv/axi4/rtl/axi4_slave.sv:1: Cannot find file containing interface: \'dut_if\'\nmodule axi4_slave(dut_if dif);\n                  ^~~~~~\n%Error: Internal Error: data/full_repos/permissive/489980666/old_ip/axi4_dv/axi4/rtl/axi4_slave.sv:1: ../V3LinkDot.cpp:2055: Unlinked interface\nmodule axi4_slave(dut_if dif);\n                  ^~~~~~\n'
module axi4_slave(dut_if dif);
  logic [31:0] mem [0:256];
  logic [ 1:0] axi4_st;

  const logic [1:0] SETUP=0;
  const logic [1:0] W_ENABLE=1;
  const logic [1:0] R_ENABLE=2;
  
  always @(posedge dif.clk or negedge dif.rst) begin
    if (dif.rst==0) begin
      axi4_st      <=0;
      dif.dr_data  <=0;
      dif.dr_ready <=1;
      dif.b_ready  <=1;
      for(int i=0;i<256;i++) mem[i]=i;
    end
    else begin
      case (axi4_st)
        SETUP: begin
          dif.dr_data <= 0;
          if (dif.dw_strb && !dif.aw_len && !dif.ar_len) begin
            if (dif.dw_valid || dif.ar_valid) begin
              axi4_st <= W_ENABLE;
            end
            else begin
              axi4_st <= R_ENABLE;
              dif.dr_data <= mem[dif.ar_addr];
            end
          end
        end
        W_ENABLE: begin
          if (dif.dw_strb && dif.aw_len && dif.ar_len && dif.dw_valid && dif.ar_valid) begin
            mem[dif.aw_addr] <= dif.dw_data;
          end
          axi4_st <= SETUP;
        end
        R_ENABLE: begin
          axi4_st <= SETUP;
        end
      endcase
    end
  end
endmodule
module axi4_slave(dut_if dif);

  logic [31:0] mem [0:256];
  logic [ 1:0] axi4_st;

  const logic [1:0] SETUP=0;
  const logic [1:0] W_ENABLE=1;
  const logic [1:0] R_ENABLE=2;
  
  always @(posedge dif.clk or negedge dif.rst) begin
    if (dif.rst==0) begin
      axi4_st      <=0;
      dif.dr_data  <=0;
      dif.dr_ready <=1;
      dif.b_ready  <=1;
      for(int i=0;i<256;i++) mem[i]=i;
    end
    else begin
      case (axi4_st)
        SETUP: begin
          dif.dr_data <= 0;
          if (dif.dw_strb && !dif.aw_len && !dif.ar_len) begin
            if (dif.dw_valid || dif.ar_valid) begin
              axi4_st <= W_ENABLE;
            end
            else begin
              axi4_st <= R_ENABLE;
              dif.dr_data <= mem[dif.ar_addr];
            end
          end
        end
        W_ENABLE: begin
          if (dif.dw_strb && dif.aw_len && dif.ar_len && dif.dw_valid && dif.ar_valid) begin
            mem[dif.aw_addr] <= dif.dw_data;
          end
          axi4_st <= SETUP;
        end
        R_ENABLE: begin
          axi4_st <= SETUP;
        end
      endcase
    end
  end
endmodule