data/full_repos/permissive/521337848/Hardware/SPISD/transmitter.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/521337848/Hardware/SPISD/transmitter.v:197: Signal definition not found, creating implicitly: \'f_startsave\'\n .f_startsave(f_startsave),\n              ^~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/SPISD/transmitter.v:376: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'arg\' generates 32 bits.\n                                                                                     : ... In instance managerx.sa\n  in3 = arg;\n      ^\n%Error: Exiting due to 2 warning(s)\n'
module starter(
	input clk,
	input rst,
	
	input [5:0] cmd,
	input [31:0] arg,
	input [6:0] crc,
	input sta,
	input sta40,
	input readit,
	
	input n_init,
	input f_startsave,
	
	input[3:0] f_timinit,
	
	output reg[4:0] p_tim,
	output reg[2:0] p_ttim,

	output reg[5:0] f_cmd,
	output reg[31:0] f_arg,
	output reg[6:0] f_crc,
	
	
	output reg f_answ40,
	output reg f_c


);

always@(posedge clk or posedge rst)begin
	if(rst)begin
		f_cmd <= 0;
		f_arg <= 0;
		f_crc <= 0;
		f_answ40 <= 0;
		f_c <= 0;
	end else
	begin
		f_cmd <= n_cmd;
		f_arg <= n_arg;
		f_crc <= n_crc;
		f_answ40 <= n_answ40;
		f_c <= n_c;
	end
end


reg [5:0] n_cmd;
reg [31:0] n_arg;
reg [6:0] n_crc;

reg n_answ40;
reg n_c;

always@(*)begin
	
	p_tim = 31;
	p_ttim = 7;
	
	n_cmd = f_cmd;
	n_arg = f_arg;
	n_crc = f_crc;
	
	n_answ40 = f_answ40;
	
	n_c = f_c;

	
	if(n_init)begin
		p_tim = 0;
		p_ttim = 0;
		
		n_c = 0;
		n_answ40 = 0;
		
		n_cmd = 0;
		n_arg = 0;
		n_crc = 0;
	end
	
	if( ((sta && (~sta40)) || (sta40 && (~sta))) && f_timinit == 0)begin
	
		if(crc == 7'h7F) p_tim = 16;
		else p_tim = 1;
		
		p_ttim = 0;
		
		n_answ40 = sta40;
		
		n_c = readit;
		
		n_cmd = cmd;
		n_arg = arg;
		n_crc = crc;
		
	end
	
	if(f_startsave || f_timinit != 0)begin
		p_tim = 0;
		p_ttim = 0;
	end
end

endmodule
module starter(
	input clk,
	input rst,
	
	input [5:0] cmd,
	input [31:0] arg,
	input [6:0] crc,
	input sta,
	input sta40,
	input readit,
	
	input n_init,
	input f_startsave,
	
	input[3:0] f_timinit,
	
	output reg[4:0] p_tim,
	output reg[2:0] p_ttim,

	output reg[5:0] f_cmd,
	output reg[31:0] f_arg,
	output reg[6:0] f_crc,
	
	
	output reg f_answ40,
	output reg f_c


);


always@(posedge clk or posedge rst)begin
	if(rst)begin
		f_cmd <= 0;
		f_arg <= 0;
		f_crc <= 0;
		f_answ40 <= 0;
		f_c <= 0;
	end else
	begin
		f_cmd <= n_cmd;
		f_arg <= n_arg;
		f_crc <= n_crc;
		f_answ40 <= n_answ40;
		f_c <= n_c;
	end
end


reg [5:0] n_cmd;
reg [31:0] n_arg;
reg [6:0] n_crc;

reg n_answ40;
reg n_c;

always@(*)begin
	
	p_tim = 31;
	p_ttim = 7;
	
	n_cmd = f_cmd;
	n_arg = f_arg;
	n_crc = f_crc;
	
	n_answ40 = f_answ40;
	
	n_c = f_c;

	
	if(n_init)begin
		p_tim = 0;
		p_ttim = 0;
		
		n_c = 0;
		n_answ40 = 0;
		
		n_cmd = 0;
		n_arg = 0;
		n_crc = 0;
	end
	
	if( ((sta && (~sta40)) || (sta40 && (~sta))) && f_timinit == 0)begin
	
		if(crc == 7'h7F) p_tim = 16;
		else p_tim = 1;
		
		p_ttim = 0;
		
		n_answ40 = sta40;
		
		n_c = readit;
		
		n_cmd = cmd;
		n_arg = arg;
		n_crc = crc;
		
	end
	
	if(f_startsave || f_timinit != 0)begin
		p_tim = 0;
		p_ttim = 0;
	end
end

endmodule