data/full_repos/permissive/421380819/verilog/rtl/ramInterface/openRam.v
data/verilator_xmls/563b0c72-fc70-4b26-9956-716119090b84.xml
module openRam (
    input   wire            CLK,
    input   wire            CSb,
    input   wire            WEb,
    input   wire    [4:0]   ADDR,
    input   wire    [7:0]   DATA_IN,
    output  wire    [7:0]   DATA_OUT
);
    

    reg       CSb_Q;
    reg       WEb_Q;
    reg [4:0] ADDR_Q;
    reg [7:0] DATA_IN_Q;

    reg [7:0] RAM_Q [31:0];
    reg [7:0] RAM_OUT_Q;


    assign DATA_OUT = RAM_OUT_Q;


    always @(posedge(CLK)) begin
        CSb_Q       <= CSb;
        WEb_Q       <= WEb;
        ADDR_Q      <= ADDR;
        DATA_IN_Q   <= DATA_IN;
    end


    always @(negedge(CLK)) begin

        if (CSb_Q == 1'b0) begin

            if (WEb_Q == 1'b0) begin
                RAM_Q[ADDR_Q] <= DATA_IN_Q;
                RAM_OUT_Q     <= DATA_IN_Q;

            end else RAM_OUT_Q <= RAM_Q[ADDR_Q];
        end
    end
endmodule
module openRam (
    input   wire            CLK,
    input   wire            CSb,
    input   wire            WEb,
    input   wire    [4:0]   ADDR,
    input   wire    [7:0]   DATA_IN,
    output  wire    [7:0]   DATA_OUT
);

    

    reg       CSb_Q;
    reg       WEb_Q;
    reg [4:0] ADDR_Q;
    reg [7:0] DATA_IN_Q;

    reg [7:0] RAM_Q [31:0];
    reg [7:0] RAM_OUT_Q;


    assign DATA_OUT = RAM_OUT_Q;


    always @(posedge(CLK)) begin
        CSb_Q       <= CSb;
        WEb_Q       <= WEb;
        ADDR_Q      <= ADDR;
        DATA_IN_Q   <= DATA_IN;
    end


    always @(negedge(CLK)) begin

        if (CSb_Q == 1'b0) begin

            if (WEb_Q == 1'b0) begin
                RAM_Q[ADDR_Q] <= DATA_IN_Q;
                RAM_OUT_Q     <= DATA_IN_Q;

            end else RAM_OUT_Q <= RAM_Q[ADDR_Q];
        end
    end
endmodule