data/full_repos/permissive/523038000/MIPS/mux32to1.v
data/verilator_xmls/e704fb90-e89d-47e6-9222-cdc920a9c50f.xml
module mux_32to1(out, a,b,sel);
output [31:0] out;
input [31:0] a,b;
input sel;
reg [31:0] out;
always @ (sel or a or b)
  if(sel==0)
  out = a;
  else
  out = b;
endmodule
module mux_32to1(out, a,b,sel);

output [31:0] out;
input [31:0] a,b;
input sel;
reg [31:0] out;
always @ (sel or a or b)
  if(sel==0)
  out = a;
  else
  out = b;
endmodule