data/full_repos/permissive/427221126/workspace/mult_booth.sv
data/verilator_xmls/8c0f0c4b-8478-4475-9fde-3cb583000ab9.xml
module csa  (
	input [31:0] op1,
	input [31:0] op2,
	input [31:0] op3,
	output [31:0] S,
	output [31:0] C
);

genvar i;
generate
	for(i=0; i<32; i=i+1) begin
		full_adder u_full_adder(
			.a      (   op1[i]    ),
			.b      (   op2[i]    ),
			.cin    (   op3[i]    ),
			.cout   (   C[i]	  ),
			.s      (   S[i]      )
		);
	end
endgenerate

endmodule
module csa  (
	input [31:0] op1,
	input [31:0] op2,
	input [31:0] op3,
	output [31:0] S,
	output [31:0] C
);


genvar i;
generate
	for(i=0; i<32; i=i+1) begin
		full_adder u_full_adder(
			.a      (   op1[i]    ),
			.b      (   op2[i]    ),
			.cin    (   op3[i]    ),
			.cout   (   C[i]	  ),
			.s      (   S[i]      )
		);
	end
endgenerate

endmodule