data/full_repos/permissive/421030651/src/cpu/mul.sv
1: b"%Error: data/full_repos/permissive/421030651/src/cpu/mul.sv:7: Define or directive not defined: '`XLEN'\n    input        [  `XLEN-1:0] src1,\n                    ^~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mul.sv:9: Define or directive not defined: '`XLEN'\n    input        [  `XLEN-1:0] src2,\n                    ^~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mul.sv:10: Define or directive not defined: '`XLEN'\n    output logic [2*`XLEN-1:0] out,\n                    ^~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mul.sv:14: Define or directive not defined: '`XLEN'\nlogic [2*`XLEN-1:0] src1_ext;\n         ^~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mul.sv:15: Define or directive not defined: '`XLEN'\nlogic [2*`XLEN-1:0] src2_ext;\n         ^~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mul.sv:26: Define or directive not defined: '`XLEN'\n        src1_ext <= {2*`XLEN{1'b0}};\n                       ^~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mul.sv:27: Define or directive not defined: '`XLEN'\n        src2_ext <= {2*`XLEN{1'b0}};\n                       ^~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mul.sv:30: Define or directive not defined: '`XLEN'\n        src1_ext <= {{`XLEN{signed1 & src1[`XLEN-1]}}, src1};\n                      ^~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mul.sv:30: Define or directive not defined: '`XLEN'\n        src1_ext <= {{`XLEN{signed1 & src1[`XLEN-1]}}, src1};\n                                           ^~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mul.sv:31: Define or directive not defined: '`XLEN'\n        src2_ext <= {{`XLEN{signed2 & src2[`XLEN-1]}}, src2};\n                      ^~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mul.sv:31: Define or directive not defined: '`XLEN'\n        src2_ext <= {{`XLEN{signed2 & src2[`XLEN-1]}}, src2};\n                                           ^~~~~\n%Error: data/full_repos/permissive/421030651/src/cpu/mul.sv:37: Define or directive not defined: '`XLEN'\n        out <= {2*`XLEN{1'b0}};\n                  ^~~~~\n%Error: Exiting due to 12 error(s)\n"
module mul (
    input                      clk,
    input                      rstn,
    input                      trig,
    input                      flush,
    input                      signed1,
    input        [  `XLEN-1:0] src1,
    input                      signed2,
    input        [  `XLEN-1:0] src2,
    output logic [2*`XLEN-1:0] out,
    output logic               okay
);

logic [2*`XLEN-1:0] src1_ext;
logic [2*`XLEN-1:0] src2_ext;

logic [        1:0] cur_state;
logic [        1:0] nxt_state;

parameter[1:0] STATE_IDLE = 2'h0,
               STATE_EXEC = 2'h1,
               STATE_DONE = 2'h2;

always_ff @(posedge clk or negedge rstn) begin: reg_src
    if (~rstn) begin
        src1_ext <= {2*`XLEN{1'b0}};
        src2_ext <= {2*`XLEN{1'b0}};
    end
    else if (trig) begin
        src1_ext <= {{`XLEN{signed1 & src1[`XLEN-1]}}, src1};
        src2_ext <= {{`XLEN{signed2 & src2[`XLEN-1]}}, src2};
    end
end

always_ff @(posedge clk or negedge rstn) begin: reg_out
    if (~rstn) begin
        out <= {2*`XLEN{1'b0}};
    end
    else begin
        out <= src1_ext * src2_ext;;
    end
end






always_ff @(posedge clk or negedge rstn) begin: fsm
    if (~rstn) cur_state <= STATE_IDLE;
    else       cur_state <= nxt_state;
end

always_comb begin: next_state
    nxt_state = cur_state;
    case (cur_state)
        STATE_IDLE: nxt_state = trig ? STATE_EXEC : STATE_IDLE;
        STATE_EXEC: nxt_state = STATE_DONE;
        STATE_DONE: nxt_state = STATE_IDLE;
    endcase
end

assign okay = cur_state == STATE_DONE;

endmodule
module mul (
    input                      clk,
    input                      rstn,
    input                      trig,
    input                      flush,
    input                      signed1,
    input        [  `XLEN-1:0] src1,
    input                      signed2,
    input        [  `XLEN-1:0] src2,
    output logic [2*`XLEN-1:0] out,
    output logic               okay
);


logic [2*`XLEN-1:0] src1_ext;
logic [2*`XLEN-1:0] src2_ext;

logic [        1:0] cur_state;
logic [        1:0] nxt_state;

parameter[1:0] STATE_IDLE = 2'h0,
               STATE_EXEC = 2'h1,
               STATE_DONE = 2'h2;

always_ff @(posedge clk or negedge rstn) begin: reg_src
    if (~rstn) begin
        src1_ext <= {2*`XLEN{1'b0}};
        src2_ext <= {2*`XLEN{1'b0}};
    end
    else if (trig) begin
        src1_ext <= {{`XLEN{signed1 & src1[`XLEN-1]}}, src1};
        src2_ext <= {{`XLEN{signed2 & src2[`XLEN-1]}}, src2};
    end
end

always_ff @(posedge clk or negedge rstn) begin: reg_out
    if (~rstn) begin
        out <= {2*`XLEN{1'b0}};
    end
    else begin
        out <= src1_ext * src2_ext;;
    end
end






always_ff @(posedge clk or negedge rstn) begin: fsm
    if (~rstn) cur_state <= STATE_IDLE;
    else       cur_state <= nxt_state;
end

always_comb begin: next_state
    nxt_state = cur_state;
    case (cur_state)
        STATE_IDLE: nxt_state = trig ? STATE_EXEC : STATE_IDLE;
        STATE_EXEC: nxt_state = STATE_DONE;
        STATE_DONE: nxt_state = STATE_IDLE;
    endcase
end

assign okay = cur_state == STATE_DONE;

endmodule