data/full_repos/permissive/423958267/lab04_2/lab04_2.srcs/sources_1/imports/sources_1/imports/new/main.v
1: b"%Error: data/full_repos/permissive/423958267/lab04_2/lab04_2.srcs/sources_1/imports/sources_1/imports/new/main.v:45: Cannot find file containing module: 'ROM'\n    ROM r(data,SW,clk);\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/423958267/lab04_2/lab04_2.srcs/sources_1/imports/sources_1/imports/new,data/full_repos/permissive/423958267/ROM\n             data/full_repos/permissive/423958267/lab04_2/lab04_2.srcs/sources_1/imports/sources_1/imports/new,data/full_repos/permissive/423958267/ROM.v\n             data/full_repos/permissive/423958267/lab04_2/lab04_2.srcs/sources_1/imports/sources_1/imports/new,data/full_repos/permissive/423958267/ROM.sv\n             ROM\n             ROM.v\n             ROM.sv\n             obj_dir/ROM\n             obj_dir/ROM.v\n             obj_dir/ROM.sv\n%Error: data/full_repos/permissive/423958267/lab04_2/lab04_2.srcs/sources_1/imports/sources_1/imports/new/main.v:56: Cannot find file containing module: 'Switch'\n            Switch s(SW[i],sw[i],clk);\n            ^~~~~~\n%Error: data/full_repos/permissive/423958267/lab04_2/lab04_2.srcs/sources_1/imports/sources_1/imports/new/main.v:65: Cannot find file containing module: 'Counter'\n    Counter #(20) c(counter,nreset,clk);\n    ^~~~~~~\n%Error: data/full_repos/permissive/423958267/lab04_2/lab04_2.srcs/sources_1/imports/sources_1/imports/new/main.v:67: Cannot find file containing module: 'Mux4to1'\n    Mux4to1 #(4) mx(d,q,digit0,digit1,digit2,digit3);\n    ^~~~~~~\n%Error: data/full_repos/permissive/423958267/lab04_2/lab04_2.srcs/sources_1/imports/sources_1/imports/new/main.v:68: Cannot find file containing module: 'Decoder4'\n    Decoder4 dec(sel,q);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/423958267/lab04_2/lab04_2.srcs/sources_1/imports/sources_1/imports/new/main.v:69: Cannot find file containing module: 'HexTo7Seg'\n    HexTo7Seg h(seg,d);\n    ^~~~~~~~~\n%Error: Exiting due to 6 error(s)\n"
module main(
    output wire [6:0] seg,
    output wire [3:0] an,

    input btnC,
    input btnU,
    input btnD,
    input [7:0] sw,
    input clk
);
    wire [1:0] q;
    wire d0,d1;
    wire [3:0] d;
    wire [3:0] digit0,digit1,digit2,digit3;
    wire [3:0] sel;
    wire [19:0] counter;

    wire [4:0] SW;
    wire [7:0] data;

    reg nreset;
    
    ROM r(data,SW,clk);
    
    assign digit0 = data[3:0];
    assign digit1 = data[7:4];
    
    assign digit2 = 4'd0;
    assign digit3 = 4'd0;
    
    genvar i;
    generate
        for(i=0;i<5;i=i+1) begin
            Switch s(SW[i],sw[i],clk);
        end
    endgenerate

    assign q = {counter[19],counter[18]};

    assign an = ~sel;
    
    initial nreset <= 1;
    Counter #(20) c(counter,nreset,clk);

    Mux4to1 #(4) mx(d,q,digit0,digit1,digit2,digit3);
    Decoder4 dec(sel,q);
    HexTo7Seg h(seg,d);

endmodule
module main(
    output wire [6:0] seg,
    output wire [3:0] an,

    input btnC,
    input btnU,
    input btnD,
    input [7:0] sw,
    input clk
);

    wire [1:0] q;
    wire d0,d1;
    wire [3:0] d;
    wire [3:0] digit0,digit1,digit2,digit3;
    wire [3:0] sel;
    wire [19:0] counter;

    wire [4:0] SW;
    wire [7:0] data;

    reg nreset;
    
    ROM r(data,SW,clk);
    
    assign digit0 = data[3:0];
    assign digit1 = data[7:4];
    
    assign digit2 = 4'd0;
    assign digit3 = 4'd0;
    
    genvar i;
    generate
        for(i=0;i<5;i=i+1) begin
            Switch s(SW[i],sw[i],clk);
        end
    endgenerate

    assign q = {counter[19],counter[18]};

    assign an = ~sel;
    
    initial nreset <= 1;
    Counter #(20) c(counter,nreset,clk);

    Mux4to1 #(4) mx(d,q,digit0,digit1,digit2,digit3);
    Decoder4 dec(sel,q);
    HexTo7Seg h(seg,d);

endmodule