data/full_repos/permissive/441359809/src/yosys/techlibs/efinix/cells_map.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/techlibs/efinix/cells_map.v:21: Multiple top level modules\n                                                                                                : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                : ... Top module \'$_DFFE_xxxx_\'\nmodule  \\$_DFFE_xxxx_ (input D, C, R, E, output Q);\n        ^~~~~~~~~~~~~\n                                                                                                : ... Top module \'$_SDFFE_xxxx_\'\nmodule  \\$_SDFFE_xxxx_ (input D, C, R, E, output Q);\n        ^~~~~~~~~~~~~~\n                                                                                                : ... Top module \'$_SDFFCE_xxxx_\'\nmodule  \\$_SDFFCE_xxxx_ (input D, C, R, E, output Q);\n        ^~~~~~~~~~~~~~~\n                                                                                                : ... Top module \'$_DLATCH_N_\'\nmodule \\$_DLATCH_N_ (E, D, Q);\n       ^~~~~~~~~~~~\n                                                                                                : ... Top module \'$_DLATCH_P_\'\nmodule \\$_DLATCH_P_ (E, D, Q);\n       ^~~~~~~~~~~~\n                                                                                                : ... Top module \'$lut\'\nmodule \\$lut (A, Y);\n       ^~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/441359809/src/yosys/techlibs/efinix/cells_map.v:76: Little bit endian vector: MSB < LSB of bit range: -1:0\n  input [WIDTH-1:0] A;\n        ^\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/efinix/cells_map.v:44: Cannot find file containing module: \'EFX_FF\'\n  EFX_FF #(\n  ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/441359809/src/yosys/techlibs/efinix,data/full_repos/permissive/441359809/EFX_FF\n             data/full_repos/permissive/441359809/src/yosys/techlibs/efinix,data/full_repos/permissive/441359809/EFX_FF.v\n             data/full_repos/permissive/441359809/src/yosys/techlibs/efinix,data/full_repos/permissive/441359809/EFX_FF.sv\n             EFX_FF\n             EFX_FF.v\n             EFX_FF.sv\n             obj_dir/EFX_FF\n             obj_dir/EFX_FF.v\n             obj_dir/EFX_FF.sv\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/efinix/cells_map.v:25: Cannot find file containing module: \'EFX_FF\'\n  EFX_FF #(\n  ^~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/efinix/cells_map.v:6: Cannot find file containing module: \'EFX_FF\'\n  EFX_FF #(\n  ^~~~~~\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module  \$_SDFFE_xxxx_ (input D, C, R, E, output Q);

  parameter _TECHMAP_CELLTYPE_ = "";

  EFX_FF #(
    .CLK_POLARITY(_TECHMAP_CELLTYPE_[39:32] == "P"),
    .CE_POLARITY(_TECHMAP_CELLTYPE_[15:8] == "P"),
    .SR_POLARITY(_TECHMAP_CELLTYPE_[31:24] == "P"),
    .D_POLARITY(1'b1),
    .SR_SYNC(1'b1),
    .SR_VALUE(_TECHMAP_CELLTYPE_[23:16] == "1"),
    .SR_SYNC_PRIORITY(1'b1)
  ) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(R), .Q(Q));

  wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;

endmodule
module  \$_SDFFE_xxxx_ (input D, C, R, E, output Q);


  parameter _TECHMAP_CELLTYPE_ = "";

  EFX_FF #(
    .CLK_POLARITY(_TECHMAP_CELLTYPE_[39:32] == "P"),
    .CE_POLARITY(_TECHMAP_CELLTYPE_[15:8] == "P"),
    .SR_POLARITY(_TECHMAP_CELLTYPE_[31:24] == "P"),
    .D_POLARITY(1'b1),
    .SR_SYNC(1'b1),
    .SR_VALUE(_TECHMAP_CELLTYPE_[23:16] == "1"),
    .SR_SYNC_PRIORITY(1'b1)
  ) _TECHMAP_REPLACE_ (.D(D), .CE(E), .CLK(C), .SR(R), .Q(Q));

  wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;

endmodule