data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/top/NV_NVDLA_partition_p.v
1: b"%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/top/NV_NVDLA_partition_p.v:301: Cannot find file containing module: 'NV_NVDLA_reset'\nNV_NVDLA_reset u_partition_p_reset (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/top,data/full_repos/permissive/509468557/NV_NVDLA_reset\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/top,data/full_repos/permissive/509468557/NV_NVDLA_reset.v\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/top,data/full_repos/permissive/509468557/NV_NVDLA_reset.sv\n             NV_NVDLA_reset\n             NV_NVDLA_reset.v\n             NV_NVDLA_reset.sv\n             obj_dir/NV_NVDLA_reset\n             obj_dir/NV_NVDLA_reset.v\n             obj_dir/NV_NVDLA_reset.sv\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/top/NV_NVDLA_partition_p.v:312: Cannot find file containing module: 'NV_NVDLA_sync3d'\nNV_NVDLA_sync3d u_dla_clk_ovr_on_sync (\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/top/NV_NVDLA_partition_p.v:318: Cannot find file containing module: 'NV_NVDLA_sync3d_s'\nNV_NVDLA_sync3d_s u_global_clk_ovr_on_sync (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/top/NV_NVDLA_partition_p.v:328: Cannot find file containing module: 'NV_NVDLA_sdp'\nNV_NVDLA_sdp u_NV_NVDLA_sdp (\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/top/NV_NVDLA_partition_p.v:425: Cannot find file containing module: 'NV_NVDLA_RT_cmac_a2cacc'\nNV_NVDLA_RT_cmac_a2cacc u_NV_NVDLA_RT_cmac_a2cacc (\n^~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module NV_NVDLA_partition_p (
   cacc2sdp_pd
  ,cacc2sdp_valid
  ,csb2sdp_rdma_req_pd
  ,csb2sdp_rdma_req_pvld
  ,csb2sdp_req_pd
  ,csb2sdp_req_pvld
  ,cvif2sdp_b_rd_rsp_pd
  ,cvif2sdp_b_rd_rsp_valid
  ,cvif2sdp_e_rd_rsp_pd
  ,cvif2sdp_e_rd_rsp_valid
  ,cvif2sdp_n_rd_rsp_pd
  ,cvif2sdp_n_rd_rsp_valid
  ,cvif2sdp_rd_rsp_pd
  ,cvif2sdp_rd_rsp_valid
  ,cvif2sdp_wr_rsp_complete
  ,direct_reset_
  ,dla_reset_rstn
  ,global_clk_ovr_on
  ,mac_a2accu_src_data0
  ,mac_a2accu_src_data1
  ,mac_a2accu_src_data2
  ,mac_a2accu_src_data3
  ,mac_a2accu_src_data4
  ,mac_a2accu_src_data5
  ,mac_a2accu_src_data6
  ,mac_a2accu_src_data7
  ,mac_a2accu_src_mask
  ,mac_a2accu_src_mode
  ,mac_a2accu_src_pd
  ,mac_a2accu_src_pvld
  ,mcif2sdp_b_rd_rsp_pd
  ,mcif2sdp_b_rd_rsp_valid
  ,mcif2sdp_e_rd_rsp_pd
  ,mcif2sdp_e_rd_rsp_valid
  ,mcif2sdp_n_rd_rsp_pd
  ,mcif2sdp_n_rd_rsp_valid
  ,mcif2sdp_rd_rsp_pd
  ,mcif2sdp_rd_rsp_valid
  ,mcif2sdp_wr_rsp_complete
  ,nvdla_clk_ovr_on
  ,nvdla_core_clk
  ,pwrbus_ram_pd
  ,sdp2cvif_rd_req_ready
  ,sdp2cvif_wr_req_ready
  ,sdp2mcif_rd_req_ready
  ,sdp2mcif_wr_req_ready
  ,sdp2pdp_ready
  ,sdp_b2cvif_rd_req_ready
  ,sdp_b2mcif_rd_req_ready
  ,sdp_e2cvif_rd_req_ready
  ,sdp_e2mcif_rd_req_ready
  ,sdp_n2cvif_rd_req_ready
  ,sdp_n2mcif_rd_req_ready
  ,test_mode
  ,tmc2slcg_disable_clock_gating
  ,cacc2sdp_ready
  ,csb2sdp_rdma_req_prdy
  ,csb2sdp_req_prdy
  ,cvif2sdp_b_rd_rsp_ready
  ,cvif2sdp_e_rd_rsp_ready
  ,cvif2sdp_n_rd_rsp_ready
  ,cvif2sdp_rd_rsp_ready
  ,mac_a2accu_dst_data0
  ,mac_a2accu_dst_data1
  ,mac_a2accu_dst_data2
  ,mac_a2accu_dst_data3
  ,mac_a2accu_dst_data4
  ,mac_a2accu_dst_data5
  ,mac_a2accu_dst_data6
  ,mac_a2accu_dst_data7
  ,mac_a2accu_dst_mask
  ,mac_a2accu_dst_mode
  ,mac_a2accu_dst_pd
  ,mac_a2accu_dst_pvld
  ,mcif2sdp_b_rd_rsp_ready
  ,mcif2sdp_e_rd_rsp_ready
  ,mcif2sdp_n_rd_rsp_ready
  ,mcif2sdp_rd_rsp_ready
  ,sdp2csb_resp_pd
  ,sdp2csb_resp_valid
  ,sdp2cvif_rd_cdt_lat_fifo_pop
  ,sdp2cvif_rd_req_pd
  ,sdp2cvif_rd_req_valid
  ,sdp2cvif_wr_req_pd
  ,sdp2cvif_wr_req_valid
  ,sdp2glb_done_intr_pd
  ,sdp2mcif_rd_cdt_lat_fifo_pop
  ,sdp2mcif_rd_req_pd
  ,sdp2mcif_rd_req_valid
  ,sdp2mcif_wr_req_pd
  ,sdp2mcif_wr_req_valid
  ,sdp2pdp_pd
  ,sdp2pdp_valid
  ,sdp_b2cvif_rd_cdt_lat_fifo_pop
  ,sdp_b2cvif_rd_req_pd
  ,sdp_b2cvif_rd_req_valid
  ,sdp_b2mcif_rd_cdt_lat_fifo_pop
  ,sdp_b2mcif_rd_req_pd
  ,sdp_b2mcif_rd_req_valid
  ,sdp_e2cvif_rd_cdt_lat_fifo_pop
  ,sdp_e2cvif_rd_req_pd
  ,sdp_e2cvif_rd_req_valid
  ,sdp_e2mcif_rd_cdt_lat_fifo_pop
  ,sdp_e2mcif_rd_req_pd
  ,sdp_e2mcif_rd_req_valid
  ,sdp_n2cvif_rd_cdt_lat_fifo_pop
  ,sdp_n2cvif_rd_req_pd
  ,sdp_n2cvif_rd_req_valid
  ,sdp_n2mcif_rd_cdt_lat_fifo_pop
  ,sdp_n2mcif_rd_req_pd
  ,sdp_n2mcif_rd_req_valid
  ,sdp_rdma2csb_resp_pd
  ,sdp_rdma2csb_resp_valid
  );





input  test_mode;
input  direct_reset_;

input  global_clk_ovr_on;
input  tmc2slcg_disable_clock_gating;

input          cacc2sdp_valid;
output         cacc2sdp_ready;
input  [513:0] cacc2sdp_pd;

input         csb2sdp_rdma_req_pvld;
output        csb2sdp_rdma_req_prdy;
input  [62:0] csb2sdp_rdma_req_pd;

input         csb2sdp_req_pvld;
output        csb2sdp_req_prdy;
input  [62:0] csb2sdp_req_pd;

input          cvif2sdp_b_rd_rsp_valid;
output         cvif2sdp_b_rd_rsp_ready;
input  [513:0] cvif2sdp_b_rd_rsp_pd;

input          cvif2sdp_e_rd_rsp_valid;
output         cvif2sdp_e_rd_rsp_ready;
input  [513:0] cvif2sdp_e_rd_rsp_pd;

input          cvif2sdp_n_rd_rsp_valid;
output         cvif2sdp_n_rd_rsp_ready;
input  [513:0] cvif2sdp_n_rd_rsp_pd;

input          cvif2sdp_rd_rsp_valid;
output         cvif2sdp_rd_rsp_ready;
input  [513:0] cvif2sdp_rd_rsp_pd;

input  cvif2sdp_wr_rsp_complete;

output         mac_a2accu_dst_pvld;
output   [7:0] mac_a2accu_dst_mask;
output   [7:0] mac_a2accu_dst_mode;
output [175:0] mac_a2accu_dst_data0;
output [175:0] mac_a2accu_dst_data1;
output [175:0] mac_a2accu_dst_data2;
output [175:0] mac_a2accu_dst_data3;
output [175:0] mac_a2accu_dst_data4;
output [175:0] mac_a2accu_dst_data5;
output [175:0] mac_a2accu_dst_data6;
output [175:0] mac_a2accu_dst_data7;
output   [8:0] mac_a2accu_dst_pd;

input         mac_a2accu_src_pvld;
input   [7:0] mac_a2accu_src_mask;
input   [7:0] mac_a2accu_src_mode;
input [175:0] mac_a2accu_src_data0;
input [175:0] mac_a2accu_src_data1;
input [175:0] mac_a2accu_src_data2;
input [175:0] mac_a2accu_src_data3;
input [175:0] mac_a2accu_src_data4;
input [175:0] mac_a2accu_src_data5;
input [175:0] mac_a2accu_src_data6;
input [175:0] mac_a2accu_src_data7;
input   [8:0] mac_a2accu_src_pd;

input          mcif2sdp_b_rd_rsp_valid;
output         mcif2sdp_b_rd_rsp_ready;
input  [513:0] mcif2sdp_b_rd_rsp_pd;

input          mcif2sdp_e_rd_rsp_valid;
output         mcif2sdp_e_rd_rsp_ready;
input  [513:0] mcif2sdp_e_rd_rsp_pd;

input          mcif2sdp_n_rd_rsp_valid;
output         mcif2sdp_n_rd_rsp_ready;
input  [513:0] mcif2sdp_n_rd_rsp_pd;

input          mcif2sdp_rd_rsp_valid;
output         mcif2sdp_rd_rsp_ready;
input  [513:0] mcif2sdp_rd_rsp_pd;

input  mcif2sdp_wr_rsp_complete;

input [31:0] pwrbus_ram_pd;

output        sdp2csb_resp_valid;
output [33:0] sdp2csb_resp_pd;

output  sdp2cvif_rd_cdt_lat_fifo_pop;

output        sdp2cvif_rd_req_valid;
input         sdp2cvif_rd_req_ready;
output [78:0] sdp2cvif_rd_req_pd;

output         sdp2cvif_wr_req_valid;
input          sdp2cvif_wr_req_ready;
output [514:0] sdp2cvif_wr_req_pd;

output [1:0] sdp2glb_done_intr_pd;

output  sdp2mcif_rd_cdt_lat_fifo_pop;

output        sdp2mcif_rd_req_valid;
input         sdp2mcif_rd_req_ready;
output [78:0] sdp2mcif_rd_req_pd;

output         sdp2mcif_wr_req_valid;
input          sdp2mcif_wr_req_ready;
output [514:0] sdp2mcif_wr_req_pd;

output         sdp2pdp_valid;
input          sdp2pdp_ready;
output [255:0] sdp2pdp_pd;

output  sdp_b2cvif_rd_cdt_lat_fifo_pop;

output        sdp_b2cvif_rd_req_valid;
input         sdp_b2cvif_rd_req_ready;
output [78:0] sdp_b2cvif_rd_req_pd;

output  sdp_b2mcif_rd_cdt_lat_fifo_pop;

output        sdp_b2mcif_rd_req_valid;
input         sdp_b2mcif_rd_req_ready;
output [78:0] sdp_b2mcif_rd_req_pd;

output  sdp_e2cvif_rd_cdt_lat_fifo_pop;

output        sdp_e2cvif_rd_req_valid;
input         sdp_e2cvif_rd_req_ready;
output [78:0] sdp_e2cvif_rd_req_pd;

output  sdp_e2mcif_rd_cdt_lat_fifo_pop;

output        sdp_e2mcif_rd_req_valid;
input         sdp_e2mcif_rd_req_ready;
output [78:0] sdp_e2mcif_rd_req_pd;

output  sdp_n2cvif_rd_cdt_lat_fifo_pop;

output        sdp_n2cvif_rd_req_valid;
input         sdp_n2cvif_rd_req_ready;
output [78:0] sdp_n2cvif_rd_req_pd;

output  sdp_n2mcif_rd_cdt_lat_fifo_pop;

output        sdp_n2mcif_rd_req_valid;
input         sdp_n2mcif_rd_req_ready;
output [78:0] sdp_n2mcif_rd_req_pd;

output        sdp_rdma2csb_resp_valid;
output [33:0] sdp_rdma2csb_resp_pd;




input  nvdla_core_clk;     
input  dla_reset_rstn;     

input  nvdla_clk_ovr_on;

wire   dla_clk_ovr_on_sync;
wire   global_clk_ovr_on_sync;
wire   nvdla_core_rstn;




NV_NVDLA_reset u_partition_p_reset (
   .dla_reset_rstn                 (dla_reset_rstn)
  ,.direct_reset_                  (direct_reset_)
  ,.test_mode                      (test_mode)
  ,.synced_rstn                    (nvdla_core_rstn)
  ,.nvdla_clk                      (nvdla_core_clk)
  );




NV_NVDLA_sync3d u_dla_clk_ovr_on_sync (
   .clk                            (nvdla_core_clk)
  ,.sync_i                         (nvdla_clk_ovr_on)
  ,.sync_o                         (dla_clk_ovr_on_sync)
  );

NV_NVDLA_sync3d_s u_global_clk_ovr_on_sync (
   .clk                            (nvdla_core_clk)
  ,.prst                           (nvdla_core_rstn)
  ,.sync_i                         (global_clk_ovr_on)
  ,.sync_o                         (global_clk_ovr_on_sync)
  );




NV_NVDLA_sdp u_NV_NVDLA_sdp (
   .nvdla_core_clk                 (nvdla_core_clk)
  ,.nvdla_core_rstn                (nvdla_core_rstn)
  ,.cacc2sdp_valid                 (cacc2sdp_valid)
  ,.cacc2sdp_ready                 (cacc2sdp_ready)
  ,.cacc2sdp_pd                    (cacc2sdp_pd[513:0])
  ,.csb2sdp_rdma_req_pvld          (csb2sdp_rdma_req_pvld)
  ,.csb2sdp_rdma_req_prdy          (csb2sdp_rdma_req_prdy)
  ,.csb2sdp_rdma_req_pd            (csb2sdp_rdma_req_pd[62:0])
  ,.csb2sdp_req_pvld               (csb2sdp_req_pvld)
  ,.csb2sdp_req_prdy               (csb2sdp_req_prdy)
  ,.csb2sdp_req_pd                 (csb2sdp_req_pd[62:0])
  ,.cvif2sdp_b_rd_rsp_valid        (cvif2sdp_b_rd_rsp_valid)
  ,.cvif2sdp_b_rd_rsp_ready        (cvif2sdp_b_rd_rsp_ready)
  ,.cvif2sdp_b_rd_rsp_pd           (cvif2sdp_b_rd_rsp_pd[513:0])
  ,.cvif2sdp_e_rd_rsp_valid        (cvif2sdp_e_rd_rsp_valid)
  ,.cvif2sdp_e_rd_rsp_ready        (cvif2sdp_e_rd_rsp_ready)
  ,.cvif2sdp_e_rd_rsp_pd           (cvif2sdp_e_rd_rsp_pd[513:0])
  ,.cvif2sdp_n_rd_rsp_valid        (cvif2sdp_n_rd_rsp_valid)
  ,.cvif2sdp_n_rd_rsp_ready        (cvif2sdp_n_rd_rsp_ready)
  ,.cvif2sdp_n_rd_rsp_pd           (cvif2sdp_n_rd_rsp_pd[513:0])
  ,.cvif2sdp_rd_rsp_valid          (cvif2sdp_rd_rsp_valid)
  ,.cvif2sdp_rd_rsp_ready          (cvif2sdp_rd_rsp_ready)
  ,.cvif2sdp_rd_rsp_pd             (cvif2sdp_rd_rsp_pd[513:0])
  ,.cvif2sdp_wr_rsp_complete       (cvif2sdp_wr_rsp_complete)
  ,.mcif2sdp_b_rd_rsp_valid        (mcif2sdp_b_rd_rsp_valid)
  ,.mcif2sdp_b_rd_rsp_ready        (mcif2sdp_b_rd_rsp_ready)
  ,.mcif2sdp_b_rd_rsp_pd           (mcif2sdp_b_rd_rsp_pd[513:0])
  ,.mcif2sdp_e_rd_rsp_valid        (mcif2sdp_e_rd_rsp_valid)
  ,.mcif2sdp_e_rd_rsp_ready        (mcif2sdp_e_rd_rsp_ready)
  ,.mcif2sdp_e_rd_rsp_pd           (mcif2sdp_e_rd_rsp_pd[513:0])
  ,.mcif2sdp_n_rd_rsp_valid        (mcif2sdp_n_rd_rsp_valid)
  ,.mcif2sdp_n_rd_rsp_ready        (mcif2sdp_n_rd_rsp_ready)
  ,.mcif2sdp_n_rd_rsp_pd           (mcif2sdp_n_rd_rsp_pd[513:0])
  ,.mcif2sdp_rd_rsp_valid          (mcif2sdp_rd_rsp_valid)
  ,.mcif2sdp_rd_rsp_ready          (mcif2sdp_rd_rsp_ready)
  ,.mcif2sdp_rd_rsp_pd             (mcif2sdp_rd_rsp_pd[513:0])
  ,.mcif2sdp_wr_rsp_complete       (mcif2sdp_wr_rsp_complete)
  ,.pwrbus_ram_pd                  (pwrbus_ram_pd[31:0])
  ,.sdp2csb_resp_valid             (sdp2csb_resp_valid)
  ,.sdp2csb_resp_pd                (sdp2csb_resp_pd[33:0])
  ,.sdp2cvif_rd_cdt_lat_fifo_pop   (sdp2cvif_rd_cdt_lat_fifo_pop)
  ,.sdp2cvif_rd_req_valid          (sdp2cvif_rd_req_valid)
  ,.sdp2cvif_rd_req_ready          (sdp2cvif_rd_req_ready)
  ,.sdp2cvif_rd_req_pd             (sdp2cvif_rd_req_pd[78:0])
  ,.sdp2cvif_wr_req_valid          (sdp2cvif_wr_req_valid)
  ,.sdp2cvif_wr_req_ready          (sdp2cvif_wr_req_ready)
  ,.sdp2cvif_wr_req_pd             (sdp2cvif_wr_req_pd[514:0])
  ,.sdp2glb_done_intr_pd           (sdp2glb_done_intr_pd[1:0])
  ,.sdp2mcif_rd_cdt_lat_fifo_pop   (sdp2mcif_rd_cdt_lat_fifo_pop)
  ,.sdp2mcif_rd_req_valid          (sdp2mcif_rd_req_valid)
  ,.sdp2mcif_rd_req_ready          (sdp2mcif_rd_req_ready)
  ,.sdp2mcif_rd_req_pd             (sdp2mcif_rd_req_pd[78:0])
  ,.sdp2mcif_wr_req_valid          (sdp2mcif_wr_req_valid)
  ,.sdp2mcif_wr_req_ready          (sdp2mcif_wr_req_ready)
  ,.sdp2mcif_wr_req_pd             (sdp2mcif_wr_req_pd[514:0])
  ,.sdp2pdp_valid                  (sdp2pdp_valid)
  ,.sdp2pdp_ready                  (sdp2pdp_ready)
  ,.sdp2pdp_pd                     (sdp2pdp_pd[255:0])
  ,.sdp_b2cvif_rd_cdt_lat_fifo_pop (sdp_b2cvif_rd_cdt_lat_fifo_pop)
  ,.sdp_b2cvif_rd_req_valid        (sdp_b2cvif_rd_req_valid)
  ,.sdp_b2cvif_rd_req_ready        (sdp_b2cvif_rd_req_ready)
  ,.sdp_b2cvif_rd_req_pd           (sdp_b2cvif_rd_req_pd[78:0])
  ,.sdp_b2mcif_rd_cdt_lat_fifo_pop (sdp_b2mcif_rd_cdt_lat_fifo_pop)
  ,.sdp_b2mcif_rd_req_valid        (sdp_b2mcif_rd_req_valid)
  ,.sdp_b2mcif_rd_req_ready        (sdp_b2mcif_rd_req_ready)
  ,.sdp_b2mcif_rd_req_pd           (sdp_b2mcif_rd_req_pd[78:0])
  ,.sdp_e2cvif_rd_cdt_lat_fifo_pop (sdp_e2cvif_rd_cdt_lat_fifo_pop)
  ,.sdp_e2cvif_rd_req_valid        (sdp_e2cvif_rd_req_valid)
  ,.sdp_e2cvif_rd_req_ready        (sdp_e2cvif_rd_req_ready)
  ,.sdp_e2cvif_rd_req_pd           (sdp_e2cvif_rd_req_pd[78:0])
  ,.sdp_e2mcif_rd_cdt_lat_fifo_pop (sdp_e2mcif_rd_cdt_lat_fifo_pop)
  ,.sdp_e2mcif_rd_req_valid        (sdp_e2mcif_rd_req_valid)
  ,.sdp_e2mcif_rd_req_ready        (sdp_e2mcif_rd_req_ready)
  ,.sdp_e2mcif_rd_req_pd           (sdp_e2mcif_rd_req_pd[78:0])
  ,.sdp_n2cvif_rd_cdt_lat_fifo_pop (sdp_n2cvif_rd_cdt_lat_fifo_pop)
  ,.sdp_n2cvif_rd_req_valid        (sdp_n2cvif_rd_req_valid)
  ,.sdp_n2cvif_rd_req_ready        (sdp_n2cvif_rd_req_ready)
  ,.sdp_n2cvif_rd_req_pd           (sdp_n2cvif_rd_req_pd[78:0])
  ,.sdp_n2mcif_rd_cdt_lat_fifo_pop (sdp_n2mcif_rd_cdt_lat_fifo_pop)
  ,.sdp_n2mcif_rd_req_valid        (sdp_n2mcif_rd_req_valid)
  ,.sdp_n2mcif_rd_req_ready        (sdp_n2mcif_rd_req_ready)
  ,.sdp_n2mcif_rd_req_pd           (sdp_n2mcif_rd_req_pd[78:0])
  ,.sdp_rdma2csb_resp_valid        (sdp_rdma2csb_resp_valid)
  ,.sdp_rdma2csb_resp_pd           (sdp_rdma2csb_resp_pd[33:0])
  ,.dla_clk_ovr_on_sync            (dla_clk_ovr_on_sync)
  ,.global_clk_ovr_on_sync         (global_clk_ovr_on_sync)
  ,.tmc2slcg_disable_clock_gating  (tmc2slcg_disable_clock_gating)
  );








NV_NVDLA_RT_cmac_a2cacc u_NV_NVDLA_RT_cmac_a2cacc (
   .nvdla_core_clk                 (nvdla_core_clk)
  ,.nvdla_core_rstn                (nvdla_core_rstn)
  ,.mac2accu_src_pvld              (mac_a2accu_src_pvld)
  ,.mac2accu_src_mask              (mac_a2accu_src_mask[7:0])
  ,.mac2accu_src_mode              (mac_a2accu_src_mode[7:0])
  ,.mac2accu_src_data0             (mac_a2accu_src_data0[175:0])
  ,.mac2accu_src_data1             (mac_a2accu_src_data1[175:0])
  ,.mac2accu_src_data2             (mac_a2accu_src_data2[175:0])
  ,.mac2accu_src_data3             (mac_a2accu_src_data3[175:0])
  ,.mac2accu_src_data4             (mac_a2accu_src_data4[175:0])
  ,.mac2accu_src_data5             (mac_a2accu_src_data5[175:0])
  ,.mac2accu_src_data6             (mac_a2accu_src_data6[175:0])
  ,.mac2accu_src_data7             (mac_a2accu_src_data7[175:0])
  ,.mac2accu_src_pd                (mac_a2accu_src_pd[8:0])
  ,.mac2accu_dst_pvld              (mac_a2accu_dst_pvld)
  ,.mac2accu_dst_mask              (mac_a2accu_dst_mask[7:0])
  ,.mac2accu_dst_mode              (mac_a2accu_dst_mode[7:0])
  ,.mac2accu_dst_data0             (mac_a2accu_dst_data0[175:0])
  ,.mac2accu_dst_data1             (mac_a2accu_dst_data1[175:0])
  ,.mac2accu_dst_data2             (mac_a2accu_dst_data2[175:0])
  ,.mac2accu_dst_data3             (mac_a2accu_dst_data3[175:0])
  ,.mac2accu_dst_data4             (mac_a2accu_dst_data4[175:0])
  ,.mac2accu_dst_data5             (mac_a2accu_dst_data5[175:0])
  ,.mac2accu_dst_data6             (mac_a2accu_dst_data6[175:0])
  ,.mac2accu_dst_data7             (mac_a2accu_dst_data7[175:0])
  ,.mac2accu_dst_pd                (mac_a2accu_dst_pd[8:0])
  );















endmodule
module NV_NVDLA_partition_p (
   cacc2sdp_pd
  ,cacc2sdp_valid
  ,csb2sdp_rdma_req_pd
  ,csb2sdp_rdma_req_pvld
  ,csb2sdp_req_pd
  ,csb2sdp_req_pvld
  ,cvif2sdp_b_rd_rsp_pd
  ,cvif2sdp_b_rd_rsp_valid
  ,cvif2sdp_e_rd_rsp_pd
  ,cvif2sdp_e_rd_rsp_valid
  ,cvif2sdp_n_rd_rsp_pd
  ,cvif2sdp_n_rd_rsp_valid
  ,cvif2sdp_rd_rsp_pd
  ,cvif2sdp_rd_rsp_valid
  ,cvif2sdp_wr_rsp_complete
  ,direct_reset_
  ,dla_reset_rstn
  ,global_clk_ovr_on
  ,mac_a2accu_src_data0
  ,mac_a2accu_src_data1
  ,mac_a2accu_src_data2
  ,mac_a2accu_src_data3
  ,mac_a2accu_src_data4
  ,mac_a2accu_src_data5
  ,mac_a2accu_src_data6
  ,mac_a2accu_src_data7
  ,mac_a2accu_src_mask
  ,mac_a2accu_src_mode
  ,mac_a2accu_src_pd
  ,mac_a2accu_src_pvld
  ,mcif2sdp_b_rd_rsp_pd
  ,mcif2sdp_b_rd_rsp_valid
  ,mcif2sdp_e_rd_rsp_pd
  ,mcif2sdp_e_rd_rsp_valid
  ,mcif2sdp_n_rd_rsp_pd
  ,mcif2sdp_n_rd_rsp_valid
  ,mcif2sdp_rd_rsp_pd
  ,mcif2sdp_rd_rsp_valid
  ,mcif2sdp_wr_rsp_complete
  ,nvdla_clk_ovr_on
  ,nvdla_core_clk
  ,pwrbus_ram_pd
  ,sdp2cvif_rd_req_ready
  ,sdp2cvif_wr_req_ready
  ,sdp2mcif_rd_req_ready
  ,sdp2mcif_wr_req_ready
  ,sdp2pdp_ready
  ,sdp_b2cvif_rd_req_ready
  ,sdp_b2mcif_rd_req_ready
  ,sdp_e2cvif_rd_req_ready
  ,sdp_e2mcif_rd_req_ready
  ,sdp_n2cvif_rd_req_ready
  ,sdp_n2mcif_rd_req_ready
  ,test_mode
  ,tmc2slcg_disable_clock_gating
  ,cacc2sdp_ready
  ,csb2sdp_rdma_req_prdy
  ,csb2sdp_req_prdy
  ,cvif2sdp_b_rd_rsp_ready
  ,cvif2sdp_e_rd_rsp_ready
  ,cvif2sdp_n_rd_rsp_ready
  ,cvif2sdp_rd_rsp_ready
  ,mac_a2accu_dst_data0
  ,mac_a2accu_dst_data1
  ,mac_a2accu_dst_data2
  ,mac_a2accu_dst_data3
  ,mac_a2accu_dst_data4
  ,mac_a2accu_dst_data5
  ,mac_a2accu_dst_data6
  ,mac_a2accu_dst_data7
  ,mac_a2accu_dst_mask
  ,mac_a2accu_dst_mode
  ,mac_a2accu_dst_pd
  ,mac_a2accu_dst_pvld
  ,mcif2sdp_b_rd_rsp_ready
  ,mcif2sdp_e_rd_rsp_ready
  ,mcif2sdp_n_rd_rsp_ready
  ,mcif2sdp_rd_rsp_ready
  ,sdp2csb_resp_pd
  ,sdp2csb_resp_valid
  ,sdp2cvif_rd_cdt_lat_fifo_pop
  ,sdp2cvif_rd_req_pd
  ,sdp2cvif_rd_req_valid
  ,sdp2cvif_wr_req_pd
  ,sdp2cvif_wr_req_valid
  ,sdp2glb_done_intr_pd
  ,sdp2mcif_rd_cdt_lat_fifo_pop
  ,sdp2mcif_rd_req_pd
  ,sdp2mcif_rd_req_valid
  ,sdp2mcif_wr_req_pd
  ,sdp2mcif_wr_req_valid
  ,sdp2pdp_pd
  ,sdp2pdp_valid
  ,sdp_b2cvif_rd_cdt_lat_fifo_pop
  ,sdp_b2cvif_rd_req_pd
  ,sdp_b2cvif_rd_req_valid
  ,sdp_b2mcif_rd_cdt_lat_fifo_pop
  ,sdp_b2mcif_rd_req_pd
  ,sdp_b2mcif_rd_req_valid
  ,sdp_e2cvif_rd_cdt_lat_fifo_pop
  ,sdp_e2cvif_rd_req_pd
  ,sdp_e2cvif_rd_req_valid
  ,sdp_e2mcif_rd_cdt_lat_fifo_pop
  ,sdp_e2mcif_rd_req_pd
  ,sdp_e2mcif_rd_req_valid
  ,sdp_n2cvif_rd_cdt_lat_fifo_pop
  ,sdp_n2cvif_rd_req_pd
  ,sdp_n2cvif_rd_req_valid
  ,sdp_n2mcif_rd_cdt_lat_fifo_pop
  ,sdp_n2mcif_rd_req_pd
  ,sdp_n2mcif_rd_req_valid
  ,sdp_rdma2csb_resp_pd
  ,sdp_rdma2csb_resp_valid
  );






input  test_mode;
input  direct_reset_;

input  global_clk_ovr_on;
input  tmc2slcg_disable_clock_gating;

input          cacc2sdp_valid;
output         cacc2sdp_ready;
input  [513:0] cacc2sdp_pd;

input         csb2sdp_rdma_req_pvld;
output        csb2sdp_rdma_req_prdy;
input  [62:0] csb2sdp_rdma_req_pd;

input         csb2sdp_req_pvld;
output        csb2sdp_req_prdy;
input  [62:0] csb2sdp_req_pd;

input          cvif2sdp_b_rd_rsp_valid;
output         cvif2sdp_b_rd_rsp_ready;
input  [513:0] cvif2sdp_b_rd_rsp_pd;

input          cvif2sdp_e_rd_rsp_valid;
output         cvif2sdp_e_rd_rsp_ready;
input  [513:0] cvif2sdp_e_rd_rsp_pd;

input          cvif2sdp_n_rd_rsp_valid;
output         cvif2sdp_n_rd_rsp_ready;
input  [513:0] cvif2sdp_n_rd_rsp_pd;

input          cvif2sdp_rd_rsp_valid;
output         cvif2sdp_rd_rsp_ready;
input  [513:0] cvif2sdp_rd_rsp_pd;

input  cvif2sdp_wr_rsp_complete;

output         mac_a2accu_dst_pvld;
output   [7:0] mac_a2accu_dst_mask;
output   [7:0] mac_a2accu_dst_mode;
output [175:0] mac_a2accu_dst_data0;
output [175:0] mac_a2accu_dst_data1;
output [175:0] mac_a2accu_dst_data2;
output [175:0] mac_a2accu_dst_data3;
output [175:0] mac_a2accu_dst_data4;
output [175:0] mac_a2accu_dst_data5;
output [175:0] mac_a2accu_dst_data6;
output [175:0] mac_a2accu_dst_data7;
output   [8:0] mac_a2accu_dst_pd;

input         mac_a2accu_src_pvld;
input   [7:0] mac_a2accu_src_mask;
input   [7:0] mac_a2accu_src_mode;
input [175:0] mac_a2accu_src_data0;
input [175:0] mac_a2accu_src_data1;
input [175:0] mac_a2accu_src_data2;
input [175:0] mac_a2accu_src_data3;
input [175:0] mac_a2accu_src_data4;
input [175:0] mac_a2accu_src_data5;
input [175:0] mac_a2accu_src_data6;
input [175:0] mac_a2accu_src_data7;
input   [8:0] mac_a2accu_src_pd;

input          mcif2sdp_b_rd_rsp_valid;
output         mcif2sdp_b_rd_rsp_ready;
input  [513:0] mcif2sdp_b_rd_rsp_pd;

input          mcif2sdp_e_rd_rsp_valid;
output         mcif2sdp_e_rd_rsp_ready;
input  [513:0] mcif2sdp_e_rd_rsp_pd;

input          mcif2sdp_n_rd_rsp_valid;
output         mcif2sdp_n_rd_rsp_ready;
input  [513:0] mcif2sdp_n_rd_rsp_pd;

input          mcif2sdp_rd_rsp_valid;
output         mcif2sdp_rd_rsp_ready;
input  [513:0] mcif2sdp_rd_rsp_pd;

input  mcif2sdp_wr_rsp_complete;

input [31:0] pwrbus_ram_pd;

output        sdp2csb_resp_valid;
output [33:0] sdp2csb_resp_pd;

output  sdp2cvif_rd_cdt_lat_fifo_pop;

output        sdp2cvif_rd_req_valid;
input         sdp2cvif_rd_req_ready;
output [78:0] sdp2cvif_rd_req_pd;

output         sdp2cvif_wr_req_valid;
input          sdp2cvif_wr_req_ready;
output [514:0] sdp2cvif_wr_req_pd;

output [1:0] sdp2glb_done_intr_pd;

output  sdp2mcif_rd_cdt_lat_fifo_pop;

output        sdp2mcif_rd_req_valid;
input         sdp2mcif_rd_req_ready;
output [78:0] sdp2mcif_rd_req_pd;

output         sdp2mcif_wr_req_valid;
input          sdp2mcif_wr_req_ready;
output [514:0] sdp2mcif_wr_req_pd;

output         sdp2pdp_valid;
input          sdp2pdp_ready;
output [255:0] sdp2pdp_pd;

output  sdp_b2cvif_rd_cdt_lat_fifo_pop;

output        sdp_b2cvif_rd_req_valid;
input         sdp_b2cvif_rd_req_ready;
output [78:0] sdp_b2cvif_rd_req_pd;

output  sdp_b2mcif_rd_cdt_lat_fifo_pop;

output        sdp_b2mcif_rd_req_valid;
input         sdp_b2mcif_rd_req_ready;
output [78:0] sdp_b2mcif_rd_req_pd;

output  sdp_e2cvif_rd_cdt_lat_fifo_pop;

output        sdp_e2cvif_rd_req_valid;
input         sdp_e2cvif_rd_req_ready;
output [78:0] sdp_e2cvif_rd_req_pd;

output  sdp_e2mcif_rd_cdt_lat_fifo_pop;

output        sdp_e2mcif_rd_req_valid;
input         sdp_e2mcif_rd_req_ready;
output [78:0] sdp_e2mcif_rd_req_pd;

output  sdp_n2cvif_rd_cdt_lat_fifo_pop;

output        sdp_n2cvif_rd_req_valid;
input         sdp_n2cvif_rd_req_ready;
output [78:0] sdp_n2cvif_rd_req_pd;

output  sdp_n2mcif_rd_cdt_lat_fifo_pop;

output        sdp_n2mcif_rd_req_valid;
input         sdp_n2mcif_rd_req_ready;
output [78:0] sdp_n2mcif_rd_req_pd;

output        sdp_rdma2csb_resp_valid;
output [33:0] sdp_rdma2csb_resp_pd;




input  nvdla_core_clk;     
input  dla_reset_rstn;     

input  nvdla_clk_ovr_on;

wire   dla_clk_ovr_on_sync;
wire   global_clk_ovr_on_sync;
wire   nvdla_core_rstn;




NV_NVDLA_reset u_partition_p_reset (
   .dla_reset_rstn                 (dla_reset_rstn)
  ,.direct_reset_                  (direct_reset_)
  ,.test_mode                      (test_mode)
  ,.synced_rstn                    (nvdla_core_rstn)
  ,.nvdla_clk                      (nvdla_core_clk)
  );




NV_NVDLA_sync3d u_dla_clk_ovr_on_sync (
   .clk                            (nvdla_core_clk)
  ,.sync_i                         (nvdla_clk_ovr_on)
  ,.sync_o                         (dla_clk_ovr_on_sync)
  );

NV_NVDLA_sync3d_s u_global_clk_ovr_on_sync (
   .clk                            (nvdla_core_clk)
  ,.prst                           (nvdla_core_rstn)
  ,.sync_i                         (global_clk_ovr_on)
  ,.sync_o                         (global_clk_ovr_on_sync)
  );




NV_NVDLA_sdp u_NV_NVDLA_sdp (
   .nvdla_core_clk                 (nvdla_core_clk)
  ,.nvdla_core_rstn                (nvdla_core_rstn)
  ,.cacc2sdp_valid                 (cacc2sdp_valid)
  ,.cacc2sdp_ready                 (cacc2sdp_ready)
  ,.cacc2sdp_pd                    (cacc2sdp_pd[513:0])
  ,.csb2sdp_rdma_req_pvld          (csb2sdp_rdma_req_pvld)
  ,.csb2sdp_rdma_req_prdy          (csb2sdp_rdma_req_prdy)
  ,.csb2sdp_rdma_req_pd            (csb2sdp_rdma_req_pd[62:0])
  ,.csb2sdp_req_pvld               (csb2sdp_req_pvld)
  ,.csb2sdp_req_prdy               (csb2sdp_req_prdy)
  ,.csb2sdp_req_pd                 (csb2sdp_req_pd[62:0])
  ,.cvif2sdp_b_rd_rsp_valid        (cvif2sdp_b_rd_rsp_valid)
  ,.cvif2sdp_b_rd_rsp_ready        (cvif2sdp_b_rd_rsp_ready)
  ,.cvif2sdp_b_rd_rsp_pd           (cvif2sdp_b_rd_rsp_pd[513:0])
  ,.cvif2sdp_e_rd_rsp_valid        (cvif2sdp_e_rd_rsp_valid)
  ,.cvif2sdp_e_rd_rsp_ready        (cvif2sdp_e_rd_rsp_ready)
  ,.cvif2sdp_e_rd_rsp_pd           (cvif2sdp_e_rd_rsp_pd[513:0])
  ,.cvif2sdp_n_rd_rsp_valid        (cvif2sdp_n_rd_rsp_valid)
  ,.cvif2sdp_n_rd_rsp_ready        (cvif2sdp_n_rd_rsp_ready)
  ,.cvif2sdp_n_rd_rsp_pd           (cvif2sdp_n_rd_rsp_pd[513:0])
  ,.cvif2sdp_rd_rsp_valid          (cvif2sdp_rd_rsp_valid)
  ,.cvif2sdp_rd_rsp_ready          (cvif2sdp_rd_rsp_ready)
  ,.cvif2sdp_rd_rsp_pd             (cvif2sdp_rd_rsp_pd[513:0])
  ,.cvif2sdp_wr_rsp_complete       (cvif2sdp_wr_rsp_complete)
  ,.mcif2sdp_b_rd_rsp_valid        (mcif2sdp_b_rd_rsp_valid)
  ,.mcif2sdp_b_rd_rsp_ready        (mcif2sdp_b_rd_rsp_ready)
  ,.mcif2sdp_b_rd_rsp_pd           (mcif2sdp_b_rd_rsp_pd[513:0])
  ,.mcif2sdp_e_rd_rsp_valid        (mcif2sdp_e_rd_rsp_valid)
  ,.mcif2sdp_e_rd_rsp_ready        (mcif2sdp_e_rd_rsp_ready)
  ,.mcif2sdp_e_rd_rsp_pd           (mcif2sdp_e_rd_rsp_pd[513:0])
  ,.mcif2sdp_n_rd_rsp_valid        (mcif2sdp_n_rd_rsp_valid)
  ,.mcif2sdp_n_rd_rsp_ready        (mcif2sdp_n_rd_rsp_ready)
  ,.mcif2sdp_n_rd_rsp_pd           (mcif2sdp_n_rd_rsp_pd[513:0])
  ,.mcif2sdp_rd_rsp_valid          (mcif2sdp_rd_rsp_valid)
  ,.mcif2sdp_rd_rsp_ready          (mcif2sdp_rd_rsp_ready)
  ,.mcif2sdp_rd_rsp_pd             (mcif2sdp_rd_rsp_pd[513:0])
  ,.mcif2sdp_wr_rsp_complete       (mcif2sdp_wr_rsp_complete)
  ,.pwrbus_ram_pd                  (pwrbus_ram_pd[31:0])
  ,.sdp2csb_resp_valid             (sdp2csb_resp_valid)
  ,.sdp2csb_resp_pd                (sdp2csb_resp_pd[33:0])
  ,.sdp2cvif_rd_cdt_lat_fifo_pop   (sdp2cvif_rd_cdt_lat_fifo_pop)
  ,.sdp2cvif_rd_req_valid          (sdp2cvif_rd_req_valid)
  ,.sdp2cvif_rd_req_ready          (sdp2cvif_rd_req_ready)
  ,.sdp2cvif_rd_req_pd             (sdp2cvif_rd_req_pd[78:0])
  ,.sdp2cvif_wr_req_valid          (sdp2cvif_wr_req_valid)
  ,.sdp2cvif_wr_req_ready          (sdp2cvif_wr_req_ready)
  ,.sdp2cvif_wr_req_pd             (sdp2cvif_wr_req_pd[514:0])
  ,.sdp2glb_done_intr_pd           (sdp2glb_done_intr_pd[1:0])
  ,.sdp2mcif_rd_cdt_lat_fifo_pop   (sdp2mcif_rd_cdt_lat_fifo_pop)
  ,.sdp2mcif_rd_req_valid          (sdp2mcif_rd_req_valid)
  ,.sdp2mcif_rd_req_ready          (sdp2mcif_rd_req_ready)
  ,.sdp2mcif_rd_req_pd             (sdp2mcif_rd_req_pd[78:0])
  ,.sdp2mcif_wr_req_valid          (sdp2mcif_wr_req_valid)
  ,.sdp2mcif_wr_req_ready          (sdp2mcif_wr_req_ready)
  ,.sdp2mcif_wr_req_pd             (sdp2mcif_wr_req_pd[514:0])
  ,.sdp2pdp_valid                  (sdp2pdp_valid)
  ,.sdp2pdp_ready                  (sdp2pdp_ready)
  ,.sdp2pdp_pd                     (sdp2pdp_pd[255:0])
  ,.sdp_b2cvif_rd_cdt_lat_fifo_pop (sdp_b2cvif_rd_cdt_lat_fifo_pop)
  ,.sdp_b2cvif_rd_req_valid        (sdp_b2cvif_rd_req_valid)
  ,.sdp_b2cvif_rd_req_ready        (sdp_b2cvif_rd_req_ready)
  ,.sdp_b2cvif_rd_req_pd           (sdp_b2cvif_rd_req_pd[78:0])
  ,.sdp_b2mcif_rd_cdt_lat_fifo_pop (sdp_b2mcif_rd_cdt_lat_fifo_pop)
  ,.sdp_b2mcif_rd_req_valid        (sdp_b2mcif_rd_req_valid)
  ,.sdp_b2mcif_rd_req_ready        (sdp_b2mcif_rd_req_ready)
  ,.sdp_b2mcif_rd_req_pd           (sdp_b2mcif_rd_req_pd[78:0])
  ,.sdp_e2cvif_rd_cdt_lat_fifo_pop (sdp_e2cvif_rd_cdt_lat_fifo_pop)
  ,.sdp_e2cvif_rd_req_valid        (sdp_e2cvif_rd_req_valid)
  ,.sdp_e2cvif_rd_req_ready        (sdp_e2cvif_rd_req_ready)
  ,.sdp_e2cvif_rd_req_pd           (sdp_e2cvif_rd_req_pd[78:0])
  ,.sdp_e2mcif_rd_cdt_lat_fifo_pop (sdp_e2mcif_rd_cdt_lat_fifo_pop)
  ,.sdp_e2mcif_rd_req_valid        (sdp_e2mcif_rd_req_valid)
  ,.sdp_e2mcif_rd_req_ready        (sdp_e2mcif_rd_req_ready)
  ,.sdp_e2mcif_rd_req_pd           (sdp_e2mcif_rd_req_pd[78:0])
  ,.sdp_n2cvif_rd_cdt_lat_fifo_pop (sdp_n2cvif_rd_cdt_lat_fifo_pop)
  ,.sdp_n2cvif_rd_req_valid        (sdp_n2cvif_rd_req_valid)
  ,.sdp_n2cvif_rd_req_ready        (sdp_n2cvif_rd_req_ready)
  ,.sdp_n2cvif_rd_req_pd           (sdp_n2cvif_rd_req_pd[78:0])
  ,.sdp_n2mcif_rd_cdt_lat_fifo_pop (sdp_n2mcif_rd_cdt_lat_fifo_pop)
  ,.sdp_n2mcif_rd_req_valid        (sdp_n2mcif_rd_req_valid)
  ,.sdp_n2mcif_rd_req_ready        (sdp_n2mcif_rd_req_ready)
  ,.sdp_n2mcif_rd_req_pd           (sdp_n2mcif_rd_req_pd[78:0])
  ,.sdp_rdma2csb_resp_valid        (sdp_rdma2csb_resp_valid)
  ,.sdp_rdma2csb_resp_pd           (sdp_rdma2csb_resp_pd[33:0])
  ,.dla_clk_ovr_on_sync            (dla_clk_ovr_on_sync)
  ,.global_clk_ovr_on_sync         (global_clk_ovr_on_sync)
  ,.tmc2slcg_disable_clock_gating  (tmc2slcg_disable_clock_gating)
  );








NV_NVDLA_RT_cmac_a2cacc u_NV_NVDLA_RT_cmac_a2cacc (
   .nvdla_core_clk                 (nvdla_core_clk)
  ,.nvdla_core_rstn                (nvdla_core_rstn)
  ,.mac2accu_src_pvld              (mac_a2accu_src_pvld)
  ,.mac2accu_src_mask              (mac_a2accu_src_mask[7:0])
  ,.mac2accu_src_mode              (mac_a2accu_src_mode[7:0])
  ,.mac2accu_src_data0             (mac_a2accu_src_data0[175:0])
  ,.mac2accu_src_data1             (mac_a2accu_src_data1[175:0])
  ,.mac2accu_src_data2             (mac_a2accu_src_data2[175:0])
  ,.mac2accu_src_data3             (mac_a2accu_src_data3[175:0])
  ,.mac2accu_src_data4             (mac_a2accu_src_data4[175:0])
  ,.mac2accu_src_data5             (mac_a2accu_src_data5[175:0])
  ,.mac2accu_src_data6             (mac_a2accu_src_data6[175:0])
  ,.mac2accu_src_data7             (mac_a2accu_src_data7[175:0])
  ,.mac2accu_src_pd                (mac_a2accu_src_pd[8:0])
  ,.mac2accu_dst_pvld              (mac_a2accu_dst_pvld)
  ,.mac2accu_dst_mask              (mac_a2accu_dst_mask[7:0])
  ,.mac2accu_dst_mode              (mac_a2accu_dst_mode[7:0])
  ,.mac2accu_dst_data0             (mac_a2accu_dst_data0[175:0])
  ,.mac2accu_dst_data1             (mac_a2accu_dst_data1[175:0])
  ,.mac2accu_dst_data2             (mac_a2accu_dst_data2[175:0])
  ,.mac2accu_dst_data3             (mac_a2accu_dst_data3[175:0])
  ,.mac2accu_dst_data4             (mac_a2accu_dst_data4[175:0])
  ,.mac2accu_dst_data5             (mac_a2accu_dst_data5[175:0])
  ,.mac2accu_dst_data6             (mac_a2accu_dst_data6[175:0])
  ,.mac2accu_dst_data7             (mac_a2accu_dst_data7[175:0])
  ,.mac2accu_dst_pd                (mac_a2accu_dst_pd[8:0])
  );















endmodule