data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/pm_rocket.v
1: b'%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/pm_rocket.v:3: Cannot find include file: noc_parameter.vh\n    `include "noc_parameter.vh" \n             ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh\n             data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.v\n             data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog,data/full_repos/permissive/463204869/noc_parameter.vh.sv\n             noc_parameter.vh\n             noc_parameter.vh.v\n             noc_parameter.vh.sv\n             obj_dir/noc_parameter.vh\n             obj_dir/noc_parameter.vh.v\n             obj_dir/noc_parameter.vh.sv\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/pm_rocket.v:4: syntax error, unexpected \',\', expecting \'[\'\n    ,parameter HOME_MODID = {NOC_MODID_SIZE{1\'b0}},\n    ^\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/pm_rocket.v:5: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter CLKFREQ_MHZ = 100\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/pm_rocket.v:6: syntax error, unexpected \')\', expecting \';\'\n)\n^\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/pm_rocket.v:9: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                                     reset_pm_n_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/pm_rocket.v:10: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire               [NOC_CHIPID_SIZE-1:0] home_chipid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/pm_rocket.v:11: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire               [NOC_CHIPID_SIZE-1:0] host_chipid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/pm_rocket.v:12: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire    [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] noc_fifo_pm_in_data_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/pm_rocket.v:13: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire           [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_pm_in_raddr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/pm_rocket.v:14: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire           [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_pm_in_waddr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/pm_rocket.v:15: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire    [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] noc_fifo_pm_out_data_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/pm_rocket.v:16: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire           [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_pm_out_raddr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/pm_rocket.v:17: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire           [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_pm_out_waddr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/pm_rocket.v:19: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire                                      jtag_tck_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/pm_rocket.v:20: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire                                      jtag_tms_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/pm_rocket.v:21: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input wire                                      jtag_tdi_i,\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/pm_rocket.v:22: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                                     jtag_tdo_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/pm_rocket.v:23: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                                     jtag_tdo_en_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/pm_rocket.v:25: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output wire                                     uart_tx_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/pm_rocket.v:26: syntax error, unexpected input, expecting IDENTIFIER or do or final\n    input  wire                                     uart_rx_i\n    ^~~~~\n%Error: data/full_repos/permissive/463204869/units/rocket/source/rtl/verilog/pm_rocket.v:36: syntax error, unexpected IDENTIFIER\nrocket_wrap #(\n^~~~~~~~~~~\n%Error: Exiting due to 21 error(s)\n'
module pm_rocket #(
    `include "noc_parameter.vh"
    ,parameter HOME_MODID = {NOC_MODID_SIZE{1'b0}},
    parameter CLKFREQ_MHZ = 100
)
(
    input  wire                                     clk_pm_i,
    input  wire                                     reset_pm_n_i,
    input  wire               [NOC_CHIPID_SIZE-1:0] home_chipid_i,
    input  wire               [NOC_CHIPID_SIZE-1:0] host_chipid_i,
    input  wire    [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] noc_fifo_pm_in_data_i,
    output wire           [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_pm_in_raddr_o,
    input  wire           [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_pm_in_waddr_i,
    output wire    [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] noc_fifo_pm_out_data_o,
    input  wire           [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_pm_out_raddr_i,
    output wire           [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_pm_out_waddr_o,

    input wire                                      jtag_tck_i,
    input wire                                      jtag_tms_i,
    input wire                                      jtag_tdi_i,
    output wire                                     jtag_tdo_o,
    output wire                                     jtag_tdo_en_o,

    output wire                                     uart_tx_o,
    input  wire                                     uart_rx_i
);

    wire reset_sync_n_s;

    wire [NOC_CHIPID_SIZE-1:0] home_chipid_s;
    wire [NOC_CHIPID_SIZE-1:0] host_chipid_s;



rocket_wrap #(
    .HOME_MODID                 (HOME_MODID),
    .CLKFREQ_MHZ                (CLKFREQ_MHZ)
) i_rocket_wrap (
    .clk_pm_i                   (clk_pm_i),
    .reset_pm_n_i               (reset_sync_n_s),
    .home_chipid_i              (home_chipid_s),
    .host_chipid_i              (host_chipid_s),
    .noc_fifo_pm_in_data_i      (noc_fifo_pm_in_data_i),
    .noc_fifo_pm_in_raddr_o     (noc_fifo_pm_in_raddr_o),
    .noc_fifo_pm_in_waddr_i     (noc_fifo_pm_in_waddr_i),
    .noc_fifo_pm_out_data_o     (noc_fifo_pm_out_data_o),
    .noc_fifo_pm_out_raddr_i    (noc_fifo_pm_out_raddr_i),
    .noc_fifo_pm_out_waddr_o    (noc_fifo_pm_out_waddr_o),

    .jtag_tck_i                 (jtag_tck_i),
    .jtag_tms_i                 (jtag_tms_i),
    .jtag_tdi_i                 (jtag_tdi_i),
    .jtag_tdo_o                 (jtag_tdo_o),
    .jtag_tdo_en_o              (jtag_tdo_en_o),

    .uart_tx_o                  (uart_tx_o),
    .uart_rx_i                  (uart_rx_i)
);

util_reset_sync i_util_reset_sync_ref (
    .clk_i(clk_pm_i),
    .reset_q_i(reset_pm_n_i),
    .scan_mode_i(1'b0),
    .sync_reset_q_o(reset_sync_n_s)
);

util_sync #(
    .WIDTH(NOC_CHIPID_SIZE)
) i_util_sync_host_chipid (
    .clk_i(clk_pm_i),
    .reset_n_i(reset_sync_n_s),
    .data_i(host_chipid_i),
    .data_o(host_chipid_s)
);

util_sync #(
    .WIDTH(NOC_CHIPID_SIZE)
) i_util_sync_home_chipid (
    .clk_i(clk_pm_i),
    .reset_n_i(reset_sync_n_s),
    .data_i(home_chipid_i),
    .data_o(home_chipid_s)
);


endmodule
module pm_rocket #(
    `include "noc_parameter.vh"
    ,parameter HOME_MODID = {NOC_MODID_SIZE{1'b0}},
    parameter CLKFREQ_MHZ = 100
)
(
    input  wire                                     clk_pm_i,
    input  wire                                     reset_pm_n_i,
    input  wire               [NOC_CHIPID_SIZE-1:0] home_chipid_i,
    input  wire               [NOC_CHIPID_SIZE-1:0] host_chipid_i,
    input  wire    [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] noc_fifo_pm_in_data_i,
    output wire           [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_pm_in_raddr_o,
    input  wire           [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_pm_in_waddr_i,
    output wire    [NOC_ASYNC_FIFO_PACKET_SIZE-1:0] noc_fifo_pm_out_data_o,
    input  wire           [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_pm_out_raddr_i,
    output wire           [NOC_ASYNC_FIFO_AWIDTH:0] noc_fifo_pm_out_waddr_o,

    input wire                                      jtag_tck_i,
    input wire                                      jtag_tms_i,
    input wire                                      jtag_tdi_i,
    output wire                                     jtag_tdo_o,
    output wire                                     jtag_tdo_en_o,

    output wire                                     uart_tx_o,
    input  wire                                     uart_rx_i
);


    wire reset_sync_n_s;

    wire [NOC_CHIPID_SIZE-1:0] home_chipid_s;
    wire [NOC_CHIPID_SIZE-1:0] host_chipid_s;



rocket_wrap #(
    .HOME_MODID                 (HOME_MODID),
    .CLKFREQ_MHZ                (CLKFREQ_MHZ)
) i_rocket_wrap (
    .clk_pm_i                   (clk_pm_i),
    .reset_pm_n_i               (reset_sync_n_s),
    .home_chipid_i              (home_chipid_s),
    .host_chipid_i              (host_chipid_s),
    .noc_fifo_pm_in_data_i      (noc_fifo_pm_in_data_i),
    .noc_fifo_pm_in_raddr_o     (noc_fifo_pm_in_raddr_o),
    .noc_fifo_pm_in_waddr_i     (noc_fifo_pm_in_waddr_i),
    .noc_fifo_pm_out_data_o     (noc_fifo_pm_out_data_o),
    .noc_fifo_pm_out_raddr_i    (noc_fifo_pm_out_raddr_i),
    .noc_fifo_pm_out_waddr_o    (noc_fifo_pm_out_waddr_o),

    .jtag_tck_i                 (jtag_tck_i),
    .jtag_tms_i                 (jtag_tms_i),
    .jtag_tdi_i                 (jtag_tdi_i),
    .jtag_tdo_o                 (jtag_tdo_o),
    .jtag_tdo_en_o              (jtag_tdo_en_o),

    .uart_tx_o                  (uart_tx_o),
    .uart_rx_i                  (uart_rx_i)
);

util_reset_sync i_util_reset_sync_ref (
    .clk_i(clk_pm_i),
    .reset_q_i(reset_pm_n_i),
    .scan_mode_i(1'b0),
    .sync_reset_q_o(reset_sync_n_s)
);

util_sync #(
    .WIDTH(NOC_CHIPID_SIZE)
) i_util_sync_host_chipid (
    .clk_i(clk_pm_i),
    .reset_n_i(reset_sync_n_s),
    .data_i(host_chipid_i),
    .data_o(host_chipid_s)
);

util_sync #(
    .WIDTH(NOC_CHIPID_SIZE)
) i_util_sync_home_chipid (
    .clk_i(clk_pm_i),
    .reset_n_i(reset_sync_n_s),
    .data_i(home_chipid_i),
    .data_o(home_chipid_s)
);


endmodule