data/full_repos/permissive/416231581/sylap.srcs/sources_1/new/uart_commands.v
1: b'%Warning-WIDTH: data/full_repos/permissive/416231581/sylap.srcs/sources_1/new/uart_commands.v:33: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'ha\' generates 7 bits.\n                                                                                                : ... In instance uart_commands\n    reg [7:0] laserCountsMax_reg=7\'d10;\n                                 ^~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/416231581/sylap.srcs/sources_1/new/uart_commands.v:104: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 16 bits.\n                                                                                                 : ... In instance uart_commands\n                                                   pulseOffset_reg<={uartRxData_store[2],uartRxData_store[1]};\n                                                                  ^~\n%Warning-WIDTH: data/full_repos/permissive/416231581/sylap.srcs/sources_1/new/uart_commands.v:109: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 16 bits.\n                                                                                                 : ... In instance uart_commands\n                                                   pulseLength_reg <= {uartRxData_store[2],uartRxData_store[1]};\n                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/416231581/sylap.srcs/sources_1/new/uart_commands.v:110: Operator ADD expects 32 bits on the RHS, but RHS\'s REPLICATE generates 16 bits.\n                                                                                                 : ... In instance uart_commands\n                                                   pulseOffsetPlusLength_reg<=(pulseOffset_reg+{uartRxData_store[2],uartRxData_store[1]});\n                                                                                              ^\n%Warning-WIDTH: data/full_repos/permissive/416231581/sylap.srcs/sources_1/new/uart_commands.v:114: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 16 bits.\n                                                                                                 : ... In instance uart_commands\n                                                   laserLengthHalf_reg<={uartRxData_store[2],uartRxData_store[1]};\n                                                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/416231581/sylap.srcs/sources_1/new/uart_commands.v:118: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                                 : ... In instance uart_commands\n                                                   laserCountsMax_reg<={24\'d0,uartRxData_store[1]};\n                                                                     ^~\n%Warning-WIDTH: data/full_repos/permissive/416231581/sylap.srcs/sources_1/new/uart_commands.v:146: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'ha\' generates 7 bits.\n                                                                                                 : ... In instance uart_commands\n                                                                   laserCountsMax_reg <= 7\'d10;\n                                                                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/416231581/sylap.srcs/sources_1/new/uart_commands.v:152: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 16 bits.\n                                                                                                 : ... In instance uart_commands\n                                                                         pulseOffset_reg <= {uartRxData_store[3],uartRxData_store[2]};\n                                                                                         ^~\n%Warning-WIDTH: data/full_repos/permissive/416231581/sylap.srcs/sources_1/new/uart_commands.v:153: Operator ADD expects 32 bits on the LHS, but LHS\'s REPLICATE generates 16 bits.\n                                                                                                 : ... In instance uart_commands\n                                                                         pulseOffsetPlusLength_reg<=({uartRxData_store[3],uartRxData_store[2]})+(pulseLength_reg);\n                                                                                                                                               ^\n%Warning-WIDTH: data/full_repos/permissive/416231581/sylap.srcs/sources_1/new/uart_commands.v:163: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s ADD generates 6 bits.\n                                                                                                 : ... In instance uart_commands\n                                                                                fineDelay1_reg<={1\'d0,uartRxData_store[1][7:3]}+{4\'d0,uartRxData_store[1][2]};\n                                                                                              ^~\n%Warning-WIDTH: data/full_repos/permissive/416231581/sylap.srcs/sources_1/new/uart_commands.v:164: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 6 bits.\n                                                                                                 : ... In instance uart_commands\n                                                                                fineDelay2_reg<={1\'d0,uartRxData_store[1][7:3]};\n                                                                                              ^~\n%Error: Exiting due to 11 warning(s)\n'
module uart_commands(
    input        clk_50,
    input        reset,
    input        UartRxDV,
    input  [7:0] uartRxData,
    output enableGenerator,
    output [31:0]pulseLength,
    output [31:0]pulseOffset,
    output [31:0]pulseOffsetPlusLength,
    output [31:0]laserLengthHalf,
    output [7:0] laserCountsMax,
    output [7:0] lastValidValue,
    output [4:0] fineDelay1,
    output [4:0] fineDelay2,
    output [4:0] fineDelay3, 
    output resetCmd
    );
    
    reg [31:0]pulseLength_reg=32'd100;
    reg [31:0]pulseOffset_reg=32'd100;
    reg [31:0]pulseOffsetPlusLength_reg=32'd102;
    reg [31:0]laserLengthHalf_reg=32'd4000;
    reg [7:0] laserCountsMax_reg=7'd10;
    reg [4:0] fineDelay1_reg=5'd0;
    reg [4:0] fineDelay2_reg=5'd0;
    reg [4:0] fineDelay3_reg=5'd0;
    
    
    reg enableGenerator_reg=0;
    reg resetCmd_reg=0;
    
    assign resetCmd=resetCmd_reg;
    assign enableGenerator=enableGenerator_reg;
    assign pulseLength=pulseLength_reg;
    assign pulseOffset=pulseOffset_reg;
    assign pulseOffsetPlusLength=pulseOffsetPlusLength_reg;
    assign laserLengthHalf=laserLengthHalf_reg;
    assign laserCountsMax=laserCountsMax_reg;
    assign fineDelay1=fineDelay1_reg;
    assign fineDelay2=fineDelay2_reg;
    assign fineDelay3=fineDelay3_reg;
    
    reg blinkLEDreg,UartRxClr;
    
    reg UartRxDV_reg, UartRxDV_regreg;
    reg UartRxDV_clear;
    reg [7:0] uartRxData_store [0:7];
    assign lastValidValue=uartRxData_store[4];
     
     always @ (posedge clk_50)
          begin
               if (reset)
               begin
                   uartRxData_store[0]<=0;
                   uartRxData_store[1]<=0;
                   uartRxData_store[2]<=0;
                   uartRxData_store[3]<=0;
                   uartRxData_store[4]<=0;
                   enableGenerator_reg<=0;
                   UartRxDV_clear<=0;
                   fineDelay1_reg<=5'd0;
                   fineDelay2_reg<=5'd0;
                   resetCmd_reg<=0;
               end
               else 
                begin 
                UartRxDV_clear <= 0;
                resetCmd_reg<=0;

                        if(UartRxDV==1)
                          begin
                           UartRxDV_reg <= UartRxDV;
                           uartRxData_store[7]<=uartRxData_store[6];                          
                           uartRxData_store[6]<=uartRxData_store[5];                          
                           uartRxData_store[5]<=uartRxData_store[4];                          
                           uartRxData_store[4]<=uartRxData_store[3];
                           uartRxData_store[3]<=uartRxData_store[2];
                           uartRxData_store[2]<=uartRxData_store[1];
                           uartRxData_store[1]<=uartRxData_store[0];
                           uartRxData_store[0]<=uartRxData;
                          end
                       else if(UartRxDV_reg==1)
                          begin
                              if ((uartRxData_store[7]==8'hAA) & (uartRxData_store[6]==8'hBB) & (uartRxData_store[5]==8'hCC)) 
                                begin
                                      resetCmd_reg<=0;
                                            if ((uartRxData_store[4]==8'h00) && (uartRxData_store[0]==8'h80))
                                                begin
                                                    enableGenerator_reg<=uartRxData_store[1][0];
                                                    resetCmd_reg<=1;
                                                end
                                       else if ((uartRxData_store[4]==8'h01) && (uartRxData_store[0]==8'h81))
                                               begin
                                                   pulseOffset_reg<={uartRxData_store[2],uartRxData_store[1]};
                                                   pulseOffsetPlusLength_reg<=(pulseOffset_reg+pulseLength_reg);
                                               end
                                       else if ((uartRxData_store[4]==8'h02) && (uartRxData_store[0]==8'h82))
                                               begin
                                                   pulseLength_reg <= {uartRxData_store[2],uartRxData_store[1]};
                                                   pulseOffsetPlusLength_reg<=(pulseOffset_reg+{uartRxData_store[2],uartRxData_store[1]});
                                               end
                                       else if ((uartRxData_store[4]==8'h03) && (uartRxData_store[0]==8'h83))
                                               begin
                                                   laserLengthHalf_reg<={uartRxData_store[2],uartRxData_store[1]};
                                               end
                                       else if ((uartRxData_store[4]==8'h04) && (uartRxData_store[0]==8'h84))
                                               begin
                                                   laserCountsMax_reg<={24'd0,uartRxData_store[1]};
                                               end
               
                                       else if ((uartRxData_store[4]==8'h05) && (uartRxData_store[0]==8'h85))
                                               begin
                                                   fineDelay1_reg<=uartRxData_store[1][4:0];
                                               end
                                       else if ((uartRxData_store[4]==8'h06) && (uartRxData_store[0]==8'h86))
                                               begin
                                                   fineDelay2_reg<=uartRxData_store[1][4:0];
                                               end
                                       else if ((uartRxData_store[4]==8'h07) && (uartRxData_store[0]==8'h87))
                                                       begin
                                                           fineDelay2_reg<=uartRxData_store[1][4:0];
                                                       end                                               
                                       else if ((uartRxData_store[4]==8'h08) && (uartRxData_store[0]==8'h88))
                                               begin
                                                 fineDelay1_reg<={1'd0,uartRxData_store[1][4:1]}+{4'd0,uartRxData_store[1][0]};
                                                 fineDelay2_reg<={1'd0,uartRxData_store[1][4:1]};
                                               end
                                                                                                                         
                                       else if ((uartRxData_store[4]==8'h10) && (uartRxData_store[0]==8'h90))
                                                               begin
                                                                   enableGenerator_reg<=1;
                                                                   pulseLength_reg <= 32'd100;
                                                                   pulseOffset_reg <= 32'd100;
                                                                   pulseOffsetPlusLength_reg <= 32'd102;
                                                                   laserLengthHalf_reg <= 32'd4000;
                                                                   laserCountsMax_reg <= 7'd10;
                                                                   fineDelay1_reg<=0;
                                                                   fineDelay2_reg<=0;                                                                   
                                                               end   
                                       else if ((uartRxData_store[4]==8'h11) && (uartRxData_store[0]==8'h91))
                                                                      begin
                                                                         pulseOffset_reg <= {uartRxData_store[3],uartRxData_store[2]};
                                                                         pulseOffsetPlusLength_reg<=({uartRxData_store[3],uartRxData_store[2]})+(pulseLength_reg);
                                                                         
                                                                         if (uartRxData_store[1][7:2]==6'd63)
                                                                            begin
                                                                                fineDelay1_reg <=5'b11111;
                                                                                fineDelay2_reg<=5'b11111;
                                                                                fineDelay3_reg<=5'b00001;
                                                                            end
                                                                         else
                                                                            begin 
                                                                                fineDelay1_reg<={1'd0,uartRxData_store[1][7:3]}+{4'd0,uartRxData_store[1][2]};
                                                                                fineDelay2_reg<={1'd0,uartRxData_store[1][7:3]};
                                                                                fineDelay3_reg<=0;
                                                                            end                                                                                                                                                                     
                                                                                                                                                                                                                
                                                                      end     
                                       else if ((uartRxData_store[4]==8'h12) && (uartRxData_store[0]==8'h92))
                                                                          begin
                                                                              resetCmd_reg<=1;
                                                                          end                                                                                                                                                             
                                end                                   
                          end
               end
          end 
                
endmodule
module uart_commands(
    input        clk_50,
    input        reset,
    input        UartRxDV,
    input  [7:0] uartRxData,
    output enableGenerator,
    output [31:0]pulseLength,
    output [31:0]pulseOffset,
    output [31:0]pulseOffsetPlusLength,
    output [31:0]laserLengthHalf,
    output [7:0] laserCountsMax,
    output [7:0] lastValidValue,
    output [4:0] fineDelay1,
    output [4:0] fineDelay2,
    output [4:0] fineDelay3, 
    output resetCmd
    );

    
    reg [31:0]pulseLength_reg=32'd100;
    reg [31:0]pulseOffset_reg=32'd100;
    reg [31:0]pulseOffsetPlusLength_reg=32'd102;
    reg [31:0]laserLengthHalf_reg=32'd4000;
    reg [7:0] laserCountsMax_reg=7'd10;
    reg [4:0] fineDelay1_reg=5'd0;
    reg [4:0] fineDelay2_reg=5'd0;
    reg [4:0] fineDelay3_reg=5'd0;
    
    
    reg enableGenerator_reg=0;
    reg resetCmd_reg=0;
    
    assign resetCmd=resetCmd_reg;
    assign enableGenerator=enableGenerator_reg;
    assign pulseLength=pulseLength_reg;
    assign pulseOffset=pulseOffset_reg;
    assign pulseOffsetPlusLength=pulseOffsetPlusLength_reg;
    assign laserLengthHalf=laserLengthHalf_reg;
    assign laserCountsMax=laserCountsMax_reg;
    assign fineDelay1=fineDelay1_reg;
    assign fineDelay2=fineDelay2_reg;
    assign fineDelay3=fineDelay3_reg;
    
    reg blinkLEDreg,UartRxClr;
    
    reg UartRxDV_reg, UartRxDV_regreg;
    reg UartRxDV_clear;
    reg [7:0] uartRxData_store [0:7];
    assign lastValidValue=uartRxData_store[4];
     
     always @ (posedge clk_50)
          begin
               if (reset)
               begin
                   uartRxData_store[0]<=0;
                   uartRxData_store[1]<=0;
                   uartRxData_store[2]<=0;
                   uartRxData_store[3]<=0;
                   uartRxData_store[4]<=0;
                   enableGenerator_reg<=0;
                   UartRxDV_clear<=0;
                   fineDelay1_reg<=5'd0;
                   fineDelay2_reg<=5'd0;
                   resetCmd_reg<=0;
               end
               else 
                begin 
                UartRxDV_clear <= 0;
                resetCmd_reg<=0;

                        if(UartRxDV==1)
                          begin
                           UartRxDV_reg <= UartRxDV;
                           uartRxData_store[7]<=uartRxData_store[6];                          
                           uartRxData_store[6]<=uartRxData_store[5];                          
                           uartRxData_store[5]<=uartRxData_store[4];                          
                           uartRxData_store[4]<=uartRxData_store[3];
                           uartRxData_store[3]<=uartRxData_store[2];
                           uartRxData_store[2]<=uartRxData_store[1];
                           uartRxData_store[1]<=uartRxData_store[0];
                           uartRxData_store[0]<=uartRxData;
                          end
                       else if(UartRxDV_reg==1)
                          begin
                              if ((uartRxData_store[7]==8'hAA) & (uartRxData_store[6]==8'hBB) & (uartRxData_store[5]==8'hCC)) 
                                begin
                                      resetCmd_reg<=0;
                                            if ((uartRxData_store[4]==8'h00) && (uartRxData_store[0]==8'h80))
                                                begin
                                                    enableGenerator_reg<=uartRxData_store[1][0];
                                                    resetCmd_reg<=1;
                                                end
                                       else if ((uartRxData_store[4]==8'h01) && (uartRxData_store[0]==8'h81))
                                               begin
                                                   pulseOffset_reg<={uartRxData_store[2],uartRxData_store[1]};
                                                   pulseOffsetPlusLength_reg<=(pulseOffset_reg+pulseLength_reg);
                                               end
                                       else if ((uartRxData_store[4]==8'h02) && (uartRxData_store[0]==8'h82))
                                               begin
                                                   pulseLength_reg <= {uartRxData_store[2],uartRxData_store[1]};
                                                   pulseOffsetPlusLength_reg<=(pulseOffset_reg+{uartRxData_store[2],uartRxData_store[1]});
                                               end
                                       else if ((uartRxData_store[4]==8'h03) && (uartRxData_store[0]==8'h83))
                                               begin
                                                   laserLengthHalf_reg<={uartRxData_store[2],uartRxData_store[1]};
                                               end
                                       else if ((uartRxData_store[4]==8'h04) && (uartRxData_store[0]==8'h84))
                                               begin
                                                   laserCountsMax_reg<={24'd0,uartRxData_store[1]};
                                               end
               
                                       else if ((uartRxData_store[4]==8'h05) && (uartRxData_store[0]==8'h85))
                                               begin
                                                   fineDelay1_reg<=uartRxData_store[1][4:0];
                                               end
                                       else if ((uartRxData_store[4]==8'h06) && (uartRxData_store[0]==8'h86))
                                               begin
                                                   fineDelay2_reg<=uartRxData_store[1][4:0];
                                               end
                                       else if ((uartRxData_store[4]==8'h07) && (uartRxData_store[0]==8'h87))
                                                       begin
                                                           fineDelay2_reg<=uartRxData_store[1][4:0];
                                                       end                                               
                                       else if ((uartRxData_store[4]==8'h08) && (uartRxData_store[0]==8'h88))
                                               begin
                                                 fineDelay1_reg<={1'd0,uartRxData_store[1][4:1]}+{4'd0,uartRxData_store[1][0]};
                                                 fineDelay2_reg<={1'd0,uartRxData_store[1][4:1]};
                                               end
                                                                                                                         
                                       else if ((uartRxData_store[4]==8'h10) && (uartRxData_store[0]==8'h90))
                                                               begin
                                                                   enableGenerator_reg<=1;
                                                                   pulseLength_reg <= 32'd100;
                                                                   pulseOffset_reg <= 32'd100;
                                                                   pulseOffsetPlusLength_reg <= 32'd102;
                                                                   laserLengthHalf_reg <= 32'd4000;
                                                                   laserCountsMax_reg <= 7'd10;
                                                                   fineDelay1_reg<=0;
                                                                   fineDelay2_reg<=0;                                                                   
                                                               end   
                                       else if ((uartRxData_store[4]==8'h11) && (uartRxData_store[0]==8'h91))
                                                                      begin
                                                                         pulseOffset_reg <= {uartRxData_store[3],uartRxData_store[2]};
                                                                         pulseOffsetPlusLength_reg<=({uartRxData_store[3],uartRxData_store[2]})+(pulseLength_reg);
                                                                         
                                                                         if (uartRxData_store[1][7:2]==6'd63)
                                                                            begin
                                                                                fineDelay1_reg <=5'b11111;
                                                                                fineDelay2_reg<=5'b11111;
                                                                                fineDelay3_reg<=5'b00001;
                                                                            end
                                                                         else
                                                                            begin 
                                                                                fineDelay1_reg<={1'd0,uartRxData_store[1][7:3]}+{4'd0,uartRxData_store[1][2]};
                                                                                fineDelay2_reg<={1'd0,uartRxData_store[1][7:3]};
                                                                                fineDelay3_reg<=0;
                                                                            end                                                                                                                                                                     
                                                                                                                                                                                                                
                                                                      end     
                                       else if ((uartRxData_store[4]==8'h12) && (uartRxData_store[0]==8'h92))
                                                                          begin
                                                                              resetCmd_reg<=1;
                                                                          end                                                                                                                                                             
                                end                                   
                          end
               end
          end 
                
endmodule