data/full_repos/permissive/504550651/verilog/rtl/rocketAlpha/IOCell.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/504550651/verilog/rtl/rocketAlpha/IOCell.v:15: Multiple top level modules\n                                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                           : ... Top module \'GenericAnalogIOCell\'\nmodule GenericAnalogIOCell(\n       ^~~~~~~~~~~~~~~~~~~\n                                                                                           : ... Top module \'GenericDigitalGPIOCell_1\'\nmodule GenericDigitalGPIOCell_1(\n       ^~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                           : ... Top module \'GenericDigitalGPIOCell\'\nmodule GenericDigitalGPIOCell(\n       ^~~~~~~~~~~~~~~~~~~~~~\n                                                                                           : ... Top module \'GenericDigitalInIOCell\'\nmodule GenericDigitalInIOCell(\n       ^~~~~~~~~~~~~~~~~~~~~~\n                                                                                           : ... Top module \'GenericDigitalOutIOCell\'\nmodule GenericDigitalOutIOCell(\n       ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module GenericDigitalInIOCell(
    input pad,
    output i,
    input ie
);

    assign i = ie ? pad : 1'b0;

endmodule
module GenericDigitalInIOCell(
    input pad,
    output i,
    input ie
);


    assign i = ie ? pad : 1'b0;

endmodule