data/full_repos/permissive/40989439/AdaptevaLib/elink-gold/fifo.v
1: b"%Error: data/full_repos/permissive/40989439/AdaptevaLib/elink-gold/fifo.v:61: Cannot find file containing module: 'fifo_mem'\n   fifo_mem #(.DW(DW),\n   ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/40989439/AdaptevaLib/elink-gold,data/full_repos/permissive/40989439/fifo_mem\n             data/full_repos/permissive/40989439/AdaptevaLib/elink-gold,data/full_repos/permissive/40989439/fifo_mem.v\n             data/full_repos/permissive/40989439/AdaptevaLib/elink-gold,data/full_repos/permissive/40989439/fifo_mem.sv\n             fifo_mem\n             fifo_mem.v\n             fifo_mem.sv\n             obj_dir/fifo_mem\n             obj_dir/fifo_mem.v\n             obj_dir/fifo_mem.sv\n%Error: data/full_repos/permissive/40989439/AdaptevaLib/elink-gold/fifo.v:74: Cannot find file containing module: 'fifo_empty_block'\n   fifo_empty_block #(.AW(AW)) fifo_empty_block( \n   ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/40989439/AdaptevaLib/elink-gold/fifo.v:88: Cannot find file containing module: 'fifo_full_block'\n   fifo_full_block #(.AW(AW)) fifo_full_block( \n   ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/40989439/AdaptevaLib/elink-gold/fifo.v:110: Cannot find file containing module: 'synchronizer'\n   synchronizer #(.DW(AW+1)) sync2wr_rd_gray_pointer ( \n   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/40989439/AdaptevaLib/elink-gold/fifo.v:119: Cannot find file containing module: 'synchronizer'\n   synchronizer #(.DW(AW+1)) sync2rd_wr_gray_pointer( \n   ^~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module fifo 
   (

   rd_data, rd_fifo_empty, wr_fifo_full,

   reset, wr_clk, rd_clk, wr_write, wr_data, rd_read
   );
   
   parameter DW = 104;
   parameter AW = 2;




   input           reset;     
   input           wr_clk;
   input           rd_clk;
   
   input           wr_write;   
   input  [DW-1:0] wr_data;
   input           rd_read;




   output [DW-1:0] rd_data;
   output          rd_fifo_empty;
   output          wr_fifo_full;




   wire [AW-1:0]	rd_addr;
   wire [AW:0]		rd_gray_pointer;
   wire [AW:0]		rd_wr_gray_pointer;
   wire [AW-1:0]	wr_addr;
   wire [AW:0]		wr_gray_pointer;
   wire [AW:0]		wr_rd_gray_pointer;

   
   

   fifo_mem #(.DW(DW),
	      .AW(AW)) fifo_mem (

				 .rd_data		(rd_data[DW-1:0]),

				 .wr_clk		(wr_clk),
				 .wr_write		(wr_write),
				 .wr_data		(wr_data[DW-1:0]),
				 .wr_addr		(wr_addr[AW-1:0]),
				 .rd_addr		(rd_addr[AW-1:0]));
   


   fifo_empty_block #(.AW(AW)) fifo_empty_block(

						.rd_fifo_empty	(rd_fifo_empty),
						.rd_addr	(rd_addr[AW-1:0]),
						.rd_gray_pointer(rd_gray_pointer[AW:0]),

						.reset		(reset),
						.rd_clk		(rd_clk),
						.rd_wr_gray_pointer(rd_wr_gray_pointer[AW:0]),
						.rd_read	(rd_read));
   
   
   

   fifo_full_block #(.AW(AW)) fifo_full_block(

					      .wr_fifo_full	(wr_fifo_full),
					      .wr_addr		(wr_addr[AW-1:0]),
					      .wr_gray_pointer	(wr_gray_pointer[AW:0]),

					      .reset		(reset),
					      .wr_clk		(wr_clk),
					      .wr_rd_gray_pointer(wr_rd_gray_pointer[AW:0]),
					      .wr_write		(wr_write));
   






   synchronizer #(.DW(AW+1)) sync2wr_rd_gray_pointer (

						      .out		(wr_rd_gray_pointer[AW:0]),

						      .in		(rd_gray_pointer[AW:0]),
						      .clk		(wr_clk),
						      .reset		(reset));
   

   synchronizer #(.DW(AW+1)) sync2rd_wr_gray_pointer(

						     .out		(rd_wr_gray_pointer[AW:0]),

						     .in		(wr_gray_pointer[AW:0]),
						     .clk		(rd_clk),
						     .reset		(reset));
   


endmodule
module fifo 
   (

   rd_data, rd_fifo_empty, wr_fifo_full,

   reset, wr_clk, rd_clk, wr_write, wr_data, rd_read
   );

   
   parameter DW = 104;
   parameter AW = 2;




   input           reset;     
   input           wr_clk;
   input           rd_clk;
   
   input           wr_write;   
   input  [DW-1:0] wr_data;
   input           rd_read;




   output [DW-1:0] rd_data;
   output          rd_fifo_empty;
   output          wr_fifo_full;




   wire [AW-1:0]	rd_addr;
   wire [AW:0]		rd_gray_pointer;
   wire [AW:0]		rd_wr_gray_pointer;
   wire [AW-1:0]	wr_addr;
   wire [AW:0]		wr_gray_pointer;
   wire [AW:0]		wr_rd_gray_pointer;

   
   

   fifo_mem #(.DW(DW),
	      .AW(AW)) fifo_mem (

				 .rd_data		(rd_data[DW-1:0]),

				 .wr_clk		(wr_clk),
				 .wr_write		(wr_write),
				 .wr_data		(wr_data[DW-1:0]),
				 .wr_addr		(wr_addr[AW-1:0]),
				 .rd_addr		(rd_addr[AW-1:0]));
   


   fifo_empty_block #(.AW(AW)) fifo_empty_block(

						.rd_fifo_empty	(rd_fifo_empty),
						.rd_addr	(rd_addr[AW-1:0]),
						.rd_gray_pointer(rd_gray_pointer[AW:0]),

						.reset		(reset),
						.rd_clk		(rd_clk),
						.rd_wr_gray_pointer(rd_wr_gray_pointer[AW:0]),
						.rd_read	(rd_read));
   
   
   

   fifo_full_block #(.AW(AW)) fifo_full_block(

					      .wr_fifo_full	(wr_fifo_full),
					      .wr_addr		(wr_addr[AW-1:0]),
					      .wr_gray_pointer	(wr_gray_pointer[AW:0]),

					      .reset		(reset),
					      .wr_clk		(wr_clk),
					      .wr_rd_gray_pointer(wr_rd_gray_pointer[AW:0]),
					      .wr_write		(wr_write));
   






   synchronizer #(.DW(AW+1)) sync2wr_rd_gray_pointer (

						      .out		(wr_rd_gray_pointer[AW:0]),

						      .in		(rd_gray_pointer[AW:0]),
						      .clk		(wr_clk),
						      .reset		(reset));
   

   synchronizer #(.DW(AW+1)) sync2rd_wr_gray_pointer(

						     .out		(rd_wr_gray_pointer[AW:0]),

						     .in		(wr_gray_pointer[AW:0]),
						     .clk		(rd_clk),
						     .reset		(reset));
   


endmodule