data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v
1: b'%Warning-REDEFMACRO: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:198: Redefining existing define: \'M_W\', with different value: 8\n                     ... Use "/* verilator lint_off REDEFMACRO */" and lint_on around source to disable this message.\n%Warning-REDEFMACRO: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:198: Previous definition is here, with value: 4\n%Warning-PINMISSING: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:379: Cell has missing pin: \'RST\'\nmb24 b_mult(\n     ^~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:499: Cannot find file containing module: \'HALF_ADDER\'\nHALF_ADDER ha000(.a(cv[0]), .b(fpp0[0]) , .sum(has000), .cout(hac000));\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/HALF_ADDER\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/HALF_ADDER.v\n             data/full_repos/permissive/526589127/verilog/rtl/b_box,data/full_repos/permissive/526589127/HALF_ADDER.sv\n             HALF_ADDER\n             HALF_ADDER.v\n             HALF_ADDER.sv\n             obj_dir/HALF_ADDER\n             obj_dir/HALF_ADDER.v\n             obj_dir/HALF_ADDER.sv\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:500: Cannot find file containing module: \'HALF_ADDER\'\nHALF_ADDER ha001(.a(cv[1]), .b(fpp0[1]) , .sum(has001), .cout(hac001));\n^~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:501: Cannot find file containing module: \'HALF_ADDER\'\nHALF_ADDER ha002(.a(cv[2]), .b(fpp0[2]) , .sum(has002), .cout(hac002));\n^~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:505: Cannot find file containing module: \'HALF_ADDER\'\nHALF_ADDER aha002(.a(cv[7]), .b(fpp1[4]) , .sum(ahas002), .cout(ahac002));\n^~~~~~~~~~\n%Error: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:509: Cannot find file containing module: \'FULL_ADDER\'\n                FULL_ADDER fa000(.a(cv[i + 3]), .b(fpp0[i + 3]), .cin(fpp1[i]), .sum(fas0[i]), .cout(fac0[i]));\n                ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:209: Operator ADD expects 6 bits on the LHS, but LHS\'s VARREF \'my\' generates 4 bits.\n                                                                                  : ... In instance sa_2D.pre_process[1].prep00\nassign SUM=my+(my<<1);\n             ^\n%Warning-WIDTH: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:209: Operator SHIFTL expects 6 bits on the LHS, but LHS\'s VARREF \'my\' generates 4 bits.\n                                                                                  : ... In instance sa_2D.pre_process[1].prep00\nassign SUM=my+(my<<1);\n                 ^~\n%Warning-LITENDIAN: data/full_repos/permissive/526589127/verilog/rtl/b_box/sa_2D.v:43: Little bit endian vector: MSB < LSB of bit range: 0:1\nreg [0:HPE-1]D_SHIFTEN;\n    ^\n%Error: Exiting due to 5 error(s), 6 warning(s)\n'
module PE_OS_16_R8( s, d, t, q, n, Y, TMY, CLK, RST,SHIFTEN,SHIFTV, S_OUT, D_OUT, T_OUT, Q_OUT, N_OUT, Y_OUT, TMY_OUT, MAC_OUT,SHIFTEN_OUT);

parameter WIDTH=4;

`define MAC_W 8
parameter group_cnt=(WIDTH>>2)+1;

input [group_cnt - 1:0] s, d, t, q, n;

input   [WIDTH-1:0]  Y;

input   [WIDTH+1:0]  TMY;

input           CLK;

input           RST;
input                   SHIFTEN;
input [2*WIDTH-1:0] SHIFTV;



output [group_cnt - 1:0]S_OUT, D_OUT, T_OUT, Q_OUT, N_OUT;

output  [WIDTH-1:0]  Y_OUT;

output  [WIDTH+1:0]  TMY_OUT;
output reg                      SHIFTEN_OUT;
output [2*WIDTH-1:0]  MAC_OUT;

wire [2*WIDTH-1:0]  MAC_OUT_FB;


reg [2*WIDTH-1:0]  MAC_OUT_BUF0;
reg [2*WIDTH-1:0]  MAC_OUT_BUF1;
reg TEMP_SHIFT;





reg [group_cnt - 1:0]S_OUT, D_OUT, T_OUT, Q_OUT, N_OUT;

reg   [WIDTH-1:0]  Y_OUT;

reg   [WIDTH+1:0]  TMY_OUT;

wire     [2*WIDTH-1:0]  product;

always @(posedge CLK)
begin

           S_OUT <= s;

           D_OUT <= d;

           T_OUT <= t;

           Q_OUT <= q;

           N_OUT <= n;

           Y_OUT <= Y;

           TMY_OUT <= TMY;
end

mb24 b_mult(
 .s(s),
 .d(d),
 .t(t),
 .q(q),
 .n(n),
 .my(Y),
 .tmy(TMY),
 .CLK(CLK),
 .product(product)
);


reg     [2*WIDTH-1:0]  product_reg;
always @(posedge CLK or negedge RST)

begin
        if (RST == 1'b0)
        begin
          MAC_OUT_BUF0 <= `MAC_W'b0;
                  MAC_OUT_BUF1 <= `MAC_W'b0;
                  TEMP_SHIFT <= 1'b0;
                  SHIFTEN_OUT <= 1'b0;
        end

        else
        begin
                  TEMP_SHIFT <= SHIFTEN;
          SHIFTEN_OUT <= TEMP_SHIFT;
              MAC_OUT_BUF0 <=TEMP_SHIFT?SHIFTV:{MAC_OUT_FB+product_reg};
              MAC_OUT_BUF1 <=~TEMP_SHIFT?SHIFTV:{MAC_OUT_FB+product_reg};
        end
end

assign MAC_OUT_FB=SHIFTEN_OUT?MAC_OUT_BUF1:MAC_OUT_BUF0;
assign MAC_OUT=~TEMP_SHIFT?MAC_OUT_BUF1:MAC_OUT_BUF0;



always @(posedge CLK)
begin
        if (RST == 1'b0)
        begin
        product_reg <= `MAC_W'b0;

        end

        else
begin
          product_reg<=product;

end
end
endmodule
module PE_OS_16_R8( s, d, t, q, n, Y, TMY, CLK, RST,SHIFTEN,SHIFTV, S_OUT, D_OUT, T_OUT, Q_OUT, N_OUT, Y_OUT, TMY_OUT, MAC_OUT,SHIFTEN_OUT);


parameter WIDTH=4;

`define MAC_W 8
parameter group_cnt=(WIDTH>>2)+1;

input [group_cnt - 1:0] s, d, t, q, n;

input   [WIDTH-1:0]  Y;

input   [WIDTH+1:0]  TMY;

input           CLK;

input           RST;
input                   SHIFTEN;
input [2*WIDTH-1:0] SHIFTV;



output [group_cnt - 1:0]S_OUT, D_OUT, T_OUT, Q_OUT, N_OUT;

output  [WIDTH-1:0]  Y_OUT;

output  [WIDTH+1:0]  TMY_OUT;
output reg                      SHIFTEN_OUT;
output [2*WIDTH-1:0]  MAC_OUT;

wire [2*WIDTH-1:0]  MAC_OUT_FB;


reg [2*WIDTH-1:0]  MAC_OUT_BUF0;
reg [2*WIDTH-1:0]  MAC_OUT_BUF1;
reg TEMP_SHIFT;





reg [group_cnt - 1:0]S_OUT, D_OUT, T_OUT, Q_OUT, N_OUT;

reg   [WIDTH-1:0]  Y_OUT;

reg   [WIDTH+1:0]  TMY_OUT;

wire     [2*WIDTH-1:0]  product;

always @(posedge CLK)
begin

           S_OUT <= s;

           D_OUT <= d;

           T_OUT <= t;

           Q_OUT <= q;

           N_OUT <= n;

           Y_OUT <= Y;

           TMY_OUT <= TMY;
end

mb24 b_mult(
 .s(s),
 .d(d),
 .t(t),
 .q(q),
 .n(n),
 .my(Y),
 .tmy(TMY),
 .CLK(CLK),
 .product(product)
);


reg     [2*WIDTH-1:0]  product_reg;
always @(posedge CLK or negedge RST)

begin
        if (RST == 1'b0)
        begin
          MAC_OUT_BUF0 <= `MAC_W'b0;
                  MAC_OUT_BUF1 <= `MAC_W'b0;
                  TEMP_SHIFT <= 1'b0;
                  SHIFTEN_OUT <= 1'b0;
        end

        else
        begin
                  TEMP_SHIFT <= SHIFTEN;
          SHIFTEN_OUT <= TEMP_SHIFT;
              MAC_OUT_BUF0 <=TEMP_SHIFT?SHIFTV:{MAC_OUT_FB+product_reg};
              MAC_OUT_BUF1 <=~TEMP_SHIFT?SHIFTV:{MAC_OUT_FB+product_reg};
        end
end

assign MAC_OUT_FB=SHIFTEN_OUT?MAC_OUT_BUF1:MAC_OUT_BUF0;
assign MAC_OUT=~TEMP_SHIFT?MAC_OUT_BUF1:MAC_OUT_BUF0;



always @(posedge CLK)
begin
        if (RST == 1'b0)
        begin
        product_reg <= `MAC_W'b0;

        end

        else
begin
          product_reg<=product;

end
end
endmodule