data/full_repos/permissive/504478691/oscilloscope/tb_SPI.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/504478691/oscilloscope/tb_SPI.v:12: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/504478691/oscilloscope/tb_SPI.v:6: Cannot find file containing module: \'oscilloscope\'\noscilloscope inst(.clk(clk), .sck(sck), .mosi(mosi), .dc(dc), .rst(rst), .cs(cs));\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/504478691/oscilloscope,data/full_repos/permissive/504478691/oscilloscope\n             data/full_repos/permissive/504478691/oscilloscope,data/full_repos/permissive/504478691/oscilloscope.v\n             data/full_repos/permissive/504478691/oscilloscope,data/full_repos/permissive/504478691/oscilloscope.sv\n             oscilloscope\n             oscilloscope.v\n             oscilloscope.sv\n             obj_dir/oscilloscope\n             obj_dir/oscilloscope.v\n             obj_dir/oscilloscope.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb();
reg clk = 0;
wire sck, mosi, dc, cs, rst;
wire [31:0] i;
oscilloscope inst(.clk(clk), .sck(sck), .mosi(mosi), .dc(dc), .rst(rst), .cs(cs));
integer ii;
initial
begin
    for (ii = 0; ii <= 100_000; ii = ii + 1)
    begin
        #1;
        clk = ~clk;
    end
end
endmodule
module tb();

reg clk = 0;
wire sck, mosi, dc, cs, rst;
wire [31:0] i;
oscilloscope inst(.clk(clk), .sck(sck), .mosi(mosi), .dc(dc), .rst(rst), .cs(cs));
integer ii;
initial
begin
    for (ii = 0; ii <= 100_000; ii = ii + 1)
    begin
        #1;
        clk = ~clk;
    end
end
endmodule