data/full_repos/permissive/419677538/Exercise_2/verilog_code/DigSysExe2.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/419677538/Exercise_2/verilog_code/DigSysExe2.v:34: Unsupported: Ignoring delay on this delayed statement.\n      #10 x<=x+1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Exercise_2/verilog_code/DigSysExe2.v:78: Unsupported: Ignoring delay on this delayed statement.\n      #10 x<=x+1;\n      ^\n%Warning-MULTITOP: data/full_repos/permissive/419677538/Exercise_2/verilog_code/DigSysExe2.v:71: Multiple top level modules\n                                                                                               : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                                                                                               : ... Top module \'testbenchDecoder4to16\'\nmodule testbenchDecoder4to16;\n       ^~~~~~~~~~~~~~~~~~~~~\n                                                                                               : ... Top module \'testbenchSqr\'\nmodule testbenchSqr;\n       ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/419677538/Exercise_2/verilog_code/DigSysExe2.v:32: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                            : ... In instance testbenchDecoder4to16\n      x=1\'b0;\n       ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbenchSqr;
   reg [3:0] x;
   wire [7:0] d;
   sqr sqr0(x,d);
   initial 
      x=4'b0;
   always
      #10 x<=x+1;
endmodule
module testbenchSqr;

   reg [3:0] x;
   wire [7:0] d;
   sqr sqr0(x,d);
   initial 
      x=4'b0;
   always
      #10 x<=x+1;
endmodule