data/full_repos/permissive/458737381/src/verilog-parser/tests/sctag_pcx_rptr_1.v
data/verilator_xmls/e2f47858-dd23-4d8e-bd45-bd09f0295f66.xml
module sctag_pcx_rptr_1 (

   sig_buf, 

   sig
   );




output  [163:0] sig_buf;
input   [163:0] sig;


assign  sig_buf  = sig;



















endmodule
module sctag_pcx_rptr_1 (

   sig_buf, 

   sig
   );





output  [163:0] sig_buf;
input   [163:0] sig;


assign  sig_buf  = sig;



















endmodule