data/full_repos/permissive/482006041/6-1/user/src/clk_div_even.v
1: b'%Warning-WIDTH: data/full_repos/permissive/482006041/6-1/user/src/clk_div_even.v:18: Operator ASSIGNDLY expects 15 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                                   : ... In instance clk_div_even\n            counter <= 16\'b0;\n                    ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/482006041/6-1/user/src/clk_div_even.v:22: Operator ASSIGNDLY expects 15 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                                   : ... In instance clk_div_even\n            counter <= 16\'b0;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/482006041/6-1/user/src/clk_div_even.v:21: Operator EQ expects 32 or 16 bits on the LHS, but LHS\'s VARREF \'counter\' generates 15 bits.\n                                                                                   : ... In instance clk_div_even\n        else if (counter == DIV/2-1) begin\n                         ^~\n%Error: Exiting due to 3 warning(s)\n'
module clk_div_even (
    input   wire    clk,
    input   wire    rst_n,

    output  reg     clk_div
);

    parameter DIV   = 50000;
    parameter DIV_W = 15;

    reg [DIV_W-1:0] counter;

    always @(posedge clk, negedge rst_n) begin
        if (rst_n == `ENABLE_) begin
            counter <= 16'b0;
            clk_div <= 1'b0;
        end
        else if (counter == DIV/2-1) begin
            counter <= 16'b0;
            clk_div <= ~clk_div;
        end
        else 
            counter <= counter + 1'b1;
    end
    
endmodule
module clk_div_even (
    input   wire    clk,
    input   wire    rst_n,

    output  reg     clk_div
);


    parameter DIV   = 50000;
    parameter DIV_W = 15;

    reg [DIV_W-1:0] counter;

    always @(posedge clk, negedge rst_n) begin
        if (rst_n == `ENABLE_) begin
            counter <= 16'b0;
            clk_div <= 1'b0;
        end
        else if (counter == DIV/2-1) begin
            counter <= 16'b0;
            clk_div <= ~clk_div;
        end
        else 
            counter <= counter + 1'b1;
    end
    
endmodule