data/full_repos/permissive/507564148/code/basic/count2rand.v
data/verilator_xmls/57d13afb-1b1a-4a7c-a86e-bd9f2b54d6e8.xml
module count2rand (
    input clk,
    input start,
    input rst_n,
    input wire[12:0] rand_num,
    output reg get_rand
);

reg [12:0] Q;
always @(posedge clk) begin

        if(!rst_n) begin
            get_rand <= 1'b0;
            Q <= 13'd5001;
        end

        else if(start) begin
            Q <= 13'b0;
            get_rand <= 1'b0;
        end

        else if(Q == rand_num) begin
            get_rand <= 1'b1;
            Q <= Q + 13'd1;
        end

        else if(Q == 13'd5001) begin
            Q <= Q;
        end

        else begin
            Q <= Q + 13'd1;
            get_rand <= 1'b0;
        end
end
endmodule
module count2rand (
    input clk,
    input start,
    input rst_n,
    input wire[12:0] rand_num,
    output reg get_rand
);


reg [12:0] Q;
always @(posedge clk) begin

        if(!rst_n) begin
            get_rand <= 1'b0;
            Q <= 13'd5001;
        end

        else if(start) begin
            Q <= 13'b0;
            get_rand <= 1'b0;
        end

        else if(Q == rand_num) begin
            get_rand <= 1'b1;
            Q <= Q + 13'd1;
        end

        else if(Q == 13'd5001) begin
            Q <= Q;
        end

        else begin
            Q <= Q + 13'd1;
            get_rand <= 1'b0;
        end
end
endmodule