data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/fflopknx.v
data/verilator_xmls/e6627656-3ec4-4a2f-9677-d7a0acd4ae98.xml
module fflopknx
    (
     clk,
     rst,
     idat,
     odat
     );



parameter           W_B = 10;
parameter           K_V = 1;
parameter           A_R = 1;
localparam          D_V = K_V <= 1 ? 2 : K_V;
localparam          O_V = K_V <= 1 ? 1 : K_V - 1;
localparam          D_B = (D_V)*W_B;
localparam          S_B = D_B-W_B;



input               clk;
input               rst;
input [W_B-1:0]     idat;
output [W_B-1:0]    odat;
  


wire [W_B-1:0]      odat;




reg [W_B-1:0]       d_reg;
reg [S_B-1:0]       s_reg = {S_B{1'b0}};

generate
    if (K_V == 0)
        begin: pp_s0
        always @(*) d_reg = idat;
end
    else
        begin: pp_s1
        always @(posedge clk) d_reg <= idat;
end
endgenerate


wire [D_B-1:0]      s_pre;
assign              s_pre = {s_reg[S_B-1:0],d_reg};
assign              odat  =  s_reg[O_V*W_B-1:(O_V-1)*W_B];

generate
    if (K_V <= 1)
        begin: off_s
        always @(*) s_reg = s_pre[S_B-1:0];
end
    else if (A_R == 0)
        begin: on_ns
        always @(posedge clk) s_reg <= s_pre[S_B-1:0];
end
    else
        begin
        always @(posedge clk) s_reg <= s_pre[S_B-1:0];
end
endgenerate


endmodule
module fflopknx
    (
     clk,
     rst,
     idat,
     odat
     );




parameter           W_B = 10;
parameter           K_V = 1;
parameter           A_R = 1;
localparam          D_V = K_V <= 1 ? 2 : K_V;
localparam          O_V = K_V <= 1 ? 1 : K_V - 1;
localparam          D_B = (D_V)*W_B;
localparam          S_B = D_B-W_B;



input               clk;
input               rst;
input [W_B-1:0]     idat;
output [W_B-1:0]    odat;
  


wire [W_B-1:0]      odat;




reg [W_B-1:0]       d_reg;
reg [S_B-1:0]       s_reg = {S_B{1'b0}};

generate
    if (K_V == 0)
        begin: pp_s0
        always @(*) d_reg = idat;
end
    else
        begin: pp_s1
        always @(posedge clk) d_reg <= idat;
end
endgenerate


wire [D_B-1:0]      s_pre;
assign              s_pre = {s_reg[S_B-1:0],d_reg};
assign              odat  =  s_reg[O_V*W_B-1:(O_V-1)*W_B];

generate
    if (K_V <= 1)
        begin: off_s
        always @(*) s_reg = s_pre[S_B-1:0];
end
    else if (A_R == 0)
        begin: on_ns
        always @(posedge clk) s_reg <= s_pre[S_B-1:0];
end
    else
        begin
        always @(posedge clk) s_reg <= s_pre[S_B-1:0];
end
endgenerate


endmodule