data/full_repos/permissive/470158975/rtl/outbond_header_crc.v
1: b'%Warning-WIDTH: data/full_repos/permissive/470158975/rtl/outbond_header_crc.v:101: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 16 bits.\n                                                                                 : ... In instance outbond_header_crc.checksum_acc_i\n         checksum_int <= checksum_int + header[15:0] + header[31:16];\n                                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/470158975/rtl/outbond_header_crc.v:101: Operator ADD expects 32 bits on the RHS, but RHS\'s SEL generates 16 bits.\n                                                                                 : ... In instance outbond_header_crc.checksum_acc_i\n         checksum_int <= checksum_int + header[15:0] + header[31:16];\n                                                     ^\n%Warning-WIDTH: data/full_repos/permissive/470158975/rtl/outbond_header_crc.v:105: Operator ADD expects 16 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                 : ... In instance outbond_header_crc.checksum_acc_i\n   assign checksum = ~(summ[15:0] + summ[16]);\n                                  ^\n%Error: Exiting due to 3 warning(s)\n'
module outbond_header_crc(
   input clk,                         
   input reset,                       
   input [159:0] header,              
   input header_valid,                
   output [15:0] checksum,            
   output checksum_valid              

);


   localparam WAIT_HEADER          =0;    
   localparam CHECKSUM_CALCULATE   =1;    
   localparam RESULT               =2;    
   
   reg [2:0]       state;                 
   reg [127:0]     header_sreg;           
   reg [2:0]       shift_cntr;            
   reg [31:0]      header_data;           
   reg             crc_reset;             
   
   
   
   always @(posedge clk) begin
      if (reset) begin                                   

         header_sreg<=0;
         header_data<=0;
         shift_cntr<=0;
         crc_reset<=0;
         state<=WAIT_HEADER;
         shift_cntr<=0;
   
      end
      else 
      case (state)
         WAIT_HEADER:begin                                     
            if (header_valid) begin                            
               state <= CHECKSUM_CALCULATE;                    
               header_data<=header[31:0];                      
               header_sreg<=header[159:32];                    
               crc_reset<=0;                                   
               
            end 
            else begin                                         
               crc_reset<=1;                                   
               state <= WAIT_HEADER;                           
            end
         end
   
         CHECKSUM_CALCULATE: begin                   
            header_data<=header_sreg[31:0];                    
            header_sreg<={32'b0, header_sreg[127:32]};         
            shift_cntr<=shift_cntr+1;                          
            if (shift_cntr==4) begin                           
               state<= WAIT_HEADER;                            
               crc_reset<=1;                                   
            end 
         end
   
         default: state<= WAIT_HEADER;                         
      endcase
   end
   
   
   
   checksum_acc checksum_acc_i(
           .clk(clk),                      
           .valid(checksum_valid),         
           .checksum(checksum[15:0]),      
           .header(header_data),           
           .reset(crc_reset)               
      
   );
   
   
endmodule
module outbond_header_crc(
   input clk,                         
   input reset,                       
   input [159:0] header,              
   input header_valid,                
   output [15:0] checksum,            
   output checksum_valid              

);



   localparam WAIT_HEADER          =0;    
   localparam CHECKSUM_CALCULATE   =1;    
   localparam RESULT               =2;    
   
   reg [2:0]       state;                 
   reg [127:0]     header_sreg;           
   reg [2:0]       shift_cntr;            
   reg [31:0]      header_data;           
   reg             crc_reset;             
   
   
   
   always @(posedge clk) begin
      if (reset) begin                                   

         header_sreg<=0;
         header_data<=0;
         shift_cntr<=0;
         crc_reset<=0;
         state<=WAIT_HEADER;
         shift_cntr<=0;
   
      end
      else 
      case (state)
         WAIT_HEADER:begin                                     
            if (header_valid) begin                            
               state <= CHECKSUM_CALCULATE;                    
               header_data<=header[31:0];                      
               header_sreg<=header[159:32];                    
               crc_reset<=0;                                   
               
            end 
            else begin                                         
               crc_reset<=1;                                   
               state <= WAIT_HEADER;                           
            end
         end
   
         CHECKSUM_CALCULATE: begin                   
            header_data<=header_sreg[31:0];                    
            header_sreg<={32'b0, header_sreg[127:32]};         
            shift_cntr<=shift_cntr+1;                          
            if (shift_cntr==4) begin                           
               state<= WAIT_HEADER;                            
               crc_reset<=1;                                   
            end 
         end
   
         default: state<= WAIT_HEADER;                         
      endcase
   end
   
   
   
   checksum_acc checksum_acc_i(
           .clk(clk),                      
           .valid(checksum_valid),         
           .checksum(checksum[15:0]),      
           .header(header_data),           
           .reset(crc_reset)               
      
   );
   
   
endmodule