data/full_repos/permissive/445695969/src_rtl/unprotected/romulus_datapath_backup.v
1: b'%Error: data/full_repos/permissive/445695969/src_rtl/unprotected/romulus_datapath_backup.v:8: Cannot find include file: romulus_config_pkg.v\n`include "romulus_config_pkg.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/445695969/src_rtl/unprotected,data/full_repos/permissive/445695969/romulus_config_pkg.v\n             data/full_repos/permissive/445695969/src_rtl/unprotected,data/full_repos/permissive/445695969/romulus_config_pkg.v.v\n             data/full_repos/permissive/445695969/src_rtl/unprotected,data/full_repos/permissive/445695969/romulus_config_pkg.v.sv\n             romulus_config_pkg.v\n             romulus_config_pkg.v.v\n             romulus_config_pkg.v.sv\n             obj_dir/romulus_config_pkg.v\n             obj_dir/romulus_config_pkg.v.v\n             obj_dir/romulus_config_pkg.v.sv\n%Error: Exiting due to 1 error(s)\n'
module tkz_update (

                   tkz,

                   tkztbc, tkzcorrect, clk, rst, tbc, en
                   ) ;
   parameter fullcnt = 0;

   output [63+fullcnt*64:0] tkz;

   input [63+fullcnt*64:0]  tkztbc, tkzcorrect;
   input                    clk, rst, tbc, en;

   reg [63+fullcnt*64:0]    state;

   generate
      always @ (posedge clk) begin
         if (rst) begin
            if (fullcnt == 1) begin:initial_counter_state
               state <= 128'h01000000000000000000000000000000;
            end
            else begin
               state <= 64'h0100000000000000;
            end
         end
         else if (en) begin
            if (tbc) begin
               state <= tkztbc;
            end
            else begin
               state <= tkzcorrect;
            end
         end
      end
   endgenerate

endmodule
module tkz_update (

                   tkz,

                   tkztbc, tkzcorrect, clk, rst, tbc, en
                   ) ;

   parameter fullcnt = 0;

   output [63+fullcnt*64:0] tkz;

   input [63+fullcnt*64:0]  tkztbc, tkzcorrect;
   input                    clk, rst, tbc, en;

   reg [63+fullcnt*64:0]    state;

   generate
      always @ (posedge clk) begin
         if (rst) begin
            if (fullcnt == 1) begin:initial_counter_state
               state <= 128'h01000000000000000000000000000000;
            end
            else begin
               state <= 64'h0100000000000000;
            end
         end
         else if (en) begin
            if (tbc) begin
               state <= tkztbc;
            end
            else begin
               state <= tkzcorrect;
            end
         end
      end
   endgenerate

endmodule