data/full_repos/permissive/405799749/amg_new2/adder/FSA_16_64_Carry_select_adder.v
data/verilator_xmls/a1e22f4f-1bee-4d86-a007-eae88622d5c2.xml
module UBPureCSe_63_0 (S, X, Y);
  output [64:0] S;
  input [63:0] X;
  input [63:0] Y;
  wire C;
  UBPriCSlA_63_0 U0 (S, X, Y, C);
  UBZero_0_0 U1 (C);
endmodule
module UBPureCSe_63_0 (S, X, Y);

  output [64:0] S;
  input [63:0] X;
  input [63:0] Y;
  wire C;
  UBPriCSlA_63_0 U0 (S, X, Y, C);
  UBZero_0_0 U1 (C);
endmodule