data/full_repos/permissive/46343463/src/MEMWB_Reg.v
1: b"%Error: data/full_repos/permissive/46343463/src/MEMWB_Reg.v:18: Cannot find file containing module: 'Latch'\n    Latch #(.width(2)) MEMWB_WB_ctrl (\n    ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/46343463/src,data/full_repos/permissive/46343463/Latch\n             data/full_repos/permissive/46343463/src,data/full_repos/permissive/46343463/Latch.v\n             data/full_repos/permissive/46343463/src,data/full_repos/permissive/46343463/Latch.sv\n             Latch\n             Latch.v\n             Latch.sv\n             obj_dir/Latch\n             obj_dir/Latch.v\n             obj_dir/Latch.sv\n%Error: data/full_repos/permissive/46343463/src/MEMWB_Reg.v:26: Cannot find file containing module: 'Latch'\n    Latch MEMWB_ALU_output (\n    ^~~~~\n%Error: data/full_repos/permissive/46343463/src/MEMWB_Reg.v:34: Cannot find file containing module: 'Latch'\n    Latch MEMWB_Mem_output (\n    ^~~~~\n%Error: data/full_repos/permissive/46343463/src/MEMWB_Reg.v:42: Cannot find file containing module: 'Latch'\n    Latch #(.width(5)) MEMWB_RegFwd (\n    ^~~~~\n%Error: Exiting due to 4 error(s)\n"
module MEMWB_Reg (
    input       clk,
    input       rst,

    input       flush,
    input       stall,

    input   [2-1:0]     WB_ctrl_i,
    output  [2-1:0]     WB_ctrl_o,
    input   [32-1:0]    ALU_output_i,
    output  [32-1:0]    ALU_output_o,
    input   [32-1:0]    Mem_output_i,
    output  [32-1:0]    Mem_output_o,
    input   [5-1:0]     RegFwd_i,
    output  [5-1:0]     RegFwd_o
);

    Latch #(.width(2)) MEMWB_WB_ctrl (
    	.clk			(clk),
        .rst            (~flush),
        .we             (~stall),
    	.data_i			(WB_ctrl_i),
    	.data_o			(WB_ctrl_o)
    );

    Latch MEMWB_ALU_output (
        .clk			(clk),
        .rst            (~flush),
        .we             (~stall),
    	.data_i			(ALU_output_i),
    	.data_o			(ALU_output_o)
    );

    Latch MEMWB_Mem_output (
        .clk			(clk),
        .rst            (~flush),
        .we             (~stall),
    	.data_i			(Mem_output_i),
    	.data_o			(Mem_output_o)
    );

    Latch #(.width(5)) MEMWB_RegFwd (
        .clk			(clk),
        .rst            (~flush),
        .we             (~stall),
    	.data_i			(RegFwd_i),
    	.data_o			(RegFwd_o)
    );

endmodule
module MEMWB_Reg (
    input       clk,
    input       rst,

    input       flush,
    input       stall,

    input   [2-1:0]     WB_ctrl_i,
    output  [2-1:0]     WB_ctrl_o,
    input   [32-1:0]    ALU_output_i,
    output  [32-1:0]    ALU_output_o,
    input   [32-1:0]    Mem_output_i,
    output  [32-1:0]    Mem_output_o,
    input   [5-1:0]     RegFwd_i,
    output  [5-1:0]     RegFwd_o
);


    Latch #(.width(2)) MEMWB_WB_ctrl (
    	.clk			(clk),
        .rst            (~flush),
        .we             (~stall),
    	.data_i			(WB_ctrl_i),
    	.data_o			(WB_ctrl_o)
    );

    Latch MEMWB_ALU_output (
        .clk			(clk),
        .rst            (~flush),
        .we             (~stall),
    	.data_i			(ALU_output_i),
    	.data_o			(ALU_output_o)
    );

    Latch MEMWB_Mem_output (
        .clk			(clk),
        .rst            (~flush),
        .we             (~stall),
    	.data_i			(Mem_output_i),
    	.data_o			(Mem_output_o)
    );

    Latch #(.width(5)) MEMWB_RegFwd (
        .clk			(clk),
        .rst            (~flush),
        .we             (~stall),
    	.data_i			(RegFwd_i),
    	.data_o			(RegFwd_o)
    );

endmodule