data/full_repos/permissive/423547971/FPGA Projects/FIFO/fifo_test.v
1: b'%Error: Cannot find file containing module: Projects/FIFO,data/full_repos/permissive/423547971\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/FIFO,data/full_repos/permissive/423547971\n             data/full_repos/permissive/423547971/FPGA/Projects/FIFO,data/full_repos/permissive/423547971.v\n             data/full_repos/permissive/423547971/FPGA/Projects/FIFO,data/full_repos/permissive/423547971.sv\n             Projects/FIFO,data/full_repos/permissive/423547971\n             Projects/FIFO,data/full_repos/permissive/423547971.v\n             Projects/FIFO,data/full_repos/permissive/423547971.sv\n             obj_dir/Projects/FIFO,data/full_repos/permissive/423547971\n             obj_dir/Projects/FIFO,data/full_repos/permissive/423547971.v\n             obj_dir/Projects/FIFO,data/full_repos/permissive/423547971.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: Projects/FIFO/fifo_test.v\n%Error: Exiting due to 3 error(s)\n'
module fifo_test(
    input clk_100MHz,
    input reset,
    input wr,
    input rd,
    input [2:0] sw,
    output full,
    output empty,
    output [2:0] data_out
    );
    

    wire write, read;
    
    debounce_explicit debounce_unit1(
        .clk_100MHz(clk_100MHz),
        .reset(reset),
        .btn(wr),
        .db_level(),
        .db_tick(write)
    );
   
    debounce_explicit debounce_unit2(
        .clk_100MHz(clk_100MHz),
        .reset(reset),
        .btn(rd),
        .db_level(),
        .db_tick(read)
    );
    
    fifo #(.DATA_SIZE(3), .ADDR_SPACE_EXP(2)) fifo_unit(
        .clk(clk_100MHz),
        .reset(reset),
        .write_to_fifo(write),
        .read_from_fifo(read),
        .write_data_in(sw),
        .read_data_out(data_out),
        .full(full),
        .empty(empty)
        );
    
endmodule
module fifo_test(
    input clk_100MHz,
    input reset,
    input wr,
    input rd,
    input [2:0] sw,
    output full,
    output empty,
    output [2:0] data_out
    );

    

    wire write, read;
    
    debounce_explicit debounce_unit1(
        .clk_100MHz(clk_100MHz),
        .reset(reset),
        .btn(wr),
        .db_level(),
        .db_tick(write)
    );
   
    debounce_explicit debounce_unit2(
        .clk_100MHz(clk_100MHz),
        .reset(reset),
        .btn(rd),
        .db_level(),
        .db_tick(read)
    );
    
    fifo #(.DATA_SIZE(3), .ADDR_SPACE_EXP(2)) fifo_unit(
        .clk(clk_100MHz),
        .reset(reset),
        .write_to_fifo(write),
        .read_from_fifo(read),
        .write_data_in(sw),
        .read_data_out(data_out),
        .full(full),
        .empty(empty)
        );
    
endmodule