data/full_repos/permissive/434837003/test/issues.v
1: b'%Error: data/full_repos/permissive/434837003/test/issues.v:90: Cannot find include file: some_include.v\n`include "some_include.v" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/434837003/test,data/full_repos/permissive/434837003/some_include.v\n             data/full_repos/permissive/434837003/test,data/full_repos/permissive/434837003/some_include.v.v\n             data/full_repos/permissive/434837003/test,data/full_repos/permissive/434837003/some_include.v.sv\n             some_include.v\n             some_include.v.v\n             some_include.v.sv\n             obj_dir/some_include.v\n             obj_dir/some_include.v.v\n             obj_dir/some_include.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/434837003/test/issues.v:27: Unsupported: Ignoring delay on this delayed statement.\ninitial #(3) display;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/434837003/test/issues.v:28: Unsupported: Ignoring delay on this delayed statement.\ninitial #1 display;\n        ^\n%Error: data/full_repos/permissive/434837003/test/issues.v:29: syntax error, unexpected \'#\', expecting IDENTIFIER or \'=\' or do or final\nreg #1 a;\n    ^\n%Error: data/full_repos/permissive/434837003/test/issues.v:30: syntax error, unexpected \'#\', expecting TYPE-IDENTIFIER\nassign b = #2 c;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/434837003/test/issues.v:31: Unsupported: Ignoring delay on this delayed statement.\ninitial begin #5 display; end\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/434837003/test/issues.v:33: Unsupported: Ignoring delay on this delayed statement.\n  begin #5 display;\n        ^\n%Error: data/full_repos/permissive/434837003/test/issues.v:57: syntax error, unexpected \';\', expecting \')\' or \',\'\n    input  input_1;\n                  ^\n%Error: data/full_repos/permissive/434837003/test/issues.v:136: Define or directive not defined: \'`CYCLE\'\n        # ( 0.25 * `CYCLE);\n                   ^~~~~~\n%Error: data/full_repos/permissive/434837003/test/issues.v:136: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        # ( 0.25 * `CYCLE);\n                         ^\n%Error: data/full_repos/permissive/434837003/test/issues.v:138: Define or directive not defined: \'`RST_DELAY\'\n        # ((`RST_DELAY) * `CYCLE);\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/434837003/test/issues.v:138: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        # ((`RST_DELAY) * `CYCLE);\n                      ^\n%Error: data/full_repos/permissive/434837003/test/issues.v:138: Define or directive not defined: \'`CYCLE\'\n        # ((`RST_DELAY) * `CYCLE);\n                          ^~~~~~\n%Error: Exiting due to 9 error(s), 4 warning(s)\n'
module sample(
    input clk,
    input signed [7:0] data,
    output result
);

`ifdef SIMULATION
    integer dbg_id;
`endif
parameter SOME_PARAM = 6;

wire signed [SOME_PARAM-1:0] some_logic;

module_def module_instance (
    .clk(clk),
    .data(data)
);

endmodule
module sample(
    input clk,
    input signed [7:0] data,
    output result
);


`ifdef SIMULATION
    integer dbg_id;
`endif
parameter SOME_PARAM = 6;

wire signed [SOME_PARAM-1:0] some_logic;

module_def module_instance (
    .clk(clk),
    .data(data)
);

endmodule