data/full_repos/permissive/441359809/src/yosys/manual/PRESENTATION_ExSyn/proc_03.v
data/verilator_xmls/ef538926-8a84-454b-bac3-ef4677cd300f.xml
module test(input A, B, C, D, E,
            output reg Y);
    always @* begin
	Y <= A;
	if (B)
	    Y <= C;
	if (D)
	    Y <= E;
    end
endmodule
module test(input A, B, C, D, E,
            output reg Y);

    always @* begin
	Y <= A;
	if (B)
	    Y <= C;
	if (D)
	    Y <= E;
    end
endmodule