data/full_repos/permissive/411457613/Pyverilog/verilogcode/reset.v
1: b'%Error: data/full_repos/permissive/411457613/Pyverilog/verilogcode/reset.v:8: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is \'logic\'\n                                                                            : ... In instance TOP\n    if(RST[0]) begin\n          ^\n%Warning-WIDTH: data/full_repos/permissive/411457613/Pyverilog/verilogcode/reset.v:25: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 1 bits.\n                                                                                     : ... In instance TOP\n      cnt3 <= cnt1[0];\n           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/411457613/Pyverilog/verilogcode/reset.v:48: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                     : ... In instance TOP\n      cnt6 <= 7\'d0 + cnt1[1:0];\n                   ^\n%Error: data/full_repos/permissive/411457613/Pyverilog/verilogcode/reset.v:73: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is \'logic\'\n                                                                             : ... In instance TOP\n    if(RST[zero]) begin\n          ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module SUB(CLK, RST);
  input CLK, RST;
  reg [7:0] cnt9;
  parameter zero = 0;

  always @(posedge CLK) begin
    if(RST) begin
      cnt9 <= zero;
    end else begin
      cnt9 <= 8'd1;
    end
  end
endmodule
module SUB(CLK, RST);

  input CLK, RST;
  reg [7:0] cnt9;
  parameter zero = 0;

  always @(posedge CLK) begin
    if(RST) begin
      cnt9 <= zero;
    end else begin
      cnt9 <= 8'd1;
    end
  end
endmodule