data/full_repos/permissive/512104971/dual_port_ram.v
data/verilator_xmls/65126c4c-9f1f-47fa-8411-a7c8a34706f9.xml
module dual_port_RAM(CLK,CS,WR_RD_A,WR_RD_B,ADDR_A,ADDR_B,WDATA_A,WDATA_B,RDATA_A,RDATA_B);
  
  parameter N = 4;
  parameter D = 16;
  parameter W = 8;
  
  input CLK,CS,WR_RD_A,WR_RD_B;
  input [N-1:0] ADDR_A,ADDR_B;
  input [W-1:0] WDATA_A,WDATA_B;
  output reg [W-1:0] RDATA_A,RDATA_B;
  
  reg [W-1:0] mem [D-1:0];
  integer i;
  

  always@(posedge CLK)
    begin
      if(!CS)
        begin
          if(WR_RD_A)
            mem[ADDR_A] <= WDATA_A;
          else
            RDATA_A <= mem[ADDR_A];
        end
    end
  

  always@(posedge CLK)
    begin
      if(!CS)
        begin
          if(WR_RD_B)
            mem[ADDR_B] <= WDATA_B;
          else
            RDATA_B <= mem[ADDR_B];
        end
    end
  
  
  endmodule
module dual_port_RAM(CLK,CS,WR_RD_A,WR_RD_B,ADDR_A,ADDR_B,WDATA_A,WDATA_B,RDATA_A,RDATA_B);

  
  parameter N = 4;
  parameter D = 16;
  parameter W = 8;
  
  input CLK,CS,WR_RD_A,WR_RD_B;
  input [N-1:0] ADDR_A,ADDR_B;
  input [W-1:0] WDATA_A,WDATA_B;
  output reg [W-1:0] RDATA_A,RDATA_B;
  
  reg [W-1:0] mem [D-1:0];
  integer i;
  

  always@(posedge CLK)
    begin
      if(!CS)
        begin
          if(WR_RD_A)
            mem[ADDR_A] <= WDATA_A;
          else
            RDATA_A <= mem[ADDR_A];
        end
    end
  

  always@(posedge CLK)
    begin
      if(!CS)
        begin
          if(WR_RD_B)
            mem[ADDR_B] <= WDATA_B;
          else
            RDATA_B <= mem[ADDR_B];
        end
    end
  
  
  endmodule