data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/ATAND2.v
data/verilator_xmls/e2bd2b7a-ca94-4e33-a2e1-fb9978dd85b0.xml
module ATAND2
    (
     A,
     B,
     Y
     );
input A;
input B;
output Y;

wire   Y;
assign Y = A&B;

endmodule
module ATAND2
    (
     A,
     B,
     Y
     );

input A;
input B;
output Y;

wire   Y;
assign Y = A&B;

endmodule