data/full_repos/permissive/512077043/rgb_sotp/rgb_sotp.v
1: b'%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_sotp/rgb_sotp.v:118: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE2_WAIT_START\' generates 3 bits.\n                                                                            : ... In instance rgb_sotp\n    reg [3:0]       state2 = STATE2_WAIT_START;\n                             ^~~~~~~~~~~~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_sotp/rgb_sotp.v:230: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE2_WAIT_START\' generates 3 bits.\n                                                                            : ... In instance rgb_sotp\n            state2 <= STATE2_WAIT_START;\n                   ^~\n%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_sotp/rgb_sotp.v:242: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE2_OUT_STRM_RST\' generates 3 bits.\n                                                                            : ... In instance rgb_sotp\n                        state2 <= STATE2_OUT_STRM_RST;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_sotp/rgb_sotp.v:245: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 5 bits.\n                                                                            : ... In instance rgb_sotp\n                        s2_outbit_count <= s1_outbit_count - 5\'d1;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_sotp/rgb_sotp.v:250: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE2_SEND_T0H\' generates 3 bits.\n                                                                            : ... In instance rgb_sotp\n                            state2 <= STATE2_SEND_T0H;\n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_sotp/rgb_sotp.v:253: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE2_SEND_T1H\' generates 3 bits.\n                                                                            : ... In instance rgb_sotp\n                            state2 <= STATE2_SEND_T1H;\n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_sotp/rgb_sotp.v:248: Bit extraction of var[7:0] requires 3 bit index, not 5 bits.\n                                                                            : ... In instance rgb_sotp\n                        if (1\'b0 == fifo_dat_red[s1_outbit_count - 5\'d1]) begin  \n                                                ^\n%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_sotp/rgb_sotp.v:264: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE2_SEND_T0L\' generates 3 bits.\n                                                                            : ... In instance rgb_sotp\n                        state2 <= STATE2_SEND_T0L;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_sotp/rgb_sotp.v:270: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE2_WAIT_START\' generates 3 bits.\n                                                                            : ... In instance rgb_sotp\n                        if (4\'d0 == s2_outbit_count) state2 <= STATE2_WAIT_START;\n                                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_sotp/rgb_sotp.v:273: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 5 bits.\n                                                                            : ... In instance rgb_sotp\n                            s2_outbit_count <= s2_outbit_count - 5\'d1;\n                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_sotp/rgb_sotp.v:276: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE2_SEND_T0H\' generates 3 bits.\n                                                                            : ... In instance rgb_sotp\n                                state2 <= STATE2_SEND_T0H;\n                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_sotp/rgb_sotp.v:279: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE2_SEND_T1H\' generates 3 bits.\n                                                                            : ... In instance rgb_sotp\n                                state2 <= STATE2_SEND_T1H;\n                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_sotp/rgb_sotp.v:274: Bit extraction of var[7:0] requires 3 bit index, not 5 bits.\n                                                                            : ... In instance rgb_sotp\n                            if (1\'b0 == s2_dat2send[s2_outbit_count-5\'d1]) begin\n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_sotp/rgb_sotp.v:289: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE2_SEND_T1L\' generates 3 bits.\n                                                                            : ... In instance rgb_sotp\n                        state2 <= STATE2_SEND_T1L;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_sotp/rgb_sotp.v:295: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE2_WAIT_START\' generates 3 bits.\n                                                                            : ... In instance rgb_sotp\n                        if (4\'d0 == s2_outbit_count) state2 <= STATE2_WAIT_START;\n                                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_sotp/rgb_sotp.v:298: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s SUB generates 5 bits.\n                                                                            : ... In instance rgb_sotp\n                            s2_outbit_count <= s2_outbit_count - 5\'d1;\n                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_sotp/rgb_sotp.v:301: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE2_SEND_T0H\' generates 3 bits.\n                                                                            : ... In instance rgb_sotp\n                                state2 <= STATE2_SEND_T0H;\n                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_sotp/rgb_sotp.v:304: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE2_SEND_T1H\' generates 3 bits.\n                                                                            : ... In instance rgb_sotp\n                                state2 <= STATE2_SEND_T1H;\n                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_sotp/rgb_sotp.v:299: Bit extraction of var[7:0] requires 3 bit index, not 5 bits.\n                                                                            : ... In instance rgb_sotp\n                            if (1\'b0 == s2_dat2send[s2_outbit_count-5\'d1]) begin\n                                                   ^\n%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_sotp/rgb_sotp.v:313: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'h0\' generates 5 bits.\n                                                                            : ... In instance rgb_sotp\n                        s2_outbit_count <= 5\'d0;\n                                        ^~\n%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_sotp/rgb_sotp.v:315: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE2_WAIT_START\' generates 3 bits.\n                                                                            : ... In instance rgb_sotp\n                        state2 <= STATE2_WAIT_START;\n                               ^~\n%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_sotp/rgb_sotp.v:318: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s VARREF \'STATE2_WAIT_START\' generates 3 bits.\n                                                                            : ... In instance rgb_sotp\n                default: state2 <= STATE2_WAIT_START;  \n                                ^~\n%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_sotp/rgb_sotp.v:233: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'STATE2_WAIT_START\' generates 3 bits.\n                                                                            : ... In instance rgb_sotp\n            case (state2)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_sotp/rgb_sotp.v:233: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'STATE2_SEND_T0H\' generates 3 bits.\n                                                                            : ... In instance rgb_sotp\n            case (state2)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_sotp/rgb_sotp.v:233: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'STATE2_SEND_T0L\' generates 3 bits.\n                                                                            : ... In instance rgb_sotp\n            case (state2)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_sotp/rgb_sotp.v:233: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'STATE2_SEND_T1H\' generates 3 bits.\n                                                                            : ... In instance rgb_sotp\n            case (state2)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_sotp/rgb_sotp.v:233: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'STATE2_SEND_T1L\' generates 3 bits.\n                                                                            : ... In instance rgb_sotp\n            case (state2)\n            ^~~~\n%Warning-WIDTH: data/full_repos/permissive/512077043/rgb_sotp/rgb_sotp.v:233: Operator CASE expects 4 bits on the Case Item, but Case Item\'s VARREF \'STATE2_OUT_STRM_RST\' generates 3 bits.\n                                                                            : ... In instance rgb_sotp\n            case (state2)\n            ^~~~\n%Error: Exiting due to 28 warning(s)\n'
module  rgb_sotp #(


    parameter RGBW_T0H = 16,
    parameter RGBW_T0L = 74,
    parameter RGBW_T1H = 45,
    parameter RGBW_T1L = 45,
    parameter RGBW_STR_RST = 7681,
    parameter COUNTER_MAX = 7800
) (


    input           clk,
    input           rst,
    input           in_rd_fifo_empty,
    input [31:0]    in_rd_fifo_data,
    
    

    output reg      out_rd_fifo_en,
    output reg      out_sig
);


    localparam WIDTH = $clog2(COUNTER_MAX + 1);
    localparam WID_MSB = WIDTH-1;

    localparam bnum_valid             = 5'd31;
    localparam bnum_stream_reset      = 5'd30;
    localparam bnum_G_first_data_bit  = 5'd23;
    localparam bnum_G_last_data_bit   = 5'd16;
    localparam bnum_R_first_data_bit  = 5'd15;
    localparam bnum_R_last_data_bit   = 5'd8;
    localparam bnum_B_first_data_bit  = 5'd7;
    localparam bnum_B_last_data_bit   = 5'd0;



    localparam STATE1_WAIT_FIFO      = 4'd0;
    localparam STATE1_GET_FIFO_DAT1  = 4'd1;
    localparam STATE1_GET_FIFO_DAT2  = 4'd2;
    localparam STATE1_CNVRT_DAT_1    = 4'd3;
    localparam STATE1_CNVRT_DAT_2    = 4'd4;
    localparam STATE1_CNVRT_DAT_3    = 4'd5;
    localparam STATE1_OUT_RED        = 4'd6;
    localparam STATE1_OUT_GREEN      = 4'd7;
    localparam STATE1_OUT_BLUE       = 4'd8;
    localparam STATE1_OUT_LAST       = 4'd9;


    localparam STATE2_WAIT_START    = 3'd0;
    localparam STATE2_SEND_T0H      = 3'd1;
    localparam STATE2_SEND_T0L      = 3'd2;
    localparam STATE2_SEND_T1H      = 3'd3;
    localparam STATE2_SEND_T1L      = 3'd4;
    localparam STATE2_OUT_STRM_RST  = 3'd5;


    wire            sig_edge;


    reg [1:0]       rstff = 2'b00;


    reg [3:0]       state1 = STATE1_WAIT_FIFO;

    reg [7:0]       fifo_dat_red = 8'b0;
    reg [7:0]       fifo_dat_green = 8'b0;
    reg [7:0]       fifo_dat_blue = 8'b0;
    reg [7:0]       calc_min_color = 8'b0;


    reg [3:0]       state2 = STATE2_WAIT_START;
    reg [WID_MSB:0] outserial_count = 13'd0;
    reg [3:0]       s1_outbit_count = 4'd0;
    reg             s1_datasend_en = 1'd0;
    reg [3:0]       s2_outbit_count = 4'd0;
    reg             s2_datasend_rcvd = 1'd0;
    reg [7:0]       s2_dat2send = 8'b0;


    

    always @ (posedge clk) begin

        if (rst == 1'b1) rstff <= 2'b11;
        else             rstff <= {rstff[0], 1'b0};

        if (rstff[1] == 1'b1) begin
            out_rd_fifo_en <= 1'b0;
            fifo_dat_red <= 8'b0;
            fifo_dat_green <= 8'b0;
            fifo_dat_blue <= 8'b0;
            calc_min_color <= 8'b0;
            s1_datasend_en = 1'd0;
            s1_outbit_count <= 4'd0;
            state1 <= STATE1_WAIT_FIFO;
        end else begin
            if (1'b1 == s2_datasend_rcvd) begin
                s1_outbit_count <= 4'd0;
                s1_datasend_en = 1'd0;
            end
            case (state1)
                STATE1_WAIT_FIFO: begin
                    if (1'b0 == in_rd_fifo_empty) begin
                        out_rd_fifo_en <= 1'b1;
                        state1 <= STATE1_GET_FIFO_DAT1;
                    end
                end
                STATE1_GET_FIFO_DAT1: begin
                    out_rd_fifo_en <= 1'b0;
                    state1 <= STATE1_GET_FIFO_DAT2;
                end
                STATE1_GET_FIFO_DAT2: begin
                    if (1'b0 == in_rd_fifo_data[bnum_valid]) begin
                        state1 <= STATE1_WAIT_FIFO;
                    end else if (1'b1 == in_rd_fifo_data[bnum_stream_reset]) begin
                        s1_outbit_count <= 4'd15;
                        s1_datasend_en = 1'd1;
                        state1 <= STATE1_OUT_LAST;
                    end else begin
                        fifo_dat_red   <= in_rd_fifo_data[bnum_R_first_data_bit:bnum_R_last_data_bit];
                        fifo_dat_green <= in_rd_fifo_data[bnum_G_first_data_bit:bnum_G_last_data_bit];
                        fifo_dat_blue  <= in_rd_fifo_data[bnum_B_first_data_bit:bnum_B_last_data_bit];
                        if (in_rd_fifo_data[bnum_R_first_data_bit:bnum_R_last_data_bit] > in_rd_fifo_data[bnum_B_first_data_bit:bnum_B_last_data_bit]) begin
                            calc_min_color <= in_rd_fifo_data[bnum_B_first_data_bit:bnum_B_last_data_bit];
                        end else begin
                            calc_min_color <= in_rd_fifo_data[bnum_R_first_data_bit:bnum_R_last_data_bit];
                        end
                        state1 <= STATE1_CNVRT_DAT_1;
                    end
                end
                STATE1_CNVRT_DAT_1: begin
                    if (calc_min_color > fifo_dat_green) calc_min_color <= fifo_dat_green;
                    state1 <= STATE1_CNVRT_DAT_2;
                end
                STATE1_CNVRT_DAT_2: begin
                    fifo_dat_red   <= fifo_dat_red - calc_min_color;
                    fifo_dat_green <= fifo_dat_green - calc_min_color;
                    fifo_dat_blue  <= fifo_dat_blue - calc_min_color;
                    s1_outbit_count <= 4'd8;
                    s1_datasend_en = 1'd1;
                    state1 <= STATE1_OUT_RED;
                end
                STATE1_OUT_RED: begin
                    if ((1'b0 == s1_datasend_en) && (4'd0 == s2_outbit_count)) begin
                        fifo_dat_red <= fifo_dat_green;
                        s1_outbit_count <= 4'd8;
                        s1_datasend_en = 1'd1;
                        state1 <= STATE1_OUT_GREEN;
                    end
                end
                STATE1_OUT_GREEN: begin
                    if ((1'b0 == s1_datasend_en) && (4'd0 == s2_outbit_count)) begin
                        fifo_dat_red <= fifo_dat_blue;
                        s1_outbit_count <= 4'd8;
                        s1_datasend_en = 1'd1;
                        state1 <= STATE1_OUT_BLUE;
                    end
                end
                STATE1_OUT_BLUE: begin
                    if ((1'b0 == s1_datasend_en) && (4'd0 == s2_outbit_count)) begin
                        fifo_dat_red <= calc_min_color;
                        s1_outbit_count <= 4'd8;
                        s1_datasend_en = 1'd1;
                        state1 <= STATE1_OUT_LAST;
                    end
                end
                STATE1_OUT_LAST: begin
                    if ((1'b0 == s1_datasend_en) && (4'd0 == s2_outbit_count)) begin
                        state1 <= STATE1_WAIT_FIFO;
                    end
                end
                default: state1 <= STATE1_WAIT_FIFO;
            endcase
        end
    end

    always @ (posedge clk) begin
        if (rstff[1] == 1'b1) begin
            out_sig <= 1'b0;
            outserial_count <= 13'd0;
            s2_outbit_count <= 4'd0;
            s2_datasend_rcvd <= 1'b0;
            state2 <= STATE2_WAIT_START;
        end else begin
            if (1'b0 == s1_datasend_en) s2_datasend_rcvd <= 1'b0;;
            case (state2)
                STATE2_WAIT_START: begin
                    if ((1'b1 == s1_datasend_en) && (4'd15 == s1_outbit_count)) begin
                        outserial_count <= RGBW_STR_RST;
                        s2_outbit_count <= s1_outbit_count;
                        s2_dat2send <= 8'b0;
                        s2_datasend_rcvd <= 1'b1;
                        out_sig <= 1'b0;
                        outserial_count <= RGBW_STR_RST - 13'd1;
                        state2 <= STATE2_OUT_STRM_RST;
                    end else if ((1'b1 == s1_datasend_en) && (4'd0 != s1_outbit_count)) begin
                        out_sig <= 1'b1;
                        s2_outbit_count <= s1_outbit_count - 5'd1;
                        s2_dat2send <= fifo_dat_red;
                        s2_datasend_rcvd <= 1'b1;
                        if (1'b0 == fifo_dat_red[s1_outbit_count - 5'd1]) begin
                            outserial_count <= RGBW_T0H-13'd1;
                            state2 <= STATE2_SEND_T0H;
                        end else begin
                            outserial_count <= RGBW_T1H-13'd1;
                            state2 <= STATE2_SEND_T1H;
                        end
                    end else begin
                        s2_datasend_rcvd <= 1'b0;
                    end
                end
                STATE2_SEND_T0H: begin
                    if (13'd0 != outserial_count) outserial_count <= outserial_count - 13'd1;
                    else begin
                        out_sig <= 1'b0;
                        outserial_count <= RGBW_T0L-13'd1;
                        state2 <= STATE2_SEND_T0L;
                    end
                end
                STATE2_SEND_T0L: begin
                    if (13'd0 != outserial_count) outserial_count <= outserial_count - 13'd1;
                    else begin
                        if (4'd0 == s2_outbit_count) state2 <= STATE2_WAIT_START;
                        else begin
                            out_sig <= 1'b1;
                            s2_outbit_count <= s2_outbit_count - 5'd1;
                            if (1'b0 == s2_dat2send[s2_outbit_count-5'd1]) begin
                                outserial_count <= RGBW_T0H-13'd1;
                                state2 <= STATE2_SEND_T0H;
                            end else begin
                                outserial_count <= RGBW_T1H-13'd1;
                                state2 <= STATE2_SEND_T1H;
                            end
                        end
                    end
                end
                STATE2_SEND_T1H: begin
                    if (13'd0 != outserial_count) outserial_count <= outserial_count - 13'd1;
                    else begin
                        out_sig <= 1'b0;
                        outserial_count <= RGBW_T1L-13'd1;
                        state2 <= STATE2_SEND_T1L;
                    end
                end
                STATE2_SEND_T1L: begin
                    if (13'd0 != outserial_count) outserial_count <= outserial_count - 13'd1;
                    else begin
                        if (4'd0 == s2_outbit_count) state2 <= STATE2_WAIT_START;
                        else begin
                            out_sig <= 1'b1;
                            s2_outbit_count <= s2_outbit_count - 5'd1;
                            if (1'b0 == s2_dat2send[s2_outbit_count-5'd1]) begin
                                outserial_count <= RGBW_T0H-13'd1;
                                state2 <= STATE2_SEND_T0H;
                            end else begin
                                outserial_count <= RGBW_T1H-13'd1;
                                state2 <= STATE2_SEND_T1H;
                            end
                        end
                    end
                end
                STATE2_OUT_STRM_RST: begin
                    out_sig <= 1'b0;
                    if (13'd1 != outserial_count) outserial_count <= outserial_count - 13'd1;
                    else begin
                        s2_outbit_count <= 5'd0;
                        outserial_count <= 13'd0;
                        state2 <= STATE2_WAIT_START;
                    end 
                end
                default: state2 <= STATE2_WAIT_START;
            endcase
        end
    end
    
endmodule
module  rgb_sotp #(


    parameter RGBW_T0H = 16,
    parameter RGBW_T0L = 74,
    parameter RGBW_T1H = 45,
    parameter RGBW_T1L = 45,
    parameter RGBW_STR_RST = 7681,
    parameter COUNTER_MAX = 7800
) (


    input           clk,
    input           rst,
    input           in_rd_fifo_empty,
    input [31:0]    in_rd_fifo_data,
    
    

    output reg      out_rd_fifo_en,
    output reg      out_sig
);



    localparam WIDTH = $clog2(COUNTER_MAX + 1);
    localparam WID_MSB = WIDTH-1;

    localparam bnum_valid             = 5'd31;
    localparam bnum_stream_reset      = 5'd30;
    localparam bnum_G_first_data_bit  = 5'd23;
    localparam bnum_G_last_data_bit   = 5'd16;
    localparam bnum_R_first_data_bit  = 5'd15;
    localparam bnum_R_last_data_bit   = 5'd8;
    localparam bnum_B_first_data_bit  = 5'd7;
    localparam bnum_B_last_data_bit   = 5'd0;



    localparam STATE1_WAIT_FIFO      = 4'd0;
    localparam STATE1_GET_FIFO_DAT1  = 4'd1;
    localparam STATE1_GET_FIFO_DAT2  = 4'd2;
    localparam STATE1_CNVRT_DAT_1    = 4'd3;
    localparam STATE1_CNVRT_DAT_2    = 4'd4;
    localparam STATE1_CNVRT_DAT_3    = 4'd5;
    localparam STATE1_OUT_RED        = 4'd6;
    localparam STATE1_OUT_GREEN      = 4'd7;
    localparam STATE1_OUT_BLUE       = 4'd8;
    localparam STATE1_OUT_LAST       = 4'd9;


    localparam STATE2_WAIT_START    = 3'd0;
    localparam STATE2_SEND_T0H      = 3'd1;
    localparam STATE2_SEND_T0L      = 3'd2;
    localparam STATE2_SEND_T1H      = 3'd3;
    localparam STATE2_SEND_T1L      = 3'd4;
    localparam STATE2_OUT_STRM_RST  = 3'd5;


    wire            sig_edge;


    reg [1:0]       rstff = 2'b00;


    reg [3:0]       state1 = STATE1_WAIT_FIFO;

    reg [7:0]       fifo_dat_red = 8'b0;
    reg [7:0]       fifo_dat_green = 8'b0;
    reg [7:0]       fifo_dat_blue = 8'b0;
    reg [7:0]       calc_min_color = 8'b0;


    reg [3:0]       state2 = STATE2_WAIT_START;
    reg [WID_MSB:0] outserial_count = 13'd0;
    reg [3:0]       s1_outbit_count = 4'd0;
    reg             s1_datasend_en = 1'd0;
    reg [3:0]       s2_outbit_count = 4'd0;
    reg             s2_datasend_rcvd = 1'd0;
    reg [7:0]       s2_dat2send = 8'b0;


    

    always @ (posedge clk) begin

        if (rst == 1'b1) rstff <= 2'b11;
        else             rstff <= {rstff[0], 1'b0};

        if (rstff[1] == 1'b1) begin
            out_rd_fifo_en <= 1'b0;
            fifo_dat_red <= 8'b0;
            fifo_dat_green <= 8'b0;
            fifo_dat_blue <= 8'b0;
            calc_min_color <= 8'b0;
            s1_datasend_en = 1'd0;
            s1_outbit_count <= 4'd0;
            state1 <= STATE1_WAIT_FIFO;
        end else begin
            if (1'b1 == s2_datasend_rcvd) begin
                s1_outbit_count <= 4'd0;
                s1_datasend_en = 1'd0;
            end
            case (state1)
                STATE1_WAIT_FIFO: begin
                    if (1'b0 == in_rd_fifo_empty) begin
                        out_rd_fifo_en <= 1'b1;
                        state1 <= STATE1_GET_FIFO_DAT1;
                    end
                end
                STATE1_GET_FIFO_DAT1: begin
                    out_rd_fifo_en <= 1'b0;
                    state1 <= STATE1_GET_FIFO_DAT2;
                end
                STATE1_GET_FIFO_DAT2: begin
                    if (1'b0 == in_rd_fifo_data[bnum_valid]) begin
                        state1 <= STATE1_WAIT_FIFO;
                    end else if (1'b1 == in_rd_fifo_data[bnum_stream_reset]) begin
                        s1_outbit_count <= 4'd15;
                        s1_datasend_en = 1'd1;
                        state1 <= STATE1_OUT_LAST;
                    end else begin
                        fifo_dat_red   <= in_rd_fifo_data[bnum_R_first_data_bit:bnum_R_last_data_bit];
                        fifo_dat_green <= in_rd_fifo_data[bnum_G_first_data_bit:bnum_G_last_data_bit];
                        fifo_dat_blue  <= in_rd_fifo_data[bnum_B_first_data_bit:bnum_B_last_data_bit];
                        if (in_rd_fifo_data[bnum_R_first_data_bit:bnum_R_last_data_bit] > in_rd_fifo_data[bnum_B_first_data_bit:bnum_B_last_data_bit]) begin
                            calc_min_color <= in_rd_fifo_data[bnum_B_first_data_bit:bnum_B_last_data_bit];
                        end else begin
                            calc_min_color <= in_rd_fifo_data[bnum_R_first_data_bit:bnum_R_last_data_bit];
                        end
                        state1 <= STATE1_CNVRT_DAT_1;
                    end
                end
                STATE1_CNVRT_DAT_1: begin
                    if (calc_min_color > fifo_dat_green) calc_min_color <= fifo_dat_green;
                    state1 <= STATE1_CNVRT_DAT_2;
                end
                STATE1_CNVRT_DAT_2: begin
                    fifo_dat_red   <= fifo_dat_red - calc_min_color;
                    fifo_dat_green <= fifo_dat_green - calc_min_color;
                    fifo_dat_blue  <= fifo_dat_blue - calc_min_color;
                    s1_outbit_count <= 4'd8;
                    s1_datasend_en = 1'd1;
                    state1 <= STATE1_OUT_RED;
                end
                STATE1_OUT_RED: begin
                    if ((1'b0 == s1_datasend_en) && (4'd0 == s2_outbit_count)) begin
                        fifo_dat_red <= fifo_dat_green;
                        s1_outbit_count <= 4'd8;
                        s1_datasend_en = 1'd1;
                        state1 <= STATE1_OUT_GREEN;
                    end
                end
                STATE1_OUT_GREEN: begin
                    if ((1'b0 == s1_datasend_en) && (4'd0 == s2_outbit_count)) begin
                        fifo_dat_red <= fifo_dat_blue;
                        s1_outbit_count <= 4'd8;
                        s1_datasend_en = 1'd1;
                        state1 <= STATE1_OUT_BLUE;
                    end
                end
                STATE1_OUT_BLUE: begin
                    if ((1'b0 == s1_datasend_en) && (4'd0 == s2_outbit_count)) begin
                        fifo_dat_red <= calc_min_color;
                        s1_outbit_count <= 4'd8;
                        s1_datasend_en = 1'd1;
                        state1 <= STATE1_OUT_LAST;
                    end
                end
                STATE1_OUT_LAST: begin
                    if ((1'b0 == s1_datasend_en) && (4'd0 == s2_outbit_count)) begin
                        state1 <= STATE1_WAIT_FIFO;
                    end
                end
                default: state1 <= STATE1_WAIT_FIFO;
            endcase
        end
    end

    always @ (posedge clk) begin
        if (rstff[1] == 1'b1) begin
            out_sig <= 1'b0;
            outserial_count <= 13'd0;
            s2_outbit_count <= 4'd0;
            s2_datasend_rcvd <= 1'b0;
            state2 <= STATE2_WAIT_START;
        end else begin
            if (1'b0 == s1_datasend_en) s2_datasend_rcvd <= 1'b0;;
            case (state2)
                STATE2_WAIT_START: begin
                    if ((1'b1 == s1_datasend_en) && (4'd15 == s1_outbit_count)) begin
                        outserial_count <= RGBW_STR_RST;
                        s2_outbit_count <= s1_outbit_count;
                        s2_dat2send <= 8'b0;
                        s2_datasend_rcvd <= 1'b1;
                        out_sig <= 1'b0;
                        outserial_count <= RGBW_STR_RST - 13'd1;
                        state2 <= STATE2_OUT_STRM_RST;
                    end else if ((1'b1 == s1_datasend_en) && (4'd0 != s1_outbit_count)) begin
                        out_sig <= 1'b1;
                        s2_outbit_count <= s1_outbit_count - 5'd1;
                        s2_dat2send <= fifo_dat_red;
                        s2_datasend_rcvd <= 1'b1;
                        if (1'b0 == fifo_dat_red[s1_outbit_count - 5'd1]) begin
                            outserial_count <= RGBW_T0H-13'd1;
                            state2 <= STATE2_SEND_T0H;
                        end else begin
                            outserial_count <= RGBW_T1H-13'd1;
                            state2 <= STATE2_SEND_T1H;
                        end
                    end else begin
                        s2_datasend_rcvd <= 1'b0;
                    end
                end
                STATE2_SEND_T0H: begin
                    if (13'd0 != outserial_count) outserial_count <= outserial_count - 13'd1;
                    else begin
                        out_sig <= 1'b0;
                        outserial_count <= RGBW_T0L-13'd1;
                        state2 <= STATE2_SEND_T0L;
                    end
                end
                STATE2_SEND_T0L: begin
                    if (13'd0 != outserial_count) outserial_count <= outserial_count - 13'd1;
                    else begin
                        if (4'd0 == s2_outbit_count) state2 <= STATE2_WAIT_START;
                        else begin
                            out_sig <= 1'b1;
                            s2_outbit_count <= s2_outbit_count - 5'd1;
                            if (1'b0 == s2_dat2send[s2_outbit_count-5'd1]) begin
                                outserial_count <= RGBW_T0H-13'd1;
                                state2 <= STATE2_SEND_T0H;
                            end else begin
                                outserial_count <= RGBW_T1H-13'd1;
                                state2 <= STATE2_SEND_T1H;
                            end
                        end
                    end
                end
                STATE2_SEND_T1H: begin
                    if (13'd0 != outserial_count) outserial_count <= outserial_count - 13'd1;
                    else begin
                        out_sig <= 1'b0;
                        outserial_count <= RGBW_T1L-13'd1;
                        state2 <= STATE2_SEND_T1L;
                    end
                end
                STATE2_SEND_T1L: begin
                    if (13'd0 != outserial_count) outserial_count <= outserial_count - 13'd1;
                    else begin
                        if (4'd0 == s2_outbit_count) state2 <= STATE2_WAIT_START;
                        else begin
                            out_sig <= 1'b1;
                            s2_outbit_count <= s2_outbit_count - 5'd1;
                            if (1'b0 == s2_dat2send[s2_outbit_count-5'd1]) begin
                                outserial_count <= RGBW_T0H-13'd1;
                                state2 <= STATE2_SEND_T0H;
                            end else begin
                                outserial_count <= RGBW_T1H-13'd1;
                                state2 <= STATE2_SEND_T1H;
                            end
                        end
                    end
                end
                STATE2_OUT_STRM_RST: begin
                    out_sig <= 1'b0;
                    if (13'd1 != outserial_count) outserial_count <= outserial_count - 13'd1;
                    else begin
                        s2_outbit_count <= 5'd0;
                        outserial_count <= 13'd0;
                        state2 <= STATE2_WAIT_START;
                    end 
                end
                default: state2 <= STATE2_WAIT_START;
            endcase
        end
    end
    
endmodule