data/full_repos/permissive/423547971/FPGA Projects/PmodENC/seg7_control.v
1: b'%Error: Cannot find file containing module: Projects/PmodENC,data/full_repos/permissive/423547971\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/PmodENC,data/full_repos/permissive/423547971\n             data/full_repos/permissive/423547971/FPGA/Projects/PmodENC,data/full_repos/permissive/423547971.v\n             data/full_repos/permissive/423547971/FPGA/Projects/PmodENC,data/full_repos/permissive/423547971.sv\n             Projects/PmodENC,data/full_repos/permissive/423547971\n             Projects/PmodENC,data/full_repos/permissive/423547971.v\n             Projects/PmodENC,data/full_repos/permissive/423547971.sv\n             obj_dir/Projects/PmodENC,data/full_repos/permissive/423547971\n             obj_dir/Projects/PmodENC,data/full_repos/permissive/423547971.v\n             obj_dir/Projects/PmodENC,data/full_repos/permissive/423547971.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: Projects/PmodENC/seg7_control.v\n%Error: Exiting due to 3 error(s)\n'
module seg7_control(
    input clk,
    input sw,
    output [4:0] enc,
    output reg [3:0] anode,
    output reg [6:0] seg_out
    );

	reg [17:0] sclk;
	reg [6:0] seg_reg;

	always @(posedge clk)  begin


		if(sw == 1'b0)
			anode <= 4'b1111;	


		else

			if(sclk == 0) begin
				anode <= 4'b1110;
				seg_out <= seg_reg;
				sclk <= sclk + 1;
			end


			else if(sclk == 100_000) begin

				if(enc > 9) begin
					seg_out <= 7'b1111001;
					anode <= 4'b1101;
				end
									
				sclk <= sclk + 1;									
			end


			else if(sclk == 200_000)	
				sclk <= 0;


			else	
				sclk <= sclk + 1;						
	 end
	 

	 always @(enc[4] or enc[3] or enc[2] or enc[1] or enc[0])
	   case (enc[4:0])

			5'b00000 : seg_reg <= 7'b1000000;
			5'b00001 : seg_reg <= 7'b1111001;
			5'b00010 : seg_reg <= 7'b0100100;
			5'b00011 : seg_reg <= 7'b0110000;
			5'b00100 : seg_reg <= 7'b0011001;
			5'b00101 : seg_reg <= 7'b0010010;
			5'b00110 : seg_reg <= 7'b0000010;
			5'b00111 : seg_reg <= 7'b1111000;
			5'b01000 : seg_reg <= 7'b0000000;
			5'b01001 : seg_reg <= 7'b0010000;
			5'b01010 : seg_reg <= 7'b1000000;
			5'b01011 : seg_reg <= 7'b1111001;
			5'b01100 : seg_reg <= 7'b0100100;
			5'b01101 : seg_reg <= 7'b0110000;
			5'b01110 : seg_reg <= 7'b0011001;
			5'b01111 : seg_reg <= 7'b0010010;
			5'b10000 : seg_reg <= 7'b0000010;
			5'b10001 : seg_reg <= 7'b1111000;
			5'b10010 : seg_reg <= 7'b0000000;
			5'b10011 : seg_reg <= 7'b0010000;
			default  : seg_reg <= 7'b0111111;

	   endcase

endmodule
module seg7_control(
    input clk,
    input sw,
    output [4:0] enc,
    output reg [3:0] anode,
    output reg [6:0] seg_out
    );


	reg [17:0] sclk;
	reg [6:0] seg_reg;

	always @(posedge clk)  begin


		if(sw == 1'b0)
			anode <= 4'b1111;	


		else

			if(sclk == 0) begin
				anode <= 4'b1110;
				seg_out <= seg_reg;
				sclk <= sclk + 1;
			end


			else if(sclk == 100_000) begin

				if(enc > 9) begin
					seg_out <= 7'b1111001;
					anode <= 4'b1101;
				end
									
				sclk <= sclk + 1;									
			end


			else if(sclk == 200_000)	
				sclk <= 0;


			else	
				sclk <= sclk + 1;						
	 end
	 

	 always @(enc[4] or enc[3] or enc[2] or enc[1] or enc[0])
	   case (enc[4:0])

			5'b00000 : seg_reg <= 7'b1000000;
			5'b00001 : seg_reg <= 7'b1111001;
			5'b00010 : seg_reg <= 7'b0100100;
			5'b00011 : seg_reg <= 7'b0110000;
			5'b00100 : seg_reg <= 7'b0011001;
			5'b00101 : seg_reg <= 7'b0010010;
			5'b00110 : seg_reg <= 7'b0000010;
			5'b00111 : seg_reg <= 7'b1111000;
			5'b01000 : seg_reg <= 7'b0000000;
			5'b01001 : seg_reg <= 7'b0010000;
			5'b01010 : seg_reg <= 7'b1000000;
			5'b01011 : seg_reg <= 7'b1111001;
			5'b01100 : seg_reg <= 7'b0100100;
			5'b01101 : seg_reg <= 7'b0110000;
			5'b01110 : seg_reg <= 7'b0011001;
			5'b01111 : seg_reg <= 7'b0010010;
			5'b10000 : seg_reg <= 7'b0000010;
			5'b10001 : seg_reg <= 7'b1111000;
			5'b10010 : seg_reg <= 7'b0000000;
			5'b10011 : seg_reg <= 7'b0010000;
			default  : seg_reg <= 7'b0111111;

	   endcase

endmodule