data/full_repos/permissive/469312749/alu/work/verilog/arith_16_7.v
1: b'%Warning-WIDTH: data/full_repos/permissive/469312749/alu/work/verilog/arith_16_7.v:33: Operator SUB expects 16 bits on the LHS, but LHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                     : ... In instance arith_16_7\n        xb = 1\'h0 - y;\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module arith_16_7 (
    input [15:0] x,
    input [15:0] y,
    input [1:0] arithAlufn,
    output reg [15:0] arithOut,
    output reg z,
    output reg v,
    output reg n
  );
  
  
  
  reg [15:0] temp;
  
  reg [15:0] xb;
  
  always @* begin
    
    case (arithAlufn)
      2'h0: begin
        temp = $signed(x) + $signed(y);
        xb = y;
        v = ((x[15+0-:1] & y[15+0-:1] & (~temp[15+0-:1])) | ((~x[15+0-:1]) & (~y[15+0-:1]) & temp[15+0-:1]));
      end
      2'h1: begin
        temp = $signed(x) - $signed(y);
        xb = 1'h0 - y;
        v = ((x[15+0-:1] & xb[15+0-:1] & (~temp[15+0-:1])) | ((~x[15+0-:1]) & (~xb[15+0-:1]) & temp[15+0-:1]));
      end
      2'h2: begin
        temp = x * y;
        v = 1'h0;
      end
      default: begin
        temp = 16'h0000;
        v = 1'h0;
      end
    endcase
    n = temp[15+0-:1];
    z = ~(|temp);
    arithOut = temp;
  end
endmodule
module arith_16_7 (
    input [15:0] x,
    input [15:0] y,
    input [1:0] arithAlufn,
    output reg [15:0] arithOut,
    output reg z,
    output reg v,
    output reg n
  );

  
  
  
  reg [15:0] temp;
  
  reg [15:0] xb;
  
  always @* begin
    
    case (arithAlufn)
      2'h0: begin
        temp = $signed(x) + $signed(y);
        xb = y;
        v = ((x[15+0-:1] & y[15+0-:1] & (~temp[15+0-:1])) | ((~x[15+0-:1]) & (~y[15+0-:1]) & temp[15+0-:1]));
      end
      2'h1: begin
        temp = $signed(x) - $signed(y);
        xb = 1'h0 - y;
        v = ((x[15+0-:1] & xb[15+0-:1] & (~temp[15+0-:1])) | ((~x[15+0-:1]) & (~xb[15+0-:1]) & temp[15+0-:1]));
      end
      2'h2: begin
        temp = x * y;
        v = 1'h0;
      end
      default: begin
        temp = 16'h0000;
        v = 1'h0;
      end
    endcase
    n = temp[15+0-:1];
    z = ~(|temp);
    arithOut = temp;
  end
endmodule