data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/halfband_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/halfband_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clock <= ~clock ;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/halfband_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n    initial #100 reset = 1\'b0 ;\n            ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/halfband_tb.v:65: Unsupported or unknown PLI call: $timeformat\n        $timeformat(-9, 2, " ns", 10) ;\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/halfband_tb.v:79: syntax error, unexpected \'@\'\n        @(negedge reset) #0 ;\n        ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/halfband_tb.v:85: syntax error, unexpected \'@\'\n            @( posedge clock ) begin\n            ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/halfband_tb.v:97: syntax error, unexpected \'@\'\n                @(posedge clock) begin\n                ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/halfband_tb.v:103: syntax error, unexpected \'@\'\n                    @(posedge clock) #1 ;\n                    ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/halfband_tb.v:106: syntax error, unexpected end\n        end\n        ^~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/halfband_tb.v:126: syntax error, unexpected $display\n                        $display( "%t: %d != %d", $realtime, data_out, compare ) ;\n                        ^~~~~~~~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module halfband_tb( ) ;
    

    parameter               clocks  = 2 ;
    parameter               decim   = 0 ;
    parameter               rate    = 2 ;

    reg                     clock ;
    reg                     reset ;
    reg                     enable ;
    reg                     strobe_in ;
    reg     signed  [17:0]  data_in ;
    wire                    strobe_out ;
    wire    signed  [17:0]  data_out ;


    initial clock = 1'b0 ;
    always #5 clock <= ~clock ;


    initial reset = 1'b1 ;
    initial #100 reset = 1'b0 ;


    initial enable = 1'b1 ;


    halfband_ideal 
      #(
        .decim      ( decim         ),
        .rate       ( rate          )
      ) uut(
        .clock      ( clock         ),
        .reset      ( reset         ),
        .enable     ( enable        ),
        .strobe_in  ( strobe_in     ),
        .data_in    ( data_in       ),
        .strobe_out ( strobe_out    ),
        .data_out   ( data_out      )
      ) ;
    
    integer i, ri, ro, infile, outfile ;


    initial begin
        infile = $fopen("input.dat","r") ;
        outfile = $fopen("output.dat","r") ;
        $timeformat(-9, 2, " ns", 10) ;
    end

    reg                 endofsim ;
    reg signed  [17:0]  compare ;
    integer             noe ;
    initial             noe = 0 ;

    initial begin

        strobe_in <= 1'd0 ;
        data_in <= 18'd0 ;


        @(negedge reset) #0 ;
        

        while( !endofsim ) begin


            @( posedge clock ) begin
                #1 ;
                strobe_in <= 1'b1 ;
                if( !$feof(infile) )
                    ri = $fscanf( infile, "%d", data_in ) ;
                else
                    data_in <= 18'd0 ;
            end



            if( clocks > 1 ) begin
                @(posedge clock) begin
                    strobe_in <= 1'b0  ;
                end


                for( i = 0 ; i < (clocks-2) ; i = i + 1 ) begin
                    @(posedge clock) #1 ;
                end
            end
        end


        if( noe )
            $display( "FAILED: %d errors during simulation", noe ) ;
        else
            $display( "PASSED: Simulation successful" ) ;

        $stop ;
    end


    always @ (posedge clock) begin
        if( reset )
            endofsim <= 1'b0 ;
        else begin
            if( !$feof(outfile) ) begin
                if( strobe_out ) begin
                    ro = $fscanf( outfile, "%d\n", compare ) ;
                    if( compare != data_out ) begin
                        $display( "%t: %d != %d", $realtime, data_out, compare ) ;
                        noe = noe + 1 ;
                    end
                end
            end else begin

                endofsim <= 1'b1 ;
            end
        end
    end     

endmodule
module halfband_tb( ) ;

    

    parameter               clocks  = 2 ;
    parameter               decim   = 0 ;
    parameter               rate    = 2 ;

    reg                     clock ;
    reg                     reset ;
    reg                     enable ;
    reg                     strobe_in ;
    reg     signed  [17:0]  data_in ;
    wire                    strobe_out ;
    wire    signed  [17:0]  data_out ;


    initial clock = 1'b0 ;
    always #5 clock <= ~clock ;


    initial reset = 1'b1 ;
    initial #100 reset = 1'b0 ;


    initial enable = 1'b1 ;


    halfband_ideal 
      #(
        .decim      ( decim         ),
        .rate       ( rate          )
      ) uut(
        .clock      ( clock         ),
        .reset      ( reset         ),
        .enable     ( enable        ),
        .strobe_in  ( strobe_in     ),
        .data_in    ( data_in       ),
        .strobe_out ( strobe_out    ),
        .data_out   ( data_out      )
      ) ;
    
    integer i, ri, ro, infile, outfile ;


    initial begin
        infile = $fopen("input.dat","r") ;
        outfile = $fopen("output.dat","r") ;
        $timeformat(-9, 2, " ns", 10) ;
    end

    reg                 endofsim ;
    reg signed  [17:0]  compare ;
    integer             noe ;
    initial             noe = 0 ;

    initial begin

        strobe_in <= 1'd0 ;
        data_in <= 18'd0 ;


        @(negedge reset) #0 ;
        

        while( !endofsim ) begin


            @( posedge clock ) begin
                #1 ;
                strobe_in <= 1'b1 ;
                if( !$feof(infile) )
                    ri = $fscanf( infile, "%d", data_in ) ;
                else
                    data_in <= 18'd0 ;
            end



            if( clocks > 1 ) begin
                @(posedge clock) begin
                    strobe_in <= 1'b0  ;
                end


                for( i = 0 ; i < (clocks-2) ; i = i + 1 ) begin
                    @(posedge clock) #1 ;
                end
            end
        end


        if( noe )
            $display( "FAILED: %d errors during simulation", noe ) ;
        else
            $display( "PASSED: Simulation successful" ) ;

        $stop ;
    end


    always @ (posedge clock) begin
        if( reset )
            endofsim <= 1'b0 ;
        else begin
            if( !$feof(outfile) ) begin
                if( strobe_out ) begin
                    ro = $fscanf( outfile, "%d\n", compare ) ;
                    if( compare != data_out ) begin
                        $display( "%t: %d != %d", $realtime, data_out, compare ) ;
                        noe = noe + 1 ;
                    end
                end
            end else begin

                endofsim <= 1'b1 ;
            end
        end
    end     

endmodule