data/full_repos/permissive/493019833/test/testcase/firrtl/EmptyChirrtlMem/reference/EmptyChirrtlMem.v
data/verilator_xmls/f5b9c1de-65ff-47b4-a3cd-cca22c4f8b30.xml
module Queue(
    input clock
);
endmodule
module Queue(
    input clock
);

endmodule