data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_clk_gclk_inv_288x.v
data/verilator_xmls/7d8b22b4-058d-413f-bf47-3b2ce479f838.xml
module bw_clk_gclk_inv_288x (
    clkout,
    clkin );

    output clkout;
    input  clkin;
 
    assign clkout = ~( clkin );

endmodule
module bw_clk_gclk_inv_288x (
    clkout,
    clkin );


    output clkout;
    input  clkin;
 
    assign clkout = ~( clkin );

endmodule