data/full_repos/permissive/418331750/periph/flash/spi_flash_ctrl.v
1: b'%Error: data/full_repos/permissive/418331750/periph/flash/spi_flash_ctrl.v:1: Cannot find include file: ./periph/flash/spi_flash_defines.v\n`include "./periph/flash/spi_flash_defines.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418331750/periph/flash,data/full_repos/permissive/418331750/./periph/flash/spi_flash_defines.v\n             data/full_repos/permissive/418331750/periph/flash,data/full_repos/permissive/418331750/./periph/flash/spi_flash_defines.v.v\n             data/full_repos/permissive/418331750/periph/flash,data/full_repos/permissive/418331750/./periph/flash/spi_flash_defines.v.sv\n             ./periph/flash/spi_flash_defines.v\n             ./periph/flash/spi_flash_defines.v.v\n             ./periph/flash/spi_flash_defines.v.sv\n             obj_dir/./periph/flash/spi_flash_defines.v\n             obj_dir/./periph/flash/spi_flash_defines.v.v\n             obj_dir/./periph/flash/spi_flash_defines.v.sv\n%Error: data/full_repos/permissive/418331750/periph/flash/spi_flash_ctrl.v:118: Define or directive not defined: \'`CMD_READ\'\n  cmd <= `CMD_READ;\n         ^~~~~~~~~\n%Error: data/full_repos/permissive/418331750/periph/flash/spi_flash_ctrl.v:118: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n  cmd <= `CMD_READ;\n                  ^\n%Error: data/full_repos/permissive/418331750/periph/flash/spi_flash_ctrl.v:122: Define or directive not defined: \'`CMD_BE\'\n    cmd <= `CMD_BE;\n           ^~~~~~~\n%Error: data/full_repos/permissive/418331750/periph/flash/spi_flash_ctrl.v:122: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    cmd <= `CMD_BE;\n                  ^\n%Error: data/full_repos/permissive/418331750/periph/flash/spi_flash_ctrl.v:124: Define or directive not defined: \'`CMD_SE\'\n    cmd <= `CMD_SE;\n           ^~~~~~~\n%Error: data/full_repos/permissive/418331750/periph/flash/spi_flash_ctrl.v:124: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    cmd <= `CMD_SE;\n                  ^\n%Error: data/full_repos/permissive/418331750/periph/flash/spi_flash_ctrl.v:126: Define or directive not defined: \'`CMD_RDSR\'\n    cmd <= `CMD_RDSR;\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/418331750/periph/flash/spi_flash_ctrl.v:126: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    cmd <= `CMD_RDSR;\n                    ^\n%Error: data/full_repos/permissive/418331750/periph/flash/spi_flash_ctrl.v:128: Define or directive not defined: \'`CMD_READ\'\n    cmd <= `CMD_READ;\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/418331750/periph/flash/spi_flash_ctrl.v:128: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    cmd <= `CMD_READ;\n                    ^\n%Error: data/full_repos/permissive/418331750/periph/flash/spi_flash_ctrl.v:130: Define or directive not defined: \'`CMD_PP\'\n    cmd <= `CMD_PP;\n           ^~~~~~~\n%Error: data/full_repos/permissive/418331750/periph/flash/spi_flash_ctrl.v:130: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    cmd <= `CMD_PP;\n                  ^\n%Error: data/full_repos/permissive/418331750/periph/flash/spi_flash_ctrl.v:132: Define or directive not defined: \'`CMD_WREN\'\n    cmd <= `CMD_WREN;\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/418331750/periph/flash/spi_flash_ctrl.v:132: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    cmd <= `CMD_WREN;\n                    ^\n%Error: data/full_repos/permissive/418331750/periph/flash/spi_flash_ctrl.v:134: Define or directive not defined: \'`CMD_READ\'\n    cmd <= `CMD_READ;\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/418331750/periph/flash/spi_flash_ctrl.v:134: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    cmd <= `CMD_READ;\n                    ^\n%Error: Exiting due to 17 error(s)\n'
module spi_flash_ctrl(
	input             sys_clk,
	input             rst,
	input             flash_read,
	input             flash_write,
	input             flash_bulk_erase,
	input             flash_sector_erase,
	output            flash_read_ack,
	output            flash_write_ack,
	output            flash_bulk_erase_ack,
	output            flash_sector_erase_ack,
	input[23:0]       flash_read_addr,
	input[23:0]       flash_write_addr,
	input[23:0]       flash_sector_addr,
	input[7:0]        flash_write_data_in,
	input[8:0]        flash_read_size,
	input[8:0]        flash_write_size,
	output            flash_write_data_req,
	output reg[7:0]   flash_read_data_out,
	output reg        flash_read_data_valid,

	output reg[7:0]   cmd,
	output reg        cmd_valid,
	input             cmd_ack,
	output reg[23:0]  addr,
	output[7:0]       data_in,
	output reg[8:0]   size,
	input             data_req,
	input[7:0]        data_out,
	input             data_valid
);

localparam S_IDLE       = 0;
localparam S_SE         = 1;
localparam S_BE         = 2;
localparam S_READ       = 3;
localparam S_WRITE      = 4;
localparam S_ACK        = 5;
localparam S_CK_STATE   = 6;
localparam S_WREN       = 7;

reg[4:0] state,next_state;
reg[7:0] state_reg;
assign data_in = flash_write_data_in;

assign flash_read_ack = (state == S_ACK) && flash_read == 1'b1 ? 1'b1 : 1'b0;
assign flash_write_ack = (state == S_ACK) && flash_write == 1'b1 ? 1'b1 : 1'b0;
assign flash_bulk_erase_ack = (state == S_ACK) && flash_bulk_erase == 1'b1 ? 1'b1 : 1'b0;
assign flash_sector_erase_ack = (state == S_ACK) && flash_sector_erase == 1'b1 ? 1'b1 : 1'b0;
assign flash_write_data_req = data_req;

always@(posedge sys_clk or posedge rst)
begin
	if(rst)
		state <= S_IDLE;
	else
		state <= next_state;
end

always@(*)
begin
	case(state)
		S_IDLE:
			if(flash_bulk_erase == 1'b1)
				next_state <= S_WREN;
			else if(flash_sector_erase == 1'b1)
				next_state <= S_WREN;
			else if(flash_read == 1'b1)
				next_state <= S_READ;
			else if(flash_write == 1'b1)
				next_state <= S_WREN;
			else
				next_state <= S_IDLE;
		S_WREN:
			if(cmd_ack == 1'b1 && flash_bulk_erase == 1'b1)
				next_state <= S_BE;
			else if(cmd_ack == 1'b1 && flash_sector_erase == 1'b1)
				next_state <= S_SE;
			else if(cmd_ack == 1'b1 && flash_write == 1'b1)
				next_state <= S_WRITE;
			else
				next_state <= S_WREN;
		S_BE:
			if(cmd_ack == 1'b1)
				next_state <= S_CK_STATE;
			else
				next_state <= S_BE;
		S_SE:
			if(cmd_ack == 1'b1)
				next_state <= S_CK_STATE;
			else
				next_state <= S_SE;
		S_READ:
			if(cmd_ack == 1'b1)
				next_state <= S_ACK;
			else
				next_state <= S_READ;
		S_WRITE:
			if(cmd_ack == 1'b1)
				next_state <= S_CK_STATE;
			else
				next_state <= S_WRITE;
		S_CK_STATE:
			if(cmd_ack == 1'b1  &&  state_reg[0] == 1'b0)
				next_state <= S_ACK;
			else
				next_state <= S_CK_STATE;
		S_ACK:
			next_state <= S_IDLE;
		default:
			next_state <= S_IDLE;
	endcase
end
always@(posedge sys_clk or posedge rst)
begin
	if(rst)
		cmd <= `CMD_READ;
	else
		case(state)
			S_BE:
				cmd <= `CMD_BE;
			S_SE:
				cmd <= `CMD_SE;
			S_CK_STATE:
				cmd <= `CMD_RDSR;
			S_READ:
				cmd <= `CMD_READ;
			S_WRITE:
				cmd <= `CMD_PP;
			S_WREN:
				cmd <= `CMD_WREN;
			default:
				cmd <= `CMD_READ;
		endcase
end

always@(posedge sys_clk or posedge rst)
begin
	if(rst)
		size <= 9'd0;
	else
		case(state)
			S_CK_STATE:
				size <= 9'd1;
			S_READ:
				size <= flash_read_size;
			S_WRITE:
				size <= flash_write_size;
			default:
				size <= 9'd0;
		endcase
end

always@(posedge sys_clk or posedge rst)
begin
	if(rst)
		addr <= 1'b0;
	else if(state == S_IDLE && flash_sector_erase == 1'b1)
		addr <= flash_sector_addr;
	else if(state == S_IDLE && flash_read == 1'b1)
		addr <= flash_read_addr;
	else if(state == S_IDLE && flash_write == 1'b1)
		addr <= flash_write_addr;
end

always@(posedge sys_clk or posedge rst)
begin
	if(rst)
		state_reg <= 8'd0;
	else if(state == S_CK_STATE && data_valid == 1'b1)
		state_reg <= data_out;
	else
		state_reg <= state_reg;
end

always@(posedge sys_clk or posedge rst)
begin
	if(rst)
		flash_read_data_out <= 8'd0;
	else if(state == S_READ && data_valid == 1'b1)
		flash_read_data_out <= data_out;
	else
		flash_read_data_out <= data_out;
end

always@(posedge sys_clk or posedge rst)
begin
	if(rst)
		flash_read_data_valid <= 1'd0;
	else if(state == S_READ && data_valid == 1'b1)
		flash_read_data_valid <= 1'b1;
	else
		flash_read_data_valid <= 1'b0;
end

always@(posedge sys_clk or posedge rst)
begin
	if(rst)
		cmd_valid <= 1'b0;
	else
		case(state)
			S_READ,S_WRITE,S_BE,S_WREN,S_SE:
				if(cmd_ack == 1'b1)
					cmd_valid <= 1'b0;
				else
					cmd_valid <= 1'b1;
			S_CK_STATE:
				if(cmd_ack == 1'b1)
					cmd_valid <= 1'b0;
				else
					cmd_valid <= 1'b1;
			default:
				cmd_valid <= 1'b0;
		endcase
end

endmodule
module spi_flash_ctrl(
	input             sys_clk,
	input             rst,
	input             flash_read,
	input             flash_write,
	input             flash_bulk_erase,
	input             flash_sector_erase,
	output            flash_read_ack,
	output            flash_write_ack,
	output            flash_bulk_erase_ack,
	output            flash_sector_erase_ack,
	input[23:0]       flash_read_addr,
	input[23:0]       flash_write_addr,
	input[23:0]       flash_sector_addr,
	input[7:0]        flash_write_data_in,
	input[8:0]        flash_read_size,
	input[8:0]        flash_write_size,
	output            flash_write_data_req,
	output reg[7:0]   flash_read_data_out,
	output reg        flash_read_data_valid,

	output reg[7:0]   cmd,
	output reg        cmd_valid,
	input             cmd_ack,
	output reg[23:0]  addr,
	output[7:0]       data_in,
	output reg[8:0]   size,
	input             data_req,
	input[7:0]        data_out,
	input             data_valid
);


localparam S_IDLE       = 0;
localparam S_SE         = 1;
localparam S_BE         = 2;
localparam S_READ       = 3;
localparam S_WRITE      = 4;
localparam S_ACK        = 5;
localparam S_CK_STATE   = 6;
localparam S_WREN       = 7;

reg[4:0] state,next_state;
reg[7:0] state_reg;
assign data_in = flash_write_data_in;

assign flash_read_ack = (state == S_ACK) && flash_read == 1'b1 ? 1'b1 : 1'b0;
assign flash_write_ack = (state == S_ACK) && flash_write == 1'b1 ? 1'b1 : 1'b0;
assign flash_bulk_erase_ack = (state == S_ACK) && flash_bulk_erase == 1'b1 ? 1'b1 : 1'b0;
assign flash_sector_erase_ack = (state == S_ACK) && flash_sector_erase == 1'b1 ? 1'b1 : 1'b0;
assign flash_write_data_req = data_req;

always@(posedge sys_clk or posedge rst)
begin
	if(rst)
		state <= S_IDLE;
	else
		state <= next_state;
end

always@(*)
begin
	case(state)
		S_IDLE:
			if(flash_bulk_erase == 1'b1)
				next_state <= S_WREN;
			else if(flash_sector_erase == 1'b1)
				next_state <= S_WREN;
			else if(flash_read == 1'b1)
				next_state <= S_READ;
			else if(flash_write == 1'b1)
				next_state <= S_WREN;
			else
				next_state <= S_IDLE;
		S_WREN:
			if(cmd_ack == 1'b1 && flash_bulk_erase == 1'b1)
				next_state <= S_BE;
			else if(cmd_ack == 1'b1 && flash_sector_erase == 1'b1)
				next_state <= S_SE;
			else if(cmd_ack == 1'b1 && flash_write == 1'b1)
				next_state <= S_WRITE;
			else
				next_state <= S_WREN;
		S_BE:
			if(cmd_ack == 1'b1)
				next_state <= S_CK_STATE;
			else
				next_state <= S_BE;
		S_SE:
			if(cmd_ack == 1'b1)
				next_state <= S_CK_STATE;
			else
				next_state <= S_SE;
		S_READ:
			if(cmd_ack == 1'b1)
				next_state <= S_ACK;
			else
				next_state <= S_READ;
		S_WRITE:
			if(cmd_ack == 1'b1)
				next_state <= S_CK_STATE;
			else
				next_state <= S_WRITE;
		S_CK_STATE:
			if(cmd_ack == 1'b1  &&  state_reg[0] == 1'b0)
				next_state <= S_ACK;
			else
				next_state <= S_CK_STATE;
		S_ACK:
			next_state <= S_IDLE;
		default:
			next_state <= S_IDLE;
	endcase
end
always@(posedge sys_clk or posedge rst)
begin
	if(rst)
		cmd <= `CMD_READ;
	else
		case(state)
			S_BE:
				cmd <= `CMD_BE;
			S_SE:
				cmd <= `CMD_SE;
			S_CK_STATE:
				cmd <= `CMD_RDSR;
			S_READ:
				cmd <= `CMD_READ;
			S_WRITE:
				cmd <= `CMD_PP;
			S_WREN:
				cmd <= `CMD_WREN;
			default:
				cmd <= `CMD_READ;
		endcase
end

always@(posedge sys_clk or posedge rst)
begin
	if(rst)
		size <= 9'd0;
	else
		case(state)
			S_CK_STATE:
				size <= 9'd1;
			S_READ:
				size <= flash_read_size;
			S_WRITE:
				size <= flash_write_size;
			default:
				size <= 9'd0;
		endcase
end

always@(posedge sys_clk or posedge rst)
begin
	if(rst)
		addr <= 1'b0;
	else if(state == S_IDLE && flash_sector_erase == 1'b1)
		addr <= flash_sector_addr;
	else if(state == S_IDLE && flash_read == 1'b1)
		addr <= flash_read_addr;
	else if(state == S_IDLE && flash_write == 1'b1)
		addr <= flash_write_addr;
end

always@(posedge sys_clk or posedge rst)
begin
	if(rst)
		state_reg <= 8'd0;
	else if(state == S_CK_STATE && data_valid == 1'b1)
		state_reg <= data_out;
	else
		state_reg <= state_reg;
end

always@(posedge sys_clk or posedge rst)
begin
	if(rst)
		flash_read_data_out <= 8'd0;
	else if(state == S_READ && data_valid == 1'b1)
		flash_read_data_out <= data_out;
	else
		flash_read_data_out <= data_out;
end

always@(posedge sys_clk or posedge rst)
begin
	if(rst)
		flash_read_data_valid <= 1'd0;
	else if(state == S_READ && data_valid == 1'b1)
		flash_read_data_valid <= 1'b1;
	else
		flash_read_data_valid <= 1'b0;
end

always@(posedge sys_clk or posedge rst)
begin
	if(rst)
		cmd_valid <= 1'b0;
	else
		case(state)
			S_READ,S_WRITE,S_BE,S_WREN,S_SE:
				if(cmd_ack == 1'b1)
					cmd_valid <= 1'b0;
				else
					cmd_valid <= 1'b1;
			S_CK_STATE:
				if(cmd_ack == 1'b1)
					cmd_valid <= 1'b0;
				else
					cmd_valid <= 1'b1;
			default:
				cmd_valid <= 1'b0;
		endcase
end

endmodule