data/full_repos/permissive/472097485/Chu04/WaveGen_01/WaveGen.v
1: b"%Error: data/full_repos/permissive/472097485/Chu04/WaveGen_01/WaveGen.v:12: Cannot find file containing module: 'FrequencyDivider'\n FrequencyDivider us1Tick( clk, reset, max_tick );\n ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/472097485/Chu04/WaveGen_01,data/full_repos/permissive/472097485/FrequencyDivider\n             data/full_repos/permissive/472097485/Chu04/WaveGen_01,data/full_repos/permissive/472097485/FrequencyDivider.v\n             data/full_repos/permissive/472097485/Chu04/WaveGen_01,data/full_repos/permissive/472097485/FrequencyDivider.sv\n             FrequencyDivider\n             FrequencyDivider.v\n             FrequencyDivider.sv\n             obj_dir/FrequencyDivider\n             obj_dir/FrequencyDivider.v\n             obj_dir/FrequencyDivider.sv\n%Error: data/full_repos/permissive/472097485/Chu04/WaveGen_01/WaveGen.v:14: Cannot find file containing module: 'ModMCounter'\n ModMCounter #(4) on( clk, reset, max_tick && on_en, on_us, on_count );\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/472097485/Chu04/WaveGen_01/WaveGen.v:15: Cannot find file containing module: 'ModMCounter'\n ModMCounter #(4) off( clk, reset, max_tick && ~on_en, off_us, off_count );\n ^~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module WaveGen( input clk, input reset, input [3:0] on_us, input [3:0] off_us, output wave );

	wire max_tick, next_on_en;
	wire [3:0] on_count, off_count;
	reg on_en;
	
	FrequencyDivider us1Tick( clk, reset, max_tick );
	
	ModMCounter #(4) on( clk, reset, max_tick && on_en, on_us, on_count );
	ModMCounter #(4) off( clk, reset, max_tick && ~on_en, off_us, off_count );
	
	always @( posedge clk )
		if( reset )
			on_en <= 1'b1;
		else
			if( max_tick )
				on_en <= next_on_en;


	assign next_on_en =( on_en && on_us - 1 != on_count ) || ( ~on_en && off_us - 1 == off_count );


	assign wave = on_en;

endmodule
module WaveGen( input clk, input reset, input [3:0] on_us, input [3:0] off_us, output wave );


	wire max_tick, next_on_en;
	wire [3:0] on_count, off_count;
	reg on_en;
	
	FrequencyDivider us1Tick( clk, reset, max_tick );
	
	ModMCounter #(4) on( clk, reset, max_tick && on_en, on_us, on_count );
	ModMCounter #(4) off( clk, reset, max_tick && ~on_en, off_us, off_count );
	
	always @( posedge clk )
		if( reset )
			on_en <= 1'b1;
		else
			if( max_tick )
				on_en <= next_on_en;


	assign next_on_en =( on_en && on_us - 1 != on_count ) || ( ~on_en && off_us - 1 == off_count );


	assign wave = on_en;

endmodule