data/full_repos/permissive/423539813/testbenches/instruction_memory_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/instruction_memory_testbench.v:33: Unsupported: Ignoring delay on this delayed statement.\n#100     \n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/instruction_memory_testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n#100     \n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/instruction_memory_testbench.v:38: Unsupported: Ignoring delay on this delayed statement.\n#100     \n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/instruction_memory_testbench.v:40: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/instruction_memory_testbench.v:42: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/instruction_memory_testbench.v:44: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/instruction_memory_testbench.v:47: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/instruction_memory_testbench.v:49: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Error: data/full_repos/permissive/423539813/testbenches/instruction_memory_testbench.v:28: Cannot find file containing module: \'instruction_memory\'\ninstruction_memory uut (.pc(pc),.instruction(instruction));\n^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423539813/testbenches,data/full_repos/permissive/423539813/instruction_memory\n             data/full_repos/permissive/423539813/testbenches,data/full_repos/permissive/423539813/instruction_memory.v\n             data/full_repos/permissive/423539813/testbenches,data/full_repos/permissive/423539813/instruction_memory.sv\n             instruction_memory\n             instruction_memory.v\n             instruction_memory.sv\n             obj_dir/instruction_memory\n             obj_dir/instruction_memory.v\n             obj_dir/instruction_memory.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module instruction_memory_testbench;

reg[31:0] pc;
wire [31:0] instruction;

instruction_memory uut (.pc(pc),.instruction(instruction));

initial begin

pc =32'h0;
#100     
pc =32'h4;
#100     

pc =32'h8;
#100     
pc =32'hC;
#100
pc =32'h10;
#100
pc =32'h14;
#100

pc =32'h18;
#100
pc =32'h1C;
#100

pc =32'h20;

end
endmodule
module instruction_memory_testbench;


reg[31:0] pc;
wire [31:0] instruction;

instruction_memory uut (.pc(pc),.instruction(instruction));

initial begin

pc =32'h0;
#100     
pc =32'h4;
#100     

pc =32'h8;
#100     
pc =32'hC;
#100
pc =32'h10;
#100
pc =32'h14;
#100

pc =32'h18;
#100
pc =32'h1C;
#100

pc =32'h20;

end
endmodule