data/full_repos/permissive/441359809/src/yosys/manual/PRESENTATION_ExSyn/memory_01.v
data/verilator_xmls/6d469b56-1a05-4a9e-87be-513a934e3e14.xml
module test(input      CLK, ADDR,
            input      [7:0] DIN,
	    output reg [7:0] DOUT);
    reg [7:0] mem [0:1];
    always @(posedge CLK) begin
        mem[ADDR] <= DIN;
	DOUT <= mem[ADDR];
    end
endmodule
module test(input      CLK, ADDR,
            input      [7:0] DIN,
	    output reg [7:0] DOUT);

    reg [7:0] mem [0:1];
    always @(posedge CLK) begin
        mem[ADDR] <= DIN;
	DOUT <= mem[ADDR];
    end
endmodule