data/full_repos/permissive/419273451/lab1/codes/Data_Memory.v
data/verilator_xmls/f99357bf-c75a-4a95-9e37-2ba398e8159b.xml
module Data_Memory
(
    clk_i, 
    addr_i, 
    MemRead_i,
    MemWrite_i,
    data_i,
    data_o
);


input               clk_i;
input   [31:0]      addr_i;
input               MemRead_i;
input               MemWrite_i;
input   [31:0]      data_i;
output  [31:0]      data_o;


reg signed[31:0]    memory  [0:1023];


reg     [63:0]     tmp;

assign  data_o = MemRead_i? memory[addr_i >> 2] : 0;

always @ (posedge clk_i) begin
    if (MemWrite_i) begin

        memory[addr_i >> 2] <= data_i;
    end
end

endmodule
module Data_Memory
(
    clk_i, 
    addr_i, 
    MemRead_i,
    MemWrite_i,
    data_i,
    data_o
);



input               clk_i;
input   [31:0]      addr_i;
input               MemRead_i;
input               MemWrite_i;
input   [31:0]      data_i;
output  [31:0]      data_o;


reg signed[31:0]    memory  [0:1023];


reg     [63:0]     tmp;

assign  data_o = MemRead_i? memory[addr_i >> 2] : 0;

always @ (posedge clk_i) begin
    if (MemWrite_i) begin

        memory[addr_i >> 2] <= data_i;
    end
end

endmodule