data/full_repos/permissive/500596939/rtl/final_video/A5001_3.v
data/verilator_xmls/ac5fb7a7-30bf-4d70-9b55-c0d36dcfa56f.xml
module A5001_3 (

    input wire SLBD7,
    input wire SLD7,
    input wire SLD0,
    input wire SLD1,
    input wire SLD2,
    input wire i7,
    input wire i8,
    input wire i9,
    input wire i11,
    input wire H1_SD30_r,

    output wire COLBANK5,
    output wire LAYER_SELA,
    output wire LAYER_SELB,
    output wire COLBANK3,
    output wire COLBANK4
);






























    wire H1_SD30_r_neg;
    wire SLBD7_neg;
    wire SLD7_neg;
    wire SLD0_neg;
    wire SLD1_neg;
    wire SLD2_neg;

    assign  H1_SD30_r_neg = ~H1_SD30_r;
    assign  SLBD7_neg     = ~SLBD7;
    assign  SLD7_neg      = ~SLD7;
    assign  SLD0_neg      = ~SLD0;
    assign  SLD1_neg      = ~SLD1;
    assign  SLD2_neg      = ~SLD2;





     assign  COLBANK5   = ~((H1_SD30_r_neg & SLD7_neg & SLD0_neg & SLD1 & SLD2) | 
                                               (H1_SD30_r_neg &             SLD0_neg & SLD1 & SLD2));                                              

    assign  LAYER_SELA = ~((H1_SD30_r_neg &                       SLD1 & SLD2));  

    assign  LAYER_SELB = ~((H1_SD30_r_neg &                       SLD1 & SLD2));

    assign  COLBANK3   = ~((H1_SD30_r_neg &  SLBD7_neg                         ) |
                                               (H1_SD30_r_neg &                         SLD1_neg   ) |
                                               (H1_SD30_r_neg &                         SLD2_neg   ));

    assign  COLBANK4   = ~((H1_SD30_r_neg &  SLBD7                             ) |
                                               (H1_SD30_r_neg &                         SLD1_neg   ) |
                                               (H1_SD30_r_neg &                         SLD2_neg   ));           
endmodule
module A5001_3 (

    input wire SLBD7,
    input wire SLD7,
    input wire SLD0,
    input wire SLD1,
    input wire SLD2,
    input wire i7,
    input wire i8,
    input wire i9,
    input wire i11,
    input wire H1_SD30_r,

    output wire COLBANK5,
    output wire LAYER_SELA,
    output wire LAYER_SELB,
    output wire COLBANK3,
    output wire COLBANK4
);































    wire H1_SD30_r_neg;
    wire SLBD7_neg;
    wire SLD7_neg;
    wire SLD0_neg;
    wire SLD1_neg;
    wire SLD2_neg;

    assign  H1_SD30_r_neg = ~H1_SD30_r;
    assign  SLBD7_neg     = ~SLBD7;
    assign  SLD7_neg      = ~SLD7;
    assign  SLD0_neg      = ~SLD0;
    assign  SLD1_neg      = ~SLD1;
    assign  SLD2_neg      = ~SLD2;





     assign  COLBANK5   = ~((H1_SD30_r_neg & SLD7_neg & SLD0_neg & SLD1 & SLD2) | 
                                               (H1_SD30_r_neg &             SLD0_neg & SLD1 & SLD2));                                              

    assign  LAYER_SELA = ~((H1_SD30_r_neg &                       SLD1 & SLD2));  

    assign  LAYER_SELB = ~((H1_SD30_r_neg &                       SLD1 & SLD2));

    assign  COLBANK3   = ~((H1_SD30_r_neg &  SLBD7_neg                         ) |
                                               (H1_SD30_r_neg &                         SLD1_neg   ) |
                                               (H1_SD30_r_neg &                         SLD2_neg   ));

    assign  COLBANK4   = ~((H1_SD30_r_neg &  SLBD7                             ) |
                                               (H1_SD30_r_neg &                         SLD1_neg   ) |
                                               (H1_SD30_r_neg &                         SLD2_neg   ));           
endmodule