data/full_repos/permissive/479923049/regfile.v
data/verilator_xmls/9a051aab-0a08-474f-86c0-6f526d9aee71.xml
module vDFFE(clk, en, in, out);
    parameter n = 16;
    input  clk, en;
    input  [n-1:0] in ;
    output [n-1:0] out ;
    reg    [n-1:0] out ;
    wire   [n-1:0] next_out ;

    assign next_out = en ? in : out;

    always @(posedge clk)
        out = next_out;  
endmodule
module vDFFE(clk, en, in, out);

    parameter n = 16;
    input  clk, en;
    input  [n-1:0] in ;
    output [n-1:0] out ;
    reg    [n-1:0] out ;
    wire   [n-1:0] next_out ;

    assign next_out = en ? in : out;

    always @(posedge clk)
        out = next_out;  
endmodule