data/full_repos/permissive/469312749/alu/work/verilog/seven_seg_5.v
1: b'%Warning-WIDTH: data/full_repos/permissive/469312749/alu/work/verilog/seven_seg_5.v:16: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                      : ... In instance seven_seg_5\n    case (char)\n    ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/469312749/alu/work/verilog/seven_seg_5.v:16: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                      : ... In instance seven_seg_5\n    case (char)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/alu/work/verilog/seven_seg_5.v:16: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                      : ... In instance seven_seg_5\n    case (char)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/alu/work/verilog/seven_seg_5.v:16: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'2\'h3\' generates 2 bits.\n                                                                                      : ... In instance seven_seg_5\n    case (char)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/alu/work/verilog/seven_seg_5.v:16: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h4\' generates 3 bits.\n                                                                                      : ... In instance seven_seg_5\n    case (char)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/alu/work/verilog/seven_seg_5.v:16: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h5\' generates 3 bits.\n                                                                                      : ... In instance seven_seg_5\n    case (char)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/alu/work/verilog/seven_seg_5.v:16: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h6\' generates 3 bits.\n                                                                                      : ... In instance seven_seg_5\n    case (char)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/alu/work/verilog/seven_seg_5.v:16: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'3\'h7\' generates 3 bits.\n                                                                                      : ... In instance seven_seg_5\n    case (char)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/alu/work/verilog/seven_seg_5.v:16: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'h8\' generates 4 bits.\n                                                                                      : ... In instance seven_seg_5\n    case (char)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/alu/work/verilog/seven_seg_5.v:16: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'h9\' generates 4 bits.\n                                                                                      : ... In instance seven_seg_5\n    case (char)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/alu/work/verilog/seven_seg_5.v:16: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'ha\' generates 4 bits.\n                                                                                      : ... In instance seven_seg_5\n    case (char)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/alu/work/verilog/seven_seg_5.v:16: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'hb\' generates 4 bits.\n                                                                                      : ... In instance seven_seg_5\n    case (char)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/alu/work/verilog/seven_seg_5.v:16: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'hc\' generates 4 bits.\n                                                                                      : ... In instance seven_seg_5\n    case (char)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/alu/work/verilog/seven_seg_5.v:16: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'hd\' generates 4 bits.\n                                                                                      : ... In instance seven_seg_5\n    case (char)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/alu/work/verilog/seven_seg_5.v:16: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'he\' generates 4 bits.\n                                                                                      : ... In instance seven_seg_5\n    case (char)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/alu/work/verilog/seven_seg_5.v:16: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'4\'hf\' generates 4 bits.\n                                                                                      : ... In instance seven_seg_5\n    case (char)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/alu/work/verilog/seven_seg_5.v:16: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'5\'h10\' generates 5 bits.\n                                                                                      : ... In instance seven_seg_5\n    case (char)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/alu/work/verilog/seven_seg_5.v:16: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'5\'h11\' generates 5 bits.\n                                                                                      : ... In instance seven_seg_5\n    case (char)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/alu/work/verilog/seven_seg_5.v:16: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'5\'h12\' generates 5 bits.\n                                                                                      : ... In instance seven_seg_5\n    case (char)\n    ^~~~\n%Warning-WIDTH: data/full_repos/permissive/469312749/alu/work/verilog/seven_seg_5.v:16: Operator CASE expects 8 bits on the Case Item, but Case Item\'s CONST \'5\'h13\' generates 5 bits.\n                                                                                      : ... In instance seven_seg_5\n    case (char)\n    ^~~~\n%Error: Exiting due to 20 warning(s)\n'
module seven_seg_5 (
    input [7:0] char,
    output reg [6:0] segs
  );
  
  
  
  always @* begin
    
    case (char)
      1'h0: begin
        segs = 7'h3f;
      end
      1'h1: begin
        segs = 7'h06;
      end
      2'h2: begin
        segs = 7'h5b;
      end
      2'h3: begin
        segs = 7'h4f;
      end
      3'h4: begin
        segs = 7'h66;
      end
      3'h5: begin
        segs = 7'h6d;
      end
      3'h6: begin
        segs = 7'h7d;
      end
      3'h7: begin
        segs = 7'h07;
      end
      4'h8: begin
        segs = 7'h7f;
      end
      4'h9: begin
        segs = 7'h67;
      end
      4'ha: begin
        segs = 7'h71;
      end
      4'hb: begin
        segs = 7'h30;
      end
      4'hc: begin
        segs = 7'h38;
      end
      4'hd: begin
        segs = 7'h73;
      end
      4'he: begin
        segs = 7'h77;
      end
      4'hf: begin
        segs = 7'h00;
      end
      5'h10: begin
        segs = 7'h08;
      end
      5'h11: begin
        segs = 7'h5e;
      end
      5'h12: begin
        segs = 7'h3e;
      end
      5'h13: begin
        segs = 7'h39;
      end
      default: begin
        segs = 7'h00;
      end
    endcase
  end
endmodule
module seven_seg_5 (
    input [7:0] char,
    output reg [6:0] segs
  );

  
  
  
  always @* begin
    
    case (char)
      1'h0: begin
        segs = 7'h3f;
      end
      1'h1: begin
        segs = 7'h06;
      end
      2'h2: begin
        segs = 7'h5b;
      end
      2'h3: begin
        segs = 7'h4f;
      end
      3'h4: begin
        segs = 7'h66;
      end
      3'h5: begin
        segs = 7'h6d;
      end
      3'h6: begin
        segs = 7'h7d;
      end
      3'h7: begin
        segs = 7'h07;
      end
      4'h8: begin
        segs = 7'h7f;
      end
      4'h9: begin
        segs = 7'h67;
      end
      4'ha: begin
        segs = 7'h71;
      end
      4'hb: begin
        segs = 7'h30;
      end
      4'hc: begin
        segs = 7'h38;
      end
      4'hd: begin
        segs = 7'h73;
      end
      4'he: begin
        segs = 7'h77;
      end
      4'hf: begin
        segs = 7'h00;
      end
      5'h10: begin
        segs = 7'h08;
      end
      5'h11: begin
        segs = 7'h5e;
      end
      5'h12: begin
        segs = 7'h3e;
      end
      5'h13: begin
        segs = 7'h39;
      end
      default: begin
        segs = 7'h00;
      end
    endcase
  end
endmodule