data/full_repos/permissive/459497172/verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv
data/verilator_xmls/31055221-b707-49f1-a6f4-d00f41eaa8f3.xml
module mbist_mem_wrapper #(
	parameter BIST_NO_SRAM=4,
	parameter BIST_ADDR_WD=10,
	parameter BIST_DATA_WD=32) (
	input   logic                          rst_n           ,

	input   logic [(BIST_NO_SRAM+1)/2-1:0] sram_id         ,
        input   logic                          wb_clk_i        ,
        input   logic [(BIST_NO_SRAM+1)/2-1:0] mem_cs          ,
        input   logic                          mem_req         ,
        input   logic [BIST_ADDR_WD-1:0]       mem_addr        ,
        input   logic                          mem_we          ,
        input   logic [BIST_DATA_WD-1:0]       mem_wdata       ,
        input   logic [BIST_DATA_WD/8-1:0]     mem_wmask       ,
        output  logic [BIST_DATA_WD-1:0]       mem_rdata       ,

        output   logic                         func_clk        ,
        output   logic                         func_cen        ,
        output   logic                         func_web        ,
        output   logic [BIST_DATA_WD/8-1:0]    func_mask       ,
        output   logic  [BIST_ADDR_WD-1:0]     func_addr       ,
        input    logic  [BIST_DATA_WD-1:0]     func_dout       ,
        output   logic  [BIST_DATA_WD-1:0]     func_din        

);



assign func_clk    = wb_clk_i;
assign func_cen    = (mem_cs  == sram_id) ? !mem_req : 1'b1;
assign func_web    = (mem_cs  == sram_id) ? !mem_we   : 1'b1;
assign func_mask   = mem_wmask;
assign func_addr   = mem_addr;
assign func_din    = mem_wdata;
assign mem_rdata   = func_dout;




endmodule
module mbist_mem_wrapper #(
	parameter BIST_NO_SRAM=4,
	parameter BIST_ADDR_WD=10,
	parameter BIST_DATA_WD=32) (
	input   logic                          rst_n           ,

	input   logic [(BIST_NO_SRAM+1)/2-1:0] sram_id         ,
        input   logic                          wb_clk_i        ,
        input   logic [(BIST_NO_SRAM+1)/2-1:0] mem_cs          ,
        input   logic                          mem_req         ,
        input   logic [BIST_ADDR_WD-1:0]       mem_addr        ,
        input   logic                          mem_we          ,
        input   logic [BIST_DATA_WD-1:0]       mem_wdata       ,
        input   logic [BIST_DATA_WD/8-1:0]     mem_wmask       ,
        output  logic [BIST_DATA_WD-1:0]       mem_rdata       ,

        output   logic                         func_clk        ,
        output   logic                         func_cen        ,
        output   logic                         func_web        ,
        output   logic [BIST_DATA_WD/8-1:0]    func_mask       ,
        output   logic  [BIST_ADDR_WD-1:0]     func_addr       ,
        input    logic  [BIST_DATA_WD-1:0]     func_dout       ,
        output   logic  [BIST_DATA_WD-1:0]     func_din        

);




assign func_clk    = wb_clk_i;
assign func_cen    = (mem_cs  == sram_id) ? !mem_req : 1'b1;
assign func_web    = (mem_cs  == sram_id) ? !mem_we   : 1'b1;
assign func_mask   = mem_wmask;
assign func_addr   = mem_addr;
assign func_din    = mem_wdata;
assign mem_rdata   = func_dout;




endmodule