data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v
1: b'%Warning-WIDTH: data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v:107: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                  : ... In instance part3.u2\n    X_out <= Location[7:0] + Counter[1:0];\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v:108: Operator ADD expects 7 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                  : ... In instance part3.u2\n    Y_out <= Location[14:8] + Counter[3:2];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v:113: Operator ADD expects 8 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                  : ... In instance part3.u2\n    X_out <= Location[7:0] + Counter[1:0];\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v:114: Operator ADD expects 7 bits on the RHS, but RHS\'s SEL generates 2 bits.\n                                                                                  : ... In instance part3.u2\n    Y_out <= Location[14:8] + Counter[3:2];\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v:40: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'Divider\' generates 7 bits.\n                                                                                 : ... In instance part3.u0\n  else if(Divider == (Frame_num - 1))\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/433640910/BouncingVGA/bouncingvga.v:49: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'Divider\' generates 7 bits.\n                                                                                 : ... In instance part3.u0\n  else if(Divider == (Frame_num - 1))\n                  ^~\n%Error: Exiting due to 6 warning(s)\n'
module FrameCounter(Clock, Resetn, Enable, Frame_next_enable);
	input Clock, Resetn, Enable;
	
	output reg Frame_next_enable;
	
	reg [3:0] Counter;
	
	always @(posedge Clock)
		if(!Resetn)
			Counter = 4'b0000;
		else if(Counter == 4'b1111)
			Counter = 0;
		else if(Enable)
			Counter = Counter + 1;
			
	always @(posedge Clock)
		if(!Resetn)
			Frame_next_enable = 0;
		else if(Counter == 4'b1111)
			Frame_next_enable = 1;
		else if(Enable)
			Frame_next_enable = 0;

endmodule
module FrameCounter(Clock, Resetn, Enable, Frame_next_enable);

	input Clock, Resetn, Enable;
	
	output reg Frame_next_enable;
	
	reg [3:0] Counter;
	
	always @(posedge Clock)
		if(!Resetn)
			Counter = 4'b0000;
		else if(Counter == 4'b1111)
			Counter = 0;
		else if(Enable)
			Counter = Counter + 1;
			
	always @(posedge Clock)
		if(!Resetn)
			Frame_next_enable = 0;
		else if(Counter == 4'b1111)
			Frame_next_enable = 1;
		else if(Enable)
			Frame_next_enable = 0;

endmodule