data/full_repos/permissive/428819669/addSubCircuit_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/428819669/addSubCircuit_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/428819669/addSubCircuit_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/428819669/addSubCircuit_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #100;    \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/428819669/addSubCircuit_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/428819669/addSubCircuit_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/428819669/addSubCircuit_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #100; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/428819669/addSubCircuit_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/428819669/addSubCircuit_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/428819669/addSubCircuit_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #100; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/428819669/addSubCircuit_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/428819669/addSubCircuit_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/428819669/addSubCircuit_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #100; \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/428819669/addSubCircuit_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/428819669/addSubCircuit_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/428819669/addSubCircuit_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #100 $stop;\n        ^\n%Error: data/full_repos/permissive/428819669/addSubCircuit_tb.v:7: Cannot find file containing module: \'addSubCircuit\'\n    addSubCircuit u1 (OFUF, done, result, X, Y, addSub, reset, clk);\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/428819669,data/full_repos/permissive/428819669/addSubCircuit\n             data/full_repos/permissive/428819669,data/full_repos/permissive/428819669/addSubCircuit.v\n             data/full_repos/permissive/428819669,data/full_repos/permissive/428819669/addSubCircuit.sv\n             addSubCircuit\n             addSubCircuit.v\n             addSubCircuit.sv\n             obj_dir/addSubCircuit\n             obj_dir/addSubCircuit.v\n             obj_dir/addSubCircuit.sv\n%Error: Exiting due to 1 error(s), 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module addSubCircuit_tb ();
    wire [1:0] OFUF;
    wire done;
    wire [15:0] result;
    reg [15:0] X, Y;
    reg addSub, reset = 0, clk = 0;
    addSubCircuit u1 (OFUF, done, result, X, Y, addSub, reset, clk);
    always clk = #5 ~clk;


    initial begin

        addSub = 0;
        X = 16'h0F00;
        Y = 16'h0B80;
        #10 reset = 1;
        #10 reset = 0;

        #100;    

        X = 16'hD98D;
        Y = 16'h4F08;
        #10 reset = 1;
        #10 reset = 0;

        #100; 

        addSub = 1;
        #10 reset = 1;
        #10 reset = 0;

        #100; 

        X = 16'h118D;
        Y = 16'hEF08;
        #10 reset = 1;
        #10 reset = 0;

        #100; 

        X = 16'h418D;
        Y = 16'hB308;
        #10 reset = 1;
        #10 reset = 0;

        #100 $stop;
    end
    
endmodule
module addSubCircuit_tb ();

    wire [1:0] OFUF;
    wire done;
    wire [15:0] result;
    reg [15:0] X, Y;
    reg addSub, reset = 0, clk = 0;
    addSubCircuit u1 (OFUF, done, result, X, Y, addSub, reset, clk);
    always clk = #5 ~clk;


    initial begin

        addSub = 0;
        X = 16'h0F00;
        Y = 16'h0B80;
        #10 reset = 1;
        #10 reset = 0;

        #100;    

        X = 16'hD98D;
        Y = 16'h4F08;
        #10 reset = 1;
        #10 reset = 0;

        #100; 

        addSub = 1;
        #10 reset = 1;
        #10 reset = 0;

        #100; 

        X = 16'h118D;
        Y = 16'hEF08;
        #10 reset = 1;
        #10 reset = 0;

        #100; 

        X = 16'h418D;
        Y = 16'hB308;
        #10 reset = 1;
        #10 reset = 0;

        #100 $stop;
    end
    
endmodule