data/full_repos/permissive/46276558/fpga/nexys4/rtl/clock/clock.v
1: b"%Error: data/full_repos/permissive/46276558/fpga/nexys4/rtl/clock/clock.v:37: Cannot find file containing module: 'clk_wiz_0'\n    clk_wiz_0 clkgen(CLK_IN, CLK_OUT, VGA_CLK_OUT, LOCKED);\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/46276558/fpga/nexys4/rtl/clock,data/full_repos/permissive/46276558/clk_wiz_0\n             data/full_repos/permissive/46276558/fpga/nexys4/rtl/clock,data/full_repos/permissive/46276558/clk_wiz_0.v\n             data/full_repos/permissive/46276558/fpga/nexys4/rtl/clock,data/full_repos/permissive/46276558/clk_wiz_0.sv\n             clk_wiz_0\n             clk_wiz_0.v\n             clk_wiz_0.sv\n             obj_dir/clk_wiz_0\n             obj_dir/clk_wiz_0.v\n             obj_dir/clk_wiz_0.sv\n%Error: Exiting due to 1 error(s)\n"
module GEN( input wire  CLK_IN,
            input wire  RST_X_IN,
            output wire CLK_OUT,
            output wire VGA_CLK_OUT,
            output wire RST_X_OUT
            );

    wire                LOCKED, VLOCKED, CLK_IBUF;
    wire                RST_X_BUF;

    clk_wiz_0 clkgen(CLK_IN, CLK_OUT, VGA_CLK_OUT, LOCKED);
    RSTGEN rstgen(CLK_OUT, (RST_X_IN & LOCKED), RST_X_OUT);
endmodule
module GEN( input wire  CLK_IN,
            input wire  RST_X_IN,
            output wire CLK_OUT,
            output wire VGA_CLK_OUT,
            output wire RST_X_OUT
            );


    wire                LOCKED, VLOCKED, CLK_IBUF;
    wire                RST_X_BUF;

    clk_wiz_0 clkgen(CLK_IN, CLK_OUT, VGA_CLK_OUT, LOCKED);
    RSTGEN rstgen(CLK_OUT, (RST_X_IN & LOCKED), RST_X_OUT);
endmodule