data/full_repos/permissive/467394306/rtl/tb/inp_tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/467394306/rtl/tb/inp_tb.sv:26: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/467394306/rtl/tb/inp_tb.sv:53: Unsupported: Ignoring delay on this delayed statement.\n        #25;\n        ^\n%Error: data/full_repos/permissive/467394306/rtl/tb/inp_tb.sv:57: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/467394306/rtl/tb/inp_tb.sv:65: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/467394306/rtl/tb/inp_tb.sv:72: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: data/full_repos/permissive/467394306/rtl/tb/inp_tb.sv:83: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: Exiting due to 4 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module INP_TB #(
    parameter SIMCYCLES = 16)
    ();





    integer i,j;





    reg clk, rstn;
    reg read, write;
    reg [7:0] ain [0:7];
    reg [7:0] win [0:7];
    wire [0:7] aemptys, wemptys;
    wire [7:0] as [0:7];
    wire [7:0] ws [0:7];

    always begin
        #10
        clk = ~clk;
    end

    CORE_INPUT_CTRL DUT (.clk(clk), .rstn(rstn),
        .ainport(ain),
        .winport(win),
        .write(write),
        .read(read),
        .aemptys(aemptys),
        .wemptys(wemptys),
        .ws(as),
        .as(ws));

    initial begin
        clk <= 0;
        rstn <= 0;
        read <= 0;
        write <= 0;

        for (i=0; i<8; i=i+1) begin
            ain[i] <= 1;
            win[i] <= 1;
        end

        $display("INITIALZIED.");

        #25;
        rstn <= 1;

        write <= 1;
        @(posedge clk);
        write <= 0;

        for (i=0; i<8; i=i+1) begin
            ain[i] <= ain[i] + 1;
            win[i] <= win[i] + 1;
        end

        @(posedge clk);
        @(posedge clk);   

        for (i=0; i<SIMCYCLES; i=i+1) begin
            write <= 1;
            read <= 1;
            
            @(posedge clk);
            for (j=0; j<8; j=j+1) begin
                ain[j] <= ain[j] + 2;
                win[j] <= win[j] + 1;
            end
        end


        for (i=0; i<8; i=i+1) begin
            write <= 0;
            read <= 1;
            @(posedge clk);
        end

        $display("SIMULATION ENDED.");
        $finish;
    end
endmodule
module INP_TB #(
    parameter SIMCYCLES = 16)
    ();






    integer i,j;





    reg clk, rstn;
    reg read, write;
    reg [7:0] ain [0:7];
    reg [7:0] win [0:7];
    wire [0:7] aemptys, wemptys;
    wire [7:0] as [0:7];
    wire [7:0] ws [0:7];

    always begin
        #10
        clk = ~clk;
    end

    CORE_INPUT_CTRL DUT (.clk(clk), .rstn(rstn),
        .ainport(ain),
        .winport(win),
        .write(write),
        .read(read),
        .aemptys(aemptys),
        .wemptys(wemptys),
        .ws(as),
        .as(ws));

    initial begin
        clk <= 0;
        rstn <= 0;
        read <= 0;
        write <= 0;

        for (i=0; i<8; i=i+1) begin
            ain[i] <= 1;
            win[i] <= 1;
        end

        $display("INITIALZIED.");

        #25;
        rstn <= 1;

        write <= 1;
        @(posedge clk);
        write <= 0;

        for (i=0; i<8; i=i+1) begin
            ain[i] <= ain[i] + 1;
            win[i] <= win[i] + 1;
        end

        @(posedge clk);
        @(posedge clk);   

        for (i=0; i<SIMCYCLES; i=i+1) begin
            write <= 1;
            read <= 1;
            
            @(posedge clk);
            for (j=0; j<8; j=j+1) begin
                ain[j] <= ain[j] + 2;
                win[j] <= win[j] + 1;
            end
        end


        for (i=0; i<8; i=i+1) begin
            write <= 0;
            read <= 1;
            @(posedge clk);
        end

        $display("SIMULATION ENDED.");
        $finish;
    end
endmodule