data/full_repos/permissive/432650104/src/sha_module.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/432650104/src/sha_module.v:226: Signal definition not found, creating implicitly: \'shafifoout_last\'\n  assign shafifoout_last = 1\'b1;\n         ^~~~~~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/432650104/src/sha_module.v:198: Cannot find file containing module: \'fifo_distram_16x256b\'\n  fifo_distram_16x256b sha_module_hin_fifo\n  ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/432650104/src,data/full_repos/permissive/432650104/fifo_distram_16x256b\n             data/full_repos/permissive/432650104/src,data/full_repos/permissive/432650104/fifo_distram_16x256b.v\n             data/full_repos/permissive/432650104/src,data/full_repos/permissive/432650104/fifo_distram_16x256b.sv\n             fifo_distram_16x256b\n             fifo_distram_16x256b.v\n             fifo_distram_16x256b.sv\n             obj_dir/fifo_distram_16x256b\n             obj_dir/fifo_distram_16x256b.v\n             obj_dir/fifo_distram_16x256b.sv\n%Error: data/full_repos/permissive/432650104/src/sha_module.v:211: Cannot find file containing module: \'fifo_distram_16x512\'\n  fifo_distram_16x512 sha_module_textin_fifo\n  ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/432650104/src/sha_module.v:352: Cannot find file containing module: \'sha256_core_pipelined\'\n  sha256_core_pipelined sha256_core_pipelined\n  ^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module sha_module (
  input wire 	      clk,
  input wire 	      reset,


  input wire 	      first,


  input wire 	      text_vld,
  output wire 	      text_rdy,
  input wire [511:0]  text_data,


  input wire 	      hin_vld,
  output wire 	      hin_rdy,
  input wire [255:0]  hin_data,


  output wire 	      hout_vld,
  input wire 	      hout_rdy,
  output wire [255:0] hout_data

  );

  reg 				     textfifo_rdy;
  wire 				     textfifo_vld;
  wire [511:0] 	                     textfifo_data;
  reg 				     hinfifo_rdy;
  wire 				     hinfifo_vld;
  wire [255:0] 	                     hinfifo_data;

  wire [255:0] 			     sha_digest;
  reg 				     sha_init;
  reg 				     sha_next;
  wire 				     sha_ready;
  wire 				     sha_valid;
  reg 				     sha_busy;
  reg 				     sha_last;
  reg 				     sha_out_valid;
  reg [31:0] 			     sha_read_counter;
  reg 				     sha2fifo_input_vld;
  































localparam
  SHA_IDLE = 3'd0,
  SHA_READ_FIRST = 3'd1,
  SHA_WAIT_NEXT = 3'd2,
  SHA_READ_NEXT = 3'd3,
  SHA_READ_REST = 3'd4,
  SHA_WAIT_OUTPUT_VALID = 3'd5,
  SHA_WAIT_OUTPUT_READ = 3'd6;
 
  reg [2:0]   sha_state;



localparam
  FIFO2SHA_IDLE = 3'd0,
  FIFO2SHA_WAIT_NEXT_BLOCK = 3'd1,
  FIFO2SHA_READ_NEXT_BLOCK = 3'd2,
  FIFO2SHA_READ_REST = 3'd3,
  FIFO2SHA_LAST_BLOCK = 3'd4;
  
  reg [2:0]   fifo2sha_state;






















































































  

  fifo_distram_16x256b sha_module_hin_fifo
    (
     .s_aclk(clk),
     .s_aresetn(~reset),
     .s_axis_tvalid(hin_vld),
     .s_axis_tready(hin_rdy),
     .s_axis_tdata(hin_data),
     .m_axis_tvalid(hinfifo_vld),
     .m_axis_tready(hinfifo_rdy),
     .m_axis_tdata(hinfifo_data)
     );


  fifo_distram_16x512 sha_module_textin_fifo
    (
     .s_aclk(clk),
     .s_aresetn(~reset),
     .s_axis_tvalid(text_vld),
     .s_axis_tready(text_rdy),
     .s_axis_tdata(text_data),
     .m_axis_tvalid(textfifo_vld),
     .m_axis_tready(textfifo_rdy),
     .m_axis_tdata(textfifo_data)
     );




  assign shafifoout_last = 1'b1;

  assign hout_vld = sha_out_valid;

  




  always @(posedge clk) begin
    if (reset) begin
      sha_state <= SHA_IDLE;
      sha_init <= 1'b0;
      sha_next <= 1'b0;
      sha_last <= 1'b0;
      sha_busy <= 1'b0;

      textfifo_rdy  <= 1'b0;
      hinfifo_rdy  <= 1'b0;
      sha_out_valid <= 1'b0;
    end
    else begin
      case (sha_state)
        SHA_IDLE: begin
	  sha_init <= 1'b0;
	  sha_next <= 1'b0;
	  sha_busy <= 1'b0;

	  textfifo_rdy  <= 1'b0;
	  hinfifo_rdy  <= 1'b0;

          if (textfifo_vld && (first || hinfifo_vld) && hout_rdy && ~sha_busy) begin





            sha_state <= SHA_READ_FIRST;
	  end
	  
	  else 
            sha_state <= SHA_IDLE;
	end
	
        SHA_READ_FIRST: begin
	  sha_busy <= 1'b1;
	  sha_init <= 1'b1;

	  textfifo_rdy  <= 1'b1;
	  if (~first && hinfifo_vld)

	    hinfifo_rdy  <= 1'b1;
	  
	  sha_last <= shafifoout_last;
          sha_state <= SHA_READ_REST;
	end
	
        SHA_READ_REST: begin 
	  sha_init <= 1'b0;
	  sha_next <= 1'b0;

	  textfifo_rdy  <= 1'b0;
	  hinfifo_rdy  <= 1'b0;
          sha_state <= SHA_WAIT_OUTPUT_VALID;
	end



















	SHA_WAIT_OUTPUT_VALID: begin
          if (sha_ready) begin
            if (sha_last) begin


              sha_state <= SHA_WAIT_OUTPUT_READ;
	      sha_out_valid <= 1'b1;
	    end
            else


              sha_state <= SHA_WAIT_NEXT;
	  end
            else
              sha_state <= SHA_WAIT_OUTPUT_VALID;
	end
	
	SHA_WAIT_OUTPUT_READ: begin



	  sha_out_valid <= 1'b0;
          sha_busy <= 1'b0;
          sha_state <= SHA_IDLE;
	end



	default: begin
          sha_state <= SHA_IDLE;
	end
      endcase
    end
  end



  wire [255:0] digest_in;
  assign digest_in = first ? 256'b0 : hinfifo_data;

  assign hout_data = sha_digest;
  
  sha256_core_pipelined sha256_core_pipelined
    (
     .clk(clk),
     .reset_n(~reset),
     .init(sha_init),
     .next(sha_next),
     .mode(1'b1),

     .first(first),
     .digest_in(digest_in),

     .block(textfifo_data),    
     .ready(sha_ready),
     .digest(sha_digest),
     .digest_valid(sha_valid)
     );
  
endmodule
module sha_module (
  input wire 	      clk,
  input wire 	      reset,


  input wire 	      first,


  input wire 	      text_vld,
  output wire 	      text_rdy,
  input wire [511:0]  text_data,


  input wire 	      hin_vld,
  output wire 	      hin_rdy,
  input wire [255:0]  hin_data,


  output wire 	      hout_vld,
  input wire 	      hout_rdy,
  output wire [255:0] hout_data

  );


  reg 				     textfifo_rdy;
  wire 				     textfifo_vld;
  wire [511:0] 	                     textfifo_data;
  reg 				     hinfifo_rdy;
  wire 				     hinfifo_vld;
  wire [255:0] 	                     hinfifo_data;

  wire [255:0] 			     sha_digest;
  reg 				     sha_init;
  reg 				     sha_next;
  wire 				     sha_ready;
  wire 				     sha_valid;
  reg 				     sha_busy;
  reg 				     sha_last;
  reg 				     sha_out_valid;
  reg [31:0] 			     sha_read_counter;
  reg 				     sha2fifo_input_vld;
  































localparam
  SHA_IDLE = 3'd0,
  SHA_READ_FIRST = 3'd1,
  SHA_WAIT_NEXT = 3'd2,
  SHA_READ_NEXT = 3'd3,
  SHA_READ_REST = 3'd4,
  SHA_WAIT_OUTPUT_VALID = 3'd5,
  SHA_WAIT_OUTPUT_READ = 3'd6;
 
  reg [2:0]   sha_state;



localparam
  FIFO2SHA_IDLE = 3'd0,
  FIFO2SHA_WAIT_NEXT_BLOCK = 3'd1,
  FIFO2SHA_READ_NEXT_BLOCK = 3'd2,
  FIFO2SHA_READ_REST = 3'd3,
  FIFO2SHA_LAST_BLOCK = 3'd4;
  
  reg [2:0]   fifo2sha_state;






















































































  

  fifo_distram_16x256b sha_module_hin_fifo
    (
     .s_aclk(clk),
     .s_aresetn(~reset),
     .s_axis_tvalid(hin_vld),
     .s_axis_tready(hin_rdy),
     .s_axis_tdata(hin_data),
     .m_axis_tvalid(hinfifo_vld),
     .m_axis_tready(hinfifo_rdy),
     .m_axis_tdata(hinfifo_data)
     );


  fifo_distram_16x512 sha_module_textin_fifo
    (
     .s_aclk(clk),
     .s_aresetn(~reset),
     .s_axis_tvalid(text_vld),
     .s_axis_tready(text_rdy),
     .s_axis_tdata(text_data),
     .m_axis_tvalid(textfifo_vld),
     .m_axis_tready(textfifo_rdy),
     .m_axis_tdata(textfifo_data)
     );




  assign shafifoout_last = 1'b1;

  assign hout_vld = sha_out_valid;

  




  always @(posedge clk) begin
    if (reset) begin
      sha_state <= SHA_IDLE;
      sha_init <= 1'b0;
      sha_next <= 1'b0;
      sha_last <= 1'b0;
      sha_busy <= 1'b0;

      textfifo_rdy  <= 1'b0;
      hinfifo_rdy  <= 1'b0;
      sha_out_valid <= 1'b0;
    end
    else begin
      case (sha_state)
        SHA_IDLE: begin
	  sha_init <= 1'b0;
	  sha_next <= 1'b0;
	  sha_busy <= 1'b0;

	  textfifo_rdy  <= 1'b0;
	  hinfifo_rdy  <= 1'b0;

          if (textfifo_vld && (first || hinfifo_vld) && hout_rdy && ~sha_busy) begin





            sha_state <= SHA_READ_FIRST;
	  end
	  
	  else 
            sha_state <= SHA_IDLE;
	end
	
        SHA_READ_FIRST: begin
	  sha_busy <= 1'b1;
	  sha_init <= 1'b1;

	  textfifo_rdy  <= 1'b1;
	  if (~first && hinfifo_vld)

	    hinfifo_rdy  <= 1'b1;
	  
	  sha_last <= shafifoout_last;
          sha_state <= SHA_READ_REST;
	end
	
        SHA_READ_REST: begin 
	  sha_init <= 1'b0;
	  sha_next <= 1'b0;

	  textfifo_rdy  <= 1'b0;
	  hinfifo_rdy  <= 1'b0;
          sha_state <= SHA_WAIT_OUTPUT_VALID;
	end



















	SHA_WAIT_OUTPUT_VALID: begin
          if (sha_ready) begin
            if (sha_last) begin


              sha_state <= SHA_WAIT_OUTPUT_READ;
	      sha_out_valid <= 1'b1;
	    end
            else


              sha_state <= SHA_WAIT_NEXT;
	  end
            else
              sha_state <= SHA_WAIT_OUTPUT_VALID;
	end
	
	SHA_WAIT_OUTPUT_READ: begin



	  sha_out_valid <= 1'b0;
          sha_busy <= 1'b0;
          sha_state <= SHA_IDLE;
	end



	default: begin
          sha_state <= SHA_IDLE;
	end
      endcase
    end
  end



  wire [255:0] digest_in;
  assign digest_in = first ? 256'b0 : hinfifo_data;

  assign hout_data = sha_digest;
  
  sha256_core_pipelined sha256_core_pipelined
    (
     .clk(clk),
     .reset_n(~reset),
     .init(sha_init),
     .next(sha_next),
     .mode(1'b1),

     .first(first),
     .digest_in(digest_in),

     .block(textfifo_data),    
     .ready(sha_ready),
     .digest(sha_digest),
     .digest_valid(sha_valid)
     );
  
endmodule