data/full_repos/permissive/4395844/ClockDivider.v
data/verilator_xmls/0a8a2ae9-6caa-4df7-ac92-2f5f5da27a5b.xml
module ClockDivider (clk50MHz, clk25MHz);
input clk50MHz;
output clk25MHz;

reg clk25MHz_;

always @ (posedge clk50MHz)
begin
	clk25MHz_ = ~clk25MHz_;
end

assign clk25MHz = clk25MHz_;

endmodule
module ClockDivider (clk50MHz, clk25MHz);

input clk50MHz;
output clk25MHz;

reg clk25MHz_;

always @ (posedge clk50MHz)
begin
	clk25MHz_ = ~clk25MHz_;
end

assign clk25MHz = clk25MHz_;

endmodule