data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/Ctrl.v
1: b'%Warning-WIDTH: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/Ctrl.v:34: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                       : ... In instance Ctrl\n        flush<=1\'b0;\n             ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/Ctrl.v:38: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                       : ... In instance Ctrl\n        flush<=1\'b0;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/Ctrl.v:41: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                       : ... In instance Ctrl\n        flush<=1\'b0;\n             ^~\n%Warning-WIDTH: data/full_repos/permissive/473511254/Project_Src/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/Ctrl.v:44: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                                       : ... In instance Ctrl\n        flush<=1\'b0;\n             ^~\n%Error: Exiting due to 4 warning(s)\n'
module Ctrl(
    input clk,
    input rst,
    input wire I_FromID_stallreq,
    input wire I_FromEX_stallreq,
    output reg [5:0] stall,
    output reg [1:0] flush,
    output reg [31:0] O_ToPC_new_pc
);
always @(*) begin
    if(rst==1'b0) begin
        stall<=6'b0;
        flush<=1'b0;
        O_ToPC_new_pc<=32'b0;
    end else if(I_FromID_stallreq==1'b1) begin
        stall<=6'b001111;
        flush<=1'b0;
    end else if(I_FromEX_stallreq==1'b1) begin
        stall<=6'b000111;
        flush<=1'b0;
    end else begin
        stall<=6'b000000;
        flush<=1'b0;
        O_ToPC_new_pc<=32'b0;
    end
end
endmodule
module Ctrl(
    input clk,
    input rst,
    input wire I_FromID_stallreq,
    input wire I_FromEX_stallreq,
    output reg [5:0] stall,
    output reg [1:0] flush,
    output reg [31:0] O_ToPC_new_pc
);

always @(*) begin
    if(rst==1'b0) begin
        stall<=6'b0;
        flush<=1'b0;
        O_ToPC_new_pc<=32'b0;
    end else if(I_FromID_stallreq==1'b1) begin
        stall<=6'b001111;
        flush<=1'b0;
    end else if(I_FromEX_stallreq==1'b1) begin
        stall<=6'b000111;
        flush<=1'b0;
    end else begin
        stall<=6'b000000;
        flush<=1'b0;
        O_ToPC_new_pc<=32'b0;
    end
end
endmodule