data/full_repos/permissive/473423187/hw/rtl/Vortex.sv
1: b'%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:1: Cannot find include file: VX_define.vh\n`include "VX_define.vh" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/473423187/hw/rtl,data/full_repos/permissive/473423187/VX_define.vh\n             data/full_repos/permissive/473423187/hw/rtl,data/full_repos/permissive/473423187/VX_define.vh.v\n             data/full_repos/permissive/473423187/hw/rtl,data/full_repos/permissive/473423187/VX_define.vh.sv\n             VX_define.vh\n             VX_define.vh.v\n             VX_define.vh.sv\n             obj_dir/VX_define.vh\n             obj_dir/VX_define.vh.v\n             obj_dir/VX_define.vh.sv\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:4: Define or directive not defined: \'`SCOPE_IO_Vortex\'\n    `SCOPE_IO_Vortex\n    ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:13: Define or directive not defined: \'`VX_MEM_BYTEEN_WIDTH\'\n    output wire [`VX_MEM_BYTEEN_WIDTH-1:0]  mem_req_byteen,    \n                 ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:14: Define or directive not defined: \'`VX_MEM_ADDR_WIDTH\'\n    output wire [`VX_MEM_ADDR_WIDTH-1:0]    mem_req_addr,\n                 ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:15: Define or directive not defined: \'`VX_MEM_DATA_WIDTH\'\n    output wire [`VX_MEM_DATA_WIDTH-1:0]    mem_req_data,\n                 ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:16: Define or directive not defined: \'`VX_MEM_TAG_WIDTH\'\n    output wire [`VX_MEM_TAG_WIDTH-1:0]     mem_req_tag,\n                 ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:21: Define or directive not defined: \'`VX_MEM_DATA_WIDTH\'\n    input wire [`VX_MEM_DATA_WIDTH-1:0]     mem_rsp_data,\n                ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:22: Define or directive not defined: \'`VX_MEM_TAG_WIDTH\'\n    input wire [`VX_MEM_TAG_WIDTH-1:0]      mem_rsp_tag,\n                ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:28: Define or directive not defined: \'`STATIC_ASSERT\'\n    `STATIC_ASSERT((`L3_ENABLE == 0 || `NUM_CLUSTERS > 1), ("invalid parameter"))\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:28: syntax error, unexpected \'(\'\n    `STATIC_ASSERT((`L3_ENABLE == 0 || `NUM_CLUSTERS > 1), ("invalid parameter"))\n                   ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:28: Define or directive not defined: \'`L3_ENABLE\'\n    `STATIC_ASSERT((`L3_ENABLE == 0 || `NUM_CLUSTERS > 1), ("invalid parameter"))\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:28: Define or directive not defined: \'`NUM_CLUSTERS\'\n    `STATIC_ASSERT((`L3_ENABLE == 0 || `NUM_CLUSTERS > 1), ("invalid parameter"))\n                                       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:30: Define or directive not defined: \'`NUM_CLUSTERS\'\n    wire [`NUM_CLUSTERS-1:0]                         per_cluster_mem_req_valid;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:31: Define or directive not defined: \'`NUM_CLUSTERS\'\n    wire [`NUM_CLUSTERS-1:0]                         per_cluster_mem_req_rw;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:32: Define or directive not defined: \'`NUM_CLUSTERS\'\n    wire [`NUM_CLUSTERS-1:0][`L2_MEM_BYTEEN_WIDTH-1:0] per_cluster_mem_req_byteen;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:32: Define or directive not defined: \'`L2_MEM_BYTEEN_WIDTH\'\n    wire [`NUM_CLUSTERS-1:0][`L2_MEM_BYTEEN_WIDTH-1:0] per_cluster_mem_req_byteen;\n                             ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:33: Define or directive not defined: \'`NUM_CLUSTERS\'\n    wire [`NUM_CLUSTERS-1:0][`L2_MEM_ADDR_WIDTH-1:0] per_cluster_mem_req_addr;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:33: Define or directive not defined: \'`L2_MEM_ADDR_WIDTH\'\n    wire [`NUM_CLUSTERS-1:0][`L2_MEM_ADDR_WIDTH-1:0] per_cluster_mem_req_addr;\n                             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:34: Define or directive not defined: \'`NUM_CLUSTERS\'\n    wire [`NUM_CLUSTERS-1:0][`L2_MEM_DATA_WIDTH-1:0] per_cluster_mem_req_data;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:34: Define or directive not defined: \'`L2_MEM_DATA_WIDTH\'\n    wire [`NUM_CLUSTERS-1:0][`L2_MEM_DATA_WIDTH-1:0] per_cluster_mem_req_data;\n                             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:35: Define or directive not defined: \'`NUM_CLUSTERS\'\n    wire [`NUM_CLUSTERS-1:0][`L2_MEM_TAG_WIDTH-1:0]  per_cluster_mem_req_tag;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:35: Define or directive not defined: \'`L2_MEM_TAG_WIDTH\'\n    wire [`NUM_CLUSTERS-1:0][`L2_MEM_TAG_WIDTH-1:0]  per_cluster_mem_req_tag;\n                             ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:36: Define or directive not defined: \'`NUM_CLUSTERS\'\n    wire [`NUM_CLUSTERS-1:0]                         per_cluster_mem_req_ready;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:38: Define or directive not defined: \'`NUM_CLUSTERS\'\n    wire [`NUM_CLUSTERS-1:0]                         per_cluster_mem_rsp_valid;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:39: Define or directive not defined: \'`NUM_CLUSTERS\'\n    wire [`NUM_CLUSTERS-1:0][`L2_MEM_DATA_WIDTH-1:0] per_cluster_mem_rsp_data;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:39: Define or directive not defined: \'`L2_MEM_DATA_WIDTH\'\n    wire [`NUM_CLUSTERS-1:0][`L2_MEM_DATA_WIDTH-1:0] per_cluster_mem_rsp_data;\n                             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:40: Define or directive not defined: \'`NUM_CLUSTERS\'\n    wire [`NUM_CLUSTERS-1:0][`L2_MEM_TAG_WIDTH-1:0]  per_cluster_mem_rsp_tag;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:40: Define or directive not defined: \'`L2_MEM_TAG_WIDTH\'\n    wire [`NUM_CLUSTERS-1:0][`L2_MEM_TAG_WIDTH-1:0]  per_cluster_mem_rsp_tag;\n                             ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:41: Define or directive not defined: \'`NUM_CLUSTERS\'\n    wire [`NUM_CLUSTERS-1:0]                         per_cluster_mem_rsp_ready;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:43: Define or directive not defined: \'`NUM_CLUSTERS\'\n    wire [`NUM_CLUSTERS-1:0]                         per_cluster_busy;\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:45: Define or directive not defined: \'`NUM_CLUSTERS\'\n    for (genvar i = 0; i < `NUM_CLUSTERS; i++) begin\n                           ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:45: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    for (genvar i = 0; i < `NUM_CLUSTERS; i++) begin\n                                        ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:47: Define or directive not defined: \'`RESET_RELAY\'\n        `RESET_RELAY (cluster_reset);\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:52: Define or directive not defined: \'`SCOPE_BIND_Vortex_cluster\'\n            `SCOPE_BIND_Vortex_cluster(i)\n            ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:72: syntax error, unexpected end\n    end\n    ^~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:76: Define or directive not defined: \'`L3_ENABLE\'\n    if (`L3_ENABLE) begin\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:76: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    if (`L3_ENABLE) begin\n                  ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:81: Define or directive not defined: \'`RESET_RELAY\'\n        `RESET_RELAY (l3_reset);\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:84: Define or directive not defined: \'`L3_CACHE_ID\'\n            .CACHE_ID           (`L3_CACHE_ID),\n                                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:85: Define or directive not defined: \'`L3_CACHE_SIZE\'\n            .CACHE_SIZE         (`L3_CACHE_SIZE),\n                                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:86: Define or directive not defined: \'`L3_CACHE_LINE_SIZE\'\n            .CACHE_LINE_SIZE    (`L3_CACHE_LINE_SIZE),\n                                 ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:87: Define or directive not defined: \'`L3_NUM_BANKS\'\n            .NUM_BANKS          (`L3_NUM_BANKS),\n                                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:88: Define or directive not defined: \'`L3_NUM_PORTS\'\n            .NUM_PORTS          (`L3_NUM_PORTS),\n                                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:89: Define or directive not defined: \'`L3_WORD_SIZE\'\n            .WORD_SIZE          (`L3_WORD_SIZE),\n                                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:90: Define or directive not defined: \'`L3_NUM_REQS\'\n            .NUM_REQS           (`L3_NUM_REQS),\n                                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:91: Define or directive not defined: \'`L3_CREQ_SIZE\'\n            .CREQ_SIZE          (`L3_CREQ_SIZE),\n                                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:92: Define or directive not defined: \'`L3_CRSQ_SIZE\'\n            .CRSQ_SIZE          (`L3_CRSQ_SIZE),\n                                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:93: Define or directive not defined: \'`L3_MSHR_SIZE\'\n            .MSHR_SIZE          (`L3_MSHR_SIZE),\n                                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:94: Define or directive not defined: \'`L3_MRSQ_SIZE\'\n            .MRSQ_SIZE          (`L3_MRSQ_SIZE),\n                                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/Vortex.sv:95: Define or directive not defined: \'`L3_MREQ_SIZE\'\n            .MREQ_SIZE          (`L3_MREQ_SIZE),\n                                 ^~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module Vortex (
    `SCOPE_IO_Vortex


    input  wire                             clk,
    input  wire                             reset,


    output wire                             mem_req_valid,
    output wire                             mem_req_rw,    
    output wire [`VX_MEM_BYTEEN_WIDTH-1:0]  mem_req_byteen,    
    output wire [`VX_MEM_ADDR_WIDTH-1:0]    mem_req_addr,
    output wire [`VX_MEM_DATA_WIDTH-1:0]    mem_req_data,
    output wire [`VX_MEM_TAG_WIDTH-1:0]     mem_req_tag,
    input  wire                             mem_req_ready,


    input wire                              mem_rsp_valid,        
    input wire [`VX_MEM_DATA_WIDTH-1:0]     mem_rsp_data,
    input wire [`VX_MEM_TAG_WIDTH-1:0]      mem_rsp_tag,
    output wire                             mem_rsp_ready,


    output wire                             busy
);
    `STATIC_ASSERT((`L3_ENABLE == 0 || `NUM_CLUSTERS > 1), ("invalid parameter"))

    wire [`NUM_CLUSTERS-1:0]                         per_cluster_mem_req_valid;
    wire [`NUM_CLUSTERS-1:0]                         per_cluster_mem_req_rw;
    wire [`NUM_CLUSTERS-1:0][`L2_MEM_BYTEEN_WIDTH-1:0] per_cluster_mem_req_byteen;
    wire [`NUM_CLUSTERS-1:0][`L2_MEM_ADDR_WIDTH-1:0] per_cluster_mem_req_addr;
    wire [`NUM_CLUSTERS-1:0][`L2_MEM_DATA_WIDTH-1:0] per_cluster_mem_req_data;
    wire [`NUM_CLUSTERS-1:0][`L2_MEM_TAG_WIDTH-1:0]  per_cluster_mem_req_tag;
    wire [`NUM_CLUSTERS-1:0]                         per_cluster_mem_req_ready;

    wire [`NUM_CLUSTERS-1:0]                         per_cluster_mem_rsp_valid;
    wire [`NUM_CLUSTERS-1:0][`L2_MEM_DATA_WIDTH-1:0] per_cluster_mem_rsp_data;
    wire [`NUM_CLUSTERS-1:0][`L2_MEM_TAG_WIDTH-1:0]  per_cluster_mem_rsp_tag;
    wire [`NUM_CLUSTERS-1:0]                         per_cluster_mem_rsp_ready;

    wire [`NUM_CLUSTERS-1:0]                         per_cluster_busy;

    for (genvar i = 0; i < `NUM_CLUSTERS; i++) begin

        `RESET_RELAY (cluster_reset);

        VX_cluster #(
            .CLUSTER_ID(i)
        ) cluster (
            `SCOPE_BIND_Vortex_cluster(i)

            .clk            (clk),
            .reset          (cluster_reset),

            .mem_req_valid  (per_cluster_mem_req_valid [i]),
            .mem_req_rw     (per_cluster_mem_req_rw    [i]),
            .mem_req_byteen (per_cluster_mem_req_byteen[i]),
            .mem_req_addr   (per_cluster_mem_req_addr  [i]),
            .mem_req_data   (per_cluster_mem_req_data  [i]),
            .mem_req_tag    (per_cluster_mem_req_tag   [i]),
            .mem_req_ready  (per_cluster_mem_req_ready [i]),

            .mem_rsp_valid  (per_cluster_mem_rsp_valid [i]),
            .mem_rsp_data   (per_cluster_mem_rsp_data  [i]),
            .mem_rsp_tag    (per_cluster_mem_rsp_tag   [i]),
            .mem_rsp_ready  (per_cluster_mem_rsp_ready [i]),

            .busy           (per_cluster_busy           [i])
        );
    end

    assign busy   = (| per_cluster_busy);

    if (`L3_ENABLE) begin
    `ifdef PERF_ENABLE
        VX_perf_cache_if perf_l3cache_if();
    `endif

        `RESET_RELAY (l3_reset);

        VX_cache #(
            .CACHE_ID           (`L3_CACHE_ID),
            .CACHE_SIZE         (`L3_CACHE_SIZE),
            .CACHE_LINE_SIZE    (`L3_CACHE_LINE_SIZE),
            .NUM_BANKS          (`L3_NUM_BANKS),
            .NUM_PORTS          (`L3_NUM_PORTS),
            .WORD_SIZE          (`L3_WORD_SIZE),
            .NUM_REQS           (`L3_NUM_REQS),
            .CREQ_SIZE          (`L3_CREQ_SIZE),
            .CRSQ_SIZE          (`L3_CRSQ_SIZE),
            .MSHR_SIZE          (`L3_MSHR_SIZE),
            .MRSQ_SIZE          (`L3_MRSQ_SIZE),
            .MREQ_SIZE          (`L3_MREQ_SIZE),
            .WRITE_ENABLE       (1),
            .CORE_TAG_WIDTH     (`L2_MEM_TAG_WIDTH),
            .CORE_TAG_ID_BITS   (0),
            .MEM_TAG_WIDTH      (`L3_MEM_TAG_WIDTH),
            .NC_ENABLE          (1)
        ) l3cache (
            `SCOPE_BIND_Vortex_l3cache
 
            .clk                (clk),
            .reset              (l3_reset),

        `ifdef PERF_ENABLE
            .perf_cache_if      (perf_l3cache_if),
        `endif


            .core_req_valid     (per_cluster_mem_req_valid),
            .core_req_rw        (per_cluster_mem_req_rw),
            .core_req_byteen    (per_cluster_mem_req_byteen),
            .core_req_addr      (per_cluster_mem_req_addr),
            .core_req_data      (per_cluster_mem_req_data),
            .core_req_tag       (per_cluster_mem_req_tag),
            .core_req_ready     (per_cluster_mem_req_ready),


            .core_rsp_valid     (per_cluster_mem_rsp_valid),
            .core_rsp_data      (per_cluster_mem_rsp_data),
            .core_rsp_tag       (per_cluster_mem_rsp_tag),              
            .core_rsp_ready     (per_cluster_mem_rsp_ready),
            `UNUSED_PIN (core_rsp_tmask),


            .mem_req_valid      (mem_req_valid),
            .mem_req_rw         (mem_req_rw),
            .mem_req_byteen     (mem_req_byteen),
            .mem_req_addr       (mem_req_addr),
            .mem_req_data       (mem_req_data),
            .mem_req_tag        (mem_req_tag),
            .mem_req_ready      (mem_req_ready),


            .mem_rsp_valid      (mem_rsp_valid),            
            .mem_rsp_data       (mem_rsp_data),
            .mem_rsp_tag        (mem_rsp_tag),
            .mem_rsp_ready      (mem_rsp_ready)
        );

    end else begin

        `RESET_RELAY (mem_arb_reset);

        VX_mem_arb #(
            .NUM_REQS     (`NUM_CLUSTERS),
            .DATA_WIDTH   (`L3_MEM_DATA_WIDTH),            
            .ADDR_WIDTH   (`L3_MEM_ADDR_WIDTH),
            .TAG_IN_WIDTH (`L2_MEM_TAG_WIDTH),
            .TYPE         ("R"),
            .BUFFERED_REQ (1),
            .BUFFERED_RSP (1)
        ) mem_arb (
            .clk            (clk),
            .reset          (mem_arb_reset),


            .req_valid_in   (per_cluster_mem_req_valid),
            .req_rw_in      (per_cluster_mem_req_rw),
            .req_byteen_in  (per_cluster_mem_req_byteen),
            .req_addr_in    (per_cluster_mem_req_addr),
            .req_data_in    (per_cluster_mem_req_data),  
            .req_tag_in     (per_cluster_mem_req_tag),  
            .req_ready_in   (per_cluster_mem_req_ready),


            .req_valid_out  (mem_req_valid),
            .req_rw_out     (mem_req_rw),        
            .req_byteen_out (mem_req_byteen),        
            .req_addr_out   (mem_req_addr),
            .req_data_out   (mem_req_data),
            .req_tag_out    (mem_req_tag),
            .req_ready_out  (mem_req_ready),


            .rsp_valid_out  (per_cluster_mem_rsp_valid),
            .rsp_data_out   (per_cluster_mem_rsp_data),
            .rsp_tag_out    (per_cluster_mem_rsp_tag),
            .rsp_ready_out  (per_cluster_mem_rsp_ready),
            

            .rsp_valid_in   (mem_rsp_valid),
            .rsp_tag_in     (mem_rsp_tag),
            .rsp_data_in    (mem_rsp_data),
            .rsp_ready_in   (mem_rsp_ready)
        );

    end

    `SCOPE_ASSIGN (reset, reset);
    `SCOPE_ASSIGN (mem_req_fire, mem_req_valid && mem_req_ready);
    `SCOPE_ASSIGN (mem_req_addr, `TO_FULL_ADDR(mem_req_addr));
    `SCOPE_ASSIGN (mem_req_rw,   mem_req_rw);
    `SCOPE_ASSIGN (mem_req_byteen, mem_req_byteen);
    `SCOPE_ASSIGN (mem_req_data, mem_req_data);
    `SCOPE_ASSIGN (mem_req_tag,  mem_req_tag);
    `SCOPE_ASSIGN (mem_rsp_fire, mem_rsp_valid && mem_rsp_ready);
    `SCOPE_ASSIGN (mem_rsp_data, mem_rsp_data);
    `SCOPE_ASSIGN (mem_rsp_tag,  mem_rsp_tag);
    `SCOPE_ASSIGN (busy, busy);

`ifdef DBG_TRACE_MEM
    always @(posedge clk) begin
        if (mem_req_valid && mem_req_ready) begin
            if (mem_req_rw)
                dpi_trace("%d: MEM Wr Req: addr=%0h, tag=%0h, byteen=%0h data=%0h\n", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_tag, mem_req_byteen, mem_req_data);
            else
                dpi_trace("%d: MEM Rd Req: addr=%0h, tag=%0h, byteen=%0h\n", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_tag, mem_req_byteen);
        end
        if (mem_rsp_valid && mem_rsp_ready) begin
            dpi_trace("%d: MEM Rsp: tag=%0h, data=%0h\n", $time, mem_rsp_tag, mem_rsp_data);
        end
    end
`endif


`ifndef NDEBUG
    always @(posedge clk) begin
        $fflush();
    end
`endif

endmodule
module Vortex (
    `SCOPE_IO_Vortex


    input  wire                             clk,
    input  wire                             reset,


    output wire                             mem_req_valid,
    output wire                             mem_req_rw,    
    output wire [`VX_MEM_BYTEEN_WIDTH-1:0]  mem_req_byteen,    
    output wire [`VX_MEM_ADDR_WIDTH-1:0]    mem_req_addr,
    output wire [`VX_MEM_DATA_WIDTH-1:0]    mem_req_data,
    output wire [`VX_MEM_TAG_WIDTH-1:0]     mem_req_tag,
    input  wire                             mem_req_ready,


    input wire                              mem_rsp_valid,        
    input wire [`VX_MEM_DATA_WIDTH-1:0]     mem_rsp_data,
    input wire [`VX_MEM_TAG_WIDTH-1:0]      mem_rsp_tag,
    output wire                             mem_rsp_ready,


    output wire                             busy
);

    `STATIC_ASSERT((`L3_ENABLE == 0 || `NUM_CLUSTERS > 1), ("invalid parameter"))

    wire [`NUM_CLUSTERS-1:0]                         per_cluster_mem_req_valid;
    wire [`NUM_CLUSTERS-1:0]                         per_cluster_mem_req_rw;
    wire [`NUM_CLUSTERS-1:0][`L2_MEM_BYTEEN_WIDTH-1:0] per_cluster_mem_req_byteen;
    wire [`NUM_CLUSTERS-1:0][`L2_MEM_ADDR_WIDTH-1:0] per_cluster_mem_req_addr;
    wire [`NUM_CLUSTERS-1:0][`L2_MEM_DATA_WIDTH-1:0] per_cluster_mem_req_data;
    wire [`NUM_CLUSTERS-1:0][`L2_MEM_TAG_WIDTH-1:0]  per_cluster_mem_req_tag;
    wire [`NUM_CLUSTERS-1:0]                         per_cluster_mem_req_ready;

    wire [`NUM_CLUSTERS-1:0]                         per_cluster_mem_rsp_valid;
    wire [`NUM_CLUSTERS-1:0][`L2_MEM_DATA_WIDTH-1:0] per_cluster_mem_rsp_data;
    wire [`NUM_CLUSTERS-1:0][`L2_MEM_TAG_WIDTH-1:0]  per_cluster_mem_rsp_tag;
    wire [`NUM_CLUSTERS-1:0]                         per_cluster_mem_rsp_ready;

    wire [`NUM_CLUSTERS-1:0]                         per_cluster_busy;

    for (genvar i = 0; i < `NUM_CLUSTERS; i++) begin

        `RESET_RELAY (cluster_reset);

        VX_cluster #(
            .CLUSTER_ID(i)
        ) cluster (
            `SCOPE_BIND_Vortex_cluster(i)

            .clk            (clk),
            .reset          (cluster_reset),

            .mem_req_valid  (per_cluster_mem_req_valid [i]),
            .mem_req_rw     (per_cluster_mem_req_rw    [i]),
            .mem_req_byteen (per_cluster_mem_req_byteen[i]),
            .mem_req_addr   (per_cluster_mem_req_addr  [i]),
            .mem_req_data   (per_cluster_mem_req_data  [i]),
            .mem_req_tag    (per_cluster_mem_req_tag   [i]),
            .mem_req_ready  (per_cluster_mem_req_ready [i]),

            .mem_rsp_valid  (per_cluster_mem_rsp_valid [i]),
            .mem_rsp_data   (per_cluster_mem_rsp_data  [i]),
            .mem_rsp_tag    (per_cluster_mem_rsp_tag   [i]),
            .mem_rsp_ready  (per_cluster_mem_rsp_ready [i]),

            .busy           (per_cluster_busy           [i])
        );
    end

    assign busy   = (| per_cluster_busy);

    if (`L3_ENABLE) begin
    `ifdef PERF_ENABLE
        VX_perf_cache_if perf_l3cache_if();
    `endif

        `RESET_RELAY (l3_reset);

        VX_cache #(
            .CACHE_ID           (`L3_CACHE_ID),
            .CACHE_SIZE         (`L3_CACHE_SIZE),
            .CACHE_LINE_SIZE    (`L3_CACHE_LINE_SIZE),
            .NUM_BANKS          (`L3_NUM_BANKS),
            .NUM_PORTS          (`L3_NUM_PORTS),
            .WORD_SIZE          (`L3_WORD_SIZE),
            .NUM_REQS           (`L3_NUM_REQS),
            .CREQ_SIZE          (`L3_CREQ_SIZE),
            .CRSQ_SIZE          (`L3_CRSQ_SIZE),
            .MSHR_SIZE          (`L3_MSHR_SIZE),
            .MRSQ_SIZE          (`L3_MRSQ_SIZE),
            .MREQ_SIZE          (`L3_MREQ_SIZE),
            .WRITE_ENABLE       (1),
            .CORE_TAG_WIDTH     (`L2_MEM_TAG_WIDTH),
            .CORE_TAG_ID_BITS   (0),
            .MEM_TAG_WIDTH      (`L3_MEM_TAG_WIDTH),
            .NC_ENABLE          (1)
        ) l3cache (
            `SCOPE_BIND_Vortex_l3cache
 
            .clk                (clk),
            .reset              (l3_reset),

        `ifdef PERF_ENABLE
            .perf_cache_if      (perf_l3cache_if),
        `endif


            .core_req_valid     (per_cluster_mem_req_valid),
            .core_req_rw        (per_cluster_mem_req_rw),
            .core_req_byteen    (per_cluster_mem_req_byteen),
            .core_req_addr      (per_cluster_mem_req_addr),
            .core_req_data      (per_cluster_mem_req_data),
            .core_req_tag       (per_cluster_mem_req_tag),
            .core_req_ready     (per_cluster_mem_req_ready),


            .core_rsp_valid     (per_cluster_mem_rsp_valid),
            .core_rsp_data      (per_cluster_mem_rsp_data),
            .core_rsp_tag       (per_cluster_mem_rsp_tag),              
            .core_rsp_ready     (per_cluster_mem_rsp_ready),
            `UNUSED_PIN (core_rsp_tmask),


            .mem_req_valid      (mem_req_valid),
            .mem_req_rw         (mem_req_rw),
            .mem_req_byteen     (mem_req_byteen),
            .mem_req_addr       (mem_req_addr),
            .mem_req_data       (mem_req_data),
            .mem_req_tag        (mem_req_tag),
            .mem_req_ready      (mem_req_ready),


            .mem_rsp_valid      (mem_rsp_valid),            
            .mem_rsp_data       (mem_rsp_data),
            .mem_rsp_tag        (mem_rsp_tag),
            .mem_rsp_ready      (mem_rsp_ready)
        );

    end else begin

        `RESET_RELAY (mem_arb_reset);

        VX_mem_arb #(
            .NUM_REQS     (`NUM_CLUSTERS),
            .DATA_WIDTH   (`L3_MEM_DATA_WIDTH),            
            .ADDR_WIDTH   (`L3_MEM_ADDR_WIDTH),
            .TAG_IN_WIDTH (`L2_MEM_TAG_WIDTH),
            .TYPE         ("R"),
            .BUFFERED_REQ (1),
            .BUFFERED_RSP (1)
        ) mem_arb (
            .clk            (clk),
            .reset          (mem_arb_reset),


            .req_valid_in   (per_cluster_mem_req_valid),
            .req_rw_in      (per_cluster_mem_req_rw),
            .req_byteen_in  (per_cluster_mem_req_byteen),
            .req_addr_in    (per_cluster_mem_req_addr),
            .req_data_in    (per_cluster_mem_req_data),  
            .req_tag_in     (per_cluster_mem_req_tag),  
            .req_ready_in   (per_cluster_mem_req_ready),


            .req_valid_out  (mem_req_valid),
            .req_rw_out     (mem_req_rw),        
            .req_byteen_out (mem_req_byteen),        
            .req_addr_out   (mem_req_addr),
            .req_data_out   (mem_req_data),
            .req_tag_out    (mem_req_tag),
            .req_ready_out  (mem_req_ready),


            .rsp_valid_out  (per_cluster_mem_rsp_valid),
            .rsp_data_out   (per_cluster_mem_rsp_data),
            .rsp_tag_out    (per_cluster_mem_rsp_tag),
            .rsp_ready_out  (per_cluster_mem_rsp_ready),
            

            .rsp_valid_in   (mem_rsp_valid),
            .rsp_tag_in     (mem_rsp_tag),
            .rsp_data_in    (mem_rsp_data),
            .rsp_ready_in   (mem_rsp_ready)
        );

    end

    `SCOPE_ASSIGN (reset, reset);
    `SCOPE_ASSIGN (mem_req_fire, mem_req_valid && mem_req_ready);
    `SCOPE_ASSIGN (mem_req_addr, `TO_FULL_ADDR(mem_req_addr));
    `SCOPE_ASSIGN (mem_req_rw,   mem_req_rw);
    `SCOPE_ASSIGN (mem_req_byteen, mem_req_byteen);
    `SCOPE_ASSIGN (mem_req_data, mem_req_data);
    `SCOPE_ASSIGN (mem_req_tag,  mem_req_tag);
    `SCOPE_ASSIGN (mem_rsp_fire, mem_rsp_valid && mem_rsp_ready);
    `SCOPE_ASSIGN (mem_rsp_data, mem_rsp_data);
    `SCOPE_ASSIGN (mem_rsp_tag,  mem_rsp_tag);
    `SCOPE_ASSIGN (busy, busy);

`ifdef DBG_TRACE_MEM
    always @(posedge clk) begin
        if (mem_req_valid && mem_req_ready) begin
            if (mem_req_rw)
                dpi_trace("%d: MEM Wr Req: addr=%0h, tag=%0h, byteen=%0h data=%0h\n", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_tag, mem_req_byteen, mem_req_data);
            else
                dpi_trace("%d: MEM Rd Req: addr=%0h, tag=%0h, byteen=%0h\n", $time, `TO_FULL_ADDR(mem_req_addr), mem_req_tag, mem_req_byteen);
        end
        if (mem_rsp_valid && mem_rsp_ready) begin
            dpi_trace("%d: MEM Rsp: tag=%0h, data=%0h\n", $time, mem_rsp_tag, mem_rsp_data);
        end
    end
`endif


`ifndef NDEBUG
    always @(posedge clk) begin
        $fflush();
    end
`endif

endmodule