data/full_repos/permissive/461000256/hdl/Instruction_Decode.v
1: b'%Warning-WIDTH: data/full_repos/permissive/461000256/hdl/Instruction_Decode.v:43: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                : ... In instance Instruction_Decode\n   reg1 = 32\'bx;\n        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/461000256/hdl/Instruction_Decode.v:44: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                : ... In instance Instruction_Decode\n   reg2 = 32\'bx;\n        ^\n%Error: Exiting due to 2 warning(s)\n'
module Instruction_Decode (
	input  wire [`IW-1:0]		in_inst,
	output reg  [`RFW-1:0]	reg1,
	output reg  [`RFW-1:0]	reg2
);



	
	wire [4:0] rs2, rs1, rd;
	wire [6:0] funct7, opcode;
	wire [2:0] funct3;
	wire [11:0] imm;
	
	assign funct7 	= in_inst[31:25];
	assign rs2 		= in_inst[24:20];
	assign rs1		= in_inst[19:15];
	assign funct3	= in_inst[14:12];
	assign rd		= in_inst[11:7 ];
	assign opcode	= in_inst[6 :0 ];
	
	assign imm		= in_inst[31:20];
	
	always @(*) begin
		if (opcode == 7'h33 | opcode == 7'h3A) begin

			reg1 	= rs1[`RFW-1:0];
			reg2 	= rs2[`RFW-1:0];
		end
		else if (opcode == 7'h03 | opcode == 7'h0F | opcode == 7'h13 | opcode == 7'h1B) begin

			reg1 = rs1[`RFW-1:0];
			reg2 = rs1[`RFW-1:0];
			
		end else begin
			reg1 = 32'bx;
			reg2 = 32'bx;
		end
	end

endmodule
module Instruction_Decode (
	input  wire [`IW-1:0]		in_inst,
	output reg  [`RFW-1:0]	reg1,
	output reg  [`RFW-1:0]	reg2
);




	
	wire [4:0] rs2, rs1, rd;
	wire [6:0] funct7, opcode;
	wire [2:0] funct3;
	wire [11:0] imm;
	
	assign funct7 	= in_inst[31:25];
	assign rs2 		= in_inst[24:20];
	assign rs1		= in_inst[19:15];
	assign funct3	= in_inst[14:12];
	assign rd		= in_inst[11:7 ];
	assign opcode	= in_inst[6 :0 ];
	
	assign imm		= in_inst[31:20];
	
	always @(*) begin
		if (opcode == 7'h33 | opcode == 7'h3A) begin

			reg1 	= rs1[`RFW-1:0];
			reg2 	= rs2[`RFW-1:0];
		end
		else if (opcode == 7'h03 | opcode == 7'h0F | opcode == 7'h13 | opcode == 7'h1B) begin

			reg1 = rs1[`RFW-1:0];
			reg2 = rs1[`RFW-1:0];
			
		end else begin
			reg1 = 32'bx;
			reg2 = 32'bx;
		end
	end

endmodule