data/full_repos/permissive/40581558/fpga_sim/model_rec/transmit_test_model.v
1: b'%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/model_rec/transmit_test_model.v:60: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'Focus_Num_Pre\' generates 1 bits.\n                                                                                               : ... In instance transmit_test_model\n  Focus_Num_reg <= Focus_Num_Pre;\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/model_rec/transmit_test_model.v:123: Operator GT expects 2 bits on the LHS, but LHS\'s VARREF \'Focus_Num_Pre\' generates 1 bits.\n                                                                                                : ... In instance transmit_test_model\n    if(Focus_Num_Pre >2\'b00) \n                     ^\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/model_rec/transmit_test_model.v:114: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'8\'h50\' generates 8 bits.\n                                                                                                : ... In instance transmit_test_model\n   else if(Pulse_Counter < (Line_Period + 8\'d80))   \n                                        ^\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/model_rec/transmit_test_model.v:154: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'8\'h5a\' generates 8 bits.\n                                                                                                : ... In instance transmit_test_model\n                        else if (Envelop_Counter >= (Line_Period + 8\'d90)&&Envelop_Counter <(Line_Period + 8\'d95))  \n                                                                 ^\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/model_rec/transmit_test_model.v:154: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'8\'h5f\' generates 8 bits.\n                                                                                                : ... In instance transmit_test_model\n                        else if (Envelop_Counter >= (Line_Period + 8\'d90)&&Envelop_Counter <(Line_Period + 8\'d95))  \n                                                                                                         ^\n%Warning-WIDTH: data/full_repos/permissive/40581558/fpga_sim/model_rec/transmit_test_model.v:149: Operator ADD expects 32 bits on the RHS, but RHS\'s CONST \'8\'h5a\' generates 8 bits.\n                                                                                                : ... In instance transmit_test_model\n                        else  if (Envelop_Counter < (Line_Period + 8\'d90)) \n                                                                 ^\n%Error: data/full_repos/permissive/40581558/fpga_sim/model_rec/transmit_test_model.v:173: Cannot find file containing module: \'cc3200_test_model\'\n             cc3200_test_model      cc3200_test_model (\n             ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/40581558/fpga_sim/model_rec,data/full_repos/permissive/40581558/cc3200_test_model\n             data/full_repos/permissive/40581558/fpga_sim/model_rec,data/full_repos/permissive/40581558/cc3200_test_model.v\n             data/full_repos/permissive/40581558/fpga_sim/model_rec,data/full_repos/permissive/40581558/cc3200_test_model.sv\n             cc3200_test_model\n             cc3200_test_model.v\n             cc3200_test_model.sv\n             obj_dir/cc3200_test_model\n             obj_dir/cc3200_test_model.v\n             obj_dir/cc3200_test_model.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n'
module   transmit_test_model  (

       input                 clk_100M ,
      
       input                 reset_n  ,

      output      [7:0]      Line_Num ,

      output      [1:0]      Focus_Num,
       
      output                 Pr_Gate  ,
     
      output                 RX_Gate  ,
      
      output                 End_Gate ,
      
      output                 Envelop   
   
   );


   


     
   
      
      wire                        Focus_Num_Pre    ;





      reg [31:0]                 Line_Period       ;

      reg [31:0]                 Envelop_Counter   ;

      reg [31:0]                 Pulse_Counter     ;

      reg                        Pr_Gate_reg       ;

      reg                        RX_Gate_reg       ;

      reg                        End_Gate_reg      ;

      reg   [1:0]                Focus_Num_reg     ;

     
      reg                        Envelop_reg       ;



        
       
        always @(posedge End_Gate_reg) 
        begin

		Focus_Num_reg <= Focus_Num_Pre;

	end




	
	always @(posedge Pr_Gate_reg) 
         begin
		case(Focus_Num_reg[1:0]) 
			2'b00:
				Line_Period<=32'd12000;
			2'b01:
				Line_Period<=32'd12000;
			2'b10:
				Line_Period<=32'd29000;
			2'b11:
				Line_Period<=32'd29000;
		endcase
	end





         always @(posedge  clk_100M or posedge Envelop) 
           begin
		if(Envelop) 
                   begin
			  Pulse_Counter <= 32'd0;
		   end
		else begin
			if(Pulse_Counter < 32'd3000)
			begin
				Pulse_Counter <= Pulse_Counter + 1'b1;
				Pr_Gate_reg   <= 1'b1;
				RX_Gate_reg   <= 1'b0;
				End_Gate_reg  <= 1'b0;
			end
			else if(Pulse_Counter < 32'd3250)
			begin
				Pulse_Counter <= Pulse_Counter + 1'b1;
				Pr_Gate_reg   <= 1'b0;
				RX_Gate_reg   <= 1'b1;
				End_Gate_reg  <= 1'b0;
			end
			else if(Pulse_Counter < Line_Period)  
			begin
				Pulse_Counter <= Pulse_Counter + 1'b1;
				Pr_Gate_reg   <= 1'b0;
				RX_Gate_reg   <= 1'b0;
				End_Gate_reg  <= 1'b0;
			end
			else if(Pulse_Counter < (Line_Period + 8'd80))
			begin
				Pulse_Counter <= Pulse_Counter + 1'b1;
				Pr_Gate_reg   <= 1'b0;
				RX_Gate_reg   <= 1'b0;
				End_Gate_reg  <= 1'b1;
			end		
			else begin
				
				if(Focus_Num_Pre >2'b00) 
					Pulse_Counter <= 32'd0;
				else 
					Pulse_Counter <= 32'd65536;
					
				Pr_Gate_reg     <= 1'b0;
				RX_Gate_reg     <= 1'b0;
				End_Gate_reg    <= 1'b0;
			end	
		end
	end 

  
                
         

            always@ (posedge  clk_100M   or  negedge reset_n ) 
       
              begin
                       if  (!reset_n)     
                               
                             begin
                                     Envelop_reg      <=  0 ;
                                     Envelop_Counter  <=  0 ; 
                             end

                        else  if (Envelop_Counter < (Line_Period + 8'd90)) 
                             begin
                                     Envelop_Counter  <= Envelop_Counter + 1'b1;
                                     Envelop_reg      <=  1'b0 ;    
                             end
                        else if (Envelop_Counter >= (Line_Period + 8'd90)&&Envelop_Counter <(Line_Period + 8'd95))  
                             begin
                                     Envelop_Counter  <= Envelop_Counter + 1'b1;
                                     Envelop_reg      <=  1'b1 ;    
                             end   
                        else
                            begin
                                     Envelop_reg      <=  0 ;
                                     Envelop_Counter  <=  0 ; 
                             end
                 


              end




       
             cc3200_test_model      cc3200_test_model (

                     .clk_in         (clk_100M)   ,
                     .reset_n        (reset_n)    ,
                     .RX_Gate        (RX_Gate_reg),
                     .Envelop        (Envelop_reg),
                     

                     .line_num       (Line_Num) ,
                     .focus_num      (Focus_Num_Pre)
                     
                  


                );
 


             
    assign                      Pr_Gate   =     Pr_Gate_reg  ;

   assign                      RX_Gate   =     RX_Gate_reg  ;

   assign                      End_Gate  =     End_Gate_reg ;
  
   assign                      Focus_Num =     Focus_Num_reg; 

  
   assign                      Envelop    =    Envelop_reg  ;






 endmodule
module   transmit_test_model  (

       input                 clk_100M ,
      
       input                 reset_n  ,

      output      [7:0]      Line_Num ,

      output      [1:0]      Focus_Num,
       
      output                 Pr_Gate  ,
     
      output                 RX_Gate  ,
      
      output                 End_Gate ,
      
      output                 Envelop   
   
   );



   


     
   
      
      wire                        Focus_Num_Pre    ;





      reg [31:0]                 Line_Period       ;

      reg [31:0]                 Envelop_Counter   ;

      reg [31:0]                 Pulse_Counter     ;

      reg                        Pr_Gate_reg       ;

      reg                        RX_Gate_reg       ;

      reg                        End_Gate_reg      ;

      reg   [1:0]                Focus_Num_reg     ;

     
      reg                        Envelop_reg       ;



        
       
        always @(posedge End_Gate_reg) 
        begin

		Focus_Num_reg <= Focus_Num_Pre;

	end




	
	always @(posedge Pr_Gate_reg) 
         begin
		case(Focus_Num_reg[1:0]) 
			2'b00:
				Line_Period<=32'd12000;
			2'b01:
				Line_Period<=32'd12000;
			2'b10:
				Line_Period<=32'd29000;
			2'b11:
				Line_Period<=32'd29000;
		endcase
	end





         always @(posedge  clk_100M or posedge Envelop) 
           begin
		if(Envelop) 
                   begin
			  Pulse_Counter <= 32'd0;
		   end
		else begin
			if(Pulse_Counter < 32'd3000)
			begin
				Pulse_Counter <= Pulse_Counter + 1'b1;
				Pr_Gate_reg   <= 1'b1;
				RX_Gate_reg   <= 1'b0;
				End_Gate_reg  <= 1'b0;
			end
			else if(Pulse_Counter < 32'd3250)
			begin
				Pulse_Counter <= Pulse_Counter + 1'b1;
				Pr_Gate_reg   <= 1'b0;
				RX_Gate_reg   <= 1'b1;
				End_Gate_reg  <= 1'b0;
			end
			else if(Pulse_Counter < Line_Period)  
			begin
				Pulse_Counter <= Pulse_Counter + 1'b1;
				Pr_Gate_reg   <= 1'b0;
				RX_Gate_reg   <= 1'b0;
				End_Gate_reg  <= 1'b0;
			end
			else if(Pulse_Counter < (Line_Period + 8'd80))
			begin
				Pulse_Counter <= Pulse_Counter + 1'b1;
				Pr_Gate_reg   <= 1'b0;
				RX_Gate_reg   <= 1'b0;
				End_Gate_reg  <= 1'b1;
			end		
			else begin
				
				if(Focus_Num_Pre >2'b00) 
					Pulse_Counter <= 32'd0;
				else 
					Pulse_Counter <= 32'd65536;
					
				Pr_Gate_reg     <= 1'b0;
				RX_Gate_reg     <= 1'b0;
				End_Gate_reg    <= 1'b0;
			end	
		end
	end 

  
                
         

            always@ (posedge  clk_100M   or  negedge reset_n ) 
       
              begin
                       if  (!reset_n)     
                               
                             begin
                                     Envelop_reg      <=  0 ;
                                     Envelop_Counter  <=  0 ; 
                             end

                        else  if (Envelop_Counter < (Line_Period + 8'd90)) 
                             begin
                                     Envelop_Counter  <= Envelop_Counter + 1'b1;
                                     Envelop_reg      <=  1'b0 ;    
                             end
                        else if (Envelop_Counter >= (Line_Period + 8'd90)&&Envelop_Counter <(Line_Period + 8'd95))  
                             begin
                                     Envelop_Counter  <= Envelop_Counter + 1'b1;
                                     Envelop_reg      <=  1'b1 ;    
                             end   
                        else
                            begin
                                     Envelop_reg      <=  0 ;
                                     Envelop_Counter  <=  0 ; 
                             end
                 


              end




       
             cc3200_test_model      cc3200_test_model (

                     .clk_in         (clk_100M)   ,
                     .reset_n        (reset_n)    ,
                     .RX_Gate        (RX_Gate_reg),
                     .Envelop        (Envelop_reg),
                     

                     .line_num       (Line_Num) ,
                     .focus_num      (Focus_Num_Pre)
                     
                  


                );
 


             
    assign                      Pr_Gate   =     Pr_Gate_reg  ;

   assign                      RX_Gate   =     RX_Gate_reg  ;

   assign                      End_Gate  =     End_Gate_reg ;
  
   assign                      Focus_Num =     Focus_Num_reg; 

  
   assign                      Envelop    =    Envelop_reg  ;






 endmodule