data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/SimulationModules/CoreDatapathModulesVerification/OnChipDataMemoryTestbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/SimulationModules/CoreDatapathModulesVerification/OnChipDataMemoryTestbench.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #15\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/SimulationModules/CoreDatapathModulesVerification/OnChipDataMemoryTestbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/SimulationModules/CoreDatapathModulesVerification/OnChipDataMemoryTestbench.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/SimulationModules/CoreDatapathModulesVerification/OnChipDataMemoryTestbench.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/SimulationModules/CoreDatapathModulesVerification/OnChipDataMemoryTestbench.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/SimulationModules/CoreDatapathModulesVerification/OnChipDataMemoryTestbench.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/SimulationModules/CoreDatapathModulesVerification/OnChipDataMemoryTestbench.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/SimulationModules/CoreDatapathModulesVerification/OnChipDataMemoryTestbench.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/SimulationModules/CoreDatapathModulesVerification/OnChipDataMemoryTestbench.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/SimulationModules/CoreDatapathModulesVerification/OnChipDataMemoryTestbench.v:53: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/SimulationModules/CoreDatapathModulesVerification/OnChipDataMemoryTestbench.v:60: Unsupported: Ignoring delay on this delayed statement.\n    always #5 clk = ~clk;\n           ^\n%Error: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/SimulationModules/CoreDatapathModulesVerification/OnChipDataMemoryTestbench.v:18: Cannot find file containing module: \'OnChipDataMemory\'\n    OnChipDataMemory ocdm(address, writeData, signExtended, writeSize, writeEnable, clk, readData);\n    ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/SimulationModules/CoreDatapathModulesVerification,data/full_repos/permissive/423012938/OnChipDataMemory\n             data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/SimulationModules/CoreDatapathModulesVerification,data/full_repos/permissive/423012938/OnChipDataMemory.v\n             data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/SimulationModules/CoreDatapathModulesVerification,data/full_repos/permissive/423012938/OnChipDataMemory.sv\n             OnChipDataMemory\n             OnChipDataMemory.v\n             OnChipDataMemory.sv\n             obj_dir/OnChipDataMemory\n             obj_dir/OnChipDataMemory.v\n             obj_dir/OnChipDataMemory.sv\n%Error: Exiting due to 1 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module OnChipDataMemoryTestbench ();
    reg [10:0] address;
    reg [63:0] writeData;
    reg signExtended;
    reg [1:0] writeSize;
    reg writeEnable;
    reg clk;
    reg [191:0] TESTNAME;

    wire [63:0] readData;

    OnChipDataMemory ocdm(address, writeData, signExtended, writeSize, writeEnable, clk, readData);

    initial begin

        TESTNAME = "endianness verification";
        address = 0;
        writeData = 64'h0;
        signExtended = 0;
        writeSize = 0;
        writeEnable = 0;
        clk = 0;
        #15
        address = 0;
        writeData = 64'h0123456789ABCDEF;
        writeSize = 2'b11;
        writeEnable = 1;
        #10
        address = 0;
        writeData = 64'h0;
        writeSize = 2'b00;
        writeEnable = 0;
        #10
        address = 1;
        #10
        address = 2;
        #10
        address = 3;
        #10
        address = 4;
        #10
        address = 5;
        #10
        address = 6;
        #10
        address = 7;
        #10
        address = 8;
        

    end


    always #5 clk = ~clk;

endmodule
module OnChipDataMemoryTestbench ();

    reg [10:0] address;
    reg [63:0] writeData;
    reg signExtended;
    reg [1:0] writeSize;
    reg writeEnable;
    reg clk;
    reg [191:0] TESTNAME;

    wire [63:0] readData;

    OnChipDataMemory ocdm(address, writeData, signExtended, writeSize, writeEnable, clk, readData);

    initial begin

        TESTNAME = "endianness verification";
        address = 0;
        writeData = 64'h0;
        signExtended = 0;
        writeSize = 0;
        writeEnable = 0;
        clk = 0;
        #15
        address = 0;
        writeData = 64'h0123456789ABCDEF;
        writeSize = 2'b11;
        writeEnable = 1;
        #10
        address = 0;
        writeData = 64'h0;
        writeSize = 2'b00;
        writeEnable = 0;
        #10
        address = 1;
        #10
        address = 2;
        #10
        address = 3;
        #10
        address = 4;
        #10
        address = 5;
        #10
        address = 6;
        #10
        address = 7;
        #10
        address = 8;
        

    end


    always #5 clk = ~clk;

endmodule