data/full_repos/permissive/427041400/verilog/rtl/avsdpll.v
data/verilator_xmls/af5b09d3-664d-479d-92e6-7725144f1ba1.xml
module avsdpll (
`ifdef USE_POWER_PINS
	inout vccd1,
	inout vssd1,
`endif
   output reg  CLK,
   input  wire VCO_IN,
   input  wire ENb_CP,
   input  wire ENb_VCO,
   input  wire REF
);

`ifdef SIM
   real period, lastedge, refpd;

   initial begin
      lastedge = 0.0;
      period = 25.0;
      CLK <= 0;
   end


   always @(CLK or ENb_VCO) begin
      if (ENb_VCO == 1'b1) begin
         #(period / 2.0);
         CLK <= (CLK === 1'b0);
      end
      else if (ENb_VCO == 1'b0) begin
         CLK <= 1'b0;
      end 
      else begin
         CLK <= 1'bx;
      end
   end
   

   always @(posedge REF) begin
      if (lastedge > 0.0) begin
         refpd = $realtime - lastedge;


         period =  (refpd / 8.0) ;
      end
      lastedge = $realtime;
   end
`endif

endmodule
module avsdpll (
`ifdef USE_POWER_PINS
	inout vccd1,
	inout vssd1,
`endif
   output reg  CLK,
   input  wire VCO_IN,
   input  wire ENb_CP,
   input  wire ENb_VCO,
   input  wire REF
);


`ifdef SIM
   real period, lastedge, refpd;

   initial begin
      lastedge = 0.0;
      period = 25.0;
      CLK <= 0;
   end


   always @(CLK or ENb_VCO) begin
      if (ENb_VCO == 1'b1) begin
         #(period / 2.0);
         CLK <= (CLK === 1'b0);
      end
      else if (ENb_VCO == 1'b0) begin
         CLK <= 1'b0;
      end 
      else begin
         CLK <= 1'bx;
      end
   end
   

   always @(posedge REF) begin
      if (lastedge > 0.0) begin
         refpd = $realtime - lastedge;


         period =  (refpd / 8.0) ;
      end
      lastedge = $realtime;
   end
`endif

endmodule