data/full_repos/permissive/502135797/Lab8_April_20_2022/Code/top_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab8_April_20_2022/Code/top_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n            #100\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab8_April_20_2022/Code/top_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n            #100    \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab8_April_20_2022/Code/top_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n            #100    \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab8_April_20_2022/Code/top_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n            #1000\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab8_April_20_2022/Code/top_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk_tb = ~clk_tb;\n        ^\n%Error: data/full_repos/permissive/502135797/Lab8_April_20_2022/Code/top_tb.v:18: Cannot find file containing module: \'top\'\n    top top_t(\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/502135797/Lab8_April_20_2022/Code,data/full_repos/permissive/502135797/top\n             data/full_repos/permissive/502135797/Lab8_April_20_2022/Code,data/full_repos/permissive/502135797/top.v\n             data/full_repos/permissive/502135797/Lab8_April_20_2022/Code,data/full_repos/permissive/502135797/top.sv\n             top\n             top.v\n             top.sv\n             obj_dir/top\n             obj_dir/top.v\n             obj_dir/top.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module top_tb();
    reg [3:0] opatb;
    reg [3:0] opbtb;
    reg audtb;
    reg budtb;
    reg altb;
    reg bltb;
    reg [1:0] asmtb;
    reg but1;
    reg clk_tb;
    
    wire [6:0] Cnode_tb;
    wire dp_tb;
    wire [7:0] AN_tb;

    
    top top_t(
        .clkt(clk_tb),
        .asw(opatb),
        .bsw(opbtb),
        .aud(audtb),
        .bud(budtb),
        .aload(altb),
        .bload(bltb),
        .in(asmtb),
        .button(but1),

         .Cnode1(Cnode_tb),
         .seg(dp_tb),
         .AN1(AN_tb)

    );
    initial
        begin: TEST
            asmtb = 2;      
            opatb = 4;
            opbtb = 2;
            audtb = 1;
            budtb = 1;
            but1 = 1;
            clk_tb=0;
            #100

            asmtb = 1;      
            opatb = 3;
            opbtb = 6;
            audtb = 0;
            budtb = 1;
            but1 = 0;
            altb=1;
            bltb=0; 

            #100    
            
            asmtb = 2;      
            opatb = 5;
            opbtb = 2;
            audtb = 1;
            budtb = 0;
            but1 = 1; 
            
            #100    
            asmtb = 3;      
            opatb = 8;
            opbtb = 9;
            audtb = 1;
            budtb = 1;
            but1 = 0; 
            #1000
            $finish;
        end
        
        always   
        begin
        #5 clk_tb = ~clk_tb;
        end        
  
endmodule
module top_tb();

    reg [3:0] opatb;
    reg [3:0] opbtb;
    reg audtb;
    reg budtb;
    reg altb;
    reg bltb;
    reg [1:0] asmtb;
    reg but1;
    reg clk_tb;
    
    wire [6:0] Cnode_tb;
    wire dp_tb;
    wire [7:0] AN_tb;

    
    top top_t(
        .clkt(clk_tb),
        .asw(opatb),
        .bsw(opbtb),
        .aud(audtb),
        .bud(budtb),
        .aload(altb),
        .bload(bltb),
        .in(asmtb),
        .button(but1),

         .Cnode1(Cnode_tb),
         .seg(dp_tb),
         .AN1(AN_tb)

    );
    initial
        begin: TEST
            asmtb = 2;      
            opatb = 4;
            opbtb = 2;
            audtb = 1;
            budtb = 1;
            but1 = 1;
            clk_tb=0;
            #100

            asmtb = 1;      
            opatb = 3;
            opbtb = 6;
            audtb = 0;
            budtb = 1;
            but1 = 0;
            altb=1;
            bltb=0; 

            #100    
            
            asmtb = 2;      
            opatb = 5;
            opbtb = 2;
            audtb = 1;
            budtb = 0;
            but1 = 1; 
            
            #100    
            asmtb = 3;      
            opatb = 8;
            opbtb = 9;
            audtb = 1;
            budtb = 1;
            but1 = 0; 
            #1000
            $finish;
        end
        
        always   
        begin
        #5 clk_tb = ~clk_tb;
        end        
  
endmodule