data/full_repos/permissive/523043017/Verilog microcontroller/test.v
1: b'%Error: Cannot find file containing module: microcontroller,data/full_repos/permissive/523043017\n        ... Looked in:\n             data/full_repos/permissive/523043017/Verilog/microcontroller,data/full_repos/permissive/523043017\n             data/full_repos/permissive/523043017/Verilog/microcontroller,data/full_repos/permissive/523043017.v\n             data/full_repos/permissive/523043017/Verilog/microcontroller,data/full_repos/permissive/523043017.sv\n             microcontroller,data/full_repos/permissive/523043017\n             microcontroller,data/full_repos/permissive/523043017.v\n             microcontroller,data/full_repos/permissive/523043017.sv\n             obj_dir/microcontroller,data/full_repos/permissive/523043017\n             obj_dir/microcontroller,data/full_repos/permissive/523043017.v\n             obj_dir/microcontroller,data/full_repos/permissive/523043017.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/523043017/Verilog\n%Error: Cannot find file containing module: microcontroller/test.v\n%Error: Exiting due to 3 error(s)\n'
module test;
	reg clk;
	reg int;
	input wire[7:0] PORTA;
    input wire[7:0] PORTB;
    input wire[7:0] PORTC;
    input wire[7:0] PORTD;
	microcontroller MK(clk, int, PORTA, PORTB, PORTC, PORTD);

	always
		#10 clk = ~clk;
		
	initial
	begin
		clk = 0;
		int = 0;
		
		#1000;
		
		@(posedge clk)
			int = 1;
		
		@(posedge clk)
			int = 0;

	end
	
	initial
	begin
		#1000 $finish;
	end
	
	initial
	begin
		$dumpfile("out.vcd");
		$dumpvars(0, test);
	end
	


	
endmodule
module test;

	reg clk;
	reg int;
	input wire[7:0] PORTA;
    input wire[7:0] PORTB;
    input wire[7:0] PORTC;
    input wire[7:0] PORTD;
	microcontroller MK(clk, int, PORTA, PORTB, PORTC, PORTD);

	always
		#10 clk = ~clk;
		
	initial
	begin
		clk = 0;
		int = 0;
		
		#1000;
		
		@(posedge clk)
			int = 1;
		
		@(posedge clk)
			int = 0;

	end
	
	initial
	begin
		#1000 $finish;
	end
	
	initial
	begin
		$dumpfile("out.vcd");
		$dumpvars(0, test);
	end
	


	
endmodule