data/full_repos/permissive/528831163/tb/key_scheduler_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/528831163/tb/key_scheduler_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n        #5 clk = ~clk;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/528831163/tb/key_scheduler_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #20;\n        ^\n%Error: data/full_repos/permissive/528831163/tb/key_scheduler_tb.v:8: Cannot find file containing module: \'key_scheduler\'\n    key_scheduler ks(.clk(clk), .rst(rst), .round_counter(round_counter), .i_ks_oldkey(i_ks_oldkey), .o_ks_newkey(o_ks_newkey));\n    ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/528831163/tb,data/full_repos/permissive/528831163/key_scheduler\n             data/full_repos/permissive/528831163/tb,data/full_repos/permissive/528831163/key_scheduler.v\n             data/full_repos/permissive/528831163/tb,data/full_repos/permissive/528831163/key_scheduler.sv\n             key_scheduler\n             key_scheduler.v\n             key_scheduler.sv\n             obj_dir/key_scheduler\n             obj_dir/key_scheduler.v\n             obj_dir/key_scheduler.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module key_scheduler_tb ();
    
    reg clk, rst;
    reg [79:0] i_ks_oldkey;
    reg [4:0] round_counter = 5'b00001;
    wire [79:0] o_ks_newkey;

    key_scheduler ks(.clk(clk), .rst(rst), .round_counter(round_counter), .i_ks_oldkey(i_ks_oldkey), .o_ks_newkey(o_ks_newkey));

    always begin
        #5 clk = ~clk;
    end

    initial begin
        clk = 0;
        i_ks_oldkey = 80'h00000000000000000000;

        rst = 0;
        #20;
        rst = 1;


    end

endmodule
module key_scheduler_tb ();

    
    reg clk, rst;
    reg [79:0] i_ks_oldkey;
    reg [4:0] round_counter = 5'b00001;
    wire [79:0] o_ks_newkey;

    key_scheduler ks(.clk(clk), .rst(rst), .round_counter(round_counter), .i_ks_oldkey(i_ks_oldkey), .o_ks_newkey(o_ks_newkey));

    always begin
        #5 clk = ~clk;
    end

    initial begin
        clk = 0;
        i_ks_oldkey = 80'h00000000000000000000;

        rst = 0;
        #20;
        rst = 1;


    end

endmodule