data/full_repos/permissive/433389019/MEM.v
1: b'%Error: data/full_repos/permissive/433389019/MEM.v:1: Cannot find include file: lib/defines.vh\n`include "lib/defines.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/433389019,data/full_repos/permissive/433389019/lib/defines.vh\n             data/full_repos/permissive/433389019,data/full_repos/permissive/433389019/lib/defines.vh.v\n             data/full_repos/permissive/433389019,data/full_repos/permissive/433389019/lib/defines.vh.sv\n             lib/defines.vh\n             lib/defines.vh.v\n             lib/defines.vh.sv\n             obj_dir/lib/defines.vh\n             obj_dir/lib/defines.vh.v\n             obj_dir/lib/defines.vh.sv\n%Error: data/full_repos/permissive/433389019/MEM.v:6: Define or directive not defined: \'`StallBus\'\n    input wire [`StallBus-1:0] stall,\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/433389019/MEM.v:8: Define or directive not defined: \'`EX_TO_MEM_WD\'\n    input wire [`EX_TO_MEM_WD-1:0] ex_to_mem_bus,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/433389019/MEM.v:10: Define or directive not defined: \'`MEM_TO_ID_WD\'\n    output wire [`MEM_TO_ID_WD-1:0]  mem_to_id_bus,\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/433389019/MEM.v:11: Define or directive not defined: \'`MEM_TO_WB_WD\'\n    output wire [`MEM_TO_WB_WD-1:0] mem_to_wb_bus\n                 ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/433389019/MEM.v:14: Define or directive not defined: \'`EX_TO_MEM_WD\'\n    reg [`EX_TO_MEM_WD-1:0] ex_to_mem_bus_r;\n         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/433389019/MEM.v:18: Define or directive not defined: \'`EX_TO_MEM_WD\'\n            ex_to_mem_bus_r <= `EX_TO_MEM_WD\'b0;\n                               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/433389019/MEM.v:23: Define or directive not defined: \'`Stop\'\n        else if (stall[3]==`Stop && stall[4]==`NoStop) begin\n                           ^~~~~\n%Error: data/full_repos/permissive/433389019/MEM.v:23: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n        else if (stall[3]==`Stop && stall[4]==`NoStop) begin\n                                 ^~\n%Error: data/full_repos/permissive/433389019/MEM.v:23: Define or directive not defined: \'`NoStop\'\n        else if (stall[3]==`Stop && stall[4]==`NoStop) begin\n                                              ^~~~~~~\n%Error: data/full_repos/permissive/433389019/MEM.v:24: Define or directive not defined: \'`EX_TO_MEM_WD\'\n            ex_to_mem_bus_r <= `EX_TO_MEM_WD\'b0;\n                               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/433389019/MEM.v:26: Define or directive not defined: \'`NoStop\'\n        else if (stall[3]==`NoStop) begin\n                           ^~~~~~~\n%Error: Exiting due to 12 error(s)\n'
module MEM(
    input wire clk,
    input wire rst,

    input wire [`StallBus-1:0] stall,

    input wire [`EX_TO_MEM_WD-1:0] ex_to_mem_bus,
    input wire [31:0] data_sram_rdata,
    output wire [`MEM_TO_ID_WD-1:0]  mem_to_id_bus,
    output wire [`MEM_TO_WB_WD-1:0] mem_to_wb_bus
);

    reg [`EX_TO_MEM_WD-1:0] ex_to_mem_bus_r;

    always @ (posedge clk) begin
        if (rst) begin
            ex_to_mem_bus_r <= `EX_TO_MEM_WD'b0;
        end



        else if (stall[3]==`Stop && stall[4]==`NoStop) begin
            ex_to_mem_bus_r <= `EX_TO_MEM_WD'b0;
        end
        else if (stall[3]==`NoStop) begin
            ex_to_mem_bus_r <= ex_to_mem_bus;
        end
    end

    wire [31:0] mem_pc;
    wire data_ram_en;
    wire [3:0] data_ram_wen;
    wire [3:0] data_ram_readen;
    wire sel_rf_res;
    wire rf_we;
    wire [4:0] rf_waddr;
    wire [31:0] rf_wdata;
    wire [31:0] ex_result;
    wire [31:0] mem_result;
    wire w_hi_we;       
    wire [31:0] w_hi_i;        
    wire w_lo_we;       
    wire [31:0] w_lo_i;  

    assign {
        data_ram_readen,
        w_hi_we,
        w_hi_i,
        w_lo_we,
        w_lo_i,
        mem_pc,
        data_ram_en,
        data_ram_wen,
        sel_rf_res,
        rf_we,
        rf_waddr,
        ex_result
    } =  ex_to_mem_bus_r;



    assign mem_result = data_sram_rdata;




    assign rf_wdata =     (data_ram_readen==4'b1111 && data_ram_en==1'b1) ? data_sram_rdata 
                        : (data_ram_readen==4'b0001 && data_ram_en==1'b1 && ex_result[1:0]==2'b00) ?({{24{data_sram_rdata[7]}},data_sram_rdata[7:0]})
                        : (data_ram_readen==4'b0001 && data_ram_en==1'b1 && ex_result[1:0]==2'b01) ?({{24{data_sram_rdata[15]}},data_sram_rdata[15:8]})
                        : (data_ram_readen==4'b0001 && data_ram_en==1'b1 && ex_result[1:0]==2'b10) ?({{24{data_sram_rdata[23]}},data_sram_rdata[23:16]})
                        : (data_ram_readen==4'b0001 && data_ram_en==1'b1 && ex_result[1:0]==2'b11) ?({{24{data_sram_rdata[31]}},data_sram_rdata[31:24]})
                        : (data_ram_readen==4'b0010 && data_ram_en==1'b1 && ex_result[1:0]==2'b00) ?({24'b0,data_sram_rdata[7:0]})
                        : (data_ram_readen==4'b0010 && data_ram_en==1'b1 && ex_result[1:0]==2'b01) ?({24'b0,data_sram_rdata[15:8]})
                        : (data_ram_readen==4'b0010 && data_ram_en==1'b1 && ex_result[1:0]==2'b10) ?({24'b0,data_sram_rdata[23:16]})
                        : (data_ram_readen==4'b0010 && data_ram_en==1'b1 && ex_result[1:0]==2'b11) ?({24'b0,data_sram_rdata[31:24]})
                        : (data_ram_readen==4'b0011 && data_ram_en==1'b1 && ex_result[1:0]==2'b00) ?({{16{data_sram_rdata[15]}},data_sram_rdata[15:0]})
                        : (data_ram_readen==4'b0011 && data_ram_en==1'b1 && ex_result[1:0]==2'b10) ?({{16{data_sram_rdata[31]}},data_sram_rdata[31:16]})
                        : (data_ram_readen==4'b0100 && data_ram_en==1'b1 && ex_result[1:0]==2'b00) ?({16'b0,data_sram_rdata[15:0]})
                        : (data_ram_readen==4'b0100 && data_ram_en==1'b1 && ex_result[1:0]==2'b10) ?({16'b0,data_sram_rdata[31:16]})
                        : ex_result;

    assign mem_to_wb_bus = {
        w_hi_we,
        w_hi_i,
        w_lo_we,
        w_lo_i,
        mem_pc,
        rf_we,
        rf_waddr,
        rf_wdata
    };
    assign mem_to_id_bus = {
        w_hi_we,
        w_hi_i,
        w_lo_we,
        w_lo_i,
        rf_we,
        rf_waddr,
        rf_wdata
    };



endmodule
module MEM(
    input wire clk,
    input wire rst,

    input wire [`StallBus-1:0] stall,

    input wire [`EX_TO_MEM_WD-1:0] ex_to_mem_bus,
    input wire [31:0] data_sram_rdata,
    output wire [`MEM_TO_ID_WD-1:0]  mem_to_id_bus,
    output wire [`MEM_TO_WB_WD-1:0] mem_to_wb_bus
);


    reg [`EX_TO_MEM_WD-1:0] ex_to_mem_bus_r;

    always @ (posedge clk) begin
        if (rst) begin
            ex_to_mem_bus_r <= `EX_TO_MEM_WD'b0;
        end



        else if (stall[3]==`Stop && stall[4]==`NoStop) begin
            ex_to_mem_bus_r <= `EX_TO_MEM_WD'b0;
        end
        else if (stall[3]==`NoStop) begin
            ex_to_mem_bus_r <= ex_to_mem_bus;
        end
    end

    wire [31:0] mem_pc;
    wire data_ram_en;
    wire [3:0] data_ram_wen;
    wire [3:0] data_ram_readen;
    wire sel_rf_res;
    wire rf_we;
    wire [4:0] rf_waddr;
    wire [31:0] rf_wdata;
    wire [31:0] ex_result;
    wire [31:0] mem_result;
    wire w_hi_we;       
    wire [31:0] w_hi_i;        
    wire w_lo_we;       
    wire [31:0] w_lo_i;  

    assign {
        data_ram_readen,
        w_hi_we,
        w_hi_i,
        w_lo_we,
        w_lo_i,
        mem_pc,
        data_ram_en,
        data_ram_wen,
        sel_rf_res,
        rf_we,
        rf_waddr,
        ex_result
    } =  ex_to_mem_bus_r;



    assign mem_result = data_sram_rdata;




    assign rf_wdata =     (data_ram_readen==4'b1111 && data_ram_en==1'b1) ? data_sram_rdata 
                        : (data_ram_readen==4'b0001 && data_ram_en==1'b1 && ex_result[1:0]==2'b00) ?({{24{data_sram_rdata[7]}},data_sram_rdata[7:0]})
                        : (data_ram_readen==4'b0001 && data_ram_en==1'b1 && ex_result[1:0]==2'b01) ?({{24{data_sram_rdata[15]}},data_sram_rdata[15:8]})
                        : (data_ram_readen==4'b0001 && data_ram_en==1'b1 && ex_result[1:0]==2'b10) ?({{24{data_sram_rdata[23]}},data_sram_rdata[23:16]})
                        : (data_ram_readen==4'b0001 && data_ram_en==1'b1 && ex_result[1:0]==2'b11) ?({{24{data_sram_rdata[31]}},data_sram_rdata[31:24]})
                        : (data_ram_readen==4'b0010 && data_ram_en==1'b1 && ex_result[1:0]==2'b00) ?({24'b0,data_sram_rdata[7:0]})
                        : (data_ram_readen==4'b0010 && data_ram_en==1'b1 && ex_result[1:0]==2'b01) ?({24'b0,data_sram_rdata[15:8]})
                        : (data_ram_readen==4'b0010 && data_ram_en==1'b1 && ex_result[1:0]==2'b10) ?({24'b0,data_sram_rdata[23:16]})
                        : (data_ram_readen==4'b0010 && data_ram_en==1'b1 && ex_result[1:0]==2'b11) ?({24'b0,data_sram_rdata[31:24]})
                        : (data_ram_readen==4'b0011 && data_ram_en==1'b1 && ex_result[1:0]==2'b00) ?({{16{data_sram_rdata[15]}},data_sram_rdata[15:0]})
                        : (data_ram_readen==4'b0011 && data_ram_en==1'b1 && ex_result[1:0]==2'b10) ?({{16{data_sram_rdata[31]}},data_sram_rdata[31:16]})
                        : (data_ram_readen==4'b0100 && data_ram_en==1'b1 && ex_result[1:0]==2'b00) ?({16'b0,data_sram_rdata[15:0]})
                        : (data_ram_readen==4'b0100 && data_ram_en==1'b1 && ex_result[1:0]==2'b10) ?({16'b0,data_sram_rdata[31:16]})
                        : ex_result;

    assign mem_to_wb_bus = {
        w_hi_we,
        w_hi_i,
        w_lo_we,
        w_lo_i,
        mem_pc,
        rf_we,
        rf_waddr,
        rf_wdata
    };
    assign mem_to_id_bus = {
        w_hi_we,
        w_hi_i,
        w_lo_we,
        w_lo_i,
        rf_we,
        rf_waddr,
        rf_wdata
    };



endmodule