data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_r_dcm.v
data/verilator_xmls/0f832701-6dc1-498d-8b23-dfc4751f6f20.xml
module bw_r_dcm(

   row_hit, rd_data0, rd_data1, rd_data2, rd_data3, so_0, so_1, 

   cam_en, inv_mask0, inv_mask1, inv_mask2, inv_mask3, si_0, se_0, 
   si_1, se_1, sehold_0, sehold_1, rclk,  rd_en, rw_addr0, 
   rw_addr1, rw_addr2, rw_addr3, rst_l_0, rst_l_1, rst_warm_0, 
   rst_warm_1, wr_en, rst_tri_en_0, rst_tri_en_1, wr_data0, wr_data1, 
   wr_data2, wr_data3
   );

output	[31:0]	row_hit;

output [31:0]         rd_data0;
output [31:0]         rd_data1;
output [31:0]         rd_data2;
output [31:0]         rd_data3;

input   [3:0]         cam_en;

input [7:0]           inv_mask0;
input [7:0]           inv_mask1;
input [7:0]           inv_mask2;
input [7:0]           inv_mask3;

input		      si_0, se_0;
output		      so_0;
input		      si_1, se_1;
output		      so_1;
input		      sehold_0;
input		      sehold_1;

input                 rclk;

input  [3:0]          rd_en ;

input [5:0]           rw_addr0;
input [5:0]           rw_addr1;
input [5:0]           rw_addr2;
input [5:0]           rw_addr3;

input                 rst_l_0;
input                 rst_l_1;
input		      rst_warm_0;
input		      rst_warm_1;

input   [3:0]         wr_en;
input		      rst_tri_en_0;
input		      rst_tri_en_1;

input [32:0]          wr_data0;
input [32:0]          wr_data1;
input [32:0]          wr_data2;
input [32:0]          wr_data3;


wire	[31:0]	bank1_hit;
wire	[31:0]	bank0_hit;



      dcm_panel_pair	panel_pair0(
                                  .so   (),
                                  .si   (),
                                  .se   (se_0),


                                  .bank_hit(bank0_hit[31:0]),
                                  .rd_data0(rd_data0[31:0]),
                                  .rd_data1(rd_data1[31:0]),

                                  .cam_en(cam_en[1:0]),
                                  .inv_mask0(inv_mask0[7:0]),
                                  .inv_mask1(inv_mask1[7:0]),
                                  .rclk (rclk),
                                  .rd_en(rd_en[1:0]),
                                  .rst_l(rst_l_0),
                                  .rst_tri_en(rst_tri_en_0),
                                  .rst_warm(rst_warm_0),
                                  .rw_addr0(rw_addr0[5:0]),
                                  .rw_addr1(rw_addr1[5:0]),
                                  .sehold(sehold_0),
                                  .wr_data0(wr_data0[32:0]),
                                  .wr_data1(wr_data1[32:0]),
                                  .wr_en(wr_en[1:0]));
				
	assign	 row_hit =  bank1_hit | bank0_hit ;



      dcm_panel_pair    panel_pair1(
                                  .so   (),
                                  .si   (),
                                  .se   (se_1),


                                    .bank_hit(bank1_hit[31:0]),
                                    .rd_data0(rd_data2[31:0]),
                                    .rd_data1(rd_data3[31:0]),

                                    .cam_en(cam_en[3:2]),
                                    .inv_mask0(inv_mask2[7:0]),
                                    .inv_mask1(inv_mask3[7:0]),
                                    .rclk(rclk),
                                    .rd_en(rd_en[3:2]),
                                    .rst_l(rst_l_1),
                                    .rst_tri_en(rst_tri_en_1),
                                    .rst_warm(rst_warm_1),
                                    .rw_addr0(rw_addr2[5:0]),
                                    .rw_addr1(rw_addr3[5:0]),
                                    .sehold(sehold_1),
                                    .wr_data0(wr_data2[32:0]),
                                    .wr_data1(wr_data3[32:0]),
                                    .wr_en(wr_en[3:2]));


endmodule
module bw_r_dcm(

   row_hit, rd_data0, rd_data1, rd_data2, rd_data3, so_0, so_1, 

   cam_en, inv_mask0, inv_mask1, inv_mask2, inv_mask3, si_0, se_0, 
   si_1, se_1, sehold_0, sehold_1, rclk,  rd_en, rw_addr0, 
   rw_addr1, rw_addr2, rw_addr3, rst_l_0, rst_l_1, rst_warm_0, 
   rst_warm_1, wr_en, rst_tri_en_0, rst_tri_en_1, wr_data0, wr_data1, 
   wr_data2, wr_data3
   );


output	[31:0]	row_hit;

output [31:0]         rd_data0;
output [31:0]         rd_data1;
output [31:0]         rd_data2;
output [31:0]         rd_data3;

input   [3:0]         cam_en;

input [7:0]           inv_mask0;
input [7:0]           inv_mask1;
input [7:0]           inv_mask2;
input [7:0]           inv_mask3;

input		      si_0, se_0;
output		      so_0;
input		      si_1, se_1;
output		      so_1;
input		      sehold_0;
input		      sehold_1;

input                 rclk;

input  [3:0]          rd_en ;

input [5:0]           rw_addr0;
input [5:0]           rw_addr1;
input [5:0]           rw_addr2;
input [5:0]           rw_addr3;

input                 rst_l_0;
input                 rst_l_1;
input		      rst_warm_0;
input		      rst_warm_1;

input   [3:0]         wr_en;
input		      rst_tri_en_0;
input		      rst_tri_en_1;

input [32:0]          wr_data0;
input [32:0]          wr_data1;
input [32:0]          wr_data2;
input [32:0]          wr_data3;


wire	[31:0]	bank1_hit;
wire	[31:0]	bank0_hit;



      dcm_panel_pair	panel_pair0(
                                  .so   (),
                                  .si   (),
                                  .se   (se_0),


                                  .bank_hit(bank0_hit[31:0]),
                                  .rd_data0(rd_data0[31:0]),
                                  .rd_data1(rd_data1[31:0]),

                                  .cam_en(cam_en[1:0]),
                                  .inv_mask0(inv_mask0[7:0]),
                                  .inv_mask1(inv_mask1[7:0]),
                                  .rclk (rclk),
                                  .rd_en(rd_en[1:0]),
                                  .rst_l(rst_l_0),
                                  .rst_tri_en(rst_tri_en_0),
                                  .rst_warm(rst_warm_0),
                                  .rw_addr0(rw_addr0[5:0]),
                                  .rw_addr1(rw_addr1[5:0]),
                                  .sehold(sehold_0),
                                  .wr_data0(wr_data0[32:0]),
                                  .wr_data1(wr_data1[32:0]),
                                  .wr_en(wr_en[1:0]));
				
	assign	 row_hit =  bank1_hit | bank0_hit ;



      dcm_panel_pair    panel_pair1(
                                  .so   (),
                                  .si   (),
                                  .se   (se_1),


                                    .bank_hit(bank1_hit[31:0]),
                                    .rd_data0(rd_data2[31:0]),
                                    .rd_data1(rd_data3[31:0]),

                                    .cam_en(cam_en[3:2]),
                                    .inv_mask0(inv_mask2[7:0]),
                                    .inv_mask1(inv_mask3[7:0]),
                                    .rclk(rclk),
                                    .rd_en(rd_en[3:2]),
                                    .rst_l(rst_l_1),
                                    .rst_tri_en(rst_tri_en_1),
                                    .rst_warm(rst_warm_1),
                                    .rw_addr0(rw_addr2[5:0]),
                                    .rw_addr1(rw_addr3[5:0]),
                                    .sehold(sehold_1),
                                    .wr_data0(wr_data2[32:0]),
                                    .wr_data1(wr_data3[32:0]),
                                    .wr_en(wr_en[3:2]));


endmodule