data/full_repos/permissive/471933052/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/471933052/verilog/rtl/user_proj_example.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/471933052/verilog/rtl/user_proj_example.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/471933052/verilog/rtl/user_proj_example.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/471933052/verilog/rtl/user_proj_example.v:311: syntax error, unexpected ')', expecting '['\nmodule delay_element #(parameter REG_WIDTH = 8) (clk,a_n_1,b_n_1,a_n,b_n,);\n                                                                         ^\n%Error: data/full_repos/permissive/471933052/verilog/rtl/user_proj_example.v:317: syntax error, unexpected output\n    output reg [REG_WIDTH-1:0] b_n;  \n    ^~~~~~\n%Error: data/full_repos/permissive/471933052/verilog/rtl/user_proj_example.v:319: syntax error, unexpected always\n    always @(posedge clk) begin\n    ^~~~~~\n%Error: Exiting due to 6 error(s)\n"
module user_proj_example #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,


    output [2:0] irq
);
    


	wire clk;
	wire [7:0] in_data;
	wire [7:0] out1,out2,out3,out4,out5;
	
	assign clk = wb_clk_i;
	assign in_data = la_data_in[7:0];
	assign la_data_out[15:8] = out1;
	assign la_data_out[23:16] = out2;
	assign la_data_out[31:24] = out3;
	assign la_data_out[39:32] = out4;
	assign la_data_out[47:40] = out5;
    	main uut(clk,in_data,out1,out2,out3,out4,out5);
endmodule
module user_proj_example #(
    parameter BITS = 32
)(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,


    input  [127:0] la_data_in,
    output [127:0] la_data_out,
    input  [127:0] la_oenb,


    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,


    output [2:0] irq
);

    


	wire clk;
	wire [7:0] in_data;
	wire [7:0] out1,out2,out3,out4,out5;
	
	assign clk = wb_clk_i;
	assign in_data = la_data_in[7:0];
	assign la_data_out[15:8] = out1;
	assign la_data_out[23:16] = out2;
	assign la_data_out[31:24] = out3;
	assign la_data_out[39:32] = out4;
	assign la_data_out[47:40] = out5;
    	main uut(clk,in_data,out1,out2,out3,out4,out5);
endmodule