data/full_repos/permissive/426864978/lab3/task1/task1.sv
1: b"%Error: data/full_repos/permissive/426864978/lab3/task1/task1.sv:19: Cannot find file containing module: 'init'\n    init i(.clk(CLOCK_50),\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/426864978/lab3/task1,data/full_repos/permissive/426864978/init\n             data/full_repos/permissive/426864978/lab3/task1,data/full_repos/permissive/426864978/init.v\n             data/full_repos/permissive/426864978/lab3/task1,data/full_repos/permissive/426864978/init.sv\n             init\n             init.v\n             init.sv\n             obj_dir/init\n             obj_dir/init.v\n             obj_dir/init.sv\n%Error: data/full_repos/permissive/426864978/lab3/task1/task1.sv:27: Cannot find file containing module: 's_mem'\n    s_mem s(.address(addr),\n    ^~~~~\n%Error: Exiting due to 2 error(s)\n"
module task1(input logic CLOCK_50, input logic [3:0] KEY, input logic [9:0] SW,
             output logic [6:0] HEX0, output logic [6:0] HEX1, output logic [6:0] HEX2,
             output logic [6:0] HEX3, output logic [6:0] HEX4, output logic [6:0] HEX5,
             output logic [9:0] LEDR);

    logic rst_n, en, rdy, wren, enabled;
    logic [7:0] addr, wrdata, q;

    assign rst_n = KEY[3];
    assign en = rdy & ~enabled;

    always @(posedge CLOCK_50) begin
       if (rst_n == 1'b0)
              enabled <= 1'b0;
       if (en == 1'b1)
              enabled <= 1'b1;
    end

    init i(.clk(CLOCK_50),
           .rst_n(rst_n),
           .en(en),
           .rdy(rdy),
           .addr(addr),
           .wrdata(wrdata),
           .wren(wren));

    s_mem s(.address(addr),
            .clock(CLOCK_50),
            .data(wrdata),
            .wren(wren),
            .q(q));

endmodule
module task1(input logic CLOCK_50, input logic [3:0] KEY, input logic [9:0] SW,
             output logic [6:0] HEX0, output logic [6:0] HEX1, output logic [6:0] HEX2,
             output logic [6:0] HEX3, output logic [6:0] HEX4, output logic [6:0] HEX5,
             output logic [9:0] LEDR);


    logic rst_n, en, rdy, wren, enabled;
    logic [7:0] addr, wrdata, q;

    assign rst_n = KEY[3];
    assign en = rdy & ~enabled;

    always @(posedge CLOCK_50) begin
       if (rst_n == 1'b0)
              enabled <= 1'b0;
       if (en == 1'b1)
              enabled <= 1'b1;
    end

    init i(.clk(CLOCK_50),
           .rst_n(rst_n),
           .en(en),
           .rdy(rdy),
           .addr(addr),
           .wrdata(wrdata),
           .wren(wren));

    s_mem s(.address(addr),
            .clock(CLOCK_50),
            .data(wrdata),
            .wren(wren),
            .q(q));

endmodule