data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/MICROBENCHMARKS/UNSUPPORTED/bm_function_2.v
1: b'%Warning-WIDTH: data/full_repos/permissive/49670587/vtr/ODIN_II/REGRESSION_TESTS/BENCHMARKS/MICROBENCHMARKS/UNSUPPORTED/bm_function_2.v:56: Operator AND expects 2 bits on the LHS, but LHS\'s VARREF \'temp1\' generates 1 bits.\n                                                                                                                                          : ... In instance bm_function_2\n out0 <= temp1 & temp2;\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module 	bm_function_2(clock, 
		reset_n, 
		a, 
		b,
		c, 
		d, 
		out0,
		out1);


input	clock;
input 	reset_n;

input [`BITS-1:0] a;
input [`BITS-1:0] b;
input c;
input d;

output [`BITS-1:0] out0;
output  out1;

reg [`BITS-1:0]    out0;
wire     out1;

reg temp1;
reg [`BITS-1:0]temp2;


function simple_func;
	input [`BITS-1:0] in1;
	input [`BITS-1:0] in2;
	input in3;
	input in4;

	simple_func <= in1[0] & in2[0] | in3 ^ in4;
endfunction

function [`BITS-1:0] simple_func_2;
	input in3;
	input in4;
begin
	simple_func_2[1] <= in3 & in4;
	simple_func_2[0] <= in3 | in4;
end
endfunction

assign out1 = simple_func(a, b, c, d) & c;

always @(posedge clock or negedge reset_n)
begin
	temp1 <= simple_func(a, b, c, d);
	temp2 <= simple_func_2(c, d);
	out0 <= temp1 & temp2;
end

endmodule
module 	bm_function_2(clock, 
		reset_n, 
		a, 
		b,
		c, 
		d, 
		out0,
		out1);



input	clock;
input 	reset_n;

input [`BITS-1:0] a;
input [`BITS-1:0] b;
input c;
input d;

output [`BITS-1:0] out0;
output  out1;

reg [`BITS-1:0]    out0;
wire     out1;

reg temp1;
reg [`BITS-1:0]temp2;


function simple_func;
	input [`BITS-1:0] in1;
	input [`BITS-1:0] in2;
	input in3;
	input in4;

	simple_func <= in1[0] & in2[0] | in3 ^ in4;
endfunction

function [`BITS-1:0] simple_func_2;
	input in3;
	input in4;
begin
	simple_func_2[1] <= in3 & in4;
	simple_func_2[0] <= in3 | in4;
end
endfunction

assign out1 = simple_func(a, b, c, d) & c;

always @(posedge clock or negedge reset_n)
begin
	temp1 <= simple_func(a, b, c, d);
	temp2 <= simple_func_2(c, d);
	out0 <= temp1 & temp2;
end

endmodule