data/full_repos/permissive/493851698/verilog/rtl/macro_15.v
1: b"%Error: data/full_repos/permissive/493851698/verilog/rtl/macro_15.v:42: Define or directive not defined: '`MPRJ_IO_PADS'\n   input  wire [`MPRJ_IO_PADS-1:0] io_in,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493851698/verilog/rtl/macro_15.v:43: Define or directive not defined: '`MPRJ_IO_PADS'\n   output wire [`MPRJ_IO_PADS-1:0] io_out,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493851698/verilog/rtl/macro_15.v:44: Define or directive not defined: '`MPRJ_IO_PADS'\n   output wire [`MPRJ_IO_PADS-1:0] io_oeb,\n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493851698/verilog/rtl/macro_15.v:54: Define or directive not defined: '`MPRJ_IO_PADS'\n   inout [`MPRJ_IO_PADS-10:0] analog_io,\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493851698/verilog/rtl/macro_15.v:79: Define or directive not defined: '`MPRJ_IO_PADS'\n wire [`MPRJ_IO_PADS-1:0]    buf_io_out;    \n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493851698/verilog/rtl/macro_15.v:80: Define or directive not defined: '`MPRJ_IO_PADS'\n wire [`MPRJ_IO_PADS-1:0]    buf_io_oeb;    \n       ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493851698/verilog/rtl/macro_15.v:97: Define or directive not defined: '`MPRJ_IO_PADS'\n         assign io_oeb       = active ? buf_io_oeb       : {`MPRJ_IO_PADS{1'b0}};\n                                                            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493851698/verilog/rtl/macro_15.v:98: Define or directive not defined: '`MPRJ_IO_PADS'\n  assign io_out       = active ? buf_io_out       : {`MPRJ_IO_PADS{1'b0}};\n                                                     ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/493851698/verilog/rtl/macro_15.v:103: Define or directive not defined: '`MPRJ_IO_PADS'\n  assign buf_io_oeb = {`MPRJ_IO_PADS{1'b0}};  \n                       ^~~~~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n"
module macro_15  (
 `ifdef USE_POWER_PINS
     inout vdda1,
     inout vdda2,
     inout vssa1,
     inout vssa2,
     inout vccd1,
     inout vccd2,
     inout vssd1,
     inout vssd2,
 `endif		


		 input wb_clk_i,
		 input wb_rst_i,
		 input wbs_stb_i,
		 input wbs_cyc_i,
		 input wbs_we_i,
		 input [3:0] wbs_sel_i,
		 input [31:0] wbs_dat_i,
		 input [31:0] wbs_adr_i,
		 output wbs_ack_o,
		 output [31:0] wbs_dat_o,
		

	`ifdef USE_LA
		 input  wire [127:0] la_data_in,
		 output wire [127:0] la_data_out,
		 input  wire [127:0] la_oenb,
	 `endif	

	`ifdef USE_IO
		 input  wire [`MPRJ_IO_PADS-1:0] io_in,
		 output wire [`MPRJ_IO_PADS-1:0] io_out,
		 output wire [`MPRJ_IO_PADS-1:0] io_oeb,
	 `endif	








		 inout [`MPRJ_IO_PADS-10:0] analog_io,
		

		 input  wire user_clock2,
		

		output wire [2:0] user_irq,

		input wire active
		 );





	reg [3:0] A0, B0, A1, B1;
	reg [1:0] ALU_Sel1, ALU_Sel2;
	wire [3:0] ALU_Out1,ALU_Out2;
	wire CarryOut1,CarryOut2;
	wire [3:0] x;
	wire y;
	wire clk;
	wire [31:0] la1_data_out;
	assign la1_data_out = la_data_out[63:32];
	wire [31:0]                 buf_la1_data_out;
	wire [`MPRJ_IO_PADS-1:0]    buf_io_out;
	wire [`MPRJ_IO_PADS-1:0]    buf_io_oeb;

 `ifdef FORMAL
	 `ifdef USE_LA 
	 assign la1_data_out = active ? buf_la1_data_out  : 32'b0;
 	 `endif
	 `ifdef USE_IO
	 assign io_oeb       = active ? buf_io_oeb       : {`MPRJ_IO_PADS{1'b0}};
	 assign io_out       = active ? buf_io_out       : {`MPRJ_IO_PADS{1'b0}};
         `endif
	 `include "properties.v"
 
 `else
	 `ifdef USE_LA
	 assign la1_data_out = active ? buf_la1_data_out  : 32'bz;
         `endif
	 `ifdef USE_IO
         assign io_oeb       = active ? buf_io_oeb       : {`MPRJ_IO_PADS{1'b0}};
	 assign io_out       = active ? buf_io_out       : {`MPRJ_IO_PADS{1'b0}};
 	 `endif

 `endif

  assign buf_io_oeb = {`MPRJ_IO_PADS{1'b0}};


 
 alu_xor_4 u_alu_xor_4(
`ifdef USE_POWER_PINS
 .vccd1(vccd1),
 .vssd1(vssd1),
`endif
	.clk(wb_clk_i),
	.A0(io_in[21:18]),
	.B0(io_in[25:22]),
	.A1(io_in[29:26]),
	.B1(io_in[33:30]),
	.ALU_Sel1(io_in[35:34]),
	.ALU_Sel2(io_in[37:36]),
	.ALU_Out1(buf_io_out[17:14]),
	.ALU_Out2(buf_io_out[13:10]),
	.CarryOut1(buf_io_out[5]),
	.CarryOut2(buf_io_out[4]),
	.x(buf_io_out[9:6]),
	.y(buf_io_out[0])
);
 endmodule
module macro_15  (
 `ifdef USE_POWER_PINS
     inout vdda1,
     inout vdda2,
     inout vssa1,
     inout vssa2,
     inout vccd1,
     inout vccd2,
     inout vssd1,
     inout vssd2,
 `endif		


		 input wb_clk_i,
		 input wb_rst_i,
		 input wbs_stb_i,
		 input wbs_cyc_i,
		 input wbs_we_i,
		 input [3:0] wbs_sel_i,
		 input [31:0] wbs_dat_i,
		 input [31:0] wbs_adr_i,
		 output wbs_ack_o,
		 output [31:0] wbs_dat_o,
		

	`ifdef USE_LA
		 input  wire [127:0] la_data_in,
		 output wire [127:0] la_data_out,
		 input  wire [127:0] la_oenb,
	 `endif	

	`ifdef USE_IO
		 input  wire [`MPRJ_IO_PADS-1:0] io_in,
		 output wire [`MPRJ_IO_PADS-1:0] io_out,
		 output wire [`MPRJ_IO_PADS-1:0] io_oeb,
	 `endif	








		 inout [`MPRJ_IO_PADS-10:0] analog_io,
		

		 input  wire user_clock2,
		

		output wire [2:0] user_irq,

		input wire active
		 );






	reg [3:0] A0, B0, A1, B1;
	reg [1:0] ALU_Sel1, ALU_Sel2;
	wire [3:0] ALU_Out1,ALU_Out2;
	wire CarryOut1,CarryOut2;
	wire [3:0] x;
	wire y;
	wire clk;
	wire [31:0] la1_data_out;
	assign la1_data_out = la_data_out[63:32];
	wire [31:0]                 buf_la1_data_out;
	wire [`MPRJ_IO_PADS-1:0]    buf_io_out;
	wire [`MPRJ_IO_PADS-1:0]    buf_io_oeb;

 `ifdef FORMAL
	 `ifdef USE_LA 
	 assign la1_data_out = active ? buf_la1_data_out  : 32'b0;
 	 `endif
	 `ifdef USE_IO
	 assign io_oeb       = active ? buf_io_oeb       : {`MPRJ_IO_PADS{1'b0}};
	 assign io_out       = active ? buf_io_out       : {`MPRJ_IO_PADS{1'b0}};
         `endif
	 `include "properties.v"
 
 `else
	 `ifdef USE_LA
	 assign la1_data_out = active ? buf_la1_data_out  : 32'bz;
         `endif
	 `ifdef USE_IO
         assign io_oeb       = active ? buf_io_oeb       : {`MPRJ_IO_PADS{1'b0}};
	 assign io_out       = active ? buf_io_out       : {`MPRJ_IO_PADS{1'b0}};
 	 `endif

 `endif

  assign buf_io_oeb = {`MPRJ_IO_PADS{1'b0}};


 
 alu_xor_4 u_alu_xor_4(
`ifdef USE_POWER_PINS
 .vccd1(vccd1),
 .vssd1(vssd1),
`endif
	.clk(wb_clk_i),
	.A0(io_in[21:18]),
	.B0(io_in[25:22]),
	.A1(io_in[29:26]),
	.B1(io_in[33:30]),
	.ALU_Sel1(io_in[35:34]),
	.ALU_Sel2(io_in[37:36]),
	.ALU_Out1(buf_io_out[17:14]),
	.ALU_Out2(buf_io_out[13:10]),
	.CarryOut1(buf_io_out[5]),
	.CarryOut2(buf_io_out[4]),
	.x(buf_io_out[9:6]),
	.y(buf_io_out[0])
);
 endmodule