data/full_repos/permissive/446997925/hw3/or.v
data/verilator_xmls/91d6b0c7-80e9-4fd8-b698-4e241996a499.xml
module or_2(out, a, b);
input [1:0] a, b;
output [1:0] out;

or f(out[0], a[0], b[0]),
    s(out[1], a[1], b[1]);
endmodule
module or_2(out, a, b);

input [1:0] a, b;
output [1:0] out;

or f(out[0], a[0], b[0]),
    s(out[1], a[1], b[1]);
endmodule