data/full_repos/permissive/408212214/glitch_filter.v
data/verilator_xmls/9a578999-403b-4d84-96b8-c198c54e7d77.xml
module glitch_filter(
	input sys_clk,
	input line_in,
	output line_out
);

reg [3:0] sample_counter;
reg filtered_output;

initial begin
	filtered_output = 1;
	sample_counter = 0;
end

always @(posedge sys_clk) begin
	if(filtered_output == line_in) begin
		sample_counter <= 0;
	end else begin
		sample_counter <= sample_counter + 1'b1;
		if(sample_counter == 5) begin
			filtered_output <= !filtered_output;
			sample_counter <= 0;
		end
	end
end

assign line_out = filtered_output;

endmodule
module glitch_filter(
	input sys_clk,
	input line_in,
	output line_out
);


reg [3:0] sample_counter;
reg filtered_output;

initial begin
	filtered_output = 1;
	sample_counter = 0;
end

always @(posedge sys_clk) begin
	if(filtered_output == line_in) begin
		sample_counter <= 0;
	end else begin
		sample_counter <= sample_counter + 1'b1;
		if(sample_counter == 5) begin
			filtered_output <= !filtered_output;
			sample_counter <= 0;
		end
	end
end

assign line_out = filtered_output;

endmodule