data/full_repos/permissive/494696040/Register_File.v
data/verilator_xmls/ea1c9cb5-7de9-49b9-8039-8da78e9da829.xml
module Register_File(
     input [4:0] Read_Register_1,
     input [4:0] Read_Register_2,
     input [4:0] Write_Register,
     input [31:0] Write_Data,
     input RegWrite,
     input CLK,
     output reg [31:0] Read_Data_1,
     output reg [31:0] Read_Data_2
    );


    reg [31:0] Registers[31:0];
    
    

    always @(Read_Register_1 or Read_Register_2)
    begin
        Read_Data_1 <= Registers[Read_Register_1];
        Read_Data_2 <= Registers[Read_Register_2];
    end


    always @(posedge CLK)
    begin
        if (RegWrite) Registers[Write_Register] <= Write_Data;
    end
  

    initial begin

        Registers[0] <= 32'd0;
        Registers[1] <= 32'd0;
        Registers[2] <= 32'd0;
        Registers[3] <= 32'd0;
        Registers[4] <= 32'd0;
        Registers[5] <= 32'd0;
        Registers[6] <= 32'd0;
        Registers[7] <= 32'd0;
        Registers[8] <= 32'd0;
        Registers[9] <= 32'd0;
        Registers[10] <= 32'd0;
        Registers[11] <= 32'd0;
    end


endmodule
module Register_File(
     input [4:0] Read_Register_1,
     input [4:0] Read_Register_2,
     input [4:0] Write_Register,
     input [31:0] Write_Data,
     input RegWrite,
     input CLK,
     output reg [31:0] Read_Data_1,
     output reg [31:0] Read_Data_2
    );



    reg [31:0] Registers[31:0];
    
    

    always @(Read_Register_1 or Read_Register_2)
    begin
        Read_Data_1 <= Registers[Read_Register_1];
        Read_Data_2 <= Registers[Read_Register_2];
    end


    always @(posedge CLK)
    begin
        if (RegWrite) Registers[Write_Register] <= Write_Data;
    end
  

    initial begin

        Registers[0] <= 32'd0;
        Registers[1] <= 32'd0;
        Registers[2] <= 32'd0;
        Registers[3] <= 32'd0;
        Registers[4] <= 32'd0;
        Registers[5] <= 32'd0;
        Registers[6] <= 32'd0;
        Registers[7] <= 32'd0;
        Registers[8] <= 32'd0;
        Registers[9] <= 32'd0;
        Registers[10] <= 32'd0;
        Registers[11] <= 32'd0;
    end


endmodule