data/full_repos/permissive/464089711/sasebo_giii_aes/aes_composite_enc.v
1: b"%Error: data/full_repos/permissive/464089711/sasebo_giii_aes/aes_composite_enc.v:181: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nmodule AES_Comp_EncCore(di, ki, Rrg, do, ko);\n                                     ^~\n%Error: data/full_repos/permissive/464089711/sasebo_giii_aes/aes_composite_enc.v:184: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n  output [127:0] do, ko;\n                 ^~\n%Error: data/full_repos/permissive/464089711/sasebo_giii_aes/aes_composite_enc.v:205: syntax error, unexpected do, expecting TYPE-IDENTIFIER\n  assign do = ((Rrg[0] == 1)? sr: mx) ^ ki;\n         ^~\n%Error: Exiting due to 3 error(s)\n"
module AES_Composite_enc (Kin, Din, Dout, Krdy, Drdy1,EncDec, Kvld, Dvld, EN, BSY, CLK,RSTn);
  input  [127:0] Kin;
  input  [127:0] Din;
  output [127:0] Dout;
  input  Krdy;
  input  Drdy1;
  input  EncDec;
  input  RSTn;
  input  EN;
  input  CLK;
  output BSY;
  output Kvld;
  output Dvld;

  wire EN_E, EN_D;
  wire [127:0] Dout_E;

  
  wire BSY_E;
  wire Dvld_E;
  wire Kvld_E;

  wire Dvld_tmp, Kvld_tmp;
  reg  Dvld_reg, Kvld_reg;

  assign EN_E = (~EncDec) & EN;
  assign EN_D =  EncDec & EN;
  assign BSY  = BSY_E ;
 

  assign Dvld_tmp = Dvld_E & (~EncDec);
  assign Kvld_tmp = Kvld_E & (~EncDec);

  assign Dvld = ( (Dvld_reg == 1'b0) && (Dvld_tmp == 1'b1) ) ? 1'b1: 1'b0;
  assign Kvld = ( (Kvld_reg == 1'b0) && (Kvld_tmp == 1'b1) ) ? 1'b1: 1'b0;  

  assign Dout = ((EncDec == 0 && Dvld_E==1)? Dout_E : 128'h0);

    AES_Comp_ENC AES_Comp_ENC0(Kin, Din, Dout_E, Krdy, Drdy1, RSTn, EN_E, CLK, BSY_E, Kvld_E, Dvld_E);
  

  always @(posedge CLK) begin
    if (RSTn == 0) begin
      Dvld_reg <= 1'b0;
      Kvld_reg <= 1'b0;
	   
		
    end
    else if (EN == 1) begin
      Dvld_reg <= Dvld_tmp;
      Kvld_reg <= Kvld_tmp;
      
       
		
    end
	
  end
endmodule
module AES_Composite_enc (Kin, Din, Dout, Krdy, Drdy1,EncDec, Kvld, Dvld, EN, BSY, CLK,RSTn);

  input  [127:0] Kin;
  input  [127:0] Din;
  output [127:0] Dout;
  input  Krdy;
  input  Drdy1;
  input  EncDec;
  input  RSTn;
  input  EN;
  input  CLK;
  output BSY;
  output Kvld;
  output Dvld;

  wire EN_E, EN_D;
  wire [127:0] Dout_E;

  
  wire BSY_E;
  wire Dvld_E;
  wire Kvld_E;

  wire Dvld_tmp, Kvld_tmp;
  reg  Dvld_reg, Kvld_reg;

  assign EN_E = (~EncDec) & EN;
  assign EN_D =  EncDec & EN;
  assign BSY  = BSY_E ;
 

  assign Dvld_tmp = Dvld_E & (~EncDec);
  assign Kvld_tmp = Kvld_E & (~EncDec);

  assign Dvld = ( (Dvld_reg == 1'b0) && (Dvld_tmp == 1'b1) ) ? 1'b1: 1'b0;
  assign Kvld = ( (Kvld_reg == 1'b0) && (Kvld_tmp == 1'b1) ) ? 1'b1: 1'b0;  

  assign Dout = ((EncDec == 0 && Dvld_E==1)? Dout_E : 128'h0);

    AES_Comp_ENC AES_Comp_ENC0(Kin, Din, Dout_E, Krdy, Drdy1, RSTn, EN_E, CLK, BSY_E, Kvld_E, Dvld_E);
  

  always @(posedge CLK) begin
    if (RSTn == 0) begin
      Dvld_reg <= 1'b0;
      Kvld_reg <= 1'b0;
	   
		
    end
    else if (EN == 1) begin
      Dvld_reg <= Dvld_tmp;
      Kvld_reg <= Kvld_tmp;
      
       
		
    end
	
  end
endmodule