data/full_repos/permissive/447283927/register_file.v
data/verilator_xmls/8790c924-0910-4d6a-8dec-99c0b417bca3.xml
module register_file(Port_A, Port_B, Din, Addr_A, Addr_B, Addr_Wr, wr,clk);
			output reg [31:0] Port_A, Port_B;
			input [31:0] Din;
			input [4:0] Addr_A, Addr_B, Addr_Wr;
			input wr;
			reg [31:0] Reg_File [31:0];
			input clk;

	always @(negedge clk)
	begin
		if (wr)
		begin
			if (Addr_Wr != 0)
			begin
			     Reg_File[Addr_Wr] <= Din;
			end
		end
	end
	
	always @(*)
	begin
		if (Addr_A == 0)
              Port_A <= 0;
        else
              Port_A <= Reg_File[Addr_A];
        if (Addr_B == 0)
             Port_B <= 0;
        else
             Port_B <= Reg_File[Addr_B];
	end
	
endmodule
module register_file(Port_A, Port_B, Din, Addr_A, Addr_B, Addr_Wr, wr,clk);

			output reg [31:0] Port_A, Port_B;
			input [31:0] Din;
			input [4:0] Addr_A, Addr_B, Addr_Wr;
			input wr;
			reg [31:0] Reg_File [31:0];
			input clk;

	always @(negedge clk)
	begin
		if (wr)
		begin
			if (Addr_Wr != 0)
			begin
			     Reg_File[Addr_Wr] <= Din;
			end
		end
	end
	
	always @(*)
	begin
		if (Addr_A == 0)
              Port_A <= 0;
        else
              Port_A <= Reg_File[Addr_A];
        if (Addr_B == 0)
             Port_B <= 0;
        else
             Port_B <= Reg_File[Addr_B];
	end
	
endmodule