data/full_repos/permissive/433624543/generic_n_x_n_mult.v
data/verilator_xmls/77bc6db2-608d-4a2f-a0fe-edfaf76a4baf.xml
module Full_Adder_two_in(input a, b, carry_in, output reg sum, carry_out);
    always @(a or b or carry_in)
    begin
        sum = a ^ b ^ carry_in;
        carry_out = a & b | (a^b) & carry_in;
    end
endmodule
module Full_Adder_two_in(input a, b, carry_in, output reg sum, carry_out);

    always @(a or b or carry_in)
    begin
        sum = a ^ b ^ carry_in;
        carry_out = a & b | (a^b) & carry_in;
    end
endmodule