data/full_repos/permissive/521337848/Hardware/MEMORIES/RAM.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/521337848/Hardware/MEMORIES/RAM.v:19: Cell has missing pin: \'readRdyRAM\'\nBRAM #(14) ram1(\n           ^~~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/521337848/Hardware/MEMORIES/RAM.v:19: Cell has missing pin: \'saveRdyRAM\'\nBRAM #(14) ram1(\n           ^~~~\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/MEMORIES/RAM.v:55: Operator ASSIGNW expects 15 bits on the Assign RHS, but Assign RHS\'s SEL generates 12 bits.\n                                                                               : ... In instance BRAMI32.ram1\nwire[14:0] raddr = addr[11:0];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/MEMORIES/RAM.v:69: Operator ASSIGNW expects 15 bits on the Assign RHS, but Assign RHS\'s SEL generates 12 bits.\n                                                                               : ... In instance BRAMI32.ram1\nwire[14:0] iraddr = addr[11:0];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/MEMORIES/RAM.v:74: Bit extraction of array[3583:0] requires 12 bit index, not 15 bits.\n                                                                               : ... In instance BRAMI32.ram1\n if(we) memory[iraddr[14:0]] <= din;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/521337848/Hardware/MEMORIES/RAM.v:76: Bit extraction of array[3583:0] requires 12 bit index, not 15 bits.\n                                                                               : ... In instance BRAMI32.ram1\n out <= memory[iraddr[14:0]];\n              ^\n%Error: Exiting due to 6 warning(s)\n'
module BRAMI32
#(
	parameter blocks = 14
)(
	input[14:0] addr,
	input[31:0] din,
	input clk,rst,we,
	output[31:0] out,
	
	input startReadRAM,
	
	output readRdyRAM = 1,
	output saveRdyRAM =1
	
);

BRAM #(14) ram1(
	.addr(addr),
	.din(din),
	.clk(clk),
	.rst(rst),
	.we(we),
	
	
	.out(out),
	
	
	
);

	
assign readRdyRAM = 1;
assign saveRdyRAM = 1;
	
endmodule
module BRAMI32
#(
	parameter blocks = 14
)(
	input[14:0] addr,
	input[31:0] din,
	input clk,rst,we,
	output[31:0] out,
	
	input startReadRAM,
	
	output readRdyRAM = 1,
	output saveRdyRAM =1
	
);


BRAM #(14) ram1(
	.addr(addr),
	.din(din),
	.clk(clk),
	.rst(rst),
	.we(we),
	
	
	.out(out),
	
	
	
);

	
assign readRdyRAM = 1;
assign saveRdyRAM = 1;
	
endmodule