data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_par34.v
data/verilator_xmls/0638a661-d1c5-46ca-805b-201320bedb0e.xml
module sparc_ifu_par34 (

   out, 

   in
   );

   input [33:0] in;
   output 	out;

   assign  out = (^in[33:0]);

endmodule
module sparc_ifu_par34 (

   out, 

   in
   );


   input [33:0] in;
   output 	out;

   assign  out = (^in[33:0]);

endmodule