data/full_repos/permissive/43858668/final_verilog/src/clib/c_wf_alloc.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_wf_alloc.v:35: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_constants.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_constants.v.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_constants.v.sv\n             c_constants.v\n             c_constants.v.v\n             c_constants.v.sv\n             obj_dir/c_constants.v\n             obj_dir/c_constants.v.v\n             obj_dir/c_constants.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_wf_alloc.v:48: Define or directive not defined: \'`WF_ALLOC_TYPE_REP\'\n   parameter wf_alloc_type = `WF_ALLOC_TYPE_REP;\n                             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_wf_alloc.v:48: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter wf_alloc_type = `WF_ALLOC_TYPE_REP;\n                                               ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_wf_alloc.v:50: Define or directive not defined: \'`RESET_TYPE_ASYNC\'\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_wf_alloc.v:50: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                                           ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_wf_alloc.v:88: Define or directive not defined: \'`WF_ALLOC_TYPE_MUX\'\n      `WF_ALLOC_TYPE_MUX:\n      ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_wf_alloc.v:88: syntax error, unexpected \':\', expecting endcase\n      `WF_ALLOC_TYPE_MUX:\n                        ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_wf_alloc.v:104: Define or directive not defined: \'`WF_ALLOC_TYPE_REP\'\n      `WF_ALLOC_TYPE_REP:\n      ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_wf_alloc.v:120: Define or directive not defined: \'`WF_ALLOC_TYPE_DPA\'\n      `WF_ALLOC_TYPE_DPA:\n      ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_wf_alloc.v:136: Define or directive not defined: \'`WF_ALLOC_TYPE_ROT\'\n      `WF_ALLOC_TYPE_ROT:\n      ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_wf_alloc.v:152: Define or directive not defined: \'`WF_ALLOC_TYPE_LOOP\'\n      `WF_ALLOC_TYPE_LOOP:\n      ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_wf_alloc.v:168: Define or directive not defined: \'`WF_ALLOC_TYPE_SDPA\'\n      `WF_ALLOC_TYPE_SDPA:\n      ^~~~~~~~~~~~~~~~~~~\n%Error: Cannot continue\n'
module c_wf_alloc
  (clk, reset, active, req_pr, gnt_pr, gnt, update);
   
`include "c_constants.v"
   


   parameter num_ports = 8;
   

   parameter num_priorities = 1;
   

   parameter skip_empty_diags = 0;
   

   parameter wf_alloc_type = `WF_ALLOC_TYPE_REP;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   input clk;
   input reset;
   input active;
   

   input [0:num_priorities*num_ports*num_ports-1] req_pr;
   

   output [0:num_priorities*num_ports*num_ports-1] gnt_pr;
   wire [0:num_priorities*num_ports*num_ports-1]   gnt_pr;
   

   output [0:num_ports*num_ports-1] 		   gnt;
   wire [0:num_ports*num_ports-1] 		   gnt;
   

   input 					   update;
   
   generate
      
      if(num_ports == 1)
	begin
	   
	   c_lod
	     #(.width(num_priorities))
	   gnt_lod
	     (.data_in(req_pr),
	      .data_out(gnt_pr));
	   
	   assign gnt = |req_pr;
	   
	end
      else if(num_ports > 1)
	begin
	   
	   case(wf_alloc_type)
	     `WF_ALLOC_TYPE_MUX:
	       begin
		  c_wf_alloc_mux
		    #(.num_ports(num_ports),
		      .num_priorities(num_priorities),
		      .skip_empty_diags(skip_empty_diags),
		      .reset_type(reset_type))
		  core_mux
		    (.clk(clk),
		     .reset(reset),
		     .active(active),
		     .req_pr(req_pr),
		     .gnt_pr(gnt_pr),
		     .gnt(gnt),
		     .update(update));
	       end
	     `WF_ALLOC_TYPE_REP:
	       begin
		  c_wf_alloc_rep
		    #(.num_ports(num_ports),
		      .num_priorities(num_priorities),
		      .skip_empty_diags(skip_empty_diags),
		      .reset_type(reset_type))
		  core_rep
		    (.clk(clk),
		     .reset(reset),
		     .active(active),
		     .req_pr(req_pr),
		     .gnt_pr(gnt_pr),
		     .gnt(gnt),
		     .update(update));
	       end
	     `WF_ALLOC_TYPE_DPA:
	       begin
		  c_wf_alloc_dpa
		    #(.num_ports(num_ports),
		      .num_priorities(num_priorities),
		      .skip_empty_diags(skip_empty_diags),
		      .reset_type(reset_type))
		  core_dpa
		    (.clk(clk),
		     .reset(reset),
		     .active(active),
		     .req_pr(req_pr),
		     .gnt_pr(gnt_pr),
		     .gnt(gnt),
		     .update(update));
	       end      
	     `WF_ALLOC_TYPE_ROT:
	       begin
		  c_wf_alloc_rot
		    #(.num_ports(num_ports),
		      .num_priorities(num_priorities),
		      .skip_empty_diags(skip_empty_diags),
		      .reset_type(reset_type))
		  core_rot
		    (.clk(clk),
		     .reset(reset),
		     .active(active),
		     .req_pr(req_pr),
		     .gnt_pr(gnt_pr),
		     .gnt(gnt),
		     .update(update));
	       end
	     `WF_ALLOC_TYPE_LOOP:
	       begin
		  c_wf_alloc_loop
		    #(.num_ports(num_ports),
		      .num_priorities(num_priorities),
		      .skip_empty_diags(skip_empty_diags),
		      .reset_type(reset_type))
		  core_loop
		    (.clk(clk),
		     .reset(reset),
		     .active(active),
		     .req_pr(req_pr),
		     .gnt_pr(gnt_pr),
		     .gnt(gnt),
		     .update(update));
	       end
	     `WF_ALLOC_TYPE_SDPA:
	       begin
		  c_wf_alloc_sdpa
		    #(.num_ports(num_ports),
		      .num_priorities(num_priorities),
		      .skip_empty_diags(skip_empty_diags),
		      .reset_type(reset_type))
		  core_sdpa
		    (.clk(clk),
		     .reset(reset),
		     .active(active),
		     .req_pr(req_pr),
		     .gnt_pr(gnt_pr),
		     .gnt(gnt),
		     .update(update));
	       end
	   endcase
	   
	end
      
   endgenerate
   
endmodule
module c_wf_alloc
  (clk, reset, active, req_pr, gnt_pr, gnt, update);

   
`include "c_constants.v"
   


   parameter num_ports = 8;
   

   parameter num_priorities = 1;
   

   parameter skip_empty_diags = 0;
   

   parameter wf_alloc_type = `WF_ALLOC_TYPE_REP;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   input clk;
   input reset;
   input active;
   

   input [0:num_priorities*num_ports*num_ports-1] req_pr;
   

   output [0:num_priorities*num_ports*num_ports-1] gnt_pr;
   wire [0:num_priorities*num_ports*num_ports-1]   gnt_pr;
   

   output [0:num_ports*num_ports-1] 		   gnt;
   wire [0:num_ports*num_ports-1] 		   gnt;
   

   input 					   update;
   
   generate
      
      if(num_ports == 1)
	begin
	   
	   c_lod
	     #(.width(num_priorities))
	   gnt_lod
	     (.data_in(req_pr),
	      .data_out(gnt_pr));
	   
	   assign gnt = |req_pr;
	   
	end
      else if(num_ports > 1)
	begin
	   
	   case(wf_alloc_type)
	     `WF_ALLOC_TYPE_MUX:
	       begin
		  c_wf_alloc_mux
		    #(.num_ports(num_ports),
		      .num_priorities(num_priorities),
		      .skip_empty_diags(skip_empty_diags),
		      .reset_type(reset_type))
		  core_mux
		    (.clk(clk),
		     .reset(reset),
		     .active(active),
		     .req_pr(req_pr),
		     .gnt_pr(gnt_pr),
		     .gnt(gnt),
		     .update(update));
	       end
	     `WF_ALLOC_TYPE_REP:
	       begin
		  c_wf_alloc_rep
		    #(.num_ports(num_ports),
		      .num_priorities(num_priorities),
		      .skip_empty_diags(skip_empty_diags),
		      .reset_type(reset_type))
		  core_rep
		    (.clk(clk),
		     .reset(reset),
		     .active(active),
		     .req_pr(req_pr),
		     .gnt_pr(gnt_pr),
		     .gnt(gnt),
		     .update(update));
	       end
	     `WF_ALLOC_TYPE_DPA:
	       begin
		  c_wf_alloc_dpa
		    #(.num_ports(num_ports),
		      .num_priorities(num_priorities),
		      .skip_empty_diags(skip_empty_diags),
		      .reset_type(reset_type))
		  core_dpa
		    (.clk(clk),
		     .reset(reset),
		     .active(active),
		     .req_pr(req_pr),
		     .gnt_pr(gnt_pr),
		     .gnt(gnt),
		     .update(update));
	       end      
	     `WF_ALLOC_TYPE_ROT:
	       begin
		  c_wf_alloc_rot
		    #(.num_ports(num_ports),
		      .num_priorities(num_priorities),
		      .skip_empty_diags(skip_empty_diags),
		      .reset_type(reset_type))
		  core_rot
		    (.clk(clk),
		     .reset(reset),
		     .active(active),
		     .req_pr(req_pr),
		     .gnt_pr(gnt_pr),
		     .gnt(gnt),
		     .update(update));
	       end
	     `WF_ALLOC_TYPE_LOOP:
	       begin
		  c_wf_alloc_loop
		    #(.num_ports(num_ports),
		      .num_priorities(num_priorities),
		      .skip_empty_diags(skip_empty_diags),
		      .reset_type(reset_type))
		  core_loop
		    (.clk(clk),
		     .reset(reset),
		     .active(active),
		     .req_pr(req_pr),
		     .gnt_pr(gnt_pr),
		     .gnt(gnt),
		     .update(update));
	       end
	     `WF_ALLOC_TYPE_SDPA:
	       begin
		  c_wf_alloc_sdpa
		    #(.num_ports(num_ports),
		      .num_priorities(num_priorities),
		      .skip_empty_diags(skip_empty_diags),
		      .reset_type(reset_type))
		  core_sdpa
		    (.clk(clk),
		     .reset(reset),
		     .active(active),
		     .req_pr(req_pr),
		     .gnt_pr(gnt_pr),
		     .gnt(gnt),
		     .update(update));
	       end
	   endcase
	   
	end
      
   endgenerate
   
endmodule