data/full_repos/permissive/502135797/Lab4_March_2_2022/Code/top.v
1: b"%Error: data/full_repos/permissive/502135797/Lab4_March_2_2022/Code/top.v:18: Cannot find file containing module: 'clkmanager'\n    clkmanager clkmanager_wrapper(\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502135797/Lab4_March_2_2022/Code,data/full_repos/permissive/502135797/clkmanager\n             data/full_repos/permissive/502135797/Lab4_March_2_2022/Code,data/full_repos/permissive/502135797/clkmanager.v\n             data/full_repos/permissive/502135797/Lab4_March_2_2022/Code,data/full_repos/permissive/502135797/clkmanager.sv\n             clkmanager\n             clkmanager.v\n             clkmanager.sv\n             obj_dir/clkmanager\n             obj_dir/clkmanager.v\n             obj_dir/clkmanager.sv\n%Error: data/full_repos/permissive/502135797/Lab4_March_2_2022/Code/top.v:24: Cannot find file containing module: 'upcounter'\n    upcounter upcounter_wrapper(\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/502135797/Lab4_March_2_2022/Code/top.v:33: Cannot find file containing module: 'seg7driver'\n    seg7driver seg7driver_wrapper(\n    ^~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module top(
    input clkt,
    input rstt,
    input ent,
    input [4:0] SW1,
    input udt,
    output seg,
    output [6:0] Cnode1,
    output [7:0] AN1
    );
    wire [3:0] digit1;
    wire [3:0] digit2; 
    wire slowclk_out;
    
    
    clkmanager clkmanager_wrapper(
        .clk(clkt),
        .SW(SW1),
        .clkout(slowclk_out)
    );
    
    upcounter upcounter_wrapper(
        .rst1(rstt),
        .en(ent),
        .clk1(slowclk_out), 
        .tmp(digit1),
        .tmp2(digit2),
        .ud(udt)
    );
    
    seg7driver seg7driver_wrapper(
        .nexysCLK(clkt), 
        .digit1(digit1),
        .digit2(digit2),
        .Cnode(Cnode1),
        .dp(seg),
        .AN(AN1)
    );
       


endmodule
module top(
    input clkt,
    input rstt,
    input ent,
    input [4:0] SW1,
    input udt,
    output seg,
    output [6:0] Cnode1,
    output [7:0] AN1
    );

    wire [3:0] digit1;
    wire [3:0] digit2; 
    wire slowclk_out;
    
    
    clkmanager clkmanager_wrapper(
        .clk(clkt),
        .SW(SW1),
        .clkout(slowclk_out)
    );
    
    upcounter upcounter_wrapper(
        .rst1(rstt),
        .en(ent),
        .clk1(slowclk_out), 
        .tmp(digit1),
        .tmp2(digit2),
        .ud(udt)
    );
    
    seg7driver seg7driver_wrapper(
        .nexysCLK(clkt), 
        .digit1(digit1),
        .digit2(digit2),
        .Cnode(Cnode1),
        .dp(seg),
        .AN(AN1)
    );
       


endmodule