data/full_repos/permissive/517427004/CA1 - Linear Regression/Verilog/Substractor.v
1: b'%Error: Invalid Option: -\n'
module Substractor(a, b, out);
    parameter N = 32;

    input [N-1:0] a, b;
    output [N-1:0] out;

    assign out = a + ~b + 1'b1;
endmodule
module Substractor(a, b, out);

    parameter N = 32;

    input [N-1:0] a, b;
    output [N-1:0] out;

    assign out = a + ~b + 1'b1;
endmodule