data/full_repos/permissive/435108851/openlane/user_proj/src/ram_1w_1rs.v
1: b'%Warning-WIDTH: data/full_repos/permissive/435108851/openlane/user_proj/src/ram_1w_1rs.v:32: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s VARREF \'wr_mask\' generates 1 bits.\n                                                                                           : ... In instance Ram_1w_1rs\nassign wr_mask0 = wrMaskEnable?wr_mask:4\'hf;\n                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/435108851/openlane/user_proj/src/ram_1w_1rs.v:32: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 4 bits.\n                                                                                           : ... In instance Ram_1w_1rs\nassign wr_mask0 = wrMaskEnable?wr_mask:4\'hf;\n                ^\n%Error: data/full_repos/permissive/435108851/openlane/user_proj/src/ram_1w_1rs.v:34: Cannot find file containing module: \'sky130_sram_1kbyte_1rw1r_32x256_8\'\nsky130_sram_1kbyte_1rw1r_32x256_8 ram (\n^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/435108851/openlane/user_proj/src,data/full_repos/permissive/435108851/sky130_sram_1kbyte_1rw1r_32x256_8\n             data/full_repos/permissive/435108851/openlane/user_proj/src,data/full_repos/permissive/435108851/sky130_sram_1kbyte_1rw1r_32x256_8.v\n             data/full_repos/permissive/435108851/openlane/user_proj/src,data/full_repos/permissive/435108851/sky130_sram_1kbyte_1rw1r_32x256_8.sv\n             sky130_sram_1kbyte_1rw1r_32x256_8\n             sky130_sram_1kbyte_1rw1r_32x256_8.v\n             sky130_sram_1kbyte_1rw1r_32x256_8.sv\n             obj_dir/sky130_sram_1kbyte_1rw1r_32x256_8\n             obj_dir/sky130_sram_1kbyte_1rw1r_32x256_8.v\n             obj_dir/sky130_sram_1kbyte_1rw1r_32x256_8.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module Ram_1w_1rs #(
  parameter wordCount = 256,
  parameter wordWidth = 32,
  parameter clockCrossing = 1'b0,
  parameter technology = "auto",
  parameter readUnderWrite = "dontCare",
  parameter wrAddressWidth = 8,
  parameter wrDataWidth = 32,
  parameter wrMaskWidth = 1,
  parameter wrMaskEnable = 1'b0,
  parameter rdAddressWidth = 8,
  parameter rdDataWidth = 32 
) (
`ifdef USE_POWER_PINS
  inout vccd1,
  inout vssd1,
`endif
  input wr_clk,
  input wr_en,
  input [wrMaskWidth-1:0] wr_mask,
  input [wrAddressWidth-1:0] wr_addr,
  input [wrDataWidth-1:0] wr_data,
  input rd_clk,
  input rd_en,
  input [rdAddressWidth-1:0] rd_addr,
  output reg [rdDataWidth-1:0] rd_data
);

wire wr_mask0;
assign wr_mask0 = wrMaskEnable?wr_mask:4'hf;

sky130_sram_1kbyte_1rw1r_32x256_8 ram (
`ifdef USE_POWER_PINS
    .vccd1(vccd1),
    .vssd1(vssd1),
`endif
    .clk0   (wr_clk),
    .csb0   (~wr_en),
    .web0   (~wr_en),
    .wmask0 (wr_mask0),
    .addr0  (wr_addr[7:0]),
    .din0   (wr_data),
    .dout0  (),
    .clk1   (rd_clk),
    .csb1   (~rd_en),
    .addr1  (rd_addr[7:0]),
    .dout1  (rd_data)
);
endmodule
module Ram_1w_1rs #(
  parameter wordCount = 256,
  parameter wordWidth = 32,
  parameter clockCrossing = 1'b0,
  parameter technology = "auto",
  parameter readUnderWrite = "dontCare",
  parameter wrAddressWidth = 8,
  parameter wrDataWidth = 32,
  parameter wrMaskWidth = 1,
  parameter wrMaskEnable = 1'b0,
  parameter rdAddressWidth = 8,
  parameter rdDataWidth = 32 
) (
`ifdef USE_POWER_PINS
  inout vccd1,
  inout vssd1,
`endif
  input wr_clk,
  input wr_en,
  input [wrMaskWidth-1:0] wr_mask,
  input [wrAddressWidth-1:0] wr_addr,
  input [wrDataWidth-1:0] wr_data,
  input rd_clk,
  input rd_en,
  input [rdAddressWidth-1:0] rd_addr,
  output reg [rdDataWidth-1:0] rd_data
);


wire wr_mask0;
assign wr_mask0 = wrMaskEnable?wr_mask:4'hf;

sky130_sram_1kbyte_1rw1r_32x256_8 ram (
`ifdef USE_POWER_PINS
    .vccd1(vccd1),
    .vssd1(vssd1),
`endif
    .clk0   (wr_clk),
    .csb0   (~wr_en),
    .web0   (~wr_en),
    .wmask0 (wr_mask0),
    .addr0  (wr_addr[7:0]),
    .din0   (wr_data),
    .dout0  (),
    .clk1   (rd_clk),
    .csb1   (~rd_en),
    .addr1  (rd_addr[7:0]),
    .dout1  (rd_data)
);
endmodule