data/full_repos/permissive/423547971/College Coursework/Digital Design II Final Project/timer_mode_TB.v
1: b'%Error: Cannot find file containing module: Coursework/Digital\n        ... Looked in:\n             data/full_repos/permissive/423547971/College/Coursework/Digital\n             data/full_repos/permissive/423547971/College/Coursework/Digital.v\n             data/full_repos/permissive/423547971/College/Coursework/Digital.sv\n             Coursework/Digital\n             Coursework/Digital.v\n             Coursework/Digital.sv\n             obj_dir/Coursework/Digital\n             obj_dir/Coursework/Digital.v\n             obj_dir/Coursework/Digital.sv\n%Error: Cannot find file containing module: Design\n%Error: Cannot find file containing module: II\n%Error: Cannot find file containing module: Final\n%Error: Cannot find file containing module: Project,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/College\n%Error: Cannot find file containing module: Project/timer_mode_TB.v\n%Error: Exiting due to 7 error(s)\n'
module timer_mode_TB;

reg CLOCK;
reg RESET;
reg enable_timer_mode;

wire D0, D1, D2, D3, D4, D5, D6, D7, D8, D9,
	 CD0_M, CD1_M, CD2_M, CD3_M, CD4_M, CD5_M
	 CD6_M, CD7_M, CD8_M, CD9_M, CD0_m, CD1_m,
	 CD2_m, CD3_m, CD4_m, CD5_m, CD6_m, CD7_m,
	 CD8_m, CD9_m, en_countdown_M, en_countdown_m;


timer_mode TM(
	.CLOCK(CLOCK),
	.RESET(RESET),
	.enable_timer_mode(enable_timer_mode),
	
	.D0(D0),
	.D1(D1),
	.D2(D2),
	.D3(D3),
	.D4(D4),
	.D5(D5),
	.D6(D6),
	.D7(D7),
	.D8(D8),
	.D9(D9),
	
	.CD0_M(CD0_M),
	.CD1_M(CD1_M),
	.CD2_M(CD2_M),
	.CD3_M(CD3_M),
	.CD4_M(CD4_M),
	.CD5_M(CD5_M),
	.CD6_M(CD6_M),
	.CD7_M(CD7_M),
	.CD8_M(CD8_M),
	.CD9_M(CD9_M),
	
	.CD0_m(CD0_m),
	.CD1_m(CD1_m),
	.CD2_m(CD2_m),
	.CD3_m(CD3_m),
	.CD4_m(CD4_m),
	.CD5_m(CD5_m),
	.CD6_m(CD6_m),
	.CD7_m(CD7_m),
	.CD8_m(CD8_m),
	.CD9_m(CD9_m),
	.en_countdown_M(en_countdown_M),
	.en_countdown_m(en_countdown_m)
);


always
  #10 CLOCK = !CLOCK ;
  

initial
begin
  $dumpfile("timer_mode_TB.vcd") ;
  $dumpvars(0, timer_mode_TB) ;
end


initial
begin
		enable_timer_mode = 0 ; 		
		CLOCK  = 0 ;
		RESET  = 1 ;
  #30 	RESET  = 0 ;
  #500  enable_timer_mode = 1 ;


  #10000 $finish ; 
end
 
endmodule
module timer_mode_TB;


reg CLOCK;
reg RESET;
reg enable_timer_mode;

wire D0, D1, D2, D3, D4, D5, D6, D7, D8, D9,
	 CD0_M, CD1_M, CD2_M, CD3_M, CD4_M, CD5_M
	 CD6_M, CD7_M, CD8_M, CD9_M, CD0_m, CD1_m,
	 CD2_m, CD3_m, CD4_m, CD5_m, CD6_m, CD7_m,
	 CD8_m, CD9_m, en_countdown_M, en_countdown_m;


timer_mode TM(
	.CLOCK(CLOCK),
	.RESET(RESET),
	.enable_timer_mode(enable_timer_mode),
	
	.D0(D0),
	.D1(D1),
	.D2(D2),
	.D3(D3),
	.D4(D4),
	.D5(D5),
	.D6(D6),
	.D7(D7),
	.D8(D8),
	.D9(D9),
	
	.CD0_M(CD0_M),
	.CD1_M(CD1_M),
	.CD2_M(CD2_M),
	.CD3_M(CD3_M),
	.CD4_M(CD4_M),
	.CD5_M(CD5_M),
	.CD6_M(CD6_M),
	.CD7_M(CD7_M),
	.CD8_M(CD8_M),
	.CD9_M(CD9_M),
	
	.CD0_m(CD0_m),
	.CD1_m(CD1_m),
	.CD2_m(CD2_m),
	.CD3_m(CD3_m),
	.CD4_m(CD4_m),
	.CD5_m(CD5_m),
	.CD6_m(CD6_m),
	.CD7_m(CD7_m),
	.CD8_m(CD8_m),
	.CD9_m(CD9_m),
	.en_countdown_M(en_countdown_M),
	.en_countdown_m(en_countdown_m)
);


always
  #10 CLOCK = !CLOCK ;
  

initial
begin
  $dumpfile("timer_mode_TB.vcd") ;
  $dumpvars(0, timer_mode_TB) ;
end


initial
begin
		enable_timer_mode = 0 ; 		
		CLOCK  = 0 ;
		RESET  = 1 ;
  #30 	RESET  = 0 ;
  #500  enable_timer_mode = 1 ;


  #10000 $finish ; 
end
 
endmodule