data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/tb/support/bytewrite_ram_1b.v
1: b'%Warning-WIDTH: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/tb/support/bytewrite_ram_1b.v:38: Bit extraction of array[4095:0] requires 12 bit index, not 14 bits.\n                                                                                                               : ... In instance bytewrite_ram_1b\n    dout <= RAM[addr >> 2];\n               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/522553437/verilog/rtl/riscv-jedro-1/tb/support/bytewrite_ram_1b.v:47: Bit extraction of array[4095:0] requires 12 bit index, not 14 bits.\n                                                                                                               : ... In instance bytewrite_ram_1b\n        RAM[addr >> 2][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= di[(i+1)*COL_WIDTH-1:i*COL_WIDTH];\n           ^\n%Error: Exiting due to 2 warning(s)\n'
module bytewrite_ram_1b (clk, we, addr, di, dout);

parameter MEM_INIT_FILE="";
parameter INIT_FILE_BIN=1;
parameter SIZE = 2**12; 
parameter ADDR_WIDTH = $clog2(SIZE*4); 
parameter COL_WIDTH = 8; 
parameter NB_COL = 4;

input clk;
input [NB_COL-1:0] we;
input [ADDR_WIDTH-1:0] addr;
input [NB_COL*COL_WIDTH-1:0] di;
output reg [NB_COL*COL_WIDTH-1:0] dout;

reg [NB_COL*COL_WIDTH-1:0] RAM [SIZE-1:0];

integer flen;
initial begin
    if (MEM_INIT_FILE != "") begin
        if   (INIT_FILE_BIN==1) $readmemb(MEM_INIT_FILE, RAM);
        else                    $readmemh(MEM_INIT_FILE, RAM);
    end
end

always @(posedge clk)
begin
    dout <= RAM[addr >> 2];
end

generate genvar i;
for (i = 0; i < NB_COL; i = i+1)
begin
always @(posedge clk)
begin
    if (we[i])
        RAM[addr >> 2][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= di[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
    end 
end
endgenerate

endmodule
module bytewrite_ram_1b (clk, we, addr, di, dout);


parameter MEM_INIT_FILE="";
parameter INIT_FILE_BIN=1;
parameter SIZE = 2**12; 
parameter ADDR_WIDTH = $clog2(SIZE*4); 
parameter COL_WIDTH = 8; 
parameter NB_COL = 4;

input clk;
input [NB_COL-1:0] we;
input [ADDR_WIDTH-1:0] addr;
input [NB_COL*COL_WIDTH-1:0] di;
output reg [NB_COL*COL_WIDTH-1:0] dout;

reg [NB_COL*COL_WIDTH-1:0] RAM [SIZE-1:0];

integer flen;
initial begin
    if (MEM_INIT_FILE != "") begin
        if   (INIT_FILE_BIN==1) $readmemb(MEM_INIT_FILE, RAM);
        else                    $readmemh(MEM_INIT_FILE, RAM);
    end
end

always @(posedge clk)
begin
    dout <= RAM[addr >> 2];
end

generate genvar i;
for (i = 0; i < NB_COL; i = i+1)
begin
always @(posedge clk)
begin
    if (we[i])
        RAM[addr >> 2][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= di[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
    end 
end
endgenerate

endmodule