data/full_repos/permissive/525452387/testbench/ram_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/ram_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #0 begin\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/ram_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/ram_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/ram_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/ram_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/ram_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/ram_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n        #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/525452387/testbench/ram_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n    always #1 begin\n           ^\n%Error: data/full_repos/permissive/525452387/testbench/ram_tb.v:75: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("regs.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/525452387/testbench/ram_tb.v:76: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, ram_1);\n        ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ram_test_bench;
    reg ram_1_clk;
    reg ram_1_rst_;
    reg ram_1_we_i;

    reg[31:0]  ram_1_addr_i;
    reg[31:0] ram_1_data_i;

    wire[31:0] ram_1_data_o;

    ram ram_1 (
        .clk  (ram_1_clk),
        .rst_ (ram_1_rst_),
        .we_i(ram_1_we_i),
        .addr_i(ram_1_addr_i),
        .data_i(ram_1_data_i),
        .data_o(ram_1_data_o)
    );

    initial begin
        #0 begin
            ram_1_clk <= 1'b1;
            ram_1_rst_ <= 0;
        end


        #1 begin
            ram_1_rst_ <= 1;
        end


        #1 begin
            ram_1_addr_i <= 5'h8;
            ram_1_data_i <= 32'h42;
            ram_1_we_i <= 1'b1;
        end


        #1 begin
            if (ram_1_data_o == 32'h42) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
            ram_1_we_i <= 1'b0;
        end


        #1 begin
            ram_1_rst_ <= 0;
        end


        #1 begin
            if (ram_1_data_o == 32'h0) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
            ram_1_we_i <= 1'b0;
        end

        #1 begin
            $finish;
        end
    end

    always #1 begin
        ram_1_clk <= ~ram_1_clk;
    end

    initial begin
        $dumpfile("regs.vcd");
        $dumpvars(0, ram_1);
    end

endmodule
module ram_test_bench;

    reg ram_1_clk;
    reg ram_1_rst_;
    reg ram_1_we_i;

    reg[31:0]  ram_1_addr_i;
    reg[31:0] ram_1_data_i;

    wire[31:0] ram_1_data_o;

    ram ram_1 (
        .clk  (ram_1_clk),
        .rst_ (ram_1_rst_),
        .we_i(ram_1_we_i),
        .addr_i(ram_1_addr_i),
        .data_i(ram_1_data_i),
        .data_o(ram_1_data_o)
    );

    initial begin
        #0 begin
            ram_1_clk <= 1'b1;
            ram_1_rst_ <= 0;
        end


        #1 begin
            ram_1_rst_ <= 1;
        end


        #1 begin
            ram_1_addr_i <= 5'h8;
            ram_1_data_i <= 32'h42;
            ram_1_we_i <= 1'b1;
        end


        #1 begin
            if (ram_1_data_o == 32'h42) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
            ram_1_we_i <= 1'b0;
        end


        #1 begin
            ram_1_rst_ <= 0;
        end


        #1 begin
            if (ram_1_data_o == 32'h0) begin
                $display("[TIME ", $time, "] OK");
            end else begin
                $display("[TIME ", $time, "] NG");
            end
            ram_1_we_i <= 1'b0;
        end

        #1 begin
            $finish;
        end
    end

    always #1 begin
        ram_1_clk <= ~ram_1_clk;
    end

    initial begin
        $dumpfile("regs.vcd");
        $dumpvars(0, ram_1);
    end

endmodule