data/full_repos/permissive/521337848/Hardware/SPISD/receiver.v
data/verilator_xmls/6b2e6e31-5c02-48da-a77c-065d76c7f3f2.xml
module receiver(
	input clk,
	input dclk,
	input rst,
	
	input reset,
		
	input readed,
	input[7:0] in,
	
	input gets,
	output reg rdy,
	output reg[7:0] out
);

localparam LENM = 8;

wire[7:0] n_in;
wire n_readed;

receiverbuffer rb(
	.clk(clk),
	.dclk(dclk),
	.rst(rst),
	
	.in(in),
	.readed(readed),
	
	.n_in(n_in),
	.n_readed(n_readed)
);

reg[7:0] f_memory[LENM - 1:0];
reg[7:0] n_memory[LENM - 1:0];

reg[7:0] f_out;

integer n;
integer p;

always@(posedge clk or posedge rst)
	if(rst)
		f_out <= 0;
	else
		f_out <= out;
		
always@(posedge clk or posedge rst)
	if(rst)
		for(n=0;n<LENM;n = n + 1) f_memory[n] <= 0; 
	else
		for(n=0;n<LENM;n = n + 1) f_memory[n] <= n_memory[n]; 
		

always@(*)begin
	
	out = f_out;
	rdy = 0;
	
	for(p=0;p<LENM;p = p + 1) n_memory[p] = f_memory[p]; 
	
	if(reset) 
		for(p=0;p<LENM;p = p + 1) n_memory[p] = 0;
	
	if(n_readed) begin
		n_memory[0] = n_in; 
		
		for(p=0;p<LENM - 1;p = p + 1)begin
			n_memory[p+1] = f_memory[p]; 
		end
	end
	
	if(gets) begin
		out = f_memory[LENM - 1];
		rdy = 1;
		
		for(p=0;p<LENM - 1;p = p + 1)begin
			n_memory[p+1] = f_memory[p];  
		end
	end
	
	
end



endmodule
module receiver(
	input clk,
	input dclk,
	input rst,
	
	input reset,
		
	input readed,
	input[7:0] in,
	
	input gets,
	output reg rdy,
	output reg[7:0] out
);


localparam LENM = 8;

wire[7:0] n_in;
wire n_readed;

receiverbuffer rb(
	.clk(clk),
	.dclk(dclk),
	.rst(rst),
	
	.in(in),
	.readed(readed),
	
	.n_in(n_in),
	.n_readed(n_readed)
);

reg[7:0] f_memory[LENM - 1:0];
reg[7:0] n_memory[LENM - 1:0];

reg[7:0] f_out;

integer n;
integer p;

always@(posedge clk or posedge rst)
	if(rst)
		f_out <= 0;
	else
		f_out <= out;
		
always@(posedge clk or posedge rst)
	if(rst)
		for(n=0;n<LENM;n = n + 1) f_memory[n] <= 0; 
	else
		for(n=0;n<LENM;n = n + 1) f_memory[n] <= n_memory[n]; 
		

always@(*)begin
	
	out = f_out;
	rdy = 0;
	
	for(p=0;p<LENM;p = p + 1) n_memory[p] = f_memory[p]; 
	
	if(reset) 
		for(p=0;p<LENM;p = p + 1) n_memory[p] = 0;
	
	if(n_readed) begin
		n_memory[0] = n_in; 
		
		for(p=0;p<LENM - 1;p = p + 1)begin
			n_memory[p+1] = f_memory[p]; 
		end
	end
	
	if(gets) begin
		out = f_memory[LENM - 1];
		rdy = 1;
		
		for(p=0;p<LENM - 1;p = p + 1)begin
			n_memory[p+1] = f_memory[p];  
		end
	end
	
	
end



endmodule