data/full_repos/permissive/451577625/system/register_32.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/451577625/system/register_32.v:45: Unsupported: Ignoring delay on this delayed statement.\n   forever #10 clockin = ~clockin;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/451577625/system/register_32.v:77: Unsupported: Ignoring delay on this delayed statement.\n    #10;  \n    ^\n%Warning-INFINITELOOP: data/full_repos/permissive/451577625/system/register_32.v:45: Infinite loop (condition always true)\n                                                                                   : ... In instance register_32_tb\n   forever #10 clockin = ~clockin;\n   ^~~~~~~\n%Error: Exiting due to 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module register_32_tb;

	reg clockin, clearin, writein;
	reg [31:0] datain;
	wire [31:0] dataout;
	
	localparam period = 20;
	
	register_32 DUT (.D(datain), .Q(dataout), .clr(clearin), .clk(clockin), .write(writein));
	
	parameter Default = 4'b0000;
	parameter s_clear = 4'b0001;
	parameter s_write_1 = 4'b0010;
	parameter s_write_2 = 4'b0011;
	
	reg [3:0] Present_state = Default;
	
	initial
		begin
			clockin = 0;
			forever #10 clockin = ~clockin;
	end
	
	always @ (posedge clockin)
	begin
		case (Present_state)
			Default: Present_state = s_write_1;
			s_write_1: Present_state = s_write_2;
			s_write_2: Present_state = s_clear;
			s_clear : Present_state = s_write_1;
		endcase
	end
	
	always @ (Present_state)
	begin
		case(Present_state)
			Default: begin
				datain = 'h00000000;
				writein = 0;
				clearin = 1;
			end
			s_write_1: begin
				clearin = 1;
				datain = 'h11111111;
				writein = 1;
			end
			s_write_2: begin
				clearin = 1;
				writein = 1;
				datain = 'h11110000;
			end
			s_clear: begin
				#10;
				clearin = 0;
			end
		endcase
	end
endmodule
module register_32_tb;


	reg clockin, clearin, writein;
	reg [31:0] datain;
	wire [31:0] dataout;
	
	localparam period = 20;
	
	register_32 DUT (.D(datain), .Q(dataout), .clr(clearin), .clk(clockin), .write(writein));
	
	parameter Default = 4'b0000;
	parameter s_clear = 4'b0001;
	parameter s_write_1 = 4'b0010;
	parameter s_write_2 = 4'b0011;
	
	reg [3:0] Present_state = Default;
	
	initial
		begin
			clockin = 0;
			forever #10 clockin = ~clockin;
	end
	
	always @ (posedge clockin)
	begin
		case (Present_state)
			Default: Present_state = s_write_1;
			s_write_1: Present_state = s_write_2;
			s_write_2: Present_state = s_clear;
			s_clear : Present_state = s_write_1;
		endcase
	end
	
	always @ (Present_state)
	begin
		case(Present_state)
			Default: begin
				datain = 'h00000000;
				writein = 0;
				clearin = 1;
			end
			s_write_1: begin
				clearin = 1;
				datain = 'h11111111;
				writein = 1;
			end
			s_write_2: begin
				clearin = 1;
				writein = 1;
				datain = 'h11110000;
			end
			s_clear: begin
				#10;
				clearin = 0;
			end
		endcase
	end
endmodule