data/full_repos/permissive/462122681/neg.v
data/verilator_xmls/8df66e02-d236-4357-a65e-8be18e8affe6.xml
module neg(
	input wire [31:0] Ra,
	output wire [31:0] Rb
);



	
endmodule
module neg(
	input wire [31:0] Ra,
	output wire [31:0] Rb
);




	
endmodule