data/full_repos/permissive/531341619/rtl/bram_fifo.v
1: b"%Error: data/full_repos/permissive/531341619/rtl/bram_fifo.v:40: Cannot find file containing module: 'simple_dual_port_no_rden'\n  simple_dual_port_no_rden #(\n  ^~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/531341619/rtl,data/full_repos/permissive/531341619/simple_dual_port_no_rden\n             data/full_repos/permissive/531341619/rtl,data/full_repos/permissive/531341619/simple_dual_port_no_rden.v\n             data/full_repos/permissive/531341619/rtl,data/full_repos/permissive/531341619/simple_dual_port_no_rden.sv\n             simple_dual_port_no_rden\n             simple_dual_port_no_rden.v\n             simple_dual_port_no_rden.sv\n             obj_dir/simple_dual_port_no_rden\n             obj_dir/simple_dual_port_no_rden.v\n             obj_dir/simple_dual_port_no_rden.sv\n%Error: Exiting due to 1 error(s)\n"
module bram_fifo
#(
  parameter ADDR_WIDTH = 8,
  parameter DATA_WIDTH = 64
) (
   input wire clk, rst_n,
   input wire rd_en, wr_en_in,
   input  wire [DATA_WIDTH-1:0] data_in,
   output wire fifo_empty, fifo_full,
   output wire [DATA_WIDTH-1:0] data_out
);
  
  reg fifo_empty_reg, fifo_empty_nxt;
  reg fifo_full_reg, fifo_full_nxt;
  reg [ADDR_WIDTH-1:0] rd_ptr_reg, rd_ptr_nxt, rd_ptr_succ;
  reg [ADDR_WIDTH-1:0] wr_ptr_reg, wr_ptr_nxt, wr_ptr_succ;
  
  
  simple_dual_port_no_rden #(
  .ADDR_WIDTH(ADDR_WIDTH),
  .DATA_WIDTH(DATA_WIDTH)
) simple_dual_port_ram(
  .clk(clk),
  .wr_en(wr_en_in),
  .wr_addr(wr_ptr_reg),
  .data_i(data_in),
  .rd_addr(rd_ptr_reg),
  .data_o_r(data_out)
);
  

  always @(posedge clk)
  begin
    if (rst_n==1'b0) 
    begin
      rd_ptr_reg <= 'd0;
      wr_ptr_reg <= 'd0;
      fifo_full_reg <= 1'b0;
      fifo_empty_reg <= 1'b1;
    end
    else 
    begin;
      rd_ptr_reg <= rd_ptr_nxt;
      wr_ptr_reg <= wr_ptr_nxt;
      fifo_full_reg <= fifo_full_nxt;
      fifo_empty_reg <= fifo_empty_nxt;
    end
  end
  
  always @(*)
  begin
    rd_ptr_succ = rd_ptr_reg + 1'b1;
    wr_ptr_succ = wr_ptr_reg + 1'b1;
    rd_ptr_nxt = rd_ptr_reg;
    wr_ptr_nxt = wr_ptr_reg;
    fifo_full_nxt = fifo_full_reg;
    fifo_empty_nxt = fifo_empty_reg;
    casex({wr_en_in, rd_en, fifo_empty_reg, fifo_full_reg})
      4'b010x:
      begin
        rd_ptr_nxt = rd_ptr_succ;
        fifo_full_nxt = 1'b0;
        if (rd_ptr_succ == wr_ptr_reg)
        begin
          fifo_empty_nxt = 1'b1;
        end
      end
      4'b10x0:
      begin
        wr_ptr_nxt = wr_ptr_succ;
        fifo_empty_nxt = 1'b0;
        if (wr_ptr_succ==rd_ptr_reg) 
        begin
          fifo_full_nxt = 1'b1;
        end
      end
      4'b110x:
      begin
        wr_ptr_nxt = wr_ptr_succ;
        rd_ptr_nxt = rd_ptr_succ;
      end
      4'b111x:
      begin
        wr_ptr_nxt = wr_ptr_succ;
        fifo_empty_nxt = 1'b0;
      end
    endcase
  end
  assign fifo_full = fifo_full_reg;
  assign fifo_empty = fifo_empty_reg;
endmodule
module bram_fifo
#(
  parameter ADDR_WIDTH = 8,
  parameter DATA_WIDTH = 64
) (
   input wire clk, rst_n,
   input wire rd_en, wr_en_in,
   input  wire [DATA_WIDTH-1:0] data_in,
   output wire fifo_empty, fifo_full,
   output wire [DATA_WIDTH-1:0] data_out
);

  
  reg fifo_empty_reg, fifo_empty_nxt;
  reg fifo_full_reg, fifo_full_nxt;
  reg [ADDR_WIDTH-1:0] rd_ptr_reg, rd_ptr_nxt, rd_ptr_succ;
  reg [ADDR_WIDTH-1:0] wr_ptr_reg, wr_ptr_nxt, wr_ptr_succ;
  
  
  simple_dual_port_no_rden #(
  .ADDR_WIDTH(ADDR_WIDTH),
  .DATA_WIDTH(DATA_WIDTH)
) simple_dual_port_ram(
  .clk(clk),
  .wr_en(wr_en_in),
  .wr_addr(wr_ptr_reg),
  .data_i(data_in),
  .rd_addr(rd_ptr_reg),
  .data_o_r(data_out)
);
  

  always @(posedge clk)
  begin
    if (rst_n==1'b0) 
    begin
      rd_ptr_reg <= 'd0;
      wr_ptr_reg <= 'd0;
      fifo_full_reg <= 1'b0;
      fifo_empty_reg <= 1'b1;
    end
    else 
    begin;
      rd_ptr_reg <= rd_ptr_nxt;
      wr_ptr_reg <= wr_ptr_nxt;
      fifo_full_reg <= fifo_full_nxt;
      fifo_empty_reg <= fifo_empty_nxt;
    end
  end
  
  always @(*)
  begin
    rd_ptr_succ = rd_ptr_reg + 1'b1;
    wr_ptr_succ = wr_ptr_reg + 1'b1;
    rd_ptr_nxt = rd_ptr_reg;
    wr_ptr_nxt = wr_ptr_reg;
    fifo_full_nxt = fifo_full_reg;
    fifo_empty_nxt = fifo_empty_reg;
    casex({wr_en_in, rd_en, fifo_empty_reg, fifo_full_reg})
      4'b010x:
      begin
        rd_ptr_nxt = rd_ptr_succ;
        fifo_full_nxt = 1'b0;
        if (rd_ptr_succ == wr_ptr_reg)
        begin
          fifo_empty_nxt = 1'b1;
        end
      end
      4'b10x0:
      begin
        wr_ptr_nxt = wr_ptr_succ;
        fifo_empty_nxt = 1'b0;
        if (wr_ptr_succ==rd_ptr_reg) 
        begin
          fifo_full_nxt = 1'b1;
        end
      end
      4'b110x:
      begin
        wr_ptr_nxt = wr_ptr_succ;
        rd_ptr_nxt = rd_ptr_succ;
      end
      4'b111x:
      begin
        wr_ptr_nxt = wr_ptr_succ;
        fifo_empty_nxt = 1'b0;
      end
    endcase
  end
  assign fifo_full = fifo_full_reg;
  assign fifo_empty = fifo_empty_reg;
endmodule