data/full_repos/permissive/528509847/src/ibnalhaytham.v
1: b"%Error: data/full_repos/permissive/528509847/src/ibnalhaytham.v:76: Cannot find file containing module: 'processor'\n    processor processor_1(stall, reset, clk, inst_mem_read, data_mem_read, data_mem_we, inst_mem_addr, data_mem_addr, data_mem_write_data);\n    ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/528509847/src,data/full_repos/permissive/528509847/processor\n             data/full_repos/permissive/528509847/src,data/full_repos/permissive/528509847/processor.v\n             data/full_repos/permissive/528509847/src,data/full_repos/permissive/528509847/processor.sv\n             processor\n             processor.v\n             processor.sv\n             obj_dir/processor\n             obj_dir/processor.v\n             obj_dir/processor.sv\n%Error: data/full_repos/permissive/528509847/src/ibnalhaytham.v:79: Cannot find file containing module: 'memory_controler'\n    memory_controler memcon1(\n    ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module ibnalhaytham(

    input wire          wb_clk_i,
	

    input wire [31:0]    la1_data_in,
    output wire [31:0]   buf_la1_data_out,
    input wire [31:0]    la1_oenb, 
	

    input wire [6:0]     io_in,
    output wire [20:0]   io_out,


    input wire           user_clock2
    );
	









    reg stall_la, reset_la;
    always @(negedge clk) begin
        if (reset_io) begin
            stall_la <= 0;
            reset_la <= 0;
        end else if (la1_oenb == 32'hFFFFFFF0) begin
            stall_la <= la1_data_in[0]; 
            reset_la <= la1_data_in[1];
        end
    end
    wire reset, reset_io; 
    assign reset_io = io_in[2];
    assign reset = reset_io | reset_la;
    wire stall_m, stall_io;
    assign stall_io = io_in[5];
    assign stall = stall_io | stall_m | stall_la;


    wire clk;
    assign clk =(io_in[4:3] == 2'd0) ? 
                    la1_data_in[0] :
                (io_in[4:3] == 2'd1) ?
                    wb_clk_i :
                (io_in[4:3] == 2'd2) ?
                    io_in[6] :
                (io_in[4:3] == 2'd3) ?
                    user_clock2 : 1'b0; 


    wire [31:0] data_mem_read;
    wire [31:0] inst_mem_read;
    wire data_mem_we;
    wire [31:0] inst_mem_addr, data_mem_addr, data_mem_write_data;
    wire stall;


    processor processor_1(stall, reset, clk, inst_mem_read, data_mem_read, data_mem_we, inst_mem_addr, data_mem_addr, data_mem_write_data);


    memory_controler memcon1(
        data_mem_read,
        inst_mem_read,
        data_mem_we,
        inst_mem_addr, data_mem_addr, data_mem_write_data,
        stall_m, 


        la1_data_in,
        buf_la1_data_out,
        la1_oenb,

        io_in[1:0],
        io_out,

        clk, reset
    );
endmodule
module ibnalhaytham(

    input wire          wb_clk_i,
	

    input wire [31:0]    la1_data_in,
    output wire [31:0]   buf_la1_data_out,
    input wire [31:0]    la1_oenb, 
	

    input wire [6:0]     io_in,
    output wire [20:0]   io_out,


    input wire           user_clock2
    );

	









    reg stall_la, reset_la;
    always @(negedge clk) begin
        if (reset_io) begin
            stall_la <= 0;
            reset_la <= 0;
        end else if (la1_oenb == 32'hFFFFFFF0) begin
            stall_la <= la1_data_in[0]; 
            reset_la <= la1_data_in[1];
        end
    end
    wire reset, reset_io; 
    assign reset_io = io_in[2];
    assign reset = reset_io | reset_la;
    wire stall_m, stall_io;
    assign stall_io = io_in[5];
    assign stall = stall_io | stall_m | stall_la;


    wire clk;
    assign clk =(io_in[4:3] == 2'd0) ? 
                    la1_data_in[0] :
                (io_in[4:3] == 2'd1) ?
                    wb_clk_i :
                (io_in[4:3] == 2'd2) ?
                    io_in[6] :
                (io_in[4:3] == 2'd3) ?
                    user_clock2 : 1'b0; 


    wire [31:0] data_mem_read;
    wire [31:0] inst_mem_read;
    wire data_mem_we;
    wire [31:0] inst_mem_addr, data_mem_addr, data_mem_write_data;
    wire stall;


    processor processor_1(stall, reset, clk, inst_mem_read, data_mem_read, data_mem_we, inst_mem_addr, data_mem_addr, data_mem_write_data);


    memory_controler memcon1(
        data_mem_read,
        inst_mem_read,
        data_mem_we,
        inst_mem_addr, data_mem_addr, data_mem_write_data,
        stall_m, 


        la1_data_in,
        buf_la1_data_out,
        la1_oenb,

        io_in[1:0],
        io_out,

        clk, reset
    );
endmodule