data/full_repos/permissive/452215364/rtl/opl2/operator/calc_rhythm_phase.v
1: b'%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/calc_rhythm_phase.v:53: Cannot find include file: opl3.vh\n`include "opl3.vh" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/452215364/rtl/opl2/operator,data/full_repos/permissive/452215364/opl3.vh\n             data/full_repos/permissive/452215364/rtl/opl2/operator,data/full_repos/permissive/452215364/opl3.vh.v\n             data/full_repos/permissive/452215364/rtl/opl2/operator,data/full_repos/permissive/452215364/opl3.vh.sv\n             opl3.vh\n             opl3.vh.v\n             opl3.vh.sv\n             obj_dir/opl3.vh\n             obj_dir/opl3.vh.v\n             obj_dir/opl3.vh.sv\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/calc_rhythm_phase.v:59: Define or directive not defined: \'`OP_NUM_WIDTH\'\n    input wire [`OP_NUM_WIDTH-1:0] op_num,          \n                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/calc_rhythm_phase.v:60: Define or directive not defined: \'`PHASE_ACC_WIDTH\'\n    input wire [`PHASE_ACC_WIDTH-1:0] phase_acc,\n                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/calc_rhythm_phase.v:61: Define or directive not defined: \'`PHASE_ACC_WIDTH\'\n    input wire [`PHASE_ACC_WIDTH-1:0] phase_acc_17,\n                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/calc_rhythm_phase.v:62: Define or directive not defined: \'`PHASE_ACC_WIDTH\'\n    input wire [`PHASE_ACC_WIDTH-1:0] phase_acc_13,\n                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/calc_rhythm_phase.v:64: Define or directive not defined: \'`PHASE_ACC_WIDTH\'\n    output reg [`PHASE_ACC_WIDTH-1:0] rhythm_phase\n                ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/calc_rhythm_phase.v:72: Define or directive not defined: \'`PHASE_ACC_WIDTH\'\n    reg [`PHASE_ACC_WIDTH-10-1:0] friend_phase;\n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/calc_rhythm_phase.v:73: Define or directive not defined: \'`PHASE_ACC_WIDTH\'\n    wire [`PHASE_ACC_WIDTH-10-1:0] phase_bit;\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/calc_rhythm_phase.v:74: Define or directive not defined: \'`PHASE_ACC_WIDTH\'\n    wire [`PHASE_ACC_WIDTH-10-1:0] upper_current_phase;\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/calc_rhythm_phase.v:75: Define or directive not defined: \'`PHASE_ACC_WIDTH\'\n    reg [`PHASE_ACC_WIDTH-10-1:0] noise_bit;    \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/calc_rhythm_phase.v:85: Define or directive not defined: \'`OP_HI_HAT\'\n        `OP_HI_HAT:     friend_phase = phase_acc_17 >> 10;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/calc_rhythm_phase.v:85: syntax error, unexpected \':\', expecting endcase\n        `OP_HI_HAT:     friend_phase = phase_acc_17 >> 10;\n                  ^\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/calc_rhythm_phase.v:86: Define or directive not defined: \'`OP_TOP_CYMBAL\'\n        `OP_TOP_CYMBAL: friend_phase = phase_acc_13 >> 10;\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/calc_rhythm_phase.v:96: Define or directive not defined: \'`OP_HI_HAT\'\n        `OP_HI_HAT:     noise_bit = rand_num[0] << 1;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/calc_rhythm_phase.v:96: syntax error, unexpected \':\', expecting endcase\n        `OP_HI_HAT:     noise_bit = rand_num[0] << 1;\n                  ^\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/calc_rhythm_phase.v:97: Define or directive not defined: \'`OP_SNARE_DRUM\'\n        `OP_SNARE_DRUM: noise_bit = rand_num[0] << 8;\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/calc_rhythm_phase.v:103: Define or directive not defined: \'`OP_NORMAL\'\n        `OP_NORMAL:     rhythm_phase = phase_acc;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/calc_rhythm_phase.v:104: Define or directive not defined: \'`OP_BASS_DRUM\'\n        `OP_BASS_DRUM:  rhythm_phase = phase_acc;\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/calc_rhythm_phase.v:105: Define or directive not defined: \'`OP_HI_HAT\'\n        `OP_HI_HAT:     rhythm_phase = ((phase_bit << 8) | (\'h34 << (phase_bit ^ noise_bit))) << 10;\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/calc_rhythm_phase.v:106: Define or directive not defined: \'`OP_TOM_TOM\'\n        `OP_TOM_TOM:    rhythm_phase = phase_acc;\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/calc_rhythm_phase.v:107: Define or directive not defined: \'`OP_SNARE_DRUM\'\n        `OP_SNARE_DRUM: rhythm_phase = ((\'h100 + (upper_current_phase & \'h100)) ^ noise_bit) << 10;\n        ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452215364/rtl/opl2/operator/calc_rhythm_phase.v:108: Define or directive not defined: \'`OP_TOP_CYMBAL\'\n        `OP_TOP_CYMBAL: rhythm_phase = ((1 + phase_bit) << 8) << 10;\n        ^~~~~~~~~~~~~~\n%Error: Exiting due to 22 error(s)\n'
module calc_rhythm_phase (
    input wire clk,
    input wire reset,
    input wire sample_clk_en,
    input wire [`OP_NUM_WIDTH-1:0] op_num,          
    input wire [`PHASE_ACC_WIDTH-1:0] phase_acc,
    input wire [`PHASE_ACC_WIDTH-1:0] phase_acc_17,
    input wire [`PHASE_ACC_WIDTH-1:0] phase_acc_13,
    input wire [2:0] op_type,    
    output reg [`PHASE_ACC_WIDTH-1:0] rhythm_phase
);	
    localparam RAND_POLYNOMIAL = 'h800302;
    localparam RAND_NUM_WIDTH = 24;
    

    reg [`PHASE_ACC_WIDTH-10-1:0] friend_phase;
    wire [`PHASE_ACC_WIDTH-10-1:0] phase_bit;
    wire [`PHASE_ACC_WIDTH-10-1:0] upper_current_phase;
    reg [`PHASE_ACC_WIDTH-10-1:0] noise_bit;    
    reg [RAND_NUM_WIDTH-1:0] rand_num = 1;
    

    assign upper_current_phase = phase_acc >> 10;
    
    always @ *
        case (op_type)
        `OP_HI_HAT:     friend_phase = phase_acc_17 >> 10;
        `OP_TOP_CYMBAL: friend_phase = phase_acc_13 >> 10;
        default:        friend_phase = 0;
        endcase
            
    assign
        phase_bit = (((upper_current_phase & 'h88) ^ ((upper_current_phase << 5) & 'h80)) |
         ((friend_phase ^ (friend_phase << 2)) & 'h20)) ? 'h02 : 'h00;
     
    always @ *
        case (op_type)
        `OP_HI_HAT:     noise_bit = rand_num[0] << 1;
        `OP_SNARE_DRUM: noise_bit = rand_num[0] << 8;
        default:        noise_bit = 0;
        endcase
    
    always @ *
        case (op_type)
        `OP_NORMAL:     rhythm_phase = phase_acc;
        `OP_BASS_DRUM:  rhythm_phase = phase_acc;
        `OP_HI_HAT:     rhythm_phase = ((phase_bit << 8) | ('h34 << (phase_bit ^ noise_bit))) << 10;
        `OP_TOM_TOM:    rhythm_phase = phase_acc;
        `OP_SNARE_DRUM: rhythm_phase = (('h100 + (upper_current_phase & 'h100)) ^ noise_bit) << 10;
        `OP_TOP_CYMBAL: rhythm_phase = ((1 + phase_bit) << 8) << 10;
        default:        rhythm_phase = phase_acc;
        endcase
            
    always @(posedge clk)

        if (reset)
            rand_num <= 1;
        else if (sample_clk_en && op_num == 0)
            if (rand_num & 1)
                rand_num <= (rand_num ^ RAND_POLYNOMIAL) >> 1;
            else
                rand_num <= rand_num >> 1;  
endmodule
module calc_rhythm_phase (
    input wire clk,
    input wire reset,
    input wire sample_clk_en,
    input wire [`OP_NUM_WIDTH-1:0] op_num,          
    input wire [`PHASE_ACC_WIDTH-1:0] phase_acc,
    input wire [`PHASE_ACC_WIDTH-1:0] phase_acc_17,
    input wire [`PHASE_ACC_WIDTH-1:0] phase_acc_13,
    input wire [2:0] op_type,    
    output reg [`PHASE_ACC_WIDTH-1:0] rhythm_phase
);
	
    localparam RAND_POLYNOMIAL = 'h800302;
    localparam RAND_NUM_WIDTH = 24;
    

    reg [`PHASE_ACC_WIDTH-10-1:0] friend_phase;
    wire [`PHASE_ACC_WIDTH-10-1:0] phase_bit;
    wire [`PHASE_ACC_WIDTH-10-1:0] upper_current_phase;
    reg [`PHASE_ACC_WIDTH-10-1:0] noise_bit;    
    reg [RAND_NUM_WIDTH-1:0] rand_num = 1;
    

    assign upper_current_phase = phase_acc >> 10;
    
    always @ *
        case (op_type)
        `OP_HI_HAT:     friend_phase = phase_acc_17 >> 10;
        `OP_TOP_CYMBAL: friend_phase = phase_acc_13 >> 10;
        default:        friend_phase = 0;
        endcase
            
    assign
        phase_bit = (((upper_current_phase & 'h88) ^ ((upper_current_phase << 5) & 'h80)) |
         ((friend_phase ^ (friend_phase << 2)) & 'h20)) ? 'h02 : 'h00;
     
    always @ *
        case (op_type)
        `OP_HI_HAT:     noise_bit = rand_num[0] << 1;
        `OP_SNARE_DRUM: noise_bit = rand_num[0] << 8;
        default:        noise_bit = 0;
        endcase
    
    always @ *
        case (op_type)
        `OP_NORMAL:     rhythm_phase = phase_acc;
        `OP_BASS_DRUM:  rhythm_phase = phase_acc;
        `OP_HI_HAT:     rhythm_phase = ((phase_bit << 8) | ('h34 << (phase_bit ^ noise_bit))) << 10;
        `OP_TOM_TOM:    rhythm_phase = phase_acc;
        `OP_SNARE_DRUM: rhythm_phase = (('h100 + (upper_current_phase & 'h100)) ^ noise_bit) << 10;
        `OP_TOP_CYMBAL: rhythm_phase = ((1 + phase_bit) << 8) << 10;
        default:        rhythm_phase = phase_acc;
        endcase
            
    always @(posedge clk)

        if (reset)
            rand_num <= 1;
        else if (sample_clk_en && op_num == 0)
            if (rand_num & 1)
                rand_num <= (rand_num ^ RAND_POLYNOMIAL) >> 1;
            else
                rand_num <= rand_num >> 1;  
endmodule