data/full_repos/permissive/455421905/src/hms.v
1: b'%Warning-WIDTH: data/full_repos/permissive/455421905/src/hms.v:490: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'FLOAT\' generates 16 bits.\n                                                                  : ... In instance MERGE_TREE.level[0].nodes[1].merge_node.merge_logic\n      if (FLOAT == "yes" || SIGNED == "yes") begin\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/455421905/src/hms.v:490: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'SIGNED\' generates 16 bits.\n                                                                  : ... In instance MERGE_TREE.level[0].nodes[1].merge_node.merge_logic\n      if (FLOAT == "yes" || SIGNED == "yes") begin\n                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/455421905/src/hms.v:342: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'FLOAT\' generates 16 bits.\n                                                                  : ... In instance MERGE_TREE.level[0].nodes[1].merge_node.merge_logic.merge_network\n      if (FLOAT == "yes" || SIGNED == "yes") begin\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/455421905/src/hms.v:342: Operator EQ expects 24 bits on the LHS, but LHS\'s VARREF \'SIGNED\' generates 16 bits.\n                                                                  : ... In instance MERGE_TREE.level[0].nodes[1].merge_node.merge_logic.merge_network\n      if (FLOAT == "yes" || SIGNED == "yes") begin\n                                   ^~\n%Error: data/full_repos/permissive/455421905/src/hms.v:80: Cannot find file containing module: \'COMPARATOR\'\n  COMPARATOR #(FLOAT, SIGNED, KEYW)\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/COMPARATOR\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/COMPARATOR.v\n             data/full_repos/permissive/455421905/src,data/full_repos/permissive/455421905/COMPARATOR.sv\n             COMPARATOR\n             COMPARATOR.v\n             COMPARATOR.sv\n             obj_dir/COMPARATOR\n             obj_dir/COMPARATOR.v\n             obj_dir/COMPARATOR.sv\n%Error: data/full_repos/permissive/455421905/src/hms.v:564: Cannot find file containing module: \'BS_FIFO\'\n  BS_FIFO #(5, (DATW<<E_LOG), USE_IPCORE)\n  ^~~~~~~\n%Error: data/full_repos/permissive/455421905/src/hms.v:567: Cannot find file containing module: \'BS_FIFO\'\n  BS_FIFO #(5, (DATW<<E_LOG), USE_IPCORE)\n  ^~~~~~~\n%Error: data/full_repos/permissive/455421905/src/hms.v:606: Cannot find file containing module: \'COMPARATOR\'\n      COMPARATOR #(FLOAT, SIGNED, KEYW)\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/455421905/src/hms.v:673: Cannot find file containing module: \'BS_FIFO\'\n  BS_FIFO #(FIFO_SIZE, (DATW<<E_LOG), USE_IPCORE)\n  ^~~~~~~\n%Error: Exiting due to 5 error(s), 4 warning(s)\n'
module MERGE_NODE #(parameter                           E_LOG      = 2,
                    parameter                           USE_IPCORE = "INTEL",
                    parameter                           FLOAT      = "no",
                    parameter                           SIGNED     = "no",
                    parameter                           DATW       = 64,
                    parameter                           KEYW       = 32)
                   (input  wire                         CLK,
                    input  wire                         RST,
                    input  wire                         IN_FULL,
                    input  wire [(DATW<<(E_LOG-1))-1:0] DIN_A,
                    input  wire                         DINEN_A,
                    input  wire [(DATW<<(E_LOG-1))-1:0] DIN_B,
                    input  wire                         DINEN_B,
                    output wire                         FUL_A,
                    output wire                         FUL_B,
                    output wire [(DATW<<E_LOG)-1:0]     DOT,
                    output wire                         DOTEN);

  reg rst;
  always @(posedge CLK) rst <= RST;

  wire [(DATW<<E_LOG)-1:0] coupler_A_dot, coupler_B_dot;
  wire                     coupler_A_doten, coupler_B_doten;

  COUPLER #(E_LOG, DATW)
  coupler_A(CLK, rst, FUL_A, DIN_A, DINEN_A, coupler_A_dot, coupler_A_doten);
  COUPLER #(E_LOG, DATW)
  coupler_B(CLK, rst, FUL_B, DIN_B, DINEN_B, coupler_B_dot, coupler_B_doten);

  MERGE_LOGIC #(E_LOG, USE_IPCORE, FLOAT, SIGNED, DATW, KEYW)
  merge_logic(CLK, rst, IN_FULL, coupler_A_doten, coupler_A_dot, coupler_B_doten, coupler_B_dot,
              FUL_A, FUL_B, DOT, DOTEN);

endmodule
module MERGE_NODE #(parameter                           E_LOG      = 2,
                    parameter                           USE_IPCORE = "INTEL",
                    parameter                           FLOAT      = "no",
                    parameter                           SIGNED     = "no",
                    parameter                           DATW       = 64,
                    parameter                           KEYW       = 32)
                   (input  wire                         CLK,
                    input  wire                         RST,
                    input  wire                         IN_FULL,
                    input  wire [(DATW<<(E_LOG-1))-1:0] DIN_A,
                    input  wire                         DINEN_A,
                    input  wire [(DATW<<(E_LOG-1))-1:0] DIN_B,
                    input  wire                         DINEN_B,
                    output wire                         FUL_A,
                    output wire                         FUL_B,
                    output wire [(DATW<<E_LOG)-1:0]     DOT,
                    output wire                         DOTEN);


  reg rst;
  always @(posedge CLK) rst <= RST;

  wire [(DATW<<E_LOG)-1:0] coupler_A_dot, coupler_B_dot;
  wire                     coupler_A_doten, coupler_B_doten;

  COUPLER #(E_LOG, DATW)
  coupler_A(CLK, rst, FUL_A, DIN_A, DINEN_A, coupler_A_dot, coupler_A_doten);
  COUPLER #(E_LOG, DATW)
  coupler_B(CLK, rst, FUL_B, DIN_B, DINEN_B, coupler_B_dot, coupler_B_doten);

  MERGE_LOGIC #(E_LOG, USE_IPCORE, FLOAT, SIGNED, DATW, KEYW)
  merge_logic(CLK, rst, IN_FULL, coupler_A_doten, coupler_A_dot, coupler_B_doten, coupler_B_dot,
              FUL_A, FUL_B, DOT, DOTEN);

endmodule