data/full_repos/permissive/473423187/hw/rtl/libs/VX_index_queue.sv
1: b'%Error: data/full_repos/permissive/473423187/hw/rtl/libs/VX_index_queue.sv:1: Cannot find include file: VX_platform.vh\n`include "VX_platform.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/473423187/hw/rtl/libs,data/full_repos/permissive/473423187/VX_platform.vh\n             data/full_repos/permissive/473423187/hw/rtl/libs,data/full_repos/permissive/473423187/VX_platform.vh.v\n             data/full_repos/permissive/473423187/hw/rtl/libs,data/full_repos/permissive/473423187/VX_platform.vh.sv\n             VX_platform.vh\n             VX_platform.vh.v\n             VX_platform.vh.sv\n             obj_dir/VX_platform.vh\n             obj_dir/VX_platform.vh.v\n             obj_dir/VX_platform.vh.sv\n%Error: data/full_repos/permissive/473423187/hw/rtl/libs/VX_index_queue.sv:3: Define or directive not defined: \'`TRACING_OFF\'\n`TRACING_OFF\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/libs/VX_index_queue.sv:11: Define or directive not defined: \'`LOG2UP\'\n    output wire [`LOG2UP(SIZE)-1:0] write_addr,\n                 ^~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/libs/VX_index_queue.sv:16: Define or directive not defined: \'`LOG2UP\'\n    input  wire [`LOG2UP(SIZE)-1:0] read_addr,\n                 ^~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/libs/VX_index_queue.sv:21: Define or directive not defined: \'`LOG2UP\'\n    reg [`LOG2UP(SIZE):0] rd_ptr, wr_ptr;\n         ^~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/libs/VX_index_queue.sv:23: Define or directive not defined: \'`LOG2UP\'\n    wire [`LOG2UP(SIZE)-1:0] rd_a, wr_a;\n          ^~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/libs/VX_index_queue.sv:26: Define or directive not defined: \'`LOG2UP\'\n    assign rd_a = rd_ptr[`LOG2UP(SIZE)-1:0];\n                         ^~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/libs/VX_index_queue.sv:27: Define or directive not defined: \'`LOG2UP\'\n    assign wr_a = wr_ptr[`LOG2UP(SIZE)-1:0];    \n                         ^~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/libs/VX_index_queue.sv:30: Define or directive not defined: \'`LOG2UP\'\n    assign full  = (wr_a == rd_a) && (wr_ptr[`LOG2UP(SIZE)] != rd_ptr[`LOG2UP(SIZE)]);\n                                             ^~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/libs/VX_index_queue.sv:30: Define or directive not defined: \'`LOG2UP\'\n    assign full  = (wr_a == rd_a) && (wr_ptr[`LOG2UP(SIZE)] != rd_ptr[`LOG2UP(SIZE)]);\n                                                                      ^~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/libs/VX_index_queue.sv:35: Define or directive not defined: \'`RUNTIME_ASSERT\'\n    `RUNTIME_ASSERT(!push || !full, ("invalid inputs"));\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/libs/VX_index_queue.sv:35: syntax error, unexpected \'(\'\n    `RUNTIME_ASSERT(!push || !full, ("invalid inputs"));\n                    ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/libs/VX_index_queue.sv:64: Define or directive not defined: \'`TRACING_ON\'\n`TRACING_ON\n^~~~~~~~~~~\n%Error: Exiting due to 13 error(s)\n'
module VX_index_queue #(
    parameter DATAW = 1,
    parameter SIZE = 1
) (
    input  wire clk,
    input  wire reset,
    input  wire [DATAW-1:0] write_data,        
    output wire [`LOG2UP(SIZE)-1:0] write_addr,
    input  wire push,    
    input  wire pop,
    output wire full,
    output wire empty,
    input  wire [`LOG2UP(SIZE)-1:0] read_addr,
    output wire [DATAW-1:0] read_data
);
    reg [DATAW-1:0] entries [SIZE-1:0];
    reg [SIZE-1:0] valid;    
    reg [`LOG2UP(SIZE):0] rd_ptr, wr_ptr;

    wire [`LOG2UP(SIZE)-1:0] rd_a, wr_a;
    wire enqueue, dequeue;

    assign rd_a = rd_ptr[`LOG2UP(SIZE)-1:0];
    assign wr_a = wr_ptr[`LOG2UP(SIZE)-1:0];    

    assign empty = (wr_ptr == rd_ptr);
    assign full  = (wr_a == rd_a) && (wr_ptr[`LOG2UP(SIZE)] != rd_ptr[`LOG2UP(SIZE)]);

    assign enqueue = push;       
    assign dequeue = !empty && !valid[rd_a];

    `RUNTIME_ASSERT(!push || !full, ("invalid inputs"));
    
    always @(posedge clk) begin
        if (reset) begin
            rd_ptr <= 0;
            wr_ptr <= 0;
            valid  <= 0;     
        end else begin
            if (enqueue)  begin
                valid[wr_a] <= 1;
                wr_ptr      <= wr_ptr + 1;
            end            
            if (dequeue) begin
                rd_ptr <= rd_ptr + 1;
            end
            if (pop) begin
                valid[read_addr] <= 0;
            end
        end

        if (enqueue)  begin
            entries[wr_a] <= write_data;
        end  
    end

    assign write_addr = wr_a;
    assign read_data = entries[read_addr];

endmodule
module VX_index_queue #(
    parameter DATAW = 1,
    parameter SIZE = 1
) (
    input  wire clk,
    input  wire reset,
    input  wire [DATAW-1:0] write_data,        
    output wire [`LOG2UP(SIZE)-1:0] write_addr,
    input  wire push,    
    input  wire pop,
    output wire full,
    output wire empty,
    input  wire [`LOG2UP(SIZE)-1:0] read_addr,
    output wire [DATAW-1:0] read_data
);

    reg [DATAW-1:0] entries [SIZE-1:0];
    reg [SIZE-1:0] valid;    
    reg [`LOG2UP(SIZE):0] rd_ptr, wr_ptr;

    wire [`LOG2UP(SIZE)-1:0] rd_a, wr_a;
    wire enqueue, dequeue;

    assign rd_a = rd_ptr[`LOG2UP(SIZE)-1:0];
    assign wr_a = wr_ptr[`LOG2UP(SIZE)-1:0];    

    assign empty = (wr_ptr == rd_ptr);
    assign full  = (wr_a == rd_a) && (wr_ptr[`LOG2UP(SIZE)] != rd_ptr[`LOG2UP(SIZE)]);

    assign enqueue = push;       
    assign dequeue = !empty && !valid[rd_a];

    `RUNTIME_ASSERT(!push || !full, ("invalid inputs"));
    
    always @(posedge clk) begin
        if (reset) begin
            rd_ptr <= 0;
            wr_ptr <= 0;
            valid  <= 0;     
        end else begin
            if (enqueue)  begin
                valid[wr_a] <= 1;
                wr_ptr      <= wr_ptr + 1;
            end            
            if (dequeue) begin
                rd_ptr <= rd_ptr + 1;
            end
            if (pop) begin
                valid[read_addr] <= 0;
            end
        end

        if (enqueue)  begin
            entries[wr_a] <= write_data;
        end  
    end

    assign write_addr = wr_a;
    assign read_data = entries[read_addr];

endmodule