data/full_repos/permissive/446312960/Verilog_Simulation/15_1bit_alu/alu1bit_test.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/15_1bit_alu/alu1bit_test.v:25: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/15_1bit_alu/alu1bit_test.v:32: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/15_1bit_alu/alu1bit_test.v:39: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/446312960/Verilog_Simulation/15_1bit_alu/alu1bit_test.v:46: Unsupported: Ignoring delay on this delayed statement.\n   #100;\n   ^\n%Error: Exiting due to 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu1bit_test(t1, t2, t3, t4, t5, p1, p2);

input  p1,  p2;


output   t1, t2,  t3, t4, t5;   

reg t1, t2, t3, t4, t5;









initial begin
   t1 <= 1'b0;
   t2 <= 1'b1;
   t3 <= 1'b1;
   t4 <= 1'b0;
   t5 <= 1'b0;

   #100;
   t1 <= 1'b0;
   t2 <= 1'b1;
   t3 <= 1'b1;
   t4 <= 1'b0;
   t5 <= 1'b1;

   #100;
   t1 <= 1'b0;
   t2 <= 1'b1;
   t3 <= 1'b1;
   t4 <= 1'b1;
   t5 <= 1'b0;

   #100;
   t1 <= 1'b0;
   t2 <= 1'b1;
   t3 <= 1'b1;
   t4 <= 1'b1;
   t5 <= 1'b1;
  
   #100;
   $finish;
end

endmodule
module alu1bit_test(t1, t2, t3, t4, t5, p1, p2);


input  p1,  p2;


output   t1, t2,  t3, t4, t5;   

reg t1, t2, t3, t4, t5;









initial begin
   t1 <= 1'b0;
   t2 <= 1'b1;
   t3 <= 1'b1;
   t4 <= 1'b0;
   t5 <= 1'b0;

   #100;
   t1 <= 1'b0;
   t2 <= 1'b1;
   t3 <= 1'b1;
   t4 <= 1'b0;
   t5 <= 1'b1;

   #100;
   t1 <= 1'b0;
   t2 <= 1'b1;
   t3 <= 1'b1;
   t4 <= 1'b1;
   t5 <= 1'b0;

   #100;
   t1 <= 1'b0;
   t2 <= 1'b1;
   t3 <= 1'b1;
   t4 <= 1'b1;
   t5 <= 1'b1;
  
   #100;
   $finish;
end

endmodule