data/full_repos/permissive/407995710/Source files/SPI_SLAVE.v
1: b'%Error: Cannot find file containing module: files,data/full_repos/permissive/407995710\n        ... Looked in:\n             data/full_repos/permissive/407995710/Source/files,data/full_repos/permissive/407995710\n             data/full_repos/permissive/407995710/Source/files,data/full_repos/permissive/407995710.v\n             data/full_repos/permissive/407995710/Source/files,data/full_repos/permissive/407995710.sv\n             files,data/full_repos/permissive/407995710\n             files,data/full_repos/permissive/407995710.v\n             files,data/full_repos/permissive/407995710.sv\n             obj_dir/files,data/full_repos/permissive/407995710\n             obj_dir/files,data/full_repos/permissive/407995710.v\n             obj_dir/files,data/full_repos/permissive/407995710.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/407995710/Source\n%Error: Cannot find file containing module: files/SPI_SLAVE.v\n%Error: Exiting due to 3 error(s)\n'
module Slave
(
	input reset,
	input [7:0]slaveDataToSend, 
	output [7:0]slaveDataReceived,
	input SCLK, CS, MOSI,
	output reg MISO
);
integer counter;
reg [7:0] SDS;
reg [7:0] SDR;

wire [7:0] SDS_next;
wire [7:0] SDR_next;

always @ (negedge CS)
begin
	counter = 0;
	SDS = slaveDataToSend;
	MISO = SDS[7];
end

always @(posedge SCLK , posedge reset)
begin
if(reset==1'b1)
begin
	SDS=slaveDataToSend;
	SDR=0;
	counter = 0;
	MISO = 1'bz;
end
else
begin 
	SDR=SDR_next;
	SDS=SDS_next;
	counter = counter+1;
end

end
assign SDS_next = (CS==1'b0&&counter<=8 &&counter >0)?{ SDS[6:0],1'b0 }:SDS;
assign SDR_next = (CS==1'b0&&counter<=8 )?{SDR[6:0],MOSI}:SDR;
assign MISO = (CS==1'b0)? SDS[7]:1'bz;
assign slaveDataReceived = SDR;


endmodule
module Slave
(
	input reset,
	input [7:0]slaveDataToSend, 
	output [7:0]slaveDataReceived,
	input SCLK, CS, MOSI,
	output reg MISO
);

integer counter;
reg [7:0] SDS;
reg [7:0] SDR;

wire [7:0] SDS_next;
wire [7:0] SDR_next;

always @ (negedge CS)
begin
	counter = 0;
	SDS = slaveDataToSend;
	MISO = SDS[7];
end

always @(posedge SCLK , posedge reset)
begin
if(reset==1'b1)
begin
	SDS=slaveDataToSend;
	SDR=0;
	counter = 0;
	MISO = 1'bz;
end
else
begin 
	SDR=SDR_next;
	SDS=SDS_next;
	counter = counter+1;
end

end
assign SDS_next = (CS==1'b0&&counter<=8 &&counter >0)?{ SDS[6:0],1'b0 }:SDS;
assign SDR_next = (CS==1'b0&&counter<=8 )?{SDR[6:0],MOSI}:SDR;
assign MISO = (CS==1'b0)? SDS[7]:1'bz;
assign slaveDataReceived = SDR;


endmodule