data/full_repos/permissive/437632408/NVDLA/nvdla/cdp/NV_NVDLA_CDP_DP_MUL_unit.v
1: b"%Error: data/full_repos/permissive/437632408/NVDLA/nvdla/cdp/NV_NVDLA_CDP_DP_MUL_unit.v:139: Cannot find file containing module: 'HLS_fp17_mul'\nHLS_fp17_mul u_fp_mul (\n^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/437632408/NVDLA/nvdla/cdp,data/full_repos/permissive/437632408/HLS_fp17_mul\n             data/full_repos/permissive/437632408/NVDLA/nvdla/cdp,data/full_repos/permissive/437632408/HLS_fp17_mul.v\n             data/full_repos/permissive/437632408/NVDLA/nvdla/cdp,data/full_repos/permissive/437632408/HLS_fp17_mul.sv\n             HLS_fp17_mul\n             HLS_fp17_mul.v\n             HLS_fp17_mul.sv\n             obj_dir/HLS_fp17_mul\n             obj_dir/HLS_fp17_mul.v\n             obj_dir/HLS_fp17_mul.sv\n%Error: Exiting due to 1 error(s)\n"
module NV_NVDLA_CDP_DP_MUL_unit (
   nvdla_core_clk
  ,nvdla_op_gated_clk_int
  ,nvdla_core_rstn
  ,datin_pd
  ,fp16_en
  ,intp2mul_pd_0
  ,intp2mul_pd_1
  ,mul_unit_rdy
  ,mul_vld
  ,nvdla_op_gated_clk_fp16
  ,reg2dp_input_data_type
  ,mul_rdy
  ,mul_unit_pd
  ,mul_unit_vld
  );
input nvdla_core_clk;
input nvdla_op_gated_clk_int;
input nvdla_core_rstn;
input [17:0] datin_pd;
input fp16_en;
input [16:0] intp2mul_pd_0;
input [16:0] intp2mul_pd_1;
input mul_unit_rdy;
input mul_vld;
input nvdla_op_gated_clk_fp16;
input [1:0] reg2dp_input_data_type;
output mul_rdy;
output [49:0] mul_unit_pd;
output mul_unit_vld;
reg fp16_en_sync;
reg int16_en_use;
reg int8_en_f;
reg [32:0] mul_int_lsb;
reg [24:0] mul_int_msb;
reg mul_int_vld_d0;
wire [16:0] datin_pd_lsb;
wire fp_mul_a_rdy;
wire fp_mul_a_vld;
wire fp_mul_b_rdy;
wire fp_mul_b_vld;
wire [16:0] fp_mul_pd;
wire fp_mul_rdy;
wire fp_mul_vld;
wire [16:0] intp2mul_msb;
wire mul_fp_rdy;
wire mul_fp_vld;
wire [24:0] mul_int8_msb;
wire mul_int_load;
wire mul_int_rdy;
wire mul_int_rdy_d0;
wire mul_int_vld;













always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    int16_en_use <= 1'b0;
  end else begin
  int16_en_use <= reg2dp_input_data_type[1:0] == 1;
  end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    fp16_en_sync <= 1'b0;
  end else begin
  fp16_en_sync <= fp16_en;
  end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    int8_en_f <= 1'b0;
  end else begin
  int8_en_f <= reg2dp_input_data_type[1:0] == 0;
  end
end
assign mul_rdy = fp16_en_sync ? mul_fp_rdy : mul_int_rdy;





assign mul_int_vld = fp16_en_sync ? 1'b0 : mul_vld;
assign mul_int_rdy = ~mul_int_vld_d0 | mul_int_rdy_d0;
assign mul_int_load = mul_int_vld & mul_int_rdy;
assign datin_pd_lsb = int8_en_f ? {{8{datin_pd[8]}},datin_pd[8:0]} : (int16_en_use ? datin_pd[16:0] : 17'd0);
assign intp2mul_msb = intp2mul_pd_1[16:0];
assign mul_int8_msb[24:0] = $signed(intp2mul_msb[15:0]) * $signed(datin_pd[17:9]);
always @(posedge nvdla_op_gated_clk_int or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    mul_int_lsb[32:0] <= {33{1'b0}};
    mul_int_msb[24:0] <= {25{1'b0}};
  end else begin
    if(mul_int_load) begin
        mul_int_lsb[32:0] <= $signed(intp2mul_pd_0[15:0]) * $signed(datin_pd_lsb);

        mul_int_msb[24:0] <= int8_en_f ? mul_int8_msb : 25'd0;
    end
  end
end
always @(posedge nvdla_op_gated_clk_int or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    mul_int_vld_d0 <= 1'b0;
  end else begin
    if(mul_int_vld)
        mul_int_vld_d0 <= 1'b1;
    else if(mul_int_rdy_d0)
        mul_int_vld_d0 <= 1'b0;
  end
end





assign mul_fp_vld = fp16_en_sync ? mul_vld : 1'b0;
assign mul_fp_rdy = fp_mul_a_rdy & fp_mul_b_rdy;

assign fp_mul_a_vld = mul_fp_vld & fp_mul_b_rdy;
assign fp_mul_b_vld = mul_fp_vld & fp_mul_a_rdy;
HLS_fp17_mul u_fp_mul (
   .nvdla_core_clk (nvdla_op_gated_clk_fp16)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.chn_a_rsc_z (datin_pd[16:0])
  ,.chn_a_rsc_vz (fp_mul_a_vld)
  ,.chn_a_rsc_lz (fp_mul_a_rdy)
  ,.chn_b_rsc_z (intp2mul_pd_0[16:0])
  ,.chn_b_rsc_vz (fp_mul_b_vld)
  ,.chn_b_rsc_lz (fp_mul_b_rdy)
  ,.chn_o_rsc_z (fp_mul_pd[16:0])
  ,.chn_o_rsc_vz (fp_mul_rdy)
  ,.chn_o_rsc_lz (fp_mul_vld)
  );




assign fp_mul_rdy = fp16_en_sync ? mul_unit_rdy : 1'b1;
assign mul_int_rdy_d0 = fp16_en_sync ? 1'b1 : mul_unit_rdy;
assign mul_unit_vld = fp16_en_sync ? fp_mul_vld : mul_int_vld_d0;
assign mul_unit_pd = fp16_en_sync ? {{33{fp_mul_pd[16]}},fp_mul_pd} : (int16_en_use ? {{17{mul_int_lsb[32]}},mul_int_lsb[32:0]} : {mul_int_msb[24:0],mul_int_lsb[24:0]});

endmodule
module NV_NVDLA_CDP_DP_MUL_unit (
   nvdla_core_clk
  ,nvdla_op_gated_clk_int
  ,nvdla_core_rstn
  ,datin_pd
  ,fp16_en
  ,intp2mul_pd_0
  ,intp2mul_pd_1
  ,mul_unit_rdy
  ,mul_vld
  ,nvdla_op_gated_clk_fp16
  ,reg2dp_input_data_type
  ,mul_rdy
  ,mul_unit_pd
  ,mul_unit_vld
  );

input nvdla_core_clk;
input nvdla_op_gated_clk_int;
input nvdla_core_rstn;
input [17:0] datin_pd;
input fp16_en;
input [16:0] intp2mul_pd_0;
input [16:0] intp2mul_pd_1;
input mul_unit_rdy;
input mul_vld;
input nvdla_op_gated_clk_fp16;
input [1:0] reg2dp_input_data_type;
output mul_rdy;
output [49:0] mul_unit_pd;
output mul_unit_vld;
reg fp16_en_sync;
reg int16_en_use;
reg int8_en_f;
reg [32:0] mul_int_lsb;
reg [24:0] mul_int_msb;
reg mul_int_vld_d0;
wire [16:0] datin_pd_lsb;
wire fp_mul_a_rdy;
wire fp_mul_a_vld;
wire fp_mul_b_rdy;
wire fp_mul_b_vld;
wire [16:0] fp_mul_pd;
wire fp_mul_rdy;
wire fp_mul_vld;
wire [16:0] intp2mul_msb;
wire mul_fp_rdy;
wire mul_fp_vld;
wire [24:0] mul_int8_msb;
wire mul_int_load;
wire mul_int_rdy;
wire mul_int_rdy_d0;
wire mul_int_vld;













always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    int16_en_use <= 1'b0;
  end else begin
  int16_en_use <= reg2dp_input_data_type[1:0] == 1;
  end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    fp16_en_sync <= 1'b0;
  end else begin
  fp16_en_sync <= fp16_en;
  end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    int8_en_f <= 1'b0;
  end else begin
  int8_en_f <= reg2dp_input_data_type[1:0] == 0;
  end
end
assign mul_rdy = fp16_en_sync ? mul_fp_rdy : mul_int_rdy;





assign mul_int_vld = fp16_en_sync ? 1'b0 : mul_vld;
assign mul_int_rdy = ~mul_int_vld_d0 | mul_int_rdy_d0;
assign mul_int_load = mul_int_vld & mul_int_rdy;
assign datin_pd_lsb = int8_en_f ? {{8{datin_pd[8]}},datin_pd[8:0]} : (int16_en_use ? datin_pd[16:0] : 17'd0);
assign intp2mul_msb = intp2mul_pd_1[16:0];
assign mul_int8_msb[24:0] = $signed(intp2mul_msb[15:0]) * $signed(datin_pd[17:9]);
always @(posedge nvdla_op_gated_clk_int or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    mul_int_lsb[32:0] <= {33{1'b0}};
    mul_int_msb[24:0] <= {25{1'b0}};
  end else begin
    if(mul_int_load) begin
        mul_int_lsb[32:0] <= $signed(intp2mul_pd_0[15:0]) * $signed(datin_pd_lsb);

        mul_int_msb[24:0] <= int8_en_f ? mul_int8_msb : 25'd0;
    end
  end
end
always @(posedge nvdla_op_gated_clk_int or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    mul_int_vld_d0 <= 1'b0;
  end else begin
    if(mul_int_vld)
        mul_int_vld_d0 <= 1'b1;
    else if(mul_int_rdy_d0)
        mul_int_vld_d0 <= 1'b0;
  end
end





assign mul_fp_vld = fp16_en_sync ? mul_vld : 1'b0;
assign mul_fp_rdy = fp_mul_a_rdy & fp_mul_b_rdy;

assign fp_mul_a_vld = mul_fp_vld & fp_mul_b_rdy;
assign fp_mul_b_vld = mul_fp_vld & fp_mul_a_rdy;
HLS_fp17_mul u_fp_mul (
   .nvdla_core_clk (nvdla_op_gated_clk_fp16)
  ,.nvdla_core_rstn (nvdla_core_rstn)
  ,.chn_a_rsc_z (datin_pd[16:0])
  ,.chn_a_rsc_vz (fp_mul_a_vld)
  ,.chn_a_rsc_lz (fp_mul_a_rdy)
  ,.chn_b_rsc_z (intp2mul_pd_0[16:0])
  ,.chn_b_rsc_vz (fp_mul_b_vld)
  ,.chn_b_rsc_lz (fp_mul_b_rdy)
  ,.chn_o_rsc_z (fp_mul_pd[16:0])
  ,.chn_o_rsc_vz (fp_mul_rdy)
  ,.chn_o_rsc_lz (fp_mul_vld)
  );




assign fp_mul_rdy = fp16_en_sync ? mul_unit_rdy : 1'b1;
assign mul_int_rdy_d0 = fp16_en_sync ? 1'b1 : mul_unit_rdy;
assign mul_unit_vld = fp16_en_sync ? fp_mul_vld : mul_int_vld_d0;
assign mul_unit_pd = fp16_en_sync ? {{33{fp_mul_pd[16]}},fp_mul_pd} : (int16_en_use ? {{17{mul_int_lsb[32]}},mul_int_lsb[32:0]} : {mul_int_msb[24:0],mul_int_lsb[24:0]});

endmodule