data/full_repos/permissive/52900389/TB_traductr.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/52900389/TB_traductr.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/52900389/TB_traductr.v:55: Unsupported: Ignoring delay on this delayed statement.\n always #10 clk=~clk;\n        ^\n%Error: data/full_repos/permissive/52900389/TB_traductr.v:36: Cannot find file containing module: \'Traductor\'\n Traductor uut (\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52900389,data/full_repos/permissive/52900389/Traductor\n             data/full_repos/permissive/52900389,data/full_repos/permissive/52900389/Traductor.v\n             data/full_repos/permissive/52900389,data/full_repos/permissive/52900389/Traductor.sv\n             Traductor\n             Traductor.v\n             Traductor.sv\n             obj_dir/Traductor\n             obj_dir/Traductor.v\n             obj_dir/Traductor.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TB_traductr;


	reg [3:0] in;
	reg clk;
	reg rst;


	wire [15:0] out;


	Traductor uut (
		.in(in), 
		.out(out), 
		.clk(clk), 
		.rst(rst)
	);

	initial begin

		in = 4'b0010;
		clk = 0;
		rst = 0;


		#100;
        


	end
	always #10 clk=~clk;
      
endmodule
module TB_traductr;



	reg [3:0] in;
	reg clk;
	reg rst;


	wire [15:0] out;


	Traductor uut (
		.in(in), 
		.out(out), 
		.clk(clk), 
		.rst(rst)
	);

	initial begin

		in = 4'b0010;
		clk = 0;
		rst = 0;


		#100;
        


	end
	always #10 clk=~clk;
      
endmodule