data/full_repos/permissive/449071180/tb_snake_game.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_snake_game.v:27: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_snake_game.v:29: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_snake_game.v:31: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_snake_game.v:41: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Warning-STMTDLY: data/full_repos/permissive/449071180/tb_snake_game.v:43: Unsupported: Ignoring delay on this delayed statement.\n#20;\n^\n%Error: data/full_repos/permissive/449071180/tb_snake_game.v:7: Cannot find file containing module: \'snake_game\'\nsnake_game port_map(\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/snake_game\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/snake_game.v\n             data/full_repos/permissive/449071180,data/full_repos/permissive/449071180/snake_game.sv\n             snake_game\n             snake_game.v\n             snake_game.sv\n             obj_dir/snake_game\n             obj_dir/snake_game.v\n             obj_dir/snake_game.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_snake_game();

reg reset_master_test,left_test,right_test,up_test,down_test,clk_master_test;
wire [7:0] out_cathode_test,out_anode_test;

snake_game port_map(

.reset_master(reset_master_test),
.left(left_test),
.right(right_test),
.up(up_test),
.down(down_test),
.clk_master(clk_master_test),
.out_cathode(out_cathode_test),
.out_anode(out_anode_test)

);

initial begin
reset_master_test = 1'b0;
left_test = 1'b1;
right_test = 1'b1;
up_test = 1'b1;
down_test = 1'b1;
clk_master_test = 1'b0;
#20;
reset_master_test = 1'b1;
#20;
reset_master_test = 1'b0;
#20;

end

always begin
left_test = 1'b1;
right_test = 1'b0;
up_test = 1'b1;
down_test = 1'b1;
clk_master_test = 0;
#20;
clk_master_test = 1;
#20;


end

endmodule
module tb_snake_game();


reg reset_master_test,left_test,right_test,up_test,down_test,clk_master_test;
wire [7:0] out_cathode_test,out_anode_test;

snake_game port_map(

.reset_master(reset_master_test),
.left(left_test),
.right(right_test),
.up(up_test),
.down(down_test),
.clk_master(clk_master_test),
.out_cathode(out_cathode_test),
.out_anode(out_anode_test)

);

initial begin
reset_master_test = 1'b0;
left_test = 1'b1;
right_test = 1'b1;
up_test = 1'b1;
down_test = 1'b1;
clk_master_test = 1'b0;
#20;
reset_master_test = 1'b1;
#20;
reset_master_test = 1'b0;
#20;

end

always begin
left_test = 1'b1;
right_test = 1'b0;
up_test = 1'b1;
down_test = 1'b1;
clk_master_test = 0;
#20;
clk_master_test = 1;
#20;


end

endmodule