data/full_repos/permissive/453763315/testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/453763315/testbench.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/453763315/testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #1\n    ^\n%Error: data/full_repos/permissive/453763315/testbench.v:36: syntax error, unexpected end\n  end\n  ^~~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module test();

  reg clk = 1'b0;
  reg regArrayEn, regArrayWe;
  reg [4:0] sela, selb;
  reg [7:0] reada, readb, write;
  reg [3:0] aluSel;
  reg [2:0] flags;
  reg aluEn;





  initial begin
    $display("Running!");
  	regArrayEn <= 1'b1;
  	regArrayWe <= 1'b1;

  	sela <= 4'h0;
  	write <= 8'h01;

    clk <= ~clk;
    #1
    sela <= 4'h1;
    selb <= 4'h0;
    write <= 8'h01;

    clk <= ~clk;
    #1
    regArrayWe <= 1'b0;

    clk <= ~clk;
    #1

  end
endmodule
module test();


  reg clk = 1'b0;
  reg regArrayEn, regArrayWe;
  reg [4:0] sela, selb;
  reg [7:0] reada, readb, write;
  reg [3:0] aluSel;
  reg [2:0] flags;
  reg aluEn;





  initial begin
    $display("Running!");
  	regArrayEn <= 1'b1;
  	regArrayWe <= 1'b1;

  	sela <= 4'h0;
  	write <= 8'h01;

    clk <= ~clk;
    #1
    sela <= 4'h1;
    selb <= 4'h0;
    write <= 8'h01;

    clk <= ~clk;
    #1
    regArrayWe <= 1'b0;

    clk <= ~clk;
    #1

  end
endmodule