data/full_repos/permissive/506636840/block_level_tbs/gpio_tb/tb/top_tb.sv
1: b'%Error: data/full_repos/permissive/506636840/block_level_tbs/gpio_tb/tb/top_tb.sv:3: Cannot find include file: gpio_defines.v\n    `include "gpio_defines.v" \n             ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/506636840/block_level_tbs/gpio_tb/tb,data/full_repos/permissive/506636840/gpio_defines.v\n             data/full_repos/permissive/506636840/block_level_tbs/gpio_tb/tb,data/full_repos/permissive/506636840/gpio_defines.v.v\n             data/full_repos/permissive/506636840/block_level_tbs/gpio_tb/tb,data/full_repos/permissive/506636840/gpio_defines.v.sv\n             gpio_defines.v\n             gpio_defines.v.v\n             gpio_defines.v.sv\n             obj_dir/gpio_defines.v\n             obj_dir/gpio_defines.v.v\n             obj_dir/gpio_defines.v.sv\n%Error: data/full_repos/permissive/506636840/block_level_tbs/gpio_tb/tb/top_tb.sv:4: Cannot find include file: timescale.v\n    `include "timescale.v" \n             ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/506636840/block_level_tbs/gpio_tb/tb/top_tb.sv:6: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n    import uvm_pkg::*;\n           ^~~~~~~\n%Error: data/full_repos/permissive/506636840/block_level_tbs/gpio_tb/tb/top_tb.sv:50: syntax error, unexpected \'#\'\n        uvm_config_db #(virtual apb_if) ::set(null,"uvm_test_top","APB_vif" , APB);\n                      ^\n%Warning-STMTDLY: data/full_repos/permissive/506636840/block_level_tbs/gpio_tb/tb/top_tb.sv:64: Unsupported: Ignoring delay on this delayed statement.\n            #10ns PCLK = ~PCLK;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/506636840/block_level_tbs/gpio_tb/tb/top_tb.sv:68: Unsupported: Ignoring delay on this delayed statement.\n            #10ns PCLK = ~PCLK;\n            ^\n%Error: Exiting due to 4 error(s), 2 warning(s)\n'
module top_tb;

    `include "gpio_defines.v"
    `include "timescale.v"

    import uvm_pkg::*;
    import gpio_rgm_test_lib_pkg::*;

    logic PCLK;
    logic PRESETn;

    apb_if APB(PCLK, PRESETn);
    gpio_if GPO();
    gpio_if GPOE();
    gpio_if GPI();
    gpio_if AUX();
    intr_if INTR();

    gpio_top DUT(

    .PCLK(PCLK),
    .PRESETN(PRESETn),
    .PSEL(APB.PSEL[0]),
    .PADDR(APB.PADDR[7:0]),
    .PWDATA(APB.PWDATA),
    .PRDATA(APB.PRDATA),
    .PENABLE(APB.PENABLE),
    .PREADY(APB.PREADY),
    .PSLVERR(),
    .PWRITE(APB.PWRITE),


    .IRQ(INTR.IRQ),

    `ifdef GPIO_AUX_IMPLEMENT

    .aux_i(AUX.gpio),
    `endif


    .ext_pad_i(GPI.gpio),
    .ext_pad_o(GPO.gpio),
    .ext_padoe_o(GPOE.gpio)
    `ifdef GPIO_CLKPAD
    , .clk_pad_i(GPI.ext_clk)
    `endif
    );

    initial begin
        uvm_config_db #(virtual apb_if) ::set(null,"uvm_test_top","APB_vif" , APB);
        uvm_config_db #(virtual gpio_if)::set(null,"uvm_test_top","GPO_vif" , GPO);
        uvm_config_db #(virtual gpio_if)::set(null,"uvm_test_top","GPOE_vif", GPOE);
        uvm_config_db #(virtual gpio_if)::set(null,"uvm_test_top","GPI_vif" , GPI);
        uvm_config_db #(virtual gpio_if)::set(null,"uvm_test_top","AUX_vif" , AUX);
        uvm_config_db #(virtual intr_if)::set(null,"uvm_test_top","INTR_vif", INTR);
        run_test();
        $finish;
    end

    initial begin
        PCLK = 0;
        PRESETn = 0;
        repeat(8) begin
            #10ns PCLK = ~PCLK;
        end
        PRESETn = 1;
        forever begin
            #10ns PCLK = ~PCLK;
        end
    end

    assign GPO.clk = PCLK;
    assign GPOE.clk = PCLK;
    assign AUX.clk = PCLK;
    assign GPI.clk = PCLK;
endmodule
module top_tb;


    `include "gpio_defines.v"
    `include "timescale.v"

    import uvm_pkg::*;
    import gpio_rgm_test_lib_pkg::*;

    logic PCLK;
    logic PRESETn;

    apb_if APB(PCLK, PRESETn);
    gpio_if GPO();
    gpio_if GPOE();
    gpio_if GPI();
    gpio_if AUX();
    intr_if INTR();

    gpio_top DUT(

    .PCLK(PCLK),
    .PRESETN(PRESETn),
    .PSEL(APB.PSEL[0]),
    .PADDR(APB.PADDR[7:0]),
    .PWDATA(APB.PWDATA),
    .PRDATA(APB.PRDATA),
    .PENABLE(APB.PENABLE),
    .PREADY(APB.PREADY),
    .PSLVERR(),
    .PWRITE(APB.PWRITE),


    .IRQ(INTR.IRQ),

    `ifdef GPIO_AUX_IMPLEMENT

    .aux_i(AUX.gpio),
    `endif


    .ext_pad_i(GPI.gpio),
    .ext_pad_o(GPO.gpio),
    .ext_padoe_o(GPOE.gpio)
    `ifdef GPIO_CLKPAD
    , .clk_pad_i(GPI.ext_clk)
    `endif
    );

    initial begin
        uvm_config_db #(virtual apb_if) ::set(null,"uvm_test_top","APB_vif" , APB);
        uvm_config_db #(virtual gpio_if)::set(null,"uvm_test_top","GPO_vif" , GPO);
        uvm_config_db #(virtual gpio_if)::set(null,"uvm_test_top","GPOE_vif", GPOE);
        uvm_config_db #(virtual gpio_if)::set(null,"uvm_test_top","GPI_vif" , GPI);
        uvm_config_db #(virtual gpio_if)::set(null,"uvm_test_top","AUX_vif" , AUX);
        uvm_config_db #(virtual intr_if)::set(null,"uvm_test_top","INTR_vif", INTR);
        run_test();
        $finish;
    end

    initial begin
        PCLK = 0;
        PRESETn = 0;
        repeat(8) begin
            #10ns PCLK = ~PCLK;
        end
        PRESETn = 1;
        forever begin
            #10ns PCLK = ~PCLK;
        end
    end

    assign GPO.clk = PCLK;
    assign GPOE.clk = PCLK;
    assign AUX.clk = PCLK;
    assign GPI.clk = PCLK;
endmodule