data/full_repos/permissive/469300759/verilog/rtl/sync_reg.v
1: b'%Warning-WIDTH: data/full_repos/permissive/469300759/verilog/rtl/sync_reg.v:40: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h7\' generates 3 bits.\n                                                                              : ... In instance sync_n\n      signal_state <= 3\'b111;\n                   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/469300759/verilog/rtl/sync_reg.v:48: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                              : ... In instance sync_n\n  assign signal_sn = signal_state == 3\'b000 ? 1\'b0:1\'b1;\n                                  ^~\n%Error: Exiting due to 2 warning(s)\n'
module sync_n(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif
  input wire signal_n,
  output wire signal_sn,
  input wire clock
);
  reg [3:0] signal_state;

  always@(posedge clock)
  begin
    if(signal_n)
    begin
      signal_state <= 3'b111;
    end
    else
    begin
      signal_state <= {signal_state[2:0],signal_n};
    end
  end

  assign signal_sn = signal_state == 3'b000 ? 1'b0:1'b1;


endmodule
module sync_n(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif
  input wire signal_n,
  output wire signal_sn,
  input wire clock
);

  reg [3:0] signal_state;

  always@(posedge clock)
  begin
    if(signal_n)
    begin
      signal_state <= 3'b111;
    end
    else
    begin
      signal_state <= {signal_state[2:0],signal_n};
    end
  end

  assign signal_sn = signal_state == 3'b000 ? 1'b0:1'b1;


endmodule