data/full_repos/permissive/445140913/RTL/radix2.v
1: b'%Warning-WIDTH: data/full_repos/permissive/445140913/RTL/radix2.v:65: Operator SUB expects 42 bits on the LHS, but LHS\'s VARREF \'w_r\' generates 24 bits.\n                                                                    : ... In instance radix2\n  inter = b * (w_r - w_i);  \n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/445140913/RTL/radix2.v:65: Operator SUB expects 42 bits on the RHS, but RHS\'s VARREF \'w_i\' generates 24 bits.\n                                                                    : ... In instance radix2\n  inter = b * (w_r - w_i);  \n                   ^\n%Warning-WIDTH: data/full_repos/permissive/445140913/RTL/radix2.v:66: Operator SUB expects 42 bits on the LHS, but LHS\'s VARREF \'a\' generates 24 bits.\n                                                                    : ... In instance radix2\n  mul_r  = w_r * (a - b) + inter;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/445140913/RTL/radix2.v:66: Operator SUB expects 42 bits on the RHS, but RHS\'s VARREF \'b\' generates 24 bits.\n                                                                    : ... In instance radix2\n  mul_r  = w_r * (a - b) + inter;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/445140913/RTL/radix2.v:67: Operator ADD expects 42 bits on the LHS, but LHS\'s VARREF \'a\' generates 24 bits.\n                                                                    : ... In instance radix2\n  mul_i  = w_i * (a + b) + inter;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/445140913/RTL/radix2.v:67: Operator ADD expects 42 bits on the RHS, but RHS\'s VARREF \'b\' generates 24 bits.\n                                                                    : ... In instance radix2\n  mul_i  = w_i * (a + b) + inter;\n                    ^\n%Error: Exiting due to 6 warning(s)\n'
module radix2(
		input wire [1:0] state,
		input wire signed [23:0] din_a_r,
		input wire signed [23:0] din_a_i,
		input wire signed [23:0] din_b_r,
		input wire signed [23:0] din_b_i,
		input wire signed [23:0] w_r,
		input wire signed [23:0] w_i,
		output reg signed[23:0] op_r,
		output reg signed[23:0] op_i,
		output reg signed[23:0] delay_r,
		output reg signed[23:0] delay_i,
		output reg outvalid
	);

	reg signed [41:0] inter,mul_r,mul_i;
	reg signed [23:0] a,b,c,d;

	always@(*)begin
		op_r = 0;
		op_i = 0;
		delay_r = din_b_r;
		delay_i = din_b_i;
		case(state)
		2'b00:begin

		delay_r = din_b_r;
		delay_i = din_b_i;
		outvalid = 1'b0;
		end
		2'b01:begin

		a = din_a_r + din_b_r;
		b = din_a_i + din_b_i;
		
		c = (din_a_r - din_b_r);
		d = (din_a_i - din_b_i);

		op_r = a;
		op_i = b;
		delay_r = c;
		delay_i = d;
		outvalid = 1'b1;
		end
		2'b10:begin

		a = din_a_r;
		b = din_a_i;
		delay_r = din_b_r;
		delay_i = din_b_i;

		inter = b * (w_r - w_i);
		mul_r  = w_r * (a - b) + inter;
		mul_i  = w_i * (a + b) + inter;

		op_r = (mul_r[31:8]);
		op_i = (mul_i[31:8]);
		outvalid = 1'b1;
		end
		2'b11:begin

		outvalid = 1'b0;
		end
		default:begin
		delay_r = din_b_r;
		delay_i = din_b_i;
		end
		endcase
		
	end


endmodule
module radix2(
		input wire [1:0] state,
		input wire signed [23:0] din_a_r,
		input wire signed [23:0] din_a_i,
		input wire signed [23:0] din_b_r,
		input wire signed [23:0] din_b_i,
		input wire signed [23:0] w_r,
		input wire signed [23:0] w_i,
		output reg signed[23:0] op_r,
		output reg signed[23:0] op_i,
		output reg signed[23:0] delay_r,
		output reg signed[23:0] delay_i,
		output reg outvalid
	);


	reg signed [41:0] inter,mul_r,mul_i;
	reg signed [23:0] a,b,c,d;

	always@(*)begin
		op_r = 0;
		op_i = 0;
		delay_r = din_b_r;
		delay_i = din_b_i;
		case(state)
		2'b00:begin

		delay_r = din_b_r;
		delay_i = din_b_i;
		outvalid = 1'b0;
		end
		2'b01:begin

		a = din_a_r + din_b_r;
		b = din_a_i + din_b_i;
		
		c = (din_a_r - din_b_r);
		d = (din_a_i - din_b_i);

		op_r = a;
		op_i = b;
		delay_r = c;
		delay_i = d;
		outvalid = 1'b1;
		end
		2'b10:begin

		a = din_a_r;
		b = din_a_i;
		delay_r = din_b_r;
		delay_i = din_b_i;

		inter = b * (w_r - w_i);
		mul_r  = w_r * (a - b) + inter;
		mul_i  = w_i * (a + b) + inter;

		op_r = (mul_r[31:8]);
		op_i = (mul_i[31:8]);
		outvalid = 1'b1;
		end
		2'b11:begin

		outvalid = 1'b0;
		end
		default:begin
		delay_r = din_b_r;
		delay_i = din_b_i;
		end
		endcase
		
	end


endmodule