data/full_repos/permissive/52900389/DivFrec_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/52900389/DivFrec_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n  #10 div = 16\'b111110011;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/52900389/DivFrec_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n always #10 clk = ~clk;\n        ^\n%Error: data/full_repos/permissive/52900389/DivFrec_tb.v:35: Cannot find file containing module: \'DivFrec\'\n DivFrec uut (\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52900389,data/full_repos/permissive/52900389/DivFrec\n             data/full_repos/permissive/52900389,data/full_repos/permissive/52900389/DivFrec.v\n             data/full_repos/permissive/52900389,data/full_repos/permissive/52900389/DivFrec.sv\n             DivFrec\n             DivFrec.v\n             DivFrec.sv\n             obj_dir/DivFrec\n             obj_dir/DivFrec.v\n             obj_dir/DivFrec.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module DivFrec_tb;


	reg clk;
	reg rst;
	reg [15:0] div;


	wire clkd;

	DivFrec uut (
		.clk(clk), 
		.rst(rst), 
		.div(div), 
		.clkd(clkd)
	);

	initial begin

		clk = 0;
		rst = 0;
		div = 0;

 

		#10 div = 16'b111110011;
	
	end
	
	always #10 clk = ~clk;
      
endmodule
module DivFrec_tb;



	reg clk;
	reg rst;
	reg [15:0] div;


	wire clkd;

	DivFrec uut (
		.clk(clk), 
		.rst(rst), 
		.div(div), 
		.clkd(clkd)
	);

	initial begin

		clk = 0;
		rst = 0;
		div = 0;

 

		#10 div = 16'b111110011;
	
	end
	
	always #10 clk = ~clk;
      
endmodule