data/full_repos/permissive/502536946/PWM_Generator_Verilog.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/502536946/PWM_Generator_Verilog.v:23: Signal definition not found, creating implicitly: \'clk_div\'\n divfreq D1(.CLK(clk), .speed_ctrl(speed_ctrl), .CLK_time(clk_div));\n                                                          ^~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/502536946/PWM_Generator_Verilog.v:37: Signal definition not found, creating implicitly: \'print_delay_1\'\n assign print_delay_1 = delay_1;\n        ^~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/502536946/PWM_Generator_Verilog.v:54: Signal definition not found, creating implicitly: \'print_delay_2\'\n                                                                                  : ... Suggested alternative: \'print_delay_1\'\n assign print_delay_2 = delay_2;\n        ^~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/502536946/PWM_Generator_Verilog.v:73: Signal definition not found, creating implicitly: \'print_delay_3\'\n                                                                                  : ... Suggested alternative: \'print_delay_1\'\n assign print_delay_3 = delay_3;\n        ^~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/502536946/PWM_Generator_Verilog.v:92: Signal definition not found, creating implicitly: \'print_delay_4\'\n                                                                                  : ... Suggested alternative: \'print_delay_1\'\n assign print_delay_4 = delay_4;\n        ^~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/502536946/PWM_Generator_Verilog.v:131: Operator ASSIGNDLY expects 26 bits on the Assign RHS, but Assign RHS\'s CONST \'25\'h0\' generates 25 bits.\n                                                                                : ... In instance PWM_Generator_Verilog.D1\n   Count <= 25\'b0;\n         ^~\n%Warning-WIDTH: data/full_repos/permissive/502536946/PWM_Generator_Verilog.v:128: Operator GT expects 26 bits on the RHS, but RHS\'s VARREF \'sp\' generates 15 bits.\n                                                                                : ... In instance PWM_Generator_Verilog.D1\n  if(Count > sp) begin\n           ^\n%Warning-WIDTH: data/full_repos/permissive/502536946/PWM_Generator_Verilog.v:29: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                               : ... In instance PWM_Generator_Verilog\n     cnt1 <= 4\'b0;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/502536946/PWM_Generator_Verilog.v:44: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'6\'h0\' generates 6 bits.\n                                                                               : ... In instance PWM_Generator_Verilog\n     cnt2 <= 6\'b0;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/502536946/PWM_Generator_Verilog.v:62: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                               : ... In instance PWM_Generator_Verilog\n     cnt3 <= 8\'b0;\n          ^~\n%Warning-WIDTH: data/full_repos/permissive/502536946/PWM_Generator_Verilog.v:81: Operator ASSIGNDLY expects 9 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                               : ... In instance PWM_Generator_Verilog\n     cnt4 <= 8\'b0;\n          ^~\n%Error: Exiting due to 11 warning(s)\n'
module divfreq(input CLK, input speed_ctrl, output reg CLK_time);
	
	reg	[25:0]	Count;
	reg 	[14:0]		sp;
	
	always@ (posedge CLK or negedge speed_ctrl) begin
		if (!speed_ctrl) sp = 15'd5000;
		else sp = 15'd2500;
	end
		
	always @(posedge CLK) begin
		if(Count > sp) begin


			Count <= 25'b0;
			CLK_time <= ~CLK_time;
		end
		else
			Count <= Count + 1'b1;
	end
endmodule
module divfreq(input CLK, input speed_ctrl, output reg CLK_time);

	
	reg	[25:0]	Count;
	reg 	[14:0]		sp;
	
	always@ (posedge CLK or negedge speed_ctrl) begin
		if (!speed_ctrl) sp = 15'd5000;
		else sp = 15'd2500;
	end
		
	always @(posedge CLK) begin
		if(Count > sp) begin


			Count <= 25'b0;
			CLK_time <= ~CLK_time;
		end
		else
			Count <= Count + 1'b1;
	end
endmodule