data/full_repos/permissive/490492655/shiftRregN_testbench.v
1: b'%Error: data/full_repos/permissive/490492655/shiftRregN_testbench.v:16: Unsupported or unknown PLI call: $monitor\n      $monitor ($time, "rst=%b, en=%b, ldsh=%b, SI=%b, d=%b, SO=%b, q=%b", \n      ^~~~~~~~\n%Error: data/full_repos/permissive/490492655/shiftRregN_testbench.v:24: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("shiftRregN.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/490492655/shiftRregN_testbench.v:25: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(1, shiftRregN_testbench);\n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/490492655/shiftRregN_testbench.v:27: Unsupported: Ignoring delay on this delayed statement.\n      #0 clk = 0; rst = 1; en = 1; ldsh = 0; SI = 0; d = 0;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/490492655/shiftRregN_testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n          #25 clk <= ~clk;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/490492655/shiftRregN_testbench.v:32: Unsupported: Ignoring delay on this delayed statement.\n          #25 clk <= ~clk; rst <= (i%9==4)?0:1; en <= (i%9==7)?0:1; ldsh <= (i%6==5)?1:0; SI <= (i<15)?0:1; d <= d+1;\n          ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module shiftRregN_testbench #(parameter N = 4) ();
  reg [N-1:0] d;
  reg clk, rst, en, ldsh, SI;
  wire SO;
  wire [N-1:0] q;
  
  shiftRregN #(.N(4)) DUT (.d(d), .clk(clk), .rst(rst), .en(en), 
                                     .ldsh(ldsh), .SI(SI), .SO(SO), .q(q));
  
  initial
    begin
      $monitor ($time, "rst=%b, en=%b, ldsh=%b, SI=%b, d=%b, SO=%b, q=%b", 
                rst, en, ldsh, SI, d, SO, q);
    end
  
  integer i;
  
  initial
    begin
      $dumpfile("shiftRregN.vcd");
      $dumpvars(1, shiftRregN_testbench);
      
      #0 clk = 0; rst = 1; en = 1; ldsh = 0; SI = 0; d = 0;
      
      for (i = 0; i < 30; i = i + 1)
        begin
          #25 clk <= ~clk;
          #25 clk <= ~clk; rst <= (i%9==4)?0:1; en <= (i%9==7)?0:1; ldsh <= (i%6==5)?1:0; SI <= (i<15)?0:1; d <= d+1;
        end
      
    end
  
endmodule
module shiftRregN_testbench #(parameter N = 4) ();

  reg [N-1:0] d;
  reg clk, rst, en, ldsh, SI;
  wire SO;
  wire [N-1:0] q;
  
  shiftRregN #(.N(4)) DUT (.d(d), .clk(clk), .rst(rst), .en(en), 
                                     .ldsh(ldsh), .SI(SI), .SO(SO), .q(q));
  
  initial
    begin
      $monitor ($time, "rst=%b, en=%b, ldsh=%b, SI=%b, d=%b, SO=%b, q=%b", 
                rst, en, ldsh, SI, d, SO, q);
    end
  
  integer i;
  
  initial
    begin
      $dumpfile("shiftRregN.vcd");
      $dumpvars(1, shiftRregN_testbench);
      
      #0 clk = 0; rst = 1; en = 1; ldsh = 0; SI = 0; d = 0;
      
      for (i = 0; i < 30; i = i + 1)
        begin
          #25 clk <= ~clk;
          #25 clk <= ~clk; rst <= (i%9==4)?0:1; en <= (i%9==7)?0:1; ldsh <= (i%6==5)?1:0; SI <= (i<15)?0:1; d <= d+1;
        end
      
    end
  
endmodule