data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code/FA_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code/FA_TB.v:42: Unsupported: Ignoring delay on this delayed statement.\n             #10 \n             ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code/FA_TB.v:46: Unsupported: Ignoring delay on this delayed statement.\n             #10\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code/FA_TB.v:50: Unsupported: Ignoring delay on this delayed statement.\n             #10\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code/FA_TB.v:54: Unsupported: Ignoring delay on this delayed statement.\n            #10\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code/FA_TB.v:58: Unsupported: Ignoring delay on this delayed statement.\n            #1000\n            ^\n%Error: data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code/FA_TB.v:29: Cannot find file containing module: \'FA\'\n    FA COMP\n    ^~\n        ... Looked in:\n             data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code,data/full_repos/permissive/502135797/FA\n             data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code,data/full_repos/permissive/502135797/FA.v\n             data/full_repos/permissive/502135797/Lab2_Feb_15_2022/Code,data/full_repos/permissive/502135797/FA.sv\n             FA\n             FA.v\n             FA.sv\n             obj_dir/FA\n             obj_dir/FA.v\n             obj_dir/FA.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module FA_TB(

    );
    reg a_tb,b_tb,cin_tb;
    wire sum_tb,cout_tb;
    
    FA COMP
    (
    .a(a_tb),
    .b(b_tb),
    .cin(cin_tb),
    .sum(sum_tb),
    .cout(cout_tb) 
    );
     initial
            begin:  TST1 
               a_tb = 1'b1;
               b_tb = 1'b0;
               cin_tb = 1'b0; 
             #10 
               a_tb = 1'b0;
               b_tb = 1'b1;
               cin_tb = 1'b1;
             #10
               a_tb = 1'b1;
               b_tb = 1'b0;
               cin_tb = 1'b0;
             #10
               a_tb = 1'b1;
               b_tb = 1'b0;
               cin_tb = 1'b1; 
            #10
               a_tb = 1'b1;
               b_tb = 1'b1;
               cin_tb = 1'b1; 
            #1000
            $finish; 
            end

    
    
    
    
    
    
    
    
    
endmodule
module FA_TB(

    );

    reg a_tb,b_tb,cin_tb;
    wire sum_tb,cout_tb;
    
    FA COMP
    (
    .a(a_tb),
    .b(b_tb),
    .cin(cin_tb),
    .sum(sum_tb),
    .cout(cout_tb) 
    );
     initial
            begin:  TST1 
               a_tb = 1'b1;
               b_tb = 1'b0;
               cin_tb = 1'b0; 
             #10 
               a_tb = 1'b0;
               b_tb = 1'b1;
               cin_tb = 1'b1;
             #10
               a_tb = 1'b1;
               b_tb = 1'b0;
               cin_tb = 1'b0;
             #10
               a_tb = 1'b1;
               b_tb = 1'b0;
               cin_tb = 1'b1; 
            #10
               a_tb = 1'b1;
               b_tb = 1'b1;
               cin_tb = 1'b1; 
            #1000
            $finish; 
            end

    
    
    
    
    
    
    
    
    
endmodule