data/full_repos/permissive/48250786/test_shiftrows.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/48250786/test_shiftrows.v:46: Unsupported: Ignoring delay on this delayed statement.\n  #20 shftIn = 128\'ha761ca9b97be8b45d8ad1a611fc97369;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_shiftrows.v:47: Unsupported: Ignoring delay on this delayed statement.\n      #20 shftIn = 128\'h3b59cb73fcd90ee05774222dc067fb68;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_shiftrows.v:48: Unsupported: Ignoring delay on this delayed statement.\n  #20 shftIn = 128\'h2dfb02343f6d12dd09337ec75b36e3f0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/48250786/test_shiftrows.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #20 shftIn = 128\'h36400926f9336d2d9fb59d23c42c3950;  \n  ^\n%Error: data/full_repos/permissive/48250786/test_shiftrows.v:35: Cannot find file containing module: \'shiftRows\'\n shiftRows uut (\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/48250786,data/full_repos/permissive/48250786/shiftRows\n             data/full_repos/permissive/48250786,data/full_repos/permissive/48250786/shiftRows.v\n             data/full_repos/permissive/48250786,data/full_repos/permissive/48250786/shiftRows.sv\n             shiftRows\n             shiftRows.v\n             shiftRows.sv\n             obj_dir/shiftRows\n             obj_dir/shiftRows.v\n             obj_dir/shiftRows.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test_shiftrows;


	reg [127:0] shftIn;
	reg inv;


	wire [127:0] shftOut;


	shiftRows uut (
		.shftOut(shftOut), 
		.shftIn(shftIn), 
		.inv(inv)
	);

	initial begin

		inv = 0;
		shftIn = 128'h63cab7040953d051cd60e0e7ba70e18c;
		
		#20 shftIn = 128'ha761ca9b97be8b45d8ad1a611fc97369;
      #20 shftIn = 128'h3b59cb73fcd90ee05774222dc067fb68;
		#20 shftIn = 128'h2dfb02343f6d12dd09337ec75b36e3f0;
		#20 shftIn = 128'h36400926f9336d2d9fb59d23c42c3950;		
		 


	end
      
endmodule
module test_shiftrows;



	reg [127:0] shftIn;
	reg inv;


	wire [127:0] shftOut;


	shiftRows uut (
		.shftOut(shftOut), 
		.shftIn(shftIn), 
		.inv(inv)
	);

	initial begin

		inv = 0;
		shftIn = 128'h63cab7040953d051cd60e0e7ba70e18c;
		
		#20 shftIn = 128'ha761ca9b97be8b45d8ad1a611fc97369;
      #20 shftIn = 128'h3b59cb73fcd90ee05774222dc067fb68;
		#20 shftIn = 128'h2dfb02343f6d12dd09337ec75b36e3f0;
		#20 shftIn = 128'h36400926f9336d2d9fb59d23c42c3950;		
		 


	end
      
endmodule