data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_rsrvs.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/447681894/pythondata_cpu_marocchino/verilog/rtl/verilog/or1k_marocchino_rsrvs.v:594: Multiple top level modules\n                                                                                                                                 : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                                                 : ... Top module \'or1k_marocchino_rsrvs\'\nmodule or1k_marocchino_rsrvs\n       ^~~~~~~~~~~~~~~~~~~~~\n                                                                                                                                 : ... Top module \'or1k_marocchino_rsrvs_1clk\'\nmodule or1k_marocchino_rsrvs_1clk\n       ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module or1k_marocchino_rsrvs_1clk
#(
  parameter OPTION_OPERAND_WIDTH = 32,
  parameter OP_WIDTH             =  1,
  parameter OPC_WIDTH            =  1,
  parameter DEST_EXTADR_WIDTH    =  3
)
(

  input                                     cpu_clk,


  input                                     pipeline_flush_i,
  input                                     padv_rsrvs_i,
  input                                     taking_op_i,


  input    [((2*OPTION_OPERAND_WIDTH)-1):0] dcod_rfxx_i,



  input                               [3:0] omn2dec_hazards_flags_i,

  input       [((2*DEST_EXTADR_WIDTH)-1):0] omn2dec_hazards_addrs_i,


  input                                     dcod_rfd1_we_i,
  input             [DEST_EXTADR_WIDTH-1:0] dcod_extadr_i,



  input           [(DEST_EXTADR_WIDTH-1):0] wrbk_extadr_i,

  input        [(OPTION_OPERAND_WIDTH-1):0] wrbk_result1_i,
  input        [(OPTION_OPERAND_WIDTH-1):0] wrbk_result2_i,


  input                    [(OP_WIDTH-1):0] dcod_op_i,
  input                   [(OPC_WIDTH-1):0] dcod_opc_i,



  output                                    exec_op_any_o,
  output                   [(OP_WIDTH-1):0] exec_op_o,
  output                  [(OPC_WIDTH-1):0] exec_opc_o,

  output                                    exec_1clk_ff_d1a1_o,
  output                                    exec_1clk_ff_d1b1_o,

  output       [(OPTION_OPERAND_WIDTH-1):0] exec_rfa1_o,
  output       [(OPTION_OPERAND_WIDTH-1):0] exec_rfb1_o,

  output                                    unit_free_o
);


  localparam [(DEST_EXTADR_WIDTH-1):0] EXTADR_ZERO = 0;
  localparam          [(OP_WIDTH-1):0] OP_ZERO     = 0;
  localparam         [(OPC_WIDTH-1):0] OPC_ZERO    = 0;






  reg                            exec_op_any_r;
  reg           [(OP_WIDTH-1):0] exec_op_r;
  reg          [(OPC_WIDTH-1):0] exec_opc_r;


  reg  [(DEST_EXTADR_WIDTH-1):0] exec_extadr_r;
  reg                            exec_1clk_ff_d1a1_r;
  reg                            exec_1clk_ff_d1b1_r;


  wire padv_exec_l = (~exec_op_any_r) |  taking_op_i;








  wire [(OPTION_OPERAND_WIDTH-1):0] dcod_rfa1;
  wire    [(DEST_EXTADR_WIDTH-1):0] omn2dec_extadr_dxa1;

  wire [(OPTION_OPERAND_WIDTH-1):0] dcod_rfb1;
  wire    [(DEST_EXTADR_WIDTH-1):0] omn2dec_extadr_dxb1;


  assign dcod_rfa1 = dcod_rfxx_i[(OPTION_OPERAND_WIDTH-1):0];
  assign omn2dec_extadr_dxa1 = omn2dec_hazards_addrs_i[(DEST_EXTADR_WIDTH-1):0];

  assign dcod_rfb1 = dcod_rfxx_i[(2*OPTION_OPERAND_WIDTH-1):OPTION_OPERAND_WIDTH];
  assign omn2dec_extadr_dxb1 = omn2dec_hazards_addrs_i[(2*DEST_EXTADR_WIDTH-1):DEST_EXTADR_WIDTH];



  wire omn2dec_hazard_d1a1 = omn2dec_hazards_flags_i[0] & (omn2dec_extadr_dxa1 != exec_extadr_r);
  wire omn2dec_hazard_d2a1 = omn2dec_hazards_flags_i[1];

  wire omn2dec_hazard_d1b1 = omn2dec_hazards_flags_i[2] & (omn2dec_extadr_dxb1 != exec_extadr_r);
  wire omn2dec_hazard_d2b1 = omn2dec_hazards_flags_i[3];


  wire omn2dec_hazard = omn2dec_hazard_d2b1 | omn2dec_hazard_d1b1 |
                        omn2dec_hazard_d2a1 | omn2dec_hazard_d1a1;


  wire   [(DEST_EXTADR_WIDTH-1):0] dcod_extadr;
  assign dcod_extadr = dcod_rfd1_we_i ? dcod_extadr_i : EXTADR_ZERO;


  wire exe2dec_ff_d1a1 = omn2dec_hazards_flags_i[0] & (omn2dec_extadr_dxa1 == exec_extadr_r);
  wire exe2dec_ff_d1b1 = omn2dec_hazards_flags_i[2] & (omn2dec_extadr_dxb1 == exec_extadr_r);






  reg                            busy_op_any_r;
  reg           [(OP_WIDTH-1):0] busy_op_r;
  reg          [(OPC_WIDTH-1):0] busy_opc_r;


  reg  [(DEST_EXTADR_WIDTH-1):0] busy_extadr_r;
  reg                            busy_1clk_ff_d1a1_r;
  reg                            busy_1clk_ff_d1b1_r;



  reg                            busy_hazard_d1a1_r;
  reg                            busy_hazard_d2a1_r;
  reg                            busy_hazard_dxa1_r;
  reg    [DEST_EXTADR_WIDTH-1:0] busy_extadr_dxa1_r;
  wire                           busy_dxa1_mux_wrbk;
  wire                           busy_dxa1_wait_wrbk;

  reg                            busy_hazard_d1b1_r;
  reg                            busy_hazard_d2b1_r;
  reg                            busy_hazard_dxb1_r;
  reg    [DEST_EXTADR_WIDTH-1:0] busy_extadr_dxb1_r;
  wire                           busy_dxb1_mux_wrbk;
  wire                           busy_dxb1_wait_wrbk;


  wire                           busy_free_of_hazards;




  assign unit_free_o = (~busy_op_any_r);



  always @(posedge cpu_clk) begin
    if (padv_rsrvs_i) begin
      busy_extadr_dxa1_r <= omn2dec_extadr_dxa1;
      busy_extadr_dxb1_r <= omn2dec_extadr_dxb1;
    end
  end


  assign busy_dxa1_mux_wrbk = busy_hazard_dxa1_r & (busy_extadr_dxa1_r == wrbk_extadr_i);
  assign busy_dxb1_mux_wrbk = busy_hazard_dxb1_r & (busy_extadr_dxb1_r == wrbk_extadr_i);


  assign busy_dxa1_wait_wrbk = busy_hazard_dxa1_r & (busy_extadr_dxa1_r != wrbk_extadr_i);
  assign busy_dxb1_wait_wrbk = busy_hazard_dxb1_r & (busy_extadr_dxb1_r != wrbk_extadr_i);


  assign busy_free_of_hazards = ((~busy_hazard_dxa1_r) | (busy_extadr_dxa1_r == wrbk_extadr_i)) &
                                ((~busy_hazard_dxb1_r) | (busy_extadr_dxb1_r == wrbk_extadr_i));





  always @(posedge cpu_clk) begin
    if (pipeline_flush_i) begin

      busy_op_any_r       <= 1'b0;
      busy_op_r           <= OP_ZERO;
      busy_opc_r          <= OPC_ZERO;

      busy_extadr_r       <= EXTADR_ZERO;
      busy_1clk_ff_d1a1_r <= 1'b0;
      busy_1clk_ff_d1b1_r <= 1'b0;

      busy_hazard_d1a1_r  <= 1'b0;
      busy_hazard_d2a1_r  <= 1'b0;
      busy_hazard_dxa1_r  <= 1'b0;

      busy_hazard_d1b1_r  <= 1'b0;
      busy_hazard_d2b1_r  <= 1'b0;
      busy_hazard_dxb1_r  <= 1'b0;
    end
    else begin
      (* parallel_case *)
      case ({padv_exec_l, padv_rsrvs_i})

        2'b00: begin

          if (busy_dxa1_mux_wrbk) begin
            busy_hazard_d1a1_r <= 1'b0;
            busy_hazard_d2a1_r <= 1'b0;
            busy_hazard_dxa1_r <= 1'b0;
          end

          if (busy_dxb1_mux_wrbk) begin
            busy_hazard_d1b1_r <= 1'b0;
            busy_hazard_d2b1_r <= 1'b0;
            busy_hazard_dxb1_r <= 1'b0;
          end
        end


        2'b01: begin

          busy_op_any_r       <= 1'b1;
          busy_op_r           <= dcod_op_i;
          busy_opc_r          <= dcod_opc_i;

          busy_extadr_r       <= dcod_extadr;
          busy_1clk_ff_d1a1_r <= exe2dec_ff_d1a1;
          busy_1clk_ff_d1b1_r <= exe2dec_ff_d1b1;

          busy_hazard_d1a1_r  <= omn2dec_hazard_d1a1;
          busy_hazard_d2a1_r  <= omn2dec_hazard_d2a1;
          busy_hazard_dxa1_r  <= omn2dec_hazard_d1a1 | omn2dec_hazard_d2a1;

          busy_hazard_d1b1_r  <= omn2dec_hazard_d1b1;
          busy_hazard_d2b1_r  <= omn2dec_hazard_d2b1;
          busy_hazard_dxb1_r  <= omn2dec_hazard_d1b1 | omn2dec_hazard_d2b1;
        end


        2'b10: begin
          if (busy_free_of_hazards) begin

            busy_op_any_r <= 1'b0;
            busy_op_r     <= OP_ZERO;
            busy_opc_r    <= OPC_ZERO;
            busy_extadr_r <= EXTADR_ZERO;
          end

          busy_1clk_ff_d1a1_r <= 1'b0;
          busy_1clk_ff_d1b1_r <= 1'b0;

          if (busy_dxa1_mux_wrbk) begin
            busy_hazard_d1a1_r <= 1'b0;
            busy_hazard_d2a1_r <= 1'b0;
            busy_hazard_dxa1_r <= 1'b0;
          end
          else if (busy_1clk_ff_d1a1_r) begin


            busy_hazard_d1a1_r <= busy_dxb1_wait_wrbk;
            busy_hazard_dxa1_r <= busy_dxb1_wait_wrbk;
          end

          if (busy_dxb1_mux_wrbk) begin
            busy_hazard_d1b1_r <= 1'b0;
            busy_hazard_d2b1_r <= 1'b0;
            busy_hazard_dxb1_r <= 1'b0;
          end
          else if (busy_1clk_ff_d1b1_r) begin


            busy_hazard_d1b1_r <= busy_dxa1_wait_wrbk;
            busy_hazard_dxb1_r <= busy_dxa1_wait_wrbk;
          end
        end


        2'b11: begin
          if (omn2dec_hazard) begin

            busy_op_any_r       <= 1'b1;
            busy_op_r           <= dcod_op_i;
            busy_opc_r          <= dcod_opc_i;
            busy_extadr_r       <= dcod_extadr;

            busy_hazard_d1a1_r <= omn2dec_hazards_flags_i[0];
            busy_hazard_d2a1_r <= omn2dec_hazard_d2a1;
            busy_hazard_dxa1_r <= omn2dec_hazards_flags_i[0] | omn2dec_hazard_d2a1;

            busy_hazard_d1b1_r <= omn2dec_hazards_flags_i[2];
            busy_hazard_d2b1_r <= omn2dec_hazard_d2b1;
            busy_hazard_dxb1_r <= omn2dec_hazards_flags_i[2] | omn2dec_hazard_d2b1;
          end

          busy_1clk_ff_d1a1_r <= 1'b0;
          busy_1clk_ff_d1b1_r <= 1'b0;
        end
      endcase
    end
  end




  reg  [OPTION_OPERAND_WIDTH-1:0] busy_rfa1_r;
  reg  [OPTION_OPERAND_WIDTH-1:0] busy_rfb1_r;

  wire [OPTION_OPERAND_WIDTH-1:0] busy_rfa1;
  wire [OPTION_OPERAND_WIDTH-1:0] busy_rfb1;


  always @(posedge cpu_clk) begin
    if (padv_rsrvs_i) begin
      busy_rfa1_r <= dcod_rfa1;
      busy_rfb1_r <= dcod_rfb1;
    end
    else begin
      busy_rfa1_r <= busy_rfa1;
      busy_rfb1_r <= busy_rfb1;
    end
  end



  assign busy_rfa1 =  busy_hazard_d1a1_r ? wrbk_result1_i :
                     (busy_hazard_d2a1_r ? wrbk_result2_i : busy_rfa1_r);

  assign busy_rfb1 =  busy_hazard_d1b1_r ? wrbk_result1_i :
                     (busy_hazard_d2b1_r ? wrbk_result2_i : busy_rfb1_r);






  always @(posedge cpu_clk) begin
    if (pipeline_flush_i) begin
      exec_op_any_r       <= 1'b0;
      exec_op_r           <= OP_ZERO;
      exec_opc_r          <= OPC_ZERO;
      exec_extadr_r       <= EXTADR_ZERO;
      exec_1clk_ff_d1a1_r <= 1'b0;
      exec_1clk_ff_d1b1_r <= 1'b0;
    end
    else begin
      (* parallel_case *)
      case ({padv_exec_l, padv_rsrvs_i})

        2'b00, 2'b01:;

        2'b10: begin
          if (busy_free_of_hazards) begin
            exec_op_any_r       <= busy_op_any_r;
            exec_op_r           <= busy_op_r;
            exec_opc_r          <= busy_opc_r;
            exec_extadr_r       <= busy_extadr_r;
            exec_1clk_ff_d1a1_r <= busy_1clk_ff_d1a1_r;
            exec_1clk_ff_d1b1_r <= busy_1clk_ff_d1b1_r;
          end
          else begin
            exec_op_any_r       <= 1'b0;
            exec_op_r           <= OP_ZERO;
            exec_opc_r          <= OPC_ZERO;
            exec_extadr_r       <= EXTADR_ZERO;
            exec_1clk_ff_d1a1_r <= 1'b0;
            exec_1clk_ff_d1b1_r <= 1'b0;
          end
        end

        2'b11: begin
          if (omn2dec_hazard) begin
            exec_op_any_r       <= 1'b0;
            exec_op_r           <= OP_ZERO;
            exec_opc_r          <= OPC_ZERO;
            exec_extadr_r       <= EXTADR_ZERO;
            exec_1clk_ff_d1a1_r <= 1'b0;
            exec_1clk_ff_d1b1_r <= 1'b0;
          end
          else begin
            exec_op_any_r       <= 1'b1;
            exec_op_r           <= dcod_op_i;
            exec_opc_r          <= dcod_opc_i;
            exec_extadr_r       <= dcod_extadr;
            exec_1clk_ff_d1a1_r <= exe2dec_ff_d1a1;
            exec_1clk_ff_d1b1_r <= exe2dec_ff_d1b1;
          end
        end
      endcase
    end
  end


  assign exec_op_any_o = exec_op_any_r;
  assign exec_op_o     = exec_op_r;
  assign exec_opc_o    = exec_opc_r;


  assign exec_1clk_ff_d1a1_o = exec_1clk_ff_d1a1_r;
  assign exec_1clk_ff_d1b1_o = exec_1clk_ff_d1b1_r;



  reg  [OPTION_OPERAND_WIDTH-1:0] exec_rfa1_r;
  reg  [OPTION_OPERAND_WIDTH-1:0] exec_rfb1_r;


  always @(posedge cpu_clk) begin
    (* parallel_case *)
    case ({padv_exec_l, padv_rsrvs_i})

      2'b00, 2'b01:;

      2'b10: begin
        exec_rfa1_r <= busy_rfa1;
        exec_rfb1_r <= busy_rfb1;
      end

      2'b11: begin
        exec_rfa1_r <= dcod_rfa1;
        exec_rfb1_r <= dcod_rfb1;
      end
    endcase
  end


  assign exec_rfa1_o = exec_rfa1_r;
  assign exec_rfb1_o = exec_rfb1_r;

endmodule
module or1k_marocchino_rsrvs_1clk
#(
  parameter OPTION_OPERAND_WIDTH = 32,
  parameter OP_WIDTH             =  1,
  parameter OPC_WIDTH            =  1,
  parameter DEST_EXTADR_WIDTH    =  3
)
(

  input                                     cpu_clk,


  input                                     pipeline_flush_i,
  input                                     padv_rsrvs_i,
  input                                     taking_op_i,


  input    [((2*OPTION_OPERAND_WIDTH)-1):0] dcod_rfxx_i,



  input                               [3:0] omn2dec_hazards_flags_i,

  input       [((2*DEST_EXTADR_WIDTH)-1):0] omn2dec_hazards_addrs_i,


  input                                     dcod_rfd1_we_i,
  input             [DEST_EXTADR_WIDTH-1:0] dcod_extadr_i,



  input           [(DEST_EXTADR_WIDTH-1):0] wrbk_extadr_i,

  input        [(OPTION_OPERAND_WIDTH-1):0] wrbk_result1_i,
  input        [(OPTION_OPERAND_WIDTH-1):0] wrbk_result2_i,


  input                    [(OP_WIDTH-1):0] dcod_op_i,
  input                   [(OPC_WIDTH-1):0] dcod_opc_i,



  output                                    exec_op_any_o,
  output                   [(OP_WIDTH-1):0] exec_op_o,
  output                  [(OPC_WIDTH-1):0] exec_opc_o,

  output                                    exec_1clk_ff_d1a1_o,
  output                                    exec_1clk_ff_d1b1_o,

  output       [(OPTION_OPERAND_WIDTH-1):0] exec_rfa1_o,
  output       [(OPTION_OPERAND_WIDTH-1):0] exec_rfb1_o,

  output                                    unit_free_o
);



  localparam [(DEST_EXTADR_WIDTH-1):0] EXTADR_ZERO = 0;
  localparam          [(OP_WIDTH-1):0] OP_ZERO     = 0;
  localparam         [(OPC_WIDTH-1):0] OPC_ZERO    = 0;






  reg                            exec_op_any_r;
  reg           [(OP_WIDTH-1):0] exec_op_r;
  reg          [(OPC_WIDTH-1):0] exec_opc_r;


  reg  [(DEST_EXTADR_WIDTH-1):0] exec_extadr_r;
  reg                            exec_1clk_ff_d1a1_r;
  reg                            exec_1clk_ff_d1b1_r;


  wire padv_exec_l = (~exec_op_any_r) |  taking_op_i;








  wire [(OPTION_OPERAND_WIDTH-1):0] dcod_rfa1;
  wire    [(DEST_EXTADR_WIDTH-1):0] omn2dec_extadr_dxa1;

  wire [(OPTION_OPERAND_WIDTH-1):0] dcod_rfb1;
  wire    [(DEST_EXTADR_WIDTH-1):0] omn2dec_extadr_dxb1;


  assign dcod_rfa1 = dcod_rfxx_i[(OPTION_OPERAND_WIDTH-1):0];
  assign omn2dec_extadr_dxa1 = omn2dec_hazards_addrs_i[(DEST_EXTADR_WIDTH-1):0];

  assign dcod_rfb1 = dcod_rfxx_i[(2*OPTION_OPERAND_WIDTH-1):OPTION_OPERAND_WIDTH];
  assign omn2dec_extadr_dxb1 = omn2dec_hazards_addrs_i[(2*DEST_EXTADR_WIDTH-1):DEST_EXTADR_WIDTH];



  wire omn2dec_hazard_d1a1 = omn2dec_hazards_flags_i[0] & (omn2dec_extadr_dxa1 != exec_extadr_r);
  wire omn2dec_hazard_d2a1 = omn2dec_hazards_flags_i[1];

  wire omn2dec_hazard_d1b1 = omn2dec_hazards_flags_i[2] & (omn2dec_extadr_dxb1 != exec_extadr_r);
  wire omn2dec_hazard_d2b1 = omn2dec_hazards_flags_i[3];


  wire omn2dec_hazard = omn2dec_hazard_d2b1 | omn2dec_hazard_d1b1 |
                        omn2dec_hazard_d2a1 | omn2dec_hazard_d1a1;


  wire   [(DEST_EXTADR_WIDTH-1):0] dcod_extadr;
  assign dcod_extadr = dcod_rfd1_we_i ? dcod_extadr_i : EXTADR_ZERO;


  wire exe2dec_ff_d1a1 = omn2dec_hazards_flags_i[0] & (omn2dec_extadr_dxa1 == exec_extadr_r);
  wire exe2dec_ff_d1b1 = omn2dec_hazards_flags_i[2] & (omn2dec_extadr_dxb1 == exec_extadr_r);






  reg                            busy_op_any_r;
  reg           [(OP_WIDTH-1):0] busy_op_r;
  reg          [(OPC_WIDTH-1):0] busy_opc_r;


  reg  [(DEST_EXTADR_WIDTH-1):0] busy_extadr_r;
  reg                            busy_1clk_ff_d1a1_r;
  reg                            busy_1clk_ff_d1b1_r;



  reg                            busy_hazard_d1a1_r;
  reg                            busy_hazard_d2a1_r;
  reg                            busy_hazard_dxa1_r;
  reg    [DEST_EXTADR_WIDTH-1:0] busy_extadr_dxa1_r;
  wire                           busy_dxa1_mux_wrbk;
  wire                           busy_dxa1_wait_wrbk;

  reg                            busy_hazard_d1b1_r;
  reg                            busy_hazard_d2b1_r;
  reg                            busy_hazard_dxb1_r;
  reg    [DEST_EXTADR_WIDTH-1:0] busy_extadr_dxb1_r;
  wire                           busy_dxb1_mux_wrbk;
  wire                           busy_dxb1_wait_wrbk;


  wire                           busy_free_of_hazards;




  assign unit_free_o = (~busy_op_any_r);



  always @(posedge cpu_clk) begin
    if (padv_rsrvs_i) begin
      busy_extadr_dxa1_r <= omn2dec_extadr_dxa1;
      busy_extadr_dxb1_r <= omn2dec_extadr_dxb1;
    end
  end


  assign busy_dxa1_mux_wrbk = busy_hazard_dxa1_r & (busy_extadr_dxa1_r == wrbk_extadr_i);
  assign busy_dxb1_mux_wrbk = busy_hazard_dxb1_r & (busy_extadr_dxb1_r == wrbk_extadr_i);


  assign busy_dxa1_wait_wrbk = busy_hazard_dxa1_r & (busy_extadr_dxa1_r != wrbk_extadr_i);
  assign busy_dxb1_wait_wrbk = busy_hazard_dxb1_r & (busy_extadr_dxb1_r != wrbk_extadr_i);


  assign busy_free_of_hazards = ((~busy_hazard_dxa1_r) | (busy_extadr_dxa1_r == wrbk_extadr_i)) &
                                ((~busy_hazard_dxb1_r) | (busy_extadr_dxb1_r == wrbk_extadr_i));





  always @(posedge cpu_clk) begin
    if (pipeline_flush_i) begin

      busy_op_any_r       <= 1'b0;
      busy_op_r           <= OP_ZERO;
      busy_opc_r          <= OPC_ZERO;

      busy_extadr_r       <= EXTADR_ZERO;
      busy_1clk_ff_d1a1_r <= 1'b0;
      busy_1clk_ff_d1b1_r <= 1'b0;

      busy_hazard_d1a1_r  <= 1'b0;
      busy_hazard_d2a1_r  <= 1'b0;
      busy_hazard_dxa1_r  <= 1'b0;

      busy_hazard_d1b1_r  <= 1'b0;
      busy_hazard_d2b1_r  <= 1'b0;
      busy_hazard_dxb1_r  <= 1'b0;
    end
    else begin
      (* parallel_case *)
      case ({padv_exec_l, padv_rsrvs_i})

        2'b00: begin

          if (busy_dxa1_mux_wrbk) begin
            busy_hazard_d1a1_r <= 1'b0;
            busy_hazard_d2a1_r <= 1'b0;
            busy_hazard_dxa1_r <= 1'b0;
          end

          if (busy_dxb1_mux_wrbk) begin
            busy_hazard_d1b1_r <= 1'b0;
            busy_hazard_d2b1_r <= 1'b0;
            busy_hazard_dxb1_r <= 1'b0;
          end
        end


        2'b01: begin

          busy_op_any_r       <= 1'b1;
          busy_op_r           <= dcod_op_i;
          busy_opc_r          <= dcod_opc_i;

          busy_extadr_r       <= dcod_extadr;
          busy_1clk_ff_d1a1_r <= exe2dec_ff_d1a1;
          busy_1clk_ff_d1b1_r <= exe2dec_ff_d1b1;

          busy_hazard_d1a1_r  <= omn2dec_hazard_d1a1;
          busy_hazard_d2a1_r  <= omn2dec_hazard_d2a1;
          busy_hazard_dxa1_r  <= omn2dec_hazard_d1a1 | omn2dec_hazard_d2a1;

          busy_hazard_d1b1_r  <= omn2dec_hazard_d1b1;
          busy_hazard_d2b1_r  <= omn2dec_hazard_d2b1;
          busy_hazard_dxb1_r  <= omn2dec_hazard_d1b1 | omn2dec_hazard_d2b1;
        end


        2'b10: begin
          if (busy_free_of_hazards) begin

            busy_op_any_r <= 1'b0;
            busy_op_r     <= OP_ZERO;
            busy_opc_r    <= OPC_ZERO;
            busy_extadr_r <= EXTADR_ZERO;
          end

          busy_1clk_ff_d1a1_r <= 1'b0;
          busy_1clk_ff_d1b1_r <= 1'b0;

          if (busy_dxa1_mux_wrbk) begin
            busy_hazard_d1a1_r <= 1'b0;
            busy_hazard_d2a1_r <= 1'b0;
            busy_hazard_dxa1_r <= 1'b0;
          end
          else if (busy_1clk_ff_d1a1_r) begin


            busy_hazard_d1a1_r <= busy_dxb1_wait_wrbk;
            busy_hazard_dxa1_r <= busy_dxb1_wait_wrbk;
          end

          if (busy_dxb1_mux_wrbk) begin
            busy_hazard_d1b1_r <= 1'b0;
            busy_hazard_d2b1_r <= 1'b0;
            busy_hazard_dxb1_r <= 1'b0;
          end
          else if (busy_1clk_ff_d1b1_r) begin


            busy_hazard_d1b1_r <= busy_dxa1_wait_wrbk;
            busy_hazard_dxb1_r <= busy_dxa1_wait_wrbk;
          end
        end


        2'b11: begin
          if (omn2dec_hazard) begin

            busy_op_any_r       <= 1'b1;
            busy_op_r           <= dcod_op_i;
            busy_opc_r          <= dcod_opc_i;
            busy_extadr_r       <= dcod_extadr;

            busy_hazard_d1a1_r <= omn2dec_hazards_flags_i[0];
            busy_hazard_d2a1_r <= omn2dec_hazard_d2a1;
            busy_hazard_dxa1_r <= omn2dec_hazards_flags_i[0] | omn2dec_hazard_d2a1;

            busy_hazard_d1b1_r <= omn2dec_hazards_flags_i[2];
            busy_hazard_d2b1_r <= omn2dec_hazard_d2b1;
            busy_hazard_dxb1_r <= omn2dec_hazards_flags_i[2] | omn2dec_hazard_d2b1;
          end

          busy_1clk_ff_d1a1_r <= 1'b0;
          busy_1clk_ff_d1b1_r <= 1'b0;
        end
      endcase
    end
  end




  reg  [OPTION_OPERAND_WIDTH-1:0] busy_rfa1_r;
  reg  [OPTION_OPERAND_WIDTH-1:0] busy_rfb1_r;

  wire [OPTION_OPERAND_WIDTH-1:0] busy_rfa1;
  wire [OPTION_OPERAND_WIDTH-1:0] busy_rfb1;


  always @(posedge cpu_clk) begin
    if (padv_rsrvs_i) begin
      busy_rfa1_r <= dcod_rfa1;
      busy_rfb1_r <= dcod_rfb1;
    end
    else begin
      busy_rfa1_r <= busy_rfa1;
      busy_rfb1_r <= busy_rfb1;
    end
  end



  assign busy_rfa1 =  busy_hazard_d1a1_r ? wrbk_result1_i :
                     (busy_hazard_d2a1_r ? wrbk_result2_i : busy_rfa1_r);

  assign busy_rfb1 =  busy_hazard_d1b1_r ? wrbk_result1_i :
                     (busy_hazard_d2b1_r ? wrbk_result2_i : busy_rfb1_r);






  always @(posedge cpu_clk) begin
    if (pipeline_flush_i) begin
      exec_op_any_r       <= 1'b0;
      exec_op_r           <= OP_ZERO;
      exec_opc_r          <= OPC_ZERO;
      exec_extadr_r       <= EXTADR_ZERO;
      exec_1clk_ff_d1a1_r <= 1'b0;
      exec_1clk_ff_d1b1_r <= 1'b0;
    end
    else begin
      (* parallel_case *)
      case ({padv_exec_l, padv_rsrvs_i})

        2'b00, 2'b01:;

        2'b10: begin
          if (busy_free_of_hazards) begin
            exec_op_any_r       <= busy_op_any_r;
            exec_op_r           <= busy_op_r;
            exec_opc_r          <= busy_opc_r;
            exec_extadr_r       <= busy_extadr_r;
            exec_1clk_ff_d1a1_r <= busy_1clk_ff_d1a1_r;
            exec_1clk_ff_d1b1_r <= busy_1clk_ff_d1b1_r;
          end
          else begin
            exec_op_any_r       <= 1'b0;
            exec_op_r           <= OP_ZERO;
            exec_opc_r          <= OPC_ZERO;
            exec_extadr_r       <= EXTADR_ZERO;
            exec_1clk_ff_d1a1_r <= 1'b0;
            exec_1clk_ff_d1b1_r <= 1'b0;
          end
        end

        2'b11: begin
          if (omn2dec_hazard) begin
            exec_op_any_r       <= 1'b0;
            exec_op_r           <= OP_ZERO;
            exec_opc_r          <= OPC_ZERO;
            exec_extadr_r       <= EXTADR_ZERO;
            exec_1clk_ff_d1a1_r <= 1'b0;
            exec_1clk_ff_d1b1_r <= 1'b0;
          end
          else begin
            exec_op_any_r       <= 1'b1;
            exec_op_r           <= dcod_op_i;
            exec_opc_r          <= dcod_opc_i;
            exec_extadr_r       <= dcod_extadr;
            exec_1clk_ff_d1a1_r <= exe2dec_ff_d1a1;
            exec_1clk_ff_d1b1_r <= exe2dec_ff_d1b1;
          end
        end
      endcase
    end
  end


  assign exec_op_any_o = exec_op_any_r;
  assign exec_op_o     = exec_op_r;
  assign exec_opc_o    = exec_opc_r;


  assign exec_1clk_ff_d1a1_o = exec_1clk_ff_d1a1_r;
  assign exec_1clk_ff_d1b1_o = exec_1clk_ff_d1b1_r;



  reg  [OPTION_OPERAND_WIDTH-1:0] exec_rfa1_r;
  reg  [OPTION_OPERAND_WIDTH-1:0] exec_rfb1_r;


  always @(posedge cpu_clk) begin
    (* parallel_case *)
    case ({padv_exec_l, padv_rsrvs_i})

      2'b00, 2'b01:;

      2'b10: begin
        exec_rfa1_r <= busy_rfa1;
        exec_rfb1_r <= busy_rfb1;
      end

      2'b11: begin
        exec_rfa1_r <= dcod_rfa1;
        exec_rfb1_r <= dcod_rfb1;
      end
    endcase
  end


  assign exec_rfa1_o = exec_rfa1_r;
  assign exec_rfb1_o = exec_rfb1_r;

endmodule