data/full_repos/permissive/491573622/counter.v
data/verilator_xmls/f167a20b-85c7-4d0e-9a30-3a4f3744aca8.xml
module counter(
    input clk,
    input reset,
    input [31:0] addr,
    input counterwr,
    input [31:0] din,
    input resetirq,
    output [31:0] dout,
    output reg irq
    );
    reg [31:0] ctrl;
    reg [31:0] preset;
    reg [31:0] count;
    wire [1:0] counter_addr = addr[3:2];
    assign dout = (counter_addr == 2'b00) ? ctrl:
                  (counter_addr == 2'b01) ? preset:
                  (counter_addr == 2'b10) ? count:
                                            ctrl;
    initial
    begin
        ctrl[31:4] <= 28'b0;
        ctrl[2:1] <= 2'b00;
        ctrl[0] <= 1'b1;
        count = 32'd50;
        irq = 0;
    end
    always@(posedge clk)
    begin
        if(ctrl[0])
            count = count - 1;
        if (count <= 0)
            case(ctrl[2:1])
                2'b01: count = 32'd50;
                2'b00: irq = 1;
            endcase
        if(resetirq)
            irq = 0;
        if(counterwr)
        begin
            if (counter_addr == 2'b00)
                ctrl = din;
            if (counter_addr == 2'b01)
                preset = din;
            if (counter_addr == 2'b10)
                count = din;
            $display("@INT:COUNTER[%d] <= %h", counter_addr, din);
        end
    end
endmodule
module counter(
    input clk,
    input reset,
    input [31:0] addr,
    input counterwr,
    input [31:0] din,
    input resetirq,
    output [31:0] dout,
    output reg irq
    );

    reg [31:0] ctrl;
    reg [31:0] preset;
    reg [31:0] count;
    wire [1:0] counter_addr = addr[3:2];
    assign dout = (counter_addr == 2'b00) ? ctrl:
                  (counter_addr == 2'b01) ? preset:
                  (counter_addr == 2'b10) ? count:
                                            ctrl;
    initial
    begin
        ctrl[31:4] <= 28'b0;
        ctrl[2:1] <= 2'b00;
        ctrl[0] <= 1'b1;
        count = 32'd50;
        irq = 0;
    end
    always@(posedge clk)
    begin
        if(ctrl[0])
            count = count - 1;
        if (count <= 0)
            case(ctrl[2:1])
                2'b01: count = 32'd50;
                2'b00: irq = 1;
            endcase
        if(resetirq)
            irq = 0;
        if(counterwr)
        begin
            if (counter_addr == 2'b00)
                ctrl = din;
            if (counter_addr == 2'b01)
                preset = din;
            if (counter_addr == 2'b10)
                count = din;
            $display("@INT:COUNTER[%d] <= %h", counter_addr, din);
        end
    end
endmodule