data/full_repos/permissive/47737018/TB/source_fix4.sv
1: b'%Warning-MULTITOP: data/full_repos/permissive/47737018/TB/source_fix4.sv:27: Multiple top level modules\n                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                           : ... Top module \'mux\'\nmodule mux #(parameter int wl=36)\n       ^~~\n                                                                           : ... Top module \'rdy_en\'\nmodule rdy_en (\n       ^~~~~~\n                                                                           : ... Top module \'crossbar\'\nmodule crossbar #(parameter int wL=36,parameter int lhsCount=5,parameter int rhsCount=5)\n       ^~~~~~~~\n                                                                           : ... Top module \'FIFO\'\nmodule FIFO #(parameter int wL=36,parameter int d=8)\n       ^~~~\n                                                                           : ... Top module \'matrix\'\nmodule matrix #(parameter int WIDTH=36)\n       ^~~~~~\n                                                                           : ... Top module \'findblock\'\nmodule findblock (\n       ^~~~~~~~~\n                                                                           : ... Top module \'priority_encoder\'\nmodule priority_encoder (\n       ^~~~~~~~~~~~~~~~\n                                                                           : ... Top module \'decoder\'\n module decoder(\n        ^~~~~~~\n                                                                           : ... Top module \'decoder_2\'\nmodule decoder_2(\n       ^~~~~~~~~\n                                                                           : ... Top module \'dffr\'\nmodule dffr #(parameter int size = 36 )\n       ^~~~\n                                                                           : ... Top module \'dffr1\'\nmodule dffr1 #(parameter int size = 1 )\n       ^~~~~\n                                                                           : ... Top module \'dffr2\'\nmodule dffr2 #(parameter int size = 5 )\n       ^~~~~\n                                                                           : ... Top module \'dffr3\'\nmodule dffr3 #(parameter int size = 3 )\n       ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/47737018/TB/source_fix4.sv:370: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'temp_block0\' generates 5 bits.\n                                                                         : ... In instance findblock\nblocked[0]=(temp_block0)?0:1;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/47737018/TB/source_fix4.sv:371: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'temp_block1\' generates 5 bits.\n                                                                         : ... In instance findblock\nblocked[1]=(temp_block1)?0:1;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/47737018/TB/source_fix4.sv:372: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'temp_block2\' generates 5 bits.\n                                                                         : ... In instance findblock\nblocked[2]=(temp_block2)?0:1;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/47737018/TB/source_fix4.sv:373: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'temp_block3\' generates 5 bits.\n                                                                         : ... In instance findblock\nblocked[3]=(temp_block3)?0:1;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/47737018/TB/source_fix4.sv:374: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'temp_block4\' generates 5 bits.\n                                                                         : ... In instance findblock\nblocked[4]=(temp_block4)?0:1;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/47737018/TB/source_fix4.sv:285: Operator CASE expects 4 bits on the Case expression, but Case expression\'s VARREF \'counter_pre\' generates 3 bits.\n                                                                         : ... In instance FIFO\nunique case (counter_pre)\n       ^~~~\n%Error: Exiting due to 7 warning(s)\n'
module decoder_2(
input logic [4:0]in_N,
input logic [4:0]in_E,
input logic [4:0]in_S,
input logic [4:0]in_W,
input logic [4:0]in_L,
output logic [4:0]out_N,
output logic [4:0]out_E,
output logic [4:0]out_S,
output logic [4:0]out_W,
output logic [4:0]out_L
);

always_comb
 begin
 out_N[4:0]<={in_L[0],in_W[0],in_S[0],in_E[0],in_N[0]};
 out_E[4:0]<={in_L[1],in_W[1],in_S[1],in_E[1],in_N[1]};
 out_S[4:0]<={in_L[2],in_W[2],in_S[2],in_E[2],in_N[2]};
 out_W[4:0]<={in_L[3],in_W[3],in_S[3],in_E[3],in_N[3]};
 out_L[4:0]<={in_L[4],in_W[4],in_S[4],in_E[4],in_N[4]};
 end

endmodule
module decoder_2(
input logic [4:0]in_N,
input logic [4:0]in_E,
input logic [4:0]in_S,
input logic [4:0]in_W,
input logic [4:0]in_L,
output logic [4:0]out_N,
output logic [4:0]out_E,
output logic [4:0]out_S,
output logic [4:0]out_W,
output logic [4:0]out_L
);


always_comb
 begin
 out_N[4:0]<={in_L[0],in_W[0],in_S[0],in_E[0],in_N[0]};
 out_E[4:0]<={in_L[1],in_W[1],in_S[1],in_E[1],in_N[1]};
 out_S[4:0]<={in_L[2],in_W[2],in_S[2],in_E[2],in_N[2]};
 out_W[4:0]<={in_L[3],in_W[3],in_S[3],in_E[3],in_N[3]};
 out_L[4:0]<={in_L[4],in_W[4],in_S[4],in_E[4],in_N[4]};
 end

endmodule