data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy/Modules.v
data/verilator_xmls/f0d1531a-3af2-4440-ad5a-c929b83a920b.xml
module mod_a ( input in1, input in2, output out );


endmodule
module mod_a ( input in1, input in2, output out );



endmodule