data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift/sift_top.v
1: b'%Error: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift/sift_top.v:54: Cannot find file containing module: \'pll_sift\'\n pll_sift clk_manager(\n ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift,data/full_repos/permissive/507203156/pll_sift\n             data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift,data/full_repos/permissive/507203156/pll_sift.v\n             data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift,data/full_repos/permissive/507203156/pll_sift.sv\n             pll_sift\n             pll_sift.v\n             pll_sift.sv\n             obj_dir/pll_sift\n             obj_dir/pll_sift.v\n             obj_dir/pll_sift.sv\n%Warning-WIDTH: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift/sift_top.v:69: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                                              : ... In instance sift_top\n assign sift_dir = {2\'b00,dir};\n                 ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift/sift_top.v:70: Operator SUB expects 32 or 18 bits on the LHS, but LHS\'s REPLICATE generates 16 bits.\n                                                                                              : ... In instance sift_top\n assign kp_addr = complete1? ({addr_sift[17:10],addr_sift[8:1]}-1538):(addr_sift-3094); \n                                                               ^\n%Error: data/full_repos/permissive/507203156/02-sift_fuxi_imple/src/sift/sift_top.v:79: Cannot find file containing module: \'sift_feat\'\n sift_feat U_sift_feat (\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n'
module sift_top(
	input clk_sys,
	input  wire flag_read,
	input  wire [7:0] img,
	
	output wire [17:0] addr_sift,
	output wire out_feat_en,
	output wire [5:0] sift_dir,
	output wire [7:0] sift_mag, 
	output wire kp,
	output wire [17:0] kp_addr,
	output wire complete1,
	output wire complete2
);
	

	parameter [17:0] grad1_addr=3077;
	parameter [17:0] dir1_addr=3077;
	
	parameter [17:0] grad2_addr=1541;
	parameter [17:0] dir2_addr=1541;
	
	parameter [17:0] kp1_addr=3074;
	parameter [17:0] kp2_addr=1538;

	wire clk_100;
	wire clk_50;
	wire rst;
	
	reg rst_complete;
	
	pll_sift clk_manager(
		.clkin0		(clk_sys),		
		.clkout0	(clk_100),
		.clkout1	(clk_50),
		.locked		(rst)
	);



	wire rst_feat;
	wire [7:0] mag;
	wire [5:0] dir;
	

	assign sift_mag = mag;
	assign sift_dir = {2'b00,dir};
	assign kp_addr = complete1? ({addr_sift[17:10],addr_sift[8:1]}-1538):(addr_sift-3094); 



	assign rst_feat= rst && rst_complete && (!flag_read);




	sift_feat U_sift_feat (
		.clk(clk_50),
		.rst(rst_feat),
		.din(img),
		.addr(addr_sift),
		
		.dout_kp(kp), 
		.mag(mag), 
		.dir(dir), 
		.out_en(out_feat_en),
		.complete1(complete1),
		.complete2(complete2)
    );
	
	
	
always @(posedge clk_50 or negedge rst) begin
	if(~rst)
		rst_complete <= 1'b1;
	else
		rst_complete <= !complete2;
end
	

endmodule
module sift_top(
	input clk_sys,
	input  wire flag_read,
	input  wire [7:0] img,
	
	output wire [17:0] addr_sift,
	output wire out_feat_en,
	output wire [5:0] sift_dir,
	output wire [7:0] sift_mag, 
	output wire kp,
	output wire [17:0] kp_addr,
	output wire complete1,
	output wire complete2
);

	

	parameter [17:0] grad1_addr=3077;
	parameter [17:0] dir1_addr=3077;
	
	parameter [17:0] grad2_addr=1541;
	parameter [17:0] dir2_addr=1541;
	
	parameter [17:0] kp1_addr=3074;
	parameter [17:0] kp2_addr=1538;

	wire clk_100;
	wire clk_50;
	wire rst;
	
	reg rst_complete;
	
	pll_sift clk_manager(
		.clkin0		(clk_sys),		
		.clkout0	(clk_100),
		.clkout1	(clk_50),
		.locked		(rst)
	);



	wire rst_feat;
	wire [7:0] mag;
	wire [5:0] dir;
	

	assign sift_mag = mag;
	assign sift_dir = {2'b00,dir};
	assign kp_addr = complete1? ({addr_sift[17:10],addr_sift[8:1]}-1538):(addr_sift-3094); 



	assign rst_feat= rst && rst_complete && (!flag_read);




	sift_feat U_sift_feat (
		.clk(clk_50),
		.rst(rst_feat),
		.din(img),
		.addr(addr_sift),
		
		.dout_kp(kp), 
		.mag(mag), 
		.dir(dir), 
		.out_en(out_feat_en),
		.complete1(complete1),
		.complete2(complete2)
    );
	
	
	
always @(posedge clk_50 or negedge rst) begin
	if(~rst)
		rst_complete <= 1'b1;
	else
		rst_complete <= !complete2;
end
	

endmodule