data/full_repos/permissive/494148647/src/peripherals/pdm/bench/pdm_iom_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/494148647/src/peripherals/pdm/bench/pdm_iom_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n        repeat(4) #10 clk = ~clk;\n                  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/494148647/src/peripherals/pdm/bench/pdm_iom_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n        forever #10 clk = ~clk;\n                ^\n%Error: data/full_repos/permissive/494148647/src/peripherals/pdm/bench/pdm_iom_tb.v:68: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("pdm_iom_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/494148647/src/peripherals/pdm/bench/pdm_iom_tb.v:69: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, pdm_iom_tb);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/494148647/src/peripherals/pdm/bench/pdm_iom_tb.v:72: syntax error, unexpected \'@\'\n        @(negedge rst);\n        ^\n%Error: data/full_repos/permissive/494148647/src/peripherals/pdm/bench/pdm_iom_tb.v:77: syntax error, unexpected \'@\'\n        repeat(2) @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/494148647/src/peripherals/pdm/bench/pdm_iom_tb.v:81: syntax error, unexpected \'@\'\n        repeat(2) @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/494148647/src/peripherals/pdm/bench/pdm_iom_tb.v:86: syntax error, unexpected \'@\'\n        repeat(4) @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/494148647/src/peripherals/pdm/bench/pdm_iom_tb.v:93: syntax error, unexpected \'@\'\n        repeat(4) @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/494148647/src/peripherals/pdm/bench/pdm_iom_tb.v:97: syntax error, unexpected \'@\'\n        repeat(4) @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/494148647/src/peripherals/pdm/bench/pdm_iom_tb.v:102: syntax error, unexpected \'@\'\n            repeat(8) @(posedge clk);\n                      ^\n%Error: data/full_repos/permissive/494148647/src/peripherals/pdm/bench/pdm_iom_tb.v:110: syntax error, unexpected \'@\'\n        repeat(32) @(posedge clk);\n                   ^\n%Error: Exiting due to 10 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pdm_iom_tb();

    localparam PDM_COUNT = 4;

    integer i;

    reg clk, rst;
    wire [PDM_COUNT-1:0] pdm;

    wire io_addr_strobe, io_read_strobe, io_write_strobe;
    wire [3:0] io_byte_en;
    wire [31:0] io_addr, io_write_data;
    wire [31:0] io_read_data;
    wire io_ready;

    reg [31:0] value;


    pdm_iom#(
        .PDM_COUNT(PDM_COUNT)
    ) DUT (
        .clk(clk),
        .rst(rst),
        .io_addr_strobe(io_addr_strobe),
        .io_read_strobe(io_read_strobe),
        .io_write_strobe(io_write_strobe),
        .io_address(io_addr[11:0]),
        .io_byte_enable(io_byte_en),
        .io_write_data(io_write_data),
        .io_read_data(io_read_data),
        .io_ready(io_ready),
        .pdm(pdm)
    );

    iobus_master_model io (
        .clk(clk),
        .rst(rst),
        .io_addr_strobe(io_addr_strobe),
        .io_read_strobe(io_read_strobe),
        .io_write_strobe(io_write_strobe),
        .io_addr(io_addr),
        .io_byte_en(io_byte_en),
        .io_write_data(io_write_data),
        .io_read_data(io_read_data),
        .io_ready(io_ready)
    );


    initial begin
        clk = 1'b0;
        rst = 1'b1;
        repeat(4) #10 clk = ~clk;
        rst = 1'b0;
        forever #10 clk = ~clk;
    end


    initial begin
        $dumpfile("pdm_iom_tb.vcd");
        $dumpvars(0, pdm_iom_tb);


        @(negedge rst);
        @(posedge clk);


        io.io_read(32'h0000, value);
        repeat(2) @(posedge clk);

        for (i = 0; i < PDM_COUNT; i = i+1)
            io.io_read(32'h0000+4*(i+1), value);
        repeat(2) @(posedge clk);


        io.io_write(32'h1000, 32'hffffffff);
        io.io_read(32'h1000, value);
        repeat(4) @(posedge clk);


        for (i = 0; i < PDM_COUNT; i = i+1) begin
            io.io_write(32'h1000+4*(i+1), 32'hffffffff);
            io.io_read(32'h1000+4*(i+1), value);
        end
        repeat(4) @(posedge clk);


        io.io_write(32'h2000, 32'h0);
        repeat(4) @(posedge clk);


        for (i = 0; i < PDM_COUNT; i = i+1) begin
            io.io_write(32'h2000, 32'h1 << i);
            repeat(8) @(posedge clk);
        end


        io.io_write(32'h5000, 32'hffffffff);
        for (i = 0; i < PDM_COUNT; i = i+1) begin
            io.io_write(32'h5000+4*(i+1), 32'd32*(i+1));
        end
        repeat(32) @(posedge clk);

        $display("%t: PDM IO module testbench complete", $time);
        $finish;
    end

endmodule
module pdm_iom_tb();


    localparam PDM_COUNT = 4;

    integer i;

    reg clk, rst;
    wire [PDM_COUNT-1:0] pdm;

    wire io_addr_strobe, io_read_strobe, io_write_strobe;
    wire [3:0] io_byte_en;
    wire [31:0] io_addr, io_write_data;
    wire [31:0] io_read_data;
    wire io_ready;

    reg [31:0] value;


    pdm_iom#(
        .PDM_COUNT(PDM_COUNT)
    ) DUT (
        .clk(clk),
        .rst(rst),
        .io_addr_strobe(io_addr_strobe),
        .io_read_strobe(io_read_strobe),
        .io_write_strobe(io_write_strobe),
        .io_address(io_addr[11:0]),
        .io_byte_enable(io_byte_en),
        .io_write_data(io_write_data),
        .io_read_data(io_read_data),
        .io_ready(io_ready),
        .pdm(pdm)
    );

    iobus_master_model io (
        .clk(clk),
        .rst(rst),
        .io_addr_strobe(io_addr_strobe),
        .io_read_strobe(io_read_strobe),
        .io_write_strobe(io_write_strobe),
        .io_addr(io_addr),
        .io_byte_en(io_byte_en),
        .io_write_data(io_write_data),
        .io_read_data(io_read_data),
        .io_ready(io_ready)
    );


    initial begin
        clk = 1'b0;
        rst = 1'b1;
        repeat(4) #10 clk = ~clk;
        rst = 1'b0;
        forever #10 clk = ~clk;
    end


    initial begin
        $dumpfile("pdm_iom_tb.vcd");
        $dumpvars(0, pdm_iom_tb);


        @(negedge rst);
        @(posedge clk);


        io.io_read(32'h0000, value);
        repeat(2) @(posedge clk);

        for (i = 0; i < PDM_COUNT; i = i+1)
            io.io_read(32'h0000+4*(i+1), value);
        repeat(2) @(posedge clk);


        io.io_write(32'h1000, 32'hffffffff);
        io.io_read(32'h1000, value);
        repeat(4) @(posedge clk);


        for (i = 0; i < PDM_COUNT; i = i+1) begin
            io.io_write(32'h1000+4*(i+1), 32'hffffffff);
            io.io_read(32'h1000+4*(i+1), value);
        end
        repeat(4) @(posedge clk);


        io.io_write(32'h2000, 32'h0);
        repeat(4) @(posedge clk);


        for (i = 0; i < PDM_COUNT; i = i+1) begin
            io.io_write(32'h2000, 32'h1 << i);
            repeat(8) @(posedge clk);
        end


        io.io_write(32'h5000, 32'hffffffff);
        for (i = 0; i < PDM_COUNT; i = i+1) begin
            io.io_write(32'h5000+4*(i+1), 32'd32*(i+1));
        end
        repeat(32) @(posedge clk);

        $display("%t: PDM IO module testbench complete", $time);
        $finish;
    end

endmodule