data/full_repos/permissive/488739248/rtl/ttl/ttl_74166_sync.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/488739248/rtl/ttl/ttl_74166_sync.v:56: Cell has missing pin: \'qb\'\n            SR_FlipFlop u0 (.s(not_norSER_SHLD[i]), .r(norSER_SHLD[i]), .Reset_n(Reset_n), .clk(CLK), .cen(CLKn),.rst(CLR), .q(SR_Q[i]));\n                        ^~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/488739248/rtl/ttl/ttl_74166_sync.v:46: Cannot find file containing module: \'srff\'\n    srff u_init (.s(not_norSER_SHLD[0]),.r(norSER_SHLD[0]),.clk(CLKn),.rst(CLR), .q(SR_Q[0]));\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/488739248/rtl/ttl,data/full_repos/permissive/488739248/srff\n             data/full_repos/permissive/488739248/rtl/ttl,data/full_repos/permissive/488739248/srff.v\n             data/full_repos/permissive/488739248/rtl/ttl,data/full_repos/permissive/488739248/srff.sv\n             srff\n             srff.v\n             srff.sv\n             obj_dir/srff\n             obj_dir/srff.v\n             obj_dir/srff.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module ttl_74166_sync
(
  input wire Reset_n,
  input wire CLRn,
  input wire CLK,
  input wire CEN,
  input wire INH,
  input wire SH_LDn,
  input wire SER,
  input wire [7:0] D,
  output wire Q
);

    wire CLR;
    wire SH_LD;
    wire SH_LDnn;
    wire CLKn;

    assign CLR = ~CLRn;
    assign SH_LD = ~SH_LDn;
    assign SH_LDnn = ~SH_LD;
    assign CLKn = ~(~(CLK | INH));

    wire [7:0] andSER;
    wire [7:0] andSH_LD;
    wire [7:0] norSER_SHLD;
    wire [7:0] not_norSER_SHLD;
    wire  [7:0] SR_Q;

    assign andSER[0]   = SER  & SH_LDnn;
    assign andSH_LD[0] = D[0] & SH_LD;
    assign norSER_SHLD[0] = ~(andSER[0] | andSH_LD[0]);
    assign not_norSER_SHLD[0] = ~norSER_SHLD[0];
    srff u_init (.s(not_norSER_SHLD[0]),.r(norSER_SHLD[0]),.clk(CLKn),.rst(CLR), .q(SR_Q[0]));
    
    genvar i;
    generate
        for (i=1; i <= 7; i=i+1) 
        begin : ls166_sync_gen
            assign andSER[i]   = SR_Q[i-1] & SH_LDnn;
            assign andSH_LD[i] =    D[i]   & SH_LD;
            assign norSER_SHLD[i] = ~(andSER[i] | andSH_LD[i]);
            assign not_norSER_SHLD[i] = ~norSER_SHLD[i];
            SR_FlipFlop u0 (.s(not_norSER_SHLD[i]), .r(norSER_SHLD[i]), .Reset_n(Reset_n), .clk(CLK), .cen(CLKn),.rst(CLR), .q(SR_Q[i]));
        end
    endgenerate

    assign Q = SR_Q[7];
endmodule
module ttl_74166_sync
(
  input wire Reset_n,
  input wire CLRn,
  input wire CLK,
  input wire CEN,
  input wire INH,
  input wire SH_LDn,
  input wire SER,
  input wire [7:0] D,
  output wire Q
);


    wire CLR;
    wire SH_LD;
    wire SH_LDnn;
    wire CLKn;

    assign CLR = ~CLRn;
    assign SH_LD = ~SH_LDn;
    assign SH_LDnn = ~SH_LD;
    assign CLKn = ~(~(CLK | INH));

    wire [7:0] andSER;
    wire [7:0] andSH_LD;
    wire [7:0] norSER_SHLD;
    wire [7:0] not_norSER_SHLD;
    wire  [7:0] SR_Q;

    assign andSER[0]   = SER  & SH_LDnn;
    assign andSH_LD[0] = D[0] & SH_LD;
    assign norSER_SHLD[0] = ~(andSER[0] | andSH_LD[0]);
    assign not_norSER_SHLD[0] = ~norSER_SHLD[0];
    srff u_init (.s(not_norSER_SHLD[0]),.r(norSER_SHLD[0]),.clk(CLKn),.rst(CLR), .q(SR_Q[0]));
    
    genvar i;
    generate
        for (i=1; i <= 7; i=i+1) 
        begin : ls166_sync_gen
            assign andSER[i]   = SR_Q[i-1] & SH_LDnn;
            assign andSH_LD[i] =    D[i]   & SH_LD;
            assign norSER_SHLD[i] = ~(andSER[i] | andSH_LD[i]);
            assign not_norSER_SHLD[i] = ~norSER_SHLD[i];
            SR_FlipFlop u0 (.s(not_norSER_SHLD[i]), .r(norSER_SHLD[i]), .Reset_n(Reset_n), .clk(CLK), .cen(CLKn),.rst(CLR), .q(SR_Q[i]));
        end
    endgenerate

    assign Q = SR_Q[7];
endmodule