data/full_repos/permissive/42434302/ivltests/pr1632861.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1632861.v:5: Unsupported: Ignoring delay on this delayed statement.\n    #1 tst = 0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1632861.v:7: Unsupported: Ignoring delay on this delayed statement.\n    #1 tst = 5\'hxx;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1632861.v:8: Unsupported: Ignoring delay on this delayed statement.\n    #1 tst = 10\'h3ff;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1632861.v:9: Unsupported: Ignoring delay on this delayed statement.\n    #1 tst = 10\'b00000xxxxx;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1632861.v:10: Unsupported: Ignoring delay on this delayed statement.\n    #1 tst = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1632861.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #1 tst = 8\'hxx;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1632861.v:12: Unsupported: Ignoring delay on this delayed statement.\n    #1 tst = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1632861.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #1 $finish;\n    ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr1632861.v:7: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'5\'bxxxxx\' generates 5 bits.\n                                                                          : ... In instance test\n    #1 tst = 5\'hxx;\n           ^\n%Warning-WIDTH: data/full_repos/permissive/42434302/ivltests/pr1632861.v:11: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'bxxxxxxxx\' generates 8 bits.\n                                                                           : ... In instance test\n    #1 tst = 8\'hxx;\n           ^\n%Error: Exiting due to 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module test;
  reg[9:0] tst;

  initial begin
    #1 tst = 0;

    #1 tst = 5'hxx;
    #1 tst = 10'h3ff;
    #1 tst = 10'b00000xxxxx;
    #1 tst = 0;
    #1 tst = 8'hxx;
    #1 tst = 0;
    #1 $finish;
  end

  always @(tst) begin
    $display("At %0t value is %b", $time, tst);
  end
endmodule
module test;

  reg[9:0] tst;

  initial begin
    #1 tst = 0;

    #1 tst = 5'hxx;
    #1 tst = 10'h3ff;
    #1 tst = 10'b00000xxxxx;
    #1 tst = 0;
    #1 tst = 8'hxx;
    #1 tst = 0;
    #1 $finish;
  end

  always @(tst) begin
    $display("At %0t value is %b", $time, tst);
  end
endmodule