data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/custom_gen/custom_gen_timer.v
1: b"%Error: data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/custom_gen/custom_gen_timer.v:16: Cannot find file containing module: 'custom_gen_counter'\n custom_gen_counter #(\n ^~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/custom_gen,data/full_repos/permissive/503053625/custom_gen_counter\n             data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/custom_gen,data/full_repos/permissive/503053625/custom_gen_counter.v\n             data/full_repos/permissive/503053625/fpga_projects/new_spgd/src/custom_gen,data/full_repos/permissive/503053625/custom_gen_counter.sv\n             custom_gen_counter\n             custom_gen_counter.v\n             custom_gen_counter.sv\n             obj_dir/custom_gen_counter\n             obj_dir/custom_gen_counter.v\n             obj_dir/custom_gen_counter.sv\n%Error: Exiting due to 1 error(s)\n"
module custom_gen_timer #(
	
) (
	input en,
	input clk,

	output [31:0] J_time
);

	reg [31:0] final_count = {32{1'b0}};

	assign J_time = {2'b00, final_count[31:2]};

	wire [31:0] count_out;

	custom_gen_counter #(
		.DATA_WIDTH(32)
	) COUNT0 (
		.clk(clk),
		.en(en),
		.count(count_out)
	);
	always @(negedge en) begin
		final_count = count_out + 1'b1;
	end

endmodule
module custom_gen_timer #(
	
) (
	input en,
	input clk,

	output [31:0] J_time
);


	reg [31:0] final_count = {32{1'b0}};

	assign J_time = {2'b00, final_count[31:2]};

	wire [31:0] count_out;

	custom_gen_counter #(
		.DATA_WIDTH(32)
	) COUNT0 (
		.clk(clk),
		.en(en),
		.count(count_out)
	);
	always @(negedge en) begin
		final_count = count_out + 1'b1;
	end

endmodule