data/full_repos/permissive/513199821/alu.v
1: b'%Error: data/full_repos/permissive/513199821/alu.v:1: Cannot find include file: global.inc\n`include "global.inc" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc.v\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc.sv\n             global.inc\n             global.inc.v\n             global.inc.sv\n             obj_dir/global.inc\n             obj_dir/global.inc.v\n             obj_dir/global.inc.sv\n%Error: data/full_repos/permissive/513199821/alu.v:24: Define or directive not defined: \'`ALU_ADD\'\n `ALU_ADD: alu = vl + vr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/513199821/alu.v:24: syntax error, unexpected \':\', expecting endcase\n `ALU_ADD: alu = vl + vr;\n         ^\n%Error: data/full_repos/permissive/513199821/alu.v:25: Define or directive not defined: \'`ALU_SUB\'\n `ALU_SUB: alu = vl - vr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/513199821/alu.v:26: Define or directive not defined: \'`ALU_AND\'\n `ALU_AND: alu = vl & vr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/513199821/alu.v:27: Define or directive not defined: \'`ALU_OR\'\n `ALU_OR : alu = vl | vr;\n ^~~~~~~\n%Error: data/full_repos/permissive/513199821/alu.v:28: Define or directive not defined: \'`ALU_XOR\'\n `ALU_XOR: alu = vl ^ vr;\n ^~~~~~~~\n%Error: data/full_repos/permissive/513199821/alu.v:48: syntax error, unexpected end\n  end\n  ^~~\n%Error: Cannot continue\n'
module alu  #(
     parameter WIDTH = 32,
     parameter RSBIT = 3
  ) (
    input		clk,
    input		rst,
    input [RSBIT - 1:0] rs_i,
    input [WIDTH - 1:0] vl,
    input [WIDTH - 1:0] vr,
    input [3:0] 	op,

    output reg [RSBIT - 1:0] rs,
    output reg [WIDTH - 1:0] result
);

function [WIDTH - 1:0] alu (input [3:0] op, input [WIDTH - 1:0] vl, input [WIDTH - 1:0] vr);
    case (op)
	`ALU_ADD: alu = vl + vr;
	`ALU_SUB: alu = vl - vr;
	`ALU_AND: alu = vl & vr;
	`ALU_OR : alu = vl | vr;
	`ALU_XOR: alu = vl ^ vr;
	default : alu = 0;
    endcase
endfunction

wire [WIDTH - 1:0] acc = alu (op, vl, vr);

always @ (posedge clk)
begin
  if (rst) begin
    rs <= 0;
  end else begin
    rs <= 0;
    if (|rs_i) begin
      result <= acc;
      rs     <= rs_i;
`ifdef ALU_TEST
      $display ("ALU\t%x @%x op=%x vl=%x vr=%x =%x", coreZ0.cycle, rs_i, op, vl, vr, acc);
`endif
    end
  end
end

endmodule
module alu  #(
     parameter WIDTH = 32,
     parameter RSBIT = 3
  ) (
    input		clk,
    input		rst,
    input [RSBIT - 1:0] rs_i,
    input [WIDTH - 1:0] vl,
    input [WIDTH - 1:0] vr,
    input [3:0] 	op,

    output reg [RSBIT - 1:0] rs,
    output reg [WIDTH - 1:0] result
);


function [WIDTH - 1:0] alu (input [3:0] op, input [WIDTH - 1:0] vl, input [WIDTH - 1:0] vr);
    case (op)
	`ALU_ADD: alu = vl + vr;
	`ALU_SUB: alu = vl - vr;
	`ALU_AND: alu = vl & vr;
	`ALU_OR : alu = vl | vr;
	`ALU_XOR: alu = vl ^ vr;
	default : alu = 0;
    endcase
endfunction

wire [WIDTH - 1:0] acc = alu (op, vl, vr);

always @ (posedge clk)
begin
  if (rst) begin
    rs <= 0;
  end else begin
    rs <= 0;
    if (|rs_i) begin
      result <= acc;
      rs     <= rs_i;
`ifdef ALU_TEST
      $display ("ALU\t%x @%x op=%x vl=%x vr=%x =%x", coreZ0.cycle, rs_i, op, vl, vr, acc);
`endif
    end
  end
end

endmodule