data/full_repos/permissive/447976230/fpga/usrp2/extramfifo/nobl_fifo.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/447976230/fpga/usrp2/extramfifo/nobl_fifo.v:54: Signal definition not found, creating implicitly: \'read\'\n   assign      read = read_strobe && data_avail_int;\n               ^~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/447976230/fpga/usrp2/extramfifo/nobl_fifo.v:55: Signal definition not found, creating implicitly: \'write\'\n   assign      write = write_strobe && space_avail;\n               ^~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/447976230/fpga/usrp2/extramfifo/nobl_fifo.v:83: Signal definition not found, creating implicitly: \'enable\'\n   assign enable = write || read; \n          ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/extramfifo/nobl_fifo.v:77: Operator ADD expects 19 bits on the RHS, but RHS\'s VARREF \'write\' generates 1 bits.\n                                                                                         : ... In instance nobl_fifo\n   wr_pointer <= wr_pointer + write;\n                            ^\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/extramfifo/nobl_fifo.v:78: Operator ADD expects 19 bits on the RHS, but RHS\'s LOGAND generates 1 bits.\n                                                                                         : ... In instance nobl_fifo\n   rd_pointer <= rd_pointer + (~write && read); \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/extramfifo/nobl_fifo.v:79: Operator SUB expects 19 bits on the RHS, but RHS\'s VARREF \'write\' generates 1 bits.\n                                                                                         : ... In instance nobl_fifo\n   capacity <= capacity - write + (~write && read) ;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/extramfifo/nobl_fifo.v:79: Operator ADD expects 19 bits on the RHS, but RHS\'s LOGAND generates 1 bits.\n                                                                                         : ... In instance nobl_fifo\n   capacity <= capacity - write + (~write && read) ;\n                                ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/extramfifo/nobl_fifo.v:90: Cannot find file containing module: \'nobl_if\'\n   nobl_if #(.WIDTH(WIDTH),.DEPTH(RAM_DEPTH))\n   ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp2/extramfifo,data/full_repos/permissive/447976230/nobl_if\n             data/full_repos/permissive/447976230/fpga/usrp2/extramfifo,data/full_repos/permissive/447976230/nobl_if.v\n             data/full_repos/permissive/447976230/fpga/usrp2/extramfifo,data/full_repos/permissive/447976230/nobl_if.sv\n             nobl_if\n             nobl_if.v\n             nobl_if.sv\n             obj_dir/nobl_if\n             obj_dir/nobl_if.v\n             obj_dir/nobl_if.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n'
module nobl_fifo
  #(parameter WIDTH=18,RAM_DEPTH=19,FIFO_DEPTH=19)
    (   
	input clk,
	input rst,
	input [WIDTH-1:0] RAM_D_pi,
	output [WIDTH-1:0] RAM_D_po,
	output RAM_D_poe,
	output [RAM_DEPTH-1:0] RAM_A,
	output RAM_WEn,
	output RAM_CENn,
	output RAM_LDn,
	output RAM_OEn,
	output RAM_CE1n,
	input [WIDTH-1:0] write_data,
	input write_strobe,
	output reg space_avail,
	output  [WIDTH-1:0] read_data,
	input read_strobe,
	output  data_avail,
	output reg [FIFO_DEPTH-1:0] capacity
	);


   reg [FIFO_DEPTH-1:0] wr_pointer;
   reg [FIFO_DEPTH-1:0] rd_pointer;
   wire [RAM_DEPTH-1:0] address;
   reg 			data_avail_int;
   
   assign 	    read = read_strobe && data_avail_int;
   assign 	    write = write_strobe && space_avail;





   always @(posedge clk)
     if (rst)
       begin
	  capacity <= (1 << FIFO_DEPTH) - 1;
	  wr_pointer <= 0;
	  rd_pointer <= 0;
	  space_avail <= 1;
	  data_avail_int <= 0;
       end
     else	  
       begin


	  space_avail <= ~((capacity == 0) || (read&&write) || ((capacity == 1) && write) );

	  data_avail_int <= ~((capacity == ((1 << FIFO_DEPTH)-1))  || ((capacity == ((1 << FIFO_DEPTH)-2)) && (~write && read))  );
	  wr_pointer <= wr_pointer + write;
	  rd_pointer <= rd_pointer + (~write && read); 
	  capacity <= capacity - write + (~write && read) ;
       end

   assign address = write ? wr_pointer : rd_pointer;
   assign enable = write || read; 






   nobl_if #(.WIDTH(WIDTH),.DEPTH(RAM_DEPTH))
     nobl_if_i1
       (
	.clk(clk),
	.rst(rst),
	.RAM_D_pi(RAM_D_pi),
	.RAM_D_po(RAM_D_po),
	.RAM_D_poe(RAM_D_poe),
	.RAM_A(RAM_A),
	.RAM_WEn(RAM_WEn),
	.RAM_CENn(RAM_CENn),
	.RAM_LDn(RAM_LDn),
	.RAM_OEn(RAM_OEn),
	.RAM_CE1n(RAM_CE1n),
	.address(address),
	.data_out(write_data),
	.data_in(read_data),
	.data_in_valid(data_avail),
	.write(write),
	.enable(enable)
	);

   

endmodule
module nobl_fifo
  #(parameter WIDTH=18,RAM_DEPTH=19,FIFO_DEPTH=19)
    (   
	input clk,
	input rst,
	input [WIDTH-1:0] RAM_D_pi,
	output [WIDTH-1:0] RAM_D_po,
	output RAM_D_poe,
	output [RAM_DEPTH-1:0] RAM_A,
	output RAM_WEn,
	output RAM_CENn,
	output RAM_LDn,
	output RAM_OEn,
	output RAM_CE1n,
	input [WIDTH-1:0] write_data,
	input write_strobe,
	output reg space_avail,
	output  [WIDTH-1:0] read_data,
	input read_strobe,
	output  data_avail,
	output reg [FIFO_DEPTH-1:0] capacity
	);



   reg [FIFO_DEPTH-1:0] wr_pointer;
   reg [FIFO_DEPTH-1:0] rd_pointer;
   wire [RAM_DEPTH-1:0] address;
   reg 			data_avail_int;
   
   assign 	    read = read_strobe && data_avail_int;
   assign 	    write = write_strobe && space_avail;





   always @(posedge clk)
     if (rst)
       begin
	  capacity <= (1 << FIFO_DEPTH) - 1;
	  wr_pointer <= 0;
	  rd_pointer <= 0;
	  space_avail <= 1;
	  data_avail_int <= 0;
       end
     else	  
       begin


	  space_avail <= ~((capacity == 0) || (read&&write) || ((capacity == 1) && write) );

	  data_avail_int <= ~((capacity == ((1 << FIFO_DEPTH)-1))  || ((capacity == ((1 << FIFO_DEPTH)-2)) && (~write && read))  );
	  wr_pointer <= wr_pointer + write;
	  rd_pointer <= rd_pointer + (~write && read); 
	  capacity <= capacity - write + (~write && read) ;
       end

   assign address = write ? wr_pointer : rd_pointer;
   assign enable = write || read; 






   nobl_if #(.WIDTH(WIDTH),.DEPTH(RAM_DEPTH))
     nobl_if_i1
       (
	.clk(clk),
	.rst(rst),
	.RAM_D_pi(RAM_D_pi),
	.RAM_D_po(RAM_D_po),
	.RAM_D_poe(RAM_D_poe),
	.RAM_A(RAM_A),
	.RAM_WEn(RAM_WEn),
	.RAM_CENn(RAM_CENn),
	.RAM_LDn(RAM_LDn),
	.RAM_OEn(RAM_OEn),
	.RAM_CE1n(RAM_CE1n),
	.address(address),
	.data_out(write_data),
	.data_in(read_data),
	.data_in_valid(data_avail),
	.write(write),
	.enable(enable)
	);

   

endmodule