data/full_repos/permissive/449807379/CPU_design/mov.v
1: b'%Warning-WIDTH: data/full_repos/permissive/449807379/CPU_design/mov.v:13: Operator ASSIGN expects 36 bits on the Assign RHS, but Assign RHS\'s CONST \'35\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz\' generates 35 bits.\n                                                                        : ... In instance mov\n    r1 = 35\'bz;\n       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module mov(r1,r2, add_en);
input [31:0] r2;
input add_en;
output reg [35:0] r1;
always @*
begin 
if (add_en ==1'b1)
begin
    r1[31:0]=r2;
    r1[35:32] = 4'b0000;
end
else 
    r1 = 35'bz;

end
endmodule
module mov(r1,r2, add_en);

input [31:0] r2;
input add_en;
output reg [35:0] r1;
always @*
begin 
if (add_en ==1'b1)
begin
    r1[31:0]=r2;
    r1[35:32] = 4'b0000;
end
else 
    r1 = 35'bz;

end
endmodule