data/full_repos/permissive/485721981/sources/simulation/UART_Hello_Tb.sv
1: b'%Error: data/full_repos/permissive/485721981/sources/simulation/UART_Hello_Tb.sv:45: Unsupported: Static in this context\n    static int seed = $urandom + 0;\n    ^~~~~~\n%Error: data/full_repos/permissive/485721981/sources/simulation/UART_Hello_Tb.sv:45: Unsupported or unknown PLI call: $urandom\n    static int seed = $urandom + 0;\n                      ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/485721981/sources/simulation/UART_Hello_Tb.sv:151: Unsupported: Ignoring delay on this delayed statement.\n        #(2 * C_CLK_PERIOD) rRstb <= 1\'b0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/485721981/sources/simulation/UART_Hello_Tb.sv:152: Unsupported: Ignoring delay on this delayed statement.\n        #(10 * C_CLK_PERIOD) rRstb <= 1\'b1;\n        ^\n%Error: data/full_repos/permissive/485721981/sources/simulation/UART_Hello_Tb.sv:159: Unsupported or unknown PLI call: $dist_normal\n        #(0.001 * $dist_normal(seed, 1000.0 * C_CLK_PERIOD / 2, C_CLK_JTR));\n                  ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/485721981/sources/simulation/UART_Hello_Tb.sv:159: Unsupported: Ignoring delay on this delayed statement.\n        #(0.001 * $dist_normal(seed, 1000.0 * C_CLK_PERIOD / 2, C_CLK_JTR));\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/485721981/sources/simulation/UART_Hello_Tb.sv:165: Unsupported: Ignoring delay on this delayed statement.\n        #(C_UART_PERIOD / 2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/485721981/sources/simulation/UART_Hello_Tb.sv:179: Unsupported: Ignoring delay on this delayed statement.\n        #(5 * C_UART_PERIOD);\n        ^\n%Error: data/full_repos/permissive/485721981/sources/simulation/UART_Hello_Tb.sv:180: Unsupported or unknown PLI call: $dist_normal\n        #($dist_normal(seed, 10 * C_UART_PERIOD, 2 * C_UART_PERIOD));\n          ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/485721981/sources/simulation/UART_Hello_Tb.sv:180: Unsupported: Ignoring delay on this delayed statement.\n        #($dist_normal(seed, 10 * C_UART_PERIOD, 2 * C_UART_PERIOD));\n        ^\n%Error: data/full_repos/permissive/485721981/sources/simulation/UART_Hello_Tb.sv:186: syntax error, unexpected \'@\'\n            @(posedge rClk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/485721981/sources/simulation/UART_Hello_Tb.sv:189: Unsupported: Ignoring delay on this delayed statement.\n            #1 rHelloSend <= 1\'b1;\n            ^\n%Error: data/full_repos/permissive/485721981/sources/simulation/UART_Hello_Tb.sv:192: Unsupported: wait statements\n            wait(wHelloBusy == 1\'b1);\n            ^~~~\n%Error: data/full_repos/permissive/485721981/sources/simulation/UART_Hello_Tb.sv:193: syntax error, unexpected \'@\'\n            @(posedge rClk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/485721981/sources/simulation/UART_Hello_Tb.sv:194: Unsupported: Ignoring delay on this delayed statement.\n            #1 rHelloSend <= 1\'b0;\n            ^\n%Error: data/full_repos/permissive/485721981/sources/simulation/UART_Hello_Tb.sv:207: Unsupported or unknown PLI call: $timeformat\n        $timeformat(-9, 0, " ns");\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/485721981/sources/simulation/UART_Hello_Tb.sv:215: syntax error, unexpected \'@\'\n            @(posedge rClk);\n            ^\n%Error: data/full_repos/permissive/485721981/sources/simulation/UART_Hello_Tb.sv:226: Unsupported: wait statements\n            wait(wRxValid == 1\'b0);\n            ^~~~\n%Error: data/full_repos/permissive/485721981/sources/simulation/UART_Hello_Tb.sv:230: syntax error, unexpected \'@\'\n            @(posedge rClk);\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/485721981/sources/simulation/UART_Hello_Tb.sv:231: Unsupported: Ignoring delay on this delayed statement.\n            #1 rRxAck <= 1\'b0;\n            ^\n%Error: data/full_repos/permissive/485721981/sources/simulation/UART_Hello_Tb.sv:238: Unsupported or unknown PLI call: $dist_normal\n        #($dist_normal(seed, 2 * C_UART_PERIOD, C_UART_PERIOD));\n          ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/485721981/sources/simulation/UART_Hello_Tb.sv:238: Unsupported: Ignoring delay on this delayed statement.\n        #($dist_normal(seed, 2 * C_UART_PERIOD, C_UART_PERIOD));\n        ^\n%Error: Exiting due to 12 error(s), 10 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module UART_Hello_tb();

    



    

    parameter C_CLK_FRQ         = 100_000_000;
    parameter C_CLK_JTR         = 50;
    localparam real C_CLK_PERIOD = 1E9 / C_CLK_FRQ;
        

    parameter C_UART_RATE       = 921_600;
    parameter C_UART_DATA_WIDTH = 8;
    parameter C_UART_STOP       = 1;
    parameter C_UART_PARITY     = 0;
    localparam real C_UART_PERIOD = 1E9 / C_UART_RATE;


    parameter C_MSG = "12345";
    parameter C_MSG_LEN = 5;





        

    static int seed = $urandom + 0;
        
    



    

    reg rRstb;
    reg rClk;
    reg rUART_Clk;
    

    wire wTxSend;
    wire wTxBusy;
    wire [C_UART_DATA_WIDTH - 1 : 0] wTxData;
    wire wTxErr;
    wire wTxRx;
    

    reg rHelloSend;
    wire wHelloBusy;
    

    wire wRxValid;
    reg rRxAck;
    wire [C_UART_DATA_WIDTH - 1 : 0] wRxData;
    wire wRxErr;
    reg [C_UART_DATA_WIDTH - 1 : 0] rRxData;
    
   
   





    UART_Tx #(
        .C_CLK_FRQ(C_CLK_FRQ),
        .C_UART_RATE(C_UART_RATE),
        .C_UART_DATA_WIDTH(C_UART_DATA_WIDTH),
        .C_UART_PARITY(C_UART_PARITY),
        .C_UART_STOP(C_UART_STOP) 
    ) DUT_Tx (
        .rstb(rRstb),
        .clk(rClk),
        .busy(wTxBusy),
        .send(wTxSend),
        .data(wTxData),
        .error(wTxErr),
        .tx(wTxRx)
    );
    

    UART_Rx #(
        .C_CLK_FRQ(C_CLK_FRQ),
        .C_UART_RATE(C_UART_RATE),
        .C_UART_DATA_WIDTH(C_UART_DATA_WIDTH), 
        .C_UART_PARITY(C_UART_PARITY),
        .C_UART_STOP(C_UART_STOP) 
    ) DUT_Rx (
        .rstb(rRstb),
        .clk(rClk),
        .data(wRxData),
        .valid(wRxValid),
        .ack(rRxAck),
        .error(wRxErr),
        .rx(wTxRx)
    );
    

    UART_Hello #(
        .C_UART_DATA_WIDTH(C_UART_DATA_WIDTH),
        .C_MSG(C_MSG),
        .C_MSG_LEN(C_MSG_LEN)
    ) DUT_Hello (
        .rstb(rRstb),
        .clk(rClk),
        

        .send(rHelloSend),
        .busy(wHelloBusy),
        

        .txBusy(wTxBusy),
        .txSend(wTxSend),
        .txData(wTxData),
        .txErr(wTxErr)
    );        
    
    



     

    initial begin 
        

        rRstb = 1'b1;
        rClk = 1'b0; 
        rUART_Clk = 1'b0; 
        rHelloSend = 1'b0;
        rRxAck = 1'b0;
             

        #(2 * C_CLK_PERIOD) rRstb <= 1'b0;
        #(10 * C_CLK_PERIOD) rRstb <= 1'b1;
    end
    



    always begin
        #(0.001 * $dist_normal(seed, 1000.0 * C_CLK_PERIOD / 2, C_CLK_JTR));
        rClk = ! rClk;
    end      
    

    always begin
        #(C_UART_PERIOD / 2);
        rUART_Clk <= ! rUART_Clk;
    end      
    
        
    



        

    always begin
        

        #(5 * C_UART_PERIOD);
        #($dist_normal(seed, 10 * C_UART_PERIOD, 2 * C_UART_PERIOD));
                

        if (wHelloBusy == 1'b0) begin
            

            @(posedge rClk);
            

            #1 rHelloSend <= 1'b1;
        

            wait(wHelloBusy == 1'b1);
            @(posedge rClk);
            #1 rHelloSend <= 1'b0;
        end
    end
      
   





    always@ (wRxValid) begin
        

        $timeformat(-9, 0, " ns");
                

        if (wRxValid == 1'b1) begin
            
            $display("\nValid found: %t", $time);
            

            @(posedge rClk);
            

            rRxData <= wRxData;
            $display("Data latched: %t", $time);
            

            rRxAck <= 1'b1;
            $display("Ack asserted: %t", $time);
        

            wait(wRxValid == 1'b0);
            $display("Valid released: %t", $time);
        

            @(posedge rClk);
            #1 rRxAck <= 1'b0;
            $display("Ack released: %t", $time);
        
        end



        #($dist_normal(seed, 2 * C_UART_PERIOD, C_UART_PERIOD));
    end
           
endmodule
module UART_Hello_tb();


    



    

    parameter C_CLK_FRQ         = 100_000_000;
    parameter C_CLK_JTR         = 50;
    localparam real C_CLK_PERIOD = 1E9 / C_CLK_FRQ;
        

    parameter C_UART_RATE       = 921_600;
    parameter C_UART_DATA_WIDTH = 8;
    parameter C_UART_STOP       = 1;
    parameter C_UART_PARITY     = 0;
    localparam real C_UART_PERIOD = 1E9 / C_UART_RATE;


    parameter C_MSG = "12345";
    parameter C_MSG_LEN = 5;





        

    static int seed = $urandom + 0;
        
    



    

    reg rRstb;
    reg rClk;
    reg rUART_Clk;
    

    wire wTxSend;
    wire wTxBusy;
    wire [C_UART_DATA_WIDTH - 1 : 0] wTxData;
    wire wTxErr;
    wire wTxRx;
    

    reg rHelloSend;
    wire wHelloBusy;
    

    wire wRxValid;
    reg rRxAck;
    wire [C_UART_DATA_WIDTH - 1 : 0] wRxData;
    wire wRxErr;
    reg [C_UART_DATA_WIDTH - 1 : 0] rRxData;
    
   
   





    UART_Tx #(
        .C_CLK_FRQ(C_CLK_FRQ),
        .C_UART_RATE(C_UART_RATE),
        .C_UART_DATA_WIDTH(C_UART_DATA_WIDTH),
        .C_UART_PARITY(C_UART_PARITY),
        .C_UART_STOP(C_UART_STOP) 
    ) DUT_Tx (
        .rstb(rRstb),
        .clk(rClk),
        .busy(wTxBusy),
        .send(wTxSend),
        .data(wTxData),
        .error(wTxErr),
        .tx(wTxRx)
    );
    

    UART_Rx #(
        .C_CLK_FRQ(C_CLK_FRQ),
        .C_UART_RATE(C_UART_RATE),
        .C_UART_DATA_WIDTH(C_UART_DATA_WIDTH), 
        .C_UART_PARITY(C_UART_PARITY),
        .C_UART_STOP(C_UART_STOP) 
    ) DUT_Rx (
        .rstb(rRstb),
        .clk(rClk),
        .data(wRxData),
        .valid(wRxValid),
        .ack(rRxAck),
        .error(wRxErr),
        .rx(wTxRx)
    );
    

    UART_Hello #(
        .C_UART_DATA_WIDTH(C_UART_DATA_WIDTH),
        .C_MSG(C_MSG),
        .C_MSG_LEN(C_MSG_LEN)
    ) DUT_Hello (
        .rstb(rRstb),
        .clk(rClk),
        

        .send(rHelloSend),
        .busy(wHelloBusy),
        

        .txBusy(wTxBusy),
        .txSend(wTxSend),
        .txData(wTxData),
        .txErr(wTxErr)
    );        
    
    



     

    initial begin 
        

        rRstb = 1'b1;
        rClk = 1'b0; 
        rUART_Clk = 1'b0; 
        rHelloSend = 1'b0;
        rRxAck = 1'b0;
             

        #(2 * C_CLK_PERIOD) rRstb <= 1'b0;
        #(10 * C_CLK_PERIOD) rRstb <= 1'b1;
    end
    



    always begin
        #(0.001 * $dist_normal(seed, 1000.0 * C_CLK_PERIOD / 2, C_CLK_JTR));
        rClk = ! rClk;
    end      
    

    always begin
        #(C_UART_PERIOD / 2);
        rUART_Clk <= ! rUART_Clk;
    end      
    
        
    



        

    always begin
        

        #(5 * C_UART_PERIOD);
        #($dist_normal(seed, 10 * C_UART_PERIOD, 2 * C_UART_PERIOD));
                

        if (wHelloBusy == 1'b0) begin
            

            @(posedge rClk);
            

            #1 rHelloSend <= 1'b1;
        

            wait(wHelloBusy == 1'b1);
            @(posedge rClk);
            #1 rHelloSend <= 1'b0;
        end
    end
      
   





    always@ (wRxValid) begin
        

        $timeformat(-9, 0, " ns");
                

        if (wRxValid == 1'b1) begin
            
            $display("\nValid found: %t", $time);
            

            @(posedge rClk);
            

            rRxData <= wRxData;
            $display("Data latched: %t", $time);
            

            rRxAck <= 1'b1;
            $display("Ack asserted: %t", $time);
        

            wait(wRxValid == 1'b0);
            $display("Valid released: %t", $time);
        

            @(posedge rClk);
            #1 rRxAck <= 1'b0;
            $display("Ack released: %t", $time);
        
        end



        #($dist_normal(seed, 2 * C_UART_PERIOD, C_UART_PERIOD));
    end
           
endmodule