data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/Execute/ALU.v
1: b'%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/Execute/ALU.v:37: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 32 bits.\n                                                                                                             : ... In instance ALU\n            4\'h8: alur = $signed(ea_lower + eb_lower);    \n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/Execute/ALU.v:38: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 32 bits.\n                                                                                                             : ... In instance ALU\n            4\'h9: alur = $signed(ea_lower - eb_lower);    \n                       ^\n%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/Execute/ALU.v:42: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 32 bits.\n                                                                                                             : ... In instance ALU\n            4\'hD: alur = $signed(ea_lower << eb_lower);   \n                       ^\n%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/Execute/ALU.v:43: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 32 bits.\n                                                                                                             : ... In instance ALU\n            4\'hE: alur = $signed(ea_lower >> eb_lower);   \n                       ^\n%Warning-WIDTH: data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/Execute/ALU.v:44: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 32 bits.\n                                                                                                             : ... In instance ALU\n            4\'hF: alur = $signed(ea_lower >>> eb_lower);  \n                       ^\n%Error: Exiting due to 5 warning(s)\n'
module ALU (
    input signed [63:0] ea, eb,
    input [3:0] ealuc,

    output reg [63:0] alur
);


    reg [31:0] alur_lower;
    

    wire signed [31:0] ea_lower = ea[31:0];
    wire signed [31:0] eb_lower = eb[31:0];

    always @(*) begin
        case (ealuc)
            4'h0: alur = ea + eb;
            4'h1: alur = ea - eb;
            4'h2: alur = ea & eb;
            4'h3: alur = ea | eb;
            4'h4: alur = ea ^ eb;
            4'h5: alur = ea << eb;
            4'h6: alur = ea >> eb;
            4'h7: alur = ea >>> eb;
            
            4'h8: alur = $signed(ea_lower + eb_lower);
            4'h9: alur = $signed(ea_lower - eb_lower);
            4'hA: alur = ea;
            4'hB: alur = eb;
            4'hC: alur = 64'hx;
            4'hD: alur = $signed(ea_lower << eb_lower);
            4'hE: alur = $signed(ea_lower >> eb_lower);
            4'hF: alur = $signed(ea_lower >>> eb_lower);
        endcase
    end

endmodule
module ALU (
    input signed [63:0] ea, eb,
    input [3:0] ealuc,

    output reg [63:0] alur
);



    reg [31:0] alur_lower;
    

    wire signed [31:0] ea_lower = ea[31:0];
    wire signed [31:0] eb_lower = eb[31:0];

    always @(*) begin
        case (ealuc)
            4'h0: alur = ea + eb;
            4'h1: alur = ea - eb;
            4'h2: alur = ea & eb;
            4'h3: alur = ea | eb;
            4'h4: alur = ea ^ eb;
            4'h5: alur = ea << eb;
            4'h6: alur = ea >> eb;
            4'h7: alur = ea >>> eb;
            
            4'h8: alur = $signed(ea_lower + eb_lower);
            4'h9: alur = $signed(ea_lower - eb_lower);
            4'hA: alur = ea;
            4'hB: alur = eb;
            4'hC: alur = 64'hx;
            4'hD: alur = $signed(ea_lower << eb_lower);
            4'hE: alur = $signed(ea_lower >> eb_lower);
            4'hF: alur = $signed(ea_lower >>> eb_lower);
        endcase
    end

endmodule