data/full_repos/permissive/425529933/Proyecto1Digitales2/phy-rx/phy_rx_e.v
data/verilator_xmls/e165d6d7-b9f4-401e-aa69-d53c08f43383.xml
module phy_rx_e(clk_32f, clk_2f_e, clk_4f_e, reset, Data_in_0, Data_in_1, valid_out_e, Data_out_e);
  (* src = "phy_rx_e.v:30" *)
  reg [31:0] _0_;
  (* src = "phy_rx_e.v:30" *)
  reg _1_;
  (* src = "phy_rx_e.v:28" *)
  wire [31:0] Data_c;
  (* src = "phy_rx_e.v:10" *)
  input Data_in_0;
  (* src = "phy_rx_e.v:11" *)
  input Data_in_1;
  (* src = "phy_rx_e.v:24" *)
  wire [7:0] Data_out_0_c;
  (* src = "phy_rx_e.v:26" *)
  wire [7:0] Data_out_1_c;
  (* src = "phy_rx_e.v:13" *)
  output [31:0] Data_out_e;
  reg [31:0] Data_out_e;
  (* src = "phy_rx_e.v:7" *)
  input clk_2f_e;
  (* src = "phy_rx_e.v:6" *)
  input clk_32f;
  (* src = "phy_rx_e.v:8" *)
  input clk_4f_e;
  (* src = "phy_rx_e.v:20" *)
  wire [31:0] lane_0_c;
  (* src = "phy_rx_e.v:22" *)
  wire [31:0] lane_1_c;
  (* src = "phy_rx_e.v:9" *)
  input reset;
  (* src = "phy_rx_e.v:19" *)
  wire valid_0_c;
  (* src = "phy_rx_e.v:21" *)
  wire valid_1_c;
  (* src = "phy_rx_e.v:27" *)
  wire valid_c;
  (* src = "phy_rx_e.v:23" *)
  wire valid_out_0_c;
  (* src = "phy_rx_e.v:25" *)
  wire valid_out_1_c;
  (* src = "phy_rx_e.v:12" *)
  output valid_out_e;
  reg valid_out_e;
  (* module_not_derived = 32'd1 *)
  (* src = "phy_rx_e.v:53" *)
  bits8_32word_e bits8_32word_1 (
    .Data_in(Data_out_0_c),
    .Data_out_e(lane_0_c),
    .clk_4f_e(clk_4f_e),
    .reset(reset),
    .valid_in(valid_out_0_c),
    .valid_out_e(valid_0_c)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "phy_rx_e.v:63" *)
  bits8_32word_e bits8_32word_2 (
    .Data_in(Data_out_1_c),
    .Data_out_e(lane_1_c),
    .clk_4f_e(clk_4f_e),
    .reset(reset),
    .valid_in(valid_out_1_c),
    .valid_out_e(valid_1_c)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "phy_rx_e.v:73" *)
  byte_un_striping_e byte_un_striping_1 (
    .Data_out_e(Data_c),
    .clk_2f_e(clk_2f_e),
    .lane_0(lane_0_c),
    .lane_1(lane_1_c),
    .reset(reset),
    .valid_0(valid_0_c),
    .valid_1(valid_1_c),
    .valid_out_e(valid_c)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "phy_rx_e.v:35" *)
  serial_parallel_e serial_parallel_1 (
    .Data_in(Data_in_0),
    .Data_out_e(Data_out_0_c),
    .clk_32f(clk_32f),
    .reset(reset),
    .valid_out_e(valid_out_0_c)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "phy_rx_e.v:44" *)
  serial_parallel_e serial_parallel_2 (
    .Data_in(Data_in_1),
    .Data_out_e(Data_out_1_c),
    .clk_32f(clk_32f),
    .reset(reset),
    .valid_out_e(valid_out_1_c)
  );
  always @* begin
    _1_ = valid_c;
    _0_ = Data_c;
  end
  always @* begin
      valid_out_e <= _1_;
      Data_out_e <= _0_;
  end
endmodule
module phy_rx_e(clk_32f, clk_2f_e, clk_4f_e, reset, Data_in_0, Data_in_1, valid_out_e, Data_out_e);

  (* src = "phy_rx_e.v:30" *)
  reg [31:0] _0_;
  (* src = "phy_rx_e.v:30" *)
  reg _1_;
  (* src = "phy_rx_e.v:28" *)
  wire [31:0] Data_c;
  (* src = "phy_rx_e.v:10" *)
  input Data_in_0;
  (* src = "phy_rx_e.v:11" *)
  input Data_in_1;
  (* src = "phy_rx_e.v:24" *)
  wire [7:0] Data_out_0_c;
  (* src = "phy_rx_e.v:26" *)
  wire [7:0] Data_out_1_c;
  (* src = "phy_rx_e.v:13" *)
  output [31:0] Data_out_e;
  reg [31:0] Data_out_e;
  (* src = "phy_rx_e.v:7" *)
  input clk_2f_e;
  (* src = "phy_rx_e.v:6" *)
  input clk_32f;
  (* src = "phy_rx_e.v:8" *)
  input clk_4f_e;
  (* src = "phy_rx_e.v:20" *)
  wire [31:0] lane_0_c;
  (* src = "phy_rx_e.v:22" *)
  wire [31:0] lane_1_c;
  (* src = "phy_rx_e.v:9" *)
  input reset;
  (* src = "phy_rx_e.v:19" *)
  wire valid_0_c;
  (* src = "phy_rx_e.v:21" *)
  wire valid_1_c;
  (* src = "phy_rx_e.v:27" *)
  wire valid_c;
  (* src = "phy_rx_e.v:23" *)
  wire valid_out_0_c;
  (* src = "phy_rx_e.v:25" *)
  wire valid_out_1_c;
  (* src = "phy_rx_e.v:12" *)
  output valid_out_e;
  reg valid_out_e;
  (* module_not_derived = 32'd1 *)
  (* src = "phy_rx_e.v:53" *)
  bits8_32word_e bits8_32word_1 (
    .Data_in(Data_out_0_c),
    .Data_out_e(lane_0_c),
    .clk_4f_e(clk_4f_e),
    .reset(reset),
    .valid_in(valid_out_0_c),
    .valid_out_e(valid_0_c)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "phy_rx_e.v:63" *)
  bits8_32word_e bits8_32word_2 (
    .Data_in(Data_out_1_c),
    .Data_out_e(lane_1_c),
    .clk_4f_e(clk_4f_e),
    .reset(reset),
    .valid_in(valid_out_1_c),
    .valid_out_e(valid_1_c)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "phy_rx_e.v:73" *)
  byte_un_striping_e byte_un_striping_1 (
    .Data_out_e(Data_c),
    .clk_2f_e(clk_2f_e),
    .lane_0(lane_0_c),
    .lane_1(lane_1_c),
    .reset(reset),
    .valid_0(valid_0_c),
    .valid_1(valid_1_c),
    .valid_out_e(valid_c)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "phy_rx_e.v:35" *)
  serial_parallel_e serial_parallel_1 (
    .Data_in(Data_in_0),
    .Data_out_e(Data_out_0_c),
    .clk_32f(clk_32f),
    .reset(reset),
    .valid_out_e(valid_out_0_c)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "phy_rx_e.v:44" *)
  serial_parallel_e serial_parallel_2 (
    .Data_in(Data_in_1),
    .Data_out_e(Data_out_1_c),
    .clk_32f(clk_32f),
    .reset(reset),
    .valid_out_e(valid_out_1_c)
  );
  always @* begin
    _1_ = valid_c;
    _0_ = Data_c;
  end
  always @* begin
      valid_out_e <= _1_;
      Data_out_e <= _0_;
  end
endmodule