data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/a23/a23_gc_main.v
1: b"%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/a23/a23_gc_main.v:26: Cannot find file containing module: 'a23_core'\na23_core u_a23_core\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/a23,data/full_repos/permissive/486954482/a23_core\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/a23,data/full_repos/permissive/486954482/a23_core.v\n             data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/a23,data/full_repos/permissive/486954482/a23_core.sv\n             a23_core\n             a23_core.v\n             a23_core.sv\n             obj_dir/a23_core\n             obj_dir/a23_core.v\n             obj_dir/a23_core.sv\n%Error: data/full_repos/permissive/486954482/TinyGarble/circuit_synthesis/a23/a23_gc_main.v:38: Cannot find file containing module: 'a23_mem'\na23_mem\n^~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module a23_gc_main
#(

  parameter CODE_MEM_SIZE  = 64  ,
  parameter G_MEM_SIZE     = 64  ,
  parameter E_MEM_SIZE     = 64  ,
  parameter OUT_MEM_SIZE   = 64  ,
  parameter STACK_MEM_SIZE = 64
)
(
  input                           clk,
  input                           rst,
  input  [CODE_MEM_SIZE*32-1:0]   p_init,
  input  [G_MEM_SIZE   *32-1:0]   g_init,
  input  [E_MEM_SIZE   *32-1:0]   e_init,
  output [OUT_MEM_SIZE *32-1:0]   o,
  output                          terminate
);

wire   [31:0]             m_address;
wire   [31:0]             m_write;
wire                      m_write_en;
wire   [3:0]              m_byte_enable;
wire   [31:0]             m_read;

a23_core u_a23_core
(
  .i_clk             (clk               ),
  .i_rst             (rst               ),
  .o_m_address       (m_address         ),
  .o_m_write         (m_write           ),
  .o_m_write_en      (m_write_en        ),
  .o_m_byte_enable   (m_byte_enable     ),
  .i_m_read          (m_read            ),
  .terminate         (terminate         )
);

a23_mem
#(
  .CODE_MEM_SIZE     (CODE_MEM_SIZE),
  .G_MEM_SIZE        (G_MEM_SIZE),
  .E_MEM_SIZE        (E_MEM_SIZE),
  .OUT_MEM_SIZE      (OUT_MEM_SIZE),
  .STACK_MEM_SIZE    (STACK_MEM_SIZE)
)
u_a23_mem
(
  .i_clk              (clk              ),
  .i_rst              (rst              ),

  .p_init             (p_init           ),
  .g_init             (g_init           ),
  .e_init             (e_init           ),
  .o                  (o                ),

  .i_m_address        (m_address        ),
  .i_m_write          (m_write          ),
  .i_m_write_en       (m_write_en       ),
  .i_m_byte_enable    (m_byte_enable    ),
  .o_m_read           (m_read           )
);




endmodule
module a23_gc_main
#(

  parameter CODE_MEM_SIZE  = 64  ,
  parameter G_MEM_SIZE     = 64  ,
  parameter E_MEM_SIZE     = 64  ,
  parameter OUT_MEM_SIZE   = 64  ,
  parameter STACK_MEM_SIZE = 64
)
(
  input                           clk,
  input                           rst,
  input  [CODE_MEM_SIZE*32-1:0]   p_init,
  input  [G_MEM_SIZE   *32-1:0]   g_init,
  input  [E_MEM_SIZE   *32-1:0]   e_init,
  output [OUT_MEM_SIZE *32-1:0]   o,
  output                          terminate
);


wire   [31:0]             m_address;
wire   [31:0]             m_write;
wire                      m_write_en;
wire   [3:0]              m_byte_enable;
wire   [31:0]             m_read;

a23_core u_a23_core
(
  .i_clk             (clk               ),
  .i_rst             (rst               ),
  .o_m_address       (m_address         ),
  .o_m_write         (m_write           ),
  .o_m_write_en      (m_write_en        ),
  .o_m_byte_enable   (m_byte_enable     ),
  .i_m_read          (m_read            ),
  .terminate         (terminate         )
);

a23_mem
#(
  .CODE_MEM_SIZE     (CODE_MEM_SIZE),
  .G_MEM_SIZE        (G_MEM_SIZE),
  .E_MEM_SIZE        (E_MEM_SIZE),
  .OUT_MEM_SIZE      (OUT_MEM_SIZE),
  .STACK_MEM_SIZE    (STACK_MEM_SIZE)
)
u_a23_mem
(
  .i_clk              (clk              ),
  .i_rst              (rst              ),

  .p_init             (p_init           ),
  .g_init             (g_init           ),
  .e_init             (e_init           ),
  .o                  (o                ),

  .i_m_address        (m_address        ),
  .i_m_write          (m_write          ),
  .i_m_write_en       (m_write_en       ),
  .i_m_byte_enable    (m_byte_enable    ),
  .o_m_read           (m_read           )
);




endmodule