data/full_repos/permissive/415103295/verilog/dbg/fwvexrisc_dbg_bfm.v
1: b"%Error: data/full_repos/permissive/415103295/verilog/dbg/fwvexrisc_dbg_bfm.v:34: Cannot find file containing module: 'riscv_debug_bfm'\n riscv_debug_bfm u_dbg (\n ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/415103295/verilog/dbg,data/full_repos/permissive/415103295/riscv_debug_bfm\n             data/full_repos/permissive/415103295/verilog/dbg,data/full_repos/permissive/415103295/riscv_debug_bfm.v\n             data/full_repos/permissive/415103295/verilog/dbg,data/full_repos/permissive/415103295/riscv_debug_bfm.sv\n             riscv_debug_bfm\n             riscv_debug_bfm.v\n             riscv_debug_bfm.sv\n             obj_dir/riscv_debug_bfm\n             obj_dir/riscv_debug_bfm.v\n             obj_dir/riscv_debug_bfm.sv\n%Error: Exiting due to 1 error(s)\n"
module fwvexrisc_dbg_bfm(
		input			   clock,
		input			   reset,
		input              rvfi_valid,
		input     [63:0]   rvfi_order,
		input     [31:0]   rvfi_insn,
		input              rvfi_trap,
		input              rvfi_halt,
		input              rvfi_intr,
		input     [4:0]    rvfi_rs1_addr,
		input     [31:0]   rvfi_rs1_rdata,
		input     [4:0]    rvfi_rs2_addr,
		input     [31:0]   rvfi_rs2_rdata,
		input     [4:0]    rvfi_rd_addr,
		input     [31:0]   rvfi_rd_wdata,
		input     [31:0]   rvfi_pc_rdata,
		input     [31:0]   rvfi_pc_wdata,
		input     [31:0]   rvfi_mem_addr,
		input     [3:0]    rvfi_mem_rmask,
		input     [3:0]    rvfi_mem_wmask,
		input     [31:0]   rvfi_mem_rdata,
		input     [31:0]   rvfi_mem_wdata);

	riscv_debug_bfm u_dbg (
			.clock(				clock),
			.reset(				reset),
			.valid( 			rvfi_valid),
			.instr( 			rvfi_insn),
			.intr(				rvfi_intr),
			.iret(				0),
			.rd_addr( 			rvfi_rd_addr),
			.rd_wdata( 			rvfi_rd_wdata),
			.pc(				rvfi_pc_rdata),
			.mem_addr(			rvfi_mem_addr),
			.mem_rmask(			rvfi_mem_rmask),
			.mem_wmask(			rvfi_mem_wmask),
			.mem_data(			rvfi_mem_wdata)
		);	

endmodule
module fwvexrisc_dbg_bfm(
		input			   clock,
		input			   reset,
		input              rvfi_valid,
		input     [63:0]   rvfi_order,
		input     [31:0]   rvfi_insn,
		input              rvfi_trap,
		input              rvfi_halt,
		input              rvfi_intr,
		input     [4:0]    rvfi_rs1_addr,
		input     [31:0]   rvfi_rs1_rdata,
		input     [4:0]    rvfi_rs2_addr,
		input     [31:0]   rvfi_rs2_rdata,
		input     [4:0]    rvfi_rd_addr,
		input     [31:0]   rvfi_rd_wdata,
		input     [31:0]   rvfi_pc_rdata,
		input     [31:0]   rvfi_pc_wdata,
		input     [31:0]   rvfi_mem_addr,
		input     [3:0]    rvfi_mem_rmask,
		input     [3:0]    rvfi_mem_wmask,
		input     [31:0]   rvfi_mem_rdata,
		input     [31:0]   rvfi_mem_wdata);


	riscv_debug_bfm u_dbg (
			.clock(				clock),
			.reset(				reset),
			.valid( 			rvfi_valid),
			.instr( 			rvfi_insn),
			.intr(				rvfi_intr),
			.iret(				0),
			.rd_addr( 			rvfi_rd_addr),
			.rd_wdata( 			rvfi_rd_wdata),
			.pc(				rvfi_pc_rdata),
			.mem_addr(			rvfi_mem_addr),
			.mem_rmask(			rvfi_mem_rmask),
			.mem_wmask(			rvfi_mem_wmask),
			.mem_data(			rvfi_mem_wdata)
		);	

endmodule