data/full_repos/permissive/40989439/AdaptevaLib/src/eclock/hdl/eclock.v
1: b"%Error: data/full_repos/permissive/40989439/AdaptevaLib/src/eclock/hdl/eclock.v:85: Cannot find file containing module: 'PLLE2_BASE'\n   PLLE2_BASE\n   ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/40989439/AdaptevaLib/src/eclock/hdl,data/full_repos/permissive/40989439/PLLE2_BASE\n             data/full_repos/permissive/40989439/AdaptevaLib/src/eclock/hdl,data/full_repos/permissive/40989439/PLLE2_BASE.v\n             data/full_repos/permissive/40989439/AdaptevaLib/src/eclock/hdl,data/full_repos/permissive/40989439/PLLE2_BASE.sv\n             PLLE2_BASE\n             PLLE2_BASE.v\n             PLLE2_BASE.sv\n             obj_dir/PLLE2_BASE\n             obj_dir/PLLE2_BASE.v\n             obj_dir/PLLE2_BASE.sv\n%Error: data/full_repos/permissive/40989439/AdaptevaLib/src/eclock/hdl/eclock.v:137: Cannot find file containing module: 'BUFG'\n   BUFG cclk_buf\n   ^~~~\n%Error: data/full_repos/permissive/40989439/AdaptevaLib/src/eclock/hdl/eclock.v:141: Cannot find file containing module: 'BUFG'\n   BUFG cclk_p_buf\n   ^~~~\n%Error: data/full_repos/permissive/40989439/AdaptevaLib/src/eclock/hdl/eclock.v:145: Cannot find file containing module: 'BUFG'\n   BUFG lclk_s_buf\n   ^~~~\n%Error: data/full_repos/permissive/40989439/AdaptevaLib/src/eclock/hdl/eclock.v:149: Cannot find file containing module: 'BUFG'\n   BUFG lclk_out_buf\n   ^~~~\n%Error: data/full_repos/permissive/40989439/AdaptevaLib/src/eclock/hdl/eclock.v:153: Cannot find file containing module: 'BUFG'\n   BUFG lclk_p_buf\n   ^~~~\n%Error: data/full_repos/permissive/40989439/AdaptevaLib/src/eclock/hdl/eclock.v:184: Cannot find file containing module: 'OSERDESE2'\n   OSERDESE2 \n   ^~~~~~~~~\n%Error: data/full_repos/permissive/40989439/AdaptevaLib/src/eclock/hdl/eclock.v:244: Cannot find file containing module: 'OBUFDS'\n   OBUFDS\n   ^~~~~~\n%Error: Exiting due to 8 error(s)\n"
module eclock (

   CCLK_P, CCLK_N, lclk_s, lclk_out, lclk_p,

   clkin, reset, ecfg_cclk_en, ecfg_cclk_div, ecfg_cclk_pllcfg
   );





   parameter  CLKIN_PERIOD = 10.000;
   parameter  CLKIN_DIVIDE = 1;
   parameter  VCO_MULT = 12;
   parameter  CCLK_DIVIDE = 2;
   parameter  LCLK_DIVIDE = 4;
   parameter  FEATURE_CCLK_DIV = 1'b1;
   parameter  IOSTD_ELINK = "LVDS_25";
   

   input        clkin;
   input        reset;
   

   input        ecfg_cclk_en;
   input [3:0]  ecfg_cclk_div;
   input [3:0]  ecfg_cclk_pllcfg;

   output       CCLK_P, CCLK_N;
   output       lclk_s;
   output       lclk_out;
   output       lclk_p;


   wire         cclk_src;
   wire         cclk_base;
   wire         cclk_p_src;
   wire         cclk_p;
   wire         cclk;
   wire         lclk_s_src;
   wire         lclk_out_src;
   wire         lclk_p_src;
   wire         clkfb;
   

   PLLE2_BASE
     #(
       .BANDWIDTH("OPTIMIZED"),
       .CLKFBOUT_MULT(VCO_MULT),
       .CLKFBOUT_PHASE(0.0),
       .CLKIN1_PERIOD(CLKIN_PERIOD),

       .CLKOUT0_DIVIDE(CCLK_DIVIDE),
       .CLKOUT1_DIVIDE(LCLK_DIVIDE),
       .CLKOUT2_DIVIDE(LCLK_DIVIDE),
       .CLKOUT3_DIVIDE(LCLK_DIVIDE * 4),
       .CLKOUT4_DIVIDE(CCLK_DIVIDE * 4),
       .CLKOUT5_DIVIDE(128),

       .CLKOUT0_DUTY_CYCLE(0.5),
       .CLKOUT1_DUTY_CYCLE(0.5),
       .CLKOUT2_DUTY_CYCLE(0.5),
       .CLKOUT3_DUTY_CYCLE(0.5),
       .CLKOUT4_DUTY_CYCLE(0.5),
       .CLKOUT5_DUTY_CYCLE(0.5),

       .CLKOUT0_PHASE(0.0),
       .CLKOUT1_PHASE(0.0),
       .CLKOUT2_PHASE(90.0),
       .CLKOUT3_PHASE(0.0),
       .CLKOUT4_PHASE(0.0),
       .CLKOUT5_PHASE(0.0),
       .DIVCLK_DIVIDE(CLKIN_DIVIDE),
       .REF_JITTER1(0.01),
       .STARTUP_WAIT("FALSE")
       ) eclk_pll
       (

        .CLKOUT0(cclk_src),
        .CLKOUT1(lclk_s_src),
        .CLKOUT2(lclk_out_src),
        .CLKOUT3(lclk_p_src),
        .CLKOUT4(cclk_p_src),
        .CLKOUT5(),

        .CLKFBOUT(clkfb),
        .LOCKED(),
        .CLKIN1(clkin),

        .PWRDWN(1'b0),
        .RST(1'b0),

        .CLKFBIN(clkfb)
        );



   BUFG cclk_buf
     (.O   (cclk_base),
      .I   (cclk_src));

   BUFG cclk_p_buf
     (.O   (cclk_p),
      .I   (cclk_p_src));
   
   BUFG lclk_s_buf
     (.O   (lclk_s),
      .I   (lclk_s_src));

   BUFG lclk_out_buf
     (.O   (lclk_out),
      .I   (lclk_out_src));

   BUFG lclk_p_buf
     (.O   (lclk_p),
      .I   (lclk_p_src));

generate
   if( FEATURE_CCLK_DIV ) begin : gen_cclk_div


   wire      rxi_cclk_out;
   reg [8:1] cclk_pattern;
   reg [3:0] clk_div_sync;
   reg       enb_sync;
   
   always @ (posedge cclk_p) begin

      clk_div_sync <= ecfg_cclk_div;
      enb_sync     <= ecfg_cclk_en;

      if(enb_sync)
        case(clk_div_sync)
          4'h0:    cclk_pattern <= 8'd0;
          4'h7:    cclk_pattern <= 8'b10101010;
          4'h6:    cclk_pattern <= 8'b11001100;
          4'h5:    cclk_pattern <= 8'b11110000;
          default: cclk_pattern <= {8{~cclk_pattern[1]}};
        endcase
      else
        cclk_pattern <= 8'b00000000;

   end
         
   OSERDESE2 
     #(
       .DATA_RATE_OQ("DDR"),
       .DATA_RATE_TQ("SDR"),
       .DATA_WIDTH(8),
       .INIT_OQ(1'b0),
       .INIT_TQ(1'b0),
       .SERDES_MODE("MASTER"),
       .SRVAL_OQ(1'b0),
       .SRVAL_TQ(1'b0),
       .TBYTE_CTL("FALSE"),
       .TBYTE_SRC("FALSE"),
       .TRISTATE_WIDTH(1)
       ) OSERDESE2_inst 
       (
        .OFB(),
        .OQ(cclk),
        .SHIFTOUT1(),
        .SHIFTOUT2(),
        .TBYTEOUT(),
        .TFB(),
        .TQ(),
        .CLK(cclk_base),
        .CLKDIV(cclk_p),
        .D1(cclk_pattern[1]),
        .D2(cclk_pattern[2]),
        .D3(cclk_pattern[3]),
        .D4(cclk_pattern[4]),
        .D5(cclk_pattern[5]),
        .D6(cclk_pattern[6]),
        .D7(cclk_pattern[7]),
        .D8(cclk_pattern[8]),
        .OCE(1'b1),
        .RST(reset),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(1'b0),
        .TCE(1'b0)
        );

   end else begin : gen_fixed_cclk

   reg       enb_sync;

   always @ (posedge cclk_p)
      enb_sync     <= ecfg_cclk_en;



   assign cclk = cclk_base & enb_sync;
   
   end
endgenerate
   


   OBUFDS
     #(.IOSTANDARD (IOSTD_ELINK)) 
   obufds_cclk_inst
     (.O   (CCLK_P),
	  .OB  (CCLK_N),
	  .I   (cclk));
        
endmodule
module eclock (

   CCLK_P, CCLK_N, lclk_s, lclk_out, lclk_p,

   clkin, reset, ecfg_cclk_en, ecfg_cclk_div, ecfg_cclk_pllcfg
   );






   parameter  CLKIN_PERIOD = 10.000;
   parameter  CLKIN_DIVIDE = 1;
   parameter  VCO_MULT = 12;
   parameter  CCLK_DIVIDE = 2;
   parameter  LCLK_DIVIDE = 4;
   parameter  FEATURE_CCLK_DIV = 1'b1;
   parameter  IOSTD_ELINK = "LVDS_25";
   

   input        clkin;
   input        reset;
   

   input        ecfg_cclk_en;
   input [3:0]  ecfg_cclk_div;
   input [3:0]  ecfg_cclk_pllcfg;

   output       CCLK_P, CCLK_N;
   output       lclk_s;
   output       lclk_out;
   output       lclk_p;


   wire         cclk_src;
   wire         cclk_base;
   wire         cclk_p_src;
   wire         cclk_p;
   wire         cclk;
   wire         lclk_s_src;
   wire         lclk_out_src;
   wire         lclk_p_src;
   wire         clkfb;
   

   PLLE2_BASE
     #(
       .BANDWIDTH("OPTIMIZED"),
       .CLKFBOUT_MULT(VCO_MULT),
       .CLKFBOUT_PHASE(0.0),
       .CLKIN1_PERIOD(CLKIN_PERIOD),

       .CLKOUT0_DIVIDE(CCLK_DIVIDE),
       .CLKOUT1_DIVIDE(LCLK_DIVIDE),
       .CLKOUT2_DIVIDE(LCLK_DIVIDE),
       .CLKOUT3_DIVIDE(LCLK_DIVIDE * 4),
       .CLKOUT4_DIVIDE(CCLK_DIVIDE * 4),
       .CLKOUT5_DIVIDE(128),

       .CLKOUT0_DUTY_CYCLE(0.5),
       .CLKOUT1_DUTY_CYCLE(0.5),
       .CLKOUT2_DUTY_CYCLE(0.5),
       .CLKOUT3_DUTY_CYCLE(0.5),
       .CLKOUT4_DUTY_CYCLE(0.5),
       .CLKOUT5_DUTY_CYCLE(0.5),

       .CLKOUT0_PHASE(0.0),
       .CLKOUT1_PHASE(0.0),
       .CLKOUT2_PHASE(90.0),
       .CLKOUT3_PHASE(0.0),
       .CLKOUT4_PHASE(0.0),
       .CLKOUT5_PHASE(0.0),
       .DIVCLK_DIVIDE(CLKIN_DIVIDE),
       .REF_JITTER1(0.01),
       .STARTUP_WAIT("FALSE")
       ) eclk_pll
       (

        .CLKOUT0(cclk_src),
        .CLKOUT1(lclk_s_src),
        .CLKOUT2(lclk_out_src),
        .CLKOUT3(lclk_p_src),
        .CLKOUT4(cclk_p_src),
        .CLKOUT5(),

        .CLKFBOUT(clkfb),
        .LOCKED(),
        .CLKIN1(clkin),

        .PWRDWN(1'b0),
        .RST(1'b0),

        .CLKFBIN(clkfb)
        );



   BUFG cclk_buf
     (.O   (cclk_base),
      .I   (cclk_src));

   BUFG cclk_p_buf
     (.O   (cclk_p),
      .I   (cclk_p_src));
   
   BUFG lclk_s_buf
     (.O   (lclk_s),
      .I   (lclk_s_src));

   BUFG lclk_out_buf
     (.O   (lclk_out),
      .I   (lclk_out_src));

   BUFG lclk_p_buf
     (.O   (lclk_p),
      .I   (lclk_p_src));

generate
   if( FEATURE_CCLK_DIV ) begin : gen_cclk_div


   wire      rxi_cclk_out;
   reg [8:1] cclk_pattern;
   reg [3:0] clk_div_sync;
   reg       enb_sync;
   
   always @ (posedge cclk_p) begin

      clk_div_sync <= ecfg_cclk_div;
      enb_sync     <= ecfg_cclk_en;

      if(enb_sync)
        case(clk_div_sync)
          4'h0:    cclk_pattern <= 8'd0;
          4'h7:    cclk_pattern <= 8'b10101010;
          4'h6:    cclk_pattern <= 8'b11001100;
          4'h5:    cclk_pattern <= 8'b11110000;
          default: cclk_pattern <= {8{~cclk_pattern[1]}};
        endcase
      else
        cclk_pattern <= 8'b00000000;

   end
         
   OSERDESE2 
     #(
       .DATA_RATE_OQ("DDR"),
       .DATA_RATE_TQ("SDR"),
       .DATA_WIDTH(8),
       .INIT_OQ(1'b0),
       .INIT_TQ(1'b0),
       .SERDES_MODE("MASTER"),
       .SRVAL_OQ(1'b0),
       .SRVAL_TQ(1'b0),
       .TBYTE_CTL("FALSE"),
       .TBYTE_SRC("FALSE"),
       .TRISTATE_WIDTH(1)
       ) OSERDESE2_inst 
       (
        .OFB(),
        .OQ(cclk),
        .SHIFTOUT1(),
        .SHIFTOUT2(),
        .TBYTEOUT(),
        .TFB(),
        .TQ(),
        .CLK(cclk_base),
        .CLKDIV(cclk_p),
        .D1(cclk_pattern[1]),
        .D2(cclk_pattern[2]),
        .D3(cclk_pattern[3]),
        .D4(cclk_pattern[4]),
        .D5(cclk_pattern[5]),
        .D6(cclk_pattern[6]),
        .D7(cclk_pattern[7]),
        .D8(cclk_pattern[8]),
        .OCE(1'b1),
        .RST(reset),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(1'b0),
        .TCE(1'b0)
        );

   end else begin : gen_fixed_cclk

   reg       enb_sync;

   always @ (posedge cclk_p)
      enb_sync     <= ecfg_cclk_en;



   assign cclk = cclk_base & enb_sync;
   
   end
endgenerate
   


   OBUFDS
     #(.IOSTANDARD (IOSTD_ELINK)) 
   obufds_cclk_inst
     (.O   (CCLK_P),
	  .OB  (CCLK_N),
	  .I   (cclk));
        
endmodule