data/full_repos/permissive/42434302/ivltests/pr1645518.v
1: b'%Error: data/full_repos/permissive/42434302/ivltests/pr1645518.v:24: Unsupported or unknown PLI call: $monitor\n      $monitor ($time,,\n      ^~~~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/pr1645518.v:24: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n      $monitor ($time,,\n                      ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1645518.v:28: Unsupported: Ignoring delay on this delayed statement.\n      #10 A = 0; B = 0; C = 0; D = 0;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1645518.v:29: Unsupported: Ignoring delay on this delayed statement.\n      #10 D = 1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1645518.v:30: Unsupported: Ignoring delay on this delayed statement.\n      #10 C = 1; D = 0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/pr1645518.v:31: Unsupported: Ignoring delay on this delayed statement.\n      #10 $finish;\n      ^\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module binaryToESeg
  (input A, B, C, D,
   output eSeg);
   nand #1
     g1 (p1, C, ~D),
     g2 (p2, A, B),
     g3 (p3, ~B, ~D),
     g4 (p4, A, C),
     g5 (eSeg, p1, p2, p3, p4);
endmodule
module binaryToESeg
  (input A, B, C, D,
   output eSeg);

   nand #1
     g1 (p1, C, ~D),
     g2 (p2, A, B),
     g3 (p3, ~B, ~D),
     g4 (p4, A, C),
     g5 (eSeg, p1, p2, p3, p4);
endmodule