data/full_repos/permissive/449370139/verilog_code/triaxial.v
data/verilator_xmls/1f840527-af8d-4052-ab41-a5a100bd716f.xml
module triaxial (
    input clk,
    input I_rst_n,
    input [4:0] set,
    input running,
    output reg [4:0] runstate
);

always @(posedge clk) begin
    if(!I_rst_n)begin
        runstate<=5'b00000;
    end
    else if(!running)begin
        runstate<=5'b00000;
    end
    else begin
        if(set[0])begin
            runstate<=5'b00001;
        end
        else if(set[1])begin
            runstate<=5'b00010;
        end
        else if(set[2])begin
            runstate<=5'b00100;
        end
        else if(set[3])begin
            runstate<=5'b01000;
        end
        else if(set[4])begin
            runstate<=5'b10000;
        end
        else begin
            runstate<=5'b00000;
        end
    end
end

endmodule
module triaxial (
    input clk,
    input I_rst_n,
    input [4:0] set,
    input running,
    output reg [4:0] runstate
);


always @(posedge clk) begin
    if(!I_rst_n)begin
        runstate<=5'b00000;
    end
    else if(!running)begin
        runstate<=5'b00000;
    end
    else begin
        if(set[0])begin
            runstate<=5'b00001;
        end
        else if(set[1])begin
            runstate<=5'b00010;
        end
        else if(set[2])begin
            runstate<=5'b00100;
        end
        else if(set[3])begin
            runstate<=5'b01000;
        end
        else if(set[4])begin
            runstate<=5'b10000;
        end
        else begin
            runstate<=5'b00000;
        end
    end
end

endmodule