data/full_repos/permissive/500001079/blink_cu.v
data/verilator_xmls/9067f5cc-6cf6-49c4-9b6e-62e5885b222d.xml
module top (CLK, LED1, LED2, LED3, LED4, LED5, LED6, LED7, LED8);

    input CLK;
    output LED1;
    output LED2;
    output LED3;
    output LED4;
    output LED5;
    output LED6;
    output LED7;
    output LED8;


    reg [31:0] counter = 32'b0;


    assign LED1 = counter[18];
    assign LED2 = counter[19];
    assign LED3 = counter[20];
    assign LED4 = counter[21];
    assign LED5 = counter[22];
    assign LED6 = counter[23];
    assign LED7 = counter[24];
    assign LED8 = counter[25];


    always @ (posedge CLK) begin
        counter <= counter + 1;
    end

endmodule
module top (CLK, LED1, LED2, LED3, LED4, LED5, LED6, LED7, LED8);


    input CLK;
    output LED1;
    output LED2;
    output LED3;
    output LED4;
    output LED5;
    output LED6;
    output LED7;
    output LED8;


    reg [31:0] counter = 32'b0;


    assign LED1 = counter[18];
    assign LED2 = counter[19];
    assign LED3 = counter[20];
    assign LED4 = counter[21];
    assign LED5 = counter[22];
    assign LED6 = counter[23];
    assign LED7 = counter[24];
    assign LED8 = counter[25];


    always @ (posedge CLK) begin
        counter <= counter + 1;
    end

endmodule