data/full_repos/permissive/499373944/verilog/dv/wavelet_transform/wavelet_transform_tb.v
1: b'%Error: data/full_repos/permissive/499373944/verilog/dv/wavelet_transform/wavelet_transform_tb.v:22: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile ("wavelet_transform.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/499373944/verilog/dv/wavelet_transform/wavelet_transform_tb.v:23: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars (0, wavelet_transform_tb);\n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/499373944/verilog/dv/wavelet_transform/wavelet_transform_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module wavelet_transform_tb;
    initial begin
        $dumpfile ("wavelet_transform.vcd");
        $dumpvars (0, wavelet_transform_tb);
        #1;
    end

    reg clk;
    reg RSTB;
    reg power1, power2;
    reg power3, power4;


    wire design_reset = uut.mprj.la_data_in[32];

    wire gpio;
    wire [37:0] mprj_io;

    wire i_data_clk;
    wire [7:0] i_value;
    wire [7:0] i_select_output_channel;



    assign mprj_io[8] = i_data_clk;
    assign mprj_io[16:9] = i_value;
    assign mprj_io[24:17] = i_select_output_channel;


    wire [7:0] o_multiplexed_wavelet_out = mprj_io[32:25];
    wire o_active = mprj_io[33];



    wire flash_csb;
    wire flash_clk;
    wire flash_io0;
    wire flash_io1;

    wire VDD3V3 = power1;
    wire VDD1V8 = power2;
    wire USER_VDD3V3 = power3;
    wire USER_VDD1V8 = power4;
    wire VSS = 1'b0;

    caravel uut (
        .vddio    (VDD3V3),
        .vssio    (VSS),
        .vdda     (VDD3V3),
        .vssa     (VSS),
        .vccd     (VDD1V8),
        .vssd     (VSS),
        .vdda1    (USER_VDD3V3),
        .vdda2    (USER_VDD3V3),
        .vssa1    (VSS),
        .vssa2    (VSS),
        .vccd1    (USER_VDD1V8),
        .vccd2    (USER_VDD1V8),
        .vssd1    (VSS),
        .vssd2    (VSS),
        .clock    (clk),
        .gpio     (gpio),
        .mprj_io  (mprj_io),
        .flash_csb(flash_csb),
        .flash_clk(flash_clk),
        .flash_io0(flash_io0),
        .flash_io1(flash_io1),
        .resetb   (RSTB)
    );

    spiflash #(
        .FILENAME("wavelet_transform.hex")
    ) spiflash (
        .csb(flash_csb),
        .clk(flash_clk),
        .io0(flash_io0),
        .io1(flash_io1),
        .io2(),
        .io3()
    );

endmodule
module wavelet_transform_tb;

    initial begin
        $dumpfile ("wavelet_transform.vcd");
        $dumpvars (0, wavelet_transform_tb);
        #1;
    end

    reg clk;
    reg RSTB;
    reg power1, power2;
    reg power3, power4;


    wire design_reset = uut.mprj.la_data_in[32];

    wire gpio;
    wire [37:0] mprj_io;

    wire i_data_clk;
    wire [7:0] i_value;
    wire [7:0] i_select_output_channel;



    assign mprj_io[8] = i_data_clk;
    assign mprj_io[16:9] = i_value;
    assign mprj_io[24:17] = i_select_output_channel;


    wire [7:0] o_multiplexed_wavelet_out = mprj_io[32:25];
    wire o_active = mprj_io[33];



    wire flash_csb;
    wire flash_clk;
    wire flash_io0;
    wire flash_io1;

    wire VDD3V3 = power1;
    wire VDD1V8 = power2;
    wire USER_VDD3V3 = power3;
    wire USER_VDD1V8 = power4;
    wire VSS = 1'b0;

    caravel uut (
        .vddio    (VDD3V3),
        .vssio    (VSS),
        .vdda     (VDD3V3),
        .vssa     (VSS),
        .vccd     (VDD1V8),
        .vssd     (VSS),
        .vdda1    (USER_VDD3V3),
        .vdda2    (USER_VDD3V3),
        .vssa1    (VSS),
        .vssa2    (VSS),
        .vccd1    (USER_VDD1V8),
        .vccd2    (USER_VDD1V8),
        .vssd1    (VSS),
        .vssd2    (VSS),
        .clock    (clk),
        .gpio     (gpio),
        .mprj_io  (mprj_io),
        .flash_csb(flash_csb),
        .flash_clk(flash_clk),
        .flash_io0(flash_io0),
        .flash_io1(flash_io1),
        .resetb   (RSTB)
    );

    spiflash #(
        .FILENAME("wavelet_transform.hex")
    ) spiflash (
        .csb(flash_csb),
        .clk(flash_clk),
        .io0(flash_io0),
        .io1(flash_io1),
        .io2(),
        .io3()
    );

endmodule