data/full_repos/permissive/493019833/test/testcase/firrtl/TestMem/sbt/TestMem.v
data/verilator_xmls/a51779bb-37f9-46c0-b7dd-33f8b74a7d0a.xml
module TestMem(
  input   clock,
  input   reset
);
endmodule
module TestMem(
  input   clock,
  input   reset
);

endmodule