data/full_repos/permissive/479997390/src/MEM.v
1: b"%Error: data/full_repos/permissive/479997390/src/MEM.v:31: Cannot find file containing module: 'DataMem_4k'\n  DataMem_4k U_DM4K (\n  ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/479997390/src,data/full_repos/permissive/479997390/DataMem_4k\n             data/full_repos/permissive/479997390/src,data/full_repos/permissive/479997390/DataMem_4k.v\n             data/full_repos/permissive/479997390/src,data/full_repos/permissive/479997390/DataMem_4k.sv\n             DataMem_4k\n             DataMem_4k.v\n             DataMem_4k.sv\n             obj_dir/DataMem_4k\n             obj_dir/DataMem_4k.v\n             obj_dir/DataMem_4k.sv\n%Error: Exiting due to 1 error(s)\n"
module MEM (
  clk, 
  ALUOutIn, 

  RegData2, WriteRegAddrIn,

  MemRead, MemWrite, 

  MemToRegIn, RegWriteIn,
  DataOut, ALUOutOut,

  MemToRegOut, RegWriteOut,
  WriteRegAddrOut
);

  input clk;
  input [31:0] ALUOutIn,RegData2;
  input [4:0] WriteRegAddrIn;

  input MemRead, MemWrite;
  input MemToRegIn, RegWriteIn;
  output [31:0] DataOut, ALUOutOut;
  outputMemToRegOut, RegWriteOut;
  output [4:0] WriteRegAddrOut;

  assign ALUOutOut = ALUOutIn;
  assign MemToRegOut = MemToRegIn;
  assign RegWriteOut = RegWriteIn;
  assign WriteRegAddrOut = WriteRegAddrIn;

  DataMem_4k U_DM4K (
    .DataAddr(ALUOutIn[11:2]),
    .WriteData(RegData2),
    .DMWr(MemWrite),
    .DMRd(MemRead),
    .clk(clk),
    .DataOut(DataOut)
  );













  
endmodule
module MEM (
  clk, 
  ALUOutIn, 

  RegData2, WriteRegAddrIn,

  MemRead, MemWrite, 

  MemToRegIn, RegWriteIn,
  DataOut, ALUOutOut,

  MemToRegOut, RegWriteOut,
  WriteRegAddrOut
);


  input clk;
  input [31:0] ALUOutIn,RegData2;
  input [4:0] WriteRegAddrIn;

  input MemRead, MemWrite;
  input MemToRegIn, RegWriteIn;
  output [31:0] DataOut, ALUOutOut;
  outputMemToRegOut, RegWriteOut;
  output [4:0] WriteRegAddrOut;

  assign ALUOutOut = ALUOutIn;
  assign MemToRegOut = MemToRegIn;
  assign RegWriteOut = RegWriteIn;
  assign WriteRegAddrOut = WriteRegAddrIn;

  DataMem_4k U_DM4K (
    .DataAddr(ALUOutIn[11:2]),
    .WriteData(RegData2),
    .DMWr(MemWrite),
    .DMRd(MemRead),
    .clk(clk),
    .DataOut(DataOut)
  );













  
endmodule