data/full_repos/permissive/46625639/pong.v
1: b'%Warning-WIDTH: data/full_repos/permissive/46625639/pong.v:438: Operator ADD expects 11 bits on the RHS, but RHS\'s VARREF \'speed\' generates 5 bits.\n                                                              : ... In instance pong.gl.bp\n    value_x <= value_x + speed;\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/46625639/pong.v:442: Operator SUB expects 11 bits on the RHS, but RHS\'s VARREF \'speed\' generates 5 bits.\n                                                              : ... In instance pong.gl.bp\n    value_x <= value_x - speed;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/46625639/pong.v:448: Operator ADD expects 11 bits on the RHS, but RHS\'s VARREF \'speed\' generates 5 bits.\n                                                              : ... In instance pong.gl.bp\n    value_y <= value_y + speed;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/46625639/pong.v:452: Operator SUB expects 11 bits on the RHS, but RHS\'s VARREF \'speed\' generates 5 bits.\n                                                              : ... In instance pong.gl.bp\n    value_y <= value_y - speed;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/46625639/pong.v:388: Operator SUB expects 11 bits on the RHS, but RHS\'s VARREF \'speed\' generates 5 bits.\n                                                              : ... In instance pong.gl.b2\n     value <= value - speed;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/46625639/pong.v:386: Operator SUB expects 32 or 11 bits on the RHS, but RHS\'s VARREF \'speed\' generates 5 bits.\n                                                              : ... In instance pong.gl.b2\n    if ((value - speed) > 3) begin\n               ^\n%Warning-WIDTH: data/full_repos/permissive/46625639/pong.v:395: Operator ADD expects 11 bits on the RHS, but RHS\'s VARREF \'speed\' generates 5 bits.\n                                                              : ... In instance pong.gl.b2\n     value <= value + speed;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/46625639/pong.v:393: Operator ADD expects 32 or 11 bits on the RHS, but RHS\'s VARREF \'speed\' generates 5 bits.\n                                                              : ... In instance pong.gl.b2\n    if ((value + speed) < (1024 - 128)) begin\n               ^\n%Warning-WIDTH: data/full_repos/permissive/46625639/pong.v:647: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                              : ... In instance pong.gl\n   count_secs = 1\'b0;\n              ^\n%Error: data/full_repos/permissive/46625639/pong.v:116: Cannot find file containing module: \'pll108MHz\'\n pll108MHz pll(.inclk0(CLOCK_27), .c0(video_clock));\n ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/46625639,data/full_repos/permissive/46625639/pll108MHz\n             data/full_repos/permissive/46625639,data/full_repos/permissive/46625639/pll108MHz.v\n             data/full_repos/permissive/46625639,data/full_repos/permissive/46625639/pll108MHz.sv\n             pll108MHz\n             pll108MHz.v\n             pll108MHz.sv\n             obj_dir/pll108MHz\n             obj_dir/pll108MHz.v\n             obj_dir/pll108MHz.sv\n%Error: data/full_repos/permissive/46625639/pong.v:203: Cannot find file containing module: \'keyboard\'\n keyboard keybd(\n ^~~~~~~~\n%Error: data/full_repos/permissive/46625639/pong.v:215: Cannot find file containing module: \'oneshot\'\n oneshot pulser(\n ^~~~~~~\n%Error: Exiting due to 3 error(s), 9 warning(s)\n'
module sevenseg(seg0, seg1, seg2, seg3, seg4, seg5, seg6, seg7, score_p1, score_p2, winner);
	input [3:0] score_p1, score_p2;								
	input [1:0] winner;
	output [6:0] seg0, seg1, seg2, seg3, seg4, seg5, seg6, seg7;
	
	reg [6:0] seg0, seg1, seg2, seg3, seg4, seg5, seg6, seg7;
	
	always @ (score_p1 or winner) begin
	
		if (winner > 0) begin

			seg7 = 7'b0001100;
			case (winner)
				2'h1: seg6 = 7'b1111001;
				2'h2: seg6 = 7'b0100100;
				default: seg6 = 7'b1111111;
			endcase
		end
		else begin
			seg7 = 7'b1111111;
			case (score_p1)
					4'h0: seg6 = 7'b1000000;
					4'h1: seg6 = 7'b1111001; 
					4'h2: seg6 = 7'b0100100; 
					4'h3: seg6 = 7'b0110000; 
					4'h4: seg6 = 7'b0011001; 	
					4'h5: seg6 = 7'b0010010; 
					4'h6: seg6 = 7'b0000010; 
					4'h7: seg6 = 7'b1111000; 
					4'h8: seg6 = 7'b0000000; 
					4'h9: seg6 = 7'b0011000; 
					default: seg6 = 7'b1111111; 
			endcase
		end
	end
	
	always @ (score_p2 or winner) begin
		if (winner > 0) begin

			seg5 = 7'b1111111;
			seg4 = 7'b1111111;
		end
		else begin
			seg5 = 7'b1111111;
			case (score_p2)
					4'h0: seg4 = 7'b1000000; 
					4'h1: seg4 = 7'b1111001; 
					4'h2: seg4 = 7'b0100100; 
					4'h3: seg4 = 7'b0110000; 
					4'h4: seg4 = 7'b0011001; 	
					4'h5: seg4 = 7'b0010010; 
					4'h6: seg4 = 7'b0000010; 
					4'h7: seg4 = 7'b1111000; 
					4'h8: seg4 = 7'b0000000; 
					4'h9: seg4 = 7'b0011000; 
					default: seg4 = 7'b1111111; 
			endcase
		end
	end
	

	always begin
		seg3 = 7'b1111111;
		seg2 = 7'b1111111;
		seg1 = 7'b1111111;
		seg0 = 7'b1111111;
	end

endmodule
module sevenseg(seg0, seg1, seg2, seg3, seg4, seg5, seg6, seg7, score_p1, score_p2, winner);

	input [3:0] score_p1, score_p2;								
	input [1:0] winner;
	output [6:0] seg0, seg1, seg2, seg3, seg4, seg5, seg6, seg7;
	
	reg [6:0] seg0, seg1, seg2, seg3, seg4, seg5, seg6, seg7;
	
	always @ (score_p1 or winner) begin
	
		if (winner > 0) begin

			seg7 = 7'b0001100;
			case (winner)
				2'h1: seg6 = 7'b1111001;
				2'h2: seg6 = 7'b0100100;
				default: seg6 = 7'b1111111;
			endcase
		end
		else begin
			seg7 = 7'b1111111;
			case (score_p1)
					4'h0: seg6 = 7'b1000000;
					4'h1: seg6 = 7'b1111001; 
					4'h2: seg6 = 7'b0100100; 
					4'h3: seg6 = 7'b0110000; 
					4'h4: seg6 = 7'b0011001; 	
					4'h5: seg6 = 7'b0010010; 
					4'h6: seg6 = 7'b0000010; 
					4'h7: seg6 = 7'b1111000; 
					4'h8: seg6 = 7'b0000000; 
					4'h9: seg6 = 7'b0011000; 
					default: seg6 = 7'b1111111; 
			endcase
		end
	end
	
	always @ (score_p2 or winner) begin
		if (winner > 0) begin

			seg5 = 7'b1111111;
			seg4 = 7'b1111111;
		end
		else begin
			seg5 = 7'b1111111;
			case (score_p2)
					4'h0: seg4 = 7'b1000000; 
					4'h1: seg4 = 7'b1111001; 
					4'h2: seg4 = 7'b0100100; 
					4'h3: seg4 = 7'b0110000; 
					4'h4: seg4 = 7'b0011001; 	
					4'h5: seg4 = 7'b0010010; 
					4'h6: seg4 = 7'b0000010; 
					4'h7: seg4 = 7'b1111000; 
					4'h8: seg4 = 7'b0000000; 
					4'h9: seg4 = 7'b0011000; 
					default: seg4 = 7'b1111111; 
			endcase
		end
	end
	

	always begin
		seg3 = 7'b1111111;
		seg2 = 7'b1111111;
		seg1 = 7'b1111111;
		seg0 = 7'b1111111;
	end

endmodule