data/full_repos/permissive/432564927/Lab4 (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new/CPU.v
1: b'%Error: Cannot find file containing module: (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927\n        ... Looked in:\n             data/full_repos/permissive/432564927/Lab4/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927\n             data/full_repos/permissive/432564927/Lab4/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             data/full_repos/permissive/432564927/Lab4/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927\n             (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             obj_dir/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927\n             obj_dir/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             obj_dir/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/432564927/Lab4\n%Error: Cannot find file containing module: (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new/CPU.v\n%Error: Exiting due to 3 error(s)\n'
module ControlMux(inst_Mux, regrt, rd_rt);
    input [31:0] inst_Mux;
    input regrt;
    output reg [4:0] rd_rt;
    wire [4:0] rd, rt;
    
    assign rd = inst_Mux[15:11];
    assign rt = inst_Mux[20:16];
    
    always @(rd, rt) begin 
        case (regrt)
            1'b1:
                rd_rt = rt;
            1'b0:
                rd_rt = rd;
        endcase
    end
endmodule
module ControlMux(inst_Mux, regrt, rd_rt);

    input [31:0] inst_Mux;
    input regrt;
    output reg [4:0] rd_rt;
    wire [4:0] rd, rt;
    
    assign rd = inst_Mux[15:11];
    assign rt = inst_Mux[20:16];
    
    always @(rd, rt) begin 
        case (regrt)
            1'b1:
                rd_rt = rt;
            1'b0:
                rd_rt = rd;
        endcase
    end
endmodule