data/full_repos/permissive/423012938/ReisenCoreRVCPU.src/Modules/CentralCore/Execute/PipelineRegIDEXE.v
data/verilator_xmls/c3d203fc-9cae-491d-ae01-aa732ecfe13d.xml
module PipelineRegIDEXE (
    input [4:0] rd,
    input [63:0] dpc,
    input [63:0] qa,
    input [63:0] qb,
    input [63:0] imm64,
    input signedComp,
    input [2:0] func3,
    input aSel,
    input bSel,
    input [3:0] aluc,
    input [1:0] rSel,
    input wmem,
    input m2reg,
    input wreg,
    input [2:0] bType,
    input isJal,
    input clk,

    output reg [4:0] erd,
    output reg [63:0] epc,
    output reg [63:0] eqa,
    output reg [63:0] eqb,
    output reg [63:0] eimm64,
    output reg esignedComp,
    output reg [2:0] efunc3,
    output reg eaSel,
    output reg ebSel,
    output reg [3:0] ealuc,
    output reg [1:0] erSel,
    output reg ewmem,
    output reg em2reg,
    output reg ewreg,
    output reg [2:0] ebType,
    output reg eisJal
);

    always @(posedge clk) begin
        erd <= rd;
        epc <= dpc;
        eqa <= qa;
        eqb <= qb;
        eimm64 <= imm64;
        esignedComp <= signedComp;
        efunc3 <= func3;
        eaSel <= aSel;
        ebSel <= bSel;
        ealuc <= aluc;
        erSel <= rSel;
        ewmem <= wmem;
        em2reg <= m2reg;
        ewreg <= wreg;
        ebType <= bType;
        eisJal <= isJal;
    end

endmodule
module PipelineRegIDEXE (
    input [4:0] rd,
    input [63:0] dpc,
    input [63:0] qa,
    input [63:0] qb,
    input [63:0] imm64,
    input signedComp,
    input [2:0] func3,
    input aSel,
    input bSel,
    input [3:0] aluc,
    input [1:0] rSel,
    input wmem,
    input m2reg,
    input wreg,
    input [2:0] bType,
    input isJal,
    input clk,

    output reg [4:0] erd,
    output reg [63:0] epc,
    output reg [63:0] eqa,
    output reg [63:0] eqb,
    output reg [63:0] eimm64,
    output reg esignedComp,
    output reg [2:0] efunc3,
    output reg eaSel,
    output reg ebSel,
    output reg [3:0] ealuc,
    output reg [1:0] erSel,
    output reg ewmem,
    output reg em2reg,
    output reg ewreg,
    output reg [2:0] ebType,
    output reg eisJal
);


    always @(posedge clk) begin
        erd <= rd;
        epc <= dpc;
        eqa <= qa;
        eqb <= qb;
        eimm64 <= imm64;
        esignedComp <= signedComp;
        efunc3 <= func3;
        eaSel <= aSel;
        ebSel <= bSel;
        ealuc <= aluc;
        erSel <= rSel;
        ewmem <= wmem;
        em2reg <= m2reg;
        ewreg <= wreg;
        ebType <= bType;
        eisJal <= isJal;
    end

endmodule