data/full_repos/permissive/441359809/src/yosys/tests/various/attrib05_port_conn.v
data/verilator_xmls/caff8835-28ec-49b6-8a44-cd8681eb773a.xml
module bar(clk, rst, inp, out);
  input  wire clk;
  input  wire rst;
  input  wire inp;
  output reg  out;

  always @(posedge clk)
    if (rst) out <= 1'd0;
    else     out <= ~inp;

endmodule
module bar(clk, rst, inp, out);

  input  wire clk;
  input  wire rst;
  input  wire inp;
  output reg  out;

  always @(posedge clk)
    if (rst) out <= 1'd0;
    else     out <= ~inp;

endmodule