data/full_repos/permissive/497819211/03/PC.v
1: b'%Error: data/full_repos/permissive/497819211/03/PC.v:9: Cannot find include file: Mux16.v\n`include "Mux16.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/497819211/03,data/full_repos/permissive/497819211/Mux16.v\n             data/full_repos/permissive/497819211/03,data/full_repos/permissive/497819211/Mux16.v.v\n             data/full_repos/permissive/497819211/03,data/full_repos/permissive/497819211/Mux16.v.sv\n             Mux16.v\n             Mux16.v.v\n             Mux16.v.sv\n             obj_dir/Mux16.v\n             obj_dir/Mux16.v.v\n             obj_dir/Mux16.v.sv\n%Error: data/full_repos/permissive/497819211/03/PC.v:10: Cannot find include file: Register.v\n`include "Register.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/497819211/03/PC.v:11: Cannot find include file: Add16.v\n`include "Add16.v" \n         ^~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module PC(
	input wire clk,
	input wire reset,
	input wire [15:0] in,
	input wire load,
	input wire inc,
	output wire [15:0] out
);	 





    
    wire[15:0] nextout1;
    wire[15:0] nextout2;
    wire[15:0] nextout3;
    
    wire[15:0] op1;
    Mux16 MUX161(.a(oldstate),.b(op1),.sel(inc), .out(nextout1));
    Mux16 MUX162(.a(nextout1),.b(in),.sel(load), .out(nextout2));
    Mux16 MUX163(.a(nextout2),.b(16'b0000000000000000),.sel(reset), .out(nextout3));

    Register REGISTER1(.in(nextout3),.load(1'b1),.out(out), .clk(clk));
    wire[15:0] oldstate = out;
    Add16 ADD161(.a(oldstate),.b(16'b0000000000000001),.out(op1));

endmodule
module PC(
	input wire clk,
	input wire reset,
	input wire [15:0] in,
	input wire load,
	input wire inc,
	output wire [15:0] out
);
	 





    
    wire[15:0] nextout1;
    wire[15:0] nextout2;
    wire[15:0] nextout3;
    
    wire[15:0] op1;
    Mux16 MUX161(.a(oldstate),.b(op1),.sel(inc), .out(nextout1));
    Mux16 MUX162(.a(nextout1),.b(in),.sel(load), .out(nextout2));
    Mux16 MUX163(.a(nextout2),.b(16'b0000000000000000),.sel(reset), .out(nextout3));

    Register REGISTER1(.in(nextout3),.load(1'b1),.out(out), .clk(clk));
    wire[15:0] oldstate = out;
    Add16 ADD161(.a(oldstate),.b(16'b0000000000000001),.out(op1));

endmodule