data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n always #12.5 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:99: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("toysram_scan.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:100: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, toysram_scan_tb);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:105: syntax error, unexpected \'@\'\n   repeat (2500) @(posedge clock) cyc = cyc + 1;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n  #2000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:130: Unsupported: Ignoring delay on this delayed statement.\n  #3_00_000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:142: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:144: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:146: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:148: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:157: Unsupported: Ignoring delay on this delayed statement.\n   #1 $display("[%08d] I/O Update", cyc);\n   ^\n%Error: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:167: Unsupported: wait statements\n      wait(~ok | done);\n      ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:177: Unsupported: Ignoring delay on this delayed statement.\n      #1000;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:182: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("[%08d] Test Enable is active.", cyc);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:186: Unsupported: Ignoring delay on this delayed statement.\n  #1 $display("[%08d] Test Enable is inactive.", cyc);\n  ^\n%Error: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:202: Unsupported: wait statements\n      wait(RSTB == 1\'b1);\n      ^~~~\n%Error: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:205: Unsupported: wait statements\n      wait(cyc == 32\'d15000);\n      ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:213: Unsupported: Ignoring delay on this delayed statement.\n      #100;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:221: Unsupported: Ignoring delay on this delayed statement.\n         #100;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:226: Unsupported: Ignoring delay on this delayed statement.\n            #100 pin_scan_clk <= 1\'b1;           \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:228: Unsupported: Ignoring delay on this delayed statement.\n            #100 pin_scan_clk <= 1\'b0;           \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:232: Unsupported: Ignoring delay on this delayed statement.\n         #100;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:238: Unsupported: Ignoring delay on this delayed statement.\n            #100 pin_scan_clk <= 1\'b1;           \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:240: Unsupported: Ignoring delay on this delayed statement.\n            #100 pin_scan_clk <= 1\'b0;           \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:254: Unsupported: Ignoring delay on this delayed statement.\n            #100;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:275: Unsupported: Ignoring delay on this delayed statement.\n      #500;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:277: Unsupported: Ignoring delay on this delayed statement.\n      #500;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:280: Unsupported: Ignoring delay on this delayed statement.\n      #100;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:284: Unsupported: Ignoring delay on this delayed statement.\n      #100;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:291: Unsupported: Ignoring delay on this delayed statement.\n         #100;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:296: Unsupported: Ignoring delay on this delayed statement.\n            #100 pin_scan_clk <= 1\'b1;           \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:298: Unsupported: Ignoring delay on this delayed statement.\n            #100 pin_scan_clk <= 1\'b0;           \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:305: Unsupported: Ignoring delay on this delayed statement.\n         #100;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:309: Unsupported: Ignoring delay on this delayed statement.\n         #100;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:311: Unsupported: Ignoring delay on this delayed statement.\n         #100;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:315: Unsupported: Ignoring delay on this delayed statement.\n         #100;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:317: Unsupported: Ignoring delay on this delayed statement.\n         #100;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:323: Unsupported: Ignoring delay on this delayed statement.\n         #100;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:328: Unsupported: Ignoring delay on this delayed statement.\n         #100;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:332: Unsupported: Ignoring delay on this delayed statement.\n            #100 pin_scan_clk <= 1\'b1;           \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:334: Unsupported: Ignoring delay on this delayed statement.\n            #100 pin_scan_clk <= 1\'b0;           \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:343: Unsupported: Ignoring delay on this delayed statement.\n         #100;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:347: Unsupported: Ignoring delay on this delayed statement.\n            #100 pin_scan_clk <= 1\'b1;           \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:349: Unsupported: Ignoring delay on this delayed statement.\n            #100 pin_scan_clk <= 1\'b0;           \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:355: Unsupported: Ignoring delay on this delayed statement.\n         #100;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:357: Unsupported: Ignoring delay on this delayed statement.\n         #100;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:362: Unsupported: Ignoring delay on this delayed statement.\n         #100;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:367: Unsupported: Ignoring delay on this delayed statement.\n            #100 pin_scan_clk <= 1\'b1;           \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:369: Unsupported: Ignoring delay on this delayed statement.\n            #100 pin_scan_clk <= 1\'b0;           \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:379: Unsupported: Ignoring delay on this delayed statement.\n         #100;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:383: Unsupported: Ignoring delay on this delayed statement.\n            #100 pin_scan_clk <= 1\'b1;           \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:385: Unsupported: Ignoring delay on this delayed statement.\n            #100 pin_scan_clk <= 1\'b0;           \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:401: Unsupported: Ignoring delay on this delayed statement.\n            #100;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:406: Unsupported: Ignoring delay on this delayed statement.\n         #100;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:410: Unsupported: Ignoring delay on this delayed statement.\n            #100 pin_scan_clk <= 1\'b1;           \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:412: Unsupported: Ignoring delay on this delayed statement.\n            #100 pin_scan_clk <= 1\'b0;           \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:418: Unsupported: Ignoring delay on this delayed statement.\n         #100;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:420: Unsupported: Ignoring delay on this delayed statement.\n         #100;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:424: Unsupported: Ignoring delay on this delayed statement.\n         #100;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:429: Unsupported: Ignoring delay on this delayed statement.\n            #100 pin_scan_clk <= 1\'b1;           \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:431: Unsupported: Ignoring delay on this delayed statement.\n            #100 pin_scan_clk <= 1\'b0;           \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:449: Unsupported: Ignoring delay on this delayed statement.\n      #1000;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/530250155/verilog/dv/toysram_scan/toysram_scan_tb.v:452: Unsupported: Ignoring delay on this delayed statement.\n      #1000;\n      ^\n%Error: Exiting due to 6 error(s), 57 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module toysram_scan_tb;

	reg clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

	wire gpio;
	wire [37:0] mprj_io;


	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;



   integer i;
   reg ok, done;
   reg [31:0] write_data;

   reg [31:0] cyc;
   reg pin_te, pin_scan_clk, pin_scan_in, pin_scan_out;
   reg pin_ra0_clk, pin_ra0_rst, pin_ra0_r0_en, pin_ra0_r1_en, pin_ra0_w0_en;
   reg [127:0] scan_in_val, scan_out_val, save_val;


   assign mprj_io[`PIN_TE] = pin_te;
   assign mprj_io[`PIN_SCAN_CLK] = pin_scan_clk;
   assign mprj_io[`PIN_SCAN_IN] = pin_scan_in;
   assign mprj_io[`PIN_RA0_CLK] = pin_ra0_clk;
   assign mprj_io[`PIN_RA0_RST] = pin_ra0_rst;
   assign mprj_io[`PIN_RA0_R0_EN] = pin_ra0_r0_en;
   assign mprj_io[`PIN_RA0_R1_EN] = pin_ra0_r1_en;
   assign mprj_io[`PIN_RA0_W0_EN] = pin_ra0_w0_en;


   always @(*) begin
      pin_scan_out <= mprj_io[`PIN_SCAN_OUT];
   end








	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
      cyc = 0;
	end




	initial begin
		$dumpfile("toysram_scan.vcd");
		$dumpvars(0, toysram_scan_tb);
      $display("\n\n");


		repeat (`CYC_MAX/`CYC_HEARTBEAT) begin
			repeat (`CYC_HEARTBEAT) @(posedge clock) cyc = cyc + 1;
			$display("[%08d] ...tick...", cyc);
		end
		$display("%c[1;31m",27);
		`ifdef GL
			$display ("*ERROR* Timeout, Test Mega-Project IO Ports (GL) Failed");
		`else
			$display ("*ERROR* Timeout, Test Mega-Project IO Ports (RTL) Failed");
		`endif
		$display("%c[0m",27);
		ok <= 1'b0;
	end




	initial begin

		RSTB <= 1'b0;
		CSB  <= 1'b1;

		#2000;
		$display("[%08d] Releasing reset.", cyc);
		RSTB <= 1'b1;

		#3_00_000;
		CSB = 1'b0;
	end




	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end




	always @(mprj_io) begin
      if (`DEBUG > 0) begin
			#1 $display("[%08d] I/O Update", cyc);
		   $display("   MPRJ-IO TE    %b ", mprj_io[`PIN_TE]);
		   $display("   MPRJ-IO SCAN  %b ", {mprj_io[`PIN_SCAN_CLK], mprj_io[`PIN_SCAN_IN], mprj_io[`PIN_SCAN_OUT]});
		   $display("   MPRJ-IO RA0   %b ", {mprj_io[`PIN_RA0_CLK], mprj_io[`PIN_RA0_RST], mprj_io[`PIN_RA0_R0_EN], mprj_io[`PIN_RA0_R1_EN], mprj_io[`PIN_RA0_W0_EN]});
      end
	end

   initial begin
      ok <= 1'b1;
      done <= 1'b0;
      wait(~ok | done);
      if (~ok) begin
   		$display("%c[1;31m",27);
		   $display("[%08d] You are worthless and weak!", cyc);
   		$display("%c[0m",27);
      end else begin
    		$display("%c[1;32m",27);
		   $display("[%08d] You has opulence.", cyc);
   		$display("%c[0m",27);
      end
      #1000;
      $finish;
   end

   always @(posedge mprj_io[`PIN_TE]) begin
		#1 $display("[%08d] Test Enable is active.", cyc);
   end

   always @(negedge mprj_io[`PIN_TE]) begin
		#1 $display("[%08d] Test Enable is inactive.", cyc);
   end




   initial begin

      pin_te <= 1'b0;
      pin_scan_clk <= 1'b0;
      pin_scan_in <= 1'b0;
      pin_ra0_clk <= 1'b0;
      pin_ra0_rst <= 1'b0;
      pin_ra0_r0_en <= 1'b0;
      pin_ra0_r1_en <= 1'b0;
      pin_ra0_w0_en <= 1'b0;
      wait(RSTB == 1'b1);


      wait(cyc == 32'd15000);



		$display("[%08d] Setting Test Enable.", cyc);
      pin_te <= 1'b1;
      scan_in_val <= `SCAN_INIT;
      i <= 0;
      #100;




  		repeat (`SCANS) begin

         $display("[%08d] Writing scan reg: %032X", cyc, scan_in_val);
         #100;
         $display("[%08d] Scanning in...", cyc);

         repeat (128) begin
            pin_scan_in <= scan_in_val[127-i];
            #100 pin_scan_clk <= 1'b1;
            i <= i + 1;
            #100 pin_scan_clk <= 1'b0;
         end
         $display("[%08d] Scan complete.", cyc);
         scan_out_val <= 128'h0;
         #100;


         $display("[%08d] Scanning out...", cyc);
         repeat (128) begin
            scan_out_val <= {scan_out_val[126:0],pin_scan_out};
            #100 pin_scan_clk <= 1'b1;
            i <= i + 1;
            #100 pin_scan_clk <= 1'b0;
         end
         $display("[%08d] Scan complete.", cyc);
         $display("[%08d] Read scan reg: %032X", cyc, scan_out_val);

         if (scan_in_val !== scan_out_val) begin
            $display("%c[1;31m",27);
            $display("*ERROR* Scanout does not compare.");
            $display("%c[0m",27);
            ok <= 1'b0;
         end else begin
            $display("[%08d] Scan good.\n", cyc);
            scan_in_val <= {~scan_in_val[0], ~scan_in_val[127:1]};
            i <= 0;
            #100;
         end

      end







		$display("[%08d] Resetting array.", cyc);
      pin_ra0_rst <= 1'b1;
      #500;
      pin_ra0_rst <= 1'b0;
      #500;

      write_data <= 32'h08675309;
      #100;
		$display("[%08d] Array cmds: R0[0], R1[1], W0[0]=%08X", cyc, write_data);
      scan_in_val <= {5'h00, 32'hFFFFFFFF, 5'h01, 32'hFFFFFFFF, 5'h00, write_data, 17'h1BABE};
      i <= 0;
      #100;

  		repeat (`CMDS) begin

         $display("[%08d] Writing scan reg: %032X", cyc, scan_in_val);
         $display("[%08d] R0[%02X]=%08X  R1[%02X]=%08X  W0[%02C]=%08X", cyc,
                   scan_in_val[127:123], scan_in_val[122:91], scan_in_val[90:86], scan_in_val[85:54], scan_in_val[53:49], scan_in_val[48:17]);
         #100;
         $display("[%08d] Scanning in...", cyc);

         repeat (128) begin
            pin_scan_in <= scan_in_val[127-i];
            #100 pin_scan_clk <= 1'b1;
            i <= i + 1;
            #100 pin_scan_clk <= 1'b0;
         end
         $display("[%08d] Scan complete.", cyc);
         $display("[%08d] R0_EN=1, R1_EN=1, W0_EN=1", cyc);
         pin_ra0_r0_en <= 1'b1;
         pin_ra0_r1_en <= 1'b1;
         pin_ra0_w0_en <= 1'b1;
         #100;

         $display("[%08d] Clocking array (set up input regs)...", cyc);
         pin_ra0_clk <= 1'b1;
         #100;
         pin_ra0_clk <= 1'b0;
         #100;

         $display("[%08d] Clocking array (clock array)...", cyc);
         pin_ra0_clk <= 1'b1;
         #100;
         pin_ra0_clk <= 1'b0;
         #100;

         $display("[%08d] R0_EN=1, R1_EN=1, W0_EN=0", cyc);
         pin_ra0_r0_en <= 1'b1;
         pin_ra0_r1_en <= 1'b1;
         pin_ra0_w0_en <= 1'b0;
         #100;


         scan_out_val <= 128'h0;
         i <= 0;
         #100;
         $display("[%08d] Scanning out...", cyc);
         repeat (128) begin
            scan_out_val <= {scan_out_val[126:0], pin_scan_out};
            #100 pin_scan_clk <= 1'b1;
            i <= i + 1;
            #100 pin_scan_clk <= 1'b0;
         end
         $display("[%08d] Scan complete.", cyc);
         $display("[%08d] Read scan reg: %032X", cyc, scan_out_val);
         $display("[%08d] R0[%02X]=%08X  R1[%02X]=%08X W0[%02C]=%08X", cyc,
                   scan_out_val[127:123], scan_out_val[122:91], scan_out_val[90:86], scan_out_val[85:54], scan_out_val[53:49], scan_out_val[48:17]);

         scan_in_val <= scan_out_val;
         i <= 0;
         #100;
         $display("[%08d] Scanning in (restore)...", cyc);
         repeat (128) begin
            pin_scan_in <= scan_in_val[127-i];
            #100 pin_scan_clk <= 1'b1;
            i <= i + 1;
            #100 pin_scan_clk <= 1'b0;
         end
         $display("[%08d] Scan complete.", cyc);

         $display("[%08d] Clocking array...", cyc);
         pin_ra0_clk <= 1'b1;
         #100;
         pin_ra0_clk <= 1'b0;
         #100;


         scan_out_val <= 128'h0;
         i <= 0;
         #100;
         $display("[%08d] Scanning out nondestructively...", cyc);
         repeat (128) begin
            pin_scan_in <= pin_scan_out;
            scan_out_val <= {scan_out_val[126:0],pin_scan_out};
            #100 pin_scan_clk <= 1'b1;
            i <= i + 1;
            #100 pin_scan_clk <= 1'b0;
         end
         $display("[%08d] Scan complete.", cyc);
         $display("[%08d] Read scan reg: %032X", cyc, scan_out_val);
         $display("[%08d] R0[%02X]=%08X  R1[%02X]=%08X W0[%02C]=%08X", cyc,
                   scan_out_val[127:123], scan_out_val[122:91], scan_out_val[90:86], scan_out_val[85:54], scan_out_val[53:49], scan_out_val[48:17]);

         save_val <= scan_out_val;
         scan_out_val <= 128'h0;
         i <= 0;
         #100;
         $display("[%08d] Scanning out...", cyc);
         repeat (128) begin
            scan_out_val <= {scan_out_val[126:0],pin_scan_out};
            #100 pin_scan_clk <= 1'b1;
            i <= i + 1;
            #100 pin_scan_clk <= 1'b0;
         end
         $display("[%08d] Scan complete.", cyc);
         $display("[%08d] Read scan reg: %032X", cyc, scan_out_val);
         $display("[%08d] R0[%02X]=%08X  R1[%02X]=%08X W0[%02C]=%08X", cyc,
                   scan_out_val[127:123], scan_out_val[122:91], scan_out_val[90:86], scan_out_val[85:54], scan_out_val[53:49], scan_out_val[48:17]);

         if (scan_out_val !== save_val) begin
            $display("%c[1;31m",27);
            $display("*ERROR* Scanout does not compare.");
            $display("%c[0m",27);
            ok <= 1'b0;
         end else begin
            $display("[%08d] Nondestructive scan good.\n", cyc);
            scan_in_val <= {~scan_in_val[0], ~scan_in_val[127:1]};
            i <= 0;
            #100;
         end

         scan_in_val <= scan_out_val;
         i <= 0;
         #100;
         $display("[%08d] Scanning in (restore)...", cyc);
         repeat (128) begin
            pin_scan_in <= scan_in_val[127-i];
            #100 pin_scan_clk <= 1'b1;
            i <= i + 1;
            #100 pin_scan_clk <= 1'b0;
         end
         $display("[%08d] Scan complete.", cyc);

         $display("[%08d] Clocking array...", cyc);
         pin_ra0_clk <= 1'b1;
         #100;
         pin_ra0_clk <= 1'b0;
         #100;

         scan_out_val <= 128'h0;
         i <= 0;
         #100;
         $display("[%08d] Scanning out nondestructively...", cyc);
         repeat (128) begin
            pin_scan_in <= pin_scan_out;
            scan_out_val <= {scan_out_val[126:0],pin_scan_out};
            #100 pin_scan_clk <= 1'b1;
            i <= i + 1;
            #100 pin_scan_clk <= 1'b0;
         end
         $display("[%08d] Scan complete.", cyc);
         $display("[%08d] Read scan reg: %032X", cyc, scan_out_val);
         $display("[%08d] R0[%02X]=%08X  R1[%02X]=%08X W0[%02C]=%08X", cyc,
                   scan_out_val[127:123], scan_out_val[122:91], scan_out_val[90:86], scan_out_val[85:54], scan_out_val[53:49], scan_out_val[48:17]);

         if (write_data !== scan_out_val[122:91]) begin
            $display("%c[1;31m",27);
            $display("*ERROR* R0 does not match expected.");
            $display("%c[0m",27);
            ok <= 1'b0;
         end else begin
            $display("[%08d] R0 good.\n", cyc);
         end

      end

      #1000;
      pin_te <= 1'b0;

      #1000;
      done <= 1'b1;

   end



	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3;
	wire VDD1V8;
	wire VSS;

	assign VDD3V3 = power1;
	assign VDD1V8 = power2;
	assign VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda1_2  (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock    (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("toysram_scan.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule
module toysram_scan_tb;


	reg clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

	wire gpio;
	wire [37:0] mprj_io;


	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;



   integer i;
   reg ok, done;
   reg [31:0] write_data;

   reg [31:0] cyc;
   reg pin_te, pin_scan_clk, pin_scan_in, pin_scan_out;
   reg pin_ra0_clk, pin_ra0_rst, pin_ra0_r0_en, pin_ra0_r1_en, pin_ra0_w0_en;
   reg [127:0] scan_in_val, scan_out_val, save_val;


   assign mprj_io[`PIN_TE] = pin_te;
   assign mprj_io[`PIN_SCAN_CLK] = pin_scan_clk;
   assign mprj_io[`PIN_SCAN_IN] = pin_scan_in;
   assign mprj_io[`PIN_RA0_CLK] = pin_ra0_clk;
   assign mprj_io[`PIN_RA0_RST] = pin_ra0_rst;
   assign mprj_io[`PIN_RA0_R0_EN] = pin_ra0_r0_en;
   assign mprj_io[`PIN_RA0_R1_EN] = pin_ra0_r1_en;
   assign mprj_io[`PIN_RA0_W0_EN] = pin_ra0_w0_en;


   always @(*) begin
      pin_scan_out <= mprj_io[`PIN_SCAN_OUT];
   end








	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
      cyc = 0;
	end




	initial begin
		$dumpfile("toysram_scan.vcd");
		$dumpvars(0, toysram_scan_tb);
      $display("\n\n");


		repeat (`CYC_MAX/`CYC_HEARTBEAT) begin
			repeat (`CYC_HEARTBEAT) @(posedge clock) cyc = cyc + 1;
			$display("[%08d] ...tick...", cyc);
		end
		$display("%c[1;31m",27);
		`ifdef GL
			$display ("*ERROR* Timeout, Test Mega-Project IO Ports (GL) Failed");
		`else
			$display ("*ERROR* Timeout, Test Mega-Project IO Ports (RTL) Failed");
		`endif
		$display("%c[0m",27);
		ok <= 1'b0;
	end




	initial begin

		RSTB <= 1'b0;
		CSB  <= 1'b1;

		#2000;
		$display("[%08d] Releasing reset.", cyc);
		RSTB <= 1'b1;

		#3_00_000;
		CSB = 1'b0;
	end




	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end




	always @(mprj_io) begin
      if (`DEBUG > 0) begin
			#1 $display("[%08d] I/O Update", cyc);
		   $display("   MPRJ-IO TE    %b ", mprj_io[`PIN_TE]);
		   $display("   MPRJ-IO SCAN  %b ", {mprj_io[`PIN_SCAN_CLK], mprj_io[`PIN_SCAN_IN], mprj_io[`PIN_SCAN_OUT]});
		   $display("   MPRJ-IO RA0   %b ", {mprj_io[`PIN_RA0_CLK], mprj_io[`PIN_RA0_RST], mprj_io[`PIN_RA0_R0_EN], mprj_io[`PIN_RA0_R1_EN], mprj_io[`PIN_RA0_W0_EN]});
      end
	end

   initial begin
      ok <= 1'b1;
      done <= 1'b0;
      wait(~ok | done);
      if (~ok) begin
   		$display("%c[1;31m",27);
		   $display("[%08d] You are worthless and weak!", cyc);
   		$display("%c[0m",27);
      end else begin
    		$display("%c[1;32m",27);
		   $display("[%08d] You has opulence.", cyc);
   		$display("%c[0m",27);
      end
      #1000;
      $finish;
   end

   always @(posedge mprj_io[`PIN_TE]) begin
		#1 $display("[%08d] Test Enable is active.", cyc);
   end

   always @(negedge mprj_io[`PIN_TE]) begin
		#1 $display("[%08d] Test Enable is inactive.", cyc);
   end




   initial begin

      pin_te <= 1'b0;
      pin_scan_clk <= 1'b0;
      pin_scan_in <= 1'b0;
      pin_ra0_clk <= 1'b0;
      pin_ra0_rst <= 1'b0;
      pin_ra0_r0_en <= 1'b0;
      pin_ra0_r1_en <= 1'b0;
      pin_ra0_w0_en <= 1'b0;
      wait(RSTB == 1'b1);


      wait(cyc == 32'd15000);



		$display("[%08d] Setting Test Enable.", cyc);
      pin_te <= 1'b1;
      scan_in_val <= `SCAN_INIT;
      i <= 0;
      #100;




  		repeat (`SCANS) begin

         $display("[%08d] Writing scan reg: %032X", cyc, scan_in_val);
         #100;
         $display("[%08d] Scanning in...", cyc);

         repeat (128) begin
            pin_scan_in <= scan_in_val[127-i];
            #100 pin_scan_clk <= 1'b1;
            i <= i + 1;
            #100 pin_scan_clk <= 1'b0;
         end
         $display("[%08d] Scan complete.", cyc);
         scan_out_val <= 128'h0;
         #100;


         $display("[%08d] Scanning out...", cyc);
         repeat (128) begin
            scan_out_val <= {scan_out_val[126:0],pin_scan_out};
            #100 pin_scan_clk <= 1'b1;
            i <= i + 1;
            #100 pin_scan_clk <= 1'b0;
         end
         $display("[%08d] Scan complete.", cyc);
         $display("[%08d] Read scan reg: %032X", cyc, scan_out_val);

         if (scan_in_val !== scan_out_val) begin
            $display("%c[1;31m",27);
            $display("*ERROR* Scanout does not compare.");
            $display("%c[0m",27);
            ok <= 1'b0;
         end else begin
            $display("[%08d] Scan good.\n", cyc);
            scan_in_val <= {~scan_in_val[0], ~scan_in_val[127:1]};
            i <= 0;
            #100;
         end

      end







		$display("[%08d] Resetting array.", cyc);
      pin_ra0_rst <= 1'b1;
      #500;
      pin_ra0_rst <= 1'b0;
      #500;

      write_data <= 32'h08675309;
      #100;
		$display("[%08d] Array cmds: R0[0], R1[1], W0[0]=%08X", cyc, write_data);
      scan_in_val <= {5'h00, 32'hFFFFFFFF, 5'h01, 32'hFFFFFFFF, 5'h00, write_data, 17'h1BABE};
      i <= 0;
      #100;

  		repeat (`CMDS) begin

         $display("[%08d] Writing scan reg: %032X", cyc, scan_in_val);
         $display("[%08d] R0[%02X]=%08X  R1[%02X]=%08X  W0[%02C]=%08X", cyc,
                   scan_in_val[127:123], scan_in_val[122:91], scan_in_val[90:86], scan_in_val[85:54], scan_in_val[53:49], scan_in_val[48:17]);
         #100;
         $display("[%08d] Scanning in...", cyc);

         repeat (128) begin
            pin_scan_in <= scan_in_val[127-i];
            #100 pin_scan_clk <= 1'b1;
            i <= i + 1;
            #100 pin_scan_clk <= 1'b0;
         end
         $display("[%08d] Scan complete.", cyc);
         $display("[%08d] R0_EN=1, R1_EN=1, W0_EN=1", cyc);
         pin_ra0_r0_en <= 1'b1;
         pin_ra0_r1_en <= 1'b1;
         pin_ra0_w0_en <= 1'b1;
         #100;

         $display("[%08d] Clocking array (set up input regs)...", cyc);
         pin_ra0_clk <= 1'b1;
         #100;
         pin_ra0_clk <= 1'b0;
         #100;

         $display("[%08d] Clocking array (clock array)...", cyc);
         pin_ra0_clk <= 1'b1;
         #100;
         pin_ra0_clk <= 1'b0;
         #100;

         $display("[%08d] R0_EN=1, R1_EN=1, W0_EN=0", cyc);
         pin_ra0_r0_en <= 1'b1;
         pin_ra0_r1_en <= 1'b1;
         pin_ra0_w0_en <= 1'b0;
         #100;


         scan_out_val <= 128'h0;
         i <= 0;
         #100;
         $display("[%08d] Scanning out...", cyc);
         repeat (128) begin
            scan_out_val <= {scan_out_val[126:0], pin_scan_out};
            #100 pin_scan_clk <= 1'b1;
            i <= i + 1;
            #100 pin_scan_clk <= 1'b0;
         end
         $display("[%08d] Scan complete.", cyc);
         $display("[%08d] Read scan reg: %032X", cyc, scan_out_val);
         $display("[%08d] R0[%02X]=%08X  R1[%02X]=%08X W0[%02C]=%08X", cyc,
                   scan_out_val[127:123], scan_out_val[122:91], scan_out_val[90:86], scan_out_val[85:54], scan_out_val[53:49], scan_out_val[48:17]);

         scan_in_val <= scan_out_val;
         i <= 0;
         #100;
         $display("[%08d] Scanning in (restore)...", cyc);
         repeat (128) begin
            pin_scan_in <= scan_in_val[127-i];
            #100 pin_scan_clk <= 1'b1;
            i <= i + 1;
            #100 pin_scan_clk <= 1'b0;
         end
         $display("[%08d] Scan complete.", cyc);

         $display("[%08d] Clocking array...", cyc);
         pin_ra0_clk <= 1'b1;
         #100;
         pin_ra0_clk <= 1'b0;
         #100;


         scan_out_val <= 128'h0;
         i <= 0;
         #100;
         $display("[%08d] Scanning out nondestructively...", cyc);
         repeat (128) begin
            pin_scan_in <= pin_scan_out;
            scan_out_val <= {scan_out_val[126:0],pin_scan_out};
            #100 pin_scan_clk <= 1'b1;
            i <= i + 1;
            #100 pin_scan_clk <= 1'b0;
         end
         $display("[%08d] Scan complete.", cyc);
         $display("[%08d] Read scan reg: %032X", cyc, scan_out_val);
         $display("[%08d] R0[%02X]=%08X  R1[%02X]=%08X W0[%02C]=%08X", cyc,
                   scan_out_val[127:123], scan_out_val[122:91], scan_out_val[90:86], scan_out_val[85:54], scan_out_val[53:49], scan_out_val[48:17]);

         save_val <= scan_out_val;
         scan_out_val <= 128'h0;
         i <= 0;
         #100;
         $display("[%08d] Scanning out...", cyc);
         repeat (128) begin
            scan_out_val <= {scan_out_val[126:0],pin_scan_out};
            #100 pin_scan_clk <= 1'b1;
            i <= i + 1;
            #100 pin_scan_clk <= 1'b0;
         end
         $display("[%08d] Scan complete.", cyc);
         $display("[%08d] Read scan reg: %032X", cyc, scan_out_val);
         $display("[%08d] R0[%02X]=%08X  R1[%02X]=%08X W0[%02C]=%08X", cyc,
                   scan_out_val[127:123], scan_out_val[122:91], scan_out_val[90:86], scan_out_val[85:54], scan_out_val[53:49], scan_out_val[48:17]);

         if (scan_out_val !== save_val) begin
            $display("%c[1;31m",27);
            $display("*ERROR* Scanout does not compare.");
            $display("%c[0m",27);
            ok <= 1'b0;
         end else begin
            $display("[%08d] Nondestructive scan good.\n", cyc);
            scan_in_val <= {~scan_in_val[0], ~scan_in_val[127:1]};
            i <= 0;
            #100;
         end

         scan_in_val <= scan_out_val;
         i <= 0;
         #100;
         $display("[%08d] Scanning in (restore)...", cyc);
         repeat (128) begin
            pin_scan_in <= scan_in_val[127-i];
            #100 pin_scan_clk <= 1'b1;
            i <= i + 1;
            #100 pin_scan_clk <= 1'b0;
         end
         $display("[%08d] Scan complete.", cyc);

         $display("[%08d] Clocking array...", cyc);
         pin_ra0_clk <= 1'b1;
         #100;
         pin_ra0_clk <= 1'b0;
         #100;

         scan_out_val <= 128'h0;
         i <= 0;
         #100;
         $display("[%08d] Scanning out nondestructively...", cyc);
         repeat (128) begin
            pin_scan_in <= pin_scan_out;
            scan_out_val <= {scan_out_val[126:0],pin_scan_out};
            #100 pin_scan_clk <= 1'b1;
            i <= i + 1;
            #100 pin_scan_clk <= 1'b0;
         end
         $display("[%08d] Scan complete.", cyc);
         $display("[%08d] Read scan reg: %032X", cyc, scan_out_val);
         $display("[%08d] R0[%02X]=%08X  R1[%02X]=%08X W0[%02C]=%08X", cyc,
                   scan_out_val[127:123], scan_out_val[122:91], scan_out_val[90:86], scan_out_val[85:54], scan_out_val[53:49], scan_out_val[48:17]);

         if (write_data !== scan_out_val[122:91]) begin
            $display("%c[1;31m",27);
            $display("*ERROR* R0 does not match expected.");
            $display("%c[0m",27);
            ok <= 1'b0;
         end else begin
            $display("[%08d] R0 good.\n", cyc);
         end

      end

      #1000;
      pin_te <= 1'b0;

      #1000;
      done <= 1'b1;

   end



	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3;
	wire VDD1V8;
	wire VSS;

	assign VDD3V3 = power1;
	assign VDD1V8 = power2;
	assign VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda1_2  (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock    (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("toysram_scan.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule