data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/blueswitch_data_processor.v
1: b'%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/blueswitch_data_processor.v:43: Cannot find include file: nf_sume_blueswitch_register_define.v\n`include "nf_sume_blueswitch_register_define.v"  \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog,data/full_repos/permissive/498471995/nf_sume_blueswitch_register_define.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog,data/full_repos/permissive/498471995/nf_sume_blueswitch_register_define.v.v\n             data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog,data/full_repos/permissive/498471995/nf_sume_blueswitch_register_define.v.sv\n             nf_sume_blueswitch_register_define.v\n             nf_sume_blueswitch_register_define.v.v\n             nf_sume_blueswitch_register_define.v.sv\n             obj_dir/nf_sume_blueswitch_register_define.v\n             obj_dir/nf_sume_blueswitch_register_define.v.v\n             obj_dir/nf_sume_blueswitch_register_define.v.sv\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/blueswitch_data_processor.v:44: Cannot find include file: nf_sume_blueswitch_parameter_define.v\n`include "nf_sume_blueswitch_parameter_define.v"  \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/blueswitch_data_processor.v:157: Define or directive not defined: \'`DEF_SW_TAG\'\nwire  [`DEF_SW_TAG-1:0]                w_sw_tag;\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/blueswitch_data_processor.v:158: Define or directive not defined: \'`DEF_SW_TAG_VAL\'\nwire  [`DEF_SW_TAG_VAL-1:0]            w_sw_tag_val;\n       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/contrib/cores/nf_sume_blueswitch_v1_0_0/hdl/verilog/blueswitch_data_processor.v:164: Define or directive not defined: \'`DEF_SW_TAG_VAL\'\nwire  [`DEF_SW_TAG_VAL-1:0]      bus_sw_tag_val;\n       ^~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n'
function integer log2; 
   input integer number; 
   begin 
      log2=0; 
      while(2**log2<number) begin 
         log2=log2+1; 
      end 
   end 
endfunction
function integer log2;
 
   input integer number; 
   begin 
      log2=0; 
      while(2**log2<number) begin 
         log2=log2+1; 
      end 
   end 
endfunction