data/full_repos/permissive/517127224/fpga/hdl/NES_KV260.v
1: b"%Error: data/full_repos/permissive/517127224/fpga/hdl/NES_KV260.v:325: Can't find definition of 'slv_reg_wren' in dotted variable: 'axi.slv_reg_wren'\n  wire       loader_clk   = (axi_state == 2) && s00_axi_aresetn == 1'b1 && axi.slv_reg_wren && s00_axi_awaddr == 4'b0;\n                                                                               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/517127224/fpga/hdl/NES_KV260.v:392: Can't find definition of 'slv_reg_wren' in dotted variable: 'axi.slv_reg_wren'\n    if (s00_axi_aresetn == 1'b1 && axi.slv_reg_wren && s00_axi_awaddr == 4'b0) begin\n                                       ^~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module GameLoader(input clk, input reset,
                  input [7:0] indata, input indata_clk,
                  output reg [21:0] mem_addr, output [7:0] mem_data, output mem_write,
                  output [31:0] mapper_flags,
                  output reg done,
                  output error);

  reg [2:0] state = 0;
  reg [7:0] prgsize;
  reg [3:0] ctr;
  reg [7:0] ines[0:15];
  reg [21:0] bytes_left;
  
  assign error = (state == 5);
  wire [7:0] prgrom = ines[4];
  wire [7:0] chrrom = ines[5];
  assign mem_data = (state == 3 || state == 4) ? 8'b0000_0000 : indata;

  assign mem_write = !done && (bytes_left != 0) && 
                    ((state == 1 || state == 2) && indata_clk || state == 3 || state == 4);
  
  wire [2:0] prg_size = prgrom <= 1  ? 0 :
                        prgrom <= 2  ? 1 : 
                        prgrom <= 4  ? 2 : 
                        prgrom <= 8  ? 3 : 
                        prgrom <= 16 ? 4 : 
                        prgrom <= 32 ? 5 : 
                        prgrom <= 64 ? 6 : 7;
                        
  wire [2:0] chr_size = chrrom <= 1  ? 0 : 
                        chrrom <= 2  ? 1 : 
                        chrrom <= 4  ? 2 : 
                        chrrom <= 8  ? 3 : 
                        chrrom <= 16 ? 4 : 
                        chrrom <= 32 ? 5 : 
                        chrrom <= 64 ? 6 : 7;
  
  wire [7:0] mapper = {ines[7][7:4], ines[6][7:4]};
  wire has_chr_ram = (chrrom == 0);
  assign mapper_flags = {16'b0, has_chr_ram, ines[6][0], chr_size, prg_size, mapper};
  always @(posedge clk) begin
    if (reset) begin
      state <= 0;
      done <= 0;
      ctr <= 0;
      mem_addr <= 0;
    end else begin
      case(state)

      0: if (indata_clk) begin
           ctr <= ctr + 1;
           ines[ctr] <= indata;
           bytes_left <= {prgrom, 14'b0};
           if (ctr == 4'b1111)
             state <= (ines[0] == 8'h4E) && (ines[1] == 8'h45) && (ines[2] == 8'h53) && (ines[3] == 8'h1A) && !ines[6][2] && !ines[6][3] ? 1 : 5;
         end
      1, 2, 3, 4: begin
          if (bytes_left != 1) begin
            if (indata_clk || state == 3 || state == 4) begin
              bytes_left <= bytes_left - 1;
              mem_addr <= mem_addr + 1;
            end

          end else if (indata_clk && state == 1) begin
            state <= 2;
            mem_addr <= 22'b10_0000_0000_0000_0000_0000;
            bytes_left <= {1'b0, chrrom, 13'b0};
          end else if (indata_clk && state == 2) begin
            state <= 3;
            mem_addr <= 22'b11_1000_0000_0000_0000_0000;
            bytes_left <= 2048;
          end else if (state == 3) begin
            state <= 4;
            mem_addr <= 22'b11_0000_0000_0000_0000_0000;
            bytes_left <= 2048;
          end else if (state == 4) begin
            done <= 1;
          end
        end
      endcase
    end
  end
endmodule
module GameLoader(input clk, input reset,
                  input [7:0] indata, input indata_clk,
                  output reg [21:0] mem_addr, output [7:0] mem_data, output mem_write,
                  output [31:0] mapper_flags,
                  output reg done,
                  output error);


  reg [2:0] state = 0;
  reg [7:0] prgsize;
  reg [3:0] ctr;
  reg [7:0] ines[0:15];
  reg [21:0] bytes_left;
  
  assign error = (state == 5);
  wire [7:0] prgrom = ines[4];
  wire [7:0] chrrom = ines[5];
  assign mem_data = (state == 3 || state == 4) ? 8'b0000_0000 : indata;

  assign mem_write = !done && (bytes_left != 0) && 
                    ((state == 1 || state == 2) && indata_clk || state == 3 || state == 4);
  
  wire [2:0] prg_size = prgrom <= 1  ? 0 :
                        prgrom <= 2  ? 1 : 
                        prgrom <= 4  ? 2 : 
                        prgrom <= 8  ? 3 : 
                        prgrom <= 16 ? 4 : 
                        prgrom <= 32 ? 5 : 
                        prgrom <= 64 ? 6 : 7;
                        
  wire [2:0] chr_size = chrrom <= 1  ? 0 : 
                        chrrom <= 2  ? 1 : 
                        chrrom <= 4  ? 2 : 
                        chrrom <= 8  ? 3 : 
                        chrrom <= 16 ? 4 : 
                        chrrom <= 32 ? 5 : 
                        chrrom <= 64 ? 6 : 7;
  
  wire [7:0] mapper = {ines[7][7:4], ines[6][7:4]};
  wire has_chr_ram = (chrrom == 0);
  assign mapper_flags = {16'b0, has_chr_ram, ines[6][0], chr_size, prg_size, mapper};
  always @(posedge clk) begin
    if (reset) begin
      state <= 0;
      done <= 0;
      ctr <= 0;
      mem_addr <= 0;
    end else begin
      case(state)

      0: if (indata_clk) begin
           ctr <= ctr + 1;
           ines[ctr] <= indata;
           bytes_left <= {prgrom, 14'b0};
           if (ctr == 4'b1111)
             state <= (ines[0] == 8'h4E) && (ines[1] == 8'h45) && (ines[2] == 8'h53) && (ines[3] == 8'h1A) && !ines[6][2] && !ines[6][3] ? 1 : 5;
         end
      1, 2, 3, 4: begin
          if (bytes_left != 1) begin
            if (indata_clk || state == 3 || state == 4) begin
              bytes_left <= bytes_left - 1;
              mem_addr <= mem_addr + 1;
            end

          end else if (indata_clk && state == 1) begin
            state <= 2;
            mem_addr <= 22'b10_0000_0000_0000_0000_0000;
            bytes_left <= {1'b0, chrrom, 13'b0};
          end else if (indata_clk && state == 2) begin
            state <= 3;
            mem_addr <= 22'b11_1000_0000_0000_0000_0000;
            bytes_left <= 2048;
          end else if (state == 3) begin
            state <= 4;
            mem_addr <= 22'b11_0000_0000_0000_0000_0000;
            bytes_left <= 2048;
          end else if (state == 4) begin
            done <= 1;
          end
        end
      endcase
    end
  end
endmodule