data/full_repos/permissive/498662723/Verilog Language/Vectors/Vector4.v
1: b'%Error: Cannot find file containing module: Language/Vectors,data/full_repos/permissive/498662723\n        ... Looked in:\n             data/full_repos/permissive/498662723/Verilog/Language/Vectors,data/full_repos/permissive/498662723\n             data/full_repos/permissive/498662723/Verilog/Language/Vectors,data/full_repos/permissive/498662723.v\n             data/full_repos/permissive/498662723/Verilog/Language/Vectors,data/full_repos/permissive/498662723.sv\n             Language/Vectors,data/full_repos/permissive/498662723\n             Language/Vectors,data/full_repos/permissive/498662723.v\n             Language/Vectors,data/full_repos/permissive/498662723.sv\n             obj_dir/Language/Vectors,data/full_repos/permissive/498662723\n             obj_dir/Language/Vectors,data/full_repos/permissive/498662723.v\n             obj_dir/Language/Vectors,data/full_repos/permissive/498662723.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/498662723/Verilog\n%Error: Cannot find file containing module: Language/Vectors/Vector4.v\n%Error: Exiting due to 3 error(s)\n'
module top_module (
    input [7:0] in,
    output [31:0] out );

    assign out = { {24{in[7]}} , in[7:0] };

endmodule
module top_module (
    input [7:0] in,
    output [31:0] out );


    assign out = { {24{in[7]}} , in[7:0] };

endmodule