data/full_repos/permissive/522534105/RTL_files/Counter_M.v
data/verilator_xmls/139fed56-6d39-488f-b243-9cf0db2d4c4e.xml
module Counter_M(
input i_clk , 
input i_rst_n , 
output [`N_COUNT_WIDTH-1:0] o_cnt
    );
    reg [`N_COUNT_WIDTH-1:0] o_counter ;
    
    
    always @(posedge i_clk or negedge i_rst_n)
        begin
          if (~i_rst_n)
             begin
                o_counter <= 0;
                 end
              else
                   begin
           o_counter <= o_counter + 1'b1 ;
        end  
      end                   
                
   assign o_cnt = o_counter ;              
endmodule
module Counter_M(
input i_clk , 
input i_rst_n , 
output [`N_COUNT_WIDTH-1:0] o_cnt
    );

    reg [`N_COUNT_WIDTH-1:0] o_counter ;
    
    
    always @(posedge i_clk or negedge i_rst_n)
        begin
          if (~i_rst_n)
             begin
                o_counter <= 0;
                 end
              else
                   begin
           o_counter <= o_counter + 1'b1 ;
        end  
      end                   
                
   assign o_cnt = o_counter ;              
endmodule