data/full_repos/permissive/464047548/display_clocks_simple.v
1: b"%Error: data/full_repos/permissive/464047548/display_clocks_simple.v:29: Cannot find file containing module: 'MMCME2_ADV'\n    MMCME2_ADV #(\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/464047548,data/full_repos/permissive/464047548/MMCME2_ADV\n             data/full_repos/permissive/464047548,data/full_repos/permissive/464047548/MMCME2_ADV.v\n             data/full_repos/permissive/464047548,data/full_repos/permissive/464047548/MMCME2_ADV.sv\n             MMCME2_ADV\n             MMCME2_ADV.v\n             MMCME2_ADV.sv\n             obj_dir/MMCME2_ADV\n             obj_dir/MMCME2_ADV.v\n             obj_dir/MMCME2_ADV.sv\n%Error: data/full_repos/permissive/464047548/display_clocks_simple.v:84: Cannot find file containing module: 'BUFG'\n    BUFG bufg_clk_pix(.I(clk_pre), .O(o_clk));\n    ^~~~\n%Error: Exiting due to 2 error(s)\n"
module display_clocks_simple #(
    parameter MULT=13,
    parameter DIV=20,
    parameter IN_PERIOD=10.0
    )
    (
    input  wire i_clk,
    input  wire i_rst,
    output wire o_clk,
    output wire o_locked
    );

    wire clk_fb;
    wire clk_pre;

    MMCME2_ADV #(
        .COMPENSATION("INTERNAL"),
        .BANDWIDTH("OPTIMIZED"),
        .CLKFBOUT_MULT_F(MULT),
        .CLKFBOUT_PHASE(0.0),
        .CLKIN1_PERIOD(IN_PERIOD),

        .CLKOUT0_DIVIDE_F(1.0),
        .CLKOUT1_DIVIDE(1),
        .CLKOUT2_DIVIDE(1),
        .CLKOUT3_DIVIDE(1),
        .CLKOUT4_DIVIDE(1),
        .CLKOUT5_DIVIDE(1),

        .CLKOUT0_DUTY_CYCLE(0.5),
        .CLKOUT1_DUTY_CYCLE(0.5),
        .CLKOUT2_DUTY_CYCLE(0.5),
        .CLKOUT3_DUTY_CYCLE(0.5),
        .CLKOUT4_DUTY_CYCLE(0.5),
        .CLKOUT5_DUTY_CYCLE(0.5),

        .CLKOUT0_PHASE(0.0),
        .CLKOUT1_PHASE(0.0),
        .CLKOUT2_PHASE(0.0),
        .CLKOUT3_PHASE(0.0),
        .CLKOUT4_PHASE(0.0),
        .CLKOUT5_PHASE(0.0),
        .DIVCLK_DIVIDE(DIV),
        .REF_JITTER1(0.010),
        .STARTUP_WAIT("FALSE")
    )
    MMCM_inst (


        .CLKOUT0(clk_pre),
        .CLKOUT1(),
        .CLKOUT2(),
        .CLKOUT3(),
        .CLKOUT4(),
        .CLKOUT5(),

        .CLKFBOUT(clk_fb),

        .LOCKED(o_locked),

        .CLKIN1(i_clk),



        .RST(i_rst),

        .CLKFBIN(clk_fb)
    );


    BUFG bufg_clk_pix(.I(clk_pre), .O(o_clk));

endmodule
module display_clocks_simple #(
    parameter MULT=13,
    parameter DIV=20,
    parameter IN_PERIOD=10.0
    )
    (
    input  wire i_clk,
    input  wire i_rst,
    output wire o_clk,
    output wire o_locked
    );


    wire clk_fb;
    wire clk_pre;

    MMCME2_ADV #(
        .COMPENSATION("INTERNAL"),
        .BANDWIDTH("OPTIMIZED"),
        .CLKFBOUT_MULT_F(MULT),
        .CLKFBOUT_PHASE(0.0),
        .CLKIN1_PERIOD(IN_PERIOD),

        .CLKOUT0_DIVIDE_F(1.0),
        .CLKOUT1_DIVIDE(1),
        .CLKOUT2_DIVIDE(1),
        .CLKOUT3_DIVIDE(1),
        .CLKOUT4_DIVIDE(1),
        .CLKOUT5_DIVIDE(1),

        .CLKOUT0_DUTY_CYCLE(0.5),
        .CLKOUT1_DUTY_CYCLE(0.5),
        .CLKOUT2_DUTY_CYCLE(0.5),
        .CLKOUT3_DUTY_CYCLE(0.5),
        .CLKOUT4_DUTY_CYCLE(0.5),
        .CLKOUT5_DUTY_CYCLE(0.5),

        .CLKOUT0_PHASE(0.0),
        .CLKOUT1_PHASE(0.0),
        .CLKOUT2_PHASE(0.0),
        .CLKOUT3_PHASE(0.0),
        .CLKOUT4_PHASE(0.0),
        .CLKOUT5_PHASE(0.0),
        .DIVCLK_DIVIDE(DIV),
        .REF_JITTER1(0.010),
        .STARTUP_WAIT("FALSE")
    )
    MMCM_inst (


        .CLKOUT0(clk_pre),
        .CLKOUT1(),
        .CLKOUT2(),
        .CLKOUT3(),
        .CLKOUT4(),
        .CLKOUT5(),

        .CLKFBOUT(clk_fb),

        .LOCKED(o_locked),

        .CLKIN1(i_clk),



        .RST(i_rst),

        .CLKFBIN(clk_fb)
    );


    BUFG bufg_clk_pix(.I(clk_pre), .O(o_clk));

endmodule