data/full_repos/permissive/450915285/clockupdate.v
data/verilator_xmls/c29cb132-acd9-4d2a-8fcf-ed5699a1aa73.xml
module clockupdate(clk,clk_update);
  input clk;
  output clk_update;
  reg clk_update;
  reg [21:0] check;
    
    always @ (posedge clk) 
      begin
        if(check < 4000000) begin
            check <= check + 1;
            clk_update <= 0;
        end
        else begin 
            check <= 0;
            clk_update <= 1;
        end
    end 
endmodule
module clockupdate(clk,clk_update);

  input clk;
  output clk_update;
  reg clk_update;
  reg [21:0] check;
    
    always @ (posedge clk) 
      begin
        if(check < 4000000) begin
            check <= check + 1;
            clk_update <= 0;
        end
        else begin 
            check <= 0;
            clk_update <= 1;
        end
    end 
endmodule