data/full_repos/permissive/458737381/src/verilog-parser/tests/d_latch_switch.v
1: b"%Error-ASSIGNIN: data/full_repos/permissive/458737381/src/verilog-parser/tests/d_latch_switch.v:21: Assigning to input/const variable: 'd'\npmos p1 (d,q,clkn);\n         ^\n%Error-ASSIGNIN: data/full_repos/permissive/458737381/src/verilog-parser/tests/d_latch_switch.v:22: Assigning to input/const variable: 'd'\nnmos n1 (d,q,clk);\n         ^\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module not_switch (out, in);
   output  out;               
   input   in;                
   
   supply1 power;             
   supply0 ground;            
   
   pmos (out, power, in);     
   nmos (out, ground, in);    
   
endmodule
module not_switch (out, in);

   output  out;               
   input   in;                
   
   supply1 power;             
   supply0 ground;            
   
   pmos (out, power, in);     
   nmos (out, ground, in);    
   
endmodule