data/full_repos/permissive/516679177/MEMORY/tb_MEMORY.v
1: b'%Error: data/full_repos/permissive/516679177/MEMORY/tb_MEMORY.v:15: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, testbench_MEMORY);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/516679177/MEMORY/tb_MEMORY.v:16: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("my.vcd");\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/516679177/MEMORY/tb_MEMORY.v:20: Unsupported: Ignoring delay on this delayed statement.\n   #5 clk = ~clk;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/516679177/MEMORY/tb_MEMORY.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/MEMORY/tb_MEMORY.v:37: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/MEMORY/tb_MEMORY.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/MEMORY/tb_MEMORY.v:49: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/MEMORY/tb_MEMORY.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/MEMORY/tb_MEMORY.v:62: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/MEMORY/tb_MEMORY.v:69: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/MEMORY/tb_MEMORY.v:75: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/MEMORY/tb_MEMORY.v:81: Unsupported: Ignoring delay on this delayed statement.\n  #13\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/MEMORY/tb_MEMORY.v:87: Unsupported: Ignoring delay on this delayed statement.\n  #5\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/516679177/MEMORY/tb_MEMORY.v:92: Unsupported: Ignoring delay on this delayed statement.\n  #270\n  ^\n%Error: Exiting due to 2 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench_MEMORY;
	parameter WIDTH = 8;
	reg [31:0] Din;
	reg [7:0] Addr;
	reg rw;
	reg Valid;
	reg reset;
	reg clk;
	wire [31:0] Dout;

	MEMORY DUT (Din, Addr, rw, Valid, reset, clk, Dout);

	initial begin

		$dumpvars(0, testbench_MEMORY);
		$dumpfile("my.vcd");

		clk = 0;
		forever
			#5 clk = ~clk;

	end

	initial begin 

		reset = 1;
		Din = 32'h5;
		Addr = 8'h0;
		#5
		display;

		reset = 0;
		Valid = 1;
		rw = 1;
		Din = 32'h5;
		Addr = 8'h0;
		#5
		display;

		rw = 1;
		Din = 32'h5;
		Addr = 8'h0;
		#5
		display;

		rw = 0;
		Din = 32'h5;
		Addr = 8'h0;
		#5
		display;

		rw = 1;
		Din = 32'h5;
		Addr = 8'h0;
		#5
		display;

		Valid = 0;
		rw = 1;
		Din = 32'h5;
		Addr = 8'h0;
		#5
		display;

		Valid = 1;
		rw = 1;
		Din = 32'hF00;
		Addr = 8'h2C;
		#5
		display;

		rw = 0;
		Din = 32'hF00;
		Addr = 8'h2C;
		#5
		display;

		rw = 1;
		Din = 32'hF00;
		Addr = 8'h2C;
		#13
		display;

		rw = 0;
		Din = 32'hF00;
		Addr = 8'h2C;
		#5
		display;



		#270
		$finish;
		end
	
	task display;
		$display("reset = %0h, clk = %0h, valid = %0h, rw = %0h, Din = %0h, Addr = %0h, Dout = %0h", reset, clk, Valid, rw, Din, Addr, Dout);
	endtask

endmodule
module testbench_MEMORY;

	parameter WIDTH = 8;
	reg [31:0] Din;
	reg [7:0] Addr;
	reg rw;
	reg Valid;
	reg reset;
	reg clk;
	wire [31:0] Dout;

	MEMORY DUT (Din, Addr, rw, Valid, reset, clk, Dout);

	initial begin

		$dumpvars(0, testbench_MEMORY);
		$dumpfile("my.vcd");

		clk = 0;
		forever
			#5 clk = ~clk;

	end

	initial begin 

		reset = 1;
		Din = 32'h5;
		Addr = 8'h0;
		#5
		display;

		reset = 0;
		Valid = 1;
		rw = 1;
		Din = 32'h5;
		Addr = 8'h0;
		#5
		display;

		rw = 1;
		Din = 32'h5;
		Addr = 8'h0;
		#5
		display;

		rw = 0;
		Din = 32'h5;
		Addr = 8'h0;
		#5
		display;

		rw = 1;
		Din = 32'h5;
		Addr = 8'h0;
		#5
		display;

		Valid = 0;
		rw = 1;
		Din = 32'h5;
		Addr = 8'h0;
		#5
		display;

		Valid = 1;
		rw = 1;
		Din = 32'hF00;
		Addr = 8'h2C;
		#5
		display;

		rw = 0;
		Din = 32'hF00;
		Addr = 8'h2C;
		#5
		display;

		rw = 1;
		Din = 32'hF00;
		Addr = 8'h2C;
		#13
		display;

		rw = 0;
		Din = 32'hF00;
		Addr = 8'h2C;
		#5
		display;



		#270
		$finish;
		end
	
	task display;
		$display("reset = %0h, clk = %0h, valid = %0h, rw = %0h, Din = %0h, Addr = %0h, Dout = %0h", reset, clk, Valid, rw, Din, Addr, Dout);
	endtask

endmodule