data/full_repos/permissive/439087417/Add_Sub.v
data/verilator_xmls/f743fd26-1201-4121-8e06-0eb435751497.xml
module Add_Sub #(parameter dw = 'h10)
(	input [dw-1: 0] a, b,
	input add,
	output [dw-1: 0] c
    );

assign c = add ? a + b : a - b;

endmodule
module Add_Sub #(parameter dw = 'h10)
(	input [dw-1: 0] a, b,
	input add,
	output [dw-1: 0] c
    );


assign c = add ? a + b : a - b;

endmodule