data/full_repos/permissive/443520440/code/sd_photo_rw.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/443520440/code/sd_photo_rw.v:108: Multiple top level modules\n                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                              : ... Top module \'sd_read_photo\'\nmodule sd_read_photo(\n       ^~~~~~~~~~~~~\n                                                                              : ... Top module \'sd_write_photo\'\nmodule sd_write_photo(\n       ^~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module sd_read_photo(
    input                clk                ,
    input                get_photo_mode     ,
    input        [3:0]   select_photo_no    ,
    input                rd_busy            ,
    input                rd_val_en          ,
    output reg           rd_start_en        ,
    output      [18:0]   sd_rd_ram_addr     ,
    output reg  [31:0]   rd_sec_addr        
    );

    parameter READ_TIME = 1200;
    parameter DIVIDED_CLK = 50000;


    reg                 send_clk            ;
    reg                 get_photo_mode_0    ;
    reg                 get_photo_mode_1    ;
    reg         [18:0]  sd_rd_ram_addr_t    ;
    wire                get_photo_mode_ena  ;
    integer             cnt = 0             ;
    initial rd_sec_addr <= 0;


    always @(posedge clk) begin
        cnt <= cnt + 1;
        if(cnt == DIVIDED_CLK) begin
            cnt <= 0;
            send_clk <= 1;
        end
        else
            send_clk <= 0;
    end
   

    assign get_photo_mode_ena = get_photo_mode_0 & ~get_photo_mode_1;
    always @(posedge clk) begin
        get_photo_mode_0 <= get_photo_mode;
        get_photo_mode_1 <= get_photo_mode_0;
    end


    reg [10:0] start_cnt;
    initial start_cnt <= 0;
    always @(posedge clk) begin
        if(get_photo_mode_ena) begin
            start_cnt <= 1;
            case (select_photo_no)
                4'h0: rd_sec_addr <= 32'd73743;
                4'h1: rd_sec_addr <= 32'd74943;
                4'h2: rd_sec_addr <= 32'd76143;
                4'h3: rd_sec_addr <= 32'd77343;
                4'h4: rd_sec_addr <= 32'd78543;
                4'h5: rd_sec_addr <= 32'd79743;
                4'h6: rd_sec_addr <= 32'd80943;
                4'h7: rd_sec_addr <= 32'd82143;
                4'h8: rd_sec_addr <= 32'd83343;
                4'h9: rd_sec_addr <= 32'd84543;
                4'ha: rd_sec_addr <= 32'd85743;
                4'hb: rd_sec_addr <= 32'd86943;
                4'hc: rd_sec_addr <= 32'd88143;
                4'hd: rd_sec_addr <= 32'd89343;
                4'he: rd_sec_addr <= 32'd90543;
                4'hf: rd_sec_addr <= 32'd91743;
                default: rd_sec_addr <= 32'd73743;
            endcase
        end
        rd_start_en <= 0;
        if(send_clk && ~rd_busy && start_cnt > 0) begin
            rd_start_en <= 1;
            rd_sec_addr <= rd_sec_addr + 1;
            start_cnt <= start_cnt + 1;
            if(start_cnt == READ_TIME) begin
                start_cnt <= 0;
            end
        end
    end


    assign sd_rd_ram_addr = (sd_rd_ram_addr_t > 0) ? sd_rd_ram_addr_t - 19'd1 : 19'd0;
    always@(posedge clk) begin
        if(!get_photo_mode) begin
            sd_rd_ram_addr_t <= 19'b0;
        end else if(rd_val_en) begin
            if(sd_rd_ram_addr_t < 19'd307219) begin
                sd_rd_ram_addr_t <= sd_rd_ram_addr_t +19'd1;
            end
            else begin
                sd_rd_ram_addr_t <= 19'd0;
            end
        end
    end

endmodule
module sd_read_photo(
    input                clk                ,
    input                get_photo_mode     ,
    input        [3:0]   select_photo_no    ,
    input                rd_busy            ,
    input                rd_val_en          ,
    output reg           rd_start_en        ,
    output      [18:0]   sd_rd_ram_addr     ,
    output reg  [31:0]   rd_sec_addr        
    );


    parameter READ_TIME = 1200;
    parameter DIVIDED_CLK = 50000;


    reg                 send_clk            ;
    reg                 get_photo_mode_0    ;
    reg                 get_photo_mode_1    ;
    reg         [18:0]  sd_rd_ram_addr_t    ;
    wire                get_photo_mode_ena  ;
    integer             cnt = 0             ;
    initial rd_sec_addr <= 0;


    always @(posedge clk) begin
        cnt <= cnt + 1;
        if(cnt == DIVIDED_CLK) begin
            cnt <= 0;
            send_clk <= 1;
        end
        else
            send_clk <= 0;
    end
   

    assign get_photo_mode_ena = get_photo_mode_0 & ~get_photo_mode_1;
    always @(posedge clk) begin
        get_photo_mode_0 <= get_photo_mode;
        get_photo_mode_1 <= get_photo_mode_0;
    end


    reg [10:0] start_cnt;
    initial start_cnt <= 0;
    always @(posedge clk) begin
        if(get_photo_mode_ena) begin
            start_cnt <= 1;
            case (select_photo_no)
                4'h0: rd_sec_addr <= 32'd73743;
                4'h1: rd_sec_addr <= 32'd74943;
                4'h2: rd_sec_addr <= 32'd76143;
                4'h3: rd_sec_addr <= 32'd77343;
                4'h4: rd_sec_addr <= 32'd78543;
                4'h5: rd_sec_addr <= 32'd79743;
                4'h6: rd_sec_addr <= 32'd80943;
                4'h7: rd_sec_addr <= 32'd82143;
                4'h8: rd_sec_addr <= 32'd83343;
                4'h9: rd_sec_addr <= 32'd84543;
                4'ha: rd_sec_addr <= 32'd85743;
                4'hb: rd_sec_addr <= 32'd86943;
                4'hc: rd_sec_addr <= 32'd88143;
                4'hd: rd_sec_addr <= 32'd89343;
                4'he: rd_sec_addr <= 32'd90543;
                4'hf: rd_sec_addr <= 32'd91743;
                default: rd_sec_addr <= 32'd73743;
            endcase
        end
        rd_start_en <= 0;
        if(send_clk && ~rd_busy && start_cnt > 0) begin
            rd_start_en <= 1;
            rd_sec_addr <= rd_sec_addr + 1;
            start_cnt <= start_cnt + 1;
            if(start_cnt == READ_TIME) begin
                start_cnt <= 0;
            end
        end
    end


    assign sd_rd_ram_addr = (sd_rd_ram_addr_t > 0) ? sd_rd_ram_addr_t - 19'd1 : 19'd0;
    always@(posedge clk) begin
        if(!get_photo_mode) begin
            sd_rd_ram_addr_t <= 19'b0;
        end else if(rd_val_en) begin
            if(sd_rd_ram_addr_t < 19'd307219) begin
                sd_rd_ram_addr_t <= sd_rd_ram_addr_t +19'd1;
            end
            else begin
                sd_rd_ram_addr_t <= 19'd0;
            end
        end
    end

endmodule