data/full_repos/permissive/522534105/RTL_files/Multiplier.v
data/verilator_xmls/f8d6a873-99fe-4b26-8ccc-0b708a57ceba.xml
module Multiplier(
input i_clk , 
input clr_q , 
input [`WIDTH_DATA_Q-1:0] i_data_q, 
input i_AQ , 
input ld_Q , 
output [`WIDTH_Q-1:0] o_data_Q );

reg [`WIDTH_Q-1:0] o_Qout ;
always @(posedge i_clk )
          begin
        if (clr_q==1'b1)
           o_Qout <= 0;
        else      
           if (ld_Q==1'b1)
                     o_Qout <= {i_data_q, 1'b0};
                       else 
            o_Qout <= {i_AQ, o_Qout[4:1]};
   end
 
 assign o_data_Q = o_Qout ;  
   
endmodule
module Multiplier(
input i_clk , 
input clr_q , 
input [`WIDTH_DATA_Q-1:0] i_data_q, 
input i_AQ , 
input ld_Q , 
output [`WIDTH_Q-1:0] o_data_Q );


reg [`WIDTH_Q-1:0] o_Qout ;
always @(posedge i_clk )
          begin
        if (clr_q==1'b1)
           o_Qout <= 0;
        else      
           if (ld_Q==1'b1)
                     o_Qout <= {i_data_q, 1'b0};
                       else 
            o_Qout <= {i_AQ, o_Qout[4:1]};
   end
 
 assign o_data_Q = o_Qout ;  
   
endmodule