data/full_repos/permissive/497660825/fpga-soc/top_SoC.v
1: b"%Error: data/full_repos/permissive/497660825/fpga-soc/top_SoC.v:11: Cannot find file containing module: 'clk_wiz_0'\nclk_wiz_0 uut1\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/497660825/fpga-soc,data/full_repos/permissive/497660825/clk_wiz_0\n             data/full_repos/permissive/497660825/fpga-soc,data/full_repos/permissive/497660825/clk_wiz_0.v\n             data/full_repos/permissive/497660825/fpga-soc,data/full_repos/permissive/497660825/clk_wiz_0.sv\n             clk_wiz_0\n             clk_wiz_0.v\n             clk_wiz_0.sv\n             obj_dir/clk_wiz_0\n             obj_dir/clk_wiz_0.v\n             obj_dir/clk_wiz_0.sv\n%Error: data/full_repos/permissive/497660825/fpga-soc/top_SoC.v:21: Cannot find file containing module: 'rvmyth'\nrvmyth uut2 (core_clk,core_reset,dac_out);  \n^~~~~~\n%Error: data/full_repos/permissive/497660825/fpga-soc/top_SoC.v:23: Cannot find file containing module: 'ila_0'\nila_0 uut3 (\n^~~~~\n%Error: Exiting due to 3 error(s)\n"
module top_SoC(main_clk,pll_reset,core_reset,dac_out);

input main_clk;
input pll_reset,core_reset;
output [7:0] dac_out;

wire locked;
wire core_clk;

clk_wiz_0 uut1
   (

    .clk_out1(core_clk),

    .reset(pll_reset),
    .locked(locked),

    .clk_in1(main_clk));
    
rvmyth uut2 (core_clk,core_reset,dac_out);  
    
ila_0 uut3 (
	.clk(main_clk),
	.probe0(dac_out),
	.probe1(core_reset),
	.probe2(core_clk)
	
);    
    
endmodule
module top_SoC(main_clk,pll_reset,core_reset,dac_out);


input main_clk;
input pll_reset,core_reset;
output [7:0] dac_out;

wire locked;
wire core_clk;

clk_wiz_0 uut1
   (

    .clk_out1(core_clk),

    .reset(pll_reset),
    .locked(locked),

    .clk_in1(main_clk));
    
rvmyth uut2 (core_clk,core_reset,dac_out);  
    
ila_0 uut3 (
	.clk(main_clk),
	.probe0(dac_out),
	.probe1(core_reset),
	.probe2(core_clk)
	
);    
    
endmodule