data/full_repos/permissive/514862365/FIFO_BUFFER_MEMORY.v
1: b'%Warning-WIDTH: data/full_repos/permissive/514862365/FIFO_BUFFER_MEMORY.v:26: Operator LT expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'count\' generates 3 bits.\n                                                                            : ... In instance FIFO_BUFFER_MEMORY\n  else if (write==1\'b1 && count<8) begin\n                               ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/514862365/FIFO_BUFFER_MEMORY.v:35: Operator EQ expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'read_pointer\' generates 3 bits.\n                                                                            : ... In instance FIFO_BUFFER_MEMORY\n else if (read_pointer==8) \n                      ^~\n%Warning-WIDTH: data/full_repos/permissive/514862365/FIFO_BUFFER_MEMORY.v:33: Operator EQ expects 32 or 4 bits on the LHS, but LHS\'s VARREF \'write_pointer\' generates 3 bits.\n                                                                            : ... In instance FIFO_BUFFER_MEMORY\n if (write_pointer==8) \n                  ^~\n%Error: Exiting due to 3 warning(s)\n'
module FIFO_BUFFER_MEMORY( clock, data_in, read, write,  enable, data_out, reset,empty ); 

input  clock, read, write, enable, reset;
input   [31:0]    data_in;
output  empty;
output reg [31:0] data_out; 

reg [2:0]  count = 0;
reg [31:0] memory [0:7];
reg [2:0]  read_pointer = 0; 
reg [2:0]  write_pointer = 0;

assign empty = (count==0)? 1'b1:1'b0; 
always @ (posedge clock) 
begin 
 if (enable==0);
 else begin 
  if (reset) begin 
   read_pointer = 0; 
   write_pointer = 0; 
  end 
  else if (read ==1'b1 && count!=0) begin 
   data_out  = memory[read_pointer]; 
   read_pointer = read_pointer+1; 
  end 
  else if (write==1'b1 && count<8) begin
   memory[write_pointer]  = data_in; 
   write_pointer  = write_pointer+1; 
  end 
  else; 
 end 

 if (write_pointer==8) 
  write_pointer=0; 
 else if (read_pointer==8) 
  read_pointer=0; 
 else;

 if (read_pointer > write_pointer) begin 
  count=read_pointer-write_pointer; 
 end 
 else if (write_pointer > read_pointer) 
  count=write_pointer-read_pointer; 
 else;
end 

endmodule
module FIFO_BUFFER_MEMORY( clock, data_in, read, write,  enable, data_out, reset,empty );
 

input  clock, read, write, enable, reset;
input   [31:0]    data_in;
output  empty;
output reg [31:0] data_out; 

reg [2:0]  count = 0;
reg [31:0] memory [0:7];
reg [2:0]  read_pointer = 0; 
reg [2:0]  write_pointer = 0;

assign empty = (count==0)? 1'b1:1'b0; 
always @ (posedge clock) 
begin 
 if (enable==0);
 else begin 
  if (reset) begin 
   read_pointer = 0; 
   write_pointer = 0; 
  end 
  else if (read ==1'b1 && count!=0) begin 
   data_out  = memory[read_pointer]; 
   read_pointer = read_pointer+1; 
  end 
  else if (write==1'b1 && count<8) begin
   memory[write_pointer]  = data_in; 
   write_pointer  = write_pointer+1; 
  end 
  else; 
 end 

 if (write_pointer==8) 
  write_pointer=0; 
 else if (read_pointer==8) 
  read_pointer=0; 
 else;

 if (read_pointer > write_pointer) begin 
  count=read_pointer-write_pointer; 
 end 
 else if (write_pointer > read_pointer) 
  count=write_pointer-read_pointer; 
 else;
end 

endmodule