data/full_repos/permissive/516340086/level3_design_corrected/lcd.v
data/verilator_xmls/a7ecf879-c8cc-4d2c-a955-fc2a9b5bdf86.xml
module lcd(
   input clk, 
   output reg [7:0] dout
    );
 
integer count = 0;
integer  i = 0;
reg rs, rw;
reg en; 
parameter send_cmd  = 0;
parameter send_data = 1;
reg state = send_cmd;
 
reg [7:0] data [11:0];

 
initial begin
 

data[0] <= 8'h38;
data[1] <= 8'h01;
data[2] <= 8'h0E;
data[3] <= 8'h06;
data[4] <= 8'h80;
 

data[5]  <= 8'h76;
data[6]  <= 8'h65;
data[7]  <= 8'h72;
data[8]  <= 8'h69;
data[9]  <= 8'h6c;
data[10] <= 8'h6f;
data[11] <= 8'h67;
end

 
always@(posedge clk)
begin
case(state)
send_cmd : 
begin
  if(i <= 4) 
   begin
    rs <= 1'b0;
    rw <= 1'b0;
    dout <= data[i];
    i <= i + 1;
   end
  else
    begin
    state <= send_data;
    dout <= data[i];
    i <= i + 1;
    end
end
 
send_data : 
begin
  if(i <= 11)
   begin
    rs   <= 1'b1;
    rw   <= 1'b0; 
    dout <= data[i];
    i <= i + 1; 
   end
 else
   begin
   i <= 0;
   state <= send_cmd;
   rs    <= 1'b0;
   rw    <= 1'b0;
   dout  <= 8'h00;
   end
end
 
endcase
 
end
 
assign en = clk;

endmodule
module lcd(
   input clk, 
   output reg [7:0] dout
    );

 
integer count = 0;
integer  i = 0;
reg rs, rw;
reg en; 
parameter send_cmd  = 0;
parameter send_data = 1;
reg state = send_cmd;
 
reg [7:0] data [11:0];

 
initial begin
 

data[0] <= 8'h38;
data[1] <= 8'h01;
data[2] <= 8'h0E;
data[3] <= 8'h06;
data[4] <= 8'h80;
 

data[5]  <= 8'h76;
data[6]  <= 8'h65;
data[7]  <= 8'h72;
data[8]  <= 8'h69;
data[9]  <= 8'h6c;
data[10] <= 8'h6f;
data[11] <= 8'h67;
end

 
always@(posedge clk)
begin
case(state)
send_cmd : 
begin
  if(i <= 4) 
   begin
    rs <= 1'b0;
    rw <= 1'b0;
    dout <= data[i];
    i <= i + 1;
   end
  else
    begin
    state <= send_data;
    dout <= data[i];
    i <= i + 1;
    end
end
 
send_data : 
begin
  if(i <= 11)
   begin
    rs   <= 1'b1;
    rw   <= 1'b0; 
    dout <= data[i];
    i <= i + 1; 
   end
 else
   begin
   i <= 0;
   state <= send_cmd;
   rs    <= 1'b0;
   rw    <= 1'b0;
   dout  <= 8'h00;
   end
end
 
endcase
 
end
 
assign en = clk;

endmodule