data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/clk/rtl/ct_clk_top.v
1: b"%Error: data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/clk/rtl/ct_clk_top.v:72: Cannot find file containing module: 'BUFGCE'\nBUFGCE core_clk_buf\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/clk/rtl,data/full_repos/permissive/418752214/BUFGCE\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/clk/rtl,data/full_repos/permissive/418752214/BUFGCE.v\n             data/full_repos/permissive/418752214/C910_RTL_FACTORY/gen_rtl/clk/rtl,data/full_repos/permissive/418752214/BUFGCE.sv\n             BUFGCE\n             BUFGCE.v\n             BUFGCE.sv\n             obj_dir/BUFGCE\n             obj_dir/BUFGCE.v\n             obj_dir/BUFGCE.sv\n%Error: Exiting due to 1 error(s)\n"
module ct_clk_top(
  biu_xx_dbg_wakeup,
  biu_xx_int_wakeup,
  biu_xx_normal_work,
  biu_xx_pmp_sel,
  biu_xx_snoop_vld,
  coreclk,
  cp0_xx_core_icg_en,
  forever_coreclk,
  had_xx_clk_en,
  pll_core_clk
);


input        biu_xx_dbg_wakeup; 
input        biu_xx_int_wakeup; 
input        biu_xx_normal_work; 
input        biu_xx_pmp_sel;    
input        biu_xx_snoop_vld;  
input        cp0_xx_core_icg_en; 
input        had_xx_clk_en;     
input        pll_core_clk;      
output       coreclk;           
output       forever_coreclk;   




wire         biu_xx_dbg_wakeup; 
wire         biu_xx_int_wakeup; 
wire         biu_xx_normal_work; 
wire         biu_xx_pmp_sel;    
wire         biu_xx_snoop_vld;  
wire         core_clk_en;       
wire         cp0_xx_core_icg_en; 
wire         forever_coreclk;   
wire         had_xx_clk_en;     
wire         pll_core_clk;      




assign forever_coreclk = pll_core_clk;



assign core_clk_en = biu_xx_normal_work |
                     biu_xx_int_wakeup | 
                     biu_xx_dbg_wakeup | 
                     biu_xx_snoop_vld |
                     had_xx_clk_en | 
                     biu_xx_pmp_sel |
                     cp0_xx_core_icg_en ;


BUFGCE core_clk_buf
(.O   (coreclk),
 .I   (forever_coreclk),
 .CE  (core_clk_en)
);









endmodule
module ct_clk_top(
  biu_xx_dbg_wakeup,
  biu_xx_int_wakeup,
  biu_xx_normal_work,
  biu_xx_pmp_sel,
  biu_xx_snoop_vld,
  coreclk,
  cp0_xx_core_icg_en,
  forever_coreclk,
  had_xx_clk_en,
  pll_core_clk
);



input        biu_xx_dbg_wakeup; 
input        biu_xx_int_wakeup; 
input        biu_xx_normal_work; 
input        biu_xx_pmp_sel;    
input        biu_xx_snoop_vld;  
input        cp0_xx_core_icg_en; 
input        had_xx_clk_en;     
input        pll_core_clk;      
output       coreclk;           
output       forever_coreclk;   




wire         biu_xx_dbg_wakeup; 
wire         biu_xx_int_wakeup; 
wire         biu_xx_normal_work; 
wire         biu_xx_pmp_sel;    
wire         biu_xx_snoop_vld;  
wire         core_clk_en;       
wire         cp0_xx_core_icg_en; 
wire         forever_coreclk;   
wire         had_xx_clk_en;     
wire         pll_core_clk;      




assign forever_coreclk = pll_core_clk;



assign core_clk_en = biu_xx_normal_work |
                     biu_xx_int_wakeup | 
                     biu_xx_dbg_wakeup | 
                     biu_xx_snoop_vld |
                     had_xx_clk_en | 
                     biu_xx_pmp_sel |
                     cp0_xx_core_icg_en ;


BUFGCE core_clk_buf
(.O   (coreclk),
 .I   (forever_coreclk),
 .CE  (core_clk_en)
);









endmodule