data/full_repos/permissive/484543204/verilog/rtl/grp_15_project_wrapper.v
1: b"%Error: data/full_repos/permissive/484543204/verilog/rtl/grp_15_project_wrapper.v:43: Define or directive not defined: '`MPRJ_IO_PADS'\n  input  [`MPRJ_IO_PADS-1:0] io_in,\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/484543204/verilog/rtl/grp_15_project_wrapper.v:44: Define or directive not defined: '`MPRJ_IO_PADS'\n  output [`MPRJ_IO_PADS-1:0] io_out,\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/484543204/verilog/rtl/grp_15_project_wrapper.v:45: Define or directive not defined: '`MPRJ_IO_PADS'\n  output [`MPRJ_IO_PADS-1:0] io_oeb,\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/484543204/verilog/rtl/grp_15_project_wrapper.v:49: Define or directive not defined: '`MPRJ_IO_PADS'\n  inout  [`MPRJ_IO_PADS-10:0] analog_io,\n          ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module user_project_wrapper
#(
  parameter BITS = 32
)(
`ifdef USE_POWER_PINS
  inout vdda1,
  inout vdda2,
  inout vssa1,
  inout vssa2,
  inout vccd1,
  inout vccd2,
  inout vssd1,
  inout vssd2,
`endif



  input                      wb_clk_i,
  input                      wb_rst_i,
  input                      wbs_stb_i,
  input                      wbs_cyc_i,
  input                      wbs_we_i,
  input  [3:0]               wbs_sel_i,
  input  [31:0]              wbs_dat_i,
  input  [31:0]              wbs_adr_i,
  output                     wbs_ack_o,
  output [31:0]              wbs_dat_o,



  input  [127:0]             la_data_in,
  output [127:0]             la_data_out,
  input  [127:0]             la_oenb,



  input  [`MPRJ_IO_PADS-1:0] io_in,
  output [`MPRJ_IO_PADS-1:0] io_out,
  output [`MPRJ_IO_PADS-1:0] io_oeb,



  inout  [`MPRJ_IO_PADS-10:0] analog_io,



  input                       user_clock2,



  output [2:0]                user_irq
);

  grp_15_SPI_TapeOutBlockRTL_32bits_5entries grp_15
  (
  `ifdef USE_POWER_PINS
    .vccd1(vccd1),
    .vssd1(vssd1),
  `endif
    .adapter_parity  (io_out[37]),
    .clk             (io_in[11]),
    .loopthrough_sel (io_in[35]),
    .minion_parity   (io_out[36]),
    .reset           (io_in[10]),
    .spi_min_cs      (io_in[8]),
    .spi_min_miso    (io_out[33]),
    .spi_min_mosi    (io_in[34]),
    .spi_min_sclk    (io_in[9]),
    .clk_en          (),
    .reset_en        (),
    .lt_sel_en       (io_oeb[35]),
    .mp_en           (io_oeb[36]),
    .ap_en           (io_oeb[37]),
    .cs_en           (io_oeb[8]),
    .sclk_en         (io_oeb[9]),
    .miso_en         (io_oeb[33]),
    .mosi_en         (io_oeb[34])
  );

endmodule
module user_project_wrapper
#(
  parameter BITS = 32
)(
`ifdef USE_POWER_PINS
  inout vdda1,
  inout vdda2,
  inout vssa1,
  inout vssa2,
  inout vccd1,
  inout vccd2,
  inout vssd1,
  inout vssd2,
`endif



  input                      wb_clk_i,
  input                      wb_rst_i,
  input                      wbs_stb_i,
  input                      wbs_cyc_i,
  input                      wbs_we_i,
  input  [3:0]               wbs_sel_i,
  input  [31:0]              wbs_dat_i,
  input  [31:0]              wbs_adr_i,
  output                     wbs_ack_o,
  output [31:0]              wbs_dat_o,



  input  [127:0]             la_data_in,
  output [127:0]             la_data_out,
  input  [127:0]             la_oenb,



  input  [`MPRJ_IO_PADS-1:0] io_in,
  output [`MPRJ_IO_PADS-1:0] io_out,
  output [`MPRJ_IO_PADS-1:0] io_oeb,



  inout  [`MPRJ_IO_PADS-10:0] analog_io,



  input                       user_clock2,



  output [2:0]                user_irq
);


  grp_15_SPI_TapeOutBlockRTL_32bits_5entries grp_15
  (
  `ifdef USE_POWER_PINS
    .vccd1(vccd1),
    .vssd1(vssd1),
  `endif
    .adapter_parity  (io_out[37]),
    .clk             (io_in[11]),
    .loopthrough_sel (io_in[35]),
    .minion_parity   (io_out[36]),
    .reset           (io_in[10]),
    .spi_min_cs      (io_in[8]),
    .spi_min_miso    (io_out[33]),
    .spi_min_mosi    (io_in[34]),
    .spi_min_sclk    (io_in[9]),
    .clk_en          (),
    .reset_en        (),
    .lt_sel_en       (io_oeb[35]),
    .mp_en           (io_oeb[36]),
    .ap_en           (io_oeb[37]),
    .cs_en           (io_oeb[8]),
    .sclk_en         (io_oeb[9]),
    .miso_en         (io_oeb[33]),
    .mosi_en         (io_oeb[34])
  );

endmodule