data/full_repos/permissive/493019833/test/testcase/firrtl/TopOfVisualizer/reference/TopOfVisualizer.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/TopOfVisualizer/reference/TopOfVisualizer.v:219: Operator COND expects 32 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 16 bits.\n                                                                                                                         : ... In instance TopOfVisualizer.u_pad_6\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module VizModA(
    input clock,
    input reset,
    input [31:0] io_in,
    output [15:0] io_out
);
    wire _modC__clock;
    wire _modC__reset;
    wire [15:0] _modC__io_in;
    wire [15:0] _modC__io_out;
    VizModC modC (
        .clock(_modC__clock),
        .reset(_modC__reset),
        .io_in(_modC__io_in),
        .io_out(_modC__io_out)
    );
    assign io_out = _modC__io_out;
    assign _modC__clock = clock;
    BITS #(.width(32), .high(15), .low(0)) bits_1 (
        .y(_modC__io_in),
        .in(io_in)
    );
    assign _modC__reset = reset;
endmodule
module VizModA(
    input clock,
    input reset,
    input [31:0] io_in,
    output [15:0] io_out
);

    wire _modC__clock;
    wire _modC__reset;
    wire [15:0] _modC__io_in;
    wire [15:0] _modC__io_out;
    VizModC modC (
        .clock(_modC__clock),
        .reset(_modC__reset),
        .io_in(_modC__io_in),
        .io_out(_modC__io_out)
    );
    assign io_out = _modC__io_out;
    assign _modC__clock = clock;
    BITS #(.width(32), .high(15), .low(0)) bits_1 (
        .y(_modC__io_in),
        .in(io_in)
    );
    assign _modC__reset = reset;
endmodule