data/full_repos/permissive/431863558/flip-flops/t_D_flip_flop.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/431863558/flip-flops/t_D_flip_flop.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #10 CLK = ~CLK;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/431863558/flip-flops/t_D_flip_flop.v:21: Unsupported: Ignoring delay on this delayed statement.\n   #10 RST = 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/431863558/flip-flops/t_D_flip_flop.v:22: Unsupported: Ignoring delay on this delayed statement.\n   #10 D = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/431863558/flip-flops/t_D_flip_flop.v:23: Unsupported: Ignoring delay on this delayed statement.\n   #20 D = 1;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/431863558/flip-flops/t_D_flip_flop.v:24: Unsupported: Ignoring delay on this delayed statement.\n   #70 RST = 0;\n   ^\n%Warning-STMTDLY: data/full_repos/permissive/431863558/flip-flops/t_D_flip_flop.v:25: Unsupported: Ignoring delay on this delayed statement.\n   #90 RST = 1;\n   ^\n%Error: data/full_repos/permissive/431863558/flip-flops/t_D_flip_flop.v:30: Unsupported or unknown PLI call: $dumpfile\n              $dumpfile("example.vcd");\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/431863558/flip-flops/t_D_flip_flop.v:31: Unsupported or unknown PLI call: $dumpvars\n              $dumpvars(0, DFF_tb);\n              ^~~~~~~~~\n%Error: data/full_repos/permissive/431863558/flip-flops/t_D_flip_flop.v:32: Unsupported or unknown PLI call: $monitor\n   $monitor("At time = %g, CLK = %b, RST = %b, D = %b, Q = %b", $time, CLK, RST, D, Q);\n   ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/431863558/flip-flops/t_D_flip_flop.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #200 $finish;\n  ^\n%Error: Exiting due to 3 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module DFF_tb;
	reg CLK = 0;
	reg D, RST;
	wire Q;

	D_FF dut(.CLK(CLK), .RST(RST), .D(D), .Q(Q));

	always
		#10 CLK = ~CLK;

	initial
		begin
			RST = 0;
			#10 RST = 1;
			#10 D = 0;
			#20 D = 1;
			#70 RST = 0;
			#90 RST = 1;
		end
	
	initial
		begin 
            		$dumpfile("example.vcd");
            		$dumpvars(0, DFF_tb);
			$monitor("At time = %g, CLK = %b, RST = %b, D = %b, Q = %b", $time, CLK, RST, D, Q);
		end

	initial
		#200 $finish;
endmodule
module DFF_tb;

	reg CLK = 0;
	reg D, RST;
	wire Q;

	D_FF dut(.CLK(CLK), .RST(RST), .D(D), .Q(Q));

	always
		#10 CLK = ~CLK;

	initial
		begin
			RST = 0;
			#10 RST = 1;
			#10 D = 0;
			#20 D = 1;
			#70 RST = 0;
			#90 RST = 1;
		end
	
	initial
		begin 
            		$dumpfile("example.vcd");
            		$dumpvars(0, DFF_tb);
			$monitor("At time = %g, CLK = %b, RST = %b, D = %b, Q = %b", $time, CLK, RST, D, Q);
		end

	initial
		#200 $finish;
endmodule