data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/ecc_synth.sv
1: b"%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/common_cells/test/ecc_synth.sv:15: syntax error, unexpected ::, expecting ':'\n        logic [ecc_pkg::get_cw_width(dw)-1:0] codeword;\n                      ^~\n                                                                                                    : ... Perhaps 'ecc_pkg' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: Exiting due to 1 error(s)\n"
module ecc_synth;

    for (genvar dw = 8; dw < 32; dw += 8) begin

        logic [ecc_pkg::get_cw_width(dw)-1:0] codeword;
        ecc_encode #(.DataWidth(dw)) i_encode (.data_i(), .data_o(codeword));
        ecc_decode #(.DataWidth(dw))
        i_decode (
            .data_i (codeword),
            .data_o (),
            .syndrome_o (),
            .single_error_o (),
            .double_error_o ()
        );
    end

endmodule
module ecc_synth;


    for (genvar dw = 8; dw < 32; dw += 8) begin

        logic [ecc_pkg::get_cw_width(dw)-1:0] codeword;
        ecc_encode #(.DataWidth(dw)) i_encode (.data_i(), .data_o(codeword));
        ecc_decode #(.DataWidth(dw))
        i_decode (
            .data_i (codeword),
            .data_o (),
            .syndrome_o (),
            .single_error_o (),
            .double_error_o ()
        );
    end

endmodule