data/full_repos/permissive/513199821/test.v
1: b'%Error: data/full_repos/permissive/513199821/test.v:1: Cannot find include file: global.inc\n`include "global.inc" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc.v\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc.sv\n             global.inc\n             global.inc.v\n             global.inc.sv\n             obj_dir/global.inc\n             obj_dir/global.inc.v\n             obj_dir/global.inc.sv\n%Warning-STMTDLY: data/full_repos/permissive/513199821/test.v:492: Unsupported: Ignoring delay on this delayed statement.\n  #32;    \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/513199821/test.v:494: Unsupported: Ignoring delay on this delayed statement.\n  #32;\n  ^\n%Error: data/full_repos/permissive/513199821/test.v:500: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile ("/tmp/eonsoc.lxt");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/513199821/test.v:501: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars (0, test);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/513199821/test.v:504: Unsupported or unknown PLI call: $timeformat\n  $timeformat (-6, 3, "us", 12);\n  ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/513199821/test.v:509: Unsupported: Ignoring delay on this delayed statement.\n  #128;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/513199821/test.v:514: Unsupported: Ignoring delay on this delayed statement.\n    #200;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/513199821/test.v:516: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/513199821/test.v:522: Unsupported: Ignoring delay on this delayed statement.\n    # 64;\n    ^\n%Error: Exiting due to 4 error(s), 6 warning(s)\n'
module test;

localparam EEPROM_PAGE = 8'd16;
localparam UART_DIV    = 139;


reg clk, rst;
wire rstn = ~rst;


wire terminate;


wire tx, scl, sda, led_r, led_h, ssn, sck, miso, mosi, uart_rx;


eonSoc #(
    .WIDTH	 (32),
    .RSTWIDTH	 (3),
    .I2CDIV	 (16'd3),
    .UART_DIV	 (UART_DIV),
    .EEPROM_PAGE (EEPROM_PAGE),
    .SPI_DIV	 (2)
  ) soc (
    .clk    (clk),
    .rstn   (rstn),
    .led_r  (led_r),
    .led_h  (led_h),

    .rx     (1'b0),
    .tx     (uart_rx),

    .scl    (scl),
    .sda    (sda),

    .ssn    (ssn),
    .sck    (sck),
    .mosi   (mosi),
    .miso   (miso)
  );


uartDump #(
    .CLKDIV (UART_DIV)
  ) uartd (
    .clk	 (clk),
    .resetn	 (rstn),
    .ser_rx	 (uart_rx),
    .reg_div_di  (UART_DIV)
);


Ic2Slave #(
    .READ_BYTES (EEPROM_PAGE)
  ) eeprom (
    .SDA (sda),
    .SCL (scl)
);


spi_ram sram (
    .clk     (sck),
    .mosi    (mosi),
    .ss_n    (ssn),
    .miso    (miso)
);


always begin
  #32;
  clk = 1'b0;
  #32;
  clk = 1'b1;
end

initial begin

  $dumpfile ("/tmp/eonsoc.lxt");
  $dumpvars (0, test);


  $timeformat (-6, 3, "us", 12);


  clk	= 1'b1;
  rst	= 1'b1;
  #128;
  rst	= 1'b0;


  if (0) repeat (4) begin
    #200;
    rst = 1'b1;
    #100;
    rst = 1'b0;
  end


  while (!led_h && soc.cpu0.cycle < 20'h20000) begin
    # 64;
  end


  $display ("\n\t%x %t", soc.cpu0.cycle, $time);
  $finish;
end

endmodule
module test;


localparam EEPROM_PAGE = 8'd16;
localparam UART_DIV    = 139;


reg clk, rst;
wire rstn = ~rst;


wire terminate;


wire tx, scl, sda, led_r, led_h, ssn, sck, miso, mosi, uart_rx;


eonSoc #(
    .WIDTH	 (32),
    .RSTWIDTH	 (3),
    .I2CDIV	 (16'd3),
    .UART_DIV	 (UART_DIV),
    .EEPROM_PAGE (EEPROM_PAGE),
    .SPI_DIV	 (2)
  ) soc (
    .clk    (clk),
    .rstn   (rstn),
    .led_r  (led_r),
    .led_h  (led_h),

    .rx     (1'b0),
    .tx     (uart_rx),

    .scl    (scl),
    .sda    (sda),

    .ssn    (ssn),
    .sck    (sck),
    .mosi   (mosi),
    .miso   (miso)
  );


uartDump #(
    .CLKDIV (UART_DIV)
  ) uartd (
    .clk	 (clk),
    .resetn	 (rstn),
    .ser_rx	 (uart_rx),
    .reg_div_di  (UART_DIV)
);


Ic2Slave #(
    .READ_BYTES (EEPROM_PAGE)
  ) eeprom (
    .SDA (sda),
    .SCL (scl)
);


spi_ram sram (
    .clk     (sck),
    .mosi    (mosi),
    .ss_n    (ssn),
    .miso    (miso)
);


always begin
  #32;
  clk = 1'b0;
  #32;
  clk = 1'b1;
end

initial begin

  $dumpfile ("/tmp/eonsoc.lxt");
  $dumpvars (0, test);


  $timeformat (-6, 3, "us", 12);


  clk	= 1'b1;
  rst	= 1'b1;
  #128;
  rst	= 1'b0;


  if (0) repeat (4) begin
    #200;
    rst = 1'b1;
    #100;
    rst = 1'b0;
  end


  while (!led_h && soc.cpu0.cycle < 20'h20000) begin
    # 64;
  end


  $display ("\n\t%x %t", soc.cpu0.cycle, $time);
  $finish;
end

endmodule