data/full_repos/permissive/49670587/vtr/ODIN_II/FULL_REGRESSION_TESTS/ch_intrinsics.v
1: b'%Error: data/full_repos/permissive/49670587/vtr/ODIN_II/FULL_REGRESSION_TESTS/ch_intrinsics.v:31: Cannot find file containing module: \'single_port_ram\'\nsingle_port_ram _str (\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/49670587/vtr/ODIN_II/FULL_REGRESSION_TESTS,data/full_repos/permissive/49670587/single_port_ram\n             data/full_repos/permissive/49670587/vtr/ODIN_II/FULL_REGRESSION_TESTS,data/full_repos/permissive/49670587/single_port_ram.v\n             data/full_repos/permissive/49670587/vtr/ODIN_II/FULL_REGRESSION_TESTS,data/full_repos/permissive/49670587/single_port_ram.sv\n             single_port_ram\n             single_port_ram.v\n             single_port_ram.sv\n             obj_dir/single_port_ram\n             obj_dir/single_port_ram.v\n             obj_dir/single_port_ram.sv\n%Warning-WIDTH: data/full_repos/permissive/49670587/vtr/ODIN_II/FULL_REGRESSION_TESTS/ch_intrinsics.v:63: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'str_out\' generates 8 bits.\n                                                                                                        : ... In instance memset.memtroll\n  memory_controller_out = str_out;\n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module memory_controller
(
	clk,
	memory_controller_address,
	memory_controller_write_enable,
	memory_controller_in,
	memory_controller_out
);
input clk;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
input memory_controller_write_enable;
input [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
output  [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;


reg [4:0] str_address;
reg str_write_enable;
reg [7:0] str_in;
wire [7:0] str_out;

single_port_ram _str (
	.clk( clk ),
	.addr( str_address ),
	.we( str_write_enable ),
	.data( str_in ),
	.out( str_out )
);


wire  tag;


assign tag = |memory_controller_address & |memory_controller_address & | memory_controller_in;
reg [`MEMORY_CONTROLLER_TAG_SIZE-1:0] prevTag;
always @(posedge clk)
	prevTag <= tag;
always @( tag or memory_controller_address or memory_controller_write_enable or memory_controller_in)
begin

case(tag)

	1'b0:
	begin
		str_address = memory_controller_address[5-1+0:0];
		str_write_enable = memory_controller_write_enable;
		str_in[8-1:0] = memory_controller_in[8-1:0];
	end
endcase

case(prevTag)

	1'b0:
		memory_controller_out = str_out;
endcase
end

endmodule
module memory_controller
(
	clk,
	memory_controller_address,
	memory_controller_write_enable,
	memory_controller_in,
	memory_controller_out
);

input clk;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
input memory_controller_write_enable;
input [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
output  [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;


reg [4:0] str_address;
reg str_write_enable;
reg [7:0] str_in;
wire [7:0] str_out;

single_port_ram _str (
	.clk( clk ),
	.addr( str_address ),
	.we( str_write_enable ),
	.data( str_in ),
	.out( str_out )
);


wire  tag;


assign tag = |memory_controller_address & |memory_controller_address & | memory_controller_in;
reg [`MEMORY_CONTROLLER_TAG_SIZE-1:0] prevTag;
always @(posedge clk)
	prevTag <= tag;
always @( tag or memory_controller_address or memory_controller_write_enable or memory_controller_in)
begin

case(tag)

	1'b0:
	begin
		str_address = memory_controller_address[5-1+0:0];
		str_write_enable = memory_controller_write_enable;
		str_in[8-1:0] = memory_controller_in[8-1:0];
	end
endcase

case(prevTag)

	1'b0:
		memory_controller_out = str_out;
endcase
end

endmodule