data/full_repos/permissive/41686596/Four_Digit_Seven_Segment_Display_2.0/src/seven_segment_display_x_4.v
1: b'%Warning-WIDTH: data/full_repos/permissive/41686596/Four_Digit_Seven_Segment_Display_2.0/src/seven_segment_display_x_4.v:52: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h40\' generates 8 bits.\n                                                                                                                           : ... In instance seven_segment_display_x_4\n        0: a_to_g = 8\'b1000000;   \n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/41686596/Four_Digit_Seven_Segment_Display_2.0/src/seven_segment_display_x_4.v:53: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h79\' generates 8 bits.\n                                                                                                                           : ... In instance seven_segment_display_x_4\n        1: a_to_g = 8\'b1111001;   \n                  ^\n%Warning-WIDTH: data/full_repos/permissive/41686596/Four_Digit_Seven_Segment_Display_2.0/src/seven_segment_display_x_4.v:54: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h24\' generates 8 bits.\n                                                                                                                           : ... In instance seven_segment_display_x_4\n        2: a_to_g = 8\'b0100100;   \n                  ^\n%Warning-WIDTH: data/full_repos/permissive/41686596/Four_Digit_Seven_Segment_Display_2.0/src/seven_segment_display_x_4.v:55: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h30\' generates 8 bits.\n                                                                                                                           : ... In instance seven_segment_display_x_4\n        3: a_to_g = 8\'b0110000;   \n                  ^\n%Warning-WIDTH: data/full_repos/permissive/41686596/Four_Digit_Seven_Segment_Display_2.0/src/seven_segment_display_x_4.v:56: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h19\' generates 8 bits.\n                                                                                                                           : ... In instance seven_segment_display_x_4\n        4: a_to_g = 8\'b0011001;   \n                  ^\n%Warning-WIDTH: data/full_repos/permissive/41686596/Four_Digit_Seven_Segment_Display_2.0/src/seven_segment_display_x_4.v:57: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h12\' generates 8 bits.\n                                                                                                                           : ... In instance seven_segment_display_x_4\n        5: a_to_g = 8\'b0010010;   \n                  ^\n%Warning-WIDTH: data/full_repos/permissive/41686596/Four_Digit_Seven_Segment_Display_2.0/src/seven_segment_display_x_4.v:58: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h2\' generates 8 bits.\n                                                                                                                           : ... In instance seven_segment_display_x_4\n        6: a_to_g = 8\'b0000010;   \n                  ^\n%Warning-WIDTH: data/full_repos/permissive/41686596/Four_Digit_Seven_Segment_Display_2.0/src/seven_segment_display_x_4.v:59: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h78\' generates 8 bits.\n                                                                                                                           : ... In instance seven_segment_display_x_4\n        7: a_to_g = 8\'b1111000;   \n                  ^\n%Warning-WIDTH: data/full_repos/permissive/41686596/Four_Digit_Seven_Segment_Display_2.0/src/seven_segment_display_x_4.v:60: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                                                           : ... In instance seven_segment_display_x_4\n        8: a_to_g = 8\'b0000000;   \n                  ^\n%Warning-WIDTH: data/full_repos/permissive/41686596/Four_Digit_Seven_Segment_Display_2.0/src/seven_segment_display_x_4.v:61: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h10\' generates 8 bits.\n                                                                                                                           : ... In instance seven_segment_display_x_4\n        9: a_to_g = 8\'b0010000;   \n                  ^\n%Warning-WIDTH: data/full_repos/permissive/41686596/Four_Digit_Seven_Segment_Display_2.0/src/seven_segment_display_x_4.v:62: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'hff\' generates 8 bits.\n                                                                                                                           : ... In instance seven_segment_display_x_4\n        default: a_to_g = 8\'b11111111;   \n                        ^\n%Error: Exiting due to 11 warning(s)\n'
module seven_segment_display_x_4(
    input [15:0] bcd_in,
    input [3:0] decimal_points,
    input clk,
    output reg [6:0] a_to_g,
    output reg decimal_point,
    output reg [3:0] anode
    );
    
wire [1:0] counter;
reg [3:0] digit;
reg [19:0] clkdiv;    
         
assign counter = clkdiv[19:18];
    

always @(posedge clk)
    case(counter)
        0: {digit, decimal_point, anode} = {bcd_in[3:0], ~decimal_points[0],  4'b1110};
        1: {digit, decimal_point, anode} = {bcd_in[7:4], ~decimal_points[1],  4'b1101};
        2: {digit, decimal_point, anode} = {bcd_in[11:8], ~decimal_points[2], 4'b1011};
        3: {digit, decimal_point, anode} = {bcd_in[15:12], ~decimal_points[3],4'b0111};
     endcase
    

always @(posedge clk)
     case(digit)
        0: a_to_g = 8'b1000000;
        1: a_to_g = 8'b1111001;
        2: a_to_g = 8'b0100100;
        3: a_to_g = 8'b0110000;
        4: a_to_g = 8'b0011001;
        5: a_to_g = 8'b0010010;
        6: a_to_g = 8'b0000010;
        7: a_to_g = 8'b1111000;
        8: a_to_g = 8'b0000000;
        9: a_to_g = 8'b0010000;
        default: a_to_g = 8'b11111111;
    endcase
          
         

always  @ (posedge clk)
       begin
        clkdiv <= clkdiv + 20'b1;
       end 
           
endmodule
module seven_segment_display_x_4(
    input [15:0] bcd_in,
    input [3:0] decimal_points,
    input clk,
    output reg [6:0] a_to_g,
    output reg decimal_point,
    output reg [3:0] anode
    );

    
wire [1:0] counter;
reg [3:0] digit;
reg [19:0] clkdiv;    
         
assign counter = clkdiv[19:18];
    

always @(posedge clk)
    case(counter)
        0: {digit, decimal_point, anode} = {bcd_in[3:0], ~decimal_points[0],  4'b1110};
        1: {digit, decimal_point, anode} = {bcd_in[7:4], ~decimal_points[1],  4'b1101};
        2: {digit, decimal_point, anode} = {bcd_in[11:8], ~decimal_points[2], 4'b1011};
        3: {digit, decimal_point, anode} = {bcd_in[15:12], ~decimal_points[3],4'b0111};
     endcase
    

always @(posedge clk)
     case(digit)
        0: a_to_g = 8'b1000000;
        1: a_to_g = 8'b1111001;
        2: a_to_g = 8'b0100100;
        3: a_to_g = 8'b0110000;
        4: a_to_g = 8'b0011001;
        5: a_to_g = 8'b0010010;
        6: a_to_g = 8'b0000010;
        7: a_to_g = 8'b1111000;
        8: a_to_g = 8'b0000000;
        9: a_to_g = 8'b0010000;
        default: a_to_g = 8'b11111111;
    endcase
          
         

always  @ (posedge clk)
       begin
        clkdiv <= clkdiv + 20'b1;
       end 
           
endmodule