data/full_repos/permissive/515598112/2_Verilog_Language/05_More_Verilog_Features/06_Generate_for-loop_100_bit_binary_adder_2.v
1: b'%Warning-MODDUP: data/full_repos/permissive/515598112/2_Verilog_Language/05_More_Verilog_Features/06_Generate_for-loop_100_bit_binary_adder_2.v:38: Duplicate declaration of module: \'top_module\'\nmodule top_module( \n       ^~~~~~~~~~\n                 data/full_repos/permissive/515598112/2_Verilog_Language/05_More_Verilog_Features/06_Generate_for-loop_100_bit_binary_adder_2.v:1: ... Location of original declaration\nmodule top_module ( \n       ^~~~~~~~~~\n                 ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Warning-MODDUP: data/full_repos/permissive/515598112/2_Verilog_Language/05_More_Verilog_Features/06_Generate_for-loop_100_bit_binary_adder_2.v:55: Duplicate declaration of module: \'full_add1\'\nmodule full_add1 (\n       ^~~~~~~~~\n                 data/full_repos/permissive/515598112/2_Verilog_Language/05_More_Verilog_Features/06_Generate_for-loop_100_bit_binary_adder_2.v:23: ... Location of original declaration\nmodule full_add1 (\n       ^~~~~~~~~\n%Error: Exiting due to 2 warning(s)\n'
module top_module( 
    input [99:0] a, b,
    input cin,
    output reg [99:0] cout,
    output reg [99:0] sum
);

    full_add1 my_add [99:0](
        .a(a),
        .b(b),
        .cin({cout[98:0], cin}),
        .cout(cout),
        .sum(sum)
    );
    
endmodule
module top_module( 
    input [99:0] a, b,
    input cin,
    output reg [99:0] cout,
    output reg [99:0] sum
);


    full_add1 my_add [99:0](
        .a(a),
        .b(b),
        .cin({cout[98:0], cin}),
        .cout(cout),
        .sum(sum)
    );
    
endmodule