data/full_repos/permissive/417929780/src/arithmetic/parallel_gf_mult.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/417929780/src/arithmetic/parallel_gf_mult.sv:15: Operator SHIFTL expects 9 bits on the LHS, but LHS\'s VARREF \'byte_in\' generates 8 bits.\n                                                                                          : ... In instance parallel_gf_mult\n    byte_ovf    = byte_in << 1;\n                          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module parallel_gf_mult (
    input   [7:0]   byte_in,
    output  [7:0]   product_out,
    input           factor_sel_in
);

logic [8:0] byte_ovf;
logic [7:0] fac_stage;
logic [7:0] product;


always_comb begin
    byte_ovf    = byte_in << 1;
    fac_stage   = (byte_ovf[8]) ? (byte_ovf[7:0] ^ 8'h1B) : byte_ovf[7:0];
    product     = (factor_sel_in) ? (fac_stage ^ byte_in) : fac_stage;
end

assign product_out  = product;

endmodule
module parallel_gf_mult (
    input   [7:0]   byte_in,
    output  [7:0]   product_out,
    input           factor_sel_in
);


logic [8:0] byte_ovf;
logic [7:0] fac_stage;
logic [7:0] product;


always_comb begin
    byte_ovf    = byte_in << 1;
    fac_stage   = (byte_ovf[8]) ? (byte_ovf[7:0] ^ 8'h1B) : byte_ovf[7:0];
    product     = (factor_sel_in) ? (fac_stage ^ byte_in) : fac_stage;
end

assign product_out  = product;

endmodule