data/full_repos/permissive/418819021/lab-06/test_in.vh
1: b'%Error: data/full_repos/permissive/418819021/lab-06/test_in.vh:5: Cannot find include file: defines.vh\n`include "defines.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/418819021/lab-06,data/full_repos/permissive/418819021/defines.vh\n             data/full_repos/permissive/418819021/lab-06,data/full_repos/permissive/418819021/defines.vh.v\n             data/full_repos/permissive/418819021/lab-06,data/full_repos/permissive/418819021/defines.vh.sv\n             defines.vh\n             defines.vh.v\n             defines.vh.sv\n             obj_dir/defines.vh\n             obj_dir/defines.vh.v\n             obj_dir/defines.vh.sv\n%Error: data/full_repos/permissive/418819021/lab-06/test_in.vh:12: Define or directive not defined: \'`STAGE_IF\'\n            `STAGE_IF :\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_in.vh:12: syntax error, unexpected \':\', expecting endcase\n            `STAGE_IF :\n                      ^\n%Error: data/full_repos/permissive/418819021/lab-06/test_in.vh:14: Define or directive not defined: \'`STAGE_ID\'\n            `STAGE_ID :\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_in.vh:15: Define or directive not defined: \'`TYPE_IN\'\n            if (!(uut.control.opcode_type === `TYPE_IN)) begin\n                                              ^~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_in.vh:20: Define or directive not defined: \'`TYPE_IN\'\n                    `TYPE_IN,\n                    ^~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_in.vh:20: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                    `TYPE_IN,\n                            ^\n%Error: data/full_repos/permissive/418819021/lab-06/test_in.vh:29: syntax error, unexpected end\n            end else if (!(uut.control.opcode_imd === io_addr)) begin\n            ^~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_in.vh:36: syntax error, unexpected end\n            end else if(!(uut.control.opcode_group[`GROUP_IO_READ])) begin\n            ^~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_in.vh:36: Define or directive not defined: \'`GROUP_IO_READ\'\n            end else if(!(uut.control.opcode_group[`GROUP_IO_READ])) begin\n                                                   ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_in.vh:41: syntax error, unexpected end\n            end else if (!(uut.control.signals[`CONTROL_IO_READ])) begin\n            ^~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_in.vh:41: Define or directive not defined: \'`CONTROL_IO_READ\'\n            end else if (!(uut.control.signals[`CONTROL_IO_READ])) begin\n                                               ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_in.vh:46: syntax error, unexpected end\n            end else if (!(uut.control.bus_int.bus_addr === io_addr)) begin\n            ^~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_in.vh:53: syntax error, unexpected end\n            end else begin\n            ^~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_in.vh:56: syntax error, unexpected end\n            end\n            ^~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_in.vh:57: Define or directive not defined: \'`STAGE_EX\'\n            `STAGE_EX  :\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_in.vh:59: Define or directive not defined: \'`STAGE_MEM\'\n            `STAGE_MEM :\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_in.vh:61: Define or directive not defined: \'`STAGE_WB\'\n            `STAGE_WB  :\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_in.vh:62: Define or directive not defined: \'`CONTROL_REG_RD_WRITE\'\n            if (!(uut.control.signals[`CONTROL_REG_RD_WRITE])) begin\n                                      ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_in.vh:67: syntax error, unexpected end\n            end else if (!(uut.control.writeback_value === uut.control.bus_data)) begin\n            ^~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_in.vh:74: syntax error, unexpected end\n            end else begin\n            ^~~\n%Error: data/full_repos/permissive/418819021/lab-06/test_in.vh:77: syntax error, unexpected end\n            end\n            ^~~\n%Error: Cannot continue\n'
function TEST_IN;
    input integer io_addr;
    input integer rd_addr;

    begin
        case (uut.pipeline_stage)
            `STAGE_IF :
            TEST_IN = 1'b1;
            `STAGE_ID :
            if (!(uut.control.opcode_type === `TYPE_IN)) begin
                TEST_IN = 1'bx;
                $display("IN R%2d, %d - ID: FAILED, check opcode_type: %d vs %d",
                    rd_addr,
                    io_addr,
                    `TYPE_IN,
                    uut.control.opcode_type);
            end else if (!(uut.control.opcode_rd === rd_addr)) begin
                TEST_IN = 1'bx;
                $display("IN R%2d, %d - ID: FAILED, check opcode_rd: %d vs %d",
                    rd_addr,
                    io_addr,
                    rd_addr,
                    uut.control.opcode_rd);
            end else if (!(uut.control.opcode_imd === io_addr)) begin
                TEST_IN = 1'bx;
                $display("IN R%2d, %d - ID: FAILED, check opcode_imd: %d vs %d",
                    rd_addr,
                    io_addr,
                    io_addr,
                    uut.control.opcode_imd);
            end else if(!(uut.control.opcode_group[`GROUP_IO_READ])) begin
                TEST_IN = 1'bx;
                $display("IN R%2d, %d - ID: FAILED - IN instruction should be in GROUP_IO_READ",
                    rd_addr,
                    io_addr);
            end else if (!(uut.control.signals[`CONTROL_IO_READ])) begin
                TEST_IN = 1'bx;
                $display("IN R%2d, %d - ID: FAILED, signal CONTROL_IO_READ should be active for IN instruction",
                    rd_addr,
                    io_addr);
            end else if (!(uut.control.bus_int.bus_addr === io_addr)) begin
                TEST_IN = 1'bx;
                $display("IN R%2d, %d - ID: FAILED, check bus_addr in bus_interface_unit.v: %d vs %d",
                    rd_addr,
                    io_addr,
                    io_addr,
                    uut.control.bus_int.bus_addr);
            end else begin
                TEST_IN = 1'b1;
                $display("IN R%2d, %d - ID: OK", rd_addr, io_addr);
            end
            `STAGE_EX  :
            TEST_IN = 1'b1;
            `STAGE_MEM :
            TEST_IN = 1'b1;
            `STAGE_WB  :
            if (!(uut.control.signals[`CONTROL_REG_RD_WRITE])) begin
                TEST_IN = 1'bx;
                $display("IN R%2d, %d - WB: FAILED, signal CONTROL_REG_RD_WRITE should be active for IN instruction",
                    rd_addr,
                    io_addr);
            end else if (!(uut.control.writeback_value === uut.control.bus_data)) begin
                TEST_IN = 1'bx;
                $display("IN R%2d, %d - WB: FAILED, check writeback_value : %d vs %d",
                    rd_addr,
                    io_addr,
                    uut.control.bus_data,
                    uut.control.writeback_value);
            end else begin
                TEST_IN = 1'b1;
                $display("IN R%2d, %d - WB: OK", rd_addr, io_addr);
            end
        endcase
    end

endfunction
function TEST_IN;

    input integer io_addr;
    input integer rd_addr;

    begin
        case (uut.pipeline_stage)
            `STAGE_IF :
            TEST_IN = 1'b1;
            `STAGE_ID :
            if (!(uut.control.opcode_type === `TYPE_IN)) begin
                TEST_IN = 1'bx;
                $display("IN R%2d, %d - ID: FAILED, check opcode_type: %d vs %d",
                    rd_addr,
                    io_addr,
                    `TYPE_IN,
                    uut.control.opcode_type);
            end else if (!(uut.control.opcode_rd === rd_addr)) begin
                TEST_IN = 1'bx;
                $display("IN R%2d, %d - ID: FAILED, check opcode_rd: %d vs %d",
                    rd_addr,
                    io_addr,
                    rd_addr,
                    uut.control.opcode_rd);
            end else if (!(uut.control.opcode_imd === io_addr)) begin
                TEST_IN = 1'bx;
                $display("IN R%2d, %d - ID: FAILED, check opcode_imd: %d vs %d",
                    rd_addr,
                    io_addr,
                    io_addr,
                    uut.control.opcode_imd);
            end else if(!(uut.control.opcode_group[`GROUP_IO_READ])) begin
                TEST_IN = 1'bx;
                $display("IN R%2d, %d - ID: FAILED - IN instruction should be in GROUP_IO_READ",
                    rd_addr,
                    io_addr);
            end else if (!(uut.control.signals[`CONTROL_IO_READ])) begin
                TEST_IN = 1'bx;
                $display("IN R%2d, %d - ID: FAILED, signal CONTROL_IO_READ should be active for IN instruction",
                    rd_addr,
                    io_addr);
            end else if (!(uut.control.bus_int.bus_addr === io_addr)) begin
                TEST_IN = 1'bx;
                $display("IN R%2d, %d - ID: FAILED, check bus_addr in bus_interface_unit.v: %d vs %d",
                    rd_addr,
                    io_addr,
                    io_addr,
                    uut.control.bus_int.bus_addr);
            end else begin
                TEST_IN = 1'b1;
                $display("IN R%2d, %d - ID: OK", rd_addr, io_addr);
            end
            `STAGE_EX  :
            TEST_IN = 1'b1;
            `STAGE_MEM :
            TEST_IN = 1'b1;
            `STAGE_WB  :
            if (!(uut.control.signals[`CONTROL_REG_RD_WRITE])) begin
                TEST_IN = 1'bx;
                $display("IN R%2d, %d - WB: FAILED, signal CONTROL_REG_RD_WRITE should be active for IN instruction",
                    rd_addr,
                    io_addr);
            end else if (!(uut.control.writeback_value === uut.control.bus_data)) begin
                TEST_IN = 1'bx;
                $display("IN R%2d, %d - WB: FAILED, check writeback_value : %d vs %d",
                    rd_addr,
                    io_addr,
                    uut.control.bus_data,
                    uut.control.writeback_value);
            end else begin
                TEST_IN = 1'b1;
                $display("IN R%2d, %d - WB: OK", rd_addr, io_addr);
            end
        endcase
    end

endfunction