data/full_repos/permissive/461141714/src/Pipelined CPU with Data Forwarding/stage_IF.v
1: b'%Error: Cannot find file containing module: CPU\n        ... Looked in:\n             data/full_repos/permissive/461141714/src/Pipelined/CPU\n             data/full_repos/permissive/461141714/src/Pipelined/CPU.v\n             data/full_repos/permissive/461141714/src/Pipelined/CPU.sv\n             CPU\n             CPU.v\n             CPU.sv\n             obj_dir/CPU\n             obj_dir/CPU.v\n             obj_dir/CPU.sv\n%Error: Cannot find file containing module: with\n%Error: Cannot find file containing module: Data\n%Error: Cannot find file containing module: Forwarding,data/full_repos/permissive/461141714\n%Error: Cannot find file containing module: data/full_repos/permissive/461141714/src/Pipelined\n%Error: Cannot find file containing module: Forwarding/stage_IF.v\n%Error: Exiting due to 6 error(s)\n'
module STAGE_IF(
        input clk,
        input reset_n,
        

        input [`WORD_SIZE-1:0] instruction,
        output [`WORD_SIZE-1:0] PC_now,
        output [`WORD_SIZE-1:0] nextPC,
        

        input forcePC,
        input [`WORD_SIZE-1:0] forcePCdata,
        input [`WORD_SIZE-1:0] EX_PC,
        output reg i_readM,
        output reg i_writeM
    );
    
    reg [`WORD_SIZE-1:0] PC;
    assign PC_now = forcePC === 1 ? forcePCdata : PC;
    

    PC_PREDICTOR pc_predictor(
        .clk(clk),
        .reset_n(reset_n),
        .PC(PC_now),
        .instruction(instruction),
        .nextPC(nextPC),
        .forcePC(forcePC),
        .forcePCdata(forcePCdata),
        .EX_PC(EX_PC)
    );
    

    initial PC = `WORD_SIZE'b0;
    always @(posedge clk) begin
        if(!reset_n) PC = `WORD_SIZE'b0;
        else PC = nextPC; 
    end
    

    initial begin
        i_readM = 1;
        i_writeM = 0;
    end
    
    
endmodule
module STAGE_IF(
        input clk,
        input reset_n,
        

        input [`WORD_SIZE-1:0] instruction,
        output [`WORD_SIZE-1:0] PC_now,
        output [`WORD_SIZE-1:0] nextPC,
        

        input forcePC,
        input [`WORD_SIZE-1:0] forcePCdata,
        input [`WORD_SIZE-1:0] EX_PC,
        output reg i_readM,
        output reg i_writeM
    );

    
    reg [`WORD_SIZE-1:0] PC;
    assign PC_now = forcePC === 1 ? forcePCdata : PC;
    

    PC_PREDICTOR pc_predictor(
        .clk(clk),
        .reset_n(reset_n),
        .PC(PC_now),
        .instruction(instruction),
        .nextPC(nextPC),
        .forcePC(forcePC),
        .forcePCdata(forcePCdata),
        .EX_PC(EX_PC)
    );
    

    initial PC = `WORD_SIZE'b0;
    always @(posedge clk) begin
        if(!reset_n) PC = `WORD_SIZE'b0;
        else PC = nextPC; 
    end
    

    initial begin
        i_readM = 1;
        i_writeM = 0;
    end
    
    
endmodule