data/full_repos/permissive/461000256/new/CORE.v
1: b"%Error: data/full_repos/permissive/461000256/new/CORE.v:16: Cannot find file containing module: 'PC'\n PC #(.RFW(RFW),.IMW(IMW),.DW(DW),.IW(IW))  program_counter  (.clk(clk),.start(start),.in(pc_in),.out_r(pc_out));\n ^~\n        ... Looked in:\n             data/full_repos/permissive/461000256/new,data/full_repos/permissive/461000256/PC\n             data/full_repos/permissive/461000256/new,data/full_repos/permissive/461000256/PC.v\n             data/full_repos/permissive/461000256/new,data/full_repos/permissive/461000256/PC.sv\n             PC\n             PC.v\n             PC.sv\n             obj_dir/PC\n             obj_dir/PC.v\n             obj_dir/PC.sv\n%Error: data/full_repos/permissive/461000256/new/CORE.v:17: Cannot find file containing module: 'IM'\n IM #(.RFW(RFW),.IMW(IMW),.DW(DW),.IW(IW))  instruction_memory  (.address(pc_out),.out(im_inst));\n ^~\n%Error: data/full_repos/permissive/461000256/new/CORE.v:18: Cannot find file containing module: 'IF_ID'\n IF_ID #(.RFW(RFW),.IMW(IMW),.DW(DW),.IW(IW)) if_id_buffer  (.clk(clk),.in(im_inst),.out(if_id_inst));\n ^~~~~\n%Error: data/full_repos/permissive/461000256/new/CORE.v:19: Cannot find file containing module: 'ID'\n ID #(.RFW(RFW),.IMW(IMW),.DW(DW),.IW(IW))  instruction_decode (.inst(if_id_inst),.addrA(addrA),.addrB(addrB),.imm(imm));\n ^~\n%Error: data/full_repos/permissive/461000256/new/CORE.v:20: Cannot find file containing module: 'RF'\n RF #(.RFW(RFW),.IMW(IMW),.DW(DW),.IW(IW))  register_file  (.clk(clk),.reg1(addrA),.reg2(addrB),.reg1data(r1),.reg2data(r2));\n ^~\n%Error: data/full_repos/permissive/461000256/new/CORE.v:21: Cannot find file containing module: 'ID_EXE'\n ID_EXE #(.RFW(RFW),.IMW(IMW),.DW(DW),.IW(IW)) id_exe_buffer  (.clk(clk),.in_inst(if_id_inst),.out_inst(id_exe_inst), \n ^~~~~~\n%Error: Exiting due to 6 error(s)\n"
module CORE
#(	parameter RFW = 5,
	parameter IMW = 4,
	parameter DW = 32,
	parameter IW = 32)
(	input wire clk,
	input wire start);

	reg [IMW-1:0] pc_in;
	wire [IMW-1:0] pc_out;
	wire [IW-1:0] im_inst, if_id_inst, id_exe_inst;
	wire [RFW-1:0] addrA,addrB;
	wire [DW-1:0] imm, r1, r2, r1_o, r2_o;

	PC #(.RFW(RFW),.IMW(IMW),.DW(DW),.IW(IW)) 	program_counter 	(.clk(clk),.start(start),.in(pc_in),.out_r(pc_out));
	IM #(.RFW(RFW),.IMW(IMW),.DW(DW),.IW(IW)) 	instruction_memory 	(.address(pc_out),.out(im_inst));
	IF_ID #(.RFW(RFW),.IMW(IMW),.DW(DW),.IW(IW)) if_id_buffer		(.clk(clk),.in(im_inst),.out(if_id_inst));
	ID #(.RFW(RFW),.IMW(IMW),.DW(DW),.IW(IW)) 	instruction_decode	(.inst(if_id_inst),.addrA(addrA),.addrB(addrB),.imm(imm));
	RF #(.RFW(RFW),.IMW(IMW),.DW(DW),.IW(IW)) 	register_file		(.clk(clk),.reg1(addrA),.reg2(addrB),.reg1data(r1),.reg2data(r2));
	ID_EXE #(.RFW(RFW),.IMW(IMW),.DW(DW),.IW(IW)) id_exe_buffer		(.clk(clk),.in_inst(if_id_inst),.out_inst(id_exe_inst), 
																	 .r1(r1), .r2(r2), .r1_o(r1_o), .r2_o(r2_o));



	always @(posedge start) begin
		pc_in = 0;
	end

endmodule
module CORE
#(	parameter RFW = 5,
	parameter IMW = 4,
	parameter DW = 32,
	parameter IW = 32)
(	input wire clk,
	input wire start);


	reg [IMW-1:0] pc_in;
	wire [IMW-1:0] pc_out;
	wire [IW-1:0] im_inst, if_id_inst, id_exe_inst;
	wire [RFW-1:0] addrA,addrB;
	wire [DW-1:0] imm, r1, r2, r1_o, r2_o;

	PC #(.RFW(RFW),.IMW(IMW),.DW(DW),.IW(IW)) 	program_counter 	(.clk(clk),.start(start),.in(pc_in),.out_r(pc_out));
	IM #(.RFW(RFW),.IMW(IMW),.DW(DW),.IW(IW)) 	instruction_memory 	(.address(pc_out),.out(im_inst));
	IF_ID #(.RFW(RFW),.IMW(IMW),.DW(DW),.IW(IW)) if_id_buffer		(.clk(clk),.in(im_inst),.out(if_id_inst));
	ID #(.RFW(RFW),.IMW(IMW),.DW(DW),.IW(IW)) 	instruction_decode	(.inst(if_id_inst),.addrA(addrA),.addrB(addrB),.imm(imm));
	RF #(.RFW(RFW),.IMW(IMW),.DW(DW),.IW(IW)) 	register_file		(.clk(clk),.reg1(addrA),.reg2(addrB),.reg1data(r1),.reg2data(r2));
	ID_EXE #(.RFW(RFW),.IMW(IMW),.DW(DW),.IW(IW)) id_exe_buffer		(.clk(clk),.in_inst(if_id_inst),.out_inst(id_exe_inst), 
																	 .r1(r1), .r2(r2), .r1_o(r1_o), .r2_o(r2_o));



	always @(posedge start) begin
		pc_in = 0;
	end

endmodule