data/full_repos/permissive/492462267/inst_rom.v
1: b'%Error: data/full_repos/permissive/492462267/inst_rom.v:1: Cannot find include file: define.vh\n`include "define.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh.v\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh.sv\n             define.vh\n             define.vh.v\n             define.vh.sv\n             obj_dir/define.vh\n             obj_dir/define.vh.v\n             obj_dir/define.vh.sv\n%Error: data/full_repos/permissive/492462267/inst_rom.v:11: Define or directive not defined: \'`InstAddrBus\'\n    input   wire[`InstAddrBus]  addr,\n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/inst_rom.v:11: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input   wire[`InstAddrBus]  addr,\n                             ^\n%Error: data/full_repos/permissive/492462267/inst_rom.v:12: Define or directive not defined: \'`InstBus\'\n    output  reg[`InstBus]       inst\n                ^~~~~~~~\n%Error: data/full_repos/permissive/492462267/inst_rom.v:16: Define or directive not defined: \'`InstBus\'\nreg[`InstBus]   inst_mem[0:`InstMemNum-1];\n    ^~~~~~~~\n%Error: data/full_repos/permissive/492462267/inst_rom.v:16: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nreg[`InstBus]   inst_mem[0:`InstMemNum-1];\n            ^\n%Error: data/full_repos/permissive/492462267/inst_rom.v:16: Define or directive not defined: \'`InstMemNum\'\nreg[`InstBus]   inst_mem[0:`InstMemNum-1];\n                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/inst_rom.v:25: Define or directive not defined: \'`ZeroWord\'\n        inst = `ZeroWord;\n               ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/inst_rom.v:27: Define or directive not defined: \'`InstBusUsed\'\n        inst = inst_mem[ addr[`InstBusUsed+1 : 2] ];\n                              ^~~~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n'
module inst_rom(
    input   wire                ce,
    input   wire[`InstAddrBus]  addr,
    output  reg[`InstBus]       inst
);


reg[`InstBus]   inst_mem[0:`InstMemNum-1];

initial begin

    $readmemh("D:/study/verilog/MartianMIPS/code/inst_rom.data",inst_mem);
end

always @(*) begin
    if(~ce) begin
        inst = `ZeroWord;
    end else begin
        inst = inst_mem[ addr[`InstBusUsed+1 : 2] ];
    end
end

endmodule
module inst_rom(
    input   wire                ce,
    input   wire[`InstAddrBus]  addr,
    output  reg[`InstBus]       inst
);



reg[`InstBus]   inst_mem[0:`InstMemNum-1];

initial begin

    $readmemh("D:/study/verilog/MartianMIPS/code/inst_rom.data",inst_mem);
end

always @(*) begin
    if(~ce) begin
        inst = `ZeroWord;
    end else begin
        inst = inst_mem[ addr[`InstBusUsed+1 : 2] ];
    end
end

endmodule