data/full_repos/permissive/42434302/ivltests/vector.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/vector.v:36: Unsupported: Ignoring delay on this delayed statement.\n #102; $finish;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/vector.v:39: Unsupported: Ignoring delay on this delayed statement.\ninitial #1 begin\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/vector.v:46: Unsupported: Ignoring delay on this delayed statement.\nalways #10 begin\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/42434302/ivltests/vector.v:26: Little bit endian vector: MSB < LSB of bit range: 0:4\nreg [0:4] foo04;  \n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/42434302/ivltests/vector.v:32: Little bit endian vector: MSB < LSB of bit range: 1:5\nreg [1:5] foo15;  \n    ^\n%Error: Exiting due to 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module  test;

reg [4:0] foo40;

reg	[0:4] foo04;


reg	[5:1] foo51;


reg	[1:5] foo15;


initial begin
	#102; $finish;
end

initial #1 begin
	foo40 = 0;
	foo04 = 0;
	foo51 = 0;
	foo15 = 0;
end

always #10 begin
	foo40 <= foo40 + 1;
	foo04 <= foo04 + 1;
	foo51 <= foo51 + 1;
	foo15 <= foo15 + 1;
end

always @(foo40) begin
	$write("foo40=%8d\n", foo40);
end

always @(foo04) begin
	$write("               foo04=%8d\n", foo04);
end

always @(foo51) begin
	$write("                              foo51=%8d\n", foo51);
end

always @(foo15) begin
	$write("                                             foo15=%8d\n", foo15);
end

endmodule
module  test;


reg [4:0] foo40;

reg	[0:4] foo04;


reg	[5:1] foo51;


reg	[1:5] foo15;


initial begin
	#102; $finish;
end

initial #1 begin
	foo40 = 0;
	foo04 = 0;
	foo51 = 0;
	foo15 = 0;
end

always #10 begin
	foo40 <= foo40 + 1;
	foo04 <= foo04 + 1;
	foo51 <= foo51 + 1;
	foo15 <= foo15 + 1;
end

always @(foo40) begin
	$write("foo40=%8d\n", foo40);
end

always @(foo04) begin
	$write("               foo04=%8d\n", foo04);
end

always @(foo51) begin
	$write("                              foo51=%8d\n", foo51);
end

always @(foo15) begin
	$write("                                             foo15=%8d\n", foo15);
end

endmodule