data/full_repos/permissive/460328193/ipa_proj_pipe/execute_tb.v
1: b'%Error: data/full_repos/permissive/460328193/ipa_proj_pipe/execute_tb.v:1: Cannot find include file: execute.v\n`include "execute.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/460328193/ipa_proj_pipe,data/full_repos/permissive/460328193/execute.v\n             data/full_repos/permissive/460328193/ipa_proj_pipe,data/full_repos/permissive/460328193/execute.v.v\n             data/full_repos/permissive/460328193/ipa_proj_pipe,data/full_repos/permissive/460328193/execute.v.sv\n             execute.v\n             execute.v.v\n             execute.v.sv\n             obj_dir/execute.v\n             obj_dir/execute.v.v\n             obj_dir/execute.v.sv\n%Error: data/full_repos/permissive/460328193/ipa_proj_pipe/execute_tb.v:18: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("execute.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/460328193/ipa_proj_pipe/execute_tb.v:19: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0,icode,ifun,valC,valA,valB,valE,Cnd,clock,new_cc,set_cc,cc);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/460328193/ipa_proj_pipe/execute_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/460328193/ipa_proj_pipe/execute_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n'
module tb();

reg [3:0]icode,ifun;
reg [63:0]valC,valA,valB;
wire [63:0]valE;
wire Cnd;
reg clock;
wire [2:0]new_cc;
wire set_cc;
reg [2:0]cc;
integer j;

execute DUT(icode,ifun,valC,valA,valB,valE,Cnd,clock,new_cc,set_cc,cc);
initial begin

	$dumpfile("execute.vcd");
    $dumpvars(0,icode,ifun,valC,valA,valB,valE,Cnd,clock,new_cc,set_cc,cc);
	icode<=4'h6;
	ifun<=4'h1;
	valA<='h123;
	valB<='h122;
	valC<='h1;
	cc<=3'b010;
	for(j=0;j<4;j++) begin 
	clock=1;
	#10;
	clock=0;
	#10;
	end
end



endmodule
module tb();


reg [3:0]icode,ifun;
reg [63:0]valC,valA,valB;
wire [63:0]valE;
wire Cnd;
reg clock;
wire [2:0]new_cc;
wire set_cc;
reg [2:0]cc;
integer j;

execute DUT(icode,ifun,valC,valA,valB,valE,Cnd,clock,new_cc,set_cc,cc);
initial begin

	$dumpfile("execute.vcd");
    $dumpvars(0,icode,ifun,valC,valA,valB,valE,Cnd,clock,new_cc,set_cc,cc);
	icode<=4'h6;
	ifun<=4'h1;
	valA<='h123;
	valB<='h122;
	valC<='h1;
	cc<=3'b010;
	for(j=0;j<4;j++) begin 
	clock=1;
	#10;
	clock=0;
	#10;
	end
end



endmodule