data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/rtl/libp/af4_ipoh_vote4.v
data/verilator_xmls/814f1738-68df-466a-9775-f7f04bd71d8a.xml
module af4_ipoh_vote4
    (
     req,
     prior,
     win,
     winval
     );



input   [3:0]   req;
input   [1:0]   prior;
output  [1:0]   win;
output          winval;



reg     [1:0]   win;
wire            winval;






assign          winval = |req[3:0];

always @ (req[3:0] or prior[1:0])
    begin
    casex ({req[3:0],prior[1:0]})
        {4'bxxx1,2'h0}: win = 2'h0;
        {4'bxx10,2'h0}: win = 2'h1;
        {4'bx100,2'h0}: win = 2'h2;
        {4'b1000,2'h0}: win = 2'h3;

        {4'b0001,2'h1}: win = 2'h0;
        {4'bxx1x,2'h1}: win = 2'h1;
        {4'bx10x,2'h1}: win = 2'h2;
        {4'b100x,2'h1}: win = 2'h3;

        {4'b00x1,2'h2}: win = 2'h0;
        {4'b0010,2'h2}: win = 2'h1;
        {4'bx1xx,2'h2}: win = 2'h2;
        {4'b10xx,2'h2}: win = 2'h3;
        
        {4'b0xx1,2'h3}: win = 2'h0;
        {4'b0x10,2'h3}: win = 2'h1;
        {4'b0100,2'h3}: win = 2'h2;
        {4'b1xxx,2'h3}: win = 2'h3;

        {4'b0000,2'hx}: win = 2'h0;
    endcase
    end
endmodule
module af4_ipoh_vote4
    (
     req,
     prior,
     win,
     winval
     );




input   [3:0]   req;
input   [1:0]   prior;
output  [1:0]   win;
output          winval;



reg     [1:0]   win;
wire            winval;






assign          winval = |req[3:0];

always @ (req[3:0] or prior[1:0])
    begin
    casex ({req[3:0],prior[1:0]})
        {4'bxxx1,2'h0}: win = 2'h0;
        {4'bxx10,2'h0}: win = 2'h1;
        {4'bx100,2'h0}: win = 2'h2;
        {4'b1000,2'h0}: win = 2'h3;

        {4'b0001,2'h1}: win = 2'h0;
        {4'bxx1x,2'h1}: win = 2'h1;
        {4'bx10x,2'h1}: win = 2'h2;
        {4'b100x,2'h1}: win = 2'h3;

        {4'b00x1,2'h2}: win = 2'h0;
        {4'b0010,2'h2}: win = 2'h1;
        {4'bx1xx,2'h2}: win = 2'h2;
        {4'b10xx,2'h2}: win = 2'h3;
        
        {4'b0xx1,2'h3}: win = 2'h0;
        {4'b0x10,2'h3}: win = 2'h1;
        {4'b0100,2'h3}: win = 2'h2;
        {4'b1xxx,2'h3}: win = 2'h3;

        {4'b0000,2'hx}: win = 2'h0;
    endcase
    end
endmodule