data/full_repos/permissive/423547971/FPGA Projects/FIFO/debounce_explicit.v
1: b'%Error: Cannot find file containing module: Projects/FIFO,data/full_repos/permissive/423547971\n        ... Looked in:\n             data/full_repos/permissive/423547971/FPGA/Projects/FIFO,data/full_repos/permissive/423547971\n             data/full_repos/permissive/423547971/FPGA/Projects/FIFO,data/full_repos/permissive/423547971.v\n             data/full_repos/permissive/423547971/FPGA/Projects/FIFO,data/full_repos/permissive/423547971.sv\n             Projects/FIFO,data/full_repos/permissive/423547971\n             Projects/FIFO,data/full_repos/permissive/423547971.v\n             Projects/FIFO,data/full_repos/permissive/423547971.sv\n             obj_dir/Projects/FIFO,data/full_repos/permissive/423547971\n             obj_dir/Projects/FIFO,data/full_repos/permissive/423547971.v\n             obj_dir/Projects/FIFO,data/full_repos/permissive/423547971.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/FPGA\n%Error: Cannot find file containing module: Projects/FIFO/debounce_explicit.v\n%Error: Exiting due to 3 error(s)\n'
module debounce_explicit(
    input clk_100MHz,
    input reset,
    input btn,
    output reg db_level,
    output reg db_tick
    );
    

    parameter [1:0] zero  = 2'b00,
                    wait0 = 2'b01,
                    one   = 2'b10,
                    wait1 = 2'b11;
    


    parameter N = 22;
    

    reg [1:0] state_reg, next_state;
    reg [N-1:0] q_reg;
    wire [N-1:0] q_next;
    wire q_zero;
    reg q_load, q_dec;
    


    always @(posedge clk_100MHz or posedge reset) 
        if(reset) begin
            state_reg <= zero;
            q_reg <= 0;
        end
        else begin
            state_reg <= next_state;
            q_reg <= q_next;
        end
        

    assign q_next = (q_load) ? {N{1'b1}} :
                    (q_dec) ? q_reg - 1  :
                     q_reg;
    

    assign q_zero = (q_next == 0);
    

    always @* begin
        next_state = state_reg;
        q_load = 1'b0;
        q_dec = 1'b0;
        db_tick = 1'b0;
        
        case(state_reg)
            zero    : begin
                        db_level = 1'b0;
                        if(btn) begin
                            next_state = wait1;
                            q_load = 1'b1;
                        end
            end
            
            wait1   : begin
                        db_level = 1'b0;
                        if(btn) begin
                            q_dec = 1'b1;
                            if(q_zero) begin
                                next_state = one;
                                db_tick = 1'b1;
                            end
                        end
                        else
                            next_state = zero;
            end
            
            one     : begin
                        db_level = 1'b1;
                        if(~btn) begin
                            q_dec = 1'b1;
                            if(q_zero)
                                next_state = zero;
                        end
                        else
                            next_state = one;
            end
            
            default : next_state = zero;
        endcase
    end
        
endmodule
module debounce_explicit(
    input clk_100MHz,
    input reset,
    input btn,
    output reg db_level,
    output reg db_tick
    );

    

    parameter [1:0] zero  = 2'b00,
                    wait0 = 2'b01,
                    one   = 2'b10,
                    wait1 = 2'b11;
    


    parameter N = 22;
    

    reg [1:0] state_reg, next_state;
    reg [N-1:0] q_reg;
    wire [N-1:0] q_next;
    wire q_zero;
    reg q_load, q_dec;
    


    always @(posedge clk_100MHz or posedge reset) 
        if(reset) begin
            state_reg <= zero;
            q_reg <= 0;
        end
        else begin
            state_reg <= next_state;
            q_reg <= q_next;
        end
        

    assign q_next = (q_load) ? {N{1'b1}} :
                    (q_dec) ? q_reg - 1  :
                     q_reg;
    

    assign q_zero = (q_next == 0);
    

    always @* begin
        next_state = state_reg;
        q_load = 1'b0;
        q_dec = 1'b0;
        db_tick = 1'b0;
        
        case(state_reg)
            zero    : begin
                        db_level = 1'b0;
                        if(btn) begin
                            next_state = wait1;
                            q_load = 1'b1;
                        end
            end
            
            wait1   : begin
                        db_level = 1'b0;
                        if(btn) begin
                            q_dec = 1'b1;
                            if(q_zero) begin
                                next_state = one;
                                db_tick = 1'b1;
                            end
                        end
                        else
                            next_state = zero;
            end
            
            one     : begin
                        db_level = 1'b1;
                        if(~btn) begin
                            q_dec = 1'b1;
                            if(q_zero)
                                next_state = zero;
                        end
                        else
                            next_state = one;
            end
            
            default : next_state = zero;
        endcase
    end
        
endmodule