data/full_repos/permissive/510160664/Adders/src/cs_adder.v
data/verilator_xmls/366819ef-6dc7-4989-842a-1cec9e804764.xml
module cs_adder
#(
					parameter WIDTH = 32
)
(
					input 	[WIDTH-1:0] Number1_i,
					input 	[WIDTH-1:0] Number2_i,
					input 					Carry_i,

					output  	[WIDTH-1:0] Result_o,
					output  		  			Carry_o
);


wire [WIDTH-2:0] c_o;


generate
	genvar j;
	
	for (j = 0; j < WIDTH; j = j + 1) begin	:csa

		if (j == 0) begin
			csa_submodule csa
			(
						.A_i(Number1_i[j]),
						.B_i(Number2_i[j]),
						.C_i(Carry_i),

						.S_o(Result_o[j]),
						.C_o(c_o[j])
			);

		end else if (j == WIDTH - 1) begin
			csa_submodule csa
			(
						.A_i(Number1_i[j]),
						.B_i(Number2_i[j]),
						.C_i(c_o[j-1]),

						.S_o(Result_o[j]),
						.C_o(Carry_o)
			);

		end else begin
			csa_submodule csa
			(
						.A_i(Number1_i[j]),
						.B_i(Number2_i[j]),
						.C_i(c_o[j-1]),

						.S_o(Result_o[j]),
						.C_o(c_o[j])
			);
		end
	end
endgenerate

endmodule
module cs_adder
#(
					parameter WIDTH = 32
)
(
					input 	[WIDTH-1:0] Number1_i,
					input 	[WIDTH-1:0] Number2_i,
					input 					Carry_i,

					output  	[WIDTH-1:0] Result_o,
					output  		  			Carry_o
);



wire [WIDTH-2:0] c_o;


generate
	genvar j;
	
	for (j = 0; j < WIDTH; j = j + 1) begin	:csa

		if (j == 0) begin
			csa_submodule csa
			(
						.A_i(Number1_i[j]),
						.B_i(Number2_i[j]),
						.C_i(Carry_i),

						.S_o(Result_o[j]),
						.C_o(c_o[j])
			);

		end else if (j == WIDTH - 1) begin
			csa_submodule csa
			(
						.A_i(Number1_i[j]),
						.B_i(Number2_i[j]),
						.C_i(c_o[j-1]),

						.S_o(Result_o[j]),
						.C_o(Carry_o)
			);

		end else begin
			csa_submodule csa
			(
						.A_i(Number1_i[j]),
						.B_i(Number2_i[j]),
						.C_i(c_o[j-1]),

						.S_o(Result_o[j]),
						.C_o(c_o[j])
			);
		end
	end
endgenerate

endmodule