data/full_repos/permissive/425928416/verilog/rtl/jacaranda-8/decoder.v
data/verilator_xmls/af6a054b-7088-4b21-9e1d-d25eb7e91412.xml
module decoder(instr, opcode, rs_a, rd_a, imm);
    input [7:0] instr;
    output [3:0] opcode;
    output [1:0] rs_a, rd_a;
    output [3:0] imm;

    assign opcode = instr[7:4];
    assign rd_a = instr[3:2];
    assign rs_a = instr[1:0];
    assign imm = instr[3:0];
endmodule
module decoder(instr, opcode, rs_a, rd_a, imm);

    input [7:0] instr;
    output [3:0] opcode;
    output [1:0] rs_a, rd_a;
    output [3:0] imm;

    assign opcode = instr[7:4];
    assign rd_a = instr[3:2];
    assign rs_a = instr[1:0];
    assign imm = instr[3:0];
endmodule