data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v
1: b'%Error: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:69: Cannot find include file: DFFRAM/DFFRAM.v\n`include "DFFRAM/DFFRAM.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/492704601/verilog/dv/user_sspi,data/full_repos/permissive/492704601/DFFRAM/DFFRAM.v\n             data/full_repos/permissive/492704601/verilog/dv/user_sspi,data/full_repos/permissive/492704601/DFFRAM/DFFRAM.v.v\n             data/full_repos/permissive/492704601/verilog/dv/user_sspi,data/full_repos/permissive/492704601/DFFRAM/DFFRAM.v.sv\n             DFFRAM/DFFRAM.v\n             DFFRAM/DFFRAM.v.v\n             DFFRAM/DFFRAM.v.sv\n             obj_dir/DFFRAM/DFFRAM.v\n             obj_dir/DFFRAM/DFFRAM.v.v\n             obj_dir/DFFRAM/DFFRAM.v.sv\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:70: Cannot find include file: is62wvs1288.v\n`include "is62wvs1288.v" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:666: Cannot find include file: sspi_task.v\n`include "sspi_task.v" \n         ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n always #12.5 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:133: Unsupported or unknown PLI call: $dumpon\n  $dumpon;\n  ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:135: Unsupported: Ignoring delay on this delayed statement.\n  #200;  \n  ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:136: syntax error, unexpected \'@\'\n         repeat (10) @(posedge clock);\n                     ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:140: Define or directive not defined: \'`ADDR_SPACE_WBHOST\'\n  wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,\'h1);\n                     ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:140: Define or directive not defined: \'`WBHOST_GLBL_CFG\'\n  wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,\'h1);\n                                        ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:140: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n  wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,\'h1);\n                                                        ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:143: Define or directive not defined: \'`ADDR_SPACE_PINMUX\'\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,\'h3C00);\n                                   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:143: Define or directive not defined: \'`PINMUX_GPIO_MULTI_FUNC\'\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,\'h3C00);\n                                                      ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:143: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,\'h3C00);\n                                                                             ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:145: syntax error, unexpected \'@\'\n         repeat (2) @(posedge clock);\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:146: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:150: Define or directive not defined: \'`ADDR_SPACE_PINMUX\'\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h01F);\n                                   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:150: Define or directive not defined: \'`PINMUX_GBL_CFG0\'\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h01F);\n                                                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:150: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,\'h01F);\n                                                                      ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:155: syntax error, unexpected \'@\'\n         repeat (200) @(posedge clock);\n                      ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:156: Define or directive not defined: \'`ADDR_SPACE_WBHOST\'\n                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,\'h1000);  \n                                   ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:156: Define or directive not defined: \'`WBHOST_BANK_SEL\'\n                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,\'h1000);  \n                                                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:156: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,\'h1000);  \n                                                                      ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:386: syntax error, unexpected \'@\'\n  repeat (100) @(posedge clock);\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:408: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:534: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:535: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:542: Unsupported: wait statements\n  wait(wbd_ext_ack_o == 1);\n  ^~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:543: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:544: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:552: syntax error, unexpected \'@\'\n  repeat (2) @(posedge clock);\n             ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:561: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:562: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:569: Unsupported: wait statements\n  wait(wbd_ext_ack_o == 1);\n  ^~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:571: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:572: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:580: syntax error, unexpected \'@\'\n  repeat (2) @(posedge clock);\n             ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:590: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:591: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:598: Unsupported: wait statements\n  wait(wbd_ext_ack_o == 1);\n  ^~~~\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:600: syntax error, unexpected \'@\'\n  repeat (1) @(posedge clock);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:601: Unsupported: Ignoring delay on this delayed statement.\n  #1;\n  ^\n%Error: data/full_repos/permissive/492704601/verilog/dv/user_sspi/user_sspi_tb.v:614: syntax error, unexpected \'@\'\n  repeat (2) @(posedge clock);\n             ^\n%Error: Exiting due to 32 error(s), 10 warning(s)\n'
module user_sspi_tb;
	reg clock;
	reg wb_rst_i;
	reg power1, power2;
	reg power3, power4;

        reg        wbd_ext_cyc_i;
        reg        wbd_ext_stb_i;
        reg [31:0] wbd_ext_adr_i;
        reg        wbd_ext_we_i;
        reg [31:0] wbd_ext_dat_i;
        reg [3:0]  wbd_ext_sel_i;

        wire [31:0] wbd_ext_dat_o;
        wire        wbd_ext_ack_o;
        wire        wbd_ext_err_o;


	wire [37:0] io_oeb;
	wire [37:0] io_out;
	wire [37:0] io_in;


	reg [1:0] spi_chip_no;

	wire gpio;
	wire [37:0] mprj_io;
	wire [7:0] mprj_io_0;
	reg        test_fail;
	reg [31:0] read_data;






	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
                wbd_ext_cyc_i ='h0;
                wbd_ext_stb_i ='h0;
                wbd_ext_adr_i ='h0;
                wbd_ext_we_i  ='h0;
                wbd_ext_dat_i ='h0;
                wbd_ext_sel_i ='h0;
	end

	`ifdef WFDUMP
	   initial begin
	   	$dumpfile("simx.vcd");
	   	$dumpvars(5, user_sspi_tb);
	   end
       `endif

	initial begin
		$dumpon;

		#200;
	        repeat (10) @(posedge clock);
		$display("Monitor: Standalone User Risc Boot Test Started");


		wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);


                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h3C00);

	        repeat (2) @(posedge clock);
		#1;



                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F);


		test_fail = 0;
		sspi_init();
	        repeat (200) @(posedge clock);
                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000);
                $display("############################################");
                $display("   Testing IS62/65WVS1288GALL SSRAM[0] Read/Write Access       ");
                $display("############################################");



                spi_chip_no = 2'b00;
		sspi_dw_read_check(8'h03,24'h0000,32'h03020100);
		sspi_dw_read_check(8'h03,24'h0004,32'h07060504);
		sspi_dw_read_check(8'h03,24'h0008,32'h0b0a0908);
		sspi_dw_read_check(8'h03,24'h000C,32'h0f0e0d0c);
		sspi_dw_read_check(8'h03,24'h0010,32'h13121110);
		sspi_dw_read_check(8'h03,24'h0014,32'h17161514);
		sspi_dw_read_check(8'h03,24'h0018,32'h1B1A1918);
		sspi_dw_read_check(8'h03,24'h001C,32'h1F1E1D1C);

		sspi_dw_read_check(8'h03,24'h0040,32'h43424140);
		sspi_dw_read_check(8'h03,24'h0044,32'h47464544);
		sspi_dw_read_check(8'h03,24'h0048,32'h4B4A4948);
		sspi_dw_read_check(8'h03,24'h004C,32'h4F4E4D4C);

		sspi_dw_read_check(8'h03,24'h00a0,32'ha3a2a1a0);
		sspi_dw_read_check(8'h03,24'h00a4,32'ha7a6a5a4);
		sspi_dw_read_check(8'h03,24'h00a8,32'habaaa9a8);
		sspi_dw_read_check(8'h03,24'h00aC,32'hafaeadac);

		sspi_dw_read_check(8'h03,24'h0200,32'h11111111);
		sspi_dw_read_check(8'h03,24'h0204,32'h22222222);
		sspi_dw_read_check(8'h03,24'h0208,32'h33333333);
		sspi_dw_read_check(8'h03,24'h020C,32'h44444444);


		sspi_dw_write(8'h02,24'h0000,32'h00112233);
		sspi_dw_write(8'h02,24'h0004,32'h44556677);
		sspi_dw_write(8'h02,24'h0008,32'h8899AABB);
		sspi_dw_write(8'h02,24'h000C,32'hCCDDEEFF);

		sspi_dw_write(8'h02,24'h0200,32'h11223344);
		sspi_dw_write(8'h02,24'h0204,32'h55667788);
		sspi_dw_write(8'h02,24'h0208,32'h99AABBCC);
		sspi_dw_write(8'h02,24'h020C,32'hDDEEFF00);


		sspi_dw_read_check(8'h03,24'h0000,32'h00112233);
		sspi_dw_read_check(8'h03,24'h0004,32'h44556677);
		sspi_dw_read_check(8'h03,24'h0008,32'h8899AABB);
		sspi_dw_read_check(8'h03,24'h000C,32'hCCDDEEFF);

		sspi_dw_read_check(8'h03,24'h0200,32'h11223344);
		sspi_dw_read_check(8'h03,24'h0204,32'h55667788);
		sspi_dw_read_check(8'h03,24'h0208,32'h99AABBCC);
		sspi_dw_read_check(8'h03,24'h020C,32'hDDEEFF00);

                $display("############################################");
                $display("   Testing IS62/65WVS1288GALL SSRAM[1] Read/Write Access       ");
                $display("############################################");



                spi_chip_no = 2'b01;
		sspi_dw_read_check(8'h03,24'h0000,32'h13121110);
		sspi_dw_read_check(8'h03,24'h0004,32'h17161514);
		sspi_dw_read_check(8'h03,24'h0008,32'h1B1A1918);
		sspi_dw_read_check(8'h03,24'h000C,32'h1F1E1D1C);
		
		sspi_dw_read_check(8'h03,24'h0010,32'h23222120);
		sspi_dw_read_check(8'h03,24'h0014,32'h27262524);
		sspi_dw_read_check(8'h03,24'h0018,32'h2B2A2928);
		sspi_dw_read_check(8'h03,24'h001C,32'h2F2E2D2C);
		
		sspi_dw_read_check(8'h03,24'h0020,32'h33323130);
		sspi_dw_read_check(8'h03,24'h0024,32'h37363534);
		sspi_dw_read_check(8'h03,24'h0028,32'h3B3A3938);
		sspi_dw_read_check(8'h03,24'h002C,32'h3F3E3D3C);

		sspi_dw_read_check(8'h03,24'h0030,32'h43424140);
		sspi_dw_read_check(8'h03,24'h0034,32'h47464544);
		sspi_dw_read_check(8'h03,24'h0038,32'h4B4A4948);
		sspi_dw_read_check(8'h03,24'h003C,32'h4F4E4D4C);

		sspi_dw_read_check(8'h03,24'h00a0,32'hb3b2b1b0);
		sspi_dw_read_check(8'h03,24'h00a4,32'hb7b6b5b4);
		sspi_dw_read_check(8'h03,24'h00a8,32'hbbbab9b8);
		sspi_dw_read_check(8'h03,24'h00aC,32'hbfbebdbc);

		sspi_dw_read_check(8'h03,24'h0200,32'h22222222);
		sspi_dw_read_check(8'h03,24'h0204,32'h33333333);
		sspi_dw_read_check(8'h03,24'h0208,32'h44444444);
		sspi_dw_read_check(8'h03,24'h020C,32'h55555555);


		sspi_dw_write(8'h02,24'h0000,32'h00112233);
		sspi_dw_write(8'h02,24'h0004,32'h44556677);
		sspi_dw_write(8'h02,24'h0008,32'h8899AABB);
		sspi_dw_write(8'h02,24'h000C,32'hCCDDEEFF);

		sspi_dw_write(8'h02,24'h0200,32'h11223344);
		sspi_dw_write(8'h02,24'h0204,32'h55667788);
		sspi_dw_write(8'h02,24'h0208,32'h99AABBCC);
		sspi_dw_write(8'h02,24'h020C,32'hDDEEFF00);


		sspi_dw_read_check(8'h03,24'h0000,32'h00112233);
		sspi_dw_read_check(8'h03,24'h0004,32'h44556677);
		sspi_dw_read_check(8'h03,24'h0008,32'h8899AABB);
		sspi_dw_read_check(8'h03,24'h000C,32'hCCDDEEFF);

		sspi_dw_read_check(8'h03,24'h0200,32'h11223344);
		sspi_dw_read_check(8'h03,24'h0204,32'h55667788);
		sspi_dw_read_check(8'h03,24'h0208,32'h99AABBCC);
		sspi_dw_read_check(8'h03,24'h020C,32'hDDEEFF00);

                $display("############################################");
                $display("   Testing IS62/65WVS1288GALL SSRAM[2] Read/Write Access       ");
                $display("############################################");



                spi_chip_no = 2'b10;
		sspi_dw_read_check(8'h03,24'h0000,32'h23222120);
		sspi_dw_read_check(8'h03,24'h0004,32'h27262524);
		sspi_dw_read_check(8'h03,24'h0008,32'h2b2a2928);
		sspi_dw_read_check(8'h03,24'h000C,32'h2f2e2d2c);

		sspi_dw_read_check(8'h03,24'h0010,32'h33323130);
		sspi_dw_read_check(8'h03,24'h0014,32'h37363534);
		sspi_dw_read_check(8'h03,24'h0018,32'h3B3A3938);
		sspi_dw_read_check(8'h03,24'h001C,32'h3F3E3D3C);
		
		sspi_dw_read_check(8'h03,24'h0020,32'h43424140);
		sspi_dw_read_check(8'h03,24'h0024,32'h47464544);
		sspi_dw_read_check(8'h03,24'h0028,32'h4B4A4948);
		sspi_dw_read_check(8'h03,24'h002C,32'h4F4E4D4C);
		
		sspi_dw_read_check(8'h03,24'h0030,32'h53525150);
		sspi_dw_read_check(8'h03,24'h0034,32'h57565554);
		sspi_dw_read_check(8'h03,24'h0038,32'h5B5A5958);
		sspi_dw_read_check(8'h03,24'h003C,32'h5F5E5D5C);

		sspi_dw_read_check(8'h03,24'h0040,32'h63626160);
		sspi_dw_read_check(8'h03,24'h0044,32'h67666564);
		sspi_dw_read_check(8'h03,24'h0048,32'h6B6A6968);
		sspi_dw_read_check(8'h03,24'h004C,32'h6F6E6D6C);

		sspi_dw_read_check(8'h03,24'h00a0,32'hc3c2c1c0);
		sspi_dw_read_check(8'h03,24'h00a4,32'hc7c6c5c4);
		sspi_dw_read_check(8'h03,24'h00a8,32'hcbcac9c8);
		sspi_dw_read_check(8'h03,24'h00aC,32'hcfcecdcc);

		sspi_dw_read_check(8'h03,24'h0200,32'h33333333);
		sspi_dw_read_check(8'h03,24'h0204,32'h44444444);
		sspi_dw_read_check(8'h03,24'h0208,32'h55555555);
		sspi_dw_read_check(8'h03,24'h020C,32'h66666666);


		sspi_dw_write(8'h02,24'h0000,32'h00112233);
		sspi_dw_write(8'h02,24'h0004,32'h44556677);
		sspi_dw_write(8'h02,24'h0008,32'h8899AABB);
		sspi_dw_write(8'h02,24'h000C,32'hCCDDEEFF);

		sspi_dw_write(8'h02,24'h0200,32'h11223344);
		sspi_dw_write(8'h02,24'h0204,32'h55667788);
		sspi_dw_write(8'h02,24'h0208,32'h99AABBCC);
		sspi_dw_write(8'h02,24'h020C,32'hDDEEFF00);


		sspi_dw_read_check(8'h03,24'h0000,32'h00112233);
		sspi_dw_read_check(8'h03,24'h0004,32'h44556677);
		sspi_dw_read_check(8'h03,24'h0008,32'h8899AABB);
		sspi_dw_read_check(8'h03,24'h000C,32'hCCDDEEFF);

		sspi_dw_read_check(8'h03,24'h0200,32'h11223344);
		sspi_dw_read_check(8'h03,24'h0204,32'h55667788);
		sspi_dw_read_check(8'h03,24'h0208,32'h99AABBCC);
		sspi_dw_read_check(8'h03,24'h020C,32'hDDEEFF00);

                $display("############################################");
                $display("   Testing IS62/65WVS1288GALL SSRAM[3] Read/Write Access       ");
                $display("############################################");



                spi_chip_no = 2'b11;
		sspi_dw_read_check(8'h03,24'h0000,32'h33323130);
		sspi_dw_read_check(8'h03,24'h0004,32'h37363534);
		sspi_dw_read_check(8'h03,24'h0008,32'h3b3a3938);
		sspi_dw_read_check(8'h03,24'h000C,32'h3f3e3d3c);

		sspi_dw_read_check(8'h03,24'h0010,32'h43424140);
		sspi_dw_read_check(8'h03,24'h0014,32'h47464544);
		sspi_dw_read_check(8'h03,24'h0018,32'h4B4A4948);
		sspi_dw_read_check(8'h03,24'h001C,32'h4F4E4D4C);

		sspi_dw_read_check(8'h03,24'h0020,32'h53525150);
		sspi_dw_read_check(8'h03,24'h0024,32'h57565554);
		sspi_dw_read_check(8'h03,24'h0028,32'h5B5A5958);
		sspi_dw_read_check(8'h03,24'h002C,32'h5F5E5D5C);

		sspi_dw_read_check(8'h03,24'h00a0,32'hd3d2d1d0);
		sspi_dw_read_check(8'h03,24'h00a4,32'hd7d6d5d4);
		sspi_dw_read_check(8'h03,24'h00a8,32'hdbdad9d8);
		sspi_dw_read_check(8'h03,24'h00aC,32'hdfdedddc);

		sspi_dw_read_check(8'h03,24'h0200,32'h44444444);
		sspi_dw_read_check(8'h03,24'h0204,32'h55555555);
		sspi_dw_read_check(8'h03,24'h0208,32'h66666666);
		sspi_dw_read_check(8'h03,24'h020C,32'h77777777);


		sspi_dw_write(8'h02,24'h0000,32'h00112233);
		sspi_dw_write(8'h02,24'h0004,32'h44556677);
		sspi_dw_write(8'h02,24'h0008,32'h8899AABB);
		sspi_dw_write(8'h02,24'h000C,32'hCCDDEEFF);

		sspi_dw_write(8'h02,24'h0200,32'h11223344);
		sspi_dw_write(8'h02,24'h0204,32'h55667788);
		sspi_dw_write(8'h02,24'h0208,32'h99AABBCC);
		sspi_dw_write(8'h02,24'h020C,32'hDDEEFF00);


		sspi_dw_read_check(8'h03,24'h0000,32'h00112233);
		sspi_dw_read_check(8'h03,24'h0004,32'h44556677);
		sspi_dw_read_check(8'h03,24'h0008,32'h8899AABB);
		sspi_dw_read_check(8'h03,24'h000C,32'hCCDDEEFF);

		sspi_dw_read_check(8'h03,24'h0200,32'h11223344);
		sspi_dw_read_check(8'h03,24'h0204,32'h55667788);
		sspi_dw_read_check(8'h03,24'h0208,32'h99AABBCC);
		sspi_dw_read_check(8'h03,24'h020C,32'hDDEEFF00);
		repeat (100) @(posedge clock);


          	if(test_fail == 0) begin
		   `ifdef GL
	    	       $display("Monitor: SPI Master Mode (GL) Passed");
		   `else
		       $display("Monitor: SPI Master Mode (RTL) Passed");
		   `endif
	        end else begin
		    `ifdef GL
	    	        $display("Monitor: SPI Master Mode (GL) Failed");
		    `else
		        $display("Monitor: SPI Master Mode (RTL) Failed");
		    `endif
		 end
	    	$display("###################################################");
	        $finish;
	end

	initial begin
		wb_rst_i <= 1'b1;
		#100;
		wb_rst_i <= 1'b0;
	end
wire USER_VDD1V8 = 1'b1;
wire VSS = 1'b0;

user_project_wrapper u_top(
`ifdef USE_POWER_PINS
    .vccd1(USER_VDD1V8),
    .vssd1(VSS),
`endif
    .wb_clk_i        (clock),
    .user_clock2     (1'b1),
    .wb_rst_i        (wb_rst_i),

    .wbs_cyc_i   (wbd_ext_cyc_i),
    .wbs_stb_i   (wbd_ext_stb_i),
    .wbs_adr_i   (wbd_ext_adr_i),
    .wbs_we_i    (wbd_ext_we_i),
    .wbs_dat_i   (wbd_ext_dat_i),
    .wbs_sel_i   (wbd_ext_sel_i),

    .wbs_dat_o   (wbd_ext_dat_o),
    .wbs_ack_o   (wbd_ext_ack_o),

 

    .la_data_in      ('1) ,
    .la_data_out     (),
    .la_oenb         ('0),
 


    .io_in          (io_in)  ,
    .io_out         (io_out) ,
    .io_oeb         (io_oeb) ,

    .user_irq       () 

);

`ifndef GL

    initial begin

    end
`endif    





   wire flash_io1;
   wire flash_clk = io_out[16];
   tri  #1 flash_io0 = io_out[15];
   assign io_in[14] = flash_io1;

   tri  #1 flash_io2 = 1'b1;
   tri  #1 flash_io3 = 1'b1;


   wire spiram_csb0 = io_out[13];
   is62wvs1288 #(.mem_file_name("flash0.hex"))
	u_sfram_0 (

           .io0     (flash_io0),
           .io1     (flash_io1),

           .clk    (flash_clk),
           .csb    (spiram_csb0),
           .io2    (flash_io2),
           .io3    (flash_io3)
    );

   wire spiram_csb1 = io_out[12];
   is62wvs1288 #(.mem_file_name("flash1.hex"))
	u_sfram_1 (

           .io0     (flash_io0),
           .io1     (flash_io1),

           .clk    (flash_clk),
           .csb    (spiram_csb1),
           .io2    (flash_io2),
           .io3    (flash_io3)
    );

   wire spiram_csb2 = io_out[9];
is62wvs1288 #(.mem_file_name("flash2.hex"))
     u_sfram_2 (

	.io0     (flash_io0),
	.io1     (flash_io1),

	.clk    (flash_clk),
	.csb    (spiram_csb2),
	.io2    (flash_io2),
	.io3    (flash_io3)
 );

   wire spiram_csb3 = io_out[8];
is62wvs1288 #(.mem_file_name("flash3.hex"))
     u_sfram_3 (

	.io0     (flash_io0),
	.io1     (flash_io1),

	.clk    (flash_clk),
	.csb    (spiram_csb3),
	.io2    (flash_io2),
	.io3    (flash_io3)
 );




task test_err;
begin
     test_fail = 1;
end
endtask

task wb_user_core_write;
input [31:0] address;
input [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h1;
  wbd_ext_dat_i =data;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  $display("STATUS: WB USER ACCESS WRITE Address : 0x%x, Data : 0x%x",address,data);
  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read;
input [31:0] address;
output [31:0] data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;

  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read_check;
input [31:0] address;
output [31:0] data;
input [31:0] cmp_data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  if(data !== cmp_data) begin
     $display("ERROR : WB USER ACCESS READ  Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
     user_sspi_tb.test_fail = 1;
  end else begin
     $display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,data);
  end
  repeat (2) @(posedge clock);
end
endtask


`ifdef GL

wire        wbd_spi_stb_i   = u_top.u_spi_master.wbd_stb_i;
wire        wbd_spi_ack_o   = u_top.u_spi_master.wbd_ack_o;
wire        wbd_spi_we_i    = u_top.u_spi_master.wbd_we_i;
wire [31:0] wbd_spi_adr_i   = u_top.u_spi_master.wbd_adr_i;
wire [31:0] wbd_spi_dat_i   = u_top.u_spi_master.wbd_dat_i;
wire [31:0] wbd_spi_dat_o   = u_top.u_spi_master.wbd_dat_o;
wire [3:0]  wbd_spi_sel_i   = u_top.u_spi_master.wbd_sel_i;

wire        wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i;
wire        wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o;
wire        wbd_sdram_we_i  = u_top.u_sdram_ctrl.wb_we_i;
wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i;
wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i;
wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
wire [3:0]  wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;

wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb.reg_cs;
wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb.reg_ack;
wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb.reg_wr;
wire [7:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb.reg_addr;
wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb.reg_wdata;
wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb.reg_rdata;
wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb.reg_be;

`endif


`include "sspi_task.v"

endmodule
module user_sspi_tb;

	reg clock;
	reg wb_rst_i;
	reg power1, power2;
	reg power3, power4;

        reg        wbd_ext_cyc_i;
        reg        wbd_ext_stb_i;
        reg [31:0] wbd_ext_adr_i;
        reg        wbd_ext_we_i;
        reg [31:0] wbd_ext_dat_i;
        reg [3:0]  wbd_ext_sel_i;

        wire [31:0] wbd_ext_dat_o;
        wire        wbd_ext_ack_o;
        wire        wbd_ext_err_o;


	wire [37:0] io_oeb;
	wire [37:0] io_out;
	wire [37:0] io_in;


	reg [1:0] spi_chip_no;

	wire gpio;
	wire [37:0] mprj_io;
	wire [7:0] mprj_io_0;
	reg        test_fail;
	reg [31:0] read_data;






	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
                wbd_ext_cyc_i ='h0;
                wbd_ext_stb_i ='h0;
                wbd_ext_adr_i ='h0;
                wbd_ext_we_i  ='h0;
                wbd_ext_dat_i ='h0;
                wbd_ext_sel_i ='h0;
	end

	`ifdef WFDUMP
	   initial begin
	   	$dumpfile("simx.vcd");
	   	$dumpvars(5, user_sspi_tb);
	   end
       `endif

	initial begin
		$dumpon;

		#200;
	        repeat (10) @(posedge clock);
		$display("Monitor: Standalone User Risc Boot Test Started");


		wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);


                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h3C00);

	        repeat (2) @(posedge clock);
		#1;



                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F);


		test_fail = 0;
		sspi_init();
	        repeat (200) @(posedge clock);
                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000);
                $display("############################################");
                $display("   Testing IS62/65WVS1288GALL SSRAM[0] Read/Write Access       ");
                $display("############################################");



                spi_chip_no = 2'b00;
		sspi_dw_read_check(8'h03,24'h0000,32'h03020100);
		sspi_dw_read_check(8'h03,24'h0004,32'h07060504);
		sspi_dw_read_check(8'h03,24'h0008,32'h0b0a0908);
		sspi_dw_read_check(8'h03,24'h000C,32'h0f0e0d0c);
		sspi_dw_read_check(8'h03,24'h0010,32'h13121110);
		sspi_dw_read_check(8'h03,24'h0014,32'h17161514);
		sspi_dw_read_check(8'h03,24'h0018,32'h1B1A1918);
		sspi_dw_read_check(8'h03,24'h001C,32'h1F1E1D1C);

		sspi_dw_read_check(8'h03,24'h0040,32'h43424140);
		sspi_dw_read_check(8'h03,24'h0044,32'h47464544);
		sspi_dw_read_check(8'h03,24'h0048,32'h4B4A4948);
		sspi_dw_read_check(8'h03,24'h004C,32'h4F4E4D4C);

		sspi_dw_read_check(8'h03,24'h00a0,32'ha3a2a1a0);
		sspi_dw_read_check(8'h03,24'h00a4,32'ha7a6a5a4);
		sspi_dw_read_check(8'h03,24'h00a8,32'habaaa9a8);
		sspi_dw_read_check(8'h03,24'h00aC,32'hafaeadac);

		sspi_dw_read_check(8'h03,24'h0200,32'h11111111);
		sspi_dw_read_check(8'h03,24'h0204,32'h22222222);
		sspi_dw_read_check(8'h03,24'h0208,32'h33333333);
		sspi_dw_read_check(8'h03,24'h020C,32'h44444444);


		sspi_dw_write(8'h02,24'h0000,32'h00112233);
		sspi_dw_write(8'h02,24'h0004,32'h44556677);
		sspi_dw_write(8'h02,24'h0008,32'h8899AABB);
		sspi_dw_write(8'h02,24'h000C,32'hCCDDEEFF);

		sspi_dw_write(8'h02,24'h0200,32'h11223344);
		sspi_dw_write(8'h02,24'h0204,32'h55667788);
		sspi_dw_write(8'h02,24'h0208,32'h99AABBCC);
		sspi_dw_write(8'h02,24'h020C,32'hDDEEFF00);


		sspi_dw_read_check(8'h03,24'h0000,32'h00112233);
		sspi_dw_read_check(8'h03,24'h0004,32'h44556677);
		sspi_dw_read_check(8'h03,24'h0008,32'h8899AABB);
		sspi_dw_read_check(8'h03,24'h000C,32'hCCDDEEFF);

		sspi_dw_read_check(8'h03,24'h0200,32'h11223344);
		sspi_dw_read_check(8'h03,24'h0204,32'h55667788);
		sspi_dw_read_check(8'h03,24'h0208,32'h99AABBCC);
		sspi_dw_read_check(8'h03,24'h020C,32'hDDEEFF00);

                $display("############################################");
                $display("   Testing IS62/65WVS1288GALL SSRAM[1] Read/Write Access       ");
                $display("############################################");



                spi_chip_no = 2'b01;
		sspi_dw_read_check(8'h03,24'h0000,32'h13121110);
		sspi_dw_read_check(8'h03,24'h0004,32'h17161514);
		sspi_dw_read_check(8'h03,24'h0008,32'h1B1A1918);
		sspi_dw_read_check(8'h03,24'h000C,32'h1F1E1D1C);
		
		sspi_dw_read_check(8'h03,24'h0010,32'h23222120);
		sspi_dw_read_check(8'h03,24'h0014,32'h27262524);
		sspi_dw_read_check(8'h03,24'h0018,32'h2B2A2928);
		sspi_dw_read_check(8'h03,24'h001C,32'h2F2E2D2C);
		
		sspi_dw_read_check(8'h03,24'h0020,32'h33323130);
		sspi_dw_read_check(8'h03,24'h0024,32'h37363534);
		sspi_dw_read_check(8'h03,24'h0028,32'h3B3A3938);
		sspi_dw_read_check(8'h03,24'h002C,32'h3F3E3D3C);

		sspi_dw_read_check(8'h03,24'h0030,32'h43424140);
		sspi_dw_read_check(8'h03,24'h0034,32'h47464544);
		sspi_dw_read_check(8'h03,24'h0038,32'h4B4A4948);
		sspi_dw_read_check(8'h03,24'h003C,32'h4F4E4D4C);

		sspi_dw_read_check(8'h03,24'h00a0,32'hb3b2b1b0);
		sspi_dw_read_check(8'h03,24'h00a4,32'hb7b6b5b4);
		sspi_dw_read_check(8'h03,24'h00a8,32'hbbbab9b8);
		sspi_dw_read_check(8'h03,24'h00aC,32'hbfbebdbc);

		sspi_dw_read_check(8'h03,24'h0200,32'h22222222);
		sspi_dw_read_check(8'h03,24'h0204,32'h33333333);
		sspi_dw_read_check(8'h03,24'h0208,32'h44444444);
		sspi_dw_read_check(8'h03,24'h020C,32'h55555555);


		sspi_dw_write(8'h02,24'h0000,32'h00112233);
		sspi_dw_write(8'h02,24'h0004,32'h44556677);
		sspi_dw_write(8'h02,24'h0008,32'h8899AABB);
		sspi_dw_write(8'h02,24'h000C,32'hCCDDEEFF);

		sspi_dw_write(8'h02,24'h0200,32'h11223344);
		sspi_dw_write(8'h02,24'h0204,32'h55667788);
		sspi_dw_write(8'h02,24'h0208,32'h99AABBCC);
		sspi_dw_write(8'h02,24'h020C,32'hDDEEFF00);


		sspi_dw_read_check(8'h03,24'h0000,32'h00112233);
		sspi_dw_read_check(8'h03,24'h0004,32'h44556677);
		sspi_dw_read_check(8'h03,24'h0008,32'h8899AABB);
		sspi_dw_read_check(8'h03,24'h000C,32'hCCDDEEFF);

		sspi_dw_read_check(8'h03,24'h0200,32'h11223344);
		sspi_dw_read_check(8'h03,24'h0204,32'h55667788);
		sspi_dw_read_check(8'h03,24'h0208,32'h99AABBCC);
		sspi_dw_read_check(8'h03,24'h020C,32'hDDEEFF00);

                $display("############################################");
                $display("   Testing IS62/65WVS1288GALL SSRAM[2] Read/Write Access       ");
                $display("############################################");



                spi_chip_no = 2'b10;
		sspi_dw_read_check(8'h03,24'h0000,32'h23222120);
		sspi_dw_read_check(8'h03,24'h0004,32'h27262524);
		sspi_dw_read_check(8'h03,24'h0008,32'h2b2a2928);
		sspi_dw_read_check(8'h03,24'h000C,32'h2f2e2d2c);

		sspi_dw_read_check(8'h03,24'h0010,32'h33323130);
		sspi_dw_read_check(8'h03,24'h0014,32'h37363534);
		sspi_dw_read_check(8'h03,24'h0018,32'h3B3A3938);
		sspi_dw_read_check(8'h03,24'h001C,32'h3F3E3D3C);
		
		sspi_dw_read_check(8'h03,24'h0020,32'h43424140);
		sspi_dw_read_check(8'h03,24'h0024,32'h47464544);
		sspi_dw_read_check(8'h03,24'h0028,32'h4B4A4948);
		sspi_dw_read_check(8'h03,24'h002C,32'h4F4E4D4C);
		
		sspi_dw_read_check(8'h03,24'h0030,32'h53525150);
		sspi_dw_read_check(8'h03,24'h0034,32'h57565554);
		sspi_dw_read_check(8'h03,24'h0038,32'h5B5A5958);
		sspi_dw_read_check(8'h03,24'h003C,32'h5F5E5D5C);

		sspi_dw_read_check(8'h03,24'h0040,32'h63626160);
		sspi_dw_read_check(8'h03,24'h0044,32'h67666564);
		sspi_dw_read_check(8'h03,24'h0048,32'h6B6A6968);
		sspi_dw_read_check(8'h03,24'h004C,32'h6F6E6D6C);

		sspi_dw_read_check(8'h03,24'h00a0,32'hc3c2c1c0);
		sspi_dw_read_check(8'h03,24'h00a4,32'hc7c6c5c4);
		sspi_dw_read_check(8'h03,24'h00a8,32'hcbcac9c8);
		sspi_dw_read_check(8'h03,24'h00aC,32'hcfcecdcc);

		sspi_dw_read_check(8'h03,24'h0200,32'h33333333);
		sspi_dw_read_check(8'h03,24'h0204,32'h44444444);
		sspi_dw_read_check(8'h03,24'h0208,32'h55555555);
		sspi_dw_read_check(8'h03,24'h020C,32'h66666666);


		sspi_dw_write(8'h02,24'h0000,32'h00112233);
		sspi_dw_write(8'h02,24'h0004,32'h44556677);
		sspi_dw_write(8'h02,24'h0008,32'h8899AABB);
		sspi_dw_write(8'h02,24'h000C,32'hCCDDEEFF);

		sspi_dw_write(8'h02,24'h0200,32'h11223344);
		sspi_dw_write(8'h02,24'h0204,32'h55667788);
		sspi_dw_write(8'h02,24'h0208,32'h99AABBCC);
		sspi_dw_write(8'h02,24'h020C,32'hDDEEFF00);


		sspi_dw_read_check(8'h03,24'h0000,32'h00112233);
		sspi_dw_read_check(8'h03,24'h0004,32'h44556677);
		sspi_dw_read_check(8'h03,24'h0008,32'h8899AABB);
		sspi_dw_read_check(8'h03,24'h000C,32'hCCDDEEFF);

		sspi_dw_read_check(8'h03,24'h0200,32'h11223344);
		sspi_dw_read_check(8'h03,24'h0204,32'h55667788);
		sspi_dw_read_check(8'h03,24'h0208,32'h99AABBCC);
		sspi_dw_read_check(8'h03,24'h020C,32'hDDEEFF00);

                $display("############################################");
                $display("   Testing IS62/65WVS1288GALL SSRAM[3] Read/Write Access       ");
                $display("############################################");



                spi_chip_no = 2'b11;
		sspi_dw_read_check(8'h03,24'h0000,32'h33323130);
		sspi_dw_read_check(8'h03,24'h0004,32'h37363534);
		sspi_dw_read_check(8'h03,24'h0008,32'h3b3a3938);
		sspi_dw_read_check(8'h03,24'h000C,32'h3f3e3d3c);

		sspi_dw_read_check(8'h03,24'h0010,32'h43424140);
		sspi_dw_read_check(8'h03,24'h0014,32'h47464544);
		sspi_dw_read_check(8'h03,24'h0018,32'h4B4A4948);
		sspi_dw_read_check(8'h03,24'h001C,32'h4F4E4D4C);

		sspi_dw_read_check(8'h03,24'h0020,32'h53525150);
		sspi_dw_read_check(8'h03,24'h0024,32'h57565554);
		sspi_dw_read_check(8'h03,24'h0028,32'h5B5A5958);
		sspi_dw_read_check(8'h03,24'h002C,32'h5F5E5D5C);

		sspi_dw_read_check(8'h03,24'h00a0,32'hd3d2d1d0);
		sspi_dw_read_check(8'h03,24'h00a4,32'hd7d6d5d4);
		sspi_dw_read_check(8'h03,24'h00a8,32'hdbdad9d8);
		sspi_dw_read_check(8'h03,24'h00aC,32'hdfdedddc);

		sspi_dw_read_check(8'h03,24'h0200,32'h44444444);
		sspi_dw_read_check(8'h03,24'h0204,32'h55555555);
		sspi_dw_read_check(8'h03,24'h0208,32'h66666666);
		sspi_dw_read_check(8'h03,24'h020C,32'h77777777);


		sspi_dw_write(8'h02,24'h0000,32'h00112233);
		sspi_dw_write(8'h02,24'h0004,32'h44556677);
		sspi_dw_write(8'h02,24'h0008,32'h8899AABB);
		sspi_dw_write(8'h02,24'h000C,32'hCCDDEEFF);

		sspi_dw_write(8'h02,24'h0200,32'h11223344);
		sspi_dw_write(8'h02,24'h0204,32'h55667788);
		sspi_dw_write(8'h02,24'h0208,32'h99AABBCC);
		sspi_dw_write(8'h02,24'h020C,32'hDDEEFF00);


		sspi_dw_read_check(8'h03,24'h0000,32'h00112233);
		sspi_dw_read_check(8'h03,24'h0004,32'h44556677);
		sspi_dw_read_check(8'h03,24'h0008,32'h8899AABB);
		sspi_dw_read_check(8'h03,24'h000C,32'hCCDDEEFF);

		sspi_dw_read_check(8'h03,24'h0200,32'h11223344);
		sspi_dw_read_check(8'h03,24'h0204,32'h55667788);
		sspi_dw_read_check(8'h03,24'h0208,32'h99AABBCC);
		sspi_dw_read_check(8'h03,24'h020C,32'hDDEEFF00);
		repeat (100) @(posedge clock);


          	if(test_fail == 0) begin
		   `ifdef GL
	    	       $display("Monitor: SPI Master Mode (GL) Passed");
		   `else
		       $display("Monitor: SPI Master Mode (RTL) Passed");
		   `endif
	        end else begin
		    `ifdef GL
	    	        $display("Monitor: SPI Master Mode (GL) Failed");
		    `else
		        $display("Monitor: SPI Master Mode (RTL) Failed");
		    `endif
		 end
	    	$display("###################################################");
	        $finish;
	end

	initial begin
		wb_rst_i <= 1'b1;
		#100;
		wb_rst_i <= 1'b0;
	end
wire USER_VDD1V8 = 1'b1;
wire VSS = 1'b0;

user_project_wrapper u_top(
`ifdef USE_POWER_PINS
    .vccd1(USER_VDD1V8),
    .vssd1(VSS),
`endif
    .wb_clk_i        (clock),
    .user_clock2     (1'b1),
    .wb_rst_i        (wb_rst_i),

    .wbs_cyc_i   (wbd_ext_cyc_i),
    .wbs_stb_i   (wbd_ext_stb_i),
    .wbs_adr_i   (wbd_ext_adr_i),
    .wbs_we_i    (wbd_ext_we_i),
    .wbs_dat_i   (wbd_ext_dat_i),
    .wbs_sel_i   (wbd_ext_sel_i),

    .wbs_dat_o   (wbd_ext_dat_o),
    .wbs_ack_o   (wbd_ext_ack_o),

 

    .la_data_in      ('1) ,
    .la_data_out     (),
    .la_oenb         ('0),
 


    .io_in          (io_in)  ,
    .io_out         (io_out) ,
    .io_oeb         (io_oeb) ,

    .user_irq       () 

);

`ifndef GL

    initial begin

    end
`endif    





   wire flash_io1;
   wire flash_clk = io_out[16];
   tri  #1 flash_io0 = io_out[15];
   assign io_in[14] = flash_io1;

   tri  #1 flash_io2 = 1'b1;
   tri  #1 flash_io3 = 1'b1;


   wire spiram_csb0 = io_out[13];
   is62wvs1288 #(.mem_file_name("flash0.hex"))
	u_sfram_0 (

           .io0     (flash_io0),
           .io1     (flash_io1),

           .clk    (flash_clk),
           .csb    (spiram_csb0),
           .io2    (flash_io2),
           .io3    (flash_io3)
    );

   wire spiram_csb1 = io_out[12];
   is62wvs1288 #(.mem_file_name("flash1.hex"))
	u_sfram_1 (

           .io0     (flash_io0),
           .io1     (flash_io1),

           .clk    (flash_clk),
           .csb    (spiram_csb1),
           .io2    (flash_io2),
           .io3    (flash_io3)
    );

   wire spiram_csb2 = io_out[9];
is62wvs1288 #(.mem_file_name("flash2.hex"))
     u_sfram_2 (

	.io0     (flash_io0),
	.io1     (flash_io1),

	.clk    (flash_clk),
	.csb    (spiram_csb2),
	.io2    (flash_io2),
	.io3    (flash_io3)
 );

   wire spiram_csb3 = io_out[8];
is62wvs1288 #(.mem_file_name("flash3.hex"))
     u_sfram_3 (

	.io0     (flash_io0),
	.io1     (flash_io1),

	.clk    (flash_clk),
	.csb    (spiram_csb3),
	.io2    (flash_io2),
	.io3    (flash_io3)
 );




task test_err;
begin
     test_fail = 1;
end
endtask

task wb_user_core_write;
input [31:0] address;
input [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h1;
  wbd_ext_dat_i =data;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  $display("STATUS: WB USER ACCESS WRITE Address : 0x%x, Data : 0x%x",address,data);
  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read;
input [31:0] address;
output [31:0] data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;

  repeat (2) @(posedge clock);
end
endtask

task  wb_user_core_read_check;
input [31:0] address;
output [31:0] data;
input [31:0] cmp_data;
reg    [31:0] data;
begin
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_adr_i =address;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='0;
  wbd_ext_sel_i ='hF;
  wbd_ext_cyc_i ='h1;
  wbd_ext_stb_i ='h1;
  wait(wbd_ext_ack_o == 1);
  data  = wbd_ext_dat_o;  
  repeat (1) @(posedge clock);
  #1;
  wbd_ext_cyc_i ='h0;
  wbd_ext_stb_i ='h0;
  wbd_ext_adr_i ='h0;
  wbd_ext_we_i  ='h0;
  wbd_ext_dat_i ='h0;
  wbd_ext_sel_i ='h0;
  if(data !== cmp_data) begin
     $display("ERROR : WB USER ACCESS READ  Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
     user_sspi_tb.test_fail = 1;
  end else begin
     $display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,data);
  end
  repeat (2) @(posedge clock);
end
endtask


`ifdef GL

wire        wbd_spi_stb_i   = u_top.u_spi_master.wbd_stb_i;
wire        wbd_spi_ack_o   = u_top.u_spi_master.wbd_ack_o;
wire        wbd_spi_we_i    = u_top.u_spi_master.wbd_we_i;
wire [31:0] wbd_spi_adr_i   = u_top.u_spi_master.wbd_adr_i;
wire [31:0] wbd_spi_dat_i   = u_top.u_spi_master.wbd_dat_i;
wire [31:0] wbd_spi_dat_o   = u_top.u_spi_master.wbd_dat_o;
wire [3:0]  wbd_spi_sel_i   = u_top.u_spi_master.wbd_sel_i;

wire        wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i;
wire        wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o;
wire        wbd_sdram_we_i  = u_top.u_sdram_ctrl.wb_we_i;
wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i;
wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i;
wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
wire [3:0]  wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;

wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb.reg_cs;
wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb.reg_ack;
wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb.reg_wr;
wire [7:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb.reg_addr;
wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb.reg_wdata;
wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb.reg_rdata;
wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb.reg_be;

`endif


`include "sspi_task.v"

endmodule