data/full_repos/permissive/417288846/List_1/Task_3/encoder_4_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_3/encoder_4_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n        #1 v2 = 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_3/encoder_4_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n        #1 v2 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_3/encoder_4_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #1 v4 = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_3/encoder_4_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #1 v4 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_3/encoder_4_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #1 v2 = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_3/encoder_4_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #1 v1 = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_3/encoder_4_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #1 v1 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_3/encoder_4_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #1 v4 = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_3/encoder_4_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #1 v3 = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_3/encoder_4_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #1 v2 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_3/encoder_4_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #1 v3 = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_3/encoder_4_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #1 v1 = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_3/encoder_4_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #2 $finish;\n        ^\n%Error: data/full_repos/permissive/417288846/List_1/Task_3/encoder_4_tb.v:30: Unsupported or unknown PLI call: $monitor\n    initial $monitor ($time, " v1=%d, v2=%d, v3=%d v4=%d | num=2\'b%d%d valid=%d", v1, v2, v3, v4, num1, num2, valid);\n            ^~~~~~~~\n%Error: Exiting due to 1 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
    reg v1, v2, v3, v4;
    wire valid, num1, num2;

    encoder_4 enc1(.v1(v1), .v2(v2), .v3(v3), .v4(v4), .valid(valid), .num1(num1), .num2(num2));
    initial begin
        v1 = 0;
        v2 = 0;
        v3 = 0;
        v4 = 0;

        #1 v2 = 1;
        #1 v2 = 0;

        #1 v4 = 1;
        #1 v4 = 0;

        #1 v2 = 1;
        #1 v1 = 1;
        #1 v1 = 0;
        #1 v4 = 1;
        #1 v3 = 1;
        #1 v2 = 0;
        #1 v3 = 0;
        #1 v1 = 1;

        #2 $finish;
    end
    initial $monitor ($time, " v1=%d, v2=%d, v3=%d v4=%d | num=2'b%d%d valid=%d", v1, v2, v3, v4, num1, num2, valid);
endmodule
module testbench;

    reg v1, v2, v3, v4;
    wire valid, num1, num2;

    encoder_4 enc1(.v1(v1), .v2(v2), .v3(v3), .v4(v4), .valid(valid), .num1(num1), .num2(num2));
    initial begin
        v1 = 0;
        v2 = 0;
        v3 = 0;
        v4 = 0;

        #1 v2 = 1;
        #1 v2 = 0;

        #1 v4 = 1;
        #1 v4 = 0;

        #1 v2 = 1;
        #1 v1 = 1;
        #1 v1 = 0;
        #1 v4 = 1;
        #1 v3 = 1;
        #1 v2 = 0;
        #1 v3 = 0;
        #1 v1 = 1;

        #2 $finish;
    end
    initial $monitor ($time, " v1=%d, v2=%d, v3=%d v4=%d | num=2'b%d%d valid=%d", v1, v2, v3, v4, num1, num2, valid);
endmodule