data/full_repos/permissive/513199821/test.v
1: b'%Error: data/full_repos/permissive/513199821/test.v:1: Cannot find include file: global.inc\n`include "global.inc" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc.v\n             data/full_repos/permissive/513199821,data/full_repos/permissive/513199821/global.inc.sv\n             global.inc\n             global.inc.v\n             global.inc.sv\n             obj_dir/global.inc\n             obj_dir/global.inc.v\n             obj_dir/global.inc.sv\n%Warning-STMTDLY: data/full_repos/permissive/513199821/test.v:492: Unsupported: Ignoring delay on this delayed statement.\n  #32;    \n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/513199821/test.v:494: Unsupported: Ignoring delay on this delayed statement.\n  #32;\n  ^\n%Error: data/full_repos/permissive/513199821/test.v:500: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile ("/tmp/eonsoc.lxt");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/513199821/test.v:501: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars (0, test);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/513199821/test.v:504: Unsupported or unknown PLI call: $timeformat\n  $timeformat (-6, 3, "us", 12);\n  ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/513199821/test.v:509: Unsupported: Ignoring delay on this delayed statement.\n  #128;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/513199821/test.v:514: Unsupported: Ignoring delay on this delayed statement.\n    #200;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/513199821/test.v:516: Unsupported: Ignoring delay on this delayed statement.\n    #100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/513199821/test.v:522: Unsupported: Ignoring delay on this delayed statement.\n    # 64;\n    ^\n%Error: Exiting due to 4 error(s), 6 warning(s)\n'
module Ic2Slave #(
    parameter SLAVE_ADDR = 7'h50,
    parameter READ_BYTES = 2
  ) (
  inout wire SDA,
  input wire SCL
  );

localparam READ_ADDRESS = 0;
localparam SKIP 	= 1;
localparam READ_WRITE	= 2;
localparam ADDRESS_ACK	= 3;
localparam ADDR_HI	= 4;
localparam ADDR_HI_ACK	= 5;
localparam ADDR_LO	= 6;
localparam ADDR_LO_ACK	= 7;
localparam READ_DATA	= 8;
localparam DATA_ACK	= 9;
localparam DATA_END0	= 10;

reg [3:0]  state = 0;
reg [6:0]  addr;
reg [3:0]  addressCounter;
reg [15:0] rom_addr = 0;

reg [7:0] data;
reg [2:0] dataCounter;
reg [7:0] readCounter;

reg readWrite;
reg start = 0;
reg write_ack = 0;

reg    vsda_out = 0;
wire   vsda_oe;
assign vsda_oe = state == READ_DATA || (state == DATA_ACK && SCL);

assign SDA = write_ack == 1 ? 0 : (vsda_oe ? vsda_out : 1'bz);



reg [7:0] rommem [0:8191];
initial begin
  $display  ("Loading ROM ...");
  $readmemh ("/tmp/zrom.hex", rommem);
end

always @(negedge SCL) begin
  write_ack <= 0;
end

always @(negedge SDA) begin
  if ((start == 0) && (SCL == 1)) begin

    start	   <= 1;
    addressCounter <= 0;
    addr	   <= 7'h00;
    vsda_out	   <= 0;
    state	   <= READ_ADDRESS;
`ifdef I2CTEST
    $display ("i2cslv start %t", $time);
`endif
  end
end

always @(posedge SDA) begin
  if (SCL == 1 && state == SKIP) begin
    start <= 0;
    state <= READ_ADDRESS;
`ifdef I2CTEST
    $display ("i2cslv stop  %t", $time);
`endif
  end
end

always @(posedge SCL) begin
  if (start == 1) begin
    case (state)

      READ_ADDRESS: begin
	addr	       <= {addr[5:0], SDA};
	addressCounter <= addressCounter + 1;

	if (addressCounter == 6) begin
	  state <= READ_WRITE;
	end
      end

      SKIP: begin

	write_ack <= 0;

      end

      READ_WRITE: begin
	readWrite   <= SDA;
	readCounter <= READ_BYTES;
	state	    <= addr == SLAVE_ADDR ? ADDRESS_ACK : SKIP;
`ifdef I2CTEST
	$display ("i2cslv r/w-- %t = %d addr %x", $time, SDA, addr);
`endif
      end

      ADDRESS_ACK: begin
	write_ack   <= 1;
	state	    <= ADDR_HI;
	dataCounter <= 0;
	if (readWrite) begin
	  state    <= READ_DATA;
	  data	   <= rommem[rom_addr[12:0]];
	  rom_addr <= rom_addr + 1'b1;
	end
`ifdef I2CTEST
	$display ("i2cslv addrC %t read/write= %d addr=%x rom_addr=%x", $time, readWrite, addr, rom_addr);
`endif
      end

      ADDR_HI: begin
	write_ack	  <= 0;
	rom_addr	  <= {rom_addr[14:0], SDA};
	dataCounter	  <= dataCounter + 1;
`ifdef I2CTEST
	$display ("i2cslv addrH %t bit %d = %d", $time, 7 - dataCounter, SDA);
`endif
	if (dataCounter == 7) begin
	  state       <= ADDR_HI_ACK;
	end
      end

      ADDR_HI_ACK: begin
	write_ack   <= 1;
	dataCounter <= 0;
	state	    <= ADDR_LO;
`ifdef I2CTEST
	$display ("i2cslv addrH %t = %x", $time, rom_addr);
`endif
      end

      ADDR_LO: begin
	write_ack   <= 0;
	rom_addr    <= {rom_addr[14:0], SDA};
	dataCounter <= dataCounter + 1;
`ifdef I2CTEST
	$display ("i2cslv addrL %t bit %d = %d", $time, 7 - dataCounter, SDA);
`endif
	if (dataCounter == 7) begin
	  state     <= ADDR_LO_ACK;
	end
      end

      ADDR_LO_ACK: begin
	write_ack <= 1;
	state	  <= SKIP;
`ifdef I2CTEST
	$display ("i2cslv addrL %t = %x", $time, rom_addr);
`endif
      end

      READ_DATA: begin
	write_ack   <= 0;
	vsda_out    <= data[7 - dataCounter];
	dataCounter <= dataCounter + 1;

	if (dataCounter == 7) begin

	  state       <= DATA_ACK;
	  dataCounter <= 0;
	  data	      <= rommem[rom_addr[12:0]];
	  rom_addr    <= rom_addr + 1'b1;
	  readCounter <= readCounter - 1'b1;

	end
      end

      DATA_ACK: begin
	state <= |readCounter ? READ_DATA : DATA_END0;

      end

      DATA_END0: begin
`ifdef I2CTEST
	$display ("i2cslv dend0 %t", $time);
`endif
	state <= SKIP;
      end

    endcase
  end
end
endmodule
module Ic2Slave #(
    parameter SLAVE_ADDR = 7'h50,
    parameter READ_BYTES = 2
  ) (
  inout wire SDA,
  input wire SCL
  );


localparam READ_ADDRESS = 0;
localparam SKIP 	= 1;
localparam READ_WRITE	= 2;
localparam ADDRESS_ACK	= 3;
localparam ADDR_HI	= 4;
localparam ADDR_HI_ACK	= 5;
localparam ADDR_LO	= 6;
localparam ADDR_LO_ACK	= 7;
localparam READ_DATA	= 8;
localparam DATA_ACK	= 9;
localparam DATA_END0	= 10;

reg [3:0]  state = 0;
reg [6:0]  addr;
reg [3:0]  addressCounter;
reg [15:0] rom_addr = 0;

reg [7:0] data;
reg [2:0] dataCounter;
reg [7:0] readCounter;

reg readWrite;
reg start = 0;
reg write_ack = 0;

reg    vsda_out = 0;
wire   vsda_oe;
assign vsda_oe = state == READ_DATA || (state == DATA_ACK && SCL);

assign SDA = write_ack == 1 ? 0 : (vsda_oe ? vsda_out : 1'bz);



reg [7:0] rommem [0:8191];
initial begin
  $display  ("Loading ROM ...");
  $readmemh ("/tmp/zrom.hex", rommem);
end

always @(negedge SCL) begin
  write_ack <= 0;
end

always @(negedge SDA) begin
  if ((start == 0) && (SCL == 1)) begin

    start	   <= 1;
    addressCounter <= 0;
    addr	   <= 7'h00;
    vsda_out	   <= 0;
    state	   <= READ_ADDRESS;
`ifdef I2CTEST
    $display ("i2cslv start %t", $time);
`endif
  end
end

always @(posedge SDA) begin
  if (SCL == 1 && state == SKIP) begin
    start <= 0;
    state <= READ_ADDRESS;
`ifdef I2CTEST
    $display ("i2cslv stop  %t", $time);
`endif
  end
end

always @(posedge SCL) begin
  if (start == 1) begin
    case (state)

      READ_ADDRESS: begin
	addr	       <= {addr[5:0], SDA};
	addressCounter <= addressCounter + 1;

	if (addressCounter == 6) begin
	  state <= READ_WRITE;
	end
      end

      SKIP: begin

	write_ack <= 0;

      end

      READ_WRITE: begin
	readWrite   <= SDA;
	readCounter <= READ_BYTES;
	state	    <= addr == SLAVE_ADDR ? ADDRESS_ACK : SKIP;
`ifdef I2CTEST
	$display ("i2cslv r/w-- %t = %d addr %x", $time, SDA, addr);
`endif
      end

      ADDRESS_ACK: begin
	write_ack   <= 1;
	state	    <= ADDR_HI;
	dataCounter <= 0;
	if (readWrite) begin
	  state    <= READ_DATA;
	  data	   <= rommem[rom_addr[12:0]];
	  rom_addr <= rom_addr + 1'b1;
	end
`ifdef I2CTEST
	$display ("i2cslv addrC %t read/write= %d addr=%x rom_addr=%x", $time, readWrite, addr, rom_addr);
`endif
      end

      ADDR_HI: begin
	write_ack	  <= 0;
	rom_addr	  <= {rom_addr[14:0], SDA};
	dataCounter	  <= dataCounter + 1;
`ifdef I2CTEST
	$display ("i2cslv addrH %t bit %d = %d", $time, 7 - dataCounter, SDA);
`endif
	if (dataCounter == 7) begin
	  state       <= ADDR_HI_ACK;
	end
      end

      ADDR_HI_ACK: begin
	write_ack   <= 1;
	dataCounter <= 0;
	state	    <= ADDR_LO;
`ifdef I2CTEST
	$display ("i2cslv addrH %t = %x", $time, rom_addr);
`endif
      end

      ADDR_LO: begin
	write_ack   <= 0;
	rom_addr    <= {rom_addr[14:0], SDA};
	dataCounter <= dataCounter + 1;
`ifdef I2CTEST
	$display ("i2cslv addrL %t bit %d = %d", $time, 7 - dataCounter, SDA);
`endif
	if (dataCounter == 7) begin
	  state     <= ADDR_LO_ACK;
	end
      end

      ADDR_LO_ACK: begin
	write_ack <= 1;
	state	  <= SKIP;
`ifdef I2CTEST
	$display ("i2cslv addrL %t = %x", $time, rom_addr);
`endif
      end

      READ_DATA: begin
	write_ack   <= 0;
	vsda_out    <= data[7 - dataCounter];
	dataCounter <= dataCounter + 1;

	if (dataCounter == 7) begin

	  state       <= DATA_ACK;
	  dataCounter <= 0;
	  data	      <= rommem[rom_addr[12:0]];
	  rom_addr    <= rom_addr + 1'b1;
	  readCounter <= readCounter - 1'b1;

	end
      end

      DATA_ACK: begin
	state <= |readCounter ? READ_DATA : DATA_END0;

      end

      DATA_END0: begin
`ifdef I2CTEST
	$display ("i2cslv dend0 %t", $time);
`endif
	state <= SKIP;
      end

    endcase
  end
end
endmodule