data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/SyzMem.v
1: b"%Error: data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new/SyzMem.v:41: Cannot find file containing module: 'BlockRamDesign_wrapper'\n  BlockRamDesign_wrapper bram(\n  ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new,data/full_repos/permissive/42815087/BlockRamDesign_wrapper\n             data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new,data/full_repos/permissive/42815087/BlockRamDesign_wrapper.v\n             data/full_repos/permissive/42815087/cpu/SyzygyB100.srcs/sources_1/new,data/full_repos/permissive/42815087/BlockRamDesign_wrapper.sv\n             BlockRamDesign_wrapper\n             BlockRamDesign_wrapper.v\n             BlockRamDesign_wrapper.sv\n             obj_dir/BlockRamDesign_wrapper\n             obj_dir/BlockRamDesign_wrapper.v\n             obj_dir/BlockRamDesign_wrapper.sv\n%Error: Exiting due to 1 error(s)\n"
module SyzMem(
    input en,
    input memClk,
    input [15:0] addr,
    input [15:0] dIn,
    input readEn,
    input writeEn,
    input vgaClk,
    input [15:0] vgaAddr,
    output [15:0] dOut,
    output [15:0] vgaOut
  );
  
  wire [15:0] wMemDataOut;
  wire wDelClk;
  
  assign #8 wDelClk = memClk;
  
  BlockRamDesign_wrapper bram(
    .addra(addr[15:0]),
    .addrb(vgaAddr[15:0]),
    .clka(wDelClk),
    .clkb(vgaClk),
    .dina(dIn[15:0]),
    .dinb(16'h0000),
    .douta(wMemDataOut[15:0]),
    .doutb(vgaOut[15:0]),
    .ena(en),
    .enb(en),
    .wea({writeEn, writeEn}),
    .web(2'b00)
  );
  
  assign dOut[15:0] = (readEn) ? wMemDataOut[15:0] : 16'h0000;
  
endmodule
module SyzMem(
    input en,
    input memClk,
    input [15:0] addr,
    input [15:0] dIn,
    input readEn,
    input writeEn,
    input vgaClk,
    input [15:0] vgaAddr,
    output [15:0] dOut,
    output [15:0] vgaOut
  );

  
  wire [15:0] wMemDataOut;
  wire wDelClk;
  
  assign #8 wDelClk = memClk;
  
  BlockRamDesign_wrapper bram(
    .addra(addr[15:0]),
    .addrb(vgaAddr[15:0]),
    .clka(wDelClk),
    .clkb(vgaClk),
    .dina(dIn[15:0]),
    .dinb(16'h0000),
    .douta(wMemDataOut[15:0]),
    .doutb(vgaOut[15:0]),
    .ena(en),
    .enb(en),
    .wea({writeEn, writeEn}),
    .web(2'b00)
  );
  
  assign dOut[15:0] = (readEn) ? wMemDataOut[15:0] : 16'h0000;
  
endmodule