data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/keyinput_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/keyinput_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n    forever #(PERIOD/2)  clk=~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/keyinput_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #PERIOD keys = 4\'b0010;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/keyinput_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #(5*PERIOD) keys = 4\'b0000;\n    ^\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/keyinput_tb.v:22: Cannot find file containing module: \'key_input\'\nkey_input #(W)  u_key_input (\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/434840709/USTB_verilog_elevator/sim,data/full_repos/permissive/434840709/key_input\n             data/full_repos/permissive/434840709/USTB_verilog_elevator/sim,data/full_repos/permissive/434840709/key_input.v\n             data/full_repos/permissive/434840709/USTB_verilog_elevator/sim,data/full_repos/permissive/434840709/key_input.sv\n             key_input\n             key_input.v\n             key_input.sv\n             obj_dir/key_input\n             obj_dir/key_input.v\n             obj_dir/key_input.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_key_input;


parameter PERIOD  = 10, W = 4;



reg   clk                                  = 0 ;
reg   [W - 1:0]  keys                      = 0 ;


wire  [W - 1: 0]  key_press                ;


initial
begin
    forever #(PERIOD/2)  clk=~clk;
end

key_input #(W)  u_key_input (
    .clk                     ( clk                   ),
    .keys                    ( keys       [W - 1:0]  ),

    .key_press               ( key_press  [W - 1: 0] )
);

initial
begin
    #PERIOD keys = 4'b0010;
    #(5*PERIOD) keys = 4'b0000;
end

endmodule
module tb_key_input;



parameter PERIOD  = 10, W = 4;



reg   clk                                  = 0 ;
reg   [W - 1:0]  keys                      = 0 ;


wire  [W - 1: 0]  key_press                ;


initial
begin
    forever #(PERIOD/2)  clk=~clk;
end

key_input #(W)  u_key_input (
    .clk                     ( clk                   ),
    .keys                    ( keys       [W - 1:0]  ),

    .key_press               ( key_press  [W - 1: 0] )
);

initial
begin
    #PERIOD keys = 4'b0010;
    #(5*PERIOD) keys = 4'b0000;
end

endmodule