data/full_repos/permissive/469509877/rtl/libs/countUD5L.v
1: b"%Error: data/full_repos/permissive/469509877/rtl/libs/countUD5L.v:37: Cannot find file containing module: 'FDRE'\n    FDRE #(.INIT(1'b0) ) ff0 (.C(clkin), .R(reset), .CE(Up | Dw | LD), .D(d0), .Q(Q[0]));\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/469509877/rtl/libs,data/full_repos/permissive/469509877/FDRE\n             data/full_repos/permissive/469509877/rtl/libs,data/full_repos/permissive/469509877/FDRE.v\n             data/full_repos/permissive/469509877/rtl/libs,data/full_repos/permissive/469509877/FDRE.sv\n             FDRE\n             FDRE.v\n             FDRE.sv\n             obj_dir/FDRE\n             obj_dir/FDRE.v\n             obj_dir/FDRE.sv\n%Error: data/full_repos/permissive/469509877/rtl/libs/countUD5L.v:38: Cannot find file containing module: 'FDRE'\n    FDRE #(.INIT(1'b0) ) ff1 (.C(clkin), .R(reset), .CE((Up & Q[0]) | (Dw & ~Q[0]) | LD), .D(d1), .Q(Q[1]));\n    ^~~~\n%Error: data/full_repos/permissive/469509877/rtl/libs/countUD5L.v:39: Cannot find file containing module: 'FDRE'\n    FDRE #(.INIT(1'b0) ) ff2 (.C(clkin), .R(reset), .CE((Up & Q[0] & Q[1]) | (Dw & ~Q[0] & ~Q[1]) | LD), .D(d2), .Q(Q[2]));\n    ^~~~\n%Error: data/full_repos/permissive/469509877/rtl/libs/countUD5L.v:40: Cannot find file containing module: 'FDRE'\n    FDRE #(.INIT(1'b0) ) ff3 (.C(clkin), .R(reset), .CE((Up & Q[0] & Q[1] & Q[2]) | (Dw & ~Q[0] & ~Q[1] * ~Q[2]) | LD), .D(d3), .Q(Q[3]));\n    ^~~~\n%Error: data/full_repos/permissive/469509877/rtl/libs/countUD5L.v:41: Cannot find file containing module: 'FDRE'\n    FDRE #(.INIT(1'b0) ) ff4 (.C(clkin), .R(reset), .CE((Up & Q[0] & Q[1] & Q[2] & Q[3]) | (Dw & ~Q[0] & ~Q[1] & ~Q[2] & ~Q[3]) | LD), .D(d4), .Q(Q[4]));\n    ^~~~\n%Error: data/full_repos/permissive/469509877/rtl/libs/countUD5L.v:43: Cannot find file containing module: 'mux2to1'\n    mux2to1 mux0 (.in0(~Q[0]), .in1(D[0]), .selector(LD), .out(d0));\n    ^~~~~~~\n%Error: data/full_repos/permissive/469509877/rtl/libs/countUD5L.v:44: Cannot find file containing module: 'mux2to1'\n    mux2to1 mux1 (.in0(~Q[1]), .in1(D[1]), .selector(LD), .out(d1));\n    ^~~~~~~\n%Error: data/full_repos/permissive/469509877/rtl/libs/countUD5L.v:45: Cannot find file containing module: 'mux2to1'\n    mux2to1 mux2 (.in0(~Q[2]), .in1(D[2]), .selector(LD), .out(d2));\n    ^~~~~~~\n%Error: data/full_repos/permissive/469509877/rtl/libs/countUD5L.v:46: Cannot find file containing module: 'mux2to1'\n    mux2to1 mux3 (.in0(~Q[3]), .in1(D[3]), .selector(LD), .out(d3));\n    ^~~~~~~\n%Error: data/full_repos/permissive/469509877/rtl/libs/countUD5L.v:47: Cannot find file containing module: 'mux2to1'\n    mux2to1 mux4 (.in0(~Q[4]), .in1(D[4]), .selector(LD), .out(d4));\n    ^~~~~~~\n%Error: Exiting due to 10 error(s)\n"
module countUD5L(
    input clkin,
    input Up,
    input Dw,
    input LD,
    input [4:0] D,
    input reset,
    output [4:0] Q,
    output UTC,
    output DTC
    );
    
    wire d0, d1, d2, d3, d4;
    
    FDRE #(.INIT(1'b0) ) ff0 (.C(clkin), .R(reset), .CE(Up | Dw | LD), .D(d0), .Q(Q[0]));
    FDRE #(.INIT(1'b0) ) ff1 (.C(clkin), .R(reset), .CE((Up & Q[0]) | (Dw & ~Q[0]) | LD), .D(d1), .Q(Q[1]));
    FDRE #(.INIT(1'b0) ) ff2 (.C(clkin), .R(reset), .CE((Up & Q[0] & Q[1]) | (Dw & ~Q[0] & ~Q[1]) | LD), .D(d2), .Q(Q[2]));
    FDRE #(.INIT(1'b0) ) ff3 (.C(clkin), .R(reset), .CE((Up & Q[0] & Q[1] & Q[2]) | (Dw & ~Q[0] & ~Q[1] * ~Q[2]) | LD), .D(d3), .Q(Q[3]));
    FDRE #(.INIT(1'b0) ) ff4 (.C(clkin), .R(reset), .CE((Up & Q[0] & Q[1] & Q[2] & Q[3]) | (Dw & ~Q[0] & ~Q[1] & ~Q[2] & ~Q[3]) | LD), .D(d4), .Q(Q[4]));
    
    mux2to1 mux0 (.in0(~Q[0]), .in1(D[0]), .selector(LD), .out(d0));
    mux2to1 mux1 (.in0(~Q[1]), .in1(D[1]), .selector(LD), .out(d1));
    mux2to1 mux2 (.in0(~Q[2]), .in1(D[2]), .selector(LD), .out(d2));
    mux2to1 mux3 (.in0(~Q[3]), .in1(D[3]), .selector(LD), .out(d3));
    mux2to1 mux4 (.in0(~Q[4]), .in1(D[4]), .selector(LD), .out(d4));
    
    assign UTC = Q[0] & Q[1] & Q[2] & Q[3] & Q[4];
    assign DTC = ~Q[0] & ~Q[1] & ~Q[2] & ~Q[3] & ~Q[4];
endmodule
module countUD5L(
    input clkin,
    input Up,
    input Dw,
    input LD,
    input [4:0] D,
    input reset,
    output [4:0] Q,
    output UTC,
    output DTC
    );

    
    wire d0, d1, d2, d3, d4;
    
    FDRE #(.INIT(1'b0) ) ff0 (.C(clkin), .R(reset), .CE(Up | Dw | LD), .D(d0), .Q(Q[0]));
    FDRE #(.INIT(1'b0) ) ff1 (.C(clkin), .R(reset), .CE((Up & Q[0]) | (Dw & ~Q[0]) | LD), .D(d1), .Q(Q[1]));
    FDRE #(.INIT(1'b0) ) ff2 (.C(clkin), .R(reset), .CE((Up & Q[0] & Q[1]) | (Dw & ~Q[0] & ~Q[1]) | LD), .D(d2), .Q(Q[2]));
    FDRE #(.INIT(1'b0) ) ff3 (.C(clkin), .R(reset), .CE((Up & Q[0] & Q[1] & Q[2]) | (Dw & ~Q[0] & ~Q[1] * ~Q[2]) | LD), .D(d3), .Q(Q[3]));
    FDRE #(.INIT(1'b0) ) ff4 (.C(clkin), .R(reset), .CE((Up & Q[0] & Q[1] & Q[2] & Q[3]) | (Dw & ~Q[0] & ~Q[1] & ~Q[2] & ~Q[3]) | LD), .D(d4), .Q(Q[4]));
    
    mux2to1 mux0 (.in0(~Q[0]), .in1(D[0]), .selector(LD), .out(d0));
    mux2to1 mux1 (.in0(~Q[1]), .in1(D[1]), .selector(LD), .out(d1));
    mux2to1 mux2 (.in0(~Q[2]), .in1(D[2]), .selector(LD), .out(d2));
    mux2to1 mux3 (.in0(~Q[3]), .in1(D[3]), .selector(LD), .out(d3));
    mux2to1 mux4 (.in0(~Q[4]), .in1(D[4]), .selector(LD), .out(d4));
    
    assign UTC = Q[0] & Q[1] & Q[2] & Q[3] & Q[4];
    assign DTC = ~Q[0] & ~Q[1] & ~Q[2] & ~Q[3] & ~Q[4];
endmodule