data/full_repos/permissive/510528482/Multiplication.v
1: b'%Warning-WIDTH: data/full_repos/permissive/510528482/Multiplication.v:12: Operator AND expects 5 bits on the LHS, but LHS\'s REPLICATE generates 4 bits.\n                                                                        : ... In instance Multiplier\n assign m1 = {4{a[1]}} & b[3:0];\n                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/510528482/Multiplication.v:12: Operator AND expects 5 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                        : ... In instance Multiplier\n assign m1 = {4{a[1]}} & b[3:0];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/510528482/Multiplication.v:13: Operator AND expects 6 bits on the LHS, but LHS\'s REPLICATE generates 4 bits.\n                                                                        : ... In instance Multiplier\n assign m2 = {4{a[2]}} & b[3:0];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/510528482/Multiplication.v:13: Operator AND expects 6 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                        : ... In instance Multiplier\n assign m2 = {4{a[2]}} & b[3:0];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/510528482/Multiplication.v:14: Operator AND expects 7 bits on the LHS, but LHS\'s REPLICATE generates 4 bits.\n                                                                        : ... In instance Multiplier\n assign m3 = {4{a[3]}} & b[3:0];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/510528482/Multiplication.v:14: Operator AND expects 7 bits on the RHS, but RHS\'s SEL generates 4 bits.\n                                                                        : ... In instance Multiplier\n assign m3 = {4{a[3]}} & b[3:0];\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/510528482/Multiplication.v:16: Operator ADD expects 8 bits on the LHS, but LHS\'s VARREF \'m0\' generates 4 bits.\n                                                                        : ... In instance Multiplier\n assign s1 = m0 + (m1<<1);\n                ^\n%Warning-WIDTH: data/full_repos/permissive/510528482/Multiplication.v:16: Operator SHIFTL expects 8 bits on the LHS, but LHS\'s VARREF \'m1\' generates 5 bits.\n                                                                        : ... In instance Multiplier\n assign s1 = m0 + (m1<<1);\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/510528482/Multiplication.v:17: Operator SHIFTL expects 8 bits on the LHS, but LHS\'s VARREF \'m2\' generates 6 bits.\n                                                                        : ... In instance Multiplier\n assign s2 = s1 + (m2<<2);\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/510528482/Multiplication.v:18: Operator SHIFTL expects 8 bits on the LHS, but LHS\'s VARREF \'m3\' generates 7 bits.\n                                                                        : ... In instance Multiplier\n assign s3 = s2 + (m3<<3);\n                     ^~\n%Error: Exiting due to 10 warning(s)\n'
module Multiplier(a,b,p);
	input [3:0] a,b;
	wire [3:0]m0;
	wire [4:0]m1;
	wire [5:0]m2;
	wire [6:0]m3;
	
	wire [7:0]s1,s2,s3;
	output [7:0]p;
	
	assign m0 = {4{a[0]}} & b[3:0];
	assign m1 = {4{a[1]}} & b[3:0];
	assign m2 = {4{a[2]}} & b[3:0];
	assign m3 = {4{a[3]}} & b[3:0];

	assign s1 = m0 + (m1<<1);
	assign s2 = s1 + (m2<<2);
	assign s3 = s2 + (m3<<3);
	assign p=s3;
endmodule
module Multiplier(a,b,p);

	input [3:0] a,b;
	wire [3:0]m0;
	wire [4:0]m1;
	wire [5:0]m2;
	wire [6:0]m3;
	
	wire [7:0]s1,s2,s3;
	output [7:0]p;
	
	assign m0 = {4{a[0]}} & b[3:0];
	assign m1 = {4{a[1]}} & b[3:0];
	assign m2 = {4{a[2]}} & b[3:0];
	assign m3 = {4{a[3]}} & b[3:0];

	assign s1 = m0 + (m1<<1);
	assign s2 = s1 + (m2<<2);
	assign s3 = s2 + (m3<<3);
	assign p=s3;
endmodule