data/full_repos/permissive/469300759/verilog/rtl/actuator_driver_controller.v
1: b"%Error: data/full_repos/permissive/469300759/verilog/rtl/actuator_driver_controller.v:203: Cannot find file containing module: 'top'\n top user_design (\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/469300759/verilog/rtl,data/full_repos/permissive/469300759/top\n             data/full_repos/permissive/469300759/verilog/rtl,data/full_repos/permissive/469300759/top.v\n             data/full_repos/permissive/469300759/verilog/rtl,data/full_repos/permissive/469300759/top.sv\n             top\n             top.v\n             top.sv\n             obj_dir/top\n             obj_dir/top.v\n             obj_dir/top.sv\n%Error: Exiting due to 1 error(s)\n"
module actuator_driver_controller
(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input  wire [127:0] la_data_in,
    output wire [127:0] la_data_out,
    input  wire [127:0] la_oenb,


    input  wire [`MPRJ_IO_PADS-1:0] io_in,
    output wire [`MPRJ_IO_PADS-1:0] io_out,
    output wire [`MPRJ_IO_PADS-1:0] io_oeb,



    input wire   user_clock2,


    output wire [2:0] irq

);
    wire 	clk;
    wire [37:0] user_data_out;
    wire [37:0] user_data_oeb;
    wire         enable_n; 
    wire [4:0]   rows;
    wire [1:0]   cols;
    wire [4:0]   rows_enable;
    wire [1:0]   cols_enable;
    wire [9:0]   rows_hbrige;
    wire [3:0]   cols_hbrige;
    reg [`MPRJ_IO_PADS-1:0] io_in_reg;
    wire         trigger_out_n;
    wire         trigger_in_n;
    wire         latch_data_n;
    wire         sclk;
    wire         mosi;
    wire         ss_n;
    wire         miso;



    assign irq = 3'b000;


    assign clk = (~la_oenb[64]) ? la_data_in[64]: user_clock2;

    genvar i;
    generate
    for(i=0;i<38;i=i+1'b1)
    begin : io_port_assignment
        assign io_out[i]     = (~la_oenb[i]) ? la_data_in[i]    : user_data_out[i];
	assign io_oeb[i]     = (~la_oenb[i+38]) ? la_data_in[i+38] : user_data_oeb[i];
	assign la_data_out[i] = (~la_oenb[i]) ? 1'b0 : io_in_reg[i];

	always@(posedge clk)
	begin
		io_in_reg[i] = io_in[i];
	end
    end
    endgenerate












    assign user_data_out = {
	1'b0,
	1'b0,
	1'b0,
	miso,
	1'b0,
	1'b0,
	1'b0,
	rows_hbrige[9],
	rows_hbrige[8],
	rows_hbrige[7],
	rows_hbrige[6],
	rows_hbrige[5],
	rows_hbrige[4],
	rows_hbrige[3],
	rows_hbrige[2],
	rows_hbrige[1],
	rows_hbrige[0],
	cols_hbrige[3],
	cols_hbrige[2],
	cols_hbrige[1],
	cols_hbrige[0],
	trigger_out_n,
	1'b0,
	rows[4],
	rows[3],
	rows[2],
	rows[1],
	rows[0],
	cols[1],
	cols[0],
	1'b0,
	1'b0,
	1'b0,
	1'b0,
	1'b0,
	1'b0,
	1'b0,
	1'b0
	};

    assign user_data_oeb = {
	1'b1,
	1'b1,
	1'b1,
	1'b0,
	1'b1,
	1'b1,
	1'b1,
	1'b0,
	1'b0,
	1'b0,
	1'b0,
	1'b0,
	1'b0,
	1'b0,
	1'b0,
	1'b0,
	1'b0,
	1'b0,
	1'b0,
	1'b0,
	1'b0,
	1'b0,
	1'b1,
	~rows_enable[4],
	~rows_enable[3],
	~rows_enable[2],
	~rows_enable[1],
	~rows_enable[0],
	~cols_enable[1],
	~cols_enable[0],
	1'b1,
	1'b1,
	1'b1,
	1'b1,
	1'b1,
	1'b1,
	1'b1,
	1'b0
	};







	
	assign enable_n     =	(~la_oenb[64]) ? la_data_in[64] : io_in_reg[37]; 
	assign trigger_in_n =	(~la_oenb[65]) ? la_data_in[65] : io_in_reg[36]; 	  
	assign latch_data_n =	(~la_oenb[66]) ? la_data_in[66] : io_in_reg[35];	
	assign mosi 	    =	(~la_oenb[67]) ? la_data_in[67] : io_in_reg[33];	
	assign ss_n 	    =	(~la_oenb[68]) ? la_data_in[68] : io_in_reg[32];	
	assign sclk 	    =	(~la_oenb[69]) ? la_data_in[69] : io_in_reg[31];	
    
	top user_design (
`ifdef USE_POWER_PINS
	    .vccd1		(vccd1		),
	    .vssd1		(vssd1		),
`endif
	  .clock		(clk		),
	  .enable_n		(enable_n	), 
	  .rows			(rows		),
	  .cols			(cols		),
	  .rows_enable		(rows_enable	),
	  .cols_enable		(cols_enable	),
	  .rows_hbrige		(rows_hbrige	),
	  .cols_hbrige		(cols_hbrige	),
	  .trigger_out_n	(trigger_out_n	),
	  .trigger_in_n		(trigger_in_n	),
	  .latch_data_n		(latch_data_n	),
	  .sclk			(sclk		),
	  .mosi			(mosi		),
	  .ss_n			(ss_n		),
	  .miso			(miso		)
	);

endmodule
module actuator_driver_controller
(
`ifdef USE_POWER_PINS
    inout vccd1,
    inout vssd1,
`endif


    input  wire [127:0] la_data_in,
    output wire [127:0] la_data_out,
    input  wire [127:0] la_oenb,


    input  wire [`MPRJ_IO_PADS-1:0] io_in,
    output wire [`MPRJ_IO_PADS-1:0] io_out,
    output wire [`MPRJ_IO_PADS-1:0] io_oeb,



    input wire   user_clock2,


    output wire [2:0] irq

);

    wire 	clk;
    wire [37:0] user_data_out;
    wire [37:0] user_data_oeb;
    wire         enable_n; 
    wire [4:0]   rows;
    wire [1:0]   cols;
    wire [4:0]   rows_enable;
    wire [1:0]   cols_enable;
    wire [9:0]   rows_hbrige;
    wire [3:0]   cols_hbrige;
    reg [`MPRJ_IO_PADS-1:0] io_in_reg;
    wire         trigger_out_n;
    wire         trigger_in_n;
    wire         latch_data_n;
    wire         sclk;
    wire         mosi;
    wire         ss_n;
    wire         miso;



    assign irq = 3'b000;


    assign clk = (~la_oenb[64]) ? la_data_in[64]: user_clock2;

    genvar i;
    generate
    for(i=0;i<38;i=i+1'b1)
    begin : io_port_assignment
        assign io_out[i]     = (~la_oenb[i]) ? la_data_in[i]    : user_data_out[i];
	assign io_oeb[i]     = (~la_oenb[i+38]) ? la_data_in[i+38] : user_data_oeb[i];
	assign la_data_out[i] = (~la_oenb[i]) ? 1'b0 : io_in_reg[i];

	always@(posedge clk)
	begin
		io_in_reg[i] = io_in[i];
	end
    end
    endgenerate












    assign user_data_out = {
	1'b0,
	1'b0,
	1'b0,
	miso,
	1'b0,
	1'b0,
	1'b0,
	rows_hbrige[9],
	rows_hbrige[8],
	rows_hbrige[7],
	rows_hbrige[6],
	rows_hbrige[5],
	rows_hbrige[4],
	rows_hbrige[3],
	rows_hbrige[2],
	rows_hbrige[1],
	rows_hbrige[0],
	cols_hbrige[3],
	cols_hbrige[2],
	cols_hbrige[1],
	cols_hbrige[0],
	trigger_out_n,
	1'b0,
	rows[4],
	rows[3],
	rows[2],
	rows[1],
	rows[0],
	cols[1],
	cols[0],
	1'b0,
	1'b0,
	1'b0,
	1'b0,
	1'b0,
	1'b0,
	1'b0,
	1'b0
	};

    assign user_data_oeb = {
	1'b1,
	1'b1,
	1'b1,
	1'b0,
	1'b1,
	1'b1,
	1'b1,
	1'b0,
	1'b0,
	1'b0,
	1'b0,
	1'b0,
	1'b0,
	1'b0,
	1'b0,
	1'b0,
	1'b0,
	1'b0,
	1'b0,
	1'b0,
	1'b0,
	1'b0,
	1'b1,
	~rows_enable[4],
	~rows_enable[3],
	~rows_enable[2],
	~rows_enable[1],
	~rows_enable[0],
	~cols_enable[1],
	~cols_enable[0],
	1'b1,
	1'b1,
	1'b1,
	1'b1,
	1'b1,
	1'b1,
	1'b1,
	1'b0
	};







	
	assign enable_n     =	(~la_oenb[64]) ? la_data_in[64] : io_in_reg[37]; 
	assign trigger_in_n =	(~la_oenb[65]) ? la_data_in[65] : io_in_reg[36]; 	  
	assign latch_data_n =	(~la_oenb[66]) ? la_data_in[66] : io_in_reg[35];	
	assign mosi 	    =	(~la_oenb[67]) ? la_data_in[67] : io_in_reg[33];	
	assign ss_n 	    =	(~la_oenb[68]) ? la_data_in[68] : io_in_reg[32];	
	assign sclk 	    =	(~la_oenb[69]) ? la_data_in[69] : io_in_reg[31];	
    
	top user_design (
`ifdef USE_POWER_PINS
	    .vccd1		(vccd1		),
	    .vssd1		(vssd1		),
`endif
	  .clock		(clk		),
	  .enable_n		(enable_n	), 
	  .rows			(rows		),
	  .cols			(cols		),
	  .rows_enable		(rows_enable	),
	  .cols_enable		(cols_enable	),
	  .rows_hbrige		(rows_hbrige	),
	  .cols_hbrige		(cols_hbrige	),
	  .trigger_out_n	(trigger_out_n	),
	  .trigger_in_n		(trigger_in_n	),
	  .latch_data_n		(latch_data_n	),
	  .sclk			(sclk		),
	  .mosi			(mosi		),
	  .ss_n			(ss_n		),
	  .miso			(miso		)
	);

endmodule