data/full_repos/permissive/458737381/src/verilog-parser/tests/ccx2mb.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ccx2mb.v:36: Cannot find include file: ccx2mb.h\n`include "ccx2mb.h" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/ccx2mb.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/ccx2mb.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/ccx2mb.h.sv\n             ccx2mb.h\n             ccx2mb.h.v\n             ccx2mb.h.sv\n             obj_dir/ccx2mb.h\n             obj_dir/ccx2mb.h.v\n             obj_dir/ccx2mb.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ccx2mb.v:76: Define or directive not defined: \'`FSL_D_WIDTH\'\n    output [`FSL_D_WIDTH-1:0] pcx_fsl_m_data;\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ccx2mb.v:81: Define or directive not defined: \'`CPX_WIDTH\'\n    output [`CPX_WIDTH-1:0] cpx_spc_data_cx2;\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ccx2mb.v:92: Define or directive not defined: \'`PCX_WIDTH\'\n    input [`PCX_WIDTH-1:0] spc_pcx_data_pa;\n           ^~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ccx2mb.v:102: Define or directive not defined: \'`FSL_D_WIDTH\'\n    input [`FSL_D_WIDTH-1:0] fsl_cpx_s_data;\n           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ccx2mb.v:111: Define or directive not defined: \'`FSL_D_WIDTH\'\n    wire [`FSL_D_WIDTH-1:0] pcx_fsl_m_data;\n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/ccx2mb.v:116: Define or directive not defined: \'`CPX_WIDTH\'\n    wire [`CPX_WIDTH-1:0] cpx_spc_data_cx2;\n          ^~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n'
module ccx2mb (

	pcx_spc_grant_px,
	pcx_fsl_m_control,
	pcx_fsl_m_data,
	pcx_fsl_m_write,

	cpx_spc_data_rdy_cx2,
	cpx_spc_data_cx2,

	cpx_fsl_s_read,


	gclk,
	reset_l,

	spc_pcx_data_pa,
	spc_pcx_atom_pq,
	spc_pcx_req_pq,

	fsl_pcx_m_full,

	fsl_cpx_s_exists,
	fsl_cpx_s_control,
	fsl_cpx_s_data
	);

    parameter C_EXT_RESET_HIGH = 0;
   




    output [4:0] pcx_spc_grant_px;


    output                    pcx_fsl_m_control;
    output [`FSL_D_WIDTH-1:0] pcx_fsl_m_data;
    output                    pcx_fsl_m_write;


    output                  cpx_spc_data_rdy_cx2;
    output [`CPX_WIDTH-1:0] cpx_spc_data_cx2;


    output cpx_fsl_s_read;



    input gclk;
    input reset_l;


    input [`PCX_WIDTH-1:0] spc_pcx_data_pa;
    input                  spc_pcx_atom_pq;
    input [4:0]            spc_pcx_req_pq;


    input fsl_pcx_m_full;


    input                    fsl_cpx_s_exists;
    input                    fsl_cpx_s_control;
    input [`FSL_D_WIDTH-1:0] fsl_cpx_s_data;




    wire [4:0] pcx_spc_grant_px;


    wire                    pcx_fsl_m_control;
    wire [`FSL_D_WIDTH-1:0] pcx_fsl_m_data;
    wire                    pcx_fsl_m_write;


    wire                  cpx_spc_data_rdy_cx2;
    wire [`CPX_WIDTH-1:0] cpx_spc_data_cx2;


    wire cpx_fsl_s_read;

    wire  reset_l_int;
    reg   reset_l_sync;
    reg   sync;

    always @(posedge gclk) begin
       {reset_l_sync, sync} <= {sync, reset_l};
    end
    assign reset_l_int = C_EXT_RESET_HIGH ? ~reset_l_sync : reset_l_sync;
   



    wire rclk;
    assign rclk = gclk;





    pcx2mb pcx (

	    .pcx_spc_grant_px(pcx_spc_grant_px),
	    .pcx_fsl_m_control(pcx_fsl_m_control),
	    .pcx_fsl_m_data(pcx_fsl_m_data),
	    .pcx_fsl_m_write(pcx_fsl_m_write),


	    .rclk(rclk),
	    .reset_l(reset_l_int),

	    .spc_pcx_data_pa(spc_pcx_data_pa),
	    .spc_pcx_atom_pq(spc_pcx_atom_pq),
	    .spc_pcx_req_pq(spc_pcx_req_pq),

	    .fsl_pcx_m_full(fsl_pcx_m_full)
	);




    mb2cpx cpx (

	    .cpx_spc_data_rdy_cx2(cpx_spc_data_rdy_cx2),
	    .cpx_spc_data_cx2(cpx_spc_data_cx2),

	    .cpx_fsl_s_read(cpx_fsl_s_read),


	    .rclk(rclk),
	    .reset_l(reset_l_int),

	    .fsl_cpx_s_exists(fsl_cpx_s_exists),
	    .fsl_cpx_s_control(fsl_cpx_s_control),
	    .fsl_cpx_s_data(fsl_cpx_s_data)
	);

endmodule
module ccx2mb (

	pcx_spc_grant_px,
	pcx_fsl_m_control,
	pcx_fsl_m_data,
	pcx_fsl_m_write,

	cpx_spc_data_rdy_cx2,
	cpx_spc_data_cx2,

	cpx_fsl_s_read,


	gclk,
	reset_l,

	spc_pcx_data_pa,
	spc_pcx_atom_pq,
	spc_pcx_req_pq,

	fsl_pcx_m_full,

	fsl_cpx_s_exists,
	fsl_cpx_s_control,
	fsl_cpx_s_data
	);


    parameter C_EXT_RESET_HIGH = 0;
   




    output [4:0] pcx_spc_grant_px;


    output                    pcx_fsl_m_control;
    output [`FSL_D_WIDTH-1:0] pcx_fsl_m_data;
    output                    pcx_fsl_m_write;


    output                  cpx_spc_data_rdy_cx2;
    output [`CPX_WIDTH-1:0] cpx_spc_data_cx2;


    output cpx_fsl_s_read;



    input gclk;
    input reset_l;


    input [`PCX_WIDTH-1:0] spc_pcx_data_pa;
    input                  spc_pcx_atom_pq;
    input [4:0]            spc_pcx_req_pq;


    input fsl_pcx_m_full;


    input                    fsl_cpx_s_exists;
    input                    fsl_cpx_s_control;
    input [`FSL_D_WIDTH-1:0] fsl_cpx_s_data;




    wire [4:0] pcx_spc_grant_px;


    wire                    pcx_fsl_m_control;
    wire [`FSL_D_WIDTH-1:0] pcx_fsl_m_data;
    wire                    pcx_fsl_m_write;


    wire                  cpx_spc_data_rdy_cx2;
    wire [`CPX_WIDTH-1:0] cpx_spc_data_cx2;


    wire cpx_fsl_s_read;

    wire  reset_l_int;
    reg   reset_l_sync;
    reg   sync;

    always @(posedge gclk) begin
       {reset_l_sync, sync} <= {sync, reset_l};
    end
    assign reset_l_int = C_EXT_RESET_HIGH ? ~reset_l_sync : reset_l_sync;
   



    wire rclk;
    assign rclk = gclk;





    pcx2mb pcx (

	    .pcx_spc_grant_px(pcx_spc_grant_px),
	    .pcx_fsl_m_control(pcx_fsl_m_control),
	    .pcx_fsl_m_data(pcx_fsl_m_data),
	    .pcx_fsl_m_write(pcx_fsl_m_write),


	    .rclk(rclk),
	    .reset_l(reset_l_int),

	    .spc_pcx_data_pa(spc_pcx_data_pa),
	    .spc_pcx_atom_pq(spc_pcx_atom_pq),
	    .spc_pcx_req_pq(spc_pcx_req_pq),

	    .fsl_pcx_m_full(fsl_pcx_m_full)
	);




    mb2cpx cpx (

	    .cpx_spc_data_rdy_cx2(cpx_spc_data_rdy_cx2),
	    .cpx_spc_data_cx2(cpx_spc_data_cx2),

	    .cpx_fsl_s_read(cpx_fsl_s_read),


	    .rclk(rclk),
	    .reset_l(reset_l_int),

	    .fsl_cpx_s_exists(fsl_cpx_s_exists),
	    .fsl_cpx_s_control(fsl_cpx_s_control),
	    .fsl_cpx_s_data(fsl_cpx_s_data)
	);

endmodule