data/full_repos/permissive/415491487/design_src/arithmetic_bus.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/415491487/design_src/arithmetic_bus.v:40: Multiple top level modules\n                                                                                      : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                      : ... Top module \'u24add_bus\'\nmodule u24add_bus(\n       ^~~~~~~~~~\n                                                                                      : ... Top module \'u24sub_bus\'\nmodule u24sub_bus(\n       ^~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module u24add_bus(
    input clk,
    input [2:0] op_sel,
    inout [23:0] bus
);
    reg [23:0] opa, opb, result;
    
    parameter in_a = 3'b01;
    parameter in_b = 3'b010;
    parameter out_result = 3'b100;
    
    assign bus = (op_sel == out_result) ? result : 24'hZ;
    always @(posedge clk) begin
        case (op_sel)
            in_a: begin
                opa <= bus;
            end
            in_b: begin
                opb <= bus;
            end
            out_result: begin
                result <= opa + opb;
            end
            default: begin
                $write("invalid case for u24add!");
            end
        endcase
    end
endmodule
module u24add_bus(
    input clk,
    input [2:0] op_sel,
    inout [23:0] bus
);

    reg [23:0] opa, opb, result;
    
    parameter in_a = 3'b01;
    parameter in_b = 3'b010;
    parameter out_result = 3'b100;
    
    assign bus = (op_sel == out_result) ? result : 24'hZ;
    always @(posedge clk) begin
        case (op_sel)
            in_a: begin
                opa <= bus;
            end
            in_b: begin
                opb <= bus;
            end
            out_result: begin
                result <= opa + opb;
            end
            default: begin
                $write("invalid case for u24add!");
            end
        endcase
    end
endmodule