data/full_repos/permissive/441359809/src/yosys/tests/simple/process.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/tests/simple/process.v:21: Multiple top level modules\n                                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                           : ... Top module \'blocking_cond\'\nmodule blocking_cond (in, out);\n       ^~~~~~~~~~~~~\n                                                                                           : ... Top module \'uut\'\nmodule uut(clk, arst, a, b, c, d, e, f,  out1);\n       ^~~\n                                                                                           : ... Top module \'uart\'\nmodule uart (reset, txclk, ld_tx_data, tx_empty, tx_cnt);\n       ^~~~\n%Error: Exiting due to 1 warning(s)\n'
module uart (reset, txclk, ld_tx_data, tx_empty, tx_cnt);

input reset;
input txclk;
input ld_tx_data;

output reg tx_empty;
output reg [3:0] tx_cnt;

always @ (posedge txclk)
if (reset) begin
  tx_empty      <= 1;
  tx_cnt        <= 0;
end else begin
   if (ld_tx_data) begin
     tx_empty <= 0;
   end
   if (!tx_empty) begin
     tx_cnt <= tx_cnt + 1;
   end
end

endmodule
module uart (reset, txclk, ld_tx_data, tx_empty, tx_cnt);


input reset;
input txclk;
input ld_tx_data;

output reg tx_empty;
output reg [3:0] tx_cnt;

always @ (posedge txclk)
if (reset) begin
  tx_empty      <= 1;
  tx_cnt        <= 0;
end else begin
   if (ld_tx_data) begin
     tx_empty <= 0;
   end
   if (!tx_empty) begin
     tx_cnt <= tx_cnt + 1;
   end
end

endmodule