data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/OEN_CLR.v
data/verilator_xmls/e0e50cc9-5439-481c-baf9-d71d6cce5957.xml
module OEN_CLR(

OEN_CLR_Clk,
OEN_CLR_Flag_Out_Full,

OEN_CLR_Clr,
OEN_CLR_Rptclr
);




input OEN_CLR_Clk;
input OEN_CLR_Flag_Out_Full;
output OEN_CLR_Clr;
output OEN_CLR_Rptclr;



reg Oe_Clr;
reg WaitClk;
reg Rptclr;





always@(posedge OEN_CLR_Clk )
begin
	if(OEN_CLR_Flag_Out_Full)begin
			WaitClk<=1;
			Rptclr<=0;
	end
			
	else
		begin
			Oe_Clr<=1;
			Rptclr<=1;
			WaitClk<=0;
		end
				
	if(WaitClk)
			Oe_Clr<=0;
end






assign OEN_CLR_Clr = Oe_Clr;
assign OEN_CLR_Rptclr = Rptclr;

endmodule
module OEN_CLR(

OEN_CLR_Clk,
OEN_CLR_Flag_Out_Full,

OEN_CLR_Clr,
OEN_CLR_Rptclr
);





input OEN_CLR_Clk;
input OEN_CLR_Flag_Out_Full;
output OEN_CLR_Clr;
output OEN_CLR_Rptclr;



reg Oe_Clr;
reg WaitClk;
reg Rptclr;





always@(posedge OEN_CLR_Clk )
begin
	if(OEN_CLR_Flag_Out_Full)begin
			WaitClk<=1;
			Rptclr<=0;
	end
			
	else
		begin
			Oe_Clr<=1;
			Rptclr<=1;
			WaitClk<=0;
		end
				
	if(WaitClk)
			Oe_Clr<=0;
end






assign OEN_CLR_Clr = Oe_Clr;
assign OEN_CLR_Rptclr = Rptclr;

endmodule