data/full_repos/permissive/489075769/write_address_ms.v
data/verilator_xmls/f15457a1-d9ea-432a-bc7c-4eb375d05308.xml
module write_address_master(ACLK, ARESETn,i_AWVALID, o_AWVALID, AWREADY, i_AWADDR, o_AWADDR, AWPROT);
	input ACLK;
	input ARESETn;
	input i_AWVALID;
	input AWREADY;
	output reg o_AWVALID;
	input [31:0] i_AWADDR;
	output reg [31:0] o_AWADDR;
	input [2:0] AWPROT;
	
		

	always @(posedge ACLK) begin
		o_AWVALID <= i_AWVALID;
		if(ARESETn)
		begin
		o_AWADDR <= 32'b0;
		o_AWVALID <=1'b0;
		end
		
		if (o_AWVALID && AWREADY) 
		o_AWADDR <= i_AWADDR;
		else 
		o_AWADDR <= 32'b0;
	end
	
	
endmodule
module write_address_master(ACLK, ARESETn,i_AWVALID, o_AWVALID, AWREADY, i_AWADDR, o_AWADDR, AWPROT);

	input ACLK;
	input ARESETn;
	input i_AWVALID;
	input AWREADY;
	output reg o_AWVALID;
	input [31:0] i_AWADDR;
	output reg [31:0] o_AWADDR;
	input [2:0] AWPROT;
	
		

	always @(posedge ACLK) begin
		o_AWVALID <= i_AWVALID;
		if(ARESETn)
		begin
		o_AWADDR <= 32'b0;
		o_AWVALID <=1'b0;
		end
		
		if (o_AWVALID && AWREADY) 
		o_AWADDR <= i_AWADDR;
		else 
		o_AWADDR <= 32'b0;
	end
	
	
endmodule