data/full_repos/permissive/50693363/riffa_builder/src/fpga/riffa_bram_core.v
data/verilator_xmls/8438626b-f0ab-48a3-a6f5-e1a831c5de58.xml
module riffa_bram_core #(
    parameter DATA_WIDTH = 32,
    parameter WEN_A_WIDTH = 4,
    parameter ADDR_WIDTH = 10
) (

    input   wire                Clk_A,
    input   wire    [WEN_A_WIDTH-1:0] WEN_A,
    input   wire                EN_A,
    input   wire    [ADDR_WIDTH-1:0]  Addr_A,
    input   wire    [DATA_WIDTH-1:0]  Din_A,
    output  reg     [DATA_WIDTH-1:0]  Dout_A,
     

    input   wire                Clk_B,
    input   wire                WEN_B,
    input   wire                EN_B,
    input   wire    [ADDR_WIDTH-1:0]  Addr_B,
    input   wire    [DATA_WIDTH-1:0]  Din_B,
    output  reg     [DATA_WIDTH-1:0]  Dout_B
);

localparam A_BYTE_WIDTH = DATA_WIDTH / WEN_A_WIDTH;

integer i;


reg [DATA_WIDTH-1:0] mem [(2**ADDR_WIDTH)-1:0];
 

always @(posedge Clk_A) begin
    if (EN_A)
    begin
        Dout_A      <= mem[Addr_A];
        
        for (i = 0; i < WEN_A_WIDTH; i = i + 1)
        begin
            if(WEN_A[i]) begin
                mem[Addr_A][i*A_BYTE_WIDTH +: A_BYTE_WIDTH] <= Din_A[i*A_BYTE_WIDTH +: A_BYTE_WIDTH];
            end
        end
    
    end
end


always @(posedge Clk_B) begin
    if (EN_B)
    begin
        Dout_B      <= mem[Addr_B];
        if(WEN_B) begin
            mem[Addr_B] <= Din_B;
        end
    end
end
 
endmodule
module riffa_bram_core #(
    parameter DATA_WIDTH = 32,
    parameter WEN_A_WIDTH = 4,
    parameter ADDR_WIDTH = 10
) (

    input   wire                Clk_A,
    input   wire    [WEN_A_WIDTH-1:0] WEN_A,
    input   wire                EN_A,
    input   wire    [ADDR_WIDTH-1:0]  Addr_A,
    input   wire    [DATA_WIDTH-1:0]  Din_A,
    output  reg     [DATA_WIDTH-1:0]  Dout_A,
     

    input   wire                Clk_B,
    input   wire                WEN_B,
    input   wire                EN_B,
    input   wire    [ADDR_WIDTH-1:0]  Addr_B,
    input   wire    [DATA_WIDTH-1:0]  Din_B,
    output  reg     [DATA_WIDTH-1:0]  Dout_B
);


localparam A_BYTE_WIDTH = DATA_WIDTH / WEN_A_WIDTH;

integer i;


reg [DATA_WIDTH-1:0] mem [(2**ADDR_WIDTH)-1:0];
 

always @(posedge Clk_A) begin
    if (EN_A)
    begin
        Dout_A      <= mem[Addr_A];
        
        for (i = 0; i < WEN_A_WIDTH; i = i + 1)
        begin
            if(WEN_A[i]) begin
                mem[Addr_A][i*A_BYTE_WIDTH +: A_BYTE_WIDTH] <= Din_A[i*A_BYTE_WIDTH +: A_BYTE_WIDTH];
            end
        end
    
    end
end


always @(posedge Clk_B) begin
    if (EN_B)
    begin
        Dout_B      <= mem[Addr_B];
        if(WEN_B) begin
            mem[Addr_B] <= Din_B;
        end
    end
end
 
endmodule