data/full_repos/permissive/507850313/rtl/general/gnl_dff.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/507850313/rtl/general/gnl_dff.v:50: Multiple top level modules\n                                                                                : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                : ... Top module \'sirv_gnrl_dfflrs\'\nmodule sirv_gnrl_dfflrs # (\n       ^~~~~~~~~~~~~~~~\n                                                                                : ... Top module \'sirv_gnrl_dfflr\'\nmodule sirv_gnrl_dfflr # (\n       ^~~~~~~~~~~~~~~\n                                                                                : ... Top module \'sirv_gnrl_dffl\'\nmodule sirv_gnrl_dffl # (\n       ^~~~~~~~~~~~~~\n                                                                                : ... Top module \'sirv_gnrl_dffrs\'\nmodule sirv_gnrl_dffrs # (\n       ^~~~~~~~~~~~~~~\n                                                                                : ... Top module \'sirv_gnrl_dffr\'\nmodule sirv_gnrl_dffr # (\n       ^~~~~~~~~~~~~~\n                                                                                : ... Top module \'sirv_gnrl_ltch\'\nmodule sirv_gnrl_ltch # (\n       ^~~~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module sirv_gnrl_dffrs # (
  parameter DW = 32
) (

  input      [DW-1:0] dnxt,
  output     [DW-1:0] qout,

  input               clk,
  input               rst_n
);

reg [DW-1:0] qout_r;

always @(posedge clk or negedge rst_n)
begin : DFFRS_PROC
  if (rst_n == 1'b0)
    qout_r <= {DW{1'b1}};
  else                  
    qout_r <= #1 dnxt;
end

assign qout = qout_r;

endmodule
module sirv_gnrl_dffrs # (
  parameter DW = 32
) (

  input      [DW-1:0] dnxt,
  output     [DW-1:0] qout,

  input               clk,
  input               rst_n
);


reg [DW-1:0] qout_r;

always @(posedge clk or negedge rst_n)
begin : DFFRS_PROC
  if (rst_n == 1'b0)
    qout_r <= {DW{1'b1}};
  else                  
    qout_r <= #1 dnxt;
end

assign qout = qout_r;

endmodule