data/full_repos/permissive/486206246/seq/fetch.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/486206246/seq/fetch.v:12: Little bit endian vector: MSB < LSB of bit range: 0:79\n  reg [0:79] instr;\n      ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/486206246/seq/fetch.v:39: Bit extraction of array[1023:0] requires 10 bit index, not 64 bits.\n                                                                   : ... In instance fetch\n      instr_mem[PC],\n               ^\n%Warning-WIDTH: data/full_repos/permissive/486206246/seq/fetch.v:40: Bit extraction of array[1023:0] requires 10 bit index, not 64 bits.\n                                                                   : ... In instance fetch\n      instr_mem[PC+1],\n               ^\n%Warning-WIDTH: data/full_repos/permissive/486206246/seq/fetch.v:41: Bit extraction of array[1023:0] requires 10 bit index, not 64 bits.\n                                                                   : ... In instance fetch\n      instr_mem[PC+2],\n               ^\n%Warning-WIDTH: data/full_repos/permissive/486206246/seq/fetch.v:42: Bit extraction of array[1023:0] requires 10 bit index, not 64 bits.\n                                                                   : ... In instance fetch\n      instr_mem[PC+3],\n               ^\n%Warning-WIDTH: data/full_repos/permissive/486206246/seq/fetch.v:43: Bit extraction of array[1023:0] requires 10 bit index, not 64 bits.\n                                                                   : ... In instance fetch\n      instr_mem[PC+4],\n               ^\n%Warning-WIDTH: data/full_repos/permissive/486206246/seq/fetch.v:44: Bit extraction of array[1023:0] requires 10 bit index, not 64 bits.\n                                                                   : ... In instance fetch\n      instr_mem[PC+5],\n               ^\n%Warning-WIDTH: data/full_repos/permissive/486206246/seq/fetch.v:45: Bit extraction of array[1023:0] requires 10 bit index, not 64 bits.\n                                                                   : ... In instance fetch\n      instr_mem[PC+6],\n               ^\n%Warning-WIDTH: data/full_repos/permissive/486206246/seq/fetch.v:46: Bit extraction of array[1023:0] requires 10 bit index, not 64 bits.\n                                                                   : ... In instance fetch\n      instr_mem[PC+7],\n               ^\n%Warning-WIDTH: data/full_repos/permissive/486206246/seq/fetch.v:47: Bit extraction of array[1023:0] requires 10 bit index, not 64 bits.\n                                                                   : ... In instance fetch\n      instr_mem[PC+8],\n               ^\n%Warning-WIDTH: data/full_repos/permissive/486206246/seq/fetch.v:48: Bit extraction of array[1023:0] requires 10 bit index, not 64 bits.\n                                                                   : ... In instance fetch\n      instr_mem[PC+9]\n               ^\n%Error: Exiting due to 11 warning(s)\n'
module fetch(
  clk,PC,
  icode,ifun,rA,rB,valC,valP,instr_valid,imem_error,hlt
);
  output reg [3:0] rA, rB, ifun, icode; 
  output reg [63:0] valP, valC;
  output reg imem_error, hlt, instr_valid;
  input clk;
  input [63:0] PC;
  reg [0:79] instr;
  reg [7:0] instr_mem[0:1023];

  initial begin

    instr_mem[37]=8'h32;
    instr_mem[38]=8'h4;
    instr_mem[39]=8'h16;
    instr_mem[40]=8'h16;
    instr_mem[41]=8'h16;
    instr_mem[42]=8'h16;
    instr_mem[43]=8'h16;
    instr_mem[44]=8'h16;
    instr_mem[45]=8'h0;

  end  

  always@(posedge clk) 
  begin 

    imem_error=0;
    if(PC>1023)
    begin
      imem_error=1;
    end

    instr={
      instr_mem[PC],
      instr_mem[PC+1],
      instr_mem[PC+2],
      instr_mem[PC+3],
      instr_mem[PC+4],
      instr_mem[PC+5],
      instr_mem[PC+6],
      instr_mem[PC+7],
      instr_mem[PC+8],
      instr_mem[PC+9]
    };

    icode= instr[0:3];
    ifun= instr[4:7];

    instr_valid=1'b1;

    if(icode==4'b0000)
    begin
      hlt=1;
      valP=PC+64'd1;
    end
    else if(icode==4'b0001)
    begin
      valP=PC+64'd1;
    end
    else if(icode==4'b0010)
    begin
      rA=instr[8:11];
      rB=instr[12:15];
      valP=PC+64'd2;
    end
    else if(icode==4'b0011)
    begin
      rA=instr[8:11];
      rB=instr[12:15];
      valC=instr[16:79];
      valP=PC+64'd10;
    end
    else if(icode==4'b0100)
    begin
      rA=instr[8:11];
      rB=instr[12:15];
      valC=instr[16:79];
      valP=PC+64'd10;
    end
    else if(icode==4'b0101)
    begin
      rA=instr[8:11];
      rB=instr[12:15];
      valC=instr[16:79];
      valP=PC+64'd10;
    end
    else if(icode==4'b0110)
    begin
      rA=instr[8:11];
      rB=instr[12:15];
      valP=PC+64'd2;
    end
    else if(icode==4'b0111)
    begin
      valC=instr[8:71];
      valP=PC+64'd9;
    end
    else if(icode==4'b1000)
    begin
      valC=instr[8:71];
      valP=PC+64'd9;
    end
    else if(icode==4'b1001)
    begin
      valP=PC+64'd1;
    end
    else if(icode==4'b1010)
    begin
      rA=instr[8:11];
      rB=instr[12:15];
      valP=PC+64'd2;
    end
    else if(icode==4'b1011)
    begin
      rA=instr[8:11];
      rB=instr[12:15];
      valP=PC+64'd2;
    end
    else 
    begin
      instr_valid=1'b0;
    end
  end

endmodule
module fetch(
  clk,PC,
  icode,ifun,rA,rB,valC,valP,instr_valid,imem_error,hlt
);

  output reg [3:0] rA, rB, ifun, icode; 
  output reg [63:0] valP, valC;
  output reg imem_error, hlt, instr_valid;
  input clk;
  input [63:0] PC;
  reg [0:79] instr;
  reg [7:0] instr_mem[0:1023];

  initial begin

    instr_mem[37]=8'h32;
    instr_mem[38]=8'h4;
    instr_mem[39]=8'h16;
    instr_mem[40]=8'h16;
    instr_mem[41]=8'h16;
    instr_mem[42]=8'h16;
    instr_mem[43]=8'h16;
    instr_mem[44]=8'h16;
    instr_mem[45]=8'h0;

  end  

  always@(posedge clk) 
  begin 

    imem_error=0;
    if(PC>1023)
    begin
      imem_error=1;
    end

    instr={
      instr_mem[PC],
      instr_mem[PC+1],
      instr_mem[PC+2],
      instr_mem[PC+3],
      instr_mem[PC+4],
      instr_mem[PC+5],
      instr_mem[PC+6],
      instr_mem[PC+7],
      instr_mem[PC+8],
      instr_mem[PC+9]
    };

    icode= instr[0:3];
    ifun= instr[4:7];

    instr_valid=1'b1;

    if(icode==4'b0000)
    begin
      hlt=1;
      valP=PC+64'd1;
    end
    else if(icode==4'b0001)
    begin
      valP=PC+64'd1;
    end
    else if(icode==4'b0010)
    begin
      rA=instr[8:11];
      rB=instr[12:15];
      valP=PC+64'd2;
    end
    else if(icode==4'b0011)
    begin
      rA=instr[8:11];
      rB=instr[12:15];
      valC=instr[16:79];
      valP=PC+64'd10;
    end
    else if(icode==4'b0100)
    begin
      rA=instr[8:11];
      rB=instr[12:15];
      valC=instr[16:79];
      valP=PC+64'd10;
    end
    else if(icode==4'b0101)
    begin
      rA=instr[8:11];
      rB=instr[12:15];
      valC=instr[16:79];
      valP=PC+64'd10;
    end
    else if(icode==4'b0110)
    begin
      rA=instr[8:11];
      rB=instr[12:15];
      valP=PC+64'd2;
    end
    else if(icode==4'b0111)
    begin
      valC=instr[8:71];
      valP=PC+64'd9;
    end
    else if(icode==4'b1000)
    begin
      valC=instr[8:71];
      valP=PC+64'd9;
    end
    else if(icode==4'b1001)
    begin
      valP=PC+64'd1;
    end
    else if(icode==4'b1010)
    begin
      rA=instr[8:11];
      rB=instr[12:15];
      valP=PC+64'd2;
    end
    else if(icode==4'b1011)
    begin
      rA=instr[8:11];
      rB=instr[12:15];
      valP=PC+64'd2;
    end
    else 
    begin
      instr_valid=1'b0;
    end
  end

endmodule