data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/control_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/control_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\nalways #(PERIOD/2) clk10hz = ~clk10hz;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/control_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\nalways #(5*PERIOD) clk1hz = ~clk1hz;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/control_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #PERIOD rst = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/control_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n    #(5*PERIOD) req = 3\'b001;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/control_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n    #(10*PERIOD) req = 3\'b000;end\n    ^\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/control_tb.v:24: Cannot find file containing module: \'control\'\ncontrol u_control (\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/434840709/USTB_verilog_elevator/sim,data/full_repos/permissive/434840709/control\n             data/full_repos/permissive/434840709/USTB_verilog_elevator/sim,data/full_repos/permissive/434840709/control.v\n             data/full_repos/permissive/434840709/USTB_verilog_elevator/sim,data/full_repos/permissive/434840709/control.sv\n             control\n             control.v\n             control.sv\n             obj_dir/control\n             obj_dir/control.v\n             obj_dir/control.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_control;    


parameter PERIOD = 10;
parameter INIT  = 0;  


reg   clk10hz                              = 0 ;
reg   clk1hz                               = 0 ;
reg   rst                                  = 1 ;
reg   [2:0]  req                           = 0 ;


wire  [7:0]  curr_floor                    ;
wire  [3:0]  running_state                 ;
wire  [3:0]  door_state                    ;
wire  [3:0]  state                         ;

always #(PERIOD/2) clk10hz = ~clk10hz;
always #(5*PERIOD) clk1hz = ~clk1hz;

control u_control (
    .clk10hz                 ( clk10hz              ),
    .clk1hz                  ( clk1hz               ),
    .rst                     ( rst                  ),
    .req                     ( req            [2:0] ),

    .curr_floor              ( curr_floor     [7:0] ),
    .running_state           ( running_state  [3:0] ),
    .door_state              ( door_state     [3:0] ),
    .state                   ( state          [3:0] )
);

initial
begin
    #PERIOD rst = 0;
    req = 3'b100;
    #(5*PERIOD) req = 3'b001;
    #(10*PERIOD) req = 3'b000;end

endmodule
module tb_control;
    


parameter PERIOD = 10;
parameter INIT  = 0;  


reg   clk10hz                              = 0 ;
reg   clk1hz                               = 0 ;
reg   rst                                  = 1 ;
reg   [2:0]  req                           = 0 ;


wire  [7:0]  curr_floor                    ;
wire  [3:0]  running_state                 ;
wire  [3:0]  door_state                    ;
wire  [3:0]  state                         ;

always #(PERIOD/2) clk10hz = ~clk10hz;
always #(5*PERIOD) clk1hz = ~clk1hz;

control u_control (
    .clk10hz                 ( clk10hz              ),
    .clk1hz                  ( clk1hz               ),
    .rst                     ( rst                  ),
    .req                     ( req            [2:0] ),

    .curr_floor              ( curr_floor     [7:0] ),
    .running_state           ( running_state  [3:0] ),
    .door_state              ( door_state     [3:0] ),
    .state                   ( state          [3:0] )
);

initial
begin
    #PERIOD rst = 0;
    req = 3'b100;
    #(5*PERIOD) req = 3'b001;
    #(10*PERIOD) req = 3'b000;end

endmodule