data/full_repos/permissive/491934675/ECE251/Buffer/buffer_tb.v
1: b'%Error: data/full_repos/permissive/491934675/ECE251/Buffer/buffer_tb.v:1: Cannot find include file: 8bitbuffer.v\n`include "8bitbuffer.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/491934675/ECE251/Buffer,data/full_repos/permissive/491934675/8bitbuffer.v\n             data/full_repos/permissive/491934675/ECE251/Buffer,data/full_repos/permissive/491934675/8bitbuffer.v.v\n             data/full_repos/permissive/491934675/ECE251/Buffer,data/full_repos/permissive/491934675/8bitbuffer.v.sv\n             8bitbuffer.v\n             8bitbuffer.v.v\n             8bitbuffer.v.sv\n             obj_dir/8bitbuffer.v\n             obj_dir/8bitbuffer.v.v\n             obj_dir/8bitbuffer.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/491934675/ECE251/Buffer/buffer_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/491934675/ECE251/Buffer/buffer_tb.v:32: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("buffer_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/491934675/ECE251/Buffer/buffer_tb.v:33: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, test);\n    ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module test;


reg [7:0] in1, hold1;
reg clk, enable;
wire [7:0] data;

assign data = in1;

buffer8bit buffer1(data, enable, hold1);

initial begin
    clk = 1;
    enable = 1;
    in1 = 10;
    for(integer i = 0; i < 10; i=i+1)begin
        clk = ~clk;
        #10;
    end
    $finish;
end

always @(posedge clk ) begin
    enable = ~enable;
    in1 = in1+1;
end

initial begin
    $dumpfile("buffer_tb.vcd");
    $dumpvars(0, test);

    $display("finished");
end


endmodule
module test;



reg [7:0] in1, hold1;
reg clk, enable;
wire [7:0] data;

assign data = in1;

buffer8bit buffer1(data, enable, hold1);

initial begin
    clk = 1;
    enable = 1;
    in1 = 10;
    for(integer i = 0; i < 10; i=i+1)begin
        clk = ~clk;
        #10;
    end
    $finish;
end

always @(posedge clk ) begin
    enable = ~enable;
    in1 = in1+1;
end

initial begin
    $dumpfile("buffer_tb.vcd");
    $dumpvars(0, test);

    $display("finished");
end


endmodule