data/full_repos/permissive/482720319/reg_file.v
data/verilator_xmls/76f7a97b-2a29-4727-84c5-cd76a66d0243.xml
module RegFile(
      input [3:0] rw, rs1, rs2,
      input [15:0] WD,
      input RegWrite,
      output reg [15:0] rd1, rd2, rd3
); 

      reg [15:0] RegData [0:15];
      initial begin
            $readmemh("reg_init.mem", RegData);
      end

      always @(rs1, rs2, rw, RegWrite, WD) begin
            rd1 <= RegData[rs1];
            rd2 <= RegData[rs2];
            rd3 <= RegData[rw];
      
            if(RegWrite)
                  RegData[rw] <= WD;
            
            $writememh("reg_fin.mem", RegData);
      end

endmodule
module RegFile(
      input [3:0] rw, rs1, rs2,
      input [15:0] WD,
      input RegWrite,
      output reg [15:0] rd1, rd2, rd3
);
 

      reg [15:0] RegData [0:15];
      initial begin
            $readmemh("reg_init.mem", RegData);
      end

      always @(rs1, rs2, rw, RegWrite, WD) begin
            rd1 <= RegData[rs1];
            rd2 <= RegData[rs2];
            rd3 <= RegData[rw];
      
            if(RegWrite)
                  RegData[rw] <= WD;
            
            $writememh("reg_fin.mem", RegData);
      end

endmodule