data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n        forever #5 clk=~clk;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n           rst=1; #10;\n                  ^\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n           B=0; #10;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n                B = 9\'b111100000; #10;\n                                  ^\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n                B = 0; #10;\n                       ^\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n            #20;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n            B[2]=1; #10;   \n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n            B[4]=1; #10;    \n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n            B[3]=1; #10;   \n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n            B[1]=1; #10;   \n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n            B=0; #10;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n            B[0]=1; #10;  \n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n                B= 9\'b000100000; #10;\n                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n                B=0; #10;\n                     ^\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n            #20;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n            B[3]=1; #10;  \n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n            B[1]=1; #10;  \n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n            B[0]=1; #10;  \n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n            B=0; #10;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n                B= 9\'b110000000; #10;\n                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n                B=0; #10;\n                     ^\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n            B[8]=1; #10;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n            B=0; #10;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n            #20;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n            B[3]=1; #10;  \n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n            B[1]=1; #10;  \n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n            B[2]=1; #10;  \n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n            B[0]=1; #10;  \n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n            B=0; #10;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n            B= 9\'b001100000; #10;\n                             ^\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n            B=0; #10;\n                 ^\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n            #20;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n            B[1]=1; #10;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n            B=0; #10;\n                 ^\n%Error: data/full_repos/permissive/499596866/Simulation/sim_1/new/tb.v:14: Cannot find file containing module: \'calculator\'\n    calculator dut(clk, rst, B, result, n1, n2, mode, neg, out1, out2, out3, out4, out5, out6, out7, out8);\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/499596866/Simulation/sim_1/new,data/full_repos/permissive/499596866/calculator\n             data/full_repos/permissive/499596866/Simulation/sim_1/new,data/full_repos/permissive/499596866/calculator.v\n             data/full_repos/permissive/499596866/Simulation/sim_1/new,data/full_repos/permissive/499596866/calculator.sv\n             calculator\n             calculator.v\n             calculator.sv\n             obj_dir/calculator\n             obj_dir/calculator.v\n             obj_dir/calculator.sv\n%Error: Exiting due to 1 error(s), 34 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module calc_tb();
    reg clk, rst;
    reg [8:0] B;
    wire  [13:0] result;
    integer i;
    wire  [6:0] n1, n2;
    wire mode;
    wire neg;
    wire [7:0] out1, out2, out3, out4, out5, out6, out7, out8;

    
    calculator dut(clk, rst, B, result, n1, n2, mode, neg, out1, out2, out3, out4, out5, out6, out7, out8);
    
    initial begin
        clk=0;
        forever #5 clk=~clk;
    end
    
    initial begin
           rst=1; #10;
           rst=0;
           B=0; #10;
           B[0]=1;
            for(i=0;i<9;i=i+1) begin
                B = 9'b111100000; #10;
                B = 0; #10;
            end
            #20;
            B[2]=1; #10;
            B[2]=0;
            B[4]=1; #10;
            B[4]=0;
            B[3]=1; #10;
            B[3]=0;
            B[1]=1; #10;
            B[1]=0;
            B=0; #10;
            B[0]=1; #10;
    

            for(i=0;i<9;i=i+1) begin
                B= 9'b000100000; #10;
                B=0; #10;
            end
            #20;
            B[3]=1; #10;
            B[3]=0;
            B[1]=1; #10;
            B[1]=0;
            B[0]=1; #10;
            B=0; #10;

            for(i=0;i<3;i=i+1) begin
                B= 9'b110000000; #10;
                B=0; #10;
            end
            B[8]=1; #10;
            B=0; #10;
            #20;
            B[3]=1; #10;
            B[3]=0;
            B[1]=1; #10;
            B[1]=0;
            B[2]=1; #10;
            B[2]=0;
            B[0]=1; #10;
            B=0; #10;

            for(i=0;i<2;i=i+1) begin
            B= 9'b001100000; #10;
            B=0; #10;
            end
            #20;
            B[1]=1; #10;
            B[1]=0;
            B=0; #10;
    
    end
          
endmodule
module calc_tb();

    reg clk, rst;
    reg [8:0] B;
    wire  [13:0] result;
    integer i;
    wire  [6:0] n1, n2;
    wire mode;
    wire neg;
    wire [7:0] out1, out2, out3, out4, out5, out6, out7, out8;

    
    calculator dut(clk, rst, B, result, n1, n2, mode, neg, out1, out2, out3, out4, out5, out6, out7, out8);
    
    initial begin
        clk=0;
        forever #5 clk=~clk;
    end
    
    initial begin
           rst=1; #10;
           rst=0;
           B=0; #10;
           B[0]=1;
            for(i=0;i<9;i=i+1) begin
                B = 9'b111100000; #10;
                B = 0; #10;
            end
            #20;
            B[2]=1; #10;
            B[2]=0;
            B[4]=1; #10;
            B[4]=0;
            B[3]=1; #10;
            B[3]=0;
            B[1]=1; #10;
            B[1]=0;
            B=0; #10;
            B[0]=1; #10;
    

            for(i=0;i<9;i=i+1) begin
                B= 9'b000100000; #10;
                B=0; #10;
            end
            #20;
            B[3]=1; #10;
            B[3]=0;
            B[1]=1; #10;
            B[1]=0;
            B[0]=1; #10;
            B=0; #10;

            for(i=0;i<3;i=i+1) begin
                B= 9'b110000000; #10;
                B=0; #10;
            end
            B[8]=1; #10;
            B=0; #10;
            #20;
            B[3]=1; #10;
            B[3]=0;
            B[1]=1; #10;
            B[1]=0;
            B[2]=1; #10;
            B[2]=0;
            B[0]=1; #10;
            B=0; #10;

            for(i=0;i<2;i=i+1) begin
            B= 9'b001100000; #10;
            B=0; #10;
            end
            #20;
            B[1]=1; #10;
            B[1]=0;
            B=0; #10;
    
    end
          
endmodule