data/full_repos/permissive/418819021/lab-07/rom.v
data/verilator_xmls/e544879d-0614-400c-85ab-1067fcf9426e.xml
module rom #(
    parameter DATA_WIDTH = 16,
    parameter ADDR_WIDTH = 8
) (
    input  wire                      clk ,
    input  wire     [ADDR_WIDTH-1:0] addr,
    output      reg [DATA_WIDTH-1:0] data
);

    reg [DATA_WIDTH-1:0] value;

    always @* begin
        case (addr)

            0       : value = 16'b1110100000000011;

            1       : value = 16'b1011101100001001;

            2       : value = 16'b1110000000001001;

            3       : value = 16'b1011101100001000;

            4       : value = 16'b1110000000000111;

            5       : value = 16'b1011101100000110;
            default : value = 16'b0000000000000000;
        endcase
    end
    always @(negedge clk) begin
        data <= value;
    end

endmodule
module rom #(
    parameter DATA_WIDTH = 16,
    parameter ADDR_WIDTH = 8
) (
    input  wire                      clk ,
    input  wire     [ADDR_WIDTH-1:0] addr,
    output      reg [DATA_WIDTH-1:0] data
);


    reg [DATA_WIDTH-1:0] value;

    always @* begin
        case (addr)

            0       : value = 16'b1110100000000011;

            1       : value = 16'b1011101100001001;

            2       : value = 16'b1110000000001001;

            3       : value = 16'b1011101100001000;

            4       : value = 16'b1110000000000111;

            5       : value = 16'b1011101100000110;
            default : value = 16'b0000000000000000;
        endcase
    end
    always @(negedge clk) begin
        data <= value;
    end

endmodule