data/full_repos/permissive/507203156/03-源代码/sift_tb/tf_block2_27.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb/tf_block2_27.v:89: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb/tf_block2_27.v:100: Unsupported: Ignoring delay on this delayed statement.\n #5 clk=~clk;\n ^\n%Error: data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb/tf_block2_27.v:44: Cannot find file containing module: \'block2_27extreme\'\n block2_27extreme uut (\n ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb,data/full_repos/permissive/507203156/block2_27extreme\n             data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb,data/full_repos/permissive/507203156/block2_27extreme.v\n             data/full_repos/permissive/507203156/03-\xe6\xba\x90\xe4\xbb\xa3\xe7\xa0\x81/sift_tb,data/full_repos/permissive/507203156/block2_27extreme.sv\n             block2_27extreme\n             block2_27extreme.v\n             block2_27extreme.sv\n             obj_dir/block2_27extreme\n             obj_dir/block2_27extreme.v\n             obj_dir/block2_27extreme.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tf_block2_27;


	reg clk;
	reg rst;
	reg [7:0] diff0;
	reg [7:0] diff1;
	reg [7:0] diff2;


	wire [7:0] dout11;
	wire [7:0] dout12;
	wire [7:0] dout13;
	wire [7:0] dout14;
	wire [7:0] dout15;
	wire [7:0] dout16;
	wire [7:0] dout17;
	wire [7:0] dout18;
	wire [7:0] dout19;
	wire [7:0] dout21;
	wire [7:0] dout22;
	wire [7:0] dout23;
	wire [7:0] dout24;
	wire [7:0] dout25;
	wire [7:0] dout26;
	wire [7:0] dout27;
	wire [7:0] dout28;
	wire [7:0] dout29;
	wire [7:0] dout31;
	wire [7:0] dout32;
	wire [7:0] dout33;
	wire [7:0] dout34;
	wire [7:0] dout35;
	wire [7:0] dout36;
	wire [7:0] dout37;
	wire [7:0] dout38;
	wire [7:0] dout39;
	wire out_en;


	block2_27extreme uut (
		.clk(clk), 
		.rst(rst), 
		.diff0(diff0), 
		.diff1(diff1), 
		.diff2(diff2), 
		.dout11(dout11), 
		.dout12(dout12), 
		.dout13(dout13), 
		.dout14(dout14), 
		.dout15(dout15), 
		.dout16(dout16), 
		.dout17(dout17), 
		.dout18(dout18), 
		.dout19(dout19), 
		.dout21(dout21), 
		.dout22(dout22), 
		.dout23(dout23), 
		.dout24(dout24), 
		.dout25(dout25), 
		.dout26(dout26), 
		.dout27(dout27), 
		.dout28(dout28), 
		.dout29(dout29), 
		.dout31(dout31), 
		.dout32(dout32), 
		.dout33(dout33), 
		.dout34(dout34), 
		.dout35(dout35), 
		.dout36(dout36), 
		.dout37(dout37), 
		.dout38(dout38), 
		.dout39(dout39), 
		.out_en(out_en)
	);

	initial begin

		clk = 0;
		rst = 0;
		diff0 = 0;
		diff1 = 0;
		diff2 = 0;


		#100;
		
		rst=1;
      diff0=0;
		diff1=0;
		diff2=0;


	end
	
	always
	#5 clk=~clk;
	
	always @(posedge clk)
	begin
		diff0=diff0+1;
		diff1=diff1+1;
		diff2=diff2+1;
	end
      
endmodule
module tf_block2_27;



	reg clk;
	reg rst;
	reg [7:0] diff0;
	reg [7:0] diff1;
	reg [7:0] diff2;


	wire [7:0] dout11;
	wire [7:0] dout12;
	wire [7:0] dout13;
	wire [7:0] dout14;
	wire [7:0] dout15;
	wire [7:0] dout16;
	wire [7:0] dout17;
	wire [7:0] dout18;
	wire [7:0] dout19;
	wire [7:0] dout21;
	wire [7:0] dout22;
	wire [7:0] dout23;
	wire [7:0] dout24;
	wire [7:0] dout25;
	wire [7:0] dout26;
	wire [7:0] dout27;
	wire [7:0] dout28;
	wire [7:0] dout29;
	wire [7:0] dout31;
	wire [7:0] dout32;
	wire [7:0] dout33;
	wire [7:0] dout34;
	wire [7:0] dout35;
	wire [7:0] dout36;
	wire [7:0] dout37;
	wire [7:0] dout38;
	wire [7:0] dout39;
	wire out_en;


	block2_27extreme uut (
		.clk(clk), 
		.rst(rst), 
		.diff0(diff0), 
		.diff1(diff1), 
		.diff2(diff2), 
		.dout11(dout11), 
		.dout12(dout12), 
		.dout13(dout13), 
		.dout14(dout14), 
		.dout15(dout15), 
		.dout16(dout16), 
		.dout17(dout17), 
		.dout18(dout18), 
		.dout19(dout19), 
		.dout21(dout21), 
		.dout22(dout22), 
		.dout23(dout23), 
		.dout24(dout24), 
		.dout25(dout25), 
		.dout26(dout26), 
		.dout27(dout27), 
		.dout28(dout28), 
		.dout29(dout29), 
		.dout31(dout31), 
		.dout32(dout32), 
		.dout33(dout33), 
		.dout34(dout34), 
		.dout35(dout35), 
		.dout36(dout36), 
		.dout37(dout37), 
		.dout38(dout38), 
		.dout39(dout39), 
		.out_en(out_en)
	);

	initial begin

		clk = 0;
		rst = 0;
		diff0 = 0;
		diff1 = 0;
		diff2 = 0;


		#100;
		
		rst=1;
      diff0=0;
		diff1=0;
		diff2=0;


	end
	
	always
	#5 clk=~clk;
	
	always @(posedge clk)
	begin
		diff0=diff0+1;
		diff1=diff1+1;
		diff2=diff2+1;
	end
      
endmodule