data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/pipectrl.v
1: b"%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/pipectrl.v:39: Cannot find file containing module: 'pipestage'\n   pipestage #(.TAGWIDTH(TAGWIDTH)) head\n   ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib,data/full_repos/permissive/447976230/pipestage\n             data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib,data/full_repos/permissive/447976230/pipestage.v\n             data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib,data/full_repos/permissive/447976230/pipestage.sv\n             pipestage\n             pipestage.v\n             pipestage.sv\n             obj_dir/pipestage\n             obj_dir/pipestage.v\n             obj_dir/pipestage.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/pipectrl.v:55: Cannot find file containing module: 'pipestage'\n   pipestage #(.TAGWIDTH(TAGWIDTH)) tail\n   ^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module pipectrl
  #(parameter STAGES = 2, 
    parameter TAGWIDTH = 1)
   (input clk,
    input reset,
    input src_rdy_i,
    output dst_rdy_o,
    output src_rdy_o,
    input dst_rdy_i,
    output [STAGES-1:0] strobes,
    output [STAGES-1:0] valids,
    input [TAGWIDTH-1:0] tag_i,
    output [TAGWIDTH-1:0] tag_o);

   wire 		new_input = src_rdy_i & dst_rdy_o;
   wire 		new_output = src_rdy_o & dst_rdy_i;
   wire [TAGWIDTH-1:0] 	tags [STAGES-1:0];

   assign dst_rdy_o = ~valids[0] | strobes[1];

   pipestage #(.TAGWIDTH(TAGWIDTH)) head
     (.clk(clk),.reset(reset), .stb_in(strobes[0]), .stb_out(strobes[1]),.valid(valids[0]),
      .tag_in(tag_i), .tag_out(tags[0]));
   assign strobes[0] = src_rdy_i & (~valids[0] | strobes[1]);

   genvar 		i;
   generate
      for(i = 1; i < STAGES - 1; i = i + 1)
	begin : gen_stages
	   pipestage #(.TAGWIDTH(TAGWIDTH)) pipestage
	     (.clk(clk),.reset(reset), .stb_in(strobes[i]),.stb_out(strobes[i+1]),.valid(valids[i]),
	      .tag_in(tags[i-1]),.tag_out(tags[i]));
	   assign strobes[i] = valids[i-1] & (~valids[i] | strobes[i+1]);
	end
   endgenerate

   pipestage #(.TAGWIDTH(TAGWIDTH)) tail
     (.clk(clk),.reset(reset), .stb_in(strobes[STAGES-1]), .stb_out(dst_rdy_i),.valid(valids[STAGES-1]),
      .tag_in(tags[STAGES-2]), .tag_out(tags[STAGES-1]));
   assign strobes[STAGES-1] = valids[STAGES-2] & (~valids[STAGES-1] | new_output);
   
   assign src_rdy_o = valids[STAGES-1];

   assign tag_o = tags[STAGES-1];
   
endmodule
module pipectrl
  #(parameter STAGES = 2, 
    parameter TAGWIDTH = 1)
   (input clk,
    input reset,
    input src_rdy_i,
    output dst_rdy_o,
    output src_rdy_o,
    input dst_rdy_i,
    output [STAGES-1:0] strobes,
    output [STAGES-1:0] valids,
    input [TAGWIDTH-1:0] tag_i,
    output [TAGWIDTH-1:0] tag_o);


   wire 		new_input = src_rdy_i & dst_rdy_o;
   wire 		new_output = src_rdy_o & dst_rdy_i;
   wire [TAGWIDTH-1:0] 	tags [STAGES-1:0];

   assign dst_rdy_o = ~valids[0] | strobes[1];

   pipestage #(.TAGWIDTH(TAGWIDTH)) head
     (.clk(clk),.reset(reset), .stb_in(strobes[0]), .stb_out(strobes[1]),.valid(valids[0]),
      .tag_in(tag_i), .tag_out(tags[0]));
   assign strobes[0] = src_rdy_i & (~valids[0] | strobes[1]);

   genvar 		i;
   generate
      for(i = 1; i < STAGES - 1; i = i + 1)
	begin : gen_stages
	   pipestage #(.TAGWIDTH(TAGWIDTH)) pipestage
	     (.clk(clk),.reset(reset), .stb_in(strobes[i]),.stb_out(strobes[i+1]),.valid(valids[i]),
	      .tag_in(tags[i-1]),.tag_out(tags[i]));
	   assign strobes[i] = valids[i-1] & (~valids[i] | strobes[i+1]);
	end
   endgenerate

   pipestage #(.TAGWIDTH(TAGWIDTH)) tail
     (.clk(clk),.reset(reset), .stb_in(strobes[STAGES-1]), .stb_out(dst_rdy_i),.valid(valids[STAGES-1]),
      .tag_in(tags[STAGES-2]), .tag_out(tags[STAGES-1]));
   assign strobes[STAGES-1] = valids[STAGES-2] & (~valids[STAGES-1] | new_output);
   
   assign src_rdy_o = valids[STAGES-1];

   assign tag_o = tags[STAGES-1];
   
endmodule