data/full_repos/permissive/518306310/iiitb_3bit_rc_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/518306310/iiitb_3bit_rc_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n  #1000 $finish;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/518306310/iiitb_3bit_rc_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: data/full_repos/permissive/518306310/iiitb_3bit_rc_tb.v:20: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("iiitb_3bit_rr_out.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/518306310/iiitb_3bit_rc_tb.v:21: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, iiitb_3bit_rc_tb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/518306310/iiitb_3bit_rc_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/518306310/iiitb_3bit_rc_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #200;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/518306310/iiitb_3bit_rc_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #20\n  ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module iiitb_3bit_rc_tb;
	reg clk;
	reg ori;
	wire [2:0] count;
	iiitb_3bit_rc rc(clk, ori, count);
	initial
	begin
		clk = 0;
		ori = 1;
		#1000 $finish;
	end
	always
	begin
		#10;
		clk = ~clk;
	end
	initial
	begin
		$dumpfile("iiitb_3bit_rr_out.vcd");
		$dumpvars(0, iiitb_3bit_rc_tb);
		#20
		ori = 0;
		#200;
		ori = 1;
		#20
		ori = 0;
	end
endmodule
module iiitb_3bit_rc_tb;

	reg clk;
	reg ori;
	wire [2:0] count;
	iiitb_3bit_rc rc(clk, ori, count);
	initial
	begin
		clk = 0;
		ori = 1;
		#1000 $finish;
	end
	always
	begin
		#10;
		clk = ~clk;
	end
	initial
	begin
		$dumpfile("iiitb_3bit_rr_out.vcd");
		$dumpvars(0, iiitb_3bit_rc_tb);
		#20
		ori = 0;
		#200;
		ori = 1;
		#20
		ori = 0;
	end
endmodule