data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dsp_core_rx_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dsp_core_rx_tb.v:8: Unsupported: Ignoring delay on this delayed statement.\n   initial #1000 rst = 0;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dsp_core_rx_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n   always #5 clk = ~clk;\n          ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dsp_core_rx_tb.v:12: Unsupported or unknown PLI call: $dumpfile\n   initial $dumpfile("ddc_chain_tb.vcd");\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dsp_core_rx_tb.v:13: Unsupported or unknown PLI call: $dumpvars\n   initial $dumpvars(0,ddc_chain_tb);\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dsp_core_rx_tb.v:41: syntax error, unexpected \'@\'\n @(negedge rst);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dsp_core_rx_tb.v:46: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dsp_core_rx_tb.v:50: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dsp_core_rx_tb.v:55: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/dsp_core_rx_tb.v:57: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: Exiting due to 7 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ddc_chain_tb();
   
   reg clk, rst;

   initial rst = 1;
   initial #1000 rst = 0;
   initial clk = 0;
   always #5 clk = ~clk;
   
   initial $dumpfile("ddc_chain_tb.vcd");
   initial $dumpvars(0,ddc_chain_tb);
   
   reg signed [23:0] adc_in;
   wire signed [15:0] adc_out_i, adc_out_q;

   always @(posedge clk)
     begin
	$display(adc_in);
	$display(adc_out_i);
	$display(adc_out_q);
     end	

   reg run;
   reg set_stb;
   reg [7:0] set_addr;
   reg [31:0] set_data;
   
   ddc_chain #(.BASE(0)) ddc_chain
     (.clk(clk),.rst(rst),
      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
      .adc_i(adc_in), .adc_ovf_i(0),
      .adc_q(0), .adc_ovf_q(0),
      .sample({adc_out_i,adc_out_q}),
      .run(run), .strobe(), .debug());

   initial
     begin
	run <= 0;
	@(negedge rst);
	@(posedge clk);
	set_addr <= 1;
	set_data <= {16'd64,16'd64};
	set_stb <= 1;
	@(posedge clk);
	set_addr <= 2;
	set_data <= {16'd0,8'd3,8'd1};
	set_stb <= 1;
	@(posedge clk);
	set_addr <= 0;

	set_data <= {32'h01CA_C083};
	set_stb <= 1;
	@(posedge clk);
	set_stb <= 0;
	@(posedge clk);
	run <= 1;
     end

   always @(posedge clk)

     adc_in <= 24'h80_0000;
   

endmodule
module ddc_chain_tb();

   
   reg clk, rst;

   initial rst = 1;
   initial #1000 rst = 0;
   initial clk = 0;
   always #5 clk = ~clk;
   
   initial $dumpfile("ddc_chain_tb.vcd");
   initial $dumpvars(0,ddc_chain_tb);
   
   reg signed [23:0] adc_in;
   wire signed [15:0] adc_out_i, adc_out_q;

   always @(posedge clk)
     begin
	$display(adc_in);
	$display(adc_out_i);
	$display(adc_out_q);
     end	

   reg run;
   reg set_stb;
   reg [7:0] set_addr;
   reg [31:0] set_data;
   
   ddc_chain #(.BASE(0)) ddc_chain
     (.clk(clk),.rst(rst),
      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
      .adc_i(adc_in), .adc_ovf_i(0),
      .adc_q(0), .adc_ovf_q(0),
      .sample({adc_out_i,adc_out_q}),
      .run(run), .strobe(), .debug());

   initial
     begin
	run <= 0;
	@(negedge rst);
	@(posedge clk);
	set_addr <= 1;
	set_data <= {16'd64,16'd64};
	set_stb <= 1;
	@(posedge clk);
	set_addr <= 2;
	set_data <= {16'd0,8'd3,8'd1};
	set_stb <= 1;
	@(posedge clk);
	set_addr <= 0;

	set_data <= {32'h01CA_C083};
	set_stb <= 1;
	@(posedge clk);
	set_stb <= 0;
	@(posedge clk);
	run <= 1;
     end

   always @(posedge clk)

     adc_in <= 24'h80_0000;
   

endmodule