data/full_repos/permissive/492462267/mem_wb.v
1: b'%Error: data/full_repos/permissive/492462267/mem_wb.v:1: Cannot find include file: define.vh\n`include "define.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh.v\n             data/full_repos/permissive/492462267,data/full_repos/permissive/492462267/define.vh.sv\n             define.vh\n             define.vh.v\n             define.vh.sv\n             obj_dir/define.vh\n             obj_dir/define.vh.v\n             obj_dir/define.vh.sv\n%Error: data/full_repos/permissive/492462267/mem_wb.v:17: Define or directive not defined: \'`RegAddrBus\'\n    input   wire[`RegAddrBus]   mem_waddr,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/mem_wb.v:17: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input   wire[`RegAddrBus]   mem_waddr,\n                            ^\n%Error: data/full_repos/permissive/492462267/mem_wb.v:18: Define or directive not defined: \'`RegDataBus\'\n    input   wire[`RegDataBus]   mem_result,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/mem_wb.v:19: Define or directive not defined: \'`RegDataBus\'\n    input   wire[`RegDataBus]   mem_hi,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/mem_wb.v:20: Define or directive not defined: \'`RegDataBus\'\n    input   wire[`RegDataBus]   mem_lo,\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/mem_wb.v:24: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output  reg                 wb_we,\n    ^~~~~~\n%Error: data/full_repos/permissive/492462267/mem_wb.v:25: syntax error, unexpected output, expecting IDENTIFIER or \'=\' or do or final\n    output  reg[`RegAddrBus]    wb_waddr,\n    ^~~~~~\n%Error: data/full_repos/permissive/492462267/mem_wb.v:25: Define or directive not defined: \'`RegAddrBus\'\n    output  reg[`RegAddrBus]    wb_waddr,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/mem_wb.v:26: Define or directive not defined: \'`RegDataBus\'\n    output  reg[`RegDataBus]    wb_result,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/mem_wb.v:27: Define or directive not defined: \'`RegDataBus\'\n    output  reg[`RegDataBus]    wb_hi,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/mem_wb.v:28: Define or directive not defined: \'`RegDataBus\'\n    output  reg[`RegDataBus]    wb_lo,\n                ^~~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/mem_wb.v:34: Define or directive not defined: \'`Disable\'\n        wb_we      <= `Disable;\n                      ^~~~~~~~\n%Error: data/full_repos/permissive/492462267/mem_wb.v:35: Define or directive not defined: \'`RegAddr_0\'\n        wb_waddr   <= `RegAddr_0;\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/mem_wb.v:36: Define or directive not defined: \'`ZeroWord\'\n        wb_result  <= `ZeroWord;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/mem_wb.v:37: Define or directive not defined: \'`ZeroWord\'\n        wb_hi      <= `ZeroWord;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/mem_wb.v:38: Define or directive not defined: \'`ZeroWord\'\n        wb_lo      <= `ZeroWord;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/mem_wb.v:39: Define or directive not defined: \'`Disable\'\n        wb_whilo   <= `Disable;\n                      ^~~~~~~~\n%Error: data/full_repos/permissive/492462267/mem_wb.v:45: Define or directive not defined: \'`Disable\'\n        wb_we      <= `Disable;\n                      ^~~~~~~~\n%Error: data/full_repos/permissive/492462267/mem_wb.v:46: Define or directive not defined: \'`RegAddr_0\'\n        wb_waddr   <= `RegAddr_0;\n                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/492462267/mem_wb.v:47: Define or directive not defined: \'`ZeroWord\'\n        wb_result  <= `ZeroWord;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/mem_wb.v:48: Define or directive not defined: \'`ZeroWord\'\n        wb_hi      <= `ZeroWord;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/mem_wb.v:49: Define or directive not defined: \'`ZeroWord\'\n        wb_lo      <= `ZeroWord;\n                      ^~~~~~~~~\n%Error: data/full_repos/permissive/492462267/mem_wb.v:50: Define or directive not defined: \'`Disable\'\n        wb_whilo   <= `Disable;\n                      ^~~~~~~~\n%Error: Exiting due to 24 error(s)\n'
module mem_wb (
    input   wire    clk,
    input   wire    rst,

    input   wire[5:0]   stall,


    input   wire                mem_we,
    input   wire[`RegAddrBus]   mem_waddr,
    input   wire[`RegDataBus]   mem_result,
    input   wire[`RegDataBus]   mem_hi,
    input   wire[`RegDataBus]   mem_lo,
    input   wire                mem_whilo,


    output  reg                 wb_we,
    output  reg[`RegAddrBus]    wb_waddr,
    output  reg[`RegDataBus]    wb_result,
    output  reg[`RegDataBus]    wb_hi,
    output  reg[`RegDataBus]    wb_lo,
    output  reg                 wb_whilo
);

always @(posedge clk ) begin
    if(rst) begin
        wb_we      <= `Disable;
        wb_waddr   <= `RegAddr_0;
        wb_result  <= `ZeroWord;
        wb_hi      <= `ZeroWord;
        wb_lo      <= `ZeroWord;
        wb_whilo   <= `Disable;
    end 

    else if(stall[4] && !stall[5])begin
        wb_we      <= `Disable;
        wb_waddr   <= `RegAddr_0;
        wb_result  <= `ZeroWord;
        wb_hi      <= `ZeroWord;
        wb_lo      <= `ZeroWord;
        wb_whilo   <= `Disable;
    end

    else if(!stall[4]) begin
        wb_we      <= mem_we;
        wb_waddr   <= mem_waddr;
        wb_result  <= mem_result;
        wb_hi      <= mem_hi;
        wb_lo      <= mem_lo;
        wb_whilo   <= mem_whilo;
    end else begin
        wb_we      <= wb_we;
        wb_waddr   <= wb_waddr;
        wb_result  <= wb_result;
        wb_hi      <= wb_hi;
        wb_lo      <= wb_lo;
        wb_whilo   <= wb_whilo;
    end
end

endmodule
module mem_wb (
    input   wire    clk,
    input   wire    rst,

    input   wire[5:0]   stall,


    input   wire                mem_we,
    input   wire[`RegAddrBus]   mem_waddr,
    input   wire[`RegDataBus]   mem_result,
    input   wire[`RegDataBus]   mem_hi,
    input   wire[`RegDataBus]   mem_lo,
    input   wire                mem_whilo,


    output  reg                 wb_we,
    output  reg[`RegAddrBus]    wb_waddr,
    output  reg[`RegDataBus]    wb_result,
    output  reg[`RegDataBus]    wb_hi,
    output  reg[`RegDataBus]    wb_lo,
    output  reg                 wb_whilo
);


always @(posedge clk ) begin
    if(rst) begin
        wb_we      <= `Disable;
        wb_waddr   <= `RegAddr_0;
        wb_result  <= `ZeroWord;
        wb_hi      <= `ZeroWord;
        wb_lo      <= `ZeroWord;
        wb_whilo   <= `Disable;
    end 

    else if(stall[4] && !stall[5])begin
        wb_we      <= `Disable;
        wb_waddr   <= `RegAddr_0;
        wb_result  <= `ZeroWord;
        wb_hi      <= `ZeroWord;
        wb_lo      <= `ZeroWord;
        wb_whilo   <= `Disable;
    end

    else if(!stall[4]) begin
        wb_we      <= mem_we;
        wb_waddr   <= mem_waddr;
        wb_result  <= mem_result;
        wb_hi      <= mem_hi;
        wb_lo      <= mem_lo;
        wb_whilo   <= mem_whilo;
    end else begin
        wb_we      <= wb_we;
        wb_waddr   <= wb_waddr;
        wb_result  <= wb_result;
        wb_hi      <= wb_hi;
        wb_lo      <= wb_lo;
        wb_whilo   <= wb_whilo;
    end
end

endmodule