data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/array112x.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/array112x.v:27: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n        ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n     do\n     ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/array112x.v:48: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\noutput [WIDTH-1:0]  do;      \n                    ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/array112x.v:56: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\nwire [WIDTH-1:0]    do;      \n                    ^~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/lib/atvn/lib_v/sim/array112x.v:83: syntax error, unexpected do, expecting TYPE-IDENTIFIER\nassign do   = ido;\n       ^~\n%Error: Exiting due to 4 error(s)\n"
module array112x
    (
     rst_,
     wclk,
     wa,
     we,
     di,
     rclk,
     ra,
     do
     );



parameter ADDRBIT = 5;
parameter DEPTH = 32;
parameter WIDTH = 32;
parameter TYPE = "AUTO";
parameter MAXDEPTH = 0;
parameter MEM_RESET = "OFF";



input               rst_;
input               wclk;
input [ADDRBIT-1:0] wa;
input               we;
input [WIDTH-1:0]   di;
input               rclk;
input [ADDRBIT-1:0] ra;
output [WIDTH-1:0]  do;

reg [ADDRBIT-1:0]   iwa;
reg                 iwe;
reg [WIDTH-1:0]     idi;
reg [ADDRBIT-1:0]   ira;

wire [WIDTH-1:0]    ido;
wire [WIDTH-1:0]    do;



always @ (posedge wclk or negedge rst_)
    if (~rst_)
        begin
        iwa <= {ADDRBIT{1'b0}};
        iwe <= 1'b0;
        idi <= {WIDTH{1'b0}};
        end
    else
        begin
        iwa <= wa;
        iwe <= we;
        idi <= di;
        end



always @ (posedge rclk or negedge rst_)
    if (~rst_)
        ira <= {ADDRBIT{1'b0}};
    else
        ira <= ra;


assign do   = ido;


array111x #(ADDRBIT,DEPTH,WIDTH) array (rst_,wclk,iwa,iwe,idi,rclk,ira,ido);

endmodule
module array112x
    (
     rst_,
     wclk,
     wa,
     we,
     di,
     rclk,
     ra,
     do
     );




parameter ADDRBIT = 5;
parameter DEPTH = 32;
parameter WIDTH = 32;
parameter TYPE = "AUTO";
parameter MAXDEPTH = 0;
parameter MEM_RESET = "OFF";



input               rst_;
input               wclk;
input [ADDRBIT-1:0] wa;
input               we;
input [WIDTH-1:0]   di;
input               rclk;
input [ADDRBIT-1:0] ra;
output [WIDTH-1:0]  do;

reg [ADDRBIT-1:0]   iwa;
reg                 iwe;
reg [WIDTH-1:0]     idi;
reg [ADDRBIT-1:0]   ira;

wire [WIDTH-1:0]    ido;
wire [WIDTH-1:0]    do;



always @ (posedge wclk or negedge rst_)
    if (~rst_)
        begin
        iwa <= {ADDRBIT{1'b0}};
        iwe <= 1'b0;
        idi <= {WIDTH{1'b0}};
        end
    else
        begin
        iwa <= wa;
        iwe <= we;
        idi <= di;
        end



always @ (posedge rclk or negedge rst_)
    if (~rst_)
        ira <= {ADDRBIT{1'b0}};
    else
        ira <= ra;


assign do   = ido;


array111x #(ADDRBIT,DEPTH,WIDTH) array (rst_,wclk,iwa,iwe,idi,rclk,ira,ido);

endmodule