data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #SPI_CSN_DELAY spi_cs_addr = 0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:44: Unsupported: Ignoring delay on this delayed statement.\n            #SPI_SCL_DELAY spi_scl = 1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:45: Unsupported: Ignoring delay on this delayed statement.\n            #SPI_SCL_DELAY spi_scl = 0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #SPI_CSN_DELAY spi_cs_addr = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:57: Unsupported: Ignoring delay on this delayed statement.\n        #SPI_CSN_DELAY spi_cs_data = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:61: Unsupported: Ignoring delay on this delayed statement.\n            #SPI_SCL_DELAY spi_scl = 1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:62: Unsupported: Ignoring delay on this delayed statement.\n            #SPI_SCL_DELAY spi_scl = 0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:64: Unsupported: Ignoring delay on this delayed statement.\n        #SPI_CSN_DELAY spi_cs_data = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:74: Unsupported: Ignoring delay on this delayed statement.\n        #SPI_CSN_DELAY spi_cs_data = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:78: Unsupported: Ignoring delay on this delayed statement.\n            #SPI_SCL_DELAY spi_scl = 1;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:80: Unsupported: Ignoring delay on this delayed statement.\n            #SPI_SCL_DELAY spi_scl = 0;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:83: Unsupported: Ignoring delay on this delayed statement.\n        #SPI_CSN_DELAY spi_cs_data = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:92: Unsupported: Ignoring delay on this delayed statement.\nalways #10 clk = ~ clk;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:105: Unsupported: Ignoring delay on this delayed statement.\n#100\n^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:108: Unsupported: Ignoring delay on this delayed statement.\n    #100 masterSendAddr(8\'d8);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:109: Unsupported: Ignoring delay on this delayed statement.\n    #100 masterSendData(16\'d1);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:116: Unsupported: Ignoring delay on this delayed statement.\n        #100 masterSendAddr(8\'d1);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:117: Unsupported: Ignoring delay on this delayed statement.\n        #100 masterSendData(data[0]);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:118: Unsupported: Ignoring delay on this delayed statement.\n        #100 masterSendAddr(8\'d2);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:119: Unsupported: Ignoring delay on this delayed statement.\n        #100 masterSendData(data[1]);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:120: Unsupported: Ignoring delay on this delayed statement.\n        #100 masterSendAddr(8\'d3);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:121: Unsupported: Ignoring delay on this delayed statement.\n        #100 masterSendData(data[2]);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:122: Unsupported: Ignoring delay on this delayed statement.\n        #100 masterSendAddr(8\'d128);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:123: Unsupported: Ignoring delay on this delayed statement.\n        #100 masterRece(r_rece);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:138: Unsupported: Ignoring delay on this delayed statement.\n    #100 masterSendAddr(8\'d4);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:141: Unsupported: Ignoring delay on this delayed statement.\n        #100 masterSendData(data[0]);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:144: Unsupported: Ignoring delay on this delayed statement.\n    #100 masterSendAddr(8\'d132);\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:146: Unsupported: Ignoring delay on this delayed statement.\n        #100 masterRece(r_rece);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:160: Unsupported: Ignoring delay on this delayed statement.\n        #100 masterSendAddr(8\'d5);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:161: Unsupported: Ignoring delay on this delayed statement.\n        #100 masterSendData(i);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:162: Unsupported: Ignoring delay on this delayed statement.\n        #100 masterSendAddr(8\'d7);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:164: Unsupported: Ignoring delay on this delayed statement.\n        #100 masterSendData(data[0]);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:168: Unsupported: Ignoring delay on this delayed statement.\n        #100 masterSendAddr(8\'d6);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:169: Unsupported: Ignoring delay on this delayed statement.\n        #100 masterSendData(9-i);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:170: Unsupported: Ignoring delay on this delayed statement.\n        #100 masterSendAddr(8\'d128+7);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:171: Unsupported: Ignoring delay on this delayed statement.\n        #100 masterRece(r_rece);\n        ^\n%Error: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:16: Cannot find file containing module: \'design_main\'\ndesign_main #(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/473686629/essential/sram_like/sim,data/full_repos/permissive/473686629/design_main\n             data/full_repos/permissive/473686629/essential/sram_like/sim,data/full_repos/permissive/473686629/design_main.v\n             data/full_repos/permissive/473686629/essential/sram_like/sim,data/full_repos/permissive/473686629/design_main.sv\n             design_main\n             design_main.v\n             design_main.sv\n             obj_dir/design_main\n             obj_dir/design_main.v\n             obj_dir/design_main.sv\n%Warning-WIDTH: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:113: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                          : ... In instance tb_main\n        data[0] = {$random};\n                ^\n%Warning-WIDTH: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:114: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                          : ... In instance tb_main\n        data[1] = {$random};\n                ^\n%Warning-WIDTH: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:115: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n                                                                                          : ... In instance tb_main\n        data[2] = {$random};\n                ^\n%Warning-WIDTH: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:140: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                          : ... In instance tb_main\n        data[0] = i+1;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:147: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'r_rece\' generates 16 bits.\n                                                                                          : ... In instance tb_main\n        if(r_rece == i+1)\n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:161: Operator TASKREF \'masterSendData\' expects 16 bits on the Function Argument, but Function Argument\'s VARREF \'i\' generates 32 bits.\n                                                                                          : ... In instance tb_main\n        #100 masterSendData(i);\n             ^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:163: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                          : ... In instance tb_main\n        data[0] = i+1;\n                ^\n%Warning-WIDTH: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:169: Operator TASKREF \'masterSendData\' expects 16 bits on the Function Argument, but Function Argument\'s SUB generates 32 bits.\n                                                                                          : ... In instance tb_main\n        #100 masterSendData(9-i);\n             ^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/473686629/essential/sram_like/sim/tb_main.v:172: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'r_rece\' generates 16 bits.\n                                                                                          : ... In instance tb_main\n        if(r_rece == (9-i+1))\n                  ^~\n%Error: Exiting due to 1 error(s), 45 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_main;



reg   clk;
reg   rst_n;
reg   spi_scl;        
reg   spi_sdi;
reg   spi_cs_addr;
reg   spi_cs_data;


wire  spi_sdo;

design_main #(
    .sim_present ( 1 ))
 u_design_main (
    .clk                     ( clk           ),
    .rst_n                   ( rst_n         ),
    .spi_scl                 ( spi_scl       ),
    .spi_sdi                 ( spi_sdi       ),
    .spi_cs_addr             ( spi_cs_addr   ),
    .spi_cs_data             ( spi_cs_data   ),

    .spi_sdo                 ( spi_sdo       )
);

localparam SPI_SCL_DELAY = 50;
localparam SPI_CSN_DELAY = 50;
localparam width_addr   = 8 ;
localparam width_data  = 16;

task masterSendAddr;
    input [width_addr-1:0] Din_addr;

    begin : block_sendAddr
        integer i;

        #SPI_CSN_DELAY spi_cs_addr = 0;
        for(i = 0; i < width_addr; i = i + 1) begin
            spi_sdi = Din_addr[width_addr - 1 - i];

            #SPI_SCL_DELAY spi_scl = 1;
            #SPI_SCL_DELAY spi_scl = 0;
        end
        #SPI_CSN_DELAY spi_cs_addr = 1;
    end
endtask

task masterSendData;
    input [width_data-1:0] Din_data;

    begin : block_sendData
        integer i;

        #SPI_CSN_DELAY spi_cs_data = 0;
        for(i = 0; i < width_data; i = i + 1) begin
            spi_sdi = Din_data[width_data - 1 - i];

            #SPI_SCL_DELAY spi_scl = 1;
            #SPI_SCL_DELAY spi_scl = 0;
        end
        #SPI_CSN_DELAY spi_cs_data = 1;
    end
endtask

task masterRece;
    output [width_data-1:0] Dout;

    begin : block_rece
        integer i;

        #SPI_CSN_DELAY spi_cs_data = 0;
        for(i = 0; i < width_data; i = i + 1) begin
            

            #SPI_SCL_DELAY spi_scl = 1;
            Dout[width_data-1-i] = spi_sdo;
            #SPI_SCL_DELAY spi_scl = 0;
            
        end
        #SPI_CSN_DELAY spi_cs_data = 1;
    end
endtask


integer i;
reg [15:0] r_rece;
reg [15:0] data [2:0];

always #10 clk = ~ clk;

initial begin
    clk = 0;
    rst_n = 0;
    spi_scl = 0;
    spi_sdi = 0;
    spi_cs_addr = 1;
    spi_cs_data = 1;
    r_rece = 0;
    data[0] = 0;
    data[1] = 0;
    data[2] = 0;
#100
    rst_n = 1;

    #100 masterSendAddr(8'd8);
    #100 masterSendData(16'd1);

    $write("test register\n");
    for(i = 0; i < 10; i = i + 1) begin
        data[0] = {$random};
        data[1] = {$random};
        data[2] = {$random};
        #100 masterSendAddr(8'd1);
        #100 masterSendData(data[0]);
        #100 masterSendAddr(8'd2);
        #100 masterSendData(data[1]);
        #100 masterSendAddr(8'd3);
        #100 masterSendData(data[2]);
        #100 masterSendAddr(8'd128);
        #100 masterRece(r_rece);
        if(r_rece == (data[0] + data[1] + data[2])) begin
            $write("test%d pass\n", i);
        end
        else begin
            $write("test%d failed, data0:%h, data1:%h, data2:%h, rece:%h\n", i, data[0], data[1], data[2], r_rece);
        end
    end
    $write("\n");


    $write("test fifo\n");
    data[0] = 16'd0;
    r_rece = 16'd0;

    #100 masterSendAddr(8'd4);
    for (i = 0; i < 10; i = i + 1) begin
        data[0] = i+1;
        #100 masterSendData(data[0]);
    end

    #100 masterSendAddr(8'd132);
    for (i = 0; i < 10; i = i + 1) begin
        #100 masterRece(r_rece);
        if(r_rece == i+1)
            $write("test%d pass\n", i);
        else
            $write("test%d failed, rece:%d\n", i, r_rece);
    end
    $write("\n");


    $write("test ram\n");
    data[0] = 16'd0;
    r_rece = 16'd0;

    for (i = 0; i < 10; i = i + 1) begin
        #100 masterSendAddr(8'd5);
        #100 masterSendData(i);
        #100 masterSendAddr(8'd7);
        data[0] = i+1;
        #100 masterSendData(data[0]);
    end

    for (i = 0; i < 10; i = i + 1) begin
        #100 masterSendAddr(8'd6);
        #100 masterSendData(9-i);
        #100 masterSendAddr(8'd128+7);
        #100 masterRece(r_rece);
        if(r_rece == (9-i+1))
            $write("test%d pass\n", i);
        else
            $write("test%d failed, rece:%d\n", i, r_rece);
    end
    $write("\n");

    $write("Simulation finish!\n");
    $stop;
end

endmodule
module tb_main;




reg   clk;
reg   rst_n;
reg   spi_scl;        
reg   spi_sdi;
reg   spi_cs_addr;
reg   spi_cs_data;


wire  spi_sdo;

design_main #(
    .sim_present ( 1 ))
 u_design_main (
    .clk                     ( clk           ),
    .rst_n                   ( rst_n         ),
    .spi_scl                 ( spi_scl       ),
    .spi_sdi                 ( spi_sdi       ),
    .spi_cs_addr             ( spi_cs_addr   ),
    .spi_cs_data             ( spi_cs_data   ),

    .spi_sdo                 ( spi_sdo       )
);

localparam SPI_SCL_DELAY = 50;
localparam SPI_CSN_DELAY = 50;
localparam width_addr   = 8 ;
localparam width_data  = 16;

task masterSendAddr;
    input [width_addr-1:0] Din_addr;

    begin : block_sendAddr
        integer i;

        #SPI_CSN_DELAY spi_cs_addr = 0;
        for(i = 0; i < width_addr; i = i + 1) begin
            spi_sdi = Din_addr[width_addr - 1 - i];

            #SPI_SCL_DELAY spi_scl = 1;
            #SPI_SCL_DELAY spi_scl = 0;
        end
        #SPI_CSN_DELAY spi_cs_addr = 1;
    end
endtask

task masterSendData;
    input [width_data-1:0] Din_data;

    begin : block_sendData
        integer i;

        #SPI_CSN_DELAY spi_cs_data = 0;
        for(i = 0; i < width_data; i = i + 1) begin
            spi_sdi = Din_data[width_data - 1 - i];

            #SPI_SCL_DELAY spi_scl = 1;
            #SPI_SCL_DELAY spi_scl = 0;
        end
        #SPI_CSN_DELAY spi_cs_data = 1;
    end
endtask

task masterRece;
    output [width_data-1:0] Dout;

    begin : block_rece
        integer i;

        #SPI_CSN_DELAY spi_cs_data = 0;
        for(i = 0; i < width_data; i = i + 1) begin
            

            #SPI_SCL_DELAY spi_scl = 1;
            Dout[width_data-1-i] = spi_sdo;
            #SPI_SCL_DELAY spi_scl = 0;
            
        end
        #SPI_CSN_DELAY spi_cs_data = 1;
    end
endtask


integer i;
reg [15:0] r_rece;
reg [15:0] data [2:0];

always #10 clk = ~ clk;

initial begin
    clk = 0;
    rst_n = 0;
    spi_scl = 0;
    spi_sdi = 0;
    spi_cs_addr = 1;
    spi_cs_data = 1;
    r_rece = 0;
    data[0] = 0;
    data[1] = 0;
    data[2] = 0;
#100
    rst_n = 1;

    #100 masterSendAddr(8'd8);
    #100 masterSendData(16'd1);

    $write("test register\n");
    for(i = 0; i < 10; i = i + 1) begin
        data[0] = {$random};
        data[1] = {$random};
        data[2] = {$random};
        #100 masterSendAddr(8'd1);
        #100 masterSendData(data[0]);
        #100 masterSendAddr(8'd2);
        #100 masterSendData(data[1]);
        #100 masterSendAddr(8'd3);
        #100 masterSendData(data[2]);
        #100 masterSendAddr(8'd128);
        #100 masterRece(r_rece);
        if(r_rece == (data[0] + data[1] + data[2])) begin
            $write("test%d pass\n", i);
        end
        else begin
            $write("test%d failed, data0:%h, data1:%h, data2:%h, rece:%h\n", i, data[0], data[1], data[2], r_rece);
        end
    end
    $write("\n");


    $write("test fifo\n");
    data[0] = 16'd0;
    r_rece = 16'd0;

    #100 masterSendAddr(8'd4);
    for (i = 0; i < 10; i = i + 1) begin
        data[0] = i+1;
        #100 masterSendData(data[0]);
    end

    #100 masterSendAddr(8'd132);
    for (i = 0; i < 10; i = i + 1) begin
        #100 masterRece(r_rece);
        if(r_rece == i+1)
            $write("test%d pass\n", i);
        else
            $write("test%d failed, rece:%d\n", i, r_rece);
    end
    $write("\n");


    $write("test ram\n");
    data[0] = 16'd0;
    r_rece = 16'd0;

    for (i = 0; i < 10; i = i + 1) begin
        #100 masterSendAddr(8'd5);
        #100 masterSendData(i);
        #100 masterSendAddr(8'd7);
        data[0] = i+1;
        #100 masterSendData(data[0]);
    end

    for (i = 0; i < 10; i = i + 1) begin
        #100 masterSendAddr(8'd6);
        #100 masterSendData(9-i);
        #100 masterSendAddr(8'd128+7);
        #100 masterRece(r_rece);
        if(r_rece == (9-i+1))
            $write("test%d pass\n", i);
        else
            $write("test%d failed, rece:%d\n", i, r_rece);
    end
    $write("\n");

    $write("Simulation finish!\n");
    $stop;
end

endmodule