data/full_repos/permissive/455657973/mux_2_1.v
data/verilator_xmls/1b0441c7-735e-4c1a-88e2-72577d350b9e.xml
module mux_2_1 (
input [31:0] input1, 
input [31:0] input2, 
input signal, 
output reg [31:0] out);
 
always@(signal)
begin
		if (signal==0)
			out <= input2;
		else
			out <= input1;
end
endmodule
module mux_2_1 (
input [31:0] input1, 
input [31:0] input2, 
input signal, 
output reg [31:0] out);

 
always@(signal)
begin
		if (signal==0)
			out <= input2;
		else
			out <= input1;
end
endmodule