data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/auc_rand_wrap.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl/auc_rand_wrap.v:61: Cannot find file containing module: 'auc_rand'\nauc_rand\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl,data/full_repos/permissive/530013823/auc_rand\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl,data/full_repos/permissive/530013823/auc_rand.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/BanGoc/LuanVan/Hardware/lv_2pl,data/full_repos/permissive/530013823/auc_rand.sv\n             auc_rand\n             auc_rand.v\n             auc_rand.sv\n             obj_dir/auc_rand\n             obj_dir/auc_rand.v\n             obj_dir/auc_rand.sv\n%Error: Exiting due to 1 error(s)\n"
module auc_rand_wrap
    (
     clk,
     rst,

     rand_en,
     rand_tnum,
     rand_curve,

     rand_vld,

     rand_wen,
     rand_wadd,
     rand_wdat
     );



`define             RTL_SIMULATION

parameter           WIDTH   = 256;
parameter           ADDR    = 5;




input               clk;
input               rst;

input               rand_en;
input [WIDTH-1:0]   rand_tnum;
input               rand_curve;

output              rand_vld;

output              rand_wen;
output [ADDR-1:0]   rand_wadd;
output [WIDTH-1:0]  rand_wdat;







wire [WIDTH-1:0]    rand_din;

auc_rand
    #(
      .WIDTH(WIDTH),
      .ADDR(ADDR)
      ) iauc_rand
    (
     .clk(clk),
     .rst(rst),

     .rand_en(rand_en),
     .rand_din(rand_din),
     .rand_curve(rand_curve),

     .rand_vld(rand_vld),

     .rand_wen(rand_wen),
     .rand_wadd(rand_wadd),
     .rand_wdat(rand_wdat)
     );

`ifdef  RTL_SIMULATION
assign              rand_din = rand_tnum;

`else
wire [WIDTH-1:0]    randvl;

lv_rd256wrap
    #(
      .WID(WIDTH)
      ) ilv_rs256wrap
    (
     .clk(clk),
     .rst(rst),
     .randvl(randvl)
     );

assign              rand_din = randvl;

`endif

endmodule
module auc_rand_wrap
    (
     clk,
     rst,

     rand_en,
     rand_tnum,
     rand_curve,

     rand_vld,

     rand_wen,
     rand_wadd,
     rand_wdat
     );




`define             RTL_SIMULATION

parameter           WIDTH   = 256;
parameter           ADDR    = 5;




input               clk;
input               rst;

input               rand_en;
input [WIDTH-1:0]   rand_tnum;
input               rand_curve;

output              rand_vld;

output              rand_wen;
output [ADDR-1:0]   rand_wadd;
output [WIDTH-1:0]  rand_wdat;







wire [WIDTH-1:0]    rand_din;

auc_rand
    #(
      .WIDTH(WIDTH),
      .ADDR(ADDR)
      ) iauc_rand
    (
     .clk(clk),
     .rst(rst),

     .rand_en(rand_en),
     .rand_din(rand_din),
     .rand_curve(rand_curve),

     .rand_vld(rand_vld),

     .rand_wen(rand_wen),
     .rand_wadd(rand_wadd),
     .rand_wdat(rand_wdat)
     );

`ifdef  RTL_SIMULATION
assign              rand_din = rand_tnum;

`else
wire [WIDTH-1:0]    randvl;

lv_rd256wrap
    #(
      .WID(WIDTH)
      ) ilv_rs256wrap
    (
     .clk(clk),
     .rst(rst),
     .randvl(randvl)
     );

assign              rand_din = randvl;

`endif

endmodule