data/full_repos/permissive/431487364/sim/ram_tb.v
1: b'%Error: data/full_repos/permissive/431487364/sim/ram_tb.v:1: Cannot find include file: ../src/headers/buceros_header.v\n`include "../src/headers/buceros_header.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/431487364/sim,data/full_repos/permissive/431487364/../src/headers/buceros_header.v\n             data/full_repos/permissive/431487364/sim,data/full_repos/permissive/431487364/../src/headers/buceros_header.v.v\n             data/full_repos/permissive/431487364/sim,data/full_repos/permissive/431487364/../src/headers/buceros_header.v.sv\n             ../src/headers/buceros_header.v\n             ../src/headers/buceros_header.v.v\n             ../src/headers/buceros_header.v.sv\n             obj_dir/../src/headers/buceros_header.v\n             obj_dir/../src/headers/buceros_header.v.v\n             obj_dir/../src/headers/buceros_header.v.sv\n%Error: data/full_repos/permissive/431487364/sim/ram_tb.v:12: Define or directive not defined: \'`MemAddrBus\'\n  reg [`MemAddrBus] r_addr1_i;\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/sim/ram_tb.v:12: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg [`MemAddrBus] r_addr1_i;\n                  ^\n%Error: data/full_repos/permissive/431487364/sim/ram_tb.v:13: Define or directive not defined: \'`MemAddrBus\'\n  reg [`MemAddrBus] r_addr2_i;\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/sim/ram_tb.v:13: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg [`MemAddrBus] r_addr2_i;\n                  ^\n%Error: data/full_repos/permissive/431487364/sim/ram_tb.v:15: Define or directive not defined: \'`MemAddrBus\'\n  reg [`MemAddrBus] w_addr_i;\n       ^~~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/sim/ram_tb.v:15: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg [`MemAddrBus] w_addr_i;\n                  ^\n%Error: data/full_repos/permissive/431487364/sim/ram_tb.v:16: Define or directive not defined: \'`WordBus\'\n  reg [   `WordBus] w_data_i;\n          ^~~~~~~~\n%Error: data/full_repos/permissive/431487364/sim/ram_tb.v:16: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  reg [   `WordBus] w_data_i;\n                  ^\n%Error: data/full_repos/permissive/431487364/sim/ram_tb.v:18: Define or directive not defined: \'`WordBus\'\n  wire [   `WordBus] r_data1_o;\n           ^~~~~~~~\n%Error: data/full_repos/permissive/431487364/sim/ram_tb.v:18: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire [   `WordBus] r_data1_o;\n                   ^\n%Error: data/full_repos/permissive/431487364/sim/ram_tb.v:19: Define or directive not defined: \'`WordBus\'\n  wire [   `WordBus] r_data2_o;\n           ^~~~~~~~\n%Error: data/full_repos/permissive/431487364/sim/ram_tb.v:19: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  wire [   `WordBus] r_data2_o;\n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/431487364/sim/ram_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n    #1 rst_n = 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/431487364/sim/ram_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n        #10 r_addr1_i = r_addr1_i + 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/431487364/sim/ram_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n    #5  clk = ! clk ;\n    ^\n%Error: Exiting due to 13 error(s), 3 warning(s)\n'
module ram_tb;


  localparam  RAM_DEPTH = 16384;
  localparam  RAM_DEPTH_BIT_LEN = 14;


  reg  clk = 0;
  reg  rst_n = 0;
  reg [`MemAddrBus] r_addr1_i;
  reg [`MemAddrBus] r_addr2_i;
  reg  w_en_i = 0;
  reg [`MemAddrBus] w_addr_i;
  reg [   `WordBus] w_data_i;
  reg [        3:0] w_sel_i;
  wire [   `WordBus] r_data1_o;
  wire [   `WordBus] r_data2_o;

  ram 
  #(
    .RAM_DEPTH(RAM_DEPTH ),
    .RAM_DEPTH_BIT_LEN (
        RAM_DEPTH_BIT_LEN )
  )
  ram_dut (
    .clk (clk ),
    .rst_n (rst_n ),
    .r_addr1_i (r_addr1_i ),
    .r_addr2_i (r_addr2_i ),
    .w_en_i (w_en_i ),
    .w_addr_i (w_addr_i ),
    .w_data_i (w_data_i ),
    .w_sel_i (w_sel_i ),
    .r_data1_o (r_data1_o ),
    .r_data2_o  ( r_data2_o)
  );

  initial begin
    begin
    #1 rst_n = 1;
    r_addr1_i = 0;
    r_addr2_i = 1;
    w_addr_i = 10;
      repeat (100000) begin
        #10 r_addr1_i = r_addr1_i + 1;
        r_addr2_i = r_addr2_i + 1;
        w_en_i = $random;
        w_addr_i = w_addr_i +1;
        w_data_i = $random;
        w_sel_i = $random;
      end
    end
  end

  always
    #5  clk = ! clk ;

endmodule
module ram_tb;



  localparam  RAM_DEPTH = 16384;
  localparam  RAM_DEPTH_BIT_LEN = 14;


  reg  clk = 0;
  reg  rst_n = 0;
  reg [`MemAddrBus] r_addr1_i;
  reg [`MemAddrBus] r_addr2_i;
  reg  w_en_i = 0;
  reg [`MemAddrBus] w_addr_i;
  reg [   `WordBus] w_data_i;
  reg [        3:0] w_sel_i;
  wire [   `WordBus] r_data1_o;
  wire [   `WordBus] r_data2_o;

  ram 
  #(
    .RAM_DEPTH(RAM_DEPTH ),
    .RAM_DEPTH_BIT_LEN (
        RAM_DEPTH_BIT_LEN )
  )
  ram_dut (
    .clk (clk ),
    .rst_n (rst_n ),
    .r_addr1_i (r_addr1_i ),
    .r_addr2_i (r_addr2_i ),
    .w_en_i (w_en_i ),
    .w_addr_i (w_addr_i ),
    .w_data_i (w_data_i ),
    .w_sel_i (w_sel_i ),
    .r_data1_o (r_data1_o ),
    .r_data2_o  ( r_data2_o)
  );

  initial begin
    begin
    #1 rst_n = 1;
    r_addr1_i = 0;
    r_addr2_i = 1;
    w_addr_i = 10;
      repeat (100000) begin
        #10 r_addr1_i = r_addr1_i + 1;
        r_addr2_i = r_addr2_i + 1;
        w_en_i = $random;
        w_addr_i = w_addr_i +1;
        w_data_i = $random;
        w_sel_i = $random;
      end
    end
  end

  always
    #5  clk = ! clk ;

endmodule