data/full_repos/permissive/447976230/fpga/usrp2/fifo/fifo_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/fifo/fifo_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n   initial #1000 rst = 0;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/fifo/fifo_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n   always #50 clk = ~clk;\n          ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/fifo/fifo_tb.v:49: Unsupported or unknown PLI call: $dumpfile\n   initial $dumpfile("fifo_tb.vcd");\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/fifo/fifo_tb.v:50: Unsupported or unknown PLI call: $dumpvars\n   initial $dumpvars(0,fifo_tb);\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/fifo/fifo_tb.v:54: syntax error, unexpected \'@\'\n @(negedge rst);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/fifo/fifo_tb.v:61: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/fifo/fifo_tb.v:63: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/fifo/fifo_tb.v:65: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/fifo/fifo_tb.v:67: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/fifo/fifo_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n   initial #4000 $finish;\n           ^\n%Error: Exiting due to 7 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module fifo_tb();
   
   reg clk = 0;
   reg rst = 1;
   reg clear = 0;
   initial #1000 rst = 0;
   always #50 clk = ~clk;
   
   reg [31:0] f36_data = 0;
   reg [1:0] f36_occ = 0;
   reg f36_sof = 0, f36_eof = 0;
   reg f36_src_rdy;
   wire f36_dst_rdy;
   
   wire [7:0] ll_data;
   wire ll_src_rdy, ll_dst_rdy, ll_sof, ll_eof;
   wire [35:0] err_dat;
   wire        err_src_rdy, err_dst_rdy;

   fifo36_to_ll8 fifo36_to_ll8
     (.clk(clk),.reset(rst),.clear(clear),
      .f36_data({f36_occ,f36_eof,f36_sof,f36_data}),.f36_src_rdy_i(f36_src_rdy),.f36_dst_rdy_o(f36_dst_rdy),
      .ll_data(ll_data),.ll_sof(ll_sof),.ll_eof(ll_eof),
      .ll_src_rdy(ll_src_rdy),.ll_dst_rdy(ll_dst_rdy));

   assign ll_dst_rdy = 1;
   
   always @(posedge clk)
     if(ll_src_rdy)
       $display("LL: SOF %d, EOF %d, DAT %x",ll_sof,ll_eof,ll_data);
   
   initial $dumpfile("fifo_tb.vcd");
   initial $dumpvars(0,fifo_tb);

   initial
     begin
	@(negedge rst);
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	f36_src_rdy <= 1;
	{f36_occ,f36_eof,f36_sof,f36_data} <= { 2'b00,1'b0,1'b1,32'h00010203};
	@(posedge clk);
	{f36_occ,f36_eof,f36_sof,f36_data} <= { 2'b00,1'b0,1'b0,32'h04050607};
	@(posedge clk);
	{f36_occ,f36_eof,f36_sof,f36_data} <= { 2'b00,1'b0,1'b0,32'h08090a0b};
	@(posedge clk);
	{f36_occ,f36_eof,f36_sof,f36_data} <= { 2'b11,1'b1,1'b0,32'h0c0d0e0f};
	@(posedge clk);
	f36_src_rdy <= 0;
     end
   
   initial #4000 $finish;
endmodule
module fifo_tb();

   
   reg clk = 0;
   reg rst = 1;
   reg clear = 0;
   initial #1000 rst = 0;
   always #50 clk = ~clk;
   
   reg [31:0] f36_data = 0;
   reg [1:0] f36_occ = 0;
   reg f36_sof = 0, f36_eof = 0;
   reg f36_src_rdy;
   wire f36_dst_rdy;
   
   wire [7:0] ll_data;
   wire ll_src_rdy, ll_dst_rdy, ll_sof, ll_eof;
   wire [35:0] err_dat;
   wire        err_src_rdy, err_dst_rdy;

   fifo36_to_ll8 fifo36_to_ll8
     (.clk(clk),.reset(rst),.clear(clear),
      .f36_data({f36_occ,f36_eof,f36_sof,f36_data}),.f36_src_rdy_i(f36_src_rdy),.f36_dst_rdy_o(f36_dst_rdy),
      .ll_data(ll_data),.ll_sof(ll_sof),.ll_eof(ll_eof),
      .ll_src_rdy(ll_src_rdy),.ll_dst_rdy(ll_dst_rdy));

   assign ll_dst_rdy = 1;
   
   always @(posedge clk)
     if(ll_src_rdy)
       $display("LL: SOF %d, EOF %d, DAT %x",ll_sof,ll_eof,ll_data);
   
   initial $dumpfile("fifo_tb.vcd");
   initial $dumpvars(0,fifo_tb);

   initial
     begin
	@(negedge rst);
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);
	f36_src_rdy <= 1;
	{f36_occ,f36_eof,f36_sof,f36_data} <= { 2'b00,1'b0,1'b1,32'h00010203};
	@(posedge clk);
	{f36_occ,f36_eof,f36_sof,f36_data} <= { 2'b00,1'b0,1'b0,32'h04050607};
	@(posedge clk);
	{f36_occ,f36_eof,f36_sof,f36_data} <= { 2'b00,1'b0,1'b0,32'h08090a0b};
	@(posedge clk);
	{f36_occ,f36_eof,f36_sof,f36_data} <= { 2'b11,1'b1,1'b0,32'h0c0d0e0f};
	@(posedge clk);
	f36_src_rdy <= 0;
     end
   
   initial #4000 $finish;
endmodule