data/full_repos/permissive/481069643/Day01/ALU_tb.v
1: b'%Error: data/full_repos/permissive/481069643/Day01/ALU_tb.v:44: Unsupported or unknown PLI call: $monitor\n$monitor(" in_b = %b, in_a = %b, fun=%b, out_alu = %b, Carry = %b",in_b,in_a,fun,out_alu,out_carry);\n^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/481069643/Day01/ALU_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n#10;\n^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/481069643/Day01/ALU_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n#10 $finish;\n^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ALU_tb();


reg [3:0]in_a,in_b;
reg [3:0]fun;
wire [3:0]out_alu;
wire out_carry;


ALU atb0(in_a,in_b,fun,out_alu,out_carry);

initial
begin
$monitor(" in_b = %b, in_a = %b, fun=%b, out_alu = %b, Carry = %b",in_b,in_a,fun,out_alu,out_carry);
in_a = 0;
in_b =0;

fun = 0;

#10;

in_a = 2;
in_b =4;
fun = 9;
#10 $finish;


end 

endmodule
module ALU_tb();



reg [3:0]in_a,in_b;
reg [3:0]fun;
wire [3:0]out_alu;
wire out_carry;


ALU atb0(in_a,in_b,fun,out_alu,out_carry);

initial
begin
$monitor(" in_b = %b, in_a = %b, fun=%b, out_alu = %b, Carry = %b",in_b,in_a,fun,out_alu,out_carry);
in_a = 0;
in_b =0;

fun = 0;

#10;

in_a = 2;
in_b =4;
fun = 9;
#10 $finish;


end 

endmodule