data/full_repos/permissive/417288846/List_1/Task_3/encoder_4.v
data/verilator_xmls/75434e67-c1ba-4f01-9b39-f10b63c7d8e4.xml
module encoder_2(input v1, v2, output valid, num);
    wire nv1;
    or  (valid, v1, v2);
    not (nv1, v1);
    and (num, nv1, v2);
endmodule
module encoder_2(input v1, v2, output valid, num);

    wire nv1;
    or  (valid, v1, v2);
    not (nv1, v1);
    and (num, nv1, v2);
endmodule