data/full_repos/permissive/443556793/lab_4/rtl/mux4.v
data/verilator_xmls/4261fd33-1b72-47b9-af58-26c9534e12cb.xml
module mux4 #(parameter WIDTH = 8)(
	input wire[WIDTH-1:0] d0,d1,d2,d3,
	input wire[1:0] s,
	output wire[WIDTH-1:0] y
    );
reg[WIDTH-1:0] ytemp;
always @(*)begin
    case(s)
        2'b00:begin
            ytemp <= d0;
        end
        2'b01:begin
            ytemp <= d1;
        end
        2'b10:begin
            ytemp <= d2;
        end
        2'b11:begin
            ytemp <= d3;
        end
        default:begin
            ytemp <= 0;
        end
    endcase
end
	
	assign y = ytemp;
endmodule
module mux4 #(parameter WIDTH = 8)(
	input wire[WIDTH-1:0] d0,d1,d2,d3,
	input wire[1:0] s,
	output wire[WIDTH-1:0] y
    );

reg[WIDTH-1:0] ytemp;
always @(*)begin
    case(s)
        2'b00:begin
            ytemp <= d0;
        end
        2'b01:begin
            ytemp <= d1;
        end
        2'b10:begin
            ytemp <= d2;
        end
        2'b11:begin
            ytemp <= d3;
        end
        default:begin
            ytemp <= 0;
        end
    endcase
end
	
	assign y = ytemp;
endmodule