data/full_repos/permissive/419677538/Exercise_3/verilog_code/Exe3_part2/SynchronousCounter.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/419677538/Exercise_3/verilog_code/Exe3_part2/SynchronousCounter.v:8: Unsupported: Ignoring delay on this delayed statement.\n     #1 q <= 1\'b0;\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/419677538/Exercise_3/verilog_code/Exe3_part2/SynchronousCounter.v:10: Unsupported: Ignoring delay on this delayed statement.\n     #2 q <= ~q;\n     ^\n%Error: Exiting due to 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module SynchronousCounter(q,clk,reset);
	output [3:0] q;
	input clk,reset;
	wire t2,t3,enable;
	reg [24:0] delay_counter;
	
	assign enable = (delay_counter == 25'd24999999) ? 1'b1 : 1'b0;	
	T_FF t_ff0(q[0],1'b1,clk,reset,enable);
	T_FF t_ff1(q[1],q[0],clk,reset,enable);
	and(t2,q[0],q[1]);
	T_FF t_ff2(q[2],t2,clk,reset,enable);
	and(t3,t2,q[2]);
	T_FF t_ff3(q[3],t3,clk,reset,enable);
	always @ (negedge clk or posedge reset) 
		if (reset)
		   delay_counter <= 25'd0; 
		else if (enable) 
		   delay_counter <= 25'd0; 
		else 
		   delay_counter <= delay_counter + 1'b1;
endmodule
module SynchronousCounter(q,clk,reset);

	output [3:0] q;
	input clk,reset;
	wire t2,t3,enable;
	reg [24:0] delay_counter;
	
	assign enable = (delay_counter == 25'd24999999) ? 1'b1 : 1'b0;	
	T_FF t_ff0(q[0],1'b1,clk,reset,enable);
	T_FF t_ff1(q[1],q[0],clk,reset,enable);
	and(t2,q[0],q[1]);
	T_FF t_ff2(q[2],t2,clk,reset,enable);
	and(t3,t2,q[2]);
	T_FF t_ff3(q[3],t3,clk,reset,enable);
	always @ (negedge clk or posedge reset) 
		if (reset)
		   delay_counter <= 25'd0; 
		else if (enable) 
		   delay_counter <= 25'd0; 
		else 
		   delay_counter <= delay_counter + 1'b1;
endmodule