data/full_repos/permissive/467394306/rtl/tb/out_tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/467394306/rtl/tb/out_tb.sv:25: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/467394306/rtl/tb/out_tb.sv:48: Unsupported: Ignoring delay on this delayed statement.\n        #25;\n        ^\n%Error: data/full_repos/permissive/467394306/rtl/tb/out_tb.sv:51: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/467394306/rtl/tb/out_tb.sv:59: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module OUT_TB #(
    parameter SIMCYCLES = 16)
    ();





    integer i,j;





    reg clk, rstn;
    reg [31:0] din [0:7];
    reg [0:7] in_v;
    reg read;
    wire [31:0] dout;
    wire rvalid;

    always begin
        #10
        clk = ~clk;
    end

    COL_OUTPUT_CTRL DUT (.clk(clk), .rstn(rstn),
        .in_r(din),
        .in_v(in_v),
        .rread(read),
        .out_r(dout),
        .rvalid(rvalid));

    initial begin
        clk <= 0;
        rstn <= 0;
        read <= 0;
        in_v <= 0;
        
        for (i=0; i<8 ; i=i+1) begin
            din[i] <= (i*100)+1;
        end

        $display("INITIALZIED.");

        #25;
        rstn <= 1;

        @(posedge clk);


        for (i=0; i<20; i=i+1) begin
            for (j=0; j<8; j=j+1) begin
                in_v[j] = i==j;
            end

            @(posedge clk);

            if (rvalid) begin
                read <= 1;
            end else begin
                read <= 0;
            end
        end

        $display("SIMULATION ENDED.");
        $finish;
    end
endmodule
module OUT_TB #(
    parameter SIMCYCLES = 16)
    ();






    integer i,j;





    reg clk, rstn;
    reg [31:0] din [0:7];
    reg [0:7] in_v;
    reg read;
    wire [31:0] dout;
    wire rvalid;

    always begin
        #10
        clk = ~clk;
    end

    COL_OUTPUT_CTRL DUT (.clk(clk), .rstn(rstn),
        .in_r(din),
        .in_v(in_v),
        .rread(read),
        .out_r(dout),
        .rvalid(rvalid));

    initial begin
        clk <= 0;
        rstn <= 0;
        read <= 0;
        in_v <= 0;
        
        for (i=0; i<8 ; i=i+1) begin
            din[i] <= (i*100)+1;
        end

        $display("INITIALZIED.");

        #25;
        rstn <= 1;

        @(posedge clk);


        for (i=0; i<20; i=i+1) begin
            for (j=0; j<8; j=j+1) begin
                in_v[j] = i==j;
            end

            @(posedge clk);

            if (rvalid) begin
                read <= 1;
            end else begin
                read <= 0;
            end
        end

        $display("SIMULATION ENDED.");
        $finish;
    end
endmodule