data/full_repos/permissive/448204225/src/z1top_axi.v
1: b'%Warning-REALCVT: data/full_repos/permissive/448204225/src/z1top_axi.v:72: Implicit conversion of real to integer\n  localparam integer B_SAMPLE_CNT_MAX = 0.0005 * CPU_CLOCK_FREQ;\n                                               ^\n                  ... Use "/* verilator lint_off REALCVT */" and lint_on around source to disable this message.\n%Warning-REALCVT: data/full_repos/permissive/448204225/src/z1top_axi.v:74: Implicit conversion of real to integer\n  localparam integer B_PULSE_CNT_MAX = 0.100 / 0.0005;\n                                             ^\n%Error: data/full_repos/permissive/448204225/src/z1top_axi.v:77: Cannot find file containing module: \'button_parser\'\n  button_parser #(\n  ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/448204225/src,data/full_repos/permissive/448204225/button_parser\n             data/full_repos/permissive/448204225/src,data/full_repos/permissive/448204225/button_parser.v\n             data/full_repos/permissive/448204225/src,data/full_repos/permissive/448204225/button_parser.sv\n             button_parser\n             button_parser.v\n             button_parser.sv\n             obj_dir/button_parser\n             obj_dir/button_parser.v\n             obj_dir/button_parser.sv\n%Error: data/full_repos/permissive/448204225/src/z1top_axi.v:113: Cannot find file containing module: \'Riscv151\'\n  Riscv151 #(\n  ^~~~~~~~\n%Error: data/full_repos/permissive/448204225/src/z1top_axi.v:176: Cannot find file containing module: \'axi_mm_adapter\'\n  axi_mm_adapter #(\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/448204225/src/z1top_axi.v:259: Cannot find file containing module: \'dma_controller\'\n  dma_controller #(\n  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/448204225/src/z1top_axi.v:323: Cannot find file containing module: \'xcel_naive\'\n  xcel_naive #(\n  ^~~~~~~~~~\n%Error: data/full_repos/permissive/448204225/src/z1top_axi.v:369: Cannot find file containing module: \'REGISTER_R_CE\'\n  REGISTER_R_CE #(.N(1)) acc_busy_reg (\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/448204225/src/z1top_axi.v:378: Cannot find file containing module: \'arbiter\'\n  arbiter #(\n  ^~~~~~~\n%Error: Exiting due to 7 error(s), 2 warning(s)\n'
module z1top_axi #(
  parameter AXI_AWIDTH = 32,
  parameter AXI_DWIDTH = 32,
  parameter AXI_MAX_BURST_LEN = 256,
  parameter CPU_CLOCK_FREQ = 50_000_000
) (
  input  CLK_125MHZ_FPGA,
  input  [3:0] BUTTONS,
  input  [1:0] SWITCHES,
  output [5:0] LEDS,

  input  FPGA_SERIAL_RX,
  output FPGA_SERIAL_TX,


  input axi_clk,
  input axi_resetn,


  output [3:0]            arid,
  output [AXI_AWIDTH-1:0] araddr,
  output                  arvalid,
  input                   arready,
  output [7:0]            arlen,
  output [2:0]            arsize,
  output [1:0]            arburst,



  input [3:0]             rid,
  input [AXI_DWIDTH-1:0]  rdata,
  input                   rvalid,
  output                  rready,
  input                   rlast,
  input [1:0]             rresp,



  output [3:0]            awid,
  output [AXI_AWIDTH-1:0] awaddr,
  output                  awvalid,
  input                   awready,
  output [7:0]            awlen,
  output [2:0]            awsize,
  output [1:0]            awburst,



  output [3:0]            wid,
  output [AXI_DWIDTH-1:0] wdata,
  output                  wvalid,
  input                   wready,
  output                  wlast,
  output [AXI_DWIDTH/8-1:0] wstrb,



  input [3:0]             bid,
  input [1:0]             bresp,
  input                   bvalid,
  output                  bready


);

  wire cpu_clk;



  localparam integer B_SAMPLE_CNT_MAX = 0.0005 * CPU_CLOCK_FREQ;

  localparam integer B_PULSE_CNT_MAX = 0.100 / 0.0005;

  wire [3:0] buttons_pressed;
  button_parser #(
    .WIDTH(4),
    .SAMPLE_CNT_MAX(B_SAMPLE_CNT_MAX),
    .PULSE_CNT_MAX(B_PULSE_CNT_MAX)
  ) bp (
    .clk(axi_clk),
    .in(BUTTONS),
    .out(buttons_pressed)
  );

  wire reset = (buttons_pressed[0] & SWITCHES[1]);

  wire [31:0] csr;

  localparam DMEM_AWIDTH = 14;
  localparam DMEM_DWIDTH = 32;

  wire dma_start, dma_done, dma_idle, dma_dir;
  wire [31:0] dma_src_addr, dma_dst_addr, dma_len;

  wire xcel_start, xcel_idle, xcel_done;

  wire [31:0] ifm_ddr_addr, wt_ddr_addr, ofm_ddr_addr;
  wire [31:0] ifm_dim;
  wire [31:0] ifm_depth;

  wire [31:0] wt_depth;

  wire [31:0] ofm_dim;
  wire [31:0] ofm_depth;

  wire [DMEM_AWIDTH-1:0] dmem_addrb;
  wire [DMEM_DWIDTH-1:0] dmem_dinb, dmem_doutb;
  wire [3:0]  dmem_web;
  wire dmem_enb;

  Riscv151 #(
    .CPU_CLOCK_FREQ(CPU_CLOCK_FREQ)
  ) cpu (
    .clk(axi_clk),
    .rst(reset),
    .FPGA_SERIAL_TX(FPGA_SERIAL_TX),
    .FPGA_SERIAL_RX(FPGA_SERIAL_RX),
    .csr(csr),


    .xcel_start(xcel_start),
    .xcel_idle(xcel_idle & (~xcel_start)),
    .xcel_done(xcel_done & (~xcel_start)),

    .ifm_ddr_addr(ifm_ddr_addr),
    .wt_ddr_addr(wt_ddr_addr),
    .ofm_ddr_addr(ofm_ddr_addr),

    .ifm_dim(ifm_dim),
    .ifm_depth(ifm_depth),

    .ofm_dim(ofm_dim),
    .ofm_depth(ofm_depth),


    .dma_start(dma_start),
    .dma_done(dma_done & (~dma_start)),
    .dma_idle(dma_idle & (~dma_start)),
    .dma_dir(dma_dir),
    .dma_src_addr(dma_src_addr),
    .dma_dst_addr(dma_dst_addr),
    .dma_len(dma_len),


    .dmem_addrb(dmem_addrb),
    .dmem_dinb(dmem_dinb),
    .dmem_doutb(dmem_doutb),
    .dmem_web(dmem_web),
    .dmem_enb(dmem_enb)
  );

  assign LEDS[5:4] = 2'b11;

  wire                  core_read_request_valid;
  wire                  core_read_request_ready;
  wire [AXI_AWIDTH-1:0] core_read_addr;
  wire [31:0]           core_read_len;
  wire [2:0]            core_read_size;
  wire [1:0]            core_read_burst;
  wire [AXI_DWIDTH-1:0] core_read_data;
  wire                  core_read_data_valid;
  wire                  core_read_data_ready;

  wire                  core_write_request_valid;
  wire                  core_write_request_ready;
  wire [AXI_AWIDTH-1:0] core_write_addr;
  wire [31:0]           core_write_len;
  wire [2:0]            core_write_size;
  wire [1:0]            core_write_burst;
  wire [AXI_DWIDTH-1:0] core_write_data;
  wire                  core_write_data_valid;
  wire                  core_write_data_ready;

  axi_mm_adapter #(
    .AXI_AWIDTH(AXI_AWIDTH),
    .AXI_DWIDTH(AXI_DWIDTH)
  ) axi_mm_core (
    .clk(axi_clk),
    .resetn(axi_resetn | ~reset),

    .arid(arid),
    .araddr(araddr),
    .arvalid(arvalid),
    .arready(arready),
    .arlen(arlen),
    .arsize(arsize),
    .arburst(arburst),

    .rid(rid),
    .rdata(rdata),
    .rvalid(rvalid),
    .rready(rready),
    .rlast(rlast),
    .rresp(rresp),

    .awid(awid),
    .awaddr(awaddr),
    .awvalid(awvalid),
    .awready(awready),
    .awlen(awlen),
    .awsize(awsize),
    .awburst(awburst),

    .wid(wid),
    .wdata(wdata),
    .wvalid(wvalid),
    .wready(wready),
    .wlast(wlast),
    .wstrb(wstrb),

    .bid(bid),
    .bresp(bresp),
    .bvalid(bvalid),
    .bready(bready),

    .core_read_request_valid(core_read_request_valid),
    .core_read_request_ready(core_read_request_ready),
    .core_read_addr(core_read_addr),
    .core_read_len(core_read_len),
    .core_read_size(core_read_size),
    .core_read_burst(core_read_burst),
    .core_read_data(core_read_data),
    .core_read_data_valid(core_read_data_valid),
    .core_read_data_ready(core_read_data_ready),

    .core_write_request_valid(core_write_request_valid),
    .core_write_request_ready(core_write_request_ready),
    .core_write_addr(core_write_addr),
    .core_write_len(core_write_len),
    .core_write_size(core_write_size),
    .core_write_burst(core_write_burst),
    .core_write_data(core_write_data),
    .core_write_data_valid(core_write_data_valid),
    .core_write_data_ready(core_write_data_ready)
  );

  wire                  dma_read_request_valid;
  wire                  dma_read_request_ready;
  wire [AXI_AWIDTH-1:0] dma_read_addr;
  wire [31:0]           dma_read_len;
  wire [2:0]            dma_read_size;
  wire [1:0]            dma_read_burst;
  wire [AXI_DWIDTH-1:0] dma_read_data;
  wire                  dma_read_data_valid;
  wire                  dma_read_data_ready;

  wire                  dma_write_request_valid;
  wire                  dma_write_request_ready;
  wire [AXI_AWIDTH-1:0] dma_write_addr;
  wire [31:0]           dma_write_len;
  wire [2:0]            dma_write_size;
  wire [1:0]            dma_write_burst;
  wire [AXI_DWIDTH-1:0] dma_write_data;
  wire                  dma_write_data_valid;
  wire                  dma_write_data_ready;

  dma_controller #(
    .AXI_AWIDTH(AXI_AWIDTH),
    .AXI_DWIDTH(AXI_DWIDTH),
    .DMEM_AWIDTH(DMEM_AWIDTH),
    .DMEM_DWIDTH(DMEM_DWIDTH)
  ) dma_unit (
    .clk(axi_clk),
    .resetn(axi_resetn | ~reset),

    .dma_read_request_valid(dma_read_request_valid),
    .dma_read_request_ready(dma_read_request_ready),
    .dma_read_addr(dma_read_addr),
    .dma_read_len(dma_read_len),
    .dma_read_size(dma_read_size),
    .dma_read_burst(dma_read_burst),
    .dma_read_data(dma_read_data),
    .dma_read_data_valid(dma_read_data_valid),
    .dma_read_data_ready(dma_read_data_ready),

    .dma_write_request_valid(dma_write_request_valid),
    .dma_write_request_ready(dma_write_request_ready),
    .dma_write_addr(dma_write_addr),
    .dma_write_len(dma_write_len),
    .dma_write_size(dma_write_size),
    .dma_write_burst(dma_write_burst),
    .dma_write_data(dma_write_data),
    .dma_write_data_valid(dma_write_data_valid),
    .dma_write_data_ready(dma_write_data_ready),

    .dma_start(dma_start),
    .dma_done(dma_done),
    .dma_idle(dma_idle),
    .dma_dir(dma_dir),
    .dma_src_addr(dma_src_addr),
    .dma_dst_addr(dma_dst_addr),
    .dma_len(dma_len),

    .dmem_addr(dmem_addrb),
    .dmem_din(dmem_dinb),
    .dmem_dout(dmem_doutb),
    .dmem_wbe(dmem_web),
    .dmem_en(dmem_enb)
  );

  wire                  xcel_read_request_valid;
  wire                  xcel_read_request_ready;
  wire [AXI_AWIDTH-1:0] xcel_read_addr;
  wire [31:0]           xcel_read_len;
  wire [2:0]            xcel_read_size;
  wire [1:0]            xcel_read_burst;
  wire [AXI_DWIDTH-1:0] xcel_read_data;
  wire                  xcel_read_data_valid;
  wire                  xcel_read_data_ready;

  wire                  xcel_write_request_valid;
  wire                  xcel_write_request_ready;
  wire [AXI_AWIDTH-1:0] xcel_write_addr;
  wire [31:0]           xcel_write_len;
  wire [2:0]            xcel_write_size;
  wire [1:0]            xcel_write_burst;
  wire [AXI_DWIDTH-1:0] xcel_write_data;
  wire                  xcel_write_data_valid;
  wire                  xcel_write_data_ready;

  xcel_naive #(
    .AXI_AWIDTH(AXI_AWIDTH),
    .AXI_DWIDTH(AXI_DWIDTH)
  ) xcel_unit (
    .clk(axi_clk),
    .rst(~axi_resetn | reset),

    .xcel_read_request_valid(xcel_read_request_valid),
    .xcel_read_request_ready(xcel_read_request_ready),
    .xcel_read_addr(xcel_read_addr),
    .xcel_read_len(xcel_read_len),
    .xcel_read_size(xcel_read_size),
    .xcel_read_burst(xcel_read_burst),
    .xcel_read_data(xcel_read_data),
    .xcel_read_data_valid(xcel_read_data_valid),
    .xcel_read_data_ready(xcel_read_data_ready),

    .xcel_write_request_valid(xcel_write_request_valid),
    .xcel_write_request_ready(xcel_write_request_ready),
    .xcel_write_addr(xcel_write_addr),
    .xcel_write_len(xcel_write_len),
    .xcel_write_size(xcel_write_size),
    .xcel_write_burst(xcel_write_burst),
    .xcel_write_data(xcel_write_data),
    .xcel_write_data_valid(xcel_write_data_valid),
    .xcel_write_data_ready(xcel_write_data_ready),

    .xcel_start(xcel_start),
    .xcel_done(xcel_done),
    .xcel_idle(xcel_idle),

    .ifm_ddr_addr(ifm_ddr_addr),
    .wt_ddr_addr(wt_ddr_addr),
    .ofm_ddr_addr(ofm_ddr_addr),

    .ifm_dim(ifm_dim),
    .ifm_depth(ifm_depth),

    .ofm_dim(ofm_dim),
    .ofm_depth(ofm_depth)
  );

  wire xcel_busy;



  REGISTER_R_CE #(.N(1)) acc_busy_reg (
    .clk(axi_clk),
    .rst((xcel_done & ~xcel_start) | ~axi_resetn | reset),
    .d(1'b1),
    .q(xcel_busy),
    .ce(xcel_start)
  );


  arbiter #(
    .AXI_AWIDTH(AXI_AWIDTH),
    .AXI_DWIDTH(AXI_DWIDTH)
  ) arb (

    .xcel_busy(xcel_busy),


    .core_read_request_valid(core_read_request_valid),
    .core_read_request_ready(core_read_request_ready),
    .core_read_addr(core_read_addr),
    .core_read_len(core_read_len),
    .core_read_size(core_read_size),
    .core_read_burst(core_read_burst),
    .core_read_data(core_read_data),
    .core_read_data_valid(core_read_data_valid),
    .core_read_data_ready(core_read_data_ready),

    .core_write_request_valid(core_write_request_valid),
    .core_write_request_ready(core_write_request_ready),
    .core_write_addr(core_write_addr),
    .core_write_len(core_write_len),
    .core_write_size(core_write_size),
    .core_write_burst(core_write_burst),
    .core_write_data(core_write_data),
    .core_write_data_valid(core_write_data_valid),
    .core_write_data_ready(core_write_data_ready),


    .dma_read_request_valid(dma_read_request_valid),
    .dma_read_request_ready(dma_read_request_ready),
    .dma_read_addr(dma_read_addr),
    .dma_read_len(dma_read_len),
    .dma_read_size(dma_read_size),
    .dma_read_burst(dma_read_burst),
    .dma_read_data(dma_read_data),
    .dma_read_data_valid(dma_read_data_valid),
    .dma_read_data_ready(dma_read_data_ready),

    .dma_write_request_valid(dma_write_request_valid),
    .dma_write_request_ready(dma_write_request_ready),
    .dma_write_addr(dma_write_addr),
    .dma_write_len(dma_write_len),
    .dma_write_size(dma_write_size),
    .dma_write_burst(dma_write_burst),
    .dma_write_data(dma_write_data),
    .dma_write_data_valid(dma_write_data_valid),
    .dma_write_data_ready(dma_write_data_ready),


    .xcel_read_request_valid(xcel_read_request_valid),
    .xcel_read_request_ready(xcel_read_request_ready),
    .xcel_read_addr(xcel_read_addr),
    .xcel_read_len(xcel_read_len),
    .xcel_read_size(xcel_read_size),
    .xcel_read_burst(xcel_read_burst),
    .xcel_read_data(xcel_read_data),
    .xcel_read_data_valid(xcel_read_data_valid),
    .xcel_read_data_ready(xcel_read_data_ready),

    .xcel_write_request_valid(xcel_write_request_valid),
    .xcel_write_request_ready(xcel_write_request_ready),
    .xcel_write_addr(xcel_write_addr),
    .xcel_write_len(xcel_write_len),
    .xcel_write_size(xcel_write_size),
    .xcel_write_burst(xcel_write_burst),
    .xcel_write_data(xcel_write_data),
    .xcel_write_data_valid(xcel_write_data_valid),
    .xcel_write_data_ready(xcel_write_data_ready)
  );

endmodule
module z1top_axi #(
  parameter AXI_AWIDTH = 32,
  parameter AXI_DWIDTH = 32,
  parameter AXI_MAX_BURST_LEN = 256,
  parameter CPU_CLOCK_FREQ = 50_000_000
) (
  input  CLK_125MHZ_FPGA,
  input  [3:0] BUTTONS,
  input  [1:0] SWITCHES,
  output [5:0] LEDS,

  input  FPGA_SERIAL_RX,
  output FPGA_SERIAL_TX,


  input axi_clk,
  input axi_resetn,


  output [3:0]            arid,
  output [AXI_AWIDTH-1:0] araddr,
  output                  arvalid,
  input                   arready,
  output [7:0]            arlen,
  output [2:0]            arsize,
  output [1:0]            arburst,



  input [3:0]             rid,
  input [AXI_DWIDTH-1:0]  rdata,
  input                   rvalid,
  output                  rready,
  input                   rlast,
  input [1:0]             rresp,



  output [3:0]            awid,
  output [AXI_AWIDTH-1:0] awaddr,
  output                  awvalid,
  input                   awready,
  output [7:0]            awlen,
  output [2:0]            awsize,
  output [1:0]            awburst,



  output [3:0]            wid,
  output [AXI_DWIDTH-1:0] wdata,
  output                  wvalid,
  input                   wready,
  output                  wlast,
  output [AXI_DWIDTH/8-1:0] wstrb,



  input [3:0]             bid,
  input [1:0]             bresp,
  input                   bvalid,
  output                  bready


);


  wire cpu_clk;



  localparam integer B_SAMPLE_CNT_MAX = 0.0005 * CPU_CLOCK_FREQ;

  localparam integer B_PULSE_CNT_MAX = 0.100 / 0.0005;

  wire [3:0] buttons_pressed;
  button_parser #(
    .WIDTH(4),
    .SAMPLE_CNT_MAX(B_SAMPLE_CNT_MAX),
    .PULSE_CNT_MAX(B_PULSE_CNT_MAX)
  ) bp (
    .clk(axi_clk),
    .in(BUTTONS),
    .out(buttons_pressed)
  );

  wire reset = (buttons_pressed[0] & SWITCHES[1]);

  wire [31:0] csr;

  localparam DMEM_AWIDTH = 14;
  localparam DMEM_DWIDTH = 32;

  wire dma_start, dma_done, dma_idle, dma_dir;
  wire [31:0] dma_src_addr, dma_dst_addr, dma_len;

  wire xcel_start, xcel_idle, xcel_done;

  wire [31:0] ifm_ddr_addr, wt_ddr_addr, ofm_ddr_addr;
  wire [31:0] ifm_dim;
  wire [31:0] ifm_depth;

  wire [31:0] wt_depth;

  wire [31:0] ofm_dim;
  wire [31:0] ofm_depth;

  wire [DMEM_AWIDTH-1:0] dmem_addrb;
  wire [DMEM_DWIDTH-1:0] dmem_dinb, dmem_doutb;
  wire [3:0]  dmem_web;
  wire dmem_enb;

  Riscv151 #(
    .CPU_CLOCK_FREQ(CPU_CLOCK_FREQ)
  ) cpu (
    .clk(axi_clk),
    .rst(reset),
    .FPGA_SERIAL_TX(FPGA_SERIAL_TX),
    .FPGA_SERIAL_RX(FPGA_SERIAL_RX),
    .csr(csr),


    .xcel_start(xcel_start),
    .xcel_idle(xcel_idle & (~xcel_start)),
    .xcel_done(xcel_done & (~xcel_start)),

    .ifm_ddr_addr(ifm_ddr_addr),
    .wt_ddr_addr(wt_ddr_addr),
    .ofm_ddr_addr(ofm_ddr_addr),

    .ifm_dim(ifm_dim),
    .ifm_depth(ifm_depth),

    .ofm_dim(ofm_dim),
    .ofm_depth(ofm_depth),


    .dma_start(dma_start),
    .dma_done(dma_done & (~dma_start)),
    .dma_idle(dma_idle & (~dma_start)),
    .dma_dir(dma_dir),
    .dma_src_addr(dma_src_addr),
    .dma_dst_addr(dma_dst_addr),
    .dma_len(dma_len),


    .dmem_addrb(dmem_addrb),
    .dmem_dinb(dmem_dinb),
    .dmem_doutb(dmem_doutb),
    .dmem_web(dmem_web),
    .dmem_enb(dmem_enb)
  );

  assign LEDS[5:4] = 2'b11;

  wire                  core_read_request_valid;
  wire                  core_read_request_ready;
  wire [AXI_AWIDTH-1:0] core_read_addr;
  wire [31:0]           core_read_len;
  wire [2:0]            core_read_size;
  wire [1:0]            core_read_burst;
  wire [AXI_DWIDTH-1:0] core_read_data;
  wire                  core_read_data_valid;
  wire                  core_read_data_ready;

  wire                  core_write_request_valid;
  wire                  core_write_request_ready;
  wire [AXI_AWIDTH-1:0] core_write_addr;
  wire [31:0]           core_write_len;
  wire [2:0]            core_write_size;
  wire [1:0]            core_write_burst;
  wire [AXI_DWIDTH-1:0] core_write_data;
  wire                  core_write_data_valid;
  wire                  core_write_data_ready;

  axi_mm_adapter #(
    .AXI_AWIDTH(AXI_AWIDTH),
    .AXI_DWIDTH(AXI_DWIDTH)
  ) axi_mm_core (
    .clk(axi_clk),
    .resetn(axi_resetn | ~reset),

    .arid(arid),
    .araddr(araddr),
    .arvalid(arvalid),
    .arready(arready),
    .arlen(arlen),
    .arsize(arsize),
    .arburst(arburst),

    .rid(rid),
    .rdata(rdata),
    .rvalid(rvalid),
    .rready(rready),
    .rlast(rlast),
    .rresp(rresp),

    .awid(awid),
    .awaddr(awaddr),
    .awvalid(awvalid),
    .awready(awready),
    .awlen(awlen),
    .awsize(awsize),
    .awburst(awburst),

    .wid(wid),
    .wdata(wdata),
    .wvalid(wvalid),
    .wready(wready),
    .wlast(wlast),
    .wstrb(wstrb),

    .bid(bid),
    .bresp(bresp),
    .bvalid(bvalid),
    .bready(bready),

    .core_read_request_valid(core_read_request_valid),
    .core_read_request_ready(core_read_request_ready),
    .core_read_addr(core_read_addr),
    .core_read_len(core_read_len),
    .core_read_size(core_read_size),
    .core_read_burst(core_read_burst),
    .core_read_data(core_read_data),
    .core_read_data_valid(core_read_data_valid),
    .core_read_data_ready(core_read_data_ready),

    .core_write_request_valid(core_write_request_valid),
    .core_write_request_ready(core_write_request_ready),
    .core_write_addr(core_write_addr),
    .core_write_len(core_write_len),
    .core_write_size(core_write_size),
    .core_write_burst(core_write_burst),
    .core_write_data(core_write_data),
    .core_write_data_valid(core_write_data_valid),
    .core_write_data_ready(core_write_data_ready)
  );

  wire                  dma_read_request_valid;
  wire                  dma_read_request_ready;
  wire [AXI_AWIDTH-1:0] dma_read_addr;
  wire [31:0]           dma_read_len;
  wire [2:0]            dma_read_size;
  wire [1:0]            dma_read_burst;
  wire [AXI_DWIDTH-1:0] dma_read_data;
  wire                  dma_read_data_valid;
  wire                  dma_read_data_ready;

  wire                  dma_write_request_valid;
  wire                  dma_write_request_ready;
  wire [AXI_AWIDTH-1:0] dma_write_addr;
  wire [31:0]           dma_write_len;
  wire [2:0]            dma_write_size;
  wire [1:0]            dma_write_burst;
  wire [AXI_DWIDTH-1:0] dma_write_data;
  wire                  dma_write_data_valid;
  wire                  dma_write_data_ready;

  dma_controller #(
    .AXI_AWIDTH(AXI_AWIDTH),
    .AXI_DWIDTH(AXI_DWIDTH),
    .DMEM_AWIDTH(DMEM_AWIDTH),
    .DMEM_DWIDTH(DMEM_DWIDTH)
  ) dma_unit (
    .clk(axi_clk),
    .resetn(axi_resetn | ~reset),

    .dma_read_request_valid(dma_read_request_valid),
    .dma_read_request_ready(dma_read_request_ready),
    .dma_read_addr(dma_read_addr),
    .dma_read_len(dma_read_len),
    .dma_read_size(dma_read_size),
    .dma_read_burst(dma_read_burst),
    .dma_read_data(dma_read_data),
    .dma_read_data_valid(dma_read_data_valid),
    .dma_read_data_ready(dma_read_data_ready),

    .dma_write_request_valid(dma_write_request_valid),
    .dma_write_request_ready(dma_write_request_ready),
    .dma_write_addr(dma_write_addr),
    .dma_write_len(dma_write_len),
    .dma_write_size(dma_write_size),
    .dma_write_burst(dma_write_burst),
    .dma_write_data(dma_write_data),
    .dma_write_data_valid(dma_write_data_valid),
    .dma_write_data_ready(dma_write_data_ready),

    .dma_start(dma_start),
    .dma_done(dma_done),
    .dma_idle(dma_idle),
    .dma_dir(dma_dir),
    .dma_src_addr(dma_src_addr),
    .dma_dst_addr(dma_dst_addr),
    .dma_len(dma_len),

    .dmem_addr(dmem_addrb),
    .dmem_din(dmem_dinb),
    .dmem_dout(dmem_doutb),
    .dmem_wbe(dmem_web),
    .dmem_en(dmem_enb)
  );

  wire                  xcel_read_request_valid;
  wire                  xcel_read_request_ready;
  wire [AXI_AWIDTH-1:0] xcel_read_addr;
  wire [31:0]           xcel_read_len;
  wire [2:0]            xcel_read_size;
  wire [1:0]            xcel_read_burst;
  wire [AXI_DWIDTH-1:0] xcel_read_data;
  wire                  xcel_read_data_valid;
  wire                  xcel_read_data_ready;

  wire                  xcel_write_request_valid;
  wire                  xcel_write_request_ready;
  wire [AXI_AWIDTH-1:0] xcel_write_addr;
  wire [31:0]           xcel_write_len;
  wire [2:0]            xcel_write_size;
  wire [1:0]            xcel_write_burst;
  wire [AXI_DWIDTH-1:0] xcel_write_data;
  wire                  xcel_write_data_valid;
  wire                  xcel_write_data_ready;

  xcel_naive #(
    .AXI_AWIDTH(AXI_AWIDTH),
    .AXI_DWIDTH(AXI_DWIDTH)
  ) xcel_unit (
    .clk(axi_clk),
    .rst(~axi_resetn | reset),

    .xcel_read_request_valid(xcel_read_request_valid),
    .xcel_read_request_ready(xcel_read_request_ready),
    .xcel_read_addr(xcel_read_addr),
    .xcel_read_len(xcel_read_len),
    .xcel_read_size(xcel_read_size),
    .xcel_read_burst(xcel_read_burst),
    .xcel_read_data(xcel_read_data),
    .xcel_read_data_valid(xcel_read_data_valid),
    .xcel_read_data_ready(xcel_read_data_ready),

    .xcel_write_request_valid(xcel_write_request_valid),
    .xcel_write_request_ready(xcel_write_request_ready),
    .xcel_write_addr(xcel_write_addr),
    .xcel_write_len(xcel_write_len),
    .xcel_write_size(xcel_write_size),
    .xcel_write_burst(xcel_write_burst),
    .xcel_write_data(xcel_write_data),
    .xcel_write_data_valid(xcel_write_data_valid),
    .xcel_write_data_ready(xcel_write_data_ready),

    .xcel_start(xcel_start),
    .xcel_done(xcel_done),
    .xcel_idle(xcel_idle),

    .ifm_ddr_addr(ifm_ddr_addr),
    .wt_ddr_addr(wt_ddr_addr),
    .ofm_ddr_addr(ofm_ddr_addr),

    .ifm_dim(ifm_dim),
    .ifm_depth(ifm_depth),

    .ofm_dim(ofm_dim),
    .ofm_depth(ofm_depth)
  );

  wire xcel_busy;



  REGISTER_R_CE #(.N(1)) acc_busy_reg (
    .clk(axi_clk),
    .rst((xcel_done & ~xcel_start) | ~axi_resetn | reset),
    .d(1'b1),
    .q(xcel_busy),
    .ce(xcel_start)
  );


  arbiter #(
    .AXI_AWIDTH(AXI_AWIDTH),
    .AXI_DWIDTH(AXI_DWIDTH)
  ) arb (

    .xcel_busy(xcel_busy),


    .core_read_request_valid(core_read_request_valid),
    .core_read_request_ready(core_read_request_ready),
    .core_read_addr(core_read_addr),
    .core_read_len(core_read_len),
    .core_read_size(core_read_size),
    .core_read_burst(core_read_burst),
    .core_read_data(core_read_data),
    .core_read_data_valid(core_read_data_valid),
    .core_read_data_ready(core_read_data_ready),

    .core_write_request_valid(core_write_request_valid),
    .core_write_request_ready(core_write_request_ready),
    .core_write_addr(core_write_addr),
    .core_write_len(core_write_len),
    .core_write_size(core_write_size),
    .core_write_burst(core_write_burst),
    .core_write_data(core_write_data),
    .core_write_data_valid(core_write_data_valid),
    .core_write_data_ready(core_write_data_ready),


    .dma_read_request_valid(dma_read_request_valid),
    .dma_read_request_ready(dma_read_request_ready),
    .dma_read_addr(dma_read_addr),
    .dma_read_len(dma_read_len),
    .dma_read_size(dma_read_size),
    .dma_read_burst(dma_read_burst),
    .dma_read_data(dma_read_data),
    .dma_read_data_valid(dma_read_data_valid),
    .dma_read_data_ready(dma_read_data_ready),

    .dma_write_request_valid(dma_write_request_valid),
    .dma_write_request_ready(dma_write_request_ready),
    .dma_write_addr(dma_write_addr),
    .dma_write_len(dma_write_len),
    .dma_write_size(dma_write_size),
    .dma_write_burst(dma_write_burst),
    .dma_write_data(dma_write_data),
    .dma_write_data_valid(dma_write_data_valid),
    .dma_write_data_ready(dma_write_data_ready),


    .xcel_read_request_valid(xcel_read_request_valid),
    .xcel_read_request_ready(xcel_read_request_ready),
    .xcel_read_addr(xcel_read_addr),
    .xcel_read_len(xcel_read_len),
    .xcel_read_size(xcel_read_size),
    .xcel_read_burst(xcel_read_burst),
    .xcel_read_data(xcel_read_data),
    .xcel_read_data_valid(xcel_read_data_valid),
    .xcel_read_data_ready(xcel_read_data_ready),

    .xcel_write_request_valid(xcel_write_request_valid),
    .xcel_write_request_ready(xcel_write_request_ready),
    .xcel_write_addr(xcel_write_addr),
    .xcel_write_len(xcel_write_len),
    .xcel_write_size(xcel_write_size),
    .xcel_write_burst(xcel_write_burst),
    .xcel_write_data(xcel_write_data),
    .xcel_write_data_valid(xcel_write_data_valid),
    .xcel_write_data_ready(xcel_write_data_ready)
  );

endmodule