data/full_repos/permissive/437141606/mipstest.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/437141606/mipstest.v:23: Unsupported: Ignoring delay on this delayed statement.\n  reset <= 1; # 22; reset <= 0;\n              ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/437141606/mipstest.v:30: Unsupported: Ignoring delay on this delayed statement.\n  clk <= 1; # 5; clk <= 0; # 5;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/437141606/mipstest.v:30: Unsupported: Ignoring delay on this delayed statement.\n  clk <= 1; # 5; clk <= 0; # 5;\n                           ^\n%Warning-STMTDLY: data/full_repos/permissive/437141606/mipstest.v:44: Unsupported: Ignoring delay on this delayed statement.\n  dispSel = 5\'d16; #15;  \n                   ^\n%Warning-STMTDLY: data/full_repos/permissive/437141606/mipstest.v:59: Unsupported: Ignoring delay on this delayed statement.\n  dispSel = 5\'d8; #15;  \n                  ^\n%Error: data/full_repos/permissive/437141606/mipstest.v:17: Cannot find file containing module: \'mips\'\n mips dut(clk, reset, writedata, dataadr, memwrite, dispSel, dispDat, pc, instr);\n ^~~~\n        ... Looked in:\n             data/full_repos/permissive/437141606,data/full_repos/permissive/437141606/mips\n             data/full_repos/permissive/437141606,data/full_repos/permissive/437141606/mips.v\n             data/full_repos/permissive/437141606,data/full_repos/permissive/437141606/mips.sv\n             mips\n             mips.v\n             mips.sv\n             obj_dir/mips\n             obj_dir/mips.v\n             obj_dir/mips.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();

	reg     clk;
	reg     reset;
	reg[4:0]dispSel;		  
	reg[31:0] IC;
	wire[31:0] writedata, dataadr,dispDat, pc, instr;
	wire	   memwrite;


	mips dut(clk, reset, writedata, dataadr, memwrite, dispSel, dispDat, pc, instr);
  

	initial
	begin
		dispSel <= 5'd4; IC <= 1;
		reset <= 1; # 22; reset <= 0;
   end

	

	always
	begin
		clk <= 1; # 5; clk <= 0; # 5;
   end

	always@(negedge clk)
    begin
		if(reset != 1)
			IC = IC +1;
			
		if(IC == 32'h90)
			$stop;
			

      if(pc[7:0]== 8'h5C)
		begin
		dispSel = 5'd16; #15;
        if(dispSel == 5'd16 && dispDat == 32'd24)
		  begin
			$display("addi, add, sw, lw, beg, jal, jr, j, multu, mflo funtion correctly.");
        end
		  else
		  begin
			$display("Simulation failed - 1st test");
			$stop;
        end
      end
		

		if(pc[7:0]== 8'h80)
		begin
		dispSel = 5'd8; #15;
        if(dispSel == 5'd8 && dispDat == 32'h3520F3A3)
		  begin
			$display("multu, mflo, mfhi, and, or function correctly.");
			$display("Simulation succeeded.");
			$stop;
        end
		  else
		  begin
			$display("Simulation failed - 2nd test");
			$stop;
        end
      end
		
    end
endmodule
module testbench();


	reg     clk;
	reg     reset;
	reg[4:0]dispSel;		  
	reg[31:0] IC;
	wire[31:0] writedata, dataadr,dispDat, pc, instr;
	wire	   memwrite;


	mips dut(clk, reset, writedata, dataadr, memwrite, dispSel, dispDat, pc, instr);
  

	initial
	begin
		dispSel <= 5'd4; IC <= 1;
		reset <= 1; # 22; reset <= 0;
   end

	

	always
	begin
		clk <= 1; # 5; clk <= 0; # 5;
   end

	always@(negedge clk)
    begin
		if(reset != 1)
			IC = IC +1;
			
		if(IC == 32'h90)
			$stop;
			

      if(pc[7:0]== 8'h5C)
		begin
		dispSel = 5'd16; #15;
        if(dispSel == 5'd16 && dispDat == 32'd24)
		  begin
			$display("addi, add, sw, lw, beg, jal, jr, j, multu, mflo funtion correctly.");
        end
		  else
		  begin
			$display("Simulation failed - 1st test");
			$stop;
        end
      end
		

		if(pc[7:0]== 8'h80)
		begin
		dispSel = 5'd8; #15;
        if(dispSel == 5'd8 && dispDat == 32'h3520F3A3)
		  begin
			$display("multu, mflo, mfhi, and, or function correctly.");
			$display("Simulation succeeded.");
			$stop;
        end
		  else
		  begin
			$display("Simulation failed - 2nd test");
			$stop;
        end
      end
		
    end
endmodule