data/full_repos/permissive/405799749/amg_new/mult/Unsigned/9/5/Simple_PPG/Wallace_tree/Han-Carlson_adder/module.v
data/verilator_xmls/72e5ceb7-1230-456d-98d4-39e8ca0391a6.xml
module WLCTR_8_0_9_1_10_000 (S1, S2, PP0, PP1, PP2, PP3, PP4);
  output [12:4] S1;
  output [12:0] S2;
  input [8:0] PP0;
  input [9:1] PP1;
  input [10:2] PP2;
  input [11:3] PP3;
  input [12:4] PP4;
  wire [10:2] IC0;
  wire [11:3] IC1;
  wire [10:0] IS0;
  wire [11:0] IS1;
  CSA_8_0_9_1_10_2 U0 (IC0, IS0, PP0, PP1, PP2);
  CSA_10_0_10_2_11_000 U1 (IC1, IS1, IS0, IC0, PP3);
  CSA_11_0_11_3_12_000 U2 (S1, S2, IS1, IC1, PP4);
endmodule
module WLCTR_8_0_9_1_10_000 (S1, S2, PP0, PP1, PP2, PP3, PP4);

  output [12:4] S1;
  output [12:0] S2;
  input [8:0] PP0;
  input [9:1] PP1;
  input [10:2] PP2;
  input [11:3] PP3;
  input [12:4] PP4;
  wire [10:2] IC0;
  wire [11:3] IC1;
  wire [10:0] IS0;
  wire [11:0] IS1;
  CSA_8_0_9_1_10_2 U0 (IC0, IS0, PP0, PP1, PP2);
  CSA_10_0_10_2_11_000 U1 (IC1, IS1, IS0, IC0, PP3);
  CSA_11_0_11_3_12_000 U2 (S1, S2, IS1, IC1, PP4);
endmodule