data/full_repos/permissive/509335294/processor.v
1: b"%Error: data/full_repos/permissive/509335294/processor.v:5: syntax error, unexpected ')', expecting '['\n     );\n     ^\n%Error: data/full_repos/permissive/509335294/processor.v:48: syntax error, unexpected IDENTIFIER\nctu     ctu( instr_line[15:13],  \n^~~\n%Error: Exiting due to 2 error(s)\n"
module processor(
					input clk, rst,

					);


	wire[15:0] 	instr_line, 
						ext_line, 
						reg_out1, 
						reg_out2, 
						wdr, 
						mem_out, 
						alu_result,

						alu_input2;
	
	wire[12:0] 	pc_p2, 
						pc_loopback,
						curr_pc, 

						brch_res,
						brch_out,
						jmp_out;
						
	wire[3:0] 		alu_sel;

	wire[2:0]		wr;
	
	wire[1:0] 		regdst, 
						aluop, 
						memtoreg;

	wire 				jump, 

						mem_re, 
						mem_we, 
						alusrc, 
						reg_we, 
						jrmux_en; 



	wire clk, rst;



ctu 				ctu(	instr_line[15:13],
							clk, 						
							regdst, 				
							jump, 
							branch, 
							mem_re, 
							memtoreg, 
							aluop, 
							mem_we, 
							alusrc, 
							reg_we
							);
alu_control 	alu_contrl(		aluop, 
							instr_line[3:0],
							clk,
							alu_sel
							);
alu				alu(	reg_out1,
							alu_input2,  
							alu_sel,

							alu_brch_en,
							alu_result
							);
sign_extend	sign_ext(
							instr_line[6:0], 
							ext_line
							); 
prog_count 	proc(		pc_loopback, 
							clk, 
							rst,
							curr_pc
							);
jrcontrol	jr_control(		instr_line[3:0], 
							aluop, 
							clk, 
							jrmux_en
							);
amod1		andgate(		branch, 
							alu_brch_en,
							brch_en
							);
brch_add 	brch_adder( pc_p2,
							ext_line[12:0],

							brch_res
							);
pc_add		pc_adder(
							curr_pc,
							13'b1,

							pc_p2
							);



regdestmux		muxregdst(		instr_line[9:7], 	
								instr_line[6:4], 			
								regdst,
								wr
								);
memtoregmux	muxdatamem(	alu_result,
								mem_out,
								pc_p2,
								memtoreg,
								wdr
								);
alusrcmux		muxalusource(	reg_out2, 
								ext_line,
								alusrc,
								alu_input2
								);
brchmux			muxbranch(		pc_p2, 
								brch_res,
								brch_en, 
								brch_out
								);
jmpmux			muxjump(		brch_out,  
								instr_line[12:0], 
								jump,
								jmp_out
								);
jrmux				muxjumpreg(	jmp_out, 
								reg_out1,
								jrmux_en,
								pc_loopback
								);




regmem 			regmem(	wdr[15:0],
								instr_line[12:10],
								instr_line[9:7],
								wr,
								clk, 
								rst, 
								reg_we, 
								reg_out1,
								reg_out2
								);
datamem 			datamem(	reg_out2,
								alu_result,
								clk, 

								mem_we, 
								mem_re, 
								mem_out
								);
instrmem			instrmem(	curr_pc, 
								clk,
								rst,
								instr_line
								); 

endmodule
module processor(
					input clk, rst,

					);



	wire[15:0] 	instr_line, 
						ext_line, 
						reg_out1, 
						reg_out2, 
						wdr, 
						mem_out, 
						alu_result,

						alu_input2;
	
	wire[12:0] 	pc_p2, 
						pc_loopback,
						curr_pc, 

						brch_res,
						brch_out,
						jmp_out;
						
	wire[3:0] 		alu_sel;

	wire[2:0]		wr;
	
	wire[1:0] 		regdst, 
						aluop, 
						memtoreg;

	wire 				jump, 

						mem_re, 
						mem_we, 
						alusrc, 
						reg_we, 
						jrmux_en; 



	wire clk, rst;



ctu 				ctu(	instr_line[15:13],
							clk, 						
							regdst, 				
							jump, 
							branch, 
							mem_re, 
							memtoreg, 
							aluop, 
							mem_we, 
							alusrc, 
							reg_we
							);
alu_control 	alu_contrl(		aluop, 
							instr_line[3:0],
							clk,
							alu_sel
							);
alu				alu(	reg_out1,
							alu_input2,  
							alu_sel,

							alu_brch_en,
							alu_result
							);
sign_extend	sign_ext(
							instr_line[6:0], 
							ext_line
							); 
prog_count 	proc(		pc_loopback, 
							clk, 
							rst,
							curr_pc
							);
jrcontrol	jr_control(		instr_line[3:0], 
							aluop, 
							clk, 
							jrmux_en
							);
amod1		andgate(		branch, 
							alu_brch_en,
							brch_en
							);
brch_add 	brch_adder( pc_p2,
							ext_line[12:0],

							brch_res
							);
pc_add		pc_adder(
							curr_pc,
							13'b1,

							pc_p2
							);



regdestmux		muxregdst(		instr_line[9:7], 	
								instr_line[6:4], 			
								regdst,
								wr
								);
memtoregmux	muxdatamem(	alu_result,
								mem_out,
								pc_p2,
								memtoreg,
								wdr
								);
alusrcmux		muxalusource(	reg_out2, 
								ext_line,
								alusrc,
								alu_input2
								);
brchmux			muxbranch(		pc_p2, 
								brch_res,
								brch_en, 
								brch_out
								);
jmpmux			muxjump(		brch_out,  
								instr_line[12:0], 
								jump,
								jmp_out
								);
jrmux				muxjumpreg(	jmp_out, 
								reg_out1,
								jrmux_en,
								pc_loopback
								);




regmem 			regmem(	wdr[15:0],
								instr_line[12:10],
								instr_line[9:7],
								wr,
								clk, 
								rst, 
								reg_we, 
								reg_out1,
								reg_out2
								);
datamem 			datamem(	reg_out2,
								alu_result,
								clk, 

								mem_we, 
								mem_re, 
								mem_out
								);
instrmem			instrmem(	curr_pc, 
								clk,
								rst,
								instr_line
								); 

endmodule