data/full_repos/permissive/424312442/Lab_4_behavioral modeling/sources_1/new/Lab_4_part_2.v
1: b'%Error: Cannot find file containing module: modeling/sources_1/new,data/full_repos/permissive/424312442\n        ... Looked in:\n             data/full_repos/permissive/424312442/Lab_4_behavioral/modeling/sources_1/new,data/full_repos/permissive/424312442\n             data/full_repos/permissive/424312442/Lab_4_behavioral/modeling/sources_1/new,data/full_repos/permissive/424312442.v\n             data/full_repos/permissive/424312442/Lab_4_behavioral/modeling/sources_1/new,data/full_repos/permissive/424312442.sv\n             modeling/sources_1/new,data/full_repos/permissive/424312442\n             modeling/sources_1/new,data/full_repos/permissive/424312442.v\n             modeling/sources_1/new,data/full_repos/permissive/424312442.sv\n             obj_dir/modeling/sources_1/new,data/full_repos/permissive/424312442\n             obj_dir/modeling/sources_1/new,data/full_repos/permissive/424312442.v\n             obj_dir/modeling/sources_1/new,data/full_repos/permissive/424312442.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/424312442/Lab_4_behavioral\n%Error: Cannot find file containing module: modeling/sources_1/new/Lab_4_part_2.v\n%Error: Exiting due to 3 error(s)\n'
module DFFas_tb;
wire Q;
reg D, CLR, CLK;

DFFas dut(D, CLR, CLK, Q);

always
begin
#5 CLK <= ~CLK;
end

initial begin
CLK = 0;
D = 1'b0; CLR = 1'b1;
#10;
D = 1'b1; CLR = 1'b1;
#10;
D = 1'b1; CLR = 1'b0;
#10;
D = 1'b0; CLR = 1'b0;
#10;
D = 1'b1; CLR = 1'b0;
#10;
D = 1'b1; CLR = 1'b1;
#10;
D = 1'b0; CLR = 1'b1;
#10;
D = 1'b1; CLR = 1'b1;
#10;
D = 1'b0; CLR = 1'b1;
#10;

end
endmodule
module DFFas_tb;

wire Q;
reg D, CLR, CLK;

DFFas dut(D, CLR, CLK, Q);

always
begin
#5 CLK <= ~CLK;
end

initial begin
CLK = 0;
D = 1'b0; CLR = 1'b1;
#10;
D = 1'b1; CLR = 1'b1;
#10;
D = 1'b1; CLR = 1'b0;
#10;
D = 1'b0; CLR = 1'b0;
#10;
D = 1'b1; CLR = 1'b0;
#10;
D = 1'b1; CLR = 1'b1;
#10;
D = 1'b0; CLR = 1'b1;
#10;
D = 1'b1; CLR = 1'b1;
#10;
D = 1'b0; CLR = 1'b1;
#10;

end
endmodule