data/full_repos/permissive/519893543/verilog/rtl/biquad/coefio.v
1: b"%Error: data/full_repos/permissive/519893543/verilog/rtl/biquad/coefio.v:73: Too many digits for 4 bit number: 4'h30000000\nassign sel_a11 = (adr_i == 4'h30000000);  \n                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/519893543/verilog/rtl/biquad/coefio.v:74: Too many digits for 4 bit number: 4'h30000004\nassign sel_a12 = (adr_i == 4'h30000004);\n                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/519893543/verilog/rtl/biquad/coefio.v:75: Too many digits for 4 bit number: 4'h30000008\nassign sel_b10 = (adr_i == 4'h30000008);\n                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/519893543/verilog/rtl/biquad/coefio.v:76: Too many digits for 4 bit number: 4'h3000000c\nassign sel_b11 = (adr_i == 4'h3000000c);\n                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/519893543/verilog/rtl/biquad/coefio.v:77: Too many digits for 4 bit number: 4'h30000010\nassign sel_b12 = (adr_i == 4'h30000010);\n                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/519893543/verilog/rtl/biquad/coefio.v:78: Too many digits for 4 bit number: 4'h30000014\nassign sel_x   = (adr_i == 4'h30000014);\n                           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/519893543/verilog/rtl/biquad/coefio.v:79: Too many digits for 4 bit number: 4'h30000018\nassign sel_y   = (adr_i == 4'h30000018);\n                           ^~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n"
module coefio # (
     parameter DATAWIDTH = 12
)
	(
    `ifdef USE_POWER_PINS
		inout vccd1,
		inout vssd1,
    `endif 
	input clk_i,
	input rst_i,
	input we_i,	
	input stb_i,
	input cyc_i,
	output wire ack_o,
	input	[31:0]	dat_i,
	output	[31:0]	dat_o,
	input	[31:0]	adr_i,
	output  reg [31:0]	a11,
	output	reg [31:0]	a12,
	output	reg [31:0]	b10,
	output	reg [31:0]	b11,
	output	reg [31:0]	b12,
	input   [DATAWIDTH-1:0] x, 
	input   [DATAWIDTH-1:0] y
	);

wire		sel_a11;
wire		sel_a12;
wire		sel_b10;
wire		sel_b11;
wire		sel_b12;
wire        sel_y;
wire        sel_x;



assign sel_a11 = (adr_i == 4'h30000000);  
assign sel_a12 = (adr_i == 4'h30000004);
assign sel_b10 = (adr_i == 4'h30000008);
assign sel_b11 = (adr_i == 4'h3000000c);
assign sel_b12 = (adr_i == 4'h30000010);
assign sel_x   = (adr_i == 4'h30000014);
assign sel_y   = (adr_i == 4'h30000018);

assign ack_o = stb_i;

always @(posedge clk_i or posedge rst_i)
if ( rst_i )
  begin
    a11 <= 32'd0;
    a12 <= 32'd0;
    b10 <= 32'd0;
    b11 <= 32'd0;
    b12 <= 32'd0;
  end
else
  begin
    a11 <= (stb_i & we_i & cyc_i & sel_a11) ? (dat_i) : (a11);
    a12 <= (stb_i & we_i & cyc_i & sel_a12) ? (dat_i) : (a12);
    b10 <= (stb_i & we_i & cyc_i & sel_b10) ? (dat_i) : (b10);
    b11 <= (stb_i & we_i & cyc_i & sel_b11) ? (dat_i) : (b11);
    b12 <= (stb_i & we_i & cyc_i & sel_b12) ? (dat_i) : (b12);
  end

assign dat_o = sel_a11 ? (a11) : 
		((sel_a12) ? (a12) : 
		((sel_b10) ? (b10) : 
		((sel_b11) ? (b11) : 
		((sel_b12) ? (b12) : 
		((sel_x)   ? ({20'b0,x[11:0]}) :
		((sel_y)   ? ({20'b0,y[11:0]}) :
		(32'h0000)))))));


endmodule
module coefio # (
     parameter DATAWIDTH = 12
)
	(
    `ifdef USE_POWER_PINS
		inout vccd1,
		inout vssd1,
    `endif 
	input clk_i,
	input rst_i,
	input we_i,	
	input stb_i,
	input cyc_i,
	output wire ack_o,
	input	[31:0]	dat_i,
	output	[31:0]	dat_o,
	input	[31:0]	adr_i,
	output  reg [31:0]	a11,
	output	reg [31:0]	a12,
	output	reg [31:0]	b10,
	output	reg [31:0]	b11,
	output	reg [31:0]	b12,
	input   [DATAWIDTH-1:0] x, 
	input   [DATAWIDTH-1:0] y
	);


wire		sel_a11;
wire		sel_a12;
wire		sel_b10;
wire		sel_b11;
wire		sel_b12;
wire        sel_y;
wire        sel_x;



assign sel_a11 = (adr_i == 4'h30000000);  
assign sel_a12 = (adr_i == 4'h30000004);
assign sel_b10 = (adr_i == 4'h30000008);
assign sel_b11 = (adr_i == 4'h3000000c);
assign sel_b12 = (adr_i == 4'h30000010);
assign sel_x   = (adr_i == 4'h30000014);
assign sel_y   = (adr_i == 4'h30000018);

assign ack_o = stb_i;

always @(posedge clk_i or posedge rst_i)
if ( rst_i )
  begin
    a11 <= 32'd0;
    a12 <= 32'd0;
    b10 <= 32'd0;
    b11 <= 32'd0;
    b12 <= 32'd0;
  end
else
  begin
    a11 <= (stb_i & we_i & cyc_i & sel_a11) ? (dat_i) : (a11);
    a12 <= (stb_i & we_i & cyc_i & sel_a12) ? (dat_i) : (a12);
    b10 <= (stb_i & we_i & cyc_i & sel_b10) ? (dat_i) : (b10);
    b11 <= (stb_i & we_i & cyc_i & sel_b11) ? (dat_i) : (b11);
    b12 <= (stb_i & we_i & cyc_i & sel_b12) ? (dat_i) : (b12);
  end

assign dat_o = sel_a11 ? (a11) : 
		((sel_a12) ? (a12) : 
		((sel_b10) ? (b10) : 
		((sel_b11) ? (b11) : 
		((sel_b12) ? (b12) : 
		((sel_x)   ? ({20'b0,x[11:0]}) :
		((sel_y)   ? ({20'b0,y[11:0]}) :
		(32'h0000)))))));


endmodule