data/full_repos/permissive/52633518/alu16.v
1: b'%Warning-WIDTH: data/full_repos/permissive/52633518/alu16.v:37: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s LT generates 1 bits.\n                                                              : ... In instance alu16\n        out <= op1 < op2;\n            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/52633518/alu16.v:39: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s LTE generates 1 bits.\n                                                              : ... In instance alu16\n        out <= op1 <= op2;\n            ^~\n%Warning-WIDTH: data/full_repos/permissive/52633518/alu16.v:23: Operator CASE expects 4 bits on the Case expression, but Case expression\'s VARREF \'operator\' generates 3 bits.\n                                                              : ... In instance alu16\n      case(operator)\n      ^~~~\n%Error: Exiting due to 3 warning(s)\n'
module alu16(

  input clk,rst,
  input [2:0] operator,
  input [15:0] op1,op2,
  
  output reg [15:0] out, status
  );
  `define numBits 16
  `define operatorSize 4







	
  always@(*) begin
    if(rst == 1'b0) begin
      out <= `numBits'd0;
    end else begin
      case(operator)
      `operatorSize'h0:
        out <= op1 + op2;
      `operatorSize'h1:
        out <= op2 - op1;
      `operatorSize'h2:
        out <= (op1 * op2);
      `operatorSize'h3:
        out <= ~(op1 & op2);
      `operatorSize'h4:
        out <= op1 / op2;
      `operatorSize'h5:
        out <= op1 % op2;
      `operatorSize'h6:
        out <= op1 < op2;
      `operatorSize'h7:
        out <= op1 <= op2;
      default:
        out <= `numBits'd0;
     endcase
    end
  end

  always@(posedge clk or negedge rst) begin
    if(rst == 1'b0) begin
      status = `numBits'd0;
    end else begin 
      status <= out;
    end
  end
endmodule
module alu16(

  input clk,rst,
  input [2:0] operator,
  input [15:0] op1,op2,
  
  output reg [15:0] out, status
  );

  `define numBits 16
  `define operatorSize 4







	
  always@(*) begin
    if(rst == 1'b0) begin
      out <= `numBits'd0;
    end else begin
      case(operator)
      `operatorSize'h0:
        out <= op1 + op2;
      `operatorSize'h1:
        out <= op2 - op1;
      `operatorSize'h2:
        out <= (op1 * op2);
      `operatorSize'h3:
        out <= ~(op1 & op2);
      `operatorSize'h4:
        out <= op1 / op2;
      `operatorSize'h5:
        out <= op1 % op2;
      `operatorSize'h6:
        out <= op1 < op2;
      `operatorSize'h7:
        out <= op1 <= op2;
      default:
        out <= `numBits'd0;
     endcase
    end
  end

  always@(posedge clk or negedge rst) begin
    if(rst == 1'b0) begin
      status = `numBits'd0;
    end else begin 
      status <= out;
    end
  end
endmodule