data/full_repos/permissive/497337299/basics/tb/tb_comp.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_comp.v:8: Unsupported: Ignoring delay on this delayed statement.\n    #0       A=15; B=6; \n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_comp.v:9: Unsupported: Ignoring delay on this delayed statement.\n    #20      A=6; B=6; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_comp.v:10: Unsupported: Ignoring delay on this delayed statement.\n    #20      A=3; B=6; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_comp.v:11: Unsupported: Ignoring delay on this delayed statement.\n    #20      A=8; B=6; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_comp.v:12: Unsupported: Ignoring delay on this delayed statement.\n    #20      A=10; B=6; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497337299/basics/tb/tb_comp.v:13: Unsupported: Ignoring delay on this delayed statement.\n    #20      A=15; B=6;      \n    ^\n%Error: data/full_repos/permissive/497337299/basics/tb/tb_comp.v:5: Cannot find file containing module: \'comp\'\n    comp ut (.A(A),.B(B),.Lt(Lt),.Eq(Eq),.Gt(Gt));\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/497337299/basics/tb,data/full_repos/permissive/497337299/comp\n             data/full_repos/permissive/497337299/basics/tb,data/full_repos/permissive/497337299/comp.v\n             data/full_repos/permissive/497337299/basics/tb,data/full_repos/permissive/497337299/comp.sv\n             comp\n             comp.v\n             comp.sv\n             obj_dir/comp\n             obj_dir/comp.v\n             obj_dir/comp.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_comp();
    reg [3:0] A,B ;
    wire Lt,Eq,Gt;
    comp ut (.A(A),.B(B),.Lt(Lt),.Eq(Eq),.Gt(Gt));
    
initial begin
    #0       A=15; B=6; 
    #20      A=6; B=6; 
    #20      A=3; B=6; 
    #20      A=8; B=6; 
    #20      A=10; B=6; 
    #20      A=15; B=6;      
end


endmodule
module tb_comp();

    reg [3:0] A,B ;
    wire Lt,Eq,Gt;
    comp ut (.A(A),.B(B),.Lt(Lt),.Eq(Eq),.Gt(Gt));
    
initial begin
    #0       A=15; B=6; 
    #20      A=6; B=6; 
    #20      A=3; B=6; 
    #20      A=8; B=6; 
    #20      A=10; B=6; 
    #20      A=15; B=6;      
end


endmodule