data/full_repos/permissive/492213907/codes/Clock_Div.v
data/verilator_xmls/c973dc9c-eeba-4bdb-ae1b-f0e63c942f73.xml
module Clock_Div (clk_in, clk_sw_1, clk_sw_2, clk_out);
 
  input clk_in;
  input clk_sw_1;
  input clk_sw_2;
  output clk_out;
    




  parameter fre_4HZ = 6250000;
  parameter fre_2HZ = 12500000;
  parameter fre_1HZ = 25000000;
 

  reg [31:0] counter_4HZ = 0;
  reg [31:0] counter_2HZ = 0;
  reg [31:0] counter_1HZ = 0;
   

  reg clk_toggle_4HZ = 1'b0;
  reg clk_toggle_2HZ = 1'b0;
  reg clk_toggle_1HZ = 1'b0;
   

  reg clk_select;
 



 
  always @ (posedge clk_in)
    begin
      if (counter_4HZ == fre_4HZ-1)
        begin        
          clk_toggle_4HZ <= !clk_toggle_4HZ;
          counter_4HZ <= 0;
        end
      else
        counter_4HZ <= counter_4HZ + 1;
    end
 
   
  always @ (posedge clk_in)
    begin
      if (counter_2HZ == fre_2HZ-1)
        begin        
          clk_toggle_2HZ <= !clk_toggle_2HZ;
          counter_2HZ <= 0;
        end
      else
        counter_2HZ <= counter_2HZ + 1;
    end
 
 
  always @ (posedge clk_in)
    begin
      if (counter_1HZ == fre_1HZ-1)
        begin        
          clk_toggle_1HZ <= !clk_toggle_1HZ;
          counter_1HZ <= 0;
        end
      else
        counter_1HZ <= counter_1HZ + 1;
    end
 

  always @ (*)
  begin
    case ({clk_sw_1, clk_sw_2})
      2'b11 : clk_select <= clk_toggle_4HZ;
      2'b10 : clk_select <= clk_toggle_2HZ;
      2'b01 : clk_select <= clk_toggle_1HZ;
      2'b00 : clk_select <= clk_in;
    endcase     
  end
 
  assign clk_out = clk_select;
   
endmodule
module Clock_Div (clk_in, clk_sw_1, clk_sw_2, clk_out);

 
  input clk_in;
  input clk_sw_1;
  input clk_sw_2;
  output clk_out;
    




  parameter fre_4HZ = 6250000;
  parameter fre_2HZ = 12500000;
  parameter fre_1HZ = 25000000;
 

  reg [31:0] counter_4HZ = 0;
  reg [31:0] counter_2HZ = 0;
  reg [31:0] counter_1HZ = 0;
   

  reg clk_toggle_4HZ = 1'b0;
  reg clk_toggle_2HZ = 1'b0;
  reg clk_toggle_1HZ = 1'b0;
   

  reg clk_select;
 



 
  always @ (posedge clk_in)
    begin
      if (counter_4HZ == fre_4HZ-1)
        begin        
          clk_toggle_4HZ <= !clk_toggle_4HZ;
          counter_4HZ <= 0;
        end
      else
        counter_4HZ <= counter_4HZ + 1;
    end
 
   
  always @ (posedge clk_in)
    begin
      if (counter_2HZ == fre_2HZ-1)
        begin        
          clk_toggle_2HZ <= !clk_toggle_2HZ;
          counter_2HZ <= 0;
        end
      else
        counter_2HZ <= counter_2HZ + 1;
    end
 
 
  always @ (posedge clk_in)
    begin
      if (counter_1HZ == fre_1HZ-1)
        begin        
          clk_toggle_1HZ <= !clk_toggle_1HZ;
          counter_1HZ <= 0;
        end
      else
        counter_1HZ <= counter_1HZ + 1;
    end
 

  always @ (*)
  begin
    case ({clk_sw_1, clk_sw_2})
      2'b11 : clk_select <= clk_toggle_4HZ;
      2'b10 : clk_select <= clk_toggle_2HZ;
      2'b01 : clk_select <= clk_toggle_1HZ;
      2'b00 : clk_select <= clk_in;
    endcase     
  end
 
  assign clk_out = clk_select;
   
endmodule