data/full_repos/permissive/418749135/tff_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/418749135/tff_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n  always #5 clk = ~clk;  \n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/418749135/tff_tb.v:16: Unsupported or unknown PLI call: $monitor\n    $monitor ("T=%0t rstn=%0b t=%0d q=%0d", $time, rstn, t, q);  \n    ^~~~~~~~\n%Error: data/full_repos/permissive/418749135/tff_tb.v:17: syntax error, unexpected \'@\'\n    repeat(2) @(posedge clk);  \n              ^\n%Warning-STMTDLY: data/full_repos/permissive/418749135/tff_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n      #(dly) t <= $random;  \n      ^\n%Warning-STMTDLY: data/full_repos/permissive/418749135/tff_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n    #20 $finish;  \n    ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;  
  reg clk;  
  reg rstn;  
  reg t;  
  
  tff u0 (  .clk(clk),  
            .rstn(rstn),  
            .t(t),  
          .q(q));  
  
  always #5 clk = ~clk;  
  
  initial begin  
    {rstn, clk, t} <= 0;  
  
    $monitor ("T=%0t rstn=%0b t=%0d q=%0d", $time, rstn, t, q);  
    repeat(2) @(posedge clk);  
    rstn <= 1;  
  
    for (integer i = 0; i < 20; i = i+1) begin  
      reg [4:0] dly = $random;  
      #(dly) t <= $random;  
    end  
    #20 $finish;  
  end  
endmodule
module tb;
  
  reg clk;  
  reg rstn;  
  reg t;  
  
  tff u0 (  .clk(clk),  
            .rstn(rstn),  
            .t(t),  
          .q(q));  
  
  always #5 clk = ~clk;  
  
  initial begin  
    {rstn, clk, t} <= 0;  
  
    $monitor ("T=%0t rstn=%0b t=%0d q=%0d", $time, rstn, t, q);  
    repeat(2) @(posedge clk);  
    rstn <= 1;  
  
    for (integer i = 0; i < 20; i = i+1) begin  
      reg [4:0] dly = $random;  
      #(dly) t <= $random;  
    end  
    #20 $finish;  
  end  
endmodule