data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:118: Multiple top level modules\n                                                                                         : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                         : ... Top module \'rs_7_5_encoder\'\nmodule rs_7_5_encoder\n       ^~~~~~~~~~~~~~\n                                                                                         : ... Top module \'rs_7_5_decoder\'\nmodule rs_7_5_decoder\n       ^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:170: Operator ADD expects 32 bits on the RHS, but RHS\'s ARRAYSEL generates 3 bits.\n                                                                                      : ... In instance rs_7_5_decoder\n    S1_poly[idx] = (7 - idx) + GF_log[s[idx]];               \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:170: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                      : ... In instance rs_7_5_decoder\n    S1_poly[idx] = (7 - idx) + GF_log[s[idx]];               \n                 ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:171: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                      : ... In instance rs_7_5_decoder\n    S1_poly[idx] = S1_poly[idx][2:0] + S1_poly[idx][3];      \n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:172: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s ARRAYSEL generates 3 bits.\n                                                                                      : ... In instance rs_7_5_decoder\n    S1_poly[idx] = s[idx] ? GF_alog[S1_poly[idx]] : 3\'b000;  \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:172: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s ARRAYSEL generates 3 bits.\n                                                                                      : ... In instance rs_7_5_decoder\n    S1_poly[idx] = s[idx] ? GF_alog[S1_poly[idx]] : 3\'b000;  \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:172: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                      : ... In instance rs_7_5_decoder\n    S1_poly[idx] = s[idx] ? GF_alog[S1_poly[idx]] : 3\'b000;  \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:175: Operator XOR expects 4 bits on the LHS, but LHS\'s VARREF \'S1\' generates 3 bits.\n                                                                                      : ... In instance rs_7_5_decoder\n    S1           = S1 ^ S1_poly[idx];\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:175: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s XOR generates 4 bits.\n                                                                                      : ... In instance rs_7_5_decoder\n    S1           = S1 ^ S1_poly[idx];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:183: Operator SUB expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                      : ... In instance rs_7_5_decoder\n    k      = k[2:0] - k[3];                                  \n                    ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:184: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s ARRAYSEL generates 3 bits.\n                                                                                      : ... In instance rs_7_5_decoder\n    k      = (k == 4\'b0000) ? GF_log[3\'b001] : k;            \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:100: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                      : ... In instance rs_7_5_encoder\n    p_data[idx] = p_data[idx][2:0] + p_data[idx][3];  \n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:101: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 3 bits.\n                                                                                      : ... In instance rs_7_5_encoder\n    p_data[idx] = GF_alog[p_data[idx]];               \n                ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:102: Operator XOR expects 4 bits on the LHS, but LHS\'s VARREF \'P\' generates 3 bits.\n                                                                                      : ... In instance rs_7_5_encoder\n    P           = P ^ p_data[idx];                    \n                    ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:102: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s XOR generates 4 bits.\n                                                                                      : ... In instance rs_7_5_encoder\n    P           = P ^ p_data[idx];                    \n                ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:106: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                      : ... In instance rs_7_5_encoder\n    q_data[idx] = q_data[idx][2:0] + q_data[idx][3];  \n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:107: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 3 bits.\n                                                                                      : ... In instance rs_7_5_encoder\n    q_data[idx] = GF_alog[q_data[idx]];               \n                ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:108: Operator XOR expects 4 bits on the LHS, but LHS\'s VARREF \'Q\' generates 3 bits.\n                                                                                      : ... In instance rs_7_5_encoder\n    Q           = Q ^ q_data[idx];                    \n                    ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:108: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s XOR generates 4 bits.\n                                                                                      : ... In instance rs_7_5_encoder\n    Q           = Q ^ q_data[idx];                    \n                ^\n%Error: Exiting due to 19 warning(s)\n'
module rs_7_5_encoder
(
  input [14:0] idata,
  output[20:0] ocode
);

wire [2:0] s [0:6];

integer idx;
reg [2:0] GF_log  [1:7];
reg [2:0] GF_alog [1:7];
reg [2:0] p_poly  [0:4];
reg [2:0] q_poly  [0:4];
reg [3:0] p_data  [0:4];
reg [3:0] q_data  [0:4];
reg [2:0] P, Q;

assign s[0] = idata[2:0];
assign s[1] = idata[5:3];
assign s[2] = idata[8:6];
assign s[3] = idata[11:9];
assign s[4] = idata[14:12];
assign s[5] = P;
assign s[6] = Q;

assign ocode = {s[6], s[5], s[4], s[3], s[2], s[1], s[0]};

initial
begin


  GF_alog[1] = 3'b010; GF_alog[2] = 3'b100;
  GF_alog[3] = 3'b011; GF_alog[4] = 3'b110;
  GF_alog[5] = 3'b111; GF_alog[6] = 3'b101;
  GF_alog[7] = 3'b001;


  GF_log[1] = 3'b111; GF_log[2] = 3'b001;
  GF_log[3] = 3'b011; GF_log[4] = 3'b010;
  GF_log[5] = 3'b110; GF_log[6] = 3'b100;
  GF_log[7] = 3'b101;


  p_poly[0] = 6; p_poly[1] = 1; p_poly[2] = 2;
  p_poly[3] = 5; p_poly[4] = 3;


  q_poly[0] = 2; q_poly[1] = 3; q_poly[2] = 6;
  q_poly[3] = 4; q_poly[4] = 1;
end

always @(*)
begin
  P = 3'b000;
  Q = 3'b000;

  for (idx = 0; idx < 5; idx = idx + 1)
  begin

    p_data[idx] = p_poly[idx] + GF_log[s[idx]];
    p_data[idx] = p_data[idx][2:0] + p_data[idx][3];
    p_data[idx] = GF_alog[p_data[idx]];
    P           = P ^ p_data[idx];


    q_data[idx] = q_poly[idx] + GF_log[s[idx]];
    q_data[idx] = q_data[idx][2:0] + q_data[idx][3];
    q_data[idx] = GF_alog[q_data[idx]];
    Q           = Q ^ q_data[idx];
  end
end

endmodule
module rs_7_5_encoder
(
  input [14:0] idata,
  output[20:0] ocode
);


wire [2:0] s [0:6];

integer idx;
reg [2:0] GF_log  [1:7];
reg [2:0] GF_alog [1:7];
reg [2:0] p_poly  [0:4];
reg [2:0] q_poly  [0:4];
reg [3:0] p_data  [0:4];
reg [3:0] q_data  [0:4];
reg [2:0] P, Q;

assign s[0] = idata[2:0];
assign s[1] = idata[5:3];
assign s[2] = idata[8:6];
assign s[3] = idata[11:9];
assign s[4] = idata[14:12];
assign s[5] = P;
assign s[6] = Q;

assign ocode = {s[6], s[5], s[4], s[3], s[2], s[1], s[0]};

initial
begin


  GF_alog[1] = 3'b010; GF_alog[2] = 3'b100;
  GF_alog[3] = 3'b011; GF_alog[4] = 3'b110;
  GF_alog[5] = 3'b111; GF_alog[6] = 3'b101;
  GF_alog[7] = 3'b001;


  GF_log[1] = 3'b111; GF_log[2] = 3'b001;
  GF_log[3] = 3'b011; GF_log[4] = 3'b010;
  GF_log[5] = 3'b110; GF_log[6] = 3'b100;
  GF_log[7] = 3'b101;


  p_poly[0] = 6; p_poly[1] = 1; p_poly[2] = 2;
  p_poly[3] = 5; p_poly[4] = 3;


  q_poly[0] = 2; q_poly[1] = 3; q_poly[2] = 6;
  q_poly[3] = 4; q_poly[4] = 1;
end

always @(*)
begin
  P = 3'b000;
  Q = 3'b000;

  for (idx = 0; idx < 5; idx = idx + 1)
  begin

    p_data[idx] = p_poly[idx] + GF_log[s[idx]];
    p_data[idx] = p_data[idx][2:0] + p_data[idx][3];
    p_data[idx] = GF_alog[p_data[idx]];
    P           = P ^ p_data[idx];


    q_data[idx] = q_poly[idx] + GF_log[s[idx]];
    q_data[idx] = q_data[idx][2:0] + q_data[idx][3];
    q_data[idx] = GF_alog[q_data[idx]];
    Q           = Q ^ q_data[idx];
  end
end

endmodule