data/full_repos/permissive/441359809/src/yosys/examples/cmos/counter.v
data/verilator_xmls/61c593fc-6fa3-4253-9e68-7c135b947651.xml
module counter (clk, rst, en, count);

   input clk, rst, en;
   output reg [2:0] count;

   always @(posedge clk)
      if (rst)
         count <= 3'd0;
      else if (en)
         count <= count + 3'd1;

endmodule
module counter (clk, rst, en, count);


   input clk, rst, en;
   output reg [2:0] count;

   always @(posedge clk)
      if (rst)
         count <= 3'd0;
      else if (en)
         count <= count + 3'd1;

endmodule