data/full_repos/permissive/520428138/verilog/rtl/user_module_341353780122485332.v
1: b"%Error: data/full_repos/permissive/520428138/verilog/rtl/user_module_341353780122485332.v:52: Can't resolve module reference: 'sky130_fd_sc_hd__dlxtp_1'\n    sky130_fd_sc_hd__dlxtp_1 mode_lat_i (\n                             ^~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module write_pulse_gen_341353780122485332 (input wire clk, input wire en, output wire q);
`ifdef SYNTHESIS
    wire clk_del1, clk_del2, clk_strb;
    (* keep, dont_touch *) buffer_chain_341353780122485332 dly0_i (.A(clk), .X(clk_del1));
    (* keep, dont_touch *) buffer_chain_341353780122485332 dly1_i (.A(clk_del1), .X(clk_del2));
    sky130_fd_sc_hd__and2b_1 cmp_i (.A_N(clk_del2), .B(clk), .X(clk_strb), .VPWR(1'b1), .VGND(1'b0));
    sky130_fd_sc_hd__and2_2 gate_i (.A(clk_strb), .B(en), .X(q), .VPWR(1'b1), .VGND(1'b0));
`else
    reg clk_del, strb_out;
    always @* clk_del = #3 clk;
    always @* strb_out = #1 (en & (clk & ~clk_del));
    assign q = strb_out;
`endif
endmodule
module write_pulse_gen_341353780122485332 (input wire clk, input wire en, output wire q);

`ifdef SYNTHESIS
    wire clk_del1, clk_del2, clk_strb;
    (* keep, dont_touch *) buffer_chain_341353780122485332 dly0_i (.A(clk), .X(clk_del1));
    (* keep, dont_touch *) buffer_chain_341353780122485332 dly1_i (.A(clk_del1), .X(clk_del2));
    sky130_fd_sc_hd__and2b_1 cmp_i (.A_N(clk_del2), .B(clk), .X(clk_strb), .VPWR(1'b1), .VGND(1'b0));
    sky130_fd_sc_hd__and2_2 gate_i (.A(clk_strb), .B(en), .X(q), .VPWR(1'b1), .VGND(1'b0));
`else
    reg clk_del, strb_out;
    always @* clk_del = #3 clk;
    always @* strb_out = #1 (en & (clk & ~clk_del));
    assign q = strb_out;
`endif
endmodule