data/full_repos/permissive/515890445/ARM_MultiCycle/MultiCycle/MultiCycleMainFSM.v
1: b'%Warning-WIDTH: data/full_repos/permissive/515890445/ARM_MultiCycle/MultiCycle/MultiCycleMainFSM.v:365: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                                                      : ... In instance MultiCycleMainFSM\n   ALUControl = 2\'b00;\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module MultiCycleMainFSM (
	input 	wire [1:0] 	Op,
	input 	wire [5:0] 	Func,
	input 	wire [3:0] 	Rd,
	input 	wire 			CLK,
	input 	wire 			RESET_N,
	
	output 	reg 			NoWrite,
	output 	reg  [1:0]	FlagW,
	output 	wire 			PCS,
	output 	reg 			NextPC,
	output 	reg  			RegW,
	output 	reg  			MemW,
	
	output 	reg  			IRWrite,
	output 	reg  			AdrSrc,
	output 	reg  [1:0]	ResultSrc,
	output 	reg  			ALUSrcA,
	output 	reg  [1:0]	ALUSrcB,
	output 	wire [1:0]	ImmSrc,
	output 	wire [1:0]	RegSrc,
	output 	reg  [2:0]	ALUControl,
	output 	reg 			BL_Active,
	output 	wire 			Shifter_En,
	output 	wire [3:0]	State
);

	localparam S0_Fetch 		= 4'd0;
	localparam S1_Decode 	= 4'd1;
	localparam S2_MemAdr 	= 4'd2;
	localparam S3_MemRead 	= 4'd3;
	localparam S4_MemWB 		= 4'd4;
	localparam S5_MemWrite 	= 4'd5;
	localparam S6_ExecuteR 	= 4'd6;
	localparam S7_ExecuteI 	= 4'd7;
	localparam S8_ALUWB 		= 4'd8;
	localparam S9_Branch 	= 4'd9;
	localparam S10_BranchLink 	= 4'd10;

	reg [3:0] state;
	assign State = state;

	initial state = S0_Fetch;
	reg ALUOp;
	reg Branch;


	always @ (posedge CLK or negedge RESET_N)
		if (!RESET_N)
			state <= S0_Fetch;
		else
		case(state)
			S0_Fetch:
				state <= S1_Decode;
			S1_Decode:
				case(Op)
					2'b00:
						if(Func[5])
							state <= S7_ExecuteI;
						else
							state <= S6_ExecuteR;
						
					2'b01:
						state <= S2_MemAdr;
					2'b10:
						if(Func[4])
							state <= S10_BranchLink;
						else
							state <= S9_Branch;
					2'b11:
						state <= S0_Fetch;
				endcase
			S2_MemAdr:
				if(Func[0])
					state <= S3_MemRead;
				else
					state <= S5_MemWrite;
			
			S3_MemRead:
				state <= S4_MemWB;
			
			S4_MemWB:
				state <= S0_Fetch;
			
			S5_MemWrite:
				state <= S0_Fetch;
			
			S6_ExecuteR:
				state <= S8_ALUWB;
			
			S7_ExecuteI:
				state <= S8_ALUWB;
			
			S8_ALUWB:
				state <= S0_Fetch;
			
			S9_Branch:
				state <= S0_Fetch;
				
			S10_BranchLink:
				state <= S0_Fetch;
				
			default:
				state <= S0_Fetch;
			
		endcase


	always @(state)
		case(state)
			S0_Fetch:
				begin
				AdrSrc 		= 1'b0;
				ALUSrcA		= 1'b1;
				ALUSrcB		= 2'b10;
				ALUOp			= 1'b0;
				ResultSrc	= 2'b10;
				IRWrite		= 1'b1;
				NextPC		= 1'b1;
				Branch 		= 1'b0;
				RegW			= 1'b0;
				MemW			= 1'b0;
				BL_Active	= 1'b0;
				end
				
			S1_Decode:
				begin
				AdrSrc 		= 1'b0;
				ALUSrcA		= 1'b1;
				ALUSrcB		= 2'b10;
				ALUOp			= 1'b0;
				ResultSrc	= 2'b10;
				IRWrite		= 1'b0;
				NextPC		= 1'b0;
				Branch 		= 1'b0;
				RegW			= 1'b0;
				MemW			= 1'b0;
				BL_Active	= 1'b0;
				end
				
			S2_MemAdr:
				begin
				AdrSrc 		= 1'b0;
				ALUSrcA		= 1'b0;
				ALUSrcB		= 2'b01;
				ALUOp			= 1'b0;
				ResultSrc	= 2'b10;
				IRWrite		= 1'b0;
				NextPC		= 1'b0;
				Branch 		= 1'b0;
				RegW			= 1'b0;
				MemW			= 1'b0;
				BL_Active	= 1'b0;
				end
			
			S3_MemRead:
				begin
				AdrSrc 		= 1'b1;
				ALUSrcA		= 1'b0;
				ALUSrcB		= 2'b01;
				ALUOp			= 1'b0;
				ResultSrc	= 2'b00;
				IRWrite		= 1'b0;
				NextPC		= 1'b0;
				Branch 		= 1'b0;
				RegW			= 1'b0;
				MemW			= 1'b0;
				BL_Active	= 1'b0;
				end
			
			S4_MemWB:
				begin
				AdrSrc 		= 1'b1;
				ALUSrcA		= 1'b0;
				ALUSrcB		= 2'b01;
				ALUOp			= 1'b0;
				ResultSrc	= 2'b01;
				IRWrite		= 1'b0;
				NextPC		= 1'b0;
				Branch 		= 1'b0;
				RegW			= 1'b1;
				MemW			= 1'b0;
				BL_Active	= 1'b0;
				end
			
			S5_MemWrite:
				begin
				AdrSrc 		= 1'b1;
				ALUSrcA		= 1'b0;
				ALUSrcB		= 2'b01;
				ALUOp			= 1'b0;
				ResultSrc	= 2'b00;
				IRWrite		= 1'b0;
				NextPC		= 1'b0;
				Branch 		= 1'b0;
				RegW			= 1'b0;
				MemW			= 1'b1;
				BL_Active	= 1'b0;
				end
			
			S6_ExecuteR:
				begin
				AdrSrc 		= 1'b1;
				ALUSrcA		= 1'b0;
				ALUSrcB		= 2'b00;
				ALUOp			= 1'b1;
				ResultSrc	= 2'b00;
				IRWrite		= 1'b0;
				NextPC		= 1'b0;
				Branch 		= 1'b0;
				RegW			= 1'b0;
				MemW			= 1'b0;
				BL_Active	= 1'b0;
				end
			
			S7_ExecuteI:
				begin
				AdrSrc 		= 1'b1;
				ALUSrcA		= 1'b0;
				ALUSrcB		= 2'b01;
				ALUOp			= 1'b1;
				ResultSrc	= 2'b00;
				IRWrite		= 1'b0;
				NextPC		= 1'b0;
				Branch 		= 1'b0;
				RegW			= 1'b0;
				MemW			= 1'b0;
				BL_Active	= 1'b0;
				end
			
			S8_ALUWB:
				begin
				AdrSrc 		= 1'b1;
				ALUSrcA		= 1'b0;
				ALUSrcB		= 2'b01;
				ALUOp			= 1'b0;
				ResultSrc	= 2'b00;
				IRWrite		= 1'b0;
				NextPC		= 1'b0;
				Branch 		= 1'b0;
				RegW			= 1'b1;
				MemW			= 1'b0;
				BL_Active	= 1'b0;
				end
				
			S9_Branch:
				begin
				AdrSrc 		= 1'b1;
				ALUSrcA		= 1'b0;
				ALUSrcB		= 2'b01;
				ALUOp			= 1'b0;
				ResultSrc	= 2'b10;
				IRWrite		= 1'b0;
				NextPC		= 1'b0;
				Branch 		= 1'b1;
				RegW			= 1'b0;
				MemW			= 1'b0;
				BL_Active	= 1'b0;
				end
				
			S10_BranchLink:
				begin
				AdrSrc 		= 1'b1;
				ALUSrcA		= 1'b0;
				ALUSrcB		= 2'b01;
				ALUOp			= 1'b0;
				ResultSrc	= 2'b10;
				IRWrite		= 1'b0;
				NextPC		= 1'b0;
				Branch 		= 1'b1;
				RegW			= 1'b1;
				MemW			= 1'b0;
				BL_Active	= 1'b1;
				end
				
			default:
				begin
				AdrSrc 		= 1'b0;
				ALUSrcA		= 1'b0;
				ALUSrcB		= 2'b00;
				ALUOp			= 1'b0;
				ResultSrc	= 2'b00;
				IRWrite		= 1'b0;
				NextPC		= 1'b0;
				Branch 		= 1'b0;
				RegW			= 1'b0;
				MemW			= 1'b0;
				BL_Active	= 1'b0;
				end
			
		endcase
		
	

	assign RegSrc[1] = (Op[1:0] == 2'b01);
	assign RegSrc[0] = (Op[1:0] == 2'b10);
	assign Shifter_En = (Op[1:0] == 2'b00) & (state == S7_ExecuteI | state == S6_ExecuteR);
	assign ImmSrc = Op;
	

	assign PCS = ((Rd == 15) & RegW) | Branch;


	always @(Func[4:1], ALUOp)
	if(ALUOp)
		case(Func[4:1])
			4'b0100:
				begin
					ALUControl = 3'b000;
					FlagW		  = (Func[0]) ? 2'b11 : 2'b00;
					NoWrite 	  = 1'b0;
				end
			4'b0010:
				begin
					ALUControl = 3'b001;
					FlagW		  = (Func[0]) ? 2'b11 : 2'b00;
					NoWrite 	  = 1'b0;
				end
			4'b0000:
				begin
					ALUControl = 3'b100;
					FlagW		  = (Func[0]) ? 2'b10 : 2'b00;
					NoWrite 	  = 1'b0;
				end
			4'b1100:
				begin
					ALUControl = 3'b101;
					FlagW		  = (Func[0]) ? 2'b10 : 2'b00;
					NoWrite 	  = 1'b0;
				end
			4'b0001:
				begin
					ALUControl = 3'b110;
					FlagW		  = (Func[0]) ? 2'b10 : 2'b00;
					NoWrite 	  = 1'b0;
				end
			4'b1110:
				begin
					ALUControl = 3'b111;
					FlagW		  = (Func[0]) ? 2'b10 : 2'b00;
					NoWrite 	  = 1'b0;
				end
			4'b1010:
				begin
					ALUControl = 3'b001;
					FlagW		  = 2'b00;
					NoWrite 	  = 1'b1;
				end
			4'b1101:
				begin
					ALUControl = 3'b010;
					FlagW		  = (Func[0]) ? 2'b10 : 2'b00;
					NoWrite 	  = 1'b0;
				end
				
			default: 
				begin
					ALUControl = 3'b000;
					FlagW		  = 2'b00;
					NoWrite 	  = 1'b0;
				end
		endcase
	else
		begin
			ALUControl = 2'b00;
			FlagW		  = 2'b00;
			NoWrite 	  = 1'b0;
		end
	
endmodule
module MultiCycleMainFSM (
	input 	wire [1:0] 	Op,
	input 	wire [5:0] 	Func,
	input 	wire [3:0] 	Rd,
	input 	wire 			CLK,
	input 	wire 			RESET_N,
	
	output 	reg 			NoWrite,
	output 	reg  [1:0]	FlagW,
	output 	wire 			PCS,
	output 	reg 			NextPC,
	output 	reg  			RegW,
	output 	reg  			MemW,
	
	output 	reg  			IRWrite,
	output 	reg  			AdrSrc,
	output 	reg  [1:0]	ResultSrc,
	output 	reg  			ALUSrcA,
	output 	reg  [1:0]	ALUSrcB,
	output 	wire [1:0]	ImmSrc,
	output 	wire [1:0]	RegSrc,
	output 	reg  [2:0]	ALUControl,
	output 	reg 			BL_Active,
	output 	wire 			Shifter_En,
	output 	wire [3:0]	State
);


	localparam S0_Fetch 		= 4'd0;
	localparam S1_Decode 	= 4'd1;
	localparam S2_MemAdr 	= 4'd2;
	localparam S3_MemRead 	= 4'd3;
	localparam S4_MemWB 		= 4'd4;
	localparam S5_MemWrite 	= 4'd5;
	localparam S6_ExecuteR 	= 4'd6;
	localparam S7_ExecuteI 	= 4'd7;
	localparam S8_ALUWB 		= 4'd8;
	localparam S9_Branch 	= 4'd9;
	localparam S10_BranchLink 	= 4'd10;

	reg [3:0] state;
	assign State = state;

	initial state = S0_Fetch;
	reg ALUOp;
	reg Branch;


	always @ (posedge CLK or negedge RESET_N)
		if (!RESET_N)
			state <= S0_Fetch;
		else
		case(state)
			S0_Fetch:
				state <= S1_Decode;
			S1_Decode:
				case(Op)
					2'b00:
						if(Func[5])
							state <= S7_ExecuteI;
						else
							state <= S6_ExecuteR;
						
					2'b01:
						state <= S2_MemAdr;
					2'b10:
						if(Func[4])
							state <= S10_BranchLink;
						else
							state <= S9_Branch;
					2'b11:
						state <= S0_Fetch;
				endcase
			S2_MemAdr:
				if(Func[0])
					state <= S3_MemRead;
				else
					state <= S5_MemWrite;
			
			S3_MemRead:
				state <= S4_MemWB;
			
			S4_MemWB:
				state <= S0_Fetch;
			
			S5_MemWrite:
				state <= S0_Fetch;
			
			S6_ExecuteR:
				state <= S8_ALUWB;
			
			S7_ExecuteI:
				state <= S8_ALUWB;
			
			S8_ALUWB:
				state <= S0_Fetch;
			
			S9_Branch:
				state <= S0_Fetch;
				
			S10_BranchLink:
				state <= S0_Fetch;
				
			default:
				state <= S0_Fetch;
			
		endcase


	always @(state)
		case(state)
			S0_Fetch:
				begin
				AdrSrc 		= 1'b0;
				ALUSrcA		= 1'b1;
				ALUSrcB		= 2'b10;
				ALUOp			= 1'b0;
				ResultSrc	= 2'b10;
				IRWrite		= 1'b1;
				NextPC		= 1'b1;
				Branch 		= 1'b0;
				RegW			= 1'b0;
				MemW			= 1'b0;
				BL_Active	= 1'b0;
				end
				
			S1_Decode:
				begin
				AdrSrc 		= 1'b0;
				ALUSrcA		= 1'b1;
				ALUSrcB		= 2'b10;
				ALUOp			= 1'b0;
				ResultSrc	= 2'b10;
				IRWrite		= 1'b0;
				NextPC		= 1'b0;
				Branch 		= 1'b0;
				RegW			= 1'b0;
				MemW			= 1'b0;
				BL_Active	= 1'b0;
				end
				
			S2_MemAdr:
				begin
				AdrSrc 		= 1'b0;
				ALUSrcA		= 1'b0;
				ALUSrcB		= 2'b01;
				ALUOp			= 1'b0;
				ResultSrc	= 2'b10;
				IRWrite		= 1'b0;
				NextPC		= 1'b0;
				Branch 		= 1'b0;
				RegW			= 1'b0;
				MemW			= 1'b0;
				BL_Active	= 1'b0;
				end
			
			S3_MemRead:
				begin
				AdrSrc 		= 1'b1;
				ALUSrcA		= 1'b0;
				ALUSrcB		= 2'b01;
				ALUOp			= 1'b0;
				ResultSrc	= 2'b00;
				IRWrite		= 1'b0;
				NextPC		= 1'b0;
				Branch 		= 1'b0;
				RegW			= 1'b0;
				MemW			= 1'b0;
				BL_Active	= 1'b0;
				end
			
			S4_MemWB:
				begin
				AdrSrc 		= 1'b1;
				ALUSrcA		= 1'b0;
				ALUSrcB		= 2'b01;
				ALUOp			= 1'b0;
				ResultSrc	= 2'b01;
				IRWrite		= 1'b0;
				NextPC		= 1'b0;
				Branch 		= 1'b0;
				RegW			= 1'b1;
				MemW			= 1'b0;
				BL_Active	= 1'b0;
				end
			
			S5_MemWrite:
				begin
				AdrSrc 		= 1'b1;
				ALUSrcA		= 1'b0;
				ALUSrcB		= 2'b01;
				ALUOp			= 1'b0;
				ResultSrc	= 2'b00;
				IRWrite		= 1'b0;
				NextPC		= 1'b0;
				Branch 		= 1'b0;
				RegW			= 1'b0;
				MemW			= 1'b1;
				BL_Active	= 1'b0;
				end
			
			S6_ExecuteR:
				begin
				AdrSrc 		= 1'b1;
				ALUSrcA		= 1'b0;
				ALUSrcB		= 2'b00;
				ALUOp			= 1'b1;
				ResultSrc	= 2'b00;
				IRWrite		= 1'b0;
				NextPC		= 1'b0;
				Branch 		= 1'b0;
				RegW			= 1'b0;
				MemW			= 1'b0;
				BL_Active	= 1'b0;
				end
			
			S7_ExecuteI:
				begin
				AdrSrc 		= 1'b1;
				ALUSrcA		= 1'b0;
				ALUSrcB		= 2'b01;
				ALUOp			= 1'b1;
				ResultSrc	= 2'b00;
				IRWrite		= 1'b0;
				NextPC		= 1'b0;
				Branch 		= 1'b0;
				RegW			= 1'b0;
				MemW			= 1'b0;
				BL_Active	= 1'b0;
				end
			
			S8_ALUWB:
				begin
				AdrSrc 		= 1'b1;
				ALUSrcA		= 1'b0;
				ALUSrcB		= 2'b01;
				ALUOp			= 1'b0;
				ResultSrc	= 2'b00;
				IRWrite		= 1'b0;
				NextPC		= 1'b0;
				Branch 		= 1'b0;
				RegW			= 1'b1;
				MemW			= 1'b0;
				BL_Active	= 1'b0;
				end
				
			S9_Branch:
				begin
				AdrSrc 		= 1'b1;
				ALUSrcA		= 1'b0;
				ALUSrcB		= 2'b01;
				ALUOp			= 1'b0;
				ResultSrc	= 2'b10;
				IRWrite		= 1'b0;
				NextPC		= 1'b0;
				Branch 		= 1'b1;
				RegW			= 1'b0;
				MemW			= 1'b0;
				BL_Active	= 1'b0;
				end
				
			S10_BranchLink:
				begin
				AdrSrc 		= 1'b1;
				ALUSrcA		= 1'b0;
				ALUSrcB		= 2'b01;
				ALUOp			= 1'b0;
				ResultSrc	= 2'b10;
				IRWrite		= 1'b0;
				NextPC		= 1'b0;
				Branch 		= 1'b1;
				RegW			= 1'b1;
				MemW			= 1'b0;
				BL_Active	= 1'b1;
				end
				
			default:
				begin
				AdrSrc 		= 1'b0;
				ALUSrcA		= 1'b0;
				ALUSrcB		= 2'b00;
				ALUOp			= 1'b0;
				ResultSrc	= 2'b00;
				IRWrite		= 1'b0;
				NextPC		= 1'b0;
				Branch 		= 1'b0;
				RegW			= 1'b0;
				MemW			= 1'b0;
				BL_Active	= 1'b0;
				end
			
		endcase
		
	

	assign RegSrc[1] = (Op[1:0] == 2'b01);
	assign RegSrc[0] = (Op[1:0] == 2'b10);
	assign Shifter_En = (Op[1:0] == 2'b00) & (state == S7_ExecuteI | state == S6_ExecuteR);
	assign ImmSrc = Op;
	

	assign PCS = ((Rd == 15) & RegW) | Branch;


	always @(Func[4:1], ALUOp)
	if(ALUOp)
		case(Func[4:1])
			4'b0100:
				begin
					ALUControl = 3'b000;
					FlagW		  = (Func[0]) ? 2'b11 : 2'b00;
					NoWrite 	  = 1'b0;
				end
			4'b0010:
				begin
					ALUControl = 3'b001;
					FlagW		  = (Func[0]) ? 2'b11 : 2'b00;
					NoWrite 	  = 1'b0;
				end
			4'b0000:
				begin
					ALUControl = 3'b100;
					FlagW		  = (Func[0]) ? 2'b10 : 2'b00;
					NoWrite 	  = 1'b0;
				end
			4'b1100:
				begin
					ALUControl = 3'b101;
					FlagW		  = (Func[0]) ? 2'b10 : 2'b00;
					NoWrite 	  = 1'b0;
				end
			4'b0001:
				begin
					ALUControl = 3'b110;
					FlagW		  = (Func[0]) ? 2'b10 : 2'b00;
					NoWrite 	  = 1'b0;
				end
			4'b1110:
				begin
					ALUControl = 3'b111;
					FlagW		  = (Func[0]) ? 2'b10 : 2'b00;
					NoWrite 	  = 1'b0;
				end
			4'b1010:
				begin
					ALUControl = 3'b001;
					FlagW		  = 2'b00;
					NoWrite 	  = 1'b1;
				end
			4'b1101:
				begin
					ALUControl = 3'b010;
					FlagW		  = (Func[0]) ? 2'b10 : 2'b00;
					NoWrite 	  = 1'b0;
				end
				
			default: 
				begin
					ALUControl = 3'b000;
					FlagW		  = 2'b00;
					NoWrite 	  = 1'b0;
				end
		endcase
	else
		begin
			ALUControl = 2'b00;
			FlagW		  = 2'b00;
			NoWrite 	  = 1'b0;
		end
	
endmodule