data/full_repos/permissive/510160664/Adders/src/ripple_carry.v
data/verilator_xmls/4594d74b-b972-4b79-8b58-9f02628346e7.xml
module full_adder
(
					input 		A_i,
					input 		B_i,
					input			C_i,

					output	S_o,
					output	C_o
);


assign S_o = A_i ^ B_i ^ C_i;
assign C_o = ((A_i ^ B_i) & C_i) | (A_i & B_i);

endmodule
module full_adder
(
					input 		A_i,
					input 		B_i,
					input			C_i,

					output	S_o,
					output	C_o
);



assign S_o = A_i ^ B_i ^ C_i;
assign C_o = ((A_i ^ B_i) & C_i) | (A_i & B_i);

endmodule