data/full_repos/permissive/489994352/Image-Part/pingpongmem.v
data/verilator_xmls/6f40b173-2a65-436a-adf0-56e4158778d8.xml
module pingpongmem(clk, rst, wren, rden, address1, address2,
                    datain, dataout, inputsize);
input clk,rst;
input wren, rden;
input [31:0] inputsize;
input [31:0] address1, address2;

input [64*16-1:0] datain;
output reg [16*16-1:0] dataout;
reg [15:0] datainmem [63:0];
reg [15:0] dataoutmem [16:0];
reg [15:0] datamem [0:128*55*55-1];



















integer i;
always @(*)
begin
for (i=0; i<64; i=i+1)
    datainmem[i]<=datain[i*16+:16];
end
always @(posedge clk)
if(rst)
    for (i=0; i<64; i=i+1)
        datamem[address1+i*inputsize] <= 16'd0;
else if (wren) begin
    for (i=0; i<64; i=i+1)
        datamem[address1+i*inputsize] <= datainmem[i];
end
always @(posedge clk)
if (rden) begin
    for (i=0;i<16;i=i+1)
        dataoutmem[i] <= datamem[address2+(i*55*55)];
end
always @(*)
begin
for (i=0; i<16; i=i+1)
    dataout[i*16+:16]<=dataoutmem[i];
end
endmodule
module pingpongmem(clk, rst, wren, rden, address1, address2,
                    datain, dataout, inputsize);

input clk,rst;
input wren, rden;
input [31:0] inputsize;
input [31:0] address1, address2;

input [64*16-1:0] datain;
output reg [16*16-1:0] dataout;
reg [15:0] datainmem [63:0];
reg [15:0] dataoutmem [16:0];
reg [15:0] datamem [0:128*55*55-1];



















integer i;
always @(*)
begin
for (i=0; i<64; i=i+1)
    datainmem[i]<=datain[i*16+:16];
end
always @(posedge clk)
if(rst)
    for (i=0; i<64; i=i+1)
        datamem[address1+i*inputsize] <= 16'd0;
else if (wren) begin
    for (i=0; i<64; i=i+1)
        datamem[address1+i*inputsize] <= datainmem[i];
end
always @(posedge clk)
if (rden) begin
    for (i=0;i<16;i=i+1)
        dataoutmem[i] <= datamem[address2+(i*55*55)];
end
always @(*)
begin
for (i=0; i<16; i=i+1)
    dataout[i*16+:16]<=dataoutmem[i];
end
endmodule