data/full_repos/permissive/510956372/src/counter_block.v
1: b'%Error: data/full_repos/permissive/510956372/src/counter_block.v:2: Cannot find include file: bcd_to_ssg.v\n`include "bcd_to_ssg.v" \n         ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/510956372/src,data/full_repos/permissive/510956372/bcd_to_ssg.v\n             data/full_repos/permissive/510956372/src,data/full_repos/permissive/510956372/bcd_to_ssg.v.v\n             data/full_repos/permissive/510956372/src,data/full_repos/permissive/510956372/bcd_to_ssg.v.sv\n             bcd_to_ssg.v\n             bcd_to_ssg.v.v\n             bcd_to_ssg.v.sv\n             obj_dir/bcd_to_ssg.v\n             obj_dir/bcd_to_ssg.v.v\n             obj_dir/bcd_to_ssg.v.sv\n%Error: data/full_repos/permissive/510956372/src/counter_block.v:3: Cannot find include file: reg_4bit.v\n`include "reg_4bit.v" \n         ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/510956372/src/counter_block.v:4: Cannot find include file: counter_bcd.v\n`include "counter_bcd.v" \n         ^~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module counter_block( input enable,
                      input reset,
                      input clk,
                      input load,
                      output [6:0] ssg,
                      output enable_next);
  wire [3:0] bcd_in;
  wire [3:0] bcd_out;
  counter_bcd cntr_bcd(clk, enable, reset, bcd_in, enable_next);
  reg_4bit r4b(load, clk, bcd_in, bcd_out);
  bcd_to_ssg bcd2ssg(bcd_out, ssg);  
endmodule
module counter_block( input enable,
                      input reset,
                      input clk,
                      input load,
                      output [6:0] ssg,
                      output enable_next);

  wire [3:0] bcd_in;
  wire [3:0] bcd_out;
  counter_bcd cntr_bcd(clk, enable, reset, bcd_in, enable_next);
  reg_4bit r4b(load, clk, bcd_in, bcd_out);
  bcd_to_ssg bcd2ssg(bcd_out, ssg);  
endmodule