data/full_repos/permissive/458737381/src/verilog-parser/tests/bw_io_cmos2_term_up.v
data/verilator_xmls/b9ab9f97-51bb-43d1-b1f7-e5e7d4ad3101.xml
module bw_io_cmos2_term_up (
   vddo, out
   );

   inout        out;              
   input	vddo;	

endmodule
module bw_io_cmos2_term_up (
   vddo, out
   );


   inout        out;              
   input	vddo;	

endmodule