data/full_repos/permissive/452648646/src/alu.v
1: b'%Error: data/full_repos/permissive/452648646/src/alu.v:1: Cannot find include file: opcode.vh\n`include "opcode.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/452648646/src,data/full_repos/permissive/452648646/opcode.vh\n             data/full_repos/permissive/452648646/src,data/full_repos/permissive/452648646/opcode.vh.v\n             data/full_repos/permissive/452648646/src,data/full_repos/permissive/452648646/opcode.vh.sv\n             opcode.vh\n             opcode.vh.v\n             opcode.vh.sv\n             obj_dir/opcode.vh\n             obj_dir/opcode.vh.v\n             obj_dir/opcode.vh.sv\n%Error: data/full_repos/permissive/452648646/src/alu.v:15: Define or directive not defined: \'`OPCODE_OP_IMM\'\nwire [31:0] b = opcode == `OPCODE_OP_IMM ? imm : rs2_value;\n                          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452648646/src/alu.v:15: syntax error, unexpected \'?\', expecting TYPE-IDENTIFIER\nwire [31:0] b = opcode == `OPCODE_OP_IMM ? imm : rs2_value;\n                                         ^\n%Error: data/full_repos/permissive/452648646/src/alu.v:19: Define or directive not defined: \'`FUNCT3_ADD\'\n        `FUNCT3_ADD: begin\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/452648646/src/alu.v:19: syntax error, unexpected \':\', expecting endcase\n        `FUNCT3_ADD: begin\n                   ^\n%Error: data/full_repos/permissive/452648646/src/alu.v:20: Define or directive not defined: \'`OPCODE_OP\'\n            if (opcode == `OPCODE_OP && (funct7 & `FUNCT7_ALTERNATE) != 0) begin\n                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/452648646/src/alu.v:20: Define or directive not defined: \'`FUNCT7_ALTERNATE\'\n            if (opcode == `OPCODE_OP && (funct7 & `FUNCT7_ALTERNATE) != 0) begin\n                                                  ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452648646/src/alu.v:26: Define or directive not defined: \'`FUNCT3_SLL\'\n        `FUNCT3_SLL: begin\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/452648646/src/alu.v:29: Define or directive not defined: \'`FUNCT3_SLT\'\n        `FUNCT3_SLT: begin\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/452648646/src/alu.v:32: Define or directive not defined: \'`FUNCT3_SLTU\'\n        `FUNCT3_SLTU: begin\n        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/452648646/src/alu.v:35: Define or directive not defined: \'`FUNCT3_XOR\'\n        `FUNCT3_XOR: begin\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/452648646/src/alu.v:38: Define or directive not defined: \'`FUNCT3_SRL\'\n        `FUNCT3_SRL: begin\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/452648646/src/alu.v:39: Define or directive not defined: \'`OPCODE_OP_IMM\'\n            if (((opcode == `OPCODE_OP_IMM ? imm[11:5] : funct7) & `FUNCT7_ALTERNATE) != 0) begin\n                            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452648646/src/alu.v:39: Define or directive not defined: \'`FUNCT7_ALTERNATE\'\n            if (((opcode == `OPCODE_OP_IMM ? imm[11:5] : funct7) & `FUNCT7_ALTERNATE) != 0) begin\n                                                                   ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452648646/src/alu.v:45: Define or directive not defined: \'`FUNCT3_OR\'\n        `FUNCT3_OR: begin\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/452648646/src/alu.v:48: Define or directive not defined: \'`FUNCT3_AND\'\n        `FUNCT3_AND: begin\n        ^~~~~~~~~~~\n%Error: data/full_repos/permissive/452648646/src/alu.v:55: Define or directive not defined: \'`OPCODE_OP\'\nassign error = (opcode == `OPCODE_OP || opcode == `OPCODE_OP_IMM) && (bad_funct7_error);\n                          ^~~~~~~~~~\n%Error: data/full_repos/permissive/452648646/src/alu.v:55: syntax error, unexpected ||, expecting TYPE-IDENTIFIER\nassign error = (opcode == `OPCODE_OP || opcode == `OPCODE_OP_IMM) && (bad_funct7_error);\n                                     ^~\n%Error: data/full_repos/permissive/452648646/src/alu.v:55: Define or directive not defined: \'`OPCODE_OP_IMM\'\nassign error = (opcode == `OPCODE_OP || opcode == `OPCODE_OP_IMM) && (bad_funct7_error);\n                                                  ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452648646/src/alu.v:58: Define or directive not defined: \'`OPCODE_OP\'\n    if (opcode == `OPCODE_OP) begin\n                  ^~~~~~~~~~\n%Error: data/full_repos/permissive/452648646/src/alu.v:58: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    if (opcode == `OPCODE_OP) begin\n                            ^\n%Error: data/full_repos/permissive/452648646/src/alu.v:59: Define or directive not defined: \'`FUNCT7_ALTERNATE\'\n        if (funct7 == `FUNCT7_ALTERNATE) begin\n                      ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/452648646/src/alu.v:60: Define or directive not defined: \'`FUNCT3_ADD\'\n            bad_funct7_error = funct3 != `FUNCT3_ADD && funct3 != `FUNCT3_SRL;\n                                         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/452648646/src/alu.v:60: Define or directive not defined: \'`FUNCT3_SRL\'\n            bad_funct7_error = funct3 != `FUNCT3_ADD && funct3 != `FUNCT3_SRL;\n                                                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/452648646/src/alu.v:61: Define or directive not defined: \'`FUNCT7_NORMAL\'\n        end else if (funct7 == `FUNCT7_NORMAL) begin\n                               ^~~~~~~~~~~~~~\n%Error: Cannot continue\n'
module alu (
    input wire [6:0] opcode,
    input wire [2:0] funct3,
    input wire [6:0] funct7,
    input wire [31:0] rs1_value,
    input wire [31:0] rs2_value,
    input wire [31:0] imm,
    output reg [31:0] result,
    output wire error
);

wire [31:0] a = rs1_value;
wire [31:0] b = opcode == `OPCODE_OP_IMM ? imm : rs2_value;

always @(opcode, funct3, funct7, a, b) begin
    case (funct3)
        `FUNCT3_ADD: begin
            if (opcode == `OPCODE_OP && (funct7 & `FUNCT7_ALTERNATE) != 0) begin
                result = a - b;
            end else begin
                result = a + b;
            end
        end
        `FUNCT3_SLL: begin
            result = a << b[4:0];
        end
        `FUNCT3_SLT: begin
            result = $signed(a) < $signed(b) ? 1 : 0;
        end
        `FUNCT3_SLTU: begin
            result = a < b ? 1 : 0;
        end
        `FUNCT3_XOR: begin
            result = a ^ b;
        end
        `FUNCT3_SRL: begin
            if (((opcode == `OPCODE_OP_IMM ? imm[11:5] : funct7) & `FUNCT7_ALTERNATE) != 0) begin
                result = $signed(a) >>> b[4:0];
            end else begin
                result = a >> b[4:0];
            end
        end
        `FUNCT3_OR: begin
            result = a | b;
        end
        `FUNCT3_AND: begin
            result = a & b;
        end
    endcase
end

reg bad_funct7_error;
assign error = (opcode == `OPCODE_OP || opcode == `OPCODE_OP_IMM) && (bad_funct7_error);

always @(opcode, funct3, funct7) begin
    if (opcode == `OPCODE_OP) begin
        if (funct7 == `FUNCT7_ALTERNATE) begin
            bad_funct7_error = funct3 != `FUNCT3_ADD && funct3 != `FUNCT3_SRL;
        end else if (funct7 == `FUNCT7_NORMAL) begin
            bad_funct7_error = 0;
        end else begin
            bad_funct7_error = 1;
        end
    end else begin
        bad_funct7_error = 0;
    end
end

endmodule
module alu (
    input wire [6:0] opcode,
    input wire [2:0] funct3,
    input wire [6:0] funct7,
    input wire [31:0] rs1_value,
    input wire [31:0] rs2_value,
    input wire [31:0] imm,
    output reg [31:0] result,
    output wire error
);


wire [31:0] a = rs1_value;
wire [31:0] b = opcode == `OPCODE_OP_IMM ? imm : rs2_value;

always @(opcode, funct3, funct7, a, b) begin
    case (funct3)
        `FUNCT3_ADD: begin
            if (opcode == `OPCODE_OP && (funct7 & `FUNCT7_ALTERNATE) != 0) begin
                result = a - b;
            end else begin
                result = a + b;
            end
        end
        `FUNCT3_SLL: begin
            result = a << b[4:0];
        end
        `FUNCT3_SLT: begin
            result = $signed(a) < $signed(b) ? 1 : 0;
        end
        `FUNCT3_SLTU: begin
            result = a < b ? 1 : 0;
        end
        `FUNCT3_XOR: begin
            result = a ^ b;
        end
        `FUNCT3_SRL: begin
            if (((opcode == `OPCODE_OP_IMM ? imm[11:5] : funct7) & `FUNCT7_ALTERNATE) != 0) begin
                result = $signed(a) >>> b[4:0];
            end else begin
                result = a >> b[4:0];
            end
        end
        `FUNCT3_OR: begin
            result = a | b;
        end
        `FUNCT3_AND: begin
            result = a & b;
        end
    endcase
end

reg bad_funct7_error;
assign error = (opcode == `OPCODE_OP || opcode == `OPCODE_OP_IMM) && (bad_funct7_error);

always @(opcode, funct3, funct7) begin
    if (opcode == `OPCODE_OP) begin
        if (funct7 == `FUNCT7_ALTERNATE) begin
            bad_funct7_error = funct3 != `FUNCT3_ADD && funct3 != `FUNCT3_SRL;
        end else if (funct7 == `FUNCT7_NORMAL) begin
            bad_funct7_error = 0;
        end else begin
            bad_funct7_error = 1;
        end
    end else begin
        bad_funct7_error = 0;
    end
end

endmodule