data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/dv/uvm/icache/dv/prim_badbit/prim_badbit_ram_1p.sv
1: b'%Error: data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/dv/uvm/icache/dv/prim_badbit/prim_badbit_ram_1p.sv:11: Cannot find include file: prim_assert.sv\n`include "prim_assert.sv" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/dv/uvm/icache/dv/prim_badbit,data/full_repos/permissive/509468557/prim_assert.sv\n             data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/dv/uvm/icache/dv/prim_badbit,data/full_repos/permissive/509468557/prim_assert.sv.v\n             data/full_repos/permissive/509468557/generators/ibex/src/main/resources/vsrc/ibex/dv/uvm/icache/dv/prim_badbit,data/full_repos/permissive/509468557/prim_assert.sv.sv\n             prim_assert.sv\n             prim_assert.sv.v\n             prim_assert.sv.sv\n             obj_dir/prim_assert.sv\n             obj_dir/prim_assert.sv.v\n             obj_dir/prim_assert.sv.sv\n%Error: Exiting due to 1 error(s)\n'
module prim_badbit_ram_1p #(
  parameter  int Width           = 32,
  parameter  int Depth           = 128,
  parameter  int DataBitsPerMask = 1,
  parameter      MemInitFile     = "",

  localparam int Aw              = $clog2(Depth)
) (
  input  logic             clk_i,

  input  logic             req_i,
  input  logic             write_i,
  input  logic [Aw-1:0]    addr_i,
  input  logic [Width-1:0] wdata_i,
  input  logic [Width-1:0] wmask_i,
  output logic [Width-1:0] rdata_o
);

  logic [Width-1:0] sram_rdata;

  prim_generic_ram_1p #(
    .Width           (Width),
    .Depth           (Depth),
    .DataBitsPerMask (DataBitsPerMask),
    .MemInitFile     (MemInitFile)
  ) u_mem (
    .clk_i   (clk_i),

    .cfg_i   ('0),
    .req_i   (req_i),
    .write_i (write_i),
    .addr_i  (addr_i),
    .wdata_i (wdata_i),
    .wmask_i (wmask_i),
    .rdata_o (sram_rdata)
  );





`ifdef VERILATOR
  assign rdata_o = sram_rdata;
`else



  `ASSERT_INIT(WidthSmallEnough, Width <= 128)
  `ASSERT_INIT(AddrSmallEnough, Aw <= 32)


  logic [31:0] width;
  assign width = Width;


  logic [31:0]  addr;
  logic [127:0] wdata, wmask, rdata;
  assign addr  = {{32-Aw{1'b0}}, addr_i};
  assign wdata = {{128-Width{1'b0}}, wdata_i};
  assign wmask = {{128-Width{1'b0}}, wmask_i};
  assign rdata = {{128-Width{1'b0}}, sram_rdata};




  wor [127:0] bad_bit_mask;
  assign bad_bit_mask = 128'b0;

  assign rdata_o = sram_rdata ^ bad_bit_mask;
`endif

endmodule
module prim_badbit_ram_1p #(
  parameter  int Width           = 32,
  parameter  int Depth           = 128,
  parameter  int DataBitsPerMask = 1,
  parameter      MemInitFile     = "",

  localparam int Aw              = $clog2(Depth)
) (
  input  logic             clk_i,

  input  logic             req_i,
  input  logic             write_i,
  input  logic [Aw-1:0]    addr_i,
  input  logic [Width-1:0] wdata_i,
  input  logic [Width-1:0] wmask_i,
  output logic [Width-1:0] rdata_o
);


  logic [Width-1:0] sram_rdata;

  prim_generic_ram_1p #(
    .Width           (Width),
    .Depth           (Depth),
    .DataBitsPerMask (DataBitsPerMask),
    .MemInitFile     (MemInitFile)
  ) u_mem (
    .clk_i   (clk_i),

    .cfg_i   ('0),
    .req_i   (req_i),
    .write_i (write_i),
    .addr_i  (addr_i),
    .wdata_i (wdata_i),
    .wmask_i (wmask_i),
    .rdata_o (sram_rdata)
  );





`ifdef VERILATOR
  assign rdata_o = sram_rdata;
`else



  `ASSERT_INIT(WidthSmallEnough, Width <= 128)
  `ASSERT_INIT(AddrSmallEnough, Aw <= 32)


  logic [31:0] width;
  assign width = Width;


  logic [31:0]  addr;
  logic [127:0] wdata, wmask, rdata;
  assign addr  = {{32-Aw{1'b0}}, addr_i};
  assign wdata = {{128-Width{1'b0}}, wdata_i};
  assign wmask = {{128-Width{1'b0}}, wmask_i};
  assign rdata = {{128-Width{1'b0}}, sram_rdata};




  wor [127:0] bad_bit_mask;
  assign bad_bit_mask = 128'b0;

  assign rdata_o = sram_rdata ^ bad_bit_mask;
`endif

endmodule