data/full_repos/permissive/506562943/DigitalCircuits/2.1-3-to-8-decoder/rtl/logic_decoder_3_8.v
data/verilator_xmls/2d77f6f3-d306-4744-bf94-f8a00c0d5ac7.xml
module logic_decoder_3_8 (
	input [2:0] addr,
	output [7:0] out
);


assign out[0] = !(!addr[0] & !addr[1] & !addr[2]);
assign out[1] = !(addr[0] & !addr[1] & !addr[2]);
assign out[2] = !(!addr[0] & addr[1] & !addr[2]);
assign out[3] = !(addr[0] & addr[1] & !addr[2]);
assign out[4] = !(!addr[0] & !addr[1] & addr[2]);
assign out[5] = !(addr[0] & !addr[1] & addr[2]);
assign out[6] = !(!addr[0] & addr[1] & addr[2]);
assign out[7] = !(addr[0] & addr[1] & addr[2]);
 
endmodule
module logic_decoder_3_8 (
	input [2:0] addr,
	output [7:0] out
);



assign out[0] = !(!addr[0] & !addr[1] & !addr[2]);
assign out[1] = !(addr[0] & !addr[1] & !addr[2]);
assign out[2] = !(!addr[0] & addr[1] & !addr[2]);
assign out[3] = !(addr[0] & addr[1] & !addr[2]);
assign out[4] = !(!addr[0] & !addr[1] & addr[2]);
assign out[5] = !(addr[0] & !addr[1] & addr[2]);
assign out[6] = !(!addr[0] & addr[1] & addr[2]);
assign out[7] = !(addr[0] & addr[1] & addr[2]);
 
endmodule