data/full_repos/permissive/467394306/qsim_rtl/tb_rbuf/tb_rbuf.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/467394306/qsim_rtl/tb_rbuf/tb_rbuf.v:20: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/467394306/qsim_rtl/tb_rbuf/tb_rbuf.v:30: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/467394306/qsim_rtl/tb_rbuf/tb_rbuf.v:34: syntax error, unexpected \'@\'\n        @(posedge clk);   \n        ^\n%Error: data/full_repos/permissive/467394306/qsim_rtl/tb_rbuf/tb_rbuf.v:47: syntax error, unexpected \'@\'\n            @(posedge clk);\n            ^\n%Error: Exiting due to 3 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();
    reg clk, rstn, abufread, abufwrite;
    reg [7:0] abufdin;
    wire [7:0] abufdout;
    integer i;

    RBUF #(.WORDLEN(8), .BUFSIZE(16)) abuf (
                .clk(clk),
                .rstn(rstn),
                .read(abufread),
                .write(abufwrite),
                .din(abufdin),
                .dout(abufdout));


    always begin
	`HALF_CLOCK_PERIOD;
	clk = ~clk;
    end

    initial begin
        clk = 0;
        rstn = 0;
        abufread = 0;
        abufwrite = 0;
        abufdin = 0;
        @(posedge clk);

	@(negedge clk);
        rstn = 1;
        @(posedge clk);

        for (i=0; i<32; i=i+1) begin
            if (i<4) begin
                abufwrite = 1;
                abufdin = i;
            end else if (i<8) begin
                abufwrite = 0;
                abufread = 1;
            end else begin
                abufwrite = 1;
                abufdin = i;
            end
            @(posedge clk);
        end
        $finish;
    end

endmodule
module testbench();

    reg clk, rstn, abufread, abufwrite;
    reg [7:0] abufdin;
    wire [7:0] abufdout;
    integer i;

    RBUF #(.WORDLEN(8), .BUFSIZE(16)) abuf (
                .clk(clk),
                .rstn(rstn),
                .read(abufread),
                .write(abufwrite),
                .din(abufdin),
                .dout(abufdout));


    always begin
	`HALF_CLOCK_PERIOD;
	clk = ~clk;
    end

    initial begin
        clk = 0;
        rstn = 0;
        abufread = 0;
        abufwrite = 0;
        abufdin = 0;
        @(posedge clk);

	@(negedge clk);
        rstn = 1;
        @(posedge clk);

        for (i=0; i<32; i=i+1) begin
            if (i<4) begin
                abufwrite = 1;
                abufdin = i;
            end else if (i<8) begin
                abufwrite = 0;
                abufread = 1;
            end else begin
                abufwrite = 1;
                abufdin = i;
            end
            @(posedge clk);
        end
        $finish;
    end

endmodule