data/full_repos/permissive/513628330/Gateware/src/sndgen.v
1: b"%Error: data/full_repos/permissive/513628330/Gateware/src/sndgen.v:191: Cannot find file containing module: 'sat'\n sat #(.isz(32-4), .osz(16))\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/513628330/Gateware/src,data/full_repos/permissive/513628330/sat\n             data/full_repos/permissive/513628330/Gateware/src,data/full_repos/permissive/513628330/sat.v\n             data/full_repos/permissive/513628330/Gateware/src,data/full_repos/permissive/513628330/sat.sv\n             sat\n             sat.v\n             sat.sv\n             obj_dir/sat\n             obj_dir/sat.v\n             obj_dir/sat.sv\n%Error: data/full_repos/permissive/513628330/Gateware/src/sndgen.v:193: Cannot find file containing module: 'sat'\n sat #(.isz(32-4), .osz(16))\n ^~~\n%Error: Exiting due to 2 error(s)\n"
module sndgen(
	input clk,
	input reset,
	input cs,
	input [3:0] we,
	input [7:0] addr,
	input [31:0] din,
	inout [1:0] pdm
);

	reg [4:0] seq, seq_d1, seq_d2;
	reg sync_d3;
	always @(posedge clk)
		if(reset)
		begin
			seq <= 5'h00;
			seq_d1 <= 5'h00;
			seq_d2 <= 5'h00;
			sync_d3 <= 1'b0;
		end
		else
		begin
			seq <= seq + 1;
			seq_d1 <= seq;
			seq_d2 <= seq_d1;
			sync_d3 <= (seq_d2==5'h00);
		end
	

	wire [31:0] frq;
	wire fsel = cs & ~addr[6];
	bram_256x32 ufrq(
		.clk(clk),
		.sel(fsel),
		.we(we),
		.waddr({3'b000,addr[4:0]}),
		.raddr({3'b000,seq}),
		.wdat(din),
		.rdat(frq)
	);
	
	wire [31:0] amp;
	wire asel = cs & addr[6];
	bram_256x32 uamp(
		.clk(clk),
		.sel(asel),
		.we(we),
		.waddr({3'b000,addr[4:0]}),
		.raddr({3'b000,seq_d1}),
		.wdat(din),
		.rdat(amp)
	);
	

	wire [31:0] phs_in;
	reg [31:0] phs;
	bram_256x32 uphs(
		.clk(clk),
		.sel(1'b1),
		.we(4'b1111),
		.waddr({3'b000,seq_d2}),
		.raddr({3'b000,seq}),
		.wdat(phs),
		.rdat(phs_in)
	);
	always @(posedge clk)
		if(reset)
			phs <= 32'd0;
		else
			phs <= phs_in + frq;
	

	wire signed [15:0] saw = phs[31:16];
	

	wire signed [15:0] la = amp[15:0], ra = amp[31:16];
		

	reg signed [31:0] lg, rg;
	always @(posedge clk)
		if(reset)
		begin
			lg <= 32'd0;
			rg <= 32'd0;
		end
		else
		begin
			lg <= saw * la;
			rg <= saw * ra;
		end
	

	wire signed [20:0]	lg_x = {{5{lg[30]}},lg[30:15]},
						rg_x = {{5{rg[30]}},rg[30:15]}; 
	reg signed [20:0] acc_l, acc_r;
	reg signed [15:0] mix_l, mix_r;
	wire signed [15:0] sat_l, sat_r;
	always @(posedge clk)
		if(reset)
		begin
			acc_l <= 21'h000000;
			acc_r <= 21'h000000;
			mix_l <= 16'h0000;
			mix_r <= 16'h0000;
		end
		else
		begin
			if(sync_d3)
			begin

				acc_l <= lg_x + 21'h000010;
				acc_r <= rg_x + 21'h000010;
				mix_l <= sat_l;
				mix_r <= sat_r;
			end
			else
			begin

				acc_l <= lg_x + acc_l;
				acc_r <= rg_x + acc_r;
			end
		end
	

`define SAT_SHF 4
	sat #(.isz(32-`SAT_SHF), .osz(16))
		u_lsat(.in(acc_l[31:`SAT_SHF]), .out(sat_l));
	sat #(.isz(32-`SAT_SHF), .osz(16))
		u_rsat(.in(acc_r[31:`SAT_SHF]), .out(sat_r));
		


	reg pdm_clk_en;
	reg [7:0] pdm_clk_cnt;
	always @(posedge clk)
		if(reset)
		begin
			pdm_clk_en <= 1'b1;
			pdm_clk_cnt <= 8'h00;
		end
		else
		begin
			pdm_clk_cnt <= pdm_clk_cnt + 8'h01;

			pdm_clk_en <= 1'b1;
		end
		
	pdm_enc #(.DSZ(16))
		updm_l(
			.clk(clk),
			.reset(reset),
			.clk_en(pdm_clk_en),
			.data(mix_l),
			.pdm(pdm[0])
		);
	pdm_enc #(.DSZ(16))
		updm_r(
			.clk(clk),
			.reset(reset),
			.clk_en(pdm_clk_en),
			.data(mix_r),
			.pdm(pdm[1])
		);
endmodule
module sndgen(
	input clk,
	input reset,
	input cs,
	input [3:0] we,
	input [7:0] addr,
	input [31:0] din,
	inout [1:0] pdm
);


	reg [4:0] seq, seq_d1, seq_d2;
	reg sync_d3;
	always @(posedge clk)
		if(reset)
		begin
			seq <= 5'h00;
			seq_d1 <= 5'h00;
			seq_d2 <= 5'h00;
			sync_d3 <= 1'b0;
		end
		else
		begin
			seq <= seq + 1;
			seq_d1 <= seq;
			seq_d2 <= seq_d1;
			sync_d3 <= (seq_d2==5'h00);
		end
	

	wire [31:0] frq;
	wire fsel = cs & ~addr[6];
	bram_256x32 ufrq(
		.clk(clk),
		.sel(fsel),
		.we(we),
		.waddr({3'b000,addr[4:0]}),
		.raddr({3'b000,seq}),
		.wdat(din),
		.rdat(frq)
	);
	
	wire [31:0] amp;
	wire asel = cs & addr[6];
	bram_256x32 uamp(
		.clk(clk),
		.sel(asel),
		.we(we),
		.waddr({3'b000,addr[4:0]}),
		.raddr({3'b000,seq_d1}),
		.wdat(din),
		.rdat(amp)
	);
	

	wire [31:0] phs_in;
	reg [31:0] phs;
	bram_256x32 uphs(
		.clk(clk),
		.sel(1'b1),
		.we(4'b1111),
		.waddr({3'b000,seq_d2}),
		.raddr({3'b000,seq}),
		.wdat(phs),
		.rdat(phs_in)
	);
	always @(posedge clk)
		if(reset)
			phs <= 32'd0;
		else
			phs <= phs_in + frq;
	

	wire signed [15:0] saw = phs[31:16];
	

	wire signed [15:0] la = amp[15:0], ra = amp[31:16];
		

	reg signed [31:0] lg, rg;
	always @(posedge clk)
		if(reset)
		begin
			lg <= 32'd0;
			rg <= 32'd0;
		end
		else
		begin
			lg <= saw * la;
			rg <= saw * ra;
		end
	

	wire signed [20:0]	lg_x = {{5{lg[30]}},lg[30:15]},
						rg_x = {{5{rg[30]}},rg[30:15]}; 
	reg signed [20:0] acc_l, acc_r;
	reg signed [15:0] mix_l, mix_r;
	wire signed [15:0] sat_l, sat_r;
	always @(posedge clk)
		if(reset)
		begin
			acc_l <= 21'h000000;
			acc_r <= 21'h000000;
			mix_l <= 16'h0000;
			mix_r <= 16'h0000;
		end
		else
		begin
			if(sync_d3)
			begin

				acc_l <= lg_x + 21'h000010;
				acc_r <= rg_x + 21'h000010;
				mix_l <= sat_l;
				mix_r <= sat_r;
			end
			else
			begin

				acc_l <= lg_x + acc_l;
				acc_r <= rg_x + acc_r;
			end
		end
	

`define SAT_SHF 4
	sat #(.isz(32-`SAT_SHF), .osz(16))
		u_lsat(.in(acc_l[31:`SAT_SHF]), .out(sat_l));
	sat #(.isz(32-`SAT_SHF), .osz(16))
		u_rsat(.in(acc_r[31:`SAT_SHF]), .out(sat_r));
		


	reg pdm_clk_en;
	reg [7:0] pdm_clk_cnt;
	always @(posedge clk)
		if(reset)
		begin
			pdm_clk_en <= 1'b1;
			pdm_clk_cnt <= 8'h00;
		end
		else
		begin
			pdm_clk_cnt <= pdm_clk_cnt + 8'h01;

			pdm_clk_en <= 1'b1;
		end
		
	pdm_enc #(.DSZ(16))
		updm_l(
			.clk(clk),
			.reset(reset),
			.clk_en(pdm_clk_en),
			.data(mix_l),
			.pdm(pdm[0])
		);
	pdm_enc #(.DSZ(16))
		updm_r(
			.clk(clk),
			.reset(reset),
			.clk_en(pdm_clk_en),
			.data(mix_r),
			.pdm(pdm[1])
		);
endmodule