data/full_repos/permissive/487479924/top.v
1: b"%Error: data/full_repos/permissive/487479924/top.v:16: Cannot find file containing module: 'clk_10mhz'\nclk_10mhz dcm (\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/487479924,data/full_repos/permissive/487479924/clk_10mhz\n             data/full_repos/permissive/487479924,data/full_repos/permissive/487479924/clk_10mhz.v\n             data/full_repos/permissive/487479924,data/full_repos/permissive/487479924/clk_10mhz.sv\n             clk_10mhz\n             clk_10mhz.v\n             clk_10mhz.sv\n             obj_dir/clk_10mhz\n             obj_dir/clk_10mhz.v\n             obj_dir/clk_10mhz.sv\n%Error: data/full_repos/permissive/487479924/top.v:22: Cannot find file containing module: 'clk_1hz'\nclk_1hz counter (\n^~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module top (
    input wire rst,
    output wire rst_cpu,
	 
    input wire clk,
    output reg clk_cpu,
	 
    input wire [15:0] A,
    output wire [7:0] D,
    output wire [7:0] LED
);

wire dcm_out;
wire counter_out;

clk_10mhz dcm (
    .CLKIN_IN(clk), 
    .RST_IN(~rst), 
    .CLKFX_OUT(dcm_out)
);

clk_1hz counter (
  .clk(dcm_out),
  .thresh0(counter_out)
);

assign rst_cpu = rst;

always @(posedge counter_out) begin
    if (!rst)
	     clk_cpu <= 0;
	 else
	     clk_cpu <= !clk_cpu;
end

assign D = 8'hEA;
assign LED[7:0] = A[7:0];

endmodule
module top (
    input wire rst,
    output wire rst_cpu,
	 
    input wire clk,
    output reg clk_cpu,
	 
    input wire [15:0] A,
    output wire [7:0] D,
    output wire [7:0] LED
);


wire dcm_out;
wire counter_out;

clk_10mhz dcm (
    .CLKIN_IN(clk), 
    .RST_IN(~rst), 
    .CLKFX_OUT(dcm_out)
);

clk_1hz counter (
  .clk(dcm_out),
  .thresh0(counter_out)
);

assign rst_cpu = rst;

always @(posedge counter_out) begin
    if (!rst)
	     clk_cpu <= 0;
	 else
	     clk_cpu <= !clk_cpu;
end

assign D = 8'hEA;
assign LED[7:0] = A[7:0];

endmodule