data/full_repos/permissive/518307247/iiitb_jc.v
data/verilator_xmls/4bf2fdaf-dca0-4ef3-87fa-5fd7a4d733db.xml
module iiitb_jc (reset,clk, q);
input reset, clk;
output reg [7:0] q;
always @(negedge reset or posedge clk)
begin
if(reset==0)
q <= 0;
else
q <= {{q[6:0]},{~q[7]}};
end
endmodule
module iiitb_jc (reset,clk, q);

input reset, clk;
output reg [7:0] q;
always @(negedge reset or posedge clk)
begin
if(reset==0)
q <= 0;
else
q <= {{q[6:0]},{~q[7]}};
end
endmodule