data/full_repos/permissive/448627443/Peripherals/APB_UART/RTL/UART.v
data/verilator_xmls/7840526d-fdcf-42be-abd3-2afae07c246c.xml
module UART (
  input               sio_txdata_valid,
  output              sio_txdata_ready,
  input      [7:0]    sio_txdata_payload,
  output              sio_rxdata_valid,
  input               sio_rxdata_ready,
  output     [7:0]    sio_rxdata_payload,
  input      [15:0]   sio_reg_ClkDiv,
  input               sio_reg_ROverRun,
  output reg          sio_reg_OverRun,
  input      [3:0]    sio_reg_TXThreshold,
  input      [3:0]    sio_reg_RXThreshold,
  output              sio_reg_TXBusy,
  output              sio_reg_RXBusy,
  output     [3:0]    sio_reg_TXCnt,
  output     [3:0]    sio_reg_RXCnt,
  output              eio_txd,
  input               eio_rxd,
  output              int_TXFIFOEmpty,
  output              int_RXFIFOFull,
  input               clk,
  input               resetn
);
  reg                 rx_io_data_ready;
  wire                tx_io_data_ready;
  wire                tx_io_txd;
  wire                tx_io_busy;
  wire                rx_io_data_valid;
  wire       [7:0]    rx_io_data_payload;
  wire                rx_io_busy;
  wire                RXStream_io_push_ready;
  wire                RXStream_io_pop_valid;
  wire       [7:0]    RXStream_io_pop_payload;
  wire       [2:0]    RXStream_io_occupancy;
  wire       [2:0]    RXStream_io_availability;
  wire                TXStream_io_push_ready;
  wire                TXStream_io_pop_valid;
  wire       [7:0]    TXStream_io_pop_payload;
  wire       [2:0]    TXStream_io_occupancy;
  wire       [2:0]    TXStream_io_availability;
  reg        [15:0]   tickgen_counter;
  wire                tickgen_tick;
  wire                when_UART_l114;
  wire                when_Stream_l408;
  reg                 tr_valid;
  wire                tr_ready;
  wire       [7:0]    tr_payload;
  wire                when_UART_l131;

  UART_TX tx (
    .io_tick            (tickgen_tick             ),
    .io_data_valid      (TXStream_io_pop_valid    ),
    .io_data_ready      (tx_io_data_ready         ),
    .io_data_payload    (TXStream_io_pop_payload  ),
    .io_txd             (tx_io_txd                ),
    .io_busy            (tx_io_busy               ),
    .clk                (clk                      ),
    .resetn             (resetn                   )
  );
  UART_RX rx (
    .io_tick            (tickgen_tick        ),
    .io_data_valid      (rx_io_data_valid    ),
    .io_data_ready      (rx_io_data_ready    ),
    .io_data_payload    (rx_io_data_payload  ),
    .io_rxd             (eio_rxd             ),
    .io_busy            (rx_io_busy          ),
    .clk                (clk                 ),
    .resetn             (resetn              )
  );
  StreamFifo RXStream (
    .io_push_valid      (tr_valid                  ),
    .io_push_ready      (RXStream_io_push_ready    ),
    .io_push_payload    (tr_payload                ),
    .io_pop_valid       (RXStream_io_pop_valid     ),
    .io_pop_ready       (sio_rxdata_ready          ),
    .io_pop_payload     (RXStream_io_pop_payload   ),
    .io_flush           (1'b0                      ),
    .io_occupancy       (RXStream_io_occupancy     ),
    .io_availability    (RXStream_io_availability  ),
    .clk                (clk                       ),
    .resetn             (resetn                    )
  );
  StreamFifo TXStream (
    .io_push_valid      (sio_txdata_valid          ),
    .io_push_ready      (TXStream_io_push_ready    ),
    .io_push_payload    (sio_txdata_payload        ),
    .io_pop_valid       (TXStream_io_pop_valid     ),
    .io_pop_ready       (tx_io_data_ready          ),
    .io_pop_payload     (TXStream_io_pop_payload   ),
    .io_flush           (1'b0                      ),
    .io_occupancy       (TXStream_io_occupancy     ),
    .io_availability    (TXStream_io_availability  ),
    .clk                (clk                       ),
    .resetn             (resetn                    )
  );
  assign sio_reg_TXCnt = {1'd0, TXStream_io_occupancy};
  assign sio_reg_RXCnt = {1'd0, RXStream_io_occupancy};
  assign sio_reg_TXBusy = tx_io_busy;
  assign sio_reg_RXBusy = rx_io_busy;
  assign sio_txdata_ready = TXStream_io_push_ready;
  assign sio_rxdata_valid = RXStream_io_pop_valid;
  assign sio_rxdata_payload = RXStream_io_pop_payload;
  assign int_RXFIFOFull = (sio_reg_RXThreshold < sio_reg_RXCnt);
  assign int_TXFIFOEmpty = (sio_reg_TXCnt < sio_reg_TXThreshold);
  assign tickgen_tick = (tickgen_counter == 16'h0);
  assign when_UART_l114 = ((tickgen_counter == 16'h0) || (sio_reg_ClkDiv < tickgen_counter));
  assign eio_txd = tx_io_txd;
  assign when_Stream_l408 = (RXStream_io_occupancy == 3'b011);
  always @(*) begin
    tr_valid = rx_io_data_valid;
    if(when_Stream_l408) begin
      tr_valid = 1'b0;
    end
  end

  always @(*) begin
    rx_io_data_ready = tr_ready;
    if(when_Stream_l408) begin
      rx_io_data_ready = 1'b1;
    end
  end

  assign tr_payload = rx_io_data_payload;
  assign tr_ready = RXStream_io_push_ready;
  assign when_UART_l131 = (rx_io_data_valid && (RXStream_io_occupancy == 3'b011));
  always @(posedge clk or negedge resetn) begin
    if(!resetn) begin
      tickgen_counter <= 16'h0;
      sio_reg_OverRun <= 1'b0;
    end else begin
      if(when_UART_l114) begin
        tickgen_counter <= sio_reg_ClkDiv;
      end else begin
        tickgen_counter <= (tickgen_counter - 16'h0001);
      end
      if(when_UART_l131) begin
        sio_reg_OverRun <= 1'b1;
      end
      if(sio_reg_ROverRun) begin
        sio_reg_OverRun <= 1'b0;
      end
    end
  end


endmodule
module UART (
  input               sio_txdata_valid,
  output              sio_txdata_ready,
  input      [7:0]    sio_txdata_payload,
  output              sio_rxdata_valid,
  input               sio_rxdata_ready,
  output     [7:0]    sio_rxdata_payload,
  input      [15:0]   sio_reg_ClkDiv,
  input               sio_reg_ROverRun,
  output reg          sio_reg_OverRun,
  input      [3:0]    sio_reg_TXThreshold,
  input      [3:0]    sio_reg_RXThreshold,
  output              sio_reg_TXBusy,
  output              sio_reg_RXBusy,
  output     [3:0]    sio_reg_TXCnt,
  output     [3:0]    sio_reg_RXCnt,
  output              eio_txd,
  input               eio_rxd,
  output              int_TXFIFOEmpty,
  output              int_RXFIFOFull,
  input               clk,
  input               resetn
);

  reg                 rx_io_data_ready;
  wire                tx_io_data_ready;
  wire                tx_io_txd;
  wire                tx_io_busy;
  wire                rx_io_data_valid;
  wire       [7:0]    rx_io_data_payload;
  wire                rx_io_busy;
  wire                RXStream_io_push_ready;
  wire                RXStream_io_pop_valid;
  wire       [7:0]    RXStream_io_pop_payload;
  wire       [2:0]    RXStream_io_occupancy;
  wire       [2:0]    RXStream_io_availability;
  wire                TXStream_io_push_ready;
  wire                TXStream_io_pop_valid;
  wire       [7:0]    TXStream_io_pop_payload;
  wire       [2:0]    TXStream_io_occupancy;
  wire       [2:0]    TXStream_io_availability;
  reg        [15:0]   tickgen_counter;
  wire                tickgen_tick;
  wire                when_UART_l114;
  wire                when_Stream_l408;
  reg                 tr_valid;
  wire                tr_ready;
  wire       [7:0]    tr_payload;
  wire                when_UART_l131;

  UART_TX tx (
    .io_tick            (tickgen_tick             ),
    .io_data_valid      (TXStream_io_pop_valid    ),
    .io_data_ready      (tx_io_data_ready         ),
    .io_data_payload    (TXStream_io_pop_payload  ),
    .io_txd             (tx_io_txd                ),
    .io_busy            (tx_io_busy               ),
    .clk                (clk                      ),
    .resetn             (resetn                   )
  );
  UART_RX rx (
    .io_tick            (tickgen_tick        ),
    .io_data_valid      (rx_io_data_valid    ),
    .io_data_ready      (rx_io_data_ready    ),
    .io_data_payload    (rx_io_data_payload  ),
    .io_rxd             (eio_rxd             ),
    .io_busy            (rx_io_busy          ),
    .clk                (clk                 ),
    .resetn             (resetn              )
  );
  StreamFifo RXStream (
    .io_push_valid      (tr_valid                  ),
    .io_push_ready      (RXStream_io_push_ready    ),
    .io_push_payload    (tr_payload                ),
    .io_pop_valid       (RXStream_io_pop_valid     ),
    .io_pop_ready       (sio_rxdata_ready          ),
    .io_pop_payload     (RXStream_io_pop_payload   ),
    .io_flush           (1'b0                      ),
    .io_occupancy       (RXStream_io_occupancy     ),
    .io_availability    (RXStream_io_availability  ),
    .clk                (clk                       ),
    .resetn             (resetn                    )
  );
  StreamFifo TXStream (
    .io_push_valid      (sio_txdata_valid          ),
    .io_push_ready      (TXStream_io_push_ready    ),
    .io_push_payload    (sio_txdata_payload        ),
    .io_pop_valid       (TXStream_io_pop_valid     ),
    .io_pop_ready       (tx_io_data_ready          ),
    .io_pop_payload     (TXStream_io_pop_payload   ),
    .io_flush           (1'b0                      ),
    .io_occupancy       (TXStream_io_occupancy     ),
    .io_availability    (TXStream_io_availability  ),
    .clk                (clk                       ),
    .resetn             (resetn                    )
  );
  assign sio_reg_TXCnt = {1'd0, TXStream_io_occupancy};
  assign sio_reg_RXCnt = {1'd0, RXStream_io_occupancy};
  assign sio_reg_TXBusy = tx_io_busy;
  assign sio_reg_RXBusy = rx_io_busy;
  assign sio_txdata_ready = TXStream_io_push_ready;
  assign sio_rxdata_valid = RXStream_io_pop_valid;
  assign sio_rxdata_payload = RXStream_io_pop_payload;
  assign int_RXFIFOFull = (sio_reg_RXThreshold < sio_reg_RXCnt);
  assign int_TXFIFOEmpty = (sio_reg_TXCnt < sio_reg_TXThreshold);
  assign tickgen_tick = (tickgen_counter == 16'h0);
  assign when_UART_l114 = ((tickgen_counter == 16'h0) || (sio_reg_ClkDiv < tickgen_counter));
  assign eio_txd = tx_io_txd;
  assign when_Stream_l408 = (RXStream_io_occupancy == 3'b011);
  always @(*) begin
    tr_valid = rx_io_data_valid;
    if(when_Stream_l408) begin
      tr_valid = 1'b0;
    end
  end

  always @(*) begin
    rx_io_data_ready = tr_ready;
    if(when_Stream_l408) begin
      rx_io_data_ready = 1'b1;
    end
  end

  assign tr_payload = rx_io_data_payload;
  assign tr_ready = RXStream_io_push_ready;
  assign when_UART_l131 = (rx_io_data_valid && (RXStream_io_occupancy == 3'b011));
  always @(posedge clk or negedge resetn) begin
    if(!resetn) begin
      tickgen_counter <= 16'h0;
      sio_reg_OverRun <= 1'b0;
    end else begin
      if(when_UART_l114) begin
        tickgen_counter <= sio_reg_ClkDiv;
      end else begin
        tickgen_counter <= (tickgen_counter - 16'h0001);
      end
      if(when_UART_l131) begin
        sio_reg_OverRun <= 1'b1;
      end
      if(sio_reg_ROverRun) begin
        sio_reg_OverRun <= 1'b0;
      end
    end
  end


endmodule