data/full_repos/permissive/503578084/single_cycle/cu.v
1: b'%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:21: Cannot find include file: param.v\n`include "param.v" \n         ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/503578084/single_cycle,data/full_repos/permissive/503578084/param.v\n             data/full_repos/permissive/503578084/single_cycle,data/full_repos/permissive/503578084/param.v.v\n             data/full_repos/permissive/503578084/single_cycle,data/full_repos/permissive/503578084/param.v.sv\n             param.v\n             param.v.v\n             param.v.sv\n             obj_dir/param.v\n             obj_dir/param.v.v\n             obj_dir/param.v.sv\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:43: Define or directive not defined: \'`OPCODE_B\'\n    else if(inst[6:0]==`OPCODE_B) npc_op=npc_op2;\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:43: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    else if(inst[6:0]==`OPCODE_B) npc_op=npc_op2;\n                                ^\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:49: Define or directive not defined: \'`OPCODE_B\'\n    else if(inst[6:0]==`OPCODE_B) begin\n                       ^~~~~~~~~\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:49: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    else if(inst[6:0]==`OPCODE_B) begin\n                                ^\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:52: Define or directive not defined: \'`EQ\'\n                if(branch==`EQ) npc_op2=\'b1;\n                           ^~~\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:56: Define or directive not defined: \'`EQ\'\n                if(branch!=`EQ) npc_op2=\'b1;\n                           ^~~\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:60: Define or directive not defined: \'`LT\'\n                if(branch==`LT) npc_op2=\'b1;\n                           ^~~\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:64: Define or directive not defined: \'`GT\'\n                if(branch==`GT || branch==`EQ) npc_op2=\'b1;\n                           ^~~\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:64: Define or directive not defined: \'`EQ\'\n                if(branch==`GT || branch==`EQ) npc_op2=\'b1;\n                                          ^~~\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:76: Define or directive not defined: \'`PC_PLUS_4\'\n        npc_op1=`PC_PLUS_4;\n                ^~~~~~~~~~\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:81: Define or directive not defined: \'`OPCODE_R\'\n        `OPCODE_R:begin\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:83: Define or directive not defined: \'`PC_PLUS_4\'\n            npc_op1=`PC_PLUS_4;\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:85: Define or directive not defined: \'`RF_ALU_C\'\n            wd_sel=`RF_ALU_C;\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:91: syntax error, unexpected \'=\', expecting IDENTIFIER\n                    if(inst[30]==\'b0) alu_op=`ADD;\n                                            ^\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:91: Define or directive not defined: \'`ADD\'\n                    if(inst[30]==\'b0) alu_op=`ADD;\n                                             ^~~~\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:92: syntax error, unexpected \'=\', expecting IDENTIFIER\n                    else alu_op=`SUB;\n                               ^\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:92: Define or directive not defined: \'`SUB\'\n                    else alu_op=`SUB;\n                                ^~~~\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:95: syntax error, unexpected \'=\', expecting IDENTIFIER\n                    alu_op=`AND;\n                          ^\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:95: Define or directive not defined: \'`AND\'\n                    alu_op=`AND;\n                           ^~~~\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:98: syntax error, unexpected \'=\', expecting IDENTIFIER\n                    alu_op=`OR;\n                          ^\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:98: Define or directive not defined: \'`OR\'\n                    alu_op=`OR;\n                           ^~~\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:101: syntax error, unexpected \'=\', expecting IDENTIFIER\n                    alu_op=`XOR;\n                          ^\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:101: Define or directive not defined: \'`XOR\'\n                    alu_op=`XOR;\n                           ^~~~\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:104: syntax error, unexpected \'=\', expecting IDENTIFIER\n                    alu_op=`SLL;\n                          ^\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:104: Define or directive not defined: \'`SLL\'\n                    alu_op=`SLL;\n                           ^~~~\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:107: syntax error, unexpected \'=\', expecting IDENTIFIER\n                    if(inst[30]==\'b0) alu_op=`SRL;\n                                            ^\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:107: Define or directive not defined: \'`SRL\'\n                    if(inst[30]==\'b0) alu_op=`SRL;\n                                             ^~~~\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:108: syntax error, unexpected \'=\', expecting IDENTIFIER\n                    else alu_op=`SRA;\n                               ^\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:108: Define or directive not defined: \'`SRA\'\n                    else alu_op=`SRA;\n                                ^~~~\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:112: syntax error, unexpected end\n        end\n        ^~~\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:113: Define or directive not defined: \'`OPCODE_I\'\n        `OPCODE_I:begin\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:115: Define or directive not defined: \'`RF_ALU_C\'\n            wd_sel=`RF_ALU_C;\n                   ^~~~~~~~~\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:116: Define or directive not defined: \'`PC_PLUS_4\'\n            npc_op1=`PC_PLUS_4;\n                    ^~~~~~~~~~\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:121: Define or directive not defined: \'`I\'\n            sext_op=`I;\n                    ^~\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:124: syntax error, unexpected \'=\', expecting IDENTIFIER\n                    alu_op=`ADD;\n                          ^\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:124: Define or directive not defined: \'`ADD\'\n                    alu_op=`ADD;\n                           ^~~~\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:127: syntax error, unexpected \'=\', expecting IDENTIFIER\n                    alu_op=`AND;\n                          ^\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:127: Define or directive not defined: \'`AND\'\n                    alu_op=`AND;\n                           ^~~~\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:130: syntax error, unexpected \'=\', expecting IDENTIFIER\n                    alu_op=`OR;\n                          ^\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:130: Define or directive not defined: \'`OR\'\n                    alu_op=`OR;\n                           ^~~\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:133: syntax error, unexpected \'=\', expecting IDENTIFIER\n                    alu_op=`XOR;\n                          ^\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:133: Define or directive not defined: \'`XOR\'\n                    alu_op=`XOR;\n                           ^~~~\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:136: syntax error, unexpected \'=\', expecting IDENTIFIER\n                    alu_op=`SLL;\n                          ^\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:136: Define or directive not defined: \'`SLL\'\n                    alu_op=`SLL;\n                           ^~~~\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:139: syntax error, unexpected \'=\', expecting IDENTIFIER\n                    if(inst[30]==\'b0) alu_op=`SRL;\n                                            ^\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:139: Define or directive not defined: \'`SRL\'\n                    if(inst[30]==\'b0) alu_op=`SRL;\n                                             ^~~~\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:140: syntax error, unexpected \'=\', expecting IDENTIFIER\n                    else alu_op=`SRA;\n                               ^\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:140: Define or directive not defined: \'`SRA\'\n                    else alu_op=`SRA;\n                                ^~~~\n%Error: data/full_repos/permissive/503578084/single_cycle/cu.v:143: syntax error, unexpected \'=\', expecting IDENTIFIER\n                    alu_op=`ADD;\n                          ^\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module cu(
    input   rst_n,
    input   [31:0]  inst,
    input   [1:0]   branch,
    output  reg pc_sel,
    output  reg npc_op,
    output  reg rf_we,
    output  reg [1:0]   wd_sel,
    output  reg [2:0]   sext_op,
    output  reg [3:0]   alu_op,
    output  reg alub_sel,
    output  reg dram_we
    );
    
reg need_branch;
reg npc_op1;
reg npc_op2;

always @ (npc_op1 or npc_op2 or rst_n) begin
    if(rst_n=='b0) npc_op='b0;
    else if(inst[6:0]==`OPCODE_B) npc_op=npc_op2;
    else npc_op=npc_op1;
end

always @ (branch or rst_n) begin
    if(rst_n=='b0) npc_op2='b0;
    else if(inst[6:0]==`OPCODE_B) begin
        case(inst[14:12])
            'b000:begin
                if(branch==`EQ) npc_op2='b1;
                else npc_op2='b0;
            end
            'b001:begin
                if(branch!=`EQ) npc_op2='b1;
                else npc_op2='b0;
            end
            'b100:begin
                if(branch==`LT) npc_op2='b1;
                else npc_op2='b0;
            end
            'b101:begin
                if(branch==`GT || branch==`EQ) npc_op2='b1;
                else npc_op2='b0;
            end
            default:npc_op2='b0;
        endcase
    end
    else npc_op2='b0;
end

always @ (*) begin
    if(rst_n=='b0) begin
        pc_sel='b0;
        npc_op1=`PC_PLUS_4;
        need_branch=1'b0;
    end
    else
    case(inst[6:0])
        `OPCODE_R:begin
            pc_sel='b0;
            npc_op1=`PC_PLUS_4;
            rf_we='b1;
            wd_sel=`RF_ALU_C;
            alub_sel='b0;
            need_branch='b0;
            dram_we='b0;
            case(inst[14:12])
                'b000:begin
                    if(inst[30]=='b0) alu_op=`ADD;
                    else alu_op=`SUB;
                end
                'b111:begin
                    alu_op=`AND;
                end
                'b110:begin
                    alu_op=`OR;
                end
                'b100:begin
                    alu_op=`XOR;
                end
                'b001:begin
                    alu_op=`SLL;
                end
                'b101:begin
                    if(inst[30]=='b0) alu_op=`SRL;
                    else alu_op=`SRA;
                end
                default:;
            endcase
        end
        `OPCODE_I:begin
            pc_sel='b0;
            wd_sel=`RF_ALU_C;
            npc_op1=`PC_PLUS_4;
            rf_we='b1;
            alub_sel='b1;
            need_branch='b0;
            dram_we='b0;
            sext_op=`I;
            case(inst[14:12])
                'b000:begin
                    alu_op=`ADD;
                end
                'b111:begin
                    alu_op=`AND;
                end
                'b110:begin
                    alu_op=`OR;
                end
                'b100:begin
                    alu_op=`XOR;
                end
                'b001:begin
                    alu_op=`SLL;
                end
                'b101:begin
                    if(inst[30]=='b0) alu_op=`SRL;
                    else alu_op=`SRA;
                end
                'b010:begin
                    alu_op=`ADD;
                end
                default:;
            endcase
        end
        `OPCODE_LW:begin
            pc_sel='b0;
            wd_sel=`RF_DRAM_RD;
            npc_op1=`PC_PLUS_4;
            rf_we='b1;
            alub_sel='b1;
            need_branch='b0;
            dram_we='b0;
            sext_op=`I;
            alu_op=`ADD;
        end
        `OPCODE_JALR:begin
            pc_sel='b1;
            wd_sel=`RF_NPC_PC4;
            npc_op1=`PC_PLUS_4;
            rf_we='b1;
            alub_sel='b1;
            need_branch='b0;
            dram_we='b0;
            sext_op=`I;
            alu_op=`ADD;
        end
        `OPCODE_S:begin
            pc_sel='b0;
            npc_op1=`PC_PLUS_4;
            rf_we='b0;
            alub_sel='b1;
            need_branch='b0;
            dram_we='b1;
            sext_op=`S;
            alu_op=`ADD;
        end
        `OPCODE_B:begin
            pc_sel='b0;
            npc_op1='b1;
            rf_we='b0;
            alub_sel='b0;
            need_branch='b1;
            dram_we='b0;
            sext_op=`B;
            alu_op=`SUB;
        end
        `OPCODE_U:begin
            pc_sel='b0;
            npc_op1=`PC_PLUS_4;
            rf_we='b1;
            wd_sel=`RF_ALU_C;
            alub_sel='b1;
            need_branch='b0;
            dram_we='b0;
            sext_op=`U;
            alu_op=`SEL_B;
        end
        `OPCODE_J:begin
            pc_sel='b0;
            npc_op1='b1;
            rf_we='b1;
            wd_sel=`RF_NPC_PC4;
            need_branch='b0;
            dram_we='b0;
            sext_op=`J;
        end
        default:begin
            rf_we='b0;
            dram_we='b0;
            pc_sel='b0;
            npc_op1=`PC_PLUS_4;
        end
    endcase
end
    
endmodule
module cu(
    input   rst_n,
    input   [31:0]  inst,
    input   [1:0]   branch,
    output  reg pc_sel,
    output  reg npc_op,
    output  reg rf_we,
    output  reg [1:0]   wd_sel,
    output  reg [2:0]   sext_op,
    output  reg [3:0]   alu_op,
    output  reg alub_sel,
    output  reg dram_we
    );

    
reg need_branch;
reg npc_op1;
reg npc_op2;

always @ (npc_op1 or npc_op2 or rst_n) begin
    if(rst_n=='b0) npc_op='b0;
    else if(inst[6:0]==`OPCODE_B) npc_op=npc_op2;
    else npc_op=npc_op1;
end

always @ (branch or rst_n) begin
    if(rst_n=='b0) npc_op2='b0;
    else if(inst[6:0]==`OPCODE_B) begin
        case(inst[14:12])
            'b000:begin
                if(branch==`EQ) npc_op2='b1;
                else npc_op2='b0;
            end
            'b001:begin
                if(branch!=`EQ) npc_op2='b1;
                else npc_op2='b0;
            end
            'b100:begin
                if(branch==`LT) npc_op2='b1;
                else npc_op2='b0;
            end
            'b101:begin
                if(branch==`GT || branch==`EQ) npc_op2='b1;
                else npc_op2='b0;
            end
            default:npc_op2='b0;
        endcase
    end
    else npc_op2='b0;
end

always @ (*) begin
    if(rst_n=='b0) begin
        pc_sel='b0;
        npc_op1=`PC_PLUS_4;
        need_branch=1'b0;
    end
    else
    case(inst[6:0])
        `OPCODE_R:begin
            pc_sel='b0;
            npc_op1=`PC_PLUS_4;
            rf_we='b1;
            wd_sel=`RF_ALU_C;
            alub_sel='b0;
            need_branch='b0;
            dram_we='b0;
            case(inst[14:12])
                'b000:begin
                    if(inst[30]=='b0) alu_op=`ADD;
                    else alu_op=`SUB;
                end
                'b111:begin
                    alu_op=`AND;
                end
                'b110:begin
                    alu_op=`OR;
                end
                'b100:begin
                    alu_op=`XOR;
                end
                'b001:begin
                    alu_op=`SLL;
                end
                'b101:begin
                    if(inst[30]=='b0) alu_op=`SRL;
                    else alu_op=`SRA;
                end
                default:;
            endcase
        end
        `OPCODE_I:begin
            pc_sel='b0;
            wd_sel=`RF_ALU_C;
            npc_op1=`PC_PLUS_4;
            rf_we='b1;
            alub_sel='b1;
            need_branch='b0;
            dram_we='b0;
            sext_op=`I;
            case(inst[14:12])
                'b000:begin
                    alu_op=`ADD;
                end
                'b111:begin
                    alu_op=`AND;
                end
                'b110:begin
                    alu_op=`OR;
                end
                'b100:begin
                    alu_op=`XOR;
                end
                'b001:begin
                    alu_op=`SLL;
                end
                'b101:begin
                    if(inst[30]=='b0) alu_op=`SRL;
                    else alu_op=`SRA;
                end
                'b010:begin
                    alu_op=`ADD;
                end
                default:;
            endcase
        end
        `OPCODE_LW:begin
            pc_sel='b0;
            wd_sel=`RF_DRAM_RD;
            npc_op1=`PC_PLUS_4;
            rf_we='b1;
            alub_sel='b1;
            need_branch='b0;
            dram_we='b0;
            sext_op=`I;
            alu_op=`ADD;
        end
        `OPCODE_JALR:begin
            pc_sel='b1;
            wd_sel=`RF_NPC_PC4;
            npc_op1=`PC_PLUS_4;
            rf_we='b1;
            alub_sel='b1;
            need_branch='b0;
            dram_we='b0;
            sext_op=`I;
            alu_op=`ADD;
        end
        `OPCODE_S:begin
            pc_sel='b0;
            npc_op1=`PC_PLUS_4;
            rf_we='b0;
            alub_sel='b1;
            need_branch='b0;
            dram_we='b1;
            sext_op=`S;
            alu_op=`ADD;
        end
        `OPCODE_B:begin
            pc_sel='b0;
            npc_op1='b1;
            rf_we='b0;
            alub_sel='b0;
            need_branch='b1;
            dram_we='b0;
            sext_op=`B;
            alu_op=`SUB;
        end
        `OPCODE_U:begin
            pc_sel='b0;
            npc_op1=`PC_PLUS_4;
            rf_we='b1;
            wd_sel=`RF_ALU_C;
            alub_sel='b1;
            need_branch='b0;
            dram_we='b0;
            sext_op=`U;
            alu_op=`SEL_B;
        end
        `OPCODE_J:begin
            pc_sel='b0;
            npc_op1='b1;
            rf_we='b1;
            wd_sel=`RF_NPC_PC4;
            need_branch='b0;
            dram_we='b0;
            sext_op=`J;
        end
        default:begin
            rf_we='b0;
            dram_we='b0;
            pc_sel='b0;
            npc_op1=`PC_PLUS_4;
        end
    endcase
end
    
endmodule