data/full_repos/permissive/456436315/src/cpu/board/rev1_tangnano4k/src/uart.sv
1: b"%Error: data/full_repos/permissive/456436315/src/cpu/board/rev1_tangnano4k/src/uart.sv:56: Cannot find file containing module: 'UART_MASTER_Top'\nUART_MASTER_Top uart_master(\n^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/456436315/src/cpu/board/rev1_tangnano4k/src,data/full_repos/permissive/456436315/UART_MASTER_Top\n             data/full_repos/permissive/456436315/src/cpu/board/rev1_tangnano4k/src,data/full_repos/permissive/456436315/UART_MASTER_Top.v\n             data/full_repos/permissive/456436315/src/cpu/board/rev1_tangnano4k/src,data/full_repos/permissive/456436315/UART_MASTER_Top.sv\n             UART_MASTER_Top\n             UART_MASTER_Top.v\n             UART_MASTER_Top.sv\n             obj_dir/UART_MASTER_Top\n             obj_dir/UART_MASTER_Top.v\n             obj_dir/UART_MASTER_Top.sv\n%Error: Exiting due to 1 error(s)\n"
module uart(
  input sys_clk,
  input rst_n,
  input uart_rx,
  output uart_tx,
  output logic [7:0] rx_data,
  output logic rx_data_wr,
  input [7:0] tx_data,
  input tx_en
);


localparam REG_RBR = 3'd0;
localparam REG_LSR = 3'd5;


logic [7:0] rdata, wdata;
logic [2:0] raddr;
logic rx_en, rx_rdy, rx_v;


assign raddr = rx_rdy ? REG_RBR : REG_LSR;
assign rx_rdy = ~rx_v & rdata[0];
assign wdata = tx_data;

always @(posedge sys_clk, negedge rst_n) begin
  if (!rst_n)
    rx_en <= 1'd0;
  else
    rx_en <= ~rx_en;
end

always @(posedge sys_clk, negedge rst_n) begin
  if (!rst_n)
    rx_v <= 1'd0;
  else if (~rx_en)
    rx_v <= rx_rdy;
end

always @(posedge sys_clk, negedge rst_n) begin
  if (!rst_n)
    rx_data <= 8'd0;
  else if (rx_v & rx_en)
    rx_data <= rdata;
end

always @(posedge sys_clk, negedge rst_n) begin
  if (!rst_n)
    rx_data_wr <= 1'd0;
  else if (rx_v & rx_en)
    rx_data_wr <= 1'd1;
  else
    rx_data_wr <= 1'd0;
end

UART_MASTER_Top uart_master(
  .I_CLK(sys_clk),
  .I_RESETN(rst_n),
  .I_TX_EN(tx_en),
  .I_WADDR(3'd0),
  .I_WDATA(wdata),
  .I_RX_EN(rx_en),
  .I_RADDR(raddr),
  .O_RDATA(rdata),
  .SIN(uart_rx),
  .RxRDYn(),
  .SOUT(uart_tx),
  .TxRDYn(),
  .DDIS(),
  .INTR(),
  .DCDn(1'b1),
  .CTSn(1'b1),
  .DSRn(1'b1),
  .RIn(1'b1),
  .DTRn(),
  .RTSn()
);

endmodule
module uart(
  input sys_clk,
  input rst_n,
  input uart_rx,
  output uart_tx,
  output logic [7:0] rx_data,
  output logic rx_data_wr,
  input [7:0] tx_data,
  input tx_en
);



localparam REG_RBR = 3'd0;
localparam REG_LSR = 3'd5;


logic [7:0] rdata, wdata;
logic [2:0] raddr;
logic rx_en, rx_rdy, rx_v;


assign raddr = rx_rdy ? REG_RBR : REG_LSR;
assign rx_rdy = ~rx_v & rdata[0];
assign wdata = tx_data;

always @(posedge sys_clk, negedge rst_n) begin
  if (!rst_n)
    rx_en <= 1'd0;
  else
    rx_en <= ~rx_en;
end

always @(posedge sys_clk, negedge rst_n) begin
  if (!rst_n)
    rx_v <= 1'd0;
  else if (~rx_en)
    rx_v <= rx_rdy;
end

always @(posedge sys_clk, negedge rst_n) begin
  if (!rst_n)
    rx_data <= 8'd0;
  else if (rx_v & rx_en)
    rx_data <= rdata;
end

always @(posedge sys_clk, negedge rst_n) begin
  if (!rst_n)
    rx_data_wr <= 1'd0;
  else if (rx_v & rx_en)
    rx_data_wr <= 1'd1;
  else
    rx_data_wr <= 1'd0;
end

UART_MASTER_Top uart_master(
  .I_CLK(sys_clk),
  .I_RESETN(rst_n),
  .I_TX_EN(tx_en),
  .I_WADDR(3'd0),
  .I_WDATA(wdata),
  .I_RX_EN(rx_en),
  .I_RADDR(raddr),
  .O_RDATA(rdata),
  .SIN(uart_rx),
  .RxRDYn(),
  .SOUT(uart_tx),
  .TxRDYn(),
  .DDIS(),
  .INTR(),
  .DCDn(1'b1),
  .CTSn(1'b1),
  .DSRn(1'b1),
  .RIn(1'b1),
  .DTRn(),
  .RTSn()
);

endmodule