data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v
1: b"%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:540: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\breaker.loop_breaker  (\n  ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block,data/full_repos/permissive/496906136/fpga_tech_buffer\n             data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block,data/full_repos/permissive/496906136/fpga_tech_buffer.v\n             data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block,data/full_repos/permissive/496906136/fpga_tech_buffer.sv\n             fpga_tech_buffer\n             fpga_tech_buffer.v\n             fpga_tech_buffer.sv\n             obj_dir/fpga_tech_buffer\n             obj_dir/fpga_tech_buffer.v\n             obj_dir/fpga_tech_buffer.sv\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:544: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\breaker.lut_tfinish  (\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:548: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\breaker.lut_tstart  (\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:347: Cannot find file containing module: 'fpga_tech_register'\n  fpga_tech_register cell_reg (\n  ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:355: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\in_bufs:1.cell_tstart  (\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:359: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\in_bufs:2.cell_tstart  (\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:363: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\in_bufs:3.cell_tstart  (\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/496906136/verilog/rtl/fpga_struct_block/fpga_struct_block_fromvhdl.v:367: Cannot find file containing module: 'fpga_tech_buffer'\n  fpga_tech_buffer \\in_bufs:4.cell_tstart  (\n  ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n"
module fpga_struct_block(clk_i, glb_rstn_i, config_clk_i, config_ena_i, config_shift_i, inputs_up_i, inputs_right_i, inputs_down_i, inputs_left_i, config_shift_o, outputs_o);
  wire _00_;
  wire _01_;
  wire _02_;
  wire _03_;
  wire _04_;
  wire _05_;
  wire _06_;
  wire _07_;
  wire _08_;
  wire _09_;
  wire _10_;
  wire _11_;
  wire _12_;
  wire _13_;
  wire _14_;
  wire _15_;
  wire _16_;
  wire _17_;
  wire _18_;
  wire _19_;
  wire _20_;
  wire _21_;
  wire _22_;
  wire _23_;
  wire _24_;
  wire _25_;
  wire _26_;
  wire _27_;
  wire _28_;
  wire _29_;
  wire _30_;
  wire _31_;
  wire _32_;
  wire _33_;
  wire _34_;
  wire _35_;
  wire _36_;
  wire _37_;
  wire _38_;
  wire _39_;
  wire _40_;
  wire _41_;
  wire _42_;
  wire _43_;
  wire _44_;
  wire _45_;
  wire _46_;
  wire _47_;
  wire _48_;
  wire _49_;
  wire _50_;
  wire _51_;
  wire _52_;
  wire _53_;
  wire _54_;
  wire _55_;
  wire _56_;
  wire _57_;
  wire _58_;
  wire _59_;
  wire _60_;
  wire _61_;
  wire [7:0] _62_;
  wire _63_;
  wire _64_;
  wire _65_;
  wire [31:0] block_in;
  wire [33:0] cfg_shift_chain;
  input clk_i;
  input config_clk_i;
  input config_ena_i;
  input config_shift_i;
  output config_shift_o;
  input glb_rstn_i;
  input [31:0] inputs_down_i;
  input [31:0] inputs_left_i;
  input [31:0] inputs_right_i;
  input [31:0] inputs_up_i;
  wire \logic.logic_block:587 ;
  wire [7:0] \logic.logic_block:588 ;
  output [7:0] outputs_o;
  fpga_logic_block \logic.logic_block  (
    .clk_i(clk_i),
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[0]),
    .config_shift_o(_61_),
    .glb_rstn_i(glb_rstn_i),
    .inputs_i(block_in),
    .outputs_o(_62_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_down:1.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[30]),
    .config_shift_o(_26_),
    .route_i({ inputs_down_i[24], inputs_down_i[16], inputs_down_i[8], inputs_down_i[0] }),
    .route_o(_27_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_down:2.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[26]),
    .config_shift_o(_28_),
    .route_i({ inputs_down_i[25], inputs_down_i[17], inputs_down_i[9], inputs_down_i[1] }),
    .route_o(_29_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_down:3.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[22]),
    .config_shift_o(_30_),
    .route_i({ inputs_down_i[26], inputs_down_i[18], inputs_down_i[10], inputs_down_i[2] }),
    .route_o(_31_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_down:4.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[18]),
    .config_shift_o(_32_),
    .route_i({ inputs_down_i[27], inputs_down_i[19], inputs_down_i[11], inputs_down_i[3] }),
    .route_o(_34_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_down:5.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[14]),
    .config_shift_o(_35_),
    .route_i({ inputs_down_i[28], inputs_down_i[20], inputs_down_i[12], inputs_down_i[4] }),
    .route_o(_36_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_down:6.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[10]),
    .config_shift_o(_37_),
    .route_i({ inputs_down_i[29], inputs_down_i[21], inputs_down_i[13], inputs_down_i[5] }),
    .route_o(_38_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_down:7.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[6]),
    .config_shift_o(_39_),
    .route_i({ inputs_down_i[30], inputs_down_i[22], inputs_down_i[14], inputs_down_i[6] }),
    .route_o(_40_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_down:8.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[2]),
    .config_shift_o(_41_),
    .route_i({ inputs_down_i[31], inputs_down_i[23], inputs_down_i[15], inputs_down_i[7] }),
    .route_o(_42_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_left:1.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[29]),
    .config_shift_o(_43_),
    .route_i({ inputs_left_i[24], inputs_left_i[16], inputs_left_i[8], inputs_left_i[0] }),
    .route_o(_45_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_left:2.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[25]),
    .config_shift_o(_46_),
    .route_i({ inputs_left_i[25], inputs_left_i[17], inputs_left_i[9], inputs_left_i[1] }),
    .route_o(_47_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_left:3.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[21]),
    .config_shift_o(_48_),
    .route_i({ inputs_left_i[26], inputs_left_i[18], inputs_left_i[10], inputs_left_i[2] }),
    .route_o(_49_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_left:4.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[17]),
    .config_shift_o(_50_),
    .route_i({ inputs_left_i[27], inputs_left_i[19], inputs_left_i[11], inputs_left_i[3] }),
    .route_o(_51_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_left:5.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[13]),
    .config_shift_o(_52_),
    .route_i({ inputs_left_i[28], inputs_left_i[20], inputs_left_i[12], inputs_left_i[4] }),
    .route_o(_53_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_left:6.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[9]),
    .config_shift_o(_54_),
    .route_i({ inputs_left_i[29], inputs_left_i[21], inputs_left_i[13], inputs_left_i[5] }),
    .route_o(_56_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_left:7.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[5]),
    .config_shift_o(_57_),
    .route_i({ inputs_left_i[30], inputs_left_i[22], inputs_left_i[14], inputs_left_i[6] }),
    .route_o(_58_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_left:8.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[1]),
    .config_shift_o(_59_),
    .route_i({ inputs_left_i[31], inputs_left_i[23], inputs_left_i[15], inputs_left_i[7] }),
    .route_o(_60_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_right:1.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[31]),
    .config_shift_o(_08_),
    .route_i({ inputs_right_i[24], inputs_right_i[16], inputs_right_i[8], inputs_right_i[0] }),
    .route_o(_09_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_right:2.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[27]),
    .config_shift_o(_10_),
    .route_i({ inputs_right_i[25], inputs_right_i[17], inputs_right_i[9], inputs_right_i[1] }),
    .route_o(_12_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_right:3.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[23]),
    .config_shift_o(_13_),
    .route_i({ inputs_right_i[26], inputs_right_i[18], inputs_right_i[10], inputs_right_i[2] }),
    .route_o(_14_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_right:4.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[19]),
    .config_shift_o(_15_),
    .route_i({ inputs_right_i[27], inputs_right_i[19], inputs_right_i[11], inputs_right_i[3] }),
    .route_o(_16_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_right:5.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[15]),
    .config_shift_o(_17_),
    .route_i({ inputs_right_i[28], inputs_right_i[20], inputs_right_i[12], inputs_right_i[4] }),
    .route_o(_18_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_right:6.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[11]),
    .config_shift_o(_19_),
    .route_i({ inputs_right_i[29], inputs_right_i[21], inputs_right_i[13], inputs_right_i[5] }),
    .route_o(_20_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_right:7.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[7]),
    .config_shift_o(_21_),
    .route_i({ inputs_right_i[30], inputs_right_i[22], inputs_right_i[14], inputs_right_i[6] }),
    .route_o(_23_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_right:8.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[3]),
    .config_shift_o(_24_),
    .route_i({ inputs_right_i[31], inputs_right_i[23], inputs_right_i[15], inputs_right_i[7] }),
    .route_o(_25_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_up:1.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[32]),
    .config_shift_o(_00_),
    .route_i({ inputs_up_i[24], inputs_up_i[16], inputs_up_i[8], inputs_up_i[0] }),
    .route_o(_11_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_up:2.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[28]),
    .config_shift_o(_22_),
    .route_i({ inputs_up_i[25], inputs_up_i[17], inputs_up_i[9], inputs_up_i[1] }),
    .route_o(_33_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_up:3.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[24]),
    .config_shift_o(_44_),
    .route_i({ inputs_up_i[26], inputs_up_i[18], inputs_up_i[10], inputs_up_i[2] }),
    .route_o(_55_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_up:4.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[20]),
    .config_shift_o(_63_),
    .route_i({ inputs_up_i[27], inputs_up_i[19], inputs_up_i[11], inputs_up_i[3] }),
    .route_o(_64_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_up:5.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[16]),
    .config_shift_o(_65_),
    .route_i({ inputs_up_i[28], inputs_up_i[20], inputs_up_i[12], inputs_up_i[4] }),
    .route_o(_01_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_up:6.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[12]),
    .config_shift_o(_02_),
    .route_i({ inputs_up_i[29], inputs_up_i[21], inputs_up_i[13], inputs_up_i[5] }),
    .route_o(_03_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_up:7.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[8]),
    .config_shift_o(_04_),
    .route_i({ inputs_up_i[30], inputs_up_i[22], inputs_up_i[14], inputs_up_i[6] }),
    .route_o(_05_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_up:8.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[4]),
    .config_shift_o(_06_),
    .route_i({ inputs_up_i[31], inputs_up_i[23], inputs_up_i[15], inputs_up_i[7] }),
    .route_o(_07_)
  );
  assign cfg_shift_chain = { _00_, _08_, _26_, _43_, _22_, _10_, _28_, _46_, _44_, _13_, _30_, _48_, _63_, _15_, _32_, _50_, _65_, _17_, _35_, _52_, _02_, _19_, _37_, _54_, _04_, _21_, _39_, _57_, _06_, _24_, _41_, _59_, \logic.logic_block:587 , config_shift_i };
  assign block_in = { _60_, _42_, _25_, _07_, _58_, _40_, _23_, _05_, _56_, _38_, _20_, _03_, _53_, _36_, _18_, _01_, _51_, _34_, _16_, _64_, _49_, _31_, _14_, _55_, _47_, _29_, _12_, _33_, _45_, _27_, _09_, _11_ };
  assign \logic.logic_block:587  = _61_;
  assign \logic.logic_block:588  = _62_;
  assign config_shift_o = cfg_shift_chain[33];
  assign outputs_o = \logic.logic_block:588 ;
endmodule
module fpga_struct_block(clk_i, glb_rstn_i, config_clk_i, config_ena_i, config_shift_i, inputs_up_i, inputs_right_i, inputs_down_i, inputs_left_i, config_shift_o, outputs_o);

  wire _00_;
  wire _01_;
  wire _02_;
  wire _03_;
  wire _04_;
  wire _05_;
  wire _06_;
  wire _07_;
  wire _08_;
  wire _09_;
  wire _10_;
  wire _11_;
  wire _12_;
  wire _13_;
  wire _14_;
  wire _15_;
  wire _16_;
  wire _17_;
  wire _18_;
  wire _19_;
  wire _20_;
  wire _21_;
  wire _22_;
  wire _23_;
  wire _24_;
  wire _25_;
  wire _26_;
  wire _27_;
  wire _28_;
  wire _29_;
  wire _30_;
  wire _31_;
  wire _32_;
  wire _33_;
  wire _34_;
  wire _35_;
  wire _36_;
  wire _37_;
  wire _38_;
  wire _39_;
  wire _40_;
  wire _41_;
  wire _42_;
  wire _43_;
  wire _44_;
  wire _45_;
  wire _46_;
  wire _47_;
  wire _48_;
  wire _49_;
  wire _50_;
  wire _51_;
  wire _52_;
  wire _53_;
  wire _54_;
  wire _55_;
  wire _56_;
  wire _57_;
  wire _58_;
  wire _59_;
  wire _60_;
  wire _61_;
  wire [7:0] _62_;
  wire _63_;
  wire _64_;
  wire _65_;
  wire [31:0] block_in;
  wire [33:0] cfg_shift_chain;
  input clk_i;
  input config_clk_i;
  input config_ena_i;
  input config_shift_i;
  output config_shift_o;
  input glb_rstn_i;
  input [31:0] inputs_down_i;
  input [31:0] inputs_left_i;
  input [31:0] inputs_right_i;
  input [31:0] inputs_up_i;
  wire \logic.logic_block:587 ;
  wire [7:0] \logic.logic_block:588 ;
  output [7:0] outputs_o;
  fpga_logic_block \logic.logic_block  (
    .clk_i(clk_i),
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[0]),
    .config_shift_o(_61_),
    .glb_rstn_i(glb_rstn_i),
    .inputs_i(block_in),
    .outputs_o(_62_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_down:1.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[30]),
    .config_shift_o(_26_),
    .route_i({ inputs_down_i[24], inputs_down_i[16], inputs_down_i[8], inputs_down_i[0] }),
    .route_o(_27_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_down:2.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[26]),
    .config_shift_o(_28_),
    .route_i({ inputs_down_i[25], inputs_down_i[17], inputs_down_i[9], inputs_down_i[1] }),
    .route_o(_29_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_down:3.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[22]),
    .config_shift_o(_30_),
    .route_i({ inputs_down_i[26], inputs_down_i[18], inputs_down_i[10], inputs_down_i[2] }),
    .route_o(_31_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_down:4.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[18]),
    .config_shift_o(_32_),
    .route_i({ inputs_down_i[27], inputs_down_i[19], inputs_down_i[11], inputs_down_i[3] }),
    .route_o(_34_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_down:5.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[14]),
    .config_shift_o(_35_),
    .route_i({ inputs_down_i[28], inputs_down_i[20], inputs_down_i[12], inputs_down_i[4] }),
    .route_o(_36_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_down:6.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[10]),
    .config_shift_o(_37_),
    .route_i({ inputs_down_i[29], inputs_down_i[21], inputs_down_i[13], inputs_down_i[5] }),
    .route_o(_38_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_down:7.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[6]),
    .config_shift_o(_39_),
    .route_i({ inputs_down_i[30], inputs_down_i[22], inputs_down_i[14], inputs_down_i[6] }),
    .route_o(_40_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_down:8.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[2]),
    .config_shift_o(_41_),
    .route_i({ inputs_down_i[31], inputs_down_i[23], inputs_down_i[15], inputs_down_i[7] }),
    .route_o(_42_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_left:1.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[29]),
    .config_shift_o(_43_),
    .route_i({ inputs_left_i[24], inputs_left_i[16], inputs_left_i[8], inputs_left_i[0] }),
    .route_o(_45_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_left:2.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[25]),
    .config_shift_o(_46_),
    .route_i({ inputs_left_i[25], inputs_left_i[17], inputs_left_i[9], inputs_left_i[1] }),
    .route_o(_47_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_left:3.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[21]),
    .config_shift_o(_48_),
    .route_i({ inputs_left_i[26], inputs_left_i[18], inputs_left_i[10], inputs_left_i[2] }),
    .route_o(_49_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_left:4.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[17]),
    .config_shift_o(_50_),
    .route_i({ inputs_left_i[27], inputs_left_i[19], inputs_left_i[11], inputs_left_i[3] }),
    .route_o(_51_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_left:5.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[13]),
    .config_shift_o(_52_),
    .route_i({ inputs_left_i[28], inputs_left_i[20], inputs_left_i[12], inputs_left_i[4] }),
    .route_o(_53_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_left:6.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[9]),
    .config_shift_o(_54_),
    .route_i({ inputs_left_i[29], inputs_left_i[21], inputs_left_i[13], inputs_left_i[5] }),
    .route_o(_56_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_left:7.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[5]),
    .config_shift_o(_57_),
    .route_i({ inputs_left_i[30], inputs_left_i[22], inputs_left_i[14], inputs_left_i[6] }),
    .route_o(_58_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_left:8.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[1]),
    .config_shift_o(_59_),
    .route_i({ inputs_left_i[31], inputs_left_i[23], inputs_left_i[15], inputs_left_i[7] }),
    .route_o(_60_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_right:1.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[31]),
    .config_shift_o(_08_),
    .route_i({ inputs_right_i[24], inputs_right_i[16], inputs_right_i[8], inputs_right_i[0] }),
    .route_o(_09_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_right:2.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[27]),
    .config_shift_o(_10_),
    .route_i({ inputs_right_i[25], inputs_right_i[17], inputs_right_i[9], inputs_right_i[1] }),
    .route_o(_12_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_right:3.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[23]),
    .config_shift_o(_13_),
    .route_i({ inputs_right_i[26], inputs_right_i[18], inputs_right_i[10], inputs_right_i[2] }),
    .route_o(_14_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_right:4.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[19]),
    .config_shift_o(_15_),
    .route_i({ inputs_right_i[27], inputs_right_i[19], inputs_right_i[11], inputs_right_i[3] }),
    .route_o(_16_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_right:5.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[15]),
    .config_shift_o(_17_),
    .route_i({ inputs_right_i[28], inputs_right_i[20], inputs_right_i[12], inputs_right_i[4] }),
    .route_o(_18_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_right:6.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[11]),
    .config_shift_o(_19_),
    .route_i({ inputs_right_i[29], inputs_right_i[21], inputs_right_i[13], inputs_right_i[5] }),
    .route_o(_20_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_right:7.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[7]),
    .config_shift_o(_21_),
    .route_i({ inputs_right_i[30], inputs_right_i[22], inputs_right_i[14], inputs_right_i[6] }),
    .route_o(_23_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_right:8.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[3]),
    .config_shift_o(_24_),
    .route_i({ inputs_right_i[31], inputs_right_i[23], inputs_right_i[15], inputs_right_i[7] }),
    .route_o(_25_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_up:1.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[32]),
    .config_shift_o(_00_),
    .route_i({ inputs_up_i[24], inputs_up_i[16], inputs_up_i[8], inputs_up_i[0] }),
    .route_o(_11_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_up:2.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[28]),
    .config_shift_o(_22_),
    .route_i({ inputs_up_i[25], inputs_up_i[17], inputs_up_i[9], inputs_up_i[1] }),
    .route_o(_33_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_up:3.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[24]),
    .config_shift_o(_44_),
    .route_i({ inputs_up_i[26], inputs_up_i[18], inputs_up_i[10], inputs_up_i[2] }),
    .route_o(_55_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_up:4.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[20]),
    .config_shift_o(_63_),
    .route_i({ inputs_up_i[27], inputs_up_i[19], inputs_up_i[11], inputs_up_i[3] }),
    .route_o(_64_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_up:5.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[16]),
    .config_shift_o(_65_),
    .route_i({ inputs_up_i[28], inputs_up_i[20], inputs_up_i[12], inputs_up_i[4] }),
    .route_o(_01_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_up:6.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[12]),
    .config_shift_o(_02_),
    .route_i({ inputs_up_i[29], inputs_up_i[21], inputs_up_i[13], inputs_up_i[5] }),
    .route_o(_03_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_up:7.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[8]),
    .config_shift_o(_04_),
    .route_i({ inputs_up_i[30], inputs_up_i[22], inputs_up_i[14], inputs_up_i[6] }),
    .route_o(_05_)
  );
  fpga_routing_mux_wcfg_4_2_18446744073709551615 \muxes_up:8.block_in_mux  (
    .config_clk_i(config_clk_i),
    .config_ena_i(config_ena_i),
    .config_shift_i(cfg_shift_chain[4]),
    .config_shift_o(_06_),
    .route_i({ inputs_up_i[31], inputs_up_i[23], inputs_up_i[15], inputs_up_i[7] }),
    .route_o(_07_)
  );
  assign cfg_shift_chain = { _00_, _08_, _26_, _43_, _22_, _10_, _28_, _46_, _44_, _13_, _30_, _48_, _63_, _15_, _32_, _50_, _65_, _17_, _35_, _52_, _02_, _19_, _37_, _54_, _04_, _21_, _39_, _57_, _06_, _24_, _41_, _59_, \logic.logic_block:587 , config_shift_i };
  assign block_in = { _60_, _42_, _25_, _07_, _58_, _40_, _23_, _05_, _56_, _38_, _20_, _03_, _53_, _36_, _18_, _01_, _51_, _34_, _16_, _64_, _49_, _31_, _14_, _55_, _47_, _29_, _12_, _33_, _45_, _27_, _09_, _11_ };
  assign \logic.logic_block:587  = _61_;
  assign \logic.logic_block:588  = _62_;
  assign config_shift_o = cfg_shift_chain[33];
  assign outputs_o = \logic.logic_block:588 ;
endmodule