data/full_repos/permissive/509335294/brchmux.v
data/verilator_xmls/bfd04fe7-f274-4926-a8f9-fcb0afb13ea6.xml
module brchmux(	input[12:0] pc_p2,
							input[12:0] brch_adder_res,
							input sel,
							output reg[12:0] brchmux_out
							);
					
always@(*)begin
	case(sel)
	1'b0 : brchmux_out <= pc_p2;
	1'b1 : brchmux_out <= brch_adder_res;
	endcase
end
				
endmodule
module brchmux(	input[12:0] pc_p2,
							input[12:0] brch_adder_res,
							input sel,
							output reg[12:0] brchmux_out
							);

					
always@(*)begin
	case(sel)
	1'b0 : brchmux_out <= pc_p2;
	1'b1 : brchmux_out <= brch_adder_res;
	endcase
end
				
endmodule