data/full_repos/permissive/529176308/CNN-FPGA-Vivado/CNN-FPGA-Vivado.srcs/sources_1/new/MaxPoolSingle.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/529176308/CNN-FPGA-Vivado/CNN-FPGA-Vivado.srcs/sources_1/new/MaxPoolSingle.v:10: Little bit endian vector: MSB < LSB of bit range: 0:12543\ninput [0:InputH*InputW*Depth*DATA_WIDTH-1] aPoolIn;\n      ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/529176308/CNN-FPGA-Vivado/CNN-FPGA-Vivado.srcs/sources_1/new/MaxPoolSingle.v:11: Little bit endian vector: MSB < LSB of bit range: 0:3135\noutput [0:(InputH/2)*(InputW/2)*Depth*DATA_WIDTH-1] aPoolOut;\n       ^\n%Error: data/full_repos/permissive/529176308/CNN-FPGA-Vivado/CNN-FPGA-Vivado.srcs/sources_1/new/MaxPoolSingle.v:18: Cannot find file containing module: \'max\'\n    max\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/529176308/CNN-FPGA-Vivado/CNN-FPGA-Vivado.srcs/sources_1/new,data/full_repos/permissive/529176308/max\n             data/full_repos/permissive/529176308/CNN-FPGA-Vivado/CNN-FPGA-Vivado.srcs/sources_1/new,data/full_repos/permissive/529176308/max.v\n             data/full_repos/permissive/529176308/CNN-FPGA-Vivado/CNN-FPGA-Vivado.srcs/sources_1/new,data/full_repos/permissive/529176308/max.sv\n             max\n             max.v\n             max.sv\n             obj_dir/max\n             obj_dir/max.v\n             obj_dir/max.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module MaxPoolSingle(aPoolIn,aPoolOut);
  
parameter DATA_WIDTH = 16;
parameter InputH = 28;
parameter InputW = 28;
parameter Depth = 1;

input [0:InputH*InputW*Depth*DATA_WIDTH-1] aPoolIn;
output [0:(InputH/2)*(InputW/2)*Depth*DATA_WIDTH-1] aPoolOut;

genvar i,j;

generate 
  for (i=0; i<(InputH); i=i+2) begin
    for (j=0; j<(InputW); j=j+2) begin
    max
    #(
     .DATA_WIDTH(DATA_WIDTH)
     ) max1
    (
      .n1(aPoolIn[(i*InputH+j)*DATA_WIDTH+:DATA_WIDTH]),
      .n2(aPoolIn[(i*InputH+j+1)*DATA_WIDTH+:DATA_WIDTH]),
      .n3(aPoolIn[((i+1)*InputH+j)*DATA_WIDTH+:DATA_WIDTH]),
      .n4(aPoolIn[((i+1)*InputH+j+1)*DATA_WIDTH+:DATA_WIDTH]),
      .max(aPoolOut[(i/2*InputH/2+j/2)*DATA_WIDTH+:DATA_WIDTH])
      );
    end
  end
endgenerate

endmodule
module MaxPoolSingle(aPoolIn,aPoolOut);

  
parameter DATA_WIDTH = 16;
parameter InputH = 28;
parameter InputW = 28;
parameter Depth = 1;

input [0:InputH*InputW*Depth*DATA_WIDTH-1] aPoolIn;
output [0:(InputH/2)*(InputW/2)*Depth*DATA_WIDTH-1] aPoolOut;

genvar i,j;

generate 
  for (i=0; i<(InputH); i=i+2) begin
    for (j=0; j<(InputW); j=j+2) begin
    max
    #(
     .DATA_WIDTH(DATA_WIDTH)
     ) max1
    (
      .n1(aPoolIn[(i*InputH+j)*DATA_WIDTH+:DATA_WIDTH]),
      .n2(aPoolIn[(i*InputH+j+1)*DATA_WIDTH+:DATA_WIDTH]),
      .n3(aPoolIn[((i+1)*InputH+j)*DATA_WIDTH+:DATA_WIDTH]),
      .n4(aPoolIn[((i+1)*InputH+j+1)*DATA_WIDTH+:DATA_WIDTH]),
      .max(aPoolOut[(i/2*InputH/2+j/2)*DATA_WIDTH+:DATA_WIDTH])
      );
    end
  end
endgenerate

endmodule