data/full_repos/permissive/434187796/testbench/FPGA_CLOCK_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/FPGA_CLOCK_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n                #100\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/FPGA_CLOCK_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n                #100\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/FPGA_CLOCK_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n                #100\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/FPGA_CLOCK_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n                #100\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/FPGA_CLOCK_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n                #100\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/FPGA_CLOCK_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n                #100\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/FPGA_CLOCK_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n                #100\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/FPGA_CLOCK_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n                #100\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/FPGA_CLOCK_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n                #100\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/FPGA_CLOCK_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n                #100\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/FPGA_CLOCK_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n                #100\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/FPGA_CLOCK_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n                #100\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/FPGA_CLOCK_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n                #100\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/FPGA_CLOCK_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n                #100\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/FPGA_CLOCK_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n                #100\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/FPGA_CLOCK_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n                #100\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/FPGA_CLOCK_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n                #100\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/FPGA_CLOCK_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n                #100\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/FPGA_CLOCK_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n                #100\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/FPGA_CLOCK_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n                #100\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/FPGA_CLOCK_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n                #100\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/FPGA_CLOCK_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n                #100\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/FPGA_CLOCK_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n                #100\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/FPGA_CLOCK_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n                #100\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/FPGA_CLOCK_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n                #100\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/FPGA_CLOCK_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n                #100\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/FPGA_CLOCK_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n                #100\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/FPGA_CLOCK_tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n                #100\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/FPGA_CLOCK_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n                #100\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/434187796/testbench/FPGA_CLOCK_tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n                #1000\n                ^\n%Warning-IMPLICIT: data/full_repos/permissive/434187796/testbench/FPGA_CLOCK_tb.v:124: Signal definition not found, creating implicitly: \'led_beep_enabled_port\'\n        assign led_beep_enabled_port = beep_enabled;\n               ^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 31 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module FPGA_CLOCK_tb;
        reg [6:0] control_status;
        reg beep_enabled;

        reg beep_button_posedge;
        reg set_button_posedge;
        reg add_button_posedge;
        reg rst;
        reg clk_1s;
        reg [23:0] current_time_data;
        reg [23:0] beep_time_data;

        wire [23:0] time_data;
        wire [6:0] control_status_next;
        wire [2:0] current_time_clk;
        wire [2:0] beep_time_clk;
        wire mode;
        wire beep;
        wire flash_hour;
        wire flash_minute;
        wire flash_second;

        initial begin
                control_status = 7'b000_000_1;
                beep_enabled = 1'b0;
                beep_button_posedge = 1'b0;
                set_button_posedge = 1'b0;
                add_button_posedge = 1'b0;
                beep_time_data = 10;
                current_time_data = 20;
                clk_1s = 1'b1;
                rst = 1'b1;

                #100
                set_button_posedge = 1'b1;
                #100
                set_button_posedge = 1'b0;
                #100
                add_button_posedge = 1'b1;
                #100
                add_button_posedge = 1'b0;

                #100
                set_button_posedge = 1'b1;
                #100
                set_button_posedge = 1'b0;
                #100
                add_button_posedge = 1'b1;
                #100
                add_button_posedge = 1'b0;

                #100
                set_button_posedge = 1'b1;
                #100
                set_button_posedge = 1'b0;
                #100
                add_button_posedge = 1'b1;
                #100
                add_button_posedge = 1'b0;

                #100
                set_button_posedge = 1'b1;
                #100
                set_button_posedge = 1'b0;
                #100
                add_button_posedge = 1'b1;
                #100
                add_button_posedge = 1'b0;

                #100
                set_button_posedge = 1'b1;
                #100
                set_button_posedge = 1'b0;
                #100
                add_button_posedge = 1'b1;
                #100
                add_button_posedge = 1'b0;

                #100
                set_button_posedge = 1'b1;
                #100
                set_button_posedge = 1'b0;
                #100
                add_button_posedge = 1'b1;
                #100
                add_button_posedge = 1'b0;

                #100
                beep_button_posedge = 1'b1;
                #100
                beep_button_posedge = 1'b0;

                #100
                beep_button_posedge = 1'b1;
                #100
                beep_button_posedge = 1'b0;

                #100
                rst = 1'b0;
                #1000
                $stop;
        end

        always @(posedge set_button_posedge or negedge rst) begin
                if (rst == 0) begin
                        control_status <= 7'b000_000_1;
                end else begin
                        if (add_button_posedge == 0) begin
                                control_status <= control_status_next;
                        end
                end
        end

        always @(posedge beep_button_posedge or negedge rst) begin
                if (rst == 1'b0) begin
                        beep_enabled <= 1'b0;
                end else begin
                        beep_enabled <= ~beep_enabled;
                end
        end

        assign led_beep_enabled_port = beep_enabled;
        assign current_time_clk[2] = control_status[3] & add_button_posedge;
        assign current_time_clk[1] = control_status[2] & add_button_posedge;
        assign current_time_clk[0] = (control_status[1] & add_button_posedge) | (control_status[0] & clk_1s);
        assign beep_time_clk[2] = control_status[6] & add_button_posedge;
        assign beep_time_clk[1] = control_status[5] & add_button_posedge;
        assign beep_time_clk[0] = control_status[4] & add_button_posedge;
        assign control_status_next = (control_status == 7'b100_000_0) ? 7'b000_000_1 : (control_status << 1);
        assign mode = control_status[0];
        assign time_data = (control_status[6] | control_status[5] | control_status[4]) ? beep_time_data : current_time_data;
        assign beep = (beep_time_data == current_time_data) & control_status[0];
        assign flash_second = control_status[1] | control_status[4];
        assign flash_minute = control_status[2] | control_status[5];
        assign flash_hour = control_status[3] | control_status[6];
endmodule
module FPGA_CLOCK_tb;

        reg [6:0] control_status;
        reg beep_enabled;

        reg beep_button_posedge;
        reg set_button_posedge;
        reg add_button_posedge;
        reg rst;
        reg clk_1s;
        reg [23:0] current_time_data;
        reg [23:0] beep_time_data;

        wire [23:0] time_data;
        wire [6:0] control_status_next;
        wire [2:0] current_time_clk;
        wire [2:0] beep_time_clk;
        wire mode;
        wire beep;
        wire flash_hour;
        wire flash_minute;
        wire flash_second;

        initial begin
                control_status = 7'b000_000_1;
                beep_enabled = 1'b0;
                beep_button_posedge = 1'b0;
                set_button_posedge = 1'b0;
                add_button_posedge = 1'b0;
                beep_time_data = 10;
                current_time_data = 20;
                clk_1s = 1'b1;
                rst = 1'b1;

                #100
                set_button_posedge = 1'b1;
                #100
                set_button_posedge = 1'b0;
                #100
                add_button_posedge = 1'b1;
                #100
                add_button_posedge = 1'b0;

                #100
                set_button_posedge = 1'b1;
                #100
                set_button_posedge = 1'b0;
                #100
                add_button_posedge = 1'b1;
                #100
                add_button_posedge = 1'b0;

                #100
                set_button_posedge = 1'b1;
                #100
                set_button_posedge = 1'b0;
                #100
                add_button_posedge = 1'b1;
                #100
                add_button_posedge = 1'b0;

                #100
                set_button_posedge = 1'b1;
                #100
                set_button_posedge = 1'b0;
                #100
                add_button_posedge = 1'b1;
                #100
                add_button_posedge = 1'b0;

                #100
                set_button_posedge = 1'b1;
                #100
                set_button_posedge = 1'b0;
                #100
                add_button_posedge = 1'b1;
                #100
                add_button_posedge = 1'b0;

                #100
                set_button_posedge = 1'b1;
                #100
                set_button_posedge = 1'b0;
                #100
                add_button_posedge = 1'b1;
                #100
                add_button_posedge = 1'b0;

                #100
                beep_button_posedge = 1'b1;
                #100
                beep_button_posedge = 1'b0;

                #100
                beep_button_posedge = 1'b1;
                #100
                beep_button_posedge = 1'b0;

                #100
                rst = 1'b0;
                #1000
                $stop;
        end

        always @(posedge set_button_posedge or negedge rst) begin
                if (rst == 0) begin
                        control_status <= 7'b000_000_1;
                end else begin
                        if (add_button_posedge == 0) begin
                                control_status <= control_status_next;
                        end
                end
        end

        always @(posedge beep_button_posedge or negedge rst) begin
                if (rst == 1'b0) begin
                        beep_enabled <= 1'b0;
                end else begin
                        beep_enabled <= ~beep_enabled;
                end
        end

        assign led_beep_enabled_port = beep_enabled;
        assign current_time_clk[2] = control_status[3] & add_button_posedge;
        assign current_time_clk[1] = control_status[2] & add_button_posedge;
        assign current_time_clk[0] = (control_status[1] & add_button_posedge) | (control_status[0] & clk_1s);
        assign beep_time_clk[2] = control_status[6] & add_button_posedge;
        assign beep_time_clk[1] = control_status[5] & add_button_posedge;
        assign beep_time_clk[0] = control_status[4] & add_button_posedge;
        assign control_status_next = (control_status == 7'b100_000_0) ? 7'b000_000_1 : (control_status << 1);
        assign mode = control_status[0];
        assign time_data = (control_status[6] | control_status[5] | control_status[4]) ? beep_time_data : current_time_data;
        assign beep = (beep_time_data == current_time_data) & control_status[0];
        assign flash_second = control_status[1] | control_status[4];
        assign flash_minute = control_status[2] | control_status[5];
        assign flash_hour = control_status[3] | control_status[6];
endmodule