data/full_repos/permissive/50693363/riffa_builder/src/fpga/pfm_counter.v
data/verilator_xmls/a4c3a10f-ef98-4496-bf86-7b0210d9c677.xml
module pfm_counter #(
    CHANNEL_NUM = 1,
    WIDTH = 32,
    DIV = 0)
(
    input rst,
    input clk,
    input [CHANNEL_NUM-1:0] trig,
    output reg [CHANNEL_NUM*WIDTH-1 : 0] mark
);

reg [WIDTH + DIV -1:0] counter;
reg [CHANNEL_NUM*3-1:0] trig_r;

integer i;

always @ (posedge rst or posedge clk)
begin
    if (rst)
    begin
        counter <= 'b0;
        trig_r <= 'b0;
        mark <= 'b0;
    end else begin
    
        trig_r <= {trig_r[CHANNEL_NUM*2-1:0], trig};
        
        if (~counter[WIDTH + DIV -1: DIV] != 0)
            counter <= counter + 1'b1;
        
        for (i = 0; i < CHANNEL_NUM; i = i + 1)
        begin
            if (trig_r[CHANNEL_NUM*1+i] && ~trig_r[CHANNEL_NUM*2+i])
                mark[i*WIDTH +: WIDTH] <= counter[WIDTH + DIV -1: DIV];
        end
    end
end

endmodule
module pfm_counter #(
    CHANNEL_NUM = 1,
    WIDTH = 32,
    DIV = 0)
(
    input rst,
    input clk,
    input [CHANNEL_NUM-1:0] trig,
    output reg [CHANNEL_NUM*WIDTH-1 : 0] mark
);


reg [WIDTH + DIV -1:0] counter;
reg [CHANNEL_NUM*3-1:0] trig_r;

integer i;

always @ (posedge rst or posedge clk)
begin
    if (rst)
    begin
        counter <= 'b0;
        trig_r <= 'b0;
        mark <= 'b0;
    end else begin
    
        trig_r <= {trig_r[CHANNEL_NUM*2-1:0], trig};
        
        if (~counter[WIDTH + DIV -1: DIV] != 0)
            counter <= counter + 1'b1;
        
        for (i = 0; i < CHANNEL_NUM; i = i + 1)
        begin
            if (trig_r[CHANNEL_NUM*1+i] && ~trig_r[CHANNEL_NUM*2+i])
                mark[i*WIDTH +: WIDTH] <= counter[WIDTH + DIV -1: DIV];
        end
    end
end

endmodule