data/full_repos/permissive/461141714/src/Pipelined CPU/stage_MEM.v
1: b'%Error: Cannot find file containing module: CPU,data/full_repos/permissive/461141714\n        ... Looked in:\n             data/full_repos/permissive/461141714/src/Pipelined/CPU,data/full_repos/permissive/461141714\n             data/full_repos/permissive/461141714/src/Pipelined/CPU,data/full_repos/permissive/461141714.v\n             data/full_repos/permissive/461141714/src/Pipelined/CPU,data/full_repos/permissive/461141714.sv\n             CPU,data/full_repos/permissive/461141714\n             CPU,data/full_repos/permissive/461141714.v\n             CPU,data/full_repos/permissive/461141714.sv\n             obj_dir/CPU,data/full_repos/permissive/461141714\n             obj_dir/CPU,data/full_repos/permissive/461141714.v\n             obj_dir/CPU,data/full_repos/permissive/461141714.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/461141714/src/Pipelined\n%Error: Cannot find file containing module: CPU/stage_MEM.v\n%Error: Exiting due to 3 error(s)\n'
module STAGE_MEM(
        input clk,
        input reset_n,
        

        input [`WORD_SIZE-1:0] instruction,
        input [`WORD_SIZE-1:0] addr,
        input [`WORD_SIZE-1:0] write_data,
        output [`WORD_SIZE-1:0] read_data,
        

        output reg d_readM, 
        output reg d_writeM, 
        output [`WORD_SIZE-1:0] d_address, 
        inout [`WORD_SIZE-1:0] d_data
    );
    

    wire [3:0] inst_opcode = instruction[15:12];
    assign d_address = addr;
    assign d_data = inst_opcode == `OPCODE_SWD ? write_data : `WORD_SIZE'bz;
    assign read_data = d_data;
    
    always @(posedge clk) begin
        d_readM = 0;
        d_writeM = 0;
        if(inst_opcode == `OPCODE_LWD) begin
            d_readM = 1;
        end
        else if(inst_opcode == `OPCODE_SWD) begin
            d_writeM = 1;
        end
    end
    
    always @(*) begin
        d_readM = 0;
        d_writeM = 0;
        if(inst_opcode == `OPCODE_LWD) begin
            d_readM = 1;
        end
        else if(inst_opcode == `OPCODE_SWD) begin
            d_writeM = 1;
        end
    end
    
endmodule
module STAGE_MEM(
        input clk,
        input reset_n,
        

        input [`WORD_SIZE-1:0] instruction,
        input [`WORD_SIZE-1:0] addr,
        input [`WORD_SIZE-1:0] write_data,
        output [`WORD_SIZE-1:0] read_data,
        

        output reg d_readM, 
        output reg d_writeM, 
        output [`WORD_SIZE-1:0] d_address, 
        inout [`WORD_SIZE-1:0] d_data
    );

    

    wire [3:0] inst_opcode = instruction[15:12];
    assign d_address = addr;
    assign d_data = inst_opcode == `OPCODE_SWD ? write_data : `WORD_SIZE'bz;
    assign read_data = d_data;
    
    always @(posedge clk) begin
        d_readM = 0;
        d_writeM = 0;
        if(inst_opcode == `OPCODE_LWD) begin
            d_readM = 1;
        end
        else if(inst_opcode == `OPCODE_SWD) begin
            d_writeM = 1;
        end
    end
    
    always @(*) begin
        d_readM = 0;
        d_writeM = 0;
        if(inst_opcode == `OPCODE_LWD) begin
            d_readM = 1;
        end
        else if(inst_opcode == `OPCODE_SWD) begin
            d_writeM = 1;
        end
    end
    
endmodule