data/full_repos/permissive/471941633/Memory/rwmem.v
data/verilator_xmls/fc16660d-8cea-4526-a0b4-a93d7af70d64.xml
module rwmem(
    output reg[7:0]dout,
    input [3:0]addr,
    input [7:0]din,
    input we,
    input clk
    );
reg [7:0]mem[0:15];
always @(posedge clk)
begin
if(we)
mem[addr] = din;
else
dout = mem[addr];
end
endmodule
module rwmem(
    output reg[7:0]dout,
    input [3:0]addr,
    input [7:0]din,
    input we,
    input clk
    );

reg [7:0]mem[0:15];
always @(posedge clk)
begin
if(we)
mem[addr] = din;
else
dout = mem[addr];
end
endmodule