data/full_repos/permissive/466926510/Project_files/CMP.v
data/verilator_xmls/fc53356f-5162-48c4-bbbf-b0862bd4f8e9.xml
module CMP
#(parameter WIDTH =8 ) 
(X, Y , eq_out , lt_out , gt_out );
 input [WIDTH-1:0] X , Y ;
 output  eq_out , lt_out , gt_out ;
 
 assign eq_out = (X==Y) ? 1'b1 : 1'b0 ;
  assign lt_out = (X<Y)? 1'b1  : 1'b0 ;
  assign gt_out = (X>Y)? 1'b1:  1'b0 ;
   
endmodule
module CMP
#(parameter WIDTH =8 ) 
(X, Y , eq_out , lt_out , gt_out );

 input [WIDTH-1:0] X , Y ;
 output  eq_out , lt_out , gt_out ;
 
 assign eq_out = (X==Y) ? 1'b1 : 1'b0 ;
  assign lt_out = (X<Y)? 1'b1  : 1'b0 ;
  assign gt_out = (X>Y)? 1'b1:  1'b0 ;
   
endmodule