data/full_repos/permissive/520452389/source_codes/Instruction_decode.v
data/verilator_xmls/2e96dc06-b42e-437b-9353-c464005c937c.xml
module Instruction_decode(input clk,input reset,input [31:0]instruction_s1, input [31:0]write_data_s4,input [4:0] write_reg_s4,
        input  RegWrite_s4,output RegDst_s2,output ALUSrc_s2,output  MemtoReg_s2,output RegWrite_s2,output MemRead_s2,
        output  MemWrite_s2,output  Branch_s2,output ALUOp1_s2,output ALUOp0_s2,input [31:0]pc_out1_s1,
        output [31:0]pc_out1_s2,output [31:0]extended_32_s2,output [4:0]dest_for_I_s2,output [4:0]dest_for_R_s2,
        output [31:0]read_data1_s2,output [31:0]read_data2_s2,output [4:0]source_s2 );
 wire RegDst,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,ALUOp1,ALUOp0;
 wire [31:0]extended_32,read_data1,read_data2;
 wire [4:0]rs_s2,rt_s2;

control ctrl(instruction_s1[31:26],RegDst,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,ALUOp1,ALUOp0);
Register_mem rm(reset,instruction_s1[25:21],instruction_s1[20:16],write_reg_s4,write_data_s4,read_data1,read_data2,RegWrite_s4);
sign_extend snext(instruction_s1[15:0],extended_32);
dff2 d2(clk,RegDst,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,ALUOp1,ALUOp0,
         RegDst_s2,ALUSrc_s2,MemtoReg_s2,RegWrite_s2,MemRead_s2,MemWrite_s2,Branch_s2,ALUOp1_s2,ALUOp0_s2,pc_out1_s1,pc_out1_s2,extended_32,extended_32_s2,
        instruction_s1[25:21],instruction_s1[20:16],instruction_s1[15:11],dest_for_I_s2,dest_for_R_s2,read_data1,read_data2,read_data1_s2,read_data2_s2,source_s2);                         
endmodule
module Instruction_decode(input clk,input reset,input [31:0]instruction_s1, input [31:0]write_data_s4,input [4:0] write_reg_s4,
        input  RegWrite_s4,output RegDst_s2,output ALUSrc_s2,output  MemtoReg_s2,output RegWrite_s2,output MemRead_s2,
        output  MemWrite_s2,output  Branch_s2,output ALUOp1_s2,output ALUOp0_s2,input [31:0]pc_out1_s1,
        output [31:0]pc_out1_s2,output [31:0]extended_32_s2,output [4:0]dest_for_I_s2,output [4:0]dest_for_R_s2,
        output [31:0]read_data1_s2,output [31:0]read_data2_s2,output [4:0]source_s2 );

 wire RegDst,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,ALUOp1,ALUOp0;
 wire [31:0]extended_32,read_data1,read_data2;
 wire [4:0]rs_s2,rt_s2;

control ctrl(instruction_s1[31:26],RegDst,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,ALUOp1,ALUOp0);
Register_mem rm(reset,instruction_s1[25:21],instruction_s1[20:16],write_reg_s4,write_data_s4,read_data1,read_data2,RegWrite_s4);
sign_extend snext(instruction_s1[15:0],extended_32);
dff2 d2(clk,RegDst,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,ALUOp1,ALUOp0,
         RegDst_s2,ALUSrc_s2,MemtoReg_s2,RegWrite_s2,MemRead_s2,MemWrite_s2,Branch_s2,ALUOp1_s2,ALUOp0_s2,pc_out1_s1,pc_out1_s2,extended_32,extended_32_s2,
        instruction_s1[25:21],instruction_s1[20:16],instruction_s1[15:11],dest_for_I_s2,dest_for_R_s2,read_data1,read_data2,read_data1_s2,read_data2_s2,source_s2);                         
endmodule