data/full_repos/permissive/42178149/Test_verificador.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/42178149/Test_verificador.v:87: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/42178149/Test_verificador.v:98: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: data/full_repos/permissive/42178149/Test_verificador.v:51: Cannot find file containing module: \'Verificador_gato\'\n Verificador_gato uut (\n ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/42178149,data/full_repos/permissive/42178149/Verificador_gato\n             data/full_repos/permissive/42178149,data/full_repos/permissive/42178149/Verificador_gato.v\n             data/full_repos/permissive/42178149,data/full_repos/permissive/42178149/Verificador_gato.sv\n             Verificador_gato\n             Verificador_gato.v\n             Verificador_gato.sv\n             obj_dir/Verificador_gato\n             obj_dir/Verificador_gato.v\n             obj_dir/Verificador_gato.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Test_verificador;


	reg verifica_status;
	reg [1:0] reg_c1;
	reg [1:0] reg_c2;
	reg [1:0] reg_c3;
	reg [1:0] reg_c4;
	reg [1:0] reg_c5;
	reg [1:0] reg_c6;
	reg [1:0] reg_c7;
	reg [1:0] reg_c8;
	reg [1:0] reg_c9;


	wire p1_tie;
	wire p1_loss;
	wire p1_win;
	wire p2_tie;
	wire p2_loss;
	wire p2_win;
	wire [1:0] linea_horizontal;
	wire [1:0] linea_vertical;
	wire [1:0] linea_cruzada;


	Verificador_gato uut (
		.verifica_status(verifica_status), 
		.p1_tie(p1_tie), 
		.p1_loss(p1_loss), 
		.p1_win(p1_win), 
		.p2_tie(p2_tie), 
		.p2_loss(p2_loss), 
		.p2_win(p2_win), 
		.linea_horizontal(linea_horizontal), 
		.linea_vertical(linea_vertical), 
		.linea_cruzada(linea_cruzada), 
		.reg_c1(reg_c1), 
		.reg_c2(reg_c2), 
		.reg_c3(reg_c3), 
		.reg_c4(reg_c4), 
		.reg_c5(reg_c5), 
		.reg_c6(reg_c6), 
		.reg_c7(reg_c7), 
		.reg_c8(reg_c8), 
		.reg_c9(reg_c9)
	);

	initial begin

		verifica_status = 0;
		reg_c1 = 0;
		reg_c2 = 0;
		reg_c3 = 0;
		reg_c4 = 0;
		reg_c5 = 0;
		reg_c6 = 0;
		reg_c7 = 0;
		reg_c8 = 0;
		reg_c9 = 0;


		#10;
		reg_c1 = 2'b11;
		reg_c2 = 2'b00;
		reg_c3 = 2'b01;
		reg_c4 = 2'b00;
		reg_c5 = 2'b11;
		reg_c6 = 2'b00;
		reg_c7 = 2'b00;
		reg_c8 = 2'b01;
		reg_c9 = 2'b11;
		
		#10;
		verifica_status = 1'b1;
		

	end
      
endmodule
module Test_verificador;



	reg verifica_status;
	reg [1:0] reg_c1;
	reg [1:0] reg_c2;
	reg [1:0] reg_c3;
	reg [1:0] reg_c4;
	reg [1:0] reg_c5;
	reg [1:0] reg_c6;
	reg [1:0] reg_c7;
	reg [1:0] reg_c8;
	reg [1:0] reg_c9;


	wire p1_tie;
	wire p1_loss;
	wire p1_win;
	wire p2_tie;
	wire p2_loss;
	wire p2_win;
	wire [1:0] linea_horizontal;
	wire [1:0] linea_vertical;
	wire [1:0] linea_cruzada;


	Verificador_gato uut (
		.verifica_status(verifica_status), 
		.p1_tie(p1_tie), 
		.p1_loss(p1_loss), 
		.p1_win(p1_win), 
		.p2_tie(p2_tie), 
		.p2_loss(p2_loss), 
		.p2_win(p2_win), 
		.linea_horizontal(linea_horizontal), 
		.linea_vertical(linea_vertical), 
		.linea_cruzada(linea_cruzada), 
		.reg_c1(reg_c1), 
		.reg_c2(reg_c2), 
		.reg_c3(reg_c3), 
		.reg_c4(reg_c4), 
		.reg_c5(reg_c5), 
		.reg_c6(reg_c6), 
		.reg_c7(reg_c7), 
		.reg_c8(reg_c8), 
		.reg_c9(reg_c9)
	);

	initial begin

		verifica_status = 0;
		reg_c1 = 0;
		reg_c2 = 0;
		reg_c3 = 0;
		reg_c4 = 0;
		reg_c5 = 0;
		reg_c6 = 0;
		reg_c7 = 0;
		reg_c8 = 0;
		reg_c9 = 0;


		#10;
		reg_c1 = 2'b11;
		reg_c2 = 2'b00;
		reg_c3 = 2'b01;
		reg_c4 = 2'b00;
		reg_c5 = 2'b11;
		reg_c6 = 2'b00;
		reg_c7 = 2'b00;
		reg_c8 = 2'b01;
		reg_c9 = 2'b11;
		
		#10;
		verifica_status = 1'b1;
		

	end
      
endmodule