data/full_repos/permissive/410272426/hardware_code_radix-2/modular_half.v
1: b'%Warning-WIDTH: data/full_repos/permissive/410272426/hardware_code_radix-2/modular_half.v:14: Operator ADD expects 257 bits on the RHS, but RHS\'s VARREF \'M_half\' generates 13 bits.\n                                                                                            : ... In instance modular_half\n    assign {c,s} = x_sh + M_half;\n                        ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module modular_half #(parameter data_width = 256)(
    input [data_width-1:0] x_half,
    output [data_width-1:0] y_half
    );
    
    parameter M = 14'd12289;
    parameter M_half = 13'd6145;

    wire [data_width-1:0] x_sh;
    wire c;
    wire [data_width-1:0] s;
    
    assign x_sh = x_half >> 1;
    assign {c,s} = x_sh + M_half;
    assign y_half = x_half[0] == 1? s : x_sh;
endmodule
module modular_half #(parameter data_width = 256)(
    input [data_width-1:0] x_half,
    output [data_width-1:0] y_half
    );

    
    parameter M = 14'd12289;
    parameter M_half = 13'd6145;

    wire [data_width-1:0] x_sh;
    wire c;
    wire [data_width-1:0] s;
    
    assign x_sh = x_half >> 1;
    assign {c,s} = x_sh + M_half;
    assign y_half = x_half[0] == 1? s : x_sh;
endmodule