data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_xbar_pkg.sv
1: b"%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_xbar_pkg.sv:21: Unsupported: classes\n  class axi_xbar_monitor #(\n  ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_xbar_pkg.sv:49: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n      axi_pkg::len_t slv_axi_len;\n      ^~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_xbar_pkg.sv:56: syntax error, unexpected ::, expecting '.' or ';'\n    typedef rand_id_queue_pkg::rand_id_queue #(\n                             ^~\n                                                                                                 : ... Perhaps 'rand_id_queue_pkg' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_xbar_pkg.sv:60: syntax error, unexpected ::, expecting '.' or ';'\n    typedef rand_id_queue_pkg::rand_id_queue #(\n                             ^~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_xbar_pkg.sv:65: syntax error, unexpected ::, expecting '.' or ';'\n    typedef rand_id_queue_pkg::rand_id_queue #(\n                             ^~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_xbar_pkg.sv:73: Unsupported: virtual data type\n    virtual AXI_BUS_DV #(\n    ^~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_xbar_pkg.sv:73: syntax error, unexpected '#', expecting IDENTIFIER or '=' or do or final\n    virtual AXI_BUS_DV #(\n                       ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_xbar_pkg.sv:79: Unsupported: virtual data type\n    virtual AXI_BUS_DV #(\n    ^~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_xbar_pkg.sv:79: syntax error, unexpected '#', expecting IDENTIFIER or '=' or do or final\n    virtual AXI_BUS_DV #(\n                       ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_xbar_pkg.sv:92: syntax error, unexpected IDENTIFIER\n    master_exp_queue_t exp_b_queue  [NoMasters-1:0];\n    ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_xbar_pkg.sv:104: syntax error, unexpected IDENTIFIER\n    semaphore        cnt_sem;\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_xbar_pkg.sv:109: Unsupported: new constructor\n    function new(\n             ^~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_xbar_pkg.sv:110: Unsupported: virtual data type\n      virtual AXI_BUS_DV #(\n      ^~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_xbar_pkg.sv:110: syntax error, unexpected '#', expecting IDENTIFIER\n      virtual AXI_BUS_DV #(\n                         ^\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_xbar_pkg.sv:157: syntax error, unexpected IDENTIFIER\n      exp_ax_t     exp_aw;\n      ^~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_xbar_pkg.sv:163: syntax error, unexpected if\n      if (masters_axi[i].aw_valid && masters_axi[i].aw_ready) begin\n      ^~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_xbar_pkg.sv:216: syntax error, unexpected if\n      if (slaves_axi[i].aw_valid && slaves_axi[i].aw_ready) begin\n      ^~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_xbar_pkg.sv:251: syntax error, unexpected if\n      if (slaves_axi[i].w_valid && slaves_axi[i].w_ready) begin\n      ^~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_xbar_pkg.sv:263: syntax error, unexpected while\n      while (this.exp_w_fifo[i].size() != 0 && this.act_w_fifo[i].size() != 0) begin\n      ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_xbar_pkg.sv:281: syntax error, unexpected if\n      if (masters_axi[i].b_valid && masters_axi[i].b_ready) begin\n      ^~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_xbar_pkg.sv:306: syntax error, unexpected IDENTIFIER\n      axi_pkg::len_t mst_axi_len;\n      ^~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_xbar_pkg.sv:310: syntax error, unexpected IDENTIFIER\n      exp_ax_t       exp_slv_ar;\n      ^~~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_xbar_pkg.sv:315: syntax error, unexpected if\n      if (masters_axi[i].ar_valid && masters_axi[i].ar_ready) begin\n      ^~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_xbar_pkg.sv:358: syntax error, unexpected if\n      if (slaves_axi[i].ar_valid && slaves_axi[i].ar_ready) begin\n      ^~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/axi/test/tb_axi_xbar_pkg.sv:381: syntax error, unexpected if\n      if (masters_axi[i].r_valid && masters_axi[i].r_ready) begin\n      ^~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n"
function new(
      virtual AXI_BUS_DV #(
        .AXI_ADDR_WIDTH ( AxiAddrWidth      ),
        .AXI_DATA_WIDTH ( AxiDataWidth      ),
        .AXI_ID_WIDTH   ( AxiIdWidthMasters ),
        .AXI_USER_WIDTH ( AxiUserWidth      )
      ) axi_masters_vif [NoMasters-1:0],
      virtual AXI_BUS_DV #(
        .AXI_ADDR_WIDTH ( AxiAddrWidth      ),
        .AXI_DATA_WIDTH ( AxiDataWidth      ),
        .AXI_ID_WIDTH   ( AxiIdWidthSlaves  ),
        .AXI_USER_WIDTH ( AxiUserWidth      )
      ) axi_slaves_vif [NoSlaves-1:0]
    );
      begin
        this.masters_axi     = axi_masters_vif;
        this.slaves_axi      = axi_slaves_vif;
        this.tests_expected  = 0;
        this.tests_conducted = 0;
        this.tests_failed    = 0;
        for (int unsigned i = 0; i < NoMasters; i++) begin
          this.exp_b_queue[i] = new;
          this.exp_r_queue[i] = new;
        end
        for (int unsigned i = 0; i < NoSlaves; i++) begin
          this.exp_aw_queue[i] = new;
          this.exp_ar_queue[i] = new;
        end
        this.cnt_sem = new(1);
      end
    endfunction
function new(
      virtual AXI_BUS_DV #(
        .AXI_ADDR_WIDTH ( AxiAddrWidth      ),
        .AXI_DATA_WIDTH ( AxiDataWidth      ),
        .AXI_ID_WIDTH   ( AxiIdWidthMasters ),
        .AXI_USER_WIDTH ( AxiUserWidth      )
      ) axi_masters_vif [NoMasters-1:0],
      virtual AXI_BUS_DV #(
        .AXI_ADDR_WIDTH ( AxiAddrWidth      ),
        .AXI_DATA_WIDTH ( AxiDataWidth      ),
        .AXI_ID_WIDTH   ( AxiIdWidthSlaves  ),
        .AXI_USER_WIDTH ( AxiUserWidth      )
      ) axi_slaves_vif [NoSlaves-1:0]
    );

      begin
        this.masters_axi     = axi_masters_vif;
        this.slaves_axi      = axi_slaves_vif;
        this.tests_expected  = 0;
        this.tests_conducted = 0;
        this.tests_failed    = 0;
        for (int unsigned i = 0; i < NoMasters; i++) begin
          this.exp_b_queue[i] = new;
          this.exp_r_queue[i] = new;
        end
        for (int unsigned i = 0; i < NoSlaves; i++) begin
          this.exp_aw_queue[i] = new;
          this.exp_ar_queue[i] = new;
        end
        this.cnt_sem = new(1);
      end
    endfunction