data/full_repos/permissive/47956074/rtl/bytewrite_ram_32bits.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/47956074/rtl/bytewrite_ram_32bits.v:38: Unsupported: Ignoring delay on this delayed statement.\n   #10;\n   ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/47956074/rtl/bytewrite_ram_32bits.v:49: Bit extraction of array[1023:0] requires 10 bit index, not 12 bits.\n                                                                                 : ... In instance bytewrite_ram_32bits\n    dout <= RAM[addr];\n               ^\n%Warning-WIDTH: data/full_repos/permissive/47956074/rtl/bytewrite_ram_32bits.v:55: Bit extraction of array[1023:0] requires 10 bit index, not 12 bits.\n                                                                                 : ... In instance bytewrite_ram_32bits\n     RAM[addr][(0+1)*COL_WIDTH-1:0*COL_WIDTH] <= din[(0+1)*COL_WIDTH-1:0*COL_WIDTH];\n        ^\n%Warning-WIDTH: data/full_repos/permissive/47956074/rtl/bytewrite_ram_32bits.v:61: Bit extraction of array[1023:0] requires 10 bit index, not 12 bits.\n                                                                                 : ... In instance bytewrite_ram_32bits\n     RAM[addr][(1+1)*COL_WIDTH-1:1*COL_WIDTH] <= din[(1+1)*COL_WIDTH-1:1*COL_WIDTH];\n        ^\n%Warning-WIDTH: data/full_repos/permissive/47956074/rtl/bytewrite_ram_32bits.v:66: Bit extraction of array[1023:0] requires 10 bit index, not 12 bits.\n                                                                                 : ... In instance bytewrite_ram_32bits\n     RAM[addr][(2+1)*COL_WIDTH-1:2*COL_WIDTH] <= din[(2+1)*COL_WIDTH-1:2*COL_WIDTH];\n        ^\n%Warning-WIDTH: data/full_repos/permissive/47956074/rtl/bytewrite_ram_32bits.v:72: Bit extraction of array[1023:0] requires 10 bit index, not 12 bits.\n                                                                                 : ... In instance bytewrite_ram_32bits\n     RAM[addr][(3+1)*COL_WIDTH-1:3*COL_WIDTH] <= din[(3+1)*COL_WIDTH-1:3*COL_WIDTH];\n        ^\n%Error: Exiting due to 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module bytewrite_ram_32bits (clk, we, addr, din, dout);

parameter SIZE = 1024;
parameter ADDR_WIDTH = 12;

parameter filename = "code.hex";

localparam COL_WIDTH = 8;
localparam NB_COL = 4;




input	clk;
input	[NB_COL-1:0]	we;
input	[ADDR_WIDTH-1:0]	addr;
input	[NB_COL*COL_WIDTH-1:0] din;
output reg [NB_COL*COL_WIDTH-1:0] dout;

reg	[NB_COL*COL_WIDTH-1:0] RAM [SIZE-1:0];

   integer                     _i;

initial begin
`ifndef IVERILOG
   $readmemh(filename,RAM);
`endif
   #10;

   for(_i=0;_i<6;_i=_i+1) begin
      $display("idx : %d data : %x",_i,RAM[_i]);
   end
   $display("======================");
end


always @(posedge clk)
begin
    dout <= RAM[addr];
end


always @(posedge clk) begin
   if (we[0])
     RAM[addr][(0+1)*COL_WIDTH-1:0*COL_WIDTH] <= din[(0+1)*COL_WIDTH-1:0*COL_WIDTH];
end


always @(posedge clk) begin
   if (we[1])
     RAM[addr][(1+1)*COL_WIDTH-1:1*COL_WIDTH] <= din[(1+1)*COL_WIDTH-1:1*COL_WIDTH];
end

always @(posedge clk) begin
   if (we[2])
     RAM[addr][(2+1)*COL_WIDTH-1:2*COL_WIDTH] <= din[(2+1)*COL_WIDTH-1:2*COL_WIDTH];
end


always @(posedge clk) begin
   if (we[3])
     RAM[addr][(3+1)*COL_WIDTH-1:3*COL_WIDTH] <= din[(3+1)*COL_WIDTH-1:3*COL_WIDTH];
end





endmodule
module bytewrite_ram_32bits (clk, we, addr, din, dout);


parameter SIZE = 1024;
parameter ADDR_WIDTH = 12;

parameter filename = "code.hex";

localparam COL_WIDTH = 8;
localparam NB_COL = 4;




input	clk;
input	[NB_COL-1:0]	we;
input	[ADDR_WIDTH-1:0]	addr;
input	[NB_COL*COL_WIDTH-1:0] din;
output reg [NB_COL*COL_WIDTH-1:0] dout;

reg	[NB_COL*COL_WIDTH-1:0] RAM [SIZE-1:0];

   integer                     _i;

initial begin
`ifndef IVERILOG
   $readmemh(filename,RAM);
`endif
   #10;

   for(_i=0;_i<6;_i=_i+1) begin
      $display("idx : %d data : %x",_i,RAM[_i]);
   end
   $display("======================");
end


always @(posedge clk)
begin
    dout <= RAM[addr];
end


always @(posedge clk) begin
   if (we[0])
     RAM[addr][(0+1)*COL_WIDTH-1:0*COL_WIDTH] <= din[(0+1)*COL_WIDTH-1:0*COL_WIDTH];
end


always @(posedge clk) begin
   if (we[1])
     RAM[addr][(1+1)*COL_WIDTH-1:1*COL_WIDTH] <= din[(1+1)*COL_WIDTH-1:1*COL_WIDTH];
end

always @(posedge clk) begin
   if (we[2])
     RAM[addr][(2+1)*COL_WIDTH-1:2*COL_WIDTH] <= din[(2+1)*COL_WIDTH-1:2*COL_WIDTH];
end


always @(posedge clk) begin
   if (we[3])
     RAM[addr][(3+1)*COL_WIDTH-1:3*COL_WIDTH] <= din[(3+1)*COL_WIDTH-1:3*COL_WIDTH];
end





endmodule