data/full_repos/permissive/494148647/src/peripherals/gcnt/gcnt_iom.v
1: b'%Error: data/full_repos/permissive/494148647/src/peripherals/gcnt/gcnt_iom.v:32: Cannot find file containing module: \'counter\'\n    counter #(.COUNT_BITS(COUNT_BITS)) global_counter (\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/494148647/src/peripherals/gcnt,data/full_repos/permissive/494148647/counter\n             data/full_repos/permissive/494148647/src/peripherals/gcnt,data/full_repos/permissive/494148647/counter.v\n             data/full_repos/permissive/494148647/src/peripherals/gcnt,data/full_repos/permissive/494148647/counter.sv\n             counter\n             counter.v\n             counter.sv\n             obj_dir/counter\n             obj_dir/counter.v\n             obj_dir/counter.sv\n%Warning-WIDTH: data/full_repos/permissive/494148647/src/peripherals/gcnt/gcnt_iom.v:50: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s SEL generates 24 bits.\n                                                                                       : ... In instance gcnt_iom\n                        4: io_read_data_q <= #1 count[COUNT_BITS-1:32];\n                                          ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module gcnt_iom#(
    parameter COUNT_BITS = 56
    )(
    input clk,
    input rst,
    input io_addr_strobe,
    input io_read_strobe,
    input io_write_strobe,
    input [11:0] io_address,
    input [3:0] io_byte_enable,
    input [31:0] io_write_data,
    output [31:0] io_read_data,
    output io_ready

    );

    reg [31:0] io_read_data_q;
    reg io_ready_q;

    wire [COUNT_BITS-1:0] count;

    assign io_read_data = io_read_data_q;
    assign io_ready = io_ready_q;

    counter #(.COUNT_BITS(COUNT_BITS)) global_counter (
        .clk(clk),
        .rst(rst),
        .count(count)
    );

    always @(posedge clk, posedge rst) begin
        if (rst) begin
            io_read_data_q <= #1 32'b0;
            io_ready_q <= #1 1'b0;
        end else begin
            io_read_data_q <= #1 32'b0;
            io_ready_q <= #1 1'b0;

            if (io_addr_strobe) begin
                if (io_read_strobe) begin
                    case (io_address)
                        0: io_read_data_q <= #1 count[31:0];
                        4: io_read_data_q <= #1 count[COUNT_BITS-1:32];
                    endcase
                end

                io_ready_q <= #1 1'b1;
            end
        end
    end

endmodule
module gcnt_iom#(
    parameter COUNT_BITS = 56
    )(
    input clk,
    input rst,
    input io_addr_strobe,
    input io_read_strobe,
    input io_write_strobe,
    input [11:0] io_address,
    input [3:0] io_byte_enable,
    input [31:0] io_write_data,
    output [31:0] io_read_data,
    output io_ready

    );


    reg [31:0] io_read_data_q;
    reg io_ready_q;

    wire [COUNT_BITS-1:0] count;

    assign io_read_data = io_read_data_q;
    assign io_ready = io_ready_q;

    counter #(.COUNT_BITS(COUNT_BITS)) global_counter (
        .clk(clk),
        .rst(rst),
        .count(count)
    );

    always @(posedge clk, posedge rst) begin
        if (rst) begin
            io_read_data_q <= #1 32'b0;
            io_ready_q <= #1 1'b0;
        end else begin
            io_read_data_q <= #1 32'b0;
            io_ready_q <= #1 1'b0;

            if (io_addr_strobe) begin
                if (io_read_strobe) begin
                    case (io_address)
                        0: io_read_data_q <= #1 count[31:0];
                        4: io_read_data_q <= #1 count[COUNT_BITS-1:32];
                    endcase
                end

                io_ready_q <= #1 1'b1;
            end
        end
    end

endmodule