data/full_repos/permissive/474104412/hardware/src/ext_mem.v
1: b'%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:3: Cannot find include file: system.vh\n`include "system.vh" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/474104412/hardware/src,data/full_repos/permissive/474104412/system.vh\n             data/full_repos/permissive/474104412/hardware/src,data/full_repos/permissive/474104412/system.vh.v\n             data/full_repos/permissive/474104412/hardware/src,data/full_repos/permissive/474104412/system.vh.sv\n             system.vh\n             system.vh.v\n             system.vh.sv\n             obj_dir/system.vh\n             obj_dir/system.vh.v\n             obj_dir/system.vh.sv\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:4: Cannot find include file: iob_intercon.vh\n`include "iob_intercon.vh" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:26: Cannot find include file: m_axi_m_port.vh\n`include "m_axi_m_port.vh" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:27: Cannot find include file: iob_gen_if.vh\n`include "iob_gen_if.vh" \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:120: Cannot find include file: m_axi_portmap.vh\n`include "m_axi_portmap.vh" \n         ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:8: Define or directive not defined: \'`ADDR_W\'\n    parameter ADDR_W=`ADDR_W,\n                     ^~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:8: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    parameter ADDR_W=`ADDR_W,\n                            ^\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:9: Define or directive not defined: \'`DATA_W\'\n    parameter DATA_W=`DATA_W,\n                     ^~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:9: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    parameter DATA_W=`DATA_W,\n                            ^\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:11: syntax error, unexpected parameter, expecting IDENTIFIER\n    parameter AXI_ADDR_W=`ADDR_W,\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:11: Define or directive not defined: \'`ADDR_W\'\n    parameter AXI_ADDR_W=`ADDR_W,\n                         ^~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:11: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n    parameter AXI_ADDR_W=`ADDR_W,\n                                ^\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:12: Define or directive not defined: \'`DATA_W\'\n    parameter AXI_DATA_W=`DATA_W\n                         ^~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:13: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n    )\n    ^\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:22: Define or directive not defined: \'`DCACHE_ADDR_W\'\n    input [1+1+`DCACHE_ADDR_W-2+`WRITE_W-1:0] d_req,\n               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:22: Define or directive not defined: \'`WRITE_W\'\n    input [1+1+`DCACHE_ADDR_W-2+`WRITE_W-1:0] d_req,\n                                ^~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:23: Define or directive not defined: \'`RESP_W\'\n    output [`RESP_W-1:0]         d_resp,\n            ^~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:31: Define or directive not defined: \'`DCACHE_ADDR_W\'\n    wire [1+`DCACHE_ADDR_W+`WRITE_W-1:0]       l2cache_req;\n            ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:31: Define or directive not defined: \'`WRITE_W\'\n    wire [1+`DCACHE_ADDR_W+`WRITE_W-1:0]       l2cache_req;\n                           ^~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:32: Define or directive not defined: \'`RESP_W\'\n    wire [`RESP_W-1:0]                        l2cache_resp;\n          ^~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:38: Define or directive not defined: \'`DCACHE_ADDR_W\'\n    wire                                      l2_valid = l2cache_req[1+`DCACHE_ADDR_W+`WRITE_W-1];\n                                                                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:38: Define or directive not defined: \'`WRITE_W\'\n    wire                                      l2_valid = l2cache_req[1+`DCACHE_ADDR_W+`WRITE_W-1];\n                                                                                      ^~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:40: syntax error, unexpected always\n    always @(posedge clk, posedge rst)\n    ^~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:61: Define or directive not defined: \'`DCACHE_ADDR_W\'\n   wire [1+`DCACHE_ADDR_W+`WRITE_W-1:0]       dcache_req;\n           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:61: Define or directive not defined: \'`WRITE_W\'\n   wire [1+`DCACHE_ADDR_W+`WRITE_W-1:0]       dcache_req;\n                          ^~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:62: Define or directive not defined: \'`RESP_W\'\n   wire [`RESP_W-1:0]                        dcache_resp;\n         ^~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:63: syntax error, unexpected assign\n   assign d_resp = dcache_resp;\n   ^~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:64: Define or directive not defined: \'`DCACHE_ADDR_W\'\n   assign dcache_req = {d_req[2+`DCACHE_ADDR_W-2+`WRITE_W-1], d_req[`address(0,`DCACHE_ADDR_W-2)], 2\'b11, d_req[`WRITE_W-1:0]};\n                                ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:64: Define or directive not defined: \'`WRITE_W\'\n   assign dcache_req = {d_req[2+`DCACHE_ADDR_W-2+`WRITE_W-1], d_req[`address(0,`DCACHE_ADDR_W-2)], 2\'b11, d_req[`WRITE_W-1:0]};\n                                                 ^~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:64: Define or directive not defined: \'`address\'\n   assign dcache_req = {d_req[2+`DCACHE_ADDR_W-2+`WRITE_W-1], d_req[`address(0,`DCACHE_ADDR_W-2)], 2\'b11, d_req[`WRITE_W-1:0]};\n                                                                    ^~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:64: Define or directive not defined: \'`DCACHE_ADDR_W\'\n   assign dcache_req = {d_req[2+`DCACHE_ADDR_W-2+`WRITE_W-1], d_req[`address(0,`DCACHE_ADDR_W-2)], 2\'b11, d_req[`WRITE_W-1:0]};\n                                                                               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:64: Define or directive not defined: \'`WRITE_W\'\n   assign dcache_req = {d_req[2+`DCACHE_ADDR_W-2+`WRITE_W-1], d_req[`address(0,`DCACHE_ADDR_W-2)], 2\'b11, d_req[`WRITE_W-1:0]};\n                                                                                                                ^~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:95: Define or directive not defined: \'`DCACHE_ADDR_W\'\n      .FE_ADDR_W(`DCACHE_ADDR_W),\n                 ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:96: Define or directive not defined: \'`DDR_ADDR_W\'\n      .BE_ADDR_W(`DDR_ADDR_W),\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:97: Define or directive not defined: \'`DDR_DATA_W\'\n      .BE_DATA_W(`DDR_DATA_W),\n                 ^~~~~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:108: Define or directive not defined: \'`DCACHE_ADDR_W\'\n      .valid    (l2cache_req[1+`DCACHE_ADDR_W+`WRITE_W-1]),\n                               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:108: Define or directive not defined: \'`WRITE_W\'\n      .valid    (l2cache_req[1+`DCACHE_ADDR_W+`WRITE_W-1]),\n                                              ^~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:109: Define or directive not defined: \'`address\'\n      .addr     (l2cache_req[`address(0, `DCACHE_ADDR_W)-2]),\n                             ^~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:109: Define or directive not defined: \'`DCACHE_ADDR_W\'\n      .addr     (l2cache_req[`address(0, `DCACHE_ADDR_W)-2]),\n                                         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:110: Define or directive not defined: \'`wdata\'\n      .wdata    (l2cache_req[`wdata(0)]),\n                             ^~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:111: Define or directive not defined: \'`wstrb\'\n      .wstrb    (l2cache_req[`wstrb(0)]),\n                             ^~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:112: Define or directive not defined: \'`rdata\'\n      .rdata    (l2cache_resp[`rdata(0)]),\n                              ^~~~~~\n%Error: data/full_repos/permissive/474104412/hardware/src/ext_mem.v:113: Define or directive not defined: \'`ready\'\n      .ready    (l2cache_resp[`ready(0)]),\n                              ^~~~~~\n%Error: Exiting due to 43 error(s)\n'
module ext_mem
  #(
    parameter ADDR_W=`ADDR_W,
    parameter DATA_W=`DATA_W,
    parameter AXI_ID_W=0,
    parameter AXI_ADDR_W=`ADDR_W,
    parameter AXI_DATA_W=`DATA_W
    )
   (
`ifdef RUN_EXTMEM

    input [1+`FIRM_ADDR_W-2+`WRITE_W-1:0]     i_req,
    output [`RESP_W-1:0] 		      i_resp,
`endif


    input [1+1+`DCACHE_ADDR_W-2+`WRITE_W-1:0] d_req,
    output [`RESP_W-1:0] 		      d_resp,


`include "m_axi_m_port.vh"
`include "iob_gen_if.vh"
    );


    wire [1+`DCACHE_ADDR_W+`WRITE_W-1:0]       l2cache_req;
    wire [`RESP_W-1:0]                        l2cache_resp;


    wire                                      l2_wtb_empty;
    wire                                      invalidate;
    reg                                       invalidate_reg;
    wire                                      l2_valid = l2cache_req[1+`DCACHE_ADDR_W+`WRITE_W-1];

    always @(posedge clk, posedge rst)
      if (rst)
        invalidate_reg <= 1'b0;
      else
        if (invalidate)
          invalidate_reg <= 1'b1;
        else
          if(~l2_valid)
            invalidate_reg <= 1'b0;
          else
            invalidate_reg <= invalidate_reg;



`ifdef RUN_EXTMEM
   wire [1+`DCACHE_ADDR_W+`WRITE_W-1:0]       icache_req;
   wire [`RESP_W-1:0]                        icache_resp;
   assign i_resp = icache_resp;
   assign icache_req = {i_req[1+`FIRM_ADDR_W-2+`WRITE_W-1], {(`DCACHE_ADDR_W-`FIRM_ADDR_W){1'b0}}, i_req[`address(0, `FIRM_ADDR_W-2)], 2'b00, i_req[`WRITE_W-1:0]};
`endif

   wire [1+`DCACHE_ADDR_W+`WRITE_W-1:0]       dcache_req;
   wire [`RESP_W-1:0]                        dcache_resp;
   assign d_resp = dcache_resp;
   assign dcache_req = {d_req[2+`DCACHE_ADDR_W-2+`WRITE_W-1], d_req[`address(0,`DCACHE_ADDR_W-2)], 2'b11, d_req[`WRITE_W-1:0]};



`ifdef RUN_EXTMEM
   iob_merge
     #(
       .ADDR_W(`DCACHE_ADDR_W),
       .N_MASTERS(2)
       )
   merge_i_d_buses_into_l2
     (
      .clk(clk),
      .rst(rst),

      .m_req  ({icache_req, dcache_req}),
      .m_resp ({icache_resp, dcache_resp}),

      .s_req  (l2cache_req),
      .s_resp (l2cache_resp)
      );
`else
   assign l2cache_req = dcache_req;
   assign l2cache_resp = dcache_resp;
`endif



   iob_cache_axi #
     (
      .AXI_ID_W(AXI_ID_W),
      .FE_ADDR_W(`DCACHE_ADDR_W),
      .BE_ADDR_W(`DDR_ADDR_W),
      .BE_DATA_W(`DDR_DATA_W),
      .N_WAYS(4),
      .LINE_OFF_W(7),
      .WORD_OFF_W(3),
      .WTBUF_DEPTH_W(5),
      .CTRL_CACHE (0),
      .CTRL_CNT(0)
      )
   l2cache 
     (

      .valid    (l2cache_req[1+`DCACHE_ADDR_W+`WRITE_W-1]),
      .addr     (l2cache_req[`address(0, `DCACHE_ADDR_W)-2]),
      .wdata    (l2cache_req[`wdata(0)]),
      .wstrb    (l2cache_req[`wstrb(0)]),
      .rdata    (l2cache_resp[`rdata(0)]),
      .ready    (l2cache_resp[`ready(0)]),

      .force_inv_in(invalidate_reg & ~l2_valid),
      .force_inv_out(),
      .wtb_empty_in(1'b1),
      .wtb_empty_out(l2_wtb_empty),

`include "m_axi_portmap.vh"
      .clk(clk),
      .reset(rst)
      );

endmodule
module ext_mem
  #(
    parameter ADDR_W=`ADDR_W,
    parameter DATA_W=`DATA_W,
    parameter AXI_ID_W=0,
    parameter AXI_ADDR_W=`ADDR_W,
    parameter AXI_DATA_W=`DATA_W
    )
   (
`ifdef RUN_EXTMEM

    input [1+`FIRM_ADDR_W-2+`WRITE_W-1:0]     i_req,
    output [`RESP_W-1:0] 		      i_resp,
`endif


    input [1+1+`DCACHE_ADDR_W-2+`WRITE_W-1:0] d_req,
    output [`RESP_W-1:0] 		      d_resp,


`include "m_axi_m_port.vh"
`include "iob_gen_if.vh"
    );



    wire [1+`DCACHE_ADDR_W+`WRITE_W-1:0]       l2cache_req;
    wire [`RESP_W-1:0]                        l2cache_resp;


    wire                                      l2_wtb_empty;
    wire                                      invalidate;
    reg                                       invalidate_reg;
    wire                                      l2_valid = l2cache_req[1+`DCACHE_ADDR_W+`WRITE_W-1];

    always @(posedge clk, posedge rst)
      if (rst)
        invalidate_reg <= 1'b0;
      else
        if (invalidate)
          invalidate_reg <= 1'b1;
        else
          if(~l2_valid)
            invalidate_reg <= 1'b0;
          else
            invalidate_reg <= invalidate_reg;



`ifdef RUN_EXTMEM
   wire [1+`DCACHE_ADDR_W+`WRITE_W-1:0]       icache_req;
   wire [`RESP_W-1:0]                        icache_resp;
   assign i_resp = icache_resp;
   assign icache_req = {i_req[1+`FIRM_ADDR_W-2+`WRITE_W-1], {(`DCACHE_ADDR_W-`FIRM_ADDR_W){1'b0}}, i_req[`address(0, `FIRM_ADDR_W-2)], 2'b00, i_req[`WRITE_W-1:0]};
`endif

   wire [1+`DCACHE_ADDR_W+`WRITE_W-1:0]       dcache_req;
   wire [`RESP_W-1:0]                        dcache_resp;
   assign d_resp = dcache_resp;
   assign dcache_req = {d_req[2+`DCACHE_ADDR_W-2+`WRITE_W-1], d_req[`address(0,`DCACHE_ADDR_W-2)], 2'b11, d_req[`WRITE_W-1:0]};



`ifdef RUN_EXTMEM
   iob_merge
     #(
       .ADDR_W(`DCACHE_ADDR_W),
       .N_MASTERS(2)
       )
   merge_i_d_buses_into_l2
     (
      .clk(clk),
      .rst(rst),

      .m_req  ({icache_req, dcache_req}),
      .m_resp ({icache_resp, dcache_resp}),

      .s_req  (l2cache_req),
      .s_resp (l2cache_resp)
      );
`else
   assign l2cache_req = dcache_req;
   assign l2cache_resp = dcache_resp;
`endif



   iob_cache_axi #
     (
      .AXI_ID_W(AXI_ID_W),
      .FE_ADDR_W(`DCACHE_ADDR_W),
      .BE_ADDR_W(`DDR_ADDR_W),
      .BE_DATA_W(`DDR_DATA_W),
      .N_WAYS(4),
      .LINE_OFF_W(7),
      .WORD_OFF_W(3),
      .WTBUF_DEPTH_W(5),
      .CTRL_CACHE (0),
      .CTRL_CNT(0)
      )
   l2cache 
     (

      .valid    (l2cache_req[1+`DCACHE_ADDR_W+`WRITE_W-1]),
      .addr     (l2cache_req[`address(0, `DCACHE_ADDR_W)-2]),
      .wdata    (l2cache_req[`wdata(0)]),
      .wstrb    (l2cache_req[`wstrb(0)]),
      .rdata    (l2cache_resp[`rdata(0)]),
      .ready    (l2cache_resp[`ready(0)]),

      .force_inv_in(invalidate_reg & ~l2_valid),
      .force_inv_out(),
      .wtb_empty_in(1'b1),
      .wtb_empty_out(l2_wtb_empty),

`include "m_axi_portmap.vh"
      .clk(clk),
      .reset(rst)
      );

endmodule