data/full_repos/permissive/419538859/lab7/lab7_1self/lab7_1self4.v
1: b'%Warning-WIDTH: data/full_repos/permissive/419538859/lab7/lab7_1self/lab7_1self4.v:19: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s VARREF \'timer1\' generates 2 bits.\n                                                                                     : ... In instance lab7_1self4\n    (seg7_sel == 3\'b100 )? timer1 :\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/419538859/lab7/lab7_1self/lab7_1self4.v:21: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s VARREF \'timer3\' generates 2 bits.\n                                                                                     : ... In instance lab7_1self4\n    (seg7_sel == 3\'b010 )? timer3 :4\'b0;\n                         ^\n%Error: Exiting due to 2 warning(s)\n'
module 		freq_div(clk_in,reset,clk_out);

parameter	exp = 20;   
input		clk_in, reset;
output		clk_out;
reg			[exp-1:0] divider;
integer 	i;

assign 	clk_out= divider[exp-1];

always@ (posedge clk_in or posedge reset)
begin
	if(reset)
		for(i=0; i < exp; i=i+1)
		divider[i] = 1'b0;
	else
		divider = divider+ 1'b1;
end
endmodule
module 		freq_div(clk_in,reset,clk_out);


parameter	exp = 20;   
input		clk_in, reset;
output		clk_out;
reg			[exp-1:0] divider;
integer 	i;

assign 	clk_out= divider[exp-1];

always@ (posedge clk_in or posedge reset)
begin
	if(reset)
		for(i=0; i < exp; i=i+1)
		divider[i] = 1'b0;
	else
		divider = divider+ 1'b1;
end
endmodule