data/full_repos/permissive/502544928/crossbar.v
data/verilator_xmls/d27f429a-a173-4699-988b-9e11640a3b19.xml
module crossbar #(parameter DATA_WIDTH = 32, IN_PORTS = 5, OUT_PORTS = 5, OUT_PORT_BITS = 3) (
    input clk,
    input reset,

    input [(IN_PORTS * DATA_WIDTH) - 1:0]      in_data,
	input [(IN_PORTS * OUT_PORT_BITS) - 1:0]   req_ports, 
	input [IN_PORTS - 1:0]                     grants, 

	output  [(OUT_PORTS * DATA_WIDTH) - 1: 0]  out_data,

	output  [OUT_PORTS - 1: 0]                 valid 			  
); 

wire		[(OUT_PORTS * DATA_WIDTH) - 1: 0] temp_out_data; 
reg		[DATA_WIDTH - 1: 0] t_temp_out_data [OUT_PORTS - 1:0];
  
reg		[OUT_PORTS - 1: 0]                temp_valid; 
wire 	   [OUT_PORT_BITS - 1: 0]   p_req_ports [IN_PORTS - 1:0];

integer i, t; 
genvar j;
generate
	   for (j = 0; j < IN_PORTS; j = j + 1) begin : XB_PORTS
      		assign p_req_ports[j] = req_ports [(((j + 1) *OUT_PORT_BITS)-1) -: OUT_PORT_BITS]; 
  		end
		
	   for (j = 0; j < OUT_PORTS; j = j + 1) begin : XB_O_PORTS
      		assign temp_out_data [(((j + 1) *DATA_WIDTH)-1) -: DATA_WIDTH] = t_temp_out_data[j]; 
  		end		
endgenerate 



always @ (posedge clk) begin
	if (reset) begin
		temp_valid    = 0; 
	end 
else begin           
		  temp_valid     = 0; 
   		for (i = 0; i < IN_PORTS; i = i + 1) begin
  			if (grants[i] && (p_req_ports[i] < OUT_PORTS)) begin
				  t_temp_out_data [p_req_ports[i]] = in_data[(((i + 1) *DATA_WIDTH)-1) -: DATA_WIDTH];
				  temp_valid [p_req_ports[i]]   = 1; 
  			end
  		end                               
	end



end




	assign valid       = temp_valid;
	assign out_data    = temp_out_data;
		
endmodule
module crossbar #(parameter DATA_WIDTH = 32, IN_PORTS = 5, OUT_PORTS = 5, OUT_PORT_BITS = 3) (
    input clk,
    input reset,

    input [(IN_PORTS * DATA_WIDTH) - 1:0]      in_data,
	input [(IN_PORTS * OUT_PORT_BITS) - 1:0]   req_ports, 
	input [IN_PORTS - 1:0]                     grants, 

	output  [(OUT_PORTS * DATA_WIDTH) - 1: 0]  out_data,

	output  [OUT_PORTS - 1: 0]                 valid 			  
);
 

wire		[(OUT_PORTS * DATA_WIDTH) - 1: 0] temp_out_data; 
reg		[DATA_WIDTH - 1: 0] t_temp_out_data [OUT_PORTS - 1:0];
  
reg		[OUT_PORTS - 1: 0]                temp_valid; 
wire 	   [OUT_PORT_BITS - 1: 0]   p_req_ports [IN_PORTS - 1:0];

integer i, t; 
genvar j;
generate
	   for (j = 0; j < IN_PORTS; j = j + 1) begin : XB_PORTS
      		assign p_req_ports[j] = req_ports [(((j + 1) *OUT_PORT_BITS)-1) -: OUT_PORT_BITS]; 
  		end
		
	   for (j = 0; j < OUT_PORTS; j = j + 1) begin : XB_O_PORTS
      		assign temp_out_data [(((j + 1) *DATA_WIDTH)-1) -: DATA_WIDTH] = t_temp_out_data[j]; 
  		end		
endgenerate 



always @ (posedge clk) begin
	if (reset) begin
		temp_valid    = 0; 
	end 
else begin           
		  temp_valid     = 0; 
   		for (i = 0; i < IN_PORTS; i = i + 1) begin
  			if (grants[i] && (p_req_ports[i] < OUT_PORTS)) begin
				  t_temp_out_data [p_req_ports[i]] = in_data[(((i + 1) *DATA_WIDTH)-1) -: DATA_WIDTH];
				  temp_valid [p_req_ports[i]]   = 1; 
  			end
  		end                               
	end



end




	assign valid       = temp_valid;
	assign out_data    = temp_out_data;
		
endmodule