data/full_repos/permissive/490299936/verilog/adxl345_controller.v
1: b'%Warning-WIDTH: data/full_repos/permissive/490299936/verilog/adxl345_controller.v:114: Value too large for 19 bit number: 599999\nassign timer[2] = (cnt_10ms == 19\'d599_999);\n                               ^~~~~~~~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/490299936/verilog/adxl345_controller.v:115: Value too large for 19 bit number: 699999\nassign timer[3] = (cnt_10ms == 19\'d699_999);\n                               ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/490299936/verilog/adxl345_controller.v:116: Value too large for 19 bit number: 899999\nassign timer[4] = (cnt_10ms == 19\'d899_999);\n                               ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/490299936/verilog/adxl345_controller.v:117: Value too large for 19 bit number: 999999\nassign timer[5] = (cnt_10ms == 19\'d999_999);\n                               ^~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/490299936/verilog/adxl345_controller.v:47: Signal definition not found, creating implicitly: \'add_cnt_1100us\'\n                                                                                       : ... Suggested alternative: \'cnt_1100us\'\nassign add_cnt_1100us = 1\'b1;\n       ^~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/490299936/verilog/adxl345_controller.v:48: Signal definition not found, creating implicitly: \'end_cnt_1100us\'\n                                                                                       : ... Suggested alternative: \'add_cnt_1100us\'\nassign end_cnt_1100us = add_cnt_1100us && (cnt_1100us == TIME_1100us - 1);\n       ^~~~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/490299936/verilog/adxl345_controller.v:94: Signal definition not found, creating implicitly: \'add_cnt_10ms\'\n                                                                                       : ... Suggested alternative: \'add_cnt_1100us\'\nassign add_cnt_10ms = 1\'b1;\n       ^~~~~~~~~~~~\n%Warning-IMPLICIT: data/full_repos/permissive/490299936/verilog/adxl345_controller.v:95: Signal definition not found, creating implicitly: \'end_cnt_10ms\'\n                                                                                       : ... Suggested alternative: \'add_cnt_10ms\'\nassign end_cnt_10ms = add_cnt_10ms && cnt_10ms == TIME_10ms - 1;\n       ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/490299936/verilog/adxl345_controller.v:48: Operator EQ expects 32 or 17 bits on the LHS, but LHS\'s VARREF \'cnt_1100us\' generates 16 bits.\n                                                                                    : ... In instance adxl345_controller\nassign end_cnt_1100us = add_cnt_1100us && (cnt_1100us == TIME_1100us - 1);\n                                                      ^~\n%Warning-WIDTH: data/full_repos/permissive/490299936/verilog/adxl345_controller.v:95: Operator EQ expects 32 or 20 bits on the LHS, but LHS\'s VARREF \'cnt_10ms\' generates 19 bits.\n                                                                                    : ... In instance adxl345_controller\nassign end_cnt_10ms = add_cnt_10ms && cnt_10ms == TIME_10ms - 1;\n                                               ^~\n%Error: Exiting due to 10 warning(s)\n'
module adxl345_controller(
	input clk,
	input rst_n,
	output reg iicwr_req,
	output reg iicrd_req,
	output reg[7:0] iic_addr,
	output reg[7:0] iic_wrdb,
	input [7:0] iic_rddb,
	input iic_ack,
	output reg[12:0] x_axis,
	output reg[12:0] y_axis,
	output reg[12:0] z_axis
    );


parameter DATA_FORMAT_ADDR = 8'h31,
		  DATA_FORMAT_INIT = 8'h0B,
		  POWER_CTL_ADDR = 8'h2D,
		  POWER_CTL_INIT = 8'h08,
		  INT_ENABLE_ADDR = 8'h2E,
		  INT_ENABLE_INIT = 8'h80;


reg[15:0] cnt_1100us;
reg load_done;
localparam TIME_1100us = 110000;
assign add_cnt_1100us = 1'b1;
assign end_cnt_1100us = add_cnt_1100us && (cnt_1100us == TIME_1100us - 1);
always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		cnt_1100us <= 16'd0;
		load_done <= 1'b0;
	end
	else if(add_cnt_1100us) begin
		if(end_cnt_1100us) begin
			cnt_1100us <= 16'd0;
			load_done <= 1'b1;
		end
		else begin
			cnt_1100us <= cnt_1100us + 1'b1;
		end
	end
end

reg init_done_r;

initial begin
	init_done_r <= 1'b0;
end
parameter CIDLE = 3'b000,
		  CWR1 = 3'b001,
		  CWA1 = 3'b010,
		  CWR2 = 3'b011,
		  CWA2 = 3'b100,
		  CWR3 = 3'b101,
		  CSTOP = 3'b110;
reg [2:0] i_cstate;
reg [2:0] i_nstate;


always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		i_cstate <= CIDLE;
	end
	else begin
		i_cstate <= i_nstate;
	end
end



reg [18:0] cnt_10ms;
parameter TIME_10ms = 1000_000;
assign add_cnt_10ms = 1'b1;
assign end_cnt_10ms = add_cnt_10ms && cnt_10ms == TIME_10ms - 1;
always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		cnt_10ms <= 19'd0;
	end
	else if(add_cnt_10ms) begin
		if(end_cnt_10ms) begin
			cnt_10ms <= 19'd0;
		end
		else begin
			cnt_10ms <= cnt_10ms + 1'b1;
		end
	end
end

wire [5:0] timer;

assign timer[0] = (cnt_10ms == 19'd299_999);
assign timer[1] = (cnt_10ms == 19'd399_999);
assign timer[2] = (cnt_10ms == 19'd599_999);
assign timer[3] = (cnt_10ms == 19'd699_999);
assign timer[4] = (cnt_10ms == 19'd899_999);
assign timer[5] = (cnt_10ms == 19'd999_999);


parameter X_LSB_ADDR = 8'h32,
		  X_MSB_ADDR = 8'h33,
		  Y_LSB_ADDR = 8'h34,
		  Y_MSB_ADDR = 8'h35,
		  Z_LSB_ADDR = 8'h36,
		  Z_MSB_ADDR = 8'h37;

parameter RIDLE = 4'h0,

		  RRDX0 = 4'h1,
		  RWAX0 = 4'h2,
		  RRDX1 = 4'h3,
		  RWAX1 = 4'h4,

		  RRDY0 = 4'h5,
		  RWAY0 = 4'h6,
		  RRDY1 = 4'h7,
		  RWAY1 = 4'h8,

		  RRDZ0 = 4'h9,
		  RWAZ0 = 4'hA,
		  RRDZ1 = 4'hB;
reg [3:0] cstate;
reg [3:0] nstate;


always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		cstate <= RIDLE;
	end
	else begin
		cstate <= nstate;
	end
end


always @(cstate or i_cstate or iic_ack or init_done_r or load_done or end_cnt_1100us
		or timer[0] or timer[1] or timer[2] or timer[3] or timer[4] or timer[5]) begin

	if(~init_done_r && load_done) begin
		case(i_cstate)
			CIDLE: begin
				if(end_cnt_1100us) begin
					i_nstate <= CWR1;
				end
				else begin
					i_nstate <= CIDLE;
				end
			end
			CWR1: begin
				if(iic_ack) begin
					i_nstate <= CWA1;
				end
				else begin
					i_nstate <= CWR1;
				end
			end
			CWA1: begin
				if(end_cnt_1100us) begin
					i_nstate <= CWR2;
				end
				else begin
					i_nstate <= CWA1;
				end
			end
			CWR2: begin
				if(iic_ack) begin
					i_nstate <= CWA2;
				end
				else begin
					i_nstate <= CWR2;
				end
			end
			CWA2: begin
				if(end_cnt_1100us) begin
					i_nstate <= CWR3;
				end
				else begin
					i_nstate <= CWA2;
				end
			end
			CWR3: begin
				if(iic_ack) begin
					i_nstate <= CSTOP;
				end
				else begin
					i_nstate <= CWR3;
				end
			end
			CSTOP: begin
				if(~init_done_r) begin
					init_done_r <= 1'b1;
				end
				i_nstate <= CIDLE;
			end
			default: i_nstate <= CIDLE;
		endcase
	end
	else begin
		case(cstate)
			RIDLE: begin
				if(timer[0]) begin
					nstate <= RRDX0;
				end
				else begin
					nstate <= RIDLE;
				end
			end
			RRDX0: begin
				if(iic_ack) begin
					nstate <= RWAX0;
				end
				else begin
					nstate <= RRDX0;
				end
			end
			RWAX0: begin
				if(timer[1]) begin
					nstate <= RRDX1;
				end
				else begin
					nstate <= RWAX0;
				end
			end
			RRDX1: begin
				if(iic_ack) begin
					nstate <= RWAX1;
				end
				else begin
					nstate <= RRDX1;
				end
			end
			RWAX1: begin
				if(timer[2]) begin
					nstate <= RRDY0;
				end
				else begin
					nstate <= RWAX1;
				end
			end
			RRDY0: begin
				if(iic_ack) begin
					nstate <= RWAY0;
				end
				else begin
					nstate <= RRDY0;
				end
			end
			RWAY0: begin
				if(timer[3]) begin
					nstate <= RRDY1;
				end
				else begin
					nstate <= RWAY0;
				end
			end
			RRDY1: begin
				if(iic_ack) begin
					nstate <= RWAY1;
				end
				else begin
					nstate <= RRDY1;
				end
			end
			RWAY1: begin
				if(timer[4]) begin
					nstate <= RRDZ0;
				end
				else begin
					nstate <= RWAY1;
				end
			end
			RRDZ0: begin
				if(iic_ack) begin
					nstate <= RWAZ0;
				end
				else begin
					nstate <= RRDZ0;
				end
			end
			RWAZ0: begin
				if(timer[5]) begin
					nstate <= RRDZ1;
				end
				else begin
					nstate <= RWAZ0;
				end
			end
			RRDZ1: begin
				if(iic_ack) begin
					nstate <= RIDLE;
				end
				else begin
					nstate <= RRDZ1;
				end
			end
			default: nstate <= RIDLE;
		endcase
	end
end

always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		iicwr_req <= 1'b0;
		iicrd_req <= 1'b0;
		iic_addr <= 8'd0;
		iic_wrdb <= 8'd0;
	end

	else if(~init_done_r) begin
		case(i_cstate)

			CWR1: begin
				iicwr_req <= 1'b1;

				iicrd_req <= 1'b0;

				iic_addr <= DATA_FORMAT_ADDR;

				iic_wrdb <= DATA_FORMAT_INIT;
			end

			CWR2: begin
				iicwr_req <= 1'b1;

				iicrd_req <= 1'b0;

				iic_addr <= POWER_CTL_ADDR;

				iic_wrdb <= POWER_CTL_INIT;
			end

			CWR3: begin
				iicwr_req <= 1'b1;

				iicrd_req <= 1'b0;

				iic_addr <= INT_ENABLE_ADDR;

				iic_wrdb <= INT_ENABLE_INIT;
			end
			default: begin
				iicwr_req <= 1'b0;
				iicrd_req <= 1'b0;
				iic_addr <= 8'd0;
				iic_wrdb <= 8'd0;
			end
		endcase
	end
	else begin
		case(cstate)

			RRDX0: begin
				iicwr_req <= 1'b0;

				iicrd_req <= 1'b1;

				iic_addr <= X_LSB_ADDR;

				iic_wrdb <= 8'd0;
			end

			RRDX1: begin
				iicwr_req <= 1'b0;

				iicrd_req <= 1'b1;

				iic_addr <= X_MSB_ADDR;

				iic_wrdb <= 8'd0;
			end

			RRDY0: begin
				iicwr_req <= 1'b0;

				iicrd_req <= 1'b1;

				iic_addr <= Y_LSB_ADDR;

				iic_wrdb <= 8'd0;
			end

			RRDY1: begin
				iicwr_req <= 1'b0;

				iicrd_req <= 1'b1;

				iic_addr <= Y_MSB_ADDR;

				iic_wrdb <= 8'd0;
			end

			RRDZ0: begin
				iicwr_req <= 1'b0;

				iicrd_req <= 1'b1;

				iic_addr <= Z_LSB_ADDR;

				iic_wrdb <= 8'd0;
			end

			RRDZ1: begin
				iicwr_req <= 1'b0;

				iicrd_req <= 1'b1;

				iic_addr <= Z_MSB_ADDR;

				iic_wrdb <= 8'd0;
			end
			default: begin
				iicwr_req <= 1'b0;
				iicrd_req <= 1'b0;
				iic_addr <= 8'd0;
				iic_wrdb <= 8'd0;
			end
		endcase
	end
end

always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		x_axis <= 13'd0;
		y_axis <= 13'd0;
		z_axis <= 13'd0;
	end
	else begin
		case(cstate)
			RRDX0: if(iic_ack) begin
				x_axis[7:0] <= iic_rddb;
			end
			RRDX1: if(iic_ack) begin
				x_axis[12:8] <= iic_rddb[4:0];
			end
			RRDY0: if(iic_ack) begin
				y_axis[7:0] <= iic_rddb;
			end
			RRDY1: if(iic_ack) begin
				y_axis[12:8] <= iic_rddb[4:0];
			end
			RRDZ0: if(iic_ack) begin
				z_axis[7:0] <= iic_rddb;
			end
			RRDZ1: if(iic_ack) begin
				z_axis[12:8] <= iic_rddb[4:0];
			end
			default: ;
		endcase
	end
end

endmodule
module adxl345_controller(
	input clk,
	input rst_n,
	output reg iicwr_req,
	output reg iicrd_req,
	output reg[7:0] iic_addr,
	output reg[7:0] iic_wrdb,
	input [7:0] iic_rddb,
	input iic_ack,
	output reg[12:0] x_axis,
	output reg[12:0] y_axis,
	output reg[12:0] z_axis
    );



parameter DATA_FORMAT_ADDR = 8'h31,
		  DATA_FORMAT_INIT = 8'h0B,
		  POWER_CTL_ADDR = 8'h2D,
		  POWER_CTL_INIT = 8'h08,
		  INT_ENABLE_ADDR = 8'h2E,
		  INT_ENABLE_INIT = 8'h80;


reg[15:0] cnt_1100us;
reg load_done;
localparam TIME_1100us = 110000;
assign add_cnt_1100us = 1'b1;
assign end_cnt_1100us = add_cnt_1100us && (cnt_1100us == TIME_1100us - 1);
always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		cnt_1100us <= 16'd0;
		load_done <= 1'b0;
	end
	else if(add_cnt_1100us) begin
		if(end_cnt_1100us) begin
			cnt_1100us <= 16'd0;
			load_done <= 1'b1;
		end
		else begin
			cnt_1100us <= cnt_1100us + 1'b1;
		end
	end
end

reg init_done_r;

initial begin
	init_done_r <= 1'b0;
end
parameter CIDLE = 3'b000,
		  CWR1 = 3'b001,
		  CWA1 = 3'b010,
		  CWR2 = 3'b011,
		  CWA2 = 3'b100,
		  CWR3 = 3'b101,
		  CSTOP = 3'b110;
reg [2:0] i_cstate;
reg [2:0] i_nstate;


always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		i_cstate <= CIDLE;
	end
	else begin
		i_cstate <= i_nstate;
	end
end



reg [18:0] cnt_10ms;
parameter TIME_10ms = 1000_000;
assign add_cnt_10ms = 1'b1;
assign end_cnt_10ms = add_cnt_10ms && cnt_10ms == TIME_10ms - 1;
always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		cnt_10ms <= 19'd0;
	end
	else if(add_cnt_10ms) begin
		if(end_cnt_10ms) begin
			cnt_10ms <= 19'd0;
		end
		else begin
			cnt_10ms <= cnt_10ms + 1'b1;
		end
	end
end

wire [5:0] timer;

assign timer[0] = (cnt_10ms == 19'd299_999);
assign timer[1] = (cnt_10ms == 19'd399_999);
assign timer[2] = (cnt_10ms == 19'd599_999);
assign timer[3] = (cnt_10ms == 19'd699_999);
assign timer[4] = (cnt_10ms == 19'd899_999);
assign timer[5] = (cnt_10ms == 19'd999_999);


parameter X_LSB_ADDR = 8'h32,
		  X_MSB_ADDR = 8'h33,
		  Y_LSB_ADDR = 8'h34,
		  Y_MSB_ADDR = 8'h35,
		  Z_LSB_ADDR = 8'h36,
		  Z_MSB_ADDR = 8'h37;

parameter RIDLE = 4'h0,

		  RRDX0 = 4'h1,
		  RWAX0 = 4'h2,
		  RRDX1 = 4'h3,
		  RWAX1 = 4'h4,

		  RRDY0 = 4'h5,
		  RWAY0 = 4'h6,
		  RRDY1 = 4'h7,
		  RWAY1 = 4'h8,

		  RRDZ0 = 4'h9,
		  RWAZ0 = 4'hA,
		  RRDZ1 = 4'hB;
reg [3:0] cstate;
reg [3:0] nstate;


always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		cstate <= RIDLE;
	end
	else begin
		cstate <= nstate;
	end
end


always @(cstate or i_cstate or iic_ack or init_done_r or load_done or end_cnt_1100us
		or timer[0] or timer[1] or timer[2] or timer[3] or timer[4] or timer[5]) begin

	if(~init_done_r && load_done) begin
		case(i_cstate)
			CIDLE: begin
				if(end_cnt_1100us) begin
					i_nstate <= CWR1;
				end
				else begin
					i_nstate <= CIDLE;
				end
			end
			CWR1: begin
				if(iic_ack) begin
					i_nstate <= CWA1;
				end
				else begin
					i_nstate <= CWR1;
				end
			end
			CWA1: begin
				if(end_cnt_1100us) begin
					i_nstate <= CWR2;
				end
				else begin
					i_nstate <= CWA1;
				end
			end
			CWR2: begin
				if(iic_ack) begin
					i_nstate <= CWA2;
				end
				else begin
					i_nstate <= CWR2;
				end
			end
			CWA2: begin
				if(end_cnt_1100us) begin
					i_nstate <= CWR3;
				end
				else begin
					i_nstate <= CWA2;
				end
			end
			CWR3: begin
				if(iic_ack) begin
					i_nstate <= CSTOP;
				end
				else begin
					i_nstate <= CWR3;
				end
			end
			CSTOP: begin
				if(~init_done_r) begin
					init_done_r <= 1'b1;
				end
				i_nstate <= CIDLE;
			end
			default: i_nstate <= CIDLE;
		endcase
	end
	else begin
		case(cstate)
			RIDLE: begin
				if(timer[0]) begin
					nstate <= RRDX0;
				end
				else begin
					nstate <= RIDLE;
				end
			end
			RRDX0: begin
				if(iic_ack) begin
					nstate <= RWAX0;
				end
				else begin
					nstate <= RRDX0;
				end
			end
			RWAX0: begin
				if(timer[1]) begin
					nstate <= RRDX1;
				end
				else begin
					nstate <= RWAX0;
				end
			end
			RRDX1: begin
				if(iic_ack) begin
					nstate <= RWAX1;
				end
				else begin
					nstate <= RRDX1;
				end
			end
			RWAX1: begin
				if(timer[2]) begin
					nstate <= RRDY0;
				end
				else begin
					nstate <= RWAX1;
				end
			end
			RRDY0: begin
				if(iic_ack) begin
					nstate <= RWAY0;
				end
				else begin
					nstate <= RRDY0;
				end
			end
			RWAY0: begin
				if(timer[3]) begin
					nstate <= RRDY1;
				end
				else begin
					nstate <= RWAY0;
				end
			end
			RRDY1: begin
				if(iic_ack) begin
					nstate <= RWAY1;
				end
				else begin
					nstate <= RRDY1;
				end
			end
			RWAY1: begin
				if(timer[4]) begin
					nstate <= RRDZ0;
				end
				else begin
					nstate <= RWAY1;
				end
			end
			RRDZ0: begin
				if(iic_ack) begin
					nstate <= RWAZ0;
				end
				else begin
					nstate <= RRDZ0;
				end
			end
			RWAZ0: begin
				if(timer[5]) begin
					nstate <= RRDZ1;
				end
				else begin
					nstate <= RWAZ0;
				end
			end
			RRDZ1: begin
				if(iic_ack) begin
					nstate <= RIDLE;
				end
				else begin
					nstate <= RRDZ1;
				end
			end
			default: nstate <= RIDLE;
		endcase
	end
end

always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		iicwr_req <= 1'b0;
		iicrd_req <= 1'b0;
		iic_addr <= 8'd0;
		iic_wrdb <= 8'd0;
	end

	else if(~init_done_r) begin
		case(i_cstate)

			CWR1: begin
				iicwr_req <= 1'b1;

				iicrd_req <= 1'b0;

				iic_addr <= DATA_FORMAT_ADDR;

				iic_wrdb <= DATA_FORMAT_INIT;
			end

			CWR2: begin
				iicwr_req <= 1'b1;

				iicrd_req <= 1'b0;

				iic_addr <= POWER_CTL_ADDR;

				iic_wrdb <= POWER_CTL_INIT;
			end

			CWR3: begin
				iicwr_req <= 1'b1;

				iicrd_req <= 1'b0;

				iic_addr <= INT_ENABLE_ADDR;

				iic_wrdb <= INT_ENABLE_INIT;
			end
			default: begin
				iicwr_req <= 1'b0;
				iicrd_req <= 1'b0;
				iic_addr <= 8'd0;
				iic_wrdb <= 8'd0;
			end
		endcase
	end
	else begin
		case(cstate)

			RRDX0: begin
				iicwr_req <= 1'b0;

				iicrd_req <= 1'b1;

				iic_addr <= X_LSB_ADDR;

				iic_wrdb <= 8'd0;
			end

			RRDX1: begin
				iicwr_req <= 1'b0;

				iicrd_req <= 1'b1;

				iic_addr <= X_MSB_ADDR;

				iic_wrdb <= 8'd0;
			end

			RRDY0: begin
				iicwr_req <= 1'b0;

				iicrd_req <= 1'b1;

				iic_addr <= Y_LSB_ADDR;

				iic_wrdb <= 8'd0;
			end

			RRDY1: begin
				iicwr_req <= 1'b0;

				iicrd_req <= 1'b1;

				iic_addr <= Y_MSB_ADDR;

				iic_wrdb <= 8'd0;
			end

			RRDZ0: begin
				iicwr_req <= 1'b0;

				iicrd_req <= 1'b1;

				iic_addr <= Z_LSB_ADDR;

				iic_wrdb <= 8'd0;
			end

			RRDZ1: begin
				iicwr_req <= 1'b0;

				iicrd_req <= 1'b1;

				iic_addr <= Z_MSB_ADDR;

				iic_wrdb <= 8'd0;
			end
			default: begin
				iicwr_req <= 1'b0;
				iicrd_req <= 1'b0;
				iic_addr <= 8'd0;
				iic_wrdb <= 8'd0;
			end
		endcase
	end
end

always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		x_axis <= 13'd0;
		y_axis <= 13'd0;
		z_axis <= 13'd0;
	end
	else begin
		case(cstate)
			RRDX0: if(iic_ack) begin
				x_axis[7:0] <= iic_rddb;
			end
			RRDX1: if(iic_ack) begin
				x_axis[12:8] <= iic_rddb[4:0];
			end
			RRDY0: if(iic_ack) begin
				y_axis[7:0] <= iic_rddb;
			end
			RRDY1: if(iic_ack) begin
				y_axis[12:8] <= iic_rddb[4:0];
			end
			RRDZ0: if(iic_ack) begin
				z_axis[7:0] <= iic_rddb;
			end
			RRDZ1: if(iic_ack) begin
				z_axis[12:8] <= iic_rddb[4:0];
			end
			default: ;
		endcase
	end
end

endmodule