data/full_repos/permissive/487568919/basic_verilog/cdc_data.sv
1: b"%Error: data/full_repos/permissive/487568919/basic_verilog/cdc_data.sv:43: Cannot find file containing module: 'delay'\ndelay #(\n^~~~~\n        ... Looked in:\n             data/full_repos/permissive/487568919/basic_verilog,data/full_repos/permissive/487568919/delay\n             data/full_repos/permissive/487568919/basic_verilog,data/full_repos/permissive/487568919/delay.v\n             data/full_repos/permissive/487568919/basic_verilog,data/full_repos/permissive/487568919/delay.sv\n             delay\n             delay.v\n             delay.sv\n             obj_dir/delay\n             obj_dir/delay.v\n             obj_dir/delay.sv\n%Error: Exiting due to 1 error(s)\n"
module cdc_data(
  input clk,
  input nrst,
  input d,
  output q
);

delay #(
    .LENGTH( 2 ),
    .WIDTH( 1 ),
    .TYPE( "CELLS" ),
    .REGISTER_OUTPUTS( "FALSE" )
) data_SYNC_ATTR (
    .clk( clk ),
    .nrst( nrst ),
    .ena( 1'b1 ),

    .in( d ),
    .out( q )
);

endmodule
module cdc_data(
  input clk,
  input nrst,
  input d,
  output q
);


delay #(
    .LENGTH( 2 ),
    .WIDTH( 1 ),
    .TYPE( "CELLS" ),
    .REGISTER_OUTPUTS( "FALSE" )
) data_SYNC_ATTR (
    .clk( clk ),
    .nrst( nrst ),
    .ena( 1'b1 ),

    .in( d ),
    .out( q )
);

endmodule