data/full_repos/permissive/418749135/shift_right.v
data/verilator_xmls/874eabc3-9e5c-494c-9327-725f62dc88ae.xml
module shift_right_register( in, en, Q, clk );

    input in, en, clk;
    output [7:0] Q;
    reg [7:0] Q;

    initial 
        Q = 8'b00000000;
    
    always @(posedge clk) begin
        if(en)
        begin
            Q = {in, Q[7:1]};
        end
    end
endmodule
module shift_right_register( in, en, Q, clk );


    input in, en, clk;
    output [7:0] Q;
    reg [7:0] Q;

    initial 
        Q = 8'b00000000;
    
    always @(posedge clk) begin
        if(en)
        begin
            Q = {in, Q[7:1]};
        end
    end
endmodule