data/full_repos/permissive/441359809/src/yosys/tests/simple/always01.v
data/verilator_xmls/6799e086-d20b-4b42-adee-00552c92402c.xml
module uut_always01(clock, reset, count);

input clock, reset;
output [3:0] count;
reg [3:0] count;

always @(posedge clock)
	count <= reset ?  0 : count + 1;

endmodule
module uut_always01(clock, reset, count);


input clock, reset;
output [3:0] count;
reg [3:0] count;

always @(posedge clock)
	count <= reset ?  0 : count + 1;

endmodule