data/full_repos/permissive/493019833/test/testcase/firrtl/Sort/reference/Sort.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/Sort/reference/Sort.v:583: Operator COND expects 64 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 24 bits.\n                                                                                                   : ... In instance Sort.s_pad_58\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/Sort/reference/Sort.v:562: Operator COND expects 56 bits on the Conditional False, but Conditional False\'s SEL generates 1 bits.\n                                                                                                   : ... In instance Sort.s_shr_41\n    assign y = n < width ? in[width-1:n] : in[width-1:width-1];\n                         ^\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/Sort/reference/Sort.v:519: Operator COND expects 3 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 1 bits.\n                                                                                                   : ... In instance Sort.u_pad_10\n    assign y = (n > width) ? {{(n - width){1\'b0}}, in} : in;\n                           ^\n%Error: Exiting due to 3 warning(s)\n'
module MUX_UNSIGNED(y, sel, a, b);
    parameter width = 4;
    output [width-1:0] y;
    input sel;
    input [width-1:0] a;
    input [width-1:0] b;
    assign y = sel ? a : b;
endmodule
module MUX_UNSIGNED(y, sel, a, b);

    parameter width = 4;
    output [width-1:0] y;
    input sel;
    input [width-1:0] a;
    input [width-1:0] b;
    assign y = sel ? a : b;
endmodule