data/full_repos/permissive/497039278/tb/pro_tbex4.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:47: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 0; wr <= 1; wdata <= 32\'h10F00001;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:48: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 1; wr <= 1; wdata <= 32\'h10F10002;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:49: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 2; wr <= 1; wdata <= 32\'h10F20003;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:50: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 3; wr <= 1; wdata <= 32\'h10F30004;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:51: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 4; wr <= 1; wdata <= 32\'h10F40005;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:52: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 5; wr <= 1; wdata <= 32\'h10F50006;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:53: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 6; wr <= 1; wdata <= 32\'h10F60007;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 7; wr <= 1; wdata <= 32\'h10F70008;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:55: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 8; wr <= 1; wdata <= 32\'h7000000A;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:56: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 9; wr <= 1; wdata <= 32\'h21760000; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:57: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 10;wr <= 1; wdata <= 32\'h20760000; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:58: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 11;wr <= 1; wdata <= 32\'h20100000; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:59: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 12;wr <= 1; wdata <= 32\'h21700000; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:60: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 13;wr <= 1; wdata <= 32\'h7500000B; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:61: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 14;wr <= 1; wdata <= 32\'h20760000; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:62: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 15;wr <= 1; wdata <= 32\'h20200000; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:63: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 16;wr <= 1; wdata <= 32\'h21700000; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:64: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 17;wr <= 1; wdata <= 32\'h7600000F; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 18;wr <= 1; wdata <= 32\'h20750000; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:66: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 19;wr <= 1; wdata <= 32\'h20300000; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:67: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 20;wr <= 1; wdata <= 32\'h21700000; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:68: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 21;wr <= 1; wdata <= 32\'h73000013; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:69: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 22;wr <= 1; wdata <= 32\'h20750000; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:70: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 23;wr <= 1; wdata <= 32\'h20300000; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:71: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 24;wr <= 1; wdata <= 32\'h21700000; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:72: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 25;wr <= 1; wdata <= 32\'h74000017; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:73: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 26;wr <= 1; wdata <= 32\'h21600000; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:74: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 27;wr <= 1; wdata <= 32\'h21670000; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:75: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 28;wr <= 1; wdata <= 32\'h7100001A; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:76: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 29;wr <= 1; wdata <= 32\'h21500000; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:77: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 30;wr <= 1; wdata <= 32\'h21570000; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:78: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 31;wr <= 1; wdata <= 32\'h7200001D; \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:80: Unsupported: Ignoring delay on this delayed statement.\n    #20         addr <= 0; wr <= 0; wdata <= 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:81: Unsupported: Ignoring delay on this delayed statement.\n    #10         working <= 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:82: Unsupported: Ignoring delay on this delayed statement.\n    #3100       working <= 0; flg <= 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:83: Unsupported: Ignoring delay on this delayed statement.\n    #100       $stop;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/497039278/tb/pro_tbex4.v:85: Unsupported: Ignoring delay on this delayed statement.\nalways #10 clock = ~clock;\n       ^\n%Error: data/full_repos/permissive/497039278/tb/pro_tbex4.v:92: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("pro_tbex4.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/497039278/tb/pro_tbex4.v:93: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars();\n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 37 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module pro_tb4;
reg             clock;
reg[31:0]        addr;
reg             wr;
reg[31:0]       wdata;
reg             working;
reg[3:0]        rID;

wire[31:0]      valE;
wire[31:0]      r0, r1, r2, r3, r4, r5, r6, r7;
wire[31:0]      rdata;
reg             flg = 0;
wire[2:0]       cc;






processor processor(
                clock,
                addr,
                wr,
                wdata,
                working,
                rID,







                valE,
                r0, r1, r2, r3, r4, r5, r6, r7,
                rdata,
                cc

);
initial begin
    clock <= 0; addr <= 0; wr <= 0; wdata <= 0; working <= 0; rID <= 4'b1111;




    #20         addr <= 0; wr <= 1; wdata <= 32'h10F00001;
    #20         addr <= 1; wr <= 1; wdata <= 32'h10F10002;
    #20         addr <= 2; wr <= 1; wdata <= 32'h10F20003;
    #20         addr <= 3; wr <= 1; wdata <= 32'h10F30004;
    #20         addr <= 4; wr <= 1; wdata <= 32'h10F40005;
    #20         addr <= 5; wr <= 1; wdata <= 32'h10F50006;
    #20         addr <= 6; wr <= 1; wdata <= 32'h10F60007;
    #20         addr <= 7; wr <= 1; wdata <= 32'h10F70008;
    #20         addr <= 8; wr <= 1; wdata <= 32'h7000000A;
    #20         addr <= 9; wr <= 1; wdata <= 32'h21760000;
    #20         addr <= 10;wr <= 1; wdata <= 32'h20760000;
    #20         addr <= 11;wr <= 1; wdata <= 32'h20100000;
    #20         addr <= 12;wr <= 1; wdata <= 32'h21700000;
    #20         addr <= 13;wr <= 1; wdata <= 32'h7500000B;
    #20         addr <= 14;wr <= 1; wdata <= 32'h20760000;
    #20         addr <= 15;wr <= 1; wdata <= 32'h20200000;
    #20         addr <= 16;wr <= 1; wdata <= 32'h21700000;
    #20         addr <= 17;wr <= 1; wdata <= 32'h7600000F;
    #20         addr <= 18;wr <= 1; wdata <= 32'h20750000;
    #20         addr <= 19;wr <= 1; wdata <= 32'h20300000;
    #20         addr <= 20;wr <= 1; wdata <= 32'h21700000;
    #20         addr <= 21;wr <= 1; wdata <= 32'h73000013;
    #20         addr <= 22;wr <= 1; wdata <= 32'h20750000;
    #20         addr <= 23;wr <= 1; wdata <= 32'h20300000;
    #20         addr <= 24;wr <= 1; wdata <= 32'h21700000;
    #20         addr <= 25;wr <= 1; wdata <= 32'h74000017;
    #20         addr <= 26;wr <= 1; wdata <= 32'h21600000;
    #20         addr <= 27;wr <= 1; wdata <= 32'h21670000;
    #20         addr <= 28;wr <= 1; wdata <= 32'h7100001A;
    #20         addr <= 29;wr <= 1; wdata <= 32'h21500000;
    #20         addr <= 30;wr <= 1; wdata <= 32'h21570000;
    #20         addr <= 31;wr <= 1; wdata <= 32'h7200001D;

    #20         addr <= 0; wr <= 0; wdata <= 0;
    #10         working <= 1;
    #3100       working <= 0; flg <= 1;
    #100       $stop;
end
always #10 clock = ~clock;
always @(posedge clock ) begin
    if (flg)begin
        rID <= rID + 1;
    end
end
initial begin
    $dumpfile("pro_tbex4.vcd");
    $dumpvars();
end
endmodule
module pro_tb4;

reg             clock;
reg[31:0]        addr;
reg             wr;
reg[31:0]       wdata;
reg             working;
reg[3:0]        rID;

wire[31:0]      valE;
wire[31:0]      r0, r1, r2, r3, r4, r5, r6, r7;
wire[31:0]      rdata;
reg             flg = 0;
wire[2:0]       cc;






processor processor(
                clock,
                addr,
                wr,
                wdata,
                working,
                rID,







                valE,
                r0, r1, r2, r3, r4, r5, r6, r7,
                rdata,
                cc

);
initial begin
    clock <= 0; addr <= 0; wr <= 0; wdata <= 0; working <= 0; rID <= 4'b1111;




    #20         addr <= 0; wr <= 1; wdata <= 32'h10F00001;
    #20         addr <= 1; wr <= 1; wdata <= 32'h10F10002;
    #20         addr <= 2; wr <= 1; wdata <= 32'h10F20003;
    #20         addr <= 3; wr <= 1; wdata <= 32'h10F30004;
    #20         addr <= 4; wr <= 1; wdata <= 32'h10F40005;
    #20         addr <= 5; wr <= 1; wdata <= 32'h10F50006;
    #20         addr <= 6; wr <= 1; wdata <= 32'h10F60007;
    #20         addr <= 7; wr <= 1; wdata <= 32'h10F70008;
    #20         addr <= 8; wr <= 1; wdata <= 32'h7000000A;
    #20         addr <= 9; wr <= 1; wdata <= 32'h21760000;
    #20         addr <= 10;wr <= 1; wdata <= 32'h20760000;
    #20         addr <= 11;wr <= 1; wdata <= 32'h20100000;
    #20         addr <= 12;wr <= 1; wdata <= 32'h21700000;
    #20         addr <= 13;wr <= 1; wdata <= 32'h7500000B;
    #20         addr <= 14;wr <= 1; wdata <= 32'h20760000;
    #20         addr <= 15;wr <= 1; wdata <= 32'h20200000;
    #20         addr <= 16;wr <= 1; wdata <= 32'h21700000;
    #20         addr <= 17;wr <= 1; wdata <= 32'h7600000F;
    #20         addr <= 18;wr <= 1; wdata <= 32'h20750000;
    #20         addr <= 19;wr <= 1; wdata <= 32'h20300000;
    #20         addr <= 20;wr <= 1; wdata <= 32'h21700000;
    #20         addr <= 21;wr <= 1; wdata <= 32'h73000013;
    #20         addr <= 22;wr <= 1; wdata <= 32'h20750000;
    #20         addr <= 23;wr <= 1; wdata <= 32'h20300000;
    #20         addr <= 24;wr <= 1; wdata <= 32'h21700000;
    #20         addr <= 25;wr <= 1; wdata <= 32'h74000017;
    #20         addr <= 26;wr <= 1; wdata <= 32'h21600000;
    #20         addr <= 27;wr <= 1; wdata <= 32'h21670000;
    #20         addr <= 28;wr <= 1; wdata <= 32'h7100001A;
    #20         addr <= 29;wr <= 1; wdata <= 32'h21500000;
    #20         addr <= 30;wr <= 1; wdata <= 32'h21570000;
    #20         addr <= 31;wr <= 1; wdata <= 32'h7200001D;

    #20         addr <= 0; wr <= 0; wdata <= 0;
    #10         working <= 1;
    #3100       working <= 0; flg <= 1;
    #100       $stop;
end
always #10 clock = ~clock;
always @(posedge clock ) begin
    if (flg)begin
        rID <= rID + 1;
    end
end
initial begin
    $dumpfile("pro_tbex4.vcd");
    $dumpvars();
end
endmodule