data/full_repos/permissive/520428138/verilog/rtl/user_module_341493393195532884.v
data/verilator_xmls/45353a9e-2f32-4532-8131-900317a99fdd.xml
module user_module_341493393195532884(
        input [7:0] io_in,
        output [7:0] io_out
    );
    wire [3:0] a = io_in[7:4];
    wire [3:0] b = io_in[3:0];
    wire [7:0] c;
    assign io_out = c;

    mul_341493393195532884 #(4) mul_i(a, b, c);

endmodule
module user_module_341493393195532884(
        input [7:0] io_in,
        output [7:0] io_out
    );

    wire [3:0] a = io_in[7:4];
    wire [3:0] b = io_in[3:0];
    wire [7:0] c;
    assign io_out = c;

    mul_341493393195532884 #(4) mul_i(a, b, c);

endmodule