data/full_repos/permissive/421450529/PC.v
data/verilator_xmls/d92272e5-b305-4498-a0b2-0284d557d5a1.xml
module PC(
     input clk,
	  input reset,
	  input stall,
	  input[31:0] npc,
	  output reg[31:0] pc
    );
    initial begin
	   pc=32'h3000;
	 end
    always@(posedge clk)begin
	    if(~stall)begin
		    if(reset)begin
			   pc=32'h3000;
			 end
		    else begin
			   pc=npc;
	       end	
		 end
	end
endmodule
module PC(
     input clk,
	  input reset,
	  input stall,
	  input[31:0] npc,
	  output reg[31:0] pc
    );

    initial begin
	   pc=32'h3000;
	 end
    always@(posedge clk)begin
	    if(~stall)begin
		    if(reset)begin
			   pc=32'h3000;
			 end
		    else begin
			   pc=npc;
	       end	
		 end
	end
endmodule