data/full_repos/permissive/466874195/verilog/rtl/calc_ck_split.v
1: b"%Error: data/full_repos/permissive/466874195/verilog/rtl/calc_ck_split.v:30: Cannot find file containing module: 'calc_ck'\n        calc_ck # (\n        ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/466874195/verilog/rtl,data/full_repos/permissive/466874195/calc_ck\n             data/full_repos/permissive/466874195/verilog/rtl,data/full_repos/permissive/466874195/calc_ck.v\n             data/full_repos/permissive/466874195/verilog/rtl,data/full_repos/permissive/466874195/calc_ck.sv\n             calc_ck\n             calc_ck.v\n             calc_ck.sv\n             obj_dir/calc_ck\n             obj_dir/calc_ck.v\n             obj_dir/calc_ck.sv\n%Error: data/full_repos/permissive/466874195/verilog/rtl/calc_ck_split.v:43: Cannot find file containing module: 'calc_ck'\ncalc_ck # (\n^~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module calc_ck_split #
(
    parameter SEQ_WIDTH = 40,
    parameter STAGE_WIDTH = 20
)
(
    input  wire                     clk,
    input  wire                     rst,

    input  wire [SEQ_WIDTH-1:0]     a,
    input  wire [SEQ_WIDTH-1:0]     b,
    output reg  [7:0]               z
);

localparam integer N_STAGES = $rtoi($ceil($itor(SEQ_WIDTH)/STAGE_WIDTH));
localparam integer LAST_STAGE_WIDTH = SEQ_WIDTH - (N_STAGES-1) * STAGE_WIDTH;

wire [7:0] t [N_STAGES-1:0];

initial begin
    z = 0;
end

genvar ii;
generate
    for (ii = 0; ii < N_STAGES-1; ii = ii + 1) begin
        calc_ck # (
            .SEQ_WIDTH(STAGE_WIDTH)
        ) inst_calc_ck_ii (
            .clk(clk), 
            .rst(rst),

            .a(a[STAGE_WIDTH*ii +: STAGE_WIDTH]),
            .b(b[STAGE_WIDTH*ii +: STAGE_WIDTH]),
            .z(t[ii])
        );
    end
endgenerate

calc_ck # (
    .SEQ_WIDTH(LAST_STAGE_WIDTH)
) inst_calc_ck_last (
    .clk(clk),
    .rst(rst),

    .a(a[SEQ_WIDTH-1 -: LAST_STAGE_WIDTH]),
    .b(b[SEQ_WIDTH-1 -: LAST_STAGE_WIDTH]),
    .z(t[N_STAGES-1])
);

reg [7:0] temp;
integer jj;

always @(posedge clk) begin
    if (rst) begin
        z <= 0;
    end else begin
        temp = 0;

        for (jj = 0; jj < N_STAGES; jj = jj + 1) begin
            temp = temp + t[jj];
        end

        z <= temp;
    end
end

endmodule
module calc_ck_split #
(
    parameter SEQ_WIDTH = 40,
    parameter STAGE_WIDTH = 20
)
(
    input  wire                     clk,
    input  wire                     rst,

    input  wire [SEQ_WIDTH-1:0]     a,
    input  wire [SEQ_WIDTH-1:0]     b,
    output reg  [7:0]               z
);


localparam integer N_STAGES = $rtoi($ceil($itor(SEQ_WIDTH)/STAGE_WIDTH));
localparam integer LAST_STAGE_WIDTH = SEQ_WIDTH - (N_STAGES-1) * STAGE_WIDTH;

wire [7:0] t [N_STAGES-1:0];

initial begin
    z = 0;
end

genvar ii;
generate
    for (ii = 0; ii < N_STAGES-1; ii = ii + 1) begin
        calc_ck # (
            .SEQ_WIDTH(STAGE_WIDTH)
        ) inst_calc_ck_ii (
            .clk(clk), 
            .rst(rst),

            .a(a[STAGE_WIDTH*ii +: STAGE_WIDTH]),
            .b(b[STAGE_WIDTH*ii +: STAGE_WIDTH]),
            .z(t[ii])
        );
    end
endgenerate

calc_ck # (
    .SEQ_WIDTH(LAST_STAGE_WIDTH)
) inst_calc_ck_last (
    .clk(clk),
    .rst(rst),

    .a(a[SEQ_WIDTH-1 -: LAST_STAGE_WIDTH]),
    .b(b[SEQ_WIDTH-1 -: LAST_STAGE_WIDTH]),
    .z(t[N_STAGES-1])
);

reg [7:0] temp;
integer jj;

always @(posedge clk) begin
    if (rst) begin
        z <= 0;
    end else begin
        temp = 0;

        for (jj = 0; jj < N_STAGES; jj = jj + 1) begin
            temp = temp + t[jj];
        end

        z <= temp;
    end
end

endmodule