data/full_repos/permissive/472097485/Chu04/Pwm_02a/SimTest.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu04/Pwm_02a/SimTest.v:22: Unsupported: Ignoring delay on this delayed statement.\n  #(T/2);\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu04/Pwm_02a/SimTest.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #(T/2);\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu04/Pwm_02a/SimTest.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #(T/2)\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/472097485/Chu04/Pwm_02a/SimTest.v:34: Unsupported: Ignoring delay on this delayed statement.\n  #(T*300);\n  ^\n%Error: data/full_repos/permissive/472097485/Chu04/Pwm_02a/SimTest.v:17: Cannot find file containing module: \'Pwm\'\n Pwm pwm( clk, reset, 4\'b0101, r );\n ^~~\n        ... Looked in:\n             data/full_repos/permissive/472097485/Chu04/Pwm_02a,data/full_repos/permissive/472097485/Pwm\n             data/full_repos/permissive/472097485/Chu04/Pwm_02a,data/full_repos/permissive/472097485/Pwm.v\n             data/full_repos/permissive/472097485/Chu04/Pwm_02a,data/full_repos/permissive/472097485/Pwm.sv\n             Pwm\n             Pwm.v\n             Pwm.sv\n             obj_dir/Pwm\n             obj_dir/Pwm.v\n             obj_dir/Pwm.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module SimTest();

	localparam T = 2;


	reg clk, reset;


	wire r;


	Pwm pwm( clk, reset, 4'b0101, r );

	always
	begin
		clk = 1'b1;
		#(T/2);
		clk = 1'b0;
		#(T/2);
	end

	initial begin

		reset = 1'b1;
		#(T/2)
		reset = 1'b0;
		

		#(T*300);
        

		$stop;
	end
      
endmodule
module SimTest();


	localparam T = 2;


	reg clk, reset;


	wire r;


	Pwm pwm( clk, reset, 4'b0101, r );

	always
	begin
		clk = 1'b1;
		#(T/2);
		clk = 1'b0;
		#(T/2);
	end

	initial begin

		reset = 1'b1;
		#(T/2)
		reset = 1'b0;
		

		#(T*300);
        

		$stop;
	end
      
endmodule