data/full_repos/permissive/463395574/forwarding.v
1: b'%Error: data/full_repos/permissive/463395574/forwarding.v:4: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v.v\n             data/full_repos/permissive/463395574,data/full_repos/permissive/463395574/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/463395574/forwarding.v:8: Define or directive not defined: \'`REG_IDX_WIDTH\'\n    input [`REG_IDX_WIDTH-1:0] readAddr1_ID, readAddr2_ID, readAddr1_EX, readAddr2_EX, readAddr2_MEM,\n           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/forwarding.v:9: Define or directive not defined: \'`REG_IDX_WIDTH\'\n    input [`REG_IDX_WIDTH-1:0] writeAddr_MEM, writeAddr_WB,\n           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/463395574/forwarding.v:46: Define or directive not defined: \'`WORD_LEN\'\n    input [`WORD_LEN-1:0] data_ID,   \n           ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/forwarding.v:47: Define or directive not defined: \'`WORD_LEN\'\n    input [`WORD_LEN-1:0] data_MEM,  \n           ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/forwarding.v:48: Define or directive not defined: \'`WORD_LEN\'\n    input [`WORD_LEN-1:0] data_WB,   \n           ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/forwarding.v:51: Define or directive not defined: \'`WORD_LEN\'\n    output reg [`WORD_LEN-1:0] out\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/forwarding.v:64: Define or directive not defined: \'`WORD_LEN\'\n    input [`WORD_LEN-1:0] data_EX,   \n           ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/forwarding.v:65: Define or directive not defined: \'`WORD_LEN\'\n    input [`WORD_LEN-1:0] data_WB,   \n           ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/forwarding.v:68: Define or directive not defined: \'`WORD_LEN\'\n    output [`WORD_LEN-1:0] out\n            ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/forwarding.v:75: Define or directive not defined: \'`WORD_LEN\'\n    input [`WORD_LEN-1:0] data_ID,   \n           ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/forwarding.v:76: Define or directive not defined: \'`WORD_LEN\'\n    input [`WORD_LEN-1:0] data_MEM,  \n           ^~~~~~~~~\n%Error: data/full_repos/permissive/463395574/forwarding.v:79: Define or directive not defined: \'`WORD_LEN\'\n    output [`WORD_LEN-1:0] out\n            ^~~~~~~~~\n%Error: Exiting due to 13 error(s)\n'
module ForwardingUnit (
    input regWrite_MEM, regWrite_WB, memWrite_EX, memWrite_MEM,
    input [`REG_IDX_WIDTH-1:0] readAddr1_ID, readAddr2_ID, readAddr1_EX, readAddr2_EX, readAddr2_MEM,
    input [`REG_IDX_WIDTH-1:0] writeAddr_MEM, writeAddr_WB,

    output reg [1:0] forwardA, forwardB,
    output forwardMEM, forwardR1, forwardR2
);

    wire MEM2ALU_A = regWrite_MEM && readAddr1_EX == writeAddr_MEM;
    wire WB2ALU_A = regWrite_WB && readAddr1_EX == writeAddr_WB;
    wire MEM2ALU_B = regWrite_MEM && readAddr2_EX == writeAddr_MEM && !memWrite_EX;
    wire WB2ALU_B = regWrite_WB && readAddr2_EX == writeAddr_WB && !memWrite_EX;

    assign forwardMEM = regWrite_WB && memWrite_MEM && readAddr2_MEM == writeAddr_WB;

    assign forwardR1 = regWrite_MEM && readAddr1_ID == writeAddr_MEM;
    assign forwardR2 = regWrite_MEM && readAddr2_ID == writeAddr_MEM;

    always @(*) begin

        if (MEM2ALU_A)
            forwardA <= 2'b01;
        else if (WB2ALU_A)
            forwardA <= 2'b10;
        else
            forwardA <= 2'b00;


        if (MEM2ALU_B)
            forwardB <= 2'b01;
        else if (WB2ALU_B)
            forwardB <= 2'b10;
        else
            forwardB <= 2'b00;
    end
endmodule
module ForwardingUnit (
    input regWrite_MEM, regWrite_WB, memWrite_EX, memWrite_MEM,
    input [`REG_IDX_WIDTH-1:0] readAddr1_ID, readAddr2_ID, readAddr1_EX, readAddr2_EX, readAddr2_MEM,
    input [`REG_IDX_WIDTH-1:0] writeAddr_MEM, writeAddr_WB,

    output reg [1:0] forwardA, forwardB,
    output forwardMEM, forwardR1, forwardR2
);


    wire MEM2ALU_A = regWrite_MEM && readAddr1_EX == writeAddr_MEM;
    wire WB2ALU_A = regWrite_WB && readAddr1_EX == writeAddr_WB;
    wire MEM2ALU_B = regWrite_MEM && readAddr2_EX == writeAddr_MEM && !memWrite_EX;
    wire WB2ALU_B = regWrite_WB && readAddr2_EX == writeAddr_WB && !memWrite_EX;

    assign forwardMEM = regWrite_WB && memWrite_MEM && readAddr2_MEM == writeAddr_WB;

    assign forwardR1 = regWrite_MEM && readAddr1_ID == writeAddr_MEM;
    assign forwardR2 = regWrite_MEM && readAddr2_ID == writeAddr_MEM;

    always @(*) begin

        if (MEM2ALU_A)
            forwardA <= 2'b01;
        else if (WB2ALU_A)
            forwardA <= 2'b10;
        else
            forwardA <= 2'b00;


        if (MEM2ALU_B)
            forwardB <= 2'b01;
        else if (WB2ALU_B)
            forwardB <= 2'b10;
        else
            forwardB <= 2'b00;
    end
endmodule