data/full_repos/permissive/43856783/j1_soc/hdl/j1soc_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/j1soc_TB.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #10 sys_rst_i = 0;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/j1soc_TB.v:26: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("j1soc_TB.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/43856783/j1_soc/hdl/j1soc_TB.v:27: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(-1, uut);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/43856783/j1_soc/hdl/j1soc_TB.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #80000 $finish;\n  ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module j1soc_TB ();

reg sys_clk_i, sys_rst_i;
wire  uart_tx, ledout; 

j1soc uut (
	 uart_tx, ledout, sys_clk_i, sys_rst_i, mosi ,miso, sck, sssd_out, pwm , rs, e, data, SCL, SDA, adelante, atras
);

initial begin
  sys_clk_i   = 1;
  sys_rst_i = 1;
  #10 sys_rst_i = 0;

end

always sys_clk_i = #1 ~sys_clk_i;


initial begin: TEST_CASE
  $dumpfile("j1soc_TB.vcd");
  $dumpvars(-1, uut);
  #80000 $finish;
end

endmodule
module j1soc_TB ();


reg sys_clk_i, sys_rst_i;
wire  uart_tx, ledout; 

j1soc uut (
	 uart_tx, ledout, sys_clk_i, sys_rst_i, mosi ,miso, sck, sssd_out, pwm , rs, e, data, SCL, SDA, adelante, atras
);

initial begin
  sys_clk_i   = 1;
  sys_rst_i = 1;
  #10 sys_rst_i = 0;

end

always sys_clk_i = #1 ~sys_clk_i;


initial begin: TEST_CASE
  $dumpfile("j1soc_TB.vcd");
  $dumpvars(-1, uut);
  #80000 $finish;
end

endmodule