data/full_repos/permissive/459838989/rtl/fpga_wrapper/sect233r1_pt_mul_wrapper.v
1: b"%Error: data/full_repos/permissive/459838989/rtl/fpga_wrapper/sect233r1_pt_mul_wrapper.v:38: Cannot find file containing module: 'Synthesis_Harness_Input'\nSynthesis_Harness_Input #(\n^~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/459838989/rtl/fpga_wrapper,data/full_repos/permissive/459838989/Synthesis_Harness_Input\n             data/full_repos/permissive/459838989/rtl/fpga_wrapper,data/full_repos/permissive/459838989/Synthesis_Harness_Input.v\n             data/full_repos/permissive/459838989/rtl/fpga_wrapper,data/full_repos/permissive/459838989/Synthesis_Harness_Input.sv\n             Synthesis_Harness_Input\n             Synthesis_Harness_Input.v\n             Synthesis_Harness_Input.sv\n             obj_dir/Synthesis_Harness_Input\n             obj_dir/Synthesis_Harness_Input.v\n             obj_dir/Synthesis_Harness_Input.sv\n%Error: data/full_repos/permissive/459838989/rtl/fpga_wrapper/sect233r1_pt_mul_wrapper.v:48: Cannot find file containing module: 'Synthesis_Harness_Output'\nSynthesis_Harness_Output #(\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/459838989/rtl/fpga_wrapper/sect233r1_pt_mul_wrapper.v:58: Cannot find file containing module: 'sect233r1_pt_mul'\nsect233r1_pt_mul u_sect233r1_pt_mul (\n^~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module sect233r1_pt_mul_wrapper (

    input clk,
    input test_i,
    output test_o
);


wire rst_n;
wire clr;
wire start;
wire [232:0] d;
wire done;
wire [232:0] x;
wire [232:0] y;
wire [235:0] word_o;
wire [466:0] word_i;



assign {rst_n, clr, start, d} = word_o;
assign word_i = {done, x, y};



Synthesis_Harness_Input #(
    .WORD_WIDTH     (236)
) u_shi (
    .clock          (clk),
    .clear          (1'b0),
    .bit_in         (test_i),
    .bit_in_valid   (1'b1),
    .word_out       (word_o)
);

Synthesis_Harness_Output #(
    .WORD_WIDTH     (467)
) u_sho (
    .clock          (clk),
    .clear          (1'b0),
    .word_in        (word_i),
    .word_in_valid  (1'b1),
    .bit_out        (test_o)
);

sect233r1_pt_mul u_sect233r1_pt_mul (
    .clk            (clk),
    .rst_n          (rst_n),
    .clr            (clr),
    .start          (start),
    .d              (d),
    .done           (done),
    .x              (x),
    .y              (y)
);


endmodule
module sect233r1_pt_mul_wrapper (

    input clk,
    input test_i,
    output test_o
);



wire rst_n;
wire clr;
wire start;
wire [232:0] d;
wire done;
wire [232:0] x;
wire [232:0] y;
wire [235:0] word_o;
wire [466:0] word_i;



assign {rst_n, clr, start, d} = word_o;
assign word_i = {done, x, y};



Synthesis_Harness_Input #(
    .WORD_WIDTH     (236)
) u_shi (
    .clock          (clk),
    .clear          (1'b0),
    .bit_in         (test_i),
    .bit_in_valid   (1'b1),
    .word_out       (word_o)
);

Synthesis_Harness_Output #(
    .WORD_WIDTH     (467)
) u_sho (
    .clock          (clk),
    .clear          (1'b0),
    .word_in        (word_i),
    .word_in_valid  (1'b1),
    .bit_out        (test_o)
);

sect233r1_pt_mul u_sect233r1_pt_mul (
    .clk            (clk),
    .rst_n          (rst_n),
    .clr            (clr),
    .start          (start),
    .d              (d),
    .done           (done),
    .x              (x),
    .y              (y)
);


endmodule