data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\nalways #1 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v:22: Define or directive not defined: \'`outfile\'\n  file = $fopen(`outfile);\n                ^~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v:22: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  file = $fopen(`outfile);\n                        ^\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v:23: syntax error, unexpected \'@\'\n  repeat (5) @ (posedge clk);\n             ^\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v:25: syntax error, unexpected \'@\'\n  repeat (1) @ (posedge clk);\n             ^\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v:27: syntax error, unexpected \'@\'\n  repeat (1) @ (posedge clk);\n             ^\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v:29: syntax error, unexpected \'@\'\n  repeat (1) @ (posedge clk);\n             ^\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v:32: syntax error, unexpected \'@\'\n  repeat (1) @ (posedge clk);\n             ^\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v:35: syntax error, unexpected \'@\'\n  repeat (1) @ (posedge clk);\n             ^\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v:38: syntax error, unexpected \'@\'\n  repeat (1) @ (posedge clk);\n             ^\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v:40: syntax error, unexpected \'@\'\n  repeat (1) @ (posedge clk);\n             ^\n%Error: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v:42: syntax error, unexpected \'@\'\n  repeat (1) @ (posedge clk);\n             ^\n%Warning-STMTDLY: data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n  #10 $finish;\n  ^\n%Error: Exiting due to 11 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench ();

reg             clk = 0;
reg             rst = 1;
reg             req3 = 0;
reg             req2 = 0;
reg             req1 = 0;
reg             req0 = 0;
wire            gnt3;   
wire            gnt2;   
wire            gnt1;   
wire            gnt0;  


always #1 clk = ~clk;
integer file;

always @(posedge clk)
  $fdisplay(file, "%b", {gnt3, gnt2, gnt1, gnt0});

initial begin
  file = $fopen(`outfile);
  repeat (5) @ (posedge clk);
  rst <= 0;
  repeat (1) @ (posedge clk);
  req0 <= 1;
  repeat (1) @ (posedge clk);
  req0 <= 0;
  repeat (1) @ (posedge clk);
  req0 <= 1;
  req1 <= 1;
  repeat (1) @ (posedge clk);
  req2 <= 1;
  req1 <= 0;
  repeat (1) @ (posedge clk);
  req3 <= 1;
  req2 <= 0;
  repeat (1) @ (posedge clk);
  req3 <= 0;
  repeat (1) @ (posedge clk);
  req0 <= 0;
  repeat (1) @ (posedge clk);
  #10 $finish;
end 


arbiter U (
 clk,    
 rst,    
 req3,   
 req2,   
 req1,   
 req0,   
 gnt3,   
 gnt2,   
 gnt1,   
 gnt0   
);

endmodule
module testbench ();


reg             clk = 0;
reg             rst = 1;
reg             req3 = 0;
reg             req2 = 0;
reg             req1 = 0;
reg             req0 = 0;
wire            gnt3;   
wire            gnt2;   
wire            gnt1;   
wire            gnt0;  


always #1 clk = ~clk;
integer file;

always @(posedge clk)
  $fdisplay(file, "%b", {gnt3, gnt2, gnt1, gnt0});

initial begin
  file = $fopen(`outfile);
  repeat (5) @ (posedge clk);
  rst <= 0;
  repeat (1) @ (posedge clk);
  req0 <= 1;
  repeat (1) @ (posedge clk);
  req0 <= 0;
  repeat (1) @ (posedge clk);
  req0 <= 1;
  req1 <= 1;
  repeat (1) @ (posedge clk);
  req2 <= 1;
  req1 <= 0;
  repeat (1) @ (posedge clk);
  req3 <= 1;
  req2 <= 0;
  repeat (1) @ (posedge clk);
  req3 <= 0;
  repeat (1) @ (posedge clk);
  req0 <= 0;
  repeat (1) @ (posedge clk);
  #10 $finish;
end 


arbiter U (
 clk,    
 rst,    
 req3,   
 req2,   
 req1,   
 req0,   
 gnt3,   
 gnt2,   
 gnt1,   
 gnt0   
);

endmodule