data/full_repos/permissive/447976230/fpga/usrp2/control_lib/double_buffer_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/double_buffer_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n   initial #1000 rst = 0;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/double_buffer_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n   always #50 clk = ~clk;\n          ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/double_buffer_tb.v:63: Unsupported or unknown PLI call: $dumpfile\n   initial $dumpfile("double_buffer_tb.vcd");\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/double_buffer_tb.v:64: Unsupported or unknown PLI call: $dumpvars\n   initial $dumpvars(0,double_buffer_tb);\n           ^~~~~~~~~\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/double_buffer_tb.v:68: syntax error, unexpected \'@\'\n @(negedge rst);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/double_buffer_tb.v:94: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/double_buffer_tb.v:195: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/double_buffer_tb.v:220: syntax error, unexpected \'@\'\n   @(posedge clk);\n   ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/double_buffer_tb.v:270: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/double_buffer_tb.v:272: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/double_buffer_tb.v:274: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/double_buffer_tb.v:279: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/double_buffer_tb.v:281: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/double_buffer_tb.v:283: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/double_buffer_tb.v:285: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/double_buffer_tb.v:287: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/double_buffer_tb.v:290: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/double_buffer_tb.v:292: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/double_buffer_tb.v:294: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/double_buffer_tb.v:299: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/double_buffer_tb.v:301: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/double_buffer_tb.v:303: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/double_buffer_tb.v:305: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/double_buffer_tb.v:307: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/447976230/fpga/usrp2/control_lib/double_buffer_tb.v:311: Unsupported: Ignoring delay on this delayed statement.\n   initial #28000 $finish;\n           ^\n%Error: Exiting due to 22 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module double_buffer_tb();
   
   reg clk = 0;
   reg rst = 1;
   reg clear = 0;
   initial #1000 rst = 0;
   always #50 clk = ~clk;

   wire src_rdy_o;
   reg src_rdy_i = 0;
   wire dst_rdy_o;
   
   wire dst_rdy_i = 0;
   wire [35:0] data_o;
   reg [35:0]  data_i;

   wire        access_we, access_stb, access_done, access_ok, access_skip_read;

   wire [8:0]  access_adr, access_len;
   wire [35:0] dsp_to_buf, buf_to_dsp;
   reg 	       set_stb = 0;
   
   double_buffer db
     (.clk(clk),.reset(rst),.clear(0),
      .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), 
      .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), 
      .access_dat_i(dsp_to_buf), .access_dat_o(buf_to_dsp),

      .data_i(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
      .data_o(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i));

   dspengine_8to16 #(.HEADER_OFFSET(1)) dspengine_8to16
     (.clk(clk),.reset(rst),.clear(0),
      .set_stb(set_stb), .set_addr(0), .set_data(1),
      .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), 
      .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), 
      .access_dat_i(buf_to_dsp), .access_dat_o(dsp_to_buf));
   
   always @(posedge clk)
     if(src_rdy_o & dst_rdy_i)
       begin
	  $display("SOF %d, EOF %d, OCC %x, DAT %x",data_o[32],data_o[33],data_o[35:34],data_o[31:0]);
	  if(data_o[33])
	    $display();
       end	  
   initial $dumpfile("double_buffer_tb.vcd");
   initial $dumpvars(0,double_buffer_tb);

   initial
     begin
	@(negedge rst);
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);

	$display("Enabled");
	set_stb <= 1;
	@(posedge clk);
	set_stb <= 0;


	while(~dst_rdy_o)
	  @(posedge clk);

	while(~dst_rdy_o)
	  @(posedge clk);


	$display("StreamID, Trailer, Odd");
	src_rdy_i <= 1;
  	data_i <= { 2'b00,1'b0,1'b1,32'hABCDEF98};
	@(posedge clk);
  	data_i <= { 2'b00,1'b0,1'b0,32'h1c034567};
	@(posedge clk);
	data_i <= { 2'b00,1'b0,1'b0,32'ha0a1a2a3};
	@(posedge clk);
	data_i <= { 2'b00,1'b0,1'b0,32'ha4a5a6a7};



	@(posedge clk);
	data_i <= { 2'b00,1'b0,1'b0,32'ha8a9aaab};
	@(posedge clk);
	data_i <= { 2'b00,1'b0,1'b0,32'hacadaeaf};
	@(posedge clk);
	data_i <= { 2'b00,1'b1,1'b0,32'hdeadbeef};
	@(posedge clk);
	src_rdy_i <= 0;
	@(posedge clk);
	src_rdy_i <= 1;
  	data_i <= { 2'b00,1'b0,1'b1,32'hABCDEF98};
	@(posedge clk);
  	data_i <= { 2'b00,1'b0,1'b0,32'h1c034567};
	@(posedge clk);
	data_i <= { 2'b00,1'b0,1'b0,32'ha0a1a2a3};
	@(posedge clk);
	data_i <= { 2'b00,1'b0,1'b0,32'ha4a5a6a7};



	@(posedge clk);
	data_i <= { 2'b00,1'b0,1'b0,32'ha8a9aaab};
	@(posedge clk);
	data_i <= { 2'b00,1'b0,1'b0,32'hacadaeaf};
	@(posedge clk);
	data_i <= { 2'b00,1'b1,1'b0,32'hdeadbeef};
	@(posedge clk);
	src_rdy_i <= 0;
	@(posedge clk);

     end
   
   initial #28000 $finish;
endmodule
module double_buffer_tb();

   
   reg clk = 0;
   reg rst = 1;
   reg clear = 0;
   initial #1000 rst = 0;
   always #50 clk = ~clk;

   wire src_rdy_o;
   reg src_rdy_i = 0;
   wire dst_rdy_o;
   
   wire dst_rdy_i = 0;
   wire [35:0] data_o;
   reg [35:0]  data_i;

   wire        access_we, access_stb, access_done, access_ok, access_skip_read;

   wire [8:0]  access_adr, access_len;
   wire [35:0] dsp_to_buf, buf_to_dsp;
   reg 	       set_stb = 0;
   
   double_buffer db
     (.clk(clk),.reset(rst),.clear(0),
      .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), 
      .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), 
      .access_dat_i(dsp_to_buf), .access_dat_o(buf_to_dsp),

      .data_i(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
      .data_o(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i));

   dspengine_8to16 #(.HEADER_OFFSET(1)) dspengine_8to16
     (.clk(clk),.reset(rst),.clear(0),
      .set_stb(set_stb), .set_addr(0), .set_data(1),
      .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), 
      .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), 
      .access_dat_i(buf_to_dsp), .access_dat_o(dsp_to_buf));
   
   always @(posedge clk)
     if(src_rdy_o & dst_rdy_i)
       begin
	  $display("SOF %d, EOF %d, OCC %x, DAT %x",data_o[32],data_o[33],data_o[35:34],data_o[31:0]);
	  if(data_o[33])
	    $display();
       end	  
   initial $dumpfile("double_buffer_tb.vcd");
   initial $dumpvars(0,double_buffer_tb);

   initial
     begin
	@(negedge rst);
	@(posedge clk);
	@(posedge clk);
	@(posedge clk);

	$display("Enabled");
	set_stb <= 1;
	@(posedge clk);
	set_stb <= 0;


	while(~dst_rdy_o)
	  @(posedge clk);

	while(~dst_rdy_o)
	  @(posedge clk);


	$display("StreamID, Trailer, Odd");
	src_rdy_i <= 1;
  	data_i <= { 2'b00,1'b0,1'b1,32'hABCDEF98};
	@(posedge clk);
  	data_i <= { 2'b00,1'b0,1'b0,32'h1c034567};
	@(posedge clk);
	data_i <= { 2'b00,1'b0,1'b0,32'ha0a1a2a3};
	@(posedge clk);
	data_i <= { 2'b00,1'b0,1'b0,32'ha4a5a6a7};



	@(posedge clk);
	data_i <= { 2'b00,1'b0,1'b0,32'ha8a9aaab};
	@(posedge clk);
	data_i <= { 2'b00,1'b0,1'b0,32'hacadaeaf};
	@(posedge clk);
	data_i <= { 2'b00,1'b1,1'b0,32'hdeadbeef};
	@(posedge clk);
	src_rdy_i <= 0;
	@(posedge clk);
	src_rdy_i <= 1;
  	data_i <= { 2'b00,1'b0,1'b1,32'hABCDEF98};
	@(posedge clk);
  	data_i <= { 2'b00,1'b0,1'b0,32'h1c034567};
	@(posedge clk);
	data_i <= { 2'b00,1'b0,1'b0,32'ha0a1a2a3};
	@(posedge clk);
	data_i <= { 2'b00,1'b0,1'b0,32'ha4a5a6a7};



	@(posedge clk);
	data_i <= { 2'b00,1'b0,1'b0,32'ha8a9aaab};
	@(posedge clk);
	data_i <= { 2'b00,1'b0,1'b0,32'hacadaeaf};
	@(posedge clk);
	data_i <= { 2'b00,1'b1,1'b0,32'hdeadbeef};
	@(posedge clk);
	src_rdy_i <= 0;
	@(posedge clk);

     end
   
   initial #28000 $finish;
endmodule