data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Vivado/Arty7/USTCRVSoC-Arty7.srcs/sources_1/new/Arty7_USTCRVSoC_top.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Vivado/Arty7/USTCRVSoC-Arty7.srcs/sources_1/new/Arty7_USTCRVSoC_top.sv:10: Operator ASSIGN expects 27 bits on the Assign RHS, but Assign RHS\'s CONST \'22\'h0\' generates 22 bits.\n                                                                                                                                                             : ... In instance Arty7_USTCRVSoC_top\nlogic [26:0] cnt  = 22\'h0;\n                    ^~~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Vivado/Arty7/USTCRVSoC-Arty7.srcs/sources_1/new/Arty7_USTCRVSoC_top.sv:12: Cannot find file containing module: \'soc_top\'\nsoc_top  #(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Vivado/Arty7/USTCRVSoC-Arty7.srcs/sources_1/new,data/full_repos/permissive/435890256/soc_top\n             data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Vivado/Arty7/USTCRVSoC-Arty7.srcs/sources_1/new,data/full_repos/permissive/435890256/soc_top.v\n             data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Vivado/Arty7/USTCRVSoC-Arty7.srcs/sources_1/new,data/full_repos/permissive/435890256/soc_top.sv\n             soc_top\n             soc_top.v\n             soc_top.sv\n             obj_dir/soc_top\n             obj_dir/soc_top.v\n             obj_dir/soc_top.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module Arty7_USTCRVSoC_top(
    input  logic CLK100MHZ,
    output logic [3:0] LED,
    output logic [1:0] LEDB,
    output logic UART_TX,
    input  logic UART_RX
);

logic [26:0] cnt  = 22'h0;

soc_top  #(
    .UART_RX_CLK_DIV  ( 217       ),
    .UART_TX_CLK_DIV  ( 868       ),
    .VGA_CLK_DIV      ( 2         )
)soc_inst (
    .clk              ( CLK100MHZ ),
    .isp_uart_rx      ( UART_RX   ),
    .isp_uart_tx      ( UART_TX   ),
    .vga_hsync        (           ),
    .vga_vsync        (           ),
    .vga_red          (           ),
    .vga_green        (           ),
    .vga_blue         (           )
);


assign LEDB = ~{UART_RX, UART_TX};


always @ (posedge CLK100MHZ) begin
    case(cnt[26:24])
    3'd0 : LED <= 4'b0001;
    3'd1 : LED <= 4'b0010;
    3'd2 : LED <= 4'b0100;
    3'd3 : LED <= 4'b1000;
    3'd4 : LED <= 4'b1000;
    3'd5 : LED <= 4'b0100;
    3'd6 : LED <= 4'b0010;
    3'd7 : LED <= 4'b0001;
    endcase
    cnt++;
end

endmodule
module Arty7_USTCRVSoC_top(
    input  logic CLK100MHZ,
    output logic [3:0] LED,
    output logic [1:0] LEDB,
    output logic UART_TX,
    input  logic UART_RX
);


logic [26:0] cnt  = 22'h0;

soc_top  #(
    .UART_RX_CLK_DIV  ( 217       ),
    .UART_TX_CLK_DIV  ( 868       ),
    .VGA_CLK_DIV      ( 2         )
)soc_inst (
    .clk              ( CLK100MHZ ),
    .isp_uart_rx      ( UART_RX   ),
    .isp_uart_tx      ( UART_TX   ),
    .vga_hsync        (           ),
    .vga_vsync        (           ),
    .vga_red          (           ),
    .vga_green        (           ),
    .vga_blue         (           )
);


assign LEDB = ~{UART_RX, UART_TX};


always @ (posedge CLK100MHZ) begin
    case(cnt[26:24])
    3'd0 : LED <= 4'b0001;
    3'd1 : LED <= 4'b0010;
    3'd2 : LED <= 4'b0100;
    3'd3 : LED <= 4'b1000;
    3'd4 : LED <= 4'b1000;
    3'd5 : LED <= 4'b0100;
    3'd6 : LED <= 4'b0010;
    3'd7 : LED <= 4'b0001;
    endcase
    cnt++;
end

endmodule