data/full_repos/permissive/493019833/test/testcase/firrtl/NestedModsWithReg/reference/NestedModsWithReg.v
data/verilator_xmls/df9e1374-d511-4bee-a424-b81a16869189.xml
module Level2(
    input clk,
    input reset,
    input [15:0] in1,
    output [15:0] out2,
    output [15:0] out3
);
    wire [15:0] _reg2__q;
    wire [15:0] _reg2__d;
    DFF_POSCLK #(.width(16)) reg2 (
        .q(_reg2__q),
        .d(_reg2__d),
        .clk(clk)
    );
    wire _level3__clk;
    wire _level3__reset;
    wire [15:0] _level3__in1;
    wire [15:0] _level3__out3;
    Level3 level3 (
        .clk(_level3__clk),
        .reset(_level3__reset),
        .in1(_level3__in1),
        .out3(_level3__out3)
    );
    assign _level3__clk = clk;
    assign _level3__in1 = in1;
    assign _level3__reset = reset;
    assign out2 = _reg2__q;
    assign out3 = _level3__out3;
    assign _reg2__d = in1;
endmodule
module Level2(
    input clk,
    input reset,
    input [15:0] in1,
    output [15:0] out2,
    output [15:0] out3
);

    wire [15:0] _reg2__q;
    wire [15:0] _reg2__d;
    DFF_POSCLK #(.width(16)) reg2 (
        .q(_reg2__q),
        .d(_reg2__d),
        .clk(clk)
    );
    wire _level3__clk;
    wire _level3__reset;
    wire [15:0] _level3__in1;
    wire [15:0] _level3__out3;
    Level3 level3 (
        .clk(_level3__clk),
        .reset(_level3__reset),
        .in1(_level3__in1),
        .out3(_level3__out3)
    );
    assign _level3__clk = clk;
    assign _level3__in1 = in1;
    assign _level3__reset = reset;
    assign out2 = _reg2__q;
    assign out3 = _level3__out3;
    assign _reg2__d = in1;
endmodule