data/full_repos/permissive/423547971/Verilog Introductory Tutorial Book/mod100_counterEX.v
1: b'%Error: Cannot find file containing module: Introductory\n        ... Looked in:\n             data/full_repos/permissive/423547971/Verilog/Introductory\n             data/full_repos/permissive/423547971/Verilog/Introductory.v\n             data/full_repos/permissive/423547971/Verilog/Introductory.sv\n             Introductory\n             Introductory.v\n             Introductory.sv\n             obj_dir/Introductory\n             obj_dir/Introductory.v\n             obj_dir/Introductory.sv\n%Error: Cannot find file containing module: Tutorial\n%Error: Cannot find file containing module: Book,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/Verilog\n%Error: Cannot find file containing module: Book/mod100_counterEX.v\n%Error: Exiting due to 5 error(s)\n'
module mod100_counter(

	input CLOCK,
	input RESET,

	output reg sig100 = 1'b0
);

reg [6:0] counter100 = 0;


always @ (posedge CLOCK) begin
	if (RESET) 
		counter100 <= 0;
	else 
		if (counter100 == 99)
			counter100 <= 0;
		else
			counter100 <= counter100 + 1;
end


always @ (posedge CLOCK) begin
	if (counter100 == 98)
		sig100 <= 1;
	else
		sig100 <= 0;
end

endmodule
module mod100_counter(

	input CLOCK,
	input RESET,

	output reg sig100 = 1'b0
);


reg [6:0] counter100 = 0;


always @ (posedge CLOCK) begin
	if (RESET) 
		counter100 <= 0;
	else 
		if (counter100 == 99)
			counter100 <= 0;
		else
			counter100 <= counter100 + 1;
end


always @ (posedge CLOCK) begin
	if (counter100 == 98)
		sig100 <= 1;
	else
		sig100 <= 0;
end

endmodule