data/full_repos/permissive/507506290/RTL_Files/MUX_MEM.v
data/verilator_xmls/ededb3e2-bf59-46e6-ae0a-5dbdd4c6db0d.xml
module MUX_MEM(i_pc_in , o_alu_branch  , i_sel_mem  , o_mem);
input [`WIDTH_MEM-1:0] i_pc_in  ;
input [`WIDTH_MEM-1:0]  o_alu_branch ;
input  i_sel_mem;
output [`WIDTH_MEM-1:0] o_mem ;

assign o_mem = i_sel_mem? o_alu_branch : i_pc_in ;

endmodule
module MUX_MEM(i_pc_in , o_alu_branch  , i_sel_mem  , o_mem);

input [`WIDTH_MEM-1:0] i_pc_in  ;
input [`WIDTH_MEM-1:0]  o_alu_branch ;
input  i_sel_mem;
output [`WIDTH_MEM-1:0] o_mem ;

assign o_mem = i_sel_mem? o_alu_branch : i_pc_in ;

endmodule