data/full_repos/permissive/405799749/amg_new2/adder/FSA_16_64_Carry_select_adder.v
data/verilator_xmls/a1e22f4f-1bee-4d86-a007-eae88622d5c2.xml
module UBRCB_63_56 (Co, S, X, Y, Ci);
  output Co;
  output [63:56] S;
  input Ci;
  input [63:56] X;
  input [63:56] Y;
  wire C57;
  wire C58;
  wire C59;
  wire C60;
  wire C61;
  wire C62;
  wire C63;
  UBFA_56 U0 (C57, S[56], X[56], Y[56], Ci);
  UBFA_57 U1 (C58, S[57], X[57], Y[57], C57);
  UBFA_58 U2 (C59, S[58], X[58], Y[58], C58);
  UBFA_59 U3 (C60, S[59], X[59], Y[59], C59);
  UBFA_60 U4 (C61, S[60], X[60], Y[60], C60);
  UBFA_61 U5 (C62, S[61], X[61], Y[61], C61);
  UBFA_62 U6 (C63, S[62], X[62], Y[62], C62);
  UBFA_63 U7 (Co, S[63], X[63], Y[63], C63);
endmodule
module UBRCB_63_56 (Co, S, X, Y, Ci);

  output Co;
  output [63:56] S;
  input Ci;
  input [63:56] X;
  input [63:56] Y;
  wire C57;
  wire C58;
  wire C59;
  wire C60;
  wire C61;
  wire C62;
  wire C63;
  UBFA_56 U0 (C57, S[56], X[56], Y[56], Ci);
  UBFA_57 U1 (C58, S[57], X[57], Y[57], C57);
  UBFA_58 U2 (C59, S[58], X[58], Y[58], C58);
  UBFA_59 U3 (C60, S[59], X[59], Y[59], C59);
  UBFA_60 U4 (C61, S[60], X[60], Y[60], C60);
  UBFA_61 U5 (C62, S[61], X[61], Y[61], C61);
  UBFA_62 U6 (C63, S[62], X[62], Y[62], C62);
  UBFA_63 U7 (Co, S[63], X[63], Y[63], C63);
endmodule