data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/More Verilog Features/Reduction operators.v
1: b'%Error: Cannot find file containing module: Verilog\n        ... Looked in:\n             data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/More/Verilog\n             data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/More/Verilog.v\n             data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/More/Verilog.sv\n             Verilog\n             Verilog.v\n             Verilog.sv\n             obj_dir/Verilog\n             obj_dir/Verilog.v\n             obj_dir/Verilog.sv\n%Error: Cannot find file containing module: Features,data/full_repos/permissive/463549945\n%Error: Cannot find file containing module: data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/More\n%Error: Cannot find file containing module: Features/Reduction\n%Error: Cannot find file containing module: operators.v\n%Error: Exiting due to 5 error(s)\n'
module top_module (
    input [7:0] in,
    output parity); 

    assign parity = ^ in [7:0];
    
endmodule
module top_module (
    input [7:0] in,
    output parity);
 

    assign parity = ^ in [7:0];
    
endmodule