data/full_repos/permissive/496508301/Lesson10/UART_TX.v
data/verilator_xmls/354d0388-6c61-4de9-bf94-a1f1cb3af9d8.xml
module UART_TX(
            clk,
            res,
            data_in,
            en_data_in,
            TX,
            rdy
);
input       clk;
input       res;
input[7:0]  data_in;
input       en_data_in;
output      TX;
output      rdy;

reg[3:0]    state;
reg[9:0]    send_buffer;
assign      TX = send_buffer[0];
reg[12:0]   con;
reg[9:0]    send_flg;
reg         rdy;
always @(posedge clk or negedge res) begin
    if (~res)begin
        state <= 0; send_buffer <= 1; con <= 0; send_flg <= 10'b10_0000_0000; rdy = 0;
    end
    else begin
        case(state)
            0:
            begin
                if(en_data_in) begin
                    send_buffer <= {1'b1, data_in, 1'b0};
                    send_flg    <= 10'b10_0000_0000;
                    state       <= 1; 
                    rdy         <= 1;
                end
            end
            1:
            begin
                if(con == 4999)begin
                    con <= 0;
                end
                else begin
                    con <= con+1;
                end
                if (con == 4999) begin

                    send_buffer[8:0] <= send_buffer[9:1];  
                    send_flg[8:0]    <= send_flg[9:1];
                end
                if(send_flg[0] == 1)begin
                    rdy   <= 0;
                    state <= 0;
                end
            end
            default:
            begin
                state <= 0;
            end
        endcase
    end
end
endmodule
module UART_TX(
            clk,
            res,
            data_in,
            en_data_in,
            TX,
            rdy
);

input       clk;
input       res;
input[7:0]  data_in;
input       en_data_in;
output      TX;
output      rdy;

reg[3:0]    state;
reg[9:0]    send_buffer;
assign      TX = send_buffer[0];
reg[12:0]   con;
reg[9:0]    send_flg;
reg         rdy;
always @(posedge clk or negedge res) begin
    if (~res)begin
        state <= 0; send_buffer <= 1; con <= 0; send_flg <= 10'b10_0000_0000; rdy = 0;
    end
    else begin
        case(state)
            0:
            begin
                if(en_data_in) begin
                    send_buffer <= {1'b1, data_in, 1'b0};
                    send_flg    <= 10'b10_0000_0000;
                    state       <= 1; 
                    rdy         <= 1;
                end
            end
            1:
            begin
                if(con == 4999)begin
                    con <= 0;
                end
                else begin
                    con <= con+1;
                end
                if (con == 4999) begin

                    send_buffer[8:0] <= send_buffer[9:1];  
                    send_flg[8:0]    <= send_flg[9:1];
                end
                if(send_flg[0] == 1)begin
                    rdy   <= 0;
                    state <= 0;
                end
            end
            default:
            begin
                state <= 0;
            end
        endcase
    end
end
endmodule