data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_explicit_mem/bdw_work/modules/dut/BASIC/v_rtl/dut_Add_9Sx9S_10S_1.v
data/verilator_xmls/5aac16ce-511a-4f2f-b858-29b163198064.xml
module dut_Add_9Sx9S_10S_1 (
	in2,
	in1,
	out1
	);
input [8:0] in2,
	in1;
output [9:0] out1;
wire [9:0] asc001;

assign asc001 = 
	+({in2[8], in2})
	+({in1[8], in1});

assign out1 = asc001;
endmodule
module dut_Add_9Sx9S_10S_1 (
	in2,
	in1,
	out1
	);

input [8:0] in2,
	in1;
output [9:0] out1;
wire [9:0] asc001;

assign asc001 = 
	+({in2[8], in2})
	+({in1[8], in1});

assign out1 = asc001;
endmodule