data/full_repos/permissive/458737381/src/verilog-parser/tests/std-3.10.3.1.1-array-declaration.v
data/verilator_xmls/13cad34a-fa57-4cb5-872d-658f827955a2.xml
module test;
reg [7:0] mema[0:255];
reg arrayb[7:0][0:255];
wire w_array[7:0][5:0];
integer inta[1:64];
time chng_hist[1:1000];
integer t_index;
endmodule
module test;

reg [7:0] mema[0:255];
reg arrayb[7:0][0:255];
wire w_array[7:0][5:0];
integer inta[1:64];
time chng_hist[1:1000];
integer t_index;
endmodule