data/full_repos/permissive/448204225/src/riscv_core/PC.v
1: b"%Error: data/full_repos/permissive/448204225/src/riscv_core/PC.v:18: Cannot find file containing module: 'REGISTER_R_CE'\n  REGISTER_R_CE #(\n  ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/448204225/src/riscv_core,data/full_repos/permissive/448204225/REGISTER_R_CE\n             data/full_repos/permissive/448204225/src/riscv_core,data/full_repos/permissive/448204225/REGISTER_R_CE.v\n             data/full_repos/permissive/448204225/src/riscv_core,data/full_repos/permissive/448204225/REGISTER_R_CE.sv\n             REGISTER_R_CE\n             REGISTER_R_CE.v\n             REGISTER_R_CE.sv\n             obj_dir/REGISTER_R_CE\n             obj_dir/REGISTER_R_CE.v\n             obj_dir/REGISTER_R_CE.sv\n%Error: Exiting due to 1 error(s)\n"
module PC #(
  parameter PC_WIDTH = 32,
  parameter RESET_PC_VAL = {{(PC_WIDTH){1'b0}}}
) (
  input clk,
  input rst,
  input pc_sel_in,
  input pc_en,
  input [PC_WIDTH - 1 : 0] pc_new_in,
  output [PC_WIDTH - 1 : 0] pc_out
);

  wire [PC_WIDTH - 1 : 0] pc_value, pc_next;
  wire pc_rst;

  REGISTER_R_CE #(
    .N(PC_WIDTH),
    .INIT(RESET_PC_VAL)
  ) pc (
    .clk(clk),
    .rst(rst),
    .ce (pc_en),
    .d  (pc_next),
    .q  (pc_value)
  );



  assign pc_next = pc_sel_in ? pc_new_in : pc_value + 4;
  assign pc_out  = pc_value;

endmodule
module PC #(
  parameter PC_WIDTH = 32,
  parameter RESET_PC_VAL = {{(PC_WIDTH){1'b0}}}
) (
  input clk,
  input rst,
  input pc_sel_in,
  input pc_en,
  input [PC_WIDTH - 1 : 0] pc_new_in,
  output [PC_WIDTH - 1 : 0] pc_out
);


  wire [PC_WIDTH - 1 : 0] pc_value, pc_next;
  wire pc_rst;

  REGISTER_R_CE #(
    .N(PC_WIDTH),
    .INIT(RESET_PC_VAL)
  ) pc (
    .clk(clk),
    .rst(rst),
    .ce (pc_en),
    .d  (pc_next),
    .q  (pc_value)
  );



  assign pc_next = pc_sel_in ? pc_new_in : pc_value + 4;
  assign pc_out  = pc_value;

endmodule