data/full_repos/permissive/441359809/src/yosys/tests/sat/share.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/tests/sat/share.v:12: Multiple top level modules\n                                                                                      : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                      : ... Top module \'test_1\'\nmodule test_1(\n       ^~~~~~\n                                                                                      : ... Top module \'test_2\'\nmodule test_2(\n       ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/sat/share.v:18: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n                                                                                   : ... In instance test_2\n  y <= \'bx;\n    ^~\n%Error: Exiting due to 2 warning(s)\n'
module test_2(
	input s,
	input [7:0] a, b, c,
	output reg [7:0] y
);
	always @* begin
		y <= 'bx;
		if (s) begin
			if (a * b > 8)
				y <= b / c;
			else
				y <= c / b;
		end else begin
			if (b * c > 8)
				y <= a / b;
			else
				y <= b / a;
		end
	end
endmodule
module test_2(
	input s,
	input [7:0] a, b, c,
	output reg [7:0] y
);

	always @* begin
		y <= 'bx;
		if (s) begin
			if (a * b > 8)
				y <= b / c;
			else
				y <= c / b;
		end else begin
			if (b * c > 8)
				y <= a / b;
			else
				y <= b / a;
		end
	end
endmodule