data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v
1: b'%Error: data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v:45: Cannot find include file: i2cSlave_define.v\n`include "i2cSlave_define.v" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb,data/full_repos/permissive/456317201/i2cSlave_define.v\n             data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb,data/full_repos/permissive/456317201/i2cSlave_define.v.v\n             data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb,data/full_repos/permissive/456317201/i2cSlave_define.v.sv\n             i2cSlave_define.v\n             i2cSlave_define.v.v\n             i2cSlave_define.v.sv\n             obj_dir/i2cSlave_define.v\n             obj_dir/i2cSlave_define.v.v\n             obj_dir/i2cSlave_define.v.sv\n%Error: data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v:84: Define or directive not defined: \'`DEB_I2C_LEN\'\nreg [`DEB_I2C_LEN-1:0] sdaPipe;\n     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v:85: Define or directive not defined: \'`DEB_I2C_LEN\'\nreg [`DEB_I2C_LEN-1:0] sclPipe;\n     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v:87: Define or directive not defined: \'`SCL_DEL_LEN\'\nreg [`SCL_DEL_LEN-1:0] sclDelayed;\n     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v:88: Define or directive not defined: \'`SDA_DEL_LEN\'\nreg [`SDA_DEL_LEN-1:0] sdaDelayed;\n     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v:122: Define or directive not defined: \'`DEB_I2C_LEN\'\n    sdaPipe <= {`DEB_I2C_LEN{1\'b1}};\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v:124: Define or directive not defined: \'`DEB_I2C_LEN\'\n    sclPipe <= {`DEB_I2C_LEN{1\'b1}};\n                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v:128: Define or directive not defined: \'`DEB_I2C_LEN\'\n    sdaPipe <= {sdaPipe[`DEB_I2C_LEN-2:0], sdaIn};\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v:129: Define or directive not defined: \'`DEB_I2C_LEN\'\n    sclPipe <= {sclPipe[`DEB_I2C_LEN-2:0], scl};\n                        ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v:130: Define or directive not defined: \'`DEB_I2C_LEN\'\n    if (&sclPipe[`DEB_I2C_LEN-1:1] == 1\'b1)\n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v:132: Define or directive not defined: \'`DEB_I2C_LEN\'\n    else if (|sclPipe[`DEB_I2C_LEN-1:1] == 1\'b0)\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v:134: Define or directive not defined: \'`DEB_I2C_LEN\'\n    if (&sdaPipe[`DEB_I2C_LEN-1:1] == 1\'b1)\n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v:136: Define or directive not defined: \'`DEB_I2C_LEN\'\n    else if (|sdaPipe[`DEB_I2C_LEN-1:1] == 1\'b0)\n                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v:150: Define or directive not defined: \'`SCL_DEL_LEN\'\n    sclDelayed <= {`SCL_DEL_LEN{1\'b1}};\n                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v:151: Define or directive not defined: \'`SDA_DEL_LEN\'\n    sdaDelayed <= {`SDA_DEL_LEN{1\'b1}};\n                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v:154: Define or directive not defined: \'`SCL_DEL_LEN\'\n    sclDelayed <= {sclDelayed[`SCL_DEL_LEN-2:0], sclDeb};\n                              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v:155: Define or directive not defined: \'`SDA_DEL_LEN\'\n    sdaDelayed <= {sdaDelayed[`SDA_DEL_LEN-2:0], sdaDeb};\n                              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v:162: Define or directive not defined: \'`NULL_DET\'\n    startStopDetState <= `NULL_DET;\n                         ^~~~~~~~~\n%Error: data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v:162: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    startStopDetState <= `NULL_DET;\n                                  ^\n%Error: data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v:166: Define or directive not defined: \'`SDA_DEL_LEN\'\n    if (sclDeb == 1\'b1 && sdaDelayed[`SDA_DEL_LEN-2] == 1\'b0 && sdaDelayed[`SDA_DEL_LEN-1] == 1\'b1)\n                                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v:166: Define or directive not defined: \'`SDA_DEL_LEN\'\n    if (sclDeb == 1\'b1 && sdaDelayed[`SDA_DEL_LEN-2] == 1\'b0 && sdaDelayed[`SDA_DEL_LEN-1] == 1\'b1)\n                                                                           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v:171: Define or directive not defined: \'`NULL_DET\'\n      startStopDetState <= `NULL_DET;\n                           ^~~~~~~~~\n%Error: data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v:171: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      startStopDetState <= `NULL_DET;\n                                    ^\n%Error: data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v:173: Define or directive not defined: \'`SDA_DEL_LEN\'\n      if (sdaDelayed[`SDA_DEL_LEN-2] == 1\'b1 && sdaDelayed[`SDA_DEL_LEN-1] == 1\'b0) \n                     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v:173: Define or directive not defined: \'`SDA_DEL_LEN\'\n      if (sdaDelayed[`SDA_DEL_LEN-2] == 1\'b1 && sdaDelayed[`SDA_DEL_LEN-1] == 1\'b0) \n                                                           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v:174: Define or directive not defined: \'`STOP_DET\'\n        startStopDetState <= `STOP_DET;\n                             ^~~~~~~~~\n%Error: data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v:174: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        startStopDetState <= `STOP_DET;\n                                      ^\n%Error: data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v:175: Define or directive not defined: \'`SDA_DEL_LEN\'\n      else if (sdaDelayed[`SDA_DEL_LEN-2] == 1\'b0 && sdaDelayed[`SDA_DEL_LEN-1] == 1\'b1)\n                          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v:175: Define or directive not defined: \'`SDA_DEL_LEN\'\n      else if (sdaDelayed[`SDA_DEL_LEN-2] == 1\'b0 && sdaDelayed[`SDA_DEL_LEN-1] == 1\'b1)\n                                                                ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v:176: Define or directive not defined: \'`START_DET\'\n        startStopDetState <= `START_DET;\n                             ^~~~~~~~~~\n%Error: data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v:176: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        startStopDetState <= `START_DET;\n                                       ^\n%Error: data/full_repos/permissive/456317201/ve/sv/i2c_initiator_cocotb/i2cSlave.v:205: Define or directive not defined: \'`SCL_DEL_LEN\'\n  .scl(sclDelayed[`SCL_DEL_LEN-1]), \n                  ^~~~~~~~~~~~\n%Error: Exiting due to 32 error(s)\n'
module i2cSlave (
  clk,
  rst,
  sda_o,
  sda_i,
  sda_en_o,
  scl_i,
  myReg0,
  myReg1,
  myReg2,
  myReg3,
  myReg4,
  myReg5,
  myReg6,
  myReg7
);

input clk;
input rst;
output sda_o;
input sda_i;
output sda_en_o;
input scl_i;
output [7:0] myReg0;
output [7:0] myReg1;
output [7:0] myReg2;
output [7:0] myReg3;
input [7:0] myReg4;
input [7:0] myReg5;
input [7:0] myReg6;
input [7:0] myReg7;



reg sdaDeb;
reg sclDeb;
reg [`DEB_I2C_LEN-1:0] sdaPipe;
reg [`DEB_I2C_LEN-1:0] sclPipe;

reg [`SCL_DEL_LEN-1:0] sclDelayed;
reg [`SDA_DEL_LEN-1:0] sdaDelayed;
reg [1:0] startStopDetState;
wire clearStartStopDet;
wire sdaOut;
wire sdaIn;
wire scl;
wire scl_i;
wire [7:0] regAddr;
wire [7:0] dataToRegIF;
wire writeEn;
wire [7:0] dataFromRegIF;
reg [1:0] rstPipe;
wire rstSyncToClk;
reg startEdgeDet;

assign sda_o = sdaOut;
assign sda_en_o = sdaOut;
assign sdaIn = sda_i;

assign scl = scl_i;


always @(posedge clk) begin
  if (rst == 1'b1)
    rstPipe <= 2'b11;
  else
    rstPipe <= {rstPipe[0], 1'b0};
end

assign rstSyncToClk = rstPipe[1];


always @(posedge clk) begin
  if (rstSyncToClk == 1'b1) begin
    sdaPipe <= {`DEB_I2C_LEN{1'b1}};
    sdaDeb <= 1'b1;
    sclPipe <= {`DEB_I2C_LEN{1'b1}};
    sclDeb <= 1'b1;
  end
  else begin
    sdaPipe <= {sdaPipe[`DEB_I2C_LEN-2:0], sdaIn};
    sclPipe <= {sclPipe[`DEB_I2C_LEN-2:0], scl};
    if (&sclPipe[`DEB_I2C_LEN-1:1] == 1'b1)
      sclDeb <= 1'b1;
    else if (|sclPipe[`DEB_I2C_LEN-1:1] == 1'b0)
      sclDeb <= 1'b0;
    if (&sdaPipe[`DEB_I2C_LEN-1:1] == 1'b1)
      sdaDeb <= 1'b1;
    else if (|sdaPipe[`DEB_I2C_LEN-1:1] == 1'b0)
      sdaDeb <= 1'b0;
  end
end








always @(posedge clk) begin
  if (rstSyncToClk == 1'b1) begin
    sclDelayed <= {`SCL_DEL_LEN{1'b1}};
    sdaDelayed <= {`SDA_DEL_LEN{1'b1}};
  end
  else begin
    sclDelayed <= {sclDelayed[`SCL_DEL_LEN-2:0], sclDeb};
    sdaDelayed <= {sdaDelayed[`SDA_DEL_LEN-2:0], sdaDeb};
  end
end


always @(posedge clk) begin
  if (rstSyncToClk == 1'b1) begin
    startStopDetState <= `NULL_DET;
    startEdgeDet <= 1'b0;
  end
  else begin
    if (sclDeb == 1'b1 && sdaDelayed[`SDA_DEL_LEN-2] == 1'b0 && sdaDelayed[`SDA_DEL_LEN-1] == 1'b1)
      startEdgeDet <= 1'b1;
    else
      startEdgeDet <= 1'b0;
    if (clearStartStopDet == 1'b1)
      startStopDetState <= `NULL_DET;
    else if (sclDeb == 1'b1) begin
      if (sdaDelayed[`SDA_DEL_LEN-2] == 1'b1 && sdaDelayed[`SDA_DEL_LEN-1] == 1'b0) 
        startStopDetState <= `STOP_DET;
      else if (sdaDelayed[`SDA_DEL_LEN-2] == 1'b0 && sdaDelayed[`SDA_DEL_LEN-1] == 1'b1)
        startStopDetState <= `START_DET;
    end
  end
end


registerInterface u_registerInterface(
  .clk(clk),
  .addr(regAddr),
  .dataIn(dataToRegIF),
  .writeEn(writeEn),
  .dataOut(dataFromRegIF),
  .myReg0(myReg0),
  .myReg1(myReg1),
  .myReg2(myReg2),
  .myReg3(myReg3),
  .myReg4(myReg4),
  .myReg5(myReg5),
  .myReg6(myReg6),
  .myReg7(myReg7)
);

serialInterface u_serialInterface (
  .clk(clk), 
  .rst(rstSyncToClk | startEdgeDet), 
  .dataIn(dataFromRegIF), 
  .dataOut(dataToRegIF), 
  .writeEn(writeEn),
  .regAddr(regAddr), 
  .scl(sclDelayed[`SCL_DEL_LEN-1]), 
  .sdaIn(sdaDeb), 
  .sdaOut(sdaOut), 
  .startStopDetState(startStopDetState),
  .clearStartStopDet(clearStartStopDet) 
);


endmodule
module i2cSlave (
  clk,
  rst,
  sda_o,
  sda_i,
  sda_en_o,
  scl_i,
  myReg0,
  myReg1,
  myReg2,
  myReg3,
  myReg4,
  myReg5,
  myReg6,
  myReg7
);


input clk;
input rst;
output sda_o;
input sda_i;
output sda_en_o;
input scl_i;
output [7:0] myReg0;
output [7:0] myReg1;
output [7:0] myReg2;
output [7:0] myReg3;
input [7:0] myReg4;
input [7:0] myReg5;
input [7:0] myReg6;
input [7:0] myReg7;



reg sdaDeb;
reg sclDeb;
reg [`DEB_I2C_LEN-1:0] sdaPipe;
reg [`DEB_I2C_LEN-1:0] sclPipe;

reg [`SCL_DEL_LEN-1:0] sclDelayed;
reg [`SDA_DEL_LEN-1:0] sdaDelayed;
reg [1:0] startStopDetState;
wire clearStartStopDet;
wire sdaOut;
wire sdaIn;
wire scl;
wire scl_i;
wire [7:0] regAddr;
wire [7:0] dataToRegIF;
wire writeEn;
wire [7:0] dataFromRegIF;
reg [1:0] rstPipe;
wire rstSyncToClk;
reg startEdgeDet;

assign sda_o = sdaOut;
assign sda_en_o = sdaOut;
assign sdaIn = sda_i;

assign scl = scl_i;


always @(posedge clk) begin
  if (rst == 1'b1)
    rstPipe <= 2'b11;
  else
    rstPipe <= {rstPipe[0], 1'b0};
end

assign rstSyncToClk = rstPipe[1];


always @(posedge clk) begin
  if (rstSyncToClk == 1'b1) begin
    sdaPipe <= {`DEB_I2C_LEN{1'b1}};
    sdaDeb <= 1'b1;
    sclPipe <= {`DEB_I2C_LEN{1'b1}};
    sclDeb <= 1'b1;
  end
  else begin
    sdaPipe <= {sdaPipe[`DEB_I2C_LEN-2:0], sdaIn};
    sclPipe <= {sclPipe[`DEB_I2C_LEN-2:0], scl};
    if (&sclPipe[`DEB_I2C_LEN-1:1] == 1'b1)
      sclDeb <= 1'b1;
    else if (|sclPipe[`DEB_I2C_LEN-1:1] == 1'b0)
      sclDeb <= 1'b0;
    if (&sdaPipe[`DEB_I2C_LEN-1:1] == 1'b1)
      sdaDeb <= 1'b1;
    else if (|sdaPipe[`DEB_I2C_LEN-1:1] == 1'b0)
      sdaDeb <= 1'b0;
  end
end








always @(posedge clk) begin
  if (rstSyncToClk == 1'b1) begin
    sclDelayed <= {`SCL_DEL_LEN{1'b1}};
    sdaDelayed <= {`SDA_DEL_LEN{1'b1}};
  end
  else begin
    sclDelayed <= {sclDelayed[`SCL_DEL_LEN-2:0], sclDeb};
    sdaDelayed <= {sdaDelayed[`SDA_DEL_LEN-2:0], sdaDeb};
  end
end


always @(posedge clk) begin
  if (rstSyncToClk == 1'b1) begin
    startStopDetState <= `NULL_DET;
    startEdgeDet <= 1'b0;
  end
  else begin
    if (sclDeb == 1'b1 && sdaDelayed[`SDA_DEL_LEN-2] == 1'b0 && sdaDelayed[`SDA_DEL_LEN-1] == 1'b1)
      startEdgeDet <= 1'b1;
    else
      startEdgeDet <= 1'b0;
    if (clearStartStopDet == 1'b1)
      startStopDetState <= `NULL_DET;
    else if (sclDeb == 1'b1) begin
      if (sdaDelayed[`SDA_DEL_LEN-2] == 1'b1 && sdaDelayed[`SDA_DEL_LEN-1] == 1'b0) 
        startStopDetState <= `STOP_DET;
      else if (sdaDelayed[`SDA_DEL_LEN-2] == 1'b0 && sdaDelayed[`SDA_DEL_LEN-1] == 1'b1)
        startStopDetState <= `START_DET;
    end
  end
end


registerInterface u_registerInterface(
  .clk(clk),
  .addr(regAddr),
  .dataIn(dataToRegIF),
  .writeEn(writeEn),
  .dataOut(dataFromRegIF),
  .myReg0(myReg0),
  .myReg1(myReg1),
  .myReg2(myReg2),
  .myReg3(myReg3),
  .myReg4(myReg4),
  .myReg5(myReg5),
  .myReg6(myReg6),
  .myReg7(myReg7)
);

serialInterface u_serialInterface (
  .clk(clk), 
  .rst(rstSyncToClk | startEdgeDet), 
  .dataIn(dataFromRegIF), 
  .dataOut(dataToRegIF), 
  .writeEn(writeEn),
  .regAddr(regAddr), 
  .scl(sclDelayed[`SCL_DEL_LEN-1]), 
  .sdaIn(sdaDeb), 
  .sdaOut(sdaOut), 
  .startStopDetState(startStopDetState),
  .clearStartStopDet(clearStartStopDet) 
);


endmodule