data/full_repos/permissive/445695969/src_rtl/protected/dom1/skinny_sbox8_dom1_rapid_non_pipelined.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/445695969/src_rtl/protected/dom1/skinny_sbox8_dom1_rapid_non_pipelined.v:135: Multiple top level modules\n                                                                                                                          : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                                                          : ... Top module \'skinny_sbox8_dom1_rapid_non_pipelined\'\nmodule skinny_sbox8_dom1_rapid_non_pipelined ( \n       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                                                          : ... Top module \'dom1_rpd_sbox8_cfn_fr_ne\'\nmodule dom1_rpd_sbox8_cfn_fr_ne ( \n       ^~~~~~~~~~~~~~~~~~~~~~~~\n                                                                                                                          : ... Top module \'and4_dom1_ne\'\nmodule and4_dom1_ne ( \n       ^~~~~~~~~~~~\n                                                                                                                          : ... Top module \'and3_dom1_ne\'\nmodule and3_dom1_ne ( \n       ^~~~~~~~~~~~\n                                                                                                                          : ... Top module \'and2_dom1_ne\'\nmodule and2_dom1_ne ( \n       ^~~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module skinny_sbox8_dom1_rapid_non_pipelined (

   bo1, bo0,

   si0, si1, r, clk
   ) ;
   (*equivalent_register_removal = "no" *)output [7:0] bo1;
   (*equivalent_register_removal = "no" *)output [7:0] bo0;

   (*equivalent_register_removal = "no" *)input [7:0]  si0, si1;
   (*equivalent_register_removal = "no" *)input [24:0] r;
   (*equivalent_register_removal = "no" *)input        clk;

   wire [1:0]   bi7;
   wire [1:0]   bi6;
   wire [1:0]   bi5;
   wire [1:0]   bi4;
   wire [1:0]   bi3;
   wire [1:0]   bi2;
   wire [1:0]   bi1;
   wire [1:0]   bi0;
   
   wire [1:0] 	nbi7;
   wire [1:0]   nbi6;
   wire [1:0]   nbi5;
   wire [1:0]   nbi4;
   wire [1:0]   nbi3;
   wire [1:0]   nbi2;
   wire [1:0]   nbi1;
   wire [1:0]   nbi0;   

   wire [1:0]   a7;
   wire [1:0]   a6;
   wire [1:0]   a5;
   wire [1:0]   a4;
   wire [1:0]   a3;
   wire [1:0]   a2;
   wire [1:0]   a1;
   wire [1:0]   a0;

   wire [1:0]   na4;
   wire [1:0]   na3;
   wire [1:0]   na2;

   assign bi0 = {si1[0],si0[0]};
   assign bi1 = {si1[1],si0[1]};
   assign bi2 = {si1[2],si0[2]};
   assign bi3 = {si1[3],si0[3]};
   assign bi4 = {si1[4],si0[4]};
   assign bi5 = {si1[5],si0[5]};
   assign bi6 = {si1[6],si0[6]};
   assign bi7 = {si1[7],si0[7]};

   assign nbi0 = {si1[0],~si0[0]};
   assign nbi1 = {si1[1],~si0[1]};
   assign nbi2 = {si1[2],~si0[2]};
   assign nbi3 = {si1[3],~si0[3]};
   assign nbi4 = {si1[4],~si0[4]};
   assign nbi5 = {si1[5],~si0[5]};
   assign nbi6 = {si1[6],~si0[6]};
   assign nbi7 = {si1[7],~si0[7]};

   assign na4 = a4 ^ 2'b01;
   assign na3 = a3 ^ 2'b01;
   assign na2 = a2 ^ 2'b01;

   dom1_rpd_sbox8_cfn_fr b764 (a0,bi7,bi6,bi4,r[0],clk);
   dom1_rpd_sbox8_cfn_fr b320 (a1,bi3,bi2,bi0,r[1],clk);
   dom1_rpd_sbox8_cfn_fr b216 (a2,bi2,bi1,bi6,r[2],clk);
   rapid_a3 a3_cf (a3,nbi7,nbi6,bi5,nbi4,nbi3,nbi2,nbi0,r[16:3],clk);   
   rapid_a4 a4_cf (a4,nbi3,nbi2,bi1,nbi0,r[18:17],clk);
   
   dom1_rpd_sbox8_cfn_fr b237 (a5,a2, a3, bi7,r[19],clk);
   dom1_rpd_sbox8_cfn_fr b303 (a6,a3, a0, bi3,r[20],clk);
   rapid_a7 a7_cf (a7,nbi7,na4,na3,na2,bi2,r[24:21],clk);

   assign {bo1[6],bo0[6]} = a0;
   assign {bo1[5],bo0[5]} = a1;
   assign {bo1[2],bo0[2]} = a2;
   assign {bo1[7],bo0[7]} = a3;
   assign {bo1[3],bo0[3]} = a4;
   assign {bo1[1],bo0[1]} = a5;
   assign {bo1[4],bo0[4]} = a6;
   assign {bo1[0],bo0[0]} = a7;
endmodule
module skinny_sbox8_dom1_rapid_non_pipelined (

   bo1, bo0,

   si0, si1, r, clk
   ) ;

   (*equivalent_register_removal = "no" *)output [7:0] bo1;
   (*equivalent_register_removal = "no" *)output [7:0] bo0;

   (*equivalent_register_removal = "no" *)input [7:0]  si0, si1;
   (*equivalent_register_removal = "no" *)input [24:0] r;
   (*equivalent_register_removal = "no" *)input        clk;

   wire [1:0]   bi7;
   wire [1:0]   bi6;
   wire [1:0]   bi5;
   wire [1:0]   bi4;
   wire [1:0]   bi3;
   wire [1:0]   bi2;
   wire [1:0]   bi1;
   wire [1:0]   bi0;
   
   wire [1:0] 	nbi7;
   wire [1:0]   nbi6;
   wire [1:0]   nbi5;
   wire [1:0]   nbi4;
   wire [1:0]   nbi3;
   wire [1:0]   nbi2;
   wire [1:0]   nbi1;
   wire [1:0]   nbi0;   

   wire [1:0]   a7;
   wire [1:0]   a6;
   wire [1:0]   a5;
   wire [1:0]   a4;
   wire [1:0]   a3;
   wire [1:0]   a2;
   wire [1:0]   a1;
   wire [1:0]   a0;

   wire [1:0]   na4;
   wire [1:0]   na3;
   wire [1:0]   na2;

   assign bi0 = {si1[0],si0[0]};
   assign bi1 = {si1[1],si0[1]};
   assign bi2 = {si1[2],si0[2]};
   assign bi3 = {si1[3],si0[3]};
   assign bi4 = {si1[4],si0[4]};
   assign bi5 = {si1[5],si0[5]};
   assign bi6 = {si1[6],si0[6]};
   assign bi7 = {si1[7],si0[7]};

   assign nbi0 = {si1[0],~si0[0]};
   assign nbi1 = {si1[1],~si0[1]};
   assign nbi2 = {si1[2],~si0[2]};
   assign nbi3 = {si1[3],~si0[3]};
   assign nbi4 = {si1[4],~si0[4]};
   assign nbi5 = {si1[5],~si0[5]};
   assign nbi6 = {si1[6],~si0[6]};
   assign nbi7 = {si1[7],~si0[7]};

   assign na4 = a4 ^ 2'b01;
   assign na3 = a3 ^ 2'b01;
   assign na2 = a2 ^ 2'b01;

   dom1_rpd_sbox8_cfn_fr b764 (a0,bi7,bi6,bi4,r[0],clk);
   dom1_rpd_sbox8_cfn_fr b320 (a1,bi3,bi2,bi0,r[1],clk);
   dom1_rpd_sbox8_cfn_fr b216 (a2,bi2,bi1,bi6,r[2],clk);
   rapid_a3 a3_cf (a3,nbi7,nbi6,bi5,nbi4,nbi3,nbi2,nbi0,r[16:3],clk);   
   rapid_a4 a4_cf (a4,nbi3,nbi2,bi1,nbi0,r[18:17],clk);
   
   dom1_rpd_sbox8_cfn_fr b237 (a5,a2, a3, bi7,r[19],clk);
   dom1_rpd_sbox8_cfn_fr b303 (a6,a3, a0, bi3,r[20],clk);
   rapid_a7 a7_cf (a7,nbi7,na4,na3,na2,bi2,r[24:21],clk);

   assign {bo1[6],bo0[6]} = a0;
   assign {bo1[5],bo0[5]} = a1;
   assign {bo1[2],bo0[2]} = a2;
   assign {bo1[7],bo0[7]} = a3;
   assign {bo1[3],bo0[3]} = a4;
   assign {bo1[1],bo0[1]} = a5;
   assign {bo1[4],bo0[4]} = a6;
   assign {bo1[0],bo0[0]} = a7;
endmodule