data/full_repos/permissive/423262203/rtl/n64rgbv2_top.v
1: b'%Error: data/full_repos/permissive/423262203/rtl/n64rgbv2_top.v:87: Cannot find include file: ../lib/n64rgb_params.vh\n`include "../lib/n64rgb_params.vh" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423262203/rtl,data/full_repos/permissive/423262203/../lib/n64rgb_params.vh\n             data/full_repos/permissive/423262203/rtl,data/full_repos/permissive/423262203/../lib/n64rgb_params.vh.v\n             data/full_repos/permissive/423262203/rtl,data/full_repos/permissive/423262203/../lib/n64rgb_params.vh.sv\n             ../lib/n64rgb_params.vh\n             ../lib/n64rgb_params.vh.v\n             ../lib/n64rgb_params.vh.sv\n             obj_dir/../lib/n64rgb_params.vh\n             obj_dir/../lib/n64rgb_params.vh.v\n             obj_dir/../lib/n64rgb_params.vh.sv\n%Error: data/full_repos/permissive/423262203/rtl/n64rgbv2_top.v:124: Define or directive not defined: \'`VDATA_SY_SLICE\'\nwire [`VDATA_SY_SLICE] vdata_sy_0;\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423262203/rtl/n64rgbv2_top.v:124: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [`VDATA_SY_SLICE] vdata_sy_0;\n                     ^\n%Error: data/full_repos/permissive/423262203/rtl/n64rgbv2_top.v:125: Define or directive not defined: \'`VDATA_FU_SLICE\'\nwire [`VDATA_FU_SLICE] vdata_1;\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423262203/rtl/n64rgbv2_top.v:125: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\nwire [`VDATA_FU_SLICE] vdata_1;\n                     ^\n%Error: data/full_repos/permissive/423262203/rtl/n64rgbv2_top.v:185: Define or directive not defined: \'`VDATA_SY_SLICE\'\n  {nVSYNC,nCLAMP,nHSYNC,nCSYNC} <=  vdata_1[`VDATA_SY_SLICE];\n                                            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423262203/rtl/n64rgbv2_top.v:185: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n  {nVSYNC,nCLAMP,nHSYNC,nCSYNC} <=  vdata_1[`VDATA_SY_SLICE];\n                                                           ^\n%Error: data/full_repos/permissive/423262203/rtl/n64rgbv2_top.v:186: Define or directive not defined: \'`VDATA_RE_SLICE\'\n   R_o                          <= {vdata_1[`VDATA_RE_SLICE],vdata_1[3*color_width-1]};\n                                            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423262203/rtl/n64rgbv2_top.v:186: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   R_o                          <= {vdata_1[`VDATA_RE_SLICE],vdata_1[3*color_width-1]};\n                                                           ^\n%Error: data/full_repos/permissive/423262203/rtl/n64rgbv2_top.v:187: Define or directive not defined: \'`VDATA_GR_SLICE\'\n   G_o                          <= {vdata_1[`VDATA_GR_SLICE],vdata_1[2*color_width-1]};\n                                            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423262203/rtl/n64rgbv2_top.v:187: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   G_o                          <= {vdata_1[`VDATA_GR_SLICE],vdata_1[2*color_width-1]};\n                                                           ^\n%Error: data/full_repos/permissive/423262203/rtl/n64rgbv2_top.v:188: Define or directive not defined: \'`VDATA_BL_SLICE\'\n   B_o                          <= {vdata_1[`VDATA_BL_SLICE],vdata_1[  color_width-1]};\n                                            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423262203/rtl/n64rgbv2_top.v:188: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n   B_o                          <= {vdata_1[`VDATA_BL_SLICE],vdata_1[  color_width-1]};\n                                                           ^\n%Error: Exiting due to 13 error(s)\n'
module n64rgbv2_top (

  VCLK,
  nDSYNC,
  D_i,


  nRST_io,
  CTRL_i,
  


  nSYNC_ON_GREEN,
  n16bit_mode_t,
  nVIDeBlur_t,
  en_IGR_Rst_Func,
  en_IGR_DeBl_16b_Func,


  nHSYNC,
  nVSYNC,
  nCSYNC,
  nCLAMP,

  R_o,
  G_o,
  B_o,

  CLK_ADV712x,
  nCSYNC_ADV712x,
  nBLANK_ADV712x,
  
  dummy_i
);


`include "../lib/n64rgb_params.vh"

input                   VCLK;
input                   nDSYNC;
input [color_width-1:0] D_i;

inout nRST_io;
input CTRL_i;

input  nSYNC_ON_GREEN;

input n16bit_mode_t;
input nVIDeBlur_t;
input en_IGR_Rst_Func;
input en_IGR_DeBl_16b_Func;

output reg nHSYNC;
output reg nVSYNC;
output reg nCSYNC;
output reg nCLAMP;

output reg [color_width:0] R_o;
output reg [color_width:0] G_o;
output reg [color_width:0] B_o;

output reg CLK_ADV712x;
output reg nCSYNC_ADV712x;
output reg nBLANK_ADV712x;

input [4:0] dummy_i;



wire DRV_RST, n16bit_mode_o, nDeBlur_o;
wire nRST_hk, nRST_video;
wire [1:0] vinfo_pass;
wire palmode, n64_480i;
wire [`VDATA_SY_SLICE] vdata_sy_0;
wire [`VDATA_FU_SLICE] vdata_1;

assign nRST_hk = nRST_io;
`ifdef NO_VIDEO_PIPELINE_RESET
  assign nRST_video = 1'b1;
`else
  assign nRST_video = nRST_io;
`endif




n64rgb_hk hk_u(
  .VCLK(VCLK),
  .nRST(nRST_hk),
  .DRV_RST(DRV_RST),
  .CTRL_i(CTRL_i),
  .n64_480i(n64_480i),
  .n16bit_mode_t(n16bit_mode_t),
  .nVIDeBlur_t(nVIDeBlur_t),
  .en_IGR_Rst_Func(en_IGR_Rst_Func),
  .en_IGR_DeBl_16b_Func(en_IGR_DeBl_16b_Func),
  .n16bit_o(n16bit_mode_o),
  .nDeBlur_o(nDeBlur_o)
);





n64_vinfo_ext get_vinfo(
  .VCLK(VCLK),
  .nRST(nRST_video),
  .nDSYNC(nDSYNC),
  .Sync_pre(vdata_sy_0),
  .Sync_cur(D_i[3:0]),
  .vinfo_o({palmode,n64_480i})
);





n64_vdemux video_demux(
  .VCLK(VCLK),
  .nDSYNC(nDSYNC),
  .nRST(nRST_video),
  .D_i(D_i),
  .demuxparams_i({palmode,nDeBlur_o,n16bit_mode_o}),
  .vdata_sy_0_o(vdata_sy_0),
  .vdata_1_o(vdata_1)
);





assign nRST_io = DRV_RST ? 1'b0 : 1'bz;

always @(*) begin
  {nVSYNC,nCLAMP,nHSYNC,nCSYNC} <=  vdata_1[`VDATA_SY_SLICE];
   R_o                          <= {vdata_1[`VDATA_RE_SLICE],vdata_1[3*color_width-1]};
   G_o                          <= {vdata_1[`VDATA_GR_SLICE],vdata_1[2*color_width-1]};
   B_o                          <= {vdata_1[`VDATA_BL_SLICE],vdata_1[  color_width-1]};

  CLK_ADV712x    <= VCLK;
  nCSYNC_ADV712x <= nSYNC_ON_GREEN ? 1'b0 : vdata_1[vdata_width-4];
  nBLANK_ADV712x <= 1'b1;
end

endmodule
module n64rgbv2_top (

  VCLK,
  nDSYNC,
  D_i,


  nRST_io,
  CTRL_i,
  


  nSYNC_ON_GREEN,
  n16bit_mode_t,
  nVIDeBlur_t,
  en_IGR_Rst_Func,
  en_IGR_DeBl_16b_Func,


  nHSYNC,
  nVSYNC,
  nCSYNC,
  nCLAMP,

  R_o,
  G_o,
  B_o,

  CLK_ADV712x,
  nCSYNC_ADV712x,
  nBLANK_ADV712x,
  
  dummy_i
);



`include "../lib/n64rgb_params.vh"

input                   VCLK;
input                   nDSYNC;
input [color_width-1:0] D_i;

inout nRST_io;
input CTRL_i;

input  nSYNC_ON_GREEN;

input n16bit_mode_t;
input nVIDeBlur_t;
input en_IGR_Rst_Func;
input en_IGR_DeBl_16b_Func;

output reg nHSYNC;
output reg nVSYNC;
output reg nCSYNC;
output reg nCLAMP;

output reg [color_width:0] R_o;
output reg [color_width:0] G_o;
output reg [color_width:0] B_o;

output reg CLK_ADV712x;
output reg nCSYNC_ADV712x;
output reg nBLANK_ADV712x;

input [4:0] dummy_i;



wire DRV_RST, n16bit_mode_o, nDeBlur_o;
wire nRST_hk, nRST_video;
wire [1:0] vinfo_pass;
wire palmode, n64_480i;
wire [`VDATA_SY_SLICE] vdata_sy_0;
wire [`VDATA_FU_SLICE] vdata_1;

assign nRST_hk = nRST_io;
`ifdef NO_VIDEO_PIPELINE_RESET
  assign nRST_video = 1'b1;
`else
  assign nRST_video = nRST_io;
`endif




n64rgb_hk hk_u(
  .VCLK(VCLK),
  .nRST(nRST_hk),
  .DRV_RST(DRV_RST),
  .CTRL_i(CTRL_i),
  .n64_480i(n64_480i),
  .n16bit_mode_t(n16bit_mode_t),
  .nVIDeBlur_t(nVIDeBlur_t),
  .en_IGR_Rst_Func(en_IGR_Rst_Func),
  .en_IGR_DeBl_16b_Func(en_IGR_DeBl_16b_Func),
  .n16bit_o(n16bit_mode_o),
  .nDeBlur_o(nDeBlur_o)
);





n64_vinfo_ext get_vinfo(
  .VCLK(VCLK),
  .nRST(nRST_video),
  .nDSYNC(nDSYNC),
  .Sync_pre(vdata_sy_0),
  .Sync_cur(D_i[3:0]),
  .vinfo_o({palmode,n64_480i})
);





n64_vdemux video_demux(
  .VCLK(VCLK),
  .nDSYNC(nDSYNC),
  .nRST(nRST_video),
  .D_i(D_i),
  .demuxparams_i({palmode,nDeBlur_o,n16bit_mode_o}),
  .vdata_sy_0_o(vdata_sy_0),
  .vdata_1_o(vdata_1)
);





assign nRST_io = DRV_RST ? 1'b0 : 1'bz;

always @(*) begin
  {nVSYNC,nCLAMP,nHSYNC,nCSYNC} <=  vdata_1[`VDATA_SY_SLICE];
   R_o                          <= {vdata_1[`VDATA_RE_SLICE],vdata_1[3*color_width-1]};
   G_o                          <= {vdata_1[`VDATA_GR_SLICE],vdata_1[2*color_width-1]};
   B_o                          <= {vdata_1[`VDATA_BL_SLICE],vdata_1[  color_width-1]};

  CLK_ADV712x    <= VCLK;
  nCSYNC_ADV712x <= nSYNC_ON_GREEN ? 1'b0 : vdata_1[vdata_width-4];
  nBLANK_ADV712x <= 1'b1;
end

endmodule