data/full_repos/permissive/503973366/NOT_USE/NOT_USE_HW/ALU/8_bit_Multiplier/Adder/Half_adder.v
data/verilator_xmls/5f44fb8c-badf-4099-9fe1-e5edd3559506.xml
module Half_adder(
    input       a,b,
    output wire Csum, Cout
);
    assign Csum = a ^ b;
    assign Cout = a && b;
endmodule
module Half_adder(
    input       a,b,
    output wire Csum, Cout
);

    assign Csum = a ^ b;
    assign Cout = a && b;
endmodule