data/full_repos/permissive/528055623/tic_tac_toe.v
1: b'%Error: data/full_repos/permissive/528055623/tic_tac_toe.v:36: Cannot find file containing module: \'check_move\'\ncheck_move SM1 (\n^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/528055623,data/full_repos/permissive/528055623/check_move\n             data/full_repos/permissive/528055623,data/full_repos/permissive/528055623/check_move.v\n             data/full_repos/permissive/528055623,data/full_repos/permissive/528055623/check_move.sv\n             check_move\n             check_move.v\n             check_move.sv\n             obj_dir/check_move\n             obj_dir/check_move.v\n             obj_dir/check_move.sv\n%Error: data/full_repos/permissive/528055623/tic_tac_toe.v:44: Cannot find file containing module: \'check_state\'\ncheck_state SM2 (\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/528055623/tic_tac_toe.v:50: Cannot find file containing module: \'update\'\nupdate SM3 (\n^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/528055623/tic_tac_toe.v:72: Operator COND expects 161 bits on the Conditional True, but Conditional True\'s CONST \'40\'h412077696e\' generates 40 bits.\n                                                                     : ... In instance tic_tac_toe\nassign result =  (temp_state == Awin) ? "A win" :\n                                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/528055623/tic_tac_toe.v:73: Operator COND expects 161 bits on the Conditional True, but Conditional True\'s CONST \'40\'h422077696e\' generates 40 bits.\n                                                                     : ... In instance tic_tac_toe\n     (temp_state == Bwin) ? "B win" :\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/528055623/tic_tac_toe.v:74: Operator COND expects 161 bits on the Conditional True, but Conditional True\'s CONST \'32\'h64726177\' generates 32 bits.\n                                                                     : ... In instance tic_tac_toe\n     (temp_state == DRAW) ? "draw" :\n                          ^\n%Warning-WIDTH: data/full_repos/permissive/528055623/tic_tac_toe.v:75: Operator COND expects 161 bits on the Conditional True, but Conditional True\'s CONST \'64\'h412773207475726e\' generates 64 bits.\n                                                                     : ... In instance tic_tac_toe\n     (temp_turn == A) ? "A\'s turn" : "B\'s turn";\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/528055623/tic_tac_toe.v:75: Operator COND expects 161 bits on the Conditional False, but Conditional False\'s CONST \'64\'h422773207475726e\' generates 64 bits.\n                                                                     : ... In instance tic_tac_toe\n     (temp_turn == A) ? "A\'s turn" : "B\'s turn";\n                      ^\n%Error: Exiting due to 3 error(s), 5 warning(s)\n'
module tic_tac_toe (
	input [8:0] A_move, B_move,
	input OK_btn, reset,
	output [8:0] A_state, B_state,
	output [8*20:0] result
);

parameter 	A = 2'b01,
			B = 2'b10;

parameter 	PLAY = 2'b00,
			Awin = 2'b01,
			Bwin = 2'b10,
			DRAW = 2'b11;

wire 	[17:0] curr_move;
reg 	[17:0] temp_move;
wire 	[17:0] next_move = {B_move, A_move};

wire 	[1:0] curr_state;
reg 	[1:0] temp_state;
wire 	[1:0] next_state;

wire 	[1:0] curr_turn;
reg 	[1:0] temp_turn;

wire valid_move;

initial
begin
	temp_move = 18'd0;
	temp_state = PLAY;
	temp_turn = A;
end

check_move SM1 (
	.turn(temp_turn),
	.state(temp_state),
	.curr_move(temp_move),
	.next_move(next_move),
	.valid_move(valid_move)
);

check_state SM2 (
	.move(next_move),
	.state(temp_state),
	.next_state(next_state)
);

update SM3 (
	.OK_button(OK_btn),
	.reset(reset),

	.valid_move(valid_move),
	.next_move(next_move),
	.curr_move(curr_move),

	.state(temp_state),
	.next_state(next_state),
	.curr_state(curr_state),

	.next_turn(temp_turn),
	.curr_turn(curr_turn)
);

always @(curr_move)		temp_move <= curr_move;
always @(curr_turn)		temp_turn <= curr_turn;
always @(curr_state)	temp_state <= curr_state;

assign A_state = temp_move[8:0];
assign B_state = temp_move[17:9];
assign result = 	(temp_state == Awin) ? "A win" :
					(temp_state == Bwin) ? "B win" :
					(temp_state == DRAW) ? "draw" :
					(temp_turn == A) ? "A's turn" : "B's turn";
endmodule
module tic_tac_toe (
	input [8:0] A_move, B_move,
	input OK_btn, reset,
	output [8:0] A_state, B_state,
	output [8*20:0] result
);


parameter 	A = 2'b01,
			B = 2'b10;

parameter 	PLAY = 2'b00,
			Awin = 2'b01,
			Bwin = 2'b10,
			DRAW = 2'b11;

wire 	[17:0] curr_move;
reg 	[17:0] temp_move;
wire 	[17:0] next_move = {B_move, A_move};

wire 	[1:0] curr_state;
reg 	[1:0] temp_state;
wire 	[1:0] next_state;

wire 	[1:0] curr_turn;
reg 	[1:0] temp_turn;

wire valid_move;

initial
begin
	temp_move = 18'd0;
	temp_state = PLAY;
	temp_turn = A;
end

check_move SM1 (
	.turn(temp_turn),
	.state(temp_state),
	.curr_move(temp_move),
	.next_move(next_move),
	.valid_move(valid_move)
);

check_state SM2 (
	.move(next_move),
	.state(temp_state),
	.next_state(next_state)
);

update SM3 (
	.OK_button(OK_btn),
	.reset(reset),

	.valid_move(valid_move),
	.next_move(next_move),
	.curr_move(curr_move),

	.state(temp_state),
	.next_state(next_state),
	.curr_state(curr_state),

	.next_turn(temp_turn),
	.curr_turn(curr_turn)
);

always @(curr_move)		temp_move <= curr_move;
always @(curr_turn)		temp_turn <= curr_turn;
always @(curr_state)	temp_state <= curr_state;

assign A_state = temp_move[8:0];
assign B_state = temp_move[17:9];
assign result = 	(temp_state == Awin) ? "A win" :
					(temp_state == Bwin) ? "B win" :
					(temp_state == DRAW) ? "draw" :
					(temp_turn == A) ? "A's turn" : "B's turn";
endmodule