data/full_repos/permissive/469979476/language/5/5.v
data/verilator_xmls/bffefb70-4984-47b7-a96d-826ea239e05e.xml
module top_module(input in,
                  output out);
    assign out = ~in;
endmodule
module top_module(input in,
                  output out);

    assign out = ~in;
endmodule