data/full_repos/permissive/420671157/verilog_files/fa2.v
1: b'%Error: data/full_repos/permissive/420671157/verilog_files/fa2.v:49: Unsupported or unknown PLI call: $dumpfile\n   $dumpfile(" 10.vcd");\n   ^~~~~~~~~\n%Error: data/full_repos/permissive/420671157/verilog_files/fa2.v:50: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module CLA(a,b,c,s,co);
	input [1:0] a,b;
	input [0:0] c;
	output [2:0] s;
	output [0:0] co;
	wire [0:0] cx0;
	Carry c1(.a(a[0:0]), .b(b[0:0]), .c(c[0:0]), .s(s[0:0]), .co(cx0[0:0]));
	Carry c2(.a(a[1:1]), .b(b[1:1]), .c(cx0[0:0]), .s(s[1:1]), .co(s[2:2]));
	assign co[0:0] = s[2:2];
endmodule
module CLA(a,b,c,s,co);

	input [1:0] a,b;
	input [0:0] c;
	output [2:0] s;
	output [0:0] co;
	wire [0:0] cx0;
	Carry c1(.a(a[0:0]), .b(b[0:0]), .c(c[0:0]), .s(s[0:0]), .co(cx0[0:0]));
	Carry c2(.a(a[1:1]), .b(b[1:1]), .c(cx0[0:0]), .s(s[1:1]), .co(s[2:2]));
	assign co[0:0] = s[2:2];
endmodule