data/full_repos/permissive/469312749/alu/work/verilog/multi_seven_seg_2.v
1: b"%Error: data/full_repos/permissive/469312749/alu/work/verilog/multi_seven_seg_2.v:27: Cannot find file containing module: 'counter_4'\n  counter_4 ctr (\n  ^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/469312749/alu/work/verilog,data/full_repos/permissive/469312749/counter_4\n             data/full_repos/permissive/469312749/alu/work/verilog,data/full_repos/permissive/469312749/counter_4.v\n             data/full_repos/permissive/469312749/alu/work/verilog,data/full_repos/permissive/469312749/counter_4.sv\n             counter_4\n             counter_4.v\n             counter_4.sv\n             obj_dir/counter_4\n             obj_dir/counter_4.v\n             obj_dir/counter_4.sv\n%Error: data/full_repos/permissive/469312749/alu/work/verilog/multi_seven_seg_2.v:35: Cannot find file containing module: 'seven_seg_5'\n  seven_seg_5 seg_dec (\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/469312749/alu/work/verilog/multi_seven_seg_2.v:42: Cannot find file containing module: 'decoder_6'\n  decoder_6 digit_dec (\n  ^~~~~~~~~\n%Error: Exiting due to 3 error(s)\n"
module multi_seven_seg_2 (
    input clk,
    input rst,
    input [31:0] values,
    output reg [6:0] seg,
    output reg [3:0] sel
  );
  
  localparam DIGITS = 3'h4;
  localparam DIV = 5'h10;
  
  
  localparam DIGIT_BITS = 2'h2;
  
  wire [2-1:0] M_ctr_value;
  counter_4 ctr (
    .clk(clk),
    .rst(rst),
    .value(M_ctr_value)
  );
  
  wire [7-1:0] M_seg_dec_segs;
  reg [8-1:0] M_seg_dec_char;
  seven_seg_5 seg_dec (
    .char(M_seg_dec_char),
    .segs(M_seg_dec_segs)
  );
  
  wire [4-1:0] M_digit_dec_out;
  reg [2-1:0] M_digit_dec_in;
  decoder_6 digit_dec (
    .in(M_digit_dec_in),
    .out(M_digit_dec_out)
  );
  
  always @* begin
    M_seg_dec_char = values[(M_ctr_value)*8+7-:8];
    seg = M_seg_dec_segs;
    M_digit_dec_in = M_ctr_value;
    sel = M_digit_dec_out;
  end
endmodule
module multi_seven_seg_2 (
    input clk,
    input rst,
    input [31:0] values,
    output reg [6:0] seg,
    output reg [3:0] sel
  );

  
  localparam DIGITS = 3'h4;
  localparam DIV = 5'h10;
  
  
  localparam DIGIT_BITS = 2'h2;
  
  wire [2-1:0] M_ctr_value;
  counter_4 ctr (
    .clk(clk),
    .rst(rst),
    .value(M_ctr_value)
  );
  
  wire [7-1:0] M_seg_dec_segs;
  reg [8-1:0] M_seg_dec_char;
  seven_seg_5 seg_dec (
    .char(M_seg_dec_char),
    .segs(M_seg_dec_segs)
  );
  
  wire [4-1:0] M_digit_dec_out;
  reg [2-1:0] M_digit_dec_in;
  decoder_6 digit_dec (
    .in(M_digit_dec_in),
    .out(M_digit_dec_out)
  );
  
  always @* begin
    M_seg_dec_char = values[(M_ctr_value)*8+7-:8];
    seg = M_seg_dec_segs;
    M_digit_dec_in = M_ctr_value;
    sel = M_digit_dec_out;
  end
endmodule