data/full_repos/permissive/432564927/Lab4 (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new/CPU.v
1: b'%Error: Cannot find file containing module: (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927\n        ... Looked in:\n             data/full_repos/permissive/432564927/Lab4/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927\n             data/full_repos/permissive/432564927/Lab4/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             data/full_repos/permissive/432564927/Lab4/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927\n             (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n             obj_dir/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927\n             obj_dir/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.v\n             obj_dir/(Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new,data/full_repos/permissive/432564927.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/432564927/Lab4\n%Error: Cannot find file containing module: (Verilog)/Lab4_Unal/Lab4.srcs/sources_1/new/CPU.v\n%Error: Exiting due to 3 error(s)\n'
module EXEMEM (clock, eWREG, eM2REG, eWMEM, eMUX, eALU_OUT, eQB, eWREG_out, 
               eM2REG_out, eWMEM_out, eMUX_out, eALU_out, eQB_out);
    input clock, eWREG, eM2REG, eWMEM;
    input [4:0] eMUX;
    input [31:0] eQB, eALU_OUT;
    
    reg ewreg, em2reg, ewmem;
    reg [4:0] emux;
    reg [31:0] ealu_out, eqb;
    
    output reg eWREG_out, eM2REG_out, eWMEM_out;
    output reg [4:0] eMUX_out;
    output reg [31:0] eALU_out, eQB_out;

    always @ (posedge clock) begin
        ewreg <= eWREG;
        em2reg <= eM2REG;
        ewmem <= eWMEM;
        emux <= eMUX;
        ealu_out <= eALU_OUT;
        eqb <= eQB;
    end

    always @ (negedge clock) begin
        eWREG_out <= ewreg;
        eM2REG_out <= em2reg;
        eWMEM_out <= ewmem;
        eMUX_out <= emux;
        eALU_out <= ealu_out;
        eQB_out <= eqb;
    end
endmodule
module EXEMEM (clock, eWREG, eM2REG, eWMEM, eMUX, eALU_OUT, eQB, eWREG_out, 
               eM2REG_out, eWMEM_out, eMUX_out, eALU_out, eQB_out);

    input clock, eWREG, eM2REG, eWMEM;
    input [4:0] eMUX;
    input [31:0] eQB, eALU_OUT;
    
    reg ewreg, em2reg, ewmem;
    reg [4:0] emux;
    reg [31:0] ealu_out, eqb;
    
    output reg eWREG_out, eM2REG_out, eWMEM_out;
    output reg [4:0] eMUX_out;
    output reg [31:0] eALU_out, eQB_out;

    always @ (posedge clock) begin
        ewreg <= eWREG;
        em2reg <= eM2REG;
        ewmem <= eWMEM;
        emux <= eMUX;
        ealu_out <= eALU_OUT;
        eqb <= eQB;
    end

    always @ (negedge clock) begin
        eWREG_out <= ewreg;
        eM2REG_out <= em2reg;
        eWMEM_out <= ewmem;
        eMUX_out <= emux;
        eALU_out <= ealu_out;
        eQB_out <= eqb;
    end
endmodule