data/full_repos/permissive/437995305/sim/SRAM2S_128X16.v
1: b'%Warning-WIDTH: data/full_repos/permissive/437995305/sim/SRAM2S_128X16.v:23: Bit extraction of array[128:0] requires 8 bit index, not 7 bits.\n                                                                           : ... In instance SRAM2S_128X16\n   Q0 <= mem[A0];\n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/437995305/sim/SRAM2S_128X16.v:25: Bit extraction of array[128:0] requires 8 bit index, not 7 bits.\n                                                                           : ... In instance SRAM2S_128X16\n    mem[A0] <= D0;\n       ^\n%Warning-WIDTH: data/full_repos/permissive/437995305/sim/SRAM2S_128X16.v:33: Bit extraction of array[128:0] requires 8 bit index, not 7 bits.\n                                                                           : ... In instance SRAM2S_128X16\n   Q1 <= mem[A1];\n            ^\n%Warning-WIDTH: data/full_repos/permissive/437995305/sim/SRAM2S_128X16.v:35: Bit extraction of array[128:0] requires 8 bit index, not 7 bits.\n                                                                           : ... In instance SRAM2S_128X16\n    mem[A1] <= D1;\n       ^\n%Error: Exiting due to 4 warning(s)\n'
module SRAM2S_128X16(
	input CLK,
	
	input CE0,
	input[6:0] A0,
	input[15:0] D0,
	input WE0,
	input [15:0] WEM0,
	output reg[15:0] Q0,
	
	input CE1,
	input[6:0] A1,
	input[15:0] D1,
	input WE1,
	input [15:0] WEM1,
	output reg[15:0] Q1
	);
	
	reg[15:0] mem[0:128];
	
	always @(posedge CLK) begin
		if(CE0) begin
			Q0 <= mem[A0];
			if(WE0)
				mem[A0] <= D0;
		end
		else
			Q0 <= 16'hxxxx;
	end
	
	always @(posedge CLK) begin
		if(CE1) begin
			Q1 <= mem[A1];
			if(WE1)
				mem[A1] <= D1;
		end
		else
			Q1 <= 16'hxxxx;
	end
	
endmodule
module SRAM2S_128X16(
	input CLK,
	
	input CE0,
	input[6:0] A0,
	input[15:0] D0,
	input WE0,
	input [15:0] WEM0,
	output reg[15:0] Q0,
	
	input CE1,
	input[6:0] A1,
	input[15:0] D1,
	input WE1,
	input [15:0] WEM1,
	output reg[15:0] Q1
	);

	
	reg[15:0] mem[0:128];
	
	always @(posedge CLK) begin
		if(CE0) begin
			Q0 <= mem[A0];
			if(WE0)
				mem[A0] <= D0;
		end
		else
			Q0 <= 16'hxxxx;
	end
	
	always @(posedge CLK) begin
		if(CE1) begin
			Q1 <= mem[A1];
			if(WE1)
				mem[A1] <= D1;
		end
		else
			Q1 <= 16'hxxxx;
	end
	
endmodule