data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/round.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/round.v:31: Little bit endian vector: MSB < LSB of bit range: -1:0\n    (input [bits_in-1:0] in,\n           ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/round.v:32: Little bit endian vector: MSB < LSB of bit range: -1:0\n     output [bits_out-1:0] out,\n            ^\n%Warning-WIDTH: data/full_repos/permissive/447976230/fpga/usrp2/sdr_lib/round.v:57: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s SUB generates 2 bits.\n                                                                                  : ... In instance round\n   assign err = in - {out,{(bits_in-bits_out){1\'b0}}};\n              ^\n%Error: Exiting due to 3 warning(s)\n'
module round
  #(parameter bits_in=0,
    parameter bits_out=0,
    parameter round_to_zero=0,
    parameter round_to_nearest=1,
    parameter trunc=0)
    (input [bits_in-1:0] in,
     output [bits_out-1:0] out,
     output [bits_in-bits_out:0] err);

   wire 			 round_corr,round_corr_trunc,round_corr_rtz,round_corr_nearest,round_corr_nearest_safe;
   
   assign 			 round_corr_trunc = 0;
   assign 			 round_corr_rtz = (in[bits_in-1] & |in[bits_in-bits_out-1:0]);
   assign 			 round_corr_nearest = in[bits_in-bits_out-1];

   generate
      if(bits_in-bits_out > 1)
	assign 			 round_corr_nearest_safe = (~in[bits_in-1] & (&in[bits_in-2:bits_out])) ? 0 :
				 round_corr_nearest;
      else
	assign round_corr_nearest_safe = round_corr_nearest;
   endgenerate
   
      
   assign round_corr = round_to_nearest ? round_corr_nearest_safe :
		       trunc ? round_corr_trunc : 
		       round_to_zero ? round_corr_rtz :
		       0;
      
   assign out = in[bits_in-1:bits_in-bits_out] + round_corr;
   
   assign err = in - {out,{(bits_in-bits_out){1'b0}}};
   
endmodule
module round
  #(parameter bits_in=0,
    parameter bits_out=0,
    parameter round_to_zero=0,
    parameter round_to_nearest=1,
    parameter trunc=0)
    (input [bits_in-1:0] in,
     output [bits_out-1:0] out,
     output [bits_in-bits_out:0] err);


   wire 			 round_corr,round_corr_trunc,round_corr_rtz,round_corr_nearest,round_corr_nearest_safe;
   
   assign 			 round_corr_trunc = 0;
   assign 			 round_corr_rtz = (in[bits_in-1] & |in[bits_in-bits_out-1:0]);
   assign 			 round_corr_nearest = in[bits_in-bits_out-1];

   generate
      if(bits_in-bits_out > 1)
	assign 			 round_corr_nearest_safe = (~in[bits_in-1] & (&in[bits_in-2:bits_out])) ? 0 :
				 round_corr_nearest;
      else
	assign round_corr_nearest_safe = round_corr_nearest;
   endgenerate
   
      
   assign round_corr = round_to_nearest ? round_corr_nearest_safe :
		       trunc ? round_corr_trunc : 
		       round_to_zero ? round_corr_rtz :
		       0;
      
   assign out = in[bits_in-1:bits_in-bits_out] + round_corr;
   
   assign err = in - {out,{(bits_in-bits_out){1'b0}}};
   
endmodule