data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/atr_controller.v
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/atr_controller.v:46: Cannot find include file: ../regmap/atr_regmap_utils.vh\n  `include "../regmap/atr_regmap_utils.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints,data/full_repos/permissive/447976230/../regmap/atr_regmap_utils.vh\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints,data/full_repos/permissive/447976230/../regmap/atr_regmap_utils.vh.v\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints,data/full_repos/permissive/447976230/../regmap/atr_regmap_utils.vh.sv\n             ../regmap/atr_regmap_utils.vh\n             ../regmap/atr_regmap_utils.vh.v\n             ../regmap/atr_regmap_utils.vh.sv\n             obj_dir/../regmap/atr_regmap_utils.vh\n             obj_dir/../regmap/atr_regmap_utils.vh.v\n             obj_dir/../regmap/atr_regmap_utils.vh.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/atr_controller.v:47: Cannot find include file: ../../../../../../lib/rfnoc/core/ctrlport.vh\n  `include "../../../../../../lib/rfnoc/core/ctrlport.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module atr_controller #(
  parameter [19:0] BASE_ADDRESS = 0,
  parameter [19:0] SIZE_ADDRESS = 0
) (

  input  wire        ctrlport_clk,
  input  wire        ctrlport_rst,


  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [31:0] s_ctrlport_req_data,


  output reg         s_ctrlport_resp_ack,
  output reg  [ 1:0] s_ctrlport_resp_status,
  output reg  [31:0] s_ctrlport_resp_data,





  input  wire [ 3:0] atr_fpga_state,


  output reg  [ 7:0] atr_config_dsa_rf0 = 8'b0,
  output reg  [ 7:0] atr_config_dsa_rf1 = 8'b0,
  output reg  [ 7:0] atr_config_rf0     = 8'b0,
  output reg  [ 7:0] atr_config_rf1     = 8'b0
);

  `include "../regmap/atr_regmap_utils.vh"
  `include "../../../../../../lib/rfnoc/core/ctrlport.vh"




  reg [    RF0_OPTION_SIZE-1:0] option_rf0     = SW_DEFINED;
  reg [    RF1_OPTION_SIZE-1:0] option_rf1     = SW_DEFINED;
  reg [RF0_DSA_OPTION_SIZE-1:0] option_dsa_rf0 = SW_DEFINED;
  reg [RF1_DSA_OPTION_SIZE-1:0] option_dsa_rf1 = SW_DEFINED;

  reg [    SW_RF0_CONFIG_SIZE-1:0] sw_atr_config_rf0     = {SW_RF0_CONFIG_SIZE {1'b0}};
  reg [    SW_RF1_CONFIG_SIZE-1:0] sw_atr_config_rf1     = {SW_RF1_CONFIG_SIZE {1'b0}};
  reg [SW_RF0_DSA_CONFIG_SIZE-1:0] sw_atr_config_dsa_rf0 = {SW_RF0_DSA_CONFIG_SIZE {1'b0}};
  reg [SW_RF1_DSA_CONFIG_SIZE-1:0] sw_atr_config_dsa_rf1 = {SW_RF1_DSA_CONFIG_SIZE {1'b0}};




  wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + SIZE_ADDRESS);

  always @(posedge ctrlport_clk) begin

    if (ctrlport_rst) begin
      option_rf0     <= SW_DEFINED;
      option_rf1     <= SW_DEFINED;
      option_dsa_rf0 <= SW_DEFINED;
      option_dsa_rf1 <= SW_DEFINED;

      sw_atr_config_rf0     <= {SW_RF0_CONFIG_SIZE {1'b0}};
      sw_atr_config_rf1     <= {SW_RF1_CONFIG_SIZE {1'b0}};
      sw_atr_config_dsa_rf0 <= {SW_RF0_DSA_CONFIG_SIZE {1'b0}};
      sw_atr_config_dsa_rf1 <= {SW_RF1_DSA_CONFIG_SIZE {1'b0}};

      s_ctrlport_resp_ack     <= 1'b0;
      s_ctrlport_resp_data    <= {32{1'bx}};
      s_ctrlport_resp_status  <= CTRL_STS_OKAY;

    end else begin


      if (s_ctrlport_req_wr) begin

        s_ctrlport_resp_ack     <= 1'b1;
        s_ctrlport_resp_data    <= {32{1'bx}};
        s_ctrlport_resp_status  <= CTRL_STS_OKAY;

        case (s_ctrlport_req_addr)
          BASE_ADDRESS + OPTION_REG: begin
            option_rf0     <= s_ctrlport_req_data[RF0_OPTION_MSB : RF0_OPTION];
            option_rf1     <= s_ctrlport_req_data[RF1_OPTION_MSB : RF1_OPTION];
            option_dsa_rf0 <= s_ctrlport_req_data[RF0_DSA_OPTION_MSB : RF0_DSA_OPTION];
            option_dsa_rf1 <= s_ctrlport_req_data[RF1_DSA_OPTION_MSB : RF1_DSA_OPTION];
          end

          BASE_ADDRESS + SW_CONFIG_REG: begin
            sw_atr_config_rf0     <= s_ctrlport_req_data[SW_RF0_CONFIG_MSB : SW_RF0_CONFIG];
            sw_atr_config_rf1     <= s_ctrlport_req_data[SW_RF1_CONFIG_MSB : SW_RF1_CONFIG];
            sw_atr_config_dsa_rf0 <= s_ctrlport_req_data[SW_RF0_DSA_CONFIG_MSB : SW_RF0_DSA_CONFIG];
            sw_atr_config_dsa_rf1 <= s_ctrlport_req_data[SW_RF1_DSA_CONFIG_MSB : SW_RF1_DSA_CONFIG];
          end


          default: begin
            if (address_in_range) begin
              s_ctrlport_resp_status  <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack     <= 1'b0;
            end
          end
        endcase


      end else if (s_ctrlport_req_rd) begin

        s_ctrlport_resp_ack     <= 1'b1;
        s_ctrlport_resp_status  <= CTRL_STS_OKAY;
        s_ctrlport_resp_data    <= {32{1'b0}};

        case (s_ctrlport_req_addr)
          BASE_ADDRESS + CURRENT_CONFIG_REG: begin
            s_ctrlport_resp_data[CURRENT_RF0_CONFIG_MSB     : CURRENT_RF0_CONFIG]     <= atr_config_rf0;
            s_ctrlport_resp_data[CURRENT_RF1_CONFIG_MSB     : CURRENT_RF1_CONFIG]     <= atr_config_rf1;
            s_ctrlport_resp_data[CURRENT_RF0_DSA_CONFIG_MSB : CURRENT_RF0_DSA_CONFIG] <= atr_config_dsa_rf0;
            s_ctrlport_resp_data[CURRENT_RF1_DSA_CONFIG_MSB : CURRENT_RF1_DSA_CONFIG] <= atr_config_dsa_rf1;
          end

          BASE_ADDRESS + OPTION_REG: begin
            s_ctrlport_resp_data[RF0_OPTION_MSB     : RF0_OPTION]     <= option_rf0;
            s_ctrlport_resp_data[RF1_OPTION_MSB     : RF1_OPTION]     <= option_rf1;
            s_ctrlport_resp_data[RF0_DSA_OPTION_MSB : RF0_DSA_OPTION] <= option_dsa_rf0;
            s_ctrlport_resp_data[RF1_DSA_OPTION_MSB : RF1_DSA_OPTION] <= option_dsa_rf1;
          end

          BASE_ADDRESS + SW_CONFIG_REG: begin
            s_ctrlport_resp_data[SW_RF0_CONFIG_MSB     : SW_RF0_CONFIG]     <= sw_atr_config_rf0;
            s_ctrlport_resp_data[SW_RF1_CONFIG_MSB     : SW_RF1_CONFIG]     <= sw_atr_config_rf1;
            s_ctrlport_resp_data[SW_RF0_DSA_CONFIG_MSB : SW_RF0_DSA_CONFIG] <= sw_atr_config_dsa_rf0;
            s_ctrlport_resp_data[SW_RF1_DSA_CONFIG_MSB : SW_RF1_DSA_CONFIG] <= sw_atr_config_dsa_rf1;
          end


          default: begin
            s_ctrlport_resp_data <= {32{1'b0}};
            if (address_in_range) begin
              s_ctrlport_resp_status <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack <= 1'b0;
            end
          end
        endcase


      end else begin
        s_ctrlport_resp_ack <= 1'b0;
      end
    end
  end




  always @(posedge ctrlport_clk) begin
    case (option_rf0)
      SW_DEFINED: begin
        atr_config_rf0 <= sw_atr_config_rf0;
      end
      CLASSIC_ATR: begin
        atr_config_rf0 <= {6'b0, atr_fpga_state[1:0]};
      end
      FPGA_STATE: begin
        atr_config_rf0 <= {4'b0, atr_fpga_state};
      end
    endcase

    case (option_rf1)
      SW_DEFINED: begin
        atr_config_rf1 <= sw_atr_config_rf1;
      end
      CLASSIC_ATR: begin
        atr_config_rf1 <= {6'b0, atr_fpga_state[3:2]};
      end
      FPGA_STATE: begin
        atr_config_rf1 <= {4'b0, atr_fpga_state};
      end
    endcase

    case (option_dsa_rf0)
      SW_DEFINED: begin
        atr_config_dsa_rf0 <= sw_atr_config_dsa_rf0;
      end
      CLASSIC_ATR: begin
        atr_config_dsa_rf0 <= {6'b0, atr_fpga_state[1:0]};
      end
      FPGA_STATE: begin
        atr_config_dsa_rf0 <= {4'b0, atr_fpga_state};
      end
    endcase

    case (option_dsa_rf1)
      SW_DEFINED: begin
        atr_config_dsa_rf1 <= sw_atr_config_dsa_rf1;
      end
      CLASSIC_ATR: begin
        atr_config_dsa_rf1 <= {6'b0, atr_fpga_state[3:2]};
      end
      FPGA_STATE: begin
        atr_config_dsa_rf1 <= {4'b0, atr_fpga_state};
      end
    endcase
  end

endmodule
module atr_controller #(
  parameter [19:0] BASE_ADDRESS = 0,
  parameter [19:0] SIZE_ADDRESS = 0
) (

  input  wire        ctrlport_clk,
  input  wire        ctrlport_rst,


  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [31:0] s_ctrlport_req_data,


  output reg         s_ctrlport_resp_ack,
  output reg  [ 1:0] s_ctrlport_resp_status,
  output reg  [31:0] s_ctrlport_resp_data,





  input  wire [ 3:0] atr_fpga_state,


  output reg  [ 7:0] atr_config_dsa_rf0 = 8'b0,
  output reg  [ 7:0] atr_config_dsa_rf1 = 8'b0,
  output reg  [ 7:0] atr_config_rf0     = 8'b0,
  output reg  [ 7:0] atr_config_rf1     = 8'b0
);


  `include "../regmap/atr_regmap_utils.vh"
  `include "../../../../../../lib/rfnoc/core/ctrlport.vh"




  reg [    RF0_OPTION_SIZE-1:0] option_rf0     = SW_DEFINED;
  reg [    RF1_OPTION_SIZE-1:0] option_rf1     = SW_DEFINED;
  reg [RF0_DSA_OPTION_SIZE-1:0] option_dsa_rf0 = SW_DEFINED;
  reg [RF1_DSA_OPTION_SIZE-1:0] option_dsa_rf1 = SW_DEFINED;

  reg [    SW_RF0_CONFIG_SIZE-1:0] sw_atr_config_rf0     = {SW_RF0_CONFIG_SIZE {1'b0}};
  reg [    SW_RF1_CONFIG_SIZE-1:0] sw_atr_config_rf1     = {SW_RF1_CONFIG_SIZE {1'b0}};
  reg [SW_RF0_DSA_CONFIG_SIZE-1:0] sw_atr_config_dsa_rf0 = {SW_RF0_DSA_CONFIG_SIZE {1'b0}};
  reg [SW_RF1_DSA_CONFIG_SIZE-1:0] sw_atr_config_dsa_rf1 = {SW_RF1_DSA_CONFIG_SIZE {1'b0}};




  wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + SIZE_ADDRESS);

  always @(posedge ctrlport_clk) begin

    if (ctrlport_rst) begin
      option_rf0     <= SW_DEFINED;
      option_rf1     <= SW_DEFINED;
      option_dsa_rf0 <= SW_DEFINED;
      option_dsa_rf1 <= SW_DEFINED;

      sw_atr_config_rf0     <= {SW_RF0_CONFIG_SIZE {1'b0}};
      sw_atr_config_rf1     <= {SW_RF1_CONFIG_SIZE {1'b0}};
      sw_atr_config_dsa_rf0 <= {SW_RF0_DSA_CONFIG_SIZE {1'b0}};
      sw_atr_config_dsa_rf1 <= {SW_RF1_DSA_CONFIG_SIZE {1'b0}};

      s_ctrlport_resp_ack     <= 1'b0;
      s_ctrlport_resp_data    <= {32{1'bx}};
      s_ctrlport_resp_status  <= CTRL_STS_OKAY;

    end else begin


      if (s_ctrlport_req_wr) begin

        s_ctrlport_resp_ack     <= 1'b1;
        s_ctrlport_resp_data    <= {32{1'bx}};
        s_ctrlport_resp_status  <= CTRL_STS_OKAY;

        case (s_ctrlport_req_addr)
          BASE_ADDRESS + OPTION_REG: begin
            option_rf0     <= s_ctrlport_req_data[RF0_OPTION_MSB : RF0_OPTION];
            option_rf1     <= s_ctrlport_req_data[RF1_OPTION_MSB : RF1_OPTION];
            option_dsa_rf0 <= s_ctrlport_req_data[RF0_DSA_OPTION_MSB : RF0_DSA_OPTION];
            option_dsa_rf1 <= s_ctrlport_req_data[RF1_DSA_OPTION_MSB : RF1_DSA_OPTION];
          end

          BASE_ADDRESS + SW_CONFIG_REG: begin
            sw_atr_config_rf0     <= s_ctrlport_req_data[SW_RF0_CONFIG_MSB : SW_RF0_CONFIG];
            sw_atr_config_rf1     <= s_ctrlport_req_data[SW_RF1_CONFIG_MSB : SW_RF1_CONFIG];
            sw_atr_config_dsa_rf0 <= s_ctrlport_req_data[SW_RF0_DSA_CONFIG_MSB : SW_RF0_DSA_CONFIG];
            sw_atr_config_dsa_rf1 <= s_ctrlport_req_data[SW_RF1_DSA_CONFIG_MSB : SW_RF1_DSA_CONFIG];
          end


          default: begin
            if (address_in_range) begin
              s_ctrlport_resp_status  <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack     <= 1'b0;
            end
          end
        endcase


      end else if (s_ctrlport_req_rd) begin

        s_ctrlport_resp_ack     <= 1'b1;
        s_ctrlport_resp_status  <= CTRL_STS_OKAY;
        s_ctrlport_resp_data    <= {32{1'b0}};

        case (s_ctrlport_req_addr)
          BASE_ADDRESS + CURRENT_CONFIG_REG: begin
            s_ctrlport_resp_data[CURRENT_RF0_CONFIG_MSB     : CURRENT_RF0_CONFIG]     <= atr_config_rf0;
            s_ctrlport_resp_data[CURRENT_RF1_CONFIG_MSB     : CURRENT_RF1_CONFIG]     <= atr_config_rf1;
            s_ctrlport_resp_data[CURRENT_RF0_DSA_CONFIG_MSB : CURRENT_RF0_DSA_CONFIG] <= atr_config_dsa_rf0;
            s_ctrlport_resp_data[CURRENT_RF1_DSA_CONFIG_MSB : CURRENT_RF1_DSA_CONFIG] <= atr_config_dsa_rf1;
          end

          BASE_ADDRESS + OPTION_REG: begin
            s_ctrlport_resp_data[RF0_OPTION_MSB     : RF0_OPTION]     <= option_rf0;
            s_ctrlport_resp_data[RF1_OPTION_MSB     : RF1_OPTION]     <= option_rf1;
            s_ctrlport_resp_data[RF0_DSA_OPTION_MSB : RF0_DSA_OPTION] <= option_dsa_rf0;
            s_ctrlport_resp_data[RF1_DSA_OPTION_MSB : RF1_DSA_OPTION] <= option_dsa_rf1;
          end

          BASE_ADDRESS + SW_CONFIG_REG: begin
            s_ctrlport_resp_data[SW_RF0_CONFIG_MSB     : SW_RF0_CONFIG]     <= sw_atr_config_rf0;
            s_ctrlport_resp_data[SW_RF1_CONFIG_MSB     : SW_RF1_CONFIG]     <= sw_atr_config_rf1;
            s_ctrlport_resp_data[SW_RF0_DSA_CONFIG_MSB : SW_RF0_DSA_CONFIG] <= sw_atr_config_dsa_rf0;
            s_ctrlport_resp_data[SW_RF1_DSA_CONFIG_MSB : SW_RF1_DSA_CONFIG] <= sw_atr_config_dsa_rf1;
          end


          default: begin
            s_ctrlport_resp_data <= {32{1'b0}};
            if (address_in_range) begin
              s_ctrlport_resp_status <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack <= 1'b0;
            end
          end
        endcase


      end else begin
        s_ctrlport_resp_ack <= 1'b0;
      end
    end
  end




  always @(posedge ctrlport_clk) begin
    case (option_rf0)
      SW_DEFINED: begin
        atr_config_rf0 <= sw_atr_config_rf0;
      end
      CLASSIC_ATR: begin
        atr_config_rf0 <= {6'b0, atr_fpga_state[1:0]};
      end
      FPGA_STATE: begin
        atr_config_rf0 <= {4'b0, atr_fpga_state};
      end
    endcase

    case (option_rf1)
      SW_DEFINED: begin
        atr_config_rf1 <= sw_atr_config_rf1;
      end
      CLASSIC_ATR: begin
        atr_config_rf1 <= {6'b0, atr_fpga_state[3:2]};
      end
      FPGA_STATE: begin
        atr_config_rf1 <= {4'b0, atr_fpga_state};
      end
    endcase

    case (option_dsa_rf0)
      SW_DEFINED: begin
        atr_config_dsa_rf0 <= sw_atr_config_dsa_rf0;
      end
      CLASSIC_ATR: begin
        atr_config_dsa_rf0 <= {6'b0, atr_fpga_state[1:0]};
      end
      FPGA_STATE: begin
        atr_config_dsa_rf0 <= {4'b0, atr_fpga_state};
      end
    endcase

    case (option_dsa_rf1)
      SW_DEFINED: begin
        atr_config_dsa_rf1 <= sw_atr_config_dsa_rf1;
      end
      CLASSIC_ATR: begin
        atr_config_dsa_rf1 <= {6'b0, atr_fpga_state[3:2]};
      end
      FPGA_STATE: begin
        atr_config_dsa_rf1 <= {4'b0, atr_fpga_state};
      end
    endcase
  end

endmodule