data/full_repos/permissive/425063934/custom_layout/sim/address_clock_sdr_2r1w_64.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/425063934/custom_layout/sim/address_clock_sdr_2r1w_64.v:92: Little bit endian vector: MSB < LSB of bit range: 0:5\n input [0:5] rd_adr_0;\n       ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/425063934/custom_layout/sim/address_clock_sdr_2r1w_64.v:94: Little bit endian vector: MSB < LSB of bit range: 0:5\n input [0:5] rd_adr_1;\n       ^\n%Warning-LITENDIAN: data/full_repos/permissive/425063934/custom_layout/sim/address_clock_sdr_2r1w_64.v:96: Little bit endian vector: MSB < LSB of bit range: 0:5\n input [0:5] wr_adr_0;\n       ^\n%Error: data/full_repos/permissive/425063934/custom_layout/sim/address_clock_sdr_2r1w_64.v:153: Cannot find file containing module: \'predecode_sdr_64\'\n  predecode_sdr_64 predecode_r0(\n  ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/425063934/custom_layout/sim,data/full_repos/permissive/425063934/predecode_sdr_64\n             data/full_repos/permissive/425063934/custom_layout/sim,data/full_repos/permissive/425063934/predecode_sdr_64.v\n             data/full_repos/permissive/425063934/custom_layout/sim,data/full_repos/permissive/425063934/predecode_sdr_64.sv\n             predecode_sdr_64\n             predecode_sdr_64.v\n             predecode_sdr_64.sv\n             obj_dir/predecode_sdr_64\n             obj_dir/predecode_sdr_64.v\n             obj_dir/predecode_sdr_64.sv\n%Error: data/full_repos/permissive/425063934/custom_layout/sim/address_clock_sdr_2r1w_64.v:171: Cannot find file containing module: \'predecode_sdr_64\'\n  predecode_sdr_64 predecode_r1(\n  ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/425063934/custom_layout/sim/address_clock_sdr_2r1w_64.v:189: Cannot find file containing module: \'predecode_sdr_64\'\n   predecode_sdr_64 predecode_w0(\n   ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s), 3 warning(s)\n'
module address_clock_sdr_2r1w_64 (

    strobe,


    rd_enb_0,
    rd_adr_0,
    rd_enb_1,
    rd_adr_1,
    wr_enb_0,
    wr_adr_0,




    rd0_c_na0,
    rd0_c_a0,
    rd0_na1_na2,
    rd0_na1_a2,
    rd0_a1_na2,
    rd0_a1_a2,
    rd0_na3,
    rd0_a3,
    rd0_na4_na5,
    rd0_na4_a5,
    rd0_a4_na5,
    rd0_a4_a5,


    rd1_c_na0,
    rd1_c_a0,
    rd1_na1_na2,
    rd1_na1_a2,
    rd1_a1_na2,
    rd1_a1_a2,
    rd1_na3,
    rd1_a3,
    rd1_na4_na5,
    rd1_na4_a5,
    rd1_a4_na5,
    rd1_a4_a5,


    wr0_c_na0,
    wr0_c_a0,
    wr0_na1_na2,
    wr0_na1_a2,
    wr0_a1_na2,
    wr0_a1_a2,
    wr0_na3,
    wr0_a3,
    wr0_na4_na5,
    wr0_na4_a5,
    wr0_a4_na5,
    wr0_a4_a5

 );

 parameter GENMODE = 0;

 input      strobe;


 input       rd_enb_0;
 input [0:5] rd_adr_0;
 input       rd_enb_1;
 input [0:5] rd_adr_1;
 input       wr_enb_0;
 input [0:5] wr_adr_0;




 output   rd0_c_na0;
 output   rd0_c_a0;

 output   rd0_na1_na2;
 output   rd0_na1_a2;
 output   rd0_a1_na2;
 output   rd0_a1_a2;

 output   rd0_na3;
 output   rd0_a3;

 output   rd0_na4_na5;
 output   rd0_na4_a5;
 output   rd0_a4_na5;
 output   rd0_a4_a5;


 output   rd1_c_na0;
 output   rd1_c_a0;

 output   rd1_na1_na2;
 output   rd1_na1_a2;
 output   rd1_a1_na2;
 output   rd1_a1_a2;

 output   rd1_na3;
 output   rd1_a3;

 output   rd1_na4_na5;
 output   rd1_na4_a5;
 output   rd1_a4_na5;
 output   rd1_a4_a5;


 output   wr0_c_na0;
 output   wr0_c_a0;

 output   wr0_na1_na2;
 output   wr0_na1_a2;
 output   wr0_a1_na2;
 output   wr0_a1_a2;

 output   wr0_na3;
 output   wr0_a3;

 output   wr0_na4_na5;
 output   wr0_na4_a5;
 output   wr0_a4_na5;
 output   wr0_a4_a5;



  predecode_sdr_64 predecode_r0(
      .strobe(strobe),
      .enable(rd_enb_0),
      .address(rd_adr_0),
      .c_na0(rd0_c_na0),
      .c_a0(rd0_c_a0),
      .na1_na2(rd0_na1_na2),
      .na1_a2(rd0_na1_a2),
      .a1_na2(rd0_a1_na2),
      .a1_a2(rd0_a1_a2),
      .na3(rd0_na3),
      .a3(rd0_a3),
      .na4_na5(rd0_na4_na5),
      .na4_a5(rd0_na4_a5),
      .a4_na5(rd0_a4_na5),
      .a4_a5(rd0_a4_a5)
  );

  predecode_sdr_64 predecode_r1(
      .strobe(strobe),
      .enable(rd_enb_1),
      .address(rd_adr_1),
      .c_na0(rd1_c_na0),
      .c_a0(rd1_c_a0),
      .na1_na2(rd1_na1_na2),
      .na1_a2(rd1_na1_a2),
      .a1_na2(rd1_a1_na2),
      .a1_a2(rd1_a1_a2),
      .na3(rd1_na3),
      .a3(rd1_a3),
      .na4_na5(rd1_na4_na5),
      .na4_a5(rd1_na4_a5),
      .a4_na5(rd1_a4_na5),
      .a4_a5(rd1_a4_a5)
   );

   predecode_sdr_64 predecode_w0(
      .strobe(strobe),
      .enable(wr_enb_0),
      .address(wr_adr_0),
      .c_na0(wr0_c_na0),
      .c_a0(wr0_c_a0),
      .na1_na2(wr0_na1_na2),
      .na1_a2(wr0_na1_a2),
      .a1_na2(wr0_a1_na2),
      .a1_a2(wr0_a1_a2),
      .na3(wr0_na3),
      .a3(wr0_a3),
      .na4_na5(wr0_na4_na5),
      .na4_a5(wr0_na4_a5),
      .a4_na5(wr0_a4_na5),
      .a4_a5(wr0_a4_a5)
   );

endmodule
module address_clock_sdr_2r1w_64 (

    strobe,


    rd_enb_0,
    rd_adr_0,
    rd_enb_1,
    rd_adr_1,
    wr_enb_0,
    wr_adr_0,




    rd0_c_na0,
    rd0_c_a0,
    rd0_na1_na2,
    rd0_na1_a2,
    rd0_a1_na2,
    rd0_a1_a2,
    rd0_na3,
    rd0_a3,
    rd0_na4_na5,
    rd0_na4_a5,
    rd0_a4_na5,
    rd0_a4_a5,


    rd1_c_na0,
    rd1_c_a0,
    rd1_na1_na2,
    rd1_na1_a2,
    rd1_a1_na2,
    rd1_a1_a2,
    rd1_na3,
    rd1_a3,
    rd1_na4_na5,
    rd1_na4_a5,
    rd1_a4_na5,
    rd1_a4_a5,


    wr0_c_na0,
    wr0_c_a0,
    wr0_na1_na2,
    wr0_na1_a2,
    wr0_a1_na2,
    wr0_a1_a2,
    wr0_na3,
    wr0_a3,
    wr0_na4_na5,
    wr0_na4_a5,
    wr0_a4_na5,
    wr0_a4_a5

 );


 parameter GENMODE = 0;

 input      strobe;


 input       rd_enb_0;
 input [0:5] rd_adr_0;
 input       rd_enb_1;
 input [0:5] rd_adr_1;
 input       wr_enb_0;
 input [0:5] wr_adr_0;




 output   rd0_c_na0;
 output   rd0_c_a0;

 output   rd0_na1_na2;
 output   rd0_na1_a2;
 output   rd0_a1_na2;
 output   rd0_a1_a2;

 output   rd0_na3;
 output   rd0_a3;

 output   rd0_na4_na5;
 output   rd0_na4_a5;
 output   rd0_a4_na5;
 output   rd0_a4_a5;


 output   rd1_c_na0;
 output   rd1_c_a0;

 output   rd1_na1_na2;
 output   rd1_na1_a2;
 output   rd1_a1_na2;
 output   rd1_a1_a2;

 output   rd1_na3;
 output   rd1_a3;

 output   rd1_na4_na5;
 output   rd1_na4_a5;
 output   rd1_a4_na5;
 output   rd1_a4_a5;


 output   wr0_c_na0;
 output   wr0_c_a0;

 output   wr0_na1_na2;
 output   wr0_na1_a2;
 output   wr0_a1_na2;
 output   wr0_a1_a2;

 output   wr0_na3;
 output   wr0_a3;

 output   wr0_na4_na5;
 output   wr0_na4_a5;
 output   wr0_a4_na5;
 output   wr0_a4_a5;



  predecode_sdr_64 predecode_r0(
      .strobe(strobe),
      .enable(rd_enb_0),
      .address(rd_adr_0),
      .c_na0(rd0_c_na0),
      .c_a0(rd0_c_a0),
      .na1_na2(rd0_na1_na2),
      .na1_a2(rd0_na1_a2),
      .a1_na2(rd0_a1_na2),
      .a1_a2(rd0_a1_a2),
      .na3(rd0_na3),
      .a3(rd0_a3),
      .na4_na5(rd0_na4_na5),
      .na4_a5(rd0_na4_a5),
      .a4_na5(rd0_a4_na5),
      .a4_a5(rd0_a4_a5)
  );

  predecode_sdr_64 predecode_r1(
      .strobe(strobe),
      .enable(rd_enb_1),
      .address(rd_adr_1),
      .c_na0(rd1_c_na0),
      .c_a0(rd1_c_a0),
      .na1_na2(rd1_na1_na2),
      .na1_a2(rd1_na1_a2),
      .a1_na2(rd1_a1_na2),
      .a1_a2(rd1_a1_a2),
      .na3(rd1_na3),
      .a3(rd1_a3),
      .na4_na5(rd1_na4_na5),
      .na4_a5(rd1_na4_a5),
      .a4_na5(rd1_a4_na5),
      .a4_a5(rd1_a4_a5)
   );

   predecode_sdr_64 predecode_w0(
      .strobe(strobe),
      .enable(wr_enb_0),
      .address(wr_adr_0),
      .c_na0(wr0_c_na0),
      .c_a0(wr0_c_a0),
      .na1_na2(wr0_na1_na2),
      .na1_a2(wr0_na1_a2),
      .a1_na2(wr0_a1_na2),
      .a1_a2(wr0_a1_a2),
      .na3(wr0_na3),
      .a3(wr0_a3),
      .na4_na5(wr0_na4_na5),
      .na4_a5(wr0_na4_a5),
      .a4_na5(wr0_a4_na5),
      .a4_a5(wr0_a4_a5)
   );

endmodule