data/full_repos/permissive/494622711/verilog/rtl/clock_divider.v
data/verilator_xmls/adf35b30-3b73-4621-b26f-4ca4b21e148d.xml
module ClockDividerPow(input clk,
                       output clk_out);
    parameter POW2DIV = 2;

    reg [POW2DIV:0] counter = 0;
    
    always @ (posedge clk)
    begin
        counter <= counter + 1;
    end
    
    assign clk_out = counter[POW2DIV];
    
endmodule
module ClockDividerPow(input clk,
                       output clk_out);

    parameter POW2DIV = 2;

    reg [POW2DIV:0] counter = 0;
    
    always @ (posedge clk)
    begin
        counter <= counter + 1;
    end
    
    assign clk_out = counter[POW2DIV];
    
endmodule