data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/stream_register_tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/stream_register_tb.sv:46: Unsupported: Ignoring delay on this delayed statement.\n            #10ns clk = ~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/stream_register_tb.sv:50: Unsupported: Ignoring delay on this delayed statement.\n            #10ns clk = ~clk;\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/stream_register_tb.sv:55: Unsupported: Ignoring delay on this delayed statement.\n        #100ms\n        ^\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/stream_register_tb.sv:60: Unsupported: classes\n    class random_action_t;\n    ^~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/stream_register_tb.sv:63: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n        constraint random_action {\n        ^~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/stream_register_tb.sv:63: syntax error, unexpected IDENTIFIER\n        constraint random_action {\n                   ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/stream_register_tb.sv:64: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n            action dist {\n                   ^~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/stream_register_tb.sv:76: syntax error, unexpected clocking\n        clocking cb @(posedge clk);\n        ^~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/stream_register_tb.sv:99: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n                void\'(random_action.randomize());\n                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/stream_register_tb.sv:100: Unsupported or unknown PLI call: $urandom_range\n                repeat($urandom_range(0, 8)) @(cb);\n                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/stream_register_tb.sv:104: Unsupported or unknown PLI call: $urandom_range\n                        cb.inp_data     <= $urandom_range(0,256);\n                                           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/stream_register_tb.sv:109: Unsupported or unknown PLI call: $urandom_range\n                        cb.inp_data     <= $urandom_range(0,256);\n                                           ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/473423187/hw/rtl/fp_cores/fpnew/src/common_cells/test/stream_register_tb.sv:129: Unsupported or unknown PLI call: $urandom_range\n                repeat($urandom_range(0, 8)) @(cb);\n                       ^~~~~~~~~~~~~~\n%Error: Cannot continue\n        ... See the manual and https://verilator.org for more assistance.\n'
module stream_register_tb #(
    parameter type T    = logic[7:0]
);

    logic   clk,
            rst_n,
            clr,
            inp_valid, inp_ready,
            oup_valid, oup_ready;

    T       inp_data,
            oup_data;

    int unsigned nr_checks;

    stream_register #(
        .T  (T)
    ) dut (
        .clk_i      (clk),
        .rst_ni     (rst_n),
        .clr_i      (clr),
        .testmode_i (1'b0),
        .valid_i    (inp_valid),
        .ready_o    (inp_ready),
        .data_i     (inp_data),
        .valid_o    (oup_valid),
        .ready_i    (oup_ready),
        .data_o     (oup_data)
    );

    initial begin
        clk = 1'b0;
        rst_n = 1'b0;
        repeat(8)
            #10ns clk = ~clk;

        rst_n = 1'b1;
        forever
            #10ns clk = ~clk;
    end


    initial begin
        #100ms
        $display("Checked %d stimuli", nr_checks);
        $stop;
    end

    class random_action_t;
        rand logic [1:0] action;

        constraint random_action {
            action dist {
                0 := 40,
                1 := 40,
                3 := 2,
                0 := 0
            };
        }
    endclass

    program testbench ();
        logic[7:0] queue [$];

        clocking cb @(posedge clk);
            default input #2 output #4;
            output clr, inp_data, inp_valid, oup_ready;
            input inp_ready, oup_valid, oup_data;
        endclocking

        clocking pck @(posedge clk);
            default input #2 output #4;
            input clr, inp_data, inp_valid, inp_ready, oup_data, oup_valid, oup_ready;
        endclocking




        initial begin
            automatic random_action_t random_action = new();

            cb.clr <= 1'b0;

            wait (rst_n == 1'b1);
            cb.inp_valid <= 1'b0;

            forever begin
                void'(random_action.randomize());
                repeat($urandom_range(0, 8)) @(cb);

                case (random_action.action)
                    0: begin
                        cb.inp_data     <= $urandom_range(0,256);
                        cb.inp_valid    <= 1'b1;
                    end
                    1: begin
                        cb.clr <= 1'b0;
                        cb.inp_data     <= $urandom_range(0,256);
                        cb.inp_valid    <= 1'b0;
                    end
                    default: begin
                        cb.clr          <= 1'b1;
                        cb.inp_valid    <= 1'b0;
                        @(cb);
                        cb.clr          <= 1'b0;
                    end
                endcase
            end
        end

        initial begin

            wait (rst_n == 1'b1);

            forever begin
                @(cb)
                cb.oup_ready    <= 1'b1;
                repeat($urandom_range(0, 8)) @(cb);
                cb.oup_ready    <= 1'b0;
            end
        end




        initial begin
            automatic T data;
            nr_checks = 0;
            forever begin
                @(pck)

                if (pck.inp_valid && pck.inp_ready && !pck.clr) begin
                    queue.push_back(pck.inp_data);
                end

                if (pck.oup_valid && pck.oup_ready) begin
                    data = queue.pop_front();

                    assert(data == pck.oup_data)
                        else $error("Mismatch, Expected: %0h Got %0h", data, pck.oup_data);
                    nr_checks++;
                end

                if (pck.clr) begin
                    queue = {};
                end

            end
        end
    endprogram

    testbench tb();
endmodule
module stream_register_tb #(
    parameter type T    = logic[7:0]
);


    logic   clk,
            rst_n,
            clr,
            inp_valid, inp_ready,
            oup_valid, oup_ready;

    T       inp_data,
            oup_data;

    int unsigned nr_checks;

    stream_register #(
        .T  (T)
    ) dut (
        .clk_i      (clk),
        .rst_ni     (rst_n),
        .clr_i      (clr),
        .testmode_i (1'b0),
        .valid_i    (inp_valid),
        .ready_o    (inp_ready),
        .data_i     (inp_data),
        .valid_o    (oup_valid),
        .ready_i    (oup_ready),
        .data_o     (oup_data)
    );

    initial begin
        clk = 1'b0;
        rst_n = 1'b0;
        repeat(8)
            #10ns clk = ~clk;

        rst_n = 1'b1;
        forever
            #10ns clk = ~clk;
    end


    initial begin
        #100ms
        $display("Checked %d stimuli", nr_checks);
        $stop;
    end

    class random_action_t;
        rand logic [1:0] action;

        constraint random_action {
            action dist {
                0 := 40,
                1 := 40,
                3 := 2,
                0 := 0
            };
        }
    endclass

    program testbench ();
        logic[7:0] queue [$];

        clocking cb @(posedge clk);
            default input #2 output #4;
            output clr, inp_data, inp_valid, oup_ready;
            input inp_ready, oup_valid, oup_data;
        endclocking

        clocking pck @(posedge clk);
            default input #2 output #4;
            input clr, inp_data, inp_valid, inp_ready, oup_data, oup_valid, oup_ready;
        endclocking




        initial begin
            automatic random_action_t random_action = new();

            cb.clr <= 1'b0;

            wait (rst_n == 1'b1);
            cb.inp_valid <= 1'b0;

            forever begin
                void'(random_action.randomize());
                repeat($urandom_range(0, 8)) @(cb);

                case (random_action.action)
                    0: begin
                        cb.inp_data     <= $urandom_range(0,256);
                        cb.inp_valid    <= 1'b1;
                    end
                    1: begin
                        cb.clr <= 1'b0;
                        cb.inp_data     <= $urandom_range(0,256);
                        cb.inp_valid    <= 1'b0;
                    end
                    default: begin
                        cb.clr          <= 1'b1;
                        cb.inp_valid    <= 1'b0;
                        @(cb);
                        cb.clr          <= 1'b0;
                    end
                endcase
            end
        end

        initial begin

            wait (rst_n == 1'b1);

            forever begin
                @(cb)
                cb.oup_ready    <= 1'b1;
                repeat($urandom_range(0, 8)) @(cb);
                cb.oup_ready    <= 1'b0;
            end
        end




        initial begin
            automatic T data;
            nr_checks = 0;
            forever begin
                @(pck)

                if (pck.inp_valid && pck.inp_ready && !pck.clr) begin
                    queue.push_back(pck.inp_data);
                end

                if (pck.oup_valid && pck.oup_ready) begin
                    data = queue.pop_front();

                    assert(data == pck.oup_data)
                        else $error("Mismatch, Expected: %0h Got %0h", data, pck.oup_data);
                    nr_checks++;
                end

                if (pck.clr) begin
                    queue = {};
                end

            end
        end
    endprogram

    testbench tb();
endmodule