data/full_repos/permissive/435516446/MIPS/Execute_TEST.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/Execute_TEST.v:53: Unsupported: Ignoring delay on this delayed statement.\n always #25 clock = ~clock;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/Execute_TEST.v:54: Unsupported: Ignoring delay on this delayed statement.\n always #50 ALUReadData1 = $random;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/Execute_TEST.v:55: Unsupported: Ignoring delay on this delayed statement.\n always #50 ALUReadData2 = $random;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/Execute_TEST.v:56: Unsupported: Ignoring delay on this delayed statement.\n always #50 immediate = $random;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/Execute_TEST.v:57: Unsupported: Ignoring delay on this delayed statement.\n always #50 funct = $random;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/Execute_TEST.v:58: Unsupported: Ignoring delay on this delayed statement.\n always #50 ALUOp = $random;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/Execute_TEST.v:59: Unsupported: Ignoring delay on this delayed statement.\n always #50 ALUSrc = $random;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/435516446/MIPS/Execute_TEST.v:72: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: data/full_repos/permissive/435516446/MIPS/Execute_TEST.v:41: Cannot find file containing module: \'Execute\'\n Execute uut (\n ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/Execute\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/Execute.v\n             data/full_repos/permissive/435516446/MIPS,data/full_repos/permissive/435516446/Execute.sv\n             Execute\n             Execute.v\n             Execute.sv\n             obj_dir/Execute\n             obj_dir/Execute.v\n             obj_dir/Execute.sv\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/Execute_TEST.v:57: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                           : ... In instance Execute_TEST\n always #50 funct = $random;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/Execute_TEST.v:58: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                           : ... In instance Execute_TEST\n always #50 ALUOp = $random;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/435516446/MIPS/Execute_TEST.v:59: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n                                                                           : ... In instance Execute_TEST\n always #50 ALUSrc = $random;\n                   ^\n%Error: Exiting due to 1 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Execute_TEST;


	reg clock;
	reg [31:0] ALUReadData1;
	reg [31:0] ALUReadData2;
	reg [31:0] immediate;
	reg [5:0] funct;
	reg [2:0] ALUOp;
	reg ALUSrc;


	wire [31:0] ALUResult;
	wire zero;


	Execute uut (
		.clock(clock), 
		.ALUReadData1(ALUReadData1), 
		.ALUReadData2(ALUReadData2), 
		.immediate(immediate), 
		.funct(funct), 
		.ALUOp(ALUOp), 
		.ALUSrc(ALUSrc), 
		.ALUResult(ALUResult), 
		.zero(zero)
	);

	always #25 clock = ~clock;
	always #50 ALUReadData1 = $random;
	always #50 ALUReadData2 = $random;
	always #50 immediate = $random;
	always #50 funct = $random;
	always #50 ALUOp = $random;
	always #50 ALUSrc = $random;
	
	initial begin

		clock = 0;
		ALUReadData1 = 0;
		ALUReadData2 = 0;
		immediate = 0;
		funct = 0;
		ALUOp = 0;
		ALUSrc = 0;


		#100;
        


	end
      
endmodule
module Execute_TEST;



	reg clock;
	reg [31:0] ALUReadData1;
	reg [31:0] ALUReadData2;
	reg [31:0] immediate;
	reg [5:0] funct;
	reg [2:0] ALUOp;
	reg ALUSrc;


	wire [31:0] ALUResult;
	wire zero;


	Execute uut (
		.clock(clock), 
		.ALUReadData1(ALUReadData1), 
		.ALUReadData2(ALUReadData2), 
		.immediate(immediate), 
		.funct(funct), 
		.ALUOp(ALUOp), 
		.ALUSrc(ALUSrc), 
		.ALUResult(ALUResult), 
		.zero(zero)
	);

	always #25 clock = ~clock;
	always #50 ALUReadData1 = $random;
	always #50 ALUReadData2 = $random;
	always #50 immediate = $random;
	always #50 funct = $random;
	always #50 ALUOp = $random;
	always #50 ALUSrc = $random;
	
	initial begin

		clock = 0;
		ALUReadData1 = 0;
		ALUReadData2 = 0;
		immediate = 0;
		funct = 0;
		ALUOp = 0;
		ALUSrc = 0;


		#100;
        


	end
      
endmodule