data/full_repos/permissive/431487364/src/core/pc_reg.v
1: b'%Error: data/full_repos/permissive/431487364/src/core/pc_reg.v:9: Cannot find include file: ../headers/buceros_header.v\n`include "../headers/buceros_header.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/431487364/src/core,data/full_repos/permissive/431487364/../headers/buceros_header.v\n             data/full_repos/permissive/431487364/src/core,data/full_repos/permissive/431487364/../headers/buceros_header.v.v\n             data/full_repos/permissive/431487364/src/core,data/full_repos/permissive/431487364/../headers/buceros_header.v.sv\n             ../headers/buceros_header.v\n             ../headers/buceros_header.v.v\n             ../headers/buceros_header.v.sv\n             obj_dir/../headers/buceros_header.v\n             obj_dir/../headers/buceros_header.v.v\n             obj_dir/../headers/buceros_header.v.sv\n%Error: data/full_repos/permissive/431487364/src/core/pc_reg.v:16: Define or directive not defined: \'`InstAddrBus\'\n    input  wire [`InstAddrBus] jmp_addr_i,\n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/src/core/pc_reg.v:16: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n    input  wire [`InstAddrBus] jmp_addr_i,\n                             ^\n%Error: data/full_repos/permissive/431487364/src/core/pc_reg.v:18: syntax error, unexpected output, expecting IDENTIFIER or do or final\n    output reg  [`InstAddrBus] pc_o\n    ^~~~~~\n%Error: data/full_repos/permissive/431487364/src/core/pc_reg.v:18: Define or directive not defined: \'`InstAddrBus\'\n    output reg  [`InstAddrBus] pc_o\n                 ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/431487364/src/core/pc_reg.v:23: Define or directive not defined: \'`PC_RST_ADDR\'\n            pc_o <= `PC_RST_ADDR;\n                    ^~~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n'
module pc_reg (
    input  wire                clk,
    input  wire                rst_n,

    input  wire                jmp_en_i,
    input  wire [`InstAddrBus] jmp_addr_i,
    input  wire                hold_i,
    output reg  [`InstAddrBus] pc_o
);

    always @(posedge clk or negedge rst_n) begin
        if(~rst_n) begin
            pc_o <= `PC_RST_ADDR;
        end else if(hold_i) begin
            pc_o <= pc_o;
        end else if(jmp_en_i) begin
            pc_o <= jmp_addr_i;
        end else begin
            pc_o <= pc_o + 32'd4;
        end
    end

endmodule
module pc_reg (
    input  wire                clk,
    input  wire                rst_n,

    input  wire                jmp_en_i,
    input  wire [`InstAddrBus] jmp_addr_i,
    input  wire                hold_i,
    output reg  [`InstAddrBus] pc_o
);


    always @(posedge clk or negedge rst_n) begin
        if(~rst_n) begin
            pc_o <= `PC_RST_ADDR;
        end else if(hold_i) begin
            pc_o <= pc_o;
        end else if(jmp_en_i) begin
            pc_o <= jmp_addr_i;
        end else begin
            pc_o <= pc_o + 32'd4;
        end
    end

endmodule