data/full_repos/permissive/405799749/amg_new/mult/Unsigned/8/8/Simple_PPG/Wallace_tree/Carry_look-ahead_adder/module.v
data/verilator_xmls/ce7719b1-d539-4194-9332-65b22bd546d7.xml
module UBPureCLA_15_5 (S, X, Y);
  output [16:5] S;
  input [15:5] X;
  input [15:5] Y;
  wire C;
  UBPriCLA_15_5 U0 (S, X, Y, C);
  UBZero_5_5 U1 (C);
endmodule
module UBPureCLA_15_5 (S, X, Y);

  output [16:5] S;
  input [15:5] X;
  input [15:5] Y;
  wire C;
  UBPriCLA_15_5 U0 (S, X, Y, C);
  UBZero_5_5 U1 (C);
endmodule