data/full_repos/permissive/529963034/src/user_module_341710255833481812.v
data/verilator_xmls/b9a04641-a081-4e3d-a04a-f3cbee3b4cf1.xml
module user_module_341710255833481812(
  input [7:0] io_in,
  output [7:0] io_out
);

wire CLK;
assign CLK = io_in[0];
wire RST;
assign RST = io_in[1];
wire [3:0] ancilla;
assign ancilla = io_in[6:3];

wire [4:0] correction;
wire [1:0] axis;
assign io_out = {1'b0, axis, correction};

  CodeLUT_339800239192932947 codelut(
    CLK, RST,
    ancilla,
    correction,
    axis);

endmodule
module user_module_341710255833481812(
  input [7:0] io_in,
  output [7:0] io_out
);


wire CLK;
assign CLK = io_in[0];
wire RST;
assign RST = io_in[1];
wire [3:0] ancilla;
assign ancilla = io_in[6:3];

wire [4:0] correction;
wire [1:0] axis;
assign io_out = {1'b0, axis, correction};

  CodeLUT_339800239192932947 codelut(
    CLK, RST,
    ancilla,
    correction,
    axis);

endmodule