data/full_repos/permissive/460468583/data/yosys/gatemate/mul_map.v
1: b'%Warning-WIDTH: data/full_repos/permissive/460468583/data/yosys/gatemate/mul_map.v:44: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'A\' generates 1 bits.\n                                                                                     : ... In instance __024___05FMULMXN\n   wire [A_ADJWIDTH-1:0] Aext = A;\n                              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/460468583/data/yosys/gatemate/mul_map.v:50: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'B\' generates 1 bits.\n                                                                                     : ... In instance __024___05FMULMXN\n   wire [B_ADJWIDTH-1:0] Bext = B;\n                              ^\n%Error: data/full_repos/permissive/460468583/data/yosys/gatemate/mul_map.v:54: Cannot find file containing module: \'CC_MULT\'\n   CC_MULT #(\n   ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/460468583/data/yosys/gatemate,data/full_repos/permissive/460468583/CC_MULT\n             data/full_repos/permissive/460468583/data/yosys/gatemate,data/full_repos/permissive/460468583/CC_MULT.v\n             data/full_repos/permissive/460468583/data/yosys/gatemate,data/full_repos/permissive/460468583/CC_MULT.sv\n             CC_MULT\n             CC_MULT.v\n             CC_MULT.sv\n             obj_dir/CC_MULT\n             obj_dir/CC_MULT.v\n             obj_dir/CC_MULT.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module \$__MULMXN (A, B, Y);

	parameter A_SIGNED = 0;
	parameter B_SIGNED = 0;
	parameter A_WIDTH = 1;
	parameter B_WIDTH = 1;
	parameter Y_WIDTH = 1;

	(* force_downto *)
	input [A_WIDTH-1:0] A;
	(* force_downto *)
	input [B_WIDTH-1:0] B;
	(* force_downto *)
	output [Y_WIDTH-1:0] Y;

	localparam A_ADJWIDTH = A_WIDTH + (A_SIGNED ? 0 : 1);
	localparam B_ADJWIDTH = B_WIDTH + (B_SIGNED ? 0 : 1);

	generate
		if (A_SIGNED) begin: blkA
			wire signed [A_ADJWIDTH-1:0] Aext = $signed(A);
		end
		else begin: blkA
			wire [A_ADJWIDTH-1:0] Aext = A;
		end
		if (B_SIGNED) begin: blkB
			wire signed [B_ADJWIDTH-1:0] Bext = $signed(B);
		end
		else begin: blkB
			wire [B_ADJWIDTH-1:0] Bext = B;
		end

		if (A_WIDTH >= B_WIDTH) begin
			CC_MULT #(
				.A_WIDTH(A_ADJWIDTH),
				.B_WIDTH(B_ADJWIDTH),
				.P_WIDTH(Y_WIDTH),
			) _TECHMAP_REPLACE_ (
				.A(blkA.Aext),
				.B(blkB.Bext),
				.P(Y)
			);
		end
		else begin
			CC_MULT #(
				.A_WIDTH(B_ADJWIDTH),
				.B_WIDTH(A_ADJWIDTH),
				.P_WIDTH(Y_WIDTH),
			) _TECHMAP_REPLACE_ (
				.A(blkB.Bext),
				.B(blkA.Aext),
				.P(Y)
			);
		end
	endgenerate

endmodule
module \$__MULMXN (A, B, Y);


	parameter A_SIGNED = 0;
	parameter B_SIGNED = 0;
	parameter A_WIDTH = 1;
	parameter B_WIDTH = 1;
	parameter Y_WIDTH = 1;

	(* force_downto *)
	input [A_WIDTH-1:0] A;
	(* force_downto *)
	input [B_WIDTH-1:0] B;
	(* force_downto *)
	output [Y_WIDTH-1:0] Y;

	localparam A_ADJWIDTH = A_WIDTH + (A_SIGNED ? 0 : 1);
	localparam B_ADJWIDTH = B_WIDTH + (B_SIGNED ? 0 : 1);

	generate
		if (A_SIGNED) begin: blkA
			wire signed [A_ADJWIDTH-1:0] Aext = $signed(A);
		end
		else begin: blkA
			wire [A_ADJWIDTH-1:0] Aext = A;
		end
		if (B_SIGNED) begin: blkB
			wire signed [B_ADJWIDTH-1:0] Bext = $signed(B);
		end
		else begin: blkB
			wire [B_ADJWIDTH-1:0] Bext = B;
		end

		if (A_WIDTH >= B_WIDTH) begin
			CC_MULT #(
				.A_WIDTH(A_ADJWIDTH),
				.B_WIDTH(B_ADJWIDTH),
				.P_WIDTH(Y_WIDTH),
			) _TECHMAP_REPLACE_ (
				.A(blkA.Aext),
				.B(blkB.Bext),
				.P(Y)
			);
		end
		else begin
			CC_MULT #(
				.A_WIDTH(B_ADJWIDTH),
				.B_WIDTH(A_ADJWIDTH),
				.P_WIDTH(Y_WIDTH),
			) _TECHMAP_REPLACE_ (
				.A(blkB.Bext),
				.B(blkA.Aext),
				.P(Y)
			);
		end
	endgenerate

endmodule