data/full_repos/permissive/528677531/LAB-4/Q3/qb.v
data/verilator_xmls/3ab07b3f-5c20-4c54-b0fc-3e356b6c8d54.xml
module mult2(x2,y2,p);
input [1:0]x2,y2;
output [3:0]p;
wire [1:0]a,b;
assign b[0]=x2[1]&y2[0];
assign a[0]=x2[0]&y2[1];
assign a[1]=x2[1]&y2[1];
assign b[1]=1'b0;
assign p[0]=x2[0]&y2[0];
adder2 stage0(a,b,1'b0,p[2:1],p[3]);
endmodule
module mult2(x2,y2,p);

input [1:0]x2,y2;
output [3:0]p;
wire [1:0]a,b;
assign b[0]=x2[1]&y2[0];
assign a[0]=x2[0]&y2[1];
assign a[1]=x2[1]&y2[1];
assign b[1]=1'b0;
assign p[0]=x2[0]&y2[0];
adder2 stage0(a,b,1'b0,p[2:1],p[3]);
endmodule