data/full_repos/permissive/434886680/src/adc_top.v
1: b"%Error: data/full_repos/permissive/434886680/src/adc_top.v:39: Cannot find file containing module: 'adc_core'\n  adc_core u_adc_core\n  ^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/434886680/src,data/full_repos/permissive/434886680/adc_core\n             data/full_repos/permissive/434886680/src,data/full_repos/permissive/434886680/adc_core.v\n             data/full_repos/permissive/434886680/src,data/full_repos/permissive/434886680/adc_core.sv\n             adc_core\n             adc_core.v\n             adc_core.sv\n             obj_dir/adc_core\n             obj_dir/adc_core.v\n             obj_dir/adc_core.sv\n%Error: data/full_repos/permissive/434886680/src/adc_top.v:54: Cannot find file containing module: 'spi'\n  spi u_spi\n  ^~~\n%Error: Exiting due to 2 error(s)\n"
module adc_top
  ( 
    input  wire        CLK_IN,
    input  wire        XRES_IN,
    input  wire        SS,
    input  wire        SCLK,
    inout  wire        MISO,
    input  wire        MOSI
    );


  reg clk2;

  always @(posedge CLK_IN, negedge XRES_IN)
    begin
      if (!XRES_IN)
        begin
          clk2 <= 0;
        end
      else
        begin
          clk2 <= ~clk2;
        end
    end


  wire soc;
  wire eoc;
  wire [11:0] dout;

  adc_core u_adc_core
    (
     .eoc(eoc),
     .dout(dout),
     .clk(clk2),
     .pd(1'b0),
     .s(3'b0),
     .soc(soc)
     );


  wire miso_o;
  bufif0 u_miso_buf(MISO, miso_o, SS);


  spi u_spi
    (
     .clk(clk2),
     .xres(XRES_IN),
     .sclk(SCLK),
     .ss(SS),
     .adc_soc(soc),
     .adc_data(dout),
     .miso(miso_o)
   );

endmodule
module adc_top
  ( 
    input  wire        CLK_IN,
    input  wire        XRES_IN,
    input  wire        SS,
    input  wire        SCLK,
    inout  wire        MISO,
    input  wire        MOSI
    );



  reg clk2;

  always @(posedge CLK_IN, negedge XRES_IN)
    begin
      if (!XRES_IN)
        begin
          clk2 <= 0;
        end
      else
        begin
          clk2 <= ~clk2;
        end
    end


  wire soc;
  wire eoc;
  wire [11:0] dout;

  adc_core u_adc_core
    (
     .eoc(eoc),
     .dout(dout),
     .clk(clk2),
     .pd(1'b0),
     .s(3'b0),
     .soc(soc)
     );


  wire miso_o;
  bufif0 u_miso_buf(MISO, miso_o, SS);


  spi u_spi
    (
     .clk(clk2),
     .xres(XRES_IN),
     .sclk(SCLK),
     .ss(SS),
     .adc_soc(soc),
     .adc_data(dout),
     .miso(miso_o)
   );

endmodule