data/full_repos/permissive/522095295/counter.v
data/verilator_xmls/e20e9946-ad8c-4bc9-a942-c125c5ff7d1d.xml
module counter
(
   input clk,
   input reset,
   output wire [2:0] out
);
   reg [2:0] b;
   always @ (posedge clk) begin
      if (!reset)
         if (b != 5)
	         b <= b + 1;
         else
            b <= 1;
      else 
         b <= 0;
   end

   assign out = b;
endmodule
module counter
(
   input clk,
   input reset,
   output wire [2:0] out
);

   reg [2:0] b;
   always @ (posedge clk) begin
      if (!reset)
         if (b != 5)
	         b <= b + 1;
         else
            b <= 1;
      else 
         b <= 0;
   end

   assign out = b;
endmodule