data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top_tb.v
1: b'%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top_tb.v:2: Cannot find include file: define.v\n`include "define.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/430337995/unibuf_systolic_tb/src,data/full_repos/permissive/430337995/define.v\n             data/full_repos/permissive/430337995/unibuf_systolic_tb/src,data/full_repos/permissive/430337995/define.v.v\n             data/full_repos/permissive/430337995/unibuf_systolic_tb/src,data/full_repos/permissive/430337995/define.v.sv\n             define.v\n             define.v.v\n             define.v.sv\n             obj_dir/define.v\n             obj_dir/define.v.v\n             obj_dir/define.v.sv\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top_tb.v:3: Cannot find include file: matrix_define.v\n`include "matrix_define.v" \n         ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top_tb.v:13: Define or directive not defined: \'`WORD_ADDR_BITS\'\n    reg [`WORD_ADDR_BITS-1:0]   data_total;\n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top_tb.v:19: Define or directive not defined: \'`WORD_SIZE\'\n    reg [`WORD_SIZE-1:0] GOLDEN_A [0:`WORD_CNT-1];\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top_tb.v:19: Define or directive not defined: \'`WORD_CNT\'\n    reg [`WORD_SIZE-1:0] GOLDEN_A [0:`WORD_CNT-1];\n                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top_tb.v:20: Define or directive not defined: \'`WORD_SIZE\'\n    reg [`WORD_SIZE-1:0] GOLDEN_B [0:`WORD_CNT-1];\n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top_tb.v:20: Define or directive not defined: \'`WORD_CNT\'\n    reg [`WORD_SIZE-1:0] GOLDEN_B [0:`WORD_CNT-1];\n                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top_tb.v:23: Define or directive not defined: \'`CYCLE\'\n    always #(`CYCLE/2) clk = ~clk;\n             ^~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top_tb.v:23: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n    always #(`CYCLE/2) clk = ~clk;\n                   ^\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top_tb.v:42: Define or directive not defined: \'`CYCLE\'\n        #(`CYCLE*10) rst = 1\'b1; data_total = `O_MAX; \n          ^~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top_tb.v:42: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n        #(`CYCLE*10) rst = 1\'b1; data_total = `O_MAX; \n                ^\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top_tb.v:42: Define or directive not defined: \'`O_MAX\'\n        #(`CYCLE*10) rst = 1\'b1; data_total = `O_MAX; \n                                              ^~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top_tb.v:42: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        #(`CYCLE*10) rst = 1\'b1; data_total = `O_MAX; \n                                                    ^\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top_tb.v:52: Define or directive not defined: \'`CYCLE\'\n        #(`CYCLE * 5)\n          ^~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top_tb.v:52: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n        #(`CYCLE * 5)\n                 ^\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top_tb.v:54: syntax error, unexpected \'@\'\n        @(posedge ack) instr_valid = 1\'b0; instr = 0;\n        ^\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top_tb.v:55: Define or directive not defined: \'`CYCLE\'\n        #(`CYCLE * 5);\n          ^~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top_tb.v:55: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n        #(`CYCLE * 5);\n                 ^\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top_tb.v:57: syntax error, unexpected \'@\'\n        @(posedge ack) instr_valid = 1\'b0; instr = 0;\n        ^\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top_tb.v:59: Unsupported: wait statements\n        wait(done == 1);\n        ^~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top_tb.v:63: Define or directive not defined: \'`O_MAX\'\n        for(i=0;i<`O_MAX; i=i+1) begin\n                  ^~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top_tb.v:63: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        for(i=0;i<`O_MAX; i=i+1) begin\n                        ^\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top_tb.v:63: syntax error, unexpected \')\', expecting \';\'\n        for(i=0;i<`O_MAX; i=i+1) begin\n                               ^\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top_tb.v:85: syntax error, unexpected \'(\', expecting IDENTIFIER\n        check_err(err);\n                  ^~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top_tb.v:98: syntax error, unexpected $display\n      $display("\\n");\n      ^~~~~~~~\n%Error: data/full_repos/permissive/430337995/unibuf_systolic_tb/src/top_tb.v:118: syntax error, unexpected $display\n      $display("\\n");\n      ^~~~~~~~\n%Error: Cannot continue\n'
module top_tb;


    reg clk;
    reg rst;
    reg instr_valid;
    reg [104:0] instr;

    reg [`WORD_ADDR_BITS-1:0]   data_total;
    wire    ack;
    wire    done;
    integer err_A, err_B, err, i, j;


    reg [`WORD_SIZE-1:0] GOLDEN_A [0:`WORD_CNT-1];
    reg [`WORD_SIZE-1:0] GOLDEN_B [0:`WORD_CNT-1];
    reg [104:0]           INSTR    [0:9];

    always #(`CYCLE/2) clk = ~clk;

    TOP top_i(
        .clk            (clk            ),
        .rst            (rst            ),
        .instr_valid    (instr_valid    ),
        .instr          (instr          ),
        .data_total     (data_total     ),
        .ack            (ack            ),
        .done           (done           )
    );

    initial begin
        for(i=0;i<10;i=i+1) begin
            INSTR[i] = 0;
        end

        clk = 1'b1; rst = 1'b0; instr_valid = 1'b0; instr = 0;
        err = 0; data_total = 0;
        #(`CYCLE*10) rst = 1'b1; data_total = `O_MAX; 

        $readmemb("build/A_input.bin", top_i.GBUFF_A.gbuff);
        $readmemb("build/B_input.bin", top_i.GBUFF_B.gbuff);
        $readmemb("build/A_golden.bin", GOLDEN_A);
        $readmemb("build/B_golden.bin", GOLDEN_B);
        $readmemb("build/instruction.bin", INSTR);

        $display("Data load finished\n");

        #(`CYCLE * 5)
        @(posedge clk) instr_valid = 1'b1; instr = INSTR[0];
        @(posedge ack) instr_valid = 1'b0; instr = 0;
        #(`CYCLE * 5);
        @(posedge clk) instr_valid = 1'b1; instr = INSTR[1];
        @(posedge ack) instr_valid = 1'b0; instr = 0;

        wait(done == 1);
        $display("\nSimulation Done\n");
        err = 0;

        for(i=0;i<`O_MAX; i=i+1) begin
            $display("%2d ================================================= %2d", i, i);
            for(j=0;j<16;j=j+1) begin
                if(GOLDEN_A[i][(127-j*8) -:8] !== top_i.GBUFF_O_uni.gbuff[i][(127-j*8) -:8]) begin
                    $write("GBUFF_O_uni[%2d][%3d:%3d] = %2h, expect = %2h ",
                    i, 127-j*8, 127-(j+1)*8+1, top_i.GBUFF_O_uni.gbuff[i][(127-j*8) -:8], GOLDEN_A[i][(127-j*8) -:8]);
                    err = err +1;
                end else begin
                    $write("GBUFF_O_uni[%2d][%3d:%3d] = %2h, pass!       ",  
                    i,127-j*8, 127-(j+1)*8+1, top_i.GBUFF_O_uni.gbuff[i][(127-j*8) -:8]);
                end

                if(GOLDEN_B[i][(127-j*8) -:8] !== top_i.GBUFF_O_wei.gbuff[i][(127-j*8) -:8]) begin
                    $display("GBUFF_O_wei[%2d][%3d:%3d] = %2h, expect = %2h ",
                    i, 127-j*8, 127-(j+1)*8+1, top_i.GBUFF_O_wei.gbuff[i][(127-j*8) -:8], GOLDEN_B[i][(127-j*8) -:8]);
                    err = err +1;
                end else begin
                    $display("GBUFF_O_wei[%2d][%3d:%3d] = %2h, pass!       ", 
                    i, 127-j*8, 127-(j+1)*8+1, top_i.GBUFF_O_wei.gbuff[i][(127-j*8) -:8]);
                end
            end
        end
        check_err(err);
        $finish;
    end





  task check_err;
    input integer err;

    if( err == 0 )
    begin
      $display("\n");
      $display("                                             / \\  //\\                      ");
      $display("                              |\\___/|      /   \\//  \\\\                   ");
      $display("                             /0  0  \\__  /    //  | \\ \\                   ");
      $display("                            /     /  \\/_/    //   |  \\  \\                 ");
      $display("                            @_^_@'/   \\/_   //    |   \\   \\               ");
      $display("                            //_^_/     \\/_ //     |    \\    \\             ");
      $display("                         ( //) |        \\///      |     \\     \\           ");
      $display("                        ( / /) _|_ /   )  //       |      \\     _\\         ");
      $display("                      ( // /) '/,_ _ _/  ( ; -.    |    _ _\\.-~        .-~~~^-.                      ");
      $display(" ********************(( / / )) ,-{        _      `-.|.-~-.            .~         `.                   ");
      $display(" **                   (( // / ))  '/\\      /                 ~-. _ .-~      .-~^-.  \                ");
      $display(" **  Congratulations!  (( /// ))      `.   {            }                    /      \  \              ");
      $display(" **  Simulation Passed!  (( / ))     .----~-.\\        \\-'                .~         \  `. \^-.      ");
      $display(" **                      **           ///.----..>        \\             _ -~             `.  ^-`  ^-_ ");
      $display(" **************************             ///-._ _ _ _ _ _ _}^ - - - -- ~                     ~-- ,.-~  ");
      $display("\n");
    end
    else
    begin
      $display("\n");
      $display(" **************************    __ __   ");
      $display(" **                      **   /--\\/ \\ ");
      $display(" **  Awwwww              **  |   /   | ");
      $display(" **  Simulation Failed!  **  |-    --| ");
      $display(" **                      **   \\__-*_/ ");
      $display(" **************************            ");
      $display(" Total %4d errors\n", err);
    end
  endtask



endmodule
module top_tb;



    reg clk;
    reg rst;
    reg instr_valid;
    reg [104:0] instr;

    reg [`WORD_ADDR_BITS-1:0]   data_total;
    wire    ack;
    wire    done;
    integer err_A, err_B, err, i, j;


    reg [`WORD_SIZE-1:0] GOLDEN_A [0:`WORD_CNT-1];
    reg [`WORD_SIZE-1:0] GOLDEN_B [0:`WORD_CNT-1];
    reg [104:0]           INSTR    [0:9];

    always #(`CYCLE/2) clk = ~clk;

    TOP top_i(
        .clk            (clk            ),
        .rst            (rst            ),
        .instr_valid    (instr_valid    ),
        .instr          (instr          ),
        .data_total     (data_total     ),
        .ack            (ack            ),
        .done           (done           )
    );

    initial begin
        for(i=0;i<10;i=i+1) begin
            INSTR[i] = 0;
        end

        clk = 1'b1; rst = 1'b0; instr_valid = 1'b0; instr = 0;
        err = 0; data_total = 0;
        #(`CYCLE*10) rst = 1'b1; data_total = `O_MAX; 

        $readmemb("build/A_input.bin", top_i.GBUFF_A.gbuff);
        $readmemb("build/B_input.bin", top_i.GBUFF_B.gbuff);
        $readmemb("build/A_golden.bin", GOLDEN_A);
        $readmemb("build/B_golden.bin", GOLDEN_B);
        $readmemb("build/instruction.bin", INSTR);

        $display("Data load finished\n");

        #(`CYCLE * 5)
        @(posedge clk) instr_valid = 1'b1; instr = INSTR[0];
        @(posedge ack) instr_valid = 1'b0; instr = 0;
        #(`CYCLE * 5);
        @(posedge clk) instr_valid = 1'b1; instr = INSTR[1];
        @(posedge ack) instr_valid = 1'b0; instr = 0;

        wait(done == 1);
        $display("\nSimulation Done\n");
        err = 0;

        for(i=0;i<`O_MAX; i=i+1) begin
            $display("%2d ================================================= %2d", i, i);
            for(j=0;j<16;j=j+1) begin
                if(GOLDEN_A[i][(127-j*8) -:8] !== top_i.GBUFF_O_uni.gbuff[i][(127-j*8) -:8]) begin
                    $write("GBUFF_O_uni[%2d][%3d:%3d] = %2h, expect = %2h ",
                    i, 127-j*8, 127-(j+1)*8+1, top_i.GBUFF_O_uni.gbuff[i][(127-j*8) -:8], GOLDEN_A[i][(127-j*8) -:8]);
                    err = err +1;
                end else begin
                    $write("GBUFF_O_uni[%2d][%3d:%3d] = %2h, pass!       ",  
                    i,127-j*8, 127-(j+1)*8+1, top_i.GBUFF_O_uni.gbuff[i][(127-j*8) -:8]);
                end

                if(GOLDEN_B[i][(127-j*8) -:8] !== top_i.GBUFF_O_wei.gbuff[i][(127-j*8) -:8]) begin
                    $display("GBUFF_O_wei[%2d][%3d:%3d] = %2h, expect = %2h ",
                    i, 127-j*8, 127-(j+1)*8+1, top_i.GBUFF_O_wei.gbuff[i][(127-j*8) -:8], GOLDEN_B[i][(127-j*8) -:8]);
                    err = err +1;
                end else begin
                    $display("GBUFF_O_wei[%2d][%3d:%3d] = %2h, pass!       ", 
                    i, 127-j*8, 127-(j+1)*8+1, top_i.GBUFF_O_wei.gbuff[i][(127-j*8) -:8]);
                end
            end
        end
        check_err(err);
        $finish;
    end





  task check_err;
    input integer err;

    if( err == 0 )
    begin
      $display("\n");
      $display("                                             / \\  //\\                      ");
      $display("                              |\\___/|      /   \\//  \\\\                   ");
      $display("                             /0  0  \\__  /    //  | \\ \\                   ");
      $display("                            /     /  \\/_/    //   |  \\  \\                 ");
      $display("                            @_^_@'/   \\/_   //    |   \\   \\               ");
      $display("                            //_^_/     \\/_ //     |    \\    \\             ");
      $display("                         ( //) |        \\///      |     \\     \\           ");
      $display("                        ( / /) _|_ /   )  //       |      \\     _\\         ");
      $display("                      ( // /) '/,_ _ _/  ( ; -.    |    _ _\\.-~        .-~~~^-.                      ");
      $display(" ********************(( / / )) ,-{        _      `-.|.-~-.            .~         `.                   ");
      $display(" **                   (( // / ))  '/\\      /                 ~-. _ .-~      .-~^-.  \                ");
      $display(" **  Congratulations!  (( /// ))      `.   {            }                    /      \  \              ");
      $display(" **  Simulation Passed!  (( / ))     .----~-.\\        \\-'                .~         \  `. \^-.      ");
      $display(" **                      **           ///.----..>        \\             _ -~             `.  ^-`  ^-_ ");
      $display(" **************************             ///-._ _ _ _ _ _ _}^ - - - -- ~                     ~-- ,.-~  ");
      $display("\n");
    end
    else
    begin
      $display("\n");
      $display(" **************************    __ __   ");
      $display(" **                      **   /--\\/ \\ ");
      $display(" **  Awwwww              **  |   /   | ");
      $display(" **  Simulation Failed!  **  |-    --| ");
      $display(" **                      **   \\__-*_/ ");
      $display(" **************************            ");
      $display(" Total %4d errors\n", err);
    end
  endtask



endmodule