data/full_repos/permissive/42149584/Lab6-Part1/lab6phase1I2C2015fall_tb.v
1: b'%Error: data/full_repos/permissive/42149584/Lab6-Part1/lab6phase1I2C2015fall_tb.v:22: syntax error, unexpected \'.\', expecting \'=\'\n defparam uut.ControlUnit.Timer.Divider=2;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/lab6phase1I2C2015fall_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n always #4 clock=~clock;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/42149584/Lab6-Part1/lab6phase1I2C2015fall_tb.v:34: Unsupported: fork statements\n initial fork\n         ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/lab6phase1I2C2015fall_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #0 Reset=1;  #12 Reset=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/lab6phase1I2C2015fall_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #0 Reset=1;  #12 Reset=0;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/lab6phase1I2C2015fall_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #0 Go=0;  #21 Go=1;     #61 Go=0;   #470 Go=1;  #479 Go=0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/lab6phase1I2C2015fall_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #0 Go=0;  #21 Go=1;     #61 Go=0;   #470 Go=1;  #479 Go=0;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/lab6phase1I2C2015fall_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #0 Go=0;  #21 Go=1;     #61 Go=0;   #470 Go=1;  #479 Go=0;\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/lab6phase1I2C2015fall_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #0 Go=0;  #21 Go=1;     #61 Go=0;   #470 Go=1;  #479 Go=0;\n                                     ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/lab6phase1I2C2015fall_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #0 Go=0;  #21 Go=1;     #61 Go=0;   #470 Go=1;  #479 Go=0;\n                                                 ^\n%Warning-STMTDLY: data/full_repos/permissive/42149584/Lab6-Part1/lab6phase1I2C2015fall_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #600 $stop;\n ^\n%Error: Exiting due to 2 error(s), 9 warning(s)\n'
module lab6phase1I2C2015fall_tb;

	reg Go, Reset, clock;

	wire SCL, ClockLocked;
	wire [2:0] State=uut.ControlUnit.State;
	wire [2:0] NextState=uut.ControlUnit.NextState;
	wire ControlClock=uut.ControlUnit.Clock;
	wire ClockI2C=uut.ControlUnit.ClockI2C;
	wire BaudEnable=uut.ControlUnit.BaudEnable;
	wire StartStopAck=uut.ControlUnit.StartStopAck;
	wire ShiftOrHold=uut.DataUnit.ShiftOrHold;
	wire ShiftDataOut=uut.DataUnit.ShiftDataOut;
	
	wire SDA;

	lab6phase1I2C2015fall uut(1'b0,Go,Reset,ClockLocked,SCL,SDA);
	
	assign uut.ClockOut=clock;
	defparam uut.ControlUnit.Timer.Divider=2;
	defparam uut.BaudRate=3;
	defparam uut.ClockFrequency=12;

	
	wire Timeout=uut.ControlUnit.Timeout;
	wire [3:0] DataCounter = uut.ControlUnit.DataCounter;
	
	wire [15:0] baud_count = uut.DataUnit.BaudUnit.baud_count;

	initial begin Go = 0;  Reset = 0;  clock = 0; end
	always #4 clock=~clock;
	initial fork
	#0 Reset=1;  #12 Reset=0;
	#0 Go=0;  #21 Go=1;     #61 Go=0;   #470 Go=1;  #479 Go=0;
	#600 $stop;
	join
      
endmodule
module lab6phase1I2C2015fall_tb;


	reg Go, Reset, clock;

	wire SCL, ClockLocked;
	wire [2:0] State=uut.ControlUnit.State;
	wire [2:0] NextState=uut.ControlUnit.NextState;
	wire ControlClock=uut.ControlUnit.Clock;
	wire ClockI2C=uut.ControlUnit.ClockI2C;
	wire BaudEnable=uut.ControlUnit.BaudEnable;
	wire StartStopAck=uut.ControlUnit.StartStopAck;
	wire ShiftOrHold=uut.DataUnit.ShiftOrHold;
	wire ShiftDataOut=uut.DataUnit.ShiftDataOut;
	
	wire SDA;

	lab6phase1I2C2015fall uut(1'b0,Go,Reset,ClockLocked,SCL,SDA);
	
	assign uut.ClockOut=clock;
	defparam uut.ControlUnit.Timer.Divider=2;
	defparam uut.BaudRate=3;
	defparam uut.ClockFrequency=12;

	
	wire Timeout=uut.ControlUnit.Timeout;
	wire [3:0] DataCounter = uut.ControlUnit.DataCounter;
	
	wire [15:0] baud_count = uut.DataUnit.BaudUnit.baud_count;

	initial begin Go = 0;  Reset = 0;  clock = 0; end
	always #4 clock=~clock;
	initial fork
	#0 Reset=1;  #12 Reset=0;
	#0 Go=0;  #21 Go=1;     #61 Go=0;   #470 Go=1;  #479 Go=0;
	#600 $stop;
	join
      
endmodule