data/full_repos/permissive/455657973/datapath_tb.v
1: b'%Error: data/full_repos/permissive/455657973/datapath_tb.v:8: syntax error, unexpected reg, expecting IDENTIFIER or \'=\' or do or final\n reg RAM_write, MDR_enable, MDRout, MAR_enable, IR_enable, MDR_read;\n ^~~\n%Warning-STMTDLY: data/full_repos/permissive/455657973/datapath_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n  forever #10 Clock = ~ Clock;\n          ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/455657973/datapath_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n  Default   : #40 Present_state = Reg_load1a;\n              ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/datapath_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n  Reg_load1a  : #40 Present_state = Reg_load1b;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/datapath_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n  Reg_load1b  : #40 Present_state = Reg_load2a;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/datapath_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n  Reg_load2a  : #40 Present_state = Reg_load2b;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/datapath_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n  Reg_load2b  : #40 Present_state = Reg_load3a;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/datapath_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n  Reg_load3a  : #40 Present_state = Reg_load3b;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/datapath_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n  Reg_load3b  : #40 Present_state = T0;\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/datapath_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n  T0     : #40 Present_state = T1;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/datapath_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n  T1     : #40 Present_state = T2;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/datapath_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n  T2     : #40 Present_state = T3;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/datapath_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n  T3     : #40 Present_state = T4;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/datapath_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n  T4     : #40 Present_state = T5;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/datapath_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n    #10 Read <= 1; MDRin <= 1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/datapath_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n    #15 Read <= 0; MDRin <= 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/datapath_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n    #10 MDRout<= 1; R2in <= 1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/datapath_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n    #15 MDRout<= 0; R2in <= 0;      \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/datapath_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n    #10 Read <= 1; MDRin <= 1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/datapath_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n    #15 Read <= 0; MDRin <= 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/datapath_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n    #10 MDRout<= 1; R4in <= 1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/datapath_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n    #15 MDRout<= 0; R4in <= 0;   \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/datapath_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n    #10 Read <= 1; MDRin <= 1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/datapath_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n    #15 Read <= 0; MDRin <= 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/datapath_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n    #10 MDRout<= 1; R5in <= 1;  \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/455657973/datapath_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n    #15 MDRout<= 0; R5in <= 0; \n    ^\n%Error: data/full_repos/permissive/455657973/datapath_tb.v:121: syntax error, unexpected IDENTIFIER\n    Read <= 1; MDRin <= 1;\n    ^~~~\n%Error: Exiting due to 2 error(s), 25 warning(s)\n'
module datapath_tb; 	
	reg clk, clr;
	reg IncPC, CON_enable;
	reg [31:0] Mdatain;
	reg [4:0] opCode, 
	reg RAM_write, MDR_enable, MDRout, MAR_enable, IR_enable, MDR_read;
	reg Gra, Grb, Grc;
	reg HI_enable, LO_enable, ZHighIn, ZLowIn, Y_enable, PC_enable, OutPort_enable;
	reg InPortout, PCout, Yout, ZLowout, ZHighout, LOout, HIout, BAout, Cout;
	wire [31:0] OutPort_output;
	reg [31:0] InPort_input;
	reg R_in, R_out, Cin, branch_flag;

parameter	Default = 4'b0000, Reg_load1a= 4'b0001, Reg_load1b= 4'b0010,
					Reg_load2a = 4'b0011, Reg_load2b = 4'b0100, Reg_load3a = 4'b0101,
					Reg_load3b = 4'b0110, T0= 4'b0111, T1= 4'b1000,T2= 4'b1001, T3= 4'b1010, T4= 4'b1011, T5= 4'b1100;
reg	[3:0] Present_state = Default;

datapath DUT(	
	OutPort_output, clk, clr, IncPC, CONin, Mdatain,
	opCode, RAM_write, MDR_enable, MDR_enable, MAR_enable,  IR_enable, MDR_read,
	Gra, Grb, Grc, HI_enable, LO_enable, ZHighIn, ZLowIn, Y_enable, PC_enable, OutPort_enable,
    InPortout, PCout, Yout, ZLowout, ZHighout, LOout, HIout, BAout, Cout, InPort_input,
	R_in, R_out, Cin, branch_flag          	
);

initial 
	begin
		Clear = 0;
		Clock = 0;
		forever #10 Clock = ~ Clock;
end

always @(posedge Clock)
begin
	case (Present_state)
		Default			:	#40 Present_state = Reg_load1a;
		Reg_load1a		:	#40 Present_state = Reg_load1b;
		Reg_load1b		:	#40 Present_state = Reg_load2a;
		Reg_load2a		:	#40 Present_state = Reg_load2b;
		Reg_load2b		:	#40 Present_state = Reg_load3a;
		Reg_load3a		:	#40 Present_state = Reg_load3b;
		Reg_load3b		:	#40 Present_state = T0;
		T0					:	#40 Present_state = T1;
		T1					:	#40 Present_state = T2;
		T2					:	#40 Present_state = T3;
		T3					:	#40 Present_state = T4;
		T4					:	#40 Present_state = T5;
		endcase
	end

always @(Present_state)
begin
	case (Present_state)
		Default: begin
						PCout <= 0;   ZLowout <= 0; ZHighout <= 0;  MDRout<= 0;
						R2out <= 0;   R4out <= 0;   MARin <= 0;   ZLowIn <= 0;  
						PCin <=0;   MDRin <= 0;   IRin  <= 0;   Yin <= 0;  
						IncPC <= 0;   Read <= 0;   opCode <= 5'b00000;  branch_flag <=0;
						HIout<=0;  LOout<=0; InPortout<=0; Cout<=0;
						R5in <= 0; R2in <= 0; R4in <= 0; Mdatain <= 32'h00000000;
		end
		Reg_load1a: begin 
				Mdatain<= 32'h00000022;
				Read = 0; MDRin = 0;
				#10 Read <= 1; MDRin <= 1;  
				#15 Read <= 0; MDRin <= 0;
		end
		Reg_load1b: begin
				#10 MDRout<= 1; R2in <= 1;  
				#15 MDRout<= 0; R2in <= 0;
		end
		Reg_load2a: begin 
				Mdatain <= 32'h00000011;
				#10 Read <= 1; MDRin <= 1;  
				#15 Read <= 0; MDRin <= 0;
		end
		Reg_load2b: begin
				#10 MDRout<= 1; R4in <= 1;  
				#15 MDRout<= 0; R4in <= 0;
		end
		Reg_load3a: begin 
				Mdatain <= 32'h00000026;
				#10 Read <= 1; MDRin <= 1;  
				#15 Read <= 0; MDRin <= 0;
		end
		Reg_load3b: begin
				#10 MDRout<= 1; R5in <= 1;  
				#15 MDRout<= 0; R5in <= 0;
		end
	
		T0: begin
				PCout<= 1; MARin <= 1; IncPC <= 1; ZLowIn <= 1;
		end
		T1: begin
				Mdatain <= 32'h4A920000; Read <= 1; MDRin <= 1; ZLowout<= 1; PCin <= 1; PCout <=0;
				
				
		end
		T2: begin								
				MDRout<= 1; IRin <= 1; ZLowout<= 0;
		end
		T3: begin
				MDRout<=0; R2out<= 1; Yin <= 1;
		end
		T4: begin
				Yin <= 0; R2out <=0; R4out<= 1; opCode <= 5'b00100; ZLowIn <= 1; 
		end
		T5: begin
				R4out <=0; ZLowout<= 1; R5in <= 1; LOin <= 1; 

		end
	endcase
end
endmodule
module datapath_tb;
 	
	reg clk, clr;
	reg IncPC, CON_enable;
	reg [31:0] Mdatain;
	reg [4:0] opCode, 
	reg RAM_write, MDR_enable, MDRout, MAR_enable, IR_enable, MDR_read;
	reg Gra, Grb, Grc;
	reg HI_enable, LO_enable, ZHighIn, ZLowIn, Y_enable, PC_enable, OutPort_enable;
	reg InPortout, PCout, Yout, ZLowout, ZHighout, LOout, HIout, BAout, Cout;
	wire [31:0] OutPort_output;
	reg [31:0] InPort_input;
	reg R_in, R_out, Cin, branch_flag;

parameter	Default = 4'b0000, Reg_load1a= 4'b0001, Reg_load1b= 4'b0010,
					Reg_load2a = 4'b0011, Reg_load2b = 4'b0100, Reg_load3a = 4'b0101,
					Reg_load3b = 4'b0110, T0= 4'b0111, T1= 4'b1000,T2= 4'b1001, T3= 4'b1010, T4= 4'b1011, T5= 4'b1100;
reg	[3:0] Present_state = Default;

datapath DUT(	
	OutPort_output, clk, clr, IncPC, CONin, Mdatain,
	opCode, RAM_write, MDR_enable, MDR_enable, MAR_enable,  IR_enable, MDR_read,
	Gra, Grb, Grc, HI_enable, LO_enable, ZHighIn, ZLowIn, Y_enable, PC_enable, OutPort_enable,
    InPortout, PCout, Yout, ZLowout, ZHighout, LOout, HIout, BAout, Cout, InPort_input,
	R_in, R_out, Cin, branch_flag          	
);

initial 
	begin
		Clear = 0;
		Clock = 0;
		forever #10 Clock = ~ Clock;
end

always @(posedge Clock)
begin
	case (Present_state)
		Default			:	#40 Present_state = Reg_load1a;
		Reg_load1a		:	#40 Present_state = Reg_load1b;
		Reg_load1b		:	#40 Present_state = Reg_load2a;
		Reg_load2a		:	#40 Present_state = Reg_load2b;
		Reg_load2b		:	#40 Present_state = Reg_load3a;
		Reg_load3a		:	#40 Present_state = Reg_load3b;
		Reg_load3b		:	#40 Present_state = T0;
		T0					:	#40 Present_state = T1;
		T1					:	#40 Present_state = T2;
		T2					:	#40 Present_state = T3;
		T3					:	#40 Present_state = T4;
		T4					:	#40 Present_state = T5;
		endcase
	end

always @(Present_state)
begin
	case (Present_state)
		Default: begin
						PCout <= 0;   ZLowout <= 0; ZHighout <= 0;  MDRout<= 0;
						R2out <= 0;   R4out <= 0;   MARin <= 0;   ZLowIn <= 0;  
						PCin <=0;   MDRin <= 0;   IRin  <= 0;   Yin <= 0;  
						IncPC <= 0;   Read <= 0;   opCode <= 5'b00000;  branch_flag <=0;
						HIout<=0;  LOout<=0; InPortout<=0; Cout<=0;
						R5in <= 0; R2in <= 0; R4in <= 0; Mdatain <= 32'h00000000;
		end
		Reg_load1a: begin 
				Mdatain<= 32'h00000022;
				Read = 0; MDRin = 0;
				#10 Read <= 1; MDRin <= 1;  
				#15 Read <= 0; MDRin <= 0;
		end
		Reg_load1b: begin
				#10 MDRout<= 1; R2in <= 1;  
				#15 MDRout<= 0; R2in <= 0;
		end
		Reg_load2a: begin 
				Mdatain <= 32'h00000011;
				#10 Read <= 1; MDRin <= 1;  
				#15 Read <= 0; MDRin <= 0;
		end
		Reg_load2b: begin
				#10 MDRout<= 1; R4in <= 1;  
				#15 MDRout<= 0; R4in <= 0;
		end
		Reg_load3a: begin 
				Mdatain <= 32'h00000026;
				#10 Read <= 1; MDRin <= 1;  
				#15 Read <= 0; MDRin <= 0;
		end
		Reg_load3b: begin
				#10 MDRout<= 1; R5in <= 1;  
				#15 MDRout<= 0; R5in <= 0;
		end
	
		T0: begin
				PCout<= 1; MARin <= 1; IncPC <= 1; ZLowIn <= 1;
		end
		T1: begin
				Mdatain <= 32'h4A920000; Read <= 1; MDRin <= 1; ZLowout<= 1; PCin <= 1; PCout <=0;
				
				
		end
		T2: begin								
				MDRout<= 1; IRin <= 1; ZLowout<= 0;
		end
		T3: begin
				MDRout<=0; R2out<= 1; Yin <= 1;
		end
		T4: begin
				Yin <= 0; R2out <=0; R4out<= 1; opCode <= 5'b00100; ZLowIn <= 1; 
		end
		T5: begin
				R4out <=0; ZLowout<= 1; R5in <= 1; LOin <= 1; 

		end
	endcase
end
endmodule