data/full_repos/permissive/485026242/Lock-system/testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/485026242/Lock-system/testbench.v:15: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/485026242/Lock-system/testbench.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #99;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/485026242/Lock-system/testbench.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/485026242/Lock-system/testbench.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #99;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/485026242/Lock-system/testbench.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/485026242/Lock-system/testbench.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #99;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/485026242/Lock-system/testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/485026242/Lock-system/testbench.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #99;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/485026242/Lock-system/testbench.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/485026242/Lock-system/testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #99;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/485026242/Lock-system/testbench.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/485026242/Lock-system/testbench.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/485026242/Lock-system/testbench.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #99;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/485026242/Lock-system/testbench.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/485026242/Lock-system/testbench.v:50: Unsupported: Ignoring delay on this delayed statement.\n        #99;\n        ^\n%Error: data/full_repos/permissive/485026242/Lock-system/testbench.v:8: Cannot find file containing module: \'Lock\'\n    Lock p1(reset,Enter,PassIn,user,Access,Setpass,Count,Alarm);\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/485026242/Lock-system,data/full_repos/permissive/485026242/Lock\n             data/full_repos/permissive/485026242/Lock-system,data/full_repos/permissive/485026242/Lock.v\n             data/full_repos/permissive/485026242/Lock-system,data/full_repos/permissive/485026242/Lock.sv\n             Lock\n             Lock.v\n             Lock.sv\n             obj_dir/Lock\n             obj_dir/Lock.v\n             obj_dir/Lock.sv\n%Error: Exiting due to 1 error(s), 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module project_tb();
    reg [11:0] PassIn;
    reg reset,Enter;
    reg [1:0]user;
    wire [11:0] Setpass;
    wire Access,Alarm;
    wire [1:0] Count;
    Lock p1(reset,Enter,PassIn,user,Access,Setpass,Count,Alarm);
    initial
    begin
        user=2'b11;
        PassIn=12'h111;
        Enter=1;
        reset=0;
        #1;
        Enter=0;
        #99;
        PassIn=12'h0AA;
        Enter=1;
        #1;
        Enter=0;
        #99;
        PassIn=12'hF1A;
        Enter=1;
        #1;
        Enter=0;
        #99;
        PassIn=12'h999;
        Enter=1;
        #1;
        Enter=0;
        #99;
        PassIn=12'h001;
        Enter=1;
        #1;
        Enter=0;
        #99;
        PassIn=12'h188;
        reset=1;
        Enter=1;
        #10;
        reset=0;
        #1;
        Enter=0;
        #99;
        PassIn=12'h111;
        Enter=1;
        #1;
        Enter=0;
        #99;
        $finish;
    end
endmodule
module project_tb();

    reg [11:0] PassIn;
    reg reset,Enter;
    reg [1:0]user;
    wire [11:0] Setpass;
    wire Access,Alarm;
    wire [1:0] Count;
    Lock p1(reset,Enter,PassIn,user,Access,Setpass,Count,Alarm);
    initial
    begin
        user=2'b11;
        PassIn=12'h111;
        Enter=1;
        reset=0;
        #1;
        Enter=0;
        #99;
        PassIn=12'h0AA;
        Enter=1;
        #1;
        Enter=0;
        #99;
        PassIn=12'hF1A;
        Enter=1;
        #1;
        Enter=0;
        #99;
        PassIn=12'h999;
        Enter=1;
        #1;
        Enter=0;
        #99;
        PassIn=12'h001;
        Enter=1;
        #1;
        Enter=0;
        #99;
        PassIn=12'h188;
        reset=1;
        Enter=1;
        #10;
        reset=0;
        #1;
        Enter=0;
        #99;
        PassIn=12'h111;
        Enter=1;
        #1;
        Enter=0;
        #99;
        $finish;
    end
endmodule