data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Vivado/Nexys4/USTCRVSoC-nexys4.srcs/sources_1/Nexys4_USTCRVSoC_top.sv
1: b'%Error: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Vivado/Nexys4/USTCRVSoC-nexys4.srcs/sources_1/Nexys4_USTCRVSoC_top.sv:14: Cannot find file containing module: \'soc_top\'\nsoc_top  #(\n^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Vivado/Nexys4/USTCRVSoC-nexys4.srcs/sources_1,data/full_repos/permissive/435890256/soc_top\n             data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Vivado/Nexys4/USTCRVSoC-nexys4.srcs/sources_1,data/full_repos/permissive/435890256/soc_top.v\n             data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Vivado/Nexys4/USTCRVSoC-nexys4.srcs/sources_1,data/full_repos/permissive/435890256/soc_top.sv\n             soc_top\n             soc_top.v\n             soc_top.sv\n             obj_dir/soc_top\n             obj_dir/soc_top.v\n             obj_dir/soc_top.sv\n%Warning-WIDTH: data/full_repos/permissive/435890256/riscv_ref2/USTC-RVSoC/hardware/Vivado/Nexys4/USTCRVSoC-nexys4.srcs/sources_1/Nexys4_USTCRVSoC_top.sv:34: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n                                                                                                                                                            : ... In instance Nexys4_USTCRVSoC_top\nreg [ 7:0] flow = 7\'h0;\n                  ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n'
module Nexys4_USTCRVSoC_top(
    input  logic CLK100MHZ,
    output logic [9:0] LED,
    output logic UART_TX,
    input  logic UART_RX,
    output logic VGA_HS, VGA_VS,
    output logic [3:0] VGA_R, VGA_G, VGA_B
);

logic vga_red, vga_green, vga_blue;
assign {VGA_R, VGA_G, VGA_B} = {{4{vga_red}}, {4{vga_green}}, {4{vga_blue}}};

soc_top  #(
    .UART_RX_CLK_DIV  ( 217       ),
    .UART_TX_CLK_DIV  ( 868       ),
    .VGA_CLK_DIV      ( 2         )
) soc_inst (
    .clk              ( CLK100MHZ ),
    .isp_uart_rx      ( UART_RX   ),
    .isp_uart_tx      ( UART_TX   ),
    .vga_hsync        ( VGA_HS    ),
    .vga_vsync        ( VGA_VS    ),
    .vga_red          ( vga_red   ),
    .vga_green        ( vga_green ),
    .vga_blue         ( vga_blue  )
);


assign LED[9:8] = ~{UART_RX, UART_TX};


reg [21:0] cnt = 22'h0;
reg [ 7:0] flow = 7'h0;
always @ (posedge CLK100MHZ) begin
        cnt <= cnt + 22'h1;
        if(cnt==22'h0)
            flow <= {flow[6:0], ~flow[7]};
    end
    
assign LED[7:0] = flow;

endmodule
module Nexys4_USTCRVSoC_top(
    input  logic CLK100MHZ,
    output logic [9:0] LED,
    output logic UART_TX,
    input  logic UART_RX,
    output logic VGA_HS, VGA_VS,
    output logic [3:0] VGA_R, VGA_G, VGA_B
);


logic vga_red, vga_green, vga_blue;
assign {VGA_R, VGA_G, VGA_B} = {{4{vga_red}}, {4{vga_green}}, {4{vga_blue}}};

soc_top  #(
    .UART_RX_CLK_DIV  ( 217       ),
    .UART_TX_CLK_DIV  ( 868       ),
    .VGA_CLK_DIV      ( 2         )
) soc_inst (
    .clk              ( CLK100MHZ ),
    .isp_uart_rx      ( UART_RX   ),
    .isp_uart_tx      ( UART_TX   ),
    .vga_hsync        ( VGA_HS    ),
    .vga_vsync        ( VGA_VS    ),
    .vga_red          ( vga_red   ),
    .vga_green        ( vga_green ),
    .vga_blue         ( vga_blue  )
);


assign LED[9:8] = ~{UART_RX, UART_TX};


reg [21:0] cnt = 22'h0;
reg [ 7:0] flow = 7'h0;
always @ (posedge CLK100MHZ) begin
        cnt <= cnt + 22'h1;
        if(cnt==22'h0)
            flow <= {flow[6:0], ~flow[7]};
    end
    
assign LED[7:0] = flow;

endmodule