data/full_repos/permissive/455657973/alu_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/455657973/alu_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n        #300 op_code <= 5\'b10001;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/455657973/alu_tb.v:15: Cannot find file containing module: \'alu\'\n    alu alu_unit(brn_flag, alu_in_a, alu_in_b, op_code, alu_out);\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/455657973,data/full_repos/permissive/455657973/alu\n             data/full_repos/permissive/455657973,data/full_repos/permissive/455657973/alu.v\n             data/full_repos/permissive/455657973,data/full_repos/permissive/455657973/alu.sv\n             alu\n             alu.v\n             alu.sv\n             obj_dir/alu\n             obj_dir/alu.v\n             obj_dir/alu.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu_tb;
    reg [31:0] alu_in_a, alu_in_b, brn_flag;
     reg [4:0] op_code;
    wire [63:0] alu_out;
	 
initial
    begin
		  brn_flag <= 0;
        alu_in_a <= 32'd10;
        alu_in_b <= 32'd2;
        #300 op_code <= 5'b10001;

    end
    alu alu_unit(brn_flag, alu_in_a, alu_in_b, op_code, alu_out);
endmodule
module alu_tb;

    reg [31:0] alu_in_a, alu_in_b, brn_flag;
     reg [4:0] op_code;
    wire [63:0] alu_out;
	 
initial
    begin
		  brn_flag <= 0;
        alu_in_a <= 32'd10;
        alu_in_b <= 32'd2;
        #300 op_code <= 5'b10001;

    end
    alu alu_unit(brn_flag, alu_in_a, alu_in_b, op_code, alu_out);
endmodule