data/full_repos/permissive/505761772/code/ModemCore.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/505761772/code/ModemCore.v:204: Multiple top level modules\n                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                            : ... Top module \'DEMODULATOR\'\nmodule DEMODULATOR  ( input             CLK,\n       ^~~~~~~~~~~\n                                                                            : ... Top module \'NCO\'\nmodule NCO( input CLK,\n       ^~~\n                                                                            : ... Top module \'DESERIALIZER\'\nmodule DESERIALIZER(  input CLK,\n       ^~~~~~~~~~~~\n                                                                            : ... Top module \'SERIALIZER\'\nmodule SERIALIZER(  input       CLK,\n       ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/505761772/code/ModemCore.v:34: Operator ASSIGNW expects 18 bits on the Assign RHS, but Assign RHS\'s SHIFTRS generates 36 bits.\n                                                                        : ... In instance DEMODULATOR.MULT8\nassign P = (P36>>>17);\n         ^\n%Error: data/full_repos/permissive/505761772/code/ModemCore.v:35: Cannot find file containing module: \'MULT18X18\'\nMULT18X18 mult ( .P(P36),\n^~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/505761772/code,data/full_repos/permissive/505761772/MULT18X18\n             data/full_repos/permissive/505761772/code,data/full_repos/permissive/505761772/MULT18X18.v\n             data/full_repos/permissive/505761772/code,data/full_repos/permissive/505761772/MULT18X18.sv\n             MULT18X18\n             MULT18X18.v\n             MULT18X18.sv\n             obj_dir/MULT18X18\n             obj_dir/MULT18X18.v\n             obj_dir/MULT18X18.sv\n%Warning-WIDTH: data/full_repos/permissive/505761772/code/ModemCore.v:10: Operator ASSIGN expects 18 bits on the Assign RHS, but Assign RHS\'s CONST \'17\'h1d000\' generates 17 bits.\n                                                                        : ... In instance DEMODULATOR.Osc2\nreg signed [17:0] X = 17\'h1D000;\n                      ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/505761772/code/ModemCore.v:11: Operator ASSIGN expects 18 bits on the Assign RHS, but Assign RHS\'s CONST \'17\'h0\' generates 17 bits.\n                                                                        : ... In instance DEMODULATOR.Osc2\nreg signed [17:0] Y = 17\'h00000;\n                      ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/505761772/code/ModemCore.v:192: Operator EQ expects 5 bits on the RHS, but RHS\'s CONST \'4\'h1\' generates 4 bits.\n                                                                         : ... In instance DEMODULATOR\n    if(cnt == 4\'h1)\n           ^~\n%Warning-WIDTH: data/full_repos/permissive/505761772/code/ModemCore.v:240: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s CONST \'17\'he800\' generates 17 bits.\n                                                                         : ... In instance NCO\n      X <= 17\'h0E800;\n        ^~\n%Warning-WIDTH: data/full_repos/permissive/505761772/code/ModemCore.v:241: Operator ASSIGNDLY expects 18 bits on the Assign RHS, but Assign RHS\'s CONST \'17\'h0\' generates 17 bits.\n                                                                         : ... In instance NCO\n      Y <= 17\'h00000;\n        ^~\n%Error: Exiting due to 1 error(s), 7 warning(s)\n'
module DESERIALIZER(  input CLK,
                      input DATA,
                      input DET,
                      output reg CLK_out,
                      output reg VALID,
                      output reg [7:0] DATA_out);

reg [7:0] cnt;
reg DATA_old;
reg [2:0] bitCnt;
reg [2:0] stuffedBit;

initial begin
  DATA_out = 8'hFF;
  cnt = 0;
  bitCnt = 0;
  stuffedBit = 0;
  VALID = 0;
end

always @(posedge CLK) begin


  if(DET) begin


    if(DATA != DATA_old) begin
      cnt <= 8'd0;
      stuffedBit <= 0;


        if(stuffedBit < 5) begin
          DATA_out <= {1'b0, DATA_out[7:1]};
          bitCnt <= bitCnt + 1;
          if(bitCnt == 3'h0)
            VALID <= 1;



        end else if(stuffedBit > 5) begin
          VALID <= 0;
          DATA_out <= {1'b0, DATA_out[7:1]};
          bitCnt <= 3'h7;
        end


    end else begin

      if(cnt < 8'd153) begin
        cnt <= cnt + 1;

      end else begin
        cnt <= 8'd51;
        DATA_out <= {1'b1, DATA_out[7:1]};
        bitCnt <= bitCnt + 1;
        if(bitCnt == 3'h0)
          VALID <= 1;
        stuffedBit <= stuffedBit + 1;
      end
    end


    CLK_out <= (bitCnt == 3'h7) && (cnt < 16);



  end else begin
    bitCnt <= 0;
    cnt <= 0;
    stuffedBit <= 0;
  end

  DATA_old <= DATA;
end

endmodule
module DESERIALIZER(  input CLK,
                      input DATA,
                      input DET,
                      output reg CLK_out,
                      output reg VALID,
                      output reg [7:0] DATA_out);


reg [7:0] cnt;
reg DATA_old;
reg [2:0] bitCnt;
reg [2:0] stuffedBit;

initial begin
  DATA_out = 8'hFF;
  cnt = 0;
  bitCnt = 0;
  stuffedBit = 0;
  VALID = 0;
end

always @(posedge CLK) begin


  if(DET) begin


    if(DATA != DATA_old) begin
      cnt <= 8'd0;
      stuffedBit <= 0;


        if(stuffedBit < 5) begin
          DATA_out <= {1'b0, DATA_out[7:1]};
          bitCnt <= bitCnt + 1;
          if(bitCnt == 3'h0)
            VALID <= 1;



        end else if(stuffedBit > 5) begin
          VALID <= 0;
          DATA_out <= {1'b0, DATA_out[7:1]};
          bitCnt <= 3'h7;
        end


    end else begin

      if(cnt < 8'd153) begin
        cnt <= cnt + 1;

      end else begin
        cnt <= 8'd51;
        DATA_out <= {1'b1, DATA_out[7:1]};
        bitCnt <= bitCnt + 1;
        if(bitCnt == 3'h0)
          VALID <= 1;
        stuffedBit <= stuffedBit + 1;
      end
    end


    CLK_out <= (bitCnt == 3'h7) && (cnt < 16);



  end else begin
    bitCnt <= 0;
    cnt <= 0;
    stuffedBit <= 0;
  end

  DATA_old <= DATA;
end

endmodule