data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv
1: b"%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv:9: syntax error, unexpected ::, expecting ')' or ','\n    parameter snitch_icache_pkg::config_t CFG = '0\n                               ^~\n                                                                                                                     : ... Perhaps 'snitch_icache_pkg' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv:12: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic rst_ni,\n    ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv:14: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic [CFG.FETCH_AW-1:0]     in_req_addr_i,\n    ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv:15: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic [CFG.PENDING_IW-1:0]   in_req_id_i,\n    ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv:16: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic                        in_req_bypass_i,\n    ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv:17: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic                        in_req_valid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv:18: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic                        in_req_ready_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv:20: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic [CFG.LINE_WIDTH-1:0]   in_rsp_data_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv:21: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic                        in_rsp_error_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv:22: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic [CFG.PENDING_IW-1:0]   in_rsp_id_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv:23: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic                        in_rsp_bypass_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv:24: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic                        in_rsp_valid_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv:25: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic                        in_rsp_ready_i,\n    ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv:27: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic [CFG.FILL_AW-1:0]      refill_qaddr_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv:28: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic [7:0]                  refill_qlen_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv:29: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic                        refill_qvalid_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv:30: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic                        refill_qready_i,\n    ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv:32: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic [CFG.FILL_DW-1:0]      refill_pdata_i,\n    ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv:33: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic                        refill_perror_i,\n    ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv:34: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic                        refill_plast_i,\n    ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv:35: syntax error, unexpected input, expecting IDENTIFIER or '=' or do or final\n    input  logic                        refill_pvalid_i,\n    ^~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv:36: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n    output logic                        refill_pready_o\n    ^~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv:51: syntax error, unexpected IDENTIFIER\n    fifo_v3  #(\n    ^~~~~~~\n%Error: data/full_repos/permissive/489147019/Testcases/mempool/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv:79: syntax error, unexpected if\n    if (CFG.LINE_WIDTH > CFG.FILL_DW) begin : g_data_concat\n    ^~\n%Error: Exiting due to 24 error(s)\n"
module snitch_icache_refill #(
    parameter snitch_icache_pkg::config_t CFG = '0
) (
    input  logic clk_i,
    input  logic rst_ni,

    input  logic [CFG.FETCH_AW-1:0]     in_req_addr_i,
    input  logic [CFG.PENDING_IW-1:0]   in_req_id_i,
    input  logic                        in_req_bypass_i,
    input  logic                        in_req_valid_i,
    output logic                        in_req_ready_o,

    output logic [CFG.LINE_WIDTH-1:0]   in_rsp_data_o,
    output logic                        in_rsp_error_o,
    output logic [CFG.PENDING_IW-1:0]   in_rsp_id_o,
    output logic                        in_rsp_bypass_o,
    output logic                        in_rsp_valid_o,
    input  logic                        in_rsp_ready_i,

    output logic [CFG.FILL_AW-1:0]      refill_qaddr_o,
    output logic [7:0]                  refill_qlen_o,
    output logic                        refill_qvalid_o,
    input  logic                        refill_qready_i,

    input  logic [CFG.FILL_DW-1:0]      refill_pdata_i,
    input  logic                        refill_perror_i,
    input  logic                        refill_plast_i,
    input  logic                        refill_pvalid_i,
    output logic                        refill_pready_o
);

    `ifndef SYNTHESIS
    initial assert(CFG != '0);
    `endif


    localparam BEATS_PER_REFILL = CFG.LINE_WIDTH >= CFG.FILL_DW ? CFG.LINE_WIDTH/CFG.FILL_DW : 1;


    logic queue_full;
    logic queue_push;
    logic queue_pop;

    fifo_v3  #(
        .DEPTH      ( 4                ),
        .DATA_WIDTH ( CFG.PENDING_IW+1 )
    ) i_fifo_id_queue (
        .clk_i       ( clk_i                          ),
        .rst_ni      ( rst_ni                         ),
        .flush_i     ( 1'b0                           ),
        .testmode_i  ( 1'b0                           ),
        .full_o      ( queue_full                     ),
        .empty_o     (                                ),
        .usage_o     (                                ),
        .data_i      ( {in_req_bypass_i, in_req_id_i} ),
        .push_i      ( queue_push                     ),
        .data_o      ( {in_rsp_bypass_o, in_rsp_id_o} ),
        .pop_i       ( queue_pop                      )
    );



    assign refill_qaddr_o  = in_req_addr_i;
    assign refill_qlen_o   = $unsigned(BEATS_PER_REFILL-1);
    assign refill_qvalid_o = in_req_valid_i & ~queue_full;
    assign in_req_ready_o  = refill_qready_i & ~queue_full;
    assign queue_push      = refill_qvalid_o & refill_qready_i;


    logic [CFG.LINE_WIDTH-1:0] response_data;

    if (CFG.LINE_WIDTH > CFG.FILL_DW) begin : g_data_concat
        always_ff @(posedge clk_i, negedge rst_ni) begin
            if (!rst_ni)
                response_data[CFG.LINE_WIDTH-CFG.FILL_DW-1:0] <= '0;
            else if (refill_pvalid_i && refill_pready_o)
                response_data[CFG.LINE_WIDTH-CFG.FILL_DW-1:0] <= response_data[CFG.LINE_WIDTH-1:CFG.FILL_DW];
        end
        assign response_data[CFG.LINE_WIDTH-1:CFG.LINE_WIDTH-CFG.FILL_DW] = refill_pdata_i;
    end else if (CFG.LINE_WIDTH < CFG.FILL_DW) begin : g_data_slice
        assign response_data = refill_pdata_i >> (in_req_addr_i[CFG.FILL_ALIGN-1:CFG.LINE_ALIGN] * CFG.LINE_WIDTH);
    end else begin : g_data_passthrough
        assign response_data = refill_pdata_i;
    end



    always_comb begin : p_response
        in_rsp_data_o  = response_data;
        in_rsp_error_o = refill_perror_i;
        in_rsp_valid_o = 0;
        queue_pop      = 0;
        refill_pready_o  = 0;

        if (refill_pvalid_i) begin
            if (!refill_plast_i) begin
                refill_pready_o  = 1;
            end else begin
                in_rsp_valid_o = 1;
                if (in_rsp_ready_i) begin
                    refill_pready_o  = 1;
                    queue_pop      = 1;
                end
            end
        end
    end

endmodule
module snitch_icache_refill #(
    parameter snitch_icache_pkg::config_t CFG = '0
) (
    input  logic clk_i,
    input  logic rst_ni,

    input  logic [CFG.FETCH_AW-1:0]     in_req_addr_i,
    input  logic [CFG.PENDING_IW-1:0]   in_req_id_i,
    input  logic                        in_req_bypass_i,
    input  logic                        in_req_valid_i,
    output logic                        in_req_ready_o,

    output logic [CFG.LINE_WIDTH-1:0]   in_rsp_data_o,
    output logic                        in_rsp_error_o,
    output logic [CFG.PENDING_IW-1:0]   in_rsp_id_o,
    output logic                        in_rsp_bypass_o,
    output logic                        in_rsp_valid_o,
    input  logic                        in_rsp_ready_i,

    output logic [CFG.FILL_AW-1:0]      refill_qaddr_o,
    output logic [7:0]                  refill_qlen_o,
    output logic                        refill_qvalid_o,
    input  logic                        refill_qready_i,

    input  logic [CFG.FILL_DW-1:0]      refill_pdata_i,
    input  logic                        refill_perror_i,
    input  logic                        refill_plast_i,
    input  logic                        refill_pvalid_i,
    output logic                        refill_pready_o
);


    `ifndef SYNTHESIS
    initial assert(CFG != '0);
    `endif


    localparam BEATS_PER_REFILL = CFG.LINE_WIDTH >= CFG.FILL_DW ? CFG.LINE_WIDTH/CFG.FILL_DW : 1;


    logic queue_full;
    logic queue_push;
    logic queue_pop;

    fifo_v3  #(
        .DEPTH      ( 4                ),
        .DATA_WIDTH ( CFG.PENDING_IW+1 )
    ) i_fifo_id_queue (
        .clk_i       ( clk_i                          ),
        .rst_ni      ( rst_ni                         ),
        .flush_i     ( 1'b0                           ),
        .testmode_i  ( 1'b0                           ),
        .full_o      ( queue_full                     ),
        .empty_o     (                                ),
        .usage_o     (                                ),
        .data_i      ( {in_req_bypass_i, in_req_id_i} ),
        .push_i      ( queue_push                     ),
        .data_o      ( {in_rsp_bypass_o, in_rsp_id_o} ),
        .pop_i       ( queue_pop                      )
    );



    assign refill_qaddr_o  = in_req_addr_i;
    assign refill_qlen_o   = $unsigned(BEATS_PER_REFILL-1);
    assign refill_qvalid_o = in_req_valid_i & ~queue_full;
    assign in_req_ready_o  = refill_qready_i & ~queue_full;
    assign queue_push      = refill_qvalid_o & refill_qready_i;


    logic [CFG.LINE_WIDTH-1:0] response_data;

    if (CFG.LINE_WIDTH > CFG.FILL_DW) begin : g_data_concat
        always_ff @(posedge clk_i, negedge rst_ni) begin
            if (!rst_ni)
                response_data[CFG.LINE_WIDTH-CFG.FILL_DW-1:0] <= '0;
            else if (refill_pvalid_i && refill_pready_o)
                response_data[CFG.LINE_WIDTH-CFG.FILL_DW-1:0] <= response_data[CFG.LINE_WIDTH-1:CFG.FILL_DW];
        end
        assign response_data[CFG.LINE_WIDTH-1:CFG.LINE_WIDTH-CFG.FILL_DW] = refill_pdata_i;
    end else if (CFG.LINE_WIDTH < CFG.FILL_DW) begin : g_data_slice
        assign response_data = refill_pdata_i >> (in_req_addr_i[CFG.FILL_ALIGN-1:CFG.LINE_ALIGN] * CFG.LINE_WIDTH);
    end else begin : g_data_passthrough
        assign response_data = refill_pdata_i;
    end



    always_comb begin : p_response
        in_rsp_data_o  = response_data;
        in_rsp_error_o = refill_perror_i;
        in_rsp_valid_o = 0;
        queue_pop      = 0;
        refill_pready_o  = 0;

        if (refill_pvalid_i) begin
            if (!refill_plast_i) begin
                refill_pready_o  = 1;
            end else begin
                in_rsp_valid_o = 1;
                if (in_rsp_ready_i) begin
                    refill_pready_o  = 1;
                    queue_pop      = 1;
                end
            end
        end
    end

endmodule