data/full_repos/permissive/489462235/final_projSrc.v
1: b'%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:170: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                        : ... In instance datapath.control_unit\n        fwda = 2\'b00;\n             ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:171: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h0\' generates 2 bits.\n                                                                        : ... In instance datapath.control_unit\n        fwdb = 2\'b00;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:174: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h1\' generates 2 bits.\n                                                                        : ... In instance datapath.control_unit\n            fwda = 2\'b01;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:173: Operator EQ expects 5 bits on the LHS, but LHS\'s VARREF \'edestReg\' generates 1 bits.\n                                                                        : ... In instance datapath.control_unit\n        if (edestReg == rs) begin\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:178: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h1\' generates 2 bits.\n                                                                        : ... In instance datapath.control_unit\n            fwdb = 2\'b01;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:177: Operator EQ expects 5 bits on the LHS, but LHS\'s VARREF \'edestReg\' generates 1 bits.\n                                                                        : ... In instance datapath.control_unit\n        if (edestReg == rt) begin\n                     ^~\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:183: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h3\' generates 2 bits.\n                                                                        : ... In instance datapath.control_unit\n                fwda = 2\'b11;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:186: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                        : ... In instance datapath.control_unit\n                fwda = 2\'b10;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:192: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h3\' generates 2 bits.\n                                                                        : ... In instance datapath.control_unit\n                fwdb = 2\'b11;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:195: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                        : ... In instance datapath.control_unit\n                fwdb = 2\'b10;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:69: Input port connection \'edestReg\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'edestReg\' generates 5 bits.\n                                                                       : ... In instance datapath\n    control_unit control_unit (dinstOut[31:26], dinstOut[5:0], dinstOut[25:21], rt, mdestReg, mm2reg, mwreg, edestReg, em2reg, ewreg, regrt, wreg, m2reg, wmem, aluimm, aluc, fwda, fwdb);\n                                                                                                             ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:69: Output port connection \'fwda\' expects 32 bits on the pin connection, but pin connection\'s VARREF \'fwda\' generates 2 bits.\n                                                                       : ... In instance datapath\n    control_unit control_unit (dinstOut[31:26], dinstOut[5:0], dinstOut[25:21], rt, mdestReg, mm2reg, mwreg, edestReg, em2reg, ewreg, regrt, wreg, m2reg, wmem, aluimm, aluc, fwda, fwdb);\n                                                                                                                                                                              ^~~~\n%Warning-WIDTH: data/full_repos/permissive/489462235/final_projSrc.v:69: Output port connection \'fwdb\' expects 32 bits on the pin connection, but pin connection\'s VARREF \'fwdb\' generates 2 bits.\n                                                                       : ... In instance datapath\n    control_unit control_unit (dinstOut[31:26], dinstOut[5:0], dinstOut[25:21], rt, mdestReg, mm2reg, mwreg, edestReg, em2reg, ewreg, regrt, wreg, m2reg, wmem, aluimm, aluc, fwda, fwdb);\n                                                                                                                                                                                    ^~~~\n%Error: Exiting due to 13 warning(s)\n'
module datapath (clk, pc, nextPc, dinstOut, ewreg, em2reg, ewmem, ealuc, ealuimm, edestReg, eqa, eqb, eimm32, mwreg, mm2reg, mwmem, mdestReg, mr, mqb, wwreg, wm2reg, wdestReg, wr, wdo);
    
    input clk;
    

    output [31:0] pc;
    output [31:0] nextPc;
    

    output [31:0] dinstOut;
    

    output ewreg;
    output em2reg;
    output ewmem;
    output [3:0] ealuc;
    output ealuimm;
    output [4:0] edestReg;
    output [31:0] eqa;
    output [31:0] eqb;
    output [31:0] eimm32;
    

    output mwreg;
    output mm2reg;
    output mwmem;
    output [4:0] mdestReg;
    output [31:0] mr;
    output [31:0] mqb;
    

    output wwreg;
    output wm2reg;
    output [4:0] wdestReg;
    output [31:0] wr;
    output [31:0] wdo;
    
    wire [31:0] instOut;
    wire regrt;
    wire wreg;
    wire m2reg;
    wire wmem;
    wire [3:0] aluc;
    wire aluimm;
    wire [4:0] rd;
    wire [4:0] rt;
    wire [4:0] destReg;
    wire [31:0] qa;
    wire [31:0] qb;
    wire [31:0] imm32;
    wire [31:0] mdo;
    wire [31:0] b;
    wire [31:0] r;
    wire [1:0] fwda;
    wire [1:0] fwdb;
    wire [31:0] fqa;
    wire [31:0] fqb;
    wire [31:0] wbData;
       
    program_Counter program_Counter (clk, nextPc, pc);
    
    pcAdder pcAdder (pc, nextPc);
            
    Instruction_memory Instruction_memory (pc, instOut);
            
    ifid_pipeline_register ifid_pipeline_register (clk, instOut, dinstOut);
    
    control_unit control_unit (dinstOut[31:26], dinstOut[5:0], dinstOut[25:21], rt, mdestReg, mm2reg, mwreg, edestReg, em2reg, ewreg, regrt, wreg, m2reg, wmem, aluimm, aluc, fwda, fwdb);
        
    regrt_multiplexer regrt_multiplexer (dinstOut[15:11], dinstOut[20:16], regrt, destReg);
            
    register_file register_file (clk, dinstOut[25:21], dinstOut[20:16], wwreg, wbData, wdestReg, qa, qb); 
    
    immediate_extender immediate_extender (dinstOut[15:0], imm32);
            
    idexe_pipeline_register idexe_pipeline_register (clk, wreg, m2reg, wmem, aluc, aluimm, destReg, fqa, fqb, imm32, ewreg, em2reg, ewmem, ealuc, ealuimm, edestReg, eqa, eqb, eimm32);
    
    AluMux AluMux (eqb, eimm32, ealuimm, b);
    
    Alu Alu (eqa, b, ealuc, r);
    
    exemem_pipeline_register exemem_pipeline_register (clk, ewreg, em2reg, ewmem, edestReg, r, eqb, mwreg, mm2reg, mwmem, mdestReg, mr, mqb);

    data_memory data_memory (clk ,mr, mqb, mwmem, mdo);
    
    memwb_pipeline_register memwb_pipeline_register (clk, mwreg, mm2reg, mdestReg, mr, mdo, wwreg, wm2reg, wdestReg, wr, wdo);
    
    WbMux WbMux (wr, wdo, wm2reg, wbData);
    
    mux4 mux4 (qa, r, mr, mdo, fwda, fqa);
    
    mux5 mux5 (qb, r, mr, mdo, fwdb, fqb);
endmodule
module datapath (clk, pc, nextPc, dinstOut, ewreg, em2reg, ewmem, ealuc, ealuimm, edestReg, eqa, eqb, eimm32, mwreg, mm2reg, mwmem, mdestReg, mr, mqb, wwreg, wm2reg, wdestReg, wr, wdo);

    
    input clk;
    

    output [31:0] pc;
    output [31:0] nextPc;
    

    output [31:0] dinstOut;
    

    output ewreg;
    output em2reg;
    output ewmem;
    output [3:0] ealuc;
    output ealuimm;
    output [4:0] edestReg;
    output [31:0] eqa;
    output [31:0] eqb;
    output [31:0] eimm32;
    

    output mwreg;
    output mm2reg;
    output mwmem;
    output [4:0] mdestReg;
    output [31:0] mr;
    output [31:0] mqb;
    

    output wwreg;
    output wm2reg;
    output [4:0] wdestReg;
    output [31:0] wr;
    output [31:0] wdo;
    
    wire [31:0] instOut;
    wire regrt;
    wire wreg;
    wire m2reg;
    wire wmem;
    wire [3:0] aluc;
    wire aluimm;
    wire [4:0] rd;
    wire [4:0] rt;
    wire [4:0] destReg;
    wire [31:0] qa;
    wire [31:0] qb;
    wire [31:0] imm32;
    wire [31:0] mdo;
    wire [31:0] b;
    wire [31:0] r;
    wire [1:0] fwda;
    wire [1:0] fwdb;
    wire [31:0] fqa;
    wire [31:0] fqb;
    wire [31:0] wbData;
       
    program_Counter program_Counter (clk, nextPc, pc);
    
    pcAdder pcAdder (pc, nextPc);
            
    Instruction_memory Instruction_memory (pc, instOut);
            
    ifid_pipeline_register ifid_pipeline_register (clk, instOut, dinstOut);
    
    control_unit control_unit (dinstOut[31:26], dinstOut[5:0], dinstOut[25:21], rt, mdestReg, mm2reg, mwreg, edestReg, em2reg, ewreg, regrt, wreg, m2reg, wmem, aluimm, aluc, fwda, fwdb);
        
    regrt_multiplexer regrt_multiplexer (dinstOut[15:11], dinstOut[20:16], regrt, destReg);
            
    register_file register_file (clk, dinstOut[25:21], dinstOut[20:16], wwreg, wbData, wdestReg, qa, qb); 
    
    immediate_extender immediate_extender (dinstOut[15:0], imm32);
            
    idexe_pipeline_register idexe_pipeline_register (clk, wreg, m2reg, wmem, aluc, aluimm, destReg, fqa, fqb, imm32, ewreg, em2reg, ewmem, ealuc, ealuimm, edestReg, eqa, eqb, eimm32);
    
    AluMux AluMux (eqb, eimm32, ealuimm, b);
    
    Alu Alu (eqa, b, ealuc, r);
    
    exemem_pipeline_register exemem_pipeline_register (clk, ewreg, em2reg, ewmem, edestReg, r, eqb, mwreg, mm2reg, mwmem, mdestReg, mr, mqb);

    data_memory data_memory (clk ,mr, mqb, mwmem, mdo);
    
    memwb_pipeline_register memwb_pipeline_register (clk, mwreg, mm2reg, mdestReg, mr, mdo, wwreg, wm2reg, wdestReg, wr, wdo);
    
    WbMux WbMux (wr, wdo, wm2reg, wbData);
    
    mux4 mux4 (qa, r, mr, mdo, fwda, fqa);
    
    mux5 mux5 (qb, r, mr, mdo, fwdb, fqb);
endmodule