data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU.v
1: b'%Error: data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU.v:10: Cannot find file containing module: \'ControlUnit\'\nControlUnit cu(IR_CU,  RFLOAD,  PCLOAD,  SRLOAD,  SRENABLED,  ALUSTORE,  MFA,  WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD,opcode,CU,MFC,Reset,Clk,IR,SR);\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU,data/full_repos/permissive/51595169/ControlUnit\n             data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU,data/full_repos/permissive/51595169/ControlUnit.v\n             data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU,data/full_repos/permissive/51595169/ControlUnit.sv\n             ControlUnit\n             ControlUnit.v\n             ControlUnit.sv\n             obj_dir/ControlUnit\n             obj_dir/ControlUnit.v\n             obj_dir/ControlUnit.sv\n%Warning-WIDTH: data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU.v:14: Operator ASSIGN expects 20 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 15 bits.\n                                                                                                 : ... In instance ARM_CU_ALU\n RSLCT = {IR[15:8],IR[3:1], IR[19:16]};\n       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU.v:20: Cannot find file containing module: \'RegisterFile\'\nRegisterFile RF(Out,Out,RSLCT,Clk, Reset, PCLOAD, RFLOAD,IR_CU, Rn,Rm,Rs,PCout);\n^~~~~~~~~~~~\n%Error: data/full_repos/permissive/51595169/VerilogSource/ControlUnit+ALU/ARM_CU_ALU.v:25: Cannot find file containing module: \'ARM_ALU\'\nARM_ALU alu(Rn,Rm, opcode, SR, Out,FLAGS_OUT,S,ALUSTORE);\n^~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module ARM_CU_ALU;

wire IR_CU,  RFLOAD,  PCLOAD,  SRLOAD,  SRENABLED,  ALUSTORE,  MFA,  WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD;
wire [4:0] opcode; 
wire [3:0] CU; 
reg [31:0] IR;
reg [3:0] SR;
reg MFC , Reset , Clk ;

ControlUnit cu(IR_CU,  RFLOAD,  PCLOAD,  SRLOAD,  SRENABLED,  ALUSTORE,  MFA,  WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD,opcode,CU,MFC,Reset,Clk,IR,SR);

always@(IR)
begin
	RSLCT = {IR[15:8],IR[3:1], IR[19:16]};
end

reg [19:0] RSLCT;
wire [31:0] Rn,Rm,Rs,PCout,Out;

RegisterFile RF(Out,Out,RSLCT,Clk, Reset, PCLOAD, RFLOAD,IR_CU, Rn,Rm,Rs,PCout);

reg S;
wire [3:0] FLAGS_OUT;

ARM_ALU alu(Rn,Rm, opcode, SR, Out,FLAGS_OUT,S,ALUSTORE);
endmodule
module ARM_CU_ALU;


wire IR_CU,  RFLOAD,  PCLOAD,  SRLOAD,  SRENABLED,  ALUSTORE,  MFA,  WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD;
wire [4:0] opcode; 
wire [3:0] CU; 
reg [31:0] IR;
reg [3:0] SR;
reg MFC , Reset , Clk ;

ControlUnit cu(IR_CU,  RFLOAD,  PCLOAD,  SRLOAD,  SRENABLED,  ALUSTORE,  MFA,  WORD_BYTE, READ_WRITE, IRLOAD, MBRLOAD, MBRSTORE, MARLOAD,opcode,CU,MFC,Reset,Clk,IR,SR);

always@(IR)
begin
	RSLCT = {IR[15:8],IR[3:1], IR[19:16]};
end

reg [19:0] RSLCT;
wire [31:0] Rn,Rm,Rs,PCout,Out;

RegisterFile RF(Out,Out,RSLCT,Clk, Reset, PCLOAD, RFLOAD,IR_CU, Rn,Rm,Rs,PCout);

reg S;
wire [3:0] FLAGS_OUT;

ARM_ALU alu(Rn,Rm, opcode, SR, Out,FLAGS_OUT,S,ALUSTORE);
endmodule