data/full_repos/permissive/47737018/TB/source_fix4.sv
1: b'%Warning-MULTITOP: data/full_repos/permissive/47737018/TB/source_fix4.sv:27: Multiple top level modules\n                                                                           : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                           : ... Top module \'mux\'\nmodule mux #(parameter int wl=36)\n       ^~~\n                                                                           : ... Top module \'rdy_en\'\nmodule rdy_en (\n       ^~~~~~\n                                                                           : ... Top module \'crossbar\'\nmodule crossbar #(parameter int wL=36,parameter int lhsCount=5,parameter int rhsCount=5)\n       ^~~~~~~~\n                                                                           : ... Top module \'FIFO\'\nmodule FIFO #(parameter int wL=36,parameter int d=8)\n       ^~~~\n                                                                           : ... Top module \'matrix\'\nmodule matrix #(parameter int WIDTH=36)\n       ^~~~~~\n                                                                           : ... Top module \'findblock\'\nmodule findblock (\n       ^~~~~~~~~\n                                                                           : ... Top module \'priority_encoder\'\nmodule priority_encoder (\n       ^~~~~~~~~~~~~~~~\n                                                                           : ... Top module \'decoder\'\n module decoder(\n        ^~~~~~~\n                                                                           : ... Top module \'decoder_2\'\nmodule decoder_2(\n       ^~~~~~~~~\n                                                                           : ... Top module \'dffr\'\nmodule dffr #(parameter int size = 36 )\n       ^~~~\n                                                                           : ... Top module \'dffr1\'\nmodule dffr1 #(parameter int size = 1 )\n       ^~~~~\n                                                                           : ... Top module \'dffr2\'\nmodule dffr2 #(parameter int size = 5 )\n       ^~~~~\n                                                                           : ... Top module \'dffr3\'\nmodule dffr3 #(parameter int size = 3 )\n       ^~~~~\n%Warning-WIDTH: data/full_repos/permissive/47737018/TB/source_fix4.sv:370: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'temp_block0\' generates 5 bits.\n                                                                         : ... In instance findblock\nblocked[0]=(temp_block0)?0:1;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/47737018/TB/source_fix4.sv:371: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'temp_block1\' generates 5 bits.\n                                                                         : ... In instance findblock\nblocked[1]=(temp_block1)?0:1;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/47737018/TB/source_fix4.sv:372: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'temp_block2\' generates 5 bits.\n                                                                         : ... In instance findblock\nblocked[2]=(temp_block2)?0:1;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/47737018/TB/source_fix4.sv:373: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'temp_block3\' generates 5 bits.\n                                                                         : ... In instance findblock\nblocked[3]=(temp_block3)?0:1;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/47737018/TB/source_fix4.sv:374: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'temp_block4\' generates 5 bits.\n                                                                         : ... In instance findblock\nblocked[4]=(temp_block4)?0:1;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/47737018/TB/source_fix4.sv:285: Operator CASE expects 4 bits on the Case expression, but Case expression\'s VARREF \'counter_pre\' generates 3 bits.\n                                                                         : ... In instance FIFO\nunique case (counter_pre)\n       ^~~~\n%Error: Exiting due to 7 warning(s)\n'
module dffr1 #(parameter int size = 1 )
               (
                 input logic [size-1:0] din,
                 input logic clk,
                 input logic rst,
                 input logic [size-1:0] rst_val,
                 input logic en,
                 output logic [size-1:0] q
               );
 
 
                 logic [size-1:0] d ;
                 bit [size-1:0] q_val;
                 
                 assign d[size-1:0] = din[size-1:0];
                 assign q = q_val ;
 
                 always @ (posedge clk) begin
                      assert ( ~$isunknown(d) || ~rst ) else $error("Error:d is X or Z") ;
 
                      priority case ( 1'b1 )
                          (~rst): q_val[size-1:0] <= rst_val[size-1:0] ;
                          ( en): q_val[size-1:0] <= d[size-1:0] ;
                          (~en): q_val[size-1:0] <= q[size-1:0] ;
                    endcase
                end
 
endmodule
module dffr1 #(parameter int size = 1 )
               (
                 input logic [size-1:0] din,
                 input logic clk,
                 input logic rst,
                 input logic [size-1:0] rst_val,
                 input logic en,
                 output logic [size-1:0] q
               );

 
 
                 logic [size-1:0] d ;
                 bit [size-1:0] q_val;
                 
                 assign d[size-1:0] = din[size-1:0];
                 assign q = q_val ;
 
                 always @ (posedge clk) begin
                      assert ( ~$isunknown(d) || ~rst ) else $error("Error:d is X or Z") ;
 
                      priority case ( 1'b1 )
                          (~rst): q_val[size-1:0] <= rst_val[size-1:0] ;
                          ( en): q_val[size-1:0] <= d[size-1:0] ;
                          (~en): q_val[size-1:0] <= q[size-1:0] ;
                    endcase
                end
 
endmodule