data/full_repos/permissive/47956074/rtl/arty_mmcm_sim.v
data/verilator_xmls/e372611f-2050-4d1e-8faf-685e07e5a115.xml
module arty_mmcm (

   clk_50m, locked,

   clk_in, resetn
   );


   input clk_in;
   output clk_50m;
   input  resetn;
   output locked;






   reg                  clk_50m;
   reg                  locked;



   always @(posedge clk_in or negedge resetn) begin
      if(resetn == 1'b0) begin


         clk_50m <= 1'h0;

      end
      else begin
         clk_50m <= !clk_50m;
      end
   end

   always @(posedge clk_50m or negedge resetn) begin
      if(resetn == 1'b0) begin


         locked = 1'h0;

      end
      else begin
         locked <= 1'b1;

      end
   end



endmodule
module arty_mmcm (

   clk_50m, locked,

   clk_in, resetn
   );



   input clk_in;
   output clk_50m;
   input  resetn;
   output locked;






   reg                  clk_50m;
   reg                  locked;



   always @(posedge clk_in or negedge resetn) begin
      if(resetn == 1'b0) begin


         clk_50m <= 1'h0;

      end
      else begin
         clk_50m <= !clk_50m;
      end
   end

   always @(posedge clk_50m or negedge resetn) begin
      if(resetn == 1'b0) begin


         locked = 1'h0;

      end
      else begin
         locked <= 1'b1;

      end
   end



endmodule