data/full_repos/permissive/423667690/src/sobel_convolution.v
1: b'%Warning-WIDTH: data/full_repos/permissive/423667690/src/sobel_convolution.v:51: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 8 bits.\n                                                                               : ... In instance sobel_convolution\n    temp1_q<={3\'b000,gray[7:3]};\n           ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/423667690/src/sobel_convolution.v:69: Operator SHIFTR expects 13 bits on the LHS, but LHS\'s VARREF \'red\' generates 8 bits.\n                                                                               : ... In instance sobel_convolution\n  assign gray=(red>>2)+(red>>5)+(red>>6) + (green>>1)+(green>>4)+(green>>5) + (blue>>3); \n                  ^~\n%Warning-WIDTH: data/full_repos/permissive/423667690/src/sobel_convolution.v:69: Operator SHIFTR expects 13 bits on the LHS, but LHS\'s VARREF \'red\' generates 8 bits.\n                                                                               : ... In instance sobel_convolution\n  assign gray=(red>>2)+(red>>5)+(red>>6) + (green>>1)+(green>>4)+(green>>5) + (blue>>3); \n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/423667690/src/sobel_convolution.v:69: Operator SHIFTR expects 13 bits on the LHS, but LHS\'s VARREF \'red\' generates 8 bits.\n                                                                               : ... In instance sobel_convolution\n  assign gray=(red>>2)+(red>>5)+(red>>6) + (green>>1)+(green>>4)+(green>>5) + (blue>>3); \n                                    ^~\n%Warning-WIDTH: data/full_repos/permissive/423667690/src/sobel_convolution.v:69: Operator SHIFTR expects 13 bits on the LHS, but LHS\'s VARREF \'green\' generates 8 bits.\n                                                                               : ... In instance sobel_convolution\n  assign gray=(red>>2)+(red>>5)+(red>>6) + (green>>1)+(green>>4)+(green>>5) + (blue>>3); \n                                                 ^~\n%Warning-WIDTH: data/full_repos/permissive/423667690/src/sobel_convolution.v:69: Operator SHIFTR expects 13 bits on the LHS, but LHS\'s VARREF \'green\' generates 8 bits.\n                                                                               : ... In instance sobel_convolution\n  assign gray=(red>>2)+(red>>5)+(red>>6) + (green>>1)+(green>>4)+(green>>5) + (blue>>3); \n                                                            ^~\n%Warning-WIDTH: data/full_repos/permissive/423667690/src/sobel_convolution.v:69: Operator SHIFTR expects 13 bits on the LHS, but LHS\'s VARREF \'green\' generates 8 bits.\n                                                                               : ... In instance sobel_convolution\n  assign gray=(red>>2)+(red>>5)+(red>>6) + (green>>1)+(green>>4)+(green>>5) + (blue>>3); \n                                                                       ^~\n%Warning-WIDTH: data/full_repos/permissive/423667690/src/sobel_convolution.v:69: Operator SHIFTR expects 13 bits on the LHS, but LHS\'s VARREF \'blue\' generates 8 bits.\n                                                                               : ... In instance sobel_convolution\n  assign gray=(red>>2)+(red>>5)+(red>>6) + (green>>1)+(green>>4)+(green>>5) + (blue>>3); \n                                                                                   ^~\n%Warning-WIDTH: data/full_repos/permissive/423667690/src/sobel_convolution.v:89: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'pixel_counter_q\' generates 11 bits.\n                                                                               : ... In instance sobel_convolution\n    addr_a_y= pixel_counter_q;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/423667690/src/sobel_convolution.v:91: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'pixel_counter_q\' generates 11 bits.\n                                                                               : ... In instance sobel_convolution\n    addr_a_x = pixel_counter_q;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/423667690/src/sobel_convolution.v:96: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 11 bits.\n                                                                               : ... In instance sobel_convolution\n    addr_a_y= pixel_counter_q-640;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/423667690/src/sobel_convolution.v:98: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 11 bits.\n                                                                               : ... In instance sobel_convolution\n    addr_a_x = pixel_counter_q-640;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/423667690/src/sobel_convolution.v:103: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 11 bits.\n                                                                                : ... In instance sobel_convolution\n    addr_a_y= pixel_counter_q-1280;\n            ^\n%Warning-WIDTH: data/full_repos/permissive/423667690/src/sobel_convolution.v:105: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 11 bits.\n                                                                                : ... In instance sobel_convolution\n    addr_a_x = pixel_counter_q-1280;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/423667690/src/sobel_convolution.v:107: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 10 bits.\n                                                                                : ... In instance sobel_convolution\n   din_ram_y= temp1_q + temp2_q + temp3_q;  \n            ^\n%Warning-WIDTH: data/full_repos/permissive/423667690/src/sobel_convolution.v:108: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s ADD generates 10 bits.\n                                                                                : ... In instance sobel_convolution\n   din_ram_x = -temp3_q + temp1_q;  \n             ^\n%Warning-WIDTH: data/full_repos/permissive/423667690/src/sobel_convolution.v:128: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'pixel_counter_q\' generates 11 bits.\n                                                                                : ... In instance sobel_convolution\n      addr_b_d=pixel_counter_q;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/423667690/src/sobel_convolution.v:138: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 11 bits.\n                                                                                : ... In instance sobel_convolution\n       addr_b_d=addr_b_d-1280;\n               ^\n%Error: data/full_repos/permissive/423667690/src/sobel_convolution.v:167: Cannot find file containing module: \'dual_port_sync\'\n  dual_port_sync #(.ADDR_WIDTH(10) , .DATA_WIDTH(8)) m0  \n  ^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423667690/src,data/full_repos/permissive/423667690/dual_port_sync\n             data/full_repos/permissive/423667690/src,data/full_repos/permissive/423667690/dual_port_sync.v\n             data/full_repos/permissive/423667690/src,data/full_repos/permissive/423667690/dual_port_sync.sv\n             dual_port_sync\n             dual_port_sync.v\n             dual_port_sync.sv\n             obj_dir/dual_port_sync\n             obj_dir/dual_port_sync.v\n             obj_dir/dual_port_sync.sv\n%Error: data/full_repos/permissive/423667690/src/sobel_convolution.v:178: Cannot find file containing module: \'dual_port_sync\'\n dual_port_sync #(.ADDR_WIDTH(10) , .DATA_WIDTH(8)) m1  \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423667690/src/sobel_convolution.v:189: Cannot find file containing module: \'dual_port_sync\'\n dual_port_sync #(.ADDR_WIDTH(10) , .DATA_WIDTH(8)) m2  \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423667690/src/sobel_convolution.v:200: Cannot find file containing module: \'dual_port_sync\'\n dual_port_sync #(.ADDR_WIDTH(10) , .DATA_WIDTH(8)) m3  \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423667690/src/sobel_convolution.v:211: Cannot find file containing module: \'dual_port_sync\'\n dual_port_sync #(.ADDR_WIDTH(10) , .DATA_WIDTH(8)) m4   \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423667690/src/sobel_convolution.v:222: Cannot find file containing module: \'dual_port_sync\'\n dual_port_sync #(.ADDR_WIDTH(10) , .DATA_WIDTH(8)) m5   \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/423667690/src/sobel_convolution.v:233: Cannot find file containing module: \'asyn_fifo\'\n asyn_fifo #(.DATA_WIDTH(9), .FIFO_DEPTH_WIDTH(10)) m6  \n ^~~~~~~~~\n%Error: Exiting due to 7 error(s), 18 warning(s)\n'
module sobel_convolution(	
	input wire clk_w,clk_r,rst_n,
	input wire[16:0] din,
	input wire[9:0] data_count_r_sobel,
	input wire rd_fifo,
	output reg rd_en,
	output reg rd_fifo_cam,
	output wire[8:0] dout,
	output wire[9:0] data_count_r
    );
	 

	 localparam init=0,
					loop=1;
					
	 reg state_q,state_d;
	 reg signed[9:0] temp1_q,temp2_q,temp3_q;
	 reg[10:0] pixel_counter_q=1920;
	 reg first_line,second_line,third_line;
	 reg we_1,we_2,we_3,we_4,we_5,we_6;
	 reg signed[7:0] din_ram_x,din_ram_y;
	 reg[9:0] addr_a_x,addr_a_y,addr_b_q,addr_b_d;
	 reg write;
	 reg signed[7:0] data_write;
	 reg signed[7:0] x,y;
	 
	 wire temp_valid;
	 wire[12:0] gray;
	 wire signed[7:0] dout_1,dout_2,dout_3,dout_4,dout_5,dout_6;
	 wire data_available= data_count_r_sobel!=10'd0 && data_count_r_sobel!=10'd1 && data_count_r_sobel!=10'd2 && data_count_r_sobel!=10'd3 && data_count_r_sobel!=10'd4 && data_count_r_sobel!=10'd5;

	 

	 always @(posedge clk_w,negedge rst_n) begin
		if(!rst_n) begin
			temp1_q<=0;
			temp2_q<=0;
			temp3_q<=0;
			state_q<=0;
			pixel_counter_q<=1920;
			addr_b_q<=0;
		end
		else begin
			state_q<=state_d;
			rd_en=0;
			addr_b_q<=addr_b_d;
			rd_fifo_cam=0;
			if(data_available) begin
				temp1_q<={3'b000,gray[7:3]};
				temp2_q<=temp1_q;
				temp3_q<=temp2_q;
				pixel_counter_q<=(pixel_counter_q==1919 || pixel_counter_q==1920)? 0:pixel_counter_q+1'b1;
				rd_en=1;
				rd_fifo_cam=1;
			end
		end
	 end
	 

	 

	 wire[7:0] red,green,blue;
	 assign red={din[15:11],3'b000},
				green={din[10:5],2'b00},
				blue={din[4:0],3'b000};
	 
	 assign gray=(red>>2)+(red>>5)+(red>>6) + (green>>1)+(green>>4)+(green>>5) + (blue>>3); 
	 


	 always @* begin
		we_1=0;
		we_2=0;
		we_3=0;
		we_4=0;
		we_5=0;
		we_6=0;
		
		din_ram_x=0; 
		addr_a_x=0;
		din_ram_y=0;
		addr_a_y=0;
		
		if(pixel_counter_q!=1920) begin
			if(first_line) begin
				we_1=1;
				addr_a_y= pixel_counter_q;
				we_4=1;
				addr_a_x = pixel_counter_q;
			end
			
			else if(second_line) begin
				we_2=1;
				addr_a_y= pixel_counter_q-640;
				we_5=1;
				addr_a_x = pixel_counter_q-640;
			end
			
			else if(third_line) begin
				we_3=1;
				addr_a_y= pixel_counter_q-1280;
				we_6=1;
				addr_a_x = pixel_counter_q-1280;
			end
			din_ram_y= temp1_q + temp2_q + temp3_q;
			din_ram_x = -temp3_q + temp1_q;
		end
		
	 end
	 

	 always @* begin
		write=0;
		data_write=0;
		x=0;
		y=0;
		addr_b_d=addr_b_q;
		state_d=state_q;
		
		case(state_q)
			init: if(pixel_counter_q==0 && data_available) begin
						addr_b_d=0;
						state_d=loop;			
					end
			loop: if(data_available) begin
						addr_b_d=pixel_counter_q;
						if(first_line) begin
							addr_b_d=addr_b_d;
							y=dout_1-dout_2;
						end
						else if(second_line) begin
							addr_b_d=addr_b_d-640;
							y=dout_2-dout_3;
						end
						else if(third_line) begin
							addr_b_d=addr_b_d-1280;
							y=dout_3-dout_1;
						end
						
						x= dout_4 + dout_5 + dout_6;
						write=1;
						if(x[7]) x=~x;
						if(y[7]) y=~y;
						data_write=x+y;
						
					end
		default: state_d=init;
		endcase 
	 end
	 
	 
	 
	 always @* begin
		first_line=0;
		second_line=0; 
		third_line=0;
		if(pixel_counter_q<=639) first_line=1;
		else if(pixel_counter_q<=1279) second_line=1;
		else if(pixel_counter_q<=1919) third_line=1;
	 
	 end
	 
	 

	 dual_port_sync #(.ADDR_WIDTH(10) , .DATA_WIDTH(8)) m0
	(
		.clk_r(clk_w),
		.clk_w(clk_w),
		.we(we_1),
		.din(din_ram_y),
		.addr_a(addr_a_y),
		.addr_b(addr_b_d),
		.dout(dout_1)
	);
	
	dual_port_sync #(.ADDR_WIDTH(10) , .DATA_WIDTH(8)) m1
	(
		.clk_r(clk_w),
		.clk_w(clk_w),
		.we(we_2),
		.din(din_ram_y),
		.addr_a(addr_a_y),
		.addr_b(addr_b_d),
		.dout(dout_2)
	);
	
	dual_port_sync #(.ADDR_WIDTH(10) , .DATA_WIDTH(8)) m2
	(
		.clk_r(clk_w),
		.clk_w(clk_w),
		.we(we_3),
		.din(din_ram_y),
		.addr_a(addr_a_y),
		.addr_b(addr_b_d),
		.dout(dout_3)
	);
	
	dual_port_sync #(.ADDR_WIDTH(10) , .DATA_WIDTH(8)) m3
	(
		.clk_r(clk_w),
		.clk_w(clk_w),
		.we(we_4),
		.din(din_ram_x),
		.addr_a(addr_a_x),
		.addr_b(addr_b_d),
		.dout(dout_4)
	);
	
	dual_port_sync #(.ADDR_WIDTH(10) , .DATA_WIDTH(8)) m4
	(
		.clk_r(clk_w),
		.clk_w(clk_w),
		.we(we_5),
		.din(din_ram_x),
		.addr_a(addr_a_x),
		.addr_b(addr_b_d),
		.dout(dout_5)
	);
	
	dual_port_sync #(.ADDR_WIDTH(10) , .DATA_WIDTH(8)) m5
	(
		.clk_r(clk_w),
		.clk_w(clk_w),
		.we(we_6),
		.din(din_ram_x),
		.addr_a(addr_a_x),
		.addr_b(addr_b_d),
		.dout(dout_6)
	);
	
	asyn_fifo #(.DATA_WIDTH(9), .FIFO_DEPTH_WIDTH(10)) m6
	(
		.rst_n(rst_n),
		.clk_write(clk_w),
		.clk_read(clk_r),
		.write(write),
		.read(rd_fifo), 
		.data_write({din[16],data_write}),
		.data_read(dout),
		.full(),
		.empty(),
		.data_count_r(data_count_r) 
    );






endmodule
module sobel_convolution(	
	input wire clk_w,clk_r,rst_n,
	input wire[16:0] din,
	input wire[9:0] data_count_r_sobel,
	input wire rd_fifo,
	output reg rd_en,
	output reg rd_fifo_cam,
	output wire[8:0] dout,
	output wire[9:0] data_count_r
    );

	 

	 localparam init=0,
					loop=1;
					
	 reg state_q,state_d;
	 reg signed[9:0] temp1_q,temp2_q,temp3_q;
	 reg[10:0] pixel_counter_q=1920;
	 reg first_line,second_line,third_line;
	 reg we_1,we_2,we_3,we_4,we_5,we_6;
	 reg signed[7:0] din_ram_x,din_ram_y;
	 reg[9:0] addr_a_x,addr_a_y,addr_b_q,addr_b_d;
	 reg write;
	 reg signed[7:0] data_write;
	 reg signed[7:0] x,y;
	 
	 wire temp_valid;
	 wire[12:0] gray;
	 wire signed[7:0] dout_1,dout_2,dout_3,dout_4,dout_5,dout_6;
	 wire data_available= data_count_r_sobel!=10'd0 && data_count_r_sobel!=10'd1 && data_count_r_sobel!=10'd2 && data_count_r_sobel!=10'd3 && data_count_r_sobel!=10'd4 && data_count_r_sobel!=10'd5;

	 

	 always @(posedge clk_w,negedge rst_n) begin
		if(!rst_n) begin
			temp1_q<=0;
			temp2_q<=0;
			temp3_q<=0;
			state_q<=0;
			pixel_counter_q<=1920;
			addr_b_q<=0;
		end
		else begin
			state_q<=state_d;
			rd_en=0;
			addr_b_q<=addr_b_d;
			rd_fifo_cam=0;
			if(data_available) begin
				temp1_q<={3'b000,gray[7:3]};
				temp2_q<=temp1_q;
				temp3_q<=temp2_q;
				pixel_counter_q<=(pixel_counter_q==1919 || pixel_counter_q==1920)? 0:pixel_counter_q+1'b1;
				rd_en=1;
				rd_fifo_cam=1;
			end
		end
	 end
	 

	 

	 wire[7:0] red,green,blue;
	 assign red={din[15:11],3'b000},
				green={din[10:5],2'b00},
				blue={din[4:0],3'b000};
	 
	 assign gray=(red>>2)+(red>>5)+(red>>6) + (green>>1)+(green>>4)+(green>>5) + (blue>>3); 
	 


	 always @* begin
		we_1=0;
		we_2=0;
		we_3=0;
		we_4=0;
		we_5=0;
		we_6=0;
		
		din_ram_x=0; 
		addr_a_x=0;
		din_ram_y=0;
		addr_a_y=0;
		
		if(pixel_counter_q!=1920) begin
			if(first_line) begin
				we_1=1;
				addr_a_y= pixel_counter_q;
				we_4=1;
				addr_a_x = pixel_counter_q;
			end
			
			else if(second_line) begin
				we_2=1;
				addr_a_y= pixel_counter_q-640;
				we_5=1;
				addr_a_x = pixel_counter_q-640;
			end
			
			else if(third_line) begin
				we_3=1;
				addr_a_y= pixel_counter_q-1280;
				we_6=1;
				addr_a_x = pixel_counter_q-1280;
			end
			din_ram_y= temp1_q + temp2_q + temp3_q;
			din_ram_x = -temp3_q + temp1_q;
		end
		
	 end
	 

	 always @* begin
		write=0;
		data_write=0;
		x=0;
		y=0;
		addr_b_d=addr_b_q;
		state_d=state_q;
		
		case(state_q)
			init: if(pixel_counter_q==0 && data_available) begin
						addr_b_d=0;
						state_d=loop;			
					end
			loop: if(data_available) begin
						addr_b_d=pixel_counter_q;
						if(first_line) begin
							addr_b_d=addr_b_d;
							y=dout_1-dout_2;
						end
						else if(second_line) begin
							addr_b_d=addr_b_d-640;
							y=dout_2-dout_3;
						end
						else if(third_line) begin
							addr_b_d=addr_b_d-1280;
							y=dout_3-dout_1;
						end
						
						x= dout_4 + dout_5 + dout_6;
						write=1;
						if(x[7]) x=~x;
						if(y[7]) y=~y;
						data_write=x+y;
						
					end
		default: state_d=init;
		endcase 
	 end
	 
	 
	 
	 always @* begin
		first_line=0;
		second_line=0; 
		third_line=0;
		if(pixel_counter_q<=639) first_line=1;
		else if(pixel_counter_q<=1279) second_line=1;
		else if(pixel_counter_q<=1919) third_line=1;
	 
	 end
	 
	 

	 dual_port_sync #(.ADDR_WIDTH(10) , .DATA_WIDTH(8)) m0
	(
		.clk_r(clk_w),
		.clk_w(clk_w),
		.we(we_1),
		.din(din_ram_y),
		.addr_a(addr_a_y),
		.addr_b(addr_b_d),
		.dout(dout_1)
	);
	
	dual_port_sync #(.ADDR_WIDTH(10) , .DATA_WIDTH(8)) m1
	(
		.clk_r(clk_w),
		.clk_w(clk_w),
		.we(we_2),
		.din(din_ram_y),
		.addr_a(addr_a_y),
		.addr_b(addr_b_d),
		.dout(dout_2)
	);
	
	dual_port_sync #(.ADDR_WIDTH(10) , .DATA_WIDTH(8)) m2
	(
		.clk_r(clk_w),
		.clk_w(clk_w),
		.we(we_3),
		.din(din_ram_y),
		.addr_a(addr_a_y),
		.addr_b(addr_b_d),
		.dout(dout_3)
	);
	
	dual_port_sync #(.ADDR_WIDTH(10) , .DATA_WIDTH(8)) m3
	(
		.clk_r(clk_w),
		.clk_w(clk_w),
		.we(we_4),
		.din(din_ram_x),
		.addr_a(addr_a_x),
		.addr_b(addr_b_d),
		.dout(dout_4)
	);
	
	dual_port_sync #(.ADDR_WIDTH(10) , .DATA_WIDTH(8)) m4
	(
		.clk_r(clk_w),
		.clk_w(clk_w),
		.we(we_5),
		.din(din_ram_x),
		.addr_a(addr_a_x),
		.addr_b(addr_b_d),
		.dout(dout_5)
	);
	
	dual_port_sync #(.ADDR_WIDTH(10) , .DATA_WIDTH(8)) m5
	(
		.clk_r(clk_w),
		.clk_w(clk_w),
		.we(we_6),
		.din(din_ram_x),
		.addr_a(addr_a_x),
		.addr_b(addr_b_d),
		.dout(dout_6)
	);
	
	asyn_fifo #(.DATA_WIDTH(9), .FIFO_DEPTH_WIDTH(10)) m6
	(
		.rst_n(rst_n),
		.clk_write(clk_w),
		.clk_read(clk_r),
		.write(write),
		.read(rd_fifo), 
		.data_write({din[16],data_write}),
		.data_read(dout),
		.full(),
		.empty(),
		.data_count_r(data_count_r) 
    );






endmodule