data/full_repos/permissive/486598419/6.1/three_state_gates_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/486598419/6.1/three_state_gates_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n      #40 iA=1;\n      ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.1/three_state_gates_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n      #40 iA=0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.1/three_state_gates_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n      #40 iA=1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.1/three_state_gates_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n      #20 iEna=0;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.1/three_state_gates_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n      #40 iEna=1;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/486598419/6.1/three_state_gates_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n      #20 iEna=0;\n      ^\n%Error: data/full_repos/permissive/486598419/6.1/three_state_gates_tb.v:27: Cannot find file containing module: \'three_state_gates\'\n   three_state_gates uut(\n   ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/486598419/6.1,data/full_repos/permissive/486598419/three_state_gates\n             data/full_repos/permissive/486598419/6.1,data/full_repos/permissive/486598419/three_state_gates.v\n             data/full_repos/permissive/486598419/6.1,data/full_repos/permissive/486598419/three_state_gates.sv\n             three_state_gates\n             three_state_gates.v\n             three_state_gates.sv\n             obj_dir/three_state_gates\n             obj_dir/three_state_gates.v\n             obj_dir/three_state_gates.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module three_state_gates_tb;
   reg iA;
   reg iEna;
   wire oTriState;
   three_state_gates uut(
   .iA(iA),
   .iEna(iEna),
   .oTri(oTriState)
   );
   initial
   begin
      iA=0;
      #40 iA=1;
      #40 iA=0;
      #40 iA=1;
   end
   initial
   begin
      iEna=1;
      #20 iEna=0;
      #40 iEna=1;
      #20 iEna=0;
   end
endmodule
module three_state_gates_tb;

   reg iA;
   reg iEna;
   wire oTriState;
   three_state_gates uut(
   .iA(iA),
   .iEna(iEna),
   .oTri(oTriState)
   );
   initial
   begin
      iA=0;
      #40 iA=1;
      #40 iA=0;
      #40 iA=1;
   end
   initial
   begin
      iEna=1;
      #20 iEna=0;
      #40 iEna=1;
      #20 iEna=0;
   end
endmodule