data/full_repos/permissive/505514178/source_code/Instruction_Memory.v
data/verilator_xmls/903aaa04-a870-4571-80db-23d11f238a7b.xml
module Instruction_Memory(
    input [31:0] PC,
    input reset,
    output [31:0] Instruction_Code
    );

reg [7:0] Mem [48:0];
assign Instruction_Code = {Mem[PC+3],Mem[PC+2],Mem[PC+1],Mem[PC]};

always @(negedge reset)
begin
$readmemh("Instruction.mem",Mem);

end
endmodule
module Instruction_Memory(
    input [31:0] PC,
    input reset,
    output [31:0] Instruction_Code
    );


reg [7:0] Mem [48:0];
assign Instruction_Code = {Mem[PC+3],Mem[PC+2],Mem[PC+1],Mem[PC]};

always @(negedge reset)
begin
$readmemh("Instruction.mem",Mem);

end
endmodule