data/full_repos/permissive/411838135/rv/synth/vsram.v
1: b'%Error: No top level module found\n%Error: Exiting due to 1 error(s)\n'
module sumul64(input clk, input [63:0]a, input [63:0]b, output[127:0]p);



	reg [127:0]pp[0:6];
	assign p = pp[0];
	wire signed [127:0]sa = {{64{a[63]}},a};
	wire unsigned [127:0]ub = {64'b0,b};
	always @(posedge clk)
 		pp[0] <= sa*ub;







endmodule
module sumul64(input clk, input [63:0]a, input [63:0]b, output[127:0]p);




	reg [127:0]pp[0:6];
	assign p = pp[0];
	wire signed [127:0]sa = {{64{a[63]}},a};
	wire unsigned [127:0]ub = {64'b0,b};
	always @(posedge clk)
 		pp[0] <= sa*ub;







endmodule