data/full_repos/permissive/505514178/source_code/BranchPredictor.v
data/verilator_xmls/c4e9000c-9ca9-4d2b-a42f-30f161f1838f.xml
module BranchPredictor(
	input clkFSM,
	input reset,
	input result,
	output reg prediction
    );

parameter S0 = 1'b0, S1 = 1'b1;
reg present_state,next_state;

always@(posedge clkFSM, negedge reset)
begin
if(reset == 0)
present_state = S1;
else if(result == 1)
present_state = S1;
else if(result == 0)
present_state = S0;
end


always@(clkFSM,reset,present_state)
begin
if(reset == 0)
prediction = 1'b1;
else if(present_state == S0)
prediction = 1'b0;
else if(present_state == S1)
present_state = 1'b1;
end
endmodule
module BranchPredictor(
	input clkFSM,
	input reset,
	input result,
	output reg prediction
    );


parameter S0 = 1'b0, S1 = 1'b1;
reg present_state,next_state;

always@(posedge clkFSM, negedge reset)
begin
if(reset == 0)
present_state = S1;
else if(result == 1)
present_state = S1;
else if(result == 0)
present_state = S0;
end


always@(clkFSM,reset,present_state)
begin
if(reset == 0)
prediction = 1'b1;
else if(present_state == S0)
prediction = 1'b0;
else if(present_state == S1)
present_state = 1'b1;
end
endmodule