data/full_repos/permissive/441359809/src/yosys/techlibs/common/gate2lut.v
1: b"%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/common/gate2lut.v:6: Define or directive not defined: '`LUT_WIDTH'\n    wire [`LUT_WIDTH-1:0] AA;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/common/gate2lut.v:10: Define or directive not defined: '`LUT_WIDTH'\n        .WIDTH(`LUT_WIDTH),\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/common/gate2lut.v:23: Define or directive not defined: '`LUT_WIDTH'\n    wire [`LUT_WIDTH-1:0] AA;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/common/gate2lut.v:27: Define or directive not defined: '`LUT_WIDTH'\n        .WIDTH(`LUT_WIDTH),\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/common/gate2lut.v:40: Define or directive not defined: '`LUT_WIDTH'\n    wire [`LUT_WIDTH-1:0] AA;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/common/gate2lut.v:44: Define or directive not defined: '`LUT_WIDTH'\n        .WIDTH(`LUT_WIDTH),\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/common/gate2lut.v:57: Define or directive not defined: '`LUT_WIDTH'\n    wire [`LUT_WIDTH-1:0] AA;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/common/gate2lut.v:61: Define or directive not defined: '`LUT_WIDTH'\n        .WIDTH(`LUT_WIDTH),\n               ^~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/common/gate2lut.v:74: Define or directive not defined: '`LUT_WIDTH'\n    wire [`LUT_WIDTH-1:0] AA;\n          ^~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/common/gate2lut.v:78: Define or directive not defined: '`LUT_WIDTH'\n        .WIDTH(`LUT_WIDTH),\n               ^~~~~~~~~~\n%Error: Exiting due to 10 error(s)\n"
module _90_lut_and (A, B, Y);
    input A, B;
    output Y;

    wire [`LUT_WIDTH-1:0] AA;
    assign AA = {B, A};

    \$lut #(
        .WIDTH(`LUT_WIDTH),
        .LUT(4'b1000)
    ) lut (
        .A(AA),
        .Y(Y)
    );
endmodule
module _90_lut_and (A, B, Y);

    input A, B;
    output Y;

    wire [`LUT_WIDTH-1:0] AA;
    assign AA = {B, A};

    \$lut #(
        .WIDTH(`LUT_WIDTH),
        .LUT(4'b1000)
    ) lut (
        .A(AA),
        .Y(Y)
    );
endmodule