data/full_repos/permissive/525152535/DLNP.v
data/verilator_xmls/b808d106-5cc3-4c02-8f89-7d3ab0cc5f6c.xml
module DLNP
#(
    parameter INIT = 1'b1
)
(
    input  PRESET,
    input  G,
    input  D,
    output Q
);

    reg _l_Q;

    initial begin
        _l_Q = INIT;
    end

    always @(PRESET or G or D) begin
    
        if (PRESET) begin
	        _l_Q = 1'b1;
        end
        else if (~G) begin
	        _l_Q = D;
        end
    end

    assign Q = _l_Q;

endmodule
module DLNP
#(
    parameter INIT = 1'b1
)
(
    input  PRESET,
    input  G,
    input  D,
    output Q
);


    reg _l_Q;

    initial begin
        _l_Q = INIT;
    end

    always @(PRESET or G or D) begin
    
        if (PRESET) begin
	        _l_Q = 1'b1;
        end
        else if (~G) begin
	        _l_Q = D;
        end
    end

    assign Q = _l_Q;

endmodule