data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v
1: b'%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v:196: Unsized constant being X/Z extended to 768 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                               : ... In instance NV_NVDLA_CACC_assembly_buffer\n    abuf_wr_data_0_d1 <= \'bx;   \n                         ^~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v:206: Unsized constant being X/Z extended to 768 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                               : ... In instance NV_NVDLA_CACC_assembly_buffer\n    abuf_wr_data_1_d1 <= \'bx;   \n                         ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v:216: Unsized constant being X/Z extended to 768 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                               : ... In instance NV_NVDLA_CACC_assembly_buffer\n    abuf_wr_data_2_d1 <= \'bx;   \n                         ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v:226: Unsized constant being X/Z extended to 768 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                               : ... In instance NV_NVDLA_CACC_assembly_buffer\n    abuf_wr_data_3_d1 <= \'bx;   \n                         ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v:236: Unsized constant being X/Z extended to 544 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                               : ... In instance NV_NVDLA_CACC_assembly_buffer\n    abuf_wr_data_4_d1 <= \'bx;   \n                         ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v:246: Unsized constant being X/Z extended to 544 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                               : ... In instance NV_NVDLA_CACC_assembly_buffer\n    abuf_wr_data_5_d1 <= \'bx;   \n                         ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v:256: Unsized constant being X/Z extended to 544 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                               : ... In instance NV_NVDLA_CACC_assembly_buffer\n    abuf_wr_data_6_d1 <= \'bx;   \n                         ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v:266: Unsized constant being X/Z extended to 544 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                               : ... In instance NV_NVDLA_CACC_assembly_buffer\n    abuf_wr_data_7_d1 <= \'bx;   \n                         ^~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v:275: Cannot find file containing module: \'nv_ram_rws_32x768\'\nnv_ram_rws_32x768 u_accu_abuf_0 (\n^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc,data/full_repos/permissive/509468557/nv_ram_rws_32x768\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc,data/full_repos/permissive/509468557/nv_ram_rws_32x768.v\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc,data/full_repos/permissive/509468557/nv_ram_rws_32x768.sv\n             nv_ram_rws_32x768\n             nv_ram_rws_32x768.v\n             nv_ram_rws_32x768.sv\n             obj_dir/nv_ram_rws_32x768\n             obj_dir/nv_ram_rws_32x768.v\n             obj_dir/nv_ram_rws_32x768.sv\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v:287: Cannot find file containing module: \'nv_ram_rws_32x768\'\nnv_ram_rws_32x768 u_accu_abuf_1 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v:299: Cannot find file containing module: \'nv_ram_rws_32x768\'\nnv_ram_rws_32x768 u_accu_abuf_2 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v:311: Cannot find file containing module: \'nv_ram_rws_32x768\'\nnv_ram_rws_32x768 u_accu_abuf_3 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v:323: Cannot find file containing module: \'nv_ram_rws_32x544\'\nnv_ram_rws_32x544 u_accu_abuf_4 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v:335: Cannot find file containing module: \'nv_ram_rws_32x544\'\nnv_ram_rws_32x544 u_accu_abuf_5 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v:347: Cannot find file containing module: \'nv_ram_rws_32x544\'\nnv_ram_rws_32x544 u_accu_abuf_6 (\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v:359: Cannot find file containing module: \'nv_ram_rws_32x544\'\nnv_ram_rws_32x544 u_accu_abuf_7 (\n^~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v:813: Unsized constant being X/Z extended to 768 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                               : ... In instance NV_NVDLA_CACC_assembly_buffer\n    abuf_rd_raw_data_0_d2 <= \'bx;   \n                             ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v:823: Unsized constant being X/Z extended to 768 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                               : ... In instance NV_NVDLA_CACC_assembly_buffer\n    abuf_rd_raw_data_1_d2 <= \'bx;   \n                             ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v:833: Unsized constant being X/Z extended to 768 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                               : ... In instance NV_NVDLA_CACC_assembly_buffer\n    abuf_rd_raw_data_2_d2 <= \'bx;   \n                             ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v:843: Unsized constant being X/Z extended to 768 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                               : ... In instance NV_NVDLA_CACC_assembly_buffer\n    abuf_rd_raw_data_3_d2 <= \'bx;   \n                             ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v:853: Unsized constant being X/Z extended to 544 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                               : ... In instance NV_NVDLA_CACC_assembly_buffer\n    abuf_rd_raw_data_4_d2 <= \'bx;   \n                             ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v:863: Unsized constant being X/Z extended to 544 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                               : ... In instance NV_NVDLA_CACC_assembly_buffer\n    abuf_rd_raw_data_5_d2 <= \'bx;   \n                             ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v:873: Unsized constant being X/Z extended to 544 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                               : ... In instance NV_NVDLA_CACC_assembly_buffer\n    abuf_rd_raw_data_6_d2 <= \'bx;   \n                             ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v:883: Unsized constant being X/Z extended to 544 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                               : ... In instance NV_NVDLA_CACC_assembly_buffer\n    abuf_rd_raw_data_7_d2 <= \'bx;   \n                             ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v:921: Unsized constant being X/Z extended to 768 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                               : ... In instance NV_NVDLA_CACC_assembly_buffer\n    abuf_rd_data_0 <= \'bx;   \n                      ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v:931: Unsized constant being X/Z extended to 768 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                               : ... In instance NV_NVDLA_CACC_assembly_buffer\n    abuf_rd_data_1 <= \'bx;   \n                      ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v:941: Unsized constant being X/Z extended to 768 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                               : ... In instance NV_NVDLA_CACC_assembly_buffer\n    abuf_rd_data_2 <= \'bx;   \n                      ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v:951: Unsized constant being X/Z extended to 768 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                               : ... In instance NV_NVDLA_CACC_assembly_buffer\n    abuf_rd_data_3 <= \'bx;   \n                      ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v:961: Unsized constant being X/Z extended to 544 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                               : ... In instance NV_NVDLA_CACC_assembly_buffer\n    abuf_rd_data_4 <= \'bx;   \n                      ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v:971: Unsized constant being X/Z extended to 544 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                               : ... In instance NV_NVDLA_CACC_assembly_buffer\n    abuf_rd_data_5 <= \'bx;   \n                      ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v:981: Unsized constant being X/Z extended to 544 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                               : ... In instance NV_NVDLA_CACC_assembly_buffer\n    abuf_rd_data_6 <= \'bx;   \n                      ^~~\n%Warning-WIDTH: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v:991: Unsized constant being X/Z extended to 544 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\n                                                                                                                                               : ... In instance NV_NVDLA_CACC_assembly_buffer\n    abuf_rd_data_7 <= \'bx;   \n                      ^~~\n%Error: Exiting due to 8 error(s), 24 warning(s)\n'
module NV_NVDLA_CACC_assembly_buffer (
   nvdla_core_clk
  ,nvdla_core_rstn
  ,abuf_rd_addr
  ,abuf_rd_en
  ,abuf_wr_addr
  ,abuf_wr_data_0
  ,abuf_wr_data_1
  ,abuf_wr_data_2
  ,abuf_wr_data_3
  ,abuf_wr_data_4
  ,abuf_wr_data_5
  ,abuf_wr_data_6
  ,abuf_wr_data_7
  ,abuf_wr_en
  ,pwrbus_ram_pd
  ,abuf_rd_data_0
  ,abuf_rd_data_1
  ,abuf_rd_data_2
  ,abuf_rd_data_3
  ,abuf_rd_data_4
  ,abuf_rd_data_5
  ,abuf_rd_data_6
  ,abuf_rd_data_7
  );


input          nvdla_core_clk;
input          nvdla_core_rstn;
input    [4:0] abuf_rd_addr;
input    [7:0] abuf_rd_en;
input    [4:0] abuf_wr_addr;
input  [767:0] abuf_wr_data_0;
input  [767:0] abuf_wr_data_1;
input  [767:0] abuf_wr_data_2;
input  [767:0] abuf_wr_data_3;
input  [543:0] abuf_wr_data_4;
input  [543:0] abuf_wr_data_5;
input  [543:0] abuf_wr_data_6;
input  [543:0] abuf_wr_data_7;
input    [7:0] abuf_wr_en;
input   [31:0] pwrbus_ram_pd;
output [767:0] abuf_rd_data_0;
output [767:0] abuf_rd_data_1;
output [767:0] abuf_rd_data_2;
output [767:0] abuf_rd_data_3;
output [543:0] abuf_rd_data_4;
output [543:0] abuf_rd_data_5;
output [543:0] abuf_rd_data_6;
output [543:0] abuf_rd_data_7;
wire   [767:0] abuf_rd_data_0_w;
wire   [767:0] abuf_rd_data_1_w;
wire   [767:0] abuf_rd_data_2_w;
wire   [767:0] abuf_rd_data_3_w;
wire   [543:0] abuf_rd_data_4_w;
wire   [543:0] abuf_rd_data_5_w;
wire   [543:0] abuf_rd_data_6_w;
wire   [543:0] abuf_rd_data_7_w;
wire   [767:0] abuf_rd_data_ecc_0;
wire   [767:0] abuf_rd_data_ecc_1;
wire   [767:0] abuf_rd_data_ecc_2;
wire   [767:0] abuf_rd_data_ecc_3;
wire   [543:0] abuf_rd_data_ecc_4;
wire   [543:0] abuf_rd_data_ecc_5;
wire   [543:0] abuf_rd_data_ecc_6;
wire   [543:0] abuf_rd_data_ecc_7;
wire   [767:0] abuf_rd_raw_data_0;
wire   [767:0] abuf_rd_raw_data_1;
wire   [767:0] abuf_rd_raw_data_2;
wire   [767:0] abuf_rd_raw_data_3;
wire   [543:0] abuf_rd_raw_data_4;
wire   [543:0] abuf_rd_raw_data_5;
wire   [543:0] abuf_rd_raw_data_6;
wire   [543:0] abuf_rd_raw_data_7;
wire     [7:0] abuf_rd_reg_en;
wire   [767:0] abuf_wr_data_0_d1_w;
wire   [767:0] abuf_wr_data_1_d1_w;
wire   [767:0] abuf_wr_data_2_d1_w;
wire   [767:0] abuf_wr_data_3_d1_w;
wire   [543:0] abuf_wr_data_4_d1_w;
wire   [543:0] abuf_wr_data_5_d1_w;
wire   [543:0] abuf_wr_data_6_d1_w;
wire   [543:0] abuf_wr_data_7_d1_w;
wire     [7:0] abuf_wr_en_d1_w;
reg    [767:0] abuf_rd_data_0;
reg    [767:0] abuf_rd_data_1;
reg    [767:0] abuf_rd_data_2;
reg    [767:0] abuf_rd_data_3;
reg    [543:0] abuf_rd_data_4;
reg    [543:0] abuf_rd_data_5;
reg    [543:0] abuf_rd_data_6;
reg    [543:0] abuf_rd_data_7;
reg      [7:0] abuf_rd_en_d1;
reg      [7:0] abuf_rd_en_d2;
reg    [767:0] abuf_rd_raw_data_0_d2;
reg    [767:0] abuf_rd_raw_data_1_d2;
reg    [767:0] abuf_rd_raw_data_2_d2;
reg    [767:0] abuf_rd_raw_data_3_d2;
reg    [543:0] abuf_rd_raw_data_4_d2;
reg    [543:0] abuf_rd_raw_data_5_d2;
reg    [543:0] abuf_rd_raw_data_6_d2;
reg    [543:0] abuf_rd_raw_data_7_d2;
reg      [4:0] abuf_wr_addr_d1;
reg    [767:0] abuf_wr_data_0_d1;
reg    [767:0] abuf_wr_data_1_d1;
reg    [767:0] abuf_wr_data_2_d1;
reg    [767:0] abuf_wr_data_3_d1;
reg    [543:0] abuf_wr_data_4_d1;
reg    [543:0] abuf_wr_data_5_d1;
reg    [543:0] abuf_wr_data_6_d1;
reg    [543:0] abuf_wr_data_7_d1;
reg      [7:0] abuf_wr_en_d1;































assign abuf_wr_en_d1_w[0] = abuf_wr_en[0];
assign abuf_wr_en_d1_w[1] = abuf_wr_en[1];
assign abuf_wr_en_d1_w[2] = abuf_wr_en[2];
assign abuf_wr_en_d1_w[3] = abuf_wr_en[3];
assign abuf_wr_en_d1_w[4] = abuf_wr_en[4];
assign abuf_wr_en_d1_w[5] = abuf_wr_en[5];
assign abuf_wr_en_d1_w[6] = abuf_wr_en[6];
assign abuf_wr_en_d1_w[7] = abuf_wr_en[7];


assign abuf_wr_data_0_d1_w = abuf_wr_data_0[768-1:0];
assign abuf_wr_data_1_d1_w = abuf_wr_data_1[768-1:0];
assign abuf_wr_data_2_d1_w = abuf_wr_data_2[768-1:0];
assign abuf_wr_data_3_d1_w = abuf_wr_data_3[768-1:0];
assign abuf_wr_data_4_d1_w = abuf_wr_data_4[544-1:0];
assign abuf_wr_data_5_d1_w = abuf_wr_data_5[544-1:0];
assign abuf_wr_data_6_d1_w = abuf_wr_data_6[544-1:0];
assign abuf_wr_data_7_d1_w = abuf_wr_data_7[544-1:0];




always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    abuf_wr_en_d1 <= {8{1'b0}};
  end else begin
  abuf_wr_en_d1 <= abuf_wr_en_d1_w;
  end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    abuf_wr_addr_d1 <= {5{1'b0}};
  end else begin
  abuf_wr_addr_d1 <= abuf_wr_addr;
  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_wr_en_d1_w[0]) == 1'b1) begin
    abuf_wr_data_0_d1 <= {abuf_wr_data_0_d1_w};

  end else if ((abuf_wr_en_d1_w[0]) == 1'b0) begin
  end else begin
    abuf_wr_data_0_d1 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_wr_en_d1_w[1]) == 1'b1) begin
    abuf_wr_data_1_d1 <= {abuf_wr_data_1_d1_w};

  end else if ((abuf_wr_en_d1_w[1]) == 1'b0) begin
  end else begin
    abuf_wr_data_1_d1 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_wr_en_d1_w[2]) == 1'b1) begin
    abuf_wr_data_2_d1 <= {abuf_wr_data_2_d1_w};

  end else if ((abuf_wr_en_d1_w[2]) == 1'b0) begin
  end else begin
    abuf_wr_data_2_d1 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_wr_en_d1_w[3]) == 1'b1) begin
    abuf_wr_data_3_d1 <= {abuf_wr_data_3_d1_w};

  end else if ((abuf_wr_en_d1_w[3]) == 1'b0) begin
  end else begin
    abuf_wr_data_3_d1 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_wr_en_d1_w[4]) == 1'b1) begin
    abuf_wr_data_4_d1 <= {abuf_wr_data_4_d1_w};

  end else if ((abuf_wr_en_d1_w[4]) == 1'b0) begin
  end else begin
    abuf_wr_data_4_d1 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_wr_en_d1_w[5]) == 1'b1) begin
    abuf_wr_data_5_d1 <= {abuf_wr_data_5_d1_w};

  end else if ((abuf_wr_en_d1_w[5]) == 1'b0) begin
  end else begin
    abuf_wr_data_5_d1 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_wr_en_d1_w[6]) == 1'b1) begin
    abuf_wr_data_6_d1 <= {abuf_wr_data_6_d1_w};

  end else if ((abuf_wr_en_d1_w[6]) == 1'b0) begin
  end else begin
    abuf_wr_data_6_d1 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_wr_en_d1_w[7]) == 1'b1) begin
    abuf_wr_data_7_d1 <= {abuf_wr_data_7_d1_w};

  end else if ((abuf_wr_en_d1_w[7]) == 1'b0) begin
  end else begin
    abuf_wr_data_7_d1 <= 'bx;

  end
end





nv_ram_rws_32x768 u_accu_abuf_0 (
   .clk           (nvdla_core_clk)
  ,.ra            (abuf_rd_addr[4:0])
  ,.re            (abuf_rd_en[0])
  ,.dout          (abuf_rd_data_ecc_0[767:0])
  ,.wa            (abuf_wr_addr_d1[4:0])
  ,.we            (abuf_wr_en_d1[0])
  ,.di            (abuf_wr_data_0_d1[767:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  );


nv_ram_rws_32x768 u_accu_abuf_1 (
   .clk           (nvdla_core_clk)
  ,.ra            (abuf_rd_addr[4:0])
  ,.re            (abuf_rd_en[1])
  ,.dout          (abuf_rd_data_ecc_1[767:0])
  ,.wa            (abuf_wr_addr_d1[4:0])
  ,.we            (abuf_wr_en_d1[1])
  ,.di            (abuf_wr_data_1_d1[767:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  );


nv_ram_rws_32x768 u_accu_abuf_2 (
   .clk           (nvdla_core_clk)
  ,.ra            (abuf_rd_addr[4:0])
  ,.re            (abuf_rd_en[2])
  ,.dout          (abuf_rd_data_ecc_2[767:0])
  ,.wa            (abuf_wr_addr_d1[4:0])
  ,.we            (abuf_wr_en_d1[2])
  ,.di            (abuf_wr_data_2_d1[767:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  );


nv_ram_rws_32x768 u_accu_abuf_3 (
   .clk           (nvdla_core_clk)
  ,.ra            (abuf_rd_addr[4:0])
  ,.re            (abuf_rd_en[3])
  ,.dout          (abuf_rd_data_ecc_3[767:0])
  ,.wa            (abuf_wr_addr_d1[4:0])
  ,.we            (abuf_wr_en_d1[3])
  ,.di            (abuf_wr_data_3_d1[767:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  );


nv_ram_rws_32x544 u_accu_abuf_4 (
   .clk           (nvdla_core_clk)
  ,.ra            (abuf_rd_addr[4:0])
  ,.re            (abuf_rd_en[4])
  ,.dout          (abuf_rd_data_ecc_4[543:0])
  ,.wa            (abuf_wr_addr_d1[4:0])
  ,.we            (abuf_wr_en_d1[4])
  ,.di            (abuf_wr_data_4_d1[543:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  );


nv_ram_rws_32x544 u_accu_abuf_5 (
   .clk           (nvdla_core_clk)
  ,.ra            (abuf_rd_addr[4:0])
  ,.re            (abuf_rd_en[5])
  ,.dout          (abuf_rd_data_ecc_5[543:0])
  ,.wa            (abuf_wr_addr_d1[4:0])
  ,.we            (abuf_wr_en_d1[5])
  ,.di            (abuf_wr_data_5_d1[543:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  );


nv_ram_rws_32x544 u_accu_abuf_6 (
   .clk           (nvdla_core_clk)
  ,.ra            (abuf_rd_addr[4:0])
  ,.re            (abuf_rd_en[6])
  ,.dout          (abuf_rd_data_ecc_6[543:0])
  ,.wa            (abuf_wr_addr_d1[4:0])
  ,.we            (abuf_wr_en_d1[6])
  ,.di            (abuf_wr_data_6_d1[543:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  );


nv_ram_rws_32x544 u_accu_abuf_7 (
   .clk           (nvdla_core_clk)
  ,.ra            (abuf_rd_addr[4:0])
  ,.re            (abuf_rd_en[7])
  ,.dout          (abuf_rd_data_ecc_7[543:0])
  ,.wa            (abuf_wr_addr_d1[4:0])
  ,.we            (abuf_wr_en_d1[7])
  ,.di            (abuf_wr_data_7_d1[543:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  );







`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_never #(0,0,"Error! Read and write same entry at same cycle!")      zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, (abuf_wr_en_d1[0] & abuf_rd_en[0] & (abuf_wr_addr_d1 == abuf_rd_addr)));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif


`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_never #(0,0,"Error! Read and write same entry at same cycle!")      zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (abuf_wr_en_d1[1] & abuf_rd_en[1] & (abuf_wr_addr_d1 == abuf_rd_addr)));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif


`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_never #(0,0,"Error! Read and write same entry at same cycle!")      zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (abuf_wr_en_d1[2] & abuf_rd_en[2] & (abuf_wr_addr_d1 == abuf_rd_addr)));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif


`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_never #(0,0,"Error! Read and write same entry at same cycle!")      zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, (abuf_wr_en_d1[3] & abuf_rd_en[3] & (abuf_wr_addr_d1 == abuf_rd_addr)));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif


`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_never #(0,0,"Error! Read and write same entry at same cycle!")      zzz_assert_never_5x (nvdla_core_clk, `ASSERT_RESET, (abuf_wr_en_d1[4] & abuf_rd_en[4] & (abuf_wr_addr_d1 == abuf_rd_addr)));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif


`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_never #(0,0,"Error! Read and write same entry at same cycle!")      zzz_assert_never_6x (nvdla_core_clk, `ASSERT_RESET, (abuf_wr_en_d1[5] & abuf_rd_en[5] & (abuf_wr_addr_d1 == abuf_rd_addr)));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif


`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_never #(0,0,"Error! Read and write same entry at same cycle!")      zzz_assert_never_7x (nvdla_core_clk, `ASSERT_RESET, (abuf_wr_en_d1[6] & abuf_rd_en[6] & (abuf_wr_addr_d1 == abuf_rd_addr)));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif


`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_never #(0,0,"Error! Read and write same entry at same cycle!")      zzz_assert_never_8x (nvdla_core_clk, `ASSERT_RESET, (abuf_wr_en_d1[7] & abuf_rd_en[7] & (abuf_wr_addr_d1 == abuf_rd_addr)));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif












always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    abuf_rd_en_d1 <= {8{1'b0}};
  end else begin
  abuf_rd_en_d1 <= abuf_rd_en;
  end
end





assign abuf_rd_raw_data_0 = abuf_rd_data_ecc_0;
assign abuf_rd_raw_data_1 = abuf_rd_data_ecc_1;
assign abuf_rd_raw_data_2 = abuf_rd_data_ecc_2;
assign abuf_rd_raw_data_3 = abuf_rd_data_ecc_3;
assign abuf_rd_raw_data_4 = abuf_rd_data_ecc_4;
assign abuf_rd_raw_data_5 = abuf_rd_data_ecc_5;
assign abuf_rd_raw_data_6 = abuf_rd_data_ecc_6;
assign abuf_rd_raw_data_7 = abuf_rd_data_ecc_7;


always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    abuf_rd_en_d2 <= {8{1'b0}};
  end else begin
  abuf_rd_en_d2 <= abuf_rd_en_d1;
  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_rd_en_d1[0]) == 1'b1) begin
    abuf_rd_raw_data_0_d2 <= abuf_rd_raw_data_0;

  end else if ((abuf_rd_en_d1[0]) == 1'b0) begin
  end else begin
    abuf_rd_raw_data_0_d2 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_rd_en_d1[1]) == 1'b1) begin
    abuf_rd_raw_data_1_d2 <= abuf_rd_raw_data_1;

  end else if ((abuf_rd_en_d1[1]) == 1'b0) begin
  end else begin
    abuf_rd_raw_data_1_d2 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_rd_en_d1[2]) == 1'b1) begin
    abuf_rd_raw_data_2_d2 <= abuf_rd_raw_data_2;

  end else if ((abuf_rd_en_d1[2]) == 1'b0) begin
  end else begin
    abuf_rd_raw_data_2_d2 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_rd_en_d1[3]) == 1'b1) begin
    abuf_rd_raw_data_3_d2 <= abuf_rd_raw_data_3;

  end else if ((abuf_rd_en_d1[3]) == 1'b0) begin
  end else begin
    abuf_rd_raw_data_3_d2 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_rd_en_d1[4]) == 1'b1) begin
    abuf_rd_raw_data_4_d2 <= abuf_rd_raw_data_4;

  end else if ((abuf_rd_en_d1[4]) == 1'b0) begin
  end else begin
    abuf_rd_raw_data_4_d2 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_rd_en_d1[5]) == 1'b1) begin
    abuf_rd_raw_data_5_d2 <= abuf_rd_raw_data_5;

  end else if ((abuf_rd_en_d1[5]) == 1'b0) begin
  end else begin
    abuf_rd_raw_data_5_d2 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_rd_en_d1[6]) == 1'b1) begin
    abuf_rd_raw_data_6_d2 <= abuf_rd_raw_data_6;

  end else if ((abuf_rd_en_d1[6]) == 1'b0) begin
  end else begin
    abuf_rd_raw_data_6_d2 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_rd_en_d1[7]) == 1'b1) begin
    abuf_rd_raw_data_7_d2 <= abuf_rd_raw_data_7;

  end else if ((abuf_rd_en_d1[7]) == 1'b0) begin
  end else begin
    abuf_rd_raw_data_7_d2 <= 'bx;

  end
end






assign abuf_rd_reg_en[0] = abuf_rd_en_d2[0];
assign abuf_rd_reg_en[1] = abuf_rd_en_d2[1];
assign abuf_rd_reg_en[2] = abuf_rd_en_d2[2];
assign abuf_rd_reg_en[3] = abuf_rd_en_d2[3];
assign abuf_rd_reg_en[4] = abuf_rd_en_d2[4];
assign abuf_rd_reg_en[5] = abuf_rd_en_d2[5];
assign abuf_rd_reg_en[6] = abuf_rd_en_d2[6];
assign abuf_rd_reg_en[7] = abuf_rd_en_d2[7];


assign abuf_rd_data_0_w = abuf_rd_raw_data_0_d2;
assign abuf_rd_data_1_w = abuf_rd_raw_data_1_d2;
assign abuf_rd_data_2_w = abuf_rd_raw_data_2_d2;
assign abuf_rd_data_3_w = abuf_rd_raw_data_3_d2;
assign abuf_rd_data_4_w = abuf_rd_raw_data_4_d2;
assign abuf_rd_data_5_w = abuf_rd_raw_data_5_d2;
assign abuf_rd_data_6_w = abuf_rd_raw_data_6_d2;
assign abuf_rd_data_7_w = abuf_rd_raw_data_7_d2;




always @(posedge nvdla_core_clk) begin
  if ((abuf_rd_reg_en[0]) == 1'b1) begin
    abuf_rd_data_0 <= abuf_rd_data_0_w;

  end else if ((abuf_rd_reg_en[0]) == 1'b0) begin
  end else begin
    abuf_rd_data_0 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_rd_reg_en[1]) == 1'b1) begin
    abuf_rd_data_1 <= abuf_rd_data_1_w;

  end else if ((abuf_rd_reg_en[1]) == 1'b0) begin
  end else begin
    abuf_rd_data_1 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_rd_reg_en[2]) == 1'b1) begin
    abuf_rd_data_2 <= abuf_rd_data_2_w;

  end else if ((abuf_rd_reg_en[2]) == 1'b0) begin
  end else begin
    abuf_rd_data_2 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_rd_reg_en[3]) == 1'b1) begin
    abuf_rd_data_3 <= abuf_rd_data_3_w;

  end else if ((abuf_rd_reg_en[3]) == 1'b0) begin
  end else begin
    abuf_rd_data_3 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_rd_reg_en[4]) == 1'b1) begin
    abuf_rd_data_4 <= abuf_rd_data_4_w;

  end else if ((abuf_rd_reg_en[4]) == 1'b0) begin
  end else begin
    abuf_rd_data_4 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_rd_reg_en[5]) == 1'b1) begin
    abuf_rd_data_5 <= abuf_rd_data_5_w;

  end else if ((abuf_rd_reg_en[5]) == 1'b0) begin
  end else begin
    abuf_rd_data_5 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_rd_reg_en[6]) == 1'b1) begin
    abuf_rd_data_6 <= abuf_rd_data_6_w;

  end else if ((abuf_rd_reg_en[6]) == 1'b0) begin
  end else begin
    abuf_rd_data_6 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_rd_reg_en[7]) == 1'b1) begin
    abuf_rd_data_7 <= abuf_rd_data_7_w;

  end else if ((abuf_rd_reg_en[7]) == 1'b0) begin
  end else begin
    abuf_rd_data_7 <= 'bx;

  end
end



endmodule
module NV_NVDLA_CACC_assembly_buffer (
   nvdla_core_clk
  ,nvdla_core_rstn
  ,abuf_rd_addr
  ,abuf_rd_en
  ,abuf_wr_addr
  ,abuf_wr_data_0
  ,abuf_wr_data_1
  ,abuf_wr_data_2
  ,abuf_wr_data_3
  ,abuf_wr_data_4
  ,abuf_wr_data_5
  ,abuf_wr_data_6
  ,abuf_wr_data_7
  ,abuf_wr_en
  ,pwrbus_ram_pd
  ,abuf_rd_data_0
  ,abuf_rd_data_1
  ,abuf_rd_data_2
  ,abuf_rd_data_3
  ,abuf_rd_data_4
  ,abuf_rd_data_5
  ,abuf_rd_data_6
  ,abuf_rd_data_7
  );



input          nvdla_core_clk;
input          nvdla_core_rstn;
input    [4:0] abuf_rd_addr;
input    [7:0] abuf_rd_en;
input    [4:0] abuf_wr_addr;
input  [767:0] abuf_wr_data_0;
input  [767:0] abuf_wr_data_1;
input  [767:0] abuf_wr_data_2;
input  [767:0] abuf_wr_data_3;
input  [543:0] abuf_wr_data_4;
input  [543:0] abuf_wr_data_5;
input  [543:0] abuf_wr_data_6;
input  [543:0] abuf_wr_data_7;
input    [7:0] abuf_wr_en;
input   [31:0] pwrbus_ram_pd;
output [767:0] abuf_rd_data_0;
output [767:0] abuf_rd_data_1;
output [767:0] abuf_rd_data_2;
output [767:0] abuf_rd_data_3;
output [543:0] abuf_rd_data_4;
output [543:0] abuf_rd_data_5;
output [543:0] abuf_rd_data_6;
output [543:0] abuf_rd_data_7;
wire   [767:0] abuf_rd_data_0_w;
wire   [767:0] abuf_rd_data_1_w;
wire   [767:0] abuf_rd_data_2_w;
wire   [767:0] abuf_rd_data_3_w;
wire   [543:0] abuf_rd_data_4_w;
wire   [543:0] abuf_rd_data_5_w;
wire   [543:0] abuf_rd_data_6_w;
wire   [543:0] abuf_rd_data_7_w;
wire   [767:0] abuf_rd_data_ecc_0;
wire   [767:0] abuf_rd_data_ecc_1;
wire   [767:0] abuf_rd_data_ecc_2;
wire   [767:0] abuf_rd_data_ecc_3;
wire   [543:0] abuf_rd_data_ecc_4;
wire   [543:0] abuf_rd_data_ecc_5;
wire   [543:0] abuf_rd_data_ecc_6;
wire   [543:0] abuf_rd_data_ecc_7;
wire   [767:0] abuf_rd_raw_data_0;
wire   [767:0] abuf_rd_raw_data_1;
wire   [767:0] abuf_rd_raw_data_2;
wire   [767:0] abuf_rd_raw_data_3;
wire   [543:0] abuf_rd_raw_data_4;
wire   [543:0] abuf_rd_raw_data_5;
wire   [543:0] abuf_rd_raw_data_6;
wire   [543:0] abuf_rd_raw_data_7;
wire     [7:0] abuf_rd_reg_en;
wire   [767:0] abuf_wr_data_0_d1_w;
wire   [767:0] abuf_wr_data_1_d1_w;
wire   [767:0] abuf_wr_data_2_d1_w;
wire   [767:0] abuf_wr_data_3_d1_w;
wire   [543:0] abuf_wr_data_4_d1_w;
wire   [543:0] abuf_wr_data_5_d1_w;
wire   [543:0] abuf_wr_data_6_d1_w;
wire   [543:0] abuf_wr_data_7_d1_w;
wire     [7:0] abuf_wr_en_d1_w;
reg    [767:0] abuf_rd_data_0;
reg    [767:0] abuf_rd_data_1;
reg    [767:0] abuf_rd_data_2;
reg    [767:0] abuf_rd_data_3;
reg    [543:0] abuf_rd_data_4;
reg    [543:0] abuf_rd_data_5;
reg    [543:0] abuf_rd_data_6;
reg    [543:0] abuf_rd_data_7;
reg      [7:0] abuf_rd_en_d1;
reg      [7:0] abuf_rd_en_d2;
reg    [767:0] abuf_rd_raw_data_0_d2;
reg    [767:0] abuf_rd_raw_data_1_d2;
reg    [767:0] abuf_rd_raw_data_2_d2;
reg    [767:0] abuf_rd_raw_data_3_d2;
reg    [543:0] abuf_rd_raw_data_4_d2;
reg    [543:0] abuf_rd_raw_data_5_d2;
reg    [543:0] abuf_rd_raw_data_6_d2;
reg    [543:0] abuf_rd_raw_data_7_d2;
reg      [4:0] abuf_wr_addr_d1;
reg    [767:0] abuf_wr_data_0_d1;
reg    [767:0] abuf_wr_data_1_d1;
reg    [767:0] abuf_wr_data_2_d1;
reg    [767:0] abuf_wr_data_3_d1;
reg    [543:0] abuf_wr_data_4_d1;
reg    [543:0] abuf_wr_data_5_d1;
reg    [543:0] abuf_wr_data_6_d1;
reg    [543:0] abuf_wr_data_7_d1;
reg      [7:0] abuf_wr_en_d1;































assign abuf_wr_en_d1_w[0] = abuf_wr_en[0];
assign abuf_wr_en_d1_w[1] = abuf_wr_en[1];
assign abuf_wr_en_d1_w[2] = abuf_wr_en[2];
assign abuf_wr_en_d1_w[3] = abuf_wr_en[3];
assign abuf_wr_en_d1_w[4] = abuf_wr_en[4];
assign abuf_wr_en_d1_w[5] = abuf_wr_en[5];
assign abuf_wr_en_d1_w[6] = abuf_wr_en[6];
assign abuf_wr_en_d1_w[7] = abuf_wr_en[7];


assign abuf_wr_data_0_d1_w = abuf_wr_data_0[768-1:0];
assign abuf_wr_data_1_d1_w = abuf_wr_data_1[768-1:0];
assign abuf_wr_data_2_d1_w = abuf_wr_data_2[768-1:0];
assign abuf_wr_data_3_d1_w = abuf_wr_data_3[768-1:0];
assign abuf_wr_data_4_d1_w = abuf_wr_data_4[544-1:0];
assign abuf_wr_data_5_d1_w = abuf_wr_data_5[544-1:0];
assign abuf_wr_data_6_d1_w = abuf_wr_data_6[544-1:0];
assign abuf_wr_data_7_d1_w = abuf_wr_data_7[544-1:0];




always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    abuf_wr_en_d1 <= {8{1'b0}};
  end else begin
  abuf_wr_en_d1 <= abuf_wr_en_d1_w;
  end
end
always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    abuf_wr_addr_d1 <= {5{1'b0}};
  end else begin
  abuf_wr_addr_d1 <= abuf_wr_addr;
  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_wr_en_d1_w[0]) == 1'b1) begin
    abuf_wr_data_0_d1 <= {abuf_wr_data_0_d1_w};

  end else if ((abuf_wr_en_d1_w[0]) == 1'b0) begin
  end else begin
    abuf_wr_data_0_d1 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_wr_en_d1_w[1]) == 1'b1) begin
    abuf_wr_data_1_d1 <= {abuf_wr_data_1_d1_w};

  end else if ((abuf_wr_en_d1_w[1]) == 1'b0) begin
  end else begin
    abuf_wr_data_1_d1 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_wr_en_d1_w[2]) == 1'b1) begin
    abuf_wr_data_2_d1 <= {abuf_wr_data_2_d1_w};

  end else if ((abuf_wr_en_d1_w[2]) == 1'b0) begin
  end else begin
    abuf_wr_data_2_d1 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_wr_en_d1_w[3]) == 1'b1) begin
    abuf_wr_data_3_d1 <= {abuf_wr_data_3_d1_w};

  end else if ((abuf_wr_en_d1_w[3]) == 1'b0) begin
  end else begin
    abuf_wr_data_3_d1 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_wr_en_d1_w[4]) == 1'b1) begin
    abuf_wr_data_4_d1 <= {abuf_wr_data_4_d1_w};

  end else if ((abuf_wr_en_d1_w[4]) == 1'b0) begin
  end else begin
    abuf_wr_data_4_d1 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_wr_en_d1_w[5]) == 1'b1) begin
    abuf_wr_data_5_d1 <= {abuf_wr_data_5_d1_w};

  end else if ((abuf_wr_en_d1_w[5]) == 1'b0) begin
  end else begin
    abuf_wr_data_5_d1 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_wr_en_d1_w[6]) == 1'b1) begin
    abuf_wr_data_6_d1 <= {abuf_wr_data_6_d1_w};

  end else if ((abuf_wr_en_d1_w[6]) == 1'b0) begin
  end else begin
    abuf_wr_data_6_d1 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_wr_en_d1_w[7]) == 1'b1) begin
    abuf_wr_data_7_d1 <= {abuf_wr_data_7_d1_w};

  end else if ((abuf_wr_en_d1_w[7]) == 1'b0) begin
  end else begin
    abuf_wr_data_7_d1 <= 'bx;

  end
end





nv_ram_rws_32x768 u_accu_abuf_0 (
   .clk           (nvdla_core_clk)
  ,.ra            (abuf_rd_addr[4:0])
  ,.re            (abuf_rd_en[0])
  ,.dout          (abuf_rd_data_ecc_0[767:0])
  ,.wa            (abuf_wr_addr_d1[4:0])
  ,.we            (abuf_wr_en_d1[0])
  ,.di            (abuf_wr_data_0_d1[767:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  );


nv_ram_rws_32x768 u_accu_abuf_1 (
   .clk           (nvdla_core_clk)
  ,.ra            (abuf_rd_addr[4:0])
  ,.re            (abuf_rd_en[1])
  ,.dout          (abuf_rd_data_ecc_1[767:0])
  ,.wa            (abuf_wr_addr_d1[4:0])
  ,.we            (abuf_wr_en_d1[1])
  ,.di            (abuf_wr_data_1_d1[767:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  );


nv_ram_rws_32x768 u_accu_abuf_2 (
   .clk           (nvdla_core_clk)
  ,.ra            (abuf_rd_addr[4:0])
  ,.re            (abuf_rd_en[2])
  ,.dout          (abuf_rd_data_ecc_2[767:0])
  ,.wa            (abuf_wr_addr_d1[4:0])
  ,.we            (abuf_wr_en_d1[2])
  ,.di            (abuf_wr_data_2_d1[767:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  );


nv_ram_rws_32x768 u_accu_abuf_3 (
   .clk           (nvdla_core_clk)
  ,.ra            (abuf_rd_addr[4:0])
  ,.re            (abuf_rd_en[3])
  ,.dout          (abuf_rd_data_ecc_3[767:0])
  ,.wa            (abuf_wr_addr_d1[4:0])
  ,.we            (abuf_wr_en_d1[3])
  ,.di            (abuf_wr_data_3_d1[767:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  );


nv_ram_rws_32x544 u_accu_abuf_4 (
   .clk           (nvdla_core_clk)
  ,.ra            (abuf_rd_addr[4:0])
  ,.re            (abuf_rd_en[4])
  ,.dout          (abuf_rd_data_ecc_4[543:0])
  ,.wa            (abuf_wr_addr_d1[4:0])
  ,.we            (abuf_wr_en_d1[4])
  ,.di            (abuf_wr_data_4_d1[543:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  );


nv_ram_rws_32x544 u_accu_abuf_5 (
   .clk           (nvdla_core_clk)
  ,.ra            (abuf_rd_addr[4:0])
  ,.re            (abuf_rd_en[5])
  ,.dout          (abuf_rd_data_ecc_5[543:0])
  ,.wa            (abuf_wr_addr_d1[4:0])
  ,.we            (abuf_wr_en_d1[5])
  ,.di            (abuf_wr_data_5_d1[543:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  );


nv_ram_rws_32x544 u_accu_abuf_6 (
   .clk           (nvdla_core_clk)
  ,.ra            (abuf_rd_addr[4:0])
  ,.re            (abuf_rd_en[6])
  ,.dout          (abuf_rd_data_ecc_6[543:0])
  ,.wa            (abuf_wr_addr_d1[4:0])
  ,.we            (abuf_wr_en_d1[6])
  ,.di            (abuf_wr_data_6_d1[543:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  );


nv_ram_rws_32x544 u_accu_abuf_7 (
   .clk           (nvdla_core_clk)
  ,.ra            (abuf_rd_addr[4:0])
  ,.re            (abuf_rd_en[7])
  ,.dout          (abuf_rd_data_ecc_7[543:0])
  ,.wa            (abuf_wr_addr_d1[4:0])
  ,.we            (abuf_wr_en_d1[7])
  ,.di            (abuf_wr_data_7_d1[543:0])
  ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0])
  );







`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_never #(0,0,"Error! Read and write same entry at same cycle!")      zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, (abuf_wr_en_d1[0] & abuf_rd_en[0] & (abuf_wr_addr_d1 == abuf_rd_addr)));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif


`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_never #(0,0,"Error! Read and write same entry at same cycle!")      zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (abuf_wr_en_d1[1] & abuf_rd_en[1] & (abuf_wr_addr_d1 == abuf_rd_addr)));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif


`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_never #(0,0,"Error! Read and write same entry at same cycle!")      zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (abuf_wr_en_d1[2] & abuf_rd_en[2] & (abuf_wr_addr_d1 == abuf_rd_addr)));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif


`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_never #(0,0,"Error! Read and write same entry at same cycle!")      zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, (abuf_wr_en_d1[3] & abuf_rd_en[3] & (abuf_wr_addr_d1 == abuf_rd_addr)));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif


`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_never #(0,0,"Error! Read and write same entry at same cycle!")      zzz_assert_never_5x (nvdla_core_clk, `ASSERT_RESET, (abuf_wr_en_d1[4] & abuf_rd_en[4] & (abuf_wr_addr_d1 == abuf_rd_addr)));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif


`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_never #(0,0,"Error! Read and write same entry at same cycle!")      zzz_assert_never_6x (nvdla_core_clk, `ASSERT_RESET, (abuf_wr_en_d1[5] & abuf_rd_en[5] & (abuf_wr_addr_d1 == abuf_rd_addr)));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif


`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_never #(0,0,"Error! Read and write same entry at same cycle!")      zzz_assert_never_7x (nvdla_core_clk, `ASSERT_RESET, (abuf_wr_en_d1[6] & abuf_rd_en[6] & (abuf_wr_addr_d1 == abuf_rd_addr)));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif


`ifdef SPYGLASS_ASSERT_ON
`else










`endif
`ifdef ASSERT_ON
`ifdef FV_ASSERT_ON
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef SYNTHESIS
`define ASSERT_RESET nvdla_core_rstn
`else
`ifdef ASSERT_OFF_RESET_IS_X
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn)
`else
`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn)
`endif
`endif
`endif
`ifndef SYNTHESIS

  nv_assert_never #(0,0,"Error! Read and write same entry at same cycle!")      zzz_assert_never_8x (nvdla_core_clk, `ASSERT_RESET, (abuf_wr_en_d1[7] & abuf_rd_en[7] & (abuf_wr_addr_d1 == abuf_rd_addr)));

`endif
`undef ASSERT_RESET
`endif
`ifdef SPYGLASS_ASSERT_ON
`else










`endif












always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    abuf_rd_en_d1 <= {8{1'b0}};
  end else begin
  abuf_rd_en_d1 <= abuf_rd_en;
  end
end





assign abuf_rd_raw_data_0 = abuf_rd_data_ecc_0;
assign abuf_rd_raw_data_1 = abuf_rd_data_ecc_1;
assign abuf_rd_raw_data_2 = abuf_rd_data_ecc_2;
assign abuf_rd_raw_data_3 = abuf_rd_data_ecc_3;
assign abuf_rd_raw_data_4 = abuf_rd_data_ecc_4;
assign abuf_rd_raw_data_5 = abuf_rd_data_ecc_5;
assign abuf_rd_raw_data_6 = abuf_rd_data_ecc_6;
assign abuf_rd_raw_data_7 = abuf_rd_data_ecc_7;


always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin
  if (!nvdla_core_rstn) begin
    abuf_rd_en_d2 <= {8{1'b0}};
  end else begin
  abuf_rd_en_d2 <= abuf_rd_en_d1;
  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_rd_en_d1[0]) == 1'b1) begin
    abuf_rd_raw_data_0_d2 <= abuf_rd_raw_data_0;

  end else if ((abuf_rd_en_d1[0]) == 1'b0) begin
  end else begin
    abuf_rd_raw_data_0_d2 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_rd_en_d1[1]) == 1'b1) begin
    abuf_rd_raw_data_1_d2 <= abuf_rd_raw_data_1;

  end else if ((abuf_rd_en_d1[1]) == 1'b0) begin
  end else begin
    abuf_rd_raw_data_1_d2 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_rd_en_d1[2]) == 1'b1) begin
    abuf_rd_raw_data_2_d2 <= abuf_rd_raw_data_2;

  end else if ((abuf_rd_en_d1[2]) == 1'b0) begin
  end else begin
    abuf_rd_raw_data_2_d2 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_rd_en_d1[3]) == 1'b1) begin
    abuf_rd_raw_data_3_d2 <= abuf_rd_raw_data_3;

  end else if ((abuf_rd_en_d1[3]) == 1'b0) begin
  end else begin
    abuf_rd_raw_data_3_d2 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_rd_en_d1[4]) == 1'b1) begin
    abuf_rd_raw_data_4_d2 <= abuf_rd_raw_data_4;

  end else if ((abuf_rd_en_d1[4]) == 1'b0) begin
  end else begin
    abuf_rd_raw_data_4_d2 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_rd_en_d1[5]) == 1'b1) begin
    abuf_rd_raw_data_5_d2 <= abuf_rd_raw_data_5;

  end else if ((abuf_rd_en_d1[5]) == 1'b0) begin
  end else begin
    abuf_rd_raw_data_5_d2 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_rd_en_d1[6]) == 1'b1) begin
    abuf_rd_raw_data_6_d2 <= abuf_rd_raw_data_6;

  end else if ((abuf_rd_en_d1[6]) == 1'b0) begin
  end else begin
    abuf_rd_raw_data_6_d2 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_rd_en_d1[7]) == 1'b1) begin
    abuf_rd_raw_data_7_d2 <= abuf_rd_raw_data_7;

  end else if ((abuf_rd_en_d1[7]) == 1'b0) begin
  end else begin
    abuf_rd_raw_data_7_d2 <= 'bx;

  end
end






assign abuf_rd_reg_en[0] = abuf_rd_en_d2[0];
assign abuf_rd_reg_en[1] = abuf_rd_en_d2[1];
assign abuf_rd_reg_en[2] = abuf_rd_en_d2[2];
assign abuf_rd_reg_en[3] = abuf_rd_en_d2[3];
assign abuf_rd_reg_en[4] = abuf_rd_en_d2[4];
assign abuf_rd_reg_en[5] = abuf_rd_en_d2[5];
assign abuf_rd_reg_en[6] = abuf_rd_en_d2[6];
assign abuf_rd_reg_en[7] = abuf_rd_en_d2[7];


assign abuf_rd_data_0_w = abuf_rd_raw_data_0_d2;
assign abuf_rd_data_1_w = abuf_rd_raw_data_1_d2;
assign abuf_rd_data_2_w = abuf_rd_raw_data_2_d2;
assign abuf_rd_data_3_w = abuf_rd_raw_data_3_d2;
assign abuf_rd_data_4_w = abuf_rd_raw_data_4_d2;
assign abuf_rd_data_5_w = abuf_rd_raw_data_5_d2;
assign abuf_rd_data_6_w = abuf_rd_raw_data_6_d2;
assign abuf_rd_data_7_w = abuf_rd_raw_data_7_d2;




always @(posedge nvdla_core_clk) begin
  if ((abuf_rd_reg_en[0]) == 1'b1) begin
    abuf_rd_data_0 <= abuf_rd_data_0_w;

  end else if ((abuf_rd_reg_en[0]) == 1'b0) begin
  end else begin
    abuf_rd_data_0 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_rd_reg_en[1]) == 1'b1) begin
    abuf_rd_data_1 <= abuf_rd_data_1_w;

  end else if ((abuf_rd_reg_en[1]) == 1'b0) begin
  end else begin
    abuf_rd_data_1 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_rd_reg_en[2]) == 1'b1) begin
    abuf_rd_data_2 <= abuf_rd_data_2_w;

  end else if ((abuf_rd_reg_en[2]) == 1'b0) begin
  end else begin
    abuf_rd_data_2 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_rd_reg_en[3]) == 1'b1) begin
    abuf_rd_data_3 <= abuf_rd_data_3_w;

  end else if ((abuf_rd_reg_en[3]) == 1'b0) begin
  end else begin
    abuf_rd_data_3 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_rd_reg_en[4]) == 1'b1) begin
    abuf_rd_data_4 <= abuf_rd_data_4_w;

  end else if ((abuf_rd_reg_en[4]) == 1'b0) begin
  end else begin
    abuf_rd_data_4 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_rd_reg_en[5]) == 1'b1) begin
    abuf_rd_data_5 <= abuf_rd_data_5_w;

  end else if ((abuf_rd_reg_en[5]) == 1'b0) begin
  end else begin
    abuf_rd_data_5 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_rd_reg_en[6]) == 1'b1) begin
    abuf_rd_data_6 <= abuf_rd_data_6_w;

  end else if ((abuf_rd_reg_en[6]) == 1'b0) begin
  end else begin
    abuf_rd_data_6 <= 'bx;

  end
end
always @(posedge nvdla_core_clk) begin
  if ((abuf_rd_reg_en[7]) == 1'b1) begin
    abuf_rd_data_7 <= abuf_rd_data_7_w;

  end else if ((abuf_rd_reg_en[7]) == 1'b0) begin
  end else begin
    abuf_rd_data_7 <= 'bx;

  end
end



endmodule