data/full_repos/permissive/481623724/hw/cores/common/bsv/SyncFIFO.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/481623724/hw/cores/common/bsv/SyncFIFO.v:293: Unsupported: Ignoring delay on this delayed statement.\n        #0\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/481623724/hw/cores/common/bsv/SyncFIFO.v:113: Cannot find file containing module: \'SyncResetA\'\n   SyncResetA#(.RSTDELAY(1))  syncReset (.IN_RST(sRST)\n   ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/481623724/hw/cores/common/bsv,data/full_repos/permissive/481623724/SyncResetA\n             data/full_repos/permissive/481623724/hw/cores/common/bsv,data/full_repos/permissive/481623724/SyncResetA.v\n             data/full_repos/permissive/481623724/hw/cores/common/bsv,data/full_repos/permissive/481623724/SyncResetA.sv\n             SyncResetA\n             SyncResetA.v\n             SyncResetA.sv\n             obj_dir/SyncResetA\n             obj_dir/SyncResetA.v\n             obj_dir/SyncResetA.sv\n%Warning-WIDTH: data/full_repos/permissive/481623724/hw/cores/common/bsv/SyncFIFO.v:247: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n                                                                                       : ... In instance SyncFIFO\n             fifoMem[i] = {((dataWidth + 1)/2){2\'b10}} ;\n                        ^\n%Warning-WIDTH: data/full_repos/permissive/481623724/hw/cores/common/bsv/SyncFIFO.v:249: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n                                                                                       : ... In instance SyncFIFO\n        dDoutReg     = {((dataWidth + 1)/2){2\'b10}} ;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/481623724/hw/cores/common/bsv/SyncFIFO.v:252: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 2 bits.\n                                                                                       : ... In instance SyncFIFO\n        sGEnqPtr = {((indxWidth + 2)/2){2\'b10}} ;\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/481623724/hw/cores/common/bsv/SyncFIFO.v:262: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'sGEnqPtr\' generates 3 bits.\n                                                                                       : ... In instance SyncFIFO\n        sSyncReg1 = sGEnqPtr ;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/481623724/hw/cores/common/bsv/SyncFIFO.v:263: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'sGEnqPtr\' generates 3 bits.\n                                                                                       : ... In instance SyncFIFO\n        sDeqPtr   = sGEnqPtr ;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/481623724/hw/cores/common/bsv/SyncFIFO.v:264: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'sGEnqPtr\' generates 3 bits.\n                                                                                       : ... In instance SyncFIFO\n        dSyncReg1 = sGEnqPtr ;\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/481623724/hw/cores/common/bsv/SyncFIFO.v:265: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s VARREF \'sGEnqPtr\' generates 3 bits.\n                                                                                       : ... In instance SyncFIFO\n        dEnqPtr   = sGEnqPtr ;\n                  ^\n%Error: Exiting due to 1 error(s), 8 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
function [indxWidth:0] incrGray ;
      input [indxWidth:0] grayin;
      input parity ;

      begin: incrGrayBlock
         integer               i;
         reg [indxWidth: 0]    tempshift;
         reg [indxWidth: 0]    flips;

         flips[0] = ! parity ;
         for ( i = 1 ; i < indxWidth ; i = i+1 )
           begin
              tempshift = grayin << (2 + indxWidth - i ) ;
              flips[i]  = parity & grayin[i-1] & ~(| tempshift ) ;
           end
         tempshift = grayin << 2 ;
         flips[indxWidth] = parity & ~(| tempshift ) ;

         incrGray = flips ^ grayin ;
      end
   endfunction
function [indxWidth:0] incrGray ;

      input [indxWidth:0] grayin;
      input parity ;

      begin: incrGrayBlock
         integer               i;
         reg [indxWidth: 0]    tempshift;
         reg [indxWidth: 0]    flips;

         flips[0] = ! parity ;
         for ( i = 1 ; i < indxWidth ; i = i+1 )
           begin
              tempshift = grayin << (2 + indxWidth - i ) ;
              flips[i]  = parity & grayin[i-1] & ~(| tempshift ) ;
           end
         tempshift = grayin << 2 ;
         flips[indxWidth] = parity & ~(| tempshift ) ;

         incrGray = flips ^ grayin ;
      end
   endfunction