data/full_repos/permissive/476477303/verilog/rtl/Peripherals/Registers/DeviceSelect.v
data/verilator_xmls/d9779f10-7774-4588-9c2c-70cf40b8b40f.xml
module DeviceSelect #(
		parameter ID = 4'h0
	)(
		input wire peripheralEnable,
		input wire[15:0] peripheralBus_address,
		output wire[11:0] localAddress,
		output wire deviceEnable
	);

	assign deviceEnable = peripheralEnable && (peripheralBus_address[15:12] == ID);
	assign localAddress = peripheralBus_address[11:0];

endmodule
module DeviceSelect #(
		parameter ID = 4'h0
	)(
		input wire peripheralEnable,
		input wire[15:0] peripheralBus_address,
		output wire[11:0] localAddress,
		output wire deviceEnable
	);


	assign deviceEnable = peripheralEnable && (peripheralBus_address[15:12] == ID);
	assign localAddress = peripheralBus_address[11:0];

endmodule