data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_1/new/tester.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_1/new/tester.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_1/new/tester.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_1/new/tester.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_1/new/tester.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_1/new/tester.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_1/new/tester.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_1/new/tester.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_1/new/tester.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_1/new/tester.v:48: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_1/new/tester.v:25: Cannot find file containing module: \'full_adder\'\n    full_adder a1(cout1,s1,a,b,cin);\n    ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_1/new,data/full_repos/permissive/423958267/full_adder\n             data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_1/new,data/full_repos/permissive/423958267/full_adder.v\n             data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_1/new,data/full_repos/permissive/423958267/full_adder.sv\n             full_adder\n             full_adder.v\n             full_adder.sv\n             obj_dir/full_adder\n             obj_dir/full_adder.v\n             obj_dir/full_adder.sv\n%Error: data/full_repos/permissive/423958267/lab01/lab01.srcs/sim_1/new/tester.v:26: Cannot find file containing module: \'full_adder2\'\n    full_adder2 a2(cout2,s2,a,b,cin);\n    ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tester;
    reg a,b,cin;
    wire cout1,s1,cout2,s2;
    full_adder a1(cout1,s1,a,b,cin);
    full_adder2 a2(cout2,s2,a,b,cin);
    initial
    begin



        #0;
        a=0; b=0; cin=0;
        #10;
        a=0; b=0; cin=1;
        #10;
        a=0; b=1; cin=0;
        #10;
        a=0; b=1; cin=1;
        #10;
        a=1; b=0; cin=0;
        #10;
        a=1; b=0; cin=1;
        #10;
        a=1; b=1; cin=0;
        #10;
        a=1; b=1; cin=1;
        #10;

        $finish;
    end
endmodule
module tester;

    reg a,b,cin;
    wire cout1,s1,cout2,s2;
    full_adder a1(cout1,s1,a,b,cin);
    full_adder2 a2(cout2,s2,a,b,cin);
    initial
    begin



        #0;
        a=0; b=0; cin=0;
        #10;
        a=0; b=0; cin=1;
        #10;
        a=0; b=1; cin=0;
        #10;
        a=0; b=1; cin=1;
        #10;
        a=1; b=0; cin=0;
        #10;
        a=1; b=0; cin=1;
        #10;
        a=1; b=1; cin=0;
        #10;
        a=1; b=1; cin=1;
        #10;

        $finish;
    end
endmodule