data/full_repos/permissive/494622711/verilog/rtl/pong.v
1: b'%Error: data/full_repos/permissive/494622711/verilog/rtl/pong.v:23: Cannot find file containing module: \'ClockDividerPow\'\n    ClockDividerPow #(1) clk25MHz(\n    ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/494622711/verilog/rtl,data/full_repos/permissive/494622711/ClockDividerPow\n             data/full_repos/permissive/494622711/verilog/rtl,data/full_repos/permissive/494622711/ClockDividerPow.v\n             data/full_repos/permissive/494622711/verilog/rtl,data/full_repos/permissive/494622711/ClockDividerPow.sv\n             ClockDividerPow\n             ClockDividerPow.v\n             ClockDividerPow.sv\n             obj_dir/ClockDividerPow\n             obj_dir/ClockDividerPow.v\n             obj_dir/ClockDividerPow.sv\n%Error: data/full_repos/permissive/494622711/verilog/rtl/pong.v:29: Cannot find file containing module: \'ClockDividerPow\'\n    ClockDividerPow #(20) status_led(\n    ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/494622711/verilog/rtl/pong.v:34: Cannot find file containing module: \'HVSync\'\n    HVSync hvsync(\n    ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/494622711/verilog/rtl/pong.v:51: Operator AND expects 32 or 16 bits on the RHS, but RHS\'s CONST \'10\'h3ff\' generates 10 bits.\n                                                                          : ... In instance pong\n    assign platform_pos = ((range - 45)/2) & 10\'h3_ff;\n                                           ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/494622711/verilog/rtl/pong.v:51: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s AND generates 32 or 16 bits.\n                                                                          : ... In instance pong\n    assign platform_pos = ((range - 45)/2) & 10\'h3_ff;\n                        ^\n%Error: data/full_repos/permissive/494622711/verilog/rtl/pong.v:53: Cannot find file containing module: \'vl53l0x_driver\'\n    vl53l0x_driver i2c_driver(\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/494622711/verilog/rtl/pong.v:63: Cannot find file containing module: \'GameEngine\'\n    GameEngine pong(\n    ^~~~~~~~~~\n%Error: Exiting due to 5 error(s), 2 warning(s)\n'
module pong (input clk,
`ifdef USE_POWER_PINS
            inout vccd1,
            inout vssd1,
`endif
            input reset,
            input game_reset,
            inout sda,
            inout scl,
            output hsync,
            output vsync,
            output [3:0] red,
            output [3:0] green,
            output [3:0] blue,
            output wire [15:0] io_oeb
);
    assign io_oeb = 16'h0000;
    wire clk_25;
    wire active_pixels;
    wire [9:0] counter_x;
    wire [9:0] counter_y;
    
    ClockDividerPow #(1) clk25MHz(
        .clk(clk), 
        .clk_out(clk_25)
    );
    
    wire led_clock;
    ClockDividerPow #(20) status_led(
        .clk(clk), 
        .clk_out(led_clock)
    );
    
    HVSync hvsync(
        .clk_vga(clk_25),
        .reset(reset),
        .hsync(hsync),
        .vsync(vsync),
        .counter_x(counter_x),
        .counter_y(counter_y),
        .active_pixels(active_pixels)
    );
    
    wire [9:0] platform_pos;
    wire [15:0] range;
    
    reg set_up_and_run;
    wire error;
    wire max_platform_pos;

    assign platform_pos = ((range - 45)/2) & 10'h3_ff;

    vl53l0x_driver i2c_driver(
        .clk(clk),
        .rst(reset),  
        .setup_and_run(game_reset),        
        .error(error),
        .range(range),
        .sda(sda),
        .scl(scl)
    );

    GameEngine pong(
        .clk(clk),
        .clk_vga(clk_25),
        .clk_input(led_clock),
        .reset(game_reset),
        .active_pixels(active_pixels),
        .counter_x(counter_x),
        .counter_y(counter_y),
        .position(platform_pos),
        .max_platform_pos(max_platform_pos),
        .red(red), 
        .green(green),
        .blue(blue)
    );
    
endmodule
module pong (input clk,
`ifdef USE_POWER_PINS
            inout vccd1,
            inout vssd1,
`endif
            input reset,
            input game_reset,
            inout sda,
            inout scl,
            output hsync,
            output vsync,
            output [3:0] red,
            output [3:0] green,
            output [3:0] blue,
            output wire [15:0] io_oeb
);

    assign io_oeb = 16'h0000;
    wire clk_25;
    wire active_pixels;
    wire [9:0] counter_x;
    wire [9:0] counter_y;
    
    ClockDividerPow #(1) clk25MHz(
        .clk(clk), 
        .clk_out(clk_25)
    );
    
    wire led_clock;
    ClockDividerPow #(20) status_led(
        .clk(clk), 
        .clk_out(led_clock)
    );
    
    HVSync hvsync(
        .clk_vga(clk_25),
        .reset(reset),
        .hsync(hsync),
        .vsync(vsync),
        .counter_x(counter_x),
        .counter_y(counter_y),
        .active_pixels(active_pixels)
    );
    
    wire [9:0] platform_pos;
    wire [15:0] range;
    
    reg set_up_and_run;
    wire error;
    wire max_platform_pos;

    assign platform_pos = ((range - 45)/2) & 10'h3_ff;

    vl53l0x_driver i2c_driver(
        .clk(clk),
        .rst(reset),  
        .setup_and_run(game_reset),        
        .error(error),
        .range(range),
        .sda(sda),
        .scl(scl)
    );

    GameEngine pong(
        .clk(clk),
        .clk_vga(clk_25),
        .clk_input(led_clock),
        .reset(game_reset),
        .active_pixels(active_pixels),
        .counter_x(counter_x),
        .counter_y(counter_y),
        .position(platform_pos),
        .max_platform_pos(max_platform_pos),
        .red(red), 
        .green(green),
        .blue(blue)
    );
    
endmodule