data/full_repos/permissive/521337848/Hardware/procesor/aluX.v
1: b'%Warning-PINMISSING: data/full_repos/permissive/521337848/Hardware/procesor/aluX.v:111: Cell has missing pin: \'sreg3\'\ncollectsubreg csr(.bank(bank[1]),\n              ^~~\n                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/521337848/Hardware/procesor/aluX.v:111: Cell has missing pin: \'sreg4\'\ncollectsubreg csr(.bank(bank[1]),\n              ^~~\n%Error: Exiting due to 2 warning(s)\n'
module basicALU(

	input[15:0] in,
	
	input[15:0] fexp,
	input sexp,
	
	input[15:0] fromRAM,
	input[15:0] muldiv,
	
	input[15:0] num1,
	input[15:0] num2,
	
	input[3:0] operation,
	
	input[15:0] arg,
	
	output reg[15:0] result,
	output reg overflow,
	output reg block,
	
	output reg save,
	
	output reg readIt
);

wire[16:0] addreg;
wire[15:0] subreg;
wire[15:0] andreg;
wire[15:0] orreg;
wire[15:0] xorreg;

wire[15:0] shlreg;
wire[15:0] shrreg;


wire[15:0] decreg;
wire[16:0] increg;
wire[15:0] muldivreg;

wire[15:0] setreg;
wire[15:0] nullreg;
wire[15:0] notreg;

localparam POP = 4'd0;
localparam ADD = 4'd1;
localparam SUB = 4'd2;
localparam AND = 4'd3;
localparam OR  = 4'd4;
localparam RES = 4'd5;

localparam READ = 4'd6;

localparam SHL = 4'd7;
localparam SHR = 4'd8;
localparam XOR = 4'd9;
localparam NOT = 4'd10;
localparam DEC = 4'd11;
localparam INC = 4'd12;
localparam SET = 4'd13;
localparam IN = 4'd14;
localparam MOV = 4'd15;

wire[15:0] num22 = ((arg == 0) ? num2 : arg);
assign addreg = {num1} + num22;
assign subreg = {num1} - num22;
assign andreg = num1 & num22;
assign orreg = num1 | num22;
assign xorreg = num1 ^ num22;
	
assign decreg = {num1} - 1;
assign increg = {num1} + 1;
assign muldivreg = muldiv;

assign nullreg = num1;
assign notreg = ~(num1);
	
assign shlreg = 0;
assign shrreg = 0;

wire overflowadd = (addreg[16]);
wire overflowsub = (num1[15] & ~subreg[15]);
wire overflowinc = (increg[16]);
wire overflowdec = (num1[15] & ~decreg[15]);

always@(*)
	if(sexp) begin
		result <= fexp;
		overflow <= 0; 
		block <= 1;
		save <= 1;
		readIt <=0;
	end else
		case(operation)
	
			ADD: begin
			
					result <= (addreg[15:0]);
					
					overflow <= overflowadd;
					block <= 0;
					save <= 1;
					readIt <=0;
					end
			SUB: begin
					result <= (subreg[15:0]);
					
					overflow <= (overflowsub); 
					block <= 0;
					save <= 1;
					readIt <=0;
					end
			AND: begin
					result <= andreg;
					overflow <= 0; 
					block <= 0;
					save <= 1;
					readIt <=0;
					end
			OR:  begin
					result <= orreg;
					overflow <= 0; 
					block <= 0;
					save <= 1;
					readIt <=0;
					end
			XOR: begin
					result <= xorreg;
					overflow <= 0; 
					block <= 0;
					save <= 1;
					readIt <=0;
					end
			NOT: begin
					result <= notreg;
					overflow <= 0; 
					block <= 0;
					save <= 1;
					readIt <=0;
					end
			
			SHL: begin
					result <= shlreg;
					overflow <= 0; 
					block <= 0;
					save <= 1;
					readIt <=0;
					end
			SHR: begin
					result <= shrreg; 
					overflow <= 0; 
					block <= 0;
					save <= 1;
					readIt <=0;
					end
			DEC: begin
					
					result <= decreg[15:0];
					
					overflow <= (overflowdec); 
					block <= 0;
					save <= 1;
					readIt <=0;
					end
			INC: begin
			
					result <= increg[15:0];
					
					overflow <= (overflowinc); 
					block <= 0;
					save <= 1;
					readIt <=0;
					end
			RES: begin
					result <= muldivreg;
					overflow <= 0; 
					block <= 1;
					save <= 1;
					readIt <=0;
					end
			SET: begin
					result <= arg;
					overflow <= 0;
					block <= 1;	
					save <= 1;
					readIt <=0;
					end
			READ: begin
					result <= fromRAM;
					overflow <= 0;
					block <= 1;	
					save <= 1;
					readIt <=1;
					end
			IN: begin
					result <= in;
					overflow <= 0; 
					block <= 1;
					save <= 1;
					readIt <=0;
					end
			MOV: begin
					result <= num2;
					overflow <= 0;
					block <= 1;	
					save <= 1;
					readIt <=0;
					end
			default: begin
						result <= nullreg;
						overflow <= 0;
						block <= 1;	
						save <= 0;
						readIt <=0;
						end
		endcase
	
endmodule
module basicALU(

	input[15:0] in,
	
	input[15:0] fexp,
	input sexp,
	
	input[15:0] fromRAM,
	input[15:0] muldiv,
	
	input[15:0] num1,
	input[15:0] num2,
	
	input[3:0] operation,
	
	input[15:0] arg,
	
	output reg[15:0] result,
	output reg overflow,
	output reg block,
	
	output reg save,
	
	output reg readIt
);


wire[16:0] addreg;
wire[15:0] subreg;
wire[15:0] andreg;
wire[15:0] orreg;
wire[15:0] xorreg;

wire[15:0] shlreg;
wire[15:0] shrreg;


wire[15:0] decreg;
wire[16:0] increg;
wire[15:0] muldivreg;

wire[15:0] setreg;
wire[15:0] nullreg;
wire[15:0] notreg;

localparam POP = 4'd0;
localparam ADD = 4'd1;
localparam SUB = 4'd2;
localparam AND = 4'd3;
localparam OR  = 4'd4;
localparam RES = 4'd5;

localparam READ = 4'd6;

localparam SHL = 4'd7;
localparam SHR = 4'd8;
localparam XOR = 4'd9;
localparam NOT = 4'd10;
localparam DEC = 4'd11;
localparam INC = 4'd12;
localparam SET = 4'd13;
localparam IN = 4'd14;
localparam MOV = 4'd15;

wire[15:0] num22 = ((arg == 0) ? num2 : arg);
assign addreg = {num1} + num22;
assign subreg = {num1} - num22;
assign andreg = num1 & num22;
assign orreg = num1 | num22;
assign xorreg = num1 ^ num22;
	
assign decreg = {num1} - 1;
assign increg = {num1} + 1;
assign muldivreg = muldiv;

assign nullreg = num1;
assign notreg = ~(num1);
	
assign shlreg = 0;
assign shrreg = 0;

wire overflowadd = (addreg[16]);
wire overflowsub = (num1[15] & ~subreg[15]);
wire overflowinc = (increg[16]);
wire overflowdec = (num1[15] & ~decreg[15]);

always@(*)
	if(sexp) begin
		result <= fexp;
		overflow <= 0; 
		block <= 1;
		save <= 1;
		readIt <=0;
	end else
		case(operation)
	
			ADD: begin
			
					result <= (addreg[15:0]);
					
					overflow <= overflowadd;
					block <= 0;
					save <= 1;
					readIt <=0;
					end
			SUB: begin
					result <= (subreg[15:0]);
					
					overflow <= (overflowsub); 
					block <= 0;
					save <= 1;
					readIt <=0;
					end
			AND: begin
					result <= andreg;
					overflow <= 0; 
					block <= 0;
					save <= 1;
					readIt <=0;
					end
			OR:  begin
					result <= orreg;
					overflow <= 0; 
					block <= 0;
					save <= 1;
					readIt <=0;
					end
			XOR: begin
					result <= xorreg;
					overflow <= 0; 
					block <= 0;
					save <= 1;
					readIt <=0;
					end
			NOT: begin
					result <= notreg;
					overflow <= 0; 
					block <= 0;
					save <= 1;
					readIt <=0;
					end
			
			SHL: begin
					result <= shlreg;
					overflow <= 0; 
					block <= 0;
					save <= 1;
					readIt <=0;
					end
			SHR: begin
					result <= shrreg; 
					overflow <= 0; 
					block <= 0;
					save <= 1;
					readIt <=0;
					end
			DEC: begin
					
					result <= decreg[15:0];
					
					overflow <= (overflowdec); 
					block <= 0;
					save <= 1;
					readIt <=0;
					end
			INC: begin
			
					result <= increg[15:0];
					
					overflow <= (overflowinc); 
					block <= 0;
					save <= 1;
					readIt <=0;
					end
			RES: begin
					result <= muldivreg;
					overflow <= 0; 
					block <= 1;
					save <= 1;
					readIt <=0;
					end
			SET: begin
					result <= arg;
					overflow <= 0;
					block <= 1;	
					save <= 1;
					readIt <=0;
					end
			READ: begin
					result <= fromRAM;
					overflow <= 0;
					block <= 1;	
					save <= 1;
					readIt <=1;
					end
			IN: begin
					result <= in;
					overflow <= 0; 
					block <= 1;
					save <= 1;
					readIt <=0;
					end
			MOV: begin
					result <= num2;
					overflow <= 0;
					block <= 1;	
					save <= 1;
					readIt <=0;
					end
			default: begin
						result <= nullreg;
						overflow <= 0;
						block <= 1;	
						save <= 0;
						readIt <=0;
						end
		endcase
	
endmodule