data/full_repos/permissive/405912356/rv32i_selector.v
1: b'%Warning-WIDTH: data/full_repos/permissive/405912356/rv32i_selector.v:41: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                        : ... In instance Selector\n            default : out_b = 4\'b0000;\n                            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module Selector (
    input [31:0] rs1,
    input [31:0] rs2,
    input [31:0] imm,
    input [31:0] pc,
    input [2:0] val_sel,
    output reg [31:0] out_a,
    output reg [31:0] out_b
);

    always @* begin
        case (val_sel)
            3'b001: begin
                out_a = rs1;
                out_b = imm;
            end
            3'b010: begin
                out_a = rs1;
                out_b = rs2;
            end
            3'b011: begin
                out_a = pc;
                out_b = imm;
            end
            3'b100: begin
                out_a = pc;
                out_b = imm;
            end
            3'b101: begin
                out_a = rs1;
                out_b = imm;
            end
            3'b110: begin
                out_a = rs1;
                out_b = imm;
            end
            default : out_b = 4'b0000;
        endcase
    end
    
endmodule
module Selector (
    input [31:0] rs1,
    input [31:0] rs2,
    input [31:0] imm,
    input [31:0] pc,
    input [2:0] val_sel,
    output reg [31:0] out_a,
    output reg [31:0] out_b
);


    always @* begin
        case (val_sel)
            3'b001: begin
                out_a = rs1;
                out_b = imm;
            end
            3'b010: begin
                out_a = rs1;
                out_b = rs2;
            end
            3'b011: begin
                out_a = pc;
                out_b = imm;
            end
            3'b100: begin
                out_a = pc;
                out_b = imm;
            end
            3'b101: begin
                out_a = rs1;
                out_b = imm;
            end
            3'b110: begin
                out_a = rs1;
                out_b = imm;
            end
            default : out_b = 4'b0000;
        endcase
    end
    
endmodule