data/full_repos/permissive/426072575/labs/lab3 Gate circuit design - familiarity with experimental environment and development board/codes/verilog/MUX41.v
1: b'%Error: Invalid Option: -\n'
module MUX41(
    input a,
    input b,
    input c,
    input d,
    input sel1,
    input sel2,
    output ot
    );
    reg ot;
    always@(a or b or c or d or sel1 or sel2)
        case({sel1,sel2})
        2'b00:ot=a;
        2'b01:ot=b;
        2'b10:ot=c;
        2'b11:ot=d;
        endcase
endmodule
module MUX41(
    input a,
    input b,
    input c,
    input d,
    input sel1,
    input sel2,
    output ot
    );

    reg ot;
    always@(a or b or c or d or sel1 or sel2)
        case({sel1,sel2})
        2'b00:ot=a;
        2'b01:ot=b;
        2'b10:ot=c;
        2'b11:ot=d;
        endcase
endmodule