data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Finite State Machines/Fsm_serialdp/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines/Fsm_serialdp,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/Fsm_serialdp/top_module.v\n%Error: Exiting due to 5 error(s)\n'
module fsm_next_state (
    input wire in,
    input wire [2:0] state,
    input wire [4:0] bits,
    output reg [2:0] next_state
);

  parameter STATE_IDLE = 3'b000;
  parameter STATE_START = 3'b001;
  parameter STATE_DATA = 3'b010;
  parameter STATE_STOP = 3'b011;
  parameter STATE_ILLIGAL = 3'b111;

  always @(*) begin
    casez ({
      in, state, (bits == 4'd9)
    })

      {1'b0, STATE_IDLE, 1'bz} : next_state = STATE_IDLE;


      {1'b1, STATE_IDLE, 1'bz} : next_state = STATE_START;


      {1'b1, STATE_START, 1'bz} : next_state = STATE_START;


      {1'b0, STATE_START, 1'bz} : next_state = STATE_DATA;


      {1'bz, STATE_DATA, 1'b0} : next_state = STATE_DATA;


      {1'b0, STATE_DATA, 1'b1} : next_state = STATE_IDLE;


      {1'b1, STATE_DATA, 1'b1} : next_state = STATE_STOP;


      {1'b0, STATE_STOP, 1'bz} : next_state = STATE_DATA;


      {1'b1, STATE_STOP, 1'bz} : next_state = STATE_START;


      {1'bz, STATE_ILLIGAL, 1'bz} : next_state = STATE_ILLIGAL;
      default: next_state = STATE_ILLIGAL;
    endcase
  end

endmodule
module fsm_next_state (
    input wire in,
    input wire [2:0] state,
    input wire [4:0] bits,
    output reg [2:0] next_state
);


  parameter STATE_IDLE = 3'b000;
  parameter STATE_START = 3'b001;
  parameter STATE_DATA = 3'b010;
  parameter STATE_STOP = 3'b011;
  parameter STATE_ILLIGAL = 3'b111;

  always @(*) begin
    casez ({
      in, state, (bits == 4'd9)
    })

      {1'b0, STATE_IDLE, 1'bz} : next_state = STATE_IDLE;


      {1'b1, STATE_IDLE, 1'bz} : next_state = STATE_START;


      {1'b1, STATE_START, 1'bz} : next_state = STATE_START;


      {1'b0, STATE_START, 1'bz} : next_state = STATE_DATA;


      {1'bz, STATE_DATA, 1'b0} : next_state = STATE_DATA;


      {1'b0, STATE_DATA, 1'b1} : next_state = STATE_IDLE;


      {1'b1, STATE_DATA, 1'b1} : next_state = STATE_STOP;


      {1'b0, STATE_STOP, 1'bz} : next_state = STATE_DATA;


      {1'b1, STATE_STOP, 1'bz} : next_state = STATE_START;


      {1'bz, STATE_ILLIGAL, 1'bz} : next_state = STATE_ILLIGAL;
      default: next_state = STATE_ILLIGAL;
    endcase
  end

endmodule