data/full_repos/permissive/428125225/cj_clk.v
1: b"%Error: data/full_repos/permissive/428125225/cj_clk.v:9: Duplicate declaration of signal: 'cj_clk_r'\n                                                       : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nwire  cj_clk_r;\n      ^~~~~~~~\n        data/full_repos/permissive/428125225/cj_clk.v:4: ... Location of original declaration\noutput cj_clk_r\n       ^~~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module cj_clk(
input clk,
input    rst,
output cj_clk_r


   );

wire  cj_clk_r;
reg   [20:0] a;
reg  cj_clk;
assign  cj_clk_r =  cj_clk;
always@(posedge clk or posedge rst)
begin
	if(rst == 1'b1)
   begin 
      cj_clk <= 0;
   end
else if (a == 250000 )
  begin 
  a <= 0;
  cj_clk <= ~cj_clk;
  end

 else 
 a <= a + 1;
end

endmodule
module cj_clk(
input clk,
input    rst,
output cj_clk_r


   );


wire  cj_clk_r;
reg   [20:0] a;
reg  cj_clk;
assign  cj_clk_r =  cj_clk;
always@(posedge clk or posedge rst)
begin
	if(rst == 1'b1)
   begin 
      cj_clk <= 0;
   end
else if (a == 250000 )
  begin 
  a <= 0;
  cj_clk <= ~cj_clk;
  end

 else 
 a <= a + 1;
end

endmodule