data/full_repos/permissive/423547971/Verilog Introductory Tutorial Book/modular_verilog.v
1: b'%Error: Cannot find file containing module: Introductory\n        ... Looked in:\n             data/full_repos/permissive/423547971/Verilog/Introductory\n             data/full_repos/permissive/423547971/Verilog/Introductory.v\n             data/full_repos/permissive/423547971/Verilog/Introductory.sv\n             Introductory\n             Introductory.v\n             Introductory.sv\n             obj_dir/Introductory\n             obj_dir/Introductory.v\n             obj_dir/Introductory.sv\n%Error: Cannot find file containing module: Tutorial\n%Error: Cannot find file containing module: Book,data/full_repos/permissive/423547971\n%Error: Cannot find file containing module: data/full_repos/permissive/423547971/Verilog\n%Error: Cannot find file containing module: Book/modular_verilog.v\n%Error: Exiting due to 5 error(s)\n'
module modular_verilog(

	input CLOCK,
	input ENABLE,

	output [7:0] OUT
);

wire [2:0] connection;


binary_counter3 BC3(
	.CLOCK(CLOCK),
	.ENABLE(ENABLE),
	.ctr3(connection)
);

decoder_3x8 DEC(
	.x(connection[2]),
	.y(connection[1]),
	.z(connection[0]),
	.F0(OUT[0]),
	.F1(OUT[1]),
	.F2(OUT[2]),
	.F3(OUT[3]),
	.F4(OUT[4]),
	.F5(OUT[5]),
	.F6(OUT[6]),
	.F7(OUT[7])
);

endmodule
module modular_verilog(

	input CLOCK,
	input ENABLE,

	output [7:0] OUT
);


wire [2:0] connection;


binary_counter3 BC3(
	.CLOCK(CLOCK),
	.ENABLE(ENABLE),
	.ctr3(connection)
);

decoder_3x8 DEC(
	.x(connection[2]),
	.y(connection[1]),
	.z(connection[0]),
	.F0(OUT[0]),
	.F1(OUT[1]),
	.F2(OUT[2]),
	.F3(OUT[3]),
	.F4(OUT[4]),
	.F5(OUT[5]),
	.F6(OUT[6]),
	.F7(OUT[7])
);

endmodule