data/full_repos/permissive/521337848/Hardware/procesor/connector.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/521337848/Hardware/procesor/connector.v:35: Multiple top level modules\n                                                                                        : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                        : ... Top module \'connector\'\nmodule connector(\n       ^~~~~~~~~\n                                                                                        : ... Top module \'innector\'\nmodule innector(\n       ^~~~~~~~\n%Error: Exiting due to 1 warning(s)\n'
module connector(
	input clk,
	input rst,
	
	input[15:0] out1,
	input[15:0] out2,
	
	output reg[31:0] out
);


always@(posedge clk or posedge rst)begin
	
	if(rst) begin
		out <= 0;
		
	end
	else if(out2 !=0) begin
		out <= {out2,out1};

	end
	else begin
		out <= 0;

	end
	
	
	
end


endmodule
module connector(
	input clk,
	input rst,
	
	input[15:0] out1,
	input[15:0] out2,
	
	output reg[31:0] out
);



always@(posedge clk or posedge rst)begin
	
	if(rst) begin
		out <= 0;
		
	end
	else if(out2 !=0) begin
		out <= {out2,out1};

	end
	else begin
		out <= 0;

	end
	
	
	
end


endmodule