data/full_repos/permissive/413230008/Binary-to-BCD/Code/Sources/half_adder.v
data/verilator_xmls/a644ab1c-c80e-4fc2-a187-271ae68afea8.xml
module half_adder(
    input x, y,
    output c, s
    );
    
    assign s = x ^ y;
    assign c = x & y;
    
endmodule
module half_adder(
    input x, y,
    output c, s
    );

    
    assign s = x ^ y;
    assign c = x & y;
    
endmodule