data/full_repos/permissive/446761070/CLOCK/clk_1s.v
data/verilator_xmls/57693f84-bbd4-46f0-8273-176db3b3f65d.xml
module clk_1s(
    input clk,
	 output reg clk_1s
    );
	 
	 reg[31:0] count_clk = 0;
	 
	 always @(posedge clk) begin
	     if (count_clk == 24999999) begin
		      count_clk <= 0;
				clk_1s <= ~clk_1s;
	     end
		  else
		      count_clk <= count_clk + 1;
	 end
	 
endmodule
module clk_1s(
    input clk,
	 output reg clk_1s
    );

	 
	 reg[31:0] count_clk = 0;
	 
	 always @(posedge clk) begin
	     if (count_clk == 24999999) begin
		      count_clk <= 0;
				clk_1s <= ~clk_1s;
	     end
		  else
		      count_clk <= count_clk + 1;
	 end
	 
endmodule