data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/RAM.v
data/verilator_xmls/b520627a-fe0e-44e8-af42-d0ad6f92e270.xml
module RAM #(parameter DATA_WIDTH = 8, MEM_SIZE=1024  ,ADDR_WIDTH = 10)
(

RAM_Clk,
RAM_We,
RAM_Oe,
RAM_Address, 
RAM_Data_In,


RAM_Data_Out
);




localparam [DATA_WIDTH-1:0] DATA0 = 0;





input RAM_Clk;
input RAM_We;
input RAM_Oe;
input [ADDR_WIDTH-1:0] RAM_Address;
input [DATA_WIDTH-1:0] RAM_Data_In;
output [DATA_WIDTH-1:0] RAM_Data_Out;





reg [DATA_WIDTH-1:0] Ram_Array[0:MEM_SIZE-1];
reg [ADDR_WIDTH-1:0] Wrptr;
reg [ADDR_WIDTH-1:0] Rdptr;
reg [DATA_WIDTH-1:0] Q_temp;





always@(posedge RAM_Clk)
begin
	
	if(RAM_We) begin
		Ram_Array[RAM_Address]<=RAM_Data_In;
	end
	
	Q_temp<=Ram_Array[RAM_Address];
	
end





assign RAM_Data_Out = RAM_Oe == 1'b1 ? Q_temp : DATA0;



endmodule
module RAM #(parameter DATA_WIDTH = 8, MEM_SIZE=1024  ,ADDR_WIDTH = 10)
(

RAM_Clk,
RAM_We,
RAM_Oe,
RAM_Address, 
RAM_Data_In,


RAM_Data_Out
);





localparam [DATA_WIDTH-1:0] DATA0 = 0;





input RAM_Clk;
input RAM_We;
input RAM_Oe;
input [ADDR_WIDTH-1:0] RAM_Address;
input [DATA_WIDTH-1:0] RAM_Data_In;
output [DATA_WIDTH-1:0] RAM_Data_Out;





reg [DATA_WIDTH-1:0] Ram_Array[0:MEM_SIZE-1];
reg [ADDR_WIDTH-1:0] Wrptr;
reg [ADDR_WIDTH-1:0] Rdptr;
reg [DATA_WIDTH-1:0] Q_temp;





always@(posedge RAM_Clk)
begin
	
	if(RAM_We) begin
		Ram_Array[RAM_Address]<=RAM_Data_In;
	end
	
	Q_temp<=Ram_Array[RAM_Address];
	
end





assign RAM_Data_Out = RAM_Oe == 1'b1 ? Q_temp : DATA0;



endmodule