data/full_repos/permissive/415491487/sim_src/arithmetic_check.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/415491487/sim_src/arithmetic_check.v:24: Unsupported: Ignoring delay on this delayed statement.\n    always #(clkp / 2.0) begin\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/415491487/sim_src/arithmetic_check.v:29: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/415491487/sim_src/arithmetic_check.v:31: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: data/full_repos/permissive/415491487/sim_src/arithmetic_check.v:35: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Error: Exiting due to 3 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module decode_check();
    reg rst, clk;
    
    reg [23:0] instr;
    
    wire valid;
    wire lit_mv;
    wire [6:0] src;
    wire [6:0] dest;
    
    wire hl;
    wire [11:0] lit;
    
    parameter clkp = 1;
    
    decodeunit d(.clk(clk), .rst(rst), .instr(instr), .valid(valid), .lit_mv(lit_mv), .src(src), .dest(dest), .hl(hl), .lit(lit));
    
    initial instr = 24'h0;
    initial clk = 1'b0;
    initial rst = 1'b0;
    
    always #(clkp / 2.0) begin
        clk = ~clk;
    end
    
    initial begin
        @(posedge clk);
        rst = 1'b1;
        @(posedge clk);
        @(posedge clk);
        rst = 1'b0;
        instr = 24'h7F020;
        @(posedge clk);
        instr = 24'h600FFF;
    end
endmodule
module decode_check();

    reg rst, clk;
    
    reg [23:0] instr;
    
    wire valid;
    wire lit_mv;
    wire [6:0] src;
    wire [6:0] dest;
    
    wire hl;
    wire [11:0] lit;
    
    parameter clkp = 1;
    
    decodeunit d(.clk(clk), .rst(rst), .instr(instr), .valid(valid), .lit_mv(lit_mv), .src(src), .dest(dest), .hl(hl), .lit(lit));
    
    initial instr = 24'h0;
    initial clk = 1'b0;
    initial rst = 1'b0;
    
    always #(clkp / 2.0) begin
        clk = ~clk;
    end
    
    initial begin
        @(posedge clk);
        rst = 1'b1;
        @(posedge clk);
        @(posedge clk);
        rst = 1'b0;
        instr = 24'h7F020;
        @(posedge clk);
        instr = 24'h600FFF;
    end
endmodule