data/full_repos/permissive/414822257/ip/third_party/picorv32_wb/mem_ff_wb.v
1: b"%Error: data/full_repos/permissive/414822257/ip/third_party/picorv32_wb/mem_ff_wb.v:41: Duplicate declaration of signal: 'wb_ack_o'\n                                                                                      : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n  reg wb_ack_o;\n      ^~~~~~~~\n        data/full_repos/permissive/414822257/ip/third_party/picorv32_wb/mem_ff_wb.v:19: ... Location of original declaration\n  output wb_ack_o,\n         ^~~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module mem_ff_wb #(
  parameter MEM_WORDS = 256
)(
  input wb_clk_i,
  input wb_rst_i,

  input [31:0] wb_adr_i,
  input [31:0] wb_dat_i,
  input [3:0] wb_sel_i,
  input wb_we_i,
  input wb_cyc_i,
  input wb_stb_i,

  output wb_ack_o,
  output [31:0] wb_dat_o
);

  localparam ADR_WIDTH = $clog2(MEM_WORDS);

  wire valid;
  wire ram_wen;
  wire [3:0] wen;

  assign valid = wb_cyc_i & wb_stb_i;
  assign ram_wen = wb_we_i && valid;

  assign wen = wb_sel_i & {4{ram_wen}} ;



  reg wb_ack_read;
  reg wb_ack_o;

  always @(posedge wb_clk_i) begin
    if (wb_rst_i == 1'b 1) begin
      wb_ack_read <= 1'b0;
      wb_ack_o <= 1'b0;
    end else begin

      wb_ack_o    <= wb_we_i? (valid & !wb_ack_o): wb_ack_read;
      wb_ack_read <= (valid & !wb_ack_o) & !wb_ack_read;
    end
  end

  ff32_ram #(
    .ADDR_WIDTH(ADR_WIDTH)
  ) ram (
    .clk(wb_clk_i),

    .addr(wb_adr_i[ADR_WIDTH+1:2]),
    .din(wb_dat_i),
    .dout(wb_dat_o),

    .en(valid),
    .wmask(wen)
  );
endmodule
module mem_ff_wb #(
  parameter MEM_WORDS = 256
)(
  input wb_clk_i,
  input wb_rst_i,

  input [31:0] wb_adr_i,
  input [31:0] wb_dat_i,
  input [3:0] wb_sel_i,
  input wb_we_i,
  input wb_cyc_i,
  input wb_stb_i,

  output wb_ack_o,
  output [31:0] wb_dat_o
);


  localparam ADR_WIDTH = $clog2(MEM_WORDS);

  wire valid;
  wire ram_wen;
  wire [3:0] wen;

  assign valid = wb_cyc_i & wb_stb_i;
  assign ram_wen = wb_we_i && valid;

  assign wen = wb_sel_i & {4{ram_wen}} ;



  reg wb_ack_read;
  reg wb_ack_o;

  always @(posedge wb_clk_i) begin
    if (wb_rst_i == 1'b 1) begin
      wb_ack_read <= 1'b0;
      wb_ack_o <= 1'b0;
    end else begin

      wb_ack_o    <= wb_we_i? (valid & !wb_ack_o): wb_ack_read;
      wb_ack_read <= (valid & !wb_ack_o) & !wb_ack_read;
    end
  end

  ff32_ram #(
    .ADDR_WIDTH(ADR_WIDTH)
  ) ram (
    .clk(wb_clk_i),

    .addr(wb_adr_i[ADR_WIDTH+1:2]),
    .din(wb_dat_i),
    .dout(wb_dat_o),

    .en(valid),
    .wmask(wen)
  );
endmodule