data/full_repos/permissive/523038000/MIPS/pc.v
data/verilator_xmls/1bac5748-b001-4a33-924b-6148e929e908.xml
module pc (out , in ,clk, rst);
output [31:0] out;
input [31:0] in;
input clk,rst;
reg [31:0]out;
always @ (posedge clk or posedge rst)
  if(rst==1)
  out = 0;
  else
  out = in;
endmodule
module pc (out , in ,clk, rst);

output [31:0] out;
input [31:0] in;
input clk,rst;
reg [31:0]out;
always @ (posedge clk or posedge rst)
  if(rst==1)
  out = 0;
  else
  out = in;
endmodule