data/full_repos/permissive/527578197/v1/design/top.v
1: b"%Error: data/full_repos/permissive/527578197/v1/design/top.v:23: Cannot find file containing module: 'fetchnum'\nfetchnum fetchnum_inst(\n^~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/527578197/v1/design,data/full_repos/permissive/527578197/fetchnum\n             data/full_repos/permissive/527578197/v1/design,data/full_repos/permissive/527578197/fetchnum.v\n             data/full_repos/permissive/527578197/v1/design,data/full_repos/permissive/527578197/fetchnum.sv\n             fetchnum\n             fetchnum.v\n             fetchnum.sv\n             obj_dir/fetchnum\n             obj_dir/fetchnum.v\n             obj_dir/fetchnum.sv\n%Error: data/full_repos/permissive/527578197/v1/design/top.v:34: Cannot find file containing module: 'bnn_conv'\nbnn_conv bnn_conv_inst(\n^~~~~~~~\n%Error: data/full_repos/permissive/527578197/v1/design/top.v:45: Cannot find file containing module: 'binary'\nbinary #(\n^~~~~~\n%Error: data/full_repos/permissive/527578197/v1/design/top.v:56: Cannot find file containing module: 'mac'\nmac mac_inst(\n^~~\n%Error: data/full_repos/permissive/527578197/v1/design/top.v:66: Cannot find file containing module: 'compare'\ncompare compare_inst(\n^~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module top (
    input   wire                clk                 ,
                                rst_n               ,
                                read_en             ,
    input   wire [15:0]         data_in[1:20]       ,
    output  wire                empty               ,
    output  reg  [1:0]          result      
);


wire [15:0]     data_one[1:5];
wire            fetchnum_vld;

wire [31:0]     conv_out[1:3];
wire [1:0]      conv_out_binarized[1:3];
wire            conv_vld;

wire [9:0]      mac_out[1:2];
wire            mac_done;



fetchnum fetchnum_inst(
                        .clk            (clk),
                        .rst_n          (rst_n),
                        .read_en        (read_en),
                        .data_in        (data_in),
                        .fetchnum_vld   (fetchnum_vld),
                        .data_one       (data_one),
                        .empty          (empty)              
);


bnn_conv bnn_conv_inst(
                        .clk             (clk),
                        .rst_n           (rst_n),
                        .data_in         (data_one),
                        .conv_en         (fetchnum_vld),
                        .conv_out        (conv_out),
                        .conv_vld        (conv_vld),
                        .conv_done       ()
);


binary #(
                        .depth           (32),
                        .target_depth    (2),
                        .WIDTH           (3)
)
binary_inst(
                        .data_raw        (conv_out),
                        .data_binarized  (conv_out_binarized)
);


mac mac_inst(
                        .clk             (clk),
                        .rst_n           (rst_n),
                        .mac_in          (conv_out_binarized),
                        .mac_en          (conv_vld),
                        .mac_out         (mac_out),
                        .mac_done        (mac_done)
);


compare compare_inst(
                        .clk             (clk),
                        .rst_n           (rst_n),
                        .enable          (mac_done),
                        .compare_in      (mac_out),
                        .result          (result)

);

endmodule
module top (
    input   wire                clk                 ,
                                rst_n               ,
                                read_en             ,
    input   wire [15:0]         data_in[1:20]       ,
    output  wire                empty               ,
    output  reg  [1:0]          result      
);



wire [15:0]     data_one[1:5];
wire            fetchnum_vld;

wire [31:0]     conv_out[1:3];
wire [1:0]      conv_out_binarized[1:3];
wire            conv_vld;

wire [9:0]      mac_out[1:2];
wire            mac_done;



fetchnum fetchnum_inst(
                        .clk            (clk),
                        .rst_n          (rst_n),
                        .read_en        (read_en),
                        .data_in        (data_in),
                        .fetchnum_vld   (fetchnum_vld),
                        .data_one       (data_one),
                        .empty          (empty)              
);


bnn_conv bnn_conv_inst(
                        .clk             (clk),
                        .rst_n           (rst_n),
                        .data_in         (data_one),
                        .conv_en         (fetchnum_vld),
                        .conv_out        (conv_out),
                        .conv_vld        (conv_vld),
                        .conv_done       ()
);


binary #(
                        .depth           (32),
                        .target_depth    (2),
                        .WIDTH           (3)
)
binary_inst(
                        .data_raw        (conv_out),
                        .data_binarized  (conv_out_binarized)
);


mac mac_inst(
                        .clk             (clk),
                        .rst_n           (rst_n),
                        .mac_in          (conv_out_binarized),
                        .mac_en          (conv_vld),
                        .mac_out         (mac_out),
                        .mac_done        (mac_done)
);


compare compare_inst(
                        .clk             (clk),
                        .rst_n           (rst_n),
                        .enable          (mac_done),
                        .compare_in      (mac_out),
                        .result          (result)

);

endmodule