data/full_repos/permissive/479997390/src/ALU.v
1: b'%Error: data/full_repos/permissive/479997390/src/ALU.v:1: Cannot find include file: CtrlDef.v\n`include "CtrlDef.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/479997390/src,data/full_repos/permissive/479997390/CtrlDef.v\n             data/full_repos/permissive/479997390/src,data/full_repos/permissive/479997390/CtrlDef.v.v\n             data/full_repos/permissive/479997390/src,data/full_repos/permissive/479997390/CtrlDef.v.sv\n             CtrlDef.v\n             CtrlDef.v.v\n             CtrlDef.v.sv\n             obj_dir/CtrlDef.v\n             obj_dir/CtrlDef.v.v\n             obj_dir/CtrlDef.v.sv\n%Error: data/full_repos/permissive/479997390/src/ALU.v:27: Define or directive not defined: \'`ALUCtrl_XOR\'\n  assign Carry = (ALUCtrl != `ALUCtrl_XOR);\n                             ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/ALU.v:27: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  assign Carry = (ALUCtrl != `ALUCtrl_XOR);\n                                         ^\n%Error: data/full_repos/permissive/479997390/src/ALU.v:46: Define or directive not defined: \'`ALUCtrl_ADD\'\n      `ALUCtrl_ADD, `ALUCtrl_ADDU : begin\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/ALU.v:46: syntax error, unexpected \',\', expecting endcase\n      `ALUCtrl_ADD, `ALUCtrl_ADDU : begin\n                  ^\n%Error: data/full_repos/permissive/479997390/src/ALU.v:46: Define or directive not defined: \'`ALUCtrl_ADDU\'\n      `ALUCtrl_ADD, `ALUCtrl_ADDU : begin\n                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/ALU.v:47: Define or directive not defined: \'`ALUInner_ADD\'\n        Operation = `ALUInner_ADD;\n                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/ALU.v:51: Define or directive not defined: \'`ALUCtrl_SUB\'\n      `ALUCtrl_SUB, `ALUCtrl_SUBU : begin\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/ALU.v:51: syntax error, unexpected \',\'\n      `ALUCtrl_SUB, `ALUCtrl_SUBU : begin\n                  ^\n%Error: data/full_repos/permissive/479997390/src/ALU.v:51: Define or directive not defined: \'`ALUCtrl_SUBU\'\n      `ALUCtrl_SUB, `ALUCtrl_SUBU : begin\n                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/ALU.v:52: Define or directive not defined: \'`ALUInner_ADD\'\n        Operation = `ALUInner_ADD;\n                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/ALU.v:56: Define or directive not defined: \'`ALUCtrl_AND\'\n      `ALUCtrl_AND : begin\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/ALU.v:57: Define or directive not defined: \'`ALUInner_AND\'\n        Operation = `ALUInner_AND;\n                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/ALU.v:61: Define or directive not defined: \'`ALUCtrl_NOR\'\n      `ALUCtrl_NOR : begin\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/ALU.v:62: Define or directive not defined: \'`ALUInner_AND\'\n        Operation = `ALUInner_AND;\n                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/ALU.v:66: Define or directive not defined: \'`ALUCtrl_OR\'\n      `ALUCtrl_OR : begin\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/ALU.v:67: Define or directive not defined: \'`ALUInner_OR\'\n        Operation = `ALUInner_OR;\n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/ALU.v:71: Define or directive not defined: \'`ALUCtrl_XOR\'\n      `ALUCtrl_XOR : begin\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/ALU.v:72: Define or directive not defined: \'`ALUInner_ADD\'\n        Operation = `ALUInner_ADD;\n                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/ALU.v:76: Define or directive not defined: \'`ALUCtrl_SLT\'\n      `ALUCtrl_SLT, `ALUCtrl_SLTU : begin\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/ALU.v:76: Define or directive not defined: \'`ALUCtrl_SLTU\'\n      `ALUCtrl_SLT, `ALUCtrl_SLTU : begin\n                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/ALU.v:77: Define or directive not defined: \'`ALUInner_LESS\'\n        Operation = `ALUInner_LESS;\n                    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/ALU.v:81: Define or directive not defined: \'`ALUCtrl_BEQ\'\n      `ALUCtrl_BEQ : begin\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/ALU.v:82: Define or directive not defined: \'`ALUInner_ADD\'\n        Operation = `ALUInner_ADD;\n                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/ALU.v:87: Define or directive not defined: \'`ALUCtrl_BNE\'\n      `ALUCtrl_BNE : begin\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/ALU.v:88: Define or directive not defined: \'`ALUInner_ADD\'\n        Operation = `ALUInner_ADD;\n                    ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/ALU.v:93: Define or directive not defined: \'`ALUCtrl_SLL\'\n      `ALUCtrl_SLL : begin\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/ALU.v:96: Define or directive not defined: \'`ALUCtrl_SRL\'\n      `ALUCtrl_SRL : begin\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/ALU.v:99: Define or directive not defined: \'`ALUCtrl_SRA\'\n      `ALUCtrl_SRA : begin\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/ALU.v:102: Define or directive not defined: \'`ALUCtrl_LUI\'\n      `ALUCtrl_LUI, `ALUCtrl_JAL : begin\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/ALU.v:102: Define or directive not defined: \'`ALUCtrl_JAL\'\n      `ALUCtrl_LUI, `ALUCtrl_JAL : begin\n                    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/479997390/src/ALU.v:105: Define or directive not defined: \'`ALUCtrl_NULL\'\n      `ALUCtrl_NULL : begin\n      ^~~~~~~~~~~~~\n%Error: Cannot continue\n'
module ALU_UsingAdder (
  ALUIn1,
  ALUIn2,
  ALUInShamt,
  ALUCtrl,
  Zero,
  ALUOut
);

  input [31:0] ALUIn1, ALUIn2;
  input [4:0] ALUInShamt;
  input [4:0] ALUCtrl;
  output Zero;
  output [31:0] ALUOut;

  reg [1:0] Operation;
  reg Anegate, Bnegate;
  wire Signed, Carry;

  wire [31:0] AdderOut;
  reg signed [31:0] ShifterOut;
  wire AdderZero, Overflow;

  assign Signed = ~(ALUCtrl[0]);
  assign Carry = (ALUCtrl != `ALUCtrl_XOR);
  assign Zero = (ALUCtrl[0] & ALUCtrl[1] & ~ALUCtrl[2] & ALUCtrl[3]) ? AdderZero : ~AdderZero;
  assign ALUOut = (ALUCtrl[4]) & (ALUCtrl[1] || ALUCtrl[0]) ? ShifterOut : AdderOut;

  FullAdder32Bits fullAdder32Bits(
    .a(ALUIn1),
    .b(ALUIn2),
    .Operation(Operation),
    .Anegate(Anegate),
    .Bnegate(Bnegate),
    .Signed(Signed),
    .Carry(Carry),
    .Result(AdderOut),
    .Zero(AdderZero),
    .Overflow(Overflow)
  );

  always @(ALUIn1 or ALUIn2 or ALUCtrl) begin
    case (ALUCtrl)
      `ALUCtrl_ADD, `ALUCtrl_ADDU : begin
        Operation = `ALUInner_ADD;
        Anegate = 1'b0;
        Bnegate = 1'b0;
      end
      `ALUCtrl_SUB, `ALUCtrl_SUBU : begin
        Operation = `ALUInner_ADD;
        Anegate = 1'b0;
        Bnegate = 1'b1;
      end
      `ALUCtrl_AND : begin
        Operation = `ALUInner_AND;
        Anegate = 1'b0;
        Bnegate = 1'b0;
      end
      `ALUCtrl_NOR : begin
        Operation = `ALUInner_AND;
        Anegate = 1'b1;
        Bnegate = 1'b1;
      end
      `ALUCtrl_OR : begin
        Operation = `ALUInner_OR;
        Anegate = 1'b0;
        Bnegate = 1'b0;
      end
      `ALUCtrl_XOR : begin
        Operation = `ALUInner_ADD;
        Anegate = 1'b0;
        Bnegate = 1'b0;
      end
      `ALUCtrl_SLT, `ALUCtrl_SLTU : begin
        Operation = `ALUInner_LESS;
        Anegate = 1'b0;
        Bnegate = 1'b1;
      end
      `ALUCtrl_BEQ : begin
        Operation = `ALUInner_ADD;
        Anegate = 1'b0;
        Bnegate = 1'b1;

      end
      `ALUCtrl_BNE : begin
        Operation = `ALUInner_ADD;
        Anegate = 1'b0;
        Bnegate = 1'b1;

      end
      `ALUCtrl_SLL : begin
        ShifterOut = $signed(ALUIn2) << ALUInShamt;
      end
      `ALUCtrl_SRL : begin
        ShifterOut = $signed(ALUIn2) >> ALUInShamt;
      end
      `ALUCtrl_SRA : begin
        ShifterOut = $signed(ALUIn2) >>> ALUInShamt;
      end
      `ALUCtrl_LUI, `ALUCtrl_JAL : begin
        ShifterOut = ALUIn2;
      end
      `ALUCtrl_NULL : begin

        ShifterOut = 0;
      end
      default : begin
        Operation = 1'b0;
        Anegate = 1'b0;
        Bnegate = 1'b0;
      end
    endcase
  end
endmodule
module ALU_UsingAdder (
  ALUIn1,
  ALUIn2,
  ALUInShamt,
  ALUCtrl,
  Zero,
  ALUOut
);


  input [31:0] ALUIn1, ALUIn2;
  input [4:0] ALUInShamt;
  input [4:0] ALUCtrl;
  output Zero;
  output [31:0] ALUOut;

  reg [1:0] Operation;
  reg Anegate, Bnegate;
  wire Signed, Carry;

  wire [31:0] AdderOut;
  reg signed [31:0] ShifterOut;
  wire AdderZero, Overflow;

  assign Signed = ~(ALUCtrl[0]);
  assign Carry = (ALUCtrl != `ALUCtrl_XOR);
  assign Zero = (ALUCtrl[0] & ALUCtrl[1] & ~ALUCtrl[2] & ALUCtrl[3]) ? AdderZero : ~AdderZero;
  assign ALUOut = (ALUCtrl[4]) & (ALUCtrl[1] || ALUCtrl[0]) ? ShifterOut : AdderOut;

  FullAdder32Bits fullAdder32Bits(
    .a(ALUIn1),
    .b(ALUIn2),
    .Operation(Operation),
    .Anegate(Anegate),
    .Bnegate(Bnegate),
    .Signed(Signed),
    .Carry(Carry),
    .Result(AdderOut),
    .Zero(AdderZero),
    .Overflow(Overflow)
  );

  always @(ALUIn1 or ALUIn2 or ALUCtrl) begin
    case (ALUCtrl)
      `ALUCtrl_ADD, `ALUCtrl_ADDU : begin
        Operation = `ALUInner_ADD;
        Anegate = 1'b0;
        Bnegate = 1'b0;
      end
      `ALUCtrl_SUB, `ALUCtrl_SUBU : begin
        Operation = `ALUInner_ADD;
        Anegate = 1'b0;
        Bnegate = 1'b1;
      end
      `ALUCtrl_AND : begin
        Operation = `ALUInner_AND;
        Anegate = 1'b0;
        Bnegate = 1'b0;
      end
      `ALUCtrl_NOR : begin
        Operation = `ALUInner_AND;
        Anegate = 1'b1;
        Bnegate = 1'b1;
      end
      `ALUCtrl_OR : begin
        Operation = `ALUInner_OR;
        Anegate = 1'b0;
        Bnegate = 1'b0;
      end
      `ALUCtrl_XOR : begin
        Operation = `ALUInner_ADD;
        Anegate = 1'b0;
        Bnegate = 1'b0;
      end
      `ALUCtrl_SLT, `ALUCtrl_SLTU : begin
        Operation = `ALUInner_LESS;
        Anegate = 1'b0;
        Bnegate = 1'b1;
      end
      `ALUCtrl_BEQ : begin
        Operation = `ALUInner_ADD;
        Anegate = 1'b0;
        Bnegate = 1'b1;

      end
      `ALUCtrl_BNE : begin
        Operation = `ALUInner_ADD;
        Anegate = 1'b0;
        Bnegate = 1'b1;

      end
      `ALUCtrl_SLL : begin
        ShifterOut = $signed(ALUIn2) << ALUInShamt;
      end
      `ALUCtrl_SRL : begin
        ShifterOut = $signed(ALUIn2) >> ALUInShamt;
      end
      `ALUCtrl_SRA : begin
        ShifterOut = $signed(ALUIn2) >>> ALUInShamt;
      end
      `ALUCtrl_LUI, `ALUCtrl_JAL : begin
        ShifterOut = ALUIn2;
      end
      `ALUCtrl_NULL : begin

        ShifterOut = 0;
      end
      default : begin
        Operation = 1'b0;
        Anegate = 1'b0;
        Bnegate = 1'b0;
      end
    endcase
  end
endmodule