data/full_repos/permissive/493019833/test/testcase/firrtl/StreamingAutocorrelator/sbt/StreamingAutocorrelator.v
data/verilator_xmls/122dc502-941b-4708-90a5-0fed93fff279.xml
module TransposedStreamingFIR(
  input         clock,
  input  [9:0]  io_input,
  output [19:0] io_output,
  input  [9:0]  io_taps_0,
  input  [9:0]  io_taps_1,
  input  [9:0]  io_taps_2
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif
  wire [19:0] products_1 = $signed(io_input) * $signed(io_taps_1);
  wire [19:0] products_2 = $signed(io_input) * $signed(io_taps_0);
  reg [19:0] last;
  reg [19:0] _T_14;
  reg [19:0] _T_19;
  assign io_output = last;
  always @(posedge clock) begin
    last <= $signed(_T_19) + $signed(products_2);
    _T_14 <= $signed(io_input) * $signed(io_taps_2);
    _T_19 <= $signed(_T_14) + $signed(products_1);
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  last = _RAND_0[19:0];
  _RAND_1 = {1{`RANDOM}};
  _T_14 = _RAND_1[19:0];
  _RAND_2 = {1{`RANDOM}};
  _T_19 = _RAND_2[19:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module TransposedStreamingFIR(
  input         clock,
  input  [9:0]  io_input,
  output [19:0] io_output,
  input  [9:0]  io_taps_0,
  input  [9:0]  io_taps_1,
  input  [9:0]  io_taps_2
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif
  wire [19:0] products_1 = $signed(io_input) * $signed(io_taps_1);
  wire [19:0] products_2 = $signed(io_input) * $signed(io_taps_0);
  reg [19:0] last;
  reg [19:0] _T_14;
  reg [19:0] _T_19;
  assign io_output = last;
  always @(posedge clock) begin
    last <= $signed(_T_19) + $signed(products_2);
    _T_14 <= $signed(io_input) * $signed(io_taps_2);
    _T_19 <= $signed(_T_14) + $signed(products_1);
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  last = _RAND_0[19:0];
  _RAND_1 = {1{`RANDOM}};
  _T_14 = _RAND_1[19:0];
  _RAND_2 = {1{`RANDOM}};
  _T_19 = _RAND_2[19:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule