data/full_repos/permissive/487478597/riscv_pipedline_cpu.v
1: b'%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:307: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Raddr1 = instruction[19:15];\n                  ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:308: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Raddr2 = instruction[24:20];\n                  ^\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:309: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n                                                                              : ... In instance top.uut5\n    assign Waddr = instruction[11:7];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/487478597/riscv_pipedline_cpu.v:26: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s EQ generates 1 bits.\n                                                                             : ... In instance top.uut11\n            4\'h4: ALUResult = (in1 == in2);  \n                            ^\n%Error: Exiting due to 4 warning(s)\n'
module DataMem #(parameter addr_width=32, data_width=32, memNum = 12)(
    input MemWrite,
    input MemRead,
    input [addr_width-1:0] addr,
    input [data_width-1:0] Wdata,
    input clk,
    input storeType,
    input [1:0] loadType,
    output reg [data_width-1:0] Rdata
);

    localparam regNum = 1 << memNum;
    reg [7:0] dataMem [regNum-1:0];
    integer i;
    initial begin for(i=0;i<regNum;i=i+1) dataMem[i] = 0; end
    always @(negedge clk) begin
        if (MemRead == 0) Rdata <= 0;
        else begin
            case(loadType)
                2'b00: Rdata <= {dataMem[addr+3], dataMem[addr+2], dataMem[addr+1], dataMem[addr]};
                2'b01: Rdata <= {{24{dataMem[addr][7]}}, dataMem[addr]};
                2'b10: Rdata <= {24'b0, dataMem[addr]};
                default: Rdata <= 0;                    
            endcase
        end
    end
    always @(posedge clk) begin
        if (MemWrite == 1'b1) begin 
            if (storeType == 1'b1) dataMem[addr] <= Wdata[7:0];
            else begin
                {dataMem[addr+3], dataMem[addr+2], dataMem[addr+1], dataMem[addr]} <= Wdata;
            end
        end
    end
endmodule
module DataMem #(parameter addr_width=32, data_width=32, memNum = 12)(
    input MemWrite,
    input MemRead,
    input [addr_width-1:0] addr,
    input [data_width-1:0] Wdata,
    input clk,
    input storeType,
    input [1:0] loadType,
    output reg [data_width-1:0] Rdata
);


    localparam regNum = 1 << memNum;
    reg [7:0] dataMem [regNum-1:0];
    integer i;
    initial begin for(i=0;i<regNum;i=i+1) dataMem[i] = 0; end
    always @(negedge clk) begin
        if (MemRead == 0) Rdata <= 0;
        else begin
            case(loadType)
                2'b00: Rdata <= {dataMem[addr+3], dataMem[addr+2], dataMem[addr+1], dataMem[addr]};
                2'b01: Rdata <= {{24{dataMem[addr][7]}}, dataMem[addr]};
                2'b10: Rdata <= {24'b0, dataMem[addr]};
                default: Rdata <= 0;                    
            endcase
        end
    end
    always @(posedge clk) begin
        if (MemWrite == 1'b1) begin 
            if (storeType == 1'b1) dataMem[addr] <= Wdata[7:0];
            else begin
                {dataMem[addr+3], dataMem[addr+2], dataMem[addr+1], dataMem[addr]} <= Wdata;
            end
        end
    end
endmodule