data/full_repos/permissive/508059792/andm.v
data/verilator_xmls/ea507327-ddea-4e88-9ccb-a1b59944e364.xml
module andm (inA, inB, out);

input inA, inB;
output out;

assign out=inA&inB;

endmodule
module andm (inA, inB, out);


input inA, inB;
output out;

assign out=inA&inB;

endmodule