data/full_repos/permissive/452648646/scripts/not.v
data/verilator_xmls/28653b19-3974-42e0-9eec-babb93fd3670.xml
module BUF(input A, output Y);
wire X;
NOT a(.A(A), .Y(X));
NOT b(.A(X), .Y(Y));
endmodule
module BUF(input A, output Y);

wire X;
NOT a(.A(A), .Y(X));
NOT b(.A(X), .Y(Y));
endmodule