data/full_repos/permissive/488739248/rtl/ttl/ttl_74298.v
1: b'%Error: data/full_repos/permissive/488739248/rtl/ttl/ttl_74298.v:5: Cannot find include file: helper.v\n`include "helper.v" \n         ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/488739248/rtl/ttl,data/full_repos/permissive/488739248/helper.v\n             data/full_repos/permissive/488739248/rtl/ttl,data/full_repos/permissive/488739248/helper.v.v\n             data/full_repos/permissive/488739248/rtl/ttl,data/full_repos/permissive/488739248/helper.v.sv\n             helper.v\n             helper.v.v\n             helper.v.sv\n             obj_dir/helper.v\n             obj_dir/helper.v.v\n             obj_dir/helper.v.sv\n%Error: Exiting due to 1 error(s)\n'
module SR_FF #(parameter DELAY=18)
(
    input wire S,
    input wire R,
    input wire clk,
    output wire Q,
    output wire Qn
);
	reg Qr;
    
	always @(posedge clk)
	begin
        case({S,R})
            2'b00: Qr <= Qr;
            2'b01: Qr <= 1'b0;
            2'b10: Qr <= 1'b1;
            2'b11: Qr <= 1'bx;
        endcase
	end

    assign #DELAY Q  =  Qr;
    assign #DELAY Qn = ~Qr;
endmodule
module SR_FF #(parameter DELAY=18)
(
    input wire S,
    input wire R,
    input wire clk,
    output wire Q,
    output wire Qn
);

	reg Qr;
    
	always @(posedge clk)
	begin
        case({S,R})
            2'b00: Qr <= Qr;
            2'b01: Qr <= 1'b0;
            2'b10: Qr <= 1'b1;
            2'b11: Qr <= 1'bx;
        endcase
	end

    assign #DELAY Q  =  Qr;
    assign #DELAY Qn = ~Qr;
endmodule