data/full_repos/permissive/458737381/src/verilog-parser/tests/std-6.1.2-contassign2.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/458737381/src/verilog-parser/tests/std-6.1.2-contassign2.v:4: Little bit endian vector: MSB < LSB of bit range: 1:16\noutput [1:n] busout;\n       ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/458737381/src/verilog-parser/tests/std-6.1.2-contassign2.v:5: Little bit endian vector: MSB < LSB of bit range: 1:16\ninput [1:n] bus0, bus1, bus2, bus3;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/458737381/src/verilog-parser/tests/std-6.1.2-contassign2.v:7: Little bit endian vector: MSB < LSB of bit range: 1:2\ninput [1:2] s;\n      ^\n%Warning-LITENDIAN: data/full_repos/permissive/458737381/src/verilog-parser/tests/std-6.1.2-contassign2.v:8: Little bit endian vector: MSB < LSB of bit range: 1:16\ntri [1:n] data;\n    ^\n%Error: Exiting due to 4 warning(s)\n'
module select_bus(busout, bus0, bus1, bus2, bus3, enable, s);
parameter n = 16;
parameter Zee = 16'bz;
output [1:n] busout;
input [1:n] bus0, bus1, bus2, bus3;
input enable;
input [1:2] s;
tri [1:n] data;


tri [1:n] busout = enable ? data : Zee;

assign
data = (s == 0) ? bus0 : Zee,
data = (s == 1) ? bus1 : Zee,
data = (s == 2) ? bus2 : Zee,
data = (s == 3) ? bus3 : Zee;
endmodule
module select_bus(busout, bus0, bus1, bus2, bus3, enable, s);

parameter n = 16;
parameter Zee = 16'bz;
output [1:n] busout;
input [1:n] bus0, bus1, bus2, bus3;
input enable;
input [1:2] s;
tri [1:n] data;


tri [1:n] busout = enable ? data : Zee;

assign
data = (s == 0) ? bus0 : Zee,
data = (s == 1) ? bus1 : Zee,
data = (s == 2) ? bus2 : Zee,
data = (s == 3) ? bus3 : Zee;
endmodule