data/full_repos/permissive/525825809/oc-accel/hardware/hdl/oc/mmio.v
1: b'%Error: data/full_repos/permissive/525825809/oc-accel/hardware/hdl/oc/mmio.v:18: Cannot find include file: snap_global_vars.v\n`include "snap_global_vars.v" \n         ^~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/525825809/oc-accel/hardware/hdl/oc,data/full_repos/permissive/525825809/snap_global_vars.v\n             data/full_repos/permissive/525825809/oc-accel/hardware/hdl/oc,data/full_repos/permissive/525825809/snap_global_vars.v.v\n             data/full_repos/permissive/525825809/oc-accel/hardware/hdl/oc,data/full_repos/permissive/525825809/snap_global_vars.v.sv\n             snap_global_vars.v\n             snap_global_vars.v.v\n             snap_global_vars.v.sv\n             obj_dir/snap_global_vars.v\n             obj_dir/snap_global_vars.v.v\n             obj_dir/snap_global_vars.v.sv\n%Error: data/full_repos/permissive/525825809/oc-accel/hardware/hdl/oc/mmio.v:272: Define or directive not defined: \'`IMP_VERSION_DAT\'\n       REG_implementation_vertion  <= `IMP_VERSION_DAT;\n                                      ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525825809/oc-accel/hardware/hdl/oc/mmio.v:272: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       REG_implementation_vertion  <= `IMP_VERSION_DAT;\n                                                      ^\n%Error: data/full_repos/permissive/525825809/oc-accel/hardware/hdl/oc/mmio.v:273: Define or directive not defined: \'`BUILD_DATE_DAT\'\n       REG_build_date              <= `BUILD_DATE_DAT;\n                                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525825809/oc-accel/hardware/hdl/oc/mmio.v:273: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       REG_build_date              <= `BUILD_DATE_DAT;\n                                                     ^\n%Error: data/full_repos/permissive/525825809/oc-accel/hardware/hdl/oc/mmio.v:275: Define or directive not defined: \'`DMA_XFER_SIZE\'\n       REG_capability [39:36]      <= `DMA_XFER_SIZE;\n                                      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525825809/oc-accel/hardware/hdl/oc/mmio.v:275: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       REG_capability [39:36]      <= `DMA_XFER_SIZE;\n                                                    ^\n%Error: data/full_repos/permissive/525825809/oc-accel/hardware/hdl/oc/mmio.v:276: Define or directive not defined: \'`DMA_ALIGNMENT\'\n       REG_capability [35:32]      <= `DMA_ALIGNMENT;\n                                      ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/525825809/oc-accel/hardware/hdl/oc/mmio.v:276: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       REG_capability [35:32]      <= `DMA_ALIGNMENT;\n                                                    ^\n%Error: data/full_repos/permissive/525825809/oc-accel/hardware/hdl/oc/mmio.v:277: Define or directive not defined: \'`SDRAM_SIZE\'\n       REG_capability [31:16]      <= `SDRAM_SIZE;\n                                      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/525825809/oc-accel/hardware/hdl/oc/mmio.v:277: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       REG_capability [31:16]      <= `SDRAM_SIZE;\n                                                 ^\n%Error: data/full_repos/permissive/525825809/oc-accel/hardware/hdl/oc/mmio.v:279: Define or directive not defined: \'`CARD_TYPE\'\n       REG_capability [7:0]        <= `CARD_TYPE;\n                                      ^~~~~~~~~~\n%Error: data/full_repos/permissive/525825809/oc-accel/hardware/hdl/oc/mmio.v:279: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       REG_capability [7:0]        <= `CARD_TYPE;\n                                                ^\n%Error: data/full_repos/permissive/525825809/oc-accel/hardware/hdl/oc/mmio.v:281: Define or directive not defined: \'`USERCODE\'\n       REG_usercode                <= `USERCODE;\n                                      ^~~~~~~~~\n%Error: data/full_repos/permissive/525825809/oc-accel/hardware/hdl/oc/mmio.v:281: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n       REG_usercode                <= `USERCODE;\n                                               ^\n%Error: Exiting due to 15 error(s)\n'
module mmio (
             input                clk                        ,
             input                rst_n                      ,


             output               debug_cnt_clear            ,
             input         [63:0] debug_tlx_cnt_cmd          ,
             input         [63:0] debug_tlx_cnt_rsp          ,
             input         [63:0] debug_tlx_cnt_retry        ,
             input         [63:0] debug_tlx_cnt_fail         ,
             input         [63:0] debug_tlx_cnt_xlt_pd       ,
             input         [63:0] debug_tlx_cnt_xlt_done     ,
             input         [63:0] debug_tlx_cnt_xlt_retry    ,
             input         [63:0] debug_axi_cnt_cmd          , 
             input         [63:0] debug_axi_cnt_rsp          , 
             input         [63:0] debug_buf_cnt              , 
             input         [63:0] debug_traffic_idle         ,
             output        [63:0] debug_tlx_idle_lim         ,
             output        [63:0] debug_axi_idle_lim         ,


             input         [63:0] fir_fifo_overflow          ,
             input         [63:0] fir_tlx_interface          ,


             output reg           soft_reset_brdg_odma       ,
             output reg           soft_reset_action          ,


             input                mmio_wr                    ,
             input                mmio_rd                    ,
             input                mmio_dw                    ,
             input         [31:0] mmio_addr                  ,
             input         [63:0] mmio_din                   ,
             output reg    [63:0] mmio_dout                  ,
             output reg           mmio_done                  ,
             output reg           mmio_failed                ,


             output reg           lcl_wr                     ,
             output reg           lcl_rd                     ,
             output reg    [31:0] lcl_addr                   ,
             output reg    [31:0] lcl_din                    ,
             input                lcl_ack                    ,
             input                lcl_rsp                    ,
             input         [31:0] lcl_dout                   ,
             input                lcl_dv
             );




 reg snap_idle       ;
 reg snap_tlx_busy   ;
 reg snap_axi_busy   ;
 reg snap_fatal_error;

`ifdef ENABLE_NVME
 parameter  NVME_ENABLED    = 1'b1;
`else
 parameter  NVME_ENABLED    = 1'b0;
`endif








 parameter GLOBAL_PP_MMIO_BIT    = 31;
 parameter ACTION_ACCESS_BIT     = 31;





 parameter PASID_START_BIT       = 30;
 parameter PASID_END_BIT         = 22;



 parameter SNAP_BASE_START_BIT   = 21;
 parameter SNAP_BASE_END_BIT     = 8;
 parameter SNAP_OFFSET_START_BIT = 7;
 parameter SNAP_OFFSET_END_BIT   = 0;







 reg [63:00] REG_implementation_vertion;
 reg [63:00] REG_build_date            ;
 reg [63:00] REG_command               ;
 reg [63:00] REG_status                ;
 reg [63:00] REG_capability            ;
 reg [63:00] REG_freeruntime           ;
 reg [63:00] REG_usercode              ;


 reg [63:00] REG_debug_clear            ;
 reg [63:00] REG_debug_tlx_cnt_cmd      ;
 reg [63:00] REG_debug_tlx_cnt_rsp      ;
 reg [63:00] REG_debug_tlx_cnt_retry    ;
 reg [63:00] REG_debug_tlx_cnt_fail     ;
 reg [63:00] REG_debug_tlx_cnt_xlt_pd   ;
 reg [63:00] REG_debug_tlx_cnt_xlt_done ;
 reg [63:00] REG_debug_tlx_cnt_xlt_retry;
 reg [63:00] REG_debug_axi_cnt_cmd      ;
 reg [63:00] REG_debug_axi_cnt_rsp      ;
 reg [63:00] REG_debug_buf_cnt          ;
 reg [63:00] REG_debug_traffic_idle     ;
 reg [63:00] REG_debug_tlx_idle_lim     ;
 reg [63:00] REG_debug_axi_idle_lim     ;


 reg [63:00] REG_fir_fifo_overflow      ;
 reg [63:00] REG_fir_tlx_interface      ;





 parameter REG_SNAP_BASE_ADDR   = 13'h0000,
                REG_SNAP_OFFSET_ADDR_IVR            = 8'h0 ,
                REG_SNAP_OFFSET_ADDR_BDR            = 8'h8 ,
                REG_SNAP_OFFSET_ADDR_SCR            = 8'h10,
                REG_SNAP_OFFSET_ADDR_SSR            = 8'h18,
                REG_SNAP_OFFSET_ADDR_CAP            = 8'h30,
                REG_SNAP_OFFSET_ADDR_FRT            = 8'h40,
                REG_SNAP_OFFSET_ADDR_USR            = 8'h50,

           REG_DEBUG_BASE_ADDR  = 13'h01A0,
                REG_DEBUG_OFFSET_ADDR_DBG_CLR       = 8'h00,
                REG_DEBUG_OFFSET_ADDR_CNT_TLX_CMD   = 8'h08,
                REG_DEBUG_OFFSET_ADDR_CNT_TLX_RSP   = 8'h10,
                REG_DEBUG_OFFSET_ADDR_CNT_TLX_RTY   = 8'h18,
                REG_DEBUG_OFFSET_ADDR_CNT_TLX_FAIL  = 8'h20,
                REG_DEBUG_OFFSET_ADDR_CNT_TLX_XLP   = 8'h28,
                REG_DEBUG_OFFSET_ADDR_CNT_TLX_XLD   = 8'h30,
                REG_DEBUG_OFFSET_ADDR_CNT_TLX_XLR   = 8'h38,
                REG_DEBUG_OFFSET_ADDR_CNT_AXI_CMD   = 8'h40,
                REG_DEBUG_OFFSET_ADDR_CNT_AXI_RSP   = 8'h48,
                REG_DEBUG_OFFSET_ADDR_BUF_CNT       = 8'h50,
                REG_DEBUG_OFFSET_ADDR_TRAFFIC_IDLE  = 8'h58,
                REG_DEBUG_OFFSET_ADDR_TLX_IDLE_LIM  = 8'h60,
                REG_DEBUG_OFFSET_ADDR_AXI_IDLE_LIM  = 8'h68,

           REG_FIR_BASE_ADDR    = 13'h01C0,
                REG_SNAP_OFFSET_ADDR_FIFO_OVFL      = 8'h0 ,
                REG_SNAP_OFFSET_ADDR_TLX_INTRFC     = 8'h8 ;




 wire data_width_incompatible = (mmio_rd || mmio_wr) && ((mmio_addr[ACTION_ACCESS_BIT] && mmio_dw) || (~mmio_addr[ACTION_ACCESS_BIT] && ~mmio_dw));


 wire action_access = mmio_addr[ACTION_ACCESS_BIT];
 wire snap_access = ~mmio_addr[ACTION_ACCESS_BIT];


 wire[SNAP_BASE_START_BIT   - SNAP_BASE_END_BIT   : 0] snap_base_addr;
 wire[SNAP_OFFSET_START_BIT - SNAP_OFFSET_END_BIT : 0] snap_offset_addr;
 assign snap_base_addr   = mmio_addr[SNAP_BASE_START_BIT  : SNAP_BASE_END_BIT];
 assign snap_offset_addr = mmio_addr[SNAP_OFFSET_START_BIT: SNAP_OFFSET_END_BIT];


 reg waddr_decode_error, raddr_decode_error;
 reg snap_wr_ack, snap_rd_ack;


 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     begin
       lcl_wr <= 1'b0;
       lcl_rd <= 1'b0;
     end
   else if(action_access)
     begin
       lcl_wr <= mmio_wr;
       lcl_rd <= mmio_rd;
     end


 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     lcl_addr <= 32'd0;
   else
     lcl_addr <= {1'b0,mmio_addr[30:0]};


 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     lcl_din <= 32'd0;
   else
     lcl_din <= mmio_addr[2]? mmio_din[63:32] : mmio_din[31:0];


 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     mmio_failed <= 1'b0;
   else
     mmio_failed <= (data_width_incompatible )                        ||
                    ((lcl_ack || lcl_dv) && (lcl_rsp == 1'b0))        ||
                    (snap_wr_ack && waddr_decode_error)               ||
                    (snap_rd_ack && raddr_decode_error);


 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     mmio_done <= 1'b0;
   else
     mmio_done <= ((lcl_ack || lcl_dv) && (lcl_rsp == 1'b1)) ||
                  (snap_wr_ack && ~waddr_decode_error)       ||
                  (snap_rd_ack && ~raddr_decode_error);



 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     begin

       REG_implementation_vertion  <= 64'd0;
       REG_build_date              <= 64'd0;
       REG_status                  <= 64'd0;
       REG_capability              <= 64'd0;
       REG_freeruntime             <= 64'd0;
       REG_usercode                <= 64'd0;


       REG_debug_tlx_cnt_cmd       <= 64'd0; 
       REG_debug_tlx_cnt_rsp       <= 64'd0;
       REG_debug_tlx_cnt_retry     <= 64'd0;
       REG_debug_tlx_cnt_fail      <= 64'd0;
       REG_debug_tlx_cnt_xlt_pd    <= 64'd0;
       REG_debug_tlx_cnt_xlt_done  <= 64'd0;
       REG_debug_tlx_cnt_xlt_retry <= 64'd0;
       REG_debug_axi_cnt_cmd       <= 64'd0;
       REG_debug_axi_cnt_rsp       <= 64'd0;
       REG_debug_buf_cnt           <= 64'd0;
       REG_debug_traffic_idle      <= 64'd0;


       REG_fir_fifo_overflow       <= 64'd0;
       REG_fir_tlx_interface       <= 64'd0;
     end
   else
     begin

       REG_implementation_vertion  <= `IMP_VERSION_DAT;
       REG_build_date              <= `BUILD_DATE_DAT;
       REG_status                  <= {60'd0, snap_fatal_error, snap_axi_busy, snap_tlx_busy, snap_idle};
       REG_capability [39:36]      <= `DMA_XFER_SIZE;
       REG_capability [35:32]      <= `DMA_ALIGNMENT;
       REG_capability [31:16]      <= `SDRAM_SIZE;
       REG_capability [8]          <= NVME_ENABLED;
       REG_capability [7:0]        <= `CARD_TYPE;
       REG_freeruntime             <= REG_freeruntime+1;
       REG_usercode                <= `USERCODE;




       REG_debug_tlx_cnt_cmd       <= debug_tlx_cnt_cmd      ; 
       REG_debug_tlx_cnt_rsp       <= debug_tlx_cnt_rsp      ;
       REG_debug_tlx_cnt_retry     <= debug_tlx_cnt_retry    ;
       REG_debug_tlx_cnt_fail      <= debug_tlx_cnt_fail     ;
       REG_debug_tlx_cnt_xlt_pd    <= debug_tlx_cnt_xlt_pd   ;
       REG_debug_tlx_cnt_xlt_done  <= debug_tlx_cnt_xlt_done ;
       REG_debug_tlx_cnt_xlt_retry <= debug_tlx_cnt_xlt_retry;
       REG_debug_axi_cnt_cmd       <= debug_axi_cnt_cmd      ;
       REG_debug_axi_cnt_rsp       <= debug_axi_cnt_rsp      ;
       REG_debug_buf_cnt           <= debug_buf_cnt          ;
       REG_debug_traffic_idle      <= debug_traffic_idle     ;


       REG_fir_fifo_overflow       <= fir_fifo_overflow      ;
       REG_fir_tlx_interface       <= fir_tlx_interface      ;
     end



 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     begin
       REG_command            <= 64'd0;
       REG_debug_clear        <= 64'd0;
       REG_debug_tlx_idle_lim <= 64'd0;
       REG_debug_axi_idle_lim <= 64'd0;

       waddr_decode_error <= 1'b0;
     end

   else if(snap_access && mmio_wr)
     case(snap_base_addr)

       REG_SNAP_BASE_ADDR :
          case(snap_offset_addr)
            REG_SNAP_OFFSET_ADDR_SCR           : REG_command <= mmio_din;
            default                            : waddr_decode_error <= 1'b1;
          endcase

       REG_DEBUG_BASE_ADDR :
          case(snap_offset_addr)
            REG_DEBUG_OFFSET_ADDR_DBG_CLR      : REG_debug_clear        <= mmio_din;
            REG_DEBUG_OFFSET_ADDR_TLX_IDLE_LIM : REG_debug_tlx_idle_lim <= mmio_din;
            REG_DEBUG_OFFSET_ADDR_AXI_IDLE_LIM : REG_debug_axi_idle_lim <= mmio_din;
            default                            : waddr_decode_error <= 1'b1;
          endcase

       default                                 : waddr_decode_error <= 1'b1;
     endcase
   else
     begin
       REG_debug_clear <= 64'd0;
       REG_command     <= 64'd0;

       waddr_decode_error <= 1'b0;
     end

 always@(posedge clk)
   begin
   end



 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     begin
       mmio_dout <= 64'd0;
       raddr_decode_error <= 1'b0;
     end


   else if(lcl_dv)
     begin
       mmio_dout <= mmio_addr[2]? {lcl_dout, 32'd0} : {32'd0, lcl_dout};
       raddr_decode_error <= 1'b0;
     end


   else if (snap_access) begin
     case(snap_base_addr)

       REG_SNAP_BASE_ADDR :
          case(snap_offset_addr)
            REG_SNAP_OFFSET_ADDR_IVR             : mmio_dout <= REG_implementation_vertion;
            REG_SNAP_OFFSET_ADDR_BDR             : mmio_dout <= REG_build_date            ;
            REG_SNAP_OFFSET_ADDR_SSR             : mmio_dout <= REG_status                ;
            REG_SNAP_OFFSET_ADDR_CAP             : mmio_dout <= REG_capability            ;
            REG_SNAP_OFFSET_ADDR_FRT             : mmio_dout <= REG_freeruntime           ;
            REG_SNAP_OFFSET_ADDR_USR             : mmio_dout <= REG_usercode              ;
            default                              : raddr_decode_error <= 1'b1;
          endcase

       REG_DEBUG_BASE_ADDR :
          case(snap_offset_addr)
            REG_DEBUG_OFFSET_ADDR_CNT_TLX_CMD   : mmio_dout <= REG_debug_tlx_cnt_cmd      ;
            REG_DEBUG_OFFSET_ADDR_CNT_TLX_RSP   : mmio_dout <= REG_debug_tlx_cnt_rsp      ;
            REG_DEBUG_OFFSET_ADDR_CNT_TLX_RTY   : mmio_dout <= REG_debug_tlx_cnt_retry    ;
            REG_DEBUG_OFFSET_ADDR_CNT_TLX_FAIL  : mmio_dout <= REG_debug_tlx_cnt_fail     ;
            REG_DEBUG_OFFSET_ADDR_CNT_TLX_XLP   : mmio_dout <= REG_debug_tlx_cnt_xlt_pd   ;
            REG_DEBUG_OFFSET_ADDR_CNT_TLX_XLD   : mmio_dout <= REG_debug_tlx_cnt_xlt_done ;
            REG_DEBUG_OFFSET_ADDR_CNT_TLX_XLR   : mmio_dout <= REG_debug_tlx_cnt_xlt_retry;
            REG_DEBUG_OFFSET_ADDR_CNT_AXI_CMD   : mmio_dout <= REG_debug_axi_cnt_cmd      ;
            REG_DEBUG_OFFSET_ADDR_CNT_AXI_RSP   : mmio_dout <= REG_debug_axi_cnt_rsp      ;
            REG_DEBUG_OFFSET_ADDR_BUF_CNT       : mmio_dout <= REG_debug_buf_cnt          ;
            REG_DEBUG_OFFSET_ADDR_TRAFFIC_IDLE  : mmio_dout <= REG_debug_traffic_idle     ;
            REG_DEBUG_OFFSET_ADDR_TLX_IDLE_LIM  : mmio_dout <= REG_debug_tlx_idle_lim     ;
            REG_DEBUG_OFFSET_ADDR_AXI_IDLE_LIM  : mmio_dout <= REG_debug_axi_idle_lim     ;
            default                             : raddr_decode_error <= 1'b1;
          endcase

       REG_FIR_BASE_ADDR :
          case(snap_offset_addr)
            REG_SNAP_OFFSET_ADDR_FIFO_OVFL      : mmio_dout <= REG_fir_fifo_overflow       ;
            REG_SNAP_OFFSET_ADDR_TLX_INTRFC     : mmio_dout <= REG_fir_tlx_interface       ;
            default                             : raddr_decode_error <= 1'b1;
          endcase

       default                                  : raddr_decode_error <= 1'b1;
     endcase
   end


 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     begin
       snap_wr_ack <= 1'b0;
       snap_rd_ack <= 1'b0;
     end
   else
     begin
       snap_wr_ack <= mmio_wr && snap_access;
       snap_rd_ack <= mmio_rd && snap_access;
     end


 reg [3:0] snap_reset_cnt;
 reg [3:0] action_reset_cnt;
 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     soft_reset_brdg_odma <= 1'b0;
   else if(&snap_reset_cnt)
     soft_reset_brdg_odma <= 1'b0;
   else if(REG_command[0])
     soft_reset_brdg_odma <= 1'b1;

 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     snap_reset_cnt <= 4'd0;
   else if(soft_reset_brdg_odma)
     snap_reset_cnt <= snap_reset_cnt + 4'd1;

 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     soft_reset_action <= 1'b0;
   else if(&action_reset_cnt)
     soft_reset_action <= 1'b0;
   else if(REG_command[0])
     soft_reset_action <= 1'b1;

 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     action_reset_cnt <= 4'd0;
   else if(soft_reset_action)
     action_reset_cnt <= action_reset_cnt + 4'd1;

 assign debug_cnt_clear    = REG_debug_clear[0];
 assign debug_tlx_idle_lim = REG_debug_tlx_idle_lim;
 assign debug_axi_idle_lim = REG_debug_axi_idle_lim;


 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     begin
       snap_idle        <= 1'b0;
       snap_tlx_busy    <= 1'b0;
       snap_axi_busy    <= 1'b0;
       snap_fatal_error <= 1'b0;
     end
   else
     begin
       snap_idle        <= (debug_buf_cnt == 64'd0);
       snap_tlx_busy    <= (debug_tlx_cnt_cmd != debug_tlx_cnt_rsp);
       snap_axi_busy    <= (debug_axi_cnt_cmd != debug_axi_cnt_rsp);
       snap_fatal_error <= |{fir_fifo_overflow, fir_tlx_interface};
     end


endmodule
module mmio (
             input                clk                        ,
             input                rst_n                      ,


             output               debug_cnt_clear            ,
             input         [63:0] debug_tlx_cnt_cmd          ,
             input         [63:0] debug_tlx_cnt_rsp          ,
             input         [63:0] debug_tlx_cnt_retry        ,
             input         [63:0] debug_tlx_cnt_fail         ,
             input         [63:0] debug_tlx_cnt_xlt_pd       ,
             input         [63:0] debug_tlx_cnt_xlt_done     ,
             input         [63:0] debug_tlx_cnt_xlt_retry    ,
             input         [63:0] debug_axi_cnt_cmd          , 
             input         [63:0] debug_axi_cnt_rsp          , 
             input         [63:0] debug_buf_cnt              , 
             input         [63:0] debug_traffic_idle         ,
             output        [63:0] debug_tlx_idle_lim         ,
             output        [63:0] debug_axi_idle_lim         ,


             input         [63:0] fir_fifo_overflow          ,
             input         [63:0] fir_tlx_interface          ,


             output reg           soft_reset_brdg_odma       ,
             output reg           soft_reset_action          ,


             input                mmio_wr                    ,
             input                mmio_rd                    ,
             input                mmio_dw                    ,
             input         [31:0] mmio_addr                  ,
             input         [63:0] mmio_din                   ,
             output reg    [63:0] mmio_dout                  ,
             output reg           mmio_done                  ,
             output reg           mmio_failed                ,


             output reg           lcl_wr                     ,
             output reg           lcl_rd                     ,
             output reg    [31:0] lcl_addr                   ,
             output reg    [31:0] lcl_din                    ,
             input                lcl_ack                    ,
             input                lcl_rsp                    ,
             input         [31:0] lcl_dout                   ,
             input                lcl_dv
             );





 reg snap_idle       ;
 reg snap_tlx_busy   ;
 reg snap_axi_busy   ;
 reg snap_fatal_error;

`ifdef ENABLE_NVME
 parameter  NVME_ENABLED    = 1'b1;
`else
 parameter  NVME_ENABLED    = 1'b0;
`endif








 parameter GLOBAL_PP_MMIO_BIT    = 31;
 parameter ACTION_ACCESS_BIT     = 31;





 parameter PASID_START_BIT       = 30;
 parameter PASID_END_BIT         = 22;



 parameter SNAP_BASE_START_BIT   = 21;
 parameter SNAP_BASE_END_BIT     = 8;
 parameter SNAP_OFFSET_START_BIT = 7;
 parameter SNAP_OFFSET_END_BIT   = 0;







 reg [63:00] REG_implementation_vertion;
 reg [63:00] REG_build_date            ;
 reg [63:00] REG_command               ;
 reg [63:00] REG_status                ;
 reg [63:00] REG_capability            ;
 reg [63:00] REG_freeruntime           ;
 reg [63:00] REG_usercode              ;


 reg [63:00] REG_debug_clear            ;
 reg [63:00] REG_debug_tlx_cnt_cmd      ;
 reg [63:00] REG_debug_tlx_cnt_rsp      ;
 reg [63:00] REG_debug_tlx_cnt_retry    ;
 reg [63:00] REG_debug_tlx_cnt_fail     ;
 reg [63:00] REG_debug_tlx_cnt_xlt_pd   ;
 reg [63:00] REG_debug_tlx_cnt_xlt_done ;
 reg [63:00] REG_debug_tlx_cnt_xlt_retry;
 reg [63:00] REG_debug_axi_cnt_cmd      ;
 reg [63:00] REG_debug_axi_cnt_rsp      ;
 reg [63:00] REG_debug_buf_cnt          ;
 reg [63:00] REG_debug_traffic_idle     ;
 reg [63:00] REG_debug_tlx_idle_lim     ;
 reg [63:00] REG_debug_axi_idle_lim     ;


 reg [63:00] REG_fir_fifo_overflow      ;
 reg [63:00] REG_fir_tlx_interface      ;





 parameter REG_SNAP_BASE_ADDR   = 13'h0000,
                REG_SNAP_OFFSET_ADDR_IVR            = 8'h0 ,
                REG_SNAP_OFFSET_ADDR_BDR            = 8'h8 ,
                REG_SNAP_OFFSET_ADDR_SCR            = 8'h10,
                REG_SNAP_OFFSET_ADDR_SSR            = 8'h18,
                REG_SNAP_OFFSET_ADDR_CAP            = 8'h30,
                REG_SNAP_OFFSET_ADDR_FRT            = 8'h40,
                REG_SNAP_OFFSET_ADDR_USR            = 8'h50,

           REG_DEBUG_BASE_ADDR  = 13'h01A0,
                REG_DEBUG_OFFSET_ADDR_DBG_CLR       = 8'h00,
                REG_DEBUG_OFFSET_ADDR_CNT_TLX_CMD   = 8'h08,
                REG_DEBUG_OFFSET_ADDR_CNT_TLX_RSP   = 8'h10,
                REG_DEBUG_OFFSET_ADDR_CNT_TLX_RTY   = 8'h18,
                REG_DEBUG_OFFSET_ADDR_CNT_TLX_FAIL  = 8'h20,
                REG_DEBUG_OFFSET_ADDR_CNT_TLX_XLP   = 8'h28,
                REG_DEBUG_OFFSET_ADDR_CNT_TLX_XLD   = 8'h30,
                REG_DEBUG_OFFSET_ADDR_CNT_TLX_XLR   = 8'h38,
                REG_DEBUG_OFFSET_ADDR_CNT_AXI_CMD   = 8'h40,
                REG_DEBUG_OFFSET_ADDR_CNT_AXI_RSP   = 8'h48,
                REG_DEBUG_OFFSET_ADDR_BUF_CNT       = 8'h50,
                REG_DEBUG_OFFSET_ADDR_TRAFFIC_IDLE  = 8'h58,
                REG_DEBUG_OFFSET_ADDR_TLX_IDLE_LIM  = 8'h60,
                REG_DEBUG_OFFSET_ADDR_AXI_IDLE_LIM  = 8'h68,

           REG_FIR_BASE_ADDR    = 13'h01C0,
                REG_SNAP_OFFSET_ADDR_FIFO_OVFL      = 8'h0 ,
                REG_SNAP_OFFSET_ADDR_TLX_INTRFC     = 8'h8 ;




 wire data_width_incompatible = (mmio_rd || mmio_wr) && ((mmio_addr[ACTION_ACCESS_BIT] && mmio_dw) || (~mmio_addr[ACTION_ACCESS_BIT] && ~mmio_dw));


 wire action_access = mmio_addr[ACTION_ACCESS_BIT];
 wire snap_access = ~mmio_addr[ACTION_ACCESS_BIT];


 wire[SNAP_BASE_START_BIT   - SNAP_BASE_END_BIT   : 0] snap_base_addr;
 wire[SNAP_OFFSET_START_BIT - SNAP_OFFSET_END_BIT : 0] snap_offset_addr;
 assign snap_base_addr   = mmio_addr[SNAP_BASE_START_BIT  : SNAP_BASE_END_BIT];
 assign snap_offset_addr = mmio_addr[SNAP_OFFSET_START_BIT: SNAP_OFFSET_END_BIT];


 reg waddr_decode_error, raddr_decode_error;
 reg snap_wr_ack, snap_rd_ack;


 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     begin
       lcl_wr <= 1'b0;
       lcl_rd <= 1'b0;
     end
   else if(action_access)
     begin
       lcl_wr <= mmio_wr;
       lcl_rd <= mmio_rd;
     end


 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     lcl_addr <= 32'd0;
   else
     lcl_addr <= {1'b0,mmio_addr[30:0]};


 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     lcl_din <= 32'd0;
   else
     lcl_din <= mmio_addr[2]? mmio_din[63:32] : mmio_din[31:0];


 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     mmio_failed <= 1'b0;
   else
     mmio_failed <= (data_width_incompatible )                        ||
                    ((lcl_ack || lcl_dv) && (lcl_rsp == 1'b0))        ||
                    (snap_wr_ack && waddr_decode_error)               ||
                    (snap_rd_ack && raddr_decode_error);


 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     mmio_done <= 1'b0;
   else
     mmio_done <= ((lcl_ack || lcl_dv) && (lcl_rsp == 1'b1)) ||
                  (snap_wr_ack && ~waddr_decode_error)       ||
                  (snap_rd_ack && ~raddr_decode_error);



 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     begin

       REG_implementation_vertion  <= 64'd0;
       REG_build_date              <= 64'd0;
       REG_status                  <= 64'd0;
       REG_capability              <= 64'd0;
       REG_freeruntime             <= 64'd0;
       REG_usercode                <= 64'd0;


       REG_debug_tlx_cnt_cmd       <= 64'd0; 
       REG_debug_tlx_cnt_rsp       <= 64'd0;
       REG_debug_tlx_cnt_retry     <= 64'd0;
       REG_debug_tlx_cnt_fail      <= 64'd0;
       REG_debug_tlx_cnt_xlt_pd    <= 64'd0;
       REG_debug_tlx_cnt_xlt_done  <= 64'd0;
       REG_debug_tlx_cnt_xlt_retry <= 64'd0;
       REG_debug_axi_cnt_cmd       <= 64'd0;
       REG_debug_axi_cnt_rsp       <= 64'd0;
       REG_debug_buf_cnt           <= 64'd0;
       REG_debug_traffic_idle      <= 64'd0;


       REG_fir_fifo_overflow       <= 64'd0;
       REG_fir_tlx_interface       <= 64'd0;
     end
   else
     begin

       REG_implementation_vertion  <= `IMP_VERSION_DAT;
       REG_build_date              <= `BUILD_DATE_DAT;
       REG_status                  <= {60'd0, snap_fatal_error, snap_axi_busy, snap_tlx_busy, snap_idle};
       REG_capability [39:36]      <= `DMA_XFER_SIZE;
       REG_capability [35:32]      <= `DMA_ALIGNMENT;
       REG_capability [31:16]      <= `SDRAM_SIZE;
       REG_capability [8]          <= NVME_ENABLED;
       REG_capability [7:0]        <= `CARD_TYPE;
       REG_freeruntime             <= REG_freeruntime+1;
       REG_usercode                <= `USERCODE;




       REG_debug_tlx_cnt_cmd       <= debug_tlx_cnt_cmd      ; 
       REG_debug_tlx_cnt_rsp       <= debug_tlx_cnt_rsp      ;
       REG_debug_tlx_cnt_retry     <= debug_tlx_cnt_retry    ;
       REG_debug_tlx_cnt_fail      <= debug_tlx_cnt_fail     ;
       REG_debug_tlx_cnt_xlt_pd    <= debug_tlx_cnt_xlt_pd   ;
       REG_debug_tlx_cnt_xlt_done  <= debug_tlx_cnt_xlt_done ;
       REG_debug_tlx_cnt_xlt_retry <= debug_tlx_cnt_xlt_retry;
       REG_debug_axi_cnt_cmd       <= debug_axi_cnt_cmd      ;
       REG_debug_axi_cnt_rsp       <= debug_axi_cnt_rsp      ;
       REG_debug_buf_cnt           <= debug_buf_cnt          ;
       REG_debug_traffic_idle      <= debug_traffic_idle     ;


       REG_fir_fifo_overflow       <= fir_fifo_overflow      ;
       REG_fir_tlx_interface       <= fir_tlx_interface      ;
     end



 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     begin
       REG_command            <= 64'd0;
       REG_debug_clear        <= 64'd0;
       REG_debug_tlx_idle_lim <= 64'd0;
       REG_debug_axi_idle_lim <= 64'd0;

       waddr_decode_error <= 1'b0;
     end

   else if(snap_access && mmio_wr)
     case(snap_base_addr)

       REG_SNAP_BASE_ADDR :
          case(snap_offset_addr)
            REG_SNAP_OFFSET_ADDR_SCR           : REG_command <= mmio_din;
            default                            : waddr_decode_error <= 1'b1;
          endcase

       REG_DEBUG_BASE_ADDR :
          case(snap_offset_addr)
            REG_DEBUG_OFFSET_ADDR_DBG_CLR      : REG_debug_clear        <= mmio_din;
            REG_DEBUG_OFFSET_ADDR_TLX_IDLE_LIM : REG_debug_tlx_idle_lim <= mmio_din;
            REG_DEBUG_OFFSET_ADDR_AXI_IDLE_LIM : REG_debug_axi_idle_lim <= mmio_din;
            default                            : waddr_decode_error <= 1'b1;
          endcase

       default                                 : waddr_decode_error <= 1'b1;
     endcase
   else
     begin
       REG_debug_clear <= 64'd0;
       REG_command     <= 64'd0;

       waddr_decode_error <= 1'b0;
     end

 always@(posedge clk)
   begin
   end



 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     begin
       mmio_dout <= 64'd0;
       raddr_decode_error <= 1'b0;
     end


   else if(lcl_dv)
     begin
       mmio_dout <= mmio_addr[2]? {lcl_dout, 32'd0} : {32'd0, lcl_dout};
       raddr_decode_error <= 1'b0;
     end


   else if (snap_access) begin
     case(snap_base_addr)

       REG_SNAP_BASE_ADDR :
          case(snap_offset_addr)
            REG_SNAP_OFFSET_ADDR_IVR             : mmio_dout <= REG_implementation_vertion;
            REG_SNAP_OFFSET_ADDR_BDR             : mmio_dout <= REG_build_date            ;
            REG_SNAP_OFFSET_ADDR_SSR             : mmio_dout <= REG_status                ;
            REG_SNAP_OFFSET_ADDR_CAP             : mmio_dout <= REG_capability            ;
            REG_SNAP_OFFSET_ADDR_FRT             : mmio_dout <= REG_freeruntime           ;
            REG_SNAP_OFFSET_ADDR_USR             : mmio_dout <= REG_usercode              ;
            default                              : raddr_decode_error <= 1'b1;
          endcase

       REG_DEBUG_BASE_ADDR :
          case(snap_offset_addr)
            REG_DEBUG_OFFSET_ADDR_CNT_TLX_CMD   : mmio_dout <= REG_debug_tlx_cnt_cmd      ;
            REG_DEBUG_OFFSET_ADDR_CNT_TLX_RSP   : mmio_dout <= REG_debug_tlx_cnt_rsp      ;
            REG_DEBUG_OFFSET_ADDR_CNT_TLX_RTY   : mmio_dout <= REG_debug_tlx_cnt_retry    ;
            REG_DEBUG_OFFSET_ADDR_CNT_TLX_FAIL  : mmio_dout <= REG_debug_tlx_cnt_fail     ;
            REG_DEBUG_OFFSET_ADDR_CNT_TLX_XLP   : mmio_dout <= REG_debug_tlx_cnt_xlt_pd   ;
            REG_DEBUG_OFFSET_ADDR_CNT_TLX_XLD   : mmio_dout <= REG_debug_tlx_cnt_xlt_done ;
            REG_DEBUG_OFFSET_ADDR_CNT_TLX_XLR   : mmio_dout <= REG_debug_tlx_cnt_xlt_retry;
            REG_DEBUG_OFFSET_ADDR_CNT_AXI_CMD   : mmio_dout <= REG_debug_axi_cnt_cmd      ;
            REG_DEBUG_OFFSET_ADDR_CNT_AXI_RSP   : mmio_dout <= REG_debug_axi_cnt_rsp      ;
            REG_DEBUG_OFFSET_ADDR_BUF_CNT       : mmio_dout <= REG_debug_buf_cnt          ;
            REG_DEBUG_OFFSET_ADDR_TRAFFIC_IDLE  : mmio_dout <= REG_debug_traffic_idle     ;
            REG_DEBUG_OFFSET_ADDR_TLX_IDLE_LIM  : mmio_dout <= REG_debug_tlx_idle_lim     ;
            REG_DEBUG_OFFSET_ADDR_AXI_IDLE_LIM  : mmio_dout <= REG_debug_axi_idle_lim     ;
            default                             : raddr_decode_error <= 1'b1;
          endcase

       REG_FIR_BASE_ADDR :
          case(snap_offset_addr)
            REG_SNAP_OFFSET_ADDR_FIFO_OVFL      : mmio_dout <= REG_fir_fifo_overflow       ;
            REG_SNAP_OFFSET_ADDR_TLX_INTRFC     : mmio_dout <= REG_fir_tlx_interface       ;
            default                             : raddr_decode_error <= 1'b1;
          endcase

       default                                  : raddr_decode_error <= 1'b1;
     endcase
   end


 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     begin
       snap_wr_ack <= 1'b0;
       snap_rd_ack <= 1'b0;
     end
   else
     begin
       snap_wr_ack <= mmio_wr && snap_access;
       snap_rd_ack <= mmio_rd && snap_access;
     end


 reg [3:0] snap_reset_cnt;
 reg [3:0] action_reset_cnt;
 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     soft_reset_brdg_odma <= 1'b0;
   else if(&snap_reset_cnt)
     soft_reset_brdg_odma <= 1'b0;
   else if(REG_command[0])
     soft_reset_brdg_odma <= 1'b1;

 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     snap_reset_cnt <= 4'd0;
   else if(soft_reset_brdg_odma)
     snap_reset_cnt <= snap_reset_cnt + 4'd1;

 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     soft_reset_action <= 1'b0;
   else if(&action_reset_cnt)
     soft_reset_action <= 1'b0;
   else if(REG_command[0])
     soft_reset_action <= 1'b1;

 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     action_reset_cnt <= 4'd0;
   else if(soft_reset_action)
     action_reset_cnt <= action_reset_cnt + 4'd1;

 assign debug_cnt_clear    = REG_debug_clear[0];
 assign debug_tlx_idle_lim = REG_debug_tlx_idle_lim;
 assign debug_axi_idle_lim = REG_debug_axi_idle_lim;


 always@(posedge clk or negedge rst_n)
   if(~rst_n)
     begin
       snap_idle        <= 1'b0;
       snap_tlx_busy    <= 1'b0;
       snap_axi_busy    <= 1'b0;
       snap_fatal_error <= 1'b0;
     end
   else
     begin
       snap_idle        <= (debug_buf_cnt == 64'd0);
       snap_tlx_busy    <= (debug_tlx_cnt_cmd != debug_tlx_cnt_rsp);
       snap_axi_busy    <= (debug_axi_cnt_cmd != debug_axi_cnt_rsp);
       snap_fatal_error <= |{fir_fifo_overflow, fir_tlx_interface};
     end


endmodule