data/full_repos/permissive/514992586/1_Verilog_language/More_Verilog_Features/41_Popcount255.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/514992586/1_Verilog_language/More_Verilog_Features/41_Popcount255.v:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out'\n                                                                                                                    : ... In instance top_module\n        out = 0;\n        ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/514992586/1_Verilog_language/More_Verilog_Features/41_Popcount255.v:10: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out'\n                                                                                                                     : ... In instance top_module\n                out = out + 1;\n                ^~~\n%Error-PROCASSWIRE: data/full_repos/permissive/514992586/1_Verilog_language/More_Verilog_Features/41_Popcount255.v:12: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'out'\n                                                                                                                     : ... In instance top_module\n                out = out + 0;\n                ^~~\n%Error: Exiting due to 3 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module top_module( 
    input [254:0] in,
    output [7:0] out );

    always @(*) begin
        integer i;
        out = 0;
        for (i = 0; i < 255; i++) begin
            if (in[i] == 1)
                out = out + 1;
            else
                out = out + 0;
        end
    end
endmodule
module top_module( 
    input [254:0] in,
    output [7:0] out );


    always @(*) begin
        integer i;
        out = 0;
        for (i = 0; i < 255; i++) begin
            if (in[i] == 1)
                out = out + 1;
            else
                out = out + 0;
        end
    end
endmodule