data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v
1: b'%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:40: Cannot find include file: openGFX430_defines.v\n`include "openGFX430_defines.v" \n         ^~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/531094269/verilog/rtl/src,data/full_repos/permissive/531094269/openGFX430_defines.v\n             data/full_repos/permissive/531094269/verilog/rtl/src,data/full_repos/permissive/531094269/openGFX430_defines.v.v\n             data/full_repos/permissive/531094269/verilog/rtl/src,data/full_repos/permissive/531094269/openGFX430_defines.v.sv\n             openGFX430_defines.v\n             openGFX430_defines.v.v\n             openGFX430_defines.v.sv\n             obj_dir/openGFX430_defines.v\n             obj_dir/openGFX430_defines.v.v\n             obj_dir/openGFX430_defines.v.sv\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:441: Cannot find include file: openGFX430_undefines.v\n`include "openGFX430_undefines.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:97: Define or directive not defined: \'`APIX_MSB\'\noutput [`APIX_MSB:0] vid_ram_addr_nxt_o;        \n        ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:97: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\noutput [`APIX_MSB:0] vid_ram_addr_nxt_o;        \n                 ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:113: Define or directive not defined: \'`LPIX_MSB\'\ninput  [`LPIX_MSB:0] display_width_i;           \n        ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:113: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\ninput  [`LPIX_MSB:0] display_width_i;           \n                 ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:121: Define or directive not defined: \'`APIX_MSB\'\ninput  [`APIX_MSB:0] vid_ram_base_addr_i;       \n        ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:121: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\ninput  [`APIX_MSB:0] vid_ram_base_addr_i;       \n                 ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:180: Define or directive not defined: \'`LPIX_MSB\'\nreg  [`LPIX_MSB:0] vid_ram_width;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:180: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nreg  [`LPIX_MSB:0] vid_ram_width;\n               ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:183: Define or directive not defined: \'`LPIX_MSB\'\nwire [`LPIX_MSB:0] vid_ram_width_nxt  = (|per_din_i[`LPIX_MSB:0]) ? per_din_i[`LPIX_MSB:0] : {{`LPIX_MSB{1\'b0}}, 1\'b1};\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:183: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire [`LPIX_MSB:0] vid_ram_width_nxt  = (|per_din_i[`LPIX_MSB:0]) ? per_din_i[`LPIX_MSB:0] : {{`LPIX_MSB{1\'b0}}, 1\'b1};\n               ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:183: Define or directive not defined: \'`LPIX_MSB\'\nwire [`LPIX_MSB:0] vid_ram_width_nxt  = (|per_din_i[`LPIX_MSB:0]) ? per_din_i[`LPIX_MSB:0] : {{`LPIX_MSB{1\'b0}}, 1\'b1};\n                                                    ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:183: Define or directive not defined: \'`LPIX_MSB\'\nwire [`LPIX_MSB:0] vid_ram_width_nxt  = (|per_din_i[`LPIX_MSB:0]) ? per_din_i[`LPIX_MSB:0] : {{`LPIX_MSB{1\'b0}}, 1\'b1};\n                                                                              ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:183: Define or directive not defined: \'`LPIX_MSB\'\nwire [`LPIX_MSB:0] vid_ram_width_nxt  = (|per_din_i[`LPIX_MSB:0]) ? per_din_i[`LPIX_MSB:0] : {{`LPIX_MSB{1\'b0}}, 1\'b1};\n                                                                                               ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:186: Define or directive not defined: \'`LPIX_MSB\'\n  if (puc_rst)                 vid_ram_width   <=  {{`LPIX_MSB{1\'b0}}, 1\'b1};\n                                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:189: Define or directive not defined: \'`LPIX_MSB\'\nwire [16:0] vid_ram_width_tmp = {{16-`LPIX_MSB{1\'b0}}, vid_ram_width};\n                                     ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:196: Define or directive not defined: \'`APIX_MSB\'\nwire   [`APIX_MSB:0] vid_ram_addr;\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:196: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire   [`APIX_MSB:0] vid_ram_addr;\n                 ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:197: Define or directive not defined: \'`APIX_MSB\'\nwire   [`APIX_MSB:0] vid_ram_addr_inc;\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:197: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire   [`APIX_MSB:0] vid_ram_addr_inc;\n                 ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:216: Define or directive not defined: \'`APIX_LO_MSB\'\nreg [`APIX_LO_MSB:0] vid_ram_addr_lo;\n     ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:216: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nreg [`APIX_LO_MSB:0] vid_ram_addr_lo;\n                 ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:219: Define or directive not defined: \'`APIX_LO_MSB\'\n  if (puc_rst)                   vid_ram_addr_lo <=  {`APIX_LO_MSB+1{1\'b0}};\n                                                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:220: Define or directive not defined: \'`APIX_LO_MSB\'\n  else if (vid_ram_addr_lo_wr_i) vid_ram_addr_lo <=  per_din_i[`APIX_LO_MSB:0];\n                                                               ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:220: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n  else if (vid_ram_addr_lo_wr_i) vid_ram_addr_lo <=  per_din_i[`APIX_LO_MSB:0];\n                                                                           ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:221: Define or directive not defined: \'`APIX_LO_MSB\'\n  else if (vid_ram_addr_inc_wr)  vid_ram_addr_lo <=  vid_ram_addr_inc[`APIX_LO_MSB:0];\n                                                                      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:221: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n  else if (vid_ram_addr_inc_wr)  vid_ram_addr_lo <=  vid_ram_addr_inc[`APIX_LO_MSB:0];\n                                                                                  ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:227: Define or directive not defined: \'`APIX_LO_MSB\'\nassign      vid_ram_addr        = {vid_ram_addr_lo[`APIX_LO_MSB:0]};\n                                                   ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:227: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nassign      vid_ram_addr        = {vid_ram_addr_lo[`APIX_LO_MSB:0]};\n                                                               ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:228: Define or directive not defined: \'`APIX_LO_MSB\'\nwire [16:0] vid_ram_addr_lo_tmp = {{16-`APIX_LO_MSB{1\'b0}},vid_ram_addr_lo};\n                                       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:388: Define or directive not defined: \'`APIX_MSB\'\nwire [`APIX_MSB:0] vid_ram_addr_mux    = vid_ram_addr_hi_wr_i ? {per_din_i[`APIX_LO_MSB:0]}                     :\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:388: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire [`APIX_MSB:0] vid_ram_addr_mux    = vid_ram_addr_hi_wr_i ? {per_din_i[`APIX_LO_MSB:0]}                     :\n               ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:388: Define or directive not defined: \'`APIX_LO_MSB\'\nwire [`APIX_MSB:0] vid_ram_addr_mux    = vid_ram_addr_hi_wr_i ? {per_din_i[`APIX_LO_MSB:0]}                     :\n                                                                           ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:393: Define or directive not defined: \'`APIX_MSB\'\nwire [`APIX_MSB:0] vid_ram_addr_offset = vid_ram_base_addr_i + vid_ram_addr_mux;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:393: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire [`APIX_MSB:0] vid_ram_addr_offset = vid_ram_base_addr_i + vid_ram_addr_mux;\n               ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:399: Define or directive not defined: \'`APIX_MSB\'\nwire [`APIX_MSB:0] vid_ram_addr_nxt_o  = {`APIX_MSB+1{vid_ram_access_o}} & vid_ram_addr_offset;\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:399: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\nwire [`APIX_MSB:0] vid_ram_addr_nxt_o  = {`APIX_MSB+1{vid_ram_access_o}} & vid_ram_addr_offset;\n               ^\n%Error: data/full_repos/permissive/531094269/verilog/rtl/src/ogfx_reg_vram_if.v:399: Define or directive not defined: \'`APIX_MSB\'\nwire [`APIX_MSB:0] vid_ram_addr_nxt_o  = {`APIX_MSB+1{vid_ram_access_o}} & vid_ram_addr_offset;\n                                          ^~~~~~~~~\n%Error: Exiting due to 39 error(s)\n'
module  ogfx_reg_vram_if (


    vid_ram_cfg_o,
    vid_ram_width_o,
`ifdef VRAM_BIGGER_4_KW
    vid_ram_addr_hi_o,
`endif
    vid_ram_addr_lo_o,
    vid_ram_data_o,

    vid_ram_we_o,
    vid_ram_ce_o,
    vid_ram_din_o,
    vid_ram_addr_nxt_o,
    vid_ram_access_o,


    mclk,
    puc_rst,

    vid_ram_cfg_wr_i,
    vid_ram_width_wr_i,
    vid_ram_addr_hi_wr_i,
    vid_ram_addr_lo_wr_i,
    vid_ram_data_wr_i,
    vid_ram_data_rd_i,

    dbg_freeze_i,
    display_width_i,
    gfx_mode_1_bpp_i,
    gfx_mode_2_bpp_i,
    gfx_mode_4_bpp_i,
    gfx_mode_8_bpp_i,
    gfx_mode_16_bpp_i,

    per_din_i,
    vid_ram_base_addr_i,
    vid_ram_dout_i
);



output        [15:0] vid_ram_cfg_o;
output        [15:0] vid_ram_width_o;
`ifdef VRAM_BIGGER_4_KW
output        [15:0] vid_ram_addr_hi_o;
`endif
output        [15:0] vid_ram_addr_lo_o;
output        [15:0] vid_ram_data_o;

output               vid_ram_we_o;
output               vid_ram_ce_o;
output        [15:0] vid_ram_din_o;
output [`APIX_MSB:0] vid_ram_addr_nxt_o;
output               vid_ram_access_o;



input                mclk;
input                puc_rst;

input                vid_ram_cfg_wr_i;
input                vid_ram_width_wr_i;
input                vid_ram_addr_hi_wr_i;
input                vid_ram_addr_lo_wr_i;
input                vid_ram_data_wr_i;
input                vid_ram_data_rd_i;

input                dbg_freeze_i;
input  [`LPIX_MSB:0] display_width_i;
input                gfx_mode_1_bpp_i;
input                gfx_mode_2_bpp_i;
input                gfx_mode_4_bpp_i;
input                gfx_mode_8_bpp_i;
input                gfx_mode_16_bpp_i;

input         [15:0] per_din_i;
input  [`APIX_MSB:0] vid_ram_base_addr_i;
input         [15:0] vid_ram_dout_i;







function [15:0] one_hot16;
   input  [3:0] binary;
   begin
      one_hot16         = 16'h0000;
      one_hot16[binary] =  1'b1;
   end
endfunction










reg                vid_ram_rmw_mode;
reg                vid_ram_msk_mode;
reg                vid_ram_win_mode;
reg                vid_ram_win_x_swap;
reg                vid_ram_win_y_swap;
reg                vid_ram_win_cl_swap;

always @ (posedge mclk or posedge puc_rst)
  if (puc_rst)
    begin
       vid_ram_win_cl_swap  <=  1'b0;
       vid_ram_win_y_swap   <=  1'b0;
       vid_ram_win_x_swap   <=  1'b0;
       vid_ram_rmw_mode     <=  1'b0;
       vid_ram_msk_mode     <=  1'b0;
       vid_ram_win_mode     <=  1'b0;
    end
  else if (vid_ram_cfg_wr_i)
    begin
       vid_ram_win_cl_swap  <=  per_din_i[0];
       vid_ram_win_y_swap   <=  per_din_i[1];
       vid_ram_win_x_swap   <=  per_din_i[2];
       vid_ram_rmw_mode     <=  per_din_i[4];
       vid_ram_msk_mode     <=  per_din_i[5];
       vid_ram_win_mode     <=  per_din_i[6];
    end

assign vid_ram_cfg_o  = {8'h00, 1'b0,  vid_ram_win_mode,   vid_ram_msk_mode,   vid_ram_rmw_mode   ,
                                1'b0,  vid_ram_win_x_swap, vid_ram_win_y_swap, vid_ram_win_cl_swap};




reg  [`LPIX_MSB:0] vid_ram_width;


wire [`LPIX_MSB:0] vid_ram_width_nxt  = (|per_din_i[`LPIX_MSB:0]) ? per_din_i[`LPIX_MSB:0] : {{`LPIX_MSB{1'b0}}, 1'b1};

always @ (posedge mclk or posedge puc_rst)
  if (puc_rst)                 vid_ram_width   <=  {{`LPIX_MSB{1'b0}}, 1'b1};
  else if (vid_ram_width_wr_i) vid_ram_width   <=  vid_ram_width_nxt;

wire [16:0] vid_ram_width_tmp = {{16-`LPIX_MSB{1'b0}}, vid_ram_width};
assign      vid_ram_width_o   = vid_ram_width_tmp[15:0];





wire   [`APIX_MSB:0] vid_ram_addr;
wire   [`APIX_MSB:0] vid_ram_addr_inc;
wire                 vid_ram_addr_inc_wr;
reg                  vid_ram_addr_hi_wr_dly;

`ifdef VRAM_BIGGER_4_KW
reg [`APIX_HI_MSB:0] vid_ram_addr_hi;

always @ (posedge mclk or posedge puc_rst)
  if (puc_rst)                   vid_ram_addr_hi <=  {`APIX_HI_MSB+1{1'b0}};
  else if (vid_ram_addr_hi_wr_i) vid_ram_addr_hi <=  per_din_i[`APIX_HI_MSB:0];
  else if (vid_ram_addr_inc_wr)  vid_ram_addr_hi <=  vid_ram_addr_inc[`APIX_MSB:16];

wire [16:0] vid_ram_addr_hi_tmp = {{16-`APIX_HI_MSB{1'b0}},vid_ram_addr_hi};
assign      vid_ram_addr_hi_o   = vid_ram_addr_hi_tmp[15:0];
`endif




reg [`APIX_LO_MSB:0] vid_ram_addr_lo;

always @ (posedge mclk or posedge puc_rst)
  if (puc_rst)                   vid_ram_addr_lo <=  {`APIX_LO_MSB+1{1'b0}};
  else if (vid_ram_addr_lo_wr_i) vid_ram_addr_lo <=  per_din_i[`APIX_LO_MSB:0];
  else if (vid_ram_addr_inc_wr)  vid_ram_addr_lo <=  vid_ram_addr_inc[`APIX_LO_MSB:0];

`ifdef VRAM_BIGGER_4_KW
assign      vid_ram_addr        = {vid_ram_addr_hi[`APIX_HI_MSB:0], vid_ram_addr_lo};
assign      vid_ram_addr_lo_o   =  vid_ram_addr_lo;
`else
assign      vid_ram_addr        = {vid_ram_addr_lo[`APIX_LO_MSB:0]};
wire [16:0] vid_ram_addr_lo_tmp = {{16-`APIX_LO_MSB{1'b0}},vid_ram_addr_lo};
assign      vid_ram_addr_lo_o   = vid_ram_addr_lo_tmp[15:0];
`endif


ogfx_reg_vram_addr ogfx_reg_vram_addr_inst (


    .vid_ram_addr_nxt_o      ( vid_ram_addr_inc       ),


    .mclk                    ( mclk                   ),
    .puc_rst                 ( puc_rst                ),
    .display_width_i         ( display_width_i        ),
    .gfx_mode_1_bpp_i        ( gfx_mode_1_bpp_i       ),
    .gfx_mode_2_bpp_i        ( gfx_mode_2_bpp_i       ),
    .gfx_mode_4_bpp_i        ( gfx_mode_4_bpp_i       ),
    .gfx_mode_8_bpp_i        ( gfx_mode_8_bpp_i       ),
    .gfx_mode_16_bpp_i       ( gfx_mode_16_bpp_i      ),
    .vid_ram_addr_i          ( vid_ram_addr           ),
    .vid_ram_addr_init_i     ( vid_ram_addr_hi_wr_dly ),
    .vid_ram_addr_step_i     ( vid_ram_addr_inc_wr    ),
    .vid_ram_width_i         ( vid_ram_width          ),
    .vid_ram_msk_mode_i      ( vid_ram_msk_mode       ),
    .vid_ram_win_mode_i      ( vid_ram_win_mode       ),
    .vid_ram_win_x_swap_i    ( vid_ram_win_x_swap     ),
    .vid_ram_win_y_swap_i    ( vid_ram_win_y_swap     ),
    .vid_ram_win_cl_swap_i   ( vid_ram_win_cl_swap    )
);







wire [15:0] per_din_mask_mode = (({16{gfx_mode_1_bpp_i  &  vid_ram_msk_mode }} & {16{per_din_i[0]  }}) |
                                 ({16{gfx_mode_2_bpp_i  &  vid_ram_msk_mode }} &  {8{per_din_i[1:0]}}) |
                                 ({16{gfx_mode_4_bpp_i  &  vid_ram_msk_mode }} &  {4{per_din_i[3:0]}}) |
                                 ({16{gfx_mode_8_bpp_i  &  vid_ram_msk_mode }} &  {2{per_din_i[7:0]}}) |
                                 ({16{gfx_mode_16_bpp_i | ~vid_ram_msk_mode }} &     per_din_i       ) );


reg  [15:0] vid_ram_data_mask;
wire [15:0] per_din_ram_nxt   = per_din_mask_mode & vid_ram_data_mask;


reg  [15:0] vid_ram_data;
wire [15:0] vid_ram_data_mux;
wire        vid_ram_dout_rdy;
always @ (posedge mclk or posedge puc_rst)
  if (puc_rst)                vid_ram_data <=  16'h0000;
  else if (vid_ram_data_wr_i) vid_ram_data <=  per_din_ram_nxt | (vid_ram_data_mux & ~vid_ram_data_mask);
  else if (vid_ram_dout_rdy)  vid_ram_data <=  vid_ram_dout_i;


assign      vid_ram_data_mux            =  vid_ram_dout_rdy ? vid_ram_dout_i : vid_ram_data;


wire [15:0] vid_ram_data_rd_mask        =  vid_ram_data_mux & vid_ram_data_mask;
wire        vid_ram_data_rd_mask_1_bpp  =  (|vid_ram_data_rd_mask);
wire  [1:0] vid_ram_data_rd_mask_2_bpp  = {(|{vid_ram_data_rd_mask[15], vid_ram_data_rd_mask[13], vid_ram_data_rd_mask[11], vid_ram_data_rd_mask[9], vid_ram_data_rd_mask[7], vid_ram_data_rd_mask[5], vid_ram_data_rd_mask[3], vid_ram_data_rd_mask[1]}),
                                           (|{vid_ram_data_rd_mask[14], vid_ram_data_rd_mask[12], vid_ram_data_rd_mask[10], vid_ram_data_rd_mask[8], vid_ram_data_rd_mask[6], vid_ram_data_rd_mask[4], vid_ram_data_rd_mask[2], vid_ram_data_rd_mask[0]})};
wire  [3:0] vid_ram_data_rd_mask_4_bpp  = {(|{vid_ram_data_rd_mask[15], vid_ram_data_rd_mask[11], vid_ram_data_rd_mask[7] , vid_ram_data_rd_mask[3]}),
                                           (|{vid_ram_data_rd_mask[14], vid_ram_data_rd_mask[10], vid_ram_data_rd_mask[6] , vid_ram_data_rd_mask[2]}),
                                           (|{vid_ram_data_rd_mask[13], vid_ram_data_rd_mask[9] , vid_ram_data_rd_mask[5] , vid_ram_data_rd_mask[1]}),
                                           (|{vid_ram_data_rd_mask[12], vid_ram_data_rd_mask[8] , vid_ram_data_rd_mask[4] , vid_ram_data_rd_mask[0]})};
wire  [7:0] vid_ram_data_rd_mask_8_bpp  = {(|{vid_ram_data_rd_mask[15], vid_ram_data_rd_mask[7]}),
                                           (|{vid_ram_data_rd_mask[14], vid_ram_data_rd_mask[6]}),
                                           (|{vid_ram_data_rd_mask[13], vid_ram_data_rd_mask[5]}),
                                           (|{vid_ram_data_rd_mask[12], vid_ram_data_rd_mask[4]}),
                                           (|{vid_ram_data_rd_mask[11], vid_ram_data_rd_mask[3]}),
                                           (|{vid_ram_data_rd_mask[10], vid_ram_data_rd_mask[2]}),
                                           (|{vid_ram_data_rd_mask[9] , vid_ram_data_rd_mask[1]}),
                                           (|{vid_ram_data_rd_mask[8] , vid_ram_data_rd_mask[0]})};
wire [15:0] vid_ram_data_rd_mask_16_bpp =     vid_ram_data_rd_mask;

assign      vid_ram_data_o              =  ({16{gfx_mode_1_bpp_i  &  vid_ram_msk_mode }} & {{15{1'b0}},vid_ram_data_rd_mask_1_bpp}) |
                                           ({16{gfx_mode_2_bpp_i  &  vid_ram_msk_mode }} & {{14{1'b0}},vid_ram_data_rd_mask_2_bpp}) |
                                           ({16{gfx_mode_4_bpp_i  &  vid_ram_msk_mode }} & {{12{1'b0}},vid_ram_data_rd_mask_4_bpp}) |
                                           ({16{gfx_mode_8_bpp_i  &  vid_ram_msk_mode }} & { {8{1'b0}},vid_ram_data_rd_mask_8_bpp}) |
                                           ({16{gfx_mode_16_bpp_i | ~vid_ram_msk_mode }} &             vid_ram_data_rd_mask_16_bpp) ;




















always @ (posedge mclk or posedge puc_rst)
  if (puc_rst) vid_ram_addr_hi_wr_dly  <= 1'b0;
  else         vid_ram_addr_hi_wr_dly  <= vid_ram_addr_hi_wr_i;


reg        vid_ram_data_rd_dly;
always @ (posedge mclk or posedge puc_rst)
  if (puc_rst) vid_ram_data_rd_dly     <= 1'b0;
  else         vid_ram_data_rd_dly     <= vid_ram_data_rd_i;


reg        vid_ram_data_wr_dly;
always @ (posedge mclk or posedge puc_rst)
  if (puc_rst) vid_ram_data_wr_dly     <= 1'b0;
  else         vid_ram_data_wr_dly     <= vid_ram_data_wr_i;


wire       vid_ram_data_rd_msk   = ((vid_ram_data_wr_dly  | vid_ram_data_rd_dly | vid_ram_addr_hi_wr_i) & vid_ram_msk_mode & ~gfx_mode_16_bpp_i);








assign vid_ram_we_o     =  vid_ram_data_wr_dly;





wire   vid_ram_ce_early = (vid_ram_addr_hi_wr_i | vid_ram_data_rd_dly | vid_ram_data_rd_msk |
                           vid_ram_data_wr_i);

reg [1:0] vid_ram_ce;
always @ (posedge mclk or posedge puc_rst)
  if (puc_rst) vid_ram_ce <= 2'b00;
  else         vid_ram_ce <= {vid_ram_ce[0] & ~vid_ram_data_wr_dly, vid_ram_ce_early};

assign vid_ram_ce_o     = vid_ram_ce[0];


assign vid_ram_din_o    = {16{vid_ram_ce[0]}} & vid_ram_data;


assign vid_ram_dout_rdy = vid_ram_ce[1];







`ifdef VRAM_BIGGER_4_KW
wire [`APIX_MSB:0] vid_ram_addr_mux    = vid_ram_addr_hi_wr_i ? {per_din_i[`APIX_HI_MSB:0], vid_ram_addr[15:0]} :
                                         vid_ram_data_rd_msk  ?  vid_ram_addr_inc                               : vid_ram_addr;
`else
wire [`APIX_MSB:0] vid_ram_addr_mux    = vid_ram_addr_hi_wr_i ? {per_din_i[`APIX_LO_MSB:0]}                     :
                                         vid_ram_data_rd_msk  ?  vid_ram_addr_inc                               : vid_ram_addr;
`endif


wire [`APIX_MSB:0] vid_ram_addr_offset = vid_ram_base_addr_i + vid_ram_addr_mux;


wire               vid_ram_access_o    = vid_ram_data_wr_i | vid_ram_data_rd_dly | vid_ram_addr_hi_wr_i | vid_ram_data_rd_msk;


wire [`APIX_MSB:0] vid_ram_addr_nxt_o  = {`APIX_MSB+1{vid_ram_access_o}} & vid_ram_addr_offset;




assign             vid_ram_addr_inc_wr = vid_ram_addr_hi_wr_dly | vid_ram_data_wr_dly | (vid_ram_data_rd_i & ~dbg_freeze_i & ~vid_ram_rmw_mode);


wire         [3:0] gfx_mode_addr_msk   = (        {4{gfx_mode_1_bpp_i}}  |
                                          {1'b0,  {3{gfx_mode_2_bpp_i}}} |
                                          {2'b00, {2{gfx_mode_4_bpp_i}}} |
                                          {3'b000,   gfx_mode_8_bpp_i});


wire    [15:0] vid_ram_data_mask_shift = one_hot16(vid_ram_addr_offset[3:0] & gfx_mode_addr_msk);
wire    [15:0] vid_ram_data_mask_nxt   = ({16{gfx_mode_1_bpp_i }} &     vid_ram_data_mask_shift      ) |
                                         ({16{gfx_mode_2_bpp_i }} & {{2{vid_ram_data_mask_shift[7]}},
                                                                     {2{vid_ram_data_mask_shift[6]}},
                                                                     {2{vid_ram_data_mask_shift[5]}},
                                                                     {2{vid_ram_data_mask_shift[4]}},
                                                                     {2{vid_ram_data_mask_shift[3]}},
                                                                     {2{vid_ram_data_mask_shift[2]}},
                                                                     {2{vid_ram_data_mask_shift[1]}},
                                                                     {2{vid_ram_data_mask_shift[0]}}}) |
                                         ({16{gfx_mode_4_bpp_i }} & {{4{vid_ram_data_mask_shift[3]}},
                                                                     {4{vid_ram_data_mask_shift[2]}},
                                                                     {4{vid_ram_data_mask_shift[1]}},
                                                                     {4{vid_ram_data_mask_shift[0]}}}) |
                                         ({16{gfx_mode_8_bpp_i }} & {{8{vid_ram_data_mask_shift[1]}},
                                                                     {8{vid_ram_data_mask_shift[0]}}}) |
                                         ({16{gfx_mode_16_bpp_i}} & {16{1'b1}}                       ) ;

always @ (posedge mclk or posedge puc_rst)
  if (puc_rst)                   vid_ram_data_mask <=  16'hffff;
  else if (vid_ram_data_rd_msk)  vid_ram_data_mask <=  vid_ram_data_mask_nxt;
  else if (vid_ram_access_o)     vid_ram_data_mask <=  16'hffff;


endmodule
module  ogfx_reg_vram_if (


    vid_ram_cfg_o,
    vid_ram_width_o,
`ifdef VRAM_BIGGER_4_KW
    vid_ram_addr_hi_o,
`endif
    vid_ram_addr_lo_o,
    vid_ram_data_o,

    vid_ram_we_o,
    vid_ram_ce_o,
    vid_ram_din_o,
    vid_ram_addr_nxt_o,
    vid_ram_access_o,


    mclk,
    puc_rst,

    vid_ram_cfg_wr_i,
    vid_ram_width_wr_i,
    vid_ram_addr_hi_wr_i,
    vid_ram_addr_lo_wr_i,
    vid_ram_data_wr_i,
    vid_ram_data_rd_i,

    dbg_freeze_i,
    display_width_i,
    gfx_mode_1_bpp_i,
    gfx_mode_2_bpp_i,
    gfx_mode_4_bpp_i,
    gfx_mode_8_bpp_i,
    gfx_mode_16_bpp_i,

    per_din_i,
    vid_ram_base_addr_i,
    vid_ram_dout_i
);




output        [15:0] vid_ram_cfg_o;
output        [15:0] vid_ram_width_o;
`ifdef VRAM_BIGGER_4_KW
output        [15:0] vid_ram_addr_hi_o;
`endif
output        [15:0] vid_ram_addr_lo_o;
output        [15:0] vid_ram_data_o;

output               vid_ram_we_o;
output               vid_ram_ce_o;
output        [15:0] vid_ram_din_o;
output [`APIX_MSB:0] vid_ram_addr_nxt_o;
output               vid_ram_access_o;



input                mclk;
input                puc_rst;

input                vid_ram_cfg_wr_i;
input                vid_ram_width_wr_i;
input                vid_ram_addr_hi_wr_i;
input                vid_ram_addr_lo_wr_i;
input                vid_ram_data_wr_i;
input                vid_ram_data_rd_i;

input                dbg_freeze_i;
input  [`LPIX_MSB:0] display_width_i;
input                gfx_mode_1_bpp_i;
input                gfx_mode_2_bpp_i;
input                gfx_mode_4_bpp_i;
input                gfx_mode_8_bpp_i;
input                gfx_mode_16_bpp_i;

input         [15:0] per_din_i;
input  [`APIX_MSB:0] vid_ram_base_addr_i;
input         [15:0] vid_ram_dout_i;







function [15:0] one_hot16;
   input  [3:0] binary;
   begin
      one_hot16         = 16'h0000;
      one_hot16[binary] =  1'b1;
   end
endfunction










reg                vid_ram_rmw_mode;
reg                vid_ram_msk_mode;
reg                vid_ram_win_mode;
reg                vid_ram_win_x_swap;
reg                vid_ram_win_y_swap;
reg                vid_ram_win_cl_swap;

always @ (posedge mclk or posedge puc_rst)
  if (puc_rst)
    begin
       vid_ram_win_cl_swap  <=  1'b0;
       vid_ram_win_y_swap   <=  1'b0;
       vid_ram_win_x_swap   <=  1'b0;
       vid_ram_rmw_mode     <=  1'b0;
       vid_ram_msk_mode     <=  1'b0;
       vid_ram_win_mode     <=  1'b0;
    end
  else if (vid_ram_cfg_wr_i)
    begin
       vid_ram_win_cl_swap  <=  per_din_i[0];
       vid_ram_win_y_swap   <=  per_din_i[1];
       vid_ram_win_x_swap   <=  per_din_i[2];
       vid_ram_rmw_mode     <=  per_din_i[4];
       vid_ram_msk_mode     <=  per_din_i[5];
       vid_ram_win_mode     <=  per_din_i[6];
    end

assign vid_ram_cfg_o  = {8'h00, 1'b0,  vid_ram_win_mode,   vid_ram_msk_mode,   vid_ram_rmw_mode   ,
                                1'b0,  vid_ram_win_x_swap, vid_ram_win_y_swap, vid_ram_win_cl_swap};




reg  [`LPIX_MSB:0] vid_ram_width;


wire [`LPIX_MSB:0] vid_ram_width_nxt  = (|per_din_i[`LPIX_MSB:0]) ? per_din_i[`LPIX_MSB:0] : {{`LPIX_MSB{1'b0}}, 1'b1};

always @ (posedge mclk or posedge puc_rst)
  if (puc_rst)                 vid_ram_width   <=  {{`LPIX_MSB{1'b0}}, 1'b1};
  else if (vid_ram_width_wr_i) vid_ram_width   <=  vid_ram_width_nxt;

wire [16:0] vid_ram_width_tmp = {{16-`LPIX_MSB{1'b0}}, vid_ram_width};
assign      vid_ram_width_o   = vid_ram_width_tmp[15:0];





wire   [`APIX_MSB:0] vid_ram_addr;
wire   [`APIX_MSB:0] vid_ram_addr_inc;
wire                 vid_ram_addr_inc_wr;
reg                  vid_ram_addr_hi_wr_dly;

`ifdef VRAM_BIGGER_4_KW
reg [`APIX_HI_MSB:0] vid_ram_addr_hi;

always @ (posedge mclk or posedge puc_rst)
  if (puc_rst)                   vid_ram_addr_hi <=  {`APIX_HI_MSB+1{1'b0}};
  else if (vid_ram_addr_hi_wr_i) vid_ram_addr_hi <=  per_din_i[`APIX_HI_MSB:0];
  else if (vid_ram_addr_inc_wr)  vid_ram_addr_hi <=  vid_ram_addr_inc[`APIX_MSB:16];

wire [16:0] vid_ram_addr_hi_tmp = {{16-`APIX_HI_MSB{1'b0}},vid_ram_addr_hi};
assign      vid_ram_addr_hi_o   = vid_ram_addr_hi_tmp[15:0];
`endif




reg [`APIX_LO_MSB:0] vid_ram_addr_lo;

always @ (posedge mclk or posedge puc_rst)
  if (puc_rst)                   vid_ram_addr_lo <=  {`APIX_LO_MSB+1{1'b0}};
  else if (vid_ram_addr_lo_wr_i) vid_ram_addr_lo <=  per_din_i[`APIX_LO_MSB:0];
  else if (vid_ram_addr_inc_wr)  vid_ram_addr_lo <=  vid_ram_addr_inc[`APIX_LO_MSB:0];

`ifdef VRAM_BIGGER_4_KW
assign      vid_ram_addr        = {vid_ram_addr_hi[`APIX_HI_MSB:0], vid_ram_addr_lo};
assign      vid_ram_addr_lo_o   =  vid_ram_addr_lo;
`else
assign      vid_ram_addr        = {vid_ram_addr_lo[`APIX_LO_MSB:0]};
wire [16:0] vid_ram_addr_lo_tmp = {{16-`APIX_LO_MSB{1'b0}},vid_ram_addr_lo};
assign      vid_ram_addr_lo_o   = vid_ram_addr_lo_tmp[15:0];
`endif


ogfx_reg_vram_addr ogfx_reg_vram_addr_inst (


    .vid_ram_addr_nxt_o      ( vid_ram_addr_inc       ),


    .mclk                    ( mclk                   ),
    .puc_rst                 ( puc_rst                ),
    .display_width_i         ( display_width_i        ),
    .gfx_mode_1_bpp_i        ( gfx_mode_1_bpp_i       ),
    .gfx_mode_2_bpp_i        ( gfx_mode_2_bpp_i       ),
    .gfx_mode_4_bpp_i        ( gfx_mode_4_bpp_i       ),
    .gfx_mode_8_bpp_i        ( gfx_mode_8_bpp_i       ),
    .gfx_mode_16_bpp_i       ( gfx_mode_16_bpp_i      ),
    .vid_ram_addr_i          ( vid_ram_addr           ),
    .vid_ram_addr_init_i     ( vid_ram_addr_hi_wr_dly ),
    .vid_ram_addr_step_i     ( vid_ram_addr_inc_wr    ),
    .vid_ram_width_i         ( vid_ram_width          ),
    .vid_ram_msk_mode_i      ( vid_ram_msk_mode       ),
    .vid_ram_win_mode_i      ( vid_ram_win_mode       ),
    .vid_ram_win_x_swap_i    ( vid_ram_win_x_swap     ),
    .vid_ram_win_y_swap_i    ( vid_ram_win_y_swap     ),
    .vid_ram_win_cl_swap_i   ( vid_ram_win_cl_swap    )
);







wire [15:0] per_din_mask_mode = (({16{gfx_mode_1_bpp_i  &  vid_ram_msk_mode }} & {16{per_din_i[0]  }}) |
                                 ({16{gfx_mode_2_bpp_i  &  vid_ram_msk_mode }} &  {8{per_din_i[1:0]}}) |
                                 ({16{gfx_mode_4_bpp_i  &  vid_ram_msk_mode }} &  {4{per_din_i[3:0]}}) |
                                 ({16{gfx_mode_8_bpp_i  &  vid_ram_msk_mode }} &  {2{per_din_i[7:0]}}) |
                                 ({16{gfx_mode_16_bpp_i | ~vid_ram_msk_mode }} &     per_din_i       ) );


reg  [15:0] vid_ram_data_mask;
wire [15:0] per_din_ram_nxt   = per_din_mask_mode & vid_ram_data_mask;


reg  [15:0] vid_ram_data;
wire [15:0] vid_ram_data_mux;
wire        vid_ram_dout_rdy;
always @ (posedge mclk or posedge puc_rst)
  if (puc_rst)                vid_ram_data <=  16'h0000;
  else if (vid_ram_data_wr_i) vid_ram_data <=  per_din_ram_nxt | (vid_ram_data_mux & ~vid_ram_data_mask);
  else if (vid_ram_dout_rdy)  vid_ram_data <=  vid_ram_dout_i;


assign      vid_ram_data_mux            =  vid_ram_dout_rdy ? vid_ram_dout_i : vid_ram_data;


wire [15:0] vid_ram_data_rd_mask        =  vid_ram_data_mux & vid_ram_data_mask;
wire        vid_ram_data_rd_mask_1_bpp  =  (|vid_ram_data_rd_mask);
wire  [1:0] vid_ram_data_rd_mask_2_bpp  = {(|{vid_ram_data_rd_mask[15], vid_ram_data_rd_mask[13], vid_ram_data_rd_mask[11], vid_ram_data_rd_mask[9], vid_ram_data_rd_mask[7], vid_ram_data_rd_mask[5], vid_ram_data_rd_mask[3], vid_ram_data_rd_mask[1]}),
                                           (|{vid_ram_data_rd_mask[14], vid_ram_data_rd_mask[12], vid_ram_data_rd_mask[10], vid_ram_data_rd_mask[8], vid_ram_data_rd_mask[6], vid_ram_data_rd_mask[4], vid_ram_data_rd_mask[2], vid_ram_data_rd_mask[0]})};
wire  [3:0] vid_ram_data_rd_mask_4_bpp  = {(|{vid_ram_data_rd_mask[15], vid_ram_data_rd_mask[11], vid_ram_data_rd_mask[7] , vid_ram_data_rd_mask[3]}),
                                           (|{vid_ram_data_rd_mask[14], vid_ram_data_rd_mask[10], vid_ram_data_rd_mask[6] , vid_ram_data_rd_mask[2]}),
                                           (|{vid_ram_data_rd_mask[13], vid_ram_data_rd_mask[9] , vid_ram_data_rd_mask[5] , vid_ram_data_rd_mask[1]}),
                                           (|{vid_ram_data_rd_mask[12], vid_ram_data_rd_mask[8] , vid_ram_data_rd_mask[4] , vid_ram_data_rd_mask[0]})};
wire  [7:0] vid_ram_data_rd_mask_8_bpp  = {(|{vid_ram_data_rd_mask[15], vid_ram_data_rd_mask[7]}),
                                           (|{vid_ram_data_rd_mask[14], vid_ram_data_rd_mask[6]}),
                                           (|{vid_ram_data_rd_mask[13], vid_ram_data_rd_mask[5]}),
                                           (|{vid_ram_data_rd_mask[12], vid_ram_data_rd_mask[4]}),
                                           (|{vid_ram_data_rd_mask[11], vid_ram_data_rd_mask[3]}),
                                           (|{vid_ram_data_rd_mask[10], vid_ram_data_rd_mask[2]}),
                                           (|{vid_ram_data_rd_mask[9] , vid_ram_data_rd_mask[1]}),
                                           (|{vid_ram_data_rd_mask[8] , vid_ram_data_rd_mask[0]})};
wire [15:0] vid_ram_data_rd_mask_16_bpp =     vid_ram_data_rd_mask;

assign      vid_ram_data_o              =  ({16{gfx_mode_1_bpp_i  &  vid_ram_msk_mode }} & {{15{1'b0}},vid_ram_data_rd_mask_1_bpp}) |
                                           ({16{gfx_mode_2_bpp_i  &  vid_ram_msk_mode }} & {{14{1'b0}},vid_ram_data_rd_mask_2_bpp}) |
                                           ({16{gfx_mode_4_bpp_i  &  vid_ram_msk_mode }} & {{12{1'b0}},vid_ram_data_rd_mask_4_bpp}) |
                                           ({16{gfx_mode_8_bpp_i  &  vid_ram_msk_mode }} & { {8{1'b0}},vid_ram_data_rd_mask_8_bpp}) |
                                           ({16{gfx_mode_16_bpp_i | ~vid_ram_msk_mode }} &             vid_ram_data_rd_mask_16_bpp) ;




















always @ (posedge mclk or posedge puc_rst)
  if (puc_rst) vid_ram_addr_hi_wr_dly  <= 1'b0;
  else         vid_ram_addr_hi_wr_dly  <= vid_ram_addr_hi_wr_i;


reg        vid_ram_data_rd_dly;
always @ (posedge mclk or posedge puc_rst)
  if (puc_rst) vid_ram_data_rd_dly     <= 1'b0;
  else         vid_ram_data_rd_dly     <= vid_ram_data_rd_i;


reg        vid_ram_data_wr_dly;
always @ (posedge mclk or posedge puc_rst)
  if (puc_rst) vid_ram_data_wr_dly     <= 1'b0;
  else         vid_ram_data_wr_dly     <= vid_ram_data_wr_i;


wire       vid_ram_data_rd_msk   = ((vid_ram_data_wr_dly  | vid_ram_data_rd_dly | vid_ram_addr_hi_wr_i) & vid_ram_msk_mode & ~gfx_mode_16_bpp_i);








assign vid_ram_we_o     =  vid_ram_data_wr_dly;





wire   vid_ram_ce_early = (vid_ram_addr_hi_wr_i | vid_ram_data_rd_dly | vid_ram_data_rd_msk |
                           vid_ram_data_wr_i);

reg [1:0] vid_ram_ce;
always @ (posedge mclk or posedge puc_rst)
  if (puc_rst) vid_ram_ce <= 2'b00;
  else         vid_ram_ce <= {vid_ram_ce[0] & ~vid_ram_data_wr_dly, vid_ram_ce_early};

assign vid_ram_ce_o     = vid_ram_ce[0];


assign vid_ram_din_o    = {16{vid_ram_ce[0]}} & vid_ram_data;


assign vid_ram_dout_rdy = vid_ram_ce[1];







`ifdef VRAM_BIGGER_4_KW
wire [`APIX_MSB:0] vid_ram_addr_mux    = vid_ram_addr_hi_wr_i ? {per_din_i[`APIX_HI_MSB:0], vid_ram_addr[15:0]} :
                                         vid_ram_data_rd_msk  ?  vid_ram_addr_inc                               : vid_ram_addr;
`else
wire [`APIX_MSB:0] vid_ram_addr_mux    = vid_ram_addr_hi_wr_i ? {per_din_i[`APIX_LO_MSB:0]}                     :
                                         vid_ram_data_rd_msk  ?  vid_ram_addr_inc                               : vid_ram_addr;
`endif


wire [`APIX_MSB:0] vid_ram_addr_offset = vid_ram_base_addr_i + vid_ram_addr_mux;


wire               vid_ram_access_o    = vid_ram_data_wr_i | vid_ram_data_rd_dly | vid_ram_addr_hi_wr_i | vid_ram_data_rd_msk;


wire [`APIX_MSB:0] vid_ram_addr_nxt_o  = {`APIX_MSB+1{vid_ram_access_o}} & vid_ram_addr_offset;




assign             vid_ram_addr_inc_wr = vid_ram_addr_hi_wr_dly | vid_ram_data_wr_dly | (vid_ram_data_rd_i & ~dbg_freeze_i & ~vid_ram_rmw_mode);


wire         [3:0] gfx_mode_addr_msk   = (        {4{gfx_mode_1_bpp_i}}  |
                                          {1'b0,  {3{gfx_mode_2_bpp_i}}} |
                                          {2'b00, {2{gfx_mode_4_bpp_i}}} |
                                          {3'b000,   gfx_mode_8_bpp_i});


wire    [15:0] vid_ram_data_mask_shift = one_hot16(vid_ram_addr_offset[3:0] & gfx_mode_addr_msk);
wire    [15:0] vid_ram_data_mask_nxt   = ({16{gfx_mode_1_bpp_i }} &     vid_ram_data_mask_shift      ) |
                                         ({16{gfx_mode_2_bpp_i }} & {{2{vid_ram_data_mask_shift[7]}},
                                                                     {2{vid_ram_data_mask_shift[6]}},
                                                                     {2{vid_ram_data_mask_shift[5]}},
                                                                     {2{vid_ram_data_mask_shift[4]}},
                                                                     {2{vid_ram_data_mask_shift[3]}},
                                                                     {2{vid_ram_data_mask_shift[2]}},
                                                                     {2{vid_ram_data_mask_shift[1]}},
                                                                     {2{vid_ram_data_mask_shift[0]}}}) |
                                         ({16{gfx_mode_4_bpp_i }} & {{4{vid_ram_data_mask_shift[3]}},
                                                                     {4{vid_ram_data_mask_shift[2]}},
                                                                     {4{vid_ram_data_mask_shift[1]}},
                                                                     {4{vid_ram_data_mask_shift[0]}}}) |
                                         ({16{gfx_mode_8_bpp_i }} & {{8{vid_ram_data_mask_shift[1]}},
                                                                     {8{vid_ram_data_mask_shift[0]}}}) |
                                         ({16{gfx_mode_16_bpp_i}} & {16{1'b1}}                       ) ;

always @ (posedge mclk or posedge puc_rst)
  if (puc_rst)                   vid_ram_data_mask <=  16'hffff;
  else if (vid_ram_data_rd_msk)  vid_ram_data_mask <=  vid_ram_data_mask_nxt;
  else if (vid_ram_access_o)     vid_ram_data_mask <=  16'hffff;


endmodule