data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:118: Multiple top level modules\n                                                                                         : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                         : ... Top module \'rs_7_5_encoder\'\nmodule rs_7_5_encoder\n       ^~~~~~~~~~~~~~\n                                                                                         : ... Top module \'rs_7_5_decoder\'\nmodule rs_7_5_decoder\n       ^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:170: Operator ADD expects 32 bits on the RHS, but RHS\'s ARRAYSEL generates 3 bits.\n                                                                                      : ... In instance rs_7_5_decoder\n    S1_poly[idx] = (7 - idx) + GF_log[s[idx]];               \n                             ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:170: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s ADD generates 32 bits.\n                                                                                      : ... In instance rs_7_5_decoder\n    S1_poly[idx] = (7 - idx) + GF_log[s[idx]];               \n                 ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:171: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                      : ... In instance rs_7_5_decoder\n    S1_poly[idx] = S1_poly[idx][2:0] + S1_poly[idx][3];      \n                                     ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:172: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s ARRAYSEL generates 3 bits.\n                                                                                      : ... In instance rs_7_5_decoder\n    S1_poly[idx] = s[idx] ? GF_alog[S1_poly[idx]] : 3\'b000;  \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:172: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s ARRAYSEL generates 3 bits.\n                                                                                      : ... In instance rs_7_5_decoder\n    S1_poly[idx] = s[idx] ? GF_alog[S1_poly[idx]] : 3\'b000;  \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:172: Operator COND expects 4 bits on the Conditional False, but Conditional False\'s CONST \'3\'h0\' generates 3 bits.\n                                                                                      : ... In instance rs_7_5_decoder\n    S1_poly[idx] = s[idx] ? GF_alog[S1_poly[idx]] : 3\'b000;  \n                          ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:175: Operator XOR expects 4 bits on the LHS, but LHS\'s VARREF \'S1\' generates 3 bits.\n                                                                                      : ... In instance rs_7_5_decoder\n    S1           = S1 ^ S1_poly[idx];\n                      ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:175: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s XOR generates 4 bits.\n                                                                                      : ... In instance rs_7_5_decoder\n    S1           = S1 ^ S1_poly[idx];\n                 ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:183: Operator SUB expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                      : ... In instance rs_7_5_decoder\n    k      = k[2:0] - k[3];                                  \n                    ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:184: Operator COND expects 4 bits on the Conditional True, but Conditional True\'s ARRAYSEL generates 3 bits.\n                                                                                      : ... In instance rs_7_5_decoder\n    k      = (k == 4\'b0000) ? GF_log[3\'b001] : k;            \n                            ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:100: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                      : ... In instance rs_7_5_encoder\n    p_data[idx] = p_data[idx][2:0] + p_data[idx][3];  \n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:101: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 3 bits.\n                                                                                      : ... In instance rs_7_5_encoder\n    p_data[idx] = GF_alog[p_data[idx]];               \n                ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:102: Operator XOR expects 4 bits on the LHS, but LHS\'s VARREF \'P\' generates 3 bits.\n                                                                                      : ... In instance rs_7_5_encoder\n    P           = P ^ p_data[idx];                    \n                    ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:102: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s XOR generates 4 bits.\n                                                                                      : ... In instance rs_7_5_encoder\n    P           = P ^ p_data[idx];                    \n                ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:106: Operator ADD expects 4 bits on the RHS, but RHS\'s SEL generates 1 bits.\n                                                                                      : ... In instance rs_7_5_encoder\n    q_data[idx] = q_data[idx][2:0] + q_data[idx][3];  \n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:107: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 3 bits.\n                                                                                      : ... In instance rs_7_5_encoder\n    q_data[idx] = GF_alog[q_data[idx]];               \n                ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:108: Operator XOR expects 4 bits on the LHS, but LHS\'s VARREF \'Q\' generates 3 bits.\n                                                                                      : ... In instance rs_7_5_encoder\n    Q           = Q ^ q_data[idx];                    \n                    ^\n%Warning-WIDTH: data/full_repos/permissive/512358321/verilog/reed_solomon/rs_7_5.v:108: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s XOR generates 4 bits.\n                                                                                      : ... In instance rs_7_5_encoder\n    Q           = Q ^ q_data[idx];                    \n                ^\n%Error: Exiting due to 19 warning(s)\n'
module tb
#(parameter
  CLK_FREQ_MHZ                         = 100,
  RESET_PERIOD                         = 10,
  DATA_PATTERN                         = 15'b111_100_010_100_101,
  TEST_GUI                             = 1
)
();

integer     count;
reg         clk;
wire        reset_n;

reg  [14:0] idata;
wire [20:0] ocode;
reg  [20:0] error;
wire [20:0] icode;
wire [14:0] odata;


wire        cmp_error                  = (idata ^ odata) != 15'h0000;





initial
begin
  count                                = -1;
  clk                                  = 1'b1;
  error                                = {3'b000, 3'b000, 3'b000, 3'b000, 3'b001};
  idata                                = DATA_PATTERN;
end


always #(500/CLK_FREQ_MHZ)
  clk                                  = ~clk;


always @(posedge clk)
  count                                = count + 1;


assign reset_n                         = (count >= RESET_PERIOD) ? 1'b1 : 1'b0;






always @(posedge clk)
begin
  if ((count > RESET_PERIOD) && ((count-RESET_PERIOD)%4) == 3)
  begin


    if (error[20:18] != 3'b000 && error[20:18] != 3'b111)
    begin
      error[2:0]                       = error[20:18] + 1;
      error[20:18]                     = 3'b000;
    end
    else
    begin

       error                           = error << 3;
    end
  end


  if (error == 0 || (reset_n && cmp_error))
  begin
    if (cmp_error)
    begin
      $display("***FAIL: comparison error");
    end
    else
    begin
      $display("No errors");
    end

    if (TEST_GUI)
      $stop;
    else
      $finish;
  end
end




  



  rs_7_5_encoder enc (idata, ocode);


  assign icode                         = ocode ^ error;




  rs_7_5_decoder dec (icode, odata);

endmodule
module tb
#(parameter
  CLK_FREQ_MHZ                         = 100,
  RESET_PERIOD                         = 10,
  DATA_PATTERN                         = 15'b111_100_010_100_101,
  TEST_GUI                             = 1
)
();


integer     count;
reg         clk;
wire        reset_n;

reg  [14:0] idata;
wire [20:0] ocode;
reg  [20:0] error;
wire [20:0] icode;
wire [14:0] odata;


wire        cmp_error                  = (idata ^ odata) != 15'h0000;





initial
begin
  count                                = -1;
  clk                                  = 1'b1;
  error                                = {3'b000, 3'b000, 3'b000, 3'b000, 3'b001};
  idata                                = DATA_PATTERN;
end


always #(500/CLK_FREQ_MHZ)
  clk                                  = ~clk;


always @(posedge clk)
  count                                = count + 1;


assign reset_n                         = (count >= RESET_PERIOD) ? 1'b1 : 1'b0;






always @(posedge clk)
begin
  if ((count > RESET_PERIOD) && ((count-RESET_PERIOD)%4) == 3)
  begin


    if (error[20:18] != 3'b000 && error[20:18] != 3'b111)
    begin
      error[2:0]                       = error[20:18] + 1;
      error[20:18]                     = 3'b000;
    end
    else
    begin

       error                           = error << 3;
    end
  end


  if (error == 0 || (reset_n && cmp_error))
  begin
    if (cmp_error)
    begin
      $display("***FAIL: comparison error");
    end
    else
    begin
      $display("No errors");
    end

    if (TEST_GUI)
      $stop;
    else
      $finish;
  end
end




  



  rs_7_5_encoder enc (idata, ocode);


  assign icode                         = ocode ^ error;




  rs_7_5_decoder dec (icode, odata);

endmodule