data/full_repos/permissive/435170935/002-counter/counter_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/435170935/002-counter/counter_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/435170935/002-counter/counter_tb.v:39: Unsupported or unknown PLI call: $monitor\n        $monitor ("[%0t] rstn=0x%0h out=0x%0h", $time, rstn, out);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/435170935/002-counter/counter_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n        #10 rstn <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/435170935/002-counter/counter_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #30 rstn <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/435170935/002-counter/counter_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #70 rstn <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/435170935/002-counter/counter_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #95 rstn <= 0;\n        ^\n%Error: data/full_repos/permissive/435170935/002-counter/counter_tb.v:46: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("counter_tb.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/435170935/002-counter/counter_tb.v:47: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, counter_tb);  \n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/435170935/002-counter/counter_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n        #100 $finish;\n        ^\n%Error: Exiting due to 3 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module counter_tb;
    localparam width = 4;

    reg clk;
    reg rstn;
    wire [width - 1:0] out;

    always #1 clk = ~clk;
    
    counter #(
        .width (width)
    ) COUNTER (
        .clk(clk),
        .rstn(rstn),
        .out(out)
    );

    initial begin
        $display("Initialize to 0.");
        clk = 0;
        rstn = 0;

        $monitor ("[%0t] rstn=0x%0h out=0x%0h", $time, rstn, out);

        #10 rstn <= 1;
        #30 rstn <= 0;
        #70 rstn <= 1;
        #95 rstn <= 0;

        $dumpfile("counter_tb.vcd");
        $dumpvars(0, counter_tb);

        #100 $finish;
    end 

endmodule
module counter_tb;

    localparam width = 4;

    reg clk;
    reg rstn;
    wire [width - 1:0] out;

    always #1 clk = ~clk;
    
    counter #(
        .width (width)
    ) COUNTER (
        .clk(clk),
        .rstn(rstn),
        .out(out)
    );

    initial begin
        $display("Initialize to 0.");
        clk = 0;
        rstn = 0;

        $monitor ("[%0t] rstn=0x%0h out=0x%0h", $time, rstn, out);

        #10 rstn <= 1;
        #30 rstn <= 0;
        #70 rstn <= 1;
        #95 rstn <= 0;

        $dumpfile("counter_tb.vcd");
        $dumpvars(0, counter_tb);

        #100 $finish;
    end 

endmodule