data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/top_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/top_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\nalways #(PERIOD/2) clk380hz = ~clk380hz;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/top_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\nalways #(5*PERIOD) clk10hz = ~clk10hz;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/top_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\nalways #(10*PERIOD) clk1hz = ~clk1hz;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/top_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n    #PERIOD rst = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/top_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n    #(5*PERIOD) external[6] = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/top_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n    #(5*PERIOD) external[5] = 1;\n    ^\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/top_tb.v:34: Cannot find file containing module: \'request\'\n    request Request(\n    ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/434840709/USTB_verilog_elevator/sim,data/full_repos/permissive/434840709/request\n             data/full_repos/permissive/434840709/USTB_verilog_elevator/sim,data/full_repos/permissive/434840709/request.v\n             data/full_repos/permissive/434840709/USTB_verilog_elevator/sim,data/full_repos/permissive/434840709/request.sv\n             request\n             request.v\n             request.sv\n             obj_dir/request\n             obj_dir/request.v\n             obj_dir/request.sv\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/top_tb.v:47: Cannot find file containing module: \'control\'\n    control Control(\n    ^~~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/top_tb.v:57: Cannot find file containing module: \'num_segMsg\'\n    num_segMsg    numbers(clk380hz, number_dataBus, posL, segL);\n    ^~~~~~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/top_tb.v:58: Cannot find file containing module: \'signal_segMsg\'\n    signal_segMsg signals(clk380hz, signal_dataBus, posH, segH);\n    ^~~~~~~~~~~~~\n%Warning-WIDTHCONCAT: data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/top_tb.v:60: Unsized numbers/parameters not allowed in concatenations.\n                                                                                                : ... In instance tb_top\n    assign number_dataBus = {state_dataBus[3:0], curr_floor[3:0]+1, 8\'hff};\n                                                                ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/top_tb.v:60: Unsized numbers/parameters not allowed in concatenations.\n                                                                                                : ... In instance tb_top\n    assign number_dataBus = {state_dataBus[3:0], curr_floor[3:0]+1, 8\'hff};\n                                               ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/434840709/USTB_verilog_elevator/sim/top_tb.v:60: Unsized numbers/parameters not allowed in replications.\n                                                                                                : ... In instance tb_top\n    assign number_dataBus = {state_dataBus[3:0], curr_floor[3:0]+1, 8\'hff};\n                                                                  ^\n%Error: Exiting due to 4 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_top;


parameter PERIOD  = 10;



reg   clk380hz                             = 0 ;
reg   clk10hz                              = 0 ;
reg   clk1hz                               = 0 ;
reg   rst                                  = 1 ;
reg   [2*`F_N - 1:0]  external             = 0 ;
reg   [  `F_N - 1:0]  internal             = 0 ;


always #(PERIOD/2) clk380hz = ~clk380hz;
always #(5*PERIOD) clk10hz = ~clk10hz;
always #(10*PERIOD) clk1hz = ~clk1hz;

    wire [7:0] curr_floor;
    wire [3:0] running_state;
    wire [3:0] door_state;
    wire [2:0] req;
    wire [2*`F_N-1:0] demand_state;
    wire [3:0] state_dataBus;
    wire [15:0] number_dataBus;
    wire [15:0] signal_dataBus;
    wire posL, segL;
    wire posH, segH;

    request Request(
        .clk380hz(clk380hz), .clk10hz(clk10hz), .clk1hz(clk1hz),
        .rst(rst),
        .curr_floor(curr_floor),
        .running_state(running_state),
        .door_state(door_state),
        .floor_in(internal),
        .up_in(external[2*`F_N-1:`F_N]),
        .down_in(external[`F_N-1:0]),
        .req(req),
        .demand_state(demand_state)     
    );

    control Control(
        .clk380hz(clk380hz), .clk10hz(clk10hz), .clk1hz(clk1hz),
        .rst(rst),
        .req(req),
        .curr_floor(curr_floor),
        .running_state(running_state),
        .door_state(door_state),
        .state(state_dataBus)
    );

    num_segMsg    numbers(clk380hz, number_dataBus, posL, segL);
    signal_segMsg signals(clk380hz, signal_dataBus, posH, segH);

    assign number_dataBus = {state_dataBus[3:0], curr_floor[3:0]+1, 8'hff};
    assign signal_dataBus = {running_state[3:0], door_state[3:0], 8'b0};

initial
begin
    #PERIOD rst = 0;
    #(5*PERIOD) external[6] = 1;
    #(5*PERIOD) external[5] = 1;
end

endmodule
module tb_top;



parameter PERIOD  = 10;



reg   clk380hz                             = 0 ;
reg   clk10hz                              = 0 ;
reg   clk1hz                               = 0 ;
reg   rst                                  = 1 ;
reg   [2*`F_N - 1:0]  external             = 0 ;
reg   [  `F_N - 1:0]  internal             = 0 ;


always #(PERIOD/2) clk380hz = ~clk380hz;
always #(5*PERIOD) clk10hz = ~clk10hz;
always #(10*PERIOD) clk1hz = ~clk1hz;

    wire [7:0] curr_floor;
    wire [3:0] running_state;
    wire [3:0] door_state;
    wire [2:0] req;
    wire [2*`F_N-1:0] demand_state;
    wire [3:0] state_dataBus;
    wire [15:0] number_dataBus;
    wire [15:0] signal_dataBus;
    wire posL, segL;
    wire posH, segH;

    request Request(
        .clk380hz(clk380hz), .clk10hz(clk10hz), .clk1hz(clk1hz),
        .rst(rst),
        .curr_floor(curr_floor),
        .running_state(running_state),
        .door_state(door_state),
        .floor_in(internal),
        .up_in(external[2*`F_N-1:`F_N]),
        .down_in(external[`F_N-1:0]),
        .req(req),
        .demand_state(demand_state)     
    );

    control Control(
        .clk380hz(clk380hz), .clk10hz(clk10hz), .clk1hz(clk1hz),
        .rst(rst),
        .req(req),
        .curr_floor(curr_floor),
        .running_state(running_state),
        .door_state(door_state),
        .state(state_dataBus)
    );

    num_segMsg    numbers(clk380hz, number_dataBus, posL, segL);
    signal_segMsg signals(clk380hz, signal_dataBus, posH, segH);

    assign number_dataBus = {state_dataBus[3:0], curr_floor[3:0]+1, 8'hff};
    assign signal_dataBus = {running_state[3:0], door_state[3:0], 8'b0};

initial
begin
    #PERIOD rst = 0;
    #(5*PERIOD) external[6] = 1;
    #(5*PERIOD) external[5] = 1;
end

endmodule