data/full_repos/permissive/42434302/ivltests/nb_ec_pv2.v
1: b'%Error: data/full_repos/permissive/42434302/ivltests/nb_ec_pv2.v:6: syntax error, unexpected bit, expecting IDENTIFIER or \'=\' or do or final\n  reg [3:0] bit;\n            ^~~\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/nb_ec_pv2.v:8: Unsupported: Ignoring delay on this delayed statement.\n  always #10 clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/42434302/ivltests/nb_ec_pv2.v:14: syntax error, unexpected \']\', expecting "\'{"\n    result[bit] <= repeat(3) @(posedge clk) 1\'b0;\n              ^\n%Error: data/full_repos/permissive/42434302/ivltests/nb_ec_pv2.v:15: Unsupported or unknown PLI call: $simtime\n    if ($simtime != 0 || result !== 8\'bx) begin\n        ^~~~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/nb_ec_pv2.v:17: Unsupported or unknown PLI call: $simtime\n               $simtime, result);\n               ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/42434302/ivltests/nb_ec_pv2.v:20: Unsupported: Ignoring delay on this delayed statement.\n    #51;\n    ^\n%Error: data/full_repos/permissive/42434302/ivltests/nb_ec_pv2.v:23: Unsupported or unknown PLI call: $simtime\n               $simtime, result);\n               ^~~~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/nb_ec_pv2.v:27: syntax error, unexpected \'=\', expecting "\'{"\n    bit = 0;\n        ^\n%Error: data/full_repos/permissive/42434302/ivltests/nb_ec_pv2.v:28: syntax error, unexpected \']\', expecting "\'{"\n    result[bit] <= @(posedge clk) 4\'h0;\n              ^\n%Error: data/full_repos/permissive/42434302/ivltests/nb_ec_pv2.v:30: Unsupported or unknown PLI call: $simtime\n    if ($simtime != 70 || result !== 8\'bxxxxxxx0) begin\n        ^~~~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/nb_ec_pv2.v:32: Unsupported or unknown PLI call: $simtime\n               $simtime, result);\n               ^~~~~~~~\n%Error: data/full_repos/permissive/42434302/ivltests/nb_ec_pv2.v:36: syntax error, unexpected $display\n    if (pass) $display("PASSED");\n              ^~~~~~~~\n%Error: Cannot continue\n'
module top;
  reg pass = 1'b1;

  reg clk = 0;
  reg [7:0] result;
  reg [3:0] bit;

  always #10 clk = ~clk;

  initial begin



    result[bit] <= repeat(3) @(posedge clk) 1'b0;
    if ($simtime != 0 || result !== 8'bx) begin
      $display("Failed repeat(3) blocked at %0t, expected 8'hxx, got %h",
               $simtime, result);
      pass = 1'b0;
    end
    #51;
    if (result !== 8'hxx) begin
      $display("Failed repeat(3) at %0t, expected 8'hxx, got %h",
               $simtime, result);
      pass = 1'b0;
    end

    bit = 0;
    result[bit] <= @(posedge clk) 4'h0;
    @(result)
    if ($simtime != 70 || result !== 8'bxxxxxxx0) begin
      $display("Failed repeat(3) at %0t, expected 8'bxxxxxxx0, got %h",
               $simtime, result);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
    $finish;
  end
endmodule
module top;

  reg pass = 1'b1;

  reg clk = 0;
  reg [7:0] result;
  reg [3:0] bit;

  always #10 clk = ~clk;

  initial begin



    result[bit] <= repeat(3) @(posedge clk) 1'b0;
    if ($simtime != 0 || result !== 8'bx) begin
      $display("Failed repeat(3) blocked at %0t, expected 8'hxx, got %h",
               $simtime, result);
      pass = 1'b0;
    end
    #51;
    if (result !== 8'hxx) begin
      $display("Failed repeat(3) at %0t, expected 8'hxx, got %h",
               $simtime, result);
      pass = 1'b0;
    end

    bit = 0;
    result[bit] <= @(posedge clk) 4'h0;
    @(result)
    if ($simtime != 70 || result !== 8'bxxxxxxx0) begin
      $display("Failed repeat(3) at %0t, expected 8'bxxxxxxx0, got %h",
               $simtime, result);
      pass = 1'b0;
    end

    if (pass) $display("PASSED");
    $finish;
  end
endmodule