data/full_repos/permissive/52714256/GYRACC/src/ACC/format_data.v
1: b"%Error: data/full_repos/permissive/52714256/GYRACC/src/ACC/format_data.v:74: Cannot find file containing module: 'Binary_To_BCD'\n   Binary_To_BCD BtoBCD(\n   ^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/52714256/GYRACC/src/ACC,data/full_repos/permissive/52714256/Binary_To_BCD\n             data/full_repos/permissive/52714256/GYRACC/src/ACC,data/full_repos/permissive/52714256/Binary_To_BCD.v\n             data/full_repos/permissive/52714256/GYRACC/src/ACC,data/full_repos/permissive/52714256/Binary_To_BCD.sv\n             Binary_To_BCD\n             Binary_To_BCD.v\n             Binary_To_BCD.sv\n             obj_dir/Binary_To_BCD\n             obj_dir/Binary_To_BCD.v\n             obj_dir/Binary_To_BCD.sv\n%Error: Exiting due to 1 error(s)\n"
module Format_Data(
		CLK,
		DCLK,
		RST,
		DIN,
		BCDOUT
);





   input           CLK;
   input           DCLK;
   input           RST;
   input wire [9:0] DIN;
   output reg [15:0] BCDOUT;
   



   

   

   wire [8:0]      inputBCD;
   wire [15:0]     outputBCD;
   



   
   	
   	reg [16:0] tmpDIVIDEND;
   	reg [9:0] unsigned_data;
   	always @(posedge CLK) begin
        unsigned_data <= (DIN[9] == 1'b1) ? ((~(DIN)) + 1'b1) : DIN;
        tmpDIVIDEND <= unsigned_data[8:0] * 8'd201;
    end
   

   assign inputBCD = {1'b0, tmpDIVIDEND[16:9]};





   Binary_To_BCD BtoBCD(
				.CLK(CLK),
				.RST(RST),
				.START(DCLK),
				.BIN(unsigned_data),
				.BCDOUT(outputBCD)
	);
   


   always @(posedge CLK) begin
        if (DIN[9]) begin
            BCDOUT <= {4'hF, outputBCD[11:0]};
        end
        else begin
            BCDOUT <= {4'hA, outputBCD[11:0]};
        end
   end
   
endmodule
module Format_Data(
		CLK,
		DCLK,
		RST,
		DIN,
		BCDOUT
);






   input           CLK;
   input           DCLK;
   input           RST;
   input wire [9:0] DIN;
   output reg [15:0] BCDOUT;
   



   

   

   wire [8:0]      inputBCD;
   wire [15:0]     outputBCD;
   



   
   	
   	reg [16:0] tmpDIVIDEND;
   	reg [9:0] unsigned_data;
   	always @(posedge CLK) begin
        unsigned_data <= (DIN[9] == 1'b1) ? ((~(DIN)) + 1'b1) : DIN;
        tmpDIVIDEND <= unsigned_data[8:0] * 8'd201;
    end
   

   assign inputBCD = {1'b0, tmpDIVIDEND[16:9]};





   Binary_To_BCD BtoBCD(
				.CLK(CLK),
				.RST(RST),
				.START(DCLK),
				.BIN(unsigned_data),
				.BCDOUT(outputBCD)
	);
   


   always @(posedge CLK) begin
        if (DIN[9]) begin
            BCDOUT <= {4'hF, outputBCD[11:0]};
        end
        else begin
            BCDOUT <= {4'hA, outputBCD[11:0]};
        end
   end
   
endmodule