data/full_repos/permissive/520811519/rtl/final_video/IkariWarriorsCore_FinalVideo.sv
1: b"%Error: data/full_repos/permissive/520811519/rtl/final_video/IkariWarriorsCore_FinalVideo.sv:34: Cannot find file containing module: 'DFF_pseudoAsyncClrPre'\n    DFF_pseudoAsyncClrPre #(.W(1)) G4 (\n    ^~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/520811519/rtl/final_video,data/full_repos/permissive/520811519/DFF_pseudoAsyncClrPre\n             data/full_repos/permissive/520811519/rtl/final_video,data/full_repos/permissive/520811519/DFF_pseudoAsyncClrPre.v\n             data/full_repos/permissive/520811519/rtl/final_video,data/full_repos/permissive/520811519/DFF_pseudoAsyncClrPre.sv\n             DFF_pseudoAsyncClrPre\n             DFF_pseudoAsyncClrPre.v\n             DFF_pseudoAsyncClrPre.sv\n             obj_dir/DFF_pseudoAsyncClrPre\n             obj_dir/DFF_pseudoAsyncClrPre.v\n             obj_dir/DFF_pseudoAsyncClrPre.sv\n%Error: data/full_repos/permissive/520811519/rtl/final_video/IkariWarriorsCore_FinalVideo.sv:65: Cannot find file containing module: 'ttl_74298_sync'\n    ttl_74298_sync P1 (.VIDEO_RSTn(VIDEO_RSTn), .clk(clk), .Cen(CK1n), .WS(G3n), .A(L1D_ena[3:0]), .B(SD_ena[3:0]), .Q(SLD[3:0]));\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/final_video/IkariWarriorsCore_FinalVideo.sv:66: Cannot find file containing module: 'ttl_74298_sync'\n    ttl_74298_sync P2 (.VIDEO_RSTn(VIDEO_RSTn), .clk(clk), .Cen(CK1n), .WS(G3n), .A(L1D_ena[7:4]), .B({1'b0,SD_ena[6:4]}), .Q(SLD[7:4]));\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/final_video/IkariWarriorsCore_FinalVideo.sv:72: Cannot find file containing module: 'A5004_3'\n    A5004_3 N2(\n    ^~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/final_video/IkariWarriorsCore_FinalVideo.sv:101: Cannot find file containing module: 'ttl_74153'\n    ttl_74153 #(.DELAY_RISE(0), .DELAY_FALL(0)) N1\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/final_video/IkariWarriorsCore_FinalVideo.sv:108: Cannot find file containing module: 'ttl_74153'\n    ttl_74153 #(.DELAY_RISE(0), .DELAY_FALL(0)) M1\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/final_video/IkariWarriorsCore_FinalVideo.sv:115: Cannot find file containing module: 'ttl_74153'\n    ttl_74153 #(.DELAY_RISE(0), .DELAY_FALL(0)) L2\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/final_video/IkariWarriorsCore_FinalVideo.sv:122: Cannot find file containing module: 'ttl_74153'\n    ttl_74153 #(.DELAY_RISE(0), .DELAY_FALL(0)) L1\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/final_video/IkariWarriorsCore_FinalVideo.sv:131: Cannot find file containing module: 'ttl_74174_sync'\n    ttl_74174_sync K1\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/final_video/IkariWarriorsCore_FinalVideo.sv:141: Cannot find file containing module: 'ttl_74174_sync'\n    ttl_74174_sync K2\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/final_video/IkariWarriorsCore_FinalVideo.sv:161: Cannot find file containing module: 'prom_1K_4bit'\n    prom_1K_4bit H1_R\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/final_video/IkariWarriorsCore_FinalVideo.sv:173: Cannot find file containing module: 'prom_1K_4bit'\n    prom_1K_4bit J2_G\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/final_video/IkariWarriorsCore_FinalVideo.sv:185: Cannot find file containing module: 'prom_1K_4bit'\n    prom_1K_4bit J1_B\n    ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/final_video/IkariWarriorsCore_FinalVideo.sv:198: Cannot find file containing module: 'ttl_74174_sync'\n    ttl_74174_sync G2\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/520811519/rtl/final_video/IkariWarriorsCore_FinalVideo.sv:208: Cannot find file containing module: 'ttl_74174_sync'\n    ttl_74174_sync H2\n    ^~~~~~~~~~~~~~\n%Error: Exiting due to 15 error(s)\n"
module IkariWarriorsCore_FinalVideo(

    input  wire VIDEO_RSTn,
    input wire clk,
    input wire HD8,
    input wire H1,
    input wire CK1,
    input wire CK1n,

    input wire         [24:0] ioctl_addr,
    input wire         [7:0] ioctl_data,
    input wire               ioctl_wr,

    input wire [3:0] layer_ena_dbg,
    input wire [7:0] L1D,
    input wire [6:0] L2D,
    input wire [6:0] SD,
    input wire [6:0] B1D,


    input wire DISP,
    output logic [3:0] R,
    output logic [3:0] G,
    output logic [3:0] B
);
    logic G4_Qn;

    DFF_pseudoAsyncClrPre #(.W(1)) G4 (
        .clk(clk),
        .rst(~VIDEO_RSTn),
        .din(HD8),
        .q(),
        .qn(G4_Qn),
        .set(1'b0),
        .clr(1'b0),
        .cen(H1)
    );

    logic [6:0] SD_ena;
    assign SD_ena = (layer_ena_dbg[0]) ? SD : 7'h7f;
        
    logic [6:0] B1D_ena;
    assign B1D_ena = (layer_ena_dbg[1]) ? B1D : 7'h7f; 

    logic [7:0] L1D_ena;
    assign L1D_ena = (layer_ena_dbg[2]) ? L1D : {1'b0,7'h7f};

    logic [6:0] L2D_ena;
    assign L2D_ena = (layer_ena_dbg[3]) ? L2D : 7'h7f;



    logic G3n;
    assign G3n = ~(G4_Qn & SD_ena[3] & SD_ena[2] & SD_ena[1]);

    logic [7:0] SLD;
    logic [7:0] SLBD;

    ttl_74298_sync P1 (.VIDEO_RSTn(VIDEO_RSTn), .clk(clk), .Cen(CK1n), .WS(G3n), .A(L1D_ena[3:0]), .B(SD_ena[3:0]), .Q(SLD[3:0]));
    ttl_74298_sync P2 (.VIDEO_RSTn(VIDEO_RSTn), .clk(clk), .Cen(CK1n), .WS(G3n), .A(L1D_ena[7:4]), .B({1'b0,SD_ena[6:4]}), .Q(SLD[7:4]));

	 logic SD30AND;
    logic SD30AND_r;
    logic SD31_r;
    logic COLBANK3, COLBANK4, COLBANK5, LAYER_SELA, LAYER_SELB;
    A5004_3 N2(
    .SD31(G3n),
    .SD0(SD_ena[0]),
    .SLD7(SLD[7]),
    .SLD0(SLD[0]),
    .SLD1(SLD[1]),
    .SLD2(SLD[2]),
    .L2D0(L2D_ena[0]),
    .L2D1(L2D_ena[1]),
    .L2D2(L2D_ena[2]),
    .i11(1'b1),
    .SD31_r(SD31_r),
    .SD30_ANDr(SD30AND_r),

    .COLBANK5(COLBANK5),
    .LAYER_SELA(LAYER_SELA),
    .LAYER_SELB(LAYER_SELB),
    .COLBANK3(COLBANK3),
    .COLBANK4(COLBANK4),
    .SD30_AND(SD30AND)
    );
	 
    logic COLBANK5n, LAYER_SELAn;
    assign COLBANK5n = ~COLBANK5;
    assign LAYER_SELAn = ~LAYER_SELA;




    ttl_74153 #(.DELAY_RISE(0), .DELAY_FALL(0)) N1
    (
        .Enable_bar({2{1'b0}}),
        .Select({LAYER_SELB,LAYER_SELAn}),
        .A_2D({{L2D_ena[1], SLD[1], B1D_ena[1], B1D_ena[1]},{L2D_ena[0], SLD[0], B1D_ena[0], B1D_ena[0]}}),
        .Y(SLBD[1:0])
    );
    ttl_74153 #(.DELAY_RISE(0), .DELAY_FALL(0)) M1
    (
        .Enable_bar({2{1'b0}}),
        .Select({LAYER_SELB,LAYER_SELAn}),
        .A_2D({{L2D_ena[3], SLD[3], B1D_ena[3], B1D_ena[3]},{L2D_ena[2], SLD[2], B1D_ena[2], B1D_ena[2]}}),
        .Y(SLBD[3:2])
    );
    ttl_74153 #(.DELAY_RISE(0), .DELAY_FALL(0)) L2
    (
        .Enable_bar({2{1'b0}}),
        .Select({LAYER_SELB,LAYER_SELAn}),
        .A_2D({{L2D_ena[5], SLD[5], B1D_ena[5], B1D_ena[5]},{L2D_ena[4], SLD[4], B1D_ena[4], B1D_ena[4]}}),
        .Y(SLBD[5:4])
    );
    ttl_74153 #(.DELAY_RISE(0), .DELAY_FALL(0)) L1
    (
        .Enable_bar({2{1'b0}}),
        .Select({LAYER_SELB,LAYER_SELAn}),
        .A_2D({{4'b1111},{L2D_ena[6], SLD[6], B1D_ena[6], B1D_ena[6]}}),
        .Y(SLBD[7:6])
    );

    logic [9:0] COLOR_IDX;
    ttl_74174_sync K1
    (
        .Reset_n(VIDEO_RSTn),
        .Clk(clk),
        .Cen(CK1),
        .Clr_n(1'b1),
        .D(SLBD[5:0]),
        .Q(COLOR_IDX[5:0])
    );

    ttl_74174_sync K2
    (
        .Reset_n(VIDEO_RSTn),
        .Clk(clk),
        .Cen(CK1),
        .Clr_n(1'b1),
        .D({G3n,     SD30AND, COLBANK5n, COLBANK4, COLBANK3, SLBD[6]}),
        .Q({SD31_r, SD30AND_r, COLOR_IDX[9:6]})
    );


    wire H1_R_cs = (ioctl_addr >= 25'hD0_000) & (ioctl_addr < 25'hD0_400);
    wire J2_G_cs = (ioctl_addr >= 25'hD0_400) & (ioctl_addr < 25'hD0_800); 
    wire J1_B_cs = (ioctl_addr >= 25'hD0_800) & (ioctl_addr < 25'hD0_C00);
    

    logic [3:0] R4_D;
    logic [3:0] G4_D;
    logic [3:0] B4_D;

    prom_1K_4bit H1_R
    (
        .ADDR(COLOR_IDX),
        .CLK(clk),
        .DATA(R4_D),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data[3:0]),
        .CS_DL(H1_R_cs),
        .WR(ioctl_wr)
    );

    prom_1K_4bit J2_G
    (
        .ADDR(COLOR_IDX),
        .CLK(clk),
        .DATA(G4_D),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data[3:0]),
        .CS_DL(J2_G_cs),
        .WR(ioctl_wr)
    );

    prom_1K_4bit J1_B
    (
        .ADDR(COLOR_IDX),
        .CLK(clk),
        .DATA(B4_D),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data[3:0]),
        .CS_DL(J1_B_cs),
        .WR(ioctl_wr)
    );


    ttl_74174_sync G2
    (
        .Reset_n(VIDEO_RSTn),
        .Clk(clk),
        .Cen(CK1),
        .Clr_n(DISP),
        .D({R4_D[3:0],G4_D[1:0]}),
        .Q({R[3:0], G[1:0]})
    );

    ttl_74174_sync H2
    (
        .Reset_n(VIDEO_RSTn),
        .Clk(clk),
        .Cen(CK1),
        .Clr_n(DISP),
        .D({G4_D[3:2],B4_D[3:0]}),
        .Q({G[3:2], B[3:0]})
    );
endmodule
module IkariWarriorsCore_FinalVideo(

    input  wire VIDEO_RSTn,
    input wire clk,
    input wire HD8,
    input wire H1,
    input wire CK1,
    input wire CK1n,

    input wire         [24:0] ioctl_addr,
    input wire         [7:0] ioctl_data,
    input wire               ioctl_wr,

    input wire [3:0] layer_ena_dbg,
    input wire [7:0] L1D,
    input wire [6:0] L2D,
    input wire [6:0] SD,
    input wire [6:0] B1D,


    input wire DISP,
    output logic [3:0] R,
    output logic [3:0] G,
    output logic [3:0] B
);

    logic G4_Qn;

    DFF_pseudoAsyncClrPre #(.W(1)) G4 (
        .clk(clk),
        .rst(~VIDEO_RSTn),
        .din(HD8),
        .q(),
        .qn(G4_Qn),
        .set(1'b0),
        .clr(1'b0),
        .cen(H1)
    );

    logic [6:0] SD_ena;
    assign SD_ena = (layer_ena_dbg[0]) ? SD : 7'h7f;
        
    logic [6:0] B1D_ena;
    assign B1D_ena = (layer_ena_dbg[1]) ? B1D : 7'h7f; 

    logic [7:0] L1D_ena;
    assign L1D_ena = (layer_ena_dbg[2]) ? L1D : {1'b0,7'h7f};

    logic [6:0] L2D_ena;
    assign L2D_ena = (layer_ena_dbg[3]) ? L2D : 7'h7f;



    logic G3n;
    assign G3n = ~(G4_Qn & SD_ena[3] & SD_ena[2] & SD_ena[1]);

    logic [7:0] SLD;
    logic [7:0] SLBD;

    ttl_74298_sync P1 (.VIDEO_RSTn(VIDEO_RSTn), .clk(clk), .Cen(CK1n), .WS(G3n), .A(L1D_ena[3:0]), .B(SD_ena[3:0]), .Q(SLD[3:0]));
    ttl_74298_sync P2 (.VIDEO_RSTn(VIDEO_RSTn), .clk(clk), .Cen(CK1n), .WS(G3n), .A(L1D_ena[7:4]), .B({1'b0,SD_ena[6:4]}), .Q(SLD[7:4]));

	 logic SD30AND;
    logic SD30AND_r;
    logic SD31_r;
    logic COLBANK3, COLBANK4, COLBANK5, LAYER_SELA, LAYER_SELB;
    A5004_3 N2(
    .SD31(G3n),
    .SD0(SD_ena[0]),
    .SLD7(SLD[7]),
    .SLD0(SLD[0]),
    .SLD1(SLD[1]),
    .SLD2(SLD[2]),
    .L2D0(L2D_ena[0]),
    .L2D1(L2D_ena[1]),
    .L2D2(L2D_ena[2]),
    .i11(1'b1),
    .SD31_r(SD31_r),
    .SD30_ANDr(SD30AND_r),

    .COLBANK5(COLBANK5),
    .LAYER_SELA(LAYER_SELA),
    .LAYER_SELB(LAYER_SELB),
    .COLBANK3(COLBANK3),
    .COLBANK4(COLBANK4),
    .SD30_AND(SD30AND)
    );
	 
    logic COLBANK5n, LAYER_SELAn;
    assign COLBANK5n = ~COLBANK5;
    assign LAYER_SELAn = ~LAYER_SELA;




    ttl_74153 #(.DELAY_RISE(0), .DELAY_FALL(0)) N1
    (
        .Enable_bar({2{1'b0}}),
        .Select({LAYER_SELB,LAYER_SELAn}),
        .A_2D({{L2D_ena[1], SLD[1], B1D_ena[1], B1D_ena[1]},{L2D_ena[0], SLD[0], B1D_ena[0], B1D_ena[0]}}),
        .Y(SLBD[1:0])
    );
    ttl_74153 #(.DELAY_RISE(0), .DELAY_FALL(0)) M1
    (
        .Enable_bar({2{1'b0}}),
        .Select({LAYER_SELB,LAYER_SELAn}),
        .A_2D({{L2D_ena[3], SLD[3], B1D_ena[3], B1D_ena[3]},{L2D_ena[2], SLD[2], B1D_ena[2], B1D_ena[2]}}),
        .Y(SLBD[3:2])
    );
    ttl_74153 #(.DELAY_RISE(0), .DELAY_FALL(0)) L2
    (
        .Enable_bar({2{1'b0}}),
        .Select({LAYER_SELB,LAYER_SELAn}),
        .A_2D({{L2D_ena[5], SLD[5], B1D_ena[5], B1D_ena[5]},{L2D_ena[4], SLD[4], B1D_ena[4], B1D_ena[4]}}),
        .Y(SLBD[5:4])
    );
    ttl_74153 #(.DELAY_RISE(0), .DELAY_FALL(0)) L1
    (
        .Enable_bar({2{1'b0}}),
        .Select({LAYER_SELB,LAYER_SELAn}),
        .A_2D({{4'b1111},{L2D_ena[6], SLD[6], B1D_ena[6], B1D_ena[6]}}),
        .Y(SLBD[7:6])
    );

    logic [9:0] COLOR_IDX;
    ttl_74174_sync K1
    (
        .Reset_n(VIDEO_RSTn),
        .Clk(clk),
        .Cen(CK1),
        .Clr_n(1'b1),
        .D(SLBD[5:0]),
        .Q(COLOR_IDX[5:0])
    );

    ttl_74174_sync K2
    (
        .Reset_n(VIDEO_RSTn),
        .Clk(clk),
        .Cen(CK1),
        .Clr_n(1'b1),
        .D({G3n,     SD30AND, COLBANK5n, COLBANK4, COLBANK3, SLBD[6]}),
        .Q({SD31_r, SD30AND_r, COLOR_IDX[9:6]})
    );


    wire H1_R_cs = (ioctl_addr >= 25'hD0_000) & (ioctl_addr < 25'hD0_400);
    wire J2_G_cs = (ioctl_addr >= 25'hD0_400) & (ioctl_addr < 25'hD0_800); 
    wire J1_B_cs = (ioctl_addr >= 25'hD0_800) & (ioctl_addr < 25'hD0_C00);
    

    logic [3:0] R4_D;
    logic [3:0] G4_D;
    logic [3:0] B4_D;

    prom_1K_4bit H1_R
    (
        .ADDR(COLOR_IDX),
        .CLK(clk),
        .DATA(R4_D),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data[3:0]),
        .CS_DL(H1_R_cs),
        .WR(ioctl_wr)
    );

    prom_1K_4bit J2_G
    (
        .ADDR(COLOR_IDX),
        .CLK(clk),
        .DATA(G4_D),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data[3:0]),
        .CS_DL(J2_G_cs),
        .WR(ioctl_wr)
    );

    prom_1K_4bit J1_B
    (
        .ADDR(COLOR_IDX),
        .CLK(clk),
        .DATA(B4_D),
        .ADDR_DL(ioctl_addr),
        .CLK_DL(clk),
        .DATA_IN(ioctl_data[3:0]),
        .CS_DL(J1_B_cs),
        .WR(ioctl_wr)
    );


    ttl_74174_sync G2
    (
        .Reset_n(VIDEO_RSTn),
        .Clk(clk),
        .Cen(CK1),
        .Clr_n(DISP),
        .D({R4_D[3:0],G4_D[1:0]}),
        .Q({R[3:0], G[1:0]})
    );

    ttl_74174_sync H2
    (
        .Reset_n(VIDEO_RSTn),
        .Clk(clk),
        .Cen(CK1),
        .Clr_n(DISP),
        .D({G4_D[3:2],B4_D[3:0]}),
        .Q({G[3:2], B[3:0]})
    );
endmodule