data/full_repos/permissive/439731184/sum_arbitrary_size.v
1: b'%Error: data/full_repos/permissive/439731184/sum_arbitrary_size.v:45: Unsupported or unknown PLI call: $urandom\n    r = $urandom;\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/439731184/sum_arbitrary_size.v:40: Unsupported: Ignoring delay on this delayed statement.\nalways #1 begin\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/439731184/sum_arbitrary_size.v:51: Unsupported or unknown PLI call: $urandom\n    $urandom(SEED);\n    ^~~~~~~~\n%Error: data/full_repos/permissive/439731184/sum_arbitrary_size.v:53: Unsupported or unknown PLI call: $monitor\n    $monitor("%h\\t%h\\t%h\\t%h\\t%h\\t%b", $time, a, b, c, d, e);\n    ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/439731184/sum_arbitrary_size.v:54: Unsupported: Ignoring delay on this delayed statement.\n    #(N_TESTS) $display("TEST PASSED");\n    ^\n%Error: Exiting due to 3 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module add_tb();

parameter N_BITS = 8;

reg [N_BITS-1:0] a = 8'b00100011, b = 8'b00010010;
wire [N_BITS:0] c, d;
integer r, SEED = 35, N_TESTS = 10000;

add #(N_BITS) A (a, b, c);
assign d = a+b;
assign e = d == c;

always #1 begin
    if (e !== 1) begin
        $display("TEST FAILED");
        $finish;
    end
    r = $urandom;
    a = r;
    b = r >> N_BITS;
end

initial begin
    $urandom(SEED);
    $display("time\ta\tb\tc\ta+b\tok");
    $monitor("%h\t%h\t%h\t%h\t%h\t%b", $time, a, b, c, d, e);
    #(N_TESTS) $display("TEST PASSED");
    $finish;
end

endmodule
module add_tb();


parameter N_BITS = 8;

reg [N_BITS-1:0] a = 8'b00100011, b = 8'b00010010;
wire [N_BITS:0] c, d;
integer r, SEED = 35, N_TESTS = 10000;

add #(N_BITS) A (a, b, c);
assign d = a+b;
assign e = d == c;

always #1 begin
    if (e !== 1) begin
        $display("TEST FAILED");
        $finish;
    end
    r = $urandom;
    a = r;
    b = r >> N_BITS;
end

initial begin
    $urandom(SEED);
    $display("time\ta\tb\tc\ta+b\tok");
    $monitor("%h\t%h\t%h\t%h\t%h\t%b", $time, a, b, c, d, e);
    #(N_TESTS) $display("TEST PASSED");
    $finish;
end

endmodule