data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/zemi3_tb.sv
1: b'%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/zemi3_tb.sv:1: Cannot find include file: syn_tb_defines.vh\n`include "syn_tb_defines.vh" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb,data/full_repos/permissive/509468557/syn_tb_defines.vh\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb,data/full_repos/permissive/509468557/syn_tb_defines.vh.v\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb,data/full_repos/permissive/509468557/syn_tb_defines.vh.sv\n             syn_tb_defines.vh\n             syn_tb_defines.vh.v\n             syn_tb_defines.vh.sv\n             obj_dir/syn_tb_defines.vh\n             obj_dir/syn_tb_defines.vh.v\n             obj_dir/syn_tb_defines.vh.sv\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/zemi3_tb.sv:8: Define or directive not defined: \'`MSEQ_CMD_SIZE\'\n  input [`MSEQ_CMD_SIZE-1:0] curr_cmd\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/zemi3_tb.sv:23: Define or directive not defined: \'`AXI_ADDR_WIDTH\'\n                                            input bit   [`AXI_ADDR_WIDTH-1:0] start_addr,\n                                                         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/zemi3_tb.sv:24: Define or directive not defined: \'`AXI_ADDR_WIDTH\'\n                                            input bit   [`AXI_ADDR_WIDTH-1:0] end_addr        );\n                                                         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/zemi3_tb.sv:29: Define or directive not defined: \'`AXI_ADDR_WIDTH\'\n                                            input bit   [`AXI_ADDR_WIDTH-1:0] start_addr,\n                                                         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/zemi3_tb.sv:30: Define or directive not defined: \'`AXI_ADDR_WIDTH\'\n                                            input bit   [`AXI_ADDR_WIDTH-1:0] end_addr        );\n                                                         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/zemi3_tb.sv:40: syntax error, unexpected \'@\'\n    repeat (1000) @(posedge clk);\n                  ^\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/zemi3_tb.sv:53: Define or directive not defined: \'`MSEQ_FILENAME_BITS\'\n        z_readmemh(curr_cmd[`MSEQ_FILENAME_BITS], "top.slave_mem_wrap.syn_mem.memory", curr_cmd[`MSEQ_MEM_ADDR_BITS]/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM), (curr_cmd[`MSEQ_MEM_ADDR_BITS] + curr_cmd[`MSEQ_MEM_SIZE_BITS])/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM) - 1);\n                            ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/zemi3_tb.sv:53: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n        z_readmemh(curr_cmd[`MSEQ_FILENAME_BITS], "top.slave_mem_wrap.syn_mem.memory", curr_cmd[`MSEQ_MEM_ADDR_BITS]/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM), (curr_cmd[`MSEQ_MEM_ADDR_BITS] + curr_cmd[`MSEQ_MEM_SIZE_BITS])/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM) - 1);\n                                               ^\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/zemi3_tb.sv:53: Define or directive not defined: \'`MSEQ_MEM_ADDR_BITS\'\n        z_readmemh(curr_cmd[`MSEQ_FILENAME_BITS], "top.slave_mem_wrap.syn_mem.memory", curr_cmd[`MSEQ_MEM_ADDR_BITS]/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM), (curr_cmd[`MSEQ_MEM_ADDR_BITS] + curr_cmd[`MSEQ_MEM_SIZE_BITS])/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM) - 1);\n                                                                                                ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/zemi3_tb.sv:53: Define or directive not defined: \'`ZRM_CHANGE_BYTES\'\n        z_readmemh(curr_cmd[`MSEQ_FILENAME_BITS], "top.slave_mem_wrap.syn_mem.memory", curr_cmd[`MSEQ_MEM_ADDR_BITS]/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM), (curr_cmd[`MSEQ_MEM_ADDR_BITS] + curr_cmd[`MSEQ_MEM_SIZE_BITS])/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM) - 1);\n                                                                                                                      ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/zemi3_tb.sv:53: Define or directive not defined: \'`DLA_ADDR_START\'\n        z_readmemh(curr_cmd[`MSEQ_FILENAME_BITS], "top.slave_mem_wrap.syn_mem.memory", curr_cmd[`MSEQ_MEM_ADDR_BITS]/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM), (curr_cmd[`MSEQ_MEM_ADDR_BITS] + curr_cmd[`MSEQ_MEM_SIZE_BITS])/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM) - 1);\n                                                                                                                                            ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/zemi3_tb.sv:53: Define or directive not defined: \'`ZRM_LOG2_MEM\'\n        z_readmemh(curr_cmd[`MSEQ_FILENAME_BITS], "top.slave_mem_wrap.syn_mem.memory", curr_cmd[`MSEQ_MEM_ADDR_BITS]/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM), (curr_cmd[`MSEQ_MEM_ADDR_BITS] + curr_cmd[`MSEQ_MEM_SIZE_BITS])/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM) - 1);\n                                                                                                                                                               ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/zemi3_tb.sv:53: Define or directive not defined: \'`MSEQ_MEM_ADDR_BITS\'\n        z_readmemh(curr_cmd[`MSEQ_FILENAME_BITS], "top.slave_mem_wrap.syn_mem.memory", curr_cmd[`MSEQ_MEM_ADDR_BITS]/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM), (curr_cmd[`MSEQ_MEM_ADDR_BITS] + curr_cmd[`MSEQ_MEM_SIZE_BITS])/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM) - 1);\n                                                                                                                                                                                         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/zemi3_tb.sv:53: Define or directive not defined: \'`MSEQ_MEM_SIZE_BITS\'\n        z_readmemh(curr_cmd[`MSEQ_FILENAME_BITS], "top.slave_mem_wrap.syn_mem.memory", curr_cmd[`MSEQ_MEM_ADDR_BITS]/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM), (curr_cmd[`MSEQ_MEM_ADDR_BITS] + curr_cmd[`MSEQ_MEM_SIZE_BITS])/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM) - 1);\n                                                                                                                                                                                                                         ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/zemi3_tb.sv:53: Define or directive not defined: \'`ZRM_CHANGE_BYTES\'\n        z_readmemh(curr_cmd[`MSEQ_FILENAME_BITS], "top.slave_mem_wrap.syn_mem.memory", curr_cmd[`MSEQ_MEM_ADDR_BITS]/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM), (curr_cmd[`MSEQ_MEM_ADDR_BITS] + curr_cmd[`MSEQ_MEM_SIZE_BITS])/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM) - 1);\n                                                                                                                                                                                                                                                ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/zemi3_tb.sv:53: Define or directive not defined: \'`DLA_ADDR_START\'\n        z_readmemh(curr_cmd[`MSEQ_FILENAME_BITS], "top.slave_mem_wrap.syn_mem.memory", curr_cmd[`MSEQ_MEM_ADDR_BITS]/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM), (curr_cmd[`MSEQ_MEM_ADDR_BITS] + curr_cmd[`MSEQ_MEM_SIZE_BITS])/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM) - 1);\n                                                                                                                                                                                                                                                                      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/zemi3_tb.sv:53: Define or directive not defined: \'`ZRM_LOG2_MEM\'\n        z_readmemh(curr_cmd[`MSEQ_FILENAME_BITS], "top.slave_mem_wrap.syn_mem.memory", curr_cmd[`MSEQ_MEM_ADDR_BITS]/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM), (curr_cmd[`MSEQ_MEM_ADDR_BITS] + curr_cmd[`MSEQ_MEM_SIZE_BITS])/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM) - 1);\n                                                                                                                                                                                                                                                                                         ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/zemi3_tb.sv:56: Define or directive not defined: \'`MSEQ_FILENAME_BITS\'\n        z_writememh(curr_cmd[`MSEQ_FILENAME_BITS], "top.slave_mem_wrap.syn_mem.memory", curr_cmd[`MSEQ_MEM_ADDR_BITS]/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM), (curr_cmd[`MSEQ_MEM_ADDR_BITS] + curr_cmd[`MSEQ_MEM_SIZE_BITS])/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM) - 1);\n                             ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/zemi3_tb.sv:56: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n        z_writememh(curr_cmd[`MSEQ_FILENAME_BITS], "top.slave_mem_wrap.syn_mem.memory", curr_cmd[`MSEQ_MEM_ADDR_BITS]/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM), (curr_cmd[`MSEQ_MEM_ADDR_BITS] + curr_cmd[`MSEQ_MEM_SIZE_BITS])/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM) - 1);\n                                                ^\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/zemi3_tb.sv:56: Define or directive not defined: \'`MSEQ_MEM_ADDR_BITS\'\n        z_writememh(curr_cmd[`MSEQ_FILENAME_BITS], "top.slave_mem_wrap.syn_mem.memory", curr_cmd[`MSEQ_MEM_ADDR_BITS]/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM), (curr_cmd[`MSEQ_MEM_ADDR_BITS] + curr_cmd[`MSEQ_MEM_SIZE_BITS])/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM) - 1);\n                                                                                                 ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/zemi3_tb.sv:56: Define or directive not defined: \'`ZRM_CHANGE_BYTES\'\n        z_writememh(curr_cmd[`MSEQ_FILENAME_BITS], "top.slave_mem_wrap.syn_mem.memory", curr_cmd[`MSEQ_MEM_ADDR_BITS]/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM), (curr_cmd[`MSEQ_MEM_ADDR_BITS] + curr_cmd[`MSEQ_MEM_SIZE_BITS])/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM) - 1);\n                                                                                                                       ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/zemi3_tb.sv:56: Define or directive not defined: \'`DLA_ADDR_START\'\n        z_writememh(curr_cmd[`MSEQ_FILENAME_BITS], "top.slave_mem_wrap.syn_mem.memory", curr_cmd[`MSEQ_MEM_ADDR_BITS]/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM), (curr_cmd[`MSEQ_MEM_ADDR_BITS] + curr_cmd[`MSEQ_MEM_SIZE_BITS])/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM) - 1);\n                                                                                                                                             ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/zemi3_tb.sv:56: Define or directive not defined: \'`ZRM_LOG2_MEM\'\n        z_writememh(curr_cmd[`MSEQ_FILENAME_BITS], "top.slave_mem_wrap.syn_mem.memory", curr_cmd[`MSEQ_MEM_ADDR_BITS]/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM), (curr_cmd[`MSEQ_MEM_ADDR_BITS] + curr_cmd[`MSEQ_MEM_SIZE_BITS])/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM) - 1);\n                                                                                                                                                                ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/zemi3_tb.sv:56: Define or directive not defined: \'`MSEQ_MEM_ADDR_BITS\'\n        z_writememh(curr_cmd[`MSEQ_FILENAME_BITS], "top.slave_mem_wrap.syn_mem.memory", curr_cmd[`MSEQ_MEM_ADDR_BITS]/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM), (curr_cmd[`MSEQ_MEM_ADDR_BITS] + curr_cmd[`MSEQ_MEM_SIZE_BITS])/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM) - 1);\n                                                                                                                                                                                          ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/zemi3_tb.sv:56: Define or directive not defined: \'`MSEQ_MEM_SIZE_BITS\'\n        z_writememh(curr_cmd[`MSEQ_FILENAME_BITS], "top.slave_mem_wrap.syn_mem.memory", curr_cmd[`MSEQ_MEM_ADDR_BITS]/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM), (curr_cmd[`MSEQ_MEM_ADDR_BITS] + curr_cmd[`MSEQ_MEM_SIZE_BITS])/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM) - 1);\n                                                                                                                                                                                                                          ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/zemi3_tb.sv:56: Define or directive not defined: \'`ZRM_CHANGE_BYTES\'\n        z_writememh(curr_cmd[`MSEQ_FILENAME_BITS], "top.slave_mem_wrap.syn_mem.memory", curr_cmd[`MSEQ_MEM_ADDR_BITS]/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM), (curr_cmd[`MSEQ_MEM_ADDR_BITS] + curr_cmd[`MSEQ_MEM_SIZE_BITS])/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM) - 1);\n                                                                                                                                                                                                                                                 ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/zemi3_tb.sv:56: Define or directive not defined: \'`DLA_ADDR_START\'\n        z_writememh(curr_cmd[`MSEQ_FILENAME_BITS], "top.slave_mem_wrap.syn_mem.memory", curr_cmd[`MSEQ_MEM_ADDR_BITS]/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM), (curr_cmd[`MSEQ_MEM_ADDR_BITS] + curr_cmd[`MSEQ_MEM_SIZE_BITS])/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM) - 1);\n                                                                                                                                                                                                                                                                       ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/zemi3_tb.sv:56: Define or directive not defined: \'`ZRM_LOG2_MEM\'\n        z_writememh(curr_cmd[`MSEQ_FILENAME_BITS], "top.slave_mem_wrap.syn_mem.memory", curr_cmd[`MSEQ_MEM_ADDR_BITS]/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM), (curr_cmd[`MSEQ_MEM_ADDR_BITS] + curr_cmd[`MSEQ_MEM_SIZE_BITS])/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM) - 1);\n                                                                                                                                                                                                                                                                                          ^~~~~~~~~~~~~\n%Error: Exiting due to 29 error(s)\n'
module zemi3_tb (
  input clk,
  output reg resetn,
  input dollar_finish,
  input [7:0] cs,
  input [`MSEQ_CMD_SIZE-1:0] curr_cmd
);

  parameter MSEQ_MEM_LD = 8'h20;
  parameter MSEQ_MEM_DMP = 8'h28;




  (* zemi3_stream = 0 *)
  import "DPI-C" function void z_initialize ();

  (* zemi3_stream = 0 *)
  import "DPI-C" function void z_readmemh ( input bit  [255:0] file_name,
                                            input bit [1023:0] dut_mem_path,
                                            input bit   [`AXI_ADDR_WIDTH-1:0] start_addr,
                                            input bit   [`AXI_ADDR_WIDTH-1:0] end_addr        );

  (* zemi3_stream = 0 *)
  import "DPI-C" function void z_writememh( input bit  [255:0] file_name,
                                            input bit [1023:0] dut_mem_path,
                                            input bit   [`AXI_ADDR_WIDTH-1:0] start_addr,
                                            input bit   [`AXI_ADDR_WIDTH-1:0] end_addr        );

  (* zemi3_stream = 0 *)
  import "DPI-C" function void z_finish ();

  initial begin
    z_initialize();
  end

  initial begin
    repeat (1000) @(posedge clk);
    resetn = 1;
  end

  always @(posedge clk) begin
    if (dollar_finish == 1'b1) begin
      z_finish();
    end
  end

  always @(posedge clk) begin
    case (cs)
      MSEQ_MEM_LD : begin
        z_readmemh(curr_cmd[`MSEQ_FILENAME_BITS], "top.slave_mem_wrap.syn_mem.memory", curr_cmd[`MSEQ_MEM_ADDR_BITS]/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM), (curr_cmd[`MSEQ_MEM_ADDR_BITS] + curr_cmd[`MSEQ_MEM_SIZE_BITS])/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM) - 1);
      end
      MSEQ_MEM_DMP : begin
        z_writememh(curr_cmd[`MSEQ_FILENAME_BITS], "top.slave_mem_wrap.syn_mem.memory", curr_cmd[`MSEQ_MEM_ADDR_BITS]/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM), (curr_cmd[`MSEQ_MEM_ADDR_BITS] + curr_cmd[`MSEQ_MEM_SIZE_BITS])/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM) - 1);
      end
    endcase
  end

endmodule
module zemi3_tb (
  input clk,
  output reg resetn,
  input dollar_finish,
  input [7:0] cs,
  input [`MSEQ_CMD_SIZE-1:0] curr_cmd
);


  parameter MSEQ_MEM_LD = 8'h20;
  parameter MSEQ_MEM_DMP = 8'h28;




  (* zemi3_stream = 0 *)
  import "DPI-C" function void z_initialize ();

  (* zemi3_stream = 0 *)
  import "DPI-C" function void z_readmemh ( input bit  [255:0] file_name,
                                            input bit [1023:0] dut_mem_path,
                                            input bit   [`AXI_ADDR_WIDTH-1:0] start_addr,
                                            input bit   [`AXI_ADDR_WIDTH-1:0] end_addr        );

  (* zemi3_stream = 0 *)
  import "DPI-C" function void z_writememh( input bit  [255:0] file_name,
                                            input bit [1023:0] dut_mem_path,
                                            input bit   [`AXI_ADDR_WIDTH-1:0] start_addr,
                                            input bit   [`AXI_ADDR_WIDTH-1:0] end_addr        );

  (* zemi3_stream = 0 *)
  import "DPI-C" function void z_finish ();

  initial begin
    z_initialize();
  end

  initial begin
    repeat (1000) @(posedge clk);
    resetn = 1;
  end

  always @(posedge clk) begin
    if (dollar_finish == 1'b1) begin
      z_finish();
    end
  end

  always @(posedge clk) begin
    case (cs)
      MSEQ_MEM_LD : begin
        z_readmemh(curr_cmd[`MSEQ_FILENAME_BITS], "top.slave_mem_wrap.syn_mem.memory", curr_cmd[`MSEQ_MEM_ADDR_BITS]/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM), (curr_cmd[`MSEQ_MEM_ADDR_BITS] + curr_cmd[`MSEQ_MEM_SIZE_BITS])/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM) - 1);
      end
      MSEQ_MEM_DMP : begin
        z_writememh(curr_cmd[`MSEQ_FILENAME_BITS], "top.slave_mem_wrap.syn_mem.memory", curr_cmd[`MSEQ_MEM_ADDR_BITS]/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM), (curr_cmd[`MSEQ_MEM_ADDR_BITS] + curr_cmd[`MSEQ_MEM_SIZE_BITS])/(`ZRM_CHANGE_BYTES) - (`DLA_ADDR_START >> `ZRM_LOG2_MEM) - 1);
      end
    endcase
  end

endmodule