data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v
1: b'%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:32: Cannot find include file: syn_tb_defines.vh\n`include "syn_tb_defines.vh" \n         ^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb,data/full_repos/permissive/509468557/syn_tb_defines.vh\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb,data/full_repos/permissive/509468557/syn_tb_defines.vh.v\n             data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb,data/full_repos/permissive/509468557/syn_tb_defines.vh.sv\n             syn_tb_defines.vh\n             syn_tb_defines.vh.v\n             syn_tb_defines.vh.sv\n             obj_dir/syn_tb_defines.vh\n             obj_dir/syn_tb_defines.vh.v\n             obj_dir/syn_tb_defines.vh.sv\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:65: Define or directive not defined: \'`AXI_SLAVE_BID_WIDTH\'\n    wire [`AXI_SLAVE_BID_WIDTH-1:0] axi_slave0_bid             ;\n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:68: Define or directive not defined: \'`DATABUS2MEM_WIDTH\'\n    wire   [`DATABUS2MEM_WIDTH-1:0] axi_slave0_rdata           ;\n            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:69: Define or directive not defined: \'`AXI_SLAVE_RID_WIDTH\'\n    wire [`AXI_SLAVE_RID_WIDTH-1:0] axi_slave0_rid             ;\n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:76: Define or directive not defined: \'`AXI_SLAVE_BID_WIDTH\'\n    wire [`AXI_SLAVE_BID_WIDTH-1:0] axi_slave1_bid             ;\n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:79: Define or directive not defined: \'`DATABUS2MEM_WIDTH\'\n    wire   [`DATABUS2MEM_WIDTH-1:0] axi_slave1_rdata           ;\n            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:80: Define or directive not defined: \'`AXI_SLAVE_RID_WIDTH\'\n    wire [`AXI_SLAVE_RID_WIDTH-1:0] axi_slave1_rid             ;\n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:85: Define or directive not defined: \'`AXI_ADDR_WIDTH\'\n    wire                     [`AXI_ADDR_WIDTH-1:0] axi_slave0_araddr          ;\n                              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:88: Define or directive not defined: \'`AXI_SLAVE_RID_WIDTH\'\n    wire [`AXI_SLAVE_RID_WIDTH-1:0] axi_slave0_arid            ;\n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:94: Define or directive not defined: \'`AXI_ADDR_WIDTH\'\n    wire                     [`AXI_ADDR_WIDTH-1:0] axi_slave0_awaddr          ;\n                              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:97: Define or directive not defined: \'`AXI_SLAVE_WID_WIDTH\'\n    wire [`AXI_SLAVE_WID_WIDTH-1:0] axi_slave0_awid            ;\n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:105: Define or directive not defined: \'`DATABUS2MEM_WIDTH\'\n    wire   [`DATABUS2MEM_WIDTH-1:0] axi_slave0_wdata           ;\n            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:107: Define or directive not defined: \'`DATABUS2MEM_WIDTH\'\n    wire [(`DATABUS2MEM_WIDTH/8)-1:0] axi_slave0_wstrb           ;\n           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:107: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n    wire [(`DATABUS2MEM_WIDTH/8)-1:0] axi_slave0_wstrb           ;\n                             ^\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:110: Define or directive not defined: \'`AXI_ADDR_WIDTH\'\n    wire                     [`AXI_ADDR_WIDTH-1:0] axi_slave1_araddr          ;\n                              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:113: Define or directive not defined: \'`AXI_SLAVE_RID_WIDTH\'\n    wire [`AXI_SLAVE_RID_WIDTH-1:0] axi_slave1_arid            ;\n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:119: Define or directive not defined: \'`AXI_ADDR_WIDTH\'\n    wire                     [`AXI_ADDR_WIDTH-1:0] axi_slave1_awaddr          ;\n                              ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:122: Define or directive not defined: \'`AXI_SLAVE_WID_WIDTH\'\n    wire [`AXI_SLAVE_WID_WIDTH-1:0] axi_slave1_awid            ;\n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:130: Define or directive not defined: \'`DATABUS2MEM_WIDTH\'\n    wire                    [`DATABUS2MEM_WIDTH-1:0] axi_slave1_wdata           ;\n                             ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:132: Define or directive not defined: \'`DATABUS2MEM_WIDTH\'\n    wire [(`DATABUS2MEM_WIDTH/8)-1:0] axi_slave1_wstrb           ;\n           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:132: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n    wire [(`DATABUS2MEM_WIDTH/8)-1:0] axi_slave1_wstrb           ;\n                             ^\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:325: syntax error, unexpected \'@\'\n  repeat (1000) @ (clk);\n                ^\n%Warning-STMTDLY: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:330: Unsupported: Ignoring delay on this delayed statement.\n always #(simulation_cycle/2) msc_clk_ip = ~msc_clk_ip;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:331: Unsupported: Ignoring delay on this delayed statement.\n always #(simulation_cycle_mem/2) mem_clk_fast = ~mem_clk_fast;\n        ^\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:686: Unsupported or unknown PLI call: $dumpfile\n$dumpfile("bench_pk_pass.vcd");\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:744: Unsupported: Ignoring delay on this delayed statement.\n           #(dump_start_time);\n           ^\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:751: Unsupported or unknown PLI call: $vcdplusfile\n            $vcdplusfile (vpd_dump_name);\n            ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:752: Unsupported or unknown PLI call: $vcdpluson\n            $vcdpluson;\n            ^~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:781: Unsupported or unknown PLI call: $set_gate_level_monitoring\n           $set_gate_level_monitoring("rtl_on");\n           ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:785: Unsupported or unknown PLI call: $set_toggle_region\n           $set_toggle_region("nvdla_top");\n           ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:791: Unsupported: wait statements\n           wait (trans_count !== {32{1\'bx}});\n           ^~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:793: Unsupported: wait statements\n           wait (trans_count >= saif_start_trans);\n           ^~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:798: Unsupported or unknown PLI call: $toggle_start\n           #10 $toggle_start;\n               ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:798: Unsupported: Ignoring delay on this delayed statement.\n           #10 $toggle_start;\n           ^\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:804: Unsupported: wait statements\n           wait (trans_count !== {32{1\'bx}});\n           ^~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:806: Unsupported: wait statements\n           wait (trans_count >= saif_end_trans);\n           ^~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:810: Unsupported or unknown PLI call: $toggle_stop\n             $toggle_stop;\n             ^~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:812: Unsupported: Ignoring delay on this delayed statement.\n           #10;\n           ^\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:820: Unsupported or unknown PLI call: $psprintf\n             full_saif_filename = $psprintf("%0s/smm0.snps.saif",input_dir);\n                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:825: Unsupported or unknown PLI call: $psprintf\n             full_saif_filename = $psprintf("%0s/top0.snps.saif",input_dir);\n                                  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:850: Unsupported: Ignoring delay on this delayed statement.\n           #(dump_start_time);\n           ^\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:854: Unsupported: wait statements\n           wait (trans_count !== {32{1\'bx}});\n           ^~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:856: Unsupported: wait statements\n           wait (trans_count >= dump_start_trans);\n           ^~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:865: Unsupported or unknown PLI call: $fsdbAutoSwitchDumpfile\n                $fsdbAutoSwitchDumpfile( 1000, dump_name, 20 );\n                ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:866: Unsupported or unknown PLI call: $fsdbDumpvars\n                $fsdbDumpvars("level=",0,top);\n                ^~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:873: Unsupported: Ignoring delay on this delayed statement.\n              #1;\n              ^\n%Error: data/full_repos/permissive/509468557/generators/nvdla/src/main/resources/hw/verif/synth_tb/tb_top.v:986: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n  $display( "(%0d) NVDLA_IP_ERROR : mem_bandwidth_window must be less than 1000)", $stime, );\n                                                                                           ^\n%Error: Exiting due to 40 error(s), 7 warning(s)\n'
function [55:0] Bin2Gray ;
   input [55:0] Bin;
   input [55:0] Bin_right_shift;
   begin
     Bin2Gray = Bin ^ Bin_right_shift;
   end
 endfunction
function [55:0] Bin2Gray ;

   input [55:0] Bin;
   input [55:0] Bin_right_shift;
   begin
     Bin2Gray = Bin ^ Bin_right_shift;
   end
 endfunction