data/full_repos/permissive/509468557/generators/testchipip/src/main/resources/testchipip/vsrc/plusarg_file_mem.sv
1: b"%Error: data/full_repos/permissive/509468557/generators/testchipip/src/main/resources/testchipip/vsrc/plusarg_file_mem.sv:22: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'PLUSARG'\n                                                                                                                            : ... In instance plusarg_file_mem\n    parameter string PLUSARG,\n                     ^~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/testchipip/src/main/resources/testchipip/vsrc/plusarg_file_mem.sv:23: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'ADDR_BITS'\n                                                                                                                            : ... In instance plusarg_file_mem\n    parameter int ADDR_BITS,\n                  ^~~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/testchipip/src/main/resources/testchipip/vsrc/plusarg_file_mem.sv:24: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'READONLY'\n                                                                                                                            : ... In instance plusarg_file_mem\n    parameter bit READONLY,\n                  ^~~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/testchipip/src/main/resources/testchipip/vsrc/plusarg_file_mem.sv:25: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'DATA_BYTES'\n                                                                                                                            : ... In instance plusarg_file_mem\n    parameter int DATA_BYTES\n                  ^~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module plusarg_file_mem #(
    parameter string PLUSARG,
    parameter int ADDR_BITS,
    parameter bit READONLY,
    parameter int DATA_BYTES
) (
    input                     clock,
    input                     reset,
    input                     mem_req_valid,
    input  [ADDR_BITS-1:0]    mem_req_addr,
    input  [DATA_BYTES*8-1:0] mem_req_data,
    input                     mem_req_r_wb,
    output [DATA_BYTES*8-1:0] mem_resp_data
);


    string filename;


    longint dev_ptr;

    initial begin
        assert(ADDR_BITS <= 64);
        assert((DATA_BYTES == 1) || (DATA_BYTES == 2) || (DATA_BYTES == 4) || (DATA_BYTES == 8));
        if ($value$plusargs($sformatf("%s=%%s", PLUSARG), filename)) begin
            dev_ptr = plusarg_file_mem_init(filename, !READONLY, ADDR_BITS, DATA_BYTES);
        end else begin

            $fwrite(32'h80000002, "No memory image provided. Use +%s=<file> to specify.\n", PLUSARG);
            $fatal;
        end
    end

    reg [63:0] mem_resp_data_reg;
    logic [63+ADDR_BITS:0] mem_req_addr_zext_pad;
    logic [63:0] mem_req_addr_zext;
    logic [63+DATA_BYTES*8:0] mem_req_data_zext_pad;
    logic [63:0] mem_req_data_zext;

    assign mem_resp_data = mem_resp_data_reg[DATA_BYTES*8-1:0];
    assign mem_req_addr_zext_pad = {64'd0, mem_req_addr};
    assign mem_req_addr_zext = mem_req_addr_zext_pad[63:0];
    assign mem_req_data_zext_pad = {64'd0, mem_req_data};
    assign mem_req_data_zext = mem_req_data_zext_pad[63:0];

    always @(posedge clock) begin
        if ((!reset) && mem_req_valid) begin
            if (mem_req_r_wb) begin
                plusarg_file_mem_read(dev_ptr, mem_req_addr_zext, mem_resp_data_reg);
            end else begin
                plusarg_file_mem_write(dev_ptr, mem_req_addr_zext, mem_req_data_zext);
            end
        end
    end

endmodule
module plusarg_file_mem #(
    parameter string PLUSARG,
    parameter int ADDR_BITS,
    parameter bit READONLY,
    parameter int DATA_BYTES
) (
    input                     clock,
    input                     reset,
    input                     mem_req_valid,
    input  [ADDR_BITS-1:0]    mem_req_addr,
    input  [DATA_BYTES*8-1:0] mem_req_data,
    input                     mem_req_r_wb,
    output [DATA_BYTES*8-1:0] mem_resp_data
);



    string filename;


    longint dev_ptr;

    initial begin
        assert(ADDR_BITS <= 64);
        assert((DATA_BYTES == 1) || (DATA_BYTES == 2) || (DATA_BYTES == 4) || (DATA_BYTES == 8));
        if ($value$plusargs($sformatf("%s=%%s", PLUSARG), filename)) begin
            dev_ptr = plusarg_file_mem_init(filename, !READONLY, ADDR_BITS, DATA_BYTES);
        end else begin

            $fwrite(32'h80000002, "No memory image provided. Use +%s=<file> to specify.\n", PLUSARG);
            $fatal;
        end
    end

    reg [63:0] mem_resp_data_reg;
    logic [63+ADDR_BITS:0] mem_req_addr_zext_pad;
    logic [63:0] mem_req_addr_zext;
    logic [63+DATA_BYTES*8:0] mem_req_data_zext_pad;
    logic [63:0] mem_req_data_zext;

    assign mem_resp_data = mem_resp_data_reg[DATA_BYTES*8-1:0];
    assign mem_req_addr_zext_pad = {64'd0, mem_req_addr};
    assign mem_req_addr_zext = mem_req_addr_zext_pad[63:0];
    assign mem_req_data_zext_pad = {64'd0, mem_req_data};
    assign mem_req_data_zext = mem_req_data_zext_pad[63:0];

    always @(posedge clock) begin
        if ((!reset) && mem_req_valid) begin
            if (mem_req_r_wb) begin
                plusarg_file_mem_read(dev_ptr, mem_req_addr_zext, mem_resp_data_reg);
            end else begin
                plusarg_file_mem_write(dev_ptr, mem_req_addr_zext, mem_req_data_zext);
            end
        end
    end

endmodule