data/full_repos/permissive/500128826/HDLBits/Modules/Module_addsub/top_module.v
1: b"%Error: data/full_repos/permissive/500128826/HDLBits/Modules/Module_addsub/top_module.v:22: Cannot find file containing module: 'add16'\n  add16 a1 (\n  ^~~~~\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Modules/Module_addsub,data/full_repos/permissive/500128826/add16\n             data/full_repos/permissive/500128826/HDLBits/Modules/Module_addsub,data/full_repos/permissive/500128826/add16.v\n             data/full_repos/permissive/500128826/HDLBits/Modules/Module_addsub,data/full_repos/permissive/500128826/add16.sv\n             add16\n             add16.v\n             add16.sv\n             obj_dir/add16\n             obj_dir/add16.v\n             obj_dir/add16.sv\n%Error: data/full_repos/permissive/500128826/HDLBits/Modules/Module_addsub/top_module.v:30: Cannot find file containing module: 'add16'\n  add16 a2 (\n  ^~~~~\n%Error: Exiting due to 2 error(s)\n"
module top_module (
    input wire [31:0] a,
    input wire [31:0] b,
    input wire sub,
    output wire [31:0] sum
);

  wire [31:0] bsub;

  assign bsub = sub ? ~b : b;

  wire carry;
  add16 a1 (
      .a(a[15:0]),
      .b(bsub[15:0]),
      .cin(sub),
      .sum(sum[15:0]),
      .cout(carry)
  );

  add16 a2 (
      .a(a[31:16]),
      .b(bsub[31:16]),
      .cin(carry),
      .sum(sum[31:16]),
      .cout()
  );

endmodule
module top_module (
    input wire [31:0] a,
    input wire [31:0] b,
    input wire sub,
    output wire [31:0] sum
);


  wire [31:0] bsub;

  assign bsub = sub ? ~b : b;

  wire carry;
  add16 a1 (
      .a(a[15:0]),
      .b(bsub[15:0]),
      .cin(sub),
      .sum(sum[15:0]),
      .cout(carry)
  );

  add16 a2 (
      .a(a[31:16]),
      .b(bsub[31:16]),
      .cin(carry),
      .sum(sum[31:16]),
      .cout()
  );

endmodule