data/full_repos/permissive/447417093/FourBitAdder/Adder4_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/447417093/FourBitAdder/Adder4_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n            #100\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/447417093/FourBitAdder/Adder4_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n            #100  \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/447417093/FourBitAdder/Adder4_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n            #100\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/447417093/FourBitAdder/Adder4_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n            #100\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/447417093/FourBitAdder/Adder4_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n            #100\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/447417093/FourBitAdder/Adder4_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n            #100\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/447417093/FourBitAdder/Adder4_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n            #100\n            ^\n%Warning-STMTDLY: data/full_repos/permissive/447417093/FourBitAdder/Adder4_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n     #100\n     ^\n%Error: data/full_repos/permissive/447417093/FourBitAdder/Adder4_tb.v:6: Cannot find file containing module: \'Adder4\'\n    Adder4 simulate_adder (\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447417093/FourBitAdder,data/full_repos/permissive/447417093/Adder4\n             data/full_repos/permissive/447417093/FourBitAdder,data/full_repos/permissive/447417093/Adder4.v\n             data/full_repos/permissive/447417093/FourBitAdder,data/full_repos/permissive/447417093/Adder4.sv\n             Adder4\n             Adder4.v\n             Adder4.sv\n             obj_dir/Adder4\n             obj_dir/Adder4.v\n             obj_dir/Adder4.sv\n%Warning-WIDTH: data/full_repos/permissive/447417093/FourBitAdder/Adder4_tb.v:30: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh457\' generates 32 or 11 bits.\n                                                                                : ... In instance Adder4_tb\n            assign B = 1111;\n            ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/447417093/FourBitAdder/Adder4_tb.v:35: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh457\' generates 32 or 11 bits.\n                                                                                : ... In instance Adder4_tb\n            assign B = 1111;\n            ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/447417093/FourBitAdder/Adder4_tb.v:39: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh457\' generates 32 or 11 bits.\n                                                                                : ... In instance Adder4_tb\n            assign A = 1111;\n            ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/447417093/FourBitAdder/Adder4_tb.v:44: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh457\' generates 32 or 11 bits.\n                                                                                : ... In instance Adder4_tb\n            assign A = 1111;\n            ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/447417093/FourBitAdder/Adder4_tb.v:49: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh457\' generates 32 or 11 bits.\n                                                                                : ... In instance Adder4_tb\n            assign A = 1111;\n            ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/447417093/FourBitAdder/Adder4_tb.v:50: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh457\' generates 32 or 11 bits.\n                                                                                : ... In instance Adder4_tb\n            assign B = 1111;\n            ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/447417093/FourBitAdder/Adder4_tb.v:54: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh457\' generates 32 or 11 bits.\n                                                                                : ... In instance Adder4_tb\n            assign A = 1111;\n            ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/447417093/FourBitAdder/Adder4_tb.v:55: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh457\' generates 32 or 11 bits.\n                                                                                : ... In instance Adder4_tb\n            assign B = 1111;\n            ^~~~~~\n%Error: Exiting due to 1 error(s), 16 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Adder4_tb();
    reg A, B, Cin;
    wire Sum, Cout;

    Adder4 simulate_adder (
        .A(A[3:0]),
        .B(B[3:0]),
        .Cin(Cin),
        .Sum(Sum[3:0]),
        .Cout(Cout)
    );

    initial
        begin
            $display($time, " <<Starting the Simulation >>");


            assign A = 0000;
            assign B = 0000;
            assign Cin = 0;
            #100

	        assign A = 0000;
            assign B = 0000;
            assign Cin = 1;
            #100

	        assign A = 0000;
            assign B = 1111;
            assign Cin = 0;
            #100

            assign A = 0000;
            assign B = 1111;
            assign Cin = 1;
            #100

            assign A = 1111;
            assign B = 0000;
            assign Cin = 0;
            #100

            assign A = 1111;
            assign B = 0000;
            assign Cin = 1;
            #100

            assign A = 1111;
            assign B = 1111;
            assign Cin = 0;
            #100

            assign A = 1111;
            assign B = 1111;
            assign Cin = 1;
	    #100
	    $finish;
            $display($time, " << Simulation complete>>");
        end
endmodule
module Adder4_tb();

    reg A, B, Cin;
    wire Sum, Cout;

    Adder4 simulate_adder (
        .A(A[3:0]),
        .B(B[3:0]),
        .Cin(Cin),
        .Sum(Sum[3:0]),
        .Cout(Cout)
    );

    initial
        begin
            $display($time, " <<Starting the Simulation >>");


            assign A = 0000;
            assign B = 0000;
            assign Cin = 0;
            #100

	        assign A = 0000;
            assign B = 0000;
            assign Cin = 1;
            #100

	        assign A = 0000;
            assign B = 1111;
            assign Cin = 0;
            #100

            assign A = 0000;
            assign B = 1111;
            assign Cin = 1;
            #100

            assign A = 1111;
            assign B = 0000;
            assign Cin = 0;
            #100

            assign A = 1111;
            assign B = 0000;
            assign Cin = 1;
            #100

            assign A = 1111;
            assign B = 1111;
            assign Cin = 0;
            #100

            assign A = 1111;
            assign B = 1111;
            assign Cin = 1;
	    #100
	    $finish;
            $display($time, " << Simulation complete>>");
        end
endmodule