data/full_repos/permissive/484543204/verilog/dv/adder_test/adder_test_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/adder_test/adder_test_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n    always #12.5 clock <= (clock === 1\'b0);\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/484543204/verilog/dv/adder_test/adder_test_tb.v:53: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("adder_test.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/484543204/verilog/dv/adder_test/adder_test_tb.v:54: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, adder_test_tb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/adder_test/adder_test_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n        #1;\n        ^\n%Error: data/full_repos/permissive/484543204/verilog/dv/adder_test/adder_test_tb.v:59: syntax error, unexpected \'@\'\n   repeat (1000) @(posedge clock);\n                 ^\n%Error: data/full_repos/permissive/484543204/verilog/dv/adder_test/adder_test_tb.v:90: Unsupported: wait statements\n      wait(checkbits == 4\'hA);\n      ^~~~\n%Error: data/full_repos/permissive/484543204/verilog/dv/adder_test/adder_test_tb.v:92: Unsupported: wait statements\n      wait(clock == 1);\n      ^~~~\n%Error: data/full_repos/permissive/484543204/verilog/dv/adder_test/adder_test_tb.v:93: Unsupported: wait statements\n      wait(clock == 0);\n      ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/adder_test/adder_test_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n      #6;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/adder_test/adder_test_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n      #12.5;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/adder_test/adder_test_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n      #12.5;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/adder_test/adder_test_tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n  #2000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/adder_test/adder_test_tb.v:120: Unsupported: Ignoring delay on this delayed statement.\n  #300000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/adder_test/adder_test_tb.v:129: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/adder_test/adder_test_tb.v:131: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/adder_test/adder_test_tb.v:133: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/484543204/verilog/dv/adder_test/adder_test_tb.v:135: Unsupported: Ignoring delay on this delayed statement.\n  #100;\n  ^\n%Error: Exiting due to 6 error(s), 11 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module adder_test_tb;
	reg clock;
	reg RSTB;
    reg reset;
	reg CSB;
    integer cycle_count;
    reg power1, power2;
	reg power3, power4;

    wire gpio;
	wire [37:0] mprj_io;
	wire [3:0] checkbits;
    reg a;
    assign mprj_io[13:10] = a;
    reg b;
    assign mprj_io[17:14] = b;

	assign checkbits = mprj_io[31:28];

    always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
	end

	initial begin
		$dumpfile("adder_test.vcd");
		$dumpvars(0, adder_test_tb);
        #1;


		repeat (25) begin
			repeat (1000) @(posedge clock);

		end
		$display("%c[1;31m",27);
		`ifdef GL
			$display ("Monitor: Timeout, Test Mega-Project Loopback (GL) Failed");
		`else
			$display ("Monitor: Timeout, Test Mega-Project Loopback (RTL) Failed");
		`endif
		$display("%c[0m",27);
		$finish;
	end









    initial begin


  


  



      wait(checkbits == 4'hA);

      wait(clock == 1);
      wait(clock == 0);
      #6;


      a = 4'b0001;
      b = 4'b0001;
      #12.5;
      if(mprj_io[21:18] != 4'b0010) begin
        $display("failed :(");
        $finish;
      end
  
      $display("");
      $display("  [ passed ]");
      $display("");
  

      #12.5;
      cycle_count += 1;
      $finish;
    end    

	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#300000;
		CSB = 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end

    	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD1V8;
    	wire VDD3V3;
	wire VSS;
    
	assign VDD3V3 = power1;
	assign VDD1V8 = power2;
	assign VSS = 1'b0;

	assign mprj_io[3] = 1;
	assign mprj_io[0] = 0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda1_2  (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock    (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("adder_test.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule
module adder_test_tb;

	reg clock;
	reg RSTB;
    reg reset;
	reg CSB;
    integer cycle_count;
    reg power1, power2;
	reg power3, power4;

    wire gpio;
	wire [37:0] mprj_io;
	wire [3:0] checkbits;
    reg a;
    assign mprj_io[13:10] = a;
    reg b;
    assign mprj_io[17:14] = b;

	assign checkbits = mprj_io[31:28];

    always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
	end

	initial begin
		$dumpfile("adder_test.vcd");
		$dumpvars(0, adder_test_tb);
        #1;


		repeat (25) begin
			repeat (1000) @(posedge clock);

		end
		$display("%c[1;31m",27);
		`ifdef GL
			$display ("Monitor: Timeout, Test Mega-Project Loopback (GL) Failed");
		`else
			$display ("Monitor: Timeout, Test Mega-Project Loopback (RTL) Failed");
		`endif
		$display("%c[0m",27);
		$finish;
	end









    initial begin


  


  



      wait(checkbits == 4'hA);

      wait(clock == 1);
      wait(clock == 0);
      #6;


      a = 4'b0001;
      b = 4'b0001;
      #12.5;
      if(mprj_io[21:18] != 4'b0010) begin
        $display("failed :(");
        $finish;
      end
  
      $display("");
      $display("  [ passed ]");
      $display("");
  

      #12.5;
      cycle_count += 1;
      $finish;
    end    

	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#300000;
		CSB = 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		power3 <= 1'b0;
		power4 <= 1'b0;
		#100;
		power1 <= 1'b1;
		#100;
		power2 <= 1'b1;
		#100;
		power3 <= 1'b1;
		#100;
		power4 <= 1'b1;
	end

    	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD1V8;
    	wire VDD3V3;
	wire VSS;
    
	assign VDD3V3 = power1;
	assign VDD1V8 = power2;
	assign VSS = 1'b0;

	assign mprj_io[3] = 1;
	assign mprj_io[0] = 0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda1_2  (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock    (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("adder_test.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule