data/full_repos/permissive/496508301/Lesson3/Comp_conv/comp_conv.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson3/Comp_conv/comp_conv.v:29: Unsupported: Ignoring delay on this delayed statement.\n    #3000   $stop;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson3/Comp_conv/comp_conv.v:31: Unsupported: Ignoring delay on this delayed statement.\nalways #10 aa <= aa+1;\n       ^\n%Error: data/full_repos/permissive/496508301/Lesson3/Comp_conv/comp_conv.v:34: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("comp_conv_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/496508301/Lesson3/Comp_conv/comp_conv.v:35: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module comp_conv_tb;
reg[7:0]     aa;
wire[7:0]    ac;
comp_conv comp_conv(
            .a(aa),
            .a_comp(ac)
);
initial begin
            aa<=0;
    #3000   $stop;
end
always #10 aa <= aa+1;

initial begin
    $dumpfile("comp_conv_tb.vcd");
    $dumpvars;
end

endmodule
module comp_conv_tb;

reg[7:0]     aa;
wire[7:0]    ac;
comp_conv comp_conv(
            .a(aa),
            .a_comp(ac)
);
initial begin
            aa<=0;
    #3000   $stop;
end
always #10 aa <= aa+1;

initial begin
    $dumpfile("comp_conv_tb.vcd");
    $dumpvars;
end

endmodule