data/full_repos/permissive/484316383/rtl/common/timer8253.v
1: b'%Warning-WIDTH: data/full_repos/permissive/484316383/rtl/common/timer8253.v:213: Operator SUB expects 16 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                               : ... In instance timer_8253.counter2\n     end else if (gate) count <= count - 2\'d2; else mode[6] <= 1;\n                                       ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module counter(
	input CS,
    input WR,
	input clk,
	input gate,
    input cmd,
	input [7:0]din,
	output [7:0]dout,
	output out,
	input [1:0]CE
	);
	 
	reg [15:0]count = 0;
	reg [15:0]init = 0;
	reg [15:0]latched = 0;
	reg [1:0]state = 0;
	reg strobe = 0;
	reg rd = 0;
	reg latch = 0;
	reg newcmd = 0;
	reg newdata = 0;
	reg [6:0] mode;
	wire c1 = count == 1;
	wire c2 = count == 2;
	reg CE1 = 0;
	reg waitgate = 0;
	reg gate_d;

	assign out = mode[6];
	assign dout = latch ?
		(rd ? latched[15:8] : latched[7:0]) : 
		(mode[5] & (~mode[4] | rd) ? count[15:8] : count[7:0]);

	wire gate_r = ~gate_d & gate;

	always @(posedge clk) begin

		if(CE == 2'b10) CE1 <= 1;

		if(CE1) begin
			newdata <= 0;
			gate_d <= gate;
			CE1 <= 0;
			case(mode[3:1])
				3'b000:
					if (newdata) begin
						count <= init;
						newcmd <= 0;
						mode[6] <= 0;
					end else if(newcmd) begin
						mode[6] <= 0;
					end else begin
						count <= count - 1'd1;
						if(c1) mode[6] <= 1;
					end
				3'b001:
					if(newcmd) begin
						if (newdata) begin
							count <= init;
							newdata <= 0;
							newcmd <= 0;
							waitgate <= 1;
						end
					end else if (waitgate) begin
						if (gate_r) begin
							mode[6] <= 0;
							waitgate <= 0;
						end
					end else if (gate_r) begin
						mode[6] <= 0;
						count <= init;
					end else begin
						count <= count - 1'd1;
						if(c1) mode[6] <= 1;
					end
				3'b010, 3'b110: begin
					mode[6] <= ~c2 | ~gate;
					if(c1 | newcmd | gate_r) begin
						if (!newcmd | newdata | gate_r) begin
							newcmd <= 0;
							count <= init;
						end
					end else if (gate) count <= count - 1'd1;
				end
				3'b011, 3'b111:
					if(c1 | c2 | newcmd | gate_r) begin
						mode[6] <= {~mode[6] | newcmd | ~gate};
						if (!newcmd | newdata | gate_r) begin
							newcmd <= 0;
							count <= {init[15:1], (~mode[6] | newcmd) & init[0]};
						end
					end else if (gate) count <= count - 2'd2; else mode[6] <= 1;
				3'b100:
					if (newdata) begin
						newcmd <= 0;
						count <= init;
						strobe <= 1;
					end else if(newcmd) begin
						mode[6] <= 1;
					end else begin
						count <= count - 1'd1;
						if(c1) begin
							if(strobe) mode[6] <= 0;
							strobe <= 0;
						end else mode[6] <= 1'd1;
					end
				3'b101:
					if(newcmd) begin
						mode[6] <= 1;
						if (newdata) begin
							newcmd <= 0;
							waitgate <= 1;
						end
					end else if (gate_r) begin
						count <= init;
						strobe <= 1;
						waitgate <= 0;
					end else if (!waitgate) begin
						count <= count - 1'd1;
						if(c1) begin
							if(strobe) mode[6] <= 0;
							strobe <= 0;
						end else mode[6] <= 1'd1;
					end

			endcase
		end

		if(CS) begin
			if(WR) begin
				rd <= 0;
				latch <= 0;
				if(cmd) begin
					if(|din[5:4]) begin
						mode[5:0] <= din[5:0];
						newcmd <= 1;
						state <= {1'b0, din[5] & ~din[4]};
					end else begin
						latch <= 1;
						latched <= count;
					end
				end else begin
					state <= state[0] + ^mode[5:4] + 1'd1;
					if(state[0]) begin
						newdata <= 1;
						init[15:8] <= din;
						if (~mode[4]) init[7:0] <= 0;
					end
					else begin
						init[7:0] <= din;
						if (~mode[5]) init[15:8] <= 0;
						newdata <= ^mode[5:4];
					end
				end
			end else begin
				rd <= ~rd;
				if(rd) latch <= 0;
			end
		end
	end

endmodule
module counter(
	input CS,
    input WR,
	input clk,
	input gate,
    input cmd,
	input [7:0]din,
	output [7:0]dout,
	output out,
	input [1:0]CE
	);

	 
	reg [15:0]count = 0;
	reg [15:0]init = 0;
	reg [15:0]latched = 0;
	reg [1:0]state = 0;
	reg strobe = 0;
	reg rd = 0;
	reg latch = 0;
	reg newcmd = 0;
	reg newdata = 0;
	reg [6:0] mode;
	wire c1 = count == 1;
	wire c2 = count == 2;
	reg CE1 = 0;
	reg waitgate = 0;
	reg gate_d;

	assign out = mode[6];
	assign dout = latch ?
		(rd ? latched[15:8] : latched[7:0]) : 
		(mode[5] & (~mode[4] | rd) ? count[15:8] : count[7:0]);

	wire gate_r = ~gate_d & gate;

	always @(posedge clk) begin

		if(CE == 2'b10) CE1 <= 1;

		if(CE1) begin
			newdata <= 0;
			gate_d <= gate;
			CE1 <= 0;
			case(mode[3:1])
				3'b000:
					if (newdata) begin
						count <= init;
						newcmd <= 0;
						mode[6] <= 0;
					end else if(newcmd) begin
						mode[6] <= 0;
					end else begin
						count <= count - 1'd1;
						if(c1) mode[6] <= 1;
					end
				3'b001:
					if(newcmd) begin
						if (newdata) begin
							count <= init;
							newdata <= 0;
							newcmd <= 0;
							waitgate <= 1;
						end
					end else if (waitgate) begin
						if (gate_r) begin
							mode[6] <= 0;
							waitgate <= 0;
						end
					end else if (gate_r) begin
						mode[6] <= 0;
						count <= init;
					end else begin
						count <= count - 1'd1;
						if(c1) mode[6] <= 1;
					end
				3'b010, 3'b110: begin
					mode[6] <= ~c2 | ~gate;
					if(c1 | newcmd | gate_r) begin
						if (!newcmd | newdata | gate_r) begin
							newcmd <= 0;
							count <= init;
						end
					end else if (gate) count <= count - 1'd1;
				end
				3'b011, 3'b111:
					if(c1 | c2 | newcmd | gate_r) begin
						mode[6] <= {~mode[6] | newcmd | ~gate};
						if (!newcmd | newdata | gate_r) begin
							newcmd <= 0;
							count <= {init[15:1], (~mode[6] | newcmd) & init[0]};
						end
					end else if (gate) count <= count - 2'd2; else mode[6] <= 1;
				3'b100:
					if (newdata) begin
						newcmd <= 0;
						count <= init;
						strobe <= 1;
					end else if(newcmd) begin
						mode[6] <= 1;
					end else begin
						count <= count - 1'd1;
						if(c1) begin
							if(strobe) mode[6] <= 0;
							strobe <= 0;
						end else mode[6] <= 1'd1;
					end
				3'b101:
					if(newcmd) begin
						mode[6] <= 1;
						if (newdata) begin
							newcmd <= 0;
							waitgate <= 1;
						end
					end else if (gate_r) begin
						count <= init;
						strobe <= 1;
						waitgate <= 0;
					end else if (!waitgate) begin
						count <= count - 1'd1;
						if(c1) begin
							if(strobe) mode[6] <= 0;
							strobe <= 0;
						end else mode[6] <= 1'd1;
					end

			endcase
		end

		if(CS) begin
			if(WR) begin
				rd <= 0;
				latch <= 0;
				if(cmd) begin
					if(|din[5:4]) begin
						mode[5:0] <= din[5:0];
						newcmd <= 1;
						state <= {1'b0, din[5] & ~din[4]};
					end else begin
						latch <= 1;
						latched <= count;
					end
				end else begin
					state <= state[0] + ^mode[5:4] + 1'd1;
					if(state[0]) begin
						newdata <= 1;
						init[15:8] <= din;
						if (~mode[4]) init[7:0] <= 0;
					end
					else begin
						init[7:0] <= din;
						if (~mode[5]) init[15:8] <= 0;
						newdata <= ^mode[5:4];
					end
				end
			end else begin
				rd <= ~rd;
				if(rd) latch <= 0;
			end
		end
	end

endmodule