data/full_repos/permissive/49670587/full-fpga-testing/custom_ms/ff_en/ff_en_fpga_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/49670587/full-fpga-testing/custom_ms/ff_en/ff_en_fpga_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #10\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/49670587/full-fpga-testing/custom_ms/ff_en/ff_en_fpga_tb.v:19: Unsupported: wait statements\n        wait ( rdy == 1\'b1 )\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/49670587/full-fpga-testing/custom_ms/ff_en/ff_en_fpga_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/49670587/full-fpga-testing/custom_ms/ff_en/ff_en_fpga_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/49670587/full-fpga-testing/custom_ms/ff_en/ff_en_fpga_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/49670587/full-fpga-testing/custom_ms/ff_en/ff_en_fpga_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/49670587/full-fpga-testing/custom_ms/ff_en/ff_en_fpga_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/49670587/full-fpga-testing/custom_ms/ff_en/ff_en_fpga_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #40\n        ^\n%Error: data/full_repos/permissive/49670587/full-fpga-testing/custom_ms/ff_en/ff_en_fpga_tb.v:53: Unsupported or unknown PLI call: $monitor\n        $monitor($time, ", clock = %b, rst = %b, d_in = %h, d_en = %b, d_out = %h", \n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/49670587/full-fpga-testing/custom_ms/ff_en/ff_en_fpga_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n        #20 rst = 1\'b0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/49670587/full-fpga-testing/custom_ms/ff_en/ff_en_fpga_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n        #10 clock = ~clock;\n        ^\n%Error: Exiting due to 2 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ff_en_tb();

    reg clock, rst;
    reg [9:0] d_in;
    reg d_en; 
    wire [9:0] d_out;

    wire rdy;

    initial
    begin
        $display($time, " << Starting the Simulation >>");
        
        d_in = 10'b0;
        d_en = 1'b0;

        wait ( rdy == 1'b1 )
        #10
        begin
            d_in = 10'h3ff;
            d_en = 1'b1;
        end

        #20
        d_in = 10'h0;
        d_en = 1'b0;

        #20
        d_in = 10'h155;
        d_en = 1'b1;

        #20
        d_in = 10'h288;
        d_en = 1'b0;

        #20
        d_in = 10'h288;
        d_en = 1'b1;

        #20
        d_in = 10'h0;
        d_en = 1'b1;

        #40
        $display($time, " << Simulation Complete >>");
        $finish;
    end

    initial
    begin
        $monitor($time, ", clock = %b, rst = %b, d_in = %h, d_en = %b, d_out = %h", 
                           clock,      rst,      d_in,      d_en,      d_out);
    end

    initial
    begin
        clock = 1'b1;
        rst = 1'b1;
        #20 rst = 1'b0;
    end

    always
    begin
        #10 clock = ~clock;
    end


    ff_en dut ( .d_in(d_in),
                     .d_out(d_out),
                     .d_en(d_en),
                     .clock(clock),
                     .rst(rst),
                     .rdy(rdy)
                   );

endmodule
module ff_en_tb();


    reg clock, rst;
    reg [9:0] d_in;
    reg d_en; 
    wire [9:0] d_out;

    wire rdy;

    initial
    begin
        $display($time, " << Starting the Simulation >>");
        
        d_in = 10'b0;
        d_en = 1'b0;

        wait ( rdy == 1'b1 )
        #10
        begin
            d_in = 10'h3ff;
            d_en = 1'b1;
        end

        #20
        d_in = 10'h0;
        d_en = 1'b0;

        #20
        d_in = 10'h155;
        d_en = 1'b1;

        #20
        d_in = 10'h288;
        d_en = 1'b0;

        #20
        d_in = 10'h288;
        d_en = 1'b1;

        #20
        d_in = 10'h0;
        d_en = 1'b1;

        #40
        $display($time, " << Simulation Complete >>");
        $finish;
    end

    initial
    begin
        $monitor($time, ", clock = %b, rst = %b, d_in = %h, d_en = %b, d_out = %h", 
                           clock,      rst,      d_in,      d_en,      d_out);
    end

    initial
    begin
        clock = 1'b1;
        rst = 1'b1;
        #20 rst = 1'b0;
    end

    always
    begin
        #10 clock = ~clock;
    end


    ff_en dut ( .d_in(d_in),
                     .d_out(d_out),
                     .d_en(d_en),
                     .clock(clock),
                     .rst(rst),
                     .rdy(rdy)
                   );

endmodule