data/full_repos/permissive/494664634/AxiS2MMTest/src/hdl/AxiS2MMTest.v
data/verilator_xmls/8782da5f-17bb-4ce7-b810-c4989e6c3866.xml
module AxiS2MMTest(

  (*
    X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clock CLK", X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF S_AXI_LITE:M_AXI:S_AXIS"
     *)
  input         clock,

  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 reset RST", X_INTERFACE_PARAMETER = "POLARITY ACTIVE_HIGH" *)
  input         reset,

  (*
    X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR", X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI_LITE, CLK_DOMAIN clock, ID_WIDTH 0, PROTOCOL AXI4LITE, DATA_WIDTH 32"
     *)
  input  [31:0] s_axi_araddr,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID" *)
  input         s_axi_arvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY" *)
  output        s_axi_arready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA" *)
  output [31:0] s_axi_rdata,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP" *)
  output [1:0]  s_axi_rresp,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID" *)
  output        s_axi_rvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY" *)
  input         s_axi_rready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR" *)
  input  [31:0] s_axi_awaddr,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID" *)
  input         s_axi_awvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY" *)
  output        s_axi_awready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA" *)
  input  [31:0] s_axi_wdata,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID" *)
  input         s_axi_wvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY" *)
  output        s_axi_wready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP" *)
  output [1:0]  s_axi_bresp,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID" *)
  output        s_axi_bvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY" *)
  input         s_axi_bready,

  (*
    X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR", X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, CLK_DOMAIN clock, ID_WIDTH 0, PROTOCOL AXI4, DATA_WIDTH 32"
     *)
  output [31:0] m_axi_awaddr,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
  output        m_axi_awvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
  input         m_axi_awready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
  output [31:0] m_axi_wdata,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
  output        m_axi_wvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
  input         m_axi_wready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
  input  [1:0]  m_axi_bresp,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
  input         m_axi_bvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
  output        m_axi_bready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
  output [7:0]  m_axi_awlen,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
  output [3:0]  m_axi_wstrb,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
  output        m_axi_wlast,

  (*
    X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA", X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, CLK_DOMAIN clock"
     *)
  input  [31:0] s_axis_tdata,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
  input         s_axis_tvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
  output        s_axis_tready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TKEEP" *)
  input  [3:0]  s_axis_tkeep
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif
  wire  axi_ctrl_clock;
  wire  axi_ctrl_reset;
  wire [31:0] axi_ctrl_s_axi_araddr;
  wire  axi_ctrl_s_axi_arvalid;
  wire  axi_ctrl_s_axi_arready;
  wire [31:0] axi_ctrl_s_axi_rdata;
  wire  axi_ctrl_s_axi_rvalid;
  wire  axi_ctrl_s_axi_rready;
  wire [31:0] axi_ctrl_s_axi_awaddr;
  wire  axi_ctrl_s_axi_awvalid;
  wire  axi_ctrl_s_axi_awready;
  wire [31:0] axi_ctrl_s_axi_wdata;
  wire  axi_ctrl_s_axi_wvalid;
  wire  axi_ctrl_s_axi_wready;
  wire  axi_ctrl_s_axi_bvalid;
  wire  axi_ctrl_s_axi_bready;
  wire  axi_ctrl_start;
  wire  axi_ctrl_done;
  wire [31:0] axi_ctrl_write_addr;
  wire [31:0] axi_ctrl_write_length;
  wire  write_master_clock;
  wire  write_master_reset;
  wire  write_master_ctrl_start;
  wire  write_master_ctrl_done;
  wire [31:0] write_master_ctrl_offset;
  wire [31:0] write_master_ctrl_length;
  wire [31:0] write_master_m_axi_awaddr;
  wire  write_master_m_axi_awvalid;
  wire  write_master_m_axi_awready;
  wire [31:0] write_master_m_axi_wdata;
  wire  write_master_m_axi_wvalid;
  wire  write_master_m_axi_wready;
  wire  write_master_m_axi_bvalid;
  wire  write_master_m_axi_bready;
  wire [7:0] write_master_m_axi_awlen;
  wire [3:0] write_master_m_axi_wstrb;
  wire  write_master_m_axi_wlast;
  wire [31:0] write_master_s_tdata;
  wire  write_master_s_tvalid;
  wire  write_master_s_tready;
  wire [3:0] write_master_s_tkeep;
  wire [31:0] dmaInfo_addr;
  wire [31:0] dmaInfo_blength;
  wire [31:0] dmaInfo_offset;
  wire [31:0] dmaInfo_wlength;
  reg  done;
  AxiCtrlS2MM axi_ctrl (
    .clock(axi_ctrl_clock),
    .reset(axi_ctrl_reset),
    .s_axi_araddr(axi_ctrl_s_axi_araddr),
    .s_axi_arvalid(axi_ctrl_s_axi_arvalid),
    .s_axi_arready(axi_ctrl_s_axi_arready),
    .s_axi_rdata(axi_ctrl_s_axi_rdata),
    .s_axi_rvalid(axi_ctrl_s_axi_rvalid),
    .s_axi_rready(axi_ctrl_s_axi_rready),
    .s_axi_awaddr(axi_ctrl_s_axi_awaddr),
    .s_axi_awvalid(axi_ctrl_s_axi_awvalid),
    .s_axi_awready(axi_ctrl_s_axi_awready),
    .s_axi_wdata(axi_ctrl_s_axi_wdata),
    .s_axi_wvalid(axi_ctrl_s_axi_wvalid),
    .s_axi_wready(axi_ctrl_s_axi_wready),
    .s_axi_bvalid(axi_ctrl_s_axi_bvalid),
    .s_axi_bready(axi_ctrl_s_axi_bready),
    .start(axi_ctrl_start),
    .done(axi_ctrl_done),
    .write_addr(axi_ctrl_write_addr),
    .write_length(axi_ctrl_write_length)
  );
  AxiWriteMaster write_master (
    .clock(write_master_clock),
    .reset(write_master_reset),
    .ctrl_start(write_master_ctrl_start),
    .ctrl_done(write_master_ctrl_done),
    .ctrl_offset(write_master_ctrl_offset),
    .ctrl_length(write_master_ctrl_length),
    .m_axi_awaddr(write_master_m_axi_awaddr),
    .m_axi_awvalid(write_master_m_axi_awvalid),
    .m_axi_awready(write_master_m_axi_awready),
    .m_axi_wdata(write_master_m_axi_wdata),
    .m_axi_wvalid(write_master_m_axi_wvalid),
    .m_axi_wready(write_master_m_axi_wready),
    .m_axi_bvalid(write_master_m_axi_bvalid),
    .m_axi_bready(write_master_m_axi_bready),
    .m_axi_awlen(write_master_m_axi_awlen),
    .m_axi_wstrb(write_master_m_axi_wstrb),
    .m_axi_wlast(write_master_m_axi_wlast),
    .s_tdata(write_master_s_tdata),
    .s_tvalid(write_master_s_tvalid),
    .s_tready(write_master_s_tready),
    .s_tkeep(write_master_s_tkeep)
  );
  DmaInfo dmaInfo (
    .addr(dmaInfo_addr),
    .blength(dmaInfo_blength),
    .offset(dmaInfo_offset),
    .wlength(dmaInfo_wlength)
  );
  assign s_axi_arready = axi_ctrl_s_axi_arready;
  assign s_axi_rdata = axi_ctrl_s_axi_rdata;
  assign s_axi_rresp = 2'h0;
  assign s_axi_rvalid = axi_ctrl_s_axi_rvalid;
  assign s_axi_awready = axi_ctrl_s_axi_awready;
  assign s_axi_wready = axi_ctrl_s_axi_wready;
  assign s_axi_bresp = 2'h0;
  assign s_axi_bvalid = axi_ctrl_s_axi_bvalid;
  assign m_axi_awaddr = write_master_m_axi_awaddr;
  assign m_axi_awvalid = write_master_m_axi_awvalid;
  assign m_axi_wdata = write_master_m_axi_wdata;
  assign m_axi_wvalid = write_master_m_axi_wvalid;
  assign m_axi_bready = 1'h1;
  assign m_axi_awlen = write_master_m_axi_awlen;
  assign m_axi_wstrb = write_master_m_axi_wstrb;
  assign m_axi_wlast = write_master_m_axi_wlast;
  assign s_axis_tready = write_master_s_tready;
  assign axi_ctrl_clock = clock;
  assign axi_ctrl_reset = reset;
  assign axi_ctrl_s_axi_araddr = s_axi_araddr;
  assign axi_ctrl_s_axi_arvalid = s_axi_arvalid;
  assign axi_ctrl_s_axi_rready = s_axi_rready;
  assign axi_ctrl_s_axi_awaddr = s_axi_awaddr;
  assign axi_ctrl_s_axi_awvalid = s_axi_awvalid;
  assign axi_ctrl_s_axi_wdata = s_axi_wdata;
  assign axi_ctrl_s_axi_wvalid = s_axi_wvalid;
  assign axi_ctrl_s_axi_bready = s_axi_bready;
  assign axi_ctrl_done = done;
  assign write_master_clock = clock;
  assign write_master_reset = reset;
  assign write_master_ctrl_start = axi_ctrl_start;
  assign write_master_ctrl_offset = dmaInfo_offset;
  assign write_master_ctrl_length = dmaInfo_wlength;
  assign write_master_m_axi_awready = m_axi_awready;
  assign write_master_m_axi_wready = m_axi_wready;
  assign write_master_m_axi_bvalid = m_axi_bvalid;
  assign write_master_s_tdata = s_axis_tdata;
  assign write_master_s_tvalid = s_axis_tvalid;
  assign write_master_s_tkeep = s_axis_tkeep;
  assign dmaInfo_addr = axi_ctrl_write_addr;
  assign dmaInfo_blength = axi_ctrl_write_length;
  always @(posedge clock) begin
    if (reset) begin
      done <= 1'h0;
    end else begin
      done <= write_master_ctrl_done | done;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  done = _RAND_0[0:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module AxiS2MMTest(

  (*
    X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clock CLK", X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF S_AXI_LITE:M_AXI:S_AXIS"
     *)
  input         clock,

  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 reset RST", X_INTERFACE_PARAMETER = "POLARITY ACTIVE_HIGH" *)
  input         reset,

  (*
    X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR", X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI_LITE, CLK_DOMAIN clock, ID_WIDTH 0, PROTOCOL AXI4LITE, DATA_WIDTH 32"
     *)
  input  [31:0] s_axi_araddr,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID" *)
  input         s_axi_arvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY" *)
  output        s_axi_arready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA" *)
  output [31:0] s_axi_rdata,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP" *)
  output [1:0]  s_axi_rresp,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID" *)
  output        s_axi_rvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY" *)
  input         s_axi_rready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR" *)
  input  [31:0] s_axi_awaddr,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID" *)
  input         s_axi_awvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY" *)
  output        s_axi_awready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA" *)
  input  [31:0] s_axi_wdata,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID" *)
  input         s_axi_wvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY" *)
  output        s_axi_wready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP" *)
  output [1:0]  s_axi_bresp,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID" *)
  output        s_axi_bvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY" *)
  input         s_axi_bready,

  (*
    X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR", X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, CLK_DOMAIN clock, ID_WIDTH 0, PROTOCOL AXI4, DATA_WIDTH 32"
     *)
  output [31:0] m_axi_awaddr,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
  output        m_axi_awvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
  input         m_axi_awready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
  output [31:0] m_axi_wdata,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
  output        m_axi_wvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
  input         m_axi_wready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
  input  [1:0]  m_axi_bresp,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
  input         m_axi_bvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
  output        m_axi_bready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
  output [7:0]  m_axi_awlen,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
  output [3:0]  m_axi_wstrb,

  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
  output        m_axi_wlast,

  (*
    X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA", X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, CLK_DOMAIN clock"
     *)
  input  [31:0] s_axis_tdata,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
  input         s_axis_tvalid,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
  output        s_axis_tready,

  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TKEEP" *)
  input  [3:0]  s_axis_tkeep
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif
  wire  axi_ctrl_clock;
  wire  axi_ctrl_reset;
  wire [31:0] axi_ctrl_s_axi_araddr;
  wire  axi_ctrl_s_axi_arvalid;
  wire  axi_ctrl_s_axi_arready;
  wire [31:0] axi_ctrl_s_axi_rdata;
  wire  axi_ctrl_s_axi_rvalid;
  wire  axi_ctrl_s_axi_rready;
  wire [31:0] axi_ctrl_s_axi_awaddr;
  wire  axi_ctrl_s_axi_awvalid;
  wire  axi_ctrl_s_axi_awready;
  wire [31:0] axi_ctrl_s_axi_wdata;
  wire  axi_ctrl_s_axi_wvalid;
  wire  axi_ctrl_s_axi_wready;
  wire  axi_ctrl_s_axi_bvalid;
  wire  axi_ctrl_s_axi_bready;
  wire  axi_ctrl_start;
  wire  axi_ctrl_done;
  wire [31:0] axi_ctrl_write_addr;
  wire [31:0] axi_ctrl_write_length;
  wire  write_master_clock;
  wire  write_master_reset;
  wire  write_master_ctrl_start;
  wire  write_master_ctrl_done;
  wire [31:0] write_master_ctrl_offset;
  wire [31:0] write_master_ctrl_length;
  wire [31:0] write_master_m_axi_awaddr;
  wire  write_master_m_axi_awvalid;
  wire  write_master_m_axi_awready;
  wire [31:0] write_master_m_axi_wdata;
  wire  write_master_m_axi_wvalid;
  wire  write_master_m_axi_wready;
  wire  write_master_m_axi_bvalid;
  wire  write_master_m_axi_bready;
  wire [7:0] write_master_m_axi_awlen;
  wire [3:0] write_master_m_axi_wstrb;
  wire  write_master_m_axi_wlast;
  wire [31:0] write_master_s_tdata;
  wire  write_master_s_tvalid;
  wire  write_master_s_tready;
  wire [3:0] write_master_s_tkeep;
  wire [31:0] dmaInfo_addr;
  wire [31:0] dmaInfo_blength;
  wire [31:0] dmaInfo_offset;
  wire [31:0] dmaInfo_wlength;
  reg  done;
  AxiCtrlS2MM axi_ctrl (
    .clock(axi_ctrl_clock),
    .reset(axi_ctrl_reset),
    .s_axi_araddr(axi_ctrl_s_axi_araddr),
    .s_axi_arvalid(axi_ctrl_s_axi_arvalid),
    .s_axi_arready(axi_ctrl_s_axi_arready),
    .s_axi_rdata(axi_ctrl_s_axi_rdata),
    .s_axi_rvalid(axi_ctrl_s_axi_rvalid),
    .s_axi_rready(axi_ctrl_s_axi_rready),
    .s_axi_awaddr(axi_ctrl_s_axi_awaddr),
    .s_axi_awvalid(axi_ctrl_s_axi_awvalid),
    .s_axi_awready(axi_ctrl_s_axi_awready),
    .s_axi_wdata(axi_ctrl_s_axi_wdata),
    .s_axi_wvalid(axi_ctrl_s_axi_wvalid),
    .s_axi_wready(axi_ctrl_s_axi_wready),
    .s_axi_bvalid(axi_ctrl_s_axi_bvalid),
    .s_axi_bready(axi_ctrl_s_axi_bready),
    .start(axi_ctrl_start),
    .done(axi_ctrl_done),
    .write_addr(axi_ctrl_write_addr),
    .write_length(axi_ctrl_write_length)
  );
  AxiWriteMaster write_master (
    .clock(write_master_clock),
    .reset(write_master_reset),
    .ctrl_start(write_master_ctrl_start),
    .ctrl_done(write_master_ctrl_done),
    .ctrl_offset(write_master_ctrl_offset),
    .ctrl_length(write_master_ctrl_length),
    .m_axi_awaddr(write_master_m_axi_awaddr),
    .m_axi_awvalid(write_master_m_axi_awvalid),
    .m_axi_awready(write_master_m_axi_awready),
    .m_axi_wdata(write_master_m_axi_wdata),
    .m_axi_wvalid(write_master_m_axi_wvalid),
    .m_axi_wready(write_master_m_axi_wready),
    .m_axi_bvalid(write_master_m_axi_bvalid),
    .m_axi_bready(write_master_m_axi_bready),
    .m_axi_awlen(write_master_m_axi_awlen),
    .m_axi_wstrb(write_master_m_axi_wstrb),
    .m_axi_wlast(write_master_m_axi_wlast),
    .s_tdata(write_master_s_tdata),
    .s_tvalid(write_master_s_tvalid),
    .s_tready(write_master_s_tready),
    .s_tkeep(write_master_s_tkeep)
  );
  DmaInfo dmaInfo (
    .addr(dmaInfo_addr),
    .blength(dmaInfo_blength),
    .offset(dmaInfo_offset),
    .wlength(dmaInfo_wlength)
  );
  assign s_axi_arready = axi_ctrl_s_axi_arready;
  assign s_axi_rdata = axi_ctrl_s_axi_rdata;
  assign s_axi_rresp = 2'h0;
  assign s_axi_rvalid = axi_ctrl_s_axi_rvalid;
  assign s_axi_awready = axi_ctrl_s_axi_awready;
  assign s_axi_wready = axi_ctrl_s_axi_wready;
  assign s_axi_bresp = 2'h0;
  assign s_axi_bvalid = axi_ctrl_s_axi_bvalid;
  assign m_axi_awaddr = write_master_m_axi_awaddr;
  assign m_axi_awvalid = write_master_m_axi_awvalid;
  assign m_axi_wdata = write_master_m_axi_wdata;
  assign m_axi_wvalid = write_master_m_axi_wvalid;
  assign m_axi_bready = 1'h1;
  assign m_axi_awlen = write_master_m_axi_awlen;
  assign m_axi_wstrb = write_master_m_axi_wstrb;
  assign m_axi_wlast = write_master_m_axi_wlast;
  assign s_axis_tready = write_master_s_tready;
  assign axi_ctrl_clock = clock;
  assign axi_ctrl_reset = reset;
  assign axi_ctrl_s_axi_araddr = s_axi_araddr;
  assign axi_ctrl_s_axi_arvalid = s_axi_arvalid;
  assign axi_ctrl_s_axi_rready = s_axi_rready;
  assign axi_ctrl_s_axi_awaddr = s_axi_awaddr;
  assign axi_ctrl_s_axi_awvalid = s_axi_awvalid;
  assign axi_ctrl_s_axi_wdata = s_axi_wdata;
  assign axi_ctrl_s_axi_wvalid = s_axi_wvalid;
  assign axi_ctrl_s_axi_bready = s_axi_bready;
  assign axi_ctrl_done = done;
  assign write_master_clock = clock;
  assign write_master_reset = reset;
  assign write_master_ctrl_start = axi_ctrl_start;
  assign write_master_ctrl_offset = dmaInfo_offset;
  assign write_master_ctrl_length = dmaInfo_wlength;
  assign write_master_m_axi_awready = m_axi_awready;
  assign write_master_m_axi_wready = m_axi_wready;
  assign write_master_m_axi_bvalid = m_axi_bvalid;
  assign write_master_s_tdata = s_axis_tdata;
  assign write_master_s_tvalid = s_axis_tvalid;
  assign write_master_s_tkeep = s_axis_tkeep;
  assign dmaInfo_addr = axi_ctrl_write_addr;
  assign dmaInfo_blength = axi_ctrl_write_length;
  always @(posedge clock) begin
    if (reset) begin
      done <= 1'h0;
    end else begin
      done <= write_master_ctrl_done | done;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  done = _RAND_0[0:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule