data/full_repos/permissive/421223411/verilog/rtl/accelerator/CoreTop.v
data/verilator_xmls/0e0a0b45-d48b-4011-aaf8-3dc66ac7878c.xml
module ALU(
  input  [15:0] io_in1,
  input  [15:0] io_in2,
  input  [3:0]  io_op,
  output [15:0] io_out,
  output        io_cc_z,
  output        io_cc_c,
  output        io_cc_n,
  output        io_cc_v
);
  wire  _T_2 = 4'h0 == io_op;
  wire [16:0] in1 = {{1'd0}, io_in1};
  wire [16:0] in2 = {{1'd0}, io_in2};
  wire [16:0] _result_T_1 = in1 + in2;
  wire  _T_5 = 4'h1 == io_op;
  wire [16:0] _result_T_2 = in1 & in2;
  wire  _T_8 = 4'h2 == io_op;
  wire [16:0] _result_T_3 = ~in1;
  wire  _T_11 = 4'h3 == io_op;
  wire [16:0] _result_T_4 = in1 | in2;
  wire  _T_14 = 4'h4 == io_op;
  wire [31:0] _GEN_22 = {{15'd0}, in1};
  wire [31:0] _result_T_6 = _GEN_22 << in2[3:0];
  wire  _T_17 = 4'h5 == io_op;
  wire [15:0] _result_T_8 = in1[15:0];
  wire [15:0] _result_T_10 = in2[15:0];
  wire  result_lo = $signed(_result_T_8) < $signed(_result_T_10);
  wire [15:0] _result_T_12 = {15'h0,result_lo};
  wire  _T_20 = 4'h6 == io_op;
  wire [15:0] _result_T_17 = $signed(_result_T_8) >>> in2[3:0];
  wire  _T_23 = 4'h7 == io_op;
  wire [16:0] _result_T_20 = in1 >> in2[3:0];
  wire  _T_26 = 4'h8 == io_op;
  wire [16:0] in1_minus_in2 = in1 - in2;
  wire  _T_29 = 4'h9 == io_op;
  wire [16:0] _result_T_21 = in1 ^ in2;
  wire [16:0] _GEN_0 = _T_29 ? _result_T_21 : 17'h0;
  wire [16:0] _GEN_1 = _T_26 ? in1_minus_in2 : _GEN_0;
  wire [16:0] _GEN_2 = _T_23 ? _result_T_20 : _GEN_1;
  wire [16:0] _GEN_3 = _T_20 ? {{1'd0}, _result_T_17} : _GEN_2;
  wire [16:0] _GEN_4 = _T_17 ? {{1'd0}, _result_T_12} : _GEN_3;
  wire [31:0] _GEN_5 = _T_14 ? _result_T_6 : {{15'd0}, _GEN_4};
  wire [31:0] _GEN_6 = _T_11 ? {{15'd0}, _result_T_4} : _GEN_5;
  wire [31:0] _GEN_7 = _T_8 ? {{15'd0}, _result_T_3} : _GEN_6;
  wire [31:0] _GEN_8 = _T_5 ? {{15'd0}, _result_T_2} : _GEN_7;
  wire [31:0] _GEN_9 = _T_2 ? {{15'd0}, _result_T_1} : _GEN_8;
  wire [16:0] result = _GEN_9[16:0];
  wire  _io_cc_z_T = io_out == 16'h0;
  wire  _io_cc_v_T_4 = ~io_out[15];
  wire  _io_cc_v_T_7 = ~in1[15];
  wire  _io_cc_v_T_9 = ~in2[15];
  wire  _io_cc_v_T_12 = ~in1[15] & ~in2[15] & io_out[15];
  wire  _io_cc_c_T_1 = in2 >= in1;
  wire  _io_cc_v_T_17 = in1[15] & _io_cc_v_T_9;
  wire  _io_cc_v_T_24 = _io_cc_v_T_7 & in2[15];
  wire  _io_cc_v_T_26 = _io_cc_v_T_7 & in2[15] & io_out[15];
  wire  _io_cc_v_T_40 = _io_cc_v_T_24 & in1_minus_in2[15];
  wire  _GEN_10 = io_op == 4'h5 ? in1_minus_in2 == 17'h0 : _io_cc_z_T;
  wire  _GEN_11 = io_op == 4'h5 & _io_cc_c_T_1;
  wire  _GEN_12 = io_op == 4'h5 ? in1_minus_in2[15] : result[15];
  wire  _GEN_13 = io_op == 4'h5 & (_io_cc_v_T_17 & ~in1_minus_in2[15] | _io_cc_v_T_40);
  wire  _GEN_14 = io_op == 4'h8 ? _io_cc_z_T : _GEN_10;
  wire  _GEN_15 = io_op == 4'h8 ? in2 >= in1 : _GEN_11;
  wire  _GEN_16 = io_op == 4'h8 ? result[15] : _GEN_12;
  wire  _GEN_17 = io_op == 4'h8 ? in1[15] & _io_cc_v_T_9 & _io_cc_v_T_4 | _io_cc_v_T_26 : _GEN_13;
  assign io_out = result[15:0];
  assign io_cc_z = io_op == 4'h0 ? io_out == 16'h0 : _GEN_14;
  assign io_cc_c = io_op == 4'h0 ? result[16] : _GEN_15;
  assign io_cc_n = io_op == 4'h0 ? result[15] : _GEN_16;
  assign io_cc_v = io_op == 4'h0 ? in1[15] & in2[15] & ~io_out[15] | _io_cc_v_T_12 : _GEN_17;
endmodule
module ALU(
  input  [15:0] io_in1,
  input  [15:0] io_in2,
  input  [3:0]  io_op,
  output [15:0] io_out,
  output        io_cc_z,
  output        io_cc_c,
  output        io_cc_n,
  output        io_cc_v
);

  wire  _T_2 = 4'h0 == io_op;
  wire [16:0] in1 = {{1'd0}, io_in1};
  wire [16:0] in2 = {{1'd0}, io_in2};
  wire [16:0] _result_T_1 = in1 + in2;
  wire  _T_5 = 4'h1 == io_op;
  wire [16:0] _result_T_2 = in1 & in2;
  wire  _T_8 = 4'h2 == io_op;
  wire [16:0] _result_T_3 = ~in1;
  wire  _T_11 = 4'h3 == io_op;
  wire [16:0] _result_T_4 = in1 | in2;
  wire  _T_14 = 4'h4 == io_op;
  wire [31:0] _GEN_22 = {{15'd0}, in1};
  wire [31:0] _result_T_6 = _GEN_22 << in2[3:0];
  wire  _T_17 = 4'h5 == io_op;
  wire [15:0] _result_T_8 = in1[15:0];
  wire [15:0] _result_T_10 = in2[15:0];
  wire  result_lo = $signed(_result_T_8) < $signed(_result_T_10);
  wire [15:0] _result_T_12 = {15'h0,result_lo};
  wire  _T_20 = 4'h6 == io_op;
  wire [15:0] _result_T_17 = $signed(_result_T_8) >>> in2[3:0];
  wire  _T_23 = 4'h7 == io_op;
  wire [16:0] _result_T_20 = in1 >> in2[3:0];
  wire  _T_26 = 4'h8 == io_op;
  wire [16:0] in1_minus_in2 = in1 - in2;
  wire  _T_29 = 4'h9 == io_op;
  wire [16:0] _result_T_21 = in1 ^ in2;
  wire [16:0] _GEN_0 = _T_29 ? _result_T_21 : 17'h0;
  wire [16:0] _GEN_1 = _T_26 ? in1_minus_in2 : _GEN_0;
  wire [16:0] _GEN_2 = _T_23 ? _result_T_20 : _GEN_1;
  wire [16:0] _GEN_3 = _T_20 ? {{1'd0}, _result_T_17} : _GEN_2;
  wire [16:0] _GEN_4 = _T_17 ? {{1'd0}, _result_T_12} : _GEN_3;
  wire [31:0] _GEN_5 = _T_14 ? _result_T_6 : {{15'd0}, _GEN_4};
  wire [31:0] _GEN_6 = _T_11 ? {{15'd0}, _result_T_4} : _GEN_5;
  wire [31:0] _GEN_7 = _T_8 ? {{15'd0}, _result_T_3} : _GEN_6;
  wire [31:0] _GEN_8 = _T_5 ? {{15'd0}, _result_T_2} : _GEN_7;
  wire [31:0] _GEN_9 = _T_2 ? {{15'd0}, _result_T_1} : _GEN_8;
  wire [16:0] result = _GEN_9[16:0];
  wire  _io_cc_z_T = io_out == 16'h0;
  wire  _io_cc_v_T_4 = ~io_out[15];
  wire  _io_cc_v_T_7 = ~in1[15];
  wire  _io_cc_v_T_9 = ~in2[15];
  wire  _io_cc_v_T_12 = ~in1[15] & ~in2[15] & io_out[15];
  wire  _io_cc_c_T_1 = in2 >= in1;
  wire  _io_cc_v_T_17 = in1[15] & _io_cc_v_T_9;
  wire  _io_cc_v_T_24 = _io_cc_v_T_7 & in2[15];
  wire  _io_cc_v_T_26 = _io_cc_v_T_7 & in2[15] & io_out[15];
  wire  _io_cc_v_T_40 = _io_cc_v_T_24 & in1_minus_in2[15];
  wire  _GEN_10 = io_op == 4'h5 ? in1_minus_in2 == 17'h0 : _io_cc_z_T;
  wire  _GEN_11 = io_op == 4'h5 & _io_cc_c_T_1;
  wire  _GEN_12 = io_op == 4'h5 ? in1_minus_in2[15] : result[15];
  wire  _GEN_13 = io_op == 4'h5 & (_io_cc_v_T_17 & ~in1_minus_in2[15] | _io_cc_v_T_40);
  wire  _GEN_14 = io_op == 4'h8 ? _io_cc_z_T : _GEN_10;
  wire  _GEN_15 = io_op == 4'h8 ? in2 >= in1 : _GEN_11;
  wire  _GEN_16 = io_op == 4'h8 ? result[15] : _GEN_12;
  wire  _GEN_17 = io_op == 4'h8 ? in1[15] & _io_cc_v_T_9 & _io_cc_v_T_4 | _io_cc_v_T_26 : _GEN_13;
  assign io_out = result[15:0];
  assign io_cc_z = io_op == 4'h0 ? io_out == 16'h0 : _GEN_14;
  assign io_cc_c = io_op == 4'h0 ? result[16] : _GEN_15;
  assign io_cc_n = io_op == 4'h0 ? result[15] : _GEN_16;
  assign io_cc_v = io_op == 4'h0 ? in1[15] & in2[15] & ~io_out[15] | _io_cc_v_T_12 : _GEN_17;
endmodule