data/full_repos/permissive/434840709/lab2/mux4bit/mux4bit2to1_version2.v
data/verilator_xmls/6f6ed941-e0c5-495d-990a-51737a5c1dda.xml
module mux4bit2to1(
    input [3:0] a,
    input [3:0] b,
    input s,
    output [3:0]y 
);
   
    reg [3:0] o;
    always @(*)begin
        if (s)begin
            o = a;
        end else begin
            o = b;
        end
    end
    assign y = o;
 

endmodule
module mux4bit2to1(
    input [3:0] a,
    input [3:0] b,
    input s,
    output [3:0]y 
);

   
    reg [3:0] o;
    always @(*)begin
        if (s)begin
            o = a;
        end else begin
            o = b;
        end
    end
    assign y = o;
 

endmodule