data/full_repos/permissive/509809169/Verilog Language/Modules_Hierarchy/adder-subtractor.v
1: b'%Error: Cannot find file containing module: Language/Modules_Hierarchy,data/full_repos/permissive/509809169\n        ... Looked in:\n             data/full_repos/permissive/509809169/Verilog/Language/Modules_Hierarchy,data/full_repos/permissive/509809169\n             data/full_repos/permissive/509809169/Verilog/Language/Modules_Hierarchy,data/full_repos/permissive/509809169.v\n             data/full_repos/permissive/509809169/Verilog/Language/Modules_Hierarchy,data/full_repos/permissive/509809169.sv\n             Language/Modules_Hierarchy,data/full_repos/permissive/509809169\n             Language/Modules_Hierarchy,data/full_repos/permissive/509809169.v\n             Language/Modules_Hierarchy,data/full_repos/permissive/509809169.sv\n             obj_dir/Language/Modules_Hierarchy,data/full_repos/permissive/509809169\n             obj_dir/Language/Modules_Hierarchy,data/full_repos/permissive/509809169.v\n             obj_dir/Language/Modules_Hierarchy,data/full_repos/permissive/509809169.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/509809169/Verilog\n%Error: Cannot find file containing module: Language/Modules_Hierarchy/adder-subtractor.v\n%Error: Exiting due to 3 error(s)\n'
module top_module(
    input [31:0] a,
    input [31:0] b,
    input sub,
    output [31:0] sum
);
    wire [31:0]w1;
    wire x,c;
    assign w1 = {32{sub}} ^ b;
    add16 ins1(a[15:0],w1[15:0],sub,sum[15:0],c);
    add16 ins2(a[31:16],w1[31:16],c,sum[31:16],x);

endmodule
module top_module(
    input [31:0] a,
    input [31:0] b,
    input sub,
    output [31:0] sum
);

    wire [31:0]w1;
    wire x,c;
    assign w1 = {32{sub}} ^ b;
    add16 ins1(a[15:0],w1[15:0],sub,sum[15:0],c);
    add16 ins2(a[31:16],w1[31:16],c,sum[31:16],x);

endmodule