data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v
1: b'%Error: data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v:6: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.v\n             data/full_repos/permissive/406635962/src/rtl,data/full_repos/permissive/406635962/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v:12: Define or directive not defined: \'`XLEN\'\n    output [`XLEN-1:0] lsu_o_wbck_data,\n            ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v:13: Define or directive not defined: \'`ITAG_WIDTH\'\n    output [`ITAG_WIDTH-1:0] lsu_o_wbck_itag,\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v:19: Define or directive not defined: \'`DTCM_ADDR_WIDTH\'\n    input [`DTCM_ADDR_WIDTH-1:0] agu_cmd_addr,\n           ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v:20: Define or directive not defined: \'`XLEN\'\n    input [`XLEN-1:0] agu_cmd_wdata,\n           ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v:21: Define or directive not defined: \'`XLEN\'\n    input [`XLEN/8-1:0] agu_cmd_wmask,\n           ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v:21: syntax error, unexpected \'/\', expecting TYPE-IDENTIFIER\n    input [`XLEN/8-1:0] agu_cmd_wmask,\n                ^\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v:22: Define or directive not defined: \'`ITAG_WIDTH\'\n    input [`ITAG_WIDTH-1:0] agu_cmd_itag,\n           ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v:32: Define or directive not defined: \'`DTCM_ADDR_WIDTH\'\n    output [`DTCM_ADDR_WIDTH-1:0] dtcm_cmd_addr,\n            ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v:33: Define or directive not defined: \'`XLEN\'\n    output [`XLEN-1:0] dtcm_cmd_wdata,\n            ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v:34: Define or directive not defined: \'`XLEN\'\n    output [`XLEN/8-1:0] dtcm_cmd_wmask,\n            ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v:37: Define or directive not defined: \'`XLEN\'\n    input [`XLEN-1:0] dtcm_rsp_rdata,\n           ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v:43: syntax error, unexpected assign\n    assign lsu_o_valid = wbck_hsked;\n    ^~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v:46: syntax error, unexpected assign\n    assign agu_cmd_ready = fifo_i_ready;  \n    ^~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v:59: Define or directive not defined: \'`ITAG_WIDTH\'\n    wire [`ITAG_WIDTH+6-1:0] agu_cmd_fifo_data = \n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v:71: Define or directive not defined: \'`ITAG_WIDTH\'\n    wire [`ITAG_WIDTH+6-1:0] agu_cmd_fifo_data_o;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v:72: syntax error, unexpected assign\n    assign lsu_o_wbck_itag= {`ITAG_WIDTH{wbck_hsked}} & agu_cmd_fifo_data_o;\n    ^~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v:72: Define or directive not defined: \'`ITAG_WIDTH\'\n    assign lsu_o_wbck_itag= {`ITAG_WIDTH{wbck_hsked}} & agu_cmd_fifo_data_o;\n                             ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v:73: Define or directive not defined: \'`ITAG_WIDTH\'\n    wire [`ITAG_WIDTH-1:0] agu_cmd_itag_o;\n          ^~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v:78: syntax error, unexpected assign\n    assign {agu_cmd_itag_o,\n    ^~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v:92: Define or directive not defined: \'`DTCM_ADDR_WIDTH\'\n    wire [`DTCM_ADDR_WIDTH-1:0]   pre_agu_rsp_addr;\n          ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v:93: syntax error, unexpected assign\n    assign   pre_agu_rsp_addr = dtcm_cmd_addr;\n    ^~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v:95: Define or directive not defined: \'`XLEN\'\n    wire [`XLEN-1:0] pre_agu_rsp_rdata;\n          ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v:96: syntax error, unexpected assign\n    assign pre_agu_rsp_rdata = dtcm_rsp_rdata;\n    ^~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v:97: Define or directive not defined: \'`XLEN\'\n    wire [`XLEN-1:0] rdata_algn= \n          ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v:102: syntax error, unexpected assign\n    assign lsu_o_wbck_data   =  {(({`XLEN{rsp_lb }} & {{24{rdata_algn[7]}}, rdata_algn[ 7:0]})\n    ^~~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v:102: Define or directive not defined: \'`XLEN\'\n    assign lsu_o_wbck_data   =  {(({`XLEN{rsp_lb }} & {{24{rdata_algn[7]}}, rdata_algn[ 7:0]})\n                                    ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v:103: Define or directive not defined: \'`XLEN\'\n                                | ({`XLEN{rsp_lh }} & {{16{rdata_algn[15]}}, rdata_algn[15:0]}) \n                                    ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v:104: Define or directive not defined: \'`XLEN\'\n                                | ({`XLEN{rsp_lw }} & rdata_algn[31:0])) \n                                    ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v:105: Define or directive not defined: \'`XLEN\'\n                                |({`XLEN{rsp_lbu }} & {{24\'b0}, rdata_algn[ 7:0]})\n                                   ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v:106: Define or directive not defined: \'`XLEN\'\n                                | ({`XLEN{rsp_lhu }} & {{16\'b0}, rdata_algn[15:0]})};\n                                    ^~~~~\n%Error: data/full_repos/permissive/406635962/src/rtl/lsu_ctrl.v:111: Define or directive not defined: \'`ITAG_WIDTH\'\n        .DW(`ITAG_WIDTH+6),\n            ^~~~~~~~~~~\n%Error: Exiting due to 32 error(s)\n'
module lsu_ctrl (

    output lsu_o_valid,
    input lsu_o_ready,
    output [`XLEN-1:0] lsu_o_wbck_data,
    output [`ITAG_WIDTH-1:0] lsu_o_wbck_itag,


    input agu_cmd_valid,
    output agu_cmd_ready,
    input agu_cmd_read,
    input [`DTCM_ADDR_WIDTH-1:0] agu_cmd_addr,
    input [`XLEN-1:0] agu_cmd_wdata,
    input [`XLEN/8-1:0] agu_cmd_wmask,
    input [`ITAG_WIDTH-1:0] agu_cmd_itag,
    input agu_cmd_usign,
    input [1:0] agu_cmd_size,
    output agu_rsp_valid,
    input agu_rsp_ready,


    output dtcm_cmd_valid,
    input dtcm_cmd_ready,
    output dtcm_cmd_read,
    output [`DTCM_ADDR_WIDTH-1:0] dtcm_cmd_addr,
    output [`XLEN-1:0] dtcm_cmd_wdata,
    output [`XLEN/8-1:0] dtcm_cmd_wmask,
    input dtcm_rsp_valid,
    output dtcm_rsp_ready,
    input [`XLEN-1:0] dtcm_rsp_rdata,
    
    input clk,
    input rst_n
);
   wire wbck_hsked = dtcm_rsp_ready & dtcm_rsp_valid;
    assign lsu_o_valid = wbck_hsked;

    wire fifo_i_ready;
    assign agu_cmd_ready = fifo_i_ready;
    assign agu_rsp_valid = wbck_hsked;
    
    assign dtcm_cmd_valid = agu_cmd_valid;
    assign dtcm_cmd_read = agu_cmd_read;
    assign dtcm_cmd_addr = agu_cmd_addr;
    assign dtcm_cmd_wdata = agu_cmd_wdata;
    assign dtcm_cmd_wmask = agu_cmd_wmask;
    assign dtcm_rsp_ready = 1'b1;



    wire [1:0] agu_cmd_addr_align_shift = agu_cmd_addr[1:0];
    wire [`ITAG_WIDTH+6-1:0] agu_cmd_fifo_data = 
                                                {agu_cmd_itag, 
                                                agu_cmd_read, 
                                                agu_cmd_usign, 
                                                agu_cmd_size,
                                                agu_cmd_addr_align_shift};

    
    wire fifo_i_valid = agu_cmd_valid;
   
    wire fifo_o_valid;
    wire fifo_o_ready = 1'b1;
    wire [`ITAG_WIDTH+6-1:0] agu_cmd_fifo_data_o;
    assign lsu_o_wbck_itag= {`ITAG_WIDTH{wbck_hsked}} & agu_cmd_fifo_data_o;
    wire [`ITAG_WIDTH-1:0] agu_cmd_itag_o;
    wire agu_cmd_read_o;
    wire [1:0] agu_cmd_size_o;
    wire agu_cmd_usign_o;
    wire [1:0] agu_cmd_cmd_align_shift_o;
    assign {agu_cmd_itag_o,
            agu_cmd_read_o,
            agu_cmd_usign_o,
            agu_cmd_size_o,
            agu_cmd_cmd_align_shift_o} = agu_cmd_fifo_data_o;

    wire [2-1:0]     pre_agu_rsp_size;
    wire rsp_lb   = (agu_cmd_size_o == 2'b00) & (agu_cmd_usign_o  == 1'b0);
    wire rsp_lh   = (agu_cmd_size_o == 2'b01) & (agu_cmd_usign_o  == 1'b0);

    wire rsp_lw   = (agu_cmd_size_o == 2'b10);
    wire rsp_lbu  = (agu_cmd_size_o == 2'b00) & (agu_cmd_usign_o  == 1'b1);
    wire rsp_lhu  = (agu_cmd_size_o == 2'b01) & (agu_cmd_usign_o  == 1'b1);

    wire [`DTCM_ADDR_WIDTH-1:0]   pre_agu_rsp_addr;
    assign   pre_agu_rsp_addr = dtcm_cmd_addr;

    wire [`XLEN-1:0] pre_agu_rsp_rdata;
    assign pre_agu_rsp_rdata = dtcm_rsp_rdata;
    wire [`XLEN-1:0] rdata_algn= 
      (pre_agu_rsp_rdata >> {agu_cmd_cmd_align_shift_o,3'b0});

    

    assign lsu_o_wbck_data   =  {(({`XLEN{rsp_lb }} & {{24{rdata_algn[7]}}, rdata_algn[ 7:0]})
                                | ({`XLEN{rsp_lh }} & {{16{rdata_algn[15]}}, rdata_algn[15:0]}) 
                                | ({`XLEN{rsp_lw }} & rdata_algn[31:0])) 
                                |({`XLEN{rsp_lbu }} & {{24'b0}, rdata_algn[ 7:0]})
                                | ({`XLEN{rsp_lhu }} & {{16'b0}, rdata_algn[15:0]})};

  

    gnrl_pipe_stage #(
        .DW(`ITAG_WIDTH+6),
        .DP(1)

    ) u_lsu_pipe_stage (
        .i_vld(fifo_i_valid),
        .i_rdy(fifo_i_ready),
        .i_dat(agu_cmd_fifo_data),
        .o_vld(fifo_o_valid),
        .o_rdy(fifo_o_ready),
        .o_dat(agu_cmd_fifo_data_o),
        .clk(clk),
        .rst_n(rst_n)
    );

    

    
    
  

endmodule
module lsu_ctrl (

    output lsu_o_valid,
    input lsu_o_ready,
    output [`XLEN-1:0] lsu_o_wbck_data,
    output [`ITAG_WIDTH-1:0] lsu_o_wbck_itag,


    input agu_cmd_valid,
    output agu_cmd_ready,
    input agu_cmd_read,
    input [`DTCM_ADDR_WIDTH-1:0] agu_cmd_addr,
    input [`XLEN-1:0] agu_cmd_wdata,
    input [`XLEN/8-1:0] agu_cmd_wmask,
    input [`ITAG_WIDTH-1:0] agu_cmd_itag,
    input agu_cmd_usign,
    input [1:0] agu_cmd_size,
    output agu_rsp_valid,
    input agu_rsp_ready,


    output dtcm_cmd_valid,
    input dtcm_cmd_ready,
    output dtcm_cmd_read,
    output [`DTCM_ADDR_WIDTH-1:0] dtcm_cmd_addr,
    output [`XLEN-1:0] dtcm_cmd_wdata,
    output [`XLEN/8-1:0] dtcm_cmd_wmask,
    input dtcm_rsp_valid,
    output dtcm_rsp_ready,
    input [`XLEN-1:0] dtcm_rsp_rdata,
    
    input clk,
    input rst_n
);

   wire wbck_hsked = dtcm_rsp_ready & dtcm_rsp_valid;
    assign lsu_o_valid = wbck_hsked;

    wire fifo_i_ready;
    assign agu_cmd_ready = fifo_i_ready;
    assign agu_rsp_valid = wbck_hsked;
    
    assign dtcm_cmd_valid = agu_cmd_valid;
    assign dtcm_cmd_read = agu_cmd_read;
    assign dtcm_cmd_addr = agu_cmd_addr;
    assign dtcm_cmd_wdata = agu_cmd_wdata;
    assign dtcm_cmd_wmask = agu_cmd_wmask;
    assign dtcm_rsp_ready = 1'b1;



    wire [1:0] agu_cmd_addr_align_shift = agu_cmd_addr[1:0];
    wire [`ITAG_WIDTH+6-1:0] agu_cmd_fifo_data = 
                                                {agu_cmd_itag, 
                                                agu_cmd_read, 
                                                agu_cmd_usign, 
                                                agu_cmd_size,
                                                agu_cmd_addr_align_shift};

    
    wire fifo_i_valid = agu_cmd_valid;
   
    wire fifo_o_valid;
    wire fifo_o_ready = 1'b1;
    wire [`ITAG_WIDTH+6-1:0] agu_cmd_fifo_data_o;
    assign lsu_o_wbck_itag= {`ITAG_WIDTH{wbck_hsked}} & agu_cmd_fifo_data_o;
    wire [`ITAG_WIDTH-1:0] agu_cmd_itag_o;
    wire agu_cmd_read_o;
    wire [1:0] agu_cmd_size_o;
    wire agu_cmd_usign_o;
    wire [1:0] agu_cmd_cmd_align_shift_o;
    assign {agu_cmd_itag_o,
            agu_cmd_read_o,
            agu_cmd_usign_o,
            agu_cmd_size_o,
            agu_cmd_cmd_align_shift_o} = agu_cmd_fifo_data_o;

    wire [2-1:0]     pre_agu_rsp_size;
    wire rsp_lb   = (agu_cmd_size_o == 2'b00) & (agu_cmd_usign_o  == 1'b0);
    wire rsp_lh   = (agu_cmd_size_o == 2'b01) & (agu_cmd_usign_o  == 1'b0);

    wire rsp_lw   = (agu_cmd_size_o == 2'b10);
    wire rsp_lbu  = (agu_cmd_size_o == 2'b00) & (agu_cmd_usign_o  == 1'b1);
    wire rsp_lhu  = (agu_cmd_size_o == 2'b01) & (agu_cmd_usign_o  == 1'b1);

    wire [`DTCM_ADDR_WIDTH-1:0]   pre_agu_rsp_addr;
    assign   pre_agu_rsp_addr = dtcm_cmd_addr;

    wire [`XLEN-1:0] pre_agu_rsp_rdata;
    assign pre_agu_rsp_rdata = dtcm_rsp_rdata;
    wire [`XLEN-1:0] rdata_algn= 
      (pre_agu_rsp_rdata >> {agu_cmd_cmd_align_shift_o,3'b0});

    

    assign lsu_o_wbck_data   =  {(({`XLEN{rsp_lb }} & {{24{rdata_algn[7]}}, rdata_algn[ 7:0]})
                                | ({`XLEN{rsp_lh }} & {{16{rdata_algn[15]}}, rdata_algn[15:0]}) 
                                | ({`XLEN{rsp_lw }} & rdata_algn[31:0])) 
                                |({`XLEN{rsp_lbu }} & {{24'b0}, rdata_algn[ 7:0]})
                                | ({`XLEN{rsp_lhu }} & {{16'b0}, rdata_algn[15:0]})};

  

    gnrl_pipe_stage #(
        .DW(`ITAG_WIDTH+6),
        .DP(1)

    ) u_lsu_pipe_stage (
        .i_vld(fifo_i_valid),
        .i_rdy(fifo_i_ready),
        .i_dat(agu_cmd_fifo_data),
        .o_vld(fifo_o_valid),
        .o_rdy(fifo_o_ready),
        .o_dat(agu_cmd_fifo_data_o),
        .clk(clk),
        .rst_n(rst_n)
    );

    

    
    
  

endmodule