data/full_repos/permissive/434840709/lab2/mux/mux3.v
data/verilator_xmls/cddf0499-69d0-4c39-9bae-aa8f7c877529.xml
module mux3(
    input wire [1:0] d,
    input wire a,
    output reg y
);
always@(*)
begin
    if(a == 1'b1)
        y = d[0];
    else
        y = d[1];
end
endmodule
module mux3(
    input wire [1:0] d,
    input wire a,
    output reg y
);

always@(*)
begin
    if(a == 1'b1)
        y = d[0];
    else
        y = d[1];
end
endmodule