data/full_repos/permissive/417288846/List_1/Task_1/D_latch_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/D_latch_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n        #1 d = 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/D_latch_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n        #1 clk = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/D_latch_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n        #2 d = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/D_latch_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #1 d = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/D_latch_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #2 clk = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/D_latch_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #1 clk = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/D_latch_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #2 clk = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/D_latch_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #1 clk = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/417288846/List_1/Task_1/D_latch_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #2 $finish;\n        ^\n%Error: data/full_repos/permissive/417288846/List_1/Task_1/D_latch_tb.v:28: Unsupported or unknown PLI call: $monitor\n    initial $monitor ($time, " d=%d, clk=%d out=%d", d, clk, out);\n            ^~~~~~~~\n%Error: Exiting due to 1 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench;
    reg d, clk;
    wire out;

    d_latch d1(.d(d), .clk(clk), .q(out));
    initial begin
        clk = 0;
        d = 0;

        #1 d = 1;
        clk = 1;
        #1 clk = 0;
        d = 0;

        #2 d = 1;
        clk = 1;
        #1 d = 0;
        clk = 0;

        #2 clk = 1;
        #1 clk = 0;

        #2 clk = 1;
        #1 clk = 0;

        #2 $finish;
    end
    initial $monitor ($time, " d=%d, clk=%d out=%d", d, clk, out);
endmodule
module testbench;

    reg d, clk;
    wire out;

    d_latch d1(.d(d), .clk(clk), .q(out));
    initial begin
        clk = 0;
        d = 0;

        #1 d = 1;
        clk = 1;
        #1 clk = 0;
        d = 0;

        #2 d = 1;
        clk = 1;
        #1 d = 0;
        clk = 0;

        #2 clk = 1;
        #1 clk = 0;

        #2 clk = 1;
        #1 clk = 0;

        #2 $finish;
    end
    initial $monitor ($time, " d=%d, clk=%d out=%d", d, clk, out);
endmodule