data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v
1: b'%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:190: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h1 )? 8\'h02 : 8\'h00\n              ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:190: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h1 )? 8\'h02 : 8\'h00\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:191: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h2 )? 8\'h04 : 8\'h00\n              ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:191: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h2 )? 8\'h04 : 8\'h00\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:192: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h3 )? 8\'h08 : 8\'h00\n              ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:192: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h3 )? 8\'h08 : 8\'h00\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:193: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h4 )? 8\'h10 : 8\'h00\n              ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:193: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h4 )? 8\'h10 : 8\'h00\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:194: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h5 )? 8\'h20 : 8\'h00\n              ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:194: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h5 )? 8\'h20 : 8\'h00\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:195: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h6 )? 8\'h40 : 8\'h00\n              ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:195: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h6 )? 8\'h40 : 8\'h00\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:196: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h7 )? 8\'h80 : 8\'h00\n              ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:196: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h7 )? 8\'h80 : 8\'h00\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:197: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h8 )? 8\'h1b : 8\'h00\n              ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:197: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h8 )? 8\'h1b : 8\'h00\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:198: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h9 )? 8\'h36 : 8\'h00;\n              ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:198: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n              | ( round_n == 4\'h9 )? 8\'h36 : 8\'h00;\n                                   ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:232: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h8 )? 8\'h02 : 8\'h00\n               ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:232: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h8 )? 8\'h02 : 8\'h00\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:233: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h7 )? 8\'h04 : 8\'h00\n               ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:233: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h7 )? 8\'h04 : 8\'h00\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:234: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h6 )? 8\'h08 : 8\'h00\n               ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:234: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h6 )? 8\'h08 : 8\'h00\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:235: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h5 )? 8\'h10 : 8\'h00\n               ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:235: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h5 )? 8\'h10 : 8\'h00\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:236: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h4 )? 8\'h20 : 8\'h00\n               ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:236: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h4 )? 8\'h20 : 8\'h00\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:237: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h3 )? 8\'h40 : 8\'h00\n               ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:237: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h3 )? 8\'h40 : 8\'h00\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:238: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h2 )? 8\'h80 : 8\'h00\n               ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:238: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h2 )? 8\'h80 : 8\'h00\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:239: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h1 )? 8\'h1b : 8\'h00\n               ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:239: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h1 )? 8\'h1b : 8\'h00\n                                    ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:240: Operator OR expects 8 bits on the RHS, but RHS\'s EQ generates 1 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h0 )? 8\'h36 : 8\'h00;\n               ^\n%Warning-WIDTH: data/full_repos/permissive/496194828/sasebo_giii_aes/aes128_table_ecb.v:240: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s OR generates 8 bits.\n                                                                                           : ... In instance aes128_table_ecb\n               | ( round_n == 4\'h0 )? 8\'h36 : 8\'h00;\n                                    ^\n%Error: Exiting due to 36 warning(s)\n'
module mixcolumns( 
  input     [7:0]  s0c, s1c, s2c, s3c,
  output    [7:0]  m0c, m1c, m2c, m3c
);




  assign m0c = mul4x8( {4'h2}, s0c ) ^ mul4x8( {4'h3}, s1c ) ^ mul4x8( {4'h1}, s2c ) ^ mul4x8( {4'h1}, s3c );
  assign m1c = mul4x8( {4'h1}, s0c ) ^ mul4x8( {4'h2}, s1c ) ^ mul4x8( {4'h3}, s2c ) ^ mul4x8( {4'h1}, s3c );
  assign m2c = mul4x8( {4'h1}, s0c ) ^ mul4x8( {4'h1}, s1c ) ^ mul4x8( {4'h2}, s2c ) ^ mul4x8( {4'h3}, s3c );
  assign m3c = mul4x8( {4'h3}, s0c ) ^ mul4x8( {4'h1}, s1c ) ^ mul4x8( {4'h1}, s2c ) ^ mul4x8( {4'h2}, s3c );


  function [7:0] mul4x8;
  input    [3:0] mx;
  input    [7:0] sc;

  reg      [7:0] sxm0, sxm1, sxm2, sxm3;
  reg     [10:0] temp;
  reg      [7:0] c0, c1, c2;

  begin
    sxm0 = sc & {8{mx[0]}};
    sxm1 = sc & {8{mx[1]}};
    sxm2 = sc & {8{mx[2]}};
    sxm3 = sc & {8{mx[3]}};

    temp = {3'b000, sxm0} ^ {2'b00, sxm1, 1'b0} ^ {1'b00, sxm2, 2'b00} ^ {sxm3, 3'b000};

    c0 = ( temp[ 8] == 1'b1 )? 8'h1B : 8'h00;
    c1 = ( temp[ 9] == 1'b1 )? (8'h1B << 1) : 8'h00;
    c2 = ( temp[10] == 1'b1 )? (8'h1B << 2) : 8'h00;

    mul4x8 = temp[7:0] ^ c0 ^ c1 ^ c2;
  end
  endfunction

endmodule
module mixcolumns( 
  input     [7:0]  s0c, s1c, s2c, s3c,
  output    [7:0]  m0c, m1c, m2c, m3c
);





  assign m0c = mul4x8( {4'h2}, s0c ) ^ mul4x8( {4'h3}, s1c ) ^ mul4x8( {4'h1}, s2c ) ^ mul4x8( {4'h1}, s3c );
  assign m1c = mul4x8( {4'h1}, s0c ) ^ mul4x8( {4'h2}, s1c ) ^ mul4x8( {4'h3}, s2c ) ^ mul4x8( {4'h1}, s3c );
  assign m2c = mul4x8( {4'h1}, s0c ) ^ mul4x8( {4'h1}, s1c ) ^ mul4x8( {4'h2}, s2c ) ^ mul4x8( {4'h3}, s3c );
  assign m3c = mul4x8( {4'h3}, s0c ) ^ mul4x8( {4'h1}, s1c ) ^ mul4x8( {4'h1}, s2c ) ^ mul4x8( {4'h2}, s3c );


  function [7:0] mul4x8;
  input    [3:0] mx;
  input    [7:0] sc;

  reg      [7:0] sxm0, sxm1, sxm2, sxm3;
  reg     [10:0] temp;
  reg      [7:0] c0, c1, c2;

  begin
    sxm0 = sc & {8{mx[0]}};
    sxm1 = sc & {8{mx[1]}};
    sxm2 = sc & {8{mx[2]}};
    sxm3 = sc & {8{mx[3]}};

    temp = {3'b000, sxm0} ^ {2'b00, sxm1, 1'b0} ^ {1'b00, sxm2, 2'b00} ^ {sxm3, 3'b000};

    c0 = ( temp[ 8] == 1'b1 )? 8'h1B : 8'h00;
    c1 = ( temp[ 9] == 1'b1 )? (8'h1B << 1) : 8'h00;
    c2 = ( temp[10] == 1'b1 )? (8'h1B << 2) : 8'h00;

    mul4x8 = temp[7:0] ^ c0 ^ c1 ^ c2;
  end
  endfunction

endmodule