data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_rxintf.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_rxintf.v:93: Cannot find file containing module: 'fflopx'\nfflopx #(1*2) ff2rxhctl (rxclk, rxrst_, {rxhctl, rxhctl_1}, {rxhctl_1, rxhctl_2});\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core,data/full_repos/permissive/530013823/fflopx\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core,data/full_repos/permissive/530013823/fflopx.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core,data/full_repos/permissive/530013823/fflopx.sv\n             fflopx\n             fflopx.v\n             fflopx.sv\n             obj_dir/fflopx\n             obj_dir/fflopx.v\n             obj_dir/fflopx.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_rxintf.v:94: Cannot find file containing module: 'fflopx'\nfflopx #(1*2) ff2rxlctl (rxclk, rxrst_, {rxlctl, rxlctl_1}, {rxlctl_1, rxlctl_2});\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_rxintf.v:96: Cannot find file containing module: 'fflopx'\nfflopx #(1*2) ff2rxherr (rxclk, rxrst_, {rxherr, rxherr_1}, {rxherr_1, rxherr_2});\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_rxintf.v:97: Cannot find file containing module: 'fflopx'\nfflopx #(1*2) ff2rxlerr (rxclk, rxrst_, {rxlerr, rxlerr_1}, {rxlerr_1, rxlerr_2});\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_rxintf.v:99: Cannot find file containing module: 'fflopx'\nfflopx #(DAT_DW*2) ff2rxhdat (rxclk, rxrst_, {rxhdat, rxhdat_1}, {rxhdat_1, rxhdat_2});\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/rsinv_test/ippackage/ipsmacge/core/ipsmacge_rxintf.v:100: Cannot find file containing module: 'fflopx'\nfflopx #(DAT_DW*2) ff2rxldat (rxclk, rxrst_, {rxldat, rxldat_1}, {rxldat_1, rxldat_2});\n^~~~~~\n%Error: Exiting due to 6 error(s)\n"
module ipsmacge_rxintf
    (
     rxrst_,
     rxclk,

     rxhdat,
     rxhctl,
     rxherr,
     rxldat,
     rxlctl,
     rxlerr,

     ogval,
     ogdat,
     ogdv,
     oger,

     up_act,
     up_pos,
     up_gmii,
     up_mspd
     );


parameter DAT_DW = 8;

parameter MSP_DW = 2;

parameter MRESERVE = 2'b11,
          M1000    = 2'b10,
          M100     = 2'b01,
          M10      = 2'b00;











input     rxrst_;
input     rxclk;

input [DAT_DW-1:0] rxhdat;
input [DAT_DW-1:0] rxldat;
input              rxhctl;
input              rxlctl;
input              rxherr;
input              rxlerr;

output [DAT_DW-1:0]ogdat;
output             ogdv;
output             oger;
output             ogval;

input              up_act;
input [MSP_DW-1:0] up_mspd;
input              up_gmii;
input              up_pos;


wire               rxhctl_1, rxhctl_2;
wire               rxlctl_1, rxlctl_2;

wire               rxherr_1, rxherr_2;
wire               rxlerr_1, rxlerr_2;

wire [DAT_DW-1:0]  rxhdat_1, rxhdat_2;
wire [DAT_DW-1:0]  rxldat_1, rxldat_2;

reg [DAT_DW-1:0]   ogdat;
reg                ogval;
reg                ogdv;
reg                oger;
reg                evalid;


fflopx #(1*2) ff2rxhctl (rxclk, rxrst_, {rxhctl, rxhctl_1}, {rxhctl_1, rxhctl_2});
fflopx #(1*2) ff2rxlctl (rxclk, rxrst_, {rxlctl, rxlctl_1}, {rxlctl_1, rxlctl_2});

fflopx #(1*2) ff2rxherr (rxclk, rxrst_, {rxherr, rxherr_1}, {rxherr_1, rxherr_2});
fflopx #(1*2) ff2rxlerr (rxclk, rxrst_, {rxlerr, rxlerr_1}, {rxlerr_1, rxlerr_2});

fflopx #(DAT_DW*2) ff2rxhdat (rxclk, rxrst_, {rxhdat, rxhdat_1}, {rxhdat_1, rxhdat_2});
fflopx #(DAT_DW*2) ff2rxldat (rxclk, rxrst_, {rxldat, rxldat_1}, {rxldat_1, rxldat_2});


always @ (posedge rxclk or negedge rxrst_)
    begin
    if (!rxrst_)                     evalid <= 1'b0;
    else if (!rxhctl_2 & rxhctl_1)   evalid <= 1'b1;
    else                             evalid <= ~evalid;
    end

always @ (posedge rxclk or negedge rxrst_)
    begin
    if (!rxrst_)
        begin
        ogdat <= {DAT_DW{1'b0}};
        ogval <= 1'b0;
        ogdv  <= 1'b0;
        oger  <= 1'b0;
        end
    else if (~up_act)
        begin
        ogdat <= {DAT_DW{1'b0}};
        ogval <= 1'b0;
        ogdv  <= 1'b0;
        oger  <= 1'b0;
        end
    else
        begin
        if (!up_gmii)
            begin
            case (up_mspd)
                MRESERVE:
                    begin
                    ogdat <= {DAT_DW{1'b0}};
                    ogval <= 1'b0;
                    ogdv  <= 1'b0;
                    oger  <= 1'b0;
                    end
                M1000:
                    begin
                    ogdat <= {rxldat_2 [3:0], rxhdat_2 [3:0]};
                    ogval <= 1'b1;
                    ogdv  <= rxhctl_2;
                    oger  <= rxhctl_2 ^ rxlctl_2;
                    end
                default:
                    begin
                    ogval <= evalid;
                    ogdat <= evalid ? (up_pos ? {rxhdat_1 [3:0], rxhdat_2 [3:0]} : {rxldat_1[3:0], rxldat_2 [3:0]}) : ogdat;
                    ogdv  <= rxhctl_2;
                    oger  <= rxhctl_2 ^ rxlctl_2;
                    end
            endcase
            end
        else
            begin
            case (up_mspd)
                MRESERVE:
                    begin
                    ogdat <= {DAT_DW{1'b0}};
                    ogval <= 1'b0;
                    ogdv  <= 1'b0;
                    oger  <= 1'b0;
                    end
                M1000:
                    begin
                    ogval <= 1'b1;
                    ogdat <= up_pos ? rxhdat_2 : rxldat_2;
                    ogdv  <= up_pos ? rxhctl_2 : rxlctl_2;
                    oger  <= up_pos ? rxherr_2 : rxlerr_2;
                    end
                default:
                    begin
                    ogval <= evalid;
                    ogdat <= evalid ? (up_pos ? {rxhdat_1 [3:0], rxhdat_2 [3:0]} : {rxldat_1[3:0], rxldat_2 [3:0]}) : ogdat;
                    ogdv  <= up_pos ? rxhctl_2 : rxlctl_2;
                    oger  <= up_pos ? rxherr_2 : rxlerr_2;
                    end
            endcase
            end
        end
    end

endmodule
module ipsmacge_rxintf
    (
     rxrst_,
     rxclk,

     rxhdat,
     rxhctl,
     rxherr,
     rxldat,
     rxlctl,
     rxlerr,

     ogval,
     ogdat,
     ogdv,
     oger,

     up_act,
     up_pos,
     up_gmii,
     up_mspd
     );



parameter DAT_DW = 8;

parameter MSP_DW = 2;

parameter MRESERVE = 2'b11,
          M1000    = 2'b10,
          M100     = 2'b01,
          M10      = 2'b00;











input     rxrst_;
input     rxclk;

input [DAT_DW-1:0] rxhdat;
input [DAT_DW-1:0] rxldat;
input              rxhctl;
input              rxlctl;
input              rxherr;
input              rxlerr;

output [DAT_DW-1:0]ogdat;
output             ogdv;
output             oger;
output             ogval;

input              up_act;
input [MSP_DW-1:0] up_mspd;
input              up_gmii;
input              up_pos;


wire               rxhctl_1, rxhctl_2;
wire               rxlctl_1, rxlctl_2;

wire               rxherr_1, rxherr_2;
wire               rxlerr_1, rxlerr_2;

wire [DAT_DW-1:0]  rxhdat_1, rxhdat_2;
wire [DAT_DW-1:0]  rxldat_1, rxldat_2;

reg [DAT_DW-1:0]   ogdat;
reg                ogval;
reg                ogdv;
reg                oger;
reg                evalid;


fflopx #(1*2) ff2rxhctl (rxclk, rxrst_, {rxhctl, rxhctl_1}, {rxhctl_1, rxhctl_2});
fflopx #(1*2) ff2rxlctl (rxclk, rxrst_, {rxlctl, rxlctl_1}, {rxlctl_1, rxlctl_2});

fflopx #(1*2) ff2rxherr (rxclk, rxrst_, {rxherr, rxherr_1}, {rxherr_1, rxherr_2});
fflopx #(1*2) ff2rxlerr (rxclk, rxrst_, {rxlerr, rxlerr_1}, {rxlerr_1, rxlerr_2});

fflopx #(DAT_DW*2) ff2rxhdat (rxclk, rxrst_, {rxhdat, rxhdat_1}, {rxhdat_1, rxhdat_2});
fflopx #(DAT_DW*2) ff2rxldat (rxclk, rxrst_, {rxldat, rxldat_1}, {rxldat_1, rxldat_2});


always @ (posedge rxclk or negedge rxrst_)
    begin
    if (!rxrst_)                     evalid <= 1'b0;
    else if (!rxhctl_2 & rxhctl_1)   evalid <= 1'b1;
    else                             evalid <= ~evalid;
    end

always @ (posedge rxclk or negedge rxrst_)
    begin
    if (!rxrst_)
        begin
        ogdat <= {DAT_DW{1'b0}};
        ogval <= 1'b0;
        ogdv  <= 1'b0;
        oger  <= 1'b0;
        end
    else if (~up_act)
        begin
        ogdat <= {DAT_DW{1'b0}};
        ogval <= 1'b0;
        ogdv  <= 1'b0;
        oger  <= 1'b0;
        end
    else
        begin
        if (!up_gmii)
            begin
            case (up_mspd)
                MRESERVE:
                    begin
                    ogdat <= {DAT_DW{1'b0}};
                    ogval <= 1'b0;
                    ogdv  <= 1'b0;
                    oger  <= 1'b0;
                    end
                M1000:
                    begin
                    ogdat <= {rxldat_2 [3:0], rxhdat_2 [3:0]};
                    ogval <= 1'b1;
                    ogdv  <= rxhctl_2;
                    oger  <= rxhctl_2 ^ rxlctl_2;
                    end
                default:
                    begin
                    ogval <= evalid;
                    ogdat <= evalid ? (up_pos ? {rxhdat_1 [3:0], rxhdat_2 [3:0]} : {rxldat_1[3:0], rxldat_2 [3:0]}) : ogdat;
                    ogdv  <= rxhctl_2;
                    oger  <= rxhctl_2 ^ rxlctl_2;
                    end
            endcase
            end
        else
            begin
            case (up_mspd)
                MRESERVE:
                    begin
                    ogdat <= {DAT_DW{1'b0}};
                    ogval <= 1'b0;
                    ogdv  <= 1'b0;
                    oger  <= 1'b0;
                    end
                M1000:
                    begin
                    ogval <= 1'b1;
                    ogdat <= up_pos ? rxhdat_2 : rxldat_2;
                    ogdv  <= up_pos ? rxhctl_2 : rxlctl_2;
                    oger  <= up_pos ? rxherr_2 : rxlerr_2;
                    end
                default:
                    begin
                    ogval <= evalid;
                    ogdat <= evalid ? (up_pos ? {rxhdat_1 [3:0], rxhdat_2 [3:0]} : {rxldat_1[3:0], rxldat_2 [3:0]}) : ogdat;
                    ogdv  <= up_pos ? rxhctl_2 : rxlctl_2;
                    oger  <= up_pos ? rxherr_2 : rxlerr_2;
                    end
            endcase
            end
        end
    end

endmodule