data/full_repos/permissive/447668373/SIPO/tb_sipo.v
1: b'%Error: data/full_repos/permissive/447668373/SIPO/tb_sipo.v:7: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("sipo_test.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/447668373/SIPO/tb_sipo.v:8: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, tb);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/447668373/SIPO/tb_sipo.v:9: Unsupported or unknown PLI call: $monitor\n        $monitor("time=",$time,", clk=%b, reset=%b,  d=%b, q=%b", clk, reset, d, q);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/447668373/SIPO/tb_sipo.v:14: Unsupported: Ignoring delay on this delayed statement.\n        forever #5 clk = ~clk;\n                ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/447668373/SIPO/tb_sipo.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #10 reset = 1\'b0; d = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/447668373/SIPO/tb_sipo.v:20: Unsupported: Ignoring delay on this delayed statement.\n        #10 d = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/447668373/SIPO/tb_sipo.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #10 d = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/447668373/SIPO/tb_sipo.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #10 d = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/447668373/SIPO/tb_sipo.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #50 $finish;\n        ^\n%Error: Exiting due to 3 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb;
    reg d, clk, reset;
    wire [3:0]q;
    sipo a(d, clk, reset, q);
    initial
    begin
        $dumpfile("sipo_test.vcd");
        $dumpvars(0, tb);
        $monitor("time=",$time,", clk=%b, reset=%b,  d=%b, q=%b", clk, reset, d, q);
    end
    initial
    begin
        clk = 1'b0;
        forever #5 clk = ~clk;
    end
    initial
    begin
        reset = 1'b1;
        #10 reset = 1'b0; d = 1;
        #10 d = 0;
        #10 d = 0;
        #10 d = 1;
        #50 $finish;
    end 
endmodule
module tb;

    reg d, clk, reset;
    wire [3:0]q;
    sipo a(d, clk, reset, q);
    initial
    begin
        $dumpfile("sipo_test.vcd");
        $dumpvars(0, tb);
        $monitor("time=",$time,", clk=%b, reset=%b,  d=%b, q=%b", clk, reset, d, q);
    end
    initial
    begin
        clk = 1'b0;
        forever #5 clk = ~clk;
    end
    initial
    begin
        reset = 1'b1;
        #10 reset = 1'b0; d = 1;
        #10 d = 0;
        #10 d = 0;
        #10 d = 1;
        #50 $finish;
    end 
endmodule