data/full_repos/permissive/463439324/keygen/poly_inverse.v
1: b'%Error: data/full_repos/permissive/463439324/keygen/poly_inverse.v:102: Cannot find file containing module: \'bram_p\'\n    bram_p #(.Q_DEPTH(Q_DEPTH),.D_SIZE(P_WIDTH))\n    ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/463439324/keygen,data/full_repos/permissive/463439324/bram_p\n             data/full_repos/permissive/463439324/keygen,data/full_repos/permissive/463439324/bram_p.v\n             data/full_repos/permissive/463439324/keygen,data/full_repos/permissive/463439324/bram_p.sv\n             bram_p\n             bram_p.v\n             bram_p.sv\n             obj_dir/bram_p\n             obj_dir/bram_p.v\n             obj_dir/bram_p.sv\n%Error: data/full_repos/permissive/463439324/keygen/poly_inverse.v:104: Cannot find file containing module: \'bram_p\'\n bram_p #(.Q_DEPTH(Q_DEPTH),.D_SIZE(P_WIDTH))\n ^~~~~~\n%Error: data/full_repos/permissive/463439324/keygen/poly_inverse.v:107: Cannot find file containing module: \'bram_p\'\n    bram_p #(.Q_DEPTH(Q_DEPTH),.D_SIZE(2*P_WIDTH))\n    ^~~~~~\n%Error: data/full_repos/permissive/463439324/keygen/poly_inverse.v:110: Cannot find file containing module: \'modmul4591S\'\n modmul4591S g_mod(.Clk(Clk), .Reset(Reset), .In(g), .Out(g_out));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/keygen/poly_inverse.v:111: Cannot find file containing module: \'modmul4591S\'\n    modmul4591S r_mod(.Clk(Clk), .Reset(Reset), .In(r), .Out(r_out));\n    ^~~~~~~~~~~\n%Error: data/full_repos/permissive/463439324/keygen/poly_inverse.v:113: Cannot find file containing module: \'inverse4591\'\n    inverse4591 inv0(.Clk(Clk), .Reset(Reset), .In(next_f0), .En(inverse_en), .Out(inverse_out), .Valid(inverse_valid));\n    ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/463439324/keygen/poly_inverse.v:328: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'counter_vr_w\' generates 11 bits.\n                                                                              : ... In instance poly_inverse\n        wr_addr_vr = counter_vr_w;\n                   ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/463439324/keygen/poly_inverse.v:340: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'counter_vr\' generates 11 bits.\n                                                                              : ... In instance poly_inverse\n            rd_addr_vr = counter_vr;\n                       ^\n%Warning-WIDTH: data/full_repos/permissive/463439324/keygen/poly_inverse.v:374: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s VARREF \'g0\' generates 13 bits.\n                                                                              : ... In instance poly_inverse\n                vg0 <= g0;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/463439324/keygen/poly_inverse.v:384: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS\'s VARREF \'f0\' generates 13 bits.\n                                                                              : ... In instance poly_inverse\n                rf0 <= f0;\n                    ^~\n%Warning-WIDTH: data/full_repos/permissive/463439324/keygen/poly_inverse.v:401: Operator EQ expects 32 or 11 bits on the LHS, but LHS\'s VARREF \'counter\' generates 10 bits.\n                                                                              : ... In instance poly_inverse\n            if (counter == counter_t + 3 || counter == 0 ) begin\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/463439324/keygen/poly_inverse.v:407: Operator EQ expects 32 or 11 bits on the LHS, but LHS\'s VARREF \'counter\' generates 10 bits.\n                                                                              : ... In instance poly_inverse\n            if (counter == counter_t + 3 || counter == 0) begin\n                        ^~\n%Warning-WIDTH: data/full_repos/permissive/463439324/keygen/poly_inverse.v:446: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h0\' generates 3 bits.\n                                                                              : ... In instance poly_inverse\n            state <= 3\'d0;\n                  ^~\n%Error: Exiting due to 6 error(s), 7 warning(s)\n'
module poly_inverse(
	Clk,
	Reset,
	Cmd,
	Addr,
	DI,
	DO,
	Valid
	);
    parameter P_WIDTH = 13;
	parameter Q_DEPTH = 10;
    parameter NTRU_Q = 4591;
	integer	  i;


	parameter IDLE = 0;
	parameter DATA_PUT = 1;
	parameter INVERSE = 2;
	parameter FINISH = 3;


	parameter input_data = 1;
	parameter write_f = 2;
	parameter write_g = 3;
	parameter start = 4;
    

    input						Clk;
	input						Reset;
	input		[2 : 0]			Cmd;
	input		[Q_DEPTH-1 : 0]	Addr;
	input		[P_WIDTH-1 : 0]	DI;
	output		[P_WIDTH-1 : 0]	DO;
	output reg					Valid;

    reg                         wr_en_f, wr_en_g;
    reg         [Q_DEPTH-1 : 0] wr_addr_f, wr_addr_g;
    reg  signed [P_WIDTH-1 : 0] wr_di_f, wr_di_g;
    reg         [Q_DEPTH-1 : 0] rd_addr_f, rd_addr_g;
    wire signed [P_WIDTH-1 : 0] wr_dout_f, wr_dout_g;
    wire signed [P_WIDTH-1 : 0] rd_dout_f, rd_dout_g;
    
    reg                    wr_en_vr;
    reg  [Q_DEPTH-1   : 0] wr_addr_vr;
    reg  [2*P_WIDTH-1 : 0] wr_di_vr;
    reg  [Q_DEPTH-1   : 0] rd_addr_vr;
    wire [2*P_WIDTH-1 : 0] wr_dout_vr;
    wire [2*P_WIDTH-1 : 0] rd_dout_vr;
    
    reg         [ 1 : 0]        state, next_state;
    reg         [ 9 : 0]        counter, counter_w;
    reg         [10 : 0]        counter_t, counter_vr, counter_vr_w;
    wire                        counter_end, counter_t_end;
    reg                         case1, case1_shift;
    wire                        case1_w;
    reg  signed [P_WIDTH-1 : 0] delta; 
    wire signed [P_WIDTH-1 : 0] g_out, r_out;
    reg  signed [P_WIDTH-1 : 0] f0, g0;
    reg  signed [P_WIDTH-1 : 0] g_temp, f_temp, f_shift_1, f_shift_2;
    reg  signed [P_WIDTH-1 : 0] f_shift_3, f_shift_4, f_shift_5, f_shift_6;
    reg  signed [23 : 0]        fg0, gf0;
    reg  signed [24 : 0]        fg, g;
    reg  signed [P_WIDTH-1 : 0] r_temp, v_temp, v_shift_1, v_shift_2;
    reg  signed [P_WIDTH-1 : 0] v_shift_3, v_shift_4, v_shift_5, v_shift_6;
    reg  signed [23 : 0]        vg0, rf0;
    reg  signed [24 : 0]        vr, r;
    reg                         v0, r0;
    reg                         inverse_en;
    wire                        inverse_valid;
    wire signed [P_WIDTH-1 : 0] inverse_out;
    wire signed [P_WIDTH-1 : 0] g00, f00;
    reg  signed [P_WIDTH-1 : 0] next_f0;


    bram_p #(.Q_DEPTH(Q_DEPTH),.D_SIZE(P_WIDTH))
		bram_f (.clk(Clk), .wr_en(wr_en_f), .wr_addr(wr_addr_f), .rd_addr(rd_addr_f), .wr_din(wr_di_f), .wr_dout(wr_dout_f), .rd_dout(rd_dout_f));
	bram_p #(.Q_DEPTH(Q_DEPTH),.D_SIZE(P_WIDTH))
		bram_g (.clk(Clk), .wr_en(wr_en_g), .wr_addr(wr_addr_g), .rd_addr(rd_addr_g), .wr_din(wr_di_g), .wr_dout(wr_dout_g), .rd_dout(rd_dout_g));
    
    bram_p #(.Q_DEPTH(Q_DEPTH),.D_SIZE(2*P_WIDTH))
		bram_vr (.clk(Clk), .wr_en(wr_en_vr), .wr_addr(wr_addr_vr), .rd_addr(rd_addr_vr), .wr_din(wr_di_vr), .wr_dout(wr_dout_vr), .rd_dout(rd_dout_vr));
	
	modmul4591S g_mod(.Clk(Clk), .Reset(Reset), .In(g), .Out(g_out));
    modmul4591S r_mod(.Clk(Clk), .Reset(Reset), .In(r), .Out(r_out));

    inverse4591 inv0(.Clk(Clk), .Reset(Reset), .In(next_f0), .En(inverse_en), .Out(inverse_out), .Valid(inverse_valid));


    assign counter_end = (counter == 763) ? 1 : 0;
    assign counter_t_end = (counter_t == 1522) ? 1 : 0;
    assign case1_w = (delta > 0 && g0 != 0) ? 1 : 0;

    always@(posedge Clk)begin
        if (wr_addr_f == 0) begin
            next_f0 <= wr_di_f;
        end else begin
            next_f0 <= next_f0;
        end
    end


    always@(posedge Clk)begin
        case1 <= case1_w;
        case1_shift <= case1;
    end


    always@(posedge Clk)begin
        if(state == INVERSE)begin
            if(counter_end)begin
                counter <= 0;
            end else begin
                counter <= counter + 1;
            end
        end else begin 
            counter <= 0;
        end

        if (counter == 7) begin
            counter_w <= 0;
        end else begin
            counter_w <= counter_w + 1;
        end

        if(state == INVERSE)begin
            if (counter_end) begin
                counter_t <= counter_t + 1;
            end else begin
                counter_t <= counter_t;
            end
        end else begin
            counter_t <= 0;
        end

        if (counter == 0) begin
            if (counter_t > 761) begin
                counter_vr <= 1;
            end else begin
                counter_vr <= 0;
            end
        end else begin
            counter_vr <= counter_vr + 1;
        end

        if (counter == 7) begin
            if (counter_t > 761) begin
                counter_vr_w <= 1;
            end else begin
                counter_vr_w <= 1;
            end
        end else begin
            counter_vr_w <= counter_vr_w + 1;
        end
    end


    always@(posedge Clk)begin
        if(next_state == DATA_PUT && Cmd == write_f)begin
            wr_en_f <= 1;
        end else if(state == INVERSE)begin
            if (counter == 7 && counter_t == 0) begin
                wr_en_f <= !wr_en_f;
            end else begin
                wr_en_f <= wr_en_f;
            end 
        end else begin
            wr_en_f <= 0;
        end

        if(next_state == DATA_PUT && Cmd == write_g)begin
            wr_en_g <= 1;
        end else if(state == INVERSE)begin
            if (counter == 7 && counter_t == 0) begin
                wr_en_g <= !wr_en_g;
            end else begin
                wr_en_g <= wr_en_g;
            end 
        end else begin
            wr_en_g <= 0;
        end
    end


    always@(*)begin
        if(state == DATA_PUT)begin
            wr_addr_f = Addr;
        end else begin 
            wr_addr_f = counter_w;
        end

        if(state == DATA_PUT)begin
            wr_addr_g = Addr;
        end else begin
            wr_addr_g = counter_w;
        end
    end


    always@(*)begin
        if(state == DATA_PUT)begin
            wr_di_f = DI;
        end else begin 
            wr_di_f = f_shift_6;
        end

        if(state == DATA_PUT)begin
            wr_di_g = DI;
        end else if (counter_w == 761) begin
            wr_di_g = 0;
        end else begin
            wr_di_g = g_out;
        end
    end


    always@(*)begin
        if(state == INVERSE)begin
            rd_addr_f = counter;
        end else begin
            rd_addr_f = Addr;
        end

        if(state == INVERSE)begin
            rd_addr_g = counter;
        end else begin
            rd_addr_g = Addr;
        end
    end


    always@(posedge Clk)begin
        if (state == INVERSE) begin
            if (counter_end) begin
                if (case1) begin
                    delta <= 1 - delta;
                end else begin
                    delta <= 1 + delta;
                end
            end else begin
                delta <= delta;
            end
        end else begin
            delta <= 1;
        end
    end


    always@(posedge Clk)begin
        if (state == INVERSE && counter == 1) begin
            f0 <= rd_dout_f;
        end else begin
            f0 <= f0;
        end

        if (state == INVERSE && counter == 1) begin
            g0 <= rd_dout_g;
        end else begin
            g0 <= g0;
        end
    end


    always@(posedge Clk)begin
        fg0 <= rd_dout_f * g0;
        gf0 <= rd_dout_g * f0;
        fg <= fg0 - gf0;
        if (case1) begin
            g <= fg;
        end else begin
            g <= -fg;
        end
        g_temp <= rd_dout_g;
        f_temp <= rd_dout_f;
        if (case1_w) begin
            f_shift_1 <= g_temp;
        end else begin
            f_shift_1 <= f_temp;
        end
        f_shift_2 <= f_shift_1;
        f_shift_3 <= f_shift_2;
        f_shift_4 <= f_shift_3;
        f_shift_5 <= f_shift_4;
        f_shift_6 <= f_shift_5;
    end


    always@(posedge Clk)begin
        if(state == INVERSE)begin
            if (counter == 7 && counter_t == 0) begin
                wr_en_vr <= !wr_en_vr;
            end else begin
                wr_en_vr <= wr_en_vr;
            end
        end else begin
            wr_en_vr <= 0;
        end
    end


    always@(*)begin
        wr_addr_vr = counter_vr_w;
    end


    always@(*)begin
        wr_di_vr = {v_shift_5, r_out};
    end

    always@(*)begin
        if (state == FINISH) begin
            rd_addr_vr = Addr;    
        end else begin
            rd_addr_vr = counter_vr;
        end
    end


    always@(posedge Clk)begin
        if (state == INVERSE) begin
            if (case1 && counter == 3) begin
                v0 <= r0;
            end else begin
                v0 <= v0;
            end
        end else begin
            v0 <= 0;
        end

        if (state == INVERSE) begin
            if (counter == 3) begin
                r0 <= 0;
            end else begin
                r0 <= r0;
            end
        end else begin
            r0 <= 1;
        end
    end

    assign g00 = (counter_t == 1521) ? inverse_out : g0;
    assign f00 = (counter_t == 1521) ? 0           : f0;


    always@(posedge Clk)begin
        if (counter_t < 762 && counter == 2) begin
            if (v0) begin
                vg0 <= g0;
            end else begin
                vg0 <= 0;
            end
        end else begin
            vg0 <= $signed(rd_dout_vr[2*P_WIDTH-1 : P_WIDTH]) * g00;
        end

        if (counter_t < 762 && counter == 2) begin
            if (r0) begin
                rf0 <= f0;
            end else begin
                rf0 <= 0;
            end
        end else begin
            rf0 <= $signed(rd_dout_vr[P_WIDTH-1 : 0]) * f00;
        end

        vr <= vg0 - rf0;

        if (case1_shift || (counter_t == 1521 && counter > 3) || counter_t_end) begin
            r <= vr;
        end else begin
            r <= -vr;
        end
        
        if (case1) begin
            if (counter == counter_t + 3 || counter == 0 ) begin
                v_shift_1 <= 0;
            end else begin
                v_shift_1 <= rd_dout_vr[P_WIDTH-1 : 0];
            end
        end else begin
            if (counter == counter_t + 3 || counter == 0) begin
                v_shift_1 <= 0;
            end else begin
                v_shift_1 <= rd_dout_vr[2*P_WIDTH-1 : P_WIDTH];
            end
        end

        v_shift_2 <= v_shift_1;
        v_shift_3 <= v_shift_2;
        v_shift_4 <= v_shift_3;
        v_shift_5 <= v_shift_4;
    end


    always@(*)begin
        if (counter_t == 1520 && counter == 100) begin
            inverse_en = 1;
        end else begin
            inverse_en = 0;
        end
    end




    assign DO = rd_dout_vr[P_WIDTH-1 : 0];


    always@(posedge Clk)begin
        if (state == FINISH) begin
            Valid <= 1;
        end else begin
            Valid <= 0;
        end
    end


	always@(posedge Clk)begin
		if(Reset) begin
            state <= 3'd0;
        end else begin
            state <= next_state;
        end
	end
	always@(*)begin
		case(state)
		IDLE: 
		begin
			if(Cmd == input_data)
				next_state = DATA_PUT;
			else
				next_state = IDLE;
		end
		DATA_PUT:
		begin
			if(Cmd == start)
				next_state = INVERSE;
			else
				next_state = DATA_PUT;
		end
		INVERSE: 
		begin
			if(counter == 5 && counter_t_end)
				next_state = FINISH;
			else
				next_state = INVERSE;
		end
		FINISH:
		begin
			next_state = FINISH;
		end
		default: next_state = state;
		endcase
	end

endmodule
module poly_inverse(
	Clk,
	Reset,
	Cmd,
	Addr,
	DI,
	DO,
	Valid
	);

    parameter P_WIDTH = 13;
	parameter Q_DEPTH = 10;
    parameter NTRU_Q = 4591;
	integer	  i;


	parameter IDLE = 0;
	parameter DATA_PUT = 1;
	parameter INVERSE = 2;
	parameter FINISH = 3;


	parameter input_data = 1;
	parameter write_f = 2;
	parameter write_g = 3;
	parameter start = 4;
    

    input						Clk;
	input						Reset;
	input		[2 : 0]			Cmd;
	input		[Q_DEPTH-1 : 0]	Addr;
	input		[P_WIDTH-1 : 0]	DI;
	output		[P_WIDTH-1 : 0]	DO;
	output reg					Valid;

    reg                         wr_en_f, wr_en_g;
    reg         [Q_DEPTH-1 : 0] wr_addr_f, wr_addr_g;
    reg  signed [P_WIDTH-1 : 0] wr_di_f, wr_di_g;
    reg         [Q_DEPTH-1 : 0] rd_addr_f, rd_addr_g;
    wire signed [P_WIDTH-1 : 0] wr_dout_f, wr_dout_g;
    wire signed [P_WIDTH-1 : 0] rd_dout_f, rd_dout_g;
    
    reg                    wr_en_vr;
    reg  [Q_DEPTH-1   : 0] wr_addr_vr;
    reg  [2*P_WIDTH-1 : 0] wr_di_vr;
    reg  [Q_DEPTH-1   : 0] rd_addr_vr;
    wire [2*P_WIDTH-1 : 0] wr_dout_vr;
    wire [2*P_WIDTH-1 : 0] rd_dout_vr;
    
    reg         [ 1 : 0]        state, next_state;
    reg         [ 9 : 0]        counter, counter_w;
    reg         [10 : 0]        counter_t, counter_vr, counter_vr_w;
    wire                        counter_end, counter_t_end;
    reg                         case1, case1_shift;
    wire                        case1_w;
    reg  signed [P_WIDTH-1 : 0] delta; 
    wire signed [P_WIDTH-1 : 0] g_out, r_out;
    reg  signed [P_WIDTH-1 : 0] f0, g0;
    reg  signed [P_WIDTH-1 : 0] g_temp, f_temp, f_shift_1, f_shift_2;
    reg  signed [P_WIDTH-1 : 0] f_shift_3, f_shift_4, f_shift_5, f_shift_6;
    reg  signed [23 : 0]        fg0, gf0;
    reg  signed [24 : 0]        fg, g;
    reg  signed [P_WIDTH-1 : 0] r_temp, v_temp, v_shift_1, v_shift_2;
    reg  signed [P_WIDTH-1 : 0] v_shift_3, v_shift_4, v_shift_5, v_shift_6;
    reg  signed [23 : 0]        vg0, rf0;
    reg  signed [24 : 0]        vr, r;
    reg                         v0, r0;
    reg                         inverse_en;
    wire                        inverse_valid;
    wire signed [P_WIDTH-1 : 0] inverse_out;
    wire signed [P_WIDTH-1 : 0] g00, f00;
    reg  signed [P_WIDTH-1 : 0] next_f0;


    bram_p #(.Q_DEPTH(Q_DEPTH),.D_SIZE(P_WIDTH))
		bram_f (.clk(Clk), .wr_en(wr_en_f), .wr_addr(wr_addr_f), .rd_addr(rd_addr_f), .wr_din(wr_di_f), .wr_dout(wr_dout_f), .rd_dout(rd_dout_f));
	bram_p #(.Q_DEPTH(Q_DEPTH),.D_SIZE(P_WIDTH))
		bram_g (.clk(Clk), .wr_en(wr_en_g), .wr_addr(wr_addr_g), .rd_addr(rd_addr_g), .wr_din(wr_di_g), .wr_dout(wr_dout_g), .rd_dout(rd_dout_g));
    
    bram_p #(.Q_DEPTH(Q_DEPTH),.D_SIZE(2*P_WIDTH))
		bram_vr (.clk(Clk), .wr_en(wr_en_vr), .wr_addr(wr_addr_vr), .rd_addr(rd_addr_vr), .wr_din(wr_di_vr), .wr_dout(wr_dout_vr), .rd_dout(rd_dout_vr));
	
	modmul4591S g_mod(.Clk(Clk), .Reset(Reset), .In(g), .Out(g_out));
    modmul4591S r_mod(.Clk(Clk), .Reset(Reset), .In(r), .Out(r_out));

    inverse4591 inv0(.Clk(Clk), .Reset(Reset), .In(next_f0), .En(inverse_en), .Out(inverse_out), .Valid(inverse_valid));


    assign counter_end = (counter == 763) ? 1 : 0;
    assign counter_t_end = (counter_t == 1522) ? 1 : 0;
    assign case1_w = (delta > 0 && g0 != 0) ? 1 : 0;

    always@(posedge Clk)begin
        if (wr_addr_f == 0) begin
            next_f0 <= wr_di_f;
        end else begin
            next_f0 <= next_f0;
        end
    end


    always@(posedge Clk)begin
        case1 <= case1_w;
        case1_shift <= case1;
    end


    always@(posedge Clk)begin
        if(state == INVERSE)begin
            if(counter_end)begin
                counter <= 0;
            end else begin
                counter <= counter + 1;
            end
        end else begin 
            counter <= 0;
        end

        if (counter == 7) begin
            counter_w <= 0;
        end else begin
            counter_w <= counter_w + 1;
        end

        if(state == INVERSE)begin
            if (counter_end) begin
                counter_t <= counter_t + 1;
            end else begin
                counter_t <= counter_t;
            end
        end else begin
            counter_t <= 0;
        end

        if (counter == 0) begin
            if (counter_t > 761) begin
                counter_vr <= 1;
            end else begin
                counter_vr <= 0;
            end
        end else begin
            counter_vr <= counter_vr + 1;
        end

        if (counter == 7) begin
            if (counter_t > 761) begin
                counter_vr_w <= 1;
            end else begin
                counter_vr_w <= 1;
            end
        end else begin
            counter_vr_w <= counter_vr_w + 1;
        end
    end


    always@(posedge Clk)begin
        if(next_state == DATA_PUT && Cmd == write_f)begin
            wr_en_f <= 1;
        end else if(state == INVERSE)begin
            if (counter == 7 && counter_t == 0) begin
                wr_en_f <= !wr_en_f;
            end else begin
                wr_en_f <= wr_en_f;
            end 
        end else begin
            wr_en_f <= 0;
        end

        if(next_state == DATA_PUT && Cmd == write_g)begin
            wr_en_g <= 1;
        end else if(state == INVERSE)begin
            if (counter == 7 && counter_t == 0) begin
                wr_en_g <= !wr_en_g;
            end else begin
                wr_en_g <= wr_en_g;
            end 
        end else begin
            wr_en_g <= 0;
        end
    end


    always@(*)begin
        if(state == DATA_PUT)begin
            wr_addr_f = Addr;
        end else begin 
            wr_addr_f = counter_w;
        end

        if(state == DATA_PUT)begin
            wr_addr_g = Addr;
        end else begin
            wr_addr_g = counter_w;
        end
    end


    always@(*)begin
        if(state == DATA_PUT)begin
            wr_di_f = DI;
        end else begin 
            wr_di_f = f_shift_6;
        end

        if(state == DATA_PUT)begin
            wr_di_g = DI;
        end else if (counter_w == 761) begin
            wr_di_g = 0;
        end else begin
            wr_di_g = g_out;
        end
    end


    always@(*)begin
        if(state == INVERSE)begin
            rd_addr_f = counter;
        end else begin
            rd_addr_f = Addr;
        end

        if(state == INVERSE)begin
            rd_addr_g = counter;
        end else begin
            rd_addr_g = Addr;
        end
    end


    always@(posedge Clk)begin
        if (state == INVERSE) begin
            if (counter_end) begin
                if (case1) begin
                    delta <= 1 - delta;
                end else begin
                    delta <= 1 + delta;
                end
            end else begin
                delta <= delta;
            end
        end else begin
            delta <= 1;
        end
    end


    always@(posedge Clk)begin
        if (state == INVERSE && counter == 1) begin
            f0 <= rd_dout_f;
        end else begin
            f0 <= f0;
        end

        if (state == INVERSE && counter == 1) begin
            g0 <= rd_dout_g;
        end else begin
            g0 <= g0;
        end
    end


    always@(posedge Clk)begin
        fg0 <= rd_dout_f * g0;
        gf0 <= rd_dout_g * f0;
        fg <= fg0 - gf0;
        if (case1) begin
            g <= fg;
        end else begin
            g <= -fg;
        end
        g_temp <= rd_dout_g;
        f_temp <= rd_dout_f;
        if (case1_w) begin
            f_shift_1 <= g_temp;
        end else begin
            f_shift_1 <= f_temp;
        end
        f_shift_2 <= f_shift_1;
        f_shift_3 <= f_shift_2;
        f_shift_4 <= f_shift_3;
        f_shift_5 <= f_shift_4;
        f_shift_6 <= f_shift_5;
    end


    always@(posedge Clk)begin
        if(state == INVERSE)begin
            if (counter == 7 && counter_t == 0) begin
                wr_en_vr <= !wr_en_vr;
            end else begin
                wr_en_vr <= wr_en_vr;
            end
        end else begin
            wr_en_vr <= 0;
        end
    end


    always@(*)begin
        wr_addr_vr = counter_vr_w;
    end


    always@(*)begin
        wr_di_vr = {v_shift_5, r_out};
    end

    always@(*)begin
        if (state == FINISH) begin
            rd_addr_vr = Addr;    
        end else begin
            rd_addr_vr = counter_vr;
        end
    end


    always@(posedge Clk)begin
        if (state == INVERSE) begin
            if (case1 && counter == 3) begin
                v0 <= r0;
            end else begin
                v0 <= v0;
            end
        end else begin
            v0 <= 0;
        end

        if (state == INVERSE) begin
            if (counter == 3) begin
                r0 <= 0;
            end else begin
                r0 <= r0;
            end
        end else begin
            r0 <= 1;
        end
    end

    assign g00 = (counter_t == 1521) ? inverse_out : g0;
    assign f00 = (counter_t == 1521) ? 0           : f0;


    always@(posedge Clk)begin
        if (counter_t < 762 && counter == 2) begin
            if (v0) begin
                vg0 <= g0;
            end else begin
                vg0 <= 0;
            end
        end else begin
            vg0 <= $signed(rd_dout_vr[2*P_WIDTH-1 : P_WIDTH]) * g00;
        end

        if (counter_t < 762 && counter == 2) begin
            if (r0) begin
                rf0 <= f0;
            end else begin
                rf0 <= 0;
            end
        end else begin
            rf0 <= $signed(rd_dout_vr[P_WIDTH-1 : 0]) * f00;
        end

        vr <= vg0 - rf0;

        if (case1_shift || (counter_t == 1521 && counter > 3) || counter_t_end) begin
            r <= vr;
        end else begin
            r <= -vr;
        end
        
        if (case1) begin
            if (counter == counter_t + 3 || counter == 0 ) begin
                v_shift_1 <= 0;
            end else begin
                v_shift_1 <= rd_dout_vr[P_WIDTH-1 : 0];
            end
        end else begin
            if (counter == counter_t + 3 || counter == 0) begin
                v_shift_1 <= 0;
            end else begin
                v_shift_1 <= rd_dout_vr[2*P_WIDTH-1 : P_WIDTH];
            end
        end

        v_shift_2 <= v_shift_1;
        v_shift_3 <= v_shift_2;
        v_shift_4 <= v_shift_3;
        v_shift_5 <= v_shift_4;
    end


    always@(*)begin
        if (counter_t == 1520 && counter == 100) begin
            inverse_en = 1;
        end else begin
            inverse_en = 0;
        end
    end




    assign DO = rd_dout_vr[P_WIDTH-1 : 0];


    always@(posedge Clk)begin
        if (state == FINISH) begin
            Valid <= 1;
        end else begin
            Valid <= 0;
        end
    end


	always@(posedge Clk)begin
		if(Reset) begin
            state <= 3'd0;
        end else begin
            state <= next_state;
        end
	end
	always@(*)begin
		case(state)
		IDLE: 
		begin
			if(Cmd == input_data)
				next_state = DATA_PUT;
			else
				next_state = IDLE;
		end
		DATA_PUT:
		begin
			if(Cmd == start)
				next_state = INVERSE;
			else
				next_state = DATA_PUT;
		end
		INVERSE: 
		begin
			if(counter == 5 && counter_t_end)
				next_state = FINISH;
			else
				next_state = INVERSE;
		end
		FINISH:
		begin
			next_state = FINISH;
		end
		default: next_state = state;
		endcase
	end

endmodule