data/full_repos/permissive/447976230/fpga/usrp1/megacells/sub32_bb.v
data/verilator_xmls/6833a8bf-7e86-48c3-91a5-441eb7182534.xml
module sub32 (
	dataa,
	datab,
	clock,
	aclr,
	clken,
	result);

	input	[31:0]  dataa;
	input	[31:0]  datab;
	input	  clock;
	input	  aclr;
	input	  clken;
	output	[31:0]  result;

endmodule
module sub32 (
	dataa,
	datab,
	clock,
	aclr,
	clken,
	result);


	input	[31:0]  dataa;
	input	[31:0]  datab;
	input	  clock;
	input	  aclr;
	input	  clken;
	output	[31:0]  result;

endmodule