data/full_repos/permissive/468612001/Week03/full_adder/tb_full_adder.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/468612001/Week03/full_adder/tb_full_adder.v:17: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/468612001/Week03/full_adder/tb_full_adder.v:7: Cannot find file containing module: \'full_adder\'\n full_adder U0(a, b, cin, sum, cout);\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/468612001/Week03/full_adder,data/full_repos/permissive/468612001/full_adder\n             data/full_repos/permissive/468612001/Week03/full_adder,data/full_repos/permissive/468612001/full_adder.v\n             data/full_repos/permissive/468612001/Week03/full_adder,data/full_repos/permissive/468612001/full_adder.sv\n             full_adder\n             full_adder.v\n             full_adder.sv\n             obj_dir/full_adder\n             obj_dir/full_adder.v\n             obj_dir/full_adder.sv\n%Warning-WIDTH: data/full_repos/permissive/468612001/Week03/full_adder/tb_full_adder.v:14: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s DIVS generates 32 bits.\n                                                                                         : ... In instance tb_full_adder\n    cin = k/4;\n        ^\n%Warning-WIDTH: data/full_repos/permissive/468612001/Week03/full_adder/tb_full_adder.v:15: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s DIVS generates 32 bits.\n                                                                                         : ... In instance tb_full_adder\n    b = (k%4)/2;\n      ^\n%Warning-WIDTH: data/full_repos/permissive/468612001/Week03/full_adder/tb_full_adder.v:16: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s MODDIVS generates 32 bits.\n                                                                                         : ... In instance tb_full_adder\n    a = k%2;\n      ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_full_adder();

	reg a, b, cin;
	wire sum, cout;
	integer k;
	
	full_adder U0(a, b, cin, sum, cout);
	
	initial
	begin
		forever
			for(k=0; k<8; k=k+1)
			begin
				cin = k/4;
				b = (k%4)/2;
				a = k%2;
				#10;
			end
		end
endmodule
module tb_full_adder();


	reg a, b, cin;
	wire sum, cout;
	integer k;
	
	full_adder U0(a, b, cin, sum, cout);
	
	initial
	begin
		forever
			for(k=0; k<8; k=k+1)
			begin
				cin = k/4;
				b = (k%4)/2;
				a = k%2;
				#10;
			end
		end
endmodule