data/full_repos/permissive/501700128/tb_ready_write.v
1: b'%Error: data/full_repos/permissive/501700128/tb_ready_write.v:8: Cannot find include file: Top.v\n`include "Top.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/501700128,data/full_repos/permissive/501700128/Top.v\n             data/full_repos/permissive/501700128,data/full_repos/permissive/501700128/Top.v.v\n             data/full_repos/permissive/501700128,data/full_repos/permissive/501700128/Top.v.sv\n             Top.v\n             Top.v.v\n             Top.v.sv\n             obj_dir/Top.v\n             obj_dir/Top.v.v\n             obj_dir/Top.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/501700128/tb_ready_write.v:25: Unsupported: Ignoring delay on this delayed statement.\n    forever  #5 clock = ~clock;\n             ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/501700128/tb_ready_write.v:33: Unsupported: Ignoring delay on this delayed statement.\n    #10 reset = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501700128/tb_ready_write.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #5\n    ^\n%Error: data/full_repos/permissive/501700128/tb_ready_write.v:38: syntax error, unexpected \'@\'\n    @(posedge clock) \n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501700128/tb_ready_write.v:37: Unsupported: Ignoring delay on this delayed statement.\n    #10 \n    ^\n%Error: data/full_repos/permissive/501700128/tb_ready_write.v:47: syntax error, unexpected \'@\'\n    @(posedge clock) \n    ^\n%Error: data/full_repos/permissive/501700128/tb_ready_write.v:57: syntax error, unexpected \'@\'\n    @(posedge clock)\n    ^\n%Error: data/full_repos/permissive/501700128/tb_ready_write.v:64: syntax error, unexpected \'@\'\n    @(posedge clock)\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/501700128/tb_ready_write.v:68: Unsupported: Ignoring delay on this delayed statement.\n    #100 $finish;\n    ^\n%Error: data/full_repos/permissive/501700128/tb_ready_write.v:74: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("top_dump.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/501700128/tb_ready_write.v:75: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, top_tb);\n    ^~~~~~~~~\n%Error: Exiting due to 7 error(s), 5 warning(s)\n'
module top_tb();

reg clock;
reg reset;
reg wr;
reg rd;
reg ready;
reg [3:0] length;
reg [3:0] address;
reg [31:0] wdata;
wire [31:0] rdata;

always begin 
    clock = 1'b0;
    forever  #5 clock = ~clock;
end 



initial begin
    #5

    #10 reset = 1'b1;

    wr = 1'b0;
    rd = 1'b0;
    #10 
    @(posedge clock) 
    reset = 1'b0;

    address = 4'h6;
    length = 4'h1;
    wdata = 4'hA;
    wr = 1'b1;
    rd = 1'b0;
    ready = 1'b0;
    @(posedge clock) 
    @(posedge clock) 
    @(posedge clock)
    ready = 1'b1; 
    @(posedge clock)
    address = 4'h7;
    length = 4'h3;
    wdata = 4'hB;
    wr = 1'b1;
    rd = 1'b0;
    @(posedge clock)
    address = 4'h0;
    length = 4'h0;
    ready = 1'b0;
    wdata = 4'hC;
    wr = 1'b0;
    rd = 1'b0;
    @(posedge clock)
    ready = 1'b1; 
    @(posedge clock)
    wdata = 4'hD;
    #100 $finish;
end


initial
begin
    $dumpfile("top_dump.vcd");
    $dumpvars(0, top_tb);
end

Top uut
(
  .clock(clock),
  .reset(reset),
  .io_top_wr(wr),
  .io_top_rd(rd),
  .io_top_address(address),
  .io_top_wdata(wdata),
  .io_top_rdata(rdata),
  .io_top_ready(ready),
  .io_top_length(length)
);

endmodule
module top_tb();


reg clock;
reg reset;
reg wr;
reg rd;
reg ready;
reg [3:0] length;
reg [3:0] address;
reg [31:0] wdata;
wire [31:0] rdata;

always begin 
    clock = 1'b0;
    forever  #5 clock = ~clock;
end 



initial begin
    #5

    #10 reset = 1'b1;

    wr = 1'b0;
    rd = 1'b0;
    #10 
    @(posedge clock) 
    reset = 1'b0;

    address = 4'h6;
    length = 4'h1;
    wdata = 4'hA;
    wr = 1'b1;
    rd = 1'b0;
    ready = 1'b0;
    @(posedge clock) 
    @(posedge clock) 
    @(posedge clock)
    ready = 1'b1; 
    @(posedge clock)
    address = 4'h7;
    length = 4'h3;
    wdata = 4'hB;
    wr = 1'b1;
    rd = 1'b0;
    @(posedge clock)
    address = 4'h0;
    length = 4'h0;
    ready = 1'b0;
    wdata = 4'hC;
    wr = 1'b0;
    rd = 1'b0;
    @(posedge clock)
    ready = 1'b1; 
    @(posedge clock)
    wdata = 4'hD;
    #100 $finish;
end


initial
begin
    $dumpfile("top_dump.vcd");
    $dumpvars(0, top_tb);
end

Top uut
(
  .clock(clock),
  .reset(reset),
  .io_top_wr(wr),
  .io_top_rd(rd),
  .io_top_address(address),
  .io_top_wdata(wdata),
  .io_top_rdata(rdata),
  .io_top_ready(ready),
  .io_top_length(length)
);

endmodule