data/full_repos/permissive/473778924/Basys3/DemoIO/FourSegDisplay.v
data/verilator_xmls/356eaf9a-e6e8-4768-ada8-21488615e920.xml
module SegmentDecoder (
  input             clk
, input             rst

, input             advAnode
, input             Blank
, input             Dpi
, input       [3:0] Digit

, output reg  [3:0] Anodes
, output reg  [6:0] Segments
, output wire       Dpo
);
  
  reg [3:0] pAnode = 4'b1111;
  reg [3:0] nAnode = 4'b1111;
  always @ (posedge clk or negedge rst)
    if( rst == 1'b0 )
      pAnode <= 4'b1111;
    else if( advAnode == 1'b1 )
      pAnode <= nAnode;
    else
      pAnode <= pAnode;
  
  always @*
    case(pAnode)
      4'b1110 : if( Blank ) Anodes <= 4'b1111; else Anodes <= 4'b1110; 
      4'b1101 : if( Blank ) Anodes <= 4'b1111; else Anodes <= 4'b1101;
      4'b1011 : if( Blank ) Anodes <= 4'b1111; else Anodes <= 4'b1011;
      4'b0111 : if( Blank ) Anodes <= 4'b1111; else Anodes <= 4'b0111;
      default : Anodes <= 4'b1111;
    endcase
  
  always @*
    case(pAnode)
      4'b1111 : nAnode <= 4'b0111;
      4'b1110 : nAnode <= 4'b0111; 
      4'b1101 : nAnode <= 4'b1110;
      4'b1011 : nAnode <= 4'b1101;
      4'b0111 : nAnode <= 4'b1011;
      default : nAnode <= 4'b1111;
    endcase
  
  assign Dpo = Dpi;
  always @*
    case(Digit)

      4'h0    : Segments = 7'b0_0_0_0_0_0_1;
      4'h1    : Segments = 7'b1_0_0_1_1_1_1;
      4'h2    : Segments = 7'b0_0_1_0_0_1_0;
      4'h3    : Segments = 7'b0_0_0_0_1_1_0;
      4'h4    : Segments = 7'b1_0_0_1_1_0_0;
      4'h5    : Segments = 7'b0_1_0_0_1_0_0;
      4'h6    : Segments = 7'b0_1_0_0_0_0_0;
      4'h7    : Segments = 7'b0_0_0_1_1_1_1;
      4'h8    : Segments = 7'b0_0_0_0_0_0_0;
      4'h9    : Segments = 7'b0_0_0_0_1_0_0;
      4'ha    : Segments = 7'b0_0_0_1_0_0_0;
      4'hb    : Segments = 7'b1_1_0_0_0_0_0;
      4'hc    : Segments = 7'b0_1_1_0_0_0_1;
      4'hd    : Segments = 7'b1_0_0_0_0_1_0;
      4'he    : Segments = 7'b0_1_1_0_0_0_0;
      4'hf    : Segments = 7'b0_1_1_1_0_0_0;
      default : Segments = 7'h7f;
    endcase

endmodule
module SegmentDecoder (
  input             clk
, input             rst

, input             advAnode
, input             Blank
, input             Dpi
, input       [3:0] Digit

, output reg  [3:0] Anodes
, output reg  [6:0] Segments
, output wire       Dpo
);

  
  reg [3:0] pAnode = 4'b1111;
  reg [3:0] nAnode = 4'b1111;
  always @ (posedge clk or negedge rst)
    if( rst == 1'b0 )
      pAnode <= 4'b1111;
    else if( advAnode == 1'b1 )
      pAnode <= nAnode;
    else
      pAnode <= pAnode;
  
  always @*
    case(pAnode)
      4'b1110 : if( Blank ) Anodes <= 4'b1111; else Anodes <= 4'b1110; 
      4'b1101 : if( Blank ) Anodes <= 4'b1111; else Anodes <= 4'b1101;
      4'b1011 : if( Blank ) Anodes <= 4'b1111; else Anodes <= 4'b1011;
      4'b0111 : if( Blank ) Anodes <= 4'b1111; else Anodes <= 4'b0111;
      default : Anodes <= 4'b1111;
    endcase
  
  always @*
    case(pAnode)
      4'b1111 : nAnode <= 4'b0111;
      4'b1110 : nAnode <= 4'b0111; 
      4'b1101 : nAnode <= 4'b1110;
      4'b1011 : nAnode <= 4'b1101;
      4'b0111 : nAnode <= 4'b1011;
      default : nAnode <= 4'b1111;
    endcase
  
  assign Dpo = Dpi;
  always @*
    case(Digit)

      4'h0    : Segments = 7'b0_0_0_0_0_0_1;
      4'h1    : Segments = 7'b1_0_0_1_1_1_1;
      4'h2    : Segments = 7'b0_0_1_0_0_1_0;
      4'h3    : Segments = 7'b0_0_0_0_1_1_0;
      4'h4    : Segments = 7'b1_0_0_1_1_0_0;
      4'h5    : Segments = 7'b0_1_0_0_1_0_0;
      4'h6    : Segments = 7'b0_1_0_0_0_0_0;
      4'h7    : Segments = 7'b0_0_0_1_1_1_1;
      4'h8    : Segments = 7'b0_0_0_0_0_0_0;
      4'h9    : Segments = 7'b0_0_0_0_1_0_0;
      4'ha    : Segments = 7'b0_0_0_1_0_0_0;
      4'hb    : Segments = 7'b1_1_0_0_0_0_0;
      4'hc    : Segments = 7'b0_1_1_0_0_0_1;
      4'hd    : Segments = 7'b1_0_0_0_0_1_0;
      4'he    : Segments = 7'b0_1_1_0_0_0_0;
      4'hf    : Segments = 7'b0_1_1_1_0_0_0;
      default : Segments = 7'h7f;
    endcase

endmodule