data/full_repos/permissive/489392257/1.9.8/tang-nano-2704/src/top.v
1: b'%Error: data/full_repos/permissive/489392257/1.9.8/tang-nano-2704/src/top.v:31: Cannot find file containing module: \'pll_lcd_ae\'\n pll_lcd_ae chip_pll(\n ^~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/489392257/1.9.8/tang-nano-2704/src,data/full_repos/permissive/489392257/pll_lcd_ae\n             data/full_repos/permissive/489392257/1.9.8/tang-nano-2704/src,data/full_repos/permissive/489392257/pll_lcd_ae.v\n             data/full_repos/permissive/489392257/1.9.8/tang-nano-2704/src,data/full_repos/permissive/489392257/pll_lcd_ae.sv\n             pll_lcd_ae\n             pll_lcd_ae.v\n             pll_lcd_ae.sv\n             obj_dir/pll_lcd_ae\n             obj_dir/pll_lcd_ae.v\n             obj_dir/pll_lcd_ae.sv\n%Error: data/full_repos/permissive/489392257/1.9.8/tang-nano-2704/src/top.v:37: Cannot find file containing module: \'vga\'\n vga vga_inst\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/489392257/1.9.8/tang-nano-2704/src/top.v:62: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n                                                                                      : ... In instance top\n   Count <= 4\'b0;\n         ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module top
(
	input           ARST_N,
	input           XTAL_IN,

	output          LCD_CLK,
	output          LCD_HSYNC,
	output          LCD_VSYNC,
	output          LCD_DEN,
	output  [4:0]   LCD_R,
	output  [5:0]   LCD_G,
	output  [4:0]   LCD_B,

	output          LED_R,
	output          LED_G,
	output          LED_B,
	input           KEY,
	input           GPIO
);

	wire            CLK_SYS;
	wire            CLK_PIX;
	wire            oscout_o;


	pll_lcd_ae chip_pll(
		.clkout(CLK_SYS),
		.clkoutd(CLK_PIX),
		.clkin(XTAL_IN)
	);

	vga vga_inst
	(
		.CLK      (CLK_SYS),
		.nRST     (ARST_N),

		.PixelClk (CLK_PIX),
		.LCD_DE   (LCD_DEN),
		.LCD_HSYNC(LCD_HSYNC),
		.LCD_VSYNC(LCD_VSYNC),

		.LCD_B    (LCD_B),
		.LCD_G    (LCD_G),
		.LCD_R    (LCD_R)
	);

	assign LCD_CLK = CLK_PIX;


	reg     [31:0]  Count;
	reg     [1:0]   rgb_data;
	always @ (posedge CLK_SYS or negedge ARST_N) begin
		if (!ARST_N) begin
			Count <= 32'd0;
			rgb_data <= 2'b00;
		end else if (Count == 10000000) begin
			Count <= 4'b0;
			rgb_data <= rgb_data + 1'b1;
		end else begin
			Count <= Count + 1'b1;
		end
	end
	assign LED_R = ~(rgb_data == 2'b01);
	assign LED_G = ~(rgb_data == 2'b10);
	assign LED_B = ~(rgb_data == 2'b11);
endmodule
module top
(
	input           ARST_N,
	input           XTAL_IN,

	output          LCD_CLK,
	output          LCD_HSYNC,
	output          LCD_VSYNC,
	output          LCD_DEN,
	output  [4:0]   LCD_R,
	output  [5:0]   LCD_G,
	output  [4:0]   LCD_B,

	output          LED_R,
	output          LED_G,
	output          LED_B,
	input           KEY,
	input           GPIO
);


	wire            CLK_SYS;
	wire            CLK_PIX;
	wire            oscout_o;


	pll_lcd_ae chip_pll(
		.clkout(CLK_SYS),
		.clkoutd(CLK_PIX),
		.clkin(XTAL_IN)
	);

	vga vga_inst
	(
		.CLK      (CLK_SYS),
		.nRST     (ARST_N),

		.PixelClk (CLK_PIX),
		.LCD_DE   (LCD_DEN),
		.LCD_HSYNC(LCD_HSYNC),
		.LCD_VSYNC(LCD_VSYNC),

		.LCD_B    (LCD_B),
		.LCD_G    (LCD_G),
		.LCD_R    (LCD_R)
	);

	assign LCD_CLK = CLK_PIX;


	reg     [31:0]  Count;
	reg     [1:0]   rgb_data;
	always @ (posedge CLK_SYS or negedge ARST_N) begin
		if (!ARST_N) begin
			Count <= 32'd0;
			rgb_data <= 2'b00;
		end else if (Count == 10000000) begin
			Count <= 4'b0;
			rgb_data <= rgb_data + 1'b1;
		end else begin
			Count <= Count + 1'b1;
		end
	end
	assign LED_R = ~(rgb_data == 2'b01);
	assign LED_G = ~(rgb_data == 2'b10);
	assign LED_B = ~(rgb_data == 2'b11);
endmodule