data/full_repos/permissive/452305748/L1/nand_gate/nand_gate_tb.v
1: b'%Error: data/full_repos/permissive/452305748/L1/nand_gate/nand_gate_tb.v:11: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("wave.vcd");         \n        ^~~~~~~~~\n%Error: data/full_repos/permissive/452305748/L1/nand_gate/nand_gate_tb.v:12: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, nand_gate_tb);     \n        ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/452305748/L1/nand_gate/nand_gate_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #10 aa <= 0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/452305748/L1/nand_gate/nand_gate_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n        #10 aa <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452305748/L1/nand_gate/nand_gate_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n        #10 aa <= 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452305748/L1/nand_gate/nand_gate_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n        #10 aa <= 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/452305748/L1/nand_gate/nand_gate_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n        #10 $stop;\n        ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module nand_gate_tb; 
reg aa, bb; 
wire yy; 
nand_gate nand_gate(.A(aa), .B(bb), .Y(yy));
    

    initial
    begin
        $dumpfile("wave.vcd");
        $dumpvars(0, nand_gate_tb);
    end

    
    initial begin
        aa     <= 0;
        bb     <= 0;
        #10 aa <= 0;
        bb     <= 1;
        #10 aa <= 1;
        bb     <= 0;
        #10 aa <= 1;
        bb     <= 1;
        #10 aa <= 0;
        bb     <= 0;
        #10 $stop;
    end
endmodule
module nand_gate_tb;
 
reg aa, bb; 
wire yy; 
nand_gate nand_gate(.A(aa), .B(bb), .Y(yy));
    

    initial
    begin
        $dumpfile("wave.vcd");
        $dumpvars(0, nand_gate_tb);
    end

    
    initial begin
        aa     <= 0;
        bb     <= 0;
        #10 aa <= 0;
        bb     <= 1;
        #10 aa <= 1;
        bb     <= 0;
        #10 aa <= 1;
        bb     <= 1;
        #10 aa <= 0;
        bb     <= 0;
        #10 $stop;
    end
endmodule