data/full_repos/permissive/419232407/verilog/dv/subservient_blinky/subservient_blinky_tb.v
1: b'%Error: data/full_repos/permissive/419232407/verilog/dv/subservient_blinky/subservient_blinky_tb.v:22: Cannot find include file: uprj_netlists.v\n `include "uprj_netlists.v" \n          ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/419232407/verilog/dv/subservient_blinky,data/full_repos/permissive/419232407/uprj_netlists.v\n             data/full_repos/permissive/419232407/verilog/dv/subservient_blinky,data/full_repos/permissive/419232407/uprj_netlists.v.v\n             data/full_repos/permissive/419232407/verilog/dv/subservient_blinky,data/full_repos/permissive/419232407/uprj_netlists.v.sv\n             uprj_netlists.v\n             uprj_netlists.v.v\n             uprj_netlists.v.sv\n             obj_dir/uprj_netlists.v\n             obj_dir/uprj_netlists.v.v\n             obj_dir/uprj_netlists.v.sv\n%Error: data/full_repos/permissive/419232407/verilog/dv/subservient_blinky/subservient_blinky_tb.v:23: Cannot find include file: caravel_netlists.v\n `include "caravel_netlists.v" \n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/419232407/verilog/dv/subservient_blinky/subservient_blinky_tb.v:24: Cannot find include file: spiflash.v\n `include "spiflash.v" \n          ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/419232407/verilog/dv/subservient_blinky/subservient_blinky_tb.v:25: Cannot find include file: tbuart.v\n `include "tbuart.v" \n          ^~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/419232407/verilog/dv/subservient_blinky/subservient_blinky_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n    always #10 clock <= (clock == 1\'b0);\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/419232407/verilog/dv/subservient_blinky/subservient_blinky_tb.v:67: Unsupported or unknown PLI call: $dumpfile\n        $dumpfile("subservient_blinky.vcd");\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/419232407/verilog/dv/subservient_blinky/subservient_blinky_tb.v:68: Unsupported or unknown PLI call: $dumpvars\n        $dumpvars(0, subservient_blinky_tb);\n        ^~~~~~~~~\n%Error: data/full_repos/permissive/419232407/verilog/dv/subservient_blinky/subservient_blinky_tb.v:70: syntax error, unexpected \'@\'\n            repeat (400) @(posedge clock);\n                         ^\n%Warning-STMTDLY: data/full_repos/permissive/419232407/verilog/dv/subservient_blinky/subservient_blinky_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n        #2000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/419232407/verilog/dv/subservient_blinky/subservient_blinky_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n        #170000;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/419232407/verilog/dv/subservient_blinky/subservient_blinky_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n        #100;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/419232407/verilog/dv/subservient_blinky/subservient_blinky_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/419232407/verilog/dv/subservient_blinky/subservient_blinky_tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/419232407/verilog/dv/subservient_blinky/subservient_blinky_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/419232407/verilog/dv/subservient_blinky/subservient_blinky_tb.v:107: Unsupported: wait statements\n        wait(mprj_io[31:0] == 1);\n        ^~~~\n%Error: data/full_repos/permissive/419232407/verilog/dv/subservient_blinky/subservient_blinky_tb.v:108: Unsupported: wait statements\n        wait(mprj_io[31:0] == 0);\n        ^~~~\n%Error: data/full_repos/permissive/419232407/verilog/dv/subservient_blinky/subservient_blinky_tb.v:110: Unsupported: wait statements\n        wait(mprj_io[31:0] == 1);\n        ^~~~\n%Error: data/full_repos/permissive/419232407/verilog/dv/subservient_blinky/subservient_blinky_tb.v:111: Unsupported: wait statements\n        wait(mprj_io[31:0] == 0);\n        ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/419232407/verilog/dv/subservient_blinky/subservient_blinky_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n        #1000;\n        ^\n%Error: Exiting due to 11 error(s), 8 warning(s)\n'
module subservient_blinky_tb;

    reg clock;
    reg RSTB;
    reg CSB;
    reg power1, power2;
    reg power3, power4;

    wire HIGH;
    wire LOW;
    wire TRI;
    assign HIGH = 1'b1;
    assign LOW = 1'b0;
    assign TRI = 1'bz;

    wire gpio;

    wire uart_tx;
    wire [37:0] mprj_io;
 

    wire flash_csb;
    wire flash_clk;
    wire flash_io0;
    wire flash_io1;

    wire VDD3V3 = power1;
    wire VDD1V8 = power2;
    wire USER_VDD3V3 = power3;
	wire USER_VDD1V8 = power4;
    wire VSS = 1'b0;


    always #10 clock <= (clock == 1'b0);

    initial begin
        clock = 0;
    end

    initial begin
        $dumpfile("subservient_blinky.vcd");
        $dumpvars(0, subservient_blinky_tb);
        repeat (150) begin
            repeat (400) @(posedge clock);
        end
        $display("%c[1;31m",27);
        $display ("Monitor: Timeout, Subservient blinky test failed");
        $display("%c[0m",27);
        $finish;
    end


    initial begin
        RSTB <= 1'b0;
        CSB  <= 1'b1;
        #2000;
        RSTB <= 1'b1;
        #170000;
        CSB = 1'b0;
    end

    initial begin
        power1 <= 1'b0;
        power2 <= 1'b0;
        power3 <= 1'b0;
        power4 <= 1'b0;
        #100;
	power1 <= 1'b1;
	#100;
	power2 <= 1'b1;
	#100;
	power3 <= 1'b1;
	#100;
	power4 <= 1'b1;
    end


    initial begin
        $display("Monitor: subservient blinky test started");

        wait(mprj_io[31:0] == 1);
        wait(mprj_io[31:0] == 0);
        $display("Monitor: gpio switched once.");
        wait(mprj_io[31:0] == 1);
        wait(mprj_io[31:0] == 0);
        $display("Monitor: gpio switched twice.");
        $display("Monitor: subservient blinky test Passed");
        #1000;
        $finish;
    end
    
    caravel dut (
        .vddio	  (VDD3V3),
        .vssio	  (VSS),
        .vdda	  (VDD3V3),
        .vssa	  (VSS),
        .vccd	  (VDD1V8),
        .vssd	  (VSS),
        .vdda1    (USER_VDD3V3),
        .vdda2    (USER_VDD3V3),
        .vssa1	  (VSS),
        .vssa2	  (VSS),
        .vccd1	  (USER_VDD1V8),
        .vccd2	  (USER_VDD1V8),
        .vssd1	  (VSS),
        .vssd2	  (VSS),
        .clock	  (clock),
        .gpio     (gpio),
        .mprj_io  (mprj_io),
        .flash_csb(flash_csb),
        .flash_clk(flash_clk),
        .flash_io0(flash_io0),
        .flash_io1(flash_io1),
        .resetb	  (RSTB)
    );

    spiflash #(
        .FILENAME("subservient_blinky.hex")
    ) spiflash (
        .csb(flash_csb),
        .clk(flash_clk),
        .io0(flash_io0),
        .io1(flash_io1),
        .io2(),
        .io3()
    );

 endmodule
module subservient_blinky_tb;


    reg clock;
    reg RSTB;
    reg CSB;
    reg power1, power2;
    reg power3, power4;

    wire HIGH;
    wire LOW;
    wire TRI;
    assign HIGH = 1'b1;
    assign LOW = 1'b0;
    assign TRI = 1'bz;

    wire gpio;

    wire uart_tx;
    wire [37:0] mprj_io;
 

    wire flash_csb;
    wire flash_clk;
    wire flash_io0;
    wire flash_io1;

    wire VDD3V3 = power1;
    wire VDD1V8 = power2;
    wire USER_VDD3V3 = power3;
	wire USER_VDD1V8 = power4;
    wire VSS = 1'b0;


    always #10 clock <= (clock == 1'b0);

    initial begin
        clock = 0;
    end

    initial begin
        $dumpfile("subservient_blinky.vcd");
        $dumpvars(0, subservient_blinky_tb);
        repeat (150) begin
            repeat (400) @(posedge clock);
        end
        $display("%c[1;31m",27);
        $display ("Monitor: Timeout, Subservient blinky test failed");
        $display("%c[0m",27);
        $finish;
    end


    initial begin
        RSTB <= 1'b0;
        CSB  <= 1'b1;
        #2000;
        RSTB <= 1'b1;
        #170000;
        CSB = 1'b0;
    end

    initial begin
        power1 <= 1'b0;
        power2 <= 1'b0;
        power3 <= 1'b0;
        power4 <= 1'b0;
        #100;
	power1 <= 1'b1;
	#100;
	power2 <= 1'b1;
	#100;
	power3 <= 1'b1;
	#100;
	power4 <= 1'b1;
    end


    initial begin
        $display("Monitor: subservient blinky test started");

        wait(mprj_io[31:0] == 1);
        wait(mprj_io[31:0] == 0);
        $display("Monitor: gpio switched once.");
        wait(mprj_io[31:0] == 1);
        wait(mprj_io[31:0] == 0);
        $display("Monitor: gpio switched twice.");
        $display("Monitor: subservient blinky test Passed");
        #1000;
        $finish;
    end
    
    caravel dut (
        .vddio	  (VDD3V3),
        .vssio	  (VSS),
        .vdda	  (VDD3V3),
        .vssa	  (VSS),
        .vccd	  (VDD1V8),
        .vssd	  (VSS),
        .vdda1    (USER_VDD3V3),
        .vdda2    (USER_VDD3V3),
        .vssa1	  (VSS),
        .vssa2	  (VSS),
        .vccd1	  (USER_VDD1V8),
        .vccd2	  (USER_VDD1V8),
        .vssd1	  (VSS),
        .vssd2	  (VSS),
        .clock	  (clock),
        .gpio     (gpio),
        .mprj_io  (mprj_io),
        .flash_csb(flash_csb),
        .flash_clk(flash_clk),
        .flash_io0(flash_io0),
        .flash_io1(flash_io1),
        .resetb	  (RSTB)
    );

    spiflash #(
        .FILENAME("subservient_blinky.hex")
    ) spiflash (
        .csb(flash_csb),
        .clk(flash_clk),
        .io0(flash_io0),
        .io1(flash_io1),
        .io2(),
        .io3()
    );

 endmodule