data/full_repos/permissive/527249789/src/Cache_top.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/527249789/src/Cache_top.v:87: Signal definition not found, creating implicitly: \'data_back\'\n                  data_back                                 ? 1\'b0 : do_req;\n                  ^~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/527249789/src/Cache_top.v:130: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n                                                                        : ... In instance Cache_top\n    inst_cache_addr <= inst_uncached                  ? 1\'b0 : \n                                                      ^\n%Error: data/full_repos/permissive/527249789/src/Cache_top.v:239: Cannot find file containing module: \'ICache\'\nICache ICache0(\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/ICache\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/ICache.v\n             data/full_repos/permissive/527249789/src,data/full_repos/permissive/527249789/ICache.sv\n             ICache\n             ICache.v\n             ICache.sv\n             obj_dir/ICache\n             obj_dir/ICache.v\n             obj_dir/ICache.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n'
module Cache_top(
        input   wire clk,  
        input   wire resetn,
        


        input   wire        inst_cpu_req,
        input   wire        inst_cpu_wr,
        input   wire[1  :0] inst_cpu_size,
        input   wire[31 :0] inst_cpu_addr,
        input   wire[31 :0] inst_cpu_wdata,
        output  wire[31 :0] inst_cpu_rdata,
        output  wire        inst_cpu_arready,
        output  wire        inst_cpu_rready,












        input   wire        axi_arready,
        input   wire        axi_rvalid,
        input   wire[1  :0] axi_rlast,
        input   wire[31 :0] axi_rdata,
        output  reg         axi_rreq,
        output  wire[1  :0] axi_rtype,
        output  wire[31 :0] axi_raddr,
        output  wire        axi_rready,








        input   wire        bvalid
    );

reg[3:0]    current_state;
reg[3:0]    next_state;
localparam  IDLE            = 4'h0,
            READ_IUNCACHED  = 4'h2,
            READ_ICACHE     = 4'h4;


reg        do_req;
reg        do_req_or;

reg [1 :0] do_size_r;
reg [31:0] do_addr_r;



always @(posedge clk)
begin
    do_req     <= !resetn                                   ? 1'b0 :
                  (inst_cpu_req)&&!do_req ? 1'b1 :
                  data_back                                 ? 1'b0 : do_req;
    do_req_or  <= !resetn ? 1'b0 :
do_req_or;


    do_size_r  <=
                  inst_cpu_req&&inst_cpu_arready ? inst_cpu_size : do_size_r;




end





wire            inst_uncached;

reg  [2  :0]    inst_read_count;

reg             inst_cache_rreq;
reg  [31 :0]    inst_cache_addr;
wire [31 :0]    inst_cache_praddr;

wire            inst_cache_rvalid;
wire            inst_cache_arready;
wire [31 :0]    inst_cache_rdata;

reg  [255:0]    inst_mem_rdata;
reg             inst_mem_rready;

wire            inst_mem_rreq;
wire [31 :0]    inst_mem_raddr;

assign inst_cache_praddr = (inst_cache_addr[31:28]==4'h8)||(inst_cache_addr[31:28]==4'h9)||
                           (inst_cache_addr[31:28]==4'ha)||(inst_cache_addr[31:28]==4'hb)?
                            inst_cache_addr & 32'h1fff_ffff:inst_cache_addr;
assign inst_uncached     = (inst_cpu_addr[31:28]==4'ha)||(inst_cpu_addr[31:28]==4'hb) ? 1:0;

always@(posedge clk) begin

    inst_cache_rreq <= inst_uncached                  ? 1'b0 : inst_cpu_req;
    inst_cache_addr <= inst_uncached                  ? 1'b0 : 
                       inst_cpu_req&&inst_cpu_arready ? inst_cpu_addr : inst_cache_addr;
end
always@(posedge clk)begin
    if(!resetn)  inst_mem_rdata  <= 256'b0;
    else if(current_state==IDLE)    inst_mem_rdata  <= 256'b0;
    else if(axi_rvalid) begin
        case(inst_read_count)
            3'h0:inst_mem_rdata[32*1-1:32*0] <= axi_rdata;
            3'h1:inst_mem_rdata[32*2-1:32*1] <= axi_rdata;
            3'h2:inst_mem_rdata[32*3-1:32*2] <= axi_rdata;
            3'h3:inst_mem_rdata[32*4-1:32*3] <= axi_rdata;
            3'h4:inst_mem_rdata[32*5-1:32*4] <= axi_rdata;
            3'h5:inst_mem_rdata[32*6-1:32*5] <= axi_rdata;
            3'h6:inst_mem_rdata[32*7-1:32*6] <= axi_rdata;
            3'h7:inst_mem_rdata[32*8-1:32*7] <= axi_rdata;
        endcase
    end
end
always@(posedge clk)begin
    if      (!resetn)   inst_mem_rready <= 0;
    else if (current_state==READ_ICACHE&&inst_read_count==3'h7&&axi_rvalid)  

                        inst_mem_rready <= 1;
    else if (current_state==READ_IUNCACHED&&axi_rvalid)               
                        inst_mem_rready <= 1;
    else                inst_mem_rready <= 0;
end


reg addr_rcv;




assign data_back = !resetn  ? 1'b0 :
                   (current_state==IDLE) && addr_rcv && (axi_rvalid&&axi_rready||bvalid)        ? 1'b1 :
                   inst_cache_rvalid                                                            ? 1'b1 : 1'b0;
                   
always @(posedge clk) begin
    addr_rcv    <= !resetn                                  ? 1'b0 :
                   inst_mem_rreq&&axi_arready && axi_rvalid ? 1'b1 :
                   data_back                                ? 1'b0 : addr_rcv;
end



always@(posedge clk) begin
    if(!resetn) begin
        current_state <= IDLE;
    end else begin
        current_state <= next_state;
    end
end

always@(posedge clk)begin
    if(!resetn)  next_state <= IDLE;
    else begin
        case(current_state)
            IDLE:begin
                if(inst_cpu_req && inst_uncached)           next_state<=READ_IUNCACHED;
                else if(inst_cpu_req && ~inst_uncached)     next_state<=READ_ICACHE;
            end

            READ_IUNCACHED:
                if(axi_rvalid)                        next_state<=IDLE;
            READ_ICACHE:begin
                if(axi_rvalid&&inst_read_count==3'h7) next_state<=IDLE;
                else if(inst_cache_rvalid)            next_state<=IDLE;
            end
        endcase
    end
end

always@(posedge clk)begin
    if      (!resetn)               inst_read_count <= 0;
    else if (current_state==IDLE)   inst_read_count <= 0;
    else if (axi_rvalid&&axi_rreq)  inst_read_count <= inst_read_count + 1;
    else                            inst_read_count <= inst_read_count;
end


assign inst_cpu_rdata   = inst_uncached ? inst_mem_rdata[31:0]:inst_cache_rdata[31:0];
assign inst_cpu_arready = !do_req;
assign inst_cpu_rready  = do_req && !do_req_or && data_back;






always@(*) begin
    axi_rreq         = (current_state == IDLE)           ? 1'b0 : 
                       (current_state == READ_IUNCACHED) ? 1'b1 :
                       (current_state == READ_ICACHE)    ? inst_mem_rreq : axi_rreq;
end
assign axi_rtype        = do_size_r;

assign axi_raddr        = (current_state == READ_IUNCACHED&&axi_rreq) ? inst_cache_praddr:
                          (current_state == READ_ICACHE&&axi_rreq)    ? {inst_cache_praddr[31:5],inst_read_count,2'b00} : 0;
assign axi_rready       = 1'b1;








ICache ICache0(
    .clk                (clk                ),
    .rst                (resetn             ),

    .rreq_inst_cpu_i    (inst_cache_rreq    ),
    .vaddr_inst_cpu_i   (inst_cache_addr    ),
    .paddr_inst_tlb_i   (inst_cache_praddr  ),
    .valid_inst_cpu_o   (inst_cache_rvalid  ),
    .arready_inst_cpu_o (inst_cache_arready ),
    .inst_cpu_o         (inst_cache_rdata   ),
    .hit_inst_cpu_o     (inst_cache_hit     ),

    .inst_mem_i         (inst_mem_rdata     ),
    .valid_mem_i        (inst_mem_rready    ),
    .ren_inst_mem_o     (inst_mem_rreq      ),
    .addr_inst_mem_o    (inst_mem_raddr     )


);
endmodule
module Cache_top(
        input   wire clk,  
        input   wire resetn,
        


        input   wire        inst_cpu_req,
        input   wire        inst_cpu_wr,
        input   wire[1  :0] inst_cpu_size,
        input   wire[31 :0] inst_cpu_addr,
        input   wire[31 :0] inst_cpu_wdata,
        output  wire[31 :0] inst_cpu_rdata,
        output  wire        inst_cpu_arready,
        output  wire        inst_cpu_rready,












        input   wire        axi_arready,
        input   wire        axi_rvalid,
        input   wire[1  :0] axi_rlast,
        input   wire[31 :0] axi_rdata,
        output  reg         axi_rreq,
        output  wire[1  :0] axi_rtype,
        output  wire[31 :0] axi_raddr,
        output  wire        axi_rready,








        input   wire        bvalid
    );


reg[3:0]    current_state;
reg[3:0]    next_state;
localparam  IDLE            = 4'h0,
            READ_IUNCACHED  = 4'h2,
            READ_ICACHE     = 4'h4;


reg        do_req;
reg        do_req_or;

reg [1 :0] do_size_r;
reg [31:0] do_addr_r;



always @(posedge clk)
begin
    do_req     <= !resetn                                   ? 1'b0 :
                  (inst_cpu_req)&&!do_req ? 1'b1 :
                  data_back                                 ? 1'b0 : do_req;
    do_req_or  <= !resetn ? 1'b0 :
do_req_or;


    do_size_r  <=
                  inst_cpu_req&&inst_cpu_arready ? inst_cpu_size : do_size_r;




end





wire            inst_uncached;

reg  [2  :0]    inst_read_count;

reg             inst_cache_rreq;
reg  [31 :0]    inst_cache_addr;
wire [31 :0]    inst_cache_praddr;

wire            inst_cache_rvalid;
wire            inst_cache_arready;
wire [31 :0]    inst_cache_rdata;

reg  [255:0]    inst_mem_rdata;
reg             inst_mem_rready;

wire            inst_mem_rreq;
wire [31 :0]    inst_mem_raddr;

assign inst_cache_praddr = (inst_cache_addr[31:28]==4'h8)||(inst_cache_addr[31:28]==4'h9)||
                           (inst_cache_addr[31:28]==4'ha)||(inst_cache_addr[31:28]==4'hb)?
                            inst_cache_addr & 32'h1fff_ffff:inst_cache_addr;
assign inst_uncached     = (inst_cpu_addr[31:28]==4'ha)||(inst_cpu_addr[31:28]==4'hb) ? 1:0;

always@(posedge clk) begin

    inst_cache_rreq <= inst_uncached                  ? 1'b0 : inst_cpu_req;
    inst_cache_addr <= inst_uncached                  ? 1'b0 : 
                       inst_cpu_req&&inst_cpu_arready ? inst_cpu_addr : inst_cache_addr;
end
always@(posedge clk)begin
    if(!resetn)  inst_mem_rdata  <= 256'b0;
    else if(current_state==IDLE)    inst_mem_rdata  <= 256'b0;
    else if(axi_rvalid) begin
        case(inst_read_count)
            3'h0:inst_mem_rdata[32*1-1:32*0] <= axi_rdata;
            3'h1:inst_mem_rdata[32*2-1:32*1] <= axi_rdata;
            3'h2:inst_mem_rdata[32*3-1:32*2] <= axi_rdata;
            3'h3:inst_mem_rdata[32*4-1:32*3] <= axi_rdata;
            3'h4:inst_mem_rdata[32*5-1:32*4] <= axi_rdata;
            3'h5:inst_mem_rdata[32*6-1:32*5] <= axi_rdata;
            3'h6:inst_mem_rdata[32*7-1:32*6] <= axi_rdata;
            3'h7:inst_mem_rdata[32*8-1:32*7] <= axi_rdata;
        endcase
    end
end
always@(posedge clk)begin
    if      (!resetn)   inst_mem_rready <= 0;
    else if (current_state==READ_ICACHE&&inst_read_count==3'h7&&axi_rvalid)  

                        inst_mem_rready <= 1;
    else if (current_state==READ_IUNCACHED&&axi_rvalid)               
                        inst_mem_rready <= 1;
    else                inst_mem_rready <= 0;
end


reg addr_rcv;




assign data_back = !resetn  ? 1'b0 :
                   (current_state==IDLE) && addr_rcv && (axi_rvalid&&axi_rready||bvalid)        ? 1'b1 :
                   inst_cache_rvalid                                                            ? 1'b1 : 1'b0;
                   
always @(posedge clk) begin
    addr_rcv    <= !resetn                                  ? 1'b0 :
                   inst_mem_rreq&&axi_arready && axi_rvalid ? 1'b1 :
                   data_back                                ? 1'b0 : addr_rcv;
end



always@(posedge clk) begin
    if(!resetn) begin
        current_state <= IDLE;
    end else begin
        current_state <= next_state;
    end
end

always@(posedge clk)begin
    if(!resetn)  next_state <= IDLE;
    else begin
        case(current_state)
            IDLE:begin
                if(inst_cpu_req && inst_uncached)           next_state<=READ_IUNCACHED;
                else if(inst_cpu_req && ~inst_uncached)     next_state<=READ_ICACHE;
            end

            READ_IUNCACHED:
                if(axi_rvalid)                        next_state<=IDLE;
            READ_ICACHE:begin
                if(axi_rvalid&&inst_read_count==3'h7) next_state<=IDLE;
                else if(inst_cache_rvalid)            next_state<=IDLE;
            end
        endcase
    end
end

always@(posedge clk)begin
    if      (!resetn)               inst_read_count <= 0;
    else if (current_state==IDLE)   inst_read_count <= 0;
    else if (axi_rvalid&&axi_rreq)  inst_read_count <= inst_read_count + 1;
    else                            inst_read_count <= inst_read_count;
end


assign inst_cpu_rdata   = inst_uncached ? inst_mem_rdata[31:0]:inst_cache_rdata[31:0];
assign inst_cpu_arready = !do_req;
assign inst_cpu_rready  = do_req && !do_req_or && data_back;






always@(*) begin
    axi_rreq         = (current_state == IDLE)           ? 1'b0 : 
                       (current_state == READ_IUNCACHED) ? 1'b1 :
                       (current_state == READ_ICACHE)    ? inst_mem_rreq : axi_rreq;
end
assign axi_rtype        = do_size_r;

assign axi_raddr        = (current_state == READ_IUNCACHED&&axi_rreq) ? inst_cache_praddr:
                          (current_state == READ_ICACHE&&axi_rreq)    ? {inst_cache_praddr[31:5],inst_read_count,2'b00} : 0;
assign axi_rready       = 1'b1;








ICache ICache0(
    .clk                (clk                ),
    .rst                (resetn             ),

    .rreq_inst_cpu_i    (inst_cache_rreq    ),
    .vaddr_inst_cpu_i   (inst_cache_addr    ),
    .paddr_inst_tlb_i   (inst_cache_praddr  ),
    .valid_inst_cpu_o   (inst_cache_rvalid  ),
    .arready_inst_cpu_o (inst_cache_arready ),
    .inst_cpu_o         (inst_cache_rdata   ),
    .hit_inst_cpu_o     (inst_cache_hit     ),

    .inst_mem_i         (inst_mem_rdata     ),
    .valid_mem_i        (inst_mem_rready    ),
    .ren_inst_mem_o     (inst_mem_rreq      ),
    .addr_inst_mem_o    (inst_mem_raddr     )


);
endmodule