data/full_repos/permissive/474582223/MUX/eightByOne/tf.v
1: b'%Error: data/full_repos/permissive/474582223/MUX/eightByOne/tf.v:35: Unsupported or unknown PLI call: $dumpfile\n      $dumpfile("dump.vcd");\n      ^~~~~~~~~\n%Error: data/full_repos/permissive/474582223/MUX/eightByOne/tf.v:36: Unsupported or unknown PLI call: $dumpvars\n      $dumpvars(1);  \n      ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/474582223/MUX/eightByOne/tf.v:47: Unsupported: Ignoring delay on this delayed statement.\n       #100;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/474582223/MUX/eightByOne/tf.v:58: Unsupported: Ignoring delay on this delayed statement.\n       #100;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/474582223/MUX/eightByOne/tf.v:69: Unsupported: Ignoring delay on this delayed statement.\n       #100;\n       ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module eightbymux1;


	reg a;
	reg b;
  	reg c;
  	reg d;
  	reg e;
  	reg f;
  	reg g;
  	reg h;
  	reg sel;


	wire yout;


	eightbyonemux uut (
      .a(a),
      .b(b),
      .c(c),
      .d(d),
      .e(e),
      .f(f),
      .g(g),
      .h(h),
      .sel(sel)
	);

	initial begin
      $dumpfile("dump.vcd");
      $dumpvars(1);

		sel = 3'b000;
      	a = 4'b0110;
      	b = 4'b0000;
      	c = 4'b1100;
      	d = 4'b0001;
      	e = 4'b0010;
      	f = 4'b1000;
      	g = 4'b1001;
      	h = 4'b0011;
      	#100;
      
      	sel = 3'b011;
      	a = 4'b1111;
      	b = 4'b0101;
      	c = 4'b1010;
      	d = 4'b0001;
      	e = 4'b0010;
      	f = 4'b1001;
      	g = 4'b0100;
      	h = 4'b0011;
      	#100;
      
      	sel = 3'b100;
      	a = 4'b1110;
      	b = 4'b0001;
      	c = 4'b1010;
      	d = 4'b0101;
      	e = 4'b1000;
      	f = 4'b0011;
      	g = 4'b0110;
      	h = 4'b0000;
      	#100;
	end
endmodule
module eightbymux1;



	reg a;
	reg b;
  	reg c;
  	reg d;
  	reg e;
  	reg f;
  	reg g;
  	reg h;
  	reg sel;


	wire yout;


	eightbyonemux uut (
      .a(a),
      .b(b),
      .c(c),
      .d(d),
      .e(e),
      .f(f),
      .g(g),
      .h(h),
      .sel(sel)
	);

	initial begin
      $dumpfile("dump.vcd");
      $dumpvars(1);

		sel = 3'b000;
      	a = 4'b0110;
      	b = 4'b0000;
      	c = 4'b1100;
      	d = 4'b0001;
      	e = 4'b0010;
      	f = 4'b1000;
      	g = 4'b1001;
      	h = 4'b0011;
      	#100;
      
      	sel = 3'b011;
      	a = 4'b1111;
      	b = 4'b0101;
      	c = 4'b1010;
      	d = 4'b0001;
      	e = 4'b0010;
      	f = 4'b1001;
      	g = 4'b0100;
      	h = 4'b0011;
      	#100;
      
      	sel = 3'b100;
      	a = 4'b1110;
      	b = 4'b0001;
      	c = 4'b1010;
      	d = 4'b0101;
      	e = 4'b1000;
      	f = 4'b0011;
      	g = 4'b0110;
      	h = 4'b0000;
      	#100;
	end
endmodule