data/full_repos/permissive/445379100/a4_synthesis/mux4input.v
data/verilator_xmls/0c46b928-fca6-461c-88f4-ebdc77c6a37b.xml
module mux4input (
    input [31:0] input0 ,
    input [31:0] input1 ,
    input [31:0] input2 ,
    input [31:0] input3 ,
    input [1:0] mux_sel ,
    output reg [31:0] mux_out
);
    always @(*) begin
        
        case (mux_sel) 
            2'd0     : mux_out = input0 ;
            2'd1     : mux_out = input1 ;
            2'd2     : mux_out = input2 ;
            2'd3     : mux_out = input3 ;

            default  : mux_out = 0 ;
            
        endcase
    end
endmodule
module mux4input (
    input [31:0] input0 ,
    input [31:0] input1 ,
    input [31:0] input2 ,
    input [31:0] input3 ,
    input [1:0] mux_sel ,
    output reg [31:0] mux_out
);

    always @(*) begin
        
        case (mux_sel) 
            2'd0     : mux_out = input0 ;
            2'd1     : mux_out = input1 ;
            2'd2     : mux_out = input2 ;
            2'd3     : mux_out = input3 ;

            default  : mux_out = 0 ;
            
        endcase
    end
endmodule