data/full_repos/permissive/480141277/regFile.v
1: b'%Warning-WIDTH: data/full_repos/permissive/480141277/regFile.v:42: Bit extraction of array[7:0] requires 3 bit index, not 4 bits.\n                                                                 : ... In instance regFile\n    register[writeAddress] = writeData;\n            ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/480141277/regFile.v:42: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'writeData\' generates 8 bits.\n                                                                 : ... In instance regFile\n    register[writeAddress] = writeData;\n                           ^\n%Warning-WIDTH: data/full_repos/permissive/480141277/regFile.v:56: Bit extraction of array[7:0] requires 3 bit index, not 4 bits.\n                                                                 : ... In instance regFile\n  assign readData1 = register[readAddress1];\n                             ^\n%Warning-WIDTH: data/full_repos/permissive/480141277/regFile.v:56: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS\'s ARRAYSEL generates 6 bits.\n                                                                 : ... In instance regFile\n  assign readData1 = register[readAddress1];\n                   ^\n%Error: Exiting due to 4 warning(s)\n'
module regFile(
   input rst,
	input [7:0] writeData,
	input writeEnable,
	input [3:0] readAddress1,
	input [3:0] writeAddress,
	input clk,
   output [7:0] readData1
 	);
 	
  reg[5:0] register[7:0];
 
  always @ (posedge clk)
   begin
		if(writeEnable)
			begin
				register[writeAddress] = writeData;
			end
		else if (rst)
			begin
				register[0] = 0;
				register[1] = 0;
				register[2] = 0;
				register[3] = 0;
				register[4] = 0;
				register[5] = 0;
				
			end
   end
  
  assign readData1 = register[readAddress1];
 
	
endmodule
module regFile(
   input rst,
	input [7:0] writeData,
	input writeEnable,
	input [3:0] readAddress1,
	input [3:0] writeAddress,
	input clk,
   output [7:0] readData1
 	);

 	
  reg[5:0] register[7:0];
 
  always @ (posedge clk)
   begin
		if(writeEnable)
			begin
				register[writeAddress] = writeData;
			end
		else if (rst)
			begin
				register[0] = 0;
				register[1] = 0;
				register[2] = 0;
				register[3] = 0;
				register[4] = 0;
				register[5] = 0;
				
			end
   end
  
  assign readData1 = register[readAddress1];
 
	
endmodule