data/full_repos/permissive/521337848/Hardware/BUZZER/buzzer.v
1: b"%Error: data/full_repos/permissive/521337848/Hardware/BUZZER/buzzer.v:146: Too many digits for 18 bit number: 18'hFFFFFFFF\n if(f_tim ==18'hFFFFFFFF) sig = 0;\n            ^~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n"
module generator(
	input clk,
	input rst,
	
	input[5:0] sound,
	
	output[1:0] tt,
	output snd,
	
	output reg finish
);


reg n_snd;
reg f_snd;

reg[17:0] tim;
reg[17:0] f_tim;

reg[5:0] ssound;

always@(posedge clk or posedge rst)begin
	if(rst) begin
		f_tim <= 0;
		f_snd <= 0;
		end
	else begin
		f_tim <= tim;
		f_snd <= n_snd;
		end
end

always@(posedge clk)
	if(sound == 0 || sound == 63) ssound <= 0;
	else ssound <= sound;


always@(*) begin
	tim = f_tim + 1;
	n_snd = f_snd;
	finish = 0;
	
	if(sound == 0) n_snd = 1;
	else begin
		if(f_tim[17:11] == {ssound})begin
			tim = 0;
			finish = 1;
		end
		else
		if(f_tim[17:15] == 0 && f_tim[14:8] <= (sound))begin
			n_snd = 0;
		end else
		begin
			n_snd = 1;
		end
	end 
	
	
end

assign tt = f_tim[1:0];
assign snd = f_snd;
endmodule
module generator(
	input clk,
	input rst,
	
	input[5:0] sound,
	
	output[1:0] tt,
	output snd,
	
	output reg finish
);



reg n_snd;
reg f_snd;

reg[17:0] tim;
reg[17:0] f_tim;

reg[5:0] ssound;

always@(posedge clk or posedge rst)begin
	if(rst) begin
		f_tim <= 0;
		f_snd <= 0;
		end
	else begin
		f_tim <= tim;
		f_snd <= n_snd;
		end
end

always@(posedge clk)
	if(sound == 0 || sound == 63) ssound <= 0;
	else ssound <= sound;


always@(*) begin
	tim = f_tim + 1;
	n_snd = f_snd;
	finish = 0;
	
	if(sound == 0) n_snd = 1;
	else begin
		if(f_tim[17:11] == {ssound})begin
			tim = 0;
			finish = 1;
		end
		else
		if(f_tim[17:15] == 0 && f_tim[14:8] <= (sound))begin
			n_snd = 0;
		end else
		begin
			n_snd = 1;
		end
	end 
	
	
end

assign tt = f_tim[1:0];
assign snd = f_snd;
endmodule