data/full_repos/permissive/486367830/hdl/signed_mult.v
1: b"%Error: data/full_repos/permissive/486367830/hdl/signed_mult.v:26: Cannot find file containing module: 'unsigned_mult'\nunsigned_mult #(\n^~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/486367830/hdl,data/full_repos/permissive/486367830/unsigned_mult\n             data/full_repos/permissive/486367830/hdl,data/full_repos/permissive/486367830/unsigned_mult.v\n             data/full_repos/permissive/486367830/hdl,data/full_repos/permissive/486367830/unsigned_mult.sv\n             unsigned_mult\n             unsigned_mult.v\n             unsigned_mult.sv\n             obj_dir/unsigned_mult\n             obj_dir/unsigned_mult.v\n             obj_dir/unsigned_mult.sv\n%Error: Exiting due to 1 error(s)\n"
module signed_mult #(
parameter DWIDTH = 8
)(

input  [  DWIDTH -1:0] op1    ,
input  [  DWIDTH -1:0] op2    ,
output [2*DWIDTH -1:0] result
); 

wire   [  DWIDTH -1:0] abs_op1    ;
wire   [  DWIDTH -1:0] abs_op2    ;
wire   [2*DWIDTH -1:0] abs_result ;

assign abs_op1 = op1[DWIDTH-1] ? (~op1 + 'd1) : op1;
assign abs_op2 = op2[DWIDTH-1] ? (~op2 + 'd1) : op2;

unsigned_mult #(
.DWIDTH (DWIDTH)
)i_unsigned_mult_1(
 .op1    (abs_op1    ),
 .op2    (abs_op2    ),
 .result (abs_result )
);  


assign result = (op1[DWIDTH-1] ^ op2[DWIDTH-1]) ? (~abs_result + 'd1) : abs_result; 


endmodule
module signed_mult #(
parameter DWIDTH = 8
)(

input  [  DWIDTH -1:0] op1    ,
input  [  DWIDTH -1:0] op2    ,
output [2*DWIDTH -1:0] result
);
 

wire   [  DWIDTH -1:0] abs_op1    ;
wire   [  DWIDTH -1:0] abs_op2    ;
wire   [2*DWIDTH -1:0] abs_result ;

assign abs_op1 = op1[DWIDTH-1] ? (~op1 + 'd1) : op1;
assign abs_op2 = op2[DWIDTH-1] ? (~op2 + 'd1) : op2;

unsigned_mult #(
.DWIDTH (DWIDTH)
)i_unsigned_mult_1(
 .op1    (abs_op1    ),
 .op2    (abs_op2    ),
 .result (abs_result )
);  


assign result = (op1[DWIDTH-1] ^ op2[DWIDTH-1]) ? (~abs_result + 'd1) : abs_result; 


endmodule