data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/ecc_core/alram112x.v
data/verilator_xmls/a304c772-55f3-4726-94e3-f51f7e0e3370.xml
module alram112x
    (
     clkw,
     clkr,
     rst,
     
     rdo,
     ra,
     
     wdi,
     wa,
     we
     );



parameter WID = 256;
parameter AWID = 5;
parameter DEP = 1<<AWID;




input clkw;
input clkr;
input rst;

output [WID-1:0] rdo;
input [AWID-1:0] ra;

input [WID-1:0]  wdi;
input [AWID-1:0] wa;
input            we;




reg [WID-1:0]    mem [DEP-1:0];

reg [AWID-1:0]   ra_reg;
reg [WID-1:0]    rdonor;

always@(posedge clkw)
    begin
    if(we)
        mem[wa] <= wdi;
    end

always@(posedge clkr)
    begin
    rdonor <= mem[ra_reg];
    ra_reg <= ra;
    end

`ifdef RWSAMECLK
wire sa;
wire [WID-1:0] wdi1;
wire [WID-1:0] wdi2;

assign sa = (ra == wa) && we;

wire   sa2;
ffxkclkx #(2,1) isa (clkw, rst, sa, sa2);

fflopx #(256) ifflopx1(clkw,rst,wdi,wdi1);
fflopx #(256) ifflopx2(clkw,rst,wdi1,wdi2);

assign rdo = sa2? wdi2 : rdonor;

`else

assign rdo =  rdonor;

`endif

endmodule
module alram112x
    (
     clkw,
     clkr,
     rst,
     
     rdo,
     ra,
     
     wdi,
     wa,
     we
     );




parameter WID = 256;
parameter AWID = 5;
parameter DEP = 1<<AWID;




input clkw;
input clkr;
input rst;

output [WID-1:0] rdo;
input [AWID-1:0] ra;

input [WID-1:0]  wdi;
input [AWID-1:0] wa;
input            we;




reg [WID-1:0]    mem [DEP-1:0];

reg [AWID-1:0]   ra_reg;
reg [WID-1:0]    rdonor;

always@(posedge clkw)
    begin
    if(we)
        mem[wa] <= wdi;
    end

always@(posedge clkr)
    begin
    rdonor <= mem[ra_reg];
    ra_reg <= ra;
    end

`ifdef RWSAMECLK
wire sa;
wire [WID-1:0] wdi1;
wire [WID-1:0] wdi2;

assign sa = (ra == wa) && we;

wire   sa2;
ffxkclkx #(2,1) isa (clkw, rst, sa, sa2);

fflopx #(256) ifflopx1(clkw,rst,wdi,wdi1);
fflopx #(256) ifflopx2(clkw,rst,wdi1,wdi2);

assign rdo = sa2? wdi2 : rdonor;

`else

assign rdo =  rdonor;

`endif

endmodule