data/full_repos/permissive/458935738/common/ir_modules.v
1: b'%Warning-WIDTH: data/full_repos/permissive/458935738/common/ir_modules.v:152: Operator ASSIGNDLY expects 17 bits on the Assign RHS, but Assign RHS\'s SEL generates 16 bits.\n                                                                            : ... In instance IRcontrol.ch7\n            ttd <= timerttd[15:0];\n                ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/458935738/common/ir_modules.v:27: Cannot find file containing module: \'pwm\'\n    pwm irevenLED (clk, ir_evenLED_en, 16\'d16000, ir_evenLED);\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/458935738/common,data/full_repos/permissive/458935738/pwm\n             data/full_repos/permissive/458935738/common,data/full_repos/permissive/458935738/pwm.v\n             data/full_repos/permissive/458935738/common,data/full_repos/permissive/458935738/pwm.sv\n             pwm\n             pwm.v\n             pwm.sv\n             obj_dir/pwm\n             obj_dir/pwm.v\n             obj_dir/pwm.sv\n%Error: data/full_repos/permissive/458935738/common/ir_modules.v:28: Cannot find file containing module: \'pwm\'\n    pwm iroddLED (clk, ir_oddLED_en, 16\'d16000, ir_oddLED);\n    ^~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n'
module IRread (
    input clk, enable,
    inout sensor,
    output reg[16:0] ttd
    );

    localparam s0	= 3'b000;
    localparam s1	= 3'b001;
    localparam s2	= 3'b010;
    localparam s3	= 3'b011;
    localparam s4	= 3'b100;
    localparam s5	= 3'b101;
    

    reg[2:0] current_state, next_state;
    reg timer10us_en, timerttd_en, drive_sensor, writettd;
    wire[31:0] timer10us;
    wire[31:0] timerttd;


    timer ten_us_buffer 	(clk, timer10us_en, 1'b0, timer10us);
    timer decay_timer	(clk, timerttd_en, 1'b0, timerttd);


    always @(posedge clk)
    begin
        if (enable)
            current_state <= next_state;
        else
            current_state <= 0;
    end
    
    always @(*)
    begin

        drive_sensor 	= 0;
        timer10us_en	= 0;
        timerttd_en 	= 0;
        writettd		= 0;

        next_state = s0;

        casex(current_state)

            s0: begin
                drive_sensor 	= 0;
                timer10us_en	= 0;
                timerttd_en 	= 0;
                writettd		= 0;
                
                next_state = s1;
            end
            

            s1: begin
                drive_sensor 	= 1;
                timer10us_en	= 1;
                timerttd_en 	= 0;
                writettd		= 0;
                
                if (timer10us == 32'd160)
                    next_state = s2;
                else
                    next_state = s1;
            end
            

            s2: begin
                drive_sensor 	= 0;
                timer10us_en	= 0;
                timerttd_en 	= 1;
                writettd		= 0;
                
                if (sensor == 0)
                    next_state = s3;
                else
                    next_state = s2;
            end
            


            s3: begin
                drive_sensor 	= 0;
                timer10us_en	= 0;
                timerttd_en 	= 1;
                writettd		= 1;
                
                next_state = s1;
            end
        endcase
    end
    

    
    assign sensor = drive_sensor ? 1'b1 : 1'bZ;
    
    always @(posedge clk)
    begin
        if (!enable)
        begin
            ttd <= 0;
        end
        else if (writettd)
            ttd <= timerttd[15:0];
        else
            ttd <= ttd;
    end
    
endmodule
module IRread (
    input clk, enable,
    inout sensor,
    output reg[16:0] ttd
    );


    localparam s0	= 3'b000;
    localparam s1	= 3'b001;
    localparam s2	= 3'b010;
    localparam s3	= 3'b011;
    localparam s4	= 3'b100;
    localparam s5	= 3'b101;
    

    reg[2:0] current_state, next_state;
    reg timer10us_en, timerttd_en, drive_sensor, writettd;
    wire[31:0] timer10us;
    wire[31:0] timerttd;


    timer ten_us_buffer 	(clk, timer10us_en, 1'b0, timer10us);
    timer decay_timer	(clk, timerttd_en, 1'b0, timerttd);


    always @(posedge clk)
    begin
        if (enable)
            current_state <= next_state;
        else
            current_state <= 0;
    end
    
    always @(*)
    begin

        drive_sensor 	= 0;
        timer10us_en	= 0;
        timerttd_en 	= 0;
        writettd		= 0;

        next_state = s0;

        casex(current_state)

            s0: begin
                drive_sensor 	= 0;
                timer10us_en	= 0;
                timerttd_en 	= 0;
                writettd		= 0;
                
                next_state = s1;
            end
            

            s1: begin
                drive_sensor 	= 1;
                timer10us_en	= 1;
                timerttd_en 	= 0;
                writettd		= 0;
                
                if (timer10us == 32'd160)
                    next_state = s2;
                else
                    next_state = s1;
            end
            

            s2: begin
                drive_sensor 	= 0;
                timer10us_en	= 0;
                timerttd_en 	= 1;
                writettd		= 0;
                
                if (sensor == 0)
                    next_state = s3;
                else
                    next_state = s2;
            end
            


            s3: begin
                drive_sensor 	= 0;
                timer10us_en	= 0;
                timerttd_en 	= 1;
                writettd		= 1;
                
                next_state = s1;
            end
        endcase
    end
    

    
    assign sensor = drive_sensor ? 1'b1 : 1'bZ;
    
    always @(posedge clk)
    begin
        if (!enable)
        begin
            ttd <= 0;
        end
        else if (writettd)
            ttd <= timerttd[15:0];
        else
            ttd <= ttd;
    end
    
endmodule