data/full_repos/permissive/458208177/hdl/32_bit_add_cla_tree.v
data/verilator_xmls/58351226-0f93-46d8-8a2a-3b95175c06b8.xml
module full_adder_gp(S, C, G, P, A, B, C0);
    output S, C, G, P;
    input A, B, C0;

    wire s0, c1;

    xor(s0, A, B);
    and(G, A, B);
    xor(S, C0, s0);
    and(c1, s0, C0);
    or(C, G, c1);

    assign P = s0;
endmodule
module full_adder_gp(S, C, G, P, A, B, C0);

    output S, C, G, P;
    input A, B, C0;

    wire s0, c1;

    xor(s0, A, B);
    and(G, A, B);
    xor(S, C0, s0);
    and(c1, s0, C0);
    or(C, G, c1);

    assign P = s0;
endmodule