data/full_repos/permissive/531233322/verilog/tb_next_state.v
1: b'%Error: data/full_repos/permissive/531233322/verilog/tb_next_state.v:17: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/531233322/verilog/tb_next_state.v:22: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/531233322/verilog/tb_next_state.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/531233322/verilog/tb_next_state.v:26: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/531233322/verilog/tb_next_state.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/531233322/verilog/tb_next_state.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/531233322/verilog/tb_next_state.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/531233322/verilog/tb_next_state.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/531233322/verilog/tb_next_state.v:36: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/531233322/verilog/tb_next_state.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/531233322/verilog/tb_next_state.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/531233322/verilog/tb_next_state.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/531233322/verilog/tb_next_state.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/531233322/verilog/tb_next_state.v:46: Unsupported: Ignoring delay on this delayed statement.\n        #10;\n        ^\n%Error: Exiting due to 1 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_next_state();

reg [7:0] state;
wire [7:0] state_next;
reg [2:0] sym;

next_state_PROJECT_ID ns(
    .state_in(state),
    .s2(sym[2]),
    .s1(sym[1]),
    .s0(sym[0]),
    .state_out(state_next));

integer i;
integer j;
initial begin
    $dumpvars;
    for (i = 0; i < 8; i = i + 1) begin
        state = 1 << i;
        $display("==== state 0x%x %c", state, "A" + $clog2(state));
        sym = 3'b000;
        #10;
        $display("0x%x %c", state_next, "A" + $clog2(state_next));
        #10;
        sym = 3'b001;
        #10;
        $display("0x%x %c", state_next, "A" + $clog2(state_next));
        #10;
        sym = 3'b010;
        #10;
        $display("0x%x %c", state_next, "A" + $clog2(state_next));
        #10;
        sym = 3'b100;
        #10;
        $display("0x%x %c", state_next, "A" + $clog2(state_next));
        #10;
        sym = 3'b101;
        #10;
        $display("0x%x %c", state_next, "A" + $clog2(state_next));
        #10;
        sym = 3'b110;
        #10;
        $display("0x%x %c", state_next, "A" + $clog2(state_next));
        #10;
        sym = 3'b111;
        #10;
        $display("0x%x %c", state_next, "A" + $clog2(state_next));
    end
end

endmodule
module tb_next_state();


reg [7:0] state;
wire [7:0] state_next;
reg [2:0] sym;

next_state_PROJECT_ID ns(
    .state_in(state),
    .s2(sym[2]),
    .s1(sym[1]),
    .s0(sym[0]),
    .state_out(state_next));

integer i;
integer j;
initial begin
    $dumpvars;
    for (i = 0; i < 8; i = i + 1) begin
        state = 1 << i;
        $display("==== state 0x%x %c", state, "A" + $clog2(state));
        sym = 3'b000;
        #10;
        $display("0x%x %c", state_next, "A" + $clog2(state_next));
        #10;
        sym = 3'b001;
        #10;
        $display("0x%x %c", state_next, "A" + $clog2(state_next));
        #10;
        sym = 3'b010;
        #10;
        $display("0x%x %c", state_next, "A" + $clog2(state_next));
        #10;
        sym = 3'b100;
        #10;
        $display("0x%x %c", state_next, "A" + $clog2(state_next));
        #10;
        sym = 3'b101;
        #10;
        $display("0x%x %c", state_next, "A" + $clog2(state_next));
        #10;
        sym = 3'b110;
        #10;
        $display("0x%x %c", state_next, "A" + $clog2(state_next));
        #10;
        sym = 3'b111;
        #10;
        $display("0x%x %c", state_next, "A" + $clog2(state_next));
    end
end

endmodule