data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/xc6s_brams_map.v
1: b'%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/xc6s_brams_map.v:35: Cannot find include file: brams_init_9.vh\n  `include "brams_init_9.vh" \n           ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx,data/full_repos/permissive/441359809/brams_init_9.vh\n             data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx,data/full_repos/permissive/441359809/brams_init_9.vh.v\n             data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx,data/full_repos/permissive/441359809/brams_init_9.vh.sv\n             brams_init_9.vh\n             brams_init_9.vh.v\n             brams_init_9.vh.sv\n             obj_dir/brams_init_9.vh\n             obj_dir/brams_init_9.vh.v\n             obj_dir/brams_init_9.vh.sv\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/xc6s_brams_map.v:103: Cannot find include file: brams_init_18.vh\n   `include "brams_init_18.vh" \n            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/xc6s_brams_map.v:133: Cannot find include file: brams_init_16.vh\n   `include "brams_init_16.vh" \n            ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/xc6s_brams_map.v:202: Cannot find include file: brams_init_9.vh\n   `include "brams_init_9.vh" \n            ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/441359809/src/yosys/techlibs/xilinx/xc6s_brams_map.v:233: Cannot find include file: brams_init_8.vh\n   `include "brams_init_8.vh" \n            ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module \$__XILINX_RAMB8BWER_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
	parameter CLKPOL2 = 1;
	parameter CLKPOL3 = 1;
	parameter [9215:0] INIT = 9216'bx;

	input CLK2;
	input CLK3;

	input [7:0] A1ADDR;
	output [35:0] A1DATA;
	input A1EN;

	input [7:0] B1ADDR;
	input [35:0] B1DATA;
	input [3:0] B1EN;

	wire [12:0] A1ADDR_13 = {A1ADDR, 5'b0};
	wire [12:0] B1ADDR_13 = {B1ADDR, 5'b0};

	wire [3:0] DIP, DOP;
	wire [31:0] DI, DO;

	assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
	assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;

	RAMB8BWER #(
		.RAM_MODE("SDP"),
		.DATA_WIDTH_A(36),
		.DATA_WIDTH_B(36),
		.WRITE_MODE_A("READ_FIRST"),
		.WRITE_MODE_B("READ_FIRST"),
		`include "brams_init_9.vh"
	) _TECHMAP_REPLACE_ (
		.DOBDO(DO[31:16]),
		.DOADO(DO[15:0]),
		.DOPBDOP(DOP[3:2]),
		.DOPADOP(DOP[1:0]),
		.DIBDI(DI[31:16]),
		.DIADI(DI[15:0]),
		.DIPBDIP(DIP[3:2]),
		.DIPADIP(DIP[1:0]),
		.WEBWEU(B1EN[3:2]),
		.WEAWEL(B1EN[1:0]),

		.ADDRAWRADDR(B1ADDR_13),
		.CLKAWRCLK(CLK3 ^ !CLKPOL3),
		.ENAWREN(|1),
		.REGCEA(|0),
		.RSTA(|0),

		.ADDRBRDADDR(A1ADDR_13),
		.CLKBRDCLK(CLK2 ^ !CLKPOL2),
		.ENBRDEN(A1EN),
		.REGCEBREGCE(|1),
		.RSTBRST(|0)
	);
endmodule
module \$__XILINX_RAMB8BWER_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);

	parameter CLKPOL2 = 1;
	parameter CLKPOL3 = 1;
	parameter [9215:0] INIT = 9216'bx;

	input CLK2;
	input CLK3;

	input [7:0] A1ADDR;
	output [35:0] A1DATA;
	input A1EN;

	input [7:0] B1ADDR;
	input [35:0] B1DATA;
	input [3:0] B1EN;

	wire [12:0] A1ADDR_13 = {A1ADDR, 5'b0};
	wire [12:0] B1ADDR_13 = {B1ADDR, 5'b0};

	wire [3:0] DIP, DOP;
	wire [31:0] DI, DO;

	assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
	assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;

	RAMB8BWER #(
		.RAM_MODE("SDP"),
		.DATA_WIDTH_A(36),
		.DATA_WIDTH_B(36),
		.WRITE_MODE_A("READ_FIRST"),
		.WRITE_MODE_B("READ_FIRST"),
		`include "brams_init_9.vh"
	) _TECHMAP_REPLACE_ (
		.DOBDO(DO[31:16]),
		.DOADO(DO[15:0]),
		.DOPBDOP(DOP[3:2]),
		.DOPADOP(DOP[1:0]),
		.DIBDI(DI[31:16]),
		.DIADI(DI[15:0]),
		.DIPBDIP(DIP[3:2]),
		.DIPADIP(DIP[1:0]),
		.WEBWEU(B1EN[3:2]),
		.WEAWEL(B1EN[1:0]),

		.ADDRAWRADDR(B1ADDR_13),
		.CLKAWRCLK(CLK3 ^ !CLKPOL3),
		.ENAWREN(|1),
		.REGCEA(|0),
		.RSTA(|0),

		.ADDRBRDADDR(A1ADDR_13),
		.CLKBRDCLK(CLK2 ^ !CLKPOL2),
		.ENBRDEN(A1EN),
		.REGCEBREGCE(|1),
		.RSTBRST(|0)
	);
endmodule