data/full_repos/permissive/490492655/shiftRregN.v
data/verilator_xmls/5111bfb8-ac23-4751-a01c-7d89b826294c.xml
module shiftRregN #(parameter N = 4) (
	input [N-1:0] d,
	input clk, rst, en, ldsh, SI,
	output SO,
	output reg [N-1:0] q
);

	always @ (negedge rst, posedge clk)
	begin
		if (rst == 0)
			q <= 0;
		else if (en)
			if (ldsh) q <= d;
			else q <= { SI, q[N-1:1]};
		else q <= q;
	end
	
	assign SO = q[0];

endmodule
module shiftRregN #(parameter N = 4) (
	input [N-1:0] d,
	input clk, rst, en, ldsh, SI,
	output SO,
	output reg [N-1:0] q
);


	always @ (negedge rst, posedge clk)
	begin
		if (rst == 0)
			q <= 0;
		else if (en)
			if (ldsh) q <= d;
			else q <= { SI, q[N-1:1]};
		else q <= q;
	end
	
	assign SO = q[0];

endmodule