data/full_repos/permissive/521104862/rtl/Psychic5_emu.v
1: b'%Error: data/full_repos/permissive/521104862/rtl/Psychic5_emu.v:20: Cannot find include file: rtl/Psychic5_emu_header.v\n`include "rtl/Psychic5_emu_header.v" \n         ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/521104862/rtl,data/full_repos/permissive/521104862/rtl/Psychic5_emu_header.v\n             data/full_repos/permissive/521104862/rtl,data/full_repos/permissive/521104862/rtl/Psychic5_emu_header.v.v\n             data/full_repos/permissive/521104862/rtl,data/full_repos/permissive/521104862/rtl/Psychic5_emu_header.v.sv\n             rtl/Psychic5_emu_header.v\n             rtl/Psychic5_emu_header.v.v\n             rtl/Psychic5_emu_header.v.sv\n             obj_dir/rtl/Psychic5_emu_header.v\n             obj_dir/rtl/Psychic5_emu_header.v.v\n             obj_dir/rtl/Psychic5_emu_header.v.sv\n%Error: Exiting due to 1 error(s)\n'
module Psychic5_emu
(
    input   wire            i_EMU_MCLK,
    input   wire            i_EMU_INITRST,
    input   wire            i_EMU_SOFTRST,

    output  wire            o_HSYNC_n,
    output  wire            o_VSYNC_n,

    output  wire            o_HBLANK_n,
    output  wire            o_VBLANK_n,

    output  wire    [3:0]   o_VIDEO_R,
    output  wire    [3:0]   o_VIDEO_G,
    output  wire    [3:0]   o_VIDEO_B,

    output  wire    [15:0]  o_SOUND,

    output  wire            o_PXCEN,

    input   wire    [15:0]  i_JOYSTICK0,
    input   wire    [15:0]  i_JOYSTICK1,


    input   wire    [15:0]  ioctl_index,
    input   wire            ioctl_download,
    input   wire    [26:0]  ioctl_addr,
    input   wire    [7:0]   ioctl_data,
    input   wire            ioctl_wr, 
    output  wire            ioctl_wait,


    inout   wire    [15:0]  sdram_dq,
    output  wire    [12:0]  sdram_a,
    output  wire            sdram_dqml,
    output  wire            sdram_dqmh,
    output  wire    [1:0]   sdram_ba,
    output  wire            sdram_nwe,
    output  wire            sdram_ncas,
    output  wire            sdram_nras,
    output  wire            sdram_ncs,
    output  wire            sdram_cke,

    output  wire            debug
);










wire            CLK12MPCEN_n;
wire            CLK5MPCEN_n, CLK5MNCEN_n;


reg     [4:0]   div5_cntr = 5'b11110;
assign          CLK12MPCEN_n = div5_cntr[4];
always @(posedge i_EMU_MCLK) begin
    if(i_EMU_INITRST) begin
        div5_cntr <= 5'b11110;
    end
    else begin
        div5_cntr[0] <= div5_cntr[4];
        div5_cntr[4:1] <= div5_cntr[3:0];
    end
end


reg     [11:0]  div12_cntr = 12'b111111_111110;
assign          CLK5MPCEN_n = div12_cntr[11];
assign          CLK5MNCEN_n = div12_cntr[5];
always @(posedge i_EMU_MCLK) begin
    if(i_EMU_INITRST) begin
        div12_cntr <= 12'b111110_111111;
    end
    else begin
        div12_cntr[0] <= div12_cntr[11];
        div12_cntr[11:1] <= div12_cntr[10:0];
    end
end














wire    [7:0]   SYS_BTN, P1_BTN, P2_BTN;


assign          SYS_BTN[0]  = ~i_JOYSTICK0[9];
assign          SYS_BTN[1]  = ~i_JOYSTICK1[9];
assign          SYS_BTN[2]  = 1'b1;
assign          SYS_BTN[3]  = 1'b1;
assign          SYS_BTN[4]  = ~i_JOYSTICK0[6];
assign          SYS_BTN[5]  = ~i_JOYSTICK0[7];
assign          SYS_BTN[6]  = ~i_JOYSTICK0[8];
assign          SYS_BTN[7]  = ~i_JOYSTICK1[8];


assign          P1_BTN[0]   = ~i_JOYSTICK0[0];
assign          P1_BTN[1]   = ~i_JOYSTICK0[1];
assign          P1_BTN[2]   = ~i_JOYSTICK0[2];
assign          P1_BTN[3]   = ~i_JOYSTICK0[3];
assign          P1_BTN[4]   = ~i_JOYSTICK0[5];
assign          P1_BTN[5]   = ~i_JOYSTICK0[4];
assign          P1_BTN[6]   = 1'b1;
assign          P1_BTN[7]   = 1'b1;


assign          P2_BTN[0]   = ~i_JOYSTICK1[0];
assign          P2_BTN[1]   = ~i_JOYSTICK1[1];
assign          P2_BTN[2]   = ~i_JOYSTICK1[2];
assign          P2_BTN[3]   = ~i_JOYSTICK1[3];
assign          P2_BTN[4]   = ~i_JOYSTICK1[4];
assign          P2_BTN[5]   = ~i_JOYSTICK1[5];
assign          P2_BTN[6]   = 1'b1;
assign          P2_BTN[7]   = 1'b1;

































reg     [7:0]   DIPSW1 = 8'hEF;
reg     [7:0]   DIPSW2 = 8'hFF;










reg             rom_download_done = 1'b0;


reg             prog_sdram_en = 1'b0;
reg             prog_bram_en = 1'b0;
reg             prog_dipsw_en = 1'b0;


wire            sdram_init;
reg             prog_sdram_wr_busy = 1'b0;
wire            prog_sdram_ack;
assign          ioctl_wait = sdram_init | prog_sdram_wr_busy;


reg     [1:0]   prog_sdram_bank_sel;
reg     [21:0]  prog_sdram_addr;
reg     [15:0]  prog_sdram_din_buf;


reg     [7:0]   prog_bram_din_buf;
reg     [16:0]  prog_bram_addr;
reg             prog_bram_wr_n;
reg     [4:0]   prog_bram_csreg_n;

wire            prog_bram_soundrom_cs_n = prog_bram_csreg_n[4];
wire            prog_bram_tmbgrom_cs_n = prog_bram_csreg_n[3];
wire            prog_bram_tmfgrom_cs_n = prog_bram_csreg_n[2];
wire            prog_bram_seqrom_cs_n = prog_bram_csreg_n[1];
wire            prog_bram_graylut_cs_n = prog_bram_csreg_n[0];
assign          debug = rom_download_done;



always @(posedge i_EMU_MCLK) begin
    if((i_EMU_INITRST | rom_download_done) == 1'b1) begin

        prog_sdram_en <= 1'b0;
        prog_bram_en <= 1'b0;
        prog_dipsw_en <= 1'b0;
        

        prog_sdram_addr <= 22'h3F_FFFF;
        prog_sdram_wr_busy <= 1'b0;
        prog_sdram_bank_sel <= 2'd0;
        prog_sdram_din_buf <= 16'hFFFF;


        prog_bram_din_buf <= 8'hFF;
        prog_bram_addr <= 17'h1FFFF;
        prog_bram_wr_n <= 1'b1;
        prog_bram_csreg_n <= 5'b11111;
    end
    else begin

        if(ioctl_index == 16'd0) begin

            if(ioctl_addr[18] == 1'b1) begin
                prog_sdram_en <= 1'b0;
                prog_bram_en <= 1'b1;
                prog_dipsw_en <= 1'b0;

                if(ioctl_wr == 1'b1) begin
                    prog_bram_din_buf <= ioctl_data;
                    prog_bram_addr <= ioctl_addr[16:0];
                    prog_bram_wr_n <= 1'b0;

                    if(ioctl_addr[17] == 1'b0) begin
                        prog_bram_csreg_n <= 5'b10111;
                    end
                    else begin
                        if(ioctl_addr[16:15] == 2'b00) begin
                            prog_bram_csreg_n <= 5'b11011;
                        end
                        else if(ioctl_addr[16:15] == 2'b01) begin
                            prog_bram_csreg_n <= 5'b01111;
                        end
                        else if(ioctl_addr[16:15] == 2'b10) begin
                            if(ioctl_addr[10] == 1'b0) begin
                                prog_bram_csreg_n <= 5'b11101;
                            end
                            else if(ioctl_addr[10:9] == 2'b10) begin
                                prog_bram_csreg_n <= 5'b11110;
                            end
                            else begin
                                prog_bram_csreg_n <= 5'b11111;
                            end
                        end
                        else begin
                            prog_bram_csreg_n <= 5'b11111;
                        end
                    end
                end
                else begin
                    prog_bram_wr_n <= 1'b1;
                end
            end


            else begin
                prog_sdram_en <= 1'b1;
                prog_bram_en <= 1'b0;
                prog_dipsw_en <= 1'b0;
                
                if(prog_sdram_wr_busy == 1'b0) begin
                    if(ioctl_wr == 1'b1) begin
                        if(ioctl_addr[0] == 1'b0) begin
                            prog_sdram_din_buf[15:8] <= ioctl_data;
                        end
                        else begin
                            prog_sdram_din_buf[7:0] <= ioctl_data;
                            prog_sdram_wr_busy <= 1'b1;

                            if(ioctl_addr[17] == 1'b0) begin
                                prog_sdram_addr <= {6'b00_0000, ioctl_addr[16:1]};
                                prog_sdram_bank_sel <= 2'd0;
                            end
                            else begin
                                prog_sdram_addr <= {6'b00_0000, ioctl_addr[16:1]};
                                prog_sdram_bank_sel <= 2'd1;
                            end
                        end
                    end
                end
                else begin
                    if(prog_sdram_ack == 1'b1) begin  
                        prog_sdram_wr_busy <= 1'b0;
                    end
                end
            end
        end

        else if(ioctl_index == 16'd254) begin
            if(ioctl_addr[24:1] == 24'h00_0000) begin
                prog_sdram_en <= 1'b0;
                prog_bram_en <= 1'b0;
                prog_dipsw_en <= 1'b1;

                if(ioctl_wr == 1'b1) begin
                    if(ioctl_addr[0] == 1'b0) begin
                        DIPSW1 <= ioctl_data;
                    end
                    else if(ioctl_addr[0] == 1'b1) begin
                        DIPSW2 <= ioctl_data;
                    end
                end
            end
            else begin
                prog_sdram_en <= 1'b0;
                prog_bram_en <= 1'b0;
                prog_dipsw_en <= 1'b0;
            end
        end
    end
end







wire    [21:0]  ba0_addr;
wire    [21:0]  ba1_addr;
wire    [21:0]  ba2_addr;
wire    [3:0]   rd;           
wire    [3:0]   ack;
wire    [3:0]   dst;
wire    [3:0]   rdy;
wire    [15:0]  data_read;

reg     [8:0]   rfsh_cntr;
wire            rfsh = rfsh_cntr == 9'd384;
always @(posedge i_EMU_MCLK) begin
    if(o_PXCEN) begin
        if(i_EMU_INITRST) begin
            rfsh_cntr <= 9'd0;
        end
        else begin
            if(rfsh_cntr < 9'd384) rfsh_cntr <= rfsh_cntr + 9'd1;
            else rfsh_cntr <= 9'd0;
        end
    end
end


jtframe_sdram64 #(.HF(0)) sdram_controller (
    .rst                        (i_EMU_INITRST              ),
    .clk                        (i_EMU_MCLK                 ),
    .init                       (sdram_init                 ),

    .ba0_addr                   (ba0_addr                   ),
    .ba1_addr                   (ba1_addr                   ),
    .ba2_addr                   (ba2_addr                   ),
    .ba3_addr                   (22'h00_0000                ),
    .rd                         ({2'b00, rd[1:0]}           ),
    .wr                         (4'b0000                    ),
    .din                        (prog_sdram_din_buf         ),
    .din_m                      (2'b00                      ),

    .prog_en                    (prog_sdram_en              ),
    .prog_addr                  (prog_sdram_addr            ),
    .prog_rd                    (1'b0                       ),
    .prog_wr                    (prog_sdram_wr_busy         ),
    .prog_din                   (prog_sdram_din_buf         ),
    .prog_din_m                 (2'b00                      ),
    .prog_ba                    (prog_sdram_bank_sel        ),
    .prog_dst                   (                           ),
    .prog_dok                   (                           ),
    .prog_rdy                   (                           ),
    .prog_ack                   (prog_sdram_ack             ),

    .rfsh                       (rfsh                       ),

    .ack                        (ack                        ),
    .dst                        (dst                        ),
    .dok                        (                           ),
    .rdy                        (rdy                        ),
    .dout                       (data_read                  ),

    .sdram_dq                   (sdram_dq                   ),
    .sdram_a                    (sdram_a                    ),
    .sdram_dqml                 (sdram_dqml                 ),
    .sdram_dqmh                 (sdram_dqmh                 ),
    .sdram_ba                   (sdram_ba                   ),
    .sdram_nwe                  (sdram_nwe                  ),
    .sdram_ncas                 (sdram_ncas                 ),
    .sdram_nras                 (sdram_nras                 ),
    .sdram_ncs                  (sdram_ncs                  ),
    .sdram_cke                  (sdram_cke                  )
);







reg     [2:0]   dwnld_done_negdet;
reg     [2:0]   dwnld_done_flags;

wire            sdram_done_set = dwnld_done_negdet[2] & ~prog_sdram_en;
wire            bram_done_set = dwnld_done_negdet[1] & ~prog_bram_en;
wire            dipsw_done_set = dwnld_done_negdet[0] & ~prog_dipsw_en;


always @(posedge i_EMU_MCLK) begin
    if(i_EMU_INITRST == 1'b1) begin
        dwnld_done_negdet <= 3'b000;
        dwnld_done_flags <= 3'b000;
        rom_download_done <= 1'b0;
    end
    else begin
        dwnld_done_negdet[2] <= prog_sdram_en;
        dwnld_done_negdet[1] <= prog_bram_en;
        dwnld_done_negdet[0] <= prog_dipsw_en;

        if(sdram_done_set) dwnld_done_flags[2] <= 1'b1;
        if(bram_done_set) dwnld_done_flags[1] <= 1'b1;
        if(dipsw_done_set) dwnld_done_flags[0] <= 1'b1;

        rom_download_done <= &{dwnld_done_flags};
    end
end










wire            maincpu_rq_n;
wire    [16:0]  maincpu_addr;
wire    [15:0]  maincpu_wide_data;
wire    [7:0]   maincpu_muxed_data = (maincpu_addr[0] == 1'b0) ? maincpu_wide_data[15:8] : maincpu_wide_data[7:0];

jtframe_rom_2slots #(

    .SLOT0_AW                   (15                         ),
    .SLOT0_DW                   (16                         ),
    .SLOT0_OFFSET               (18'h0_C000                 ),


    .SLOT1_AW                   (16                         ),
    .SLOT1_DW                   (16                         ),
    .SLOT1_OFFSET               (18'h0_0000                 )
) bank0 (
    .rst                        (~rom_download_done         ),
    .clk                        (i_EMU_MCLK                 ),

    .slot0_cs                   (1'b0                       ),
    .slot1_cs                   (~maincpu_rq_n              ),

    .slot0_ok                   (                           ),
    .slot1_ok                   (                           ),

    .slot0_addr                 (                           ),
    .slot1_addr                 (maincpu_addr[16:1]         ),

    .slot0_dout                 (                           ),
    .slot1_dout                 (maincpu_wide_data          ),

    .sdram_addr                 (ba0_addr                   ),
    .sdram_req                  (rd[0]                      ),
    .sdram_ack                  (ack[0]                     ),
    .data_dst                   (dst[0]                     ),
    .data_rdy                   (rdy[0]                     ),
    .data_read                  (data_read                  )
);


wire            objrom_rq_n;
wire    [16:0]  objrom_addr;
wire    [15:0]  objrom_wide_data;
wire    [7:0]   objrom_muxed_data = (objrom_addr[0] == 1'b0) ? objrom_wide_data[15:8] : objrom_wide_data[7:0];

jtframe_rom_2slots #(

    .SLOT0_AW                   (16                         ),
    .SLOT0_DW                   (16                         ),
    .SLOT0_OFFSET               (18'h0_0000                 ),

    .SLOT1_AW                   (                           ),
    .SLOT1_DW                   (                           ),
    .SLOT1_OFFSET               (                           )
) bank1 (
    .rst                        (~rom_download_done         ),
    .clk                        (i_EMU_MCLK                 ),

    .slot0_cs                   (~objrom_rq_n               ),
    .slot1_cs                   (1'b0                       ),

    .slot0_ok                   (                           ),
    .slot1_ok                   (                           ),

    .slot0_addr                 (objrom_addr[16:1]          ),
    .slot1_addr                 (                           ),

    .slot0_dout                 (objrom_wide_data           ),
    .slot1_dout                 (                           ),

    .sdram_addr                 (ba1_addr                   ),
    .sdram_req                  (rd[1]                      ),
    .sdram_ack                  (ack[1]                     ),
    .data_dst                   (dst[1]                     ),
    .data_rdy                   (rdy[1]                     ),
    .data_read                  (data_read                  )
);










`ifdef FASTBOOT
wire            core_reset = i_EMU_INITRST;

`else
wire            core_reset = i_EMU_INITRST | ~rom_download_done;

`endif

wire            cpu_soft_reset = i_EMU_INITRST | i_EMU_SOFTRST;



`ifdef SIMULATION
wire    [8:0]   HCOUNTER, VCOUNTER;

Psychic5_screensim screensim_main (
    .i_EMU_MCLK                 (i_EMU_MCLK                 ),
    .i_EMU_CLK6MPCEN_n          (~o_PXCEN                   ),
    .i_EMU_MRST_n               (~core_reset                ),

    .i_HCOUNTER                 (HCOUNTER                   ),
    .i_VCOUNTER                 (VCOUNTER                   ),
    .i_VIDEODATA                ({o_VIDEO_R, o_VIDEO_G, o_VIDEO_B})
);
`endif


wire            hsync_n, hblank_n;

Psychic5_top gameboard_top (
    .i_EMU_MCLK                 (i_EMU_MCLK                 ),
    .i_EMU_CLK12MPCEN_n         (CLK12MPCEN_n               ),
    .i_EMU_CLK5MPCEN_n          (CLK5MPCEN_n                ),
    .i_EMU_CLK5MNCEN_n          (CLK5MNCEN_n                ),

    .i_EMU_INITRST_n            (~core_reset                ),
    .i_EMU_SOFTRST_n            (~cpu_soft_reset            ),

    .o_CSYNC_n                  (                           ),
    .o_HSYNC_n                  (hsync_n                    ),
    .o_VSYNC_n                  (o_VSYNC_n                  ),
    
    .o_HBLANK_n                 (hblank_n                   ),
    .o_VBLANK_n                 (o_VBLANK_n                 ),

    .o_VIDEO_R                  (o_VIDEO_R                  ),
    .o_VIDEO_G                  (o_VIDEO_G                  ),
    .o_VIDEO_B                  (o_VIDEO_B                  ),

    .o_SOUND                    (o_SOUND                    ),

    .__REF_PXCEN                (o_PXCEN                    ),
    .__REF_HCOUNTER             (HCOUNTER                   ),
    .__REF_VCOUNTER             (VCOUNTER                   ),

    .i_P1_BTN                   (P1_BTN                     ),
    .i_P2_BTN                   (P2_BTN                     ),
    .i_SYS_BTN                  (SYS_BTN                    ),
    .i_DIPSW1                   (DIPSW1                     ),
    .i_DIPSW2                   (DIPSW2                     ),


    .o_EMU_MAINCPU_ADDR         (maincpu_addr               ),
    .i_EMU_MAINCPU_DATA         (maincpu_muxed_data         ),
    .o_EMU_MAINCPU_RQ_n         (maincpu_rq_n               ),

    .o_EMU_OBJROM_ADDR          (objrom_addr                ),
    .i_EMU_OBJROM_DATA          (objrom_muxed_data          ),
    .o_EMU_OBJROM_RQ_n          (objrom_rq_n                ),


    .i_EMU_BRAM_ADDR            (prog_bram_addr             ),
    .i_EMU_BRAM_DATA            (prog_bram_din_buf          ),
    .i_EMU_BRAM_WR_n            (prog_bram_wr_n             ),

    .i_EMU_BRAM_SOUNDROM_CS_n   (prog_bram_soundrom_cs_n    ),
    .i_EMU_BRAM_TMBGROM_CS_n    (prog_bram_tmbgrom_cs_n     ),
    .i_EMU_BRAM_TMFGROM_CS_n    (prog_bram_tmfgrom_cs_n     ),
    .i_EMU_BRAM_GRAYLUT_CS_n    (prog_bram_graylut_cs_n     ),
    .i_EMU_BRAM_SEQROM_CS_n     (prog_bram_seqrom_cs_n      )
);







reg     [9:0]   hsync_dlyline, hblank_dlyline;

assign          o_HSYNC_n = hsync_dlyline[4];
assign          o_HBLANK_n = hblank_dlyline[4];

always @(posedge i_EMU_MCLK) begin
    if(o_PXCEN) begin
        hsync_dlyline[0] <= hsync_n;
        hsync_dlyline[9:1] <= hsync_dlyline[8:0];

        hblank_dlyline[0] <= hblank_n;
        hblank_dlyline[9:1] <= hblank_dlyline[8:0];
    end
end

endmodule
module Psychic5_emu
(
    input   wire            i_EMU_MCLK,
    input   wire            i_EMU_INITRST,
    input   wire            i_EMU_SOFTRST,

    output  wire            o_HSYNC_n,
    output  wire            o_VSYNC_n,

    output  wire            o_HBLANK_n,
    output  wire            o_VBLANK_n,

    output  wire    [3:0]   o_VIDEO_R,
    output  wire    [3:0]   o_VIDEO_G,
    output  wire    [3:0]   o_VIDEO_B,

    output  wire    [15:0]  o_SOUND,

    output  wire            o_PXCEN,

    input   wire    [15:0]  i_JOYSTICK0,
    input   wire    [15:0]  i_JOYSTICK1,


    input   wire    [15:0]  ioctl_index,
    input   wire            ioctl_download,
    input   wire    [26:0]  ioctl_addr,
    input   wire    [7:0]   ioctl_data,
    input   wire            ioctl_wr, 
    output  wire            ioctl_wait,


    inout   wire    [15:0]  sdram_dq,
    output  wire    [12:0]  sdram_a,
    output  wire            sdram_dqml,
    output  wire            sdram_dqmh,
    output  wire    [1:0]   sdram_ba,
    output  wire            sdram_nwe,
    output  wire            sdram_ncas,
    output  wire            sdram_nras,
    output  wire            sdram_ncs,
    output  wire            sdram_cke,

    output  wire            debug
);











wire            CLK12MPCEN_n;
wire            CLK5MPCEN_n, CLK5MNCEN_n;


reg     [4:0]   div5_cntr = 5'b11110;
assign          CLK12MPCEN_n = div5_cntr[4];
always @(posedge i_EMU_MCLK) begin
    if(i_EMU_INITRST) begin
        div5_cntr <= 5'b11110;
    end
    else begin
        div5_cntr[0] <= div5_cntr[4];
        div5_cntr[4:1] <= div5_cntr[3:0];
    end
end


reg     [11:0]  div12_cntr = 12'b111111_111110;
assign          CLK5MPCEN_n = div12_cntr[11];
assign          CLK5MNCEN_n = div12_cntr[5];
always @(posedge i_EMU_MCLK) begin
    if(i_EMU_INITRST) begin
        div12_cntr <= 12'b111110_111111;
    end
    else begin
        div12_cntr[0] <= div12_cntr[11];
        div12_cntr[11:1] <= div12_cntr[10:0];
    end
end














wire    [7:0]   SYS_BTN, P1_BTN, P2_BTN;


assign          SYS_BTN[0]  = ~i_JOYSTICK0[9];
assign          SYS_BTN[1]  = ~i_JOYSTICK1[9];
assign          SYS_BTN[2]  = 1'b1;
assign          SYS_BTN[3]  = 1'b1;
assign          SYS_BTN[4]  = ~i_JOYSTICK0[6];
assign          SYS_BTN[5]  = ~i_JOYSTICK0[7];
assign          SYS_BTN[6]  = ~i_JOYSTICK0[8];
assign          SYS_BTN[7]  = ~i_JOYSTICK1[8];


assign          P1_BTN[0]   = ~i_JOYSTICK0[0];
assign          P1_BTN[1]   = ~i_JOYSTICK0[1];
assign          P1_BTN[2]   = ~i_JOYSTICK0[2];
assign          P1_BTN[3]   = ~i_JOYSTICK0[3];
assign          P1_BTN[4]   = ~i_JOYSTICK0[5];
assign          P1_BTN[5]   = ~i_JOYSTICK0[4];
assign          P1_BTN[6]   = 1'b1;
assign          P1_BTN[7]   = 1'b1;


assign          P2_BTN[0]   = ~i_JOYSTICK1[0];
assign          P2_BTN[1]   = ~i_JOYSTICK1[1];
assign          P2_BTN[2]   = ~i_JOYSTICK1[2];
assign          P2_BTN[3]   = ~i_JOYSTICK1[3];
assign          P2_BTN[4]   = ~i_JOYSTICK1[4];
assign          P2_BTN[5]   = ~i_JOYSTICK1[5];
assign          P2_BTN[6]   = 1'b1;
assign          P2_BTN[7]   = 1'b1;

































reg     [7:0]   DIPSW1 = 8'hEF;
reg     [7:0]   DIPSW2 = 8'hFF;










reg             rom_download_done = 1'b0;


reg             prog_sdram_en = 1'b0;
reg             prog_bram_en = 1'b0;
reg             prog_dipsw_en = 1'b0;


wire            sdram_init;
reg             prog_sdram_wr_busy = 1'b0;
wire            prog_sdram_ack;
assign          ioctl_wait = sdram_init | prog_sdram_wr_busy;


reg     [1:0]   prog_sdram_bank_sel;
reg     [21:0]  prog_sdram_addr;
reg     [15:0]  prog_sdram_din_buf;


reg     [7:0]   prog_bram_din_buf;
reg     [16:0]  prog_bram_addr;
reg             prog_bram_wr_n;
reg     [4:0]   prog_bram_csreg_n;

wire            prog_bram_soundrom_cs_n = prog_bram_csreg_n[4];
wire            prog_bram_tmbgrom_cs_n = prog_bram_csreg_n[3];
wire            prog_bram_tmfgrom_cs_n = prog_bram_csreg_n[2];
wire            prog_bram_seqrom_cs_n = prog_bram_csreg_n[1];
wire            prog_bram_graylut_cs_n = prog_bram_csreg_n[0];
assign          debug = rom_download_done;



always @(posedge i_EMU_MCLK) begin
    if((i_EMU_INITRST | rom_download_done) == 1'b1) begin

        prog_sdram_en <= 1'b0;
        prog_bram_en <= 1'b0;
        prog_dipsw_en <= 1'b0;
        

        prog_sdram_addr <= 22'h3F_FFFF;
        prog_sdram_wr_busy <= 1'b0;
        prog_sdram_bank_sel <= 2'd0;
        prog_sdram_din_buf <= 16'hFFFF;


        prog_bram_din_buf <= 8'hFF;
        prog_bram_addr <= 17'h1FFFF;
        prog_bram_wr_n <= 1'b1;
        prog_bram_csreg_n <= 5'b11111;
    end
    else begin

        if(ioctl_index == 16'd0) begin

            if(ioctl_addr[18] == 1'b1) begin
                prog_sdram_en <= 1'b0;
                prog_bram_en <= 1'b1;
                prog_dipsw_en <= 1'b0;

                if(ioctl_wr == 1'b1) begin
                    prog_bram_din_buf <= ioctl_data;
                    prog_bram_addr <= ioctl_addr[16:0];
                    prog_bram_wr_n <= 1'b0;

                    if(ioctl_addr[17] == 1'b0) begin
                        prog_bram_csreg_n <= 5'b10111;
                    end
                    else begin
                        if(ioctl_addr[16:15] == 2'b00) begin
                            prog_bram_csreg_n <= 5'b11011;
                        end
                        else if(ioctl_addr[16:15] == 2'b01) begin
                            prog_bram_csreg_n <= 5'b01111;
                        end
                        else if(ioctl_addr[16:15] == 2'b10) begin
                            if(ioctl_addr[10] == 1'b0) begin
                                prog_bram_csreg_n <= 5'b11101;
                            end
                            else if(ioctl_addr[10:9] == 2'b10) begin
                                prog_bram_csreg_n <= 5'b11110;
                            end
                            else begin
                                prog_bram_csreg_n <= 5'b11111;
                            end
                        end
                        else begin
                            prog_bram_csreg_n <= 5'b11111;
                        end
                    end
                end
                else begin
                    prog_bram_wr_n <= 1'b1;
                end
            end


            else begin
                prog_sdram_en <= 1'b1;
                prog_bram_en <= 1'b0;
                prog_dipsw_en <= 1'b0;
                
                if(prog_sdram_wr_busy == 1'b0) begin
                    if(ioctl_wr == 1'b1) begin
                        if(ioctl_addr[0] == 1'b0) begin
                            prog_sdram_din_buf[15:8] <= ioctl_data;
                        end
                        else begin
                            prog_sdram_din_buf[7:0] <= ioctl_data;
                            prog_sdram_wr_busy <= 1'b1;

                            if(ioctl_addr[17] == 1'b0) begin
                                prog_sdram_addr <= {6'b00_0000, ioctl_addr[16:1]};
                                prog_sdram_bank_sel <= 2'd0;
                            end
                            else begin
                                prog_sdram_addr <= {6'b00_0000, ioctl_addr[16:1]};
                                prog_sdram_bank_sel <= 2'd1;
                            end
                        end
                    end
                end
                else begin
                    if(prog_sdram_ack == 1'b1) begin  
                        prog_sdram_wr_busy <= 1'b0;
                    end
                end
            end
        end

        else if(ioctl_index == 16'd254) begin
            if(ioctl_addr[24:1] == 24'h00_0000) begin
                prog_sdram_en <= 1'b0;
                prog_bram_en <= 1'b0;
                prog_dipsw_en <= 1'b1;

                if(ioctl_wr == 1'b1) begin
                    if(ioctl_addr[0] == 1'b0) begin
                        DIPSW1 <= ioctl_data;
                    end
                    else if(ioctl_addr[0] == 1'b1) begin
                        DIPSW2 <= ioctl_data;
                    end
                end
            end
            else begin
                prog_sdram_en <= 1'b0;
                prog_bram_en <= 1'b0;
                prog_dipsw_en <= 1'b0;
            end
        end
    end
end







wire    [21:0]  ba0_addr;
wire    [21:0]  ba1_addr;
wire    [21:0]  ba2_addr;
wire    [3:0]   rd;           
wire    [3:0]   ack;
wire    [3:0]   dst;
wire    [3:0]   rdy;
wire    [15:0]  data_read;

reg     [8:0]   rfsh_cntr;
wire            rfsh = rfsh_cntr == 9'd384;
always @(posedge i_EMU_MCLK) begin
    if(o_PXCEN) begin
        if(i_EMU_INITRST) begin
            rfsh_cntr <= 9'd0;
        end
        else begin
            if(rfsh_cntr < 9'd384) rfsh_cntr <= rfsh_cntr + 9'd1;
            else rfsh_cntr <= 9'd0;
        end
    end
end


jtframe_sdram64 #(.HF(0)) sdram_controller (
    .rst                        (i_EMU_INITRST              ),
    .clk                        (i_EMU_MCLK                 ),
    .init                       (sdram_init                 ),

    .ba0_addr                   (ba0_addr                   ),
    .ba1_addr                   (ba1_addr                   ),
    .ba2_addr                   (ba2_addr                   ),
    .ba3_addr                   (22'h00_0000                ),
    .rd                         ({2'b00, rd[1:0]}           ),
    .wr                         (4'b0000                    ),
    .din                        (prog_sdram_din_buf         ),
    .din_m                      (2'b00                      ),

    .prog_en                    (prog_sdram_en              ),
    .prog_addr                  (prog_sdram_addr            ),
    .prog_rd                    (1'b0                       ),
    .prog_wr                    (prog_sdram_wr_busy         ),
    .prog_din                   (prog_sdram_din_buf         ),
    .prog_din_m                 (2'b00                      ),
    .prog_ba                    (prog_sdram_bank_sel        ),
    .prog_dst                   (                           ),
    .prog_dok                   (                           ),
    .prog_rdy                   (                           ),
    .prog_ack                   (prog_sdram_ack             ),

    .rfsh                       (rfsh                       ),

    .ack                        (ack                        ),
    .dst                        (dst                        ),
    .dok                        (                           ),
    .rdy                        (rdy                        ),
    .dout                       (data_read                  ),

    .sdram_dq                   (sdram_dq                   ),
    .sdram_a                    (sdram_a                    ),
    .sdram_dqml                 (sdram_dqml                 ),
    .sdram_dqmh                 (sdram_dqmh                 ),
    .sdram_ba                   (sdram_ba                   ),
    .sdram_nwe                  (sdram_nwe                  ),
    .sdram_ncas                 (sdram_ncas                 ),
    .sdram_nras                 (sdram_nras                 ),
    .sdram_ncs                  (sdram_ncs                  ),
    .sdram_cke                  (sdram_cke                  )
);







reg     [2:0]   dwnld_done_negdet;
reg     [2:0]   dwnld_done_flags;

wire            sdram_done_set = dwnld_done_negdet[2] & ~prog_sdram_en;
wire            bram_done_set = dwnld_done_negdet[1] & ~prog_bram_en;
wire            dipsw_done_set = dwnld_done_negdet[0] & ~prog_dipsw_en;


always @(posedge i_EMU_MCLK) begin
    if(i_EMU_INITRST == 1'b1) begin
        dwnld_done_negdet <= 3'b000;
        dwnld_done_flags <= 3'b000;
        rom_download_done <= 1'b0;
    end
    else begin
        dwnld_done_negdet[2] <= prog_sdram_en;
        dwnld_done_negdet[1] <= prog_bram_en;
        dwnld_done_negdet[0] <= prog_dipsw_en;

        if(sdram_done_set) dwnld_done_flags[2] <= 1'b1;
        if(bram_done_set) dwnld_done_flags[1] <= 1'b1;
        if(dipsw_done_set) dwnld_done_flags[0] <= 1'b1;

        rom_download_done <= &{dwnld_done_flags};
    end
end










wire            maincpu_rq_n;
wire    [16:0]  maincpu_addr;
wire    [15:0]  maincpu_wide_data;
wire    [7:0]   maincpu_muxed_data = (maincpu_addr[0] == 1'b0) ? maincpu_wide_data[15:8] : maincpu_wide_data[7:0];

jtframe_rom_2slots #(

    .SLOT0_AW                   (15                         ),
    .SLOT0_DW                   (16                         ),
    .SLOT0_OFFSET               (18'h0_C000                 ),


    .SLOT1_AW                   (16                         ),
    .SLOT1_DW                   (16                         ),
    .SLOT1_OFFSET               (18'h0_0000                 )
) bank0 (
    .rst                        (~rom_download_done         ),
    .clk                        (i_EMU_MCLK                 ),

    .slot0_cs                   (1'b0                       ),
    .slot1_cs                   (~maincpu_rq_n              ),

    .slot0_ok                   (                           ),
    .slot1_ok                   (                           ),

    .slot0_addr                 (                           ),
    .slot1_addr                 (maincpu_addr[16:1]         ),

    .slot0_dout                 (                           ),
    .slot1_dout                 (maincpu_wide_data          ),

    .sdram_addr                 (ba0_addr                   ),
    .sdram_req                  (rd[0]                      ),
    .sdram_ack                  (ack[0]                     ),
    .data_dst                   (dst[0]                     ),
    .data_rdy                   (rdy[0]                     ),
    .data_read                  (data_read                  )
);


wire            objrom_rq_n;
wire    [16:0]  objrom_addr;
wire    [15:0]  objrom_wide_data;
wire    [7:0]   objrom_muxed_data = (objrom_addr[0] == 1'b0) ? objrom_wide_data[15:8] : objrom_wide_data[7:0];

jtframe_rom_2slots #(

    .SLOT0_AW                   (16                         ),
    .SLOT0_DW                   (16                         ),
    .SLOT0_OFFSET               (18'h0_0000                 ),

    .SLOT1_AW                   (                           ),
    .SLOT1_DW                   (                           ),
    .SLOT1_OFFSET               (                           )
) bank1 (
    .rst                        (~rom_download_done         ),
    .clk                        (i_EMU_MCLK                 ),

    .slot0_cs                   (~objrom_rq_n               ),
    .slot1_cs                   (1'b0                       ),

    .slot0_ok                   (                           ),
    .slot1_ok                   (                           ),

    .slot0_addr                 (objrom_addr[16:1]          ),
    .slot1_addr                 (                           ),

    .slot0_dout                 (objrom_wide_data           ),
    .slot1_dout                 (                           ),

    .sdram_addr                 (ba1_addr                   ),
    .sdram_req                  (rd[1]                      ),
    .sdram_ack                  (ack[1]                     ),
    .data_dst                   (dst[1]                     ),
    .data_rdy                   (rdy[1]                     ),
    .data_read                  (data_read                  )
);










`ifdef FASTBOOT
wire            core_reset = i_EMU_INITRST;

`else
wire            core_reset = i_EMU_INITRST | ~rom_download_done;

`endif

wire            cpu_soft_reset = i_EMU_INITRST | i_EMU_SOFTRST;



`ifdef SIMULATION
wire    [8:0]   HCOUNTER, VCOUNTER;

Psychic5_screensim screensim_main (
    .i_EMU_MCLK                 (i_EMU_MCLK                 ),
    .i_EMU_CLK6MPCEN_n          (~o_PXCEN                   ),
    .i_EMU_MRST_n               (~core_reset                ),

    .i_HCOUNTER                 (HCOUNTER                   ),
    .i_VCOUNTER                 (VCOUNTER                   ),
    .i_VIDEODATA                ({o_VIDEO_R, o_VIDEO_G, o_VIDEO_B})
);
`endif


wire            hsync_n, hblank_n;

Psychic5_top gameboard_top (
    .i_EMU_MCLK                 (i_EMU_MCLK                 ),
    .i_EMU_CLK12MPCEN_n         (CLK12MPCEN_n               ),
    .i_EMU_CLK5MPCEN_n          (CLK5MPCEN_n                ),
    .i_EMU_CLK5MNCEN_n          (CLK5MNCEN_n                ),

    .i_EMU_INITRST_n            (~core_reset                ),
    .i_EMU_SOFTRST_n            (~cpu_soft_reset            ),

    .o_CSYNC_n                  (                           ),
    .o_HSYNC_n                  (hsync_n                    ),
    .o_VSYNC_n                  (o_VSYNC_n                  ),
    
    .o_HBLANK_n                 (hblank_n                   ),
    .o_VBLANK_n                 (o_VBLANK_n                 ),

    .o_VIDEO_R                  (o_VIDEO_R                  ),
    .o_VIDEO_G                  (o_VIDEO_G                  ),
    .o_VIDEO_B                  (o_VIDEO_B                  ),

    .o_SOUND                    (o_SOUND                    ),

    .__REF_PXCEN                (o_PXCEN                    ),
    .__REF_HCOUNTER             (HCOUNTER                   ),
    .__REF_VCOUNTER             (VCOUNTER                   ),

    .i_P1_BTN                   (P1_BTN                     ),
    .i_P2_BTN                   (P2_BTN                     ),
    .i_SYS_BTN                  (SYS_BTN                    ),
    .i_DIPSW1                   (DIPSW1                     ),
    .i_DIPSW2                   (DIPSW2                     ),


    .o_EMU_MAINCPU_ADDR         (maincpu_addr               ),
    .i_EMU_MAINCPU_DATA         (maincpu_muxed_data         ),
    .o_EMU_MAINCPU_RQ_n         (maincpu_rq_n               ),

    .o_EMU_OBJROM_ADDR          (objrom_addr                ),
    .i_EMU_OBJROM_DATA          (objrom_muxed_data          ),
    .o_EMU_OBJROM_RQ_n          (objrom_rq_n                ),


    .i_EMU_BRAM_ADDR            (prog_bram_addr             ),
    .i_EMU_BRAM_DATA            (prog_bram_din_buf          ),
    .i_EMU_BRAM_WR_n            (prog_bram_wr_n             ),

    .i_EMU_BRAM_SOUNDROM_CS_n   (prog_bram_soundrom_cs_n    ),
    .i_EMU_BRAM_TMBGROM_CS_n    (prog_bram_tmbgrom_cs_n     ),
    .i_EMU_BRAM_TMFGROM_CS_n    (prog_bram_tmfgrom_cs_n     ),
    .i_EMU_BRAM_GRAYLUT_CS_n    (prog_bram_graylut_cs_n     ),
    .i_EMU_BRAM_SEQROM_CS_n     (prog_bram_seqrom_cs_n      )
);







reg     [9:0]   hsync_dlyline, hblank_dlyline;

assign          o_HSYNC_n = hsync_dlyline[4];
assign          o_HBLANK_n = hblank_dlyline[4];

always @(posedge i_EMU_MCLK) begin
    if(o_PXCEN) begin
        hsync_dlyline[0] <= hsync_n;
        hsync_dlyline[9:1] <= hsync_dlyline[8:0];

        hblank_dlyline[0] <= hblank_n;
        hblank_dlyline[9:1] <= hblank_dlyline[8:0];
    end
end

endmodule