data/full_repos/permissive/516385853/kernel_kcore/kernel_kcore_fifo_w64_d128_A.v
1: b'%Warning-WIDTH: data/full_repos/permissive/516385853/kernel_kcore/kernel_kcore_fifo_w64_d128_A.v:66: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                   : ... In instance kernel_kcore_fifo_w64_d128_A\nreg  [ADDR_WIDTH-1:0] waddr = 1\'b0;\n                              ^~~~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/516385853/kernel_kcore/kernel_kcore_fifo_w64_d128_A.v:67: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                   : ... In instance kernel_kcore_fifo_w64_d128_A\nreg  [ADDR_WIDTH-1:0] raddr = 1\'b0;\n                              ^~~~\n%Warning-WIDTH: data/full_repos/permissive/516385853/kernel_kcore/kernel_kcore_fifo_w64_d128_A.v:72: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                   : ... In instance kernel_kcore_fifo_w64_d128_A\nreg  [ADDR_WIDTH:0]   mOutPtr = 1\'b0;\n                                ^~~~\n%Warning-WIDTH: data/full_repos/permissive/516385853/kernel_kcore/kernel_kcore_fifo_w64_d128_A.v:100: Operator EQ expects 32 or 8 bits on the LHS, but LHS\'s VARREF \'waddr\' generates 7 bits.\n                                                                                                    : ... In instance kernel_kcore_fifo_w64_d128_A\n                    (waddr == DEPTH - 1) ? 1\'b0  :\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/516385853/kernel_kcore/kernel_kcore_fifo_w64_d128_A.v:100: Operator COND expects 7 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                    : ... In instance kernel_kcore_fifo_w64_d128_A\n                    (waddr == DEPTH - 1) ? 1\'b0  :\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/516385853/kernel_kcore/kernel_kcore_fifo_w64_d128_A.v:103: Operator EQ expects 32 or 8 bits on the LHS, but LHS\'s VARREF \'raddr\' generates 7 bits.\n                                                                                                    : ... In instance kernel_kcore_fifo_w64_d128_A\n                    (raddr == DEPTH - 1) ? 1\'b0  :\n                           ^~\n%Warning-WIDTH: data/full_repos/permissive/516385853/kernel_kcore/kernel_kcore_fifo_w64_d128_A.v:103: Operator COND expects 7 bits on the Conditional True, but Conditional True\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                    : ... In instance kernel_kcore_fifo_w64_d128_A\n                    (raddr == DEPTH - 1) ? 1\'b0  :\n                                         ^\n%Warning-WIDTH: data/full_repos/permissive/516385853/kernel_kcore/kernel_kcore_fifo_w64_d128_A.v:109: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                    : ... In instance kernel_kcore_fifo_w64_d128_A\n        waddr <= 1\'b0;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/516385853/kernel_kcore/kernel_kcore_fifo_w64_d128_A.v:117: Operator ASSIGNDLY expects 7 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                    : ... In instance kernel_kcore_fifo_w64_d128_A\n        raddr <= 1\'b0;\n              ^~\n%Warning-WIDTH: data/full_repos/permissive/516385853/kernel_kcore/kernel_kcore_fifo_w64_d128_A.v:125: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n                                                                                                    : ... In instance kernel_kcore_fifo_w64_d128_A\n        mOutPtr <= 1\'b0;\n                ^~\n%Warning-WIDTH: data/full_repos/permissive/516385853/kernel_kcore/kernel_kcore_fifo_w64_d128_A.v:149: Operator NEQ expects 8 bits on the RHS, but RHS\'s CONST \'1\'h1\' generates 1 bits.\n                                                                                                    : ... In instance kernel_kcore_fifo_w64_d128_A\n        empty_n <= (mOutPtr != 1\'b1);\n                            ^~\n%Error: Exiting due to 11 warning(s)\n'
module kernel_kcore_fifo_w64_d128_A_ram
#(parameter
    DATA_WIDTH  = 64,
    ADDR_WIDTH  = 7,
    DEPTH       = 128
)
(
    input  wire                  clk,
    input  wire                  we,
    input  wire [ADDR_WIDTH-1:0] waddr,
    input  wire [DATA_WIDTH-1:0] din,
    input  wire [ADDR_WIDTH-1:0] raddr,
    output wire [DATA_WIDTH-1:0] dout
);

(* rw_addr_collision = "yes" *)
reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
reg  [ADDR_WIDTH-1:0] raddr_reg;


always @(posedge clk) begin
    if (we)
        mem[waddr] <= din;
end


always @(posedge clk) begin
    raddr_reg <= raddr;
end


assign dout = mem[raddr_reg];

endmodule
module kernel_kcore_fifo_w64_d128_A_ram
#(parameter
    DATA_WIDTH  = 64,
    ADDR_WIDTH  = 7,
    DEPTH       = 128
)
(
    input  wire                  clk,
    input  wire                  we,
    input  wire [ADDR_WIDTH-1:0] waddr,
    input  wire [DATA_WIDTH-1:0] din,
    input  wire [ADDR_WIDTH-1:0] raddr,
    output wire [DATA_WIDTH-1:0] dout
);


(* rw_addr_collision = "yes" *)
reg  [DATA_WIDTH-1:0] mem[0:DEPTH-1];
reg  [ADDR_WIDTH-1:0] raddr_reg;


always @(posedge clk) begin
    if (we)
        mem[waddr] <= din;
end


always @(posedge clk) begin
    raddr_reg <= raddr;
end


assign dout = mem[raddr_reg];

endmodule