data/full_repos/permissive/463549945/Problem_sets/Verilog_Language/Modules_Hierarchy/Modules.v
data/verilator_xmls/f0d1531a-3af2-4440-ad5a-c929b83a920b.xml
module top_module ( input a, input b, output out );
    
    mod_a instance1 (a, b, out);

endmodule
module top_module ( input a, input b, output out );

    
    mod_a instance1 (a, b, out);

endmodule