data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/led_control.v
1: b'%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/led_control.v:46: Cannot find include file: ../regmap/led_setup_regmap_utils.vh\n  `include "../regmap/led_setup_regmap_utils.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints,data/full_repos/permissive/447976230/../regmap/led_setup_regmap_utils.vh\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints,data/full_repos/permissive/447976230/../regmap/led_setup_regmap_utils.vh.v\n             data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints,data/full_repos/permissive/447976230/../regmap/led_setup_regmap_utils.vh.sv\n             ../regmap/led_setup_regmap_utils.vh\n             ../regmap/led_setup_regmap_utils.vh.v\n             ../regmap/led_setup_regmap_utils.vh.sv\n             obj_dir/../regmap/led_setup_regmap_utils.vh\n             obj_dir/../regmap/led_setup_regmap_utils.vh.v\n             obj_dir/../regmap/led_setup_regmap_utils.vh.sv\n%Error: data/full_repos/permissive/447976230/fpga/usrp3/top/x400/dboards/zbx/cpld/register_endpoints/led_control.v:47: Cannot find include file: ../../../../../../lib/rfnoc/core/ctrlport.vh\n  `include "../../../../../../lib/rfnoc/core/ctrlport.vh" \n           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n'
module led_control #(
  parameter [19:0]  BASE_ADDRESS = 0,
  parameter [19:0]  SIZE_ADDRESS = 0
) (

  input  wire        ctrlport_clk,
  input  wire        ctrlport_rst,


  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [31:0] s_ctrlport_req_data,

  output reg         s_ctrlport_resp_ack,
  output reg  [ 1:0] s_ctrlport_resp_status = 2'b0,
  output reg  [31:0] s_ctrlport_resp_data = 32'b0,


  output reg         ch0_rx2_led,
  output reg         ch0_tx_led,
  output reg         ch0_rx_led,
  output reg         ch1_rx2_led,
  output reg         ch1_tx_led,
  output reg         ch1_rx_led,


  input  wire [ 7:0] atr_config_rf0,
  input  wire [ 7:0] atr_config_rf1
);

  `include "../regmap/led_setup_regmap_utils.vh"
  `include "../../../../../../lib/rfnoc/core/ctrlport.vh"




  reg         ram_ch0_wea;
  wire [31:0] ram_ch0_doa;
  wire [31:0] ram_ch0_dob;

  reg         ram_ch1_wea;
  wire [31:0] ram_ch1_dob;





  wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + SIZE_ADDRESS);

  reg  [ 1:0] read_req_shift_reg = 2'b0;


  wire [31:0] register_base_address = {s_ctrlport_req_addr[19:10], 8'b0, s_ctrlport_req_addr[1:0]};


  wire [ 7:0] register_index = s_ctrlport_req_addr[9:2];

  always @(posedge ctrlport_clk) begin

    if (ctrlport_rst) begin
      s_ctrlport_resp_ack <= 1'b0;

      read_req_shift_reg <= 2'b0;

      ram_ch0_wea <= 1'b0;
      ram_ch1_wea <= 1'b0;

    end else begin

      read_req_shift_reg <= {read_req_shift_reg[0], s_ctrlport_req_rd};

      ram_ch0_wea <= 1'b0;
      ram_ch1_wea <= 1'b0;


      if (s_ctrlport_req_wr) begin

        s_ctrlport_resp_ack     <= 1'b1;
        s_ctrlport_resp_data    <= {32{1'bx}};
        s_ctrlport_resp_status  <= CTRL_STS_OKAY;

        case (register_base_address)
          BASE_ADDRESS + LED_CONTROL(0): begin
            ram_ch0_wea <= 1'b1;
            ram_ch1_wea <= 1'b1;
          end


          default: begin
            if (address_in_range) begin
              s_ctrlport_resp_status <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack <= 1'b0;
            end
          end
        endcase




      end else if (read_req_shift_reg[1]) begin

        s_ctrlport_resp_ack     <= 1'b1;
        s_ctrlport_resp_status  <= CTRL_STS_OKAY;
        s_ctrlport_resp_data    <= {32{1'b0}};

        case (register_base_address)
          BASE_ADDRESS + LED_CONTROL(0): begin
            s_ctrlport_resp_data <= ram_ch0_doa & LED_CONTROL_TYPE_MASK;
          end


          default: begin
            if (address_in_range) begin
              s_ctrlport_resp_status <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack <= 1'b0;
            end
          end
        endcase


      end else begin
        s_ctrlport_resp_ack <= 1'b0;
      end
    end
  end


  reg [ 7:0] ram_addr   =  8'b0;
  reg [31:0] ram_datain = 32'b0;
  always @(posedge ctrlport_clk) begin

    ram_addr   <= register_index;
    ram_datain <= s_ctrlport_req_data;


    ch0_rx2_led <= ram_ch0_dob[CH0_RX2_LED_EN];
    ch0_tx_led  <= ram_ch0_dob[CH0_TRX1_LED_EN + 1];
    ch0_rx_led  <= ram_ch0_dob[CH0_TRX1_LED_EN + 0];

    ch1_rx2_led <= ram_ch1_dob[CH1_RX2_LED_EN];
    ch1_tx_led  <= ram_ch1_dob[CH1_TRX1_LED_EN + 1];
    ch1_rx_led  <= ram_ch1_dob[CH1_TRX1_LED_EN + 0];
  end

  ram_2port #(
    .DWIDTH     (32),
    .AWIDTH     (8),
    .RW_MODE    ("READ-FIRST"),
    .RAM_TYPE   ("AUTOMATIC"),
    .OUT_REG    (0),
    .INIT_FILE  ("")
  ) ram_ch0_i (
    .clka   (ctrlport_clk),
    .ena    (1'b1),
    .wea    (ram_ch0_wea),
    .addra  (ram_addr),
    .dia    (ram_datain),
    .doa    (ram_ch0_doa),
    .clkb   (ctrlport_clk),
    .enb    (1'b1),
    .web    (1'b0),
    .addrb  (atr_config_rf0),
    .dib    (0),
    .dob    (ram_ch0_dob)
  );

  ram_2port #(
    .DWIDTH     (32),
    .AWIDTH     (8),
    .RW_MODE    ("READ-FIRST"),
    .RAM_TYPE   ("AUTOMATIC"),
    .OUT_REG    (0),
    .INIT_FILE  ("")
  ) ram_ch1_i (
    .clka   (ctrlport_clk),
    .ena    (1'b1),
    .wea    (ram_ch1_wea),
    .addra  (ram_addr),
    .dia    (ram_datain),
    .doa    (),
    .clkb   (ctrlport_clk),
    .enb    (1'b1),
    .web    (1'b0),
    .addrb  (atr_config_rf1),
    .dib    (0),
    .dob    (ram_ch1_dob));

endmodule
module led_control #(
  parameter [19:0]  BASE_ADDRESS = 0,
  parameter [19:0]  SIZE_ADDRESS = 0
) (

  input  wire        ctrlport_clk,
  input  wire        ctrlport_rst,


  input  wire        s_ctrlport_req_wr,
  input  wire        s_ctrlport_req_rd,
  input  wire [19:0] s_ctrlport_req_addr,
  input  wire [31:0] s_ctrlport_req_data,

  output reg         s_ctrlport_resp_ack,
  output reg  [ 1:0] s_ctrlport_resp_status = 2'b0,
  output reg  [31:0] s_ctrlport_resp_data = 32'b0,


  output reg         ch0_rx2_led,
  output reg         ch0_tx_led,
  output reg         ch0_rx_led,
  output reg         ch1_rx2_led,
  output reg         ch1_tx_led,
  output reg         ch1_rx_led,


  input  wire [ 7:0] atr_config_rf0,
  input  wire [ 7:0] atr_config_rf1
);


  `include "../regmap/led_setup_regmap_utils.vh"
  `include "../../../../../../lib/rfnoc/core/ctrlport.vh"




  reg         ram_ch0_wea;
  wire [31:0] ram_ch0_doa;
  wire [31:0] ram_ch0_dob;

  reg         ram_ch1_wea;
  wire [31:0] ram_ch1_dob;





  wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + SIZE_ADDRESS);

  reg  [ 1:0] read_req_shift_reg = 2'b0;


  wire [31:0] register_base_address = {s_ctrlport_req_addr[19:10], 8'b0, s_ctrlport_req_addr[1:0]};


  wire [ 7:0] register_index = s_ctrlport_req_addr[9:2];

  always @(posedge ctrlport_clk) begin

    if (ctrlport_rst) begin
      s_ctrlport_resp_ack <= 1'b0;

      read_req_shift_reg <= 2'b0;

      ram_ch0_wea <= 1'b0;
      ram_ch1_wea <= 1'b0;

    end else begin

      read_req_shift_reg <= {read_req_shift_reg[0], s_ctrlport_req_rd};

      ram_ch0_wea <= 1'b0;
      ram_ch1_wea <= 1'b0;


      if (s_ctrlport_req_wr) begin

        s_ctrlport_resp_ack     <= 1'b1;
        s_ctrlport_resp_data    <= {32{1'bx}};
        s_ctrlport_resp_status  <= CTRL_STS_OKAY;

        case (register_base_address)
          BASE_ADDRESS + LED_CONTROL(0): begin
            ram_ch0_wea <= 1'b1;
            ram_ch1_wea <= 1'b1;
          end


          default: begin
            if (address_in_range) begin
              s_ctrlport_resp_status <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack <= 1'b0;
            end
          end
        endcase




      end else if (read_req_shift_reg[1]) begin

        s_ctrlport_resp_ack     <= 1'b1;
        s_ctrlport_resp_status  <= CTRL_STS_OKAY;
        s_ctrlport_resp_data    <= {32{1'b0}};

        case (register_base_address)
          BASE_ADDRESS + LED_CONTROL(0): begin
            s_ctrlport_resp_data <= ram_ch0_doa & LED_CONTROL_TYPE_MASK;
          end


          default: begin
            if (address_in_range) begin
              s_ctrlport_resp_status <= CTRL_STS_CMDERR;


            end else begin
              s_ctrlport_resp_ack <= 1'b0;
            end
          end
        endcase


      end else begin
        s_ctrlport_resp_ack <= 1'b0;
      end
    end
  end


  reg [ 7:0] ram_addr   =  8'b0;
  reg [31:0] ram_datain = 32'b0;
  always @(posedge ctrlport_clk) begin

    ram_addr   <= register_index;
    ram_datain <= s_ctrlport_req_data;


    ch0_rx2_led <= ram_ch0_dob[CH0_RX2_LED_EN];
    ch0_tx_led  <= ram_ch0_dob[CH0_TRX1_LED_EN + 1];
    ch0_rx_led  <= ram_ch0_dob[CH0_TRX1_LED_EN + 0];

    ch1_rx2_led <= ram_ch1_dob[CH1_RX2_LED_EN];
    ch1_tx_led  <= ram_ch1_dob[CH1_TRX1_LED_EN + 1];
    ch1_rx_led  <= ram_ch1_dob[CH1_TRX1_LED_EN + 0];
  end

  ram_2port #(
    .DWIDTH     (32),
    .AWIDTH     (8),
    .RW_MODE    ("READ-FIRST"),
    .RAM_TYPE   ("AUTOMATIC"),
    .OUT_REG    (0),
    .INIT_FILE  ("")
  ) ram_ch0_i (
    .clka   (ctrlport_clk),
    .ena    (1'b1),
    .wea    (ram_ch0_wea),
    .addra  (ram_addr),
    .dia    (ram_datain),
    .doa    (ram_ch0_doa),
    .clkb   (ctrlport_clk),
    .enb    (1'b1),
    .web    (1'b0),
    .addrb  (atr_config_rf0),
    .dib    (0),
    .dob    (ram_ch0_dob)
  );

  ram_2port #(
    .DWIDTH     (32),
    .AWIDTH     (8),
    .RW_MODE    ("READ-FIRST"),
    .RAM_TYPE   ("AUTOMATIC"),
    .OUT_REG    (0),
    .INIT_FILE  ("")
  ) ram_ch1_i (
    .clka   (ctrlport_clk),
    .ena    (1'b1),
    .wea    (ram_ch1_wea),
    .addra  (ram_addr),
    .dia    (ram_datain),
    .doa    (),
    .clkb   (ctrlport_clk),
    .enb    (1'b1),
    .web    (1'b0),
    .addrb  (atr_config_rf1),
    .dib    (0),
    .dob    (ram_ch1_dob));

endmodule