data/full_repos/permissive/452305748/L6/sigma_16p/sigma_16p.v
1: b"%Error: data/full_repos/permissive/452305748/L6/sigma_16p/sigma_16p.v:25: Duplicate declaration of signal: 'data_out'\n                                                                        : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n    reg [11:0] data_out;\n               ^~~~~~~~\n        data/full_repos/permissive/452305748/L6/sigma_16p/sigma_16p.v:7: ... Location of original declaration\n                  output[11:0] data_out,  \n                               ^~~~~~~~\n%Error: data/full_repos/permissive/452305748/L6/sigma_16p/sigma_16p.v:26: Duplicate declaration of signal: 'syn_out'\n    reg syn_out;\n        ^~~~~~~\n        data/full_repos/permissive/452305748/L6/sigma_16p/sigma_16p.v:8: ... Location of original declaration\n                  output syn_out);\n                         ^~~~~~~\n%Error: Exiting due to 2 error(s)\n"
module sigma_16p (input clk,
                  input res,
                  input[7:0] data_in,
                  input syn_in,
                  output[11:0] data_out,
                  output syn_out);
    
    reg syn_in_n1;
    wire syn_pulse;
    assign syn_pulse = syn_in&syn_in_n1;
    reg [3:0] con_syn;
    
    wire [7:0] comp_8;
    wire [11:0] d_12;
    wire [7:0] comp_8_temp;
    assign comp_8_temp[6:0] = ~data_in[6:0]+1;

    assign comp_8 = data_in[7]?{data_in[7],comp_8_temp[6:0]}:data_in;

    assign d_12 = {comp_8[7], comp_8[7], comp_8[7], comp_8[7], comp_8};
    
    reg[11:0] sigma;
    reg [11:0] data_out;
    reg syn_out;
    
    always @(posedge clk or negedge res) begin
        if (~res) begin
            syn_in_n1 <= 0;
            con_syn   <= 0;
            sigma     <= 0;
            data_out  <= 0;
            syn_out   <= 1;
        end
        else begin
            syn_in_n1 <= ~syn_in;
            if (syn_pulse) begin
                con_syn <= con_syn +1;
            end
                if (syn_pulse) begin
                    if (con_syn == 15) begin
                        sigma    <= d_12;
                        data_out <= sigma;
                        syn_out  <= 1;
                    end
                    else
                    begin
                        sigma <= sigma+12;
                    end
                end
            end
    end
endmodule
module sigma_16p (input clk,
                  input res,
                  input[7:0] data_in,
                  input syn_in,
                  output[11:0] data_out,
                  output syn_out);

    
    reg syn_in_n1;
    wire syn_pulse;
    assign syn_pulse = syn_in&syn_in_n1;
    reg [3:0] con_syn;
    
    wire [7:0] comp_8;
    wire [11:0] d_12;
    wire [7:0] comp_8_temp;
    assign comp_8_temp[6:0] = ~data_in[6:0]+1;

    assign comp_8 = data_in[7]?{data_in[7],comp_8_temp[6:0]}:data_in;

    assign d_12 = {comp_8[7], comp_8[7], comp_8[7], comp_8[7], comp_8};
    
    reg[11:0] sigma;
    reg [11:0] data_out;
    reg syn_out;
    
    always @(posedge clk or negedge res) begin
        if (~res) begin
            syn_in_n1 <= 0;
            con_syn   <= 0;
            sigma     <= 0;
            data_out  <= 0;
            syn_out   <= 1;
        end
        else begin
            syn_in_n1 <= ~syn_in;
            if (syn_pulse) begin
                con_syn <= con_syn +1;
            end
                if (syn_pulse) begin
                    if (con_syn == 15) begin
                        sigma    <= d_12;
                        data_out <= sigma;
                        syn_out  <= 1;
                    end
                    else
                    begin
                        sigma <= sigma+12;
                    end
                end
            end
    end
endmodule