data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential Logic/Finite State Machines/Lemmings1/top_module.v
1: b'%Error: Cannot find file containing module: Logic/Finite\n        ... Looked in:\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.v\n             data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential/Logic/Finite.sv\n             Logic/Finite\n             Logic/Finite.v\n             Logic/Finite.sv\n             obj_dir/Logic/Finite\n             obj_dir/Logic/Finite.v\n             obj_dir/Logic/Finite.sv\n%Error: Cannot find file containing module: State\n%Error: Cannot find file containing module: Machines/Lemmings1,data/full_repos/permissive/500128826\n%Error: Cannot find file containing module: data/full_repos/permissive/500128826/HDLBits/Circuits/Sequential\n%Error: Cannot find file containing module: Machines/Lemmings1/top_module.v\n%Error: Exiting due to 5 error(s)\n'
module top_module (
    input  wire clk,
    input  wire areset,
    input  wire bump_left,
    input  wire bump_right,
    output reg  walk_left,
    output reg  walk_right
);

  parameter LEFT = 1'd0, RIGHT = 1'd1;
  reg state, next_state;


  always @(*) begin
    casez ({
      bump_left, bump_right, state
    })
      {2'b11, LEFT} : next_state = RIGHT;
      {2'b11, RIGHT} : next_state = LEFT;
      {2'b10, LEFT} : next_state = RIGHT;
      {2'b01, RIGHT} : next_state = LEFT;
      default:  next_state = state;
    endcase
  end


  always @(posedge clk, posedge areset) begin
    if (areset) state <= LEFT;
    else if (clk) begin
      state <= next_state;
    end
  end


  always @(*) begin
    case (state)
      LEFT: {walk_left, walk_right} = 2'b10;
      RIGHT: {walk_left, walk_right} = 2'b01;
      default: {walk_left, walk_right} = 2'b00;
    endcase
  end
endmodule
module top_module (
    input  wire clk,
    input  wire areset,
    input  wire bump_left,
    input  wire bump_right,
    output reg  walk_left,
    output reg  walk_right
);


  parameter LEFT = 1'd0, RIGHT = 1'd1;
  reg state, next_state;


  always @(*) begin
    casez ({
      bump_left, bump_right, state
    })
      {2'b11, LEFT} : next_state = RIGHT;
      {2'b11, RIGHT} : next_state = LEFT;
      {2'b10, LEFT} : next_state = RIGHT;
      {2'b01, RIGHT} : next_state = LEFT;
      default:  next_state = state;
    endcase
  end


  always @(posedge clk, posedge areset) begin
    if (areset) state <= LEFT;
    else if (clk) begin
      state <= next_state;
    end
  end


  always @(*) begin
    case (state)
      LEFT: {walk_left, walk_right} = 2'b10;
      RIGHT: {walk_left, walk_right} = 2'b01;
      default: {walk_left, walk_right} = 2'b00;
    endcase
  end
endmodule