data/full_repos/permissive/423539813/testbenches/alu_testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/423539813/testbenches/alu_testbench.v:31: Unsupported: Ignoring delay on this delayed statement.\n    #10;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/423539813/testbenches/alu_testbench.v:11: Cannot find file containing module: \'alu\'\nalu uut(\n^~~\n        ... Looked in:\n             data/full_repos/permissive/423539813/testbenches,data/full_repos/permissive/423539813/alu\n             data/full_repos/permissive/423539813/testbenches,data/full_repos/permissive/423539813/alu.v\n             data/full_repos/permissive/423539813/testbenches,data/full_repos/permissive/423539813/alu.sv\n             alu\n             alu.v\n             alu.sv\n             obj_dir/alu\n             obj_dir/alu.v\n             obj_dir/alu.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module alu_testbench;
reg [31:0] A,B;
reg [3:0] ALU_Sel;
wire [31:0] ALU_Out;
wire CarryOut;
wire ZeroOut;

alu uut(
    .A(A),
    .B(B),
    .ALU_Sel(ALU_Sel),
    .ALU_Out(ALU_Out),
    .CarryOut(CarryOut),
    .ZeroOut(ZeroOut)
);







initial begin
    A = 0;
    B = 0;
    ALU_Sel= 0;
    
    #10;
    
    A = 2;
    B = 2;
    ALU_Sel = 4'b0001;

end

endmodule
module alu_testbench;

reg [31:0] A,B;
reg [3:0] ALU_Sel;
wire [31:0] ALU_Out;
wire CarryOut;
wire ZeroOut;

alu uut(
    .A(A),
    .B(B),
    .ALU_Sel(ALU_Sel),
    .ALU_Out(ALU_Out),
    .CarryOut(CarryOut),
    .ZeroOut(ZeroOut)
);







initial begin
    A = 0;
    B = 0;
    ALU_Sel= 0;
    
    #10;
    
    A = 2;
    B = 2;
    ALU_Sel = 4'b0001;

end

endmodule