data/full_repos/permissive/458737381/src/verilog-parser/tests/scbuf_slowsig_buf.v
data/verilator_xmls/cbca7fee-2c25-4b85-bca9-e82431aad6d6.xml
module scbuf_slowsig_buf
 (
  mem_write_disable_buf,
  sehold_buf,
  se_buf,
  arst_l_buf,


  mem_write_disable,
  sehold,
  se,
  arst_l
 );


output    mem_write_disable_buf;
output    sehold_buf;
output    se_buf;
output    arst_l_buf;

input     mem_write_disable;
input     sehold;
input     se;
input     arst_l;


assign  mem_write_disable_buf = mem_write_disable;
assign  sehold_buf            = sehold;
assign  se_buf                = se;
assign  arst_l_buf            = arst_l;


endmodule
module scbuf_slowsig_buf
 (
  mem_write_disable_buf,
  sehold_buf,
  se_buf,
  arst_l_buf,


  mem_write_disable,
  sehold,
  se,
  arst_l
 );



output    mem_write_disable_buf;
output    sehold_buf;
output    se_buf;
output    arst_l_buf;

input     mem_write_disable;
input     sehold;
input     se;
input     arst_l;


assign  mem_write_disable_buf = mem_write_disable;
assign  sehold_buf            = sehold;
assign  se_buf                = se;
assign  arst_l_buf            = arst_l;


endmodule