data/full_repos/permissive/426889244/verilog/SoC.v
1: b"%Error: data/full_repos/permissive/426889244/verilog/SoC.v:17: Cannot find file containing module: 'IMEM'\n    IMEM imem_inst(\n    ^~~~\n        ... Looked in:\n             data/full_repos/permissive/426889244/verilog,data/full_repos/permissive/426889244/IMEM\n             data/full_repos/permissive/426889244/verilog,data/full_repos/permissive/426889244/IMEM.v\n             data/full_repos/permissive/426889244/verilog,data/full_repos/permissive/426889244/IMEM.sv\n             IMEM\n             IMEM.v\n             IMEM.sv\n             obj_dir/IMEM\n             obj_dir/IMEM.v\n             obj_dir/IMEM.sv\n%Error: data/full_repos/permissive/426889244/verilog/SoC.v:24: Cannot find file containing module: 'DMEM'\n    DMEM dmem_inst(\n    ^~~~\n%Error: data/full_repos/permissive/426889244/verilog/SoC.v:34: Cannot find file containing module: 'Core'\n    Core core0(\n    ^~~~\n%Error: Exiting due to 3 error(s)\n"
module SoC (
    input wire clk,
    input wire reset,
    input wire system_ena,
    input wire pause
);

    wire[31:0] IMEM_rdata;
    wire[31:0] DMEM_rdata;

    wire[31:0] IMEM_raddr;
    wire[31:0] DMEM_addr;
    wire[31:0] fetch_DMEM_addr;
    wire[31:0] DMEM_wdata;
    wire DMEM_we;

    IMEM imem_inst(
        .a(IMEM_raddr[31:2]),

        .spo(IMEM_rdata)
    );

    
    DMEM dmem_inst(
        .clk(clk),
        .we(DMEM_we),
        .ask_addr(DMEM_addr),
        .fetch_addr(fetch_DMEM_addr),
        .wdata(DMEM_wdata),

        .rdata(DMEM_rdata)
    );

    Core core0(
        .clk(clk),
        .reset(reset),
        .cpu_ena(system_ena),
        .out_interruption(pause),

        .IMEM_rdata(IMEM_rdata),
        .DMEM_rdata(DMEM_rdata),

        .IMEM_raddr(IMEM_raddr),
        .DMEM_addr(DMEM_addr),
        .fetch_DMEM_addr(fetch_DMEM_addr),
        .DMEM_wdata(DMEM_wdata),
        .DMEM_we(DMEM_we)
    );
    
endmodule
module SoC (
    input wire clk,
    input wire reset,
    input wire system_ena,
    input wire pause
);


    wire[31:0] IMEM_rdata;
    wire[31:0] DMEM_rdata;

    wire[31:0] IMEM_raddr;
    wire[31:0] DMEM_addr;
    wire[31:0] fetch_DMEM_addr;
    wire[31:0] DMEM_wdata;
    wire DMEM_we;

    IMEM imem_inst(
        .a(IMEM_raddr[31:2]),

        .spo(IMEM_rdata)
    );

    
    DMEM dmem_inst(
        .clk(clk),
        .we(DMEM_we),
        .ask_addr(DMEM_addr),
        .fetch_addr(fetch_DMEM_addr),
        .wdata(DMEM_wdata),

        .rdata(DMEM_rdata)
    );

    Core core0(
        .clk(clk),
        .reset(reset),
        .cpu_ena(system_ena),
        .out_interruption(pause),

        .IMEM_rdata(IMEM_rdata),
        .DMEM_rdata(DMEM_rdata),

        .IMEM_raddr(IMEM_raddr),
        .DMEM_addr(DMEM_addr),
        .fetch_DMEM_addr(fetch_DMEM_addr),
        .DMEM_wdata(DMEM_wdata),
        .DMEM_we(DMEM_we)
    );
    
endmodule