data/full_repos/permissive/43858668/final_verilog/src/clib/c_matrix_arbiter.v
1: b'%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_matrix_arbiter.v:35: Cannot find include file: c_constants.v\n`include "c_constants.v" \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_constants.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_constants.v.v\n             data/full_repos/permissive/43858668/final_verilog/src/clib,data/full_repos/permissive/43858668/c_constants.v.sv\n             c_constants.v\n             c_constants.v.v\n             c_constants.v.sv\n             obj_dir/c_constants.v\n             obj_dir/c_constants.v.v\n             obj_dir/c_constants.v.sv\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_matrix_arbiter.v:43: Define or directive not defined: \'`RESET_TYPE_ASYNC\'\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                          ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_matrix_arbiter.v:43: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n   parameter reset_type = `RESET_TYPE_ASYNC;\n                                           ^\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_matrix_arbiter.v:142: Define or directive not defined: \'`BINARY_OP_OR\'\n        .op(`BINARY_OP_OR))\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/43858668/final_verilog/src/clib/c_matrix_arbiter.v:160: Define or directive not defined: \'`BINARY_OP_AND\'\n        .op(`BINARY_OP_AND))\n            ^~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n'
module c_matrix_arbiter
  (clk, reset, active, req_pr, gnt_pr, gnt, update);
   
`include "c_constants.v"
   

   parameter num_ports = 32;
   

   parameter num_priorities = 1;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   input clk;
   input reset;
   input active;
   

   input [0:num_priorities*num_ports-1] req_pr;
   

   output [0:num_priorities*num_ports-1] gnt_pr;
   wire [0:num_priorities*num_ports-1] 	 gnt_pr;
   

   output [0:num_ports-1] 		 gnt;
   wire [0:num_ports-1] 		 gnt;
   

   input 				 update;
   
   wire [0:num_priorities*num_ports-1] 	 gnt_intm_pr;
   

   wire [0:num_ports*num_ports-1] 	 state;
   
   genvar 				 row;
   
   generate
      
      for(row = 0; row < num_ports; row = row + 1)
	begin:rows
	   
	   genvar prio;
	   
	   for(prio = 0; prio < num_priorities; prio = prio + 1)
	     begin:prios
		


		assign gnt_intm_pr[prio*num_ports+row] 
		  = req_pr[prio*num_ports+row] &
		    (&(state[row*num_ports:(row+1)*num_ports-1] | 
		       ~req_pr[prio*num_ports:(prio+1)*num_ports-1]));
		
	     end
	   
	   genvar col;
	   
	   for(col = 0; col < num_ports; col = col + 1)
	     begin:cols
		


		if(col < row)
		  assign state[row*num_ports+col] = ~state[col*num_ports+row];
		

		else if(col == row)
		  assign state[row*num_ports+col] = 1'b1;
		

		else if(col > row)
		  begin
		     
		     wire state_s, state_q;
		     assign state_s = update ? 
				      ((state_q | gnt[col]) & ~gnt[row]) : 
				      state_q;
		     c_dff
		       #(.width(1),
			 .reset_type(reset_type),
			 .reset_value(1'b1))
		     stateq
		       (.clk(clk),
			.reset(reset),
			.active(active),
			.d(state_s),
			.q(state_q));
		     
		     assign state[row*num_ports+col] = state_q;
		     
		  end
		
	     end
	   
	end
      
      if(num_priorities == 1)
	begin
	   assign gnt_pr = gnt_intm_pr;
	   assign gnt = gnt_intm_pr;
	end
      else if(num_priorities > 1)
	begin
	   
	   wire [0:num_priorities-1] 	any_req_pr;
	   c_reduce_bits
	     #(.num_ports(num_priorities),
	       .width(num_ports),
	       .op(`BINARY_OP_OR))
	   any_req_pr_rb
	     (.data_in(req_pr),
	      .data_out(any_req_pr));
	   
	   wire [0:num_priorities-1] 	any_req_mod_pr;
	   assign any_req_mod_pr = {any_req_pr[0:num_priorities-2], 1'b1};
	   
	   wire [0:num_priorities-1] 	sel_pr;
	   c_lod
	     #(.width(num_priorities))
	   sel_pr_lod
	     (.data_in(any_req_mod_pr),
	      .data_out(sel_pr));
	   
	   c_gate_bits
	     #(.num_ports(num_priorities),
	       .width(num_ports),
	       .op(`BINARY_OP_AND))
	   gnt_pr_gb
	     (.select(sel_pr),
	      .data_in(gnt_intm_pr),
	      .data_out(gnt_pr));
	   
	   c_select_1ofn
	     #(.num_ports(num_priorities),
	       .width(num_ports))
	   gnt_sel
	     (.select(sel_pr),
	      .data_in(gnt_intm_pr),
	      .data_out(gnt));
	   
	end
      
   endgenerate
   
endmodule
module c_matrix_arbiter
  (clk, reset, active, req_pr, gnt_pr, gnt, update);

   
`include "c_constants.v"
   

   parameter num_ports = 32;
   

   parameter num_priorities = 1;
   
   parameter reset_type = `RESET_TYPE_ASYNC;
   
   input clk;
   input reset;
   input active;
   

   input [0:num_priorities*num_ports-1] req_pr;
   

   output [0:num_priorities*num_ports-1] gnt_pr;
   wire [0:num_priorities*num_ports-1] 	 gnt_pr;
   

   output [0:num_ports-1] 		 gnt;
   wire [0:num_ports-1] 		 gnt;
   

   input 				 update;
   
   wire [0:num_priorities*num_ports-1] 	 gnt_intm_pr;
   

   wire [0:num_ports*num_ports-1] 	 state;
   
   genvar 				 row;
   
   generate
      
      for(row = 0; row < num_ports; row = row + 1)
	begin:rows
	   
	   genvar prio;
	   
	   for(prio = 0; prio < num_priorities; prio = prio + 1)
	     begin:prios
		


		assign gnt_intm_pr[prio*num_ports+row] 
		  = req_pr[prio*num_ports+row] &
		    (&(state[row*num_ports:(row+1)*num_ports-1] | 
		       ~req_pr[prio*num_ports:(prio+1)*num_ports-1]));
		
	     end
	   
	   genvar col;
	   
	   for(col = 0; col < num_ports; col = col + 1)
	     begin:cols
		


		if(col < row)
		  assign state[row*num_ports+col] = ~state[col*num_ports+row];
		

		else if(col == row)
		  assign state[row*num_ports+col] = 1'b1;
		

		else if(col > row)
		  begin
		     
		     wire state_s, state_q;
		     assign state_s = update ? 
				      ((state_q | gnt[col]) & ~gnt[row]) : 
				      state_q;
		     c_dff
		       #(.width(1),
			 .reset_type(reset_type),
			 .reset_value(1'b1))
		     stateq
		       (.clk(clk),
			.reset(reset),
			.active(active),
			.d(state_s),
			.q(state_q));
		     
		     assign state[row*num_ports+col] = state_q;
		     
		  end
		
	     end
	   
	end
      
      if(num_priorities == 1)
	begin
	   assign gnt_pr = gnt_intm_pr;
	   assign gnt = gnt_intm_pr;
	end
      else if(num_priorities > 1)
	begin
	   
	   wire [0:num_priorities-1] 	any_req_pr;
	   c_reduce_bits
	     #(.num_ports(num_priorities),
	       .width(num_ports),
	       .op(`BINARY_OP_OR))
	   any_req_pr_rb
	     (.data_in(req_pr),
	      .data_out(any_req_pr));
	   
	   wire [0:num_priorities-1] 	any_req_mod_pr;
	   assign any_req_mod_pr = {any_req_pr[0:num_priorities-2], 1'b1};
	   
	   wire [0:num_priorities-1] 	sel_pr;
	   c_lod
	     #(.width(num_priorities))
	   sel_pr_lod
	     (.data_in(any_req_mod_pr),
	      .data_out(sel_pr));
	   
	   c_gate_bits
	     #(.num_ports(num_priorities),
	       .width(num_ports),
	       .op(`BINARY_OP_AND))
	   gnt_pr_gb
	     (.select(sel_pr),
	      .data_in(gnt_intm_pr),
	      .data_out(gnt_pr));
	   
	   c_select_1ofn
	     #(.num_ports(num_priorities),
	       .width(num_ports))
	   gnt_sel
	     (.select(sel_pr),
	      .data_in(gnt_intm_pr),
	      .data_out(gnt));
	   
	end
      
   endgenerate
   
endmodule