data/full_repos/permissive/498471995/sume/felix/simple_sume_switch/test/ip_repo/std/cores/nf_10ge_attachment_v1_0_0/hdl/data_synch.v
data/verilator_xmls/e19d0a3f-d826-4c7c-87fe-f7670e0698bb.xml
module data_sync_block #(
  parameter   C_NUM_SYNC_REGS = 5
  )
  (
    input   wire  clk,
    input   wire  data_in,
    output  wire  data_out
  );
  
(* shreg_extract = "no", ASYNC_REG = "TRUE" *) reg  [C_NUM_SYNC_REGS-1:0]    sync1_r = {C_NUM_SYNC_REGS{1'b1}};




  always @(posedge clk) begin
    sync1_r <= {sync1_r[C_NUM_SYNC_REGS-2:0], data_in};
  end    
  
  assign data_out = sync1_r[C_NUM_SYNC_REGS-1];
endmodule
module data_sync_block #(
  parameter   C_NUM_SYNC_REGS = 5
  )
  (
    input   wire  clk,
    input   wire  data_in,
    output  wire  data_out
  );

  
(* shreg_extract = "no", ASYNC_REG = "TRUE" *) reg  [C_NUM_SYNC_REGS-1:0]    sync1_r = {C_NUM_SYNC_REGS{1'b1}};




  always @(posedge clk) begin
    sync1_r <= {sync1_r[C_NUM_SYNC_REGS-2:0], data_in};
  end    
  
  assign data_out = sync1_r[C_NUM_SYNC_REGS-1];
endmodule