data/full_repos/permissive/410822585/cell.v
1: b"%Error: data/full_repos/permissive/410822585/cell.v:22: syntax error, unexpected output, expecting ')' or ','\n     output diff, bout\n     ^~~~~~\n%Error: data/full_repos/permissive/410822585/cell.v:27: syntax error, unexpected pmos\n     pmos q1 (t1, vdd, x);\n     ^~~~\n%Error: data/full_repos/permissive/410822585/cell.v:39: syntax error, unexpected output, expecting ')' or ','\n     output diff, bout\n     ^~~~~~\n%Error: data/full_repos/permissive/410822585/cell.v:44: syntax error, unexpected pmos\n     pmos q1 (t1, vdd, x);\n     ^~~~\n%Error: Exiting due to 4 error(s)\n"
module exdcr(
    output bout, diff,
    input x, y, bin
);
    wire t1, t2, t3;
    supply1 vdd;
    supply0 gnd;
    pmos q1 (t1, vdd, x);
    nmos q2 (t1, gnd, x);
    pmos q3 (t2, x, y);
    nmos q4 (t2, t1, y);
    pmos q5 (t3, vdd, t2);
    nmos q6 (t3, gnd, t2);
    pmos q7 (diff, t2, bin);
    nmos q8 (diff, t3, bin);
    pmos q9 (bout, y, t2);
    nmos q10 (bout, bin, t2);
endmodule
module exdcr(
    output bout, diff,
    input x, y, bin
);

    wire t1, t2, t3;
    supply1 vdd;
    supply0 gnd;
    pmos q1 (t1, vdd, x);
    nmos q2 (t1, gnd, x);
    pmos q3 (t2, x, y);
    nmos q4 (t2, t1, y);
    pmos q5 (t3, vdd, t2);
    nmos q6 (t3, gnd, t2);
    pmos q7 (diff, t2, bin);
    nmos q8 (diff, t3, bin);
    pmos q9 (bout, y, t2);
    nmos q10 (bout, bin, t2);
endmodule