data/full_repos/permissive/431605717/Code/RV32IM/ID_EX.v
data/verilator_xmls/81dfc94a-67bd-47dc-82fc-a27d2bef61af.xml
module idexreg(clk,clrn,PCsrc,inst_i,pc_i,inst_decode_i,imm_in,read_data1_i,read_data2_i,wr_i,rs1_i,rs2_i,inst_o,pc_o,inst_decode_o,imm_out,read_data1_o,read_data2_o,wr_o,rs1_o,rs2_o);
    input             clk, clrn;
    input             PCsrc;
    input      [31:0] pc_i;
    input      [31:0] inst_i;
    input      [36:0] inst_decode_i;
    input      [31:0] imm_in;
    input      [31:0] read_data1_i;
    input      [31:0] read_data2_i;
    input       [4:0] wr_i;
    input       [4:0] rs1_i;
    input       [4:0] rs2_i;
    
    output reg [31:0] pc_o;
    output reg [31:0] inst_o;
    output reg [36:0] inst_decode_o;
    output reg [31:0] imm_out;
    output reg [31:0] read_data1_o;
    output reg [31:0] read_data2_o;
    output reg  [4:0] wr_o;
    output reg  [4:0] rs1_o;
    output reg  [4:0] rs2_o;
        
    always @ (posedge clk) begin
        if (clrn && (!PCsrc)) begin
            pc_o          <= pc_i;
            inst_o        <= inst_i;
            inst_decode_o <= inst_decode_i;
            imm_out       <= imm_in;
            read_data1_o  <= read_data1_i;
            read_data2_o  <= read_data2_i;
            wr_o          <= wr_i;
            rs1_o         <= rs1_i;
            rs2_o         <= rs2_i;
        end
        else begin
            pc_o          <= 0;
            inst_o        <= 0;
            inst_decode_o <= 0;
            imm_out       <= 0;
            read_data1_o  <= 0;
            read_data2_o  <= 0;
            wr_o          <= 0;
            rs1_o         <= 0;
            rs2_o         <= 0;
        end
    end
    
endmodule
module idexreg(clk,clrn,PCsrc,inst_i,pc_i,inst_decode_i,imm_in,read_data1_i,read_data2_i,wr_i,rs1_i,rs2_i,inst_o,pc_o,inst_decode_o,imm_out,read_data1_o,read_data2_o,wr_o,rs1_o,rs2_o);

    input             clk, clrn;
    input             PCsrc;
    input      [31:0] pc_i;
    input      [31:0] inst_i;
    input      [36:0] inst_decode_i;
    input      [31:0] imm_in;
    input      [31:0] read_data1_i;
    input      [31:0] read_data2_i;
    input       [4:0] wr_i;
    input       [4:0] rs1_i;
    input       [4:0] rs2_i;
    
    output reg [31:0] pc_o;
    output reg [31:0] inst_o;
    output reg [36:0] inst_decode_o;
    output reg [31:0] imm_out;
    output reg [31:0] read_data1_o;
    output reg [31:0] read_data2_o;
    output reg  [4:0] wr_o;
    output reg  [4:0] rs1_o;
    output reg  [4:0] rs2_o;
        
    always @ (posedge clk) begin
        if (clrn && (!PCsrc)) begin
            pc_o          <= pc_i;
            inst_o        <= inst_i;
            inst_decode_o <= inst_decode_i;
            imm_out       <= imm_in;
            read_data1_o  <= read_data1_i;
            read_data2_o  <= read_data2_i;
            wr_o          <= wr_i;
            rs1_o         <= rs1_i;
            rs2_o         <= rs2_i;
        end
        else begin
            pc_o          <= 0;
            inst_o        <= 0;
            inst_decode_o <= 0;
            imm_out       <= 0;
            read_data1_o  <= 0;
            read_data2_o  <= 0;
            wr_o          <= 0;
            rs1_o         <= 0;
            rs2_o         <= 0;
        end
    end
    
endmodule