data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_subcore/rtl/wfg_subcore.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/500717851/verilog/rtl/wfg/wfg_subcore/rtl/wfg_subcore.sv:73: Operator ASSIGNDLY expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n                                                                                                      : ... In instance wfg_subcore\n                subcycle_count   <= 8\'d0;\n                                 ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module wfg_subcore (
    input wire clk,
    input wire rst_n,
    input wire en_i,


    input wire [ 7:0] wfg_sync_count_i,
    input wire [15:0] wfg_subcycle_count_i,


    output wire       wfg_subcore_sync_o,
    output wire       wfg_subcore_subcycle_o,
    output wire       wfg_subcore_start_o,
    output wire [7:0] wfg_subcore_subcycle_cnt_o,
    output wire       active_o
);





    logic [15:0]   subcycle_count;
    logic [ 7:0]   sync_count;
    logic        temp_subcycle;
    logic        temp_sync;
    logic        subcycle_dly;
    logic        sync_dly;
    logic        en_i_dly;
    logic [ 7:0]   subcycle_pls_cnt;





    always @(posedge clk, negedge rst_n) begin

        if (~rst_n) begin
            subcycle_count <= 16'd0;
            sync_count    <=  8'd0;
            temp_subcycle <=  1'b0;
            temp_sync    <=  1'b0;
            subcycle_pls_cnt  <=  8'd0;
        end else begin

            if (en_i) begin

                if (subcycle_count > 0) begin
                    temp_subcycle  <= temp_subcycle;
                    subcycle_count <= subcycle_count - 1;
                end else begin
                    temp_subcycle  <= ~temp_subcycle;
                    subcycle_count <= (wfg_subcycle_count_i);

                    if (sync_count > 0) begin
                        temp_sync  <= temp_sync;
                        sync_count <= sync_count - 1;
                    end else begin
                        temp_sync  <= ~temp_sync;
                        sync_count <= (wfg_sync_count_i);
                    end

                end

                if (wfg_subcore_subcycle_o) begin
                    subcycle_pls_cnt <= subcycle_pls_cnt + 1;
                end

            end else begin
                subcycle_count   <= 8'd0;
                sync_count       <= 8'd0;
                temp_subcycle    <= 1'b0;
                temp_sync        <= 1'b0;
                subcycle_pls_cnt <= 8'd0;
            end

            subcycle_dly <= temp_subcycle;
            sync_dly     <= temp_sync;
            en_i_dly     <= en_i;

            if (wfg_subcore_sync_o) begin
                subcycle_pls_cnt <= 8'd0;
            end

        end

    end

    assign wfg_subcore_subcycle_o     = temp_subcycle & ~subcycle_dly;
    assign wfg_subcore_sync_o         = temp_sync & ~sync_dly;
    assign active_o                   = en_i;
    assign wfg_subcore_start_o        = en_i & ~en_i_dly;
    assign wfg_subcore_subcycle_cnt_o = subcycle_pls_cnt;

endmodule
module wfg_subcore (
    input wire clk,
    input wire rst_n,
    input wire en_i,


    input wire [ 7:0] wfg_sync_count_i,
    input wire [15:0] wfg_subcycle_count_i,


    output wire       wfg_subcore_sync_o,
    output wire       wfg_subcore_subcycle_o,
    output wire       wfg_subcore_start_o,
    output wire [7:0] wfg_subcore_subcycle_cnt_o,
    output wire       active_o
);






    logic [15:0]   subcycle_count;
    logic [ 7:0]   sync_count;
    logic        temp_subcycle;
    logic        temp_sync;
    logic        subcycle_dly;
    logic        sync_dly;
    logic        en_i_dly;
    logic [ 7:0]   subcycle_pls_cnt;





    always @(posedge clk, negedge rst_n) begin

        if (~rst_n) begin
            subcycle_count <= 16'd0;
            sync_count    <=  8'd0;
            temp_subcycle <=  1'b0;
            temp_sync    <=  1'b0;
            subcycle_pls_cnt  <=  8'd0;
        end else begin

            if (en_i) begin

                if (subcycle_count > 0) begin
                    temp_subcycle  <= temp_subcycle;
                    subcycle_count <= subcycle_count - 1;
                end else begin
                    temp_subcycle  <= ~temp_subcycle;
                    subcycle_count <= (wfg_subcycle_count_i);

                    if (sync_count > 0) begin
                        temp_sync  <= temp_sync;
                        sync_count <= sync_count - 1;
                    end else begin
                        temp_sync  <= ~temp_sync;
                        sync_count <= (wfg_sync_count_i);
                    end

                end

                if (wfg_subcore_subcycle_o) begin
                    subcycle_pls_cnt <= subcycle_pls_cnt + 1;
                end

            end else begin
                subcycle_count   <= 8'd0;
                sync_count       <= 8'd0;
                temp_subcycle    <= 1'b0;
                temp_sync        <= 1'b0;
                subcycle_pls_cnt <= 8'd0;
            end

            subcycle_dly <= temp_subcycle;
            sync_dly     <= temp_sync;
            en_i_dly     <= en_i;

            if (wfg_subcore_sync_o) begin
                subcycle_pls_cnt <= 8'd0;
            end

        end

    end

    assign wfg_subcore_subcycle_o     = temp_subcycle & ~subcycle_dly;
    assign wfg_subcore_sync_o         = temp_sync & ~sync_dly;
    assign active_o                   = en_i;
    assign wfg_subcore_start_o        = en_i & ~en_i_dly;
    assign wfg_subcore_subcycle_cnt_o = subcycle_pls_cnt;

endmodule