data/full_repos/permissive/493019833/test/testcase/firrtl/RealGCD2/sbt/RealGCD2.v
data/verilator_xmls/364d6af6-d2cb-4659-a3e6-254c062bdf41.xml
module RealGCD2(
  input         clock,
  input         reset,
  output        io_in_ready,
  input         io_in_valid,
  input  [15:0] io_in_bits_a,
  input  [15:0] io_in_bits_b,
  output        io_out_valid,
  output [15:0] io_out_bits
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif
  reg [15:0] x;
  reg [15:0] y;
  reg  p;
  wire  _T_41 = ~p;
  wire [15:0] _GEN_0 = io_in_valid & _T_41 ? io_in_bits_a : x;
  wire [15:0] _GEN_1 = io_in_valid & _T_41 ? io_in_bits_b : y;
  wire  _GEN_2 = io_in_valid & _T_41 | p;
  wire  _T_48 = ~(x > y);
  wire [15:0] _T_50 = y - x;
  assign io_in_ready = ~p;
  assign io_out_valid = y == 16'h0 & p;
  assign io_out_bits = x;
  always @(posedge clock) begin
    if (p) begin
      if (x > y) begin
        x <= y;
      end else begin
        x <= _GEN_0;
      end
    end else begin
      x <= _GEN_0;
    end
    if (p) begin
      if (_T_48) begin
        y <= _T_50;
      end else if (x > y) begin
        y <= x;
      end else begin
        y <= _GEN_1;
      end
    end else begin
      y <= _GEN_1;
    end
    if (reset) begin
      p <= 1'h0;
    end else if (io_out_valid) begin
      p <= 1'h0;
    end else begin
      p <= _GEN_2;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  x = _RAND_0[15:0];
  _RAND_1 = {1{`RANDOM}};
  y = _RAND_1[15:0];
  _RAND_2 = {1{`RANDOM}};
  p = _RAND_2[0:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule
module RealGCD2(
  input         clock,
  input         reset,
  output        io_in_ready,
  input         io_in_valid,
  input  [15:0] io_in_bits_a,
  input  [15:0] io_in_bits_b,
  output        io_out_valid,
  output [15:0] io_out_bits
);

`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif
  reg [15:0] x;
  reg [15:0] y;
  reg  p;
  wire  _T_41 = ~p;
  wire [15:0] _GEN_0 = io_in_valid & _T_41 ? io_in_bits_a : x;
  wire [15:0] _GEN_1 = io_in_valid & _T_41 ? io_in_bits_b : y;
  wire  _GEN_2 = io_in_valid & _T_41 | p;
  wire  _T_48 = ~(x > y);
  wire [15:0] _T_50 = y - x;
  assign io_in_ready = ~p;
  assign io_out_valid = y == 16'h0 & p;
  assign io_out_bits = x;
  always @(posedge clock) begin
    if (p) begin
      if (x > y) begin
        x <= y;
      end else begin
        x <= _GEN_0;
      end
    end else begin
      x <= _GEN_0;
    end
    if (p) begin
      if (_T_48) begin
        y <= _T_50;
      end else if (x > y) begin
        y <= x;
      end else begin
        y <= _GEN_1;
      end
    end else begin
      y <= _GEN_1;
    end
    if (reset) begin
      p <= 1'h0;
    end else if (io_out_valid) begin
      p <= 1'h0;
    end else begin
      p <= _GEN_2;
    end
  end

`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  x = _RAND_0[15:0];
  _RAND_1 = {1{`RANDOM}};
  y = _RAND_1[15:0];
  _RAND_2 = {1{`RANDOM}};
  p = _RAND_2[0:0];
`endif
  `endif
end
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif
endmodule