data/full_repos/permissive/491294671/timer_input_control/div_100/div_100.v
data/verilator_xmls/7649de25-a148-44ef-90bc-e1729a2a9fc7.xml
module div_100(input clock, output wire clock_div);
  
  wire clock_2, clock_4, clock_20;
  
  div_2 D2_1(clock, clock_2);
  div_2 D2_2(clock_2, clock_4);
  div_5 D5_1(clock_4, clock_20);
  div_5 D5_2(clock_20, clock_div);
  
endmodule
module div_100(input clock, output wire clock_div);

  
  wire clock_2, clock_4, clock_20;
  
  div_2 D2_1(clock, clock_2);
  div_2 D2_2(clock_2, clock_4);
  div_5 D5_1(clock_4, clock_20);
  div_5 D5_2(clock_20, clock_div);
  
endmodule