data/full_repos/permissive/527176783/Pipeline/PC_branch.v
data/verilator_xmls/0ca07ea9-222a-40d1-bbbb-95dd719aede2.xml
module PC_branch(
    input   [31:0] immd_pc,
    input   [31:0] pc_add4,
    output  [31:0] pc_branch
);
    assign pc_branch = immd_pc + pc_add4;

endmodule
module PC_branch(
    input   [31:0] immd_pc,
    input   [31:0] pc_add4,
    output  [31:0] pc_branch
);

    assign pc_branch = immd_pc + pc_add4;

endmodule