data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/sim_timeout.sv
data/verilator_xmls/84b1cc65-f277-4ee2-9065-8a603e119cbd.xml
module sim_timeout #(
  parameter longint unsigned  Cycles = 0,
  parameter bit               ResetRestartsTimeout = 1'b0
) (
  input logic clk_i,
  input logic rst_ni
);

  longint unsigned cycles = 0;
  always_ff @(posedge clk_i, negedge rst_ni) begin
    if (ResetRestartsTimeout && !rst_ni) begin
      cycles <= 0;
    end else begin
      cycles <= cycles + 1;
    end
    if (cycles > Cycles) begin
      $fatal(1, "Timeout exceeded!");
    end
  end

  `ifndef VERILATOR
    initial begin: validate_params
      assert (Cycles > 0)
        else $fatal("The number of timeout cycles must be greater than 0!");
      end
  `endif

endmodule
module sim_timeout #(
  parameter longint unsigned  Cycles = 0,
  parameter bit               ResetRestartsTimeout = 1'b0
) (
  input logic clk_i,
  input logic rst_ni
);


  longint unsigned cycles = 0;
  always_ff @(posedge clk_i, negedge rst_ni) begin
    if (ResetRestartsTimeout && !rst_ni) begin
      cycles <= 0;
    end else begin
      cycles <= cycles + 1;
    end
    if (cycles > Cycles) begin
      $fatal(1, "Timeout exceeded!");
    end
  end

  `ifndef VERILATOR
    initial begin: validate_params
      assert (Cycles > 0)
        else $fatal("The number of timeout cycles must be greater than 0!");
      end
  `endif

endmodule