data/full_repos/permissive/515624136/testbench/ENPC_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/515624136/testbench/ENPC_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/515624136/testbench/ENPC_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n  #10;\n  ^\n%Error: data/full_repos/permissive/515624136/testbench/ENPC_tb.v:64: syntax error, unexpected \'@\'\n @(negedge tb_clk_50)\n ^\n%Error: data/full_repos/permissive/515624136/testbench/ENPC_tb.v:68: syntax error, unexpected \'@\'\n @(posedge tb_clk_50)\n ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module ENPC_tb();



reg tb_clk_50;
reg tb_reset;
reg tb_en;

wire Enpc_set_en;



ENPC Enpc(


.ENPC_Clk(tb_clk_50),
.ENPC_En(tb_en),
.ENPC_Reset(tb_reset),

.ENPC_Set_En(Enpc_set_en)

);




always
begin
		tb_clk_50=1'b1;
		#10;
		tb_clk_50=1'b0;
		#10;
end


initial
begin

	tb_reset<=1'b0;
	tb_en<=1'b0;
	@(negedge tb_clk_50)
	@(posedge tb_clk_50)
	tb_reset<=1'b1;
	tb_en<=1'b1;
	@(posedge tb_clk_50)
	@(posedge tb_clk_50)
	@(posedge tb_clk_50)
	@(posedge tb_clk_50)
	@(posedge tb_clk_50)
	@(posedge tb_clk_50)
	@(posedge tb_clk_50)
	@(posedge tb_clk_50)
	
		
	$stop;
	
end

endmodule
module ENPC_tb();




reg tb_clk_50;
reg tb_reset;
reg tb_en;

wire Enpc_set_en;



ENPC Enpc(


.ENPC_Clk(tb_clk_50),
.ENPC_En(tb_en),
.ENPC_Reset(tb_reset),

.ENPC_Set_En(Enpc_set_en)

);




always
begin
		tb_clk_50=1'b1;
		#10;
		tb_clk_50=1'b0;
		#10;
end


initial
begin

	tb_reset<=1'b0;
	tb_en<=1'b0;
	@(negedge tb_clk_50)
	@(posedge tb_clk_50)
	tb_reset<=1'b1;
	tb_en<=1'b1;
	@(posedge tb_clk_50)
	@(posedge tb_clk_50)
	@(posedge tb_clk_50)
	@(posedge tb_clk_50)
	@(posedge tb_clk_50)
	@(posedge tb_clk_50)
	@(posedge tb_clk_50)
	@(posedge tb_clk_50)
	
		
	$stop;
	
end

endmodule