data/full_repos/permissive/484765019/BIST/MISR_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/484765019/BIST/MISR_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n # 10;\n ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/484765019/BIST/MISR_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n # 10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/484765019/BIST/MISR_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n # 10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/484765019/BIST/MISR_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n # 10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/484765019/BIST/MISR_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n # 10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/484765019/BIST/MISR_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n # 10;\n ^\n%Error: data/full_repos/permissive/484765019/BIST/MISR_tb.v:35: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("MISR_tb.vcd"); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/484765019/BIST/MISR_tb.v:36: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/484765019/BIST/MISR_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n #10 clk <= ~clk; \n ^\n%Error: Exiting due to 2 error(s), 7 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module MISR_tb (
	
);

reg [3:0] in_t;
wire [3:0] out_t;
reg clk = 0;
reg n_rst = 0;  
reg done=0;

initial begin
	# 10;
	n_rst = 0;
	in_t = 1011;
	# 10;
	n_rst = 1;
	in_t = 1011; 
	# 10;
	n_rst = 1;
	in_t = 1001;
	# 10;
	n_rst = 1;
	in_t = 0110;
	# 10;
	n_rst = 1;
	in_t = 0110;
	# 10;
	n_rst = 1;
	in_t = 1111;
	done = 1;
end

initial begin 
	$dumpfile("MISR_tb.vcd"); 
	$dumpvars;
end

MISR MISR1(.in(in_t), .clk(clk), .n_rst(n_rst), .out(out_t));

always @(*) begin
	#10 clk <= ~clk; 
end

endmodule
module MISR_tb (
	
);


reg [3:0] in_t;
wire [3:0] out_t;
reg clk = 0;
reg n_rst = 0;  
reg done=0;

initial begin
	# 10;
	n_rst = 0;
	in_t = 1011;
	# 10;
	n_rst = 1;
	in_t = 1011; 
	# 10;
	n_rst = 1;
	in_t = 1001;
	# 10;
	n_rst = 1;
	in_t = 0110;
	# 10;
	n_rst = 1;
	in_t = 0110;
	# 10;
	n_rst = 1;
	in_t = 1111;
	done = 1;
end

initial begin 
	$dumpfile("MISR_tb.vcd"); 
	$dumpvars;
end

MISR MISR1(.in(in_t), .clk(clk), .n_rst(n_rst), .out(out_t));

always @(*) begin
	#10 clk <= ~clk; 
end

endmodule