data/full_repos/permissive/408955603/Sesion2/testPuertasLogicas.v
1: b'%Error: data/full_repos/permissive/408955603/Sesion2/testPuertasLogicas.v:20: Unsupported or unknown PLI call: $monitor\n  $monitor($time, " a=%1b, b=%1b, AND=%1b, OR=%1b, NOT=%1b, NAND=%1b, NOR=%1b, XOR=%1b, XNOR=%1b, BUF=%1b", a, b, salidaAND, salidaOR, salidaNOT, salidaNAND, salidaNOR, salidaXOR, salidaXNOR, salidaBUF);\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion2/testPuertasLogicas.v:28: Unsupported: Ignoring delay on this delayed statement.\n        #5 a = 0; b = 1;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion2/testPuertasLogicas.v:29: Unsupported: Ignoring delay on this delayed statement.\n        #5 a = 1; b = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion2/testPuertasLogicas.v:30: Unsupported: Ignoring delay on this delayed statement.\n        #5 a = 1; b = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion2/testPuertasLogicas.v:32: Unsupported: Ignoring delay on this delayed statement.\n        #5 a = \'bx; b = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion2/testPuertasLogicas.v:33: Unsupported: Ignoring delay on this delayed statement.\n        #5 a = \'bx; b = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion2/testPuertasLogicas.v:34: Unsupported: Ignoring delay on this delayed statement.\n        #5 a = 0; b = \'bx;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion2/testPuertasLogicas.v:35: Unsupported: Ignoring delay on this delayed statement.\n        #5 a = 1; b = \'bx;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion2/testPuertasLogicas.v:37: Unsupported: Ignoring delay on this delayed statement.\n        #5 a = \'bz; b = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion2/testPuertasLogicas.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #5 a = \'bz; b = 1;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion2/testPuertasLogicas.v:39: Unsupported: Ignoring delay on this delayed statement.\n        #5 a = 0; b = \'bz;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion2/testPuertasLogicas.v:40: Unsupported: Ignoring delay on this delayed statement.\n        #5 a = 1; b = \'bz;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion2/testPuertasLogicas.v:42: Unsupported: Ignoring delay on this delayed statement.\n        #5 a = \'bx; b = \'bz;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion2/testPuertasLogicas.v:43: Unsupported: Ignoring delay on this delayed statement.\n        #5 a = \'bx; b = \'bx;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion2/testPuertasLogicas.v:44: Unsupported: Ignoring delay on this delayed statement.\n        #5 a = \'bz; b = \'bx;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/408955603/Sesion2/testPuertasLogicas.v:45: Unsupported: Ignoring delay on this delayed statement.\n        #5 a = \'bz; b = \'bz;\n        ^\n%Error: Exiting due to 1 error(s), 15 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module TestAnd;
	reg a,b;
	wire salidaAND, salidaOR, salidaNOT, salidaNAND, salidaNOR, salidaXOR, salidaXNOR, salidaBUF;
	and a1(salidaAND, a, b);
	or o1(salidaOR, a, b);
	not n1(salidaNOT, a);
	nand na1(salidaNAND, a, b);
	nor nor1(salidaNOR, a, b);
	xor xor1(salidaXOR, a, b);
	xnor xnor1(salidaXNOR, a, b);
	buf buffer1(salidaBUF, a);

	initial
	begin

		$monitor($time, " a=%1b, b=%1b, AND=%1b, OR=%1b, NOT=%1b, NAND=%1b, NOR=%1b, XOR=%1b, XNOR=%1b, BUF=%1b", a, b, salidaAND, salidaOR, salidaNOT, salidaNAND, salidaNOR, salidaXOR, salidaXNOR, salidaBUF);


	       a = 0; b = 0;
	       #5 a = 0; b = 1;
	       #5 a = 1; b = 0;
	       #5 a = 1; b = 1;

	       #5 a = 'bx; b = 0;
	       #5 a = 'bx; b = 1;
	       #5 a = 0; b = 'bx;
	       #5 a = 1; b = 'bx;

	       #5 a = 'bz; b = 0;
	       #5 a = 'bz; b = 1;
	       #5 a = 0; b = 'bz;
	       #5 a = 1; b = 'bz;

	       #5 a = 'bx; b = 'bz;
	       #5 a = 'bx; b = 'bx;
	       #5 a = 'bz; b = 'bx;
	       #5 a = 'bz; b = 'bz;
	end
endmodule
module TestAnd;

	reg a,b;
	wire salidaAND, salidaOR, salidaNOT, salidaNAND, salidaNOR, salidaXOR, salidaXNOR, salidaBUF;
	and a1(salidaAND, a, b);
	or o1(salidaOR, a, b);
	not n1(salidaNOT, a);
	nand na1(salidaNAND, a, b);
	nor nor1(salidaNOR, a, b);
	xor xor1(salidaXOR, a, b);
	xnor xnor1(salidaXNOR, a, b);
	buf buffer1(salidaBUF, a);

	initial
	begin

		$monitor($time, " a=%1b, b=%1b, AND=%1b, OR=%1b, NOT=%1b, NAND=%1b, NOR=%1b, XOR=%1b, XNOR=%1b, BUF=%1b", a, b, salidaAND, salidaOR, salidaNOT, salidaNAND, salidaNOR, salidaXOR, salidaXNOR, salidaBUF);


	       a = 0; b = 0;
	       #5 a = 0; b = 1;
	       #5 a = 1; b = 0;
	       #5 a = 1; b = 1;

	       #5 a = 'bx; b = 0;
	       #5 a = 'bx; b = 1;
	       #5 a = 0; b = 'bx;
	       #5 a = 1; b = 'bx;

	       #5 a = 'bz; b = 0;
	       #5 a = 'bz; b = 1;
	       #5 a = 0; b = 'bz;
	       #5 a = 1; b = 'bz;

	       #5 a = 'bx; b = 'bz;
	       #5 a = 'bx; b = 'bx;
	       #5 a = 'bz; b = 'bx;
	       #5 a = 'bz; b = 'bz;
	end
endmodule