data/full_repos/permissive/48602886/src/device/vga/vga_command_controller.sv
1: b'%Warning-WIDTH: data/full_repos/permissive/48602886/src/device/vga/vga_command_controller.sv:105: Operator ASSIGNDLY expects 19 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 bits.\n                                                                                                : ... In instance vga_command_controller\n         vram_addr <= iBUSMOD_ADDR - 32\'h00000100;\n                   ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module vga_command_controller(
		input wire iCLOCK,
		input wire inRESET,
		input wire iRESET_SYNC,

		input wire iBUSMOD_REQ,
		input wire [31:0] iBUSMOD_ADDR,
		input wire [31:0] iBUSMOD_DATA,
		output wire oBUSMOD_WAIT,

		input wire iVRAM_WAIT,
		output wire oVRAM_WRITE_REQ,
		output wire [18:0] oVRAM_WRITE_ADDR,
		output wire [15:0] oVRAM_WRITE_DATA
	);
	
	localparam PL_STT_IDLE = 2'h0;
	localparam PL_STT_CLEAR = 2'h1;
	localparam PL_STT_BITMAP = 2'h2;


	wire state_lock = iVRAM_WAIT;
										

	reg [1:0] main_state;
	reg [6:0] sub_state;
	reg [13:0] req_addr;
	reg [15:0] req_data;
	reg [18:0] vram_addr;

	wire [111:0] font_rom_data;
	

	always@(posedge iCLOCK or negedge inRESET)begin
		if(!inRESET)begin
			main_state <= PL_STT_IDLE;
		end
		else if(iRESET_SYNC)begin
			main_state <= PL_STT_IDLE;
		end
		else begin
			if(!state_lock)begin
				case(main_state)
					PL_STT_IDLE :
						begin
							if(iBUSMOD_REQ)begin
								if(iBUSMOD_ADDR == 32'h00000000)begin
									main_state <= PL_STT_CLEAR;
								end
								else if(iBUSMOD_ADDR >= 32'h00000100 && iBUSMOD_ADDR < 19'h4B0ff)begin
									main_state <= PL_STT_BITMAP;
								end
							end
						end
					PL_STT_CLEAR :
						begin
							if(!(vram_addr < 19'h4B000))begin
								main_state <= PL_STT_IDLE;
							end
						end
					PL_STT_BITMAP :
						begin
							main_state <= PL_STT_IDLE;
						end
				endcase	
			end
		end
	end
	
	
	always@(posedge iCLOCK or negedge inRESET)begin
		if(!inRESET)begin
			sub_state <= {7{1'b0}};
			req_addr <= {14{1'b0}};
			req_data <= {16{1'b0}};
			vram_addr <= {19{1'b0}};
		end
		else if(iRESET_SYNC)begin
			sub_state <= {7{1'b0}};
			req_addr <= {14{1'b0}};
			req_data <= {16{1'b0}};
			vram_addr <= {19{1'b0}};
		end
		else begin
			if(!state_lock)begin
				case(main_state)
					PL_STT_IDLE :
						begin
							if(iBUSMOD_REQ)begin
								if(iBUSMOD_ADDR == 32'h00000000)begin
									req_data <= iBUSMOD_DATA[15:0];
									vram_addr <= {19{1'b0}};
								end
								else if(iBUSMOD_ADDR >= 32'h00000100 && iBUSMOD_ADDR < 19'h4b0ff)begin
									req_data <= iBUSMOD_DATA[15:0];
									vram_addr <= iBUSMOD_ADDR - 32'h00000100;
								end
							end
							sub_state <= {7{1'b0}};
						end
					PL_STT_CLEAR :
						begin
							if(vram_addr < 19'h4B000)begin
								vram_addr <= vram_addr + 19'h00001;
							end 
						end
				endcase	
			end
		end
	end

	

	assign oBUSMOD_WAIT = state_lock || (main_state != PL_STT_IDLE);
	assign oVRAM_WRITE_REQ = !state_lock && (main_state != PL_STT_IDLE);
	assign oVRAM_WRITE_ADDR = vram_addr;
	assign oVRAM_WRITE_DATA = req_data;
	
endmodule
module vga_command_controller(
		input wire iCLOCK,
		input wire inRESET,
		input wire iRESET_SYNC,

		input wire iBUSMOD_REQ,
		input wire [31:0] iBUSMOD_ADDR,
		input wire [31:0] iBUSMOD_DATA,
		output wire oBUSMOD_WAIT,

		input wire iVRAM_WAIT,
		output wire oVRAM_WRITE_REQ,
		output wire [18:0] oVRAM_WRITE_ADDR,
		output wire [15:0] oVRAM_WRITE_DATA
	);

	
	localparam PL_STT_IDLE = 2'h0;
	localparam PL_STT_CLEAR = 2'h1;
	localparam PL_STT_BITMAP = 2'h2;


	wire state_lock = iVRAM_WAIT;
										

	reg [1:0] main_state;
	reg [6:0] sub_state;
	reg [13:0] req_addr;
	reg [15:0] req_data;
	reg [18:0] vram_addr;

	wire [111:0] font_rom_data;
	

	always@(posedge iCLOCK or negedge inRESET)begin
		if(!inRESET)begin
			main_state <= PL_STT_IDLE;
		end
		else if(iRESET_SYNC)begin
			main_state <= PL_STT_IDLE;
		end
		else begin
			if(!state_lock)begin
				case(main_state)
					PL_STT_IDLE :
						begin
							if(iBUSMOD_REQ)begin
								if(iBUSMOD_ADDR == 32'h00000000)begin
									main_state <= PL_STT_CLEAR;
								end
								else if(iBUSMOD_ADDR >= 32'h00000100 && iBUSMOD_ADDR < 19'h4B0ff)begin
									main_state <= PL_STT_BITMAP;
								end
							end
						end
					PL_STT_CLEAR :
						begin
							if(!(vram_addr < 19'h4B000))begin
								main_state <= PL_STT_IDLE;
							end
						end
					PL_STT_BITMAP :
						begin
							main_state <= PL_STT_IDLE;
						end
				endcase	
			end
		end
	end
	
	
	always@(posedge iCLOCK or negedge inRESET)begin
		if(!inRESET)begin
			sub_state <= {7{1'b0}};
			req_addr <= {14{1'b0}};
			req_data <= {16{1'b0}};
			vram_addr <= {19{1'b0}};
		end
		else if(iRESET_SYNC)begin
			sub_state <= {7{1'b0}};
			req_addr <= {14{1'b0}};
			req_data <= {16{1'b0}};
			vram_addr <= {19{1'b0}};
		end
		else begin
			if(!state_lock)begin
				case(main_state)
					PL_STT_IDLE :
						begin
							if(iBUSMOD_REQ)begin
								if(iBUSMOD_ADDR == 32'h00000000)begin
									req_data <= iBUSMOD_DATA[15:0];
									vram_addr <= {19{1'b0}};
								end
								else if(iBUSMOD_ADDR >= 32'h00000100 && iBUSMOD_ADDR < 19'h4b0ff)begin
									req_data <= iBUSMOD_DATA[15:0];
									vram_addr <= iBUSMOD_ADDR - 32'h00000100;
								end
							end
							sub_state <= {7{1'b0}};
						end
					PL_STT_CLEAR :
						begin
							if(vram_addr < 19'h4B000)begin
								vram_addr <= vram_addr + 19'h00001;
							end 
						end
				endcase	
			end
		end
	end

	

	assign oBUSMOD_WAIT = state_lock || (main_state != PL_STT_IDLE);
	assign oVRAM_WRITE_REQ = !state_lock && (main_state != PL_STT_IDLE);
	assign oVRAM_WRITE_ADDR = vram_addr;
	assign oVRAM_WRITE_DATA = req_data;
	
endmodule