data/full_repos/permissive/447223480/03_branch/runner.v
1: b'%Error: data/full_repos/permissive/447223480/03_branch/runner.v:10: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("result.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/447223480/03_branch/runner.v:11: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, runner);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/447223480/03_branch/runner.v:16: Unsupported: Ignoring delay on this delayed statement.\n  #100\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/447223480/03_branch/runner.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #3000\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/447223480/03_branch/runner.v:22: Unsupported: Ignoring delay on this delayed statement.\n always #50 begin\n        ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module runner();
	reg clock;
	reg reset;

	cpu CPU(.clock(clock), .reset(reset));

	initial begin
		$dumpfile("result.vcd");
		$dumpvars(0, runner);
		$readmemb("prog.txt", CPU.pmem.mem);

		clock <= 1'b0;
		reset <= 1'b1;
		#100
		reset <= 1'b0;
		#3000
		$finish;
	end

	always #50 begin
		clock <= ~clock;
	end

endmodule
module runner();

	reg clock;
	reg reset;

	cpu CPU(.clock(clock), .reset(reset));

	initial begin
		$dumpfile("result.vcd");
		$dumpvars(0, runner);
		$readmemb("prog.txt", CPU.pmem.mem);

		clock <= 1'b0;
		reset <= 1'b1;
		#100
		reset <= 1'b0;
		#3000
		$finish;
	end

	always #50 begin
		clock <= ~clock;
	end

endmodule