data/full_repos/permissive/521337848/Hardware/SPISD/prepare.v
1: b'%Error: data/full_repos/permissive/521337848/Hardware/SPISD/prepare.v:70: syntax error, unexpected bit, expecting IDENTIFIER\nbufferin100k bit(\n             ^~~\n%Error: Exiting due to 1 error(s)\n'
module bufferin100k(
	input dclk,
	input clk,
	input rst,
	
	input start,
	input start40,
	input[5:0] cmd,
	input[31:0] arg,
	input readit,
	
	output reg n_start,
	output reg n_start40,
	output reg[5:0] n_cmd,
	output reg[31:0] n_arg,
	output reg n_readit
);


always@(*)begin
	begin
		n_start <= start;
		n_start40 <= start40;
		n_cmd <= cmd;
		n_arg <= arg;
		n_readit <= readit;
	end	
end


endmodule
module bufferin100k(
	input dclk,
	input clk,
	input rst,
	
	input start,
	input start40,
	input[5:0] cmd,
	input[31:0] arg,
	input readit,
	
	output reg n_start,
	output reg n_start40,
	output reg[5:0] n_cmd,
	output reg[31:0] n_arg,
	output reg n_readit
);



always@(*)begin
	begin
		n_start <= start;
		n_start40 <= start40;
		n_cmd <= cmd;
		n_arg <= arg;
		n_readit <= readit;
	end	
end


endmodule