data/full_repos/permissive/496508301/Lesson6/sigma_16p.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson6/sigma_16p.v:75: Unsupported: Ignoring delay on this delayed statement.\n    #17     res <= 1;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson6/sigma_16p.v:76: Unsupported: Ignoring delay on this delayed statement.\n    #25000  $stop;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson6/sigma_16p.v:78: Unsupported: Ignoring delay on this delayed statement.\nalways #5   clk <= ~clk;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/496508301/Lesson6/sigma_16p.v:79: Unsupported: Ignoring delay on this delayed statement.\nalways #100 syn_in <= ~syn_in;   \n       ^\n%Error: data/full_repos/permissive/496508301/Lesson6/sigma_16p.v:82: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("sigma_16p_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/496508301/Lesson6/sigma_16p.v:83: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars;\n    ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sigma_16p(
    clk,
    res,
    data_in,
    syn_in,
    data_out,
    syn_out
);
input           clk;
input           res;
input[7:0]      data_in;
input           syn_in;
output[11:0]    data_out;
output          syn_out;

reg             syn_in_n1;
wire            syn_pulse;
assign          syn_pulse = syn_in_n1 & syn_in;
reg[3:0]        con_syn;

wire[7:0]       comp_8;
wire[11:0]      d_12;
wire[6:0]       tmp;
assign          tmp = ~data_in[6:0]+1;
assign          comp_8 = data_in[7]?{data_in[7],tmp}:data_in;
assign          d_12 = {comp_8[7], comp_8[7], comp_8[7], comp_8[7], comp_8};
reg[11:0]       sigma;
reg[11:0]       data_out;
reg             syn_out;
always @(posedge clk or negedge res) begin
    if (~res)begin
        syn_in_n1 <= 0; con_syn <= 0; sigma <= 0; data_out <= 0; syn_out <= 0;
    end
    else begin
        syn_in_n1 <= ~syn_in;
        if (syn_pulse)begin
            con_syn <= con_syn+1;
        end
        if (syn_pulse)begin
            if (con_syn==15)begin
                sigma <= d_12;
                data_out <= sigma;
                syn_out <= 1;
            end
            else begin
                sigma <= sigma+d_12;
            end
        end
        else begin
            syn_out <= 0;
        end
    end
end
endmodule
module sigma_16p(
    clk,
    res,
    data_in,
    syn_in,
    data_out,
    syn_out
);

input           clk;
input           res;
input[7:0]      data_in;
input           syn_in;
output[11:0]    data_out;
output          syn_out;

reg             syn_in_n1;
wire            syn_pulse;
assign          syn_pulse = syn_in_n1 & syn_in;
reg[3:0]        con_syn;

wire[7:0]       comp_8;
wire[11:0]      d_12;
wire[6:0]       tmp;
assign          tmp = ~data_in[6:0]+1;
assign          comp_8 = data_in[7]?{data_in[7],tmp}:data_in;
assign          d_12 = {comp_8[7], comp_8[7], comp_8[7], comp_8[7], comp_8};
reg[11:0]       sigma;
reg[11:0]       data_out;
reg             syn_out;
always @(posedge clk or negedge res) begin
    if (~res)begin
        syn_in_n1 <= 0; con_syn <= 0; sigma <= 0; data_out <= 0; syn_out <= 0;
    end
    else begin
        syn_in_n1 <= ~syn_in;
        if (syn_pulse)begin
            con_syn <= con_syn+1;
        end
        if (syn_pulse)begin
            if (con_syn==15)begin
                sigma <= d_12;
                data_out <= sigma;
                syn_out <= 1;
            end
            else begin
                sigma <= sigma+d_12;
            end
        end
        else begin
            syn_out <= 0;
        end
    end
end
endmodule