data/full_repos/permissive/481307378/source_files/TrafficLight/timer_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/481307378/source_files/TrafficLight/timer_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n    always #250 CLK = !CLK;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/481307378/source_files/TrafficLight/timer_tb.v:27: syntax error, unexpected \'@\'\n        @(negedge CLK);  \n        ^\n%Error: data/full_repos/permissive/481307378/source_files/TrafficLight/timer_tb.v:30: syntax error, unexpected \'@\'\n        @(posedge TICK);  \n        ^\n%Error: Exiting due to 2 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module timer_tb();

    reg RES, CLK;
    wire TICK;
    

    timer dut(.RES(RES), .CLK(CLK), .TICK(TICK));
    

    defparam dut.CLOCK_SIGNALS = 32'd10;
    

    initial 
    begin
        RES = 1'b1;
        CLK = 1'b0;
    end
    

    always #250 CLK = !CLK;
    

    initial
    begin  
        @(negedge CLK);
        RES = 1'b0;
        
        @(posedge TICK);
        $finish;
    end
      

endmodule
module timer_tb();


    reg RES, CLK;
    wire TICK;
    

    timer dut(.RES(RES), .CLK(CLK), .TICK(TICK));
    

    defparam dut.CLOCK_SIGNALS = 32'd10;
    

    initial 
    begin
        RES = 1'b1;
        CLK = 1'b0;
    end
    

    always #250 CLK = !CLK;
    

    initial
    begin  
        @(negedge CLK);
        RES = 1'b0;
        
        @(posedge TICK);
        $finish;
    end
      

endmodule