data/full_repos/permissive/503973366/NOT_USE/NOT_USE_HW/Adder/Backup/CLALogic.v
data/verilator_xmls/2200d3f1-43ba-4564-86e6-0d481df68f69.xml
module CLALogic (
    input [3 : 0] G, P,
    input Ci,

    output [3 : 1] C,
    output Co,
    output PG,
    output GG
);
    wire GG_int;
    wire PG_int;

    assign C[1] = G[0] | (P[0] & Ci);
    assign C[2] = G[1] | (P[1] & G[0]) | (P[1] & P[0] & Ci);
    assign C[3] = G[2] | (P[2] & G[1]) | (P[2] & P[1] & G[0]) | (P[2] & P[1] & P[0] & Ci);

    assign PG_int = P[3] & P[2] & P[1] & P[0];
    assign GG_int = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]);
    
    assign Co = GG_int | (PG_int & Ci);
    assign PG = PG_int;
    assign GG = GG_int;
endmodule
module CLALogic (
    input [3 : 0] G, P,
    input Ci,

    output [3 : 1] C,
    output Co,
    output PG,
    output GG
);

    wire GG_int;
    wire PG_int;

    assign C[1] = G[0] | (P[0] & Ci);
    assign C[2] = G[1] | (P[1] & G[0]) | (P[1] & P[0] & Ci);
    assign C[3] = G[2] | (P[2] & G[1]) | (P[2] & P[1] & G[0]) | (P[2] & P[1] & P[0] & Ci);

    assign PG_int = P[3] & P[2] & P[1] & P[0];
    assign GG_int = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]);
    
    assign Co = GG_int | (PG_int & Ci);
    assign PG = PG_int;
    assign GG = GG_int;
endmodule