data/full_repos/permissive/445357518/datapath.v
1: b"%Error: data/full_repos/permissive/445357518/datapath.v:17: Cannot find file containing module: 'regfile'\n  regfile REGFILE(data_in, writenum, write, readnum, clk, data_out);\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/regfile\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/regfile.v\n             data/full_repos/permissive/445357518,data/full_repos/permissive/445357518/regfile.sv\n             regfile\n             regfile.v\n             regfile.sv\n             obj_dir/regfile\n             obj_dir/regfile.v\n             obj_dir/regfile.sv\n%Error: data/full_repos/permissive/445357518/datapath.v:20: Cannot find file containing module: 'vDFF1'\n  vDFF1 #(16)loadA(clk, data_out, loada, aout);\n  ^~~~~\n%Error: data/full_repos/permissive/445357518/datapath.v:22: Cannot find file containing module: 'vDFF1'\n  vDFF1 #(16)loadB(clk, data_out, loadb, in);\n  ^~~~~\n%Error: data/full_repos/permissive/445357518/datapath.v:25: Cannot find file containing module: 'shifter'\n  shifter SHIFTER(in, shift, sout);\n  ^~~~~~~\n%Error: data/full_repos/permissive/445357518/datapath.v:32: Cannot find file containing module: 'ALU'\n  ALU U2(Ain,Bin,ALUop,out,N,V,Z);\n  ^~~\n%Error: data/full_repos/permissive/445357518/datapath.v:34: Cannot find file containing module: 'vDFF1'\n  vDFF1 #(16) C(clk,out,loadc,datapath_out);\n  ^~~~~\n%Error: data/full_repos/permissive/445357518/datapath.v:36: Cannot find file containing module: 'vDFF1'\n  vDFF1 #(1) statusN(clk,N,loads,N_out);\n  ^~~~~\n%Error: data/full_repos/permissive/445357518/datapath.v:38: Cannot find file containing module: 'vDFF1'\n  vDFF1 #(1) statusV(clk,V,loads,V_out);\n  ^~~~~\n%Error: data/full_repos/permissive/445357518/datapath.v:40: Cannot find file containing module: 'vDFF1'\n  vDFF1 #(1) statusZ(clk,Z,loads,Z_out);\n  ^~~~~\n%Error: Exiting due to 9 error(s)\n"
module datapath(clk,readnum,write,writenum, sximm8, sximm5, mdata, PC ,datapath_out,loada,loadb,shift,asel,bsel,ALUop,loadc,loads,vsel,Z_out,V_out,N_out);
  input clk,write, loada, loadb, asel, bsel, loadc, loads;
  input [1:0] vsel;
  input [15:0] sximm8, mdata, PC, sximm5;
  input [2:0] readnum, writenum;
  input [1:0] shift, ALUop;
  output Z_out,V_out,N_out;
  output [15:0] datapath_out;
  wire[15:0] data_in, data_out,in,sout,Ain,Bin,out,aout;
  wire N,V,Z;



  writeBackMux wbm(mdata, sximm8, PC, datapath_out, data_in, vsel); 
  

  regfile REGFILE(data_in, writenum, write, readnum, clk, data_out);


  vDFF1 #(16)loadA(clk, data_out, loada, aout);

  vDFF1 #(16)loadB(clk, data_out, loadb, in);


  shifter SHIFTER(in, shift, sout);

  assign Ain= asel ? 16'b0000000000000000: aout;

  assign Bin= bsel ? sximm5 : sout;
  

  ALU U2(Ain,Bin,ALUop,out,N,V,Z);

  vDFF1 #(16) C(clk,out,loadc,datapath_out);

  vDFF1 #(1) statusN(clk,N,loads,N_out);

  vDFF1 #(1) statusV(clk,V,loads,V_out);

  vDFF1 #(1) statusZ(clk,Z,loads,Z_out);

endmodule
module datapath(clk,readnum,write,writenum, sximm8, sximm5, mdata, PC ,datapath_out,loada,loadb,shift,asel,bsel,ALUop,loadc,loads,vsel,Z_out,V_out,N_out);

  input clk,write, loada, loadb, asel, bsel, loadc, loads;
  input [1:0] vsel;
  input [15:0] sximm8, mdata, PC, sximm5;
  input [2:0] readnum, writenum;
  input [1:0] shift, ALUop;
  output Z_out,V_out,N_out;
  output [15:0] datapath_out;
  wire[15:0] data_in, data_out,in,sout,Ain,Bin,out,aout;
  wire N,V,Z;



  writeBackMux wbm(mdata, sximm8, PC, datapath_out, data_in, vsel); 
  

  regfile REGFILE(data_in, writenum, write, readnum, clk, data_out);


  vDFF1 #(16)loadA(clk, data_out, loada, aout);

  vDFF1 #(16)loadB(clk, data_out, loadb, in);


  shifter SHIFTER(in, shift, sout);

  assign Ain= asel ? 16'b0000000000000000: aout;

  assign Bin= bsel ? sximm5 : sout;
  

  ALU U2(Ain,Bin,ALUop,out,N,V,Z);

  vDFF1 #(16) C(clk,out,loadc,datapath_out);

  vDFF1 #(1) statusN(clk,N,loads,N_out);

  vDFF1 #(1) statusV(clk,V,loads,V_out);

  vDFF1 #(1) statusZ(clk,Z,loads,Z_out);

endmodule