data/full_repos/permissive/459277146/divider.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/459277146/divider.v:90: Unsupported: Ignoring delay on this delayed statement.\n    always #(CLK_PERIOD / 2) clk = ~clk;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/459277146/divider.v:93: Unsupported or unknown PLI call: $monitor\n        $monitor("\\t%d:\\t%d /%d =%d (r =) (V=) (DBZ=)",\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/459277146/divider.v:100: Unsupported: Ignoring delay on this delayed statement.\n        #100    x = 4\'b0000;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/divider.v:103: Unsupported: Ignoring delay on this delayed statement.\n        #10     start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/divider.v:105: Unsupported: Ignoring delay on this delayed statement.\n        #50     x = 4\'b0010;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/divider.v:108: Unsupported: Ignoring delay on this delayed statement.\n        #10     start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/divider.v:110: Unsupported: Ignoring delay on this delayed statement.\n        #50     x = 4\'b0111;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/divider.v:113: Unsupported: Ignoring delay on this delayed statement.\n        #10     start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/divider.v:115: Unsupported: Ignoring delay on this delayed statement.\n        #50     x = 4\'b1111;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/divider.v:118: Unsupported: Ignoring delay on this delayed statement.\n        #10     start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/divider.v:120: Unsupported: Ignoring delay on this delayed statement.\n        #50     x = 4\'b0001;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/divider.v:123: Unsupported: Ignoring delay on this delayed statement.\n        #10     start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/divider.v:125: Unsupported: Ignoring delay on this delayed statement.\n        #50     x = 4\'b1000;   \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/divider.v:128: Unsupported: Ignoring delay on this delayed statement.\n        #10     start = 0;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/459277146/divider.v:132: Unsupported: Ignoring delay on this delayed statement.\n        #50     $finish;\n        ^\n%Error: data/full_repos/permissive/459277146/divider.v:135: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("div.vcd"); \n  ^~~~~~~~~\n%Error: data/full_repos/permissive/459277146/divider.v:136: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars; \n  ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 14 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module divider_tb();

    parameter CLK_PERIOD = 10;
    parameter DWIDTH = 8;

    logic clk;
    logic start;



    logic [DWIDTH-1:0] x;
    logic [DWIDTH-1:0] y;
    logic [(DWIDTH<<1)-1:0] dout;


    divider #(.DWIDTH(DWIDTH)) divider_inst (.*);

    always #(CLK_PERIOD / 2) clk = ~clk;

    initial begin
        $monitor("\t%d:\t%d /%d =%d (r =) (V=) (DBZ=)",
            $time, x, y, dout);
    end

    initial begin
        clk = 1;

        #100    x = 4'b0000;
                y = 4'b0010;
                start = 1;
        #10     start = 0;

        #50     x = 4'b0010;
                y = 4'b0000;
                start = 1;
        #10     start = 0;

        #50     x = 4'b0111;
                y = 4'b0010;
                start = 1;
        #10     start = 0;

        #50     x = 4'b1111;
                y = 4'b0101;
                start = 1;
        #10     start = 0;

        #50     x = 4'b0001;
                y = 4'b0001;
                start = 1;
        #10     start = 0;

        #50     x = 4'b1000;
                y = 4'b1001;
                start = 1;
        #10     start = 0;



        #50     $finish;
    end
   initial begin
  $dumpfile("div.vcd"); 
  $dumpvars; 
 end
endmodule
module divider_tb();


    parameter CLK_PERIOD = 10;
    parameter DWIDTH = 8;

    logic clk;
    logic start;



    logic [DWIDTH-1:0] x;
    logic [DWIDTH-1:0] y;
    logic [(DWIDTH<<1)-1:0] dout;


    divider #(.DWIDTH(DWIDTH)) divider_inst (.*);

    always #(CLK_PERIOD / 2) clk = ~clk;

    initial begin
        $monitor("\t%d:\t%d /%d =%d (r =) (V=) (DBZ=)",
            $time, x, y, dout);
    end

    initial begin
        clk = 1;

        #100    x = 4'b0000;
                y = 4'b0010;
                start = 1;
        #10     start = 0;

        #50     x = 4'b0010;
                y = 4'b0000;
                start = 1;
        #10     start = 0;

        #50     x = 4'b0111;
                y = 4'b0010;
                start = 1;
        #10     start = 0;

        #50     x = 4'b1111;
                y = 4'b0101;
                start = 1;
        #10     start = 0;

        #50     x = 4'b0001;
                y = 4'b0001;
                start = 1;
        #10     start = 0;

        #50     x = 4'b1000;
                y = 4'b1001;
                start = 1;
        #10     start = 0;



        #50     $finish;
    end
   initial begin
  $dumpfile("div.vcd"); 
  $dumpvars; 
 end
endmodule