data/full_repos/permissive/466186152/akhil_full_adder/akhil_full_adder.v
data/verilator_xmls/ab0569b8-ecd0-4653-8639-93b24d12ff77.xml
module akhil_full_adder(s,c_out,a,b,c_in);
input a,b,c_in;
output reg s,c_out;


always@(a or b or c_in)
begin

  {c_out, s} = a + b + c_in; 

end
endmodule
module akhil_full_adder(s,c_out,a,b,c_in);

input a,b,c_in;
output reg s,c_out;


always@(a or b or c_in)
begin

  {c_out, s} = a + b + c_in; 

end
endmodule