data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_tlu_penc64.v
data/verilator_xmls/cc50182b-4626-404f-8793-e79c707ba223.xml
module sparc_tlu_penc64 (

   out, 

   in
   );

   input [63:0] in;

   output [5:0] out;


   reg [5:0] 	out;
   integer 	i;
   
always @ (in)
begin



	out = 6'b0;

	for (i=0;i<64;i=i+1)
	    begin
	       if (in[i])
		   out[5:0] = i[5:0];
	    end
end
   
endmodule
module sparc_tlu_penc64 (

   out, 

   in
   );


   input [63:0] in;

   output [5:0] out;


   reg [5:0] 	out;
   integer 	i;
   
always @ (in)
begin



	out = 6'b0;

	for (i=0;i<64;i=i+1)
	    begin
	       if (in[i])
		   out[5:0] = i[5:0];
	    end
end
   
endmodule