data/full_repos/permissive/467899092/four_bit_subtractor_tb.v
1: b'%Error: data/full_repos/permissive/467899092/four_bit_subtractor_tb.v:11: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("test.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/467899092/four_bit_subtractor_tb.v:12: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(1, four_bit_subtractor_tb);\n  ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/467899092/four_bit_subtractor_tb.v:15: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/467899092/four_bit_subtractor_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/467899092/four_bit_subtractor_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/467899092/four_bit_subtractor_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/467899092/four_bit_subtractor_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/467899092/four_bit_subtractor_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/467899092/four_bit_subtractor_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/467899092/four_bit_subtractor_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/467899092/four_bit_subtractor_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n  #10\n  ^\n%Error: Exiting due to 2 error(s), 9 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module four_bit_subtractor_tb();
	reg [3:0] a;
	reg [3:0] b;
	wire [4:0] c;

	four_bit_subtractor fbs(c, a, b);		

	initial begin
		$dumpfile("test.vcd");
		$dumpvars(1, four_bit_subtractor_tb);
		a = 4'b0001;
		b = 4'b0000;
		#10
		a = 4'b0011;
		b = 4'b0001;
		#10
		a = 4'b0011;
		b = 4'b0011;
		#10
		a = 4'b0111;
		b = 4'b0011;
		#10
		a = 4'b0111;
		b = 4'b0111;
		#10
		a = 4'b1111;
		b = 4'b0111;
		#10
		a = 4'b1111;
		b = 4'b1111;
		#10
		a = 4'b1111;
		b = 4'b1111;
		#10
		a = 4'b0000;
		b = 4'b0001;
		#10
		$finish;
	end
endmodule
module four_bit_subtractor_tb();

	reg [3:0] a;
	reg [3:0] b;
	wire [4:0] c;

	four_bit_subtractor fbs(c, a, b);		

	initial begin
		$dumpfile("test.vcd");
		$dumpvars(1, four_bit_subtractor_tb);
		a = 4'b0001;
		b = 4'b0000;
		#10
		a = 4'b0011;
		b = 4'b0001;
		#10
		a = 4'b0011;
		b = 4'b0011;
		#10
		a = 4'b0111;
		b = 4'b0011;
		#10
		a = 4'b0111;
		b = 4'b0111;
		#10
		a = 4'b1111;
		b = 4'b0111;
		#10
		a = 4'b1111;
		b = 4'b1111;
		#10
		a = 4'b1111;
		b = 4'b1111;
		#10
		a = 4'b0000;
		b = 4'b0001;
		#10
		$finish;
	end
endmodule