data/full_repos/permissive/472586361/machine/CPU.v
1: b'%Error: data/full_repos/permissive/472586361/machine/CPU.v:2: Cannot find include file: ALU.v\n`include "ALU.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/472586361/machine,data/full_repos/permissive/472586361/ALU.v\n             data/full_repos/permissive/472586361/machine,data/full_repos/permissive/472586361/ALU.v.v\n             data/full_repos/permissive/472586361/machine,data/full_repos/permissive/472586361/ALU.v.sv\n             ALU.v\n             ALU.v.v\n             ALU.v.sv\n             obj_dir/ALU.v\n             obj_dir/ALU.v.v\n             obj_dir/ALU.v.sv\n%Error: data/full_repos/permissive/472586361/machine/CPU.v:3: Cannot find include file: PC.v\n`include "PC.v" \n         ^~~~~~\n%Error: data/full_repos/permissive/472586361/machine/CPU.v:4: Cannot find include file: control.v\n`include "control.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/472586361/machine/CPU.v:5: Cannot find include file: register-8.v\n`include "register-8.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472586361/machine/CPU.v:6: Cannot find include file: register-4.v\n`include "register-4.v" \n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/472586361/machine/CPU.v:7: Cannot find include file: block8.v\n`include "block8.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/472586361/machine/CPU.v:8: Cannot find include file: block4.v\n`include "block4.v" \n         ^~~~~~~~~~\n%Error: data/full_repos/permissive/472586361/machine/CPU.v:9: Cannot find include file: RAM.v\n`include "RAM.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/472586361/machine/CPU.v:10: Cannot find include file: bcd2disp.v\n`include "bcd2disp.v" \n         ^~~~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n'
module CPU(input clkin,output [7:0] LED,output HLT);
wire [7:0] bus;
wire [3:0] MemAddr;
wire [7:0] Aout;
wire [7:0] Bout;
wire [7:0] Instout;
wire [3:0] Pcount;
wire [3:0] Addr_in;
wire [7:0] Dispout;
wire [7:0] aluOut;
wire AI,AO,BI,MI,RR,RW,II,IO,CI,CO,CE,ALUOPTION,ALUO,DI,FL;
wire PCrst, flag;
wire clk;
wire [7:0] OutPut;

assign clk = (clkin & ~HLT);


    register8 A(.clk(clk), .data_in(bus),  .EI(AI),.data_out(Aout));
    block8 triA(.data(Aout), .dataOut(bus), .enable(AO));

    register8 B(.clk(clk), .data_in(bus),.EI(BI), .data_out(Bout) );

    register8 InstReg(.clk(clk), .data_in(bus),  .EI(II),.data_out(Instout));
    block4 triInstReg(.data(Instout[3:0]), .dataOut(bus[3:0]), .enable(IO));

    ALU alu(.A(Aout), .B(Bout), .op(ALUOPTION),.FLAGENABLE(FL), .res({flag,aluOut}));
    block8 tri_alu(.data(aluOut), .enable(ALUO), .dataOut(bus));


    PC pc(.clk(clk), .rst(1'b0), .enable(CE), .jmp(CI), .jmploc(bus[3:0]), .count(Pcount));
    block4 tripc(.data(Pcount), .dataOut(bus[3:0]), .enable(CO));


    register4 MemAdd(.clk(clk), .data_in(bus[3:0]),  .EI(MI),.data_out(Addr_in));

    RAM ram(.clk(~clk), .address(Addr_in), .write_enable(RW), .read_enable(RR), .data(bus));


    control ic(.CLK(clk),.command(Instout[7:4]), .ctrl_wrd({HLT,AI,AO,BI,MI,RR,RW,II,IO,CI,CO,CE,ALUOPTION,ALUO,DI,FL}));


    register8 O(.clk(clk), .data_in(bus), .EI(DI), .data_out(LED));





endmodule
module CPU(input clkin,output [7:0] LED,output HLT);

wire [7:0] bus;
wire [3:0] MemAddr;
wire [7:0] Aout;
wire [7:0] Bout;
wire [7:0] Instout;
wire [3:0] Pcount;
wire [3:0] Addr_in;
wire [7:0] Dispout;
wire [7:0] aluOut;
wire AI,AO,BI,MI,RR,RW,II,IO,CI,CO,CE,ALUOPTION,ALUO,DI,FL;
wire PCrst, flag;
wire clk;
wire [7:0] OutPut;

assign clk = (clkin & ~HLT);


    register8 A(.clk(clk), .data_in(bus),  .EI(AI),.data_out(Aout));
    block8 triA(.data(Aout), .dataOut(bus), .enable(AO));

    register8 B(.clk(clk), .data_in(bus),.EI(BI), .data_out(Bout) );

    register8 InstReg(.clk(clk), .data_in(bus),  .EI(II),.data_out(Instout));
    block4 triInstReg(.data(Instout[3:0]), .dataOut(bus[3:0]), .enable(IO));

    ALU alu(.A(Aout), .B(Bout), .op(ALUOPTION),.FLAGENABLE(FL), .res({flag,aluOut}));
    block8 tri_alu(.data(aluOut), .enable(ALUO), .dataOut(bus));


    PC pc(.clk(clk), .rst(1'b0), .enable(CE), .jmp(CI), .jmploc(bus[3:0]), .count(Pcount));
    block4 tripc(.data(Pcount), .dataOut(bus[3:0]), .enable(CO));


    register4 MemAdd(.clk(clk), .data_in(bus[3:0]),  .EI(MI),.data_out(Addr_in));

    RAM ram(.clk(~clk), .address(Addr_in), .write_enable(RW), .read_enable(RR), .data(bus));


    control ic(.CLK(clk),.command(Instout[7:4]), .ctrl_wrd({HLT,AI,AO,BI,MI,RR,RW,II,IO,CI,CO,CE,ALUOPTION,ALUO,DI,FL}));


    register8 O(.clk(clk), .data_in(bus), .EI(DI), .data_out(LED));





endmodule