data/full_repos/permissive/493019833/test/testcase/firrtl/FixedPrecisionChanger/reference/FixedPrecisionChanger.v
1: b'%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/FixedPrecisionChanger/reference/FixedPrecisionChanger.v:46: Operator COND expects 64 bits on the Conditional False, but Conditional False\'s VARREF \'in\' generates 22 bits.\n                                                                                                                                    : ... In instance FixedPrecisionChanger.s_pad_2\n    assign y = n > width ? {{(n - width){in[width-1]}}, in} : in;\n                         ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/493019833/test/testcase/firrtl/FixedPrecisionChanger/reference/FixedPrecisionChanger.v:39: Operator COND expects 22 bits on the Conditional False, but Conditional False\'s SEL generates 1 bits.\n                                                                                                                                    : ... In instance FixedPrecisionChanger.s_shr_1\n    assign y = n < width ? in[width-1:n] : in[width-1:width-1];\n                         ^\n%Error: Exiting due to 2 warning(s)\n'
module FixedPrecisionChanger(
    input clock,
    input reset,
    input [63:0] io_in,
    output [63:0] io_out
);
    wire [63:0] _reg___q;
    wire [63:0] _reg___d;
    DFF_POSCLK #(.width(64)) reg_ (
        .q(_reg___q),
        .d(_reg___d),
        .clk(clock)
    );
    wire [21:0] _node_0;
    SHR_SIGNED #(.width(64), .n(42)) s_shr_1 (
        .y(_node_0),
        .in(_reg___q)
    );
    PAD_SIGNED #(.width(22), .n(64)) s_pad_2 (
        .y(io_out),
        .in(_node_0)
    );
    assign _reg___d = io_in;
endmodule
module FixedPrecisionChanger(
    input clock,
    input reset,
    input [63:0] io_in,
    output [63:0] io_out
);

    wire [63:0] _reg___q;
    wire [63:0] _reg___d;
    DFF_POSCLK #(.width(64)) reg_ (
        .q(_reg___q),
        .d(_reg___d),
        .clk(clock)
    );
    wire [21:0] _node_0;
    SHR_SIGNED #(.width(64), .n(42)) s_shr_1 (
        .y(_node_0),
        .in(_reg___q)
    );
    PAD_SIGNED #(.width(22), .n(64)) s_pad_2 (
        .y(io_out),
        .in(_node_0)
    );
    assign _reg___d = io_in;
endmodule