data/full_repos/permissive/425816165/rtl/videogen.v
1: b'%Warning-WIDTH: data/full_repos/permissive/425816165/rtl/videogen.v:70: Operator ASSIGNW expects 11 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 10 bits.\n                                                                      : ... In instance videogen\n wire [10:0] charaddr = {membuf[6:0], charY[3:1]};\n                      ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/425816165/rtl/videogen.v:71: Bit extraction of array[1023:0] requires 10 bit index, not 11 bits.\n                                                                      : ... In instance videogen\n wire [8:0] charline = charY[4] ? 0 : {1\'b0, chars[charaddr], 1\'b0};\n                                                  ^\n%Error: Exiting due to 2 warning(s)\n'
module addressmap(
	input wire [6:0] X,
	input wire [4:0] Y,
	output wire [10:0] address
);
	wire outside = (&Y[4:3]) | X[6];
	assign address = outside ? {Y[0], 2'b11, Y[2:1], Y[4:3], X[3:0]} : { Y[0], Y[4:1], X[5:0]};
endmodule
module addressmap(
	input wire [6:0] X,
	input wire [4:0] Y,
	output wire [10:0] address
);

	wire outside = (&Y[4:3]) | X[6];
	assign address = outside ? {Y[0], 2'b11, Y[2:1], Y[4:3], X[3:0]} : { Y[0], Y[4:1], X[5:0]};
endmodule