data/full_repos/permissive/423686025/clkg.v
data/verilator_xmls/8d4b6207-39ea-4de8-aadc-17b47489b3ba.xml
module clkg(clko,reset,clk);
    output clko;
    input reset,clk;
    reg [5:0] count;
	 reg clko;
	 

    always @(posedge clk)
        begin
            if (!reset) 
				   begin
                count<=0;
					 clko<=1;
				   end
            else
                {clko,count}<=count+1;
					 
        end
		  



endmodule
module clkg(clko,reset,clk);

    output clko;
    input reset,clk;
    reg [5:0] count;
	 reg clko;
	 

    always @(posedge clk)
        begin
            if (!reset) 
				   begin
                count<=0;
					 clko<=1;
				   end
            else
                {clko,count}<=count+1;
					 
        end
		  



endmodule