data/full_repos/permissive/428601773/src/core/Core.v
1: b'%Error: data/full_repos/permissive/428601773/src/core/Core.v:1: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/428601773/src/core,data/full_repos/permissive/428601773/defines.v\n             data/full_repos/permissive/428601773/src/core,data/full_repos/permissive/428601773/defines.v.v\n             data/full_repos/permissive/428601773/src/core,data/full_repos/permissive/428601773/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/428601773/src/core/Core.v:2: Cannot find include file: ALU.v\n`include "ALU.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/428601773/src/core/Core.v:3: Cannot find include file: RegFile.v\n`include "RegFile.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/428601773/src/core/Core.v:4: Cannot find include file: Decoder.v\n`include "Decoder.v" \n         ^~~~~~~~~~~\n%Error: data/full_repos/permissive/428601773/src/core/Core.v:5: Cannot find include file: LSU.v\n`include "LSU.v" \n         ^~~~~~~\n%Error: data/full_repos/permissive/428601773/src/core/Core.v:51: Define or directive not defined: \'`ALU_OP_WIDTH\'\n  wire [`ALU_OP_WIDTH - 1: 0] alu_operation_signal;\n        ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/428601773/src/core/Core.v:101: Define or directive not defined: \'`TYPE_A_RD1\'\n      `TYPE_A_RD1:  operand_A <= rd1;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/428601773/src/core/Core.v:101: syntax error, unexpected \':\', expecting endcase\n      `TYPE_A_RD1:  operand_A <= rd1;\n                 ^\n%Error: data/full_repos/permissive/428601773/src/core/Core.v:102: Define or directive not defined: \'`TYPE_A_PC\'\n      `TYPE_A_PC:   operand_A <= pc;\n      ^~~~~~~~~~\n%Error: data/full_repos/permissive/428601773/src/core/Core.v:103: Define or directive not defined: \'`TYPE_A_ZERO\'\n      `TYPE_A_ZERO: operand_A <= 0;\n      ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/428601773/src/core/Core.v:106: Define or directive not defined: \'`TYPE_B_RD2\'\n      `TYPE_B_RD2:     operand_B <= rd2;\n      ^~~~~~~~~~~\n%Error: data/full_repos/permissive/428601773/src/core/Core.v:107: Define or directive not defined: \'`TYPE_B_IMM_I\'\n      `TYPE_B_IMM_I:   operand_B <= imm_I;\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/428601773/src/core/Core.v:108: Define or directive not defined: \'`TYPE_B_IMM_U\'\n      `TYPE_B_IMM_U:   operand_B <= imm_U;\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/428601773/src/core/Core.v:109: Define or directive not defined: \'`TYPE_B_IMM_S\'\n      `TYPE_B_IMM_S:   operand_B <= imm_S;\n      ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/428601773/src/core/Core.v:110: Define or directive not defined: \'`TYPE_B_PC_INCR\'\n      `TYPE_B_PC_INCR: operand_B <= 4;\n      ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/428601773/src/core/Core.v:126: syntax error, unexpected IDENTIFIER, expecting "\'{"\n  reg [31: 0] pc_increment, pre_pc;\n              ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/428601773/src/core/Core.v:131: syntax error, unexpected \':\'\n      {1\'b1, 1\'b0}: pc_increment <= imm_J;\n                  ^\n%Error: data/full_repos/permissive/428601773/src/core/Core.v:132: syntax error, unexpected \':\'\n      {1\'b1, 1\'b1}: pc_increment <= imm_B;\n                  ^\n%Error: data/full_repos/permissive/428601773/src/core/Core.v:141: Define or directive not defined: \'`RESET_ADDR\'\n      pc <= `RESET_ADDR;\n            ^~~~~~~~~~~\n%Error: data/full_repos/permissive/428601773/src/core/Core.v:141: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n      pc <= `RESET_ADDR;\n                       ^\n%Error: Exiting due to 20 error(s)\n'
module Core (
  input  clk,
  input  areset,


  input logic [31: 0] instr,
  output      [31: 0] instr_address,


  input logic [31: 0] external_data,
  output      [31: 0] internal_data,
  output      [31: 0] external_address,
  output      [3:  0] memory_load_byte_map,
  output       memory_require, memory_write_enable
);
  
    
  reg [31: 0] pc;
  assign instr_address = pc;
  

  wire [1: 0] opcode_type;
  wire [4: 0] opcode;
  wire [2: 0] func3;
  wire [4: 0] rs1, rs2, rd3;
  wire [6: 0] func7;

  assign {func7, rs2, rs1, func3, rd3, opcode, opcode_type} = instr; 
  
  wire [31: 0] imm_I = {{20{instr[31]}}, instr[31: 20]};
  wire [31: 0] imm_S = {{20{instr[31]}}, instr[31: 25], instr[11: 7]};
  wire [31: 0] imm_U = {  instr[31: 12], 12'b0};
  wire [31: 0] imm_B = {{20{instr[31]}}, instr[7], instr[30: 25], instr[11: 8], 1'b0};
  wire [31: 0] imm_J = {{12{instr[31]}}, instr[19: 12], instr[20], instr[30: 21], 1'b0};

  
  

  wire memory_require_signal, memory_write_enable_signal;
  wire reg_file_write_enable_signal, reg_file_write_data_type_signal;
  wire branch_signal, jal_signal, jalr_signal; 
  wire interrupted_signal, illegal_signal;
  wire [1: 0] operand_A_type_signal;
  wire [2: 0] operand_B_type_signal, memory_size_signal;
  wire [`ALU_OP_WIDTH - 1: 0] alu_operation_signal;
  
  Decoder Decoder_connection(
    .opcode_type(opcode_type),
    .opcode(opcode),
    .func3(func3),
    .func7(func7),
    
    .alu_operation(alu_operation_signal),
    .operand_A_type(operand_A_type_signal),
    .operand_B_type(operand_B_type_signal),

    .memory_require(memory_require_signal),
    .memory_write_enable(memory_write_enable_signal),
    .memory_size(memory_size_signal),

    .reg_file_write_enable(reg_file_write_enable_signal),
    .reg_file_write_data_type(reg_file_write_data_type_signal),

    .branch_flag(branch_signal),
    .jal_flag(jal_signal),
    .jalr_flag(jalr_signal),
    .stop_signal(interrupted_signal),
    .illegal_flag(illegal_signal)
  );


  

  wire [31: 0] rd1, rd2; 
  reg  [31: 0] wd3, operand_A, operand_B;
  wire [31: 0] alu_result, readed_data;
  wire comparator;
 
  RegFile RF_connection(
    .clk(clk),

    .address_1(rs1),
    .read_data_1(rd1),

    .address_2(rs2),
    .read_data_2(rd2),

    .address_3(rd3),
    .write_data_3(wd3),
    .write_enable_3(reg_file_write_enable_signal)
  );
  
  always @(*) begin
    case(operand_A_type_signal)
      `TYPE_A_RD1:  operand_A <= rd1;
      `TYPE_A_PC:   operand_A <= pc;
      `TYPE_A_ZERO: operand_A <= 0;
    endcase
    case(operand_B_type_signal)
      `TYPE_B_RD2:     operand_B <= rd2;
      `TYPE_B_IMM_I:   operand_B <= imm_I;
      `TYPE_B_IMM_U:   operand_B <= imm_U;
      `TYPE_B_IMM_S:   operand_B <= imm_S;
      `TYPE_B_PC_INCR: operand_B <= 4;
    endcase
  end
  
  ALU ALU_connection(
    .A(operand_A),
    .B(operand_B),
    .operation(alu_operation_signal),
    
    .result(alu_result),
    .flag(comparator)
  );

  
  

  reg [31: 0] pc_increment, pre_pc;
    
  always @(*) begin
    casez({jal_signal | branch_signal & comparator, branch_signal})
      {1'b0, 1'b?}: pc_increment <= 3'd4;
      {1'b1, 1'b0}: pc_increment <= imm_J;
      {1'b1, 1'b1}: pc_increment <= imm_B;
    endcase
    pre_pc <= ( (jalr_signal) ? rd1 + imm_I : pc + pc_increment  );

  end

  wire en_pc;
  always @(posedge clk) begin
    if (areset) begin
      pc <= `RESET_ADDR;
    end else 
      if (!en_pc)
        pc <= pre_pc;
      else
        $display("interrupted");


  end

  

  LSU LSU_connection(
    .clk(clk),
    .areset(areset),
    
    .core_address(alu_result),
    .core_write_data(rd2),
    .core_require(memory_require_signal),
    .core_write_enable(memory_write_enable_signal),
    .core_size(memory_size_signal),

    .core_read_data(readed_data),
    .core_stall_signal(en_pc),
    
    .memory_read_data(external_data),
    
    .memory_begin_signal(data_gnt_i),
    .memory_end_signal(data_rvalid_i),
    .memory_require(memory_require),
    .memory_write_enable(memory_write_enable),
    .memory_byte_enable_map(memory_load_byte_map),
    .memory_address(external_address),
    .memory_write_data(internal_data)
  );

  


  always @(*)
    wd3 <= ((reg_file_write_data_type_signal) ? readed_data : alu_result);

endmodule
module Core (
  input  clk,
  input  areset,


  input logic [31: 0] instr,
  output      [31: 0] instr_address,


  input logic [31: 0] external_data,
  output      [31: 0] internal_data,
  output      [31: 0] external_address,
  output      [3:  0] memory_load_byte_map,
  output       memory_require, memory_write_enable
);

  
    
  reg [31: 0] pc;
  assign instr_address = pc;
  

  wire [1: 0] opcode_type;
  wire [4: 0] opcode;
  wire [2: 0] func3;
  wire [4: 0] rs1, rs2, rd3;
  wire [6: 0] func7;

  assign {func7, rs2, rs1, func3, rd3, opcode, opcode_type} = instr; 
  
  wire [31: 0] imm_I = {{20{instr[31]}}, instr[31: 20]};
  wire [31: 0] imm_S = {{20{instr[31]}}, instr[31: 25], instr[11: 7]};
  wire [31: 0] imm_U = {  instr[31: 12], 12'b0};
  wire [31: 0] imm_B = {{20{instr[31]}}, instr[7], instr[30: 25], instr[11: 8], 1'b0};
  wire [31: 0] imm_J = {{12{instr[31]}}, instr[19: 12], instr[20], instr[30: 21], 1'b0};

  
  

  wire memory_require_signal, memory_write_enable_signal;
  wire reg_file_write_enable_signal, reg_file_write_data_type_signal;
  wire branch_signal, jal_signal, jalr_signal; 
  wire interrupted_signal, illegal_signal;
  wire [1: 0] operand_A_type_signal;
  wire [2: 0] operand_B_type_signal, memory_size_signal;
  wire [`ALU_OP_WIDTH - 1: 0] alu_operation_signal;
  
  Decoder Decoder_connection(
    .opcode_type(opcode_type),
    .opcode(opcode),
    .func3(func3),
    .func7(func7),
    
    .alu_operation(alu_operation_signal),
    .operand_A_type(operand_A_type_signal),
    .operand_B_type(operand_B_type_signal),

    .memory_require(memory_require_signal),
    .memory_write_enable(memory_write_enable_signal),
    .memory_size(memory_size_signal),

    .reg_file_write_enable(reg_file_write_enable_signal),
    .reg_file_write_data_type(reg_file_write_data_type_signal),

    .branch_flag(branch_signal),
    .jal_flag(jal_signal),
    .jalr_flag(jalr_signal),
    .stop_signal(interrupted_signal),
    .illegal_flag(illegal_signal)
  );


  

  wire [31: 0] rd1, rd2; 
  reg  [31: 0] wd3, operand_A, operand_B;
  wire [31: 0] alu_result, readed_data;
  wire comparator;
 
  RegFile RF_connection(
    .clk(clk),

    .address_1(rs1),
    .read_data_1(rd1),

    .address_2(rs2),
    .read_data_2(rd2),

    .address_3(rd3),
    .write_data_3(wd3),
    .write_enable_3(reg_file_write_enable_signal)
  );
  
  always @(*) begin
    case(operand_A_type_signal)
      `TYPE_A_RD1:  operand_A <= rd1;
      `TYPE_A_PC:   operand_A <= pc;
      `TYPE_A_ZERO: operand_A <= 0;
    endcase
    case(operand_B_type_signal)
      `TYPE_B_RD2:     operand_B <= rd2;
      `TYPE_B_IMM_I:   operand_B <= imm_I;
      `TYPE_B_IMM_U:   operand_B <= imm_U;
      `TYPE_B_IMM_S:   operand_B <= imm_S;
      `TYPE_B_PC_INCR: operand_B <= 4;
    endcase
  end
  
  ALU ALU_connection(
    .A(operand_A),
    .B(operand_B),
    .operation(alu_operation_signal),
    
    .result(alu_result),
    .flag(comparator)
  );

  
  

  reg [31: 0] pc_increment, pre_pc;
    
  always @(*) begin
    casez({jal_signal | branch_signal & comparator, branch_signal})
      {1'b0, 1'b?}: pc_increment <= 3'd4;
      {1'b1, 1'b0}: pc_increment <= imm_J;
      {1'b1, 1'b1}: pc_increment <= imm_B;
    endcase
    pre_pc <= ( (jalr_signal) ? rd1 + imm_I : pc + pc_increment  );

  end

  wire en_pc;
  always @(posedge clk) begin
    if (areset) begin
      pc <= `RESET_ADDR;
    end else 
      if (!en_pc)
        pc <= pre_pc;
      else
        $display("interrupted");


  end

  

  LSU LSU_connection(
    .clk(clk),
    .areset(areset),
    
    .core_address(alu_result),
    .core_write_data(rd2),
    .core_require(memory_require_signal),
    .core_write_enable(memory_write_enable_signal),
    .core_size(memory_size_signal),

    .core_read_data(readed_data),
    .core_stall_signal(en_pc),
    
    .memory_read_data(external_data),
    
    .memory_begin_signal(data_gnt_i),
    .memory_end_signal(data_rvalid_i),
    .memory_require(memory_require),
    .memory_write_enable(memory_write_enable),
    .memory_byte_enable_map(memory_load_byte_map),
    .memory_address(external_address),
    .memory_write_data(internal_data)
  );

  


  always @(*)
    wd3 <= ((reg_file_write_data_type_signal) ? readed_data : alu_result);

endmodule