data/full_repos/permissive/449807379/CPU_design/shiftLeft.v
1: b'%Warning-WIDTH: data/full_repos/permissive/449807379/CPU_design/shiftLeft.v:20: Operator SHIFTL expects 33 bits on the LHS, but LHS\'s VARREF \'din\' generates 32 bits.\n                                                                              : ... In instance leftShift_reg\n  temp = din<<N;\n            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/449807379/CPU_design/shiftLeft.v:22: Operator SHIFTL expects 33 bits on the LHS, but LHS\'s VARREF \'din\' generates 32 bits.\n                                                                              : ... In instance leftShift_reg\n  temp = din<<s_value;\n            ^~\n%Error: Exiting due to 2 warning(s)\n'
module leftShift_reg(din,out,s_value,enbit);

parameter N = 5;

input [31:0] din;
input [4:0] s_value;
input enbit;
output reg [35:0] out;

reg [32:0] temp;

reg isNegative, isZero, hasCarry, hasOverflow;

always@*
begin
if(enbit==1'b1)
begin

	if( s_value > N)
		temp = din<<N;
	else
		temp = din<<s_value;
		
isNegative = (temp[31] == 1'b1) ? 1'b1 : 1'b0;
isZero = (temp[31:0] == 32'b0) ? 1'b1 : 1'b0;
hasCarry = (temp[32] == 1'b1 ) ? 1'b1 : 1'b0;
hasOverflow = 1'b0;
out = {isNegative, isZero, hasCarry, hasOverflow, temp[31:0] };
end
else 
begin
out = {4'b0,32'bz};
end
end
endmodule
module leftShift_reg(din,out,s_value,enbit);


parameter N = 5;

input [31:0] din;
input [4:0] s_value;
input enbit;
output reg [35:0] out;

reg [32:0] temp;

reg isNegative, isZero, hasCarry, hasOverflow;

always@*
begin
if(enbit==1'b1)
begin

	if( s_value > N)
		temp = din<<N;
	else
		temp = din<<s_value;
		
isNegative = (temp[31] == 1'b1) ? 1'b1 : 1'b0;
isZero = (temp[31:0] == 32'b0) ? 1'b1 : 1'b0;
hasCarry = (temp[32] == 1'b1 ) ? 1'b1 : 1'b0;
hasOverflow = 1'b0;
out = {isNegative, isZero, hasCarry, hasOverflow, temp[31:0] };
end
else 
begin
out = {4'b0,32'bz};
end
end
endmodule