data/full_repos/permissive/496266817/rtl/bram1024_core.v
data/verilator_xmls/3aad0b6e-14a1-4501-9faf-23013461fa2d.xml
module bram1024_core #(parameter ADDR_WIDTH = 10, DATA_WIDTH = 1024, DEPTH = 1024) (
    input wire i_clk,
    input wire [ADDR_WIDTH-1:0] i_addr, 
    input wire i_write,

    input wire [DATA_WIDTH-1:0] i_data,
    output wire [DATA_WIDTH-1:0] o_data

    );
    reg [DATA_WIDTH-1:0] memory_array [0:DEPTH-1];
	reg [DATA_WIDTH-1:0] o_data_reg;
	assign o_data = o_data_reg;
    always @ (posedge i_clk) begin
	    o_data_reg <= memory_array [i_addr];

        if(i_write==1'b1) begin
            memory_array[i_addr] <= i_data;
        end
    end
endmodule
module bram1024_core #(parameter ADDR_WIDTH = 10, DATA_WIDTH = 1024, DEPTH = 1024) (
    input wire i_clk,
    input wire [ADDR_WIDTH-1:0] i_addr, 
    input wire i_write,

    input wire [DATA_WIDTH-1:0] i_data,
    output wire [DATA_WIDTH-1:0] o_data

    );

    reg [DATA_WIDTH-1:0] memory_array [0:DEPTH-1];
	reg [DATA_WIDTH-1:0] o_data_reg;
	assign o_data = o_data_reg;
    always @ (posedge i_clk) begin
	    o_data_reg <= memory_array [i_addr];

        if(i_write==1'b1) begin
            memory_array[i_addr] <= i_data;
        end
    end
endmodule