data/full_repos/permissive/478063538/decoder_3_8_B.v
data/verilator_xmls/92d40016-5c01-47c8-86e3-f5d7db2792b7.xml
module decoder_3_8_B (
	input [2:0] a, 
	input en,
	output reg [7:0] z
	);
	
	always@(a, en)
	begin
		if (~en)
			case(a)
				0: z = ~1;
				1: z = ~2;
				2: z = ~4;
				3: z = ~8;
				4: z = ~16;
				5: z = ~32;
				6: z = ~64;
				7: z = ~128;
				default: z = ~0;
			endcase
		else
			z = ~0;
	end
	
endmodule
module decoder_3_8_B (
	input [2:0] a, 
	input en,
	output reg [7:0] z
	);

	
	always@(a, en)
	begin
		if (~en)
			case(a)
				0: z = ~1;
				1: z = ~2;
				2: z = ~4;
				3: z = ~8;
				4: z = ~16;
				5: z = ~32;
				6: z = ~64;
				7: z = ~128;
				default: z = ~0;
			endcase
		else
			z = ~0;
	end
	
endmodule