data/full_repos/permissive/454159683/bcd2dec/bcd2dec.v
data/verilator_xmls/cb2aaff8-d713-40c5-b240-35dbef941177.xml
module bcd2dec(input [3:0]bcd, output reg [9:0]out);
	always @(bcd)
	begin
		case(bcd)
			 0: out = 1;
			 9: out = 2;
			 8: out = 4;
			 7: out = 8;
			 6: out = 16;
			 5: out = 32;
			 4: out = 64;
			 3: out = 128;
			 2: out = 256;
			 1: out = 512;
			 default: out = 0;
		 endcase
	end
endmodule
module bcd2dec(input [3:0]bcd, output reg [9:0]out);

	always @(bcd)
	begin
		case(bcd)
			 0: out = 1;
			 9: out = 2;
			 8: out = 4;
			 7: out = 8;
			 6: out = 16;
			 5: out = 32;
			 4: out = 64;
			 3: out = 128;
			 2: out = 256;
			 1: out = 512;
			 default: out = 0;
		 endcase
	end
endmodule