data/full_repos/permissive/414822257/verilog/rtl/user_project_wrapper.v
1: b"%Error: data/full_repos/permissive/414822257/verilog/rtl/user_project_wrapper.v:64: Define or directive not defined: '`MPRJ_IO_PADS'\n  input  [`MPRJ_IO_PADS-1:0] io_in,\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/414822257/verilog/rtl/user_project_wrapper.v:65: Define or directive not defined: '`MPRJ_IO_PADS'\n  output [`MPRJ_IO_PADS-1:0] io_out,\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/414822257/verilog/rtl/user_project_wrapper.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n  output [`MPRJ_IO_PADS-1:0] io_oeb,\n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/414822257/verilog/rtl/user_project_wrapper.v:72: Define or directive not defined: '`MPRJ_IO_PADS'\n  inout [`MPRJ_IO_PADS-10:0] analog_io,\n         ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module user_project_wrapper #(
  parameter BITS = 32
) (
`ifdef USE_POWER_PINS
  inout vdda1,
  inout vdda2,
  inout vssa1,
  inout vssa2,
  inout vccd1,
  inout vccd2,
  inout vssd1,
  inout vssd2,
`endif


  input wb_clk_i,
  input wb_rst_i,
  input wbs_stb_i,
  input wbs_cyc_i,
  input wbs_we_i,
  input [3:0] wbs_sel_i,
  input [31:0] wbs_dat_i,
  input [31:0] wbs_adr_i,
  output wbs_ack_o,
  output [31:0] wbs_dat_o,


  input  [127:0] la_data_in,
  output [127:0] la_data_out,
  input  [127:0] la_oenb,


  input  [`MPRJ_IO_PADS-1:0] io_in,
  output [`MPRJ_IO_PADS-1:0] io_out,
  output [`MPRJ_IO_PADS-1:0] io_oeb,





  inout [`MPRJ_IO_PADS-10:0] analog_io,


  input   user_clock2,


  output [2:0] user_irq
);





  wire ring0_clk;
  wire ring0_start;
  wire [27:0] ring0_trim_a;
  wire [27:0] ring0_trim_b;
  wire [2:0] ring0_clkmux;

  wire ring1_clk;
  wire ring1_start;
  wire [25:0] ring1_trim_a;
  wire [2:0] ring1_clkmux;

digitalcore_macro digitalcore (
`ifdef USE_POWER_PINS
  .vccd1(vccd1),
  .vssd1(vssd1),
`endif

  .wb_clk_i(wb_clk_i),
  .wb_rst_i(wb_rst_i),


  .wbs_cyc_i(wbs_cyc_i),
  .wbs_stb_i(wbs_stb_i),
  .wbs_we_i(wbs_we_i),
  .wbs_sel_i(wbs_sel_i),
  .wbs_adr_i(wbs_adr_i),
  .wbs_dat_i(wbs_dat_i),
  .wbs_ack_o(wbs_ack_o),
  .wbs_dat_o(wbs_dat_o),


  .la_data_in(la_data_in),
  .la_data_out(la_data_out),
  .la_oenb (la_oenb),


  .io_in (io_in),
  .io_out(io_out),
  .io_oeb(io_oeb),


  .irq(user_irq),


  .ring0_clk(ring0_clk),
  .ring0_start(ring0_start),
  .ring0_trim_a(ring0_trim_a),
  .ring0_trim_b(ring0_trim_b),
  .ring0_clkmux(ring0_clkmux),


  .ring1_clk(ring1_clk),
  .ring1_start(ring1_start),
  .ring1_trim_a(ring1_trim_a),
  .ring1_clkmux(ring1_clkmux)
);

collapsering_macro ring0 (
`ifdef USE_POWER_PINS
  .vccd1(vccd1),
  .vssd1(vssd1),
`endif

  .clk_out(ring0_clk),
  .start(ring0_start),
  .trim_a(ring0_trim_a),
  .trim_b(ring0_trim_b),
  .clkmux(ring0_clkmux)
);

ringosc_macro ring1 (
`ifdef USE_POWER_PINS
  .vccd1(vccd1),
  .vssd1(vssd1),
`endif

  .clk_out(ring1_clk),
  .start(ring1_start),
  .trim_a(ring1_trim_a),
  .clkmux(ring1_clkmux)
);

endmodule
module user_project_wrapper #(
  parameter BITS = 32
) (
`ifdef USE_POWER_PINS
  inout vdda1,
  inout vdda2,
  inout vssa1,
  inout vssa2,
  inout vccd1,
  inout vccd2,
  inout vssd1,
  inout vssd2,
`endif


  input wb_clk_i,
  input wb_rst_i,
  input wbs_stb_i,
  input wbs_cyc_i,
  input wbs_we_i,
  input [3:0] wbs_sel_i,
  input [31:0] wbs_dat_i,
  input [31:0] wbs_adr_i,
  output wbs_ack_o,
  output [31:0] wbs_dat_o,


  input  [127:0] la_data_in,
  output [127:0] la_data_out,
  input  [127:0] la_oenb,


  input  [`MPRJ_IO_PADS-1:0] io_in,
  output [`MPRJ_IO_PADS-1:0] io_out,
  output [`MPRJ_IO_PADS-1:0] io_oeb,





  inout [`MPRJ_IO_PADS-10:0] analog_io,


  input   user_clock2,


  output [2:0] user_irq
);






  wire ring0_clk;
  wire ring0_start;
  wire [27:0] ring0_trim_a;
  wire [27:0] ring0_trim_b;
  wire [2:0] ring0_clkmux;

  wire ring1_clk;
  wire ring1_start;
  wire [25:0] ring1_trim_a;
  wire [2:0] ring1_clkmux;

digitalcore_macro digitalcore (
`ifdef USE_POWER_PINS
  .vccd1(vccd1),
  .vssd1(vssd1),
`endif

  .wb_clk_i(wb_clk_i),
  .wb_rst_i(wb_rst_i),


  .wbs_cyc_i(wbs_cyc_i),
  .wbs_stb_i(wbs_stb_i),
  .wbs_we_i(wbs_we_i),
  .wbs_sel_i(wbs_sel_i),
  .wbs_adr_i(wbs_adr_i),
  .wbs_dat_i(wbs_dat_i),
  .wbs_ack_o(wbs_ack_o),
  .wbs_dat_o(wbs_dat_o),


  .la_data_in(la_data_in),
  .la_data_out(la_data_out),
  .la_oenb (la_oenb),


  .io_in (io_in),
  .io_out(io_out),
  .io_oeb(io_oeb),


  .irq(user_irq),


  .ring0_clk(ring0_clk),
  .ring0_start(ring0_start),
  .ring0_trim_a(ring0_trim_a),
  .ring0_trim_b(ring0_trim_b),
  .ring0_clkmux(ring0_clkmux),


  .ring1_clk(ring1_clk),
  .ring1_start(ring1_start),
  .ring1_trim_a(ring1_trim_a),
  .ring1_clkmux(ring1_clkmux)
);

collapsering_macro ring0 (
`ifdef USE_POWER_PINS
  .vccd1(vccd1),
  .vssd1(vssd1),
`endif

  .clk_out(ring0_clk),
  .start(ring0_start),
  .trim_a(ring0_trim_a),
  .trim_b(ring0_trim_b),
  .clkmux(ring0_clkmux)
);

ringosc_macro ring1 (
`ifdef USE_POWER_PINS
  .vccd1(vccd1),
  .vssd1(vssd1),
`endif

  .clk_out(ring1_clk),
  .start(ring1_start),
  .trim_a(ring1_trim_a),
  .clkmux(ring1_clkmux)
);

endmodule