data/full_repos/permissive/509783883/sequenceDetector/sequenceTester.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/509783883/sequenceDetector/sequenceTester.v:21: Unsupported: Ignoring delay on this delayed statement.\n  #5 clock = ~clock;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/509783883/sequenceDetector/sequenceTester.v:27: Unsupported: Ignoring delay on this delayed statement.\n #30\n ^\n%Warning-STMTDLY: data/full_repos/permissive/509783883/sequenceDetector/sequenceTester.v:29: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/509783883/sequenceDetector/sequenceTester.v:31: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/509783883/sequenceDetector/sequenceTester.v:33: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/509783883/sequenceDetector/sequenceTester.v:35: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/509783883/sequenceDetector/sequenceTester.v:37: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/509783883/sequenceDetector/sequenceTester.v:39: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/509783883/sequenceDetector/sequenceTester.v:41: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/509783883/sequenceDetector/sequenceTester.v:43: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/509783883/sequenceDetector/sequenceTester.v:45: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/509783883/sequenceDetector/sequenceTester.v:47: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Error: data/full_repos/permissive/509783883/sequenceDetector/sequenceTester.v:11: Cannot find file containing module: \'seqDetector\'\nseqDetector one(\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/509783883/sequenceDetector,data/full_repos/permissive/509783883/seqDetector\n             data/full_repos/permissive/509783883/sequenceDetector,data/full_repos/permissive/509783883/seqDetector.v\n             data/full_repos/permissive/509783883/sequenceDetector,data/full_repos/permissive/509783883/seqDetector.sv\n             seqDetector\n             seqDetector.v\n             seqDetector.sv\n             obj_dir/seqDetector\n             obj_dir/seqDetector.v\n             obj_dir/seqDetector.sv\n%Error: Exiting due to 1 error(s), 12 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module seqTester;

reg sequence_in;
reg reset;
reg clock;

wire detector_out;

seqDetector one(
.sequence_in(sequence_in),
.clock(clock),
.reset(reset),
.detector_out(detector_out)
);

initial begin
	clock = 0;
	forever
		#5 clock = ~clock;
end

initial begin
	sequence_in = 0;
	reset = 1;
	#30
	reset = 0;
	#40;
	sequence_in = 1;
	#10;
	sequence_in = 0;
	#10;
	sequence_in = 1;
	#10;
	sequence_in = 0;
	#10;
	sequence_in = 1;
	#10;
	sequence_in = 1;
	#10;
	sequence_in = 0;
	#10;
	sequence_in = 1;
	#10;
	sequence_in = 1;
	#10;
	sequence_in = 0;
end

endmodule
module seqTester;


reg sequence_in;
reg reset;
reg clock;

wire detector_out;

seqDetector one(
.sequence_in(sequence_in),
.clock(clock),
.reset(reset),
.detector_out(detector_out)
);

initial begin
	clock = 0;
	forever
		#5 clock = ~clock;
end

initial begin
	sequence_in = 0;
	reset = 1;
	#30
	reset = 0;
	#40;
	sequence_in = 1;
	#10;
	sequence_in = 0;
	#10;
	sequence_in = 1;
	#10;
	sequence_in = 0;
	#10;
	sequence_in = 1;
	#10;
	sequence_in = 1;
	#10;
	sequence_in = 0;
	#10;
	sequence_in = 1;
	#10;
	sequence_in = 1;
	#10;
	sequence_in = 0;
end

endmodule