data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_array/cachelib/v_rtl/dut_Equal_6Ux3U_1U_4.v
1: b'%Warning-WIDTH: data/full_repos/permissive/452098851/tutorial/stratus_examples/lab_array/cachelib/v_rtl/dut_Equal_6Ux3U_1U_4.v:34: Operator EQ expects 6 bits on the LHS, but LHS\'s VARREF \'in1\' generates 3 bits.\n                                                                                                                                 : ... In instance dut_Equal_6Ux3U_1U_4\nassign asc001 = (in1==in2);\n                    ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module dut_Equal_6Ux3U_1U_4 (
	in2,
	in1,
	out1
	);
input [5:0] in2;
input [2:0] in1;
output  out1;
wire  asc001;

assign asc001 = (in1==in2);

assign out1 = asc001;
endmodule
module dut_Equal_6Ux3U_1U_4 (
	in2,
	in1,
	out1
	);

input [5:0] in2;
input [2:0] in1;
output  out1;
wire  asc001;

assign asc001 = (in1==in2);

assign out1 = asc001;
endmodule