data/full_repos/permissive/420070038/examples/bootloader/fusesoc/rtl/rst/rstgen.sv
data/verilator_xmls/141d23ad-a8ed-445d-aaf0-6e71ae909a84.xml
module rstgen
       (

	input  sys_clk_pad_i,

	input  rst_n_pad_i,
	input locked_mcm,


	input wb_clk,

	output wb_rst_o,
	output ddr2_if_rst_o
);







logic [15:0] 	   wb_rst_shr;
always_ff @(posedge wb_clk or posedge rst_n_pad_i)
	if (rst_n_pad_i)
		wb_rst_shr <= 16'hffff;
	else
		wb_rst_shr <= {wb_rst_shr[14:0], ~(locked_mcm)};

assign wb_rst_o = ~ rst_n_pad_i;

assign ddr2_if_rst_o = rst_n_pad_i;

endmodule
module rstgen
       (

	input  sys_clk_pad_i,

	input  rst_n_pad_i,
	input locked_mcm,


	input wb_clk,

	output wb_rst_o,
	output ddr2_if_rst_o
);








logic [15:0] 	   wb_rst_shr;
always_ff @(posedge wb_clk or posedge rst_n_pad_i)
	if (rst_n_pad_i)
		wb_rst_shr <= 16'hffff;
	else
		wb_rst_shr <= {wb_rst_shr[14:0], ~(locked_mcm)};

assign wb_rst_o = ~ rst_n_pad_i;

assign ddr2_if_rst_o = rst_n_pad_i;

endmodule