data/full_repos/permissive/505918157/Regfile.v
data/verilator_xmls/19625b44-91ca-4de6-9cc0-65b3af58e6d8.xml
module Regfile(
    input clk_n,
    input rst_n,
    input [4:0] Rs1,
    input [4:0] Rs2,
    input [4:0] Rd,
    
    input Wen,
    output [31:0]BusA,      
    output [31:0]BusB,
    input [31:0]BusW
);

    reg [31:0] DataReg[31:0];

    integer i;
    
    always@(negedge clk_n or negedge rst_n)begin
        if(!rst_n)begin
            for(i=0;i<32;i=i+1)
                DataReg[i] <= 32'B0;
        end
        else if(Wen&Rd!=5'd0) DataReg[Rd]<=BusW;
    end
    
    assign BusA=DataReg[Rs1];
    assign BusB=DataReg[Rs2];
 
endmodule
module Regfile(
    input clk_n,
    input rst_n,
    input [4:0] Rs1,
    input [4:0] Rs2,
    input [4:0] Rd,
    
    input Wen,
    output [31:0]BusA,      
    output [31:0]BusB,
    input [31:0]BusW
);


    reg [31:0] DataReg[31:0];

    integer i;
    
    always@(negedge clk_n or negedge rst_n)begin
        if(!rst_n)begin
            for(i=0;i<32;i=i+1)
                DataReg[i] <= 32'B0;
        end
        else if(Wen&Rd!=5'd0) DataReg[Rd]<=BusW;
    end
    
    assign BusA=DataReg[Rs1];
    assign BusB=DataReg[Rs2];
 
endmodule