data/full_repos/permissive/433640910/RateDivider/500hertzdivider.v
data/verilator_xmls/b39f86ae-6406-42e9-ab5c-066d899b9777.xml
module RateDivider(Speed, ClockIn, Clear_b, Out);
	input [1:0]Speed;
	input	ClockIn, Clear_b;
	output reg [10:0] Out;
	reg [10:0] d;
	
	always @(Speed)
	begin
	case (Speed)
		2'b00: d <= 11'b00000000000;
		2'b01: d <= 11'b00111110011;
		2'b10: d <= 11'b01111100111;
		2'b11: d <= 11'b11111001111;
		default: d <= 11'b00000000000;
	endcase
	end
	
	always@ (posedge ClockIn)
	begin
		if(Clear_b)
			Out <= 11'b00000000000;
		else if (Out == 11'b00000000000)				
			Out <= d;
		else  
			Out <= Out - 1;
		end
	
endmodule
module RateDivider(Speed, ClockIn, Clear_b, Out);

	input [1:0]Speed;
	input	ClockIn, Clear_b;
	output reg [10:0] Out;
	reg [10:0] d;
	
	always @(Speed)
	begin
	case (Speed)
		2'b00: d <= 11'b00000000000;
		2'b01: d <= 11'b00111110011;
		2'b10: d <= 11'b01111100111;
		2'b11: d <= 11'b11111001111;
		default: d <= 11'b00000000000;
	endcase
	end
	
	always@ (posedge ClockIn)
	begin
		if(Clear_b)
			Out <= 11'b00000000000;
		else if (Out == 11'b00000000000)				
			Out <= d;
		else  
			Out <= Out - 1;
		end
	
endmodule