data/full_repos/permissive/449071180/D_Flip_Flop.v
data/verilator_xmls/74866d97-a8db-40e4-9925-320c9fa80409.xml
module D_Flip_Flop(D,Q,Rst,Clk,set);
input D,Rst,Clk,set;
output reg Q;

always@(posedge Clk,posedge Rst, posedge set) begin
if(set == 1) begin
Q <= 1;
end
else if(Rst == 1) begin
Q <= 0;
end
else begin
Q <= D;
end
end

endmodule
module D_Flip_Flop(D,Q,Rst,Clk,set);

input D,Rst,Clk,set;
output reg Q;

always@(posedge Clk,posedge Rst, posedge set) begin
if(set == 1) begin
Q <= 1;
end
else if(Rst == 1) begin
Q <= 0;
end
else begin
Q <= D;
end
end

endmodule