data/full_repos/permissive/482848318/Debug_Interface_testbench.v
1: b'%Error: data/full_repos/permissive/482848318/Debug_Interface_testbench.v:19: Unsupported or unknown PLI call: $monitor\n    $monitor($time, " ALUout=%d, Ain=%d, Bin=%d, ALUop=%b, dsel=%b, dout=%d ",    \n    ^~~~~~~~\n%Error: data/full_repos/permissive/482848318/Debug_Interface_testbench.v:27: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("Debug_Interface.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/482848318/Debug_Interface_testbench.v:28: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(1, Debug_interface_testbench);\n    ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/482848318/Debug_Interface_testbench.v:30: Unsupported: Ignoring delay on this delayed statement.\n    #0 ALUout=0; Ain=15; Bin=0; ALUop=0; dsel=0;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/482848318/Debug_Interface_testbench.v:34: Unsupported: Ignoring delay on this delayed statement.\n      #50 ALUout <= ALUout + stepSize;\n      ^\n%Warning-STMTDLY: data/full_repos/permissive/482848318/Debug_Interface_testbench.v:37: Unsupported: Ignoring delay on this delayed statement.\n       #50 Ain <= Ain - stepSize;\n       ^\n%Warning-STMTDLY: data/full_repos/permissive/482848318/Debug_Interface_testbench.v:38: Unsupported: Ignoring delay on this delayed statement.\n        #50 Bin <= Bin + stepSize;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/482848318/Debug_Interface_testbench.v:41: Unsupported: Ignoring delay on this delayed statement.\n          #50 ALUop <= ALUop + stepSize;\n          ^\n%Warning-STMTDLY: data/full_repos/permissive/482848318/Debug_Interface_testbench.v:44: Unsupported: Ignoring delay on this delayed statement.\n            #50 dsel <= dsel + 1;\n            ^\n%Error: Exiting due to 3 error(s), 6 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module Debug_interface_testbench();
  
  reg [3:0] Ain, Bin, ALUout;
  reg [2:0] ALUop;
  reg [1:0] dsel;
  wire [7:0] dout;
  
  Debug_Interface DUT( .Ain(Ain), .Bin(Bin), .ALUout(ALUout), 
                      .ALUop(ALUop), .dsel(dsel), .dout(dout));
  
  initial
  begin
    $monitor($time, " ALUout=%d, Ain=%d, Bin=%d, ALUop=%b, dsel=%b, dout=%d ", 			
             ALUout,Ain,Bin,ALUop,dsel,dout);
  end
  
  integer stepSize = 4;
  
  initial
  begin
    $dumpfile("Debug_Interface.vcd");
    $dumpvars(1, Debug_interface_testbench);
    
    #0 ALUout=0; Ain=15; Bin=0; ALUop=0; dsel=0;
    
    repeat (15 / stepSize)
    begin
      #50 ALUout <= ALUout + stepSize;
      repeat (15 / stepSize)
      begin
      	#50 Ain <= Ain - stepSize;
        #50 Bin <= Bin + stepSize;
        repeat (7 / stepSize)
        begin
          #50 ALUop <= ALUop + stepSize;
          repeat (3)
          begin
            #50 dsel <= dsel + 1;
          end
        end
      end
    end
    
  end

endmodule
module Debug_interface_testbench();

  
  reg [3:0] Ain, Bin, ALUout;
  reg [2:0] ALUop;
  reg [1:0] dsel;
  wire [7:0] dout;
  
  Debug_Interface DUT( .Ain(Ain), .Bin(Bin), .ALUout(ALUout), 
                      .ALUop(ALUop), .dsel(dsel), .dout(dout));
  
  initial
  begin
    $monitor($time, " ALUout=%d, Ain=%d, Bin=%d, ALUop=%b, dsel=%b, dout=%d ", 			
             ALUout,Ain,Bin,ALUop,dsel,dout);
  end
  
  integer stepSize = 4;
  
  initial
  begin
    $dumpfile("Debug_Interface.vcd");
    $dumpvars(1, Debug_interface_testbench);
    
    #0 ALUout=0; Ain=15; Bin=0; ALUop=0; dsel=0;
    
    repeat (15 / stepSize)
    begin
      #50 ALUout <= ALUout + stepSize;
      repeat (15 / stepSize)
      begin
      	#50 Ain <= Ain - stepSize;
        #50 Bin <= Bin + stepSize;
        repeat (7 / stepSize)
        begin
          #50 ALUop <= ALUop + stepSize;
          repeat (3)
          begin
            #50 dsel <= dsel + 1;
          end
        end
      end
    end
    
  end

endmodule