data/full_repos/permissive/434840709/USTB_digital_logic_homework/task3/top.v
1: b'%Warning-IMPLICIT: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task3/top.v:50: Signal definition not found, creating implicitly: \'key_rd_rise\'\n                                                                                                  : ... Suggested alternative: \'key_disp\'\n assign key_rd_rise=key_rd_ff1&(key_rd_ff2==0);\n        ^~~~~~~~~~~\n                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task3/top.v:53: Cannot find file containing module: \'clkDiv\'\n clkDiv U1(clk100mhz,clk190hz,clk3hz,clk10m);\n ^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/434840709/USTB_digital_logic_homework/task3,data/full_repos/permissive/434840709/clkDiv\n             data/full_repos/permissive/434840709/USTB_digital_logic_homework/task3,data/full_repos/permissive/434840709/clkDiv.v\n             data/full_repos/permissive/434840709/USTB_digital_logic_homework/task3,data/full_repos/permissive/434840709/clkDiv.sv\n             clkDiv\n             clkDiv.v\n             clkDiv.sv\n             obj_dir/clkDiv\n             obj_dir/clkDiv.v\n             obj_dir/clkDiv.sv\n%Error: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task3/top.v:54: Cannot find file containing module: \'key_xd\'\n key_xd Ukey_wei_xd(\n ^~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task3/top.v:60: Cannot find file containing module: \'key_xd\'\n key_xd Ukey_enter_xd(\n ^~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task3/top.v:66: Cannot find file containing module: \'key_xd\'\n key_xd Ukey_input_xd(\n ^~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task3/top.v:72: Cannot find file containing module: \'key_xd\'\n key_xd Ukey_shuzi_xd(\n ^~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task3/top.v:78: Cannot find file containing module: \'key_xd\'\n key_xd Ukey_disp_xd(\n ^~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task3/top.v:84: Cannot find file containing module: \'key_ctrl\'\n key_ctrl Ukey_ctrl(\n ^~~~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task3/top.v:97: Cannot find file containing module: \'SRAM\'\n SRAM USRAM(\n ^~~~\n%Error: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task3/top.v:112: Cannot find file containing module: \'GPU\'\n    GPU UGPU(\n    ^~~\n%Error: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task3/top.v:119: Cannot find file containing module: \'segMsg\'\n segMsg UsegMsg_f(\n ^~~~~~\n%Error: data/full_repos/permissive/434840709/USTB_digital_logic_homework/task3/top.v:125: Cannot find file containing module: \'segMsg\'\n segMsg UsegMsg_b(\n ^~~~~~\n%Error: Exiting due to 11 error(s), 1 warning(s)\n'
module top(
input 				clk100mhz,
input 				clr,
input				key_rd,
input				key_wei,
input				key_shuzi,
input				key_enter,
input				key_input,
input				key_disp,
output 		[3:0] 	pos_f,
output 		[7:0] 	seg_f,
output 		[3:0] 	pos_b,
output 		[7:0] 	seg_b,

output				sram_we_n,
output				sram_oe_n,
output				sram_ce_n,
output				sram_ub_n,
output				sram_lb_n,
inout		[15:0]		sram_data,
output		[18:0]		sram_addr

    );

    wire clk190hz,clk3hz;
    wire 	[15:0]	dataBus_f;
	wire	[3:0]	pos_f_tmp;
	wire	[15:0]	dataBus_b;
	wire	[3:0]	pos_b_tmp;
	wire	[31:0]	disp_data;
	wire	[31:0]	disp_data_b;
	wire	[3:0]	shuzi;
	wire	[3:0]	weishu;
	wire			disp_data_en;
	wire	[31:0]	disp_data_out;
	reg				key_rd_ff1;
	reg				key_rd_ff2;
	assign	dataBus_f={weishu,4'h0,shuzi,4'h0};

	assign	pos_f={pos_f_tmp[3],1'b0,pos_f_tmp[1],1'b0};
	assign	pos_b={pos_b_tmp[0],pos_b_tmp[1],pos_b_tmp[2],pos_b_tmp[3]};
	always@(posedge clk3hz)key_rd_ff1<=key_rd;
	always@(posedge clk3hz)key_rd_ff2<=key_rd_ff1;
	assign	key_rd_rise=key_rd_ff1&(key_rd_ff2==0);

	
	clkDiv U1(clk100mhz,clk190hz,clk3hz,clk10m);
	key_xd Ukey_wei_xd(
	.clk			(clk10m),
	.rst_n			(clr),
	.key_in			(key_wei),
	.key_out        (key_wei_out)
		);
	key_xd Ukey_enter_xd(
	.clk			(clk10m),
	.rst_n			(clr),
	.key_in			(key_enter),
	.key_out        (key_enter_out)
		);
	key_xd Ukey_input_xd(
	.clk			(clk10m),
	.rst_n			(clr),
	.key_in			(key_input),
	.key_out        (key_input_out)
		);
	key_xd Ukey_shuzi_xd(
	.clk			(clk10m),
	.rst_n			(clr),
	.key_in			(key_shuzi),
	.key_out        (key_shuzi_out)
		);
	key_xd Ukey_disp_xd(
	.clk			(clk10m),
	.rst_n			(clr),
	.key_in			(key_disp),
	.key_out        (key_disp_out)
		);
	key_ctrl Ukey_ctrl(
	.clk			(clk10m),
	.rst_n			(clr),
	.key_wei		(key_wei_out	),
	.key_shuzi		(key_shuzi_out	),
	.key_enter		(key_enter_out	),
	.key_input		(key_input_out	),
	.key_disp		(key_disp_out	),
	.weishu			(weishu),
	.shuzi			(shuzi),
	.disp_data		(disp_data_b),
	.disp_data_en	(disp_data_en)
);
	SRAM USRAM(
	.ctr_r			(key_rd_rise),
	.ctr_w			(key_disp_out),
	.clk			(clk10m),
	.data_in		(disp_data_b),
	.databus		(sram_data),
	.addrbus		(sram_addr),
	.data_out		(disp_data_out),
	.data_out_vld	(data_out_vld),
	.we				(sram_we_n),
	.oe				(sram_oe_n),
	.ce				(sram_ce_n),
	.ub				(sram_ub_n),
	.lb				(sram_lb_n)
	);
    GPU UGPU(
	.clk3hz			(clk3hz),
	.clr			(clr),
	.disp_data_en	(data_out_vld),
	.datain			(disp_data_out),
	.dataBus    	(dataBus_b)
    );
	segMsg UsegMsg_f(
	.clk190hz		(clk190hz),
	.dataBus		(dataBus_f),
	.pos			(pos_f_tmp),
	.seg            (seg_f)
    );
	segMsg UsegMsg_b(
	.clk190hz		(clk190hz),
	.dataBus		(dataBus_b),
	.pos			(pos_b_tmp),
	.seg            (seg_b)
    );
endmodule
module top(
input 				clk100mhz,
input 				clr,
input				key_rd,
input				key_wei,
input				key_shuzi,
input				key_enter,
input				key_input,
input				key_disp,
output 		[3:0] 	pos_f,
output 		[7:0] 	seg_f,
output 		[3:0] 	pos_b,
output 		[7:0] 	seg_b,

output				sram_we_n,
output				sram_oe_n,
output				sram_ce_n,
output				sram_ub_n,
output				sram_lb_n,
inout		[15:0]		sram_data,
output		[18:0]		sram_addr

    );


    wire clk190hz,clk3hz;
    wire 	[15:0]	dataBus_f;
	wire	[3:0]	pos_f_tmp;
	wire	[15:0]	dataBus_b;
	wire	[3:0]	pos_b_tmp;
	wire	[31:0]	disp_data;
	wire	[31:0]	disp_data_b;
	wire	[3:0]	shuzi;
	wire	[3:0]	weishu;
	wire			disp_data_en;
	wire	[31:0]	disp_data_out;
	reg				key_rd_ff1;
	reg				key_rd_ff2;
	assign	dataBus_f={weishu,4'h0,shuzi,4'h0};

	assign	pos_f={pos_f_tmp[3],1'b0,pos_f_tmp[1],1'b0};
	assign	pos_b={pos_b_tmp[0],pos_b_tmp[1],pos_b_tmp[2],pos_b_tmp[3]};
	always@(posedge clk3hz)key_rd_ff1<=key_rd;
	always@(posedge clk3hz)key_rd_ff2<=key_rd_ff1;
	assign	key_rd_rise=key_rd_ff1&(key_rd_ff2==0);

	
	clkDiv U1(clk100mhz,clk190hz,clk3hz,clk10m);
	key_xd Ukey_wei_xd(
	.clk			(clk10m),
	.rst_n			(clr),
	.key_in			(key_wei),
	.key_out        (key_wei_out)
		);
	key_xd Ukey_enter_xd(
	.clk			(clk10m),
	.rst_n			(clr),
	.key_in			(key_enter),
	.key_out        (key_enter_out)
		);
	key_xd Ukey_input_xd(
	.clk			(clk10m),
	.rst_n			(clr),
	.key_in			(key_input),
	.key_out        (key_input_out)
		);
	key_xd Ukey_shuzi_xd(
	.clk			(clk10m),
	.rst_n			(clr),
	.key_in			(key_shuzi),
	.key_out        (key_shuzi_out)
		);
	key_xd Ukey_disp_xd(
	.clk			(clk10m),
	.rst_n			(clr),
	.key_in			(key_disp),
	.key_out        (key_disp_out)
		);
	key_ctrl Ukey_ctrl(
	.clk			(clk10m),
	.rst_n			(clr),
	.key_wei		(key_wei_out	),
	.key_shuzi		(key_shuzi_out	),
	.key_enter		(key_enter_out	),
	.key_input		(key_input_out	),
	.key_disp		(key_disp_out	),
	.weishu			(weishu),
	.shuzi			(shuzi),
	.disp_data		(disp_data_b),
	.disp_data_en	(disp_data_en)
);
	SRAM USRAM(
	.ctr_r			(key_rd_rise),
	.ctr_w			(key_disp_out),
	.clk			(clk10m),
	.data_in		(disp_data_b),
	.databus		(sram_data),
	.addrbus		(sram_addr),
	.data_out		(disp_data_out),
	.data_out_vld	(data_out_vld),
	.we				(sram_we_n),
	.oe				(sram_oe_n),
	.ce				(sram_ce_n),
	.ub				(sram_ub_n),
	.lb				(sram_lb_n)
	);
    GPU UGPU(
	.clk3hz			(clk3hz),
	.clr			(clr),
	.disp_data_en	(data_out_vld),
	.datain			(disp_data_out),
	.dataBus    	(dataBus_b)
    );
	segMsg UsegMsg_f(
	.clk190hz		(clk190hz),
	.dataBus		(dataBus_f),
	.pos			(pos_f_tmp),
	.seg            (seg_f)
    );
	segMsg UsegMsg_b(
	.clk190hz		(clk190hz),
	.dataBus		(dataBus_b),
	.pos			(pos_b_tmp),
	.seg            (seg_b)
    );
endmodule