data/full_repos/permissive/458737381/src/verilog-parser/tests/delay_example.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/delay_example.v:21: Unsupported or unknown PLI call: $monitor\n  $monitor (\n  ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/delay_example.v:26: Unsupported: Ignoring delay on this delayed statement.\n  #10 b = 1;\n  ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/delay_example.v:27: Unsupported: Ignoring delay on this delayed statement.\n  #10 c = 1;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/delay_example.v:28: Unsupported: Ignoring delay on this delayed statement.\n  #10 b = 0;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/458737381/src/verilog-parser/tests/delay_example.v:29: Unsupported: Ignoring delay on this delayed statement.\n  #10 $finish;\n  ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module delay_example();

wire out1,out2,out3,out4,out5,out6;
reg b,c;


or     #5                   u_or     (out1,b,c);

and    #(1,2)               u_and    (out2,b,c);

nor    #(1,2,3)             u_nor    (out3,b,c);

nand   #(1:2:3)             u_nand   (out4,b,c);

buf    #(1:4:8,4:5:6)       u_buf    (out5,b);

notif1 #(1:2:3,4:5:6,7:8:9) u_notif1 (out6,b,c);


initial begin
  $monitor (
  "Time=%g b=%b c=%b  out1=%b out2=%b out3=%b out4=%b out5=%b out6=%b", 
    $time, b, c , out1, out2, out3, out4, out5, out6); 
  b = 0;
  c = 0;
  #10 b = 1;
  #10 c = 1;
  #10 b = 0;
  #10 $finish;
end	

endmodule
module delay_example();


wire out1,out2,out3,out4,out5,out6;
reg b,c;


or     #5                   u_or     (out1,b,c);

and    #(1,2)               u_and    (out2,b,c);

nor    #(1,2,3)             u_nor    (out3,b,c);

nand   #(1:2:3)             u_nand   (out4,b,c);

buf    #(1:4:8,4:5:6)       u_buf    (out5,b);

notif1 #(1:2:3,4:5:6,7:8:9) u_notif1 (out6,b,c);


initial begin
  $monitor (
  "Time=%g b=%b c=%b  out1=%b out2=%b out3=%b out4=%b out5=%b out6=%b", 
    $time, b, c , out1, out2, out3, out4, out5, out6); 
  b = 0;
  c = 0;
  #10 b = 1;
  #10 c = 1;
  #10 b = 0;
  #10 $finish;
end	

endmodule