data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro/convclk_grayffctrl.v
1: b"%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro/convclk_grayffctrl.v:106: Cannot find file containing module: 'fflopx'\nfflopx #(FSHW+1) flxfifoflush_c2w_sh\n^~~~~~\n        ... Looked in:\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro,data/full_repos/permissive/530013823/fflopx\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro,data/full_repos/permissive/530013823/fflopx.v\n             data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro,data/full_repos/permissive/530013823/fflopx.sv\n             fflopx\n             fflopx.v\n             fflopx.sv\n             obj_dir/fflopx\n             obj_dir/fflopx.v\n             obj_dir/fflopx.sv\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro/convclk_grayffctrl.v:109: Cannot find file containing module: 'fflopx'\nfflopx #(FSHW+1) flxfifoflush_r2w_sh\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro/convclk_grayffctrl.v:112: Cannot find file containing module: 'fflopx'\nfflopx #(FSHW+1) flxfifoflush_c2r_sh\n^~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro/convclk_grayffctrl.v:115: Cannot find file containing module: 'convclk_grayffwr'\nconvclk_grayffwr #(ADDRB)   write_control\n^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/macro/convclk_grayffctrl.v:131: Cannot find file containing module: 'convclk_grayffrd'\nconvclk_grayffrd #(ADDRB)   read_control\n^~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n"
module convclk_grayffctrl
    (
     wrclk,
     rdclk,
     wrrst_,
     rdrst_,

     fifowr,
     fiford,
     
     fifoflush,
     oflushrd,
     oflushwr,
     
     fifofull,
     half_full,
     fifonemp,

     rdfifolen,
     wrfifolen,
     
     write,
     wraddr,
     read,
     rdaddr
     
     );



parameter   ADDRB = 4;
parameter   LENGTH = 16;
parameter   FSHW = 2;



input               wrclk;
input               rdclk;
input               wrrst_;
input               rdrst_;

input               fifowr;
input               fiford;

input               fifoflush;
output              oflushrd;
output              oflushwr;

output              fifofull;
output              half_full;
output              fifonemp;

output [ADDRB:0]    rdfifolen;
output [ADDRB:0]    wrfifolen;

output              write;
output [ADDRB-1:0]  wraddr;
output              read;
output [ADDRB-1:0]  rdaddr;






wire [ADDRB:0]      wrpnt_gray,rdpnt_gray;

wire [FSHW:0]       fifoflush_c2w_sh;
wire [FSHW:0]       fifoflush_r2w_sh;
wire [FSHW:0]       fifoflush_c2r_sh;
wire                flush_c2w = fifoflush_c2w_sh[FSHW];
wire                flush_r2w = fifoflush_r2w_sh[FSHW];
wire                flush_c2r = fifoflush_c2r_sh[FSHW];
wire                flush_x2w = flush_c2w | flush_r2w;
wire                oflushwr  = flush_x2w;
wire                oflushrd  = flush_c2r;

fflopx #(FSHW+1) flxfifoflush_c2w_sh
    (wrclk,wrrst_,{fifoflush_c2w_sh[FSHW-1:0],fifoflush},fifoflush_c2w_sh);

fflopx #(FSHW+1) flxfifoflush_r2w_sh
    (wrclk,wrrst_,{fifoflush_r2w_sh[FSHW-1:0],flush_c2r},fifoflush_r2w_sh);

fflopx #(FSHW+1) flxfifoflush_c2r_sh
    (rdclk,rdrst_,{fifoflush_c2r_sh[FSHW-1:0],fifoflush},fifoflush_c2r_sh);

convclk_grayffwr #(ADDRB)   write_control
    (

     .wrclk                             (wrclk),
     .wrrst_                            (wrrst_),
     .fifowr                            (fifowr),
     .fifoflush                         (flush_x2w),
     .fifofull                          (fifofull),
     .half_full                         (half_full),
     .wrfifolen                         (wrfifolen),
     .wrpnt_gray                        (wrpnt_gray[ADDRB:0]),
     .write                             (write),
     .wraddr                            (wraddr[ADDRB-1:0]),
     .rdpnt_gray                        (rdpnt_gray[ADDRB:0])
    );

convclk_grayffrd #(ADDRB)   read_control
    (

     .rdclk                             (rdclk),
     .rdrst_                            (rdrst_),
     .fiford                            (fiford),
     .fifoflush                         (flush_c2r),
     .fifonemp                          (fifonemp),
     .rdfifolen                         (rdfifolen),
     .rdpnt_gray                        (rdpnt_gray[ADDRB:0]),
     .read                              (read),
     .rdaddr                            (rdaddr[ADDRB-1:0]),
     .wrpnt_gray                        (wrpnt_gray[ADDRB:0])
    );

endmodule
module convclk_grayffctrl
    (
     wrclk,
     rdclk,
     wrrst_,
     rdrst_,

     fifowr,
     fiford,
     
     fifoflush,
     oflushrd,
     oflushwr,
     
     fifofull,
     half_full,
     fifonemp,

     rdfifolen,
     wrfifolen,
     
     write,
     wraddr,
     read,
     rdaddr
     
     );




parameter   ADDRB = 4;
parameter   LENGTH = 16;
parameter   FSHW = 2;



input               wrclk;
input               rdclk;
input               wrrst_;
input               rdrst_;

input               fifowr;
input               fiford;

input               fifoflush;
output              oflushrd;
output              oflushwr;

output              fifofull;
output              half_full;
output              fifonemp;

output [ADDRB:0]    rdfifolen;
output [ADDRB:0]    wrfifolen;

output              write;
output [ADDRB-1:0]  wraddr;
output              read;
output [ADDRB-1:0]  rdaddr;






wire [ADDRB:0]      wrpnt_gray,rdpnt_gray;

wire [FSHW:0]       fifoflush_c2w_sh;
wire [FSHW:0]       fifoflush_r2w_sh;
wire [FSHW:0]       fifoflush_c2r_sh;
wire                flush_c2w = fifoflush_c2w_sh[FSHW];
wire                flush_r2w = fifoflush_r2w_sh[FSHW];
wire                flush_c2r = fifoflush_c2r_sh[FSHW];
wire                flush_x2w = flush_c2w | flush_r2w;
wire                oflushwr  = flush_x2w;
wire                oflushrd  = flush_c2r;

fflopx #(FSHW+1) flxfifoflush_c2w_sh
    (wrclk,wrrst_,{fifoflush_c2w_sh[FSHW-1:0],fifoflush},fifoflush_c2w_sh);

fflopx #(FSHW+1) flxfifoflush_r2w_sh
    (wrclk,wrrst_,{fifoflush_r2w_sh[FSHW-1:0],flush_c2r},fifoflush_r2w_sh);

fflopx #(FSHW+1) flxfifoflush_c2r_sh
    (rdclk,rdrst_,{fifoflush_c2r_sh[FSHW-1:0],fifoflush},fifoflush_c2r_sh);

convclk_grayffwr #(ADDRB)   write_control
    (

     .wrclk                             (wrclk),
     .wrrst_                            (wrrst_),
     .fifowr                            (fifowr),
     .fifoflush                         (flush_x2w),
     .fifofull                          (fifofull),
     .half_full                         (half_full),
     .wrfifolen                         (wrfifolen),
     .wrpnt_gray                        (wrpnt_gray[ADDRB:0]),
     .write                             (write),
     .wraddr                            (wraddr[ADDRB-1:0]),
     .rdpnt_gray                        (rdpnt_gray[ADDRB:0])
    );

convclk_grayffrd #(ADDRB)   read_control
    (

     .rdclk                             (rdclk),
     .rdrst_                            (rdrst_),
     .fiford                            (fiford),
     .fifoflush                         (flush_c2r),
     .fifonemp                          (fifonemp),
     .rdfifolen                         (rdfifolen),
     .rdpnt_gray                        (rdpnt_gray[ADDRB:0]),
     .read                              (read),
     .rdaddr                            (rdaddr[ADDRB-1:0]),
     .wrpnt_gray                        (wrpnt_gray[ADDRB:0])
    );

endmodule