data/full_repos/permissive/493212017/blink/dffBehavioral.v
1: b"%Error-PROCASSWIRE: data/full_repos/permissive/493212017/blink/dffBehavioral.v:11: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Q'\n                                                                                 : ... In instance dff\n   Q <= 1'b0;\n   ^\n%Error-PROCASSWIRE: data/full_repos/permissive/493212017/blink/dffBehavioral.v:13: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'Q'\n                                                                                 : ... In instance dff\n   Q <= D;\n   ^\n%Error: Exiting due to 2 error(s)\n        ... See the manual and https://verilator.org for more assistance.\n"
module dff(
		input	D,
		input	clk,
		input	rst,
		output	Q
	);

	always @ (posedge(clk), posedge(rst))
	begin
		if (rst == 1)
			Q <= 1'b0;
		else
			Q <= D;
	end
endmodule
module dff(
		input	D,
		input	clk,
		input	rst,
		output	Q
	);


	always @ (posedge(clk), posedge(rst))
	begin
		if (rst == 1)
			Q <= 1'b0;
		else
			Q <= D;
	end
endmodule