data/full_repos/permissive/518685803/iiitb__RISCV_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/518685803/iiitb__RISCV_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\nalways #10 clk=!clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/518685803/iiitb__RISCV_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\nreset =0;#5;reset=1;#5;reset =0;\n         ^\n%Warning-STMTDLY: data/full_repos/permissive/518685803/iiitb__RISCV_tb.v:17: Unsupported: Ignoring delay on this delayed statement.\nreset =0;#5;reset=1;#5;reset =0;\n                    ^\n%Warning-STMTDLY: data/full_repos/permissive/518685803/iiitb__RISCV_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\ninitial #1000 $finish;\n        ^\n%Error: data/full_repos/permissive/518685803/iiitb__RISCV_tb.v:9: Cannot find file containing module: \'iiitb_RISCV\'\niiitb_RISCV riscv(clk,WB1_OUT,PC,reset);\n^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/518685803,data/full_repos/permissive/518685803/iiitb_RISCV\n             data/full_repos/permissive/518685803,data/full_repos/permissive/518685803/iiitb_RISCV.v\n             data/full_repos/permissive/518685803,data/full_repos/permissive/518685803/iiitb_RISCV.sv\n             iiitb_RISCV\n             iiitb_RISCV.v\n             iiitb_RISCV.sv\n             obj_dir/iiitb_RISCV\n             obj_dir/iiitb_RISCV.v\n             obj_dir/iiitb_RISCV.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module RISCV32Itb;

reg clk,reset;
integer k;

wire [31:0]WB1_OUT,PC;

iiitb_RISCV riscv(clk,WB1_OUT,PC,reset);

initial clk=1'b0;

always #10 clk=!clk;


initial begin
reset =0;#5;reset=1;#5;reset =0;
end
initial #1000 $finish;
endmodule
module RISCV32Itb;


reg clk,reset;
integer k;

wire [31:0]WB1_OUT,PC;

iiitb_RISCV riscv(clk,WB1_OUT,PC,reset);

initial clk=1'b0;

always #10 clk=!clk;


initial begin
reset =0;#5;reset=1;#5;reset =0;
end
initial #1000 $finish;
endmodule