data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sim_1/new/testbench.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sim_1/new/testbench.v:10: Unsupported: Ignoring delay on this delayed statement.\n    always #1 clock = ~clock;\n           ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sim_1/new/testbench.v:20: Cannot find file containing module: \'top\'\n    top t(clock, sw, leds, seg, anode);\n    ^~~\n        ... Looked in:\n             data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sim_1/new,data/full_repos/permissive/464120924/top\n             data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sim_1/new,data/full_repos/permissive/464120924/top.v\n             data/full_repos/permissive/464120924/Basys3_CPU/Basys3_CPU.srcs/sim_1/new,data/full_repos/permissive/464120924/top.sv\n             top\n             top.v\n             top.sv\n             obj_dir/top\n             obj_dir/top.v\n             obj_dir/top.sv\n%Error: Exiting due to 1 error(s), 1 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module testbench();
    
    reg clock = 0;
    
    
    always #1 clock = ~clock;
    
    
    reg[15:0] sw = 133;
    
    wire[15:0] leds;
    wire[6:0] seg;
    wire[3:0] anode;
    
    
    top t(clock, sw, leds, seg, anode);
    
    
endmodule
module testbench();

    
    reg clock = 0;
    
    
    always #1 clock = ~clock;
    
    
    reg[15:0] sw = 133;
    
    wire[15:0] leds;
    wire[6:0] seg;
    wire[3:0] anode;
    
    
    top t(clock, sw, leds, seg, anode);
    
    
endmodule