data/full_repos/permissive/441359809/src/yosys/tests/sva/extnets.sv
data/verilator_xmls/9718adf1-bd25-495b-9904-2a3765982913.xml
module top(input i, output o);
	A A();
	B B();
	assign A.i = i;
	assign o = B.o;
	always @* assert(o == i);
endmodule
module top(input i, output o);

	A A();
	B B();
	assign A.i = i;
	assign o = B.o;
	always @* assert(o == i);
endmodule