data/full_repos/permissive/530013823/LuanVan-20210617T090538Z-001/LuanVan/rtl/montscarmult/testtruonghopnetindex/test.v
data/verilator_xmls/81431b7a-10ff-4497-9017-b6573e827074.xml
module test
    (
     clk,
     k,
     t,
     kt
     );



input clk;
input [255:0] k;
input [7:0]   t;
output        kt;








reg           kt;

always@(posedge clk)
    begin
    kt <= k[t];
    end

endmodule
module test
    (
     clk,
     k,
     t,
     kt
     );




input clk;
input [255:0] k;
input [7:0]   t;
output        kt;








reg           kt;

always@(posedge clk)
    begin
    kt <= k[t];
    end

endmodule