data/full_repos/permissive/456762006/testbench/LineAlign_tb.sv
1: b'%Warning-STMTDLY: data/full_repos/permissive/456762006/testbench/LineAlign_tb.sv:34: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n       ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/456762006/testbench/LineAlign_tb.sv:40: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/456762006/testbench/LineAlign_tb.sv:42: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Error: data/full_repos/permissive/456762006/testbench/LineAlign_tb.sv:48: syntax error, unexpected \'@\'\n                        @(posedge clk);\n                        ^\n%Warning-STMTDLY: data/full_repos/permissive/456762006/testbench/LineAlign_tb.sv:49: Unsupported: Ignoring delay on this delayed statement.\n                        #2 \n                        ^\n%Error: data/full_repos/permissive/456762006/testbench/LineAlign_tb.sv:56: syntax error, unexpected \'@\'\n        @(posedge clk);\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/456762006/testbench/LineAlign_tb.sv:58: Unsupported: Ignoring delay on this delayed statement.\n        #2000 $finish;\n        ^\n%Error: Exiting due to 2 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module LineAlign_tb;
bit clk;
bit arstn;
bit [13:0]data_in;
bit datain_valid;
wire [3*14-1:0]data_out;
wire dataout_valid;
wire [13:0]data_out0;
wire [13:0]data_out1;
wire [13:0]data_out2;
integer i,j;
always #5 clk = ~clk;
initial
    begin
        datain_valid = 1'b0;
        arstn = 1'b1;
        data_in = 0;
        #20
        arstn = 1'b0;
        #20
        arstn = 1'b1;
        for(i=1;i<13;i=i+1)
            begin
                for(j=1;j<241;j=j+1)
                    begin
                        @(posedge clk);
                        #2 
                            data_in = j;
                            datain_valid = 1'b1;

                    end

            end
        @(posedge clk);
            datain_valid = 1'b0;
        #2000 $finish;
    end




assign data_out0[13:0] = data_out[13:0];
assign data_out1[13:0] = data_out[27:14];
assign data_out2[13:0] = data_out[41:28];
LineAlign #(
    .DATA_WIDTH(14),
    .BUFFER_DEPTH(256),
    .FIFO_WIDTH(8),
    .LINE_NUM(3),
    .IMAGE_WIDTH(240)
    
)DUT(clk,arstn,data_in,datain_valid,data_out,dataout_valid);
endmodule
module LineAlign_tb;

bit clk;
bit arstn;
bit [13:0]data_in;
bit datain_valid;
wire [3*14-1:0]data_out;
wire dataout_valid;
wire [13:0]data_out0;
wire [13:0]data_out1;
wire [13:0]data_out2;
integer i,j;
always #5 clk = ~clk;
initial
    begin
        datain_valid = 1'b0;
        arstn = 1'b1;
        data_in = 0;
        #20
        arstn = 1'b0;
        #20
        arstn = 1'b1;
        for(i=1;i<13;i=i+1)
            begin
                for(j=1;j<241;j=j+1)
                    begin
                        @(posedge clk);
                        #2 
                            data_in = j;
                            datain_valid = 1'b1;

                    end

            end
        @(posedge clk);
            datain_valid = 1'b0;
        #2000 $finish;
    end




assign data_out0[13:0] = data_out[13:0];
assign data_out1[13:0] = data_out[27:14];
assign data_out2[13:0] = data_out[41:28];
LineAlign #(
    .DATA_WIDTH(14),
    .BUFFER_DEPTH(256),
    .FIFO_WIDTH(8),
    .LINE_NUM(3),
    .IMAGE_WIDTH(240)
    
)DUT(clk,arstn,data_in,datain_valid,data_out,dataout_valid);
endmodule