data/full_repos/permissive/422421961/sort2in1_tb.v
1: b'%Error: data/full_repos/permissive/422421961/sort2in1_tb.v:18: Cannot find include file: system_init.v\n`include "system_init.v"                            \n         ^~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/422421961,data/full_repos/permissive/422421961/system_init.v\n             data/full_repos/permissive/422421961,data/full_repos/permissive/422421961/system_init.v.v\n             data/full_repos/permissive/422421961,data/full_repos/permissive/422421961/system_init.v.sv\n             system_init.v\n             system_init.v.v\n             system_init.v.sv\n             obj_dir/system_init.v\n             obj_dir/system_init.v.v\n             obj_dir/system_init.v.sv\n%Error: data/full_repos/permissive/422421961/sort2in1_tb.v:20: Cannot find include file: read_signal.v\n`include "read_signal.v"                     \n         ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422421961/sort2in1_tb.v:21: Cannot find include file: tb_clock_div.v\n`include "tb_clock_div.v"                         \n         ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422421961/sort2in1_tb.v:32: Cannot find include file: init_dump.v\n `include "init_dump.v" \n          ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/422421961/sort2in1_tb.v:38: Unsupported: Verilog 1995 force\n    force clk       = system_init.masterclock;       \n    ^~~~~\n%Error: data/full_repos/permissive/422421961/sort2in1_tb.v:39: Unsupported: Verilog 1995 force\n    force rst_x     = system_init.rst_all    ;       \n    ^~~~~\n%Error: Exiting due to 6 error(s)\n'
module sort2in1_tb 
#(parameter W =`DATA_WIDTH ) 
(
);    
                       
  reg  clk;                                          
  reg  rst_x;                                        
  wire synrst;                                      
                                                     
 `include "init_dump.v"
  system_init  system_init();                        

                                                     
  initial                                            
  begin                                              
    force clk       = system_init.masterclock;       
    force rst_x     = system_init.rst_all    ;       
  end                                                
  assign synrst = system_init.syn_rst;              
                                                     
                                                     
 wire [`DATA_WIDTH-1:0]  Data_in;                   
                                                     
	wire clkDiv160;                                     
	tb_clock_div #( 2) U_clkDiv160  ( .clk_in(clk),.rst(synrst), .clk_out(clkDiv160) );

  read_signal #(`DATA_WIDTH,`DATA_FILE,`DISPLAY_OK) U_data_in(.clk(clk),.signal_out(Data_in)); 

wire DataEn;
wire [W-1:0] DataIn;
wire [W-1:0] DataMax;    
wire [W+3:0] DataSumOut;
                                                 
assign DataEn=1;
assign DataIn=Data_in;
 
sort2in1 #(.W(12))U_sort2in1
(
    .clk               (clk          ), 
    .synrst            (synrst       ), 
    .DataEn            (DataEn       ), 
    .DataIn            (DataIn       ), 
    .DataMax           (DataMax      ), 
    .DataSumOut        (DataSumOut   ) 
    );
       
       
endmodule
module sort2in1_tb 
#(parameter W =`DATA_WIDTH ) 
(
);
    
                       
  reg  clk;                                          
  reg  rst_x;                                        
  wire synrst;                                      
                                                     
 `include "init_dump.v"
  system_init  system_init();                        

                                                     
  initial                                            
  begin                                              
    force clk       = system_init.masterclock;       
    force rst_x     = system_init.rst_all    ;       
  end                                                
  assign synrst = system_init.syn_rst;              
                                                     
                                                     
 wire [`DATA_WIDTH-1:0]  Data_in;                   
                                                     
	wire clkDiv160;                                     
	tb_clock_div #( 2) U_clkDiv160  ( .clk_in(clk),.rst(synrst), .clk_out(clkDiv160) );

  read_signal #(`DATA_WIDTH,`DATA_FILE,`DISPLAY_OK) U_data_in(.clk(clk),.signal_out(Data_in)); 

wire DataEn;
wire [W-1:0] DataIn;
wire [W-1:0] DataMax;    
wire [W+3:0] DataSumOut;
                                                 
assign DataEn=1;
assign DataIn=Data_in;
 
sort2in1 #(.W(12))U_sort2in1
(
    .clk               (clk          ), 
    .synrst            (synrst       ), 
    .DataEn            (DataEn       ), 
    .DataIn            (DataIn       ), 
    .DataMax           (DataMax      ), 
    .DataSumOut        (DataSumOut   ) 
    );
       
       
endmodule