data/full_repos/permissive/476411617/TopTop.v
1: b'%Warning-LITENDIAN: data/full_repos/permissive/476411617/TopTop.v:53: Little bit endian vector: MSB < LSB of bit range: 0:63\nwire[0:PE_H*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] EAST_O;\n    ^\n                    ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-LITENDIAN: data/full_repos/permissive/476411617/TopTop.v:54: Little bit endian vector: MSB < LSB of bit range: 0:63\nwire[0:PE_H*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] WEST_O;\n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/476411617/TopTop.v:55: Little bit endian vector: MSB < LSB of bit range: 0:63\nwire[0:PE_W*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] SOUTH_O;\n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/476411617/TopTop.v:56: Little bit endian vector: MSB < LSB of bit range: 0:63\nwire[0:PE_W*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] NORTH_O;\n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/476411617/TopTop.v:57: Little bit endian vector: MSB < LSB of bit range: 0:63\nwire[0:PE_H*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] EAST_I;\n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/476411617/TopTop.v:58: Little bit endian vector: MSB < LSB of bit range: 0:63\nwire[0:PE_H*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] WEST_I;\n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/476411617/TopTop.v:59: Little bit endian vector: MSB < LSB of bit range: 0:63\nwire[0:PE_W*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] SOUTH_I;\n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/476411617/TopTop.v:60: Little bit endian vector: MSB < LSB of bit range: 0:63\nwire[0:PE_W*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] NORTH_I;\n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/476411617/TopTop.v:62: Little bit endian vector: MSB < LSB of bit range: 0:63\nwire[0:PE_H*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] SIG_O;\n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/476411617/TopTop.v:63: Little bit endian vector: MSB < LSB of bit range: 0:63\nwire[0:PE_H*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] TANH_O;\n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/476411617/TopTop.v:65: Little bit endian vector: MSB < LSB of bit range: 0:63\nwire[0:PE_H*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] SIG_I;\n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/476411617/TopTop.v:66: Little bit endian vector: MSB < LSB of bit range: 0:63\nwire[0:PE_H*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] TANH_I;\n    ^\n%Warning-LITENDIAN: data/full_repos/permissive/476411617/TopTop.v:68: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:PE_H*ARRAY_DIM*TILE_DIM-1] Ready_Sig;\n     ^\n%Warning-LITENDIAN: data/full_repos/permissive/476411617/TopTop.v:69: Little bit endian vector: MSB < LSB of bit range: 0:1\nwire [0:PE_H*ARRAY_DIM*TILE_DIM-1] Ready_Tanh;\n     ^\n%Error: data/full_repos/permissive/476411617/TopTop.v:71: Cannot find file containing module: \'Top\'\nTop #(ARRAY_DIM,TILE_DIM, MAX_WORD_LENGTH, Slice_Size, PE_W, PE_H) top\n^~~\n        ... Looked in:\n             data/full_repos/permissive/476411617,data/full_repos/permissive/476411617/Top\n             data/full_repos/permissive/476411617,data/full_repos/permissive/476411617/Top.v\n             data/full_repos/permissive/476411617,data/full_repos/permissive/476411617/Top.sv\n             Top\n             Top.v\n             Top.sv\n             obj_dir/Top\n             obj_dir/Top.v\n             obj_dir/Top.sv\n%Error: data/full_repos/permissive/476411617/TopTop.v:102: Cannot find file containing module: \'Sigmoid_Array\'\nSigmoid_Array #(MAX_WORD_LENGTH, PE_H*ARRAY_DIM*TILE_DIM) sig\n^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/476411617/TopTop.v:110: Cannot find file containing module: \'Tanh_Array\'\nTanh_Array #(MAX_WORD_LENGTH, PE_H*ARRAY_DIM*TILE_DIM) tanh\n^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/476411617/TopTop.v:124: Unsized constant being X/Z extended to 64 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz\n                                                                 : ... In instance TopTop\nassign NORTH_I = Activation_Function == 0? EAST_O : (Activation_Function == 1 && Ready_Sig[0] == 1\'b1)? SIG_O : (Activation_Function == 2 && Ready_Tanh[0] == 1\'b1)? TANH_O : \'hz;\n                                                                                                                                                                              ^~~\n%Error: Exiting due to 3 error(s), 15 warning(s)\n'
module TopTop #(parameter[7:0] ARRAY_DIM = 8'b01,parameter[7:0] TILE_DIM =  8'b01, parameter MAX_WORD_LENGTH = 32, parameter Slice_Size = 4, parameter PE_W = 2, parameter PE_H = 2)
(
    input clk,
    input reset,
    input start,

    input[31:0] instruction,
    input external,
    input[7:0] Tile_i,
    input[7:0] Tile_j,
    input[7:0] Block_i,
    input[7:0] Block_j,
    input WEA,
    input WEB,
    input[9:0] ADDRA,
    input[9:0] ADDRB,
    input[15:0] DIA,
    input[15:0] DIB,
    output[15:0] DOA,
    output[15:0] DOB,
    input[1:0] Activation_Function,
    input Tanh_In
    );




wire[0:PE_H*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] EAST_O;
wire[0:PE_H*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] WEST_O;
wire[0:PE_W*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] SOUTH_O;
wire[0:PE_W*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] NORTH_O;
wire[0:PE_H*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] EAST_I;
wire[0:PE_H*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] WEST_I;
wire[0:PE_W*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] SOUTH_I;
wire[0:PE_W*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] NORTH_I;

wire[0:PE_H*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] SIG_O;
wire[0:PE_H*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] TANH_O;

wire[0:PE_H*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] SIG_I;
wire[0:PE_H*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] TANH_I;

wire [0:PE_H*ARRAY_DIM*TILE_DIM-1] Ready_Sig;
wire [0:PE_H*ARRAY_DIM*TILE_DIM-1] Ready_Tanh;

Top #(ARRAY_DIM,TILE_DIM, MAX_WORD_LENGTH, Slice_Size, PE_W, PE_H) top
    (
        clk,
        reset,
        start,
        instruction,
        external,
        Tile_i,
        Tile_j,
        Block_i,
        Block_j,
        WEA,
        WEB,
        ADDRA,
        ADDRB,
        DIA,
        DIB,
        DOA,
        DOB,
        EAST_I,
        WEST_I,
        SOUTH_I,
        NORTH_I,
        EAST_O,
        WEST_O,
        SOUTH_O,
        NORTH_O
    );


assign SIG_I = EAST_O;
Sigmoid_Array #(MAX_WORD_LENGTH, PE_H*ARRAY_DIM*TILE_DIM) sig
    (
        clk,
        SIG_I,
        SIG_O,
		Ready_Sig
    );
assign TANH_I = Tanh_In == 0? EAST_O : NORTH_O;
Tanh_Array #(MAX_WORD_LENGTH, PE_H*ARRAY_DIM*TILE_DIM) tanh
    (
        clk,
        TANH_I,
        TANH_O,
		Ready_Tanh
    );


assign WEST_I = 0;
assign EAST_I = 0;
assign SOUTH_I = 0;


assign NORTH_I = Activation_Function == 0? EAST_O : (Activation_Function == 1 && Ready_Sig[0] == 1'b1)? SIG_O : (Activation_Function == 2 && Ready_Tanh[0] == 1'b1)? TANH_O : 'hz;













endmodule
module TopTop #(parameter[7:0] ARRAY_DIM = 8'b01,parameter[7:0] TILE_DIM =  8'b01, parameter MAX_WORD_LENGTH = 32, parameter Slice_Size = 4, parameter PE_W = 2, parameter PE_H = 2)
(
    input clk,
    input reset,
    input start,

    input[31:0] instruction,
    input external,
    input[7:0] Tile_i,
    input[7:0] Tile_j,
    input[7:0] Block_i,
    input[7:0] Block_j,
    input WEA,
    input WEB,
    input[9:0] ADDRA,
    input[9:0] ADDRB,
    input[15:0] DIA,
    input[15:0] DIB,
    output[15:0] DOA,
    output[15:0] DOB,
    input[1:0] Activation_Function,
    input Tanh_In
    );





wire[0:PE_H*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] EAST_O;
wire[0:PE_H*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] WEST_O;
wire[0:PE_W*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] SOUTH_O;
wire[0:PE_W*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] NORTH_O;
wire[0:PE_H*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] EAST_I;
wire[0:PE_H*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] WEST_I;
wire[0:PE_W*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] SOUTH_I;
wire[0:PE_W*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] NORTH_I;

wire[0:PE_H*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] SIG_O;
wire[0:PE_H*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] TANH_O;

wire[0:PE_H*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] SIG_I;
wire[0:PE_H*ARRAY_DIM*TILE_DIM*MAX_WORD_LENGTH-1] TANH_I;

wire [0:PE_H*ARRAY_DIM*TILE_DIM-1] Ready_Sig;
wire [0:PE_H*ARRAY_DIM*TILE_DIM-1] Ready_Tanh;

Top #(ARRAY_DIM,TILE_DIM, MAX_WORD_LENGTH, Slice_Size, PE_W, PE_H) top
    (
        clk,
        reset,
        start,
        instruction,
        external,
        Tile_i,
        Tile_j,
        Block_i,
        Block_j,
        WEA,
        WEB,
        ADDRA,
        ADDRB,
        DIA,
        DIB,
        DOA,
        DOB,
        EAST_I,
        WEST_I,
        SOUTH_I,
        NORTH_I,
        EAST_O,
        WEST_O,
        SOUTH_O,
        NORTH_O
    );


assign SIG_I = EAST_O;
Sigmoid_Array #(MAX_WORD_LENGTH, PE_H*ARRAY_DIM*TILE_DIM) sig
    (
        clk,
        SIG_I,
        SIG_O,
		Ready_Sig
    );
assign TANH_I = Tanh_In == 0? EAST_O : NORTH_O;
Tanh_Array #(MAX_WORD_LENGTH, PE_H*ARRAY_DIM*TILE_DIM) tanh
    (
        clk,
        TANH_I,
        TANH_O,
		Ready_Tanh
    );


assign WEST_I = 0;
assign EAST_I = 0;
assign SOUTH_I = 0;


assign NORTH_I = Activation_Function == 0? EAST_O : (Activation_Function == 1 && Ready_Sig[0] == 1'b1)? SIG_O : (Activation_Function == 2 && Ready_Tanh[0] == 1'b1)? TANH_O : 'hz;













endmodule