data/full_repos/permissive/49522715/rtl/testbench/tb_top.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/49522715/rtl/testbench/tb_top.v:22: Unsupported: Ignoring delay on this delayed statement.\n    forever #10 clk <= ~clk;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/49522715/rtl/testbench/tb_top.v:27: Unsupported: Ignoring delay on this delayed statement.\n    #120 reset <= 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/49522715/rtl/testbench/tb_top.v:32: Unsupported: Ignoring delay on this delayed statement.\n    #2000 init_done <= 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/49522715/rtl/testbench/tb_top.v:36: Unsupported: Ignoring delay on this delayed statement.\n    #2000000 $finish;\n    ^\n%Error: data/full_repos/permissive/49522715/rtl/testbench/tb_top.v:45: Cannot find file containing module: \'lcd_control\'\n  lcd_control lcd_control(\n  ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/49522715/rtl/testbench,data/full_repos/permissive/49522715/lcd_control\n             data/full_repos/permissive/49522715/rtl/testbench,data/full_repos/permissive/49522715/lcd_control.v\n             data/full_repos/permissive/49522715/rtl/testbench,data/full_repos/permissive/49522715/lcd_control.sv\n             lcd_control\n             lcd_control.v\n             lcd_control.sv\n             obj_dir/lcd_control\n             obj_dir/lcd_control.v\n             obj_dir/lcd_control.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module tb_top();

  reg clk, reset, init_done;
  wire [3:0] sf_d;
  wire sf_ceo;
  wire [7:0] led;
  wire lcd_e, lcd_rs, lcd_rw;

  initial $display("LCD_CONTROLLER tb_top");


  initial begin
    clk <= 0;
    forever #10 clk <= ~clk;
  end

  initial begin
    reset <= 1'b0;
    #120 reset <= 1'b1;
  end

  initial begin 
    init_done <= 1'b0;
    #2000 init_done <= 1'b1;
  end

  initial begin
    #2000000 $finish;
  end

`ifdef DUMPS
  initial $display("Dumping enabled");
  initial $dumpvars;
`endif


  lcd_control lcd_control(
	      .clk(clk),
	      .reset(reset),
	      .init_done(init_done),

	      .sf_d(sf_d),
	      .sf_ceo(sf_ceo),

	      .led(led),
	      .lcd_e(lcd_e),
	      .lcd_rs(lcd_rs),
	      .lcd_rw(lcd_rw));


endmodule
module tb_top();


  reg clk, reset, init_done;
  wire [3:0] sf_d;
  wire sf_ceo;
  wire [7:0] led;
  wire lcd_e, lcd_rs, lcd_rw;

  initial $display("LCD_CONTROLLER tb_top");


  initial begin
    clk <= 0;
    forever #10 clk <= ~clk;
  end

  initial begin
    reset <= 1'b0;
    #120 reset <= 1'b1;
  end

  initial begin 
    init_done <= 1'b0;
    #2000 init_done <= 1'b1;
  end

  initial begin
    #2000000 $finish;
  end

`ifdef DUMPS
  initial $display("Dumping enabled");
  initial $dumpvars;
`endif


  lcd_control lcd_control(
	      .clk(clk),
	      .reset(reset),
	      .init_done(init_done),

	      .sf_d(sf_d),
	      .sf_ceo(sf_ceo),

	      .led(led),
	      .lcd_e(lcd_e),
	      .lcd_rs(lcd_rs),
	      .lcd_rw(lcd_rw));


endmodule