data/full_repos/permissive/458134463/Modules/DataMemory.v
data/verilator_xmls/5b7d5a96-5a9e-4fc8-bf1b-0d46afe5706d.xml
module DataMemory(MemWrite, MemRead, address, write_data, read_data, clock);

input MemWrite, MemRead;
input clock;
input [31:0] address;
input [31:0] write_data;

output reg [31:0] read_data;

reg [31:0] memory [31:0];

always @(posedge clock) begin
	if(MemWrite == 1)
		memory[address] = write_data[31:0];
end

always @(clock) begin
	if(MemRead == 1)
		read_data[31:0] = memory[address];
end


endmodule
module DataMemory(MemWrite, MemRead, address, write_data, read_data, clock);


input MemWrite, MemRead;
input clock;
input [31:0] address;
input [31:0] write_data;

output reg [31:0] read_data;

reg [31:0] memory [31:0];

always @(posedge clock) begin
	if(MemWrite == 1)
		memory[address] = write_data[31:0];
end

always @(clock) begin
	if(MemRead == 1)
		read_data[31:0] = memory[address];
end


endmodule