data/full_repos/permissive/492776038/verilog/dv/gpio/gpio_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/492776038/verilog/dv/gpio/gpio_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n always #12.5 clock <= (clock === 1\'b0);\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/492776038/verilog/dv/gpio/gpio_tb.v:45: Unsupported or unknown PLI call: $dumpfile\n  $dumpfile("gpio.vcd");\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/492776038/verilog/dv/gpio/gpio_tb.v:46: Unsupported or unknown PLI call: $dumpvars\n  $dumpvars(0, gpio_tb);\n  ^~~~~~~~~\n%Error: data/full_repos/permissive/492776038/verilog/dv/gpio/gpio_tb.v:50: syntax error, unexpected \'@\'\n   repeat (1000) @(posedge clock);\n                 ^\n%Error: data/full_repos/permissive/492776038/verilog/dv/gpio/gpio_tb.v:65: Unsupported: wait statements\n  wait(mprj_io[36-1:12] == 24\'hFFFFFF);\n  ^~~~\n%Error: data/full_repos/permissive/492776038/verilog/dv/gpio/gpio_tb.v:66: Unsupported: wait statements\n  wait(mprj_io[36-1:12] == 24\'h0);\n  ^~~~\n%Error: data/full_repos/permissive/492776038/verilog/dv/gpio/gpio_tb.v:67: Unsupported: wait statements\n  wait(mprj_io[36-1:12] == 24\'hFFFFFF);\n  ^~~~\n%Error: data/full_repos/permissive/492776038/verilog/dv/gpio/gpio_tb.v:68: Unsupported: wait statements\n  wait(mprj_io[36-1:12] == 24\'h0);\n  ^~~~\n%Error: data/full_repos/permissive/492776038/verilog/dv/gpio/gpio_tb.v:69: Unsupported: wait statements\n  wait(mprj_io[36-1:12] == 24\'hFFFFFF);\n  ^~~~\n%Error: data/full_repos/permissive/492776038/verilog/dv/gpio/gpio_tb.v:70: Unsupported: wait statements\n  wait(mprj_io[36-1:12] == 24\'h0);\n  ^~~~\n%Error: data/full_repos/permissive/492776038/verilog/dv/gpio/gpio_tb.v:71: Unsupported: wait statements\n  wait(mprj_io[36-1:12] == 24\'hFFFFFF);\n  ^~~~\n%Error: data/full_repos/permissive/492776038/verilog/dv/gpio/gpio_tb.v:72: Unsupported: wait statements\n  wait(mprj_io[36-1:12] == 24\'h0);\n  ^~~~\n%Error: data/full_repos/permissive/492776038/verilog/dv/gpio/gpio_tb.v:73: Unsupported: wait statements\n  wait(mprj_io[36-1:12] == 24\'hFFFFFF);\n  ^~~~\n%Error: data/full_repos/permissive/492776038/verilog/dv/gpio/gpio_tb.v:74: Unsupported: wait statements\n  wait(mprj_io[36-1:12] == 24\'h0);\n  ^~~~\n%Error: data/full_repos/permissive/492776038/verilog/dv/gpio/gpio_tb.v:75: Unsupported: wait statements\n  wait(mprj_io[36-1:12] == 24\'hFFFFFF);\n  ^~~~\n%Error: data/full_repos/permissive/492776038/verilog/dv/gpio/gpio_tb.v:76: Unsupported: wait statements\n  wait(mprj_io[36-1:12] == 24\'h0);\n  ^~~~\n%Error: data/full_repos/permissive/492776038/verilog/dv/gpio/gpio_tb.v:77: Unsupported: wait statements\n  wait(mprj_io[36-1:12] == 24\'hFFFFFF);\n  ^~~~\n%Error: data/full_repos/permissive/492776038/verilog/dv/gpio/gpio_tb.v:78: Unsupported: wait statements\n  wait(mprj_io[36-1:12] == 24\'h0);\n  ^~~~\n%Error: data/full_repos/permissive/492776038/verilog/dv/gpio/gpio_tb.v:79: Unsupported: wait statements\n  wait(mprj_io[36-1:12] == 24\'hFFFFFF);\n  ^~~~\n%Error: data/full_repos/permissive/492776038/verilog/dv/gpio/gpio_tb.v:80: syntax error, unexpected \'@\'\n  repeat (400) @(posedge clock);\n               ^\n%Warning-STMTDLY: data/full_repos/permissive/492776038/verilog/dv/gpio/gpio_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n  #2000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/492776038/verilog/dv/gpio/gpio_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n  #100000;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/492776038/verilog/dv/gpio/gpio_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n  #200;\n  ^\n%Warning-STMTDLY: data/full_repos/permissive/492776038/verilog/dv/gpio/gpio_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n  #200;\n  ^\n%Error: Exiting due to 19 error(s), 5 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module gpio_tb;
	reg clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

	wire gpio;
	wire [37:0] mprj_io;
	wire [7:0] mprj_io_0;
	wire [24-1:0] gpio_bits;

	assign gpio_bits = mprj_io[36-1:12];
	pullup(mprj_io[3]);                                                                                                 
    assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;




	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
	end

	initial begin
		$dumpfile("gpio.vcd");
		$dumpvars(0, gpio_tb);


		repeat (140) begin
			repeat (1000) @(posedge clock);

		end
		$display("%c[1;31m",27);
		`ifdef GL
			$display ("Monitor: Timeout, Test gpio basic WB Port (GL) FAILED!!!!!!!!!!!!!!!!!!!!!!!!!");
		`else
			$display ("Monitor: Timeout, Test in gpio basic WB Port (RTL) FAILED!!!!!!!!!!!!!!!!!!!!!");
		`endif
		$display("%c[0m",27);
		$finish;
	end

	initial begin
		$display("Monitor: GPIo basic WB Started");
		wait(mprj_io[36-1:12] == 24'hFFFFFF);
		wait(mprj_io[36-1:12] == 24'h0);
		wait(mprj_io[36-1:12] == 24'hFFFFFF);
		wait(mprj_io[36-1:12] == 24'h0);
		wait(mprj_io[36-1:12] == 24'hFFFFFF);
		wait(mprj_io[36-1:12] == 24'h0);
		wait(mprj_io[36-1:12] == 24'hFFFFFF);
		wait(mprj_io[36-1:12] == 24'h0);
		wait(mprj_io[36-1:12] == 24'hFFFFFF);
		wait(mprj_io[36-1:12] == 24'h0);
		wait(mprj_io[36-1:12] == 24'hFFFFFF);
		wait(mprj_io[36-1:12] == 24'h0);
		wait(mprj_io[36-1:12] == 24'hFFFFFF);
		wait(mprj_io[36-1:12] == 24'h0);
		wait(mprj_io[36-1:12] == 24'hFFFFFF);
		repeat (400) @(posedge clock);
		`ifdef GL
	    	$display("Monitor: gpio basic WB (GL) PASSED------------------------------");
		`else
		    $display("Monitor: gpio basic WB (RTL) PASSED-----------------------------");
		`endif
	    $finish;
	end

	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#100000;
		CSB = 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		#200;
		power1 <= 1'b1;
		#200;
		power2 <= 1'b1;
	end

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3 = power1;
	wire VDD1V8 = power2;
	wire USER_VDD3V3 = power3;
	wire USER_VDD1V8 = power4;
	wire VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda1_2  (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock    (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("gpio.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule
module gpio_tb;

	reg clock;
	reg RSTB;
	reg CSB;
	reg power1, power2;
	reg power3, power4;

	wire gpio;
	wire [37:0] mprj_io;
	wire [7:0] mprj_io_0;
	wire [24-1:0] gpio_bits;

	assign gpio_bits = mprj_io[36-1:12];
	pullup(mprj_io[3]);                                                                                                 
    assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;




	always #12.5 clock <= (clock === 1'b0);

	initial begin
		clock = 0;
	end

	initial begin
		$dumpfile("gpio.vcd");
		$dumpvars(0, gpio_tb);


		repeat (140) begin
			repeat (1000) @(posedge clock);

		end
		$display("%c[1;31m",27);
		`ifdef GL
			$display ("Monitor: Timeout, Test gpio basic WB Port (GL) FAILED!!!!!!!!!!!!!!!!!!!!!!!!!");
		`else
			$display ("Monitor: Timeout, Test in gpio basic WB Port (RTL) FAILED!!!!!!!!!!!!!!!!!!!!!");
		`endif
		$display("%c[0m",27);
		$finish;
	end

	initial begin
		$display("Monitor: GPIo basic WB Started");
		wait(mprj_io[36-1:12] == 24'hFFFFFF);
		wait(mprj_io[36-1:12] == 24'h0);
		wait(mprj_io[36-1:12] == 24'hFFFFFF);
		wait(mprj_io[36-1:12] == 24'h0);
		wait(mprj_io[36-1:12] == 24'hFFFFFF);
		wait(mprj_io[36-1:12] == 24'h0);
		wait(mprj_io[36-1:12] == 24'hFFFFFF);
		wait(mprj_io[36-1:12] == 24'h0);
		wait(mprj_io[36-1:12] == 24'hFFFFFF);
		wait(mprj_io[36-1:12] == 24'h0);
		wait(mprj_io[36-1:12] == 24'hFFFFFF);
		wait(mprj_io[36-1:12] == 24'h0);
		wait(mprj_io[36-1:12] == 24'hFFFFFF);
		wait(mprj_io[36-1:12] == 24'h0);
		wait(mprj_io[36-1:12] == 24'hFFFFFF);
		repeat (400) @(posedge clock);
		`ifdef GL
	    	$display("Monitor: gpio basic WB (GL) PASSED------------------------------");
		`else
		    $display("Monitor: gpio basic WB (RTL) PASSED-----------------------------");
		`endif
	    $finish;
	end

	initial begin
		RSTB <= 1'b0;
		CSB  <= 1'b1;
		#2000;
		RSTB <= 1'b1;
		#100000;
		CSB = 1'b0;
	end

	initial begin
		power1 <= 1'b0;
		power2 <= 1'b0;
		#200;
		power1 <= 1'b1;
		#200;
		power2 <= 1'b1;
	end

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3 = power1;
	wire VDD1V8 = power2;
	wire USER_VDD3V3 = power3;
	wire USER_VDD1V8 = power4;
	wire VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vddio_2  (VDD3V3),
		.vssio	  (VSS),
		.vssio_2  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (VDD3V3),
		.vdda1_2  (VDD3V3),
		.vdda2    (VDD3V3),
		.vssa1	  (VSS),
		.vssa1_2  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (VDD1V8),
		.vccd2	  (VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock    (clock),
		.gpio     (gpio),
		.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("gpio.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule