data/full_repos/permissive/440139665/src/multiplier.v
data/verilator_xmls/693c8a6d-5762-4d80-b534-2c15b3fd0487.xml
module mixcolumn(data_in,data_out);

input [127:0] data_in;
output  [127:0] data_out;

wire  [31:0] n1,n2,n3,n4;
wire  [31:0] n_tmp_out1, n_tmp_out2, n_tmp_out3, n_tmp_out4;


wire clk = 1'b0;

assign n1 = data_in[127:96];
assign n2=data_in[95:64];
assign n3=data_in[63:32];
assign n4=data_in[31:0];

mixcolumn_32 m1 (clk,n1,n_tmp_out1);
mixcolumn_32 m2 (clk,n2,n_tmp_out2);
mixcolumn_32 m3 (clk,n3,n_tmp_out3);
mixcolumn_32 m4 (clk,n4,n_tmp_out4);

assign data_out={n_tmp_out1,n_tmp_out2,n_tmp_out3,n_tmp_out4};

endmodule
module mixcolumn(data_in,data_out);


input [127:0] data_in;
output  [127:0] data_out;

wire  [31:0] n1,n2,n3,n4;
wire  [31:0] n_tmp_out1, n_tmp_out2, n_tmp_out3, n_tmp_out4;


wire clk = 1'b0;

assign n1 = data_in[127:96];
assign n2=data_in[95:64];
assign n3=data_in[63:32];
assign n4=data_in[31:0];

mixcolumn_32 m1 (clk,n1,n_tmp_out1);
mixcolumn_32 m2 (clk,n2,n_tmp_out2);
mixcolumn_32 m3 (clk,n3,n_tmp_out3);
mixcolumn_32 m4 (clk,n4,n_tmp_out4);

assign data_out={n_tmp_out1,n_tmp_out2,n_tmp_out3,n_tmp_out4};

endmodule