data/full_repos/permissive/458737381/src/verilog-parser/tests/sparc_ifu_cmp35.v
data/verilator_xmls/7d0efe21-674f-4756-8455-7506312445ab.xml
module sparc_ifu_cmp35(

   hit, 

   a, b, valid
   );

   input [34:0] a, b;
   input 	valid;
   
   output 	hit;

   reg 		hit;
   wire 	valid;
   wire [34:0] 	a, b;

   always @ (a or b or valid)
     begin
	if ((a==b) & valid)
	  hit = 1'b1;
	else
	  hit = 1'b0;
     end

endmodule
module sparc_ifu_cmp35(

   hit, 

   a, b, valid
   );


   input [34:0] a, b;
   input 	valid;
   
   output 	hit;

   reg 		hit;
   wire 	valid;
   wire [34:0] 	a, b;

   always @ (a or b or valid)
     begin
	if ((a==b) & valid)
	  hit = 1'b1;
	else
	  hit = 1'b0;
     end

endmodule