data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv
1: b'%Error: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:26: Cannot find include file: toysram.vh\n`include "toysram.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/425063934/custom_layout/sim,data/full_repos/permissive/425063934/toysram.vh\n             data/full_repos/permissive/425063934/custom_layout/sim,data/full_repos/permissive/425063934/toysram.vh.v\n             data/full_repos/permissive/425063934/custom_layout/sim,data/full_repos/permissive/425063934/toysram.vh.sv\n             toysram.vh\n             toysram.vh.v\n             toysram.vh.sv\n             obj_dir/toysram.vh\n             obj_dir/toysram.vh.v\n             obj_dir/toysram.vh.sv\n%Error: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:33: Define or directive not defined: \'`LCBSDR_CONFIGWIDTH\'\n   logic [0:`LCBSDR_CONFIGWIDTH-1] cfg_dat;\n            ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:47: Define or directive not defined: \'`LCBSDR_CONFIGWIDTH\'\n   logic [0:`LCBSDR_CONFIGWIDTH-1] cfg;\n            ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:58: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("test_ra_sdr.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:59: Unsupported or unknown PLI call: $dumpvars\n $dumpvars (0,test_ra_sdr.lcb);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:60: Unsupported or unknown PLI call: $dumpvars\n $dumpvars (0,test_ra_sdr.cfig);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:61: Unsupported or unknown PLI call: $dumpvars\n $dumpvars (0,test_ra_sdr.bist);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:62: Unsupported or unknown PLI call: $dumpvars\n $dumpvars (0,test_ra_sdr.ra);\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:69: Unsupported: Ignoring delay on this delayed statement.\n forever #5 clk = ~clk;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:122: Unsupported: Ignoring delay on this delayed statement.\n #0   reset = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:123: Unsupported: Ignoring delay on this delayed statement.\n #0   wr_enb_0 = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:124: Unsupported: Ignoring delay on this delayed statement.\n #0   wr_adr_0 = 6\'h0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:125: Unsupported: Ignoring delay on this delayed statement.\n #0   rd_adr_0 = 6\'h0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:126: Unsupported: Ignoring delay on this delayed statement.\n #0   rd_adr_1 = 6\'h0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:127: Unsupported: Ignoring delay on this delayed statement.\n #0   rd_enb_0 = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:128: Unsupported: Ignoring delay on this delayed statement.\n #0   rd_enb_1 = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:129: Unsupported: Ignoring delay on this delayed statement.\n #0   bist_ctl = 32\'h0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:130: Unsupported: Ignoring delay on this delayed statement.\n #0   cfg_wr = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:131: Unsupported: Ignoring delay on this delayed statement.\n #0   cfg_dat = 16\'h0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:132: Unsupported: Ignoring delay on this delayed statement.\n #15  reset = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:134: Unsupported: Ignoring delay on this delayed statement.\n    #400 wr_enb_0 = 1\'b1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:135: Unsupported: Ignoring delay on this delayed statement.\n #0   wr_adr_0 = 6\'h0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:137: Unsupported: Ignoring delay on this delayed statement.\n #0   wr_adr_0 = 6\'b00_0000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:138: Unsupported: Ignoring delay on this delayed statement.\n    #0   wr_dat_0 = 6\'b00_1111;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:140: Unsupported: Ignoring delay on this delayed statement.\n    #10  wr_adr_0 = 6\'b00_0010;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:141: Unsupported: Ignoring delay on this delayed statement.\n    #0   wr_dat_0 = 6\'b00_1001;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:143: Unsupported: Ignoring delay on this delayed statement.\n #10  wr_adr_0 = 6\'b00_0100;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:144: Unsupported: Ignoring delay on this delayed statement.\n    #0   wr_dat_0 = 6\'b00_1100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:146: Unsupported: Ignoring delay on this delayed statement.\n #10  wr_adr_0 = 6\'b00_0110;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:147: Unsupported: Ignoring delay on this delayed statement.\n    #0   wr_adr_0 = 6\'b00_1101;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:149: Unsupported: Ignoring delay on this delayed statement.\n #10  wr_adr_0 = 6\'b00_1000;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:150: Unsupported: Ignoring delay on this delayed statement.\n    #0   wr_adr_0 = 6\'b00_1000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:152: Unsupported: Ignoring delay on this delayed statement.\n    #5 wr_enb_0 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:154: Unsupported: Ignoring delay on this delayed statement.\n    #5 rd_enb_0 = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:155: Unsupported: Ignoring delay on this delayed statement.\n    #0 rd_enb_1 = 1;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:157: Unsupported: Ignoring delay on this delayed statement.\n    #10 rd_adr_0 = 6\'b00_0000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:158: Unsupported: Ignoring delay on this delayed statement.\n    #0  rd_adr_1 = 6\'b00_0010;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:160: Unsupported: Ignoring delay on this delayed statement.\n    #10 rd_adr_0 = 6\'b00_0100;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:161: Unsupported: Ignoring delay on this delayed statement.\n    #0  rd_adr_1 = 6\'b00_0110;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:163: Unsupported: Ignoring delay on this delayed statement.\n    #10 rd_adr_0 = 6\'b00_1000;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:165: Unsupported: Ignoring delay on this delayed statement.\n    #5 rd_enb_0 = 0;\n    ^\n%Warning-STMTDLY: data/full_repos/permissive/425063934/custom_layout/sim/test_ra_sdr.sv:166: Unsupported: Ignoring delay on this delayed statement.\n    #0 rd_enb_1 = 0;\n    ^\n%Error: Exiting due to 8 error(s), 34 warning(s)\n'
module  test_ra_sdr ();

   logic                           clk;
   logic 			   reset;
   logic 			   cfg_wr;
   logic [0:`LCBSDR_CONFIGWIDTH-1] cfg_dat;
   logic [0:31] 		   bist_ctl;
   logic [0:31] 		   bist_status;
   logic 			   rd_enb_0;
   logic [0:5] 			   rd_adr_0;
   logic [0:71] 		   rd_dat_0;
   logic 			   rd_enb_1;
   logic [0:5] 			   rd_adr_1;
   logic [0:71] 		   rd_dat_1;
   logic 			   wr_enb_0;
   logic [0:5] 			   wr_adr_0;
   logic [0:71] 		   wr_dat_0;

   logic 			   strobe;
   logic [0:`LCBSDR_CONFIGWIDTH-1] cfg;
   logic 			   mux_rd0_enb;
   logic [0:5] 			   mux_rd0_adr;
   logic 			   mux_rd1_enb;
   logic [0:5] 			   mux_rd1_adr;
   logic 			   mux_wr0_enb;
   logic [0:5] 			   mux_wr0_adr;
   logic [0:71] 		   mux_wr0_dat;

   initial
     begin
	$dumpfile("test_ra_sdr.vcd");
	$dumpvars (0,test_ra_sdr.lcb);
	$dumpvars (0,test_ra_sdr.cfig);
	$dumpvars (0,test_ra_sdr.bist);
	$dumpvars (0,test_ra_sdr.ra);
     end


   initial
     begin
	clk = 1'b1;
	forever #5 clk = ~clk;
     end



   ra_lcb_sdr lcb (.clk      (clk),
		   .reset    (reset),
		   .cfg      (cfg),
		   .strobe   (strobe));

   ra_cfg_sdr #(.INIT(-1)) cfig (.clk (clk),
				  .reset    (reset),
				  .cfg_wr   (cfg_wr),
				  .cfg_dat  (cfg_dat),
				  .cfg      (cfg));

   ra_bist_sdr bist (.clk         (clk),
		     .reset       (reset),
		     .ctl         (bist_ctl),
		     .status      (bist_status),
		     .rd0_enb_in  (rd_enb_0),
		     .rd0_adr_in  (rd_adr_0),
		     .rd0_dat     (rd_dat_0),
		     .rd1_enb_in  (rd_enb_1),
		     .rd1_adr_in  (rd_adr_1),
		     .rd1_dat     (rd_dat_1),
		     .wr0_enb_in  (wr_enb_0),
		     .wr0_adr_in  (wr_adr_0),
		     .wr0_dat_in  (wr_dat_0),
		     .rd0_enb_out (mux_rd0_enb),
		     .rd0_adr_out (mux_rd0_adr),
		     .rd1_enb_out (mux_rd1_enb),
		     .rd1_adr_out (mux_rd1_adr),
		     .wr0_enb_out (mux_wr0_enb),
		     .wr0_adr_out (mux_wr0_adr),
		     .wr0_dat_out (mux_wr0_dat));


   ra_2r1w_64x72_sdr ra (.clk        (clk),
			 .reset      (reset),
			 .strobe     (strobe),
			 .rd_enb_0   (mux_rd0_enb),
			 .rd_adr_0   (mux_rd0_adr),
			 .rd_dat_0   (rd_dat_0),
			 .rd_enb_1   (mux_rd1_enb),
			 .rd_adr_1   (mux_rd1_adr),
			 .rd_dat_1   (rd_dat_1),
			 .wr_enb_0   (mux_wr0_enb),
			 .wr_adr_0   (mux_wr0_adr),
			 .wr_dat_0   (mux_wr0_dat));

   initial
     begin
	#0   reset = 1'b1;
	#0   wr_enb_0 = 1'b0;
	#0   wr_adr_0 = 6'h0;
	#0   rd_adr_0 = 6'h0;
	#0   rd_adr_1 = 6'h0;
	#0   rd_enb_0 = 1'b0;
	#0   rd_enb_1 = 1'b0;
	#0   bist_ctl = 32'h0;
	#0   cfg_wr = 1'b0;
	#0   cfg_dat = 16'h0;
	#15  reset = 1'b0;

   	#400 wr_enb_0 = 1'b1;
	#0   wr_adr_0 = 6'h0;

	#0   wr_adr_0 = 6'b00_0000;
    #0   wr_dat_0 = 6'b00_1111;

   	#10  wr_adr_0 = 6'b00_0010;
    #0   wr_dat_0 = 6'b00_1001;

	#10  wr_adr_0 = 6'b00_0100;
    #0   wr_dat_0 = 6'b00_1100;

	#10  wr_adr_0 = 6'b00_0110;
    #0   wr_adr_0 = 6'b00_1101;

	#10  wr_adr_0 = 6'b00_1000;
    #0   wr_adr_0 = 6'b00_1000;

    #5 wr_enb_0 = 0;

    #5 rd_enb_0 = 1;
    #0 rd_enb_1 = 1;

    #10 rd_adr_0 = 6'b00_0000;
    #0  rd_adr_1 = 6'b00_0010;

    #10 rd_adr_0 = 6'b00_0100;
    #0  rd_adr_1 = 6'b00_0110;

    #10 rd_adr_0 = 6'b00_1000;

    #5 rd_enb_0 = 0;
    #0 rd_enb_1 = 0;


     end

endmodule
module  test_ra_sdr ();


   logic                           clk;
   logic 			   reset;
   logic 			   cfg_wr;
   logic [0:`LCBSDR_CONFIGWIDTH-1] cfg_dat;
   logic [0:31] 		   bist_ctl;
   logic [0:31] 		   bist_status;
   logic 			   rd_enb_0;
   logic [0:5] 			   rd_adr_0;
   logic [0:71] 		   rd_dat_0;
   logic 			   rd_enb_1;
   logic [0:5] 			   rd_adr_1;
   logic [0:71] 		   rd_dat_1;
   logic 			   wr_enb_0;
   logic [0:5] 			   wr_adr_0;
   logic [0:71] 		   wr_dat_0;

   logic 			   strobe;
   logic [0:`LCBSDR_CONFIGWIDTH-1] cfg;
   logic 			   mux_rd0_enb;
   logic [0:5] 			   mux_rd0_adr;
   logic 			   mux_rd1_enb;
   logic [0:5] 			   mux_rd1_adr;
   logic 			   mux_wr0_enb;
   logic [0:5] 			   mux_wr0_adr;
   logic [0:71] 		   mux_wr0_dat;

   initial
     begin
	$dumpfile("test_ra_sdr.vcd");
	$dumpvars (0,test_ra_sdr.lcb);
	$dumpvars (0,test_ra_sdr.cfig);
	$dumpvars (0,test_ra_sdr.bist);
	$dumpvars (0,test_ra_sdr.ra);
     end


   initial
     begin
	clk = 1'b1;
	forever #5 clk = ~clk;
     end



   ra_lcb_sdr lcb (.clk      (clk),
		   .reset    (reset),
		   .cfg      (cfg),
		   .strobe   (strobe));

   ra_cfg_sdr #(.INIT(-1)) cfig (.clk (clk),
				  .reset    (reset),
				  .cfg_wr   (cfg_wr),
				  .cfg_dat  (cfg_dat),
				  .cfg      (cfg));

   ra_bist_sdr bist (.clk         (clk),
		     .reset       (reset),
		     .ctl         (bist_ctl),
		     .status      (bist_status),
		     .rd0_enb_in  (rd_enb_0),
		     .rd0_adr_in  (rd_adr_0),
		     .rd0_dat     (rd_dat_0),
		     .rd1_enb_in  (rd_enb_1),
		     .rd1_adr_in  (rd_adr_1),
		     .rd1_dat     (rd_dat_1),
		     .wr0_enb_in  (wr_enb_0),
		     .wr0_adr_in  (wr_adr_0),
		     .wr0_dat_in  (wr_dat_0),
		     .rd0_enb_out (mux_rd0_enb),
		     .rd0_adr_out (mux_rd0_adr),
		     .rd1_enb_out (mux_rd1_enb),
		     .rd1_adr_out (mux_rd1_adr),
		     .wr0_enb_out (mux_wr0_enb),
		     .wr0_adr_out (mux_wr0_adr),
		     .wr0_dat_out (mux_wr0_dat));


   ra_2r1w_64x72_sdr ra (.clk        (clk),
			 .reset      (reset),
			 .strobe     (strobe),
			 .rd_enb_0   (mux_rd0_enb),
			 .rd_adr_0   (mux_rd0_adr),
			 .rd_dat_0   (rd_dat_0),
			 .rd_enb_1   (mux_rd1_enb),
			 .rd_adr_1   (mux_rd1_adr),
			 .rd_dat_1   (rd_dat_1),
			 .wr_enb_0   (mux_wr0_enb),
			 .wr_adr_0   (mux_wr0_adr),
			 .wr_dat_0   (mux_wr0_dat));

   initial
     begin
	#0   reset = 1'b1;
	#0   wr_enb_0 = 1'b0;
	#0   wr_adr_0 = 6'h0;
	#0   rd_adr_0 = 6'h0;
	#0   rd_adr_1 = 6'h0;
	#0   rd_enb_0 = 1'b0;
	#0   rd_enb_1 = 1'b0;
	#0   bist_ctl = 32'h0;
	#0   cfg_wr = 1'b0;
	#0   cfg_dat = 16'h0;
	#15  reset = 1'b0;

   	#400 wr_enb_0 = 1'b1;
	#0   wr_adr_0 = 6'h0;

	#0   wr_adr_0 = 6'b00_0000;
    #0   wr_dat_0 = 6'b00_1111;

   	#10  wr_adr_0 = 6'b00_0010;
    #0   wr_dat_0 = 6'b00_1001;

	#10  wr_adr_0 = 6'b00_0100;
    #0   wr_dat_0 = 6'b00_1100;

	#10  wr_adr_0 = 6'b00_0110;
    #0   wr_adr_0 = 6'b00_1101;

	#10  wr_adr_0 = 6'b00_1000;
    #0   wr_adr_0 = 6'b00_1000;

    #5 wr_enb_0 = 0;

    #5 rd_enb_0 = 1;
    #0 rd_enb_1 = 1;

    #10 rd_adr_0 = 6'b00_0000;
    #0  rd_adr_1 = 6'b00_0010;

    #10 rd_adr_0 = 6'b00_0100;
    #0  rd_adr_1 = 6'b00_0110;

    #10 rd_adr_0 = 6'b00_1000;

    #5 rd_enb_0 = 0;
    #0 rd_enb_1 = 0;


     end

endmodule