data/full_repos/permissive/505376079/testbench/tb_nblock.sv
1: b'%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:38: syntax error, unexpected clocking\n  clocking drv_ck @(posedge aclk);\n  ^~~~~~~~\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:42: syntax error, unexpected endclocking\n  endclocking\n  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:54: Unsupported: wait statements\n    wait(intf.drv_ck.m_tvalid == 1\'b1)\n    ^~~~\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:62: syntax error, unexpected \'@\'\n    @(posedge intf.aclk);\n    ^\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:72: syntax error, unexpected \'@\'\n    @(posedge intf.aclk);\n    ^\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:78: syntax error, unexpected \'@\'\n    @(posedge intf.aclk);\n    ^\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:84: syntax error, unexpected \'@\'\n    @(posedge intf.aclk);\n    ^\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:91: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:112: Unsupported: Ignoring delay on this delayed statement.\n    #1.5625 aclk = !aclk;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:117: Unsupported: Ignoring delay on this delayed statement.\n  #15.6 aresetn <= 0;\n  ^\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:118: syntax error, unexpected \'@\'\n  repeat(5) @(posedge aclk);\n            ^\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:120: syntax error, unexpected \'@\'\n  repeat(10) @(posedge aclk);\n             ^\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:124: syntax error, unexpected \'@\'\n  repeat(5) @(posedge aclk);\n            ^\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:127: syntax error, unexpected \'@\'\n  repeat(2) @(posedge aclk);\n            ^\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:189: syntax error, unexpected \'@\'\n  repeat(20) @(posedge aclk);\n             ^\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:193: syntax error, unexpected \'@\'\n  repeat(50) @(posedge aclk);\n             ^\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:198: syntax error, unexpected \'@\'\n  repeat(20) @(posedge aclk);\n             ^\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:199: Unsupported: wait statements\n  wait ( intf.s_tready == 1\'b1);\n  ^~~~\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:208: Unsupported: fork statements\n  fork\n  ^~~~\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:210: Unsupported: wait statements\n                wait(intf.drv_ck.m_tvalid == 1\'b1)\n                ^~~~\n%Error: data/full_repos/permissive/505376079/testbench/tb_nblock.sv:250: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: Cannot continue\n'
module sim_mlp (mlp_if intf);
        
task print_result();
  shortint resut_nn;
    wait(intf.drv_ck.m_tvalid == 1'b1)
      begin
        resut_nn = intf.m_tdata;
        $display("%d \n", resut_nn);
      end
 endtask    
        
task automatic set_idle();
    @(posedge intf.aclk);
    intf.drv_ck.s_tdata <= 16'h0;
    intf.drv_ck.s_tvalid <= 1'b0;
    intf.drv_ck.set_in <= 16'h0;
    intf.drv_ck.set_en <= 1'b0;

    intf.drv_ck.w_tdata <=  32'h0;
  endtask

task automatic set_reg(input int reg_value);
    @(posedge intf.aclk);
    intf.drv_ck.set_in <= reg_value[15:0];
    intf.drv_ck.set_en <= 1'b1;
  endtask

  task automatic sent_weight(input int weight_id,input int weight_value);
    @(posedge intf.aclk);
    intf.drv_ck.w_tdata <= {weight_id[15:0],weight_value[15:0]};

  endtask

  task automatic sent_pack(input int act,input int last);
    @(posedge intf.aclk);
    intf.drv_ck.s_tdata <= act[15:0];
    intf.drv_ck.s_tvalid <= 1'b1;

    intf.drv_ck.s_tlast <=  last[0];
  endtask

endmodule
module sim_mlp (mlp_if intf);

        
task print_result();
  shortint resut_nn;
    wait(intf.drv_ck.m_tvalid == 1'b1)
      begin
        resut_nn = intf.m_tdata;
        $display("%d \n", resut_nn);
      end
 endtask    
        
task automatic set_idle();
    @(posedge intf.aclk);
    intf.drv_ck.s_tdata <= 16'h0;
    intf.drv_ck.s_tvalid <= 1'b0;
    intf.drv_ck.set_in <= 16'h0;
    intf.drv_ck.set_en <= 1'b0;

    intf.drv_ck.w_tdata <=  32'h0;
  endtask

task automatic set_reg(input int reg_value);
    @(posedge intf.aclk);
    intf.drv_ck.set_in <= reg_value[15:0];
    intf.drv_ck.set_en <= 1'b1;
  endtask

  task automatic sent_weight(input int weight_id,input int weight_value);
    @(posedge intf.aclk);
    intf.drv_ck.w_tdata <= {weight_id[15:0],weight_value[15:0]};

  endtask

  task automatic sent_pack(input int act,input int last);
    @(posedge intf.aclk);
    intf.drv_ck.s_tdata <= act[15:0];
    intf.drv_ck.s_tvalid <= 1'b1;

    intf.drv_ck.s_tlast <=  last[0];
  endtask

endmodule