data/full_repos/permissive/433389019/CTRL.v
1: b'%Error: data/full_repos/permissive/433389019/CTRL.v:1: Cannot find include file: lib/defines.vh\n`include "lib/defines.vh" \n         ^~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/433389019,data/full_repos/permissive/433389019/lib/defines.vh\n             data/full_repos/permissive/433389019,data/full_repos/permissive/433389019/lib/defines.vh.v\n             data/full_repos/permissive/433389019,data/full_repos/permissive/433389019/lib/defines.vh.sv\n             lib/defines.vh\n             lib/defines.vh.v\n             lib/defines.vh.sv\n             obj_dir/lib/defines.vh\n             obj_dir/lib/defines.vh.v\n             obj_dir/lib/defines.vh.sv\n%Error: data/full_repos/permissive/433389019/CTRL.v:12: Define or directive not defined: \'`StallBus\'\n    output reg [`StallBus-1:0] stall\n                ^~~~~~~~~\n%Error: data/full_repos/permissive/433389019/CTRL.v:16: Define or directive not defined: \'`StallBus\'\n            stall = `StallBus\'b0;\n                    ^~~~~~~~~\n%Error: data/full_repos/permissive/433389019/CTRL.v:17: Define or directive not defined: \'`Stop\'\n        end else if(stallreq_for_id == `Stop) begin\n                                       ^~~~~\n%Error: data/full_repos/permissive/433389019/CTRL.v:17: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n        end else if(stallreq_for_id == `Stop) begin\n                                            ^\n%Error: data/full_repos/permissive/433389019/CTRL.v:19: Define or directive not defined: \'`Stop\'\n        end else if(stallreq_for_ex == `Stop) begin\n                                       ^~~~~\n%Error: data/full_repos/permissive/433389019/CTRL.v:23: Define or directive not defined: \'`StallBus\'\n            stall = `StallBus\'b0;\n                    ^~~~~~~~~\n%Error: Cannot continue\n'
module CTRL(
    input wire rst,




    input wire stallreq_for_ex,
    input wire stallreq_for_id,


    output reg [`StallBus-1:0] stall
);  
    always @ (*) begin
        if (rst) begin
            stall = `StallBus'b0;
        end else if(stallreq_for_id == `Stop) begin
            stall = 6'b000_111;
        end else if(stallreq_for_ex == `Stop) begin
            stall = 6'b001_111;
        end
        else begin
            stall = `StallBus'b0;
        end
    end

endmodule
module CTRL(
    input wire rst,




    input wire stallreq_for_ex,
    input wire stallreq_for_id,


    output reg [`StallBus-1:0] stall
);
  
    always @ (*) begin
        if (rst) begin
            stall = `StallBus'b0;
        end else if(stallreq_for_id == `Stop) begin
            stall = 6'b000_111;
        end else if(stallreq_for_ex == `Stop) begin
            stall = 6'b001_111;
        end
        else begin
            stall = `StallBus'b0;
        end
    end

endmodule