data/full_repos/permissive/441359809/src/yosys/tests/simple/generate.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/441359809/src/yosys/tests/simple/generate.v:43: Multiple top level modules\n                                                                                            : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                                            : ... Top module \'gen_test1\'\nmodule gen_test1(clk, a, b, y);\n       ^~~~~~~~~\n                                                                                            : ... Top module \'gen_test2\'\nmodule gen_test2(clk, a, b, y);\n       ^~~~~~~~~\n                                                                                            : ... Top module \'gen_test3\'\nmodule gen_test3(a, b, sel, y, z);\n       ^~~~~~~~~\n                                                                                            : ... Top module \'gen_test4\'\nmodule gen_test4(a, b);\n       ^~~~~~~~~\n                                                                                            : ... Top module \'gen_test5\'\nmodule gen_test5(input_bits, out);\n       ^~~~~~~~~\n                                                                                            : ... Top module \'gen_test6\'\nmodule gen_test6(output [3:0] o);\n       ^~~~~~~~~\n                                                                                            : ... Top module \'gen_test7\'\nmodule gen_test7;\n       ^~~~~~~~~\n                                                                                            : ... Top module \'gen_test8\'\nmodule gen_test8;\n       ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/generate.v:177: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'x\' generates 32 bits.\n                                                                                          : ... In instance gen_test7\n    out1 = x;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/generate.v:178: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'x\' generates 32 bits.\n                                                                                          : ... In instance gen_test7\n    sub_out1 = x;\n             ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/generate.v:183: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'x\' generates 32 bits.\n                                                                                          : ... In instance gen_test7\n    out2 = x;\n         ^\n%Warning-WIDTH: data/full_repos/permissive/441359809/src/yosys/tests/simple/generate.v:184: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s VARREF \'x\' generates 32 bits.\n                                                                                          : ... In instance gen_test7\n    sub_out2 = x;\n             ^\n%Error: Exiting due to 5 warning(s)\n'
module gen_test5(input_bits, out);

parameter WIDTH = 256;
parameter CHUNK = 4;

input [WIDTH-1:0] input_bits;
output out;

genvar step, i, j;
generate
	for (step = 1; step <= WIDTH; step = step * CHUNK) begin : steps
		localparam PREV = step / CHUNK;
		localparam DIM = WIDTH / step;
		for (i = 0; i < DIM; i = i + 1) begin : outer
			localparam LAST_START = i * CHUNK;
			for (j = 0; j < CHUNK; j = j + 1) begin : inner
				wire temp;
				if (step == 1)
					assign temp = input_bits[i];
				else if (j == 0)
					assign temp = steps[PREV].outer[LAST_START].val;
				else
					assign temp
						= steps[step].outer[i].inner[j-1].temp
						& steps[PREV].outer[LAST_START + j].val;
			end
			wire val;
			assign val = steps[step].outer[i].inner[CHUNK - 1].temp;
		end
	end
endgenerate
assign out = steps[WIDTH].outer[0].val;
endmodule
module gen_test5(input_bits, out);


parameter WIDTH = 256;
parameter CHUNK = 4;

input [WIDTH-1:0] input_bits;
output out;

genvar step, i, j;
generate
	for (step = 1; step <= WIDTH; step = step * CHUNK) begin : steps
		localparam PREV = step / CHUNK;
		localparam DIM = WIDTH / step;
		for (i = 0; i < DIM; i = i + 1) begin : outer
			localparam LAST_START = i * CHUNK;
			for (j = 0; j < CHUNK; j = j + 1) begin : inner
				wire temp;
				if (step == 1)
					assign temp = input_bits[i];
				else if (j == 0)
					assign temp = steps[PREV].outer[LAST_START].val;
				else
					assign temp
						= steps[step].outer[i].inner[j-1].temp
						& steps[PREV].outer[LAST_START + j].val;
			end
			wire val;
			assign val = steps[step].outer[i].inner[CHUNK - 1].temp;
		end
	end
endgenerate
assign out = steps[WIDTH].outer[0].val;
endmodule