data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v
1: b'%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:12: Cannot find include file: pa_chip_param.v\n`include "pa_chip_param.v" \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc,data/full_repos/permissive/485610894/pa_chip_param.v\n             data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc,data/full_repos/permissive/485610894/pa_chip_param.v.v\n             data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc,data/full_repos/permissive/485610894/pa_chip_param.v.sv\n             pa_chip_param.v\n             pa_chip_param.v.v\n             pa_chip_param.v.sv\n             obj_dir/pa_chip_param.v\n             obj_dir/pa_chip_param.v.v\n             obj_dir/pa_chip_param.v.sv\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:15: Define or directive not defined: \'`ADDR_BUS_WIDTH\'\n    input  wire [`ADDR_BUS_WIDTH-1:0]   m_addr_i,\n                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:16: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    output reg  [`DATA_BUS_WIDTH-1:0]   m_data_o,\n                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:20: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    input  wire [`DATA_BUS_WIDTH-1:0]   s0_data_i,\n                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:24: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    input  wire [`DATA_BUS_WIDTH-1:0]   s1_data_i,\n                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:28: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    input  wire [`DATA_BUS_WIDTH-1:0]   s2_data_i,\n                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:32: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    input  wire [`DATA_BUS_WIDTH-1:0]   s3_data_i,\n                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:36: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    input  wire [`DATA_BUS_WIDTH-1:0]   s4_data_i,\n                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:40: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    input  wire [`DATA_BUS_WIDTH-1:0]   s5_data_i,\n                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:44: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n    input  wire [`DATA_BUS_WIDTH-1:0]   s6_data_i,\n                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:59: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n        SLAVE_0_ADDR : m_data_o[`DATA_BUS_WIDTH-1:0] = s0_data_i[`DATA_BUS_WIDTH-1:0];\n                                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:59: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n        SLAVE_0_ADDR : m_data_o[`DATA_BUS_WIDTH-1:0] = s0_data_i[`DATA_BUS_WIDTH-1:0];\n                                                                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:60: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n        SLAVE_1_ADDR : m_data_o[`DATA_BUS_WIDTH-1:0] = s1_data_i[`DATA_BUS_WIDTH-1:0];\n                                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:60: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n        SLAVE_1_ADDR : m_data_o[`DATA_BUS_WIDTH-1:0] = s1_data_i[`DATA_BUS_WIDTH-1:0];\n                                                                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:61: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n        SLAVE_2_ADDR : m_data_o[`DATA_BUS_WIDTH-1:0] = s2_data_i[`DATA_BUS_WIDTH-1:0];\n                                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:61: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n        SLAVE_2_ADDR : m_data_o[`DATA_BUS_WIDTH-1:0] = s2_data_i[`DATA_BUS_WIDTH-1:0];\n                                                                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:62: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n        SLAVE_3_ADDR : m_data_o[`DATA_BUS_WIDTH-1:0] = s3_data_i[`DATA_BUS_WIDTH-1:0];\n                                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:62: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n        SLAVE_3_ADDR : m_data_o[`DATA_BUS_WIDTH-1:0] = s3_data_i[`DATA_BUS_WIDTH-1:0];\n                                                                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:63: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n        SLAVE_4_ADDR : m_data_o[`DATA_BUS_WIDTH-1:0] = s4_data_i[`DATA_BUS_WIDTH-1:0];\n                                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:63: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n        SLAVE_4_ADDR : m_data_o[`DATA_BUS_WIDTH-1:0] = s4_data_i[`DATA_BUS_WIDTH-1:0];\n                                                                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:64: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n        SLAVE_5_ADDR : m_data_o[`DATA_BUS_WIDTH-1:0] = s5_data_i[`DATA_BUS_WIDTH-1:0];\n                                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:64: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n        SLAVE_5_ADDR : m_data_o[`DATA_BUS_WIDTH-1:0] = s5_data_i[`DATA_BUS_WIDTH-1:0];\n                                                                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:65: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n        SLAVE_6_ADDR : m_data_o[`DATA_BUS_WIDTH-1:0] = s6_data_i[`DATA_BUS_WIDTH-1:0];\n                                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:65: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n        SLAVE_6_ADDR : m_data_o[`DATA_BUS_WIDTH-1:0] = s6_data_i[`DATA_BUS_WIDTH-1:0];\n                                                                 ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:66: Define or directive not defined: \'`DATA_BUS_WIDTH\'\n        default      : m_data_o[`DATA_BUS_WIDTH-1:0] = `ZERO_WORD;\n                                ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:66: Define or directive not defined: \'`ZERO_WORD\'\n        default      : m_data_o[`DATA_BUS_WIDTH-1:0] = `ZERO_WORD;\n                                                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:66: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n        default      : m_data_o[`DATA_BUS_WIDTH-1:0] = `ZERO_WORD;\n                                                                 ^\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:71: Define or directive not defined: \'`INVALID\'\n    s0_we_o = `INVALID;\n              ^~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:71: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    s0_we_o = `INVALID;\n                      ^\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:72: Define or directive not defined: \'`INVALID\'\n    s1_we_o = `INVALID;\n              ^~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:72: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    s1_we_o = `INVALID;\n                      ^\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:73: Define or directive not defined: \'`INVALID\'\n    s2_we_o = `INVALID;\n              ^~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:73: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    s2_we_o = `INVALID;\n                      ^\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:74: Define or directive not defined: \'`INVALID\'\n    s3_we_o = `INVALID;\n              ^~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:74: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    s3_we_o = `INVALID;\n                      ^\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:75: Define or directive not defined: \'`INVALID\'\n    s4_we_o = `INVALID;\n              ^~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:75: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    s4_we_o = `INVALID;\n                      ^\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:76: Define or directive not defined: \'`INVALID\'\n    s5_we_o = `INVALID;\n              ^~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:76: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    s5_we_o = `INVALID;\n                      ^\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:77: Define or directive not defined: \'`INVALID\'\n    s6_we_o = `INVALID;\n              ^~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:77: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    s6_we_o = `INVALID;\n                      ^\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:90: Define or directive not defined: \'`INVALID\'\n    s0_rd_o = `INVALID;\n              ^~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:90: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    s0_rd_o = `INVALID;\n                      ^\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:91: Define or directive not defined: \'`INVALID\'\n    s1_rd_o = `INVALID;\n              ^~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:91: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    s1_rd_o = `INVALID;\n                      ^\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:92: Define or directive not defined: \'`INVALID\'\n    s2_rd_o = `INVALID;\n              ^~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:92: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    s2_rd_o = `INVALID;\n                      ^\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:93: Define or directive not defined: \'`INVALID\'\n    s3_rd_o = `INVALID;\n              ^~~~~~~~\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:93: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n    s3_rd_o = `INVALID;\n                      ^\n%Error: data/full_repos/permissive/485610894/yuheng-riscv-env/rtl/soc/pa_soc_rbm.v:94: Define or directive not defined: \'`INVALID\'\n    s4_rd_o = `INVALID;\n              ^~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n'
module pa_soc_rbm (
    input  wire [`ADDR_BUS_WIDTH-1:0]   m_addr_i,
    output reg  [`DATA_BUS_WIDTH-1:0]   m_data_o,
    input  wire                         m_we_i,
    input  wire                         m_rd_i,

    input  wire [`DATA_BUS_WIDTH-1:0]   s0_data_i,
    output reg                          s0_we_o,
    output reg                          s0_rd_o,

    input  wire [`DATA_BUS_WIDTH-1:0]   s1_data_i,
    output reg                          s1_we_o,
    output reg                          s1_rd_o,

    input  wire [`DATA_BUS_WIDTH-1:0]   s2_data_i,
    output reg                          s2_we_o,
    output reg                          s2_rd_o,

    input  wire [`DATA_BUS_WIDTH-1:0]   s3_data_i,
    output reg                          s3_we_o,
    output reg                          s3_rd_o,

    input  wire [`DATA_BUS_WIDTH-1:0]   s4_data_i,
    output reg                          s4_we_o,
    output reg                          s4_rd_o,

    input  wire [`DATA_BUS_WIDTH-1:0]   s5_data_i,
    output reg                          s5_we_o,
    output reg                          s5_rd_o,

    input  wire [`DATA_BUS_WIDTH-1:0]   s6_data_i,
    output reg                          s6_we_o,
    output reg                          s6_rd_o
);

localparam SLAVE_0_ADDR                 = 4'b0000;
localparam SLAVE_1_ADDR                 = 4'b0001;
localparam SLAVE_2_ADDR                 = 4'b0010;
localparam SLAVE_3_ADDR                 = 4'b0011;
localparam SLAVE_4_ADDR                 = 4'b0100;
localparam SLAVE_5_ADDR                 = 4'b0101;
localparam SLAVE_6_ADDR                 = 4'b0110;

always @ (*) begin
    case (m_addr_i[31:28])
        SLAVE_0_ADDR : m_data_o[`DATA_BUS_WIDTH-1:0] = s0_data_i[`DATA_BUS_WIDTH-1:0];
        SLAVE_1_ADDR : m_data_o[`DATA_BUS_WIDTH-1:0] = s1_data_i[`DATA_BUS_WIDTH-1:0];
        SLAVE_2_ADDR : m_data_o[`DATA_BUS_WIDTH-1:0] = s2_data_i[`DATA_BUS_WIDTH-1:0];
        SLAVE_3_ADDR : m_data_o[`DATA_BUS_WIDTH-1:0] = s3_data_i[`DATA_BUS_WIDTH-1:0];
        SLAVE_4_ADDR : m_data_o[`DATA_BUS_WIDTH-1:0] = s4_data_i[`DATA_BUS_WIDTH-1:0];
        SLAVE_5_ADDR : m_data_o[`DATA_BUS_WIDTH-1:0] = s5_data_i[`DATA_BUS_WIDTH-1:0];
        SLAVE_6_ADDR : m_data_o[`DATA_BUS_WIDTH-1:0] = s6_data_i[`DATA_BUS_WIDTH-1:0];
        default      : m_data_o[`DATA_BUS_WIDTH-1:0] = `ZERO_WORD;
    endcase
end

always @ (*) begin
    s0_we_o = `INVALID;
    s1_we_o = `INVALID;
    s2_we_o = `INVALID;
    s3_we_o = `INVALID;
    s4_we_o = `INVALID;
    s5_we_o = `INVALID;
    s6_we_o = `INVALID;
    case (m_addr_i[31:28])
        SLAVE_0_ADDR : s0_we_o = m_we_i;
        SLAVE_1_ADDR : s1_we_o = m_we_i;
        SLAVE_2_ADDR : s2_we_o = m_we_i;
        SLAVE_3_ADDR : s3_we_o = m_we_i;
        SLAVE_4_ADDR : s4_we_o = m_we_i;
        SLAVE_5_ADDR : s5_we_o = m_we_i;
        SLAVE_6_ADDR : s6_we_o = m_we_i;
    endcase
end

always @ (*) begin
    s0_rd_o = `INVALID;
    s1_rd_o = `INVALID;
    s2_rd_o = `INVALID;
    s3_rd_o = `INVALID;
    s4_rd_o = `INVALID;
    s5_rd_o = `INVALID;
    s6_rd_o = `INVALID;
    case (m_addr_i[31:28])
        SLAVE_0_ADDR : s0_rd_o = m_rd_i;
        SLAVE_1_ADDR : s1_rd_o = m_rd_i;
        SLAVE_2_ADDR : s2_rd_o = m_rd_i;
        SLAVE_3_ADDR : s3_rd_o = m_rd_i;
        SLAVE_4_ADDR : s4_rd_o = m_rd_i;
        SLAVE_5_ADDR : s5_rd_o = m_rd_i;
        SLAVE_6_ADDR : s6_rd_o = m_rd_i;
    endcase
end

endmodule
module pa_soc_rbm (
    input  wire [`ADDR_BUS_WIDTH-1:0]   m_addr_i,
    output reg  [`DATA_BUS_WIDTH-1:0]   m_data_o,
    input  wire                         m_we_i,
    input  wire                         m_rd_i,

    input  wire [`DATA_BUS_WIDTH-1:0]   s0_data_i,
    output reg                          s0_we_o,
    output reg                          s0_rd_o,

    input  wire [`DATA_BUS_WIDTH-1:0]   s1_data_i,
    output reg                          s1_we_o,
    output reg                          s1_rd_o,

    input  wire [`DATA_BUS_WIDTH-1:0]   s2_data_i,
    output reg                          s2_we_o,
    output reg                          s2_rd_o,

    input  wire [`DATA_BUS_WIDTH-1:0]   s3_data_i,
    output reg                          s3_we_o,
    output reg                          s3_rd_o,

    input  wire [`DATA_BUS_WIDTH-1:0]   s4_data_i,
    output reg                          s4_we_o,
    output reg                          s4_rd_o,

    input  wire [`DATA_BUS_WIDTH-1:0]   s5_data_i,
    output reg                          s5_we_o,
    output reg                          s5_rd_o,

    input  wire [`DATA_BUS_WIDTH-1:0]   s6_data_i,
    output reg                          s6_we_o,
    output reg                          s6_rd_o
);


localparam SLAVE_0_ADDR                 = 4'b0000;
localparam SLAVE_1_ADDR                 = 4'b0001;
localparam SLAVE_2_ADDR                 = 4'b0010;
localparam SLAVE_3_ADDR                 = 4'b0011;
localparam SLAVE_4_ADDR                 = 4'b0100;
localparam SLAVE_5_ADDR                 = 4'b0101;
localparam SLAVE_6_ADDR                 = 4'b0110;

always @ (*) begin
    case (m_addr_i[31:28])
        SLAVE_0_ADDR : m_data_o[`DATA_BUS_WIDTH-1:0] = s0_data_i[`DATA_BUS_WIDTH-1:0];
        SLAVE_1_ADDR : m_data_o[`DATA_BUS_WIDTH-1:0] = s1_data_i[`DATA_BUS_WIDTH-1:0];
        SLAVE_2_ADDR : m_data_o[`DATA_BUS_WIDTH-1:0] = s2_data_i[`DATA_BUS_WIDTH-1:0];
        SLAVE_3_ADDR : m_data_o[`DATA_BUS_WIDTH-1:0] = s3_data_i[`DATA_BUS_WIDTH-1:0];
        SLAVE_4_ADDR : m_data_o[`DATA_BUS_WIDTH-1:0] = s4_data_i[`DATA_BUS_WIDTH-1:0];
        SLAVE_5_ADDR : m_data_o[`DATA_BUS_WIDTH-1:0] = s5_data_i[`DATA_BUS_WIDTH-1:0];
        SLAVE_6_ADDR : m_data_o[`DATA_BUS_WIDTH-1:0] = s6_data_i[`DATA_BUS_WIDTH-1:0];
        default      : m_data_o[`DATA_BUS_WIDTH-1:0] = `ZERO_WORD;
    endcase
end

always @ (*) begin
    s0_we_o = `INVALID;
    s1_we_o = `INVALID;
    s2_we_o = `INVALID;
    s3_we_o = `INVALID;
    s4_we_o = `INVALID;
    s5_we_o = `INVALID;
    s6_we_o = `INVALID;
    case (m_addr_i[31:28])
        SLAVE_0_ADDR : s0_we_o = m_we_i;
        SLAVE_1_ADDR : s1_we_o = m_we_i;
        SLAVE_2_ADDR : s2_we_o = m_we_i;
        SLAVE_3_ADDR : s3_we_o = m_we_i;
        SLAVE_4_ADDR : s4_we_o = m_we_i;
        SLAVE_5_ADDR : s5_we_o = m_we_i;
        SLAVE_6_ADDR : s6_we_o = m_we_i;
    endcase
end

always @ (*) begin
    s0_rd_o = `INVALID;
    s1_rd_o = `INVALID;
    s2_rd_o = `INVALID;
    s3_rd_o = `INVALID;
    s4_rd_o = `INVALID;
    s5_rd_o = `INVALID;
    s6_rd_o = `INVALID;
    case (m_addr_i[31:28])
        SLAVE_0_ADDR : s0_rd_o = m_rd_i;
        SLAVE_1_ADDR : s1_rd_o = m_rd_i;
        SLAVE_2_ADDR : s2_rd_o = m_rd_i;
        SLAVE_3_ADDR : s3_rd_o = m_rd_i;
        SLAVE_4_ADDR : s4_rd_o = m_rd_i;
        SLAVE_5_ADDR : s5_rd_o = m_rd_i;
        SLAVE_6_ADDR : s6_rd_o = m_rd_i;
    endcase
end

endmodule