data/full_repos/permissive/441359809/src/yosys/tests/asicworld/code_verilog_tutorial_bus_con.v
data/verilator_xmls/62f330b4-c1de-4f04-8d9b-97e23624a579.xml
module bus_con (a,b, y);
  	  	input [3:0] a, b;
  	  	output [7:0] y;
  	  	wire [7:0] y;
  	  	 
  	  	assign y = {a,b};
  	  	 
endmodule
module bus_con (a,b, y);

  	  	input [3:0] a, b;
  	  	output [7:0] y;
  	  	wire [7:0] y;
  	  	 
  	  	assign y = {a,b};
  	  	 
endmodule