data/full_repos/permissive/486588912/verilog/sims/sim_top.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/486588912/verilog/sims/sim_top.v:13: Unsupported: Ignoring delay on this delayed statement.\n        #11 bank_rst = 0;\n        ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/486588912/verilog/sims/sim_top.v:15: Unsupported: Ignoring delay on this delayed statement.\n        #100 switches_pin = 24\'b00000000_00000000_00000001;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/486588912/verilog/sims/sim_top.v:16: Unsupported: Ignoring delay on this delayed statement.\n        #100 switches_pin = 24\'b00000000_00000000_00000011;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/486588912/verilog/sims/sim_top.v:17: Unsupported: Ignoring delay on this delayed statement.\n        #100 switches_pin = 24\'b00000000_00000000_00000111;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/486588912/verilog/sims/sim_top.v:18: Unsupported: Ignoring delay on this delayed statement.\n        #1000 switches_pin = 24\'b00100000_00000000_00000111;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/486588912/verilog/sims/sim_top.v:19: Unsupported: Ignoring delay on this delayed statement.\n        #1000 switches_pin = 24\'b10100000_11000011_00000111;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/486588912/verilog/sims/sim_top.v:24: Unsupported: Ignoring delay on this delayed statement.\n        #5000 keypad_detect = 4\'b1110;\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/486588912/verilog/sims/sim_top.v:27: Unsupported: Ignoring delay on this delayed statement.\n    always #5 bank_sys_clk = ~bank_sys_clk;\n           ^\n%Warning-STMTDLY: data/full_repos/permissive/486588912/verilog/sims/sim_top.v:59: Unsupported: Ignoring delay on this delayed statement.\n        #1000000 \n        ^\n%Warning-STMTDLY: data/full_repos/permissive/486588912/verilog/sims/sim_top.v:62: Unsupported: Ignoring delay on this delayed statement.\n        #200\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/486588912/verilog/sims/sim_top.v:64: Unsupported: Ignoring delay on this delayed statement.\n        #20\n        ^\n%Warning-STMTDLY: data/full_repos/permissive/486588912/verilog/sims/sim_top.v:72: Unsupported: Ignoring delay on this delayed statement.\n            #200 send = 1; \n            ^\n%Warning-STMTDLY: data/full_repos/permissive/486588912/verilog/sims/sim_top.v:73: Unsupported: Ignoring delay on this delayed statement.\n            #20 send = 0;\n            ^\n%Error: data/full_repos/permissive/486588912/verilog/sims/sim_top.v:29: Can\'t find definition of \'sys_clk\' in dotted variable: \'ttop.sys_clk\'\n    assign sys_clk = ttop.sys_clk;\n                          ^~~~~~~\n%Error: Exiting due to 1 error(s), 13 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module sim_top();
    reg bank_sys_clk;
    reg bank_rst;
    reg [23:0] switches_pin;
    reg [3:0] keypad_detect;

    initial begin 
        bank_sys_clk = 0;
        bank_rst = 1;
        switches_pin = 0;
        #11 bank_rst = 0;

        #100 switches_pin = 24'b00000000_00000000_00000001;
        #100 switches_pin = 24'b00000000_00000000_00000011;
        #100 switches_pin = 24'b00000000_00000000_00000111;
        #1000 switches_pin = 24'b00100000_00000000_00000111;
        #1000 switches_pin = 24'b10100000_11000011_00000111;
    end

    initial begin
        keypad_detect = 4'b1111;
        #5000 keypad_detect = 4'b1110;
    end

    always #5 bank_sys_clk = ~bank_sys_clk;
    wire sys_clk;
    assign sys_clk = ttop.sys_clk;
    wire uart_rx;
    wire uart_tx;
    top ttop(
        .bank_sys_clk(bank_sys_clk),
        .bank_rst(bank_rst),
        .switches_pin(switches_pin),

        .uart_rx_pin(uart_rx),
        .uart_tx_pin(uart_tx),
        .keypad_detect(keypad_detect)
    );
    reg send;
    reg [7:0] dsend;
    wire uart_tx_busy;
    uart_send test_send(
        .sys_clk(sys_clk),
        .sys_rst_n(!bank_rst),

        .uart_en(send),
        .uart_din(dsend),
        .uart_tx_busy(uart_tx_busy),
        .uart_txd(uart_rx)
    );

    initial begin
        cnt = 0;
    end

    initial begin
        #1000000 
        dsend = 8'h00;
        send = 0;
        #200
        send = 1;
        #20
        send = 0;
        
    end
    reg [2:0] cnt;
    always @(negedge uart_tx_busy) begin
        if (cnt <= 6) begin
            dsend = (cnt < 4 ) ? 8'H00 : 8'H02;
            #200 send = 1; 
            #20 send = 0;
            cnt = cnt + 1;
        end
    end

    wire sim_uart_rx_done;
    wire [7:0] sim_uart_rx_data;
    uart_recv test_recv(
        .sys_clk(sys_clk),
        .sys_rst_n(!bank_rst),
        .uart_rxd(uart_tx),
        .uart_done(sim_uart_rx_done),
        .uart_data(sim_uart_rx_data)
    );
endmodule
module sim_top();

    reg bank_sys_clk;
    reg bank_rst;
    reg [23:0] switches_pin;
    reg [3:0] keypad_detect;

    initial begin 
        bank_sys_clk = 0;
        bank_rst = 1;
        switches_pin = 0;
        #11 bank_rst = 0;

        #100 switches_pin = 24'b00000000_00000000_00000001;
        #100 switches_pin = 24'b00000000_00000000_00000011;
        #100 switches_pin = 24'b00000000_00000000_00000111;
        #1000 switches_pin = 24'b00100000_00000000_00000111;
        #1000 switches_pin = 24'b10100000_11000011_00000111;
    end

    initial begin
        keypad_detect = 4'b1111;
        #5000 keypad_detect = 4'b1110;
    end

    always #5 bank_sys_clk = ~bank_sys_clk;
    wire sys_clk;
    assign sys_clk = ttop.sys_clk;
    wire uart_rx;
    wire uart_tx;
    top ttop(
        .bank_sys_clk(bank_sys_clk),
        .bank_rst(bank_rst),
        .switches_pin(switches_pin),

        .uart_rx_pin(uart_rx),
        .uart_tx_pin(uart_tx),
        .keypad_detect(keypad_detect)
    );
    reg send;
    reg [7:0] dsend;
    wire uart_tx_busy;
    uart_send test_send(
        .sys_clk(sys_clk),
        .sys_rst_n(!bank_rst),

        .uart_en(send),
        .uart_din(dsend),
        .uart_tx_busy(uart_tx_busy),
        .uart_txd(uart_rx)
    );

    initial begin
        cnt = 0;
    end

    initial begin
        #1000000 
        dsend = 8'h00;
        send = 0;
        #200
        send = 1;
        #20
        send = 0;
        
    end
    reg [2:0] cnt;
    always @(negedge uart_tx_busy) begin
        if (cnt <= 6) begin
            dsend = (cnt < 4 ) ? 8'H00 : 8'H02;
            #200 send = 1; 
            #20 send = 0;
            cnt = cnt + 1;
        end
    end

    wire sim_uart_rx_done;
    wire [7:0] sim_uart_rx_data;
    uart_recv test_recv(
        .sys_clk(sys_clk),
        .sys_rst_n(!bank_rst),
        .uart_rxd(uart_tx),
        .uart_done(sim_uart_rx_done),
        .uart_data(sim_uart_rx_data)
    );
endmodule