data/full_repos/permissive/424376038/csync.v
data/verilator_xmls/4ae1df44-79b6-4dbd-a7e9-7b4f55de4054.xml
module csync
(
	input  clk,
	input  hsync,
	input  vsync,

	output csync
);



assign csync = (csync_vs ^ csync_hs);

reg csync_hs, csync_vs;
reg prev_hs;
reg [15:0] h_cnt, line_len, hs_len;

always @(negedge clk) begin

	h_cnt <= h_cnt + 1'd1;

	prev_hs <= hsync;
	if (prev_hs ^ hsync) begin
		h_cnt <= 0;
		if (hsync) begin
			line_len <= h_cnt - hs_len;
			csync_hs <= 0;
		end
		else hs_len <= h_cnt;
	end
	
	if (~vsync) csync_hs <= hsync;
	else if(h_cnt == line_len) csync_hs <= 1;
	
	csync_vs <= vsync;
end

endmodule
module csync
(
	input  clk,
	input  hsync,
	input  vsync,

	output csync
);




assign csync = (csync_vs ^ csync_hs);

reg csync_hs, csync_vs;
reg prev_hs;
reg [15:0] h_cnt, line_len, hs_len;

always @(negedge clk) begin

	h_cnt <= h_cnt + 1'd1;

	prev_hs <= hsync;
	if (prev_hs ^ hsync) begin
		h_cnt <= 0;
		if (hsync) begin
			line_len <= h_cnt - hs_len;
			csync_hs <= 0;
		end
		else hs_len <= h_cnt;
	end
	
	if (~vsync) csync_hs <= hsync;
	else if(h_cnt == line_len) csync_hs <= 1;
	
	csync_vs <= vsync;
end

endmodule