data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/clk_rst_gen.sv
1: b"%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/clk_rst_gen.sv:13: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER\n  parameter time          ClkPeriod = 0ps,  \n                                      ^~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/clk_rst_gen.sv:15: syntax error, unexpected ')', expecting ';'\n) (\n^\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/clk_rst_gen.sv:17: syntax error, unexpected output, expecting IDENTIFIER or '=' or do or final\n  output logic rst_no\n  ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/clk_rst_gen.sv:23: syntax error, unexpected initial\n  initial begin\n  ^~~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/clk_rst_gen.sv:34: Unsupported: Static in this context\n    static int unsigned rst_cnt = 0;\n    ^~~~~~\n%Error: data/full_repos/permissive/509468557/generators/cva6/src/main/resources/vsrc/cva6/tb/common_verification/src/clk_rst_gen.sv:35: syntax error, unexpected IDENTIFIER\n    rst_no = 1'b0;\n    ^~~~~~\n%Error: Exiting due to 6 error(s)\n"
module clk_rst_gen #(
  parameter time          ClkPeriod = 0ps,
  parameter int unsigned  RstClkCycles = 0
) (
  output logic clk_o,
  output logic rst_no
);

  logic clk;


  initial begin
    clk = 1'b0;
  end
  always begin
    clk = ~clk;
    #(ClkPeriod / 2);
  end
  assign clk_o = clk;


  initial begin
    static int unsigned rst_cnt = 0;
    rst_no = 1'b0;
    while (rst_cnt <= RstClkCycles) begin
      @(posedge clk);
      rst_cnt++;
    end
    rst_no = 1'b1;
  end


`ifndef VERILATOR
  initial begin: validate_params
    assert (ClkPeriod >= 2ps)
      else $fatal("The clock period must be at least 2ps!");


    assert (RstClkCycles > 0)
      else $fatal("The number of clock cycles in reset must be greater than 0!");
  end
`endif

endmodule
module clk_rst_gen #(
  parameter time          ClkPeriod = 0ps,
  parameter int unsigned  RstClkCycles = 0
) (
  output logic clk_o,
  output logic rst_no
);


  logic clk;


  initial begin
    clk = 1'b0;
  end
  always begin
    clk = ~clk;
    #(ClkPeriod / 2);
  end
  assign clk_o = clk;


  initial begin
    static int unsigned rst_cnt = 0;
    rst_no = 1'b0;
    while (rst_cnt <= RstClkCycles) begin
      @(posedge clk);
      rst_cnt++;
    end
    rst_no = 1'b1;
  end


`ifndef VERILATOR
  initial begin: validate_params
    assert (ClkPeriod >= 2ps)
      else $fatal("The clock period must be at least 2ps!");


    assert (RstClkCycles > 0)
      else $fatal("The number of clock cycles in reset must be greater than 0!");
  end
`endif

endmodule