data/full_repos/permissive/504478691/PCF8591/integer_display.v
1: b'%Warning-WIDTH: data/full_repos/permissive/504478691/PCF8591/integer_display.v:31: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n                                                                                 : ... In instance integer_display\nassign digits[31:28] = n / 10000000 % 10;\n                     ^\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/504478691/PCF8591/integer_display.v:32: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n                                                                                 : ... In instance integer_display\nassign digits[27:24] = n / 1000000 % 10;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/504478691/PCF8591/integer_display.v:33: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n                                                                                 : ... In instance integer_display\nassign digits[23:20] = n / 100000 % 10;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/504478691/PCF8591/integer_display.v:34: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n                                                                                 : ... In instance integer_display\nassign digits[19:16] = n / 10000 % 10;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/504478691/PCF8591/integer_display.v:35: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n                                                                                 : ... In instance integer_display\nassign digits[15:12] = n / 1000 % 10;\n                     ^\n%Warning-WIDTH: data/full_repos/permissive/504478691/PCF8591/integer_display.v:36: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n                                                                                 : ... In instance integer_display\nassign digits[11:8] =  n / 100 % 10;\n                    ^\n%Warning-WIDTH: data/full_repos/permissive/504478691/PCF8591/integer_display.v:37: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n                                                                                 : ... In instance integer_display\nassign digits[7:4] =   n / 10 % 10;\n                   ^\n%Warning-WIDTH: data/full_repos/permissive/504478691/PCF8591/integer_display.v:38: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s MODDIV generates 32 bits.\n                                                                                 : ... In instance integer_display\nassign digits[3:0] =   n / 1 % 10;\n                   ^\n%Error: Exiting due to 8 warning(s)\n'
module integer_display(input [31:0] n, input clk, input [2:0] blink, input blink_ena, output reg [7:0] anode, output [6:0] cathode);
reg [3:0] digit;
wire [31:0] digits;
integer num = 0, blink_num = 0, j;
reg [2:0] i = 7;
reg ena = 1;
wire cathode_ena;
assign cathode_ena = (i == blink && ena == 0) ? 0 : 1;
display7 inst(.iData(digit), .cathode_ena(cathode_ena), .oData(cathode));
assign digits[31:28] = n / 10000000 % 10;
assign digits[27:24] = n / 1000000 % 10;
assign digits[23:20] = n / 100000 % 10;
assign digits[19:16] = n / 10000 % 10;
assign digits[15:12] = n / 1000 % 10;
assign digits[11:8] =  n / 100 % 10;
assign digits[7:4] =   n / 10 % 10;
assign digits[3:0] =   n / 1 % 10;
always @(posedge clk)
begin
    if (num == 50_000_000 / 400)
    begin
        i = i + 1;
        if (blink_ena && blink_num == 400)
        begin
            blink_num = 1;
            ena = ~ena;
        end
        else if (blink_ena)
            blink_num = blink_num + 1;
        else
        begin
            blink_num = 0;
            ena = 1;
        end
        anode = 8'b11111111;
        anode[i] = 0;
        for (j = 0; j < 4; j = j + 1)
            digit[j] = digits[i * 4 + j];
        num = 1;
    end
    else
        num = num + 1;
end
endmodule
module integer_display(input [31:0] n, input clk, input [2:0] blink, input blink_ena, output reg [7:0] anode, output [6:0] cathode);

reg [3:0] digit;
wire [31:0] digits;
integer num = 0, blink_num = 0, j;
reg [2:0] i = 7;
reg ena = 1;
wire cathode_ena;
assign cathode_ena = (i == blink && ena == 0) ? 0 : 1;
display7 inst(.iData(digit), .cathode_ena(cathode_ena), .oData(cathode));
assign digits[31:28] = n / 10000000 % 10;
assign digits[27:24] = n / 1000000 % 10;
assign digits[23:20] = n / 100000 % 10;
assign digits[19:16] = n / 10000 % 10;
assign digits[15:12] = n / 1000 % 10;
assign digits[11:8] =  n / 100 % 10;
assign digits[7:4] =   n / 10 % 10;
assign digits[3:0] =   n / 1 % 10;
always @(posedge clk)
begin
    if (num == 50_000_000 / 400)
    begin
        i = i + 1;
        if (blink_ena && blink_num == 400)
        begin
            blink_num = 1;
            ena = ~ena;
        end
        else if (blink_ena)
            blink_num = blink_num + 1;
        else
        begin
            blink_num = 0;
            ena = 1;
        end
        anode = 8'b11111111;
        anode[i] = 0;
        for (j = 0; j < 4; j = j + 1)
            digit[j] = digits[i * 4 + j];
        num = 1;
    end
    else
        num = num + 1;
end
endmodule