data/full_repos/permissive/419677538/Calculator_Project/verilog_code/calculator.v
data/verilator_xmls/49e5f47e-b5f1-49fc-9ab3-e473e607d07a.xml
module calculator(sys_clk,reset,keyb_clk,keyb_data,HEX7,HEX6,HEX5,HEX4,HEX3,HEX2);
   input sys_clk,reset,keyb_data;
   inout keyb_clk;
   output reg [6:0] HEX2,HEX3,HEX4,HEX5,HEX6,HEX7;
   parameter [2:0] WAIT_OPERAND1=3'b000,WAIT_OPERATOR=3'b001,WAIT_OPERAND2=3'b010,WAIT_EQ=3'b011,WAIT_F0=3'b100,AFTER_F0=3'b101;
   
   reg [5:0] keyb_clk_samples;
   reg [10:0] keyb_data_reg;
   reg [7:0] keyb_data_8bit;
   
   wire [5:0] result;
   wire [5:0] mux;
   reg [5:0] a;
   reg [5:0] b;
   reg [5:0] c;
   reg op;
   

   reg [2:0] next_calc_state;
   reg [2:0] state;
   

   reg [6:0] disp1,disp2;
   
   
   assign keyb_clk=(!keyb_data_reg[0])?1'b0:1'bz;
   
   assign mux=(next_calc_state==WAIT_EQ)?result:c;
   
   assign result=op?a+(~b)+1'b1:a+b;
   
   
   

   always @(posedge sys_clk or posedge reset)
    begin
      if(reset)
	     keyb_clk_samples<=6'b000000;
	  else
	     keyb_clk_samples<={keyb_clk,keyb_clk_samples[5:1]};
    end
		 

   always @(posedge sys_clk or posedge reset)
    begin
      if(reset)
	     keyb_data_reg<=11'b11111111111;
	  else if(!keyb_data_reg[0])
	    begin
          keyb_data_8bit<=keyb_data_reg[8:1];
		  keyb_data_reg<=11'b11111111111;
	    end
	  else if(keyb_clk_samples==6'b000111)
		 keyb_data_reg<={keyb_data,keyb_data_reg[10:1]};	 
    end
		 

   always @(*)
    begin
		case(keyb_data_8bit)
		    8'h16: c<=6'd1;
		    8'h1E: c<=6'd2;
		    8'h26: c<=6'd3;
		    8'h25: c<=6'd4;
		    8'h2E: c<=6'd5;
		    8'h36: c<=6'd6;
		    8'h3D: c<=6'd7;
		    8'h3E: c<=6'd8;
		    8'h46: c<=6'd9;
		    8'h45: c<=6'd0;
		    8'h69: c<=6'd1;
		    8'h72: c<=6'd2;
		    8'h7A: c<=6'd3;
		    8'h6B: c<=6'd4;
		    8'h73: c<=6'd5;
		    8'h74: c<=6'd6;
		    8'h6C: c<=6'd7;
		    8'h75: c<=6'd8;
		    8'h7D: c<=6'd9;
		    8'h70: c<=6'd0;
		    default: c<=6'b100000;
		endcase
	end
		 	 

   always @(*)
    begin
		case(mux)
		   -6'd9: 
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b0010000;
			 end			   
		   -6'd8:
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b0000000;
			 end	
		   -6'd7:
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b1111000;
			 end	
		   -6'd6:
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b0000010;
			 end	
		   -6'd5:
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b0010010;
			 end	
		   -6'd4:
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b0011001;
			 end	
		   -6'd3:
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b0110000;
			 end	
		   -6'd2:
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b0100100;
			 end	
		   -6'd1:
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b1111001;
			 end	
		    6'd0:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b1000000;
			 end	
		    6'd1:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b1111001;
			 end	
		    6'd2:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b0100100;
			 end
		    6'd3:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b0110000;
			 end
		    6'd4:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b0011001;
			 end
		    6'd5:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b0010010;
			 end
		    6'd6:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b0000010;
			 end
		    6'd7:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b1111000;
			 end
		    6'd8:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b0000000;
			 end
		    6'd9:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b0010000;
			 end
		    6'd10:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b1000000;
			 end
		    6'd11:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b1111001;
			 end
		    6'd12:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b0100100;
			 end
		    6'd13:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b0110000;
			 end
		    6'd14:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b0011001;
			 end
		    6'd15:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b0010010;
			 end
		    6'd16:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b0000010;
			 end
		    6'd17:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b1111000;
			 end
		    6'd18:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b0000000;
			 end
		    default:
			 begin
               disp1<=7'b0000100; 
			   disp2<=7'b0000100;
			 end
		endcase
	end	 
		 	 

	always @(posedge sys_clk or posedge reset)
	 begin
	  if(reset)
	     begin		
			HEX2<=7'b1111111;
			HEX3<=7'b1111111;
			HEX4<=7'b1111111;
			HEX5<=7'b1111111;
			HEX6<=7'b1111111;
			HEX7<=7'b1111111;
			next_calc_state<=WAIT_OPERAND1;
		 end
	  else if(!keyb_data_reg[0])
        case(next_calc_state)
		   WAIT_OPERAND1: begin
							  HEX2<=7'b1111111;
							  HEX3<=7'b1111111;
							  HEX4<=7'b1111111;
							  HEX5<=7'b1111111;
							  HEX6<=7'b1111111;
							  if(c[5]!=1'b1)
								  begin
									 a<=c;
									 next_calc_state<=WAIT_F0;
								  end
							 HEX7<=disp2;
							 state<=WAIT_OPERAND1;
					      end
		   WAIT_OPERATOR: begin
							 case(keyb_data_8bit)
								8'h79: begin
										   HEX6<=7'b0111001;
										   op<=1'b0;
										   next_calc_state<=WAIT_F0;
										 end
								8'h7B: begin
										   HEX6<=7'b0111111;
										   op<=1'b1;
										   next_calc_state<=WAIT_F0;
										 end
								default: HEX6<=7'b0000100;
							 endcase
							 state<=WAIT_OPERATOR;
						  end 					
		   WAIT_OPERAND2: begin
							   if(c[5]!=1'b1)
									begin
									   b<=c;
									   next_calc_state<=WAIT_F0;
									end   
							   HEX5<=disp2;
							   state<=WAIT_OPERAND2;
			              end 
		   WAIT_EQ: begin
					   if(keyb_data_8bit==8'h55)
							begin
							   HEX4<=7'b0111110;
							   HEX3<=disp1;
							   HEX2<=disp2;
							   next_calc_state<=WAIT_F0;
							end
					   else
							HEX4<=7'b0000100;
					   state<=WAIT_EQ;
					end
		   WAIT_F0: begin
					  if(keyb_data_8bit==8'hF0)
						next_calc_state<=AFTER_F0;
			        end
		   AFTER_F0: begin
						case(state)
						   WAIT_OPERAND1:next_calc_state<=WAIT_OPERATOR; 
						   WAIT_OPERATOR:next_calc_state<=WAIT_OPERAND2;
						   WAIT_OPERAND2:next_calc_state<=WAIT_EQ;
						   default:next_calc_state<=WAIT_OPERAND1;
						endcase   
		             end   
		   default: begin               
					   HEX2<=7'b1111111;
					   HEX3<=7'b1111111;
					   HEX4<=7'b1111111;
					   HEX5<=7'b1111111;
					   HEX6<=7'b1111111;
					   HEX7<=7'b1111111;
					   next_calc_state<=WAIT_OPERAND1;
					end
		endcase
	 end
endmodule
module calculator(sys_clk,reset,keyb_clk,keyb_data,HEX7,HEX6,HEX5,HEX4,HEX3,HEX2);

   input sys_clk,reset,keyb_data;
   inout keyb_clk;
   output reg [6:0] HEX2,HEX3,HEX4,HEX5,HEX6,HEX7;
   parameter [2:0] WAIT_OPERAND1=3'b000,WAIT_OPERATOR=3'b001,WAIT_OPERAND2=3'b010,WAIT_EQ=3'b011,WAIT_F0=3'b100,AFTER_F0=3'b101;
   
   reg [5:0] keyb_clk_samples;
   reg [10:0] keyb_data_reg;
   reg [7:0] keyb_data_8bit;
   
   wire [5:0] result;
   wire [5:0] mux;
   reg [5:0] a;
   reg [5:0] b;
   reg [5:0] c;
   reg op;
   

   reg [2:0] next_calc_state;
   reg [2:0] state;
   

   reg [6:0] disp1,disp2;
   
   
   assign keyb_clk=(!keyb_data_reg[0])?1'b0:1'bz;
   
   assign mux=(next_calc_state==WAIT_EQ)?result:c;
   
   assign result=op?a+(~b)+1'b1:a+b;
   
   
   

   always @(posedge sys_clk or posedge reset)
    begin
      if(reset)
	     keyb_clk_samples<=6'b000000;
	  else
	     keyb_clk_samples<={keyb_clk,keyb_clk_samples[5:1]};
    end
		 

   always @(posedge sys_clk or posedge reset)
    begin
      if(reset)
	     keyb_data_reg<=11'b11111111111;
	  else if(!keyb_data_reg[0])
	    begin
          keyb_data_8bit<=keyb_data_reg[8:1];
		  keyb_data_reg<=11'b11111111111;
	    end
	  else if(keyb_clk_samples==6'b000111)
		 keyb_data_reg<={keyb_data,keyb_data_reg[10:1]};	 
    end
		 

   always @(*)
    begin
		case(keyb_data_8bit)
		    8'h16: c<=6'd1;
		    8'h1E: c<=6'd2;
		    8'h26: c<=6'd3;
		    8'h25: c<=6'd4;
		    8'h2E: c<=6'd5;
		    8'h36: c<=6'd6;
		    8'h3D: c<=6'd7;
		    8'h3E: c<=6'd8;
		    8'h46: c<=6'd9;
		    8'h45: c<=6'd0;
		    8'h69: c<=6'd1;
		    8'h72: c<=6'd2;
		    8'h7A: c<=6'd3;
		    8'h6B: c<=6'd4;
		    8'h73: c<=6'd5;
		    8'h74: c<=6'd6;
		    8'h6C: c<=6'd7;
		    8'h75: c<=6'd8;
		    8'h7D: c<=6'd9;
		    8'h70: c<=6'd0;
		    default: c<=6'b100000;
		endcase
	end
		 	 

   always @(*)
    begin
		case(mux)
		   -6'd9: 
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b0010000;
			 end			   
		   -6'd8:
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b0000000;
			 end	
		   -6'd7:
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b1111000;
			 end	
		   -6'd6:
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b0000010;
			 end	
		   -6'd5:
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b0010010;
			 end	
		   -6'd4:
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b0011001;
			 end	
		   -6'd3:
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b0110000;
			 end	
		   -6'd2:
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b0100100;
			 end	
		   -6'd1:
		     begin
               disp1<=7'b0111111; 
			   disp2<=7'b1111001;
			 end	
		    6'd0:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b1000000;
			 end	
		    6'd1:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b1111001;
			 end	
		    6'd2:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b0100100;
			 end
		    6'd3:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b0110000;
			 end
		    6'd4:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b0011001;
			 end
		    6'd5:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b0010010;
			 end
		    6'd6:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b0000010;
			 end
		    6'd7:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b1111000;
			 end
		    6'd8:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b0000000;
			 end
		    6'd9:
			 begin
               disp1<=7'b1111111; 
			   disp2<=7'b0010000;
			 end
		    6'd10:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b1000000;
			 end
		    6'd11:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b1111001;
			 end
		    6'd12:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b0100100;
			 end
		    6'd13:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b0110000;
			 end
		    6'd14:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b0011001;
			 end
		    6'd15:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b0010010;
			 end
		    6'd16:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b0000010;
			 end
		    6'd17:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b1111000;
			 end
		    6'd18:
			 begin
               disp1<=7'b1111001; 
			   disp2<=7'b0000000;
			 end
		    default:
			 begin
               disp1<=7'b0000100; 
			   disp2<=7'b0000100;
			 end
		endcase
	end	 
		 	 

	always @(posedge sys_clk or posedge reset)
	 begin
	  if(reset)
	     begin		
			HEX2<=7'b1111111;
			HEX3<=7'b1111111;
			HEX4<=7'b1111111;
			HEX5<=7'b1111111;
			HEX6<=7'b1111111;
			HEX7<=7'b1111111;
			next_calc_state<=WAIT_OPERAND1;
		 end
	  else if(!keyb_data_reg[0])
        case(next_calc_state)
		   WAIT_OPERAND1: begin
							  HEX2<=7'b1111111;
							  HEX3<=7'b1111111;
							  HEX4<=7'b1111111;
							  HEX5<=7'b1111111;
							  HEX6<=7'b1111111;
							  if(c[5]!=1'b1)
								  begin
									 a<=c;
									 next_calc_state<=WAIT_F0;
								  end
							 HEX7<=disp2;
							 state<=WAIT_OPERAND1;
					      end
		   WAIT_OPERATOR: begin
							 case(keyb_data_8bit)
								8'h79: begin
										   HEX6<=7'b0111001;
										   op<=1'b0;
										   next_calc_state<=WAIT_F0;
										 end
								8'h7B: begin
										   HEX6<=7'b0111111;
										   op<=1'b1;
										   next_calc_state<=WAIT_F0;
										 end
								default: HEX6<=7'b0000100;
							 endcase
							 state<=WAIT_OPERATOR;
						  end 					
		   WAIT_OPERAND2: begin
							   if(c[5]!=1'b1)
									begin
									   b<=c;
									   next_calc_state<=WAIT_F0;
									end   
							   HEX5<=disp2;
							   state<=WAIT_OPERAND2;
			              end 
		   WAIT_EQ: begin
					   if(keyb_data_8bit==8'h55)
							begin
							   HEX4<=7'b0111110;
							   HEX3<=disp1;
							   HEX2<=disp2;
							   next_calc_state<=WAIT_F0;
							end
					   else
							HEX4<=7'b0000100;
					   state<=WAIT_EQ;
					end
		   WAIT_F0: begin
					  if(keyb_data_8bit==8'hF0)
						next_calc_state<=AFTER_F0;
			        end
		   AFTER_F0: begin
						case(state)
						   WAIT_OPERAND1:next_calc_state<=WAIT_OPERATOR; 
						   WAIT_OPERATOR:next_calc_state<=WAIT_OPERAND2;
						   WAIT_OPERAND2:next_calc_state<=WAIT_EQ;
						   default:next_calc_state<=WAIT_OPERAND1;
						endcase   
		             end   
		   default: begin               
					   HEX2<=7'b1111111;
					   HEX3<=7'b1111111;
					   HEX4<=7'b1111111;
					   HEX5<=7'b1111111;
					   HEX6<=7'b1111111;
					   HEX7<=7'b1111111;
					   next_calc_state<=WAIT_OPERAND1;
					end
		endcase
	 end
endmodule