data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v
1: b'%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:29: Cannot find include file: sys.h\n`include "sys.h" // system level definition file which contains the  \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.v\n             data/full_repos/permissive/458737381/src/verilog-parser/tests,data/full_repos/permissive/458737381/sys.h.sv\n             sys.h\n             sys.h.v\n             sys.h.sv\n             obj_dir/sys.h\n             obj_dir/sys.h.v\n             obj_dir/sys.h.sv\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:31: Cannot find include file: iop.h\n`include        "iop.h" \n                ^~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:81: Define or directive not defined: \'`UCB_64PAY_PKT_WIDTH\'\n   input [`UCB_64PAY_PKT_WIDTH-1:0]c2i_packet;  \n          ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:83: Define or directive not defined: \'`CLK_IOB_WIDTH\'\n   input [`CLK_IOB_WIDTH-1:0]clk_iob_data;  \n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:112: Define or directive not defined: \'`DRAM_IOB_WIDTH\'\n   input [`DRAM_IOB_WIDTH-1:0]dram02_iob_data;  \n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:115: Define or directive not defined: \'`DRAM_IOB_WIDTH\'\n   input [`DRAM_IOB_WIDTH-1:0]dram13_iob_data;  \n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:119: Define or directive not defined: \'`IOB_CLK_WIDTH\'\n   input [`IOB_CLK_WIDTH-1:0]iob_clk_data;  \n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:122: Define or directive not defined: \'`IOB_DRAM_WIDTH\'\n   input [`IOB_DRAM_WIDTH-1:0]iob_dram02_data;  \n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:125: Define or directive not defined: \'`IOB_DRAM_WIDTH\'\n   input [`IOB_DRAM_WIDTH-1:0]iob_dram13_data;  \n          ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:128: Define or directive not defined: \'`IOB_JBI_WIDTH\'\n   input [`IOB_JBI_WIDTH-1:0]iob_jbi_pio_data;  \n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:131: Define or directive not defined: \'`IOB_SPI_WIDTH\'\n   input [`IOB_SPI_WIDTH-1:0]iob_jbi_spi_data;  \n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:134: Define or directive not defined: \'`IOB_TAP_WIDTH\'\n   input [`IOB_TAP_WIDTH-1:0]iob_tap_data;  \n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:137: Define or directive not defined: \'`JBI_IOB_WIDTH\'\n   input [`JBI_IOB_WIDTH-1:0]jbi_iob_pio_data;  \n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:140: Define or directive not defined: \'`SPI_IOB_WIDTH\'\n   input [`SPI_IOB_WIDTH-1:0]jbi_iob_spi_data;  \n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:149: Define or directive not defined: \'`TAP_IOB_WIDTH\'\n   input [`TAP_IOB_WIDTH-1:0]tap_iob_data;  \n          ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:171: Define or directive not defined: \'`IOB_L2_VIS_BUF_INDEX\'\n   output [`IOB_L2_VIS_BUF_INDEX-1:0]l2_vis_buf_head_ptr; \n           ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:174: Define or directive not defined: \'`IOB_L2_VIS_BUF_INDEX\'\n   output [`IOB_L2_VIS_BUF_INDEX-1:0]l2_vis_buf_tail_ptr; \n           ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:186: Define or directive not defined: \'`IOB_JBI_WIDTH\'\n   wire [`IOB_JBI_WIDTH-1:0] iob_jbi_pio_data_d1;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:187: Define or directive not defined: \'`JBI_IOB_WIDTH\'\n   wire [`JBI_IOB_WIDTH-1:0] jbi_iob_pio_data_d1;\n         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:205: Define or directive not defined: \'`IOB_JBI_WIDTH\'\n   iobdg_dbg_iob iobdg_dbg_iob (.iob_jbi_pio_data_d1(iob_jbi_pio_data_d1[`IOB_JBI_WIDTH-1:0]),\n                                                                         ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:206: Define or directive not defined: \'`JBI_IOB_WIDTH\'\n    .jbi_iob_pio_data_d1(jbi_iob_pio_data_d1[`JBI_IOB_WIDTH-1:0]),\n                                             ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:213: Define or directive not defined: \'`UCB_64PAY_PKT_WIDTH\'\n    .c2i_packet(c2i_packet[`UCB_64PAY_PKT_WIDTH-1:0]),\n                           ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:217: Define or directive not defined: \'`IOB_CLK_WIDTH\'\n    .iob_clk_data(iob_clk_data[`IOB_CLK_WIDTH-1:0]),\n                               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:220: Define or directive not defined: \'`IOB_DRAM_WIDTH\'\n    .iob_dram02_data(iob_dram02_data[`IOB_DRAM_WIDTH-1:0]),\n                                     ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:223: Define or directive not defined: \'`IOB_DRAM_WIDTH\'\n    .iob_dram13_data(iob_dram13_data[`IOB_DRAM_WIDTH-1:0]),\n                                     ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:226: Define or directive not defined: \'`IOB_JBI_WIDTH\'\n    .iob_jbi_pio_data(iob_jbi_pio_data[`IOB_JBI_WIDTH-1:0]),\n                                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:229: Define or directive not defined: \'`IOB_SPI_WIDTH\'\n    .iob_jbi_spi_data(iob_jbi_spi_data[`IOB_SPI_WIDTH-1:0]),\n                                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:232: Define or directive not defined: \'`IOB_TAP_WIDTH\'\n    .iob_tap_data(iob_tap_data[`IOB_TAP_WIDTH-1:0]),\n                               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:235: Define or directive not defined: \'`CLK_IOB_WIDTH\'\n    .clk_iob_data(clk_iob_data[`CLK_IOB_WIDTH-1:0]),\n                               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:238: Define or directive not defined: \'`DRAM_IOB_WIDTH\'\n    .dram02_iob_data(dram02_iob_data[`DRAM_IOB_WIDTH-1:0]),\n                                     ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:241: Define or directive not defined: \'`DRAM_IOB_WIDTH\'\n    .dram13_iob_data(dram13_iob_data[`DRAM_IOB_WIDTH-1:0]),\n                                     ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:244: Define or directive not defined: \'`JBI_IOB_WIDTH\'\n    .jbi_iob_pio_data(jbi_iob_pio_data[`JBI_IOB_WIDTH-1:0]),\n                                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:247: Define or directive not defined: \'`SPI_IOB_WIDTH\'\n    .jbi_iob_spi_data(jbi_iob_spi_data[`SPI_IOB_WIDTH-1:0]),\n                                       ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:250: Define or directive not defined: \'`TAP_IOB_WIDTH\'\n    .tap_iob_data(tap_iob_data[`TAP_IOB_WIDTH-1:0]),\n                               ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:299: Define or directive not defined: \'`IOB_L2_VIS_BUF_INDEX\'\n         .l2_vis_buf_tail_ptr(l2_vis_buf_tail_ptr[`IOB_L2_VIS_BUF_INDEX-1:0]),\n                                                  ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/458737381/src/verilog-parser/tests/iobdg_dbg.v:300: Define or directive not defined: \'`IOB_L2_VIS_BUF_INDEX\'\n         .l2_vis_buf_head_ptr(l2_vis_buf_head_ptr[`IOB_L2_VIS_BUF_INDEX-1:0]),\n                                                  ^~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 36 error(s)\n'
module iobdg_dbg (

   l2_vis_buf_wr_lo_l, l2_vis_buf_wr_hi_l, l2_vis_buf_tail_ptr, 
   l2_vis_buf_rd_lo_l, l2_vis_buf_rd_hi_l, l2_vis_buf_head_ptr, 
   l2_vis_buf_din_lo, l2_vis_buf_din_hi, l2_vis_armin, 
   iob_jbi_dbg_lo_vld, iob_jbi_dbg_lo_data, iob_jbi_dbg_hi_vld, 
   iob_jbi_dbg_hi_data, iob_io_dbg_en, iob_io_dbg_data, 
   iob_io_dbg_ck_p, iob_io_dbg_ck_n, iob_clk_tr, iob_clk_l2_tr, 

   ucb_buf_acpt, tx_sync, tap_iob_vld, tap_iob_stall, tap_iob_data, 
   rx_sync, rst_l, l2_vis_buf_dout_lo, l2_vis_buf_dout_hi, 
   l2_dbgbus_23, l2_dbgbus_01, jbi_iob_spi_vld, jbi_iob_spi_stall, 
   jbi_iob_spi_data, jbi_iob_pio_vld, jbi_iob_pio_stall, 
   jbi_iob_pio_data, iob_tap_vld, iob_tap_stall, iob_tap_data, 
   iob_jbi_spi_vld, iob_jbi_spi_stall, iob_jbi_spi_data, 
   iob_jbi_pio_vld, iob_jbi_pio_stall, iob_jbi_pio_data, 
   iob_dram13_vld, iob_dram13_stall, iob_dram13_data, iob_dram02_vld, 
   iob_dram02_stall, iob_dram02_data, iob_clk_vld, iob_clk_stall, 
   iob_clk_data, io_trigin, dram13_iob_vld, dram13_iob_stall, 
   dram13_iob_data, dram02_iob_vld, dram02_iob_stall, 
   dram02_iob_data, dbg_en_23, dbg_en_01, 
   creg_dbg_l2_vis_trig_delay_s, creg_dbg_l2_vis_maskb_s, 
   creg_dbg_l2_vis_maska_s, creg_dbg_l2_vis_ctrl, 
   creg_dbg_l2_vis_cmpb_s, creg_dbg_l2_vis_cmpa_s, 
   creg_dbg_jbus_lo_mask1, creg_dbg_jbus_lo_mask0, 
   creg_dbg_jbus_lo_cnt1, creg_dbg_jbus_lo_cnt0, 
   creg_dbg_jbus_lo_cmp1, creg_dbg_jbus_lo_cmp0, 
   creg_dbg_jbus_hi_mask1, creg_dbg_jbus_hi_mask0, 
   creg_dbg_jbus_hi_cnt1, creg_dbg_jbus_hi_cnt0, 
   creg_dbg_jbus_hi_cmp1, creg_dbg_jbus_hi_cmp0, creg_dbg_jbus_ctrl, 
   creg_dbg_iob_vis_ctrl, creg_dbg_enet_idleval, creg_dbg_enet_ctrl, 
   cpu_rst_l, cpu_clk, clk_iob_vld, clk_iob_stall, clk_iob_data, clk, 
   c2i_packet
   );






   input [`UCB_64PAY_PKT_WIDTH-1:0]c2i_packet;
   input		clk;
   input [`CLK_IOB_WIDTH-1:0]clk_iob_data;
   input		clk_iob_stall;
   input		clk_iob_vld;
   input		cpu_clk;
   input		cpu_rst_l;
   input [63:0]		creg_dbg_enet_ctrl;
   input [63:0]		creg_dbg_enet_idleval;
   input [63:0]		creg_dbg_iob_vis_ctrl;
   input [63:0]		creg_dbg_jbus_ctrl;
   input [63:0]		creg_dbg_jbus_hi_cmp0;
   input [63:0]		creg_dbg_jbus_hi_cmp1;
   input [63:0]		creg_dbg_jbus_hi_cnt0;
   input [63:0]		creg_dbg_jbus_hi_cnt1;
   input [63:0]		creg_dbg_jbus_hi_mask0;
   input [63:0]		creg_dbg_jbus_hi_mask1;
   input [63:0]		creg_dbg_jbus_lo_cmp0;
   input [63:0]		creg_dbg_jbus_lo_cmp1;
   input [63:0]		creg_dbg_jbus_lo_cnt0;
   input [63:0]		creg_dbg_jbus_lo_cnt1;
   input [63:0]		creg_dbg_jbus_lo_mask0;
   input [63:0]		creg_dbg_jbus_lo_mask1;
   input [63:0]		creg_dbg_l2_vis_cmpa_s;
   input [63:0]		creg_dbg_l2_vis_cmpb_s;
   input [63:0]		creg_dbg_l2_vis_ctrl;
   input [63:0]		creg_dbg_l2_vis_maska_s;
   input [63:0]		creg_dbg_l2_vis_maskb_s;
   input [63:0]		creg_dbg_l2_vis_trig_delay_s;
   input		dbg_en_01;
   input		dbg_en_23;
   input [`DRAM_IOB_WIDTH-1:0]dram02_iob_data;
   input		dram02_iob_stall;
   input		dram02_iob_vld;
   input [`DRAM_IOB_WIDTH-1:0]dram13_iob_data;
   input		dram13_iob_stall;
   input		dram13_iob_vld;
   input		io_trigin;
   input [`IOB_CLK_WIDTH-1:0]iob_clk_data;
   input		iob_clk_stall;
   input		iob_clk_vld;
   input [`IOB_DRAM_WIDTH-1:0]iob_dram02_data;
   input		iob_dram02_stall;
   input		iob_dram02_vld;
   input [`IOB_DRAM_WIDTH-1:0]iob_dram13_data;
   input		iob_dram13_stall;
   input		iob_dram13_vld;
   input [`IOB_JBI_WIDTH-1:0]iob_jbi_pio_data;
   input		iob_jbi_pio_stall;
   input		iob_jbi_pio_vld;
   input [`IOB_SPI_WIDTH-1:0]iob_jbi_spi_data;
   input		iob_jbi_spi_stall;
   input		iob_jbi_spi_vld;
   input [`IOB_TAP_WIDTH-1:0]iob_tap_data;
   input		iob_tap_stall;
   input		iob_tap_vld;
   input [`JBI_IOB_WIDTH-1:0]jbi_iob_pio_data;
   input		jbi_iob_pio_stall;
   input		jbi_iob_pio_vld;
   input [`SPI_IOB_WIDTH-1:0]jbi_iob_spi_data;
   input		jbi_iob_spi_stall;
   input		jbi_iob_spi_vld;
   input [39:0]		l2_dbgbus_01;
   input [39:0]		l2_dbgbus_23;
   input [64:0]		l2_vis_buf_dout_hi;
   input [64:0]		l2_vis_buf_dout_lo;
   input		rst_l;
   input		rx_sync;
   input [`TAP_IOB_WIDTH-1:0]tap_iob_data;
   input		tap_iob_stall;
   input		tap_iob_vld;
   input		tx_sync;
   input		ucb_buf_acpt;




   output		iob_clk_l2_tr;
   output		iob_clk_tr;
   output [2:0]		iob_io_dbg_ck_n;
   output [2:0]		iob_io_dbg_ck_p;
   output [39:0]	iob_io_dbg_data;
   output		iob_io_dbg_en;
   output [47:0]	iob_jbi_dbg_hi_data;
   output		iob_jbi_dbg_hi_vld;
   output [47:0]	iob_jbi_dbg_lo_data;
   output		iob_jbi_dbg_lo_vld;
   output		l2_vis_armin;
   output [64:0]	l2_vis_buf_din_hi;
   output [64:0]	l2_vis_buf_din_lo;
   output [`IOB_L2_VIS_BUF_INDEX-1:0]l2_vis_buf_head_ptr;
   output		l2_vis_buf_rd_hi_l;
   output		l2_vis_buf_rd_lo_l;
   output [`IOB_L2_VIS_BUF_INDEX-1:0]l2_vis_buf_tail_ptr;
   output		l2_vis_buf_wr_hi_l;
   output		l2_vis_buf_wr_lo_l;




   wire [43:0]		iob_dbg_bus;
   wire [39:0]		l2_dbg_data;
   wire			l2_dbg_vld;


   wire [`IOB_JBI_WIDTH-1:0] iob_jbi_pio_data_d1;
   wire [`JBI_IOB_WIDTH-1:0] jbi_iob_pio_data_d1;
       
   wire [5:0] 		iob_vld_bus;
   wire [5:0] 		iob_stall_bus;
   wire [5:0] 		iob_vld_bus_d1;
   wire [5:0] 		iob_stall_bus_d1;
   wire [5:0] 		iob_vld_qual_bus;
   wire [5:0] 		iob_soh_bus;
   
   wire [7:0]		l2_dbg_tstamp;

   




   iobdg_dbg_iob iobdg_dbg_iob (.iob_jbi_pio_data_d1(iob_jbi_pio_data_d1[`IOB_JBI_WIDTH-1:0]),
				.jbi_iob_pio_data_d1(jbi_iob_pio_data_d1[`JBI_IOB_WIDTH-1:0]),


				.iob_dbg_bus(iob_dbg_bus[43:0]),

				.rst_l	(rst_l),
				.clk	(clk),
				.c2i_packet(c2i_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
				.ucb_buf_acpt(ucb_buf_acpt),
				.creg_dbg_iob_vis_ctrl(creg_dbg_iob_vis_ctrl[63:0]),
				.iob_clk_vld(iob_clk_vld),
				.iob_clk_data(iob_clk_data[`IOB_CLK_WIDTH-1:0]),
				.clk_iob_stall(clk_iob_stall),
				.iob_dram02_vld(iob_dram02_vld),
				.iob_dram02_data(iob_dram02_data[`IOB_DRAM_WIDTH-1:0]),
				.dram02_iob_stall(dram02_iob_stall),
				.iob_dram13_vld(iob_dram13_vld),
				.iob_dram13_data(iob_dram13_data[`IOB_DRAM_WIDTH-1:0]),
				.dram13_iob_stall(dram13_iob_stall),
				.iob_jbi_pio_vld(iob_jbi_pio_vld),
				.iob_jbi_pio_data(iob_jbi_pio_data[`IOB_JBI_WIDTH-1:0]),
				.jbi_iob_pio_stall(jbi_iob_pio_stall),
				.iob_jbi_spi_vld(iob_jbi_spi_vld),
				.iob_jbi_spi_data(iob_jbi_spi_data[`IOB_SPI_WIDTH-1:0]),
				.jbi_iob_spi_stall(jbi_iob_spi_stall),
				.iob_tap_vld(iob_tap_vld),
				.iob_tap_data(iob_tap_data[`IOB_TAP_WIDTH-1:0]),
				.tap_iob_stall(tap_iob_stall),
				.clk_iob_vld(clk_iob_vld),
				.clk_iob_data(clk_iob_data[`CLK_IOB_WIDTH-1:0]),
				.iob_clk_stall(iob_clk_stall),
				.dram02_iob_vld(dram02_iob_vld),
				.dram02_iob_data(dram02_iob_data[`DRAM_IOB_WIDTH-1:0]),
				.iob_dram02_stall(iob_dram02_stall),
				.dram13_iob_vld(dram13_iob_vld),
				.dram13_iob_data(dram13_iob_data[`DRAM_IOB_WIDTH-1:0]),
				.iob_dram13_stall(iob_dram13_stall),
				.jbi_iob_pio_vld(jbi_iob_pio_vld),
				.jbi_iob_pio_data(jbi_iob_pio_data[`JBI_IOB_WIDTH-1:0]),
				.iob_jbi_pio_stall(iob_jbi_pio_stall),
				.jbi_iob_spi_vld(jbi_iob_spi_vld),
				.jbi_iob_spi_data(jbi_iob_spi_data[`SPI_IOB_WIDTH-1:0]),
				.iob_jbi_spi_stall(iob_jbi_spi_stall),
				.tap_iob_vld(tap_iob_vld),
				.tap_iob_data(tap_iob_data[`TAP_IOB_WIDTH-1:0]),
				.iob_tap_stall(iob_tap_stall));

   assign 	       iob_vld_bus = {iob_dbg_bus[43],
				      iob_dbg_bus[41],
				      iob_dbg_bus[39],
				      iob_dbg_bus[37],
				      iob_dbg_bus[35],
				      iob_dbg_bus[33]};
   
   assign 	       iob_stall_bus = {iob_dbg_bus[42],
					iob_dbg_bus[40],
					iob_dbg_bus[38],
					iob_dbg_bus[36],
					iob_dbg_bus[34],
					iob_dbg_bus[32]};
   
   dff_ns #(6) iob_vld_bus_d1_ff (.din(iob_vld_bus),
				  .clk(clk),
				  .q(iob_vld_bus_d1));
   
   dff_ns #(6) iob_stall_bus_d1_ff (.din(iob_stall_bus),
				    .clk(clk),
				    .q(iob_stall_bus_d1));
   
   assign 	       iob_vld_qual_bus = iob_vld_bus & ~iob_stall_bus_d1;

   assign 	       iob_soh_bus = ~iob_vld_bus_d1 & iob_vld_bus;
   
   


   iobdg_dbg_l2 iobdg_dbg_l2 (


			      .l2_dbg_vld(l2_dbg_vld),
			      .l2_dbg_tstamp({l2_dbg_tstamp[7:0]}),
			      .l2_dbg_data(l2_dbg_data[39:0]),
			      .iob_clk_l2_tr(iob_clk_l2_tr),
			      .l2_vis_buf_wr_lo_l(l2_vis_buf_wr_lo_l),
			      .l2_vis_buf_wr_hi_l(l2_vis_buf_wr_hi_l),
			      .l2_vis_buf_rd_lo_l(l2_vis_buf_rd_lo_l),
			      .l2_vis_buf_rd_hi_l(l2_vis_buf_rd_hi_l),
			      .l2_vis_buf_tail_ptr(l2_vis_buf_tail_ptr[`IOB_L2_VIS_BUF_INDEX-1:0]),
			      .l2_vis_buf_head_ptr(l2_vis_buf_head_ptr[`IOB_L2_VIS_BUF_INDEX-1:0]),
			      .l2_vis_buf_din_lo(l2_vis_buf_din_lo[64:0]),
			      .l2_vis_buf_din_hi(l2_vis_buf_din_hi[64:0]),

			      .cpu_rst_l(cpu_rst_l),
			      .rst_l	(rst_l),
			      .cpu_clk	(cpu_clk),
			      .clk	(clk),
			      .tx_sync	(tx_sync),
			      .rx_sync	(rx_sync),
			      .l2_dbgbus_01(l2_dbgbus_01[39:0]),
			      .l2_dbgbus_23(l2_dbgbus_23[39:0]),
			      .dbg_en_01(dbg_en_01),
			      .dbg_en_23(dbg_en_23),
			      .creg_dbg_l2_vis_ctrl(creg_dbg_l2_vis_ctrl[63:0]),
			      .creg_dbg_l2_vis_maska_s(creg_dbg_l2_vis_maska_s[63:0]),
			      .creg_dbg_l2_vis_cmpa_s(creg_dbg_l2_vis_cmpa_s[63:0]),
			      .creg_dbg_l2_vis_maskb_s(creg_dbg_l2_vis_maskb_s[63:0]),
			      .creg_dbg_l2_vis_cmpb_s(creg_dbg_l2_vis_cmpb_s[63:0]),
			      .creg_dbg_l2_vis_trig_delay_s(creg_dbg_l2_vis_trig_delay_s[63:0]),
			      .l2_vis_buf_dout_lo(l2_vis_buf_dout_lo[64:0]),
			      .l2_vis_buf_dout_hi(l2_vis_buf_dout_hi[64:0]));





   iobdg_dbg_porta iobdg_dbg_porta (


				    .iob_io_dbg_data(iob_io_dbg_data[39:0]),
				    .iob_io_dbg_en(iob_io_dbg_en),
				    .iob_io_dbg_ck_p(iob_io_dbg_ck_p[2:0]),
				    .iob_io_dbg_ck_n(iob_io_dbg_ck_n[2:0]),
				    .l2_vis_armin(l2_vis_armin),
				    .iob_clk_tr(iob_clk_tr),

				    .rst_l(rst_l),
				    .clk(clk),
				    .src0_data(l2_dbg_data[39:0]),
				    .src1_data({l2_dbg_data[39:30],l2_dbg_tstamp[7:0],l2_dbg_data[21:0]}),
				    .src2_data(iob_dbg_bus[39:0]),
				    .src3_data({1'b0,|iob_soh_bus[5:0],iob_vld_qual_bus[5:0],iob_dbg_bus[31:0]}),
				    .src4_data({iob_dbg_bus[39:35],iob_dbg_bus[41],iob_dbg_bus[33:0]}),
				    .src0_vld(l2_dbg_vld),
				    .src1_vld(l2_dbg_vld),
				    .src2_vld(1'b1),
				    .src3_vld({|iob_vld_qual_bus[5:0]}),
				    .src4_vld(iob_dbg_bus[43]),
				    .creg_dbg_enet_ctrl(creg_dbg_enet_ctrl[63:0]),
				    .creg_dbg_enet_idleval(creg_dbg_enet_idleval[63:0]),
				    .io_trigin(io_trigin));

   



   iobdg_dbg_portb iobdg_dbg_portb_hi (


				       .dbg_data(iob_jbi_dbg_hi_data[47:0]),
				       .dbg_vld(iob_jbi_dbg_hi_vld),

				       .rst_l(rst_l),
				       .clk(clk),
				       .src0_data({l2_dbg_vld,l2_dbg_tstamp[7:0],l2_dbg_data[39:0]}),
				       .src2_data({iob_vld_qual_bus[4],4'b0,iob_soh_bus[5:4],iob_vld_qual_bus[5:4],iob_dbg_bus[39:0]}),
				       .src3_data({iob_vld_qual_bus[4],4'b0,iob_soh_bus[5:4],iob_vld_qual_bus[5:4],iob_soh_bus[3:0],iob_vld_qual_bus[3:0],iob_dbg_bus[31:0]}),
				       .src4_data({iob_dbg_bus[40],4'b0,iob_dbg_bus[43:0]}),
				       .src0_vld(l2_dbg_vld),
				       .src2_vld({|iob_vld_qual_bus[5:4]}),
				       .src3_vld({|iob_vld_qual_bus[5:0]}),
				       .src4_vld(1'b1),
				       .i_am_hi(1'b1),
				       .creg_dbg_jbus_ctrl(creg_dbg_jbus_ctrl[63:0]),
				       .creg_dbg_jbus_mask0(creg_dbg_jbus_hi_mask0[63:0]),
				       .creg_dbg_jbus_cmp0(creg_dbg_jbus_hi_cmp0[63:0]),
				       .creg_dbg_jbus_cnt0(creg_dbg_jbus_hi_cnt0[63:0]),
				       .creg_dbg_jbus_mask1(creg_dbg_jbus_hi_mask1[63:0]),
				       .creg_dbg_jbus_cmp1(creg_dbg_jbus_hi_cmp1[63:0]),
				       .creg_dbg_jbus_cnt1(creg_dbg_jbus_hi_cnt1[63:0]));

   



   iobdg_dbg_portb iobdg_dbg_portb_lo (


				       .dbg_data(iob_jbi_dbg_lo_data[47:0]),
				       .dbg_vld(iob_jbi_dbg_lo_vld),

				       .rst_l(rst_l),
				       .clk(clk),
				       .src0_data({l2_dbg_vld,l2_dbg_tstamp[7:0],l2_dbg_data[39:0]}),
				       .src2_data({iob_vld_qual_bus[4],4'b0,iob_soh_bus[5:4],iob_vld_qual_bus[5:4],jbi_iob_pio_data_d1[7:0],iob_jbi_pio_data_d1[31:0]}),
				       .src3_data({iob_vld_qual_bus[4],4'b0,iob_soh_bus[5:4],iob_vld_qual_bus[5:4],iob_soh_bus[3:0],iob_vld_qual_bus[3:0],iob_dbg_bus[31:0]}),
				       .src4_data({iob_dbg_bus[40],4'b0,iob_dbg_bus[43:0]}),
				       .src0_vld(l2_dbg_vld),
				       .src2_vld({|iob_vld_qual_bus[5:4]}),
				       .src3_vld({|iob_vld_qual_bus[5:0]}),
				       .src4_vld(1'b1),
				       .i_am_hi(1'b0),
				       .creg_dbg_jbus_ctrl(creg_dbg_jbus_ctrl[63:0]),
				       .creg_dbg_jbus_mask0(creg_dbg_jbus_lo_mask0[63:0]),
				       .creg_dbg_jbus_cmp0(creg_dbg_jbus_lo_cmp0[63:0]),
				       .creg_dbg_jbus_cnt0(creg_dbg_jbus_lo_cnt0[63:0]),
				       .creg_dbg_jbus_mask1(creg_dbg_jbus_lo_mask1[63:0]),
				       .creg_dbg_jbus_cmp1(creg_dbg_jbus_lo_cmp1[63:0]),
				       .creg_dbg_jbus_cnt1(creg_dbg_jbus_lo_cnt1[63:0]));

   
endmodule
module iobdg_dbg (

   l2_vis_buf_wr_lo_l, l2_vis_buf_wr_hi_l, l2_vis_buf_tail_ptr, 
   l2_vis_buf_rd_lo_l, l2_vis_buf_rd_hi_l, l2_vis_buf_head_ptr, 
   l2_vis_buf_din_lo, l2_vis_buf_din_hi, l2_vis_armin, 
   iob_jbi_dbg_lo_vld, iob_jbi_dbg_lo_data, iob_jbi_dbg_hi_vld, 
   iob_jbi_dbg_hi_data, iob_io_dbg_en, iob_io_dbg_data, 
   iob_io_dbg_ck_p, iob_io_dbg_ck_n, iob_clk_tr, iob_clk_l2_tr, 

   ucb_buf_acpt, tx_sync, tap_iob_vld, tap_iob_stall, tap_iob_data, 
   rx_sync, rst_l, l2_vis_buf_dout_lo, l2_vis_buf_dout_hi, 
   l2_dbgbus_23, l2_dbgbus_01, jbi_iob_spi_vld, jbi_iob_spi_stall, 
   jbi_iob_spi_data, jbi_iob_pio_vld, jbi_iob_pio_stall, 
   jbi_iob_pio_data, iob_tap_vld, iob_tap_stall, iob_tap_data, 
   iob_jbi_spi_vld, iob_jbi_spi_stall, iob_jbi_spi_data, 
   iob_jbi_pio_vld, iob_jbi_pio_stall, iob_jbi_pio_data, 
   iob_dram13_vld, iob_dram13_stall, iob_dram13_data, iob_dram02_vld, 
   iob_dram02_stall, iob_dram02_data, iob_clk_vld, iob_clk_stall, 
   iob_clk_data, io_trigin, dram13_iob_vld, dram13_iob_stall, 
   dram13_iob_data, dram02_iob_vld, dram02_iob_stall, 
   dram02_iob_data, dbg_en_23, dbg_en_01, 
   creg_dbg_l2_vis_trig_delay_s, creg_dbg_l2_vis_maskb_s, 
   creg_dbg_l2_vis_maska_s, creg_dbg_l2_vis_ctrl, 
   creg_dbg_l2_vis_cmpb_s, creg_dbg_l2_vis_cmpa_s, 
   creg_dbg_jbus_lo_mask1, creg_dbg_jbus_lo_mask0, 
   creg_dbg_jbus_lo_cnt1, creg_dbg_jbus_lo_cnt0, 
   creg_dbg_jbus_lo_cmp1, creg_dbg_jbus_lo_cmp0, 
   creg_dbg_jbus_hi_mask1, creg_dbg_jbus_hi_mask0, 
   creg_dbg_jbus_hi_cnt1, creg_dbg_jbus_hi_cnt0, 
   creg_dbg_jbus_hi_cmp1, creg_dbg_jbus_hi_cmp0, creg_dbg_jbus_ctrl, 
   creg_dbg_iob_vis_ctrl, creg_dbg_enet_idleval, creg_dbg_enet_ctrl, 
   cpu_rst_l, cpu_clk, clk_iob_vld, clk_iob_stall, clk_iob_data, clk, 
   c2i_packet
   );







   input [`UCB_64PAY_PKT_WIDTH-1:0]c2i_packet;
   input		clk;
   input [`CLK_IOB_WIDTH-1:0]clk_iob_data;
   input		clk_iob_stall;
   input		clk_iob_vld;
   input		cpu_clk;
   input		cpu_rst_l;
   input [63:0]		creg_dbg_enet_ctrl;
   input [63:0]		creg_dbg_enet_idleval;
   input [63:0]		creg_dbg_iob_vis_ctrl;
   input [63:0]		creg_dbg_jbus_ctrl;
   input [63:0]		creg_dbg_jbus_hi_cmp0;
   input [63:0]		creg_dbg_jbus_hi_cmp1;
   input [63:0]		creg_dbg_jbus_hi_cnt0;
   input [63:0]		creg_dbg_jbus_hi_cnt1;
   input [63:0]		creg_dbg_jbus_hi_mask0;
   input [63:0]		creg_dbg_jbus_hi_mask1;
   input [63:0]		creg_dbg_jbus_lo_cmp0;
   input [63:0]		creg_dbg_jbus_lo_cmp1;
   input [63:0]		creg_dbg_jbus_lo_cnt0;
   input [63:0]		creg_dbg_jbus_lo_cnt1;
   input [63:0]		creg_dbg_jbus_lo_mask0;
   input [63:0]		creg_dbg_jbus_lo_mask1;
   input [63:0]		creg_dbg_l2_vis_cmpa_s;
   input [63:0]		creg_dbg_l2_vis_cmpb_s;
   input [63:0]		creg_dbg_l2_vis_ctrl;
   input [63:0]		creg_dbg_l2_vis_maska_s;
   input [63:0]		creg_dbg_l2_vis_maskb_s;
   input [63:0]		creg_dbg_l2_vis_trig_delay_s;
   input		dbg_en_01;
   input		dbg_en_23;
   input [`DRAM_IOB_WIDTH-1:0]dram02_iob_data;
   input		dram02_iob_stall;
   input		dram02_iob_vld;
   input [`DRAM_IOB_WIDTH-1:0]dram13_iob_data;
   input		dram13_iob_stall;
   input		dram13_iob_vld;
   input		io_trigin;
   input [`IOB_CLK_WIDTH-1:0]iob_clk_data;
   input		iob_clk_stall;
   input		iob_clk_vld;
   input [`IOB_DRAM_WIDTH-1:0]iob_dram02_data;
   input		iob_dram02_stall;
   input		iob_dram02_vld;
   input [`IOB_DRAM_WIDTH-1:0]iob_dram13_data;
   input		iob_dram13_stall;
   input		iob_dram13_vld;
   input [`IOB_JBI_WIDTH-1:0]iob_jbi_pio_data;
   input		iob_jbi_pio_stall;
   input		iob_jbi_pio_vld;
   input [`IOB_SPI_WIDTH-1:0]iob_jbi_spi_data;
   input		iob_jbi_spi_stall;
   input		iob_jbi_spi_vld;
   input [`IOB_TAP_WIDTH-1:0]iob_tap_data;
   input		iob_tap_stall;
   input		iob_tap_vld;
   input [`JBI_IOB_WIDTH-1:0]jbi_iob_pio_data;
   input		jbi_iob_pio_stall;
   input		jbi_iob_pio_vld;
   input [`SPI_IOB_WIDTH-1:0]jbi_iob_spi_data;
   input		jbi_iob_spi_stall;
   input		jbi_iob_spi_vld;
   input [39:0]		l2_dbgbus_01;
   input [39:0]		l2_dbgbus_23;
   input [64:0]		l2_vis_buf_dout_hi;
   input [64:0]		l2_vis_buf_dout_lo;
   input		rst_l;
   input		rx_sync;
   input [`TAP_IOB_WIDTH-1:0]tap_iob_data;
   input		tap_iob_stall;
   input		tap_iob_vld;
   input		tx_sync;
   input		ucb_buf_acpt;




   output		iob_clk_l2_tr;
   output		iob_clk_tr;
   output [2:0]		iob_io_dbg_ck_n;
   output [2:0]		iob_io_dbg_ck_p;
   output [39:0]	iob_io_dbg_data;
   output		iob_io_dbg_en;
   output [47:0]	iob_jbi_dbg_hi_data;
   output		iob_jbi_dbg_hi_vld;
   output [47:0]	iob_jbi_dbg_lo_data;
   output		iob_jbi_dbg_lo_vld;
   output		l2_vis_armin;
   output [64:0]	l2_vis_buf_din_hi;
   output [64:0]	l2_vis_buf_din_lo;
   output [`IOB_L2_VIS_BUF_INDEX-1:0]l2_vis_buf_head_ptr;
   output		l2_vis_buf_rd_hi_l;
   output		l2_vis_buf_rd_lo_l;
   output [`IOB_L2_VIS_BUF_INDEX-1:0]l2_vis_buf_tail_ptr;
   output		l2_vis_buf_wr_hi_l;
   output		l2_vis_buf_wr_lo_l;




   wire [43:0]		iob_dbg_bus;
   wire [39:0]		l2_dbg_data;
   wire			l2_dbg_vld;


   wire [`IOB_JBI_WIDTH-1:0] iob_jbi_pio_data_d1;
   wire [`JBI_IOB_WIDTH-1:0] jbi_iob_pio_data_d1;
       
   wire [5:0] 		iob_vld_bus;
   wire [5:0] 		iob_stall_bus;
   wire [5:0] 		iob_vld_bus_d1;
   wire [5:0] 		iob_stall_bus_d1;
   wire [5:0] 		iob_vld_qual_bus;
   wire [5:0] 		iob_soh_bus;
   
   wire [7:0]		l2_dbg_tstamp;

   




   iobdg_dbg_iob iobdg_dbg_iob (.iob_jbi_pio_data_d1(iob_jbi_pio_data_d1[`IOB_JBI_WIDTH-1:0]),
				.jbi_iob_pio_data_d1(jbi_iob_pio_data_d1[`JBI_IOB_WIDTH-1:0]),


				.iob_dbg_bus(iob_dbg_bus[43:0]),

				.rst_l	(rst_l),
				.clk	(clk),
				.c2i_packet(c2i_packet[`UCB_64PAY_PKT_WIDTH-1:0]),
				.ucb_buf_acpt(ucb_buf_acpt),
				.creg_dbg_iob_vis_ctrl(creg_dbg_iob_vis_ctrl[63:0]),
				.iob_clk_vld(iob_clk_vld),
				.iob_clk_data(iob_clk_data[`IOB_CLK_WIDTH-1:0]),
				.clk_iob_stall(clk_iob_stall),
				.iob_dram02_vld(iob_dram02_vld),
				.iob_dram02_data(iob_dram02_data[`IOB_DRAM_WIDTH-1:0]),
				.dram02_iob_stall(dram02_iob_stall),
				.iob_dram13_vld(iob_dram13_vld),
				.iob_dram13_data(iob_dram13_data[`IOB_DRAM_WIDTH-1:0]),
				.dram13_iob_stall(dram13_iob_stall),
				.iob_jbi_pio_vld(iob_jbi_pio_vld),
				.iob_jbi_pio_data(iob_jbi_pio_data[`IOB_JBI_WIDTH-1:0]),
				.jbi_iob_pio_stall(jbi_iob_pio_stall),
				.iob_jbi_spi_vld(iob_jbi_spi_vld),
				.iob_jbi_spi_data(iob_jbi_spi_data[`IOB_SPI_WIDTH-1:0]),
				.jbi_iob_spi_stall(jbi_iob_spi_stall),
				.iob_tap_vld(iob_tap_vld),
				.iob_tap_data(iob_tap_data[`IOB_TAP_WIDTH-1:0]),
				.tap_iob_stall(tap_iob_stall),
				.clk_iob_vld(clk_iob_vld),
				.clk_iob_data(clk_iob_data[`CLK_IOB_WIDTH-1:0]),
				.iob_clk_stall(iob_clk_stall),
				.dram02_iob_vld(dram02_iob_vld),
				.dram02_iob_data(dram02_iob_data[`DRAM_IOB_WIDTH-1:0]),
				.iob_dram02_stall(iob_dram02_stall),
				.dram13_iob_vld(dram13_iob_vld),
				.dram13_iob_data(dram13_iob_data[`DRAM_IOB_WIDTH-1:0]),
				.iob_dram13_stall(iob_dram13_stall),
				.jbi_iob_pio_vld(jbi_iob_pio_vld),
				.jbi_iob_pio_data(jbi_iob_pio_data[`JBI_IOB_WIDTH-1:0]),
				.iob_jbi_pio_stall(iob_jbi_pio_stall),
				.jbi_iob_spi_vld(jbi_iob_spi_vld),
				.jbi_iob_spi_data(jbi_iob_spi_data[`SPI_IOB_WIDTH-1:0]),
				.iob_jbi_spi_stall(iob_jbi_spi_stall),
				.tap_iob_vld(tap_iob_vld),
				.tap_iob_data(tap_iob_data[`TAP_IOB_WIDTH-1:0]),
				.iob_tap_stall(iob_tap_stall));

   assign 	       iob_vld_bus = {iob_dbg_bus[43],
				      iob_dbg_bus[41],
				      iob_dbg_bus[39],
				      iob_dbg_bus[37],
				      iob_dbg_bus[35],
				      iob_dbg_bus[33]};
   
   assign 	       iob_stall_bus = {iob_dbg_bus[42],
					iob_dbg_bus[40],
					iob_dbg_bus[38],
					iob_dbg_bus[36],
					iob_dbg_bus[34],
					iob_dbg_bus[32]};
   
   dff_ns #(6) iob_vld_bus_d1_ff (.din(iob_vld_bus),
				  .clk(clk),
				  .q(iob_vld_bus_d1));
   
   dff_ns #(6) iob_stall_bus_d1_ff (.din(iob_stall_bus),
				    .clk(clk),
				    .q(iob_stall_bus_d1));
   
   assign 	       iob_vld_qual_bus = iob_vld_bus & ~iob_stall_bus_d1;

   assign 	       iob_soh_bus = ~iob_vld_bus_d1 & iob_vld_bus;
   
   


   iobdg_dbg_l2 iobdg_dbg_l2 (


			      .l2_dbg_vld(l2_dbg_vld),
			      .l2_dbg_tstamp({l2_dbg_tstamp[7:0]}),
			      .l2_dbg_data(l2_dbg_data[39:0]),
			      .iob_clk_l2_tr(iob_clk_l2_tr),
			      .l2_vis_buf_wr_lo_l(l2_vis_buf_wr_lo_l),
			      .l2_vis_buf_wr_hi_l(l2_vis_buf_wr_hi_l),
			      .l2_vis_buf_rd_lo_l(l2_vis_buf_rd_lo_l),
			      .l2_vis_buf_rd_hi_l(l2_vis_buf_rd_hi_l),
			      .l2_vis_buf_tail_ptr(l2_vis_buf_tail_ptr[`IOB_L2_VIS_BUF_INDEX-1:0]),
			      .l2_vis_buf_head_ptr(l2_vis_buf_head_ptr[`IOB_L2_VIS_BUF_INDEX-1:0]),
			      .l2_vis_buf_din_lo(l2_vis_buf_din_lo[64:0]),
			      .l2_vis_buf_din_hi(l2_vis_buf_din_hi[64:0]),

			      .cpu_rst_l(cpu_rst_l),
			      .rst_l	(rst_l),
			      .cpu_clk	(cpu_clk),
			      .clk	(clk),
			      .tx_sync	(tx_sync),
			      .rx_sync	(rx_sync),
			      .l2_dbgbus_01(l2_dbgbus_01[39:0]),
			      .l2_dbgbus_23(l2_dbgbus_23[39:0]),
			      .dbg_en_01(dbg_en_01),
			      .dbg_en_23(dbg_en_23),
			      .creg_dbg_l2_vis_ctrl(creg_dbg_l2_vis_ctrl[63:0]),
			      .creg_dbg_l2_vis_maska_s(creg_dbg_l2_vis_maska_s[63:0]),
			      .creg_dbg_l2_vis_cmpa_s(creg_dbg_l2_vis_cmpa_s[63:0]),
			      .creg_dbg_l2_vis_maskb_s(creg_dbg_l2_vis_maskb_s[63:0]),
			      .creg_dbg_l2_vis_cmpb_s(creg_dbg_l2_vis_cmpb_s[63:0]),
			      .creg_dbg_l2_vis_trig_delay_s(creg_dbg_l2_vis_trig_delay_s[63:0]),
			      .l2_vis_buf_dout_lo(l2_vis_buf_dout_lo[64:0]),
			      .l2_vis_buf_dout_hi(l2_vis_buf_dout_hi[64:0]));





   iobdg_dbg_porta iobdg_dbg_porta (


				    .iob_io_dbg_data(iob_io_dbg_data[39:0]),
				    .iob_io_dbg_en(iob_io_dbg_en),
				    .iob_io_dbg_ck_p(iob_io_dbg_ck_p[2:0]),
				    .iob_io_dbg_ck_n(iob_io_dbg_ck_n[2:0]),
				    .l2_vis_armin(l2_vis_armin),
				    .iob_clk_tr(iob_clk_tr),

				    .rst_l(rst_l),
				    .clk(clk),
				    .src0_data(l2_dbg_data[39:0]),
				    .src1_data({l2_dbg_data[39:30],l2_dbg_tstamp[7:0],l2_dbg_data[21:0]}),
				    .src2_data(iob_dbg_bus[39:0]),
				    .src3_data({1'b0,|iob_soh_bus[5:0],iob_vld_qual_bus[5:0],iob_dbg_bus[31:0]}),
				    .src4_data({iob_dbg_bus[39:35],iob_dbg_bus[41],iob_dbg_bus[33:0]}),
				    .src0_vld(l2_dbg_vld),
				    .src1_vld(l2_dbg_vld),
				    .src2_vld(1'b1),
				    .src3_vld({|iob_vld_qual_bus[5:0]}),
				    .src4_vld(iob_dbg_bus[43]),
				    .creg_dbg_enet_ctrl(creg_dbg_enet_ctrl[63:0]),
				    .creg_dbg_enet_idleval(creg_dbg_enet_idleval[63:0]),
				    .io_trigin(io_trigin));

   



   iobdg_dbg_portb iobdg_dbg_portb_hi (


				       .dbg_data(iob_jbi_dbg_hi_data[47:0]),
				       .dbg_vld(iob_jbi_dbg_hi_vld),

				       .rst_l(rst_l),
				       .clk(clk),
				       .src0_data({l2_dbg_vld,l2_dbg_tstamp[7:0],l2_dbg_data[39:0]}),
				       .src2_data({iob_vld_qual_bus[4],4'b0,iob_soh_bus[5:4],iob_vld_qual_bus[5:4],iob_dbg_bus[39:0]}),
				       .src3_data({iob_vld_qual_bus[4],4'b0,iob_soh_bus[5:4],iob_vld_qual_bus[5:4],iob_soh_bus[3:0],iob_vld_qual_bus[3:0],iob_dbg_bus[31:0]}),
				       .src4_data({iob_dbg_bus[40],4'b0,iob_dbg_bus[43:0]}),
				       .src0_vld(l2_dbg_vld),
				       .src2_vld({|iob_vld_qual_bus[5:4]}),
				       .src3_vld({|iob_vld_qual_bus[5:0]}),
				       .src4_vld(1'b1),
				       .i_am_hi(1'b1),
				       .creg_dbg_jbus_ctrl(creg_dbg_jbus_ctrl[63:0]),
				       .creg_dbg_jbus_mask0(creg_dbg_jbus_hi_mask0[63:0]),
				       .creg_dbg_jbus_cmp0(creg_dbg_jbus_hi_cmp0[63:0]),
				       .creg_dbg_jbus_cnt0(creg_dbg_jbus_hi_cnt0[63:0]),
				       .creg_dbg_jbus_mask1(creg_dbg_jbus_hi_mask1[63:0]),
				       .creg_dbg_jbus_cmp1(creg_dbg_jbus_hi_cmp1[63:0]),
				       .creg_dbg_jbus_cnt1(creg_dbg_jbus_hi_cnt1[63:0]));

   



   iobdg_dbg_portb iobdg_dbg_portb_lo (


				       .dbg_data(iob_jbi_dbg_lo_data[47:0]),
				       .dbg_vld(iob_jbi_dbg_lo_vld),

				       .rst_l(rst_l),
				       .clk(clk),
				       .src0_data({l2_dbg_vld,l2_dbg_tstamp[7:0],l2_dbg_data[39:0]}),
				       .src2_data({iob_vld_qual_bus[4],4'b0,iob_soh_bus[5:4],iob_vld_qual_bus[5:4],jbi_iob_pio_data_d1[7:0],iob_jbi_pio_data_d1[31:0]}),
				       .src3_data({iob_vld_qual_bus[4],4'b0,iob_soh_bus[5:4],iob_vld_qual_bus[5:4],iob_soh_bus[3:0],iob_vld_qual_bus[3:0],iob_dbg_bus[31:0]}),
				       .src4_data({iob_dbg_bus[40],4'b0,iob_dbg_bus[43:0]}),
				       .src0_vld(l2_dbg_vld),
				       .src2_vld({|iob_vld_qual_bus[5:4]}),
				       .src3_vld({|iob_vld_qual_bus[5:0]}),
				       .src4_vld(1'b1),
				       .i_am_hi(1'b0),
				       .creg_dbg_jbus_ctrl(creg_dbg_jbus_ctrl[63:0]),
				       .creg_dbg_jbus_mask0(creg_dbg_jbus_lo_mask0[63:0]),
				       .creg_dbg_jbus_cmp0(creg_dbg_jbus_lo_cmp0[63:0]),
				       .creg_dbg_jbus_cnt0(creg_dbg_jbus_lo_cnt0[63:0]),
				       .creg_dbg_jbus_mask1(creg_dbg_jbus_lo_mask1[63:0]),
				       .creg_dbg_jbus_cmp1(creg_dbg_jbus_lo_cmp1[63:0]),
				       .creg_dbg_jbus_cnt1(creg_dbg_jbus_lo_cnt1[63:0]));

   
endmodule