data/full_repos/permissive/456424671/Design_files/GRAY_CNT_tb.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/456424671/Design_files/GRAY_CNT_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n  always #0.5 i_clk = ~i_clk ;\n         ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/456424671/Design_files/GRAY_CNT_tb.v:27: Unsupported or unknown PLI call: $monitor\n        $monitor(" gray_out = %4b", gray_out);\n        ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/456424671/Design_files/GRAY_CNT_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n   #3 rst_n = 1\'b1 ;\n   ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module GRAY_CNT_tb ();

reg i_clk ;
 reg rst_n ;
 wire [3:0] gray_out ;

GRAY_CNT2  DUT ( i_clk , gray_out , rst_n   );






initial
  begin
   i_clk = 1'b0 ;
	rst_n = 1'b0 ;
	 end
	 
	 
	 always #0.5 i_clk = ~i_clk ;
	 initial begin
        $monitor(" gray_out = %4b", gray_out);
    end  
	 
	 initial 
	   begin
		 #3 rst_n = 1'b1 ;
		  end
	 
	
		  
		  endmodule
module GRAY_CNT_tb ();


reg i_clk ;
 reg rst_n ;
 wire [3:0] gray_out ;

GRAY_CNT2  DUT ( i_clk , gray_out , rst_n   );






initial
  begin
   i_clk = 1'b0 ;
	rst_n = 1'b0 ;
	 end
	 
	 
	 always #0.5 i_clk = ~i_clk ;
	 initial begin
        $monitor(" gray_out = %4b", gray_out);
    end  
	 
	 initial 
	   begin
		 #3 rst_n = 1'b1 ;
		  end
	 
	
		  
		  endmodule