data/full_repos/permissive/514437299/digital/rtl/clkg.v
1: b'%Warning-MULTITOP: data/full_repos/permissive/514437299/digital/rtl/clkg.v:151: Multiple top level modules\n                                                                              : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n                   ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n                                                                              : ... Top module \'mux8\'\nmodule mux8(input  wire [2:0] i_sel,\n       ^~~~\n                                                                              : ... Top module \'clkg\'\nmodule clkg #(parameter NINVERTER = 66) (\n       ^~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:65: Cannot find file containing module: \'CKLNQD1\'\n  CKLNQD1 U_CLK_GATE(\n  ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/514437299/digital/rtl,data/full_repos/permissive/514437299/CKLNQD1\n             data/full_repos/permissive/514437299/digital/rtl,data/full_repos/permissive/514437299/CKLNQD1.v\n             data/full_repos/permissive/514437299/digital/rtl,data/full_repos/permissive/514437299/CKLNQD1.sv\n             CKLNQD1\n             CKLNQD1.v\n             CKLNQD1.sv\n             obj_dir/CKLNQD1\n             obj_dir/CKLNQD1.v\n             obj_dir/CKLNQD1.sv\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:217: Cannot find file containing module: \'INVLONG_OSC37\'\n  INVLONG_OSC37 U_CLK_OSC(\n  ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:223: Cannot find file containing module: \'INVD2\'\n  INVD2 U_CLK_OSC_DRV(\n  ^~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:227: Cannot find file containing module: \'MUX2D0\'\n  MUX2D0 U_MUX2_JTAG_OSC(\n  ^~~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:233: Cannot find file containing module: \'MUX2D0\'\n  MUX2D0 U_MUX2_JTAG_FCK(\n  ^~~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:364: Cannot find file containing module: \'CKLNQD1\'\n  CKLNQD1 U_CLK_GATE_MEM(\n  ^~~~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:370: Cannot find file containing module: \'CKLNQD1\'\n  CKLNQD1 U_CLK_GATE_RNG(\n  ^~~~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:376: Cannot find file containing module: \'CKLNQD1\'\n  CKLNQD1 U_CLK_GATE_SMP(\n  ^~~~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:382: Cannot find file containing module: \'CKLNQD1\'\n  CKLNQD1 U_CLK_GATE_CMO(\n  ^~~~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:397: Cannot find file containing module: \'CKLNQD1\'\n  CKLNQD1 U_CLK_GATE_DLO(\n  ^~~~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:407: Cannot find file containing module: \'CKLHQD1\'\n  CKLHQD1 U_CLK_GATE_PCH(\n  ^~~~~~~\n%Error: data/full_repos/permissive/514437299/digital/rtl/clkg.v:413: Cannot find file containing module: \'CKLNQD1\'\n  CKLNQD1 U_CLK_GATE_PLN(\n  ^~~~~~~\n%Error: Exiting due to 12 error(s), 1 warning(s)\n'
module clkg #(parameter NINVERTER = 66) (
   input  wire                 clk_jtag,
   input  wire                 rst_n,
   input  wire                 i_clk_osc_en,
   input  wire                 i_clk_flk_bit,
   input  wire [1:0]           i_clk_sel_src,
   input  wire                 i_clk_gbl_en,
   input  wire                 i_clk_mem_en,
   input  wire                 i_clk_rng_en,
   input  wire                 i_clk_smp_en,
   input  wire                 i_clk_cmo_en,
   input  wire                 i_clk_dlo_en,
   input  wire                 i_clk_pln_en,
   input  wire [2:0]           i_clk_sys_div,
   input  wire [2:0]           i_clk_smp_div,
   input  wire                 i_clk_pch_rfs,
   input  wire [1:0]           i_clk_rnd_sel,
   input  wire                 i_clk_rnd_ptb_en,
   input  wire [7:0]           i_clk_rnd_ptb_gamma,
   input  wire                 i_rng_psd_en,
   input  wire                 i_rng_initdone,
   input  wire                 i_rng_ptb,
   output wire                 o_clk_mem,
   output wire                 o_clk_rng,
   output wire                 o_clk_smp,
   output wire                 o_clk_cmo,
   output wire                 o_clk_dlo,
   output wire                 o_clk_pch,
   output wire                 o_clk_pln,
   output reg                  o_clk_initdone);


  localparam IDLE = 2'd0;
  localparam INIT = 2'd1;
  localparam CHCK = 2'd2;
  localparam RUNN = 2'd3;

  reg  [7:0] gamma_cnter;
  wire [7:0] rnd_state;

  reg [1:0] state;

  wire clk_jtag_fck;

  reg  clk_sys_pre, clk_sys_pre_noskip;
  wire clk_smp;

  reg  rnd_ptb_valid, skip_clk;

  wire clk_rnd_en;

  wire clk_osc, clk_osc_pre, clk_mux_glitch;
  wire p25, p50, p75;
  wire clk_sys_tap;
  wire [7:0] clk_sys_all;

  wire initdone;

  reg clk_dlo_en_late;







  INVLONG_OSC37 U_CLK_OSC(
    .EN  ( i_clk_osc_en ),
    .OUT ( clk_osc_pre  ) );


  INVD2 U_CLK_OSC_DRV(
    .I  ( clk_osc_pre ),
    .ZN ( clk_osc     ) );

  MUX2D0 U_MUX2_JTAG_OSC(
    .I0( clk_jtag_fck  ),
    .I1( clk_osc          ),
    .S ( i_clk_sel_src[0] ),
    .Z ( clk_mux_glitch   ) );

  MUX2D0 U_MUX2_JTAG_FCK(
    .I0( clk_jtag         ),
    .I1( i_clk_flk_bit    ),
    .S ( i_clk_sel_src[1] ),
    .Z ( clk_jtag_fck  ) );


  clkdiv U_CLKDIV_SYS(
    .clk         ( clk_mux_glitch ) ,
    .rst_n       ( rst_n          ) ,
    .i_en        ( i_clk_gbl_en   ) ,
    .i_div       ( i_clk_sys_div  ) ,
    .o_clk_div   ( clk_sys_tap    ) ,
    .o_clk_all   ( clk_sys_all    ) );





  always @(posedge clk_sys_tap or negedge rst_n)
    if (!rst_n) begin
      gamma_cnter    <= 8'b0;
      rnd_ptb_valid  <= 1'b0;
      o_clk_initdone <= 1'b0;
      state          <= 2'b0;
    end else
      case (state)
        IDLE: begin

          if (i_rng_initdone) begin
            if (i_rng_psd_en) begin
              state         <= INIT;
              rnd_ptb_valid <= 1'b1;
            end else
              state         <= RUNN;
          end
        end
        INIT: begin
          gamma_cnter <= gamma_cnter + 1'b1;
          if (gamma_cnter > 8'hf) begin
            gamma_cnter   <= 8'b0;
            rnd_ptb_valid <= 1'b0;
            state         <= CHCK;
          end
        end
        CHCK: begin

          state <= RUNN;
          if ((&rnd_state))
            state <= IDLE;
        end
        RUNN: begin
          o_clk_initdone <= 1'b1;
          if (i_clk_rnd_ptb_en) begin
            gamma_cnter   <= gamma_cnter + 1'b1;
            rnd_ptb_valid <= 1'b0;
            if (gamma_cnter >= i_clk_rnd_ptb_gamma) begin
              gamma_cnter   <= 8'b0;
              rnd_ptb_valid <= 1'b1;
            end
          end
        end
      endcase

  assign clk_rnd_en = (|i_clk_rnd_sel);

  always @*
    case (i_clk_rnd_sel)
        2'b00:   skip_clk = 1'b0;
        2'b01:   skip_clk = p25 & initdone;
        2'b10:   skip_clk = p50 & initdone;
        2'b11:   skip_clk = p75 & initdone;
        default: skip_clk = 1'b0;
    endcase





  wire not_insync = (~clk_sys_pre) & clk_sys_pre_noskip & i_clk_pch_rfs & clk_rnd_en;

  always @(posedge clk_sys_tap or negedge rst_n)
    if (!rst_n)
      clk_sys_pre <= 1'b0;
    else if ((~skip_clk) & (~not_insync))
      clk_sys_pre <= ~clk_sys_pre;

  always @(posedge clk_sys_tap or negedge rst_n)
    if (!rst_n) clk_sys_pre_noskip <= 1'b0;
    else        clk_sys_pre_noskip <= ~clk_sys_pre_noskip;

  wire clk_sys_pch     = (i_clk_pch_rfs) ? ~clk_sys_pre_noskip : ~clk_sys_pre;

  clkdiv U_CLKDIV_SMP(
    .clk        ( clk_sys_tap   ) ,
    .rst_n      ( rst_n         ) ,
    .i_en       ( i_clk_smp_en  ) ,
    .i_div      ( i_clk_smp_div ) ,
    .o_clk_div  ( clk_smp       ) ,
    .o_clk_all  () );

  lfsr8 U_LFSR8(
    .clk             ( clk_sys_tap                       ) ,
    .rst_n           ( rst_n                             ) ,
    .i_en            ( clk_rnd_en & o_clk_initdone       ) ,
    .i_ptb           ( i_rng_ptb                         ) ,
    .i_ptb_valid     ( rnd_ptb_valid                     ) ,
    .i_si            ( i_rng_ptb                         ) ,
    .i_sr_valid      ( rnd_ptb_valid & (~o_clk_initdone) ) ,
    .o_state         ( rnd_state                         ) ,
    .o_p25           ( p25                               ) ,
    .o_p50           ( p50                               ) ,
    .o_p75           ( p75                               ) );

  assign initdone = i_rng_initdone & o_clk_initdone;

  CKLNQD1 U_CLK_GATE_MEM(
    .TE ( 1'b0         ) ,
    .E  ( i_clk_mem_en ) ,
    .CP ( clk_sys_pre  ) ,
    .Q  ( o_clk_mem    ) );

  CKLNQD1 U_CLK_GATE_RNG(
    .TE ( 1'b0               ) ,
    .E  ( i_clk_rng_en       ) ,
    .CP ( clk_sys_pre_noskip ) ,
    .Q  ( o_clk_rng          ) );

  CKLNQD1 U_CLK_GATE_SMP(
    .TE ( 1'b0         ) ,
    .E  ( i_clk_smp_en ) ,
    .CP ( clk_smp      ) ,
    .Q  ( o_clk_smp    ) );

  CKLNQD1 U_CLK_GATE_CMO(
    .TE ( 1'b0                    ) ,
    .E  ( i_clk_cmo_en & initdone ) ,
    .CP ( clk_sys_pre             ) ,
    .Q  ( o_clk_cmo               ) );



  always @(posedge clk_sys_pre or negedge rst_n)
    if (!rst_n) clk_dlo_en_late <= 1'b0;
    else        clk_dlo_en_late <= i_clk_gbl_en & i_clk_dlo_en & initdone;

  CKLNQD1 U_CLK_GATE_DLO(
    .TE  ( 1'b0            ) ,
    .E   ( clk_dlo_en_late ) ,
    .CP  ( clk_sys_pre     ) ,
    .Q   ( o_clk_dlo       ) );


  CKLHQD1 U_CLK_GATE_PCH(
    .TE  ( 1'b0                    ) ,
    .E   ( i_clk_dlo_en & initdone ) ,
    .CPN ( clk_sys_pch             ) ,
    .Q   ( o_clk_pch               ) );

  CKLNQD1 U_CLK_GATE_PLN(
    .TE ( 1'b0                    ) ,
    .E  ( i_clk_pln_en & initdone ) ,
    .CP ( clk_sys_pre             ) ,
    .Q  ( o_clk_pln               ) );

endmodule
module clkg #(parameter NINVERTER = 66) (
   input  wire                 clk_jtag,
   input  wire                 rst_n,
   input  wire                 i_clk_osc_en,
   input  wire                 i_clk_flk_bit,
   input  wire [1:0]           i_clk_sel_src,
   input  wire                 i_clk_gbl_en,
   input  wire                 i_clk_mem_en,
   input  wire                 i_clk_rng_en,
   input  wire                 i_clk_smp_en,
   input  wire                 i_clk_cmo_en,
   input  wire                 i_clk_dlo_en,
   input  wire                 i_clk_pln_en,
   input  wire [2:0]           i_clk_sys_div,
   input  wire [2:0]           i_clk_smp_div,
   input  wire                 i_clk_pch_rfs,
   input  wire [1:0]           i_clk_rnd_sel,
   input  wire                 i_clk_rnd_ptb_en,
   input  wire [7:0]           i_clk_rnd_ptb_gamma,
   input  wire                 i_rng_psd_en,
   input  wire                 i_rng_initdone,
   input  wire                 i_rng_ptb,
   output wire                 o_clk_mem,
   output wire                 o_clk_rng,
   output wire                 o_clk_smp,
   output wire                 o_clk_cmo,
   output wire                 o_clk_dlo,
   output wire                 o_clk_pch,
   output wire                 o_clk_pln,
   output reg                  o_clk_initdone);



  localparam IDLE = 2'd0;
  localparam INIT = 2'd1;
  localparam CHCK = 2'd2;
  localparam RUNN = 2'd3;

  reg  [7:0] gamma_cnter;
  wire [7:0] rnd_state;

  reg [1:0] state;

  wire clk_jtag_fck;

  reg  clk_sys_pre, clk_sys_pre_noskip;
  wire clk_smp;

  reg  rnd_ptb_valid, skip_clk;

  wire clk_rnd_en;

  wire clk_osc, clk_osc_pre, clk_mux_glitch;
  wire p25, p50, p75;
  wire clk_sys_tap;
  wire [7:0] clk_sys_all;

  wire initdone;

  reg clk_dlo_en_late;







  INVLONG_OSC37 U_CLK_OSC(
    .EN  ( i_clk_osc_en ),
    .OUT ( clk_osc_pre  ) );


  INVD2 U_CLK_OSC_DRV(
    .I  ( clk_osc_pre ),
    .ZN ( clk_osc     ) );

  MUX2D0 U_MUX2_JTAG_OSC(
    .I0( clk_jtag_fck  ),
    .I1( clk_osc          ),
    .S ( i_clk_sel_src[0] ),
    .Z ( clk_mux_glitch   ) );

  MUX2D0 U_MUX2_JTAG_FCK(
    .I0( clk_jtag         ),
    .I1( i_clk_flk_bit    ),
    .S ( i_clk_sel_src[1] ),
    .Z ( clk_jtag_fck  ) );


  clkdiv U_CLKDIV_SYS(
    .clk         ( clk_mux_glitch ) ,
    .rst_n       ( rst_n          ) ,
    .i_en        ( i_clk_gbl_en   ) ,
    .i_div       ( i_clk_sys_div  ) ,
    .o_clk_div   ( clk_sys_tap    ) ,
    .o_clk_all   ( clk_sys_all    ) );





  always @(posedge clk_sys_tap or negedge rst_n)
    if (!rst_n) begin
      gamma_cnter    <= 8'b0;
      rnd_ptb_valid  <= 1'b0;
      o_clk_initdone <= 1'b0;
      state          <= 2'b0;
    end else
      case (state)
        IDLE: begin

          if (i_rng_initdone) begin
            if (i_rng_psd_en) begin
              state         <= INIT;
              rnd_ptb_valid <= 1'b1;
            end else
              state         <= RUNN;
          end
        end
        INIT: begin
          gamma_cnter <= gamma_cnter + 1'b1;
          if (gamma_cnter > 8'hf) begin
            gamma_cnter   <= 8'b0;
            rnd_ptb_valid <= 1'b0;
            state         <= CHCK;
          end
        end
        CHCK: begin

          state <= RUNN;
          if ((&rnd_state))
            state <= IDLE;
        end
        RUNN: begin
          o_clk_initdone <= 1'b1;
          if (i_clk_rnd_ptb_en) begin
            gamma_cnter   <= gamma_cnter + 1'b1;
            rnd_ptb_valid <= 1'b0;
            if (gamma_cnter >= i_clk_rnd_ptb_gamma) begin
              gamma_cnter   <= 8'b0;
              rnd_ptb_valid <= 1'b1;
            end
          end
        end
      endcase

  assign clk_rnd_en = (|i_clk_rnd_sel);

  always @*
    case (i_clk_rnd_sel)
        2'b00:   skip_clk = 1'b0;
        2'b01:   skip_clk = p25 & initdone;
        2'b10:   skip_clk = p50 & initdone;
        2'b11:   skip_clk = p75 & initdone;
        default: skip_clk = 1'b0;
    endcase





  wire not_insync = (~clk_sys_pre) & clk_sys_pre_noskip & i_clk_pch_rfs & clk_rnd_en;

  always @(posedge clk_sys_tap or negedge rst_n)
    if (!rst_n)
      clk_sys_pre <= 1'b0;
    else if ((~skip_clk) & (~not_insync))
      clk_sys_pre <= ~clk_sys_pre;

  always @(posedge clk_sys_tap or negedge rst_n)
    if (!rst_n) clk_sys_pre_noskip <= 1'b0;
    else        clk_sys_pre_noskip <= ~clk_sys_pre_noskip;

  wire clk_sys_pch     = (i_clk_pch_rfs) ? ~clk_sys_pre_noskip : ~clk_sys_pre;

  clkdiv U_CLKDIV_SMP(
    .clk        ( clk_sys_tap   ) ,
    .rst_n      ( rst_n         ) ,
    .i_en       ( i_clk_smp_en  ) ,
    .i_div      ( i_clk_smp_div ) ,
    .o_clk_div  ( clk_smp       ) ,
    .o_clk_all  () );

  lfsr8 U_LFSR8(
    .clk             ( clk_sys_tap                       ) ,
    .rst_n           ( rst_n                             ) ,
    .i_en            ( clk_rnd_en & o_clk_initdone       ) ,
    .i_ptb           ( i_rng_ptb                         ) ,
    .i_ptb_valid     ( rnd_ptb_valid                     ) ,
    .i_si            ( i_rng_ptb                         ) ,
    .i_sr_valid      ( rnd_ptb_valid & (~o_clk_initdone) ) ,
    .o_state         ( rnd_state                         ) ,
    .o_p25           ( p25                               ) ,
    .o_p50           ( p50                               ) ,
    .o_p75           ( p75                               ) );

  assign initdone = i_rng_initdone & o_clk_initdone;

  CKLNQD1 U_CLK_GATE_MEM(
    .TE ( 1'b0         ) ,
    .E  ( i_clk_mem_en ) ,
    .CP ( clk_sys_pre  ) ,
    .Q  ( o_clk_mem    ) );

  CKLNQD1 U_CLK_GATE_RNG(
    .TE ( 1'b0               ) ,
    .E  ( i_clk_rng_en       ) ,
    .CP ( clk_sys_pre_noskip ) ,
    .Q  ( o_clk_rng          ) );

  CKLNQD1 U_CLK_GATE_SMP(
    .TE ( 1'b0         ) ,
    .E  ( i_clk_smp_en ) ,
    .CP ( clk_smp      ) ,
    .Q  ( o_clk_smp    ) );

  CKLNQD1 U_CLK_GATE_CMO(
    .TE ( 1'b0                    ) ,
    .E  ( i_clk_cmo_en & initdone ) ,
    .CP ( clk_sys_pre             ) ,
    .Q  ( o_clk_cmo               ) );



  always @(posedge clk_sys_pre or negedge rst_n)
    if (!rst_n) clk_dlo_en_late <= 1'b0;
    else        clk_dlo_en_late <= i_clk_gbl_en & i_clk_dlo_en & initdone;

  CKLNQD1 U_CLK_GATE_DLO(
    .TE  ( 1'b0            ) ,
    .E   ( clk_dlo_en_late ) ,
    .CP  ( clk_sys_pre     ) ,
    .Q   ( o_clk_dlo       ) );


  CKLHQD1 U_CLK_GATE_PCH(
    .TE  ( 1'b0                    ) ,
    .E   ( i_clk_dlo_en & initdone ) ,
    .CPN ( clk_sys_pch             ) ,
    .Q   ( o_clk_pch               ) );

  CKLNQD1 U_CLK_GATE_PLN(
    .TE ( 1'b0                    ) ,
    .E  ( i_clk_pln_en & initdone ) ,
    .CP ( clk_sys_pre             ) ,
    .Q  ( o_clk_pln               ) );

endmodule