data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v
1: b'%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:31: Unsupported: Static in this context\nstatic integer FILE;\n^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:38: Unsupported: Ignoring delay on this delayed statement.\n    #10000;\n    ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:45: Define or directive not defined: \'`hcr\'\n    write_hadreg_corea(`hcr,32\'h8000);                  \n                       ^~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:47: Define or directive not defined: \'`hcr\'\n    write_hadreg_corea(`hcr,32\'h0);                     \n                       ^~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:48: Define or directive not defined: \'`event_outen\'\n    write_hadreg_corea(`event_outen,32\'h0); \n                       ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:56: Define or directive not defined: \'`csr\'\n    write_hadreg_corea(`csr,16\'h100);                   \n                       ^~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:59: Define or directive not defined: \'`wbbr\'\n    write_hadreg_corea(`wbbr,rand_data);\n                       ^~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:60: Define or directive not defined: \'`ir_go_nex\'\n    write_hadreg_corea(`ir_go_nex,`MV_X6_X6);          \n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:60: Define or directive not defined: \'`MV_X6_X6\'\n    write_hadreg_corea(`ir_go_nex,`MV_X6_X6);          \n                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:61: Define or directive not defined: \'`csr\'\n    write_hadreg_corea(`csr,16\'h0);                    \n                       ^~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:64: Define or directive not defined: \'`csr\'\n    write_hadreg_corea(`csr,16\'h0);\n                       ^~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:65: Define or directive not defined: \'`ir_go_nex\'\n    write_hadreg_corea(`ir_go_nex,`LD_X7_0_X6 );\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:65: Define or directive not defined: \'`LD_X7_0_X6\'\n    write_hadreg_corea(`ir_go_nex,`LD_X7_0_X6 );\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:68: Define or directive not defined: \'`hsr\'\n       read_hadreg_corea(`hsr,hsr_data_out);\n                         ^~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:69: Define or directive not defined: \'`wbbr\'\n    read_hadreg_corea(`wbbr,wbbr_data_out);\n                      ^~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:76: Define or directive not defined: \'`csr\'\n    write_hadreg_corea(`csr,16\'h100);\n                       ^~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:78: Define or directive not defined: \'`wbbr\'\n    write_hadreg_corea(`wbbr,64\'h0);\n                       ^~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:79: Define or directive not defined: \'`ir_go_nex\'\n    write_hadreg_corea(`ir_go_nex,`MV_X6_X6);\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:79: Define or directive not defined: \'`MV_X6_X6\'\n    write_hadreg_corea(`ir_go_nex,`MV_X6_X6);\n                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:81: Define or directive not defined: \'`wbbr\'\n    write_hadreg_corea(`wbbr,64\'h1111111111111111);\n                       ^~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:83: Define or directive not defined: \'`ir_go_nex\'\n    write_hadreg_corea(`ir_go_nex,`MV_X7_X7);\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:83: Define or directive not defined: \'`MV_X7_X7\'\n    write_hadreg_corea(`ir_go_nex,`MV_X7_X7);\n                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:84: Define or directive not defined: \'`ir_go_nex\'\n    write_hadreg_corea(`ir_go_nex,`SD_X7_0_X6);\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:84: Define or directive not defined: \'`SD_X7_0_X6\'\n    write_hadreg_corea(`ir_go_nex,`SD_X7_0_X6);\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:86: Define or directive not defined: \'`wbbr\'\n    write_hadreg_corea(`wbbr,64\'h2222222222222222);\n                       ^~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:88: Define or directive not defined: \'`ir_go_nex\'\n    write_hadreg_corea(`ir_go_nex,`MV_X7_X7);\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:88: Define or directive not defined: \'`MV_X7_X7\'\n    write_hadreg_corea(`ir_go_nex,`MV_X7_X7);\n                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:89: Define or directive not defined: \'`ir_go_nex\'\n    write_hadreg_corea(`ir_go_nex,`SD_X7_8_X6);\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:89: Define or directive not defined: \'`SD_X7_8_X6\'\n    write_hadreg_corea(`ir_go_nex,`SD_X7_8_X6);\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:91: Define or directive not defined: \'`wbbr\'\n    write_hadreg_corea(`wbbr,64\'h3333333333333333);\n                       ^~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:93: Define or directive not defined: \'`ir_go_nex\'\n    write_hadreg_corea(`ir_go_nex,`MV_X7_X7);\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:93: Define or directive not defined: \'`MV_X7_X7\'\n    write_hadreg_corea(`ir_go_nex,`MV_X7_X7);\n                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:94: Define or directive not defined: \'`ir_go_nex\'\n    write_hadreg_corea(`ir_go_nex,`SD_X7_16_X6);\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:94: Define or directive not defined: \'`SD_X7_16_X6\'\n    write_hadreg_corea(`ir_go_nex,`SD_X7_16_X6);\n                                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:96: Define or directive not defined: \'`wbbr\'\n    write_hadreg_corea(`wbbr,64\'h4444444444444444);\n                       ^~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:98: Define or directive not defined: \'`ir_go_nex\'\n    write_hadreg_corea(`ir_go_nex,`MV_X7_X7);\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:98: Define or directive not defined: \'`MV_X7_X7\'\n    write_hadreg_corea(`ir_go_nex,`MV_X7_X7);\n                                  ^~~~~~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:99: Define or directive not defined: \'`ir_go_nex\'\n    write_hadreg_corea(`ir_go_nex,`SD_X7_24_X6);\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:99: Define or directive not defined: \'`SD_X7_24_X6\'\n    write_hadreg_corea(`ir_go_nex,`SD_X7_24_X6);\n                                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:102: Define or directive not defined: \'`csr\'\n    write_hadreg_corea(`csr,16\'h0);\n                       ^~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:103: Define or directive not defined: \'`ir_go_nex\'\n    write_hadreg_corea(`ir_go_nex,`LD_X7_0_X6 );\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:103: Define or directive not defined: \'`LD_X7_0_X6\'\n    write_hadreg_corea(`ir_go_nex,`LD_X7_0_X6 );\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:106: Define or directive not defined: \'`hsr\'\n       read_hadreg_corea(`hsr,hsr_data_out);\n                         ^~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:107: Define or directive not defined: \'`wbbr\'\n   read_hadreg_corea(`wbbr,wbbr_data_out);\n                     ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:115: Unsupported: Ignoring delay on this delayed statement.\n    #100; \n    ^\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:118: Define or directive not defined: \'`ir_go_nex\'\n    write_hadreg_corea(`ir_go_nex,`LD_X7_8_X6 );\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:118: Define or directive not defined: \'`LD_X7_8_X6\'\n    write_hadreg_corea(`ir_go_nex,`LD_X7_8_X6 );\n                                  ^~~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:122: Define or directive not defined: \'`hsr\'\n      read_hadreg_corea(`hsr,hsr_data_out);\n                        ^~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:123: Define or directive not defined: \'`wbbr\'\n    read_hadreg_corea(`wbbr,wbbr_data_out);\n                      ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:131: Unsupported: Ignoring delay on this delayed statement.\n    #100; \n    ^\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:134: Define or directive not defined: \'`ir_go_nex\'\n    write_hadreg_corea(`ir_go_nex,`LD_X7_16_X6 );\n                       ^~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:134: Define or directive not defined: \'`LD_X7_16_X6\'\n    write_hadreg_corea(`ir_go_nex,`LD_X7_16_X6 );\n                                  ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/418752214/smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.v:138: Define or directive not defined: \'`hsr\'\n      read_hadreg_corea(`hsr,hsr_data_out);\n                        ^~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n        ... See the manual and https://verilator.org for more assistance.\n'
module debug_read_write_memory(
);

reg[15:0]  hsr_data_out;
reg[63:0]  wbbr_data_out;
reg[63:0]  rand_data;

static integer FILE;

initial
  begin
    hsr_data_out   = 0;
    wbbr_data_out  = 0;
    rand_data      = 0;
    #10000;

    jtag_rst(32'h10);
open_event;



    write_hadreg_corea(`hcr,32'h8000);
    wait_debug_mode_corea;
    write_hadreg_corea(`hcr,32'h0);
    write_hadreg_corea(`event_outen,32'h0); 







    write_hadreg_corea(`csr,16'h100);
    rand_data = 64'h0;
    $display("Write X6 = 0x%h",rand_data);
    write_hadreg_corea(`wbbr,rand_data);
    write_hadreg_corea(`ir_go_nex,`MV_X6_X6);
    write_hadreg_corea(`csr,16'h0);


    write_hadreg_corea(`csr,16'h0);
    write_hadreg_corea(`ir_go_nex,`LD_X7_0_X6 );
    hsr_data_out[12] = 0;
    while(!hsr_data_out[12])
       read_hadreg_corea(`hsr,hsr_data_out);
    read_hadreg_corea(`wbbr,wbbr_data_out);
    $display("read address 0 = 0x%h",wbbr_data_out);





    write_hadreg_corea(`csr,16'h100);

    write_hadreg_corea(`wbbr,64'h0);
    write_hadreg_corea(`ir_go_nex,`MV_X6_X6);

    write_hadreg_corea(`wbbr,64'h1111111111111111);
    $display("write address  0 = 0x%h",64'h1111111111111111);
    write_hadreg_corea(`ir_go_nex,`MV_X7_X7);
    write_hadreg_corea(`ir_go_nex,`SD_X7_0_X6);

    write_hadreg_corea(`wbbr,64'h2222222222222222);
    $display("write address  8 = 0x%h",64'h2222222222222222);
    write_hadreg_corea(`ir_go_nex,`MV_X7_X7);
    write_hadreg_corea(`ir_go_nex,`SD_X7_8_X6);

    write_hadreg_corea(`wbbr,64'h3333333333333333);
    $display("write address 16 = 0x%h",64'h3333333333333333);
    write_hadreg_corea(`ir_go_nex,`MV_X7_X7);
    write_hadreg_corea(`ir_go_nex,`SD_X7_16_X6);

    write_hadreg_corea(`wbbr,64'h4444444444444444);
    $display("write address 24 = 0x%h",64'h4444444444444444);
    write_hadreg_corea(`ir_go_nex,`MV_X7_X7);
    write_hadreg_corea(`ir_go_nex,`SD_X7_24_X6);


    write_hadreg_corea(`csr,16'h0);
    write_hadreg_corea(`ir_go_nex,`LD_X7_0_X6 );
    hsr_data_out[12] = 0;
    while(!hsr_data_out[12])
       read_hadreg_corea(`hsr,hsr_data_out);
   read_hadreg_corea(`wbbr,wbbr_data_out);
    if(wbbr_data_out == 64'h1111111111111111)
      $display("Success!Addr at X6+0 mem is 0x%h!",wbbr_data_out);
    else begin
      $display("Fail!Addr at X6+0 mem is 0x%h!",wbbr_data_out);



      `TEST_FAIL_AND_FINISH
    end

    write_hadreg_corea(`ir_go_nex,`LD_X7_8_X6 );
    wbbr_data_out = 64'h0;
    hsr_data_out[12] = 0;
    while(!hsr_data_out[12])
      read_hadreg_corea(`hsr,hsr_data_out);
    read_hadreg_corea(`wbbr,wbbr_data_out);
    if(wbbr_data_out == 64'h2222222222222222)
      $display("Success!Addr at X6+8 mem is 0x%h!",wbbr_data_out);
    else begin
      $display("Fail!Addr at X6+8 mem is 0x%h!",wbbr_data_out);



      `TEST_FAIL_AND_FINISH
    end

    write_hadreg_corea(`ir_go_nex,`LD_X7_16_X6 );
    wbbr_data_out = 64'h0;
    hsr_data_out[12] = 0;
    while(!hsr_data_out[12])
      read_hadreg_corea(`hsr,hsr_data_out);
    read_hadreg_corea(`wbbr,wbbr_data_out);
    if(wbbr_data_out == 64'h3333333333333333)
      $display("Success!Addr at X6+16 mem is 0x%h!",wbbr_data_out);
    else begin
      $display("Fail!Addr at X6+16 mem is 0x%h!",wbbr_data_out);


      `TEST_FAIL_AND_FINISH
    end

    write_hadreg_corea(`ir_go_nex,`LD_X7_24_X6 );
    wbbr_data_out = 64'h0;
    hsr_data_out[12] = 0;
    while(!hsr_data_out[12])
      read_hadreg_corea(`hsr,hsr_data_out);
    read_hadreg_corea(`wbbr,wbbr_data_out);
    if(wbbr_data_out == 64'h4444444444444444)
      $display("Success!Addr at X6+24 mem is 0x%h!",wbbr_data_out);
    else begin
      $display("Fail!Addr at X6+24 mem is 0x%h!",wbbr_data_out);



      `TEST_FAIL_AND_FINISH
    end
      $display("#####################################################");
      $display("XXXXX Congratulations!!!!!!  Simulation PASS!!! XXXXX");
      $display("#####################################################");

      FILE = $fopen("run_case.report","w");
      $fdisplay(FILE,"TEST PASS");   
      #100;

      $finish;
end



endmodule
module debug_read_write_memory(
);


reg[15:0]  hsr_data_out;
reg[63:0]  wbbr_data_out;
reg[63:0]  rand_data;

static integer FILE;

initial
  begin
    hsr_data_out   = 0;
    wbbr_data_out  = 0;
    rand_data      = 0;
    #10000;

    jtag_rst(32'h10);
open_event;



    write_hadreg_corea(`hcr,32'h8000);
    wait_debug_mode_corea;
    write_hadreg_corea(`hcr,32'h0);
    write_hadreg_corea(`event_outen,32'h0); 







    write_hadreg_corea(`csr,16'h100);
    rand_data = 64'h0;
    $display("Write X6 = 0x%h",rand_data);
    write_hadreg_corea(`wbbr,rand_data);
    write_hadreg_corea(`ir_go_nex,`MV_X6_X6);
    write_hadreg_corea(`csr,16'h0);


    write_hadreg_corea(`csr,16'h0);
    write_hadreg_corea(`ir_go_nex,`LD_X7_0_X6 );
    hsr_data_out[12] = 0;
    while(!hsr_data_out[12])
       read_hadreg_corea(`hsr,hsr_data_out);
    read_hadreg_corea(`wbbr,wbbr_data_out);
    $display("read address 0 = 0x%h",wbbr_data_out);





    write_hadreg_corea(`csr,16'h100);

    write_hadreg_corea(`wbbr,64'h0);
    write_hadreg_corea(`ir_go_nex,`MV_X6_X6);

    write_hadreg_corea(`wbbr,64'h1111111111111111);
    $display("write address  0 = 0x%h",64'h1111111111111111);
    write_hadreg_corea(`ir_go_nex,`MV_X7_X7);
    write_hadreg_corea(`ir_go_nex,`SD_X7_0_X6);

    write_hadreg_corea(`wbbr,64'h2222222222222222);
    $display("write address  8 = 0x%h",64'h2222222222222222);
    write_hadreg_corea(`ir_go_nex,`MV_X7_X7);
    write_hadreg_corea(`ir_go_nex,`SD_X7_8_X6);

    write_hadreg_corea(`wbbr,64'h3333333333333333);
    $display("write address 16 = 0x%h",64'h3333333333333333);
    write_hadreg_corea(`ir_go_nex,`MV_X7_X7);
    write_hadreg_corea(`ir_go_nex,`SD_X7_16_X6);

    write_hadreg_corea(`wbbr,64'h4444444444444444);
    $display("write address 24 = 0x%h",64'h4444444444444444);
    write_hadreg_corea(`ir_go_nex,`MV_X7_X7);
    write_hadreg_corea(`ir_go_nex,`SD_X7_24_X6);


    write_hadreg_corea(`csr,16'h0);
    write_hadreg_corea(`ir_go_nex,`LD_X7_0_X6 );
    hsr_data_out[12] = 0;
    while(!hsr_data_out[12])
       read_hadreg_corea(`hsr,hsr_data_out);
   read_hadreg_corea(`wbbr,wbbr_data_out);
    if(wbbr_data_out == 64'h1111111111111111)
      $display("Success!Addr at X6+0 mem is 0x%h!",wbbr_data_out);
    else begin
      $display("Fail!Addr at X6+0 mem is 0x%h!",wbbr_data_out);



      `TEST_FAIL_AND_FINISH
    end

    write_hadreg_corea(`ir_go_nex,`LD_X7_8_X6 );
    wbbr_data_out = 64'h0;
    hsr_data_out[12] = 0;
    while(!hsr_data_out[12])
      read_hadreg_corea(`hsr,hsr_data_out);
    read_hadreg_corea(`wbbr,wbbr_data_out);
    if(wbbr_data_out == 64'h2222222222222222)
      $display("Success!Addr at X6+8 mem is 0x%h!",wbbr_data_out);
    else begin
      $display("Fail!Addr at X6+8 mem is 0x%h!",wbbr_data_out);



      `TEST_FAIL_AND_FINISH
    end

    write_hadreg_corea(`ir_go_nex,`LD_X7_16_X6 );
    wbbr_data_out = 64'h0;
    hsr_data_out[12] = 0;
    while(!hsr_data_out[12])
      read_hadreg_corea(`hsr,hsr_data_out);
    read_hadreg_corea(`wbbr,wbbr_data_out);
    if(wbbr_data_out == 64'h3333333333333333)
      $display("Success!Addr at X6+16 mem is 0x%h!",wbbr_data_out);
    else begin
      $display("Fail!Addr at X6+16 mem is 0x%h!",wbbr_data_out);


      `TEST_FAIL_AND_FINISH
    end

    write_hadreg_corea(`ir_go_nex,`LD_X7_24_X6 );
    wbbr_data_out = 64'h0;
    hsr_data_out[12] = 0;
    while(!hsr_data_out[12])
      read_hadreg_corea(`hsr,hsr_data_out);
    read_hadreg_corea(`wbbr,wbbr_data_out);
    if(wbbr_data_out == 64'h4444444444444444)
      $display("Success!Addr at X6+24 mem is 0x%h!",wbbr_data_out);
    else begin
      $display("Fail!Addr at X6+24 mem is 0x%h!",wbbr_data_out);



      `TEST_FAIL_AND_FINISH
    end
      $display("#####################################################");
      $display("XXXXX Congratulations!!!!!!  Simulation PASS!!! XXXXX");
      $display("#####################################################");

      FILE = $fopen("run_case.report","w");
      $fdisplay(FILE,"TEST PASS");   
      #100;

      $finish;
end



endmodule