data/full_repos/permissive/412284801/or/or_rtl.v
data/verilator_xmls/98c79d85-f947-4d4e-9560-b4105fa0fff5.xml
module or_rtl(a,b,o);

input a,b;
output reg o;

always @(a,b) 
begin
o = a|b;    
end
endmodule
module or_rtl(a,b,o);


input a,b;
output reg o;

always @(a,b) 
begin
o = a|b;    
end
endmodule