data/full_repos/permissive/499054870/verilog/rtl/user_proj_example.v
1: b"%Error: data/full_repos/permissive/499054870/verilog/rtl/user_proj_example.v:66: Define or directive not defined: '`MPRJ_IO_PADS'\n    input  [`MPRJ_IO_PADS-1:0] io_in,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499054870/verilog/rtl/user_proj_example.v:67: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_out,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499054870/verilog/rtl/user_proj_example.v:68: Define or directive not defined: '`MPRJ_IO_PADS'\n    output [`MPRJ_IO_PADS-1:0] io_oeb,\n            ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/499054870/verilog/rtl/user_proj_example.v:115: Define or directive not defined: '`MPRJ_IO_PADS'\n    assign io_oeb = {(`MPRJ_IO_PADS-1){1'b1}};\n                      ^~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n"
module garo_poly3(
    output o_garo
    );

localparam [7:0] length = 8'd20;
wire [length:0] f;
assign o_garo = f[0];     

sky130_fd_sc_hd__inv_2 inverter1 (.A(f[1]),.Y(f[0]));
sky130_fd_sc_hd__inv_2 inverter2 (.A(f[2]),.Y(f[1]));

sky130_fd_sc_hd__xor2_4 xor_garo_1 (.A(f[0]), .B(f[3]), .X(f[2]));

sky130_fd_sc_hd__inv_2 inverter3 (.A(f[4]),.Y(f[3]));
sky130_fd_sc_hd__inv_2 inverter4 (.A(f[5]),.Y(f[4]));

sky130_fd_sc_hd__xor2_4 xor_garo_2 (.A(f[0]), .B(f[6]), .X(f[5]));

sky130_fd_sc_hd__inv_2 inverter5 (.A(f[7]),.Y(f[6]));

sky130_fd_sc_hd__xor2_4 xor_garo_3 (.A(f[0]), .B(f[8]), .X(f[7]));

sky130_fd_sc_hd__inv_2 inverter6 (.A(f[9]),.Y(f[8]));

sky130_fd_sc_hd__xor2_4 xor_garo_4 (.A(f[0]), .B(f[10]), .X(f[9]));

sky130_fd_sc_hd__inv_2 inverter7 (.A(f[11]),.Y(f[10]));

sky130_fd_sc_hd__xor2_4 xor_garo_5 (.A(f[0]), .B(f[12]), .X(f[11]));

sky130_fd_sc_hd__inv_2 inverter8 (.A(f[13]),.Y(f[12]));
sky130_fd_sc_hd__inv_2 inverter9 (.A(f[14]),.Y(f[13]));
sky130_fd_sc_hd__inv_2 inverter10 (.A(f[15]),.Y(f[14]));                          
sky130_fd_sc_hd__inv_2 inverter11 (.A(f[16]),.Y(f[15]));
sky130_fd_sc_hd__inv_2 inverter12 (.A(f[17]),.Y(f[16]));
sky130_fd_sc_hd__inv_2 inverter13 (.A(f[18]),.Y(f[17]));
sky130_fd_sc_hd__inv_2 inverter14 (.A(f[19]),.Y(f[18]));

sky130_fd_sc_hd__xor2_4 xor_garo_6 (.A(f[0]), .B(f[20]), .X(f[19]));

sky130_fd_sc_hd__inv_2 inverter15 (.A(f[0]),.Y(f[20]));

endmodule
module garo_poly3(
    output o_garo
    );


localparam [7:0] length = 8'd20;
wire [length:0] f;
assign o_garo = f[0];     

sky130_fd_sc_hd__inv_2 inverter1 (.A(f[1]),.Y(f[0]));
sky130_fd_sc_hd__inv_2 inverter2 (.A(f[2]),.Y(f[1]));

sky130_fd_sc_hd__xor2_4 xor_garo_1 (.A(f[0]), .B(f[3]), .X(f[2]));

sky130_fd_sc_hd__inv_2 inverter3 (.A(f[4]),.Y(f[3]));
sky130_fd_sc_hd__inv_2 inverter4 (.A(f[5]),.Y(f[4]));

sky130_fd_sc_hd__xor2_4 xor_garo_2 (.A(f[0]), .B(f[6]), .X(f[5]));

sky130_fd_sc_hd__inv_2 inverter5 (.A(f[7]),.Y(f[6]));

sky130_fd_sc_hd__xor2_4 xor_garo_3 (.A(f[0]), .B(f[8]), .X(f[7]));

sky130_fd_sc_hd__inv_2 inverter6 (.A(f[9]),.Y(f[8]));

sky130_fd_sc_hd__xor2_4 xor_garo_4 (.A(f[0]), .B(f[10]), .X(f[9]));

sky130_fd_sc_hd__inv_2 inverter7 (.A(f[11]),.Y(f[10]));

sky130_fd_sc_hd__xor2_4 xor_garo_5 (.A(f[0]), .B(f[12]), .X(f[11]));

sky130_fd_sc_hd__inv_2 inverter8 (.A(f[13]),.Y(f[12]));
sky130_fd_sc_hd__inv_2 inverter9 (.A(f[14]),.Y(f[13]));
sky130_fd_sc_hd__inv_2 inverter10 (.A(f[15]),.Y(f[14]));                          
sky130_fd_sc_hd__inv_2 inverter11 (.A(f[16]),.Y(f[15]));
sky130_fd_sc_hd__inv_2 inverter12 (.A(f[17]),.Y(f[16]));
sky130_fd_sc_hd__inv_2 inverter13 (.A(f[18]),.Y(f[17]));
sky130_fd_sc_hd__inv_2 inverter14 (.A(f[19]),.Y(f[18]));

sky130_fd_sc_hd__xor2_4 xor_garo_6 (.A(f[0]), .B(f[20]), .X(f[19]));

sky130_fd_sc_hd__inv_2 inverter15 (.A(f[0]),.Y(f[20]));

endmodule