data/full_repos/permissive/426999198/caravel_test/wiggly_ic_1_tb.sv
1: b'%Error: data/full_repos/permissive/426999198/caravel_test/wiggly_ic_1_tb.sv:20: Cannot find include file: uprj_netlists.v\n`include "uprj_netlists.v" // this file gets created automatically by multi_project_tools from the source section of info.yaml \n         ^~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/426999198/caravel_test,data/full_repos/permissive/426999198/uprj_netlists.v\n             data/full_repos/permissive/426999198/caravel_test,data/full_repos/permissive/426999198/uprj_netlists.v.v\n             data/full_repos/permissive/426999198/caravel_test,data/full_repos/permissive/426999198/uprj_netlists.v.sv\n             uprj_netlists.v\n             uprj_netlists.v.v\n             uprj_netlists.v.sv\n             obj_dir/uprj_netlists.v\n             obj_dir/uprj_netlists.v.v\n             obj_dir/uprj_netlists.v.sv\n%Error: data/full_repos/permissive/426999198/caravel_test/wiggly_ic_1_tb.sv:21: Cannot find include file: caravel_netlists.v\n`include "caravel_netlists.v" \n         ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/426999198/caravel_test/wiggly_ic_1_tb.sv:22: Cannot find include file: spiflash.v\n`include "spiflash.v" \n         ^~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n'
module wiggly_ic_1_tb;






	reg clk;
    reg RSTB;
	reg power1, power2;
	reg power3, power4;

    wire gpio;
    wire [37:0] mprj_io;


    wire        kbd_clk;
    wire        kbd_data;
    wire        mouse_clk_in;
    wire        mouse_data_in;
    assign mprj_io[ 8] = kbd_clk;
    assign mprj_io[ 9] = kbd_data;
    assign mprj_io[10] = mouse_clk_in;
    assign mprj_io[11] = mouse_data_in;
    wire        vga_clk_pix;
    assign vga_clk_pix = clk;

    wire [1:0] vga_r = mprj_io[13:12];
    wire [1:0] vga_g = mprj_io[15:14];
    wire [1:0] vga_b = mprj_io[17:16];
    wire       vga_hsync = mprj_io[18];
    wire       vga_vsync = mprj_io[19];


    

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3 = power1;
	wire VDD1V8 = power2;
	wire USER_VDD3V3 = power3;
	wire USER_VDD1V8 = power4;
	wire VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vssio	  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (USER_VDD3V3),
		.vdda2    (USER_VDD3V3),
		.vssa1	  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (USER_VDD1V8),
		.vccd2	  (USER_VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock	  (clk),
		.gpio     (gpio),
        	.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("wiggly_ic_1.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule
module wiggly_ic_1_tb;







	reg clk;
    reg RSTB;
	reg power1, power2;
	reg power3, power4;

    wire gpio;
    wire [37:0] mprj_io;


    wire        kbd_clk;
    wire        kbd_data;
    wire        mouse_clk_in;
    wire        mouse_data_in;
    assign mprj_io[ 8] = kbd_clk;
    assign mprj_io[ 9] = kbd_data;
    assign mprj_io[10] = mouse_clk_in;
    assign mprj_io[11] = mouse_data_in;
    wire        vga_clk_pix;
    assign vga_clk_pix = clk;

    wire [1:0] vga_r = mprj_io[13:12];
    wire [1:0] vga_g = mprj_io[15:14];
    wire [1:0] vga_b = mprj_io[17:16];
    wire       vga_hsync = mprj_io[18];
    wire       vga_vsync = mprj_io[19];


    

	wire flash_csb;
	wire flash_clk;
	wire flash_io0;
	wire flash_io1;

	wire VDD3V3 = power1;
	wire VDD1V8 = power2;
	wire USER_VDD3V3 = power3;
	wire USER_VDD1V8 = power4;
	wire VSS = 1'b0;

	caravel uut (
		.vddio	  (VDD3V3),
		.vssio	  (VSS),
		.vdda	  (VDD3V3),
		.vssa	  (VSS),
		.vccd	  (VDD1V8),
		.vssd	  (VSS),
		.vdda1    (USER_VDD3V3),
		.vdda2    (USER_VDD3V3),
		.vssa1	  (VSS),
		.vssa2	  (VSS),
		.vccd1	  (USER_VDD1V8),
		.vccd2	  (USER_VDD1V8),
		.vssd1	  (VSS),
		.vssd2	  (VSS),
		.clock	  (clk),
		.gpio     (gpio),
        	.mprj_io  (mprj_io),
		.flash_csb(flash_csb),
		.flash_clk(flash_clk),
		.flash_io0(flash_io0),
		.flash_io1(flash_io1),
		.resetb	  (RSTB)
	);

	spiflash #(
		.FILENAME("wiggly_ic_1.hex")
	) spiflash (
		.csb(flash_csb),
		.clk(flash_clk),
		.io0(flash_io0),
		.io1(flash_io1),
		.io2(),
		.io3()
	);

endmodule