data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/ADDER.v
1: b'%Error: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/ADDER.v:74: Cannot find file containing module: \'SIMPLE_COUNTER\'\nSIMPLE_COUNTER #(.BITWIDTH(BITWIDTH_MAX_IF_SIZE)) Simple_Counter (\n^~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules,data/full_repos/permissive/436253691/SIMPLE_COUNTER\n             data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules,data/full_repos/permissive/436253691/SIMPLE_COUNTER.v\n             data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules,data/full_repos/permissive/436253691/SIMPLE_COUNTER.sv\n             SIMPLE_COUNTER\n             SIMPLE_COUNTER.v\n             SIMPLE_COUNTER.sv\n             obj_dir/SIMPLE_COUNTER\n             obj_dir/SIMPLE_COUNTER.v\n             obj_dir/SIMPLE_COUNTER.sv\n%Error: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/ADDER.v:90: Cannot find file containing module: \'ADDER_STATEMACHINE\'\nADDER_STATEMACHINE Adder_Statemachine(\n^~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/ADDER.v:116: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'ADDER_Out_Mem1\' generates 16 bits.\n                                                                                                                   : ... In instance ADDER\n   Adder_out<= ADDER_Out_Mem1;\n            ^~\n                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/ADDER.v:118: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'ADDER_Out_Mem1\' generates 16 bits.\n                                                                                                                   : ... In instance ADDER\n   Adder_out<= ADDER_Out_Mem1 + ADDER_Out_Mem2;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/ADDER.v:118: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'ADDER_Out_Mem2\' generates 16 bits.\n                                                                                                                   : ... In instance ADDER\n   Adder_out<= ADDER_Out_Mem1 + ADDER_Out_Mem2;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/ADDER.v:120: Operator ADD expects 32 bits on the LHS, but LHS\'s VARREF \'ADDER_Out_Mem1\' generates 16 bits.\n                                                                                                                   : ... In instance ADDER\n   Adder_out<= ADDER_Out_Mem1 + ADDER_Out_Mem2 + ADDER_Out_Mem3;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/ADDER.v:120: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'ADDER_Out_Mem2\' generates 16 bits.\n                                                                                                                   : ... In instance ADDER\n   Adder_out<= ADDER_Out_Mem1 + ADDER_Out_Mem2 + ADDER_Out_Mem3;\n                              ^\n%Warning-WIDTH: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/ADDER.v:120: Operator ADD expects 32 bits on the RHS, but RHS\'s VARREF \'ADDER_Out_Mem3\' generates 16 bits.\n                                                                                                                   : ... In instance ADDER\n   Adder_out<= ADDER_Out_Mem1 + ADDER_Out_Mem2 + ADDER_Out_Mem3;\n                                               ^\n%Warning-WIDTH: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/ADDER.v:119: Operator EQ expects 3 bits on the RHS, but RHS\'s CONST \'2\'h3\' generates 2 bits.\n                                                                                                                   : ... In instance ADDER\n  else if (ADDER_If_Channels == 2\'d3)\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/ADDER.v:117: Operator EQ expects 3 bits on the RHS, but RHS\'s CONST \'2\'h2\' generates 2 bits.\n                                                                                                                   : ... In instance ADDER\n  else if (ADDER_If_Channels == 2\'d2)\n                             ^~\n%Warning-WIDTH: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/ADDER.v:115: Operator EQ expects 3 bits on the RHS, but RHS\'s CONST \'2\'h1\' generates 2 bits.\n                                                                                                                   : ... In instance ADDER\n  if(ADDER_If_Channels == 2\'d1)\n                       ^~\n%Warning-WIDTH: data/full_repos/permissive/436253691/hardware/nios_sys/nios_system/synthesis/submodules/ADDER.v:123: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'16\'h0\' generates 16 bits.\n                                                                                                                   : ... In instance ADDER\n  Adder_out<=16\'b0;\n           ^~\n%Error: Exiting due to 2 error(s), 10 warning(s)\n'
module ADDER #(parameter MEM_OUT_DATA_WIDTH = 16, BITWIDTH_MAX_IF_SIZE= 22, BITWIDTH_DATA_OUT= 32, BITWIDTH_IF_CHANNELS= 3)(


ADDER_Clk,
ADDER_Start_Routine,
ADDER_Routine_Finished_Already_Ok,
ADDER_If_Channels,
ADDER_Of_Size,
ADDER_Out_Mem1,
ADDER_Out_Mem2,
ADDER_Out_Mem3,



ADDER_Out,
ADDER_Routine_Finished_Already,
ADDER_Channel_Mems_Re

);




input ADDER_Clk;
input ADDER_Start_Routine;
input ADDER_Routine_Finished_Already_Ok;
input [BITWIDTH_IF_CHANNELS-1:0] ADDER_If_Channels;
input [BITWIDTH_MAX_IF_SIZE-1:0] ADDER_Of_Size;
input [MEM_OUT_DATA_WIDTH-1:0] ADDER_Out_Mem1;
input [MEM_OUT_DATA_WIDTH-1:0] ADDER_Out_Mem2;
input [MEM_OUT_DATA_WIDTH-1:0] ADDER_Out_Mem3;

output signed[BITWIDTH_DATA_OUT-1:0] ADDER_Out;
output ADDER_Routine_Finished_Already;
output ADDER_Channel_Mems_Re;





wire Simple_Counter_Eqn_Flag;
wire Adder_Statemachine_Counter_Clr;
wire Adder_Statemachine_Counter_En;
wire Adder_Statemachine_Counter_Load;

reg signed[BITWIDTH_DATA_OUT-1:0] Adder_out;
wire [BITWIDTH_MAX_IF_SIZE-1:0] Simple_Counter_Out;





SIMPLE_COUNTER #(.BITWIDTH(BITWIDTH_MAX_IF_SIZE)) Simple_Counter (


.COUNTER_Clk(ADDER_Clk),
.COUNTER_Clr(Adder_Statemachine_Counter_Clr),
.COUNTER_En(Adder_Statemachine_Counter_En),
.COUNTER_Number(ADDER_Of_Size),


.COUNTER_Out(Simple_Counter_Out),
.COUNTER_Eqn_Flag(Simple_Counter_Eqn_Flag)
);




ADDER_STATEMACHINE Adder_Statemachine(


.ADDER_STATEMACHINE_Clk(ADDER_Clk),
.ADDER_STATEMACHINE_Start_Routine(ADDER_Start_Routine),
.ADDER_STATEMACHINE_Counter_Flag(Simple_Counter_Eqn_Flag),
.ADDER_STATEMACHINE_Routine_Finished_Already_Ok(ADDER_Routine_Finished_Already_Ok),


.ADDER_STATEMACHINE_Mems_Re(ADDER_Channel_Mems_Re),
.ADDER_STATEMACHINE_Counter_Clr(Adder_Statemachine_Counter_Clr),
.ADDER_STATEMACHINE_Counter_En(Adder_Statemachine_Counter_En),
.ADDER_STATEMACHINE_Routine_Finished_Already(ADDER_Routine_Finished_Already)

);






always@(posedge ADDER_Clk)
begin
	if(Adder_Statemachine_Counter_En)
	begin
		if(ADDER_If_Channels == 2'd1)
			Adder_out<= ADDER_Out_Mem1;
		else if (ADDER_If_Channels == 2'd2)
			Adder_out<= ADDER_Out_Mem1 + ADDER_Out_Mem2;
		else if (ADDER_If_Channels == 2'd3)
			Adder_out<= ADDER_Out_Mem1 + ADDER_Out_Mem2 + ADDER_Out_Mem3;
	end
	else
		Adder_out<=16'b0;
end


assign ADDER_Out= Adder_out;

endmodule
module ADDER #(parameter MEM_OUT_DATA_WIDTH = 16, BITWIDTH_MAX_IF_SIZE= 22, BITWIDTH_DATA_OUT= 32, BITWIDTH_IF_CHANNELS= 3)(


ADDER_Clk,
ADDER_Start_Routine,
ADDER_Routine_Finished_Already_Ok,
ADDER_If_Channels,
ADDER_Of_Size,
ADDER_Out_Mem1,
ADDER_Out_Mem2,
ADDER_Out_Mem3,



ADDER_Out,
ADDER_Routine_Finished_Already,
ADDER_Channel_Mems_Re

);





input ADDER_Clk;
input ADDER_Start_Routine;
input ADDER_Routine_Finished_Already_Ok;
input [BITWIDTH_IF_CHANNELS-1:0] ADDER_If_Channels;
input [BITWIDTH_MAX_IF_SIZE-1:0] ADDER_Of_Size;
input [MEM_OUT_DATA_WIDTH-1:0] ADDER_Out_Mem1;
input [MEM_OUT_DATA_WIDTH-1:0] ADDER_Out_Mem2;
input [MEM_OUT_DATA_WIDTH-1:0] ADDER_Out_Mem3;

output signed[BITWIDTH_DATA_OUT-1:0] ADDER_Out;
output ADDER_Routine_Finished_Already;
output ADDER_Channel_Mems_Re;





wire Simple_Counter_Eqn_Flag;
wire Adder_Statemachine_Counter_Clr;
wire Adder_Statemachine_Counter_En;
wire Adder_Statemachine_Counter_Load;

reg signed[BITWIDTH_DATA_OUT-1:0] Adder_out;
wire [BITWIDTH_MAX_IF_SIZE-1:0] Simple_Counter_Out;





SIMPLE_COUNTER #(.BITWIDTH(BITWIDTH_MAX_IF_SIZE)) Simple_Counter (


.COUNTER_Clk(ADDER_Clk),
.COUNTER_Clr(Adder_Statemachine_Counter_Clr),
.COUNTER_En(Adder_Statemachine_Counter_En),
.COUNTER_Number(ADDER_Of_Size),


.COUNTER_Out(Simple_Counter_Out),
.COUNTER_Eqn_Flag(Simple_Counter_Eqn_Flag)
);




ADDER_STATEMACHINE Adder_Statemachine(


.ADDER_STATEMACHINE_Clk(ADDER_Clk),
.ADDER_STATEMACHINE_Start_Routine(ADDER_Start_Routine),
.ADDER_STATEMACHINE_Counter_Flag(Simple_Counter_Eqn_Flag),
.ADDER_STATEMACHINE_Routine_Finished_Already_Ok(ADDER_Routine_Finished_Already_Ok),


.ADDER_STATEMACHINE_Mems_Re(ADDER_Channel_Mems_Re),
.ADDER_STATEMACHINE_Counter_Clr(Adder_Statemachine_Counter_Clr),
.ADDER_STATEMACHINE_Counter_En(Adder_Statemachine_Counter_En),
.ADDER_STATEMACHINE_Routine_Finished_Already(ADDER_Routine_Finished_Already)

);






always@(posedge ADDER_Clk)
begin
	if(Adder_Statemachine_Counter_En)
	begin
		if(ADDER_If_Channels == 2'd1)
			Adder_out<= ADDER_Out_Mem1;
		else if (ADDER_If_Channels == 2'd2)
			Adder_out<= ADDER_Out_Mem1 + ADDER_Out_Mem2;
		else if (ADDER_If_Channels == 2'd3)
			Adder_out<= ADDER_Out_Mem1 + ADDER_Out_Mem2 + ADDER_Out_Mem3;
	end
	else
		Adder_out<=16'b0;
end


assign ADDER_Out= Adder_out;

endmodule