data/full_repos/permissive/452461941/AES_Decryption/Counter.v
data/verilator_xmls/795e18e9-d665-44cd-89dd-137193fc63dc.xml
module Counter #(n = 4)(output reg [n-1:0] count, input [n-1:0] loadValue, input load, increment, decrement, clock, reset);
	always @(posedge clock, posedge reset) begin
		if (reset)
			count <= 0;
		else if (load)
			count <= loadValue;
		else if (increment)
			count <= count + 1;
		else if (decrement)
			count <= count - 1;
	end

endmodule
module Counter #(n = 4)(output reg [n-1:0] count, input [n-1:0] loadValue, input load, increment, decrement, clock, reset);

	always @(posedge clock, posedge reset) begin
		if (reset)
			count <= 0;
		else if (load)
			count <= loadValue;
		else if (increment)
			count <= count + 1;
		else if (decrement)
			count <= count - 1;
	end

endmodule