data/full_repos/permissive/515598112/2_Verilog_Language/02_Vectors/07_Vector_reversal_1.v
1: b'%Warning-MODDUP: data/full_repos/permissive/515598112/2_Verilog_Language/02_Vectors/07_Vector_reversal_1.v:47: Duplicate declaration of module: \'top_module\'\nmodule top_module( \n       ^~~~~~~~~~\n                 data/full_repos/permissive/515598112/2_Verilog_Language/02_Vectors/07_Vector_reversal_1.v:2: ... Location of original declaration\nmodule top_module (\n       ^~~~~~~~~~\n                 ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n'
module top_module (
	input [7:0] in,
	output [7:0] out
);
	
	assign {out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7]} = in;
	

	
endmodule
module top_module (
	input [7:0] in,
	output [7:0] out
);

	
	assign {out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7]} = in;
	

	
endmodule