data/full_repos/permissive/425063934/custom_layout/sim/ra_lcb_ddr.v
1: b'%Error: data/full_repos/permissive/425063934/custom_layout/sim/ra_lcb_ddr.v:27: Cannot find include file: toysram.vh\n`include "toysram.vh" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/425063934/custom_layout/sim,data/full_repos/permissive/425063934/toysram.vh\n             data/full_repos/permissive/425063934/custom_layout/sim,data/full_repos/permissive/425063934/toysram.vh.v\n             data/full_repos/permissive/425063934/custom_layout/sim,data/full_repos/permissive/425063934/toysram.vh.sv\n             toysram.vh\n             toysram.vh.v\n             toysram.vh.sv\n             obj_dir/toysram.vh\n             obj_dir/toysram.vh.v\n             obj_dir/toysram.vh.sv\n%Error: data/full_repos/permissive/425063934/custom_layout/sim/ra_lcb_ddr.v:39: Define or directive not defined: \'`GENMODE\'\n parameter GENMODE = `GENMODE;          \n                     ^~~~~~~~\n%Error: data/full_repos/permissive/425063934/custom_layout/sim/ra_lcb_ddr.v:39: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter GENMODE = `GENMODE;          \n                             ^\n%Error: data/full_repos/permissive/425063934/custom_layout/sim/ra_lcb_ddr.v:43: Define or directive not defined: \'`LCBDDR_CONFIGWIDTH\'\n   input [0:`LCBDDR_CONFIGWIDTH-1] cfg;\n            ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n'
module  ra_lcb_ddr (

    clk,
    reset,
    cfg,
    strobe,
    el_sel

);

 parameter GENMODE = `GENMODE;

   input  clk;
   input  reset;
   input [0:`LCBDDR_CONFIGWIDTH-1] cfg;
   output strobe;
   output el_sel;



         reg el_sel_q;


   wire clk_dly;
   wire o0;
   wire o1;
   wire clk_dly2;


generate

  if (GENMODE == 0)
     assign strobe = !clk & !reset;
  else begin






   ra_delay d0 (
      .i(clk),
      .o(o0)
   );




   assign clk_dly = o0;


   ra_delay w0 (
      .i(clk_dly),
      .o(o1)
   );




   assign clk_dly2 = o1;


   assign strobe = clk_dly & !clk_dly2;

  end

endgenerate


generate

   if (GENMODE == 0) begin
      always @ (posedge clk)
         if (reset)
            el_sel_q <= 1'b0;
         else
            el_sel_q <= !el_sel_q;
      assign el_sel = el_sel_q;
   end else begin



   end

endgenerate

endmodule
module  ra_lcb_ddr (

    clk,
    reset,
    cfg,
    strobe,
    el_sel

);


 parameter GENMODE = `GENMODE;

   input  clk;
   input  reset;
   input [0:`LCBDDR_CONFIGWIDTH-1] cfg;
   output strobe;
   output el_sel;



         reg el_sel_q;


   wire clk_dly;
   wire o0;
   wire o1;
   wire clk_dly2;


generate

  if (GENMODE == 0)
     assign strobe = !clk & !reset;
  else begin






   ra_delay d0 (
      .i(clk),
      .o(o0)
   );




   assign clk_dly = o0;


   ra_delay w0 (
      .i(clk_dly),
      .o(o1)
   );




   assign clk_dly2 = o1;


   assign strobe = clk_dly & !clk_dly2;

  end

endgenerate


generate

   if (GENMODE == 0) begin
      always @ (posedge clk)
         if (reset)
            el_sel_q <= 1'b0;
         else
            el_sel_q <= !el_sel_q;
      assign el_sel = el_sel_q;
   end else begin



   end

endgenerate

endmodule