data/full_repos/permissive/502764644/mpeg_audio_video/AC97/ac97_ctr.v
1: b'%Error: data/full_repos/permissive/502764644/mpeg_audio_video/AC97/ac97_ctr.v:3: Cannot find include file: defines.v\n`include "defines.v" \n         ^~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/502764644/mpeg_audio_video/AC97,data/full_repos/permissive/502764644/defines.v\n             data/full_repos/permissive/502764644/mpeg_audio_video/AC97,data/full_repos/permissive/502764644/defines.v.v\n             data/full_repos/permissive/502764644/mpeg_audio_video/AC97,data/full_repos/permissive/502764644/defines.v.sv\n             defines.v\n             defines.v.v\n             defines.v.sv\n             obj_dir/defines.v\n             obj_dir/defines.v.v\n             obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/AC97/ac97_ctr.v:162: Define or directive not defined: \'`FREQUENCY_48K\'\n    `FREQUENCY_48K: cur_sample_frequency <= 16\'hBB80;\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/AC97/ac97_ctr.v:162: syntax error, unexpected \':\', expecting endcase\n    `FREQUENCY_48K: cur_sample_frequency <= 16\'hBB80;\n                  ^\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/AC97/ac97_ctr.v:163: Define or directive not defined: \'`FREQUENCY_44K\'\n    `FREQUENCY_44K: cur_sample_frequency <= 16\'hAC44;\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/AC97/ac97_ctr.v:164: Define or directive not defined: \'`FREQUENCY_32K\'\n    `FREQUENCY_32K: cur_sample_frequency <= 16\'h7D00;\n    ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/AC97/ac97_ctr.v:176: syntax error, unexpected else\n     else begin\n     ^~~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/AC97/ac97_ctr.v:186: syntax error, unexpected INTEGER NUMBER\n    \'d1: begin\n    ^~~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/AC97/ac97_ctr.v:305: syntax error, unexpected <=, expecting IDENTIFIER\n     if (pause_cnt == 0) state <= \'d16;\n                               ^~\n%Error: data/full_repos/permissive/502764644/mpeg_audio_video/AC97/ac97_ctr.v:314: syntax error, unexpected <=, expecting IDENTIFIER\n     if (pause_cnt == 0) state <= \'d15;  \n                               ^~\n%Error: Exiting due to 9 error(s)\n'
module ac97_ctr(
	BIT_CLOCK_I,
	SAMPLE_FREQUENCY_I,
	AC97_RESETN_I,
	SOURCE_SELECT_I,
	AC97_SYNCH_O,
	AC97_DATA_IN_I,
	AC97_DATA_OUT_O,
	AC97_BEEP_TONE_O,
	PCM_READ_ADVANCE_EN_I,
	PCM_READ_ADDRESS_O,
	CH0_PCM_DATA_I,
	CH1_PCM_DATA_I,
	STARTUP_O
);	

    input BIT_CLOCK_I;
	 input AC97_RESETN_I;
	 input [1:0] SAMPLE_FREQUENCY_I;
	 input SOURCE_SELECT_I;
    output AC97_SYNCH_O;
    input AC97_DATA_IN_I;
    output AC97_DATA_OUT_O;
    output AC97_BEEP_TONE_O;
    output STARTUP_O;
	 input [`DATA_WIDTH-1:0] CH0_PCM_DATA_I;
	 input [`DATA_WIDTH-1:0] CH1_PCM_DATA_I;
    input PCM_READ_ADVANCE_EN_I;
	 output [`ADDRESS_WIDTH-1:0] PCM_READ_ADDRESS_O;
	 
    wire AC97_SYNCH;
    reg  AC97_SYNCH_buffer, AC97_SYNCH_buffer_buffer;
    wire AC97_DATA_OUT;
    reg  AC97_codec_ready;


    reg	[15:0]	out_slt0;
    reg	[19:0]	out_slt1;
    reg	[19:0]	out_slt2;
    reg	[19:0]	out_slt3;
    reg	[19:0]	out_slt4;


    wire	[15:0]	in_slt0;
    wire	[19:0]	in_slt1;
    wire	[19:0]	in_slt2;
    wire	[19:0]	in_slt3;
    wire	[19:0]	in_slt4;


    wire	ld;
    wire	[4:0] out_le;
    reg [4:0] state;

	 reg [15:0] cur_sample_frequency;

	 wire pause_cnt;

	 reg [`ADDRESS_WIDTH-1:0] sample_counter;

	 parameter reset_reg_set = 1'b1;

	 parameter pc_beep_set = 1'b1;

	 parameter line_out_set = 1'b0;
	 parameter line_out_mute = 1'b0;
	 parameter line_out_left = 5'h08;
	 parameter line_out_right = 5'h08;

	 parameter level_out_set = 1'b1;
	 parameter level_mute = 1'b0;
	 parameter level_left = 5'h08;
	 parameter level_right = 5'h08;

	 parameter mono_out_set = 1'b1;
	 parameter mono_mute = 1'b0;
	 parameter mono_left = 5'h08;
	 parameter mono_right = 5'h08;

	 parameter phone_volume_set = 1'b1;
	 parameter phone_mute = 1'b0;
	 parameter phone_volume = 5'h08;

	 parameter mic_volume_set = 1'b0;
	 parameter mic_mute = 1'b0;
	 parameter mic_volume = 5'h08;

	 parameter line_in_set = 1'b1;
	 parameter line_in_mute = 1'b0;
	 parameter line_in_left = 5'h08;
	 parameter line_in_right = 5'h08;

	 parameter PCM_set = 1'b0;
	 parameter PCM_mute = 1'b0;
	 parameter PCM_left = 5'h08;
	 parameter PCM_right = 5'h08;



	 parameter record_select_set = 1'b0;
	 parameter record_select_left = 3'h0;
	 parameter record_select_right = 3'h0;

	 parameter record_gain_set = 1'b0;
	 parameter record_gain_mute = 1'b0;
	 parameter record_gain_left = 4'h0;
	 parameter record_gain_right = 4'h0;

	 parameter gp_set = 1'b1;
	 parameter gp_pop = 1'b0;
	 parameter gp_3d = 1'b1;
	 parameter gp_mix = 1'b0;
	 parameter gp_ms = 1'b0;
	 parameter gp_LPBK = 1'b0;

 	 parameter extended_audio_set = 1'b0;
	 parameter variable_frequency = 1'b1;

	 parameter sample_set = 1'b0;
	 

	 assign AC97_BEEP_TONE_O = 1'b1;

    always @(posedge BIT_CLOCK_I or negedge AC97_RESETN_I)
    begin
    		if (AC97_RESETN_I == 1'b0) begin
			AC97_codec_ready <= 1'b0;
			AC97_SYNCH_buffer <= 1'b0;
			AC97_SYNCH_buffer_buffer <= 1'b0;
		end
    		else begin
			if (AC97_SYNCH_buffer_buffer == 1'b0 && AC97_SYNCH_buffer == 1'b1)
				AC97_codec_ready <= AC97_DATA_IN_I;						
			AC97_SYNCH_buffer <= AC97_SYNCH;
			AC97_SYNCH_buffer_buffer <= AC97_SYNCH_buffer;
		end
    end



	 assign STARTUP_O = AC97_RESETN_I;

	 always @ (state or SAMPLE_FREQUENCY_I) begin
	 	if (state <= 'd15) cur_sample_frequency <= 16'hBB80;
		else begin
			case (SAMPLE_FREQUENCY_I)
				`FREQUENCY_48K: cur_sample_frequency <= 16'hBB80;
				`FREQUENCY_44K: cur_sample_frequency <= 16'hAC44;
				`FREQUENCY_32K: cur_sample_frequency <= 16'h7D00;
				default: cur_sample_frequency <= 16'h1F40;
			endcase
		end
	 end

	 always @(posedge BIT_CLOCK_I or negedge AC97_RESETN_I)
    begin
    	if (AC97_RESETN_I == 1'b0) begin
			state <= 'd0;
			out_slt0 <= 0;
		end
    	else begin
  			if (AC97_SYNCH_buffer == 1'b0 && AC97_SYNCH == 1'b1) begin
				case (state)
		      'd0  : begin


			    	out_slt1 <= {1'b1, 19'h00000};		 
			    	out_slt2 <= 20'h00000;		 
					if (AC97_codec_ready) state <= 'd1;	
		      end
				'd1: begin

					out_slt0 <= {1'b1, 2'b11, 2'b00, 11'h0 };
			    	out_slt1 <= {reset_reg_set, 7'h00, 12'h000};		 
			    	out_slt2 <= 20'h00000;

					state <= 'd2;	 
				end
				'd2: begin

					out_slt0 <= {1'b1, 2'b11, 2'b00, 11'h0 };
			    	out_slt1 <= {line_out_set, 7'h02, 12'h000};		 
			    	out_slt2 <= {line_out_mute, 2'b00, line_out_left, 3'b000, line_out_right, 4'h0};		
	
					state <= 'd3;	 
				end
				'd3: begin

					out_slt0 <= {1'b1, 2'b11, 2'b00, 11'h0 };
			    	out_slt1 <= {level_out_set, 7'h04, 12'h000};		 
			    	out_slt2 <= {level_mute, 2'b00, level_left, 3'b000, level_right, 4'h0};		

					state <= 'd4;	 
				end
				'd4: begin

					out_slt0 <= {1'b1, 2'b11, 2'b00, 11'h0 };
			    	out_slt1 <= {mono_out_set, 7'h06, 12'h000};		 
			    	out_slt2 <= {level_mute, 2'b00, 4'h0, 3'b000, mono_right, 4'h0};		

					state <= 'd5;	 
				end
				'd5: begin

					out_slt0 <= {1'b1, 2'b11, 2'b00, 11'h0 };
			    	out_slt1 <= {pc_beep_set, 7'h0a, 12'h000};		 
			    	out_slt2 <= 20'h00000;

					state <= 'd6;	 
				end
				'd6: begin

					out_slt0 <= {1'b1, 2'b11, 2'b00, 11'h0 };
			    	out_slt1 <= {phone_volume_set, 7'h0c, 12'h000};		 
			    	out_slt2 <= {phone_mute, 12'h000, phone_volume, 4'h0};		

					state <= 'd7;	 
				end
				'd7: begin

					out_slt0 <= {1'b1, 2'b11, 2'b00, 11'h0 };
			    	out_slt1 <= {mic_volume_set, 7'h0e, 12'h000};		 
			    	out_slt2 <= {mic_mute, 12'h000, mic_volume, 4'h0};		

					state <= 'd8;	 
				end
				'd8: begin

					out_slt0 <= {1'b1, 2'b11, 2'b00, 11'h0 };

			    	out_slt1 <= {line_in_set, 7'h10, 12'h000};		 
			    	out_slt2 <= {line_in_mute, 2'b00, line_in_left, 3'h0, line_in_right, 4'h0};		

					state <= 'd9;	 
				end
				'd9: begin

					out_slt0 <= {1'b1, 2'b11, 2'b00, 11'h0 };
					out_slt1 <= {PCM_set, 7'h18, 12'h000};		 
			    	out_slt2 <= {PCM_mute, 2'b00, PCM_left, 3'h0, PCM_right, 4'h0};		

					state <= 'd10;	 
				end
				'd10: begin

					out_slt0 <= {1'b1, 2'b11, 2'b00, 11'h0 };
					out_slt1 <= {record_select_set, 7'h1a, 12'h000};		 
			    	out_slt2 <= {5'h00, record_select_left, 5'h00, record_select_right, 4'h0};		

					state <= 'd11;	 
				end
				'd11: begin

					out_slt0 <= {1'b1, 2'b11, 2'b00, 11'h0 };
					out_slt1 <= {record_gain_set, 7'h1c, 12'h000};		 
			    	out_slt2 <= {record_gain_mute, 3'b00, record_gain_left, 4'h0, record_gain_right, 4'h0};		
					
					state <= 'd12;	 
				end
				'd12: begin

					out_slt0 <= {1'b1, 2'b11, 2'b00, 11'h0 };
					out_slt1 <= {gp_set, 7'h20, 12'h000};		 
			    	out_slt2 <= {gp_pop, 1'b0, gp_3d, 3'h0, gp_mix, gp_ms, gp_LPBK, 11'h000};
					
					state <= 'd13;	 
				end
				'd13: begin

					out_slt0 <= {1'b1, 2'b11, 2'b00, 11'h0 };
					out_slt1 <= {1'd1, 7'h26, 12'h000};		 
			    	out_slt2 <= 20'h00000;
						 					
					state <= 'd14;	 
				end
				'd14: begin

					out_slt0 <= {1'b1, 2'b11, 2'b00, 11'h0 };
					out_slt1 <= {extended_audio_set, 7'h2a, 12'h000};		 
			    	out_slt2 <= {15'h0, variable_frequency};
					
					state <= 'd15;	 
				end
				'd15: begin

					out_slt0 <= {1'b1, 2'b11, 2'b11, 11'h0 };
					out_slt1 <= {sample_set, 7'h2c, 12'h000};		 
			    	out_slt2 <= {4'h0, cur_sample_frequency};
					
					if (pause_cnt == 0) state <= 'd16;
				end

				'd16: begin

					out_slt0 <= {1'b1, 2'b11, 2'b11, 11'h0 };
					out_slt1 <= {sample_set, 7'h32, 12'h000};		 
		    		out_slt2 <= {4'h0, cur_sample_frequency};

					if (pause_cnt == 0) state <= 'd15;	 
				end
				endcase
			end
		end
    end

	 always @(posedge BIT_CLOCK_I or negedge AC97_RESETN_I)
    begin
    	if (AC97_RESETN_I == 1'b0) begin
			out_slt3 <= 0;
			out_slt4 <= 0;
		end
    	else begin
  			if (AC97_SYNCH_buffer == 1'b1 && AC97_SYNCH == 1'b0) begin
				if (state < 'd15) begin
					out_slt3 <= 0;
					out_slt4 <= 0;
				end else begin

					if (SOURCE_SELECT_I == 1'b1) begin
						out_slt3 <= {CH0_PCM_DATA_I, 4'h0};
						out_slt4 <= {CH1_PCM_DATA_I, 4'h0};
					end
					else begin
						out_slt3 <= in_slt3;
						out_slt4 <= in_slt4;
					end			
				end
			end
		end
	end


	always @(posedge BIT_CLOCK_I or negedge AC97_RESETN_I)
   begin
    	if (AC97_RESETN_I == 1'b0) begin

			sample_counter <= 10'd0;
		end else begin
				if (state >= 'd15) begin
					if (AC97_SYNCH_buffer == 1'b0 && AC97_SYNCH == 1'b1) 
						if (PCM_READ_ADVANCE_EN_I)
							sample_counter <= sample_counter + 10'd1;
				end

		end
	end

	assign PCM_READ_ADDRESS_O = sample_counter;

    ac97_sout u0(
		.clk(BIT_CLOCK_I),
		.so_ld(ld),
		.slt0(out_slt0),
		.slt1(out_slt1),
		.slt2(out_slt2),
		.slt3(out_slt3),
		.slt4(out_slt4),
		.sdata_out(AC97_DATA_OUT)
		);

    ac97_sin u1(
		.clk(BIT_CLOCK_I),
		.out_le(out_le),
		.slt0(in_slt0),
		.slt1(in_slt1),
		.slt2(in_slt2),
		.slt3(in_slt3),
		.slt4(in_slt4),
		.sdata_in(AC97_DATA_IN_I)
		);

    ac97_soc u2(
    	.clk(BIT_CLOCK_I),
		.rst(AC97_RESETN_I),
		.sample_frequency(cur_sample_frequency),
		.sync(AC97_SYNCH),
		.out_le(out_le),
		.ld(ld),
		.pause_cnt(pause_cnt)
		);

   assign AC97_DATA_OUT_O = AC97_codec_ready && AC97_DATA_OUT;
   assign AC97_SYNCH_O = AC97_SYNCH;

endmodule
module ac97_ctr(
	BIT_CLOCK_I,
	SAMPLE_FREQUENCY_I,
	AC97_RESETN_I,
	SOURCE_SELECT_I,
	AC97_SYNCH_O,
	AC97_DATA_IN_I,
	AC97_DATA_OUT_O,
	AC97_BEEP_TONE_O,
	PCM_READ_ADVANCE_EN_I,
	PCM_READ_ADDRESS_O,
	CH0_PCM_DATA_I,
	CH1_PCM_DATA_I,
	STARTUP_O
);
	

    input BIT_CLOCK_I;
	 input AC97_RESETN_I;
	 input [1:0] SAMPLE_FREQUENCY_I;
	 input SOURCE_SELECT_I;
    output AC97_SYNCH_O;
    input AC97_DATA_IN_I;
    output AC97_DATA_OUT_O;
    output AC97_BEEP_TONE_O;
    output STARTUP_O;
	 input [`DATA_WIDTH-1:0] CH0_PCM_DATA_I;
	 input [`DATA_WIDTH-1:0] CH1_PCM_DATA_I;
    input PCM_READ_ADVANCE_EN_I;
	 output [`ADDRESS_WIDTH-1:0] PCM_READ_ADDRESS_O;
	 
    wire AC97_SYNCH;
    reg  AC97_SYNCH_buffer, AC97_SYNCH_buffer_buffer;
    wire AC97_DATA_OUT;
    reg  AC97_codec_ready;


    reg	[15:0]	out_slt0;
    reg	[19:0]	out_slt1;
    reg	[19:0]	out_slt2;
    reg	[19:0]	out_slt3;
    reg	[19:0]	out_slt4;


    wire	[15:0]	in_slt0;
    wire	[19:0]	in_slt1;
    wire	[19:0]	in_slt2;
    wire	[19:0]	in_slt3;
    wire	[19:0]	in_slt4;


    wire	ld;
    wire	[4:0] out_le;
    reg [4:0] state;

	 reg [15:0] cur_sample_frequency;

	 wire pause_cnt;

	 reg [`ADDRESS_WIDTH-1:0] sample_counter;

	 parameter reset_reg_set = 1'b1;

	 parameter pc_beep_set = 1'b1;

	 parameter line_out_set = 1'b0;
	 parameter line_out_mute = 1'b0;
	 parameter line_out_left = 5'h08;
	 parameter line_out_right = 5'h08;

	 parameter level_out_set = 1'b1;
	 parameter level_mute = 1'b0;
	 parameter level_left = 5'h08;
	 parameter level_right = 5'h08;

	 parameter mono_out_set = 1'b1;
	 parameter mono_mute = 1'b0;
	 parameter mono_left = 5'h08;
	 parameter mono_right = 5'h08;

	 parameter phone_volume_set = 1'b1;
	 parameter phone_mute = 1'b0;
	 parameter phone_volume = 5'h08;

	 parameter mic_volume_set = 1'b0;
	 parameter mic_mute = 1'b0;
	 parameter mic_volume = 5'h08;

	 parameter line_in_set = 1'b1;
	 parameter line_in_mute = 1'b0;
	 parameter line_in_left = 5'h08;
	 parameter line_in_right = 5'h08;

	 parameter PCM_set = 1'b0;
	 parameter PCM_mute = 1'b0;
	 parameter PCM_left = 5'h08;
	 parameter PCM_right = 5'h08;



	 parameter record_select_set = 1'b0;
	 parameter record_select_left = 3'h0;
	 parameter record_select_right = 3'h0;

	 parameter record_gain_set = 1'b0;
	 parameter record_gain_mute = 1'b0;
	 parameter record_gain_left = 4'h0;
	 parameter record_gain_right = 4'h0;

	 parameter gp_set = 1'b1;
	 parameter gp_pop = 1'b0;
	 parameter gp_3d = 1'b1;
	 parameter gp_mix = 1'b0;
	 parameter gp_ms = 1'b0;
	 parameter gp_LPBK = 1'b0;

 	 parameter extended_audio_set = 1'b0;
	 parameter variable_frequency = 1'b1;

	 parameter sample_set = 1'b0;
	 

	 assign AC97_BEEP_TONE_O = 1'b1;

    always @(posedge BIT_CLOCK_I or negedge AC97_RESETN_I)
    begin
    		if (AC97_RESETN_I == 1'b0) begin
			AC97_codec_ready <= 1'b0;
			AC97_SYNCH_buffer <= 1'b0;
			AC97_SYNCH_buffer_buffer <= 1'b0;
		end
    		else begin
			if (AC97_SYNCH_buffer_buffer == 1'b0 && AC97_SYNCH_buffer == 1'b1)
				AC97_codec_ready <= AC97_DATA_IN_I;						
			AC97_SYNCH_buffer <= AC97_SYNCH;
			AC97_SYNCH_buffer_buffer <= AC97_SYNCH_buffer;
		end
    end



	 assign STARTUP_O = AC97_RESETN_I;

	 always @ (state or SAMPLE_FREQUENCY_I) begin
	 	if (state <= 'd15) cur_sample_frequency <= 16'hBB80;
		else begin
			case (SAMPLE_FREQUENCY_I)
				`FREQUENCY_48K: cur_sample_frequency <= 16'hBB80;
				`FREQUENCY_44K: cur_sample_frequency <= 16'hAC44;
				`FREQUENCY_32K: cur_sample_frequency <= 16'h7D00;
				default: cur_sample_frequency <= 16'h1F40;
			endcase
		end
	 end

	 always @(posedge BIT_CLOCK_I or negedge AC97_RESETN_I)
    begin
    	if (AC97_RESETN_I == 1'b0) begin
			state <= 'd0;
			out_slt0 <= 0;
		end
    	else begin
  			if (AC97_SYNCH_buffer == 1'b0 && AC97_SYNCH == 1'b1) begin
				case (state)
		      'd0  : begin


			    	out_slt1 <= {1'b1, 19'h00000};		 
			    	out_slt2 <= 20'h00000;		 
					if (AC97_codec_ready) state <= 'd1;	
		      end
				'd1: begin

					out_slt0 <= {1'b1, 2'b11, 2'b00, 11'h0 };
			    	out_slt1 <= {reset_reg_set, 7'h00, 12'h000};		 
			    	out_slt2 <= 20'h00000;

					state <= 'd2;	 
				end
				'd2: begin

					out_slt0 <= {1'b1, 2'b11, 2'b00, 11'h0 };
			    	out_slt1 <= {line_out_set, 7'h02, 12'h000};		 
			    	out_slt2 <= {line_out_mute, 2'b00, line_out_left, 3'b000, line_out_right, 4'h0};		
	
					state <= 'd3;	 
				end
				'd3: begin

					out_slt0 <= {1'b1, 2'b11, 2'b00, 11'h0 };
			    	out_slt1 <= {level_out_set, 7'h04, 12'h000};		 
			    	out_slt2 <= {level_mute, 2'b00, level_left, 3'b000, level_right, 4'h0};		

					state <= 'd4;	 
				end
				'd4: begin

					out_slt0 <= {1'b1, 2'b11, 2'b00, 11'h0 };
			    	out_slt1 <= {mono_out_set, 7'h06, 12'h000};		 
			    	out_slt2 <= {level_mute, 2'b00, 4'h0, 3'b000, mono_right, 4'h0};		

					state <= 'd5;	 
				end
				'd5: begin

					out_slt0 <= {1'b1, 2'b11, 2'b00, 11'h0 };
			    	out_slt1 <= {pc_beep_set, 7'h0a, 12'h000};		 
			    	out_slt2 <= 20'h00000;

					state <= 'd6;	 
				end
				'd6: begin

					out_slt0 <= {1'b1, 2'b11, 2'b00, 11'h0 };
			    	out_slt1 <= {phone_volume_set, 7'h0c, 12'h000};		 
			    	out_slt2 <= {phone_mute, 12'h000, phone_volume, 4'h0};		

					state <= 'd7;	 
				end
				'd7: begin

					out_slt0 <= {1'b1, 2'b11, 2'b00, 11'h0 };
			    	out_slt1 <= {mic_volume_set, 7'h0e, 12'h000};		 
			    	out_slt2 <= {mic_mute, 12'h000, mic_volume, 4'h0};		

					state <= 'd8;	 
				end
				'd8: begin

					out_slt0 <= {1'b1, 2'b11, 2'b00, 11'h0 };

			    	out_slt1 <= {line_in_set, 7'h10, 12'h000};		 
			    	out_slt2 <= {line_in_mute, 2'b00, line_in_left, 3'h0, line_in_right, 4'h0};		

					state <= 'd9;	 
				end
				'd9: begin

					out_slt0 <= {1'b1, 2'b11, 2'b00, 11'h0 };
					out_slt1 <= {PCM_set, 7'h18, 12'h000};		 
			    	out_slt2 <= {PCM_mute, 2'b00, PCM_left, 3'h0, PCM_right, 4'h0};		

					state <= 'd10;	 
				end
				'd10: begin

					out_slt0 <= {1'b1, 2'b11, 2'b00, 11'h0 };
					out_slt1 <= {record_select_set, 7'h1a, 12'h000};		 
			    	out_slt2 <= {5'h00, record_select_left, 5'h00, record_select_right, 4'h0};		

					state <= 'd11;	 
				end
				'd11: begin

					out_slt0 <= {1'b1, 2'b11, 2'b00, 11'h0 };
					out_slt1 <= {record_gain_set, 7'h1c, 12'h000};		 
			    	out_slt2 <= {record_gain_mute, 3'b00, record_gain_left, 4'h0, record_gain_right, 4'h0};		
					
					state <= 'd12;	 
				end
				'd12: begin

					out_slt0 <= {1'b1, 2'b11, 2'b00, 11'h0 };
					out_slt1 <= {gp_set, 7'h20, 12'h000};		 
			    	out_slt2 <= {gp_pop, 1'b0, gp_3d, 3'h0, gp_mix, gp_ms, gp_LPBK, 11'h000};
					
					state <= 'd13;	 
				end
				'd13: begin

					out_slt0 <= {1'b1, 2'b11, 2'b00, 11'h0 };
					out_slt1 <= {1'd1, 7'h26, 12'h000};		 
			    	out_slt2 <= 20'h00000;
						 					
					state <= 'd14;	 
				end
				'd14: begin

					out_slt0 <= {1'b1, 2'b11, 2'b00, 11'h0 };
					out_slt1 <= {extended_audio_set, 7'h2a, 12'h000};		 
			    	out_slt2 <= {15'h0, variable_frequency};
					
					state <= 'd15;	 
				end
				'd15: begin

					out_slt0 <= {1'b1, 2'b11, 2'b11, 11'h0 };
					out_slt1 <= {sample_set, 7'h2c, 12'h000};		 
			    	out_slt2 <= {4'h0, cur_sample_frequency};
					
					if (pause_cnt == 0) state <= 'd16;
				end

				'd16: begin

					out_slt0 <= {1'b1, 2'b11, 2'b11, 11'h0 };
					out_slt1 <= {sample_set, 7'h32, 12'h000};		 
		    		out_slt2 <= {4'h0, cur_sample_frequency};

					if (pause_cnt == 0) state <= 'd15;	 
				end
				endcase
			end
		end
    end

	 always @(posedge BIT_CLOCK_I or negedge AC97_RESETN_I)
    begin
    	if (AC97_RESETN_I == 1'b0) begin
			out_slt3 <= 0;
			out_slt4 <= 0;
		end
    	else begin
  			if (AC97_SYNCH_buffer == 1'b1 && AC97_SYNCH == 1'b0) begin
				if (state < 'd15) begin
					out_slt3 <= 0;
					out_slt4 <= 0;
				end else begin

					if (SOURCE_SELECT_I == 1'b1) begin
						out_slt3 <= {CH0_PCM_DATA_I, 4'h0};
						out_slt4 <= {CH1_PCM_DATA_I, 4'h0};
					end
					else begin
						out_slt3 <= in_slt3;
						out_slt4 <= in_slt4;
					end			
				end
			end
		end
	end


	always @(posedge BIT_CLOCK_I or negedge AC97_RESETN_I)
   begin
    	if (AC97_RESETN_I == 1'b0) begin

			sample_counter <= 10'd0;
		end else begin
				if (state >= 'd15) begin
					if (AC97_SYNCH_buffer == 1'b0 && AC97_SYNCH == 1'b1) 
						if (PCM_READ_ADVANCE_EN_I)
							sample_counter <= sample_counter + 10'd1;
				end

		end
	end

	assign PCM_READ_ADDRESS_O = sample_counter;

    ac97_sout u0(
		.clk(BIT_CLOCK_I),
		.so_ld(ld),
		.slt0(out_slt0),
		.slt1(out_slt1),
		.slt2(out_slt2),
		.slt3(out_slt3),
		.slt4(out_slt4),
		.sdata_out(AC97_DATA_OUT)
		);

    ac97_sin u1(
		.clk(BIT_CLOCK_I),
		.out_le(out_le),
		.slt0(in_slt0),
		.slt1(in_slt1),
		.slt2(in_slt2),
		.slt3(in_slt3),
		.slt4(in_slt4),
		.sdata_in(AC97_DATA_IN_I)
		);

    ac97_soc u2(
    	.clk(BIT_CLOCK_I),
		.rst(AC97_RESETN_I),
		.sample_frequency(cur_sample_frequency),
		.sync(AC97_SYNCH),
		.out_le(out_le),
		.ld(ld),
		.pause_cnt(pause_cnt)
		);

   assign AC97_DATA_OUT_O = AC97_codec_ready && AC97_DATA_OUT;
   assign AC97_SYNCH_O = AC97_SYNCH;

endmodule