data/full_repos/permissive/515613199/odd.v
1: b'%Error: data/full_repos/permissive/515613199/odd.v:1: Cannot find include file: reg_size.v\n`include "reg_size.v" \n         ^~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/515613199,data/full_repos/permissive/515613199/reg_size.v\n             data/full_repos/permissive/515613199,data/full_repos/permissive/515613199/reg_size.v.v\n             data/full_repos/permissive/515613199,data/full_repos/permissive/515613199/reg_size.v.sv\n             reg_size.v\n             reg_size.v.v\n             reg_size.v.sv\n             obj_dir/reg_size.v\n             obj_dir/reg_size.v.v\n             obj_dir/reg_size.v.sv\n%Error: data/full_repos/permissive/515613199/odd.v:5: Define or directive not defined: \'`SIZE\'\n input [`SIZE-1:0] N,   \n        ^~~~~\n%Error: data/full_repos/permissive/515613199/odd.v:11: Define or directive not defined: \'`SIZE\'\n    wire[`SIZE-2:0] ton;\n         ^~~~~\n%Error: data/full_repos/permissive/515613199/odd.v:12: Define or directive not defined: \'`SIZE\'\n    wire[`SIZE-2:0] toff;\n         ^~~~~\n%Error: data/full_repos/permissive/515613199/odd.v:13: Define or directive not defined: \'`SIZE\'\n reg [`SIZE-2:0] counter;  \n      ^~~~~\n%Error: data/full_repos/permissive/515613199/odd.v:20: Define or directive not defined: \'`SIZE\'\n assign ton  = N[`SIZE-1:1];  \n                 ^~~~~\n%Error: Exiting due to 6 error(s)\n'
module odd_divider(
    input clk,
	input [`SIZE-1:0] N,
	input reset,
	input enable,
    output out
    );
	
    wire[`SIZE-2:0] ton;
    wire[`SIZE-2:0] toff;
	reg [`SIZE-2:0] counter;	 
	reg posedge_count;
	reg negedge_count;
    reg round_robin_counter;

	assign out = (enable) ? (posedge_count | negedge_count) : 1'hz;

	assign ton  = N[`SIZE-1:1];
	assign toff = ton+1'b1;
    

	always @(posedge reset or posedge clk)
	begin
		if(reset)
		begin
			counter				<= 1;
            round_robin_counter <= 1'b0;
			posedge_count       <= 1'b0;
		end
		else if(enable)
		begin
			if(counter == 1)
			begin
				counter 			 <= (round_robin_counter)? toff: ton;
				round_robin_counter  <= ~round_robin_counter;
				posedge_count 	 	 <= ~posedge_count;
			end
            else
                counter <= counter-1;
		end
	end


	always @(negedge clk or posedge reset)
	begin
		if(reset)
		begin										
			negedge_count <= 0;
		end
		else if(enable)
		begin
			negedge_count <= posedge_count;
		end
	end

endmodule
module odd_divider(
    input clk,
	input [`SIZE-1:0] N,
	input reset,
	input enable,
    output out
    );

	
    wire[`SIZE-2:0] ton;
    wire[`SIZE-2:0] toff;
	reg [`SIZE-2:0] counter;	 
	reg posedge_count;
	reg negedge_count;
    reg round_robin_counter;

	assign out = (enable) ? (posedge_count | negedge_count) : 1'hz;

	assign ton  = N[`SIZE-1:1];
	assign toff = ton+1'b1;
    

	always @(posedge reset or posedge clk)
	begin
		if(reset)
		begin
			counter				<= 1;
            round_robin_counter <= 1'b0;
			posedge_count       <= 1'b0;
		end
		else if(enable)
		begin
			if(counter == 1)
			begin
				counter 			 <= (round_robin_counter)? toff: ton;
				round_robin_counter  <= ~round_robin_counter;
				posedge_count 	 	 <= ~posedge_count;
			end
            else
                counter <= counter-1;
		end
	end


	always @(negedge clk or posedge reset)
	begin
		if(reset)
		begin										
			negedge_count <= 0;
		end
		else if(enable)
		begin
			negedge_count <= posedge_count;
		end
	end

endmodule