data/full_repos/permissive/497819211/01/Mux_tb.v
1: b'%Error: data/full_repos/permissive/497819211/01/Mux_tb.v:1: Cannot find include file: Mux.v\n`include "Mux.v" \n         ^~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/497819211/01,data/full_repos/permissive/497819211/Mux.v\n             data/full_repos/permissive/497819211/01,data/full_repos/permissive/497819211/Mux.v.v\n             data/full_repos/permissive/497819211/01,data/full_repos/permissive/497819211/Mux.v.sv\n             Mux.v\n             Mux.v.v\n             Mux.v.sv\n             obj_dir/Mux.v\n             obj_dir/Mux.v.v\n             obj_dir/Mux.v.sv\n%Warning-STMTDLY: data/full_repos/permissive/497819211/01/Mux_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n     #1 $fwrite(file, "|%1b|%1b|%1b|%1b|\\n", a,b,sel,out);\n     ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/497819211/01/Mux_tb.v:24: Unsupported or unknown PLI call: $dumpfile\n    $dumpfile("Mux_tb.vcd");\n    ^~~~~~~~~\n%Error: data/full_repos/permissive/497819211/01/Mux_tb.v:25: Unsupported or unknown PLI call: $dumpvars\n    $dumpvars(0, Mux_tb);\n    ^~~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n'
module Mux_tb();

	integer file;

	reg a = 0;
	reg b = 0;
	reg sel = 0;
	wire out;
	
	Mux MUX(
	    .a(a),
		.b(b),
		.sel(sel),
	    .out(out)
	  );

	task display;
    	#1 $fwrite(file, "|%1b|%1b|%1b|%1b|\n", a,b,sel,out);
  	endtask
  	
  	initial begin
  		$dumpfile("Mux_tb.vcd");
  		$dumpvars(0, Mux_tb);
		file = $fopen("Mux.out","w");
    	$fwrite(file, "|a|b|sel|out|\n");
		
		a=0;b=0;sel=0;
		display();

        a=0;b=0;sel=1;
		display();
  		
		a=0;b=1;sel=0;
		display();

        a=0;b=1;sel=1;
		display();
		
		a=1;b=0;sel=0;
		display();

        a=1;b=0;sel=1;
		display();
		
		a=1;b=1;sel=0;
		display();

        a=1;b=1;sel=1;
		display();
		$finish();	
	end

endmodule
module Mux_tb();


	integer file;

	reg a = 0;
	reg b = 0;
	reg sel = 0;
	wire out;
	
	Mux MUX(
	    .a(a),
		.b(b),
		.sel(sel),
	    .out(out)
	  );

	task display;
    	#1 $fwrite(file, "|%1b|%1b|%1b|%1b|\n", a,b,sel,out);
  	endtask
  	
  	initial begin
  		$dumpfile("Mux_tb.vcd");
  		$dumpvars(0, Mux_tb);
		file = $fopen("Mux.out","w");
    	$fwrite(file, "|a|b|sel|out|\n");
		
		a=0;b=0;sel=0;
		display();

        a=0;b=0;sel=1;
		display();
  		
		a=0;b=1;sel=0;
		display();

        a=0;b=1;sel=1;
		display();
		
		a=1;b=0;sel=0;
		display();

        a=1;b=0;sel=1;
		display();
		
		a=1;b=1;sel=0;
		display();

        a=1;b=1;sel=1;
		display();
		$finish();	
	end

endmodule