data/full_repos/permissive/434840709/USTB_digital_logic_homework/task4/clkDiv.v
data/verilator_xmls/e0557cde-0532-406f-8988-2edc10d43739.xml
module clkDiv(
input clk100mhz,
output clk190hz,
output clk3hz
    );
    reg[25:0] count=0;
    assign clk190hz = count[18];
    assign clk3hz = count[25];
    always@(posedge clk100mhz)
        count<=count+1;
endmodule
module clkDiv(
input clk100mhz,
output clk190hz,
output clk3hz
    );

    reg[25:0] count=0;
    assign clk190hz = count[18];
    assign clk3hz = count[25];
    always@(posedge clk100mhz)
        count<=count+1;
endmodule