data/full_repos/permissive/472469504/src/RISC_V_Single_Cycle_TB.v
1: b'%Warning-STMTDLY: data/full_repos/permissive/472469504/src/RISC_V_Single_Cycle_TB.v:30: Unsupported: Ignoring delay on this delayed statement.\n    forever #2 clk_tb = !clk_tb;\n            ^\n                  ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/472469504/src/RISC_V_Single_Cycle_TB.v:34: Unsupported: Ignoring delay on this delayed statement.\n #5 reset_tb = 1;\n ^\n%Error: data/full_repos/permissive/472469504/src/RISC_V_Single_Cycle_TB.v:20: Cannot find file containing module: \'RISC_V_Single_Cycle\'\nRISC_V_Single_Cycle\n^~~~~~~~~~~~~~~~~~~\n        ... Looked in:\n             data/full_repos/permissive/472469504/src,data/full_repos/permissive/472469504/RISC_V_Single_Cycle\n             data/full_repos/permissive/472469504/src,data/full_repos/permissive/472469504/RISC_V_Single_Cycle.v\n             data/full_repos/permissive/472469504/src,data/full_repos/permissive/472469504/RISC_V_Single_Cycle.sv\n             RISC_V_Single_Cycle\n             RISC_V_Single_Cycle.v\n             RISC_V_Single_Cycle.sv\n             obj_dir/RISC_V_Single_Cycle\n             obj_dir/RISC_V_Single_Cycle.v\n             obj_dir/RISC_V_Single_Cycle.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n        ... See the manual and https://verilator.org for more assistance.\n'
module RISC_V_Single_Cycle_TB;
reg clk_tb = 0;
reg reset_tb = 0;  
  
  
RISC_V_Single_Cycle
DUV
(
	.clk(clk_tb),
	.reset(reset_tb)

);

initial
  begin
    forever #2 clk_tb = !clk_tb;
  end

initial begin
	#5 reset_tb = 1;
end




endmodule
module RISC_V_Single_Cycle_TB;

reg clk_tb = 0;
reg reset_tb = 0;  
  
  
RISC_V_Single_Cycle
DUV
(
	.clk(clk_tb),
	.reset(reset_tb)

);

initial
  begin
    forever #2 clk_tb = !clk_tb;
  end

initial begin
	#5 reset_tb = 1;
end




endmodule